diff --git a/Workspace/.metadata/.log b/Workspace/.metadata/.log
new file mode 100644
index 0000000..9c780dc
--- /dev/null
+++ b/Workspace/.metadata/.log
@@ -0,0 +1,4286 @@
+!SESSION 2014-11-29 23:35:14.649 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-11-29 23:35:53.423
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-11-29 23:35:55.603
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-11-29 23:35:55.606
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-11-29 23:35:56.593
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-11-29 23:36:42.947
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 4 0 2014-11-29 23:38:54.159
+!MESSAGE Processor Expert project not opened.
+
+!ENTRY org.eclipse.cdt.core 1 0 2014-11-29 23:39:22.942
+!MESSAGE Indexed 'Project5' (3 sources, 88 headers) in 21.39 sec: 12,416 declarations; 6,686 references; 6 unresolved inclusions; 64 syntax errors; 5,560 unresolved names (22.54%)
+!SESSION 2014-11-29 23:46:02.380 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY org.eclipse.core.resources 2 10035 2014-11-29 23:46:09.927
+!MESSAGE The workspace exited with unsaved changes in the previous session; refreshing workspace to recover changes.
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-11-29 23:46:21.579
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-11-29 23:46:23.225
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-11-29 23:46:23.228
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-11-29 23:46:24.671
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.core.resources 4 4 2014-11-29 23:48:39.359
+!MESSAGE Exception occurred while saving project preferences: /ksdk_platform_lib_K64F12/.settings/com.processorexpert.core.ide.newprojectwizard.prefs.
+!STACK 1
+org.eclipse.core.internal.resources.ResourceException: A resource already exists on disk 'C:\Freescale\KSDK_1.0.0\lib\ksdk_platform_lib\kds\K64F12\.settings'.
+	at org.eclipse.core.internal.resources.Folder.assertCreateRequirements(Folder.java:47)
+	at org.eclipse.core.internal.resources.Folder.create(Folder.java:95)
+	at org.eclipse.core.internal.resources.ProjectPreferences$1.run(ProjectPreferences.java:571)
+	at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2345)
+	at org.eclipse.core.internal.resources.ProjectPreferences.save(ProjectPreferences.java:597)
+	at org.eclipse.core.internal.preferences.EclipsePreferences.internalFlush(EclipsePreferences.java:471)
+	at org.eclipse.core.internal.resources.ProjectPreferences.flush(ProjectPreferences.java:350)
+	at org.eclipse.core.internal.resources.ProjectPreferences.flush(ProjectPreferences.java:353)
+	at com.processorexpert.core.ide.newprojectwizard.CCProjectNatureManager.correctProjectNature(CCProjectNatureManager.java:66)
+	at com.processorexpert.core.ide.newprojectwizard.StartupHandler$1.runInUIThread(StartupHandler.java:45)
+	at org.eclipse.ui.progress.UIJob$1.run(UIJob.java:95)
+	at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:35)
+	at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:135)
+	at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4145)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3762)
+	at org.eclipse.jface.operation.ModalContext$ModalContextThread.block(ModalContext.java:173)
+	at org.eclipse.jface.operation.ModalContext.run(ModalContext.java:388)
+	at org.eclipse.jface.wizard.WizardDialog.run(WizardDialog.java:1028)
+	at org.eclipse.ui.internal.wizards.datatransfer.WizardProjectsImportPage.createProjects(WizardProjectsImportPage.java:1286)
+	at org.eclipse.ui.wizards.datatransfer.ExternalProjectImportWizard.performFinish(ExternalProjectImportWizard.java:113)
+	at org.eclipse.jface.wizard.WizardDialog.finishPressed(WizardDialog.java:827)
+	at org.eclipse.jface.wizard.WizardDialog.buttonPressed(WizardDialog.java:432)
+	at org.eclipse.jface.dialogs.Dialog$2.widgetSelected(Dialog.java:628)
+	at org.eclipse.swt.widgets.TypedListener.handleEvent(TypedListener.java:248)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1057)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4170)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3759)
+	at org.eclipse.jface.window.Window.runEventLoop(Window.java:826)
+	at org.eclipse.jface.window.Window.open(Window.java:802)
+	at org.eclipse.ui.internal.handlers.WizardHandler$Import.executeHandler(WizardHandler.java:152)
+	at org.eclipse.ui.internal.handlers.WizardHandler.execute(WizardHandler.java:279)
+	at org.eclipse.ui.internal.handlers.HandlerProxy.execute(HandlerProxy.java:290)
+	at org.eclipse.ui.internal.handlers.E4HandlerProxy.execute(E4HandlerProxy.java:90)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:56)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:243)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:224)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:132)
+	at org.eclipse.e4.core.commands.internal.HandlerServiceHandler.execute(HandlerServiceHandler.java:167)
+	at org.eclipse.core.commands.Command.executeWithChecks(Command.java:499)
+	at org.eclipse.core.commands.ParameterizedCommand.executeWithChecks(ParameterizedCommand.java:508)
+	at org.eclipse.e4.core.commands.internal.HandlerServiceImpl.executeHandler(HandlerServiceImpl.java:213)
+	at org.eclipse.ui.internal.handlers.LegacyHandlerService.executeCommand(LegacyHandlerService.java:420)
+	at org.eclipse.ui.internal.actions.CommandAction.runWithEvent(CommandAction.java:157)
+	at org.eclipse.jface.action.ActionContributionItem.handleWidgetSelection(ActionContributionItem.java:584)
+	at org.eclipse.jface.action.ActionContributionItem.access$2(ActionContributionItem.java:501)
+	at org.eclipse.jface.action.ActionContributionItem$5.handleEvent(ActionContributionItem.java:411)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1057)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4170)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3759)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1113)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:997)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:140)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:611)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:567)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:124)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:110)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:79)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:354)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:181)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:636)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:591)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1450)
+!SUBENTRY 1 org.eclipse.core.resources 4 272 2014-11-29 23:48:39.375
+!MESSAGE A resource already exists on disk 'C:\Freescale\KSDK_1.0.0\lib\ksdk_platform_lib\kds\K64F12\.settings'.
+
+!ENTRY com.processorexpert.core.ide.newprojectwizard 4 0 2014-11-29 23:48:39.375
+!MESSAGE Exception occurred while saving project preferences: /ksdk_platform_lib_K64F12/.settings/com.processorexpert.core.ide.newprojectwizard.prefs.
+!STACK 0
+org.osgi.service.prefs.BackingStoreException: Exception occurred while saving project preferences: /ksdk_platform_lib_K64F12/.settings/com.processorexpert.core.ide.newprojectwizard.prefs.
+	at org.eclipse.core.internal.resources.ProjectPreferences.save(ProjectPreferences.java:607)
+	at org.eclipse.core.internal.preferences.EclipsePreferences.internalFlush(EclipsePreferences.java:471)
+	at org.eclipse.core.internal.resources.ProjectPreferences.flush(ProjectPreferences.java:350)
+	at org.eclipse.core.internal.resources.ProjectPreferences.flush(ProjectPreferences.java:353)
+	at com.processorexpert.core.ide.newprojectwizard.CCProjectNatureManager.correctProjectNature(CCProjectNatureManager.java:66)
+	at com.processorexpert.core.ide.newprojectwizard.StartupHandler$1.runInUIThread(StartupHandler.java:45)
+	at org.eclipse.ui.progress.UIJob$1.run(UIJob.java:95)
+	at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:35)
+	at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:135)
+	at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4145)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3762)
+	at org.eclipse.jface.operation.ModalContext$ModalContextThread.block(ModalContext.java:173)
+	at org.eclipse.jface.operation.ModalContext.run(ModalContext.java:388)
+	at org.eclipse.jface.wizard.WizardDialog.run(WizardDialog.java:1028)
+	at org.eclipse.ui.internal.wizards.datatransfer.WizardProjectsImportPage.createProjects(WizardProjectsImportPage.java:1286)
+	at org.eclipse.ui.wizards.datatransfer.ExternalProjectImportWizard.performFinish(ExternalProjectImportWizard.java:113)
+	at org.eclipse.jface.wizard.WizardDialog.finishPressed(WizardDialog.java:827)
+	at org.eclipse.jface.wizard.WizardDialog.buttonPressed(WizardDialog.java:432)
+	at org.eclipse.jface.dialogs.Dialog$2.widgetSelected(Dialog.java:628)
+	at org.eclipse.swt.widgets.TypedListener.handleEvent(TypedListener.java:248)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1057)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4170)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3759)
+	at org.eclipse.jface.window.Window.runEventLoop(Window.java:826)
+	at org.eclipse.jface.window.Window.open(Window.java:802)
+	at org.eclipse.ui.internal.handlers.WizardHandler$Import.executeHandler(WizardHandler.java:152)
+	at org.eclipse.ui.internal.handlers.WizardHandler.execute(WizardHandler.java:279)
+	at org.eclipse.ui.internal.handlers.HandlerProxy.execute(HandlerProxy.java:290)
+	at org.eclipse.ui.internal.handlers.E4HandlerProxy.execute(E4HandlerProxy.java:90)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:56)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:243)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:224)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:132)
+	at org.eclipse.e4.core.commands.internal.HandlerServiceHandler.execute(HandlerServiceHandler.java:167)
+	at org.eclipse.core.commands.Command.executeWithChecks(Command.java:499)
+	at org.eclipse.core.commands.ParameterizedCommand.executeWithChecks(ParameterizedCommand.java:508)
+	at org.eclipse.e4.core.commands.internal.HandlerServiceImpl.executeHandler(HandlerServiceImpl.java:213)
+	at org.eclipse.ui.internal.handlers.LegacyHandlerService.executeCommand(LegacyHandlerService.java:420)
+	at org.eclipse.ui.internal.actions.CommandAction.runWithEvent(CommandAction.java:157)
+	at org.eclipse.jface.action.ActionContributionItem.handleWidgetSelection(ActionContributionItem.java:584)
+	at org.eclipse.jface.action.ActionContributionItem.access$2(ActionContributionItem.java:501)
+	at org.eclipse.jface.action.ActionContributionItem$5.handleEvent(ActionContributionItem.java:411)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1057)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4170)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3759)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1113)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:997)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:140)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:611)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:567)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:124)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:110)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:79)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:354)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:181)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:636)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:591)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1450)
+
+!ENTRY org.eclipse.cdt.core 1 0 2014-11-29 23:49:36.497
+!MESSAGE Indexed 'ksdk_platform_lib_K64F12' (81 sources, 196 headers) in 48.98 sec: 22,513 declarations; 70,707 references; 0 unresolved inclusions; 0 syntax errors; 0 unresolved names (0.00%)
+
+!ENTRY org.eclipse.core.resources 4 2 2014-11-29 23:53:03.286
+!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.core.resources".
+!STACK 0
+java.lang.NullPointerException
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:379)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.resourceChanged(SystemTempFileListener.java:218)
+	at org.eclipse.core.internal.events.NotificationManager$1.run(NotificationManager.java:291)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.core.internal.events.NotificationManager.notify(NotificationManager.java:285)
+	at org.eclipse.core.internal.events.NotificationManager.broadcastChanges(NotificationManager.java:149)
+	at org.eclipse.core.internal.resources.Workspace.broadcastPostChange(Workspace.java:396)
+	at org.eclipse.core.internal.resources.Workspace.endOperation(Workspace.java:1531)
+	at org.eclipse.core.internal.resources.InternalWorkspaceJob.run(InternalWorkspaceJob.java:45)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:53)
+
+!ENTRY org.eclipse.core.resources 4 2 2014-11-29 23:53:03.302
+!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.core.resources".
+!STACK 0
+java.lang.NullPointerException
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:379)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.resourceChanged(SystemTempFileListener.java:218)
+	at org.eclipse.core.internal.events.NotificationManager$1.run(NotificationManager.java:291)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.core.internal.events.NotificationManager.notify(NotificationManager.java:285)
+	at org.eclipse.core.internal.events.NotificationManager.broadcastChanges(NotificationManager.java:149)
+	at org.eclipse.core.internal.resources.Workspace.broadcastPostChange(Workspace.java:396)
+	at org.eclipse.core.internal.resources.Workspace.endOperation(Workspace.java:1531)
+	at org.eclipse.core.internal.resources.InternalWorkspaceJob.run(InternalWorkspaceJob.java:45)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:53)
+
+!ENTRY org.eclipse.jface 2 0 2014-11-30 00:03:55.399
+!MESSAGE Keybinding conflicts occurred.  They may interfere with normal accelerator operation.
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:03:55.399
+!MESSAGE A conflict occurred for ALT+CTRL+I:
+Binding(ALT+CTRL+I,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser,
+		Open an include browser on the selected element,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@71e0ea,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(ALT+CTRL+I,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser,
+		Open an include browser on the selected element,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@71e0ea,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:03:55.399
+!MESSAGE A conflict occurred for ALT+SHIFT+R:
+Binding(ALT+SHIFT+R,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring ,
+		Rename the selected element,
+		Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@653036,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(ALT+SHIFT+R,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring ,
+		Rename the selected element,
+		Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@653036,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:03:55.399
+!MESSAGE A conflict occurred for F3:
+Binding(F3,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration,
+		Open an editor on the selected element's declaration(s),
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1403ef8,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(F3,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration,
+		Open an editor on the selected element's declaration(s),
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1403ef8,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:03:55.399
+!MESSAGE A conflict occurred for CTRL+SHIFT+T:
+Binding(CTRL+SHIFT+T,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element,
+		Open an element in an Editor,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@e6398f,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(CTRL+SHIFT+T,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element,
+		Open an element in an Editor,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@e6398f,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:03:55.399
+!MESSAGE A conflict occurred for F4:
+Binding(F4,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy,
+		Open a type hierarchy on the selected element,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ccdfd9,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(F4,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy,
+		Open a type hierarchy on the selected element,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ccdfd9,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:03:55.399
+!MESSAGE A conflict occurred for CTRL+G:
+Binding(CTRL+G,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration,
+		Search for declarations of the selected element in the workspace,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@7c41d2,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(CTRL+G,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration,
+		Search for declarations of the selected element in the workspace,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@7c41d2,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:03:55.399
+!MESSAGE A conflict occurred for CTRL+SHIFT+G:
+Binding(CTRL+SHIFT+G,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References,
+		Search for references to the selected element in the workspace,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1c54e8d,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(CTRL+SHIFT+G,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References,
+		Search for references to the selected element in the workspace,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1c54e8d,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:03:55.399
+!MESSAGE A conflict occurred for ALT+CTRL+H:
+Binding(ALT+CTRL+H,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy,
+		Open the call hierarchy for the selected element,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@a80df0,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(ALT+CTRL+H,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy,
+		Open the call hierarchy for the selected element,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@a80df0,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:03:55.399
+!MESSAGE A conflict occurred for CTRL+SHIFT+H:
+Binding(CTRL+SHIFT+H,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy,
+		Open a type in the type hierarchy view,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@12b3716,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(CTRL+SHIFT+H,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy,
+		Open a type in the type hierarchy view,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@12b3716,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+
+!ENTRY org.eclipse.jface 2 0 2014-11-30 00:14:21.569
+!MESSAGE Keybinding conflicts occurred.  They may interfere with normal accelerator operation.
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:14:21.569
+!MESSAGE A conflict occurred for ALT+ARROW_DOWN:
+Binding(ALT+ARROW_DOWN,
+	ParameterizedCommand(Command(org.eclipse.mylyn.tasks.ui.command.goToNextUnread,Go To Next Unread Task,
+		,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1323a9e,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.mylyn.tasks.ui.views.tasks,,,system)
+Binding(ALT+ARROW_DOWN,
+	ParameterizedCommand(Command(org.eclipse.ui.edit.text.moveLineDown,Move Lines Down,
+		Moves the selected lines down,
+		Category(org.eclipse.ui.category.textEditor,Text Editing,Text Editing Commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@23b959,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.ui.textEditorScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:14:21.569
+!MESSAGE A conflict occurred for ALT+SHIFT+ARROW_UP:
+Binding(ALT+SHIFT+ARROW_UP,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.c.select.enclosing,Select Enclosing C/C++ Element,
+		Expand the selection to enclosing C/C++ element,
+		Category(org.eclipse.ui.category.edit,Edit,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15da1ee,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(ALT+SHIFT+ARROW_UP,
+	ParameterizedCommand(Command(org.eclipse.mylyn.tasks.ui.command.markTaskReadGoToPreviousUnread,Mark Task Read and Go To Previous Unread Task,
+		,
+		Category(org.eclipse.mylyn.tasks.ui.commands,Task Repositories,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@321e4b,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.mylyn.tasks.ui.views.tasks,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:14:21.569
+!MESSAGE A conflict occurred for INSERT:
+Binding(INSERT,
+	ParameterizedCommand(Command(org.eclipse.mylyn.tasks.ui.command.new.local.task,New Local Task,
+		,
+		Category(org.eclipse.mylyn.tasks.ui.commands,Task Repositories,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@62de70,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.mylyn.tasks.ui.views.tasks,,,system)
+Binding(INSERT,
+	ParameterizedCommand(Command(org.eclipse.ui.edit.text.toggleOverwrite,Toggle Overwrite,
+		Toggle overwrite mode,
+		Category(org.eclipse.ui.category.textEditor,Text Editing,Text Editing Commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@f9a902,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.ui.textEditorScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:14:21.569
+!MESSAGE A conflict occurred for ALT+ARROW_UP:
+Binding(ALT+ARROW_UP,
+	ParameterizedCommand(Command(org.eclipse.mylyn.tasks.ui.command.goToPreviousUnread,Go To Previous Unread Task,
+		,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@b1831e,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.mylyn.tasks.ui.views.tasks,,,system)
+Binding(ALT+ARROW_UP,
+	ParameterizedCommand(Command(org.eclipse.ui.edit.text.moveLineUp,Move Lines Up,
+		Moves the selected lines up,
+		Category(org.eclipse.ui.category.textEditor,Text Editing,Text Editing Commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@c6db6c,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.ui.textEditorScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-11-30 00:14:21.569
+!MESSAGE A conflict occurred for ALT+SHIFT+ARROW_DOWN:
+Binding(ALT+SHIFT+ARROW_DOWN,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.c.select.last,Restore Last C/C++ Selection,
+		Restore last selection in C/C++ editor,
+		Category(org.eclipse.ui.category.edit,Edit,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@16fbbf6,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(ALT+SHIFT+ARROW_DOWN,
+	ParameterizedCommand(Command(org.eclipse.mylyn.tasks.ui.command.markTaskReadGoToNextUnread,Mark Task Read and Go To Next Unread Task,
+		,
+		Category(org.eclipse.mylyn.tasks.ui.commands,Task Repositories,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@9d2085,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.mylyn.tasks.ui.views.tasks,,,system)
+!SESSION 2014-12-04 00:38:29.837 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-12-04 00:39:26.135
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-12-04 00:39:34.338
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-04 00:40:46.218
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-04 00:40:46.218
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.ui 4 0 2014-12-04 00:41:50.995
+!MESSAGE Unhandled event loop exception
+!STACK 0
+org.eclipse.swt.SWTException: Failed to execute runnable (java.lang.NullPointerException)
+	at org.eclipse.swt.SWT.error(SWT.java:4397)
+	at org.eclipse.swt.SWT.error(SWT.java:4312)
+	at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:138)
+	at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4145)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3762)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1113)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:997)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:140)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:611)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:567)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:124)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:110)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:79)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:354)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:181)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:636)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:591)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1450)
+Caused by: java.lang.NullPointerException
+	at org.eclipse.debug.internal.ui.launchConfigurations.LaunchDelegateNotAvailableHandler$1.run(LaunchDelegateNotAvailableHandler.java:42)
+	at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:35)
+	at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:135)
+	... 23 more
+!SESSION 2014-12-04 00:52:06.184 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-12-04 00:52:31.590
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-12-04 00:52:35.262
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-04 00:53:20.469
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-04 00:53:20.469
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY com.pemicro.debug.gdbjtag.pne 4 5012 2014-12-04 00:54:29.400
+!MESSAGE Error in final launch sequence
+!STACK 1
+org.eclipse.core.runtime.CoreException: Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.concurrent.Query.get(Query.java:115)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugSession(LaunchConfigurationDelegate.java:282)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugger(LaunchConfigurationDelegate.java:86)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launch(LaunchConfigurationDelegate.java:73)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:858)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:707)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1018)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1222)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:53)
+Caused by: java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 10004 2014-12-04 00:54:29.400
+!MESSAGE Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+!STACK 0
+java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+
+!ENTRY com.pemicro.debug.gdbjtag.pne 4 5012 2014-12-04 00:54:58.822
+!MESSAGE Error in final launch sequence
+!STACK 1
+org.eclipse.core.runtime.CoreException: Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.concurrent.Query.get(Query.java:115)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugSession(LaunchConfigurationDelegate.java:282)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugger(LaunchConfigurationDelegate.java:86)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launch(LaunchConfigurationDelegate.java:73)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:858)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:707)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1018)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1222)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:53)
+Caused by: java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 10004 2014-12-04 00:54:58.822
+!MESSAGE Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+!STACK 0
+java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+
+!ENTRY com.pemicro.debug.gdbjtag.pne 4 5012 2014-12-04 00:56:14.276
+!MESSAGE Error in final launch sequence
+!STACK 1
+org.eclipse.core.runtime.CoreException: Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.concurrent.Query.get(Query.java:115)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugSession(LaunchConfigurationDelegate.java:282)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugger(LaunchConfigurationDelegate.java:86)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launch(LaunchConfigurationDelegate.java:73)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:858)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:707)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1018)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1222)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:53)
+Caused by: java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 10004 2014-12-04 00:56:14.276
+!MESSAGE Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+!STACK 0
+java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+!SESSION 2014-12-05 17:14:42.527 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-12-05 17:15:17.308
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-12-05 17:15:22.402
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-05 17:17:12.944
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-05 17:17:12.944
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY com.pemicro.debug.gdbjtag.pne 4 5012 2014-12-05 17:19:24.117
+!MESSAGE Error in final launch sequence
+!STACK 1
+org.eclipse.core.runtime.CoreException: Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.concurrent.Query.get(Query.java:115)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugSession(LaunchConfigurationDelegate.java:282)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugger(LaunchConfigurationDelegate.java:86)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launch(LaunchConfigurationDelegate.java:73)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:858)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:707)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1018)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1222)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:53)
+Caused by: java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 10004 2014-12-05 17:19:24.117
+!MESSAGE Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+!STACK 0
+java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+
+!ENTRY com.pemicro.debug.gdbjtag.pne 4 5012 2014-12-05 17:24:59.533
+!MESSAGE Error in final launch sequence
+!STACK 1
+org.eclipse.core.runtime.CoreException: Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.concurrent.Query.get(Query.java:115)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugSession(LaunchConfigurationDelegate.java:282)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugger(LaunchConfigurationDelegate.java:86)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launch(LaunchConfigurationDelegate.java:73)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:858)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:707)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1018)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1222)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:53)
+Caused by: java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 10004 2014-12-05 17:24:59.533
+!MESSAGE Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+!STACK 0
+java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+
+!ENTRY com.pemicro.debug.gdbjtag.pne 4 5012 2014-12-05 17:25:29.877
+!MESSAGE Error in final launch sequence
+!STACK 1
+org.eclipse.core.runtime.CoreException: Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.concurrent.Query.get(Query.java:115)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugSession(LaunchConfigurationDelegate.java:282)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugger(LaunchConfigurationDelegate.java:86)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launch(LaunchConfigurationDelegate.java:73)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:858)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:707)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1018)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1222)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:53)
+Caused by: java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 10004 2014-12-05 17:25:29.877
+!MESSAGE Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+!STACK 0
+java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+
+!ENTRY com.pemicro.debug.gdbjtag.pne 4 5012 2014-12-05 17:26:33.260
+!MESSAGE Error in final launch sequence
+!STACK 1
+org.eclipse.core.runtime.CoreException: Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.concurrent.Query.get(Query.java:115)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugSession(LaunchConfigurationDelegate.java:282)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugger(LaunchConfigurationDelegate.java:86)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launch(LaunchConfigurationDelegate.java:73)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:858)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:707)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1018)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1222)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:53)
+Caused by: java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 10004 2014-12-05 17:26:33.260
+!MESSAGE Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+!STACK 0
+java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+!SESSION 2014-12-05 17:27:49.011 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-12-05 17:28:15.996
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-12-05 17:28:20.949
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-05 17:29:48.967
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-05 17:29:48.967
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+!SESSION 2014-12-06 08:18:22.568 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY org.eclipse.core.resources 2 10035 2014-12-06 08:18:32.068
+!MESSAGE The workspace exited with unsaved changes in the previous session; refreshing workspace to recover changes.
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-12-06 08:18:58.679
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-12-06 08:19:05.554
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-06 08:21:04.380
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-06 08:21:04.380
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY com.pemicro.debug.gdbjtag.pne 4 5012 2014-12-06 08:54:32.846
+!MESSAGE Error in final launch sequence
+!STACK 1
+org.eclipse.core.runtime.CoreException: Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.concurrent.Query.get(Query.java:115)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugSession(LaunchConfigurationDelegate.java:282)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugger(LaunchConfigurationDelegate.java:86)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launch(LaunchConfigurationDelegate.java:73)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:858)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:707)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1018)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1222)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:53)
+Caused by: java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 10004 2014-12-06 08:54:32.862
+!MESSAGE Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+!STACK 0
+java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+
+!ENTRY org.eclipse.debug.core 4 125 2014-12-06 08:55:43.890
+!MESSAGE Error logged from Debug Core: 
+!STACK 0
+java.io.IOException: Pipe closed
+	at java.io.PipedInputStream.read(Unknown Source)
+	at java.io.PipedInputStream.read(Unknown Source)
+	at java.io.BufferedInputStream.read1(Unknown Source)
+	at java.io.BufferedInputStream.read(Unknown Source)
+	at java.io.FilterInputStream.read(Unknown Source)
+	at org.eclipse.debug.internal.core.OutputStreamMonitor.read(OutputStreamMonitor.java:145)
+	at org.eclipse.debug.internal.core.OutputStreamMonitor.access$1(OutputStreamMonitor.java:135)
+	at org.eclipse.debug.internal.core.OutputStreamMonitor$1.run(OutputStreamMonitor.java:208)
+	at java.lang.Thread.run(Unknown Source)
+
+!ENTRY com.pemicro.debug.gdbjtag.pne 4 5012 2014-12-06 08:55:43.984
+!MESSAGE Error in final launch sequence
+!STACK 1
+org.eclipse.core.runtime.CoreException: Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.concurrent.Query.get(Query.java:115)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugSession(LaunchConfigurationDelegate.java:282)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launchDebugger(LaunchConfigurationDelegate.java:86)
+	at com.pemicro.debug.gdbjtag.pne.LaunchConfigurationDelegate.launch(LaunchConfigurationDelegate.java:73)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:858)
+	at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:707)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1018)
+	at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1222)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:53)
+Caused by: java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 10004 2014-12-06 08:55:43.984
+!MESSAGE Failed to execute MI command:
+-target-select remote 127.0.0.1:7224
+
+Error message from debugger back end:
+Remote communication error.  Target disconnected.: No error.
+!STACK 0
+java.lang.Exception: Remote communication error.  Target disconnected.: No error.
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:925)
+	at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:754)
+
+!ENTRY org.eclipse.ui 4 0 2014-12-06 08:58:23.425
+!MESSAGE Unhandled event loop exception
+!STACK 0
+org.eclipse.swt.SWTException: Failed to execute runnable (java.lang.NullPointerException)
+	at org.eclipse.swt.SWT.error(SWT.java:4397)
+	at org.eclipse.swt.SWT.error(SWT.java:4312)
+	at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:138)
+	at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4145)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3762)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1113)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:997)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:140)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:611)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:567)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:124)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:110)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:79)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:354)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:181)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:636)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:591)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1450)
+Caused by: java.lang.NullPointerException
+	at org.eclipse.debug.internal.ui.launchConfigurations.LaunchDelegateNotAvailableHandler$1.run(LaunchDelegateNotAvailableHandler.java:42)
+	at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:35)
+	at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:135)
+	... 23 more
+!SESSION 2014-12-06 08:58:41.524 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-12-06 08:59:08.724
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-12-06 08:59:13.505
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-06 09:00:13.984
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-06 09:00:13.984
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.jface 2 0 2014-12-06 09:47:00.901
+!MESSAGE Keybinding conflicts occurred.  They may interfere with normal accelerator operation.
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-12-06 09:47:00.901
+!MESSAGE A conflict occurred for HOME:
+Binding(HOME,
+	ParameterizedCommand(Command(org.eclipse.cdt.dsf.debug.ui.disassembly.commands.gotoPC,Go to Program Counter,
+		Navigate to current program counter,
+		Category(org.eclipse.debug.ui.category.run,Run/Debug,Run/Debug command category,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3c3f2c,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.dsf.debug.ui.disassembly.context,,,system)
+Binding(HOME,
+	ParameterizedCommand(Command(org.eclipse.ui.edit.text.goto.lineStart,Line Start,
+		Go to the start of the line of text,
+		Category(org.eclipse.ui.category.textEditor,Text Editing,Text Editing Commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1577e8b,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.ui.textEditorScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-12-06 09:47:00.901
+!MESSAGE A conflict occurred for CTRL+G:
+Binding(CTRL+G,
+	ParameterizedCommand(Command(org.eclipse.cdt.dsf.debug.ui.disassembly.commands.gotoAddress,Go to Address...,
+		Navigate to address,
+		Category(org.eclipse.debug.ui.category.run,Run/Debug,Run/Debug command category,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@13516f0,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.dsf.debug.ui.disassembly.context,,,system)
+Binding(CTRL+G,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration,
+		Search for declarations of the selected element in the workspace,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@74fdbf,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+!SESSION 2014-12-06 09:58:37.344 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-12-06 09:59:05.503
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-12-06 09:59:09.925
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-06 10:00:40.357
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-06 10:00:40.357
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+!SESSION 2014-12-06 18:18:32.066 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-12-06 18:20:09.047
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-12-06 18:20:17.015
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-06 18:21:37.596
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-06 18:21:37.596
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+!SESSION 2014-12-06 18:26:08.880 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-12-06 18:26:37.520
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-12-06 18:26:41.317
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-06 18:27:15.997
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-06 18:27:15.997
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+!SESSION 2014-12-06 19:22:11.583 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-12-06 19:22:46.409
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-12-06 19:22:51.831
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-06 19:36:48.355
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-06 19:36:48.402
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+!SESSION 2014-12-29 22:10:21.205 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-12-29 22:11:11.158
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-12-29 22:11:15.236
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-29 22:11:27.948
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-29 22:11:27.948
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+!SESSION 2014-12-29 22:34:15.707 -----------------------------------------------
+eclipse.buildId=0.0.0.201408201009
+java.version=1.7.0_60
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.freescale.processorexpert.core 1 0 2014-12-29 22:35:15.460
+!MESSAGE Plugin com.freescale.processorexpert.core.service ProcessorExpertServiceProvider
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-29 22:35:18.772
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2014-12-29 22:35:18.772
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Mo'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2014-12-29 22:35:19.710
+!MESSAGE External elements location C:\Freescale\KDS_1.1.1\eclipse\ProcessorExpert/Config/PE/CPE/wizard_data/wizards/launch_config does not exist
+
+!ENTRY org.eclipse.jface 2 0 2014-12-29 22:43:27.453
+!MESSAGE Keybinding conflicts occurred.  They may interfere with normal accelerator operation.
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-12-29 22:43:27.453
+!MESSAGE A conflict occurred for ALT+CTRL+I:
+Binding(ALT+CTRL+I,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser,
+		Open an include browser on the selected element,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@5dd0d7,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(ALT+CTRL+I,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser,
+		Open an include browser on the selected element,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@5dd0d7,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-12-29 22:43:27.453
+!MESSAGE A conflict occurred for ALT+SHIFT+R:
+Binding(ALT+SHIFT+R,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring ,
+		Rename the selected element,
+		Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@139e3da,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(ALT+SHIFT+R,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring ,
+		Rename the selected element,
+		Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@139e3da,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-12-29 22:43:27.453
+!MESSAGE A conflict occurred for F3:
+Binding(F3,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration,
+		Open an editor on the selected element's declaration(s),
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@19e3642,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(F3,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration,
+		Open an editor on the selected element's declaration(s),
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@19e3642,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-12-29 22:43:27.453
+!MESSAGE A conflict occurred for CTRL+SHIFT+T:
+Binding(CTRL+SHIFT+T,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element,
+		Open an element in an Editor,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1fc48b5,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(CTRL+SHIFT+T,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element,
+		Open an element in an Editor,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1fc48b5,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-12-29 22:43:27.453
+!MESSAGE A conflict occurred for F4:
+Binding(F4,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy,
+		Open a type hierarchy on the selected element,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@9a1a4,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(F4,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy,
+		Open a type hierarchy on the selected element,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@9a1a4,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-12-29 22:43:27.453
+!MESSAGE A conflict occurred for CTRL+G:
+Binding(CTRL+G,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration,
+		Search for declarations of the selected element in the workspace,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@532771,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(CTRL+G,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration,
+		Search for declarations of the selected element in the workspace,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@532771,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-12-29 22:43:27.453
+!MESSAGE A conflict occurred for CTRL+SHIFT+G:
+Binding(CTRL+SHIFT+G,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References,
+		Search for references to the selected element in the workspace,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1427f5f,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(CTRL+SHIFT+G,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References,
+		Search for references to the selected element in the workspace,
+		Category(org.eclipse.cdt.ui.category.source,Source,Source commands,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1427f5f,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-12-29 22:43:27.453
+!MESSAGE A conflict occurred for ALT+CTRL+H:
+Binding(ALT+CTRL+H,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy,
+		Open the call hierarchy for the selected element,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@b844fa,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(ALT+CTRL+H,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy,
+		Open the call hierarchy for the selected element,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@b844fa,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+!SUBENTRY 1 org.eclipse.jface 2 0 2014-12-29 22:43:27.453
+!MESSAGE A conflict occurred for CTRL+SHIFT+H:
+Binding(CTRL+SHIFT+H,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy,
+		Open a type in the type hierarchy view,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1b8b701,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cEditorScope,,,system)
+Binding(CTRL+SHIFT+H,
+	ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy,
+		Open a type in the type hierarchy view,
+		Category(org.eclipse.ui.category.navigate,Navigate,null,true),
+		org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1b8b701,
+		,,true),null),
+	org.eclipse.ui.defaultAcceleratorConfiguration,
+	org.eclipse.cdt.ui.cViewScope,,,system)
+
+!ENTRY org.eclipse.cdt.dsf.ui 2 0 2014-12-29 22:49:17.253
+!MESSAGE Unable to locate file: ../FastMathFunctions/arm_cos_f32.c
+
+!ENTRY org.eclipse.ui 4 0 2014-12-29 22:49:56.518
+!MESSAGE Unhandled event loop exception
+!STACK 0
+org.eclipse.swt.SWTException: Failed to execute runnable (java.lang.NullPointerException)
+	at org.eclipse.swt.SWT.error(SWT.java:4397)
+	at org.eclipse.swt.SWT.error(SWT.java:4312)
+	at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:138)
+	at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4145)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3762)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1113)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:997)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:140)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:611)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:567)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:124)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:110)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:79)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:354)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:181)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:636)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:591)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1450)
+Caused by: java.lang.NullPointerException
+	at org.eclipse.debug.internal.ui.launchConfigurations.LaunchDelegateNotAvailableHandler$1.run(LaunchDelegateNotAvailableHandler.java:42)
+	at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:35)
+	at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:135)
+	... 23 more
+!SESSION 2016-02-23 15:40:41.671 -----------------------------------------------
+eclipse.buildId=3.1.0.201512141710
+java.version=1.7.0_76
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY org.eclipse.egit.ui 2 0 2016-02-23 15:40:53.362
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2016-02-23 15:40:53.366
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\sethg'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.cdt.core 1 0 2016-02-23 15:40:53.449
+!MESSAGE Indexed 'Project5' (3 sources, 58 headers) in 1.29 sec: 5,934 declarations; 7,041 references; 47 unresolved inclusions; 36 syntax errors; 681 unresolved names (5%)
+
+!ENTRY org.eclipse.e4.ui.workbench 4 0 2016-02-23 15:42:19.889
+!MESSAGE Error setting focus to : org.eclipse.e4.ui.model.application.ui.basic.impl.PartImpl core_cm4.h
+!STACK 0
+org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.swt.SWT.error(SWT.java:4441)
+	at org.eclipse.swt.SWT.error(SWT.java:4356)
+	at org.eclipse.swt.SWT.error(SWT.java:4327)
+	at org.eclipse.swt.widgets.Widget.error(Widget.java:476)
+	at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348)
+	at org.eclipse.swt.widgets.Control.setFocus(Control.java:3320)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.ui.texteditor.StatusTextEditor.setFocus(StatusTextEditor.java:120)
+	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.delegateSetFocus(CompatibilityPart.java:191)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:253)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:225)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.focusGui(PartRenderingEngine.java:795)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer$2.setFocus(ContributedPartRenderer.java:100)
+	at org.eclipse.swt.custom.CTabItem.setFocus(CTabItem.java:332)
+	at org.eclipse.swt.custom.CTabFolder.setFocus(CTabFolder.java:2555)
+	at org.eclipse.swt.widgets.Control.fixFocus(Control.java:1052)
+	at org.eclipse.swt.widgets.Control.setVisible(Control.java:3818)
+	at org.eclipse.swt.custom.CTabFolder.setItemSize(CTabFolder.java:2724)
+	at org.eclipse.swt.custom.CTabFolder.updateItems(CTabFolder.java:3703)
+	at org.eclipse.swt.custom.CTabFolder.updateItems(CTabFolder.java:3640)
+	at org.eclipse.swt.custom.CTabFolder.onResize(CTabFolder.java:2034)
+	at org.eclipse.swt.custom.CTabFolder$1.handleEvent(CTabFolder.java:290)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1085)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1066)
+	at org.eclipse.swt.widgets.Control.WM_SIZE(Control.java:5257)
+	at org.eclipse.swt.widgets.Scrollable.WM_SIZE(Scrollable.java:316)
+	at org.eclipse.swt.widgets.Composite.WM_SIZE(Composite.java:1690)
+	at org.eclipse.swt.widgets.Control.windowProc(Control.java:4685)
+	at org.eclipse.swt.widgets.Display.windowProc(Display.java:5023)
+	at org.eclipse.swt.internal.win32.OS.DefWindowProcW(Native Method)
+	at org.eclipse.swt.internal.win32.OS.DefWindowProc(OS.java:2544)
+	at org.eclipse.swt.widgets.Scrollable.callWindowProc(Scrollable.java:79)
+	at org.eclipse.swt.widgets.Control.WM_WINDOWPOSCHANGED(Control.java:5492)
+	at org.eclipse.swt.widgets.Control.windowProc(Control.java:4698)
+	at org.eclipse.swt.widgets.Display.windowProc(Display.java:5023)
+	at org.eclipse.swt.internal.win32.OS.SetWindowPos(Native Method)
+	at org.eclipse.swt.widgets.Widget.SetWindowPos(Widget.java:1465)
+	at org.eclipse.swt.widgets.Control.setBounds(Control.java:3143)
+	at org.eclipse.swt.widgets.Composite.setBounds(Composite.java:1020)
+	at org.eclipse.swt.widgets.Control.setBounds(Control.java:3104)
+	at org.eclipse.swt.widgets.Control.setSize(Control.java:3641)
+	at org.eclipse.swt.widgets.Control.setSize(Control.java:3665)
+	at org.eclipse.swt.widgets.Control.pack(Control.java:2129)
+	at org.eclipse.swt.widgets.Control.pack(Control.java:2103)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.adjustTopRight(StackRenderer.java:786)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1263)
+	at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer$1.handleEvent(LazyStackRenderer.java:69)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler$1.run(UIEventHandler.java:40)
+	at org.eclipse.swt.widgets.Synchronizer.syncExec(Synchronizer.java:187)
+	at org.eclipse.ui.internal.UISynchronizer.syncExec(UISynchronizer.java:156)
+	at org.eclipse.swt.widgets.Display.syncExec(Display.java:4734)
+	at org.eclipse.e4.ui.internal.workbench.swt.E4Application$1.syncExec(E4Application.java:218)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler.handleEvent(UIEventHandler.java:36)
+	at org.eclipse.equinox.internal.event.EventHandlerWrapper.handleEvent(EventHandlerWrapper.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:1)
+	at org.eclipse.osgi.framework.eventmgr.EventManager.dispatchEvent(EventManager.java:230)
+	at org.eclipse.osgi.framework.eventmgr.ListenerQueue.dispatchEventSynchronous(ListenerQueue.java:148)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.dispatchEvent(EventAdminImpl.java:135)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.sendEvent(EventAdminImpl.java:78)
+	at org.eclipse.equinox.internal.event.EventComponent.sendEvent(EventComponent.java:39)
+	at org.eclipse.e4.ui.services.internal.events.EventBroker.send(EventBroker.java:81)
+	at org.eclipse.e4.ui.internal.workbench.UIEventPublisher.notifyChanged(UIEventPublisher.java:59)
+	at org.eclipse.emf.common.notify.impl.BasicNotifierImpl.eNotify(BasicNotifierImpl.java:374)
+	at org.eclipse.e4.ui.model.application.ui.impl.ElementContainerImpl.setSelectedElement(ElementContainerImpl.java:171)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer$10.widgetSelected(StackRenderer.java:1031)
+	at org.eclipse.swt.widgets.TypedListener.handleEvent(TypedListener.java:248)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1085)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1070)
+	at org.eclipse.swt.widgets.Widget.notifyListeners(Widget.java:782)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3110)
+	at org.eclipse.swt.custom.CTabFolder.onMouse(CTabFolder.java:1794)
+	at org.eclipse.swt.custom.CTabFolder$1.handleEvent(CTabFolder.java:283)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+
+!ENTRY org.eclipse.e4.ui.workbench 4 0 2016-02-23 15:42:21.483
+!MESSAGE Error setting focus to : org.eclipse.e4.ui.model.application.ui.basic.impl.PartImpl core_cm4.h
+!STACK 0
+org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.swt.SWT.error(SWT.java:4441)
+	at org.eclipse.swt.SWT.error(SWT.java:4356)
+	at org.eclipse.swt.SWT.error(SWT.java:4327)
+	at org.eclipse.swt.widgets.Widget.error(Widget.java:476)
+	at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348)
+	at org.eclipse.swt.widgets.Control.setFocus(Control.java:3320)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.ui.texteditor.StatusTextEditor.setFocus(StatusTextEditor.java:120)
+	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.delegateSetFocus(CompatibilityPart.java:191)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:253)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:225)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.focusGui(PartRenderingEngine.java:795)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer$2.setFocus(ContributedPartRenderer.java:100)
+	at org.eclipse.swt.custom.CTabItem.setFocus(CTabItem.java:332)
+	at org.eclipse.swt.custom.CTabFolder.setFocus(CTabFolder.java:2555)
+	at org.eclipse.swt.widgets.Control.fixFocus(Control.java:1052)
+	at org.eclipse.swt.widgets.Control.setVisible(Control.java:3818)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3098)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3055)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1259)
+	at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer$1.handleEvent(LazyStackRenderer.java:69)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler$1.run(UIEventHandler.java:40)
+	at org.eclipse.swt.widgets.Synchronizer.syncExec(Synchronizer.java:187)
+	at org.eclipse.ui.internal.UISynchronizer.syncExec(UISynchronizer.java:156)
+	at org.eclipse.swt.widgets.Display.syncExec(Display.java:4734)
+	at org.eclipse.e4.ui.internal.workbench.swt.E4Application$1.syncExec(E4Application.java:218)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler.handleEvent(UIEventHandler.java:36)
+	at org.eclipse.equinox.internal.event.EventHandlerWrapper.handleEvent(EventHandlerWrapper.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:1)
+	at org.eclipse.osgi.framework.eventmgr.EventManager.dispatchEvent(EventManager.java:230)
+	at org.eclipse.osgi.framework.eventmgr.ListenerQueue.dispatchEventSynchronous(ListenerQueue.java:148)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.dispatchEvent(EventAdminImpl.java:135)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.sendEvent(EventAdminImpl.java:78)
+	at org.eclipse.equinox.internal.event.EventComponent.sendEvent(EventComponent.java:39)
+	at org.eclipse.e4.ui.services.internal.events.EventBroker.send(EventBroker.java:81)
+	at org.eclipse.e4.ui.internal.workbench.UIEventPublisher.notifyChanged(UIEventPublisher.java:59)
+	at org.eclipse.emf.common.notify.impl.BasicNotifierImpl.eNotify(BasicNotifierImpl.java:374)
+	at org.eclipse.e4.ui.model.application.ui.impl.ElementContainerImpl.setSelectedElement(ElementContainerImpl.java:171)
+	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1258)
+	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1215)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.closePart(StackRenderer.java:1218)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.access$3(StackRenderer.java:1200)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer$12.close(StackRenderer.java:1092)
+	at org.eclipse.swt.custom.CTabFolder.onMouse(CTabFolder.java:1874)
+	at org.eclipse.swt.custom.CTabFolder$1.handleEvent(CTabFolder.java:288)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+
+!ENTRY org.eclipse.e4.ui.workbench 4 0 2016-02-23 15:42:22.331
+!MESSAGE Error setting focus to : org.eclipse.e4.ui.model.application.ui.basic.impl.PartImpl K64FN1Mxxx12_flash.ld
+!STACK 0
+org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.swt.SWT.error(SWT.java:4441)
+	at org.eclipse.swt.SWT.error(SWT.java:4356)
+	at org.eclipse.swt.SWT.error(SWT.java:4327)
+	at org.eclipse.swt.widgets.Widget.error(Widget.java:476)
+	at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348)
+	at org.eclipse.swt.widgets.Control.setFocus(Control.java:3320)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.ui.texteditor.StatusTextEditor.setFocus(StatusTextEditor.java:120)
+	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.delegateSetFocus(CompatibilityPart.java:191)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:253)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:225)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.focusGui(PartRenderingEngine.java:795)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer$2.setFocus(ContributedPartRenderer.java:100)
+	at org.eclipse.swt.custom.CTabItem.setFocus(CTabItem.java:332)
+	at org.eclipse.swt.custom.CTabFolder.setFocus(CTabFolder.java:2555)
+	at org.eclipse.swt.widgets.Control.fixFocus(Control.java:1052)
+	at org.eclipse.swt.widgets.Control.setVisible(Control.java:3818)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3098)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3106)
+	at org.eclipse.swt.custom.CTabFolder.onMouse(CTabFolder.java:1794)
+	at org.eclipse.swt.custom.CTabFolder$1.handleEvent(CTabFolder.java:283)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+
+!ENTRY org.eclipse.e4.ui.workbench 4 0 2016-02-23 15:42:24.142
+!MESSAGE Error setting focus to : org.eclipse.e4.ui.model.application.ui.basic.impl.PartImpl core_cm4.h
+!STACK 0
+org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.swt.SWT.error(SWT.java:4441)
+	at org.eclipse.swt.SWT.error(SWT.java:4356)
+	at org.eclipse.swt.SWT.error(SWT.java:4327)
+	at org.eclipse.swt.widgets.Widget.error(Widget.java:476)
+	at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348)
+	at org.eclipse.swt.widgets.Control.setFocus(Control.java:3320)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.ui.texteditor.StatusTextEditor.setFocus(StatusTextEditor.java:120)
+	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.delegateSetFocus(CompatibilityPart.java:191)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:253)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:225)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.focusGui(PartRenderingEngine.java:795)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer$2.setFocus(ContributedPartRenderer.java:100)
+	at org.eclipse.swt.custom.CTabItem.setFocus(CTabItem.java:332)
+	at org.eclipse.swt.custom.CTabFolder.setFocus(CTabFolder.java:2555)
+	at org.eclipse.swt.widgets.Control.fixFocus(Control.java:1052)
+	at org.eclipse.swt.widgets.Control.setVisible(Control.java:3818)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3098)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3055)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1259)
+	at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer$1.handleEvent(LazyStackRenderer.java:69)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler$1.run(UIEventHandler.java:40)
+	at org.eclipse.swt.widgets.Synchronizer.syncExec(Synchronizer.java:187)
+	at org.eclipse.ui.internal.UISynchronizer.syncExec(UISynchronizer.java:156)
+	at org.eclipse.swt.widgets.Display.syncExec(Display.java:4734)
+	at org.eclipse.e4.ui.internal.workbench.swt.E4Application$1.syncExec(E4Application.java:218)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler.handleEvent(UIEventHandler.java:36)
+	at org.eclipse.equinox.internal.event.EventHandlerWrapper.handleEvent(EventHandlerWrapper.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:1)
+	at org.eclipse.osgi.framework.eventmgr.EventManager.dispatchEvent(EventManager.java:230)
+	at org.eclipse.osgi.framework.eventmgr.ListenerQueue.dispatchEventSynchronous(ListenerQueue.java:148)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.dispatchEvent(EventAdminImpl.java:135)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.sendEvent(EventAdminImpl.java:78)
+	at org.eclipse.equinox.internal.event.EventComponent.sendEvent(EventComponent.java:39)
+	at org.eclipse.e4.ui.services.internal.events.EventBroker.send(EventBroker.java:81)
+	at org.eclipse.e4.ui.internal.workbench.UIEventPublisher.notifyChanged(UIEventPublisher.java:59)
+	at org.eclipse.emf.common.notify.impl.BasicNotifierImpl.eNotify(BasicNotifierImpl.java:374)
+	at org.eclipse.e4.ui.model.application.ui.impl.ElementContainerImpl.setSelectedElement(ElementContainerImpl.java:171)
+	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1258)
+	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1215)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.closePart(StackRenderer.java:1218)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.access$3(StackRenderer.java:1200)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer$12.close(StackRenderer.java:1092)
+	at org.eclipse.swt.custom.CTabFolder.onMouse(CTabFolder.java:1874)
+	at org.eclipse.swt.custom.CTabFolder$1.handleEvent(CTabFolder.java:288)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+
+!ENTRY org.eclipse.e4.ui.workbench 4 0 2016-02-23 15:42:25.858
+!MESSAGE Error setting focus to : org.eclipse.e4.ui.model.application.ui.basic.impl.PartImpl main.c
+!STACK 0
+org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.swt.SWT.error(SWT.java:4441)
+	at org.eclipse.swt.SWT.error(SWT.java:4356)
+	at org.eclipse.swt.SWT.error(SWT.java:4327)
+	at org.eclipse.swt.widgets.Widget.error(Widget.java:476)
+	at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348)
+	at org.eclipse.swt.widgets.Control.setFocus(Control.java:3320)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.ui.texteditor.StatusTextEditor.setFocus(StatusTextEditor.java:120)
+	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.delegateSetFocus(CompatibilityPart.java:191)
+	at sun.reflect.GeneratedMethodAccessor34.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:253)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:225)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.focusGui(PartRenderingEngine.java:795)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer$2.setFocus(ContributedPartRenderer.java:100)
+	at org.eclipse.swt.custom.CTabItem.setFocus(CTabItem.java:332)
+	at org.eclipse.swt.custom.CTabFolder.setFocus(CTabFolder.java:2555)
+	at org.eclipse.swt.widgets.Control.fixFocus(Control.java:1052)
+	at org.eclipse.swt.widgets.Control.setVisible(Control.java:3818)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3098)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3055)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1259)
+	at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer$1.handleEvent(LazyStackRenderer.java:69)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler$1.run(UIEventHandler.java:40)
+	at org.eclipse.swt.widgets.Synchronizer.syncExec(Synchronizer.java:187)
+	at org.eclipse.ui.internal.UISynchronizer.syncExec(UISynchronizer.java:156)
+	at org.eclipse.swt.widgets.Display.syncExec(Display.java:4734)
+	at org.eclipse.e4.ui.internal.workbench.swt.E4Application$1.syncExec(E4Application.java:218)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler.handleEvent(UIEventHandler.java:36)
+	at org.eclipse.equinox.internal.event.EventHandlerWrapper.handleEvent(EventHandlerWrapper.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:1)
+	at org.eclipse.osgi.framework.eventmgr.EventManager.dispatchEvent(EventManager.java:230)
+	at org.eclipse.osgi.framework.eventmgr.ListenerQueue.dispatchEventSynchronous(ListenerQueue.java:148)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.dispatchEvent(EventAdminImpl.java:135)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.sendEvent(EventAdminImpl.java:78)
+	at org.eclipse.equinox.internal.event.EventComponent.sendEvent(EventComponent.java:39)
+	at org.eclipse.e4.ui.services.internal.events.EventBroker.send(EventBroker.java:81)
+	at org.eclipse.e4.ui.internal.workbench.UIEventPublisher.notifyChanged(UIEventPublisher.java:59)
+	at org.eclipse.emf.common.notify.impl.BasicNotifierImpl.eNotify(BasicNotifierImpl.java:374)
+	at org.eclipse.e4.ui.model.application.ui.impl.ElementContainerImpl.setSelectedElement(ElementContainerImpl.java:171)
+	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1258)
+	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1215)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.closePart(StackRenderer.java:1218)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.access$3(StackRenderer.java:1200)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer$12.close(StackRenderer.java:1092)
+	at org.eclipse.swt.custom.CTabFolder.onMouse(CTabFolder.java:1874)
+	at org.eclipse.swt.custom.CTabFolder$1.handleEvent(CTabFolder.java:288)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+
+!ENTRY org.eclipse.cdt.core 1 0 2016-02-23 15:56:24.289
+!MESSAGE Indexed 'GPIO' (3 sources, 53 headers) in 1.84 sec: 4,857 declarations; 6,187 references; 0 unresolved inclusions; 34 syntax errors; 533 unresolved names (4.6%)
+
+!ENTRY org.eclipse.cdt.core 1 0 2016-02-23 15:57:01.242
+!MESSAGE Indexed 'GPIO' (3 sources, 53 headers) in 1.85 sec: 4,857 declarations; 6,187 references; 0 unresolved inclusions; 34 syntax errors; 533 unresolved names (4.6%)
+
+!ENTRY org.eclipse.equinox.p2.metadata.repository 2 0 2016-02-23 16:01:45.032
+!MESSAGE Error parsing metadata repository
+!SUBENTRY 1 org.eclipse.equinox.p2.core 2 0 2016-02-23 16:01:45.032
+!MESSAGE Error in file:/C:/Freescale/KDS_3.0.0/eclipse/p2/org.eclipse.equinox.p2.repository/cache/content-783366767.jar at line 13356, column 45: Missing required attribute in "unit": id
+
+!ENTRY org.eclipse.equinox.p2.core 4 0 2016-02-23 16:01:47.418
+!MESSAGE Provisioning exception
+!STACK 1
+org.eclipse.equinox.p2.core.ProvisionException: No repository found at file:/C:/Freescale/KSDK_1.3.0/tools/eclipse_update/.
+	at org.eclipse.equinox.internal.p2.repository.helpers.AbstractRepositoryManager.fail(AbstractRepositoryManager.java:395)
+	at org.eclipse.equinox.internal.p2.repository.helpers.AbstractRepositoryManager.loadRepository(AbstractRepositoryManager.java:692)
+	at org.eclipse.equinox.internal.p2.metadata.repository.MetadataRepositoryManager.loadRepository(MetadataRepositoryManager.java:96)
+	at org.eclipse.equinox.internal.p2.metadata.repository.MetadataRepositoryManager.loadRepository(MetadataRepositoryManager.java:92)
+	at org.eclipse.equinox.p2.ui.LoadMetadataRepositoryJob.doLoad(LoadMetadataRepositoryJob.java:117)
+	at org.eclipse.equinox.p2.ui.LoadMetadataRepositoryJob.runModal(LoadMetadataRepositoryJob.java:102)
+	at org.eclipse.equinox.internal.p2.ui.sdk.PreloadingRepositoryHandler$2.runModal(PreloadingRepositoryHandler.java:83)
+	at org.eclipse.equinox.p2.operations.ProvisioningJob.run(ProvisioningJob.java:177)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.equinox.p2.metadata.repository 4 1000 2016-02-23 16:01:47.418
+!MESSAGE No repository found at file:/C:/Freescale/KSDK_1.3.0/tools/eclipse_update/.
+
+!ENTRY org.eclipse.equinox.p2.core 4 0 2016-02-23 16:01:47.426
+!MESSAGE Provisioning exception
+!STACK 1
+org.eclipse.equinox.p2.core.ProvisionException: No repository found at file:/C:/Freescale/KSDK_1.3.0/lib/.
+	at org.eclipse.equinox.internal.p2.repository.helpers.AbstractRepositoryManager.fail(AbstractRepositoryManager.java:395)
+	at org.eclipse.equinox.internal.p2.repository.helpers.AbstractRepositoryManager.loadRepository(AbstractRepositoryManager.java:692)
+	at org.eclipse.equinox.internal.p2.metadata.repository.MetadataRepositoryManager.loadRepository(MetadataRepositoryManager.java:96)
+	at org.eclipse.equinox.internal.p2.metadata.repository.MetadataRepositoryManager.loadRepository(MetadataRepositoryManager.java:92)
+	at org.eclipse.equinox.p2.ui.LoadMetadataRepositoryJob.doLoad(LoadMetadataRepositoryJob.java:117)
+	at org.eclipse.equinox.p2.ui.LoadMetadataRepositoryJob.runModal(LoadMetadataRepositoryJob.java:102)
+	at org.eclipse.equinox.internal.p2.ui.sdk.PreloadingRepositoryHandler$2.runModal(PreloadingRepositoryHandler.java:83)
+	at org.eclipse.equinox.p2.operations.ProvisioningJob.run(ProvisioningJob.java:177)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.equinox.p2.metadata.repository 4 1000 2016-02-23 16:01:47.426
+!MESSAGE No repository found at file:/C:/Freescale/KSDK_1.3.0/lib/.
+
+!ENTRY org.eclipse.equinox.p2.core 4 0 2016-02-23 16:01:50.769
+!MESSAGE Provisioning exception
+!STACK 1
+org.eclipse.equinox.p2.core.ProvisionException: No repository found at file:/C:/Freescale/KSDK_1.3.0/tools/.
+	at org.eclipse.equinox.internal.p2.repository.helpers.AbstractRepositoryManager.fail(AbstractRepositoryManager.java:395)
+	at org.eclipse.equinox.internal.p2.repository.helpers.AbstractRepositoryManager.loadRepository(AbstractRepositoryManager.java:692)
+	at org.eclipse.equinox.internal.p2.metadata.repository.MetadataRepositoryManager.loadRepository(MetadataRepositoryManager.java:96)
+	at org.eclipse.equinox.internal.p2.metadata.repository.MetadataRepositoryManager.loadRepository(MetadataRepositoryManager.java:92)
+	at org.eclipse.equinox.p2.ui.LoadMetadataRepositoryJob.doLoad(LoadMetadataRepositoryJob.java:117)
+	at org.eclipse.equinox.p2.ui.LoadMetadataRepositoryJob.runModal(LoadMetadataRepositoryJob.java:102)
+	at org.eclipse.equinox.internal.p2.ui.sdk.PreloadingRepositoryHandler$2.runModal(PreloadingRepositoryHandler.java:83)
+	at org.eclipse.equinox.p2.operations.ProvisioningJob.run(ProvisioningJob.java:177)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.equinox.p2.metadata.repository 4 1000 2016-02-23 16:01:50.769
+!MESSAGE No repository found at file:/C:/Freescale/KSDK_1.3.0/tools/.
+
+!ENTRY org.eclipse.equinox.p2.core 4 0 2016-02-23 16:01:50.783
+!MESSAGE Provisioning exception
+!STACK 1
+org.eclipse.equinox.p2.core.ProvisionException: No repository found at file:/C:/Freescale/KSDK_1.1.0/.
+	at org.eclipse.equinox.internal.p2.repository.helpers.AbstractRepositoryManager.fail(AbstractRepositoryManager.java:395)
+	at org.eclipse.equinox.internal.p2.repository.helpers.AbstractRepositoryManager.loadRepository(AbstractRepositoryManager.java:692)
+	at org.eclipse.equinox.internal.p2.metadata.repository.MetadataRepositoryManager.loadRepository(MetadataRepositoryManager.java:96)
+	at org.eclipse.equinox.internal.p2.metadata.repository.MetadataRepositoryManager.loadRepository(MetadataRepositoryManager.java:92)
+	at org.eclipse.equinox.p2.ui.LoadMetadataRepositoryJob.doLoad(LoadMetadataRepositoryJob.java:117)
+	at org.eclipse.equinox.p2.ui.LoadMetadataRepositoryJob.runModal(LoadMetadataRepositoryJob.java:102)
+	at org.eclipse.equinox.internal.p2.ui.sdk.PreloadingRepositoryHandler$2.runModal(PreloadingRepositoryHandler.java:83)
+	at org.eclipse.equinox.p2.operations.ProvisioningJob.run(ProvisioningJob.java:177)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.equinox.p2.metadata.repository 4 1000 2016-02-23 16:01:50.783
+!MESSAGE No repository found at file:/C:/Freescale/KSDK_1.1.0/.
+!SESSION 2016-02-23 21:38:36.370 -----------------------------------------------
+eclipse.buildId=3.1.0.201512141710
+java.version=1.7.0_76
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY org.eclipse.egit.ui 2 0 2016-02-23 21:39:00.968
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2016-02-23 21:39:00.968
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\sethg'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.cdt.core 1 0 2016-02-23 21:40:47.700
+!MESSAGE Indexed 'ADC' (3 sources, 53 headers) in 4.03 sec: 4,877 declarations; 6,358 references; 0 unresolved inclusions; 34 syntax errors; 533 unresolved names (4.5%)
+
+!ENTRY org.eclipse.cdt.core 1 0 2016-02-23 21:40:51.440
+!MESSAGE Indexed 'UART' (3 sources, 53 headers) in 3.72 sec: 4,869 declarations; 6,316 references; 0 unresolved inclusions; 34 syntax errors; 533 unresolved names (4.5%)
+
+!ENTRY org.eclipse.cdt.core 1 0 2016-02-23 21:40:55.133
+!MESSAGE Indexed 'NVIC' (3 sources, 53 headers) in 3.67 sec: 4,863 declarations; 6,316 references; 0 unresolved inclusions; 34 syntax errors; 533 unresolved names (4.6%)
+
+!ENTRY org.eclipse.cdt.core 1 0 2016-02-23 21:40:59.131
+!MESSAGE Indexed 'FTM_AND_PWM' (3 sources, 53 headers) in 3.98 sec: 4,860 declarations; 6,274 references; 0 unresolved inclusions; 34 syntax errors; 533 unresolved names (4.6%)
+!SESSION 2016-02-23 21:55:20.123 -----------------------------------------------
+eclipse.buildId=3.1.0.201512141710
+java.version=1.7.0_76
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY org.eclipse.egit.ui 2 0 2016-02-23 21:55:36.366
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2016-02-23 21:55:36.366
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\sethg'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+!SESSION 2016-02-24 10:33:42.392 -----------------------------------------------
+eclipse.buildId=3.1.0.201512141710
+java.version=1.7.0_76
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY org.eclipse.egit.ui 2 0 2016-02-24 10:33:54.222
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2016-02-24 10:33:54.238
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\sethg'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.cdt.core 1 0 2016-02-24 10:35:15.307
+!MESSAGE Indexed '4part1' (3 sources, 53 headers) in 2.54 sec: 4,857 declarations; 6,187 references; 0 unresolved inclusions; 34 syntax errors; 533 unresolved names (4.6%)
+
+!ENTRY org.eclipse.e4.ui.workbench 4 0 2016-02-24 10:56:30.589
+!MESSAGE Error setting focus to : org.eclipse.e4.ui.model.application.ui.basic.impl.PartImpl main.c
+!STACK 0
+org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.swt.SWT.error(SWT.java:4441)
+	at org.eclipse.swt.SWT.error(SWT.java:4356)
+	at org.eclipse.swt.SWT.error(SWT.java:4327)
+	at org.eclipse.swt.widgets.Widget.error(Widget.java:476)
+	at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348)
+	at org.eclipse.swt.widgets.Control.setFocus(Control.java:3320)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.ui.texteditor.StatusTextEditor.setFocus(StatusTextEditor.java:120)
+	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.delegateSetFocus(CompatibilityPart.java:191)
+	at sun.reflect.GeneratedMethodAccessor38.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:253)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:225)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.focusGui(PartRenderingEngine.java:795)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer$2.setFocus(ContributedPartRenderer.java:100)
+	at org.eclipse.swt.custom.CTabItem.setFocus(CTabItem.java:332)
+	at org.eclipse.swt.custom.CTabFolder.setFocus(CTabFolder.java:2555)
+	at org.eclipse.swt.widgets.Control.fixFocus(Control.java:1052)
+	at org.eclipse.swt.widgets.Control.setVisible(Control.java:3818)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3098)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3055)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1259)
+	at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer$1.handleEvent(LazyStackRenderer.java:69)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler$1.run(UIEventHandler.java:40)
+	at org.eclipse.swt.widgets.Synchronizer.syncExec(Synchronizer.java:187)
+	at org.eclipse.ui.internal.UISynchronizer.syncExec(UISynchronizer.java:156)
+	at org.eclipse.swt.widgets.Display.syncExec(Display.java:4734)
+	at org.eclipse.e4.ui.internal.workbench.swt.E4Application$1.syncExec(E4Application.java:218)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler.handleEvent(UIEventHandler.java:36)
+	at org.eclipse.equinox.internal.event.EventHandlerWrapper.handleEvent(EventHandlerWrapper.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:1)
+	at org.eclipse.osgi.framework.eventmgr.EventManager.dispatchEvent(EventManager.java:230)
+	at org.eclipse.osgi.framework.eventmgr.ListenerQueue.dispatchEventSynchronous(ListenerQueue.java:148)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.dispatchEvent(EventAdminImpl.java:135)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.sendEvent(EventAdminImpl.java:78)
+	at org.eclipse.equinox.internal.event.EventComponent.sendEvent(EventComponent.java:39)
+	at org.eclipse.e4.ui.services.internal.events.EventBroker.send(EventBroker.java:81)
+	at org.eclipse.e4.ui.internal.workbench.UIEventPublisher.notifyChanged(UIEventPublisher.java:59)
+	at org.eclipse.emf.common.notify.impl.BasicNotifierImpl.eNotify(BasicNotifierImpl.java:374)
+	at org.eclipse.e4.ui.model.application.ui.impl.ElementContainerImpl.setSelectedElement(ElementContainerImpl.java:171)
+	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1258)
+	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1215)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.closePart(StackRenderer.java:1218)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.access$3(StackRenderer.java:1200)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer$12.close(StackRenderer.java:1092)
+	at org.eclipse.swt.custom.CTabFolder.onMouse(CTabFolder.java:1874)
+	at org.eclipse.swt.custom.CTabFolder$1.handleEvent(CTabFolder.java:288)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+
+!ENTRY org.eclipse.e4.ui.workbench 4 0 2016-02-24 10:56:35.094
+!MESSAGE Error setting focus to : org.eclipse.e4.ui.model.application.ui.basic.impl.PartImpl main.c
+!STACK 0
+org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.swt.SWT.error(SWT.java:4441)
+	at org.eclipse.swt.SWT.error(SWT.java:4356)
+	at org.eclipse.swt.SWT.error(SWT.java:4327)
+	at org.eclipse.swt.widgets.Widget.error(Widget.java:476)
+	at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348)
+	at org.eclipse.swt.widgets.Control.setFocus(Control.java:3320)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.ui.texteditor.StatusTextEditor.setFocus(StatusTextEditor.java:120)
+	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.delegateSetFocus(CompatibilityPart.java:191)
+	at sun.reflect.GeneratedMethodAccessor38.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:253)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:225)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.focusGui(PartRenderingEngine.java:795)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer$2.setFocus(ContributedPartRenderer.java:100)
+	at org.eclipse.swt.custom.CTabItem.setFocus(CTabItem.java:332)
+	at org.eclipse.swt.custom.CTabFolder.setFocus(CTabFolder.java:2555)
+	at org.eclipse.swt.widgets.Control.fixFocus(Control.java:1052)
+	at org.eclipse.swt.widgets.Control.setVisible(Control.java:3818)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3098)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3106)
+	at org.eclipse.swt.custom.CTabFolder.onMouse(CTabFolder.java:1794)
+	at org.eclipse.swt.custom.CTabFolder$1.handleEvent(CTabFolder.java:283)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+
+!ENTRY org.eclipse.e4.ui.workbench 4 0 2016-02-24 10:56:37.190
+!MESSAGE Error setting focus to : org.eclipse.e4.ui.model.application.ui.basic.impl.PartImpl main.c
+!STACK 0
+org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.swt.SWT.error(SWT.java:4441)
+	at org.eclipse.swt.SWT.error(SWT.java:4356)
+	at org.eclipse.swt.SWT.error(SWT.java:4327)
+	at org.eclipse.swt.widgets.Widget.error(Widget.java:476)
+	at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348)
+	at org.eclipse.swt.widgets.Control.setFocus(Control.java:3320)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.ui.texteditor.StatusTextEditor.setFocus(StatusTextEditor.java:120)
+	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.delegateSetFocus(CompatibilityPart.java:191)
+	at sun.reflect.GeneratedMethodAccessor38.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:253)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:225)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.focusGui(PartRenderingEngine.java:795)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer$2.setFocus(ContributedPartRenderer.java:100)
+	at org.eclipse.swt.custom.CTabItem.setFocus(CTabItem.java:332)
+	at org.eclipse.swt.custom.CTabFolder.setFocus(CTabFolder.java:2555)
+	at org.eclipse.swt.widgets.Control.fixFocus(Control.java:1052)
+	at org.eclipse.swt.widgets.Control.setVisible(Control.java:3818)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3098)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3106)
+	at org.eclipse.swt.custom.CTabFolder.onMouse(CTabFolder.java:1794)
+	at org.eclipse.swt.custom.CTabFolder$1.handleEvent(CTabFolder.java:283)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+
+!ENTRY org.eclipse.e4.ui.workbench 4 0 2016-02-24 10:56:40.763
+!MESSAGE Error setting focus to : org.eclipse.e4.ui.model.application.ui.basic.impl.PartImpl main.c
+!STACK 0
+org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.swt.SWT.error(SWT.java:4441)
+	at org.eclipse.swt.SWT.error(SWT.java:4356)
+	at org.eclipse.swt.SWT.error(SWT.java:4327)
+	at org.eclipse.swt.widgets.Widget.error(Widget.java:476)
+	at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348)
+	at org.eclipse.swt.widgets.Control.setFocus(Control.java:3320)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.ui.texteditor.StatusTextEditor.setFocus(StatusTextEditor.java:120)
+	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.delegateSetFocus(CompatibilityPart.java:191)
+	at sun.reflect.GeneratedMethodAccessor38.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:253)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:225)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.focusGui(PartRenderingEngine.java:795)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer$2.setFocus(ContributedPartRenderer.java:100)
+	at org.eclipse.swt.custom.CTabItem.setFocus(CTabItem.java:332)
+	at org.eclipse.swt.custom.CTabFolder.setFocus(CTabFolder.java:2555)
+	at org.eclipse.swt.widgets.Control.fixFocus(Control.java:1052)
+	at org.eclipse.swt.widgets.Control.setVisible(Control.java:3818)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3098)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3055)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1259)
+	at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer$1.handleEvent(LazyStackRenderer.java:69)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler$1.run(UIEventHandler.java:40)
+	at org.eclipse.swt.widgets.Synchronizer.syncExec(Synchronizer.java:187)
+	at org.eclipse.ui.internal.UISynchronizer.syncExec(UISynchronizer.java:156)
+	at org.eclipse.swt.widgets.Display.syncExec(Display.java:4734)
+	at org.eclipse.e4.ui.internal.workbench.swt.E4Application$1.syncExec(E4Application.java:218)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler.handleEvent(UIEventHandler.java:36)
+	at org.eclipse.equinox.internal.event.EventHandlerWrapper.handleEvent(EventHandlerWrapper.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:1)
+	at org.eclipse.osgi.framework.eventmgr.EventManager.dispatchEvent(EventManager.java:230)
+	at org.eclipse.osgi.framework.eventmgr.ListenerQueue.dispatchEventSynchronous(ListenerQueue.java:148)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.dispatchEvent(EventAdminImpl.java:135)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.sendEvent(EventAdminImpl.java:78)
+	at org.eclipse.equinox.internal.event.EventComponent.sendEvent(EventComponent.java:39)
+	at org.eclipse.e4.ui.services.internal.events.EventBroker.send(EventBroker.java:81)
+	at org.eclipse.e4.ui.internal.workbench.UIEventPublisher.notifyChanged(UIEventPublisher.java:59)
+	at org.eclipse.emf.common.notify.impl.BasicNotifierImpl.eNotify(BasicNotifierImpl.java:374)
+	at org.eclipse.e4.ui.model.application.ui.impl.ElementContainerImpl.setSelectedElement(ElementContainerImpl.java:171)
+	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1258)
+	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1215)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.closePart(StackRenderer.java:1218)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.access$3(StackRenderer.java:1200)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer$12.close(StackRenderer.java:1092)
+	at org.eclipse.swt.custom.CTabFolder.onMouse(CTabFolder.java:1874)
+	at org.eclipse.swt.custom.CTabFolder$1.handleEvent(CTabFolder.java:288)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+
+!ENTRY org.eclipse.cdt.dsf.ui 2 0 2016-02-24 11:04:50.782
+!MESSAGE Unable to locate file: C:\Downloads\Projects\KDS\wksp5_lab4 B\wksp5\GPIO\Debug/../Project_Settings/Startup_Code/startup_MK64F12.S
+
+!ENTRY org.eclipse.cdt.dsf.ui 2 0 2016-02-24 11:04:52.596
+!MESSAGE Unable to locate file: C:\Downloads\Projects\KDS\wksp5_lab4 B\wksp5\NVIC\Debug/../Sources/main.c
+!SESSION 2016-02-24 11:16:47.533 -----------------------------------------------
+eclipse.buildId=3.1.0.201512141710
+java.version=1.7.0_76
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY org.eclipse.egit.ui 2 0 2016-02-24 11:16:54.161
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2016-02-24 11:16:54.164
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\sethg'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.cdt.dsf.ui 2 0 2016-02-24 11:17:52.409
+!MESSAGE Unable to locate file: C:\Downloads\Projects\KDS\wksp5_lab4 B\wksp5\UART\Debug/../Sources/main.c
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.849
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.851
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.851
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.851
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.859
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.859
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.859
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.860
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.868
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.868
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.868
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.868
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.874
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.874
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.874
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.874
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.882
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.882
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.882
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.882
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.889
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.889
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.889
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.889
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.894
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.894
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.894
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.894
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.899
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.900
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.900
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.900
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.904
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.905
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.905
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.905
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.910
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.911
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.911
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.911
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.915
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.915
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.916
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.916
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.920
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.920
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.920
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.920
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.925
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.925
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.925
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.925
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.928
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.928
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.928
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.928
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.932
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.932
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.932
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.932
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.936
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.936
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.936
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.936
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.941
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.941
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.941
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.941
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.944
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.945
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.945
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.945
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.949
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.949
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.949
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.949
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.955
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.956
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.956
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.956
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:18:30.960
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Source lookup error
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:172)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+Contains: Invalid object
+Contains: Invalid object
+!SUBENTRY 1 org.eclipse.debug.core 4 125 2016-02-24 11:18:30.960
+!MESSAGE Source lookup error
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.960
+!MESSAGE Invalid object
+!SUBENTRY 2 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:18:30.960
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.142
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.142
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.148
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.148
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.153
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.153
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.158
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.158
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.165
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.165
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.169
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.170
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.174
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.174
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.178
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.178
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.182
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.182
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.188
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.189
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.196
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.197
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.202
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.202
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.208
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.208
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.212
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.213
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.219
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.219
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.224
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.224
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.229
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.229
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.235
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.235
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.240
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.240
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.250
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.250
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.debug.core 4 125 2016-02-24 11:19:00.256
+!MESSAGE Error logged from Debug Core: 
+!STACK 1
+org.eclipse.core.runtime.CoreException: Invalid object
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.getSourceName(DsfSourceLookupParticipant.java:194)
+	at org.eclipse.cdt.dsf.debug.sourcelookup.DsfSourceLookupParticipant.findSourceElements(DsfSourceLookupParticipant.java:91)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector$SourceLookupQuery.run(AbstractSourceLookupDirector.java:142)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.doSourceLookup(AbstractSourceLookupDirector.java:505)
+	at org.eclipse.debug.core.sourcelookup.AbstractSourceLookupDirector.getSourceElement(AbstractSourceLookupDirector.java:785)
+	at org.eclipse.cdt.debug.internal.core.srcfinder.CSourceFinder.toLocalPath(CSourceFinder.java:162)
+	at org.eclipse.cdt.debug.internal.core.executables.StandardSourceFileRemapping.remapSourceFile(StandardSourceFileRemapping.java:30)
+	at org.eclipse.cdt.debug.core.executables.Executable.remapSourceFile(Executable.java:172)
+	at org.eclipse.cdt.debug.core.executables.Executable.getSourceFiles(Executable.java:212)
+	at org.eclipse.cdt.debug.internal.ui.views.executables.SourceFilesContentProvider$QuickParseJob.run(SourceFilesContentProvider.java:53)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+!SUBENTRY 1 org.eclipse.cdt.dsf 4 -1 2016-02-24 11:19:00.256
+!MESSAGE Invalid object
+
+!ENTRY org.eclipse.cdt.dsf 4 10005 2016-02-24 11:33:41.194
+!MESSAGE Request monitor: 'Sequence "", result for executing step #0 = Status CANCEL: unknown code=1  null' resulted in a cancel status: Status CANCEL: unknown code=1  null, even though the request is not set to cancel.
+
+!ENTRY org.eclipse.cdt.dsf 4 10005 2016-02-24 11:33:41.197
+!MESSAGE Request monitor: 'Sequence "Initializing debugger services", result for executing step #0 = Status CANCEL: unknown code=1  null' resulted in a cancel status: Status CANCEL: unknown code=1  null, even though the request is not set to cancel.
+
+!ENTRY org.eclipse.cdt.dsf 4 10005 2016-02-24 11:33:41.200
+!MESSAGE Request monitor: 'RequestMonitor (org.eclipse.cdt.dsf.concurrent.RequestMonitorWithProgress@1af3a08): Status CANCEL: unknown code=1  null' resulted in a cancel status: Status CANCEL: unknown code=1  null, even though the request is not set to cancel.
+
+!ENTRY com.pemicro.debug.gdbjtag.pne 4 5012 2016-02-24 11:33:41.205
+!MESSAGE Error in services launch sequence
+!STACK 1
+org.eclipse.core.runtime.CoreException: 
+	at org.eclipse.cdt.dsf.concurrent.Sequence.abortExecution(Sequence.java:582)
+	at org.eclipse.cdt.dsf.concurrent.Sequence.access$4(Sequence.java:574)
+	at org.eclipse.cdt.dsf.concurrent.Sequence$2.handleErrorOrWarning(Sequence.java:431)
+	at org.eclipse.cdt.dsf.concurrent.RequestMonitor.handleFailure(RequestMonitor.java:425)
+	at org.eclipse.cdt.dsf.concurrent.RequestMonitor.handleCompleted(RequestMonitor.java:388)
+	at org.eclipse.cdt.dsf.concurrent.RequestMonitor$2.run(RequestMonitor.java:313)
+	at java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
+	at java.util.concurrent.FutureTask.run(Unknown Source)
+	at java.util.concurrent.ScheduledThreadPoolExecutor$ScheduledFutureTask.access$201(Unknown Source)
+	at java.util.concurrent.ScheduledThreadPoolExecutor$ScheduledFutureTask.run(Unknown Source)
+	at java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
+	at java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
+	at java.lang.Thread.run(Unknown Source)
+!SUBENTRY 1 unknown 8 1 2016-02-24 11:33:41.205
+!MESSAGE 
+!SESSION 2016-02-24 13:25:41.202 -----------------------------------------------
+eclipse.buildId=3.1.0.201512141710
+java.version=1.7.0_76
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY org.eclipse.egit.ui 2 0 2016-02-24 13:25:59.081
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2016-02-24 13:25:59.097
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\sethg'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+!SESSION 2018-02-06 20:57:47.556 -----------------------------------------------
+eclipse.buildId=3.2.0.201603041649
+java.version=1.7.0_76
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide
+
+!ENTRY org.eclipse.cdt.core 4 0 2018-02-06 20:57:54.245
+!MESSAGE Can't load preferences from file C:/Users/Akash/Desktop/Lab 4 595/ECE595_Lab 4_Seth Tucker/Seth Tucker Lab4/wksp5/GPIO/.settings/language.settings.xml
+!STACK 1
+org.eclipse.core.runtime.CoreException: Internal error while trying to load XML document
+	at org.eclipse.cdt.internal.core.XmlUtil.loadXml(XmlUtil.java:264)
+	at org.eclipse.cdt.internal.core.language.settings.providers.LanguageSettingsProvidersSerializer.loadLanguageSettings(LanguageSettingsProvidersSerializer.java:1145)
+	at org.eclipse.cdt.internal.core.settings.model.xml.XmlProjectDescriptionStorage.loadProjectDescription(XmlProjectDescriptionStorage.java:499)
+	at org.eclipse.cdt.internal.core.settings.model.xml.XmlProjectDescriptionStorage.getProjectDescription(XmlProjectDescriptionStorage.java:237)
+	at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.getProjectDescriptionInternal(CProjectDescriptionManager.java:437)
+	at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.getProjectDescription(CProjectDescriptionManager.java:419)
+	at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.getProjectDescription(CProjectDescriptionManager.java:413)
+	at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.getProjectDescription(CProjectDescriptionManager.java:406)
+	at org.eclipse.cdt.internal.core.model.CProject.computeSourceRoots(CProject.java:584)
+	at org.eclipse.cdt.internal.core.model.CProject.computeChildren(CProject.java:605)
+	at org.eclipse.cdt.internal.core.model.CProject.buildStructure(CProject.java:569)
+	at org.eclipse.cdt.internal.core.model.Openable.generateInfos(Openable.java:261)
+	at org.eclipse.cdt.internal.core.model.CElement.openWhenClosed(CElement.java:427)
+	at org.eclipse.cdt.internal.core.model.CElement.getElementInfo(CElement.java:305)
+	at org.eclipse.cdt.internal.core.model.CElement.getElementInfo(CElement.java:295)
+	at org.eclipse.cdt.internal.core.model.Parent.getChildren(Parent.java:55)
+	at org.eclipse.cdt.internal.core.model.CProject.getSourceRoots(CProject.java:467)
+	at org.eclipse.cdt.internal.core.model.CModelManager.create(CModelManager.java:337)
+	at org.eclipse.cdt.core.model.CoreModel.create(CoreModel.java:121)
+	at org.eclipse.cdt.internal.ui.editor.CDocumentProvider.createTranslationUnit(CDocumentProvider.java:741)
+	at org.eclipse.cdt.internal.ui.editor.CDocumentProvider.createFileInfo(CDocumentProvider.java:773)
+	at org.eclipse.ui.editors.text.TextFileDocumentProvider.connect(TextFileDocumentProvider.java:478)
+	at org.eclipse.cdt.internal.ui.editor.CDocumentProvider.connect(CDocumentProvider.java:726)
+	at org.eclipse.ui.texteditor.AbstractTextEditor.doSetInput(AbstractTextEditor.java:4233)
+	at org.eclipse.ui.texteditor.StatusTextEditor.doSetInput(StatusTextEditor.java:237)
+	at org.eclipse.ui.texteditor.AbstractDecoratedTextEditor.doSetInput(AbstractDecoratedTextEditor.java:1480)
+	at org.eclipse.ui.editors.text.TextEditor.doSetInput(TextEditor.java:169)
+	at org.eclipse.cdt.internal.ui.editor.CEditor.internalDoSetInput(CEditor.java:1430)
+	at org.eclipse.cdt.internal.ui.editor.CEditor.doSetInput(CEditor.java:1395)
+	at org.eclipse.ui.texteditor.AbstractTextEditor$19.run(AbstractTextEditor.java:3220)
+	at org.eclipse.ui.internal.WorkbenchWindow.run(WorkbenchWindow.java:2099)
+	at org.eclipse.ui.texteditor.AbstractTextEditor.internalInit(AbstractTextEditor.java:3238)
+	at org.eclipse.ui.texteditor.AbstractTextEditor.init(AbstractTextEditor.java:3265)
+	at org.eclipse.ui.internal.EditorReference.initialize(EditorReference.java:390)
+	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.create(CompatibilityPart.java:305)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:888)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:869)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.inject(InjectorImpl.java:120)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.internalMake(InjectorImpl.java:337)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.make(InjectorImpl.java:258)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.make(ContextInjectionFactory.java:162)
+	at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.createFromBundle(ReflectionContributionFactory.java:104)
+	at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.doCreate(ReflectionContributionFactory.java:73)
+	at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.create(ReflectionContributionFactory.java:55)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer.createWidget(ContributedPartRenderer.java:127)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createWidget(PartRenderingEngine.java:983)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:662)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1246)
+	at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer.postProcess(LazyStackRenderer.java:103)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:678)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$6.run(PartRenderingEngine.java:547)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:531)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ElementReferenceRenderer.createWidget(ElementReferenceRenderer.java:69)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createWidget(PartRenderingEngine.java:983)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:662)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:185)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:185)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:185)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:185)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveRenderer.processContents(PerspectiveRenderer.java:49)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveStackRenderer.showTab(PerspectiveStackRenderer.java:103)
+	at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer.postProcess(LazyStackRenderer.java:103)
+	at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveStackRenderer.postProcess(PerspectiveStackRenderer.java:77)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:678)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:185)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.WBWRenderer.processContents(WBWRenderer.java:663)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1078)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+Caused by: org.eclipse.core.internal.resources.ResourceException: Resource is out of sync with the file system: '/GPIO/.settings/language.settings.xml'.
+	at org.eclipse.core.internal.localstore.FileSystemResourceManager.read(FileSystemResourceManager.java:793)
+	at org.eclipse.core.internal.resources.File.getContents(File.java:290)
+	at org.eclipse.core.internal.resources.File.getContents(File.java:279)
+	at org.eclipse.cdt.internal.core.XmlUtil.loadXml(XmlUtil.java:257)
+	... 163 more
+!SUBENTRY 1 org.eclipse.cdt.core 4 0 2018-02-06 20:57:54.247
+!MESSAGE Internal error while trying to load XML document
+!STACK 1
+org.eclipse.core.internal.resources.ResourceException: Resource is out of sync with the file system: '/GPIO/.settings/language.settings.xml'.
+	at org.eclipse.core.internal.localstore.FileSystemResourceManager.read(FileSystemResourceManager.java:793)
+	at org.eclipse.core.internal.resources.File.getContents(File.java:290)
+	at org.eclipse.core.internal.resources.File.getContents(File.java:279)
+	at org.eclipse.cdt.internal.core.XmlUtil.loadXml(XmlUtil.java:257)
+	at org.eclipse.cdt.internal.core.language.settings.providers.LanguageSettingsProvidersSerializer.loadLanguageSettings(LanguageSettingsProvidersSerializer.java:1145)
+	at org.eclipse.cdt.internal.core.settings.model.xml.XmlProjectDescriptionStorage.loadProjectDescription(XmlProjectDescriptionStorage.java:499)
+	at org.eclipse.cdt.internal.core.settings.model.xml.XmlProjectDescriptionStorage.getProjectDescription(XmlProjectDescriptionStorage.java:237)
+	at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.getProjectDescriptionInternal(CProjectDescriptionManager.java:437)
+	at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.getProjectDescription(CProjectDescriptionManager.java:419)
+	at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.getProjectDescription(CProjectDescriptionManager.java:413)
+	at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.getProjectDescription(CProjectDescriptionManager.java:406)
+	at org.eclipse.cdt.internal.core.model.CProject.computeSourceRoots(CProject.java:584)
+	at org.eclipse.cdt.internal.core.model.CProject.computeChildren(CProject.java:605)
+	at org.eclipse.cdt.internal.core.model.CProject.buildStructure(CProject.java:569)
+	at org.eclipse.cdt.internal.core.model.Openable.generateInfos(Openable.java:261)
+	at org.eclipse.cdt.internal.core.model.CElement.openWhenClosed(CElement.java:427)
+	at org.eclipse.cdt.internal.core.model.CElement.getElementInfo(CElement.java:305)
+	at org.eclipse.cdt.internal.core.model.CElement.getElementInfo(CElement.java:295)
+	at org.eclipse.cdt.internal.core.model.Parent.getChildren(Parent.java:55)
+	at org.eclipse.cdt.internal.core.model.CProject.getSourceRoots(CProject.java:467)
+	at org.eclipse.cdt.internal.core.model.CModelManager.create(CModelManager.java:337)
+	at org.eclipse.cdt.core.model.CoreModel.create(CoreModel.java:121)
+	at org.eclipse.cdt.internal.ui.editor.CDocumentProvider.createTranslationUnit(CDocumentProvider.java:741)
+	at org.eclipse.cdt.internal.ui.editor.CDocumentProvider.createFileInfo(CDocumentProvider.java:773)
+	at org.eclipse.ui.editors.text.TextFileDocumentProvider.connect(TextFileDocumentProvider.java:478)
+	at org.eclipse.cdt.internal.ui.editor.CDocumentProvider.connect(CDocumentProvider.java:726)
+	at org.eclipse.ui.texteditor.AbstractTextEditor.doSetInput(AbstractTextEditor.java:4233)
+	at org.eclipse.ui.texteditor.StatusTextEditor.doSetInput(StatusTextEditor.java:237)
+	at org.eclipse.ui.texteditor.AbstractDecoratedTextEditor.doSetInput(AbstractDecoratedTextEditor.java:1480)
+	at org.eclipse.ui.editors.text.TextEditor.doSetInput(TextEditor.java:169)
+	at org.eclipse.cdt.internal.ui.editor.CEditor.internalDoSetInput(CEditor.java:1430)
+	at org.eclipse.cdt.internal.ui.editor.CEditor.doSetInput(CEditor.java:1395)
+	at org.eclipse.ui.texteditor.AbstractTextEditor$19.run(AbstractTextEditor.java:3220)
+	at org.eclipse.ui.internal.WorkbenchWindow.run(WorkbenchWindow.java:2099)
+	at org.eclipse.ui.texteditor.AbstractTextEditor.internalInit(AbstractTextEditor.java:3238)
+	at org.eclipse.ui.texteditor.AbstractTextEditor.init(AbstractTextEditor.java:3265)
+	at org.eclipse.ui.internal.EditorReference.initialize(EditorReference.java:390)
+	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.create(CompatibilityPart.java:305)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:888)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:869)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.inject(InjectorImpl.java:120)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.internalMake(InjectorImpl.java:337)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.make(InjectorImpl.java:258)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.make(ContextInjectionFactory.java:162)
+	at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.createFromBundle(ReflectionContributionFactory.java:104)
+	at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.doCreate(ReflectionContributionFactory.java:73)
+	at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.create(ReflectionContributionFactory.java:55)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer.createWidget(ContributedPartRenderer.java:127)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createWidget(PartRenderingEngine.java:983)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:662)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1246)
+	at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer.postProcess(LazyStackRenderer.java:103)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:678)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$6.run(PartRenderingEngine.java:547)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:531)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ElementReferenceRenderer.createWidget(ElementReferenceRenderer.java:69)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createWidget(PartRenderingEngine.java:983)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:662)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:185)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:185)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:185)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:185)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveRenderer.processContents(PerspectiveRenderer.java:49)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveStackRenderer.showTab(PerspectiveStackRenderer.java:103)
+	at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer.postProcess(LazyStackRenderer.java:103)
+	at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveStackRenderer.postProcess(PerspectiveStackRenderer.java:77)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:678)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:185)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:69)
+	at org.eclipse.e4.ui.workbench.renderers.swt.WBWRenderer.processContents(WBWRenderer.java:663)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:674)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:766)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$2(PartRenderingEngine.java:737)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$7.run(PartRenderingEngine.java:731)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:715)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1078)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+!SUBENTRY 2 org.eclipse.core.resources 4 274 2018-02-06 20:57:54.248
+!MESSAGE Resource is out of sync with the file system: '/GPIO/.settings/language.settings.xml'.
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2018-02-06 20:57:56.883
+!MESSAGE External elements location C:\Freescale\KDS_v3\eclipse\ProcessorExpert\BoardConfigurations/wizard_data does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2018-02-06 20:57:57.158
+!MESSAGE Warning: EGit couldn't detect the installation path "gitPrefix" of native Git. Hence EGit can't respect system level
+Git settings which might be configured in ${gitPrefix}/etc/gitconfig under the native Git installation directory.
+The most important of these settings is core.autocrlf. Git for Windows by default sets this parameter to true in
+this system level configuration. The Git installation location can be configured on the
+Team > Git > Configuration preference page's 'System Settings' tab.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.egit.ui 2 0 2018-02-06 20:57:57.165
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\Akash'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.e4.ui.workbench 4 0 2018-02-06 20:58:01.713
+!MESSAGE Error setting focus to : org.eclipse.e4.ui.model.application.ui.basic.impl.PartImpl main.c
+!STACK 0
+org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.swt.SWT.error(SWT.java:4441)
+	at org.eclipse.swt.SWT.error(SWT.java:4356)
+	at org.eclipse.swt.SWT.error(SWT.java:4327)
+	at org.eclipse.swt.widgets.Widget.error(Widget.java:476)
+	at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348)
+	at org.eclipse.swt.widgets.Control.setFocus(Control.java:3320)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1039)
+	at org.eclipse.ui.texteditor.StatusTextEditor.setFocus(StatusTextEditor.java:120)
+	at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.delegateSetFocus(CompatibilityPart.java:191)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:253)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:225)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.focusGui(PartRenderingEngine.java:795)
+	at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer$2.setFocus(ContributedPartRenderer.java:100)
+	at org.eclipse.swt.custom.CTabItem.setFocus(CTabItem.java:332)
+	at org.eclipse.swt.custom.CTabFolder.setFocus(CTabFolder.java:2555)
+	at org.eclipse.swt.widgets.Control.fixFocus(Control.java:1052)
+	at org.eclipse.swt.widgets.Control.setVisible(Control.java:3818)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3098)
+	at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3055)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1259)
+	at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer$1.handleEvent(LazyStackRenderer.java:69)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler$1.run(UIEventHandler.java:40)
+	at org.eclipse.swt.widgets.Synchronizer.syncExec(Synchronizer.java:187)
+	at org.eclipse.ui.internal.UISynchronizer.syncExec(UISynchronizer.java:156)
+	at org.eclipse.swt.widgets.Display.syncExec(Display.java:4734)
+	at org.eclipse.e4.ui.internal.workbench.swt.E4Application$1.syncExec(E4Application.java:218)
+	at org.eclipse.e4.ui.services.internal.events.UIEventHandler.handleEvent(UIEventHandler.java:36)
+	at org.eclipse.equinox.internal.event.EventHandlerWrapper.handleEvent(EventHandlerWrapper.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:197)
+	at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:1)
+	at org.eclipse.osgi.framework.eventmgr.EventManager.dispatchEvent(EventManager.java:230)
+	at org.eclipse.osgi.framework.eventmgr.ListenerQueue.dispatchEventSynchronous(ListenerQueue.java:148)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.dispatchEvent(EventAdminImpl.java:135)
+	at org.eclipse.equinox.internal.event.EventAdminImpl.sendEvent(EventAdminImpl.java:78)
+	at org.eclipse.equinox.internal.event.EventComponent.sendEvent(EventComponent.java:39)
+	at org.eclipse.e4.ui.services.internal.events.EventBroker.send(EventBroker.java:81)
+	at org.eclipse.e4.ui.internal.workbench.UIEventPublisher.notifyChanged(UIEventPublisher.java:59)
+	at org.eclipse.emf.common.notify.impl.BasicNotifierImpl.eNotify(BasicNotifierImpl.java:374)
+	at org.eclipse.e4.ui.model.application.ui.impl.ElementContainerImpl.setSelectedElement(ElementContainerImpl.java:171)
+	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1262)
+	at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1215)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.closePart(StackRenderer.java:1218)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.access$3(StackRenderer.java:1200)
+	at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer$12.close(StackRenderer.java:1092)
+	at org.eclipse.swt.custom.CTabFolder.onMouse(CTabFolder.java:1874)
+	at org.eclipse.swt.custom.CTabFolder$1.handleEvent(CTabFolder.java:288)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+!SESSION 2018-02-06 21:25:29.599 -----------------------------------------------
+eclipse.buildId=3.2.0.201603041649
+java.version=1.7.0_76
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2018-02-06 21:25:38.017
+!MESSAGE External elements location C:\Freescale\KDS_v3\eclipse\ProcessorExpert\BoardConfigurations/wizard_data does not exist
+!SESSION 2023-02-05 15:27:01.004 -----------------------------------------------
+eclipse.buildId=3.2.0.201603041649
+java.version=1.7.0_76
+java.vendor=Oracle Corporation
+BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US
+Framework arguments:  -product com.somniumtech.branding.kds.ide -showlocation
+Command-line arguments:  -os win32 -ws win32 -arch x86 -product com.somniumtech.branding.kds.ide -showlocation
+
+!ENTRY com.processorexpert.core.ide.wizard.ui 2 0 2023-02-05 15:27:14.065
+!MESSAGE External elements location C:\Freescale\KDS_v3\eclipse\ProcessorExpert\BoardConfigurations/wizard_data does not exist
+
+!ENTRY org.eclipse.egit.ui 2 0 2023-02-05 15:27:14.070
+!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git
+user global configuration and to define the default location to store repositories: 'C:\Users\pkalgaon'. If this is
+not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and
+EGit might behave differently since they see different configuration options.
+This warning can be switched off on the Team > Git > Confirmations and Warnings preference page.
+
+!ENTRY org.eclipse.core.resources 4 4 2023-02-05 15:27:39.255
+!MESSAGE Exception occurred while saving project preferences: /ksdk_platform_lib_K64F12/.settings/com.processorexpert.core.ide.newprojectwizard.prefs.
+!STACK 1
+org.eclipse.core.internal.resources.ResourceException: A resource already exists on disk 'C:\Freescale\KSDK_1.3.0\lib\ksdk_platform_lib\kds\K64F12\.settings\com.processorexpert.core.ide.newprojectwizard.prefs'.
+	at org.eclipse.core.internal.resources.File.create(File.java:146)
+	at org.eclipse.core.internal.resources.ProjectPreferences$1.run(ProjectPreferences.java:626)
+	at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2313)
+	at org.eclipse.core.internal.resources.ProjectPreferences.save(ProjectPreferences.java:648)
+	at org.eclipse.core.internal.preferences.EclipsePreferences.internalFlush(EclipsePreferences.java:471)
+	at org.eclipse.core.internal.resources.ProjectPreferences.flush(ProjectPreferences.java:363)
+	at org.eclipse.core.internal.resources.ProjectPreferences.flush(ProjectPreferences.java:366)
+	at com.processorexpert.core.ide.newprojectwizard.CCProjectNatureManager.correctProjectNature(CCProjectNatureManager.java:69)
+	at com.processorexpert.core.ide.newprojectwizard.StartupHandler$1.runInUIThread(StartupHandler.java:48)
+	at org.eclipse.ui.progress.UIJob$1.run(UIJob.java:97)
+	at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:35)
+	at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:136)
+	at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4147)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3764)
+	at org.eclipse.jface.operation.ModalContext$ModalContextThread.block(ModalContext.java:175)
+	at org.eclipse.jface.operation.ModalContext.run(ModalContext.java:390)
+	at org.eclipse.jface.wizard.WizardDialog.run(WizardDialog.java:1059)
+	at org.eclipse.ui.internal.wizards.datatransfer.WizardProjectsImportPage.createProjects(WizardProjectsImportPage.java:1329)
+	at org.eclipse.ui.wizards.datatransfer.ExternalProjectImportWizard.performFinish(ExternalProjectImportWizard.java:113)
+	at org.eclipse.jface.wizard.WizardDialog.finishPressed(WizardDialog.java:853)
+	at org.eclipse.jface.wizard.WizardDialog.buttonPressed(WizardDialog.java:438)
+	at org.eclipse.jface.dialogs.Dialog$2.widgetSelected(Dialog.java:619)
+	at org.eclipse.swt.widgets.TypedListener.handleEvent(TypedListener.java:248)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.jface.window.Window.runEventLoop(Window.java:832)
+	at org.eclipse.jface.window.Window.open(Window.java:808)
+	at org.eclipse.ui.internal.handlers.WizardHandler$Import.executeHandler(WizardHandler.java:158)
+	at org.eclipse.ui.internal.handlers.WizardHandler.execute(WizardHandler.java:290)
+	at org.eclipse.ui.internal.handlers.HandlerProxy.execute(HandlerProxy.java:294)
+	at org.eclipse.ui.internal.handlers.E4HandlerProxy.execute(E4HandlerProxy.java:90)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:229)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:132)
+	at org.eclipse.e4.core.commands.internal.HandlerServiceHandler.execute(HandlerServiceHandler.java:149)
+	at org.eclipse.core.commands.Command.executeWithChecks(Command.java:499)
+	at org.eclipse.core.commands.ParameterizedCommand.executeWithChecks(ParameterizedCommand.java:508)
+	at org.eclipse.e4.core.commands.internal.HandlerServiceImpl.executeHandler(HandlerServiceImpl.java:210)
+	at org.eclipse.ui.internal.handlers.LegacyHandlerService.executeCommand(LegacyHandlerService.java:343)
+	at org.eclipse.ui.internal.actions.CommandAction.runWithEvent(CommandAction.java:159)
+	at org.eclipse.jface.action.ActionContributionItem.handleWidgetSelection(ActionContributionItem.java:595)
+	at org.eclipse.jface.action.ActionContributionItem.access$2(ActionContributionItem.java:511)
+	at org.eclipse.jface.action.ActionContributionItem$5.handleEvent(ActionContributionItem.java:420)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+!SUBENTRY 1 org.eclipse.core.resources 4 272 2023-02-05 15:27:39.256
+!MESSAGE A resource already exists on disk 'C:\Freescale\KSDK_1.3.0\lib\ksdk_platform_lib\kds\K64F12\.settings\com.processorexpert.core.ide.newprojectwizard.prefs'.
+
+!ENTRY com.processorexpert.core.ide.newprojectwizard 4 0 2023-02-05 15:27:39.257
+!MESSAGE Exception occurred while saving project preferences: /ksdk_platform_lib_K64F12/.settings/com.processorexpert.core.ide.newprojectwizard.prefs.
+!STACK 0
+org.osgi.service.prefs.BackingStoreException: Exception occurred while saving project preferences: /ksdk_platform_lib_K64F12/.settings/com.processorexpert.core.ide.newprojectwizard.prefs.
+	at org.eclipse.core.internal.resources.ProjectPreferences.save(ProjectPreferences.java:658)
+	at org.eclipse.core.internal.preferences.EclipsePreferences.internalFlush(EclipsePreferences.java:471)
+	at org.eclipse.core.internal.resources.ProjectPreferences.flush(ProjectPreferences.java:363)
+	at org.eclipse.core.internal.resources.ProjectPreferences.flush(ProjectPreferences.java:366)
+	at com.processorexpert.core.ide.newprojectwizard.CCProjectNatureManager.correctProjectNature(CCProjectNatureManager.java:69)
+	at com.processorexpert.core.ide.newprojectwizard.StartupHandler$1.runInUIThread(StartupHandler.java:48)
+	at org.eclipse.ui.progress.UIJob$1.run(UIJob.java:97)
+	at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:35)
+	at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:136)
+	at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4147)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3764)
+	at org.eclipse.jface.operation.ModalContext$ModalContextThread.block(ModalContext.java:175)
+	at org.eclipse.jface.operation.ModalContext.run(ModalContext.java:390)
+	at org.eclipse.jface.wizard.WizardDialog.run(WizardDialog.java:1059)
+	at org.eclipse.ui.internal.wizards.datatransfer.WizardProjectsImportPage.createProjects(WizardProjectsImportPage.java:1329)
+	at org.eclipse.ui.wizards.datatransfer.ExternalProjectImportWizard.performFinish(ExternalProjectImportWizard.java:113)
+	at org.eclipse.jface.wizard.WizardDialog.finishPressed(WizardDialog.java:853)
+	at org.eclipse.jface.wizard.WizardDialog.buttonPressed(WizardDialog.java:438)
+	at org.eclipse.jface.dialogs.Dialog$2.widgetSelected(Dialog.java:619)
+	at org.eclipse.swt.widgets.TypedListener.handleEvent(TypedListener.java:248)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.jface.window.Window.runEventLoop(Window.java:832)
+	at org.eclipse.jface.window.Window.open(Window.java:808)
+	at org.eclipse.ui.internal.handlers.WizardHandler$Import.executeHandler(WizardHandler.java:158)
+	at org.eclipse.ui.internal.handlers.WizardHandler.execute(WizardHandler.java:290)
+	at org.eclipse.ui.internal.handlers.HandlerProxy.execute(HandlerProxy.java:294)
+	at org.eclipse.ui.internal.handlers.E4HandlerProxy.execute(E4HandlerProxy.java:90)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:229)
+	at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:132)
+	at org.eclipse.e4.core.commands.internal.HandlerServiceHandler.execute(HandlerServiceHandler.java:149)
+	at org.eclipse.core.commands.Command.executeWithChecks(Command.java:499)
+	at org.eclipse.core.commands.ParameterizedCommand.executeWithChecks(ParameterizedCommand.java:508)
+	at org.eclipse.e4.core.commands.internal.HandlerServiceImpl.executeHandler(HandlerServiceImpl.java:210)
+	at org.eclipse.ui.internal.handlers.LegacyHandlerService.executeCommand(LegacyHandlerService.java:343)
+	at org.eclipse.ui.internal.actions.CommandAction.runWithEvent(CommandAction.java:159)
+	at org.eclipse.jface.action.ActionContributionItem.handleWidgetSelection(ActionContributionItem.java:595)
+	at org.eclipse.jface.action.ActionContributionItem.access$2(ActionContributionItem.java:511)
+	at org.eclipse.jface.action.ActionContributionItem$5.handleEvent(ActionContributionItem.java:420)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+
+!ENTRY org.eclipse.cdt.core 1 0 2023-02-05 15:27:45.487
+!MESSAGE Indexed 'ksdk_platform_lib_K64F12' (101 sources, 129 headers) in 5.81 sec: 16,450 declarations; 62,497 references; 0 unresolved inclusions; 0 syntax errors; 0 unresolved names (0%)
+
+!ENTRY org.eclipse.core.resources 4 2 2023-02-05 15:28:09.951
+!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.core.resources".
+!STACK 0
+java.lang.NullPointerException
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:379)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.resourceChanged(SystemTempFileListener.java:218)
+	at org.eclipse.core.internal.events.NotificationManager$1.run(NotificationManager.java:291)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.core.internal.events.NotificationManager.notify(NotificationManager.java:285)
+	at org.eclipse.core.internal.events.NotificationManager.broadcastChanges(NotificationManager.java:149)
+	at org.eclipse.core.internal.resources.Workspace.broadcastPostChange(Workspace.java:378)
+	at org.eclipse.core.internal.resources.Workspace.endOperation(Workspace.java:1498)
+	at org.eclipse.core.internal.resources.InternalWorkspaceJob.run(InternalWorkspaceJob.java:45)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+
+!ENTRY org.eclipse.cdt.core 1 0 2023-02-05 15:28:30.276
+!MESSAGE Indexed '4part1' (3 sources, 61 headers) in 2.59 sec: 5,543 declarations; 8,023 references; 0 unresolved inclusions; 34 syntax errors; 533 unresolved names (3.8%)
+
+!ENTRY org.eclipse.core.resources 4 2 2023-02-05 15:29:11.963
+!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.core.resources".
+!STACK 0
+java.lang.NullPointerException
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:379)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.checkLocalChanges(SystemTempFileListener.java:386)
+	at org.eclipse.rse.files.ui.resources.SystemTempFileListener.resourceChanged(SystemTempFileListener.java:218)
+	at org.eclipse.core.internal.events.NotificationManager$1.run(NotificationManager.java:291)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.core.internal.events.NotificationManager.notify(NotificationManager.java:285)
+	at org.eclipse.core.internal.events.NotificationManager.broadcastChanges(NotificationManager.java:149)
+	at org.eclipse.core.internal.resources.Workspace.broadcastPostChange(Workspace.java:378)
+	at org.eclipse.core.internal.resources.Workspace.endOperation(Workspace.java:1498)
+	at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2322)
+	at org.eclipse.core.internal.events.NotificationManager$NotifyJob.run(NotificationManager.java:40)
+	at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54)
+
+!ENTRY org.eclipse.cdt.core 1 0 2023-02-05 15:38:09.520
+!MESSAGE Indexed 'GPIO' (3 sources, 53 headers) in 1.88 sec: 4,857 declarations; 6,346 references; 0 unresolved inclusions; 34 syntax errors; 533 unresolved names (4.5%)
+
+!ENTRY org.eclipse.cdt.core 1 0 2023-02-05 15:56:41.672
+!MESSAGE Indexed 'Interrupt' (3 sources, 38 headers) in 1.79 sec: 4,092 declarations; 3,926 references; 5 unresolved inclusions; 53 syntax errors; 1,564 unresolved names (16%)
+
+!ENTRY org.eclipse.cdt.dsf 4 10005 2023-02-05 16:04:49.965
+!MESSAGE Request monitor: 'Sequence "", result for executing step #0 = Status CANCEL: unknown code=1  null' resulted in a cancel status: Status CANCEL: unknown code=1  null, even though the request is not set to cancel.
+
+!ENTRY org.eclipse.cdt.dsf 4 10005 2023-02-05 16:04:49.965
+!MESSAGE Request monitor: 'Sequence "Initializing debugger services", result for executing step #0 = Status CANCEL: unknown code=1  null' resulted in a cancel status: Status CANCEL: unknown code=1  null, even though the request is not set to cancel.
+
+!ENTRY org.eclipse.cdt.dsf 4 10005 2023-02-05 16:04:49.965
+!MESSAGE Request monitor: 'RequestMonitor (org.eclipse.cdt.dsf.concurrent.RequestMonitorWithProgress@1b158c1): Status CANCEL: unknown code=1  null' resulted in a cancel status: Status CANCEL: unknown code=1  null, even though the request is not set to cancel.
+
+!ENTRY com.pemicro.debug.gdbjtag.pne 4 5012 2023-02-05 16:04:49.968
+!MESSAGE Error in services launch sequence
+!STACK 1
+org.eclipse.core.runtime.CoreException: 
+	at org.eclipse.cdt.dsf.concurrent.Sequence.abortExecution(Sequence.java:582)
+	at org.eclipse.cdt.dsf.concurrent.Sequence.access$4(Sequence.java:574)
+	at org.eclipse.cdt.dsf.concurrent.Sequence$2.handleErrorOrWarning(Sequence.java:431)
+	at org.eclipse.cdt.dsf.concurrent.RequestMonitor.handleFailure(RequestMonitor.java:425)
+	at org.eclipse.cdt.dsf.concurrent.RequestMonitor.handleCompleted(RequestMonitor.java:388)
+	at org.eclipse.cdt.dsf.concurrent.RequestMonitor$2.run(RequestMonitor.java:313)
+	at java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
+	at java.util.concurrent.FutureTask.run(Unknown Source)
+	at java.util.concurrent.ScheduledThreadPoolExecutor$ScheduledFutureTask.access$201(Unknown Source)
+	at java.util.concurrent.ScheduledThreadPoolExecutor$ScheduledFutureTask.run(Unknown Source)
+	at java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
+	at java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
+	at java.lang.Thread.run(Unknown Source)
+!SUBENTRY 1 unknown 8 1 2023-02-05 16:04:49.969
+!MESSAGE 
+
+!ENTRY org.eclipse.cdt.core 1 0 2023-02-05 16:10:04.814
+!MESSAGE Indexed 'UART' (3 sources, 53 headers) in 2.04 sec: 4,857 declarations; 6,346 references; 0 unresolved inclusions; 34 syntax errors; 533 unresolved names (4.5%)
+
+!ENTRY org.eclipse.e4.ui.workbench.swt 4 2 2023-02-05 16:23:27.155
+!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.e4.ui.workbench.swt".
+!STACK 0
+org.eclipse.e4.core.di.InjectionException: org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:62)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:888)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.disposed(InjectorImpl.java:390)
+	at org.eclipse.e4.core.internal.di.Requestor.disposed(Requestor.java:143)
+	at org.eclipse.e4.core.internal.contexts.ContextObjectSupplier$ContextInjectionListener.update(ContextObjectSupplier.java:76)
+	at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.update(TrackableComputationExt.java:107)
+	at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.handleInvalid(TrackableComputationExt.java:70)
+	at org.eclipse.e4.core.internal.contexts.EclipseContext.dispose(EclipseContext.java:175)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.clearContext(PartRenderingEngine.java:974)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeRemoveGui(PartRenderingEngine.java:954)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$3(PartRenderingEngine.java:862)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$8.run(PartRenderingEngine.java:857)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.removeGui(PartRenderingEngine.java:841)
+	at org.eclipse.ui.internal.WorkbenchWindow.hardClose(WorkbenchWindow.java:1937)
+	at org.eclipse.ui.internal.WorkbenchWindow.busyClose(WorkbenchWindow.java:1560)
+	at org.eclipse.ui.internal.WorkbenchWindow.access$15(WorkbenchWindow.java:1527)
+	at org.eclipse.ui.internal.WorkbenchWindow$10.run(WorkbenchWindow.java:1592)
+	at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70)
+	at org.eclipse.ui.internal.WorkbenchWindow.close(WorkbenchWindow.java:1589)
+	at org.eclipse.ui.internal.Workbench$14.run(Workbench.java:1155)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.ui.internal.Workbench.busyClose(Workbench.java:1137)
+	at org.eclipse.ui.internal.Workbench.access$21(Workbench.java:1079)
+	at org.eclipse.ui.internal.Workbench$19.run(Workbench.java:1410)
+	at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70)
+	at org.eclipse.ui.internal.Workbench.close(Workbench.java:1407)
+	at org.eclipse.ui.internal.Workbench.close(Workbench.java:1380)
+	at org.eclipse.ui.internal.WorkbenchWindow.busyClose(WorkbenchWindow.java:1556)
+	at org.eclipse.ui.internal.WorkbenchWindow.access$15(WorkbenchWindow.java:1527)
+	at org.eclipse.ui.internal.WorkbenchWindow$10.run(WorkbenchWindow.java:1592)
+	at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70)
+	at org.eclipse.ui.internal.WorkbenchWindow.close(WorkbenchWindow.java:1589)
+	at org.eclipse.ui.internal.WorkbenchWindow.close(WorkbenchWindow.java:1603)
+	at org.eclipse.ui.internal.WorkbenchWindow$6.close(WorkbenchWindow.java:521)
+	at org.eclipse.e4.ui.workbench.renderers.swt.WBWRenderer$11.shellClosed(WBWRenderer.java:563)
+	at org.eclipse.swt.widgets.TypedListener.handleEvent(TypedListener.java:98)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1085)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1070)
+	at org.eclipse.swt.widgets.Decorations.closeWidget(Decorations.java:308)
+	at org.eclipse.swt.widgets.Decorations.WM_CLOSE(Decorations.java:1696)
+	at org.eclipse.swt.widgets.Control.windowProc(Control.java:4612)
+	at org.eclipse.swt.widgets.Canvas.windowProc(Canvas.java:339)
+	at org.eclipse.swt.widgets.Decorations.windowProc(Decorations.java:1626)
+	at org.eclipse.swt.widgets.Shell.windowProc(Shell.java:2075)
+	at org.eclipse.swt.widgets.Display.windowProc(Display.java:5023)
+	at org.eclipse.swt.internal.win32.OS.DefWindowProcW(Native Method)
+	at org.eclipse.swt.internal.win32.OS.DefWindowProc(OS.java:2544)
+	at org.eclipse.swt.widgets.Shell.callWindowProc(Shell.java:498)
+	at org.eclipse.swt.widgets.Control.windowProc(Control.java:4705)
+	at org.eclipse.swt.widgets.Canvas.windowProc(Canvas.java:339)
+	at org.eclipse.swt.widgets.Decorations.windowProc(Decorations.java:1626)
+	at org.eclipse.swt.widgets.Shell.windowProc(Shell.java:2075)
+	at org.eclipse.swt.widgets.Display.windowProc(Display.java:5023)
+	at org.eclipse.swt.internal.win32.OS.DefWindowProcW(Native Method)
+	at org.eclipse.swt.internal.win32.OS.DefWindowProc(OS.java:2544)
+	at org.eclipse.swt.widgets.Shell.callWindowProc(Shell.java:498)
+	at org.eclipse.swt.widgets.Control.windowProc(Control.java:4705)
+	at org.eclipse.swt.widgets.Canvas.windowProc(Canvas.java:339)
+	at org.eclipse.swt.widgets.Decorations.windowProc(Decorations.java:1626)
+	at org.eclipse.swt.widgets.Shell.windowProc(Shell.java:2075)
+	at org.eclipse.swt.widgets.Display.windowProc(Display.java:5023)
+	at org.eclipse.swt.internal.win32.OS.DispatchMessageW(Native Method)
+	at org.eclipse.swt.internal.win32.OS.DispatchMessage(OS.java:2549)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3759)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+Caused by: org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.swt.SWT.error(SWT.java:4441)
+	at org.eclipse.swt.SWT.error(SWT.java:4356)
+	at org.eclipse.swt.SWT.error(SWT.java:4327)
+	at org.eclipse.swt.widgets.Widget.error(Widget.java:476)
+	at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348)
+	at org.eclipse.swt.widgets.Shell.getSize(Shell.java:1092)
+	at org.eclipse.ui.internal.quickaccess.SearchField.storeDialog(SearchField.java:580)
+	at org.eclipse.ui.internal.quickaccess.SearchField.dispose(SearchField.java:557)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	... 88 more
+
+!ENTRY org.eclipse.e4.ui.workbench 4 0 2023-02-05 16:23:27.157
+!MESSAGE Exception occurred while unrendering: org.eclipse.e4.ui.model.application.ui.basic.impl.TrimmedWindowImpl@e5332 (elementId: IDEWindow, tags: [topLevel, shellMaximized], contributorURI: platform:/plugin/org.eclipse.ui.workbench) (widget: null, renderer: null, toBeRendered: true, onTop: false, visible: true, containerData: null, accessibilityPhrase: null) (label: %trimmedwindow.label.eclipseSDK, iconURI: null, tooltip: null, context: null, variables: [], x: 130, y: 130, width: 1024, height: 768)
+!STACK 0
+org.eclipse.e4.core.di.InjectionException: org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:62)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:888)
+	at org.eclipse.e4.core.internal.di.InjectorImpl.disposed(InjectorImpl.java:390)
+	at org.eclipse.e4.core.internal.di.Requestor.disposed(Requestor.java:143)
+	at org.eclipse.e4.core.internal.contexts.ContextObjectSupplier$ContextInjectionListener.update(ContextObjectSupplier.java:76)
+	at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.update(TrackableComputationExt.java:107)
+	at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.handleInvalid(TrackableComputationExt.java:70)
+	at org.eclipse.e4.core.internal.contexts.EclipseContext.dispose(EclipseContext.java:175)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.clearContext(PartRenderingEngine.java:974)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeRemoveGui(PartRenderingEngine.java:954)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$3(PartRenderingEngine.java:862)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$8.run(PartRenderingEngine.java:857)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.removeGui(PartRenderingEngine.java:841)
+	at org.eclipse.ui.internal.WorkbenchWindow.hardClose(WorkbenchWindow.java:1937)
+	at org.eclipse.ui.internal.WorkbenchWindow.busyClose(WorkbenchWindow.java:1560)
+	at org.eclipse.ui.internal.WorkbenchWindow.access$15(WorkbenchWindow.java:1527)
+	at org.eclipse.ui.internal.WorkbenchWindow$10.run(WorkbenchWindow.java:1592)
+	at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70)
+	at org.eclipse.ui.internal.WorkbenchWindow.close(WorkbenchWindow.java:1589)
+	at org.eclipse.ui.internal.Workbench$14.run(Workbench.java:1155)
+	at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42)
+	at org.eclipse.ui.internal.Workbench.busyClose(Workbench.java:1137)
+	at org.eclipse.ui.internal.Workbench.access$21(Workbench.java:1079)
+	at org.eclipse.ui.internal.Workbench$19.run(Workbench.java:1410)
+	at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70)
+	at org.eclipse.ui.internal.Workbench.close(Workbench.java:1407)
+	at org.eclipse.ui.internal.Workbench.close(Workbench.java:1380)
+	at org.eclipse.ui.internal.WorkbenchWindow.busyClose(WorkbenchWindow.java:1556)
+	at org.eclipse.ui.internal.WorkbenchWindow.access$15(WorkbenchWindow.java:1527)
+	at org.eclipse.ui.internal.WorkbenchWindow$10.run(WorkbenchWindow.java:1592)
+	at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70)
+	at org.eclipse.ui.internal.WorkbenchWindow.close(WorkbenchWindow.java:1589)
+	at org.eclipse.ui.internal.WorkbenchWindow.close(WorkbenchWindow.java:1603)
+	at org.eclipse.ui.internal.WorkbenchWindow$6.close(WorkbenchWindow.java:521)
+	at org.eclipse.e4.ui.workbench.renderers.swt.WBWRenderer$11.shellClosed(WBWRenderer.java:563)
+	at org.eclipse.swt.widgets.TypedListener.handleEvent(TypedListener.java:98)
+	at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84)
+	at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1085)
+	at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1070)
+	at org.eclipse.swt.widgets.Decorations.closeWidget(Decorations.java:308)
+	at org.eclipse.swt.widgets.Decorations.WM_CLOSE(Decorations.java:1696)
+	at org.eclipse.swt.widgets.Control.windowProc(Control.java:4612)
+	at org.eclipse.swt.widgets.Canvas.windowProc(Canvas.java:339)
+	at org.eclipse.swt.widgets.Decorations.windowProc(Decorations.java:1626)
+	at org.eclipse.swt.widgets.Shell.windowProc(Shell.java:2075)
+	at org.eclipse.swt.widgets.Display.windowProc(Display.java:5023)
+	at org.eclipse.swt.internal.win32.OS.DefWindowProcW(Native Method)
+	at org.eclipse.swt.internal.win32.OS.DefWindowProc(OS.java:2544)
+	at org.eclipse.swt.widgets.Shell.callWindowProc(Shell.java:498)
+	at org.eclipse.swt.widgets.Control.windowProc(Control.java:4705)
+	at org.eclipse.swt.widgets.Canvas.windowProc(Canvas.java:339)
+	at org.eclipse.swt.widgets.Decorations.windowProc(Decorations.java:1626)
+	at org.eclipse.swt.widgets.Shell.windowProc(Shell.java:2075)
+	at org.eclipse.swt.widgets.Display.windowProc(Display.java:5023)
+	at org.eclipse.swt.internal.win32.OS.DefWindowProcW(Native Method)
+	at org.eclipse.swt.internal.win32.OS.DefWindowProc(OS.java:2544)
+	at org.eclipse.swt.widgets.Shell.callWindowProc(Shell.java:498)
+	at org.eclipse.swt.widgets.Control.windowProc(Control.java:4705)
+	at org.eclipse.swt.widgets.Canvas.windowProc(Canvas.java:339)
+	at org.eclipse.swt.widgets.Decorations.windowProc(Decorations.java:1626)
+	at org.eclipse.swt.widgets.Shell.windowProc(Shell.java:2075)
+	at org.eclipse.swt.widgets.Display.windowProc(Display.java:5023)
+	at org.eclipse.swt.internal.win32.OS.DispatchMessageW(Native Method)
+	at org.eclipse.swt.internal.win32.OS.DispatchMessage(OS.java:2549)
+	at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3759)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032)
+	at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148)
+	at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636)
+	at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332)
+	at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579)
+	at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150)
+	at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135)
+	at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134)
+	at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380)
+	at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648)
+	at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603)
+	at org.eclipse.equinox.launcher.Main.run(Main.java:1465)
+Caused by: org.eclipse.swt.SWTException: Widget is disposed
+	at org.eclipse.swt.SWT.error(SWT.java:4441)
+	at org.eclipse.swt.SWT.error(SWT.java:4356)
+	at org.eclipse.swt.SWT.error(SWT.java:4327)
+	at org.eclipse.swt.widgets.Widget.error(Widget.java:476)
+	at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348)
+	at org.eclipse.swt.widgets.Shell.getSize(Shell.java:1092)
+	at org.eclipse.ui.internal.quickaccess.SearchField.storeDialog(SearchField.java:580)
+	at org.eclipse.ui.internal.quickaccess.SearchField.dispose(SearchField.java:557)
+	at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
+	at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
+	at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
+	at java.lang.reflect.Method.invoke(Unknown Source)
+	at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55)
+	... 88 more
diff --git a/Workspace/.metadata/.mylyn/.taskListIndex/segments.gen b/Workspace/.metadata/.mylyn/.taskListIndex/segments.gen
new file mode 100644
index 0000000..63a7ec9
Binary files /dev/null and b/Workspace/.metadata/.mylyn/.taskListIndex/segments.gen differ
diff --git a/Workspace/.metadata/.mylyn/.taskListIndex/segments_1 b/Workspace/.metadata/.mylyn/.taskListIndex/segments_1
new file mode 100644
index 0000000..2f75555
Binary files /dev/null and b/Workspace/.metadata/.mylyn/.taskListIndex/segments_1 differ
diff --git a/Workspace/.metadata/.mylyn/.tasks.xml.zip b/Workspace/.metadata/.mylyn/.tasks.xml.zip
new file mode 100644
index 0000000..9c6c0df
Binary files /dev/null and b/Workspace/.metadata/.mylyn/.tasks.xml.zip differ
diff --git a/Workspace/.metadata/.mylyn/repositories.xml.zip b/Workspace/.metadata/.mylyn/repositories.xml.zip
new file mode 100644
index 0000000..fecb78e
Binary files /dev/null and b/Workspace/.metadata/.mylyn/repositories.xml.zip differ
diff --git a/Workspace/.metadata/.mylyn/tasks.xml.zip b/Workspace/.metadata/.mylyn/tasks.xml.zip
new file mode 100644
index 0000000..9146680
Binary files /dev/null and b/Workspace/.metadata/.mylyn/tasks.xml.zip differ
diff --git a/Workspace/.metadata/.plugins/com.pemicro.debug.gdbjtag.pne/config.ini b/Workspace/.metadata/.plugins/com.pemicro.debug.gdbjtag.pne/config.ini
new file mode 100644
index 0000000..0d91ca0
--- /dev/null
+++ b/Workspace/.metadata/.plugins/com.pemicro.debug.gdbjtag.pne/config.ini
@@ -0,0 +1,7 @@
+[STARTUP]
+USE_CYCLONEPRO_RELAYS=0
+FORCE_MASS_ERASE=0
+
+[PEDEBUG]
+CURRENT_ALGORITHM_INDEX=0
+
diff --git a/Workspace/.metadata/.plugins/com.somniumtech.branding.kds/dialog_settings.xml b/Workspace/.metadata/.plugins/com.somniumtech.branding.kds/dialog_settings.xml
new file mode 100644
index 0000000..c22c5cb
--- /dev/null
+++ b/Workspace/.metadata/.plugins/com.somniumtech.branding.kds/dialog_settings.xml
@@ -0,0 +1,4 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<section name="Workbench">
+	<item value="true" key="FIRST_CLOSE_EMB_SYS_REG_VIEW"/>
+</section>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.core/.log b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/.log
new file mode 100644
index 0000000..c203ffc
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/.log
@@ -0,0 +1 @@
+*** SESSION Feb 05, 2023 15:27:11.49 -------------------------------------------
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.core/4part1.1675628907677.pdom b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/4part1.1675628907677.pdom
new file mode 100644
index 0000000..4ea2997
Binary files /dev/null and b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/4part1.1675628907677.pdom differ
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.core/4part1.language.settings.xml b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/4part1.language.settings.xml
new file mode 100644
index 0000000..9d13c2b
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/4part1.language.settings.xml
@@ -0,0 +1,2182 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1802811856" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector">
+				<language id="org.eclipse.cdt.core.gcc">
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/lib/gcc/arm-none-eabi/4.8.4/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/lib/gcc/arm-none-eabi/4.8.4/include-fixed">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/arm-none-eabi/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_EPSILON__" value="0x1P-15K">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_FBIT__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_MAX__" value="0X7FFFFFFFP-15K">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_MIN__" value="(-0X1P15K-0X1P15K)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__APCS_32__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARMEL__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_7EM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_EXT_IDIV__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_ISA_THUMB" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_PROFILE" value="77">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_EABI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_CLZ" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_DSP" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_FMA" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_LDREX" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_QBIT" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_SAT" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_SIMD32" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_UNALIGNED" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FP" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_NEON_FP" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_PCS_VFP" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_SIZEOF_MINIMAL_ENUM" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_SIZEOF_WCHAR_T" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQUIRE" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQ_REL" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_CONSUME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELAXED" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELEASE" value="3">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_SEQ_CST" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BIGGEST_ALIGNMENT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BYTE_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR_BIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DA_FBIT__" value="31">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DA_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DENORM_MIN__" value="((double)4.9406564584124654e-324L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_EPSILON__" value="((double)2.2204460492503131e-16L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_10_EXP__" value="308">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX__" value="((double)1.7976931348623157e+308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_10_EXP__" value="(-307)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN__" value="((double)2.2250738585072014e-308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_EPSILON__" value="1E-33DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MANT_DIG__" value="34">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX_EXP__" value="6145">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX__" value="9.999999999999999999999999999999999E6144DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN_EXP__" value="(-6142)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN__" value="1E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__DEC128_SUBNORMAL_MIN__" value="0.000000000000000000000000000000001E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__DEC32_EPSILON__" value="1E-6DF">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__DEC32_MANT_DIG__" value="7">
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+					<entry kind="macro" name="__DEC32_MAX_EXP__" value="97">
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+					<entry kind="macro" name="__DEC32_MAX__" value="9.999999E96DF">
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+					</entry>
+					<entry kind="macro" name="__DEC32_MIN_EXP__" value="(-94)">
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+					<entry kind="macro" name="__DEC32_MIN__" value="1E-95DF">
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+					<entry kind="macro" name="__DEC32_SUBNORMAL_MIN__" value="0.000001E-95DF">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__DEC64_EPSILON__" value="1E-15DD">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__DEC64_MANT_DIG__" value="16">
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+					<entry kind="macro" name="__DEC64_MAX_EXP__" value="385">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__DEC64_MAX__" value="9.999999999999999E384DD">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__DEC64_MIN_EXP__" value="(-382)">
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+					<entry kind="macro" name="__DEC64_MIN__" value="1E-383DD">
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+					<entry kind="macro" name="__DEC64_SUBNORMAL_MIN__" value="0.000000000000001E-383DD">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__DECIMAL_DIG__" value="17">
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+					<entry kind="macro" name="__DEC_EVAL_METHOD__" value="2">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__DQ_FBIT__" value="63">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__DQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ELF__" value="1">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__FINITE_MATH_ONLY__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__FLOAT_WORD_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__FLT_DECIMAL_DIG__" value="9">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__FLT_DENORM_MIN__" value="1.4012984643248171e-45F">
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+					<entry kind="macro" name="__FLT_DIG__" value="6">
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+					<entry kind="macro" name="__FLT_EPSILON__" value="1.1920928955078125e-7F">
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+					<entry kind="macro" name="__FLT_EVAL_METHOD__" value="0">
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+					<entry kind="macro" name="__FLT_HAS_DENORM__" value="1">
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+					<entry kind="macro" name="__FLT_RADIX__" value="2">
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+					<entry kind="macro" name="__FP_FAST_FMAF" value="1">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__FRACT_EPSILON__" value="0x1P-15R">
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+					<entry kind="macro" name="__INT8_TYPE__" value="signed char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__INTMAX_C(c)" value="c ## LL">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__INTMAX_MAX__" value="9223372036854775807LL">
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+					<entry kind="macro" name="__INTMAX_TYPE__" value="long long int">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__INTPTR_MAX__" value="2147483647">
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__INT_FAST16_MAX__" value="2147483647">
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+					</entry>
+					<entry kind="macro" name="__INT_FAST64_MAX__" value="9223372036854775807LL">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__LDBL_MIN_10_EXP__" value="(-307)">
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+					<entry kind="macro" name="__LDBL_MIN_EXP__" value="(-1021)">
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+					<entry kind="macro" name="__LFRACT_MIN__" value="(-0.5LR-0.5LR)">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__LLACCUM_EPSILON__" value="0x1P-31LLK">
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+					<entry kind="macro" name="__STDC__" value="1">
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_LONG_LONG__" value="8">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_LONG__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_POINTER__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_PTRDIFF_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_SHORT__" value="2">
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+					<entry kind="macro" name="__SIZEOF_SIZE_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_WCHAR_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_WINT_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZE_MAX__" value="4294967295U">
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+					<entry kind="macro" name="__SIZE_TYPE__" value="unsigned int">
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+					<entry kind="macro" name="__STDC_HOSTED__" value="1">
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__TQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UACCUM_EPSILON__" value="0x1P-16UK">
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+					<entry kind="macro" name="__UACCUM_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UACCUM_MAX__" value="0XFFFFFFFFP-16UK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_MIN__" value="0.0UK">
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+					<entry kind="macro" name="__UDA_IBIT__" value="32">
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+					<entry kind="macro" name="__UDQ_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UDQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UFRACT_EPSILON__" value="0x1P-16UR">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UFRACT_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UFRACT_MAX__" value="0XFFFFP-16UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_MIN__" value="0.0UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHA_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHA_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHQ_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UHQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_C(c)" value="c ## UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_EPSILON__" value="0x1P-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MIN__" value="0.0ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_EPSILON__" value="0x1P-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULFRACT_MAX__" value="0XFFFFFFFFP-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_MIN__" value="0.0ULR">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULLACCUM_EPSILON__" value="0x1P-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULLACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULLACCUM_MIN__" value="0.0ULLK">
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+					<entry kind="macro" name="__ULLFRACT_EPSILON__" value="0x1P-64ULLR">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULLFRACT_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULLFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULLFRACT_MAX__" value="0XFFFFFFFFFFFFFFFFP-64ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_MIN__" value="0.0ULLR">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UQQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_EPSILON__" value="0x1P-8UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__USACCUM_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_MAX__" value="0XFFFFP-8UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_MIN__" value="0.0UHK">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__USA_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__USA_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__USER_LABEL_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__USES_INITFINI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__USFRACT_EPSILON__" value="0x1P-8UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_MAX__" value="0XFFP-8UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_MIN__" value="0.0UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USQ_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTA_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTA_IBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTQ_FBIT__" value="128">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VERSION__" value="&quot;4.8.4 20140725 (release) [ARM/embedded-4_8-branch revision 213147]&quot;">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VFP_FP__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_UNSIGNED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__arm__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cplusplus" value="201103L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__thumb2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__thumb__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+				</language>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.core/GPIO.1675629487635.pdom b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/GPIO.1675629487635.pdom
new file mode 100644
index 0000000..e17e1d8
Binary files /dev/null and b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/GPIO.1675629487635.pdom differ
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.core/GPIO.language.settings.xml b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/GPIO.language.settings.xml
new file mode 100644
index 0000000..9932c09
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/GPIO.language.settings.xml
@@ -0,0 +1,2182 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector">
+				<language id="org.eclipse.cdt.core.gcc">
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/lib/gcc/arm-none-eabi/4.8.4/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/lib/gcc/arm-none-eabi/4.8.4/include-fixed">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/arm-none-eabi/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_EPSILON__" value="0x1P-15K">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_FBIT__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_MAX__" value="0X7FFFFFFFP-15K">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_MIN__" value="(-0X1P15K-0X1P15K)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__APCS_32__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARMEL__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_7EM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_EXT_IDIV__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_ISA_THUMB" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_PROFILE" value="77">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_EABI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_CLZ" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_DSP" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_FMA" value="1">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__LDBL_EPSILON__" value="2.2204460492503131e-16L">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__LDBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX_10_EXP__" value="308">
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+					</entry>
+					<entry kind="macro" name="__LDBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX__" value="1.7976931348623157e+308L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN_10_EXP__" value="(-307)">
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+					</entry>
+					<entry kind="macro" name="__LDBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__LDBL_MIN__" value="2.2250738585072014e-308L">
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+					<entry kind="macro" name="__LFRACT_EPSILON__" value="0x1P-31LR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LFRACT_FBIT__" value="31">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__LFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__LFRACT_MAX__" value="0X7FFFFFFFP-31LR">
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+					<entry kind="macro" name="__LFRACT_MIN__" value="(-0.5LR-0.5LR)">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__LLACCUM_EPSILON__" value="0x1P-31LLK">
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+					</entry>
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+					<entry kind="macro" name="__LONG_LONG_MAX__" value="9223372036854775807LL">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__LONG_MAX__" value="2147483647L">
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+					<entry kind="macro" name="__NO_INLINE__" value="1">
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+					<entry kind="macro" name="__ORDER_BIG_ENDIAN__" value="4321">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ORDER_LITTLE_ENDIAN__" value="1234">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ORDER_PDP_ENDIAN__" value="3412">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__PRAGMA_REDEFINE_EXTNAME" value="1">
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+					<entry kind="macro" name="__PTRDIFF_MAX__" value="2147483647">
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+					<entry kind="macro" name="__PTRDIFF_TYPE__" value="int">
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+					<entry kind="macro" name="__QQ_FBIT__" value="7">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__QQ_IBIT__" value="0">
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+					<entry kind="macro" name="__REGISTER_PREFIX__" value="">
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SACCUM_MAX__" value="0X7FFFP-7HK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_MIN__" value="(-0X1P7HK-0X1P7HK)">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SA_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SCHAR_MAX__" value="127">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SFRACT_EPSILON__" value="0x1P-7HR">
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+					<entry kind="macro" name="__SFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SFRACT_MIN__" value="(-0.5HR-0.5HR)">
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+					<entry kind="macro" name="__SHRT_MAX__" value="32767">
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIG_ATOMIC_MIN__" value="(-__SIG_ATOMIC_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIG_ATOMIC_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_FLOAT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_INT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_LONG_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_LONG_LONG__" value="8">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_POINTER__" value="4">
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+					<entry kind="macro" name="__SIZEOF_PTRDIFF_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_SIZE_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_WCHAR_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_WINT_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZE_MAX__" value="4294967295U">
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+					<entry kind="macro" name="__SIZE_TYPE__" value="unsigned int">
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+					<entry kind="macro" name="__SQ_FBIT__" value="31">
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+					<entry kind="macro" name="__SQ_IBIT__" value="0">
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+					<entry kind="macro" name="__STDC_HOSTED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_VERSION__" value="199901L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC__" value="1">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__STRICT_ANSI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__TA_FBIT__" value="63">
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__THUMBEL__" value="1">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__THUMB_INTERWORK__" value="1">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__TQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UACCUM_EPSILON__" value="0x1P-16UK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UACCUM_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UACCUM_MAX__" value="0XFFFFFFFFP-16UK">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UACCUM_MIN__" value="0.0UK">
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+					<entry kind="macro" name="__UDA_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UDQ_IBIT__" value="0">
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+					<entry kind="macro" name="__UFRACT_EPSILON__" value="0x1P-16UR">
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+					<entry kind="macro" name="__UFRACT_MIN__" value="0.0UR">
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UHA_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UHQ_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UHQ_IBIT__" value="0">
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+					<entry kind="macro" name="__UINT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT32_C(c)" value="c ## UL">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINTMAX_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINTMAX_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_FAST16_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_FAST16_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_FAST32_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_FAST32_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_FAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_FAST8_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_FAST8_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_LEAST16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_LEAST32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_LEAST32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_LEAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_LEAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT_LEAST8_MAX__" value="255">
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULK">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULACCUM_MIN__" value="0.0ULK">
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULFRACT_MIN__" value="0.0ULR">
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+					<entry kind="macro" name="__ULLACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULLACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULLACCUM_MIN__" value="0.0ULLK">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULLFRACT_EPSILON__" value="0x1P-64ULLR">
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+					<entry kind="macro" name="__ULLFRACT_FBIT__" value="64">
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+					<entry kind="macro" name="__ULLFRACT_IBIT__" value="0">
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+					<entry kind="macro" name="__ULLFRACT_MAX__" value="0XFFFFFFFFFFFFFFFFP-64ULLR">
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UFRACT_EPSILON__" value="0x1P-16UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_MAX__" value="0XFFFFP-16UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_MIN__" value="0.0UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHA_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHA_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHQ_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_C(c)" value="c ## UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_EPSILON__" value="0x1P-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MIN__" value="0.0ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_EPSILON__" value="0x1P-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_MAX__" value="0XFFFFFFFFP-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_MIN__" value="0.0ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_EPSILON__" value="0x1P-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_MIN__" value="0.0ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_EPSILON__" value="0x1P-64ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_MAX__" value="0XFFFFFFFFFFFFFFFFP-64ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_MIN__" value="0.0ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UQQ_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UQQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_EPSILON__" value="0x1P-8UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_MAX__" value="0XFFFFP-8UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_MIN__" value="0.0UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USA_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USA_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USER_LABEL_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USES_INITFINI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_EPSILON__" value="0x1P-8UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_MAX__" value="0XFFP-8UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_MIN__" value="0.0UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USQ_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTA_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTA_IBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTQ_FBIT__" value="128">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VERSION__" value="&quot;4.8.4 20140725 (release) [ARM/embedded-4_8-branch revision 213147]&quot;">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VFP_FP__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_UNSIGNED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__arm__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cplusplus" value="201103L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__thumb2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__thumb__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+				</language>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.core/Interrupt.1675630599866.pdom b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/Interrupt.1675630599866.pdom
new file mode 100644
index 0000000..bc30598
Binary files /dev/null and b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/Interrupt.1675630599866.pdom differ
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.core/Interrupt.language.settings.xml b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/Interrupt.language.settings.xml
new file mode 100644
index 0000000..9932c09
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/Interrupt.language.settings.xml
@@ -0,0 +1,2182 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector">
+				<language id="org.eclipse.cdt.core.gcc">
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/lib/gcc/arm-none-eabi/4.8.4/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/lib/gcc/arm-none-eabi/4.8.4/include-fixed">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/arm-none-eabi/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_EPSILON__" value="0x1P-15K">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_FBIT__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_MAX__" value="0X7FFFFFFFP-15K">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_MIN__" value="(-0X1P15K-0X1P15K)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__APCS_32__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARMEL__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_7EM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_EXT_IDIV__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_ISA_THUMB" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_PROFILE" value="77">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_EABI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_CLZ" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_DSP" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_FMA" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_LDREX" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_QBIT" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_SAT" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_SIMD32" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_UNALIGNED" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FP" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_NEON_FP" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_PCS_VFP" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_SIZEOF_MINIMAL_ENUM" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_SIZEOF_WCHAR_T" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQUIRE" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQ_REL" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_CONSUME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELAXED" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELEASE" value="3">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_SEQ_CST" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BIGGEST_ALIGNMENT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BYTE_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR_BIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DA_FBIT__" value="31">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DA_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DENORM_MIN__" value="((double)4.9406564584124654e-324L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_EPSILON__" value="((double)2.2204460492503131e-16L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__LONG_LONG_MAX__" value="9223372036854775807LL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_MAX__" value="2147483647L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NO_INLINE__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_BIG_ENDIAN__" value="4321">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_LITTLE_ENDIAN__" value="1234">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_PDP_ENDIAN__" value="3412">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PRAGMA_REDEFINE_EXTNAME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_MAX__" value="2147483647">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__QQ_FBIT__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__QQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__REGISTER_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_EPSILON__" value="0x1P-7HK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_FBIT__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_MAX__" value="0X7FFFP-7HK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_MIN__" value="(-0X1P7HK-0X1P7HK)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SA_FBIT__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SA_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SCHAR_MAX__" value="127">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_EPSILON__" value="0x1P-7HR">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SFRACT_FBIT__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_MAX__" value="0X7FP-7HR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_MIN__" value="(-0.5HR-0.5HR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SHRT_MAX__" value="32767">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MAX__" value="2147483647">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MIN__" value="(-__SIG_ATOMIC_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_FLOAT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_INT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_LONG__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_POINTER__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_PTRDIFF_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SHORT__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SIZE_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WCHAR_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WINT_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SQ_FBIT__" value="31">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_HOSTED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_VERSION__" value="199901L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STRICT_ANSI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__TA_FBIT__" value="63">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__TA_IBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__THUMBEL__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__THUMB_INTERWORK__" value="1">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__TQ_FBIT__" value="127">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__TQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_EPSILON__" value="0x1P-16UK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_MAX__" value="0XFFFFFFFFP-16UK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_MIN__" value="0.0UK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UDA_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UDA_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UDQ_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UDQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_EPSILON__" value="0x1P-16UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UFRACT_MAX__" value="0XFFFFP-16UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_MIN__" value="0.0UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHA_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UHA_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UHQ_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UHQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINT16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_C(c)" value="c ## UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_EPSILON__" value="0x1P-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MIN__" value="0.0ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_EPSILON__" value="0x1P-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_MAX__" value="0XFFFFFFFFP-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_MIN__" value="0.0ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_EPSILON__" value="0x1P-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_MIN__" value="0.0ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_EPSILON__" value="0x1P-64ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_MAX__" value="0XFFFFFFFFFFFFFFFFP-64ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_MIN__" value="0.0ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UQQ_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UQQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_EPSILON__" value="0x1P-8UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_MAX__" value="0XFFFFP-8UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_MIN__" value="0.0UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USA_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USA_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USER_LABEL_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USES_INITFINI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_EPSILON__" value="0x1P-8UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_MAX__" value="0XFFP-8UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_MIN__" value="0.0UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USQ_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTA_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTA_IBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTQ_FBIT__" value="128">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VERSION__" value="&quot;4.8.4 20140725 (release) [ARM/embedded-4_8-branch revision 213147]&quot;">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VFP_FP__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__INT8_TYPE__" value="signed char">
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+					<entry kind="macro" name="__INTMAX_C(c)" value="c ## LL">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__INTPTR_TYPE__" value="int">
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+					<entry kind="macro" name="__LDBL_DENORM_MIN__" value="4.9406564584124654e-324L">
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+					<entry kind="macro" name="__LDBL_MIN_10_EXP__" value="(-307)">
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_EPSILON__" value="0x1P-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MIN__" value="0.0ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_EPSILON__" value="0x1P-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_MAX__" value="0XFFFFFFFFP-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_MIN__" value="0.0ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_EPSILON__" value="0x1P-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_MIN__" value="0.0ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_EPSILON__" value="0x1P-64ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_MAX__" value="0XFFFFFFFFFFFFFFFFP-64ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_MIN__" value="0.0ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UQQ_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UQQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_EPSILON__" value="0x1P-8UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_MAX__" value="0XFFFFP-8UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_MIN__" value="0.0UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USA_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USA_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USER_LABEL_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USES_INITFINI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_EPSILON__" value="0x1P-8UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_MAX__" value="0XFFP-8UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_MIN__" value="0.0UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USQ_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTA_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTA_IBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTQ_FBIT__" value="128">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VERSION__" value="&quot;4.8.4 20140725 (release) [ARM/embedded-4_8-branch revision 213147]&quot;">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VFP_FP__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_UNSIGNED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__arm__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cplusplus" value="201103L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__thumb2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__thumb__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+				</language>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.core/UART.1675631402766.pdom b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/UART.1675631402766.pdom
new file mode 100644
index 0000000..e5db028
Binary files /dev/null and b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/UART.1675631402766.pdom differ
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.core/UART.language.settings.xml b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/UART.language.settings.xml
new file mode 100644
index 0000000..9932c09
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/UART.language.settings.xml
@@ -0,0 +1,2182 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector">
+				<language id="org.eclipse.cdt.core.gcc">
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/lib/gcc/arm-none-eabi/4.8.4/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/lib/gcc/arm-none-eabi/4.8.4/include-fixed">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/arm-none-eabi/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_EPSILON__" value="0x1P-15K">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_FBIT__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_MAX__" value="0X7FFFFFFFP-15K">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_MIN__" value="(-0X1P15K-0X1P15K)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__APCS_32__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARMEL__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_7EM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_EXT_IDIV__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_ISA_THUMB" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_PROFILE" value="77">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_EABI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_CLZ" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_DSP" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_FMA" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_LDREX" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_QBIT" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_SAT" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_SIMD32" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_UNALIGNED" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FP" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_NEON_FP" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_PCS_VFP" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_SIZEOF_MINIMAL_ENUM" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_SIZEOF_WCHAR_T" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQUIRE" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQ_REL" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_CONSUME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELAXED" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELEASE" value="3">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_SEQ_CST" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BIGGEST_ALIGNMENT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BYTE_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR_BIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DA_FBIT__" value="31">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DA_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DENORM_MIN__" value="((double)4.9406564584124654e-324L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_EPSILON__" value="((double)2.2204460492503131e-16L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_10_EXP__" value="308">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX__" value="((double)1.7976931348623157e+308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_10_EXP__" value="(-307)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN__" value="((double)2.2250738585072014e-308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_EPSILON__" value="1E-33DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MANT_DIG__" value="34">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX_EXP__" value="6145">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX__" value="9.999999999999999999999999999999999E6144DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN_EXP__" value="(-6142)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN__" value="1E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_SUBNORMAL_MIN__" value="0.000000000000000000000000000000001E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_EPSILON__" value="1E-6DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MANT_DIG__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MAX_EXP__" value="97">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MAX__" value="9.999999E96DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MIN_EXP__" value="(-94)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MIN__" value="1E-95DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_SUBNORMAL_MIN__" value="0.000001E-95DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_EPSILON__" value="1E-15DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MANT_DIG__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MAX_EXP__" value="385">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MAX__" value="9.999999999999999E384DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MIN_EXP__" value="(-382)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MIN__" value="1E-383DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_SUBNORMAL_MIN__" value="0.000000000000001E-383DD">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__FLOAT_WORD_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LACCUM_FBIT__" value="31">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LACCUM_MAX__" value="0X7FFFFFFFFFFFFFFFP-31LK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LACCUM_MIN__" value="(-0X1P31LK-0X1P31LK)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_DENORM_MIN__" value="4.9406564584124654e-324L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_EPSILON__" value="2.2204460492503131e-16L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX_10_EXP__" value="308">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MAX__" value="1.7976931348623157e+308L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN_10_EXP__" value="(-307)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LDBL_MIN__" value="2.2250738585072014e-308L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LFRACT_EPSILON__" value="0x1P-31LR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LFRACT_FBIT__" value="31">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LFRACT_MAX__" value="0X7FFFFFFFP-31LR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LFRACT_MIN__" value="(-0.5LR-0.5LR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLACCUM_EPSILON__" value="0x1P-31LLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLACCUM_FBIT__" value="31">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLACCUM_MAX__" value="0X7FFFFFFFFFFFFFFFP-31LLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLACCUM_MIN__" value="(-0X1P31LLK-0X1P31LLK)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLFRACT_EPSILON__" value="0x1P-63LLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLFRACT_FBIT__" value="63">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLFRACT_MAX__" value="0X7FFFFFFFFFFFFFFFP-63LLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLFRACT_MIN__" value="(-0.5LLR-0.5LLR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_LONG_MAX__" value="9223372036854775807LL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_MAX__" value="2147483647L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NO_INLINE__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_BIG_ENDIAN__" value="4321">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_LITTLE_ENDIAN__" value="1234">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_PDP_ENDIAN__" value="3412">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PRAGMA_REDEFINE_EXTNAME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_MAX__" value="2147483647">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__QQ_FBIT__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__QQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__REGISTER_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_EPSILON__" value="0x1P-7HK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_FBIT__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_MAX__" value="0X7FFFP-7HK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_MIN__" value="(-0X1P7HK-0X1P7HK)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SA_FBIT__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SA_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SCHAR_MAX__" value="127">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_EPSILON__" value="0x1P-7HR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_FBIT__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_MAX__" value="0X7FP-7HR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_MIN__" value="(-0.5HR-0.5HR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SHRT_MAX__" value="32767">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MAX__" value="2147483647">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MIN__" value="(-__SIG_ATOMIC_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_FLOAT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_INT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_LONG__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_POINTER__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_PTRDIFF_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SHORT__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SIZE_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WCHAR_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WINT_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SQ_FBIT__" value="31">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_HOSTED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__TA_FBIT__" value="63">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__TA_IBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__THUMBEL__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__THUMB_INTERWORK__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__TQ_FBIT__" value="127">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__TQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_EPSILON__" value="0x1P-16UK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_MAX__" value="0XFFFFFFFFP-16UK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_MIN__" value="0.0UK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UDA_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UDA_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UDQ_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UDQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_EPSILON__" value="0x1P-16UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_MAX__" value="0XFFFFP-16UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_MIN__" value="0.0UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHA_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHA_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHQ_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_C(c)" value="c ## UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_EPSILON__" value="0x1P-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MIN__" value="0.0ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_EPSILON__" value="0x1P-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_MAX__" value="0XFFFFFFFFP-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_MIN__" value="0.0ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_EPSILON__" value="0x1P-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_MIN__" value="0.0ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_EPSILON__" value="0x1P-64ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_MAX__" value="0XFFFFFFFFFFFFFFFFP-64ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_MIN__" value="0.0ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UQQ_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UQQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_EPSILON__" value="0x1P-8UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_MAX__" value="0XFFFFP-8UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_MIN__" value="0.0UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USA_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USA_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USER_LABEL_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USES_INITFINI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_EPSILON__" value="0x1P-8UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_MAX__" value="0XFFP-8UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_MIN__" value="0.0UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USQ_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTA_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTA_IBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTQ_FBIT__" value="128">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VERSION__" value="&quot;4.8.4 20140725 (release) [ARM/embedded-4_8-branch revision 213147]&quot;">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VFP_FP__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_UNSIGNED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__arm__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cplusplus" value="201103L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__thumb2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__thumb__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+				</language>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.core/ksdk_platform_lib_K64F12.1675628859594.pdom b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/ksdk_platform_lib_K64F12.1675628859594.pdom
new file mode 100644
index 0000000..0db3a4f
Binary files /dev/null and b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/ksdk_platform_lib_K64F12.1675628859594.pdom differ
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.core/ksdk_platform_lib_K64F12.language.settings.xml b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/ksdk_platform_lib_K64F12.language.settings.xml
new file mode 100644
index 0000000..4b7fc3d
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/ksdk_platform_lib_K64F12.language.settings.xml
@@ -0,0 +1,4367 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.lib.debug.660039418" name="debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector">
+				<language id="org.eclipse.cdt.core.gcc">
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/lib/gcc/arm-none-eabi/4.8.4/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/lib/gcc/arm-none-eabi/4.8.4/include-fixed">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="includePath" name="C:/Freescale/KDS_v3/Toolchain/arm-none-eabi/include">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_EPSILON__" value="0x1P-15K">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_FBIT__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_MAX__" value="0X7FFFFFFFP-15K">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ACCUM_MIN__" value="(-0X1P15K-0X1P15K)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__APCS_32__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARMEL__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_7EM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_EXT_IDIV__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_ISA_THUMB" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_ARCH_PROFILE" value="77">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_EABI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_CLZ" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_DSP" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_FMA" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_LDREX" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_QBIT" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_SAT" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_SIMD32" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FEATURE_UNALIGNED" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_FP" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_NEON_FP" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_PCS_VFP" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_SIZEOF_MINIMAL_ENUM" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ARM_SIZEOF_WCHAR_T" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQUIRE" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_ACQ_REL" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_CONSUME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELAXED" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_RELEASE" value="3">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ATOMIC_SEQ_CST" value="5">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BIGGEST_ALIGNMENT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__BYTE_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__CHAR_BIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DA_FBIT__" value="31">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DA_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DENORM_MIN__" value="((double)4.9406564584124654e-324L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_DIG__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_EPSILON__" value="((double)2.2204460492503131e-16L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MANT_DIG__" value="53">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_10_EXP__" value="308">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX_EXP__" value="1024">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MAX__" value="((double)1.7976931348623157e+308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_10_EXP__" value="(-307)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN_EXP__" value="(-1021)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DBL_MIN__" value="((double)2.2250738585072014e-308L)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_EPSILON__" value="1E-33DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MANT_DIG__" value="34">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX_EXP__" value="6145">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MAX__" value="9.999999999999999999999999999999999E6144DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN_EXP__" value="(-6142)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_MIN__" value="1E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC128_SUBNORMAL_MIN__" value="0.000000000000000000000000000000001E-6143DL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_EPSILON__" value="1E-6DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MANT_DIG__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MAX_EXP__" value="97">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MAX__" value="9.999999E96DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MIN_EXP__" value="(-94)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_MIN__" value="1E-95DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC32_SUBNORMAL_MIN__" value="0.000001E-95DF">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_EPSILON__" value="1E-15DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MANT_DIG__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MAX_EXP__" value="385">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MAX__" value="9.999999999999999E384DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MIN_EXP__" value="(-382)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_MIN__" value="1E-383DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC64_SUBNORMAL_MIN__" value="0.000000000000001E-383DD">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DECIMAL_DIG__" value="17">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DEC_EVAL_METHOD__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DQ_FBIT__" value="63">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__DQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ELF__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FINITE_MATH_ONLY__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLOAT_WORD_ORDER__" value="__ORDER_LITTLE_ENDIAN__">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DECIMAL_DIG__" value="9">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DENORM_MIN__" value="1.4012984643248171e-45F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_DIG__" value="6">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_EPSILON__" value="1.1920928955078125e-7F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_EVAL_METHOD__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_DENORM__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_INFINITY__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_HAS_QUIET_NAN__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MANT_DIG__" value="24">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX_10_EXP__" value="38">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX_EXP__" value="128">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MAX__" value="3.4028234663852886e+38F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN_10_EXP__" value="(-37)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN_EXP__" value="(-125)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_MIN__" value="1.1754943508222875e-38F">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FLT_RADIX__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FP_FAST_FMAF" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FRACT_EPSILON__" value="0x1P-15R">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FRACT_FBIT__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__FRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__LLACCUM_MAX__" value="0X7FFFFFFFFFFFFFFFP-31LLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLACCUM_MIN__" value="(-0X1P31LLK-0X1P31LLK)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLFRACT_EPSILON__" value="0x1P-63LLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLFRACT_FBIT__" value="63">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLFRACT_MAX__" value="0X7FFFFFFFFFFFFFFFP-63LLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LLFRACT_MIN__" value="(-0.5LLR-0.5LLR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_LONG_MAX__" value="9223372036854775807LL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__LONG_MAX__" value="2147483647L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__NO_INLINE__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_BIG_ENDIAN__" value="4321">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_LITTLE_ENDIAN__" value="1234">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ORDER_PDP_ENDIAN__" value="3412">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PRAGMA_REDEFINE_EXTNAME" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_MAX__" value="2147483647">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__PTRDIFF_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__QQ_FBIT__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__QQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__REGISTER_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_EPSILON__" value="0x1P-7HK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_FBIT__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_MAX__" value="0X7FFFP-7HK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SACCUM_MIN__" value="(-0X1P7HK-0X1P7HK)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SA_FBIT__" value="15">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SA_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SCHAR_MAX__" value="127">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_EPSILON__" value="0x1P-7HR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_FBIT__" value="7">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_MAX__" value="0X7FP-7HR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SFRACT_MIN__" value="(-0.5HR-0.5HR)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SHRT_MAX__" value="32767">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MAX__" value="2147483647">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_MIN__" value="(-__SIG_ATOMIC_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_FLOAT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_INT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG_LONG__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_POINTER__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_PTRDIFF_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SHORT__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SIZE_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WCHAR_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_WINT_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SQ_FBIT__" value="31">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC_HOSTED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__STDC__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__TA_FBIT__" value="63">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__TA_IBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__THUMBEL__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__THUMB_INTERWORK__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__TQ_FBIT__" value="127">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__TQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_EPSILON__" value="0x1P-16UK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_MAX__" value="0XFFFFFFFFP-16UK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UACCUM_MIN__" value="0.0UK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UDA_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UDA_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UDQ_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UDQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_EPSILON__" value="0x1P-16UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_MAX__" value="0XFFFFP-16UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UFRACT_MIN__" value="0.0UR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHA_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHA_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHQ_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_C(c)" value="c ## UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_C(c)" value="c">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTPTR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_EPSILON__" value="0x1P-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MIN__" value="0.0ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_EPSILON__" value="0x1P-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_MAX__" value="0XFFFFFFFFP-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_MIN__" value="0.0ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_EPSILON__" value="0x1P-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLACCUM_MIN__" value="0.0ULLK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_EPSILON__" value="0x1P-64ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_MAX__" value="0XFFFFFFFFFFFFFFFFP-64ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULLFRACT_MIN__" value="0.0ULLR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UQQ_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UQQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_EPSILON__" value="0x1P-8UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_MAX__" value="0XFFFFP-8UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USACCUM_MIN__" value="0.0UHK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USA_FBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USA_IBIT__" value="16">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USER_LABEL_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USES_INITFINI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_EPSILON__" value="0x1P-8UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_FBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_MAX__" value="0XFFP-8UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USFRACT_MIN__" value="0.0UHR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USQ_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__USQ_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTA_FBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTA_IBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTQ_FBIT__" value="128">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UTQ_IBIT__" value="0">
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIG_ATOMIC_MIN__" value="(-__SIG_ATOMIC_MAX__ - 1)">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIG_ATOMIC_TYPE__" value="int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_FLOAT__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_LONG_DOUBLE__" value="8">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_LONG__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_POINTER__" value="4">
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+					</entry>
+					<entry kind="macro" name="__SIZEOF_PTRDIFF_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SHORT__" value="2">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZEOF_SIZE_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZEOF_WCHAR_T__" value="4">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__SIZE_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__SIZE_TYPE__" value="unsigned int">
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+					</entry>
+					<entry kind="macro" name="__STDC__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__TA_FBIT__" value="63">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+					</entry>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UDA_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UFRACT_MIN__" value="0.0UR">
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UHA_IBIT__" value="8">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT32_C(c)" value="c ## UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+					</entry>
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+					</entry>
+					<entry kind="macro" name="__UINT64_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+					</entry>
+					<entry kind="macro" name="__UINT8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_C(c)" value="c ## ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINTMAX_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__UINTPTR_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST16_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST32_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_FAST8_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_MAX__" value="65535">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST16_TYPE__" value="short unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_MAX__" value="4294967295UL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST32_TYPE__" value="long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_MAX__" value="18446744073709551615ULL">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST64_TYPE__" value="long long unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_MAX__" value="255">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__UINT_LEAST8_TYPE__" value="unsigned char">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_EPSILON__" value="0x1P-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_IBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MAX__" value="0XFFFFFFFFFFFFFFFFP-32ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULACCUM_MIN__" value="0.0ULK">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_EPSILON__" value="0x1P-32ULR">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_FBIT__" value="32">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_IBIT__" value="0">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__ULFRACT_MAX__" value="0XFFFFFFFFP-32ULR">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__ULFRACT_MIN__" value="0.0ULR">
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__USER_LABEL_PREFIX__" value="">
+						<flag value="BUILTIN|READONLY"/>
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+					<entry kind="macro" name="__USES_INITFINI__" value="1">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
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+					<entry kind="macro" name="__UTA_IBIT__" value="64">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__VERSION__" value="&quot;4.8.4 20140725 (release) [ARM/embedded-4_8-branch revision 213147]&quot;">
+						<flag value="BUILTIN|READONLY"/>
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+						<flag value="BUILTIN|READONLY"/>
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+					</entry>
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+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WCHAR_UNSIGNED__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MAX__" value="4294967295U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_MIN__" value="0U">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__WINT_TYPE__" value="unsigned int">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__arm__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__cplusplus" value="201103L">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__thumb2__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+					<entry kind="macro" name="__thumb__" value="1">
+						<flag value="BUILTIN|READONLY"/>
+					</entry>
+				</language>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml
new file mode 100644
index 0000000..c4b91cf
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.core/shareddefaults.xml
@@ -0,0 +1 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?><SharedRoot><SharedProperty id="" value=""/></SharedRoot>
\ No newline at end of file
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c b/Workspace/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c
@@ -0,0 +1 @@
+
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp b/Workspace/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp
@@ -0,0 +1 @@
+
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.managedbuilder.core/spec.c b/Workspace/.metadata/.plugins/org.eclipse.cdt.managedbuilder.core/spec.c
new file mode 100644
index 0000000..e69de29
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/4part1.build.log b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/4part1.build.log
new file mode 100644
index 0000000..8bb9d66
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/4part1.build.log
@@ -0,0 +1,124 @@
+15:29:10 **** Build of configuration Debug for project 4part1 ****
+make all 
+Building file: ../Sources/main.c
+Invoking: Cross ARM C Compiler
+arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"C:\Freescale\KSDK_1.3.0/platform/hal/inc" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"Sources/main.d" -MT"Sources/main.o" -c -o "Sources/main.o" "../Sources/main.c"
+../Sources/main.c: In function 'main':
+../Sources/main.c:26:3: warning: passing argument 1 of 'SIM_HAL_EnableClock' makes pointer from integer without a cast [enabled by default]
+   SIM_HAL_EnableClock(SIM_BASE, kSimClockGatePortE); // Enable Port E Clock Gate
+   ^
+In file included from C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_sim_hal.h:135:0,
+                 from ../Sources/main.c:3:
+c:\freescale\ksdk_1.3.0\platform\hal\src\sim\mk64f12\fsl_sim_hal_mk64f12.h:478:20: note: expected 'struct SIM_Type *' but argument is of type 'unsigned int'
+ static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+                    ^
+../Sources/main.c:27:3: warning: passing argument 1 of 'SIM_HAL_EnableClock' makes pointer from integer without a cast [enabled by default]
+   SIM_HAL_EnableClock(SIM_BASE, kSimClockGatePit0); // Enable PIT Clock Gates
+   ^
+In file included from C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_sim_hal.h:135:0,
+                 from ../Sources/main.c:3:
+c:\freescale\ksdk_1.3.0\platform\hal\src\sim\mk64f12\fsl_sim_hal_mk64f12.h:478:20: note: expected 'struct SIM_Type *' but argument is of type 'unsigned int'
+ static inline void SIM_HAL_EnableClock(SIM_Type * base, sim_clock_gate_name_t name)
+                    ^
+../Sources/main.c:29:3: warning: passing argument 1 of 'PORT_HAL_SetMuxMode' makes pointer from integer without a cast [enabled by default]
+   PORT_HAL_SetMuxMode(PORTE_BASE, PORT_PIN, kPortMuxAsGpio);           // Configure PORTE, Pin 26, MUX as a GPIO
+   ^
+In file included from ../Sources/main.c:4:0:
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_port_hal.h:251:20: note: expected 'struct PORT_Type *' but argument is of type 'unsigned int'
+ static inline void PORT_HAL_SetMuxMode(PORT_Type * base,
+                    ^
+../Sources/main.c:31:3: warning: passing argument 1 of 'GPIO_HAL_SetPinDir' makes pointer from integer without a cast [enabled by default]
+   GPIO_HAL_SetPinDir(PTE_BASE, PORT_PIN, kGpioDigitalOutput);          // Configure PORTE, Pin 26, as an Output
+   ^
+In file included from ../Sources/main.c:2:0:
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_gpio_hal.h:83:6: note: expected 'struct GPIO_Type *' but argument is of type 'unsigned int'
+ void GPIO_HAL_SetPinDir(GPIO_Type * base, uint32_t pin,
+      ^
+../Sources/main.c:35:3: warning: passing argument 1 of 'PIT_HAL_SetTimerRunInDebugCmd' makes pointer from integer without a cast [enabled by default]
+   PIT_HAL_SetTimerRunInDebugCmd(PIT_BASE, true);                       // Allow PIT timer to run in Debug Mode
+   ^
+In file included from ../Sources/main.c:5:0:
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_pit_hal.h:107:20: note: expected 'struct PIT_Type *' but argument is of type 'unsigned int'
+ static inline void PIT_HAL_SetTimerRunInDebugCmd(PIT_Type * base, bool timerRun)
+                    ^
+../Sources/main.c:36:3: warning: passing argument 1 of 'PIT_HAL_Enable' makes pointer from integer without a cast [enabled by default]
+   PIT_HAL_Enable(PIT_BASE);                                            // Enables PIT timers
+   ^
+In file included from ../Sources/main.c:5:0:
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_pit_hal.h:76:20: note: expected 'struct PIT_Type *' but argument is of type 'unsigned int'
+ static inline void PIT_HAL_Enable(PIT_Type * base)
+                    ^
+../Sources/main.c:37:3: warning: passing argument 1 of 'PIT_HAL_StopTimer' makes pointer from integer without a cast [enabled by default]
+   PIT_HAL_StopTimer(PIT_BASE, PIT_Module);                             // Disable PIT0 Timer
+   ^
+In file included from ../Sources/main.c:5:0:
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_pit_hal.h:169:20: note: expected 'struct PIT_Type *' but argument is of type 'unsigned int'
+ static inline void PIT_HAL_StopTimer(PIT_Type * base, uint32_t channel)
+                    ^
+../Sources/main.c:38:3: warning: passing argument 1 of 'PIT_HAL_SetTimerPeriodByCount' makes pointer from integer without a cast [enabled by default]
+   PIT_HAL_SetTimerPeriodByCount(PIT_BASE, PIT_Module, PIT_Period);     // PIT0 Timer count value, PIT Period=1ms, busclk=60,000,000Hz, Period=1ms/(1/60000000Hz)=60000
+   ^
+In file included from ../Sources/main.c:5:0:
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_pit_hal.h:210:20: note: expected 'struct PIT_Type *' but argument is of type 'unsigned int'
+ static inline void PIT_HAL_SetTimerPeriodByCount(PIT_Type * base, uint32_t channel, uint32_t count)
+                    ^
+../Sources/main.c:39:3: warning: passing argument 1 of 'PIT_HAL_StartTimer' makes pointer from integer without a cast [enabled by default]
+   PIT_HAL_StartTimer(PIT_BASE, PIT_Module);                            // Start PIT0 Timer
+   ^
+In file included from ../Sources/main.c:5:0:
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_pit_hal.h:154:20: note: expected 'struct PIT_Type *' but argument is of type 'unsigned int'
+ static inline void PIT_HAL_StartTimer(PIT_Type * base, uint32_t channel)
+                    ^
+../Sources/main.c:46:5: warning: passing argument 1 of 'GPIO_HAL_TogglePinOutput' makes pointer from integer without a cast [enabled by default]
+     GPIO_HAL_TogglePinOutput(PTE_BASE, PORT_PIN);                        // Toggle GREEN LED
+     ^
+In file included from ../Sources/main.c:2:0:
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_gpio_hal.h:201:20: note: expected 'struct GPIO_Type *' but argument is of type 'unsigned int'
+ static inline void GPIO_HAL_TogglePinOutput(GPIO_Type * base, uint32_t pin)
+                    ^
+../Sources/main.c: In function 'PIT_Delay':
+../Sources/main.c:54:1: warning: passing argument 1 of 'PIT_HAL_IsIntPending' makes pointer from integer without a cast [enabled by default]
+ {long pit_i; for (pit_i=0;pit_i<pit_delay;pit_i++) {while (!PIT_Overflow); PIT_HAL_ClearIntFlag(PIT_BASE, PIT_Module);}}
+ ^
+In file included from ../Sources/main.c:5:0:
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_pit_hal.h:328:20: note: expected 'struct PIT_Type *' but argument is of type 'unsigned int'
+ static inline bool PIT_HAL_IsIntPending(PIT_Type * base, uint32_t channel)
+                    ^
+../Sources/main.c:54:1: warning: passing argument 1 of 'PIT_HAL_ClearIntFlag' makes pointer from integer without a cast [enabled by default]
+ {long pit_i; for (pit_i=0;pit_i<pit_delay;pit_i++) {while (!PIT_Overflow); PIT_HAL_ClearIntFlag(PIT_BASE, PIT_Module);}}
+ ^
+In file included from ../Sources/main.c:5:0:
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_pit_hal.h:310:20: note: expected 'struct PIT_Type *' but argument is of type 'unsigned int'
+ static inline void PIT_HAL_ClearIntFlag(PIT_Type * base, uint32_t channel)
+                    ^
+Finished building: ../Sources/main.c
+ 
+Building file: ../Project_Settings/Startup_Code/startup.c
+Invoking: Cross ARM C Compiler
+arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"C:\Freescale\KSDK_1.3.0/platform/hal/inc" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"Project_Settings/Startup_Code/startup.d" -MT"Project_Settings/Startup_Code/startup.o" -c -o "Project_Settings/Startup_Code/startup.o" "../Project_Settings/Startup_Code/startup.c"
+Finished building: ../Project_Settings/Startup_Code/startup.c
+ 
+Building file: ../Project_Settings/Startup_Code/startup_MK64F12.S
+Invoking: Cross ARM GNU Assembler
+arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -x assembler-with-cpp -MMD -MP -MF"Project_Settings/Startup_Code/startup_MK64F12.d" -MT"Project_Settings/Startup_Code/startup_MK64F12.o" -c -o "Project_Settings/Startup_Code/startup_MK64F12.o" "../Project_Settings/Startup_Code/startup_MK64F12.S"
+Finished building: ../Project_Settings/Startup_Code/startup_MK64F12.S
+ 
+Building file: ../Project_Settings/Startup_Code/system_MK64F12.c
+Invoking: Cross ARM C Compiler
+arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"C:\Freescale\KSDK_1.3.0/platform/hal/inc" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"Project_Settings/Startup_Code/system_MK64F12.d" -MT"Project_Settings/Startup_Code/system_MK64F12.o" -c -o "Project_Settings/Startup_Code/system_MK64F12.o" "../Project_Settings/Startup_Code/system_MK64F12.c"
+Finished building: ../Project_Settings/Startup_Code/system_MK64F12.c
+ 
+Building target: 4part1.elf
+Invoking: Cross ARM C++ Linker
+arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -T "MK64FN1M0xxx12_flash.ld" -Xlinker --gc-sections -L"C:/Users/pkalgaon/Desktop/Workspace/4part1/Project_Settings/Linker_Files" -Wl,-Map,"4part1.map" -specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs -o "4part1.elf"  ./Sources/main.o  ./Project_Settings/Startup_Code/startup.o ./Project_Settings/Startup_Code/startup_MK64F12.o ./Project_Settings/Startup_Code/system_MK64F12.o  C:/Freescale/KSDK_1.3.0/lib/ksdk_platform_lib/kds/K64F12/debug/libksdk_platform.a 
+Finished building target: 4part1.elf
+ 
+Invoking: Cross ARM GNU Print Size
+arm-none-eabi-size --format=berkeley "4part1.elf"
+   text	   data	    bss	    dec	    hex	filename
+   7100	    112	   2092	   9304	   2458	4part1.elf
+Finished building: 4part1.siz
+ 
+
+15:29:12 Build Finished (took 2s.438ms)
+
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/GPIO.build.log b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/GPIO.build.log
new file mode 100644
index 0000000..3f21ed0
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/GPIO.build.log
@@ -0,0 +1,21 @@
+15:56:16 **** Incremental Build of configuration Debug for project GPIO ****
+make all 
+Building file: ../Sources/main.c
+Invoking: Cross ARM C Compiler
+arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"Sources/main.d" -MT"Sources/main.o" -c -o "Sources/main.o" "../Sources/main.c"
+Finished building: ../Sources/main.c
+ 
+Building target: GPIO.elf
+Invoking: Cross ARM C++ Linker
+arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -T "MK64FN1M0xxx12_flash.ld" -Xlinker --gc-sections -L"C:/Users/pkalgaon/Desktop/Workspace/GPIO/Project_Settings/Linker_Files" -Wl,-Map,"GPIO.map" -specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs -o "GPIO.elf"  ./Sources/main.o  ./Project_Settings/Startup_Code/startup.o ./Project_Settings/Startup_Code/startup_MK64F12.o ./Project_Settings/Startup_Code/system_MK64F12.o   
+Finished building target: GPIO.elf
+ 
+Invoking: Cross ARM GNU Print Size
+arm-none-eabi-size --format=berkeley "GPIO.elf"
+   text	   data	    bss	    dec	    hex	filename
+   2140	    108	   2076	   4324	   10e4	GPIO.elf
+Finished building: GPIO.siz
+ 
+
+15:56:17 Build Finished (took 863ms)
+
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/Interrupt.build.log b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/Interrupt.build.log
new file mode 100644
index 0000000..2462026
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/Interrupt.build.log
@@ -0,0 +1,11 @@
+16:05:12 **** Incremental Build of configuration Debug for project Interrupt ****
+make all 
+Invoking: Cross ARM GNU Print Size
+arm-none-eabi-size --format=berkeley "GPIO.elf"
+   text	   data	    bss	    dec	    hex	filename
+   2084	    108	   2076	   4268	   10ac	GPIO.elf
+Finished building: GPIO.siz
+ 
+
+16:05:12 Build Finished (took 306ms)
+
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/UART.build.log b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/UART.build.log
new file mode 100644
index 0000000..a614e0e
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/UART.build.log
@@ -0,0 +1,11 @@
+16:15:50 **** Incremental Build of configuration Debug for project UART ****
+make all 
+Invoking: Cross ARM GNU Print Size
+arm-none-eabi-size --format=berkeley "GPIO.elf"
+   text	   data	    bss	    dec	    hex	filename
+   2056	    108	   2076	   4240	   1090	GPIO.elf
+Finished building: GPIO.siz
+ 
+
+16:15:51 Build Finished (took 305ms)
+
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml
new file mode 100644
index 0000000..8e47957
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<section name="Workbench">
+	<section name="completion_proposal_size">
+	</section>
+	<section name="org.eclipse.cdt.ui.text.hover.CMacroExpansionExploration">
+	</section>
+</section>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log
new file mode 100644
index 0000000..8737322
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log
@@ -0,0 +1,34 @@
+16:13:03 **** Build of configuration Debug for project UART ****
+make all 
+Building file: ../Sources/main.c
+Invoking: Cross ARM C Compiler
+arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"Sources/main.d" -MT"Sources/main.o" -c -o "Sources/main.o" "../Sources/main.c"
+Finished building: ../Sources/main.c
+ 
+Building target: GPIO.elf
+Invoking: Cross ARM C++ Linker
+arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -T "MK64FN1M0xxx12_flash.ld" -Xlinker --gc-sections -L"C:/Users/pkalgaon/Desktop/Workspace/UART/Project_Settings/Linker_Files" -Wl,-Map,"GPIO.map" -specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs -o "GPIO.elf"  ./Sources/main.o  ./Project_Settings/Startup_Code/startup.o ./Project_Settings/Startup_Code/startup_MK64F12.o ./Project_Settings/Startup_Code/system_MK64F12.o   
+Finished building target: GPIO.elf
+ 
+Invoking: Cross ARM GNU Print Size
+arm-none-eabi-size --format=berkeley "GPIO.elf"
+   text	   data	    bss	    dec	    hex	filename
+   2056	    108	   2076	   4240	   1090	GPIO.elf
+Finished building: GPIO.siz
+ 
+16:13:29 **** Incremental Build of configuration Debug for project UART ****
+make all 
+Invoking: Cross ARM GNU Print Size
+arm-none-eabi-size --format=berkeley "GPIO.elf"
+   text	   data	    bss	    dec	    hex	filename
+   2056	    108	   2076	   4240	   1090	GPIO.elf
+Finished building: GPIO.siz
+ 
+16:15:50 **** Incremental Build of configuration Debug for project UART ****
+make all 
+Invoking: Cross ARM GNU Print Size
+arm-none-eabi-size --format=berkeley "GPIO.elf"
+   text	   data	    bss	    dec	    hex	filename
+   2056	    108	   2076	   4240	   1090	GPIO.elf
+Finished building: GPIO.siz
+ 
diff --git a/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/ksdk_platform_lib_K64F12.build.log b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/ksdk_platform_lib_K64F12.build.log
new file mode 100644
index 0000000..4091e72
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.cdt.ui/ksdk_platform_lib_K64F12.build.log
@@ -0,0 +1,6 @@
+15:28:30 **** Incremental Build of configuration debug for project ksdk_platform_lib_K64F12 ****
+make -k all 
+make: Nothing to be done for 'all'.
+
+15:28:31 Build Finished (took 1s.183ms)
+
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.resources/.history/4b/b0caad0998a5001d10f5c311a15de552 b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.history/4b/b0caad0998a5001d10f5c311a15de552
new file mode 100644
index 0000000..2f74731
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.history/4b/b0caad0998a5001d10f5c311a15de552
@@ -0,0 +1,70 @@
+#include "MK64F12.h"
+
+int main(void)
+{
+
+	SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; /*Enable Port B Clock Gate Control*/
+	SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;/*Enable Port E Clock Gate Control*/
+	SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;/*Enable Port C Clock Gate Control*/
+	SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /*Enable Port A Clock Gate Control*/
+	PORTB_PCR21 = 0x100; /*Blue Led, configured as Alternative 1 (GPIO)*/
+	PORTB_PCR22 = 0x100;/*Red Led, configured as Alternative 1 (GPIO)*/
+	PORTE_PCR26 = 0x100;/*Green Led, configured as Alternative 1 (GPIO)*/
+	PORTC_PCR6 = 0X100;/*Switch 2, configured as Alternative 1 (GPIO)*/
+	PORTA_PCR4 = 0x100;/*Changing the NMI to GPIO*/
+	GPIOB_PDDR |= (1 << 21);/*Setting the bit 21 of the port B as Output*/
+	GPIOB_PDDR |= (1 << 22);/*Setting the bit 22 of the port B as Output*/
+	GPIOE_PDDR |= (1 << 26);/*Setting the bit 26 of the port E as Output*/
+	GPIOC_PDDR |= (0 << 6);/*Setting the bit 6 of the port C as Input*/
+	/*Turn off RGB Leds*/
+	GPIOB_PDOR |= (1 << 22);/*Turn Off Red Led*/
+	GPIOB_PDOR |= (1 << 21);/*Turn Off Blue Led*/
+	GPIOE_PDOR |= (1 << 26);/*Turn Off Green Led*/
+
+	unsigned long Counter = 0x100000;/*Delay Value*/
+
+	for(;;)
+	{
+		if(GPIOC_PDIR == 0)/*If the Switch 2 was press*/
+		{
+			GPIOB_PDOR = (1 << 21);/*Turn On Red Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOB_PDOR = (1 << 22) | ( 1 << 21); /*Turn Off Red Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOE_PDOR = (0 << 26);/*Turn On Green Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOE_PDOR = (1 << 26); /*Turn Off Green Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOB_PDOR = (1 << 22);/*Turn On Blue Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOB_PDOR = (1 << 21) | (1 << 22); /*Turn Off Blue Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+		}
+	}
+	return 0;
+}
+
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.resources/.history/5a/a060688897a5001d10f5c311a15de552 b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.history/5a/a060688897a5001d10f5c311a15de552
new file mode 100644
index 0000000..ad57627
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.history/5a/a060688897a5001d10f5c311a15de552
@@ -0,0 +1,45 @@
+#include "MK64F12.h"
+void DelayFunction(void);
+intmain(void)
+{
+SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; /*Enable Port B Clock Gate Control*/
+SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;/*Enable Port C Clock Gate Control*/
+SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /*Enable Port A Clock Gate Control*/
+PORTB_PCR21 = 0x100; /*Blue Led, configured as Alternative 1 (GPIO)*/
+PORTB_PCR22 = 0x100;/*Red Led, configured as Alternative 1 (GPIO)*/
+PORTC_PCR6 = 0x90100; /*PORTC_PCR6: ISF=0,IRQC=9,MUX=1 */
+PORTA_PCR4 = 0x100;/*Changing the NMI to GPIO*/
+GPIOB_PDDR |= (1 << 21);/*Setting the bit 21 of the port B as Output*/
+GPIOB_PDDR |= (1 << 22);/*Setting the bit 22 of the port B as Output*/
+GPIOC_PDDR |= (0 << 6);/*Setting the bit 6 of the port C as Input*/
+/*Turn off Red and Blue Leds*/
+GPIOB_PDOR |= (1 << 22);
+GPIOB_PDOR |= (1 << 21);
+/*Turn Off Red Led*/ /*Turn Off Blue Led*/
+PORTC_ISFR = PORT_ISFR_ISF(0x40); /* Clear interrupt status flag */
+NVIC_EnableIRQ(PORTC_IRQn);/*Enable the PORTC interrupt*/
+for (;;)
+{
+GPIOB_PTOR |= (1 << 22); /*Red LED blinking*/
+DelayFunction();
+}
+return 0;
+}
+void PORTC_IRQHandler(void)
+{
+DelayFunction();
+GPIOB_PSOR |= (1 << 22);/*Turn Off Red Led*/
+GPIOB_PCOR |= (1 << 21);/*Turn On Blue Led*/
+DelayFunction();
+GPIOB_PSOR |= (1 << 21);/*Turn Off Blue Led*/
+DelayFunction();
+PORTC_ISFR = PORT_ISFR_ISF(0x40);
+}
+/* Clear interrupt status flag */
+void DelayFunction(void)
+{
+int cnt;
+for(cnt=0; cnt<1000000; cnt++)
+{
+}
+}
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.resources/.history/8e/f0f389e099a5001d10f5c311a15de552 b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.history/8e/f0f389e099a5001d10f5c311a15de552
new file mode 100644
index 0000000..2f74731
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.history/8e/f0f389e099a5001d10f5c311a15de552
@@ -0,0 +1,70 @@
+#include "MK64F12.h"
+
+int main(void)
+{
+
+	SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; /*Enable Port B Clock Gate Control*/
+	SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;/*Enable Port E Clock Gate Control*/
+	SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;/*Enable Port C Clock Gate Control*/
+	SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /*Enable Port A Clock Gate Control*/
+	PORTB_PCR21 = 0x100; /*Blue Led, configured as Alternative 1 (GPIO)*/
+	PORTB_PCR22 = 0x100;/*Red Led, configured as Alternative 1 (GPIO)*/
+	PORTE_PCR26 = 0x100;/*Green Led, configured as Alternative 1 (GPIO)*/
+	PORTC_PCR6 = 0X100;/*Switch 2, configured as Alternative 1 (GPIO)*/
+	PORTA_PCR4 = 0x100;/*Changing the NMI to GPIO*/
+	GPIOB_PDDR |= (1 << 21);/*Setting the bit 21 of the port B as Output*/
+	GPIOB_PDDR |= (1 << 22);/*Setting the bit 22 of the port B as Output*/
+	GPIOE_PDDR |= (1 << 26);/*Setting the bit 26 of the port E as Output*/
+	GPIOC_PDDR |= (0 << 6);/*Setting the bit 6 of the port C as Input*/
+	/*Turn off RGB Leds*/
+	GPIOB_PDOR |= (1 << 22);/*Turn Off Red Led*/
+	GPIOB_PDOR |= (1 << 21);/*Turn Off Blue Led*/
+	GPIOE_PDOR |= (1 << 26);/*Turn Off Green Led*/
+
+	unsigned long Counter = 0x100000;/*Delay Value*/
+
+	for(;;)
+	{
+		if(GPIOC_PDIR == 0)/*If the Switch 2 was press*/
+		{
+			GPIOB_PDOR = (1 << 21);/*Turn On Red Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOB_PDOR = (1 << 22) | ( 1 << 21); /*Turn Off Red Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOE_PDOR = (0 << 26);/*Turn On Green Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOE_PDOR = (1 << 26); /*Turn Off Green Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOB_PDOR = (1 << 22);/*Turn On Blue Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOB_PDOR = (1 << 21) | (1 << 22); /*Turn Off Blue Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+		}
+	}
+	return 0;
+}
+
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.resources/.history/ff/f066f68097a5001d10f5c311a15de552 b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.history/ff/f066f68097a5001d10f5c311a15de552
new file mode 100644
index 0000000..35d1e64
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.history/ff/f066f68097a5001d10f5c311a15de552
@@ -0,0 +1,45 @@
+#include "MK64F12.h"
+void DelayFunction(void);
+intmain(void)
+{
+SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; /*Enable Port B Clock Gate Control*/
+SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;/*Enable Port C Clock Gate Control*/
+SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /*Enable Port A Clock Gate Control*/
+PORTB_PCR21 = 0x100; /*Blue Led, configured as Alternative 1 (GPIO)*/
+PORTB_PCR22 = 0x100;/*Red Led, configured as Alternative 1 (GPIO)*/
+PORTC_PCR6 = 0x90100; /*PORTC_PCR6: ISF=0,IRQC=9,MUX=1 */
+PORTA_PCR4 = 0x100;/*Changing the NMI to GPIO*/
+GPIOB_PDDR |= (1 << 21);/*Setting the bit 21 of the port B as Output*/
+GPIOB_PDDR |= (1 << 22);/*Setting the bit 22 of the port B as Output*/
+GPIOC_PDDR |= (0 << 6);/*Setting the bit 6 of the port C as Input*/
+/*Turn off Red and Blue Leds*/
+GPIOB_PDOR |= (1 << 22);
+GPIOB_PDOR |= (1 << 21);
+/*Turn Off Red Led*/ /*Turn Off Blue Led*/
+PORTC_ISFR = PORT_ISFR_ISF(0x40); /* Clear interrupt status flag */
+NVIC_EnableIRQ(PORTC_IRQn);/*Enable the PORTC interrupt*/
+for (;;)
+{
+GPIOB_PTOR |= (1 << 22); /*Red LED blinking*/
+DelayFunction();
+}
+return 0;
+}
+void PORTC_IRQHandler(void)
+{
+DelayFunction();
+GPIOB_PSOR |= (1 << 22);/*Turn Off Red Led*/
+GPIOB_PCOR |= (1 << 21);/*Turn On Blue Led*/
+DelayFunction();
+GPIOB_PSOR |= (1 << 21);/*Turn Off Blue Led*/
+DelayFunction();
+PORTC_ISFR = PORT_ISFR_ISF(0x40);
+}
+/* Clear interrupt status flag */
+void DelayFunction(void)
+{
+intcnt;
+for(cnt=0; cnt<1000000; cnt++)
+{
+}
+}
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.resources/.projects/4part1/.indexes/68/properties.index b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.projects/4part1/.indexes/68/properties.index
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new file mode 100644
index 0000000..fa01e07
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diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.resources/.projects/ksdk_platform_lib_K64F12/1.tree b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.projects/ksdk_platform_lib_K64F12/1.tree
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diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version
new file mode 100644
index 0000000..25cb955
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version
@@ -0,0 +1 @@
+
\ No newline at end of file
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index
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diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version
new file mode 100644
index 0000000..6b2aaa7
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version
@@ -0,0 +1 @@
+

\ No newline at end of file
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.resources/.root/1.tree b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.root/1.tree
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diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources b/Workspace/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources
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diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.freescale.processorexpert.core.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.freescale.processorexpert.core.prefs
new file mode 100644
index 0000000..f38ed7f
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.freescale.processorexpert.core.prefs
@@ -0,0 +1,5 @@
+UserPEpath=C\:\\ProgramData\\Processor Expert\\PEXDRV_PE5_3
+UserPEpath_Default=C\:\\ProgramData\\Processor Expert\\CWMCU_PE5_00
+eclipse.preferences.version=1
+localPEpath=C\:\\Freescale\\KDS_v3\\eclipse\\ProcessorExpert
+localPEpath_Default=C\:\\Freescale\\KDS_v3\\eclipse\\ProcessorExpert
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 0000000..77ca49a
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+macros/workspace=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<macros/>\r\n
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-4part1.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-4part1.prefs
new file mode 100644
index 0000000..9c00dc4
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-4part1.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+indexer/preferenceScope=0
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-GPIO.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-GPIO.prefs
new file mode 100644
index 0000000..9c00dc4
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-GPIO.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+indexer/preferenceScope=0
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-Interrupt.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-Interrupt.prefs
new file mode 100644
index 0000000..9c00dc4
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-Interrupt.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+indexer/preferenceScope=0
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-UART.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-UART.prefs
new file mode 100644
index 0000000..9c00dc4
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-UART.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+indexer/preferenceScope=0
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-ksdk_platform_lib_K64F12.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-ksdk_platform_lib_K64F12.prefs
new file mode 100644
index 0000000..9c00dc4
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-ksdk_platform_lib_K64F12.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+indexer/preferenceScope=0
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs
new file mode 100644
index 0000000..aa2411d
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.cDebug.default_source_containers=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<sourceLookupDirector>\r\n<sourceContainers duplicates\="false">\r\n<container memento\="AbsolutePath" typeId\="org.eclipse.cdt.debug.core.containerType.absolutePath"/>\r\n<container memento\="programRelativePath" typeId\="org.eclipse.cdt.debug.core.containerType.programRelativePath"/>\r\n<container memento\="&lt;?xml version\=&quot;1.0&quot; encoding\=&quot;UTF-8&quot; standalone\=&quot;no&quot;?&gt;&\#13;&\#10;&lt;project referencedProjects\=&quot;true&quot;/&gt;&\#13;&\#10;" typeId\="org.eclipse.cdt.debug.core.containerType.project"/>\r\n</sourceContainers>\r\n</sourceLookupDirector>\r\n
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.dsf.ui.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.dsf.ui.prefs
new file mode 100644
index 0000000..2c7c1b9
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.dsf.ui.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+useAnnotationsPrefPage=true
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 0000000..52f81d2
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,4 @@
+eclipse.preferences.version=1
+properties/4part1.ilg.gnuarmeclipse.managedbuild.cross.target.elf.1945281639/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1802811856=ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.1014728790\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.1696087855\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1097552796\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.1079464894\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.assembler.951867785\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.656910265\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1886357308\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.698695929\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.189597559\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1802811856\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1244079227\=rebuildState\\\=false\\r\\n\r\n
+properties/GPIO.ilg.gnuarmeclipse.managedbuild.cross.target.elf.1672910064/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934=ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.462759647\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1276352763\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1648336251\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.536657092\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.createflash.830299569\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.138424891\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1102412416\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.printsize.805423770\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.assembler.2120002892\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.282145612\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\n
+properties/libtemplatestatic.ilg.gnuarmeclipse.managedbuild.cross.target.lib.297819605/ilg.gnuarmeclipse.managedbuild.cross.config.lib.debug.660039418=ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.1510905647\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.archiver.663925858\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.config.lib.debug.660039418\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.955395052\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.createflash.856579085\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.1671453659\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.assembler.707313748\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.513430167\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1836014414\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.toolchain.lib.debug.1112966798\=rebuildState\\\=false\\r\\n\r\nilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.516400165\=rebuildState\\\=false\\r\\n\r\n
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.mylyn.ui.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.mylyn.ui.prefs
new file mode 100644
index 0000000..0451f54
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.mylyn.ui.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.mylyn.cdt.ui.run.count.3_3_0=1
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs
new file mode 100644
index 0000000..cbfe61a
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs
@@ -0,0 +1,5 @@
+content_assist_disabled_computers=org.eclipse.cdt.ui.parserProposalCategory\u0000org.eclipse.cdt.ui.textProposalCategory\u0000
+eclipse.preferences.version=1
+spelling_locale_initialized=true
+useAnnotationsPrefPage=true
+useQuickDiffPrefPage=true
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 0000000..dffc6b5
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+version=1
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.variables.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.variables.prefs
new file mode 100644
index 0000000..44b54e0
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.variables.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.core.variables.valueVariables=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<valueVariables>\r\n<valueVariable description\="Path to J-Link installation folder" name\="jlink_path" readOnly\="false" value\="${eclipse_home}../segger"/>\r\n<valueVariable name\="cross_prefix" readOnly\="false" value\="arm-none-eabi-"/>\r\n<valueVariable description\="Name of the OpenOCD executable" name\="openocd_executable" readOnly\="false" value\="openocd"/>\r\n<valueVariable description\="Name of the J-Link GDB server executable" name\="jlink_gdbserver" readOnly\="false" value\="JLinkGDBServerCL"/>\r\n<valueVariable description\="Path to OpenOCD installation folder" name\="openocd_path" readOnly\="false" value\="${eclipse_home}../openocd/bin"/>\r\n<valueVariable name\="cross_suffix" readOnly\="false"/>\r\n</valueVariables>\r\n
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs
new file mode 100644
index 0000000..c8e90d4
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs
@@ -0,0 +1,6 @@
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.debug.gdbjtag.launchConfigurationType=org.eclipse.cdt.debug.gdbjtag.core.dsfLaunchDelegate,debug,;
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.applicationLaunchType=org.eclipse.cdt.dsf.gdb.launch.localCLaunch,debug,;org.eclipse.cdt.cdi.launch.localCLaunch,run,;
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.attachLaunchType=org.eclipse.cdt.dsf.gdb.launch.attachCLaunch,debug,;
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.postmortemLaunchType=org.eclipse.cdt.dsf.gdb.launch.coreCLaunch,debug,;
+//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.remoteApplicationLaunchType=org.eclipse.rse.remotecdt.dsf.debug,debug,;
+eclipse.preferences.version=1
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs
new file mode 100644
index 0000000..b6507df
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs
@@ -0,0 +1,5 @@
+eclipse.preferences.version=1
+org.eclipse.debug.ui.MemoryView.orientation=0
+org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<launchPerspectives/>\r\n
+preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane|
+preferredTargets=org.eclipse.cdt.debug.ui.toggleCBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCDynamicPrintfTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget|
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.context.core.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.context.core.prefs
new file mode 100644
index 0000000..43e97e4
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.context.core.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+mylyn.attention.migrated=true
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.monitor.ui.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.monitor.ui.prefs
new file mode 100644
index 0000000..8d462a6
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.monitor.ui.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.mylyn.monitor.activity.tracking.enabled.checked=true
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.tasks.ui.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.tasks.ui.prefs
new file mode 100644
index 0000000..5330e43
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.tasks.ui.prefs
@@ -0,0 +1,4 @@
+eclipse.preferences.version=1
+migrated.task.repositories.secure.store=true
+org.eclipse.mylyn.tasks.ui.filters.nonmatching=true
+org.eclipse.mylyn.tasks.ui.filters.nonmatching.encouraged=true
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.core.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.core.prefs
new file mode 100644
index 0000000..c1f4ecf
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.core.prefs
@@ -0,0 +1,3 @@
+activeuserprofiles=IN-ENGR-IOTLAB3;Team
+eclipse.preferences.version=1
+org.eclipse.rse.systemtype.local.systemType.defaultUserId=pkalgaon
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.ui.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.ui.prefs
new file mode 100644
index 0000000..131b751
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.ui.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.rse.preferences.order.connections=IN-ENGR-IOTLAB3.Local
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.cvs.ui.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.cvs.ui.prefs
new file mode 100644
index 0000000..f9e585b
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.cvs.ui.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+pref_first_startup=false
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs
new file mode 100644
index 0000000..56cd496
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.team.ui.first_time=false
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs
new file mode 100644
index 0000000..61f3bb8
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+overviewRuler_migration=migrated_3.1
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs
new file mode 100644
index 0000000..5458974
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs
@@ -0,0 +1,5 @@
+PROBLEMS_FILTERS_MIGRATE=true
+eclipse.preferences.version=1
+platformState=1675537032353
+quickStart=false
+tipsAndTricks=true
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs
new file mode 100644
index 0000000..08076f2
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+showIntro=false
diff --git a/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs
new file mode 100644
index 0000000..8aa86ed
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs
@@ -0,0 +1,3 @@
+ENABLED_DECORATORS=com.freescale.processorexpert.cde.ui.editors.componenteditor.providers.CDEErrorDecorator\:true,com.processorexpert.ui.decorators.EnableDecorator\:true,com.processorexpert.ui.selector.ComponentDecorator\:true,org.eclipse.cdt.ui.indexedFiles\:false,org.eclipse.cdt.managedbuilder.ui.excludedFile\:true,org.eclipse.cdt.managedbuilder.ui.includeFolder\:true,org.eclipse.cdt.internal.ui.CustomBuildSettingsDecorator\:true,org.eclipse.egit.ui.internal.decorators.GitLightweightDecorator\:true,org.eclipse.linuxtools.tmf.ui.trace_folder.decorator\:true,org.eclipse.linuxtools.tmf.ui.experiment_folder.decorator\:true,org.eclipse.linuxtools.tmf.ui.linked_trace.decorator\:true,org.eclipse.mylyn.context.ui.decorator.interest\:true,org.eclipse.mylyn.tasks.ui.decorators.task\:true,org.eclipse.mylyn.team.ui.changeset.decorator\:true,org.eclipse.rse.core.virtualobject.decorator\:true,org.eclipse.rse.core.binary.executable.decorator\:true,org.eclipse.rse.core.script.executable.decorator\:true,org.eclipse.rse.core.java.executable.decorator\:true,org.eclipse.rse.core.library.decorator\:true,org.eclipse.rse.core.link.decorator\:true,org.eclipse.rse.subsystems.error.decorator\:true,org.eclipse.team.cvs.ui.decorator\:true,org.eclipse.ui.LinkedResourceDecorator\:true,org.eclipse.ui.SymlinkDecorator\:true,org.eclipse.ui.VirtualResourceDecorator\:true,org.eclipse.ui.ContentTypeDecorator\:true,org.eclipse.ui.ResourceFilterDecorator\:false,
+UIActivities.org.eclipse.cdt.debug.dsfgdbActivity=true
+eclipse.preferences.version=1
diff --git a/Workspace/.metadata/.plugins/org.eclipse.debug.core/.launches/GPIO Debug.launch b/Workspace/.metadata/.plugins/org.eclipse.debug.core/.launches/GPIO Debug.launch
new file mode 100644
index 0000000..70deb58
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.debug.core/.launches/GPIO Debug.launch	
@@ -0,0 +1,193 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.pemicro.debug.gdbjtag.pne.launchConfigurationType">
+<listAttribute key="com.pemicro.debug.gdbjtag.pne.ELVES"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.NUMBER_ELVES" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.DEVICE_NAME" value="NXP_K6x_K64FN1M0M12"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_OPTIONS" value=""/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDWARE_INTERFACE" value="6"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.LAST_ATTRIBUTE_HEADER" value="com.pemicro.debug.gdbjtag.pne.sda."/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.USE_EXTERNAL_SERVER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.algorithmIndex" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.alternativeAlgorithmPath" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.attachToRunning" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.customTrimFrequency" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.PROVIDE_POWER" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.PROVIDE_POWER" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT_STRING" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.PROVIDE_POWER" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.STARTUP_USE_SWD" value="true"/>
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diff --git a/Workspace/.metadata/.plugins/org.eclipse.debug.core/.launches/Interrupt Debug.launch b/Workspace/.metadata/.plugins/org.eclipse.debug.core/.launches/Interrupt Debug.launch
new file mode 100644
index 0000000..5467cfe
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.debug.core/.launches/Interrupt Debug.launch	
@@ -0,0 +1,193 @@
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diff --git a/Workspace/.metadata/.plugins/org.eclipse.debug.core/.launches/UART Debug.launch b/Workspace/.metadata/.plugins/org.eclipse.debug.core/.launches/UART Debug.launch
new file mode 100644
index 0000000..202e59f
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.debug.core/.launches/UART Debug.launch	
@@ -0,0 +1,193 @@
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diff --git a/Workspace/.metadata/.plugins/org.eclipse.debug.core/.launches/ksdk_platform_lib_K64F12 debug.launch b/Workspace/.metadata/.plugins/org.eclipse.debug.core/.launches/ksdk_platform_lib_K64F12 debug.launch
new file mode 100644
index 0000000..45d93d7
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.debug.core/.launches/ksdk_platform_lib_K64F12 debug.launch	
@@ -0,0 +1,189 @@
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+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_UP_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.PROVIDE_POWER" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.STARTUP_USE_SWD" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useAlternativeAlgorithm" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useCustomTrim" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useDaisyChain" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM PEMicro Interface"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${eclipse_home}/../toolchain/bin/arm-none-eabi-gdb"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="ksdk_platform_lib_K64F12"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/ksdk_platform_lib_K64F12"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+</launchConfiguration>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml b/Workspace/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml
new file mode 100644
index 0000000..2f5d22c
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<section name="Workbench">
+	<section name="org.eclipse.debug.ui.STRING_VARIABLE_SELECTION_DIALOG_SECTION">
+		<item value="398" key="DIALOG_WIDTH"/>
+		<item value="-37" key="DIALOG_Y_ORIGIN"/>
+		<item value="602" key="DIALOG_HEIGHT"/>
+		<item value="271" key="DIALOG_X_ORIGIN"/>
+		<item value="1|Segoe UI|9.0|0|WINDOWS|1|-12|0|0|0|400|0|0|0|1|0|0|0|0|Segoe UI" key="DIALOG_FONT_NAME"/>
+	</section>
+	<section name="org.eclipse.debug.ui.LAUNCH_CONFIGURATIONS_DIALOG_SECTION">
+		<item value="941" key="DIALOG_WIDTH"/>
+		<item value=", com.pemicro.debug.gdbjtag.pne.launchConfigurationType, " key="org.eclipse.debug.ui.EXPANDED_NODES"/>
+		<item value="702" key="DIALOG_HEIGHT"/>
+		<item value="237" key="org.eclipse.debug.ui.DIALOG_SASH_WEIGHTS_1"/>
+		<item value="1|Segoe UI|9.0|0|WINDOWS|1|-12|0|0|0|400|0|0|0|1|0|0|0|0|Segoe UI" key="DIALOG_FONT_NAME"/>
+		<item value="762" key="org.eclipse.debug.ui.DIALOG_SASH_WEIGHTS_2"/>
+	</section>
+</section>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/Workspace/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml
new file mode 100644
index 0000000..14c20f8
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchHistory>
+<launchGroup id="org.eclipse.ui.externaltools.launchGroup">
+<mruHistory/>
+<favorites/>
+</launchGroup>
+<launchGroup id="com.somn.flash.launchGroup.flash">
+<mruHistory/>
+<favorites/>
+</launchGroup>
+<launchGroup id="org.eclipse.debug.ui.launchGroup.profilee">
+<mruHistory/>
+<favorites/>
+</launchGroup>
+<launchGroup id="org.eclipse.debug.ui.launchGroup.profile">
+<mruHistory/>
+<favorites/>
+</launchGroup>
+<launchGroup id="org.eclipse.debug.ui.launchGroup.debug">
+<mruHistory/>
+<favorites/>
+</launchGroup>
+<launchGroup id="org.eclipse.debug.ui.launchGroup.run">
+<mruHistory/>
+<favorites/>
+</launchGroup>
+</launchHistory>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi b/Workspace/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi
new file mode 100644
index 0000000..154c1da
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi
@@ -0,0 +1,2379 @@
+<?xml version="1.0" encoding="ASCII"?>
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+  <persistedState key="memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?>&#xD;&#xA;&lt;workbench>&#xD;&#xA;&lt;mruList>&#xD;&#xA;&lt;file factoryID=&quot;org.eclipse.ui.part.FileEditorInputFactory&quot; id=&quot;org.eclipse.cdt.ui.editor.CEditor&quot; name=&quot;main.c&quot; tooltip=&quot;UART/Sources/main.c&quot;>&#xD;&#xA;&lt;persistable path=&quot;/UART/Sources/main.c&quot;/>&#xD;&#xA;&lt;/file>&#xD;&#xA;&lt;file factoryID=&quot;org.eclipse.ui.part.FileEditorInputFactory&quot; id=&quot;org.eclipse.cdt.ui.editor.CEditor&quot; name=&quot;main.c&quot; tooltip=&quot;Interrupt/Sources/main.c&quot;>&#xD;&#xA;&lt;persistable path=&quot;/Interrupt/Sources/main.c&quot;/>&#xD;&#xA;&lt;/file>&#xD;&#xA;&lt;file factoryID=&quot;org.eclipse.ui.part.FileEditorInputFactory&quot; id=&quot;org.eclipse.ui.DefaultTextEditor&quot; name=&quot;GPIO_Debug_OpenOCD.launch&quot; tooltip=&quot;Interrupt/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch&quot;>&#xD;&#xA;&lt;persistable path=&quot;/Interrupt/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch&quot;/>&#xD;&#xA;&lt;/file>&#xD;&#xA;&lt;file factoryID=&quot;org.eclipse.ui.part.FileEditorInputFactory&quot; id=&quot;org.eclipse.cdt.ui.editor.CEditor&quot; name=&quot;main.c&quot; tooltip=&quot;GPIO/Sources/main.c&quot;>&#xD;&#xA;&lt;persistable path=&quot;/GPIO/Sources/main.c&quot;/>&#xD;&#xA;&lt;/file>&#xD;&#xA;&lt;file factoryID=&quot;org.eclipse.ui.part.FileEditorInputFactory&quot; id=&quot;org.eclipse.cdt.ui.editor.CEditor&quot; name=&quot;main.c&quot; tooltip=&quot;4part1/Sources/main.c&quot;>&#xD;&#xA;&lt;persistable path=&quot;/4part1/Sources/main.c&quot;/>&#xD;&#xA;&lt;/file>&#xD;&#xA;&lt;/mruList>&#xD;&#xA;&lt;/workbench>"/>
+  <tags>activeSchemeId:org.eclipse.ui.defaultAcceleratorConfiguration</tags>
+  <tags>ModelMigrationProcessor.001</tags>
+  <children xsi:type="basic:TrimmedWindow" xmi:id="_drUdcqWTEe2ZZ82yKaHfjQ" elementId="IDEWindow" contributorURI="platform:/plugin/org.eclipse.ui.workbench" selectedElement="_d44YUqWTEe2ZZ82yKaHfjQ" label="%trimmedwindow.label.eclipseSDK" x="130" y="130" width="1024" height="768">
+    <persistedState key="coolBarVisible" value="true"/>
+    <persistedState key="perspectiveBarVisible" value="true"/>
+    <tags>topLevel</tags>
+    <tags>shellMaximized</tags>
+    <children xsi:type="basic:PartSashContainer" xmi:id="_d44YUqWTEe2ZZ82yKaHfjQ" selectedElement="_d44_YKWTEe2ZZ82yKaHfjQ" horizontal="true">
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+          <tags>persp.actionSet:org.eclipse.mylyn.doc.actionSet</tags>
+          <tags>persp.actionSet:org.eclipse.mylyn.tasks.ui.navigation</tags>
+          <tags>persp.actionSet:org.eclipse.ui.cheatsheets.actionSet</tags>
+          <tags>persp.actionSet:org.eclipse.rse.core.search.searchActionSet</tags>
+          <tags>persp.actionSet:org.eclipse.search.searchActionSet</tags>
+          <tags>persp.actionSet:org.eclipse.ui.edit.text.actionSet.annotationNavigation</tags>
+          <tags>persp.actionSet:org.eclipse.ui.edit.text.actionSet.navigation</tags>
+          <tags>persp.actionSet:org.eclipse.ui.edit.text.actionSet.convertLineDelimitersTo</tags>
+          <tags>persp.actionSet:org.eclipse.ui.externaltools.ExternalToolsSet</tags>
+          <tags>persp.actionSet:org.eclipse.ui.actionSet.keyBindings</tags>
+          <tags>persp.actionSet:org.eclipse.ui.actionSet.openFiles</tags>
+          <tags>persp.actionSet:org.eclipse.cdt.ui.SearchActionSet</tags>
+          <tags>persp.actionSet:org.eclipse.cdt.ui.CElementCreationActionSet</tags>
+          <tags>persp.actionSet:org.eclipse.ui.NavigateActionSet</tags>
+          <tags>persp.viewSC:org.eclipse.ui.console.ConsoleView</tags>
+          <tags>persp.viewSC:org.eclipse.search.ui.views.SearchView</tags>
+          <tags>persp.viewSC:org.eclipse.ui.views.ContentOutline</tags>
+          <tags>persp.viewSC:org.eclipse.ui.views.ProblemView</tags>
+          <tags>persp.viewSC:org.eclipse.cdt.ui.CView</tags>
+          <tags>persp.viewSC:org.eclipse.ui.views.ResourceNavigator</tags>
+          <tags>persp.viewSC:org.eclipse.ui.views.PropertySheet</tags>
+          <tags>persp.viewSC:org.eclipse.ui.views.TaskList</tags>
+          <tags>persp.newWizSC:com.nxp.npw4sdk2.NewSDK2xProjectWizard</tags>
+          <tags>persp.newWizSC:org.eclipse.cdt.autotools.ui.wizards.conversionWizard</tags>
+          <tags>persp.newWizSC:org.eclipse.cdt.ui.wizards.ConvertToMakeWizard</tags>
+          <tags>persp.newWizSC:org.eclipse.cdt.ui.wizards.NewMakeFromExisting</tags>
+          <tags>persp.newWizSC:org.eclipse.cdt.ui.wizards.NewCWizard1</tags>
+          <tags>persp.newWizSC:org.eclipse.cdt.ui.wizards.NewCWizard2</tags>
+          <tags>persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFolderCreationWizard</tags>
+          <tags>persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFolderCreationWizard</tags>
+          <tags>persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFileCreationWizard</tags>
+          <tags>persp.newWizSC:org.eclipse.cdt.ui.wizards.NewHeaderFileCreationWizard</tags>
+          <tags>persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFileCreationWizard</tags>
+          <tags>persp.newWizSC:org.eclipse.cdt.ui.wizards.NewClassCreationWizard</tags>
+          <tags>persp.perspSC:com.processorexpert.ui.perspective.perspectives.DeviceInit</tags>
+          <tags>persp.viewSC:com.processorexpert.ui.projectview.ProjectView</tags>
+          <tags>persp.showIn:org.eclipse.cdt.codan.internal.ui.views.ProblemDetails</tags>
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+          <tags>persp.actionSet:org.eclipse.debug.ui.breakpointActionSet</tags>
+          <tags>persp.viewSC:org.eclipse.cdt.make.ui.views.MakeView</tags>
+          <tags>persp.actionSet:org.eclipse.cdt.make.ui.makeTargetActionSet</tags>
+          <tags>persp.perspSC:org.eclipse.debug.ui.DebugPerspective</tags>
+          <tags>persp.perspSC:org.eclipse.team.ui.TeamSynchronizingPerspective</tags>
+          <tags>persp.actionSet:org.eclipse.debug.ui.launchActionSet</tags>
+          <tags>persp.actionSet:org.eclipse.cdt.ui.buildConfigActionSet</tags>
+          <tags>persp.actionSet:org.eclipse.cdt.ui.NavigationActionSet</tags>
+          <tags>persp.actionSet:org.eclipse.cdt.ui.OpenActionSet</tags>
+          <tags>persp.actionSet:org.eclipse.cdt.ui.CodingActionSet</tags>
+          <tags>persp.actionSet:org.eclipse.ui.edit.text.actionSet.presentation</tags>
+          <tags>persp.showIn:org.eclipse.cdt.ui.includeBrowser</tags>
+          <tags>persp.showIn:org.eclipse.cdt.ui.CView</tags>
+          <tags>persp.showIn:org.eclipse.ui.navigator.ProjectExplorer</tags>
+          <tags>persp.viewSC:org.eclipse.ui.navigator.ProjectExplorer</tags>
+          <tags>persp.viewSC:org.eclipse.cdt.ui.includeBrowser</tags>
+          <tags>persp.actionSet:org.eclipse.debug.ui.profileActionSet</tags>
+          <tags>persp.viewSC:org.eclipse.mylyn.tasks.ui.views.tasks</tags>
+          <tags>persp.newWizSC:org.eclipse.mylyn.tasks.ui.wizards.new.repository.task</tags>
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+                <tags>newtablook</tags>
+                <tags>active</tags>
+                <children xsi:type="advanced:Placeholder" xmi:id="_eGk2FKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigator.ProjectExplorer" ref="_eGevcKWTEe2ZZ82yKaHfjQ"/>
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+                <children xsi:type="advanced:Placeholder" xmi:id="_eGk2GaWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.projectview.ProjectView" toBeRendered="false" ref="_eGjA4qWTEe2ZZ82yKaHfjQ"/>
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+    <tags>categoryTag:General</tags>
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+  <descriptors xmi:id="_duY_kKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.views.ContentOutline" label="Outline" iconURI="platform:/plugin/org.eclipse.ui.views/icons/full/eview16/outline_co.png" category="org.eclipse.e4.secondaryNavigationStack" closeable="true" contributionURI="bundleclass://org.eclipse.ui.workbench/org.eclipse.ui.internal.e4.compatibility.CompatibilityView">
+    <tags>View</tags>
+    <tags>categoryTag:General</tags>
+  </descriptors>
+  <descriptors xmi:id="_duZmoKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.pde.runtime.LogView" label="Error Log" iconURI="platform:/plugin/org.eclipse.ui.views.log/icons/eview16/error_log.gif" category="org.eclipse.e4.secondaryDataStack" closeable="true" contributionURI="bundleclass://org.eclipse.ui.workbench/org.eclipse.ui.internal.e4.compatibility.CompatibilityView">
+    <tags>View</tags>
+    <tags>categoryTag:General</tags>
+  </descriptors>
+  <trimContributions xmi:id="_2r10UF9tEeO-yojH_y4TJA" elementId="org.eclipse.ui.ide.application.trimcontribution.QuickAccess" contributorURI="platform:/plugin/org.eclipse.ui.ide.application" toBeRendered="false" parentId="org.eclipse.ui.main.toolbar" positionInParent="last">
+    <children xsi:type="menu:ToolControl" xmi:id="_76uUAF9tEeO-yojH_y4TJA" elementId="Spacer Glue" contributorURI="platform:/plugin/org.eclipse.ui.ide.application" contributionURI="bundleclass://org.eclipse.e4.ui.workbench.renderers.swt/org.eclipse.e4.ui.workbench.renderers.swt.LayoutModifierToolControl">
+      <tags>glue</tags>
+      <tags>move_after:PerspectiveSpacer</tags>
+      <tags>SHOW_RESTORE_MENU</tags>
+    </children>
+    <children xsi:type="menu:ToolControl" xmi:id="_8tJPcF9tEeO-yojH_y4TJA" elementId="SearchField" contributorURI="platform:/plugin/org.eclipse.ui.ide.application" contributionURI="bundleclass://org.eclipse.ui.workbench/org.eclipse.ui.internal.quickaccess.SearchField">
+      <tags>move_after:Spacer Glue</tags>
+      <tags>HIDEABLE</tags>
+      <tags>SHOW_RESTORE_MENU</tags>
+    </children>
+    <children xsi:type="menu:ToolControl" xmi:id="_9LgmcF9tEeO-yojH_y4TJA" elementId="Search-PS Glue" contributorURI="platform:/plugin/org.eclipse.ui.ide.application" contributionURI="bundleclass://org.eclipse.e4.ui.workbench.renderers.swt/org.eclipse.e4.ui.workbench.renderers.swt.LayoutModifierToolControl">
+      <tags>glue</tags>
+      <tags>move_after:SearchField</tags>
+      <tags>SHOW_RESTORE_MENU</tags>
+    </children>
+  </trimContributions>
+  <commands xmi:id="_drp0oKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.command.synchronize_traces" commandName="Synchronize Traces" description="Synchronize 2 or more traces" category="_drpNrqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0oaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.command.nextpage" commandName="Next Page of Memory" description="Load next page of memory" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0oqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.search.findrefs.project" commandName="References in Project" description="Searches for references to the selected element in the enclosing project" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0o6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.changelog.core.preparechangelog" commandName="Prepare Changelog" description="Prepares Changelog" category="_drpNqqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0pKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.removeTrailingWhitespace" commandName="Remove Trailing Whitespace" description="Removes the trailing whitespace of each line" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0paWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.GenerateDiff" commandName="Create Patch" description="Compare your workspace contents with the server and generate a diff file that can be used as a patch file." category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0pqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.dsf.debug.ui.disassembly.commands.gotoAddress" commandName="Go to Address..." description="Navigate to address" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0p6WTEe2ZZ82yKaHfjQ" elementId="rpmEditor.showOutline.command" commandName="Show outline" category="_drpNvKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0qKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.discoveryWizardCommand" commandName="%command.name" description="%command.description" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0qaWTEe2ZZ82yKaHfjQ" elementId="rpmstubby.stubifyFeature" commandName="Stub out an RPM specfile" description="Stub out an RPM specfile" category="_drpNnqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0qqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.showChangeRulerInformation" commandName="Show Quick Diff Ruler Tooltip" description="Displays quick diff or revision information for the caret line in a focused hover" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0q6WTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.importpackage.menucommand" commandName="Import Component(s)" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0rKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.views.uml2sd.handlers.ShowNodeEnd" commandName="Show node end" description="Show the node end" category="_drpNs6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0raWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewClone" commandName="Clone a Git Repository" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0rqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.command.exporttracepkg" commandName="Export Trace Package..." category="_drpNrqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0r6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.open.quick.type.hierarchy" commandName="Quick Type Hierarchy" description="Shows quick type hierarchy" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0sKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.enableChannelOnSession" commandName="Enable Channel..." description="Enable a Trace Channel" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0saWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.textStart" commandName="Select Text Start" description="Select to the beginning of the text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drp0sqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.groupDebugContexts" commandName="Group" description="Groups the selected debug contexts" category="_drpNtqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbsKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.cheatsheets.openCheatSheetURL" commandName="Open Cheat Sheet from URL" description="Open a Cheat Sheet from file at a specified URL." category="_drpNvaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drqbsaWTEe2ZZ82yKaHfjQ" elementId="cheatSheetId" name="Identifier" optional="false"/>
+    <parameters xmi:id="_drqbsqWTEe2ZZ82yKaHfjQ" elementId="name" name="Name" optional="false"/>
+    <parameters xmi:id="_drqbs6WTEe2ZZ82yKaHfjQ" elementId="url" name="URL" optional="false"/>
+  </commands>
+  <commands xmi:id="_drqbtKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewRefresh" commandName="Refresh" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbtaWTEe2ZZ82yKaHfjQ" elementId="rpmlint.runRpmlint.command" commandName="Run rpmlint" category="_drpNpKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbtqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.project.buildAll" commandName="Build All" description="Build all projects" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbt6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.lockToolBar" commandName="Lock the Toolbars" description="Lock the Toolbars" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbuKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.disableChannel" commandName="Disable Channel" description="Disable a Trace Channel" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbuaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.expandAll" commandName="Expand All" description="Expand the current tree" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbuqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.dsf.gdb.ui.command.selectNextTraceRecord" commandName="Next Trace Record" description="Select Next Trace Record" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbu6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.import" commandName="Import" description="Import" category="_drpNraWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drqbvKWTEe2ZZ82yKaHfjQ" elementId="importWizardId" name="Import Wizard"/>
+  </commands>
+  <commands xmi:id="_drqbvaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.lineEnd" commandName="Select Line End" description="Select to the end of the line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbvqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.help.helpSearch" commandName="Help Search" description="Open the help search" category="_drpNvaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbv6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.CompareWithHead" commandName="Compare with HEAD Revision" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbwKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.smartEnterInverse" commandName="Insert Line Above Current Line" description="Adds a new line above the current line" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbwaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.refactor.extract.local.variable" commandName="Extract Local Variable - Refactoring " description="Extracts a local variable for the selected expression" category="_drpNkaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbwqWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.InheritCommand" commandName="Inherit Component ..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbw6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.externalTools.commands.OpenExternalToolsConfigurations" commandName="External Tools..." description="Open external tools launch configuration dialog" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbxKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.windowEnd" commandName="Window End" description="Go to the end of the window" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbxaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.tm.terminal.paste" commandName="Paste" category="_drpNvqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbxqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.update" commandName="Update" description="Update resources with new content from the repository" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbx6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.add.include" commandName="Add Include" description="Create include statement on selection" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbyKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.ui.TeamSynchronizingPerspective" commandName="Team Synchronizing" description="Open the Team Synchronizing Perspective" category="_dromgKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbyaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.application.command.debugAttachedExecutable" commandName="Debug Attached Executable" description="Debug an attached executable" category="_drpNtqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbyqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.help.ui.indexcommand" commandName="Index" description="Show Keyword Index" category="_drpNvaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqby6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.StepOver" commandName="Step Over" description="Step over" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbzKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.hover.backwardMacroExpansion" commandName="Back" description="Steps backward in macro expansions" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbzaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewOpenInEditor" commandName="Open in Editor" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqbzqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.wikitext.ui.convertToMarkupCommand" commandName="Generate Markup" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drqbz6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.wikitext.ui.targetLanguage" name="TargetLanguage" optional="false"/>
+  </commands>
+  <commands xmi:id="_drqb0KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.valgrind.launch.exportCommand" commandName="Export Valgrind Log Files" description="Exports Valgrind log output to a directory" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb0aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.RenameBranch" commandName="Rename Branch..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb0qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.addMemoryMonitor" commandName="Add Memory Block" description="Add memory block" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb06WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewRebase" commandName="Rebase on" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb1KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.addContextOnChannel" commandName="Add Context..." description="Add Context to Channel(s) and/or Event(s)" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb1aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.revertToSaved" commandName="Revert to Saved" description="Revert to the last saved state" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb1qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.command.new_folder" commandName="New Folder..." description="Create a new trace folder" category="_drpNrqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb16WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.markTaskReadGoToPreviousUnread" commandName="Mark Task Read and Go To Previous Unread Task" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb2KWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.scripteditor.commentSelection" commandName="commentSelection" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb2aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Rebase" commandName="Rebase on" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb2qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.pinEditor" commandName="Pin Editor" description="Pin the current editor" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb26WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.views.uml2sd.handlers.GoToMessage" commandName="Go to associated message" description="Go to the associated message" category="_drpNs6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb3KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.views.uml2sd.handlers.MoveSDLeft" commandName="Scroll left" description="Scroll left the sequence diagram" category="_drpNs6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb3aWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.projectpanel.project.properties" commandName="Properties" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb3qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.commit.Reword" commandName="Reword Commit" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb36WTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.scripteditor.openImplementation" commandName="openImplementation" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb4KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.context.ui.commands.open.context.dialog" commandName="Show Context Quick View" description="Show Context Quick View" category="_drpNpaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb4aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Tag" commandName="Tag" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb4qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.ShowRepositoriesView" commandName="Show Git Repositories View" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb46WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.folding.restore" commandName="Reset Structure" description="Resets the folding structure" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb5KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.restartWorkbench" commandName="Restart" description="Restart the workbench" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb5aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.export" commandName="Export" description="Export" category="_drpNraWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drqb5qWTEe2ZZ82yKaHfjQ" elementId="exportWizardId" name="Export Wizard"/>
+  </commands>
+  <commands xmi:id="_drqb56WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewConfigurePush" commandName="Configure Push..." category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drqb6KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.command.breakpointProperties" commandName="C/C++ Breakpoint Properties" description="View and edit properties for a given C/C++ breakpoint" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCwKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.lineDown" commandName="Select Line Down" description="Extend the selection to the next line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCwaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.resetPerspective" commandName="Reset Perspective" description="Reset the current perspective to its default state" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCwqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ltk.ui.refactoring.commands.renameResource" commandName="Rename Resource" description="Rename the selected resource and notify LTK participants." category="_drpNwaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCw6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.PushHeadToGerrit" commandName="Push Current Head to Gerrit" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCxKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.showContextMenu" commandName="Show Context Menu" description="Show the context menu" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCxaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.stash.drop" commandName="Delete Stashed Commit..." category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCxqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.savePerspective" commandName="Save Perspective As" description="Save the current perspective" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCx6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.ConfigureUpstreamPush" commandName="Configure Upstream Push" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCyKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.showInformation" commandName="Show Tooltip Description" description="Displays information for the current caret location in a focused hover" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCyaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.ide.markCompleted" commandName="Mark Completed" description="Mark the selected tasks as completed" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCyqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.ConfigureFetch" commandName="Configure Upstream Fetch" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCy6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.nextMemoryBlock" commandName="Next Memory Monitor" description="Show renderings from next memory monitor." category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCzKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.refactor.extract.constant" commandName="Extract Constant - Refactoring " description="Extracts a constant for the selected expression" category="_drpNkaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCzaWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.generate.menucommand" commandName="Generate Processor Expert Code" category="_drpNmqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCzqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.toggleOverwrite" commandName="Toggle Overwrite" description="Toggle overwrite mode" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrCz6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.textEnd" commandName="Text End" description="Go to the end of the text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC0KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.Squash" commandName="Squash Commits" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC0aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.showKeyAssist" commandName="Show Key Assist" description="Show the key assist dialog" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC0qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.delete" commandName="Delete" description="Delete the selection" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC06WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.saveAs" commandName="Save As" description="Save the current contents to another location" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC1KWTEe2ZZ82yKaHfjQ" elementId="rpmstubby.stubifyGem" commandName="Stub out an RPM specfile" description="Stub out an RPM specfile" category="_drpNnqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC1aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewChangeCredentials" commandName="Change Credentials" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC1qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.ide.showInSystemExplorer" commandName="Show In (System Explorer)" description="Show in system's explorer (file manager)" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC16WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.search.ui.performTextSearchWorkspace" commandName="Find Text in Workspace" description="Searches the files in the workspace for specific text." category="_drpNn6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC2KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.refactor.getters.and.setters" commandName="Generate Getters and Setters..." description="Generates getters and setters for a selected field" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC2aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.refactor.hide.method" commandName="Hide Member Function..." category="_drpNkaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC2qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.deactivateAllTasks" commandName="Deactivate Task" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC26WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.activateTask" commandName="Activate Task" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC3KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.openEditorDropDown" commandName="Quick Switch Editor" description="Open the editor drop down list" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC3aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.CreateTag" commandName="Create Tag..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC3qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.ProfileLast" commandName="Profile" description="Launch in profile mode" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC36WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.index.ui.command.ResetIndex" commandName="Refresh Search Index" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC4KWTEe2ZZ82yKaHfjQ" elementId="rpmstubby.stubifyMakefilePL" commandName="Stub out an RPM specfile" description="Stub out an RPM specfile" category="_drpNnqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC4aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.search.ui.performTextSearchFile" commandName="Find Text in File" description="Searches the files in the file for specific text." category="_drpNn6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC4qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.specific_content_assist.command" commandName="C/C++ Content Assist" description="A parameterizable command that invokes content assist with a single completion proposal category" category="_drpNoKWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drrC46WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.specific_content_assist.category_id" name="type" optional="false"/>
+  </commands>
+  <commands xmi:id="_drrC5KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.refactor.extract.function" commandName="Extract Function - Refactoring " description="Extracts a function for the selected list of expressions or statements" category="_drpNkaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC5aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewPaste" commandName="Paste Repository Path or URI" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC5qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.paste" commandName="Paste" description="Paste from the clipboard" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC56WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.enableChannel" commandName="Enable Channel" description="Enable a Trace Channel" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC6KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.previous" commandName="Previous" description="Navigate to the previous item" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC6aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewCopyPath" commandName="Copy Path to Clipboard" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC6qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Ignore" commandName="Ignore" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC66WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.reverseStepInto" commandName="Reverse Step Into" description="Perform Reverse Step Into" category="_drpNoqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC7KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.RemoveFromIndex" commandName="Remove from Git Index" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC7aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.open.quick.macro.explorer" commandName="Explore Macro Expansion" description="Opens a quick view for macro expansion exploration" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC7qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.lineUp" commandName="Line Up" description="Go up one line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC76WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.newQuickMenu" commandName="New menu" description="Open the New menu" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC8KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.context.ui.commands.attachment.retrieveContext" commandName="Retrieve Context Attachment" category="_drpNpaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC8aWTEe2ZZ82yKaHfjQ" elementId="rpmstubby.stubifyEgg" commandName="Stub out an RPM specfile" description="Stub out an RPM specfile" category="_drpNnqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC8qWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.ReqisterUnregisterCommand" commandName="ReqisterUnregister" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drrC86WTEe2ZZ82yKaHfjQ" elementId="ReqisterUnregister" name="ReqisterUnregister"/>
+  </commands>
+  <commands xmi:id="_drrC9KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.deleteNext" commandName="Delete Next" description="Delete the next character" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC9aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.deleteNextWord" commandName="Delete Next Word" description="Delete the next word" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC9qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.undo" commandName="Undo" description="Undo the last operation" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC96WTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.perspective.menucommand" commandName="Show Views" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC-KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.castToType" commandName="Cast To Type..." category="_drpNnKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC-aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.back" commandName="Back" description="Navigate back" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC-qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.DebugLast" commandName="Debug" description="Launch in debug mode" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC-6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.bugs.commands.newTaskFromMarker" commandName="New Task from Marker..." description="Report as Bug from Marker" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC_KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.autotools.ui.command.reconfigure" commandName="Reconfigure Project" description="Run configuration scripts for project" category="_dromgaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC_aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.markTaskRead" commandName="Mark Task Read" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC_qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.excludeCommand" commandName="Exclude from Build" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrC_6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.enableEventOnSession" commandName="Enable Event (default channel)..." description="Enable Event on Default Channel" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDAKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.ToggleLineBreakpoint" commandName="Toggle Line Breakpoint" description="Creates or removes a line breakpoint" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDAaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.editors.lineNumberToggle" commandName="Show Line Numbers" description="Toggle display of line numbers" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDAqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.context.ui.commands.task.attachContext" commandName="Attach Context" category="_drpNpaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDA6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.ToggleStepFilters" commandName="Use Step Filters" description="Toggles enablement of debug step filters" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDBKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesLinkWithSelection" commandName="Link with Selection" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDBaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.newEditor" commandName="New Editor" description="Open another editor on the active editor's input" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDBqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Fetch" commandName="Fetch" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDB6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.org.eclipse.egit.ui.AbortRebase" commandName="Abort Rebase" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDCKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.executeScript" commandName="Execute Command Script..." description="Execute Command Script" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDCaWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.importexport.import.components" commandName="Import Processor Expert Component Settings" description="Opens wizard for importing Processor Expert Component Settings" category="_drpNmqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDCqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.SetQuickdiffBaseline" commandName="Set quickdiff baseline" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDC6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.wordPrevious" commandName="Previous Word" description="Go to the previous word" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDDKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewDelete" commandName="Delete Repository" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDDaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.ShowBlame" commandName="Show Annotations" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDDqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.recenter" commandName="Recenter" description="Scroll cursor line to center, top and bottom" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDD6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.help.installationDialog" commandName="Installation Information" description="Open the installation dialog" category="_drpNvaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDEKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Pull" commandName="Pull" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDEaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.restoreDefaultType" commandName="Restore Original Type" description="View and edit properties for a given C/C++ breakpoint" category="_drpNnKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDEqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.CompareWithIndex" commandName="Compare with Git Index" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDE6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.application.command.debugCore" commandName="Debug Core File" description="Debug a corefile" category="_drpNtqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDFKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.shiftRight" commandName="Shift Right" description="Shift a block of text to the right" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDFaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.changelog.core.preparechangelog2" commandName="Prepare Changelog In Editor" description="Prepares ChangeLog in an editor" category="_drpNqqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDFqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.tag" commandName="Tag as Version" description="Tag the resources with a CVS version tag" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDF6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.indent" commandName="Indent Line" description="Indents the current line" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrDGKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.addRegisterGroup" commandName="Add RegisterGroup" description="Adds a Register Group" category="_drpNnaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp0KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.refresh" commandName="Refresh" description="Refresh the selected items" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp0aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.dsf.debug.ui.disassembly.commands.gotoPC" commandName="Go to Program Counter" description="Navigate to current program counter" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp0qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.Merge" commandName="Merge" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp06WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.search.ui.performTextSearchWorkingSet" commandName="Find Text in Working Set" description="Searches the files in the working set for specific text." category="_drpNn6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp1KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.delete.line.to.end" commandName="Delete to End of Line" description="Delete to the end of a line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp1aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.CreateBranch" commandName="Create Branch" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp1qWTEe2ZZ82yKaHfjQ" elementId="ilg.gnuarmeclipse.debug.gdbjtag.restart.commands.Restart" commandName="Restart" description="Restart a process or debug target without terminating and re-launching" category="_drpNp6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp16WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.deactivateSelectedTask" commandName="Deactivate Selected Task" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp2KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.nextEditor" commandName="Next Editor" description="Switch to the next editor" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp2aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.ShowBlame" commandName="Show Annotations" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp2qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.forward" commandName="Forward" description="Navigate forward" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp26WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.pageUp" commandName="Page Up" description="Go up one page" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp3KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.updateSwitch" commandName="Switch to Another Branch or Version" description="Switch to Another Branch or Version" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp3aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.closeAllSaved" commandName="Close All Saved" description="Close all saved editors" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp3qWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.deviceinit.command.selectpackage" commandName="Select Package" category="_drpNsqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp36WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.loadAllSymbols" commandName="Load Symbols For All" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp4KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.openFile" commandName="Open File" description="Opens a file" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp4aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.OpenRunConfigurations" commandName="Run..." description="Open run launch configuration dialog" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp4qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.AssumeUnchanged" commandName="Assume Unchanged" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp46WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.uncall" commandName="Uncall" description="Perform Uncall" category="_drpNoqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp5KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.deletePreviousWord" commandName="Delete Previous Word" description="Delete the previous word" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp5aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.deletePrevious" commandName="Delete Previous" description="Delete the previous character" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp5qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.SkipAllBreakpoints" commandName="Skip All Breakpoints" description="Sets whether or not any breakpoint should suspend execution" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp56WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.disableEvent" commandName="Disable Event" description="Disable Event" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp6KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.application.command.debugNewExecutable" commandName="Debug New Executable" description="Debug a new executable" category="_drpNtqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp6aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.set.mark" commandName="Set Mark" description="Set the mark" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp6qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.OpenCommit" commandName="Open Git Commit" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp66WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.RenameBranch" commandName="Rename Branch" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp7KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.menu.rebuildIndex" commandName="Rebuild Index" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp7aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.AddToIndex" commandName="Add to Git Index" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp7qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.epp.mpc.ui.command.showMarketplaceWizard" commandName="Eclipse Marketplace" description="Show the Eclipse Marketplace wizard" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp76WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.exit" commandName="Exit" description="Exit the application" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp8KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.navigate.open.type.in.hierarchy" commandName="Open Type in Hierarchy" description="Open a type in the type hierarchy view" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp8aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.ConfigurePush" commandName="Configure Upstream Push" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp8qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.customizePerspective" commandName="Customize Perspective" description="Customize the current perspective" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp86WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.showInQuickMenu" commandName="Show In..." description="Open the Show In menu" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp9KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.organize.includes" commandName="Organize Includes" description="Evaluates all required includes and replaces the current includes" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp9aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.ide.deleteCompleted" commandName="Delete Completed Tasks" description="Delete the tasks marked as completed" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp9qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.DebugPerspective" commandName="Debug" description="Open the debug perspective" category="_dromgKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp96WTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.componentwizard.menucommand" commandName="Component Wizard" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp-KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.rename" commandName="Rename" description="Rename the selected item" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp-aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ltk.ui.refactoring.commands.deleteResources" commandName="Delete Resources" description="Delete the selected resources and notify LTK participants." category="_drpNwaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp-qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.CheckoutCommand" commandName="Checkout" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp-6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.maximizePart" commandName="Maximize Part" description="Maximize Part" category="_drpNsKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp_KWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.OpenComponentEditorCommand" commandName="Open Component Editor" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drrp_aWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.openWith" name="openWith"/>
+  </commands>
+  <commands xmi:id="_drrp_qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.next" commandName="Next" description="Navigate to the next item" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrp_6WTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.scripteditor.openInterface" commandName="openInterface" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqAKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.previousTask" commandName="Previous Task Command" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqAaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.project.buildAutomatically" commandName="Build Automatically" description="Toggle the workspace build automatically function" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqAqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.wikitext.ui.editor.showCheatSheetCommand" commandName="Show Markup Cheat Sheet" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqA6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.internal.reflog.OpenInCommitViewerCommand" commandName="Open in Commit Viewer" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqBKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.lineUp" commandName="Select Line Up" description="Extend the selection to the previous line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqBaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.ShowHistory" commandName="Show in History" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqBqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.replaceWithTag" commandName="Replace With Another Branch or Version" description="Replace with Branch or Version on the CVS Server" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqB6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.compare.compareWithOther" commandName="Compare With Other Resource" description="Compare resources, clipboard contents or editors" category="_drpNwKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqCKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.goto.next.bookmark" commandName="Next Bookmark" description="Goes to the next bookmark of the selected file" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqCaWTEe2ZZ82yKaHfjQ" elementId="com.somn.flash.commands.contextmenu" commandName="Flash from file..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqCqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.browser.openBundleResource" commandName="Open Resource in Browser" description="Opens a bundle resource in the default web browser." category="_drpNkKWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drrqC6WTEe2ZZ82yKaHfjQ" elementId="plugin" name="Plugin"/>
+    <parameters xmi:id="_drrqDKWTEe2ZZ82yKaHfjQ" elementId="path" name="Path"/>
+  </commands>
+  <commands xmi:id="_drrqDaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Push" commandName="Push" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqDqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.ContinueRebase" commandName="Continue Rebase" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqD6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.stash.apply" commandName="Apply Stashed Changes" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqEKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.compare.copyAllLeftToRight" commandName="Copy All from Left to Right" description="Copy All Changes from Left to Right" category="_drpNwKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqEaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.toggleShowWhitespaceCharacters" commandName="Show Whitespace Characters" description="Shows whitespace characters in current text editor" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqEqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.preferences" commandName="Preferences" description="Open the preferences dialog" category="_drpNkKWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drrqE6WTEe2ZZ82yKaHfjQ" elementId="preferencePageId" name="Preference Page"/>
+  </commands>
+  <commands xmi:id="_drrqFKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.selectAll" commandName="Select All" description="Select all" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqFaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.changelog.core.prepareCommit" commandName="Prepare Commit" description="Copies latest changelog entry to clipboard" category="_drpNqqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqFqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.close" commandName="Close" description="Close the active editor" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqF6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.internal.reflog.CopyCommand" commandName="Copy SHA-1" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqGKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.newWizard" commandName="New" description="Open the New item wizard" category="_drpNraWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drrqGaWTEe2ZZ82yKaHfjQ" elementId="newWizardId" name="New Wizard"/>
+  </commands>
+  <commands xmi:id="_drrqGqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.goToPreviousUnread" commandName="Go To Previous Unread Task" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqG6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.comment" commandName="Comment" description="Turns the selected lines into // style comments" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqHKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.managedbuilder.ui.buildFiles" commandName="Build Selected File(s)" description="Rebuilds the selected source files" category="_drpNmaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqHaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.help.ui.ignoreMissingPlaceholders" commandName="Do not warn of missing documentation" description="Sets the help preferences to no longer report a warning about the current set of missing documents." category="_drpNvaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqHqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.help.tipsAndTricksAction" commandName="Tips and Tricks" description="Open the tips and tricks help page" category="_drpNvaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqH6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.showHistory" commandName="Show History" description="Show History" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqIKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.wikitext.ui.convertToDocbookCommand" commandName="Generate Docbook" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqIaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.restoreRegisterGroups" commandName="Restore Default Register Groups" description="Restores the Default Register Groups" category="_drpNnaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqIqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.disconnect" commandName="Disconnect" description="Disconnect to Target Node" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqI6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.find.word" commandName="Find Word" description="Selects a word and find the next occurrence" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqJKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.copy" commandName="Copy" description="Copy the selection to the clipboard" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqJaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.deleteConfigsCommand" commandName="Reset to Default" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqJqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.Revert" commandName="Revert Commit" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqJ6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewCreateBranch" commandName="Create Branch..." category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqKKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.select.previous" commandName="Select Previous C/C++ Element" description="Expand the selection to enclosing C/C++ element" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqKaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.RunToLine" commandName="Run to Line" description="Resume and break when execution reaches the current line" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqKqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.import" commandName="Import..." description="Import Traces to LTTng Project" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqK6WTEe2ZZ82yKaHfjQ" elementId="rpmstubby.stubifyPom" commandName="Stub out an RPM specfile" description="Stub out an RPM specfile" category="_drpNnqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqLKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.UpdateRepositoryConfiguration" commandName="Update Repository Configuration" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqLaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.refactor.toggle.function" commandName="Toggle Function - Refactoring " description="Toggles the implementation between header and implementation file" category="_drpNkaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqLqWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.perspectivehide.menucommand" commandName="Hide Views" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqL6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.ide.copyConfigCommand" commandName="Copy Configuration Data To Clipboard" description="Copies the configuration data (system properties, installed bundles, etc) to the clipboard." category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqMKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.Restart" commandName="Restart" description="Restart a process or debug target without terminating and re-launching" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drrqMaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.part.previousPage" commandName="Previous Page" description="Switch to the previous page" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs38KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.openResource" commandName="Open Resource" description="Open an editor on a particular resource" category="_drpNwqWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drs38aWTEe2ZZ82yKaHfjQ" elementId="filePath" name="File Path" typeId="org.eclipse.ui.ide.resourcePath"/>
+  </commands>
+  <commands xmi:id="_drs38qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Synchronize" commandName="Synchronize" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs386WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.enableEvent" commandName="Enable Event" description="Enable Event" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs39KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.help.helpContents" commandName="Help Contents" description="Open the help contents" category="_drpNvaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs39aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.opencview" commandName="Show in C/C++ Project view" description="Shows the selected resource in the C/C++ Project view" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs39qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.reverseStepOver" commandName="Reverse Step Over" description="Perform Reverse Step Over" category="_drpNoqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs396WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.saveAll" commandName="Save All" description="Save all current contents" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs3-KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.views.uml2sd.handlers.MoveSDDown" commandName="Scroll down" description="Scroll down the sequence diagram" category="_drpNs6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs3-aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.GarbageCollect" commandName="Collect Garbage" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs3-qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.analysis.xml.ui.importxml" commandName="Import XML analysis" description="Import an XML file containing analysis information" category="_drpNrqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs3-6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.textEnd" commandName="Select Text End" description="Select to the end of the text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs3_KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.autotools.ui.command.autoheader" commandName="Invoke Autoheader" description="Run autoheader from the selected directory" category="_dromgaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs3_aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.delete.line" commandName="Delete Line" description="Delete a line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs3_qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.showViewMenu" commandName="Show View Menu" description="Show the view menu" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs3_6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.PushBranch" commandName="Push Branch..." category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4AKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.valgrind.launch.clearMarkersCommand" commandName="Remove Valgrind Markers" description="Removes all Valgrind markers" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4AaWTEe2ZZ82yKaHfjQ" elementId="rpmEditor.downloadSources.command" commandName="Download Sources" category="_drpNvKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4AqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.findIncremental" commandName="Incremental Find" description="Incremental find" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4A6WTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.projectpanel.components.snapshot" commandName="Snapshot Components..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4BKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.search.ui.performTextSearchProject" commandName="Find Text in Project" description="Searches the files in the project for specific text." category="_drpNn6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4BaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.managedbuilder.ui.convertTarget" commandName="Convert To" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4BqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.make.ui.targetBuildLastCommand" commandName="Rebuild Last Target" description="Rebuild the last make target for the selected container or project." category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4B6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.previousEditor" commandName="Previous Editor" description="Switch to the previous editor" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4CKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.DeleteBranch" commandName="Delete Branch..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4CaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.maximizePart" commandName="Maximize Active View or Editor" description="Toggles maximize/restore state of active view or editor" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4CqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.ide.configureColumns" commandName="Configure Columns..." description="Configure the columns in the markers view" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4C6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.debugNewExecutable" commandName="Debug New Executable" description="Debug a new executable" category="_drpNtqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4DKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.editors.revisions.id.toggle" commandName="Toggle Revision Id Display" description="Toggles the display of the revision id" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4DaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.folding.collapse_all" commandName="Collapse All" description="Collapses all folded regions" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4DqWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.scripteditor.openFileInSelectionDrivers" commandName="openFileInSelectionDrivers" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4D6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.commit.CherryPick" commandName="Cherry Pick" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4EKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.autotools.ui.command.libtoolize" commandName="Invoke Libtoolize" description="Run libtoolize in the selected directory" category="_dromgaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4EaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.perspectives.showPerspective" commandName="Show Perspective" description="Show a particular perspective" category="_dromgKWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drs4EqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.perspectives.showPerspective.perspectiveId" name="Parameter"/>
+    <parameters xmi:id="_drs4E6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.perspectives.showPerspective.newWindow" name="In New Window"/>
+  </commands>
+  <commands xmi:id="_drs4FKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.command.new_experiment" commandName="New..." description="Create Tracing Experiment" category="_drpNrqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4FaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.eof" commandName="EOF" description="Send end of file" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4FqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.rse.terminals.ui.actions.LaunchTerminalCommand" commandName="Launch Terminal " category="_drpNlaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4F6WTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.importexport.export.registersComponentsView" commandName="Export Registers" description="Opens wizard for exporting registers configuration" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4GKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.editors.quickdiff.revert" commandName="Revert Lines" description="Revert the current selection, block or deleted lines" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4GaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.previousSubTab" commandName="Previous Sub-Tab" description="Switch to the previous sub-tab" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4GqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.smartEnter" commandName="Insert Line Below Current Line" description="Adds a new line below the current line" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4G6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.pageDown" commandName="Page Down" description="Go down one page" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4HKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Reset" commandName="Reset..." category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4HaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.autotools.ui.command.aclocal" commandName="Invoke Aclocal" description="Run aclocal from the selected directory" category="_dromgaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4HqWTEe2ZZ82yKaHfjQ" elementId="rpmlint.toggleRpmlint.command" commandName="Toggle Rpmlint" category="_drpNpKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4H6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.windowStart" commandName="Window Start" description="Go to the start of the window" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4IKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.goInto" commandName="Go Into" description="Navigate into the selected item" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4IaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.stopTracing" commandName="Stop Tracing " description="Stop Tracing Experiment" category="_drpNpqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4IqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.ungroupDebugContexts" commandName="Ungroup" description="Ungroups the selected debug contexts" category="_drpNtqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4I6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.contentAssist.proposals" commandName="Content Assist" description="Content Assist" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4JKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.folding.expand_all" commandName="Expand All" description="Expands all folded regions" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4JaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.nextTab" commandName="Next Tab" description="Switch to the next tab" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4JqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.add.block.comment" commandName="Add Block Comment" description="Encloses the selection with a block comment" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4J6WTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.kds.newprojectwizard.menucommand" commandName="Kinetis Project" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4KKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Discard" commandName="Replace with File in Git Index" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4KaWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.MoveUpDownCommand" commandName="MoveUpDown" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drs4KqWTEe2ZZ82yKaHfjQ" elementId="MoveUpDown" name="MoveUpDown"/>
+  </commands>
+  <commands xmi:id="_drs4K6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.ide.OpenMarkersView" commandName="Open Another" description="Open another view" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4LKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.goto.matching.bracket" commandName="Go to Matching Bracket" description="Moves the cursor to the matching bracket" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4LaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.markTaskIncomplete" commandName="Mark Task Incomplete" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4LqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.command.delete_suppl_files" commandName="Delete Supplementary Files..." category="_drpNrqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4L6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.Terminate" commandName="Terminate" description="Terminate" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4MKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.new.local.task" commandName="New Local Task" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4MaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.NoAssumeUnchanged" commandName="No Assume Unchanged" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4MqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.openTask" commandName="Open Task" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4M6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.sort.lines" commandName="Sort Lines" description="Sort selected lines alphabetically" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4NKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.windowEnd" commandName="Select Window End" description="Select to the end of the window" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4NaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.command.gotoaddress" commandName="Go to Address" description="Go to Address" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4NqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.make.ui.edit.text.makefile.uncomment" commandName="Uncomment" description="Uncomment the selected # style comment lines" category="_drpNlKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4N6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.switchToEditor" commandName="Switch to Editor" description="Switch to an editor" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4OKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.Suspend" commandName="Suspend" description="Suspend" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4OaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.search.findrefs.workingset" commandName="References in Working Set" description="Searches for references to the selected element in a working set" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4OqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.command.shareProject" commandName="Share with Git" description="Share the project using Git" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drs4O6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.command.projectNameParameter" name="Project" optional="false"/>
+  </commands>
+  <commands xmi:id="_drs4PKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.previousView" commandName="Previous View" description="Switch to the previous view" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4PaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.views.uml2sd.handlers.MoveSDRight" commandName="Scroll right" description="Scroll right the sequence diagram" category="_drpNs6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4PqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.navigate.open.element.in.call.hierarchy" commandName="Open Element in Call Hierarchy" description="Open an element in the call hierarchy view" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4P6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.linkWithEditor" commandName="Toggle Link with Editor " description="Toggles linking of a view's selection with the active editor's selection" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4QKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.closeRendering" commandName="Close Rendering" description="Close the selected rendering." category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4QaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.ui.synchronizeAll" commandName="Synchronize..." description="Synchronize resources in the workspace with another location" category="_drpNo6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4QqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.help.displayHelp" commandName="Display Help" description="Display a Help topic" category="_drpNvaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drs4Q6WTEe2ZZ82yKaHfjQ" elementId="href" name="Help topic href"/>
+  </commands>
+  <commands xmi:id="_drs4RKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.previousPerspective" commandName="Previous Perspective" description="Switch to the previous perspective" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4RaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Branch" commandName="Branch" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4RqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.project.closeProject" commandName="Close Project" description="Close the selected project" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4R6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.context.ui.commands.task.clearContext" commandName="Clear Context" category="_drpNpaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4SKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.markTaskUnread" commandName="Mark Task Unread" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4SaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Disconnect" commandName="Disconnect" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4SqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.commitAll" commandName="Commit All Outgoing Changes" description="Commit all outgoing changes to the repository" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4S6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.refactoring.command.ExtractConstant" commandName="Extract Constant..." category="_drpNkaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4TKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.cvsPerspective" commandName="CVS Repository Exploring" description="Open the CVS Repository Exploring Perspective" category="_dromgKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4TaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.RefreshRepositoryTasks" commandName="Synchronize Changed" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4TqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.FetchGerritChange" commandName="Fetch From Gerrit" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4T6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.folding.expand" commandName="Expand" description="Expands the folded region at the current selection" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4UKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewRemove" commandName="Remove Repository" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4UaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.assign.event" commandName="Enable Event..." description="Assign Event to Session and Channel and Enable Event " category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4UqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.PushTags" commandName="Push Tags..." category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4U6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.rse.shells.ui.actions.LaunchShellCommand" commandName="Launch Shell" category="_drpNlaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4VKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.lineStart" commandName="Line Start" description="Go to the start of the line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4VaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.application.command.debugRemoteExecutable" commandName="Debug Remote Executable" description="Debug a Remote executable" category="_drpNtqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4VqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.select.next" commandName="Select Next C/C++ Element" description="Expand the selection to next C/C++ element" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4V6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.help.ui.closeTray" commandName="Close User Assistance Tray" description="Close the user assistance tray containing context help information and cheat sheets." category="_drpNvaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4WKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.project.properties" commandName="Properties" description="Display the properties of the selected item's project " category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4WaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.toggleBlockSelectionMode" commandName="Toggle Block Selection" description="Toggle block / column selection in the current text editor" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4WqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.save" commandName="Save" description="Save the current contents" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4W6WTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.scripteditor.openDefinedSymbols" commandName="openDefinedSymbols" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4XKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.checkout" commandName="Checkout from CVS" description="Checkout from CVS" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4XaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.CompareWithWorkingTree" commandName="Compare with Working Directory" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4XqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.context.ui.commands.task.copyContext" commandName="Copy Context" category="_drpNpaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4X6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.closePart" commandName="Close Part" description="Close the active workbench part" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4YKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.ToggleWatchpoint" commandName="Toggle Watchpoint" description="Creates or removes a watchpoint" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4YaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewConfigureBranch" commandName="Configure Branch" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4YqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.commit.Squash" commandName="Squash Commits" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4Y6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.compareWithRemote" commandName="Compare With Latest from Repository" description="Compare with Content on CVS Server" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4ZKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.OpenInCommitViewerCommand" commandName="Open in Commit Viewer" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4ZaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.viewSource.command" commandName="View Unformatted Text" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4ZqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.jdt.ui.edit.text.java.correction.assist.proposals" commandName="Quick Fix" description="Suggest possible fixes for a problem" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4Z6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.editors.revisions.rendering.cycle" commandName="Cycle Revision Coloring Mode" description="Cycles through the available coloring modes for revisions" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4aKWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.importexport.import.board" commandName="Apply Board Configuration" description="Opens wizard for importing Board Configuration" category="_drpNmqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4aaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.showRulerContextMenu" commandName="Show Ruler Context Menu" description="Show the context menu for the ruler" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4aqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.minimizePart" commandName="Minimize Active View or Editor" description="Minimizes the active view or editor" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4a6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.ToggleMethodBreakpoint" commandName="Toggle Method Breakpoint" description="Creates or removes a method breakpoint" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4bKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.command.offset_traces" commandName="Apply Time Offset..." description="Shift traces by a constant time offset" category="_drpNrqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4baWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Untrack" commandName="Untrack" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4bqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.menu.updateUnresolvedIncludes" commandName="Re-resolve Unresolved Includes" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4b6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.activateSelectedTask" commandName="Activate Selected Task" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4cKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.part.nextPage" commandName="Next Page" description="Switch to the next page" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4caWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.ReplaceWithRef" commandName="Replace with branch, tag, or reference" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4cqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.delete.line.to.beginning" commandName="Delete to Beginning of Line" description="Delete to the beginning of a line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4c6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.tm.terminal.maximize" commandName="Maximize Active View or Editor" category="_drpNvqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4dKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.backwardHistory" commandName="Backward History" description="Move backward in the editor navigation history" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4daWTEe2ZZ82yKaHfjQ" elementId="rpmEditor.toggleComment.command" commandName="Toggle Comment" category="_drpNvKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4dqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.swap.mark" commandName="Swap Mark" description="Swap the mark with the cursor position" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4d6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.refactoring.command.ExtractLocalVariable" commandName="Extract Local Variable..." category="_drpNkaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4eKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.commons.ui.command.AddRepository" commandName="Add Repository" category="_drpNuKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4eaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.replaceWithRevision" commandName="Replace With Revision" description="Replace with Revision on CVS Server" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4eqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.project.buildProject" commandName="Build Project" description="Build the selected project" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4e6WTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.scripteditor.openFileInSelection" commandName="openFileInSelection" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4fKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.compareWithRevision" commandName="Compare With Revision" description="Compare with Revision on CVS Server" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4faWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.saveTraceData" commandName="Save Trace Data " description="Save Trace Data to File" category="_drpNpqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4fqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.showSystemMenu" commandName="Show System Menu" description="Show the system menu" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4f6WTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.ImportExportCommand" commandName="ImportExport" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drs4gKWTEe2ZZ82yKaHfjQ" elementId="ImportExport" name="ImportExport"/>
+  </commands>
+  <commands xmi:id="_drs4gaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.lowerCase" commandName="To Lower Case" description="Changes the selection to lower case" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4gqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.goto.next.member" commandName="Go to Next Member" description="Move the caret to the next member of the translation unit" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4g6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.pageDown" commandName="Select Page Down" description="Select to the bottom of the page" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4hKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.newRendering" commandName="New Rendering" description="Add a new rendering." category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4haWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.menu.freshenAllFiles" commandName="Freshen All Files in Index" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4hqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.equinox.p2.ui.discovery.commands.ShowBundleCatalog" commandName="Show Bundle Catalog" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drs4h6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.equinox.p2.ui.discovery.commands.DirectoryParameter" name="Directory URL"/>
+    <parameters xmi:id="_drs4iKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.equinox.p2.ui.discovery.commands.TagsParameter" name="Tags"/>
+  </commands>
+  <commands xmi:id="_drs4iaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.SimplePush" commandName="Push to Upstream" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4iqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.MergeTool" commandName="Merge Tool" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4i6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.open.hyperlink" commandName="Open Hyperlink" description="Opens the hyperlink at the caret location or opens a chooser if more than one hyperlink is available" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4jKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.OpenInTextEditorCommand" commandName="Open in Text Editor" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4jaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.openLocalFile" commandName="Open File..." description="Open a file" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4jqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.splitEditor" commandName="Toggle Split Editor" description="Split or join the currently active editor." category="_drpNkKWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drs4j6WTEe2ZZ82yKaHfjQ" elementId="Splitter.isHorizontal" name="Orientation" optional="false"/>
+  </commands>
+  <commands xmi:id="_drs4kKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.compare.selectPreviousChange" commandName="Select Previous Change" description="Select Previous Change" category="_drpNwKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4kaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.toggleShowSelectedElementOnly" commandName="Show Selected Element Only" description="Show Selected Element Only" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4kqWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.selector.copyComponent" commandName="Copy To..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4k6WTEe2ZZ82yKaHfjQ" elementId="rpmEditor.organizePatches.command" commandName="Organize patches" category="_drpNvKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4lKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.wordPrevious" commandName="Select Previous Word" description="Select the previous word" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4laWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.ToggleCoolbarAction" commandName="Toggle Toolbar Visibility" description="Toggles the visibility of the window toolbar" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4lqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.Reset" commandName="Reset..." category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drs4l6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.ResetMode" name="Reset mode" optional="false"/>
+  </commands>
+  <commands xmi:id="_drs4mKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RebaseInteractiveCurrent" commandName="%RebaseInteractiveCurrentHandler.name" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4maWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.branch" commandName="Branch" description="Branch" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4mqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.context.ui.commands.interest.increment" commandName="Make Landmark" description="Make Landmark" category="_drpNpaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4m6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.reverseToggle" commandName="Reverse Toggle" description="Toggle Reverse Debugging" category="_drpNoqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4nKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.CompareVersionsInTree" commandName="Compare in Tree" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4naWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.opendecl" commandName="Open Declaration" description="Opens an editor on the selected element's declaration(s)" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4nqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.project.openProject" commandName="Open Project" description="Open a project" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4n6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.cut" commandName="Cut" description="Cut the selection to the clipboard" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4oKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.commit.Edit" commandName="Edit Commit" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4oaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.moveLineDown" commandName="Move Lines Down" description="Moves the selected lines down" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4oqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.tm.terminal.copy" commandName="Copy" category="_drpNvqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4o6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.findReplace" commandName="Find and Replace" description="Find and replace text" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4pKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.quickdiff.toggle" commandName="Quick Diff Toggle" description="Toggles quick diff information display on the line number ruler" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4paWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.ui.applyPatch" commandName="Apply Patch..." description="Apply a patch to one or more workspace projects." category="_drpNo6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4pqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.new.subtask" commandName="New Subtask" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4p6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.compare.copyLeftToRight" commandName="Copy from Left to Right" description="Copy Current Change from Left to Right" category="_drpNwKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4qKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ltk.ui.refactoring.commands.moveResources" commandName="Move Resources" description="Move the selected resources and notify LTK participants." category="_drpNwaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4qaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.startTracing" commandName="Start Tracing " description="Start Tracing Experiment" category="_drpNpqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4qqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.enableEventOnChannel" commandName="Enable Event..." description="Enable Event" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4q6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewRenameBranch" commandName="Rename Branch..." category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4rKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.calibrate" commandName="Calibrate" description="Quantify LTTng overhead" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4raWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.toggleInsertMode" commandName="Toggle Insert Mode" description="Toggle insert mode" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4rqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.line" commandName="Go to Line" description="Go to a specified line of text" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4r6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.nextSubTab" commandName="Next Sub-Tab" description="Switch to the next sub-tab" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4sKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.toggleMarkOccurrences" commandName="Toggle Mark Occurrences" description="Toggles mark occurrences in C/C++ editors" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4saWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewRemoveRemote" commandName="Delete Remote" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4sqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.stash.create" commandName="Stash Changes" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4s6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.columnPrevious" commandName="Previous Column" description="Go to the previous column" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4tKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.externaltools.ExternalToolMenuDelegateToolbar" commandName="Run Last Launched External Tool" description="Runs the last launched external Tool" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4taWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Commit" commandName="Commit..." category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4tqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.search.findrefs" commandName="References" description="Searches for references to the selected element in the workspace" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4t6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.addBookmark" commandName="Add Bookmark" description="Add a bookmark" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4uKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.task.clearOutgoing" commandName="Clear Outgoing Changes" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4uaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.lineStart" commandName="Select Line Start" description="Select to the beginning of the line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4uqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.CheckoutCommand" commandName="Checkout" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4u6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.cut.line.to.end" commandName="Cut to End of Line" description="Cut to the end of a line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4vKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.createSession" commandName="Create Session..." description="Create a Trace Session" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4vaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.search.finddecl.project" commandName="Declaration in Project" description="Searches for declarations of the selected element in the enclosing project" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4vqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.context.ui.commands.task.retrieveContext" commandName="Retrieve Context" category="_drpNpaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4v6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.command.clear_offset" commandName="Clear Time Offset" description="Clear time offset" category="_drpNrqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4wKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewAddRepository" commandName="Add a Git Repository" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4waWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.hover.forwardMacroExpansion" commandName="Forward" description="Steps forward in macro expansions" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4wqWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.projectpanel.project.reload" commandName="Reload Project" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4w6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.autotools.ui.command.autoreconf" commandName="Invoke Autoreconf" description="Run autoreconf from the selected directory" category="_dromgaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4xKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.equinox.p2.ui.sdk.update" commandName="Check for Updates" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4xaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.findIncrementalReverse" commandName="Incremental Find Reverse" description="Incremental find reverse" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4xqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.project.rebuildAll" commandName="Rebuild All" description="Rebuild all projects" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4x6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.activateEditor" commandName="Activate Editor" description="Activate the editor" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4yKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.compare.copyAllRightToLeft" commandName="Copy All from Right to Left" description="Copy All Changes from Right to Left" category="_drpNwKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4yaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.enableChannelOnDomain" commandName="Enable Channel..." description="Enable a Trace Channel" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4yqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.PushCommit" commandName="Push Commit..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4y6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.reverseResume" commandName="Reverse Resume" description="Perform Reverse Resume" category="_drpNoqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4zKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.project.closeUnrelatedProjects" commandName="Close Unrelated Projects" description="Close unrelated projects" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4zaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.lineDown" commandName="Line Down" description="Go down one line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4zqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.compare.ignoreWhiteSpace" commandName="Ignore White Space" description="Ignore white space where applicable" category="_drpNwKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs4z6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.ToggleBreakpoint" commandName="Toggle Breakpoint" description="Creates or removes a breakpoint" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs40KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewConfigureGerritRemote" commandName="Gerrit Configuration..." category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs40aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.previousTab" commandName="Previous Tab" description="Switch to the previous tab" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs40qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.goToNextUnread" commandName="Go To Next Unread Task" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs406WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.gotoLastEditPosition" commandName="Last Edit Location" description="Last edit location" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs41KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.SkipRebase" commandName="Skip commit and continue" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs41aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.toggleMemoryMonitorsPane" commandName="Toggle Memory Monitors Pane" description="Toggle visibility of the Memory Monitors Pane" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs41qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RebaseCurrent" commandName="Rebase" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs416WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.newConnection" commandName="New Connection..." description="New Connection to Target Node" category="_drpNv6WTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drs42KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.lttng2.control.ui.remoteServicesIdParameter" name="Remote Services ID"/>
+    <parameters xmi:id="_drs42aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.lttng2.control.ui.connectionNameParameter" name="Connection Name"/>
+  </commands>
+  <commands xmi:id="_drs42qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.openSelectedTask" commandName="Open Selected Task" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs426WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.showToolTip" commandName="Show Tooltip Description" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs43KWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.importexport.export.components" commandName="Export Component Settings" description="Opens wizard for exporting Processor Expert Component Settings" category="_drpNmqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs43aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.changelog.core.formatChangeLog" commandName="Format ChangeLog" description="Formats ChangeLog" category="_drpNqqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs43qWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.disconnected" commandName="Disconnected" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs436WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.ignore" commandName="Add to .cvsignore" description="Ignore the Selected Resources when Synchronizing" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs44KWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.open.type.hierarchy" commandName="Open Type Hierarchy" description="Open a type hierarchy on the selected element" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drs44aWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.ide.copyBuildIdCommand" commandName="Copy Build Id To Clipboard" description="Copies the build id to the clipboard." category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfAKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.autotools.ui.command.autoconf" commandName="Invoke Autoconf" description="Run autoconf in the selected directory" category="_dromgaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfAaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.dialogs.openInputDialog" commandName="Open Input Dialog" description="Open an Input Dialog" category="_drpNtaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drtfAqWTEe2ZZ82yKaHfjQ" elementId="title" name="Title"/>
+    <parameters xmi:id="_drtfA6WTEe2ZZ82yKaHfjQ" elementId="message" name="Message"/>
+    <parameters xmi:id="_drtfBKWTEe2ZZ82yKaHfjQ" elementId="initialValue" name="Initial Value"/>
+    <parameters xmi:id="_drtfBaWTEe2ZZ82yKaHfjQ" elementId="cancelReturns" name="Return Value on Cancel"/>
+  </commands>
+  <commands xmi:id="_drtfBqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.ShowVersions" commandName="Open" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drtfB6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.CompareMode" name="Compare mode"/>
+  </commands>
+  <commands xmi:id="_drtfCKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.navigate.opentype" commandName="Open Element" description="Open an element in an Editor" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfCaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.attachment.open" commandName="Open Attachment" category="_drpNsKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfCqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.views.properties.NewPropertySheetCommand" commandName="Properties" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfC6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.gdbtrace.ui.command.project.trace.selectexecutable" commandName="Select Trace Executable..." description="Select executable binary file for a GDB trace" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfDKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.collapseAll" commandName="Collapse All" description="Collapse the current tree" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfDaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.folding.toggle" commandName="Toggle Folding" description="Toggles folding in the current editor" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfDqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.submodule.update" commandName="Update Submodule" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfD6WTEe2ZZ82yKaHfjQ" elementId="rpmEditor.prepareSources.command" commandName="Prepare Sources" category="_drpNvKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfEKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.StepIntoSelection" commandName="Step Into Selection" description="Step into the current selected statement" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfEaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.remove.block.comment" commandName="Remove Block Comment" description="Removes the block comment enclosing the selection" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfEqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.commit.Revert" commandName="Revert Commit" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfE6WTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.AddRemoveDriverCommand" commandName="AddRemoveDriver" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drtfFKWTEe2ZZ82yKaHfjQ" elementId="AddRemoveDriver" name="AddRemoveDriver"/>
+  </commands>
+  <commands xmi:id="_drtfFaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.addContextOnEvent" commandName="Add Context..." description="Add Context to Channel(s) and/or Event(s)" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfFqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.snapshot" commandName="Record Snapshot" description="Record a snapshot" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfF6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewCreateRepository" commandName="Create a Repository" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfGKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.revert" commandName="Revert" description="Revert to the last saved state" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfGaWTEe2ZZ82yKaHfjQ" elementId="rpmEditor.build.command" commandName="RPM Build Command" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drtfGqWTEe2ZZ82yKaHfjQ" elementId="buildType" name="buildType" optional="false"/>
+    <parameters xmi:id="_drtfG6WTEe2ZZ82yKaHfjQ" elementId="actOnEditor" name="actOnEditor"/>
+  </commands>
+  <commands xmi:id="_drtfHKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.scroll.lineDown" commandName="Scroll Line Down" description="Scroll down one line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfHaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.redo" commandName="Redo" description="Redo the last operation" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfHqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.StepInto" commandName="Step Into" description="Step into" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfH6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.SimpleFetch" commandName="Fetch from Upstream" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfIKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.commit.Checkout" commandName="Checkout" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfIaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.join.lines" commandName="Join Lines" description="Join lines of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfIqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.search.finddecl" commandName="Declaration" description="Searches for declarations of the selected element in the workspace" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfI6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.scroll.lineUp" commandName="Scroll Line Up" description="Scroll up one line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfJKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.TerminateAndRelaunch" commandName="Terminate and Relaunch" description="Terminate and Relaunch" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfJaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.equinox.p2.ui.sdk.installationDetails" commandName="Installation Details" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfJqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.print" commandName="Print" description="Print" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfJ6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.forwardHistory" commandName="Forward History" description="Move forward in the editor navigation history" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfKKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.pageUp" commandName="Select Page Up" description="Select to the top of the page" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfKaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.SynchronizeAll" commandName="Synchronize Changed" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfKqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.CompareWithPrevious" commandName="Compare with Previous Revision" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfK6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.menu.findUnresolvedIncludes" commandName="Search for Unresolved Includes" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfLKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.help.dynamicHelp" commandName="Dynamic Help" description="Open the dynamic help" category="_drpNvaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfLaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.commit" commandName="Commit" description="Commit resources to the repository" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfLqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.RunLast" commandName="Run" description="Launch in run mode" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfL6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.copyLineUp" commandName="Duplicate Lines" description="Duplicates the selected lines and leaves the selection unchanged" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfMKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.stop" commandName="Stop" description="Stop Trace Session" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfMaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.command.select_trace_type" commandName="Select Trace Type..." description="Select a trace type" category="_drpNrqWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drtfMqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.commandparameter.select_trace_type.bundle" name="Bundle" optional="false"/>
+    <parameters xmi:id="_drtfM6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.commandparameter.select_trace_type.type" name="Trace Type" optional="false"/>
+    <parameters xmi:id="_drtfNKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.commandparameter.select_trace_type.icon" name="Icon" optional="false"/>
+  </commands>
+  <commands xmi:id="_drtfNaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.commit.CreateBranch" commandName="Create Branch..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfNqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.removeFromWorkingSet" commandName="Remove From Working Set" description="Removes the selected object from a working set." category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfN6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.ReplaceWithCommit" commandName="Replace with commit" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfOKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.start" commandName="Start" description="Start Trace Session" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfOaWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.importexport.export.board" commandName="Export Board Configuration" description="Opens wizard for exporting Board Configuration" category="_drpNmqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfOqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.DeleteBranch" commandName="Delete Branch" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfO6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesToggleBranchHierarchy" commandName="Toggle Branch Representation" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfPKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.ApplyPatch" commandName="Apply Patch" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfPaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.markTaskComplete" commandName="Mark Task Complete" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfPqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.showRulerAnnotationInformation" commandName="Show Ruler Annotation Tooltip" description="Displays annotation information for the caret line in a focused hover" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfP6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.folding.collapse" commandName="Collapse" description="Collapses the folded region at the current selection" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfQKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.source.quickMenu" commandName="Show Source Quick Menu" description="Shows the source quick menu" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfQaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.commit.ShowInHistory" commandName="Show in History" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfQqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.equinox.p2.ui.sdk.install" commandName="Install New Software..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfQ6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.nextView" commandName="Next View" description="Switch to the next view" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfRKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.project.buildLast" commandName="Repeat Working Set Build" description="Repeat the last working set build" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfRaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.autotools.ui.command.automake" commandName="Invoke Automake" description="Run automake from the selected directory" category="_dromgaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfRqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.removeRegisterGroups" commandName="Remove Register Groups" description="Removes one or more Register Groups" category="_drpNnaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfR6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.textStart" commandName="Text Start" description="Go to the beginning of the text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfSKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.properties" commandName="Properties" description="Display the properties of the selected item" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfSaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.search.ui.openSearchDialog" commandName="Open Search Dialog" description="Open the Search dialog" category="_drpNn6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfSqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.actions.WatchCommand" commandName="Watch" description="Create a watch expression from the current selection and add it to the Expressions view" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfS6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.openWorkspace" commandName="Switch Workspace" description="Open the workspace selection dialog" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfTKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.editRegisterGroup" commandName="Edit Register Group" description="Edits a Register Group" category="_drpNnaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfTaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.moveLineUp" commandName="Move Lines Up" description="Moves the selected lines up" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfTqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.ide.configureFilters" commandName="Configure Contents..." description="Configure the filters to apply to the markers view" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfT6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.dsf.ui.addRegistersExpression" commandName="Add Expression Group > Registers" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfUKWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.DeployCommand" commandName="Deploy" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfUaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.open.outline" commandName="Show outline" description="Shows outline" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfUqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.copyLineDown" commandName="Copy Lines" description="Duplicates the selected lines and moves the selection to the copy" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfU6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.open.call.hierarchy" commandName="Open Call Hierarchy" description="Opens the call hierarchy for the selected element" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfVKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.menu.updateWithModifiedFiles" commandName="Update Index with Modified Files" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfVaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.connect" commandName="Connect" description="Connect to a process" category="_drpNtqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfVqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.wordNext" commandName="Next Word" description="Go to the next word" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfV6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.CherryPick" commandName="Cherry Pick" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfWKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.addLocation" commandName="Add Repository Location" description="Add a new CVS repository location" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfWaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.ConfigureUpstreamFetch" commandName="Configure Upstream Fetch" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfWqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.Merge" commandName="Merge" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfW6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.toggle.comment" commandName="Comment/Uncomment" description="Comments/Uncomments the selected lines" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfXKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.up" commandName="Up" description="Navigate up one level" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfXaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.ResetQuickdiffBaseline" commandName="Reset quickdiff baseline" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drtfXqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.ResetQuickdiffBaselineTarget" name="Reset target (HEAD, HEAD^1)" optional="false"/>
+  </commands>
+  <commands xmi:id="_drtfX6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.submodule.add" commandName="Add Submodule" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfYKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.make.ui.targetBuildCommand" commandName="Make Target Build" description="Invoke a make target build for the selected container." category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfYaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.openRemoteTask" commandName="Open Remote Task" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfYqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.hideShowEditors" commandName="Toggle Editor Area Visibility" description="Toggles the visibility of the editor area" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfY6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.closePerspective" commandName="Close Perspective" description="Close the current perspective" category="_drpNkKWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drtfZKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.closePerspective.perspectiveId" name="Perspective Id"/>
+  </commands>
+  <commands xmi:id="_drtfZaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.project.rebuildProject" commandName="Rebuild Project" description="Rebuild the selected projects" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfZqWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.deviceinit.commands.generate" commandName="Generate Code" category="_drpNsqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfZ6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.Edit" commandName="Edit Commit" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfaKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.move" commandName="Move..." description="Move the selected item" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfaaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.surround.with.quickMenu" commandName="Surround With Quick Menu" description="Shows the Surround With quick menu" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfaqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.clear.mark" commandName="Clear Mark" description="Clear the mark" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfa6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.updateAll" commandName="Update All Incoming Changes" description="Update all incoming changes with new content from the repository" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfbKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.addTaskRepository" commandName="Add Task Repository..." category="_drpNuaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drtfbaWTEe2ZZ82yKaHfjQ" elementId="connectorKind" name="Repository Type"/>
+  </commands>
+  <commands xmi:id="_drtfbqWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.importexport.export.registers" commandName="Export Registers" description="Opens wizard for exporting registers configuration" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfb6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.goto.prev.member" commandName="Go to Previous Member" description="Move the caret to the previous member of the translation unit" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfcKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.wikitext.ui.convertToHtmlCommand" commandName="Generate HTML" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfcaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.ReplaceWithHead" commandName="Replace with HEAD revision" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfcqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.command.analysis_help" commandName="Help" description="Help" category="_drpNrqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfc6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.OpenProfileConfigurations" commandName="Profile..." description="Open profile launch configuration dialog" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfdKWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.AddCommand" commandName="Add" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drtfdaWTEe2ZZ82yKaHfjQ" elementId="addParameter1" name="addParameter1"/>
+  </commands>
+  <commands xmi:id="_drtfdqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.cdt.ui.editor.folding.auto" commandName="Toggle Active Folding" description="Toggle Active Folding" category="_drpNsaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfd6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.managedbuilder.ui.buildAllConfigurations" commandName="Build All Configurations" category="_drpNmaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfeKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.cheatsheets.openCheatSheet" commandName="Open Cheat Sheet" description="Open a Cheat Sheet." category="_drpNvaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drtfeaWTEe2ZZ82yKaHfjQ" elementId="cheatSheetId" name="Identifier"/>
+  </commands>
+  <commands xmi:id="_drtfeqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.command.managecustomparsers" commandName="Manage Custom Parsers..." description="Manage Custom Parsers" category="_drpNl6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfe6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewOpen" commandName="Open" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtffKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.command.importtracepkg" commandName="Import Trace Package..." category="_drpNrqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtffaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesToggleBranchCommit" commandName="Toggle Latest Branch Commit" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtffqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.tm.terminal.command1" commandName="Terminal view insert" category="_drpNvqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtff6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.castToArray" commandName="Cast To Type..." category="_drpNnKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfgKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.contentAssist.contextInformation" commandName="Context Information" description="Show Context Information" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfgaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.CompareVersions" commandName="Compare with each other" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfgqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.browser.openBrowser" commandName="Open Browser" description="Opens the default web browser." category="_drpNkKWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drtfg6WTEe2ZZ82yKaHfjQ" elementId="url" name="URL"/>
+    <parameters xmi:id="_drtfhKWTEe2ZZ82yKaHfjQ" elementId="browserId" name="Browser Id"/>
+    <parameters xmi:id="_drtfhaWTEe2ZZ82yKaHfjQ" elementId="name" name="Browser Name"/>
+    <parameters xmi:id="_drtfhqWTEe2ZZ82yKaHfjQ" elementId="tooltip" name="Browser Tooltip"/>
+  </commands>
+  <commands xmi:id="_drtfh6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.wikitext.ui.convertToEclipseHelpCommand" commandName="Generate Eclipse Help (*.html and *-toc.xml)" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfiKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.columnNext" commandName="Select Next Column" description="Select the next column" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfiaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.select.last" commandName="Restore Last C/C++ Selection" description="Restore last selection in C/C++ editor" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfiqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.views.uml2sd.handlers.ShowNodeStart" commandName="Show node start " description="Show the node start" category="_drpNs6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfi6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.merge" commandName="Merge" description="Merge" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfjKWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.SelectGlobalCommand" commandName="Select Global" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfjaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.upperCase" commandName="To Upper Case" description="Changes the selection to upper case" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfjqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.loadSymbols" commandName="Load Symbols" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfj6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.context.ui.commands.focus.view" commandName="Focus View" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_drtfkKWTEe2ZZ82yKaHfjQ" elementId="viewId" name="View ID to Focus" optional="false"/>
+  </commands>
+  <commands xmi:id="_drtfkaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.DropToFrame" commandName="Drop to Frame" description="Drop to Frame" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfkqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.format" commandName="Format" description="Formats Source Code" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtfk6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewNewRemote" commandName="Create Remote..." category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_drtflKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.search.ui.openFileSearchPage" commandName="File Search" description="Open the Search dialog's file search page" category="_drpNn6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGEKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.command.resumeWithoutSignal" commandName="Resume Without Signal" description="Resume Without Signal" category="_drpNu6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGEaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.ui.synchronizeLast" commandName="Repeat last synchronization" description="Repeat the last synchronization" category="_drpNo6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGEqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.CreatePatch" commandName="Create Patch" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGE6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.managedbuilder.ui.cleanAllConfigurations" commandName="Clean All Configurations" category="_drpNmaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGFKWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.DisplayListCommand" commandName="Display List" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGFaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.clean" commandName="Clean..." category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGFqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.columnNext" commandName="Next Column" description="Go to the next column" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGF6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.searchForTask" commandName="Search Repository for Task" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGGKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.selectWorkingSets" commandName="Select Working Sets" description="Select the working sets that are applicable for this window." category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGGaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.help.aboutAction" commandName="About" description="Open the about dialog" category="_drpNvaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGGqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.context.ui.commands.interest.decrement" commandName="Make Less Interesting" description="Make Less Interesting" category="_drpNpaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGG6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.dsf.ui.addLocalsExpression" commandName="Add Expression Group > Local Variables" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGHKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.compare.copyRightToLeft" commandName="Copy from Right to Left" description="Copy Current Change from Right to Left" category="_drpNwKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGHaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.uncomment" commandName="Uncomment" description="Uncomments the selected // style comment lines" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGHqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.wikitext.ui.quickOutlineCommand" commandName="Quick Outline" description="Open a popup dialog with a quick outline of the current document" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGH6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.command.configureTrace" commandName="Configure Git Debug Trace" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGIKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.views.uml2sd.handlers.MoveSDUp" commandName="Scroll up" description="Scroll up the sequence diagram" category="_drpNs6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGIaWTEe2ZZ82yKaHfjQ" elementId="com.somn.flash.commands.flashconfigurations" commandName="Flash from file..." category="_drpNrKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGIqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.addContextOnDomain" commandName="Add Context..." description="Add Context to Channel(s) and/or Event(s)" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGI6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.compare.selectNextChange" commandName="Select Next Change" description="Select Next Change" category="_drpNwKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGJKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.dsf.debug.ui.disassembly.commands.rulerToggleBreakpoint" commandName="Toggle Breakpoint" description="Toggle breakpoint in disassembly ruler" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGJaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.search.finddecl.workingset" commandName="Declaration in Working Set" description="Searches for declarations of the selected element in a working set" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGJqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.newWindow" commandName="New Window" description="Open another window" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGJ6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.RemoveAllBreakpoints" commandName="Remove All Breakpoints" description="Removes all breakpoints" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGKKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.showResourceByPath" commandName="Show Resource in Navigator" description="Show a resource in the Navigator given its path" category="_drpNwqWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_druGKaWTEe2ZZ82yKaHfjQ" elementId="resourcePath" name="Resource Path" typeId="org.eclipse.ui.ide.resourcePath" optional="false"/>
+  </commands>
+  <commands xmi:id="_druGKqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.refactor.implement.method" commandName="Implement Method - Source Generation " description="Implements a method for a selected method declaration" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGK6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.make.ui.targetCreateCommand" commandName="Create Make Target" description="Create a new make build target for the selected container." category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGLKWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.AddGroupCommand" commandName="Add Group" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGLaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.dsf.gdb.ui.command.selectPreviousTraceRecord" commandName="Previous Trace Record" description="Select Previous Trace Record" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGLqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.shiftLeft" commandName="Shift Left" description="Shift a block of text to the left" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGL6WTEe2ZZ82yKaHfjQ" elementId="com.freescale.new4sdk.menucommand" commandName="Kinetis SDK 2.x Project" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGMKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.managedbuilder.ui.cleanFiles" commandName="Clean Selected File(s)" description="Deletes build output files for the selected source files" category="_drpNmaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGMaWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.scripteditor.openComponentScript" commandName="openComponentScript" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGMqWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.RefreshCommand" commandName="Refresh" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGM6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.showAnnotation" commandName="Show Annotation" description="Show Annotation" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGNKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.project.cleanAction" commandName="Build Clean" description="Discard old built state" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGNaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.activeContextInfo" commandName="Show activeContext Info" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGNqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.autotools.ui.editors.text.show.tooltip" commandName="Show Tooltip Description" description="Shows the tooltip description for the element at the cursor" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGN6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.replace" commandName="Replace With Latest from Repository" description="Replace with last committed content from CVS Server" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGOKWTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.commands.ImportComponentCommand" commandName="Import Component/Interface" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGOaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.compareWithTag" commandName="Compare With Another Branch or Version" description="Compare with a Branch or a Version on the CVS Server" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGOqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.findNext" commandName="Find Next" description="Find next item" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGO6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.delete" commandName="Delete" description="Delete Target Node" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGPKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.Disconnect" commandName="Disconnect" description="Disconnect" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGPaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.destroySession" commandName="Destroy Session..." description="Destroy a Trace Session" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGPqWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.synchronizestaticcode.menucommand" commandName="Synchronize Processor Expert Static Code" category="_drpNmqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGP6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.commit.CreateTag" commandName="Create Tag..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGQKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.make.ui.edit.text.makefile.comment" commandName="Comment" description="Turn the selected lines into # style comments" category="_drpNlKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGQaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.select.enclosing" commandName="Select Enclosing C/C++ Element" description="Expand the selection to enclosing C/C++ element" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGQqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.rpm.createrepo.executeCommand" commandName="Execute" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_druGQ6WTEe2ZZ82yKaHfjQ" elementId="executionType" name="executionType" optional="false"/>
+  </commands>
+  <commands xmi:id="_druGRKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.changelog.core.actions.KeyActionCommand" commandName="Insert ChangeLog entry" description="Insert a ChangeLog entry" category="_drpNqqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGRaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.setKeywordSubstitution" commandName="Change ASCII/Binary Property" description="Change whether the selected resources should be treated as ASCII or binary on the CVS Server" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGRqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.windowStart" commandName="Select Window Start" description="Select to the start of the window" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGR6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.c.toggle.source.header" commandName="Toggle Source/Header" description="Toggles between corresponding source and header files" category="_drpNuqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGSKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.internal.reflog.CheckoutCommand" commandName="Checkout" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGSaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.help.quickStartAction" commandName="Welcome" description="Show help for beginning users" category="_drpNvaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGSqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.addTask" commandName="Add Task..." description="Add a task" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGS6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.task.ui.editor.QuickOutline" commandName="Quick Outline" description="Show the quick outline for the editor input" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGTKWTEe2ZZ82yKaHfjQ" elementId="com.somn.projectconverter.commands.contextmenu" commandName="Convert CodeWarrior project file..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGTaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.closeAllPerspectives" commandName="Close All Perspectives" description="Close all open perspectives" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGTqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.context.ui.commands.toggle.focus.active.view" commandName="Focus on Active Task" description="Toggle the focus on active task for the active view" category="_drpNpaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGT6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.editors.quickdiff.revertLine" commandName="Revert Line" description="Revert the current line" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGUKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.command.select_traces" commandName="Select Traces..." description="Select Traces" category="_drpNrqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGUaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.command.prevpage" commandName="Previous Page of Memory" description="Load previous page of memory" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGUqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.refresh" commandName="Refresh" description="Refresh Node Configuration" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGU6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.findPrevious" commandName="Find Previous" description="Find previous item" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGVKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.views.showView" commandName="Show View" description="Shows a particular view" category="_drpNk6WTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_druGVaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.views.showView.viewId" name="View"/>
+    <parameters xmi:id="_druGVqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.views.showView.secondaryId" name="Secondary Id"/>
+    <parameters xmi:id="_druGV6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.views.showView.makeFast" name="As FastView"/>
+  </commands>
+  <commands xmi:id="_druGWKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.managedbuilder.ui.rebuildConfigurations" commandName="Build Selected Configurations" category="_drpNmaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGWaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.commands.viewMemory" commandName="View Memory" description="View variable in memory view" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGWqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.delimiter.windows" commandName="Convert Line Delimiters to Windows (CRLF, \r\n, 0D0A, &#xa4;&#xb6;)" description="Converts the line delimiters to Windows (CRLF, \r\n, 0D0A, &#xa4;&#xb6;)" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGW6WTEe2ZZ82yKaHfjQ" elementId="com.freescale.processorexpert.cde.ui.menucommand" commandName="New Component Wizard" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGXKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.cut.line" commandName="Cut Line" description="Cut a line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGXaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.columnPrevious" commandName="Select Previous Column" description="Select the previous column" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGXqWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.initsequence.showview" commandName="Initialization Sequence..." description="Shows View Edit Initialization Sequence" category="_drpNmqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGX6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.closeAll" commandName="Close All" description="Close all editors" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGYKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.cut.line.to.beginning" commandName="Cut to Beginning of Line" description="Cut to the beginning of a line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGYaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.text.rename.element" commandName="Rename - Refactoring " description="Renames the selected element" category="_drpNkaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGYqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.codan.commands.runCodanCommand" commandName="Run Code Analysis" category="_drpNqaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGY6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.select.wordNext" commandName="Select Next Word" description="Select the next word" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGZKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.goToResource" commandName="Go to" description="Go to a particular resource in the active view" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGZaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.spy" commandName="Show Contributing Plug-in" description="Shows contribution information for the currently selected element" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGZqWTEe2ZZ82yKaHfjQ" elementId="com.freescale.core.ide.license.freescaleLicenseCommand" commandName="Freescale Licenses" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGZ6WTEe2ZZ82yKaHfjQ" elementId="com.somniumtech.common.kds2projectconverter.commands.id" commandName="KDS Upgrade Assistant..." category="_drpNmKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGaKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.submodule.sync" commandName="Sync Submodule" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGaaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.quickAccess" commandName="Quick Access" description="Quickly access UI elements" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGaqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.connect" commandName="Connect" description="Connect to Target Node" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGa6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.dsf.debug.ui.refreshAll" commandName="Refresh Debug Views" description="Refresh all data in debug views" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGbKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.CompareIndexWithHead" commandName="Compare File in Git Index with HEAD Revision" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGbaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.StepReturn" commandName="Step Return" description="Step return" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGbqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.addToWorkingSet" commandName="Add to Working Set" description="Adds the selected object to a working set." category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGb6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.exportToText" commandName="Export To Text..." description="Export trace to text..." category="_drpNrqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGcKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.tm.terminal.quickaccess" commandName="Quick Access" category="_drpNvqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGcaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.markTaskReadGoToNextUnread" commandName="Mark Task Read and Go To Next Unread Task" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGcqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.goto.lineEnd" commandName="Line End" description="Go to the end of the line of text" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGc6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.team.CreatePatch" commandName="Create Patch" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGdKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewImportProjects" commandName="Import Projects..." description="Import or create in local Git repository" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGdaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.delimiter.unix" commandName="Convert Line Delimiters to Unix (LF, \n, 0A, &#xb6;)" description="Converts the line delimiters to Unix (LF, \n, 0A, &#xb6;)" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGdqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.showIn" commandName="Show In" category="_drpNwqWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_druGd6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.navigate.showIn.targetId" name="Show In Target Id" optional="false"/>
+  </commands>
+  <commands xmi:id="_druGeKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.submitTask" commandName="Submit Task" description="Submits the currently open task" category="_drpNsKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGeaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.command.task.clearActiveTime" commandName="Clear Active Time" category="_drpNuaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGeqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.enableEventOnDomain" commandName="Enable Event (default channel)..." description="Enable Event on Default Channel" category="_drpNv6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGe6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.discovery.ui.discoveryWizardCommand" commandName="Discovery Wizard" description="shows the connector discovery wizard" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGfKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.dialogs.openMessageDialog" commandName="Open Message Dialog" description="Open a Message Dialog" category="_drpNtaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_druGfaWTEe2ZZ82yKaHfjQ" elementId="title" name="Title"/>
+    <parameters xmi:id="_druGfqWTEe2ZZ82yKaHfjQ" elementId="message" name="Message"/>
+    <parameters xmi:id="_druGf6WTEe2ZZ82yKaHfjQ" elementId="imageType" name="Image Type Constant" typeId="org.eclipse.ui.dialogs.Integer"/>
+    <parameters xmi:id="_druGgKWTEe2ZZ82yKaHfjQ" elementId="defaultIndex" name="Default Button Index" typeId="org.eclipse.ui.dialogs.Integer"/>
+    <parameters xmi:id="_druGgaWTEe2ZZ82yKaHfjQ" elementId="buttonLabel0" name="First Button Label"/>
+    <parameters xmi:id="_druGgqWTEe2ZZ82yKaHfjQ" elementId="buttonLabel1" name="Second Button Label"/>
+    <parameters xmi:id="_druGg6WTEe2ZZ82yKaHfjQ" elementId="buttonLabel2" name="Third Button Label"/>
+    <parameters xmi:id="_druGhKWTEe2ZZ82yKaHfjQ" elementId="buttonLabel3" name="Fourth Button Label"/>
+    <parameters xmi:id="_druGhaWTEe2ZZ82yKaHfjQ" elementId="cancelReturns" name="Return Value on Cancel"/>
+  </commands>
+  <commands xmi:id="_druGhqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.equinox.p2.ui.discovery.commands.ShowRepositoryCatalog" commandName="Show Repository Catalog" category="_drpNoaWTEe2ZZ82yKaHfjQ">
+    <parameters xmi:id="_druGh6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.equinox.p2.ui.discovery.commands.RepositoryParameter" name="P2 Repository URI"/>
+  </commands>
+  <commands xmi:id="_druGiKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.window.nextPerspective" commandName="Next Perspective" description="Switch to the next perspective" category="_drpNkKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGiaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.OpenDebugConfigurations" commandName="Debug..." description="Open debug launch configuration dialog" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGiqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.edit.text.hippieCompletion" commandName="Word Completion" description="Context insensitive completion" category="_drpNoKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGi6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewClearCredentials" commandName="Clear Credentials" category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGjKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.edit.open.include.browser" commandName="Open Include Browser" description="Open an include browser on the selected element" category="_drpNwqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGjaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.add" commandName="Add to Version Control" description="Add the Selected Resources to Version Control" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGjqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.sync" commandName="Synchronize with Repository" description="Synchronize the workspace resources with those in the repository" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGj6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.file.closeOthers" commandName="Close Others" description="Close all editors except the one that is active" category="_drpNraWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGkKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.make.ui.edit.text.makefile.opendecl" commandName="Open declaration" description="Follow to the directive definition" category="_drpNlKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGkaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.editors.revisions.author.toggle" commandName="Toggle Revision Author Display" description="Toggles the display of the revision author" category="_drpNt6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGkqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.history.Reword" commandName="Reword Commit" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGk6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.replaceWithBase" commandName="Revert to Base" description="Revert to Base revisions" category="_dromgqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGlKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.wikitext.context.ui.editor.folding.auto" commandName="Toggle Active Folding" description="Toggle Active Folding" category="_drpNtKWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGlaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.RepositoriesViewConfigureFetch" commandName="Configure Fetch..." category="_drpNm6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGlqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.import" commandName="Import..." description="Import traces into project" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGl6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.commands.Resume" commandName="Resume" description="Resume" category="_drpNr6WTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_druGmKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.menu.createParserLog" commandName="Create Parser Log File" category="_drpNkqWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_du3gsKWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.kds.newprojectwizard.menucommand_duplicated" commandName="com.processorexpert.ui.kds.newprojectwizard.menucommand_duplicated"/>
+  <commands xmi:id="_d4cTcKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.debugActionSet/org.eclipse.cdt.debug.ui.actions.ResumeAtLine" commandName="Resume At Line (C/C++)" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4cTcaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.debugActionSet/org.eclipse.cdt.debug.ui.actions.MoveToLine" commandName="Move to Line (C/C++)" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4cTcqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.debugActionSet/org.eclipse.cdt.debug.ui.actions.ToggleInstructionStepMode" commandName="Instruction Stepping Mode" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4cTc6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.make.ui.updateActionSet/org.eclipse.cdt.make.ui.UpdateMakeAction" commandName="Update Old Make Project..." description="Update Old Make Project" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4dhkKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.make.ui.makeTargetActionSet/org.eclipse.cdt.make.ui.actions.buildLastTargetAction" commandName="Rebuild Last Target" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4dhkaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.make.ui.makeTargetActionSet/org.eclipse.cdt.make.ui.makeTargetAction" commandName="Build..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4eIoKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ltk.ui.refactor.show.refactoring.history" commandName="History..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4eIoaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ltk.ui.refactor.create.refactoring.script" commandName="Create Script..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4eIoqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ltk.ui.refactor.apply.refactoring.script" commandName="Apply Script..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4eIo6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.ui.SearchActionSet/org.eclipse.cdt.ui.actions.OpenCSearchPage" commandName="C/C++..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4eIpKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.ui.buildConfigActionSet/org.eclipse.cdt.ui.buildActiveConfigToolbarAction" commandName="Build Active Configuration" description="Build the active configurations of selected projects" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4eIpaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.ui.buildConfigActionSet/org.eclipse.cdt.ui.buildConfigToolbarAction" commandName="Active Build Configuration" description="Manage configurations for the current project" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4eIpqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.ui.buildConfigActionSet/org.eclipse.cdt.ui.manageConfigsAction2" commandName="Manage..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4eIp6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.ui.buildConfigActionSet/org.eclipse.cdt.ui.buildConfigMenuAction" commandName="Set Active" description="Change active build configuration for project(s)" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4eIqKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.ui.buildConfigActionSet/org.eclipse.cdt.ui.wsselection" commandName="Manage Working Sets..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4eIqaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.ui.CElementCreationActionSet/org.eclipse.cdt.ui.actions.NewTypeDropDown" commandName="Class..." description="New C++ Class" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4evsKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.ui.CElementCreationActionSet/org.eclipse.cdt.ui.actions.NewFileDropDown" commandName="Source File..." description="New C/C++ Source File" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4evsaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.ui.CElementCreationActionSet/org.eclipse.cdt.ui.actions.NewFolderDropDown" commandName="Source Folder..." description="New C/C++ Source Folder" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4evsqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.ui.CElementCreationActionSet/org.eclipse.cdt.ui.actions.NewProjectDropDown" commandName="Project..." description="New C/C++ Project" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4evs6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.launchActionSet/org.eclipse.debug.internal.ui.actions.RunWithConfigurationAction" commandName="Run As" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4evtKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.launchActionSet/org.eclipse.debug.internal.ui.actions.RunHistoryMenuAction" commandName="Run History" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4fWwKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.launchActionSet/org.eclipse.debug.internal.ui.actions.RunDropDownAction" commandName="Run" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4fWwaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.launchActionSet/org.eclipse.debug.internal.ui.actions.DebugWithConfigurationAction" commandName="Debug As" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4fWwqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.launchActionSet/org.eclipse.debug.internal.ui.actions.DebugHistoryMenuAction" commandName="Debug History" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4fWw6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.launchActionSet/org.eclipse.debug.internal.ui.actions.DebugDropDownAction" commandName="Debug" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4fWxKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.profileActionSet/org.eclipse.debug.internal.ui.actions.ProfileDropDownAction" commandName="Profile" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4fWxaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.profileActionSet/org.eclipse.debug.internal.ui.actions.ProfileWithConfigurationAction" commandName="Profile As" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4fWxqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.profileActionSet/org.eclipse.debug.internal.ui.actions.ProfileHistoryMenuAction" commandName="Profile History" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4f90KWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.doc.actionSet/org.eclipse.mylyn.tasks.ui.bug.report" commandName="Report Bug or Enhancement..." description="Report Bug or Enhancement" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4f90aWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.tasks.ui.navigation.additions/org.eclipse.mylyn.tasks.ui.navigate.task.history" commandName="Activate Previous Task" description="Activate Previous Task" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4f90qWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.ui.cheatsheets.actionSet/org.eclipse.ui.cheatsheets.actions.CheatSheetHelpMenuAction" commandName="Cheat Sheets..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4f906WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.rse.core.search.searchActionSet/org.eclipse.rse.core.search.searchAction" commandName="Remote..." description="Opens Remote Search dialog page for text and file searching on remote systems" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4f91KWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.search.searchActionSet/org.eclipse.search.OpenSearchDialogPage" commandName="Search..." description="Search" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4gk4KWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.team.ui.actionSet/org.eclipse.team.ui.synchronizeAll" commandName="Synchronize..." description="Synchronize..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4gk4aWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.team.ui.actionSet/org.eclipse.team.ui.ConfigureProject" commandName="Share Project..." description="Share the project with others using a version and configuration management system." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4gk4qWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.ui.externaltools.ExternalToolsSet/org.eclipse.ui.externaltools.ExternalToolMenuDelegateMenu" commandName="External Tools" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hL8KWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.CEditor.BreakpointRulerActions/org.eclipse.cdt.debug.ui.CEditor.RulerTobbleBreakpointAction" commandName="%Dummy.label" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hL8aWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.ui.editor.asm.AsmEditor.BreakpointRulerActions/org.eclipse.cdt.debug.ui.CEditor.RulerTobbleBreakpointAction" commandName="%Dummy.label" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hL8qWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.ui.texteditor.ruler.actions/org.eclipse.ui.texteditor.BookmarkRulerAction" commandName="dummy" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hL86WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.ui.texteditor.ruler.actions/org.eclipse.cdt.internal.ui.text.correction.CSelectRulerAction" commandName="dummy" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hL9KWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.ui.texteditor.ruler.actions/org.eclipse.ui.texteditor.SelectRulerAction" commandName="Text Editor Ruler Single-Click" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hL9aWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::com.processorexpert.ui.projectpanel.view.GenerateAction/com.processorexpert.ui.inspector.action.view.Generate2" commandName="Generate" description="Generate Processor Expert Code" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hL9qWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.debugview.toolbar/org.eclipse.cdt.debug.internal.ui.actions.ToggleInstructionStepModeActionDelegate" commandName="Instruction Stepping Mode" description="Instruction Stepping Mode" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hL96WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.debugView.menu/org.eclipse.cdt.debug.internal.ui.actions.ShowFullPathsAction" commandName="Show Full Paths" description="Show Full Paths" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hzAKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.breakpointView.menu/org.eclipse.cdt.debug.internal.ui.actions.ShowFullPathsAction" commandName="Show Full Paths" description="Show Full Paths" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hzAaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.breakpointView.menu/org.eclipse.cdt.debug.ui.addWatchpoint" commandName="Add Watchpoint (C/C++)..." description="Add Watchpoint (C/C++)" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hzAqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.breakpointView.menu/org.eclipse.cdt.debug.internal.ui.actions.AddEventBreakpointActionDelegate" commandName="Add Event Breakpoint (C/C++)..." description="Add Event Breakpoint (C/C++)" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hzA6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.breakpointView.menu/org.eclipse.cdt.debug.ui.addFunctionBreakpoint" commandName="Add Function Breakpoint (C/C++)..." description="Add Function Breakpoint (C/C++)" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hzBKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.variablesView.toolbar/org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate" commandName="Remove All Global Variables" description="Remove All Global Variables" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hzBaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.variablesView.toolbar/org.eclipse.cdt.debug.internal.ui.actions.RemoveGlobalsActionDelegate" commandName="Remove Global Variables" description="Remove Selected Global Variables" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hzBqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.variablesView.toolbar/org.eclipse.cdt.debug.internal.ui.actions.AddGlobalsActionDelegate" commandName="Add Global Variables..." description="Add Global Variables" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hzB6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.expression.toolbar/org.eclipse.pinclone.expression.pinDebugContext" commandName="Pin to Debug Context" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hzCKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.expression.toolbar/org.eclipse.pinclone.expression.clone" commandName="Open New View" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hzCaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.variable.toolbar/org.eclipse.pinclone.variable.pinDebugContext" commandName="Pin to Debug Context" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4hzCqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.variable.toolbar/org.eclipse.pinclone.variable.clone" commandName="Open New View" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4iaEKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.register.toolbar/org.eclipse.pinclone.register.pinDebugContext" commandName="Pin to Debug Context" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4iaEaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.register.toolbar/org.eclipse.pinclone.register.clone" commandName="Open New View" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4iaEqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.memoryView.toolbar/org.eclipse.cdt.debug.ui.memory.floatingpoint.preferenceaction" commandName="Floating Point Rendering Preferences ..." description="Floating Point Rendering Preferences ..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4iaE6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.memoryBrowser.toolbar/org.eclipse.pinclone.memoryBrowser.pinDebugContext" commandName="Pin to Debug Context" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4iaFKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.memoryBrowser.toolbar/org.eclipse.pinclone.memoryBrowser.clone" commandName="Open New View" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4iaFaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.memory.memorybrowser.MemoryBrowser.clearExpressionList/org.eclipse.cdt.debug.ui.memory.memorybrowser.ClearExpressionListActionID" commandName="Clear Expressions" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4iaFqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.MemoryView.findNext/org.eclipse.cdt.debug.ui.memory.search.FindNextAction" commandName="Find Next" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4iaF6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.MemoryView.findReplace/org.eclipse.cdt.debug.ui.memory.search.FindAction" commandName="Find/Replace..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4iaGKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.memory.memorybrowser.MemoryBrowser.findNext/org.eclipse.cdt.debug.ui.memory.search.FindNextAction" commandName="Find Next" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4iaGaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.memoryView.toolbar/org.eclipse.cdt.debug.ui.memory.traditional.preferenceaction" commandName="Traditional Rendering Preferences..." description="Traditional Rendering Preferences..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4iaGqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.memoryView.toolbar/org.eclipse.cdt.debug.ui.memory.transport.actions.ExportMemoryAction" commandName="Export" description="Export" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4jBIKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.memoryView.toolbar/org.eclipse.cdt.debug.ui.memory.transport.actions.ImportMemoryAction" commandName="Import" description="Import" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4jBIaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.memory.memorybrowser.MemoryBrowser.toolbar/org.eclipse.cdt.debug.ui.memory.transport.actions.ExportMemoryAction" commandName="Export" description="Export" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4jBIqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.memory.memorybrowser.MemoryBrowser.toolbar/org.eclipse.cdt.debug.ui.memory.transport.actions.ImportMemoryAction2" commandName="Import" description="Import" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4jBI6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.dsf.debug.ui.viewmodel.variables.update.Refresh/org.eclipse.cdt.dsf.debug.ui.variables.viewmodel.update.actions.refresh" commandName="Refresh" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4jBJKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.dsf.debug.ui.viewmodel.registers.update.Refresh/org.eclipse.cdt.dsf.debug.ui.registers.viewmodel.update.actions.refresh" commandName="Refresh" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4jBJaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.dsf.debug.ui.viewmodel.expressions.update.Refresh/org.eclipse.cdt.dsf.debug.ui.expressions.viewmodel.update.actions.refresh" commandName="Refresh" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4jBJqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.dsf.debug.ui.viewmodel.debugview.update.Refresh/org.eclipse.cdt.dsf.debug.ui.debugview.viewmodel.update.actions.refresh" commandName="Refresh" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4jBJ6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.disassembly.toolbar/org.eclipse.pinclone.disassembly.pinDebugContext" commandName="Pin to Debug Context" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4jBKKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.cdt.debug.ui.disassembly.toolbar/org.eclipse.pinclone.disassembly.clone" commandName="Open New View" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4jBKaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.cdt.ui.cview.contribution/org.eclipse.mylyn.cdt.ui.cview.focusActiveTask.action" commandName="Focus on Active Task" description="Focus only on elements in active Mylyn task" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4jBKqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.PulldownActions/org.eclipse.debug.ui.debugview.pulldown.ViewManagementAction" commandName="View Management..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4jBK6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.debugview.toolbar/org.eclipse.debug.ui.debugview.toolbar.removeAllTerminated" commandName="Remove All Terminated" description="Remove All Terminated Launches" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4joMKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.breakpointsview.toolbar/org.eclipse.debug.ui.breakpointsView.toolbar.removeAll" commandName="Remove All" description="Remove All Breakpoints" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4joMaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.breakpointsview.toolbar/org.eclipse.debug.ui.breakpointsView.toolbar.linkWithDebugView" commandName="Link with Debug View" description="Link with Debug View" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4joMqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.breakpointsview.toolbar/org.eclipse.debug.ui.breakpointsView.toolbar.workingSets" commandName="Working Sets..." description="Manage Working Sets" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4joM6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.breakpointsview.toolbar/org.eclipse.debug.ui.breakpointsView.toolbar.clearDefaultBreakpointGroup" commandName="Deselect Default Working Set" description="Deselect Default Working Set" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4joNKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.breakpointsview.toolbar/org.eclipse.debug.ui.breakpointsView.toolbar.setDefaultBreakpointGroup" commandName="Select Default Working Set..." description="Select Default Working Set" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4joNaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.breakpointsview.toolbar/org.eclipse.debug.ui.breakpointsView.toolbar.groupByAction" commandName="Group By" description="Show" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4kPQKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.expressionsView.toolbar/org.eclipse.debug.ui.expresssionsView.toolbar.removeAll" commandName="Remove All" description="Remove All Expressions" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4kPQaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.expressionsView.toolbar/org.eclipse.debug.ui.expresssionsView.toolbar.AddWatchExpression" commandName="Add Watch Expression..." description="Create a new watch expression" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4kPQqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.memoryView.toolbar/org.eclipse.debug.ui.PinMemoryBlockAction" commandName="Pin Memory Monitor" description="Pin Memory Monitor" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4kPQ6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.memoryView.toolbar/org.eclipse.debug.ui.NewMemoryViewAction" commandName="New Memory View" description="New Memory View" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4kPRKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.memoryView.toolbar/org.eclipse.debug.ui.togglemonitors" commandName="Toggle Memory Monitors Pane" description="Toggle Memory Monitors Pane" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4kPRaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.memoryView.toolbar/org.eclipse.debug.ui.linkrenderingpanes" commandName="Link Memory Rendering Panes" description="Link Memory Rendering Panes" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4kPRqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.memoryView.toolbar/org.eclipse.debug.ui.tablerendering.preferencesaction" commandName="Table Renderings Preferences..." description="&amp;Table Renderings Preferences..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4kPR6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.memoryView.toolbar/org.eclipse.debug.ui.togglesplitpane" commandName="Toggle Split Pane" description="Toggle Split Pane" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4kPSKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.memoryView.toolbar/org.eclipse.debug.ui.switchMemoryBlock" commandName="Switch Memory Monitor" description="Switch Memory Monitor" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4kPSaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.debug.ui.memoryView.toolbar/org.eclipse.debug.ui.memoryViewPreferencesAction" commandName="Preferences..." description="&amp;Preferences..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4kPSqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.context.ui.outline.contribution/org.eclipse.mylyn.context.ui.contentOutline.focus" commandName="Focus on Active Task" description="Focus on Active Task (Alt+click to reveal filtered elements)" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4k2UKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.ui.projectexplorer.filter/org.eclipse.mylyn.ide.ui.actions.focus.projectExplorer" commandName="Focus on Active Task" description="Focus on Active Task (Alt+click to reveal filtered elements)" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4k2UaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.ui.resource.navigator.filter/org.eclipse.mylyn.ide.ui.actions.focus.resourceNavigator" commandName="Focus on Active Task" description="Focus on Active Task (Alt+click to reveal filtered elements)" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4k2UqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.problems.contribution/org.eclipse.mylyn.ide.ui.actions.focus.markers.problems" commandName="Focus on Active Task" description="Focus on Active Task" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4k2U6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.markers.all.contribution/org.eclipse.mylyn.ide.ui.actions.focus.markers.all" commandName="Focus on Active Task" description="Focus on Active Task" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4k2VKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.markers.tasks.contribution/org.eclipse.mylyn.ide.ui.actions.focus.markers.tasks" commandName="Focus on Active Task" description="Focus on Active Task" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4k2VaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.markers.bookmarks.contribution/org.eclipse.mylyn.ide.ui.actions.focus.markers.bookmarks" commandName="Focus on Active Task" description="Focus on Active Task" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4k2VqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.tasks.ui.actions.view/org.eclipse.mylyn.tasks.ui.search.open" commandName="Search Repository..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4k2V6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.tasks.ui.actions.view/org.eclipse.mylyn.tasks.ui.synchronize.changed" commandName="Synchronize Changed" description="Synchronize Changed" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4k2WKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.tasks.ui.actions.view/org.eclipse.mylyn.tasks.ui.tasks.restore" commandName="Restore Tasks from History..." category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4ldYKWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.tasks.ui.actions.view/org.eclipse.mylyn.tasks.ui.open.repositories.view" commandName="Show Task Repositories View" description="Show Task Repositories View" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4ldYaWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.tasks.ui.actions.view/org.eclipse.mylyn.doc.legend.show.action" commandName="Show UI Legend" description="Show Tasks UI Legend" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4ldYqWTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.mylyn.tasks.ui.actions.view/org.eclipse.mylyn.context.ui.actions.tasklist.focus" commandName="Focus on Workweek" description="Focus on Workweek" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <commands xmi:id="_d4ldY6WTEe2ZZ82yKaHfjQ" elementId="AUTOGEN:::org.eclipse.rse.ui.view.systemView.toolbar/org.eclipse.rse.ui.view.systemView.toolbar.linkWithSystemView" commandName="Link with Editor" category="_drpNoaWTEe2ZZ82yKaHfjQ"/>
+  <addons xmi:id="_drUdfKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.e4.core.commands.service" contributorURI="platform:/plugin/org.eclipse.ui.workbench" contributionURI="bundleclass://org.eclipse.e4.core.commands/org.eclipse.e4.core.commands.CommandServiceAddon"/>
+  <addons xmi:id="_drUdfaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.e4.ui.contexts.service" contributorURI="platform:/plugin/org.eclipse.ui.workbench" contributionURI="bundleclass://org.eclipse.e4.ui.services/org.eclipse.e4.ui.services.ContextServiceAddon"/>
+  <addons xmi:id="_drUdfqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.e4.ui.bindings.service" contributorURI="platform:/plugin/org.eclipse.ui.workbench" contributionURI="bundleclass://org.eclipse.e4.ui.bindings/org.eclipse.e4.ui.bindings.BindingServiceAddon"/>
+  <addons xmi:id="_drUdf6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.e4.ui.workbench.commands.model" contributorURI="platform:/plugin/org.eclipse.ui.workbench" contributionURI="bundleclass://org.eclipse.e4.ui.workbench/org.eclipse.e4.ui.internal.workbench.addons.CommandProcessingAddon"/>
+  <addons xmi:id="_drUdgKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.e4.ui.workbench.contexts.model" contributorURI="platform:/plugin/org.eclipse.ui.workbench" contributionURI="bundleclass://org.eclipse.e4.ui.workbench/org.eclipse.e4.ui.internal.workbench.addons.ContextProcessingAddon"/>
+  <addons xmi:id="_drUdgaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.e4.ui.workbench.bindings.model" contributorURI="platform:/plugin/org.eclipse.ui.workbench" contributionURI="bundleclass://org.eclipse.e4.ui.workbench.swt/org.eclipse.e4.ui.workbench.swt.util.BindingProcessingAddon"/>
+  <addons xmi:id="_drUdgqWTEe2ZZ82yKaHfjQ" elementId="Cleanup Addon" contributorURI="platform:/plugin/org.eclipse.ui.workbench" contributionURI="bundleclass://org.eclipse.e4.ui.workbench.addons.swt/org.eclipse.e4.ui.workbench.addons.cleanupaddon.CleanupAddon"/>
+  <addons xmi:id="_drUdg6WTEe2ZZ82yKaHfjQ" elementId="DnD Addon" contributorURI="platform:/plugin/org.eclipse.ui.workbench" contributionURI="bundleclass://org.eclipse.e4.ui.workbench.addons.swt/org.eclipse.e4.ui.workbench.addons.dndaddon.DnDAddon"/>
+  <addons xmi:id="_drUdhKWTEe2ZZ82yKaHfjQ" elementId="MinMax Addon" contributorURI="platform:/plugin/org.eclipse.ui.workbench" contributionURI="bundleclass://org.eclipse.e4.ui.workbench.addons.swt/org.eclipse.e4.ui.workbench.addons.minmax.MinMaxAddon"/>
+  <addons xmi:id="_drUdhaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.workbench.addon.0" contributorURI="platform:/plugin/org.eclipse.ui.workbench" contributionURI="bundleclass://org.eclipse.e4.ui.workbench/org.eclipse.e4.ui.internal.workbench.addons.HandlerProcessingAddon"/>
+  <addons xmi:id="_drZV8KWTEe2ZZ82yKaHfjQ" elementId="SplitterAddon" contributionURI="bundleclass://org.eclipse.e4.ui.workbench.addons.swt/org.eclipse.e4.ui.workbench.addons.splitteraddon.SplitterAddon"/>
+  <categories xmi:id="_dromgKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.category.perspectives" name="Perspectives" description="Commands for opening perspectives"/>
+  <categories xmi:id="_dromgaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.autotools.ui.category.invokeAutotools" name="Invoke Autotools"/>
+  <categories xmi:id="_dromgqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.cvs.ui.actionSet" name="CVS" description="Actions that apply when working with CVS repositories"/>
+  <categories xmi:id="_drpNkKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.category.window" name="Window"/>
+  <categories xmi:id="_drpNkaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.category.refactoring" name="Refactor - C++" description="C/C++ Refactorings"/>
+  <categories xmi:id="_drpNkqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.category.project" name="Project"/>
+  <categories xmi:id="_drpNk6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.category.views" name="Views" description="Commands for opening views"/>
+  <categories xmi:id="_drpNlKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.make.ui.category.source" name="Makefile Source" description="Makefile Source Actions"/>
+  <categories xmi:id="_drpNlaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.rse.ui.commands.category" name="Remote Systems"/>
+  <categories xmi:id="_drpNlqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.wikitext.ui.editor.category" name="WikiText Markup Editing Commands" description="commands for editing lightweight markup"/>
+  <categories xmi:id="_drpNl6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.commands.parser.category" name="Parser Commands" description="Parser Commands"/>
+  <categories xmi:id="_drpNmKWTEe2ZZ82yKaHfjQ" elementId="com.somniumtech.common.kds2projectconverter.commands.category" name="KDS Upgrade Assistant..."/>
+  <categories xmi:id="_drpNmaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.managedbuilder.ui.category.build" name="C/C++ Build" description="C/C++ Build Actions"/>
+  <categories xmi:id="_drpNmqWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.keybinding.generatecode" name="Code Generation" description="Code Generation"/>
+  <categories xmi:id="_drpNm6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.egit.ui.commandCategory" name="Git"/>
+  <categories xmi:id="_drpNnKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.category.casting" name="Cast to Type or Array" description="Set of commands for displaying variables and expressions as other types or arrays."/>
+  <categories xmi:id="_drpNnaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.category.registerGrouping" name="Register Grouping commands" description="Set of commands for Register Grouping"/>
+  <categories xmi:id="_drpNnqWTEe2ZZ82yKaHfjQ" elementId="rpmstubby.commands" name="RPMStubby Commands" description="Commands for the RPM Stubby plugin"/>
+  <categories xmi:id="_drpNn6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.search.ui.category.search" name="Search" description="Search command category"/>
+  <categories xmi:id="_drpNoKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.category.edit" name="Edit"/>
+  <categories xmi:id="_drpNoaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.core.commands.categories.autogenerated" name="Uncategorized" description="Commands that were either auto-generated or have no category"/>
+  <categories xmi:id="_drpNoqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.category.reverseDebugging" name="Reverse Debugging Commands" description="Set of commands for Reverse Debugging"/>
+  <categories xmi:id="_drpNo6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.team.ui.category.team" name="Team" description="Actions that apply when working with a Team"/>
+  <categories xmi:id="_drpNpKWTEe2ZZ82yKaHfjQ" elementId="rpmlint.category" name="Rpmlint Commands" description="Specfile Editor Commands"/>
+  <categories xmi:id="_drpNpaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.context.ui.commands" name="Focused UI" description="Task-Focused Interface"/>
+  <categories xmi:id="_drpNpqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.category.tracing" name="Tracing Commands" description="Category for Tracing Commands"/>
+  <categories xmi:id="_drpNp6WTEe2ZZ82yKaHfjQ" elementId="ilg.gnuarmeclipse.debug.gdbjtag.restart.category" name="Run/Debug" description="Run/Debug command category"/>
+  <categories xmi:id="_drpNqKWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.keybinding.perspective" name="Code Generation" description="Bring Processor Expert Views"/>
+  <categories xmi:id="_drpNqaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.codan.ui.commands.category" name="Code Analysis"/>
+  <categories xmi:id="_drpNqqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.changelog" name="Changelog" description="Changelog key bindings"/>
+  <categories xmi:id="_drpNq6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.ide.markerContents" name="Contents" description="The category for menu contents"/>
+  <categories xmi:id="_drpNrKWTEe2ZZ82yKaHfjQ" elementId="com.somn.flash.commands.category" name="Flash Category"/>
+  <categories xmi:id="_drpNraWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.category.file" name="File"/>
+  <categories xmi:id="_drpNrqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.commands.category" name="Tracing" description="Tracing Commands"/>
+  <categories xmi:id="_drpNr6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.debug.ui.category.run" name="Run/Debug" description="Run/Debug command category"/>
+  <categories xmi:id="_drpNsKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.category.editor" name="Task Editor"/>
+  <categories xmi:id="_drpNsaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.cdt.ui.commands" name="CDT Context" description="CDT Task-Focused Interface Commands"/>
+  <categories xmi:id="_drpNsqWTEe2ZZ82yKaHfjQ" elementId="com.processorexpert.ui.deviceinit.commands.category" name="Sample Category"/>
+  <categories xmi:id="_drpNs6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.tmf.ui.views.uml2sd.category" name="UML2 Sequence Diagram Viewer Commands" description="UML2 Sequence Diagram Viewer Commands"/>
+  <categories xmi:id="_drpNtKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.wikitext.context.ui.commands" name="%commands.category.name" description="%commands.category.description"/>
+  <categories xmi:id="_drpNtaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.category.dialogs" name="Dialogs" description="Commands for opening dialogs"/>
+  <categories xmi:id="_drpNtqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.category.debugViewLayout" name="Debug View Layout Commands" description="Set of commands for controlling the Debug View Layout"/>
+  <categories xmi:id="_drpNt6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.category.textEditor" name="Text Editing" description="Text Editing Commands"/>
+  <categories xmi:id="_drpNuKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.commons.repositories.ui.category.Team" name="Team"/>
+  <categories xmi:id="_drpNuaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.mylyn.tasks.ui.commands" name="Task Repositories"/>
+  <categories xmi:id="_drpNuqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.ui.category.source" name="Source" description="Source commands"/>
+  <categories xmi:id="_drpNu6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.cdt.debug.ui.category.runControl" name="Run Control Commands" description="Set of commands for Run Control"/>
+  <categories xmi:id="_drpNvKWTEe2ZZ82yKaHfjQ" elementId="rpmEditor.category" name="Editor Commands" description="Specfile Editor Commands"/>
+  <categories xmi:id="_drpNvaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.category.help" name="Help"/>
+  <categories xmi:id="_drpNvqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.tm.terminal.category1" name="Terminal view commands" description="Terminal view commands"/>
+  <categories xmi:id="_drpNv6WTEe2ZZ82yKaHfjQ" elementId="org.eclipse.linuxtools.internal.lttng2.ui.commands.control.category" name="LTTng Trace Control Commands" description="LTTng Trace Control Commands"/>
+  <categories xmi:id="_drpNwKWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.compare.ui.category.compare" name="Compare" description="Compare command category"/>
+  <categories xmi:id="_drpNwaWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ltk.ui.category.refactoring" name="Refactoring"/>
+  <categories xmi:id="_drpNwqWTEe2ZZ82yKaHfjQ" elementId="org.eclipse.ui.category.navigate" name="Navigate"/>
+</application:Application>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.linuxtools.cdt.libhover/C/devhelp.libhover b/Workspace/.metadata/.plugins/org.eclipse.linuxtools.cdt.libhover/C/devhelp.libhover
new file mode 100644
index 0000000..c7a1e5c
Binary files /dev/null and b/Workspace/.metadata/.plugins/org.eclipse.linuxtools.cdt.libhover/C/devhelp.libhover differ
diff --git a/Workspace/.metadata/.plugins/org.eclipse.linuxtools.cdt.libhover/C/glibc_library.libhover b/Workspace/.metadata/.plugins/org.eclipse.linuxtools.cdt.libhover/C/glibc_library.libhover
new file mode 100644
index 0000000..c7dd073
Binary files /dev/null and b/Workspace/.metadata/.plugins/org.eclipse.linuxtools.cdt.libhover/C/glibc_library.libhover differ
diff --git a/Workspace/.metadata/.plugins/org.eclipse.rse.core/.log b/Workspace/.metadata/.plugins/org.eclipse.rse.core/.log
new file mode 100644
index 0000000..e69de29
diff --git a/Workspace/.metadata/.plugins/org.eclipse.rse.core/initializerMarks/org.eclipse.rse.internal.core.RSELocalConnectionInitializer.mark b/Workspace/.metadata/.plugins/org.eclipse.rse.core/initializerMarks/org.eclipse.rse.internal.core.RSELocalConnectionInitializer.mark
new file mode 100644
index 0000000..e69de29
diff --git a/Workspace/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.in-engr-iotlab3_28542/FP.local.files_0/node.properties b/Workspace/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.in-engr-iotlab3_28542/FP.local.files_0/node.properties
new file mode 100644
index 0000000..270af27
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.in-engr-iotlab3_28542/FP.local.files_0/node.properties
@@ -0,0 +1,57 @@
+# RSE DOM Node
+00-name=IN-ENGR-IOTLAB3\:local.files
+01-type=FilterPool
+03-attr.default=true
+03-attr.deletable=true
+03-attr.id=local.files
+03-attr.nonRenamable=false
+03-attr.owningParentName=null
+03-attr.release=200
+03-attr.singleFilterStringOnly=false
+03-attr.singleFilterStringOnlyESet=false
+03-attr.stringsCaseSensitive=true
+03-attr.supportsDuplicateFilterStrings=false
+03-attr.supportsNestedFilters=true
+03-attr.type=default
+06-child.00000.00-name=My Home
+06-child.00000.01-type=Filter
+06-child.00000.03-attr.default=false
+06-child.00000.03-attr.filterType=default
+06-child.00000.03-attr.id=My Home
+06-child.00000.03-attr.nonChangable=false
+06-child.00000.03-attr.nonDeletable=false
+06-child.00000.03-attr.nonRenamable=false
+06-child.00000.03-attr.promptable=false
+06-child.00000.03-attr.relativeOrder=0
+06-child.00000.03-attr.release=200
+06-child.00000.03-attr.singleFilterStringOnly=false
+06-child.00000.03-attr.stringsCaseSensitive=false
+06-child.00000.03-attr.stringsNonChangable=false
+06-child.00000.03-attr.supportsDuplicateFilterStrings=false
+06-child.00000.03-attr.supportsNestedFilters=true
+06-child.00000.06-child.00000.00-name=C\:\\Users\\pkalgaon\\*
+06-child.00000.06-child.00000.01-type=FilterString
+06-child.00000.06-child.00000.03-attr.default=false
+06-child.00000.06-child.00000.03-attr.string=C\:\\Users\\pkalgaon\\*
+06-child.00000.06-child.00000.03-attr.type=default
+06-child.00001.00-name=Drives
+06-child.00001.01-type=Filter
+06-child.00001.03-attr.default=false
+06-child.00001.03-attr.filterType=default
+06-child.00001.03-attr.id=Drives
+06-child.00001.03-attr.nonChangable=false
+06-child.00001.03-attr.nonDeletable=false
+06-child.00001.03-attr.nonRenamable=false
+06-child.00001.03-attr.promptable=false
+06-child.00001.03-attr.relativeOrder=0
+06-child.00001.03-attr.release=200
+06-child.00001.03-attr.singleFilterStringOnly=false
+06-child.00001.03-attr.stringsCaseSensitive=false
+06-child.00001.03-attr.stringsNonChangable=false
+06-child.00001.03-attr.supportsDuplicateFilterStrings=false
+06-child.00001.03-attr.supportsNestedFilters=true
+06-child.00001.06-child.00000.00-name=*
+06-child.00001.06-child.00000.01-type=FilterString
+06-child.00001.06-child.00000.03-attr.default=false
+06-child.00001.06-child.00000.03-attr.string=*
+06-child.00001.06-child.00000.03-attr.type=default
diff --git a/Workspace/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.in-engr-iotlab3_28542/H.local_16/node.properties b/Workspace/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.in-engr-iotlab3_28542/H.local_16/node.properties
new file mode 100644
index 0000000..08e0d40
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.in-engr-iotlab3_28542/H.local_16/node.properties
@@ -0,0 +1,25 @@
+# RSE DOM Node
+00-name=Local
+01-type=Host
+03-attr.description=
+03-attr.hostname=LOCALHOST
+03-attr.offline=false
+03-attr.promptable=false
+03-attr.systemType=org.eclipse.rse.systemtype.local
+03-attr.type=Local
+06-child.00000.00-name=Local Connector Service
+06-child.00000.01-type=ConnectorService
+06-child.00000.03-attr.group=Local Connector Service
+06-child.00000.03-attr.port=0
+06-child.00000.03-attr.useSSL=false
+06-child.00000.06-child.00000.00-name=Local Files
+06-child.00000.06-child.00000.01-type=SubSystem
+06-child.00000.06-child.00000.03-attr.hidden=false
+06-child.00000.06-child.00000.03-attr.type=local.files
+06-child.00000.06-child.00000.06-child.00000.00-name=IN-ENGR-IOTLAB3___IN-ENGR-IOTLAB3\:local.files
+06-child.00000.06-child.00000.06-child.00000.01-type=FilterPoolReference
+06-child.00000.06-child.00000.06-child.00000.03-attr.refID=local.files
+06-child.00000.06-child.00001.00-name=Local Shells
+06-child.00000.06-child.00001.01-type=SubSystem
+06-child.00000.06-child.00001.03-attr.hidden=false
+06-child.00000.06-child.00001.03-attr.type=local.shells
diff --git a/Workspace/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.in-engr-iotlab3_28542/node.properties b/Workspace/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.in-engr-iotlab3_28542/node.properties
new file mode 100644
index 0000000..0e30ad6
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.in-engr-iotlab3_28542/node.properties
@@ -0,0 +1,7 @@
+# RSE DOM Node
+00-name=IN-ENGR-IOTLAB3
+01-type=Profile
+03-attr.defaultPrivate=true
+03-attr.isActive=true
+05-ref.00000=FP.local.files_0
+05-ref.00001=H.local_16
diff --git a/Workspace/.metadata/.plugins/org.eclipse.rse.ui/.log b/Workspace/.metadata/.plugins/org.eclipse.rse.ui/.log
new file mode 100644
index 0000000..e69de29
diff --git a/Workspace/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml b/Workspace/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml
new file mode 100644
index 0000000..50f1edb
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<section name="Workbench">
+	<section name="quick_assist_proposal_size">
+	</section>
+</section>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/Workspace/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml
new file mode 100644
index 0000000..86c6995
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<section name="Workbench">
+	<section name="ExternalProjectImportWizard">
+		<item value="false" key="WizardProjectsImportPage.STORE_ARCHIVE_SELECTED"/>
+		<item value="false" key="WizardProjectsImportPage.STORE_COPY_PROJECT_ID"/>
+		<item value="false" key="WizardProjectsImportPage.STORE_NESTED_PROJECTS"/>
+		<list key="WizardProjectsImportPage.STORE_DIRECTORIES">
+			<item value="C:\Users\pkalgaon\Desktop\Workspace\GPIO"/>
+			<item value="C:\Users\pkalgaon\Desktop\Workspace\4part1"/>
+			<item value="C:\Freescale\KSDK_1.3.0\lib\ksdk_platform_lib\kds\K64F12"/>
+		</list>
+		<list key="WizardProjectsImportPage.STORE_ARCHIVES">
+			<item value=""/>
+		</list>
+	</section>
+</section>
diff --git a/Workspace/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/Workspace/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml
new file mode 100644
index 0000000..0824967
--- /dev/null
+++ b/Workspace/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<section name="Workbench">
+	<section name="org.eclipse.ui.internal.QuickAccess">
+		<item value="1260" key="dialogWidth"/>
+		<item value="737" key="dialogHeight"/>
+		<list key="orderedProviders">
+		</list>
+		<list key="textArray">
+		</list>
+		<list key="orderedElements">
+		</list>
+		<list key="textEntries">
+		</list>
+	</section>
+	<section name="ImportExportAction">
+		<item value="org.eclipse.ui.wizards.import.ExternalProject" key="ImportExportPage.STORE_SELECTED_IMPORT_WIZARD_ID"/>
+		<list key="ImportExportPage.STORE_EXPANDED_IMPORT_CATEGORIES">
+			<item value="org.eclipse.ui.Basic"/>
+		</list>
+	</section>
+</section>
diff --git a/Workspace/.metadata/version.ini b/Workspace/.metadata/version.ini
new file mode 100644
index 0000000..af499ed
--- /dev/null
+++ b/Workspace/.metadata/version.ini
@@ -0,0 +1,3 @@
+#Sun Feb 05 15:27:08 EST 2023
+org.eclipse.core.runtime=2
+org.eclipse.platform=4.4.2.v20150204-1700
diff --git a/Workspace/4part1/.cproject b/Workspace/4part1/.cproject
new file mode 100644
index 0000000..db35cd8
--- /dev/null
+++ b/Workspace/4part1/.cproject
@@ -0,0 +1,133 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1802811856">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1802811856" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<macros>
+					<stringMacro name="PROJECT_KSDK_PATH" type="VALUE_TEXT" value="C:\Freescale\KSDK_1.3.0"/>
+				</macros>
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="4part1" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1802811856" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1802811856." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.656910265" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.796637494" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1714945544" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1165110540" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.1263105726" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.277823424" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1026556311" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.max" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.966866235" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.975904448" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.1316482884" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.hard" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.341036961" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.fpv4spd16" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.988017157" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="GNU Tools for ARM Embedded Processors" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.1079691859" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.708971840" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.849129314" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1368088066" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.2137731026" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.1412504167" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.1943845231" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.1127192489" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.1819077788" name="Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" value="ar" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.661513161" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1791186537" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.2036116218" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder buildPath="${workspace_loc:/4part1}/Debug" id="ilg.gnuarmeclipse.managedbuild.cross.builder.1334130950" keepEnvironmentInBuildfile="false" name="Gnu Make Builder" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.951867785" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.1794484301" name="Use preprocessor" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.1349149942" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.698695929" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.616999998" name="Language standard" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.c99" valueType="enumerated"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.548831883" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;../Sources&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${PROJECT_KSDK_PATH}/platform/hal/inc&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../Project_Settings/Startup_Code&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/CMSIS/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices/MK64F12/include&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.2095125393" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="&quot;CPU_MK64FN1M0VMD12&quot;"/>
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.560430606" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1097552796" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.1706223245" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;../Sources&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../Project_Settings/Startup_Code&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/CMSIS/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices/MK64F12/include&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.1426480598" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="&quot;CPU_MK64FN1M0VMD12&quot;"/>
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.854967712" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.1696087855" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.1443988570" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.1079464894" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.1429249845" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.959444724" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.154406337" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="-specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs" valueType="string"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.260853481" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="&quot;MK64FN1M0xxx12_flash.ld&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs.328564800" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs" valueType="userObjs">
+									<listOptionValue builtIn="false" value="&quot;C:\Freescale\KSDK_1.3.0\lib\ksdk_platform_lib\kds\K64F12\debug\libksdk_platform.a&quot;"/>
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.997628175" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1244079227" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1886357308" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.189597559" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.2019914421" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.1959829632" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.1909660357" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1559454099" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.252498923" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.1014728790" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.2005177176" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="4part1.ilg.gnuarmeclipse.managedbuild.cross.target.elf.1945281639" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1802811856;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1802811856.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1097552796;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.854967712">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1802811856;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1802811856.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.698695929;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.560430606">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="refreshScope"/>
+</cproject>
diff --git a/Workspace/4part1/.cwGeneratedFileSetLog b/Workspace/4part1/.cwGeneratedFileSetLog
new file mode 100644
index 0000000..da94cd8
--- /dev/null
+++ b/Workspace/4part1/.cwGeneratedFileSetLog
@@ -0,0 +1,19 @@
+Sources/main.c
+Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
+SDK/platform/devices/MK64F12/include/MK64F12_extension.h
+SDK/platform/CMSIS/Include/arm_math.h
+SDK/platform/CMSIS/Include/core_cmSimd.h
+SDK/platform/devices/MK64F12/include/MK64F12.h
+SDK/platform/CMSIS/Include/core_cm4.h
+SDK/platform/CMSIS/Include/arm_common_tables.h
+SDK/platform/devices/MK64F12/include/MK64F12_features.h
+SDK/platform/devices/fsl_device_registers.h
+SDK/platform/CMSIS/Include/arm_const_structs.h
+SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
+SDK/platform/CMSIS/Include/core_cmFunc.h
+SDK/platform/CMSIS/Include/core_cmInstr.h
+Project_Settings/Startup_Code/system_MK64F12.h
+Project_Settings/Startup_Code/startup.c
+Project_Settings/Startup_Code/startup_MK64F12.S
+Project_Settings/Startup_Code/startup.h
+Project_Settings/Startup_Code/system_MK64F12.c
\ No newline at end of file
diff --git a/Workspace/4part1/.project b/Workspace/4part1/.project
new file mode 100644
index 0000000..df5a502
--- /dev/null
+++ b/Workspace/4part1/.project
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>4part1</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<variableList>
+		<variable>
+			<name>PROJECT_KSDK_PATH</name>
+			<value>file:/C:/Freescale/KSDK_1.3.0</value>
+		</variable>
+	</variableList>
+</projectDescription>
diff --git a/Workspace/4part1/.settings/com.freescale.processorexpert.derivative.prefs b/Workspace/4part1/.settings/com.freescale.processorexpert.derivative.prefs
new file mode 100644
index 0000000..60d5016
--- /dev/null
+++ b/Workspace/4part1/.settings/com.freescale.processorexpert.derivative.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+versionGenerated/versionGenerated=1.0.0.RT7_b1550-0615
diff --git a/Workspace/4part1/.settings/language.settings.xml b/Workspace/4part1/.settings/language.settings.xml
new file mode 100644
index 0000000..083ef79
--- /dev/null
+++ b/Workspace/4part1/.settings/language.settings.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1802811856" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="355957199812988073" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings Cross ARM" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/Workspace/4part1/Debug/4part1.elf b/Workspace/4part1/Debug/4part1.elf
new file mode 100644
index 0000000..4328f95
Binary files /dev/null and b/Workspace/4part1/Debug/4part1.elf differ
diff --git a/Workspace/4part1/Debug/4part1.map b/Workspace/4part1/Debug/4part1.map
new file mode 100644
index 0000000..eee7e7b
--- /dev/null
+++ b/Workspace/4part1/Debug/4part1.map
@@ -0,0 +1,1262 @@
+Archive member included because of file (symbol)
+
+C:/Freescale/KSDK_1.3.0/lib/ksdk_platform_lib/kds/K64F12/debug/libksdk_platform.a(fsl_gpio_hal.o)
+                              ./Sources/main.o (GPIO_HAL_SetPinDir)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-assert.o)
+                              ./Sources/main.o (__assert_func)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (exit)
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+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-assert.o) (fiprintf)
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+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_global_impure_ptr)
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+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (__libc_init_array)
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+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-vfprintf.o) (__swbuf_r)
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+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-assert.o) (abort)
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+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-wbuf.o) (_fflush_r)
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+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-vfprintf.o) (__sinit)
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+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-vfprintf.o) (__sfvwrite_r)
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+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-findfp.o) (_malloc_r)
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+ .ARM.attributes
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+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(kill.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(kill.o)
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+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(lseek.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(lseek.o)
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+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(read.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(read.o)
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+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(sbrk.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(sbrk.o)
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+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(write.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(write.o)
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+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
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+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .eh_frame      0x00000000        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+m_interrupts     0x00000000         0x00000400         xr
+m_flash_config   0x00000400         0x00000010         xr
+m_text           0x00000410         0x000ffbf0         xr
+m_data           0x1fff0000         0x00010000         rw
+m_data_2         0x20000000         0x00030000         rw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+LOAD ./Sources/main.o
+LOAD ./Project_Settings/Startup_Code/startup.o
+LOAD ./Project_Settings/Startup_Code/startup_MK64F12.o
+LOAD ./Project_Settings/Startup_Code/system_MK64F12.o
+LOAD C:/Freescale/KSDK_1.3.0/lib/ksdk_platform_lib/kds/K64F12/debug/libksdk_platform.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libstdc++_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libm.a
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000400                HEAP_SIZE = DEFINED (__heap_size__)?__heap_size__:0x400
+                0x00000400                STACK_SIZE = DEFINED (__stack_size__)?__stack_size__:0x400
+                0x00000000                M_VECTOR_RAM_SIZE = DEFINED (__ram_vector_table__)?0x400:0x0
+
+.interrupts     0x00000000      0x400
+                0x00000000                __VECTOR_TABLE = .
+                0x00000000                . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector    0x00000000      0x400 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000000                __isr_vector
+                0x00000400                . = ALIGN (0x4)
+
+.flash_config   0x00000400       0x10
+                0x00000400                . = ALIGN (0x4)
+ *(.FlashConfig)
+ .FlashConfig   0x00000400       0x10 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000410                . = ALIGN (0x4)
+
+.text           0x00000410     0x17a4
+                0x00000410                . = ALIGN (0x4)
+ *(.text)
+ .text          0x00000410       0x54 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .text          0x00000464       0x74 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00000464                _start
+                0x00000464                _mainCRTStartup
+ .text          0x000004d8       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x000004d8                Reset_Handler
+                0x000004e8                DebugMon_Handler
+                0x000004e8                I2C0_IRQHandler
+                0x000004e8                HardFault_Handler
+                0x000004e8                SysTick_Handler
+                0x000004e8                UART3_RX_TX_IRQHandler
+                0x000004e8                PendSV_Handler
+                0x000004e8                NMI_Handler
+                0x000004e8                UART0_RX_TX_IRQHandler
+                0x000004e8                I2C1_IRQHandler
+                0x000004e8                DMA2_IRQHandler
+                0x000004e8                ENET_Error_IRQHandler
+                0x000004e8                CAN0_Tx_Warning_IRQHandler
+                0x000004e8                PIT0_IRQHandler
+                0x000004e8                CAN0_ORed_Message_buffer_IRQHandler
+                0x000004e8                CMP2_IRQHandler
+                0x000004e8                LLWU_IRQHandler
+                0x000004e8                ENET_Receive_IRQHandler
+                0x000004e8                ENET_1588_Timer_IRQHandler
+                0x000004e8                UART2_RX_TX_IRQHandler
+                0x000004e8                SWI_IRQHandler
+                0x000004e8                ADC0_IRQHandler
+                0x000004e8                UsageFault_Handler
+                0x000004e8                I2S0_Tx_IRQHandler
+                0x000004e8                CMT_IRQHandler
+                0x000004e8                UART4_RX_TX_IRQHandler
+                0x000004e8                SPI1_IRQHandler
+                0x000004e8                DefaultISR
+                0x000004e8                DMA9_IRQHandler
+                0x000004e8                DMA14_IRQHandler
+                0x000004e8                CMP1_IRQHandler
+                0x000004e8                Reserved71_IRQHandler
+                0x000004e8                PORTD_IRQHandler
+                0x000004e8                PORTB_IRQHandler
+                0x000004e8                UART4_ERR_IRQHandler
+                0x000004e8                ADC1_IRQHandler
+                0x000004e8                I2C2_IRQHandler
+                0x000004e8                PIT2_IRQHandler
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+                0x00001b7c       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-findfp.o)
+                0x00001b7c                __sf_fake_stderr
+ *(.glue_7)
+ .glue_7        0x00000000        0x0 linker stubs
+ *(.glue_7t)
+ .glue_7t       0x00000000        0x0 linker stubs
+ *(.eh_frame)
+ .eh_frame      0x00001b9c        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.init)
+ .init          0x00001b9c        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x00001b9c                _init
+ .init          0x00001ba0        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ *(.fini)
+ .fini          0x00001ba8        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x00001ba8                _fini
+ .fini          0x00001bac        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00001bb4                . = ALIGN (0x4)
+
+.vfp11_veneer   0x00001bb4        0x0
+ .vfp11_veneer  0x00000000        0x0 linker stubs
+
+.v4_bx          0x00001bb4        0x0
+ .v4_bx         0x00000000        0x0 linker stubs
+
+.iplt           0x00001bb4        0x0
+ .iplt          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM            0x00001bb4        0x8
+                0x00001bb4                __exidx_start = .
+ *(.ARM.exidx*)
+ .ARM.exidx     0x00001bb4        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00001bbc                __exidx_end = .
+
+.rel.dyn        0x00001bbc        0x0
+ .rel.iplt      0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ctors          0x00001bbc        0x0
+                0x00001bbc                __CTOR_LIST__ = .
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+                0x00001bbc                __CTOR_END__ = .
+
+.dtors          0x00001bbc        0x0
+                0x00001bbc                __DTOR_LIST__ = .
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+                0x00001bbc                __DTOR_END__ = .
+
+.preinit_array  0x00001bbc        0x0
+                0x00001bbc                PROVIDE (__preinit_array_start, .)
+ *(.preinit_array*)
+                0x00001bbc                PROVIDE (__preinit_array_end, .)
+
+.init_array     0x00001bbc        0x4
+                0x00001bbc                PROVIDE (__init_array_start, .)
+ *(SORT(.init_array.*))
+ *(.init_array*)
+ .init_array    0x00001bbc        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x00001bc0                PROVIDE (__init_array_end, .)
+
+.fini_array     0x00001bc0        0x4
+                0x00001bc0                PROVIDE (__fini_array_start, .)
+ *(SORT(.fini_array.*))
+ *(.fini_array*)
+ .fini_array    0x00001bc0        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x00001bc4                PROVIDE (__fini_array_end, .)
+                0x00001bc4                __etext = .
+                0x00001bc4                __DATA_ROM = .
+
+.interrupts_ram
+                0x1fff0000        0x0
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __VECTOR_RAM__ = .
+                0x1fff0000                __interrupts_ram_start__ = .
+ *(.m_interrupts_ram)
+                0x1fff0000                . = (. + M_VECTOR_RAM_SIZE)
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __interrupts_ram_end__ = .
+                0x00000000                __VECTOR_RAM = DEFINED (__ram_vector_table__)?__VECTOR_RAM__:ORIGIN (m_interrupts)
+                0x00000000                __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED (__ram_vector_table__)?(__interrupts_ram_end__ - __interrupts_ram_start__):0x0
+
+.data           0x1fff0000       0x68 load address 0x00001bc4
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __DATA_RAM = .
+                0x1fff0000                __data_start__ = .
+ *(.data)
+ *(.data*)
+ .data.impure_data
+                0x1fff0000       0x60 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data._impure_ptr
+                0x1fff0060        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                0x1fff0060                _impure_ptr
+ *(.jcr*)
+ .jcr           0x1fff0064        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .jcr           0x1fff0064        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+                0x1fff0068                . = ALIGN (0x4)
+                0x1fff0068                __data_end__ = .
+                0x00001c2c                __DATA_END = (__DATA_ROM + (__data_end__ - __data_start__))
+                0x00100000                text_end = (ORIGIN (m_text) + 0xffbf0)
+                0x00000001                ASSERT ((__DATA_END <= text_end), region m_text overflowed with text and data)
+
+.igot.plt       0x1fff0068        0x0 load address 0x00001c2c
+ .igot.plt      0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.bss            0x1fff0068       0x2c load address 0x00001c2c
+                0x1fff0068                . = ALIGN (0x4)
+                0x1fff0068                __START_BSS = .
+                0x1fff0068                __bss_start__ = .
+ *(.bss)
+ .bss           0x1fff0068       0x1c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.bss*)
+ .bss.__malloc_sbrk_start
+                0x1fff0084        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-nano-mallocr.o)
+                0x1fff0084                __malloc_sbrk_start
+ .bss.__malloc_free_list
+                0x1fff0088        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-nano-mallocr.o)
+                0x1fff0088                __malloc_free_list
+ .bss.heap_end.4246
+                0x1fff008c        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(sbrk.o)
+ *(COMMON)
+ COMMON         0x1fff0090        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-reent.o)
+                0x1fff0090                errno
+                0x1fff0094                . = ALIGN (0x4)
+                0x1fff0094                __bss_end__ = .
+                0x1fff0094                __END_BSS = .
+
+.heap           0x20000000      0x400
+                0x20000000                . = ALIGN (0x8)
+                0x20000000                __end__ = .
+                0x20000000                PROVIDE (end, .)
+                0x20000000                __HeapBase = .
+                0x20000400                . = (. + HEAP_SIZE)
+ *fill*         0x20000000      0x400 
+                0x20000400                __HeapLimit = .
+
+.stack          0x20000400      0x400
+                0x20000400                . = ALIGN (0x8)
+                0x20000800                . = (. + STACK_SIZE)
+ *fill*         0x20000400      0x400 
+                0x20030000                __StackTop = (ORIGIN (m_data_2) + 0x30000)
+                0x2002fc00                __StackLimit = (__StackTop - STACK_SIZE)
+                0x20030000                PROVIDE (__stack, __StackTop)
+
+.ARM.attributes
+                0x00000000       0x30
+ *(.ARM.attributes)
+ .ARM.attributes
+                0x00000000       0x22 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .ARM.attributes
+                0x00000022       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .ARM.attributes
+                0x00000056       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.attributes
+                0x00000076       0x39 ./Sources/main.o
+ .ARM.attributes
+                0x000000af       0x39 ./Project_Settings/Startup_Code/startup.o
+ .ARM.attributes
+                0x000000e8       0x1f ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .ARM.attributes
+                0x00000107       0x39 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .ARM.attributes
+                0x00000140       0x39 C:/Freescale/KSDK_1.3.0/lib/ksdk_platform_lib/kds/K64F12/debug/libksdk_platform.a(fsl_gpio_hal.o)
+ .ARM.attributes
+                0x00000179       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-assert.o)
+ .ARM.attributes
+                0x000001ad       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .ARM.attributes
+                0x000001e1       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-fprintf.o)
+ .ARM.attributes
+                0x00000215       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .ARM.attributes
+                0x00000249       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .ARM.attributes
+                0x0000027d       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .ARM.attributes
+                0x000002b1       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-vfprintf.o)
+ .ARM.attributes
+                0x000002e5       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-vfprintf_i.o)
+ .ARM.attributes
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+ .ARM.attributes
+                0x0000034d       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-wsetup.o)
+ .ARM.attributes
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+ .ARM.attributes
+                0x000003b5       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-fflush.o)
+ .ARM.attributes
+                0x000003e9       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-findfp.o)
+ .ARM.attributes
+                0x0000041d       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-makebuf.o)
+ .ARM.attributes
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+ .ARM.attributes
+                0x00000485       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-nano-freer.o)
+ .ARM.attributes
+                0x000004b9       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-nano-mallocr.o)
+ .ARM.attributes
+                0x000004ed       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-sbrkr.o)
+ .ARM.attributes
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+ .ARM.attributes
+                0x00000555       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-signalr.o)
+ .ARM.attributes
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+ .ARM.attributes
+                0x000005bd       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-strlen.o)
+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
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+ .ARM.attributes
+                0x0000068d       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-isattyr.o)
+ .ARM.attributes
+                0x000006c1       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-lseekr.o)
+ .ARM.attributes
+                0x000006f5       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-readr.o)
+ .ARM.attributes
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+ .ARM.attributes
+                0x0000075d       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(close.o)
+ .ARM.attributes
+                0x00000791       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(fstat.o)
+ .ARM.attributes
+                0x000007c5       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(getpid.o)
+ .ARM.attributes
+                0x000007f9       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(isatty.o)
+ .ARM.attributes
+                0x0000082d       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(kill.o)
+ .ARM.attributes
+                0x00000861       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(lseek.o)
+ .ARM.attributes
+                0x00000895       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(read.o)
+ .ARM.attributes
+                0x000008c9       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(sbrk.o)
+ .ARM.attributes
+                0x000008fd       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(write.o)
+ .ARM.attributes
+                0x00000931       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .ARM.attributes
+                0x00000965       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
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+                0x00000999       0x22 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000001                ASSERT ((__StackLimit >= __HeapLimit), region m_data_2 overflowed with stack and heap)
+OUTPUT(4part1.elf elf32-littlearm)
+
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+ .debug_info    0x00000000      0x97b ./Sources/main.o
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+ .debug_info    0x00000d22       0x8c ./Project_Settings/Startup_Code/startup_MK64F12.o
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+
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+ .debug_abbrev  0x00000000      0x1ef ./Sources/main.o
+ .debug_abbrev  0x000001ef       0xfa ./Project_Settings/Startup_Code/startup.o
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+ .debug_frame   0x000006a4       0x28 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memchr-stub.o)
+ .debug_frame   0x000006cc       0x2c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-nano-freer.o)
+ .debug_frame   0x000006f8       0x2c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-nano-mallocr.o)
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+ .debug_frame   0x00000750       0xc0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-signal.o)
+ .debug_frame   0x00000810       0x3c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-signalr.o)
+ .debug_frame   0x0000084c       0x80 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-stdio.o)
+ .debug_frame   0x000008cc       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-strlen.o)
+ .debug_frame   0x000008ec       0x2c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-writer.o)
+ .debug_frame   0x00000918       0x2c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-closer.o)
+ .debug_frame   0x00000944       0x2c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-fstatr.o)
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+ .debug_frame   0x0000099c       0x2c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-lseekr.o)
+ .debug_frame   0x000009c8       0x2c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-readr.o)
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+ .debug_frame   0x00000a5c       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(fstat.o)
+ .debug_frame   0x00000a7c       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(getpid.o)
+ .debug_frame   0x00000a9c       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(isatty.o)
+ .debug_frame   0x00000abc       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(kill.o)
+ .debug_frame   0x00000adc       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(lseek.o)
+ .debug_frame   0x00000afc       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(read.o)
+ .debug_frame   0x00000b1c       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(sbrk.o)
+ .debug_frame   0x00000b3c       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(write.o)
+ .debug_frame   0x00000b5c       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+
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+ .stab          0x00000024       0x18 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(fstat.o)
+                                 0x24 (size before relaxing)
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+                                 0x24 (size before relaxing)
+ .stab          0x00000054       0x18 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(isatty.o)
+                                 0x24 (size before relaxing)
+ .stab          0x0000006c       0x18 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(kill.o)
+                                 0x24 (size before relaxing)
+ .stab          0x00000084       0x18 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(lseek.o)
+                                 0x24 (size before relaxing)
+ .stab          0x0000009c       0x18 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(read.o)
+                                 0x24 (size before relaxing)
+ .stab          0x000000b4       0x18 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(write.o)
+                                 0x24 (size before relaxing)
+
+.stabstr        0x00000000      0x1b9
+ .stabstr       0x00000000      0x1b9 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(close.o)
diff --git a/Workspace/4part1/Debug/Project_Settings/Startup_Code/startup.d b/Workspace/4part1/Debug/Project_Settings/Startup_Code/startup.d
new file mode 100644
index 0000000..09df623
--- /dev/null
+++ b/Workspace/4part1/Debug/Project_Settings/Startup_Code/startup.d
@@ -0,0 +1,38 @@
+Project_Settings/Startup_Code/startup.o: \
+ ../Project_Settings/Startup_Code/startup.c \
+ ../Project_Settings/Startup_Code/startup.h \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h
+
+../Project_Settings/Startup_Code/startup.h:
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
diff --git a/Workspace/4part1/Debug/Project_Settings/Startup_Code/startup.o b/Workspace/4part1/Debug/Project_Settings/Startup_Code/startup.o
new file mode 100644
index 0000000..ec78a69
Binary files /dev/null and b/Workspace/4part1/Debug/Project_Settings/Startup_Code/startup.o differ
diff --git a/Workspace/4part1/Debug/Project_Settings/Startup_Code/startup_MK64F12.d b/Workspace/4part1/Debug/Project_Settings/Startup_Code/startup_MK64F12.d
new file mode 100644
index 0000000..15e90f1
--- /dev/null
+++ b/Workspace/4part1/Debug/Project_Settings/Startup_Code/startup_MK64F12.d
@@ -0,0 +1,2 @@
+Project_Settings/Startup_Code/startup_MK64F12.o: \
+ ../Project_Settings/Startup_Code/startup_MK64F12.S
diff --git a/Workspace/4part1/Debug/Project_Settings/Startup_Code/startup_MK64F12.o b/Workspace/4part1/Debug/Project_Settings/Startup_Code/startup_MK64F12.o
new file mode 100644
index 0000000..42711d1
Binary files /dev/null and b/Workspace/4part1/Debug/Project_Settings/Startup_Code/startup_MK64F12.o differ
diff --git a/Workspace/4part1/Debug/Project_Settings/Startup_Code/subdir.mk b/Workspace/4part1/Debug/Project_Settings/Startup_Code/subdir.mk
new file mode 100644
index 0000000..6adee33
--- /dev/null
+++ b/Workspace/4part1/Debug/Project_Settings/Startup_Code/subdir.mk
@@ -0,0 +1,41 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Project_Settings/Startup_Code/startup.c \
+../Project_Settings/Startup_Code/system_MK64F12.c 
+
+S_UPPER_SRCS += \
+../Project_Settings/Startup_Code/startup_MK64F12.S 
+
+OBJS += \
+./Project_Settings/Startup_Code/startup.o \
+./Project_Settings/Startup_Code/startup_MK64F12.o \
+./Project_Settings/Startup_Code/system_MK64F12.o 
+
+C_DEPS += \
+./Project_Settings/Startup_Code/startup.d \
+./Project_Settings/Startup_Code/system_MK64F12.d 
+
+S_UPPER_DEPS += \
+./Project_Settings/Startup_Code/startup_MK64F12.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Project_Settings/Startup_Code/%.o: ../Project_Settings/Startup_Code/%.c
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM C Compiler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"C:\Freescale\KSDK_1.3.0/platform/hal/inc" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+Project_Settings/Startup_Code/%.o: ../Project_Settings/Startup_Code/%.S
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM GNU Assembler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+
diff --git a/Workspace/4part1/Debug/Project_Settings/Startup_Code/system_MK64F12.d b/Workspace/4part1/Debug/Project_Settings/Startup_Code/system_MK64F12.d
new file mode 100644
index 0000000..d0e2961
--- /dev/null
+++ b/Workspace/4part1/Debug/Project_Settings/Startup_Code/system_MK64F12.d
@@ -0,0 +1,35 @@
+Project_Settings/Startup_Code/system_MK64F12.o: \
+ ../Project_Settings/Startup_Code/system_MK64F12.c \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
diff --git a/Workspace/4part1/Debug/Project_Settings/Startup_Code/system_MK64F12.o b/Workspace/4part1/Debug/Project_Settings/Startup_Code/system_MK64F12.o
new file mode 100644
index 0000000..e7c7fc7
Binary files /dev/null and b/Workspace/4part1/Debug/Project_Settings/Startup_Code/system_MK64F12.o differ
diff --git a/Workspace/4part1/Debug/Sources/main.d b/Workspace/4part1/Debug/Sources/main.d
new file mode 100644
index 0000000..95c3b92
--- /dev/null
+++ b/Workspace/4part1/Debug/Sources/main.d
@@ -0,0 +1,49 @@
+Sources/main.o: ../Sources/main.c \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h \
+ C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_gpio_hal.h \
+ C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_sim_hal.h \
+ c:\freescale\ksdk_1.3.0\platform\hal\src\sim\mk64f12\fsl_sim_hal_mk64f12.h \
+ C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_port_hal.h \
+ C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_pit_hal.h
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
+
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_gpio_hal.h:
+
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_sim_hal.h:
+
+c:\freescale\ksdk_1.3.0\platform\hal\src\sim\mk64f12\fsl_sim_hal_mk64f12.h:
+
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_port_hal.h:
+
+C:\Freescale\KSDK_1.3.0/platform/hal/inc/fsl_pit_hal.h:
diff --git a/Workspace/4part1/Debug/Sources/main.o b/Workspace/4part1/Debug/Sources/main.o
new file mode 100644
index 0000000..b0d54b1
Binary files /dev/null and b/Workspace/4part1/Debug/Sources/main.o differ
diff --git a/Workspace/4part1/Debug/Sources/subdir.mk b/Workspace/4part1/Debug/Sources/subdir.mk
new file mode 100644
index 0000000..94c8a66
--- /dev/null
+++ b/Workspace/4part1/Debug/Sources/subdir.mk
@@ -0,0 +1,24 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Sources/main.c 
+
+OBJS += \
+./Sources/main.o 
+
+C_DEPS += \
+./Sources/main.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Sources/%.o: ../Sources/%.c
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM C Compiler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"C:\Freescale\KSDK_1.3.0/platform/hal/inc" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+
diff --git a/Workspace/4part1/Debug/makefile b/Workspace/4part1/Debug/makefile
new file mode 100644
index 0000000..f7382ea
--- /dev/null
+++ b/Workspace/4part1/Debug/makefile
@@ -0,0 +1,77 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include Sources/subdir.mk
+-include Project_Settings/Startup_Code/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C++_DEPS)),)
+-include $(C++_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+ifneq ($(strip $(ASM_DEPS)),)
+-include $(ASM_DEPS)
+endif
+ifneq ($(strip $(CC_DEPS)),)
+-include $(CC_DEPS)
+endif
+ifneq ($(strip $(CPP_DEPS)),)
+-include $(CPP_DEPS)
+endif
+ifneq ($(strip $(CXX_DEPS)),)
+-include $(CXX_DEPS)
+endif
+ifneq ($(strip $(C_UPPER_DEPS)),)
+-include $(C_UPPER_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables 
+SECONDARY_SIZE += \
+4part1.siz \
+
+
+# All Target
+all: 4part1.elf secondary-outputs
+
+# Tool invocations
+4part1.elf: $(OBJS) $(USER_OBJS)
+	@echo 'Building target: $@'
+	@echo 'Invoking: Cross ARM C++ Linker'
+	arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -T "MK64FN1M0xxx12_flash.ld" -Xlinker --gc-sections -L"C:/Users/pkalgaon/Desktop/Workspace/4part1/Project_Settings/Linker_Files" -Wl,-Map,"4part1.map" -specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs -o "4part1.elf" $(OBJS) $(USER_OBJS) $(LIBS)
+	@echo 'Finished building target: $@'
+	@echo ' '
+
+4part1.siz: 4part1.elf
+	@echo 'Invoking: Cross ARM GNU Print Size'
+	arm-none-eabi-size --format=berkeley "4part1.elf"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+# Other Targets
+clean:
+	-$(RM) $(SECONDARY_SIZE)$(C++_DEPS)$(OBJS)$(C_DEPS)$(ASM_DEPS)$(CC_DEPS)$(CPP_DEPS)$(CXX_DEPS)$(C_UPPER_DEPS)$(S_UPPER_DEPS) 4part1.elf
+	-@echo ' '
+
+secondary-outputs: $(SECONDARY_SIZE)
+
+.PHONY: all clean dependents
+.SECONDARY:
+
+-include ../makefile.targets
diff --git a/Workspace/4part1/Debug/objects.mk b/Workspace/4part1/Debug/objects.mk
new file mode 100644
index 0000000..90f8af5
--- /dev/null
+++ b/Workspace/4part1/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS := C:/Freescale/KSDK_1.3.0/lib/ksdk_platform_lib/kds/K64F12/debug/libksdk_platform.a
+
+LIBS :=
+
diff --git a/Workspace/4part1/Debug/sources.mk b/Workspace/4part1/Debug/sources.mk
new file mode 100644
index 0000000..80f8a41
--- /dev/null
+++ b/Workspace/4part1/Debug/sources.mk
@@ -0,0 +1,31 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ELF_SRCS := 
+O_SRCS := 
+CPP_SRCS := 
+C_UPPER_SRCS := 
+C_SRCS := 
+S_UPPER_SRCS := 
+OBJ_SRCS := 
+ASM_SRCS := 
+CXX_SRCS := 
+C++_SRCS := 
+CC_SRCS := 
+SECONDARY_SIZE := 
+C++_DEPS := 
+OBJS := 
+C_DEPS := 
+ASM_DEPS := 
+CC_DEPS := 
+CPP_DEPS := 
+CXX_DEPS := 
+C_UPPER_DEPS := 
+S_UPPER_DEPS := 
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Sources \
+Project_Settings/Startup_Code \
+
diff --git a/Workspace/4part1/Project_Settings/Debugger/4part1_Debug_OpenOCD.launch b/Workspace/4part1/Project_Settings/Debugger/4part1_Debug_OpenOCD.launch
new file mode 100644
index 0000000..9ad8a4a
--- /dev/null
+++ b/Workspace/4part1/Project_Settings/Debugger/4part1_Debug_OpenOCD.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doConnectToRunning" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f kinetis.cfg"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/4part1.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="4part1"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/4part1"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/4part1/Project_Settings/Debugger/4part1_Debug_PNE.launch b/Workspace/4part1/Project_Settings/Debugger/4part1_Debug_PNE.launch
new file mode 100644
index 0000000..cda85da
--- /dev/null
+++ b/Workspace/4part1/Project_Settings/Debugger/4part1_Debug_PNE.launch
@@ -0,0 +1,125 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.pemicro.debug.gdbjtag.pne.launchConfigurationType">
+<listAttribute key="com.pemicro.debug.gdbjtag.pne.ELVES"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.NUMBER_ELVES" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.DEVICE_NAME" value="NXP_K6x_K64FN1M0M12"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_IP" value="127.0.0.1"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_OPTIONS" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_PORT" value="7224"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDWARE_INTERFACE" value="6"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.LAST_ATTRIBUTE_HEADER" value="com.pemicro.debug.gdbjtag.pne.sda."/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.USE_EXTERNAL_SERVER" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.algorithmIndex" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.alternativeAlgorithmPath" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.attachToRunning" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.customTrimFrequency" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doContinue" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerAllocateSemihostingConsole" value="true"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doPartitioning" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihosting" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientGdbClient" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientTelnet" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set tcp auto-retry on&#13;&#10;set tcp connect-timeout 30"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherOptions" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerConnection" value="usb"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDebugInterface" value="swd"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDeviceEndianness" value="little"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDeviceName" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerDeviceSpeed" value="30"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerExecutable" value="${jlink_path}/JLinkGDBServerCL"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerGdbPortNumber" value="7224"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerLog" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerOther" value="-s"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerSwoPortNumber" value="2332"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerTelnetPortNumber" value="51794"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.interfaceSpeed" value="auto"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagPreIrBits" value="0"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagTapNumber" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT" value="-1"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_DOWN_DELAY" value="250"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_UP_DELAY" value="1000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.PROVIDE_POWER" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.STARTUP_USE_SWD" value="true"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherRunCommands" value=""/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.partitionParam" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory0" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory1" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory2" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom0" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom1" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom2" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo0" value="3"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo1" value="3"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo2" value="3"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preservePartioning" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.programtrim" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.ALWAYS_ERASE" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.CYCLONE_IP" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.DO_RESET_DELAY" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT_STRING" value="USB1"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.NETWORK_CARD_IP" value=""/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_DOWN_DELAY" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_OFF" value="false"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_UP_DELAY" value=""/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.PROVIDE_POWER" value="false"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.REGULATOR_VOLTAGE" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.RESET_DELAY" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SHIFT_FREQ" value="5000"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_IP" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_NETWORK_CARD" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.STARTUP_USE_SWD" value="true"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.selectedCoreNumber" value="1"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.serverPortNumber" value="7224"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.swoEnableTargetCpuFreq" value="0"/>
+<stringAttribute key="com.pemicro.debug.gdbjtag.pne.swoEnableTargetPortMask" value="0x1"/>
+<intAttribute key="com.pemicro.debug.gdbjtag.pne.swoEnableTargetSwoFreq" value="0"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useAlternativeAlgorithm" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useCustomTrim" value="false"/>
+<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useDaisyChain" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM PEMicro Interface"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="7224"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/4part1.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="4part1"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/4part1"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/4part1/Project_Settings/Debugger/4part1_Debug_Segger.launch b/Workspace/4part1/Project_Settings/Debugger/4part1_Debug_Segger.launch
new file mode 100644
index 0000000..bec6491
--- /dev/null
+++ b/Workspace/4part1/Project_Settings/Debugger/4part1_Debug_Segger.launch
@@ -0,0 +1,77 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.jlink.launchConfigurationType">
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.enableSemihosting" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.enableSwo" value="true"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="MK64FN1M0xxx12"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="1000"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun -strict -timeout 0"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM J-Link"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/4part1.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="4part1"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/4part1"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/4part1/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld b/Workspace/4part1/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
new file mode 100644
index 0000000..506082b
--- /dev/null
+++ b/Workspace/4part1/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
@@ -0,0 +1,245 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150624
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
+  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0
+  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
+  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+  } > m_data_2
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data_2
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
+}
+
diff --git a/Workspace/4part1/Project_Settings/Startup_Code/startup.c b/Workspace/4part1/Project_Settings/Startup_Code/startup.c
new file mode 100644
index 0000000..b89e7fc
--- /dev/null
+++ b/Workspace/4part1/Project_Settings/Startup_Code/startup.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "startup.h"
+#include "fsl_device_registers.h"
+
+#if (defined(__ICCARM__))
+    #pragma section = ".data"
+    #pragma section = ".data_init"
+    #pragma section = ".bss"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : init_data_bss
+ * Description   : Make necessary initializations for RAM.
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ *
+ * Tool Chians:
+ *   __GNUC__   : GCC
+ *   __CC_ARM   : KEIL
+ *   __ICCARM__ : IAR
+ *
+ *END**************************************************************************/
+void init_data_bss(void)
+{
+    uint32_t n; 
+    
+    /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+    #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base  
+    #define __VECTOR_RAM Image$$VECTOR_RAM$$Base  
+    #define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];  
+    extern uint32_t __VECTOR_RAM[];  
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif
+
+    if (__VECTOR_RAM != __VECTOR_TABLE)
+    {   
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+    else
+    {
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_TABLE;
+    }
+
+#if !defined(__CC_ARM) && !defined(__ICCARM__)
+    
+    /* Declare pointers for various data sections. These pointers
+     * are initialized using values pulled in from the linker file */
+    uint8_t * data_ram, * data_rom, * data_rom_end;
+    uint8_t * bss_start, * bss_end;
+
+    /* Get the addresses for the .data section (initialized data section) */
+#if defined(__GNUC__)
+    extern uint32_t __DATA_ROM[];
+    extern uint32_t __DATA_RAM[];
+    extern char __DATA_END[];
+    data_ram = (uint8_t *)__DATA_RAM;
+    data_rom = (uint8_t *)__DATA_ROM;
+    data_rom_end  = (uint8_t *)__DATA_END;
+    n = data_rom_end - data_rom;
+#endif
+
+    /* Copy initialized data from ROM to RAM */
+    while (n--)
+    {
+        *data_ram++ = *data_rom++;
+    }   
+    
+    /* Get the addresses for the .bss section (zero-initialized data) */
+#if defined(__GNUC__)
+    extern char __START_BSS[];
+    extern char __END_BSS[];
+    bss_start = (uint8_t *)__START_BSS;
+    bss_end = (uint8_t *)__END_BSS;
+#endif
+		
+    /* Clear the zero-initialized data section */
+    n = bss_end - bss_start;
+    while(n--)
+    {
+        *bss_start++ = 0;
+    }
+#endif /* !__CC_ARM && !__ICCARM__*/
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/Workspace/4part1/Project_Settings/Startup_Code/startup.h b/Workspace/4part1/Project_Settings/Startup_Code/startup.h
new file mode 100644
index 0000000..17ad55f
--- /dev/null
+++ b/Workspace/4part1/Project_Settings/Startup_Code/startup.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _STARTUP_H_
+#define _STARTUP_H_
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Make necessary initializations for RAM.
+ *
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ */
+void init_data_bss(void);
+
+#endif /* _STARTUP_H_*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/Workspace/4part1/Project_Settings/Startup_Code/startup_MK64F12.S b/Workspace/4part1/Project_Settings/Startup_Code/startup_MK64F12.S
new file mode 100644
index 0000000..aebe2e6
--- /dev/null
+++ b/Workspace/4part1/Project_Settings/Startup_Code/startup_MK64F12.S
@@ -0,0 +1,457 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK64F12.s                                                           */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK64F12                                                                     */
+/*  @version: 2.8                                                                         */
+/*  @date:    2015-2-19                                                                   */
+/*  @build:   b150225                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_IRQHandler                                 /* DMA Channel 0 Transfer Complete*/
+    .long   DMA1_IRQHandler                                 /* DMA Channel 1 Transfer Complete*/
+    .long   DMA2_IRQHandler                                 /* DMA Channel 2 Transfer Complete*/
+    .long   DMA3_IRQHandler                                 /* DMA Channel 3 Transfer Complete*/
+    .long   DMA4_IRQHandler                                 /* DMA Channel 4 Transfer Complete*/
+    .long   DMA5_IRQHandler                                 /* DMA Channel 5 Transfer Complete*/
+    .long   DMA6_IRQHandler                                 /* DMA Channel 6 Transfer Complete*/
+    .long   DMA7_IRQHandler                                 /* DMA Channel 7 Transfer Complete*/
+    .long   DMA8_IRQHandler                                 /* DMA Channel 8 Transfer Complete*/
+    .long   DMA9_IRQHandler                                 /* DMA Channel 9 Transfer Complete*/
+    .long   DMA10_IRQHandler                                /* DMA Channel 10 Transfer Complete*/
+    .long   DMA11_IRQHandler                                /* DMA Channel 11 Transfer Complete*/
+    .long   DMA12_IRQHandler                                /* DMA Channel 12 Transfer Complete*/
+    .long   DMA13_IRQHandler                                /* DMA Channel 13 Transfer Complete*/
+    .long   DMA14_IRQHandler                                /* DMA Channel 14 Transfer Complete*/
+    .long   DMA15_IRQHandler                                /* DMA Channel 15 Transfer Complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA Error Interrupt*/
+    .long   MCM_IRQHandler                                  /* Normal Interrupt*/
+    .long   FTFE_IRQHandler                                 /* FTFE Command complete interrupt*/
+    .long   Read_Collision_IRQHandler                       /* Read Collision Interrupt*/
+    .long   LVD_LVW_IRQHandler                              /* Low Voltage Detect, Low Voltage Warning*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup Unit*/
+    .long   WDOG_EWM_IRQHandler                             /* WDOG Interrupt*/
+    .long   RNG_IRQHandler                                  /* RNG Interrupt*/
+    .long   I2C0_IRQHandler                                 /* I2C0 interrupt*/
+    .long   I2C1_IRQHandler                                 /* I2C1 interrupt*/
+    .long   SPI0_IRQHandler                                 /* SPI0 Interrupt*/
+    .long   SPI1_IRQHandler                                 /* SPI1 Interrupt*/
+    .long   I2S0_Tx_IRQHandler                              /* I2S0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* I2S0 receive interrupt*/
+    .long   UART0_LON_IRQHandler                            /* UART0 LON interrupt*/
+    .long   UART0_RX_TX_IRQHandler                          /* UART0 Receive/Transmit interrupt*/
+    .long   UART0_ERR_IRQHandler                            /* UART0 Error interrupt*/
+    .long   UART1_RX_TX_IRQHandler                          /* UART1 Receive/Transmit interrupt*/
+    .long   UART1_ERR_IRQHandler                            /* UART1 Error interrupt*/
+    .long   UART2_RX_TX_IRQHandler                          /* UART2 Receive/Transmit interrupt*/
+    .long   UART2_ERR_IRQHandler                            /* UART2 Error interrupt*/
+    .long   UART3_RX_TX_IRQHandler                          /* UART3 Receive/Transmit interrupt*/
+    .long   UART3_ERR_IRQHandler                            /* UART3 Error interrupt*/
+    .long   ADC0_IRQHandler                                 /* ADC0 interrupt*/
+    .long   CMP0_IRQHandler                                 /* CMP0 interrupt*/
+    .long   CMP1_IRQHandler                                 /* CMP1 interrupt*/
+    .long   FTM0_IRQHandler                                 /* FTM0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FTM1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FTM2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* CMT interrupt*/
+    .long   RTC_IRQHandler                                  /* RTC interrupt*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds interrupt*/
+    .long   PIT0_IRQHandler                                 /* PIT timer channel 0 interrupt*/
+    .long   PIT1_IRQHandler                                 /* PIT timer channel 1 interrupt*/
+    .long   PIT2_IRQHandler                                 /* PIT timer channel 2 interrupt*/
+    .long   PIT3_IRQHandler                                 /* PIT timer channel 3 interrupt*/
+    .long   PDB0_IRQHandler                                 /* PDB0 Interrupt*/
+    .long   USB0_IRQHandler                                 /* USB0 interrupt*/
+    .long   USBDCD_IRQHandler                               /* USBDCD Interrupt*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt 71*/
+    .long   DAC0_IRQHandler                                 /* DAC0 interrupt*/
+    .long   MCG_IRQHandler                                  /* MCG Interrupt*/
+    .long   LPTMR0_IRQHandler                               /* LPTimer interrupt*/
+    .long   PORTA_IRQHandler                                /* Port A interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* SPI2 Interrupt*/
+    .long   UART4_RX_TX_IRQHandler                          /* UART4 Receive/Transmit interrupt*/
+    .long   UART4_ERR_IRQHandler                            /* UART4 Error interrupt*/
+    .long   UART5_RX_TX_IRQHandler                          /* UART5 Receive/Transmit interrupt*/
+    .long   UART5_ERR_IRQHandler                            /* UART5 Error interrupt*/
+    .long   CMP2_IRQHandler                                 /* CMP2 interrupt*/
+    .long   FTM3_IRQHandler                                 /* FTM3 fault, overflow and channels interrupt*/
+    .long   DAC1_IRQHandler                                 /* DAC1 interrupt*/
+    .long   ADC1_IRQHandler                                 /* ADC1 interrupt*/
+    .long   I2C2_IRQHandler                                 /* I2C2 interrupt*/
+    .long   CAN0_ORed_Message_buffer_IRQHandler             /* CAN0 OR'd message buffers interrupt*/
+    .long   CAN0_Bus_Off_IRQHandler                         /* CAN0 bus off interrupt*/
+    .long   CAN0_Error_IRQHandler                           /* CAN0 error interrupt*/
+    .long   CAN0_Tx_Warning_IRQHandler                      /* CAN0 Tx warning interrupt*/
+    .long   CAN0_Rx_Warning_IRQHandler                      /* CAN0 Rx warning interrupt*/
+    .long   CAN0_Wake_Up_IRQHandler                         /* CAN0 wake up interrupt*/
+    .long   SDHC_IRQHandler                                 /* SDHC interrupt*/
+    .long   ENET_1588_Timer_IRQHandler                      /* Ethernet MAC IEEE 1588 Timer Interrupt*/
+    .long   ENET_Transmit_IRQHandler                        /* Ethernet MAC Transmit Interrupt*/
+    .long   ENET_Receive_IRQHandler                         /* Ethernet MAC Receive Interrupt*/
+    .long   ENET_Error_IRQHandler                           /* Ethernet MAC Error and miscelaneous Interrupt*/
+    .long   DefaultISR                                      /* 102*/
+    .long   DefaultISR                                      /* 103*/
+    .long   DefaultISR                                      /* 104*/
+    .long   DefaultISR                                      /* 105*/
+    .long   DefaultISR                                      /* 106*/
+    .long   DefaultISR                                      /* 107*/
+    .long   DefaultISR                                      /* 108*/
+    .long   DefaultISR                                      /* 109*/
+    .long   DefaultISR                                      /* 110*/
+    .long   DefaultISR                                      /* 111*/
+    .long   DefaultISR                                      /* 112*/
+    .long   DefaultISR                                      /* 113*/
+    .long   DefaultISR                                      /* 114*/
+    .long   DefaultISR                                      /* 115*/
+    .long   DefaultISR                                      /* 116*/
+    .long   DefaultISR                                      /* 117*/
+    .long   DefaultISR                                      /* 118*/
+    .long   DefaultISR                                      /* 119*/
+    .long   DefaultISR                                      /* 120*/
+    .long   DefaultISR                                      /* 121*/
+    .long   DefaultISR                                      /* 122*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+    .long   DefaultISR                                      /* 240*/
+    .long   DefaultISR                                      /* 241*/
+    .long   DefaultISR                                      /* 242*/
+    .long   DefaultISR                                      /* 243*/
+    .long   DefaultISR                                      /* 244*/
+    .long   DefaultISR                                      /* 245*/
+    .long   DefaultISR                                      /* 246*/
+    .long   DefaultISR                                      /* 247*/
+    .long   DefaultISR                                      /* 248*/
+    .long   DefaultISR                                      /* 249*/
+    .long   DefaultISR                                      /* 250*/
+    .long   DefaultISR                                      /* 251*/
+    .long   DefaultISR                                      /* 252*/
+    .long   DefaultISR                                      /* 253*/
+    .long   DefaultISR                                      /* 254*/
+    .long   0xFFFFFFFF                                      /*  Reserved for user TRIM value*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_IRQHandler
+    def_irq_handler    DMA1_IRQHandler
+    def_irq_handler    DMA2_IRQHandler
+    def_irq_handler    DMA3_IRQHandler
+    def_irq_handler    DMA4_IRQHandler
+    def_irq_handler    DMA5_IRQHandler
+    def_irq_handler    DMA6_IRQHandler
+    def_irq_handler    DMA7_IRQHandler
+    def_irq_handler    DMA8_IRQHandler
+    def_irq_handler    DMA9_IRQHandler
+    def_irq_handler    DMA10_IRQHandler
+    def_irq_handler    DMA11_IRQHandler
+    def_irq_handler    DMA12_IRQHandler
+    def_irq_handler    DMA13_IRQHandler
+    def_irq_handler    DMA14_IRQHandler
+    def_irq_handler    DMA15_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFE_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    RNG_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    UART0_LON_IRQHandler
+    def_irq_handler    UART0_RX_TX_IRQHandler
+    def_irq_handler    UART0_ERR_IRQHandler
+    def_irq_handler    UART1_RX_TX_IRQHandler
+    def_irq_handler    UART1_ERR_IRQHandler
+    def_irq_handler    UART2_RX_TX_IRQHandler
+    def_irq_handler    UART2_ERR_IRQHandler
+    def_irq_handler    UART3_RX_TX_IRQHandler
+    def_irq_handler    UART3_ERR_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    PIT1_IRQHandler
+    def_irq_handler    PIT2_IRQHandler
+    def_irq_handler    PIT3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    UART4_RX_TX_IRQHandler
+    def_irq_handler    UART4_ERR_IRQHandler
+    def_irq_handler    UART5_RX_TX_IRQHandler
+    def_irq_handler    UART5_ERR_IRQHandler
+    def_irq_handler    CMP2_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    DAC1_IRQHandler
+    def_irq_handler    ADC1_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    CAN0_ORed_Message_buffer_IRQHandler
+    def_irq_handler    CAN0_Bus_Off_IRQHandler
+    def_irq_handler    CAN0_Error_IRQHandler
+    def_irq_handler    CAN0_Tx_Warning_IRQHandler
+    def_irq_handler    CAN0_Rx_Warning_IRQHandler
+    def_irq_handler    CAN0_Wake_Up_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    ENET_1588_Timer_IRQHandler
+    def_irq_handler    ENET_Transmit_IRQHandler
+    def_irq_handler    ENET_Receive_IRQHandler
+    def_irq_handler    ENET_Error_IRQHandler
+
+    .end
diff --git a/Workspace/4part1/Project_Settings/Startup_Code/system_MK64F12.c b/Workspace/4part1/Project_Settings/Startup_Code/system_MK64F12.c
new file mode 100644
index 0000000..e3c1376
--- /dev/null
+++ b/Workspace/4part1/Project_Settings/Startup_Code/system_MK64F12.c
@@ -0,0 +1,414 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief Device specific configuration file for MK64F12 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+#if (DISABLE_WDOG)
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+  /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+  WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+                 WDOG_STCTRLH_WAITEN_MASK |
+                 WDOG_STCTRLH_STOPEN_MASK |
+                 WDOG_STCTRLH_ALLOWUPDATE_MASK |
+                 WDOG_STCTRLH_CLKSRC_MASK |
+                 0x0100U;
+#endif /* (DISABLE_WDOG) */
+#ifdef CLOCK_SETUP
+  if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
+  {
+    if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
+    {
+       PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO:  Only has an effect if recovering from VLLSx.*/
+    }
+  } else {
+#ifdef SYSTEM_RTC_CR_VALUE
+    SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
+    if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
+      RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
+      RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
+      RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
+    }
+#endif
+  }
+
+  /* Power mode protection initialization */
+#ifdef SYSTEM_SMC_PMPROT_VALUE
+  SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
+#endif
+
+  /* System clock initialization */
+  /* Internal reference clock trim initialization */
+#if defined(SLOW_TRIM_ADDRESS)
+  if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) {                              /* Skip if non-volatile flash memory is erased */
+    MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
+  #endif /* defined(SLOW_TRIM_ADDRESS) */
+  #if defined(SLOW_FINE_TRIM_ADDRESS)
+    MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
+  #endif
+  #if defined(FAST_TRIM_ADDRESS)
+    MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
+  #endif
+  #if defined(FAST_FINE_TRIM_ADDRESS)
+    MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
+  #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
+#if defined(SLOW_TRIM_ADDRESS)
+  }
+  #endif /* defined(SLOW_TRIM_ADDRESS) */
+
+  /* Set system prescalers and clock sources */
+  SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
+  SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
+  SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+  /* Set MCG and OSC */
+#if  ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+  /* PORTA_PCR19: ISF=0,MUX=0 */
+  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
+  MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+  /* Check that the source of the FLL reference clock is the requested one. */
+  if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+    }
+  } else {
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+    }
+  }
+  MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+  MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+  OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
+  #if (MCG_MODE == MCG_MODE_BLPI)
+  /* BLPI specific */
+  MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
+  #endif
+
+#else /* MCG_MODE */
+  /* Set MCG and OSC */
+#if  (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+  /* PORTA_PCR19: ISF=0,MUX=0 */
+  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
+  MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+  OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
+  #if (MCG_MODE == MCG_MODE_PEE)
+  MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
+  #else
+  MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+  #endif
+  if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
+    while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
+    }
+  }
+  /* Check that the source of the FLL reference clock is the requested one. */
+  if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+    }
+  } else {
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+    }
+  }
+  MCG->C4 = ((SYSTEM_MCG_C4_VALUE)  & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+#endif /* MCG_MODE */
+
+  /* Common for all MCG modes */
+
+  /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
+  MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
+  MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+  if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
+    MCG->C5 |= MCG_C5_PLLCLKEN0_MASK;  /* PLL clock enable in mode other than PEE or PBE */
+  }
+  /* BLPE, PEE and PBE MCG mode specific */
+
+#if (MCG_MODE == MCG_MODE_BLPE)
+  MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
+#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
+  MCG->C6 |= (MCG_C6_PLLS_MASK);       /* Set C6 (PLL select, VCO divider etc.) */
+  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
+  }
+  #if (MCG_MODE == MCG_MODE_PEE)
+  MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
+  #endif
+#endif
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
+  }
+  /* Use LPTMR to wait for 1ms dor FLL clock stabilization */
+  SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;   /* Alow software control of LPMTR */
+  LPTMR0->CMR = LPTMR_CMR_COMPARE(0);  /* Default 1 LPO tick */
+  LPTMR0->CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00));
+  LPTMR0->PSR = (LPTMR_PSR_PCS(0x01) | LPTMR_PSR_PBYP_MASK); /* Clock source: LPO, Prescaler bypass enable */
+  LPTMR0->CSR = LPTMR_CSR_TEN_MASK;    /* LPMTR enable */
+  while((LPTMR0_CSR & LPTMR_CSR_TCF_MASK) == 0u) {
+  }
+  LPTMR0_CSR = 0x00;                   /* Disable LPTMR */
+  SIM_SCGC5 &= (uint32_t)~(uint32_t)SIM_SCGC5_LPTMR_MASK;
+#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
+  }
+#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+  }
+#elif (MCG_MODE == MCG_MODE_PEE)
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
+  }
+#endif
+#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
+  SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
+  while(SMC->PMSTAT != 0x04U) {        /* Wait until the system is in VLPR mode */
+  }
+#endif
+
+#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
+  SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
+#endif
+
+  /* PLL loss of lock interrupt request initialization */
+  if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
+    NVIC_EnableIRQ(MCG_IRQn);          /* Enable PLL loss of lock interrupt request */
+  }
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+  uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
+  uint16_t Divider;
+
+  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
+    /* Output of FLL or PLL is selected */
+    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
+      /* FLL is selected */
+      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+        case 0x00U:
+          MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+          break;
+        case 0x01U:
+          MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+          break;
+        case 0x02U:
+        default:
+          MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+          break;
+        }
+        if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
+          switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
+          case 0x38U:
+            Divider = 1536U;
+            break;
+          case 0x30U:
+            Divider = 1280U;
+            break;
+          default:
+            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+            break;
+          }
+        } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+          Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+        }
+        MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+        MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+      /* Select correct multiplier to calculate the MCG output clock  */
+      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+        case 0x00U:
+          MCGOUTClock *= 640U;
+          break;
+        case 0x20U:
+          MCGOUTClock *= 1280U;
+          break;
+        case 0x40U:
+          MCGOUTClock *= 1920U;
+          break;
+        case 0x60U:
+          MCGOUTClock *= 2560U;
+          break;
+        case 0x80U:
+          MCGOUTClock *= 732U;
+          break;
+        case 0xA0U:
+          MCGOUTClock *= 1464U;
+          break;
+        case 0xC0U:
+          MCGOUTClock *= 2197U;
+          break;
+        case 0xE0U:
+          MCGOUTClock *= 2929U;
+          break;
+        default:
+          break;
+      }
+    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+      /* PLL is selected */
+      Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
+      MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+      Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
+      MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
+    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
+    /* Internal reference clock is selected */
+    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+      Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+      MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
+    /* External reference clock is selected */
+    switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+    case 0x00U:
+      MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
+      break;
+    case 0x01U:
+      MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+      break;
+    case 0x02U:
+    default:
+      MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+      break;
+    }
+  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    /* Reserved value */
+    return;
+  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+  SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/Workspace/4part1/Project_Settings/Startup_Code/system_MK64F12.h b/Workspace/4part1/Project_Settings/Startup_Code/system_MK64F12.h
new file mode 100644
index 0000000..d6a5f05
--- /dev/null
+++ b/Workspace/4part1/Project_Settings/Startup_Code/system_MK64F12.h
@@ -0,0 +1,352 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief Device specific configuration file for MK64F12 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK64F12_H_
+#define SYSTEM_MK64F12_H_                        /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG                 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI                   0U
+#define MCG_MODE_FBI                   1U
+#define MCG_MODE_BLPI                  2U
+#define MCG_MODE_FEE                   3U
+#define MCG_MODE_FBE                   4U
+#define MCG_MODE_BLPE                  5U
+#define MCG_MODE_PBE                   6U
+#define MCG_MODE_PEE                   7U
+
+/* Predefined clock setups
+   0 ... Default  part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock = 20.97152MHz
+         Bus clock  = 20.97152MHz
+   1 ... Maximum achievable clock frequency configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+   2 ... Chip internaly clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   3 ... Chip externally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: RTC oscillator reference clock
+         Core clock = 0.032768MHz
+         Bus clock  = 0.032768MHz
+   4 ... USB clock setup
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+ */
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ                50000000u           /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_XTAL32k_CLK_HZ             32768u              /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+#define CPU_INT_SLOW_CLK_HZ            32768u              /* Value of the slow internal oscillator clock frequency in Hz  */
+#define CPU_INT_FAST_CLK_HZ            4000000u            /* Value of the fast internal oscillator clock frequency in Hz  */
+#define CPU_INT_IRC_CLK_HZ             48000000u           /* Value of the 48M internal oscillator clock frequency in Hz  */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE            0x0300U             /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE        0x2AU               /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */                             /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */                        /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */                             /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */                        /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_FEI /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x06U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00110000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00U               /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 1)
+  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 2)
+  #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_BLPI /* Clock generator mode */
+  /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x46U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00040000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 3)
+  #define DEFAULT_SYSTEM_CLOCK         32768u              /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_BLPE /* Clock generator mode */
+  /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x82U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x02U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=1 */
+  #define SYSTEM_MCG_C7_VALUE          0x01U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00U               /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 4)
+  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
+  #define SYSTEM_SIM_CLKDIV2_VALUE     0x09U               /* SIM_CLKDIV2 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
+#endif
+#else
+  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* #if !defined(SYSTEM_MK64F12_H_) */
diff --git a/Workspace/4part1/SDK/platform/CMSIS/Include/arm_common_tables.h b/Workspace/4part1/SDK/platform/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000..039cc3d
--- /dev/null
+++ b/Workspace/4part1/SDK/platform/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/Workspace/4part1/SDK/platform/CMSIS/Include/arm_const_structs.h b/Workspace/4part1/SDK/platform/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 0000000..726d06e
--- /dev/null
+++ b/Workspace/4part1/SDK/platform/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/Workspace/4part1/SDK/platform/CMSIS/Include/arm_math.h b/Workspace/4part1/SDK/platform/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000..e4b2f62
--- /dev/null
+++ b/Workspace/4part1/SDK/platform/CMSIS/Include/arm_math.h
@@ -0,0 +1,7556 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_math.h
+*
+* Description:	Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   * 
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   * 
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+  #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31	   0x400000
+#define TABLE_SPACING_Q15	   0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+#elif defined __GNUC__
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__			/* Cosmic */
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+#elif defined __TASKING__
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+//#define __CLZ __clz
+//#endif
+
+//note: function can be removed when all toolchain support __CLZ for Cortex-M0
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+      ((q15_t) x * (q15_t) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		 *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15( 
+    const arm_cfft_instance_q15 * S, 
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31( 
+    const arm_cfft_instance_q31 * S, 
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+  
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in >= 0.0f)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+   
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("push")         \
+         _Pragma ("O1")
+    #else
+      #define LOW_OPTIMIZATION_ENTER 
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_EXIT \
+         _Pragma ("pop")
+    #else
+      #define LOW_OPTIMIZATION_EXIT  
+    #endif
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)		// Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)		// TASKING
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/Workspace/4part1/SDK/platform/CMSIS/Include/core_cm4.h b/Workspace/4part1/SDK/platform/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000..9749c27
--- /dev/null
+++ b/Workspace/4part1/SDK/platform/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1858 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)IRQn < 0) {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)IRQn < 0) {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                             /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Workspace/4part1/SDK/platform/CMSIS/Include/core_cmFunc.h b/Workspace/4part1/SDK/platform/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000..b6ad0a4
--- /dev/null
+++ b/Workspace/4part1/SDK/platform/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,664 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+    or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+	or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/Workspace/4part1/SDK/platform/CMSIS/Include/core_cmInstr.h b/Workspace/4part1/SDK/platform/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000..fca425c
--- /dev/null
+++ b/Workspace/4part1/SDK/platform/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,916 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+  return(result);
+}
+#endif
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+#endif
+  return(result);
+}
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/Workspace/4part1/SDK/platform/CMSIS/Include/core_cmSimd.h b/Workspace/4part1/SDK/platform/CMSIS/Include/core_cmSimd.h
new file mode 100644
index 0000000..7b8e37f
--- /dev/null
+++ b/Workspace/4part1/SDK/platform/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/Workspace/4part1/SDK/platform/devices/MK64F12/include/MK64F12.h b/Workspace/4part1/SDK/platform/devices/MK64F12/include/MK64F12.h
new file mode 100644
index 0000000..3114ad7
--- /dev/null
+++ b/Workspace/4part1/SDK/platform/devices/MK64F12/include/MK64F12.h
@@ -0,0 +1,18767 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MK64F12
+**
+**     Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12.h
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief CMSIS Peripheral Access Layer for MK64F12
+ *
+ * CMSIS Peripheral Access Layer for MK64F12
+ */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCU activation
+   ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MK64F12_H_)  /* Check if memory map has not been already included */
+#define MK64F12_H_
+#define MCU_MK64F12
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+  #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0008u
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ *        bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ *        0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return  Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 102                /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_IRQn                    = 0,                /**< DMA Channel 0 Transfer Complete */
+  DMA1_IRQn                    = 1,                /**< DMA Channel 1 Transfer Complete */
+  DMA2_IRQn                    = 2,                /**< DMA Channel 2 Transfer Complete */
+  DMA3_IRQn                    = 3,                /**< DMA Channel 3 Transfer Complete */
+  DMA4_IRQn                    = 4,                /**< DMA Channel 4 Transfer Complete */
+  DMA5_IRQn                    = 5,                /**< DMA Channel 5 Transfer Complete */
+  DMA6_IRQn                    = 6,                /**< DMA Channel 6 Transfer Complete */
+  DMA7_IRQn                    = 7,                /**< DMA Channel 7 Transfer Complete */
+  DMA8_IRQn                    = 8,                /**< DMA Channel 8 Transfer Complete */
+  DMA9_IRQn                    = 9,                /**< DMA Channel 9 Transfer Complete */
+  DMA10_IRQn                   = 10,               /**< DMA Channel 10 Transfer Complete */
+  DMA11_IRQn                   = 11,               /**< DMA Channel 11 Transfer Complete */
+  DMA12_IRQn                   = 12,               /**< DMA Channel 12 Transfer Complete */
+  DMA13_IRQn                   = 13,               /**< DMA Channel 13 Transfer Complete */
+  DMA14_IRQn                   = 14,               /**< DMA Channel 14 Transfer Complete */
+  DMA15_IRQn                   = 15,               /**< DMA Channel 15 Transfer Complete */
+  DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
+  MCM_IRQn                     = 17,               /**< Normal Interrupt */
+  FTFE_IRQn                    = 18,               /**< FTFE Command complete interrupt */
+  Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
+  LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
+  LLWU_IRQn                    = 21,               /**< Low Leakage Wakeup Unit */
+  WDOG_EWM_IRQn                = 22,               /**< WDOG Interrupt */
+  RNG_IRQn                     = 23,               /**< RNG Interrupt */
+  I2C0_IRQn                    = 24,               /**< I2C0 interrupt */
+  I2C1_IRQn                    = 25,               /**< I2C1 interrupt */
+  SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
+  SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
+  I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
+  I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
+  UART0_LON_IRQn               = 30,               /**< UART0 LON interrupt */
+  UART0_RX_TX_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
+  UART0_ERR_IRQn               = 32,               /**< UART0 Error interrupt */
+  UART1_RX_TX_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
+  UART1_ERR_IRQn               = 34,               /**< UART1 Error interrupt */
+  UART2_RX_TX_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
+  UART2_ERR_IRQn               = 36,               /**< UART2 Error interrupt */
+  UART3_RX_TX_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
+  UART3_ERR_IRQn               = 38,               /**< UART3 Error interrupt */
+  ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
+  CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
+  FTM0_IRQn                    = 42,               /**< FTM0 fault, overflow and channels interrupt */
+  FTM1_IRQn                    = 43,               /**< FTM1 fault, overflow and channels interrupt */
+  FTM2_IRQn                    = 44,               /**< FTM2 fault, overflow and channels interrupt */
+  CMT_IRQn                     = 45,               /**< CMT interrupt */
+  RTC_IRQn                     = 46,               /**< RTC interrupt */
+  RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
+  PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
+  PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
+  PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
+  PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
+  PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
+  USB0_IRQn                    = 53,               /**< USB0 interrupt */
+  USBDCD_IRQn                  = 54,               /**< USBDCD Interrupt */
+  Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
+  DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
+  MCG_IRQn                     = 57,               /**< MCG Interrupt */
+  LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
+  PORTA_IRQn                   = 59,               /**< Port A interrupt */
+  PORTB_IRQn                   = 60,               /**< Port B interrupt */
+  PORTC_IRQn                   = 61,               /**< Port C interrupt */
+  PORTD_IRQn                   = 62,               /**< Port D interrupt */
+  PORTE_IRQn                   = 63,               /**< Port E interrupt */
+  SWI_IRQn                     = 64,               /**< Software interrupt */
+  SPI2_IRQn                    = 65,               /**< SPI2 Interrupt */
+  UART4_RX_TX_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
+  UART4_ERR_IRQn               = 67,               /**< UART4 Error interrupt */
+  UART5_RX_TX_IRQn             = 68,               /**< UART5 Receive/Transmit interrupt */
+  UART5_ERR_IRQn               = 69,               /**< UART5 Error interrupt */
+  CMP2_IRQn                    = 70,               /**< CMP2 interrupt */
+  FTM3_IRQn                    = 71,               /**< FTM3 fault, overflow and channels interrupt */
+  DAC1_IRQn                    = 72,               /**< DAC1 interrupt */
+  ADC1_IRQn                    = 73,               /**< ADC1 interrupt */
+  I2C2_IRQn                    = 74,               /**< I2C2 interrupt */
+  CAN0_ORed_Message_buffer_IRQn = 75,              /**< CAN0 OR'd message buffers interrupt */
+  CAN0_Bus_Off_IRQn            = 76,               /**< CAN0 bus off interrupt */
+  CAN0_Error_IRQn              = 77,               /**< CAN0 error interrupt */
+  CAN0_Tx_Warning_IRQn         = 78,               /**< CAN0 Tx warning interrupt */
+  CAN0_Rx_Warning_IRQn         = 79,               /**< CAN0 Rx warning interrupt */
+  CAN0_Wake_Up_IRQn            = 80,               /**< CAN0 wake up interrupt */
+  SDHC_IRQn                    = 81,               /**< SDHC interrupt */
+  ENET_1588_Timer_IRQn         = 82,               /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+  ENET_Transmit_IRQn           = 83,               /**< Ethernet MAC Transmit Interrupt */
+  ENET_Receive_IRQn            = 84,               /**< Ethernet MAC Receive Interrupt */
+  ENET_Error_IRQn              = 85                /**< Ethernet MAC Error and miscelaneous Interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_MK64F12.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index)                  ((base)->SC1[index])
+#define ADC_SC1_COUNT                            2
+#define ADC_CFG1_REG(base)                       ((base)->CFG1)
+#define ADC_CFG2_REG(base)                       ((base)->CFG2)
+#define ADC_R_REG(base,index)                    ((base)->R[index])
+#define ADC_R_COUNT                              2
+#define ADC_CV1_REG(base)                        ((base)->CV1)
+#define ADC_CV2_REG(base)                        ((base)->CV2)
+#define ADC_SC2_REG(base)                        ((base)->SC2)
+#define ADC_SC3_REG(base)                        ((base)->SC3)
+#define ADC_OFS_REG(base)                        ((base)->OFS)
+#define ADC_PG_REG(base)                         ((base)->PG)
+#define ADC_MG_REG(base)                         ((base)->MG)
+#define ADC_CLPD_REG(base)                       ((base)->CLPD)
+#define ADC_CLPS_REG(base)                       ((base)->CLPS)
+#define ADC_CLP4_REG(base)                       ((base)->CLP4)
+#define ADC_CLP3_REG(base)                       ((base)->CLP3)
+#define ADC_CLP2_REG(base)                       ((base)->CLP2)
+#define ADC_CLP1_REG(base)                       ((base)->CLP1)
+#define ADC_CLP0_REG(base)                       ((base)->CLP0)
+#define ADC_CLMD_REG(base)                       ((base)->CLMD)
+#define ADC_CLMS_REG(base)                       ((base)->CLMS)
+#define ADC_CLM4_REG(base)                       ((base)->CLM4)
+#define ADC_CLM3_REG(base)                       ((base)->CLM3)
+#define ADC_CLM2_REG(base)                       ((base)->CLM2)
+#define ADC_CLM1_REG(base)                       ((base)->CLM1)
+#define ADC_CLM0_REG(base)                       ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK                        0x1Fu
+#define ADC_SC1_ADCH_SHIFT                       0
+#define ADC_SC1_ADCH_WIDTH                       5
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        0x20u
+#define ADC_SC1_DIFF_SHIFT                       5
+#define ADC_SC1_DIFF_WIDTH                       1
+#define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK                        0x40u
+#define ADC_SC1_AIEN_SHIFT                       6
+#define ADC_SC1_AIEN_WIDTH                       1
+#define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK                        0x80u
+#define ADC_SC1_COCO_SHIFT                       7
+#define ADC_SC1_COCO_WIDTH                       1
+#define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK                     0x3u
+#define ADC_CFG1_ADICLK_SHIFT                    0
+#define ADC_CFG1_ADICLK_WIDTH                    2
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       0xCu
+#define ADC_CFG1_MODE_SHIFT                      2
+#define ADC_CFG1_MODE_WIDTH                      2
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     0x10u
+#define ADC_CFG1_ADLSMP_SHIFT                    4
+#define ADC_CFG1_ADLSMP_WIDTH                    1
+#define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK                       0x60u
+#define ADC_CFG1_ADIV_SHIFT                      5
+#define ADC_CFG1_ADIV_WIDTH                      2
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      0x80u
+#define ADC_CFG1_ADLPC_SHIFT                     7
+#define ADC_CFG1_ADLPC_WIDTH                     1
+#define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK                     0x3u
+#define ADC_CFG2_ADLSTS_SHIFT                    0
+#define ADC_CFG2_ADLSTS_WIDTH                    2
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      0x4u
+#define ADC_CFG2_ADHSC_SHIFT                     2
+#define ADC_CFG2_ADHSC_WIDTH                     1
+#define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK                    0x8u
+#define ADC_CFG2_ADACKEN_SHIFT                   3
+#define ADC_CFG2_ADACKEN_WIDTH                   1
+#define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK                     0x10u
+#define ADC_CFG2_MUXSEL_SHIFT                    4
+#define ADC_CFG2_MUXSEL_WIDTH                    1
+#define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
+/* R Bit Fields */
+#define ADC_R_D_MASK                             0xFFFFu
+#define ADC_R_D_SHIFT                            0
+#define ADC_R_D_WIDTH                            16
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK                          0xFFFFu
+#define ADC_CV1_CV_SHIFT                         0
+#define ADC_CV1_CV_WIDTH                         16
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK                          0xFFFFu
+#define ADC_CV2_CV_SHIFT                         0
+#define ADC_CV2_CV_WIDTH                         16
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK                      0x3u
+#define ADC_SC2_REFSEL_SHIFT                     0
+#define ADC_SC2_REFSEL_WIDTH                     2
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       0x4u
+#define ADC_SC2_DMAEN_SHIFT                      2
+#define ADC_SC2_DMAEN_WIDTH                      1
+#define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK                       0x8u
+#define ADC_SC2_ACREN_SHIFT                      3
+#define ADC_SC2_ACREN_WIDTH                      1
+#define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK                       0x10u
+#define ADC_SC2_ACFGT_SHIFT                      4
+#define ADC_SC2_ACFGT_WIDTH                      1
+#define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK                        0x20u
+#define ADC_SC2_ACFE_SHIFT                       5
+#define ADC_SC2_ACFE_WIDTH                       1
+#define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK                       0x40u
+#define ADC_SC2_ADTRG_SHIFT                      6
+#define ADC_SC2_ADTRG_WIDTH                      1
+#define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK                       0x80u
+#define ADC_SC2_ADACT_SHIFT                      7
+#define ADC_SC2_ADACT_WIDTH                      1
+#define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK                        0x3u
+#define ADC_SC3_AVGS_SHIFT                       0
+#define ADC_SC3_AVGS_WIDTH                       2
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        0x4u
+#define ADC_SC3_AVGE_SHIFT                       2
+#define ADC_SC3_AVGE_WIDTH                       1
+#define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK                        0x8u
+#define ADC_SC3_ADCO_SHIFT                       3
+#define ADC_SC3_ADCO_WIDTH                       1
+#define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK                        0x40u
+#define ADC_SC3_CALF_SHIFT                       6
+#define ADC_SC3_CALF_WIDTH                       1
+#define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK                         0x80u
+#define ADC_SC3_CAL_SHIFT                        7
+#define ADC_SC3_CAL_WIDTH                        1
+#define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK                         0xFFFFu
+#define ADC_OFS_OFS_SHIFT                        0
+#define ADC_OFS_OFS_WIDTH                        16
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK                           0xFFFFu
+#define ADC_PG_PG_SHIFT                          0
+#define ADC_PG_PG_WIDTH                          16
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK                           0xFFFFu
+#define ADC_MG_MG_SHIFT                          0
+#define ADC_MG_MG_WIDTH                          16
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK                       0x3Fu
+#define ADC_CLPD_CLPD_SHIFT                      0
+#define ADC_CLPD_CLPD_WIDTH                      6
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK                       0x3Fu
+#define ADC_CLPS_CLPS_SHIFT                      0
+#define ADC_CLPS_CLPS_WIDTH                      6
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK                       0x3FFu
+#define ADC_CLP4_CLP4_SHIFT                      0
+#define ADC_CLP4_CLP4_WIDTH                      10
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK                       0x1FFu
+#define ADC_CLP3_CLP3_SHIFT                      0
+#define ADC_CLP3_CLP3_WIDTH                      9
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK                       0xFFu
+#define ADC_CLP2_CLP2_SHIFT                      0
+#define ADC_CLP2_CLP2_WIDTH                      8
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK                       0x7Fu
+#define ADC_CLP1_CLP1_SHIFT                      0
+#define ADC_CLP1_CLP1_WIDTH                      7
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK                       0x3Fu
+#define ADC_CLP0_CLP0_SHIFT                      0
+#define ADC_CLP0_CLP0_WIDTH                      6
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK                       0x3Fu
+#define ADC_CLMD_CLMD_SHIFT                      0
+#define ADC_CLMD_CLMD_WIDTH                      6
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK                       0x3Fu
+#define ADC_CLMS_CLMS_SHIFT                      0
+#define ADC_CLMS_CLMS_WIDTH                      6
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK                       0x3FFu
+#define ADC_CLM4_CLM4_SHIFT                      0
+#define ADC_CLM4_CLM4_WIDTH                      10
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK                       0x1FFu
+#define ADC_CLM3_CLM3_SHIFT                      0
+#define ADC_CLM3_CLM3_WIDTH                      9
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK                       0xFFu
+#define ADC_CLM2_CLM2_SHIFT                      0
+#define ADC_CLM2_CLM2_WIDTH                      8
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK                       0x7Fu
+#define ADC_CLM1_CLM1_SHIFT                      0
+#define ADC_CLM1_CLM1_WIDTH                      7
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK                       0x3Fu
+#define ADC_CLM0_CLM0_SHIFT                      0
+#define ADC_CLM0_CLM0_WIDTH                      6
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR                            (ADC0)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_Type *)ADC1_BASE)
+#define ADC1_BASE_PTR                            (ADC1)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A                                ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B                                ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1                                ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2                                ADC_CFG2_REG(ADC0)
+#define ADC0_RA                                  ADC_R_REG(ADC0,0)
+#define ADC0_RB                                  ADC_R_REG(ADC0,1)
+#define ADC0_CV1                                 ADC_CV1_REG(ADC0)
+#define ADC0_CV2                                 ADC_CV2_REG(ADC0)
+#define ADC0_SC2                                 ADC_SC2_REG(ADC0)
+#define ADC0_SC3                                 ADC_SC3_REG(ADC0)
+#define ADC0_OFS                                 ADC_OFS_REG(ADC0)
+#define ADC0_PG                                  ADC_PG_REG(ADC0)
+#define ADC0_MG                                  ADC_MG_REG(ADC0)
+#define ADC0_CLPD                                ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS                                ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4                                ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3                                ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2                                ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1                                ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0                                ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD                                ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS                                ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4                                ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3                                ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2                                ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1                                ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0                                ADC_CLM0_REG(ADC0)
+/* ADC1 */
+#define ADC1_SC1A                                ADC_SC1_REG(ADC1,0)
+#define ADC1_SC1B                                ADC_SC1_REG(ADC1,1)
+#define ADC1_CFG1                                ADC_CFG1_REG(ADC1)
+#define ADC1_CFG2                                ADC_CFG2_REG(ADC1)
+#define ADC1_RA                                  ADC_R_REG(ADC1,0)
+#define ADC1_RB                                  ADC_R_REG(ADC1,1)
+#define ADC1_CV1                                 ADC_CV1_REG(ADC1)
+#define ADC1_CV2                                 ADC_CV2_REG(ADC1)
+#define ADC1_SC2                                 ADC_SC2_REG(ADC1)
+#define ADC1_SC3                                 ADC_SC3_REG(ADC1)
+#define ADC1_OFS                                 ADC_OFS_REG(ADC1)
+#define ADC1_PG                                  ADC_PG_REG(ADC1)
+#define ADC1_MG                                  ADC_MG_REG(ADC1)
+#define ADC1_CLPD                                ADC_CLPD_REG(ADC1)
+#define ADC1_CLPS                                ADC_CLPS_REG(ADC1)
+#define ADC1_CLP4                                ADC_CLP4_REG(ADC1)
+#define ADC1_CLP3                                ADC_CLP3_REG(ADC1)
+#define ADC1_CLP2                                ADC_CLP2_REG(ADC1)
+#define ADC1_CLP1                                ADC_CLP1_REG(ADC1)
+#define ADC1_CLP0                                ADC_CLP0_REG(ADC1)
+#define ADC1_CLMD                                ADC_CLMD_REG(ADC1)
+#define ADC1_CLMS                                ADC_CLMS_REG(ADC1)
+#define ADC1_CLM4                                ADC_CLM4_REG(ADC1)
+#define ADC1_CLM3                                ADC_CLM3_REG(ADC1)
+#define ADC1_CLM2                                ADC_CLM2_REG(ADC1)
+#define ADC1_CLM1                                ADC_CLM1_REG(ADC1)
+#define ADC1_CLM0                                ADC_CLM0_REG(ADC1)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index)                          ADC_SC1_REG(ADC0,index)
+#define ADC1_SC1(index)                          ADC_SC1_REG(ADC1,index)
+#define ADC0_R(index)                            ADC_R_REG(ADC0,index)
+#define ADC1_R(index)                            ADC_R_REG(ADC1,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPRA;                              /**< Master Privilege Register A, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PACRA;                             /**< Peripheral Access Control Register, offset: 0x20 */
+  __IO uint32_t PACRB;                             /**< Peripheral Access Control Register, offset: 0x24 */
+  __IO uint32_t PACRC;                             /**< Peripheral Access Control Register, offset: 0x28 */
+  __IO uint32_t PACRD;                             /**< Peripheral Access Control Register, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PACRE;                             /**< Peripheral Access Control Register, offset: 0x40 */
+  __IO uint32_t PACRF;                             /**< Peripheral Access Control Register, offset: 0x44 */
+  __IO uint32_t PACRG;                             /**< Peripheral Access Control Register, offset: 0x48 */
+  __IO uint32_t PACRH;                             /**< Peripheral Access Control Register, offset: 0x4C */
+  __IO uint32_t PACRI;                             /**< Peripheral Access Control Register, offset: 0x50 */
+  __IO uint32_t PACRJ;                             /**< Peripheral Access Control Register, offset: 0x54 */
+  __IO uint32_t PACRK;                             /**< Peripheral Access Control Register, offset: 0x58 */
+  __IO uint32_t PACRL;                             /**< Peripheral Access Control Register, offset: 0x5C */
+  __IO uint32_t PACRM;                             /**< Peripheral Access Control Register, offset: 0x60 */
+  __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
+  __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
+  __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t PACRU;                             /**< Peripheral Access Control Register, offset: 0x80 */
+} AIPS_Type, *AIPS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register accessors */
+#define AIPS_MPRA_REG(base)                      ((base)->MPRA)
+#define AIPS_PACRA_REG(base)                     ((base)->PACRA)
+#define AIPS_PACRB_REG(base)                     ((base)->PACRB)
+#define AIPS_PACRC_REG(base)                     ((base)->PACRC)
+#define AIPS_PACRD_REG(base)                     ((base)->PACRD)
+#define AIPS_PACRE_REG(base)                     ((base)->PACRE)
+#define AIPS_PACRF_REG(base)                     ((base)->PACRF)
+#define AIPS_PACRG_REG(base)                     ((base)->PACRG)
+#define AIPS_PACRH_REG(base)                     ((base)->PACRH)
+#define AIPS_PACRI_REG(base)                     ((base)->PACRI)
+#define AIPS_PACRJ_REG(base)                     ((base)->PACRJ)
+#define AIPS_PACRK_REG(base)                     ((base)->PACRK)
+#define AIPS_PACRL_REG(base)                     ((base)->PACRL)
+#define AIPS_PACRM_REG(base)                     ((base)->PACRM)
+#define AIPS_PACRN_REG(base)                     ((base)->PACRN)
+#define AIPS_PACRO_REG(base)                     ((base)->PACRO)
+#define AIPS_PACRP_REG(base)                     ((base)->PACRP)
+#define AIPS_PACRU_REG(base)                     ((base)->PACRU)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/* MPRA Bit Fields */
+#define AIPS_MPRA_MPL5_MASK                      0x100u
+#define AIPS_MPRA_MPL5_SHIFT                     8
+#define AIPS_MPRA_MPL5_WIDTH                     1
+#define AIPS_MPRA_MPL5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL5_SHIFT))&AIPS_MPRA_MPL5_MASK)
+#define AIPS_MPRA_MTW5_MASK                      0x200u
+#define AIPS_MPRA_MTW5_SHIFT                     9
+#define AIPS_MPRA_MTW5_WIDTH                     1
+#define AIPS_MPRA_MTW5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW5_SHIFT))&AIPS_MPRA_MTW5_MASK)
+#define AIPS_MPRA_MTR5_MASK                      0x400u
+#define AIPS_MPRA_MTR5_SHIFT                     10
+#define AIPS_MPRA_MTR5_WIDTH                     1
+#define AIPS_MPRA_MTR5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR5_SHIFT))&AIPS_MPRA_MTR5_MASK)
+#define AIPS_MPRA_MPL4_MASK                      0x1000u
+#define AIPS_MPRA_MPL4_SHIFT                     12
+#define AIPS_MPRA_MPL4_WIDTH                     1
+#define AIPS_MPRA_MPL4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL4_SHIFT))&AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MTW4_MASK                      0x2000u
+#define AIPS_MPRA_MTW4_SHIFT                     13
+#define AIPS_MPRA_MTW4_WIDTH                     1
+#define AIPS_MPRA_MTW4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW4_SHIFT))&AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTR4_MASK                      0x4000u
+#define AIPS_MPRA_MTR4_SHIFT                     14
+#define AIPS_MPRA_MTR4_WIDTH                     1
+#define AIPS_MPRA_MTR4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR4_SHIFT))&AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MPL3_MASK                      0x10000u
+#define AIPS_MPRA_MPL3_SHIFT                     16
+#define AIPS_MPRA_MPL3_WIDTH                     1
+#define AIPS_MPRA_MPL3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL3_SHIFT))&AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MTW3_MASK                      0x20000u
+#define AIPS_MPRA_MTW3_SHIFT                     17
+#define AIPS_MPRA_MTW3_WIDTH                     1
+#define AIPS_MPRA_MTW3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW3_SHIFT))&AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTR3_MASK                      0x40000u
+#define AIPS_MPRA_MTR3_SHIFT                     18
+#define AIPS_MPRA_MTR3_WIDTH                     1
+#define AIPS_MPRA_MTR3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR3_SHIFT))&AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MPL2_MASK                      0x100000u
+#define AIPS_MPRA_MPL2_SHIFT                     20
+#define AIPS_MPRA_MPL2_WIDTH                     1
+#define AIPS_MPRA_MPL2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL2_SHIFT))&AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MTW2_MASK                      0x200000u
+#define AIPS_MPRA_MTW2_SHIFT                     21
+#define AIPS_MPRA_MTW2_WIDTH                     1
+#define AIPS_MPRA_MTW2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW2_SHIFT))&AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTR2_MASK                      0x400000u
+#define AIPS_MPRA_MTR2_SHIFT                     22
+#define AIPS_MPRA_MTR2_WIDTH                     1
+#define AIPS_MPRA_MTR2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR2_SHIFT))&AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MPL1_MASK                      0x1000000u
+#define AIPS_MPRA_MPL1_SHIFT                     24
+#define AIPS_MPRA_MPL1_WIDTH                     1
+#define AIPS_MPRA_MPL1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL1_SHIFT))&AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MTW1_MASK                      0x2000000u
+#define AIPS_MPRA_MTW1_SHIFT                     25
+#define AIPS_MPRA_MTW1_WIDTH                     1
+#define AIPS_MPRA_MTW1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW1_SHIFT))&AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTR1_MASK                      0x4000000u
+#define AIPS_MPRA_MTR1_SHIFT                     26
+#define AIPS_MPRA_MTR1_WIDTH                     1
+#define AIPS_MPRA_MTR1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR1_SHIFT))&AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MPL0_MASK                      0x10000000u
+#define AIPS_MPRA_MPL0_SHIFT                     28
+#define AIPS_MPRA_MPL0_WIDTH                     1
+#define AIPS_MPRA_MPL0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL0_SHIFT))&AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MTW0_MASK                      0x20000000u
+#define AIPS_MPRA_MTW0_SHIFT                     29
+#define AIPS_MPRA_MTW0_WIDTH                     1
+#define AIPS_MPRA_MTW0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW0_SHIFT))&AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTR0_MASK                      0x40000000u
+#define AIPS_MPRA_MTR0_SHIFT                     30
+#define AIPS_MPRA_MTR0_WIDTH                     1
+#define AIPS_MPRA_MTR0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR0_SHIFT))&AIPS_MPRA_MTR0_MASK)
+/* PACRA Bit Fields */
+#define AIPS_PACRA_TP7_MASK                      0x1u
+#define AIPS_PACRA_TP7_SHIFT                     0
+#define AIPS_PACRA_TP7_WIDTH                     1
+#define AIPS_PACRA_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP7_SHIFT))&AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_WP7_MASK                      0x2u
+#define AIPS_PACRA_WP7_SHIFT                     1
+#define AIPS_PACRA_WP7_WIDTH                     1
+#define AIPS_PACRA_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP7_SHIFT))&AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_SP7_MASK                      0x4u
+#define AIPS_PACRA_SP7_SHIFT                     2
+#define AIPS_PACRA_SP7_WIDTH                     1
+#define AIPS_PACRA_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP7_SHIFT))&AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_TP6_MASK                      0x10u
+#define AIPS_PACRA_TP6_SHIFT                     4
+#define AIPS_PACRA_TP6_WIDTH                     1
+#define AIPS_PACRA_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP6_SHIFT))&AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_WP6_MASK                      0x20u
+#define AIPS_PACRA_WP6_SHIFT                     5
+#define AIPS_PACRA_WP6_WIDTH                     1
+#define AIPS_PACRA_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP6_SHIFT))&AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_SP6_MASK                      0x40u
+#define AIPS_PACRA_SP6_SHIFT                     6
+#define AIPS_PACRA_SP6_WIDTH                     1
+#define AIPS_PACRA_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP6_SHIFT))&AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_TP5_MASK                      0x100u
+#define AIPS_PACRA_TP5_SHIFT                     8
+#define AIPS_PACRA_TP5_WIDTH                     1
+#define AIPS_PACRA_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP5_SHIFT))&AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_WP5_MASK                      0x200u
+#define AIPS_PACRA_WP5_SHIFT                     9
+#define AIPS_PACRA_WP5_WIDTH                     1
+#define AIPS_PACRA_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP5_SHIFT))&AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_SP5_MASK                      0x400u
+#define AIPS_PACRA_SP5_SHIFT                     10
+#define AIPS_PACRA_SP5_WIDTH                     1
+#define AIPS_PACRA_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP5_SHIFT))&AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_TP4_MASK                      0x1000u
+#define AIPS_PACRA_TP4_SHIFT                     12
+#define AIPS_PACRA_TP4_WIDTH                     1
+#define AIPS_PACRA_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP4_SHIFT))&AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_WP4_MASK                      0x2000u
+#define AIPS_PACRA_WP4_SHIFT                     13
+#define AIPS_PACRA_WP4_WIDTH                     1
+#define AIPS_PACRA_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP4_SHIFT))&AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_SP4_MASK                      0x4000u
+#define AIPS_PACRA_SP4_SHIFT                     14
+#define AIPS_PACRA_SP4_WIDTH                     1
+#define AIPS_PACRA_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP4_SHIFT))&AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_TP3_MASK                      0x10000u
+#define AIPS_PACRA_TP3_SHIFT                     16
+#define AIPS_PACRA_TP3_WIDTH                     1
+#define AIPS_PACRA_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP3_SHIFT))&AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_WP3_MASK                      0x20000u
+#define AIPS_PACRA_WP3_SHIFT                     17
+#define AIPS_PACRA_WP3_WIDTH                     1
+#define AIPS_PACRA_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP3_SHIFT))&AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_SP3_MASK                      0x40000u
+#define AIPS_PACRA_SP3_SHIFT                     18
+#define AIPS_PACRA_SP3_WIDTH                     1
+#define AIPS_PACRA_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP3_SHIFT))&AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_TP2_MASK                      0x100000u
+#define AIPS_PACRA_TP2_SHIFT                     20
+#define AIPS_PACRA_TP2_WIDTH                     1
+#define AIPS_PACRA_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP2_SHIFT))&AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_WP2_MASK                      0x200000u
+#define AIPS_PACRA_WP2_SHIFT                     21
+#define AIPS_PACRA_WP2_WIDTH                     1
+#define AIPS_PACRA_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP2_SHIFT))&AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_SP2_MASK                      0x400000u
+#define AIPS_PACRA_SP2_SHIFT                     22
+#define AIPS_PACRA_SP2_WIDTH                     1
+#define AIPS_PACRA_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP2_SHIFT))&AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_TP1_MASK                      0x1000000u
+#define AIPS_PACRA_TP1_SHIFT                     24
+#define AIPS_PACRA_TP1_WIDTH                     1
+#define AIPS_PACRA_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP1_SHIFT))&AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_WP1_MASK                      0x2000000u
+#define AIPS_PACRA_WP1_SHIFT                     25
+#define AIPS_PACRA_WP1_WIDTH                     1
+#define AIPS_PACRA_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP1_SHIFT))&AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_SP1_MASK                      0x4000000u
+#define AIPS_PACRA_SP1_SHIFT                     26
+#define AIPS_PACRA_SP1_WIDTH                     1
+#define AIPS_PACRA_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP1_SHIFT))&AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_TP0_MASK                      0x10000000u
+#define AIPS_PACRA_TP0_SHIFT                     28
+#define AIPS_PACRA_TP0_WIDTH                     1
+#define AIPS_PACRA_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP0_SHIFT))&AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_WP0_MASK                      0x20000000u
+#define AIPS_PACRA_WP0_SHIFT                     29
+#define AIPS_PACRA_WP0_WIDTH                     1
+#define AIPS_PACRA_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP0_SHIFT))&AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_SP0_MASK                      0x40000000u
+#define AIPS_PACRA_SP0_SHIFT                     30
+#define AIPS_PACRA_SP0_WIDTH                     1
+#define AIPS_PACRA_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP0_SHIFT))&AIPS_PACRA_SP0_MASK)
+/* PACRB Bit Fields */
+#define AIPS_PACRB_TP7_MASK                      0x1u
+#define AIPS_PACRB_TP7_SHIFT                     0
+#define AIPS_PACRB_TP7_WIDTH                     1
+#define AIPS_PACRB_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP7_SHIFT))&AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_WP7_MASK                      0x2u
+#define AIPS_PACRB_WP7_SHIFT                     1
+#define AIPS_PACRB_WP7_WIDTH                     1
+#define AIPS_PACRB_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP7_SHIFT))&AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_SP7_MASK                      0x4u
+#define AIPS_PACRB_SP7_SHIFT                     2
+#define AIPS_PACRB_SP7_WIDTH                     1
+#define AIPS_PACRB_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP7_SHIFT))&AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_TP6_MASK                      0x10u
+#define AIPS_PACRB_TP6_SHIFT                     4
+#define AIPS_PACRB_TP6_WIDTH                     1
+#define AIPS_PACRB_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP6_SHIFT))&AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_WP6_MASK                      0x20u
+#define AIPS_PACRB_WP6_SHIFT                     5
+#define AIPS_PACRB_WP6_WIDTH                     1
+#define AIPS_PACRB_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP6_SHIFT))&AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_SP6_MASK                      0x40u
+#define AIPS_PACRB_SP6_SHIFT                     6
+#define AIPS_PACRB_SP6_WIDTH                     1
+#define AIPS_PACRB_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP6_SHIFT))&AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_TP5_MASK                      0x100u
+#define AIPS_PACRB_TP5_SHIFT                     8
+#define AIPS_PACRB_TP5_WIDTH                     1
+#define AIPS_PACRB_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP5_SHIFT))&AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_WP5_MASK                      0x200u
+#define AIPS_PACRB_WP5_SHIFT                     9
+#define AIPS_PACRB_WP5_WIDTH                     1
+#define AIPS_PACRB_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP5_SHIFT))&AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_SP5_MASK                      0x400u
+#define AIPS_PACRB_SP5_SHIFT                     10
+#define AIPS_PACRB_SP5_WIDTH                     1
+#define AIPS_PACRB_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP5_SHIFT))&AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_TP4_MASK                      0x1000u
+#define AIPS_PACRB_TP4_SHIFT                     12
+#define AIPS_PACRB_TP4_WIDTH                     1
+#define AIPS_PACRB_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP4_SHIFT))&AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_WP4_MASK                      0x2000u
+#define AIPS_PACRB_WP4_SHIFT                     13
+#define AIPS_PACRB_WP4_WIDTH                     1
+#define AIPS_PACRB_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP4_SHIFT))&AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_SP4_MASK                      0x4000u
+#define AIPS_PACRB_SP4_SHIFT                     14
+#define AIPS_PACRB_SP4_WIDTH                     1
+#define AIPS_PACRB_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP4_SHIFT))&AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_TP3_MASK                      0x10000u
+#define AIPS_PACRB_TP3_SHIFT                     16
+#define AIPS_PACRB_TP3_WIDTH                     1
+#define AIPS_PACRB_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP3_SHIFT))&AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_WP3_MASK                      0x20000u
+#define AIPS_PACRB_WP3_SHIFT                     17
+#define AIPS_PACRB_WP3_WIDTH                     1
+#define AIPS_PACRB_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP3_SHIFT))&AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_SP3_MASK                      0x40000u
+#define AIPS_PACRB_SP3_SHIFT                     18
+#define AIPS_PACRB_SP3_WIDTH                     1
+#define AIPS_PACRB_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP3_SHIFT))&AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_TP2_MASK                      0x100000u
+#define AIPS_PACRB_TP2_SHIFT                     20
+#define AIPS_PACRB_TP2_WIDTH                     1
+#define AIPS_PACRB_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP2_SHIFT))&AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_WP2_MASK                      0x200000u
+#define AIPS_PACRB_WP2_SHIFT                     21
+#define AIPS_PACRB_WP2_WIDTH                     1
+#define AIPS_PACRB_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP2_SHIFT))&AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_SP2_MASK                      0x400000u
+#define AIPS_PACRB_SP2_SHIFT                     22
+#define AIPS_PACRB_SP2_WIDTH                     1
+#define AIPS_PACRB_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP2_SHIFT))&AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_TP1_MASK                      0x1000000u
+#define AIPS_PACRB_TP1_SHIFT                     24
+#define AIPS_PACRB_TP1_WIDTH                     1
+#define AIPS_PACRB_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP1_SHIFT))&AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_WP1_MASK                      0x2000000u
+#define AIPS_PACRB_WP1_SHIFT                     25
+#define AIPS_PACRB_WP1_WIDTH                     1
+#define AIPS_PACRB_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP1_SHIFT))&AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_SP1_MASK                      0x4000000u
+#define AIPS_PACRB_SP1_SHIFT                     26
+#define AIPS_PACRB_SP1_WIDTH                     1
+#define AIPS_PACRB_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP1_SHIFT))&AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_TP0_MASK                      0x10000000u
+#define AIPS_PACRB_TP0_SHIFT                     28
+#define AIPS_PACRB_TP0_WIDTH                     1
+#define AIPS_PACRB_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP0_SHIFT))&AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_WP0_MASK                      0x20000000u
+#define AIPS_PACRB_WP0_SHIFT                     29
+#define AIPS_PACRB_WP0_WIDTH                     1
+#define AIPS_PACRB_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP0_SHIFT))&AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_SP0_MASK                      0x40000000u
+#define AIPS_PACRB_SP0_SHIFT                     30
+#define AIPS_PACRB_SP0_WIDTH                     1
+#define AIPS_PACRB_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP0_SHIFT))&AIPS_PACRB_SP0_MASK)
+/* PACRC Bit Fields */
+#define AIPS_PACRC_TP7_MASK                      0x1u
+#define AIPS_PACRC_TP7_SHIFT                     0
+#define AIPS_PACRC_TP7_WIDTH                     1
+#define AIPS_PACRC_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP7_SHIFT))&AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_WP7_MASK                      0x2u
+#define AIPS_PACRC_WP7_SHIFT                     1
+#define AIPS_PACRC_WP7_WIDTH                     1
+#define AIPS_PACRC_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP7_SHIFT))&AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_SP7_MASK                      0x4u
+#define AIPS_PACRC_SP7_SHIFT                     2
+#define AIPS_PACRC_SP7_WIDTH                     1
+#define AIPS_PACRC_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP7_SHIFT))&AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_TP6_MASK                      0x10u
+#define AIPS_PACRC_TP6_SHIFT                     4
+#define AIPS_PACRC_TP6_WIDTH                     1
+#define AIPS_PACRC_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP6_SHIFT))&AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_WP6_MASK                      0x20u
+#define AIPS_PACRC_WP6_SHIFT                     5
+#define AIPS_PACRC_WP6_WIDTH                     1
+#define AIPS_PACRC_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP6_SHIFT))&AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_SP6_MASK                      0x40u
+#define AIPS_PACRC_SP6_SHIFT                     6
+#define AIPS_PACRC_SP6_WIDTH                     1
+#define AIPS_PACRC_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP6_SHIFT))&AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_TP5_MASK                      0x100u
+#define AIPS_PACRC_TP5_SHIFT                     8
+#define AIPS_PACRC_TP5_WIDTH                     1
+#define AIPS_PACRC_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP5_SHIFT))&AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_WP5_MASK                      0x200u
+#define AIPS_PACRC_WP5_SHIFT                     9
+#define AIPS_PACRC_WP5_WIDTH                     1
+#define AIPS_PACRC_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP5_SHIFT))&AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_SP5_MASK                      0x400u
+#define AIPS_PACRC_SP5_SHIFT                     10
+#define AIPS_PACRC_SP5_WIDTH                     1
+#define AIPS_PACRC_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP5_SHIFT))&AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_TP4_MASK                      0x1000u
+#define AIPS_PACRC_TP4_SHIFT                     12
+#define AIPS_PACRC_TP4_WIDTH                     1
+#define AIPS_PACRC_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP4_SHIFT))&AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_WP4_MASK                      0x2000u
+#define AIPS_PACRC_WP4_SHIFT                     13
+#define AIPS_PACRC_WP4_WIDTH                     1
+#define AIPS_PACRC_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP4_SHIFT))&AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_SP4_MASK                      0x4000u
+#define AIPS_PACRC_SP4_SHIFT                     14
+#define AIPS_PACRC_SP4_WIDTH                     1
+#define AIPS_PACRC_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP4_SHIFT))&AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_TP3_MASK                      0x10000u
+#define AIPS_PACRC_TP3_SHIFT                     16
+#define AIPS_PACRC_TP3_WIDTH                     1
+#define AIPS_PACRC_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP3_SHIFT))&AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_WP3_MASK                      0x20000u
+#define AIPS_PACRC_WP3_SHIFT                     17
+#define AIPS_PACRC_WP3_WIDTH                     1
+#define AIPS_PACRC_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP3_SHIFT))&AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_SP3_MASK                      0x40000u
+#define AIPS_PACRC_SP3_SHIFT                     18
+#define AIPS_PACRC_SP3_WIDTH                     1
+#define AIPS_PACRC_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP3_SHIFT))&AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_TP2_MASK                      0x100000u
+#define AIPS_PACRC_TP2_SHIFT                     20
+#define AIPS_PACRC_TP2_WIDTH                     1
+#define AIPS_PACRC_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP2_SHIFT))&AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_WP2_MASK                      0x200000u
+#define AIPS_PACRC_WP2_SHIFT                     21
+#define AIPS_PACRC_WP2_WIDTH                     1
+#define AIPS_PACRC_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP2_SHIFT))&AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_SP2_MASK                      0x400000u
+#define AIPS_PACRC_SP2_SHIFT                     22
+#define AIPS_PACRC_SP2_WIDTH                     1
+#define AIPS_PACRC_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP2_SHIFT))&AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_TP1_MASK                      0x1000000u
+#define AIPS_PACRC_TP1_SHIFT                     24
+#define AIPS_PACRC_TP1_WIDTH                     1
+#define AIPS_PACRC_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP1_SHIFT))&AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_WP1_MASK                      0x2000000u
+#define AIPS_PACRC_WP1_SHIFT                     25
+#define AIPS_PACRC_WP1_WIDTH                     1
+#define AIPS_PACRC_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP1_SHIFT))&AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_SP1_MASK                      0x4000000u
+#define AIPS_PACRC_SP1_SHIFT                     26
+#define AIPS_PACRC_SP1_WIDTH                     1
+#define AIPS_PACRC_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP1_SHIFT))&AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_TP0_MASK                      0x10000000u
+#define AIPS_PACRC_TP0_SHIFT                     28
+#define AIPS_PACRC_TP0_WIDTH                     1
+#define AIPS_PACRC_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP0_SHIFT))&AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_WP0_MASK                      0x20000000u
+#define AIPS_PACRC_WP0_SHIFT                     29
+#define AIPS_PACRC_WP0_WIDTH                     1
+#define AIPS_PACRC_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP0_SHIFT))&AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_SP0_MASK                      0x40000000u
+#define AIPS_PACRC_SP0_SHIFT                     30
+#define AIPS_PACRC_SP0_WIDTH                     1
+#define AIPS_PACRC_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP0_SHIFT))&AIPS_PACRC_SP0_MASK)
+/* PACRD Bit Fields */
+#define AIPS_PACRD_TP7_MASK                      0x1u
+#define AIPS_PACRD_TP7_SHIFT                     0
+#define AIPS_PACRD_TP7_WIDTH                     1
+#define AIPS_PACRD_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP7_SHIFT))&AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_WP7_MASK                      0x2u
+#define AIPS_PACRD_WP7_SHIFT                     1
+#define AIPS_PACRD_WP7_WIDTH                     1
+#define AIPS_PACRD_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP7_SHIFT))&AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_SP7_MASK                      0x4u
+#define AIPS_PACRD_SP7_SHIFT                     2
+#define AIPS_PACRD_SP7_WIDTH                     1
+#define AIPS_PACRD_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP7_SHIFT))&AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_TP6_MASK                      0x10u
+#define AIPS_PACRD_TP6_SHIFT                     4
+#define AIPS_PACRD_TP6_WIDTH                     1
+#define AIPS_PACRD_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP6_SHIFT))&AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_WP6_MASK                      0x20u
+#define AIPS_PACRD_WP6_SHIFT                     5
+#define AIPS_PACRD_WP6_WIDTH                     1
+#define AIPS_PACRD_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP6_SHIFT))&AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_SP6_MASK                      0x40u
+#define AIPS_PACRD_SP6_SHIFT                     6
+#define AIPS_PACRD_SP6_WIDTH                     1
+#define AIPS_PACRD_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP6_SHIFT))&AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_TP5_MASK                      0x100u
+#define AIPS_PACRD_TP5_SHIFT                     8
+#define AIPS_PACRD_TP5_WIDTH                     1
+#define AIPS_PACRD_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP5_SHIFT))&AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_WP5_MASK                      0x200u
+#define AIPS_PACRD_WP5_SHIFT                     9
+#define AIPS_PACRD_WP5_WIDTH                     1
+#define AIPS_PACRD_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP5_SHIFT))&AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_SP5_MASK                      0x400u
+#define AIPS_PACRD_SP5_SHIFT                     10
+#define AIPS_PACRD_SP5_WIDTH                     1
+#define AIPS_PACRD_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP5_SHIFT))&AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_TP4_MASK                      0x1000u
+#define AIPS_PACRD_TP4_SHIFT                     12
+#define AIPS_PACRD_TP4_WIDTH                     1
+#define AIPS_PACRD_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP4_SHIFT))&AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_WP4_MASK                      0x2000u
+#define AIPS_PACRD_WP4_SHIFT                     13
+#define AIPS_PACRD_WP4_WIDTH                     1
+#define AIPS_PACRD_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP4_SHIFT))&AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_SP4_MASK                      0x4000u
+#define AIPS_PACRD_SP4_SHIFT                     14
+#define AIPS_PACRD_SP4_WIDTH                     1
+#define AIPS_PACRD_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP4_SHIFT))&AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_TP3_MASK                      0x10000u
+#define AIPS_PACRD_TP3_SHIFT                     16
+#define AIPS_PACRD_TP3_WIDTH                     1
+#define AIPS_PACRD_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP3_SHIFT))&AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_WP3_MASK                      0x20000u
+#define AIPS_PACRD_WP3_SHIFT                     17
+#define AIPS_PACRD_WP3_WIDTH                     1
+#define AIPS_PACRD_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP3_SHIFT))&AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_SP3_MASK                      0x40000u
+#define AIPS_PACRD_SP3_SHIFT                     18
+#define AIPS_PACRD_SP3_WIDTH                     1
+#define AIPS_PACRD_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP3_SHIFT))&AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_TP2_MASK                      0x100000u
+#define AIPS_PACRD_TP2_SHIFT                     20
+#define AIPS_PACRD_TP2_WIDTH                     1
+#define AIPS_PACRD_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP2_SHIFT))&AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_WP2_MASK                      0x200000u
+#define AIPS_PACRD_WP2_SHIFT                     21
+#define AIPS_PACRD_WP2_WIDTH                     1
+#define AIPS_PACRD_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP2_SHIFT))&AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_SP2_MASK                      0x400000u
+#define AIPS_PACRD_SP2_SHIFT                     22
+#define AIPS_PACRD_SP2_WIDTH                     1
+#define AIPS_PACRD_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP2_SHIFT))&AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_TP1_MASK                      0x1000000u
+#define AIPS_PACRD_TP1_SHIFT                     24
+#define AIPS_PACRD_TP1_WIDTH                     1
+#define AIPS_PACRD_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP1_SHIFT))&AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_WP1_MASK                      0x2000000u
+#define AIPS_PACRD_WP1_SHIFT                     25
+#define AIPS_PACRD_WP1_WIDTH                     1
+#define AIPS_PACRD_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP1_SHIFT))&AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_SP1_MASK                      0x4000000u
+#define AIPS_PACRD_SP1_SHIFT                     26
+#define AIPS_PACRD_SP1_WIDTH                     1
+#define AIPS_PACRD_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP1_SHIFT))&AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_TP0_MASK                      0x10000000u
+#define AIPS_PACRD_TP0_SHIFT                     28
+#define AIPS_PACRD_TP0_WIDTH                     1
+#define AIPS_PACRD_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP0_SHIFT))&AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_WP0_MASK                      0x20000000u
+#define AIPS_PACRD_WP0_SHIFT                     29
+#define AIPS_PACRD_WP0_WIDTH                     1
+#define AIPS_PACRD_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP0_SHIFT))&AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_SP0_MASK                      0x40000000u
+#define AIPS_PACRD_SP0_SHIFT                     30
+#define AIPS_PACRD_SP0_WIDTH                     1
+#define AIPS_PACRD_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP0_SHIFT))&AIPS_PACRD_SP0_MASK)
+/* PACRE Bit Fields */
+#define AIPS_PACRE_TP7_MASK                      0x1u
+#define AIPS_PACRE_TP7_SHIFT                     0
+#define AIPS_PACRE_TP7_WIDTH                     1
+#define AIPS_PACRE_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP7_SHIFT))&AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_WP7_MASK                      0x2u
+#define AIPS_PACRE_WP7_SHIFT                     1
+#define AIPS_PACRE_WP7_WIDTH                     1
+#define AIPS_PACRE_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP7_SHIFT))&AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_SP7_MASK                      0x4u
+#define AIPS_PACRE_SP7_SHIFT                     2
+#define AIPS_PACRE_SP7_WIDTH                     1
+#define AIPS_PACRE_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP7_SHIFT))&AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_TP6_MASK                      0x10u
+#define AIPS_PACRE_TP6_SHIFT                     4
+#define AIPS_PACRE_TP6_WIDTH                     1
+#define AIPS_PACRE_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP6_SHIFT))&AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_WP6_MASK                      0x20u
+#define AIPS_PACRE_WP6_SHIFT                     5
+#define AIPS_PACRE_WP6_WIDTH                     1
+#define AIPS_PACRE_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP6_SHIFT))&AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_SP6_MASK                      0x40u
+#define AIPS_PACRE_SP6_SHIFT                     6
+#define AIPS_PACRE_SP6_WIDTH                     1
+#define AIPS_PACRE_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP6_SHIFT))&AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_TP5_MASK                      0x100u
+#define AIPS_PACRE_TP5_SHIFT                     8
+#define AIPS_PACRE_TP5_WIDTH                     1
+#define AIPS_PACRE_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP5_SHIFT))&AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_WP5_MASK                      0x200u
+#define AIPS_PACRE_WP5_SHIFT                     9
+#define AIPS_PACRE_WP5_WIDTH                     1
+#define AIPS_PACRE_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP5_SHIFT))&AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_SP5_MASK                      0x400u
+#define AIPS_PACRE_SP5_SHIFT                     10
+#define AIPS_PACRE_SP5_WIDTH                     1
+#define AIPS_PACRE_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP5_SHIFT))&AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_TP4_MASK                      0x1000u
+#define AIPS_PACRE_TP4_SHIFT                     12
+#define AIPS_PACRE_TP4_WIDTH                     1
+#define AIPS_PACRE_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP4_SHIFT))&AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_WP4_MASK                      0x2000u
+#define AIPS_PACRE_WP4_SHIFT                     13
+#define AIPS_PACRE_WP4_WIDTH                     1
+#define AIPS_PACRE_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP4_SHIFT))&AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_SP4_MASK                      0x4000u
+#define AIPS_PACRE_SP4_SHIFT                     14
+#define AIPS_PACRE_SP4_WIDTH                     1
+#define AIPS_PACRE_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP4_SHIFT))&AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_TP3_MASK                      0x10000u
+#define AIPS_PACRE_TP3_SHIFT                     16
+#define AIPS_PACRE_TP3_WIDTH                     1
+#define AIPS_PACRE_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP3_SHIFT))&AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_WP3_MASK                      0x20000u
+#define AIPS_PACRE_WP3_SHIFT                     17
+#define AIPS_PACRE_WP3_WIDTH                     1
+#define AIPS_PACRE_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP3_SHIFT))&AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_SP3_MASK                      0x40000u
+#define AIPS_PACRE_SP3_SHIFT                     18
+#define AIPS_PACRE_SP3_WIDTH                     1
+#define AIPS_PACRE_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP3_SHIFT))&AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_TP2_MASK                      0x100000u
+#define AIPS_PACRE_TP2_SHIFT                     20
+#define AIPS_PACRE_TP2_WIDTH                     1
+#define AIPS_PACRE_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP2_SHIFT))&AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_WP2_MASK                      0x200000u
+#define AIPS_PACRE_WP2_SHIFT                     21
+#define AIPS_PACRE_WP2_WIDTH                     1
+#define AIPS_PACRE_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP2_SHIFT))&AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_SP2_MASK                      0x400000u
+#define AIPS_PACRE_SP2_SHIFT                     22
+#define AIPS_PACRE_SP2_WIDTH                     1
+#define AIPS_PACRE_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP2_SHIFT))&AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_TP1_MASK                      0x1000000u
+#define AIPS_PACRE_TP1_SHIFT                     24
+#define AIPS_PACRE_TP1_WIDTH                     1
+#define AIPS_PACRE_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP1_SHIFT))&AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_WP1_MASK                      0x2000000u
+#define AIPS_PACRE_WP1_SHIFT                     25
+#define AIPS_PACRE_WP1_WIDTH                     1
+#define AIPS_PACRE_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP1_SHIFT))&AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_SP1_MASK                      0x4000000u
+#define AIPS_PACRE_SP1_SHIFT                     26
+#define AIPS_PACRE_SP1_WIDTH                     1
+#define AIPS_PACRE_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP1_SHIFT))&AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_TP0_MASK                      0x10000000u
+#define AIPS_PACRE_TP0_SHIFT                     28
+#define AIPS_PACRE_TP0_WIDTH                     1
+#define AIPS_PACRE_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP0_SHIFT))&AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_WP0_MASK                      0x20000000u
+#define AIPS_PACRE_WP0_SHIFT                     29
+#define AIPS_PACRE_WP0_WIDTH                     1
+#define AIPS_PACRE_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP0_SHIFT))&AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_SP0_MASK                      0x40000000u
+#define AIPS_PACRE_SP0_SHIFT                     30
+#define AIPS_PACRE_SP0_WIDTH                     1
+#define AIPS_PACRE_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP0_SHIFT))&AIPS_PACRE_SP0_MASK)
+/* PACRF Bit Fields */
+#define AIPS_PACRF_TP7_MASK                      0x1u
+#define AIPS_PACRF_TP7_SHIFT                     0
+#define AIPS_PACRF_TP7_WIDTH                     1
+#define AIPS_PACRF_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP7_SHIFT))&AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_WP7_MASK                      0x2u
+#define AIPS_PACRF_WP7_SHIFT                     1
+#define AIPS_PACRF_WP7_WIDTH                     1
+#define AIPS_PACRF_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP7_SHIFT))&AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_SP7_MASK                      0x4u
+#define AIPS_PACRF_SP7_SHIFT                     2
+#define AIPS_PACRF_SP7_WIDTH                     1
+#define AIPS_PACRF_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP7_SHIFT))&AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_TP6_MASK                      0x10u
+#define AIPS_PACRF_TP6_SHIFT                     4
+#define AIPS_PACRF_TP6_WIDTH                     1
+#define AIPS_PACRF_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP6_SHIFT))&AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_WP6_MASK                      0x20u
+#define AIPS_PACRF_WP6_SHIFT                     5
+#define AIPS_PACRF_WP6_WIDTH                     1
+#define AIPS_PACRF_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP6_SHIFT))&AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_SP6_MASK                      0x40u
+#define AIPS_PACRF_SP6_SHIFT                     6
+#define AIPS_PACRF_SP6_WIDTH                     1
+#define AIPS_PACRF_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP6_SHIFT))&AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_TP5_MASK                      0x100u
+#define AIPS_PACRF_TP5_SHIFT                     8
+#define AIPS_PACRF_TP5_WIDTH                     1
+#define AIPS_PACRF_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP5_SHIFT))&AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_WP5_MASK                      0x200u
+#define AIPS_PACRF_WP5_SHIFT                     9
+#define AIPS_PACRF_WP5_WIDTH                     1
+#define AIPS_PACRF_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP5_SHIFT))&AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_SP5_MASK                      0x400u
+#define AIPS_PACRF_SP5_SHIFT                     10
+#define AIPS_PACRF_SP5_WIDTH                     1
+#define AIPS_PACRF_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP5_SHIFT))&AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_TP4_MASK                      0x1000u
+#define AIPS_PACRF_TP4_SHIFT                     12
+#define AIPS_PACRF_TP4_WIDTH                     1
+#define AIPS_PACRF_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP4_SHIFT))&AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_WP4_MASK                      0x2000u
+#define AIPS_PACRF_WP4_SHIFT                     13
+#define AIPS_PACRF_WP4_WIDTH                     1
+#define AIPS_PACRF_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP4_SHIFT))&AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_SP4_MASK                      0x4000u
+#define AIPS_PACRF_SP4_SHIFT                     14
+#define AIPS_PACRF_SP4_WIDTH                     1
+#define AIPS_PACRF_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP4_SHIFT))&AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_TP3_MASK                      0x10000u
+#define AIPS_PACRF_TP3_SHIFT                     16
+#define AIPS_PACRF_TP3_WIDTH                     1
+#define AIPS_PACRF_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP3_SHIFT))&AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_WP3_MASK                      0x20000u
+#define AIPS_PACRF_WP3_SHIFT                     17
+#define AIPS_PACRF_WP3_WIDTH                     1
+#define AIPS_PACRF_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP3_SHIFT))&AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_SP3_MASK                      0x40000u
+#define AIPS_PACRF_SP3_SHIFT                     18
+#define AIPS_PACRF_SP3_WIDTH                     1
+#define AIPS_PACRF_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP3_SHIFT))&AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_TP2_MASK                      0x100000u
+#define AIPS_PACRF_TP2_SHIFT                     20
+#define AIPS_PACRF_TP2_WIDTH                     1
+#define AIPS_PACRF_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP2_SHIFT))&AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_WP2_MASK                      0x200000u
+#define AIPS_PACRF_WP2_SHIFT                     21
+#define AIPS_PACRF_WP2_WIDTH                     1
+#define AIPS_PACRF_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP2_SHIFT))&AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_SP2_MASK                      0x400000u
+#define AIPS_PACRF_SP2_SHIFT                     22
+#define AIPS_PACRF_SP2_WIDTH                     1
+#define AIPS_PACRF_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP2_SHIFT))&AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_TP1_MASK                      0x1000000u
+#define AIPS_PACRF_TP1_SHIFT                     24
+#define AIPS_PACRF_TP1_WIDTH                     1
+#define AIPS_PACRF_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP1_SHIFT))&AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_WP1_MASK                      0x2000000u
+#define AIPS_PACRF_WP1_SHIFT                     25
+#define AIPS_PACRF_WP1_WIDTH                     1
+#define AIPS_PACRF_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP1_SHIFT))&AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_SP1_MASK                      0x4000000u
+#define AIPS_PACRF_SP1_SHIFT                     26
+#define AIPS_PACRF_SP1_WIDTH                     1
+#define AIPS_PACRF_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP1_SHIFT))&AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_TP0_MASK                      0x10000000u
+#define AIPS_PACRF_TP0_SHIFT                     28
+#define AIPS_PACRF_TP0_WIDTH                     1
+#define AIPS_PACRF_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP0_SHIFT))&AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_WP0_MASK                      0x20000000u
+#define AIPS_PACRF_WP0_SHIFT                     29
+#define AIPS_PACRF_WP0_WIDTH                     1
+#define AIPS_PACRF_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP0_SHIFT))&AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_SP0_MASK                      0x40000000u
+#define AIPS_PACRF_SP0_SHIFT                     30
+#define AIPS_PACRF_SP0_WIDTH                     1
+#define AIPS_PACRF_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP0_SHIFT))&AIPS_PACRF_SP0_MASK)
+/* PACRG Bit Fields */
+#define AIPS_PACRG_TP7_MASK                      0x1u
+#define AIPS_PACRG_TP7_SHIFT                     0
+#define AIPS_PACRG_TP7_WIDTH                     1
+#define AIPS_PACRG_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP7_SHIFT))&AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_WP7_MASK                      0x2u
+#define AIPS_PACRG_WP7_SHIFT                     1
+#define AIPS_PACRG_WP7_WIDTH                     1
+#define AIPS_PACRG_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP7_SHIFT))&AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_SP7_MASK                      0x4u
+#define AIPS_PACRG_SP7_SHIFT                     2
+#define AIPS_PACRG_SP7_WIDTH                     1
+#define AIPS_PACRG_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP7_SHIFT))&AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_TP6_MASK                      0x10u
+#define AIPS_PACRG_TP6_SHIFT                     4
+#define AIPS_PACRG_TP6_WIDTH                     1
+#define AIPS_PACRG_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP6_SHIFT))&AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_WP6_MASK                      0x20u
+#define AIPS_PACRG_WP6_SHIFT                     5
+#define AIPS_PACRG_WP6_WIDTH                     1
+#define AIPS_PACRG_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP6_SHIFT))&AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_SP6_MASK                      0x40u
+#define AIPS_PACRG_SP6_SHIFT                     6
+#define AIPS_PACRG_SP6_WIDTH                     1
+#define AIPS_PACRG_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP6_SHIFT))&AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_TP5_MASK                      0x100u
+#define AIPS_PACRG_TP5_SHIFT                     8
+#define AIPS_PACRG_TP5_WIDTH                     1
+#define AIPS_PACRG_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP5_SHIFT))&AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_WP5_MASK                      0x200u
+#define AIPS_PACRG_WP5_SHIFT                     9
+#define AIPS_PACRG_WP5_WIDTH                     1
+#define AIPS_PACRG_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP5_SHIFT))&AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_SP5_MASK                      0x400u
+#define AIPS_PACRG_SP5_SHIFT                     10
+#define AIPS_PACRG_SP5_WIDTH                     1
+#define AIPS_PACRG_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP5_SHIFT))&AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_TP4_MASK                      0x1000u
+#define AIPS_PACRG_TP4_SHIFT                     12
+#define AIPS_PACRG_TP4_WIDTH                     1
+#define AIPS_PACRG_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP4_SHIFT))&AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_WP4_MASK                      0x2000u
+#define AIPS_PACRG_WP4_SHIFT                     13
+#define AIPS_PACRG_WP4_WIDTH                     1
+#define AIPS_PACRG_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP4_SHIFT))&AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_SP4_MASK                      0x4000u
+#define AIPS_PACRG_SP4_SHIFT                     14
+#define AIPS_PACRG_SP4_WIDTH                     1
+#define AIPS_PACRG_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP4_SHIFT))&AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_TP3_MASK                      0x10000u
+#define AIPS_PACRG_TP3_SHIFT                     16
+#define AIPS_PACRG_TP3_WIDTH                     1
+#define AIPS_PACRG_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP3_SHIFT))&AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_WP3_MASK                      0x20000u
+#define AIPS_PACRG_WP3_SHIFT                     17
+#define AIPS_PACRG_WP3_WIDTH                     1
+#define AIPS_PACRG_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP3_SHIFT))&AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_SP3_MASK                      0x40000u
+#define AIPS_PACRG_SP3_SHIFT                     18
+#define AIPS_PACRG_SP3_WIDTH                     1
+#define AIPS_PACRG_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP3_SHIFT))&AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_TP2_MASK                      0x100000u
+#define AIPS_PACRG_TP2_SHIFT                     20
+#define AIPS_PACRG_TP2_WIDTH                     1
+#define AIPS_PACRG_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP2_SHIFT))&AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_WP2_MASK                      0x200000u
+#define AIPS_PACRG_WP2_SHIFT                     21
+#define AIPS_PACRG_WP2_WIDTH                     1
+#define AIPS_PACRG_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP2_SHIFT))&AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_SP2_MASK                      0x400000u
+#define AIPS_PACRG_SP2_SHIFT                     22
+#define AIPS_PACRG_SP2_WIDTH                     1
+#define AIPS_PACRG_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP2_SHIFT))&AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_TP1_MASK                      0x1000000u
+#define AIPS_PACRG_TP1_SHIFT                     24
+#define AIPS_PACRG_TP1_WIDTH                     1
+#define AIPS_PACRG_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP1_SHIFT))&AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_WP1_MASK                      0x2000000u
+#define AIPS_PACRG_WP1_SHIFT                     25
+#define AIPS_PACRG_WP1_WIDTH                     1
+#define AIPS_PACRG_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP1_SHIFT))&AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_SP1_MASK                      0x4000000u
+#define AIPS_PACRG_SP1_SHIFT                     26
+#define AIPS_PACRG_SP1_WIDTH                     1
+#define AIPS_PACRG_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP1_SHIFT))&AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_TP0_MASK                      0x10000000u
+#define AIPS_PACRG_TP0_SHIFT                     28
+#define AIPS_PACRG_TP0_WIDTH                     1
+#define AIPS_PACRG_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP0_SHIFT))&AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_WP0_MASK                      0x20000000u
+#define AIPS_PACRG_WP0_SHIFT                     29
+#define AIPS_PACRG_WP0_WIDTH                     1
+#define AIPS_PACRG_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP0_SHIFT))&AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_SP0_MASK                      0x40000000u
+#define AIPS_PACRG_SP0_SHIFT                     30
+#define AIPS_PACRG_SP0_WIDTH                     1
+#define AIPS_PACRG_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP0_SHIFT))&AIPS_PACRG_SP0_MASK)
+/* PACRH Bit Fields */
+#define AIPS_PACRH_TP7_MASK                      0x1u
+#define AIPS_PACRH_TP7_SHIFT                     0
+#define AIPS_PACRH_TP7_WIDTH                     1
+#define AIPS_PACRH_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP7_SHIFT))&AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_WP7_MASK                      0x2u
+#define AIPS_PACRH_WP7_SHIFT                     1
+#define AIPS_PACRH_WP7_WIDTH                     1
+#define AIPS_PACRH_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP7_SHIFT))&AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_SP7_MASK                      0x4u
+#define AIPS_PACRH_SP7_SHIFT                     2
+#define AIPS_PACRH_SP7_WIDTH                     1
+#define AIPS_PACRH_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP7_SHIFT))&AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_TP6_MASK                      0x10u
+#define AIPS_PACRH_TP6_SHIFT                     4
+#define AIPS_PACRH_TP6_WIDTH                     1
+#define AIPS_PACRH_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP6_SHIFT))&AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_WP6_MASK                      0x20u
+#define AIPS_PACRH_WP6_SHIFT                     5
+#define AIPS_PACRH_WP6_WIDTH                     1
+#define AIPS_PACRH_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP6_SHIFT))&AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_SP6_MASK                      0x40u
+#define AIPS_PACRH_SP6_SHIFT                     6
+#define AIPS_PACRH_SP6_WIDTH                     1
+#define AIPS_PACRH_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP6_SHIFT))&AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_TP5_MASK                      0x100u
+#define AIPS_PACRH_TP5_SHIFT                     8
+#define AIPS_PACRH_TP5_WIDTH                     1
+#define AIPS_PACRH_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP5_SHIFT))&AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_WP5_MASK                      0x200u
+#define AIPS_PACRH_WP5_SHIFT                     9
+#define AIPS_PACRH_WP5_WIDTH                     1
+#define AIPS_PACRH_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP5_SHIFT))&AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_SP5_MASK                      0x400u
+#define AIPS_PACRH_SP5_SHIFT                     10
+#define AIPS_PACRH_SP5_WIDTH                     1
+#define AIPS_PACRH_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP5_SHIFT))&AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_TP4_MASK                      0x1000u
+#define AIPS_PACRH_TP4_SHIFT                     12
+#define AIPS_PACRH_TP4_WIDTH                     1
+#define AIPS_PACRH_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP4_SHIFT))&AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_WP4_MASK                      0x2000u
+#define AIPS_PACRH_WP4_SHIFT                     13
+#define AIPS_PACRH_WP4_WIDTH                     1
+#define AIPS_PACRH_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP4_SHIFT))&AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_SP4_MASK                      0x4000u
+#define AIPS_PACRH_SP4_SHIFT                     14
+#define AIPS_PACRH_SP4_WIDTH                     1
+#define AIPS_PACRH_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP4_SHIFT))&AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_TP3_MASK                      0x10000u
+#define AIPS_PACRH_TP3_SHIFT                     16
+#define AIPS_PACRH_TP3_WIDTH                     1
+#define AIPS_PACRH_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP3_SHIFT))&AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_WP3_MASK                      0x20000u
+#define AIPS_PACRH_WP3_SHIFT                     17
+#define AIPS_PACRH_WP3_WIDTH                     1
+#define AIPS_PACRH_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP3_SHIFT))&AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_SP3_MASK                      0x40000u
+#define AIPS_PACRH_SP3_SHIFT                     18
+#define AIPS_PACRH_SP3_WIDTH                     1
+#define AIPS_PACRH_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP3_SHIFT))&AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_TP2_MASK                      0x100000u
+#define AIPS_PACRH_TP2_SHIFT                     20
+#define AIPS_PACRH_TP2_WIDTH                     1
+#define AIPS_PACRH_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP2_SHIFT))&AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_WP2_MASK                      0x200000u
+#define AIPS_PACRH_WP2_SHIFT                     21
+#define AIPS_PACRH_WP2_WIDTH                     1
+#define AIPS_PACRH_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP2_SHIFT))&AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_SP2_MASK                      0x400000u
+#define AIPS_PACRH_SP2_SHIFT                     22
+#define AIPS_PACRH_SP2_WIDTH                     1
+#define AIPS_PACRH_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP2_SHIFT))&AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_TP1_MASK                      0x1000000u
+#define AIPS_PACRH_TP1_SHIFT                     24
+#define AIPS_PACRH_TP1_WIDTH                     1
+#define AIPS_PACRH_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP1_SHIFT))&AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_WP1_MASK                      0x2000000u
+#define AIPS_PACRH_WP1_SHIFT                     25
+#define AIPS_PACRH_WP1_WIDTH                     1
+#define AIPS_PACRH_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP1_SHIFT))&AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_SP1_MASK                      0x4000000u
+#define AIPS_PACRH_SP1_SHIFT                     26
+#define AIPS_PACRH_SP1_WIDTH                     1
+#define AIPS_PACRH_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP1_SHIFT))&AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_TP0_MASK                      0x10000000u
+#define AIPS_PACRH_TP0_SHIFT                     28
+#define AIPS_PACRH_TP0_WIDTH                     1
+#define AIPS_PACRH_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP0_SHIFT))&AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_WP0_MASK                      0x20000000u
+#define AIPS_PACRH_WP0_SHIFT                     29
+#define AIPS_PACRH_WP0_WIDTH                     1
+#define AIPS_PACRH_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP0_SHIFT))&AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_SP0_MASK                      0x40000000u
+#define AIPS_PACRH_SP0_SHIFT                     30
+#define AIPS_PACRH_SP0_WIDTH                     1
+#define AIPS_PACRH_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP0_SHIFT))&AIPS_PACRH_SP0_MASK)
+/* PACRI Bit Fields */
+#define AIPS_PACRI_TP7_MASK                      0x1u
+#define AIPS_PACRI_TP7_SHIFT                     0
+#define AIPS_PACRI_TP7_WIDTH                     1
+#define AIPS_PACRI_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP7_SHIFT))&AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_WP7_MASK                      0x2u
+#define AIPS_PACRI_WP7_SHIFT                     1
+#define AIPS_PACRI_WP7_WIDTH                     1
+#define AIPS_PACRI_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP7_SHIFT))&AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_SP7_MASK                      0x4u
+#define AIPS_PACRI_SP7_SHIFT                     2
+#define AIPS_PACRI_SP7_WIDTH                     1
+#define AIPS_PACRI_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP7_SHIFT))&AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_TP6_MASK                      0x10u
+#define AIPS_PACRI_TP6_SHIFT                     4
+#define AIPS_PACRI_TP6_WIDTH                     1
+#define AIPS_PACRI_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP6_SHIFT))&AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_WP6_MASK                      0x20u
+#define AIPS_PACRI_WP6_SHIFT                     5
+#define AIPS_PACRI_WP6_WIDTH                     1
+#define AIPS_PACRI_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP6_SHIFT))&AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_SP6_MASK                      0x40u
+#define AIPS_PACRI_SP6_SHIFT                     6
+#define AIPS_PACRI_SP6_WIDTH                     1
+#define AIPS_PACRI_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP6_SHIFT))&AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_TP5_MASK                      0x100u
+#define AIPS_PACRI_TP5_SHIFT                     8
+#define AIPS_PACRI_TP5_WIDTH                     1
+#define AIPS_PACRI_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP5_SHIFT))&AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_WP5_MASK                      0x200u
+#define AIPS_PACRI_WP5_SHIFT                     9
+#define AIPS_PACRI_WP5_WIDTH                     1
+#define AIPS_PACRI_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP5_SHIFT))&AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_SP5_MASK                      0x400u
+#define AIPS_PACRI_SP5_SHIFT                     10
+#define AIPS_PACRI_SP5_WIDTH                     1
+#define AIPS_PACRI_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP5_SHIFT))&AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_TP4_MASK                      0x1000u
+#define AIPS_PACRI_TP4_SHIFT                     12
+#define AIPS_PACRI_TP4_WIDTH                     1
+#define AIPS_PACRI_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP4_SHIFT))&AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_WP4_MASK                      0x2000u
+#define AIPS_PACRI_WP4_SHIFT                     13
+#define AIPS_PACRI_WP4_WIDTH                     1
+#define AIPS_PACRI_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP4_SHIFT))&AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_SP4_MASK                      0x4000u
+#define AIPS_PACRI_SP4_SHIFT                     14
+#define AIPS_PACRI_SP4_WIDTH                     1
+#define AIPS_PACRI_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP4_SHIFT))&AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_TP3_MASK                      0x10000u
+#define AIPS_PACRI_TP3_SHIFT                     16
+#define AIPS_PACRI_TP3_WIDTH                     1
+#define AIPS_PACRI_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP3_SHIFT))&AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_WP3_MASK                      0x20000u
+#define AIPS_PACRI_WP3_SHIFT                     17
+#define AIPS_PACRI_WP3_WIDTH                     1
+#define AIPS_PACRI_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP3_SHIFT))&AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_SP3_MASK                      0x40000u
+#define AIPS_PACRI_SP3_SHIFT                     18
+#define AIPS_PACRI_SP3_WIDTH                     1
+#define AIPS_PACRI_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP3_SHIFT))&AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_TP2_MASK                      0x100000u
+#define AIPS_PACRI_TP2_SHIFT                     20
+#define AIPS_PACRI_TP2_WIDTH                     1
+#define AIPS_PACRI_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP2_SHIFT))&AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_WP2_MASK                      0x200000u
+#define AIPS_PACRI_WP2_SHIFT                     21
+#define AIPS_PACRI_WP2_WIDTH                     1
+#define AIPS_PACRI_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP2_SHIFT))&AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_SP2_MASK                      0x400000u
+#define AIPS_PACRI_SP2_SHIFT                     22
+#define AIPS_PACRI_SP2_WIDTH                     1
+#define AIPS_PACRI_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP2_SHIFT))&AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_TP1_MASK                      0x1000000u
+#define AIPS_PACRI_TP1_SHIFT                     24
+#define AIPS_PACRI_TP1_WIDTH                     1
+#define AIPS_PACRI_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP1_SHIFT))&AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_WP1_MASK                      0x2000000u
+#define AIPS_PACRI_WP1_SHIFT                     25
+#define AIPS_PACRI_WP1_WIDTH                     1
+#define AIPS_PACRI_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP1_SHIFT))&AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_SP1_MASK                      0x4000000u
+#define AIPS_PACRI_SP1_SHIFT                     26
+#define AIPS_PACRI_SP1_WIDTH                     1
+#define AIPS_PACRI_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP1_SHIFT))&AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_TP0_MASK                      0x10000000u
+#define AIPS_PACRI_TP0_SHIFT                     28
+#define AIPS_PACRI_TP0_WIDTH                     1
+#define AIPS_PACRI_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP0_SHIFT))&AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_WP0_MASK                      0x20000000u
+#define AIPS_PACRI_WP0_SHIFT                     29
+#define AIPS_PACRI_WP0_WIDTH                     1
+#define AIPS_PACRI_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP0_SHIFT))&AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_SP0_MASK                      0x40000000u
+#define AIPS_PACRI_SP0_SHIFT                     30
+#define AIPS_PACRI_SP0_WIDTH                     1
+#define AIPS_PACRI_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP0_SHIFT))&AIPS_PACRI_SP0_MASK)
+/* PACRJ Bit Fields */
+#define AIPS_PACRJ_TP7_MASK                      0x1u
+#define AIPS_PACRJ_TP7_SHIFT                     0
+#define AIPS_PACRJ_TP7_WIDTH                     1
+#define AIPS_PACRJ_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP7_SHIFT))&AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_WP7_MASK                      0x2u
+#define AIPS_PACRJ_WP7_SHIFT                     1
+#define AIPS_PACRJ_WP7_WIDTH                     1
+#define AIPS_PACRJ_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP7_SHIFT))&AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_SP7_MASK                      0x4u
+#define AIPS_PACRJ_SP7_SHIFT                     2
+#define AIPS_PACRJ_SP7_WIDTH                     1
+#define AIPS_PACRJ_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP7_SHIFT))&AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_TP6_MASK                      0x10u
+#define AIPS_PACRJ_TP6_SHIFT                     4
+#define AIPS_PACRJ_TP6_WIDTH                     1
+#define AIPS_PACRJ_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP6_SHIFT))&AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_WP6_MASK                      0x20u
+#define AIPS_PACRJ_WP6_SHIFT                     5
+#define AIPS_PACRJ_WP6_WIDTH                     1
+#define AIPS_PACRJ_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP6_SHIFT))&AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_SP6_MASK                      0x40u
+#define AIPS_PACRJ_SP6_SHIFT                     6
+#define AIPS_PACRJ_SP6_WIDTH                     1
+#define AIPS_PACRJ_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP6_SHIFT))&AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_TP5_MASK                      0x100u
+#define AIPS_PACRJ_TP5_SHIFT                     8
+#define AIPS_PACRJ_TP5_WIDTH                     1
+#define AIPS_PACRJ_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP5_SHIFT))&AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_WP5_MASK                      0x200u
+#define AIPS_PACRJ_WP5_SHIFT                     9
+#define AIPS_PACRJ_WP5_WIDTH                     1
+#define AIPS_PACRJ_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP5_SHIFT))&AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_SP5_MASK                      0x400u
+#define AIPS_PACRJ_SP5_SHIFT                     10
+#define AIPS_PACRJ_SP5_WIDTH                     1
+#define AIPS_PACRJ_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP5_SHIFT))&AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_TP4_MASK                      0x1000u
+#define AIPS_PACRJ_TP4_SHIFT                     12
+#define AIPS_PACRJ_TP4_WIDTH                     1
+#define AIPS_PACRJ_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP4_SHIFT))&AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_WP4_MASK                      0x2000u
+#define AIPS_PACRJ_WP4_SHIFT                     13
+#define AIPS_PACRJ_WP4_WIDTH                     1
+#define AIPS_PACRJ_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP4_SHIFT))&AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_SP4_MASK                      0x4000u
+#define AIPS_PACRJ_SP4_SHIFT                     14
+#define AIPS_PACRJ_SP4_WIDTH                     1
+#define AIPS_PACRJ_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP4_SHIFT))&AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_TP3_MASK                      0x10000u
+#define AIPS_PACRJ_TP3_SHIFT                     16
+#define AIPS_PACRJ_TP3_WIDTH                     1
+#define AIPS_PACRJ_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP3_SHIFT))&AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_WP3_MASK                      0x20000u
+#define AIPS_PACRJ_WP3_SHIFT                     17
+#define AIPS_PACRJ_WP3_WIDTH                     1
+#define AIPS_PACRJ_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP3_SHIFT))&AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_SP3_MASK                      0x40000u
+#define AIPS_PACRJ_SP3_SHIFT                     18
+#define AIPS_PACRJ_SP3_WIDTH                     1
+#define AIPS_PACRJ_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP3_SHIFT))&AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_TP2_MASK                      0x100000u
+#define AIPS_PACRJ_TP2_SHIFT                     20
+#define AIPS_PACRJ_TP2_WIDTH                     1
+#define AIPS_PACRJ_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP2_SHIFT))&AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_WP2_MASK                      0x200000u
+#define AIPS_PACRJ_WP2_SHIFT                     21
+#define AIPS_PACRJ_WP2_WIDTH                     1
+#define AIPS_PACRJ_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP2_SHIFT))&AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_SP2_MASK                      0x400000u
+#define AIPS_PACRJ_SP2_SHIFT                     22
+#define AIPS_PACRJ_SP2_WIDTH                     1
+#define AIPS_PACRJ_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP2_SHIFT))&AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_TP1_MASK                      0x1000000u
+#define AIPS_PACRJ_TP1_SHIFT                     24
+#define AIPS_PACRJ_TP1_WIDTH                     1
+#define AIPS_PACRJ_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP1_SHIFT))&AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_WP1_MASK                      0x2000000u
+#define AIPS_PACRJ_WP1_SHIFT                     25
+#define AIPS_PACRJ_WP1_WIDTH                     1
+#define AIPS_PACRJ_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP1_SHIFT))&AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_SP1_MASK                      0x4000000u
+#define AIPS_PACRJ_SP1_SHIFT                     26
+#define AIPS_PACRJ_SP1_WIDTH                     1
+#define AIPS_PACRJ_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP1_SHIFT))&AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_TP0_MASK                      0x10000000u
+#define AIPS_PACRJ_TP0_SHIFT                     28
+#define AIPS_PACRJ_TP0_WIDTH                     1
+#define AIPS_PACRJ_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP0_SHIFT))&AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_WP0_MASK                      0x20000000u
+#define AIPS_PACRJ_WP0_SHIFT                     29
+#define AIPS_PACRJ_WP0_WIDTH                     1
+#define AIPS_PACRJ_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP0_SHIFT))&AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_SP0_MASK                      0x40000000u
+#define AIPS_PACRJ_SP0_SHIFT                     30
+#define AIPS_PACRJ_SP0_WIDTH                     1
+#define AIPS_PACRJ_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP0_SHIFT))&AIPS_PACRJ_SP0_MASK)
+/* PACRK Bit Fields */
+#define AIPS_PACRK_TP7_MASK                      0x1u
+#define AIPS_PACRK_TP7_SHIFT                     0
+#define AIPS_PACRK_TP7_WIDTH                     1
+#define AIPS_PACRK_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP7_SHIFT))&AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_WP7_MASK                      0x2u
+#define AIPS_PACRK_WP7_SHIFT                     1
+#define AIPS_PACRK_WP7_WIDTH                     1
+#define AIPS_PACRK_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP7_SHIFT))&AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_SP7_MASK                      0x4u
+#define AIPS_PACRK_SP7_SHIFT                     2
+#define AIPS_PACRK_SP7_WIDTH                     1
+#define AIPS_PACRK_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP7_SHIFT))&AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_TP6_MASK                      0x10u
+#define AIPS_PACRK_TP6_SHIFT                     4
+#define AIPS_PACRK_TP6_WIDTH                     1
+#define AIPS_PACRK_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP6_SHIFT))&AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_WP6_MASK                      0x20u
+#define AIPS_PACRK_WP6_SHIFT                     5
+#define AIPS_PACRK_WP6_WIDTH                     1
+#define AIPS_PACRK_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP6_SHIFT))&AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_SP6_MASK                      0x40u
+#define AIPS_PACRK_SP6_SHIFT                     6
+#define AIPS_PACRK_SP6_WIDTH                     1
+#define AIPS_PACRK_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP6_SHIFT))&AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_TP5_MASK                      0x100u
+#define AIPS_PACRK_TP5_SHIFT                     8
+#define AIPS_PACRK_TP5_WIDTH                     1
+#define AIPS_PACRK_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP5_SHIFT))&AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_WP5_MASK                      0x200u
+#define AIPS_PACRK_WP5_SHIFT                     9
+#define AIPS_PACRK_WP5_WIDTH                     1
+#define AIPS_PACRK_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP5_SHIFT))&AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_SP5_MASK                      0x400u
+#define AIPS_PACRK_SP5_SHIFT                     10
+#define AIPS_PACRK_SP5_WIDTH                     1
+#define AIPS_PACRK_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP5_SHIFT))&AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_TP4_MASK                      0x1000u
+#define AIPS_PACRK_TP4_SHIFT                     12
+#define AIPS_PACRK_TP4_WIDTH                     1
+#define AIPS_PACRK_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP4_SHIFT))&AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_WP4_MASK                      0x2000u
+#define AIPS_PACRK_WP4_SHIFT                     13
+#define AIPS_PACRK_WP4_WIDTH                     1
+#define AIPS_PACRK_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP4_SHIFT))&AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_SP4_MASK                      0x4000u
+#define AIPS_PACRK_SP4_SHIFT                     14
+#define AIPS_PACRK_SP4_WIDTH                     1
+#define AIPS_PACRK_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP4_SHIFT))&AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_TP3_MASK                      0x10000u
+#define AIPS_PACRK_TP3_SHIFT                     16
+#define AIPS_PACRK_TP3_WIDTH                     1
+#define AIPS_PACRK_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP3_SHIFT))&AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_WP3_MASK                      0x20000u
+#define AIPS_PACRK_WP3_SHIFT                     17
+#define AIPS_PACRK_WP3_WIDTH                     1
+#define AIPS_PACRK_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP3_SHIFT))&AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_SP3_MASK                      0x40000u
+#define AIPS_PACRK_SP3_SHIFT                     18
+#define AIPS_PACRK_SP3_WIDTH                     1
+#define AIPS_PACRK_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP3_SHIFT))&AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_TP2_MASK                      0x100000u
+#define AIPS_PACRK_TP2_SHIFT                     20
+#define AIPS_PACRK_TP2_WIDTH                     1
+#define AIPS_PACRK_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP2_SHIFT))&AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_WP2_MASK                      0x200000u
+#define AIPS_PACRK_WP2_SHIFT                     21
+#define AIPS_PACRK_WP2_WIDTH                     1
+#define AIPS_PACRK_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP2_SHIFT))&AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_SP2_MASK                      0x400000u
+#define AIPS_PACRK_SP2_SHIFT                     22
+#define AIPS_PACRK_SP2_WIDTH                     1
+#define AIPS_PACRK_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP2_SHIFT))&AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_TP1_MASK                      0x1000000u
+#define AIPS_PACRK_TP1_SHIFT                     24
+#define AIPS_PACRK_TP1_WIDTH                     1
+#define AIPS_PACRK_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP1_SHIFT))&AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_WP1_MASK                      0x2000000u
+#define AIPS_PACRK_WP1_SHIFT                     25
+#define AIPS_PACRK_WP1_WIDTH                     1
+#define AIPS_PACRK_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP1_SHIFT))&AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_SP1_MASK                      0x4000000u
+#define AIPS_PACRK_SP1_SHIFT                     26
+#define AIPS_PACRK_SP1_WIDTH                     1
+#define AIPS_PACRK_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP1_SHIFT))&AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_TP0_MASK                      0x10000000u
+#define AIPS_PACRK_TP0_SHIFT                     28
+#define AIPS_PACRK_TP0_WIDTH                     1
+#define AIPS_PACRK_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP0_SHIFT))&AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_WP0_MASK                      0x20000000u
+#define AIPS_PACRK_WP0_SHIFT                     29
+#define AIPS_PACRK_WP0_WIDTH                     1
+#define AIPS_PACRK_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP0_SHIFT))&AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_SP0_MASK                      0x40000000u
+#define AIPS_PACRK_SP0_SHIFT                     30
+#define AIPS_PACRK_SP0_WIDTH                     1
+#define AIPS_PACRK_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP0_SHIFT))&AIPS_PACRK_SP0_MASK)
+/* PACRL Bit Fields */
+#define AIPS_PACRL_TP7_MASK                      0x1u
+#define AIPS_PACRL_TP7_SHIFT                     0
+#define AIPS_PACRL_TP7_WIDTH                     1
+#define AIPS_PACRL_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP7_SHIFT))&AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_WP7_MASK                      0x2u
+#define AIPS_PACRL_WP7_SHIFT                     1
+#define AIPS_PACRL_WP7_WIDTH                     1
+#define AIPS_PACRL_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP7_SHIFT))&AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_SP7_MASK                      0x4u
+#define AIPS_PACRL_SP7_SHIFT                     2
+#define AIPS_PACRL_SP7_WIDTH                     1
+#define AIPS_PACRL_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP7_SHIFT))&AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_TP6_MASK                      0x10u
+#define AIPS_PACRL_TP6_SHIFT                     4
+#define AIPS_PACRL_TP6_WIDTH                     1
+#define AIPS_PACRL_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP6_SHIFT))&AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_WP6_MASK                      0x20u
+#define AIPS_PACRL_WP6_SHIFT                     5
+#define AIPS_PACRL_WP6_WIDTH                     1
+#define AIPS_PACRL_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP6_SHIFT))&AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_SP6_MASK                      0x40u
+#define AIPS_PACRL_SP6_SHIFT                     6
+#define AIPS_PACRL_SP6_WIDTH                     1
+#define AIPS_PACRL_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP6_SHIFT))&AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_TP5_MASK                      0x100u
+#define AIPS_PACRL_TP5_SHIFT                     8
+#define AIPS_PACRL_TP5_WIDTH                     1
+#define AIPS_PACRL_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP5_SHIFT))&AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_WP5_MASK                      0x200u
+#define AIPS_PACRL_WP5_SHIFT                     9
+#define AIPS_PACRL_WP5_WIDTH                     1
+#define AIPS_PACRL_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP5_SHIFT))&AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_SP5_MASK                      0x400u
+#define AIPS_PACRL_SP5_SHIFT                     10
+#define AIPS_PACRL_SP5_WIDTH                     1
+#define AIPS_PACRL_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP5_SHIFT))&AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_TP4_MASK                      0x1000u
+#define AIPS_PACRL_TP4_SHIFT                     12
+#define AIPS_PACRL_TP4_WIDTH                     1
+#define AIPS_PACRL_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP4_SHIFT))&AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_WP4_MASK                      0x2000u
+#define AIPS_PACRL_WP4_SHIFT                     13
+#define AIPS_PACRL_WP4_WIDTH                     1
+#define AIPS_PACRL_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP4_SHIFT))&AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_SP4_MASK                      0x4000u
+#define AIPS_PACRL_SP4_SHIFT                     14
+#define AIPS_PACRL_SP4_WIDTH                     1
+#define AIPS_PACRL_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP4_SHIFT))&AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_TP3_MASK                      0x10000u
+#define AIPS_PACRL_TP3_SHIFT                     16
+#define AIPS_PACRL_TP3_WIDTH                     1
+#define AIPS_PACRL_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP3_SHIFT))&AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_WP3_MASK                      0x20000u
+#define AIPS_PACRL_WP3_SHIFT                     17
+#define AIPS_PACRL_WP3_WIDTH                     1
+#define AIPS_PACRL_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP3_SHIFT))&AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_SP3_MASK                      0x40000u
+#define AIPS_PACRL_SP3_SHIFT                     18
+#define AIPS_PACRL_SP3_WIDTH                     1
+#define AIPS_PACRL_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP3_SHIFT))&AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_TP2_MASK                      0x100000u
+#define AIPS_PACRL_TP2_SHIFT                     20
+#define AIPS_PACRL_TP2_WIDTH                     1
+#define AIPS_PACRL_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP2_SHIFT))&AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_WP2_MASK                      0x200000u
+#define AIPS_PACRL_WP2_SHIFT                     21
+#define AIPS_PACRL_WP2_WIDTH                     1
+#define AIPS_PACRL_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP2_SHIFT))&AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_SP2_MASK                      0x400000u
+#define AIPS_PACRL_SP2_SHIFT                     22
+#define AIPS_PACRL_SP2_WIDTH                     1
+#define AIPS_PACRL_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP2_SHIFT))&AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_TP1_MASK                      0x1000000u
+#define AIPS_PACRL_TP1_SHIFT                     24
+#define AIPS_PACRL_TP1_WIDTH                     1
+#define AIPS_PACRL_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP1_SHIFT))&AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_WP1_MASK                      0x2000000u
+#define AIPS_PACRL_WP1_SHIFT                     25
+#define AIPS_PACRL_WP1_WIDTH                     1
+#define AIPS_PACRL_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP1_SHIFT))&AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_SP1_MASK                      0x4000000u
+#define AIPS_PACRL_SP1_SHIFT                     26
+#define AIPS_PACRL_SP1_WIDTH                     1
+#define AIPS_PACRL_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP1_SHIFT))&AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_TP0_MASK                      0x10000000u
+#define AIPS_PACRL_TP0_SHIFT                     28
+#define AIPS_PACRL_TP0_WIDTH                     1
+#define AIPS_PACRL_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP0_SHIFT))&AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_WP0_MASK                      0x20000000u
+#define AIPS_PACRL_WP0_SHIFT                     29
+#define AIPS_PACRL_WP0_WIDTH                     1
+#define AIPS_PACRL_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP0_SHIFT))&AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_SP0_MASK                      0x40000000u
+#define AIPS_PACRL_SP0_SHIFT                     30
+#define AIPS_PACRL_SP0_WIDTH                     1
+#define AIPS_PACRL_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP0_SHIFT))&AIPS_PACRL_SP0_MASK)
+/* PACRM Bit Fields */
+#define AIPS_PACRM_TP7_MASK                      0x1u
+#define AIPS_PACRM_TP7_SHIFT                     0
+#define AIPS_PACRM_TP7_WIDTH                     1
+#define AIPS_PACRM_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP7_SHIFT))&AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_WP7_MASK                      0x2u
+#define AIPS_PACRM_WP7_SHIFT                     1
+#define AIPS_PACRM_WP7_WIDTH                     1
+#define AIPS_PACRM_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP7_SHIFT))&AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_SP7_MASK                      0x4u
+#define AIPS_PACRM_SP7_SHIFT                     2
+#define AIPS_PACRM_SP7_WIDTH                     1
+#define AIPS_PACRM_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP7_SHIFT))&AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_TP6_MASK                      0x10u
+#define AIPS_PACRM_TP6_SHIFT                     4
+#define AIPS_PACRM_TP6_WIDTH                     1
+#define AIPS_PACRM_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP6_SHIFT))&AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_WP6_MASK                      0x20u
+#define AIPS_PACRM_WP6_SHIFT                     5
+#define AIPS_PACRM_WP6_WIDTH                     1
+#define AIPS_PACRM_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP6_SHIFT))&AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_SP6_MASK                      0x40u
+#define AIPS_PACRM_SP6_SHIFT                     6
+#define AIPS_PACRM_SP6_WIDTH                     1
+#define AIPS_PACRM_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP6_SHIFT))&AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_TP5_MASK                      0x100u
+#define AIPS_PACRM_TP5_SHIFT                     8
+#define AIPS_PACRM_TP5_WIDTH                     1
+#define AIPS_PACRM_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP5_SHIFT))&AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_WP5_MASK                      0x200u
+#define AIPS_PACRM_WP5_SHIFT                     9
+#define AIPS_PACRM_WP5_WIDTH                     1
+#define AIPS_PACRM_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP5_SHIFT))&AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_SP5_MASK                      0x400u
+#define AIPS_PACRM_SP5_SHIFT                     10
+#define AIPS_PACRM_SP5_WIDTH                     1
+#define AIPS_PACRM_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP5_SHIFT))&AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_TP4_MASK                      0x1000u
+#define AIPS_PACRM_TP4_SHIFT                     12
+#define AIPS_PACRM_TP4_WIDTH                     1
+#define AIPS_PACRM_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP4_SHIFT))&AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_WP4_MASK                      0x2000u
+#define AIPS_PACRM_WP4_SHIFT                     13
+#define AIPS_PACRM_WP4_WIDTH                     1
+#define AIPS_PACRM_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP4_SHIFT))&AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_SP4_MASK                      0x4000u
+#define AIPS_PACRM_SP4_SHIFT                     14
+#define AIPS_PACRM_SP4_WIDTH                     1
+#define AIPS_PACRM_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP4_SHIFT))&AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_TP3_MASK                      0x10000u
+#define AIPS_PACRM_TP3_SHIFT                     16
+#define AIPS_PACRM_TP3_WIDTH                     1
+#define AIPS_PACRM_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP3_SHIFT))&AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_WP3_MASK                      0x20000u
+#define AIPS_PACRM_WP3_SHIFT                     17
+#define AIPS_PACRM_WP3_WIDTH                     1
+#define AIPS_PACRM_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP3_SHIFT))&AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_SP3_MASK                      0x40000u
+#define AIPS_PACRM_SP3_SHIFT                     18
+#define AIPS_PACRM_SP3_WIDTH                     1
+#define AIPS_PACRM_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP3_SHIFT))&AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_TP2_MASK                      0x100000u
+#define AIPS_PACRM_TP2_SHIFT                     20
+#define AIPS_PACRM_TP2_WIDTH                     1
+#define AIPS_PACRM_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP2_SHIFT))&AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_WP2_MASK                      0x200000u
+#define AIPS_PACRM_WP2_SHIFT                     21
+#define AIPS_PACRM_WP2_WIDTH                     1
+#define AIPS_PACRM_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP2_SHIFT))&AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_SP2_MASK                      0x400000u
+#define AIPS_PACRM_SP2_SHIFT                     22
+#define AIPS_PACRM_SP2_WIDTH                     1
+#define AIPS_PACRM_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP2_SHIFT))&AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_TP1_MASK                      0x1000000u
+#define AIPS_PACRM_TP1_SHIFT                     24
+#define AIPS_PACRM_TP1_WIDTH                     1
+#define AIPS_PACRM_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP1_SHIFT))&AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_WP1_MASK                      0x2000000u
+#define AIPS_PACRM_WP1_SHIFT                     25
+#define AIPS_PACRM_WP1_WIDTH                     1
+#define AIPS_PACRM_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP1_SHIFT))&AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_SP1_MASK                      0x4000000u
+#define AIPS_PACRM_SP1_SHIFT                     26
+#define AIPS_PACRM_SP1_WIDTH                     1
+#define AIPS_PACRM_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP1_SHIFT))&AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_TP0_MASK                      0x10000000u
+#define AIPS_PACRM_TP0_SHIFT                     28
+#define AIPS_PACRM_TP0_WIDTH                     1
+#define AIPS_PACRM_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP0_SHIFT))&AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_WP0_MASK                      0x20000000u
+#define AIPS_PACRM_WP0_SHIFT                     29
+#define AIPS_PACRM_WP0_WIDTH                     1
+#define AIPS_PACRM_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP0_SHIFT))&AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_SP0_MASK                      0x40000000u
+#define AIPS_PACRM_SP0_SHIFT                     30
+#define AIPS_PACRM_SP0_WIDTH                     1
+#define AIPS_PACRM_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP0_SHIFT))&AIPS_PACRM_SP0_MASK)
+/* PACRN Bit Fields */
+#define AIPS_PACRN_TP7_MASK                      0x1u
+#define AIPS_PACRN_TP7_SHIFT                     0
+#define AIPS_PACRN_TP7_WIDTH                     1
+#define AIPS_PACRN_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP7_SHIFT))&AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_WP7_MASK                      0x2u
+#define AIPS_PACRN_WP7_SHIFT                     1
+#define AIPS_PACRN_WP7_WIDTH                     1
+#define AIPS_PACRN_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP7_SHIFT))&AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_SP7_MASK                      0x4u
+#define AIPS_PACRN_SP7_SHIFT                     2
+#define AIPS_PACRN_SP7_WIDTH                     1
+#define AIPS_PACRN_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP7_SHIFT))&AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_TP6_MASK                      0x10u
+#define AIPS_PACRN_TP6_SHIFT                     4
+#define AIPS_PACRN_TP6_WIDTH                     1
+#define AIPS_PACRN_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP6_SHIFT))&AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_WP6_MASK                      0x20u
+#define AIPS_PACRN_WP6_SHIFT                     5
+#define AIPS_PACRN_WP6_WIDTH                     1
+#define AIPS_PACRN_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP6_SHIFT))&AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_SP6_MASK                      0x40u
+#define AIPS_PACRN_SP6_SHIFT                     6
+#define AIPS_PACRN_SP6_WIDTH                     1
+#define AIPS_PACRN_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP6_SHIFT))&AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_TP5_MASK                      0x100u
+#define AIPS_PACRN_TP5_SHIFT                     8
+#define AIPS_PACRN_TP5_WIDTH                     1
+#define AIPS_PACRN_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP5_SHIFT))&AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_WP5_MASK                      0x200u
+#define AIPS_PACRN_WP5_SHIFT                     9
+#define AIPS_PACRN_WP5_WIDTH                     1
+#define AIPS_PACRN_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP5_SHIFT))&AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_SP5_MASK                      0x400u
+#define AIPS_PACRN_SP5_SHIFT                     10
+#define AIPS_PACRN_SP5_WIDTH                     1
+#define AIPS_PACRN_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP5_SHIFT))&AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_TP4_MASK                      0x1000u
+#define AIPS_PACRN_TP4_SHIFT                     12
+#define AIPS_PACRN_TP4_WIDTH                     1
+#define AIPS_PACRN_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP4_SHIFT))&AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_WP4_MASK                      0x2000u
+#define AIPS_PACRN_WP4_SHIFT                     13
+#define AIPS_PACRN_WP4_WIDTH                     1
+#define AIPS_PACRN_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP4_SHIFT))&AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_SP4_MASK                      0x4000u
+#define AIPS_PACRN_SP4_SHIFT                     14
+#define AIPS_PACRN_SP4_WIDTH                     1
+#define AIPS_PACRN_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP4_SHIFT))&AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_TP3_MASK                      0x10000u
+#define AIPS_PACRN_TP3_SHIFT                     16
+#define AIPS_PACRN_TP3_WIDTH                     1
+#define AIPS_PACRN_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP3_SHIFT))&AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_WP3_MASK                      0x20000u
+#define AIPS_PACRN_WP3_SHIFT                     17
+#define AIPS_PACRN_WP3_WIDTH                     1
+#define AIPS_PACRN_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP3_SHIFT))&AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_SP3_MASK                      0x40000u
+#define AIPS_PACRN_SP3_SHIFT                     18
+#define AIPS_PACRN_SP3_WIDTH                     1
+#define AIPS_PACRN_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP3_SHIFT))&AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_TP2_MASK                      0x100000u
+#define AIPS_PACRN_TP2_SHIFT                     20
+#define AIPS_PACRN_TP2_WIDTH                     1
+#define AIPS_PACRN_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP2_SHIFT))&AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_WP2_MASK                      0x200000u
+#define AIPS_PACRN_WP2_SHIFT                     21
+#define AIPS_PACRN_WP2_WIDTH                     1
+#define AIPS_PACRN_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP2_SHIFT))&AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_SP2_MASK                      0x400000u
+#define AIPS_PACRN_SP2_SHIFT                     22
+#define AIPS_PACRN_SP2_WIDTH                     1
+#define AIPS_PACRN_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP2_SHIFT))&AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_TP1_MASK                      0x1000000u
+#define AIPS_PACRN_TP1_SHIFT                     24
+#define AIPS_PACRN_TP1_WIDTH                     1
+#define AIPS_PACRN_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP1_SHIFT))&AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_WP1_MASK                      0x2000000u
+#define AIPS_PACRN_WP1_SHIFT                     25
+#define AIPS_PACRN_WP1_WIDTH                     1
+#define AIPS_PACRN_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP1_SHIFT))&AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_SP1_MASK                      0x4000000u
+#define AIPS_PACRN_SP1_SHIFT                     26
+#define AIPS_PACRN_SP1_WIDTH                     1
+#define AIPS_PACRN_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP1_SHIFT))&AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_TP0_MASK                      0x10000000u
+#define AIPS_PACRN_TP0_SHIFT                     28
+#define AIPS_PACRN_TP0_WIDTH                     1
+#define AIPS_PACRN_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP0_SHIFT))&AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_WP0_MASK                      0x20000000u
+#define AIPS_PACRN_WP0_SHIFT                     29
+#define AIPS_PACRN_WP0_WIDTH                     1
+#define AIPS_PACRN_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP0_SHIFT))&AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_SP0_MASK                      0x40000000u
+#define AIPS_PACRN_SP0_SHIFT                     30
+#define AIPS_PACRN_SP0_WIDTH                     1
+#define AIPS_PACRN_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP0_SHIFT))&AIPS_PACRN_SP0_MASK)
+/* PACRO Bit Fields */
+#define AIPS_PACRO_TP7_MASK                      0x1u
+#define AIPS_PACRO_TP7_SHIFT                     0
+#define AIPS_PACRO_TP7_WIDTH                     1
+#define AIPS_PACRO_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP7_SHIFT))&AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_WP7_MASK                      0x2u
+#define AIPS_PACRO_WP7_SHIFT                     1
+#define AIPS_PACRO_WP7_WIDTH                     1
+#define AIPS_PACRO_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP7_SHIFT))&AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_SP7_MASK                      0x4u
+#define AIPS_PACRO_SP7_SHIFT                     2
+#define AIPS_PACRO_SP7_WIDTH                     1
+#define AIPS_PACRO_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP7_SHIFT))&AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_TP6_MASK                      0x10u
+#define AIPS_PACRO_TP6_SHIFT                     4
+#define AIPS_PACRO_TP6_WIDTH                     1
+#define AIPS_PACRO_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP6_SHIFT))&AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_WP6_MASK                      0x20u
+#define AIPS_PACRO_WP6_SHIFT                     5
+#define AIPS_PACRO_WP6_WIDTH                     1
+#define AIPS_PACRO_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP6_SHIFT))&AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_SP6_MASK                      0x40u
+#define AIPS_PACRO_SP6_SHIFT                     6
+#define AIPS_PACRO_SP6_WIDTH                     1
+#define AIPS_PACRO_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP6_SHIFT))&AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_TP5_MASK                      0x100u
+#define AIPS_PACRO_TP5_SHIFT                     8
+#define AIPS_PACRO_TP5_WIDTH                     1
+#define AIPS_PACRO_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP5_SHIFT))&AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_WP5_MASK                      0x200u
+#define AIPS_PACRO_WP5_SHIFT                     9
+#define AIPS_PACRO_WP5_WIDTH                     1
+#define AIPS_PACRO_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP5_SHIFT))&AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_SP5_MASK                      0x400u
+#define AIPS_PACRO_SP5_SHIFT                     10
+#define AIPS_PACRO_SP5_WIDTH                     1
+#define AIPS_PACRO_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP5_SHIFT))&AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_TP4_MASK                      0x1000u
+#define AIPS_PACRO_TP4_SHIFT                     12
+#define AIPS_PACRO_TP4_WIDTH                     1
+#define AIPS_PACRO_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP4_SHIFT))&AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_WP4_MASK                      0x2000u
+#define AIPS_PACRO_WP4_SHIFT                     13
+#define AIPS_PACRO_WP4_WIDTH                     1
+#define AIPS_PACRO_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP4_SHIFT))&AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_SP4_MASK                      0x4000u
+#define AIPS_PACRO_SP4_SHIFT                     14
+#define AIPS_PACRO_SP4_WIDTH                     1
+#define AIPS_PACRO_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP4_SHIFT))&AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_TP3_MASK                      0x10000u
+#define AIPS_PACRO_TP3_SHIFT                     16
+#define AIPS_PACRO_TP3_WIDTH                     1
+#define AIPS_PACRO_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP3_SHIFT))&AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_WP3_MASK                      0x20000u
+#define AIPS_PACRO_WP3_SHIFT                     17
+#define AIPS_PACRO_WP3_WIDTH                     1
+#define AIPS_PACRO_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP3_SHIFT))&AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_SP3_MASK                      0x40000u
+#define AIPS_PACRO_SP3_SHIFT                     18
+#define AIPS_PACRO_SP3_WIDTH                     1
+#define AIPS_PACRO_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP3_SHIFT))&AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_TP2_MASK                      0x100000u
+#define AIPS_PACRO_TP2_SHIFT                     20
+#define AIPS_PACRO_TP2_WIDTH                     1
+#define AIPS_PACRO_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP2_SHIFT))&AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_WP2_MASK                      0x200000u
+#define AIPS_PACRO_WP2_SHIFT                     21
+#define AIPS_PACRO_WP2_WIDTH                     1
+#define AIPS_PACRO_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP2_SHIFT))&AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_SP2_MASK                      0x400000u
+#define AIPS_PACRO_SP2_SHIFT                     22
+#define AIPS_PACRO_SP2_WIDTH                     1
+#define AIPS_PACRO_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP2_SHIFT))&AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_TP1_MASK                      0x1000000u
+#define AIPS_PACRO_TP1_SHIFT                     24
+#define AIPS_PACRO_TP1_WIDTH                     1
+#define AIPS_PACRO_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP1_SHIFT))&AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_WP1_MASK                      0x2000000u
+#define AIPS_PACRO_WP1_SHIFT                     25
+#define AIPS_PACRO_WP1_WIDTH                     1
+#define AIPS_PACRO_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP1_SHIFT))&AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_SP1_MASK                      0x4000000u
+#define AIPS_PACRO_SP1_SHIFT                     26
+#define AIPS_PACRO_SP1_WIDTH                     1
+#define AIPS_PACRO_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP1_SHIFT))&AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_TP0_MASK                      0x10000000u
+#define AIPS_PACRO_TP0_SHIFT                     28
+#define AIPS_PACRO_TP0_WIDTH                     1
+#define AIPS_PACRO_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP0_SHIFT))&AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_WP0_MASK                      0x20000000u
+#define AIPS_PACRO_WP0_SHIFT                     29
+#define AIPS_PACRO_WP0_WIDTH                     1
+#define AIPS_PACRO_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP0_SHIFT))&AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_SP0_MASK                      0x40000000u
+#define AIPS_PACRO_SP0_SHIFT                     30
+#define AIPS_PACRO_SP0_WIDTH                     1
+#define AIPS_PACRO_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP0_SHIFT))&AIPS_PACRO_SP0_MASK)
+/* PACRP Bit Fields */
+#define AIPS_PACRP_TP7_MASK                      0x1u
+#define AIPS_PACRP_TP7_SHIFT                     0
+#define AIPS_PACRP_TP7_WIDTH                     1
+#define AIPS_PACRP_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP7_SHIFT))&AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_WP7_MASK                      0x2u
+#define AIPS_PACRP_WP7_SHIFT                     1
+#define AIPS_PACRP_WP7_WIDTH                     1
+#define AIPS_PACRP_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP7_SHIFT))&AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_SP7_MASK                      0x4u
+#define AIPS_PACRP_SP7_SHIFT                     2
+#define AIPS_PACRP_SP7_WIDTH                     1
+#define AIPS_PACRP_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP7_SHIFT))&AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_TP6_MASK                      0x10u
+#define AIPS_PACRP_TP6_SHIFT                     4
+#define AIPS_PACRP_TP6_WIDTH                     1
+#define AIPS_PACRP_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP6_SHIFT))&AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_WP6_MASK                      0x20u
+#define AIPS_PACRP_WP6_SHIFT                     5
+#define AIPS_PACRP_WP6_WIDTH                     1
+#define AIPS_PACRP_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP6_SHIFT))&AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_SP6_MASK                      0x40u
+#define AIPS_PACRP_SP6_SHIFT                     6
+#define AIPS_PACRP_SP6_WIDTH                     1
+#define AIPS_PACRP_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP6_SHIFT))&AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_TP5_MASK                      0x100u
+#define AIPS_PACRP_TP5_SHIFT                     8
+#define AIPS_PACRP_TP5_WIDTH                     1
+#define AIPS_PACRP_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP5_SHIFT))&AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_WP5_MASK                      0x200u
+#define AIPS_PACRP_WP5_SHIFT                     9
+#define AIPS_PACRP_WP5_WIDTH                     1
+#define AIPS_PACRP_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP5_SHIFT))&AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_SP5_MASK                      0x400u
+#define AIPS_PACRP_SP5_SHIFT                     10
+#define AIPS_PACRP_SP5_WIDTH                     1
+#define AIPS_PACRP_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP5_SHIFT))&AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_TP4_MASK                      0x1000u
+#define AIPS_PACRP_TP4_SHIFT                     12
+#define AIPS_PACRP_TP4_WIDTH                     1
+#define AIPS_PACRP_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP4_SHIFT))&AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_WP4_MASK                      0x2000u
+#define AIPS_PACRP_WP4_SHIFT                     13
+#define AIPS_PACRP_WP4_WIDTH                     1
+#define AIPS_PACRP_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP4_SHIFT))&AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_SP4_MASK                      0x4000u
+#define AIPS_PACRP_SP4_SHIFT                     14
+#define AIPS_PACRP_SP4_WIDTH                     1
+#define AIPS_PACRP_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP4_SHIFT))&AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_TP3_MASK                      0x10000u
+#define AIPS_PACRP_TP3_SHIFT                     16
+#define AIPS_PACRP_TP3_WIDTH                     1
+#define AIPS_PACRP_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP3_SHIFT))&AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_WP3_MASK                      0x20000u
+#define AIPS_PACRP_WP3_SHIFT                     17
+#define AIPS_PACRP_WP3_WIDTH                     1
+#define AIPS_PACRP_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP3_SHIFT))&AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_SP3_MASK                      0x40000u
+#define AIPS_PACRP_SP3_SHIFT                     18
+#define AIPS_PACRP_SP3_WIDTH                     1
+#define AIPS_PACRP_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP3_SHIFT))&AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_TP2_MASK                      0x100000u
+#define AIPS_PACRP_TP2_SHIFT                     20
+#define AIPS_PACRP_TP2_WIDTH                     1
+#define AIPS_PACRP_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP2_SHIFT))&AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_WP2_MASK                      0x200000u
+#define AIPS_PACRP_WP2_SHIFT                     21
+#define AIPS_PACRP_WP2_WIDTH                     1
+#define AIPS_PACRP_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP2_SHIFT))&AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_SP2_MASK                      0x400000u
+#define AIPS_PACRP_SP2_SHIFT                     22
+#define AIPS_PACRP_SP2_WIDTH                     1
+#define AIPS_PACRP_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP2_SHIFT))&AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_TP1_MASK                      0x1000000u
+#define AIPS_PACRP_TP1_SHIFT                     24
+#define AIPS_PACRP_TP1_WIDTH                     1
+#define AIPS_PACRP_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP1_SHIFT))&AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_WP1_MASK                      0x2000000u
+#define AIPS_PACRP_WP1_SHIFT                     25
+#define AIPS_PACRP_WP1_WIDTH                     1
+#define AIPS_PACRP_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP1_SHIFT))&AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_SP1_MASK                      0x4000000u
+#define AIPS_PACRP_SP1_SHIFT                     26
+#define AIPS_PACRP_SP1_WIDTH                     1
+#define AIPS_PACRP_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP1_SHIFT))&AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_TP0_MASK                      0x10000000u
+#define AIPS_PACRP_TP0_SHIFT                     28
+#define AIPS_PACRP_TP0_WIDTH                     1
+#define AIPS_PACRP_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP0_SHIFT))&AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_WP0_MASK                      0x20000000u
+#define AIPS_PACRP_WP0_SHIFT                     29
+#define AIPS_PACRP_WP0_WIDTH                     1
+#define AIPS_PACRP_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP0_SHIFT))&AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_SP0_MASK                      0x40000000u
+#define AIPS_PACRP_SP0_SHIFT                     30
+#define AIPS_PACRP_SP0_WIDTH                     1
+#define AIPS_PACRP_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP0_SHIFT))&AIPS_PACRP_SP0_MASK)
+/* PACRU Bit Fields */
+#define AIPS_PACRU_TP1_MASK                      0x1000000u
+#define AIPS_PACRU_TP1_SHIFT                     24
+#define AIPS_PACRU_TP1_WIDTH                     1
+#define AIPS_PACRU_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_TP1_SHIFT))&AIPS_PACRU_TP1_MASK)
+#define AIPS_PACRU_WP1_MASK                      0x2000000u
+#define AIPS_PACRU_WP1_SHIFT                     25
+#define AIPS_PACRU_WP1_WIDTH                     1
+#define AIPS_PACRU_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_WP1_SHIFT))&AIPS_PACRU_WP1_MASK)
+#define AIPS_PACRU_SP1_MASK                      0x4000000u
+#define AIPS_PACRU_SP1_SHIFT                     26
+#define AIPS_PACRU_SP1_WIDTH                     1
+#define AIPS_PACRU_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_SP1_SHIFT))&AIPS_PACRU_SP1_MASK)
+#define AIPS_PACRU_TP0_MASK                      0x10000000u
+#define AIPS_PACRU_TP0_SHIFT                     28
+#define AIPS_PACRU_TP0_WIDTH                     1
+#define AIPS_PACRU_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_TP0_SHIFT))&AIPS_PACRU_TP0_MASK)
+#define AIPS_PACRU_WP0_MASK                      0x20000000u
+#define AIPS_PACRU_WP0_SHIFT                     29
+#define AIPS_PACRU_WP0_WIDTH                     1
+#define AIPS_PACRU_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_WP0_SHIFT))&AIPS_PACRU_WP0_MASK)
+#define AIPS_PACRU_SP0_MASK                      0x40000000u
+#define AIPS_PACRU_SP0_SHIFT                     30
+#define AIPS_PACRU_SP0_WIDTH                     1
+#define AIPS_PACRU_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_SP0_SHIFT))&AIPS_PACRU_SP0_MASK)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base address */
+#define AIPS0_BASE                               (0x40000000u)
+/** Peripheral AIPS0 base pointer */
+#define AIPS0                                    ((AIPS_Type *)AIPS0_BASE)
+#define AIPS0_BASE_PTR                           (AIPS0)
+/** Peripheral AIPS1 base address */
+#define AIPS1_BASE                               (0x40080000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1                                    ((AIPS_Type *)AIPS1_BASE)
+#define AIPS1_BASE_PTR                           (AIPS1)
+/** Array initializer of AIPS peripheral base addresses */
+#define AIPS_BASE_ADDRS                          { AIPS0_BASE, AIPS1_BASE }
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS                           { AIPS0, AIPS1 }
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register instance definitions */
+/* AIPS0 */
+#define AIPS0_MPRA                               AIPS_MPRA_REG(AIPS0)
+#define AIPS0_PACRA                              AIPS_PACRA_REG(AIPS0)
+#define AIPS0_PACRB                              AIPS_PACRB_REG(AIPS0)
+#define AIPS0_PACRC                              AIPS_PACRC_REG(AIPS0)
+#define AIPS0_PACRD                              AIPS_PACRD_REG(AIPS0)
+#define AIPS0_PACRE                              AIPS_PACRE_REG(AIPS0)
+#define AIPS0_PACRF                              AIPS_PACRF_REG(AIPS0)
+#define AIPS0_PACRG                              AIPS_PACRG_REG(AIPS0)
+#define AIPS0_PACRH                              AIPS_PACRH_REG(AIPS0)
+#define AIPS0_PACRI                              AIPS_PACRI_REG(AIPS0)
+#define AIPS0_PACRJ                              AIPS_PACRJ_REG(AIPS0)
+#define AIPS0_PACRK                              AIPS_PACRK_REG(AIPS0)
+#define AIPS0_PACRL                              AIPS_PACRL_REG(AIPS0)
+#define AIPS0_PACRM                              AIPS_PACRM_REG(AIPS0)
+#define AIPS0_PACRN                              AIPS_PACRN_REG(AIPS0)
+#define AIPS0_PACRO                              AIPS_PACRO_REG(AIPS0)
+#define AIPS0_PACRP                              AIPS_PACRP_REG(AIPS0)
+#define AIPS0_PACRU                              AIPS_PACRU_REG(AIPS0)
+/* AIPS1 */
+#define AIPS1_MPRA                               AIPS_MPRA_REG(AIPS1)
+#define AIPS1_PACRA                              AIPS_PACRA_REG(AIPS1)
+#define AIPS1_PACRB                              AIPS_PACRB_REG(AIPS1)
+#define AIPS1_PACRC                              AIPS_PACRC_REG(AIPS1)
+#define AIPS1_PACRD                              AIPS_PACRD_REG(AIPS1)
+#define AIPS1_PACRE                              AIPS_PACRE_REG(AIPS1)
+#define AIPS1_PACRF                              AIPS_PACRF_REG(AIPS1)
+#define AIPS1_PACRG                              AIPS_PACRG_REG(AIPS1)
+#define AIPS1_PACRH                              AIPS_PACRH_REG(AIPS1)
+#define AIPS1_PACRI                              AIPS_PACRI_REG(AIPS1)
+#define AIPS1_PACRJ                              AIPS_PACRJ_REG(AIPS1)
+#define AIPS1_PACRK                              AIPS_PACRK_REG(AIPS1)
+#define AIPS1_PACRL                              AIPS_PACRL_REG(AIPS1)
+#define AIPS1_PACRM                              AIPS_PACRM_REG(AIPS1)
+#define AIPS1_PACRN                              AIPS_PACRN_REG(AIPS1)
+#define AIPS1_PACRO                              AIPS_PACRO_REG(AIPS1)
+#define AIPS1_PACRP                              AIPS_PACRP_REG(AIPS1)
+#define AIPS1_PACRU                              AIPS_PACRU_REG(AIPS1)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t PRS;                               /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CRS;                               /**< Control Register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_1[236];
+  } SLAVE[5];
+       uint8_t RESERVED_0[768];
+  __IO uint32_t MGPCR0;                            /**< Master General Purpose Control Register, offset: 0x800 */
+       uint8_t RESERVED_1[252];
+  __IO uint32_t MGPCR1;                            /**< Master General Purpose Control Register, offset: 0x900 */
+       uint8_t RESERVED_2[252];
+  __IO uint32_t MGPCR2;                            /**< Master General Purpose Control Register, offset: 0xA00 */
+       uint8_t RESERVED_3[252];
+  __IO uint32_t MGPCR3;                            /**< Master General Purpose Control Register, offset: 0xB00 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t MGPCR4;                            /**< Master General Purpose Control Register, offset: 0xC00 */
+       uint8_t RESERVED_5[252];
+  __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
+} AXBS_Type, *AXBS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register accessors */
+#define AXBS_PRS_REG(base,index)                 ((base)->SLAVE[index].PRS)
+#define AXBS_PRS_COUNT                           5
+#define AXBS_CRS_REG(base,index)                 ((base)->SLAVE[index].CRS)
+#define AXBS_CRS_COUNT                           5
+#define AXBS_MGPCR0_REG(base)                    ((base)->MGPCR0)
+#define AXBS_MGPCR1_REG(base)                    ((base)->MGPCR1)
+#define AXBS_MGPCR2_REG(base)                    ((base)->MGPCR2)
+#define AXBS_MGPCR3_REG(base)                    ((base)->MGPCR3)
+#define AXBS_MGPCR4_REG(base)                    ((base)->MGPCR4)
+#define AXBS_MGPCR5_REG(base)                    ((base)->MGPCR5)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/* PRS Bit Fields */
+#define AXBS_PRS_M0_MASK                         0x7u
+#define AXBS_PRS_M0_SHIFT                        0
+#define AXBS_PRS_M0_WIDTH                        3
+#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK                         0x70u
+#define AXBS_PRS_M1_SHIFT                        4
+#define AXBS_PRS_M1_WIDTH                        3
+#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK                         0x700u
+#define AXBS_PRS_M2_SHIFT                        8
+#define AXBS_PRS_M2_WIDTH                        3
+#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK                         0x7000u
+#define AXBS_PRS_M3_SHIFT                        12
+#define AXBS_PRS_M3_WIDTH                        3
+#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK                         0x70000u
+#define AXBS_PRS_M4_SHIFT                        16
+#define AXBS_PRS_M4_WIDTH                        3
+#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK                         0x700000u
+#define AXBS_PRS_M5_SHIFT                        20
+#define AXBS_PRS_M5_WIDTH                        3
+#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
+/* CRS Bit Fields */
+#define AXBS_CRS_PARK_MASK                       0x7u
+#define AXBS_CRS_PARK_SHIFT                      0
+#define AXBS_CRS_PARK_WIDTH                      3
+#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK                       0x30u
+#define AXBS_CRS_PCTL_SHIFT                      4
+#define AXBS_CRS_PCTL_WIDTH                      2
+#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK                        0x300u
+#define AXBS_CRS_ARB_SHIFT                       8
+#define AXBS_CRS_ARB_WIDTH                       2
+#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK                        0x40000000u
+#define AXBS_CRS_HLP_SHIFT                       30
+#define AXBS_CRS_HLP_WIDTH                       1
+#define AXBS_CRS_HLP(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_HLP_SHIFT))&AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_RO_MASK                         0x80000000u
+#define AXBS_CRS_RO_SHIFT                        31
+#define AXBS_CRS_RO_WIDTH                        1
+#define AXBS_CRS_RO(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_RO_SHIFT))&AXBS_CRS_RO_MASK)
+/* MGPCR0 Bit Fields */
+#define AXBS_MGPCR0_AULB_MASK                    0x7u
+#define AXBS_MGPCR0_AULB_SHIFT                   0
+#define AXBS_MGPCR0_AULB_WIDTH                   3
+#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
+/* MGPCR1 Bit Fields */
+#define AXBS_MGPCR1_AULB_MASK                    0x7u
+#define AXBS_MGPCR1_AULB_SHIFT                   0
+#define AXBS_MGPCR1_AULB_WIDTH                   3
+#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
+/* MGPCR2 Bit Fields */
+#define AXBS_MGPCR2_AULB_MASK                    0x7u
+#define AXBS_MGPCR2_AULB_SHIFT                   0
+#define AXBS_MGPCR2_AULB_WIDTH                   3
+#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
+/* MGPCR3 Bit Fields */
+#define AXBS_MGPCR3_AULB_MASK                    0x7u
+#define AXBS_MGPCR3_AULB_SHIFT                   0
+#define AXBS_MGPCR3_AULB_WIDTH                   3
+#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
+/* MGPCR4 Bit Fields */
+#define AXBS_MGPCR4_AULB_MASK                    0x7u
+#define AXBS_MGPCR4_AULB_SHIFT                   0
+#define AXBS_MGPCR4_AULB_WIDTH                   3
+#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
+/* MGPCR5 Bit Fields */
+#define AXBS_MGPCR5_AULB_MASK                    0x7u
+#define AXBS_MGPCR5_AULB_SHIFT                   0
+#define AXBS_MGPCR5_AULB_WIDTH                   3
+#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS base address */
+#define AXBS_BASE                                (0x40004000u)
+/** Peripheral AXBS base pointer */
+#define AXBS                                     ((AXBS_Type *)AXBS_BASE)
+#define AXBS_BASE_PTR                            (AXBS)
+/** Array initializer of AXBS peripheral base addresses */
+#define AXBS_BASE_ADDRS                          { AXBS_BASE }
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASE_PTRS                           { AXBS }
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register instance definitions */
+/* AXBS */
+#define AXBS_PRS0                                AXBS_PRS_REG(AXBS,0)
+#define AXBS_CRS0                                AXBS_CRS_REG(AXBS,0)
+#define AXBS_PRS1                                AXBS_PRS_REG(AXBS,1)
+#define AXBS_CRS1                                AXBS_CRS_REG(AXBS,1)
+#define AXBS_PRS2                                AXBS_PRS_REG(AXBS,2)
+#define AXBS_CRS2                                AXBS_CRS_REG(AXBS,2)
+#define AXBS_PRS3                                AXBS_PRS_REG(AXBS,3)
+#define AXBS_CRS3                                AXBS_CRS_REG(AXBS,3)
+#define AXBS_PRS4                                AXBS_PRS_REG(AXBS,4)
+#define AXBS_CRS4                                AXBS_CRS_REG(AXBS,4)
+#define AXBS_MGPCR0                              AXBS_MGPCR0_REG(AXBS)
+#define AXBS_MGPCR1                              AXBS_MGPCR1_REG(AXBS)
+#define AXBS_MGPCR2                              AXBS_MGPCR2_REG(AXBS)
+#define AXBS_MGPCR3                              AXBS_MGPCR3_REG(AXBS)
+#define AXBS_MGPCR4                              AXBS_MGPCR4_REG(AXBS)
+#define AXBS_MGPCR5                              AXBS_MGPCR5_REG(AXBS)
+
+/* AXBS - Register array accessors */
+#define AXBS_PRS(index)                          AXBS_PRS_REG(AXBS,index)
+#define AXBS_CRS(index)                          AXBS_CRS_REG(AXBS,index)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
+  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
+  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
+  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
+  __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
+  __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
+  __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
+  __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
+  __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
+       uint8_t RESERVED_4[48];
+  struct {                                         /* offset: 0x80, array step: 0x10 */
+    __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+    __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+    __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+    __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+  } MB[16];
+       uint8_t RESERVED_5[1792];
+  __IO uint32_t RXIMR[16];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_Type, *CAN_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register accessors */
+#define CAN_MCR_REG(base)                        ((base)->MCR)
+#define CAN_CTRL1_REG(base)                      ((base)->CTRL1)
+#define CAN_TIMER_REG(base)                      ((base)->TIMER)
+#define CAN_RXMGMASK_REG(base)                   ((base)->RXMGMASK)
+#define CAN_RX14MASK_REG(base)                   ((base)->RX14MASK)
+#define CAN_RX15MASK_REG(base)                   ((base)->RX15MASK)
+#define CAN_ECR_REG(base)                        ((base)->ECR)
+#define CAN_ESR1_REG(base)                       ((base)->ESR1)
+#define CAN_IMASK1_REG(base)                     ((base)->IMASK1)
+#define CAN_IFLAG1_REG(base)                     ((base)->IFLAG1)
+#define CAN_CTRL2_REG(base)                      ((base)->CTRL2)
+#define CAN_ESR2_REG(base)                       ((base)->ESR2)
+#define CAN_CRCR_REG(base)                       ((base)->CRCR)
+#define CAN_RXFGMASK_REG(base)                   ((base)->RXFGMASK)
+#define CAN_RXFIR_REG(base)                      ((base)->RXFIR)
+#define CAN_CS_REG(base,index)                   ((base)->MB[index].CS)
+#define CAN_CS_COUNT                             16
+#define CAN_ID_REG(base,index)                   ((base)->MB[index].ID)
+#define CAN_ID_COUNT                             16
+#define CAN_WORD0_REG(base,index)                ((base)->MB[index].WORD0)
+#define CAN_WORD0_COUNT                          16
+#define CAN_WORD1_REG(base,index)                ((base)->MB[index].WORD1)
+#define CAN_WORD1_COUNT                          16
+#define CAN_RXIMR_REG(base,index)                ((base)->RXIMR[index])
+#define CAN_RXIMR_COUNT                          16
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define CAN_MCR_MAXMB_MASK                       0x7Fu
+#define CAN_MCR_MAXMB_SHIFT                      0
+#define CAN_MCR_MAXMB_WIDTH                      7
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK                        0x300u
+#define CAN_MCR_IDAM_SHIFT                       8
+#define CAN_MCR_IDAM_WIDTH                       2
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK                         0x1000u
+#define CAN_MCR_AEN_SHIFT                        12
+#define CAN_MCR_AEN_WIDTH                        1
+#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK                     0x2000u
+#define CAN_MCR_LPRIOEN_SHIFT                    13
+#define CAN_MCR_LPRIOEN_WIDTH                    1
+#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_IRMQ_MASK                        0x10000u
+#define CAN_MCR_IRMQ_SHIFT                       16
+#define CAN_MCR_IRMQ_WIDTH                       1
+#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK                      0x20000u
+#define CAN_MCR_SRXDIS_SHIFT                     17
+#define CAN_MCR_SRXDIS_WIDTH                     1
+#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_WAKSRC_MASK                      0x80000u
+#define CAN_MCR_WAKSRC_SHIFT                     19
+#define CAN_MCR_WAKSRC_WIDTH                     1
+#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKSRC_SHIFT))&CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_LPMACK_MASK                      0x100000u
+#define CAN_MCR_LPMACK_SHIFT                     20
+#define CAN_MCR_LPMACK_WIDTH                     1
+#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK                       0x200000u
+#define CAN_MCR_WRNEN_SHIFT                      21
+#define CAN_MCR_WRNEN_WIDTH                      1
+#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SLFWAK_MASK                      0x400000u
+#define CAN_MCR_SLFWAK_SHIFT                     22
+#define CAN_MCR_SLFWAK_WIDTH                     1
+#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SLFWAK_SHIFT))&CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SUPV_MASK                        0x800000u
+#define CAN_MCR_SUPV_SHIFT                       23
+#define CAN_MCR_SUPV_WIDTH                       1
+#define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
+#define CAN_MCR_FRZACK_MASK                      0x1000000u
+#define CAN_MCR_FRZACK_SHIFT                     24
+#define CAN_MCR_FRZACK_WIDTH                     1
+#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK                     0x2000000u
+#define CAN_MCR_SOFTRST_SHIFT                    25
+#define CAN_MCR_SOFTRST_WIDTH                    1
+#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_WAKMSK_MASK                      0x4000000u
+#define CAN_MCR_WAKMSK_SHIFT                     26
+#define CAN_MCR_WAKMSK_WIDTH                     1
+#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKMSK_SHIFT))&CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_NOTRDY_MASK                      0x8000000u
+#define CAN_MCR_NOTRDY_SHIFT                     27
+#define CAN_MCR_NOTRDY_WIDTH                     1
+#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK                        0x10000000u
+#define CAN_MCR_HALT_SHIFT                       28
+#define CAN_MCR_HALT_WIDTH                       1
+#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK                        0x20000000u
+#define CAN_MCR_RFEN_SHIFT                       29
+#define CAN_MCR_RFEN_WIDTH                       1
+#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK                         0x40000000u
+#define CAN_MCR_FRZ_SHIFT                        30
+#define CAN_MCR_FRZ_WIDTH                        1
+#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK                        0x80000000u
+#define CAN_MCR_MDIS_SHIFT                       31
+#define CAN_MCR_MDIS_WIDTH                       1
+#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
+/* CTRL1 Bit Fields */
+#define CAN_CTRL1_PROPSEG_MASK                   0x7u
+#define CAN_CTRL1_PROPSEG_SHIFT                  0
+#define CAN_CTRL1_PROPSEG_WIDTH                  3
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK                       0x8u
+#define CAN_CTRL1_LOM_SHIFT                      3
+#define CAN_CTRL1_LOM_WIDTH                      1
+#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK                      0x10u
+#define CAN_CTRL1_LBUF_SHIFT                     4
+#define CAN_CTRL1_LBUF_WIDTH                     1
+#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK                      0x20u
+#define CAN_CTRL1_TSYN_SHIFT                     5
+#define CAN_CTRL1_TSYN_WIDTH                     1
+#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK                   0x40u
+#define CAN_CTRL1_BOFFREC_SHIFT                  6
+#define CAN_CTRL1_BOFFREC_WIDTH                  1
+#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK                       0x80u
+#define CAN_CTRL1_SMP_SHIFT                      7
+#define CAN_CTRL1_SMP_WIDTH                      1
+#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK                   0x400u
+#define CAN_CTRL1_RWRNMSK_SHIFT                  10
+#define CAN_CTRL1_RWRNMSK_WIDTH                  1
+#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK                   0x800u
+#define CAN_CTRL1_TWRNMSK_SHIFT                  11
+#define CAN_CTRL1_TWRNMSK_WIDTH                  1
+#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK                       0x1000u
+#define CAN_CTRL1_LPB_SHIFT                      12
+#define CAN_CTRL1_LPB_WIDTH                      1
+#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_CLKSRC_MASK                    0x2000u
+#define CAN_CTRL1_CLKSRC_SHIFT                   13
+#define CAN_CTRL1_CLKSRC_WIDTH                   1
+#define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_ERRMSK_MASK                    0x4000u
+#define CAN_CTRL1_ERRMSK_SHIFT                   14
+#define CAN_CTRL1_ERRMSK_WIDTH                   1
+#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK                   0x8000u
+#define CAN_CTRL1_BOFFMSK_SHIFT                  15
+#define CAN_CTRL1_BOFFMSK_WIDTH                  1
+#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK                     0x70000u
+#define CAN_CTRL1_PSEG2_SHIFT                    16
+#define CAN_CTRL1_PSEG2_WIDTH                    3
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK                     0x380000u
+#define CAN_CTRL1_PSEG1_SHIFT                    19
+#define CAN_CTRL1_PSEG1_WIDTH                    3
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK                       0xC00000u
+#define CAN_CTRL1_RJW_SHIFT                      22
+#define CAN_CTRL1_RJW_WIDTH                      2
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
+#define CAN_CTRL1_PRESDIV_SHIFT                  24
+#define CAN_CTRL1_PRESDIV_WIDTH                  8
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
+/* TIMER Bit Fields */
+#define CAN_TIMER_TIMER_MASK                     0xFFFFu
+#define CAN_TIMER_TIMER_SHIFT                    0
+#define CAN_TIMER_TIMER_WIDTH                    16
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
+/* RXMGMASK Bit Fields */
+#define CAN_RXMGMASK_MG_MASK                     0xFFFFFFFFu
+#define CAN_RXMGMASK_MG_SHIFT                    0
+#define CAN_RXMGMASK_MG_WIDTH                    32
+#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
+/* RX14MASK Bit Fields */
+#define CAN_RX14MASK_RX14M_MASK                  0xFFFFFFFFu
+#define CAN_RX14MASK_RX14M_SHIFT                 0
+#define CAN_RX14MASK_RX14M_WIDTH                 32
+#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
+/* RX15MASK Bit Fields */
+#define CAN_RX15MASK_RX15M_MASK                  0xFFFFFFFFu
+#define CAN_RX15MASK_RX15M_SHIFT                 0
+#define CAN_RX15MASK_RX15M_WIDTH                 32
+#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
+/* ECR Bit Fields */
+#define CAN_ECR_TXERRCNT_MASK                    0xFFu
+#define CAN_ECR_TXERRCNT_SHIFT                   0
+#define CAN_ECR_TXERRCNT_WIDTH                   8
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK                    0xFF00u
+#define CAN_ECR_RXERRCNT_SHIFT                   8
+#define CAN_ECR_RXERRCNT_WIDTH                   8
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
+/* ESR1 Bit Fields */
+#define CAN_ESR1_WAKINT_MASK                     0x1u
+#define CAN_ESR1_WAKINT_SHIFT                    0
+#define CAN_ESR1_WAKINT_WIDTH                    1
+#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_WAKINT_SHIFT))&CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_ERRINT_MASK                     0x2u
+#define CAN_ESR1_ERRINT_SHIFT                    1
+#define CAN_ESR1_ERRINT_WIDTH                    1
+#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK                    0x4u
+#define CAN_ESR1_BOFFINT_SHIFT                   2
+#define CAN_ESR1_BOFFINT_WIDTH                   1
+#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK                         0x8u
+#define CAN_ESR1_RX_SHIFT                        3
+#define CAN_ESR1_RX_WIDTH                        1
+#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK                    0x30u
+#define CAN_ESR1_FLTCONF_SHIFT                   4
+#define CAN_ESR1_FLTCONF_WIDTH                   2
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK                         0x40u
+#define CAN_ESR1_TX_SHIFT                        6
+#define CAN_ESR1_TX_WIDTH                        1
+#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK                       0x80u
+#define CAN_ESR1_IDLE_SHIFT                      7
+#define CAN_ESR1_IDLE_WIDTH                      1
+#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK                      0x100u
+#define CAN_ESR1_RXWRN_SHIFT                     8
+#define CAN_ESR1_RXWRN_WIDTH                     1
+#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK                      0x200u
+#define CAN_ESR1_TXWRN_SHIFT                     9
+#define CAN_ESR1_TXWRN_WIDTH                     1
+#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK                     0x400u
+#define CAN_ESR1_STFERR_SHIFT                    10
+#define CAN_ESR1_STFERR_WIDTH                    1
+#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK                     0x800u
+#define CAN_ESR1_FRMERR_SHIFT                    11
+#define CAN_ESR1_FRMERR_WIDTH                    1
+#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK                     0x1000u
+#define CAN_ESR1_CRCERR_SHIFT                    12
+#define CAN_ESR1_CRCERR_WIDTH                    1
+#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK                     0x2000u
+#define CAN_ESR1_ACKERR_SHIFT                    13
+#define CAN_ESR1_ACKERR_WIDTH                    1
+#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK                    0x4000u
+#define CAN_ESR1_BIT0ERR_SHIFT                   14
+#define CAN_ESR1_BIT0ERR_WIDTH                   1
+#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK                    0x8000u
+#define CAN_ESR1_BIT1ERR_SHIFT                   15
+#define CAN_ESR1_BIT1ERR_WIDTH                   1
+#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK                    0x10000u
+#define CAN_ESR1_RWRNINT_SHIFT                   16
+#define CAN_ESR1_RWRNINT_WIDTH                   1
+#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK                    0x20000u
+#define CAN_ESR1_TWRNINT_SHIFT                   17
+#define CAN_ESR1_TWRNINT_WIDTH                   1
+#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK                      0x40000u
+#define CAN_ESR1_SYNCH_SHIFT                     18
+#define CAN_ESR1_SYNCH_WIDTH                     1
+#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
+/* IMASK1 Bit Fields */
+#define CAN_IMASK1_BUFLM_MASK                    0xFFFFFFFFu
+#define CAN_IMASK1_BUFLM_SHIFT                   0
+#define CAN_IMASK1_BUFLM_WIDTH                   32
+#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
+/* IFLAG1 Bit Fields */
+#define CAN_IFLAG1_BUF0I_MASK                    0x1u
+#define CAN_IFLAG1_BUF0I_SHIFT                   0
+#define CAN_IFLAG1_BUF0I_WIDTH                   1
+#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF4TO1I_MASK                 0x1Eu
+#define CAN_IFLAG1_BUF4TO1I_SHIFT                1
+#define CAN_IFLAG1_BUF4TO1I_WIDTH                4
+#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK                    0x20u
+#define CAN_IFLAG1_BUF5I_SHIFT                   5
+#define CAN_IFLAG1_BUF5I_WIDTH                   1
+#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK                    0x40u
+#define CAN_IFLAG1_BUF6I_SHIFT                   6
+#define CAN_IFLAG1_BUF6I_WIDTH                   1
+#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK                    0x80u
+#define CAN_IFLAG1_BUF7I_SHIFT                   7
+#define CAN_IFLAG1_BUF7I_WIDTH                   1
+#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK                0xFFFFFF00u
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               8
+#define CAN_IFLAG1_BUF31TO8I_WIDTH               24
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
+/* CTRL2 Bit Fields */
+#define CAN_CTRL2_EACEN_MASK                     0x10000u
+#define CAN_CTRL2_EACEN_SHIFT                    16
+#define CAN_CTRL2_EACEN_WIDTH                    1
+#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK                       0x20000u
+#define CAN_CTRL2_RRS_SHIFT                      17
+#define CAN_CTRL2_RRS_WIDTH                      1
+#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK                       0x40000u
+#define CAN_CTRL2_MRP_SHIFT                      18
+#define CAN_CTRL2_MRP_WIDTH                      1
+#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK                      0xF80000u
+#define CAN_CTRL2_TASD_SHIFT                     19
+#define CAN_CTRL2_TASD_WIDTH                     5
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK                      0xF000000u
+#define CAN_CTRL2_RFFN_SHIFT                     24
+#define CAN_CTRL2_RFFN_WIDTH                     4
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK                    0x10000000u
+#define CAN_CTRL2_WRMFRZ_SHIFT                   28
+#define CAN_CTRL2_WRMFRZ_WIDTH                   1
+#define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_WRMFRZ_SHIFT))&CAN_CTRL2_WRMFRZ_MASK)
+/* ESR2 Bit Fields */
+#define CAN_ESR2_IMB_MASK                        0x2000u
+#define CAN_ESR2_IMB_SHIFT                       13
+#define CAN_ESR2_IMB_WIDTH                       1
+#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK                        0x4000u
+#define CAN_ESR2_VPS_SHIFT                       14
+#define CAN_ESR2_VPS_WIDTH                       1
+#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK                       0x7F0000u
+#define CAN_ESR2_LPTM_SHIFT                      16
+#define CAN_ESR2_LPTM_WIDTH                      7
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
+/* CRCR Bit Fields */
+#define CAN_CRCR_TXCRC_MASK                      0x7FFFu
+#define CAN_CRCR_TXCRC_SHIFT                     0
+#define CAN_CRCR_TXCRC_WIDTH                     15
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK                      0x7F0000u
+#define CAN_CRCR_MBCRC_SHIFT                     16
+#define CAN_CRCR_MBCRC_WIDTH                     7
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
+/* RXFGMASK Bit Fields */
+#define CAN_RXFGMASK_FGM_MASK                    0xFFFFFFFFu
+#define CAN_RXFGMASK_FGM_SHIFT                   0
+#define CAN_RXFGMASK_FGM_WIDTH                   32
+#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
+/* RXFIR Bit Fields */
+#define CAN_RXFIR_IDHIT_MASK                     0x1FFu
+#define CAN_RXFIR_IDHIT_SHIFT                    0
+#define CAN_RXFIR_IDHIT_WIDTH                    9
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
+/* CS Bit Fields */
+#define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
+#define CAN_CS_TIME_STAMP_SHIFT                  0
+#define CAN_CS_TIME_STAMP_WIDTH                  16
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK                          0xF0000u
+#define CAN_CS_DLC_SHIFT                         16
+#define CAN_CS_DLC_WIDTH                         4
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK                          0x100000u
+#define CAN_CS_RTR_SHIFT                         20
+#define CAN_CS_RTR_WIDTH                         1
+#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_RTR_SHIFT))&CAN_CS_RTR_MASK)
+#define CAN_CS_IDE_MASK                          0x200000u
+#define CAN_CS_IDE_SHIFT                         21
+#define CAN_CS_IDE_WIDTH                         1
+#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_IDE_SHIFT))&CAN_CS_IDE_MASK)
+#define CAN_CS_SRR_MASK                          0x400000u
+#define CAN_CS_SRR_SHIFT                         22
+#define CAN_CS_SRR_WIDTH                         1
+#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_SRR_SHIFT))&CAN_CS_SRR_MASK)
+#define CAN_CS_CODE_MASK                         0xF000000u
+#define CAN_CS_CODE_SHIFT                        24
+#define CAN_CS_CODE_WIDTH                        4
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
+/* ID Bit Fields */
+#define CAN_ID_EXT_MASK                          0x3FFFFu
+#define CAN_ID_EXT_SHIFT                         0
+#define CAN_ID_EXT_WIDTH                         18
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK                          0x1FFC0000u
+#define CAN_ID_STD_SHIFT                         18
+#define CAN_ID_STD_WIDTH                         11
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK                         0xE0000000u
+#define CAN_ID_PRIO_SHIFT                        29
+#define CAN_ID_PRIO_WIDTH                        3
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
+/* WORD0 Bit Fields */
+#define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              0
+#define CAN_WORD0_DATA_BYTE_3_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              8
+#define CAN_WORD0_DATA_BYTE_2_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              16
+#define CAN_WORD0_DATA_BYTE_1_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              24
+#define CAN_WORD0_DATA_BYTE_0_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
+/* WORD1 Bit Fields */
+#define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              0
+#define CAN_WORD1_DATA_BYTE_7_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              8
+#define CAN_WORD1_DATA_BYTE_6_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              16
+#define CAN_WORD1_DATA_BYTE_5_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              24
+#define CAN_WORD1_DATA_BYTE_4_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
+/* RXIMR Bit Fields */
+#define CAN_RXIMR_MI_MASK                        0xFFFFFFFFu
+#define CAN_RXIMR_MI_SHIFT                       0
+#define CAN_RXIMR_MI_WIDTH                       32
+#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+#define CAN0_BASE_PTR                            (CAN0)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS                      { CAN0_Rx_Warning_IRQn }
+#define CAN_Tx_Warning_IRQS                      { CAN0_Tx_Warning_IRQn }
+#define CAN_Wake_Up_IRQS                         { CAN0_Wake_Up_IRQn }
+#define CAN_Error_IRQS                           { CAN0_Error_IRQn }
+#define CAN_Bus_Off_IRQS                         { CAN0_Bus_Off_IRQn }
+#define CAN_ORed_Message_buffer_IRQS             { CAN0_ORed_Message_buffer_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register instance definitions */
+/* CAN0 */
+#define CAN0_MCR                                 CAN_MCR_REG(CAN0)
+#define CAN0_CTRL1                               CAN_CTRL1_REG(CAN0)
+#define CAN0_TIMER                               CAN_TIMER_REG(CAN0)
+#define CAN0_RXMGMASK                            CAN_RXMGMASK_REG(CAN0)
+#define CAN0_RX14MASK                            CAN_RX14MASK_REG(CAN0)
+#define CAN0_RX15MASK                            CAN_RX15MASK_REG(CAN0)
+#define CAN0_ECR                                 CAN_ECR_REG(CAN0)
+#define CAN0_ESR1                                CAN_ESR1_REG(CAN0)
+#define CAN0_IMASK1                              CAN_IMASK1_REG(CAN0)
+#define CAN0_IFLAG1                              CAN_IFLAG1_REG(CAN0)
+#define CAN0_CTRL2                               CAN_CTRL2_REG(CAN0)
+#define CAN0_ESR2                                CAN_ESR2_REG(CAN0)
+#define CAN0_CRCR                                CAN_CRCR_REG(CAN0)
+#define CAN0_RXFGMASK                            CAN_RXFGMASK_REG(CAN0)
+#define CAN0_RXFIR                               CAN_RXFIR_REG(CAN0)
+#define CAN0_CS0                                 CAN_CS_REG(CAN0,0)
+#define CAN0_ID0                                 CAN_ID_REG(CAN0,0)
+#define CAN0_WORD00                              CAN_WORD0_REG(CAN0,0)
+#define CAN0_WORD10                              CAN_WORD1_REG(CAN0,0)
+#define CAN0_CS1                                 CAN_CS_REG(CAN0,1)
+#define CAN0_ID1                                 CAN_ID_REG(CAN0,1)
+#define CAN0_WORD01                              CAN_WORD0_REG(CAN0,1)
+#define CAN0_WORD11                              CAN_WORD1_REG(CAN0,1)
+#define CAN0_CS2                                 CAN_CS_REG(CAN0,2)
+#define CAN0_ID2                                 CAN_ID_REG(CAN0,2)
+#define CAN0_WORD02                              CAN_WORD0_REG(CAN0,2)
+#define CAN0_WORD12                              CAN_WORD1_REG(CAN0,2)
+#define CAN0_CS3                                 CAN_CS_REG(CAN0,3)
+#define CAN0_ID3                                 CAN_ID_REG(CAN0,3)
+#define CAN0_WORD03                              CAN_WORD0_REG(CAN0,3)
+#define CAN0_WORD13                              CAN_WORD1_REG(CAN0,3)
+#define CAN0_CS4                                 CAN_CS_REG(CAN0,4)
+#define CAN0_ID4                                 CAN_ID_REG(CAN0,4)
+#define CAN0_WORD04                              CAN_WORD0_REG(CAN0,4)
+#define CAN0_WORD14                              CAN_WORD1_REG(CAN0,4)
+#define CAN0_CS5                                 CAN_CS_REG(CAN0,5)
+#define CAN0_ID5                                 CAN_ID_REG(CAN0,5)
+#define CAN0_WORD05                              CAN_WORD0_REG(CAN0,5)
+#define CAN0_WORD15                              CAN_WORD1_REG(CAN0,5)
+#define CAN0_CS6                                 CAN_CS_REG(CAN0,6)
+#define CAN0_ID6                                 CAN_ID_REG(CAN0,6)
+#define CAN0_WORD06                              CAN_WORD0_REG(CAN0,6)
+#define CAN0_WORD16                              CAN_WORD1_REG(CAN0,6)
+#define CAN0_CS7                                 CAN_CS_REG(CAN0,7)
+#define CAN0_ID7                                 CAN_ID_REG(CAN0,7)
+#define CAN0_WORD07                              CAN_WORD0_REG(CAN0,7)
+#define CAN0_WORD17                              CAN_WORD1_REG(CAN0,7)
+#define CAN0_CS8                                 CAN_CS_REG(CAN0,8)
+#define CAN0_ID8                                 CAN_ID_REG(CAN0,8)
+#define CAN0_WORD08                              CAN_WORD0_REG(CAN0,8)
+#define CAN0_WORD18                              CAN_WORD1_REG(CAN0,8)
+#define CAN0_CS9                                 CAN_CS_REG(CAN0,9)
+#define CAN0_ID9                                 CAN_ID_REG(CAN0,9)
+#define CAN0_WORD09                              CAN_WORD0_REG(CAN0,9)
+#define CAN0_WORD19                              CAN_WORD1_REG(CAN0,9)
+#define CAN0_CS10                                CAN_CS_REG(CAN0,10)
+#define CAN0_ID10                                CAN_ID_REG(CAN0,10)
+#define CAN0_WORD010                             CAN_WORD0_REG(CAN0,10)
+#define CAN0_WORD110                             CAN_WORD1_REG(CAN0,10)
+#define CAN0_CS11                                CAN_CS_REG(CAN0,11)
+#define CAN0_ID11                                CAN_ID_REG(CAN0,11)
+#define CAN0_WORD011                             CAN_WORD0_REG(CAN0,11)
+#define CAN0_WORD111                             CAN_WORD1_REG(CAN0,11)
+#define CAN0_CS12                                CAN_CS_REG(CAN0,12)
+#define CAN0_ID12                                CAN_ID_REG(CAN0,12)
+#define CAN0_WORD012                             CAN_WORD0_REG(CAN0,12)
+#define CAN0_WORD112                             CAN_WORD1_REG(CAN0,12)
+#define CAN0_CS13                                CAN_CS_REG(CAN0,13)
+#define CAN0_ID13                                CAN_ID_REG(CAN0,13)
+#define CAN0_WORD013                             CAN_WORD0_REG(CAN0,13)
+#define CAN0_WORD113                             CAN_WORD1_REG(CAN0,13)
+#define CAN0_CS14                                CAN_CS_REG(CAN0,14)
+#define CAN0_ID14                                CAN_ID_REG(CAN0,14)
+#define CAN0_WORD014                             CAN_WORD0_REG(CAN0,14)
+#define CAN0_WORD114                             CAN_WORD1_REG(CAN0,14)
+#define CAN0_CS15                                CAN_CS_REG(CAN0,15)
+#define CAN0_ID15                                CAN_ID_REG(CAN0,15)
+#define CAN0_WORD015                             CAN_WORD0_REG(CAN0,15)
+#define CAN0_WORD115                             CAN_WORD1_REG(CAN0,15)
+#define CAN0_RXIMR0                              CAN_RXIMR_REG(CAN0,0)
+#define CAN0_RXIMR1                              CAN_RXIMR_REG(CAN0,1)
+#define CAN0_RXIMR2                              CAN_RXIMR_REG(CAN0,2)
+#define CAN0_RXIMR3                              CAN_RXIMR_REG(CAN0,3)
+#define CAN0_RXIMR4                              CAN_RXIMR_REG(CAN0,4)
+#define CAN0_RXIMR5                              CAN_RXIMR_REG(CAN0,5)
+#define CAN0_RXIMR6                              CAN_RXIMR_REG(CAN0,6)
+#define CAN0_RXIMR7                              CAN_RXIMR_REG(CAN0,7)
+#define CAN0_RXIMR8                              CAN_RXIMR_REG(CAN0,8)
+#define CAN0_RXIMR9                              CAN_RXIMR_REG(CAN0,9)
+#define CAN0_RXIMR10                             CAN_RXIMR_REG(CAN0,10)
+#define CAN0_RXIMR11                             CAN_RXIMR_REG(CAN0,11)
+#define CAN0_RXIMR12                             CAN_RXIMR_REG(CAN0,12)
+#define CAN0_RXIMR13                             CAN_RXIMR_REG(CAN0,13)
+#define CAN0_RXIMR14                             CAN_RXIMR_REG(CAN0,14)
+#define CAN0_RXIMR15                             CAN_RXIMR_REG(CAN0,15)
+
+/* CAN - Register array accessors */
+#define CAN0_CS(index)                           CAN_CS_REG(CAN0,index)
+#define CAN0_ID(index)                           CAN_ID_REG(CAN0,index)
+#define CAN0_WORD0(index)                        CAN_WORD0_REG(CAN0,index)
+#define CAN0_WORD1(index)                        CAN_WORD1_REG(CAN0,index)
+#define CAN0_RXIMR(index)                        CAN_RXIMR_REG(CAN0,index)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+  __O  uint32_t DIRECT[16];                        /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[2048];
+  __O  uint32_t LDR_CASR;                          /**< Status register - Load Register command, offset: 0x840 */
+  __O  uint32_t LDR_CAA;                           /**< Accumulator register - Load Register command, offset: 0x844 */
+  __O  uint32_t LDR_CA[9];                         /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
+       uint8_t RESERVED_1[20];
+  __I  uint32_t STR_CASR;                          /**< Status register - Store Register command, offset: 0x880 */
+  __I  uint32_t STR_CAA;                           /**< Accumulator register - Store Register command, offset: 0x884 */
+  __I  uint32_t STR_CA[9];                         /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
+       uint8_t RESERVED_2[20];
+  __O  uint32_t ADR_CASR;                          /**< Status register - Add Register command, offset: 0x8C0 */
+  __O  uint32_t ADR_CAA;                           /**< Accumulator register - Add to register command, offset: 0x8C4 */
+  __O  uint32_t ADR_CA[9];                         /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
+       uint8_t RESERVED_3[20];
+  __O  uint32_t RADR_CASR;                         /**< Status register - Reverse and Add to Register command, offset: 0x900 */
+  __O  uint32_t RADR_CAA;                          /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
+  __O  uint32_t RADR_CA[9];                        /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
+       uint8_t RESERVED_4[84];
+  __O  uint32_t XOR_CASR;                          /**< Status register - Exclusive Or command, offset: 0x980 */
+  __O  uint32_t XOR_CAA;                           /**< Accumulator register - Exclusive Or command, offset: 0x984 */
+  __O  uint32_t XOR_CA[9];                         /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
+       uint8_t RESERVED_5[20];
+  __O  uint32_t ROTL_CASR;                         /**< Status register - Rotate Left command, offset: 0x9C0 */
+  __O  uint32_t ROTL_CAA;                          /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
+  __O  uint32_t ROTL_CA[9];                        /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
+       uint8_t RESERVED_6[276];
+  __O  uint32_t AESC_CASR;                         /**< Status register - AES Column Operation command, offset: 0xB00 */
+  __O  uint32_t AESC_CAA;                          /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
+  __O  uint32_t AESC_CA[9];                        /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
+       uint8_t RESERVED_7[20];
+  __O  uint32_t AESIC_CASR;                        /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
+  __O  uint32_t AESIC_CAA;                         /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
+  __O  uint32_t AESIC_CA[9];                       /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
+} CAU_Type, *CAU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register accessors */
+#define CAU_DIRECT_REG(base,index)               ((base)->DIRECT[index])
+#define CAU_DIRECT_COUNT                         16
+#define CAU_LDR_CASR_REG(base)                   ((base)->LDR_CASR)
+#define CAU_LDR_CAA_REG(base)                    ((base)->LDR_CAA)
+#define CAU_LDR_CA_REG(base,index)               ((base)->LDR_CA[index])
+#define CAU_LDR_CA_COUNT                         9
+#define CAU_STR_CASR_REG(base)                   ((base)->STR_CASR)
+#define CAU_STR_CAA_REG(base)                    ((base)->STR_CAA)
+#define CAU_STR_CA_REG(base,index)               ((base)->STR_CA[index])
+#define CAU_STR_CA_COUNT                         9
+#define CAU_ADR_CASR_REG(base)                   ((base)->ADR_CASR)
+#define CAU_ADR_CAA_REG(base)                    ((base)->ADR_CAA)
+#define CAU_ADR_CA_REG(base,index)               ((base)->ADR_CA[index])
+#define CAU_ADR_CA_COUNT                         9
+#define CAU_RADR_CASR_REG(base)                  ((base)->RADR_CASR)
+#define CAU_RADR_CAA_REG(base)                   ((base)->RADR_CAA)
+#define CAU_RADR_CA_REG(base,index)              ((base)->RADR_CA[index])
+#define CAU_RADR_CA_COUNT                        9
+#define CAU_XOR_CASR_REG(base)                   ((base)->XOR_CASR)
+#define CAU_XOR_CAA_REG(base)                    ((base)->XOR_CAA)
+#define CAU_XOR_CA_REG(base,index)               ((base)->XOR_CA[index])
+#define CAU_XOR_CA_COUNT                         9
+#define CAU_ROTL_CASR_REG(base)                  ((base)->ROTL_CASR)
+#define CAU_ROTL_CAA_REG(base)                   ((base)->ROTL_CAA)
+#define CAU_ROTL_CA_REG(base,index)              ((base)->ROTL_CA[index])
+#define CAU_ROTL_CA_COUNT                        9
+#define CAU_AESC_CASR_REG(base)                  ((base)->AESC_CASR)
+#define CAU_AESC_CAA_REG(base)                   ((base)->AESC_CAA)
+#define CAU_AESC_CA_REG(base,index)              ((base)->AESC_CA[index])
+#define CAU_AESC_CA_COUNT                        9
+#define CAU_AESIC_CASR_REG(base)                 ((base)->AESIC_CASR)
+#define CAU_AESIC_CAA_REG(base)                  ((base)->AESIC_CAA)
+#define CAU_AESIC_CA_REG(base,index)             ((base)->AESIC_CA[index])
+#define CAU_AESIC_CA_COUNT                       9
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/* DIRECT Bit Fields */
+#define CAU_DIRECT_CAU_DIRECT0_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT0_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT0_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT0(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
+#define CAU_DIRECT_CAU_DIRECT1_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT1_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT1_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT1(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
+#define CAU_DIRECT_CAU_DIRECT2_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT2_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT2_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT2(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
+#define CAU_DIRECT_CAU_DIRECT3_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT3_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT3_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT3(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
+#define CAU_DIRECT_CAU_DIRECT4_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT4_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT4_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT4(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
+#define CAU_DIRECT_CAU_DIRECT5_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT5_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT5_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT5(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
+#define CAU_DIRECT_CAU_DIRECT6_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT6_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT6_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT6(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
+#define CAU_DIRECT_CAU_DIRECT7_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT7_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT7_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT7(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
+#define CAU_DIRECT_CAU_DIRECT8_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT8_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT8_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT8(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
+#define CAU_DIRECT_CAU_DIRECT9_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT9_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT9_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT9(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
+#define CAU_DIRECT_CAU_DIRECT10_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT10_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT10_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT10(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
+#define CAU_DIRECT_CAU_DIRECT11_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT11_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT11_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT11(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
+#define CAU_DIRECT_CAU_DIRECT12_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT12_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT12_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT12(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
+#define CAU_DIRECT_CAU_DIRECT13_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT13_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT13_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT13(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
+#define CAU_DIRECT_CAU_DIRECT14_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT14_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT14_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT14(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
+#define CAU_DIRECT_CAU_DIRECT15_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT15_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT15_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT15(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
+/* LDR_CASR Bit Fields */
+#define CAU_LDR_CASR_IC_MASK                     0x1u
+#define CAU_LDR_CASR_IC_SHIFT                    0
+#define CAU_LDR_CASR_IC_WIDTH                    1
+#define CAU_LDR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_IC_SHIFT))&CAU_LDR_CASR_IC_MASK)
+#define CAU_LDR_CASR_DPE_MASK                    0x2u
+#define CAU_LDR_CASR_DPE_SHIFT                   1
+#define CAU_LDR_CASR_DPE_WIDTH                   1
+#define CAU_LDR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_DPE_SHIFT))&CAU_LDR_CASR_DPE_MASK)
+#define CAU_LDR_CASR_VER_MASK                    0xF0000000u
+#define CAU_LDR_CASR_VER_SHIFT                   28
+#define CAU_LDR_CASR_VER_WIDTH                   4
+#define CAU_LDR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
+/* LDR_CAA Bit Fields */
+#define CAU_LDR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_LDR_CAA_ACC_SHIFT                    0
+#define CAU_LDR_CAA_ACC_WIDTH                    32
+#define CAU_LDR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
+/* LDR_CA Bit Fields */
+#define CAU_LDR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA0_SHIFT                     0
+#define CAU_LDR_CA_CA0_WIDTH                     32
+#define CAU_LDR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
+#define CAU_LDR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA1_SHIFT                     0
+#define CAU_LDR_CA_CA1_WIDTH                     32
+#define CAU_LDR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
+#define CAU_LDR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA2_SHIFT                     0
+#define CAU_LDR_CA_CA2_WIDTH                     32
+#define CAU_LDR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
+#define CAU_LDR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA3_SHIFT                     0
+#define CAU_LDR_CA_CA3_WIDTH                     32
+#define CAU_LDR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
+#define CAU_LDR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA4_SHIFT                     0
+#define CAU_LDR_CA_CA4_WIDTH                     32
+#define CAU_LDR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
+#define CAU_LDR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA5_SHIFT                     0
+#define CAU_LDR_CA_CA5_WIDTH                     32
+#define CAU_LDR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
+#define CAU_LDR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA6_SHIFT                     0
+#define CAU_LDR_CA_CA6_WIDTH                     32
+#define CAU_LDR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
+#define CAU_LDR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA7_SHIFT                     0
+#define CAU_LDR_CA_CA7_WIDTH                     32
+#define CAU_LDR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
+#define CAU_LDR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA8_SHIFT                     0
+#define CAU_LDR_CA_CA8_WIDTH                     32
+#define CAU_LDR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
+/* STR_CASR Bit Fields */
+#define CAU_STR_CASR_IC_MASK                     0x1u
+#define CAU_STR_CASR_IC_SHIFT                    0
+#define CAU_STR_CASR_IC_WIDTH                    1
+#define CAU_STR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_IC_SHIFT))&CAU_STR_CASR_IC_MASK)
+#define CAU_STR_CASR_DPE_MASK                    0x2u
+#define CAU_STR_CASR_DPE_SHIFT                   1
+#define CAU_STR_CASR_DPE_WIDTH                   1
+#define CAU_STR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_DPE_SHIFT))&CAU_STR_CASR_DPE_MASK)
+#define CAU_STR_CASR_VER_MASK                    0xF0000000u
+#define CAU_STR_CASR_VER_SHIFT                   28
+#define CAU_STR_CASR_VER_WIDTH                   4
+#define CAU_STR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
+/* STR_CAA Bit Fields */
+#define CAU_STR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_STR_CAA_ACC_SHIFT                    0
+#define CAU_STR_CAA_ACC_WIDTH                    32
+#define CAU_STR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
+/* STR_CA Bit Fields */
+#define CAU_STR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA0_SHIFT                     0
+#define CAU_STR_CA_CA0_WIDTH                     32
+#define CAU_STR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
+#define CAU_STR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA1_SHIFT                     0
+#define CAU_STR_CA_CA1_WIDTH                     32
+#define CAU_STR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
+#define CAU_STR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA2_SHIFT                     0
+#define CAU_STR_CA_CA2_WIDTH                     32
+#define CAU_STR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
+#define CAU_STR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA3_SHIFT                     0
+#define CAU_STR_CA_CA3_WIDTH                     32
+#define CAU_STR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
+#define CAU_STR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA4_SHIFT                     0
+#define CAU_STR_CA_CA4_WIDTH                     32
+#define CAU_STR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
+#define CAU_STR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA5_SHIFT                     0
+#define CAU_STR_CA_CA5_WIDTH                     32
+#define CAU_STR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
+#define CAU_STR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA6_SHIFT                     0
+#define CAU_STR_CA_CA6_WIDTH                     32
+#define CAU_STR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
+#define CAU_STR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA7_SHIFT                     0
+#define CAU_STR_CA_CA7_WIDTH                     32
+#define CAU_STR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
+#define CAU_STR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA8_SHIFT                     0
+#define CAU_STR_CA_CA8_WIDTH                     32
+#define CAU_STR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
+/* ADR_CASR Bit Fields */
+#define CAU_ADR_CASR_IC_MASK                     0x1u
+#define CAU_ADR_CASR_IC_SHIFT                    0
+#define CAU_ADR_CASR_IC_WIDTH                    1
+#define CAU_ADR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_IC_SHIFT))&CAU_ADR_CASR_IC_MASK)
+#define CAU_ADR_CASR_DPE_MASK                    0x2u
+#define CAU_ADR_CASR_DPE_SHIFT                   1
+#define CAU_ADR_CASR_DPE_WIDTH                   1
+#define CAU_ADR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_DPE_SHIFT))&CAU_ADR_CASR_DPE_MASK)
+#define CAU_ADR_CASR_VER_MASK                    0xF0000000u
+#define CAU_ADR_CASR_VER_SHIFT                   28
+#define CAU_ADR_CASR_VER_WIDTH                   4
+#define CAU_ADR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
+/* ADR_CAA Bit Fields */
+#define CAU_ADR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_ADR_CAA_ACC_SHIFT                    0
+#define CAU_ADR_CAA_ACC_WIDTH                    32
+#define CAU_ADR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
+/* ADR_CA Bit Fields */
+#define CAU_ADR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA0_SHIFT                     0
+#define CAU_ADR_CA_CA0_WIDTH                     32
+#define CAU_ADR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
+#define CAU_ADR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA1_SHIFT                     0
+#define CAU_ADR_CA_CA1_WIDTH                     32
+#define CAU_ADR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
+#define CAU_ADR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA2_SHIFT                     0
+#define CAU_ADR_CA_CA2_WIDTH                     32
+#define CAU_ADR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
+#define CAU_ADR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA3_SHIFT                     0
+#define CAU_ADR_CA_CA3_WIDTH                     32
+#define CAU_ADR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
+#define CAU_ADR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA4_SHIFT                     0
+#define CAU_ADR_CA_CA4_WIDTH                     32
+#define CAU_ADR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
+#define CAU_ADR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA5_SHIFT                     0
+#define CAU_ADR_CA_CA5_WIDTH                     32
+#define CAU_ADR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
+#define CAU_ADR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA6_SHIFT                     0
+#define CAU_ADR_CA_CA6_WIDTH                     32
+#define CAU_ADR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
+#define CAU_ADR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA7_SHIFT                     0
+#define CAU_ADR_CA_CA7_WIDTH                     32
+#define CAU_ADR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
+#define CAU_ADR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA8_SHIFT                     0
+#define CAU_ADR_CA_CA8_WIDTH                     32
+#define CAU_ADR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
+/* RADR_CASR Bit Fields */
+#define CAU_RADR_CASR_IC_MASK                    0x1u
+#define CAU_RADR_CASR_IC_SHIFT                   0
+#define CAU_RADR_CASR_IC_WIDTH                   1
+#define CAU_RADR_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_IC_SHIFT))&CAU_RADR_CASR_IC_MASK)
+#define CAU_RADR_CASR_DPE_MASK                   0x2u
+#define CAU_RADR_CASR_DPE_SHIFT                  1
+#define CAU_RADR_CASR_DPE_WIDTH                  1
+#define CAU_RADR_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_DPE_SHIFT))&CAU_RADR_CASR_DPE_MASK)
+#define CAU_RADR_CASR_VER_MASK                   0xF0000000u
+#define CAU_RADR_CASR_VER_SHIFT                  28
+#define CAU_RADR_CASR_VER_WIDTH                  4
+#define CAU_RADR_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
+/* RADR_CAA Bit Fields */
+#define CAU_RADR_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_RADR_CAA_ACC_SHIFT                   0
+#define CAU_RADR_CAA_ACC_WIDTH                   32
+#define CAU_RADR_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
+/* RADR_CA Bit Fields */
+#define CAU_RADR_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA0_SHIFT                    0
+#define CAU_RADR_CA_CA0_WIDTH                    32
+#define CAU_RADR_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
+#define CAU_RADR_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA1_SHIFT                    0
+#define CAU_RADR_CA_CA1_WIDTH                    32
+#define CAU_RADR_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
+#define CAU_RADR_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA2_SHIFT                    0
+#define CAU_RADR_CA_CA2_WIDTH                    32
+#define CAU_RADR_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
+#define CAU_RADR_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA3_SHIFT                    0
+#define CAU_RADR_CA_CA3_WIDTH                    32
+#define CAU_RADR_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
+#define CAU_RADR_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA4_SHIFT                    0
+#define CAU_RADR_CA_CA4_WIDTH                    32
+#define CAU_RADR_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
+#define CAU_RADR_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA5_SHIFT                    0
+#define CAU_RADR_CA_CA5_WIDTH                    32
+#define CAU_RADR_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
+#define CAU_RADR_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA6_SHIFT                    0
+#define CAU_RADR_CA_CA6_WIDTH                    32
+#define CAU_RADR_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
+#define CAU_RADR_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA7_SHIFT                    0
+#define CAU_RADR_CA_CA7_WIDTH                    32
+#define CAU_RADR_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
+#define CAU_RADR_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA8_SHIFT                    0
+#define CAU_RADR_CA_CA8_WIDTH                    32
+#define CAU_RADR_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
+/* XOR_CASR Bit Fields */
+#define CAU_XOR_CASR_IC_MASK                     0x1u
+#define CAU_XOR_CASR_IC_SHIFT                    0
+#define CAU_XOR_CASR_IC_WIDTH                    1
+#define CAU_XOR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_IC_SHIFT))&CAU_XOR_CASR_IC_MASK)
+#define CAU_XOR_CASR_DPE_MASK                    0x2u
+#define CAU_XOR_CASR_DPE_SHIFT                   1
+#define CAU_XOR_CASR_DPE_WIDTH                   1
+#define CAU_XOR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_DPE_SHIFT))&CAU_XOR_CASR_DPE_MASK)
+#define CAU_XOR_CASR_VER_MASK                    0xF0000000u
+#define CAU_XOR_CASR_VER_SHIFT                   28
+#define CAU_XOR_CASR_VER_WIDTH                   4
+#define CAU_XOR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
+/* XOR_CAA Bit Fields */
+#define CAU_XOR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_XOR_CAA_ACC_SHIFT                    0
+#define CAU_XOR_CAA_ACC_WIDTH                    32
+#define CAU_XOR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
+/* XOR_CA Bit Fields */
+#define CAU_XOR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA0_SHIFT                     0
+#define CAU_XOR_CA_CA0_WIDTH                     32
+#define CAU_XOR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
+#define CAU_XOR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA1_SHIFT                     0
+#define CAU_XOR_CA_CA1_WIDTH                     32
+#define CAU_XOR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
+#define CAU_XOR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA2_SHIFT                     0
+#define CAU_XOR_CA_CA2_WIDTH                     32
+#define CAU_XOR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
+#define CAU_XOR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA3_SHIFT                     0
+#define CAU_XOR_CA_CA3_WIDTH                     32
+#define CAU_XOR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
+#define CAU_XOR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA4_SHIFT                     0
+#define CAU_XOR_CA_CA4_WIDTH                     32
+#define CAU_XOR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
+#define CAU_XOR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA5_SHIFT                     0
+#define CAU_XOR_CA_CA5_WIDTH                     32
+#define CAU_XOR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
+#define CAU_XOR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA6_SHIFT                     0
+#define CAU_XOR_CA_CA6_WIDTH                     32
+#define CAU_XOR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
+#define CAU_XOR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA7_SHIFT                     0
+#define CAU_XOR_CA_CA7_WIDTH                     32
+#define CAU_XOR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
+#define CAU_XOR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA8_SHIFT                     0
+#define CAU_XOR_CA_CA8_WIDTH                     32
+#define CAU_XOR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
+/* ROTL_CASR Bit Fields */
+#define CAU_ROTL_CASR_IC_MASK                    0x1u
+#define CAU_ROTL_CASR_IC_SHIFT                   0
+#define CAU_ROTL_CASR_IC_WIDTH                   1
+#define CAU_ROTL_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_IC_SHIFT))&CAU_ROTL_CASR_IC_MASK)
+#define CAU_ROTL_CASR_DPE_MASK                   0x2u
+#define CAU_ROTL_CASR_DPE_SHIFT                  1
+#define CAU_ROTL_CASR_DPE_WIDTH                  1
+#define CAU_ROTL_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_DPE_SHIFT))&CAU_ROTL_CASR_DPE_MASK)
+#define CAU_ROTL_CASR_VER_MASK                   0xF0000000u
+#define CAU_ROTL_CASR_VER_SHIFT                  28
+#define CAU_ROTL_CASR_VER_WIDTH                  4
+#define CAU_ROTL_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
+/* ROTL_CAA Bit Fields */
+#define CAU_ROTL_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_ROTL_CAA_ACC_SHIFT                   0
+#define CAU_ROTL_CAA_ACC_WIDTH                   32
+#define CAU_ROTL_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
+/* ROTL_CA Bit Fields */
+#define CAU_ROTL_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA0_SHIFT                    0
+#define CAU_ROTL_CA_CA0_WIDTH                    32
+#define CAU_ROTL_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
+#define CAU_ROTL_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA1_SHIFT                    0
+#define CAU_ROTL_CA_CA1_WIDTH                    32
+#define CAU_ROTL_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
+#define CAU_ROTL_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA2_SHIFT                    0
+#define CAU_ROTL_CA_CA2_WIDTH                    32
+#define CAU_ROTL_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
+#define CAU_ROTL_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA3_SHIFT                    0
+#define CAU_ROTL_CA_CA3_WIDTH                    32
+#define CAU_ROTL_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
+#define CAU_ROTL_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA4_SHIFT                    0
+#define CAU_ROTL_CA_CA4_WIDTH                    32
+#define CAU_ROTL_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
+#define CAU_ROTL_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA5_SHIFT                    0
+#define CAU_ROTL_CA_CA5_WIDTH                    32
+#define CAU_ROTL_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
+#define CAU_ROTL_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA6_SHIFT                    0
+#define CAU_ROTL_CA_CA6_WIDTH                    32
+#define CAU_ROTL_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
+#define CAU_ROTL_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA7_SHIFT                    0
+#define CAU_ROTL_CA_CA7_WIDTH                    32
+#define CAU_ROTL_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
+#define CAU_ROTL_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA8_SHIFT                    0
+#define CAU_ROTL_CA_CA8_WIDTH                    32
+#define CAU_ROTL_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
+/* AESC_CASR Bit Fields */
+#define CAU_AESC_CASR_IC_MASK                    0x1u
+#define CAU_AESC_CASR_IC_SHIFT                   0
+#define CAU_AESC_CASR_IC_WIDTH                   1
+#define CAU_AESC_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_IC_SHIFT))&CAU_AESC_CASR_IC_MASK)
+#define CAU_AESC_CASR_DPE_MASK                   0x2u
+#define CAU_AESC_CASR_DPE_SHIFT                  1
+#define CAU_AESC_CASR_DPE_WIDTH                  1
+#define CAU_AESC_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_DPE_SHIFT))&CAU_AESC_CASR_DPE_MASK)
+#define CAU_AESC_CASR_VER_MASK                   0xF0000000u
+#define CAU_AESC_CASR_VER_SHIFT                  28
+#define CAU_AESC_CASR_VER_WIDTH                  4
+#define CAU_AESC_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
+/* AESC_CAA Bit Fields */
+#define CAU_AESC_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_AESC_CAA_ACC_SHIFT                   0
+#define CAU_AESC_CAA_ACC_WIDTH                   32
+#define CAU_AESC_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
+/* AESC_CA Bit Fields */
+#define CAU_AESC_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA0_SHIFT                    0
+#define CAU_AESC_CA_CA0_WIDTH                    32
+#define CAU_AESC_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
+#define CAU_AESC_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA1_SHIFT                    0
+#define CAU_AESC_CA_CA1_WIDTH                    32
+#define CAU_AESC_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
+#define CAU_AESC_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA2_SHIFT                    0
+#define CAU_AESC_CA_CA2_WIDTH                    32
+#define CAU_AESC_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
+#define CAU_AESC_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA3_SHIFT                    0
+#define CAU_AESC_CA_CA3_WIDTH                    32
+#define CAU_AESC_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
+#define CAU_AESC_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA4_SHIFT                    0
+#define CAU_AESC_CA_CA4_WIDTH                    32
+#define CAU_AESC_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
+#define CAU_AESC_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA5_SHIFT                    0
+#define CAU_AESC_CA_CA5_WIDTH                    32
+#define CAU_AESC_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
+#define CAU_AESC_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA6_SHIFT                    0
+#define CAU_AESC_CA_CA6_WIDTH                    32
+#define CAU_AESC_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
+#define CAU_AESC_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA7_SHIFT                    0
+#define CAU_AESC_CA_CA7_WIDTH                    32
+#define CAU_AESC_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
+#define CAU_AESC_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA8_SHIFT                    0
+#define CAU_AESC_CA_CA8_WIDTH                    32
+#define CAU_AESC_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
+/* AESIC_CASR Bit Fields */
+#define CAU_AESIC_CASR_IC_MASK                   0x1u
+#define CAU_AESIC_CASR_IC_SHIFT                  0
+#define CAU_AESIC_CASR_IC_WIDTH                  1
+#define CAU_AESIC_CASR_IC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_IC_SHIFT))&CAU_AESIC_CASR_IC_MASK)
+#define CAU_AESIC_CASR_DPE_MASK                  0x2u
+#define CAU_AESIC_CASR_DPE_SHIFT                 1
+#define CAU_AESIC_CASR_DPE_WIDTH                 1
+#define CAU_AESIC_CASR_DPE(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_DPE_SHIFT))&CAU_AESIC_CASR_DPE_MASK)
+#define CAU_AESIC_CASR_VER_MASK                  0xF0000000u
+#define CAU_AESIC_CASR_VER_SHIFT                 28
+#define CAU_AESIC_CASR_VER_WIDTH                 4
+#define CAU_AESIC_CASR_VER(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
+/* AESIC_CAA Bit Fields */
+#define CAU_AESIC_CAA_ACC_MASK                   0xFFFFFFFFu
+#define CAU_AESIC_CAA_ACC_SHIFT                  0
+#define CAU_AESIC_CAA_ACC_WIDTH                  32
+#define CAU_AESIC_CAA_ACC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
+/* AESIC_CA Bit Fields */
+#define CAU_AESIC_CA_CA0_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA0_SHIFT                   0
+#define CAU_AESIC_CA_CA0_WIDTH                   32
+#define CAU_AESIC_CA_CA0(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
+#define CAU_AESIC_CA_CA1_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA1_SHIFT                   0
+#define CAU_AESIC_CA_CA1_WIDTH                   32
+#define CAU_AESIC_CA_CA1(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
+#define CAU_AESIC_CA_CA2_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA2_SHIFT                   0
+#define CAU_AESIC_CA_CA2_WIDTH                   32
+#define CAU_AESIC_CA_CA2(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
+#define CAU_AESIC_CA_CA3_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA3_SHIFT                   0
+#define CAU_AESIC_CA_CA3_WIDTH                   32
+#define CAU_AESIC_CA_CA3(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
+#define CAU_AESIC_CA_CA4_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA4_SHIFT                   0
+#define CAU_AESIC_CA_CA4_WIDTH                   32
+#define CAU_AESIC_CA_CA4(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
+#define CAU_AESIC_CA_CA5_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA5_SHIFT                   0
+#define CAU_AESIC_CA_CA5_WIDTH                   32
+#define CAU_AESIC_CA_CA5(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
+#define CAU_AESIC_CA_CA6_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA6_SHIFT                   0
+#define CAU_AESIC_CA_CA6_WIDTH                   32
+#define CAU_AESIC_CA_CA6(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
+#define CAU_AESIC_CA_CA7_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA7_SHIFT                   0
+#define CAU_AESIC_CA_CA7_WIDTH                   32
+#define CAU_AESIC_CA_CA7(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
+#define CAU_AESIC_CA_CA8_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA8_SHIFT                   0
+#define CAU_AESIC_CA_CA8_WIDTH                   32
+#define CAU_AESIC_CA_CA8(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+/** Peripheral CAU base address */
+#define CAU_BASE                                 (0xE0081000u)
+/** Peripheral CAU base pointer */
+#define CAU                                      ((CAU_Type *)CAU_BASE)
+#define CAU_BASE_PTR                             (CAU)
+/** Array initializer of CAU peripheral base addresses */
+#define CAU_BASE_ADDRS                           { CAU_BASE }
+/** Array initializer of CAU peripheral base pointers */
+#define CAU_BASE_PTRS                            { CAU }
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register instance definitions */
+/* CAU */
+#define CAU_DIRECT0                              CAU_DIRECT_REG(CAU,0)
+#define CAU_DIRECT1                              CAU_DIRECT_REG(CAU,1)
+#define CAU_DIRECT2                              CAU_DIRECT_REG(CAU,2)
+#define CAU_DIRECT3                              CAU_DIRECT_REG(CAU,3)
+#define CAU_DIRECT4                              CAU_DIRECT_REG(CAU,4)
+#define CAU_DIRECT5                              CAU_DIRECT_REG(CAU,5)
+#define CAU_DIRECT6                              CAU_DIRECT_REG(CAU,6)
+#define CAU_DIRECT7                              CAU_DIRECT_REG(CAU,7)
+#define CAU_DIRECT8                              CAU_DIRECT_REG(CAU,8)
+#define CAU_DIRECT9                              CAU_DIRECT_REG(CAU,9)
+#define CAU_DIRECT10                             CAU_DIRECT_REG(CAU,10)
+#define CAU_DIRECT11                             CAU_DIRECT_REG(CAU,11)
+#define CAU_DIRECT12                             CAU_DIRECT_REG(CAU,12)
+#define CAU_DIRECT13                             CAU_DIRECT_REG(CAU,13)
+#define CAU_DIRECT14                             CAU_DIRECT_REG(CAU,14)
+#define CAU_DIRECT15                             CAU_DIRECT_REG(CAU,15)
+#define CAU_LDR_CASR                             CAU_LDR_CASR_REG(CAU)
+#define CAU_LDR_CAA                              CAU_LDR_CAA_REG(CAU)
+#define CAU_LDR_CA0                              CAU_LDR_CA_REG(CAU,0)
+#define CAU_LDR_CA1                              CAU_LDR_CA_REG(CAU,1)
+#define CAU_LDR_CA2                              CAU_LDR_CA_REG(CAU,2)
+#define CAU_LDR_CA3                              CAU_LDR_CA_REG(CAU,3)
+#define CAU_LDR_CA4                              CAU_LDR_CA_REG(CAU,4)
+#define CAU_LDR_CA5                              CAU_LDR_CA_REG(CAU,5)
+#define CAU_LDR_CA6                              CAU_LDR_CA_REG(CAU,6)
+#define CAU_LDR_CA7                              CAU_LDR_CA_REG(CAU,7)
+#define CAU_LDR_CA8                              CAU_LDR_CA_REG(CAU,8)
+#define CAU_STR_CASR                             CAU_STR_CASR_REG(CAU)
+#define CAU_STR_CAA                              CAU_STR_CAA_REG(CAU)
+#define CAU_STR_CA0                              CAU_STR_CA_REG(CAU,0)
+#define CAU_STR_CA1                              CAU_STR_CA_REG(CAU,1)
+#define CAU_STR_CA2                              CAU_STR_CA_REG(CAU,2)
+#define CAU_STR_CA3                              CAU_STR_CA_REG(CAU,3)
+#define CAU_STR_CA4                              CAU_STR_CA_REG(CAU,4)
+#define CAU_STR_CA5                              CAU_STR_CA_REG(CAU,5)
+#define CAU_STR_CA6                              CAU_STR_CA_REG(CAU,6)
+#define CAU_STR_CA7                              CAU_STR_CA_REG(CAU,7)
+#define CAU_STR_CA8                              CAU_STR_CA_REG(CAU,8)
+#define CAU_ADR_CASR                             CAU_ADR_CASR_REG(CAU)
+#define CAU_ADR_CAA                              CAU_ADR_CAA_REG(CAU)
+#define CAU_ADR_CA0                              CAU_ADR_CA_REG(CAU,0)
+#define CAU_ADR_CA1                              CAU_ADR_CA_REG(CAU,1)
+#define CAU_ADR_CA2                              CAU_ADR_CA_REG(CAU,2)
+#define CAU_ADR_CA3                              CAU_ADR_CA_REG(CAU,3)
+#define CAU_ADR_CA4                              CAU_ADR_CA_REG(CAU,4)
+#define CAU_ADR_CA5                              CAU_ADR_CA_REG(CAU,5)
+#define CAU_ADR_CA6                              CAU_ADR_CA_REG(CAU,6)
+#define CAU_ADR_CA7                              CAU_ADR_CA_REG(CAU,7)
+#define CAU_ADR_CA8                              CAU_ADR_CA_REG(CAU,8)
+#define CAU_RADR_CASR                            CAU_RADR_CASR_REG(CAU)
+#define CAU_RADR_CAA                             CAU_RADR_CAA_REG(CAU)
+#define CAU_RADR_CA0                             CAU_RADR_CA_REG(CAU,0)
+#define CAU_RADR_CA1                             CAU_RADR_CA_REG(CAU,1)
+#define CAU_RADR_CA2                             CAU_RADR_CA_REG(CAU,2)
+#define CAU_RADR_CA3                             CAU_RADR_CA_REG(CAU,3)
+#define CAU_RADR_CA4                             CAU_RADR_CA_REG(CAU,4)
+#define CAU_RADR_CA5                             CAU_RADR_CA_REG(CAU,5)
+#define CAU_RADR_CA6                             CAU_RADR_CA_REG(CAU,6)
+#define CAU_RADR_CA7                             CAU_RADR_CA_REG(CAU,7)
+#define CAU_RADR_CA8                             CAU_RADR_CA_REG(CAU,8)
+#define CAU_XOR_CASR                             CAU_XOR_CASR_REG(CAU)
+#define CAU_XOR_CAA                              CAU_XOR_CAA_REG(CAU)
+#define CAU_XOR_CA0                              CAU_XOR_CA_REG(CAU,0)
+#define CAU_XOR_CA1                              CAU_XOR_CA_REG(CAU,1)
+#define CAU_XOR_CA2                              CAU_XOR_CA_REG(CAU,2)
+#define CAU_XOR_CA3                              CAU_XOR_CA_REG(CAU,3)
+#define CAU_XOR_CA4                              CAU_XOR_CA_REG(CAU,4)
+#define CAU_XOR_CA5                              CAU_XOR_CA_REG(CAU,5)
+#define CAU_XOR_CA6                              CAU_XOR_CA_REG(CAU,6)
+#define CAU_XOR_CA7                              CAU_XOR_CA_REG(CAU,7)
+#define CAU_XOR_CA8                              CAU_XOR_CA_REG(CAU,8)
+#define CAU_ROTL_CASR                            CAU_ROTL_CASR_REG(CAU)
+#define CAU_ROTL_CAA                             CAU_ROTL_CAA_REG(CAU)
+#define CAU_ROTL_CA0                             CAU_ROTL_CA_REG(CAU,0)
+#define CAU_ROTL_CA1                             CAU_ROTL_CA_REG(CAU,1)
+#define CAU_ROTL_CA2                             CAU_ROTL_CA_REG(CAU,2)
+#define CAU_ROTL_CA3                             CAU_ROTL_CA_REG(CAU,3)
+#define CAU_ROTL_CA4                             CAU_ROTL_CA_REG(CAU,4)
+#define CAU_ROTL_CA5                             CAU_ROTL_CA_REG(CAU,5)
+#define CAU_ROTL_CA6                             CAU_ROTL_CA_REG(CAU,6)
+#define CAU_ROTL_CA7                             CAU_ROTL_CA_REG(CAU,7)
+#define CAU_ROTL_CA8                             CAU_ROTL_CA_REG(CAU,8)
+#define CAU_AESC_CASR                            CAU_AESC_CASR_REG(CAU)
+#define CAU_AESC_CAA                             CAU_AESC_CAA_REG(CAU)
+#define CAU_AESC_CA0                             CAU_AESC_CA_REG(CAU,0)
+#define CAU_AESC_CA1                             CAU_AESC_CA_REG(CAU,1)
+#define CAU_AESC_CA2                             CAU_AESC_CA_REG(CAU,2)
+#define CAU_AESC_CA3                             CAU_AESC_CA_REG(CAU,3)
+#define CAU_AESC_CA4                             CAU_AESC_CA_REG(CAU,4)
+#define CAU_AESC_CA5                             CAU_AESC_CA_REG(CAU,5)
+#define CAU_AESC_CA6                             CAU_AESC_CA_REG(CAU,6)
+#define CAU_AESC_CA7                             CAU_AESC_CA_REG(CAU,7)
+#define CAU_AESC_CA8                             CAU_AESC_CA_REG(CAU,8)
+#define CAU_AESIC_CASR                           CAU_AESIC_CASR_REG(CAU)
+#define CAU_AESIC_CAA                            CAU_AESIC_CAA_REG(CAU)
+#define CAU_AESIC_CA0                            CAU_AESIC_CA_REG(CAU,0)
+#define CAU_AESIC_CA1                            CAU_AESIC_CA_REG(CAU,1)
+#define CAU_AESIC_CA2                            CAU_AESIC_CA_REG(CAU,2)
+#define CAU_AESIC_CA3                            CAU_AESIC_CA_REG(CAU,3)
+#define CAU_AESIC_CA4                            CAU_AESIC_CA_REG(CAU,4)
+#define CAU_AESIC_CA5                            CAU_AESIC_CA_REG(CAU,5)
+#define CAU_AESIC_CA6                            CAU_AESIC_CA_REG(CAU,6)
+#define CAU_AESIC_CA7                            CAU_AESIC_CA_REG(CAU,7)
+#define CAU_AESIC_CA8                            CAU_AESIC_CA_REG(CAU,8)
+
+/* CAU - Register array accessors */
+#define CAU_DIRECT(index)                        CAU_DIRECT_REG(CAU,index)
+#define CAU_LDR_CA(index)                        CAU_LDR_CA_REG(CAU,index)
+#define CAU_STR_CA(index)                        CAU_STR_CA_REG(CAU,index)
+#define CAU_ADR_CA(index)                        CAU_ADR_CA_REG(CAU,index)
+#define CAU_RADR_CA(index)                       CAU_RADR_CA_REG(CAU,index)
+#define CAU_XOR_CA(index)                        CAU_XOR_CA_REG(CAU,index)
+#define CAU_ROTL_CA(index)                       CAU_ROTL_CA_REG(CAU,index)
+#define CAU_AESC_CA(index)                       CAU_AESC_CA_REG(CAU,index)
+#define CAU_AESIC_CA(index)                      CAU_AESIC_CA_REG(CAU,index)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base)                        ((base)->CR0)
+#define CMP_CR1_REG(base)                        ((base)->CR1)
+#define CMP_FPR_REG(base)                        ((base)->FPR)
+#define CMP_SCR_REG(base)                        ((base)->SCR)
+#define CMP_DACCR_REG(base)                      ((base)->DACCR)
+#define CMP_MUXCR_REG(base)                      ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK                     0x3u
+#define CMP_CR0_HYSTCTR_SHIFT                    0
+#define CMP_CR0_HYSTCTR_WIDTH                    2
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT                 4
+#define CMP_CR0_FILTER_CNT_WIDTH                 3
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK                          0x1u
+#define CMP_CR1_EN_SHIFT                         0
+#define CMP_CR1_EN_WIDTH                         1
+#define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK                         0x2u
+#define CMP_CR1_OPE_SHIFT                        1
+#define CMP_CR1_OPE_WIDTH                        1
+#define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK                         0x4u
+#define CMP_CR1_COS_SHIFT                        2
+#define CMP_CR1_COS_WIDTH                        1
+#define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK                         0x8u
+#define CMP_CR1_INV_SHIFT                        3
+#define CMP_CR1_INV_WIDTH                        1
+#define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK                       0x10u
+#define CMP_CR1_PMODE_SHIFT                      4
+#define CMP_CR1_PMODE_WIDTH                      1
+#define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
+#define CMP_CR1_WE_MASK                          0x40u
+#define CMP_CR1_WE_SHIFT                         6
+#define CMP_CR1_WE_WIDTH                         1
+#define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK                          0x80u
+#define CMP_CR1_SE_SHIFT                         7
+#define CMP_CR1_SE_WIDTH                         1
+#define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK                    0xFFu
+#define CMP_FPR_FILT_PER_SHIFT                   0
+#define CMP_FPR_FILT_PER_WIDTH                   8
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK                        0x1u
+#define CMP_SCR_COUT_SHIFT                       0
+#define CMP_SCR_COUT_WIDTH                       1
+#define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK                         0x2u
+#define CMP_SCR_CFF_SHIFT                        1
+#define CMP_SCR_CFF_WIDTH                        1
+#define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK                         0x4u
+#define CMP_SCR_CFR_SHIFT                        2
+#define CMP_SCR_CFR_WIDTH                        1
+#define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK                         0x8u
+#define CMP_SCR_IEF_SHIFT                        3
+#define CMP_SCR_IEF_WIDTH                        1
+#define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK                         0x10u
+#define CMP_SCR_IER_SHIFT                        4
+#define CMP_SCR_IER_WIDTH                        1
+#define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK                       0x40u
+#define CMP_SCR_DMAEN_SHIFT                      6
+#define CMP_SCR_DMAEN_WIDTH                      1
+#define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK                     0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT                    0
+#define CMP_DACCR_VOSEL_WIDTH                    6
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     0x40u
+#define CMP_DACCR_VRSEL_SHIFT                    6
+#define CMP_DACCR_VRSEL_WIDTH                    1
+#define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK                     0x80u
+#define CMP_DACCR_DACEN_SHIFT                    7
+#define CMP_DACCR_DACEN_WIDTH                    1
+#define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK                      0x7u
+#define CMP_MUXCR_MSEL_SHIFT                     0
+#define CMP_MUXCR_MSEL_WIDTH                     3
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      0x38u
+#define CMP_MUXCR_PSEL_SHIFT                     3
+#define CMP_MUXCR_PSEL_WIDTH                     3
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK                      0x80u
+#define CMP_MUXCR_PSTM_SHIFT                     7
+#define CMP_MUXCR_PSTM_WIDTH                     1
+#define CMP_MUXCR_PSTM(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSTM_SHIFT))&CMP_MUXCR_PSTM_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR                            (CMP0)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE                                (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1                                     ((CMP_Type *)CMP1_BASE)
+#define CMP1_BASE_PTR                            (CMP1)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE                                (0x40073010u)
+/** Peripheral CMP2 base pointer */
+#define CMP2                                     ((CMP_Type *)CMP2_BASE)
+#define CMP2_BASE_PTR                            (CMP2)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS                           { CMP0_BASE, CMP1_BASE, CMP2_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS                            { CMP0, CMP1, CMP2 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0                                 CMP_CR0_REG(CMP0)
+#define CMP0_CR1                                 CMP_CR1_REG(CMP0)
+#define CMP0_FPR                                 CMP_FPR_REG(CMP0)
+#define CMP0_SCR                                 CMP_SCR_REG(CMP0)
+#define CMP0_DACCR                               CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR                               CMP_MUXCR_REG(CMP0)
+/* CMP1 */
+#define CMP1_CR0                                 CMP_CR0_REG(CMP1)
+#define CMP1_CR1                                 CMP_CR1_REG(CMP1)
+#define CMP1_FPR                                 CMP_FPR_REG(CMP1)
+#define CMP1_SCR                                 CMP_SCR_REG(CMP1)
+#define CMP1_DACCR                               CMP_DACCR_REG(CMP1)
+#define CMP1_MUXCR                               CMP_MUXCR_REG(CMP1)
+/* CMP2 */
+#define CMP2_CR0                                 CMP_CR0_REG(CMP2)
+#define CMP2_CR1                                 CMP_CR1_REG(CMP2)
+#define CMP2_FPR                                 CMP_FPR_REG(CMP2)
+#define CMP2_SCR                                 CMP_SCR_REG(CMP2)
+#define CMP2_DACCR                               CMP_DACCR_REG(CMP2)
+#define CMP2_MUXCR                               CMP_MUXCR_REG(CMP2)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CGH1;                               /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+  __IO uint8_t CGL1;                               /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+  __IO uint8_t CGH2;                               /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+  __IO uint8_t CGL2;                               /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+  __IO uint8_t OC;                                 /**< CMT Output Control Register, offset: 0x4 */
+  __IO uint8_t MSC;                                /**< CMT Modulator Status and Control Register, offset: 0x5 */
+  __IO uint8_t CMD1;                               /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+  __IO uint8_t CMD2;                               /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+  __IO uint8_t CMD3;                               /**< CMT Modulator Data Register Space High, offset: 0x8 */
+  __IO uint8_t CMD4;                               /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+  __IO uint8_t PPS;                                /**< CMT Primary Prescaler Register, offset: 0xA */
+  __IO uint8_t DMA;                                /**< CMT Direct Memory Access Register, offset: 0xB */
+} CMT_Type, *CMT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register accessors */
+#define CMT_CGH1_REG(base)                       ((base)->CGH1)
+#define CMT_CGL1_REG(base)                       ((base)->CGL1)
+#define CMT_CGH2_REG(base)                       ((base)->CGH2)
+#define CMT_CGL2_REG(base)                       ((base)->CGL2)
+#define CMT_OC_REG(base)                         ((base)->OC)
+#define CMT_MSC_REG(base)                        ((base)->MSC)
+#define CMT_CMD1_REG(base)                       ((base)->CMD1)
+#define CMT_CMD2_REG(base)                       ((base)->CMD2)
+#define CMT_CMD3_REG(base)                       ((base)->CMD3)
+#define CMT_CMD4_REG(base)                       ((base)->CMD4)
+#define CMT_PPS_REG(base)                        ((base)->PPS)
+#define CMT_DMA_REG(base)                        ((base)->DMA)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK                         0xFFu
+#define CMT_CGH1_PH_SHIFT                        0
+#define CMT_CGH1_PH_WIDTH                        8
+#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK                         0xFFu
+#define CMT_CGL1_PL_SHIFT                        0
+#define CMT_CGL1_PL_WIDTH                        8
+#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK                         0xFFu
+#define CMT_CGH2_SH_SHIFT                        0
+#define CMT_CGH2_SH_WIDTH                        8
+#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK                         0xFFu
+#define CMT_CGL2_SL_SHIFT                        0
+#define CMT_CGL2_SL_WIDTH                        8
+#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK                       0x20u
+#define CMT_OC_IROPEN_SHIFT                      5
+#define CMT_OC_IROPEN_WIDTH                      1
+#define CMT_OC_IROPEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROPEN_SHIFT))&CMT_OC_IROPEN_MASK)
+#define CMT_OC_CMTPOL_MASK                       0x40u
+#define CMT_OC_CMTPOL_SHIFT                      6
+#define CMT_OC_CMTPOL_WIDTH                      1
+#define CMT_OC_CMTPOL(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_OC_CMTPOL_SHIFT))&CMT_OC_CMTPOL_MASK)
+#define CMT_OC_IROL_MASK                         0x80u
+#define CMT_OC_IROL_SHIFT                        7
+#define CMT_OC_IROL_WIDTH                        1
+#define CMT_OC_IROL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROL_SHIFT))&CMT_OC_IROL_MASK)
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK                       0x1u
+#define CMT_MSC_MCGEN_SHIFT                      0
+#define CMT_MSC_MCGEN_WIDTH                      1
+#define CMT_MSC_MCGEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_MCGEN_SHIFT))&CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_EOCIE_MASK                       0x2u
+#define CMT_MSC_EOCIE_SHIFT                      1
+#define CMT_MSC_EOCIE_WIDTH                      1
+#define CMT_MSC_EOCIE(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCIE_SHIFT))&CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_FSK_MASK                         0x4u
+#define CMT_MSC_FSK_SHIFT                        2
+#define CMT_MSC_FSK_WIDTH                        1
+#define CMT_MSC_FSK(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_MSC_FSK_SHIFT))&CMT_MSC_FSK_MASK)
+#define CMT_MSC_BASE_MASK                        0x8u
+#define CMT_MSC_BASE_SHIFT                       3
+#define CMT_MSC_BASE_WIDTH                       1
+#define CMT_MSC_BASE(x)                          (((uint8_t)(((uint8_t)(x))<<CMT_MSC_BASE_SHIFT))&CMT_MSC_BASE_MASK)
+#define CMT_MSC_EXSPC_MASK                       0x10u
+#define CMT_MSC_EXSPC_SHIFT                      4
+#define CMT_MSC_EXSPC_WIDTH                      1
+#define CMT_MSC_EXSPC(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EXSPC_SHIFT))&CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_CMTDIV_MASK                      0x60u
+#define CMT_MSC_CMTDIV_SHIFT                     5
+#define CMT_MSC_CMTDIV_WIDTH                     2
+#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK                        0x80u
+#define CMT_MSC_EOCF_SHIFT                       7
+#define CMT_MSC_EOCF_WIDTH                       1
+#define CMT_MSC_EOCF(x)                          (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCF_SHIFT))&CMT_MSC_EOCF_MASK)
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK                         0xFFu
+#define CMT_CMD1_MB_SHIFT                        0
+#define CMT_CMD1_MB_WIDTH                        8
+#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK                         0xFFu
+#define CMT_CMD2_MB_SHIFT                        0
+#define CMT_CMD2_MB_WIDTH                        8
+#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK                         0xFFu
+#define CMT_CMD3_SB_SHIFT                        0
+#define CMT_CMD3_SB_WIDTH                        8
+#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK                         0xFFu
+#define CMT_CMD4_SB_SHIFT                        0
+#define CMT_CMD4_SB_WIDTH                        8
+#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK                      0xFu
+#define CMT_PPS_PPSDIV_SHIFT                     0
+#define CMT_PPS_PPSDIV_WIDTH                     4
+#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK                         0x1u
+#define CMT_DMA_DMA_SHIFT                        0
+#define CMT_DMA_DMA_WIDTH                        1
+#define CMT_DMA_DMA(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_DMA_DMA_SHIFT))&CMT_DMA_DMA_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE                                 (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT                                      ((CMT_Type *)CMT_BASE)
+#define CMT_BASE_PTR                             (CMT)
+/** Array initializer of CMT peripheral base addresses */
+#define CMT_BASE_ADDRS                           { CMT_BASE }
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASE_PTRS                            { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS                                 { CMT_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register instance definitions */
+/* CMT */
+#define CMT_CGH1                                 CMT_CGH1_REG(CMT)
+#define CMT_CGL1                                 CMT_CGL1_REG(CMT)
+#define CMT_CGH2                                 CMT_CGH2_REG(CMT)
+#define CMT_CGL2                                 CMT_CGL2_REG(CMT)
+#define CMT_OC                                   CMT_OC_REG(CMT)
+#define CMT_MSC                                  CMT_MSC_REG(CMT)
+#define CMT_CMD1                                 CMT_CMD1_REG(CMT)
+#define CMT_CMD2                                 CMT_CMD2_REG(CMT)
+#define CMT_CMD3                                 CMT_CMD3_REG(CMT)
+#define CMT_CMD4                                 CMT_CMD4_REG(CMT)
+#define CMT_PPS                                  CMT_PPS_REG(CMT)
+#define CMT_DMA                                  CMT_DMA_REG(CMT)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type, *CRC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register accessors */
+#define CRC_DATAL_REG(base)                      ((base)->ACCESS16BIT.DATAL)
+#define CRC_DATAH_REG(base)                      ((base)->ACCESS16BIT.DATAH)
+#define CRC_DATA_REG(base)                       ((base)->DATA)
+#define CRC_DATALL_REG(base)                     ((base)->ACCESS8BIT.DATALL)
+#define CRC_DATALU_REG(base)                     ((base)->ACCESS8BIT.DATALU)
+#define CRC_DATAHL_REG(base)                     ((base)->ACCESS8BIT.DATAHL)
+#define CRC_DATAHU_REG(base)                     ((base)->ACCESS8BIT.DATAHU)
+#define CRC_GPOLYL_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYL)
+#define CRC_GPOLYH_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYH)
+#define CRC_GPOLY_REG(base)                      ((base)->GPOLY)
+#define CRC_GPOLYLL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
+#define CRC_GPOLYLU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
+#define CRC_GPOLYHL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
+#define CRC_GPOLYHU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
+#define CRC_CTRL_REG(base)                       ((base)->CTRL)
+#define CRC_CTRLHU_REG(base)                     ((base)->CTRL_ACCESS8BIT.CTRLHU)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK                     0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT                    0
+#define CRC_DATAL_DATAL_WIDTH                    16
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK                     0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT                    0
+#define CRC_DATAH_DATAH_WIDTH                    16
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK                         0xFFu
+#define CRC_DATA_LL_SHIFT                        0
+#define CRC_DATA_LL_WIDTH                        8
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         0xFF00u
+#define CRC_DATA_LU_SHIFT                        8
+#define CRC_DATA_LU_WIDTH                        8
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         0xFF0000u
+#define CRC_DATA_HL_SHIFT                        16
+#define CRC_DATA_HL_WIDTH                        8
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         0xFF000000u
+#define CRC_DATA_HU_SHIFT                        24
+#define CRC_DATA_HU_WIDTH                        8
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK                   0xFFu
+#define CRC_DATALL_DATALL_SHIFT                  0
+#define CRC_DATALL_DATALL_WIDTH                  8
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK                   0xFFu
+#define CRC_DATALU_DATALU_SHIFT                  0
+#define CRC_DATALU_DATALU_WIDTH                  8
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK                   0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT                  0
+#define CRC_DATAHL_DATAHL_WIDTH                  8
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK                   0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT                  0
+#define CRC_DATAHU_DATAHU_WIDTH                  8
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT                  0
+#define CRC_GPOLYL_GPOLYL_WIDTH                  16
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT                  0
+#define CRC_GPOLYH_GPOLYH_WIDTH                  16
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK                       0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT                      0
+#define CRC_GPOLY_LOW_WIDTH                      16
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT                     16
+#define CRC_GPOLY_HIGH_WIDTH                     16
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                0
+#define CRC_GPOLYLL_GPOLYLL_WIDTH                8
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                0
+#define CRC_GPOLYLU_GPOLYLU_WIDTH                8
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                0
+#define CRC_GPOLYHL_GPOLYHL_WIDTH                8
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                0
+#define CRC_GPOLYHU_GPOLYHU_WIDTH                8
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK                       0x1000000u
+#define CRC_CTRL_TCRC_SHIFT                      24
+#define CRC_CTRL_TCRC_WIDTH                      1
+#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK                        0x2000000u
+#define CRC_CTRL_WAS_SHIFT                       25
+#define CRC_CTRL_WAS_WIDTH                       1
+#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK                       0x4000000u
+#define CRC_CTRL_FXOR_SHIFT                      26
+#define CRC_CTRL_FXOR_WIDTH                      1
+#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK                       0x30000000u
+#define CRC_CTRL_TOTR_SHIFT                      28
+#define CRC_CTRL_TOTR_WIDTH                      2
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        0xC0000000u
+#define CRC_CTRL_TOT_SHIFT                       30
+#define CRC_CTRL_TOT_WIDTH                       2
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK                     0x1u
+#define CRC_CTRLHU_TCRC_SHIFT                    0
+#define CRC_CTRLHU_TCRC_WIDTH                    1
+#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TCRC_SHIFT))&CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK                      0x2u
+#define CRC_CTRLHU_WAS_SHIFT                     1
+#define CRC_CTRLHU_WAS_WIDTH                     1
+#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_WAS_SHIFT))&CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK                     0x4u
+#define CRC_CTRLHU_FXOR_SHIFT                    2
+#define CRC_CTRLHU_FXOR_WIDTH                    1
+#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_FXOR_SHIFT))&CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK                     0x30u
+#define CRC_CTRLHU_TOTR_SHIFT                    4
+#define CRC_CTRLHU_TOTR_WIDTH                    2
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      0xC0u
+#define CRC_CTRLHU_TOT_SHIFT                     6
+#define CRC_CTRLHU_TOT_WIDTH                     2
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+#define CRC_BASE_PTR                             (CRC0)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register instance definitions */
+/* CRC */
+#define CRC_DATA                                 CRC_DATA_REG(CRC0)
+#define CRC_DATAL                                CRC_DATAL_REG(CRC0)
+#define CRC_DATALL                               CRC_DATALL_REG(CRC0)
+#define CRC_DATALU                               CRC_DATALU_REG(CRC0)
+#define CRC_DATAH                                CRC_DATAH_REG(CRC0)
+#define CRC_DATAHL                               CRC_DATAHL_REG(CRC0)
+#define CRC_DATAHU                               CRC_DATAHU_REG(CRC0)
+#define CRC_GPOLY                                CRC_GPOLY_REG(CRC0)
+#define CRC_GPOLYL                               CRC_GPOLYL_REG(CRC0)
+#define CRC_GPOLYLL                              CRC_GPOLYLL_REG(CRC0)
+#define CRC_GPOLYLU                              CRC_GPOLYLU_REG(CRC0)
+#define CRC_GPOLYH                               CRC_GPOLYH_REG(CRC0)
+#define CRC_GPOLYHL                              CRC_GPOLYHL_REG(CRC0)
+#define CRC_GPOLYHU                              CRC_GPOLYHU_REG(CRC0)
+#define CRC_CTRL                                 CRC_CTRL_REG(CRC0)
+#define CRC_CTRLHU                               CRC_CTRLHU_REG(CRC0)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[16];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index)                 ((base)->DAT[index].DATL)
+#define DAC_DATL_COUNT                           16
+#define DAC_DATH_REG(base,index)                 ((base)->DAT[index].DATH)
+#define DAC_DATH_COUNT                           16
+#define DAC_SR_REG(base)                         ((base)->SR)
+#define DAC_C0_REG(base)                         ((base)->C0)
+#define DAC_C1_REG(base)                         ((base)->C1)
+#define DAC_C2_REG(base)                         ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK                      0xFFu
+#define DAC_DATL_DATA0_SHIFT                     0
+#define DAC_DATL_DATA0_WIDTH                     8
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK                      0xFu
+#define DAC_DATH_DATA1_SHIFT                     0
+#define DAC_DATH_DATA1_WIDTH                     4
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK                    0x1u
+#define DAC_SR_DACBFRPBF_SHIFT                   0
+#define DAC_SR_DACBFRPBF_WIDTH                   1
+#define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK                    0x2u
+#define DAC_SR_DACBFRPTF_SHIFT                   1
+#define DAC_SR_DACBFRPTF_WIDTH                   1
+#define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK                     0x4u
+#define DAC_SR_DACBFWMF_SHIFT                    2
+#define DAC_SR_DACBFWMF_WIDTH                    1
+#define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFWMF_SHIFT))&DAC_SR_DACBFWMF_MASK)
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK                     0x1u
+#define DAC_C0_DACBBIEN_SHIFT                    0
+#define DAC_C0_DACBBIEN_WIDTH                    1
+#define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK                     0x2u
+#define DAC_C0_DACBTIEN_SHIFT                    1
+#define DAC_C0_DACBTIEN_WIDTH                    1
+#define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK                     0x4u
+#define DAC_C0_DACBWIEN_SHIFT                    2
+#define DAC_C0_DACBWIEN_WIDTH                    1
+#define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBWIEN_SHIFT))&DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK                         0x8u
+#define DAC_C0_LPEN_SHIFT                        3
+#define DAC_C0_LPEN_WIDTH                        1
+#define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK                     0x10u
+#define DAC_C0_DACSWTRG_SHIFT                    4
+#define DAC_C0_DACSWTRG_WIDTH                    1
+#define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK                    0x20u
+#define DAC_C0_DACTRGSEL_SHIFT                   5
+#define DAC_C0_DACTRGSEL_WIDTH                   1
+#define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK                       0x40u
+#define DAC_C0_DACRFS_SHIFT                      6
+#define DAC_C0_DACRFS_WIDTH                      1
+#define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK                        0x80u
+#define DAC_C0_DACEN_SHIFT                       7
+#define DAC_C0_DACEN_WIDTH                       1
+#define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK                      0x1u
+#define DAC_C1_DACBFEN_SHIFT                     0
+#define DAC_C1_DACBFEN_WIDTH                     1
+#define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK                      0x6u
+#define DAC_C1_DACBFMD_SHIFT                     1
+#define DAC_C1_DACBFMD_WIDTH                     2
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK                      0x18u
+#define DAC_C1_DACBFWM_SHIFT                     3
+#define DAC_C1_DACBFWM_WIDTH                     2
+#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK                        0x80u
+#define DAC_C1_DMAEN_SHIFT                       7
+#define DAC_C1_DMAEN_WIDTH                       1
+#define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK                      0xFu
+#define DAC_C2_DACBFUP_SHIFT                     0
+#define DAC_C2_DACBFUP_WIDTH                     4
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      0xF0u
+#define DAC_C2_DACBFRP_SHIFT                     4
+#define DAC_C2_DACBFRP_WIDTH                     4
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR                            (DAC0)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE                                (0x400CD000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1                                     ((DAC_Type *)DAC1_BASE)
+#define DAC1_BASE_PTR                            (DAC1)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS                           { DAC0_BASE, DAC1_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS                            { DAC0, DAC1 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn, DAC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L                               DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H                               DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L                               DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H                               DAC_DATH_REG(DAC0,1)
+#define DAC0_DAT2L                               DAC_DATL_REG(DAC0,2)
+#define DAC0_DAT2H                               DAC_DATH_REG(DAC0,2)
+#define DAC0_DAT3L                               DAC_DATL_REG(DAC0,3)
+#define DAC0_DAT3H                               DAC_DATH_REG(DAC0,3)
+#define DAC0_DAT4L                               DAC_DATL_REG(DAC0,4)
+#define DAC0_DAT4H                               DAC_DATH_REG(DAC0,4)
+#define DAC0_DAT5L                               DAC_DATL_REG(DAC0,5)
+#define DAC0_DAT5H                               DAC_DATH_REG(DAC0,5)
+#define DAC0_DAT6L                               DAC_DATL_REG(DAC0,6)
+#define DAC0_DAT6H                               DAC_DATH_REG(DAC0,6)
+#define DAC0_DAT7L                               DAC_DATL_REG(DAC0,7)
+#define DAC0_DAT7H                               DAC_DATH_REG(DAC0,7)
+#define DAC0_DAT8L                               DAC_DATL_REG(DAC0,8)
+#define DAC0_DAT8H                               DAC_DATH_REG(DAC0,8)
+#define DAC0_DAT9L                               DAC_DATL_REG(DAC0,9)
+#define DAC0_DAT9H                               DAC_DATH_REG(DAC0,9)
+#define DAC0_DAT10L                              DAC_DATL_REG(DAC0,10)
+#define DAC0_DAT10H                              DAC_DATH_REG(DAC0,10)
+#define DAC0_DAT11L                              DAC_DATL_REG(DAC0,11)
+#define DAC0_DAT11H                              DAC_DATH_REG(DAC0,11)
+#define DAC0_DAT12L                              DAC_DATL_REG(DAC0,12)
+#define DAC0_DAT12H                              DAC_DATH_REG(DAC0,12)
+#define DAC0_DAT13L                              DAC_DATL_REG(DAC0,13)
+#define DAC0_DAT13H                              DAC_DATH_REG(DAC0,13)
+#define DAC0_DAT14L                              DAC_DATL_REG(DAC0,14)
+#define DAC0_DAT14H                              DAC_DATH_REG(DAC0,14)
+#define DAC0_DAT15L                              DAC_DATL_REG(DAC0,15)
+#define DAC0_DAT15H                              DAC_DATH_REG(DAC0,15)
+#define DAC0_SR                                  DAC_SR_REG(DAC0)
+#define DAC0_C0                                  DAC_C0_REG(DAC0)
+#define DAC0_C1                                  DAC_C1_REG(DAC0)
+#define DAC0_C2                                  DAC_C2_REG(DAC0)
+/* DAC1 */
+#define DAC1_DAT0L                               DAC_DATL_REG(DAC1,0)
+#define DAC1_DAT0H                               DAC_DATH_REG(DAC1,0)
+#define DAC1_DAT1L                               DAC_DATL_REG(DAC1,1)
+#define DAC1_DAT1H                               DAC_DATH_REG(DAC1,1)
+#define DAC1_DAT2L                               DAC_DATL_REG(DAC1,2)
+#define DAC1_DAT2H                               DAC_DATH_REG(DAC1,2)
+#define DAC1_DAT3L                               DAC_DATL_REG(DAC1,3)
+#define DAC1_DAT3H                               DAC_DATH_REG(DAC1,3)
+#define DAC1_DAT4L                               DAC_DATL_REG(DAC1,4)
+#define DAC1_DAT4H                               DAC_DATH_REG(DAC1,4)
+#define DAC1_DAT5L                               DAC_DATL_REG(DAC1,5)
+#define DAC1_DAT5H                               DAC_DATH_REG(DAC1,5)
+#define DAC1_DAT6L                               DAC_DATL_REG(DAC1,6)
+#define DAC1_DAT6H                               DAC_DATH_REG(DAC1,6)
+#define DAC1_DAT7L                               DAC_DATL_REG(DAC1,7)
+#define DAC1_DAT7H                               DAC_DATH_REG(DAC1,7)
+#define DAC1_DAT8L                               DAC_DATL_REG(DAC1,8)
+#define DAC1_DAT8H                               DAC_DATH_REG(DAC1,8)
+#define DAC1_DAT9L                               DAC_DATL_REG(DAC1,9)
+#define DAC1_DAT9H                               DAC_DATH_REG(DAC1,9)
+#define DAC1_DAT10L                              DAC_DATL_REG(DAC1,10)
+#define DAC1_DAT10H                              DAC_DATH_REG(DAC1,10)
+#define DAC1_DAT11L                              DAC_DATL_REG(DAC1,11)
+#define DAC1_DAT11H                              DAC_DATH_REG(DAC1,11)
+#define DAC1_DAT12L                              DAC_DATL_REG(DAC1,12)
+#define DAC1_DAT12H                              DAC_DATH_REG(DAC1,12)
+#define DAC1_DAT13L                              DAC_DATL_REG(DAC1,13)
+#define DAC1_DAT13H                              DAC_DATH_REG(DAC1,13)
+#define DAC1_DAT14L                              DAC_DATL_REG(DAC1,14)
+#define DAC1_DAT14H                              DAC_DATH_REG(DAC1,14)
+#define DAC1_DAT15L                              DAC_DATL_REG(DAC1,15)
+#define DAC1_DAT15H                              DAC_DATH_REG(DAC1,15)
+#define DAC1_SR                                  DAC_SR_REG(DAC1)
+#define DAC1_C0                                  DAC_C0_REG(DAC1)
+#define DAC1_C1                                  DAC_C1_REG(DAC1)
+#define DAC1_C2                                  DAC_C2_REG(DAC1)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index)                         DAC_DATL_REG(DAC0,index)
+#define DAC1_DATL(index)                         DAC_DATL_REG(DAC1,index)
+#define DAC0_DATH(index)                         DAC_DATH_REG(DAC0,index)
+#define DAC1_DATH(index)                         DAC_DATH_REG(DAC1,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[200];
+  __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /**< Channel n Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /**< Channel n Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /**< Channel n Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /**< Channel n Priority Register, offset: 0x107 */
+  __IO uint8_t DCHPRI11;                           /**< Channel n Priority Register, offset: 0x108 */
+  __IO uint8_t DCHPRI10;                           /**< Channel n Priority Register, offset: 0x109 */
+  __IO uint8_t DCHPRI9;                            /**< Channel n Priority Register, offset: 0x10A */
+  __IO uint8_t DCHPRI8;                            /**< Channel n Priority Register, offset: 0x10B */
+  __IO uint8_t DCHPRI15;                           /**< Channel n Priority Register, offset: 0x10C */
+  __IO uint8_t DCHPRI14;                           /**< Channel n Priority Register, offset: 0x10D */
+  __IO uint8_t DCHPRI13;                           /**< Channel n Priority Register, offset: 0x10E */
+  __IO uint8_t DCHPRI12;                           /**< Channel n Priority Register, offset: 0x10F */
+       uint8_t RESERVED_6[3824];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[16];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_CR_REG(base)                         ((base)->CR)
+#define DMA_ES_REG(base)                         ((base)->ES)
+#define DMA_ERQ_REG(base)                        ((base)->ERQ)
+#define DMA_EEI_REG(base)                        ((base)->EEI)
+#define DMA_CEEI_REG(base)                       ((base)->CEEI)
+#define DMA_SEEI_REG(base)                       ((base)->SEEI)
+#define DMA_CERQ_REG(base)                       ((base)->CERQ)
+#define DMA_SERQ_REG(base)                       ((base)->SERQ)
+#define DMA_CDNE_REG(base)                       ((base)->CDNE)
+#define DMA_SSRT_REG(base)                       ((base)->SSRT)
+#define DMA_CERR_REG(base)                       ((base)->CERR)
+#define DMA_CINT_REG(base)                       ((base)->CINT)
+#define DMA_INT_REG(base)                        ((base)->INT)
+#define DMA_ERR_REG(base)                        ((base)->ERR)
+#define DMA_HRS_REG(base)                        ((base)->HRS)
+#define DMA_DCHPRI3_REG(base)                    ((base)->DCHPRI3)
+#define DMA_DCHPRI2_REG(base)                    ((base)->DCHPRI2)
+#define DMA_DCHPRI1_REG(base)                    ((base)->DCHPRI1)
+#define DMA_DCHPRI0_REG(base)                    ((base)->DCHPRI0)
+#define DMA_DCHPRI7_REG(base)                    ((base)->DCHPRI7)
+#define DMA_DCHPRI6_REG(base)                    ((base)->DCHPRI6)
+#define DMA_DCHPRI5_REG(base)                    ((base)->DCHPRI5)
+#define DMA_DCHPRI4_REG(base)                    ((base)->DCHPRI4)
+#define DMA_DCHPRI11_REG(base)                   ((base)->DCHPRI11)
+#define DMA_DCHPRI10_REG(base)                   ((base)->DCHPRI10)
+#define DMA_DCHPRI9_REG(base)                    ((base)->DCHPRI9)
+#define DMA_DCHPRI8_REG(base)                    ((base)->DCHPRI8)
+#define DMA_DCHPRI15_REG(base)                   ((base)->DCHPRI15)
+#define DMA_DCHPRI14_REG(base)                   ((base)->DCHPRI14)
+#define DMA_DCHPRI13_REG(base)                   ((base)->DCHPRI13)
+#define DMA_DCHPRI12_REG(base)                   ((base)->DCHPRI12)
+#define DMA_SADDR_REG(base,index)                ((base)->TCD[index].SADDR)
+#define DMA_SADDR_COUNT                          16
+#define DMA_SOFF_REG(base,index)                 ((base)->TCD[index].SOFF)
+#define DMA_SOFF_COUNT                           16
+#define DMA_ATTR_REG(base,index)                 ((base)->TCD[index].ATTR)
+#define DMA_ATTR_COUNT                           16
+#define DMA_NBYTES_MLNO_REG(base,index)          ((base)->TCD[index].NBYTES_MLNO)
+#define DMA_NBYTES_MLNO_COUNT                    16
+#define DMA_NBYTES_MLOFFNO_REG(base,index)       ((base)->TCD[index].NBYTES_MLOFFNO)
+#define DMA_NBYTES_MLOFFNO_COUNT                 16
+#define DMA_NBYTES_MLOFFYES_REG(base,index)      ((base)->TCD[index].NBYTES_MLOFFYES)
+#define DMA_NBYTES_MLOFFYES_COUNT                16
+#define DMA_SLAST_REG(base,index)                ((base)->TCD[index].SLAST)
+#define DMA_SLAST_COUNT                          16
+#define DMA_DADDR_REG(base,index)                ((base)->TCD[index].DADDR)
+#define DMA_DADDR_COUNT                          16
+#define DMA_DOFF_REG(base,index)                 ((base)->TCD[index].DOFF)
+#define DMA_DOFF_COUNT                           16
+#define DMA_CITER_ELINKNO_REG(base,index)        ((base)->TCD[index].CITER_ELINKNO)
+#define DMA_CITER_ELINKNO_COUNT                  16
+#define DMA_CITER_ELINKYES_REG(base,index)       ((base)->TCD[index].CITER_ELINKYES)
+#define DMA_CITER_ELINKYES_COUNT                 16
+#define DMA_DLAST_SGA_REG(base,index)            ((base)->TCD[index].DLAST_SGA)
+#define DMA_DLAST_SGA_COUNT                      16
+#define DMA_CSR_REG(base,index)                  ((base)->TCD[index].CSR)
+#define DMA_CSR_COUNT                            16
+#define DMA_BITER_ELINKNO_REG(base,index)        ((base)->TCD[index].BITER_ELINKNO)
+#define DMA_BITER_ELINKNO_COUNT                  16
+#define DMA_BITER_ELINKYES_REG(base,index)       ((base)->TCD[index].BITER_ELINKYES)
+#define DMA_BITER_ELINKYES_COUNT                 16
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK                         0x2u
+#define DMA_CR_EDBG_SHIFT                        1
+#define DMA_CR_EDBG_WIDTH                        1
+#define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK                         0x4u
+#define DMA_CR_ERCA_SHIFT                        2
+#define DMA_CR_ERCA_WIDTH                        1
+#define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK                          0x10u
+#define DMA_CR_HOE_SHIFT                         4
+#define DMA_CR_HOE_WIDTH                         1
+#define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK                         0x20u
+#define DMA_CR_HALT_SHIFT                        5
+#define DMA_CR_HALT_WIDTH                        1
+#define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK                          0x40u
+#define DMA_CR_CLM_SHIFT                         6
+#define DMA_CR_CLM_WIDTH                         1
+#define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK                         0x80u
+#define DMA_CR_EMLM_SHIFT                        7
+#define DMA_CR_EMLM_WIDTH                        1
+#define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK                          0x10000u
+#define DMA_CR_ECX_SHIFT                         16
+#define DMA_CR_ECX_WIDTH                         1
+#define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK                           0x20000u
+#define DMA_CR_CX_SHIFT                          17
+#define DMA_CR_CX_WIDTH                          1
+#define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK                          0x1u
+#define DMA_ES_DBE_SHIFT                         0
+#define DMA_ES_DBE_WIDTH                         1
+#define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK                          0x2u
+#define DMA_ES_SBE_SHIFT                         1
+#define DMA_ES_SBE_WIDTH                         1
+#define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK                          0x4u
+#define DMA_ES_SGE_SHIFT                         2
+#define DMA_ES_SGE_WIDTH                         1
+#define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK                          0x8u
+#define DMA_ES_NCE_SHIFT                         3
+#define DMA_ES_NCE_WIDTH                         1
+#define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK                          0x10u
+#define DMA_ES_DOE_SHIFT                         4
+#define DMA_ES_DOE_WIDTH                         1
+#define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK                          0x20u
+#define DMA_ES_DAE_SHIFT                         5
+#define DMA_ES_DAE_WIDTH                         1
+#define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK                          0x40u
+#define DMA_ES_SOE_SHIFT                         6
+#define DMA_ES_SOE_WIDTH                         1
+#define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK                          0x80u
+#define DMA_ES_SAE_SHIFT                         7
+#define DMA_ES_SAE_WIDTH                         1
+#define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK                       0xF00u
+#define DMA_ES_ERRCHN_SHIFT                      8
+#define DMA_ES_ERRCHN_WIDTH                      4
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          0x4000u
+#define DMA_ES_CPE_SHIFT                         14
+#define DMA_ES_CPE_WIDTH                         1
+#define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK                          0x10000u
+#define DMA_ES_ECX_SHIFT                         16
+#define DMA_ES_ECX_WIDTH                         1
+#define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK                          0x80000000u
+#define DMA_ES_VLD_SHIFT                         31
+#define DMA_ES_VLD_WIDTH                         1
+#define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK                        0x1u
+#define DMA_ERQ_ERQ0_SHIFT                       0
+#define DMA_ERQ_ERQ0_WIDTH                       1
+#define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK                        0x2u
+#define DMA_ERQ_ERQ1_SHIFT                       1
+#define DMA_ERQ_ERQ1_WIDTH                       1
+#define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK                        0x4u
+#define DMA_ERQ_ERQ2_SHIFT                       2
+#define DMA_ERQ_ERQ2_WIDTH                       1
+#define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK                        0x8u
+#define DMA_ERQ_ERQ3_SHIFT                       3
+#define DMA_ERQ_ERQ3_WIDTH                       1
+#define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK                        0x10u
+#define DMA_ERQ_ERQ4_SHIFT                       4
+#define DMA_ERQ_ERQ4_WIDTH                       1
+#define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK                        0x20u
+#define DMA_ERQ_ERQ5_SHIFT                       5
+#define DMA_ERQ_ERQ5_WIDTH                       1
+#define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK                        0x40u
+#define DMA_ERQ_ERQ6_SHIFT                       6
+#define DMA_ERQ_ERQ6_WIDTH                       1
+#define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK                        0x80u
+#define DMA_ERQ_ERQ7_SHIFT                       7
+#define DMA_ERQ_ERQ7_WIDTH                       1
+#define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK                        0x100u
+#define DMA_ERQ_ERQ8_SHIFT                       8
+#define DMA_ERQ_ERQ8_WIDTH                       1
+#define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK                        0x200u
+#define DMA_ERQ_ERQ9_SHIFT                       9
+#define DMA_ERQ_ERQ9_WIDTH                       1
+#define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK                       0x400u
+#define DMA_ERQ_ERQ10_SHIFT                      10
+#define DMA_ERQ_ERQ10_WIDTH                      1
+#define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK                       0x800u
+#define DMA_ERQ_ERQ11_SHIFT                      11
+#define DMA_ERQ_ERQ11_WIDTH                      1
+#define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK                       0x1000u
+#define DMA_ERQ_ERQ12_SHIFT                      12
+#define DMA_ERQ_ERQ12_WIDTH                      1
+#define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK                       0x2000u
+#define DMA_ERQ_ERQ13_SHIFT                      13
+#define DMA_ERQ_ERQ13_WIDTH                      1
+#define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK                       0x4000u
+#define DMA_ERQ_ERQ14_SHIFT                      14
+#define DMA_ERQ_ERQ14_WIDTH                      1
+#define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK                       0x8000u
+#define DMA_ERQ_ERQ15_SHIFT                      15
+#define DMA_ERQ_ERQ15_WIDTH                      1
+#define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK                        0x1u
+#define DMA_EEI_EEI0_SHIFT                       0
+#define DMA_EEI_EEI0_WIDTH                       1
+#define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK                        0x2u
+#define DMA_EEI_EEI1_SHIFT                       1
+#define DMA_EEI_EEI1_WIDTH                       1
+#define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK                        0x4u
+#define DMA_EEI_EEI2_SHIFT                       2
+#define DMA_EEI_EEI2_WIDTH                       1
+#define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK                        0x8u
+#define DMA_EEI_EEI3_SHIFT                       3
+#define DMA_EEI_EEI3_WIDTH                       1
+#define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK                        0x10u
+#define DMA_EEI_EEI4_SHIFT                       4
+#define DMA_EEI_EEI4_WIDTH                       1
+#define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK                        0x20u
+#define DMA_EEI_EEI5_SHIFT                       5
+#define DMA_EEI_EEI5_WIDTH                       1
+#define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK                        0x40u
+#define DMA_EEI_EEI6_SHIFT                       6
+#define DMA_EEI_EEI6_WIDTH                       1
+#define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK                        0x80u
+#define DMA_EEI_EEI7_SHIFT                       7
+#define DMA_EEI_EEI7_WIDTH                       1
+#define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK                        0x100u
+#define DMA_EEI_EEI8_SHIFT                       8
+#define DMA_EEI_EEI8_WIDTH                       1
+#define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK                        0x200u
+#define DMA_EEI_EEI9_SHIFT                       9
+#define DMA_EEI_EEI9_WIDTH                       1
+#define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK                       0x400u
+#define DMA_EEI_EEI10_SHIFT                      10
+#define DMA_EEI_EEI10_WIDTH                      1
+#define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK                       0x800u
+#define DMA_EEI_EEI11_SHIFT                      11
+#define DMA_EEI_EEI11_WIDTH                      1
+#define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK                       0x1000u
+#define DMA_EEI_EEI12_SHIFT                      12
+#define DMA_EEI_EEI12_WIDTH                      1
+#define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK                       0x2000u
+#define DMA_EEI_EEI13_SHIFT                      13
+#define DMA_EEI_EEI13_WIDTH                      1
+#define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK                       0x4000u
+#define DMA_EEI_EEI14_SHIFT                      14
+#define DMA_EEI_EEI14_WIDTH                      1
+#define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK                       0x8000u
+#define DMA_EEI_EEI15_SHIFT                      15
+#define DMA_EEI_EEI15_WIDTH                      1
+#define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK                       0xFu
+#define DMA_CEEI_CEEI_SHIFT                      0
+#define DMA_CEEI_CEEI_WIDTH                      4
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       0x40u
+#define DMA_CEEI_CAEE_SHIFT                      6
+#define DMA_CEEI_CAEE_WIDTH                      1
+#define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK                        0x80u
+#define DMA_CEEI_NOP_SHIFT                       7
+#define DMA_CEEI_NOP_WIDTH                       1
+#define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK                       0xFu
+#define DMA_SEEI_SEEI_SHIFT                      0
+#define DMA_SEEI_SEEI_WIDTH                      4
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       0x40u
+#define DMA_SEEI_SAEE_SHIFT                      6
+#define DMA_SEEI_SAEE_WIDTH                      1
+#define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK                        0x80u
+#define DMA_SEEI_NOP_SHIFT                       7
+#define DMA_SEEI_NOP_WIDTH                       1
+#define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK                       0xFu
+#define DMA_CERQ_CERQ_SHIFT                      0
+#define DMA_CERQ_CERQ_WIDTH                      4
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       0x40u
+#define DMA_CERQ_CAER_SHIFT                      6
+#define DMA_CERQ_CAER_WIDTH                      1
+#define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK                        0x80u
+#define DMA_CERQ_NOP_SHIFT                       7
+#define DMA_CERQ_NOP_WIDTH                       1
+#define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK                       0xFu
+#define DMA_SERQ_SERQ_SHIFT                      0
+#define DMA_SERQ_SERQ_WIDTH                      4
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       0x40u
+#define DMA_SERQ_SAER_SHIFT                      6
+#define DMA_SERQ_SAER_WIDTH                      1
+#define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK                        0x80u
+#define DMA_SERQ_NOP_SHIFT                       7
+#define DMA_SERQ_NOP_WIDTH                       1
+#define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK                       0xFu
+#define DMA_CDNE_CDNE_SHIFT                      0
+#define DMA_CDNE_CDNE_WIDTH                      4
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       0x40u
+#define DMA_CDNE_CADN_SHIFT                      6
+#define DMA_CDNE_CADN_WIDTH                      1
+#define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK                        0x80u
+#define DMA_CDNE_NOP_SHIFT                       7
+#define DMA_CDNE_NOP_WIDTH                       1
+#define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK                       0xFu
+#define DMA_SSRT_SSRT_SHIFT                      0
+#define DMA_SSRT_SSRT_WIDTH                      4
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       0x40u
+#define DMA_SSRT_SAST_SHIFT                      6
+#define DMA_SSRT_SAST_WIDTH                      1
+#define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK                        0x80u
+#define DMA_SSRT_NOP_SHIFT                       7
+#define DMA_SSRT_NOP_WIDTH                       1
+#define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK                       0xFu
+#define DMA_CERR_CERR_SHIFT                      0
+#define DMA_CERR_CERR_WIDTH                      4
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       0x40u
+#define DMA_CERR_CAEI_SHIFT                      6
+#define DMA_CERR_CAEI_WIDTH                      1
+#define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK                        0x80u
+#define DMA_CERR_NOP_SHIFT                       7
+#define DMA_CERR_NOP_WIDTH                       1
+#define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK                       0xFu
+#define DMA_CINT_CINT_SHIFT                      0
+#define DMA_CINT_CINT_WIDTH                      4
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       0x40u
+#define DMA_CINT_CAIR_SHIFT                      6
+#define DMA_CINT_CAIR_WIDTH                      1
+#define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK                        0x80u
+#define DMA_CINT_NOP_SHIFT                       7
+#define DMA_CINT_NOP_WIDTH                       1
+#define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK                        0x1u
+#define DMA_INT_INT0_SHIFT                       0
+#define DMA_INT_INT0_WIDTH                       1
+#define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK                        0x2u
+#define DMA_INT_INT1_SHIFT                       1
+#define DMA_INT_INT1_WIDTH                       1
+#define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK                        0x4u
+#define DMA_INT_INT2_SHIFT                       2
+#define DMA_INT_INT2_WIDTH                       1
+#define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK                        0x8u
+#define DMA_INT_INT3_SHIFT                       3
+#define DMA_INT_INT3_WIDTH                       1
+#define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK                        0x10u
+#define DMA_INT_INT4_SHIFT                       4
+#define DMA_INT_INT4_WIDTH                       1
+#define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK                        0x20u
+#define DMA_INT_INT5_SHIFT                       5
+#define DMA_INT_INT5_WIDTH                       1
+#define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK                        0x40u
+#define DMA_INT_INT6_SHIFT                       6
+#define DMA_INT_INT6_WIDTH                       1
+#define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK                        0x80u
+#define DMA_INT_INT7_SHIFT                       7
+#define DMA_INT_INT7_WIDTH                       1
+#define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK                        0x100u
+#define DMA_INT_INT8_SHIFT                       8
+#define DMA_INT_INT8_WIDTH                       1
+#define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK                        0x200u
+#define DMA_INT_INT9_SHIFT                       9
+#define DMA_INT_INT9_WIDTH                       1
+#define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK                       0x400u
+#define DMA_INT_INT10_SHIFT                      10
+#define DMA_INT_INT10_WIDTH                      1
+#define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK                       0x800u
+#define DMA_INT_INT11_SHIFT                      11
+#define DMA_INT_INT11_WIDTH                      1
+#define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK                       0x1000u
+#define DMA_INT_INT12_SHIFT                      12
+#define DMA_INT_INT12_WIDTH                      1
+#define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK                       0x2000u
+#define DMA_INT_INT13_SHIFT                      13
+#define DMA_INT_INT13_WIDTH                      1
+#define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK                       0x4000u
+#define DMA_INT_INT14_SHIFT                      14
+#define DMA_INT_INT14_WIDTH                      1
+#define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK                       0x8000u
+#define DMA_INT_INT15_SHIFT                      15
+#define DMA_INT_INT15_WIDTH                      1
+#define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK                        0x1u
+#define DMA_ERR_ERR0_SHIFT                       0
+#define DMA_ERR_ERR0_WIDTH                       1
+#define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK                        0x2u
+#define DMA_ERR_ERR1_SHIFT                       1
+#define DMA_ERR_ERR1_WIDTH                       1
+#define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK                        0x4u
+#define DMA_ERR_ERR2_SHIFT                       2
+#define DMA_ERR_ERR2_WIDTH                       1
+#define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK                        0x8u
+#define DMA_ERR_ERR3_SHIFT                       3
+#define DMA_ERR_ERR3_WIDTH                       1
+#define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK                        0x10u
+#define DMA_ERR_ERR4_SHIFT                       4
+#define DMA_ERR_ERR4_WIDTH                       1
+#define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK                        0x20u
+#define DMA_ERR_ERR5_SHIFT                       5
+#define DMA_ERR_ERR5_WIDTH                       1
+#define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK                        0x40u
+#define DMA_ERR_ERR6_SHIFT                       6
+#define DMA_ERR_ERR6_WIDTH                       1
+#define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK                        0x80u
+#define DMA_ERR_ERR7_SHIFT                       7
+#define DMA_ERR_ERR7_WIDTH                       1
+#define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK                        0x100u
+#define DMA_ERR_ERR8_SHIFT                       8
+#define DMA_ERR_ERR8_WIDTH                       1
+#define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK                        0x200u
+#define DMA_ERR_ERR9_SHIFT                       9
+#define DMA_ERR_ERR9_WIDTH                       1
+#define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK                       0x400u
+#define DMA_ERR_ERR10_SHIFT                      10
+#define DMA_ERR_ERR10_WIDTH                      1
+#define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK                       0x800u
+#define DMA_ERR_ERR11_SHIFT                      11
+#define DMA_ERR_ERR11_WIDTH                      1
+#define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK                       0x1000u
+#define DMA_ERR_ERR12_SHIFT                      12
+#define DMA_ERR_ERR12_WIDTH                      1
+#define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK                       0x2000u
+#define DMA_ERR_ERR13_SHIFT                      13
+#define DMA_ERR_ERR13_WIDTH                      1
+#define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK                       0x4000u
+#define DMA_ERR_ERR14_SHIFT                      14
+#define DMA_ERR_ERR14_WIDTH                      1
+#define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK                       0x8000u
+#define DMA_ERR_ERR15_SHIFT                      15
+#define DMA_ERR_ERR15_WIDTH                      1
+#define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK                        0x1u
+#define DMA_HRS_HRS0_SHIFT                       0
+#define DMA_HRS_HRS0_WIDTH                       1
+#define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK                        0x2u
+#define DMA_HRS_HRS1_SHIFT                       1
+#define DMA_HRS_HRS1_WIDTH                       1
+#define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK                        0x4u
+#define DMA_HRS_HRS2_SHIFT                       2
+#define DMA_HRS_HRS2_WIDTH                       1
+#define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK                        0x8u
+#define DMA_HRS_HRS3_SHIFT                       3
+#define DMA_HRS_HRS3_WIDTH                       1
+#define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK                        0x10u
+#define DMA_HRS_HRS4_SHIFT                       4
+#define DMA_HRS_HRS4_WIDTH                       1
+#define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK                        0x20u
+#define DMA_HRS_HRS5_SHIFT                       5
+#define DMA_HRS_HRS5_WIDTH                       1
+#define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK                        0x40u
+#define DMA_HRS_HRS6_SHIFT                       6
+#define DMA_HRS_HRS6_WIDTH                       1
+#define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK                        0x80u
+#define DMA_HRS_HRS7_SHIFT                       7
+#define DMA_HRS_HRS7_WIDTH                       1
+#define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK                        0x100u
+#define DMA_HRS_HRS8_SHIFT                       8
+#define DMA_HRS_HRS8_WIDTH                       1
+#define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK                        0x200u
+#define DMA_HRS_HRS9_SHIFT                       9
+#define DMA_HRS_HRS9_WIDTH                       1
+#define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK                       0x400u
+#define DMA_HRS_HRS10_SHIFT                      10
+#define DMA_HRS_HRS10_WIDTH                      1
+#define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK                       0x800u
+#define DMA_HRS_HRS11_SHIFT                      11
+#define DMA_HRS_HRS11_WIDTH                      1
+#define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK                       0x1000u
+#define DMA_HRS_HRS12_SHIFT                      12
+#define DMA_HRS_HRS12_WIDTH                      1
+#define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK                       0x2000u
+#define DMA_HRS_HRS13_SHIFT                      13
+#define DMA_HRS_HRS13_WIDTH                      1
+#define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK                       0x4000u
+#define DMA_HRS_HRS14_SHIFT                      14
+#define DMA_HRS_HRS14_WIDTH                      1
+#define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK                       0x8000u
+#define DMA_HRS_HRS15_SHIFT                      15
+#define DMA_HRS_HRS15_WIDTH                      1
+#define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT                  0
+#define DMA_DCHPRI3_CHPRI_WIDTH                  4
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     0x40u
+#define DMA_DCHPRI3_DPA_SHIFT                    6
+#define DMA_DCHPRI3_DPA_WIDTH                    1
+#define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_DPA_SHIFT))&DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK                     0x80u
+#define DMA_DCHPRI3_ECP_SHIFT                    7
+#define DMA_DCHPRI3_ECP_WIDTH                    1
+#define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_ECP_SHIFT))&DMA_DCHPRI3_ECP_MASK)
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT                  0
+#define DMA_DCHPRI2_CHPRI_WIDTH                  4
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     0x40u
+#define DMA_DCHPRI2_DPA_SHIFT                    6
+#define DMA_DCHPRI2_DPA_WIDTH                    1
+#define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_DPA_SHIFT))&DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK                     0x80u
+#define DMA_DCHPRI2_ECP_SHIFT                    7
+#define DMA_DCHPRI2_ECP_WIDTH                    1
+#define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_ECP_SHIFT))&DMA_DCHPRI2_ECP_MASK)
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT                  0
+#define DMA_DCHPRI1_CHPRI_WIDTH                  4
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     0x40u
+#define DMA_DCHPRI1_DPA_SHIFT                    6
+#define DMA_DCHPRI1_DPA_WIDTH                    1
+#define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_DPA_SHIFT))&DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK                     0x80u
+#define DMA_DCHPRI1_ECP_SHIFT                    7
+#define DMA_DCHPRI1_ECP_WIDTH                    1
+#define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_ECP_SHIFT))&DMA_DCHPRI1_ECP_MASK)
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT                  0
+#define DMA_DCHPRI0_CHPRI_WIDTH                  4
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     0x40u
+#define DMA_DCHPRI0_DPA_SHIFT                    6
+#define DMA_DCHPRI0_DPA_WIDTH                    1
+#define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_DPA_SHIFT))&DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK                     0x80u
+#define DMA_DCHPRI0_ECP_SHIFT                    7
+#define DMA_DCHPRI0_ECP_WIDTH                    1
+#define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_ECP_SHIFT))&DMA_DCHPRI0_ECP_MASK)
+/* DCHPRI7 Bit Fields */
+#define DMA_DCHPRI7_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI7_CHPRI_SHIFT                  0
+#define DMA_DCHPRI7_CHPRI_WIDTH                  4
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     0x40u
+#define DMA_DCHPRI7_DPA_SHIFT                    6
+#define DMA_DCHPRI7_DPA_WIDTH                    1
+#define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_DPA_SHIFT))&DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK                     0x80u
+#define DMA_DCHPRI7_ECP_SHIFT                    7
+#define DMA_DCHPRI7_ECP_WIDTH                    1
+#define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_ECP_SHIFT))&DMA_DCHPRI7_ECP_MASK)
+/* DCHPRI6 Bit Fields */
+#define DMA_DCHPRI6_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI6_CHPRI_SHIFT                  0
+#define DMA_DCHPRI6_CHPRI_WIDTH                  4
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     0x40u
+#define DMA_DCHPRI6_DPA_SHIFT                    6
+#define DMA_DCHPRI6_DPA_WIDTH                    1
+#define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_DPA_SHIFT))&DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK                     0x80u
+#define DMA_DCHPRI6_ECP_SHIFT                    7
+#define DMA_DCHPRI6_ECP_WIDTH                    1
+#define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_ECP_SHIFT))&DMA_DCHPRI6_ECP_MASK)
+/* DCHPRI5 Bit Fields */
+#define DMA_DCHPRI5_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI5_CHPRI_SHIFT                  0
+#define DMA_DCHPRI5_CHPRI_WIDTH                  4
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     0x40u
+#define DMA_DCHPRI5_DPA_SHIFT                    6
+#define DMA_DCHPRI5_DPA_WIDTH                    1
+#define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_DPA_SHIFT))&DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK                     0x80u
+#define DMA_DCHPRI5_ECP_SHIFT                    7
+#define DMA_DCHPRI5_ECP_WIDTH                    1
+#define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_ECP_SHIFT))&DMA_DCHPRI5_ECP_MASK)
+/* DCHPRI4 Bit Fields */
+#define DMA_DCHPRI4_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI4_CHPRI_SHIFT                  0
+#define DMA_DCHPRI4_CHPRI_WIDTH                  4
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     0x40u
+#define DMA_DCHPRI4_DPA_SHIFT                    6
+#define DMA_DCHPRI4_DPA_WIDTH                    1
+#define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_DPA_SHIFT))&DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK                     0x80u
+#define DMA_DCHPRI4_ECP_SHIFT                    7
+#define DMA_DCHPRI4_ECP_WIDTH                    1
+#define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_ECP_SHIFT))&DMA_DCHPRI4_ECP_MASK)
+/* DCHPRI11 Bit Fields */
+#define DMA_DCHPRI11_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI11_CHPRI_SHIFT                 0
+#define DMA_DCHPRI11_CHPRI_WIDTH                 4
+#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK                    0x40u
+#define DMA_DCHPRI11_DPA_SHIFT                   6
+#define DMA_DCHPRI11_DPA_WIDTH                   1
+#define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_DPA_SHIFT))&DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_ECP_MASK                    0x80u
+#define DMA_DCHPRI11_ECP_SHIFT                   7
+#define DMA_DCHPRI11_ECP_WIDTH                   1
+#define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_ECP_SHIFT))&DMA_DCHPRI11_ECP_MASK)
+/* DCHPRI10 Bit Fields */
+#define DMA_DCHPRI10_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI10_CHPRI_SHIFT                 0
+#define DMA_DCHPRI10_CHPRI_WIDTH                 4
+#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK                    0x40u
+#define DMA_DCHPRI10_DPA_SHIFT                   6
+#define DMA_DCHPRI10_DPA_WIDTH                   1
+#define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_DPA_SHIFT))&DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_ECP_MASK                    0x80u
+#define DMA_DCHPRI10_ECP_SHIFT                   7
+#define DMA_DCHPRI10_ECP_WIDTH                   1
+#define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_ECP_SHIFT))&DMA_DCHPRI10_ECP_MASK)
+/* DCHPRI9 Bit Fields */
+#define DMA_DCHPRI9_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI9_CHPRI_SHIFT                  0
+#define DMA_DCHPRI9_CHPRI_WIDTH                  4
+#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK                     0x40u
+#define DMA_DCHPRI9_DPA_SHIFT                    6
+#define DMA_DCHPRI9_DPA_WIDTH                    1
+#define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_DPA_SHIFT))&DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_ECP_MASK                     0x80u
+#define DMA_DCHPRI9_ECP_SHIFT                    7
+#define DMA_DCHPRI9_ECP_WIDTH                    1
+#define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_ECP_SHIFT))&DMA_DCHPRI9_ECP_MASK)
+/* DCHPRI8 Bit Fields */
+#define DMA_DCHPRI8_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI8_CHPRI_SHIFT                  0
+#define DMA_DCHPRI8_CHPRI_WIDTH                  4
+#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK                     0x40u
+#define DMA_DCHPRI8_DPA_SHIFT                    6
+#define DMA_DCHPRI8_DPA_WIDTH                    1
+#define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_DPA_SHIFT))&DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_ECP_MASK                     0x80u
+#define DMA_DCHPRI8_ECP_SHIFT                    7
+#define DMA_DCHPRI8_ECP_WIDTH                    1
+#define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_ECP_SHIFT))&DMA_DCHPRI8_ECP_MASK)
+/* DCHPRI15 Bit Fields */
+#define DMA_DCHPRI15_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI15_CHPRI_SHIFT                 0
+#define DMA_DCHPRI15_CHPRI_WIDTH                 4
+#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK                    0x40u
+#define DMA_DCHPRI15_DPA_SHIFT                   6
+#define DMA_DCHPRI15_DPA_WIDTH                   1
+#define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_DPA_SHIFT))&DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_ECP_MASK                    0x80u
+#define DMA_DCHPRI15_ECP_SHIFT                   7
+#define DMA_DCHPRI15_ECP_WIDTH                   1
+#define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_ECP_SHIFT))&DMA_DCHPRI15_ECP_MASK)
+/* DCHPRI14 Bit Fields */
+#define DMA_DCHPRI14_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI14_CHPRI_SHIFT                 0
+#define DMA_DCHPRI14_CHPRI_WIDTH                 4
+#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK                    0x40u
+#define DMA_DCHPRI14_DPA_SHIFT                   6
+#define DMA_DCHPRI14_DPA_WIDTH                   1
+#define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_DPA_SHIFT))&DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_ECP_MASK                    0x80u
+#define DMA_DCHPRI14_ECP_SHIFT                   7
+#define DMA_DCHPRI14_ECP_WIDTH                   1
+#define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_ECP_SHIFT))&DMA_DCHPRI14_ECP_MASK)
+/* DCHPRI13 Bit Fields */
+#define DMA_DCHPRI13_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI13_CHPRI_SHIFT                 0
+#define DMA_DCHPRI13_CHPRI_WIDTH                 4
+#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK                    0x40u
+#define DMA_DCHPRI13_DPA_SHIFT                   6
+#define DMA_DCHPRI13_DPA_WIDTH                   1
+#define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_DPA_SHIFT))&DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_ECP_MASK                    0x80u
+#define DMA_DCHPRI13_ECP_SHIFT                   7
+#define DMA_DCHPRI13_ECP_WIDTH                   1
+#define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_ECP_SHIFT))&DMA_DCHPRI13_ECP_MASK)
+/* DCHPRI12 Bit Fields */
+#define DMA_DCHPRI12_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI12_CHPRI_SHIFT                 0
+#define DMA_DCHPRI12_CHPRI_WIDTH                 4
+#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK                    0x40u
+#define DMA_DCHPRI12_DPA_SHIFT                   6
+#define DMA_DCHPRI12_DPA_WIDTH                   1
+#define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_DPA_SHIFT))&DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_ECP_MASK                    0x80u
+#define DMA_DCHPRI12_ECP_SHIFT                   7
+#define DMA_DCHPRI12_ECP_WIDTH                   1
+#define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_ECP_SHIFT))&DMA_DCHPRI12_ECP_MASK)
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK                     0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT                    0
+#define DMA_SADDR_SADDR_WIDTH                    32
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK                       0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT                      0
+#define DMA_SOFF_SOFF_WIDTH                      16
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK                      0x7u
+#define DMA_ATTR_DSIZE_SHIFT                     0
+#define DMA_ATTR_DSIZE_WIDTH                     3
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       0xF8u
+#define DMA_ATTR_DMOD_SHIFT                      3
+#define DMA_ATTR_DMOD_WIDTH                      5
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      0x700u
+#define DMA_ATTR_SSIZE_SHIFT                     8
+#define DMA_ATTR_SSIZE_WIDTH                     3
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       0xF800u
+#define DMA_ATTR_SMOD_SHIFT                      11
+#define DMA_ATTR_SMOD_WIDTH                      5
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             0
+#define DMA_NBYTES_MLNO_NBYTES_WIDTH             32
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          0
+#define DMA_NBYTES_MLOFFNO_NBYTES_WIDTH          30
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           30
+#define DMA_NBYTES_MLOFFNO_DMLOE_WIDTH           1
+#define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           31
+#define DMA_NBYTES_MLOFFNO_SMLOE_WIDTH           1
+#define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         0
+#define DMA_NBYTES_MLOFFYES_NBYTES_WIDTH         10
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          10
+#define DMA_NBYTES_MLOFFYES_MLOFF_WIDTH          20
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          30
+#define DMA_NBYTES_MLOFFYES_DMLOE_WIDTH          1
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          31
+#define DMA_NBYTES_MLOFFYES_SMLOE_WIDTH          1
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK                     0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT                    0
+#define DMA_SLAST_SLAST_WIDTH                    32
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK                     0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT                    0
+#define DMA_DADDR_DADDR_WIDTH                    32
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK                       0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT                      0
+#define DMA_DOFF_DOFF_WIDTH                      16
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK             0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT            0
+#define DMA_CITER_ELINKNO_CITER_WIDTH            15
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            15
+#define DMA_CITER_ELINKNO_ELINK_WIDTH            1
+#define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_ELINK_SHIFT))&DMA_CITER_ELINKNO_ELINK_MASK)
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK            0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT           0
+#define DMA_CITER_ELINKYES_CITER_WIDTH           9
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_CITER_ELINKYES_LINKCH_WIDTH          4
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           15
+#define DMA_CITER_ELINKYES_ELINK_WIDTH           1
+#define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_ELINK_SHIFT))&DMA_CITER_ELINKYES_ELINK_MASK)
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             0
+#define DMA_DLAST_SGA_DLASTSGA_WIDTH             32
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK                       0x1u
+#define DMA_CSR_START_SHIFT                      0
+#define DMA_CSR_START_WIDTH                      1
+#define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_CSR_START_SHIFT))&DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK                    0x2u
+#define DMA_CSR_INTMAJOR_SHIFT                   1
+#define DMA_CSR_INTMAJOR_WIDTH                   1
+#define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTMAJOR_SHIFT))&DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK                     0x4u
+#define DMA_CSR_INTHALF_SHIFT                    2
+#define DMA_CSR_INTHALF_WIDTH                    1
+#define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTHALF_SHIFT))&DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK                        0x8u
+#define DMA_CSR_DREQ_SHIFT                       3
+#define DMA_CSR_DREQ_WIDTH                       1
+#define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DREQ_SHIFT))&DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK                         0x10u
+#define DMA_CSR_ESG_SHIFT                        4
+#define DMA_CSR_ESG_WIDTH                        1
+#define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ESG_SHIFT))&DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK                  0x20u
+#define DMA_CSR_MAJORELINK_SHIFT                 5
+#define DMA_CSR_MAJORELINK_WIDTH                 1
+#define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORELINK_SHIFT))&DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK                      0x40u
+#define DMA_CSR_ACTIVE_SHIFT                     6
+#define DMA_CSR_ACTIVE_WIDTH                     1
+#define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ACTIVE_SHIFT))&DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK                        0x80u
+#define DMA_CSR_DONE_SHIFT                       7
+#define DMA_CSR_DONE_WIDTH                       1
+#define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DONE_SHIFT))&DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK                 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT                8
+#define DMA_CSR_MAJORLINKCH_WIDTH                4
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         0xC000u
+#define DMA_CSR_BWC_SHIFT                        14
+#define DMA_CSR_BWC_WIDTH                        2
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK             0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT            0
+#define DMA_BITER_ELINKNO_BITER_WIDTH            15
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            15
+#define DMA_BITER_ELINKNO_ELINK_WIDTH            1
+#define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_ELINK_SHIFT))&DMA_BITER_ELINKNO_ELINK_MASK)
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK            0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT           0
+#define DMA_BITER_ELINKYES_BITER_WIDTH           9
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_BITER_ELINKYES_LINKCH_WIDTH          4
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           15
+#define DMA_BITER_ELINKYES_ELINK_WIDTH           1
+#define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_ELINK_SHIFT))&DMA_BITER_ELINKYES_ELINK_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR                             (DMA0)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_CR                                   DMA_CR_REG(DMA0)
+#define DMA_ES                                   DMA_ES_REG(DMA0)
+#define DMA_ERQ                                  DMA_ERQ_REG(DMA0)
+#define DMA_EEI                                  DMA_EEI_REG(DMA0)
+#define DMA_CEEI                                 DMA_CEEI_REG(DMA0)
+#define DMA_SEEI                                 DMA_SEEI_REG(DMA0)
+#define DMA_CERQ                                 DMA_CERQ_REG(DMA0)
+#define DMA_SERQ                                 DMA_SERQ_REG(DMA0)
+#define DMA_CDNE                                 DMA_CDNE_REG(DMA0)
+#define DMA_SSRT                                 DMA_SSRT_REG(DMA0)
+#define DMA_CERR                                 DMA_CERR_REG(DMA0)
+#define DMA_CINT                                 DMA_CINT_REG(DMA0)
+#define DMA_INT                                  DMA_INT_REG(DMA0)
+#define DMA_ERR                                  DMA_ERR_REG(DMA0)
+#define DMA_HRS                                  DMA_HRS_REG(DMA0)
+#define DMA_DCHPRI3                              DMA_DCHPRI3_REG(DMA0)
+#define DMA_DCHPRI2                              DMA_DCHPRI2_REG(DMA0)
+#define DMA_DCHPRI1                              DMA_DCHPRI1_REG(DMA0)
+#define DMA_DCHPRI0                              DMA_DCHPRI0_REG(DMA0)
+#define DMA_DCHPRI7                              DMA_DCHPRI7_REG(DMA0)
+#define DMA_DCHPRI6                              DMA_DCHPRI6_REG(DMA0)
+#define DMA_DCHPRI5                              DMA_DCHPRI5_REG(DMA0)
+#define DMA_DCHPRI4                              DMA_DCHPRI4_REG(DMA0)
+#define DMA_DCHPRI11                             DMA_DCHPRI11_REG(DMA0)
+#define DMA_DCHPRI10                             DMA_DCHPRI10_REG(DMA0)
+#define DMA_DCHPRI9                              DMA_DCHPRI9_REG(DMA0)
+#define DMA_DCHPRI8                              DMA_DCHPRI8_REG(DMA0)
+#define DMA_DCHPRI15                             DMA_DCHPRI15_REG(DMA0)
+#define DMA_DCHPRI14                             DMA_DCHPRI14_REG(DMA0)
+#define DMA_DCHPRI13                             DMA_DCHPRI13_REG(DMA0)
+#define DMA_DCHPRI12                             DMA_DCHPRI12_REG(DMA0)
+#define DMA_TCD0_SADDR                           DMA_SADDR_REG(DMA0,0)
+#define DMA_TCD0_SOFF                            DMA_SOFF_REG(DMA0,0)
+#define DMA_TCD0_ATTR                            DMA_ATTR_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,0)
+#define DMA_TCD0_SLAST                           DMA_SLAST_REG(DMA0,0)
+#define DMA_TCD0_DADDR                           DMA_DADDR_REG(DMA0,0)
+#define DMA_TCD0_DOFF                            DMA_DOFF_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD0_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,0)
+#define DMA_TCD0_CSR                             DMA_CSR_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD1_SADDR                           DMA_SADDR_REG(DMA0,1)
+#define DMA_TCD1_SOFF                            DMA_SOFF_REG(DMA0,1)
+#define DMA_TCD1_ATTR                            DMA_ATTR_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,1)
+#define DMA_TCD1_SLAST                           DMA_SLAST_REG(DMA0,1)
+#define DMA_TCD1_DADDR                           DMA_DADDR_REG(DMA0,1)
+#define DMA_TCD1_DOFF                            DMA_DOFF_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD1_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,1)
+#define DMA_TCD1_CSR                             DMA_CSR_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD2_SADDR                           DMA_SADDR_REG(DMA0,2)
+#define DMA_TCD2_SOFF                            DMA_SOFF_REG(DMA0,2)
+#define DMA_TCD2_ATTR                            DMA_ATTR_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,2)
+#define DMA_TCD2_SLAST                           DMA_SLAST_REG(DMA0,2)
+#define DMA_TCD2_DADDR                           DMA_DADDR_REG(DMA0,2)
+#define DMA_TCD2_DOFF                            DMA_DOFF_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD2_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,2)
+#define DMA_TCD2_CSR                             DMA_CSR_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD3_SADDR                           DMA_SADDR_REG(DMA0,3)
+#define DMA_TCD3_SOFF                            DMA_SOFF_REG(DMA0,3)
+#define DMA_TCD3_ATTR                            DMA_ATTR_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,3)
+#define DMA_TCD3_SLAST                           DMA_SLAST_REG(DMA0,3)
+#define DMA_TCD3_DADDR                           DMA_DADDR_REG(DMA0,3)
+#define DMA_TCD3_DOFF                            DMA_DOFF_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD3_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,3)
+#define DMA_TCD3_CSR                             DMA_CSR_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD4_SADDR                           DMA_SADDR_REG(DMA0,4)
+#define DMA_TCD4_SOFF                            DMA_SOFF_REG(DMA0,4)
+#define DMA_TCD4_ATTR                            DMA_ATTR_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,4)
+#define DMA_TCD4_SLAST                           DMA_SLAST_REG(DMA0,4)
+#define DMA_TCD4_DADDR                           DMA_DADDR_REG(DMA0,4)
+#define DMA_TCD4_DOFF                            DMA_DOFF_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD4_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,4)
+#define DMA_TCD4_CSR                             DMA_CSR_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD5_SADDR                           DMA_SADDR_REG(DMA0,5)
+#define DMA_TCD5_SOFF                            DMA_SOFF_REG(DMA0,5)
+#define DMA_TCD5_ATTR                            DMA_ATTR_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,5)
+#define DMA_TCD5_SLAST                           DMA_SLAST_REG(DMA0,5)
+#define DMA_TCD5_DADDR                           DMA_DADDR_REG(DMA0,5)
+#define DMA_TCD5_DOFF                            DMA_DOFF_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD5_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,5)
+#define DMA_TCD5_CSR                             DMA_CSR_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD6_SADDR                           DMA_SADDR_REG(DMA0,6)
+#define DMA_TCD6_SOFF                            DMA_SOFF_REG(DMA0,6)
+#define DMA_TCD6_ATTR                            DMA_ATTR_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,6)
+#define DMA_TCD6_SLAST                           DMA_SLAST_REG(DMA0,6)
+#define DMA_TCD6_DADDR                           DMA_DADDR_REG(DMA0,6)
+#define DMA_TCD6_DOFF                            DMA_DOFF_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD6_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,6)
+#define DMA_TCD6_CSR                             DMA_CSR_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD7_SADDR                           DMA_SADDR_REG(DMA0,7)
+#define DMA_TCD7_SOFF                            DMA_SOFF_REG(DMA0,7)
+#define DMA_TCD7_ATTR                            DMA_ATTR_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,7)
+#define DMA_TCD7_SLAST                           DMA_SLAST_REG(DMA0,7)
+#define DMA_TCD7_DADDR                           DMA_DADDR_REG(DMA0,7)
+#define DMA_TCD7_DOFF                            DMA_DOFF_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD7_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,7)
+#define DMA_TCD7_CSR                             DMA_CSR_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD8_SADDR                           DMA_SADDR_REG(DMA0,8)
+#define DMA_TCD8_SOFF                            DMA_SOFF_REG(DMA0,8)
+#define DMA_TCD8_ATTR                            DMA_ATTR_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,8)
+#define DMA_TCD8_SLAST                           DMA_SLAST_REG(DMA0,8)
+#define DMA_TCD8_DADDR                           DMA_DADDR_REG(DMA0,8)
+#define DMA_TCD8_DOFF                            DMA_DOFF_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD8_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,8)
+#define DMA_TCD8_CSR                             DMA_CSR_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD9_SADDR                           DMA_SADDR_REG(DMA0,9)
+#define DMA_TCD9_SOFF                            DMA_SOFF_REG(DMA0,9)
+#define DMA_TCD9_ATTR                            DMA_ATTR_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,9)
+#define DMA_TCD9_SLAST                           DMA_SLAST_REG(DMA0,9)
+#define DMA_TCD9_DADDR                           DMA_DADDR_REG(DMA0,9)
+#define DMA_TCD9_DOFF                            DMA_DOFF_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD9_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,9)
+#define DMA_TCD9_CSR                             DMA_CSR_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD10_SADDR                          DMA_SADDR_REG(DMA0,10)
+#define DMA_TCD10_SOFF                           DMA_SOFF_REG(DMA0,10)
+#define DMA_TCD10_ATTR                           DMA_ATTR_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,10)
+#define DMA_TCD10_SLAST                          DMA_SLAST_REG(DMA0,10)
+#define DMA_TCD10_DADDR                          DMA_DADDR_REG(DMA0,10)
+#define DMA_TCD10_DOFF                           DMA_DOFF_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD10_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,10)
+#define DMA_TCD10_CSR                            DMA_CSR_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD11_SADDR                          DMA_SADDR_REG(DMA0,11)
+#define DMA_TCD11_SOFF                           DMA_SOFF_REG(DMA0,11)
+#define DMA_TCD11_ATTR                           DMA_ATTR_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,11)
+#define DMA_TCD11_SLAST                          DMA_SLAST_REG(DMA0,11)
+#define DMA_TCD11_DADDR                          DMA_DADDR_REG(DMA0,11)
+#define DMA_TCD11_DOFF                           DMA_DOFF_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD11_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,11)
+#define DMA_TCD11_CSR                            DMA_CSR_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD12_SADDR                          DMA_SADDR_REG(DMA0,12)
+#define DMA_TCD12_SOFF                           DMA_SOFF_REG(DMA0,12)
+#define DMA_TCD12_ATTR                           DMA_ATTR_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,12)
+#define DMA_TCD12_SLAST                          DMA_SLAST_REG(DMA0,12)
+#define DMA_TCD12_DADDR                          DMA_DADDR_REG(DMA0,12)
+#define DMA_TCD12_DOFF                           DMA_DOFF_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD12_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,12)
+#define DMA_TCD12_CSR                            DMA_CSR_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD13_SADDR                          DMA_SADDR_REG(DMA0,13)
+#define DMA_TCD13_SOFF                           DMA_SOFF_REG(DMA0,13)
+#define DMA_TCD13_ATTR                           DMA_ATTR_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,13)
+#define DMA_TCD13_SLAST                          DMA_SLAST_REG(DMA0,13)
+#define DMA_TCD13_DADDR                          DMA_DADDR_REG(DMA0,13)
+#define DMA_TCD13_DOFF                           DMA_DOFF_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD13_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,13)
+#define DMA_TCD13_CSR                            DMA_CSR_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD14_SADDR                          DMA_SADDR_REG(DMA0,14)
+#define DMA_TCD14_SOFF                           DMA_SOFF_REG(DMA0,14)
+#define DMA_TCD14_ATTR                           DMA_ATTR_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,14)
+#define DMA_TCD14_SLAST                          DMA_SLAST_REG(DMA0,14)
+#define DMA_TCD14_DADDR                          DMA_DADDR_REG(DMA0,14)
+#define DMA_TCD14_DOFF                           DMA_DOFF_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD14_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,14)
+#define DMA_TCD14_CSR                            DMA_CSR_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD15_SADDR                          DMA_SADDR_REG(DMA0,15)
+#define DMA_TCD15_SOFF                           DMA_SOFF_REG(DMA0,15)
+#define DMA_TCD15_ATTR                           DMA_ATTR_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,15)
+#define DMA_TCD15_SLAST                          DMA_SLAST_REG(DMA0,15)
+#define DMA_TCD15_DADDR                          DMA_DADDR_REG(DMA0,15)
+#define DMA_TCD15_DOFF                           DMA_DOFF_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,15)
+#define DMA_TCD15_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,15)
+#define DMA_TCD15_CSR                            DMA_CSR_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,15)
+
+/* DMA - Register array accessors */
+#define DMA_SADDR(index)                         DMA_SADDR_REG(DMA0,index)
+#define DMA_SOFF(index)                          DMA_SOFF_REG(DMA0,index)
+#define DMA_ATTR(index)                          DMA_ATTR_REG(DMA0,index)
+#define DMA_NBYTES_MLNO(index)                   DMA_NBYTES_MLNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFNO(index)                DMA_NBYTES_MLOFFNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFYES(index)               DMA_NBYTES_MLOFFYES_REG(DMA0,index)
+#define DMA_SLAST(index)                         DMA_SLAST_REG(DMA0,index)
+#define DMA_DADDR(index)                         DMA_DADDR_REG(DMA0,index)
+#define DMA_DOFF(index)                          DMA_DOFF_REG(DMA0,index)
+#define DMA_CITER_ELINKNO(index)                 DMA_CITER_ELINKNO_REG(DMA0,index)
+#define DMA_CITER_ELINKYES(index)                DMA_CITER_ELINKYES_REG(DMA0,index)
+#define DMA_DLAST_SGA(index)                     DMA_DLAST_SGA_REG(DMA0,index)
+#define DMA_CSR(index)                           DMA_CSR_REG(DMA0,index)
+#define DMA_BITER_ELINKNO(index)                 DMA_BITER_ELINKNO_REG(DMA0,index)
+#define DMA_BITER_ELINKYES(index)                DMA_BITER_ELINKYES_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[16];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index)             ((base)->CHCFG[index])
+#define DMAMUX_CHCFG_COUNT                       16
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT                0
+#define DMAMUX_CHCFG_SOURCE_WIDTH                6
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT                  6
+#define DMAMUX_CHCFG_TRIG_WIDTH                  1
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT                  7
+#define DMAMUX_CHCFG_ENBL_WIDTH                  1
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE                              (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
+#define DMAMUX_BASE_PTR                          (DMAMUX)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { DMAMUX }
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX */
+#define DMAMUX_CHCFG0                            DMAMUX_CHCFG_REG(DMAMUX,0)
+#define DMAMUX_CHCFG1                            DMAMUX_CHCFG_REG(DMAMUX,1)
+#define DMAMUX_CHCFG2                            DMAMUX_CHCFG_REG(DMAMUX,2)
+#define DMAMUX_CHCFG3                            DMAMUX_CHCFG_REG(DMAMUX,3)
+#define DMAMUX_CHCFG4                            DMAMUX_CHCFG_REG(DMAMUX,4)
+#define DMAMUX_CHCFG5                            DMAMUX_CHCFG_REG(DMAMUX,5)
+#define DMAMUX_CHCFG6                            DMAMUX_CHCFG_REG(DMAMUX,6)
+#define DMAMUX_CHCFG7                            DMAMUX_CHCFG_REG(DMAMUX,7)
+#define DMAMUX_CHCFG8                            DMAMUX_CHCFG_REG(DMAMUX,8)
+#define DMAMUX_CHCFG9                            DMAMUX_CHCFG_REG(DMAMUX,9)
+#define DMAMUX_CHCFG10                           DMAMUX_CHCFG_REG(DMAMUX,10)
+#define DMAMUX_CHCFG11                           DMAMUX_CHCFG_REG(DMAMUX,11)
+#define DMAMUX_CHCFG12                           DMAMUX_CHCFG_REG(DMAMUX,12)
+#define DMAMUX_CHCFG13                           DMAMUX_CHCFG_REG(DMAMUX,13)
+#define DMAMUX_CHCFG14                           DMAMUX_CHCFG_REG(DMAMUX,14)
+#define DMAMUX_CHCFG15                           DMAMUX_CHCFG_REG(DMAMUX,15)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX_CHCFG(index)                      DMAMUX_CHCFG_REG(DMAMUX,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4];
+  __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
+  __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register, offset: 0x10 */
+  __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register, offset: 0x14 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
+  __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
+       uint8_t RESERVED_4[28];
+  __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
+       uint8_t RESERVED_5[28];
+  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
+  __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
+  __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
+       uint8_t RESERVED_8[40];
+  __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+  __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+  __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
+  __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
+       uint8_t RESERVED_9[28];
+  __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
+       uint8_t RESERVED_10[56];
+  __IO uint32_t RDSR;                              /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+  __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+  __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+  __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+  __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+  __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+  __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+  __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+  __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+  __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+  __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
+       uint8_t RESERVED_12[12];
+  __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+  __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+       uint8_t RESERVED_13[60];
+  __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
+  __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
+  __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
+  __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
+  __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
+  __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
+  __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
+  __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
+  __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
+  __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
+  __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
+  __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
+  __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
+  __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
+  __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
+  __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
+  __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
+       uint8_t RESERVED_14[4];
+  __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
+  __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
+  __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
+  __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
+  __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
+  __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
+  __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
+  __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
+       uint8_t RESERVED_15[4];
+  __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
+  __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
+       uint8_t RESERVED_16[12];
+  __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
+  __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
+  __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
+  __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
+  __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
+  __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
+  __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
+  __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
+       uint8_t RESERVED_17[4];
+  __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
+  __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
+  __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
+  __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
+  __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
+  __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
+  __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
+  __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
+  __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
+  __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
+  __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
+  __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
+  __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
+  __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
+  __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
+       uint8_t RESERVED_18[284];
+  __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
+  __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
+  __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
+  __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
+  __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
+  __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
+  __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+       uint8_t RESERVED_19[488];
+  __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
+  struct {                                         /* offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+  } CHANNEL[4];
+} ENET_Type, *ENET_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register accessors */
+#define ENET_EIR_REG(base)                       ((base)->EIR)
+#define ENET_EIMR_REG(base)                      ((base)->EIMR)
+#define ENET_RDAR_REG(base)                      ((base)->RDAR)
+#define ENET_TDAR_REG(base)                      ((base)->TDAR)
+#define ENET_ECR_REG(base)                       ((base)->ECR)
+#define ENET_MMFR_REG(base)                      ((base)->MMFR)
+#define ENET_MSCR_REG(base)                      ((base)->MSCR)
+#define ENET_MIBC_REG(base)                      ((base)->MIBC)
+#define ENET_RCR_REG(base)                       ((base)->RCR)
+#define ENET_TCR_REG(base)                       ((base)->TCR)
+#define ENET_PALR_REG(base)                      ((base)->PALR)
+#define ENET_PAUR_REG(base)                      ((base)->PAUR)
+#define ENET_OPD_REG(base)                       ((base)->OPD)
+#define ENET_IAUR_REG(base)                      ((base)->IAUR)
+#define ENET_IALR_REG(base)                      ((base)->IALR)
+#define ENET_GAUR_REG(base)                      ((base)->GAUR)
+#define ENET_GALR_REG(base)                      ((base)->GALR)
+#define ENET_TFWR_REG(base)                      ((base)->TFWR)
+#define ENET_RDSR_REG(base)                      ((base)->RDSR)
+#define ENET_TDSR_REG(base)                      ((base)->TDSR)
+#define ENET_MRBR_REG(base)                      ((base)->MRBR)
+#define ENET_RSFL_REG(base)                      ((base)->RSFL)
+#define ENET_RSEM_REG(base)                      ((base)->RSEM)
+#define ENET_RAEM_REG(base)                      ((base)->RAEM)
+#define ENET_RAFL_REG(base)                      ((base)->RAFL)
+#define ENET_TSEM_REG(base)                      ((base)->TSEM)
+#define ENET_TAEM_REG(base)                      ((base)->TAEM)
+#define ENET_TAFL_REG(base)                      ((base)->TAFL)
+#define ENET_TIPG_REG(base)                      ((base)->TIPG)
+#define ENET_FTRL_REG(base)                      ((base)->FTRL)
+#define ENET_TACC_REG(base)                      ((base)->TACC)
+#define ENET_RACC_REG(base)                      ((base)->RACC)
+#define ENET_RMON_T_PACKETS_REG(base)            ((base)->RMON_T_PACKETS)
+#define ENET_RMON_T_BC_PKT_REG(base)             ((base)->RMON_T_BC_PKT)
+#define ENET_RMON_T_MC_PKT_REG(base)             ((base)->RMON_T_MC_PKT)
+#define ENET_RMON_T_CRC_ALIGN_REG(base)          ((base)->RMON_T_CRC_ALIGN)
+#define ENET_RMON_T_UNDERSIZE_REG(base)          ((base)->RMON_T_UNDERSIZE)
+#define ENET_RMON_T_OVERSIZE_REG(base)           ((base)->RMON_T_OVERSIZE)
+#define ENET_RMON_T_FRAG_REG(base)               ((base)->RMON_T_FRAG)
+#define ENET_RMON_T_JAB_REG(base)                ((base)->RMON_T_JAB)
+#define ENET_RMON_T_COL_REG(base)                ((base)->RMON_T_COL)
+#define ENET_RMON_T_P64_REG(base)                ((base)->RMON_T_P64)
+#define ENET_RMON_T_P65TO127_REG(base)           ((base)->RMON_T_P65TO127)
+#define ENET_RMON_T_P128TO255_REG(base)          ((base)->RMON_T_P128TO255)
+#define ENET_RMON_T_P256TO511_REG(base)          ((base)->RMON_T_P256TO511)
+#define ENET_RMON_T_P512TO1023_REG(base)         ((base)->RMON_T_P512TO1023)
+#define ENET_RMON_T_P1024TO2047_REG(base)        ((base)->RMON_T_P1024TO2047)
+#define ENET_RMON_T_P_GTE2048_REG(base)          ((base)->RMON_T_P_GTE2048)
+#define ENET_RMON_T_OCTETS_REG(base)             ((base)->RMON_T_OCTETS)
+#define ENET_IEEE_T_FRAME_OK_REG(base)           ((base)->IEEE_T_FRAME_OK)
+#define ENET_IEEE_T_1COL_REG(base)               ((base)->IEEE_T_1COL)
+#define ENET_IEEE_T_MCOL_REG(base)               ((base)->IEEE_T_MCOL)
+#define ENET_IEEE_T_DEF_REG(base)                ((base)->IEEE_T_DEF)
+#define ENET_IEEE_T_LCOL_REG(base)               ((base)->IEEE_T_LCOL)
+#define ENET_IEEE_T_EXCOL_REG(base)              ((base)->IEEE_T_EXCOL)
+#define ENET_IEEE_T_MACERR_REG(base)             ((base)->IEEE_T_MACERR)
+#define ENET_IEEE_T_CSERR_REG(base)              ((base)->IEEE_T_CSERR)
+#define ENET_IEEE_T_FDXFC_REG(base)              ((base)->IEEE_T_FDXFC)
+#define ENET_IEEE_T_OCTETS_OK_REG(base)          ((base)->IEEE_T_OCTETS_OK)
+#define ENET_RMON_R_PACKETS_REG(base)            ((base)->RMON_R_PACKETS)
+#define ENET_RMON_R_BC_PKT_REG(base)             ((base)->RMON_R_BC_PKT)
+#define ENET_RMON_R_MC_PKT_REG(base)             ((base)->RMON_R_MC_PKT)
+#define ENET_RMON_R_CRC_ALIGN_REG(base)          ((base)->RMON_R_CRC_ALIGN)
+#define ENET_RMON_R_UNDERSIZE_REG(base)          ((base)->RMON_R_UNDERSIZE)
+#define ENET_RMON_R_OVERSIZE_REG(base)           ((base)->RMON_R_OVERSIZE)
+#define ENET_RMON_R_FRAG_REG(base)               ((base)->RMON_R_FRAG)
+#define ENET_RMON_R_JAB_REG(base)                ((base)->RMON_R_JAB)
+#define ENET_RMON_R_P64_REG(base)                ((base)->RMON_R_P64)
+#define ENET_RMON_R_P65TO127_REG(base)           ((base)->RMON_R_P65TO127)
+#define ENET_RMON_R_P128TO255_REG(base)          ((base)->RMON_R_P128TO255)
+#define ENET_RMON_R_P256TO511_REG(base)          ((base)->RMON_R_P256TO511)
+#define ENET_RMON_R_P512TO1023_REG(base)         ((base)->RMON_R_P512TO1023)
+#define ENET_RMON_R_P1024TO2047_REG(base)        ((base)->RMON_R_P1024TO2047)
+#define ENET_RMON_R_P_GTE2048_REG(base)          ((base)->RMON_R_P_GTE2048)
+#define ENET_RMON_R_OCTETS_REG(base)             ((base)->RMON_R_OCTETS)
+#define ENET_IEEE_R_DROP_REG(base)               ((base)->IEEE_R_DROP)
+#define ENET_IEEE_R_FRAME_OK_REG(base)           ((base)->IEEE_R_FRAME_OK)
+#define ENET_IEEE_R_CRC_REG(base)                ((base)->IEEE_R_CRC)
+#define ENET_IEEE_R_ALIGN_REG(base)              ((base)->IEEE_R_ALIGN)
+#define ENET_IEEE_R_MACERR_REG(base)             ((base)->IEEE_R_MACERR)
+#define ENET_IEEE_R_FDXFC_REG(base)              ((base)->IEEE_R_FDXFC)
+#define ENET_IEEE_R_OCTETS_OK_REG(base)          ((base)->IEEE_R_OCTETS_OK)
+#define ENET_ATCR_REG(base)                      ((base)->ATCR)
+#define ENET_ATVR_REG(base)                      ((base)->ATVR)
+#define ENET_ATOFF_REG(base)                     ((base)->ATOFF)
+#define ENET_ATPER_REG(base)                     ((base)->ATPER)
+#define ENET_ATCOR_REG(base)                     ((base)->ATCOR)
+#define ENET_ATINC_REG(base)                     ((base)->ATINC)
+#define ENET_ATSTMP_REG(base)                    ((base)->ATSTMP)
+#define ENET_TGSR_REG(base)                      ((base)->TGSR)
+#define ENET_TCSR_REG(base,index)                ((base)->CHANNEL[index].TCSR)
+#define ENET_TCSR_COUNT                          4
+#define ENET_TCCR_REG(base,index)                ((base)->CHANNEL[index].TCCR)
+#define ENET_TCCR_COUNT                          4
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/* EIR Bit Fields */
+#define ENET_EIR_TS_TIMER_MASK                   0x8000u
+#define ENET_EIR_TS_TIMER_SHIFT                  15
+#define ENET_EIR_TS_TIMER_WIDTH                  1
+#define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_TIMER_SHIFT))&ENET_EIR_TS_TIMER_MASK)
+#define ENET_EIR_TS_AVAIL_MASK                   0x10000u
+#define ENET_EIR_TS_AVAIL_SHIFT                  16
+#define ENET_EIR_TS_AVAIL_WIDTH                  1
+#define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_AVAIL_SHIFT))&ENET_EIR_TS_AVAIL_MASK)
+#define ENET_EIR_WAKEUP_MASK                     0x20000u
+#define ENET_EIR_WAKEUP_SHIFT                    17
+#define ENET_EIR_WAKEUP_WIDTH                    1
+#define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_EIR_WAKEUP_SHIFT))&ENET_EIR_WAKEUP_MASK)
+#define ENET_EIR_PLR_MASK                        0x40000u
+#define ENET_EIR_PLR_SHIFT                       18
+#define ENET_EIR_PLR_WIDTH                       1
+#define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_PLR_SHIFT))&ENET_EIR_PLR_MASK)
+#define ENET_EIR_UN_MASK                         0x80000u
+#define ENET_EIR_UN_SHIFT                        19
+#define ENET_EIR_UN_WIDTH                        1
+#define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_UN_SHIFT))&ENET_EIR_UN_MASK)
+#define ENET_EIR_RL_MASK                         0x100000u
+#define ENET_EIR_RL_SHIFT                        20
+#define ENET_EIR_RL_WIDTH                        1
+#define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RL_SHIFT))&ENET_EIR_RL_MASK)
+#define ENET_EIR_LC_MASK                         0x200000u
+#define ENET_EIR_LC_SHIFT                        21
+#define ENET_EIR_LC_WIDTH                        1
+#define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_LC_SHIFT))&ENET_EIR_LC_MASK)
+#define ENET_EIR_EBERR_MASK                      0x400000u
+#define ENET_EIR_EBERR_SHIFT                     22
+#define ENET_EIR_EBERR_WIDTH                     1
+#define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIR_EBERR_SHIFT))&ENET_EIR_EBERR_MASK)
+#define ENET_EIR_MII_MASK                        0x800000u
+#define ENET_EIR_MII_SHIFT                       23
+#define ENET_EIR_MII_WIDTH                       1
+#define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_MII_SHIFT))&ENET_EIR_MII_MASK)
+#define ENET_EIR_RXB_MASK                        0x1000000u
+#define ENET_EIR_RXB_SHIFT                       24
+#define ENET_EIR_RXB_WIDTH                       1
+#define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXB_SHIFT))&ENET_EIR_RXB_MASK)
+#define ENET_EIR_RXF_MASK                        0x2000000u
+#define ENET_EIR_RXF_SHIFT                       25
+#define ENET_EIR_RXF_WIDTH                       1
+#define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXF_SHIFT))&ENET_EIR_RXF_MASK)
+#define ENET_EIR_TXB_MASK                        0x4000000u
+#define ENET_EIR_TXB_SHIFT                       26
+#define ENET_EIR_TXB_WIDTH                       1
+#define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXB_SHIFT))&ENET_EIR_TXB_MASK)
+#define ENET_EIR_TXF_MASK                        0x8000000u
+#define ENET_EIR_TXF_SHIFT                       27
+#define ENET_EIR_TXF_WIDTH                       1
+#define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXF_SHIFT))&ENET_EIR_TXF_MASK)
+#define ENET_EIR_GRA_MASK                        0x10000000u
+#define ENET_EIR_GRA_SHIFT                       28
+#define ENET_EIR_GRA_WIDTH                       1
+#define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_GRA_SHIFT))&ENET_EIR_GRA_MASK)
+#define ENET_EIR_BABT_MASK                       0x20000000u
+#define ENET_EIR_BABT_SHIFT                      29
+#define ENET_EIR_BABT_WIDTH                      1
+#define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABT_SHIFT))&ENET_EIR_BABT_MASK)
+#define ENET_EIR_BABR_MASK                       0x40000000u
+#define ENET_EIR_BABR_SHIFT                      30
+#define ENET_EIR_BABR_WIDTH                      1
+#define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABR_SHIFT))&ENET_EIR_BABR_MASK)
+/* EIMR Bit Fields */
+#define ENET_EIMR_TS_TIMER_MASK                  0x8000u
+#define ENET_EIMR_TS_TIMER_SHIFT                 15
+#define ENET_EIMR_TS_TIMER_WIDTH                 1
+#define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_TIMER_SHIFT))&ENET_EIMR_TS_TIMER_MASK)
+#define ENET_EIMR_TS_AVAIL_MASK                  0x10000u
+#define ENET_EIMR_TS_AVAIL_SHIFT                 16
+#define ENET_EIMR_TS_AVAIL_WIDTH                 1
+#define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_AVAIL_SHIFT))&ENET_EIMR_TS_AVAIL_MASK)
+#define ENET_EIMR_WAKEUP_MASK                    0x20000u
+#define ENET_EIMR_WAKEUP_SHIFT                   17
+#define ENET_EIMR_WAKEUP_WIDTH                   1
+#define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_WAKEUP_SHIFT))&ENET_EIMR_WAKEUP_MASK)
+#define ENET_EIMR_PLR_MASK                       0x40000u
+#define ENET_EIMR_PLR_SHIFT                      18
+#define ENET_EIMR_PLR_WIDTH                      1
+#define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_PLR_SHIFT))&ENET_EIMR_PLR_MASK)
+#define ENET_EIMR_UN_MASK                        0x80000u
+#define ENET_EIMR_UN_SHIFT                       19
+#define ENET_EIMR_UN_WIDTH                       1
+#define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_UN_SHIFT))&ENET_EIMR_UN_MASK)
+#define ENET_EIMR_RL_MASK                        0x100000u
+#define ENET_EIMR_RL_SHIFT                       20
+#define ENET_EIMR_RL_WIDTH                       1
+#define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RL_SHIFT))&ENET_EIMR_RL_MASK)
+#define ENET_EIMR_LC_MASK                        0x200000u
+#define ENET_EIMR_LC_SHIFT                       21
+#define ENET_EIMR_LC_WIDTH                       1
+#define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_LC_SHIFT))&ENET_EIMR_LC_MASK)
+#define ENET_EIMR_EBERR_MASK                     0x400000u
+#define ENET_EIMR_EBERR_SHIFT                    22
+#define ENET_EIMR_EBERR_WIDTH                    1
+#define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_EBERR_SHIFT))&ENET_EIMR_EBERR_MASK)
+#define ENET_EIMR_MII_MASK                       0x800000u
+#define ENET_EIMR_MII_SHIFT                      23
+#define ENET_EIMR_MII_WIDTH                      1
+#define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_MII_SHIFT))&ENET_EIMR_MII_MASK)
+#define ENET_EIMR_RXB_MASK                       0x1000000u
+#define ENET_EIMR_RXB_SHIFT                      24
+#define ENET_EIMR_RXB_WIDTH                      1
+#define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXB_SHIFT))&ENET_EIMR_RXB_MASK)
+#define ENET_EIMR_RXF_MASK                       0x2000000u
+#define ENET_EIMR_RXF_SHIFT                      25
+#define ENET_EIMR_RXF_WIDTH                      1
+#define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXF_SHIFT))&ENET_EIMR_RXF_MASK)
+#define ENET_EIMR_TXB_MASK                       0x4000000u
+#define ENET_EIMR_TXB_SHIFT                      26
+#define ENET_EIMR_TXB_WIDTH                      1
+#define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXB_SHIFT))&ENET_EIMR_TXB_MASK)
+#define ENET_EIMR_TXF_MASK                       0x8000000u
+#define ENET_EIMR_TXF_SHIFT                      27
+#define ENET_EIMR_TXF_WIDTH                      1
+#define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXF_SHIFT))&ENET_EIMR_TXF_MASK)
+#define ENET_EIMR_GRA_MASK                       0x10000000u
+#define ENET_EIMR_GRA_SHIFT                      28
+#define ENET_EIMR_GRA_WIDTH                      1
+#define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_GRA_SHIFT))&ENET_EIMR_GRA_MASK)
+#define ENET_EIMR_BABT_MASK                      0x20000000u
+#define ENET_EIMR_BABT_SHIFT                     29
+#define ENET_EIMR_BABT_WIDTH                     1
+#define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABT_SHIFT))&ENET_EIMR_BABT_MASK)
+#define ENET_EIMR_BABR_MASK                      0x40000000u
+#define ENET_EIMR_BABR_SHIFT                     30
+#define ENET_EIMR_BABR_WIDTH                     1
+#define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABR_SHIFT))&ENET_EIMR_BABR_MASK)
+/* RDAR Bit Fields */
+#define ENET_RDAR_RDAR_MASK                      0x1000000u
+#define ENET_RDAR_RDAR_SHIFT                     24
+#define ENET_RDAR_RDAR_WIDTH                     1
+#define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RDAR_RDAR_SHIFT))&ENET_RDAR_RDAR_MASK)
+/* TDAR Bit Fields */
+#define ENET_TDAR_TDAR_MASK                      0x1000000u
+#define ENET_TDAR_TDAR_SHIFT                     24
+#define ENET_TDAR_TDAR_WIDTH                     1
+#define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TDAR_TDAR_SHIFT))&ENET_TDAR_TDAR_MASK)
+/* ECR Bit Fields */
+#define ENET_ECR_RESET_MASK                      0x1u
+#define ENET_ECR_RESET_SHIFT                     0
+#define ENET_ECR_RESET_WIDTH                     1
+#define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_RESET_SHIFT))&ENET_ECR_RESET_MASK)
+#define ENET_ECR_ETHEREN_MASK                    0x2u
+#define ENET_ECR_ETHEREN_SHIFT                   1
+#define ENET_ECR_ETHEREN_WIDTH                   1
+#define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ECR_ETHEREN_SHIFT))&ENET_ECR_ETHEREN_MASK)
+#define ENET_ECR_MAGICEN_MASK                    0x4u
+#define ENET_ECR_MAGICEN_SHIFT                   2
+#define ENET_ECR_MAGICEN_WIDTH                   1
+#define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ECR_MAGICEN_SHIFT))&ENET_ECR_MAGICEN_MASK)
+#define ENET_ECR_SLEEP_MASK                      0x8u
+#define ENET_ECR_SLEEP_SHIFT                     3
+#define ENET_ECR_SLEEP_WIDTH                     1
+#define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_SLEEP_SHIFT))&ENET_ECR_SLEEP_MASK)
+#define ENET_ECR_EN1588_MASK                     0x10u
+#define ENET_ECR_EN1588_SHIFT                    4
+#define ENET_ECR_EN1588_WIDTH                    1
+#define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ECR_EN1588_SHIFT))&ENET_ECR_EN1588_MASK)
+#define ENET_ECR_DBGEN_MASK                      0x40u
+#define ENET_ECR_DBGEN_SHIFT                     6
+#define ENET_ECR_DBGEN_WIDTH                     1
+#define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBGEN_SHIFT))&ENET_ECR_DBGEN_MASK)
+#define ENET_ECR_STOPEN_MASK                     0x80u
+#define ENET_ECR_STOPEN_SHIFT                    7
+#define ENET_ECR_STOPEN_WIDTH                    1
+#define ENET_ECR_STOPEN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ECR_STOPEN_SHIFT))&ENET_ECR_STOPEN_MASK)
+#define ENET_ECR_DBSWP_MASK                      0x100u
+#define ENET_ECR_DBSWP_SHIFT                     8
+#define ENET_ECR_DBSWP_WIDTH                     1
+#define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBSWP_SHIFT))&ENET_ECR_DBSWP_MASK)
+/* MMFR Bit Fields */
+#define ENET_MMFR_DATA_MASK                      0xFFFFu
+#define ENET_MMFR_DATA_SHIFT                     0
+#define ENET_MMFR_DATA_WIDTH                     16
+#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK                        0x30000u
+#define ENET_MMFR_TA_SHIFT                       16
+#define ENET_MMFR_TA_WIDTH                       2
+#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK                        0x7C0000u
+#define ENET_MMFR_RA_SHIFT                       18
+#define ENET_MMFR_RA_WIDTH                       5
+#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK                        0xF800000u
+#define ENET_MMFR_PA_SHIFT                       23
+#define ENET_MMFR_PA_WIDTH                       5
+#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK                        0x30000000u
+#define ENET_MMFR_OP_SHIFT                       28
+#define ENET_MMFR_OP_WIDTH                       2
+#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK                        0xC0000000u
+#define ENET_MMFR_ST_SHIFT                       30
+#define ENET_MMFR_ST_WIDTH                       2
+#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
+/* MSCR Bit Fields */
+#define ENET_MSCR_MII_SPEED_MASK                 0x7Eu
+#define ENET_MSCR_MII_SPEED_SHIFT                1
+#define ENET_MSCR_MII_SPEED_WIDTH                6
+#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE_MASK                   0x80u
+#define ENET_MSCR_DIS_PRE_SHIFT                  7
+#define ENET_MSCR_DIS_PRE_WIDTH                  1
+#define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_DIS_PRE_SHIFT))&ENET_MSCR_DIS_PRE_MASK)
+#define ENET_MSCR_HOLDTIME_MASK                  0x700u
+#define ENET_MSCR_HOLDTIME_SHIFT                 8
+#define ENET_MSCR_HOLDTIME_WIDTH                 3
+#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
+/* MIBC Bit Fields */
+#define ENET_MIBC_MIB_CLEAR_MASK                 0x20000000u
+#define ENET_MIBC_MIB_CLEAR_SHIFT                29
+#define ENET_MIBC_MIB_CLEAR_WIDTH                1
+#define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_CLEAR_SHIFT))&ENET_MIBC_MIB_CLEAR_MASK)
+#define ENET_MIBC_MIB_IDLE_MASK                  0x40000000u
+#define ENET_MIBC_MIB_IDLE_SHIFT                 30
+#define ENET_MIBC_MIB_IDLE_WIDTH                 1
+#define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_IDLE_SHIFT))&ENET_MIBC_MIB_IDLE_MASK)
+#define ENET_MIBC_MIB_DIS_MASK                   0x80000000u
+#define ENET_MIBC_MIB_DIS_SHIFT                  31
+#define ENET_MIBC_MIB_DIS_WIDTH                  1
+#define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_DIS_SHIFT))&ENET_MIBC_MIB_DIS_MASK)
+/* RCR Bit Fields */
+#define ENET_RCR_LOOP_MASK                       0x1u
+#define ENET_RCR_LOOP_SHIFT                      0
+#define ENET_RCR_LOOP_WIDTH                      1
+#define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_LOOP_SHIFT))&ENET_RCR_LOOP_MASK)
+#define ENET_RCR_DRT_MASK                        0x2u
+#define ENET_RCR_DRT_SHIFT                       1
+#define ENET_RCR_DRT_WIDTH                       1
+#define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_DRT_SHIFT))&ENET_RCR_DRT_MASK)
+#define ENET_RCR_MII_MODE_MASK                   0x4u
+#define ENET_RCR_MII_MODE_SHIFT                  2
+#define ENET_RCR_MII_MODE_WIDTH                  1
+#define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MII_MODE_SHIFT))&ENET_RCR_MII_MODE_MASK)
+#define ENET_RCR_PROM_MASK                       0x8u
+#define ENET_RCR_PROM_SHIFT                      3
+#define ENET_RCR_PROM_WIDTH                      1
+#define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PROM_SHIFT))&ENET_RCR_PROM_MASK)
+#define ENET_RCR_BC_REJ_MASK                     0x10u
+#define ENET_RCR_BC_REJ_SHIFT                    4
+#define ENET_RCR_BC_REJ_WIDTH                    1
+#define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_BC_REJ_SHIFT))&ENET_RCR_BC_REJ_MASK)
+#define ENET_RCR_FCE_MASK                        0x20u
+#define ENET_RCR_FCE_SHIFT                       5
+#define ENET_RCR_FCE_WIDTH                       1
+#define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_FCE_SHIFT))&ENET_RCR_FCE_MASK)
+#define ENET_RCR_RMII_MODE_MASK                  0x100u
+#define ENET_RCR_RMII_MODE_SHIFT                 8
+#define ENET_RCR_RMII_MODE_WIDTH                 1
+#define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_MODE_SHIFT))&ENET_RCR_RMII_MODE_MASK)
+#define ENET_RCR_RMII_10T_MASK                   0x200u
+#define ENET_RCR_RMII_10T_SHIFT                  9
+#define ENET_RCR_RMII_10T_WIDTH                  1
+#define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_10T_SHIFT))&ENET_RCR_RMII_10T_MASK)
+#define ENET_RCR_PADEN_MASK                      0x1000u
+#define ENET_RCR_PADEN_SHIFT                     12
+#define ENET_RCR_PADEN_WIDTH                     1
+#define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PADEN_SHIFT))&ENET_RCR_PADEN_MASK)
+#define ENET_RCR_PAUFWD_MASK                     0x2000u
+#define ENET_RCR_PAUFWD_SHIFT                    13
+#define ENET_RCR_PAUFWD_WIDTH                    1
+#define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PAUFWD_SHIFT))&ENET_RCR_PAUFWD_MASK)
+#define ENET_RCR_CRCFWD_MASK                     0x4000u
+#define ENET_RCR_CRCFWD_SHIFT                    14
+#define ENET_RCR_CRCFWD_WIDTH                    1
+#define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CRCFWD_SHIFT))&ENET_RCR_CRCFWD_MASK)
+#define ENET_RCR_CFEN_MASK                       0x8000u
+#define ENET_RCR_CFEN_SHIFT                      15
+#define ENET_RCR_CFEN_WIDTH                      1
+#define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CFEN_SHIFT))&ENET_RCR_CFEN_MASK)
+#define ENET_RCR_MAX_FL_MASK                     0x3FFF0000u
+#define ENET_RCR_MAX_FL_SHIFT                    16
+#define ENET_RCR_MAX_FL_WIDTH                    14
+#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC_MASK                        0x40000000u
+#define ENET_RCR_NLC_SHIFT                       30
+#define ENET_RCR_NLC_WIDTH                       1
+#define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_NLC_SHIFT))&ENET_RCR_NLC_MASK)
+#define ENET_RCR_GRS_MASK                        0x80000000u
+#define ENET_RCR_GRS_SHIFT                       31
+#define ENET_RCR_GRS_WIDTH                       1
+#define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_GRS_SHIFT))&ENET_RCR_GRS_MASK)
+/* TCR Bit Fields */
+#define ENET_TCR_GTS_MASK                        0x1u
+#define ENET_TCR_GTS_SHIFT                       0
+#define ENET_TCR_GTS_WIDTH                       1
+#define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_TCR_GTS_SHIFT))&ENET_TCR_GTS_MASK)
+#define ENET_TCR_FDEN_MASK                       0x4u
+#define ENET_TCR_FDEN_SHIFT                      2
+#define ENET_TCR_FDEN_WIDTH                      1
+#define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCR_FDEN_SHIFT))&ENET_TCR_FDEN_MASK)
+#define ENET_TCR_TFC_PAUSE_MASK                  0x8u
+#define ENET_TCR_TFC_PAUSE_SHIFT                 3
+#define ENET_TCR_TFC_PAUSE_WIDTH                 1
+#define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_TCR_TFC_PAUSE_SHIFT))&ENET_TCR_TFC_PAUSE_MASK)
+#define ENET_TCR_RFC_PAUSE_MASK                  0x10u
+#define ENET_TCR_RFC_PAUSE_SHIFT                 4
+#define ENET_TCR_RFC_PAUSE_WIDTH                 1
+#define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_TCR_RFC_PAUSE_SHIFT))&ENET_TCR_RFC_PAUSE_MASK)
+#define ENET_TCR_ADDSEL_MASK                     0xE0u
+#define ENET_TCR_ADDSEL_SHIFT                    5
+#define ENET_TCR_ADDSEL_WIDTH                    3
+#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS_MASK                     0x100u
+#define ENET_TCR_ADDINS_SHIFT                    8
+#define ENET_TCR_ADDINS_WIDTH                    1
+#define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDINS_SHIFT))&ENET_TCR_ADDINS_MASK)
+#define ENET_TCR_CRCFWD_MASK                     0x200u
+#define ENET_TCR_CRCFWD_SHIFT                    9
+#define ENET_TCR_CRCFWD_WIDTH                    1
+#define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_CRCFWD_SHIFT))&ENET_TCR_CRCFWD_MASK)
+/* PALR Bit Fields */
+#define ENET_PALR_PADDR1_MASK                    0xFFFFFFFFu
+#define ENET_PALR_PADDR1_SHIFT                   0
+#define ENET_PALR_PADDR1_WIDTH                   32
+#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
+/* PAUR Bit Fields */
+#define ENET_PAUR_TYPE_MASK                      0xFFFFu
+#define ENET_PAUR_TYPE_SHIFT                     0
+#define ENET_PAUR_TYPE_WIDTH                     16
+#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK                    0xFFFF0000u
+#define ENET_PAUR_PADDR2_SHIFT                   16
+#define ENET_PAUR_PADDR2_WIDTH                   16
+#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
+/* OPD Bit Fields */
+#define ENET_OPD_PAUSE_DUR_MASK                  0xFFFFu
+#define ENET_OPD_PAUSE_DUR_SHIFT                 0
+#define ENET_OPD_PAUSE_DUR_WIDTH                 16
+#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK                     0xFFFF0000u
+#define ENET_OPD_OPCODE_SHIFT                    16
+#define ENET_OPD_OPCODE_WIDTH                    16
+#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
+/* IAUR Bit Fields */
+#define ENET_IAUR_IADDR1_MASK                    0xFFFFFFFFu
+#define ENET_IAUR_IADDR1_SHIFT                   0
+#define ENET_IAUR_IADDR1_WIDTH                   32
+#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
+/* IALR Bit Fields */
+#define ENET_IALR_IADDR2_MASK                    0xFFFFFFFFu
+#define ENET_IALR_IADDR2_SHIFT                   0
+#define ENET_IALR_IADDR2_WIDTH                   32
+#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
+/* GAUR Bit Fields */
+#define ENET_GAUR_GADDR1_MASK                    0xFFFFFFFFu
+#define ENET_GAUR_GADDR1_SHIFT                   0
+#define ENET_GAUR_GADDR1_WIDTH                   32
+#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
+/* GALR Bit Fields */
+#define ENET_GALR_GADDR2_MASK                    0xFFFFFFFFu
+#define ENET_GALR_GADDR2_SHIFT                   0
+#define ENET_GALR_GADDR2_WIDTH                   32
+#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
+/* TFWR Bit Fields */
+#define ENET_TFWR_TFWR_MASK                      0x3Fu
+#define ENET_TFWR_TFWR_SHIFT                     0
+#define ENET_TFWR_TFWR_WIDTH                     6
+#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD_MASK                    0x100u
+#define ENET_TFWR_STRFWD_SHIFT                   8
+#define ENET_TFWR_STRFWD_WIDTH                   1
+#define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_STRFWD_SHIFT))&ENET_TFWR_STRFWD_MASK)
+/* RDSR Bit Fields */
+#define ENET_RDSR_R_DES_START_MASK               0xFFFFFFF8u
+#define ENET_RDSR_R_DES_START_SHIFT              3
+#define ENET_RDSR_R_DES_START_WIDTH              29
+#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
+/* TDSR Bit Fields */
+#define ENET_TDSR_X_DES_START_MASK               0xFFFFFFF8u
+#define ENET_TDSR_X_DES_START_SHIFT              3
+#define ENET_TDSR_X_DES_START_WIDTH              29
+#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
+/* MRBR Bit Fields */
+#define ENET_MRBR_R_BUF_SIZE_MASK                0x3FF0u
+#define ENET_MRBR_R_BUF_SIZE_SHIFT               4
+#define ENET_MRBR_R_BUF_SIZE_WIDTH               10
+#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
+/* RSFL Bit Fields */
+#define ENET_RSFL_RX_SECTION_FULL_MASK           0xFFu
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT          0
+#define ENET_RSFL_RX_SECTION_FULL_WIDTH          8
+#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
+/* RSEM Bit Fields */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         0
+#define ENET_RSEM_RX_SECTION_EMPTY_WIDTH         8
+#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK        0x1F0000u
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       16
+#define ENET_RSEM_STAT_SECTION_EMPTY_WIDTH       5
+#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+/* RAEM Bit Fields */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          0
+#define ENET_RAEM_RX_ALMOST_EMPTY_WIDTH          8
+#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+/* RAFL Bit Fields */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK            0xFFu
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           0
+#define ENET_RAFL_RX_ALMOST_FULL_WIDTH           8
+#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
+/* TSEM Bit Fields */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         0
+#define ENET_TSEM_TX_SECTION_EMPTY_WIDTH         8
+#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
+/* TAEM Bit Fields */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          0
+#define ENET_TAEM_TX_ALMOST_EMPTY_WIDTH          8
+#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+/* TAFL Bit Fields */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK            0xFFu
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           0
+#define ENET_TAFL_TX_ALMOST_FULL_WIDTH           8
+#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
+/* TIPG Bit Fields */
+#define ENET_TIPG_IPG_MASK                       0x1Fu
+#define ENET_TIPG_IPG_SHIFT                      0
+#define ENET_TIPG_IPG_WIDTH                      5
+#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
+/* FTRL Bit Fields */
+#define ENET_FTRL_TRUNC_FL_MASK                  0x3FFFu
+#define ENET_FTRL_TRUNC_FL_SHIFT                 0
+#define ENET_FTRL_TRUNC_FL_WIDTH                 14
+#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
+/* TACC Bit Fields */
+#define ENET_TACC_SHIFT16_MASK                   0x1u
+#define ENET_TACC_SHIFT16_SHIFT                  0
+#define ENET_TACC_SHIFT16_WIDTH                  1
+#define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_TACC_SHIFT16_SHIFT))&ENET_TACC_SHIFT16_MASK)
+#define ENET_TACC_IPCHK_MASK                     0x8u
+#define ENET_TACC_IPCHK_SHIFT                    3
+#define ENET_TACC_IPCHK_WIDTH                    1
+#define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TACC_IPCHK_SHIFT))&ENET_TACC_IPCHK_MASK)
+#define ENET_TACC_PROCHK_MASK                    0x10u
+#define ENET_TACC_PROCHK_SHIFT                   4
+#define ENET_TACC_PROCHK_WIDTH                   1
+#define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_TACC_PROCHK_SHIFT))&ENET_TACC_PROCHK_MASK)
+/* RACC Bit Fields */
+#define ENET_RACC_PADREM_MASK                    0x1u
+#define ENET_RACC_PADREM_SHIFT                   0
+#define ENET_RACC_PADREM_WIDTH                   1
+#define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PADREM_SHIFT))&ENET_RACC_PADREM_MASK)
+#define ENET_RACC_IPDIS_MASK                     0x2u
+#define ENET_RACC_IPDIS_SHIFT                    1
+#define ENET_RACC_IPDIS_WIDTH                    1
+#define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RACC_IPDIS_SHIFT))&ENET_RACC_IPDIS_MASK)
+#define ENET_RACC_PRODIS_MASK                    0x4u
+#define ENET_RACC_PRODIS_SHIFT                   2
+#define ENET_RACC_PRODIS_WIDTH                   1
+#define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PRODIS_SHIFT))&ENET_RACC_PRODIS_MASK)
+#define ENET_RACC_LINEDIS_MASK                   0x40u
+#define ENET_RACC_LINEDIS_SHIFT                  6
+#define ENET_RACC_LINEDIS_WIDTH                  1
+#define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RACC_LINEDIS_SHIFT))&ENET_RACC_LINEDIS_MASK)
+#define ENET_RACC_SHIFT16_MASK                   0x80u
+#define ENET_RACC_SHIFT16_SHIFT                  7
+#define ENET_RACC_SHIFT16_WIDTH                  1
+#define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RACC_SHIFT16_SHIFT))&ENET_RACC_SHIFT16_MASK)
+/* RMON_T_PACKETS Bit Fields */
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK          0xFFFFu
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         0
+#define ENET_RMON_T_PACKETS_TXPKTS_WIDTH         16
+#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
+/* RMON_T_BC_PKT Bit Fields */
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           0xFFFFu
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          0
+#define ENET_RMON_T_BC_PKT_TXPKTS_WIDTH          16
+#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+/* RMON_T_MC_PKT Bit Fields */
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           0xFFFFu
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          0
+#define ENET_RMON_T_MC_PKT_TXPKTS_WIDTH          16
+#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+/* RMON_T_CRC_ALIGN Bit Fields */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       0
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_WIDTH       16
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+/* RMON_T_UNDERSIZE Bit Fields */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       0
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_WIDTH       16
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+/* RMON_T_OVERSIZE Bit Fields */
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         0xFFFFu
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        0
+#define ENET_RMON_T_OVERSIZE_TXPKTS_WIDTH        16
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+/* RMON_T_FRAG Bit Fields */
+#define ENET_RMON_T_FRAG_TXPKTS_MASK             0xFFFFu
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            0
+#define ENET_RMON_T_FRAG_TXPKTS_WIDTH            16
+#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
+/* RMON_T_JAB Bit Fields */
+#define ENET_RMON_T_JAB_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT             0
+#define ENET_RMON_T_JAB_TXPKTS_WIDTH             16
+#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
+/* RMON_T_COL Bit Fields */
+#define ENET_RMON_T_COL_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_COL_TXPKTS_SHIFT             0
+#define ENET_RMON_T_COL_TXPKTS_WIDTH             16
+#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
+/* RMON_T_P64 Bit Fields */
+#define ENET_RMON_T_P64_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_P64_TXPKTS_SHIFT             0
+#define ENET_RMON_T_P64_TXPKTS_WIDTH             16
+#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
+/* RMON_T_P65TO127 Bit Fields */
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK         0xFFFFu
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        0
+#define ENET_RMON_T_P65TO127_TXPKTS_WIDTH        16
+#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
+/* RMON_T_P128TO255 Bit Fields */
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P128TO255_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
+/* RMON_T_P256TO511 Bit Fields */
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P256TO511_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
+/* RMON_T_P512TO1023 Bit Fields */
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       0xFFFFu
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      0
+#define ENET_RMON_T_P512TO1023_TXPKTS_WIDTH      16
+#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+/* RMON_T_P1024TO2047 Bit Fields */
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      0xFFFFu
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     0
+#define ENET_RMON_T_P1024TO2047_TXPKTS_WIDTH     16
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+/* RMON_T_P_GTE2048 Bit Fields */
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P_GTE2048_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+/* RMON_T_OCTETS Bit Fields */
+#define ENET_RMON_T_OCTETS_TXOCTS_MASK           0xFFFFFFFFu
+#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          0
+#define ENET_RMON_T_OCTETS_TXOCTS_WIDTH          32
+#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
+/* IEEE_T_FRAME_OK Bit Fields */
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          0xFFFFu
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         0
+#define ENET_IEEE_T_FRAME_OK_COUNT_WIDTH         16
+#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+/* IEEE_T_1COL Bit Fields */
+#define ENET_IEEE_T_1COL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_1COL_COUNT_SHIFT             0
+#define ENET_IEEE_T_1COL_COUNT_WIDTH             16
+#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
+/* IEEE_T_MCOL Bit Fields */
+#define ENET_IEEE_T_MCOL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT             0
+#define ENET_IEEE_T_MCOL_COUNT_WIDTH             16
+#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
+/* IEEE_T_DEF Bit Fields */
+#define ENET_IEEE_T_DEF_COUNT_MASK               0xFFFFu
+#define ENET_IEEE_T_DEF_COUNT_SHIFT              0
+#define ENET_IEEE_T_DEF_COUNT_WIDTH              16
+#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
+/* IEEE_T_LCOL Bit Fields */
+#define ENET_IEEE_T_LCOL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT             0
+#define ENET_IEEE_T_LCOL_COUNT_WIDTH             16
+#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
+/* IEEE_T_EXCOL Bit Fields */
+#define ENET_IEEE_T_EXCOL_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            0
+#define ENET_IEEE_T_EXCOL_COUNT_WIDTH            16
+#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
+/* IEEE_T_MACERR Bit Fields */
+#define ENET_IEEE_T_MACERR_COUNT_MASK            0xFFFFu
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT           0
+#define ENET_IEEE_T_MACERR_COUNT_WIDTH           16
+#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
+/* IEEE_T_CSERR Bit Fields */
+#define ENET_IEEE_T_CSERR_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT            0
+#define ENET_IEEE_T_CSERR_COUNT_WIDTH            16
+#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
+/* IEEE_T_FDXFC Bit Fields */
+#define ENET_IEEE_T_FDXFC_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            0
+#define ENET_IEEE_T_FDXFC_COUNT_WIDTH            16
+#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
+/* IEEE_T_OCTETS_OK Bit Fields */
+#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        0
+#define ENET_IEEE_T_OCTETS_OK_COUNT_WIDTH        32
+#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+/* RMON_R_PACKETS Bit Fields */
+#define ENET_RMON_R_PACKETS_COUNT_MASK           0xFFFFu
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT          0
+#define ENET_RMON_R_PACKETS_COUNT_WIDTH          16
+#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
+/* RMON_R_BC_PKT Bit Fields */
+#define ENET_RMON_R_BC_PKT_COUNT_MASK            0xFFFFu
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           0
+#define ENET_RMON_R_BC_PKT_COUNT_WIDTH           16
+#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
+/* RMON_R_MC_PKT Bit Fields */
+#define ENET_RMON_R_MC_PKT_COUNT_MASK            0xFFFFu
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           0
+#define ENET_RMON_R_MC_PKT_COUNT_WIDTH           16
+#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
+/* RMON_R_CRC_ALIGN Bit Fields */
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        0
+#define ENET_RMON_R_CRC_ALIGN_COUNT_WIDTH        16
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+/* RMON_R_UNDERSIZE Bit Fields */
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        0
+#define ENET_RMON_R_UNDERSIZE_COUNT_WIDTH        16
+#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+/* RMON_R_OVERSIZE Bit Fields */
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK          0xFFFFu
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         0
+#define ENET_RMON_R_OVERSIZE_COUNT_WIDTH         16
+#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
+/* RMON_R_FRAG Bit Fields */
+#define ENET_RMON_R_FRAG_COUNT_MASK              0xFFFFu
+#define ENET_RMON_R_FRAG_COUNT_SHIFT             0
+#define ENET_RMON_R_FRAG_COUNT_WIDTH             16
+#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
+/* RMON_R_JAB Bit Fields */
+#define ENET_RMON_R_JAB_COUNT_MASK               0xFFFFu
+#define ENET_RMON_R_JAB_COUNT_SHIFT              0
+#define ENET_RMON_R_JAB_COUNT_WIDTH              16
+#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
+/* RMON_R_P64 Bit Fields */
+#define ENET_RMON_R_P64_COUNT_MASK               0xFFFFu
+#define ENET_RMON_R_P64_COUNT_SHIFT              0
+#define ENET_RMON_R_P64_COUNT_WIDTH              16
+#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
+/* RMON_R_P65TO127 Bit Fields */
+#define ENET_RMON_R_P65TO127_COUNT_MASK          0xFFFFu
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT         0
+#define ENET_RMON_R_P65TO127_COUNT_WIDTH         16
+#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
+/* RMON_R_P128TO255 Bit Fields */
+#define ENET_RMON_R_P128TO255_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT        0
+#define ENET_RMON_R_P128TO255_COUNT_WIDTH        16
+#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
+/* RMON_R_P256TO511 Bit Fields */
+#define ENET_RMON_R_P256TO511_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT        0
+#define ENET_RMON_R_P256TO511_COUNT_WIDTH        16
+#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
+/* RMON_R_P512TO1023 Bit Fields */
+#define ENET_RMON_R_P512TO1023_COUNT_MASK        0xFFFFu
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       0
+#define ENET_RMON_R_P512TO1023_COUNT_WIDTH       16
+#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
+/* RMON_R_P1024TO2047 Bit Fields */
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK       0xFFFFu
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      0
+#define ENET_RMON_R_P1024TO2047_COUNT_WIDTH      16
+#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
+/* RMON_R_P_GTE2048 Bit Fields */
+#define ENET_RMON_R_P_GTE2048_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        0
+#define ENET_RMON_R_P_GTE2048_COUNT_WIDTH        16
+#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
+/* RMON_R_OCTETS Bit Fields */
+#define ENET_RMON_R_OCTETS_COUNT_MASK            0xFFFFFFFFu
+#define ENET_RMON_R_OCTETS_COUNT_SHIFT           0
+#define ENET_RMON_R_OCTETS_COUNT_WIDTH           32
+#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
+/* IEEE_R_DROP Bit Fields */
+#define ENET_IEEE_R_DROP_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_R_DROP_COUNT_SHIFT             0
+#define ENET_IEEE_R_DROP_COUNT_WIDTH             16
+#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
+/* IEEE_R_FRAME_OK Bit Fields */
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          0xFFFFu
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         0
+#define ENET_IEEE_R_FRAME_OK_COUNT_WIDTH         16
+#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+/* IEEE_R_CRC Bit Fields */
+#define ENET_IEEE_R_CRC_COUNT_MASK               0xFFFFu
+#define ENET_IEEE_R_CRC_COUNT_SHIFT              0
+#define ENET_IEEE_R_CRC_COUNT_WIDTH              16
+#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
+/* IEEE_R_ALIGN Bit Fields */
+#define ENET_IEEE_R_ALIGN_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            0
+#define ENET_IEEE_R_ALIGN_COUNT_WIDTH            16
+#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
+/* IEEE_R_MACERR Bit Fields */
+#define ENET_IEEE_R_MACERR_COUNT_MASK            0xFFFFu
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT           0
+#define ENET_IEEE_R_MACERR_COUNT_WIDTH           16
+#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
+/* IEEE_R_FDXFC Bit Fields */
+#define ENET_IEEE_R_FDXFC_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            0
+#define ENET_IEEE_R_FDXFC_COUNT_WIDTH            16
+#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
+/* IEEE_R_OCTETS_OK Bit Fields */
+#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        0
+#define ENET_IEEE_R_OCTETS_OK_COUNT_WIDTH        32
+#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+/* ATCR Bit Fields */
+#define ENET_ATCR_EN_MASK                        0x1u
+#define ENET_ATCR_EN_SHIFT                       0
+#define ENET_ATCR_EN_WIDTH                       1
+#define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_EN_SHIFT))&ENET_ATCR_EN_MASK)
+#define ENET_ATCR_OFFEN_MASK                     0x4u
+#define ENET_ATCR_OFFEN_SHIFT                    2
+#define ENET_ATCR_OFFEN_WIDTH                    1
+#define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFEN_SHIFT))&ENET_ATCR_OFFEN_MASK)
+#define ENET_ATCR_OFFRST_MASK                    0x8u
+#define ENET_ATCR_OFFRST_SHIFT                   3
+#define ENET_ATCR_OFFRST_WIDTH                   1
+#define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFRST_SHIFT))&ENET_ATCR_OFFRST_MASK)
+#define ENET_ATCR_PEREN_MASK                     0x10u
+#define ENET_ATCR_PEREN_SHIFT                    4
+#define ENET_ATCR_PEREN_WIDTH                    1
+#define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PEREN_SHIFT))&ENET_ATCR_PEREN_MASK)
+#define ENET_ATCR_PINPER_MASK                    0x80u
+#define ENET_ATCR_PINPER_SHIFT                   7
+#define ENET_ATCR_PINPER_WIDTH                   1
+#define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PINPER_SHIFT))&ENET_ATCR_PINPER_MASK)
+#define ENET_ATCR_RESTART_MASK                   0x200u
+#define ENET_ATCR_RESTART_SHIFT                  9
+#define ENET_ATCR_RESTART_WIDTH                  1
+#define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_RESTART_SHIFT))&ENET_ATCR_RESTART_MASK)
+#define ENET_ATCR_CAPTURE_MASK                   0x800u
+#define ENET_ATCR_CAPTURE_SHIFT                  11
+#define ENET_ATCR_CAPTURE_WIDTH                  1
+#define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_CAPTURE_SHIFT))&ENET_ATCR_CAPTURE_MASK)
+#define ENET_ATCR_SLAVE_MASK                     0x2000u
+#define ENET_ATCR_SLAVE_SHIFT                    13
+#define ENET_ATCR_SLAVE_WIDTH                    1
+#define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_SLAVE_SHIFT))&ENET_ATCR_SLAVE_MASK)
+/* ATVR Bit Fields */
+#define ENET_ATVR_ATIME_MASK                     0xFFFFFFFFu
+#define ENET_ATVR_ATIME_SHIFT                    0
+#define ENET_ATVR_ATIME_WIDTH                    32
+#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
+/* ATOFF Bit Fields */
+#define ENET_ATOFF_OFFSET_MASK                   0xFFFFFFFFu
+#define ENET_ATOFF_OFFSET_SHIFT                  0
+#define ENET_ATOFF_OFFSET_WIDTH                  32
+#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
+/* ATPER Bit Fields */
+#define ENET_ATPER_PERIOD_MASK                   0xFFFFFFFFu
+#define ENET_ATPER_PERIOD_SHIFT                  0
+#define ENET_ATPER_PERIOD_WIDTH                  32
+#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
+/* ATCOR Bit Fields */
+#define ENET_ATCOR_COR_MASK                      0x7FFFFFFFu
+#define ENET_ATCOR_COR_SHIFT                     0
+#define ENET_ATCOR_COR_WIDTH                     31
+#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
+/* ATINC Bit Fields */
+#define ENET_ATINC_INC_MASK                      0x7Fu
+#define ENET_ATINC_INC_SHIFT                     0
+#define ENET_ATINC_INC_WIDTH                     7
+#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK                 0x7F00u
+#define ENET_ATINC_INC_CORR_SHIFT                8
+#define ENET_ATINC_INC_CORR_WIDTH                7
+#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
+/* ATSTMP Bit Fields */
+#define ENET_ATSTMP_TIMESTAMP_MASK               0xFFFFFFFFu
+#define ENET_ATSTMP_TIMESTAMP_SHIFT              0
+#define ENET_ATSTMP_TIMESTAMP_WIDTH              32
+#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
+/* TGSR Bit Fields */
+#define ENET_TGSR_TF0_MASK                       0x1u
+#define ENET_TGSR_TF0_SHIFT                      0
+#define ENET_TGSR_TF0_WIDTH                      1
+#define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF0_SHIFT))&ENET_TGSR_TF0_MASK)
+#define ENET_TGSR_TF1_MASK                       0x2u
+#define ENET_TGSR_TF1_SHIFT                      1
+#define ENET_TGSR_TF1_WIDTH                      1
+#define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF1_SHIFT))&ENET_TGSR_TF1_MASK)
+#define ENET_TGSR_TF2_MASK                       0x4u
+#define ENET_TGSR_TF2_SHIFT                      2
+#define ENET_TGSR_TF2_WIDTH                      1
+#define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF2_SHIFT))&ENET_TGSR_TF2_MASK)
+#define ENET_TGSR_TF3_MASK                       0x8u
+#define ENET_TGSR_TF3_SHIFT                      3
+#define ENET_TGSR_TF3_WIDTH                      1
+#define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF3_SHIFT))&ENET_TGSR_TF3_MASK)
+/* TCSR Bit Fields */
+#define ENET_TCSR_TDRE_MASK                      0x1u
+#define ENET_TCSR_TDRE_SHIFT                     0
+#define ENET_TCSR_TDRE_WIDTH                     1
+#define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TDRE_SHIFT))&ENET_TCSR_TDRE_MASK)
+#define ENET_TCSR_TMODE_MASK                     0x3Cu
+#define ENET_TCSR_TMODE_SHIFT                    2
+#define ENET_TCSR_TMODE_WIDTH                    4
+#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE_MASK                       0x40u
+#define ENET_TCSR_TIE_SHIFT                      6
+#define ENET_TCSR_TIE_WIDTH                      1
+#define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TIE_SHIFT))&ENET_TCSR_TIE_MASK)
+#define ENET_TCSR_TF_MASK                        0x80u
+#define ENET_TCSR_TF_SHIFT                       7
+#define ENET_TCSR_TF_WIDTH                       1
+#define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TF_SHIFT))&ENET_TCSR_TF_MASK)
+/* TCCR Bit Fields */
+#define ENET_TCCR_TCC_MASK                       0xFFFFFFFFu
+#define ENET_TCCR_TCC_SHIFT                      0
+#define ENET_TCCR_TCC_WIDTH                      32
+#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE                                (0x400C0000u)
+/** Peripheral ENET base pointer */
+#define ENET                                     ((ENET_Type *)ENET_BASE)
+#define ENET_BASE_PTR                            (ENET)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS                          { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS                           { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_Transmit_IRQS                       { ENET_Transmit_IRQn }
+#define ENET_Receive_IRQS                        { ENET_Receive_IRQn }
+#define ENET_Error_IRQS                          { ENET_Error_IRQn }
+#define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register instance definitions */
+/* ENET */
+#define ENET_EIR                                 ENET_EIR_REG(ENET)
+#define ENET_EIMR                                ENET_EIMR_REG(ENET)
+#define ENET_RDAR                                ENET_RDAR_REG(ENET)
+#define ENET_TDAR                                ENET_TDAR_REG(ENET)
+#define ENET_ECR                                 ENET_ECR_REG(ENET)
+#define ENET_MMFR                                ENET_MMFR_REG(ENET)
+#define ENET_MSCR                                ENET_MSCR_REG(ENET)
+#define ENET_MIBC                                ENET_MIBC_REG(ENET)
+#define ENET_RCR                                 ENET_RCR_REG(ENET)
+#define ENET_TCR                                 ENET_TCR_REG(ENET)
+#define ENET_PALR                                ENET_PALR_REG(ENET)
+#define ENET_PAUR                                ENET_PAUR_REG(ENET)
+#define ENET_OPD                                 ENET_OPD_REG(ENET)
+#define ENET_IAUR                                ENET_IAUR_REG(ENET)
+#define ENET_IALR                                ENET_IALR_REG(ENET)
+#define ENET_GAUR                                ENET_GAUR_REG(ENET)
+#define ENET_GALR                                ENET_GALR_REG(ENET)
+#define ENET_TFWR                                ENET_TFWR_REG(ENET)
+#define ENET_RDSR                                ENET_RDSR_REG(ENET)
+#define ENET_TDSR                                ENET_TDSR_REG(ENET)
+#define ENET_MRBR                                ENET_MRBR_REG(ENET)
+#define ENET_RSFL                                ENET_RSFL_REG(ENET)
+#define ENET_RSEM                                ENET_RSEM_REG(ENET)
+#define ENET_RAEM                                ENET_RAEM_REG(ENET)
+#define ENET_RAFL                                ENET_RAFL_REG(ENET)
+#define ENET_TSEM                                ENET_TSEM_REG(ENET)
+#define ENET_TAEM                                ENET_TAEM_REG(ENET)
+#define ENET_TAFL                                ENET_TAFL_REG(ENET)
+#define ENET_TIPG                                ENET_TIPG_REG(ENET)
+#define ENET_FTRL                                ENET_FTRL_REG(ENET)
+#define ENET_TACC                                ENET_TACC_REG(ENET)
+#define ENET_RACC                                ENET_RACC_REG(ENET)
+#define ENET_RMON_T_PACKETS                      ENET_RMON_T_PACKETS_REG(ENET)
+#define ENET_RMON_T_BC_PKT                       ENET_RMON_T_BC_PKT_REG(ENET)
+#define ENET_RMON_T_MC_PKT                       ENET_RMON_T_MC_PKT_REG(ENET)
+#define ENET_RMON_T_CRC_ALIGN                    ENET_RMON_T_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_T_UNDERSIZE                    ENET_RMON_T_UNDERSIZE_REG(ENET)
+#define ENET_RMON_T_OVERSIZE                     ENET_RMON_T_OVERSIZE_REG(ENET)
+#define ENET_RMON_T_FRAG                         ENET_RMON_T_FRAG_REG(ENET)
+#define ENET_RMON_T_JAB                          ENET_RMON_T_JAB_REG(ENET)
+#define ENET_RMON_T_COL                          ENET_RMON_T_COL_REG(ENET)
+#define ENET_RMON_T_P64                          ENET_RMON_T_P64_REG(ENET)
+#define ENET_RMON_T_P65TO127                     ENET_RMON_T_P65TO127_REG(ENET)
+#define ENET_RMON_T_P128TO255                    ENET_RMON_T_P128TO255_REG(ENET)
+#define ENET_RMON_T_P256TO511                    ENET_RMON_T_P256TO511_REG(ENET)
+#define ENET_RMON_T_P512TO1023                   ENET_RMON_T_P512TO1023_REG(ENET)
+#define ENET_RMON_T_P1024TO2047                  ENET_RMON_T_P1024TO2047_REG(ENET)
+#define ENET_RMON_T_P_GTE2048                    ENET_RMON_T_P_GTE2048_REG(ENET)
+#define ENET_RMON_T_OCTETS                       ENET_RMON_T_OCTETS_REG(ENET)
+#define ENET_IEEE_T_FRAME_OK                     ENET_IEEE_T_FRAME_OK_REG(ENET)
+#define ENET_IEEE_T_1COL                         ENET_IEEE_T_1COL_REG(ENET)
+#define ENET_IEEE_T_MCOL                         ENET_IEEE_T_MCOL_REG(ENET)
+#define ENET_IEEE_T_DEF                          ENET_IEEE_T_DEF_REG(ENET)
+#define ENET_IEEE_T_LCOL                         ENET_IEEE_T_LCOL_REG(ENET)
+#define ENET_IEEE_T_EXCOL                        ENET_IEEE_T_EXCOL_REG(ENET)
+#define ENET_IEEE_T_MACERR                       ENET_IEEE_T_MACERR_REG(ENET)
+#define ENET_IEEE_T_CSERR                        ENET_IEEE_T_CSERR_REG(ENET)
+#define ENET_IEEE_T_FDXFC                        ENET_IEEE_T_FDXFC_REG(ENET)
+#define ENET_IEEE_T_OCTETS_OK                    ENET_IEEE_T_OCTETS_OK_REG(ENET)
+#define ENET_RMON_R_PACKETS                      ENET_RMON_R_PACKETS_REG(ENET)
+#define ENET_RMON_R_BC_PKT                       ENET_RMON_R_BC_PKT_REG(ENET)
+#define ENET_RMON_R_MC_PKT                       ENET_RMON_R_MC_PKT_REG(ENET)
+#define ENET_RMON_R_CRC_ALIGN                    ENET_RMON_R_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_R_UNDERSIZE                    ENET_RMON_R_UNDERSIZE_REG(ENET)
+#define ENET_RMON_R_OVERSIZE                     ENET_RMON_R_OVERSIZE_REG(ENET)
+#define ENET_RMON_R_FRAG                         ENET_RMON_R_FRAG_REG(ENET)
+#define ENET_RMON_R_JAB                          ENET_RMON_R_JAB_REG(ENET)
+#define ENET_RMON_R_P64                          ENET_RMON_R_P64_REG(ENET)
+#define ENET_RMON_R_P65TO127                     ENET_RMON_R_P65TO127_REG(ENET)
+#define ENET_RMON_R_P128TO255                    ENET_RMON_R_P128TO255_REG(ENET)
+#define ENET_RMON_R_P256TO511                    ENET_RMON_R_P256TO511_REG(ENET)
+#define ENET_RMON_R_P512TO1023                   ENET_RMON_R_P512TO1023_REG(ENET)
+#define ENET_RMON_R_P1024TO2047                  ENET_RMON_R_P1024TO2047_REG(ENET)
+#define ENET_RMON_R_P_GTE2048                    ENET_RMON_R_P_GTE2048_REG(ENET)
+#define ENET_RMON_R_OCTETS                       ENET_RMON_R_OCTETS_REG(ENET)
+#define ENET_IEEE_R_DROP                         ENET_IEEE_R_DROP_REG(ENET)
+#define ENET_IEEE_R_FRAME_OK                     ENET_IEEE_R_FRAME_OK_REG(ENET)
+#define ENET_IEEE_R_CRC                          ENET_IEEE_R_CRC_REG(ENET)
+#define ENET_IEEE_R_ALIGN                        ENET_IEEE_R_ALIGN_REG(ENET)
+#define ENET_IEEE_R_MACERR                       ENET_IEEE_R_MACERR_REG(ENET)
+#define ENET_IEEE_R_FDXFC                        ENET_IEEE_R_FDXFC_REG(ENET)
+#define ENET_IEEE_R_OCTETS_OK                    ENET_IEEE_R_OCTETS_OK_REG(ENET)
+#define ENET_ATCR                                ENET_ATCR_REG(ENET)
+#define ENET_ATVR                                ENET_ATVR_REG(ENET)
+#define ENET_ATOFF                               ENET_ATOFF_REG(ENET)
+#define ENET_ATPER                               ENET_ATPER_REG(ENET)
+#define ENET_ATCOR                               ENET_ATCOR_REG(ENET)
+#define ENET_ATINC                               ENET_ATINC_REG(ENET)
+#define ENET_ATSTMP                              ENET_ATSTMP_REG(ENET)
+#define ENET_TGSR                                ENET_TGSR_REG(ENET)
+#define ENET_TCSR0                               ENET_TCSR_REG(ENET,0)
+#define ENET_TCCR0                               ENET_TCCR_REG(ENET,0)
+#define ENET_TCSR1                               ENET_TCSR_REG(ENET,1)
+#define ENET_TCCR1                               ENET_TCCR_REG(ENET,1)
+#define ENET_TCSR2                               ENET_TCSR_REG(ENET,2)
+#define ENET_TCCR2                               ENET_TCCR_REG(ENET,2)
+#define ENET_TCSR3                               ENET_TCSR_REG(ENET,3)
+#define ENET_TCCR3                               ENET_TCCR_REG(ENET,3)
+
+/* ENET - Register array accessors */
+#define ENET_TCSR(index)                         ENET_TCSR_REG(ENET,index)
+#define ENET_TCCR(index)                         ENET_TCCR_REG(ENET,index)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
+} EWM_Type, *EWM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register accessors */
+#define EWM_CTRL_REG(base)                       ((base)->CTRL)
+#define EWM_SERV_REG(base)                       ((base)->SERV)
+#define EWM_CMPL_REG(base)                       ((base)->CMPL)
+#define EWM_CMPH_REG(base)                       ((base)->CMPH)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK                      0x1u
+#define EWM_CTRL_EWMEN_SHIFT                     0
+#define EWM_CTRL_EWMEN_WIDTH                     1
+#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK                      0x2u
+#define EWM_CTRL_ASSIN_SHIFT                     1
+#define EWM_CTRL_ASSIN_WIDTH                     1
+#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK                       0x4u
+#define EWM_CTRL_INEN_SHIFT                      2
+#define EWM_CTRL_INEN_WIDTH                      1
+#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK                      0x8u
+#define EWM_CTRL_INTEN_SHIFT                     3
+#define EWM_CTRL_INTEN_WIDTH                     1
+#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK                    0xFFu
+#define EWM_SERV_SERVICE_SHIFT                   0
+#define EWM_SERV_SERVICE_WIDTH                   8
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK                   0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT                  0
+#define EWM_CMPL_COMPAREL_WIDTH                  8
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK                   0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT                  0
+#define EWM_CMPH_COMPAREH_WIDTH                  8
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE                                 (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM                                      ((EWM_Type *)EWM_BASE)
+#define EWM_BASE_PTR                             (EWM)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS                           { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS                            { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS                                 { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register instance definitions */
+/* EWM */
+#define EWM_CTRL                                 EWM_CTRL_REG(EWM)
+#define EWM_SERV                                 EWM_SERV_REG(EWM)
+#define EWM_CMPL                                 EWM_CMPL_REG(EWM)
+#define EWM_CMPH                                 EWM_CMPH_REG(EWM)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0xC */
+    __IO uint32_t CSAR;                              /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+    __IO uint32_t CSMR;                              /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+    __IO uint32_t CSCR;                              /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+  } CS[6];
+       uint8_t RESERVED_0[24];
+  __IO uint32_t CSPMCR;                            /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type, *FB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register accessors */
+#define FB_CSAR_REG(base,index)                  ((base)->CS[index].CSAR)
+#define FB_CSAR_COUNT                            6
+#define FB_CSMR_REG(base,index)                  ((base)->CS[index].CSMR)
+#define FB_CSMR_COUNT                            6
+#define FB_CSCR_REG(base,index)                  ((base)->CS[index].CSCR)
+#define FB_CSCR_COUNT                            6
+#define FB_CSPMCR_REG(base)                      ((base)->CSPMCR)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK                          0xFFFF0000u
+#define FB_CSAR_BA_SHIFT                         16
+#define FB_CSAR_BA_WIDTH                         16
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
+/* CSMR Bit Fields */
+#define FB_CSMR_V_MASK                           0x1u
+#define FB_CSMR_V_SHIFT                          0
+#define FB_CSMR_V_WIDTH                          1
+#define FB_CSMR_V(x)                             (((uint32_t)(((uint32_t)(x))<<FB_CSMR_V_SHIFT))&FB_CSMR_V_MASK)
+#define FB_CSMR_WP_MASK                          0x100u
+#define FB_CSMR_WP_SHIFT                         8
+#define FB_CSMR_WP_WIDTH                         1
+#define FB_CSMR_WP(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSMR_WP_SHIFT))&FB_CSMR_WP_MASK)
+#define FB_CSMR_BAM_MASK                         0xFFFF0000u
+#define FB_CSMR_BAM_SHIFT                        16
+#define FB_CSMR_BAM_WIDTH                        16
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
+/* CSCR Bit Fields */
+#define FB_CSCR_BSTW_MASK                        0x8u
+#define FB_CSCR_BSTW_SHIFT                       3
+#define FB_CSCR_BSTW_WIDTH                       1
+#define FB_CSCR_BSTW(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTW_SHIFT))&FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTR_MASK                        0x10u
+#define FB_CSCR_BSTR_SHIFT                       4
+#define FB_CSCR_BSTR_WIDTH                       1
+#define FB_CSCR_BSTR(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTR_SHIFT))&FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BEM_MASK                         0x20u
+#define FB_CSCR_BEM_SHIFT                        5
+#define FB_CSCR_BEM_WIDTH                        1
+#define FB_CSCR_BEM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BEM_SHIFT))&FB_CSCR_BEM_MASK)
+#define FB_CSCR_PS_MASK                          0xC0u
+#define FB_CSCR_PS_SHIFT                         6
+#define FB_CSCR_PS_WIDTH                         2
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK                          0x100u
+#define FB_CSCR_AA_SHIFT                         8
+#define FB_CSCR_AA_WIDTH                         1
+#define FB_CSCR_AA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_AA_SHIFT))&FB_CSCR_AA_MASK)
+#define FB_CSCR_BLS_MASK                         0x200u
+#define FB_CSCR_BLS_SHIFT                        9
+#define FB_CSCR_BLS_WIDTH                        1
+#define FB_CSCR_BLS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BLS_SHIFT))&FB_CSCR_BLS_MASK)
+#define FB_CSCR_WS_MASK                          0xFC00u
+#define FB_CSCR_WS_SHIFT                         10
+#define FB_CSCR_WS_WIDTH                         6
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        0x30000u
+#define FB_CSCR_WRAH_SHIFT                       16
+#define FB_CSCR_WRAH_WIDTH                       2
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        0xC0000u
+#define FB_CSCR_RDAH_SHIFT                       18
+#define FB_CSCR_RDAH_WIDTH                       2
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        0x300000u
+#define FB_CSCR_ASET_SHIFT                       20
+#define FB_CSCR_ASET_WIDTH                       2
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK                        0x400000u
+#define FB_CSCR_EXTS_SHIFT                       22
+#define FB_CSCR_EXTS_WIDTH                       1
+#define FB_CSCR_EXTS(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_EXTS_SHIFT))&FB_CSCR_EXTS_MASK)
+#define FB_CSCR_SWSEN_MASK                       0x800000u
+#define FB_CSCR_SWSEN_SHIFT                      23
+#define FB_CSCR_SWSEN_WIDTH                      1
+#define FB_CSCR_SWSEN(x)                         (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWSEN_SHIFT))&FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWS_MASK                         0xFC000000u
+#define FB_CSCR_SWS_SHIFT                        26
+#define FB_CSCR_SWS_WIDTH                        6
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
+/* CSPMCR Bit Fields */
+#define FB_CSPMCR_GROUP5_MASK                    0xF000u
+#define FB_CSPMCR_GROUP5_SHIFT                   12
+#define FB_CSPMCR_GROUP5_WIDTH                   4
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    0xF0000u
+#define FB_CSPMCR_GROUP4_SHIFT                   16
+#define FB_CSPMCR_GROUP4_WIDTH                   4
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    0xF00000u
+#define FB_CSPMCR_GROUP3_SHIFT                   20
+#define FB_CSPMCR_GROUP3_WIDTH                   4
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    0xF000000u
+#define FB_CSPMCR_GROUP2_SHIFT                   24
+#define FB_CSPMCR_GROUP2_WIDTH                   4
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    0xF0000000u
+#define FB_CSPMCR_GROUP1_SHIFT                   28
+#define FB_CSPMCR_GROUP1_WIDTH                   4
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE                                  (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB                                       ((FB_Type *)FB_BASE)
+#define FB_BASE_PTR                              (FB)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS                            { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS                             { FB }
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register instance definitions */
+/* FB */
+#define FB_CSAR0                                 FB_CSAR_REG(FB,0)
+#define FB_CSMR0                                 FB_CSMR_REG(FB,0)
+#define FB_CSCR0                                 FB_CSCR_REG(FB,0)
+#define FB_CSAR1                                 FB_CSAR_REG(FB,1)
+#define FB_CSMR1                                 FB_CSMR_REG(FB,1)
+#define FB_CSCR1                                 FB_CSCR_REG(FB,1)
+#define FB_CSAR2                                 FB_CSAR_REG(FB,2)
+#define FB_CSMR2                                 FB_CSMR_REG(FB,2)
+#define FB_CSCR2                                 FB_CSCR_REG(FB,2)
+#define FB_CSAR3                                 FB_CSAR_REG(FB,3)
+#define FB_CSMR3                                 FB_CSMR_REG(FB,3)
+#define FB_CSCR3                                 FB_CSCR_REG(FB,3)
+#define FB_CSAR4                                 FB_CSAR_REG(FB,4)
+#define FB_CSMR4                                 FB_CSMR_REG(FB,4)
+#define FB_CSCR4                                 FB_CSCR_REG(FB,4)
+#define FB_CSAR5                                 FB_CSAR_REG(FB,5)
+#define FB_CSMR5                                 FB_CSMR_REG(FB,5)
+#define FB_CSCR5                                 FB_CSCR_REG(FB,5)
+#define FB_CSPMCR                                FB_CSPMCR_REG(FB)
+
+/* FB - Register array accessors */
+#define FB_CSAR(index)                           FB_CSAR_REG(FB,index)
+#define FB_CSMR(index)                           FB_CSMR_REG(FB,index)
+#define FB_CSCR(index)                           FB_CSCR_REG(FB,index)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PFAPR;                             /**< Flash Access Protection Register, offset: 0x0 */
+  __IO uint32_t PFB0CR;                            /**< Flash Bank 0 Control Register, offset: 0x4 */
+  __IO uint32_t PFB1CR;                            /**< Flash Bank 1 Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[244];
+  __IO uint32_t TAGVDW0S[4];                       /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+  __IO uint32_t TAGVDW1S[4];                       /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
+  __IO uint32_t TAGVDW2S[4];                       /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+  __IO uint32_t TAGVDW3S[4];                       /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
+       uint8_t RESERVED_1[192];
+  struct {                                         /* offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_U;                            /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_L;                            /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
+  } SET[4][4];
+} FMC_Type, *FMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register accessors */
+#define FMC_PFAPR_REG(base)                      ((base)->PFAPR)
+#define FMC_PFB0CR_REG(base)                     ((base)->PFB0CR)
+#define FMC_PFB1CR_REG(base)                     ((base)->PFB1CR)
+#define FMC_TAGVDW0S_REG(base,index)             ((base)->TAGVDW0S[index])
+#define FMC_TAGVDW0S_COUNT                       4
+#define FMC_TAGVDW1S_REG(base,index)             ((base)->TAGVDW1S[index])
+#define FMC_TAGVDW1S_COUNT                       4
+#define FMC_TAGVDW2S_REG(base,index)             ((base)->TAGVDW2S[index])
+#define FMC_TAGVDW2S_COUNT                       4
+#define FMC_TAGVDW3S_REG(base,index)             ((base)->TAGVDW3S[index])
+#define FMC_TAGVDW3S_COUNT                       4
+#define FMC_DATA_U_REG(base,index,index2)        ((base)->SET[index][index2].DATA_U)
+#define FMC_DATA_U_COUNT                         4
+#define FMC_DATA_U_COUNT2                        4
+#define FMC_DATA_L_REG(base,index,index2)        ((base)->SET[index][index2].DATA_L)
+#define FMC_DATA_L_COUNT                         4
+#define FMC_DATA_L_COUNT2                        4
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK                      0x3u
+#define FMC_PFAPR_M0AP_SHIFT                     0
+#define FMC_PFAPR_M0AP_WIDTH                     2
+#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK                      0xCu
+#define FMC_PFAPR_M1AP_SHIFT                     2
+#define FMC_PFAPR_M1AP_WIDTH                     2
+#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK                      0x30u
+#define FMC_PFAPR_M2AP_SHIFT                     4
+#define FMC_PFAPR_M2AP_WIDTH                     2
+#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK                      0xC0u
+#define FMC_PFAPR_M3AP_SHIFT                     6
+#define FMC_PFAPR_M3AP_WIDTH                     2
+#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK                      0x300u
+#define FMC_PFAPR_M4AP_SHIFT                     8
+#define FMC_PFAPR_M4AP_WIDTH                     2
+#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK                      0xC00u
+#define FMC_PFAPR_M5AP_SHIFT                     10
+#define FMC_PFAPR_M5AP_WIDTH                     2
+#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK                      0x3000u
+#define FMC_PFAPR_M6AP_SHIFT                     12
+#define FMC_PFAPR_M6AP_WIDTH                     2
+#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK                      0xC000u
+#define FMC_PFAPR_M7AP_SHIFT                     14
+#define FMC_PFAPR_M7AP_WIDTH                     2
+#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK                     0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT                    16
+#define FMC_PFAPR_M0PFD_WIDTH                    1
+#define FMC_PFAPR_M0PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0PFD_SHIFT))&FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK                     0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT                    17
+#define FMC_PFAPR_M1PFD_WIDTH                    1
+#define FMC_PFAPR_M1PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1PFD_SHIFT))&FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK                     0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT                    18
+#define FMC_PFAPR_M2PFD_WIDTH                    1
+#define FMC_PFAPR_M2PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2PFD_SHIFT))&FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK                     0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT                    19
+#define FMC_PFAPR_M3PFD_WIDTH                    1
+#define FMC_PFAPR_M3PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3PFD_SHIFT))&FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M4PFD_MASK                     0x100000u
+#define FMC_PFAPR_M4PFD_SHIFT                    20
+#define FMC_PFAPR_M4PFD_WIDTH                    1
+#define FMC_PFAPR_M4PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4PFD_SHIFT))&FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M5PFD_MASK                     0x200000u
+#define FMC_PFAPR_M5PFD_SHIFT                    21
+#define FMC_PFAPR_M5PFD_WIDTH                    1
+#define FMC_PFAPR_M5PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5PFD_SHIFT))&FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M6PFD_MASK                     0x400000u
+#define FMC_PFAPR_M6PFD_SHIFT                    22
+#define FMC_PFAPR_M6PFD_WIDTH                    1
+#define FMC_PFAPR_M6PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6PFD_SHIFT))&FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M7PFD_MASK                     0x800000u
+#define FMC_PFAPR_M7PFD_SHIFT                    23
+#define FMC_PFAPR_M7PFD_WIDTH                    1
+#define FMC_PFAPR_M7PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7PFD_SHIFT))&FMC_PFAPR_M7PFD_MASK)
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK                   0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT                  0
+#define FMC_PFB0CR_B0SEBE_WIDTH                  1
+#define FMC_PFB0CR_B0SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0SEBE_SHIFT))&FMC_PFB0CR_B0SEBE_MASK)
+#define FMC_PFB0CR_B0IPE_MASK                    0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT                   1
+#define FMC_PFB0CR_B0IPE_WIDTH                   1
+#define FMC_PFB0CR_B0IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0IPE_SHIFT))&FMC_PFB0CR_B0IPE_MASK)
+#define FMC_PFB0CR_B0DPE_MASK                    0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT                   2
+#define FMC_PFB0CR_B0DPE_WIDTH                   1
+#define FMC_PFB0CR_B0DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DPE_SHIFT))&FMC_PFB0CR_B0DPE_MASK)
+#define FMC_PFB0CR_B0ICE_MASK                    0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT                   3
+#define FMC_PFB0CR_B0ICE_WIDTH                   1
+#define FMC_PFB0CR_B0ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0ICE_SHIFT))&FMC_PFB0CR_B0ICE_MASK)
+#define FMC_PFB0CR_B0DCE_MASK                    0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT                   4
+#define FMC_PFB0CR_B0DCE_WIDTH                   1
+#define FMC_PFB0CR_B0DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DCE_SHIFT))&FMC_PFB0CR_B0DCE_MASK)
+#define FMC_PFB0CR_CRC_MASK                      0xE0u
+#define FMC_PFB0CR_CRC_SHIFT                     5
+#define FMC_PFB0CR_CRC_WIDTH                     3
+#define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK                     0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT                    17
+#define FMC_PFB0CR_B0MW_WIDTH                    2
+#define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK                  0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT                 19
+#define FMC_PFB0CR_S_B_INV_WIDTH                 1
+#define FMC_PFB0CR_S_B_INV(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_S_B_INV_SHIFT))&FMC_PFB0CR_S_B_INV_MASK)
+#define FMC_PFB0CR_CINV_WAY_MASK                 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT                20
+#define FMC_PFB0CR_CINV_WAY_WIDTH                4
+#define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK                 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT                24
+#define FMC_PFB0CR_CLCK_WAY_WIDTH                4
+#define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK                   0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT                  28
+#define FMC_PFB0CR_B0RWSC_WIDTH                  4
+#define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* PFB1CR Bit Fields */
+#define FMC_PFB1CR_B1SEBE_MASK                   0x1u
+#define FMC_PFB1CR_B1SEBE_SHIFT                  0
+#define FMC_PFB1CR_B1SEBE_WIDTH                  1
+#define FMC_PFB1CR_B1SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1SEBE_SHIFT))&FMC_PFB1CR_B1SEBE_MASK)
+#define FMC_PFB1CR_B1IPE_MASK                    0x2u
+#define FMC_PFB1CR_B1IPE_SHIFT                   1
+#define FMC_PFB1CR_B1IPE_WIDTH                   1
+#define FMC_PFB1CR_B1IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1IPE_SHIFT))&FMC_PFB1CR_B1IPE_MASK)
+#define FMC_PFB1CR_B1DPE_MASK                    0x4u
+#define FMC_PFB1CR_B1DPE_SHIFT                   2
+#define FMC_PFB1CR_B1DPE_WIDTH                   1
+#define FMC_PFB1CR_B1DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DPE_SHIFT))&FMC_PFB1CR_B1DPE_MASK)
+#define FMC_PFB1CR_B1ICE_MASK                    0x8u
+#define FMC_PFB1CR_B1ICE_SHIFT                   3
+#define FMC_PFB1CR_B1ICE_WIDTH                   1
+#define FMC_PFB1CR_B1ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1ICE_SHIFT))&FMC_PFB1CR_B1ICE_MASK)
+#define FMC_PFB1CR_B1DCE_MASK                    0x10u
+#define FMC_PFB1CR_B1DCE_SHIFT                   4
+#define FMC_PFB1CR_B1DCE_WIDTH                   1
+#define FMC_PFB1CR_B1DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DCE_SHIFT))&FMC_PFB1CR_B1DCE_MASK)
+#define FMC_PFB1CR_B1MW_MASK                     0x60000u
+#define FMC_PFB1CR_B1MW_SHIFT                    17
+#define FMC_PFB1CR_B1MW_WIDTH                    2
+#define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK                   0xF0000000u
+#define FMC_PFB1CR_B1RWSC_SHIFT                  28
+#define FMC_PFB1CR_B1RWSC_WIDTH                  4
+#define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
+/* TAGVDW0S Bit Fields */
+#define FMC_TAGVDW0S_valid_MASK                  0x1u
+#define FMC_TAGVDW0S_valid_SHIFT                 0
+#define FMC_TAGVDW0S_valid_WIDTH                 1
+#define FMC_TAGVDW0S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_valid_SHIFT))&FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW0S_tag_SHIFT                   5
+#define FMC_TAGVDW0S_tag_WIDTH                   14
+#define FMC_TAGVDW0S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
+/* TAGVDW1S Bit Fields */
+#define FMC_TAGVDW1S_valid_MASK                  0x1u
+#define FMC_TAGVDW1S_valid_SHIFT                 0
+#define FMC_TAGVDW1S_valid_WIDTH                 1
+#define FMC_TAGVDW1S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_valid_SHIFT))&FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW1S_tag_SHIFT                   5
+#define FMC_TAGVDW1S_tag_WIDTH                   14
+#define FMC_TAGVDW1S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
+/* TAGVDW2S Bit Fields */
+#define FMC_TAGVDW2S_valid_MASK                  0x1u
+#define FMC_TAGVDW2S_valid_SHIFT                 0
+#define FMC_TAGVDW2S_valid_WIDTH                 1
+#define FMC_TAGVDW2S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_valid_SHIFT))&FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW2S_tag_SHIFT                   5
+#define FMC_TAGVDW2S_tag_WIDTH                   14
+#define FMC_TAGVDW2S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
+/* TAGVDW3S Bit Fields */
+#define FMC_TAGVDW3S_valid_MASK                  0x1u
+#define FMC_TAGVDW3S_valid_SHIFT                 0
+#define FMC_TAGVDW3S_valid_WIDTH                 1
+#define FMC_TAGVDW3S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_valid_SHIFT))&FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW3S_tag_SHIFT                   5
+#define FMC_TAGVDW3S_tag_WIDTH                   14
+#define FMC_TAGVDW3S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
+/* DATA_U Bit Fields */
+#define FMC_DATA_U_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_U_data_SHIFT                    0
+#define FMC_DATA_U_data_WIDTH                    32
+#define FMC_DATA_U_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
+/* DATA_L Bit Fields */
+#define FMC_DATA_L_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_L_data_SHIFT                    0
+#define FMC_DATA_L_data_WIDTH                    32
+#define FMC_DATA_L_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE                                 (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC                                      ((FMC_Type *)FMC_BASE)
+#define FMC_BASE_PTR                             (FMC)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS                           { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS                            { FMC }
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register instance definitions */
+/* FMC */
+#define FMC_PFAPR                                FMC_PFAPR_REG(FMC)
+#define FMC_PFB0CR                               FMC_PFB0CR_REG(FMC)
+#define FMC_PFB1CR                               FMC_PFB1CR_REG(FMC)
+#define FMC_TAGVDW0S0                            FMC_TAGVDW0S_REG(FMC,0)
+#define FMC_TAGVDW0S1                            FMC_TAGVDW0S_REG(FMC,1)
+#define FMC_TAGVDW0S2                            FMC_TAGVDW0S_REG(FMC,2)
+#define FMC_TAGVDW0S3                            FMC_TAGVDW0S_REG(FMC,3)
+#define FMC_TAGVDW1S0                            FMC_TAGVDW1S_REG(FMC,0)
+#define FMC_TAGVDW1S1                            FMC_TAGVDW1S_REG(FMC,1)
+#define FMC_TAGVDW1S2                            FMC_TAGVDW1S_REG(FMC,2)
+#define FMC_TAGVDW1S3                            FMC_TAGVDW1S_REG(FMC,3)
+#define FMC_TAGVDW2S0                            FMC_TAGVDW2S_REG(FMC,0)
+#define FMC_TAGVDW2S1                            FMC_TAGVDW2S_REG(FMC,1)
+#define FMC_TAGVDW2S2                            FMC_TAGVDW2S_REG(FMC,2)
+#define FMC_TAGVDW2S3                            FMC_TAGVDW2S_REG(FMC,3)
+#define FMC_TAGVDW3S0                            FMC_TAGVDW3S_REG(FMC,0)
+#define FMC_TAGVDW3S1                            FMC_TAGVDW3S_REG(FMC,1)
+#define FMC_TAGVDW3S2                            FMC_TAGVDW3S_REG(FMC,2)
+#define FMC_TAGVDW3S3                            FMC_TAGVDW3S_REG(FMC,3)
+#define FMC_DATAW0S0U                            FMC_DATA_U_REG(FMC,0,0)
+#define FMC_DATAW0S0L                            FMC_DATA_L_REG(FMC,0,0)
+#define FMC_DATAW0S1U                            FMC_DATA_U_REG(FMC,0,1)
+#define FMC_DATAW0S1L                            FMC_DATA_L_REG(FMC,0,1)
+#define FMC_DATAW0S2U                            FMC_DATA_U_REG(FMC,0,2)
+#define FMC_DATAW0S2L                            FMC_DATA_L_REG(FMC,0,2)
+#define FMC_DATAW0S3U                            FMC_DATA_U_REG(FMC,0,3)
+#define FMC_DATAW0S3L                            FMC_DATA_L_REG(FMC,0,3)
+#define FMC_DATAW1S0U                            FMC_DATA_U_REG(FMC,1,0)
+#define FMC_DATAW1S0L                            FMC_DATA_L_REG(FMC,1,0)
+#define FMC_DATAW1S1U                            FMC_DATA_U_REG(FMC,1,1)
+#define FMC_DATAW1S1L                            FMC_DATA_L_REG(FMC,1,1)
+#define FMC_DATAW1S2U                            FMC_DATA_U_REG(FMC,1,2)
+#define FMC_DATAW1S2L                            FMC_DATA_L_REG(FMC,1,2)
+#define FMC_DATAW1S3U                            FMC_DATA_U_REG(FMC,1,3)
+#define FMC_DATAW1S3L                            FMC_DATA_L_REG(FMC,1,3)
+#define FMC_DATAW2S0U                            FMC_DATA_U_REG(FMC,2,0)
+#define FMC_DATAW2S0L                            FMC_DATA_L_REG(FMC,2,0)
+#define FMC_DATAW2S1U                            FMC_DATA_U_REG(FMC,2,1)
+#define FMC_DATAW2S1L                            FMC_DATA_L_REG(FMC,2,1)
+#define FMC_DATAW2S2U                            FMC_DATA_U_REG(FMC,2,2)
+#define FMC_DATAW2S2L                            FMC_DATA_L_REG(FMC,2,2)
+#define FMC_DATAW2S3U                            FMC_DATA_U_REG(FMC,2,3)
+#define FMC_DATAW2S3L                            FMC_DATA_L_REG(FMC,2,3)
+#define FMC_DATAW3S0U                            FMC_DATA_U_REG(FMC,3,0)
+#define FMC_DATAW3S0L                            FMC_DATA_L_REG(FMC,3,0)
+#define FMC_DATAW3S1U                            FMC_DATA_U_REG(FMC,3,1)
+#define FMC_DATAW3S1L                            FMC_DATA_L_REG(FMC,3,1)
+#define FMC_DATAW3S2U                            FMC_DATA_U_REG(FMC,3,2)
+#define FMC_DATAW3S2L                            FMC_DATA_L_REG(FMC,3,2)
+#define FMC_DATAW3S3U                            FMC_DATA_U_REG(FMC,3,3)
+#define FMC_DATAW3S3L                            FMC_DATA_L_REG(FMC,3,3)
+
+/* FMC - Register array accessors */
+#define FMC_TAGVDW0S(index)                      FMC_TAGVDW0S_REG(FMC,index)
+#define FMC_TAGVDW1S(index)                      FMC_TAGVDW1S_REG(FMC,index)
+#define FMC_TAGVDW2S(index)                      FMC_TAGVDW2S_REG(FMC,index)
+#define FMC_TAGVDW3S(index)                      FMC_TAGVDW3S_REG(FMC,index)
+#define FMC_DATA_U(index,index2)                 FMC_DATA_U_REG(FMC,index,index2)
+#define FMC_DATA_L(index,index2)                 FMC_DATA_L_REG(FMC,index,index2)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t FEPROT;                             /**< EEPROM Protection Register, offset: 0x16 */
+  __IO uint8_t FDPROT;                             /**< Data Flash Protection Register, offset: 0x17 */
+} FTFE_Type, *FTFE_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register accessors */
+#define FTFE_FSTAT_REG(base)                     ((base)->FSTAT)
+#define FTFE_FCNFG_REG(base)                     ((base)->FCNFG)
+#define FTFE_FSEC_REG(base)                      ((base)->FSEC)
+#define FTFE_FOPT_REG(base)                      ((base)->FOPT)
+#define FTFE_FCCOB3_REG(base)                    ((base)->FCCOB3)
+#define FTFE_FCCOB2_REG(base)                    ((base)->FCCOB2)
+#define FTFE_FCCOB1_REG(base)                    ((base)->FCCOB1)
+#define FTFE_FCCOB0_REG(base)                    ((base)->FCCOB0)
+#define FTFE_FCCOB7_REG(base)                    ((base)->FCCOB7)
+#define FTFE_FCCOB6_REG(base)                    ((base)->FCCOB6)
+#define FTFE_FCCOB5_REG(base)                    ((base)->FCCOB5)
+#define FTFE_FCCOB4_REG(base)                    ((base)->FCCOB4)
+#define FTFE_FCCOBB_REG(base)                    ((base)->FCCOBB)
+#define FTFE_FCCOBA_REG(base)                    ((base)->FCCOBA)
+#define FTFE_FCCOB9_REG(base)                    ((base)->FCCOB9)
+#define FTFE_FCCOB8_REG(base)                    ((base)->FCCOB8)
+#define FTFE_FPROT3_REG(base)                    ((base)->FPROT3)
+#define FTFE_FPROT2_REG(base)                    ((base)->FPROT2)
+#define FTFE_FPROT1_REG(base)                    ((base)->FPROT1)
+#define FTFE_FPROT0_REG(base)                    ((base)->FPROT0)
+#define FTFE_FEPROT_REG(base)                    ((base)->FEPROT)
+#define FTFE_FDPROT_REG(base)                    ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFE_FSTAT_MGSTAT0_MASK                  0x1u
+#define FTFE_FSTAT_MGSTAT0_SHIFT                 0
+#define FTFE_FSTAT_MGSTAT0_WIDTH                 1
+#define FTFE_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_MGSTAT0_SHIFT))&FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_FPVIOL_MASK                   0x10u
+#define FTFE_FSTAT_FPVIOL_SHIFT                  4
+#define FTFE_FSTAT_FPVIOL_WIDTH                  1
+#define FTFE_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_FPVIOL_SHIFT))&FTFE_FSTAT_FPVIOL_MASK)
+#define FTFE_FSTAT_ACCERR_MASK                   0x20u
+#define FTFE_FSTAT_ACCERR_SHIFT                  5
+#define FTFE_FSTAT_ACCERR_WIDTH                  1
+#define FTFE_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_ACCERR_SHIFT))&FTFE_FSTAT_ACCERR_MASK)
+#define FTFE_FSTAT_RDCOLERR_MASK                 0x40u
+#define FTFE_FSTAT_RDCOLERR_SHIFT                6
+#define FTFE_FSTAT_RDCOLERR_WIDTH                1
+#define FTFE_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_RDCOLERR_SHIFT))&FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFE_FSTAT_CCIF_MASK                     0x80u
+#define FTFE_FSTAT_CCIF_SHIFT                    7
+#define FTFE_FSTAT_CCIF_WIDTH                    1
+#define FTFE_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_CCIF_SHIFT))&FTFE_FSTAT_CCIF_MASK)
+/* FCNFG Bit Fields */
+#define FTFE_FCNFG_EEERDY_MASK                   0x1u
+#define FTFE_FCNFG_EEERDY_SHIFT                  0
+#define FTFE_FCNFG_EEERDY_WIDTH                  1
+#define FTFE_FCNFG_EEERDY(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_EEERDY_SHIFT))&FTFE_FCNFG_EEERDY_MASK)
+#define FTFE_FCNFG_RAMRDY_MASK                   0x2u
+#define FTFE_FCNFG_RAMRDY_SHIFT                  1
+#define FTFE_FCNFG_RAMRDY_WIDTH                  1
+#define FTFE_FCNFG_RAMRDY(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RAMRDY_SHIFT))&FTFE_FCNFG_RAMRDY_MASK)
+#define FTFE_FCNFG_PFLSH_MASK                    0x4u
+#define FTFE_FCNFG_PFLSH_SHIFT                   2
+#define FTFE_FCNFG_PFLSH_WIDTH                   1
+#define FTFE_FCNFG_PFLSH(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_PFLSH_SHIFT))&FTFE_FCNFG_PFLSH_MASK)
+#define FTFE_FCNFG_SWAP_MASK                     0x8u
+#define FTFE_FCNFG_SWAP_SHIFT                    3
+#define FTFE_FCNFG_SWAP_WIDTH                    1
+#define FTFE_FCNFG_SWAP(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_SWAP_SHIFT))&FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_ERSSUSP_MASK                  0x10u
+#define FTFE_FCNFG_ERSSUSP_SHIFT                 4
+#define FTFE_FCNFG_ERSSUSP_WIDTH                 1
+#define FTFE_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSSUSP_SHIFT))&FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSAREQ_MASK                  0x20u
+#define FTFE_FCNFG_ERSAREQ_SHIFT                 5
+#define FTFE_FCNFG_ERSAREQ_WIDTH                 1
+#define FTFE_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSAREQ_SHIFT))&FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_RDCOLLIE_MASK                 0x40u
+#define FTFE_FCNFG_RDCOLLIE_SHIFT                6
+#define FTFE_FCNFG_RDCOLLIE_WIDTH                1
+#define FTFE_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RDCOLLIE_SHIFT))&FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_CCIE_MASK                     0x80u
+#define FTFE_FCNFG_CCIE_SHIFT                    7
+#define FTFE_FCNFG_CCIE_WIDTH                    1
+#define FTFE_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_CCIE_SHIFT))&FTFE_FCNFG_CCIE_MASK)
+/* FSEC Bit Fields */
+#define FTFE_FSEC_SEC_MASK                       0x3u
+#define FTFE_FSEC_SEC_SHIFT                      0
+#define FTFE_FSEC_SEC_WIDTH                      2
+#define FTFE_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK                    0xCu
+#define FTFE_FSEC_FSLACC_SHIFT                   2
+#define FTFE_FSEC_FSLACC_WIDTH                   2
+#define FTFE_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK                      0x30u
+#define FTFE_FSEC_MEEN_SHIFT                     4
+#define FTFE_FSEC_MEEN_WIDTH                     2
+#define FTFE_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK                     0xC0u
+#define FTFE_FSEC_KEYEN_SHIFT                    6
+#define FTFE_FSEC_KEYEN_WIDTH                    2
+#define FTFE_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFE_FOPT_OPT_MASK                       0xFFu
+#define FTFE_FOPT_OPT_SHIFT                      0
+#define FTFE_FOPT_OPT_WIDTH                      8
+#define FTFE_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFE_FCCOB3_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB3_CCOBn_SHIFT                  0
+#define FTFE_FCCOB3_CCOBn_WIDTH                  8
+#define FTFE_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFE_FCCOB2_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB2_CCOBn_SHIFT                  0
+#define FTFE_FCCOB2_CCOBn_WIDTH                  8
+#define FTFE_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFE_FCCOB1_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB1_CCOBn_SHIFT                  0
+#define FTFE_FCCOB1_CCOBn_WIDTH                  8
+#define FTFE_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFE_FCCOB0_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB0_CCOBn_SHIFT                  0
+#define FTFE_FCCOB0_CCOBn_WIDTH                  8
+#define FTFE_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFE_FCCOB7_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB7_CCOBn_SHIFT                  0
+#define FTFE_FCCOB7_CCOBn_WIDTH                  8
+#define FTFE_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFE_FCCOB6_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB6_CCOBn_SHIFT                  0
+#define FTFE_FCCOB6_CCOBn_WIDTH                  8
+#define FTFE_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFE_FCCOB5_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB5_CCOBn_SHIFT                  0
+#define FTFE_FCCOB5_CCOBn_WIDTH                  8
+#define FTFE_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFE_FCCOB4_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB4_CCOBn_SHIFT                  0
+#define FTFE_FCCOB4_CCOBn_WIDTH                  8
+#define FTFE_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFE_FCCOBB_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBB_CCOBn_SHIFT                  0
+#define FTFE_FCCOBB_CCOBn_WIDTH                  8
+#define FTFE_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFE_FCCOBA_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBA_CCOBn_SHIFT                  0
+#define FTFE_FCCOBA_CCOBn_WIDTH                  8
+#define FTFE_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFE_FCCOB9_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB9_CCOBn_SHIFT                  0
+#define FTFE_FCCOB9_CCOBn_WIDTH                  8
+#define FTFE_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFE_FCCOB8_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB8_CCOBn_SHIFT                  0
+#define FTFE_FCCOB8_CCOBn_WIDTH                  8
+#define FTFE_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFE_FPROT3_PROT_MASK                    0xFFu
+#define FTFE_FPROT3_PROT_SHIFT                   0
+#define FTFE_FPROT3_PROT_WIDTH                   8
+#define FTFE_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFE_FPROT2_PROT_MASK                    0xFFu
+#define FTFE_FPROT2_PROT_SHIFT                   0
+#define FTFE_FPROT2_PROT_WIDTH                   8
+#define FTFE_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFE_FPROT1_PROT_MASK                    0xFFu
+#define FTFE_FPROT1_PROT_SHIFT                   0
+#define FTFE_FPROT1_PROT_WIDTH                   8
+#define FTFE_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFE_FPROT0_PROT_MASK                    0xFFu
+#define FTFE_FPROT0_PROT_SHIFT                   0
+#define FTFE_FPROT0_PROT_WIDTH                   8
+#define FTFE_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFE_FEPROT_EPROT_MASK                   0xFFu
+#define FTFE_FEPROT_EPROT_SHIFT                  0
+#define FTFE_FEPROT_EPROT_WIDTH                  8
+#define FTFE_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFE_FDPROT_DPROT_MASK                   0xFFu
+#define FTFE_FDPROT_DPROT_SHIFT                  0
+#define FTFE_FDPROT_DPROT_WIDTH                  8
+#define FTFE_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE                                (0x40020000u)
+/** Peripheral FTFE base pointer */
+#define FTFE                                     ((FTFE_Type *)FTFE_BASE)
+#define FTFE_BASE_PTR                            (FTFE)
+/** Array initializer of FTFE peripheral base addresses */
+#define FTFE_BASE_ADDRS                          { FTFE_BASE }
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASE_PTRS                           { FTFE }
+/** Interrupt vectors for the FTFE peripheral type */
+#define FTFE_COMMAND_COMPLETE_IRQS               { FTFE_IRQn }
+#define FTFE_READ_COLLISION_IRQS                 { Read_Collision_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register instance definitions */
+/* FTFE */
+#define FTFE_FSTAT                               FTFE_FSTAT_REG(FTFE)
+#define FTFE_FCNFG                               FTFE_FCNFG_REG(FTFE)
+#define FTFE_FSEC                                FTFE_FSEC_REG(FTFE)
+#define FTFE_FOPT                                FTFE_FOPT_REG(FTFE)
+#define FTFE_FCCOB3                              FTFE_FCCOB3_REG(FTFE)
+#define FTFE_FCCOB2                              FTFE_FCCOB2_REG(FTFE)
+#define FTFE_FCCOB1                              FTFE_FCCOB1_REG(FTFE)
+#define FTFE_FCCOB0                              FTFE_FCCOB0_REG(FTFE)
+#define FTFE_FCCOB7                              FTFE_FCCOB7_REG(FTFE)
+#define FTFE_FCCOB6                              FTFE_FCCOB6_REG(FTFE)
+#define FTFE_FCCOB5                              FTFE_FCCOB5_REG(FTFE)
+#define FTFE_FCCOB4                              FTFE_FCCOB4_REG(FTFE)
+#define FTFE_FCCOBB                              FTFE_FCCOBB_REG(FTFE)
+#define FTFE_FCCOBA                              FTFE_FCCOBA_REG(FTFE)
+#define FTFE_FCCOB9                              FTFE_FCCOB9_REG(FTFE)
+#define FTFE_FCCOB8                              FTFE_FCCOB8_REG(FTFE)
+#define FTFE_FPROT3                              FTFE_FPROT3_REG(FTFE)
+#define FTFE_FPROT2                              FTFE_FPROT2_REG(FTFE)
+#define FTFE_FPROT1                              FTFE_FPROT1_REG(FTFE)
+#define FTFE_FPROT0                              FTFE_FPROT0_REG(FTFE)
+#define FTFE_FEPROT                              FTFE_FEPROT_REG(FTFE)
+#define FTFE_FDPROT                              FTFE_FDPROT_REG(FTFE)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[8];
+  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
+  __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
+  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
+  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
+  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
+  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
+  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
+  __IO uint32_t DEADTIME;                          /**< Deadtime Insertion Control, offset: 0x68 */
+  __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
+  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
+  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
+  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
+  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+  __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
+  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
+  __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
+  __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
+  __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type, *FTM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register accessors */
+#define FTM_SC_REG(base)                         ((base)->SC)
+#define FTM_CNT_REG(base)                        ((base)->CNT)
+#define FTM_MOD_REG(base)                        ((base)->MOD)
+#define FTM_CnSC_REG(base,index)                 ((base)->CONTROLS[index].CnSC)
+#define FTM_CnSC_COUNT                           8
+#define FTM_CnV_REG(base,index)                  ((base)->CONTROLS[index].CnV)
+#define FTM_CnV_COUNT                            8
+#define FTM_CNTIN_REG(base)                      ((base)->CNTIN)
+#define FTM_STATUS_REG(base)                     ((base)->STATUS)
+#define FTM_MODE_REG(base)                       ((base)->MODE)
+#define FTM_SYNC_REG(base)                       ((base)->SYNC)
+#define FTM_OUTINIT_REG(base)                    ((base)->OUTINIT)
+#define FTM_OUTMASK_REG(base)                    ((base)->OUTMASK)
+#define FTM_COMBINE_REG(base)                    ((base)->COMBINE)
+#define FTM_DEADTIME_REG(base)                   ((base)->DEADTIME)
+#define FTM_EXTTRIG_REG(base)                    ((base)->EXTTRIG)
+#define FTM_POL_REG(base)                        ((base)->POL)
+#define FTM_FMS_REG(base)                        ((base)->FMS)
+#define FTM_FILTER_REG(base)                     ((base)->FILTER)
+#define FTM_FLTCTRL_REG(base)                    ((base)->FLTCTRL)
+#define FTM_QDCTRL_REG(base)                     ((base)->QDCTRL)
+#define FTM_CONF_REG(base)                       ((base)->CONF)
+#define FTM_FLTPOL_REG(base)                     ((base)->FLTPOL)
+#define FTM_SYNCONF_REG(base)                    ((base)->SYNCONF)
+#define FTM_INVCTRL_REG(base)                    ((base)->INVCTRL)
+#define FTM_SWOCTRL_REG(base)                    ((base)->SWOCTRL)
+#define FTM_PWMLOAD_REG(base)                    ((base)->PWMLOAD)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK                           0x7u
+#define FTM_SC_PS_SHIFT                          0
+#define FTM_SC_PS_WIDTH                          3
+#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK                         0x18u
+#define FTM_SC_CLKS_SHIFT                        3
+#define FTM_SC_CLKS_WIDTH                        2
+#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK                        0x20u
+#define FTM_SC_CPWMS_SHIFT                       5
+#define FTM_SC_CPWMS_WIDTH                       1
+#define FTM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK                         0x40u
+#define FTM_SC_TOIE_SHIFT                        6
+#define FTM_SC_TOIE_WIDTH                        1
+#define FTM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK                          0x80u
+#define FTM_SC_TOF_SHIFT                         7
+#define FTM_SC_TOF_WIDTH                         1
+#define FTM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK                       0xFFFFu
+#define FTM_CNT_COUNT_SHIFT                      0
+#define FTM_CNT_COUNT_WIDTH                      16
+#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK                         0xFFFFu
+#define FTM_MOD_MOD_SHIFT                        0
+#define FTM_MOD_MOD_WIDTH                        16
+#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK                        0x1u
+#define FTM_CnSC_DMA_SHIFT                       0
+#define FTM_CnSC_DMA_WIDTH                       1
+#define FTM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ELSA_MASK                       0x4u
+#define FTM_CnSC_ELSA_SHIFT                      2
+#define FTM_CnSC_ELSA_WIDTH                      1
+#define FTM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK                       0x8u
+#define FTM_CnSC_ELSB_SHIFT                      3
+#define FTM_CnSC_ELSB_WIDTH                      1
+#define FTM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK                        0x10u
+#define FTM_CnSC_MSA_SHIFT                       4
+#define FTM_CnSC_MSA_WIDTH                       1
+#define FTM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK                        0x20u
+#define FTM_CnSC_MSB_SHIFT                       5
+#define FTM_CnSC_MSB_WIDTH                       1
+#define FTM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK                       0x40u
+#define FTM_CnSC_CHIE_SHIFT                      6
+#define FTM_CnSC_CHIE_WIDTH                      1
+#define FTM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK                        0x80u
+#define FTM_CnSC_CHF_SHIFT                       7
+#define FTM_CnSC_CHF_WIDTH                       1
+#define FTM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK                         0xFFFFu
+#define FTM_CnV_VAL_SHIFT                        0
+#define FTM_CnV_VAL_WIDTH                        16
+#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK                      0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT                     0
+#define FTM_CNTIN_INIT_WIDTH                     16
+#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK                     0x1u
+#define FTM_STATUS_CH0F_SHIFT                    0
+#define FTM_STATUS_CH0F_WIDTH                    1
+#define FTM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK                     0x2u
+#define FTM_STATUS_CH1F_SHIFT                    1
+#define FTM_STATUS_CH1F_WIDTH                    1
+#define FTM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK                     0x4u
+#define FTM_STATUS_CH2F_SHIFT                    2
+#define FTM_STATUS_CH2F_WIDTH                    1
+#define FTM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK                     0x8u
+#define FTM_STATUS_CH3F_SHIFT                    3
+#define FTM_STATUS_CH3F_WIDTH                    1
+#define FTM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK                     0x10u
+#define FTM_STATUS_CH4F_SHIFT                    4
+#define FTM_STATUS_CH4F_WIDTH                    1
+#define FTM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK                     0x20u
+#define FTM_STATUS_CH5F_SHIFT                    5
+#define FTM_STATUS_CH5F_WIDTH                    1
+#define FTM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK                     0x40u
+#define FTM_STATUS_CH6F_SHIFT                    6
+#define FTM_STATUS_CH6F_WIDTH                    1
+#define FTM_STATUS_CH6F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK                     0x80u
+#define FTM_STATUS_CH7F_SHIFT                    7
+#define FTM_STATUS_CH7F_WIDTH                    1
+#define FTM_STATUS_CH7F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK                      0x1u
+#define FTM_MODE_FTMEN_SHIFT                     0
+#define FTM_MODE_FTMEN_WIDTH                     1
+#define FTM_MODE_FTMEN(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK                       0x2u
+#define FTM_MODE_INIT_SHIFT                      1
+#define FTM_MODE_INIT_WIDTH                      1
+#define FTM_MODE_INIT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK                      0x4u
+#define FTM_MODE_WPDIS_SHIFT                     2
+#define FTM_MODE_WPDIS_WIDTH                     1
+#define FTM_MODE_WPDIS(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK                    0x8u
+#define FTM_MODE_PWMSYNC_SHIFT                   3
+#define FTM_MODE_PWMSYNC_WIDTH                   1
+#define FTM_MODE_PWMSYNC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK                    0x10u
+#define FTM_MODE_CAPTEST_SHIFT                   4
+#define FTM_MODE_CAPTEST_WIDTH                   1
+#define FTM_MODE_CAPTEST(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK                     0x60u
+#define FTM_MODE_FAULTM_SHIFT                    5
+#define FTM_MODE_FAULTM_WIDTH                    2
+#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK                    0x80u
+#define FTM_MODE_FAULTIE_SHIFT                   7
+#define FTM_MODE_FAULTIE_WIDTH                   1
+#define FTM_MODE_FAULTIE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK                     0x1u
+#define FTM_SYNC_CNTMIN_SHIFT                    0
+#define FTM_SYNC_CNTMIN_WIDTH                    1
+#define FTM_SYNC_CNTMIN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK                     0x2u
+#define FTM_SYNC_CNTMAX_SHIFT                    1
+#define FTM_SYNC_CNTMAX_WIDTH                    1
+#define FTM_SYNC_CNTMAX(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK                     0x4u
+#define FTM_SYNC_REINIT_SHIFT                    2
+#define FTM_SYNC_REINIT_WIDTH                    1
+#define FTM_SYNC_REINIT(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK                    0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT                   3
+#define FTM_SYNC_SYNCHOM_WIDTH                   1
+#define FTM_SYNC_SYNCHOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK                      0x10u
+#define FTM_SYNC_TRIG0_SHIFT                     4
+#define FTM_SYNC_TRIG0_WIDTH                     1
+#define FTM_SYNC_TRIG0(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK                      0x20u
+#define FTM_SYNC_TRIG1_SHIFT                     5
+#define FTM_SYNC_TRIG1_WIDTH                     1
+#define FTM_SYNC_TRIG1(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK                      0x40u
+#define FTM_SYNC_TRIG2_SHIFT                     6
+#define FTM_SYNC_TRIG2_WIDTH                     1
+#define FTM_SYNC_TRIG2(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK                     0x80u
+#define FTM_SYNC_SWSYNC_SHIFT                    7
+#define FTM_SYNC_SWSYNC_WIDTH                    1
+#define FTM_SYNC_SWSYNC(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK                   0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT                  0
+#define FTM_OUTINIT_CH0OI_WIDTH                  1
+#define FTM_OUTINIT_CH0OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK                   0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT                  1
+#define FTM_OUTINIT_CH1OI_WIDTH                  1
+#define FTM_OUTINIT_CH1OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK                   0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT                  2
+#define FTM_OUTINIT_CH2OI_WIDTH                  1
+#define FTM_OUTINIT_CH2OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK                   0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT                  3
+#define FTM_OUTINIT_CH3OI_WIDTH                  1
+#define FTM_OUTINIT_CH3OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK                   0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT                  4
+#define FTM_OUTINIT_CH4OI_WIDTH                  1
+#define FTM_OUTINIT_CH4OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK                   0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT                  5
+#define FTM_OUTINIT_CH5OI_WIDTH                  1
+#define FTM_OUTINIT_CH5OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK                   0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT                  6
+#define FTM_OUTINIT_CH6OI_WIDTH                  1
+#define FTM_OUTINIT_CH6OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK                   0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT                  7
+#define FTM_OUTINIT_CH7OI_WIDTH                  1
+#define FTM_OUTINIT_CH7OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK                   0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT                  0
+#define FTM_OUTMASK_CH0OM_WIDTH                  1
+#define FTM_OUTMASK_CH0OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK                   0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT                  1
+#define FTM_OUTMASK_CH1OM_WIDTH                  1
+#define FTM_OUTMASK_CH1OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK                   0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT                  2
+#define FTM_OUTMASK_CH2OM_WIDTH                  1
+#define FTM_OUTMASK_CH2OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK                   0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT                  3
+#define FTM_OUTMASK_CH3OM_WIDTH                  1
+#define FTM_OUTMASK_CH3OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK                   0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT                  4
+#define FTM_OUTMASK_CH4OM_WIDTH                  1
+#define FTM_OUTMASK_CH4OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK                   0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT                  5
+#define FTM_OUTMASK_CH5OM_WIDTH                  1
+#define FTM_OUTMASK_CH5OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK                   0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT                  6
+#define FTM_OUTMASK_CH6OM_WIDTH                  1
+#define FTM_OUTMASK_CH6OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK                   0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT                  7
+#define FTM_OUTMASK_CH7OM_WIDTH                  1
+#define FTM_OUTMASK_CH7OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK                0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT               0
+#define FTM_COMBINE_COMBINE0_WIDTH               1
+#define FTM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK                   0x2u
+#define FTM_COMBINE_COMP0_SHIFT                  1
+#define FTM_COMBINE_COMP0_WIDTH                  1
+#define FTM_COMBINE_COMP0(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK                0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT               2
+#define FTM_COMBINE_DECAPEN0_WIDTH               1
+#define FTM_COMBINE_DECAPEN0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK                  0x8u
+#define FTM_COMBINE_DECAP0_SHIFT                 3
+#define FTM_COMBINE_DECAP0_WIDTH                 1
+#define FTM_COMBINE_DECAP0(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK                   0x10u
+#define FTM_COMBINE_DTEN0_SHIFT                  4
+#define FTM_COMBINE_DTEN0_WIDTH                  1
+#define FTM_COMBINE_DTEN0(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK                 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT                5
+#define FTM_COMBINE_SYNCEN0_WIDTH                1
+#define FTM_COMBINE_SYNCEN0(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK                0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT               6
+#define FTM_COMBINE_FAULTEN0_WIDTH               1
+#define FTM_COMBINE_FAULTEN0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK                0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT               8
+#define FTM_COMBINE_COMBINE1_WIDTH               1
+#define FTM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK                   0x200u
+#define FTM_COMBINE_COMP1_SHIFT                  9
+#define FTM_COMBINE_COMP1_WIDTH                  1
+#define FTM_COMBINE_COMP1(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK                0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT               10
+#define FTM_COMBINE_DECAPEN1_WIDTH               1
+#define FTM_COMBINE_DECAPEN1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK                  0x800u
+#define FTM_COMBINE_DECAP1_SHIFT                 11
+#define FTM_COMBINE_DECAP1_WIDTH                 1
+#define FTM_COMBINE_DECAP1(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK                   0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT                  12
+#define FTM_COMBINE_DTEN1_WIDTH                  1
+#define FTM_COMBINE_DTEN1(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK                 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT                13
+#define FTM_COMBINE_SYNCEN1_WIDTH                1
+#define FTM_COMBINE_SYNCEN1(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK                0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT               14
+#define FTM_COMBINE_FAULTEN1_WIDTH               1
+#define FTM_COMBINE_FAULTEN1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK                0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT               16
+#define FTM_COMBINE_COMBINE2_WIDTH               1
+#define FTM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK                   0x20000u
+#define FTM_COMBINE_COMP2_SHIFT                  17
+#define FTM_COMBINE_COMP2_WIDTH                  1
+#define FTM_COMBINE_COMP2(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK                0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT               18
+#define FTM_COMBINE_DECAPEN2_WIDTH               1
+#define FTM_COMBINE_DECAPEN2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK                  0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT                 19
+#define FTM_COMBINE_DECAP2_WIDTH                 1
+#define FTM_COMBINE_DECAP2(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK                   0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT                  20
+#define FTM_COMBINE_DTEN2_WIDTH                  1
+#define FTM_COMBINE_DTEN2(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK                 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT                21
+#define FTM_COMBINE_SYNCEN2_WIDTH                1
+#define FTM_COMBINE_SYNCEN2(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK                0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT               22
+#define FTM_COMBINE_FAULTEN2_WIDTH               1
+#define FTM_COMBINE_FAULTEN2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK                0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT               24
+#define FTM_COMBINE_COMBINE3_WIDTH               1
+#define FTM_COMBINE_COMBINE3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK                   0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT                  25
+#define FTM_COMBINE_COMP3_WIDTH                  1
+#define FTM_COMBINE_COMP3(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK                0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT               26
+#define FTM_COMBINE_DECAPEN3_WIDTH               1
+#define FTM_COMBINE_DECAPEN3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK                  0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT                 27
+#define FTM_COMBINE_DECAP3_WIDTH                 1
+#define FTM_COMBINE_DECAP3(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK                   0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT                  28
+#define FTM_COMBINE_DTEN3_WIDTH                  1
+#define FTM_COMBINE_DTEN3(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK                 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT                29
+#define FTM_COMBINE_SYNCEN3_WIDTH                1
+#define FTM_COMBINE_SYNCEN3(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK                0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT               30
+#define FTM_COMBINE_FAULTEN3_WIDTH               1
+#define FTM_COMBINE_FAULTEN3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK                  0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT                 0
+#define FTM_DEADTIME_DTVAL_WIDTH                 6
+#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK                   0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT                  6
+#define FTM_DEADTIME_DTPS_WIDTH                  2
+#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK                 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT                0
+#define FTM_EXTTRIG_CH2TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH2TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK                 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT                1
+#define FTM_EXTTRIG_CH3TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH3TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK                 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT                2
+#define FTM_EXTTRIG_CH4TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH4TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK                 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT                3
+#define FTM_EXTTRIG_CH5TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH5TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK                 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT                4
+#define FTM_EXTTRIG_CH0TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH0TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK                 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT                5
+#define FTM_EXTTRIG_CH1TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH1TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK              0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT             6
+#define FTM_EXTTRIG_INITTRIGEN_WIDTH             1
+#define FTM_EXTTRIG_INITTRIGEN(x)                (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK                   0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT                  7
+#define FTM_EXTTRIG_TRIGF_WIDTH                  1
+#define FTM_EXTTRIG_TRIGF(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK                        0x1u
+#define FTM_POL_POL0_SHIFT                       0
+#define FTM_POL_POL0_WIDTH                       1
+#define FTM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK                        0x2u
+#define FTM_POL_POL1_SHIFT                       1
+#define FTM_POL_POL1_WIDTH                       1
+#define FTM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK                        0x4u
+#define FTM_POL_POL2_SHIFT                       2
+#define FTM_POL_POL2_WIDTH                       1
+#define FTM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK                        0x8u
+#define FTM_POL_POL3_SHIFT                       3
+#define FTM_POL_POL3_WIDTH                       1
+#define FTM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK                        0x10u
+#define FTM_POL_POL4_SHIFT                       4
+#define FTM_POL_POL4_WIDTH                       1
+#define FTM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK                        0x20u
+#define FTM_POL_POL5_SHIFT                       5
+#define FTM_POL_POL5_WIDTH                       1
+#define FTM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK                        0x40u
+#define FTM_POL_POL6_SHIFT                       6
+#define FTM_POL_POL6_WIDTH                       1
+#define FTM_POL_POL6(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK                        0x80u
+#define FTM_POL_POL7_SHIFT                       7
+#define FTM_POL_POL7_WIDTH                       1
+#define FTM_POL_POL7(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK                     0x1u
+#define FTM_FMS_FAULTF0_SHIFT                    0
+#define FTM_FMS_FAULTF0_WIDTH                    1
+#define FTM_FMS_FAULTF0(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK                     0x2u
+#define FTM_FMS_FAULTF1_SHIFT                    1
+#define FTM_FMS_FAULTF1_WIDTH                    1
+#define FTM_FMS_FAULTF1(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK                     0x4u
+#define FTM_FMS_FAULTF2_SHIFT                    2
+#define FTM_FMS_FAULTF2_WIDTH                    1
+#define FTM_FMS_FAULTF2(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK                     0x8u
+#define FTM_FMS_FAULTF3_SHIFT                    3
+#define FTM_FMS_FAULTF3_WIDTH                    1
+#define FTM_FMS_FAULTF3(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK                     0x20u
+#define FTM_FMS_FAULTIN_SHIFT                    5
+#define FTM_FMS_FAULTIN_WIDTH                    1
+#define FTM_FMS_FAULTIN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK                        0x40u
+#define FTM_FMS_WPEN_SHIFT                       6
+#define FTM_FMS_WPEN_WIDTH                       1
+#define FTM_FMS_WPEN(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK                      0x80u
+#define FTM_FMS_FAULTF_SHIFT                     7
+#define FTM_FMS_FAULTF_WIDTH                     1
+#define FTM_FMS_FAULTF(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK                  0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT                 0
+#define FTM_FILTER_CH0FVAL_WIDTH                 4
+#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK                  0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT                 4
+#define FTM_FILTER_CH1FVAL_WIDTH                 4
+#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK                  0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT                 8
+#define FTM_FILTER_CH2FVAL_WIDTH                 4
+#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK                  0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT                 12
+#define FTM_FILTER_CH3FVAL_WIDTH                 4
+#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK                0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT               0
+#define FTM_FLTCTRL_FAULT0EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT0EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK                0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT               1
+#define FTM_FLTCTRL_FAULT1EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT1EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK                0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT               2
+#define FTM_FLTCTRL_FAULT2EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT2EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK                0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT               3
+#define FTM_FLTCTRL_FAULT3EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT3EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK                0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT               4
+#define FTM_FLTCTRL_FFLTR0EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR0EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK                0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT               5
+#define FTM_FLTCTRL_FFLTR1EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR1EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK                0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT               6
+#define FTM_FLTCTRL_FFLTR2EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR2EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK                0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT               7
+#define FTM_FLTCTRL_FFLTR3EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR3EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK                   0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT                  8
+#define FTM_FLTCTRL_FFVAL_WIDTH                  4
+#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK                   0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT                  0
+#define FTM_QDCTRL_QUADEN_WIDTH                  1
+#define FTM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK                   0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT                  1
+#define FTM_QDCTRL_TOFDIR_WIDTH                  1
+#define FTM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK                   0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT                  2
+#define FTM_QDCTRL_QUADIR_WIDTH                  1
+#define FTM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK                 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT                3
+#define FTM_QDCTRL_QUADMODE_WIDTH                1
+#define FTM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK                   0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT                  4
+#define FTM_QDCTRL_PHBPOL_WIDTH                  1
+#define FTM_QDCTRL_PHBPOL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK                   0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT                  5
+#define FTM_QDCTRL_PHAPOL_WIDTH                  1
+#define FTM_QDCTRL_PHAPOL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK                0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT               6
+#define FTM_QDCTRL_PHBFLTREN_WIDTH               1
+#define FTM_QDCTRL_PHBFLTREN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK                0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT               7
+#define FTM_QDCTRL_PHAFLTREN_WIDTH               1
+#define FTM_QDCTRL_PHAFLTREN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK                     0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT                    0
+#define FTM_CONF_NUMTOF_WIDTH                    5
+#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK                    0xC0u
+#define FTM_CONF_BDMMODE_SHIFT                   6
+#define FTM_CONF_BDMMODE_WIDTH                   2
+#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK                     0x200u
+#define FTM_CONF_GTBEEN_SHIFT                    9
+#define FTM_CONF_GTBEEN_WIDTH                    1
+#define FTM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK                    0x400u
+#define FTM_CONF_GTBEOUT_SHIFT                   10
+#define FTM_CONF_GTBEOUT_WIDTH                   1
+#define FTM_CONF_GTBEOUT(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK                  0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT                 0
+#define FTM_FLTPOL_FLT0POL_WIDTH                 1
+#define FTM_FLTPOL_FLT0POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK                  0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT                 1
+#define FTM_FLTPOL_FLT1POL_WIDTH                 1
+#define FTM_FLTPOL_FLT1POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK                  0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT                 2
+#define FTM_FLTPOL_FLT2POL_WIDTH                 1
+#define FTM_FLTPOL_FLT2POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK                  0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT                 3
+#define FTM_FLTPOL_FLT3POL_WIDTH                 1
+#define FTM_FLTPOL_FLT3POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK              0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT             0
+#define FTM_SYNCONF_HWTRIGMODE_WIDTH             1
+#define FTM_SYNCONF_HWTRIGMODE(x)                (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK                  0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT                 2
+#define FTM_SYNCONF_CNTINC_WIDTH                 1
+#define FTM_SYNCONF_CNTINC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK                    0x10u
+#define FTM_SYNCONF_INVC_SHIFT                   4
+#define FTM_SYNCONF_INVC_WIDTH                   1
+#define FTM_SYNCONF_INVC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK                    0x20u
+#define FTM_SYNCONF_SWOC_SHIFT                   5
+#define FTM_SYNCONF_SWOC_WIDTH                   1
+#define FTM_SYNCONF_SWOC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK                0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT               7
+#define FTM_SYNCONF_SYNCMODE_WIDTH               1
+#define FTM_SYNCONF_SYNCMODE(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK                0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT               8
+#define FTM_SYNCONF_SWRSTCNT_WIDTH               1
+#define FTM_SYNCONF_SWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK                 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT                9
+#define FTM_SYNCONF_SWWRBUF_WIDTH                1
+#define FTM_SYNCONF_SWWRBUF(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK                    0x400u
+#define FTM_SYNCONF_SWOM_SHIFT                   10
+#define FTM_SYNCONF_SWOM_WIDTH                   1
+#define FTM_SYNCONF_SWOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK                  0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT                 11
+#define FTM_SYNCONF_SWINVC_WIDTH                 1
+#define FTM_SYNCONF_SWINVC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK                   0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT                  12
+#define FTM_SYNCONF_SWSOC_WIDTH                  1
+#define FTM_SYNCONF_SWSOC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK                0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT               16
+#define FTM_SYNCONF_HWRSTCNT_WIDTH               1
+#define FTM_SYNCONF_HWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK                 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT                17
+#define FTM_SYNCONF_HWWRBUF_WIDTH                1
+#define FTM_SYNCONF_HWWRBUF(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK                    0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT                   18
+#define FTM_SYNCONF_HWOM_WIDTH                   1
+#define FTM_SYNCONF_HWOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK                  0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT                 19
+#define FTM_SYNCONF_HWINVC_WIDTH                 1
+#define FTM_SYNCONF_HWINVC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK                   0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT                  20
+#define FTM_SYNCONF_HWSOC_WIDTH                  1
+#define FTM_SYNCONF_HWSOC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK                  0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT                 0
+#define FTM_INVCTRL_INV0EN_WIDTH                 1
+#define FTM_INVCTRL_INV0EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK                  0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT                 1
+#define FTM_INVCTRL_INV1EN_WIDTH                 1
+#define FTM_INVCTRL_INV1EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK                  0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT                 2
+#define FTM_INVCTRL_INV2EN_WIDTH                 1
+#define FTM_INVCTRL_INV2EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK                  0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT                 3
+#define FTM_INVCTRL_INV3EN_WIDTH                 1
+#define FTM_INVCTRL_INV3EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK                   0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT                  0
+#define FTM_SWOCTRL_CH0OC_WIDTH                  1
+#define FTM_SWOCTRL_CH0OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK                   0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT                  1
+#define FTM_SWOCTRL_CH1OC_WIDTH                  1
+#define FTM_SWOCTRL_CH1OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK                   0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT                  2
+#define FTM_SWOCTRL_CH2OC_WIDTH                  1
+#define FTM_SWOCTRL_CH2OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK                   0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT                  3
+#define FTM_SWOCTRL_CH3OC_WIDTH                  1
+#define FTM_SWOCTRL_CH3OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK                   0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT                  4
+#define FTM_SWOCTRL_CH4OC_WIDTH                  1
+#define FTM_SWOCTRL_CH4OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK                   0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT                  5
+#define FTM_SWOCTRL_CH5OC_WIDTH                  1
+#define FTM_SWOCTRL_CH5OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK                   0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT                  6
+#define FTM_SWOCTRL_CH6OC_WIDTH                  1
+#define FTM_SWOCTRL_CH6OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK                   0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT                  7
+#define FTM_SWOCTRL_CH7OC_WIDTH                  1
+#define FTM_SWOCTRL_CH7OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK                  0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT                 8
+#define FTM_SWOCTRL_CH0OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH0OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK                  0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT                 9
+#define FTM_SWOCTRL_CH1OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH1OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK                  0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT                 10
+#define FTM_SWOCTRL_CH2OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH2OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK                  0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT                 11
+#define FTM_SWOCTRL_CH3OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH3OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK                  0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT                 12
+#define FTM_SWOCTRL_CH4OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH4OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK                  0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT                 13
+#define FTM_SWOCTRL_CH5OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH5OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK                  0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT                 14
+#define FTM_SWOCTRL_CH6OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH6OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK                  0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT                 15
+#define FTM_SWOCTRL_CH7OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH7OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK                  0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT                 0
+#define FTM_PWMLOAD_CH0SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH0SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK                  0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT                 1
+#define FTM_PWMLOAD_CH1SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH1SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK                  0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT                 2
+#define FTM_PWMLOAD_CH2SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH2SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK                  0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT                 3
+#define FTM_PWMLOAD_CH3SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH3SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK                  0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT                 4
+#define FTM_PWMLOAD_CH4SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH4SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK                  0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT                 5
+#define FTM_PWMLOAD_CH5SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH5SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK                  0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT                 6
+#define FTM_PWMLOAD_CH6SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH6SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK                  0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT                 7
+#define FTM_PWMLOAD_CH7SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH7SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK                    0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT                   9
+#define FTM_PWMLOAD_LDOK_WIDTH                   1
+#define FTM_PWMLOAD_LDOK(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE                                (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0                                     ((FTM_Type *)FTM0_BASE)
+#define FTM0_BASE_PTR                            (FTM0)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE                                (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1                                     ((FTM_Type *)FTM1_BASE)
+#define FTM1_BASE_PTR                            (FTM1)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE                                (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2                                     ((FTM_Type *)FTM2_BASE)
+#define FTM2_BASE_PTR                            (FTM2)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE                                (0x400B9000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3                                     ((FTM_Type *)FTM3_BASE)
+#define FTM3_BASE_PTR                            (FTM3)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS                           { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS                            { FTM0, FTM1, FTM2, FTM3 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS                                 { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register instance definitions */
+/* FTM0 */
+#define FTM0_SC                                  FTM_SC_REG(FTM0)
+#define FTM0_CNT                                 FTM_CNT_REG(FTM0)
+#define FTM0_MOD                                 FTM_MOD_REG(FTM0)
+#define FTM0_C0SC                                FTM_CnSC_REG(FTM0,0)
+#define FTM0_C0V                                 FTM_CnV_REG(FTM0,0)
+#define FTM0_C1SC                                FTM_CnSC_REG(FTM0,1)
+#define FTM0_C1V                                 FTM_CnV_REG(FTM0,1)
+#define FTM0_C2SC                                FTM_CnSC_REG(FTM0,2)
+#define FTM0_C2V                                 FTM_CnV_REG(FTM0,2)
+#define FTM0_C3SC                                FTM_CnSC_REG(FTM0,3)
+#define FTM0_C3V                                 FTM_CnV_REG(FTM0,3)
+#define FTM0_C4SC                                FTM_CnSC_REG(FTM0,4)
+#define FTM0_C4V                                 FTM_CnV_REG(FTM0,4)
+#define FTM0_C5SC                                FTM_CnSC_REG(FTM0,5)
+#define FTM0_C5V                                 FTM_CnV_REG(FTM0,5)
+#define FTM0_C6SC                                FTM_CnSC_REG(FTM0,6)
+#define FTM0_C6V                                 FTM_CnV_REG(FTM0,6)
+#define FTM0_C7SC                                FTM_CnSC_REG(FTM0,7)
+#define FTM0_C7V                                 FTM_CnV_REG(FTM0,7)
+#define FTM0_CNTIN                               FTM_CNTIN_REG(FTM0)
+#define FTM0_STATUS                              FTM_STATUS_REG(FTM0)
+#define FTM0_MODE                                FTM_MODE_REG(FTM0)
+#define FTM0_SYNC                                FTM_SYNC_REG(FTM0)
+#define FTM0_OUTINIT                             FTM_OUTINIT_REG(FTM0)
+#define FTM0_OUTMASK                             FTM_OUTMASK_REG(FTM0)
+#define FTM0_COMBINE                             FTM_COMBINE_REG(FTM0)
+#define FTM0_DEADTIME                            FTM_DEADTIME_REG(FTM0)
+#define FTM0_EXTTRIG                             FTM_EXTTRIG_REG(FTM0)
+#define FTM0_POL                                 FTM_POL_REG(FTM0)
+#define FTM0_FMS                                 FTM_FMS_REG(FTM0)
+#define FTM0_FILTER                              FTM_FILTER_REG(FTM0)
+#define FTM0_FLTCTRL                             FTM_FLTCTRL_REG(FTM0)
+#define FTM0_QDCTRL                              FTM_QDCTRL_REG(FTM0)
+#define FTM0_CONF                                FTM_CONF_REG(FTM0)
+#define FTM0_FLTPOL                              FTM_FLTPOL_REG(FTM0)
+#define FTM0_SYNCONF                             FTM_SYNCONF_REG(FTM0)
+#define FTM0_INVCTRL                             FTM_INVCTRL_REG(FTM0)
+#define FTM0_SWOCTRL                             FTM_SWOCTRL_REG(FTM0)
+#define FTM0_PWMLOAD                             FTM_PWMLOAD_REG(FTM0)
+/* FTM1 */
+#define FTM1_SC                                  FTM_SC_REG(FTM1)
+#define FTM1_CNT                                 FTM_CNT_REG(FTM1)
+#define FTM1_MOD                                 FTM_MOD_REG(FTM1)
+#define FTM1_C0SC                                FTM_CnSC_REG(FTM1,0)
+#define FTM1_C0V                                 FTM_CnV_REG(FTM1,0)
+#define FTM1_C1SC                                FTM_CnSC_REG(FTM1,1)
+#define FTM1_C1V                                 FTM_CnV_REG(FTM1,1)
+#define FTM1_CNTIN                               FTM_CNTIN_REG(FTM1)
+#define FTM1_STATUS                              FTM_STATUS_REG(FTM1)
+#define FTM1_MODE                                FTM_MODE_REG(FTM1)
+#define FTM1_SYNC                                FTM_SYNC_REG(FTM1)
+#define FTM1_OUTINIT                             FTM_OUTINIT_REG(FTM1)
+#define FTM1_OUTMASK                             FTM_OUTMASK_REG(FTM1)
+#define FTM1_COMBINE                             FTM_COMBINE_REG(FTM1)
+#define FTM1_DEADTIME                            FTM_DEADTIME_REG(FTM1)
+#define FTM1_EXTTRIG                             FTM_EXTTRIG_REG(FTM1)
+#define FTM1_POL                                 FTM_POL_REG(FTM1)
+#define FTM1_FMS                                 FTM_FMS_REG(FTM1)
+#define FTM1_FILTER                              FTM_FILTER_REG(FTM1)
+#define FTM1_FLTCTRL                             FTM_FLTCTRL_REG(FTM1)
+#define FTM1_QDCTRL                              FTM_QDCTRL_REG(FTM1)
+#define FTM1_CONF                                FTM_CONF_REG(FTM1)
+#define FTM1_FLTPOL                              FTM_FLTPOL_REG(FTM1)
+#define FTM1_SYNCONF                             FTM_SYNCONF_REG(FTM1)
+#define FTM1_INVCTRL                             FTM_INVCTRL_REG(FTM1)
+#define FTM1_SWOCTRL                             FTM_SWOCTRL_REG(FTM1)
+#define FTM1_PWMLOAD                             FTM_PWMLOAD_REG(FTM1)
+/* FTM2 */
+#define FTM2_SC                                  FTM_SC_REG(FTM2)
+#define FTM2_CNT                                 FTM_CNT_REG(FTM2)
+#define FTM2_MOD                                 FTM_MOD_REG(FTM2)
+#define FTM2_C0SC                                FTM_CnSC_REG(FTM2,0)
+#define FTM2_C0V                                 FTM_CnV_REG(FTM2,0)
+#define FTM2_C1SC                                FTM_CnSC_REG(FTM2,1)
+#define FTM2_C1V                                 FTM_CnV_REG(FTM2,1)
+#define FTM2_CNTIN                               FTM_CNTIN_REG(FTM2)
+#define FTM2_STATUS                              FTM_STATUS_REG(FTM2)
+#define FTM2_MODE                                FTM_MODE_REG(FTM2)
+#define FTM2_SYNC                                FTM_SYNC_REG(FTM2)
+#define FTM2_OUTINIT                             FTM_OUTINIT_REG(FTM2)
+#define FTM2_OUTMASK                             FTM_OUTMASK_REG(FTM2)
+#define FTM2_COMBINE                             FTM_COMBINE_REG(FTM2)
+#define FTM2_DEADTIME                            FTM_DEADTIME_REG(FTM2)
+#define FTM2_EXTTRIG                             FTM_EXTTRIG_REG(FTM2)
+#define FTM2_POL                                 FTM_POL_REG(FTM2)
+#define FTM2_FMS                                 FTM_FMS_REG(FTM2)
+#define FTM2_FILTER                              FTM_FILTER_REG(FTM2)
+#define FTM2_FLTCTRL                             FTM_FLTCTRL_REG(FTM2)
+#define FTM2_QDCTRL                              FTM_QDCTRL_REG(FTM2)
+#define FTM2_CONF                                FTM_CONF_REG(FTM2)
+#define FTM2_FLTPOL                              FTM_FLTPOL_REG(FTM2)
+#define FTM2_SYNCONF                             FTM_SYNCONF_REG(FTM2)
+#define FTM2_INVCTRL                             FTM_INVCTRL_REG(FTM2)
+#define FTM2_SWOCTRL                             FTM_SWOCTRL_REG(FTM2)
+#define FTM2_PWMLOAD                             FTM_PWMLOAD_REG(FTM2)
+/* FTM3 */
+#define FTM3_SC                                  FTM_SC_REG(FTM3)
+#define FTM3_CNT                                 FTM_CNT_REG(FTM3)
+#define FTM3_MOD                                 FTM_MOD_REG(FTM3)
+#define FTM3_C0SC                                FTM_CnSC_REG(FTM3,0)
+#define FTM3_C0V                                 FTM_CnV_REG(FTM3,0)
+#define FTM3_C1SC                                FTM_CnSC_REG(FTM3,1)
+#define FTM3_C1V                                 FTM_CnV_REG(FTM3,1)
+#define FTM3_C2SC                                FTM_CnSC_REG(FTM3,2)
+#define FTM3_C2V                                 FTM_CnV_REG(FTM3,2)
+#define FTM3_C3SC                                FTM_CnSC_REG(FTM3,3)
+#define FTM3_C3V                                 FTM_CnV_REG(FTM3,3)
+#define FTM3_C4SC                                FTM_CnSC_REG(FTM3,4)
+#define FTM3_C4V                                 FTM_CnV_REG(FTM3,4)
+#define FTM3_C5SC                                FTM_CnSC_REG(FTM3,5)
+#define FTM3_C5V                                 FTM_CnV_REG(FTM3,5)
+#define FTM3_C6SC                                FTM_CnSC_REG(FTM3,6)
+#define FTM3_C6V                                 FTM_CnV_REG(FTM3,6)
+#define FTM3_C7SC                                FTM_CnSC_REG(FTM3,7)
+#define FTM3_C7V                                 FTM_CnV_REG(FTM3,7)
+#define FTM3_CNTIN                               FTM_CNTIN_REG(FTM3)
+#define FTM3_STATUS                              FTM_STATUS_REG(FTM3)
+#define FTM3_MODE                                FTM_MODE_REG(FTM3)
+#define FTM3_SYNC                                FTM_SYNC_REG(FTM3)
+#define FTM3_OUTINIT                             FTM_OUTINIT_REG(FTM3)
+#define FTM3_OUTMASK                             FTM_OUTMASK_REG(FTM3)
+#define FTM3_COMBINE                             FTM_COMBINE_REG(FTM3)
+#define FTM3_DEADTIME                            FTM_DEADTIME_REG(FTM3)
+#define FTM3_EXTTRIG                             FTM_EXTTRIG_REG(FTM3)
+#define FTM3_POL                                 FTM_POL_REG(FTM3)
+#define FTM3_FMS                                 FTM_FMS_REG(FTM3)
+#define FTM3_FILTER                              FTM_FILTER_REG(FTM3)
+#define FTM3_FLTCTRL                             FTM_FLTCTRL_REG(FTM3)
+#define FTM3_QDCTRL                              FTM_QDCTRL_REG(FTM3)
+#define FTM3_CONF                                FTM_CONF_REG(FTM3)
+#define FTM3_FLTPOL                              FTM_FLTPOL_REG(FTM3)
+#define FTM3_SYNCONF                             FTM_SYNCONF_REG(FTM3)
+#define FTM3_INVCTRL                             FTM_INVCTRL_REG(FTM3)
+#define FTM3_SWOCTRL                             FTM_SWOCTRL_REG(FTM3)
+#define FTM3_PWMLOAD                             FTM_PWMLOAD_REG(FTM3)
+
+/* FTM - Register array accessors */
+#define FTM0_CnSC(index)                         FTM_CnSC_REG(FTM0,index)
+#define FTM1_CnSC(index)                         FTM_CnSC_REG(FTM1,index)
+#define FTM2_CnSC(index)                         FTM_CnSC_REG(FTM2,index)
+#define FTM3_CnSC(index)                         FTM_CnSC_REG(FTM3,index)
+#define FTM0_CnV(index)                          FTM_CnV_REG(FTM0,index)
+#define FTM1_CnV(index)                          FTM_CnV_REG(FTM1,index)
+#define FTM2_CnV(index)                          FTM_CnV_REG(FTM2,index)
+#define FTM3_CnV(index)                          FTM_CnV_REG(FTM3,index)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base)                      ((base)->PDOR)
+#define GPIO_PSOR_REG(base)                      ((base)->PSOR)
+#define GPIO_PCOR_REG(base)                      ((base)->PCOR)
+#define GPIO_PTOR_REG(base)                      ((base)->PTOR)
+#define GPIO_PDIR_REG(base)                      ((base)->PDIR)
+#define GPIO_PDDR_REG(base)                      ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT                      0
+#define GPIO_PDOR_PDO_WIDTH                      32
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT                     0
+#define GPIO_PSOR_PTSO_WIDTH                     32
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT                     0
+#define GPIO_PCOR_PTCO_WIDTH                     32
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT                     0
+#define GPIO_PTOR_PTTO_WIDTH                     32
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT                      0
+#define GPIO_PDIR_PDI_WIDTH                      32
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT                      0
+#define GPIO_PDDR_PDD_WIDTH                      32
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE                                 (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA                                      ((GPIO_Type *)PTA_BASE)
+#define PTA_BASE_PTR                             (PTA)
+/** Peripheral PTB base address */
+#define PTB_BASE                                 (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB                                      ((GPIO_Type *)PTB_BASE)
+#define PTB_BASE_PTR                             (PTB)
+/** Peripheral PTC base address */
+#define PTC_BASE                                 (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC                                      ((GPIO_Type *)PTC_BASE)
+#define PTC_BASE_PTR                             (PTC)
+/** Peripheral PTD base address */
+#define PTD_BASE                                 (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD                                      ((GPIO_Type *)PTD_BASE)
+#define PTD_BASE_PTR                             (PTD)
+/** Peripheral PTE base address */
+#define PTE_BASE                                 (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE                                      ((GPIO_Type *)PTE_BASE)
+#define PTE_BASE_PTR                             (PTE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { PTA, PTB, PTC, PTD, PTE }
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* PTA */
+#define GPIOA_PDOR                               GPIO_PDOR_REG(PTA)
+#define GPIOA_PSOR                               GPIO_PSOR_REG(PTA)
+#define GPIOA_PCOR                               GPIO_PCOR_REG(PTA)
+#define GPIOA_PTOR                               GPIO_PTOR_REG(PTA)
+#define GPIOA_PDIR                               GPIO_PDIR_REG(PTA)
+#define GPIOA_PDDR                               GPIO_PDDR_REG(PTA)
+/* PTB */
+#define GPIOB_PDOR                               GPIO_PDOR_REG(PTB)
+#define GPIOB_PSOR                               GPIO_PSOR_REG(PTB)
+#define GPIOB_PCOR                               GPIO_PCOR_REG(PTB)
+#define GPIOB_PTOR                               GPIO_PTOR_REG(PTB)
+#define GPIOB_PDIR                               GPIO_PDIR_REG(PTB)
+#define GPIOB_PDDR                               GPIO_PDDR_REG(PTB)
+/* PTC */
+#define GPIOC_PDOR                               GPIO_PDOR_REG(PTC)
+#define GPIOC_PSOR                               GPIO_PSOR_REG(PTC)
+#define GPIOC_PCOR                               GPIO_PCOR_REG(PTC)
+#define GPIOC_PTOR                               GPIO_PTOR_REG(PTC)
+#define GPIOC_PDIR                               GPIO_PDIR_REG(PTC)
+#define GPIOC_PDDR                               GPIO_PDDR_REG(PTC)
+/* PTD */
+#define GPIOD_PDOR                               GPIO_PDOR_REG(PTD)
+#define GPIOD_PSOR                               GPIO_PSOR_REG(PTD)
+#define GPIOD_PCOR                               GPIO_PCOR_REG(PTD)
+#define GPIOD_PTOR                               GPIO_PTOR_REG(PTD)
+#define GPIOD_PDIR                               GPIO_PDIR_REG(PTD)
+#define GPIOD_PDDR                               GPIO_PDDR_REG(PTD)
+/* PTE */
+#define GPIOE_PDOR                               GPIO_PDOR_REG(PTE)
+#define GPIOE_PSOR                               GPIO_PSOR_REG(PTE)
+#define GPIOE_PCOR                               GPIO_PCOR_REG(PTE)
+#define GPIOE_PTOR                               GPIO_PTOR_REG(PTE)
+#define GPIOE_PDIR                               GPIO_PDIR_REG(PTE)
+#define GPIOE_PDDR                               GPIO_PDDR_REG(PTE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base)                         ((base)->A1)
+#define I2C_F_REG(base)                          ((base)->F)
+#define I2C_C1_REG(base)                         ((base)->C1)
+#define I2C_S_REG(base)                          ((base)->S)
+#define I2C_D_REG(base)                          ((base)->D)
+#define I2C_C2_REG(base)                         ((base)->C2)
+#define I2C_FLT_REG(base)                        ((base)->FLT)
+#define I2C_RA_REG(base)                         ((base)->RA)
+#define I2C_SMB_REG(base)                        ((base)->SMB)
+#define I2C_A2_REG(base)                         ((base)->A2)
+#define I2C_SLTH_REG(base)                       ((base)->SLTH)
+#define I2C_SLTL_REG(base)                       ((base)->SLTL)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK                           0xFEu
+#define I2C_A1_AD_SHIFT                          1
+#define I2C_A1_AD_WIDTH                          7
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK                           0x3Fu
+#define I2C_F_ICR_SHIFT                          0
+#define I2C_F_ICR_WIDTH                          6
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          0xC0u
+#define I2C_F_MULT_SHIFT                         6
+#define I2C_F_MULT_WIDTH                         2
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK                        0x1u
+#define I2C_C1_DMAEN_SHIFT                       0
+#define I2C_C1_DMAEN_WIDTH                       1
+#define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_DMAEN_SHIFT))&I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK                         0x2u
+#define I2C_C1_WUEN_SHIFT                        1
+#define I2C_C1_WUEN_WIDTH                        1
+#define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_WUEN_SHIFT))&I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK                         0x4u
+#define I2C_C1_RSTA_SHIFT                        2
+#define I2C_C1_RSTA_WIDTH                        1
+#define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_RSTA_SHIFT))&I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK                         0x8u
+#define I2C_C1_TXAK_SHIFT                        3
+#define I2C_C1_TXAK_WIDTH                        1
+#define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_TXAK_SHIFT))&I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK                           0x10u
+#define I2C_C1_TX_SHIFT                          4
+#define I2C_C1_TX_WIDTH                          1
+#define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C1_TX_SHIFT))&I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK                          0x20u
+#define I2C_C1_MST_SHIFT                         5
+#define I2C_C1_MST_WIDTH                         1
+#define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_C1_MST_SHIFT))&I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK                        0x40u
+#define I2C_C1_IICIE_SHIFT                       6
+#define I2C_C1_IICIE_WIDTH                       1
+#define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICIE_SHIFT))&I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK                        0x80u
+#define I2C_C1_IICEN_SHIFT                       7
+#define I2C_C1_IICEN_WIDTH                       1
+#define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICEN_SHIFT))&I2C_C1_IICEN_MASK)
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK                          0x1u
+#define I2C_S_RXAK_SHIFT                         0
+#define I2C_S_RXAK_WIDTH                         1
+#define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_RXAK_SHIFT))&I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK                         0x2u
+#define I2C_S_IICIF_SHIFT                        1
+#define I2C_S_IICIF_WIDTH                        1
+#define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_S_IICIF_SHIFT))&I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK                           0x4u
+#define I2C_S_SRW_SHIFT                          2
+#define I2C_S_SRW_WIDTH                          1
+#define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_SRW_SHIFT))&I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK                           0x8u
+#define I2C_S_RAM_SHIFT                          3
+#define I2C_S_RAM_WIDTH                          1
+#define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_RAM_SHIFT))&I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK                          0x10u
+#define I2C_S_ARBL_SHIFT                         4
+#define I2C_S_ARBL_WIDTH                         1
+#define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_ARBL_SHIFT))&I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK                          0x20u
+#define I2C_S_BUSY_SHIFT                         5
+#define I2C_S_BUSY_WIDTH                         1
+#define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_BUSY_SHIFT))&I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK                          0x40u
+#define I2C_S_IAAS_SHIFT                         6
+#define I2C_S_IAAS_WIDTH                         1
+#define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_IAAS_SHIFT))&I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK                           0x80u
+#define I2C_S_TCF_SHIFT                          7
+#define I2C_S_TCF_WIDTH                          1
+#define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_TCF_SHIFT))&I2C_S_TCF_MASK)
+/* D Bit Fields */
+#define I2C_D_DATA_MASK                          0xFFu
+#define I2C_D_DATA_SHIFT                         0
+#define I2C_D_DATA_WIDTH                         8
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK                           0x7u
+#define I2C_C2_AD_SHIFT                          0
+#define I2C_C2_AD_WIDTH                          3
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         0x8u
+#define I2C_C2_RMEN_SHIFT                        3
+#define I2C_C2_RMEN_WIDTH                        1
+#define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_RMEN_SHIFT))&I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK                         0x10u
+#define I2C_C2_SBRC_SHIFT                        4
+#define I2C_C2_SBRC_WIDTH                        1
+#define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_SBRC_SHIFT))&I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK                         0x20u
+#define I2C_C2_HDRS_SHIFT                        5
+#define I2C_C2_HDRS_WIDTH                        1
+#define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_HDRS_SHIFT))&I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK                        0x40u
+#define I2C_C2_ADEXT_SHIFT                       6
+#define I2C_C2_ADEXT_WIDTH                       1
+#define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_ADEXT_SHIFT))&I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK                        0x80u
+#define I2C_C2_GCAEN_SHIFT                       7
+#define I2C_C2_GCAEN_WIDTH                       1
+#define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_GCAEN_SHIFT))&I2C_C2_GCAEN_MASK)
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK                         0xFu
+#define I2C_FLT_FLT_SHIFT                        0
+#define I2C_FLT_FLT_WIDTH                        4
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK                      0x10u
+#define I2C_FLT_STARTF_SHIFT                     4
+#define I2C_FLT_STARTF_WIDTH                     1
+#define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STARTF_SHIFT))&I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK                        0x20u
+#define I2C_FLT_SSIE_SHIFT                       5
+#define I2C_FLT_SSIE_WIDTH                       1
+#define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SSIE_SHIFT))&I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK                       0x40u
+#define I2C_FLT_STOPF_SHIFT                      6
+#define I2C_FLT_STOPF_WIDTH                      1
+#define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STOPF_SHIFT))&I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK                        0x80u
+#define I2C_FLT_SHEN_SHIFT                       7
+#define I2C_FLT_SHEN_WIDTH                       1
+#define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SHEN_SHIFT))&I2C_FLT_SHEN_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK                          0xFEu
+#define I2C_RA_RAD_SHIFT                         1
+#define I2C_RA_RAD_WIDTH                         7
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK                     0x1u
+#define I2C_SMB_SHTF2IE_SHIFT                    0
+#define I2C_SMB_SHTF2IE_WIDTH                    1
+#define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2IE_SHIFT))&I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK                       0x2u
+#define I2C_SMB_SHTF2_SHIFT                      1
+#define I2C_SMB_SHTF2_WIDTH                      1
+#define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2_SHIFT))&I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK                       0x4u
+#define I2C_SMB_SHTF1_SHIFT                      2
+#define I2C_SMB_SHTF1_WIDTH                      1
+#define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF1_SHIFT))&I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK                        0x8u
+#define I2C_SMB_SLTF_SHIFT                       3
+#define I2C_SMB_SLTF_WIDTH                       1
+#define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SLTF_SHIFT))&I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK                      0x10u
+#define I2C_SMB_TCKSEL_SHIFT                     4
+#define I2C_SMB_TCKSEL_WIDTH                     1
+#define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_SMB_TCKSEL_SHIFT))&I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK                     0x20u
+#define I2C_SMB_SIICAEN_SHIFT                    5
+#define I2C_SMB_SIICAEN_WIDTH                    1
+#define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SIICAEN_SHIFT))&I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK                     0x40u
+#define I2C_SMB_ALERTEN_SHIFT                    6
+#define I2C_SMB_ALERTEN_WIDTH                    1
+#define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_ALERTEN_SHIFT))&I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK                        0x80u
+#define I2C_SMB_FACK_SHIFT                       7
+#define I2C_SMB_FACK_WIDTH                       1
+#define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_FACK_SHIFT))&I2C_SMB_FACK_MASK)
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK                          0xFEu
+#define I2C_A2_SAD_SHIFT                         1
+#define I2C_A2_SAD_WIDTH                         7
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK                       0xFFu
+#define I2C_SLTH_SSLT_SHIFT                      0
+#define I2C_SLTH_SSLT_WIDTH                      8
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK                       0xFFu
+#define I2C_SLTL_SSLT_SHIFT                      0
+#define I2C_SLTL_SSLT_WIDTH                      8
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR                            (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR                            (I2C1)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x400E6000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+#define I2C2_BASE_PTR                            (I2C2)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1                                  I2C_A1_REG(I2C0)
+#define I2C0_F                                   I2C_F_REG(I2C0)
+#define I2C0_C1                                  I2C_C1_REG(I2C0)
+#define I2C0_S                                   I2C_S_REG(I2C0)
+#define I2C0_D                                   I2C_D_REG(I2C0)
+#define I2C0_C2                                  I2C_C2_REG(I2C0)
+#define I2C0_FLT                                 I2C_FLT_REG(I2C0)
+#define I2C0_RA                                  I2C_RA_REG(I2C0)
+#define I2C0_SMB                                 I2C_SMB_REG(I2C0)
+#define I2C0_A2                                  I2C_A2_REG(I2C0)
+#define I2C0_SLTH                                I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL                                I2C_SLTL_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1                                  I2C_A1_REG(I2C1)
+#define I2C1_F                                   I2C_F_REG(I2C1)
+#define I2C1_C1                                  I2C_C1_REG(I2C1)
+#define I2C1_S                                   I2C_S_REG(I2C1)
+#define I2C1_D                                   I2C_D_REG(I2C1)
+#define I2C1_C2                                  I2C_C2_REG(I2C1)
+#define I2C1_FLT                                 I2C_FLT_REG(I2C1)
+#define I2C1_RA                                  I2C_RA_REG(I2C1)
+#define I2C1_SMB                                 I2C_SMB_REG(I2C1)
+#define I2C1_A2                                  I2C_A2_REG(I2C1)
+#define I2C1_SLTH                                I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL                                I2C_SLTL_REG(I2C1)
+/* I2C2 */
+#define I2C2_A1                                  I2C_A1_REG(I2C2)
+#define I2C2_F                                   I2C_F_REG(I2C2)
+#define I2C2_C1                                  I2C_C1_REG(I2C2)
+#define I2C2_S                                   I2C_S_REG(I2C2)
+#define I2C2_D                                   I2C_D_REG(I2C2)
+#define I2C2_C2                                  I2C_C2_REG(I2C2)
+#define I2C2_FLT                                 I2C_FLT_REG(I2C2)
+#define I2C2_RA                                  I2C_RA_REG(I2C2)
+#define I2C2_SMB                                 I2C_SMB_REG(I2C2)
+#define I2C2_A2                                  I2C_A2_REG(I2C2)
+#define I2C2_SLTH                                I2C_SLTH_REG(I2C2)
+#define I2C2_SLTL                                I2C_SLTL_REG(I2C2)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
+  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t TDR[2];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __I  uint32_t TFR[2];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_3[28];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
+  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t RDR[2];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[24];
+  __I  uint32_t RFR[2];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_6[24];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
+  __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base)                       ((base)->TCSR)
+#define I2S_TCR1_REG(base)                       ((base)->TCR1)
+#define I2S_TCR2_REG(base)                       ((base)->TCR2)
+#define I2S_TCR3_REG(base)                       ((base)->TCR3)
+#define I2S_TCR4_REG(base)                       ((base)->TCR4)
+#define I2S_TCR5_REG(base)                       ((base)->TCR5)
+#define I2S_TDR_REG(base,index)                  ((base)->TDR[index])
+#define I2S_TDR_COUNT                            2
+#define I2S_TFR_REG(base,index)                  ((base)->TFR[index])
+#define I2S_TFR_COUNT                            2
+#define I2S_TMR_REG(base)                        ((base)->TMR)
+#define I2S_RCSR_REG(base)                       ((base)->RCSR)
+#define I2S_RCR1_REG(base)                       ((base)->RCR1)
+#define I2S_RCR2_REG(base)                       ((base)->RCR2)
+#define I2S_RCR3_REG(base)                       ((base)->RCR3)
+#define I2S_RCR4_REG(base)                       ((base)->RCR4)
+#define I2S_RCR5_REG(base)                       ((base)->RCR5)
+#define I2S_RDR_REG(base,index)                  ((base)->RDR[index])
+#define I2S_RDR_COUNT                            2
+#define I2S_RFR_REG(base,index)                  ((base)->RFR[index])
+#define I2S_RFR_COUNT                            2
+#define I2S_RMR_REG(base)                        ((base)->RMR)
+#define I2S_MCR_REG(base)                        ((base)->MCR)
+#define I2S_MDR_REG(base)                        ((base)->MDR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK                       0x1u
+#define I2S_TCSR_FRDE_SHIFT                      0
+#define I2S_TCSR_FRDE_WIDTH                      1
+#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRDE_SHIFT))&I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK                       0x2u
+#define I2S_TCSR_FWDE_SHIFT                      1
+#define I2S_TCSR_FWDE_WIDTH                      1
+#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK                       0x100u
+#define I2S_TCSR_FRIE_SHIFT                      8
+#define I2S_TCSR_FRIE_WIDTH                      1
+#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRIE_SHIFT))&I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK                       0x200u
+#define I2S_TCSR_FWIE_SHIFT                      9
+#define I2S_TCSR_FWIE_WIDTH                      1
+#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK                       0x400u
+#define I2S_TCSR_FEIE_SHIFT                      10
+#define I2S_TCSR_FEIE_WIDTH                      1
+#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK                       0x800u
+#define I2S_TCSR_SEIE_SHIFT                      11
+#define I2S_TCSR_SEIE_WIDTH                      1
+#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK                       0x1000u
+#define I2S_TCSR_WSIE_SHIFT                      12
+#define I2S_TCSR_WSIE_WIDTH                      1
+#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK                        0x10000u
+#define I2S_TCSR_FRF_SHIFT                       16
+#define I2S_TCSR_FRF_WIDTH                       1
+#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRF_SHIFT))&I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK                        0x20000u
+#define I2S_TCSR_FWF_SHIFT                       17
+#define I2S_TCSR_FWF_WIDTH                       1
+#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK                        0x40000u
+#define I2S_TCSR_FEF_SHIFT                       18
+#define I2S_TCSR_FEF_WIDTH                       1
+#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK                        0x80000u
+#define I2S_TCSR_SEF_SHIFT                       19
+#define I2S_TCSR_SEF_WIDTH                       1
+#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK                        0x100000u
+#define I2S_TCSR_WSF_SHIFT                       20
+#define I2S_TCSR_WSF_WIDTH                       1
+#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK                         0x1000000u
+#define I2S_TCSR_SR_SHIFT                        24
+#define I2S_TCSR_SR_WIDTH                        1
+#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK                         0x2000000u
+#define I2S_TCSR_FR_SHIFT                        25
+#define I2S_TCSR_FR_WIDTH                        1
+#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK                        0x10000000u
+#define I2S_TCSR_BCE_SHIFT                       28
+#define I2S_TCSR_BCE_WIDTH                       1
+#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK                       0x20000000u
+#define I2S_TCSR_DBGE_SHIFT                      29
+#define I2S_TCSR_DBGE_WIDTH                      1
+#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK                      0x40000000u
+#define I2S_TCSR_STOPE_SHIFT                     30
+#define I2S_TCSR_STOPE_WIDTH                     1
+#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK                         0x80000000u
+#define I2S_TCSR_TE_SHIFT                        31
+#define I2S_TCSR_TE_WIDTH                        1
+#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK                        0x7u
+#define I2S_TCR1_TFW_SHIFT                       0
+#define I2S_TCR1_TFW_WIDTH                       3
+#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK                        0xFFu
+#define I2S_TCR2_DIV_SHIFT                       0
+#define I2S_TCR2_DIV_WIDTH                       8
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        0x1000000u
+#define I2S_TCR2_BCD_SHIFT                       24
+#define I2S_TCR2_BCD_WIDTH                       1
+#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK                        0x2000000u
+#define I2S_TCR2_BCP_SHIFT                       25
+#define I2S_TCR2_BCP_WIDTH                       1
+#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK                       0xC000000u
+#define I2S_TCR2_MSEL_SHIFT                      26
+#define I2S_TCR2_MSEL_WIDTH                      2
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK                        0x10000000u
+#define I2S_TCR2_BCI_SHIFT                       28
+#define I2S_TCR2_BCI_WIDTH                       1
+#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK                        0x20000000u
+#define I2S_TCR2_BCS_SHIFT                       29
+#define I2S_TCR2_BCS_WIDTH                       1
+#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK                       0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT                      30
+#define I2S_TCR2_SYNC_WIDTH                      2
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK                       0x1Fu
+#define I2S_TCR3_WDFL_SHIFT                      0
+#define I2S_TCR3_WDFL_WIDTH                      5
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        0x30000u
+#define I2S_TCR3_TCE_SHIFT                       16
+#define I2S_TCR3_TCE_WIDTH                       2
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK                        0x1u
+#define I2S_TCR4_FSD_SHIFT                       0
+#define I2S_TCR4_FSD_WIDTH                       1
+#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK                        0x2u
+#define I2S_TCR4_FSP_SHIFT                       1
+#define I2S_TCR4_FSP_WIDTH                       1
+#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSE_MASK                        0x8u
+#define I2S_TCR4_FSE_SHIFT                       3
+#define I2S_TCR4_FSE_WIDTH                       1
+#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK                         0x10u
+#define I2S_TCR4_MF_SHIFT                        4
+#define I2S_TCR4_MF_WIDTH                        1
+#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK                       0x1F00u
+#define I2S_TCR4_SYWD_SHIFT                      8
+#define I2S_TCR4_SYWD_WIDTH                      5
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT                      16
+#define I2S_TCR4_FRSZ_WIDTH                      5
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK                        0x1F00u
+#define I2S_TCR5_FBT_SHIFT                       8
+#define I2S_TCR5_FBT_WIDTH                       5
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        0x1F0000u
+#define I2S_TCR5_W0W_SHIFT                       16
+#define I2S_TCR5_W0W_WIDTH                       5
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        0x1F000000u
+#define I2S_TCR5_WNW_SHIFT                       24
+#define I2S_TCR5_WNW_WIDTH                       5
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT                        0
+#define I2S_TDR_TDR_WIDTH                        32
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK                         0xFu
+#define I2S_TFR_RFP_SHIFT                        0
+#define I2S_TFR_RFP_WIDTH                        4
+#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK                         0xF0000u
+#define I2S_TFR_WFP_SHIFT                        16
+#define I2S_TFR_WFP_WIDTH                        4
+#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK                         0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT                        0
+#define I2S_TMR_TWM_WIDTH                        32
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK                       0x1u
+#define I2S_RCSR_FRDE_SHIFT                      0
+#define I2S_RCSR_FRDE_WIDTH                      1
+#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRDE_SHIFT))&I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK                       0x2u
+#define I2S_RCSR_FWDE_SHIFT                      1
+#define I2S_RCSR_FWDE_WIDTH                      1
+#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK                       0x100u
+#define I2S_RCSR_FRIE_SHIFT                      8
+#define I2S_RCSR_FRIE_WIDTH                      1
+#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRIE_SHIFT))&I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK                       0x200u
+#define I2S_RCSR_FWIE_SHIFT                      9
+#define I2S_RCSR_FWIE_WIDTH                      1
+#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK                       0x400u
+#define I2S_RCSR_FEIE_SHIFT                      10
+#define I2S_RCSR_FEIE_WIDTH                      1
+#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK                       0x800u
+#define I2S_RCSR_SEIE_SHIFT                      11
+#define I2S_RCSR_SEIE_WIDTH                      1
+#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK                       0x1000u
+#define I2S_RCSR_WSIE_SHIFT                      12
+#define I2S_RCSR_WSIE_WIDTH                      1
+#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK                        0x10000u
+#define I2S_RCSR_FRF_SHIFT                       16
+#define I2S_RCSR_FRF_WIDTH                       1
+#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRF_SHIFT))&I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK                        0x20000u
+#define I2S_RCSR_FWF_SHIFT                       17
+#define I2S_RCSR_FWF_WIDTH                       1
+#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK                        0x40000u
+#define I2S_RCSR_FEF_SHIFT                       18
+#define I2S_RCSR_FEF_WIDTH                       1
+#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK                        0x80000u
+#define I2S_RCSR_SEF_SHIFT                       19
+#define I2S_RCSR_SEF_WIDTH                       1
+#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK                        0x100000u
+#define I2S_RCSR_WSF_SHIFT                       20
+#define I2S_RCSR_WSF_WIDTH                       1
+#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK                         0x1000000u
+#define I2S_RCSR_SR_SHIFT                        24
+#define I2S_RCSR_SR_WIDTH                        1
+#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK                         0x2000000u
+#define I2S_RCSR_FR_SHIFT                        25
+#define I2S_RCSR_FR_WIDTH                        1
+#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK                        0x10000000u
+#define I2S_RCSR_BCE_SHIFT                       28
+#define I2S_RCSR_BCE_WIDTH                       1
+#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK                       0x20000000u
+#define I2S_RCSR_DBGE_SHIFT                      29
+#define I2S_RCSR_DBGE_WIDTH                      1
+#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK                      0x40000000u
+#define I2S_RCSR_STOPE_SHIFT                     30
+#define I2S_RCSR_STOPE_WIDTH                     1
+#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK                         0x80000000u
+#define I2S_RCSR_RE_SHIFT                        31
+#define I2S_RCSR_RE_WIDTH                        1
+#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK                        0x7u
+#define I2S_RCR1_RFW_SHIFT                       0
+#define I2S_RCR1_RFW_WIDTH                       3
+#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK                        0xFFu
+#define I2S_RCR2_DIV_SHIFT                       0
+#define I2S_RCR2_DIV_WIDTH                       8
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        0x1000000u
+#define I2S_RCR2_BCD_SHIFT                       24
+#define I2S_RCR2_BCD_WIDTH                       1
+#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK                        0x2000000u
+#define I2S_RCR2_BCP_SHIFT                       25
+#define I2S_RCR2_BCP_WIDTH                       1
+#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK                       0xC000000u
+#define I2S_RCR2_MSEL_SHIFT                      26
+#define I2S_RCR2_MSEL_WIDTH                      2
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK                        0x10000000u
+#define I2S_RCR2_BCI_SHIFT                       28
+#define I2S_RCR2_BCI_WIDTH                       1
+#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK                        0x20000000u
+#define I2S_RCR2_BCS_SHIFT                       29
+#define I2S_RCR2_BCS_WIDTH                       1
+#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK                       0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT                      30
+#define I2S_RCR2_SYNC_WIDTH                      2
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK                       0x1Fu
+#define I2S_RCR3_WDFL_SHIFT                      0
+#define I2S_RCR3_WDFL_WIDTH                      5
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        0x30000u
+#define I2S_RCR3_RCE_SHIFT                       16
+#define I2S_RCR3_RCE_WIDTH                       2
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK                        0x1u
+#define I2S_RCR4_FSD_SHIFT                       0
+#define I2S_RCR4_FSD_WIDTH                       1
+#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK                        0x2u
+#define I2S_RCR4_FSP_SHIFT                       1
+#define I2S_RCR4_FSP_WIDTH                       1
+#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSE_MASK                        0x8u
+#define I2S_RCR4_FSE_SHIFT                       3
+#define I2S_RCR4_FSE_WIDTH                       1
+#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK                         0x10u
+#define I2S_RCR4_MF_SHIFT                        4
+#define I2S_RCR4_MF_WIDTH                        1
+#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK                       0x1F00u
+#define I2S_RCR4_SYWD_SHIFT                      8
+#define I2S_RCR4_SYWD_WIDTH                      5
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT                      16
+#define I2S_RCR4_FRSZ_WIDTH                      5
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK                        0x1F00u
+#define I2S_RCR5_FBT_SHIFT                       8
+#define I2S_RCR5_FBT_WIDTH                       5
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        0x1F0000u
+#define I2S_RCR5_W0W_SHIFT                       16
+#define I2S_RCR5_W0W_WIDTH                       5
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        0x1F000000u
+#define I2S_RCR5_WNW_SHIFT                       24
+#define I2S_RCR5_WNW_WIDTH                       5
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT                        0
+#define I2S_RDR_RDR_WIDTH                        32
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK                         0xFu
+#define I2S_RFR_RFP_SHIFT                        0
+#define I2S_RFR_RFP_WIDTH                        4
+#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK                         0xF0000u
+#define I2S_RFR_WFP_SHIFT                        16
+#define I2S_RFR_WFP_WIDTH                        4
+#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK                         0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT                        0
+#define I2S_RMR_RWM_WIDTH                        32
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK                        0x3000000u
+#define I2S_MCR_MICS_SHIFT                       24
+#define I2S_MCR_MICS_WIDTH                       2
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK                         0x40000000u
+#define I2S_MCR_MOE_SHIFT                        30
+#define I2S_MCR_MOE_WIDTH                        1
+#define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MOE_SHIFT))&I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK                         0x80000000u
+#define I2S_MCR_DUF_SHIFT                        31
+#define I2S_MCR_DUF_WIDTH                        1
+#define I2S_MCR_DUF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_DUF_SHIFT))&I2S_MCR_DUF_MASK)
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK                      0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT                     0
+#define I2S_MDR_DIVIDE_WIDTH                     12
+#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK                       0xFF000u
+#define I2S_MDR_FRACT_SHIFT                      12
+#define I2S_MDR_FRACT_WIDTH                      8
+#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR                            (I2S0)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS                              { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS                              { I2S0_Tx_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR                                I2S_TCSR_REG(I2S0)
+#define I2S0_TCR1                                I2S_TCR1_REG(I2S0)
+#define I2S0_TCR2                                I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3                                I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4                                I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5                                I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0                                I2S_TDR_REG(I2S0,0)
+#define I2S0_TDR1                                I2S_TDR_REG(I2S0,1)
+#define I2S0_TFR0                                I2S_TFR_REG(I2S0,0)
+#define I2S0_TFR1                                I2S_TFR_REG(I2S0,1)
+#define I2S0_TMR                                 I2S_TMR_REG(I2S0)
+#define I2S0_RCSR                                I2S_RCSR_REG(I2S0)
+#define I2S0_RCR1                                I2S_RCR1_REG(I2S0)
+#define I2S0_RCR2                                I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3                                I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4                                I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5                                I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0                                I2S_RDR_REG(I2S0,0)
+#define I2S0_RDR1                                I2S_RDR_REG(I2S0,1)
+#define I2S0_RFR0                                I2S_RFR_REG(I2S0,0)
+#define I2S0_RFR1                                I2S_RFR_REG(I2S0,1)
+#define I2S0_RMR                                 I2S_RMR_REG(I2S0)
+#define I2S0_MCR                                 I2S_MCR_REG(I2S0)
+#define I2S0_MDR                                 I2S_MDR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index)                          I2S_TDR_REG(I2S0,index)
+#define I2S0_TFR(index)                          I2S_TFR_REG(I2S0,index)
+#define I2S0_RDR(index)                          I2S_RDR_REG(I2S0,index)
+#define I2S0_RFR(index)                          I2S_RFR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
+  __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
+  __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
+  __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
+  __IO uint8_t RST;                                /**< LLWU Reset Enable register, offset: 0xA */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base)                       ((base)->PE1)
+#define LLWU_PE2_REG(base)                       ((base)->PE2)
+#define LLWU_PE3_REG(base)                       ((base)->PE3)
+#define LLWU_PE4_REG(base)                       ((base)->PE4)
+#define LLWU_ME_REG(base)                        ((base)->ME)
+#define LLWU_F1_REG(base)                        ((base)->F1)
+#define LLWU_F2_REG(base)                        ((base)->F2)
+#define LLWU_F3_REG(base)                        ((base)->F3)
+#define LLWU_FILT1_REG(base)                     ((base)->FILT1)
+#define LLWU_FILT2_REG(base)                     ((base)->FILT2)
+#define LLWU_RST_REG(base)                       ((base)->RST)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK                      0x3u
+#define LLWU_PE1_WUPE0_SHIFT                     0
+#define LLWU_PE1_WUPE0_WIDTH                     2
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      0xCu
+#define LLWU_PE1_WUPE1_SHIFT                     2
+#define LLWU_PE1_WUPE1_WIDTH                     2
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      0x30u
+#define LLWU_PE1_WUPE2_SHIFT                     4
+#define LLWU_PE1_WUPE2_WIDTH                     2
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      0xC0u
+#define LLWU_PE1_WUPE3_SHIFT                     6
+#define LLWU_PE1_WUPE3_WIDTH                     2
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK                      0x3u
+#define LLWU_PE2_WUPE4_SHIFT                     0
+#define LLWU_PE2_WUPE4_WIDTH                     2
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      0xCu
+#define LLWU_PE2_WUPE5_SHIFT                     2
+#define LLWU_PE2_WUPE5_WIDTH                     2
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      0x30u
+#define LLWU_PE2_WUPE6_SHIFT                     4
+#define LLWU_PE2_WUPE6_WIDTH                     2
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      0xC0u
+#define LLWU_PE2_WUPE7_SHIFT                     6
+#define LLWU_PE2_WUPE7_WIDTH                     2
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK                      0x3u
+#define LLWU_PE3_WUPE8_SHIFT                     0
+#define LLWU_PE3_WUPE8_WIDTH                     2
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      0xCu
+#define LLWU_PE3_WUPE9_SHIFT                     2
+#define LLWU_PE3_WUPE9_WIDTH                     2
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     0x30u
+#define LLWU_PE3_WUPE10_SHIFT                    4
+#define LLWU_PE3_WUPE10_WIDTH                    2
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     0xC0u
+#define LLWU_PE3_WUPE11_SHIFT                    6
+#define LLWU_PE3_WUPE11_WIDTH                    2
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK                     0x3u
+#define LLWU_PE4_WUPE12_SHIFT                    0
+#define LLWU_PE4_WUPE12_WIDTH                    2
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     0xCu
+#define LLWU_PE4_WUPE13_SHIFT                    2
+#define LLWU_PE4_WUPE13_WIDTH                    2
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     0x30u
+#define LLWU_PE4_WUPE14_SHIFT                    4
+#define LLWU_PE4_WUPE14_WIDTH                    2
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     0xC0u
+#define LLWU_PE4_WUPE15_SHIFT                    6
+#define LLWU_PE4_WUPE15_WIDTH                    2
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK                       0x1u
+#define LLWU_ME_WUME0_SHIFT                      0
+#define LLWU_ME_WUME0_WIDTH                      1
+#define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK                       0x2u
+#define LLWU_ME_WUME1_SHIFT                      1
+#define LLWU_ME_WUME1_WIDTH                      1
+#define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK                       0x4u
+#define LLWU_ME_WUME2_SHIFT                      2
+#define LLWU_ME_WUME2_WIDTH                      1
+#define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK                       0x8u
+#define LLWU_ME_WUME3_SHIFT                      3
+#define LLWU_ME_WUME3_WIDTH                      1
+#define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK                       0x10u
+#define LLWU_ME_WUME4_SHIFT                      4
+#define LLWU_ME_WUME4_WIDTH                      1
+#define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK                       0x20u
+#define LLWU_ME_WUME5_SHIFT                      5
+#define LLWU_ME_WUME5_WIDTH                      1
+#define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK                       0x40u
+#define LLWU_ME_WUME6_SHIFT                      6
+#define LLWU_ME_WUME6_WIDTH                      1
+#define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK                       0x80u
+#define LLWU_ME_WUME7_SHIFT                      7
+#define LLWU_ME_WUME7_WIDTH                      1
+#define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK                        0x1u
+#define LLWU_F1_WUF0_SHIFT                       0
+#define LLWU_F1_WUF0_WIDTH                       1
+#define LLWU_F1_WUF0(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF0_SHIFT))&LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK                        0x2u
+#define LLWU_F1_WUF1_SHIFT                       1
+#define LLWU_F1_WUF1_WIDTH                       1
+#define LLWU_F1_WUF1(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF1_SHIFT))&LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK                        0x4u
+#define LLWU_F1_WUF2_SHIFT                       2
+#define LLWU_F1_WUF2_WIDTH                       1
+#define LLWU_F1_WUF2(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF2_SHIFT))&LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK                        0x8u
+#define LLWU_F1_WUF3_SHIFT                       3
+#define LLWU_F1_WUF3_WIDTH                       1
+#define LLWU_F1_WUF3(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF3_SHIFT))&LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK                        0x10u
+#define LLWU_F1_WUF4_SHIFT                       4
+#define LLWU_F1_WUF4_WIDTH                       1
+#define LLWU_F1_WUF4(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF4_SHIFT))&LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK                        0x20u
+#define LLWU_F1_WUF5_SHIFT                       5
+#define LLWU_F1_WUF5_WIDTH                       1
+#define LLWU_F1_WUF5(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF5_SHIFT))&LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK                        0x40u
+#define LLWU_F1_WUF6_SHIFT                       6
+#define LLWU_F1_WUF6_WIDTH                       1
+#define LLWU_F1_WUF6(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF6_SHIFT))&LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK                        0x80u
+#define LLWU_F1_WUF7_SHIFT                       7
+#define LLWU_F1_WUF7_WIDTH                       1
+#define LLWU_F1_WUF7(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF7_SHIFT))&LLWU_F1_WUF7_MASK)
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK                        0x1u
+#define LLWU_F2_WUF8_SHIFT                       0
+#define LLWU_F2_WUF8_WIDTH                       1
+#define LLWU_F2_WUF8(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF8_SHIFT))&LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK                        0x2u
+#define LLWU_F2_WUF9_SHIFT                       1
+#define LLWU_F2_WUF9_WIDTH                       1
+#define LLWU_F2_WUF9(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF9_SHIFT))&LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK                       0x4u
+#define LLWU_F2_WUF10_SHIFT                      2
+#define LLWU_F2_WUF10_WIDTH                      1
+#define LLWU_F2_WUF10(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF10_SHIFT))&LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK                       0x8u
+#define LLWU_F2_WUF11_SHIFT                      3
+#define LLWU_F2_WUF11_WIDTH                      1
+#define LLWU_F2_WUF11(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF11_SHIFT))&LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK                       0x10u
+#define LLWU_F2_WUF12_SHIFT                      4
+#define LLWU_F2_WUF12_WIDTH                      1
+#define LLWU_F2_WUF12(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF12_SHIFT))&LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK                       0x20u
+#define LLWU_F2_WUF13_SHIFT                      5
+#define LLWU_F2_WUF13_WIDTH                      1
+#define LLWU_F2_WUF13(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF13_SHIFT))&LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK                       0x40u
+#define LLWU_F2_WUF14_SHIFT                      6
+#define LLWU_F2_WUF14_WIDTH                      1
+#define LLWU_F2_WUF14(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF14_SHIFT))&LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK                       0x80u
+#define LLWU_F2_WUF15_SHIFT                      7
+#define LLWU_F2_WUF15_WIDTH                      1
+#define LLWU_F2_WUF15(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF15_SHIFT))&LLWU_F2_WUF15_MASK)
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK                       0x1u
+#define LLWU_F3_MWUF0_SHIFT                      0
+#define LLWU_F3_MWUF0_WIDTH                      1
+#define LLWU_F3_MWUF0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF0_SHIFT))&LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK                       0x2u
+#define LLWU_F3_MWUF1_SHIFT                      1
+#define LLWU_F3_MWUF1_WIDTH                      1
+#define LLWU_F3_MWUF1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF1_SHIFT))&LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK                       0x4u
+#define LLWU_F3_MWUF2_SHIFT                      2
+#define LLWU_F3_MWUF2_WIDTH                      1
+#define LLWU_F3_MWUF2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF2_SHIFT))&LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK                       0x8u
+#define LLWU_F3_MWUF3_SHIFT                      3
+#define LLWU_F3_MWUF3_WIDTH                      1
+#define LLWU_F3_MWUF3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF3_SHIFT))&LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK                       0x10u
+#define LLWU_F3_MWUF4_SHIFT                      4
+#define LLWU_F3_MWUF4_WIDTH                      1
+#define LLWU_F3_MWUF4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF4_SHIFT))&LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK                       0x20u
+#define LLWU_F3_MWUF5_SHIFT                      5
+#define LLWU_F3_MWUF5_WIDTH                      1
+#define LLWU_F3_MWUF5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF5_SHIFT))&LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK                       0x40u
+#define LLWU_F3_MWUF6_SHIFT                      6
+#define LLWU_F3_MWUF6_WIDTH                      1
+#define LLWU_F3_MWUF6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF6_SHIFT))&LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK                       0x80u
+#define LLWU_F3_MWUF7_SHIFT                      7
+#define LLWU_F3_MWUF7_WIDTH                      1
+#define LLWU_F3_MWUF7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF7_SHIFT))&LLWU_F3_MWUF7_MASK)
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK                  0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT                 0
+#define LLWU_FILT1_FILTSEL_WIDTH                 4
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    0x60u
+#define LLWU_FILT1_FILTE_SHIFT                   5
+#define LLWU_FILT1_FILTE_WIDTH                   2
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK                    0x80u
+#define LLWU_FILT1_FILTF_SHIFT                   7
+#define LLWU_FILT1_FILTF_WIDTH                   1
+#define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK                  0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT                 0
+#define LLWU_FILT2_FILTSEL_WIDTH                 4
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    0x60u
+#define LLWU_FILT2_FILTE_SHIFT                   5
+#define LLWU_FILT2_FILTE_WIDTH                   2
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK                    0x80u
+#define LLWU_FILT2_FILTF_SHIFT                   7
+#define LLWU_FILT2_FILTF_WIDTH                   1
+#define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK                    0x1u
+#define LLWU_RST_RSTFILT_SHIFT                   0
+#define LLWU_RST_RSTFILT_WIDTH                   1
+#define LLWU_RST_RSTFILT(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_RST_RSTFILT_SHIFT))&LLWU_RST_RSTFILT_MASK)
+#define LLWU_RST_LLRSTE_MASK                     0x2u
+#define LLWU_RST_LLRSTE_SHIFT                    1
+#define LLWU_RST_LLRSTE_WIDTH                    1
+#define LLWU_RST_LLRSTE(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_RST_LLRSTE_SHIFT))&LLWU_RST_LLRSTE_MASK)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR                            (LLWU)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1                                 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2                                 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3                                 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4                                 LLWU_PE4_REG(LLWU)
+#define LLWU_ME                                  LLWU_ME_REG(LLWU)
+#define LLWU_F1                                  LLWU_F1_REG(LLWU)
+#define LLWU_F2                                  LLWU_F2_REG(LLWU)
+#define LLWU_F3                                  LLWU_F3_REG(LLWU)
+#define LLWU_FILT1                               LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2                               LLWU_FILT2_REG(LLWU)
+#define LLWU_RST                                 LLWU_RST_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base)                      ((base)->CSR)
+#define LPTMR_PSR_REG(base)                      ((base)->PSR)
+#define LPTMR_CMR_REG(base)                      ((base)->CMR)
+#define LPTMR_CNR_REG(base)                      ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK                       0x1u
+#define LPTMR_CSR_TEN_SHIFT                      0
+#define LPTMR_CSR_TEN_WIDTH                      1
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK                       0x2u
+#define LPTMR_CSR_TMS_SHIFT                      1
+#define LPTMR_CSR_TMS_WIDTH                      1
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK                       0x4u
+#define LPTMR_CSR_TFC_SHIFT                      2
+#define LPTMR_CSR_TFC_WIDTH                      1
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK                       0x8u
+#define LPTMR_CSR_TPP_SHIFT                      3
+#define LPTMR_CSR_TPP_WIDTH                      1
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK                       0x30u
+#define LPTMR_CSR_TPS_SHIFT                      4
+#define LPTMR_CSR_TPS_WIDTH                      2
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       0x40u
+#define LPTMR_CSR_TIE_SHIFT                      6
+#define LPTMR_CSR_TIE_WIDTH                      1
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK                       0x80u
+#define LPTMR_CSR_TCF_SHIFT                      7
+#define LPTMR_CSR_TCF_WIDTH                      1
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK                       0x3u
+#define LPTMR_PSR_PCS_SHIFT                      0
+#define LPTMR_PSR_PCS_WIDTH                      2
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      0x4u
+#define LPTMR_PSR_PBYP_SHIFT                     2
+#define LPTMR_PSR_PBYP_WIDTH                     1
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK                  0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT                 3
+#define LPTMR_PSR_PRESCALE_WIDTH                 4
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT                  0
+#define LPTMR_CMR_COMPARE_WIDTH                  16
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT                  0
+#define LPTMR_CNR_COUNTER_WIDTH                  16
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR                          (LPTMR0)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR                               LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR                               LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR                               LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR                               LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
+  __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
+  __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
+  __IO uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+  __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+  __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
+  __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base)                         ((base)->C1)
+#define MCG_C2_REG(base)                         ((base)->C2)
+#define MCG_C3_REG(base)                         ((base)->C3)
+#define MCG_C4_REG(base)                         ((base)->C4)
+#define MCG_C5_REG(base)                         ((base)->C5)
+#define MCG_C6_REG(base)                         ((base)->C6)
+#define MCG_S_REG(base)                          ((base)->S)
+#define MCG_SC_REG(base)                         ((base)->SC)
+#define MCG_ATCVH_REG(base)                      ((base)->ATCVH)
+#define MCG_ATCVL_REG(base)                      ((base)->ATCVL)
+#define MCG_C7_REG(base)                         ((base)->C7)
+#define MCG_C8_REG(base)                         ((base)->C8)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK                     0x1u
+#define MCG_C1_IREFSTEN_SHIFT                    0
+#define MCG_C1_IREFSTEN_WIDTH                    1
+#define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK                      0x2u
+#define MCG_C1_IRCLKEN_SHIFT                     1
+#define MCG_C1_IRCLKEN_WIDTH                     1
+#define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK                        0x4u
+#define MCG_C1_IREFS_SHIFT                       2
+#define MCG_C1_IREFS_WIDTH                       1
+#define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFS_SHIFT))&MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK                        0x38u
+#define MCG_C1_FRDIV_SHIFT                       3
+#define MCG_C1_FRDIV_WIDTH                       3
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         0xC0u
+#define MCG_C1_CLKS_SHIFT                        6
+#define MCG_C1_CLKS_WIDTH                        2
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK                         0x1u
+#define MCG_C2_IRCS_SHIFT                        0
+#define MCG_C2_IRCS_WIDTH                        1
+#define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK                           0x2u
+#define MCG_C2_LP_SHIFT                          1
+#define MCG_C2_LP_WIDTH                          1
+#define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x))<<MCG_C2_LP_SHIFT))&MCG_C2_LP_MASK)
+#define MCG_C2_EREFS_MASK                        0x4u
+#define MCG_C2_EREFS_SHIFT                       2
+#define MCG_C2_EREFS_WIDTH                       1
+#define MCG_C2_EREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS_SHIFT))&MCG_C2_EREFS_MASK)
+#define MCG_C2_HGO_MASK                          0x8u
+#define MCG_C2_HGO_SHIFT                         3
+#define MCG_C2_HGO_WIDTH                         1
+#define MCG_C2_HGO(x)                            (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO_SHIFT))&MCG_C2_HGO_MASK)
+#define MCG_C2_RANGE_MASK                        0x30u
+#define MCG_C2_RANGE_SHIFT                       4
+#define MCG_C2_RANGE_WIDTH                       2
+#define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK                      0x40u
+#define MCG_C2_FCFTRIM_SHIFT                     6
+#define MCG_C2_FCFTRIM_WIDTH                     1
+#define MCG_C2_FCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C2_FCFTRIM_SHIFT))&MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK                       0x80u
+#define MCG_C2_LOCRE0_SHIFT                      7
+#define MCG_C2_LOCRE0_WIDTH                      1
+#define MCG_C2_LOCRE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_LOCRE0_SHIFT))&MCG_C2_LOCRE0_MASK)
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK                       0xFFu
+#define MCG_C3_SCTRIM_SHIFT                      0
+#define MCG_C3_SCTRIM_WIDTH                      8
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK                      0x1u
+#define MCG_C4_SCFTRIM_SHIFT                     0
+#define MCG_C4_SCFTRIM_WIDTH                     1
+#define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C4_SCFTRIM_SHIFT))&MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK                       0x1Eu
+#define MCG_C4_FCTRIM_SHIFT                      1
+#define MCG_C4_FCTRIM_WIDTH                      4
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     0x60u
+#define MCG_C4_DRST_DRS_SHIFT                    5
+#define MCG_C4_DRST_DRS_WIDTH                    2
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK                        0x80u
+#define MCG_C4_DMX32_SHIFT                       7
+#define MCG_C4_DMX32_WIDTH                       1
+#define MCG_C4_DMX32(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C4_DMX32_SHIFT))&MCG_C4_DMX32_MASK)
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK                       0x1Fu
+#define MCG_C5_PRDIV0_SHIFT                      0
+#define MCG_C5_PRDIV0_WIDTH                      5
+#define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK                     0x20u
+#define MCG_C5_PLLSTEN0_SHIFT                    5
+#define MCG_C5_PLLSTEN0_WIDTH                    1
+#define MCG_C5_PLLSTEN0(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLSTEN0_SHIFT))&MCG_C5_PLLSTEN0_MASK)
+#define MCG_C5_PLLCLKEN0_MASK                    0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT                   6
+#define MCG_C5_PLLCLKEN0_WIDTH                   1
+#define MCG_C5_PLLCLKEN0(x)                      (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLCLKEN0_SHIFT))&MCG_C5_PLLCLKEN0_MASK)
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK                        0x1Fu
+#define MCG_C6_VDIV0_SHIFT                       0
+#define MCG_C6_VDIV0_WIDTH                       5
+#define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK                         0x20u
+#define MCG_C6_CME0_SHIFT                        5
+#define MCG_C6_CME0_WIDTH                        1
+#define MCG_C6_CME0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_CME0_SHIFT))&MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK                         0x40u
+#define MCG_C6_PLLS_SHIFT                        6
+#define MCG_C6_PLLS_WIDTH                        1
+#define MCG_C6_PLLS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_PLLS_SHIFT))&MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK                       0x80u
+#define MCG_C6_LOLIE0_SHIFT                      7
+#define MCG_C6_LOLIE0_WIDTH                      1
+#define MCG_C6_LOLIE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C6_LOLIE0_SHIFT))&MCG_C6_LOLIE0_MASK)
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK                         0x1u
+#define MCG_S_IRCST_SHIFT                        0
+#define MCG_S_IRCST_WIDTH                        1
+#define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_IRCST_SHIFT))&MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK                      0x2u
+#define MCG_S_OSCINIT0_SHIFT                     1
+#define MCG_S_OSCINIT0_WIDTH                     1
+#define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK                         0xCu
+#define MCG_S_CLKST_SHIFT                        2
+#define MCG_S_CLKST_WIDTH                        2
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK                        0x10u
+#define MCG_S_IREFST_SHIFT                       4
+#define MCG_S_IREFST_WIDTH                       1
+#define MCG_S_IREFST(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_S_IREFST_SHIFT))&MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK                         0x20u
+#define MCG_S_PLLST_SHIFT                        5
+#define MCG_S_PLLST_WIDTH                        1
+#define MCG_S_PLLST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_PLLST_SHIFT))&MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK                         0x40u
+#define MCG_S_LOCK0_SHIFT                        6
+#define MCG_S_LOCK0_WIDTH                        1
+#define MCG_S_LOCK0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOCK0_SHIFT))&MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK                         0x80u
+#define MCG_S_LOLS0_SHIFT                        7
+#define MCG_S_LOLS0_WIDTH                        1
+#define MCG_S_LOLS0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOLS0_SHIFT))&MCG_S_LOLS0_MASK)
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK                        0x1u
+#define MCG_SC_LOCS0_SHIFT                       0
+#define MCG_SC_LOCS0_WIDTH                       1
+#define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_SC_LOCS0_SHIFT))&MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK                       0xEu
+#define MCG_SC_FCRDIV_SHIFT                      1
+#define MCG_SC_FCRDIV_WIDTH                      3
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK                     0x10u
+#define MCG_SC_FLTPRSRV_SHIFT                    4
+#define MCG_SC_FLTPRSRV_WIDTH                    1
+#define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_SC_FLTPRSRV_SHIFT))&MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK                         0x20u
+#define MCG_SC_ATMF_SHIFT                        5
+#define MCG_SC_ATMF_WIDTH                        1
+#define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMF_SHIFT))&MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK                         0x40u
+#define MCG_SC_ATMS_SHIFT                        6
+#define MCG_SC_ATMS_WIDTH                        1
+#define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMS_SHIFT))&MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK                         0x80u
+#define MCG_SC_ATME_SHIFT                        7
+#define MCG_SC_ATME_WIDTH                        1
+#define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATME_SHIFT))&MCG_SC_ATME_MASK)
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK                     0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT                    0
+#define MCG_ATCVH_ATCVH_WIDTH                    8
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK                     0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT                    0
+#define MCG_ATCVL_ATCVL_WIDTH                    8
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK                       0x3u
+#define MCG_C7_OSCSEL_SHIFT                      0
+#define MCG_C7_OSCSEL_WIDTH                      2
+#define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK                        0x1u
+#define MCG_C8_LOCS1_SHIFT                       0
+#define MCG_C8_LOCS1_WIDTH                       1
+#define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCS1_SHIFT))&MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK                         0x20u
+#define MCG_C8_CME1_SHIFT                        5
+#define MCG_C8_CME1_WIDTH                        1
+#define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C8_CME1_SHIFT))&MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK                        0x40u
+#define MCG_C8_LOLRE_SHIFT                       6
+#define MCG_C8_LOLRE_WIDTH                       1
+#define MCG_C8_LOLRE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOLRE_SHIFT))&MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK                       0x80u
+#define MCG_C8_LOCRE1_SHIFT                      7
+#define MCG_C8_LOCRE1_WIDTH                      1
+#define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCRE1_SHIFT))&MCG_C8_LOCRE1_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR                             (MCG)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS                           { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS                            { MCG }
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1                                   MCG_C1_REG(MCG)
+#define MCG_C2                                   MCG_C2_REG(MCG)
+#define MCG_C3                                   MCG_C3_REG(MCG)
+#define MCG_C4                                   MCG_C4_REG(MCG)
+#define MCG_C5                                   MCG_C5_REG(MCG)
+#define MCG_C6                                   MCG_C6_REG(MCG)
+#define MCG_S                                    MCG_S_REG(MCG)
+#define MCG_SC                                   MCG_SC_REG(MCG)
+#define MCG_ATCVH                                MCG_ATCVH_REG(MCG)
+#define MCG_ATCVL                                MCG_ATCVL_REG(MCG)
+#define MCG_C7                                   MCG_C7_REG(MCG)
+#define MCG_C8                                   MCG_C8_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t CR;                                /**< Control Register, offset: 0xC */
+  __IO uint32_t ISCR;                              /**< Interrupt Status Register, offset: 0x10 */
+  __IO uint32_t ETBCC;                             /**< ETB Counter Control register, offset: 0x14 */
+  __IO uint32_t ETBRL;                             /**< ETB Reload register, offset: 0x18 */
+  __I  uint32_t ETBCNT;                            /**< ETB Counter Value register, offset: 0x1C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PID;                               /**< Process ID register, offset: 0x30 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base)                      ((base)->PLASC)
+#define MCM_PLAMC_REG(base)                      ((base)->PLAMC)
+#define MCM_CR_REG(base)                         ((base)->CR)
+#define MCM_ISCR_REG(base)                       ((base)->ISCR)
+#define MCM_ETBCC_REG(base)                      ((base)->ETBCC)
+#define MCM_ETBRL_REG(base)                      ((base)->ETBRL)
+#define MCM_ETBCNT_REG(base)                     ((base)->ETBCNT)
+#define MCM_PID_REG(base)                        ((base)->PID)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK                       0xFFu
+#define MCM_PLASC_ASC_SHIFT                      0
+#define MCM_PLASC_ASC_WIDTH                      8
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK                       0xFFu
+#define MCM_PLAMC_AMC_SHIFT                      0
+#define MCM_PLAMC_AMC_WIDTH                      8
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* CR Bit Fields */
+#define MCM_CR_SRAMUAP_MASK                      0x3000000u
+#define MCM_CR_SRAMUAP_SHIFT                     24
+#define MCM_CR_SRAMUAP_WIDTH                     2
+#define MCM_CR_SRAMUAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP_MASK                      0x4000000u
+#define MCM_CR_SRAMUWP_SHIFT                     26
+#define MCM_CR_SRAMUWP_WIDTH                     1
+#define MCM_CR_SRAMUWP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUWP_SHIFT))&MCM_CR_SRAMUWP_MASK)
+#define MCM_CR_SRAMLAP_MASK                      0x30000000u
+#define MCM_CR_SRAMLAP_SHIFT                     28
+#define MCM_CR_SRAMLAP_WIDTH                     2
+#define MCM_CR_SRAMLAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP_MASK                      0x40000000u
+#define MCM_CR_SRAMLWP_SHIFT                     30
+#define MCM_CR_SRAMLWP_WIDTH                     1
+#define MCM_CR_SRAMLWP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLWP_SHIFT))&MCM_CR_SRAMLWP_MASK)
+/* ISCR Bit Fields */
+#define MCM_ISCR_IRQ_MASK                        0x2u
+#define MCM_ISCR_IRQ_SHIFT                       1
+#define MCM_ISCR_IRQ_WIDTH                       1
+#define MCM_ISCR_IRQ(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_IRQ_SHIFT))&MCM_ISCR_IRQ_MASK)
+#define MCM_ISCR_NMI_MASK                        0x4u
+#define MCM_ISCR_NMI_SHIFT                       2
+#define MCM_ISCR_NMI_WIDTH                       1
+#define MCM_ISCR_NMI(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_NMI_SHIFT))&MCM_ISCR_NMI_MASK)
+#define MCM_ISCR_DHREQ_MASK                      0x8u
+#define MCM_ISCR_DHREQ_SHIFT                     3
+#define MCM_ISCR_DHREQ_WIDTH                     1
+#define MCM_ISCR_DHREQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_DHREQ_SHIFT))&MCM_ISCR_DHREQ_MASK)
+#define MCM_ISCR_FIOC_MASK                       0x100u
+#define MCM_ISCR_FIOC_SHIFT                      8
+#define MCM_ISCR_FIOC_WIDTH                      1
+#define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FDZC_MASK                       0x200u
+#define MCM_ISCR_FDZC_SHIFT                      9
+#define MCM_ISCR_FDZC_WIDTH                      1
+#define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FOFC_MASK                       0x400u
+#define MCM_ISCR_FOFC_SHIFT                      10
+#define MCM_ISCR_FOFC_WIDTH                      1
+#define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FUFC_MASK                       0x800u
+#define MCM_ISCR_FUFC_SHIFT                      11
+#define MCM_ISCR_FUFC_WIDTH                      1
+#define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FIXC_MASK                       0x1000u
+#define MCM_ISCR_FIXC_SHIFT                      12
+#define MCM_ISCR_FIXC_WIDTH                      1
+#define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIDC_MASK                       0x8000u
+#define MCM_ISCR_FIDC_SHIFT                      15
+#define MCM_ISCR_FIDC_WIDTH                      1
+#define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIOCE_MASK                      0x1000000u
+#define MCM_ISCR_FIOCE_SHIFT                     24
+#define MCM_ISCR_FIOCE_WIDTH                     1
+#define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FDZCE_MASK                      0x2000000u
+#define MCM_ISCR_FDZCE_SHIFT                     25
+#define MCM_ISCR_FDZCE_WIDTH                     1
+#define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FOFCE_MASK                      0x4000000u
+#define MCM_ISCR_FOFCE_SHIFT                     26
+#define MCM_ISCR_FOFCE_WIDTH                     1
+#define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FUFCE_MASK                      0x8000000u
+#define MCM_ISCR_FUFCE_SHIFT                     27
+#define MCM_ISCR_FUFCE_WIDTH                     1
+#define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FIXCE_MASK                      0x10000000u
+#define MCM_ISCR_FIXCE_SHIFT                     28
+#define MCM_ISCR_FIXCE_WIDTH                     1
+#define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIDCE_MASK                      0x80000000u
+#define MCM_ISCR_FIDCE_SHIFT                     31
+#define MCM_ISCR_FIDCE_WIDTH                     1
+#define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
+/* ETBCC Bit Fields */
+#define MCM_ETBCC_CNTEN_MASK                     0x1u
+#define MCM_ETBCC_CNTEN_SHIFT                    0
+#define MCM_ETBCC_CNTEN_WIDTH                    1
+#define MCM_ETBCC_CNTEN(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_CNTEN_SHIFT))&MCM_ETBCC_CNTEN_MASK)
+#define MCM_ETBCC_RSPT_MASK                      0x6u
+#define MCM_ETBCC_RSPT_SHIFT                     1
+#define MCM_ETBCC_RSPT_WIDTH                     2
+#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK                      0x8u
+#define MCM_ETBCC_RLRQ_SHIFT                     3
+#define MCM_ETBCC_RLRQ_WIDTH                     1
+#define MCM_ETBCC_RLRQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RLRQ_SHIFT))&MCM_ETBCC_RLRQ_MASK)
+#define MCM_ETBCC_ETDIS_MASK                     0x10u
+#define MCM_ETBCC_ETDIS_SHIFT                    4
+#define MCM_ETBCC_ETDIS_WIDTH                    1
+#define MCM_ETBCC_ETDIS(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ETDIS_SHIFT))&MCM_ETBCC_ETDIS_MASK)
+#define MCM_ETBCC_ITDIS_MASK                     0x20u
+#define MCM_ETBCC_ITDIS_SHIFT                    5
+#define MCM_ETBCC_ITDIS_WIDTH                    1
+#define MCM_ETBCC_ITDIS(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ITDIS_SHIFT))&MCM_ETBCC_ITDIS_MASK)
+/* ETBRL Bit Fields */
+#define MCM_ETBRL_RELOAD_MASK                    0x7FFu
+#define MCM_ETBRL_RELOAD_SHIFT                   0
+#define MCM_ETBRL_RELOAD_WIDTH                   11
+#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
+/* ETBCNT Bit Fields */
+#define MCM_ETBCNT_COUNTER_MASK                  0x7FFu
+#define MCM_ETBCNT_COUNTER_SHIFT                 0
+#define MCM_ETBCNT_COUNTER_WIDTH                 11
+#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
+/* PID Bit Fields */
+#define MCM_PID_PID_MASK                         0xFFu
+#define MCM_PID_PID_SHIFT                        0
+#define MCM_PID_PID_WIDTH                        8
+#define MCM_PID_PID(x)                           (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR                             (MCM)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { MCM }
+/** Interrupt vectors for the MCM peripheral type */
+#define MCM_IRQS                                 { MCM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC                                MCM_PLASC_REG(MCM)
+#define MCM_PLAMC                                MCM_PLAMC_REG(MCM)
+#define MCM_CR                                   MCM_CR_REG(MCM)
+#define MCM_ISCR                                 MCM_ISCR_REG(MCM)
+#define MCM_ETBCC                                MCM_ETBCC_REG(MCM)
+#define MCM_ETBRL                                MCM_ETBRL_REG(MCM)
+#define MCM_ETBCNT                               MCM_ETBCNT_REG(MCM)
+#define MCM_PID                                  MCM_PID_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
+ * @{
+ */
+
+/** MPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} MPU_Type, *MPU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register accessors */
+#define MPU_CESR_REG(base)                       ((base)->CESR)
+#define MPU_EAR_REG(base,index)                  ((base)->SP[index].EAR)
+#define MPU_EAR_COUNT                            5
+#define MPU_EDR_REG(base,index)                  ((base)->SP[index].EDR)
+#define MPU_EDR_COUNT                            5
+#define MPU_WORD_REG(base,index,index2)          ((base)->WORD[index][index2])
+#define MPU_WORD_COUNT                           12
+#define MPU_WORD_COUNT2                          4
+#define MPU_RGDAAC_REG(base,index)               ((base)->RGDAAC[index])
+#define MPU_RGDAAC_COUNT                         12
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Masks MPU Register Masks
+ * @{
+ */
+
+/* CESR Bit Fields */
+#define MPU_CESR_VLD_MASK                        0x1u
+#define MPU_CESR_VLD_SHIFT                       0
+#define MPU_CESR_VLD_WIDTH                       1
+#define MPU_CESR_VLD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_VLD_SHIFT))&MPU_CESR_VLD_MASK)
+#define MPU_CESR_NRGD_MASK                       0xF00u
+#define MPU_CESR_NRGD_SHIFT                      8
+#define MPU_CESR_NRGD_WIDTH                      4
+#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
+#define MPU_CESR_NSP_MASK                        0xF000u
+#define MPU_CESR_NSP_SHIFT                       12
+#define MPU_CESR_NSP_WIDTH                       4
+#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
+#define MPU_CESR_HRL_MASK                        0xF0000u
+#define MPU_CESR_HRL_SHIFT                       16
+#define MPU_CESR_HRL_WIDTH                       4
+#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
+#define MPU_CESR_SPERR_MASK                      0xF8000000u
+#define MPU_CESR_SPERR_SHIFT                     27
+#define MPU_CESR_SPERR_WIDTH                     5
+#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
+/* EAR Bit Fields */
+#define MPU_EAR_EADDR_MASK                       0xFFFFFFFFu
+#define MPU_EAR_EADDR_SHIFT                      0
+#define MPU_EAR_EADDR_WIDTH                      32
+#define MPU_EAR_EADDR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
+/* EDR Bit Fields */
+#define MPU_EDR_ERW_MASK                         0x1u
+#define MPU_EDR_ERW_SHIFT                        0
+#define MPU_EDR_ERW_WIDTH                        1
+#define MPU_EDR_ERW(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_ERW_SHIFT))&MPU_EDR_ERW_MASK)
+#define MPU_EDR_EATTR_MASK                       0xEu
+#define MPU_EDR_EATTR_SHIFT                      1
+#define MPU_EDR_EATTR_WIDTH                      3
+#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
+#define MPU_EDR_EMN_MASK                         0xF0u
+#define MPU_EDR_EMN_SHIFT                        4
+#define MPU_EDR_EMN_WIDTH                        4
+#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
+#define MPU_EDR_EPID_MASK                        0xFF00u
+#define MPU_EDR_EPID_SHIFT                       8
+#define MPU_EDR_EPID_WIDTH                       8
+#define MPU_EDR_EPID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
+#define MPU_EDR_EACD_MASK                        0xFFFF0000u
+#define MPU_EDR_EACD_SHIFT                       16
+#define MPU_EDR_EACD_WIDTH                       16
+#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
+/* WORD Bit Fields */
+#define MPU_WORD_VLD_MASK                        0x1u
+#define MPU_WORD_VLD_SHIFT                       0
+#define MPU_WORD_VLD_WIDTH                       1
+#define MPU_WORD_VLD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_VLD_SHIFT))&MPU_WORD_VLD_MASK)
+#define MPU_WORD_M0UM_MASK                       0x7u
+#define MPU_WORD_M0UM_SHIFT                      0
+#define MPU_WORD_M0UM_WIDTH                      3
+#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
+#define MPU_WORD_M0SM_MASK                       0x18u
+#define MPU_WORD_M0SM_SHIFT                      3
+#define MPU_WORD_M0SM_WIDTH                      2
+#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
+#define MPU_WORD_M0PE_MASK                       0x20u
+#define MPU_WORD_M0PE_SHIFT                      5
+#define MPU_WORD_M0PE_WIDTH                      1
+#define MPU_WORD_M0PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0PE_SHIFT))&MPU_WORD_M0PE_MASK)
+#define MPU_WORD_ENDADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_ENDADDR_SHIFT                   5
+#define MPU_WORD_ENDADDR_WIDTH                   27
+#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
+#define MPU_WORD_SRTADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_SRTADDR_SHIFT                   5
+#define MPU_WORD_SRTADDR_WIDTH                   27
+#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
+#define MPU_WORD_M1UM_MASK                       0x1C0u
+#define MPU_WORD_M1UM_SHIFT                      6
+#define MPU_WORD_M1UM_WIDTH                      3
+#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
+#define MPU_WORD_M1SM_MASK                       0x600u
+#define MPU_WORD_M1SM_SHIFT                      9
+#define MPU_WORD_M1SM_WIDTH                      2
+#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
+#define MPU_WORD_M1PE_MASK                       0x800u
+#define MPU_WORD_M1PE_SHIFT                      11
+#define MPU_WORD_M1PE_WIDTH                      1
+#define MPU_WORD_M1PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1PE_SHIFT))&MPU_WORD_M1PE_MASK)
+#define MPU_WORD_M2UM_MASK                       0x7000u
+#define MPU_WORD_M2UM_SHIFT                      12
+#define MPU_WORD_M2UM_WIDTH                      3
+#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
+#define MPU_WORD_M2SM_MASK                       0x18000u
+#define MPU_WORD_M2SM_SHIFT                      15
+#define MPU_WORD_M2SM_WIDTH                      2
+#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
+#define MPU_WORD_PIDMASK_MASK                    0xFF0000u
+#define MPU_WORD_PIDMASK_SHIFT                   16
+#define MPU_WORD_PIDMASK_WIDTH                   8
+#define MPU_WORD_PIDMASK(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
+#define MPU_WORD_M2PE_MASK                       0x20000u
+#define MPU_WORD_M2PE_SHIFT                      17
+#define MPU_WORD_M2PE_WIDTH                      1
+#define MPU_WORD_M2PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2PE_SHIFT))&MPU_WORD_M2PE_MASK)
+#define MPU_WORD_M3UM_MASK                       0x1C0000u
+#define MPU_WORD_M3UM_SHIFT                      18
+#define MPU_WORD_M3UM_WIDTH                      3
+#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
+#define MPU_WORD_M3SM_MASK                       0x600000u
+#define MPU_WORD_M3SM_SHIFT                      21
+#define MPU_WORD_M3SM_WIDTH                      2
+#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
+#define MPU_WORD_M3PE_MASK                       0x800000u
+#define MPU_WORD_M3PE_SHIFT                      23
+#define MPU_WORD_M3PE_WIDTH                      1
+#define MPU_WORD_M3PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3PE_SHIFT))&MPU_WORD_M3PE_MASK)
+#define MPU_WORD_PID_MASK                        0xFF000000u
+#define MPU_WORD_PID_SHIFT                       24
+#define MPU_WORD_PID_WIDTH                       8
+#define MPU_WORD_PID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
+#define MPU_WORD_M4WE_MASK                       0x1000000u
+#define MPU_WORD_M4WE_SHIFT                      24
+#define MPU_WORD_M4WE_WIDTH                      1
+#define MPU_WORD_M4WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4WE_SHIFT))&MPU_WORD_M4WE_MASK)
+#define MPU_WORD_M4RE_MASK                       0x2000000u
+#define MPU_WORD_M4RE_SHIFT                      25
+#define MPU_WORD_M4RE_WIDTH                      1
+#define MPU_WORD_M4RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4RE_SHIFT))&MPU_WORD_M4RE_MASK)
+#define MPU_WORD_M5WE_MASK                       0x4000000u
+#define MPU_WORD_M5WE_SHIFT                      26
+#define MPU_WORD_M5WE_WIDTH                      1
+#define MPU_WORD_M5WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5WE_SHIFT))&MPU_WORD_M5WE_MASK)
+#define MPU_WORD_M5RE_MASK                       0x8000000u
+#define MPU_WORD_M5RE_SHIFT                      27
+#define MPU_WORD_M5RE_WIDTH                      1
+#define MPU_WORD_M5RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5RE_SHIFT))&MPU_WORD_M5RE_MASK)
+#define MPU_WORD_M6WE_MASK                       0x10000000u
+#define MPU_WORD_M6WE_SHIFT                      28
+#define MPU_WORD_M6WE_WIDTH                      1
+#define MPU_WORD_M6WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6WE_SHIFT))&MPU_WORD_M6WE_MASK)
+#define MPU_WORD_M6RE_MASK                       0x20000000u
+#define MPU_WORD_M6RE_SHIFT                      29
+#define MPU_WORD_M6RE_WIDTH                      1
+#define MPU_WORD_M6RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6RE_SHIFT))&MPU_WORD_M6RE_MASK)
+#define MPU_WORD_M7WE_MASK                       0x40000000u
+#define MPU_WORD_M7WE_SHIFT                      30
+#define MPU_WORD_M7WE_WIDTH                      1
+#define MPU_WORD_M7WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7WE_SHIFT))&MPU_WORD_M7WE_MASK)
+#define MPU_WORD_M7RE_MASK                       0x80000000u
+#define MPU_WORD_M7RE_SHIFT                      31
+#define MPU_WORD_M7RE_WIDTH                      1
+#define MPU_WORD_M7RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7RE_SHIFT))&MPU_WORD_M7RE_MASK)
+/* RGDAAC Bit Fields */
+#define MPU_RGDAAC_M0UM_MASK                     0x7u
+#define MPU_RGDAAC_M0UM_SHIFT                    0
+#define MPU_RGDAAC_M0UM_WIDTH                    3
+#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
+#define MPU_RGDAAC_M0SM_MASK                     0x18u
+#define MPU_RGDAAC_M0SM_SHIFT                    3
+#define MPU_RGDAAC_M0SM_WIDTH                    2
+#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
+#define MPU_RGDAAC_M0PE_MASK                     0x20u
+#define MPU_RGDAAC_M0PE_SHIFT                    5
+#define MPU_RGDAAC_M0PE_WIDTH                    1
+#define MPU_RGDAAC_M0PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0PE_SHIFT))&MPU_RGDAAC_M0PE_MASK)
+#define MPU_RGDAAC_M1UM_MASK                     0x1C0u
+#define MPU_RGDAAC_M1UM_SHIFT                    6
+#define MPU_RGDAAC_M1UM_WIDTH                    3
+#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
+#define MPU_RGDAAC_M1SM_MASK                     0x600u
+#define MPU_RGDAAC_M1SM_SHIFT                    9
+#define MPU_RGDAAC_M1SM_WIDTH                    2
+#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
+#define MPU_RGDAAC_M1PE_MASK                     0x800u
+#define MPU_RGDAAC_M1PE_SHIFT                    11
+#define MPU_RGDAAC_M1PE_WIDTH                    1
+#define MPU_RGDAAC_M1PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1PE_SHIFT))&MPU_RGDAAC_M1PE_MASK)
+#define MPU_RGDAAC_M2UM_MASK                     0x7000u
+#define MPU_RGDAAC_M2UM_SHIFT                    12
+#define MPU_RGDAAC_M2UM_WIDTH                    3
+#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
+#define MPU_RGDAAC_M2SM_MASK                     0x18000u
+#define MPU_RGDAAC_M2SM_SHIFT                    15
+#define MPU_RGDAAC_M2SM_WIDTH                    2
+#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
+#define MPU_RGDAAC_M2PE_MASK                     0x20000u
+#define MPU_RGDAAC_M2PE_SHIFT                    17
+#define MPU_RGDAAC_M2PE_WIDTH                    1
+#define MPU_RGDAAC_M2PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2PE_SHIFT))&MPU_RGDAAC_M2PE_MASK)
+#define MPU_RGDAAC_M3UM_MASK                     0x1C0000u
+#define MPU_RGDAAC_M3UM_SHIFT                    18
+#define MPU_RGDAAC_M3UM_WIDTH                    3
+#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
+#define MPU_RGDAAC_M3SM_MASK                     0x600000u
+#define MPU_RGDAAC_M3SM_SHIFT                    21
+#define MPU_RGDAAC_M3SM_WIDTH                    2
+#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
+#define MPU_RGDAAC_M3PE_MASK                     0x800000u
+#define MPU_RGDAAC_M3PE_SHIFT                    23
+#define MPU_RGDAAC_M3PE_WIDTH                    1
+#define MPU_RGDAAC_M3PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3PE_SHIFT))&MPU_RGDAAC_M3PE_MASK)
+#define MPU_RGDAAC_M4WE_MASK                     0x1000000u
+#define MPU_RGDAAC_M4WE_SHIFT                    24
+#define MPU_RGDAAC_M4WE_WIDTH                    1
+#define MPU_RGDAAC_M4WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4WE_SHIFT))&MPU_RGDAAC_M4WE_MASK)
+#define MPU_RGDAAC_M4RE_MASK                     0x2000000u
+#define MPU_RGDAAC_M4RE_SHIFT                    25
+#define MPU_RGDAAC_M4RE_WIDTH                    1
+#define MPU_RGDAAC_M4RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4RE_SHIFT))&MPU_RGDAAC_M4RE_MASK)
+#define MPU_RGDAAC_M5WE_MASK                     0x4000000u
+#define MPU_RGDAAC_M5WE_SHIFT                    26
+#define MPU_RGDAAC_M5WE_WIDTH                    1
+#define MPU_RGDAAC_M5WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5WE_SHIFT))&MPU_RGDAAC_M5WE_MASK)
+#define MPU_RGDAAC_M5RE_MASK                     0x8000000u
+#define MPU_RGDAAC_M5RE_SHIFT                    27
+#define MPU_RGDAAC_M5RE_WIDTH                    1
+#define MPU_RGDAAC_M5RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5RE_SHIFT))&MPU_RGDAAC_M5RE_MASK)
+#define MPU_RGDAAC_M6WE_MASK                     0x10000000u
+#define MPU_RGDAAC_M6WE_SHIFT                    28
+#define MPU_RGDAAC_M6WE_WIDTH                    1
+#define MPU_RGDAAC_M6WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6WE_SHIFT))&MPU_RGDAAC_M6WE_MASK)
+#define MPU_RGDAAC_M6RE_MASK                     0x20000000u
+#define MPU_RGDAAC_M6RE_SHIFT                    29
+#define MPU_RGDAAC_M6RE_WIDTH                    1
+#define MPU_RGDAAC_M6RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6RE_SHIFT))&MPU_RGDAAC_M6RE_MASK)
+#define MPU_RGDAAC_M7WE_MASK                     0x40000000u
+#define MPU_RGDAAC_M7WE_SHIFT                    30
+#define MPU_RGDAAC_M7WE_WIDTH                    1
+#define MPU_RGDAAC_M7WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7WE_SHIFT))&MPU_RGDAAC_M7WE_MASK)
+#define MPU_RGDAAC_M7RE_MASK                     0x80000000u
+#define MPU_RGDAAC_M7RE_SHIFT                    31
+#define MPU_RGDAAC_M7RE_WIDTH                    1
+#define MPU_RGDAAC_M7RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7RE_SHIFT))&MPU_RGDAAC_M7RE_MASK)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Masks */
+
+
+/* MPU - Peripheral instance base addresses */
+/** Peripheral MPU base address */
+#define MPU_BASE                                 (0x4000D000u)
+/** Peripheral MPU base pointer */
+#define MPU                                      ((MPU_Type *)MPU_BASE)
+#define MPU_BASE_PTR                             (MPU)
+/** Array initializer of MPU peripheral base addresses */
+#define MPU_BASE_ADDRS                           { MPU_BASE }
+/** Array initializer of MPU peripheral base pointers */
+#define MPU_BASE_PTRS                            { MPU }
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register instance definitions */
+/* MPU */
+#define MPU_CESR                                 MPU_CESR_REG(MPU)
+#define MPU_EAR0                                 MPU_EAR_REG(MPU,0)
+#define MPU_EDR0                                 MPU_EDR_REG(MPU,0)
+#define MPU_EAR1                                 MPU_EAR_REG(MPU,1)
+#define MPU_EDR1                                 MPU_EDR_REG(MPU,1)
+#define MPU_EAR2                                 MPU_EAR_REG(MPU,2)
+#define MPU_EDR2                                 MPU_EDR_REG(MPU,2)
+#define MPU_EAR3                                 MPU_EAR_REG(MPU,3)
+#define MPU_EDR3                                 MPU_EDR_REG(MPU,3)
+#define MPU_EAR4                                 MPU_EAR_REG(MPU,4)
+#define MPU_EDR4                                 MPU_EDR_REG(MPU,4)
+#define MPU_RGD0_WORD0                           MPU_WORD_REG(MPU,0,0)
+#define MPU_RGD0_WORD1                           MPU_WORD_REG(MPU,0,1)
+#define MPU_RGD0_WORD2                           MPU_WORD_REG(MPU,0,2)
+#define MPU_RGD0_WORD3                           MPU_WORD_REG(MPU,0,3)
+#define MPU_RGD1_WORD0                           MPU_WORD_REG(MPU,1,0)
+#define MPU_RGD1_WORD1                           MPU_WORD_REG(MPU,1,1)
+#define MPU_RGD1_WORD2                           MPU_WORD_REG(MPU,1,2)
+#define MPU_RGD1_WORD3                           MPU_WORD_REG(MPU,1,3)
+#define MPU_RGD2_WORD0                           MPU_WORD_REG(MPU,2,0)
+#define MPU_RGD2_WORD1                           MPU_WORD_REG(MPU,2,1)
+#define MPU_RGD2_WORD2                           MPU_WORD_REG(MPU,2,2)
+#define MPU_RGD2_WORD3                           MPU_WORD_REG(MPU,2,3)
+#define MPU_RGD3_WORD0                           MPU_WORD_REG(MPU,3,0)
+#define MPU_RGD3_WORD1                           MPU_WORD_REG(MPU,3,1)
+#define MPU_RGD3_WORD2                           MPU_WORD_REG(MPU,3,2)
+#define MPU_RGD3_WORD3                           MPU_WORD_REG(MPU,3,3)
+#define MPU_RGD4_WORD0                           MPU_WORD_REG(MPU,4,0)
+#define MPU_RGD4_WORD1                           MPU_WORD_REG(MPU,4,1)
+#define MPU_RGD4_WORD2                           MPU_WORD_REG(MPU,4,2)
+#define MPU_RGD4_WORD3                           MPU_WORD_REG(MPU,4,3)
+#define MPU_RGD5_WORD0                           MPU_WORD_REG(MPU,5,0)
+#define MPU_RGD5_WORD1                           MPU_WORD_REG(MPU,5,1)
+#define MPU_RGD5_WORD2                           MPU_WORD_REG(MPU,5,2)
+#define MPU_RGD5_WORD3                           MPU_WORD_REG(MPU,5,3)
+#define MPU_RGD6_WORD0                           MPU_WORD_REG(MPU,6,0)
+#define MPU_RGD6_WORD1                           MPU_WORD_REG(MPU,6,1)
+#define MPU_RGD6_WORD2                           MPU_WORD_REG(MPU,6,2)
+#define MPU_RGD6_WORD3                           MPU_WORD_REG(MPU,6,3)
+#define MPU_RGD7_WORD0                           MPU_WORD_REG(MPU,7,0)
+#define MPU_RGD7_WORD1                           MPU_WORD_REG(MPU,7,1)
+#define MPU_RGD7_WORD2                           MPU_WORD_REG(MPU,7,2)
+#define MPU_RGD7_WORD3                           MPU_WORD_REG(MPU,7,3)
+#define MPU_RGD8_WORD0                           MPU_WORD_REG(MPU,8,0)
+#define MPU_RGD8_WORD1                           MPU_WORD_REG(MPU,8,1)
+#define MPU_RGD8_WORD2                           MPU_WORD_REG(MPU,8,2)
+#define MPU_RGD8_WORD3                           MPU_WORD_REG(MPU,8,3)
+#define MPU_RGD9_WORD0                           MPU_WORD_REG(MPU,9,0)
+#define MPU_RGD9_WORD1                           MPU_WORD_REG(MPU,9,1)
+#define MPU_RGD9_WORD2                           MPU_WORD_REG(MPU,9,2)
+#define MPU_RGD9_WORD3                           MPU_WORD_REG(MPU,9,3)
+#define MPU_RGD10_WORD0                          MPU_WORD_REG(MPU,10,0)
+#define MPU_RGD10_WORD1                          MPU_WORD_REG(MPU,10,1)
+#define MPU_RGD10_WORD2                          MPU_WORD_REG(MPU,10,2)
+#define MPU_RGD10_WORD3                          MPU_WORD_REG(MPU,10,3)
+#define MPU_RGD11_WORD0                          MPU_WORD_REG(MPU,11,0)
+#define MPU_RGD11_WORD1                          MPU_WORD_REG(MPU,11,1)
+#define MPU_RGD11_WORD2                          MPU_WORD_REG(MPU,11,2)
+#define MPU_RGD11_WORD3                          MPU_WORD_REG(MPU,11,3)
+#define MPU_RGDAAC0                              MPU_RGDAAC_REG(MPU,0)
+#define MPU_RGDAAC1                              MPU_RGDAAC_REG(MPU,1)
+#define MPU_RGDAAC2                              MPU_RGDAAC_REG(MPU,2)
+#define MPU_RGDAAC3                              MPU_RGDAAC_REG(MPU,3)
+#define MPU_RGDAAC4                              MPU_RGDAAC_REG(MPU,4)
+#define MPU_RGDAAC5                              MPU_RGDAAC_REG(MPU,5)
+#define MPU_RGDAAC6                              MPU_RGDAAC_REG(MPU,6)
+#define MPU_RGDAAC7                              MPU_RGDAAC_REG(MPU,7)
+#define MPU_RGDAAC8                              MPU_RGDAAC_REG(MPU,8)
+#define MPU_RGDAAC9                              MPU_RGDAAC_REG(MPU,9)
+#define MPU_RGDAAC10                             MPU_RGDAAC_REG(MPU,10)
+#define MPU_RGDAAC11                             MPU_RGDAAC_REG(MPU,11)
+
+/* MPU - Register array accessors */
+#define MPU_EAR(index)                           MPU_EAR_REG(MPU,index)
+#define MPU_EDR(index)                           MPU_EDR_REG(MPU,index)
+#define MPU_WORD(index,index2)                   MPU_WORD_REG(MPU,index,index2)
+#define MPU_RGDAAC(index)                        MPU_RGDAAC_REG(MPU,index)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+  __I  uint8_t FEPROT;                             /**< Non-volatile EERAM Protection Register, offset: 0xE */
+  __I  uint8_t FDPROT;                             /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base)                    ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base)                    ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base)                    ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base)                    ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base)                    ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base)                    ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base)                    ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base)                    ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base)                      ((base)->FPROT3)
+#define NV_FPROT2_REG(base)                      ((base)->FPROT2)
+#define NV_FPROT1_REG(base)                      ((base)->FPROT1)
+#define NV_FPROT0_REG(base)                      ((base)->FPROT0)
+#define NV_FSEC_REG(base)                        ((base)->FSEC)
+#define NV_FOPT_REG(base)                        ((base)->FOPT)
+#define NV_FEPROT_REG(base)                      ((base)->FEPROT)
+#define NV_FDPROT_REG(base)                      ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK                     0xFFu
+#define NV_BACKKEY3_KEY_SHIFT                    0
+#define NV_BACKKEY3_KEY_WIDTH                    8
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK                     0xFFu
+#define NV_BACKKEY2_KEY_SHIFT                    0
+#define NV_BACKKEY2_KEY_WIDTH                    8
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK                     0xFFu
+#define NV_BACKKEY1_KEY_SHIFT                    0
+#define NV_BACKKEY1_KEY_WIDTH                    8
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK                     0xFFu
+#define NV_BACKKEY0_KEY_SHIFT                    0
+#define NV_BACKKEY0_KEY_WIDTH                    8
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK                     0xFFu
+#define NV_BACKKEY7_KEY_SHIFT                    0
+#define NV_BACKKEY7_KEY_WIDTH                    8
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK                     0xFFu
+#define NV_BACKKEY6_KEY_SHIFT                    0
+#define NV_BACKKEY6_KEY_WIDTH                    8
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK                     0xFFu
+#define NV_BACKKEY5_KEY_SHIFT                    0
+#define NV_BACKKEY5_KEY_WIDTH                    8
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK                     0xFFu
+#define NV_BACKKEY4_KEY_SHIFT                    0
+#define NV_BACKKEY4_KEY_WIDTH                    8
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK                      0xFFu
+#define NV_FPROT3_PROT_SHIFT                     0
+#define NV_FPROT3_PROT_WIDTH                     8
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK                      0xFFu
+#define NV_FPROT2_PROT_SHIFT                     0
+#define NV_FPROT2_PROT_WIDTH                     8
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK                      0xFFu
+#define NV_FPROT1_PROT_SHIFT                     0
+#define NV_FPROT1_PROT_WIDTH                     8
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK                      0xFFu
+#define NV_FPROT0_PROT_SHIFT                     0
+#define NV_FPROT0_PROT_WIDTH                     8
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK                         0x3u
+#define NV_FSEC_SEC_SHIFT                        0
+#define NV_FSEC_SEC_WIDTH                        2
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      0xCu
+#define NV_FSEC_FSLACC_SHIFT                     2
+#define NV_FSEC_FSLACC_WIDTH                     2
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        0x30u
+#define NV_FSEC_MEEN_SHIFT                       4
+#define NV_FSEC_MEEN_WIDTH                       2
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       0xC0u
+#define NV_FSEC_KEYEN_SHIFT                      6
+#define NV_FSEC_KEYEN_WIDTH                      2
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK                      0x1u
+#define NV_FOPT_LPBOOT_SHIFT                     0
+#define NV_FOPT_LPBOOT_WIDTH                     1
+#define NV_FOPT_LPBOOT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT_SHIFT))&NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK                  0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT                 1
+#define NV_FOPT_EZPORT_DIS_WIDTH                 1
+#define NV_FOPT_EZPORT_DIS(x)                    (((uint8_t)(((uint8_t)(x))<<NV_FOPT_EZPORT_DIS_SHIFT))&NV_FOPT_EZPORT_DIS_MASK)
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK                     0xFFu
+#define NV_FEPROT_EPROT_SHIFT                    0
+#define NV_FEPROT_EPROT_WIDTH                    8
+#define NV_FEPROT_EPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK                     0xFFu
+#define NV_FDPROT_DPROT_SHIFT                    0
+#define NV_FDPROT_DPROT_WIDTH                    8
+#define NV_FDPROT_DPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFE_FlashConfig base address */
+#define FTFE_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFE_FlashConfig base pointer */
+#define FTFE_FlashConfig                         ((NV_Type *)FTFE_FlashConfig_BASE)
+#define FTFE_FlashConfig_BASE_PTR                (FTFE_FlashConfig)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS                            { FTFE_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS                             { FTFE_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFE_FlashConfig */
+#define NV_BACKKEY3                              NV_BACKKEY3_REG(FTFE_FlashConfig)
+#define NV_BACKKEY2                              NV_BACKKEY2_REG(FTFE_FlashConfig)
+#define NV_BACKKEY1                              NV_BACKKEY1_REG(FTFE_FlashConfig)
+#define NV_BACKKEY0                              NV_BACKKEY0_REG(FTFE_FlashConfig)
+#define NV_BACKKEY7                              NV_BACKKEY7_REG(FTFE_FlashConfig)
+#define NV_BACKKEY6                              NV_BACKKEY6_REG(FTFE_FlashConfig)
+#define NV_BACKKEY5                              NV_BACKKEY5_REG(FTFE_FlashConfig)
+#define NV_BACKKEY4                              NV_BACKKEY4_REG(FTFE_FlashConfig)
+#define NV_FPROT3                                NV_FPROT3_REG(FTFE_FlashConfig)
+#define NV_FPROT2                                NV_FPROT2_REG(FTFE_FlashConfig)
+#define NV_FPROT1                                NV_FPROT1_REG(FTFE_FlashConfig)
+#define NV_FPROT0                                NV_FPROT0_REG(FTFE_FlashConfig)
+#define NV_FSEC                                  NV_FSEC_REG(FTFE_FlashConfig)
+#define NV_FOPT                                  NV_FOPT_REG(FTFE_FlashConfig)
+#define NV_FEPROT                                NV_FEPROT_REG(FTFE_FlashConfig)
+#define NV_FDPROT                                NV_FDPROT_REG(FTFE_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base)                         ((base)->CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK                        0x1u
+#define OSC_CR_SC16P_SHIFT                       0
+#define OSC_CR_SC16P_WIDTH                       1
+#define OSC_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK                         0x2u
+#define OSC_CR_SC8P_SHIFT                        1
+#define OSC_CR_SC8P_WIDTH                        1
+#define OSC_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK                         0x4u
+#define OSC_CR_SC4P_SHIFT                        2
+#define OSC_CR_SC4P_WIDTH                        1
+#define OSC_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK                         0x8u
+#define OSC_CR_SC2P_SHIFT                        3
+#define OSC_CR_SC2P_WIDTH                        1
+#define OSC_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK                     0x20u
+#define OSC_CR_EREFSTEN_SHIFT                    5
+#define OSC_CR_EREFSTEN_WIDTH                    1
+#define OSC_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK                      0x80u
+#define OSC_CR_ERCLKEN_SHIFT                     7
+#define OSC_CR_ERCLKEN_WIDTH                     1
+#define OSC_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE                                 (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC                                      ((OSC_Type *)OSC_BASE)
+#define OSC_BASE_PTR                             (OSC)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS                           { OSC_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS                            { OSC }
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC */
+#define OSC_CR                                   OSC_CR_REG(OSC)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control register, offset: 0x0 */
+  __IO uint32_t MOD;                               /**< Modulus register, offset: 0x4 */
+  __I  uint32_t CNT;                               /**< Counter register, offset: 0x8 */
+  __IO uint32_t IDLY;                              /**< Interrupt Delay register, offset: 0xC */
+  struct {                                         /* offset: 0x10, array step: 0x28 */
+    __IO uint32_t C1;                                /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+    __IO uint32_t S;                                 /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+    __IO uint32_t DLY[2];                            /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+         uint8_t RESERVED_0[24];
+  } CH[2];
+       uint8_t RESERVED_0[240];
+  struct {                                         /* offset: 0x150, array step: 0x8 */
+    __IO uint32_t INTC;                              /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+    __IO uint32_t INT;                               /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+  } DAC[2];
+       uint8_t RESERVED_1[48];
+  __IO uint32_t POEN;                              /**< Pulse-Out n Enable register, offset: 0x190 */
+  __IO uint32_t PODLY[3];                          /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type, *PDB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register accessors */
+#define PDB_SC_REG(base)                         ((base)->SC)
+#define PDB_MOD_REG(base)                        ((base)->MOD)
+#define PDB_CNT_REG(base)                        ((base)->CNT)
+#define PDB_IDLY_REG(base)                       ((base)->IDLY)
+#define PDB_C1_REG(base,index)                   ((base)->CH[index].C1)
+#define PDB_C1_COUNT                             2
+#define PDB_S_REG(base,index)                    ((base)->CH[index].S)
+#define PDB_S_COUNT                              2
+#define PDB_DLY_REG(base,index,index2)           ((base)->CH[index].DLY[index2])
+#define PDB_DLY_COUNT                            2
+#define PDB_DLY_COUNT2                           2
+#define PDB_INTC_REG(base,index)                 ((base)->DAC[index].INTC)
+#define PDB_INTC_COUNT                           2
+#define PDB_INT_REG(base,index)                  ((base)->DAC[index].INT)
+#define PDB_INT_COUNT                            2
+#define PDB_POEN_REG(base)                       ((base)->POEN)
+#define PDB_PODLY_REG(base,index)                ((base)->PODLY[index])
+#define PDB_PODLY_COUNT                          3
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK                         0x1u
+#define PDB_SC_LDOK_SHIFT                        0
+#define PDB_SC_LDOK_WIDTH                        1
+#define PDB_SC_LDOK(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK                         0x2u
+#define PDB_SC_CONT_SHIFT                        1
+#define PDB_SC_CONT_WIDTH                        1
+#define PDB_SC_CONT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK                         0xCu
+#define PDB_SC_MULT_SHIFT                        2
+#define PDB_SC_MULT_WIDTH                        2
+#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK                        0x20u
+#define PDB_SC_PDBIE_SHIFT                       5
+#define PDB_SC_PDBIE_WIDTH                       1
+#define PDB_SC_PDBIE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK                        0x40u
+#define PDB_SC_PDBIF_SHIFT                       6
+#define PDB_SC_PDBIF_WIDTH                       1
+#define PDB_SC_PDBIF(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK                        0x80u
+#define PDB_SC_PDBEN_SHIFT                       7
+#define PDB_SC_PDBEN_WIDTH                       1
+#define PDB_SC_PDBEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK                       0xF00u
+#define PDB_SC_TRGSEL_SHIFT                      8
+#define PDB_SC_TRGSEL_WIDTH                      4
+#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK                    0x7000u
+#define PDB_SC_PRESCALER_SHIFT                   12
+#define PDB_SC_PRESCALER_WIDTH                   3
+#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK                        0x8000u
+#define PDB_SC_DMAEN_SHIFT                       15
+#define PDB_SC_DMAEN_WIDTH                       1
+#define PDB_SC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK                       0x10000u
+#define PDB_SC_SWTRIG_SHIFT                      16
+#define PDB_SC_SWTRIG_WIDTH                      1
+#define PDB_SC_SWTRIG(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK                       0x20000u
+#define PDB_SC_PDBEIE_SHIFT                      17
+#define PDB_SC_PDBEIE_WIDTH                      1
+#define PDB_SC_PDBEIE(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK                        0xC0000u
+#define PDB_SC_LDMOD_SHIFT                       18
+#define PDB_SC_LDMOD_WIDTH                       2
+#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK                         0xFFFFu
+#define PDB_MOD_MOD_SHIFT                        0
+#define PDB_MOD_MOD_WIDTH                        16
+#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK                         0xFFFFu
+#define PDB_CNT_CNT_SHIFT                        0
+#define PDB_CNT_CNT_WIDTH                        16
+#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK                       0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT                      0
+#define PDB_IDLY_IDLY_WIDTH                      16
+#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK                           0xFFu
+#define PDB_C1_EN_SHIFT                          0
+#define PDB_C1_EN_WIDTH                          8
+#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK                          0xFF00u
+#define PDB_C1_TOS_SHIFT                         8
+#define PDB_C1_TOS_WIDTH                         8
+#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK                           0xFF0000u
+#define PDB_C1_BB_SHIFT                          16
+#define PDB_C1_BB_WIDTH                          8
+#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK                           0xFFu
+#define PDB_S_ERR_SHIFT                          0
+#define PDB_S_ERR_WIDTH                          8
+#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK                            0xFF0000u
+#define PDB_S_CF_SHIFT                           16
+#define PDB_S_CF_WIDTH                           8
+#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK                         0xFFFFu
+#define PDB_DLY_DLY_SHIFT                        0
+#define PDB_DLY_DLY_WIDTH                        16
+#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* INTC Bit Fields */
+#define PDB_INTC_TOE_MASK                        0x1u
+#define PDB_INTC_TOE_SHIFT                       0
+#define PDB_INTC_TOE_WIDTH                       1
+#define PDB_INTC_TOE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_TOE_SHIFT))&PDB_INTC_TOE_MASK)
+#define PDB_INTC_EXT_MASK                        0x2u
+#define PDB_INTC_EXT_SHIFT                       1
+#define PDB_INTC_EXT_WIDTH                       1
+#define PDB_INTC_EXT(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_EXT_SHIFT))&PDB_INTC_EXT_MASK)
+/* INT Bit Fields */
+#define PDB_INT_INT_MASK                         0xFFFFu
+#define PDB_INT_INT_SHIFT                        0
+#define PDB_INT_INT_WIDTH                        16
+#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK                       0xFFu
+#define PDB_POEN_POEN_SHIFT                      0
+#define PDB_POEN_POEN_WIDTH                      8
+#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK                      0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT                     0
+#define PDB_PODLY_DLY2_WIDTH                     16
+#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK                      0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT                     16
+#define PDB_PODLY_DLY1_WIDTH                     16
+#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE                                (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0                                     ((PDB_Type *)PDB0_BASE)
+#define PDB0_BASE_PTR                            (PDB0)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS                           { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS                            { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS                                 { PDB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register instance definitions */
+/* PDB0 */
+#define PDB0_SC                                  PDB_SC_REG(PDB0)
+#define PDB0_MOD                                 PDB_MOD_REG(PDB0)
+#define PDB0_CNT                                 PDB_CNT_REG(PDB0)
+#define PDB0_IDLY                                PDB_IDLY_REG(PDB0)
+#define PDB0_CH0C1                               PDB_C1_REG(PDB0,0)
+#define PDB0_CH0S                                PDB_S_REG(PDB0,0)
+#define PDB0_CH0DLY0                             PDB_DLY_REG(PDB0,0,0)
+#define PDB0_CH0DLY1                             PDB_DLY_REG(PDB0,0,1)
+#define PDB0_CH1C1                               PDB_C1_REG(PDB0,1)
+#define PDB0_CH1S                                PDB_S_REG(PDB0,1)
+#define PDB0_CH1DLY0                             PDB_DLY_REG(PDB0,1,0)
+#define PDB0_CH1DLY1                             PDB_DLY_REG(PDB0,1,1)
+#define PDB0_DACINTC0                            PDB_INTC_REG(PDB0,0)
+#define PDB0_DACINT0                             PDB_INT_REG(PDB0,0)
+#define PDB0_DACINTC1                            PDB_INTC_REG(PDB0,1)
+#define PDB0_DACINT1                             PDB_INT_REG(PDB0,1)
+#define PDB0_POEN                                PDB_POEN_REG(PDB0)
+#define PDB0_PO0DLY                              PDB_PODLY_REG(PDB0,0)
+#define PDB0_PO1DLY                              PDB_PODLY_REG(PDB0,1)
+#define PDB0_PO2DLY                              PDB_PODLY_REG(PDB0,2)
+
+/* PDB - Register array accessors */
+#define PDB0_C1(index)                           PDB_C1_REG(PDB0,index)
+#define PDB0_S(index)                            PDB_S_REG(PDB0,index)
+#define PDB0_DLY(index,index2)                   PDB_DLY_REG(PDB0,index,index2)
+#define PDB0_INTC(index)                         PDB_INTC_REG(PDB0,index)
+#define PDB0_INT(index)                          PDB_INT_REG(PDB0,index)
+#define PDB0_PODLY(index)                        PDB_PODLY_REG(PDB0,index)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[252];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[4];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base)                        ((base)->MCR)
+#define PIT_LDVAL_REG(base,index)                ((base)->CHANNEL[index].LDVAL)
+#define PIT_LDVAL_COUNT                          4
+#define PIT_CVAL_REG(base,index)                 ((base)->CHANNEL[index].CVAL)
+#define PIT_CVAL_COUNT                           4
+#define PIT_TCTRL_REG(base,index)                ((base)->CHANNEL[index].TCTRL)
+#define PIT_TCTRL_COUNT                          4
+#define PIT_TFLG_REG(base,index)                 ((base)->CHANNEL[index].TFLG)
+#define PIT_TFLG_COUNT                           4
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK                         0x1u
+#define PIT_MCR_FRZ_SHIFT                        0
+#define PIT_MCR_FRZ_WIDTH                        1
+#define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK                        0x2u
+#define PIT_MCR_MDIS_SHIFT                       1
+#define PIT_MCR_MDIS_WIDTH                       1
+#define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT                      0
+#define PIT_LDVAL_TSV_WIDTH                      32
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT                       0
+#define PIT_CVAL_TVL_WIDTH                       32
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK                       0x1u
+#define PIT_TCTRL_TEN_SHIFT                      0
+#define PIT_TCTRL_TEN_WIDTH                      1
+#define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK                       0x2u
+#define PIT_TCTRL_TIE_SHIFT                      1
+#define PIT_TCTRL_TIE_WIDTH                      1
+#define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK                       0x4u
+#define PIT_TCTRL_CHN_SHIFT                      2
+#define PIT_TCTRL_CHN_WIDTH                      1
+#define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK                        0x1u
+#define PIT_TFLG_TIF_SHIFT                       0
+#define PIT_TFLG_TIF_WIDTH                       1
+#define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR                             (PIT)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS                           { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR                                  PIT_MCR_REG(PIT)
+#define PIT_LDVAL0                               PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0                                PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0                               PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0                                PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1                               PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1                                PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1                               PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1                                PIT_TFLG_REG(PIT,1)
+#define PIT_LDVAL2                               PIT_LDVAL_REG(PIT,2)
+#define PIT_CVAL2                                PIT_CVAL_REG(PIT,2)
+#define PIT_TCTRL2                               PIT_TCTRL_REG(PIT,2)
+#define PIT_TFLG2                                PIT_TFLG_REG(PIT,2)
+#define PIT_LDVAL3                               PIT_LDVAL_REG(PIT,3)
+#define PIT_CVAL3                                PIT_CVAL_REG(PIT,3)
+#define PIT_TCTRL3                               PIT_TCTRL_REG(PIT,3)
+#define PIT_TFLG3                                PIT_TFLG_REG(PIT,3)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index)                         PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index)                          PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index)                         PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index)                          PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base)                     ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base)                     ((base)->LVDSC2)
+#define PMC_REGSC_REG(base)                      ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK                     0x3u
+#define PMC_LVDSC1_LVDV_SHIFT                    0
+#define PMC_LVDSC1_LVDV_WIDTH                    2
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT                   4
+#define PMC_LVDSC1_LVDRE_WIDTH                   1
+#define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK                    0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT                   5
+#define PMC_LVDSC1_LVDIE_WIDTH                   1
+#define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK                   0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT                  6
+#define PMC_LVDSC1_LVDACK_WIDTH                  1
+#define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK                     0x80u
+#define PMC_LVDSC1_LVDF_SHIFT                    7
+#define PMC_LVDSC1_LVDF_WIDTH                    1
+#define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK                     0x3u
+#define PMC_LVDSC2_LVWV_SHIFT                    0
+#define PMC_LVDSC2_LVWV_WIDTH                    2
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT                   5
+#define PMC_LVDSC2_LVWIE_WIDTH                   1
+#define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK                   0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT                  6
+#define PMC_LVDSC2_LVWACK_WIDTH                  1
+#define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK                     0x80u
+#define PMC_LVDSC2_LVWF_SHIFT                    7
+#define PMC_LVDSC2_LVWF_WIDTH                    1
+#define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK                      0x1u
+#define PMC_REGSC_BGBE_SHIFT                     0
+#define PMC_REGSC_BGBE_WIDTH                     1
+#define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK                    0x4u
+#define PMC_REGSC_REGONS_SHIFT                   2
+#define PMC_REGSC_REGONS_WIDTH                   1
+#define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK                    0x8u
+#define PMC_REGSC_ACKISO_SHIFT                   3
+#define PMC_REGSC_ACKISO_WIDTH                   1
+#define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK                      0x10u
+#define PMC_REGSC_BGEN_SHIFT                     4
+#define PMC_REGSC_BGEN_WIDTH                     1
+#define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR                             (PMC)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS                           { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { LVD_LVW_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1                               PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2                               PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC                                PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
+  __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
+  __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index)                 ((base)->PCR[index])
+#define PORT_PCR_COUNT                           32
+#define PORT_GPCLR_REG(base)                     ((base)->GPCLR)
+#define PORT_GPCHR_REG(base)                     ((base)->GPCHR)
+#define PORT_ISFR_REG(base)                      ((base)->ISFR)
+#define PORT_DFER_REG(base)                      ((base)->DFER)
+#define PORT_DFCR_REG(base)                      ((base)->DFCR)
+#define PORT_DFWR_REG(base)                      ((base)->DFWR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK                         0x1u
+#define PORT_PCR_PS_SHIFT                        0
+#define PORT_PCR_PS_WIDTH                        1
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK                         0x2u
+#define PORT_PCR_PE_SHIFT                        1
+#define PORT_PCR_PE_WIDTH                        1
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK                        0x4u
+#define PORT_PCR_SRE_SHIFT                       2
+#define PORT_PCR_SRE_WIDTH                       1
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK                        0x10u
+#define PORT_PCR_PFE_SHIFT                       4
+#define PORT_PCR_PFE_WIDTH                       1
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK                        0x20u
+#define PORT_PCR_ODE_SHIFT                       5
+#define PORT_PCR_ODE_WIDTH                       1
+#define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK                        0x40u
+#define PORT_PCR_DSE_SHIFT                       6
+#define PORT_PCR_DSE_WIDTH                       1
+#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK                        0x700u
+#define PORT_PCR_MUX_SHIFT                       8
+#define PORT_PCR_MUX_WIDTH                       3
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK                         0x8000u
+#define PORT_PCR_LK_SHIFT                        15
+#define PORT_PCR_LK_WIDTH                        1
+#define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK                       0xF0000u
+#define PORT_PCR_IRQC_SHIFT                      16
+#define PORT_PCR_IRQC_WIDTH                      4
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        0x1000000u
+#define PORT_PCR_ISF_SHIFT                       24
+#define PORT_PCR_ISF_WIDTH                       1
+#define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT                    0
+#define PORT_GPCLR_GPWD_WIDTH                    16
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT                    16
+#define PORT_GPCLR_GPWE_WIDTH                    16
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT                    0
+#define PORT_GPCHR_GPWD_WIDTH                    16
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT                    16
+#define PORT_GPCHR_GPWE_WIDTH                    16
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT                      0
+#define PORT_ISFR_ISF_WIDTH                      32
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK                       0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT                      0
+#define PORT_DFER_DFE_WIDTH                      32
+#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK                        0x1u
+#define PORT_DFCR_CS_SHIFT                       0
+#define PORT_DFCR_CS_WIDTH                       1
+#define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK                      0x1Fu
+#define PORT_DFWR_FILT_SHIFT                     0
+#define PORT_DFWR_FILT_WIDTH                     5
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR                           (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR                           (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR                           (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR                           (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR                           (PORTE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0                               PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1                               PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2                               PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3                               PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4                               PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5                               PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6                               PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7                               PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8                               PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9                               PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10                              PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11                              PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12                              PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13                              PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14                              PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15                              PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16                              PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17                              PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18                              PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19                              PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20                              PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21                              PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22                              PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23                              PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24                              PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25                              PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26                              PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27                              PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28                              PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29                              PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30                              PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31                              PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR                              PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR                              PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR                               PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0                               PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1                               PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2                               PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3                               PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4                               PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5                               PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6                               PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7                               PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8                               PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9                               PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10                              PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11                              PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12                              PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13                              PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14                              PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15                              PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16                              PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17                              PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18                              PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19                              PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20                              PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21                              PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22                              PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23                              PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24                              PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25                              PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26                              PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27                              PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28                              PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29                              PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30                              PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31                              PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR                              PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR                              PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR                               PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0                               PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1                               PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2                               PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3                               PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4                               PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5                               PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6                               PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7                               PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8                               PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9                               PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10                              PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11                              PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12                              PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13                              PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14                              PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15                              PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16                              PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17                              PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18                              PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19                              PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20                              PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21                              PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22                              PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23                              PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24                              PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25                              PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26                              PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27                              PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28                              PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29                              PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30                              PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31                              PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR                              PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR                              PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR                               PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0                               PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1                               PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2                               PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3                               PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4                               PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5                               PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6                               PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7                               PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8                               PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9                               PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10                              PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11                              PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12                              PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13                              PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14                              PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15                              PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16                              PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17                              PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18                              PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19                              PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20                              PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21                              PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22                              PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23                              PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24                              PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25                              PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26                              PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27                              PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28                              PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29                              PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30                              PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31                              PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR                              PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR                              PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR                               PORT_ISFR_REG(PORTD)
+#define PORTD_DFER                               PORT_DFER_REG(PORTD)
+#define PORTD_DFCR                               PORT_DFCR_REG(PORTD)
+#define PORTD_DFWR                               PORT_DFWR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0                               PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1                               PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2                               PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3                               PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4                               PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5                               PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6                               PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7                               PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8                               PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9                               PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10                              PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11                              PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12                              PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13                              PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14                              PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15                              PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16                              PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17                              PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18                              PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19                              PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20                              PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21                              PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22                              PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23                              PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24                              PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25                              PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26                              PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27                              PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28                              PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29                              PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30                              PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31                              PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR                              PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR                              PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR                               PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index)                         PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index)                         PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index)                         PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index)                         PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index)                         PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+       uint8_t RESERVED_1[1];
+  __I  uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base)                       ((base)->SRS0)
+#define RCM_SRS1_REG(base)                       ((base)->SRS1)
+#define RCM_RPFC_REG(base)                       ((base)->RPFC)
+#define RCM_RPFW_REG(base)                       ((base)->RPFW)
+#define RCM_MR_REG(base)                         ((base)->MR)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK                     0x1u
+#define RCM_SRS0_WAKEUP_SHIFT                    0
+#define RCM_SRS0_WAKEUP_WIDTH                    1
+#define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK                        0x2u
+#define RCM_SRS0_LVD_SHIFT                       1
+#define RCM_SRS0_LVD_WIDTH                       1
+#define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK                        0x4u
+#define RCM_SRS0_LOC_SHIFT                       2
+#define RCM_SRS0_LOC_WIDTH                       1
+#define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOC_SHIFT))&RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK                        0x8u
+#define RCM_SRS0_LOL_SHIFT                       3
+#define RCM_SRS0_LOL_WIDTH                       1
+#define RCM_SRS0_LOL(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOL_SHIFT))&RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK                       0x20u
+#define RCM_SRS0_WDOG_SHIFT                      5
+#define RCM_SRS0_WDOG_WIDTH                      1
+#define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK                        0x40u
+#define RCM_SRS0_PIN_SHIFT                       6
+#define RCM_SRS0_PIN_WIDTH                       1
+#define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK                        0x80u
+#define RCM_SRS0_POR_SHIFT                       7
+#define RCM_SRS0_POR_WIDTH                       1
+#define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK                       0x1u
+#define RCM_SRS1_JTAG_SHIFT                      0
+#define RCM_SRS1_JTAG_WIDTH                      1
+#define RCM_SRS1_JTAG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_JTAG_SHIFT))&RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK                     0x2u
+#define RCM_SRS1_LOCKUP_SHIFT                    1
+#define RCM_SRS1_LOCKUP_WIDTH                    1
+#define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK                         0x4u
+#define RCM_SRS1_SW_SHIFT                        2
+#define RCM_SRS1_SW_WIDTH                        1
+#define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK                     0x8u
+#define RCM_SRS1_MDM_AP_SHIFT                    3
+#define RCM_SRS1_MDM_AP_WIDTH                    1
+#define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK                       0x10u
+#define RCM_SRS1_EZPT_SHIFT                      4
+#define RCM_SRS1_EZPT_WIDTH                      1
+#define RCM_SRS1_EZPT(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_EZPT_SHIFT))&RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK                    0x20u
+#define RCM_SRS1_SACKERR_SHIFT                   5
+#define RCM_SRS1_SACKERR_WIDTH                   1
+#define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 0
+#define RCM_RPFC_RSTFLTSRW_WIDTH                 2
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK                   0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT                  2
+#define RCM_RPFC_RSTFLTSS_WIDTH                  1
+#define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 0
+#define RCM_RPFW_RSTFLTSEL_WIDTH                 5
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK                       0x2u
+#define RCM_MR_EZP_MS_SHIFT                      1
+#define RCM_MR_EZP_MS_WIDTH                      1
+#define RCM_MR_EZP_MS(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_MR_EZP_MS_SHIFT))&RCM_MR_EZP_MS_MASK)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR                             (RCM)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS                           { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS                            { RCM }
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0                                 RCM_SRS0_REG(RCM)
+#define RCM_SRS1                                 RCM_SRS1_REG(RCM)
+#define RCM_RPFC                                 RCM_RPFC_REG(RCM)
+#define RCM_RPFW                                 RCM_RPFW_REG(RCM)
+#define RCM_MR                                   RCM_MR_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index)                ((base)->REG[index])
+#define RFSYS_REG_COUNT                          8
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK                        0xFFu
+#define RFSYS_REG_LL_SHIFT                       0
+#define RFSYS_REG_LL_WIDTH                       8
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        0xFF00u
+#define RFSYS_REG_LH_SHIFT                       8
+#define RFSYS_REG_LH_WIDTH                       8
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        0xFF0000u
+#define RFSYS_REG_HL_SHIFT                       16
+#define RFSYS_REG_HL_WIDTH                       8
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        0xFF000000u
+#define RFSYS_REG_HH_SHIFT                       24
+#define RFSYS_REG_HH_WIDTH                       8
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR                           (RFSYS)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS                          { RFSYS }
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0                               RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1                               RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2                               RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3                               RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4                               RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5                               RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6                               RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7                               RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index)                         RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type, *RFVBAT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register accessors */
+#define RFVBAT_REG_REG(base,index)               ((base)->REG[index])
+#define RFVBAT_REG_COUNT                         8
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK                       0xFFu
+#define RFVBAT_REG_LL_SHIFT                      0
+#define RFVBAT_REG_LL_WIDTH                      8
+#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK                       0xFF00u
+#define RFVBAT_REG_LH_SHIFT                      8
+#define RFVBAT_REG_LH_WIDTH                      8
+#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK                       0xFF0000u
+#define RFVBAT_REG_HL_SHIFT                      16
+#define RFVBAT_REG_HL_WIDTH                      8
+#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK                       0xFF000000u
+#define RFVBAT_REG_HH_SHIFT                      24
+#define RFVBAT_REG_HH_WIDTH                      8
+#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE                              (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
+#define RFVBAT_BASE_PTR                          (RFVBAT)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS                        { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS                         { RFVBAT }
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register instance definitions */
+/* RFVBAT */
+#define RFVBAT_REG0                              RFVBAT_REG_REG(RFVBAT,0)
+#define RFVBAT_REG1                              RFVBAT_REG_REG(RFVBAT,1)
+#define RFVBAT_REG2                              RFVBAT_REG_REG(RFVBAT,2)
+#define RFVBAT_REG3                              RFVBAT_REG_REG(RFVBAT,3)
+#define RFVBAT_REG4                              RFVBAT_REG_REG(RFVBAT,4)
+#define RFVBAT_REG5                              RFVBAT_REG_REG(RFVBAT,5)
+#define RFVBAT_REG6                              RFVBAT_REG_REG(RFVBAT,6)
+#define RFVBAT_REG7                              RFVBAT_REG_REG(RFVBAT,7)
+
+/* RFVBAT - Register array accessors */
+#define RFVBAT_REG(index)                        RFVBAT_REG_REG(RFVBAT,index)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< RNGA Control Register, offset: 0x0 */
+  __I  uint32_t SR;                                /**< RNGA Status Register, offset: 0x4 */
+  __O  uint32_t ER;                                /**< RNGA Entropy Register, offset: 0x8 */
+  __I  uint32_t OR;                                /**< RNGA Output Register, offset: 0xC */
+} RNG_Type, *RNG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register accessors */
+#define RNG_CR_REG(base)                         ((base)->CR)
+#define RNG_SR_REG(base)                         ((base)->SR)
+#define RNG_ER_REG(base)                         ((base)->ER)
+#define RNG_OR_REG(base)                         ((base)->OR)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define RNG_CR_GO_MASK                           0x1u
+#define RNG_CR_GO_SHIFT                          0
+#define RNG_CR_GO_WIDTH                          1
+#define RNG_CR_GO(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_GO_SHIFT))&RNG_CR_GO_MASK)
+#define RNG_CR_HA_MASK                           0x2u
+#define RNG_CR_HA_SHIFT                          1
+#define RNG_CR_HA_WIDTH                          1
+#define RNG_CR_HA(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_HA_SHIFT))&RNG_CR_HA_MASK)
+#define RNG_CR_INTM_MASK                         0x4u
+#define RNG_CR_INTM_SHIFT                        2
+#define RNG_CR_INTM_WIDTH                        1
+#define RNG_CR_INTM(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_INTM_SHIFT))&RNG_CR_INTM_MASK)
+#define RNG_CR_CLRI_MASK                         0x8u
+#define RNG_CR_CLRI_SHIFT                        3
+#define RNG_CR_CLRI_WIDTH                        1
+#define RNG_CR_CLRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_CLRI_SHIFT))&RNG_CR_CLRI_MASK)
+#define RNG_CR_SLP_MASK                          0x10u
+#define RNG_CR_SLP_SHIFT                         4
+#define RNG_CR_SLP_WIDTH                         1
+#define RNG_CR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_CR_SLP_SHIFT))&RNG_CR_SLP_MASK)
+/* SR Bit Fields */
+#define RNG_SR_SECV_MASK                         0x1u
+#define RNG_SR_SECV_SHIFT                        0
+#define RNG_SR_SECV_WIDTH                        1
+#define RNG_SR_SECV(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_SECV_SHIFT))&RNG_SR_SECV_MASK)
+#define RNG_SR_LRS_MASK                          0x2u
+#define RNG_SR_LRS_SHIFT                         1
+#define RNG_SR_LRS_WIDTH                         1
+#define RNG_SR_LRS(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_LRS_SHIFT))&RNG_SR_LRS_MASK)
+#define RNG_SR_ORU_MASK                          0x4u
+#define RNG_SR_ORU_SHIFT                         2
+#define RNG_SR_ORU_WIDTH                         1
+#define RNG_SR_ORU(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_ORU_SHIFT))&RNG_SR_ORU_MASK)
+#define RNG_SR_ERRI_MASK                         0x8u
+#define RNG_SR_ERRI_SHIFT                        3
+#define RNG_SR_ERRI_WIDTH                        1
+#define RNG_SR_ERRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_ERRI_SHIFT))&RNG_SR_ERRI_MASK)
+#define RNG_SR_SLP_MASK                          0x10u
+#define RNG_SR_SLP_SHIFT                         4
+#define RNG_SR_SLP_WIDTH                         1
+#define RNG_SR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_SLP_SHIFT))&RNG_SR_SLP_MASK)
+#define RNG_SR_OREG_LVL_MASK                     0xFF00u
+#define RNG_SR_OREG_LVL_SHIFT                    8
+#define RNG_SR_OREG_LVL_WIDTH                    8
+#define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK                    0xFF0000u
+#define RNG_SR_OREG_SIZE_SHIFT                   16
+#define RNG_SR_OREG_SIZE_WIDTH                   8
+#define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
+/* ER Bit Fields */
+#define RNG_ER_EXT_ENT_MASK                      0xFFFFFFFFu
+#define RNG_ER_EXT_ENT_SHIFT                     0
+#define RNG_ER_EXT_ENT_WIDTH                     32
+#define RNG_ER_EXT_ENT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
+/* OR Bit Fields */
+#define RNG_OR_RANDOUT_MASK                      0xFFFFFFFFu
+#define RNG_OR_RANDOUT_SHIFT                     0
+#define RNG_OR_RANDOUT_WIDTH                     32
+#define RNG_OR_RANDOUT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE                                 (0x40029000u)
+/** Peripheral RNG base pointer */
+#define RNG                                      ((RNG_Type *)RNG_BASE)
+#define RNG_BASE_PTR                             (RNG)
+/** Array initializer of RNG peripheral base addresses */
+#define RNG_BASE_ADDRS                           { RNG_BASE }
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASE_PTRS                            { RNG }
+/** Interrupt vectors for the RNG peripheral type */
+#define RNG_IRQS                                 { RNG_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register instance definitions */
+/* RNG */
+#define RNG_CR                                   RNG_CR_REG(RNG)
+#define RNG_SR                                   RNG_SR_REG(RNG)
+#define RNG_ER                                   RNG_ER_REG(RNG)
+#define RNG_OR                                   RNG_OR_REG(RNG)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+       uint8_t RESERVED_0[2016];
+  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base)                        ((base)->TSR)
+#define RTC_TPR_REG(base)                        ((base)->TPR)
+#define RTC_TAR_REG(base)                        ((base)->TAR)
+#define RTC_TCR_REG(base)                        ((base)->TCR)
+#define RTC_CR_REG(base)                         ((base)->CR)
+#define RTC_SR_REG(base)                         ((base)->SR)
+#define RTC_LR_REG(base)                         ((base)->LR)
+#define RTC_IER_REG(base)                        ((base)->IER)
+#define RTC_WAR_REG(base)                        ((base)->WAR)
+#define RTC_RAR_REG(base)                        ((base)->RAR)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT                        0
+#define RTC_TSR_TSR_WIDTH                        32
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK                         0xFFFFu
+#define RTC_TPR_TPR_SHIFT                        0
+#define RTC_TPR_TPR_WIDTH                        16
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT                        0
+#define RTC_TAR_TAR_WIDTH                        32
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK                         0xFFu
+#define RTC_TCR_TCR_SHIFT                        0
+#define RTC_TCR_TCR_WIDTH                        8
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         0xFF00u
+#define RTC_TCR_CIR_SHIFT                        8
+#define RTC_TCR_CIR_WIDTH                        8
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         0xFF0000u
+#define RTC_TCR_TCV_SHIFT                        16
+#define RTC_TCR_TCV_WIDTH                        8
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         0xFF000000u
+#define RTC_TCR_CIC_SHIFT                        24
+#define RTC_TCR_CIC_WIDTH                        8
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK                          0x1u
+#define RTC_CR_SWR_SHIFT                         0
+#define RTC_CR_SWR_WIDTH                         1
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK                          0x2u
+#define RTC_CR_WPE_SHIFT                         1
+#define RTC_CR_WPE_WIDTH                         1
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK                          0x4u
+#define RTC_CR_SUP_SHIFT                         2
+#define RTC_CR_SUP_WIDTH                         1
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK                           0x8u
+#define RTC_CR_UM_SHIFT                          3
+#define RTC_CR_UM_WIDTH                          1
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK                          0x10u
+#define RTC_CR_WPS_SHIFT                         4
+#define RTC_CR_WPS_WIDTH                         1
+#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK                         0x100u
+#define RTC_CR_OSCE_SHIFT                        8
+#define RTC_CR_OSCE_WIDTH                        1
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK                         0x200u
+#define RTC_CR_CLKO_SHIFT                        9
+#define RTC_CR_CLKO_WIDTH                        1
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK                        0x400u
+#define RTC_CR_SC16P_SHIFT                       10
+#define RTC_CR_SC16P_WIDTH                       1
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK                         0x800u
+#define RTC_CR_SC8P_SHIFT                        11
+#define RTC_CR_SC8P_WIDTH                        1
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK                         0x1000u
+#define RTC_CR_SC4P_SHIFT                        12
+#define RTC_CR_SC4P_WIDTH                        1
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK                         0x2000u
+#define RTC_CR_SC2P_SHIFT                        13
+#define RTC_CR_SC2P_WIDTH                        1
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK                          0x1u
+#define RTC_SR_TIF_SHIFT                         0
+#define RTC_SR_TIF_WIDTH                         1
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK                          0x2u
+#define RTC_SR_TOF_SHIFT                         1
+#define RTC_SR_TOF_WIDTH                         1
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK                          0x4u
+#define RTC_SR_TAF_SHIFT                         2
+#define RTC_SR_TAF_WIDTH                         1
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK                          0x10u
+#define RTC_SR_TCE_SHIFT                         4
+#define RTC_SR_TCE_WIDTH                         1
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK                          0x8u
+#define RTC_LR_TCL_SHIFT                         3
+#define RTC_LR_TCL_WIDTH                         1
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK                          0x10u
+#define RTC_LR_CRL_SHIFT                         4
+#define RTC_LR_CRL_WIDTH                         1
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK                          0x20u
+#define RTC_LR_SRL_SHIFT                         5
+#define RTC_LR_SRL_WIDTH                         1
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK                          0x40u
+#define RTC_LR_LRL_SHIFT                         6
+#define RTC_LR_LRL_WIDTH                         1
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK                        0x1u
+#define RTC_IER_TIIE_SHIFT                       0
+#define RTC_IER_TIIE_WIDTH                       1
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK                        0x2u
+#define RTC_IER_TOIE_SHIFT                       1
+#define RTC_IER_TOIE_WIDTH                       1
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK                        0x4u
+#define RTC_IER_TAIE_SHIFT                       2
+#define RTC_IER_TAIE_WIDTH                       1
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK                        0x10u
+#define RTC_IER_TSIE_SHIFT                       4
+#define RTC_IER_TSIE_WIDTH                       1
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK                        0x80u
+#define RTC_IER_WPON_SHIFT                       7
+#define RTC_IER_WPON_WIDTH                       1
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK                        0x1u
+#define RTC_WAR_TSRW_SHIFT                       0
+#define RTC_WAR_TSRW_WIDTH                       1
+#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TSRW_SHIFT))&RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK                        0x2u
+#define RTC_WAR_TPRW_SHIFT                       1
+#define RTC_WAR_TPRW_WIDTH                       1
+#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TPRW_SHIFT))&RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK                        0x4u
+#define RTC_WAR_TARW_SHIFT                       2
+#define RTC_WAR_TARW_WIDTH                       1
+#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TARW_SHIFT))&RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK                        0x8u
+#define RTC_WAR_TCRW_SHIFT                       3
+#define RTC_WAR_TCRW_WIDTH                       1
+#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TCRW_SHIFT))&RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK                         0x10u
+#define RTC_WAR_CRW_SHIFT                        4
+#define RTC_WAR_CRW_WIDTH                        1
+#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_CRW_SHIFT))&RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK                         0x20u
+#define RTC_WAR_SRW_SHIFT                        5
+#define RTC_WAR_SRW_WIDTH                        1
+#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_SRW_SHIFT))&RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK                         0x40u
+#define RTC_WAR_LRW_SHIFT                        6
+#define RTC_WAR_LRW_WIDTH                        1
+#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_LRW_SHIFT))&RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK                        0x80u
+#define RTC_WAR_IERW_SHIFT                       7
+#define RTC_WAR_IERW_WIDTH                       1
+#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_IERW_SHIFT))&RTC_WAR_IERW_MASK)
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK                        0x1u
+#define RTC_RAR_TSRR_SHIFT                       0
+#define RTC_RAR_TSRR_WIDTH                       1
+#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TSRR_SHIFT))&RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK                        0x2u
+#define RTC_RAR_TPRR_SHIFT                       1
+#define RTC_RAR_TPRR_WIDTH                       1
+#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TPRR_SHIFT))&RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK                        0x4u
+#define RTC_RAR_TARR_SHIFT                       2
+#define RTC_RAR_TARR_WIDTH                       1
+#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TARR_SHIFT))&RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK                        0x8u
+#define RTC_RAR_TCRR_SHIFT                       3
+#define RTC_RAR_TCRR_WIDTH                       1
+#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TCRR_SHIFT))&RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK                         0x10u
+#define RTC_RAR_CRR_SHIFT                        4
+#define RTC_RAR_CRR_WIDTH                        1
+#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_CRR_SHIFT))&RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK                         0x20u
+#define RTC_RAR_SRR_SHIFT                        5
+#define RTC_RAR_SRR_WIDTH                        1
+#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_SRR_SHIFT))&RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK                         0x40u
+#define RTC_RAR_LRR_SHIFT                        6
+#define RTC_RAR_LRR_WIDTH                        1
+#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_LRR_SHIFT))&RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK                        0x80u
+#define RTC_RAR_IERR_SHIFT                       7
+#define RTC_RAR_IERR_WIDTH                       1
+#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_IERR_SHIFT))&RTC_RAR_IERR_MASK)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR                             (RTC)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR                                  RTC_TSR_REG(RTC)
+#define RTC_TPR                                  RTC_TPR_REG(RTC)
+#define RTC_TAR                                  RTC_TAR_REG(RTC)
+#define RTC_TCR                                  RTC_TCR_REG(RTC)
+#define RTC_CR                                   RTC_CR_REG(RTC)
+#define RTC_SR                                   RTC_SR_REG(RTC)
+#define RTC_LR                                   RTC_LR_REG(RTC)
+#define RTC_IER                                  RTC_IER_REG(RTC)
+#define RTC_WAR                                  RTC_WAR_REG(RTC)
+#define RTC_RAR                                  RTC_RAR_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
+ * @{
+ */
+
+/** SDHC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DSADDR;                            /**< DMA System Address register, offset: 0x0 */
+  __IO uint32_t BLKATTR;                           /**< Block Attributes register, offset: 0x4 */
+  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x8 */
+  __IO uint32_t XFERTYP;                           /**< Transfer Type register, offset: 0xC */
+  __I  uint32_t CMDRSP[4];                         /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t DATPORT;                           /**< Buffer Data Port register, offset: 0x20 */
+  __I  uint32_t PRSSTAT;                           /**< Present State register, offset: 0x24 */
+  __IO uint32_t PROCTL;                            /**< Protocol Control register, offset: 0x28 */
+  __IO uint32_t SYSCTL;                            /**< System Control register, offset: 0x2C */
+  __IO uint32_t IRQSTAT;                           /**< Interrupt Status register, offset: 0x30 */
+  __IO uint32_t IRQSTATEN;                         /**< Interrupt Status Enable register, offset: 0x34 */
+  __IO uint32_t IRQSIGEN;                          /**< Interrupt Signal Enable register, offset: 0x38 */
+  __I  uint32_t AC12ERR;                           /**< Auto CMD12 Error Status Register, offset: 0x3C */
+  __I  uint32_t HTCAPBLT;                          /**< Host Controller Capabilities, offset: 0x40 */
+  __IO uint32_t WML;                               /**< Watermark Level Register, offset: 0x44 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t FEVT;                              /**< Force Event register, offset: 0x50 */
+  __I  uint32_t ADMAES;                            /**< ADMA Error Status register, offset: 0x54 */
+  __IO uint32_t ADSADDR;                           /**< ADMA System Addressregister, offset: 0x58 */
+       uint8_t RESERVED_1[100];
+  __IO uint32_t VENDOR;                            /**< Vendor Specific register, offset: 0xC0 */
+  __IO uint32_t MMCBOOT;                           /**< MMC Boot register, offset: 0xC4 */
+       uint8_t RESERVED_2[52];
+  __I  uint32_t HOSTVER;                           /**< Host Controller Version, offset: 0xFC */
+} SDHC_Type, *SDHC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register accessors */
+#define SDHC_DSADDR_REG(base)                    ((base)->DSADDR)
+#define SDHC_BLKATTR_REG(base)                   ((base)->BLKATTR)
+#define SDHC_CMDARG_REG(base)                    ((base)->CMDARG)
+#define SDHC_XFERTYP_REG(base)                   ((base)->XFERTYP)
+#define SDHC_CMDRSP_REG(base,index)              ((base)->CMDRSP[index])
+#define SDHC_CMDRSP_COUNT                        4
+#define SDHC_DATPORT_REG(base)                   ((base)->DATPORT)
+#define SDHC_PRSSTAT_REG(base)                   ((base)->PRSSTAT)
+#define SDHC_PROCTL_REG(base)                    ((base)->PROCTL)
+#define SDHC_SYSCTL_REG(base)                    ((base)->SYSCTL)
+#define SDHC_IRQSTAT_REG(base)                   ((base)->IRQSTAT)
+#define SDHC_IRQSTATEN_REG(base)                 ((base)->IRQSTATEN)
+#define SDHC_IRQSIGEN_REG(base)                  ((base)->IRQSIGEN)
+#define SDHC_AC12ERR_REG(base)                   ((base)->AC12ERR)
+#define SDHC_HTCAPBLT_REG(base)                  ((base)->HTCAPBLT)
+#define SDHC_WML_REG(base)                       ((base)->WML)
+#define SDHC_FEVT_REG(base)                      ((base)->FEVT)
+#define SDHC_ADMAES_REG(base)                    ((base)->ADMAES)
+#define SDHC_ADSADDR_REG(base)                   ((base)->ADSADDR)
+#define SDHC_VENDOR_REG(base)                    ((base)->VENDOR)
+#define SDHC_MMCBOOT_REG(base)                   ((base)->MMCBOOT)
+#define SDHC_HOSTVER_REG(base)                   ((base)->HOSTVER)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/* DSADDR Bit Fields */
+#define SDHC_DSADDR_DSADDR_MASK                  0xFFFFFFFCu
+#define SDHC_DSADDR_DSADDR_SHIFT                 2
+#define SDHC_DSADDR_DSADDR_WIDTH                 30
+#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
+/* BLKATTR Bit Fields */
+#define SDHC_BLKATTR_BLKSIZE_MASK                0x1FFFu
+#define SDHC_BLKATTR_BLKSIZE_SHIFT               0
+#define SDHC_BLKATTR_BLKSIZE_WIDTH               13
+#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK                 0xFFFF0000u
+#define SDHC_BLKATTR_BLKCNT_SHIFT                16
+#define SDHC_BLKATTR_BLKCNT_WIDTH                16
+#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
+/* CMDARG Bit Fields */
+#define SDHC_CMDARG_CMDARG_MASK                  0xFFFFFFFFu
+#define SDHC_CMDARG_CMDARG_SHIFT                 0
+#define SDHC_CMDARG_CMDARG_WIDTH                 32
+#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
+/* XFERTYP Bit Fields */
+#define SDHC_XFERTYP_DMAEN_MASK                  0x1u
+#define SDHC_XFERTYP_DMAEN_SHIFT                 0
+#define SDHC_XFERTYP_DMAEN_WIDTH                 1
+#define SDHC_XFERTYP_DMAEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DMAEN_SHIFT))&SDHC_XFERTYP_DMAEN_MASK)
+#define SDHC_XFERTYP_BCEN_MASK                   0x2u
+#define SDHC_XFERTYP_BCEN_SHIFT                  1
+#define SDHC_XFERTYP_BCEN_WIDTH                  1
+#define SDHC_XFERTYP_BCEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_BCEN_SHIFT))&SDHC_XFERTYP_BCEN_MASK)
+#define SDHC_XFERTYP_AC12EN_MASK                 0x4u
+#define SDHC_XFERTYP_AC12EN_SHIFT                2
+#define SDHC_XFERTYP_AC12EN_WIDTH                1
+#define SDHC_XFERTYP_AC12EN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_AC12EN_SHIFT))&SDHC_XFERTYP_AC12EN_MASK)
+#define SDHC_XFERTYP_DTDSEL_MASK                 0x10u
+#define SDHC_XFERTYP_DTDSEL_SHIFT                4
+#define SDHC_XFERTYP_DTDSEL_WIDTH                1
+#define SDHC_XFERTYP_DTDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DTDSEL_SHIFT))&SDHC_XFERTYP_DTDSEL_MASK)
+#define SDHC_XFERTYP_MSBSEL_MASK                 0x20u
+#define SDHC_XFERTYP_MSBSEL_SHIFT                5
+#define SDHC_XFERTYP_MSBSEL_WIDTH                1
+#define SDHC_XFERTYP_MSBSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_MSBSEL_SHIFT))&SDHC_XFERTYP_MSBSEL_MASK)
+#define SDHC_XFERTYP_RSPTYP_MASK                 0x30000u
+#define SDHC_XFERTYP_RSPTYP_SHIFT                16
+#define SDHC_XFERTYP_RSPTYP_WIDTH                2
+#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK                  0x80000u
+#define SDHC_XFERTYP_CCCEN_SHIFT                 19
+#define SDHC_XFERTYP_CCCEN_WIDTH                 1
+#define SDHC_XFERTYP_CCCEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CCCEN_SHIFT))&SDHC_XFERTYP_CCCEN_MASK)
+#define SDHC_XFERTYP_CICEN_MASK                  0x100000u
+#define SDHC_XFERTYP_CICEN_SHIFT                 20
+#define SDHC_XFERTYP_CICEN_WIDTH                 1
+#define SDHC_XFERTYP_CICEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CICEN_SHIFT))&SDHC_XFERTYP_CICEN_MASK)
+#define SDHC_XFERTYP_DPSEL_MASK                  0x200000u
+#define SDHC_XFERTYP_DPSEL_SHIFT                 21
+#define SDHC_XFERTYP_DPSEL_WIDTH                 1
+#define SDHC_XFERTYP_DPSEL(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DPSEL_SHIFT))&SDHC_XFERTYP_DPSEL_MASK)
+#define SDHC_XFERTYP_CMDTYP_MASK                 0xC00000u
+#define SDHC_XFERTYP_CMDTYP_SHIFT                22
+#define SDHC_XFERTYP_CMDTYP_WIDTH                2
+#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK                 0x3F000000u
+#define SDHC_XFERTYP_CMDINX_SHIFT                24
+#define SDHC_XFERTYP_CMDINX_WIDTH                6
+#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
+/* CMDRSP Bit Fields */
+#define SDHC_CMDRSP_CMDRSP0_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP0_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP0_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP1_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP1_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP2_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP2_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP3_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP3_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
+/* DATPORT Bit Fields */
+#define SDHC_DATPORT_DATCONT_MASK                0xFFFFFFFFu
+#define SDHC_DATPORT_DATCONT_SHIFT               0
+#define SDHC_DATPORT_DATCONT_WIDTH               32
+#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
+/* PRSSTAT Bit Fields */
+#define SDHC_PRSSTAT_CIHB_MASK                   0x1u
+#define SDHC_PRSSTAT_CIHB_SHIFT                  0
+#define SDHC_PRSSTAT_CIHB_WIDTH                  1
+#define SDHC_PRSSTAT_CIHB(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CIHB_SHIFT))&SDHC_PRSSTAT_CIHB_MASK)
+#define SDHC_PRSSTAT_CDIHB_MASK                  0x2u
+#define SDHC_PRSSTAT_CDIHB_SHIFT                 1
+#define SDHC_PRSSTAT_CDIHB_WIDTH                 1
+#define SDHC_PRSSTAT_CDIHB(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CDIHB_SHIFT))&SDHC_PRSSTAT_CDIHB_MASK)
+#define SDHC_PRSSTAT_DLA_MASK                    0x4u
+#define SDHC_PRSSTAT_DLA_SHIFT                   2
+#define SDHC_PRSSTAT_DLA_WIDTH                   1
+#define SDHC_PRSSTAT_DLA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLA_SHIFT))&SDHC_PRSSTAT_DLA_MASK)
+#define SDHC_PRSSTAT_SDSTB_MASK                  0x8u
+#define SDHC_PRSSTAT_SDSTB_SHIFT                 3
+#define SDHC_PRSSTAT_SDSTB_WIDTH                 1
+#define SDHC_PRSSTAT_SDSTB(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDSTB_SHIFT))&SDHC_PRSSTAT_SDSTB_MASK)
+#define SDHC_PRSSTAT_IPGOFF_MASK                 0x10u
+#define SDHC_PRSSTAT_IPGOFF_SHIFT                4
+#define SDHC_PRSSTAT_IPGOFF_WIDTH                1
+#define SDHC_PRSSTAT_IPGOFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_IPGOFF_SHIFT))&SDHC_PRSSTAT_IPGOFF_MASK)
+#define SDHC_PRSSTAT_HCKOFF_MASK                 0x20u
+#define SDHC_PRSSTAT_HCKOFF_SHIFT                5
+#define SDHC_PRSSTAT_HCKOFF_WIDTH                1
+#define SDHC_PRSSTAT_HCKOFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_HCKOFF_SHIFT))&SDHC_PRSSTAT_HCKOFF_MASK)
+#define SDHC_PRSSTAT_PEROFF_MASK                 0x40u
+#define SDHC_PRSSTAT_PEROFF_SHIFT                6
+#define SDHC_PRSSTAT_PEROFF_WIDTH                1
+#define SDHC_PRSSTAT_PEROFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_PEROFF_SHIFT))&SDHC_PRSSTAT_PEROFF_MASK)
+#define SDHC_PRSSTAT_SDOFF_MASK                  0x80u
+#define SDHC_PRSSTAT_SDOFF_SHIFT                 7
+#define SDHC_PRSSTAT_SDOFF_WIDTH                 1
+#define SDHC_PRSSTAT_SDOFF(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDOFF_SHIFT))&SDHC_PRSSTAT_SDOFF_MASK)
+#define SDHC_PRSSTAT_WTA_MASK                    0x100u
+#define SDHC_PRSSTAT_WTA_SHIFT                   8
+#define SDHC_PRSSTAT_WTA_WIDTH                   1
+#define SDHC_PRSSTAT_WTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_WTA_SHIFT))&SDHC_PRSSTAT_WTA_MASK)
+#define SDHC_PRSSTAT_RTA_MASK                    0x200u
+#define SDHC_PRSSTAT_RTA_SHIFT                   9
+#define SDHC_PRSSTAT_RTA_WIDTH                   1
+#define SDHC_PRSSTAT_RTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_RTA_SHIFT))&SDHC_PRSSTAT_RTA_MASK)
+#define SDHC_PRSSTAT_BWEN_MASK                   0x400u
+#define SDHC_PRSSTAT_BWEN_SHIFT                  10
+#define SDHC_PRSSTAT_BWEN_WIDTH                  1
+#define SDHC_PRSSTAT_BWEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BWEN_SHIFT))&SDHC_PRSSTAT_BWEN_MASK)
+#define SDHC_PRSSTAT_BREN_MASK                   0x800u
+#define SDHC_PRSSTAT_BREN_SHIFT                  11
+#define SDHC_PRSSTAT_BREN_WIDTH                  1
+#define SDHC_PRSSTAT_BREN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BREN_SHIFT))&SDHC_PRSSTAT_BREN_MASK)
+#define SDHC_PRSSTAT_CINS_MASK                   0x10000u
+#define SDHC_PRSSTAT_CINS_SHIFT                  16
+#define SDHC_PRSSTAT_CINS_WIDTH                  1
+#define SDHC_PRSSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CINS_SHIFT))&SDHC_PRSSTAT_CINS_MASK)
+#define SDHC_PRSSTAT_CLSL_MASK                   0x800000u
+#define SDHC_PRSSTAT_CLSL_SHIFT                  23
+#define SDHC_PRSSTAT_CLSL_WIDTH                  1
+#define SDHC_PRSSTAT_CLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CLSL_SHIFT))&SDHC_PRSSTAT_CLSL_MASK)
+#define SDHC_PRSSTAT_DLSL_MASK                   0xFF000000u
+#define SDHC_PRSSTAT_DLSL_SHIFT                  24
+#define SDHC_PRSSTAT_DLSL_WIDTH                  8
+#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
+/* PROCTL Bit Fields */
+#define SDHC_PROCTL_LCTL_MASK                    0x1u
+#define SDHC_PROCTL_LCTL_SHIFT                   0
+#define SDHC_PROCTL_LCTL_WIDTH                   1
+#define SDHC_PROCTL_LCTL(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_LCTL_SHIFT))&SDHC_PROCTL_LCTL_MASK)
+#define SDHC_PROCTL_DTW_MASK                     0x6u
+#define SDHC_PROCTL_DTW_SHIFT                    1
+#define SDHC_PROCTL_DTW_WIDTH                    2
+#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK                    0x8u
+#define SDHC_PROCTL_D3CD_SHIFT                   3
+#define SDHC_PROCTL_D3CD_WIDTH                   1
+#define SDHC_PROCTL_D3CD(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_D3CD_SHIFT))&SDHC_PROCTL_D3CD_MASK)
+#define SDHC_PROCTL_EMODE_MASK                   0x30u
+#define SDHC_PROCTL_EMODE_SHIFT                  4
+#define SDHC_PROCTL_EMODE_WIDTH                  2
+#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK                    0x40u
+#define SDHC_PROCTL_CDTL_SHIFT                   6
+#define SDHC_PROCTL_CDTL_WIDTH                   1
+#define SDHC_PROCTL_CDTL(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDTL_SHIFT))&SDHC_PROCTL_CDTL_MASK)
+#define SDHC_PROCTL_CDSS_MASK                    0x80u
+#define SDHC_PROCTL_CDSS_SHIFT                   7
+#define SDHC_PROCTL_CDSS_WIDTH                   1
+#define SDHC_PROCTL_CDSS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDSS_SHIFT))&SDHC_PROCTL_CDSS_MASK)
+#define SDHC_PROCTL_DMAS_MASK                    0x300u
+#define SDHC_PROCTL_DMAS_SHIFT                   8
+#define SDHC_PROCTL_DMAS_WIDTH                   2
+#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK                 0x10000u
+#define SDHC_PROCTL_SABGREQ_SHIFT                16
+#define SDHC_PROCTL_SABGREQ_WIDTH                1
+#define SDHC_PROCTL_SABGREQ(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_SABGREQ_SHIFT))&SDHC_PROCTL_SABGREQ_MASK)
+#define SDHC_PROCTL_CREQ_MASK                    0x20000u
+#define SDHC_PROCTL_CREQ_SHIFT                   17
+#define SDHC_PROCTL_CREQ_WIDTH                   1
+#define SDHC_PROCTL_CREQ(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CREQ_SHIFT))&SDHC_PROCTL_CREQ_MASK)
+#define SDHC_PROCTL_RWCTL_MASK                   0x40000u
+#define SDHC_PROCTL_RWCTL_SHIFT                  18
+#define SDHC_PROCTL_RWCTL_WIDTH                  1
+#define SDHC_PROCTL_RWCTL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_RWCTL_SHIFT))&SDHC_PROCTL_RWCTL_MASK)
+#define SDHC_PROCTL_IABG_MASK                    0x80000u
+#define SDHC_PROCTL_IABG_SHIFT                   19
+#define SDHC_PROCTL_IABG_WIDTH                   1
+#define SDHC_PROCTL_IABG(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_IABG_SHIFT))&SDHC_PROCTL_IABG_MASK)
+#define SDHC_PROCTL_WECINT_MASK                  0x1000000u
+#define SDHC_PROCTL_WECINT_SHIFT                 24
+#define SDHC_PROCTL_WECINT_WIDTH                 1
+#define SDHC_PROCTL_WECINT(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINT_SHIFT))&SDHC_PROCTL_WECINT_MASK)
+#define SDHC_PROCTL_WECINS_MASK                  0x2000000u
+#define SDHC_PROCTL_WECINS_SHIFT                 25
+#define SDHC_PROCTL_WECINS_WIDTH                 1
+#define SDHC_PROCTL_WECINS(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINS_SHIFT))&SDHC_PROCTL_WECINS_MASK)
+#define SDHC_PROCTL_WECRM_MASK                   0x4000000u
+#define SDHC_PROCTL_WECRM_SHIFT                  26
+#define SDHC_PROCTL_WECRM_WIDTH                  1
+#define SDHC_PROCTL_WECRM(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECRM_SHIFT))&SDHC_PROCTL_WECRM_MASK)
+/* SYSCTL Bit Fields */
+#define SDHC_SYSCTL_IPGEN_MASK                   0x1u
+#define SDHC_SYSCTL_IPGEN_SHIFT                  0
+#define SDHC_SYSCTL_IPGEN_WIDTH                  1
+#define SDHC_SYSCTL_IPGEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_IPGEN_SHIFT))&SDHC_SYSCTL_IPGEN_MASK)
+#define SDHC_SYSCTL_HCKEN_MASK                   0x2u
+#define SDHC_SYSCTL_HCKEN_SHIFT                  1
+#define SDHC_SYSCTL_HCKEN_WIDTH                  1
+#define SDHC_SYSCTL_HCKEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_HCKEN_SHIFT))&SDHC_SYSCTL_HCKEN_MASK)
+#define SDHC_SYSCTL_PEREN_MASK                   0x4u
+#define SDHC_SYSCTL_PEREN_SHIFT                  2
+#define SDHC_SYSCTL_PEREN_WIDTH                  1
+#define SDHC_SYSCTL_PEREN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_PEREN_SHIFT))&SDHC_SYSCTL_PEREN_MASK)
+#define SDHC_SYSCTL_SDCLKEN_MASK                 0x8u
+#define SDHC_SYSCTL_SDCLKEN_SHIFT                3
+#define SDHC_SYSCTL_SDCLKEN_WIDTH                1
+#define SDHC_SYSCTL_SDCLKEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKEN_SHIFT))&SDHC_SYSCTL_SDCLKEN_MASK)
+#define SDHC_SYSCTL_DVS_MASK                     0xF0u
+#define SDHC_SYSCTL_DVS_SHIFT                    4
+#define SDHC_SYSCTL_DVS_WIDTH                    4
+#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK                 0xFF00u
+#define SDHC_SYSCTL_SDCLKFS_SHIFT                8
+#define SDHC_SYSCTL_SDCLKFS_WIDTH                8
+#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK                   0xF0000u
+#define SDHC_SYSCTL_DTOCV_SHIFT                  16
+#define SDHC_SYSCTL_DTOCV_WIDTH                  4
+#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK                    0x1000000u
+#define SDHC_SYSCTL_RSTA_SHIFT                   24
+#define SDHC_SYSCTL_RSTA_WIDTH                   1
+#define SDHC_SYSCTL_RSTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTA_SHIFT))&SDHC_SYSCTL_RSTA_MASK)
+#define SDHC_SYSCTL_RSTC_MASK                    0x2000000u
+#define SDHC_SYSCTL_RSTC_SHIFT                   25
+#define SDHC_SYSCTL_RSTC_WIDTH                   1
+#define SDHC_SYSCTL_RSTC(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTC_SHIFT))&SDHC_SYSCTL_RSTC_MASK)
+#define SDHC_SYSCTL_RSTD_MASK                    0x4000000u
+#define SDHC_SYSCTL_RSTD_SHIFT                   26
+#define SDHC_SYSCTL_RSTD_WIDTH                   1
+#define SDHC_SYSCTL_RSTD(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTD_SHIFT))&SDHC_SYSCTL_RSTD_MASK)
+#define SDHC_SYSCTL_INITA_MASK                   0x8000000u
+#define SDHC_SYSCTL_INITA_SHIFT                  27
+#define SDHC_SYSCTL_INITA_WIDTH                  1
+#define SDHC_SYSCTL_INITA(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_INITA_SHIFT))&SDHC_SYSCTL_INITA_MASK)
+/* IRQSTAT Bit Fields */
+#define SDHC_IRQSTAT_CC_MASK                     0x1u
+#define SDHC_IRQSTAT_CC_SHIFT                    0
+#define SDHC_IRQSTAT_CC_WIDTH                    1
+#define SDHC_IRQSTAT_CC(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CC_SHIFT))&SDHC_IRQSTAT_CC_MASK)
+#define SDHC_IRQSTAT_TC_MASK                     0x2u
+#define SDHC_IRQSTAT_TC_SHIFT                    1
+#define SDHC_IRQSTAT_TC_WIDTH                    1
+#define SDHC_IRQSTAT_TC(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_TC_SHIFT))&SDHC_IRQSTAT_TC_MASK)
+#define SDHC_IRQSTAT_BGE_MASK                    0x4u
+#define SDHC_IRQSTAT_BGE_SHIFT                   2
+#define SDHC_IRQSTAT_BGE_WIDTH                   1
+#define SDHC_IRQSTAT_BGE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BGE_SHIFT))&SDHC_IRQSTAT_BGE_MASK)
+#define SDHC_IRQSTAT_DINT_MASK                   0x8u
+#define SDHC_IRQSTAT_DINT_SHIFT                  3
+#define SDHC_IRQSTAT_DINT_WIDTH                  1
+#define SDHC_IRQSTAT_DINT(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DINT_SHIFT))&SDHC_IRQSTAT_DINT_MASK)
+#define SDHC_IRQSTAT_BWR_MASK                    0x10u
+#define SDHC_IRQSTAT_BWR_SHIFT                   4
+#define SDHC_IRQSTAT_BWR_WIDTH                   1
+#define SDHC_IRQSTAT_BWR(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BWR_SHIFT))&SDHC_IRQSTAT_BWR_MASK)
+#define SDHC_IRQSTAT_BRR_MASK                    0x20u
+#define SDHC_IRQSTAT_BRR_SHIFT                   5
+#define SDHC_IRQSTAT_BRR_WIDTH                   1
+#define SDHC_IRQSTAT_BRR(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BRR_SHIFT))&SDHC_IRQSTAT_BRR_MASK)
+#define SDHC_IRQSTAT_CINS_MASK                   0x40u
+#define SDHC_IRQSTAT_CINS_SHIFT                  6
+#define SDHC_IRQSTAT_CINS_WIDTH                  1
+#define SDHC_IRQSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINS_SHIFT))&SDHC_IRQSTAT_CINS_MASK)
+#define SDHC_IRQSTAT_CRM_MASK                    0x80u
+#define SDHC_IRQSTAT_CRM_SHIFT                   7
+#define SDHC_IRQSTAT_CRM_WIDTH                   1
+#define SDHC_IRQSTAT_CRM(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CRM_SHIFT))&SDHC_IRQSTAT_CRM_MASK)
+#define SDHC_IRQSTAT_CINT_MASK                   0x100u
+#define SDHC_IRQSTAT_CINT_SHIFT                  8
+#define SDHC_IRQSTAT_CINT_WIDTH                  1
+#define SDHC_IRQSTAT_CINT(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINT_SHIFT))&SDHC_IRQSTAT_CINT_MASK)
+#define SDHC_IRQSTAT_CTOE_MASK                   0x10000u
+#define SDHC_IRQSTAT_CTOE_SHIFT                  16
+#define SDHC_IRQSTAT_CTOE_WIDTH                  1
+#define SDHC_IRQSTAT_CTOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CTOE_SHIFT))&SDHC_IRQSTAT_CTOE_MASK)
+#define SDHC_IRQSTAT_CCE_MASK                    0x20000u
+#define SDHC_IRQSTAT_CCE_SHIFT                   17
+#define SDHC_IRQSTAT_CCE_WIDTH                   1
+#define SDHC_IRQSTAT_CCE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CCE_SHIFT))&SDHC_IRQSTAT_CCE_MASK)
+#define SDHC_IRQSTAT_CEBE_MASK                   0x40000u
+#define SDHC_IRQSTAT_CEBE_SHIFT                  18
+#define SDHC_IRQSTAT_CEBE_WIDTH                  1
+#define SDHC_IRQSTAT_CEBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CEBE_SHIFT))&SDHC_IRQSTAT_CEBE_MASK)
+#define SDHC_IRQSTAT_CIE_MASK                    0x80000u
+#define SDHC_IRQSTAT_CIE_SHIFT                   19
+#define SDHC_IRQSTAT_CIE_WIDTH                   1
+#define SDHC_IRQSTAT_CIE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CIE_SHIFT))&SDHC_IRQSTAT_CIE_MASK)
+#define SDHC_IRQSTAT_DTOE_MASK                   0x100000u
+#define SDHC_IRQSTAT_DTOE_SHIFT                  20
+#define SDHC_IRQSTAT_DTOE_WIDTH                  1
+#define SDHC_IRQSTAT_DTOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DTOE_SHIFT))&SDHC_IRQSTAT_DTOE_MASK)
+#define SDHC_IRQSTAT_DCE_MASK                    0x200000u
+#define SDHC_IRQSTAT_DCE_SHIFT                   21
+#define SDHC_IRQSTAT_DCE_WIDTH                   1
+#define SDHC_IRQSTAT_DCE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DCE_SHIFT))&SDHC_IRQSTAT_DCE_MASK)
+#define SDHC_IRQSTAT_DEBE_MASK                   0x400000u
+#define SDHC_IRQSTAT_DEBE_SHIFT                  22
+#define SDHC_IRQSTAT_DEBE_WIDTH                  1
+#define SDHC_IRQSTAT_DEBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DEBE_SHIFT))&SDHC_IRQSTAT_DEBE_MASK)
+#define SDHC_IRQSTAT_AC12E_MASK                  0x1000000u
+#define SDHC_IRQSTAT_AC12E_SHIFT                 24
+#define SDHC_IRQSTAT_AC12E_WIDTH                 1
+#define SDHC_IRQSTAT_AC12E(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_AC12E_SHIFT))&SDHC_IRQSTAT_AC12E_MASK)
+#define SDHC_IRQSTAT_DMAE_MASK                   0x10000000u
+#define SDHC_IRQSTAT_DMAE_SHIFT                  28
+#define SDHC_IRQSTAT_DMAE_WIDTH                  1
+#define SDHC_IRQSTAT_DMAE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DMAE_SHIFT))&SDHC_IRQSTAT_DMAE_MASK)
+/* IRQSTATEN Bit Fields */
+#define SDHC_IRQSTATEN_CCSEN_MASK                0x1u
+#define SDHC_IRQSTATEN_CCSEN_SHIFT               0
+#define SDHC_IRQSTATEN_CCSEN_WIDTH               1
+#define SDHC_IRQSTATEN_CCSEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCSEN_SHIFT))&SDHC_IRQSTATEN_CCSEN_MASK)
+#define SDHC_IRQSTATEN_TCSEN_MASK                0x2u
+#define SDHC_IRQSTATEN_TCSEN_SHIFT               1
+#define SDHC_IRQSTATEN_TCSEN_WIDTH               1
+#define SDHC_IRQSTATEN_TCSEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_TCSEN_SHIFT))&SDHC_IRQSTATEN_TCSEN_MASK)
+#define SDHC_IRQSTATEN_BGESEN_MASK               0x4u
+#define SDHC_IRQSTATEN_BGESEN_SHIFT              2
+#define SDHC_IRQSTATEN_BGESEN_WIDTH              1
+#define SDHC_IRQSTATEN_BGESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BGESEN_SHIFT))&SDHC_IRQSTATEN_BGESEN_MASK)
+#define SDHC_IRQSTATEN_DINTSEN_MASK              0x8u
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT             3
+#define SDHC_IRQSTATEN_DINTSEN_WIDTH             1
+#define SDHC_IRQSTATEN_DINTSEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DINTSEN_SHIFT))&SDHC_IRQSTATEN_DINTSEN_MASK)
+#define SDHC_IRQSTATEN_BWRSEN_MASK               0x10u
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT              4
+#define SDHC_IRQSTATEN_BWRSEN_WIDTH              1
+#define SDHC_IRQSTATEN_BWRSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BWRSEN_SHIFT))&SDHC_IRQSTATEN_BWRSEN_MASK)
+#define SDHC_IRQSTATEN_BRRSEN_MASK               0x20u
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT              5
+#define SDHC_IRQSTATEN_BRRSEN_WIDTH              1
+#define SDHC_IRQSTATEN_BRRSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BRRSEN_SHIFT))&SDHC_IRQSTATEN_BRRSEN_MASK)
+#define SDHC_IRQSTATEN_CINSEN_MASK               0x40u
+#define SDHC_IRQSTATEN_CINSEN_SHIFT              6
+#define SDHC_IRQSTATEN_CINSEN_WIDTH              1
+#define SDHC_IRQSTATEN_CINSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINSEN_SHIFT))&SDHC_IRQSTATEN_CINSEN_MASK)
+#define SDHC_IRQSTATEN_CRMSEN_MASK               0x80u
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT              7
+#define SDHC_IRQSTATEN_CRMSEN_WIDTH              1
+#define SDHC_IRQSTATEN_CRMSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CRMSEN_SHIFT))&SDHC_IRQSTATEN_CRMSEN_MASK)
+#define SDHC_IRQSTATEN_CINTSEN_MASK              0x100u
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT             8
+#define SDHC_IRQSTATEN_CINTSEN_WIDTH             1
+#define SDHC_IRQSTATEN_CINTSEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINTSEN_SHIFT))&SDHC_IRQSTATEN_CINTSEN_MASK)
+#define SDHC_IRQSTATEN_CTOESEN_MASK              0x10000u
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT             16
+#define SDHC_IRQSTATEN_CTOESEN_WIDTH             1
+#define SDHC_IRQSTATEN_CTOESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CTOESEN_SHIFT))&SDHC_IRQSTATEN_CTOESEN_MASK)
+#define SDHC_IRQSTATEN_CCESEN_MASK               0x20000u
+#define SDHC_IRQSTATEN_CCESEN_SHIFT              17
+#define SDHC_IRQSTATEN_CCESEN_WIDTH              1
+#define SDHC_IRQSTATEN_CCESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCESEN_SHIFT))&SDHC_IRQSTATEN_CCESEN_MASK)
+#define SDHC_IRQSTATEN_CEBESEN_MASK              0x40000u
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT             18
+#define SDHC_IRQSTATEN_CEBESEN_WIDTH             1
+#define SDHC_IRQSTATEN_CEBESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CEBESEN_SHIFT))&SDHC_IRQSTATEN_CEBESEN_MASK)
+#define SDHC_IRQSTATEN_CIESEN_MASK               0x80000u
+#define SDHC_IRQSTATEN_CIESEN_SHIFT              19
+#define SDHC_IRQSTATEN_CIESEN_WIDTH              1
+#define SDHC_IRQSTATEN_CIESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CIESEN_SHIFT))&SDHC_IRQSTATEN_CIESEN_MASK)
+#define SDHC_IRQSTATEN_DTOESEN_MASK              0x100000u
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT             20
+#define SDHC_IRQSTATEN_DTOESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DTOESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DTOESEN_SHIFT))&SDHC_IRQSTATEN_DTOESEN_MASK)
+#define SDHC_IRQSTATEN_DCESEN_MASK               0x200000u
+#define SDHC_IRQSTATEN_DCESEN_SHIFT              21
+#define SDHC_IRQSTATEN_DCESEN_WIDTH              1
+#define SDHC_IRQSTATEN_DCESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DCESEN_SHIFT))&SDHC_IRQSTATEN_DCESEN_MASK)
+#define SDHC_IRQSTATEN_DEBESEN_MASK              0x400000u
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT             22
+#define SDHC_IRQSTATEN_DEBESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DEBESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DEBESEN_SHIFT))&SDHC_IRQSTATEN_DEBESEN_MASK)
+#define SDHC_IRQSTATEN_AC12ESEN_MASK             0x1000000u
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT            24
+#define SDHC_IRQSTATEN_AC12ESEN_WIDTH            1
+#define SDHC_IRQSTATEN_AC12ESEN(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_AC12ESEN_SHIFT))&SDHC_IRQSTATEN_AC12ESEN_MASK)
+#define SDHC_IRQSTATEN_DMAESEN_MASK              0x10000000u
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT             28
+#define SDHC_IRQSTATEN_DMAESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DMAESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DMAESEN_SHIFT))&SDHC_IRQSTATEN_DMAESEN_MASK)
+/* IRQSIGEN Bit Fields */
+#define SDHC_IRQSIGEN_CCIEN_MASK                 0x1u
+#define SDHC_IRQSIGEN_CCIEN_SHIFT                0
+#define SDHC_IRQSIGEN_CCIEN_WIDTH                1
+#define SDHC_IRQSIGEN_CCIEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCIEN_SHIFT))&SDHC_IRQSIGEN_CCIEN_MASK)
+#define SDHC_IRQSIGEN_TCIEN_MASK                 0x2u
+#define SDHC_IRQSIGEN_TCIEN_SHIFT                1
+#define SDHC_IRQSIGEN_TCIEN_WIDTH                1
+#define SDHC_IRQSIGEN_TCIEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_TCIEN_SHIFT))&SDHC_IRQSIGEN_TCIEN_MASK)
+#define SDHC_IRQSIGEN_BGEIEN_MASK                0x4u
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT               2
+#define SDHC_IRQSIGEN_BGEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BGEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BGEIEN_SHIFT))&SDHC_IRQSIGEN_BGEIEN_MASK)
+#define SDHC_IRQSIGEN_DINTIEN_MASK               0x8u
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT              3
+#define SDHC_IRQSIGEN_DINTIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DINTIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DINTIEN_SHIFT))&SDHC_IRQSIGEN_DINTIEN_MASK)
+#define SDHC_IRQSIGEN_BWRIEN_MASK                0x10u
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT               4
+#define SDHC_IRQSIGEN_BWRIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BWRIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BWRIEN_SHIFT))&SDHC_IRQSIGEN_BWRIEN_MASK)
+#define SDHC_IRQSIGEN_BRRIEN_MASK                0x20u
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT               5
+#define SDHC_IRQSIGEN_BRRIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BRRIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BRRIEN_SHIFT))&SDHC_IRQSIGEN_BRRIEN_MASK)
+#define SDHC_IRQSIGEN_CINSIEN_MASK               0x40u
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT              6
+#define SDHC_IRQSIGEN_CINSIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CINSIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINSIEN_SHIFT))&SDHC_IRQSIGEN_CINSIEN_MASK)
+#define SDHC_IRQSIGEN_CRMIEN_MASK                0x80u
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT               7
+#define SDHC_IRQSIGEN_CRMIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CRMIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CRMIEN_SHIFT))&SDHC_IRQSIGEN_CRMIEN_MASK)
+#define SDHC_IRQSIGEN_CINTIEN_MASK               0x100u
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT              8
+#define SDHC_IRQSIGEN_CINTIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CINTIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINTIEN_SHIFT))&SDHC_IRQSIGEN_CINTIEN_MASK)
+#define SDHC_IRQSIGEN_CTOEIEN_MASK               0x10000u
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT              16
+#define SDHC_IRQSIGEN_CTOEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CTOEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CTOEIEN_SHIFT))&SDHC_IRQSIGEN_CTOEIEN_MASK)
+#define SDHC_IRQSIGEN_CCEIEN_MASK                0x20000u
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT               17
+#define SDHC_IRQSIGEN_CCEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CCEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCEIEN_SHIFT))&SDHC_IRQSIGEN_CCEIEN_MASK)
+#define SDHC_IRQSIGEN_CEBEIEN_MASK               0x40000u
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT              18
+#define SDHC_IRQSIGEN_CEBEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CEBEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CEBEIEN_SHIFT))&SDHC_IRQSIGEN_CEBEIEN_MASK)
+#define SDHC_IRQSIGEN_CIEIEN_MASK                0x80000u
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT               19
+#define SDHC_IRQSIGEN_CIEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CIEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CIEIEN_SHIFT))&SDHC_IRQSIGEN_CIEIEN_MASK)
+#define SDHC_IRQSIGEN_DTOEIEN_MASK               0x100000u
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT              20
+#define SDHC_IRQSIGEN_DTOEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DTOEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DTOEIEN_SHIFT))&SDHC_IRQSIGEN_DTOEIEN_MASK)
+#define SDHC_IRQSIGEN_DCEIEN_MASK                0x200000u
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT               21
+#define SDHC_IRQSIGEN_DCEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_DCEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DCEIEN_SHIFT))&SDHC_IRQSIGEN_DCEIEN_MASK)
+#define SDHC_IRQSIGEN_DEBEIEN_MASK               0x400000u
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT              22
+#define SDHC_IRQSIGEN_DEBEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DEBEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DEBEIEN_SHIFT))&SDHC_IRQSIGEN_DEBEIEN_MASK)
+#define SDHC_IRQSIGEN_AC12EIEN_MASK              0x1000000u
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT             24
+#define SDHC_IRQSIGEN_AC12EIEN_WIDTH             1
+#define SDHC_IRQSIGEN_AC12EIEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_AC12EIEN_SHIFT))&SDHC_IRQSIGEN_AC12EIEN_MASK)
+#define SDHC_IRQSIGEN_DMAEIEN_MASK               0x10000000u
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT              28
+#define SDHC_IRQSIGEN_DMAEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DMAEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DMAEIEN_SHIFT))&SDHC_IRQSIGEN_DMAEIEN_MASK)
+/* AC12ERR Bit Fields */
+#define SDHC_AC12ERR_AC12NE_MASK                 0x1u
+#define SDHC_AC12ERR_AC12NE_SHIFT                0
+#define SDHC_AC12ERR_AC12NE_WIDTH                1
+#define SDHC_AC12ERR_AC12NE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12NE_SHIFT))&SDHC_AC12ERR_AC12NE_MASK)
+#define SDHC_AC12ERR_AC12TOE_MASK                0x2u
+#define SDHC_AC12ERR_AC12TOE_SHIFT               1
+#define SDHC_AC12ERR_AC12TOE_WIDTH               1
+#define SDHC_AC12ERR_AC12TOE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12TOE_SHIFT))&SDHC_AC12ERR_AC12TOE_MASK)
+#define SDHC_AC12ERR_AC12EBE_MASK                0x4u
+#define SDHC_AC12ERR_AC12EBE_SHIFT               2
+#define SDHC_AC12ERR_AC12EBE_WIDTH               1
+#define SDHC_AC12ERR_AC12EBE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12EBE_SHIFT))&SDHC_AC12ERR_AC12EBE_MASK)
+#define SDHC_AC12ERR_AC12CE_MASK                 0x8u
+#define SDHC_AC12ERR_AC12CE_SHIFT                3
+#define SDHC_AC12ERR_AC12CE_WIDTH                1
+#define SDHC_AC12ERR_AC12CE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12CE_SHIFT))&SDHC_AC12ERR_AC12CE_MASK)
+#define SDHC_AC12ERR_AC12IE_MASK                 0x10u
+#define SDHC_AC12ERR_AC12IE_SHIFT                4
+#define SDHC_AC12ERR_AC12IE_WIDTH                1
+#define SDHC_AC12ERR_AC12IE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12IE_SHIFT))&SDHC_AC12ERR_AC12IE_MASK)
+#define SDHC_AC12ERR_CNIBAC12E_MASK              0x80u
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT             7
+#define SDHC_AC12ERR_CNIBAC12E_WIDTH             1
+#define SDHC_AC12ERR_CNIBAC12E(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_CNIBAC12E_SHIFT))&SDHC_AC12ERR_CNIBAC12E_MASK)
+/* HTCAPBLT Bit Fields */
+#define SDHC_HTCAPBLT_MBL_MASK                   0x70000u
+#define SDHC_HTCAPBLT_MBL_SHIFT                  16
+#define SDHC_HTCAPBLT_MBL_WIDTH                  3
+#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK                 0x100000u
+#define SDHC_HTCAPBLT_ADMAS_SHIFT                20
+#define SDHC_HTCAPBLT_ADMAS_WIDTH                1
+#define SDHC_HTCAPBLT_ADMAS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_ADMAS_SHIFT))&SDHC_HTCAPBLT_ADMAS_MASK)
+#define SDHC_HTCAPBLT_HSS_MASK                   0x200000u
+#define SDHC_HTCAPBLT_HSS_SHIFT                  21
+#define SDHC_HTCAPBLT_HSS_WIDTH                  1
+#define SDHC_HTCAPBLT_HSS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_HSS_SHIFT))&SDHC_HTCAPBLT_HSS_MASK)
+#define SDHC_HTCAPBLT_DMAS_MASK                  0x400000u
+#define SDHC_HTCAPBLT_DMAS_SHIFT                 22
+#define SDHC_HTCAPBLT_DMAS_WIDTH                 1
+#define SDHC_HTCAPBLT_DMAS(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_DMAS_SHIFT))&SDHC_HTCAPBLT_DMAS_MASK)
+#define SDHC_HTCAPBLT_SRS_MASK                   0x800000u
+#define SDHC_HTCAPBLT_SRS_SHIFT                  23
+#define SDHC_HTCAPBLT_SRS_WIDTH                  1
+#define SDHC_HTCAPBLT_SRS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_SRS_SHIFT))&SDHC_HTCAPBLT_SRS_MASK)
+#define SDHC_HTCAPBLT_VS33_MASK                  0x1000000u
+#define SDHC_HTCAPBLT_VS33_SHIFT                 24
+#define SDHC_HTCAPBLT_VS33_WIDTH                 1
+#define SDHC_HTCAPBLT_VS33(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_VS33_SHIFT))&SDHC_HTCAPBLT_VS33_MASK)
+/* WML Bit Fields */
+#define SDHC_WML_RDWML_MASK                      0xFFu
+#define SDHC_WML_RDWML_SHIFT                     0
+#define SDHC_WML_RDWML_WIDTH                     8
+#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK                      0xFF0000u
+#define SDHC_WML_WRWML_SHIFT                     16
+#define SDHC_WML_WRWML_WIDTH                     8
+#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
+/* FEVT Bit Fields */
+#define SDHC_FEVT_AC12NE_MASK                    0x1u
+#define SDHC_FEVT_AC12NE_SHIFT                   0
+#define SDHC_FEVT_AC12NE_WIDTH                   1
+#define SDHC_FEVT_AC12NE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12NE_SHIFT))&SDHC_FEVT_AC12NE_MASK)
+#define SDHC_FEVT_AC12TOE_MASK                   0x2u
+#define SDHC_FEVT_AC12TOE_SHIFT                  1
+#define SDHC_FEVT_AC12TOE_WIDTH                  1
+#define SDHC_FEVT_AC12TOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12TOE_SHIFT))&SDHC_FEVT_AC12TOE_MASK)
+#define SDHC_FEVT_AC12CE_MASK                    0x4u
+#define SDHC_FEVT_AC12CE_SHIFT                   2
+#define SDHC_FEVT_AC12CE_WIDTH                   1
+#define SDHC_FEVT_AC12CE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12CE_SHIFT))&SDHC_FEVT_AC12CE_MASK)
+#define SDHC_FEVT_AC12EBE_MASK                   0x8u
+#define SDHC_FEVT_AC12EBE_SHIFT                  3
+#define SDHC_FEVT_AC12EBE_WIDTH                  1
+#define SDHC_FEVT_AC12EBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12EBE_SHIFT))&SDHC_FEVT_AC12EBE_MASK)
+#define SDHC_FEVT_AC12IE_MASK                    0x10u
+#define SDHC_FEVT_AC12IE_SHIFT                   4
+#define SDHC_FEVT_AC12IE_WIDTH                   1
+#define SDHC_FEVT_AC12IE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12IE_SHIFT))&SDHC_FEVT_AC12IE_MASK)
+#define SDHC_FEVT_CNIBAC12E_MASK                 0x80u
+#define SDHC_FEVT_CNIBAC12E_SHIFT                7
+#define SDHC_FEVT_CNIBAC12E_WIDTH                1
+#define SDHC_FEVT_CNIBAC12E(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CNIBAC12E_SHIFT))&SDHC_FEVT_CNIBAC12E_MASK)
+#define SDHC_FEVT_CTOE_MASK                      0x10000u
+#define SDHC_FEVT_CTOE_SHIFT                     16
+#define SDHC_FEVT_CTOE_WIDTH                     1
+#define SDHC_FEVT_CTOE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CTOE_SHIFT))&SDHC_FEVT_CTOE_MASK)
+#define SDHC_FEVT_CCE_MASK                       0x20000u
+#define SDHC_FEVT_CCE_SHIFT                      17
+#define SDHC_FEVT_CCE_WIDTH                      1
+#define SDHC_FEVT_CCE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CCE_SHIFT))&SDHC_FEVT_CCE_MASK)
+#define SDHC_FEVT_CEBE_MASK                      0x40000u
+#define SDHC_FEVT_CEBE_SHIFT                     18
+#define SDHC_FEVT_CEBE_WIDTH                     1
+#define SDHC_FEVT_CEBE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CEBE_SHIFT))&SDHC_FEVT_CEBE_MASK)
+#define SDHC_FEVT_CIE_MASK                       0x80000u
+#define SDHC_FEVT_CIE_SHIFT                      19
+#define SDHC_FEVT_CIE_WIDTH                      1
+#define SDHC_FEVT_CIE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CIE_SHIFT))&SDHC_FEVT_CIE_MASK)
+#define SDHC_FEVT_DTOE_MASK                      0x100000u
+#define SDHC_FEVT_DTOE_SHIFT                     20
+#define SDHC_FEVT_DTOE_WIDTH                     1
+#define SDHC_FEVT_DTOE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DTOE_SHIFT))&SDHC_FEVT_DTOE_MASK)
+#define SDHC_FEVT_DCE_MASK                       0x200000u
+#define SDHC_FEVT_DCE_SHIFT                      21
+#define SDHC_FEVT_DCE_WIDTH                      1
+#define SDHC_FEVT_DCE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DCE_SHIFT))&SDHC_FEVT_DCE_MASK)
+#define SDHC_FEVT_DEBE_MASK                      0x400000u
+#define SDHC_FEVT_DEBE_SHIFT                     22
+#define SDHC_FEVT_DEBE_WIDTH                     1
+#define SDHC_FEVT_DEBE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DEBE_SHIFT))&SDHC_FEVT_DEBE_MASK)
+#define SDHC_FEVT_AC12E_MASK                     0x1000000u
+#define SDHC_FEVT_AC12E_SHIFT                    24
+#define SDHC_FEVT_AC12E_WIDTH                    1
+#define SDHC_FEVT_AC12E(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12E_SHIFT))&SDHC_FEVT_AC12E_MASK)
+#define SDHC_FEVT_DMAE_MASK                      0x10000000u
+#define SDHC_FEVT_DMAE_SHIFT                     28
+#define SDHC_FEVT_DMAE_WIDTH                     1
+#define SDHC_FEVT_DMAE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DMAE_SHIFT))&SDHC_FEVT_DMAE_MASK)
+#define SDHC_FEVT_CINT_MASK                      0x80000000u
+#define SDHC_FEVT_CINT_SHIFT                     31
+#define SDHC_FEVT_CINT_WIDTH                     1
+#define SDHC_FEVT_CINT(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CINT_SHIFT))&SDHC_FEVT_CINT_MASK)
+/* ADMAES Bit Fields */
+#define SDHC_ADMAES_ADMAES_MASK                  0x3u
+#define SDHC_ADMAES_ADMAES_SHIFT                 0
+#define SDHC_ADMAES_ADMAES_WIDTH                 2
+#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK                 0x4u
+#define SDHC_ADMAES_ADMALME_SHIFT                2
+#define SDHC_ADMAES_ADMALME_WIDTH                1
+#define SDHC_ADMAES_ADMALME(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMALME_SHIFT))&SDHC_ADMAES_ADMALME_MASK)
+#define SDHC_ADMAES_ADMADCE_MASK                 0x8u
+#define SDHC_ADMAES_ADMADCE_SHIFT                3
+#define SDHC_ADMAES_ADMADCE_WIDTH                1
+#define SDHC_ADMAES_ADMADCE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMADCE_SHIFT))&SDHC_ADMAES_ADMADCE_MASK)
+/* ADSADDR Bit Fields */
+#define SDHC_ADSADDR_ADSADDR_MASK                0xFFFFFFFCu
+#define SDHC_ADSADDR_ADSADDR_SHIFT               2
+#define SDHC_ADSADDR_ADSADDR_WIDTH               30
+#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
+/* VENDOR Bit Fields */
+#define SDHC_VENDOR_EXTDMAEN_MASK                0x1u
+#define SDHC_VENDOR_EXTDMAEN_SHIFT               0
+#define SDHC_VENDOR_EXTDMAEN_WIDTH               1
+#define SDHC_VENDOR_EXTDMAEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXTDMAEN_SHIFT))&SDHC_VENDOR_EXTDMAEN_MASK)
+#define SDHC_VENDOR_EXBLKNU_MASK                 0x2u
+#define SDHC_VENDOR_EXBLKNU_SHIFT                1
+#define SDHC_VENDOR_EXBLKNU_WIDTH                1
+#define SDHC_VENDOR_EXBLKNU(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXBLKNU_SHIFT))&SDHC_VENDOR_EXBLKNU_MASK)
+#define SDHC_VENDOR_INTSTVAL_MASK                0xFF0000u
+#define SDHC_VENDOR_INTSTVAL_SHIFT               16
+#define SDHC_VENDOR_INTSTVAL_WIDTH               8
+#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
+/* MMCBOOT Bit Fields */
+#define SDHC_MMCBOOT_DTOCVACK_MASK               0xFu
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT              0
+#define SDHC_MMCBOOT_DTOCVACK_WIDTH              4
+#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK                0x10u
+#define SDHC_MMCBOOT_BOOTACK_SHIFT               4
+#define SDHC_MMCBOOT_BOOTACK_WIDTH               1
+#define SDHC_MMCBOOT_BOOTACK(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTACK_SHIFT))&SDHC_MMCBOOT_BOOTACK_MASK)
+#define SDHC_MMCBOOT_BOOTMODE_MASK               0x20u
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT              5
+#define SDHC_MMCBOOT_BOOTMODE_WIDTH              1
+#define SDHC_MMCBOOT_BOOTMODE(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTMODE_SHIFT))&SDHC_MMCBOOT_BOOTMODE_MASK)
+#define SDHC_MMCBOOT_BOOTEN_MASK                 0x40u
+#define SDHC_MMCBOOT_BOOTEN_SHIFT                6
+#define SDHC_MMCBOOT_BOOTEN_WIDTH                1
+#define SDHC_MMCBOOT_BOOTEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTEN_SHIFT))&SDHC_MMCBOOT_BOOTEN_MASK)
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK             0x80u
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            7
+#define SDHC_MMCBOOT_AUTOSABGEN_WIDTH            1
+#define SDHC_MMCBOOT_AUTOSABGEN(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_AUTOSABGEN_SHIFT))&SDHC_MMCBOOT_AUTOSABGEN_MASK)
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             0xFFFF0000u
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            16
+#define SDHC_MMCBOOT_BOOTBLKCNT_WIDTH            16
+#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+/* HOSTVER Bit Fields */
+#define SDHC_HOSTVER_SVN_MASK                    0xFFu
+#define SDHC_HOSTVER_SVN_SHIFT                   0
+#define SDHC_HOSTVER_SVN_WIDTH                   8
+#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK                    0xFF00u
+#define SDHC_HOSTVER_VVN_SHIFT                   8
+#define SDHC_HOSTVER_VVN_WIDTH                   8
+#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/** Peripheral SDHC base address */
+#define SDHC_BASE                                (0x400B1000u)
+/** Peripheral SDHC base pointer */
+#define SDHC                                     ((SDHC_Type *)SDHC_BASE)
+#define SDHC_BASE_PTR                            (SDHC)
+/** Array initializer of SDHC peripheral base addresses */
+#define SDHC_BASE_ADDRS                          { SDHC_BASE }
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASE_PTRS                           { SDHC }
+/** Interrupt vectors for the SDHC peripheral type */
+#define SDHC_IRQS                                { SDHC_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register instance definitions */
+/* SDHC */
+#define SDHC_DSADDR                              SDHC_DSADDR_REG(SDHC)
+#define SDHC_BLKATTR                             SDHC_BLKATTR_REG(SDHC)
+#define SDHC_CMDARG                              SDHC_CMDARG_REG(SDHC)
+#define SDHC_XFERTYP                             SDHC_XFERTYP_REG(SDHC)
+#define SDHC_CMDRSP0                             SDHC_CMDRSP_REG(SDHC,0)
+#define SDHC_CMDRSP1                             SDHC_CMDRSP_REG(SDHC,1)
+#define SDHC_CMDRSP2                             SDHC_CMDRSP_REG(SDHC,2)
+#define SDHC_CMDRSP3                             SDHC_CMDRSP_REG(SDHC,3)
+#define SDHC_DATPORT                             SDHC_DATPORT_REG(SDHC)
+#define SDHC_PRSSTAT                             SDHC_PRSSTAT_REG(SDHC)
+#define SDHC_PROCTL                              SDHC_PROCTL_REG(SDHC)
+#define SDHC_SYSCTL                              SDHC_SYSCTL_REG(SDHC)
+#define SDHC_IRQSTAT                             SDHC_IRQSTAT_REG(SDHC)
+#define SDHC_IRQSTATEN                           SDHC_IRQSTATEN_REG(SDHC)
+#define SDHC_IRQSIGEN                            SDHC_IRQSIGEN_REG(SDHC)
+#define SDHC_AC12ERR                             SDHC_AC12ERR_REG(SDHC)
+#define SDHC_HTCAPBLT                            SDHC_HTCAPBLT_REG(SDHC)
+#define SDHC_WML                                 SDHC_WML_REG(SDHC)
+#define SDHC_FEVT                                SDHC_FEVT_REG(SDHC)
+#define SDHC_ADMAES                              SDHC_ADMAES_REG(SDHC)
+#define SDHC_ADSADDR                             SDHC_ADSADDR_REG(SDHC)
+#define SDHC_VENDOR                              SDHC_VENDOR_REG(SDHC)
+#define SDHC_MMCBOOT                             SDHC_MMCBOOT_REG(SDHC)
+#define SDHC_HOSTVER                             SDHC_HOSTVER_REG(SDHC)
+
+/* SDHC - Register array accessors */
+#define SDHC_CMDRSP(index)                       SDHC_CMDRSP_REG(SDHC,index)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
+       uint8_t RESERVED_0[4092];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+  __IO uint32_t SCGC1;                             /**< System Clock Gating Control Register 1, offset: 0x1028 */
+  __IO uint32_t SCGC2;                             /**< System Clock Gating Control Register 2, offset: 0x102C */
+  __IO uint32_t SCGC3;                             /**< System Clock Gating Control Register 3, offset: 0x1030 */
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+  __IO uint32_t CLKDIV2;                           /**< System Clock Divider Register 2, offset: 0x1048 */
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+  __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base)                      ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base)                   ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base)                      ((base)->SOPT2)
+#define SIM_SOPT4_REG(base)                      ((base)->SOPT4)
+#define SIM_SOPT5_REG(base)                      ((base)->SOPT5)
+#define SIM_SOPT7_REG(base)                      ((base)->SOPT7)
+#define SIM_SDID_REG(base)                       ((base)->SDID)
+#define SIM_SCGC1_REG(base)                      ((base)->SCGC1)
+#define SIM_SCGC2_REG(base)                      ((base)->SCGC2)
+#define SIM_SCGC3_REG(base)                      ((base)->SCGC3)
+#define SIM_SCGC4_REG(base)                      ((base)->SCGC4)
+#define SIM_SCGC5_REG(base)                      ((base)->SCGC5)
+#define SIM_SCGC6_REG(base)                      ((base)->SCGC6)
+#define SIM_SCGC7_REG(base)                      ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base)                    ((base)->CLKDIV1)
+#define SIM_CLKDIV2_REG(base)                    ((base)->CLKDIV2)
+#define SIM_FCFG1_REG(base)                      ((base)->FCFG1)
+#define SIM_FCFG2_REG(base)                      ((base)->FCFG2)
+#define SIM_UIDH_REG(base)                       ((base)->UIDH)
+#define SIM_UIDMH_REG(base)                      ((base)->UIDMH)
+#define SIM_UIDML_REG(base)                      ((base)->UIDML)
+#define SIM_UIDL_REG(base)                       ((base)->UIDL)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK                   0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT                  12
+#define SIM_SOPT1_RAMSIZE_WIDTH                  4
+#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT                18
+#define SIM_SOPT1_OSC32KSEL_WIDTH                2
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK                  0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT                 29
+#define SIM_SOPT1_USBVSTBY_WIDTH                 1
+#define SIM_SOPT1_USBVSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBVSTBY_SHIFT))&SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK                  0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT                 30
+#define SIM_SOPT1_USBSSTBY_WIDTH                 1
+#define SIM_SOPT1_USBSSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBSSTBY_SHIFT))&SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK                  0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT                 31
+#define SIM_SOPT1_USBREGEN_WIDTH                 1
+#define SIM_SOPT1_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBREGEN_SHIFT))&SIM_SOPT1_USBREGEN_MASK)
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK                   0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT                  24
+#define SIM_SOPT1CFG_URWE_WIDTH                  1
+#define SIM_SOPT1CFG_URWE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_URWE_SHIFT))&SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK                  0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT                 25
+#define SIM_SOPT1CFG_UVSWE_WIDTH                 1
+#define SIM_SOPT1CFG_UVSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_UVSWE_SHIFT))&SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK                  0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT                 26
+#define SIM_SOPT1CFG_USSWE_WIDTH                 1
+#define SIM_SOPT1CFG_USSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_USSWE_SHIFT))&SIM_SOPT1CFG_USSWE_MASK)
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
+#define SIM_SOPT2_RTCCLKOUTSEL_WIDTH             1
+#define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                5
+#define SIM_SOPT2_CLKOUTSEL_WIDTH                3
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK                      0x300u
+#define SIM_SOPT2_FBSL_SHIFT                     8
+#define SIM_SOPT2_FBSL_WIDTH                     2
+#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK                   0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT                  11
+#define SIM_SOPT2_PTD7PAD_WIDTH                  1
+#define SIM_SOPT2_PTD7PAD(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PTD7PAD_SHIFT))&SIM_SOPT2_PTD7PAD_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK               0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT              12
+#define SIM_SOPT2_TRACECLKSEL_WIDTH              1
+#define SIM_SOPT2_TRACECLKSEL(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TRACECLKSEL_SHIFT))&SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK                 0x30000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                16
+#define SIM_SOPT2_PLLFLLSEL_WIDTH                2
+#define SIM_SOPT2_PLLFLLSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK                    0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT                   18
+#define SIM_SOPT2_USBSRC_WIDTH                   1
+#define SIM_SOPT2_USBSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_RMIISRC_MASK                   0x80000u
+#define SIM_SOPT2_RMIISRC_SHIFT                  19
+#define SIM_SOPT2_RMIISRC_WIDTH                  1
+#define SIM_SOPT2_RMIISRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RMIISRC_SHIFT))&SIM_SOPT2_RMIISRC_MASK)
+#define SIM_SOPT2_TIMESRC_MASK                   0x300000u
+#define SIM_SOPT2_TIMESRC_SHIFT                  20
+#define SIM_SOPT2_TIMESRC_WIDTH                  2
+#define SIM_SOPT2_TIMESRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK                   0x30000000u
+#define SIM_SOPT2_SDHCSRC_SHIFT                  28
+#define SIM_SOPT2_SDHCSRC_WIDTH                  2
+#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK                  0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT                 0
+#define SIM_SOPT4_FTM0FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT0_SHIFT))&SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK                  0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT                 1
+#define SIM_SOPT4_FTM0FLT1_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT1_SHIFT))&SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM0FLT2_MASK                  0x4u
+#define SIM_SOPT4_FTM0FLT2_SHIFT                 2
+#define SIM_SOPT4_FTM0FLT2_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT2(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT2_SHIFT))&SIM_SOPT4_FTM0FLT2_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK                  0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT                 4
+#define SIM_SOPT4_FTM1FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM1FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1FLT0_SHIFT))&SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_MASK                  0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT                 8
+#define SIM_SOPT4_FTM2FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM2FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2FLT0_SHIFT))&SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM3FLT0_MASK                  0x1000u
+#define SIM_SOPT4_FTM3FLT0_SHIFT                 12
+#define SIM_SOPT4_FTM3FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM3FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3FLT0_SHIFT))&SIM_SOPT4_FTM3FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK                0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT               18
+#define SIM_SOPT4_FTM1CH0SRC_WIDTH               2
+#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK                0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT               20
+#define SIM_SOPT4_FTM2CH0SRC_WIDTH               2
+#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK                0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT               24
+#define SIM_SOPT4_FTM0CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0CLKSEL_SHIFT))&SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK                0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT               25
+#define SIM_SOPT4_FTM1CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CLKSEL_SHIFT))&SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_MASK                0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT               26
+#define SIM_SOPT4_FTM2CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CLKSEL_SHIFT))&SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM3CLKSEL_MASK                0x8000000u
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT               27
+#define SIM_SOPT4_FTM3CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM3CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3CLKSEL_SHIFT))&SIM_SOPT4_FTM3CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK               0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT              28
+#define SIM_SOPT4_FTM0TRG0SRC_WIDTH              1
+#define SIM_SOPT4_FTM0TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG0SRC_SHIFT))&SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_MASK               0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT              29
+#define SIM_SOPT4_FTM0TRG1SRC_WIDTH              1
+#define SIM_SOPT4_FTM0TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG1SRC_SHIFT))&SIM_SOPT4_FTM0TRG1SRC_MASK)
+#define SIM_SOPT4_FTM3TRG0SRC_MASK               0x40000000u
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT              30
+#define SIM_SOPT4_FTM3TRG0SRC_WIDTH              1
+#define SIM_SOPT4_FTM3TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG0SRC_SHIFT))&SIM_SOPT4_FTM3TRG0SRC_MASK)
+#define SIM_SOPT4_FTM3TRG1SRC_MASK               0x80000000u
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT              31
+#define SIM_SOPT4_FTM3TRG1SRC_WIDTH              1
+#define SIM_SOPT4_FTM3TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG1SRC_SHIFT))&SIM_SOPT4_FTM3TRG1SRC_MASK)
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK                0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT               0
+#define SIM_SOPT5_UART0TXSRC_WIDTH               2
+#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK                0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT               2
+#define SIM_SOPT5_UART0RXSRC_WIDTH               2
+#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK                0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT               4
+#define SIM_SOPT5_UART1TXSRC_WIDTH               2
+#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK                0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT               6
+#define SIM_SOPT5_UART1RXSRC_WIDTH               2
+#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
+#define SIM_SOPT7_ADC0TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
+#define SIM_SOPT7_ADC0PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
+#define SIM_SOPT7_ADC0ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_MASK                0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT               8
+#define SIM_SOPT7_ADC1TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK             0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            12
+#define SIM_SOPT7_ADC1PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC1PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1PRETRGSEL_SHIFT))&SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK              0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             15
+#define SIM_SOPT7_ADC1ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC1ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1ALTTRGEN_SHIFT))&SIM_SOPT7_ADC1ALTTRGEN_MASK)
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK                      0xFu
+#define SIM_SDID_PINID_SHIFT                     0
+#define SIM_SDID_PINID_WIDTH                     4
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK                      0x70u
+#define SIM_SDID_FAMID_SHIFT                     4
+#define SIM_SDID_FAMID_WIDTH                     3
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK                      0xF80u
+#define SIM_SDID_DIEID_SHIFT                     7
+#define SIM_SDID_DIEID_WIDTH                     5
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      0xF000u
+#define SIM_SDID_REVID_SHIFT                     12
+#define SIM_SDID_REVID_WIDTH                     4
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK                   0xF00000u
+#define SIM_SDID_SERIESID_SHIFT                  20
+#define SIM_SDID_SERIESID_WIDTH                  4
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT                  24
+#define SIM_SDID_SUBFAMID_WIDTH                  4
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK                   0xF0000000u
+#define SIM_SDID_FAMILYID_SHIFT                  28
+#define SIM_SDID_FAMILYID_WIDTH                  4
+#define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
+/* SCGC1 Bit Fields */
+#define SIM_SCGC1_I2C2_MASK                      0x40u
+#define SIM_SCGC1_I2C2_SHIFT                     6
+#define SIM_SCGC1_I2C2_WIDTH                     1
+#define SIM_SCGC1_I2C2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_I2C2_SHIFT))&SIM_SCGC1_I2C2_MASK)
+#define SIM_SCGC1_UART4_MASK                     0x400u
+#define SIM_SCGC1_UART4_SHIFT                    10
+#define SIM_SCGC1_UART4_WIDTH                    1
+#define SIM_SCGC1_UART4(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART4_SHIFT))&SIM_SCGC1_UART4_MASK)
+#define SIM_SCGC1_UART5_MASK                     0x800u
+#define SIM_SCGC1_UART5_SHIFT                    11
+#define SIM_SCGC1_UART5_WIDTH                    1
+#define SIM_SCGC1_UART5(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART5_SHIFT))&SIM_SCGC1_UART5_MASK)
+/* SCGC2 Bit Fields */
+#define SIM_SCGC2_ENET_MASK                      0x1u
+#define SIM_SCGC2_ENET_SHIFT                     0
+#define SIM_SCGC2_ENET_WIDTH                     1
+#define SIM_SCGC2_ENET(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_ENET_SHIFT))&SIM_SCGC2_ENET_MASK)
+#define SIM_SCGC2_DAC0_MASK                      0x1000u
+#define SIM_SCGC2_DAC0_SHIFT                     12
+#define SIM_SCGC2_DAC0_WIDTH                     1
+#define SIM_SCGC2_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC0_SHIFT))&SIM_SCGC2_DAC0_MASK)
+#define SIM_SCGC2_DAC1_MASK                      0x2000u
+#define SIM_SCGC2_DAC1_SHIFT                     13
+#define SIM_SCGC2_DAC1_WIDTH                     1
+#define SIM_SCGC2_DAC1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC1_SHIFT))&SIM_SCGC2_DAC1_MASK)
+/* SCGC3 Bit Fields */
+#define SIM_SCGC3_RNGA_MASK                      0x1u
+#define SIM_SCGC3_RNGA_SHIFT                     0
+#define SIM_SCGC3_RNGA_WIDTH                     1
+#define SIM_SCGC3_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_RNGA_SHIFT))&SIM_SCGC3_RNGA_MASK)
+#define SIM_SCGC3_SPI2_MASK                      0x1000u
+#define SIM_SCGC3_SPI2_SHIFT                     12
+#define SIM_SCGC3_SPI2_WIDTH                     1
+#define SIM_SCGC3_SPI2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SPI2_SHIFT))&SIM_SCGC3_SPI2_MASK)
+#define SIM_SCGC3_SDHC_MASK                      0x20000u
+#define SIM_SCGC3_SDHC_SHIFT                     17
+#define SIM_SCGC3_SDHC_WIDTH                     1
+#define SIM_SCGC3_SDHC(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SDHC_SHIFT))&SIM_SCGC3_SDHC_MASK)
+#define SIM_SCGC3_FTM2_MASK                      0x1000000u
+#define SIM_SCGC3_FTM2_SHIFT                     24
+#define SIM_SCGC3_FTM2_WIDTH                     1
+#define SIM_SCGC3_FTM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM2_SHIFT))&SIM_SCGC3_FTM2_MASK)
+#define SIM_SCGC3_FTM3_MASK                      0x2000000u
+#define SIM_SCGC3_FTM3_SHIFT                     25
+#define SIM_SCGC3_FTM3_WIDTH                     1
+#define SIM_SCGC3_FTM3(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM3_SHIFT))&SIM_SCGC3_FTM3_MASK)
+#define SIM_SCGC3_ADC1_MASK                      0x8000000u
+#define SIM_SCGC3_ADC1_SHIFT                     27
+#define SIM_SCGC3_ADC1_WIDTH                     1
+#define SIM_SCGC3_ADC1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_ADC1_SHIFT))&SIM_SCGC3_ADC1_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK                       0x2u
+#define SIM_SCGC4_EWM_SHIFT                      1
+#define SIM_SCGC4_EWM_WIDTH                      1
+#define SIM_SCGC4_EWM(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_EWM_SHIFT))&SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_CMT_MASK                       0x4u
+#define SIM_SCGC4_CMT_SHIFT                      2
+#define SIM_SCGC4_CMT_WIDTH                      1
+#define SIM_SCGC4_CMT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMT_SHIFT))&SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_I2C0_MASK                      0x40u
+#define SIM_SCGC4_I2C0_SHIFT                     6
+#define SIM_SCGC4_I2C0_WIDTH                     1
+#define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C0_SHIFT))&SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK                      0x80u
+#define SIM_SCGC4_I2C1_SHIFT                     7
+#define SIM_SCGC4_I2C1_WIDTH                     1
+#define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C1_SHIFT))&SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK                     0x400u
+#define SIM_SCGC4_UART0_SHIFT                    10
+#define SIM_SCGC4_UART0_WIDTH                    1
+#define SIM_SCGC4_UART0(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART0_SHIFT))&SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK                     0x800u
+#define SIM_SCGC4_UART1_SHIFT                    11
+#define SIM_SCGC4_UART1_WIDTH                    1
+#define SIM_SCGC4_UART1(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART1_SHIFT))&SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK                     0x1000u
+#define SIM_SCGC4_UART2_SHIFT                    12
+#define SIM_SCGC4_UART2_WIDTH                    1
+#define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_UART3_MASK                     0x2000u
+#define SIM_SCGC4_UART3_SHIFT                    13
+#define SIM_SCGC4_UART3_WIDTH                    1
+#define SIM_SCGC4_UART3(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART3_SHIFT))&SIM_SCGC4_UART3_MASK)
+#define SIM_SCGC4_USBOTG_MASK                    0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT                   18
+#define SIM_SCGC4_USBOTG_WIDTH                   1
+#define SIM_SCGC4_USBOTG(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBOTG_SHIFT))&SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK                       0x80000u
+#define SIM_SCGC4_CMP_SHIFT                      19
+#define SIM_SCGC4_CMP_WIDTH                      1
+#define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK                      0x100000u
+#define SIM_SCGC4_VREF_SHIFT                     20
+#define SIM_SCGC4_VREF_WIDTH                     1
+#define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_VREF_SHIFT))&SIM_SCGC4_VREF_MASK)
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK                     0x1u
+#define SIM_SCGC5_LPTMR_SHIFT                    0
+#define SIM_SCGC5_LPTMR_WIDTH                    1
+#define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_PORTA_MASK                     0x200u
+#define SIM_SCGC5_PORTA_SHIFT                    9
+#define SIM_SCGC5_PORTA_WIDTH                    1
+#define SIM_SCGC5_PORTA(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK                     0x400u
+#define SIM_SCGC5_PORTB_SHIFT                    10
+#define SIM_SCGC5_PORTB_WIDTH                    1
+#define SIM_SCGC5_PORTB(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK                     0x800u
+#define SIM_SCGC5_PORTC_SHIFT                    11
+#define SIM_SCGC5_PORTC_WIDTH                    1
+#define SIM_SCGC5_PORTC(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK                     0x1000u
+#define SIM_SCGC5_PORTD_SHIFT                    12
+#define SIM_SCGC5_PORTD_WIDTH                    1
+#define SIM_SCGC5_PORTD(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK                     0x2000u
+#define SIM_SCGC5_PORTE_SHIFT                    13
+#define SIM_SCGC5_PORTE_WIDTH                    1
+#define SIM_SCGC5_PORTE(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK                       0x1u
+#define SIM_SCGC6_FTF_SHIFT                      0
+#define SIM_SCGC6_FTF_WIDTH                      1
+#define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK                    0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT                   1
+#define SIM_SCGC6_DMAMUX_WIDTH                   1
+#define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_FLEXCAN0_MASK                  0x10u
+#define SIM_SCGC6_FLEXCAN0_SHIFT                 4
+#define SIM_SCGC6_FLEXCAN0_WIDTH                 1
+#define SIM_SCGC6_FLEXCAN0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FLEXCAN0_SHIFT))&SIM_SCGC6_FLEXCAN0_MASK)
+#define SIM_SCGC6_RNGA_MASK                      0x200u
+#define SIM_SCGC6_RNGA_SHIFT                     9
+#define SIM_SCGC6_RNGA_WIDTH                     1
+#define SIM_SCGC6_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RNGA_SHIFT))&SIM_SCGC6_RNGA_MASK)
+#define SIM_SCGC6_SPI0_MASK                      0x1000u
+#define SIM_SCGC6_SPI0_SHIFT                     12
+#define SIM_SCGC6_SPI0_WIDTH                     1
+#define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI0_SHIFT))&SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK                      0x2000u
+#define SIM_SCGC6_SPI1_SHIFT                     13
+#define SIM_SCGC6_SPI1_WIDTH                     1
+#define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI1_SHIFT))&SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_I2S_MASK                       0x8000u
+#define SIM_SCGC6_I2S_SHIFT                      15
+#define SIM_SCGC6_I2S_WIDTH                      1
+#define SIM_SCGC6_I2S(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S_SHIFT))&SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK                       0x40000u
+#define SIM_SCGC6_CRC_SHIFT                      18
+#define SIM_SCGC6_CRC_WIDTH                      1
+#define SIM_SCGC6_CRC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_CRC_SHIFT))&SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_USBDCD_MASK                    0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT                   21
+#define SIM_SCGC6_USBDCD_WIDTH                   1
+#define SIM_SCGC6_USBDCD(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_USBDCD_SHIFT))&SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_PDB_MASK                       0x400000u
+#define SIM_SCGC6_PDB_SHIFT                      22
+#define SIM_SCGC6_PDB_WIDTH                      1
+#define SIM_SCGC6_PDB(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PDB_SHIFT))&SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK                       0x800000u
+#define SIM_SCGC6_PIT_SHIFT                      23
+#define SIM_SCGC6_PIT_WIDTH                      1
+#define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK                      0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT                     24
+#define SIM_SCGC6_FTM0_WIDTH                     1
+#define SIM_SCGC6_FTM0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM0_SHIFT))&SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK                      0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT                     25
+#define SIM_SCGC6_FTM1_WIDTH                     1
+#define SIM_SCGC6_FTM1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM1_SHIFT))&SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM2_MASK                      0x4000000u
+#define SIM_SCGC6_FTM2_SHIFT                     26
+#define SIM_SCGC6_FTM2_WIDTH                     1
+#define SIM_SCGC6_FTM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM2_SHIFT))&SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_ADC0_MASK                      0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT                     27
+#define SIM_SCGC6_ADC0_WIDTH                     1
+#define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK                       0x20000000u
+#define SIM_SCGC6_RTC_SHIFT                      29
+#define SIM_SCGC6_RTC_WIDTH                      1
+#define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK                      0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT                     31
+#define SIM_SCGC6_DAC0_WIDTH                     1
+#define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_FLEXBUS_MASK                   0x1u
+#define SIM_SCGC7_FLEXBUS_SHIFT                  0
+#define SIM_SCGC7_FLEXBUS_WIDTH                  1
+#define SIM_SCGC7_FLEXBUS(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_FLEXBUS_SHIFT))&SIM_SCGC7_FLEXBUS_MASK)
+#define SIM_SCGC7_DMA_MASK                       0x2u
+#define SIM_SCGC7_DMA_SHIFT                      1
+#define SIM_SCGC7_DMA_WIDTH                      1
+#define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_MPU_MASK                       0x4u
+#define SIM_SCGC7_MPU_SHIFT                      2
+#define SIM_SCGC7_MPU_WIDTH                      1
+#define SIM_SCGC7_MPU(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_MPU_SHIFT))&SIM_SCGC7_MPU_MASK)
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
+#define SIM_CLKDIV1_OUTDIV4_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK                 0xF00000u
+#define SIM_CLKDIV1_OUTDIV3_SHIFT                20
+#define SIM_CLKDIV1_OUTDIV3_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV3(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK                 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT                24
+#define SIM_CLKDIV1_OUTDIV2_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
+#define SIM_CLKDIV1_OUTDIV1_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK                 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT                0
+#define SIM_CLKDIV2_USBFRAC_WIDTH                1
+#define SIM_CLKDIV2_USBFRAC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBFRAC_SHIFT))&SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK                  0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT                 1
+#define SIM_CLKDIV2_USBDIV_WIDTH                 3
+#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK                  0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT                 0
+#define SIM_FCFG1_FLASHDIS_WIDTH                 1
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT                1
+#define SIM_FCFG1_FLASHDOZE_WIDTH                1
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_DEPART_MASK                    0xF00u
+#define SIM_FCFG1_DEPART_SHIFT                   8
+#define SIM_FCFG1_DEPART_WIDTH                   4
+#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK                    0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT                   16
+#define SIM_FCFG1_EESIZE_WIDTH                   4
+#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT                   24
+#define SIM_FCFG1_PFSIZE_WIDTH                   4
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK                   0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT                  28
+#define SIM_FCFG1_NVMSIZE_WIDTH                  4
+#define SIM_FCFG1_NVMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK                  0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT                 16
+#define SIM_FCFG2_MAXADDR1_WIDTH                 7
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK                     0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT                    23
+#define SIM_FCFG2_PFLSH_WIDTH                    1
+#define SIM_FCFG2_PFLSH(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_PFLSH_SHIFT))&SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK                  0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT                 24
+#define SIM_FCFG2_MAXADDR0_WIDTH                 7
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT                       0
+#define SIM_UIDH_UID_WIDTH                       32
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT                      0
+#define SIM_UIDMH_UID_WIDTH                      32
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT                      0
+#define SIM_UIDML_UID_WIDTH                      32
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT                       0
+#define SIM_UIDL_UID_WIDTH                       32
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR                             (SIM)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1                                SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG                             SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2                                SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4                                SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5                                SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7                                SIM_SOPT7_REG(SIM)
+#define SIM_SDID                                 SIM_SDID_REG(SIM)
+#define SIM_SCGC1                                SIM_SCGC1_REG(SIM)
+#define SIM_SCGC2                                SIM_SCGC2_REG(SIM)
+#define SIM_SCGC3                                SIM_SCGC3_REG(SIM)
+#define SIM_SCGC4                                SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5                                SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6                                SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7                                SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1                              SIM_CLKDIV1_REG(SIM)
+#define SIM_CLKDIV2                              SIM_CLKDIV2_REG(SIM)
+#define SIM_FCFG1                                SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2                                SIM_FCFG2_REG(SIM)
+#define SIM_UIDH                                 SIM_UIDH_REG(SIM)
+#define SIM_UIDMH                                SIM_UIDMH_REG(SIM)
+#define SIM_UIDML                                SIM_UIDML_REG(SIM)
+#define SIM_UIDL                                 SIM_UIDL_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t VLLSCTRL;                           /**< VLLS Control register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base)                     ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base)                     ((base)->PMCTRL)
+#define SMC_VLLSCTRL_REG(base)                   ((base)->VLLSCTRL)
+#define SMC_PMSTAT_REG(base)                     ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK                    0x2u
+#define SMC_PMPROT_AVLLS_SHIFT                   1
+#define SMC_PMPROT_AVLLS_WIDTH                   1
+#define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK                     0x8u
+#define SMC_PMPROT_ALLS_SHIFT                    3
+#define SMC_PMPROT_ALLS_WIDTH                    1
+#define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK                     0x20u
+#define SMC_PMPROT_AVLP_SHIFT                    5
+#define SMC_PMPROT_AVLP_WIDTH                    1
+#define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK                    0x7u
+#define SMC_PMCTRL_STOPM_SHIFT                   0
+#define SMC_PMCTRL_STOPM_WIDTH                   3
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK                    0x8u
+#define SMC_PMCTRL_STOPA_SHIFT                   3
+#define SMC_PMCTRL_STOPA_WIDTH                   1
+#define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK                     0x60u
+#define SMC_PMCTRL_RUNM_SHIFT                    5
+#define SMC_PMCTRL_RUNM_WIDTH                    2
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK                    0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT                   7
+#define SMC_PMCTRL_LPWUI_WIDTH                   1
+#define SMC_PMCTRL_LPWUI(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_LPWUI_SHIFT))&SMC_PMCTRL_LPWUI_MASK)
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK                  0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT                 0
+#define SMC_VLLSCTRL_VLLSM_WIDTH                 3
+#define SMC_VLLSCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK                  0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT                 5
+#define SMC_VLLSCTRL_PORPO_WIDTH                 1
+#define SMC_VLLSCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_PORPO_SHIFT))&SMC_VLLSCTRL_PORPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK                   0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT                  0
+#define SMC_PMSTAT_PMSTAT_WIDTH                  7
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR                             (SMC)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC }
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT                               SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL                               SMC_PMCTRL_REG(SMC)
+#define SMC_VLLSCTRL                             SMC_VLLSCTRL_REG(SMC)
+#define SMC_PMSTAT                               SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+    __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+  };
+       uint8_t RESERVED_1[24];
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
+  __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+  union {                                          /* offset: 0x34 */
+    __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+    __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+  };
+  __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
+  __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
+  __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
+  __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
+  __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
+       uint8_t RESERVED_2[48];
+  __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
+  __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
+  __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
+  __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_MCR_REG(base)                        ((base)->MCR)
+#define SPI_TCR_REG(base)                        ((base)->TCR)
+#define SPI_CTAR_REG(base,index2)                ((base)->CTAR[index2])
+#define SPI_CTAR_COUNT                           2
+#define SPI_CTAR_SLAVE_REG(base,index2)          ((base)->CTAR_SLAVE[index2])
+#define SPI_CTAR_SLAVE_COUNT                     1
+#define SPI_SR_REG(base)                         ((base)->SR)
+#define SPI_RSER_REG(base)                       ((base)->RSER)
+#define SPI_PUSHR_REG(base)                      ((base)->PUSHR)
+#define SPI_PUSHR_SLAVE_REG(base)                ((base)->PUSHR_SLAVE)
+#define SPI_POPR_REG(base)                       ((base)->POPR)
+#define SPI_TXFR0_REG(base)                      ((base)->TXFR0)
+#define SPI_TXFR1_REG(base)                      ((base)->TXFR1)
+#define SPI_TXFR2_REG(base)                      ((base)->TXFR2)
+#define SPI_TXFR3_REG(base)                      ((base)->TXFR3)
+#define SPI_RXFR0_REG(base)                      ((base)->RXFR0)
+#define SPI_RXFR1_REG(base)                      ((base)->RXFR1)
+#define SPI_RXFR2_REG(base)                      ((base)->RXFR2)
+#define SPI_RXFR3_REG(base)                      ((base)->RXFR3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK                        0x1u
+#define SPI_MCR_HALT_SHIFT                       0
+#define SPI_MCR_HALT_WIDTH                       1
+#define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_HALT_SHIFT))&SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK                     0x300u
+#define SPI_MCR_SMPL_PT_SHIFT                    8
+#define SPI_MCR_SMPL_PT_WIDTH                    2
+#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK                     0x400u
+#define SPI_MCR_CLR_RXF_SHIFT                    10
+#define SPI_MCR_CLR_RXF_WIDTH                    1
+#define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_RXF_SHIFT))&SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK                     0x800u
+#define SPI_MCR_CLR_TXF_SHIFT                    11
+#define SPI_MCR_CLR_TXF_WIDTH                    1
+#define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_TXF_SHIFT))&SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK                     0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT                    12
+#define SPI_MCR_DIS_RXF_WIDTH                    1
+#define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_RXF_SHIFT))&SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK                     0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT                    13
+#define SPI_MCR_DIS_TXF_WIDTH                    1
+#define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_TXF_SHIFT))&SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK                        0x4000u
+#define SPI_MCR_MDIS_SHIFT                       14
+#define SPI_MCR_MDIS_WIDTH                       1
+#define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MDIS_SHIFT))&SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK                        0x8000u
+#define SPI_MCR_DOZE_SHIFT                       15
+#define SPI_MCR_DOZE_WIDTH                       1
+#define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DOZE_SHIFT))&SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK                       0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT                      16
+#define SPI_MCR_PCSIS_WIDTH                      6
+#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK                        0x1000000u
+#define SPI_MCR_ROOE_SHIFT                       24
+#define SPI_MCR_ROOE_WIDTH                       1
+#define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_ROOE_SHIFT))&SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK                       0x2000000u
+#define SPI_MCR_PCSSE_SHIFT                      25
+#define SPI_MCR_PCSSE_WIDTH                      1
+#define SPI_MCR_PCSSE(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSSE_SHIFT))&SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK                        0x4000000u
+#define SPI_MCR_MTFE_SHIFT                       26
+#define SPI_MCR_MTFE_WIDTH                       1
+#define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MTFE_SHIFT))&SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK                         0x8000000u
+#define SPI_MCR_FRZ_SHIFT                        27
+#define SPI_MCR_FRZ_WIDTH                        1
+#define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_MCR_FRZ_SHIFT))&SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK                       0x30000000u
+#define SPI_MCR_DCONF_SHIFT                      28
+#define SPI_MCR_DCONF_WIDTH                      2
+#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK                   0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT                  30
+#define SPI_MCR_CONT_SCKE_WIDTH                  1
+#define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CONT_SCKE_SHIFT))&SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK                        0x80000000u
+#define SPI_MCR_MSTR_SHIFT                       31
+#define SPI_MCR_MSTR_WIDTH                       1
+#define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MSTR_SHIFT))&SPI_MCR_MSTR_MASK)
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK                    0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT                   16
+#define SPI_TCR_SPI_TCNT_WIDTH                   16
+#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK                         0xFu
+#define SPI_CTAR_BR_SHIFT                        0
+#define SPI_CTAR_BR_WIDTH                        4
+#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK                         0xF0u
+#define SPI_CTAR_DT_SHIFT                        4
+#define SPI_CTAR_DT_WIDTH                        4
+#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK                        0xF00u
+#define SPI_CTAR_ASC_SHIFT                       8
+#define SPI_CTAR_ASC_WIDTH                       4
+#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK                      0xF000u
+#define SPI_CTAR_CSSCK_SHIFT                     12
+#define SPI_CTAR_CSSCK_WIDTH                     4
+#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK                        0x30000u
+#define SPI_CTAR_PBR_SHIFT                       16
+#define SPI_CTAR_PBR_WIDTH                       2
+#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK                        0xC0000u
+#define SPI_CTAR_PDT_SHIFT                       18
+#define SPI_CTAR_PDT_WIDTH                       2
+#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK                       0x300000u
+#define SPI_CTAR_PASC_SHIFT                      20
+#define SPI_CTAR_PASC_WIDTH                      2
+#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK                     0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT                    22
+#define SPI_CTAR_PCSSCK_WIDTH                    2
+#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK                      0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT                     24
+#define SPI_CTAR_LSBFE_WIDTH                     1
+#define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_LSBFE_SHIFT))&SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK                       0x2000000u
+#define SPI_CTAR_CPHA_SHIFT                      25
+#define SPI_CTAR_CPHA_WIDTH                      1
+#define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPHA_SHIFT))&SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK                       0x4000000u
+#define SPI_CTAR_CPOL_SHIFT                      26
+#define SPI_CTAR_CPOL_WIDTH                      1
+#define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPOL_SHIFT))&SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK                       0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT                      27
+#define SPI_CTAR_FMSZ_WIDTH                      4
+#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK                        0x80000000u
+#define SPI_CTAR_DBR_SHIFT                       31
+#define SPI_CTAR_DBR_WIDTH                       1
+#define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DBR_SHIFT))&SPI_CTAR_DBR_MASK)
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK                 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT                25
+#define SPI_CTAR_SLAVE_CPHA_WIDTH                1
+#define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPHA_SHIFT))&SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK                 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT                26
+#define SPI_CTAR_SLAVE_CPOL_WIDTH                1
+#define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPOL_SHIFT))&SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK                 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT                27
+#define SPI_CTAR_SLAVE_FMSZ_WIDTH                5
+#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK                    0xFu
+#define SPI_SR_POPNXTPTR_SHIFT                   0
+#define SPI_SR_POPNXTPTR_WIDTH                   4
+#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK                        0xF0u
+#define SPI_SR_RXCTR_SHIFT                       4
+#define SPI_SR_RXCTR_WIDTH                       4
+#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK                     0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT                    8
+#define SPI_SR_TXNXTPTR_WIDTH                    4
+#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK                        0xF000u
+#define SPI_SR_TXCTR_SHIFT                       12
+#define SPI_SR_TXCTR_WIDTH                       4
+#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK                         0x20000u
+#define SPI_SR_RFDF_SHIFT                        17
+#define SPI_SR_RFDF_WIDTH                        1
+#define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFDF_SHIFT))&SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK                         0x80000u
+#define SPI_SR_RFOF_SHIFT                        19
+#define SPI_SR_RFOF_WIDTH                        1
+#define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFOF_SHIFT))&SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK                         0x2000000u
+#define SPI_SR_TFFF_SHIFT                        25
+#define SPI_SR_TFFF_WIDTH                        1
+#define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK                         0x8000000u
+#define SPI_SR_TFUF_SHIFT                        27
+#define SPI_SR_TFUF_WIDTH                        1
+#define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFUF_SHIFT))&SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK                         0x10000000u
+#define SPI_SR_EOQF_SHIFT                        28
+#define SPI_SR_EOQF_WIDTH                        1
+#define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_EOQF_SHIFT))&SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK                        0x40000000u
+#define SPI_SR_TXRXS_SHIFT                       30
+#define SPI_SR_TXRXS_WIDTH                       1
+#define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXRXS_SHIFT))&SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK                          0x80000000u
+#define SPI_SR_TCF_SHIFT                         31
+#define SPI_SR_TCF_WIDTH                         1
+#define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x))<<SPI_SR_TCF_SHIFT))&SPI_SR_TCF_MASK)
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK                  0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT                 16
+#define SPI_RSER_RFDF_DIRS_WIDTH                 1
+#define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_DIRS_SHIFT))&SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK                    0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT                   17
+#define SPI_RSER_RFDF_RE_WIDTH                   1
+#define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_RE_SHIFT))&SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK                    0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT                   19
+#define SPI_RSER_RFOF_RE_WIDTH                   1
+#define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFOF_RE_SHIFT))&SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK                  0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT                 24
+#define SPI_RSER_TFFF_DIRS_WIDTH                 1
+#define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_DIRS_SHIFT))&SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK                    0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT                   25
+#define SPI_RSER_TFFF_RE_WIDTH                   1
+#define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK                    0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT                   27
+#define SPI_RSER_TFUF_RE_WIDTH                   1
+#define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFUF_RE_SHIFT))&SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK                    0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT                   28
+#define SPI_RSER_EOQF_RE_WIDTH                   1
+#define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_EOQF_RE_SHIFT))&SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK                     0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT                    31
+#define SPI_RSER_TCF_RE_WIDTH                    1
+#define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TCF_RE_SHIFT))&SPI_RSER_TCF_RE_MASK)
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK                    0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT                   0
+#define SPI_PUSHR_TXDATA_WIDTH                   16
+#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK                       0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT                      16
+#define SPI_PUSHR_PCS_WIDTH                      6
+#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK                     0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT                    26
+#define SPI_PUSHR_CTCNT_WIDTH                    1
+#define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTCNT_SHIFT))&SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK                       0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT                      27
+#define SPI_PUSHR_EOQ_WIDTH                      1
+#define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_EOQ_SHIFT))&SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK                      0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT                     28
+#define SPI_PUSHR_CTAS_WIDTH                     3
+#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK                      0x80000000u
+#define SPI_PUSHR_CONT_SHIFT                     31
+#define SPI_PUSHR_CONT_WIDTH                     1
+#define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CONT_SHIFT))&SPI_PUSHR_CONT_MASK)
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK              0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             0
+#define SPI_PUSHR_SLAVE_TXDATA_WIDTH             32
+#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK                     0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT                    0
+#define SPI_POPR_RXDATA_WIDTH                    32
+#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT                   0
+#define SPI_TXFR0_TXDATA_WIDTH                   16
+#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR0_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT                   0
+#define SPI_TXFR1_TXDATA_WIDTH                   16
+#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR1_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT                   0
+#define SPI_TXFR2_TXDATA_WIDTH                   16
+#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR2_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT                   0
+#define SPI_TXFR3_TXDATA_WIDTH                   16
+#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR3_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT                   0
+#define SPI_RXFR0_RXDATA_WIDTH                   32
+#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT                   0
+#define SPI_RXFR1_RXDATA_WIDTH                   32
+#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT                   0
+#define SPI_RXFR2_RXDATA_WIDTH                   32
+#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT                   0
+#define SPI_RXFR3_RXDATA_WIDTH                   32
+#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR                            (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR                            (SPI1)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x400AC000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+#define SPI2_BASE_PTR                            (SPI2)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_MCR                                 SPI_MCR_REG(SPI0)
+#define SPI0_TCR                                 SPI_TCR_REG(SPI0)
+#define SPI0_CTAR0                               SPI_CTAR_REG(SPI0,0)
+#define SPI0_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI0,0)
+#define SPI0_CTAR1                               SPI_CTAR_REG(SPI0,1)
+#define SPI0_SR                                  SPI_SR_REG(SPI0)
+#define SPI0_RSER                                SPI_RSER_REG(SPI0)
+#define SPI0_PUSHR                               SPI_PUSHR_REG(SPI0)
+#define SPI0_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI0)
+#define SPI0_POPR                                SPI_POPR_REG(SPI0)
+#define SPI0_TXFR0                               SPI_TXFR0_REG(SPI0)
+#define SPI0_TXFR1                               SPI_TXFR1_REG(SPI0)
+#define SPI0_TXFR2                               SPI_TXFR2_REG(SPI0)
+#define SPI0_TXFR3                               SPI_TXFR3_REG(SPI0)
+#define SPI0_RXFR0                               SPI_RXFR0_REG(SPI0)
+#define SPI0_RXFR1                               SPI_RXFR1_REG(SPI0)
+#define SPI0_RXFR2                               SPI_RXFR2_REG(SPI0)
+#define SPI0_RXFR3                               SPI_RXFR3_REG(SPI0)
+/* SPI1 */
+#define SPI1_MCR                                 SPI_MCR_REG(SPI1)
+#define SPI1_TCR                                 SPI_TCR_REG(SPI1)
+#define SPI1_CTAR0                               SPI_CTAR_REG(SPI1,0)
+#define SPI1_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI1,0)
+#define SPI1_CTAR1                               SPI_CTAR_REG(SPI1,1)
+#define SPI1_SR                                  SPI_SR_REG(SPI1)
+#define SPI1_RSER                                SPI_RSER_REG(SPI1)
+#define SPI1_PUSHR                               SPI_PUSHR_REG(SPI1)
+#define SPI1_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI1)
+#define SPI1_POPR                                SPI_POPR_REG(SPI1)
+#define SPI1_TXFR0                               SPI_TXFR0_REG(SPI1)
+#define SPI1_TXFR1                               SPI_TXFR1_REG(SPI1)
+#define SPI1_TXFR2                               SPI_TXFR2_REG(SPI1)
+#define SPI1_TXFR3                               SPI_TXFR3_REG(SPI1)
+#define SPI1_RXFR0                               SPI_RXFR0_REG(SPI1)
+#define SPI1_RXFR1                               SPI_RXFR1_REG(SPI1)
+#define SPI1_RXFR2                               SPI_RXFR2_REG(SPI1)
+#define SPI1_RXFR3                               SPI_RXFR3_REG(SPI1)
+/* SPI2 */
+#define SPI2_MCR                                 SPI_MCR_REG(SPI2)
+#define SPI2_TCR                                 SPI_TCR_REG(SPI2)
+#define SPI2_CTAR0                               SPI_CTAR_REG(SPI2,0)
+#define SPI2_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI2,0)
+#define SPI2_CTAR1                               SPI_CTAR_REG(SPI2,1)
+#define SPI2_SR                                  SPI_SR_REG(SPI2)
+#define SPI2_RSER                                SPI_RSER_REG(SPI2)
+#define SPI2_PUSHR                               SPI_PUSHR_REG(SPI2)
+#define SPI2_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI2)
+#define SPI2_POPR                                SPI_POPR_REG(SPI2)
+#define SPI2_TXFR0                               SPI_TXFR0_REG(SPI2)
+#define SPI2_TXFR1                               SPI_TXFR1_REG(SPI2)
+#define SPI2_TXFR2                               SPI_TXFR2_REG(SPI2)
+#define SPI2_TXFR3                               SPI_TXFR3_REG(SPI2)
+#define SPI2_RXFR0                               SPI_RXFR0_REG(SPI2)
+#define SPI2_RXFR1                               SPI_RXFR1_REG(SPI2)
+#define SPI2_RXFR2                               SPI_RXFR2_REG(SPI2)
+#define SPI2_RXFR3                               SPI_RXFR3_REG(SPI2)
+
+/* SPI - Register array accessors */
+#define SPI0_CTAR(index2)                        SPI_CTAR_REG(SPI0,index2)
+#define SPI1_CTAR(index2)                        SPI_CTAR_REG(SPI1,index2)
+#define SPI2_CTAR(index2)                        SPI_CTAR_REG(SPI2,index2)
+#define SPI0_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI0,index2)
+#define SPI1_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI1,index2)
+#define SPI2_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI2,index2)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
+  __I  uint8_t ED;                                 /**< UART Extended Data Register, offset: 0xC */
+  __IO uint8_t MODEM;                              /**< UART Modem Register, offset: 0xD */
+  __IO uint8_t IR;                                 /**< UART Infrared Register, offset: 0xE */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t PFIFO;                              /**< UART FIFO Parameters, offset: 0x10 */
+  __IO uint8_t CFIFO;                              /**< UART FIFO Control Register, offset: 0x11 */
+  __IO uint8_t SFIFO;                              /**< UART FIFO Status Register, offset: 0x12 */
+  __IO uint8_t TWFIFO;                             /**< UART FIFO Transmit Watermark, offset: 0x13 */
+  __I  uint8_t TCFIFO;                             /**< UART FIFO Transmit Count, offset: 0x14 */
+  __IO uint8_t RWFIFO;                             /**< UART FIFO Receive Watermark, offset: 0x15 */
+  __I  uint8_t RCFIFO;                             /**< UART FIFO Receive Count, offset: 0x16 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
+  __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+  __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+  union {                                          /* offset: 0x1B */
+    __IO uint8_t WP7816T0;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+    __IO uint8_t WP7816T1;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+  };
+  __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
+  __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
+  __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
+  __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base)                       ((base)->BDH)
+#define UART_BDL_REG(base)                       ((base)->BDL)
+#define UART_C1_REG(base)                        ((base)->C1)
+#define UART_C2_REG(base)                        ((base)->C2)
+#define UART_S1_REG(base)                        ((base)->S1)
+#define UART_S2_REG(base)                        ((base)->S2)
+#define UART_C3_REG(base)                        ((base)->C3)
+#define UART_D_REG(base)                         ((base)->D)
+#define UART_MA1_REG(base)                       ((base)->MA1)
+#define UART_MA2_REG(base)                       ((base)->MA2)
+#define UART_C4_REG(base)                        ((base)->C4)
+#define UART_C5_REG(base)                        ((base)->C5)
+#define UART_ED_REG(base)                        ((base)->ED)
+#define UART_MODEM_REG(base)                     ((base)->MODEM)
+#define UART_IR_REG(base)                        ((base)->IR)
+#define UART_PFIFO_REG(base)                     ((base)->PFIFO)
+#define UART_CFIFO_REG(base)                     ((base)->CFIFO)
+#define UART_SFIFO_REG(base)                     ((base)->SFIFO)
+#define UART_TWFIFO_REG(base)                    ((base)->TWFIFO)
+#define UART_TCFIFO_REG(base)                    ((base)->TCFIFO)
+#define UART_RWFIFO_REG(base)                    ((base)->RWFIFO)
+#define UART_RCFIFO_REG(base)                    ((base)->RCFIFO)
+#define UART_C7816_REG(base)                     ((base)->C7816)
+#define UART_IE7816_REG(base)                    ((base)->IE7816)
+#define UART_IS7816_REG(base)                    ((base)->IS7816)
+#define UART_WP7816T0_REG(base)                  ((base)->WP7816T0)
+#define UART_WP7816T1_REG(base)                  ((base)->WP7816T1)
+#define UART_WN7816_REG(base)                    ((base)->WN7816)
+#define UART_WF7816_REG(base)                    ((base)->WF7816)
+#define UART_ET7816_REG(base)                    ((base)->ET7816)
+#define UART_TL7816_REG(base)                    ((base)->TL7816)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK                        0x1Fu
+#define UART_BDH_SBR_SHIFT                       0
+#define UART_BDH_SBR_WIDTH                       5
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK                       0x20u
+#define UART_BDH_SBNS_SHIFT                      5
+#define UART_BDH_SBNS_WIDTH                      1
+#define UART_BDH_SBNS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBNS_SHIFT))&UART_BDH_SBNS_MASK)
+#define UART_BDH_RXEDGIE_MASK                    0x40u
+#define UART_BDH_RXEDGIE_SHIFT                   6
+#define UART_BDH_RXEDGIE_WIDTH                   1
+#define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK                     0x80u
+#define UART_BDH_LBKDIE_SHIFT                    7
+#define UART_BDH_LBKDIE_WIDTH                    1
+#define UART_BDH_LBKDIE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_BDH_LBKDIE_SHIFT))&UART_BDH_LBKDIE_MASK)
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK                        0xFFu
+#define UART_BDL_SBR_SHIFT                       0
+#define UART_BDL_SBR_WIDTH                       8
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK                          0x1u
+#define UART_C1_PT_SHIFT                         0
+#define UART_C1_PT_WIDTH                         1
+#define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
+#define UART_C1_PE_MASK                          0x2u
+#define UART_C1_PE_SHIFT                         1
+#define UART_C1_PE_WIDTH                         1
+#define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK                         0x4u
+#define UART_C1_ILT_SHIFT                        2
+#define UART_C1_ILT_WIDTH                        1
+#define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK                        0x8u
+#define UART_C1_WAKE_SHIFT                       3
+#define UART_C1_WAKE_WIDTH                       1
+#define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK                           0x10u
+#define UART_C1_M_SHIFT                          4
+#define UART_C1_M_WIDTH                          1
+#define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK                        0x20u
+#define UART_C1_RSRC_SHIFT                       5
+#define UART_C1_RSRC_WIDTH                       1
+#define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK                    0x40u
+#define UART_C1_UARTSWAI_SHIFT                   6
+#define UART_C1_UARTSWAI_WIDTH                   1
+#define UART_C1_UARTSWAI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C1_UARTSWAI_SHIFT))&UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK                       0x80u
+#define UART_C1_LOOPS_SHIFT                      7
+#define UART_C1_LOOPS_WIDTH                      1
+#define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK                         0x1u
+#define UART_C2_SBK_SHIFT                        0
+#define UART_C2_SBK_WIDTH                        1
+#define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK                         0x2u
+#define UART_C2_RWU_SHIFT                        1
+#define UART_C2_RWU_WIDTH                        1
+#define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK                          0x4u
+#define UART_C2_RE_SHIFT                         2
+#define UART_C2_RE_WIDTH                         1
+#define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
+#define UART_C2_TE_MASK                          0x8u
+#define UART_C2_TE_SHIFT                         3
+#define UART_C2_TE_WIDTH                         1
+#define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK                        0x10u
+#define UART_C2_ILIE_SHIFT                       4
+#define UART_C2_ILIE_WIDTH                       1
+#define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK                         0x20u
+#define UART_C2_RIE_SHIFT                        5
+#define UART_C2_RIE_WIDTH                        1
+#define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK                        0x40u
+#define UART_C2_TCIE_SHIFT                       6
+#define UART_C2_TCIE_WIDTH                       1
+#define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK                         0x80u
+#define UART_C2_TIE_SHIFT                        7
+#define UART_C2_TIE_WIDTH                        1
+#define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK                          0x1u
+#define UART_S1_PF_SHIFT                         0
+#define UART_S1_PF_WIDTH                         1
+#define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
+#define UART_S1_FE_MASK                          0x2u
+#define UART_S1_FE_SHIFT                         1
+#define UART_S1_FE_WIDTH                         1
+#define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
+#define UART_S1_NF_MASK                          0x4u
+#define UART_S1_NF_SHIFT                         2
+#define UART_S1_NF_WIDTH                         1
+#define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
+#define UART_S1_OR_MASK                          0x8u
+#define UART_S1_OR_SHIFT                         3
+#define UART_S1_OR_WIDTH                         1
+#define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK                        0x10u
+#define UART_S1_IDLE_SHIFT                       4
+#define UART_S1_IDLE_WIDTH                       1
+#define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK                        0x20u
+#define UART_S1_RDRF_SHIFT                       5
+#define UART_S1_RDRF_WIDTH                       1
+#define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK                          0x40u
+#define UART_S1_TC_SHIFT                         6
+#define UART_S1_TC_WIDTH                         1
+#define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK                        0x80u
+#define UART_S1_TDRE_SHIFT                       7
+#define UART_S1_TDRE_WIDTH                       1
+#define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK                         0x1u
+#define UART_S2_RAF_SHIFT                        0
+#define UART_S2_RAF_WIDTH                        1
+#define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK                       0x2u
+#define UART_S2_LBKDE_SHIFT                      1
+#define UART_S2_LBKDE_WIDTH                      1
+#define UART_S2_LBKDE(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDE_SHIFT))&UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK                       0x4u
+#define UART_S2_BRK13_SHIFT                      2
+#define UART_S2_BRK13_WIDTH                      1
+#define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK                       0x8u
+#define UART_S2_RWUID_SHIFT                      3
+#define UART_S2_RWUID_WIDTH                      1
+#define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK                       0x10u
+#define UART_S2_RXINV_SHIFT                      4
+#define UART_S2_RXINV_WIDTH                      1
+#define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK                        0x20u
+#define UART_S2_MSBF_SHIFT                       5
+#define UART_S2_MSBF_WIDTH                       1
+#define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S2_MSBF_SHIFT))&UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK                     0x40u
+#define UART_S2_RXEDGIF_SHIFT                    6
+#define UART_S2_RXEDGIF_WIDTH                    1
+#define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK                      0x80u
+#define UART_S2_LBKDIF_SHIFT                     7
+#define UART_S2_LBKDIF_WIDTH                     1
+#define UART_S2_LBKDIF(x)                        (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDIF_SHIFT))&UART_S2_LBKDIF_MASK)
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK                        0x1u
+#define UART_C3_PEIE_SHIFT                       0
+#define UART_C3_PEIE_WIDTH                       1
+#define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK                        0x2u
+#define UART_C3_FEIE_SHIFT                       1
+#define UART_C3_FEIE_WIDTH                       1
+#define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK                        0x4u
+#define UART_C3_NEIE_SHIFT                       2
+#define UART_C3_NEIE_WIDTH                       1
+#define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK                        0x8u
+#define UART_C3_ORIE_SHIFT                       3
+#define UART_C3_ORIE_WIDTH                       1
+#define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK                       0x10u
+#define UART_C3_TXINV_SHIFT                      4
+#define UART_C3_TXINV_WIDTH                      1
+#define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK                       0x20u
+#define UART_C3_TXDIR_SHIFT                      5
+#define UART_C3_TXDIR_WIDTH                      1
+#define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK                          0x40u
+#define UART_C3_T8_SHIFT                         6
+#define UART_C3_T8_WIDTH                         1
+#define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
+#define UART_C3_R8_MASK                          0x80u
+#define UART_C3_R8_SHIFT                         7
+#define UART_C3_R8_WIDTH                         1
+#define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
+/* D Bit Fields */
+#define UART_D_RT_MASK                           0xFFu
+#define UART_D_RT_SHIFT                          0
+#define UART_D_RT_WIDTH                          8
+#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK                         0xFFu
+#define UART_MA1_MA_SHIFT                        0
+#define UART_MA1_MA_WIDTH                        8
+#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK                         0xFFu
+#define UART_MA2_MA_SHIFT                        0
+#define UART_MA2_MA_WIDTH                        8
+#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK                        0x1Fu
+#define UART_C4_BRFA_SHIFT                       0
+#define UART_C4_BRFA_WIDTH                       5
+#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK                         0x20u
+#define UART_C4_M10_SHIFT                        5
+#define UART_C4_M10_WIDTH                        1
+#define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C4_M10_SHIFT))&UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK                       0x40u
+#define UART_C4_MAEN2_SHIFT                      6
+#define UART_C4_MAEN2_WIDTH                      1
+#define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN2_SHIFT))&UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK                       0x80u
+#define UART_C4_MAEN1_SHIFT                      7
+#define UART_C4_MAEN1_WIDTH                      1
+#define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN1_SHIFT))&UART_C4_MAEN1_MASK)
+/* C5 Bit Fields */
+#define UART_C5_LBKDDMAS_MASK                    0x8u
+#define UART_C5_LBKDDMAS_SHIFT                   3
+#define UART_C5_LBKDDMAS_WIDTH                   1
+#define UART_C5_LBKDDMAS(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C5_LBKDDMAS_SHIFT))&UART_C5_LBKDDMAS_MASK)
+#define UART_C5_ILDMAS_MASK                      0x10u
+#define UART_C5_ILDMAS_SHIFT                     4
+#define UART_C5_ILDMAS_WIDTH                     1
+#define UART_C5_ILDMAS(x)                        (((uint8_t)(((uint8_t)(x))<<UART_C5_ILDMAS_SHIFT))&UART_C5_ILDMAS_MASK)
+#define UART_C5_RDMAS_MASK                       0x20u
+#define UART_C5_RDMAS_SHIFT                      5
+#define UART_C5_RDMAS_WIDTH                      1
+#define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_RDMAS_SHIFT))&UART_C5_RDMAS_MASK)
+#define UART_C5_TCDMAS_MASK                      0x40u
+#define UART_C5_TCDMAS_SHIFT                     6
+#define UART_C5_TCDMAS_WIDTH                     1
+#define UART_C5_TCDMAS(x)                        (((uint8_t)(((uint8_t)(x))<<UART_C5_TCDMAS_SHIFT))&UART_C5_TCDMAS_MASK)
+#define UART_C5_TDMAS_MASK                       0x80u
+#define UART_C5_TDMAS_SHIFT                      7
+#define UART_C5_TDMAS_WIDTH                      1
+#define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_TDMAS_SHIFT))&UART_C5_TDMAS_MASK)
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK                     0x40u
+#define UART_ED_PARITYE_SHIFT                    6
+#define UART_ED_PARITYE_WIDTH                    1
+#define UART_ED_PARITYE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_ED_PARITYE_SHIFT))&UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK                       0x80u
+#define UART_ED_NOISY_SHIFT                      7
+#define UART_ED_NOISY_WIDTH                      1
+#define UART_ED_NOISY(x)                         (((uint8_t)(((uint8_t)(x))<<UART_ED_NOISY_SHIFT))&UART_ED_NOISY_MASK)
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK                   0x1u
+#define UART_MODEM_TXCTSE_SHIFT                  0
+#define UART_MODEM_TXCTSE_WIDTH                  1
+#define UART_MODEM_TXCTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXCTSE_SHIFT))&UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK                   0x2u
+#define UART_MODEM_TXRTSE_SHIFT                  1
+#define UART_MODEM_TXRTSE_WIDTH                  1
+#define UART_MODEM_TXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSE_SHIFT))&UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK                 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT                2
+#define UART_MODEM_TXRTSPOL_WIDTH                1
+#define UART_MODEM_TXRTSPOL(x)                   (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSPOL_SHIFT))&UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK                   0x8u
+#define UART_MODEM_RXRTSE_SHIFT                  3
+#define UART_MODEM_RXRTSE_WIDTH                  1
+#define UART_MODEM_RXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_RXRTSE_SHIFT))&UART_MODEM_RXRTSE_MASK)
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK                         0x3u
+#define UART_IR_TNP_SHIFT                        0
+#define UART_IR_TNP_WIDTH                        2
+#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK                        0x4u
+#define UART_IR_IREN_SHIFT                       2
+#define UART_IR_IREN_WIDTH                       1
+#define UART_IR_IREN(x)                          (((uint8_t)(((uint8_t)(x))<<UART_IR_IREN_SHIFT))&UART_IR_IREN_MASK)
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK               0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT              0
+#define UART_PFIFO_RXFIFOSIZE_WIDTH              3
+#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK                     0x8u
+#define UART_PFIFO_RXFE_SHIFT                    3
+#define UART_PFIFO_RXFE_WIDTH                    1
+#define UART_PFIFO_RXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFE_SHIFT))&UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK               0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT              4
+#define UART_PFIFO_TXFIFOSIZE_WIDTH              3
+#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK                     0x80u
+#define UART_PFIFO_TXFE_SHIFT                    7
+#define UART_PFIFO_TXFE_WIDTH                    1
+#define UART_PFIFO_TXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFE_SHIFT))&UART_PFIFO_TXFE_MASK)
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK                    0x1u
+#define UART_CFIFO_RXUFE_SHIFT                   0
+#define UART_CFIFO_RXUFE_WIDTH                   1
+#define UART_CFIFO_RXUFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXUFE_SHIFT))&UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK                    0x2u
+#define UART_CFIFO_TXOFE_SHIFT                   1
+#define UART_CFIFO_TXOFE_WIDTH                   1
+#define UART_CFIFO_TXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXOFE_SHIFT))&UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXOFE_MASK                    0x4u
+#define UART_CFIFO_RXOFE_SHIFT                   2
+#define UART_CFIFO_RXOFE_WIDTH                   1
+#define UART_CFIFO_RXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXOFE_SHIFT))&UART_CFIFO_RXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK                  0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT                 6
+#define UART_CFIFO_RXFLUSH_WIDTH                 1
+#define UART_CFIFO_RXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXFLUSH_SHIFT))&UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK                  0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT                 7
+#define UART_CFIFO_TXFLUSH_WIDTH                 1
+#define UART_CFIFO_TXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXFLUSH_SHIFT))&UART_CFIFO_TXFLUSH_MASK)
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK                     0x1u
+#define UART_SFIFO_RXUF_SHIFT                    0
+#define UART_SFIFO_RXUF_WIDTH                    1
+#define UART_SFIFO_RXUF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXUF_SHIFT))&UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK                     0x2u
+#define UART_SFIFO_TXOF_SHIFT                    1
+#define UART_SFIFO_TXOF_WIDTH                    1
+#define UART_SFIFO_TXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXOF_SHIFT))&UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXOF_MASK                     0x4u
+#define UART_SFIFO_RXOF_SHIFT                    2
+#define UART_SFIFO_RXOF_WIDTH                    1
+#define UART_SFIFO_RXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXOF_SHIFT))&UART_SFIFO_RXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK                   0x40u
+#define UART_SFIFO_RXEMPT_SHIFT                  6
+#define UART_SFIFO_RXEMPT_WIDTH                  1
+#define UART_SFIFO_RXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXEMPT_SHIFT))&UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK                   0x80u
+#define UART_SFIFO_TXEMPT_SHIFT                  7
+#define UART_SFIFO_TXEMPT_WIDTH                  1
+#define UART_SFIFO_TXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXEMPT_SHIFT))&UART_SFIFO_TXEMPT_MASK)
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK                 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT                0
+#define UART_TWFIFO_TXWATER_WIDTH                8
+#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK                 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT                0
+#define UART_TCFIFO_TXCOUNT_WIDTH                8
+#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK                 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT                0
+#define UART_RWFIFO_RXWATER_WIDTH                8
+#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK                 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT                0
+#define UART_RCFIFO_RXCOUNT_WIDTH                8
+#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK                0x1u
+#define UART_C7816_ISO_7816E_SHIFT               0
+#define UART_C7816_ISO_7816E_WIDTH               1
+#define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x))<<UART_C7816_ISO_7816E_SHIFT))&UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK                    0x2u
+#define UART_C7816_TTYPE_SHIFT                   1
+#define UART_C7816_TTYPE_WIDTH                   1
+#define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_TTYPE_SHIFT))&UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK                     0x4u
+#define UART_C7816_INIT_SHIFT                    2
+#define UART_C7816_INIT_WIDTH                    1
+#define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_C7816_INIT_SHIFT))&UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK                    0x8u
+#define UART_C7816_ANACK_SHIFT                   3
+#define UART_C7816_ANACK_WIDTH                   1
+#define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ANACK_SHIFT))&UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK                    0x10u
+#define UART_C7816_ONACK_SHIFT                   4
+#define UART_C7816_ONACK_WIDTH                   1
+#define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ONACK_SHIFT))&UART_C7816_ONACK_MASK)
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK                    0x1u
+#define UART_IE7816_RXTE_SHIFT                   0
+#define UART_IE7816_RXTE_WIDTH                   1
+#define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_RXTE_SHIFT))&UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK                    0x2u
+#define UART_IE7816_TXTE_SHIFT                   1
+#define UART_IE7816_TXTE_WIDTH                   1
+#define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_TXTE_SHIFT))&UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK                    0x4u
+#define UART_IE7816_GTVE_SHIFT                   2
+#define UART_IE7816_GTVE_WIDTH                   1
+#define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_GTVE_SHIFT))&UART_IE7816_GTVE_MASK)
+#define UART_IE7816_INITDE_MASK                  0x10u
+#define UART_IE7816_INITDE_SHIFT                 4
+#define UART_IE7816_INITDE_WIDTH                 1
+#define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x))<<UART_IE7816_INITDE_SHIFT))&UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK                    0x20u
+#define UART_IE7816_BWTE_SHIFT                   5
+#define UART_IE7816_BWTE_WIDTH                   1
+#define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_BWTE_SHIFT))&UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK                    0x40u
+#define UART_IE7816_CWTE_SHIFT                   6
+#define UART_IE7816_CWTE_WIDTH                   1
+#define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_CWTE_SHIFT))&UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK                     0x80u
+#define UART_IE7816_WTE_SHIFT                    7
+#define UART_IE7816_WTE_WIDTH                    1
+#define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IE7816_WTE_SHIFT))&UART_IE7816_WTE_MASK)
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK                     0x1u
+#define UART_IS7816_RXT_SHIFT                    0
+#define UART_IS7816_RXT_WIDTH                    1
+#define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_RXT_SHIFT))&UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK                     0x2u
+#define UART_IS7816_TXT_SHIFT                    1
+#define UART_IS7816_TXT_WIDTH                    1
+#define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_TXT_SHIFT))&UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK                     0x4u
+#define UART_IS7816_GTV_SHIFT                    2
+#define UART_IS7816_GTV_WIDTH                    1
+#define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_GTV_SHIFT))&UART_IS7816_GTV_MASK)
+#define UART_IS7816_INITD_MASK                   0x10u
+#define UART_IS7816_INITD_SHIFT                  4
+#define UART_IS7816_INITD_WIDTH                  1
+#define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x))<<UART_IS7816_INITD_SHIFT))&UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK                     0x20u
+#define UART_IS7816_BWT_SHIFT                    5
+#define UART_IS7816_BWT_WIDTH                    1
+#define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_BWT_SHIFT))&UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK                     0x40u
+#define UART_IS7816_CWT_SHIFT                    6
+#define UART_IS7816_CWT_WIDTH                    1
+#define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_CWT_SHIFT))&UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK                      0x80u
+#define UART_IS7816_WT_SHIFT                     7
+#define UART_IS7816_WT_WIDTH                     1
+#define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x))<<UART_IS7816_WT_SHIFT))&UART_IS7816_WT_MASK)
+/* WP7816T0 Bit Fields */
+#define UART_WP7816T0_WI_MASK                    0xFFu
+#define UART_WP7816T0_WI_SHIFT                   0
+#define UART_WP7816T0_WI_WIDTH                   8
+#define UART_WP7816T0_WI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
+/* WP7816T1 Bit Fields */
+#define UART_WP7816T1_BWI_MASK                   0xFu
+#define UART_WP7816T1_BWI_SHIFT                  0
+#define UART_WP7816T1_BWI_WIDTH                  4
+#define UART_WP7816T1_BWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
+#define UART_WP7816T1_CWI_MASK                   0xF0u
+#define UART_WP7816T1_CWI_SHIFT                  4
+#define UART_WP7816T1_CWI_WIDTH                  4
+#define UART_WP7816T1_CWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK                     0xFFu
+#define UART_WN7816_GTN_SHIFT                    0
+#define UART_WN7816_GTN_WIDTH                    8
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK                    0xFFu
+#define UART_WF7816_GTFD_SHIFT                   0
+#define UART_WF7816_GTFD_WIDTH                   8
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK             0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT            0
+#define UART_ET7816_RXTHRESHOLD_WIDTH            4
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK             0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT            4
+#define UART_ET7816_TXTHRESHOLD_WIDTH            4
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK                    0xFFu
+#define UART_TL7816_TLEN_SHIFT                   0
+#define UART_TL7816_TLEN_WIDTH                   8
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0                                    ((UART_Type *)UART0_BASE)
+#define UART0_BASE_PTR                           (UART0)
+/** Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1                                    ((UART_Type *)UART1_BASE)
+#define UART1_BASE_PTR                           (UART1)
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR                           (UART2)
+/** Peripheral UART3 base address */
+#define UART3_BASE                               (0x4006D000u)
+/** Peripheral UART3 base pointer */
+#define UART3                                    ((UART_Type *)UART3_BASE)
+#define UART3_BASE_PTR                           (UART3)
+/** Peripheral UART4 base address */
+#define UART4_BASE                               (0x400EA000u)
+/** Peripheral UART4 base pointer */
+#define UART4                                    ((UART_Type *)UART4_BASE)
+#define UART4_BASE_PTR                           (UART4)
+/** Peripheral UART5 base address */
+#define UART5_BASE                               (0x400EB000u)
+/** Peripheral UART5 base pointer */
+#define UART5                                    ((UART_Type *)UART5_BASE)
+#define UART5_BASE_PTR                           (UART5)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS                           { UART0, UART1, UART2, UART3, UART4, UART5 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS                          { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
+#define UART_ERR_IRQS                            { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
+#define UART_LON_IRQS                            { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART0 */
+#define UART0_BDH                                UART_BDH_REG(UART0)
+#define UART0_BDL                                UART_BDL_REG(UART0)
+#define UART0_C1                                 UART_C1_REG(UART0)
+#define UART0_C2                                 UART_C2_REG(UART0)
+#define UART0_S1                                 UART_S1_REG(UART0)
+#define UART0_S2                                 UART_S2_REG(UART0)
+#define UART0_C3                                 UART_C3_REG(UART0)
+#define UART0_D                                  UART_D_REG(UART0)
+#define UART0_MA1                                UART_MA1_REG(UART0)
+#define UART0_MA2                                UART_MA2_REG(UART0)
+#define UART0_C4                                 UART_C4_REG(UART0)
+#define UART0_C5                                 UART_C5_REG(UART0)
+#define UART0_ED                                 UART_ED_REG(UART0)
+#define UART0_MODEM                              UART_MODEM_REG(UART0)
+#define UART0_IR                                 UART_IR_REG(UART0)
+#define UART0_PFIFO                              UART_PFIFO_REG(UART0)
+#define UART0_CFIFO                              UART_CFIFO_REG(UART0)
+#define UART0_SFIFO                              UART_SFIFO_REG(UART0)
+#define UART0_TWFIFO                             UART_TWFIFO_REG(UART0)
+#define UART0_TCFIFO                             UART_TCFIFO_REG(UART0)
+#define UART0_RWFIFO                             UART_RWFIFO_REG(UART0)
+#define UART0_RCFIFO                             UART_RCFIFO_REG(UART0)
+#define UART0_C7816                              UART_C7816_REG(UART0)
+#define UART0_IE7816                             UART_IE7816_REG(UART0)
+#define UART0_IS7816                             UART_IS7816_REG(UART0)
+#define UART0_WP7816T0                           UART_WP7816T0_REG(UART0)
+#define UART0_WP7816T1                           UART_WP7816T1_REG(UART0)
+#define UART0_WN7816                             UART_WN7816_REG(UART0)
+#define UART0_WF7816                             UART_WF7816_REG(UART0)
+#define UART0_ET7816                             UART_ET7816_REG(UART0)
+#define UART0_TL7816                             UART_TL7816_REG(UART0)
+/* UART1 */
+#define UART1_BDH                                UART_BDH_REG(UART1)
+#define UART1_BDL                                UART_BDL_REG(UART1)
+#define UART1_C1                                 UART_C1_REG(UART1)
+#define UART1_C2                                 UART_C2_REG(UART1)
+#define UART1_S1                                 UART_S1_REG(UART1)
+#define UART1_S2                                 UART_S2_REG(UART1)
+#define UART1_C3                                 UART_C3_REG(UART1)
+#define UART1_D                                  UART_D_REG(UART1)
+#define UART1_MA1                                UART_MA1_REG(UART1)
+#define UART1_MA2                                UART_MA2_REG(UART1)
+#define UART1_C4                                 UART_C4_REG(UART1)
+#define UART1_C5                                 UART_C5_REG(UART1)
+#define UART1_ED                                 UART_ED_REG(UART1)
+#define UART1_MODEM                              UART_MODEM_REG(UART1)
+#define UART1_IR                                 UART_IR_REG(UART1)
+#define UART1_PFIFO                              UART_PFIFO_REG(UART1)
+#define UART1_CFIFO                              UART_CFIFO_REG(UART1)
+#define UART1_SFIFO                              UART_SFIFO_REG(UART1)
+#define UART1_TWFIFO                             UART_TWFIFO_REG(UART1)
+#define UART1_TCFIFO                             UART_TCFIFO_REG(UART1)
+#define UART1_RWFIFO                             UART_RWFIFO_REG(UART1)
+#define UART1_RCFIFO                             UART_RCFIFO_REG(UART1)
+/* UART2 */
+#define UART2_BDH                                UART_BDH_REG(UART2)
+#define UART2_BDL                                UART_BDL_REG(UART2)
+#define UART2_C1                                 UART_C1_REG(UART2)
+#define UART2_C2                                 UART_C2_REG(UART2)
+#define UART2_S1                                 UART_S1_REG(UART2)
+#define UART2_S2                                 UART_S2_REG(UART2)
+#define UART2_C3                                 UART_C3_REG(UART2)
+#define UART2_D                                  UART_D_REG(UART2)
+#define UART2_MA1                                UART_MA1_REG(UART2)
+#define UART2_MA2                                UART_MA2_REG(UART2)
+#define UART2_C4                                 UART_C4_REG(UART2)
+#define UART2_C5                                 UART_C5_REG(UART2)
+#define UART2_ED                                 UART_ED_REG(UART2)
+#define UART2_MODEM                              UART_MODEM_REG(UART2)
+#define UART2_IR                                 UART_IR_REG(UART2)
+#define UART2_PFIFO                              UART_PFIFO_REG(UART2)
+#define UART2_CFIFO                              UART_CFIFO_REG(UART2)
+#define UART2_SFIFO                              UART_SFIFO_REG(UART2)
+#define UART2_TWFIFO                             UART_TWFIFO_REG(UART2)
+#define UART2_TCFIFO                             UART_TCFIFO_REG(UART2)
+#define UART2_RWFIFO                             UART_RWFIFO_REG(UART2)
+#define UART2_RCFIFO                             UART_RCFIFO_REG(UART2)
+/* UART3 */
+#define UART3_BDH                                UART_BDH_REG(UART3)
+#define UART3_BDL                                UART_BDL_REG(UART3)
+#define UART3_C1                                 UART_C1_REG(UART3)
+#define UART3_C2                                 UART_C2_REG(UART3)
+#define UART3_S1                                 UART_S1_REG(UART3)
+#define UART3_S2                                 UART_S2_REG(UART3)
+#define UART3_C3                                 UART_C3_REG(UART3)
+#define UART3_D                                  UART_D_REG(UART3)
+#define UART3_MA1                                UART_MA1_REG(UART3)
+#define UART3_MA2                                UART_MA2_REG(UART3)
+#define UART3_C4                                 UART_C4_REG(UART3)
+#define UART3_C5                                 UART_C5_REG(UART3)
+#define UART3_ED                                 UART_ED_REG(UART3)
+#define UART3_MODEM                              UART_MODEM_REG(UART3)
+#define UART3_IR                                 UART_IR_REG(UART3)
+#define UART3_PFIFO                              UART_PFIFO_REG(UART3)
+#define UART3_CFIFO                              UART_CFIFO_REG(UART3)
+#define UART3_SFIFO                              UART_SFIFO_REG(UART3)
+#define UART3_TWFIFO                             UART_TWFIFO_REG(UART3)
+#define UART3_TCFIFO                             UART_TCFIFO_REG(UART3)
+#define UART3_RWFIFO                             UART_RWFIFO_REG(UART3)
+#define UART3_RCFIFO                             UART_RCFIFO_REG(UART3)
+/* UART4 */
+#define UART4_BDH                                UART_BDH_REG(UART4)
+#define UART4_BDL                                UART_BDL_REG(UART4)
+#define UART4_C1                                 UART_C1_REG(UART4)
+#define UART4_C2                                 UART_C2_REG(UART4)
+#define UART4_S1                                 UART_S1_REG(UART4)
+#define UART4_S2                                 UART_S2_REG(UART4)
+#define UART4_C3                                 UART_C3_REG(UART4)
+#define UART4_D                                  UART_D_REG(UART4)
+#define UART4_MA1                                UART_MA1_REG(UART4)
+#define UART4_MA2                                UART_MA2_REG(UART4)
+#define UART4_C4                                 UART_C4_REG(UART4)
+#define UART4_C5                                 UART_C5_REG(UART4)
+#define UART4_ED                                 UART_ED_REG(UART4)
+#define UART4_MODEM                              UART_MODEM_REG(UART4)
+#define UART4_IR                                 UART_IR_REG(UART4)
+#define UART4_PFIFO                              UART_PFIFO_REG(UART4)
+#define UART4_CFIFO                              UART_CFIFO_REG(UART4)
+#define UART4_SFIFO                              UART_SFIFO_REG(UART4)
+#define UART4_TWFIFO                             UART_TWFIFO_REG(UART4)
+#define UART4_TCFIFO                             UART_TCFIFO_REG(UART4)
+#define UART4_RWFIFO                             UART_RWFIFO_REG(UART4)
+#define UART4_RCFIFO                             UART_RCFIFO_REG(UART4)
+/* UART5 */
+#define UART5_BDH                                UART_BDH_REG(UART5)
+#define UART5_BDL                                UART_BDL_REG(UART5)
+#define UART5_C1                                 UART_C1_REG(UART5)
+#define UART5_C2                                 UART_C2_REG(UART5)
+#define UART5_S1                                 UART_S1_REG(UART5)
+#define UART5_S2                                 UART_S2_REG(UART5)
+#define UART5_C3                                 UART_C3_REG(UART5)
+#define UART5_D                                  UART_D_REG(UART5)
+#define UART5_MA1                                UART_MA1_REG(UART5)
+#define UART5_MA2                                UART_MA2_REG(UART5)
+#define UART5_C4                                 UART_C4_REG(UART5)
+#define UART5_C5                                 UART_C5_REG(UART5)
+#define UART5_ED                                 UART_ED_REG(UART5)
+#define UART5_MODEM                              UART_MODEM_REG(UART5)
+#define UART5_IR                                 UART_IR_REG(UART5)
+#define UART5_PFIFO                              UART_PFIFO_REG(UART5)
+#define UART5_CFIFO                              UART_CFIFO_REG(UART5)
+#define UART5_SFIFO                              UART_SFIFO_REG(UART5)
+#define UART5_TWFIFO                             UART_TWFIFO_REG(UART5)
+#define UART5_TCFIFO                             UART_TCFIFO_REG(UART5)
+#define UART5_RWFIFO                             UART_RWFIFO_REG(UART5)
+#define UART5_RCFIFO                             UART_RCFIFO_REG(UART5)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[3];
+  __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t OTGICR;                             /**< OTG Interrupt Control register, offset: 0x14 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_7[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_11[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_16[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t SOFTHLD;                            /**< SOF Threshold register, offset: 0xAC */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_20[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_21[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_22[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_25[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
+       uint8_t RESERVED_26[43];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_27[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48M oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_28[23];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base)                      ((base)->PERID)
+#define USB_IDCOMP_REG(base)                     ((base)->IDCOMP)
+#define USB_REV_REG(base)                        ((base)->REV)
+#define USB_ADDINFO_REG(base)                    ((base)->ADDINFO)
+#define USB_OTGISTAT_REG(base)                   ((base)->OTGISTAT)
+#define USB_OTGICR_REG(base)                     ((base)->OTGICR)
+#define USB_OTGSTAT_REG(base)                    ((base)->OTGSTAT)
+#define USB_OTGCTL_REG(base)                     ((base)->OTGCTL)
+#define USB_ISTAT_REG(base)                      ((base)->ISTAT)
+#define USB_INTEN_REG(base)                      ((base)->INTEN)
+#define USB_ERRSTAT_REG(base)                    ((base)->ERRSTAT)
+#define USB_ERREN_REG(base)                      ((base)->ERREN)
+#define USB_STAT_REG(base)                       ((base)->STAT)
+#define USB_CTL_REG(base)                        ((base)->CTL)
+#define USB_ADDR_REG(base)                       ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base)                   ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base)                    ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base)                    ((base)->FRMNUMH)
+#define USB_TOKEN_REG(base)                      ((base)->TOKEN)
+#define USB_SOFTHLD_REG(base)                    ((base)->SOFTHLD)
+#define USB_BDTPAGE2_REG(base)                   ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base)                   ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index)                ((base)->ENDPOINT[index].ENDPT)
+#define USB_ENDPT_COUNT                          16
+#define USB_USBCTRL_REG(base)                    ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base)                    ((base)->OBSERVE)
+#define USB_CONTROL_REG(base)                    ((base)->CONTROL)
+#define USB_USBTRC0_REG(base)                    ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base)               ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base)           ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base)         ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base)     ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK                        0x3Fu
+#define USB_PERID_ID_SHIFT                       0
+#define USB_PERID_ID_WIDTH                       6
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK                      0x3Fu
+#define USB_IDCOMP_NID_SHIFT                     0
+#define USB_IDCOMP_NID_WIDTH                     6
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK                         0xFFu
+#define USB_REV_REV_SHIFT                        0
+#define USB_REV_REV_WIDTH                        8
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK                  0x1u
+#define USB_ADDINFO_IEHOST_SHIFT                 0
+#define USB_ADDINFO_IEHOST_WIDTH                 1
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
+#define USB_ADDINFO_IRQNUM_MASK                  0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT                 3
+#define USB_ADDINFO_IRQNUM_WIDTH                 5
+#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK               0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT              0
+#define USB_OTGISTAT_AVBUSCHG_WIDTH              1
+#define USB_OTGISTAT_AVBUSCHG(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_AVBUSCHG_SHIFT))&USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK             0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT            2
+#define USB_OTGISTAT_B_SESS_CHG_WIDTH            1
+#define USB_OTGISTAT_B_SESS_CHG(x)               (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_B_SESS_CHG_SHIFT))&USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK             0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT            3
+#define USB_OTGISTAT_SESSVLDCHG_WIDTH            1
+#define USB_OTGISTAT_SESSVLDCHG(x)               (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_SESSVLDCHG_SHIFT))&USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK         0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        5
+#define USB_OTGISTAT_LINE_STATE_CHG_WIDTH        1
+#define USB_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK                0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT               6
+#define USB_OTGISTAT_ONEMSEC_WIDTH               1
+#define USB_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK                  0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT                 7
+#define USB_OTGISTAT_IDCHG_WIDTH                 1
+#define USB_OTGISTAT_IDCHG(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_IDCHG_SHIFT))&USB_OTGISTAT_IDCHG_MASK)
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK                  0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT                 0
+#define USB_OTGICR_AVBUSEN_WIDTH                 1
+#define USB_OTGICR_AVBUSEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_AVBUSEN_SHIFT))&USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK                  0x4u
+#define USB_OTGICR_BSESSEN_SHIFT                 2
+#define USB_OTGICR_BSESSEN_WIDTH                 1
+#define USB_OTGICR_BSESSEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_BSESSEN_SHIFT))&USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK                0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT               3
+#define USB_OTGICR_SESSVLDEN_WIDTH               1
+#define USB_OTGICR_SESSVLDEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_SESSVLDEN_SHIFT))&USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK              0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT             5
+#define USB_OTGICR_LINESTATEEN_WIDTH             1
+#define USB_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK                0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT               6
+#define USB_OTGICR_ONEMSECEN_WIDTH               1
+#define USB_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK                     0x80u
+#define USB_OTGICR_IDEN_SHIFT                    7
+#define USB_OTGICR_IDEN_WIDTH                    1
+#define USB_OTGICR_IDEN(x)                       (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_IDEN_SHIFT))&USB_OTGICR_IDEN_MASK)
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK                0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT               0
+#define USB_OTGSTAT_AVBUSVLD_WIDTH               1
+#define USB_OTGSTAT_AVBUSVLD(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_AVBUSVLD_SHIFT))&USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK                0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT               2
+#define USB_OTGSTAT_BSESSEND_WIDTH               1
+#define USB_OTGSTAT_BSESSEND(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_BSESSEND_SHIFT))&USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK                0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT               3
+#define USB_OTGSTAT_SESS_VLD_WIDTH               1
+#define USB_OTGSTAT_SESS_VLD(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_SESS_VLD_SHIFT))&USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK         0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        5
+#define USB_OTGSTAT_LINESTATESTABLE_WIDTH        1
+#define USB_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK               0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT              6
+#define USB_OTGSTAT_ONEMSECEN_WIDTH              1
+#define USB_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK                      0x80u
+#define USB_OTGSTAT_ID_SHIFT                     7
+#define USB_OTGSTAT_ID_WIDTH                     1
+#define USB_OTGSTAT_ID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ID_SHIFT))&USB_OTGSTAT_ID_MASK)
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK                    0x4u
+#define USB_OTGCTL_OTGEN_SHIFT                   2
+#define USB_OTGCTL_OTGEN_WIDTH                   1
+#define USB_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK                    0x10u
+#define USB_OTGCTL_DMLOW_SHIFT                   4
+#define USB_OTGCTL_DMLOW_WIDTH                   1
+#define USB_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK                    0x20u
+#define USB_OTGCTL_DPLOW_SHIFT                   5
+#define USB_OTGCTL_DPLOW_WIDTH                   1
+#define USB_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK                   0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT                  7
+#define USB_OTGCTL_DPHIGH_WIDTH                  1
+#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK                    0x1u
+#define USB_ISTAT_USBRST_SHIFT                   0
+#define USB_ISTAT_USBRST_WIDTH                   1
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK                     0x2u
+#define USB_ISTAT_ERROR_SHIFT                    1
+#define USB_ISTAT_ERROR_WIDTH                    1
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK                    0x4u
+#define USB_ISTAT_SOFTOK_SHIFT                   2
+#define USB_ISTAT_SOFTOK_WIDTH                   1
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK                    0x8u
+#define USB_ISTAT_TOKDNE_SHIFT                   3
+#define USB_ISTAT_TOKDNE_WIDTH                   1
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK                     0x10u
+#define USB_ISTAT_SLEEP_SHIFT                    4
+#define USB_ISTAT_SLEEP_WIDTH                    1
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK                    0x20u
+#define USB_ISTAT_RESUME_SHIFT                   5
+#define USB_ISTAT_RESUME_WIDTH                   1
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK                    0x40u
+#define USB_ISTAT_ATTACH_SHIFT                   6
+#define USB_ISTAT_ATTACH_WIDTH                   1
+#define USB_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK                     0x80u
+#define USB_ISTAT_STALL_SHIFT                    7
+#define USB_ISTAT_STALL_WIDTH                    1
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK                  0x1u
+#define USB_INTEN_USBRSTEN_SHIFT                 0
+#define USB_INTEN_USBRSTEN_WIDTH                 1
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK                   0x2u
+#define USB_INTEN_ERROREN_SHIFT                  1
+#define USB_INTEN_ERROREN_WIDTH                  1
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK                  0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT                 2
+#define USB_INTEN_SOFTOKEN_WIDTH                 1
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK                  0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT                 3
+#define USB_INTEN_TOKDNEEN_WIDTH                 1
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK                   0x10u
+#define USB_INTEN_SLEEPEN_SHIFT                  4
+#define USB_INTEN_SLEEPEN_WIDTH                  1
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK                  0x20u
+#define USB_INTEN_RESUMEEN_SHIFT                 5
+#define USB_INTEN_RESUMEEN_WIDTH                 1
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK                  0x40u
+#define USB_INTEN_ATTACHEN_SHIFT                 6
+#define USB_INTEN_ATTACHEN_WIDTH                 1
+#define USB_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK                   0x80u
+#define USB_INTEN_STALLEN_SHIFT                  7
+#define USB_INTEN_STALLEN_WIDTH                  1
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK                  0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT                 0
+#define USB_ERRSTAT_PIDERR_WIDTH                 1
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK                 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT                1
+#define USB_ERRSTAT_CRC5EOF_WIDTH                1
+#define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK                   0x4u
+#define USB_ERRSTAT_CRC16_SHIFT                  2
+#define USB_ERRSTAT_CRC16_WIDTH                  1
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK                    0x8u
+#define USB_ERRSTAT_DFN8_SHIFT                   3
+#define USB_ERRSTAT_DFN8_WIDTH                   1
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK                  0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT                 4
+#define USB_ERRSTAT_BTOERR_WIDTH                 1
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK                  0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT                 5
+#define USB_ERRSTAT_DMAERR_WIDTH                 1
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK                  0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT                 7
+#define USB_ERRSTAT_BTSERR_WIDTH                 1
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK                  0x1u
+#define USB_ERREN_PIDERREN_SHIFT                 0
+#define USB_ERREN_PIDERREN_WIDTH                 1
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK                 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT                1
+#define USB_ERREN_CRC5EOFEN_WIDTH                1
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK                   0x4u
+#define USB_ERREN_CRC16EN_SHIFT                  2
+#define USB_ERREN_CRC16EN_WIDTH                  1
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK                    0x8u
+#define USB_ERREN_DFN8EN_SHIFT                   3
+#define USB_ERREN_DFN8EN_WIDTH                   1
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK                  0x10u
+#define USB_ERREN_BTOERREN_SHIFT                 4
+#define USB_ERREN_BTOERREN_WIDTH                 1
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK                  0x20u
+#define USB_ERREN_DMAERREN_SHIFT                 5
+#define USB_ERREN_DMAERREN_WIDTH                 1
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK                  0x80u
+#define USB_ERREN_BTSERREN_SHIFT                 7
+#define USB_ERREN_BTSERREN_WIDTH                 1
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK                        0x4u
+#define USB_STAT_ODD_SHIFT                       2
+#define USB_STAT_ODD_WIDTH                       1
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK                         0x8u
+#define USB_STAT_TX_SHIFT                        3
+#define USB_STAT_TX_WIDTH                        1
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK                       0xF0u
+#define USB_STAT_ENDP_SHIFT                      4
+#define USB_STAT_ENDP_WIDTH                      4
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK                  0x1u
+#define USB_CTL_USBENSOFEN_SHIFT                 0
+#define USB_CTL_USBENSOFEN_WIDTH                 1
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK                      0x2u
+#define USB_CTL_ODDRST_SHIFT                     1
+#define USB_CTL_ODDRST_WIDTH                     1
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK                      0x4u
+#define USB_CTL_RESUME_SHIFT                     2
+#define USB_CTL_RESUME_WIDTH                     1
+#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK                  0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT                 3
+#define USB_CTL_HOSTMODEEN_WIDTH                 1
+#define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK                       0x10u
+#define USB_CTL_RESET_SHIFT                      4
+#define USB_CTL_RESET_WIDTH                      1
+#define USB_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
+#define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH         1
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK                         0x40u
+#define USB_CTL_SE0_SHIFT                        6
+#define USB_CTL_SE0_WIDTH                        1
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK                      0x80u
+#define USB_CTL_JSTATE_SHIFT                     7
+#define USB_CTL_JSTATE_WIDTH                     1
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK                       0x7Fu
+#define USB_ADDR_ADDR_SHIFT                      0
+#define USB_ADDR_ADDR_WIDTH                      7
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK                       0x80u
+#define USB_ADDR_LSEN_SHIFT                      7
+#define USB_ADDR_LSEN_WIDTH                      1
+#define USB_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT                 1
+#define USB_BDTPAGE1_BDTBA_WIDTH                 7
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK                     0xFFu
+#define USB_FRMNUML_FRM_SHIFT                    0
+#define USB_FRMNUML_FRM_WIDTH                    8
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK                     0x7u
+#define USB_FRMNUMH_FRM_SHIFT                    0
+#define USB_FRMNUMH_FRM_WIDTH                    3
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK                0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT               0
+#define USB_TOKEN_TOKENENDPT_WIDTH               4
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT                 4
+#define USB_TOKEN_TOKENPID_WIDTH                 4
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK                     0xFFu
+#define USB_SOFTHLD_CNT_SHIFT                    0
+#define USB_SOFTHLD_CNT_WIDTH                    8
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT                 0
+#define USB_BDTPAGE2_BDTBA_WIDTH                 8
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT                 0
+#define USB_BDTPAGE3_BDTBA_WIDTH                 8
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK                    0x1u
+#define USB_ENDPT_EPHSHK_SHIFT                   0
+#define USB_ENDPT_EPHSHK_WIDTH                   1
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK                   0x2u
+#define USB_ENDPT_EPSTALL_SHIFT                  1
+#define USB_ENDPT_EPSTALL_WIDTH                  1
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK                    0x4u
+#define USB_ENDPT_EPTXEN_SHIFT                   2
+#define USB_ENDPT_EPTXEN_WIDTH                   1
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK                    0x8u
+#define USB_ENDPT_EPRXEN_SHIFT                   3
+#define USB_ENDPT_EPRXEN_WIDTH                   1
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK                  0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT                 4
+#define USB_ENDPT_EPCTLDIS_WIDTH                 1
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK                  0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT                 6
+#define USB_ENDPT_RETRYDIS_WIDTH                 1
+#define USB_ENDPT_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK                 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT                7
+#define USB_ENDPT_HOSTWOHUB_WIDTH                1
+#define USB_ENDPT_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK                     0x40u
+#define USB_USBCTRL_PDE_SHIFT                    6
+#define USB_USBCTRL_PDE_WIDTH                    1
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK                    0x80u
+#define USB_USBCTRL_SUSP_SHIFT                   7
+#define USB_USBCTRL_SUSP_WIDTH                   1
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK                    0x10u
+#define USB_OBSERVE_DMPD_SHIFT                   4
+#define USB_OBSERVE_DMPD_WIDTH                   1
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK                    0x40u
+#define USB_OBSERVE_DPPD_SHIFT                   6
+#define USB_OBSERVE_DPPD_WIDTH                   1
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK                    0x80u
+#define USB_OBSERVE_DPPU_SHIFT                   7
+#define USB_OBSERVE_DPPU_WIDTH                   1
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
+#define USB_CONTROL_DPPULLUPNONOTG_WIDTH         1
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
+#define USB_USBTRC0_USB_RESUME_INT_WIDTH         1
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK                0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT               1
+#define USB_USBTRC0_SYNC_DET_WIDTH               1
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   2
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH   1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))&USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK               0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT              5
+#define USB_USBTRC0_USBRESMEN_WIDTH              1
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK                0x80u
+#define USB_USBTRC0_USBRESET_SHIFT               7
+#define USB_USBTRC0_USBRESET_WIDTH               1
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK                0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT               0
+#define USB_USBFRMADJUST_ADJ_WIDTH               8
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))&USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK       0x1u
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      0
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH 1
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))&USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR                            (USB0)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID                               USB_PERID_REG(USB0)
+#define USB0_IDCOMP                              USB_IDCOMP_REG(USB0)
+#define USB0_REV                                 USB_REV_REG(USB0)
+#define USB0_ADDINFO                             USB_ADDINFO_REG(USB0)
+#define USB0_OTGISTAT                            USB_OTGISTAT_REG(USB0)
+#define USB0_OTGICR                              USB_OTGICR_REG(USB0)
+#define USB0_OTGSTAT                             USB_OTGSTAT_REG(USB0)
+#define USB0_OTGCTL                              USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT                               USB_ISTAT_REG(USB0)
+#define USB0_INTEN                               USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT                             USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN                               USB_ERREN_REG(USB0)
+#define USB0_STAT                                USB_STAT_REG(USB0)
+#define USB0_CTL                                 USB_CTL_REG(USB0)
+#define USB0_ADDR                                USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1                            USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML                             USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH                             USB_FRMNUMH_REG(USB0)
+#define USB0_TOKEN                               USB_TOKEN_REG(USB0)
+#define USB0_SOFTHLD                             USB_SOFTHLD_REG(USB0)
+#define USB0_BDTPAGE2                            USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3                            USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0                              USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1                              USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2                              USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3                              USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4                              USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5                              USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6                              USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7                              USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8                              USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9                              USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10                             USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11                             USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12                             USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13                             USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14                             USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15                             USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL                             USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE                             USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL                             USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0                             USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST                        USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL                    USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN                  USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS              USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index)                        USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
+  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
+  __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
+  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
+  union {                                          /* offset: 0x18 */
+    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
+    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
+  };
+} USBDCD_Type, *USBDCD_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register accessors */
+#define USBDCD_CONTROL_REG(base)                 ((base)->CONTROL)
+#define USBDCD_CLOCK_REG(base)                   ((base)->CLOCK)
+#define USBDCD_STATUS_REG(base)                  ((base)->STATUS)
+#define USBDCD_TIMER0_REG(base)                  ((base)->TIMER0)
+#define USBDCD_TIMER1_REG(base)                  ((base)->TIMER1)
+#define USBDCD_TIMER2_BC11_REG(base)             ((base)->TIMER2_BC11)
+#define USBDCD_TIMER2_BC12_REG(base)             ((base)->TIMER2_BC12)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK                 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT                0
+#define USBDCD_CONTROL_IACK_WIDTH                1
+#define USBDCD_CONTROL_IACK(x)                   (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IACK_SHIFT))&USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IF_MASK                   0x100u
+#define USBDCD_CONTROL_IF_SHIFT                  8
+#define USBDCD_CONTROL_IF_WIDTH                  1
+#define USBDCD_CONTROL_IF(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IF_SHIFT))&USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IE_MASK                   0x10000u
+#define USBDCD_CONTROL_IE_SHIFT                  16
+#define USBDCD_CONTROL_IE_WIDTH                  1
+#define USBDCD_CONTROL_IE(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IE_SHIFT))&USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_BC12_MASK                 0x20000u
+#define USBDCD_CONTROL_BC12_SHIFT                17
+#define USBDCD_CONTROL_BC12_WIDTH                1
+#define USBDCD_CONTROL_BC12(x)                   (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_BC12_SHIFT))&USBDCD_CONTROL_BC12_MASK)
+#define USBDCD_CONTROL_START_MASK                0x1000000u
+#define USBDCD_CONTROL_START_SHIFT               24
+#define USBDCD_CONTROL_START_WIDTH               1
+#define USBDCD_CONTROL_START(x)                  (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_START_SHIFT))&USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_SR_MASK                   0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT                  25
+#define USBDCD_CONTROL_SR_WIDTH                  1
+#define USBDCD_CONTROL_SR(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_SR_SHIFT))&USBDCD_CONTROL_SR_MASK)
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK             0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            0
+#define USBDCD_CLOCK_CLOCK_UNIT_WIDTH            1
+#define USBDCD_CLOCK_CLOCK_UNIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_UNIT_SHIFT))&USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK            0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           2
+#define USBDCD_CLOCK_CLOCK_SPEED_WIDTH           10
+#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK               0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT              16
+#define USBDCD_STATUS_SEQ_RES_WIDTH              2
+#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK              0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT             18
+#define USBDCD_STATUS_SEQ_STAT_WIDTH             2
+#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK                   0x100000u
+#define USBDCD_STATUS_ERR_SHIFT                  20
+#define USBDCD_STATUS_ERR_WIDTH                  1
+#define USBDCD_STATUS_ERR(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ERR_SHIFT))&USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_TO_MASK                    0x200000u
+#define USBDCD_STATUS_TO_SHIFT                   21
+#define USBDCD_STATUS_TO_WIDTH                   1
+#define USBDCD_STATUS_TO(x)                      (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_TO_SHIFT))&USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_ACTIVE_MASK                0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT               22
+#define USBDCD_STATUS_ACTIVE_WIDTH               1
+#define USBDCD_STATUS_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ACTIVE_SHIFT))&USBDCD_STATUS_ACTIVE_MASK)
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK              0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT             0
+#define USBDCD_TIMER0_TUNITCON_WIDTH             12
+#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK             0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            16
+#define USBDCD_TIMER0_TSEQ_INIT_WIDTH            10
+#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK            0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           0
+#define USBDCD_TIMER1_TVDPSRC_ON_WIDTH           10
+#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK             0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            16
+#define USBDCD_TIMER1_TDCD_DBNC_WIDTH            10
+#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2_BC11 Bit Fields */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK         0xFu
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        0
+#define USBDCD_TIMER2_BC11_CHECK_DM_WIDTH        4
+#define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      0x3FF0000u
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     16
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_WIDTH     10
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+/* TIMER2_BC12 Bit Fields */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       0x3FFu
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      0
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_WIDTH      10
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  0x3FF0000u
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_WIDTH 10
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE                              (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD                                   ((USBDCD_Type *)USBDCD_BASE)
+#define USBDCD_BASE_PTR                          (USBDCD)
+/** Array initializer of USBDCD peripheral base addresses */
+#define USBDCD_BASE_ADDRS                        { USBDCD_BASE }
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASE_PTRS                         { USBDCD }
+/** Interrupt vectors for the USBDCD peripheral type */
+#define USBDCD_IRQS                              { USBDCD_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register instance definitions */
+/* USBDCD */
+#define USBDCD_CONTROL                           USBDCD_CONTROL_REG(USBDCD)
+#define USBDCD_CLOCK                             USBDCD_CLOCK_REG(USBDCD)
+#define USBDCD_STATUS                            USBDCD_STATUS_REG(USBDCD)
+#define USBDCD_TIMER0                            USBDCD_TIMER0_REG(USBDCD)
+#define USBDCD_TIMER1                            USBDCD_TIMER1_REG(USBDCD)
+#define USBDCD_TIMER2_BC11                       USBDCD_TIMER2_BC11_REG(USBDCD)
+#define USBDCD_TIMER2_BC12                       USBDCD_TIMER2_BC12_REG(USBDCD)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base)                       ((base)->TRM)
+#define VREF_SC_REG(base)                        ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK                       0x3Fu
+#define VREF_TRM_TRIM_SHIFT                      0
+#define VREF_TRM_TRIM_WIDTH                      6
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     0x40u
+#define VREF_TRM_CHOPEN_SHIFT                    6
+#define VREF_TRM_CHOPEN_WIDTH                    1
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_TRM_CHOPEN_SHIFT))&VREF_TRM_CHOPEN_MASK)
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK                     0x3u
+#define VREF_SC_MODE_LV_SHIFT                    0
+#define VREF_SC_MODE_LV_WIDTH                    2
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      0x4u
+#define VREF_SC_VREFST_SHIFT                     2
+#define VREF_SC_VREFST_WIDTH                     1
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFST_SHIFT))&VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK                     0x20u
+#define VREF_SC_ICOMPEN_SHIFT                    5
+#define VREF_SC_ICOMPEN_WIDTH                    1
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_ICOMPEN_SHIFT))&VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK                       0x40u
+#define VREF_SC_REGEN_SHIFT                      6
+#define VREF_SC_REGEN_WIDTH                      1
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_SC_REGEN_SHIFT))&VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK                      0x80u
+#define VREF_SC_VREFEN_SHIFT                     7
+#define VREF_SC_VREFEN_WIDTH                     1
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFEN_SHIFT))&VREF_SC_VREFEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR                            (VREF)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM                                 VREF_TRM_REG(VREF)
+#define VREF_SC                                  VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t STCTRLH;                           /**< Watchdog Status and Control Register High, offset: 0x0 */
+  __IO uint16_t STCTRLL;                           /**< Watchdog Status and Control Register Low, offset: 0x2 */
+  __IO uint16_t TOVALH;                            /**< Watchdog Time-out Value Register High, offset: 0x4 */
+  __IO uint16_t TOVALL;                            /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+  __IO uint16_t WINH;                              /**< Watchdog Window Register High, offset: 0x8 */
+  __IO uint16_t WINL;                              /**< Watchdog Window Register Low, offset: 0xA */
+  __IO uint16_t REFRESH;                           /**< Watchdog Refresh register, offset: 0xC */
+  __IO uint16_t UNLOCK;                            /**< Watchdog Unlock register, offset: 0xE */
+  __IO uint16_t TMROUTH;                           /**< Watchdog Timer Output Register High, offset: 0x10 */
+  __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
+  __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
+  __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type, *WDOG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register accessors */
+#define WDOG_STCTRLH_REG(base)                   ((base)->STCTRLH)
+#define WDOG_STCTRLL_REG(base)                   ((base)->STCTRLL)
+#define WDOG_TOVALH_REG(base)                    ((base)->TOVALH)
+#define WDOG_TOVALL_REG(base)                    ((base)->TOVALL)
+#define WDOG_WINH_REG(base)                      ((base)->WINH)
+#define WDOG_WINL_REG(base)                      ((base)->WINL)
+#define WDOG_REFRESH_REG(base)                   ((base)->REFRESH)
+#define WDOG_UNLOCK_REG(base)                    ((base)->UNLOCK)
+#define WDOG_TMROUTH_REG(base)                   ((base)->TMROUTH)
+#define WDOG_TMROUTL_REG(base)                   ((base)->TMROUTL)
+#define WDOG_RSTCNT_REG(base)                    ((base)->RSTCNT)
+#define WDOG_PRESC_REG(base)                     ((base)->PRESC)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK                 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT                0
+#define WDOG_STCTRLH_WDOGEN_WIDTH                1
+#define WDOG_STCTRLH_WDOGEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WDOGEN_SHIFT))&WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK                 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT                1
+#define WDOG_STCTRLH_CLKSRC_WIDTH                1
+#define WDOG_STCTRLH_CLKSRC(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_CLKSRC_SHIFT))&WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK               0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT              2
+#define WDOG_STCTRLH_IRQRSTEN_WIDTH              1
+#define WDOG_STCTRLH_IRQRSTEN(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_IRQRSTEN_SHIFT))&WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK                  0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT                 3
+#define WDOG_STCTRLH_WINEN_WIDTH                 1
+#define WDOG_STCTRLH_WINEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WINEN_SHIFT))&WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK            0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           4
+#define WDOG_STCTRLH_ALLOWUPDATE_WIDTH           1
+#define WDOG_STCTRLH_ALLOWUPDATE(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_ALLOWUPDATE_SHIFT))&WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK                  0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT                 5
+#define WDOG_STCTRLH_DBGEN_WIDTH                 1
+#define WDOG_STCTRLH_DBGEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DBGEN_SHIFT))&WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK                 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT                6
+#define WDOG_STCTRLH_STOPEN_WIDTH                1
+#define WDOG_STCTRLH_STOPEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_STOPEN_SHIFT))&WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK                 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT                7
+#define WDOG_STCTRLH_WAITEN_WIDTH                1
+#define WDOG_STCTRLH_WAITEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WAITEN_SHIFT))&WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK               0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT              10
+#define WDOG_STCTRLH_TESTWDOG_WIDTH              1
+#define WDOG_STCTRLH_TESTWDOG(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTWDOG_SHIFT))&WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK                0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT               11
+#define WDOG_STCTRLH_TESTSEL_WIDTH               1
+#define WDOG_STCTRLH_TESTSEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTSEL_SHIFT))&WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK                0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT               12
+#define WDOG_STCTRLH_BYTESEL_WIDTH               2
+#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK            0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT           14
+#define WDOG_STCTRLH_DISTESTWDOG_WIDTH           1
+#define WDOG_STCTRLH_DISTESTWDOG(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DISTESTWDOG_SHIFT))&WDOG_STCTRLH_DISTESTWDOG_MASK)
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK                 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT                15
+#define WDOG_STCTRLL_INTFLG_WIDTH                1
+#define WDOG_STCTRLL_INTFLG(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLL_INTFLG_SHIFT))&WDOG_STCTRLL_INTFLG_MASK)
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK               0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              0
+#define WDOG_TOVALH_TOVALHIGH_WIDTH              16
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK                0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT               0
+#define WDOG_TOVALL_TOVALLOW_WIDTH               16
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK                   0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT                  0
+#define WDOG_WINH_WINHIGH_WIDTH                  16
+#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK                    0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT                   0
+#define WDOG_WINL_WINLOW_WIDTH                   16
+#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK            0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT           0
+#define WDOG_REFRESH_WDOGREFRESH_WIDTH           16
+#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK              0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             0
+#define WDOG_UNLOCK_WDOGUNLOCK_WIDTH             16
+#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK           0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          0
+#define WDOG_TMROUTH_TIMEROUTHIGH_WIDTH          16
+#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK            0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           0
+#define WDOG_TMROUTL_TIMEROUTLOW_WIDTH           16
+#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK                  0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT                 0
+#define WDOG_RSTCNT_RSTCNT_WIDTH                 16
+#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK                 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT                8
+#define WDOG_PRESC_PRESCVAL_WIDTH                3
+#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+#define WDOG_BASE_PTR                            (WDOG)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS                          { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS                           { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS                                { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register instance definitions */
+/* WDOG */
+#define WDOG_STCTRLH                             WDOG_STCTRLH_REG(WDOG)
+#define WDOG_STCTRLL                             WDOG_STCTRLL_REG(WDOG)
+#define WDOG_TOVALH                              WDOG_TOVALH_REG(WDOG)
+#define WDOG_TOVALL                              WDOG_TOVALL_REG(WDOG)
+#define WDOG_WINH                                WDOG_WINH_REG(WDOG)
+#define WDOG_WINL                                WDOG_WINL_REG(WDOG)
+#define WDOG_REFRESH                             WDOG_REFRESH_REG(WDOG)
+#define WDOG_UNLOCK                              WDOG_UNLOCK_REG(WDOG)
+#define WDOG_TMROUTH                             WDOG_TMROUTH_REG(WDOG)
+#define WDOG_TMROUTL                             WDOG_TMROUTL_REG(WDOG)
+#define WDOG_RSTCNT                              WDOG_RSTCNT_REG(WDOG)
+#define WDOG_PRESC                               WDOG_PRESC_REG(WDOG)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Backward Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define DMA_EARS_REG(base)                       This_symbol_has_been_deprecated
+#define DMA_EARS                                 This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_SHIFT                  This_symbol_has_been_deprecated
+#define ENET_RMON_T_DROP_REG(base)               This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP_REG(base)               This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE_REG(base)                This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0_REG(base)            This_symbol_has_been_deprecated
+#define ENET_RMON_R_DROP_REG(base)               ENET_IEEE_R_DROP_REG(base)
+#define ENET_RMON_R_FRAME_OK_REG(base)           ENET_IEEE_R_FRAME_OK_REG(base)
+#define ENET_RMON_T_DROP                         This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP                         This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE                          This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0                      This_symbol_has_been_deprecated
+#define MCG_C9_REG(base)                         This_symbol_has_been_deprecated
+#define MCG_C2_EREFS0_MASK                       MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT                      MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK                         MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT                        MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK                       MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT                      MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x)                         MCG_C2_RANGE(x)
+#define MCG_C9                                   This_symbol_has_been_deprecated
+#define MCM_PLACR_REG(base)                      This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_MASK                       This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_SHIFT                      This_symbol_has_been_deprecated
+#define MCM_PLACR                                This_symbol_has_been_deprecated
+#define ADC_BASES                    ADC_BASE_PTRS
+#define AIPS_BASES                   AIPS_BASE_PTRS
+#define AXBS_BASES                   AXBS_BASE_PTRS
+#define CAN_BASES                    CAN_BASE_PTRS
+#define CAU_BASES                    CAU_BASE_PTRS
+#define CMP_BASES                    CMP_BASE_PTRS
+#define CMT_BASES                    CMT_BASE_PTRS
+#define CRC_BASES                    CRC_BASE_PTRS
+#define DAC_BASES                    DAC_BASE_PTRS
+#define DMA_BASES                    DMA_BASE_PTRS
+#define DMAMUX_BASES                 DMAMUX_BASE_PTRS
+#define ENET_BASES                   ENET_BASE_PTRS
+#define EWM_BASES                    EWM_BASE_PTRS
+#define FB_BASES                     FB_BASE_PTRS
+#define FMC_BASES                    FMC_BASE_PTRS
+#define FTFE_BASES                   FTFE_BASE_PTRS
+#define FTM_BASES                    FTM_BASE_PTRS
+#define GPIO_BASES                   GPIO_BASE_PTRS
+#define I2C_BASES                    I2C_BASE_PTRS
+#define I2S_BASES                    I2S_BASE_PTRS
+#define LLWU_BASES                   LLWU_BASE_PTRS
+#define LPTMR_BASES                  LPTMR_BASE_PTRS
+#define MCG_BASES                    MCG_BASE_PTRS
+#define MCM_ISR_REG(base)            MCM_ISCR_REG(base)
+#define MCM_ISR_FIOC_MASK            MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT           MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK            MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT           MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK            MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT           MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK            MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT           MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK            MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT           MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK            MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT           MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK           MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT          MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK           MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT          MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK           MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT          MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK           MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT          MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK           MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT          MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK           MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT          MCM_ISCR_FIDCE_SHIFT
+#define MCM_BASES                    MCM_BASE_PTRS
+#define MPU_BASES                    MPU_BASE_PTRS
+#define NV_BASES                     NV_BASE_PTRS
+#define OSC_BASES                    OSC_BASE_PTRS
+#define PDB_BASES                    PDB_BASE_PTRS
+#define PIT_BASES                    PIT_BASE_PTRS
+#define PMC_BASES                    PMC_BASE_PTRS
+#define PORT_BASES                   PORT_BASE_PTRS
+#define RCM_BASES                    RCM_BASE_PTRS
+#define RFSYS_BASES                  RFSYS_BASE_PTRS
+#define RFVBAT_BASES                 RFVBAT_BASE_PTRS
+#define RNG_BASES                    RNG_BASE_PTRS
+#define RTC_BASES                    RTC_BASE_PTRS
+#define SDHC_BASES                   SDHC_BASE_PTRS
+#define SIM_BASES                    SIM_BASE_PTRS
+#define SMC_BASES                    SMC_BASE_PTRS
+#define SPI_BASES                    SPI_BASE_PTRS
+#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
+#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
+#define UART_WP7816_T_TYPE0_WI_MASK  UART_WP7816T0_WI_MASK
+#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
+#define UART_WP7816_T_TYPE0_WI(x)    UART_WP7816T0_WI(x)
+#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
+#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
+#define UART_WP7816_T_TYPE1_BWI(x)   UART_WP7816T1_BWI(x)
+#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
+#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
+#define UART_WP7816_T_TYPE1_CWI(x)   UART_WP7816T1_CWI(x)
+#define UART_BASES                   UART_BASE_PTRS
+#define USB_BASES                    USB_BASE_PTRS
+#define USBDCD_BASES                 USBDCD_BASE_PTRS
+#define VREF_BASES                   VREF_BASE_PTRS
+#define WDOG_BASES                   WDOG_BASE_PTRS
+#define Watchdog_IRQn                WDOG_EWM_IRQn
+#define Watchdog_IRQHandler          WDOG_EWM_IRQHandler
+#define LPTimer_IRQn                 LPTMR0_IRQn
+#define LPTimer_IRQHandler           LPTMR0_IRQHandler
+#define LLW_IRQn                     LLWU_IRQn
+#define LLW_IRQHandler               LLWU_IRQHandler
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MK64F12_H_) */
+  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+  #if (MCU_MEM_MAP_VERSION != 0x0200u)
+    #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+      #warning There are included two not compatible versions of memory maps. Please check possible differences.
+    #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+  #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
+#endif  /* #if !defined(MK64F12_H_) */
+
+/* MK64F12.h, eof. */
diff --git a/Workspace/4part1/SDK/platform/devices/MK64F12/include/MK64F12_extension.h b/Workspace/4part1/SDK/platform/devices/MK64F12/include/MK64F12_extension.h
new file mode 100644
index 0000000..c47b6c4
--- /dev/null
+++ b/Workspace/4part1/SDK/platform/devices/MK64F12/include/MK64F12_extension.h
@@ -0,0 +1,63846 @@
+/*
+** ###################################################################
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150612
+**
+**     Abstract:
+**         Extension to the CMSIS register access layer header.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __MK64F12_EXTENSION_H__
+#define __MK64F12_EXTENSION_H__
+
+#include "MK64F12.h"
+#include "fsl_bitaccess.h"
+
+#if defined(__IAR_SYSTEMS_ICC__)
+  /*
+   * Suppress "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)"
+   * as some register descriptions contain code examples
+   */
+  #pragma diag_suppress=pm008
+#endif
+
+/*
+ * MK64F12 ADC
+ *
+ * Analog-to-Digital Converter
+ *
+ * Registers defined in this header file:
+ * - ADC_SC1 - ADC Status and Control Registers 1
+ * - ADC_CFG1 - ADC Configuration Register 1
+ * - ADC_CFG2 - ADC Configuration Register 2
+ * - ADC_R - ADC Data Result Register
+ * - ADC_CV1 - Compare Value Registers
+ * - ADC_CV2 - Compare Value Registers
+ * - ADC_SC2 - Status and Control Register 2
+ * - ADC_SC3 - Status and Control Register 3
+ * - ADC_OFS - ADC Offset Correction Register
+ * - ADC_PG - ADC Plus-Side Gain Register
+ * - ADC_MG - ADC Minus-Side Gain Register
+ * - ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ */
+
+#define ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
+#define ADC0_IDX (0U) /*!< Instance number for ADC0. */
+#define ADC1_IDX (1U) /*!< Instance number for ADC1. */
+
+/*******************************************************************************
+ * ADC_SC1 - ADC Status and Control Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC1 - ADC Status and Control Registers 1 (RW)
+ *
+ * Reset value: 0x0000001FU
+ *
+ * SC1A is used for both software and hardware trigger modes of operation. To
+ * allow sequential conversions of the ADC to be triggered by internal peripherals,
+ * the ADC can have more than one status and control register: one for each
+ * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
+ * for use only in hardware trigger mode. See the chip configuration information
+ * about the number of SC1n registers specific to this device. The SC1n registers
+ * have identical fields, and are used in a "ping-pong" approach to control ADC
+ * operation. At any one point in time, only one of the SC1n registers is actively
+ * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
+ * a conversion is allowed, and vice-versa for any of the SC1n registers specific
+ * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
+ * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
+ * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
+ * value other than all 1s. Writing any of the SC1n registers while that specific
+ * SC1n register is actively controlling a conversion aborts the current conversion.
+ * None of the SC1B-SC1n registers are used for software trigger operation and
+ * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC1 register
+ */
+/*@{*/
+#define ADC_RD_SC1(base, index)  (ADC_SC1_REG(base, index))
+#define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value))
+#define ADC_RMW_SC1(base, index, mask, value) (ADC_WR_SC1(base, index, (ADC_RD_SC1(base, index) & ~(mask)) | (value)))
+#define ADC_SET_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) |  (value)))
+#define ADC_CLR_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) & ~(value)))
+#define ADC_TOG_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC1 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC1, field ADCH[4:0] (RW)
+ *
+ * Selects one of the input channels. The input channel decode depends on the
+ * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
+ * DADMx. Some of the input channel options in the bitfield-setting descriptions might
+ * not be available for your device. For the actual ADC channel assignments for
+ * your device, see the Chip Configuration details. The successive approximation
+ * converter subsystem is turned off when the channel select bits are all set,
+ * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
+ * isolation of the input channel from all sources. Terminating continuous
+ * conversions this way prevents an additional single conversion from being performed. It
+ * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
+ * when continuous conversions are not enabled because the module automatically
+ * enters a low-power state when a conversion completes.
+ *
+ * Values:
+ * - 0b00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
+ *     selected as input.
+ * - 0b00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
+ *     selected as input.
+ * - 0b00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
+ *     selected as input.
+ * - 0b00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
+ *     selected as input.
+ * - 0b00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b11000 - Reserved.
+ * - 0b11001 - Reserved.
+ * - 0b11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input;
+ *     when DIFF=1, Temp Sensor (differential) is selected as input.
+ * - 0b11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
+ *     DIFF=1, Bandgap (differential) is selected as input.
+ * - 0b11100 - Reserved.
+ * - 0b11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
+ *     (differential) is selected as input. Voltage reference selected is determined
+ *     by SC2[REFSEL].
+ * - 0b11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
+ *     reserved. Voltage reference selected is determined by SC2[REFSEL].
+ * - 0b11111 - Module is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_ADCH field. */
+#define ADC_RD_SC1_ADCH(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_ADCH_MASK) >> ADC_SC1_ADCH_SHIFT)
+#define ADC_BRD_SC1_ADCH(base, index) (ADC_RD_SC1_ADCH(base, index))
+
+/*! @brief Set the ADCH field to a new value. */
+#define ADC_WR_SC1_ADCH(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_ADCH_MASK, ADC_SC1_ADCH(value)))
+#define ADC_BWR_SC1_ADCH(base, index, value) (ADC_WR_SC1_ADCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field DIFF[5] (RW)
+ *
+ * Configures the ADC to operate in differential mode. When enabled, this mode
+ * automatically selects from the differential channels, and changes the
+ * conversion algorithm and the number of cycles to complete a conversion.
+ *
+ * Values:
+ * - 0b0 - Single-ended conversions and input channels are selected.
+ * - 0b1 - Differential conversions and input channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_DIFF field. */
+#define ADC_RD_SC1_DIFF(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_DIFF_MASK) >> ADC_SC1_DIFF_SHIFT)
+#define ADC_BRD_SC1_DIFF(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT))
+
+/*! @brief Set the DIFF field to a new value. */
+#define ADC_WR_SC1_DIFF(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_DIFF_MASK, ADC_SC1_DIFF(value)))
+#define ADC_BWR_SC1_DIFF(base, index, value) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field AIEN[6] (RW)
+ *
+ * Enables conversion complete interrupts. When COCO becomes set while the
+ * respective AIEN is high, an interrupt is asserted.
+ *
+ * Values:
+ * - 0b0 - Conversion complete interrupt is disabled.
+ * - 0b1 - Conversion complete interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_AIEN field. */
+#define ADC_RD_SC1_AIEN(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIEN_SHIFT)
+#define ADC_BRD_SC1_AIEN(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT))
+
+/*! @brief Set the AIEN field to a new value. */
+#define ADC_WR_SC1_AIEN(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_AIEN_MASK, ADC_SC1_AIEN(value)))
+#define ADC_BWR_SC1_AIEN(base, index, value) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field COCO[7] (RO)
+ *
+ * This is a read-only field that is set each time a conversion is completed
+ * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
+ * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
+ * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
+ * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
+ * COCO is set upon completion of the selected number of conversions (determined
+ * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
+ * COCO is cleared when the respective SC1n register is written or when the
+ * respective Rn register is read.
+ *
+ * Values:
+ * - 0b0 - Conversion is not completed.
+ * - 0b1 - Conversion is completed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_COCO field. */
+#define ADC_RD_SC1_COCO(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_COCO_MASK) >> ADC_SC1_COCO_SHIFT)
+#define ADC_BRD_SC1_COCO(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG1 - ADC Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG1 - ADC Configuration Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The configuration Register 1 (CFG1) selects the mode of operation, clock
+ * source, clock divide, and configuration for low power or long sample time.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG1 register
+ */
+/*@{*/
+#define ADC_RD_CFG1(base)        (ADC_CFG1_REG(base))
+#define ADC_WR_CFG1(base, value) (ADC_CFG1_REG(base) = (value))
+#define ADC_RMW_CFG1(base, mask, value) (ADC_WR_CFG1(base, (ADC_RD_CFG1(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) |  (value)))
+#define ADC_CLR_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) & ~(value)))
+#define ADC_TOG_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
+ *
+ * Selects the input clock source to generate the internal clock, ADCK. Note
+ * that when the ADACK clock source is selected, it is not required to be active
+ * prior to conversion start. When it is selected and it is not active prior to a
+ * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
+ * the start of a conversion and deactivated when conversions are terminated. In
+ * this case, there is an associated clock startup delay each time the clock
+ * source is re-activated.
+ *
+ * Values:
+ * - 0b00 - Bus clock
+ * - 0b01 - Alternate clock 2 (ALTCLK2)
+ * - 0b10 - Alternate clock (ALTCLK)
+ * - 0b11 - Asynchronous clock (ADACK)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADICLK field. */
+#define ADC_RD_CFG1_ADICLK(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADICLK_MASK) >> ADC_CFG1_ADICLK_SHIFT)
+#define ADC_BRD_CFG1_ADICLK(base) (ADC_RD_CFG1_ADICLK(base))
+
+/*! @brief Set the ADICLK field to a new value. */
+#define ADC_WR_CFG1_ADICLK(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADICLK_MASK, ADC_CFG1_ADICLK(value)))
+#define ADC_BWR_CFG1_ADICLK(base, value) (ADC_WR_CFG1_ADICLK(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field MODE[3:2] (RW)
+ *
+ * Selects the ADC resolution mode.
+ *
+ * Values:
+ * - 0b00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
+ *     differential 9-bit conversion with 2's complement output.
+ * - 0b01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it
+ *     is differential 13-bit conversion with 2's complement output.
+ * - 0b10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it
+ *     is differential 11-bit conversion with 2's complement output
+ * - 0b11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it
+ *     is differential 16-bit conversion with 2's complement output
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_MODE field. */
+#define ADC_RD_CFG1_MODE(base) ((ADC_CFG1_REG(base) & ADC_CFG1_MODE_MASK) >> ADC_CFG1_MODE_SHIFT)
+#define ADC_BRD_CFG1_MODE(base) (ADC_RD_CFG1_MODE(base))
+
+/*! @brief Set the MODE field to a new value. */
+#define ADC_WR_CFG1_MODE(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_MODE_MASK, ADC_CFG1_MODE(value)))
+#define ADC_BWR_CFG1_MODE(base, value) (ADC_WR_CFG1_MODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLSMP[4] (RW)
+ *
+ * Selects between different sample times based on the conversion mode selected.
+ * This field adjusts the sample period to allow higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption if
+ * continuous conversions are enabled and high conversion rates are not required.
+ * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
+ * extent of the long sample time.
+ *
+ * Values:
+ * - 0b0 - Short sample time.
+ * - 0b1 - Long sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
+#define ADC_RD_CFG1_ADLSMP(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLSMP_MASK) >> ADC_CFG1_ADLSMP_SHIFT)
+#define ADC_BRD_CFG1_ADLSMP(base) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT))
+
+/*! @brief Set the ADLSMP field to a new value. */
+#define ADC_WR_CFG1_ADLSMP(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLSMP_MASK, ADC_CFG1_ADLSMP(value)))
+#define ADC_BWR_CFG1_ADLSMP(base, value) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADIV[6:5] (RW)
+ *
+ * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
+ *
+ * Values:
+ * - 0b00 - The divide ratio is 1 and the clock rate is input clock.
+ * - 0b01 - The divide ratio is 2 and the clock rate is (input clock)/2.
+ * - 0b10 - The divide ratio is 4 and the clock rate is (input clock)/4.
+ * - 0b11 - The divide ratio is 8 and the clock rate is (input clock)/8.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADIV field. */
+#define ADC_RD_CFG1_ADIV(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT)
+#define ADC_BRD_CFG1_ADIV(base) (ADC_RD_CFG1_ADIV(base))
+
+/*! @brief Set the ADIV field to a new value. */
+#define ADC_WR_CFG1_ADIV(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADIV_MASK, ADC_CFG1_ADIV(value)))
+#define ADC_BWR_CFG1_ADIV(base, value) (ADC_WR_CFG1_ADIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLPC[7] (RW)
+ *
+ * Controls the power configuration of the successive approximation converter.
+ * This optimizes power consumption when higher sample rates are not required.
+ *
+ * Values:
+ * - 0b0 - Normal power configuration.
+ * - 0b1 - Low-power configuration. The power is reduced at the expense of
+ *     maximum clock speed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLPC field. */
+#define ADC_RD_CFG1_ADLPC(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLPC_MASK) >> ADC_CFG1_ADLPC_SHIFT)
+#define ADC_BRD_CFG1_ADLPC(base) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT))
+
+/*! @brief Set the ADLPC field to a new value. */
+#define ADC_WR_CFG1_ADLPC(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLPC_MASK, ADC_CFG1_ADLPC(value)))
+#define ADC_BWR_CFG1_ADLPC(base, value) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG2 - ADC Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG2 - ADC Configuration Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Configuration Register 2 (CFG2) selects the special high-speed configuration
+ * for very high speed conversions and selects the long sample time duration
+ * during long sample mode.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG2 register
+ */
+/*@{*/
+#define ADC_RD_CFG2(base)        (ADC_CFG2_REG(base))
+#define ADC_WR_CFG2(base, value) (ADC_CFG2_REG(base) = (value))
+#define ADC_RMW_CFG2(base, mask, value) (ADC_WR_CFG2(base, (ADC_RD_CFG2(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) |  (value)))
+#define ADC_CLR_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) & ~(value)))
+#define ADC_TOG_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
+ *
+ * Selects between the extended sample times when long sample time is selected,
+ * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption when
+ * continuous conversions are enabled if high conversion rates are not required.
+ *
+ * Values:
+ * - 0b00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
+ *     total.
+ * - 0b01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
+ * - 0b10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
+ * - 0b11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
+#define ADC_RD_CFG2_ADLSTS(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADLSTS_MASK) >> ADC_CFG2_ADLSTS_SHIFT)
+#define ADC_BRD_CFG2_ADLSTS(base) (ADC_RD_CFG2_ADLSTS(base))
+
+/*! @brief Set the ADLSTS field to a new value. */
+#define ADC_WR_CFG2_ADLSTS(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADLSTS_MASK, ADC_CFG2_ADLSTS(value)))
+#define ADC_BWR_CFG2_ADLSTS(base, value) (ADC_WR_CFG2_ADLSTS(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADHSC[2] (RW)
+ *
+ * Configures the ADC for very high-speed operation. The conversion sequence is
+ * altered with 2 ADCK cycles added to the conversion time to allow higher speed
+ * conversion clocks.
+ *
+ * Values:
+ * - 0b0 - Normal conversion sequence selected.
+ * - 0b1 - High-speed conversion sequence selected with 2 additional ADCK cycles
+ *     to total conversion time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADHSC field. */
+#define ADC_RD_CFG2_ADHSC(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADHSC_MASK) >> ADC_CFG2_ADHSC_SHIFT)
+#define ADC_BRD_CFG2_ADHSC(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT))
+
+/*! @brief Set the ADHSC field to a new value. */
+#define ADC_WR_CFG2_ADHSC(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADHSC_MASK, ADC_CFG2_ADHSC(value)))
+#define ADC_BWR_CFG2_ADHSC(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADACKEN[3] (RW)
+ *
+ * Enables the asynchronous clock source and the clock source output regardless
+ * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
+ * asynchronous clock may be used by other modules. See chip configuration
+ * information. Setting this field allows the clock to be used even while the ADC is
+ * idle or operating from a different clock source. Also, latency of initiating a
+ * single or first-continuous conversion with the asynchronous clock selected is
+ * reduced because the ADACK clock is already operational.
+ *
+ * Values:
+ * - 0b0 - Asynchronous clock output disabled; Asynchronous clock is enabled
+ *     only if selected by ADICLK and a conversion is active.
+ * - 0b1 - Asynchronous clock and clock output is enabled regardless of the
+ *     state of the ADC.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
+#define ADC_RD_CFG2_ADACKEN(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADACKEN_MASK) >> ADC_CFG2_ADACKEN_SHIFT)
+#define ADC_BRD_CFG2_ADACKEN(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT))
+
+/*! @brief Set the ADACKEN field to a new value. */
+#define ADC_WR_CFG2_ADACKEN(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADACKEN_MASK, ADC_CFG2_ADACKEN(value)))
+#define ADC_BWR_CFG2_ADACKEN(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field MUXSEL[4] (RW)
+ *
+ * Changes the ADC mux setting to select between alternate sets of ADC channels.
+ *
+ * Values:
+ * - 0b0 - ADxxa channels are selected.
+ * - 0b1 - ADxxb channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
+#define ADC_RD_CFG2_MUXSEL(base) ((ADC_CFG2_REG(base) & ADC_CFG2_MUXSEL_MASK) >> ADC_CFG2_MUXSEL_SHIFT)
+#define ADC_BRD_CFG2_MUXSEL(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT))
+
+/*! @brief Set the MUXSEL field to a new value. */
+#define ADC_WR_CFG2_MUXSEL(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_MUXSEL_MASK, ADC_CFG2_MUXSEL(value)))
+#define ADC_BWR_CFG2_MUXSEL(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_R - ADC Data Result Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_R - ADC Data Result Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The data result registers (Rn) contain the result of an ADC conversion of the
+ * channel selected by the corresponding status and channel control register
+ * (SC1A:SC1n). For every status and channel control register, there is a
+ * corresponding data result register. Unused bits in R n are cleared in unsigned
+ * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
+ * For example, when configured for 10-bit single-ended mode, D[15:10] are
+ * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
+ * that is, bit 10 extended through bit 15. The following table describes the
+ * behavior of the data result registers in the different modes of operation. Data
+ * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
+ * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
+ * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
+ * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
+ * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
+ * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
+ * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
+ * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
+ * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
+ * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
+ * 2's complement data if indicated
+ */
+/*!
+ * @name Constants and macros for entire ADC_R register
+ */
+/*@{*/
+#define ADC_RD_R(base, index)    (ADC_R_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_R bitfields
+ */
+
+/*!
+ * @name Register ADC_R, field D[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_R_D field. */
+#define ADC_RD_R_D(base, index) ((ADC_R_REG(base, index) & ADC_R_D_MASK) >> ADC_R_D_SHIFT)
+#define ADC_BRD_R_D(base, index) (ADC_RD_R_D(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV1 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV1 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV1 register
+ */
+/*@{*/
+#define ADC_RD_CV1(base)         (ADC_CV1_REG(base))
+#define ADC_WR_CV1(base, value)  (ADC_CV1_REG(base) = (value))
+#define ADC_RMW_CV1(base, mask, value) (ADC_WR_CV1(base, (ADC_RD_CV1(base) & ~(mask)) | (value)))
+#define ADC_SET_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) |  (value)))
+#define ADC_CLR_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) & ~(value)))
+#define ADC_TOG_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV1, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV1_CV field. */
+#define ADC_RD_CV1_CV(base)  ((ADC_CV1_REG(base) & ADC_CV1_CV_MASK) >> ADC_CV1_CV_SHIFT)
+#define ADC_BRD_CV1_CV(base) (ADC_RD_CV1_CV(base))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV1_CV(base, value) (ADC_RMW_CV1(base, ADC_CV1_CV_MASK, ADC_CV1_CV(value)))
+#define ADC_BWR_CV1_CV(base, value) (ADC_WR_CV1_CV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV2 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV2 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV2 register
+ */
+/*@{*/
+#define ADC_RD_CV2(base)         (ADC_CV2_REG(base))
+#define ADC_WR_CV2(base, value)  (ADC_CV2_REG(base) = (value))
+#define ADC_RMW_CV2(base, mask, value) (ADC_WR_CV2(base, (ADC_RD_CV2(base) & ~(mask)) | (value)))
+#define ADC_SET_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) |  (value)))
+#define ADC_CLR_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) & ~(value)))
+#define ADC_TOG_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV2, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV2_CV field. */
+#define ADC_RD_CV2_CV(base)  ((ADC_CV2_REG(base) & ADC_CV2_CV_MASK) >> ADC_CV2_CV_SHIFT)
+#define ADC_BRD_CV2_CV(base) (ADC_RD_CV2_CV(base))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV2_CV(base, value) (ADC_RMW_CV2(base, ADC_CV2_CV_MASK, ADC_CV2_CV(value)))
+#define ADC_BWR_CV2_CV(base, value) (ADC_WR_CV2_CV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC2 - Status and Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC2 - Status and Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The status and control register 2 (SC2) contains the conversion active,
+ * hardware/software trigger select, compare function, and voltage reference select of
+ * the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC2 register
+ */
+/*@{*/
+#define ADC_RD_SC2(base)         (ADC_SC2_REG(base))
+#define ADC_WR_SC2(base, value)  (ADC_SC2_REG(base) = (value))
+#define ADC_RMW_SC2(base, mask, value) (ADC_WR_SC2(base, (ADC_RD_SC2(base) & ~(mask)) | (value)))
+#define ADC_SET_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) |  (value)))
+#define ADC_CLR_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) & ~(value)))
+#define ADC_TOG_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC2 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC2, field REFSEL[1:0] (RW)
+ *
+ * Selects the voltage reference source used for conversions.
+ *
+ * Values:
+ * - 0b00 - Default voltage reference pin pair, that is, external pins VREFH and
+ *     VREFL
+ * - 0b01 - Alternate reference pair, that is, VALTH and VALTL . This pair may
+ *     be additional external pins or internal sources depending on the MCU
+ *     configuration. See the chip configuration information for details specific to
+ *     this MCU
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_REFSEL field. */
+#define ADC_RD_SC2_REFSEL(base) ((ADC_SC2_REG(base) & ADC_SC2_REFSEL_MASK) >> ADC_SC2_REFSEL_SHIFT)
+#define ADC_BRD_SC2_REFSEL(base) (ADC_RD_SC2_REFSEL(base))
+
+/*! @brief Set the REFSEL field to a new value. */
+#define ADC_WR_SC2_REFSEL(base, value) (ADC_RMW_SC2(base, ADC_SC2_REFSEL_MASK, ADC_SC2_REFSEL(value)))
+#define ADC_BWR_SC2_REFSEL(base, value) (ADC_WR_SC2_REFSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field DMAEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled and will assert the ADC DMA request during an ADC
+ *     conversion complete event noted when any of the SC1n[COCO] flags is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_DMAEN field. */
+#define ADC_RD_SC2_DMAEN(base) ((ADC_SC2_REG(base) & ADC_SC2_DMAEN_MASK) >> ADC_SC2_DMAEN_SHIFT)
+#define ADC_BRD_SC2_DMAEN(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define ADC_WR_SC2_DMAEN(base, value) (ADC_RMW_SC2(base, ADC_SC2_DMAEN_MASK, ADC_SC2_DMAEN(value)))
+#define ADC_BWR_SC2_DMAEN(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACREN[3] (RW)
+ *
+ * Configures the compare function to check if the conversion result of the
+ * input being monitored is either between or outside the range formed by CV1 and CV2
+ * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
+ * effect.
+ *
+ * Values:
+ * - 0b0 - Range function disabled. Only CV1 is compared.
+ * - 0b1 - Range function enabled. Both CV1 and CV2 are compared.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACREN field. */
+#define ADC_RD_SC2_ACREN(base) ((ADC_SC2_REG(base) & ADC_SC2_ACREN_MASK) >> ADC_SC2_ACREN_SHIFT)
+#define ADC_BRD_SC2_ACREN(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT))
+
+/*! @brief Set the ACREN field to a new value. */
+#define ADC_WR_SC2_ACREN(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACREN_MASK, ADC_SC2_ACREN(value)))
+#define ADC_BWR_SC2_ACREN(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFGT[4] (RW)
+ *
+ * Configures the compare function to check the conversion result relative to
+ * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
+ * have any effect.
+ *
+ * Values:
+ * - 0b0 - Configures less than threshold, outside range not inclusive and
+ *     inside range not inclusive; functionality based on the values placed in CV1 and
+ *     CV2.
+ * - 0b1 - Configures greater than or equal to threshold, outside and inside
+ *     ranges inclusive; functionality based on the values placed in CV1 and CV2.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFGT field. */
+#define ADC_RD_SC2_ACFGT(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFGT_MASK) >> ADC_SC2_ACFGT_SHIFT)
+#define ADC_BRD_SC2_ACFGT(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT))
+
+/*! @brief Set the ACFGT field to a new value. */
+#define ADC_WR_SC2_ACFGT(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFGT_MASK, ADC_SC2_ACFGT(value)))
+#define ADC_BWR_SC2_ACFGT(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFE[5] (RW)
+ *
+ * Enables the compare function.
+ *
+ * Values:
+ * - 0b0 - Compare function disabled.
+ * - 0b1 - Compare function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFE field. */
+#define ADC_RD_SC2_ACFE(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFE_MASK) >> ADC_SC2_ACFE_SHIFT)
+#define ADC_BRD_SC2_ACFE(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT))
+
+/*! @brief Set the ACFE field to a new value. */
+#define ADC_WR_SC2_ACFE(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFE_MASK, ADC_SC2_ACFE(value)))
+#define ADC_BWR_SC2_ACFE(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADTRG[6] (RW)
+ *
+ * Selects the type of trigger used for initiating a conversion. Two types of
+ * trigger are selectable: Software trigger: When software trigger is selected, a
+ * conversion is initiated following a write to SC1A. Hardware trigger: When
+ * hardware trigger is selected, a conversion is initiated following the assertion of
+ * the ADHWT input after a pulse of the ADHWTSn input.
+ *
+ * Values:
+ * - 0b0 - Software trigger selected.
+ * - 0b1 - Hardware trigger selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADTRG field. */
+#define ADC_RD_SC2_ADTRG(base) ((ADC_SC2_REG(base) & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT)
+#define ADC_BRD_SC2_ADTRG(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT))
+
+/*! @brief Set the ADTRG field to a new value. */
+#define ADC_WR_SC2_ADTRG(base, value) (ADC_RMW_SC2(base, ADC_SC2_ADTRG_MASK, ADC_SC2_ADTRG(value)))
+#define ADC_BWR_SC2_ADTRG(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADACT[7] (RO)
+ *
+ * Indicates that a conversion or hardware averaging is in progress. ADACT is
+ * set when a conversion is initiated and cleared when a conversion is completed or
+ * aborted.
+ *
+ * Values:
+ * - 0b0 - Conversion not in progress.
+ * - 0b1 - Conversion in progress.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADACT field. */
+#define ADC_RD_SC2_ADACT(base) ((ADC_SC2_REG(base) & ADC_SC2_ADACT_MASK) >> ADC_SC2_ADACT_SHIFT)
+#define ADC_BRD_SC2_ADACT(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADACT_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC3 - Status and Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC3 - Status and Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Status and Control Register 3 (SC3) controls the calibration, continuous
+ * convert, and hardware averaging functions of the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC3 register
+ */
+/*@{*/
+#define ADC_RD_SC3(base)         (ADC_SC3_REG(base))
+#define ADC_WR_SC3(base, value)  (ADC_SC3_REG(base) = (value))
+#define ADC_RMW_SC3(base, mask, value) (ADC_WR_SC3(base, (ADC_RD_SC3(base) & ~(mask)) | (value)))
+#define ADC_SET_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) |  (value)))
+#define ADC_CLR_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) & ~(value)))
+#define ADC_TOG_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC3 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC3, field AVGS[1:0] (RW)
+ *
+ * Determines how many ADC conversions will be averaged to create the ADC
+ * average result.
+ *
+ * Values:
+ * - 0b00 - 4 samples averaged.
+ * - 0b01 - 8 samples averaged.
+ * - 0b10 - 16 samples averaged.
+ * - 0b11 - 32 samples averaged.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGS field. */
+#define ADC_RD_SC3_AVGS(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGS_MASK) >> ADC_SC3_AVGS_SHIFT)
+#define ADC_BRD_SC3_AVGS(base) (ADC_RD_SC3_AVGS(base))
+
+/*! @brief Set the AVGS field to a new value. */
+#define ADC_WR_SC3_AVGS(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGS_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGS(value)))
+#define ADC_BWR_SC3_AVGS(base, value) (ADC_WR_SC3_AVGS(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field AVGE[2] (RW)
+ *
+ * Enables the hardware average function of the ADC.
+ *
+ * Values:
+ * - 0b0 - Hardware average function disabled.
+ * - 0b1 - Hardware average function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGE field. */
+#define ADC_RD_SC3_AVGE(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGE_MASK) >> ADC_SC3_AVGE_SHIFT)
+#define ADC_BRD_SC3_AVGE(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT))
+
+/*! @brief Set the AVGE field to a new value. */
+#define ADC_WR_SC3_AVGE(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGE_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGE(value)))
+#define ADC_BWR_SC3_AVGE(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field ADCO[3] (RW)
+ *
+ * Enables continuous conversions.
+ *
+ * Values:
+ * - 0b0 - One conversion or one set of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ * - 0b1 - Continuous conversions or sets of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_ADCO field. */
+#define ADC_RD_SC3_ADCO(base) ((ADC_SC3_REG(base) & ADC_SC3_ADCO_MASK) >> ADC_SC3_ADCO_SHIFT)
+#define ADC_BRD_SC3_ADCO(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT))
+
+/*! @brief Set the ADCO field to a new value. */
+#define ADC_WR_SC3_ADCO(base, value) (ADC_RMW_SC3(base, (ADC_SC3_ADCO_MASK | ADC_SC3_CALF_MASK), ADC_SC3_ADCO(value)))
+#define ADC_BWR_SC3_ADCO(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CALF[6] (W1C)
+ *
+ * Displays the result of the calibration sequence. The calibration sequence
+ * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
+ * entered before the calibration sequence completes. Writing 1 to CALF clears it.
+ *
+ * Values:
+ * - 0b0 - Calibration completed normally.
+ * - 0b1 - Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CALF field. */
+#define ADC_RD_SC3_CALF(base) ((ADC_SC3_REG(base) & ADC_SC3_CALF_MASK) >> ADC_SC3_CALF_SHIFT)
+#define ADC_BRD_SC3_CALF(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT))
+
+/*! @brief Set the CALF field to a new value. */
+#define ADC_WR_SC3_CALF(base, value) (ADC_RMW_SC3(base, ADC_SC3_CALF_MASK, ADC_SC3_CALF(value)))
+#define ADC_BWR_SC3_CALF(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CAL[7] (RW)
+ *
+ * Begins the calibration sequence when set. This field stays set while the
+ * calibration is in progress and is cleared when the calibration sequence is
+ * completed. CALF must be checked to determine the result of the calibration sequence.
+ * Once started, the calibration routine cannot be interrupted by writes to the
+ * ADC registers or the results will be invalid and CALF will set. Setting CAL
+ * will abort any current conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CAL field. */
+#define ADC_RD_SC3_CAL(base) ((ADC_SC3_REG(base) & ADC_SC3_CAL_MASK) >> ADC_SC3_CAL_SHIFT)
+#define ADC_BRD_SC3_CAL(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT))
+
+/*! @brief Set the CAL field to a new value. */
+#define ADC_WR_SC3_CAL(base, value) (ADC_RMW_SC3(base, (ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK), ADC_SC3_CAL(value)))
+#define ADC_BWR_SC3_CAL(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_OFS - ADC Offset Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_OFS - ADC Offset Correction Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * The ADC Offset Correction Register (OFS) contains the user-selected or
+ * calibration-generated offset error correction value. This register is a 2's
+ * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
+ * conversion and the result is transferred into the result registers, Rn. If the
+ * result is greater than the maximum or less than the minimum result value, it is
+ * forced to the appropriate limit for the current mode of operation.
+ */
+/*!
+ * @name Constants and macros for entire ADC_OFS register
+ */
+/*@{*/
+#define ADC_RD_OFS(base)         (ADC_OFS_REG(base))
+#define ADC_WR_OFS(base, value)  (ADC_OFS_REG(base) = (value))
+#define ADC_RMW_OFS(base, mask, value) (ADC_WR_OFS(base, (ADC_RD_OFS(base) & ~(mask)) | (value)))
+#define ADC_SET_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) |  (value)))
+#define ADC_CLR_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) & ~(value)))
+#define ADC_TOG_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_OFS bitfields
+ */
+
+/*!
+ * @name Register ADC_OFS, field OFS[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_OFS_OFS field. */
+#define ADC_RD_OFS_OFS(base) ((ADC_OFS_REG(base) & ADC_OFS_OFS_MASK) >> ADC_OFS_OFS_SHIFT)
+#define ADC_BRD_OFS_OFS(base) (ADC_RD_OFS_OFS(base))
+
+/*! @brief Set the OFS field to a new value. */
+#define ADC_WR_OFS_OFS(base, value) (ADC_RMW_OFS(base, ADC_OFS_OFS_MASK, ADC_OFS_OFS(value)))
+#define ADC_BWR_OFS_OFS(base, value) (ADC_WR_OFS_OFS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_PG - ADC Plus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_PG - ADC Plus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Plus-Side Gain Register (PG) contains the gain error correction for the
+ * plus-side input in differential mode or the overall conversion in single-ended
+ * mode. PG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
+ * written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_PG register
+ */
+/*@{*/
+#define ADC_RD_PG(base)          (ADC_PG_REG(base))
+#define ADC_WR_PG(base, value)   (ADC_PG_REG(base) = (value))
+#define ADC_RMW_PG(base, mask, value) (ADC_WR_PG(base, (ADC_RD_PG(base) & ~(mask)) | (value)))
+#define ADC_SET_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) |  (value)))
+#define ADC_CLR_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) & ~(value)))
+#define ADC_TOG_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_PG bitfields
+ */
+
+/*!
+ * @name Register ADC_PG, field PG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_PG_PG field. */
+#define ADC_RD_PG_PG(base)   ((ADC_PG_REG(base) & ADC_PG_PG_MASK) >> ADC_PG_PG_SHIFT)
+#define ADC_BRD_PG_PG(base)  (ADC_RD_PG_PG(base))
+
+/*! @brief Set the PG field to a new value. */
+#define ADC_WR_PG_PG(base, value) (ADC_RMW_PG(base, ADC_PG_PG_MASK, ADC_PG_PG(value)))
+#define ADC_BWR_PG_PG(base, value) (ADC_WR_PG_PG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_MG - ADC Minus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_MG - ADC Minus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Minus-Side Gain Register (MG) contains the gain error correction for the
+ * minus-side input in differential mode. This register is ignored in
+ * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
+ * be written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_MG register
+ */
+/*@{*/
+#define ADC_RD_MG(base)          (ADC_MG_REG(base))
+#define ADC_WR_MG(base, value)   (ADC_MG_REG(base) = (value))
+#define ADC_RMW_MG(base, mask, value) (ADC_WR_MG(base, (ADC_RD_MG(base) & ~(mask)) | (value)))
+#define ADC_SET_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) |  (value)))
+#define ADC_CLR_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) & ~(value)))
+#define ADC_TOG_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_MG bitfields
+ */
+
+/*!
+ * @name Register ADC_MG, field MG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_MG_MG field. */
+#define ADC_RD_MG_MG(base)   ((ADC_MG_REG(base) & ADC_MG_MG_MASK) >> ADC_MG_MG_SHIFT)
+#define ADC_BRD_MG_MG(base)  (ADC_RD_MG_MG(base))
+
+/*! @brief Set the MG field to a new value. */
+#define ADC_WR_MG_MG(base, value) (ADC_RMW_MG(base, ADC_MG_MG_MASK, ADC_MG_MG(value)))
+#define ADC_BWR_MG_MG(base, value) (ADC_WR_MG_MG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
+ * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
+ * when the self-calibration sequence is done, that is, CAL is cleared. If these
+ * registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPD register
+ */
+/*@{*/
+#define ADC_RD_CLPD(base)        (ADC_CLPD_REG(base))
+#define ADC_WR_CLPD(base, value) (ADC_CLPD_REG(base) = (value))
+#define ADC_RMW_CLPD(base, mask, value) (ADC_WR_CLPD(base, (ADC_RD_CLPD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) |  (value)))
+#define ADC_CLR_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) & ~(value)))
+#define ADC_TOG_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPD, field CLPD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPD_CLPD field. */
+#define ADC_RD_CLPD_CLPD(base) ((ADC_CLPD_REG(base) & ADC_CLPD_CLPD_MASK) >> ADC_CLPD_CLPD_SHIFT)
+#define ADC_BRD_CLPD_CLPD(base) (ADC_RD_CLPD_CLPD(base))
+
+/*! @brief Set the CLPD field to a new value. */
+#define ADC_WR_CLPD_CLPD(base, value) (ADC_RMW_CLPD(base, ADC_CLPD_CLPD_MASK, ADC_CLPD_CLPD(value)))
+#define ADC_BWR_CLPD_CLPD(base, value) (ADC_WR_CLPD_CLPD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPS register
+ */
+/*@{*/
+#define ADC_RD_CLPS(base)        (ADC_CLPS_REG(base))
+#define ADC_WR_CLPS(base, value) (ADC_CLPS_REG(base) = (value))
+#define ADC_RMW_CLPS(base, mask, value) (ADC_WR_CLPS(base, (ADC_RD_CLPS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) |  (value)))
+#define ADC_CLR_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) & ~(value)))
+#define ADC_TOG_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPS, field CLPS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPS_CLPS field. */
+#define ADC_RD_CLPS_CLPS(base) ((ADC_CLPS_REG(base) & ADC_CLPS_CLPS_MASK) >> ADC_CLPS_CLPS_SHIFT)
+#define ADC_BRD_CLPS_CLPS(base) (ADC_RD_CLPS_CLPS(base))
+
+/*! @brief Set the CLPS field to a new value. */
+#define ADC_WR_CLPS_CLPS(base, value) (ADC_RMW_CLPS(base, ADC_CLPS_CLPS_MASK, ADC_CLPS_CLPS(value)))
+#define ADC_BWR_CLPS_CLPS(base, value) (ADC_WR_CLPS_CLPS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP4 register
+ */
+/*@{*/
+#define ADC_RD_CLP4(base)        (ADC_CLP4_REG(base))
+#define ADC_WR_CLP4(base, value) (ADC_CLP4_REG(base) = (value))
+#define ADC_RMW_CLP4(base, mask, value) (ADC_WR_CLP4(base, (ADC_RD_CLP4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) |  (value)))
+#define ADC_CLR_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) & ~(value)))
+#define ADC_TOG_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP4, field CLP4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP4_CLP4 field. */
+#define ADC_RD_CLP4_CLP4(base) ((ADC_CLP4_REG(base) & ADC_CLP4_CLP4_MASK) >> ADC_CLP4_CLP4_SHIFT)
+#define ADC_BRD_CLP4_CLP4(base) (ADC_RD_CLP4_CLP4(base))
+
+/*! @brief Set the CLP4 field to a new value. */
+#define ADC_WR_CLP4_CLP4(base, value) (ADC_RMW_CLP4(base, ADC_CLP4_CLP4_MASK, ADC_CLP4_CLP4(value)))
+#define ADC_BWR_CLP4_CLP4(base, value) (ADC_WR_CLP4_CLP4(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP3 register
+ */
+/*@{*/
+#define ADC_RD_CLP3(base)        (ADC_CLP3_REG(base))
+#define ADC_WR_CLP3(base, value) (ADC_CLP3_REG(base) = (value))
+#define ADC_RMW_CLP3(base, mask, value) (ADC_WR_CLP3(base, (ADC_RD_CLP3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) |  (value)))
+#define ADC_CLR_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) & ~(value)))
+#define ADC_TOG_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP3, field CLP3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP3_CLP3 field. */
+#define ADC_RD_CLP3_CLP3(base) ((ADC_CLP3_REG(base) & ADC_CLP3_CLP3_MASK) >> ADC_CLP3_CLP3_SHIFT)
+#define ADC_BRD_CLP3_CLP3(base) (ADC_RD_CLP3_CLP3(base))
+
+/*! @brief Set the CLP3 field to a new value. */
+#define ADC_WR_CLP3_CLP3(base, value) (ADC_RMW_CLP3(base, ADC_CLP3_CLP3_MASK, ADC_CLP3_CLP3(value)))
+#define ADC_BWR_CLP3_CLP3(base, value) (ADC_WR_CLP3_CLP3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP2 register
+ */
+/*@{*/
+#define ADC_RD_CLP2(base)        (ADC_CLP2_REG(base))
+#define ADC_WR_CLP2(base, value) (ADC_CLP2_REG(base) = (value))
+#define ADC_RMW_CLP2(base, mask, value) (ADC_WR_CLP2(base, (ADC_RD_CLP2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) |  (value)))
+#define ADC_CLR_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) & ~(value)))
+#define ADC_TOG_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP2, field CLP2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP2_CLP2 field. */
+#define ADC_RD_CLP2_CLP2(base) ((ADC_CLP2_REG(base) & ADC_CLP2_CLP2_MASK) >> ADC_CLP2_CLP2_SHIFT)
+#define ADC_BRD_CLP2_CLP2(base) (ADC_RD_CLP2_CLP2(base))
+
+/*! @brief Set the CLP2 field to a new value. */
+#define ADC_WR_CLP2_CLP2(base, value) (ADC_RMW_CLP2(base, ADC_CLP2_CLP2_MASK, ADC_CLP2_CLP2(value)))
+#define ADC_BWR_CLP2_CLP2(base, value) (ADC_WR_CLP2_CLP2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP1 register
+ */
+/*@{*/
+#define ADC_RD_CLP1(base)        (ADC_CLP1_REG(base))
+#define ADC_WR_CLP1(base, value) (ADC_CLP1_REG(base) = (value))
+#define ADC_RMW_CLP1(base, mask, value) (ADC_WR_CLP1(base, (ADC_RD_CLP1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) |  (value)))
+#define ADC_CLR_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) & ~(value)))
+#define ADC_TOG_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP1, field CLP1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP1_CLP1 field. */
+#define ADC_RD_CLP1_CLP1(base) ((ADC_CLP1_REG(base) & ADC_CLP1_CLP1_MASK) >> ADC_CLP1_CLP1_SHIFT)
+#define ADC_BRD_CLP1_CLP1(base) (ADC_RD_CLP1_CLP1(base))
+
+/*! @brief Set the CLP1 field to a new value. */
+#define ADC_WR_CLP1_CLP1(base, value) (ADC_RMW_CLP1(base, ADC_CLP1_CLP1_MASK, ADC_CLP1_CLP1(value)))
+#define ADC_BWR_CLP1_CLP1(base, value) (ADC_WR_CLP1_CLP1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP0 register
+ */
+/*@{*/
+#define ADC_RD_CLP0(base)        (ADC_CLP0_REG(base))
+#define ADC_WR_CLP0(base, value) (ADC_CLP0_REG(base) = (value))
+#define ADC_RMW_CLP0(base, mask, value) (ADC_WR_CLP0(base, (ADC_RD_CLP0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) |  (value)))
+#define ADC_CLR_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) & ~(value)))
+#define ADC_TOG_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP0, field CLP0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP0_CLP0 field. */
+#define ADC_RD_CLP0_CLP0(base) ((ADC_CLP0_REG(base) & ADC_CLP0_CLP0_MASK) >> ADC_CLP0_CLP0_SHIFT)
+#define ADC_BRD_CLP0_CLP0(base) (ADC_RD_CLP0_CLP0(base))
+
+/*! @brief Set the CLP0 field to a new value. */
+#define ADC_WR_CLP0_CLP0(base, value) (ADC_RMW_CLP0(base, ADC_CLP0_CLP0_MASK, ADC_CLP0_CLP0(value)))
+#define ADC_BWR_CLP0_CLP0(base, value) (ADC_WR_CLP0_CLP0(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Minus-Side General Calibration Value (CLMx) registers contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
+ * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
+ * set when the self-calibration sequence is done, that is, CAL is cleared. If
+ * these registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMD register
+ */
+/*@{*/
+#define ADC_RD_CLMD(base)        (ADC_CLMD_REG(base))
+#define ADC_WR_CLMD(base, value) (ADC_CLMD_REG(base) = (value))
+#define ADC_RMW_CLMD(base, mask, value) (ADC_WR_CLMD(base, (ADC_RD_CLMD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) |  (value)))
+#define ADC_CLR_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) & ~(value)))
+#define ADC_TOG_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMD, field CLMD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMD_CLMD field. */
+#define ADC_RD_CLMD_CLMD(base) ((ADC_CLMD_REG(base) & ADC_CLMD_CLMD_MASK) >> ADC_CLMD_CLMD_SHIFT)
+#define ADC_BRD_CLMD_CLMD(base) (ADC_RD_CLMD_CLMD(base))
+
+/*! @brief Set the CLMD field to a new value. */
+#define ADC_WR_CLMD_CLMD(base, value) (ADC_RMW_CLMD(base, ADC_CLMD_CLMD_MASK, ADC_CLMD_CLMD(value)))
+#define ADC_BWR_CLMD_CLMD(base, value) (ADC_WR_CLMD_CLMD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMS register
+ */
+/*@{*/
+#define ADC_RD_CLMS(base)        (ADC_CLMS_REG(base))
+#define ADC_WR_CLMS(base, value) (ADC_CLMS_REG(base) = (value))
+#define ADC_RMW_CLMS(base, mask, value) (ADC_WR_CLMS(base, (ADC_RD_CLMS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) |  (value)))
+#define ADC_CLR_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) & ~(value)))
+#define ADC_TOG_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMS, field CLMS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMS_CLMS field. */
+#define ADC_RD_CLMS_CLMS(base) ((ADC_CLMS_REG(base) & ADC_CLMS_CLMS_MASK) >> ADC_CLMS_CLMS_SHIFT)
+#define ADC_BRD_CLMS_CLMS(base) (ADC_RD_CLMS_CLMS(base))
+
+/*! @brief Set the CLMS field to a new value. */
+#define ADC_WR_CLMS_CLMS(base, value) (ADC_RMW_CLMS(base, ADC_CLMS_CLMS_MASK, ADC_CLMS_CLMS(value)))
+#define ADC_BWR_CLMS_CLMS(base, value) (ADC_WR_CLMS_CLMS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM4 register
+ */
+/*@{*/
+#define ADC_RD_CLM4(base)        (ADC_CLM4_REG(base))
+#define ADC_WR_CLM4(base, value) (ADC_CLM4_REG(base) = (value))
+#define ADC_RMW_CLM4(base, mask, value) (ADC_WR_CLM4(base, (ADC_RD_CLM4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) |  (value)))
+#define ADC_CLR_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) & ~(value)))
+#define ADC_TOG_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM4, field CLM4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM4_CLM4 field. */
+#define ADC_RD_CLM4_CLM4(base) ((ADC_CLM4_REG(base) & ADC_CLM4_CLM4_MASK) >> ADC_CLM4_CLM4_SHIFT)
+#define ADC_BRD_CLM4_CLM4(base) (ADC_RD_CLM4_CLM4(base))
+
+/*! @brief Set the CLM4 field to a new value. */
+#define ADC_WR_CLM4_CLM4(base, value) (ADC_RMW_CLM4(base, ADC_CLM4_CLM4_MASK, ADC_CLM4_CLM4(value)))
+#define ADC_BWR_CLM4_CLM4(base, value) (ADC_WR_CLM4_CLM4(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM3 register
+ */
+/*@{*/
+#define ADC_RD_CLM3(base)        (ADC_CLM3_REG(base))
+#define ADC_WR_CLM3(base, value) (ADC_CLM3_REG(base) = (value))
+#define ADC_RMW_CLM3(base, mask, value) (ADC_WR_CLM3(base, (ADC_RD_CLM3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) |  (value)))
+#define ADC_CLR_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) & ~(value)))
+#define ADC_TOG_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM3, field CLM3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM3_CLM3 field. */
+#define ADC_RD_CLM3_CLM3(base) ((ADC_CLM3_REG(base) & ADC_CLM3_CLM3_MASK) >> ADC_CLM3_CLM3_SHIFT)
+#define ADC_BRD_CLM3_CLM3(base) (ADC_RD_CLM3_CLM3(base))
+
+/*! @brief Set the CLM3 field to a new value. */
+#define ADC_WR_CLM3_CLM3(base, value) (ADC_RMW_CLM3(base, ADC_CLM3_CLM3_MASK, ADC_CLM3_CLM3(value)))
+#define ADC_BWR_CLM3_CLM3(base, value) (ADC_WR_CLM3_CLM3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM2 register
+ */
+/*@{*/
+#define ADC_RD_CLM2(base)        (ADC_CLM2_REG(base))
+#define ADC_WR_CLM2(base, value) (ADC_CLM2_REG(base) = (value))
+#define ADC_RMW_CLM2(base, mask, value) (ADC_WR_CLM2(base, (ADC_RD_CLM2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) |  (value)))
+#define ADC_CLR_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) & ~(value)))
+#define ADC_TOG_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM2, field CLM2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM2_CLM2 field. */
+#define ADC_RD_CLM2_CLM2(base) ((ADC_CLM2_REG(base) & ADC_CLM2_CLM2_MASK) >> ADC_CLM2_CLM2_SHIFT)
+#define ADC_BRD_CLM2_CLM2(base) (ADC_RD_CLM2_CLM2(base))
+
+/*! @brief Set the CLM2 field to a new value. */
+#define ADC_WR_CLM2_CLM2(base, value) (ADC_RMW_CLM2(base, ADC_CLM2_CLM2_MASK, ADC_CLM2_CLM2(value)))
+#define ADC_BWR_CLM2_CLM2(base, value) (ADC_WR_CLM2_CLM2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM1 register
+ */
+/*@{*/
+#define ADC_RD_CLM1(base)        (ADC_CLM1_REG(base))
+#define ADC_WR_CLM1(base, value) (ADC_CLM1_REG(base) = (value))
+#define ADC_RMW_CLM1(base, mask, value) (ADC_WR_CLM1(base, (ADC_RD_CLM1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) |  (value)))
+#define ADC_CLR_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) & ~(value)))
+#define ADC_TOG_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM1, field CLM1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM1_CLM1 field. */
+#define ADC_RD_CLM1_CLM1(base) ((ADC_CLM1_REG(base) & ADC_CLM1_CLM1_MASK) >> ADC_CLM1_CLM1_SHIFT)
+#define ADC_BRD_CLM1_CLM1(base) (ADC_RD_CLM1_CLM1(base))
+
+/*! @brief Set the CLM1 field to a new value. */
+#define ADC_WR_CLM1_CLM1(base, value) (ADC_RMW_CLM1(base, ADC_CLM1_CLM1_MASK, ADC_CLM1_CLM1(value)))
+#define ADC_BWR_CLM1_CLM1(base, value) (ADC_WR_CLM1_CLM1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM0 register
+ */
+/*@{*/
+#define ADC_RD_CLM0(base)        (ADC_CLM0_REG(base))
+#define ADC_WR_CLM0(base, value) (ADC_CLM0_REG(base) = (value))
+#define ADC_RMW_CLM0(base, mask, value) (ADC_WR_CLM0(base, (ADC_RD_CLM0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) |  (value)))
+#define ADC_CLR_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) & ~(value)))
+#define ADC_TOG_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM0, field CLM0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM0_CLM0 field. */
+#define ADC_RD_CLM0_CLM0(base) ((ADC_CLM0_REG(base) & ADC_CLM0_CLM0_MASK) >> ADC_CLM0_CLM0_SHIFT)
+#define ADC_BRD_CLM0_CLM0(base) (ADC_RD_CLM0_CLM0(base))
+
+/*! @brief Set the CLM0 field to a new value. */
+#define ADC_WR_CLM0_CLM0(base, value) (ADC_RMW_CLM0(base, ADC_CLM0_CLM0_MASK, ADC_CLM0_CLM0(value)))
+#define ADC_BWR_CLM0_CLM0(base, value) (ADC_WR_CLM0_CLM0(base, value))
+/*@}*/
+
+/*
+ * MK64F12 AIPS
+ *
+ * AIPS-Lite Bridge
+ *
+ * Registers defined in this header file:
+ * - AIPS_MPRA - Master Privilege Register A
+ * - AIPS_PACRA - Peripheral Access Control Register
+ * - AIPS_PACRB - Peripheral Access Control Register
+ * - AIPS_PACRC - Peripheral Access Control Register
+ * - AIPS_PACRD - Peripheral Access Control Register
+ * - AIPS_PACRE - Peripheral Access Control Register
+ * - AIPS_PACRF - Peripheral Access Control Register
+ * - AIPS_PACRG - Peripheral Access Control Register
+ * - AIPS_PACRH - Peripheral Access Control Register
+ * - AIPS_PACRI - Peripheral Access Control Register
+ * - AIPS_PACRJ - Peripheral Access Control Register
+ * - AIPS_PACRK - Peripheral Access Control Register
+ * - AIPS_PACRL - Peripheral Access Control Register
+ * - AIPS_PACRM - Peripheral Access Control Register
+ * - AIPS_PACRN - Peripheral Access Control Register
+ * - AIPS_PACRO - Peripheral Access Control Register
+ * - AIPS_PACRP - Peripheral Access Control Register
+ * - AIPS_PACRU - Peripheral Access Control Register
+ */
+
+#define AIPS_INSTANCE_COUNT (2U) /*!< Number of instances of the AIPS module. */
+#define AIPS0_IDX (0U) /*!< Instance number for AIPS0. */
+#define AIPS1_IDX (1U) /*!< Instance number for AIPS1. */
+
+/*******************************************************************************
+ * AIPS_MPRA - Master Privilege Register A
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_MPRA - Master Privilege Register A (RW)
+ *
+ * Reset value: 0x77700000U
+ *
+ * The MPRA specifies identical 4-bit fields defining the access-privilege level
+ * associated with a bus master to various peripherals on the chip. The register
+ * provides one field per bus master. At reset, the default value loaded into
+ * the MPRA fields is chip-specific. See the chip configuration details for the
+ * value of a particular device. A register field that maps to an unimplemented
+ * master or peripheral behaves as read-only-zero. Each master is assigned a logical
+ * ID from 0 to 15. See the master logical ID assignment table in the
+ * chip-specific AIPS information.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_MPRA register
+ */
+/*@{*/
+#define AIPS_RD_MPRA(base)       (AIPS_MPRA_REG(base))
+#define AIPS_WR_MPRA(base, value) (AIPS_MPRA_REG(base) = (value))
+#define AIPS_RMW_MPRA(base, mask, value) (AIPS_WR_MPRA(base, (AIPS_RD_MPRA(base) & ~(mask)) | (value)))
+#define AIPS_SET_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) |  (value)))
+#define AIPS_CLR_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) & ~(value)))
+#define AIPS_TOG_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_MPRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_MPRA, field MPL5[8] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL5 field. */
+#define AIPS_RD_MPRA_MPL5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL5_MASK) >> AIPS_MPRA_MPL5_SHIFT)
+#define AIPS_BRD_MPRA_MPL5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL5_SHIFT))
+
+/*! @brief Set the MPL5 field to a new value. */
+#define AIPS_WR_MPRA_MPL5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL5_MASK, AIPS_MPRA_MPL5(value)))
+#define AIPS_BWR_MPRA_MPL5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW5[9] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW5 field. */
+#define AIPS_RD_MPRA_MTW5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW5_MASK) >> AIPS_MPRA_MTW5_SHIFT)
+#define AIPS_BRD_MPRA_MTW5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW5_SHIFT))
+
+/*! @brief Set the MTW5 field to a new value. */
+#define AIPS_WR_MPRA_MTW5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW5_MASK, AIPS_MPRA_MTW5(value)))
+#define AIPS_BWR_MPRA_MTW5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR5[10] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR5 field. */
+#define AIPS_RD_MPRA_MTR5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR5_MASK) >> AIPS_MPRA_MTR5_SHIFT)
+#define AIPS_BRD_MPRA_MTR5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR5_SHIFT))
+
+/*! @brief Set the MTR5 field to a new value. */
+#define AIPS_WR_MPRA_MTR5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR5_MASK, AIPS_MPRA_MTR5(value)))
+#define AIPS_BWR_MPRA_MTR5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL4[12] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL4 field. */
+#define AIPS_RD_MPRA_MPL4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL4_MASK) >> AIPS_MPRA_MPL4_SHIFT)
+#define AIPS_BRD_MPRA_MPL4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL4_SHIFT))
+
+/*! @brief Set the MPL4 field to a new value. */
+#define AIPS_WR_MPRA_MPL4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL4_MASK, AIPS_MPRA_MPL4(value)))
+#define AIPS_BWR_MPRA_MPL4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW4[13] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW4 field. */
+#define AIPS_RD_MPRA_MTW4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW4_MASK) >> AIPS_MPRA_MTW4_SHIFT)
+#define AIPS_BRD_MPRA_MTW4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW4_SHIFT))
+
+/*! @brief Set the MTW4 field to a new value. */
+#define AIPS_WR_MPRA_MTW4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW4_MASK, AIPS_MPRA_MTW4(value)))
+#define AIPS_BWR_MPRA_MTW4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR4[14] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR4 field. */
+#define AIPS_RD_MPRA_MTR4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR4_MASK) >> AIPS_MPRA_MTR4_SHIFT)
+#define AIPS_BRD_MPRA_MTR4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR4_SHIFT))
+
+/*! @brief Set the MTR4 field to a new value. */
+#define AIPS_WR_MPRA_MTR4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR4_MASK, AIPS_MPRA_MTR4(value)))
+#define AIPS_BWR_MPRA_MTR4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL3[16] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL3 field. */
+#define AIPS_RD_MPRA_MPL3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL3_MASK) >> AIPS_MPRA_MPL3_SHIFT)
+#define AIPS_BRD_MPRA_MPL3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL3_SHIFT))
+
+/*! @brief Set the MPL3 field to a new value. */
+#define AIPS_WR_MPRA_MPL3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL3_MASK, AIPS_MPRA_MPL3(value)))
+#define AIPS_BWR_MPRA_MPL3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW3[17] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW3 field. */
+#define AIPS_RD_MPRA_MTW3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW3_MASK) >> AIPS_MPRA_MTW3_SHIFT)
+#define AIPS_BRD_MPRA_MTW3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW3_SHIFT))
+
+/*! @brief Set the MTW3 field to a new value. */
+#define AIPS_WR_MPRA_MTW3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW3_MASK, AIPS_MPRA_MTW3(value)))
+#define AIPS_BWR_MPRA_MTW3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR3[18] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR3 field. */
+#define AIPS_RD_MPRA_MTR3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR3_MASK) >> AIPS_MPRA_MTR3_SHIFT)
+#define AIPS_BRD_MPRA_MTR3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR3_SHIFT))
+
+/*! @brief Set the MTR3 field to a new value. */
+#define AIPS_WR_MPRA_MTR3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR3_MASK, AIPS_MPRA_MTR3(value)))
+#define AIPS_BWR_MPRA_MTR3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL2[20] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL2 field. */
+#define AIPS_RD_MPRA_MPL2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL2_MASK) >> AIPS_MPRA_MPL2_SHIFT)
+#define AIPS_BRD_MPRA_MPL2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL2_SHIFT))
+
+/*! @brief Set the MPL2 field to a new value. */
+#define AIPS_WR_MPRA_MPL2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL2_MASK, AIPS_MPRA_MPL2(value)))
+#define AIPS_BWR_MPRA_MPL2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW2[21] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW2 field. */
+#define AIPS_RD_MPRA_MTW2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW2_MASK) >> AIPS_MPRA_MTW2_SHIFT)
+#define AIPS_BRD_MPRA_MTW2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW2_SHIFT))
+
+/*! @brief Set the MTW2 field to a new value. */
+#define AIPS_WR_MPRA_MTW2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW2_MASK, AIPS_MPRA_MTW2(value)))
+#define AIPS_BWR_MPRA_MTW2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR2[22] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR2 field. */
+#define AIPS_RD_MPRA_MTR2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR2_MASK) >> AIPS_MPRA_MTR2_SHIFT)
+#define AIPS_BRD_MPRA_MTR2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR2_SHIFT))
+
+/*! @brief Set the MTR2 field to a new value. */
+#define AIPS_WR_MPRA_MTR2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR2_MASK, AIPS_MPRA_MTR2(value)))
+#define AIPS_BWR_MPRA_MTR2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL1[24] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL1 field. */
+#define AIPS_RD_MPRA_MPL1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL1_MASK) >> AIPS_MPRA_MPL1_SHIFT)
+#define AIPS_BRD_MPRA_MPL1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL1_SHIFT))
+
+/*! @brief Set the MPL1 field to a new value. */
+#define AIPS_WR_MPRA_MPL1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL1_MASK, AIPS_MPRA_MPL1(value)))
+#define AIPS_BWR_MPRA_MPL1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW1[25] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW1 field. */
+#define AIPS_RD_MPRA_MTW1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW1_MASK) >> AIPS_MPRA_MTW1_SHIFT)
+#define AIPS_BRD_MPRA_MTW1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW1_SHIFT))
+
+/*! @brief Set the MTW1 field to a new value. */
+#define AIPS_WR_MPRA_MTW1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW1_MASK, AIPS_MPRA_MTW1(value)))
+#define AIPS_BWR_MPRA_MTW1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR1[26] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR1 field. */
+#define AIPS_RD_MPRA_MTR1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR1_MASK) >> AIPS_MPRA_MTR1_SHIFT)
+#define AIPS_BRD_MPRA_MTR1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR1_SHIFT))
+
+/*! @brief Set the MTR1 field to a new value. */
+#define AIPS_WR_MPRA_MTR1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR1_MASK, AIPS_MPRA_MTR1(value)))
+#define AIPS_BWR_MPRA_MTR1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL0[28] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL0 field. */
+#define AIPS_RD_MPRA_MPL0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL0_MASK) >> AIPS_MPRA_MPL0_SHIFT)
+#define AIPS_BRD_MPRA_MPL0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL0_SHIFT))
+
+/*! @brief Set the MPL0 field to a new value. */
+#define AIPS_WR_MPRA_MPL0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL0_MASK, AIPS_MPRA_MPL0(value)))
+#define AIPS_BWR_MPRA_MPL0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW0[29] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW0 field. */
+#define AIPS_RD_MPRA_MTW0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW0_MASK) >> AIPS_MPRA_MTW0_SHIFT)
+#define AIPS_BRD_MPRA_MTW0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW0_SHIFT))
+
+/*! @brief Set the MTW0 field to a new value. */
+#define AIPS_WR_MPRA_MTW0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW0_MASK, AIPS_MPRA_MTW0(value)))
+#define AIPS_BWR_MPRA_MTW0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR0[30] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR0 field. */
+#define AIPS_RD_MPRA_MTR0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR0_MASK) >> AIPS_MPRA_MTR0_SHIFT)
+#define AIPS_BRD_MPRA_MTR0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR0_SHIFT))
+
+/*! @brief Set the MTR0 field to a new value. */
+#define AIPS_WR_MPRA_MTR0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR0_MASK, AIPS_MPRA_MTR0(value)))
+#define AIPS_BWR_MPRA_MTR0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRA - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRA - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x50004000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRA register
+ */
+/*@{*/
+#define AIPS_RD_PACRA(base)      (AIPS_PACRA_REG(base))
+#define AIPS_WR_PACRA(base, value) (AIPS_PACRA_REG(base) = (value))
+#define AIPS_RMW_PACRA(base, mask, value) (AIPS_WR_PACRA(base, (AIPS_RD_PACRA(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) |  (value)))
+#define AIPS_CLR_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) & ~(value)))
+#define AIPS_TOG_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRA, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP7 field. */
+#define AIPS_RD_PACRA_TP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP7_MASK) >> AIPS_PACRA_TP7_SHIFT)
+#define AIPS_BRD_PACRA_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRA_TP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP7_MASK, AIPS_PACRA_TP7(value)))
+#define AIPS_BWR_PACRA_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP7 field. */
+#define AIPS_RD_PACRA_WP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP7_MASK) >> AIPS_PACRA_WP7_SHIFT)
+#define AIPS_BRD_PACRA_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRA_WP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP7_MASK, AIPS_PACRA_WP7(value)))
+#define AIPS_BWR_PACRA_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP7 field. */
+#define AIPS_RD_PACRA_SP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP7_MASK) >> AIPS_PACRA_SP7_SHIFT)
+#define AIPS_BRD_PACRA_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRA_SP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP7_MASK, AIPS_PACRA_SP7(value)))
+#define AIPS_BWR_PACRA_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP6 field. */
+#define AIPS_RD_PACRA_TP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP6_MASK) >> AIPS_PACRA_TP6_SHIFT)
+#define AIPS_BRD_PACRA_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRA_TP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP6_MASK, AIPS_PACRA_TP6(value)))
+#define AIPS_BWR_PACRA_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP6 field. */
+#define AIPS_RD_PACRA_WP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP6_MASK) >> AIPS_PACRA_WP6_SHIFT)
+#define AIPS_BRD_PACRA_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRA_WP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP6_MASK, AIPS_PACRA_WP6(value)))
+#define AIPS_BWR_PACRA_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP6 field. */
+#define AIPS_RD_PACRA_SP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP6_MASK) >> AIPS_PACRA_SP6_SHIFT)
+#define AIPS_BRD_PACRA_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRA_SP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP6_MASK, AIPS_PACRA_SP6(value)))
+#define AIPS_BWR_PACRA_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP5 field. */
+#define AIPS_RD_PACRA_TP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP5_MASK) >> AIPS_PACRA_TP5_SHIFT)
+#define AIPS_BRD_PACRA_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRA_TP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP5_MASK, AIPS_PACRA_TP5(value)))
+#define AIPS_BWR_PACRA_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP5 field. */
+#define AIPS_RD_PACRA_WP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP5_MASK) >> AIPS_PACRA_WP5_SHIFT)
+#define AIPS_BRD_PACRA_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRA_WP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP5_MASK, AIPS_PACRA_WP5(value)))
+#define AIPS_BWR_PACRA_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP5 field. */
+#define AIPS_RD_PACRA_SP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP5_MASK) >> AIPS_PACRA_SP5_SHIFT)
+#define AIPS_BRD_PACRA_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRA_SP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP5_MASK, AIPS_PACRA_SP5(value)))
+#define AIPS_BWR_PACRA_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP4 field. */
+#define AIPS_RD_PACRA_TP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP4_MASK) >> AIPS_PACRA_TP4_SHIFT)
+#define AIPS_BRD_PACRA_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRA_TP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP4_MASK, AIPS_PACRA_TP4(value)))
+#define AIPS_BWR_PACRA_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP4 field. */
+#define AIPS_RD_PACRA_WP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP4_MASK) >> AIPS_PACRA_WP4_SHIFT)
+#define AIPS_BRD_PACRA_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRA_WP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP4_MASK, AIPS_PACRA_WP4(value)))
+#define AIPS_BWR_PACRA_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP4 field. */
+#define AIPS_RD_PACRA_SP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP4_MASK) >> AIPS_PACRA_SP4_SHIFT)
+#define AIPS_BRD_PACRA_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRA_SP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP4_MASK, AIPS_PACRA_SP4(value)))
+#define AIPS_BWR_PACRA_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP3 field. */
+#define AIPS_RD_PACRA_TP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP3_MASK) >> AIPS_PACRA_TP3_SHIFT)
+#define AIPS_BRD_PACRA_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRA_TP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP3_MASK, AIPS_PACRA_TP3(value)))
+#define AIPS_BWR_PACRA_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP3 field. */
+#define AIPS_RD_PACRA_WP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP3_MASK) >> AIPS_PACRA_WP3_SHIFT)
+#define AIPS_BRD_PACRA_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRA_WP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP3_MASK, AIPS_PACRA_WP3(value)))
+#define AIPS_BWR_PACRA_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP3 field. */
+#define AIPS_RD_PACRA_SP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP3_MASK) >> AIPS_PACRA_SP3_SHIFT)
+#define AIPS_BRD_PACRA_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRA_SP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP3_MASK, AIPS_PACRA_SP3(value)))
+#define AIPS_BWR_PACRA_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP2 field. */
+#define AIPS_RD_PACRA_TP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP2_MASK) >> AIPS_PACRA_TP2_SHIFT)
+#define AIPS_BRD_PACRA_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRA_TP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP2_MASK, AIPS_PACRA_TP2(value)))
+#define AIPS_BWR_PACRA_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP2 field. */
+#define AIPS_RD_PACRA_WP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP2_MASK) >> AIPS_PACRA_WP2_SHIFT)
+#define AIPS_BRD_PACRA_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRA_WP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP2_MASK, AIPS_PACRA_WP2(value)))
+#define AIPS_BWR_PACRA_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP2 field. */
+#define AIPS_RD_PACRA_SP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP2_MASK) >> AIPS_PACRA_SP2_SHIFT)
+#define AIPS_BRD_PACRA_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRA_SP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP2_MASK, AIPS_PACRA_SP2(value)))
+#define AIPS_BWR_PACRA_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP1 field. */
+#define AIPS_RD_PACRA_TP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP1_MASK) >> AIPS_PACRA_TP1_SHIFT)
+#define AIPS_BRD_PACRA_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRA_TP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP1_MASK, AIPS_PACRA_TP1(value)))
+#define AIPS_BWR_PACRA_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP1 field. */
+#define AIPS_RD_PACRA_WP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP1_MASK) >> AIPS_PACRA_WP1_SHIFT)
+#define AIPS_BRD_PACRA_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRA_WP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP1_MASK, AIPS_PACRA_WP1(value)))
+#define AIPS_BWR_PACRA_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP1 field. */
+#define AIPS_RD_PACRA_SP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP1_MASK) >> AIPS_PACRA_SP1_SHIFT)
+#define AIPS_BRD_PACRA_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRA_SP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP1_MASK, AIPS_PACRA_SP1(value)))
+#define AIPS_BWR_PACRA_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP0 field. */
+#define AIPS_RD_PACRA_TP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP0_MASK) >> AIPS_PACRA_TP0_SHIFT)
+#define AIPS_BRD_PACRA_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRA_TP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP0_MASK, AIPS_PACRA_TP0(value)))
+#define AIPS_BWR_PACRA_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP0 field. */
+#define AIPS_RD_PACRA_WP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP0_MASK) >> AIPS_PACRA_WP0_SHIFT)
+#define AIPS_BRD_PACRA_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRA_WP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP0_MASK, AIPS_PACRA_WP0(value)))
+#define AIPS_BWR_PACRA_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP0 field. */
+#define AIPS_RD_PACRA_SP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP0_MASK) >> AIPS_PACRA_SP0_SHIFT)
+#define AIPS_BRD_PACRA_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRA_SP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP0_MASK, AIPS_PACRA_SP0(value)))
+#define AIPS_BWR_PACRA_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRB - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRB - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44004400U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRB register
+ */
+/*@{*/
+#define AIPS_RD_PACRB(base)      (AIPS_PACRB_REG(base))
+#define AIPS_WR_PACRB(base, value) (AIPS_PACRB_REG(base) = (value))
+#define AIPS_RMW_PACRB(base, mask, value) (AIPS_WR_PACRB(base, (AIPS_RD_PACRB(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) |  (value)))
+#define AIPS_CLR_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) & ~(value)))
+#define AIPS_TOG_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRB bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRB, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP7 field. */
+#define AIPS_RD_PACRB_TP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP7_MASK) >> AIPS_PACRB_TP7_SHIFT)
+#define AIPS_BRD_PACRB_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRB_TP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP7_MASK, AIPS_PACRB_TP7(value)))
+#define AIPS_BWR_PACRB_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP7 field. */
+#define AIPS_RD_PACRB_WP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP7_MASK) >> AIPS_PACRB_WP7_SHIFT)
+#define AIPS_BRD_PACRB_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRB_WP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP7_MASK, AIPS_PACRB_WP7(value)))
+#define AIPS_BWR_PACRB_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP7 field. */
+#define AIPS_RD_PACRB_SP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP7_MASK) >> AIPS_PACRB_SP7_SHIFT)
+#define AIPS_BRD_PACRB_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRB_SP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP7_MASK, AIPS_PACRB_SP7(value)))
+#define AIPS_BWR_PACRB_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP6 field. */
+#define AIPS_RD_PACRB_TP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP6_MASK) >> AIPS_PACRB_TP6_SHIFT)
+#define AIPS_BRD_PACRB_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRB_TP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP6_MASK, AIPS_PACRB_TP6(value)))
+#define AIPS_BWR_PACRB_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP6 field. */
+#define AIPS_RD_PACRB_WP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP6_MASK) >> AIPS_PACRB_WP6_SHIFT)
+#define AIPS_BRD_PACRB_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRB_WP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP6_MASK, AIPS_PACRB_WP6(value)))
+#define AIPS_BWR_PACRB_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP6 field. */
+#define AIPS_RD_PACRB_SP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP6_MASK) >> AIPS_PACRB_SP6_SHIFT)
+#define AIPS_BRD_PACRB_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRB_SP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP6_MASK, AIPS_PACRB_SP6(value)))
+#define AIPS_BWR_PACRB_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP5 field. */
+#define AIPS_RD_PACRB_TP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP5_MASK) >> AIPS_PACRB_TP5_SHIFT)
+#define AIPS_BRD_PACRB_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRB_TP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP5_MASK, AIPS_PACRB_TP5(value)))
+#define AIPS_BWR_PACRB_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP5 field. */
+#define AIPS_RD_PACRB_WP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP5_MASK) >> AIPS_PACRB_WP5_SHIFT)
+#define AIPS_BRD_PACRB_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRB_WP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP5_MASK, AIPS_PACRB_WP5(value)))
+#define AIPS_BWR_PACRB_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP5 field. */
+#define AIPS_RD_PACRB_SP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP5_MASK) >> AIPS_PACRB_SP5_SHIFT)
+#define AIPS_BRD_PACRB_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRB_SP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP5_MASK, AIPS_PACRB_SP5(value)))
+#define AIPS_BWR_PACRB_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP4 field. */
+#define AIPS_RD_PACRB_TP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP4_MASK) >> AIPS_PACRB_TP4_SHIFT)
+#define AIPS_BRD_PACRB_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRB_TP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP4_MASK, AIPS_PACRB_TP4(value)))
+#define AIPS_BWR_PACRB_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP4 field. */
+#define AIPS_RD_PACRB_WP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP4_MASK) >> AIPS_PACRB_WP4_SHIFT)
+#define AIPS_BRD_PACRB_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRB_WP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP4_MASK, AIPS_PACRB_WP4(value)))
+#define AIPS_BWR_PACRB_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP4 field. */
+#define AIPS_RD_PACRB_SP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP4_MASK) >> AIPS_PACRB_SP4_SHIFT)
+#define AIPS_BRD_PACRB_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRB_SP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP4_MASK, AIPS_PACRB_SP4(value)))
+#define AIPS_BWR_PACRB_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP3 field. */
+#define AIPS_RD_PACRB_TP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP3_MASK) >> AIPS_PACRB_TP3_SHIFT)
+#define AIPS_BRD_PACRB_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRB_TP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP3_MASK, AIPS_PACRB_TP3(value)))
+#define AIPS_BWR_PACRB_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP3 field. */
+#define AIPS_RD_PACRB_WP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP3_MASK) >> AIPS_PACRB_WP3_SHIFT)
+#define AIPS_BRD_PACRB_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRB_WP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP3_MASK, AIPS_PACRB_WP3(value)))
+#define AIPS_BWR_PACRB_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP3 field. */
+#define AIPS_RD_PACRB_SP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP3_MASK) >> AIPS_PACRB_SP3_SHIFT)
+#define AIPS_BRD_PACRB_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRB_SP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP3_MASK, AIPS_PACRB_SP3(value)))
+#define AIPS_BWR_PACRB_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP2 field. */
+#define AIPS_RD_PACRB_TP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP2_MASK) >> AIPS_PACRB_TP2_SHIFT)
+#define AIPS_BRD_PACRB_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRB_TP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP2_MASK, AIPS_PACRB_TP2(value)))
+#define AIPS_BWR_PACRB_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP2 field. */
+#define AIPS_RD_PACRB_WP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP2_MASK) >> AIPS_PACRB_WP2_SHIFT)
+#define AIPS_BRD_PACRB_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRB_WP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP2_MASK, AIPS_PACRB_WP2(value)))
+#define AIPS_BWR_PACRB_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP2 field. */
+#define AIPS_RD_PACRB_SP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP2_MASK) >> AIPS_PACRB_SP2_SHIFT)
+#define AIPS_BRD_PACRB_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRB_SP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP2_MASK, AIPS_PACRB_SP2(value)))
+#define AIPS_BWR_PACRB_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP1 field. */
+#define AIPS_RD_PACRB_TP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP1_MASK) >> AIPS_PACRB_TP1_SHIFT)
+#define AIPS_BRD_PACRB_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRB_TP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP1_MASK, AIPS_PACRB_TP1(value)))
+#define AIPS_BWR_PACRB_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP1 field. */
+#define AIPS_RD_PACRB_WP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP1_MASK) >> AIPS_PACRB_WP1_SHIFT)
+#define AIPS_BRD_PACRB_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRB_WP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP1_MASK, AIPS_PACRB_WP1(value)))
+#define AIPS_BWR_PACRB_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP1 field. */
+#define AIPS_RD_PACRB_SP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP1_MASK) >> AIPS_PACRB_SP1_SHIFT)
+#define AIPS_BRD_PACRB_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRB_SP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP1_MASK, AIPS_PACRB_SP1(value)))
+#define AIPS_BWR_PACRB_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP0 field. */
+#define AIPS_RD_PACRB_TP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP0_MASK) >> AIPS_PACRB_TP0_SHIFT)
+#define AIPS_BRD_PACRB_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRB_TP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP0_MASK, AIPS_PACRB_TP0(value)))
+#define AIPS_BWR_PACRB_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP0 field. */
+#define AIPS_RD_PACRB_WP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP0_MASK) >> AIPS_PACRB_WP0_SHIFT)
+#define AIPS_BRD_PACRB_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRB_WP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP0_MASK, AIPS_PACRB_WP0(value)))
+#define AIPS_BWR_PACRB_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP0 field. */
+#define AIPS_RD_PACRB_SP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP0_MASK) >> AIPS_PACRB_SP0_SHIFT)
+#define AIPS_BRD_PACRB_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRB_SP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP0_MASK, AIPS_PACRB_SP0(value)))
+#define AIPS_BWR_PACRB_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRC - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRC - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRC register
+ */
+/*@{*/
+#define AIPS_RD_PACRC(base)      (AIPS_PACRC_REG(base))
+#define AIPS_WR_PACRC(base, value) (AIPS_PACRC_REG(base) = (value))
+#define AIPS_RMW_PACRC(base, mask, value) (AIPS_WR_PACRC(base, (AIPS_RD_PACRC(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) |  (value)))
+#define AIPS_CLR_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) & ~(value)))
+#define AIPS_TOG_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRC bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRC, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP7 field. */
+#define AIPS_RD_PACRC_TP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP7_MASK) >> AIPS_PACRC_TP7_SHIFT)
+#define AIPS_BRD_PACRC_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRC_TP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP7_MASK, AIPS_PACRC_TP7(value)))
+#define AIPS_BWR_PACRC_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP7 field. */
+#define AIPS_RD_PACRC_WP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP7_MASK) >> AIPS_PACRC_WP7_SHIFT)
+#define AIPS_BRD_PACRC_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRC_WP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP7_MASK, AIPS_PACRC_WP7(value)))
+#define AIPS_BWR_PACRC_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP7 field. */
+#define AIPS_RD_PACRC_SP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP7_MASK) >> AIPS_PACRC_SP7_SHIFT)
+#define AIPS_BRD_PACRC_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRC_SP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP7_MASK, AIPS_PACRC_SP7(value)))
+#define AIPS_BWR_PACRC_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP6 field. */
+#define AIPS_RD_PACRC_TP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP6_MASK) >> AIPS_PACRC_TP6_SHIFT)
+#define AIPS_BRD_PACRC_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRC_TP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP6_MASK, AIPS_PACRC_TP6(value)))
+#define AIPS_BWR_PACRC_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP6 field. */
+#define AIPS_RD_PACRC_WP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP6_MASK) >> AIPS_PACRC_WP6_SHIFT)
+#define AIPS_BRD_PACRC_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRC_WP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP6_MASK, AIPS_PACRC_WP6(value)))
+#define AIPS_BWR_PACRC_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP6 field. */
+#define AIPS_RD_PACRC_SP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP6_MASK) >> AIPS_PACRC_SP6_SHIFT)
+#define AIPS_BRD_PACRC_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRC_SP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP6_MASK, AIPS_PACRC_SP6(value)))
+#define AIPS_BWR_PACRC_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP5 field. */
+#define AIPS_RD_PACRC_TP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP5_MASK) >> AIPS_PACRC_TP5_SHIFT)
+#define AIPS_BRD_PACRC_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRC_TP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP5_MASK, AIPS_PACRC_TP5(value)))
+#define AIPS_BWR_PACRC_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP5 field. */
+#define AIPS_RD_PACRC_WP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP5_MASK) >> AIPS_PACRC_WP5_SHIFT)
+#define AIPS_BRD_PACRC_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRC_WP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP5_MASK, AIPS_PACRC_WP5(value)))
+#define AIPS_BWR_PACRC_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP5 field. */
+#define AIPS_RD_PACRC_SP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP5_MASK) >> AIPS_PACRC_SP5_SHIFT)
+#define AIPS_BRD_PACRC_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRC_SP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP5_MASK, AIPS_PACRC_SP5(value)))
+#define AIPS_BWR_PACRC_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP4 field. */
+#define AIPS_RD_PACRC_TP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP4_MASK) >> AIPS_PACRC_TP4_SHIFT)
+#define AIPS_BRD_PACRC_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRC_TP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP4_MASK, AIPS_PACRC_TP4(value)))
+#define AIPS_BWR_PACRC_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP4 field. */
+#define AIPS_RD_PACRC_WP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP4_MASK) >> AIPS_PACRC_WP4_SHIFT)
+#define AIPS_BRD_PACRC_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRC_WP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP4_MASK, AIPS_PACRC_WP4(value)))
+#define AIPS_BWR_PACRC_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP4 field. */
+#define AIPS_RD_PACRC_SP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP4_MASK) >> AIPS_PACRC_SP4_SHIFT)
+#define AIPS_BRD_PACRC_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRC_SP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP4_MASK, AIPS_PACRC_SP4(value)))
+#define AIPS_BWR_PACRC_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP3 field. */
+#define AIPS_RD_PACRC_TP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP3_MASK) >> AIPS_PACRC_TP3_SHIFT)
+#define AIPS_BRD_PACRC_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRC_TP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP3_MASK, AIPS_PACRC_TP3(value)))
+#define AIPS_BWR_PACRC_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP3 field. */
+#define AIPS_RD_PACRC_WP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP3_MASK) >> AIPS_PACRC_WP3_SHIFT)
+#define AIPS_BRD_PACRC_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRC_WP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP3_MASK, AIPS_PACRC_WP3(value)))
+#define AIPS_BWR_PACRC_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP3 field. */
+#define AIPS_RD_PACRC_SP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP3_MASK) >> AIPS_PACRC_SP3_SHIFT)
+#define AIPS_BRD_PACRC_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRC_SP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP3_MASK, AIPS_PACRC_SP3(value)))
+#define AIPS_BWR_PACRC_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP2 field. */
+#define AIPS_RD_PACRC_TP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP2_MASK) >> AIPS_PACRC_TP2_SHIFT)
+#define AIPS_BRD_PACRC_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRC_TP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP2_MASK, AIPS_PACRC_TP2(value)))
+#define AIPS_BWR_PACRC_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP2 field. */
+#define AIPS_RD_PACRC_WP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP2_MASK) >> AIPS_PACRC_WP2_SHIFT)
+#define AIPS_BRD_PACRC_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRC_WP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP2_MASK, AIPS_PACRC_WP2(value)))
+#define AIPS_BWR_PACRC_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP2 field. */
+#define AIPS_RD_PACRC_SP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP2_MASK) >> AIPS_PACRC_SP2_SHIFT)
+#define AIPS_BRD_PACRC_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRC_SP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP2_MASK, AIPS_PACRC_SP2(value)))
+#define AIPS_BWR_PACRC_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP1 field. */
+#define AIPS_RD_PACRC_TP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP1_MASK) >> AIPS_PACRC_TP1_SHIFT)
+#define AIPS_BRD_PACRC_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRC_TP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP1_MASK, AIPS_PACRC_TP1(value)))
+#define AIPS_BWR_PACRC_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP1 field. */
+#define AIPS_RD_PACRC_WP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP1_MASK) >> AIPS_PACRC_WP1_SHIFT)
+#define AIPS_BRD_PACRC_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRC_WP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP1_MASK, AIPS_PACRC_WP1(value)))
+#define AIPS_BWR_PACRC_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP1 field. */
+#define AIPS_RD_PACRC_SP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP1_MASK) >> AIPS_PACRC_SP1_SHIFT)
+#define AIPS_BRD_PACRC_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRC_SP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP1_MASK, AIPS_PACRC_SP1(value)))
+#define AIPS_BWR_PACRC_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP0 field. */
+#define AIPS_RD_PACRC_TP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP0_MASK) >> AIPS_PACRC_TP0_SHIFT)
+#define AIPS_BRD_PACRC_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRC_TP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP0_MASK, AIPS_PACRC_TP0(value)))
+#define AIPS_BWR_PACRC_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP0 field. */
+#define AIPS_RD_PACRC_WP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP0_MASK) >> AIPS_PACRC_WP0_SHIFT)
+#define AIPS_BRD_PACRC_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRC_WP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP0_MASK, AIPS_PACRC_WP0(value)))
+#define AIPS_BWR_PACRC_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP0 field. */
+#define AIPS_RD_PACRC_SP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP0_MASK) >> AIPS_PACRC_SP0_SHIFT)
+#define AIPS_BRD_PACRC_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRC_SP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP0_MASK, AIPS_PACRC_SP0(value)))
+#define AIPS_BWR_PACRC_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRD - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRD - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRD register
+ */
+/*@{*/
+#define AIPS_RD_PACRD(base)      (AIPS_PACRD_REG(base))
+#define AIPS_WR_PACRD(base, value) (AIPS_PACRD_REG(base) = (value))
+#define AIPS_RMW_PACRD(base, mask, value) (AIPS_WR_PACRD(base, (AIPS_RD_PACRD(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) |  (value)))
+#define AIPS_CLR_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) & ~(value)))
+#define AIPS_TOG_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRD bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRD, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP7 field. */
+#define AIPS_RD_PACRD_TP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP7_MASK) >> AIPS_PACRD_TP7_SHIFT)
+#define AIPS_BRD_PACRD_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRD_TP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP7_MASK, AIPS_PACRD_TP7(value)))
+#define AIPS_BWR_PACRD_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP7 field. */
+#define AIPS_RD_PACRD_WP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP7_MASK) >> AIPS_PACRD_WP7_SHIFT)
+#define AIPS_BRD_PACRD_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRD_WP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP7_MASK, AIPS_PACRD_WP7(value)))
+#define AIPS_BWR_PACRD_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP7 field. */
+#define AIPS_RD_PACRD_SP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP7_MASK) >> AIPS_PACRD_SP7_SHIFT)
+#define AIPS_BRD_PACRD_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRD_SP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP7_MASK, AIPS_PACRD_SP7(value)))
+#define AIPS_BWR_PACRD_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP6 field. */
+#define AIPS_RD_PACRD_TP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP6_MASK) >> AIPS_PACRD_TP6_SHIFT)
+#define AIPS_BRD_PACRD_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRD_TP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP6_MASK, AIPS_PACRD_TP6(value)))
+#define AIPS_BWR_PACRD_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP6 field. */
+#define AIPS_RD_PACRD_WP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP6_MASK) >> AIPS_PACRD_WP6_SHIFT)
+#define AIPS_BRD_PACRD_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRD_WP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP6_MASK, AIPS_PACRD_WP6(value)))
+#define AIPS_BWR_PACRD_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP6 field. */
+#define AIPS_RD_PACRD_SP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP6_MASK) >> AIPS_PACRD_SP6_SHIFT)
+#define AIPS_BRD_PACRD_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRD_SP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP6_MASK, AIPS_PACRD_SP6(value)))
+#define AIPS_BWR_PACRD_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP5 field. */
+#define AIPS_RD_PACRD_TP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP5_MASK) >> AIPS_PACRD_TP5_SHIFT)
+#define AIPS_BRD_PACRD_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRD_TP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP5_MASK, AIPS_PACRD_TP5(value)))
+#define AIPS_BWR_PACRD_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP5 field. */
+#define AIPS_RD_PACRD_WP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP5_MASK) >> AIPS_PACRD_WP5_SHIFT)
+#define AIPS_BRD_PACRD_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRD_WP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP5_MASK, AIPS_PACRD_WP5(value)))
+#define AIPS_BWR_PACRD_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP5 field. */
+#define AIPS_RD_PACRD_SP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP5_MASK) >> AIPS_PACRD_SP5_SHIFT)
+#define AIPS_BRD_PACRD_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRD_SP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP5_MASK, AIPS_PACRD_SP5(value)))
+#define AIPS_BWR_PACRD_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP4 field. */
+#define AIPS_RD_PACRD_TP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP4_MASK) >> AIPS_PACRD_TP4_SHIFT)
+#define AIPS_BRD_PACRD_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRD_TP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP4_MASK, AIPS_PACRD_TP4(value)))
+#define AIPS_BWR_PACRD_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP4 field. */
+#define AIPS_RD_PACRD_WP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP4_MASK) >> AIPS_PACRD_WP4_SHIFT)
+#define AIPS_BRD_PACRD_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRD_WP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP4_MASK, AIPS_PACRD_WP4(value)))
+#define AIPS_BWR_PACRD_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP4 field. */
+#define AIPS_RD_PACRD_SP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP4_MASK) >> AIPS_PACRD_SP4_SHIFT)
+#define AIPS_BRD_PACRD_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRD_SP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP4_MASK, AIPS_PACRD_SP4(value)))
+#define AIPS_BWR_PACRD_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP3 field. */
+#define AIPS_RD_PACRD_TP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP3_MASK) >> AIPS_PACRD_TP3_SHIFT)
+#define AIPS_BRD_PACRD_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRD_TP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP3_MASK, AIPS_PACRD_TP3(value)))
+#define AIPS_BWR_PACRD_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP3 field. */
+#define AIPS_RD_PACRD_WP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP3_MASK) >> AIPS_PACRD_WP3_SHIFT)
+#define AIPS_BRD_PACRD_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRD_WP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP3_MASK, AIPS_PACRD_WP3(value)))
+#define AIPS_BWR_PACRD_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP3 field. */
+#define AIPS_RD_PACRD_SP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP3_MASK) >> AIPS_PACRD_SP3_SHIFT)
+#define AIPS_BRD_PACRD_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRD_SP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP3_MASK, AIPS_PACRD_SP3(value)))
+#define AIPS_BWR_PACRD_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP2 field. */
+#define AIPS_RD_PACRD_TP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP2_MASK) >> AIPS_PACRD_TP2_SHIFT)
+#define AIPS_BRD_PACRD_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRD_TP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP2_MASK, AIPS_PACRD_TP2(value)))
+#define AIPS_BWR_PACRD_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP2 field. */
+#define AIPS_RD_PACRD_WP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP2_MASK) >> AIPS_PACRD_WP2_SHIFT)
+#define AIPS_BRD_PACRD_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRD_WP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP2_MASK, AIPS_PACRD_WP2(value)))
+#define AIPS_BWR_PACRD_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP2 field. */
+#define AIPS_RD_PACRD_SP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP2_MASK) >> AIPS_PACRD_SP2_SHIFT)
+#define AIPS_BRD_PACRD_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRD_SP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP2_MASK, AIPS_PACRD_SP2(value)))
+#define AIPS_BWR_PACRD_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP1 field. */
+#define AIPS_RD_PACRD_TP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP1_MASK) >> AIPS_PACRD_TP1_SHIFT)
+#define AIPS_BRD_PACRD_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRD_TP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP1_MASK, AIPS_PACRD_TP1(value)))
+#define AIPS_BWR_PACRD_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP1 field. */
+#define AIPS_RD_PACRD_WP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP1_MASK) >> AIPS_PACRD_WP1_SHIFT)
+#define AIPS_BRD_PACRD_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRD_WP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP1_MASK, AIPS_PACRD_WP1(value)))
+#define AIPS_BWR_PACRD_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP1 field. */
+#define AIPS_RD_PACRD_SP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP1_MASK) >> AIPS_PACRD_SP1_SHIFT)
+#define AIPS_BRD_PACRD_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRD_SP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP1_MASK, AIPS_PACRD_SP1(value)))
+#define AIPS_BWR_PACRD_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP0 field. */
+#define AIPS_RD_PACRD_TP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP0_MASK) >> AIPS_PACRD_TP0_SHIFT)
+#define AIPS_BRD_PACRD_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRD_TP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP0_MASK, AIPS_PACRD_TP0(value)))
+#define AIPS_BWR_PACRD_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP0 field. */
+#define AIPS_RD_PACRD_WP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP0_MASK) >> AIPS_PACRD_WP0_SHIFT)
+#define AIPS_BRD_PACRD_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRD_WP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP0_MASK, AIPS_PACRD_WP0(value)))
+#define AIPS_BWR_PACRD_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP0 field. */
+#define AIPS_RD_PACRD_SP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP0_MASK) >> AIPS_PACRD_SP0_SHIFT)
+#define AIPS_BRD_PACRD_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRD_SP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP0_MASK, AIPS_PACRD_SP0(value)))
+#define AIPS_BWR_PACRD_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRE - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRE - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRE register
+ */
+/*@{*/
+#define AIPS_RD_PACRE(base)      (AIPS_PACRE_REG(base))
+#define AIPS_WR_PACRE(base, value) (AIPS_PACRE_REG(base) = (value))
+#define AIPS_RMW_PACRE(base, mask, value) (AIPS_WR_PACRE(base, (AIPS_RD_PACRE(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) |  (value)))
+#define AIPS_CLR_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) & ~(value)))
+#define AIPS_TOG_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRE bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRE, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP7 field. */
+#define AIPS_RD_PACRE_TP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP7_MASK) >> AIPS_PACRE_TP7_SHIFT)
+#define AIPS_BRD_PACRE_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRE_TP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP7_MASK, AIPS_PACRE_TP7(value)))
+#define AIPS_BWR_PACRE_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP7 field. */
+#define AIPS_RD_PACRE_WP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP7_MASK) >> AIPS_PACRE_WP7_SHIFT)
+#define AIPS_BRD_PACRE_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRE_WP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP7_MASK, AIPS_PACRE_WP7(value)))
+#define AIPS_BWR_PACRE_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP7 field. */
+#define AIPS_RD_PACRE_SP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP7_MASK) >> AIPS_PACRE_SP7_SHIFT)
+#define AIPS_BRD_PACRE_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRE_SP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP7_MASK, AIPS_PACRE_SP7(value)))
+#define AIPS_BWR_PACRE_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP6 field. */
+#define AIPS_RD_PACRE_TP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP6_MASK) >> AIPS_PACRE_TP6_SHIFT)
+#define AIPS_BRD_PACRE_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRE_TP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP6_MASK, AIPS_PACRE_TP6(value)))
+#define AIPS_BWR_PACRE_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP6 field. */
+#define AIPS_RD_PACRE_WP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP6_MASK) >> AIPS_PACRE_WP6_SHIFT)
+#define AIPS_BRD_PACRE_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRE_WP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP6_MASK, AIPS_PACRE_WP6(value)))
+#define AIPS_BWR_PACRE_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP6 field. */
+#define AIPS_RD_PACRE_SP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP6_MASK) >> AIPS_PACRE_SP6_SHIFT)
+#define AIPS_BRD_PACRE_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRE_SP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP6_MASK, AIPS_PACRE_SP6(value)))
+#define AIPS_BWR_PACRE_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP5 field. */
+#define AIPS_RD_PACRE_TP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP5_MASK) >> AIPS_PACRE_TP5_SHIFT)
+#define AIPS_BRD_PACRE_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRE_TP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP5_MASK, AIPS_PACRE_TP5(value)))
+#define AIPS_BWR_PACRE_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP5 field. */
+#define AIPS_RD_PACRE_WP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP5_MASK) >> AIPS_PACRE_WP5_SHIFT)
+#define AIPS_BRD_PACRE_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRE_WP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP5_MASK, AIPS_PACRE_WP5(value)))
+#define AIPS_BWR_PACRE_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP5 field. */
+#define AIPS_RD_PACRE_SP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP5_MASK) >> AIPS_PACRE_SP5_SHIFT)
+#define AIPS_BRD_PACRE_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRE_SP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP5_MASK, AIPS_PACRE_SP5(value)))
+#define AIPS_BWR_PACRE_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP4 field. */
+#define AIPS_RD_PACRE_TP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP4_MASK) >> AIPS_PACRE_TP4_SHIFT)
+#define AIPS_BRD_PACRE_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRE_TP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP4_MASK, AIPS_PACRE_TP4(value)))
+#define AIPS_BWR_PACRE_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP4 field. */
+#define AIPS_RD_PACRE_WP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP4_MASK) >> AIPS_PACRE_WP4_SHIFT)
+#define AIPS_BRD_PACRE_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRE_WP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP4_MASK, AIPS_PACRE_WP4(value)))
+#define AIPS_BWR_PACRE_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP4 field. */
+#define AIPS_RD_PACRE_SP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP4_MASK) >> AIPS_PACRE_SP4_SHIFT)
+#define AIPS_BRD_PACRE_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRE_SP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP4_MASK, AIPS_PACRE_SP4(value)))
+#define AIPS_BWR_PACRE_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP3 field. */
+#define AIPS_RD_PACRE_TP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP3_MASK) >> AIPS_PACRE_TP3_SHIFT)
+#define AIPS_BRD_PACRE_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRE_TP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP3_MASK, AIPS_PACRE_TP3(value)))
+#define AIPS_BWR_PACRE_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP3 field. */
+#define AIPS_RD_PACRE_WP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP3_MASK) >> AIPS_PACRE_WP3_SHIFT)
+#define AIPS_BRD_PACRE_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRE_WP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP3_MASK, AIPS_PACRE_WP3(value)))
+#define AIPS_BWR_PACRE_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP3 field. */
+#define AIPS_RD_PACRE_SP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP3_MASK) >> AIPS_PACRE_SP3_SHIFT)
+#define AIPS_BRD_PACRE_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRE_SP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP3_MASK, AIPS_PACRE_SP3(value)))
+#define AIPS_BWR_PACRE_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP2 field. */
+#define AIPS_RD_PACRE_TP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP2_MASK) >> AIPS_PACRE_TP2_SHIFT)
+#define AIPS_BRD_PACRE_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRE_TP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP2_MASK, AIPS_PACRE_TP2(value)))
+#define AIPS_BWR_PACRE_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP2 field. */
+#define AIPS_RD_PACRE_WP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP2_MASK) >> AIPS_PACRE_WP2_SHIFT)
+#define AIPS_BRD_PACRE_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRE_WP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP2_MASK, AIPS_PACRE_WP2(value)))
+#define AIPS_BWR_PACRE_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP2 field. */
+#define AIPS_RD_PACRE_SP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP2_MASK) >> AIPS_PACRE_SP2_SHIFT)
+#define AIPS_BRD_PACRE_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRE_SP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP2_MASK, AIPS_PACRE_SP2(value)))
+#define AIPS_BWR_PACRE_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP1 field. */
+#define AIPS_RD_PACRE_TP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP1_MASK) >> AIPS_PACRE_TP1_SHIFT)
+#define AIPS_BRD_PACRE_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRE_TP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP1_MASK, AIPS_PACRE_TP1(value)))
+#define AIPS_BWR_PACRE_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP1 field. */
+#define AIPS_RD_PACRE_WP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP1_MASK) >> AIPS_PACRE_WP1_SHIFT)
+#define AIPS_BRD_PACRE_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRE_WP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP1_MASK, AIPS_PACRE_WP1(value)))
+#define AIPS_BWR_PACRE_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP1 field. */
+#define AIPS_RD_PACRE_SP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP1_MASK) >> AIPS_PACRE_SP1_SHIFT)
+#define AIPS_BRD_PACRE_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRE_SP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP1_MASK, AIPS_PACRE_SP1(value)))
+#define AIPS_BWR_PACRE_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP0 field. */
+#define AIPS_RD_PACRE_TP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP0_MASK) >> AIPS_PACRE_TP0_SHIFT)
+#define AIPS_BRD_PACRE_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRE_TP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP0_MASK, AIPS_PACRE_TP0(value)))
+#define AIPS_BWR_PACRE_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP0 field. */
+#define AIPS_RD_PACRE_WP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP0_MASK) >> AIPS_PACRE_WP0_SHIFT)
+#define AIPS_BRD_PACRE_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRE_WP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP0_MASK, AIPS_PACRE_WP0(value)))
+#define AIPS_BWR_PACRE_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP0 field. */
+#define AIPS_RD_PACRE_SP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP0_MASK) >> AIPS_PACRE_SP0_SHIFT)
+#define AIPS_BRD_PACRE_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRE_SP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP0_MASK, AIPS_PACRE_SP0(value)))
+#define AIPS_BWR_PACRE_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRF - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRF - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRF register
+ */
+/*@{*/
+#define AIPS_RD_PACRF(base)      (AIPS_PACRF_REG(base))
+#define AIPS_WR_PACRF(base, value) (AIPS_PACRF_REG(base) = (value))
+#define AIPS_RMW_PACRF(base, mask, value) (AIPS_WR_PACRF(base, (AIPS_RD_PACRF(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) |  (value)))
+#define AIPS_CLR_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) & ~(value)))
+#define AIPS_TOG_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRF bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRF, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP7 field. */
+#define AIPS_RD_PACRF_TP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP7_MASK) >> AIPS_PACRF_TP7_SHIFT)
+#define AIPS_BRD_PACRF_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRF_TP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP7_MASK, AIPS_PACRF_TP7(value)))
+#define AIPS_BWR_PACRF_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP7 field. */
+#define AIPS_RD_PACRF_WP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP7_MASK) >> AIPS_PACRF_WP7_SHIFT)
+#define AIPS_BRD_PACRF_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRF_WP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP7_MASK, AIPS_PACRF_WP7(value)))
+#define AIPS_BWR_PACRF_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP7 field. */
+#define AIPS_RD_PACRF_SP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP7_MASK) >> AIPS_PACRF_SP7_SHIFT)
+#define AIPS_BRD_PACRF_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRF_SP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP7_MASK, AIPS_PACRF_SP7(value)))
+#define AIPS_BWR_PACRF_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP6 field. */
+#define AIPS_RD_PACRF_TP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP6_MASK) >> AIPS_PACRF_TP6_SHIFT)
+#define AIPS_BRD_PACRF_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRF_TP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP6_MASK, AIPS_PACRF_TP6(value)))
+#define AIPS_BWR_PACRF_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP6 field. */
+#define AIPS_RD_PACRF_WP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP6_MASK) >> AIPS_PACRF_WP6_SHIFT)
+#define AIPS_BRD_PACRF_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRF_WP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP6_MASK, AIPS_PACRF_WP6(value)))
+#define AIPS_BWR_PACRF_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP6 field. */
+#define AIPS_RD_PACRF_SP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP6_MASK) >> AIPS_PACRF_SP6_SHIFT)
+#define AIPS_BRD_PACRF_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRF_SP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP6_MASK, AIPS_PACRF_SP6(value)))
+#define AIPS_BWR_PACRF_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP5 field. */
+#define AIPS_RD_PACRF_TP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP5_MASK) >> AIPS_PACRF_TP5_SHIFT)
+#define AIPS_BRD_PACRF_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRF_TP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP5_MASK, AIPS_PACRF_TP5(value)))
+#define AIPS_BWR_PACRF_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP5 field. */
+#define AIPS_RD_PACRF_WP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP5_MASK) >> AIPS_PACRF_WP5_SHIFT)
+#define AIPS_BRD_PACRF_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRF_WP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP5_MASK, AIPS_PACRF_WP5(value)))
+#define AIPS_BWR_PACRF_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP5 field. */
+#define AIPS_RD_PACRF_SP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP5_MASK) >> AIPS_PACRF_SP5_SHIFT)
+#define AIPS_BRD_PACRF_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRF_SP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP5_MASK, AIPS_PACRF_SP5(value)))
+#define AIPS_BWR_PACRF_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP4 field. */
+#define AIPS_RD_PACRF_TP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP4_MASK) >> AIPS_PACRF_TP4_SHIFT)
+#define AIPS_BRD_PACRF_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRF_TP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP4_MASK, AIPS_PACRF_TP4(value)))
+#define AIPS_BWR_PACRF_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP4 field. */
+#define AIPS_RD_PACRF_WP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP4_MASK) >> AIPS_PACRF_WP4_SHIFT)
+#define AIPS_BRD_PACRF_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRF_WP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP4_MASK, AIPS_PACRF_WP4(value)))
+#define AIPS_BWR_PACRF_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP4 field. */
+#define AIPS_RD_PACRF_SP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP4_MASK) >> AIPS_PACRF_SP4_SHIFT)
+#define AIPS_BRD_PACRF_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRF_SP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP4_MASK, AIPS_PACRF_SP4(value)))
+#define AIPS_BWR_PACRF_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP3 field. */
+#define AIPS_RD_PACRF_TP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP3_MASK) >> AIPS_PACRF_TP3_SHIFT)
+#define AIPS_BRD_PACRF_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRF_TP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP3_MASK, AIPS_PACRF_TP3(value)))
+#define AIPS_BWR_PACRF_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP3 field. */
+#define AIPS_RD_PACRF_WP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP3_MASK) >> AIPS_PACRF_WP3_SHIFT)
+#define AIPS_BRD_PACRF_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRF_WP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP3_MASK, AIPS_PACRF_WP3(value)))
+#define AIPS_BWR_PACRF_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP3 field. */
+#define AIPS_RD_PACRF_SP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP3_MASK) >> AIPS_PACRF_SP3_SHIFT)
+#define AIPS_BRD_PACRF_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRF_SP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP3_MASK, AIPS_PACRF_SP3(value)))
+#define AIPS_BWR_PACRF_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP2 field. */
+#define AIPS_RD_PACRF_TP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP2_MASK) >> AIPS_PACRF_TP2_SHIFT)
+#define AIPS_BRD_PACRF_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRF_TP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP2_MASK, AIPS_PACRF_TP2(value)))
+#define AIPS_BWR_PACRF_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP2 field. */
+#define AIPS_RD_PACRF_WP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP2_MASK) >> AIPS_PACRF_WP2_SHIFT)
+#define AIPS_BRD_PACRF_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRF_WP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP2_MASK, AIPS_PACRF_WP2(value)))
+#define AIPS_BWR_PACRF_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP2 field. */
+#define AIPS_RD_PACRF_SP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP2_MASK) >> AIPS_PACRF_SP2_SHIFT)
+#define AIPS_BRD_PACRF_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRF_SP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP2_MASK, AIPS_PACRF_SP2(value)))
+#define AIPS_BWR_PACRF_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP1 field. */
+#define AIPS_RD_PACRF_TP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP1_MASK) >> AIPS_PACRF_TP1_SHIFT)
+#define AIPS_BRD_PACRF_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRF_TP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP1_MASK, AIPS_PACRF_TP1(value)))
+#define AIPS_BWR_PACRF_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP1 field. */
+#define AIPS_RD_PACRF_WP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP1_MASK) >> AIPS_PACRF_WP1_SHIFT)
+#define AIPS_BRD_PACRF_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRF_WP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP1_MASK, AIPS_PACRF_WP1(value)))
+#define AIPS_BWR_PACRF_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP1 field. */
+#define AIPS_RD_PACRF_SP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP1_MASK) >> AIPS_PACRF_SP1_SHIFT)
+#define AIPS_BRD_PACRF_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRF_SP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP1_MASK, AIPS_PACRF_SP1(value)))
+#define AIPS_BWR_PACRF_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP0 field. */
+#define AIPS_RD_PACRF_TP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP0_MASK) >> AIPS_PACRF_TP0_SHIFT)
+#define AIPS_BRD_PACRF_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRF_TP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP0_MASK, AIPS_PACRF_TP0(value)))
+#define AIPS_BWR_PACRF_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP0 field. */
+#define AIPS_RD_PACRF_WP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP0_MASK) >> AIPS_PACRF_WP0_SHIFT)
+#define AIPS_BRD_PACRF_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRF_WP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP0_MASK, AIPS_PACRF_WP0(value)))
+#define AIPS_BWR_PACRF_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP0 field. */
+#define AIPS_RD_PACRF_SP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP0_MASK) >> AIPS_PACRF_SP0_SHIFT)
+#define AIPS_BRD_PACRF_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRF_SP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP0_MASK, AIPS_PACRF_SP0(value)))
+#define AIPS_BWR_PACRF_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRG - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRG - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRG register
+ */
+/*@{*/
+#define AIPS_RD_PACRG(base)      (AIPS_PACRG_REG(base))
+#define AIPS_WR_PACRG(base, value) (AIPS_PACRG_REG(base) = (value))
+#define AIPS_RMW_PACRG(base, mask, value) (AIPS_WR_PACRG(base, (AIPS_RD_PACRG(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) |  (value)))
+#define AIPS_CLR_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) & ~(value)))
+#define AIPS_TOG_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRG bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRG, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP7 field. */
+#define AIPS_RD_PACRG_TP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP7_MASK) >> AIPS_PACRG_TP7_SHIFT)
+#define AIPS_BRD_PACRG_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRG_TP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP7_MASK, AIPS_PACRG_TP7(value)))
+#define AIPS_BWR_PACRG_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP7 field. */
+#define AIPS_RD_PACRG_WP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP7_MASK) >> AIPS_PACRG_WP7_SHIFT)
+#define AIPS_BRD_PACRG_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRG_WP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP7_MASK, AIPS_PACRG_WP7(value)))
+#define AIPS_BWR_PACRG_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP7 field. */
+#define AIPS_RD_PACRG_SP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP7_MASK) >> AIPS_PACRG_SP7_SHIFT)
+#define AIPS_BRD_PACRG_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRG_SP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP7_MASK, AIPS_PACRG_SP7(value)))
+#define AIPS_BWR_PACRG_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP6 field. */
+#define AIPS_RD_PACRG_TP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP6_MASK) >> AIPS_PACRG_TP6_SHIFT)
+#define AIPS_BRD_PACRG_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRG_TP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP6_MASK, AIPS_PACRG_TP6(value)))
+#define AIPS_BWR_PACRG_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP6 field. */
+#define AIPS_RD_PACRG_WP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP6_MASK) >> AIPS_PACRG_WP6_SHIFT)
+#define AIPS_BRD_PACRG_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRG_WP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP6_MASK, AIPS_PACRG_WP6(value)))
+#define AIPS_BWR_PACRG_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP6 field. */
+#define AIPS_RD_PACRG_SP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP6_MASK) >> AIPS_PACRG_SP6_SHIFT)
+#define AIPS_BRD_PACRG_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRG_SP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP6_MASK, AIPS_PACRG_SP6(value)))
+#define AIPS_BWR_PACRG_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP5 field. */
+#define AIPS_RD_PACRG_TP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP5_MASK) >> AIPS_PACRG_TP5_SHIFT)
+#define AIPS_BRD_PACRG_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRG_TP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP5_MASK, AIPS_PACRG_TP5(value)))
+#define AIPS_BWR_PACRG_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP5 field. */
+#define AIPS_RD_PACRG_WP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP5_MASK) >> AIPS_PACRG_WP5_SHIFT)
+#define AIPS_BRD_PACRG_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRG_WP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP5_MASK, AIPS_PACRG_WP5(value)))
+#define AIPS_BWR_PACRG_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP5 field. */
+#define AIPS_RD_PACRG_SP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP5_MASK) >> AIPS_PACRG_SP5_SHIFT)
+#define AIPS_BRD_PACRG_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRG_SP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP5_MASK, AIPS_PACRG_SP5(value)))
+#define AIPS_BWR_PACRG_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP4 field. */
+#define AIPS_RD_PACRG_TP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP4_MASK) >> AIPS_PACRG_TP4_SHIFT)
+#define AIPS_BRD_PACRG_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRG_TP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP4_MASK, AIPS_PACRG_TP4(value)))
+#define AIPS_BWR_PACRG_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP4 field. */
+#define AIPS_RD_PACRG_WP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP4_MASK) >> AIPS_PACRG_WP4_SHIFT)
+#define AIPS_BRD_PACRG_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRG_WP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP4_MASK, AIPS_PACRG_WP4(value)))
+#define AIPS_BWR_PACRG_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP4 field. */
+#define AIPS_RD_PACRG_SP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP4_MASK) >> AIPS_PACRG_SP4_SHIFT)
+#define AIPS_BRD_PACRG_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRG_SP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP4_MASK, AIPS_PACRG_SP4(value)))
+#define AIPS_BWR_PACRG_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP3 field. */
+#define AIPS_RD_PACRG_TP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP3_MASK) >> AIPS_PACRG_TP3_SHIFT)
+#define AIPS_BRD_PACRG_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRG_TP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP3_MASK, AIPS_PACRG_TP3(value)))
+#define AIPS_BWR_PACRG_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP3 field. */
+#define AIPS_RD_PACRG_WP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP3_MASK) >> AIPS_PACRG_WP3_SHIFT)
+#define AIPS_BRD_PACRG_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRG_WP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP3_MASK, AIPS_PACRG_WP3(value)))
+#define AIPS_BWR_PACRG_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP3 field. */
+#define AIPS_RD_PACRG_SP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP3_MASK) >> AIPS_PACRG_SP3_SHIFT)
+#define AIPS_BRD_PACRG_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRG_SP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP3_MASK, AIPS_PACRG_SP3(value)))
+#define AIPS_BWR_PACRG_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP2 field. */
+#define AIPS_RD_PACRG_TP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP2_MASK) >> AIPS_PACRG_TP2_SHIFT)
+#define AIPS_BRD_PACRG_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRG_TP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP2_MASK, AIPS_PACRG_TP2(value)))
+#define AIPS_BWR_PACRG_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP2 field. */
+#define AIPS_RD_PACRG_WP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP2_MASK) >> AIPS_PACRG_WP2_SHIFT)
+#define AIPS_BRD_PACRG_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRG_WP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP2_MASK, AIPS_PACRG_WP2(value)))
+#define AIPS_BWR_PACRG_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP2 field. */
+#define AIPS_RD_PACRG_SP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP2_MASK) >> AIPS_PACRG_SP2_SHIFT)
+#define AIPS_BRD_PACRG_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRG_SP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP2_MASK, AIPS_PACRG_SP2(value)))
+#define AIPS_BWR_PACRG_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP1 field. */
+#define AIPS_RD_PACRG_TP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP1_MASK) >> AIPS_PACRG_TP1_SHIFT)
+#define AIPS_BRD_PACRG_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRG_TP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP1_MASK, AIPS_PACRG_TP1(value)))
+#define AIPS_BWR_PACRG_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP1 field. */
+#define AIPS_RD_PACRG_WP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP1_MASK) >> AIPS_PACRG_WP1_SHIFT)
+#define AIPS_BRD_PACRG_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRG_WP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP1_MASK, AIPS_PACRG_WP1(value)))
+#define AIPS_BWR_PACRG_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP1 field. */
+#define AIPS_RD_PACRG_SP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP1_MASK) >> AIPS_PACRG_SP1_SHIFT)
+#define AIPS_BRD_PACRG_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRG_SP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP1_MASK, AIPS_PACRG_SP1(value)))
+#define AIPS_BWR_PACRG_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP0 field. */
+#define AIPS_RD_PACRG_TP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP0_MASK) >> AIPS_PACRG_TP0_SHIFT)
+#define AIPS_BRD_PACRG_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRG_TP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP0_MASK, AIPS_PACRG_TP0(value)))
+#define AIPS_BWR_PACRG_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP0 field. */
+#define AIPS_RD_PACRG_WP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP0_MASK) >> AIPS_PACRG_WP0_SHIFT)
+#define AIPS_BRD_PACRG_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRG_WP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP0_MASK, AIPS_PACRG_WP0(value)))
+#define AIPS_BWR_PACRG_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP0 field. */
+#define AIPS_RD_PACRG_SP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP0_MASK) >> AIPS_PACRG_SP0_SHIFT)
+#define AIPS_BRD_PACRG_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRG_SP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP0_MASK, AIPS_PACRG_SP0(value)))
+#define AIPS_BWR_PACRG_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRH - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRH - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRH register
+ */
+/*@{*/
+#define AIPS_RD_PACRH(base)      (AIPS_PACRH_REG(base))
+#define AIPS_WR_PACRH(base, value) (AIPS_PACRH_REG(base) = (value))
+#define AIPS_RMW_PACRH(base, mask, value) (AIPS_WR_PACRH(base, (AIPS_RD_PACRH(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) |  (value)))
+#define AIPS_CLR_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) & ~(value)))
+#define AIPS_TOG_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRH bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRH, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP7 field. */
+#define AIPS_RD_PACRH_TP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP7_MASK) >> AIPS_PACRH_TP7_SHIFT)
+#define AIPS_BRD_PACRH_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRH_TP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP7_MASK, AIPS_PACRH_TP7(value)))
+#define AIPS_BWR_PACRH_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP7 field. */
+#define AIPS_RD_PACRH_WP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP7_MASK) >> AIPS_PACRH_WP7_SHIFT)
+#define AIPS_BRD_PACRH_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRH_WP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP7_MASK, AIPS_PACRH_WP7(value)))
+#define AIPS_BWR_PACRH_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP7 field. */
+#define AIPS_RD_PACRH_SP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP7_MASK) >> AIPS_PACRH_SP7_SHIFT)
+#define AIPS_BRD_PACRH_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRH_SP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP7_MASK, AIPS_PACRH_SP7(value)))
+#define AIPS_BWR_PACRH_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP6 field. */
+#define AIPS_RD_PACRH_TP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP6_MASK) >> AIPS_PACRH_TP6_SHIFT)
+#define AIPS_BRD_PACRH_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRH_TP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP6_MASK, AIPS_PACRH_TP6(value)))
+#define AIPS_BWR_PACRH_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP6 field. */
+#define AIPS_RD_PACRH_WP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP6_MASK) >> AIPS_PACRH_WP6_SHIFT)
+#define AIPS_BRD_PACRH_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRH_WP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP6_MASK, AIPS_PACRH_WP6(value)))
+#define AIPS_BWR_PACRH_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP6 field. */
+#define AIPS_RD_PACRH_SP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP6_MASK) >> AIPS_PACRH_SP6_SHIFT)
+#define AIPS_BRD_PACRH_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRH_SP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP6_MASK, AIPS_PACRH_SP6(value)))
+#define AIPS_BWR_PACRH_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP5 field. */
+#define AIPS_RD_PACRH_TP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP5_MASK) >> AIPS_PACRH_TP5_SHIFT)
+#define AIPS_BRD_PACRH_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRH_TP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP5_MASK, AIPS_PACRH_TP5(value)))
+#define AIPS_BWR_PACRH_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP5 field. */
+#define AIPS_RD_PACRH_WP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP5_MASK) >> AIPS_PACRH_WP5_SHIFT)
+#define AIPS_BRD_PACRH_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRH_WP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP5_MASK, AIPS_PACRH_WP5(value)))
+#define AIPS_BWR_PACRH_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP5 field. */
+#define AIPS_RD_PACRH_SP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP5_MASK) >> AIPS_PACRH_SP5_SHIFT)
+#define AIPS_BRD_PACRH_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRH_SP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP5_MASK, AIPS_PACRH_SP5(value)))
+#define AIPS_BWR_PACRH_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP4 field. */
+#define AIPS_RD_PACRH_TP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP4_MASK) >> AIPS_PACRH_TP4_SHIFT)
+#define AIPS_BRD_PACRH_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRH_TP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP4_MASK, AIPS_PACRH_TP4(value)))
+#define AIPS_BWR_PACRH_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP4 field. */
+#define AIPS_RD_PACRH_WP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP4_MASK) >> AIPS_PACRH_WP4_SHIFT)
+#define AIPS_BRD_PACRH_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRH_WP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP4_MASK, AIPS_PACRH_WP4(value)))
+#define AIPS_BWR_PACRH_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP4 field. */
+#define AIPS_RD_PACRH_SP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP4_MASK) >> AIPS_PACRH_SP4_SHIFT)
+#define AIPS_BRD_PACRH_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRH_SP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP4_MASK, AIPS_PACRH_SP4(value)))
+#define AIPS_BWR_PACRH_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP3 field. */
+#define AIPS_RD_PACRH_TP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP3_MASK) >> AIPS_PACRH_TP3_SHIFT)
+#define AIPS_BRD_PACRH_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRH_TP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP3_MASK, AIPS_PACRH_TP3(value)))
+#define AIPS_BWR_PACRH_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP3 field. */
+#define AIPS_RD_PACRH_WP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP3_MASK) >> AIPS_PACRH_WP3_SHIFT)
+#define AIPS_BRD_PACRH_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRH_WP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP3_MASK, AIPS_PACRH_WP3(value)))
+#define AIPS_BWR_PACRH_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP3 field. */
+#define AIPS_RD_PACRH_SP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP3_MASK) >> AIPS_PACRH_SP3_SHIFT)
+#define AIPS_BRD_PACRH_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRH_SP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP3_MASK, AIPS_PACRH_SP3(value)))
+#define AIPS_BWR_PACRH_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP2 field. */
+#define AIPS_RD_PACRH_TP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP2_MASK) >> AIPS_PACRH_TP2_SHIFT)
+#define AIPS_BRD_PACRH_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRH_TP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP2_MASK, AIPS_PACRH_TP2(value)))
+#define AIPS_BWR_PACRH_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP2 field. */
+#define AIPS_RD_PACRH_WP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP2_MASK) >> AIPS_PACRH_WP2_SHIFT)
+#define AIPS_BRD_PACRH_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRH_WP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP2_MASK, AIPS_PACRH_WP2(value)))
+#define AIPS_BWR_PACRH_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP2 field. */
+#define AIPS_RD_PACRH_SP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP2_MASK) >> AIPS_PACRH_SP2_SHIFT)
+#define AIPS_BRD_PACRH_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRH_SP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP2_MASK, AIPS_PACRH_SP2(value)))
+#define AIPS_BWR_PACRH_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP1 field. */
+#define AIPS_RD_PACRH_TP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP1_MASK) >> AIPS_PACRH_TP1_SHIFT)
+#define AIPS_BRD_PACRH_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRH_TP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP1_MASK, AIPS_PACRH_TP1(value)))
+#define AIPS_BWR_PACRH_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP1 field. */
+#define AIPS_RD_PACRH_WP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP1_MASK) >> AIPS_PACRH_WP1_SHIFT)
+#define AIPS_BRD_PACRH_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRH_WP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP1_MASK, AIPS_PACRH_WP1(value)))
+#define AIPS_BWR_PACRH_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP1 field. */
+#define AIPS_RD_PACRH_SP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP1_MASK) >> AIPS_PACRH_SP1_SHIFT)
+#define AIPS_BRD_PACRH_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRH_SP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP1_MASK, AIPS_PACRH_SP1(value)))
+#define AIPS_BWR_PACRH_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP0 field. */
+#define AIPS_RD_PACRH_TP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP0_MASK) >> AIPS_PACRH_TP0_SHIFT)
+#define AIPS_BRD_PACRH_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRH_TP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP0_MASK, AIPS_PACRH_TP0(value)))
+#define AIPS_BWR_PACRH_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP0 field. */
+#define AIPS_RD_PACRH_WP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP0_MASK) >> AIPS_PACRH_WP0_SHIFT)
+#define AIPS_BRD_PACRH_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRH_WP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP0_MASK, AIPS_PACRH_WP0(value)))
+#define AIPS_BWR_PACRH_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP0 field. */
+#define AIPS_RD_PACRH_SP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP0_MASK) >> AIPS_PACRH_SP0_SHIFT)
+#define AIPS_BRD_PACRH_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRH_SP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP0_MASK, AIPS_PACRH_SP0(value)))
+#define AIPS_BWR_PACRH_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRI - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRI - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRI register
+ */
+/*@{*/
+#define AIPS_RD_PACRI(base)      (AIPS_PACRI_REG(base))
+#define AIPS_WR_PACRI(base, value) (AIPS_PACRI_REG(base) = (value))
+#define AIPS_RMW_PACRI(base, mask, value) (AIPS_WR_PACRI(base, (AIPS_RD_PACRI(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) |  (value)))
+#define AIPS_CLR_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) & ~(value)))
+#define AIPS_TOG_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRI bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRI, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP7 field. */
+#define AIPS_RD_PACRI_TP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP7_MASK) >> AIPS_PACRI_TP7_SHIFT)
+#define AIPS_BRD_PACRI_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRI_TP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP7_MASK, AIPS_PACRI_TP7(value)))
+#define AIPS_BWR_PACRI_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP7 field. */
+#define AIPS_RD_PACRI_WP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP7_MASK) >> AIPS_PACRI_WP7_SHIFT)
+#define AIPS_BRD_PACRI_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRI_WP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP7_MASK, AIPS_PACRI_WP7(value)))
+#define AIPS_BWR_PACRI_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP7 field. */
+#define AIPS_RD_PACRI_SP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP7_MASK) >> AIPS_PACRI_SP7_SHIFT)
+#define AIPS_BRD_PACRI_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRI_SP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP7_MASK, AIPS_PACRI_SP7(value)))
+#define AIPS_BWR_PACRI_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP6 field. */
+#define AIPS_RD_PACRI_TP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP6_MASK) >> AIPS_PACRI_TP6_SHIFT)
+#define AIPS_BRD_PACRI_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRI_TP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP6_MASK, AIPS_PACRI_TP6(value)))
+#define AIPS_BWR_PACRI_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP6 field. */
+#define AIPS_RD_PACRI_WP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP6_MASK) >> AIPS_PACRI_WP6_SHIFT)
+#define AIPS_BRD_PACRI_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRI_WP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP6_MASK, AIPS_PACRI_WP6(value)))
+#define AIPS_BWR_PACRI_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP6 field. */
+#define AIPS_RD_PACRI_SP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP6_MASK) >> AIPS_PACRI_SP6_SHIFT)
+#define AIPS_BRD_PACRI_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRI_SP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP6_MASK, AIPS_PACRI_SP6(value)))
+#define AIPS_BWR_PACRI_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP5 field. */
+#define AIPS_RD_PACRI_TP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP5_MASK) >> AIPS_PACRI_TP5_SHIFT)
+#define AIPS_BRD_PACRI_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRI_TP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP5_MASK, AIPS_PACRI_TP5(value)))
+#define AIPS_BWR_PACRI_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP5 field. */
+#define AIPS_RD_PACRI_WP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP5_MASK) >> AIPS_PACRI_WP5_SHIFT)
+#define AIPS_BRD_PACRI_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRI_WP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP5_MASK, AIPS_PACRI_WP5(value)))
+#define AIPS_BWR_PACRI_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP5 field. */
+#define AIPS_RD_PACRI_SP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP5_MASK) >> AIPS_PACRI_SP5_SHIFT)
+#define AIPS_BRD_PACRI_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRI_SP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP5_MASK, AIPS_PACRI_SP5(value)))
+#define AIPS_BWR_PACRI_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP4 field. */
+#define AIPS_RD_PACRI_TP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP4_MASK) >> AIPS_PACRI_TP4_SHIFT)
+#define AIPS_BRD_PACRI_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRI_TP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP4_MASK, AIPS_PACRI_TP4(value)))
+#define AIPS_BWR_PACRI_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP4 field. */
+#define AIPS_RD_PACRI_WP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP4_MASK) >> AIPS_PACRI_WP4_SHIFT)
+#define AIPS_BRD_PACRI_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRI_WP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP4_MASK, AIPS_PACRI_WP4(value)))
+#define AIPS_BWR_PACRI_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP4 field. */
+#define AIPS_RD_PACRI_SP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP4_MASK) >> AIPS_PACRI_SP4_SHIFT)
+#define AIPS_BRD_PACRI_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRI_SP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP4_MASK, AIPS_PACRI_SP4(value)))
+#define AIPS_BWR_PACRI_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP3 field. */
+#define AIPS_RD_PACRI_TP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP3_MASK) >> AIPS_PACRI_TP3_SHIFT)
+#define AIPS_BRD_PACRI_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRI_TP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP3_MASK, AIPS_PACRI_TP3(value)))
+#define AIPS_BWR_PACRI_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP3 field. */
+#define AIPS_RD_PACRI_WP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP3_MASK) >> AIPS_PACRI_WP3_SHIFT)
+#define AIPS_BRD_PACRI_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRI_WP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP3_MASK, AIPS_PACRI_WP3(value)))
+#define AIPS_BWR_PACRI_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP3 field. */
+#define AIPS_RD_PACRI_SP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP3_MASK) >> AIPS_PACRI_SP3_SHIFT)
+#define AIPS_BRD_PACRI_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRI_SP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP3_MASK, AIPS_PACRI_SP3(value)))
+#define AIPS_BWR_PACRI_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP2 field. */
+#define AIPS_RD_PACRI_TP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP2_MASK) >> AIPS_PACRI_TP2_SHIFT)
+#define AIPS_BRD_PACRI_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRI_TP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP2_MASK, AIPS_PACRI_TP2(value)))
+#define AIPS_BWR_PACRI_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP2 field. */
+#define AIPS_RD_PACRI_WP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP2_MASK) >> AIPS_PACRI_WP2_SHIFT)
+#define AIPS_BRD_PACRI_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRI_WP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP2_MASK, AIPS_PACRI_WP2(value)))
+#define AIPS_BWR_PACRI_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP2 field. */
+#define AIPS_RD_PACRI_SP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP2_MASK) >> AIPS_PACRI_SP2_SHIFT)
+#define AIPS_BRD_PACRI_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRI_SP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP2_MASK, AIPS_PACRI_SP2(value)))
+#define AIPS_BWR_PACRI_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP1 field. */
+#define AIPS_RD_PACRI_TP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP1_MASK) >> AIPS_PACRI_TP1_SHIFT)
+#define AIPS_BRD_PACRI_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRI_TP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP1_MASK, AIPS_PACRI_TP1(value)))
+#define AIPS_BWR_PACRI_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP1 field. */
+#define AIPS_RD_PACRI_WP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP1_MASK) >> AIPS_PACRI_WP1_SHIFT)
+#define AIPS_BRD_PACRI_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRI_WP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP1_MASK, AIPS_PACRI_WP1(value)))
+#define AIPS_BWR_PACRI_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP1 field. */
+#define AIPS_RD_PACRI_SP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP1_MASK) >> AIPS_PACRI_SP1_SHIFT)
+#define AIPS_BRD_PACRI_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRI_SP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP1_MASK, AIPS_PACRI_SP1(value)))
+#define AIPS_BWR_PACRI_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP0 field. */
+#define AIPS_RD_PACRI_TP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP0_MASK) >> AIPS_PACRI_TP0_SHIFT)
+#define AIPS_BRD_PACRI_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRI_TP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP0_MASK, AIPS_PACRI_TP0(value)))
+#define AIPS_BWR_PACRI_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP0 field. */
+#define AIPS_RD_PACRI_WP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP0_MASK) >> AIPS_PACRI_WP0_SHIFT)
+#define AIPS_BRD_PACRI_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRI_WP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP0_MASK, AIPS_PACRI_WP0(value)))
+#define AIPS_BWR_PACRI_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP0 field. */
+#define AIPS_RD_PACRI_SP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP0_MASK) >> AIPS_PACRI_SP0_SHIFT)
+#define AIPS_BRD_PACRI_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRI_SP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP0_MASK, AIPS_PACRI_SP0(value)))
+#define AIPS_BWR_PACRI_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRJ - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRJ - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRJ register
+ */
+/*@{*/
+#define AIPS_RD_PACRJ(base)      (AIPS_PACRJ_REG(base))
+#define AIPS_WR_PACRJ(base, value) (AIPS_PACRJ_REG(base) = (value))
+#define AIPS_RMW_PACRJ(base, mask, value) (AIPS_WR_PACRJ(base, (AIPS_RD_PACRJ(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) |  (value)))
+#define AIPS_CLR_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) & ~(value)))
+#define AIPS_TOG_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRJ bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRJ, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP7 field. */
+#define AIPS_RD_PACRJ_TP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP7_MASK) >> AIPS_PACRJ_TP7_SHIFT)
+#define AIPS_BRD_PACRJ_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRJ_TP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP7_MASK, AIPS_PACRJ_TP7(value)))
+#define AIPS_BWR_PACRJ_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP7 field. */
+#define AIPS_RD_PACRJ_WP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP7_MASK) >> AIPS_PACRJ_WP7_SHIFT)
+#define AIPS_BRD_PACRJ_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRJ_WP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP7_MASK, AIPS_PACRJ_WP7(value)))
+#define AIPS_BWR_PACRJ_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP7 field. */
+#define AIPS_RD_PACRJ_SP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP7_MASK) >> AIPS_PACRJ_SP7_SHIFT)
+#define AIPS_BRD_PACRJ_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRJ_SP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP7_MASK, AIPS_PACRJ_SP7(value)))
+#define AIPS_BWR_PACRJ_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP6 field. */
+#define AIPS_RD_PACRJ_TP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP6_MASK) >> AIPS_PACRJ_TP6_SHIFT)
+#define AIPS_BRD_PACRJ_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRJ_TP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP6_MASK, AIPS_PACRJ_TP6(value)))
+#define AIPS_BWR_PACRJ_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP6 field. */
+#define AIPS_RD_PACRJ_WP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP6_MASK) >> AIPS_PACRJ_WP6_SHIFT)
+#define AIPS_BRD_PACRJ_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRJ_WP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP6_MASK, AIPS_PACRJ_WP6(value)))
+#define AIPS_BWR_PACRJ_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP6 field. */
+#define AIPS_RD_PACRJ_SP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP6_MASK) >> AIPS_PACRJ_SP6_SHIFT)
+#define AIPS_BRD_PACRJ_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRJ_SP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP6_MASK, AIPS_PACRJ_SP6(value)))
+#define AIPS_BWR_PACRJ_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP5 field. */
+#define AIPS_RD_PACRJ_TP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP5_MASK) >> AIPS_PACRJ_TP5_SHIFT)
+#define AIPS_BRD_PACRJ_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRJ_TP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP5_MASK, AIPS_PACRJ_TP5(value)))
+#define AIPS_BWR_PACRJ_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP5 field. */
+#define AIPS_RD_PACRJ_WP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP5_MASK) >> AIPS_PACRJ_WP5_SHIFT)
+#define AIPS_BRD_PACRJ_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRJ_WP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP5_MASK, AIPS_PACRJ_WP5(value)))
+#define AIPS_BWR_PACRJ_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP5 field. */
+#define AIPS_RD_PACRJ_SP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP5_MASK) >> AIPS_PACRJ_SP5_SHIFT)
+#define AIPS_BRD_PACRJ_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRJ_SP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP5_MASK, AIPS_PACRJ_SP5(value)))
+#define AIPS_BWR_PACRJ_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP4 field. */
+#define AIPS_RD_PACRJ_TP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP4_MASK) >> AIPS_PACRJ_TP4_SHIFT)
+#define AIPS_BRD_PACRJ_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRJ_TP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP4_MASK, AIPS_PACRJ_TP4(value)))
+#define AIPS_BWR_PACRJ_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP4 field. */
+#define AIPS_RD_PACRJ_WP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP4_MASK) >> AIPS_PACRJ_WP4_SHIFT)
+#define AIPS_BRD_PACRJ_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRJ_WP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP4_MASK, AIPS_PACRJ_WP4(value)))
+#define AIPS_BWR_PACRJ_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP4 field. */
+#define AIPS_RD_PACRJ_SP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP4_MASK) >> AIPS_PACRJ_SP4_SHIFT)
+#define AIPS_BRD_PACRJ_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRJ_SP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP4_MASK, AIPS_PACRJ_SP4(value)))
+#define AIPS_BWR_PACRJ_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP3 field. */
+#define AIPS_RD_PACRJ_TP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP3_MASK) >> AIPS_PACRJ_TP3_SHIFT)
+#define AIPS_BRD_PACRJ_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRJ_TP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP3_MASK, AIPS_PACRJ_TP3(value)))
+#define AIPS_BWR_PACRJ_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP3 field. */
+#define AIPS_RD_PACRJ_WP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP3_MASK) >> AIPS_PACRJ_WP3_SHIFT)
+#define AIPS_BRD_PACRJ_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRJ_WP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP3_MASK, AIPS_PACRJ_WP3(value)))
+#define AIPS_BWR_PACRJ_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP3 field. */
+#define AIPS_RD_PACRJ_SP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP3_MASK) >> AIPS_PACRJ_SP3_SHIFT)
+#define AIPS_BRD_PACRJ_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRJ_SP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP3_MASK, AIPS_PACRJ_SP3(value)))
+#define AIPS_BWR_PACRJ_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP2 field. */
+#define AIPS_RD_PACRJ_TP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP2_MASK) >> AIPS_PACRJ_TP2_SHIFT)
+#define AIPS_BRD_PACRJ_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRJ_TP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP2_MASK, AIPS_PACRJ_TP2(value)))
+#define AIPS_BWR_PACRJ_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP2 field. */
+#define AIPS_RD_PACRJ_WP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP2_MASK) >> AIPS_PACRJ_WP2_SHIFT)
+#define AIPS_BRD_PACRJ_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRJ_WP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP2_MASK, AIPS_PACRJ_WP2(value)))
+#define AIPS_BWR_PACRJ_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP2 field. */
+#define AIPS_RD_PACRJ_SP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP2_MASK) >> AIPS_PACRJ_SP2_SHIFT)
+#define AIPS_BRD_PACRJ_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRJ_SP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP2_MASK, AIPS_PACRJ_SP2(value)))
+#define AIPS_BWR_PACRJ_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP1 field. */
+#define AIPS_RD_PACRJ_TP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP1_MASK) >> AIPS_PACRJ_TP1_SHIFT)
+#define AIPS_BRD_PACRJ_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRJ_TP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP1_MASK, AIPS_PACRJ_TP1(value)))
+#define AIPS_BWR_PACRJ_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP1 field. */
+#define AIPS_RD_PACRJ_WP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP1_MASK) >> AIPS_PACRJ_WP1_SHIFT)
+#define AIPS_BRD_PACRJ_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRJ_WP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP1_MASK, AIPS_PACRJ_WP1(value)))
+#define AIPS_BWR_PACRJ_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP1 field. */
+#define AIPS_RD_PACRJ_SP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP1_MASK) >> AIPS_PACRJ_SP1_SHIFT)
+#define AIPS_BRD_PACRJ_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRJ_SP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP1_MASK, AIPS_PACRJ_SP1(value)))
+#define AIPS_BWR_PACRJ_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP0 field. */
+#define AIPS_RD_PACRJ_TP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP0_MASK) >> AIPS_PACRJ_TP0_SHIFT)
+#define AIPS_BRD_PACRJ_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRJ_TP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP0_MASK, AIPS_PACRJ_TP0(value)))
+#define AIPS_BWR_PACRJ_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP0 field. */
+#define AIPS_RD_PACRJ_WP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP0_MASK) >> AIPS_PACRJ_WP0_SHIFT)
+#define AIPS_BRD_PACRJ_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRJ_WP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP0_MASK, AIPS_PACRJ_WP0(value)))
+#define AIPS_BWR_PACRJ_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP0 field. */
+#define AIPS_RD_PACRJ_SP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP0_MASK) >> AIPS_PACRJ_SP0_SHIFT)
+#define AIPS_BRD_PACRJ_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRJ_SP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP0_MASK, AIPS_PACRJ_SP0(value)))
+#define AIPS_BWR_PACRJ_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRK - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRK - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRK register
+ */
+/*@{*/
+#define AIPS_RD_PACRK(base)      (AIPS_PACRK_REG(base))
+#define AIPS_WR_PACRK(base, value) (AIPS_PACRK_REG(base) = (value))
+#define AIPS_RMW_PACRK(base, mask, value) (AIPS_WR_PACRK(base, (AIPS_RD_PACRK(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) |  (value)))
+#define AIPS_CLR_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) & ~(value)))
+#define AIPS_TOG_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRK bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRK, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP7 field. */
+#define AIPS_RD_PACRK_TP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP7_MASK) >> AIPS_PACRK_TP7_SHIFT)
+#define AIPS_BRD_PACRK_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRK_TP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP7_MASK, AIPS_PACRK_TP7(value)))
+#define AIPS_BWR_PACRK_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP7 field. */
+#define AIPS_RD_PACRK_WP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP7_MASK) >> AIPS_PACRK_WP7_SHIFT)
+#define AIPS_BRD_PACRK_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRK_WP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP7_MASK, AIPS_PACRK_WP7(value)))
+#define AIPS_BWR_PACRK_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP7 field. */
+#define AIPS_RD_PACRK_SP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP7_MASK) >> AIPS_PACRK_SP7_SHIFT)
+#define AIPS_BRD_PACRK_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRK_SP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP7_MASK, AIPS_PACRK_SP7(value)))
+#define AIPS_BWR_PACRK_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP6 field. */
+#define AIPS_RD_PACRK_TP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP6_MASK) >> AIPS_PACRK_TP6_SHIFT)
+#define AIPS_BRD_PACRK_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRK_TP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP6_MASK, AIPS_PACRK_TP6(value)))
+#define AIPS_BWR_PACRK_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP6 field. */
+#define AIPS_RD_PACRK_WP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP6_MASK) >> AIPS_PACRK_WP6_SHIFT)
+#define AIPS_BRD_PACRK_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRK_WP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP6_MASK, AIPS_PACRK_WP6(value)))
+#define AIPS_BWR_PACRK_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP6 field. */
+#define AIPS_RD_PACRK_SP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP6_MASK) >> AIPS_PACRK_SP6_SHIFT)
+#define AIPS_BRD_PACRK_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRK_SP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP6_MASK, AIPS_PACRK_SP6(value)))
+#define AIPS_BWR_PACRK_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP5 field. */
+#define AIPS_RD_PACRK_TP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP5_MASK) >> AIPS_PACRK_TP5_SHIFT)
+#define AIPS_BRD_PACRK_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRK_TP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP5_MASK, AIPS_PACRK_TP5(value)))
+#define AIPS_BWR_PACRK_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP5 field. */
+#define AIPS_RD_PACRK_WP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP5_MASK) >> AIPS_PACRK_WP5_SHIFT)
+#define AIPS_BRD_PACRK_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRK_WP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP5_MASK, AIPS_PACRK_WP5(value)))
+#define AIPS_BWR_PACRK_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP5 field. */
+#define AIPS_RD_PACRK_SP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP5_MASK) >> AIPS_PACRK_SP5_SHIFT)
+#define AIPS_BRD_PACRK_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRK_SP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP5_MASK, AIPS_PACRK_SP5(value)))
+#define AIPS_BWR_PACRK_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP4 field. */
+#define AIPS_RD_PACRK_TP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP4_MASK) >> AIPS_PACRK_TP4_SHIFT)
+#define AIPS_BRD_PACRK_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRK_TP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP4_MASK, AIPS_PACRK_TP4(value)))
+#define AIPS_BWR_PACRK_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP4 field. */
+#define AIPS_RD_PACRK_WP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP4_MASK) >> AIPS_PACRK_WP4_SHIFT)
+#define AIPS_BRD_PACRK_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRK_WP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP4_MASK, AIPS_PACRK_WP4(value)))
+#define AIPS_BWR_PACRK_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP4 field. */
+#define AIPS_RD_PACRK_SP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP4_MASK) >> AIPS_PACRK_SP4_SHIFT)
+#define AIPS_BRD_PACRK_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRK_SP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP4_MASK, AIPS_PACRK_SP4(value)))
+#define AIPS_BWR_PACRK_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP3 field. */
+#define AIPS_RD_PACRK_TP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP3_MASK) >> AIPS_PACRK_TP3_SHIFT)
+#define AIPS_BRD_PACRK_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRK_TP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP3_MASK, AIPS_PACRK_TP3(value)))
+#define AIPS_BWR_PACRK_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP3 field. */
+#define AIPS_RD_PACRK_WP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP3_MASK) >> AIPS_PACRK_WP3_SHIFT)
+#define AIPS_BRD_PACRK_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRK_WP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP3_MASK, AIPS_PACRK_WP3(value)))
+#define AIPS_BWR_PACRK_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP3 field. */
+#define AIPS_RD_PACRK_SP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP3_MASK) >> AIPS_PACRK_SP3_SHIFT)
+#define AIPS_BRD_PACRK_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRK_SP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP3_MASK, AIPS_PACRK_SP3(value)))
+#define AIPS_BWR_PACRK_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP2 field. */
+#define AIPS_RD_PACRK_TP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP2_MASK) >> AIPS_PACRK_TP2_SHIFT)
+#define AIPS_BRD_PACRK_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRK_TP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP2_MASK, AIPS_PACRK_TP2(value)))
+#define AIPS_BWR_PACRK_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP2 field. */
+#define AIPS_RD_PACRK_WP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP2_MASK) >> AIPS_PACRK_WP2_SHIFT)
+#define AIPS_BRD_PACRK_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRK_WP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP2_MASK, AIPS_PACRK_WP2(value)))
+#define AIPS_BWR_PACRK_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP2 field. */
+#define AIPS_RD_PACRK_SP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP2_MASK) >> AIPS_PACRK_SP2_SHIFT)
+#define AIPS_BRD_PACRK_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRK_SP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP2_MASK, AIPS_PACRK_SP2(value)))
+#define AIPS_BWR_PACRK_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP1 field. */
+#define AIPS_RD_PACRK_TP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP1_MASK) >> AIPS_PACRK_TP1_SHIFT)
+#define AIPS_BRD_PACRK_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRK_TP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP1_MASK, AIPS_PACRK_TP1(value)))
+#define AIPS_BWR_PACRK_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP1 field. */
+#define AIPS_RD_PACRK_WP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP1_MASK) >> AIPS_PACRK_WP1_SHIFT)
+#define AIPS_BRD_PACRK_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRK_WP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP1_MASK, AIPS_PACRK_WP1(value)))
+#define AIPS_BWR_PACRK_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP1 field. */
+#define AIPS_RD_PACRK_SP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP1_MASK) >> AIPS_PACRK_SP1_SHIFT)
+#define AIPS_BRD_PACRK_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRK_SP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP1_MASK, AIPS_PACRK_SP1(value)))
+#define AIPS_BWR_PACRK_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP0 field. */
+#define AIPS_RD_PACRK_TP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP0_MASK) >> AIPS_PACRK_TP0_SHIFT)
+#define AIPS_BRD_PACRK_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRK_TP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP0_MASK, AIPS_PACRK_TP0(value)))
+#define AIPS_BWR_PACRK_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP0 field. */
+#define AIPS_RD_PACRK_WP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP0_MASK) >> AIPS_PACRK_WP0_SHIFT)
+#define AIPS_BRD_PACRK_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRK_WP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP0_MASK, AIPS_PACRK_WP0(value)))
+#define AIPS_BWR_PACRK_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP0 field. */
+#define AIPS_RD_PACRK_SP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP0_MASK) >> AIPS_PACRK_SP0_SHIFT)
+#define AIPS_BRD_PACRK_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRK_SP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP0_MASK, AIPS_PACRK_SP0(value)))
+#define AIPS_BWR_PACRK_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRL - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRL - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRL register
+ */
+/*@{*/
+#define AIPS_RD_PACRL(base)      (AIPS_PACRL_REG(base))
+#define AIPS_WR_PACRL(base, value) (AIPS_PACRL_REG(base) = (value))
+#define AIPS_RMW_PACRL(base, mask, value) (AIPS_WR_PACRL(base, (AIPS_RD_PACRL(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) |  (value)))
+#define AIPS_CLR_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) & ~(value)))
+#define AIPS_TOG_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRL bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRL, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP7 field. */
+#define AIPS_RD_PACRL_TP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP7_MASK) >> AIPS_PACRL_TP7_SHIFT)
+#define AIPS_BRD_PACRL_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRL_TP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP7_MASK, AIPS_PACRL_TP7(value)))
+#define AIPS_BWR_PACRL_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP7 field. */
+#define AIPS_RD_PACRL_WP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP7_MASK) >> AIPS_PACRL_WP7_SHIFT)
+#define AIPS_BRD_PACRL_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRL_WP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP7_MASK, AIPS_PACRL_WP7(value)))
+#define AIPS_BWR_PACRL_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP7 field. */
+#define AIPS_RD_PACRL_SP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP7_MASK) >> AIPS_PACRL_SP7_SHIFT)
+#define AIPS_BRD_PACRL_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRL_SP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP7_MASK, AIPS_PACRL_SP7(value)))
+#define AIPS_BWR_PACRL_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP6 field. */
+#define AIPS_RD_PACRL_TP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP6_MASK) >> AIPS_PACRL_TP6_SHIFT)
+#define AIPS_BRD_PACRL_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRL_TP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP6_MASK, AIPS_PACRL_TP6(value)))
+#define AIPS_BWR_PACRL_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP6 field. */
+#define AIPS_RD_PACRL_WP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP6_MASK) >> AIPS_PACRL_WP6_SHIFT)
+#define AIPS_BRD_PACRL_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRL_WP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP6_MASK, AIPS_PACRL_WP6(value)))
+#define AIPS_BWR_PACRL_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP6 field. */
+#define AIPS_RD_PACRL_SP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP6_MASK) >> AIPS_PACRL_SP6_SHIFT)
+#define AIPS_BRD_PACRL_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRL_SP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP6_MASK, AIPS_PACRL_SP6(value)))
+#define AIPS_BWR_PACRL_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP5 field. */
+#define AIPS_RD_PACRL_TP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP5_MASK) >> AIPS_PACRL_TP5_SHIFT)
+#define AIPS_BRD_PACRL_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRL_TP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP5_MASK, AIPS_PACRL_TP5(value)))
+#define AIPS_BWR_PACRL_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP5 field. */
+#define AIPS_RD_PACRL_WP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP5_MASK) >> AIPS_PACRL_WP5_SHIFT)
+#define AIPS_BRD_PACRL_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRL_WP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP5_MASK, AIPS_PACRL_WP5(value)))
+#define AIPS_BWR_PACRL_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP5 field. */
+#define AIPS_RD_PACRL_SP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP5_MASK) >> AIPS_PACRL_SP5_SHIFT)
+#define AIPS_BRD_PACRL_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRL_SP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP5_MASK, AIPS_PACRL_SP5(value)))
+#define AIPS_BWR_PACRL_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP4 field. */
+#define AIPS_RD_PACRL_TP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP4_MASK) >> AIPS_PACRL_TP4_SHIFT)
+#define AIPS_BRD_PACRL_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRL_TP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP4_MASK, AIPS_PACRL_TP4(value)))
+#define AIPS_BWR_PACRL_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP4 field. */
+#define AIPS_RD_PACRL_WP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP4_MASK) >> AIPS_PACRL_WP4_SHIFT)
+#define AIPS_BRD_PACRL_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRL_WP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP4_MASK, AIPS_PACRL_WP4(value)))
+#define AIPS_BWR_PACRL_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP4 field. */
+#define AIPS_RD_PACRL_SP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP4_MASK) >> AIPS_PACRL_SP4_SHIFT)
+#define AIPS_BRD_PACRL_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRL_SP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP4_MASK, AIPS_PACRL_SP4(value)))
+#define AIPS_BWR_PACRL_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP3 field. */
+#define AIPS_RD_PACRL_TP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP3_MASK) >> AIPS_PACRL_TP3_SHIFT)
+#define AIPS_BRD_PACRL_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRL_TP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP3_MASK, AIPS_PACRL_TP3(value)))
+#define AIPS_BWR_PACRL_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP3 field. */
+#define AIPS_RD_PACRL_WP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP3_MASK) >> AIPS_PACRL_WP3_SHIFT)
+#define AIPS_BRD_PACRL_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRL_WP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP3_MASK, AIPS_PACRL_WP3(value)))
+#define AIPS_BWR_PACRL_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP3 field. */
+#define AIPS_RD_PACRL_SP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP3_MASK) >> AIPS_PACRL_SP3_SHIFT)
+#define AIPS_BRD_PACRL_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRL_SP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP3_MASK, AIPS_PACRL_SP3(value)))
+#define AIPS_BWR_PACRL_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP2 field. */
+#define AIPS_RD_PACRL_TP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP2_MASK) >> AIPS_PACRL_TP2_SHIFT)
+#define AIPS_BRD_PACRL_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRL_TP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP2_MASK, AIPS_PACRL_TP2(value)))
+#define AIPS_BWR_PACRL_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP2 field. */
+#define AIPS_RD_PACRL_WP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP2_MASK) >> AIPS_PACRL_WP2_SHIFT)
+#define AIPS_BRD_PACRL_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRL_WP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP2_MASK, AIPS_PACRL_WP2(value)))
+#define AIPS_BWR_PACRL_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP2 field. */
+#define AIPS_RD_PACRL_SP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP2_MASK) >> AIPS_PACRL_SP2_SHIFT)
+#define AIPS_BRD_PACRL_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRL_SP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP2_MASK, AIPS_PACRL_SP2(value)))
+#define AIPS_BWR_PACRL_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP1 field. */
+#define AIPS_RD_PACRL_TP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP1_MASK) >> AIPS_PACRL_TP1_SHIFT)
+#define AIPS_BRD_PACRL_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRL_TP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP1_MASK, AIPS_PACRL_TP1(value)))
+#define AIPS_BWR_PACRL_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP1 field. */
+#define AIPS_RD_PACRL_WP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP1_MASK) >> AIPS_PACRL_WP1_SHIFT)
+#define AIPS_BRD_PACRL_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRL_WP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP1_MASK, AIPS_PACRL_WP1(value)))
+#define AIPS_BWR_PACRL_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP1 field. */
+#define AIPS_RD_PACRL_SP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP1_MASK) >> AIPS_PACRL_SP1_SHIFT)
+#define AIPS_BRD_PACRL_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRL_SP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP1_MASK, AIPS_PACRL_SP1(value)))
+#define AIPS_BWR_PACRL_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP0 field. */
+#define AIPS_RD_PACRL_TP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP0_MASK) >> AIPS_PACRL_TP0_SHIFT)
+#define AIPS_BRD_PACRL_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRL_TP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP0_MASK, AIPS_PACRL_TP0(value)))
+#define AIPS_BWR_PACRL_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP0 field. */
+#define AIPS_RD_PACRL_WP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP0_MASK) >> AIPS_PACRL_WP0_SHIFT)
+#define AIPS_BRD_PACRL_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRL_WP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP0_MASK, AIPS_PACRL_WP0(value)))
+#define AIPS_BWR_PACRL_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP0 field. */
+#define AIPS_RD_PACRL_SP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP0_MASK) >> AIPS_PACRL_SP0_SHIFT)
+#define AIPS_BRD_PACRL_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRL_SP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP0_MASK, AIPS_PACRL_SP0(value)))
+#define AIPS_BWR_PACRL_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRM - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRM - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRM register
+ */
+/*@{*/
+#define AIPS_RD_PACRM(base)      (AIPS_PACRM_REG(base))
+#define AIPS_WR_PACRM(base, value) (AIPS_PACRM_REG(base) = (value))
+#define AIPS_RMW_PACRM(base, mask, value) (AIPS_WR_PACRM(base, (AIPS_RD_PACRM(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) |  (value)))
+#define AIPS_CLR_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) & ~(value)))
+#define AIPS_TOG_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRM bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRM, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP7 field. */
+#define AIPS_RD_PACRM_TP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP7_MASK) >> AIPS_PACRM_TP7_SHIFT)
+#define AIPS_BRD_PACRM_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRM_TP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP7_MASK, AIPS_PACRM_TP7(value)))
+#define AIPS_BWR_PACRM_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP7 field. */
+#define AIPS_RD_PACRM_WP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP7_MASK) >> AIPS_PACRM_WP7_SHIFT)
+#define AIPS_BRD_PACRM_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRM_WP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP7_MASK, AIPS_PACRM_WP7(value)))
+#define AIPS_BWR_PACRM_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP7 field. */
+#define AIPS_RD_PACRM_SP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP7_MASK) >> AIPS_PACRM_SP7_SHIFT)
+#define AIPS_BRD_PACRM_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRM_SP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP7_MASK, AIPS_PACRM_SP7(value)))
+#define AIPS_BWR_PACRM_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP6 field. */
+#define AIPS_RD_PACRM_TP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP6_MASK) >> AIPS_PACRM_TP6_SHIFT)
+#define AIPS_BRD_PACRM_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRM_TP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP6_MASK, AIPS_PACRM_TP6(value)))
+#define AIPS_BWR_PACRM_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP6 field. */
+#define AIPS_RD_PACRM_WP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP6_MASK) >> AIPS_PACRM_WP6_SHIFT)
+#define AIPS_BRD_PACRM_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRM_WP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP6_MASK, AIPS_PACRM_WP6(value)))
+#define AIPS_BWR_PACRM_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP6 field. */
+#define AIPS_RD_PACRM_SP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP6_MASK) >> AIPS_PACRM_SP6_SHIFT)
+#define AIPS_BRD_PACRM_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRM_SP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP6_MASK, AIPS_PACRM_SP6(value)))
+#define AIPS_BWR_PACRM_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP5 field. */
+#define AIPS_RD_PACRM_TP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP5_MASK) >> AIPS_PACRM_TP5_SHIFT)
+#define AIPS_BRD_PACRM_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRM_TP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP5_MASK, AIPS_PACRM_TP5(value)))
+#define AIPS_BWR_PACRM_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP5 field. */
+#define AIPS_RD_PACRM_WP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP5_MASK) >> AIPS_PACRM_WP5_SHIFT)
+#define AIPS_BRD_PACRM_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRM_WP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP5_MASK, AIPS_PACRM_WP5(value)))
+#define AIPS_BWR_PACRM_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP5 field. */
+#define AIPS_RD_PACRM_SP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP5_MASK) >> AIPS_PACRM_SP5_SHIFT)
+#define AIPS_BRD_PACRM_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRM_SP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP5_MASK, AIPS_PACRM_SP5(value)))
+#define AIPS_BWR_PACRM_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP4 field. */
+#define AIPS_RD_PACRM_TP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP4_MASK) >> AIPS_PACRM_TP4_SHIFT)
+#define AIPS_BRD_PACRM_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRM_TP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP4_MASK, AIPS_PACRM_TP4(value)))
+#define AIPS_BWR_PACRM_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP4 field. */
+#define AIPS_RD_PACRM_WP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP4_MASK) >> AIPS_PACRM_WP4_SHIFT)
+#define AIPS_BRD_PACRM_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRM_WP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP4_MASK, AIPS_PACRM_WP4(value)))
+#define AIPS_BWR_PACRM_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP4 field. */
+#define AIPS_RD_PACRM_SP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP4_MASK) >> AIPS_PACRM_SP4_SHIFT)
+#define AIPS_BRD_PACRM_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRM_SP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP4_MASK, AIPS_PACRM_SP4(value)))
+#define AIPS_BWR_PACRM_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP3 field. */
+#define AIPS_RD_PACRM_TP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP3_MASK) >> AIPS_PACRM_TP3_SHIFT)
+#define AIPS_BRD_PACRM_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRM_TP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP3_MASK, AIPS_PACRM_TP3(value)))
+#define AIPS_BWR_PACRM_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP3 field. */
+#define AIPS_RD_PACRM_WP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP3_MASK) >> AIPS_PACRM_WP3_SHIFT)
+#define AIPS_BRD_PACRM_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRM_WP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP3_MASK, AIPS_PACRM_WP3(value)))
+#define AIPS_BWR_PACRM_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP3 field. */
+#define AIPS_RD_PACRM_SP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP3_MASK) >> AIPS_PACRM_SP3_SHIFT)
+#define AIPS_BRD_PACRM_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRM_SP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP3_MASK, AIPS_PACRM_SP3(value)))
+#define AIPS_BWR_PACRM_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP2 field. */
+#define AIPS_RD_PACRM_TP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP2_MASK) >> AIPS_PACRM_TP2_SHIFT)
+#define AIPS_BRD_PACRM_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRM_TP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP2_MASK, AIPS_PACRM_TP2(value)))
+#define AIPS_BWR_PACRM_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP2 field. */
+#define AIPS_RD_PACRM_WP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP2_MASK) >> AIPS_PACRM_WP2_SHIFT)
+#define AIPS_BRD_PACRM_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRM_WP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP2_MASK, AIPS_PACRM_WP2(value)))
+#define AIPS_BWR_PACRM_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP2 field. */
+#define AIPS_RD_PACRM_SP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP2_MASK) >> AIPS_PACRM_SP2_SHIFT)
+#define AIPS_BRD_PACRM_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRM_SP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP2_MASK, AIPS_PACRM_SP2(value)))
+#define AIPS_BWR_PACRM_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP1 field. */
+#define AIPS_RD_PACRM_TP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP1_MASK) >> AIPS_PACRM_TP1_SHIFT)
+#define AIPS_BRD_PACRM_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRM_TP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP1_MASK, AIPS_PACRM_TP1(value)))
+#define AIPS_BWR_PACRM_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP1 field. */
+#define AIPS_RD_PACRM_WP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP1_MASK) >> AIPS_PACRM_WP1_SHIFT)
+#define AIPS_BRD_PACRM_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRM_WP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP1_MASK, AIPS_PACRM_WP1(value)))
+#define AIPS_BWR_PACRM_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP1 field. */
+#define AIPS_RD_PACRM_SP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP1_MASK) >> AIPS_PACRM_SP1_SHIFT)
+#define AIPS_BRD_PACRM_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRM_SP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP1_MASK, AIPS_PACRM_SP1(value)))
+#define AIPS_BWR_PACRM_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP0 field. */
+#define AIPS_RD_PACRM_TP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP0_MASK) >> AIPS_PACRM_TP0_SHIFT)
+#define AIPS_BRD_PACRM_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRM_TP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP0_MASK, AIPS_PACRM_TP0(value)))
+#define AIPS_BWR_PACRM_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP0 field. */
+#define AIPS_RD_PACRM_WP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP0_MASK) >> AIPS_PACRM_WP0_SHIFT)
+#define AIPS_BRD_PACRM_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRM_WP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP0_MASK, AIPS_PACRM_WP0(value)))
+#define AIPS_BWR_PACRM_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP0 field. */
+#define AIPS_RD_PACRM_SP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP0_MASK) >> AIPS_PACRM_SP0_SHIFT)
+#define AIPS_BRD_PACRM_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRM_SP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP0_MASK, AIPS_PACRM_SP0(value)))
+#define AIPS_BWR_PACRM_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRN - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRN - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRN register
+ */
+/*@{*/
+#define AIPS_RD_PACRN(base)      (AIPS_PACRN_REG(base))
+#define AIPS_WR_PACRN(base, value) (AIPS_PACRN_REG(base) = (value))
+#define AIPS_RMW_PACRN(base, mask, value) (AIPS_WR_PACRN(base, (AIPS_RD_PACRN(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) |  (value)))
+#define AIPS_CLR_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) & ~(value)))
+#define AIPS_TOG_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRN bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRN, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP7 field. */
+#define AIPS_RD_PACRN_TP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP7_MASK) >> AIPS_PACRN_TP7_SHIFT)
+#define AIPS_BRD_PACRN_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRN_TP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP7_MASK, AIPS_PACRN_TP7(value)))
+#define AIPS_BWR_PACRN_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP7 field. */
+#define AIPS_RD_PACRN_WP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP7_MASK) >> AIPS_PACRN_WP7_SHIFT)
+#define AIPS_BRD_PACRN_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRN_WP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP7_MASK, AIPS_PACRN_WP7(value)))
+#define AIPS_BWR_PACRN_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP7 field. */
+#define AIPS_RD_PACRN_SP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP7_MASK) >> AIPS_PACRN_SP7_SHIFT)
+#define AIPS_BRD_PACRN_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRN_SP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP7_MASK, AIPS_PACRN_SP7(value)))
+#define AIPS_BWR_PACRN_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP6 field. */
+#define AIPS_RD_PACRN_TP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP6_MASK) >> AIPS_PACRN_TP6_SHIFT)
+#define AIPS_BRD_PACRN_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRN_TP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP6_MASK, AIPS_PACRN_TP6(value)))
+#define AIPS_BWR_PACRN_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP6 field. */
+#define AIPS_RD_PACRN_WP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP6_MASK) >> AIPS_PACRN_WP6_SHIFT)
+#define AIPS_BRD_PACRN_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRN_WP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP6_MASK, AIPS_PACRN_WP6(value)))
+#define AIPS_BWR_PACRN_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP6 field. */
+#define AIPS_RD_PACRN_SP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP6_MASK) >> AIPS_PACRN_SP6_SHIFT)
+#define AIPS_BRD_PACRN_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRN_SP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP6_MASK, AIPS_PACRN_SP6(value)))
+#define AIPS_BWR_PACRN_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP5 field. */
+#define AIPS_RD_PACRN_TP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP5_MASK) >> AIPS_PACRN_TP5_SHIFT)
+#define AIPS_BRD_PACRN_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRN_TP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP5_MASK, AIPS_PACRN_TP5(value)))
+#define AIPS_BWR_PACRN_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP5 field. */
+#define AIPS_RD_PACRN_WP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP5_MASK) >> AIPS_PACRN_WP5_SHIFT)
+#define AIPS_BRD_PACRN_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRN_WP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP5_MASK, AIPS_PACRN_WP5(value)))
+#define AIPS_BWR_PACRN_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP5 field. */
+#define AIPS_RD_PACRN_SP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP5_MASK) >> AIPS_PACRN_SP5_SHIFT)
+#define AIPS_BRD_PACRN_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRN_SP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP5_MASK, AIPS_PACRN_SP5(value)))
+#define AIPS_BWR_PACRN_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP4 field. */
+#define AIPS_RD_PACRN_TP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP4_MASK) >> AIPS_PACRN_TP4_SHIFT)
+#define AIPS_BRD_PACRN_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRN_TP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP4_MASK, AIPS_PACRN_TP4(value)))
+#define AIPS_BWR_PACRN_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP4 field. */
+#define AIPS_RD_PACRN_WP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP4_MASK) >> AIPS_PACRN_WP4_SHIFT)
+#define AIPS_BRD_PACRN_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRN_WP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP4_MASK, AIPS_PACRN_WP4(value)))
+#define AIPS_BWR_PACRN_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP4 field. */
+#define AIPS_RD_PACRN_SP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP4_MASK) >> AIPS_PACRN_SP4_SHIFT)
+#define AIPS_BRD_PACRN_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRN_SP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP4_MASK, AIPS_PACRN_SP4(value)))
+#define AIPS_BWR_PACRN_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP3 field. */
+#define AIPS_RD_PACRN_TP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP3_MASK) >> AIPS_PACRN_TP3_SHIFT)
+#define AIPS_BRD_PACRN_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRN_TP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP3_MASK, AIPS_PACRN_TP3(value)))
+#define AIPS_BWR_PACRN_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP3 field. */
+#define AIPS_RD_PACRN_WP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP3_MASK) >> AIPS_PACRN_WP3_SHIFT)
+#define AIPS_BRD_PACRN_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRN_WP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP3_MASK, AIPS_PACRN_WP3(value)))
+#define AIPS_BWR_PACRN_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP3 field. */
+#define AIPS_RD_PACRN_SP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP3_MASK) >> AIPS_PACRN_SP3_SHIFT)
+#define AIPS_BRD_PACRN_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRN_SP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP3_MASK, AIPS_PACRN_SP3(value)))
+#define AIPS_BWR_PACRN_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP2 field. */
+#define AIPS_RD_PACRN_TP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP2_MASK) >> AIPS_PACRN_TP2_SHIFT)
+#define AIPS_BRD_PACRN_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRN_TP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP2_MASK, AIPS_PACRN_TP2(value)))
+#define AIPS_BWR_PACRN_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP2 field. */
+#define AIPS_RD_PACRN_WP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP2_MASK) >> AIPS_PACRN_WP2_SHIFT)
+#define AIPS_BRD_PACRN_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRN_WP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP2_MASK, AIPS_PACRN_WP2(value)))
+#define AIPS_BWR_PACRN_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP2 field. */
+#define AIPS_RD_PACRN_SP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP2_MASK) >> AIPS_PACRN_SP2_SHIFT)
+#define AIPS_BRD_PACRN_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRN_SP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP2_MASK, AIPS_PACRN_SP2(value)))
+#define AIPS_BWR_PACRN_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP1 field. */
+#define AIPS_RD_PACRN_TP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP1_MASK) >> AIPS_PACRN_TP1_SHIFT)
+#define AIPS_BRD_PACRN_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRN_TP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP1_MASK, AIPS_PACRN_TP1(value)))
+#define AIPS_BWR_PACRN_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP1 field. */
+#define AIPS_RD_PACRN_WP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP1_MASK) >> AIPS_PACRN_WP1_SHIFT)
+#define AIPS_BRD_PACRN_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRN_WP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP1_MASK, AIPS_PACRN_WP1(value)))
+#define AIPS_BWR_PACRN_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP1 field. */
+#define AIPS_RD_PACRN_SP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP1_MASK) >> AIPS_PACRN_SP1_SHIFT)
+#define AIPS_BRD_PACRN_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRN_SP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP1_MASK, AIPS_PACRN_SP1(value)))
+#define AIPS_BWR_PACRN_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP0 field. */
+#define AIPS_RD_PACRN_TP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP0_MASK) >> AIPS_PACRN_TP0_SHIFT)
+#define AIPS_BRD_PACRN_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRN_TP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP0_MASK, AIPS_PACRN_TP0(value)))
+#define AIPS_BWR_PACRN_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP0 field. */
+#define AIPS_RD_PACRN_WP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP0_MASK) >> AIPS_PACRN_WP0_SHIFT)
+#define AIPS_BRD_PACRN_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRN_WP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP0_MASK, AIPS_PACRN_WP0(value)))
+#define AIPS_BWR_PACRN_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP0 field. */
+#define AIPS_RD_PACRN_SP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP0_MASK) >> AIPS_PACRN_SP0_SHIFT)
+#define AIPS_BRD_PACRN_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRN_SP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP0_MASK, AIPS_PACRN_SP0(value)))
+#define AIPS_BWR_PACRN_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRO - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRO - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRO register
+ */
+/*@{*/
+#define AIPS_RD_PACRO(base)      (AIPS_PACRO_REG(base))
+#define AIPS_WR_PACRO(base, value) (AIPS_PACRO_REG(base) = (value))
+#define AIPS_RMW_PACRO(base, mask, value) (AIPS_WR_PACRO(base, (AIPS_RD_PACRO(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) |  (value)))
+#define AIPS_CLR_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) & ~(value)))
+#define AIPS_TOG_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRO bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRO, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP7 field. */
+#define AIPS_RD_PACRO_TP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP7_MASK) >> AIPS_PACRO_TP7_SHIFT)
+#define AIPS_BRD_PACRO_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRO_TP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP7_MASK, AIPS_PACRO_TP7(value)))
+#define AIPS_BWR_PACRO_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP7 field. */
+#define AIPS_RD_PACRO_WP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP7_MASK) >> AIPS_PACRO_WP7_SHIFT)
+#define AIPS_BRD_PACRO_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRO_WP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP7_MASK, AIPS_PACRO_WP7(value)))
+#define AIPS_BWR_PACRO_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP7 field. */
+#define AIPS_RD_PACRO_SP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP7_MASK) >> AIPS_PACRO_SP7_SHIFT)
+#define AIPS_BRD_PACRO_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRO_SP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP7_MASK, AIPS_PACRO_SP7(value)))
+#define AIPS_BWR_PACRO_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP6 field. */
+#define AIPS_RD_PACRO_TP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP6_MASK) >> AIPS_PACRO_TP6_SHIFT)
+#define AIPS_BRD_PACRO_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRO_TP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP6_MASK, AIPS_PACRO_TP6(value)))
+#define AIPS_BWR_PACRO_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP6 field. */
+#define AIPS_RD_PACRO_WP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP6_MASK) >> AIPS_PACRO_WP6_SHIFT)
+#define AIPS_BRD_PACRO_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRO_WP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP6_MASK, AIPS_PACRO_WP6(value)))
+#define AIPS_BWR_PACRO_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP6 field. */
+#define AIPS_RD_PACRO_SP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP6_MASK) >> AIPS_PACRO_SP6_SHIFT)
+#define AIPS_BRD_PACRO_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRO_SP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP6_MASK, AIPS_PACRO_SP6(value)))
+#define AIPS_BWR_PACRO_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP5 field. */
+#define AIPS_RD_PACRO_TP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP5_MASK) >> AIPS_PACRO_TP5_SHIFT)
+#define AIPS_BRD_PACRO_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRO_TP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP5_MASK, AIPS_PACRO_TP5(value)))
+#define AIPS_BWR_PACRO_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP5 field. */
+#define AIPS_RD_PACRO_WP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP5_MASK) >> AIPS_PACRO_WP5_SHIFT)
+#define AIPS_BRD_PACRO_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRO_WP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP5_MASK, AIPS_PACRO_WP5(value)))
+#define AIPS_BWR_PACRO_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP5 field. */
+#define AIPS_RD_PACRO_SP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP5_MASK) >> AIPS_PACRO_SP5_SHIFT)
+#define AIPS_BRD_PACRO_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRO_SP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP5_MASK, AIPS_PACRO_SP5(value)))
+#define AIPS_BWR_PACRO_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP4 field. */
+#define AIPS_RD_PACRO_TP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP4_MASK) >> AIPS_PACRO_TP4_SHIFT)
+#define AIPS_BRD_PACRO_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRO_TP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP4_MASK, AIPS_PACRO_TP4(value)))
+#define AIPS_BWR_PACRO_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP4 field. */
+#define AIPS_RD_PACRO_WP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP4_MASK) >> AIPS_PACRO_WP4_SHIFT)
+#define AIPS_BRD_PACRO_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRO_WP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP4_MASK, AIPS_PACRO_WP4(value)))
+#define AIPS_BWR_PACRO_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP4 field. */
+#define AIPS_RD_PACRO_SP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP4_MASK) >> AIPS_PACRO_SP4_SHIFT)
+#define AIPS_BRD_PACRO_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRO_SP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP4_MASK, AIPS_PACRO_SP4(value)))
+#define AIPS_BWR_PACRO_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP3 field. */
+#define AIPS_RD_PACRO_TP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP3_MASK) >> AIPS_PACRO_TP3_SHIFT)
+#define AIPS_BRD_PACRO_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRO_TP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP3_MASK, AIPS_PACRO_TP3(value)))
+#define AIPS_BWR_PACRO_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP3 field. */
+#define AIPS_RD_PACRO_WP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP3_MASK) >> AIPS_PACRO_WP3_SHIFT)
+#define AIPS_BRD_PACRO_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRO_WP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP3_MASK, AIPS_PACRO_WP3(value)))
+#define AIPS_BWR_PACRO_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP3 field. */
+#define AIPS_RD_PACRO_SP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP3_MASK) >> AIPS_PACRO_SP3_SHIFT)
+#define AIPS_BRD_PACRO_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRO_SP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP3_MASK, AIPS_PACRO_SP3(value)))
+#define AIPS_BWR_PACRO_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP2 field. */
+#define AIPS_RD_PACRO_TP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP2_MASK) >> AIPS_PACRO_TP2_SHIFT)
+#define AIPS_BRD_PACRO_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRO_TP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP2_MASK, AIPS_PACRO_TP2(value)))
+#define AIPS_BWR_PACRO_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP2 field. */
+#define AIPS_RD_PACRO_WP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP2_MASK) >> AIPS_PACRO_WP2_SHIFT)
+#define AIPS_BRD_PACRO_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRO_WP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP2_MASK, AIPS_PACRO_WP2(value)))
+#define AIPS_BWR_PACRO_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP2 field. */
+#define AIPS_RD_PACRO_SP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP2_MASK) >> AIPS_PACRO_SP2_SHIFT)
+#define AIPS_BRD_PACRO_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRO_SP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP2_MASK, AIPS_PACRO_SP2(value)))
+#define AIPS_BWR_PACRO_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP1 field. */
+#define AIPS_RD_PACRO_TP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP1_MASK) >> AIPS_PACRO_TP1_SHIFT)
+#define AIPS_BRD_PACRO_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRO_TP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP1_MASK, AIPS_PACRO_TP1(value)))
+#define AIPS_BWR_PACRO_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP1 field. */
+#define AIPS_RD_PACRO_WP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP1_MASK) >> AIPS_PACRO_WP1_SHIFT)
+#define AIPS_BRD_PACRO_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRO_WP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP1_MASK, AIPS_PACRO_WP1(value)))
+#define AIPS_BWR_PACRO_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP1 field. */
+#define AIPS_RD_PACRO_SP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP1_MASK) >> AIPS_PACRO_SP1_SHIFT)
+#define AIPS_BRD_PACRO_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRO_SP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP1_MASK, AIPS_PACRO_SP1(value)))
+#define AIPS_BWR_PACRO_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP0 field. */
+#define AIPS_RD_PACRO_TP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP0_MASK) >> AIPS_PACRO_TP0_SHIFT)
+#define AIPS_BRD_PACRO_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRO_TP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP0_MASK, AIPS_PACRO_TP0(value)))
+#define AIPS_BWR_PACRO_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP0 field. */
+#define AIPS_RD_PACRO_WP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP0_MASK) >> AIPS_PACRO_WP0_SHIFT)
+#define AIPS_BRD_PACRO_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRO_WP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP0_MASK, AIPS_PACRO_WP0(value)))
+#define AIPS_BWR_PACRO_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP0 field. */
+#define AIPS_RD_PACRO_SP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP0_MASK) >> AIPS_PACRO_SP0_SHIFT)
+#define AIPS_BRD_PACRO_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRO_SP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP0_MASK, AIPS_PACRO_SP0(value)))
+#define AIPS_BWR_PACRO_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRP - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRP - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRP register
+ */
+/*@{*/
+#define AIPS_RD_PACRP(base)      (AIPS_PACRP_REG(base))
+#define AIPS_WR_PACRP(base, value) (AIPS_PACRP_REG(base) = (value))
+#define AIPS_RMW_PACRP(base, mask, value) (AIPS_WR_PACRP(base, (AIPS_RD_PACRP(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) |  (value)))
+#define AIPS_CLR_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) & ~(value)))
+#define AIPS_TOG_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRP bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRP, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP7 field. */
+#define AIPS_RD_PACRP_TP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP7_MASK) >> AIPS_PACRP_TP7_SHIFT)
+#define AIPS_BRD_PACRP_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRP_TP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP7_MASK, AIPS_PACRP_TP7(value)))
+#define AIPS_BWR_PACRP_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP7 field. */
+#define AIPS_RD_PACRP_WP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP7_MASK) >> AIPS_PACRP_WP7_SHIFT)
+#define AIPS_BRD_PACRP_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRP_WP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP7_MASK, AIPS_PACRP_WP7(value)))
+#define AIPS_BWR_PACRP_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP7 field. */
+#define AIPS_RD_PACRP_SP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP7_MASK) >> AIPS_PACRP_SP7_SHIFT)
+#define AIPS_BRD_PACRP_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRP_SP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP7_MASK, AIPS_PACRP_SP7(value)))
+#define AIPS_BWR_PACRP_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP6 field. */
+#define AIPS_RD_PACRP_TP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP6_MASK) >> AIPS_PACRP_TP6_SHIFT)
+#define AIPS_BRD_PACRP_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRP_TP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP6_MASK, AIPS_PACRP_TP6(value)))
+#define AIPS_BWR_PACRP_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP6 field. */
+#define AIPS_RD_PACRP_WP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP6_MASK) >> AIPS_PACRP_WP6_SHIFT)
+#define AIPS_BRD_PACRP_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRP_WP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP6_MASK, AIPS_PACRP_WP6(value)))
+#define AIPS_BWR_PACRP_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP6 field. */
+#define AIPS_RD_PACRP_SP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP6_MASK) >> AIPS_PACRP_SP6_SHIFT)
+#define AIPS_BRD_PACRP_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRP_SP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP6_MASK, AIPS_PACRP_SP6(value)))
+#define AIPS_BWR_PACRP_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP5 field. */
+#define AIPS_RD_PACRP_TP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP5_MASK) >> AIPS_PACRP_TP5_SHIFT)
+#define AIPS_BRD_PACRP_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRP_TP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP5_MASK, AIPS_PACRP_TP5(value)))
+#define AIPS_BWR_PACRP_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP5 field. */
+#define AIPS_RD_PACRP_WP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP5_MASK) >> AIPS_PACRP_WP5_SHIFT)
+#define AIPS_BRD_PACRP_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRP_WP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP5_MASK, AIPS_PACRP_WP5(value)))
+#define AIPS_BWR_PACRP_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP5 field. */
+#define AIPS_RD_PACRP_SP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP5_MASK) >> AIPS_PACRP_SP5_SHIFT)
+#define AIPS_BRD_PACRP_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRP_SP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP5_MASK, AIPS_PACRP_SP5(value)))
+#define AIPS_BWR_PACRP_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP4 field. */
+#define AIPS_RD_PACRP_TP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP4_MASK) >> AIPS_PACRP_TP4_SHIFT)
+#define AIPS_BRD_PACRP_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRP_TP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP4_MASK, AIPS_PACRP_TP4(value)))
+#define AIPS_BWR_PACRP_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP4 field. */
+#define AIPS_RD_PACRP_WP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP4_MASK) >> AIPS_PACRP_WP4_SHIFT)
+#define AIPS_BRD_PACRP_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRP_WP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP4_MASK, AIPS_PACRP_WP4(value)))
+#define AIPS_BWR_PACRP_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP4 field. */
+#define AIPS_RD_PACRP_SP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP4_MASK) >> AIPS_PACRP_SP4_SHIFT)
+#define AIPS_BRD_PACRP_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRP_SP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP4_MASK, AIPS_PACRP_SP4(value)))
+#define AIPS_BWR_PACRP_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP3 field. */
+#define AIPS_RD_PACRP_TP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP3_MASK) >> AIPS_PACRP_TP3_SHIFT)
+#define AIPS_BRD_PACRP_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRP_TP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP3_MASK, AIPS_PACRP_TP3(value)))
+#define AIPS_BWR_PACRP_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP3 field. */
+#define AIPS_RD_PACRP_WP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP3_MASK) >> AIPS_PACRP_WP3_SHIFT)
+#define AIPS_BRD_PACRP_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRP_WP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP3_MASK, AIPS_PACRP_WP3(value)))
+#define AIPS_BWR_PACRP_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP3 field. */
+#define AIPS_RD_PACRP_SP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP3_MASK) >> AIPS_PACRP_SP3_SHIFT)
+#define AIPS_BRD_PACRP_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRP_SP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP3_MASK, AIPS_PACRP_SP3(value)))
+#define AIPS_BWR_PACRP_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP2 field. */
+#define AIPS_RD_PACRP_TP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP2_MASK) >> AIPS_PACRP_TP2_SHIFT)
+#define AIPS_BRD_PACRP_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRP_TP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP2_MASK, AIPS_PACRP_TP2(value)))
+#define AIPS_BWR_PACRP_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP2 field. */
+#define AIPS_RD_PACRP_WP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP2_MASK) >> AIPS_PACRP_WP2_SHIFT)
+#define AIPS_BRD_PACRP_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRP_WP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP2_MASK, AIPS_PACRP_WP2(value)))
+#define AIPS_BWR_PACRP_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP2 field. */
+#define AIPS_RD_PACRP_SP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP2_MASK) >> AIPS_PACRP_SP2_SHIFT)
+#define AIPS_BRD_PACRP_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRP_SP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP2_MASK, AIPS_PACRP_SP2(value)))
+#define AIPS_BWR_PACRP_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP1 field. */
+#define AIPS_RD_PACRP_TP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP1_MASK) >> AIPS_PACRP_TP1_SHIFT)
+#define AIPS_BRD_PACRP_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRP_TP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP1_MASK, AIPS_PACRP_TP1(value)))
+#define AIPS_BWR_PACRP_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP1 field. */
+#define AIPS_RD_PACRP_WP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP1_MASK) >> AIPS_PACRP_WP1_SHIFT)
+#define AIPS_BRD_PACRP_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRP_WP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP1_MASK, AIPS_PACRP_WP1(value)))
+#define AIPS_BWR_PACRP_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP1 field. */
+#define AIPS_RD_PACRP_SP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP1_MASK) >> AIPS_PACRP_SP1_SHIFT)
+#define AIPS_BRD_PACRP_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRP_SP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP1_MASK, AIPS_PACRP_SP1(value)))
+#define AIPS_BWR_PACRP_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP0 field. */
+#define AIPS_RD_PACRP_TP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP0_MASK) >> AIPS_PACRP_TP0_SHIFT)
+#define AIPS_BRD_PACRP_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRP_TP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP0_MASK, AIPS_PACRP_TP0(value)))
+#define AIPS_BWR_PACRP_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP0 field. */
+#define AIPS_RD_PACRP_WP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP0_MASK) >> AIPS_PACRP_WP0_SHIFT)
+#define AIPS_BRD_PACRP_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRP_WP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP0_MASK, AIPS_PACRP_WP0(value)))
+#define AIPS_BWR_PACRP_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP0 field. */
+#define AIPS_RD_PACRP_SP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP0_MASK) >> AIPS_PACRP_SP0_SHIFT)
+#define AIPS_BRD_PACRP_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRP_SP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP0_MASK, AIPS_PACRP_SP0(value)))
+#define AIPS_BWR_PACRP_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRU - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRU - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44000000U
+ *
+ * PACRU defines the access levels for the two global spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRU register
+ */
+/*@{*/
+#define AIPS_RD_PACRU(base)      (AIPS_PACRU_REG(base))
+#define AIPS_WR_PACRU(base, value) (AIPS_PACRU_REG(base) = (value))
+#define AIPS_RMW_PACRU(base, mask, value) (AIPS_WR_PACRU(base, (AIPS_RD_PACRU(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) |  (value)))
+#define AIPS_CLR_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) & ~(value)))
+#define AIPS_TOG_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRU bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRU, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_TP1 field. */
+#define AIPS_RD_PACRU_TP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_TP1_MASK) >> AIPS_PACRU_TP1_SHIFT)
+#define AIPS_BRD_PACRU_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRU_TP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_TP1_MASK, AIPS_PACRU_TP1(value)))
+#define AIPS_BWR_PACRU_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_WP1 field. */
+#define AIPS_RD_PACRU_WP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_WP1_MASK) >> AIPS_PACRU_WP1_SHIFT)
+#define AIPS_BRD_PACRU_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRU_WP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_WP1_MASK, AIPS_PACRU_WP1(value)))
+#define AIPS_BWR_PACRU_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_SP1 field. */
+#define AIPS_RD_PACRU_SP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_SP1_MASK) >> AIPS_PACRU_SP1_SHIFT)
+#define AIPS_BRD_PACRU_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRU_SP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_SP1_MASK, AIPS_PACRU_SP1(value)))
+#define AIPS_BWR_PACRU_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_TP0 field. */
+#define AIPS_RD_PACRU_TP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_TP0_MASK) >> AIPS_PACRU_TP0_SHIFT)
+#define AIPS_BRD_PACRU_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRU_TP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_TP0_MASK, AIPS_PACRU_TP0(value)))
+#define AIPS_BWR_PACRU_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_WP0 field. */
+#define AIPS_RD_PACRU_WP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_WP0_MASK) >> AIPS_PACRU_WP0_SHIFT)
+#define AIPS_BRD_PACRU_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRU_WP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_WP0_MASK, AIPS_PACRU_WP0(value)))
+#define AIPS_BWR_PACRU_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_SP0 field. */
+#define AIPS_RD_PACRU_SP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_SP0_MASK) >> AIPS_PACRU_SP0_SHIFT)
+#define AIPS_BRD_PACRU_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRU_SP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_SP0_MASK, AIPS_PACRU_SP0(value)))
+#define AIPS_BWR_PACRU_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP0_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 AXBS
+ *
+ * Crossbar switch
+ *
+ * Registers defined in this header file:
+ * - AXBS_PRS - Priority Registers Slave
+ * - AXBS_CRS - Control Register
+ * - AXBS_MGPCR0 - Master General Purpose Control Register
+ * - AXBS_MGPCR1 - Master General Purpose Control Register
+ * - AXBS_MGPCR2 - Master General Purpose Control Register
+ * - AXBS_MGPCR3 - Master General Purpose Control Register
+ * - AXBS_MGPCR4 - Master General Purpose Control Register
+ * - AXBS_MGPCR5 - Master General Purpose Control Register
+ */
+
+#define AXBS_INSTANCE_COUNT (1U) /*!< Number of instances of the AXBS module. */
+#define AXBS_IDX (0U) /*!< Instance number for AXBS. */
+
+/*******************************************************************************
+ * AXBS_PRS - Priority Registers Slave
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_PRS - Priority Registers Slave (RW)
+ *
+ * Reset value: 0x00543210U
+ *
+ * The priority registers (PRSn) set the priority of each master port on a per
+ * slave port basis and reside in each slave port. The priority register can be
+ * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
+ * register can only be read; attempts to write to it have no effect on PRSn and
+ * result in a bus-error response to the master initiating the write. Two available
+ * masters must not be programmed with the same priority level. Attempts to
+ * program two or more masters with the same priority level result in a bus-error
+ * response and the PRSn is not updated. Valid values for the Mn priority fields
+ * depend on which masters are available on the chip. This information can be found in
+ * the chip-specific information for the crossbar. If the chip contains less
+ * than five masters, values 0 to 3 are valid. Writing other values will result in
+ * an error. If the chip contains five or more masters, valid values are 0 to n-1,
+ * where n is the number of masters attached to the AXBS module. Other values
+ * will result in an error.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_PRS register
+ */
+/*@{*/
+#define AXBS_RD_PRS(base, index) (AXBS_PRS_REG(base, index))
+#define AXBS_WR_PRS(base, index, value) (AXBS_PRS_REG(base, index) = (value))
+#define AXBS_RMW_PRS(base, index, mask, value) (AXBS_WR_PRS(base, index, (AXBS_RD_PRS(base, index) & ~(mask)) | (value)))
+#define AXBS_SET_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) |  (value)))
+#define AXBS_CLR_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) & ~(value)))
+#define AXBS_TOG_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_PRS bitfields
+ */
+
+/*!
+ * @name Register AXBS_PRS, field M0[2:0] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M0 field. */
+#define AXBS_RD_PRS_M0(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M0_MASK) >> AXBS_PRS_M0_SHIFT)
+#define AXBS_BRD_PRS_M0(base, index) (AXBS_RD_PRS_M0(base, index))
+
+/*! @brief Set the M0 field to a new value. */
+#define AXBS_WR_PRS_M0(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M0_MASK, AXBS_PRS_M0(value)))
+#define AXBS_BWR_PRS_M0(base, index, value) (AXBS_WR_PRS_M0(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M1[6:4] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M1 field. */
+#define AXBS_RD_PRS_M1(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M1_MASK) >> AXBS_PRS_M1_SHIFT)
+#define AXBS_BRD_PRS_M1(base, index) (AXBS_RD_PRS_M1(base, index))
+
+/*! @brief Set the M1 field to a new value. */
+#define AXBS_WR_PRS_M1(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M1_MASK, AXBS_PRS_M1(value)))
+#define AXBS_BWR_PRS_M1(base, index, value) (AXBS_WR_PRS_M1(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M2[10:8] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M2 field. */
+#define AXBS_RD_PRS_M2(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M2_MASK) >> AXBS_PRS_M2_SHIFT)
+#define AXBS_BRD_PRS_M2(base, index) (AXBS_RD_PRS_M2(base, index))
+
+/*! @brief Set the M2 field to a new value. */
+#define AXBS_WR_PRS_M2(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M2_MASK, AXBS_PRS_M2(value)))
+#define AXBS_BWR_PRS_M2(base, index, value) (AXBS_WR_PRS_M2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M3[14:12] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M3 field. */
+#define AXBS_RD_PRS_M3(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M3_MASK) >> AXBS_PRS_M3_SHIFT)
+#define AXBS_BRD_PRS_M3(base, index) (AXBS_RD_PRS_M3(base, index))
+
+/*! @brief Set the M3 field to a new value. */
+#define AXBS_WR_PRS_M3(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M3_MASK, AXBS_PRS_M3(value)))
+#define AXBS_BWR_PRS_M3(base, index, value) (AXBS_WR_PRS_M3(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M4[18:16] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M4 field. */
+#define AXBS_RD_PRS_M4(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M4_MASK) >> AXBS_PRS_M4_SHIFT)
+#define AXBS_BRD_PRS_M4(base, index) (AXBS_RD_PRS_M4(base, index))
+
+/*! @brief Set the M4 field to a new value. */
+#define AXBS_WR_PRS_M4(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M4_MASK, AXBS_PRS_M4(value)))
+#define AXBS_BWR_PRS_M4(base, index, value) (AXBS_WR_PRS_M4(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M5[22:20] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M5 field. */
+#define AXBS_RD_PRS_M5(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M5_MASK) >> AXBS_PRS_M5_SHIFT)
+#define AXBS_BRD_PRS_M5(base, index) (AXBS_RD_PRS_M5(base, index))
+
+/*! @brief Set the M5 field to a new value. */
+#define AXBS_WR_PRS_M5(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M5_MASK, AXBS_PRS_M5(value)))
+#define AXBS_BWR_PRS_M5(base, index, value) (AXBS_WR_PRS_M5(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_CRS - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_CRS - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers control several features of each slave port and must be
+ * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
+ * attempts to write to it have no effect and result in an error response.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_CRS register
+ */
+/*@{*/
+#define AXBS_RD_CRS(base, index) (AXBS_CRS_REG(base, index))
+#define AXBS_WR_CRS(base, index, value) (AXBS_CRS_REG(base, index) = (value))
+#define AXBS_RMW_CRS(base, index, mask, value) (AXBS_WR_CRS(base, index, (AXBS_RD_CRS(base, index) & ~(mask)) | (value)))
+#define AXBS_SET_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) |  (value)))
+#define AXBS_CLR_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) & ~(value)))
+#define AXBS_TOG_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_CRS bitfields
+ */
+
+/*!
+ * @name Register AXBS_CRS, field PARK[2:0] (RW)
+ *
+ * Determines which master port the current slave port parks on when no masters
+ * are actively making requests and the PCTL bits are cleared. Select only master
+ * ports that are present on the chip. Otherwise, undefined behavior might occur.
+ *
+ * Values:
+ * - 0b000 - Park on master port M0
+ * - 0b001 - Park on master port M1
+ * - 0b010 - Park on master port M2
+ * - 0b011 - Park on master port M3
+ * - 0b100 - Park on master port M4
+ * - 0b101 - Park on master port M5
+ * - 0b110 - Park on master port M6
+ * - 0b111 - Park on master port M7
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_PARK field. */
+#define AXBS_RD_CRS_PARK(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_PARK_MASK) >> AXBS_CRS_PARK_SHIFT)
+#define AXBS_BRD_CRS_PARK(base, index) (AXBS_RD_CRS_PARK(base, index))
+
+/*! @brief Set the PARK field to a new value. */
+#define AXBS_WR_CRS_PARK(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_PARK_MASK, AXBS_CRS_PARK(value)))
+#define AXBS_BWR_CRS_PARK(base, index, value) (AXBS_WR_CRS_PARK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field PCTL[5:4] (RW)
+ *
+ * Determines the slave port's parking control. The low-power park feature
+ * results in an overall power savings if the slave port is not saturated. However,
+ * this forces an extra latency clock when any master tries to access the slave
+ * port while not in use because it is not parked on any master.
+ *
+ * Values:
+ * - 0b00 - When no master makes a request, the arbiter parks the slave port on
+ *     the master port defined by the PARK field
+ * - 0b01 - When no master makes a request, the arbiter parks the slave port on
+ *     the last master to be in control of the slave port
+ * - 0b10 - When no master makes a request, the slave port is not parked on a
+ *     master and the arbiter drives all outputs to a constant safe state
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_PCTL field. */
+#define AXBS_RD_CRS_PCTL(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_PCTL_MASK) >> AXBS_CRS_PCTL_SHIFT)
+#define AXBS_BRD_CRS_PCTL(base, index) (AXBS_RD_CRS_PCTL(base, index))
+
+/*! @brief Set the PCTL field to a new value. */
+#define AXBS_WR_CRS_PCTL(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_PCTL_MASK, AXBS_CRS_PCTL(value)))
+#define AXBS_BWR_CRS_PCTL(base, index, value) (AXBS_WR_CRS_PCTL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field ARB[9:8] (RW)
+ *
+ * Selects the arbitration policy for the slave port.
+ *
+ * Values:
+ * - 0b00 - Fixed priority
+ * - 0b01 - Round-robin, or rotating, priority
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_ARB field. */
+#define AXBS_RD_CRS_ARB(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_ARB_MASK) >> AXBS_CRS_ARB_SHIFT)
+#define AXBS_BRD_CRS_ARB(base, index) (AXBS_RD_CRS_ARB(base, index))
+
+/*! @brief Set the ARB field to a new value. */
+#define AXBS_WR_CRS_ARB(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_ARB_MASK, AXBS_CRS_ARB(value)))
+#define AXBS_BWR_CRS_ARB(base, index, value) (AXBS_WR_CRS_ARB(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field HLP[30] (RW)
+ *
+ * Sets the initial arbitration priority for low power mode requests . Setting
+ * this bit will not affect the request for low power mode from attaining highest
+ * priority once it has control of the slave ports.
+ *
+ * Values:
+ * - 0b0 - The low power mode request has the highest priority for arbitration
+ *     on this slave port
+ * - 0b1 - The low power mode request has the lowest initial priority for
+ *     arbitration on this slave port
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_HLP field. */
+#define AXBS_RD_CRS_HLP(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_HLP_MASK) >> AXBS_CRS_HLP_SHIFT)
+#define AXBS_BRD_CRS_HLP(base, index) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_HLP_SHIFT))
+
+/*! @brief Set the HLP field to a new value. */
+#define AXBS_WR_CRS_HLP(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_HLP_MASK, AXBS_CRS_HLP(value)))
+#define AXBS_BWR_CRS_HLP(base, index, value) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_HLP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field RO[31] (RW)
+ *
+ * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
+ * only a hardware reset clears it.
+ *
+ * Values:
+ * - 0b0 - The slave port's registers are writeable
+ * - 0b1 - The slave port's registers are read-only and cannot be written.
+ *     Attempted writes have no effect on the registers and result in a bus error
+ *     response.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_RO field. */
+#define AXBS_RD_CRS_RO(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_RO_MASK) >> AXBS_CRS_RO_SHIFT)
+#define AXBS_BRD_CRS_RO(base, index) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_RO_SHIFT))
+
+/*! @brief Set the RO field to a new value. */
+#define AXBS_WR_CRS_RO(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_RO_MASK, AXBS_CRS_RO(value)))
+#define AXBS_BWR_CRS_RO(base, index, value) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_RO_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR0 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR0 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR0 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR0(base)     (AXBS_MGPCR0_REG(base))
+#define AXBS_WR_MGPCR0(base, value) (AXBS_MGPCR0_REG(base) = (value))
+#define AXBS_RMW_MGPCR0(base, mask, value) (AXBS_WR_MGPCR0(base, (AXBS_RD_MGPCR0(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) |  (value)))
+#define AXBS_CLR_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) & ~(value)))
+#define AXBS_TOG_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR0 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR0_AULB field. */
+#define AXBS_RD_MGPCR0_AULB(base) ((AXBS_MGPCR0_REG(base) & AXBS_MGPCR0_AULB_MASK) >> AXBS_MGPCR0_AULB_SHIFT)
+#define AXBS_BRD_MGPCR0_AULB(base) (AXBS_RD_MGPCR0_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR0_AULB(base, value) (AXBS_RMW_MGPCR0(base, AXBS_MGPCR0_AULB_MASK, AXBS_MGPCR0_AULB(value)))
+#define AXBS_BWR_MGPCR0_AULB(base, value) (AXBS_WR_MGPCR0_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR1 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR1 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR1 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR1(base)     (AXBS_MGPCR1_REG(base))
+#define AXBS_WR_MGPCR1(base, value) (AXBS_MGPCR1_REG(base) = (value))
+#define AXBS_RMW_MGPCR1(base, mask, value) (AXBS_WR_MGPCR1(base, (AXBS_RD_MGPCR1(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) |  (value)))
+#define AXBS_CLR_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) & ~(value)))
+#define AXBS_TOG_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR1 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR1_AULB field. */
+#define AXBS_RD_MGPCR1_AULB(base) ((AXBS_MGPCR1_REG(base) & AXBS_MGPCR1_AULB_MASK) >> AXBS_MGPCR1_AULB_SHIFT)
+#define AXBS_BRD_MGPCR1_AULB(base) (AXBS_RD_MGPCR1_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR1_AULB(base, value) (AXBS_RMW_MGPCR1(base, AXBS_MGPCR1_AULB_MASK, AXBS_MGPCR1_AULB(value)))
+#define AXBS_BWR_MGPCR1_AULB(base, value) (AXBS_WR_MGPCR1_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR2 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR2 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR2 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR2(base)     (AXBS_MGPCR2_REG(base))
+#define AXBS_WR_MGPCR2(base, value) (AXBS_MGPCR2_REG(base) = (value))
+#define AXBS_RMW_MGPCR2(base, mask, value) (AXBS_WR_MGPCR2(base, (AXBS_RD_MGPCR2(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) |  (value)))
+#define AXBS_CLR_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) & ~(value)))
+#define AXBS_TOG_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR2 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR2_AULB field. */
+#define AXBS_RD_MGPCR2_AULB(base) ((AXBS_MGPCR2_REG(base) & AXBS_MGPCR2_AULB_MASK) >> AXBS_MGPCR2_AULB_SHIFT)
+#define AXBS_BRD_MGPCR2_AULB(base) (AXBS_RD_MGPCR2_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR2_AULB(base, value) (AXBS_RMW_MGPCR2(base, AXBS_MGPCR2_AULB_MASK, AXBS_MGPCR2_AULB(value)))
+#define AXBS_BWR_MGPCR2_AULB(base, value) (AXBS_WR_MGPCR2_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR3 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR3 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR3 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR3(base)     (AXBS_MGPCR3_REG(base))
+#define AXBS_WR_MGPCR3(base, value) (AXBS_MGPCR3_REG(base) = (value))
+#define AXBS_RMW_MGPCR3(base, mask, value) (AXBS_WR_MGPCR3(base, (AXBS_RD_MGPCR3(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) |  (value)))
+#define AXBS_CLR_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) & ~(value)))
+#define AXBS_TOG_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR3 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR3_AULB field. */
+#define AXBS_RD_MGPCR3_AULB(base) ((AXBS_MGPCR3_REG(base) & AXBS_MGPCR3_AULB_MASK) >> AXBS_MGPCR3_AULB_SHIFT)
+#define AXBS_BRD_MGPCR3_AULB(base) (AXBS_RD_MGPCR3_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR3_AULB(base, value) (AXBS_RMW_MGPCR3(base, AXBS_MGPCR3_AULB_MASK, AXBS_MGPCR3_AULB(value)))
+#define AXBS_BWR_MGPCR3_AULB(base, value) (AXBS_WR_MGPCR3_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR4 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR4 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR4 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR4(base)     (AXBS_MGPCR4_REG(base))
+#define AXBS_WR_MGPCR4(base, value) (AXBS_MGPCR4_REG(base) = (value))
+#define AXBS_RMW_MGPCR4(base, mask, value) (AXBS_WR_MGPCR4(base, (AXBS_RD_MGPCR4(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) |  (value)))
+#define AXBS_CLR_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) & ~(value)))
+#define AXBS_TOG_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR4 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR4_AULB field. */
+#define AXBS_RD_MGPCR4_AULB(base) ((AXBS_MGPCR4_REG(base) & AXBS_MGPCR4_AULB_MASK) >> AXBS_MGPCR4_AULB_SHIFT)
+#define AXBS_BRD_MGPCR4_AULB(base) (AXBS_RD_MGPCR4_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR4_AULB(base, value) (AXBS_RMW_MGPCR4(base, AXBS_MGPCR4_AULB_MASK, AXBS_MGPCR4_AULB(value)))
+#define AXBS_BWR_MGPCR4_AULB(base, value) (AXBS_WR_MGPCR4_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR5 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR5 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR5 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR5(base)     (AXBS_MGPCR5_REG(base))
+#define AXBS_WR_MGPCR5(base, value) (AXBS_MGPCR5_REG(base) = (value))
+#define AXBS_RMW_MGPCR5(base, mask, value) (AXBS_WR_MGPCR5(base, (AXBS_RD_MGPCR5(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) |  (value)))
+#define AXBS_CLR_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) & ~(value)))
+#define AXBS_TOG_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR5 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR5_AULB field. */
+#define AXBS_RD_MGPCR5_AULB(base) ((AXBS_MGPCR5_REG(base) & AXBS_MGPCR5_AULB_MASK) >> AXBS_MGPCR5_AULB_SHIFT)
+#define AXBS_BRD_MGPCR5_AULB(base) (AXBS_RD_MGPCR5_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR5_AULB(base, value) (AXBS_RMW_MGPCR5(base, AXBS_MGPCR5_AULB_MASK, AXBS_MGPCR5_AULB(value)))
+#define AXBS_BWR_MGPCR5_AULB(base, value) (AXBS_WR_MGPCR5_AULB(base, value))
+/*@}*/
+
+/*
+ * MK64F12 CAN
+ *
+ * Flex Controller Area Network module
+ *
+ * Registers defined in this header file:
+ * - CAN_MCR - Module Configuration Register
+ * - CAN_CTRL1 - Control 1 register
+ * - CAN_TIMER - Free Running Timer
+ * - CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ * - CAN_RX14MASK - Rx 14 Mask register
+ * - CAN_RX15MASK - Rx 15 Mask register
+ * - CAN_ECR - Error Counter
+ * - CAN_ESR1 - Error and Status 1 register
+ * - CAN_IMASK1 - Interrupt Masks 1 register
+ * - CAN_IFLAG1 - Interrupt Flags 1 register
+ * - CAN_CTRL2 - Control 2 register
+ * - CAN_ESR2 - Error and Status 2 register
+ * - CAN_CRCR - CRC Register
+ * - CAN_RXFGMASK - Rx FIFO Global Mask register
+ * - CAN_RXFIR - Rx FIFO Information Register
+ * - CAN_CS - Message Buffer 0 CS Register
+ * - CAN_ID - Message Buffer 0 ID Register
+ * - CAN_WORD0 - Message Buffer 0 WORD0 Register
+ * - CAN_WORD1 - Message Buffer 0 WORD1 Register
+ * - CAN_RXIMR - Rx Individual Mask Registers
+ */
+
+#define CAN_INSTANCE_COUNT (1U) /*!< Number of instances of the CAN module. */
+#define CAN0_IDX (0U) /*!< Instance number for CAN0. */
+
+/*******************************************************************************
+ * CAN_MCR - Module Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0xD890000FU
+ *
+ * This register defines global system configurations, such as the module
+ * operation modes and the maximum message buffer configuration.
+ */
+/*!
+ * @name Constants and macros for entire CAN_MCR register
+ */
+/*@{*/
+#define CAN_RD_MCR(base)         (CAN_MCR_REG(base))
+#define CAN_WR_MCR(base, value)  (CAN_MCR_REG(base) = (value))
+#define CAN_RMW_MCR(base, mask, value) (CAN_WR_MCR(base, (CAN_RD_MCR(base) & ~(mask)) | (value)))
+#define CAN_SET_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) |  (value)))
+#define CAN_CLR_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) & ~(value)))
+#define CAN_TOG_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_MCR bitfields
+ */
+
+/*!
+ * @name Register CAN_MCR, field MAXMB[6:0] (RW)
+ *
+ * This 7-bit field defines the number of the last Message Buffers that will
+ * take part in the matching and arbitration processes. The reset value (0x0F) is
+ * equivalent to a 16 MB configuration. This field can be written only in Freeze
+ * mode because it is blocked by hardware in other modes. Number of the last MB =
+ * MAXMB MAXMB must be programmed with a value smaller than the parameter
+ * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
+ * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
+ * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
+ * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
+ * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
+ * Matching Timing").
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_MAXMB field. */
+#define CAN_RD_MCR_MAXMB(base) ((CAN_MCR_REG(base) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT)
+#define CAN_BRD_MCR_MAXMB(base) (CAN_RD_MCR_MAXMB(base))
+
+/*! @brief Set the MAXMB field to a new value. */
+#define CAN_WR_MCR_MAXMB(base, value) (CAN_RMW_MCR(base, CAN_MCR_MAXMB_MASK, CAN_MCR_MAXMB(value)))
+#define CAN_BWR_MCR_MAXMB(base, value) (CAN_WR_MCR_MAXMB(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field IDAM[9:8] (RW)
+ *
+ * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
+ * elements. Note that all elements of the table are configured at the same time by this
+ * field (they are all the same format). See Section "Rx FIFO Structure". This
+ * field can be written only in Freeze mode because it is blocked by hardware in
+ * other modes.
+ *
+ * Values:
+ * - 0b00 - Format A: One full ID (standard and extended) per ID Filter Table
+ *     element.
+ * - 0b01 - Format B: Two full standard IDs or two partial 14-bit (standard and
+ *     extended) IDs per ID Filter Table element.
+ * - 0b10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table
+ *     element.
+ * - 0b11 - Format D: All frames rejected.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_IDAM field. */
+#define CAN_RD_MCR_IDAM(base) ((CAN_MCR_REG(base) & CAN_MCR_IDAM_MASK) >> CAN_MCR_IDAM_SHIFT)
+#define CAN_BRD_MCR_IDAM(base) (CAN_RD_MCR_IDAM(base))
+
+/*! @brief Set the IDAM field to a new value. */
+#define CAN_WR_MCR_IDAM(base, value) (CAN_RMW_MCR(base, CAN_MCR_IDAM_MASK, CAN_MCR_IDAM(value)))
+#define CAN_BWR_MCR_IDAM(base, value) (CAN_WR_MCR_IDAM(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field AEN[12] (RW)
+ *
+ * This bit is supplied for backwards compatibility with legacy applications.
+ * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
+ * safe procedure for aborting a pending transmission, so that no frame is sent in
+ * the CAN bus without notification. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
+ * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
+ * used for updating Mailboxes configured for transmission. Writing the Abort code
+ * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Abort disabled.
+ * - 0b1 - Abort enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_AEN field. */
+#define CAN_RD_MCR_AEN(base) ((CAN_MCR_REG(base) & CAN_MCR_AEN_MASK) >> CAN_MCR_AEN_SHIFT)
+#define CAN_BRD_MCR_AEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_AEN_SHIFT))
+
+/*! @brief Set the AEN field to a new value. */
+#define CAN_WR_MCR_AEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_AEN_MASK, CAN_MCR_AEN(value)))
+#define CAN_BWR_MCR_AEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_AEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field LPRIOEN[13] (RW)
+ *
+ * This bit is provided for backwards compatibility with legacy applications. It
+ * controls whether the local priority feature is enabled or not. It is used to
+ * expand the ID used during the arbitration process. With this expanded ID
+ * concept, the arbitration process is done based on the full 32-bit word, but the
+ * actual transmitted ID still has 11-bit for standard frames and 29-bit for
+ * extended frames. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Local Priority disabled.
+ * - 0b1 - Local Priority enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_LPRIOEN field. */
+#define CAN_RD_MCR_LPRIOEN(base) ((CAN_MCR_REG(base) & CAN_MCR_LPRIOEN_MASK) >> CAN_MCR_LPRIOEN_SHIFT)
+#define CAN_BRD_MCR_LPRIOEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPRIOEN_SHIFT))
+
+/*! @brief Set the LPRIOEN field to a new value. */
+#define CAN_WR_MCR_LPRIOEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_LPRIOEN_MASK, CAN_MCR_LPRIOEN(value)))
+#define CAN_BWR_MCR_LPRIOEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPRIOEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field IRMQ[16] (RW)
+ *
+ * This bit indicates whether Rx matching process will be based either on
+ * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
+ * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Individual Rx masking and queue feature are disabled. For backward
+ *     compatibility with legacy applications, the reading of C/S word locks the MB
+ *     even if it is EMPTY.
+ * - 0b1 - Individual Rx masking and queue feature are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_IRMQ field. */
+#define CAN_RD_MCR_IRMQ(base) ((CAN_MCR_REG(base) & CAN_MCR_IRMQ_MASK) >> CAN_MCR_IRMQ_SHIFT)
+#define CAN_BRD_MCR_IRMQ(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_IRMQ_SHIFT))
+
+/*! @brief Set the IRMQ field to a new value. */
+#define CAN_WR_MCR_IRMQ(base, value) (CAN_RMW_MCR(base, CAN_MCR_IRMQ_MASK, CAN_MCR_IRMQ(value)))
+#define CAN_BWR_MCR_IRMQ(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_IRMQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SRXDIS[17] (RW)
+ *
+ * This bit defines whether FlexCAN is allowed to receive frames transmitted by
+ * itself. If this bit is asserted, frames transmitted by the module will not be
+ * stored in any MB, regardless if the MB is programmed with an ID that matches
+ * the transmitted frame, and no interrupt flag or interrupt signal will be
+ * generated due to the frame reception. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Self reception enabled.
+ * - 0b1 - Self reception disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SRXDIS field. */
+#define CAN_RD_MCR_SRXDIS(base) ((CAN_MCR_REG(base) & CAN_MCR_SRXDIS_MASK) >> CAN_MCR_SRXDIS_SHIFT)
+#define CAN_BRD_MCR_SRXDIS(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SRXDIS_SHIFT))
+
+/*! @brief Set the SRXDIS field to a new value. */
+#define CAN_WR_MCR_SRXDIS(base, value) (CAN_RMW_MCR(base, CAN_MCR_SRXDIS_MASK, CAN_MCR_SRXDIS(value)))
+#define CAN_BWR_MCR_SRXDIS(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SRXDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WAKSRC[19] (RW)
+ *
+ * This bit defines whether the integrated low-pass filter is applied to protect
+ * the Rx CAN input from spurious wake up. This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ * - 0b1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WAKSRC field. */
+#define CAN_RD_MCR_WAKSRC(base) ((CAN_MCR_REG(base) & CAN_MCR_WAKSRC_MASK) >> CAN_MCR_WAKSRC_SHIFT)
+#define CAN_BRD_MCR_WAKSRC(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKSRC_SHIFT))
+
+/*! @brief Set the WAKSRC field to a new value. */
+#define CAN_WR_MCR_WAKSRC(base, value) (CAN_RMW_MCR(base, CAN_MCR_WAKSRC_MASK, CAN_MCR_WAKSRC(value)))
+#define CAN_BWR_MCR_WAKSRC(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field LPMACK[20] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
+ * mode , Stop mode ). A low-power mode cannot be entered until all current
+ * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
+ * to know when FlexCAN has actually entered low power mode. LPMACK will be
+ * asserted within 180 CAN bits from the low-power mode request by the CPU, and
+ * negated within 2 CAN bits after the low-power mode request removal (see Section
+ * "Protocol Timing").
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not in a low-power mode.
+ * - 0b1 - FlexCAN is in a low-power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_LPMACK field. */
+#define CAN_RD_MCR_LPMACK(base) ((CAN_MCR_REG(base) & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT)
+#define CAN_BRD_MCR_LPMACK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPMACK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WRNEN[21] (RW)
+ *
+ * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
+ * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
+ * RWRNINT flags will always be zero, independent of the values of the error
+ * counters, and no warning interrupt will ever be generated. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
+ *     error counters.
+ * - 0b1 - TWRNINT and RWRNINT bits are set when the respective error counter
+ *     transitions from less than 96 to greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WRNEN field. */
+#define CAN_RD_MCR_WRNEN(base) ((CAN_MCR_REG(base) & CAN_MCR_WRNEN_MASK) >> CAN_MCR_WRNEN_SHIFT)
+#define CAN_BRD_MCR_WRNEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WRNEN_SHIFT))
+
+/*! @brief Set the WRNEN field to a new value. */
+#define CAN_WR_MCR_WRNEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_WRNEN_MASK, CAN_MCR_WRNEN(value)))
+#define CAN_BWR_MCR_WRNEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WRNEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SLFWAK[22] (RW)
+ *
+ * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
+ * other than Disable mode. When this feature is enabled, the FlexCAN module
+ * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
+ * If a wake up event is detected during Stop mode, then FlexCAN generates, if
+ * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
+ * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
+ * low-power mode other than Disable mode, this bit cannot be written as it is
+ * blocked by hardware.
+ *
+ * Values:
+ * - 0b0 - FlexCAN Self Wake Up feature is disabled.
+ * - 0b1 - FlexCAN Self Wake Up feature is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SLFWAK field. */
+#define CAN_RD_MCR_SLFWAK(base) ((CAN_MCR_REG(base) & CAN_MCR_SLFWAK_MASK) >> CAN_MCR_SLFWAK_SHIFT)
+#define CAN_BRD_MCR_SLFWAK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SLFWAK_SHIFT))
+
+/*! @brief Set the SLFWAK field to a new value. */
+#define CAN_WR_MCR_SLFWAK(base, value) (CAN_RMW_MCR(base, CAN_MCR_SLFWAK_MASK, CAN_MCR_SLFWAK(value)))
+#define CAN_BWR_MCR_SLFWAK(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SLFWAK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SUPV[23] (RW)
+ *
+ * This bit configures the FlexCAN to be either in Supervisor or User mode. The
+ * registers affected by this bit are marked as S/U in the Access Type column of
+ * the module memory map. Reset value of this bit is 1, so the affected registers
+ * start with Supervisor access allowance only . This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
+ *     Unrestricted accesses .
+ * - 0b1 - FlexCAN is in Supervisor mode. Affected registers allow only
+ *     Supervisor access. Unrestricted access behaves as though the access was done to an
+ *     unimplemented register location .
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SUPV field. */
+#define CAN_RD_MCR_SUPV(base) ((CAN_MCR_REG(base) & CAN_MCR_SUPV_MASK) >> CAN_MCR_SUPV_SHIFT)
+#define CAN_BRD_MCR_SUPV(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SUPV_SHIFT))
+
+/*! @brief Set the SUPV field to a new value. */
+#define CAN_WR_MCR_SUPV(base, value) (CAN_RMW_MCR(base, CAN_MCR_SUPV_MASK, CAN_MCR_SUPV(value)))
+#define CAN_BWR_MCR_SUPV(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SUPV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field FRZACK[24] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
+ * is stopped. The Freeze mode request cannot be granted until current
+ * transmission or reception processes have finished. Therefore the software can poll the
+ * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
+ * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
+ * running again. If Freeze mode is requested while FlexCAN is in a low power
+ * mode, then the FRZACK bit will be set only when the low-power mode is exited.
+ * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
+ * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
+ * mode request removal (see Section "Protocol Timing").
+ *
+ * Values:
+ * - 0b0 - FlexCAN not in Freeze mode, prescaler running.
+ * - 0b1 - FlexCAN in Freeze mode, prescaler stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_FRZACK field. */
+#define CAN_RD_MCR_FRZACK(base) ((CAN_MCR_REG(base) & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)
+#define CAN_BRD_MCR_FRZACK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZACK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SOFTRST[25] (RW)
+ *
+ * When this bit is asserted, FlexCAN resets its internal state machines and
+ * some of the memory mapped registers. The following registers are reset: MCR
+ * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
+ * CRCR. Configuration registers that control the interface to the CAN bus are
+ * not affected by soft reset. The following registers are unaffected: CTRL1,
+ * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
+ * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
+ * writes to the MCR Register, but it is also asserted when global soft reset is
+ * requested at MCU level . Because soft reset is synchronous and has to follow a
+ * request/acknowledge procedure across clock domains, it may take some time to
+ * fully propagate its effect. The SOFTRST bit remains asserted while reset is
+ * pending, and is automatically negated when reset completes. Therefore, software can
+ * poll this bit to know when the soft reset has completed. Soft reset cannot be
+ * applied while clocks are shut down in a low power mode. The module should be
+ * first removed from low power mode, and then soft reset can be applied.
+ *
+ * Values:
+ * - 0b0 - No reset request.
+ * - 0b1 - Resets the registers affected by soft reset.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SOFTRST field. */
+#define CAN_RD_MCR_SOFTRST(base) ((CAN_MCR_REG(base) & CAN_MCR_SOFTRST_MASK) >> CAN_MCR_SOFTRST_SHIFT)
+#define CAN_BRD_MCR_SOFTRST(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SOFTRST_SHIFT))
+
+/*! @brief Set the SOFTRST field to a new value. */
+#define CAN_WR_MCR_SOFTRST(base, value) (CAN_RMW_MCR(base, CAN_MCR_SOFTRST_MASK, CAN_MCR_SOFTRST(value)))
+#define CAN_BWR_MCR_SOFTRST(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SOFTRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WAKMSK[26] (RW)
+ *
+ * This bit enables the Wake Up Interrupt generation under Self Wake Up
+ * mechanism.
+ *
+ * Values:
+ * - 0b0 - Wake Up Interrupt is disabled.
+ * - 0b1 - Wake Up Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WAKMSK field. */
+#define CAN_RD_MCR_WAKMSK(base) ((CAN_MCR_REG(base) & CAN_MCR_WAKMSK_MASK) >> CAN_MCR_WAKMSK_SHIFT)
+#define CAN_BRD_MCR_WAKMSK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKMSK_SHIFT))
+
+/*! @brief Set the WAKMSK field to a new value. */
+#define CAN_WR_MCR_WAKMSK(base, value) (CAN_RMW_MCR(base, CAN_MCR_WAKMSK_MASK, CAN_MCR_WAKMSK(value)))
+#define CAN_BWR_MCR_WAKMSK(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field NOTRDY[27] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
+ * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN module is either in Normal mode, Listen-Only mode or
+ *     Loop-Back mode.
+ * - 0b1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_NOTRDY field. */
+#define CAN_RD_MCR_NOTRDY(base) ((CAN_MCR_REG(base) & CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT)
+#define CAN_BRD_MCR_NOTRDY(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_NOTRDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field HALT[28] (RW)
+ *
+ * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
+ * should clear it after initializing the Message Buffers and Control Register. No
+ * reception or transmission is performed by FlexCAN before this bit is cleared.
+ * Freeze mode cannot be entered while FlexCAN is in a low power mode.
+ *
+ * Values:
+ * - 0b0 - No Freeze mode request.
+ * - 0b1 - Enters Freeze mode if the FRZ bit is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_HALT field. */
+#define CAN_RD_MCR_HALT(base) ((CAN_MCR_REG(base) & CAN_MCR_HALT_MASK) >> CAN_MCR_HALT_SHIFT)
+#define CAN_BRD_MCR_HALT(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define CAN_WR_MCR_HALT(base, value) (CAN_RMW_MCR(base, CAN_MCR_HALT_MASK, CAN_MCR_HALT(value)))
+#define CAN_BWR_MCR_HALT(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field RFEN[29] (RW)
+ *
+ * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
+ * set, MBs 0 to 5 cannot be used for normal reception and transmission because
+ * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
+ * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
+ * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
+ * minimum number of peripheral clocks per CAN bit as described in the table
+ * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
+ * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Rx FIFO not enabled.
+ * - 0b1 - Rx FIFO enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_RFEN field. */
+#define CAN_RD_MCR_RFEN(base) ((CAN_MCR_REG(base) & CAN_MCR_RFEN_MASK) >> CAN_MCR_RFEN_SHIFT)
+#define CAN_BRD_MCR_RFEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_RFEN_SHIFT))
+
+/*! @brief Set the RFEN field to a new value. */
+#define CAN_WR_MCR_RFEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_RFEN_MASK, CAN_MCR_RFEN(value)))
+#define CAN_BWR_MCR_RFEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_RFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field FRZ[30] (RW)
+ *
+ * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
+ * Register is set or when Debug mode is requested at MCU level . When FRZ is
+ * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
+ * FlexCAN to exit from Freeze mode.
+ *
+ * Values:
+ * - 0b0 - Not enabled to enter Freeze mode.
+ * - 0b1 - Enabled to enter Freeze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_FRZ field. */
+#define CAN_RD_MCR_FRZ(base) ((CAN_MCR_REG(base) & CAN_MCR_FRZ_MASK) >> CAN_MCR_FRZ_SHIFT)
+#define CAN_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define CAN_WR_MCR_FRZ(base, value) (CAN_RMW_MCR(base, CAN_MCR_FRZ_MASK, CAN_MCR_FRZ(value)))
+#define CAN_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field MDIS[31] (RW)
+ *
+ * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
+ * disables the clocks to the CAN Protocol Engine and Controller Host Interface
+ * sub-modules. This is the only bit within this register not affected by soft
+ * reset.
+ *
+ * Values:
+ * - 0b0 - Enable the FlexCAN module.
+ * - 0b1 - Disable the FlexCAN module.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_MDIS field. */
+#define CAN_RD_MCR_MDIS(base) ((CAN_MCR_REG(base) & CAN_MCR_MDIS_MASK) >> CAN_MCR_MDIS_SHIFT)
+#define CAN_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define CAN_WR_MCR_MDIS(base, value) (CAN_RMW_MCR(base, CAN_MCR_MDIS_MASK, CAN_MCR_MDIS(value)))
+#define CAN_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CTRL1 - Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CTRL1 - Control 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is defined for specific FlexCAN control features related to the
+ * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
+ * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
+ * (Bus-Off, Error, Warning). It also determines the Division Factor for the
+ * clock prescaler.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CTRL1 register
+ */
+/*@{*/
+#define CAN_RD_CTRL1(base)       (CAN_CTRL1_REG(base))
+#define CAN_WR_CTRL1(base, value) (CAN_CTRL1_REG(base) = (value))
+#define CAN_RMW_CTRL1(base, mask, value) (CAN_WR_CTRL1(base, (CAN_RD_CTRL1(base) & ~(mask)) | (value)))
+#define CAN_SET_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) |  (value)))
+#define CAN_CLR_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) & ~(value)))
+#define CAN_TOG_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CTRL1 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
+ *
+ * This 3-bit field defines the length of the Propagation Segment in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Propagation
+ * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PROPSEG field. */
+#define CAN_RD_CTRL1_PROPSEG(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PROPSEG_MASK) >> CAN_CTRL1_PROPSEG_SHIFT)
+#define CAN_BRD_CTRL1_PROPSEG(base) (CAN_RD_CTRL1_PROPSEG(base))
+
+/*! @brief Set the PROPSEG field to a new value. */
+#define CAN_WR_CTRL1_PROPSEG(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PROPSEG_MASK, CAN_CTRL1_PROPSEG(value)))
+#define CAN_BWR_CTRL1_PROPSEG(base, value) (CAN_WR_CTRL1_PROPSEG(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LOM[3] (RW)
+ *
+ * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
+ * transmission is disabled, all error counters are frozen and the module operates
+ * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
+ * will be received. If FlexCAN detects a message that has not been acknowledged,
+ * it will flag a BIT0 error without changing the REC, as if it was trying to
+ * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
+ * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
+ * entered. There can be some delay between the Listen-Only mode request and
+ * acknowledge. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Listen-Only mode is deactivated.
+ * - 0b1 - FlexCAN module operates in Listen-Only mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LOM field. */
+#define CAN_RD_CTRL1_LOM(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LOM_MASK) >> CAN_CTRL1_LOM_SHIFT)
+#define CAN_BRD_CTRL1_LOM(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LOM_SHIFT))
+
+/*! @brief Set the LOM field to a new value. */
+#define CAN_WR_CTRL1_LOM(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LOM_MASK, CAN_CTRL1_LOM(value)))
+#define CAN_BWR_CTRL1_LOM(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LBUF[4] (RW)
+ *
+ * This bit defines the ordering mechanism for Message Buffer transmission. When
+ * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0b0 - Buffer with highest priority is transmitted first.
+ * - 0b1 - Lowest number buffer is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LBUF field. */
+#define CAN_RD_CTRL1_LBUF(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LBUF_MASK) >> CAN_CTRL1_LBUF_SHIFT)
+#define CAN_BRD_CTRL1_LBUF(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LBUF_SHIFT))
+
+/*! @brief Set the LBUF field to a new value. */
+#define CAN_WR_CTRL1_LBUF(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LBUF_MASK, CAN_CTRL1_LBUF(value)))
+#define CAN_BWR_CTRL1_LBUF(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field TSYN[5] (RW)
+ *
+ * This bit enables a mechanism that resets the free-running timer each time a
+ * message is received in Message Buffer 0. This feature provides means to
+ * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
+ * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
+ * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
+ * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Timer Sync feature disabled
+ * - 0b1 - Timer Sync feature enabled
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_TSYN field. */
+#define CAN_RD_CTRL1_TSYN(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_TSYN_MASK) >> CAN_CTRL1_TSYN_SHIFT)
+#define CAN_BRD_CTRL1_TSYN(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TSYN_SHIFT))
+
+/*! @brief Set the TSYN field to a new value. */
+#define CAN_WR_CTRL1_TSYN(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_TSYN_MASK, CAN_CTRL1_TSYN(value)))
+#define CAN_BWR_CTRL1_TSYN(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TSYN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
+ *
+ * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
+ * negated, automatic recovering from Bus Off state occurs according to the CAN
+ * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
+ * disabled and the module remains in Bus Off state until the bit is negated by the
+ * user. If the negation occurs before 128 sequences of 11 recessive bits are
+ * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
+ * never been asserted. If the negation occurs after 128 sequences of 11
+ * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
+ * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
+ * be re-asserted again during Bus Off, but it will be effective only the next
+ * time the module enters Bus Off. If BOFFREC was negated when the module entered
+ * Bus Off, asserting it during Bus Off will not be effective for the current Bus
+ * Off recovery.
+ *
+ * Values:
+ * - 0b0 - Automatic recovering from Bus Off state enabled, according to CAN
+ *     Spec 2.0 part B.
+ * - 0b1 - Automatic recovering from Bus Off state disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_BOFFREC field. */
+#define CAN_RD_CTRL1_BOFFREC(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_BOFFREC_MASK) >> CAN_CTRL1_BOFFREC_SHIFT)
+#define CAN_BRD_CTRL1_BOFFREC(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFREC_SHIFT))
+
+/*! @brief Set the BOFFREC field to a new value. */
+#define CAN_WR_CTRL1_BOFFREC(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_BOFFREC_MASK, CAN_CTRL1_BOFFREC(value)))
+#define CAN_BWR_CTRL1_BOFFREC(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFREC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field SMP[7] (RW)
+ *
+ * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
+ * be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0b0 - Just one sample is used to determine the bit value.
+ * - 0b1 - Three samples are used to determine the value of the received bit:
+ *     the regular one (sample point) and 2 preceding samples; a majority rule is
+ *     used.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_SMP field. */
+#define CAN_RD_CTRL1_SMP(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_SMP_MASK) >> CAN_CTRL1_SMP_SHIFT)
+#define CAN_BRD_CTRL1_SMP(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_SMP_SHIFT))
+
+/*! @brief Set the SMP field to a new value. */
+#define CAN_WR_CTRL1_SMP(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_SMP_MASK, CAN_CTRL1_SMP(value)))
+#define CAN_BWR_CTRL1_SMP(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_SMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
+ *
+ * This bit provides a mask for the Rx Warning Interrupt associated with the
+ * RWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Rx Warning Interrupt disabled.
+ * - 0b1 - Rx Warning Interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_RWRNMSK field. */
+#define CAN_RD_CTRL1_RWRNMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_RWRNMSK_MASK) >> CAN_CTRL1_RWRNMSK_SHIFT)
+#define CAN_BRD_CTRL1_RWRNMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_RWRNMSK_SHIFT))
+
+/*! @brief Set the RWRNMSK field to a new value. */
+#define CAN_WR_CTRL1_RWRNMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_RWRNMSK_MASK, CAN_CTRL1_RWRNMSK(value)))
+#define CAN_BWR_CTRL1_RWRNMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_RWRNMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
+ *
+ * This bit provides a mask for the Tx Warning Interrupt associated with the
+ * TWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Tx Warning Interrupt disabled.
+ * - 0b1 - Tx Warning Interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_TWRNMSK field. */
+#define CAN_RD_CTRL1_TWRNMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_TWRNMSK_MASK) >> CAN_CTRL1_TWRNMSK_SHIFT)
+#define CAN_BRD_CTRL1_TWRNMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TWRNMSK_SHIFT))
+
+/*! @brief Set the TWRNMSK field to a new value. */
+#define CAN_WR_CTRL1_TWRNMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_TWRNMSK_MASK, CAN_CTRL1_TWRNMSK(value)))
+#define CAN_BWR_CTRL1_TWRNMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TWRNMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LPB[12] (RW)
+ *
+ * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
+ * FlexCAN performs an internal loop back that can be used for self test operation.
+ * The bit stream output of the transmitter is fed back internally to the receiver
+ * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
+ * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
+ * and treats its own transmitted message as a message received from a remote
+ * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
+ * frame acknowledge field, generating an internal acknowledge bit to ensure proper
+ * reception of its own message. Both transmit and receive interrupts are
+ * generated. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
+ * this will impede the self reception of a transmitted message.
+ *
+ * Values:
+ * - 0b0 - Loop Back disabled.
+ * - 0b1 - Loop Back enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LPB field. */
+#define CAN_RD_CTRL1_LPB(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LPB_MASK) >> CAN_CTRL1_LPB_SHIFT)
+#define CAN_BRD_CTRL1_LPB(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LPB_SHIFT))
+
+/*! @brief Set the LPB field to a new value. */
+#define CAN_WR_CTRL1_LPB(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LPB_MASK, CAN_CTRL1_LPB(value)))
+#define CAN_BWR_CTRL1_LPB(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LPB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
+ *
+ * This bit selects the clock source to the CAN Protocol Engine (PE) to be
+ * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
+ * The selected clock is the one fed to the prescaler to generate the Serial Clock
+ * (Sclock). In order to guarantee reliable operation, this bit can be written
+ * only in Disable mode because it is blocked by hardware in other modes. See
+ * Section "Protocol Timing".
+ *
+ * Values:
+ * - 0b0 - The CAN engine clock source is the oscillator clock. Under this
+ *     condition, the oscillator clock frequency must be lower than the bus clock.
+ * - 0b1 - The CAN engine clock source is the peripheral clock.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_CLKSRC field. */
+#define CAN_RD_CTRL1_CLKSRC(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_CLKSRC_MASK) >> CAN_CTRL1_CLKSRC_SHIFT)
+#define CAN_BRD_CTRL1_CLKSRC(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_CLKSRC_SHIFT))
+
+/*! @brief Set the CLKSRC field to a new value. */
+#define CAN_WR_CTRL1_CLKSRC(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_CLKSRC_MASK, CAN_CTRL1_CLKSRC(value)))
+#define CAN_BWR_CTRL1_CLKSRC(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_CLKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
+ *
+ * This bit provides a mask for the Error Interrupt.
+ *
+ * Values:
+ * - 0b0 - Error interrupt disabled.
+ * - 0b1 - Error interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_ERRMSK field. */
+#define CAN_RD_CTRL1_ERRMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_ERRMSK_MASK) >> CAN_CTRL1_ERRMSK_SHIFT)
+#define CAN_BRD_CTRL1_ERRMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_ERRMSK_SHIFT))
+
+/*! @brief Set the ERRMSK field to a new value. */
+#define CAN_WR_CTRL1_ERRMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_ERRMSK_MASK, CAN_CTRL1_ERRMSK(value)))
+#define CAN_BWR_CTRL1_ERRMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_ERRMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
+ *
+ * This bit provides a mask for the Bus Off Interrupt.
+ *
+ * Values:
+ * - 0b0 - Bus Off interrupt disabled.
+ * - 0b1 - Bus Off interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_BOFFMSK field. */
+#define CAN_RD_CTRL1_BOFFMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_BOFFMSK_MASK) >> CAN_CTRL1_BOFFMSK_SHIFT)
+#define CAN_BRD_CTRL1_BOFFMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFMSK_SHIFT))
+
+/*! @brief Set the BOFFMSK field to a new value. */
+#define CAN_WR_CTRL1_BOFFMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_BOFFMSK_MASK, CAN_CTRL1_BOFFMSK(value)))
+#define CAN_BWR_CTRL1_BOFFMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
+ * time. The valid programmable values are 1-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 2 = (PSEG2 + 1) * Time-Quanta.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PSEG2 field. */
+#define CAN_RD_CTRL1_PSEG2(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PSEG2_MASK) >> CAN_CTRL1_PSEG2_SHIFT)
+#define CAN_BRD_CTRL1_PSEG2(base) (CAN_RD_CTRL1_PSEG2(base))
+
+/*! @brief Set the PSEG2 field to a new value. */
+#define CAN_WR_CTRL1_PSEG2(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PSEG2_MASK, CAN_CTRL1_PSEG2(value)))
+#define CAN_BWR_CTRL1_PSEG2(base, value) (CAN_WR_CTRL1_PSEG2(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 1 = (PSEG1 + 1) * Time-Quanta.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PSEG1 field. */
+#define CAN_RD_CTRL1_PSEG1(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PSEG1_MASK) >> CAN_CTRL1_PSEG1_SHIFT)
+#define CAN_BRD_CTRL1_PSEG1(base) (CAN_RD_CTRL1_PSEG1(base))
+
+/*! @brief Set the PSEG1 field to a new value. */
+#define CAN_WR_CTRL1_PSEG1(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PSEG1_MASK, CAN_CTRL1_PSEG1(value)))
+#define CAN_BWR_CTRL1_PSEG1(base, value) (CAN_WR_CTRL1_PSEG1(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field RJW[23:22] (RW)
+ *
+ * This 2-bit field defines the maximum number of time quanta that a bit time
+ * can be changed by one re-synchronization. One time quantum is equal to the
+ * Sclock period. The valid programmable values are 0-3. This field can be written
+ * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
+ * Width = RJW + 1.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_RJW field. */
+#define CAN_RD_CTRL1_RJW(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_RJW_MASK) >> CAN_CTRL1_RJW_SHIFT)
+#define CAN_BRD_CTRL1_RJW(base) (CAN_RD_CTRL1_RJW(base))
+
+/*! @brief Set the RJW field to a new value. */
+#define CAN_WR_CTRL1_RJW(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_RJW_MASK, CAN_CTRL1_RJW(value)))
+#define CAN_BWR_CTRL1_RJW(base, value) (CAN_WR_CTRL1_RJW(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
+ *
+ * This 8-bit field defines the ratio between the PE clock frequency and the
+ * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
+ * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
+ * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
+ * Sclock frequency equal to the PE clock frequency divided by 256. See Section
+ * "Protocol Timing". This field can be written only in Freeze mode because it is
+ * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
+ * (PRESDIV + 1)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PRESDIV field. */
+#define CAN_RD_CTRL1_PRESDIV(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PRESDIV_MASK) >> CAN_CTRL1_PRESDIV_SHIFT)
+#define CAN_BRD_CTRL1_PRESDIV(base) (CAN_RD_CTRL1_PRESDIV(base))
+
+/*! @brief Set the PRESDIV field to a new value. */
+#define CAN_WR_CTRL1_PRESDIV(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PRESDIV_MASK, CAN_CTRL1_PRESDIV(value)))
+#define CAN_BWR_CTRL1_PRESDIV(base, value) (CAN_WR_CTRL1_PRESDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_TIMER - Free Running Timer
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_TIMER - Free Running Timer (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register represents a 16-bit free running counter that can be read and
+ * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
+ * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
+ * defines the baud rate on the CAN bus. During a message transmission/reception,
+ * it increments by one for each bit that is received or transmitted. When there
+ * is no message on the bus, it counts using the previously programmed baud
+ * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
+ * timer value is captured when the second bit of the identifier field of any frame
+ * is on the CAN bus. This captured value is written into the Time Stamp entry
+ * in a message buffer after a successful reception or transmission of a message.
+ * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
+ * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
+ * can write to this register anytime. However, if the write occurs at the same
+ * time that the Timer is being reset by a reception in the first Mailbox, then
+ * the write value is discarded. Reading this register affects the Mailbox
+ * Unlocking procedure; see Section "Mailbox Lock Mechanism".
+ */
+/*!
+ * @name Constants and macros for entire CAN_TIMER register
+ */
+/*@{*/
+#define CAN_RD_TIMER(base)       (CAN_TIMER_REG(base))
+#define CAN_WR_TIMER(base, value) (CAN_TIMER_REG(base) = (value))
+#define CAN_RMW_TIMER(base, mask, value) (CAN_WR_TIMER(base, (CAN_RD_TIMER(base) & ~(mask)) | (value)))
+#define CAN_SET_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) |  (value)))
+#define CAN_CLR_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) & ~(value)))
+#define CAN_TOG_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_TIMER bitfields
+ */
+
+/*!
+ * @name Register CAN_TIMER, field TIMER[15:0] (RW)
+ *
+ * Contains the free-running counter value.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_TIMER_TIMER field. */
+#define CAN_RD_TIMER_TIMER(base) ((CAN_TIMER_REG(base) & CAN_TIMER_TIMER_MASK) >> CAN_TIMER_TIMER_SHIFT)
+#define CAN_BRD_TIMER_TIMER(base) (CAN_RD_TIMER_TIMER(base))
+
+/*! @brief Set the TIMER field to a new value. */
+#define CAN_WR_TIMER_TIMER(base, value) (CAN_RMW_TIMER(base, CAN_TIMER_TIMER_MASK, CAN_TIMER_TIMER(value)))
+#define CAN_BWR_TIMER_TIMER(base, value) (CAN_WR_TIMER_TIMER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RXMGMASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
+ * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
+ * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
+ * mask registers. This register can only be written in Freeze mode as it is
+ * blocked by hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXMGMASK register
+ */
+/*@{*/
+#define CAN_RD_RXMGMASK(base)    (CAN_RXMGMASK_REG(base))
+#define CAN_WR_RXMGMASK(base, value) (CAN_RXMGMASK_REG(base) = (value))
+#define CAN_RMW_RXMGMASK(base, mask, value) (CAN_WR_RXMGMASK(base, (CAN_RD_RXMGMASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) |  (value)))
+#define CAN_CLR_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) & ~(value)))
+#define CAN_TOG_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RX14MASK - Rx 14 Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RX14MASK - Rx 14 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX14MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
+ * is used to mask the filter fields of Message Buffer 14. This register can only
+ * be programmed while the module is in Freeze mode as it is blocked by hardware
+ * in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RX14MASK register
+ */
+/*@{*/
+#define CAN_RD_RX14MASK(base)    (CAN_RX14MASK_REG(base))
+#define CAN_WR_RX14MASK(base, value) (CAN_RX14MASK_REG(base) = (value))
+#define CAN_RMW_RX14MASK(base, mask, value) (CAN_WR_RX14MASK(base, (CAN_RD_RX14MASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) |  (value)))
+#define CAN_CLR_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) & ~(value)))
+#define CAN_TOG_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RX15MASK - Rx 15 Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RX15MASK - Rx 15 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX15MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
+ * is used to mask the filter fields of Message Buffer 15. This register can be
+ * programmed only while the module is in Freeze mode because it is blocked by
+ * hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RX15MASK register
+ */
+/*@{*/
+#define CAN_RD_RX15MASK(base)    (CAN_RX15MASK_REG(base))
+#define CAN_WR_RX15MASK(base, value) (CAN_RX15MASK_REG(base) = (value))
+#define CAN_RMW_RX15MASK(base, mask, value) (CAN_WR_RX15MASK(base, (CAN_RD_RX15MASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) |  (value)))
+#define CAN_CLR_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) & ~(value)))
+#define CAN_TOG_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ECR - Error Counter
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ECR - Error Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has two 8-bit fields reflecting the value of two FlexCAN error
+ * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
+ * (RXERRCNT field). The rules for increasing and decreasing these counters are
+ * described in the CAN protocol and are completely implemented in the FlexCAN
+ * module. Both counters are read-only except in Freeze mode, where they can be
+ * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
+ * for example, transmit Error Active or Error Passive flag, delay its
+ * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
+ * Off state. The following are the basic rules for FlexCAN bus state transitions:
+ * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
+ * 128, the FLTCONF field in the Error and Status Register is updated to reflect
+ * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
+ * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
+ * other already satisfies this condition, the FLTCONF field in the Error and
+ * Status Register is updated to reflect 'Error Active' state. If the value of
+ * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
+ * Register is updated to reflect 'Bus Off' state, and an interrupt may be
+ * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
+ * state, then TXERRCNT is cascaded together with another internal counter to count
+ * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
+ * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
+ * 11 such bits and then wraps around while incrementing the TXERRCNT. When
+ * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
+ * Register is updated to be 'Error Active' and both error counters are reset to zero.
+ * At any instance of dominant bit following a stream of less than 11
+ * consecutive recessive bits, the internal counter resets itself to zero without affecting
+ * the TXERRCNT value. If during system start-up, only one node is operating,
+ * then its TXERRCNT increases in each message it is trying to transmit, as a
+ * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
+ * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
+ * increment anymore by acknowledge errors. Therefore the device never goes to
+ * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
+ * is not incremented further, even if more errors are detected while being a
+ * receiver. At the next successful message reception, the counter is set to a value
+ * between 119 and 127 to resume to 'Error Active' state.
+ */
+/*!
+ * @name Constants and macros for entire CAN_ECR register
+ */
+/*@{*/
+#define CAN_RD_ECR(base)         (CAN_ECR_REG(base))
+#define CAN_WR_ECR(base, value)  (CAN_ECR_REG(base) = (value))
+#define CAN_RMW_ECR(base, mask, value) (CAN_WR_ECR(base, (CAN_RD_ECR(base) & ~(mask)) | (value)))
+#define CAN_SET_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) |  (value)))
+#define CAN_CLR_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) & ~(value)))
+#define CAN_TOG_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ECR bitfields
+ */
+
+/*!
+ * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ECR_TXERRCNT field. */
+#define CAN_RD_ECR_TXERRCNT(base) ((CAN_ECR_REG(base) & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT)
+#define CAN_BRD_ECR_TXERRCNT(base) (CAN_RD_ECR_TXERRCNT(base))
+
+/*! @brief Set the TXERRCNT field to a new value. */
+#define CAN_WR_ECR_TXERRCNT(base, value) (CAN_RMW_ECR(base, CAN_ECR_TXERRCNT_MASK, CAN_ECR_TXERRCNT(value)))
+#define CAN_BWR_ECR_TXERRCNT(base, value) (CAN_WR_ECR_TXERRCNT(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ECR_RXERRCNT field. */
+#define CAN_RD_ECR_RXERRCNT(base) ((CAN_ECR_REG(base) & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT)
+#define CAN_BRD_ECR_RXERRCNT(base) (CAN_RD_ECR_RXERRCNT(base))
+
+/*! @brief Set the RXERRCNT field to a new value. */
+#define CAN_WR_ECR_RXERRCNT(base, value) (CAN_RMW_ECR(base, CAN_ECR_RXERRCNT_MASK, CAN_ECR_RXERRCNT(value)))
+#define CAN_BWR_ECR_RXERRCNT(base, value) (CAN_WR_ECR_RXERRCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ESR1 - Error and Status 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ESR1 - Error and Status 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various error conditions, some general status of the
+ * device and it is the source of interrupts to the CPU. The CPU read action
+ * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
+ * that occurred since the last time the CPU read this register. Bits 9-3 are
+ * status bits. The following table shows the FlexCAN state variables and their
+ * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
+ * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
+ * Transmitting 1 0 0 1 Receiving
+ */
+/*!
+ * @name Constants and macros for entire CAN_ESR1 register
+ */
+/*@{*/
+#define CAN_RD_ESR1(base)        (CAN_ESR1_REG(base))
+#define CAN_WR_ESR1(base, value) (CAN_ESR1_REG(base) = (value))
+#define CAN_RMW_ESR1(base, mask, value) (CAN_WR_ESR1(base, (CAN_RD_ESR1(base) & ~(mask)) | (value)))
+#define CAN_SET_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) |  (value)))
+#define CAN_CLR_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) & ~(value)))
+#define CAN_TOG_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ESR1 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR1, field WAKINT[0] (W1C)
+ *
+ * This field applies when FlexCAN is in low-power mode under Self Wake Up
+ * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
+ * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
+ * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
+ * is masked. The CPU must clear this flag before disabling the bit. Otherwise
+ * it will be set when the SLFWAK is set again. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - Indicates a recessive to dominant transition was received on the CAN
+ *     bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_WAKINT field. */
+#define CAN_RD_ESR1_WAKINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_WAKINT_MASK) >> CAN_ESR1_WAKINT_SHIFT)
+#define CAN_BRD_ESR1_WAKINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_WAKINT_SHIFT))
+
+/*! @brief Set the WAKINT field to a new value. */
+#define CAN_WR_ESR1_WAKINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_WAKINT(value)))
+#define CAN_BWR_ESR1_WAKINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_WAKINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field ERRINT[1] (W1C)
+ *
+ * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
+ * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
+ * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - Indicates setting of any Error Bit in the Error and Status Register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_ERRINT field. */
+#define CAN_RD_ESR1_ERRINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_ERRINT_MASK) >> CAN_ESR1_ERRINT_SHIFT)
+#define CAN_BRD_ESR1_ERRINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ERRINT_SHIFT))
+
+/*! @brief Set the ERRINT field to a new value. */
+#define CAN_WR_ESR1_ERRINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_ERRINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_ERRINT(value)))
+#define CAN_BWR_ESR1_ERRINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ERRINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
+ *
+ * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
+ * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
+ * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - FlexCAN module entered Bus Off state.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BOFFINT field. */
+#define CAN_RD_ESR1_BOFFINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BOFFINT_MASK) >> CAN_ESR1_BOFFINT_SHIFT)
+#define CAN_BRD_ESR1_BOFFINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BOFFINT_SHIFT))
+
+/*! @brief Set the BOFFINT field to a new value. */
+#define CAN_WR_ESR1_BOFFINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_BOFFINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_BOFFINT(value)))
+#define CAN_BWR_ESR1_BOFFINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BOFFINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RX[3] (RO)
+ *
+ * This bit indicates if FlexCAN is receiving a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not receiving a message.
+ * - 0b1 - FlexCAN is receiving a message.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RX field. */
+#define CAN_RD_ESR1_RX(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RX_MASK) >> CAN_ESR1_RX_SHIFT)
+#define CAN_BRD_ESR1_RX(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
+ *
+ * This 2-bit field indicates the Confinement State of the FlexCAN module. If
+ * the LOM bit in the Control Register is asserted, after some delay that depends
+ * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
+ * same delay affects the way how FLTCONF reflects an update to ECR register by
+ * the CPU. It may be necessary up to one CAN bit time to get them coherent
+ * again. Because the Control Register is not affected by soft reset, the FLTCONF
+ * field will not be affected by soft reset if the LOM bit is asserted.
+ *
+ * Values:
+ * - 0b00 - Error Active
+ * - 0b01 - Error Passive
+ * - 0b1x - Bus Off
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_FLTCONF field. */
+#define CAN_RD_ESR1_FLTCONF(base) ((CAN_ESR1_REG(base) & CAN_ESR1_FLTCONF_MASK) >> CAN_ESR1_FLTCONF_SHIFT)
+#define CAN_BRD_ESR1_FLTCONF(base) (CAN_RD_ESR1_FLTCONF(base))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TX[6] (RO)
+ *
+ * This bit indicates if FlexCAN is transmitting a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not transmitting a message.
+ * - 0b1 - FlexCAN is transmitting a message.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TX field. */
+#define CAN_RD_ESR1_TX(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TX_MASK) >> CAN_ESR1_TX_SHIFT)
+#define CAN_BRD_ESR1_TX(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field IDLE[7] (RO)
+ *
+ * This bit indicates when CAN bus is in IDLE state. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - CAN bus is now IDLE.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_IDLE field. */
+#define CAN_RD_ESR1_IDLE(base) ((CAN_ESR1_REG(base) & CAN_ESR1_IDLE_MASK) >> CAN_ESR1_IDLE_SHIFT)
+#define CAN_BRD_ESR1_IDLE(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RXWRN[8] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * reception. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - RXERRCNT is greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RXWRN field. */
+#define CAN_RD_ESR1_RXWRN(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RXWRN_MASK) >> CAN_ESR1_RXWRN_SHIFT)
+#define CAN_BRD_ESR1_RXWRN(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RXWRN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TXWRN[9] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * transmission. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - TXERRCNT is greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TXWRN field. */
+#define CAN_RD_ESR1_TXWRN(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TXWRN_MASK) >> CAN_ESR1_TXWRN_SHIFT)
+#define CAN_BRD_ESR1_TXWRN(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TXWRN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field STFERR[10] (RO)
+ *
+ * This bit indicates that a Stuffing Error has been etected.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A Stuffing Error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_STFERR field. */
+#define CAN_RD_ESR1_STFERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_STFERR_MASK) >> CAN_ESR1_STFERR_SHIFT)
+#define CAN_BRD_ESR1_STFERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_STFERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field FRMERR[11] (RO)
+ *
+ * This bit indicates that a Form Error has been detected by the receiver node,
+ * that is, a fixed-form bit field contains at least one illegal bit.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A Form Error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_FRMERR field. */
+#define CAN_RD_ESR1_FRMERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_FRMERR_MASK) >> CAN_ESR1_FRMERR_SHIFT)
+#define CAN_BRD_ESR1_FRMERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_FRMERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field CRCERR[12] (RO)
+ *
+ * This bit indicates that a CRC Error has been detected by the receiver node,
+ * that is, the calculated CRC is different from the received.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A CRC error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_CRCERR field. */
+#define CAN_RD_ESR1_CRCERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_CRCERR_MASK) >> CAN_ESR1_CRCERR_SHIFT)
+#define CAN_BRD_ESR1_CRCERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_CRCERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field ACKERR[13] (RO)
+ *
+ * This bit indicates that an Acknowledge Error has been detected by the
+ * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - An ACK error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_ACKERR field. */
+#define CAN_RD_ESR1_ACKERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_ACKERR_MASK) >> CAN_ESR1_ACKERR_SHIFT)
+#define CAN_BRD_ESR1_ACKERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ACKERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - At least one bit sent as dominant is received as recessive.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BIT0ERR field. */
+#define CAN_RD_ESR1_BIT0ERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BIT0ERR_MASK) >> CAN_ESR1_BIT0ERR_SHIFT)
+#define CAN_BRD_ESR1_BIT0ERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BIT0ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message. This bit is not set by a transmitter in case of
+ * arbitration field or ACK slot, or in case of a node sending a passive error
+ * flag that detects dominant bits.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - At least one bit sent as recessive is received as dominant.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BIT1ERR field. */
+#define CAN_RD_ESR1_BIT1ERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BIT1ERR_MASK) >> CAN_ESR1_BIT1ERR_SHIFT)
+#define CAN_BRD_ESR1_BIT1ERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BIT1ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
+ * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
+ * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
+ * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - The Rx error counter transitioned from less than 96 to greater than
+ *     or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RWRNINT field. */
+#define CAN_RD_ESR1_RWRNINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RWRNINT_MASK) >> CAN_ESR1_RWRNINT_SHIFT)
+#define CAN_BRD_ESR1_RWRNINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RWRNINT_SHIFT))
+
+/*! @brief Set the RWRNINT field to a new value. */
+#define CAN_WR_ESR1_RWRNINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_RWRNINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_RWRNINT(value)))
+#define CAN_BWR_ESR1_RWRNINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RWRNINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
+ * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
+ * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
+ * is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This flag is not generated during Bus Off state. This bit is not
+ * updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - The Tx error counter transitioned from less than 96 to greater than
+ *     or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TWRNINT field. */
+#define CAN_RD_ESR1_TWRNINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TWRNINT_MASK) >> CAN_ESR1_TWRNINT_SHIFT)
+#define CAN_BRD_ESR1_TWRNINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TWRNINT_SHIFT))
+
+/*! @brief Set the TWRNINT field to a new value. */
+#define CAN_WR_ESR1_TWRNINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_TWRNINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK), CAN_ESR1_TWRNINT(value)))
+#define CAN_BWR_ESR1_TWRNINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TWRNINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field SYNCH[18] (RO)
+ *
+ * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
+ * bus and able to participate in the communication process. It is set and
+ * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not synchronized to the CAN bus.
+ * - 0b1 - FlexCAN is synchronized to the CAN bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_SYNCH field. */
+#define CAN_RD_ESR1_SYNCH(base) ((CAN_ESR1_REG(base) & CAN_ESR1_SYNCH_MASK) >> CAN_ESR1_SYNCH_SHIFT)
+#define CAN_BRD_ESR1_SYNCH(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_SYNCH_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_IMASK1 - Interrupt Masks 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_IMASK1 - Interrupt Masks 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register allows any number of a range of the 32 Message Buffer
+ * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
+ * bit per buffer, enabling the CPU to determine which buffer generates an
+ * interrupt after a successful transmission or reception, that is, when the
+ * corresponding IFLAG1 bit is set.
+ */
+/*!
+ * @name Constants and macros for entire CAN_IMASK1 register
+ */
+/*@{*/
+#define CAN_RD_IMASK1(base)      (CAN_IMASK1_REG(base))
+#define CAN_WR_IMASK1(base, value) (CAN_IMASK1_REG(base) = (value))
+#define CAN_RMW_IMASK1(base, mask, value) (CAN_WR_IMASK1(base, (CAN_RD_IMASK1(base) & ~(mask)) | (value)))
+#define CAN_SET_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) |  (value)))
+#define CAN_CLR_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) & ~(value)))
+#define CAN_TOG_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_IFLAG1 - Interrupt Flags 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the flags for the 32 Message Buffer interrupts for MB31
+ * to MB0. It contains one interrupt flag bit per buffer. Each successful
+ * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
+ * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
+ * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
+ * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
+ * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
+ * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
+ * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
+ * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
+ * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
+ * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
+ * the FIFO flags must be cleared. The same care must be taken when an RFFN
+ * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
+ * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
+ * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
+ * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
+ * they will remain set and be inconsistent with the number of MBs available.
+ */
+/*!
+ * @name Constants and macros for entire CAN_IFLAG1 register
+ */
+/*@{*/
+#define CAN_RD_IFLAG1(base)      (CAN_IFLAG1_REG(base))
+#define CAN_WR_IFLAG1(base, value) (CAN_IFLAG1_REG(base) = (value))
+#define CAN_RMW_IFLAG1(base, mask, value) (CAN_WR_IFLAG1(base, (CAN_RD_IFLAG1(base) & ~(mask)) | (value)))
+#define CAN_SET_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) |  (value)))
+#define CAN_CLR_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) & ~(value)))
+#define CAN_TOG_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_IFLAG1 bitfields
+ */
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
+ * set.
+ *
+ * Values:
+ * - 0b0 - The corresponding buffer has no occurrence of successfully completed
+ *     transmission or reception when MCR[RFEN]=0.
+ * - 0b1 - The corresponding buffer has successfully completed transmission or
+ *     reception when MCR[RFEN]=0.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF0I field. */
+#define CAN_RD_IFLAG1_BUF0I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF0I_MASK) >> CAN_IFLAG1_BUF0I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF0I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF0I_SHIFT))
+
+/*! @brief Set the BUF0I field to a new value. */
+#define CAN_WR_IFLAG1_BUF0I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF0I(value)))
+#define CAN_BWR_IFLAG1_BUF0I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF0I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
+ * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
+ * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
+ * when MCR[RFEN] is set.
+ *
+ * Values:
+ * - 0b0000 - The corresponding buffer has no occurrence of successfully
+ *     completed transmission or reception when MCR[RFEN]=0.
+ * - 0b0001 - The corresponding buffer has successfully completed transmission
+ *     or reception when MCR[RFEN]=0.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field. */
+#define CAN_RD_IFLAG1_BUF4TO1I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF4TO1I_MASK) >> CAN_IFLAG1_BUF4TO1I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF4TO1I(base) (CAN_RD_IFLAG1_BUF4TO1I(base))
+
+/*! @brief Set the BUF4TO1I field to a new value. */
+#define CAN_WR_IFLAG1_BUF4TO1I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF4TO1I(value)))
+#define CAN_BWR_IFLAG1_BUF4TO1I(base, value) (CAN_WR_IFLAG1_BUF4TO1I(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
+ * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
+ * least one frame is available to be read from the Rx FIFO.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB5 completing transmission/reception when
+ *     MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
+ * - 0b1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
+ *     available in the Rx FIFO when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF5I field. */
+#define CAN_RD_IFLAG1_BUF5I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF5I_MASK) >> CAN_IFLAG1_BUF5I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF5I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF5I_SHIFT))
+
+/*! @brief Set the BUF5I field to a new value. */
+#define CAN_WR_IFLAG1_BUF5I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF5I(value)))
+#define CAN_BWR_IFLAG1_BUF5I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF5I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
+ * when MCR[RFEN] is set. In this case, the flag indicates when the number of
+ * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
+ * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
+ * cleared while the number of unread messages is greater than 4, it does not
+ * assert again until the number of unread messages within the Rx FIFO is decreased
+ * to be equal to or less than 4.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB6 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
+ * - 0b1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     almost full when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF6I field. */
+#define CAN_RD_IFLAG1_BUF6I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF6I_MASK) >> CAN_IFLAG1_BUF6I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF6I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF6I_SHIFT))
+
+/*! @brief Set the BUF6I field to a new value. */
+#define CAN_WR_IFLAG1_BUF6I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF6I(value)))
+#define CAN_BWR_IFLAG1_BUF6I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF6I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
+ * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
+ * because the Rx FIFO is full. Note that the flag will not be asserted when the
+ * Rx FIFO is full and the message was captured by a Mailbox.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB7 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
+ * - 0b1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     overflow when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF7I field. */
+#define CAN_RD_IFLAG1_BUF7I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF7I_MASK) >> CAN_IFLAG1_BUF7I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF7I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF7I_SHIFT))
+
+/*! @brief Set the BUF7I field to a new value. */
+#define CAN_WR_IFLAG1_BUF7I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF7I(value)))
+#define CAN_BWR_IFLAG1_BUF7I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF7I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
+ *
+ * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
+ * MB8.
+ *
+ * Values:
+ * - 0b000000000000000000000000 - The corresponding buffer has no occurrence of
+ *     successfully completed transmission or reception.
+ * - 0b000000000000000000000001 - The corresponding buffer has successfully
+ *     completed transmission or reception.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field. */
+#define CAN_RD_IFLAG1_BUF31TO8I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF31TO8I_MASK) >> CAN_IFLAG1_BUF31TO8I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF31TO8I(base) (CAN_RD_IFLAG1_BUF31TO8I(base))
+
+/*! @brief Set the BUF31TO8I field to a new value. */
+#define CAN_WR_IFLAG1_BUF31TO8I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF31TO8I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK), CAN_IFLAG1_BUF31TO8I(value)))
+#define CAN_BWR_IFLAG1_BUF31TO8I(base, value) (CAN_WR_IFLAG1_BUF31TO8I(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CTRL2 - Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CTRL2 - Control 2 register (RW)
+ *
+ * Reset value: 0x00B00000U
+ *
+ * This register contains control bits for CAN errors, FIFO features, and mode
+ * selection.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CTRL2 register
+ */
+/*@{*/
+#define CAN_RD_CTRL2(base)       (CAN_CTRL2_REG(base))
+#define CAN_WR_CTRL2(base, value) (CAN_CTRL2_REG(base) = (value))
+#define CAN_RMW_CTRL2(base, mask, value) (CAN_WR_CTRL2(base, (CAN_RD_CTRL2(base) & ~(mask)) | (value)))
+#define CAN_SET_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) |  (value)))
+#define CAN_CLR_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) & ~(value)))
+#define CAN_TOG_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CTRL2 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL2, field EACEN[16] (RW)
+ *
+ * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
+ * filters with their corresponding bits in the incoming frame by the matching
+ * process. This bit does not affect matching for Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
+ *     compared despite mask bits.
+ * - 0b1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit
+ *     with their corresponding bits within the incoming frame. Mask bits do apply.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_EACEN field. */
+#define CAN_RD_CTRL2_EACEN(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_EACEN_MASK) >> CAN_CTRL2_EACEN_SHIFT)
+#define CAN_BRD_CTRL2_EACEN(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_EACEN_SHIFT))
+
+/*! @brief Set the EACEN field to a new value. */
+#define CAN_WR_CTRL2_EACEN(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_EACEN_MASK, CAN_CTRL2_EACEN(value)))
+#define CAN_BWR_CTRL2_EACEN(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_EACEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field RRS[17] (RW)
+ *
+ * If this bit is asserted Remote Request Frame is submitted to a matching
+ * process and stored in the corresponding Message Buffer in the same fashion of a
+ * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
+ * negated the Remote Request Frame is submitted to a matching process and an
+ * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
+ * is found with the same ID. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Remote Response Frame is generated.
+ * - 0b1 - Remote Request Frame is stored.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_RRS field. */
+#define CAN_RD_CTRL2_RRS(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_RRS_MASK) >> CAN_CTRL2_RRS_SHIFT)
+#define CAN_BRD_CTRL2_RRS(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_RRS_SHIFT))
+
+/*! @brief Set the RRS field to a new value. */
+#define CAN_WR_CTRL2_RRS(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_RRS_MASK, CAN_CTRL2_RRS(value)))
+#define CAN_BWR_CTRL2_RRS(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_RRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field MRP[18] (RW)
+ *
+ * If this bit is set the matching process starts from the Mailboxes and if no
+ * match occurs the matching continues on the Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Matching starts from Rx FIFO and continues on Mailboxes.
+ * - 0b1 - Matching starts from Mailboxes and continues on Rx FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_MRP field. */
+#define CAN_RD_CTRL2_MRP(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_MRP_MASK) >> CAN_CTRL2_MRP_SHIFT)
+#define CAN_BRD_CTRL2_MRP(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_MRP_SHIFT))
+
+/*! @brief Set the MRP field to a new value. */
+#define CAN_WR_CTRL2_MRP(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_MRP_MASK, CAN_CTRL2_MRP(value)))
+#define CAN_BWR_CTRL2_MRP(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_MRP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field TASD[23:19] (RW)
+ *
+ * This 5-bit field indicates how many CAN bits the Tx arbitration process start
+ * point can be delayed from the first bit of CRC field on CAN bus. This field
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes. This field is useful to optimize the transmit performance based on
+ * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
+ * The duration of an arbitration process, in terms of CAN bits, is directly
+ * proportional to the number of available MBs and CAN baud rate and inversely
+ * proportional to the peripheral clock frequency. The optimal arbitration timing is
+ * that in which the last MB is scanned right before the first bit of the
+ * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
+ * clock ratio is high and the CAN baud rate is low then the arbitration can be
+ * delayed and vice-versa. If TASD is 0 then the arbitration start is not
+ * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
+ * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
+ * the CPU can configure a Tx MB later and less time is reserved for
+ * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
+ * to find winner MBs in time to compete with other nodes for the CAN bus. If the
+ * arbitration ends too much time before the first bit of Intermission field then
+ * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
+ * not the best to be transmitted. The optimal configuration for TASD can be
+ * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
+ * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
+ * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
+ * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
+ * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
+ * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
+ * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
+ * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
+ * Timing" for more details.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_TASD field. */
+#define CAN_RD_CTRL2_TASD(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_TASD_MASK) >> CAN_CTRL2_TASD_SHIFT)
+#define CAN_BRD_CTRL2_TASD(base) (CAN_RD_CTRL2_TASD(base))
+
+/*! @brief Set the TASD field to a new value. */
+#define CAN_WR_CTRL2_TASD(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_TASD_MASK, CAN_CTRL2_TASD(value)))
+#define CAN_BWR_CTRL2_TASD(base, value) (CAN_WR_CTRL2_TASD(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
+ *
+ * This 4-bit field defines the number of Rx FIFO filters, as shown in the
+ * following table. The maximum selectable number of filters is determined by the MCU.
+ * This field can only be written in Freeze mode as it is blocked by hardware in
+ * other modes. This field must not be programmed with values that make the
+ * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
+ * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
+ * a memory space equivalent to two Message Buffers which means that the more
+ * filters are implemented the less Mailboxes will be available. Considering that
+ * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
+ * be programmed with a value correponding to a number of filters not greater
+ * than the number of available memory words which can be calculated as follows:
+ * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
+ * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
+ * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
+ * SETUP_MB value (memory space available) the exceeding ones will not be functional.
+ * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
+ * Filter Table Remaining Available MailboxesThe number of the last remaining
+ * available mailboxes is defined by the least value between the parameter
+ * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
+ * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
+ * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
+ * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
+ * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
+ * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
+ * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
+ * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
+ * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
+ * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
+ * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
+ * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
+ * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
+ * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
+ * 0-37 MB 38-63 Elements 0-31 Elements 32-127
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_RFFN field. */
+#define CAN_RD_CTRL2_RFFN(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT)
+#define CAN_BRD_CTRL2_RFFN(base) (CAN_RD_CTRL2_RFFN(base))
+
+/*! @brief Set the RFFN field to a new value. */
+#define CAN_WR_CTRL2_RFFN(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_RFFN_MASK, CAN_CTRL2_RFFN(value)))
+#define CAN_BWR_CTRL2_RFFN(base, value) (CAN_WR_CTRL2_RFFN(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
+ *
+ * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
+ * can only be written in Freeze mode and has no effect out of Freeze mode.
+ *
+ * Values:
+ * - 0b0 - Maintain the write access restrictions.
+ * - 0b1 - Enable unrestricted write access to FlexCAN memory.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_WRMFRZ field. */
+#define CAN_RD_CTRL2_WRMFRZ(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_WRMFRZ_MASK) >> CAN_CTRL2_WRMFRZ_SHIFT)
+#define CAN_BRD_CTRL2_WRMFRZ(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_WRMFRZ_SHIFT))
+
+/*! @brief Set the WRMFRZ field to a new value. */
+#define CAN_WR_CTRL2_WRMFRZ(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_WRMFRZ_MASK, CAN_CTRL2_WRMFRZ(value)))
+#define CAN_BWR_CTRL2_WRMFRZ(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_WRMFRZ_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ESR2 - Error and Status 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ESR2 - Error and Status 2 register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various interrupt flags and some general status.
+ */
+/*!
+ * @name Constants and macros for entire CAN_ESR2 register
+ */
+/*@{*/
+#define CAN_RD_ESR2(base)        (CAN_ESR2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ESR2 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR2, field IMB[13] (RO)
+ *
+ * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
+ * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
+ * following cases: During arbitration, if an LPTM is found and it is inactive. If
+ * IMB is not asserted and a frame is transmitted successfully. This bit is
+ * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
+ * mechanism have the following behavior: if an MB is successfully transmitted and
+ * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
+ * the index related to the MB just transmitted is loaded into ESR2[LPTM].
+ *
+ * Values:
+ * - 0b0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
+ * - 0b1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox.
+ *     LPTM content is the number of the first one.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_IMB field. */
+#define CAN_RD_ESR2_IMB(base) ((CAN_ESR2_REG(base) & CAN_ESR2_IMB_MASK) >> CAN_ESR2_IMB_SHIFT)
+#define CAN_BRD_ESR2_IMB(base) (BITBAND_ACCESS32(&CAN_ESR2_REG(base), CAN_ESR2_IMB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR2, field VPS[14] (RO)
+ *
+ * This bit indicates whether IMB and LPTM contents are currently valid or not.
+ * VPS is asserted upon every complete Tx arbitration process unless the CPU
+ * writes to Control and Status word of a Mailbox that has already been scanned, that
+ * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
+ * If there is no inactive Mailbox and only one Tx Mailbox that is being
+ * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
+ * arbitration process or upon a write to Control and Status word of any Mailbox.
+ * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
+ * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
+ * in C/S of a MB that is being transmitted (pending abort), or any write attempt
+ * into a Tx MB with IFLAG set is blocked.
+ *
+ * Values:
+ * - 0b0 - Contents of IMB and LPTM are invalid.
+ * - 0b1 - Contents of IMB and LPTM are valid.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_VPS field. */
+#define CAN_RD_ESR2_VPS(base) ((CAN_ESR2_REG(base) & CAN_ESR2_VPS_MASK) >> CAN_ESR2_VPS_SHIFT)
+#define CAN_BRD_ESR2_VPS(base) (BITBAND_ACCESS32(&CAN_ESR2_REG(base), CAN_ESR2_VPS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR2, field LPTM[22:16] (RO)
+ *
+ * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
+ * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
+ * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
+ * negated then the Mailbox indicated is the one that has the greatest arbitration
+ * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
+ * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
+ * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
+ * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
+ * updated with its Mailbox number.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_LPTM field. */
+#define CAN_RD_ESR2_LPTM(base) ((CAN_ESR2_REG(base) & CAN_ESR2_LPTM_MASK) >> CAN_ESR2_LPTM_SHIFT)
+#define CAN_BRD_ESR2_LPTM(base) (CAN_RD_ESR2_LPTM(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CRCR - CRC Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CRCR - CRC Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides information about the CRC of transmitted messages.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CRCR register
+ */
+/*@{*/
+#define CAN_RD_CRCR(base)        (CAN_CRCR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CRCR bitfields
+ */
+
+/*!
+ * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
+ *
+ * This field indicates the CRC value of the last message transmitted. This
+ * field is updated at the same time the Tx Interrupt Flag is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CRCR_TXCRC field. */
+#define CAN_RD_CRCR_TXCRC(base) ((CAN_CRCR_REG(base) & CAN_CRCR_TXCRC_MASK) >> CAN_CRCR_TXCRC_SHIFT)
+#define CAN_BRD_CRCR_TXCRC(base) (CAN_RD_CRCR_TXCRC(base))
+/*@}*/
+
+/*!
+ * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
+ *
+ * This field indicates the number of the Mailbox corresponding to the value in
+ * TXCRC field.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CRCR_MBCRC field. */
+#define CAN_RD_CRCR_MBCRC(base) ((CAN_CRCR_REG(base) & CAN_CRCR_MBCRC_MASK) >> CAN_CRCR_MBCRC_SHIFT)
+#define CAN_BRD_CRCR_MBCRC(base) (CAN_RD_CRCR_MBCRC(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXFGMASK - Rx FIFO Global Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
+ * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
+ * according to CTRL2[RFFN] field setting. This register can only be written in
+ * Freeze mode as it is blocked by hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXFGMASK register
+ */
+/*@{*/
+#define CAN_RD_RXFGMASK(base)    (CAN_RXFGMASK_REG(base))
+#define CAN_WR_RXFGMASK(base, value) (CAN_RXFGMASK_REG(base) = (value))
+#define CAN_RMW_RXFGMASK(base, mask, value) (CAN_WR_RXFGMASK(base, (CAN_RD_RXFGMASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) |  (value)))
+#define CAN_CLR_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) & ~(value)))
+#define CAN_TOG_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXFIR - Rx FIFO Information Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXFIR - Rx FIFO Information Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFIR provides information on Rx FIFO. This register is the port through
+ * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
+ * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
+ * well as its output is updated whenever the output of the Rx FIFO is updated
+ * with the next message. See Section "Rx FIFO" for instructions on reading this
+ * register.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXFIR register
+ */
+/*@{*/
+#define CAN_RD_RXFIR(base)       (CAN_RXFIR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_RXFIR bitfields
+ */
+
+/*!
+ * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
+ *
+ * This field indicates which Identifier Acceptance Filter was hit by the
+ * received message that is in the output of the Rx FIFO. If multiple filters match the
+ * incoming message ID then the first matching IDAF found (lowest number) by the
+ * matching process is indicated. This field is valid only while the
+ * IFLAG[BUF5I] is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_RXFIR_IDHIT field. */
+#define CAN_RD_RXFIR_IDHIT(base) ((CAN_RXFIR_REG(base) & CAN_RXFIR_IDHIT_MASK) >> CAN_RXFIR_IDHIT_SHIFT)
+#define CAN_BRD_RXFIR_IDHIT(base) (CAN_RD_RXFIR_IDHIT(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CS - Message Buffer 0 CS Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CS - Message Buffer 0 CS Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_CS register
+ */
+/*@{*/
+#define CAN_RD_CS(base, index)   (CAN_CS_REG(base, index))
+#define CAN_WR_CS(base, index, value) (CAN_CS_REG(base, index) = (value))
+#define CAN_RMW_CS(base, index, mask, value) (CAN_WR_CS(base, index, (CAN_RD_CS(base, index) & ~(mask)) | (value)))
+#define CAN_SET_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) |  (value)))
+#define CAN_CLR_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) & ~(value)))
+#define CAN_TOG_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CS bitfields
+ */
+
+/*!
+ * @name Register CAN_CS, field TIME_STAMP[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_TIME_STAMP field. */
+#define CAN_RD_CS_TIME_STAMP(base, index) ((CAN_CS_REG(base, index) & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT)
+#define CAN_BRD_CS_TIME_STAMP(base, index) (CAN_RD_CS_TIME_STAMP(base, index))
+
+/*! @brief Set the TIME_STAMP field to a new value. */
+#define CAN_WR_CS_TIME_STAMP(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_TIME_STAMP_MASK, CAN_CS_TIME_STAMP(value)))
+#define CAN_BWR_CS_TIME_STAMP(base, index, value) (CAN_WR_CS_TIME_STAMP(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field DLC[19:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_DLC field. */
+#define CAN_RD_CS_DLC(base, index) ((CAN_CS_REG(base, index) & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT)
+#define CAN_BRD_CS_DLC(base, index) (CAN_RD_CS_DLC(base, index))
+
+/*! @brief Set the DLC field to a new value. */
+#define CAN_WR_CS_DLC(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_DLC_MASK, CAN_CS_DLC(value)))
+#define CAN_BWR_CS_DLC(base, index, value) (CAN_WR_CS_DLC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field RTR[20] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_RTR field. */
+#define CAN_RD_CS_RTR(base, index) ((CAN_CS_REG(base, index) & CAN_CS_RTR_MASK) >> CAN_CS_RTR_SHIFT)
+#define CAN_BRD_CS_RTR(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_RTR_SHIFT))
+
+/*! @brief Set the RTR field to a new value. */
+#define CAN_WR_CS_RTR(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_RTR_MASK, CAN_CS_RTR(value)))
+#define CAN_BWR_CS_RTR(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_RTR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field IDE[21] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_IDE field. */
+#define CAN_RD_CS_IDE(base, index) ((CAN_CS_REG(base, index) & CAN_CS_IDE_MASK) >> CAN_CS_IDE_SHIFT)
+#define CAN_BRD_CS_IDE(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_IDE_SHIFT))
+
+/*! @brief Set the IDE field to a new value. */
+#define CAN_WR_CS_IDE(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_IDE_MASK, CAN_CS_IDE(value)))
+#define CAN_BWR_CS_IDE(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_IDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field SRR[22] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_SRR field. */
+#define CAN_RD_CS_SRR(base, index) ((CAN_CS_REG(base, index) & CAN_CS_SRR_MASK) >> CAN_CS_SRR_SHIFT)
+#define CAN_BRD_CS_SRR(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_SRR_SHIFT))
+
+/*! @brief Set the SRR field to a new value. */
+#define CAN_WR_CS_SRR(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_SRR_MASK, CAN_CS_SRR(value)))
+#define CAN_BWR_CS_SRR(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_SRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field CODE[27:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_CODE field. */
+#define CAN_RD_CS_CODE(base, index) ((CAN_CS_REG(base, index) & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT)
+#define CAN_BRD_CS_CODE(base, index) (CAN_RD_CS_CODE(base, index))
+
+/*! @brief Set the CODE field to a new value. */
+#define CAN_WR_CS_CODE(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_CODE_MASK, CAN_CS_CODE(value)))
+#define CAN_BWR_CS_CODE(base, index, value) (CAN_WR_CS_CODE(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ID - Message Buffer 0 ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ID - Message Buffer 0 ID Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_ID register
+ */
+/*@{*/
+#define CAN_RD_ID(base, index)   (CAN_ID_REG(base, index))
+#define CAN_WR_ID(base, index, value) (CAN_ID_REG(base, index) = (value))
+#define CAN_RMW_ID(base, index, mask, value) (CAN_WR_ID(base, index, (CAN_RD_ID(base, index) & ~(mask)) | (value)))
+#define CAN_SET_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) |  (value)))
+#define CAN_CLR_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) & ~(value)))
+#define CAN_TOG_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ID bitfields
+ */
+
+/*!
+ * @name Register CAN_ID, field EXT[17:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_EXT field. */
+#define CAN_RD_ID_EXT(base, index) ((CAN_ID_REG(base, index) & CAN_ID_EXT_MASK) >> CAN_ID_EXT_SHIFT)
+#define CAN_BRD_ID_EXT(base, index) (CAN_RD_ID_EXT(base, index))
+
+/*! @brief Set the EXT field to a new value. */
+#define CAN_WR_ID_EXT(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_EXT_MASK, CAN_ID_EXT(value)))
+#define CAN_BWR_ID_EXT(base, index, value) (CAN_WR_ID_EXT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ID, field STD[28:18] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_STD field. */
+#define CAN_RD_ID_STD(base, index) ((CAN_ID_REG(base, index) & CAN_ID_STD_MASK) >> CAN_ID_STD_SHIFT)
+#define CAN_BRD_ID_STD(base, index) (CAN_RD_ID_STD(base, index))
+
+/*! @brief Set the STD field to a new value. */
+#define CAN_WR_ID_STD(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_STD_MASK, CAN_ID_STD(value)))
+#define CAN_BWR_ID_STD(base, index, value) (CAN_WR_ID_STD(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ID, field PRIO[31:29] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_PRIO field. */
+#define CAN_RD_ID_PRIO(base, index) ((CAN_ID_REG(base, index) & CAN_ID_PRIO_MASK) >> CAN_ID_PRIO_SHIFT)
+#define CAN_BRD_ID_PRIO(base, index) (CAN_RD_ID_PRIO(base, index))
+
+/*! @brief Set the PRIO field to a new value. */
+#define CAN_WR_ID_PRIO(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_PRIO_MASK, CAN_ID_PRIO(value)))
+#define CAN_BWR_ID_PRIO(base, index, value) (CAN_WR_ID_PRIO(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_WORD0 - Message Buffer 0 WORD0 Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_WORD0 - Message Buffer 0 WORD0 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_WORD0 register
+ */
+/*@{*/
+#define CAN_RD_WORD0(base, index) (CAN_WORD0_REG(base, index))
+#define CAN_WR_WORD0(base, index, value) (CAN_WORD0_REG(base, index) = (value))
+#define CAN_RMW_WORD0(base, index, mask, value) (CAN_WR_WORD0(base, index, (CAN_RD_WORD0(base, index) & ~(mask)) | (value)))
+#define CAN_SET_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) |  (value)))
+#define CAN_CLR_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) & ~(value)))
+#define CAN_TOG_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_WORD0 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_3[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_3 field. */
+#define CAN_RD_WORD0_DATA_BYTE_3(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_3_MASK) >> CAN_WORD0_DATA_BYTE_3_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_3(base, index) (CAN_RD_WORD0_DATA_BYTE_3(base, index))
+
+/*! @brief Set the DATA_BYTE_3 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_3(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_3_MASK, CAN_WORD0_DATA_BYTE_3(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_3(base, index, value) (CAN_WR_WORD0_DATA_BYTE_3(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_2[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_2 field. */
+#define CAN_RD_WORD0_DATA_BYTE_2(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_2_MASK) >> CAN_WORD0_DATA_BYTE_2_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_2(base, index) (CAN_RD_WORD0_DATA_BYTE_2(base, index))
+
+/*! @brief Set the DATA_BYTE_2 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_2(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_2_MASK, CAN_WORD0_DATA_BYTE_2(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_2(base, index, value) (CAN_WR_WORD0_DATA_BYTE_2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_1[23:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_1 field. */
+#define CAN_RD_WORD0_DATA_BYTE_1(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_1_MASK) >> CAN_WORD0_DATA_BYTE_1_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_1(base, index) (CAN_RD_WORD0_DATA_BYTE_1(base, index))
+
+/*! @brief Set the DATA_BYTE_1 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_1(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_1_MASK, CAN_WORD0_DATA_BYTE_1(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_1(base, index, value) (CAN_WR_WORD0_DATA_BYTE_1(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_0[31:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_0 field. */
+#define CAN_RD_WORD0_DATA_BYTE_0(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_0_MASK) >> CAN_WORD0_DATA_BYTE_0_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_0(base, index) (CAN_RD_WORD0_DATA_BYTE_0(base, index))
+
+/*! @brief Set the DATA_BYTE_0 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_0(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_0_MASK, CAN_WORD0_DATA_BYTE_0(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_0(base, index, value) (CAN_WR_WORD0_DATA_BYTE_0(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_WORD1 - Message Buffer 0 WORD1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_WORD1 - Message Buffer 0 WORD1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_WORD1 register
+ */
+/*@{*/
+#define CAN_RD_WORD1(base, index) (CAN_WORD1_REG(base, index))
+#define CAN_WR_WORD1(base, index, value) (CAN_WORD1_REG(base, index) = (value))
+#define CAN_RMW_WORD1(base, index, mask, value) (CAN_WR_WORD1(base, index, (CAN_RD_WORD1(base, index) & ~(mask)) | (value)))
+#define CAN_SET_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) |  (value)))
+#define CAN_CLR_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) & ~(value)))
+#define CAN_TOG_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_WORD1 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_7[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_7 field. */
+#define CAN_RD_WORD1_DATA_BYTE_7(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_7_MASK) >> CAN_WORD1_DATA_BYTE_7_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_7(base, index) (CAN_RD_WORD1_DATA_BYTE_7(base, index))
+
+/*! @brief Set the DATA_BYTE_7 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_7(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_7_MASK, CAN_WORD1_DATA_BYTE_7(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_7(base, index, value) (CAN_WR_WORD1_DATA_BYTE_7(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_6[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_6 field. */
+#define CAN_RD_WORD1_DATA_BYTE_6(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_6_MASK) >> CAN_WORD1_DATA_BYTE_6_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_6(base, index) (CAN_RD_WORD1_DATA_BYTE_6(base, index))
+
+/*! @brief Set the DATA_BYTE_6 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_6(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_6_MASK, CAN_WORD1_DATA_BYTE_6(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_6(base, index, value) (CAN_WR_WORD1_DATA_BYTE_6(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_5[23:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_5 field. */
+#define CAN_RD_WORD1_DATA_BYTE_5(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_5_MASK) >> CAN_WORD1_DATA_BYTE_5_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_5(base, index) (CAN_RD_WORD1_DATA_BYTE_5(base, index))
+
+/*! @brief Set the DATA_BYTE_5 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_5(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_5_MASK, CAN_WORD1_DATA_BYTE_5(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_5(base, index, value) (CAN_WR_WORD1_DATA_BYTE_5(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_4[31:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_4 field. */
+#define CAN_RD_WORD1_DATA_BYTE_4(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_4_MASK) >> CAN_WORD1_DATA_BYTE_4_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_4(base, index) (CAN_RD_WORD1_DATA_BYTE_4(base, index))
+
+/*! @brief Set the DATA_BYTE_4 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_4(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_4_MASK, CAN_WORD1_DATA_BYTE_4(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_4(base, index, value) (CAN_WR_WORD1_DATA_BYTE_4(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXIMR - Rx Individual Mask Registers
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXIMR - Rx Individual Mask Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers are located in RAM. RXIMR are used as acceptance masks for ID
+ * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
+ * register is provided for each available Mailbox, providing ID masking
+ * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
+ * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
+ * Table elements on a one-to-one correspondence depending on the setting of
+ * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
+ * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
+ * are not affected by reset and must be explicitly initialized prior to any
+ * reception.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXIMR register
+ */
+/*@{*/
+#define CAN_RD_RXIMR(base, index) (CAN_RXIMR_REG(base, index))
+#define CAN_WR_RXIMR(base, index, value) (CAN_RXIMR_REG(base, index) = (value))
+#define CAN_RMW_RXIMR(base, index, mask, value) (CAN_WR_RXIMR(base, index, (CAN_RD_RXIMR(base, index) & ~(mask)) | (value)))
+#define CAN_SET_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) |  (value)))
+#define CAN_CLR_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) & ~(value)))
+#define CAN_TOG_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 CAU
+ *
+ * Memory Mapped Cryptographic Acceleration Unit (MMCAU)
+ *
+ * Registers defined in this header file:
+ * - CAU_DIRECT - Direct access register 0
+ * - CAU_LDR_CASR - Status register - Load Register command
+ * - CAU_LDR_CAA - Accumulator register - Load Register command
+ * - CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ * - CAU_STR_CASR - Status register - Store Register command
+ * - CAU_STR_CAA - Accumulator register - Store Register command
+ * - CAU_STR_CA - General Purpose Register 0 - Store Register command
+ * - CAU_ADR_CASR - Status register - Add Register command
+ * - CAU_ADR_CAA - Accumulator register - Add to register command
+ * - CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ * - CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ * - CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ * - CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ * - CAU_XOR_CASR - Status register - Exclusive Or command
+ * - CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ * - CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ * - CAU_ROTL_CASR - Status register - Rotate Left command
+ * - CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ * - CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ * - CAU_AESC_CASR - Status register - AES Column Operation command
+ * - CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ * - CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ * - CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ * - CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ * - CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ */
+
+#define CAU_INSTANCE_COUNT (1U) /*!< Number of instances of the CAU module. */
+#define CAU_IDX (0U) /*!< Instance number for CAU. */
+
+/*******************************************************************************
+ * CAU_DIRECT - Direct access register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_DIRECT - Direct access register 0 (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_DIRECT register
+ */
+/*@{*/
+#define CAU_WR_DIRECT(base, index, value) (CAU_DIRECT_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CASR - Status register - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CASR - Status register - Load Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CASR register
+ */
+/*@{*/
+#define CAU_WR_LDR_CASR(base, value) (CAU_LDR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_LDR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_LDR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_LDR_CASR_IC(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_IC(value)))
+#define CAU_BWR_LDR_CASR_IC(base, value) (CAU_WR_LDR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_LDR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_LDR_CASR_DPE(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_DPE(value)))
+#define CAU_BWR_LDR_CASR_DPE(base, value) (CAU_WR_LDR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_LDR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_LDR_CASR_VER(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_VER(value)))
+#define CAU_BWR_LDR_CASR_VER(base, value) (CAU_WR_LDR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CAA - Accumulator register - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CAA - Accumulator register - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CAA register
+ */
+/*@{*/
+#define CAU_WR_LDR_CAA(base, value) (CAU_LDR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CA - General Purpose Register 0 - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CA register
+ */
+/*@{*/
+#define CAU_WR_LDR_CA(base, index, value) (CAU_LDR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CASR - Status register - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CASR - Status register - Store Register command (RO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CASR register
+ */
+/*@{*/
+#define CAU_RD_STR_CASR(base)    (CAU_STR_CASR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_STR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_STR_CASR, field IC[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_IC field. */
+#define CAU_RD_STR_CASR_IC(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_IC_MASK) >> CAU_STR_CASR_IC_SHIFT)
+#define CAU_BRD_STR_CASR_IC(base) (CAU_RD_STR_CASR_IC(base))
+/*@}*/
+
+/*!
+ * @name Register CAU_STR_CASR, field DPE[1] (RO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_DPE field. */
+#define CAU_RD_STR_CASR_DPE(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_DPE_MASK) >> CAU_STR_CASR_DPE_SHIFT)
+#define CAU_BRD_STR_CASR_DPE(base) (CAU_RD_STR_CASR_DPE(base))
+/*@}*/
+
+/*!
+ * @name Register CAU_STR_CASR, field VER[31:28] (RO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_VER field. */
+#define CAU_RD_STR_CASR_VER(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_VER_MASK) >> CAU_STR_CASR_VER_SHIFT)
+#define CAU_BRD_STR_CASR_VER(base) (CAU_RD_STR_CASR_VER(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CAA - Accumulator register - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CAA - Accumulator register - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CAA register
+ */
+/*@{*/
+#define CAU_RD_STR_CAA(base)     (CAU_STR_CAA_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CA - General Purpose Register 0 - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CA - General Purpose Register 0 - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CA register
+ */
+/*@{*/
+#define CAU_RD_STR_CA(base, index) (CAU_STR_CA_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CASR - Status register - Add Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CASR - Status register - Add Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CASR register
+ */
+/*@{*/
+#define CAU_WR_ADR_CASR(base, value) (CAU_ADR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_ADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_ADR_CASR_IC(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_IC(value)))
+#define CAU_BWR_ADR_CASR_IC(base, value) (CAU_WR_ADR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_ADR_CASR_DPE(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_DPE(value)))
+#define CAU_BWR_ADR_CASR_DPE(base, value) (CAU_WR_ADR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_ADR_CASR_VER(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_VER(value)))
+#define CAU_BWR_ADR_CASR_VER(base, value) (CAU_WR_ADR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CAA - Accumulator register - Add to register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CAA - Accumulator register - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CAA register
+ */
+/*@{*/
+#define CAU_WR_ADR_CAA(base, value) (CAU_ADR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CA - General Purpose Register 0 - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CA register
+ */
+/*@{*/
+#define CAU_WR_ADR_CA(base, index, value) (CAU_ADR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CASR - Status register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CASR register
+ */
+/*@{*/
+#define CAU_WR_RADR_CASR(base, value) (CAU_RADR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_RADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_RADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_RADR_CASR_IC(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_IC(value)))
+#define CAU_BWR_RADR_CASR_IC(base, value) (CAU_WR_RADR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_RADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_RADR_CASR_DPE(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_DPE(value)))
+#define CAU_BWR_RADR_CASR_DPE(base, value) (CAU_WR_RADR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_RADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_RADR_CASR_VER(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_VER(value)))
+#define CAU_BWR_RADR_CASR_VER(base, value) (CAU_WR_RADR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CAA register
+ */
+/*@{*/
+#define CAU_WR_RADR_CAA(base, value) (CAU_RADR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CA register
+ */
+/*@{*/
+#define CAU_WR_RADR_CA(base, index, value) (CAU_RADR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CASR - Status register - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CASR - Status register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CASR register
+ */
+/*@{*/
+#define CAU_WR_XOR_CASR(base, value) (CAU_XOR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_XOR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_XOR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_XOR_CASR_IC(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_IC(value)))
+#define CAU_BWR_XOR_CASR_IC(base, value) (CAU_WR_XOR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_XOR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_XOR_CASR_DPE(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_DPE(value)))
+#define CAU_BWR_XOR_CASR_DPE(base, value) (CAU_WR_XOR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_XOR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_XOR_CASR_VER(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_VER(value)))
+#define CAU_BWR_XOR_CASR_VER(base, value) (CAU_WR_XOR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CAA register
+ */
+/*@{*/
+#define CAU_WR_XOR_CAA(base, value) (CAU_XOR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CA register
+ */
+/*@{*/
+#define CAU_WR_XOR_CA(base, index, value) (CAU_XOR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CASR - Status register - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CASR - Status register - Rotate Left command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CASR register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CASR(base, value) (CAU_ROTL_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_ROTL_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ROTL_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_ROTL_CASR_IC(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_IC(value)))
+#define CAU_BWR_ROTL_CASR_IC(base, value) (CAU_WR_ROTL_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ROTL_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_ROTL_CASR_DPE(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_DPE(value)))
+#define CAU_BWR_ROTL_CASR_DPE(base, value) (CAU_WR_ROTL_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_ROTL_CASR_VER(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_VER(value)))
+#define CAU_BWR_ROTL_CASR_VER(base, value) (CAU_WR_ROTL_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CAA register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CAA(base, value) (CAU_ROTL_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CA register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CA(base, index, value) (CAU_ROTL_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CASR - Status register - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CASR - Status register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CASR register
+ */
+/*@{*/
+#define CAU_WR_AESC_CASR(base, value) (CAU_AESC_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_AESC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_AESC_CASR_IC(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_IC(value)))
+#define CAU_BWR_AESC_CASR_IC(base, value) (CAU_WR_AESC_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_AESC_CASR_DPE(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_DPE(value)))
+#define CAU_BWR_AESC_CASR_DPE(base, value) (CAU_WR_AESC_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_AESC_CASR_VER(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_VER(value)))
+#define CAU_BWR_AESC_CASR_VER(base, value) (CAU_WR_AESC_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CAA register
+ */
+/*@{*/
+#define CAU_WR_AESC_CAA(base, value) (CAU_AESC_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CA register
+ */
+/*@{*/
+#define CAU_WR_AESC_CA(base, index, value) (CAU_AESC_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CASR - Status register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CASR register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CASR(base, value) (CAU_AESIC_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_AESIC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESIC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_AESIC_CASR_IC(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_IC(value)))
+#define CAU_BWR_AESIC_CASR_IC(base, value) (CAU_WR_AESIC_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESIC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_AESIC_CASR_DPE(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_DPE(value)))
+#define CAU_BWR_AESIC_CASR_DPE(base, value) (CAU_WR_AESIC_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_AESIC_CASR_VER(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_VER(value)))
+#define CAU_BWR_AESIC_CASR_VER(base, value) (CAU_WR_AESIC_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CAA register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CAA(base, value) (CAU_AESIC_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CA register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CA(base, index, value) (CAU_AESIC_CA_REG(base, index) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CMP
+ *
+ * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
+ *
+ * Registers defined in this header file:
+ * - CMP_CR0 - CMP Control Register 0
+ * - CMP_CR1 - CMP Control Register 1
+ * - CMP_FPR - CMP Filter Period Register
+ * - CMP_SCR - CMP Status and Control Register
+ * - CMP_DACCR - DAC Control Register
+ * - CMP_MUXCR - MUX Control Register
+ */
+
+#define CMP_INSTANCE_COUNT (3U) /*!< Number of instances of the CMP module. */
+#define CMP0_IDX (0U) /*!< Instance number for CMP0. */
+#define CMP1_IDX (1U) /*!< Instance number for CMP1. */
+#define CMP2_IDX (2U) /*!< Instance number for CMP2. */
+
+/*******************************************************************************
+ * CMP_CR0 - CMP Control Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR0 - CMP Control Register 0 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR0 register
+ */
+/*@{*/
+#define CMP_RD_CR0(base)         (CMP_CR0_REG(base))
+#define CMP_WR_CR0(base, value)  (CMP_CR0_REG(base) = (value))
+#define CMP_RMW_CR0(base, mask, value) (CMP_WR_CR0(base, (CMP_RD_CR0(base) & ~(mask)) | (value)))
+#define CMP_SET_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) |  (value)))
+#define CMP_CLR_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) & ~(value)))
+#define CMP_TOG_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR0 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
+ *
+ * Defines the programmable hysteresis level. The hysteresis values associated
+ * with each level are device-specific. See the Data Sheet of the device for the
+ * exact values.
+ *
+ * Values:
+ * - 0b00 - Level 0
+ * - 0b01 - Level 1
+ * - 0b10 - Level 2
+ * - 0b11 - Level 3
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
+#define CMP_RD_CR0_HYSTCTR(base) ((CMP_CR0_REG(base) & CMP_CR0_HYSTCTR_MASK) >> CMP_CR0_HYSTCTR_SHIFT)
+#define CMP_BRD_CR0_HYSTCTR(base) (CMP_RD_CR0_HYSTCTR(base))
+
+/*! @brief Set the HYSTCTR field to a new value. */
+#define CMP_WR_CR0_HYSTCTR(base, value) (CMP_RMW_CR0(base, CMP_CR0_HYSTCTR_MASK, CMP_CR0_HYSTCTR(value)))
+#define CMP_BWR_CR0_HYSTCTR(base, value) (CMP_WR_CR0_HYSTCTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
+ *
+ * Represents the number of consecutive samples that must agree prior to the
+ * comparator ouput filter accepting a new output state. For information regarding
+ * filter programming and latency, see the Functional descriptionThe CMP module
+ * can be used to compare two analog input voltages applied to INP and INM. .
+ *
+ * Values:
+ * - 0b000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not
+ *     a legal state, and is not recommended. If SE = 0, COUT = COUTA.
+ * - 0b001 - One sample must agree. The comparator output is simply sampled.
+ * - 0b010 - 2 consecutive samples must agree.
+ * - 0b011 - 3 consecutive samples must agree.
+ * - 0b100 - 4 consecutive samples must agree.
+ * - 0b101 - 5 consecutive samples must agree.
+ * - 0b110 - 6 consecutive samples must agree.
+ * - 0b111 - 7 consecutive samples must agree.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
+#define CMP_RD_CR0_FILTER_CNT(base) ((CMP_CR0_REG(base) & CMP_CR0_FILTER_CNT_MASK) >> CMP_CR0_FILTER_CNT_SHIFT)
+#define CMP_BRD_CR0_FILTER_CNT(base) (CMP_RD_CR0_FILTER_CNT(base))
+
+/*! @brief Set the FILTER_CNT field to a new value. */
+#define CMP_WR_CR0_FILTER_CNT(base, value) (CMP_RMW_CR0(base, CMP_CR0_FILTER_CNT_MASK, CMP_CR0_FILTER_CNT(value)))
+#define CMP_BWR_CR0_FILTER_CNT(base, value) (CMP_WR_CR0_FILTER_CNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_CR1 - CMP Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR1 - CMP Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR1 register
+ */
+/*@{*/
+#define CMP_RD_CR1(base)         (CMP_CR1_REG(base))
+#define CMP_WR_CR1(base, value)  (CMP_CR1_REG(base) = (value))
+#define CMP_RMW_CR1(base, mask, value) (CMP_WR_CR1(base, (CMP_RD_CR1(base) & ~(mask)) | (value)))
+#define CMP_SET_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) |  (value)))
+#define CMP_CLR_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) & ~(value)))
+#define CMP_TOG_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR1 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR1, field EN[0] (RW)
+ *
+ * Enables the Analog Comparator module. When the module is not enabled, it
+ * remains in the off state, and consumes no power. When the user selects the same
+ * input from analog mux to the positive and negative port, the comparator is
+ * disabled automatically.
+ *
+ * Values:
+ * - 0b0 - Analog Comparator is disabled.
+ * - 0b1 - Analog Comparator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_EN field. */
+#define CMP_RD_CR1_EN(base)  ((CMP_CR1_REG(base) & CMP_CR1_EN_MASK) >> CMP_CR1_EN_SHIFT)
+#define CMP_BRD_CR1_EN(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT))
+
+/*! @brief Set the EN field to a new value. */
+#define CMP_WR_CR1_EN(base, value) (CMP_RMW_CR1(base, CMP_CR1_EN_MASK, CMP_CR1_EN(value)))
+#define CMP_BWR_CR1_EN(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field OPE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - CMPO is not available on the associated CMPO output pin. If the
+ *     comparator does not own the pin, this field has no effect.
+ * - 0b1 - CMPO is available on the associated CMPO output pin. The comparator
+ *     output (CMPO) is driven out on the associated CMPO output pin if the
+ *     comparator owns the pin. If the comparator does not own the field, this bit has
+ *     no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_OPE field. */
+#define CMP_RD_CR1_OPE(base) ((CMP_CR1_REG(base) & CMP_CR1_OPE_MASK) >> CMP_CR1_OPE_SHIFT)
+#define CMP_BRD_CR1_OPE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT))
+
+/*! @brief Set the OPE field to a new value. */
+#define CMP_WR_CR1_OPE(base, value) (CMP_RMW_CR1(base, CMP_CR1_OPE_MASK, CMP_CR1_OPE(value)))
+#define CMP_BWR_CR1_OPE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field COS[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Set the filtered comparator output (CMPO) to equal COUT.
+ * - 0b1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_COS field. */
+#define CMP_RD_CR1_COS(base) ((CMP_CR1_REG(base) & CMP_CR1_COS_MASK) >> CMP_CR1_COS_SHIFT)
+#define CMP_BRD_CR1_COS(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT))
+
+/*! @brief Set the COS field to a new value. */
+#define CMP_WR_CR1_COS(base, value) (CMP_RMW_CR1(base, CMP_CR1_COS_MASK, CMP_CR1_COS(value)))
+#define CMP_BWR_CR1_COS(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field INV[3] (RW)
+ *
+ * Allows selection of the polarity of the analog comparator function. It is
+ * also driven to the COUT output, on both the device pin and as SCR[COUT], when
+ * OPE=0.
+ *
+ * Values:
+ * - 0b0 - Does not invert the comparator output.
+ * - 0b1 - Inverts the comparator output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_INV field. */
+#define CMP_RD_CR1_INV(base) ((CMP_CR1_REG(base) & CMP_CR1_INV_MASK) >> CMP_CR1_INV_SHIFT)
+#define CMP_BRD_CR1_INV(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT))
+
+/*! @brief Set the INV field to a new value. */
+#define CMP_WR_CR1_INV(base, value) (CMP_RMW_CR1(base, CMP_CR1_INV_MASK, CMP_CR1_INV(value)))
+#define CMP_BWR_CR1_INV(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field PMODE[4] (RW)
+ *
+ * See the electrical specifications table in the device Data Sheet for details.
+ *
+ * Values:
+ * - 0b0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
+ *     output propagation delay and lower current consumption.
+ * - 0b1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has
+ *     faster output propagation delay and higher current consumption.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_PMODE field. */
+#define CMP_RD_CR1_PMODE(base) ((CMP_CR1_REG(base) & CMP_CR1_PMODE_MASK) >> CMP_CR1_PMODE_SHIFT)
+#define CMP_BRD_CR1_PMODE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT))
+
+/*! @brief Set the PMODE field to a new value. */
+#define CMP_WR_CR1_PMODE(base, value) (CMP_RMW_CR1(base, CMP_CR1_PMODE_MASK, CMP_CR1_PMODE(value)))
+#define CMP_BWR_CR1_PMODE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field WE[6] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0b0 - Windowing mode is not selected.
+ * - 0b1 - Windowing mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_WE field. */
+#define CMP_RD_CR1_WE(base)  ((CMP_CR1_REG(base) & CMP_CR1_WE_MASK) >> CMP_CR1_WE_SHIFT)
+#define CMP_BRD_CR1_WE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT))
+
+/*! @brief Set the WE field to a new value. */
+#define CMP_WR_CR1_WE(base, value) (CMP_RMW_CR1(base, CMP_CR1_WE_MASK, CMP_CR1_WE(value)))
+#define CMP_BWR_CR1_WE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field SE[7] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0b0 - Sampling mode is not selected.
+ * - 0b1 - Sampling mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_SE field. */
+#define CMP_RD_CR1_SE(base)  ((CMP_CR1_REG(base) & CMP_CR1_SE_MASK) >> CMP_CR1_SE_SHIFT)
+#define CMP_BRD_CR1_SE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT))
+
+/*! @brief Set the SE field to a new value. */
+#define CMP_WR_CR1_SE(base, value) (CMP_RMW_CR1(base, CMP_CR1_SE_MASK, CMP_CR1_SE(value)))
+#define CMP_BWR_CR1_SE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_FPR - CMP Filter Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_FPR - CMP Filter Period Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_FPR register
+ */
+/*@{*/
+#define CMP_RD_FPR(base)         (CMP_FPR_REG(base))
+#define CMP_WR_FPR(base, value)  (CMP_FPR_REG(base) = (value))
+#define CMP_RMW_FPR(base, mask, value) (CMP_WR_FPR(base, (CMP_RD_FPR(base) & ~(mask)) | (value)))
+#define CMP_SET_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) |  (value)))
+#define CMP_CLR_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) & ~(value)))
+#define CMP_TOG_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_SCR - CMP Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_SCR - CMP Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_SCR register
+ */
+/*@{*/
+#define CMP_RD_SCR(base)         (CMP_SCR_REG(base))
+#define CMP_WR_SCR(base, value)  (CMP_SCR_REG(base) = (value))
+#define CMP_RMW_SCR(base, mask, value) (CMP_WR_SCR(base, (CMP_RD_SCR(base) & ~(mask)) | (value)))
+#define CMP_SET_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) |  (value)))
+#define CMP_CLR_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) & ~(value)))
+#define CMP_TOG_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_SCR bitfields
+ */
+
+/*!
+ * @name Register CMP_SCR, field COUT[0] (RO)
+ *
+ * Returns the current value of the Analog Comparator output, when read. The
+ * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
+ * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_COUT field. */
+#define CMP_RD_SCR_COUT(base) ((CMP_SCR_REG(base) & CMP_SCR_COUT_MASK) >> CMP_SCR_COUT_SHIFT)
+#define CMP_BRD_SCR_COUT(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_COUT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFF[1] (W1C)
+ *
+ * Detects a falling-edge on COUT, when set, during normal operation. CFF is
+ * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0b0 - Falling-edge on COUT has not been detected.
+ * - 0b1 - Falling-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFF field. */
+#define CMP_RD_SCR_CFF(base) ((CMP_SCR_REG(base) & CMP_SCR_CFF_MASK) >> CMP_SCR_CFF_SHIFT)
+#define CMP_BRD_SCR_CFF(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT))
+
+/*! @brief Set the CFF field to a new value. */
+#define CMP_WR_SCR_CFF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_CFF(value)))
+#define CMP_BWR_SCR_CFF(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFR[2] (W1C)
+ *
+ * Detects a rising-edge on COUT, when set, during normal operation. CFR is
+ * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0b0 - Rising-edge on COUT has not been detected.
+ * - 0b1 - Rising-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFR field. */
+#define CMP_RD_SCR_CFR(base) ((CMP_SCR_REG(base) & CMP_SCR_CFR_MASK) >> CMP_SCR_CFR_SHIFT)
+#define CMP_BRD_SCR_CFR(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT))
+
+/*! @brief Set the CFR field to a new value. */
+#define CMP_WR_SCR_CFR(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK), CMP_SCR_CFR(value)))
+#define CMP_BWR_SCR_CFR(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IEF[3] (RW)
+ *
+ * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFF is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled.
+ * - 0b1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IEF field. */
+#define CMP_RD_SCR_IEF(base) ((CMP_SCR_REG(base) & CMP_SCR_IEF_MASK) >> CMP_SCR_IEF_SHIFT)
+#define CMP_BRD_SCR_IEF(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT))
+
+/*! @brief Set the IEF field to a new value. */
+#define CMP_WR_SCR_IEF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IEF_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IEF(value)))
+#define CMP_BWR_SCR_IEF(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IER[4] (RW)
+ *
+ * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFR is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled.
+ * - 0b1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IER field. */
+#define CMP_RD_SCR_IER(base) ((CMP_SCR_REG(base) & CMP_SCR_IER_MASK) >> CMP_SCR_IER_SHIFT)
+#define CMP_BRD_SCR_IER(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT))
+
+/*! @brief Set the IER field to a new value. */
+#define CMP_WR_SCR_IER(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IER_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IER(value)))
+#define CMP_BWR_SCR_IER(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field DMAEN[6] (RW)
+ *
+ * Enables the DMA transfer triggered from the CMP module. When this field is
+ * set, a DMA request is asserted when CFR or CFF is set.
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_DMAEN field. */
+#define CMP_RD_SCR_DMAEN(base) ((CMP_SCR_REG(base) & CMP_SCR_DMAEN_MASK) >> CMP_SCR_DMAEN_SHIFT)
+#define CMP_BRD_SCR_DMAEN(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define CMP_WR_SCR_DMAEN(base, value) (CMP_RMW_SCR(base, (CMP_SCR_DMAEN_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_DMAEN(value)))
+#define CMP_BWR_SCR_DMAEN(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_DACCR - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_DACCR - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_DACCR register
+ */
+/*@{*/
+#define CMP_RD_DACCR(base)       (CMP_DACCR_REG(base))
+#define CMP_WR_DACCR(base, value) (CMP_DACCR_REG(base) = (value))
+#define CMP_RMW_DACCR(base, mask, value) (CMP_WR_DACCR(base, (CMP_RD_DACCR(base) & ~(mask)) | (value)))
+#define CMP_SET_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) |  (value)))
+#define CMP_CLR_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) & ~(value)))
+#define CMP_TOG_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_DACCR bitfields
+ */
+
+/*!
+ * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
+ *
+ * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
+ * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VOSEL field. */
+#define CMP_RD_DACCR_VOSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VOSEL_MASK) >> CMP_DACCR_VOSEL_SHIFT)
+#define CMP_BRD_DACCR_VOSEL(base) (CMP_RD_DACCR_VOSEL(base))
+
+/*! @brief Set the VOSEL field to a new value. */
+#define CMP_WR_DACCR_VOSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VOSEL_MASK, CMP_DACCR_VOSEL(value)))
+#define CMP_BWR_DACCR_VOSEL(base, value) (CMP_WR_DACCR_VOSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field VRSEL[6] (RW)
+ *
+ * Values:
+ * - 0b0 - V is selected as resistor ladder network supply reference V. in1 in
+ * - 0b1 - V is selected as resistor ladder network supply reference V. in2 in
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VRSEL field. */
+#define CMP_RD_DACCR_VRSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VRSEL_MASK) >> CMP_DACCR_VRSEL_SHIFT)
+#define CMP_BRD_DACCR_VRSEL(base) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT))
+
+/*! @brief Set the VRSEL field to a new value. */
+#define CMP_WR_DACCR_VRSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VRSEL_MASK, CMP_DACCR_VRSEL(value)))
+#define CMP_BWR_DACCR_VRSEL(base, value) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field DACEN[7] (RW)
+ *
+ * Enables the DAC. When the DAC is disabled, it is powered down to conserve
+ * power.
+ *
+ * Values:
+ * - 0b0 - DAC is disabled.
+ * - 0b1 - DAC is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_DACEN field. */
+#define CMP_RD_DACCR_DACEN(base) ((CMP_DACCR_REG(base) & CMP_DACCR_DACEN_MASK) >> CMP_DACCR_DACEN_SHIFT)
+#define CMP_BRD_DACCR_DACEN(base) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT))
+
+/*! @brief Set the DACEN field to a new value. */
+#define CMP_WR_DACCR_DACEN(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_DACEN_MASK, CMP_DACCR_DACEN(value)))
+#define CMP_BWR_DACCR_DACEN(base, value) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_MUXCR - MUX Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_MUXCR - MUX Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_MUXCR register
+ */
+/*@{*/
+#define CMP_RD_MUXCR(base)       (CMP_MUXCR_REG(base))
+#define CMP_WR_MUXCR(base, value) (CMP_MUXCR_REG(base) = (value))
+#define CMP_RMW_MUXCR(base, mask, value) (CMP_WR_MUXCR(base, (CMP_RD_MUXCR(base) & ~(mask)) | (value)))
+#define CMP_SET_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) |  (value)))
+#define CMP_CLR_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) & ~(value)))
+#define CMP_TOG_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_MUXCR bitfields
+ */
+
+/*!
+ * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
+ *
+ * Determines which input is selected for the minus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 0b000 - IN0
+ * - 0b001 - IN1
+ * - 0b010 - IN2
+ * - 0b011 - IN3
+ * - 0b100 - IN4
+ * - 0b101 - IN5
+ * - 0b110 - IN6
+ * - 0b111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_MSEL field. */
+#define CMP_RD_MUXCR_MSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_MSEL_MASK) >> CMP_MUXCR_MSEL_SHIFT)
+#define CMP_BRD_MUXCR_MSEL(base) (CMP_RD_MUXCR_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define CMP_WR_MUXCR_MSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_MSEL_MASK, CMP_MUXCR_MSEL(value)))
+#define CMP_BWR_MUXCR_MSEL(base, value) (CMP_WR_MUXCR_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
+ *
+ * Determines which input is selected for the plus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 0b000 - IN0
+ * - 0b001 - IN1
+ * - 0b010 - IN2
+ * - 0b011 - IN3
+ * - 0b100 - IN4
+ * - 0b101 - IN5
+ * - 0b110 - IN6
+ * - 0b111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSEL field. */
+#define CMP_RD_MUXCR_PSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSEL_MASK) >> CMP_MUXCR_PSEL_SHIFT)
+#define CMP_BRD_MUXCR_PSEL(base) (CMP_RD_MUXCR_PSEL(base))
+
+/*! @brief Set the PSEL field to a new value. */
+#define CMP_WR_MUXCR_PSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSEL_MASK, CMP_MUXCR_PSEL(value)))
+#define CMP_BWR_MUXCR_PSEL(base, value) (CMP_WR_MUXCR_PSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSTM[7] (RW)
+ *
+ * This bit is used to enable to MUX pass through mode. Pass through mode is
+ * always available but for some devices this feature must be always disabled due to
+ * the lack of package pins.
+ *
+ * Values:
+ * - 0b0 - Pass Through Mode is disabled.
+ * - 0b1 - Pass Through Mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSTM field. */
+#define CMP_RD_MUXCR_PSTM(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSTM_MASK) >> CMP_MUXCR_PSTM_SHIFT)
+#define CMP_BRD_MUXCR_PSTM(base) (BITBAND_ACCESS8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT))
+
+/*! @brief Set the PSTM field to a new value. */
+#define CMP_WR_MUXCR_PSTM(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSTM_MASK, CMP_MUXCR_PSTM(value)))
+#define CMP_BWR_MUXCR_PSTM(base, value) (BITBAND_ACCESS8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CMT
+ *
+ * Carrier Modulator Transmitter
+ *
+ * Registers defined in this header file:
+ * - CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ * - CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ * - CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ * - CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ * - CMT_OC - CMT Output Control Register
+ * - CMT_MSC - CMT Modulator Status and Control Register
+ * - CMT_CMD1 - CMT Modulator Data Register Mark High
+ * - CMT_CMD2 - CMT Modulator Data Register Mark Low
+ * - CMT_CMD3 - CMT Modulator Data Register Space High
+ * - CMT_CMD4 - CMT Modulator Data Register Space Low
+ * - CMT_PPS - CMT Primary Prescaler Register
+ * - CMT_DMA - CMT Direct Memory Access Register
+ */
+
+#define CMT_INSTANCE_COUNT (1U) /*!< Number of instances of the CMT module. */
+#define CMT_IDX (0U) /*!< Instance number for CMT. */
+
+/*******************************************************************************
+ * CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary high value for generating the carrier
+ * output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGH1 register
+ */
+/*@{*/
+#define CMT_RD_CGH1(base)        (CMT_CGH1_REG(base))
+#define CMT_WR_CGH1(base, value) (CMT_CGH1_REG(base) = (value))
+#define CMT_RMW_CGH1(base, mask, value) (CMT_WR_CGH1(base, (CMT_RD_CGH1(base) & ~(mask)) | (value)))
+#define CMT_SET_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) |  (value)))
+#define CMT_CLR_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) & ~(value)))
+#define CMT_TOG_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary low value for generating the carrier
+ * output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGL1 register
+ */
+/*@{*/
+#define CMT_RD_CGL1(base)        (CMT_CGL1_REG(base))
+#define CMT_WR_CGL1(base, value) (CMT_CGL1_REG(base) = (value))
+#define CMT_RMW_CGL1(base, mask, value) (CMT_WR_CGL1(base, (CMT_RD_CGL1(base) & ~(mask)) | (value)))
+#define CMT_SET_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) |  (value)))
+#define CMT_CLR_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) & ~(value)))
+#define CMT_TOG_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary high value for generating the
+ * carrier output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGH2 register
+ */
+/*@{*/
+#define CMT_RD_CGH2(base)        (CMT_CGH2_REG(base))
+#define CMT_WR_CGH2(base, value) (CMT_CGH2_REG(base) = (value))
+#define CMT_RMW_CGH2(base, mask, value) (CMT_WR_CGH2(base, (CMT_RD_CGH2(base) & ~(mask)) | (value)))
+#define CMT_SET_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) |  (value)))
+#define CMT_CLR_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) & ~(value)))
+#define CMT_TOG_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary low value for generating the
+ * carrier output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGL2 register
+ */
+/*@{*/
+#define CMT_RD_CGL2(base)        (CMT_CGL2_REG(base))
+#define CMT_WR_CGL2(base, value) (CMT_CGL2_REG(base) = (value))
+#define CMT_RMW_CGL2(base, mask, value) (CMT_WR_CGL2(base, (CMT_RD_CGL2(base) & ~(mask)) | (value)))
+#define CMT_SET_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) |  (value)))
+#define CMT_CLR_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) & ~(value)))
+#define CMT_TOG_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_OC - CMT Output Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_OC - CMT Output Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to control the IRO signal of the CMT module.
+ */
+/*!
+ * @name Constants and macros for entire CMT_OC register
+ */
+/*@{*/
+#define CMT_RD_OC(base)          (CMT_OC_REG(base))
+#define CMT_WR_OC(base, value)   (CMT_OC_REG(base) = (value))
+#define CMT_RMW_OC(base, mask, value) (CMT_WR_OC(base, (CMT_RD_OC(base) & ~(mask)) | (value)))
+#define CMT_SET_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) |  (value)))
+#define CMT_CLR_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) & ~(value)))
+#define CMT_TOG_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_OC bitfields
+ */
+
+/*!
+ * @name Register CMT_OC, field IROPEN[5] (RW)
+ *
+ * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
+ * output that drives out either the CMT transmitter output or the state of IROL
+ * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
+ * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
+ * signal is disabled, it is in a high-impedance state and is unable to draw any
+ * current. This signal is disabled during reset.
+ *
+ * Values:
+ * - 0b0 - The IRO signal is disabled.
+ * - 0b1 - The IRO signal is enabled as output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_IROPEN field. */
+#define CMT_RD_OC_IROPEN(base) ((CMT_OC_REG(base) & CMT_OC_IROPEN_MASK) >> CMT_OC_IROPEN_SHIFT)
+#define CMT_BRD_OC_IROPEN(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT))
+
+/*! @brief Set the IROPEN field to a new value. */
+#define CMT_WR_OC_IROPEN(base, value) (CMT_RMW_OC(base, CMT_OC_IROPEN_MASK, CMT_OC_IROPEN(value)))
+#define CMT_BWR_OC_IROPEN(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_OC, field CMTPOL[6] (RW)
+ *
+ * Controls the polarity of the IRO signal.
+ *
+ * Values:
+ * - 0b0 - The IRO signal is active-low.
+ * - 0b1 - The IRO signal is active-high.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_CMTPOL field. */
+#define CMT_RD_OC_CMTPOL(base) ((CMT_OC_REG(base) & CMT_OC_CMTPOL_MASK) >> CMT_OC_CMTPOL_SHIFT)
+#define CMT_BRD_OC_CMTPOL(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT))
+
+/*! @brief Set the CMTPOL field to a new value. */
+#define CMT_WR_OC_CMTPOL(base, value) (CMT_RMW_OC(base, CMT_OC_CMTPOL_MASK, CMT_OC_CMTPOL(value)))
+#define CMT_BWR_OC_CMTPOL(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_OC, field IROL[7] (RW)
+ *
+ * Reads the state of the IRO latch. Writing to IROL changes the state of the
+ * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_IROL field. */
+#define CMT_RD_OC_IROL(base) ((CMT_OC_REG(base) & CMT_OC_IROL_MASK) >> CMT_OC_IROL_SHIFT)
+#define CMT_BRD_OC_IROL(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT))
+
+/*! @brief Set the IROL field to a new value. */
+#define CMT_WR_OC_IROL(base, value) (CMT_RMW_OC(base, CMT_OC_IROL_MASK, CMT_OC_IROL(value)))
+#define CMT_BWR_OC_IROL(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_MSC - CMT Modulator Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_MSC - CMT Modulator Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the modulator and carrier generator enable (MCGEN),
+ * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
+ * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
+ * (EOCF) status bit.
+ */
+/*!
+ * @name Constants and macros for entire CMT_MSC register
+ */
+/*@{*/
+#define CMT_RD_MSC(base)         (CMT_MSC_REG(base))
+#define CMT_WR_MSC(base, value)  (CMT_MSC_REG(base) = (value))
+#define CMT_RMW_MSC(base, mask, value) (CMT_WR_MSC(base, (CMT_RD_MSC(base) & ~(mask)) | (value)))
+#define CMT_SET_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) |  (value)))
+#define CMT_CLR_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) & ~(value)))
+#define CMT_TOG_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_MSC bitfields
+ */
+
+/*!
+ * @name Register CMT_MSC, field MCGEN[0] (RW)
+ *
+ * Setting MCGEN will initialize the carrier generator and modulator and will
+ * enable all clocks. When enabled, the carrier generator and modulator will
+ * function continuously. When MCGEN is cleared, the current modulator cycle will be
+ * allowed to expire before all carrier and modulator clocks are disabled to save
+ * power and the modulator output is forced low. To prevent spurious operation,
+ * the user should initialize all data and control registers before enabling the
+ * system.
+ *
+ * Values:
+ * - 0b0 - Modulator and carrier generator disabled
+ * - 0b1 - Modulator and carrier generator enabled
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_MCGEN field. */
+#define CMT_RD_MSC_MCGEN(base) ((CMT_MSC_REG(base) & CMT_MSC_MCGEN_MASK) >> CMT_MSC_MCGEN_SHIFT)
+#define CMT_BRD_MSC_MCGEN(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT))
+
+/*! @brief Set the MCGEN field to a new value. */
+#define CMT_WR_MSC_MCGEN(base, value) (CMT_RMW_MSC(base, CMT_MSC_MCGEN_MASK, CMT_MSC_MCGEN(value)))
+#define CMT_BWR_MSC_MCGEN(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EOCIE[1] (RW)
+ *
+ * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
+ *
+ * Values:
+ * - 0b0 - CPU interrupt is disabled.
+ * - 0b1 - CPU interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EOCIE field. */
+#define CMT_RD_MSC_EOCIE(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCIE_MASK) >> CMT_MSC_EOCIE_SHIFT)
+#define CMT_BRD_MSC_EOCIE(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT))
+
+/*! @brief Set the EOCIE field to a new value. */
+#define CMT_WR_MSC_EOCIE(base, value) (CMT_RMW_MSC(base, CMT_MSC_EOCIE_MASK, CMT_MSC_EOCIE(value)))
+#define CMT_BWR_MSC_EOCIE(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field FSK[2] (RW)
+ *
+ * Enables FSK operation.
+ *
+ * Values:
+ * - 0b0 - The CMT operates in Time or Baseband mode.
+ * - 0b1 - The CMT operates in FSK mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_FSK field. */
+#define CMT_RD_MSC_FSK(base) ((CMT_MSC_REG(base) & CMT_MSC_FSK_MASK) >> CMT_MSC_FSK_SHIFT)
+#define CMT_BRD_MSC_FSK(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT))
+
+/*! @brief Set the FSK field to a new value. */
+#define CMT_WR_MSC_FSK(base, value) (CMT_RMW_MSC(base, CMT_MSC_FSK_MASK, CMT_MSC_FSK(value)))
+#define CMT_BWR_MSC_FSK(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field BASE[3] (RW)
+ *
+ * When set, BASE disables the carrier generator and forces the carrier output
+ * high for generation of baseband protocols. When BASE is cleared, the carrier
+ * generator is enabled and the carrier output toggles at the frequency determined
+ * by values stored in the carrier data registers. This field is cleared by
+ * reset. This field is not double-buffered and must not be written to during a
+ * transmission.
+ *
+ * Values:
+ * - 0b0 - Baseband mode is disabled.
+ * - 0b1 - Baseband mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_BASE field. */
+#define CMT_RD_MSC_BASE(base) ((CMT_MSC_REG(base) & CMT_MSC_BASE_MASK) >> CMT_MSC_BASE_SHIFT)
+#define CMT_BRD_MSC_BASE(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT))
+
+/*! @brief Set the BASE field to a new value. */
+#define CMT_WR_MSC_BASE(base, value) (CMT_RMW_MSC(base, CMT_MSC_BASE_MASK, CMT_MSC_BASE(value)))
+#define CMT_BWR_MSC_BASE(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EXSPC[4] (RW)
+ *
+ * Enables the extended space operation.
+ *
+ * Values:
+ * - 0b0 - Extended space is disabled.
+ * - 0b1 - Extended space is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EXSPC field. */
+#define CMT_RD_MSC_EXSPC(base) ((CMT_MSC_REG(base) & CMT_MSC_EXSPC_MASK) >> CMT_MSC_EXSPC_SHIFT)
+#define CMT_BRD_MSC_EXSPC(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT))
+
+/*! @brief Set the EXSPC field to a new value. */
+#define CMT_WR_MSC_EXSPC(base, value) (CMT_RMW_MSC(base, CMT_MSC_EXSPC_MASK, CMT_MSC_EXSPC(value)))
+#define CMT_BWR_MSC_EXSPC(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
+ *
+ * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
+ * divided by 2 ,4, or 8 . This field must not be changed during a transmission
+ * because it is not double-buffered.
+ *
+ * Values:
+ * - 0b00 - IF * 1
+ * - 0b01 - IF * 2
+ * - 0b10 - IF * 4
+ * - 0b11 - IF * 8
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_CMTDIV field. */
+#define CMT_RD_MSC_CMTDIV(base) ((CMT_MSC_REG(base) & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT)
+#define CMT_BRD_MSC_CMTDIV(base) (CMT_RD_MSC_CMTDIV(base))
+
+/*! @brief Set the CMTDIV field to a new value. */
+#define CMT_WR_MSC_CMTDIV(base, value) (CMT_RMW_MSC(base, CMT_MSC_CMTDIV_MASK, CMT_MSC_CMTDIV(value)))
+#define CMT_BWR_MSC_CMTDIV(base, value) (CMT_WR_MSC_CMTDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EOCF[7] (RO)
+ *
+ * Sets when: The modulator is not currently active and MCGEN is set to begin
+ * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
+ * set. This is recognized when a match occurs between the contents of the space
+ * period register and the down counter. At this time, the counter is
+ * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
+ * the space period register is loaded with, possibly new contents of the space
+ * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
+ * access of CMD2 or CMD4, or by the DMA transfer.
+ *
+ * Values:
+ * - 0b0 - End of modulation cycle has not occured since the flag last cleared.
+ * - 0b1 - End of modulator cycle has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EOCF field. */
+#define CMT_RD_MSC_EOCF(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCF_MASK) >> CMT_MSC_EOCF_SHIFT)
+#define CMT_BRD_MSC_EOCF(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD1 - CMT Modulator Data Register Mark High
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD1 register
+ */
+/*@{*/
+#define CMT_RD_CMD1(base)        (CMT_CMD1_REG(base))
+#define CMT_WR_CMD1(base, value) (CMT_CMD1_REG(base) = (value))
+#define CMT_RMW_CMD1(base, mask, value) (CMT_WR_CMD1(base, (CMT_RD_CMD1(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) |  (value)))
+#define CMT_CLR_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) & ~(value)))
+#define CMT_TOG_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD2 - CMT Modulator Data Register Mark Low
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD2 register
+ */
+/*@{*/
+#define CMT_RD_CMD2(base)        (CMT_CMD2_REG(base))
+#define CMT_WR_CMD2(base, value) (CMT_CMD2_REG(base) = (value))
+#define CMT_RMW_CMD2(base, mask, value) (CMT_WR_CMD2(base, (CMT_RD_CMD2(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) |  (value)))
+#define CMT_CLR_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) & ~(value)))
+#define CMT_TOG_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD3 - CMT Modulator Data Register Space High
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD3 - CMT Modulator Data Register Space High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD3 register
+ */
+/*@{*/
+#define CMT_RD_CMD3(base)        (CMT_CMD3_REG(base))
+#define CMT_WR_CMD3(base, value) (CMT_CMD3_REG(base) = (value))
+#define CMT_RMW_CMD3(base, mask, value) (CMT_WR_CMD3(base, (CMT_RD_CMD3(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) |  (value)))
+#define CMT_CLR_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) & ~(value)))
+#define CMT_TOG_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD4 - CMT Modulator Data Register Space Low
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD4 register
+ */
+/*@{*/
+#define CMT_RD_CMD4(base)        (CMT_CMD4_REG(base))
+#define CMT_WR_CMD4(base, value) (CMT_CMD4_REG(base) = (value))
+#define CMT_RMW_CMD4(base, mask, value) (CMT_WR_CMD4(base, (CMT_RD_CMD4(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) |  (value)))
+#define CMT_CLR_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) & ~(value)))
+#define CMT_TOG_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_PPS - CMT Primary Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_PPS - CMT Primary Prescaler Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to set the Primary Prescaler Divider field (PPSDIV).
+ */
+/*!
+ * @name Constants and macros for entire CMT_PPS register
+ */
+/*@{*/
+#define CMT_RD_PPS(base)         (CMT_PPS_REG(base))
+#define CMT_WR_PPS(base, value)  (CMT_PPS_REG(base) = (value))
+#define CMT_RMW_PPS(base, mask, value) (CMT_WR_PPS(base, (CMT_RD_PPS(base) & ~(mask)) | (value)))
+#define CMT_SET_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) |  (value)))
+#define CMT_CLR_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) & ~(value)))
+#define CMT_TOG_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_PPS bitfields
+ */
+
+/*!
+ * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
+ *
+ * Divides the CMT clock to generate the Intermediate Frequency clock enable to
+ * the secondary prescaler.
+ *
+ * Values:
+ * - 0b0000 - Bus clock * 1
+ * - 0b0001 - Bus clock * 2
+ * - 0b0010 - Bus clock * 3
+ * - 0b0011 - Bus clock * 4
+ * - 0b0100 - Bus clock * 5
+ * - 0b0101 - Bus clock * 6
+ * - 0b0110 - Bus clock * 7
+ * - 0b0111 - Bus clock * 8
+ * - 0b1000 - Bus clock * 9
+ * - 0b1001 - Bus clock * 10
+ * - 0b1010 - Bus clock * 11
+ * - 0b1011 - Bus clock * 12
+ * - 0b1100 - Bus clock * 13
+ * - 0b1101 - Bus clock * 14
+ * - 0b1110 - Bus clock * 15
+ * - 0b1111 - Bus clock * 16
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_PPS_PPSDIV field. */
+#define CMT_RD_PPS_PPSDIV(base) ((CMT_PPS_REG(base) & CMT_PPS_PPSDIV_MASK) >> CMT_PPS_PPSDIV_SHIFT)
+#define CMT_BRD_PPS_PPSDIV(base) (CMT_RD_PPS_PPSDIV(base))
+
+/*! @brief Set the PPSDIV field to a new value. */
+#define CMT_WR_PPS_PPSDIV(base, value) (CMT_RMW_PPS(base, CMT_PPS_PPSDIV_MASK, CMT_PPS_PPSDIV(value)))
+#define CMT_BWR_PPS_PPSDIV(base, value) (CMT_WR_PPS_PPSDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_DMA - CMT Direct Memory Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_DMA - CMT Direct Memory Access Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to enable/disable direct memory access (DMA).
+ */
+/*!
+ * @name Constants and macros for entire CMT_DMA register
+ */
+/*@{*/
+#define CMT_RD_DMA(base)         (CMT_DMA_REG(base))
+#define CMT_WR_DMA(base, value)  (CMT_DMA_REG(base) = (value))
+#define CMT_RMW_DMA(base, mask, value) (CMT_WR_DMA(base, (CMT_RD_DMA(base) & ~(mask)) | (value)))
+#define CMT_SET_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) |  (value)))
+#define CMT_CLR_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) & ~(value)))
+#define CMT_TOG_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_DMA bitfields
+ */
+
+/*!
+ * @name Register CMT_DMA, field DMA[0] (RW)
+ *
+ * Enables the DMA protocol.
+ *
+ * Values:
+ * - 0b0 - DMA transfer request and done are disabled.
+ * - 0b1 - DMA transfer request and done are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_DMA_DMA field. */
+#define CMT_RD_DMA_DMA(base) ((CMT_DMA_REG(base) & CMT_DMA_DMA_MASK) >> CMT_DMA_DMA_SHIFT)
+#define CMT_BRD_DMA_DMA(base) (BITBAND_ACCESS8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define CMT_WR_DMA_DMA(base, value) (CMT_RMW_DMA(base, CMT_DMA_DMA_MASK, CMT_DMA_DMA(value)))
+#define CMT_BWR_DMA_DMA(base, value) (BITBAND_ACCESS8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CRC
+ *
+ * Cyclic Redundancy Check
+ *
+ * Registers defined in this header file:
+ * - CRC_DATAL - CRC_DATAL register.
+ * - CRC_DATAH - CRC_DATAH register.
+ * - CRC_DATALL - CRC_DATALL register.
+ * - CRC_DATALU - CRC_DATALU register.
+ * - CRC_DATAHL - CRC_DATAHL register.
+ * - CRC_DATAHU - CRC_DATAHU register.
+ * - CRC_DATA - CRC Data register
+ * - CRC_GPOLY - CRC Polynomial register
+ * - CRC_GPOLYL - CRC_GPOLYL register.
+ * - CRC_GPOLYH - CRC_GPOLYH register.
+ * - CRC_GPOLYLL - CRC_GPOLYLL register.
+ * - CRC_GPOLYLU - CRC_GPOLYLU register.
+ * - CRC_GPOLYHL - CRC_GPOLYHL register.
+ * - CRC_GPOLYHU - CRC_GPOLYHU register.
+ * - CRC_CTRL - CRC Control register
+ * - CRC_CTRLHU - CRC_CTRLHU register.
+ */
+
+#define CRC_INSTANCE_COUNT (1U) /*!< Number of instances of the CRC module. */
+#define CRC_IDX (0U) /*!< Instance number for CRC. */
+
+/*******************************************************************************
+ * CRC_DATALL - CRC_DATALL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATALL - CRC_DATALL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATALL register
+ */
+/*@{*/
+#define CRC_RD_DATALL(base)      (CRC_DATALL_REG(base))
+#define CRC_WR_DATALL(base, value) (CRC_DATALL_REG(base) = (value))
+#define CRC_RMW_DATALL(base, mask, value) (CRC_WR_DATALL(base, (CRC_RD_DATALL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) |  (value)))
+#define CRC_CLR_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) & ~(value)))
+#define CRC_TOG_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAL - CRC_DATAL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAL - CRC_DATAL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAL register
+ */
+/*@{*/
+#define CRC_RD_DATAL(base)       (CRC_DATAL_REG(base))
+#define CRC_WR_DATAL(base, value) (CRC_DATAL_REG(base) = (value))
+#define CRC_RMW_DATAL(base, mask, value) (CRC_WR_DATAL(base, (CRC_RD_DATAL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) |  (value)))
+#define CRC_CLR_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) & ~(value)))
+#define CRC_TOG_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATA - CRC Data register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATA - CRC Data register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * The CRC Data register contains the value of the seed, data, and checksum.
+ * When CTRL[WAS] is set, any write to the data register is regarded as the seed
+ * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
+ * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
+ * not used for programming the seed value, and reads of these fields return an
+ * indeterminate value. In 32-bit CRC mode, all fields are used for programming
+ * the seed value. When programming data values, the values can be written 8 bits,
+ * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
+ * data value written first. After all data values are written, the CRC result
+ * can be read from this data register. In 16-bit CRC mode, the CRC result is
+ * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
+ * result. Reads of this register at any time return the intermediate CRC value,
+ * provided the CRC module is configured.
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATA register
+ */
+/*@{*/
+#define CRC_RD_DATA(base)        (CRC_DATA_REG(base))
+#define CRC_WR_DATA(base, value) (CRC_DATA_REG(base) = (value))
+#define CRC_RMW_DATA(base, mask, value) (CRC_WR_DATA(base, (CRC_RD_DATA(base) & ~(mask)) | (value)))
+#define CRC_SET_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) |  (value)))
+#define CRC_CLR_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) & ~(value)))
+#define CRC_TOG_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_DATA bitfields
+ */
+
+/*!
+ * @name Register CRC_DATA, field LL[7:0] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_LL field. */
+#define CRC_RD_DATA_LL(base) ((CRC_DATA_REG(base) & CRC_DATA_LL_MASK) >> CRC_DATA_LL_SHIFT)
+#define CRC_BRD_DATA_LL(base) (CRC_RD_DATA_LL(base))
+
+/*! @brief Set the LL field to a new value. */
+#define CRC_WR_DATA_LL(base, value) (CRC_RMW_DATA(base, CRC_DATA_LL_MASK, CRC_DATA_LL(value)))
+#define CRC_BWR_DATA_LL(base, value) (CRC_WR_DATA_LL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field LU[15:8] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_LU field. */
+#define CRC_RD_DATA_LU(base) ((CRC_DATA_REG(base) & CRC_DATA_LU_MASK) >> CRC_DATA_LU_SHIFT)
+#define CRC_BRD_DATA_LU(base) (CRC_RD_DATA_LU(base))
+
+/*! @brief Set the LU field to a new value. */
+#define CRC_WR_DATA_LU(base, value) (CRC_RMW_DATA(base, CRC_DATA_LU_MASK, CRC_DATA_LU(value)))
+#define CRC_BWR_DATA_LU(base, value) (CRC_WR_DATA_LU(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field HL[23:16] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_HL field. */
+#define CRC_RD_DATA_HL(base) ((CRC_DATA_REG(base) & CRC_DATA_HL_MASK) >> CRC_DATA_HL_SHIFT)
+#define CRC_BRD_DATA_HL(base) (CRC_RD_DATA_HL(base))
+
+/*! @brief Set the HL field to a new value. */
+#define CRC_WR_DATA_HL(base, value) (CRC_RMW_DATA(base, CRC_DATA_HL_MASK, CRC_DATA_HL(value)))
+#define CRC_BWR_DATA_HL(base, value) (CRC_WR_DATA_HL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field HU[31:24] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_HU field. */
+#define CRC_RD_DATA_HU(base) ((CRC_DATA_REG(base) & CRC_DATA_HU_MASK) >> CRC_DATA_HU_SHIFT)
+#define CRC_BRD_DATA_HU(base) (CRC_RD_DATA_HU(base))
+
+/*! @brief Set the HU field to a new value. */
+#define CRC_WR_DATA_HU(base, value) (CRC_RMW_DATA(base, CRC_DATA_HU_MASK, CRC_DATA_HU(value)))
+#define CRC_BWR_DATA_HU(base, value) (CRC_WR_DATA_HU(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATALU - CRC_DATALU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATALU - CRC_DATALU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATALU register
+ */
+/*@{*/
+#define CRC_RD_DATALU(base)      (CRC_DATALU_REG(base))
+#define CRC_WR_DATALU(base, value) (CRC_DATALU_REG(base) = (value))
+#define CRC_RMW_DATALU(base, mask, value) (CRC_WR_DATALU(base, (CRC_RD_DATALU(base) & ~(mask)) | (value)))
+#define CRC_SET_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) |  (value)))
+#define CRC_CLR_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) & ~(value)))
+#define CRC_TOG_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAHL - CRC_DATAHL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAHL - CRC_DATAHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAHL register
+ */
+/*@{*/
+#define CRC_RD_DATAHL(base)      (CRC_DATAHL_REG(base))
+#define CRC_WR_DATAHL(base, value) (CRC_DATAHL_REG(base) = (value))
+#define CRC_RMW_DATAHL(base, mask, value) (CRC_WR_DATAHL(base, (CRC_RD_DATAHL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) |  (value)))
+#define CRC_CLR_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) & ~(value)))
+#define CRC_TOG_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAH - CRC_DATAH register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAH - CRC_DATAH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAH register
+ */
+/*@{*/
+#define CRC_RD_DATAH(base)       (CRC_DATAH_REG(base))
+#define CRC_WR_DATAH(base, value) (CRC_DATAH_REG(base) = (value))
+#define CRC_RMW_DATAH(base, mask, value) (CRC_WR_DATAH(base, (CRC_RD_DATAH(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) |  (value)))
+#define CRC_CLR_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) & ~(value)))
+#define CRC_TOG_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAHU - CRC_DATAHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAHU - CRC_DATAHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAHU register
+ */
+/*@{*/
+#define CRC_RD_DATAHU(base)      (CRC_DATAHU_REG(base))
+#define CRC_WR_DATAHU(base, value) (CRC_DATAHU_REG(base) = (value))
+#define CRC_RMW_DATAHU(base, mask, value) (CRC_WR_DATAHU(base, (CRC_RD_DATAHU(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) |  (value)))
+#define CRC_CLR_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) & ~(value)))
+#define CRC_TOG_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYLL - CRC_GPOLYLL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYLL(base)     (CRC_GPOLYLL_REG(base))
+#define CRC_WR_GPOLYLL(base, value) (CRC_GPOLYLL_REG(base) = (value))
+#define CRC_RMW_GPOLYLL(base, mask, value) (CRC_WR_GPOLYLL(base, (CRC_RD_GPOLYLL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) |  (value)))
+#define CRC_CLR_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) & ~(value)))
+#define CRC_TOG_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLY - CRC Polynomial register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLY - CRC Polynomial register (RW)
+ *
+ * Reset value: 0x00001021U
+ *
+ * This register contains the value of the polynomial for the CRC calculation.
+ * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
+ * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
+ * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
+ * used in both 16- and 32-bit CRC modes.
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLY register
+ */
+/*@{*/
+#define CRC_RD_GPOLY(base)       (CRC_GPOLY_REG(base))
+#define CRC_WR_GPOLY(base, value) (CRC_GPOLY_REG(base) = (value))
+#define CRC_RMW_GPOLY(base, mask, value) (CRC_WR_GPOLY(base, (CRC_RD_GPOLY(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) |  (value)))
+#define CRC_CLR_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) & ~(value)))
+#define CRC_TOG_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_GPOLY bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLY, field LOW[15:0] (RW)
+ *
+ * Writable and readable in both 32-bit and 16-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_GPOLY_LOW field. */
+#define CRC_RD_GPOLY_LOW(base) ((CRC_GPOLY_REG(base) & CRC_GPOLY_LOW_MASK) >> CRC_GPOLY_LOW_SHIFT)
+#define CRC_BRD_GPOLY_LOW(base) (CRC_RD_GPOLY_LOW(base))
+
+/*! @brief Set the LOW field to a new value. */
+#define CRC_WR_GPOLY_LOW(base, value) (CRC_RMW_GPOLY(base, CRC_GPOLY_LOW_MASK, CRC_GPOLY_LOW(value)))
+#define CRC_BWR_GPOLY_LOW(base, value) (CRC_WR_GPOLY_LOW(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
+ *
+ * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
+ * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_GPOLY_HIGH field. */
+#define CRC_RD_GPOLY_HIGH(base) ((CRC_GPOLY_REG(base) & CRC_GPOLY_HIGH_MASK) >> CRC_GPOLY_HIGH_SHIFT)
+#define CRC_BRD_GPOLY_HIGH(base) (CRC_RD_GPOLY_HIGH(base))
+
+/*! @brief Set the HIGH field to a new value. */
+#define CRC_WR_GPOLY_HIGH(base, value) (CRC_RMW_GPOLY(base, CRC_GPOLY_HIGH_MASK, CRC_GPOLY_HIGH(value)))
+#define CRC_BWR_GPOLY_HIGH(base, value) (CRC_WR_GPOLY_HIGH(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYL - CRC_GPOLYL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYL - CRC_GPOLYL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYL(base)      (CRC_GPOLYL_REG(base))
+#define CRC_WR_GPOLYL(base, value) (CRC_GPOLYL_REG(base) = (value))
+#define CRC_RMW_GPOLYL(base, mask, value) (CRC_WR_GPOLYL(base, (CRC_RD_GPOLYL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) |  (value)))
+#define CRC_CLR_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) & ~(value)))
+#define CRC_TOG_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYLU - CRC_GPOLYLU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLU register
+ */
+/*@{*/
+#define CRC_RD_GPOLYLU(base)     (CRC_GPOLYLU_REG(base))
+#define CRC_WR_GPOLYLU(base, value) (CRC_GPOLYLU_REG(base) = (value))
+#define CRC_RMW_GPOLYLU(base, mask, value) (CRC_WR_GPOLYLU(base, (CRC_RD_GPOLYLU(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) |  (value)))
+#define CRC_CLR_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) & ~(value)))
+#define CRC_TOG_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYH - CRC_GPOLYH register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYH - CRC_GPOLYH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYH register
+ */
+/*@{*/
+#define CRC_RD_GPOLYH(base)      (CRC_GPOLYH_REG(base))
+#define CRC_WR_GPOLYH(base, value) (CRC_GPOLYH_REG(base) = (value))
+#define CRC_RMW_GPOLYH(base, mask, value) (CRC_WR_GPOLYH(base, (CRC_RD_GPOLYH(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) |  (value)))
+#define CRC_CLR_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) & ~(value)))
+#define CRC_TOG_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYHL - CRC_GPOLYHL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYHL(base)     (CRC_GPOLYHL_REG(base))
+#define CRC_WR_GPOLYHL(base, value) (CRC_GPOLYHL_REG(base) = (value))
+#define CRC_RMW_GPOLYHL(base, mask, value) (CRC_WR_GPOLYHL(base, (CRC_RD_GPOLYHL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) |  (value)))
+#define CRC_CLR_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) & ~(value)))
+#define CRC_TOG_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYHU - CRC_GPOLYHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHU register
+ */
+/*@{*/
+#define CRC_RD_GPOLYHU(base)     (CRC_GPOLYHU_REG(base))
+#define CRC_WR_GPOLYHU(base, value) (CRC_GPOLYHU_REG(base) = (value))
+#define CRC_RMW_GPOLYHU(base, mask, value) (CRC_WR_GPOLYHU(base, (CRC_RD_GPOLYHU(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) |  (value)))
+#define CRC_CLR_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) & ~(value)))
+#define CRC_TOG_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_CTRL - CRC Control register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_CTRL - CRC Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls the configuration and working of the CRC module.
+ * Appropriate bits must be set before starting a new CRC calculation. A new CRC
+ * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
+ * the CRC data register.
+ */
+/*!
+ * @name Constants and macros for entire CRC_CTRL register
+ */
+/*@{*/
+#define CRC_RD_CTRL(base)        (CRC_CTRL_REG(base))
+#define CRC_WR_CTRL(base, value) (CRC_CTRL_REG(base) = (value))
+#define CRC_RMW_CTRL(base, mask, value) (CRC_WR_CTRL(base, (CRC_RD_CTRL(base) & ~(mask)) | (value)))
+#define CRC_SET_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) |  (value)))
+#define CRC_CLR_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) & ~(value)))
+#define CRC_TOG_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_CTRL bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRL, field TCRC[24] (RW)
+ *
+ * Width of CRC protocol.
+ *
+ * Values:
+ * - 0b0 - 16-bit CRC protocol.
+ * - 0b1 - 32-bit CRC protocol.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TCRC field. */
+#define CRC_RD_CTRL_TCRC(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TCRC_MASK) >> CRC_CTRL_TCRC_SHIFT)
+#define CRC_BRD_CTRL_TCRC(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_TCRC_SHIFT))
+
+/*! @brief Set the TCRC field to a new value. */
+#define CRC_WR_CTRL_TCRC(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TCRC_MASK, CRC_CTRL_TCRC(value)))
+#define CRC_BWR_CTRL_TCRC(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_TCRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field WAS[25] (RW)
+ *
+ * When asserted, a value written to the CRC data register is considered a seed
+ * value. When deasserted, a value written to the CRC data register is taken as
+ * data for CRC computation.
+ *
+ * Values:
+ * - 0b0 - Writes to the CRC data register are data values.
+ * - 0b1 - Writes to the CRC data register are seed values.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_WAS field. */
+#define CRC_RD_CTRL_WAS(base) ((CRC_CTRL_REG(base) & CRC_CTRL_WAS_MASK) >> CRC_CTRL_WAS_SHIFT)
+#define CRC_BRD_CTRL_WAS(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_WAS_SHIFT))
+
+/*! @brief Set the WAS field to a new value. */
+#define CRC_WR_CTRL_WAS(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_WAS_MASK, CRC_CTRL_WAS(value)))
+#define CRC_BWR_CTRL_WAS(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_WAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field FXOR[26] (RW)
+ *
+ * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
+ * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
+ *
+ * Values:
+ * - 0b0 - No XOR on reading.
+ * - 0b1 - Invert or complement the read value of the CRC Data register.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_FXOR field. */
+#define CRC_RD_CTRL_FXOR(base) ((CRC_CTRL_REG(base) & CRC_CTRL_FXOR_MASK) >> CRC_CTRL_FXOR_SHIFT)
+#define CRC_BRD_CTRL_FXOR(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_FXOR_SHIFT))
+
+/*! @brief Set the FXOR field to a new value. */
+#define CRC_WR_CTRL_FXOR(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_FXOR_MASK, CRC_CTRL_FXOR(value)))
+#define CRC_BWR_CTRL_FXOR(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_FXOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field TOTR[29:28] (RW)
+ *
+ * Identifies the transpose configuration of the value read from the CRC Data
+ * register. See the description of the transpose feature for the available
+ * transpose options.
+ *
+ * Values:
+ * - 0b00 - No transposition.
+ * - 0b01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TOTR field. */
+#define CRC_RD_CTRL_TOTR(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT)
+#define CRC_BRD_CTRL_TOTR(base) (CRC_RD_CTRL_TOTR(base))
+
+/*! @brief Set the TOTR field to a new value. */
+#define CRC_WR_CTRL_TOTR(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TOTR_MASK, CRC_CTRL_TOTR(value)))
+#define CRC_BWR_CTRL_TOTR(base, value) (CRC_WR_CTRL_TOTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field TOT[31:30] (RW)
+ *
+ * Defines the transpose configuration of the data written to the CRC data
+ * register. See the description of the transpose feature for the available transpose
+ * options.
+ *
+ * Values:
+ * - 0b00 - No transposition.
+ * - 0b01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TOT field. */
+#define CRC_RD_CTRL_TOT(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TOT_MASK) >> CRC_CTRL_TOT_SHIFT)
+#define CRC_BRD_CTRL_TOT(base) (CRC_RD_CTRL_TOT(base))
+
+/*! @brief Set the TOT field to a new value. */
+#define CRC_WR_CTRL_TOT(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TOT_MASK, CRC_CTRL_TOT(value)))
+#define CRC_BWR_CTRL_TOT(base, value) (CRC_WR_CTRL_TOT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_CTRLHU - CRC_CTRLHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_CTRLHU - CRC_CTRLHU register. (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CRC_CTRLHU register
+ */
+/*@{*/
+#define CRC_RD_CTRLHU(base)      (CRC_CTRLHU_REG(base))
+#define CRC_WR_CTRLHU(base, value) (CRC_CTRLHU_REG(base) = (value))
+#define CRC_RMW_CTRLHU(base, mask, value) (CRC_WR_CTRLHU(base, (CRC_RD_CTRLHU(base) & ~(mask)) | (value)))
+#define CRC_SET_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) |  (value)))
+#define CRC_CLR_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) & ~(value)))
+#define CRC_TOG_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_CTRLHU bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRLHU, field TCRC[0] (RW)
+ *
+ * Values:
+ * - 0b0 - 16-bit CRC protocol.
+ * - 0b1 - 32-bit CRC protocol.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TCRC field. */
+#define CRC_RD_CTRLHU_TCRC(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TCRC_MASK) >> CRC_CTRLHU_TCRC_SHIFT)
+#define CRC_BRD_CTRLHU_TCRC(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_TCRC_SHIFT))
+
+/*! @brief Set the TCRC field to a new value. */
+#define CRC_WR_CTRLHU_TCRC(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TCRC_MASK, CRC_CTRLHU_TCRC(value)))
+#define CRC_BWR_CTRLHU_TCRC(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_TCRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field WAS[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Writes to CRC data register are data values.
+ * - 0b1 - Writes to CRC data reguster are seed values.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_WAS field. */
+#define CRC_RD_CTRLHU_WAS(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_WAS_MASK) >> CRC_CTRLHU_WAS_SHIFT)
+#define CRC_BRD_CTRLHU_WAS(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_WAS_SHIFT))
+
+/*! @brief Set the WAS field to a new value. */
+#define CRC_WR_CTRLHU_WAS(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_WAS_MASK, CRC_CTRLHU_WAS(value)))
+#define CRC_BWR_CTRLHU_WAS(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_WAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field FXOR[2] (RW)
+ *
+ * Values:
+ * - 0b0 - No XOR on reading.
+ * - 0b1 - Invert or complement the read value of CRC data register.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_FXOR field. */
+#define CRC_RD_CTRLHU_FXOR(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_FXOR_MASK) >> CRC_CTRLHU_FXOR_SHIFT)
+#define CRC_BRD_CTRLHU_FXOR(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_FXOR_SHIFT))
+
+/*! @brief Set the FXOR field to a new value. */
+#define CRC_WR_CTRLHU_FXOR(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_FXOR_MASK, CRC_CTRLHU_FXOR(value)))
+#define CRC_BWR_CTRLHU_FXOR(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_FXOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
+ *
+ * Values:
+ * - 0b00 - No Transposition.
+ * - 0b01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TOTR field. */
+#define CRC_RD_CTRLHU_TOTR(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TOTR_MASK) >> CRC_CTRLHU_TOTR_SHIFT)
+#define CRC_BRD_CTRLHU_TOTR(base) (CRC_RD_CTRLHU_TOTR(base))
+
+/*! @brief Set the TOTR field to a new value. */
+#define CRC_WR_CTRLHU_TOTR(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TOTR_MASK, CRC_CTRLHU_TOTR(value)))
+#define CRC_BWR_CTRLHU_TOTR(base, value) (CRC_WR_CTRLHU_TOTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
+ *
+ * Values:
+ * - 0b00 - No Transposition.
+ * - 0b01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TOT field. */
+#define CRC_RD_CTRLHU_TOT(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TOT_MASK) >> CRC_CTRLHU_TOT_SHIFT)
+#define CRC_BRD_CTRLHU_TOT(base) (CRC_RD_CTRLHU_TOT(base))
+
+/*! @brief Set the TOT field to a new value. */
+#define CRC_WR_CTRLHU_TOT(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TOT_MASK, CRC_CTRLHU_TOT(value)))
+#define CRC_BWR_CTRLHU_TOT(base, value) (CRC_WR_CTRLHU_TOT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 DAC
+ *
+ * 12-Bit Digital-to-Analog Converter
+ *
+ * Registers defined in this header file:
+ * - DAC_DATL - DAC Data Low Register
+ * - DAC_DATH - DAC Data High Register
+ * - DAC_SR - DAC Status Register
+ * - DAC_C0 - DAC Control Register
+ * - DAC_C1 - DAC Control Register 1
+ * - DAC_C2 - DAC Control Register 2
+ */
+
+#define DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
+#define DAC0_IDX (0U) /*!< Instance number for DAC0. */
+#define DAC1_IDX (1U) /*!< Instance number for DAC1. */
+
+/*******************************************************************************
+ * DAC_DATL - DAC Data Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATL - DAC Data Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATL register
+ */
+/*@{*/
+#define DAC_RD_DATL(base, index) (DAC_DATL_REG(base, index))
+#define DAC_WR_DATL(base, index, value) (DAC_DATL_REG(base, index) = (value))
+#define DAC_RMW_DATL(base, index, mask, value) (DAC_WR_DATL(base, index, (DAC_RD_DATL(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) |  (value)))
+#define DAC_CLR_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) & ~(value)))
+#define DAC_TOG_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_DATH - DAC Data High Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATH - DAC Data High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATH register
+ */
+/*@{*/
+#define DAC_RD_DATH(base, index) (DAC_DATH_REG(base, index))
+#define DAC_WR_DATH(base, index, value) (DAC_DATH_REG(base, index) = (value))
+#define DAC_RMW_DATH(base, index, mask, value) (DAC_WR_DATH(base, index, (DAC_RD_DATH(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) |  (value)))
+#define DAC_CLR_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) & ~(value)))
+#define DAC_TOG_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_DATH bitfields
+ */
+
+/*!
+ * @name Register DAC_DATH, field DATA1[3:0] (RW)
+ *
+ * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
+ * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
+ * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_DATH_DATA1 field. */
+#define DAC_RD_DATH_DATA1(base, index) ((DAC_DATH_REG(base, index) & DAC_DATH_DATA1_MASK) >> DAC_DATH_DATA1_SHIFT)
+#define DAC_BRD_DATH_DATA1(base, index) (DAC_RD_DATH_DATA1(base, index))
+
+/*! @brief Set the DATA1 field to a new value. */
+#define DAC_WR_DATH_DATA1(base, index, value) (DAC_RMW_DATH(base, index, DAC_DATH_DATA1_MASK, DAC_DATH_DATA1(value)))
+#define DAC_BWR_DATH_DATA1(base, index, value) (DAC_WR_DATH_DATA1(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_SR - DAC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_SR - DAC Status Register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
+ * request is done. Writing 0 to a field clears it whereas writing 1 has no
+ * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
+ * The flags are set only when the data buffer status is changed. Do not use
+ * 32/16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_SR register
+ */
+/*@{*/
+#define DAC_RD_SR(base)          (DAC_SR_REG(base))
+#define DAC_WR_SR(base, value)   (DAC_SR_REG(base) = (value))
+#define DAC_RMW_SR(base, mask, value) (DAC_WR_SR(base, (DAC_RD_SR(base) & ~(mask)) | (value)))
+#define DAC_SET_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) |  (value)))
+#define DAC_CLR_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) & ~(value)))
+#define DAC_TOG_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_SR bitfields
+ */
+
+/*!
+ * @name Register DAC_SR, field DACBFRPBF[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
+ * - 0b1 - The DAC buffer read pointer is equal to C2[DACBFUP].
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
+#define DAC_RD_SR_DACBFRPBF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPBF_MASK) >> DAC_SR_DACBFRPBF_SHIFT)
+#define DAC_BRD_SR_DACBFRPBF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT))
+
+/*! @brief Set the DACBFRPBF field to a new value. */
+#define DAC_WR_SR_DACBFRPBF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPBF_MASK, DAC_SR_DACBFRPBF(value)))
+#define DAC_BWR_SR_DACBFRPBF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFRPTF[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer is not zero.
+ * - 0b1 - The DAC buffer read pointer is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
+#define DAC_RD_SR_DACBFRPTF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPTF_MASK) >> DAC_SR_DACBFRPTF_SHIFT)
+#define DAC_BRD_SR_DACBFRPTF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT))
+
+/*! @brief Set the DACBFRPTF field to a new value. */
+#define DAC_WR_SR_DACBFRPTF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPTF_MASK, DAC_SR_DACBFRPTF(value)))
+#define DAC_BWR_SR_DACBFRPTF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFWMF[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer has not reached the watermark level.
+ * - 0b1 - The DAC buffer read pointer has reached the watermark level.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFWMF field. */
+#define DAC_RD_SR_DACBFWMF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFWMF_MASK) >> DAC_SR_DACBFWMF_SHIFT)
+#define DAC_BRD_SR_DACBFWMF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFWMF_SHIFT))
+
+/*! @brief Set the DACBFWMF field to a new value. */
+#define DAC_WR_SR_DACBFWMF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFWMF_MASK, DAC_SR_DACBFWMF(value)))
+#define DAC_BWR_SR_DACBFWMF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFWMF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C0 - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C0 - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_C0 register
+ */
+/*@{*/
+#define DAC_RD_C0(base)          (DAC_C0_REG(base))
+#define DAC_WR_C0(base, value)   (DAC_C0_REG(base) = (value))
+#define DAC_RMW_C0(base, mask, value) (DAC_WR_C0(base, (DAC_RD_C0(base) & ~(mask)) | (value)))
+#define DAC_SET_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) |  (value)))
+#define DAC_CLR_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) & ~(value)))
+#define DAC_TOG_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C0 bitfields
+ */
+
+/*!
+ * @name Register DAC_C0, field DACBBIEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer bottom flag interrupt is disabled.
+ * - 0b1 - The DAC buffer read pointer bottom flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBBIEN field. */
+#define DAC_RD_C0_DACBBIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBBIEN_MASK) >> DAC_C0_DACBBIEN_SHIFT)
+#define DAC_BRD_C0_DACBBIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT))
+
+/*! @brief Set the DACBBIEN field to a new value. */
+#define DAC_WR_C0_DACBBIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBBIEN_MASK, DAC_C0_DACBBIEN(value)))
+#define DAC_BWR_C0_DACBBIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBTIEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer top flag interrupt is disabled.
+ * - 0b1 - The DAC buffer read pointer top flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBTIEN field. */
+#define DAC_RD_C0_DACBTIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBTIEN_MASK) >> DAC_C0_DACBTIEN_SHIFT)
+#define DAC_BRD_C0_DACBTIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT))
+
+/*! @brief Set the DACBTIEN field to a new value. */
+#define DAC_WR_C0_DACBTIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBTIEN_MASK, DAC_C0_DACBTIEN(value)))
+#define DAC_BWR_C0_DACBTIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBWIEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer watermark interrupt is disabled.
+ * - 0b1 - The DAC buffer watermark interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBWIEN field. */
+#define DAC_RD_C0_DACBWIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBWIEN_MASK) >> DAC_C0_DACBWIEN_SHIFT)
+#define DAC_BRD_C0_DACBWIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBWIEN_SHIFT))
+
+/*! @brief Set the DACBWIEN field to a new value. */
+#define DAC_WR_C0_DACBWIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBWIEN_MASK, DAC_C0_DACBWIEN(value)))
+#define DAC_BWR_C0_DACBWIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBWIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field LPEN[3] (RW)
+ *
+ * See the 12-bit DAC electrical characteristics of the device data sheet for
+ * details on the impact of the modes below.
+ *
+ * Values:
+ * - 0b0 - High-Power mode
+ * - 0b1 - Low-Power mode
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_LPEN field. */
+#define DAC_RD_C0_LPEN(base) ((DAC_C0_REG(base) & DAC_C0_LPEN_MASK) >> DAC_C0_LPEN_SHIFT)
+#define DAC_BRD_C0_LPEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT))
+
+/*! @brief Set the LPEN field to a new value. */
+#define DAC_WR_C0_LPEN(base, value) (DAC_RMW_C0(base, DAC_C0_LPEN_MASK, DAC_C0_LPEN(value)))
+#define DAC_BWR_C0_LPEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
+ *
+ * Active high. This is a write-only field, which always reads 0. If DAC
+ * software trigger is selected and buffer is enabled, writing 1 to this field will
+ * advance the buffer read pointer once.
+ *
+ * Values:
+ * - 0b0 - The DAC soft trigger is not valid.
+ * - 0b1 - The DAC soft trigger is valid.
+ */
+/*@{*/
+/*! @brief Set the DACSWTRG field to a new value. */
+#define DAC_WR_C0_DACSWTRG(base, value) (DAC_RMW_C0(base, DAC_C0_DACSWTRG_MASK, DAC_C0_DACSWTRG(value)))
+#define DAC_BWR_C0_DACSWTRG(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACSWTRG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACTRGSEL[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC hardware trigger is selected.
+ * - 0b1 - The DAC software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
+#define DAC_RD_C0_DACTRGSEL(base) ((DAC_C0_REG(base) & DAC_C0_DACTRGSEL_MASK) >> DAC_C0_DACTRGSEL_SHIFT)
+#define DAC_BRD_C0_DACTRGSEL(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT))
+
+/*! @brief Set the DACTRGSEL field to a new value. */
+#define DAC_WR_C0_DACTRGSEL(base, value) (DAC_RMW_C0(base, DAC_C0_DACTRGSEL_MASK, DAC_C0_DACTRGSEL(value)))
+#define DAC_BWR_C0_DACTRGSEL(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACRFS[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC selects DACREF_1 as the reference voltage.
+ * - 0b1 - The DAC selects DACREF_2 as the reference voltage.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACRFS field. */
+#define DAC_RD_C0_DACRFS(base) ((DAC_C0_REG(base) & DAC_C0_DACRFS_MASK) >> DAC_C0_DACRFS_SHIFT)
+#define DAC_BRD_C0_DACRFS(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT))
+
+/*! @brief Set the DACRFS field to a new value. */
+#define DAC_WR_C0_DACRFS(base, value) (DAC_RMW_C0(base, DAC_C0_DACRFS_MASK, DAC_C0_DACRFS(value)))
+#define DAC_BWR_C0_DACRFS(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACEN[7] (RW)
+ *
+ * Starts the Programmable Reference Generator operation.
+ *
+ * Values:
+ * - 0b0 - The DAC system is disabled.
+ * - 0b1 - The DAC system is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACEN field. */
+#define DAC_RD_C0_DACEN(base) ((DAC_C0_REG(base) & DAC_C0_DACEN_MASK) >> DAC_C0_DACEN_SHIFT)
+#define DAC_BRD_C0_DACEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT))
+
+/*! @brief Set the DACEN field to a new value. */
+#define DAC_WR_C0_DACEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACEN_MASK, DAC_C0_DACEN(value)))
+#define DAC_BWR_C0_DACEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C1 - DAC Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C1 - DAC Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_C1 register
+ */
+/*@{*/
+#define DAC_RD_C1(base)          (DAC_C1_REG(base))
+#define DAC_WR_C1(base, value)   (DAC_C1_REG(base) = (value))
+#define DAC_RMW_C1(base, mask, value) (DAC_WR_C1(base, (DAC_RD_C1(base) & ~(mask)) | (value)))
+#define DAC_SET_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) |  (value)))
+#define DAC_CLR_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) & ~(value)))
+#define DAC_TOG_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C1 bitfields
+ */
+
+/*!
+ * @name Register DAC_C1, field DACBFEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Buffer read pointer is disabled. The converted data is always the
+ *     first word of the buffer.
+ * - 0b1 - Buffer read pointer is enabled. The converted data is the word that
+ *     the read pointer points to. It means converted data can be from any word of
+ *     the buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFEN field. */
+#define DAC_RD_C1_DACBFEN(base) ((DAC_C1_REG(base) & DAC_C1_DACBFEN_MASK) >> DAC_C1_DACBFEN_SHIFT)
+#define DAC_BRD_C1_DACBFEN(base) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT))
+
+/*! @brief Set the DACBFEN field to a new value. */
+#define DAC_WR_C1_DACBFEN(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFEN_MASK, DAC_C1_DACBFEN(value)))
+#define DAC_BWR_C1_DACBFEN(base, value) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFMD[2:1] (RW)
+ *
+ * Values:
+ * - 0b00 - Normal mode
+ * - 0b01 - Swing mode
+ * - 0b10 - One-Time Scan mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFMD field. */
+#define DAC_RD_C1_DACBFMD(base) ((DAC_C1_REG(base) & DAC_C1_DACBFMD_MASK) >> DAC_C1_DACBFMD_SHIFT)
+#define DAC_BRD_C1_DACBFMD(base) (DAC_RD_C1_DACBFMD(base))
+
+/*! @brief Set the DACBFMD field to a new value. */
+#define DAC_WR_C1_DACBFMD(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFMD_MASK, DAC_C1_DACBFMD(value)))
+#define DAC_BWR_C1_DACBFMD(base, value) (DAC_WR_C1_DACBFMD(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFWM[4:3] (RW)
+ *
+ * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
+ * the word defined by this field, which is 1-4 words away from the upper limit
+ * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
+ * watermark interrupt.
+ *
+ * Values:
+ * - 0b00 - 1 word
+ * - 0b01 - 2 words
+ * - 0b10 - 3 words
+ * - 0b11 - 4 words
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFWM field. */
+#define DAC_RD_C1_DACBFWM(base) ((DAC_C1_REG(base) & DAC_C1_DACBFWM_MASK) >> DAC_C1_DACBFWM_SHIFT)
+#define DAC_BRD_C1_DACBFWM(base) (DAC_RD_C1_DACBFWM(base))
+
+/*! @brief Set the DACBFWM field to a new value. */
+#define DAC_WR_C1_DACBFWM(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFWM_MASK, DAC_C1_DACBFWM(value)))
+#define DAC_BWR_C1_DACBFWM(base, value) (DAC_WR_C1_DACBFWM(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DMAEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled. When DMA is enabled, the DMA request will be
+ *     generated by original interrupts. The interrupts will not be presented on this
+ *     module at the same time.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DMAEN field. */
+#define DAC_RD_C1_DMAEN(base) ((DAC_C1_REG(base) & DAC_C1_DMAEN_MASK) >> DAC_C1_DMAEN_SHIFT)
+#define DAC_BRD_C1_DMAEN(base) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define DAC_WR_C1_DMAEN(base, value) (DAC_RMW_C1(base, DAC_C1_DMAEN_MASK, DAC_C1_DMAEN(value)))
+#define DAC_BWR_C1_DMAEN(base, value) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C2 - DAC Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C2 - DAC Control Register 2 (RW)
+ *
+ * Reset value: 0x0FU
+ */
+/*!
+ * @name Constants and macros for entire DAC_C2 register
+ */
+/*@{*/
+#define DAC_RD_C2(base)          (DAC_C2_REG(base))
+#define DAC_WR_C2(base, value)   (DAC_C2_REG(base) = (value))
+#define DAC_RMW_C2(base, mask, value) (DAC_WR_C2(base, (DAC_RD_C2(base) & ~(mask)) | (value)))
+#define DAC_SET_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) |  (value)))
+#define DAC_CLR_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) & ~(value)))
+#define DAC_TOG_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C2 bitfields
+ */
+
+/*!
+ * @name Register DAC_C2, field DACBFUP[3:0] (RW)
+ *
+ * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
+ * exceed it.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFUP field. */
+#define DAC_RD_C2_DACBFUP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFUP_MASK) >> DAC_C2_DACBFUP_SHIFT)
+#define DAC_BRD_C2_DACBFUP(base) (DAC_RD_C2_DACBFUP(base))
+
+/*! @brief Set the DACBFUP field to a new value. */
+#define DAC_WR_C2_DACBFUP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFUP_MASK, DAC_C2_DACBFUP(value)))
+#define DAC_BWR_C2_DACBFUP(base, value) (DAC_WR_C2_DACBFUP(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C2, field DACBFRP[7:4] (RW)
+ *
+ * Keeps the current value of the buffer read pointer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFRP field. */
+#define DAC_RD_C2_DACBFRP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT)
+#define DAC_BRD_C2_DACBFRP(base) (DAC_RD_C2_DACBFRP(base))
+
+/*! @brief Set the DACBFRP field to a new value. */
+#define DAC_WR_C2_DACBFRP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFRP_MASK, DAC_C2_DACBFRP(value)))
+#define DAC_BWR_C2_DACBFRP(base, value) (DAC_WR_C2_DACBFRP(base, value))
+/*@}*/
+
+/*
+ * MK64F12 DMA
+ *
+ * Enhanced direct memory access controller
+ *
+ * Registers defined in this header file:
+ * - DMA_CR - Control Register
+ * - DMA_ES - Error Status Register
+ * - DMA_ERQ - Enable Request Register
+ * - DMA_EEI - Enable Error Interrupt Register
+ * - DMA_CEEI - Clear Enable Error Interrupt Register
+ * - DMA_SEEI - Set Enable Error Interrupt Register
+ * - DMA_CERQ - Clear Enable Request Register
+ * - DMA_SERQ - Set Enable Request Register
+ * - DMA_CDNE - Clear DONE Status Bit Register
+ * - DMA_SSRT - Set START Bit Register
+ * - DMA_CERR - Clear Error Register
+ * - DMA_CINT - Clear Interrupt Request Register
+ * - DMA_INT - Interrupt Request Register
+ * - DMA_ERR - Error Register
+ * - DMA_HRS - Hardware Request Status Register
+ * - DMA_DCHPRI3 - Channel n Priority Register
+ * - DMA_DCHPRI2 - Channel n Priority Register
+ * - DMA_DCHPRI1 - Channel n Priority Register
+ * - DMA_DCHPRI0 - Channel n Priority Register
+ * - DMA_DCHPRI7 - Channel n Priority Register
+ * - DMA_DCHPRI6 - Channel n Priority Register
+ * - DMA_DCHPRI5 - Channel n Priority Register
+ * - DMA_DCHPRI4 - Channel n Priority Register
+ * - DMA_DCHPRI11 - Channel n Priority Register
+ * - DMA_DCHPRI10 - Channel n Priority Register
+ * - DMA_DCHPRI9 - Channel n Priority Register
+ * - DMA_DCHPRI8 - Channel n Priority Register
+ * - DMA_DCHPRI15 - Channel n Priority Register
+ * - DMA_DCHPRI14 - Channel n Priority Register
+ * - DMA_DCHPRI13 - Channel n Priority Register
+ * - DMA_DCHPRI12 - Channel n Priority Register
+ * - DMA_SADDR - TCD Source Address
+ * - DMA_SOFF - TCD Signed Source Address Offset
+ * - DMA_ATTR - TCD Transfer Attributes
+ * - DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ * - DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ * - DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ * - DMA_SLAST - TCD Last Source Address Adjustment
+ * - DMA_DADDR - TCD Destination Address
+ * - DMA_DOFF - TCD Signed Destination Address Offset
+ * - DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ * - DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ * - DMA_CSR - TCD Control and Status
+ * - DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ */
+
+#define DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
+#define DMA_IDX (0U) /*!< Instance number for DMA. */
+
+/*******************************************************************************
+ * DMA_CR - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CR defines the basic operating configuration of the DMA. Arbitration can
+ * be configured to use either a fixed-priority or a round-robin scheme. For
+ * fixed-priority arbitration, the highest priority channel requesting service is
+ * selected to execute. The channel priority registers assign the priorities; see
+ * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
+ * ignored and channels are cycled through (from high to low channel number)
+ * without regard to priority. For correct operation, writes to the CR register must
+ * be performed only when the DMA channels are inactive; that is, when
+ * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
+ * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
+ * minor loop completion. When minor loop offsets are enabled, the minor loop
+ * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
+ * destination address (TCDn_DADDR), or to both prior to the addresses being
+ * written back into the TCD. If the major loop is complete, the minor loop offset is
+ * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
+ * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
+ * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
+ * is used to specify multiple fields: a source enable bit (SMLOE) to specify
+ * the minor loop offset should be applied to the source address (TCDn_SADDR) upon
+ * minor loop completion, a destination enable bit (DMLOE) to specify the minor
+ * loop offset should be applied to the destination address (TCDn_DADDR) upon
+ * minor loop completion, and the sign extended minor loop offset value (MLOFF). The
+ * same offset value (MLOFF) is used for both source and destination minor loop
+ * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
+ * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
+ * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
+ * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
+ * assigned to the NBYTES field.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CR register
+ */
+/*@{*/
+#define DMA_RD_CR(base)          (DMA_CR_REG(base))
+#define DMA_WR_CR(base, value)   (DMA_CR_REG(base) = (value))
+#define DMA_RMW_CR(base, mask, value) (DMA_WR_CR(base, (DMA_RD_CR(base) & ~(mask)) | (value)))
+#define DMA_SET_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) |  (value)))
+#define DMA_CLR_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) & ~(value)))
+#define DMA_TOG_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CR bitfields
+ */
+
+/*!
+ * @name Register DMA_CR, field EDBG[1] (RW)
+ *
+ * Values:
+ * - 0b0 - When in debug mode, the DMA continues to operate.
+ * - 0b1 - When in debug mode, the DMA stalls the start of a new channel.
+ *     Executing channels are allowed to complete. Channel execution resumes when the
+ *     system exits debug mode or the EDBG bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_EDBG field. */
+#define DMA_RD_CR_EDBG(base) ((DMA_CR_REG(base) & DMA_CR_EDBG_MASK) >> DMA_CR_EDBG_SHIFT)
+#define DMA_BRD_CR_EDBG(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EDBG_SHIFT))
+
+/*! @brief Set the EDBG field to a new value. */
+#define DMA_WR_CR_EDBG(base, value) (DMA_RMW_CR(base, DMA_CR_EDBG_MASK, DMA_CR_EDBG(value)))
+#define DMA_BWR_CR_EDBG(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EDBG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field ERCA[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Fixed priority arbitration is used for channel selection .
+ * - 0b1 - Round robin arbitration is used for channel selection .
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_ERCA field. */
+#define DMA_RD_CR_ERCA(base) ((DMA_CR_REG(base) & DMA_CR_ERCA_MASK) >> DMA_CR_ERCA_SHIFT)
+#define DMA_BRD_CR_ERCA(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ERCA_SHIFT))
+
+/*! @brief Set the ERCA field to a new value. */
+#define DMA_WR_CR_ERCA(base, value) (DMA_RMW_CR(base, DMA_CR_ERCA_MASK, DMA_CR_ERCA(value)))
+#define DMA_BWR_CR_ERCA(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ERCA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field HOE[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Any error causes the HALT bit to set. Subsequently, all service
+ *     requests are ignored until the HALT bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_HOE field. */
+#define DMA_RD_CR_HOE(base)  ((DMA_CR_REG(base) & DMA_CR_HOE_MASK) >> DMA_CR_HOE_SHIFT)
+#define DMA_BRD_CR_HOE(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HOE_SHIFT))
+
+/*! @brief Set the HOE field to a new value. */
+#define DMA_WR_CR_HOE(base, value) (DMA_RMW_CR(base, DMA_CR_HOE_MASK, DMA_CR_HOE(value)))
+#define DMA_BWR_CR_HOE(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field HALT[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Stall the start of any new channels. Executing channels are allowed
+ *     to complete. Channel execution resumes when this bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_HALT field. */
+#define DMA_RD_CR_HALT(base) ((DMA_CR_REG(base) & DMA_CR_HALT_MASK) >> DMA_CR_HALT_SHIFT)
+#define DMA_BRD_CR_HALT(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define DMA_WR_CR_HALT(base, value) (DMA_RMW_CR(base, DMA_CR_HALT_MASK, DMA_CR_HALT(value)))
+#define DMA_BWR_CR_HALT(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field CLM[6] (RW)
+ *
+ * Values:
+ * - 0b0 - A minor loop channel link made to itself goes through channel
+ *     arbitration before being activated again.
+ * - 0b1 - A minor loop channel link made to itself does not go through channel
+ *     arbitration before being activated again. Upon minor loop completion, the
+ *     channel activates again if that channel has a minor loop channel link
+ *     enabled and the link channel is itself. This effectively applies the minor
+ *     loop offsets and restarts the next minor loop.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_CLM field. */
+#define DMA_RD_CR_CLM(base)  ((DMA_CR_REG(base) & DMA_CR_CLM_MASK) >> DMA_CR_CLM_SHIFT)
+#define DMA_BRD_CR_CLM(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CLM_SHIFT))
+
+/*! @brief Set the CLM field to a new value. */
+#define DMA_WR_CR_CLM(base, value) (DMA_RMW_CR(base, DMA_CR_CLM_MASK, DMA_CR_CLM(value)))
+#define DMA_BWR_CR_CLM(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CLM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field EMLM[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
+ * - 0b1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
+ *     an offset field, and the NBYTES field. The individual enable fields allow
+ *     the minor loop offset to be applied to the source address, the
+ *     destination address, or both. The NBYTES field is reduced when either offset is
+ *     enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_EMLM field. */
+#define DMA_RD_CR_EMLM(base) ((DMA_CR_REG(base) & DMA_CR_EMLM_MASK) >> DMA_CR_EMLM_SHIFT)
+#define DMA_BRD_CR_EMLM(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EMLM_SHIFT))
+
+/*! @brief Set the EMLM field to a new value. */
+#define DMA_WR_CR_EMLM(base, value) (DMA_RMW_CR(base, DMA_CR_EMLM_MASK, DMA_CR_EMLM(value)))
+#define DMA_BWR_CR_EMLM(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EMLM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field ECX[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Cancel the remaining data transfer in the same fashion as the CX bit.
+ *     Stop the executing channel and force the minor loop to finish. The cancel
+ *     takes effect after the last write of the current read/write sequence. The
+ *     ECX bit clears itself after the cancel is honored. In addition to
+ *     cancelling the transfer, ECX treats the cancel as an error condition, thus
+ *     updating the Error Status register (DMAx_ES) and generating an optional error
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_ECX field. */
+#define DMA_RD_CR_ECX(base)  ((DMA_CR_REG(base) & DMA_CR_ECX_MASK) >> DMA_CR_ECX_SHIFT)
+#define DMA_BRD_CR_ECX(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ECX_SHIFT))
+
+/*! @brief Set the ECX field to a new value. */
+#define DMA_WR_CR_ECX(base, value) (DMA_RMW_CR(base, DMA_CR_ECX_MASK, DMA_CR_ECX(value)))
+#define DMA_BWR_CR_ECX(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ECX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field CX[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Cancel the remaining data transfer. Stop the executing channel and
+ *     force the minor loop to finish. The cancel takes effect after the last write
+ *     of the current read/write sequence. The CX bit clears itself after the
+ *     cancel has been honored. This cancel retires the channel normally as if the
+ *     minor loop was completed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_CX field. */
+#define DMA_RD_CR_CX(base)   ((DMA_CR_REG(base) & DMA_CR_CX_MASK) >> DMA_CR_CX_SHIFT)
+#define DMA_BRD_CR_CX(base)  (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CX_SHIFT))
+
+/*! @brief Set the CX field to a new value. */
+#define DMA_WR_CR_CX(base, value) (DMA_RMW_CR(base, DMA_CR_CX_MASK, DMA_CR_CX(value)))
+#define DMA_BWR_CR_CX(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CX_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ES - Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ES - Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ES provides information concerning the last recorded channel error.
+ * Channel errors can be caused by: A configuration error, that is: An illegal setting
+ * in the transfer-control descriptor, or An illegal priority register setting
+ * in fixed-arbitration An error termination to a bus master read or write cycle
+ * See the Error Reporting and Handling section for more details.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ES register
+ */
+/*@{*/
+#define DMA_RD_ES(base)          (DMA_ES_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ES bitfields
+ */
+
+/*!
+ * @name Register DMA_ES, field DBE[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination bus error
+ * - 0b1 - The last recorded error was a bus error on a destination write
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DBE field. */
+#define DMA_RD_ES_DBE(base)  ((DMA_ES_REG(base) & DMA_ES_DBE_MASK) >> DMA_ES_DBE_SHIFT)
+#define DMA_BRD_ES_DBE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SBE[1] (RO)
+ *
+ * Values:
+ * - 0b0 - No source bus error
+ * - 0b1 - The last recorded error was a bus error on a source read
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SBE field. */
+#define DMA_RD_ES_SBE(base)  ((DMA_ES_REG(base) & DMA_ES_SBE_MASK) >> DMA_ES_SBE_SHIFT)
+#define DMA_BRD_ES_SBE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SGE[2] (RO)
+ *
+ * Values:
+ * - 0b0 - No scatter/gather configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DLASTSGA field. This field is checked at the beginning of a
+ *     scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled.
+ *     TCDn_DLASTSGA is not on a 32 byte boundary.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SGE field. */
+#define DMA_RD_ES_SGE(base)  ((DMA_ES_REG(base) & DMA_ES_SGE_MASK) >> DMA_ES_SGE_SHIFT)
+#define DMA_BRD_ES_SGE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SGE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field NCE[3] (RO)
+ *
+ * Values:
+ * - 0b0 - No NBYTES/CITER configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
+ *     TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
+ *     TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_NCE field. */
+#define DMA_RD_ES_NCE(base)  ((DMA_ES_REG(base) & DMA_ES_NCE_MASK) >> DMA_ES_NCE_SHIFT)
+#define DMA_BRD_ES_NCE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_NCE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field DOE[4] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination offset configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DOE field. */
+#define DMA_RD_ES_DOE(base)  ((DMA_ES_REG(base) & DMA_ES_DOE_MASK) >> DMA_ES_DOE_SHIFT)
+#define DMA_BRD_ES_DOE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field DAE[5] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination address configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DAE field. */
+#define DMA_RD_ES_DAE(base)  ((DMA_ES_REG(base) & DMA_ES_DAE_MASK) >> DMA_ES_DAE_SHIFT)
+#define DMA_BRD_ES_DAE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DAE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SOE[6] (RO)
+ *
+ * Values:
+ * - 0b0 - No source offset configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SOE field. */
+#define DMA_RD_ES_SOE(base)  ((DMA_ES_REG(base) & DMA_ES_SOE_MASK) >> DMA_ES_SOE_SHIFT)
+#define DMA_BRD_ES_SOE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SAE[7] (RO)
+ *
+ * Values:
+ * - 0b0 - No source address configuration error.
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SAE field. */
+#define DMA_RD_ES_SAE(base)  ((DMA_ES_REG(base) & DMA_ES_SAE_MASK) >> DMA_ES_SAE_SHIFT)
+#define DMA_BRD_ES_SAE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SAE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field ERRCHN[11:8] (RO)
+ *
+ * The channel number of the last recorded error (excluding CPE errors) or last
+ * recorded error canceled transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_ERRCHN field. */
+#define DMA_RD_ES_ERRCHN(base) ((DMA_ES_REG(base) & DMA_ES_ERRCHN_MASK) >> DMA_ES_ERRCHN_SHIFT)
+#define DMA_BRD_ES_ERRCHN(base) (DMA_RD_ES_ERRCHN(base))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field CPE[14] (RO)
+ *
+ * Values:
+ * - 0b0 - No channel priority error
+ * - 0b1 - The last recorded error was a configuration error in the channel
+ *     priorities . Channel priorities are not unique.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_CPE field. */
+#define DMA_RD_ES_CPE(base)  ((DMA_ES_REG(base) & DMA_ES_CPE_MASK) >> DMA_ES_CPE_SHIFT)
+#define DMA_BRD_ES_CPE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_CPE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field ECX[16] (RO)
+ *
+ * Values:
+ * - 0b0 - No canceled transfers
+ * - 0b1 - The last recorded entry was a canceled transfer by the error cancel
+ *     transfer input
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_ECX field. */
+#define DMA_RD_ES_ECX(base)  ((DMA_ES_REG(base) & DMA_ES_ECX_MASK) >> DMA_ES_ECX_SHIFT)
+#define DMA_BRD_ES_ECX(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_ECX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field VLD[31] (RO)
+ *
+ * Logical OR of all ERR status bits
+ *
+ * Values:
+ * - 0b0 - No ERR bits are set
+ * - 0b1 - At least one ERR bit is set indicating a valid error exists that has
+ *     not been cleared
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_VLD field. */
+#define DMA_RD_ES_VLD(base)  ((DMA_ES_REG(base) & DMA_ES_VLD_MASK) >> DMA_ES_VLD_SHIFT)
+#define DMA_BRD_ES_VLD(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_VLD_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ERQ - Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ERQ - Enable Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERQ register provides a bit map for the 16 implemented channels to enable
+ * the request signal for each channel. The state of any given channel enable is
+ * directly affected by writes to this register; it is also affected by writes
+ * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
+ * for a single channel can easily be modified without needing to perform a
+ * read-modify-write sequence to the ERQ. DMA request input signals and this enable
+ * request flag must be asserted before a channel's hardware service request is
+ * accepted. The state of the DMA enable request flag does not affect a channel
+ * service request made explicitly through software or a linked channel request.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ERQ register
+ */
+/*@{*/
+#define DMA_RD_ERQ(base)         (DMA_ERQ_REG(base))
+#define DMA_WR_ERQ(base, value)  (DMA_ERQ_REG(base) = (value))
+#define DMA_RMW_ERQ(base, mask, value) (DMA_WR_ERQ(base, (DMA_RD_ERQ(base) & ~(mask)) | (value)))
+#define DMA_SET_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) |  (value)))
+#define DMA_CLR_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) & ~(value)))
+#define DMA_TOG_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_ERQ, field ERQ0[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ0 field. */
+#define DMA_RD_ERQ_ERQ0(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ0_MASK) >> DMA_ERQ_ERQ0_SHIFT)
+#define DMA_BRD_ERQ_ERQ0(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ0_SHIFT))
+
+/*! @brief Set the ERQ0 field to a new value. */
+#define DMA_WR_ERQ_ERQ0(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ0_MASK, DMA_ERQ_ERQ0(value)))
+#define DMA_BWR_ERQ_ERQ0(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ1[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ1 field. */
+#define DMA_RD_ERQ_ERQ1(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ1_MASK) >> DMA_ERQ_ERQ1_SHIFT)
+#define DMA_BRD_ERQ_ERQ1(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ1_SHIFT))
+
+/*! @brief Set the ERQ1 field to a new value. */
+#define DMA_WR_ERQ_ERQ1(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ1_MASK, DMA_ERQ_ERQ1(value)))
+#define DMA_BWR_ERQ_ERQ1(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ2[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ2 field. */
+#define DMA_RD_ERQ_ERQ2(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ2_MASK) >> DMA_ERQ_ERQ2_SHIFT)
+#define DMA_BRD_ERQ_ERQ2(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ2_SHIFT))
+
+/*! @brief Set the ERQ2 field to a new value. */
+#define DMA_WR_ERQ_ERQ2(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ2_MASK, DMA_ERQ_ERQ2(value)))
+#define DMA_BWR_ERQ_ERQ2(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ3[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ3 field. */
+#define DMA_RD_ERQ_ERQ3(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ3_MASK) >> DMA_ERQ_ERQ3_SHIFT)
+#define DMA_BRD_ERQ_ERQ3(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ3_SHIFT))
+
+/*! @brief Set the ERQ3 field to a new value. */
+#define DMA_WR_ERQ_ERQ3(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ3_MASK, DMA_ERQ_ERQ3(value)))
+#define DMA_BWR_ERQ_ERQ3(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ4[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ4 field. */
+#define DMA_RD_ERQ_ERQ4(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ4_MASK) >> DMA_ERQ_ERQ4_SHIFT)
+#define DMA_BRD_ERQ_ERQ4(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ4_SHIFT))
+
+/*! @brief Set the ERQ4 field to a new value. */
+#define DMA_WR_ERQ_ERQ4(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ4_MASK, DMA_ERQ_ERQ4(value)))
+#define DMA_BWR_ERQ_ERQ4(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ5[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ5 field. */
+#define DMA_RD_ERQ_ERQ5(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ5_MASK) >> DMA_ERQ_ERQ5_SHIFT)
+#define DMA_BRD_ERQ_ERQ5(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ5_SHIFT))
+
+/*! @brief Set the ERQ5 field to a new value. */
+#define DMA_WR_ERQ_ERQ5(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ5_MASK, DMA_ERQ_ERQ5(value)))
+#define DMA_BWR_ERQ_ERQ5(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ6[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ6 field. */
+#define DMA_RD_ERQ_ERQ6(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ6_MASK) >> DMA_ERQ_ERQ6_SHIFT)
+#define DMA_BRD_ERQ_ERQ6(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ6_SHIFT))
+
+/*! @brief Set the ERQ6 field to a new value. */
+#define DMA_WR_ERQ_ERQ6(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ6_MASK, DMA_ERQ_ERQ6(value)))
+#define DMA_BWR_ERQ_ERQ6(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ7[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ7 field. */
+#define DMA_RD_ERQ_ERQ7(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ7_MASK) >> DMA_ERQ_ERQ7_SHIFT)
+#define DMA_BRD_ERQ_ERQ7(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ7_SHIFT))
+
+/*! @brief Set the ERQ7 field to a new value. */
+#define DMA_WR_ERQ_ERQ7(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ7_MASK, DMA_ERQ_ERQ7(value)))
+#define DMA_BWR_ERQ_ERQ7(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ8[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ8 field. */
+#define DMA_RD_ERQ_ERQ8(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ8_MASK) >> DMA_ERQ_ERQ8_SHIFT)
+#define DMA_BRD_ERQ_ERQ8(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ8_SHIFT))
+
+/*! @brief Set the ERQ8 field to a new value. */
+#define DMA_WR_ERQ_ERQ8(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ8_MASK, DMA_ERQ_ERQ8(value)))
+#define DMA_BWR_ERQ_ERQ8(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ9[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ9 field. */
+#define DMA_RD_ERQ_ERQ9(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ9_MASK) >> DMA_ERQ_ERQ9_SHIFT)
+#define DMA_BRD_ERQ_ERQ9(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ9_SHIFT))
+
+/*! @brief Set the ERQ9 field to a new value. */
+#define DMA_WR_ERQ_ERQ9(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ9_MASK, DMA_ERQ_ERQ9(value)))
+#define DMA_BWR_ERQ_ERQ9(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ10[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ10 field. */
+#define DMA_RD_ERQ_ERQ10(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ10_MASK) >> DMA_ERQ_ERQ10_SHIFT)
+#define DMA_BRD_ERQ_ERQ10(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ10_SHIFT))
+
+/*! @brief Set the ERQ10 field to a new value. */
+#define DMA_WR_ERQ_ERQ10(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ10_MASK, DMA_ERQ_ERQ10(value)))
+#define DMA_BWR_ERQ_ERQ10(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ11[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ11 field. */
+#define DMA_RD_ERQ_ERQ11(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ11_MASK) >> DMA_ERQ_ERQ11_SHIFT)
+#define DMA_BRD_ERQ_ERQ11(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ11_SHIFT))
+
+/*! @brief Set the ERQ11 field to a new value. */
+#define DMA_WR_ERQ_ERQ11(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ11_MASK, DMA_ERQ_ERQ11(value)))
+#define DMA_BWR_ERQ_ERQ11(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ12[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ12 field. */
+#define DMA_RD_ERQ_ERQ12(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ12_MASK) >> DMA_ERQ_ERQ12_SHIFT)
+#define DMA_BRD_ERQ_ERQ12(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ12_SHIFT))
+
+/*! @brief Set the ERQ12 field to a new value. */
+#define DMA_WR_ERQ_ERQ12(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ12_MASK, DMA_ERQ_ERQ12(value)))
+#define DMA_BWR_ERQ_ERQ12(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ13[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ13 field. */
+#define DMA_RD_ERQ_ERQ13(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ13_MASK) >> DMA_ERQ_ERQ13_SHIFT)
+#define DMA_BRD_ERQ_ERQ13(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ13_SHIFT))
+
+/*! @brief Set the ERQ13 field to a new value. */
+#define DMA_WR_ERQ_ERQ13(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ13_MASK, DMA_ERQ_ERQ13(value)))
+#define DMA_BWR_ERQ_ERQ13(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ14[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ14 field. */
+#define DMA_RD_ERQ_ERQ14(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ14_MASK) >> DMA_ERQ_ERQ14_SHIFT)
+#define DMA_BRD_ERQ_ERQ14(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ14_SHIFT))
+
+/*! @brief Set the ERQ14 field to a new value. */
+#define DMA_WR_ERQ_ERQ14(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ14_MASK, DMA_ERQ_ERQ14(value)))
+#define DMA_BWR_ERQ_ERQ14(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ15[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ15 field. */
+#define DMA_RD_ERQ_ERQ15(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ15_MASK) >> DMA_ERQ_ERQ15_SHIFT)
+#define DMA_BRD_ERQ_ERQ15(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ15_SHIFT))
+
+/*! @brief Set the ERQ15 field to a new value. */
+#define DMA_WR_ERQ_ERQ15(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ15_MASK, DMA_ERQ_ERQ15(value)))
+#define DMA_BWR_ERQ_ERQ15(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_EEI - Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_EEI - Enable Error Interrupt Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The EEI register provides a bit map for the 16 channels to enable the error
+ * interrupt signal for each channel. The state of any given channel's error
+ * interrupt enable is directly affected by writes to this register; it is also
+ * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
+ * interrupt enable for a single channel can easily be modified without the need to
+ * perform a read-modify-write sequence to the EEI register. The DMA error
+ * indicator and the error interrupt enable flag must be asserted before an error
+ * interrupt request for a given channel is asserted to the interrupt controller.
+ */
+/*!
+ * @name Constants and macros for entire DMA_EEI register
+ */
+/*@{*/
+#define DMA_RD_EEI(base)         (DMA_EEI_REG(base))
+#define DMA_WR_EEI(base, value)  (DMA_EEI_REG(base) = (value))
+#define DMA_RMW_EEI(base, mask, value) (DMA_WR_EEI(base, (DMA_RD_EEI(base) & ~(mask)) | (value)))
+#define DMA_SET_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) |  (value)))
+#define DMA_CLR_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) & ~(value)))
+#define DMA_TOG_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_EEI bitfields
+ */
+
+/*!
+ * @name Register DMA_EEI, field EEI0[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI0 field. */
+#define DMA_RD_EEI_EEI0(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI0_MASK) >> DMA_EEI_EEI0_SHIFT)
+#define DMA_BRD_EEI_EEI0(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI0_SHIFT))
+
+/*! @brief Set the EEI0 field to a new value. */
+#define DMA_WR_EEI_EEI0(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI0_MASK, DMA_EEI_EEI0(value)))
+#define DMA_BWR_EEI_EEI0(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI1[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI1 field. */
+#define DMA_RD_EEI_EEI1(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI1_MASK) >> DMA_EEI_EEI1_SHIFT)
+#define DMA_BRD_EEI_EEI1(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI1_SHIFT))
+
+/*! @brief Set the EEI1 field to a new value. */
+#define DMA_WR_EEI_EEI1(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI1_MASK, DMA_EEI_EEI1(value)))
+#define DMA_BWR_EEI_EEI1(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI2[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI2 field. */
+#define DMA_RD_EEI_EEI2(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI2_MASK) >> DMA_EEI_EEI2_SHIFT)
+#define DMA_BRD_EEI_EEI2(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI2_SHIFT))
+
+/*! @brief Set the EEI2 field to a new value. */
+#define DMA_WR_EEI_EEI2(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI2_MASK, DMA_EEI_EEI2(value)))
+#define DMA_BWR_EEI_EEI2(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI3[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI3 field. */
+#define DMA_RD_EEI_EEI3(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI3_MASK) >> DMA_EEI_EEI3_SHIFT)
+#define DMA_BRD_EEI_EEI3(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI3_SHIFT))
+
+/*! @brief Set the EEI3 field to a new value. */
+#define DMA_WR_EEI_EEI3(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI3_MASK, DMA_EEI_EEI3(value)))
+#define DMA_BWR_EEI_EEI3(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI4[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI4 field. */
+#define DMA_RD_EEI_EEI4(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI4_MASK) >> DMA_EEI_EEI4_SHIFT)
+#define DMA_BRD_EEI_EEI4(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI4_SHIFT))
+
+/*! @brief Set the EEI4 field to a new value. */
+#define DMA_WR_EEI_EEI4(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI4_MASK, DMA_EEI_EEI4(value)))
+#define DMA_BWR_EEI_EEI4(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI5[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI5 field. */
+#define DMA_RD_EEI_EEI5(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI5_MASK) >> DMA_EEI_EEI5_SHIFT)
+#define DMA_BRD_EEI_EEI5(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI5_SHIFT))
+
+/*! @brief Set the EEI5 field to a new value. */
+#define DMA_WR_EEI_EEI5(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI5_MASK, DMA_EEI_EEI5(value)))
+#define DMA_BWR_EEI_EEI5(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI6[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI6 field. */
+#define DMA_RD_EEI_EEI6(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI6_MASK) >> DMA_EEI_EEI6_SHIFT)
+#define DMA_BRD_EEI_EEI6(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI6_SHIFT))
+
+/*! @brief Set the EEI6 field to a new value. */
+#define DMA_WR_EEI_EEI6(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI6_MASK, DMA_EEI_EEI6(value)))
+#define DMA_BWR_EEI_EEI6(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI7[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI7 field. */
+#define DMA_RD_EEI_EEI7(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI7_MASK) >> DMA_EEI_EEI7_SHIFT)
+#define DMA_BRD_EEI_EEI7(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI7_SHIFT))
+
+/*! @brief Set the EEI7 field to a new value. */
+#define DMA_WR_EEI_EEI7(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI7_MASK, DMA_EEI_EEI7(value)))
+#define DMA_BWR_EEI_EEI7(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI8[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI8 field. */
+#define DMA_RD_EEI_EEI8(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI8_MASK) >> DMA_EEI_EEI8_SHIFT)
+#define DMA_BRD_EEI_EEI8(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI8_SHIFT))
+
+/*! @brief Set the EEI8 field to a new value. */
+#define DMA_WR_EEI_EEI8(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI8_MASK, DMA_EEI_EEI8(value)))
+#define DMA_BWR_EEI_EEI8(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI9[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI9 field. */
+#define DMA_RD_EEI_EEI9(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI9_MASK) >> DMA_EEI_EEI9_SHIFT)
+#define DMA_BRD_EEI_EEI9(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI9_SHIFT))
+
+/*! @brief Set the EEI9 field to a new value. */
+#define DMA_WR_EEI_EEI9(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI9_MASK, DMA_EEI_EEI9(value)))
+#define DMA_BWR_EEI_EEI9(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI10[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI10 field. */
+#define DMA_RD_EEI_EEI10(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI10_MASK) >> DMA_EEI_EEI10_SHIFT)
+#define DMA_BRD_EEI_EEI10(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI10_SHIFT))
+
+/*! @brief Set the EEI10 field to a new value. */
+#define DMA_WR_EEI_EEI10(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI10_MASK, DMA_EEI_EEI10(value)))
+#define DMA_BWR_EEI_EEI10(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI11[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI11 field. */
+#define DMA_RD_EEI_EEI11(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI11_MASK) >> DMA_EEI_EEI11_SHIFT)
+#define DMA_BRD_EEI_EEI11(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI11_SHIFT))
+
+/*! @brief Set the EEI11 field to a new value. */
+#define DMA_WR_EEI_EEI11(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI11_MASK, DMA_EEI_EEI11(value)))
+#define DMA_BWR_EEI_EEI11(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI12[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI12 field. */
+#define DMA_RD_EEI_EEI12(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI12_MASK) >> DMA_EEI_EEI12_SHIFT)
+#define DMA_BRD_EEI_EEI12(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI12_SHIFT))
+
+/*! @brief Set the EEI12 field to a new value. */
+#define DMA_WR_EEI_EEI12(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI12_MASK, DMA_EEI_EEI12(value)))
+#define DMA_BWR_EEI_EEI12(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI13[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI13 field. */
+#define DMA_RD_EEI_EEI13(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI13_MASK) >> DMA_EEI_EEI13_SHIFT)
+#define DMA_BRD_EEI_EEI13(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI13_SHIFT))
+
+/*! @brief Set the EEI13 field to a new value. */
+#define DMA_WR_EEI_EEI13(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI13_MASK, DMA_EEI_EEI13(value)))
+#define DMA_BWR_EEI_EEI13(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI14[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI14 field. */
+#define DMA_RD_EEI_EEI14(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI14_MASK) >> DMA_EEI_EEI14_SHIFT)
+#define DMA_BRD_EEI_EEI14(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI14_SHIFT))
+
+/*! @brief Set the EEI14 field to a new value. */
+#define DMA_WR_EEI_EEI14(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI14_MASK, DMA_EEI_EEI14(value)))
+#define DMA_BWR_EEI_EEI14(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI15[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI15 field. */
+#define DMA_RD_EEI_EEI15(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI15_MASK) >> DMA_EEI_EEI15_SHIFT)
+#define DMA_BRD_EEI_EEI15(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI15_SHIFT))
+
+/*! @brief Set the EEI15 field to a new value. */
+#define DMA_WR_EEI_EEI15(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI15_MASK, DMA_EEI_EEI15(value)))
+#define DMA_BWR_EEI_EEI15(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CEEI - Clear Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CEEI - Clear Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
+ * the EEI to disable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be cleared. Setting
+ * the CAEE bit provides a global clear function, forcing the EEI contents to be
+ * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
+ * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
+ * Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CEEI register
+ */
+/*@{*/
+#define DMA_RD_CEEI(base)        (DMA_CEEI_REG(base))
+#define DMA_WR_CEEI(base, value) (DMA_CEEI_REG(base) = (value))
+#define DMA_RMW_CEEI(base, mask, value) (DMA_WR_CEEI(base, (DMA_RD_CEEI(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in EEI
+ */
+/*@{*/
+/*! @brief Set the CEEI field to a new value. */
+#define DMA_WR_CEEI_CEEI(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_CEEI_MASK, DMA_CEEI_CEEI(value)))
+#define DMA_BWR_CEEI_CEEI(base, value) (DMA_WR_CEEI_CEEI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CEEI, field CAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the EEI bit specified in the CEEI field
+ * - 0b1 - Clear all bits in EEI
+ */
+/*@{*/
+/*! @brief Set the CAEE field to a new value. */
+#define DMA_WR_CEEI_CAEE(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_CAEE_MASK, DMA_CEEI_CAEE(value)))
+#define DMA_BWR_CEEI_CAEE(base, value) (BITBAND_ACCESS8(&DMA_CEEI_REG(base), DMA_CEEI_CAEE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CEEI_NOP(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_NOP_MASK, DMA_CEEI_NOP(value)))
+#define DMA_BWR_CEEI_NOP(base, value) (BITBAND_ACCESS8(&DMA_CEEI_REG(base), DMA_CEEI_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SEEI - Set Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SEEI - Set Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
+ * EEI to enable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be set. Setting the
+ * SAEE bit provides a global set function, forcing the entire EEI contents to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SEEI register
+ */
+/*@{*/
+#define DMA_RD_SEEI(base)        (DMA_SEEI_REG(base))
+#define DMA_WR_SEEI(base, value) (DMA_SEEI_REG(base) = (value))
+#define DMA_RMW_SEEI(base, mask, value) (DMA_WR_SEEI(base, (DMA_RD_SEEI(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in EEI
+ */
+/*@{*/
+/*! @brief Set the SEEI field to a new value. */
+#define DMA_WR_SEEI_SEEI(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_SEEI_MASK, DMA_SEEI_SEEI(value)))
+#define DMA_BWR_SEEI_SEEI(base, value) (DMA_WR_SEEI_SEEI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SEEI, field SAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the EEI bit specified in the SEEI field.
+ * - 0b1 - Sets all bits in EEI
+ */
+/*@{*/
+/*! @brief Set the SAEE field to a new value. */
+#define DMA_WR_SEEI_SAEE(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_SAEE_MASK, DMA_SEEI_SAEE(value)))
+#define DMA_BWR_SEEI_SAEE(base, value) (BITBAND_ACCESS8(&DMA_SEEI_REG(base), DMA_SEEI_SAEE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SEEI_NOP(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_NOP_MASK, DMA_SEEI_NOP(value)))
+#define DMA_BWR_SEEI_NOP(base, value) (BITBAND_ACCESS8(&DMA_SEEI_REG(base), DMA_SEEI_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CERQ - Clear Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CERQ - Clear Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERQ to disable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be cleared. Setting the
+ * CAER bit provides a global clear function, forcing the entire contents of the
+ * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
+ * command is ignored. This allows you to write multiple-byte registers as a 32-bit
+ * word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CERQ register
+ */
+/*@{*/
+#define DMA_RD_CERQ(base)        (DMA_CERQ_REG(base))
+#define DMA_WR_CERQ(base, value) (DMA_CERQ_REG(base) = (value))
+#define DMA_RMW_CERQ(base, mask, value) (DMA_WR_CERQ(base, (DMA_RD_CERQ(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERQ
+ */
+/*@{*/
+/*! @brief Set the CERQ field to a new value. */
+#define DMA_WR_CERQ_CERQ(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_CERQ_MASK, DMA_CERQ_CERQ(value)))
+#define DMA_BWR_CERQ_CERQ(base, value) (DMA_WR_CERQ_CERQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERQ, field CAER[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the ERQ bit specified in the CERQ field
+ * - 0b1 - Clear all bits in ERQ
+ */
+/*@{*/
+/*! @brief Set the CAER field to a new value. */
+#define DMA_WR_CERQ_CAER(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_CAER_MASK, DMA_CERQ_CAER(value)))
+#define DMA_BWR_CERQ_CAER(base, value) (BITBAND_ACCESS8(&DMA_CERQ_REG(base), DMA_CERQ_CAER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CERQ_NOP(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_NOP_MASK, DMA_CERQ_NOP(value)))
+#define DMA_BWR_CERQ_NOP(base, value) (BITBAND_ACCESS8(&DMA_CERQ_REG(base), DMA_CERQ_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SERQ - Set Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SERQ - Set Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
+ * ERQ to enable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
+ * bit provides a global set function, forcing the entire contents of ERQ to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SERQ register
+ */
+/*@{*/
+#define DMA_RD_SERQ(base)        (DMA_SERQ_REG(base))
+#define DMA_WR_SERQ(base, value) (DMA_SERQ_REG(base) = (value))
+#define DMA_RMW_SERQ(base, mask, value) (DMA_WR_SERQ(base, (DMA_RD_SERQ(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in ERQ
+ */
+/*@{*/
+/*! @brief Set the SERQ field to a new value. */
+#define DMA_WR_SERQ_SERQ(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_SERQ_MASK, DMA_SERQ_SERQ(value)))
+#define DMA_BWR_SERQ_SERQ(base, value) (DMA_WR_SERQ_SERQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SERQ, field SAER[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the ERQ bit specified in the SERQ field
+ * - 0b1 - Set all bits in ERQ
+ */
+/*@{*/
+/*! @brief Set the SAER field to a new value. */
+#define DMA_WR_SERQ_SAER(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_SAER_MASK, DMA_SERQ_SAER(value)))
+#define DMA_BWR_SERQ_SAER(base, value) (BITBAND_ACCESS8(&DMA_SERQ_REG(base), DMA_SERQ_SAER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SERQ_NOP(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_NOP_MASK, DMA_SERQ_NOP(value)))
+#define DMA_BWR_SERQ_NOP(base, value) (BITBAND_ACCESS8(&DMA_SERQ_REG(base), DMA_SERQ_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CDNE - Clear DONE Status Bit Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CDNE - Clear DONE Status Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
+ * the CADN bit provides a global clear function, forcing all DONE bits to be
+ * cleared. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CDNE register
+ */
+/*@{*/
+#define DMA_RD_CDNE(base)        (DMA_CDNE_REG(base))
+#define DMA_WR_CDNE(base, value) (DMA_CDNE_REG(base) = (value))
+#define DMA_RMW_CDNE(base, mask, value) (DMA_WR_CDNE(base, (DMA_RD_CDNE(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CDNE bitfields
+ */
+
+/*!
+ * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in TCDn_CSR[DONE]
+ */
+/*@{*/
+/*! @brief Set the CDNE field to a new value. */
+#define DMA_WR_CDNE_CDNE(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_CDNE_MASK, DMA_CDNE_CDNE(value)))
+#define DMA_BWR_CDNE_CDNE(base, value) (DMA_WR_CDNE_CDNE(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CDNE, field CADN[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
+ * - 0b1 - Clears all bits in TCDn_CSR[DONE]
+ */
+/*@{*/
+/*! @brief Set the CADN field to a new value. */
+#define DMA_WR_CDNE_CADN(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_CADN_MASK, DMA_CDNE_CADN(value)))
+#define DMA_BWR_CDNE_CADN(base, value) (BITBAND_ACCESS8(&DMA_CDNE_REG(base), DMA_CDNE_CADN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CDNE, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CDNE_NOP(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_NOP_MASK, DMA_CDNE_NOP(value)))
+#define DMA_BWR_CDNE_NOP(base, value) (BITBAND_ACCESS8(&DMA_CDNE_REG(base), DMA_CDNE_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SSRT - Set START Bit Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SSRT - Set START Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SSRT provides a simple memory-mapped mechanism to set the START bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * START bit in the corresponding transfer control descriptor to be set. Setting the
+ * SAST bit provides a global set function, forcing all START bits to be set. If
+ * the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SSRT register
+ */
+/*@{*/
+#define DMA_RD_SSRT(base)        (DMA_SSRT_REG(base))
+#define DMA_WR_SSRT(base, value) (DMA_SSRT_REG(base) = (value))
+#define DMA_RMW_SSRT(base, mask, value) (DMA_WR_SSRT(base, (DMA_RD_SSRT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SSRT bitfields
+ */
+
+/*!
+ * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in TCDn_CSR[START]
+ */
+/*@{*/
+/*! @brief Set the SSRT field to a new value. */
+#define DMA_WR_SSRT_SSRT(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_SSRT_MASK, DMA_SSRT_SSRT(value)))
+#define DMA_BWR_SSRT_SSRT(base, value) (DMA_WR_SSRT_SSRT(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SSRT, field SAST[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
+ * - 0b1 - Set all bits in TCDn_CSR[START]
+ */
+/*@{*/
+/*! @brief Set the SAST field to a new value. */
+#define DMA_WR_SSRT_SAST(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_SAST_MASK, DMA_SSRT_SAST(value)))
+#define DMA_BWR_SSRT_SAST(base, value) (BITBAND_ACCESS8(&DMA_SSRT_REG(base), DMA_SSRT_SAST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SSRT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SSRT_NOP(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_NOP_MASK, DMA_SSRT_NOP(value)))
+#define DMA_BWR_SSRT_NOP(base, value) (BITBAND_ACCESS8(&DMA_SSRT_REG(base), DMA_SSRT_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CERR - Clear Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CERR - Clear Error Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERR provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERR to disable the error condition flag for a given channel. The given value
+ * on a register write causes the corresponding bit in the ERR to be cleared.
+ * Setting the CAEI bit provides a global clear function, forcing the ERR contents
+ * to be cleared, clearing all channel error indicators. If the NOP bit is set,
+ * the command is ignored. This allows you to write multiple-byte registers as a
+ * 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CERR register
+ */
+/*@{*/
+#define DMA_RD_CERR(base)        (DMA_CERR_REG(base))
+#define DMA_WR_CERR(base, value) (DMA_CERR_REG(base) = (value))
+#define DMA_RMW_CERR(base, mask, value) (DMA_WR_CERR(base, (DMA_RD_CERR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CERR bitfields
+ */
+
+/*!
+ * @name Register DMA_CERR, field CERR[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERR
+ */
+/*@{*/
+/*! @brief Set the CERR field to a new value. */
+#define DMA_WR_CERR_CERR(base, value) (DMA_RMW_CERR(base, DMA_CERR_CERR_MASK, DMA_CERR_CERR(value)))
+#define DMA_BWR_CERR_CERR(base, value) (DMA_WR_CERR_CERR(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERR, field CAEI[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the ERR bit specified in the CERR field
+ * - 0b1 - Clear all bits in ERR
+ */
+/*@{*/
+/*! @brief Set the CAEI field to a new value. */
+#define DMA_WR_CERR_CAEI(base, value) (DMA_RMW_CERR(base, DMA_CERR_CAEI_MASK, DMA_CERR_CAEI(value)))
+#define DMA_BWR_CERR_CAEI(base, value) (BITBAND_ACCESS8(&DMA_CERR_REG(base), DMA_CERR_CAEI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERR, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CERR_NOP(base, value) (DMA_RMW_CERR(base, DMA_CERR_NOP_MASK, DMA_CERR_NOP(value)))
+#define DMA_BWR_CERR_NOP(base, value) (BITBAND_ACCESS8(&DMA_CERR_REG(base), DMA_CERR_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CINT - Clear Interrupt Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CINT - Clear Interrupt Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
+ * the INT to disable the interrupt request for a given channel. The given value
+ * on a register write causes the corresponding bit in the INT to be cleared.
+ * Setting the CAIR bit provides a global clear function, forcing the entire contents
+ * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
+ * bit is set, the command is ignored. This allows you to write multiple-byte
+ * registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CINT register
+ */
+/*@{*/
+#define DMA_RD_CINT(base)        (DMA_CINT_REG(base))
+#define DMA_WR_CINT(base, value) (DMA_CINT_REG(base) = (value))
+#define DMA_RMW_CINT(base, mask, value) (DMA_WR_CINT(base, (DMA_RD_CINT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CINT bitfields
+ */
+
+/*!
+ * @name Register DMA_CINT, field CINT[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in INT
+ */
+/*@{*/
+/*! @brief Set the CINT field to a new value. */
+#define DMA_WR_CINT_CINT(base, value) (DMA_RMW_CINT(base, DMA_CINT_CINT_MASK, DMA_CINT_CINT(value)))
+#define DMA_BWR_CINT_CINT(base, value) (DMA_WR_CINT_CINT(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CINT, field CAIR[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the INT bit specified in the CINT field
+ * - 0b1 - Clear all bits in INT
+ */
+/*@{*/
+/*! @brief Set the CAIR field to a new value. */
+#define DMA_WR_CINT_CAIR(base, value) (DMA_RMW_CINT(base, DMA_CINT_CAIR_MASK, DMA_CINT_CAIR(value)))
+#define DMA_BWR_CINT_CAIR(base, value) (BITBAND_ACCESS8(&DMA_CINT_REG(base), DMA_CINT_CAIR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CINT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CINT_NOP(base, value) (DMA_RMW_CINT(base, DMA_CINT_NOP_MASK, DMA_CINT_NOP(value)))
+#define DMA_BWR_CINT_NOP(base, value) (BITBAND_ACCESS8(&DMA_CINT_REG(base), DMA_CINT_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_INT - Interrupt Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_INT - Interrupt Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The INT register provides a bit map for the 16 channels signaling the
+ * presence of an interrupt request for each channel. Depending on the appropriate bit
+ * setting in the transfer-control descriptors, the eDMA engine generates an
+ * interrupt on data transfer completion. The outputs of this register are directly
+ * routed to the interrupt controller (INTC). During the interrupt-service routine
+ * associated with any given channel, it is the software's responsibility to
+ * clear the appropriate bit, negating the interrupt request. Typically, a write to
+ * the CINT register in the interrupt service routine is used for this purpose.
+ * The state of any given channel's interrupt request is directly affected by
+ * writes to this register; it is also affected by writes to the CINT register. On
+ * writes to INT, a 1 in any bit position clears the corresponding channel's
+ * interrupt request. A zero in any bit position has no affect on the corresponding
+ * channel's current interrupt status. The CINT register is provided so the interrupt
+ * request for a single channel can easily be cleared without the need to
+ * perform a read-modify-write sequence to the INT register.
+ */
+/*!
+ * @name Constants and macros for entire DMA_INT register
+ */
+/*@{*/
+#define DMA_RD_INT(base)         (DMA_INT_REG(base))
+#define DMA_WR_INT(base, value)  (DMA_INT_REG(base) = (value))
+#define DMA_RMW_INT(base, mask, value) (DMA_WR_INT(base, (DMA_RD_INT(base) & ~(mask)) | (value)))
+#define DMA_SET_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) |  (value)))
+#define DMA_CLR_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) & ~(value)))
+#define DMA_TOG_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_INT bitfields
+ */
+
+/*!
+ * @name Register DMA_INT, field INT0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT0 field. */
+#define DMA_RD_INT_INT0(base) ((DMA_INT_REG(base) & DMA_INT_INT0_MASK) >> DMA_INT_INT0_SHIFT)
+#define DMA_BRD_INT_INT0(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT0_SHIFT))
+
+/*! @brief Set the INT0 field to a new value. */
+#define DMA_WR_INT_INT0(base, value) (DMA_RMW_INT(base, (DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT0(value)))
+#define DMA_BWR_INT_INT0(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT1 field. */
+#define DMA_RD_INT_INT1(base) ((DMA_INT_REG(base) & DMA_INT_INT1_MASK) >> DMA_INT_INT1_SHIFT)
+#define DMA_BRD_INT_INT1(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT1_SHIFT))
+
+/*! @brief Set the INT1 field to a new value. */
+#define DMA_WR_INT_INT1(base, value) (DMA_RMW_INT(base, (DMA_INT_INT1_MASK | DMA_INT_INT0_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT1(value)))
+#define DMA_BWR_INT_INT1(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT2 field. */
+#define DMA_RD_INT_INT2(base) ((DMA_INT_REG(base) & DMA_INT_INT2_MASK) >> DMA_INT_INT2_SHIFT)
+#define DMA_BRD_INT_INT2(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT2_SHIFT))
+
+/*! @brief Set the INT2 field to a new value. */
+#define DMA_WR_INT_INT2(base, value) (DMA_RMW_INT(base, (DMA_INT_INT2_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT2(value)))
+#define DMA_BWR_INT_INT2(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT3 field. */
+#define DMA_RD_INT_INT3(base) ((DMA_INT_REG(base) & DMA_INT_INT3_MASK) >> DMA_INT_INT3_SHIFT)
+#define DMA_BRD_INT_INT3(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT3_SHIFT))
+
+/*! @brief Set the INT3 field to a new value. */
+#define DMA_WR_INT_INT3(base, value) (DMA_RMW_INT(base, (DMA_INT_INT3_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT3(value)))
+#define DMA_BWR_INT_INT3(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT4[4] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT4 field. */
+#define DMA_RD_INT_INT4(base) ((DMA_INT_REG(base) & DMA_INT_INT4_MASK) >> DMA_INT_INT4_SHIFT)
+#define DMA_BRD_INT_INT4(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT4_SHIFT))
+
+/*! @brief Set the INT4 field to a new value. */
+#define DMA_WR_INT_INT4(base, value) (DMA_RMW_INT(base, (DMA_INT_INT4_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT4(value)))
+#define DMA_BWR_INT_INT4(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT5[5] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT5 field. */
+#define DMA_RD_INT_INT5(base) ((DMA_INT_REG(base) & DMA_INT_INT5_MASK) >> DMA_INT_INT5_SHIFT)
+#define DMA_BRD_INT_INT5(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT5_SHIFT))
+
+/*! @brief Set the INT5 field to a new value. */
+#define DMA_WR_INT_INT5(base, value) (DMA_RMW_INT(base, (DMA_INT_INT5_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT5(value)))
+#define DMA_BWR_INT_INT5(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT6[6] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT6 field. */
+#define DMA_RD_INT_INT6(base) ((DMA_INT_REG(base) & DMA_INT_INT6_MASK) >> DMA_INT_INT6_SHIFT)
+#define DMA_BRD_INT_INT6(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT6_SHIFT))
+
+/*! @brief Set the INT6 field to a new value. */
+#define DMA_WR_INT_INT6(base, value) (DMA_RMW_INT(base, (DMA_INT_INT6_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT6(value)))
+#define DMA_BWR_INT_INT6(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT7[7] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT7 field. */
+#define DMA_RD_INT_INT7(base) ((DMA_INT_REG(base) & DMA_INT_INT7_MASK) >> DMA_INT_INT7_SHIFT)
+#define DMA_BRD_INT_INT7(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT7_SHIFT))
+
+/*! @brief Set the INT7 field to a new value. */
+#define DMA_WR_INT_INT7(base, value) (DMA_RMW_INT(base, (DMA_INT_INT7_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT7(value)))
+#define DMA_BWR_INT_INT7(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT8[8] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT8 field. */
+#define DMA_RD_INT_INT8(base) ((DMA_INT_REG(base) & DMA_INT_INT8_MASK) >> DMA_INT_INT8_SHIFT)
+#define DMA_BRD_INT_INT8(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT8_SHIFT))
+
+/*! @brief Set the INT8 field to a new value. */
+#define DMA_WR_INT_INT8(base, value) (DMA_RMW_INT(base, (DMA_INT_INT8_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT8(value)))
+#define DMA_BWR_INT_INT8(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT9[9] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT9 field. */
+#define DMA_RD_INT_INT9(base) ((DMA_INT_REG(base) & DMA_INT_INT9_MASK) >> DMA_INT_INT9_SHIFT)
+#define DMA_BRD_INT_INT9(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT9_SHIFT))
+
+/*! @brief Set the INT9 field to a new value. */
+#define DMA_WR_INT_INT9(base, value) (DMA_RMW_INT(base, (DMA_INT_INT9_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT9(value)))
+#define DMA_BWR_INT_INT9(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT10[10] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT10 field. */
+#define DMA_RD_INT_INT10(base) ((DMA_INT_REG(base) & DMA_INT_INT10_MASK) >> DMA_INT_INT10_SHIFT)
+#define DMA_BRD_INT_INT10(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT10_SHIFT))
+
+/*! @brief Set the INT10 field to a new value. */
+#define DMA_WR_INT_INT10(base, value) (DMA_RMW_INT(base, (DMA_INT_INT10_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT10(value)))
+#define DMA_BWR_INT_INT10(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT11[11] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT11 field. */
+#define DMA_RD_INT_INT11(base) ((DMA_INT_REG(base) & DMA_INT_INT11_MASK) >> DMA_INT_INT11_SHIFT)
+#define DMA_BRD_INT_INT11(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT11_SHIFT))
+
+/*! @brief Set the INT11 field to a new value. */
+#define DMA_WR_INT_INT11(base, value) (DMA_RMW_INT(base, (DMA_INT_INT11_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT11(value)))
+#define DMA_BWR_INT_INT11(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT12[12] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT12 field. */
+#define DMA_RD_INT_INT12(base) ((DMA_INT_REG(base) & DMA_INT_INT12_MASK) >> DMA_INT_INT12_SHIFT)
+#define DMA_BRD_INT_INT12(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT12_SHIFT))
+
+/*! @brief Set the INT12 field to a new value. */
+#define DMA_WR_INT_INT12(base, value) (DMA_RMW_INT(base, (DMA_INT_INT12_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT12(value)))
+#define DMA_BWR_INT_INT12(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT13[13] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT13 field. */
+#define DMA_RD_INT_INT13(base) ((DMA_INT_REG(base) & DMA_INT_INT13_MASK) >> DMA_INT_INT13_SHIFT)
+#define DMA_BRD_INT_INT13(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT13_SHIFT))
+
+/*! @brief Set the INT13 field to a new value. */
+#define DMA_WR_INT_INT13(base, value) (DMA_RMW_INT(base, (DMA_INT_INT13_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT13(value)))
+#define DMA_BWR_INT_INT13(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT14[14] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT14 field. */
+#define DMA_RD_INT_INT14(base) ((DMA_INT_REG(base) & DMA_INT_INT14_MASK) >> DMA_INT_INT14_SHIFT)
+#define DMA_BRD_INT_INT14(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT14_SHIFT))
+
+/*! @brief Set the INT14 field to a new value. */
+#define DMA_WR_INT_INT14(base, value) (DMA_RMW_INT(base, (DMA_INT_INT14_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT15_MASK), DMA_INT_INT14(value)))
+#define DMA_BWR_INT_INT14(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT15[15] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT15 field. */
+#define DMA_RD_INT_INT15(base) ((DMA_INT_REG(base) & DMA_INT_INT15_MASK) >> DMA_INT_INT15_SHIFT)
+#define DMA_BRD_INT_INT15(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT15_SHIFT))
+
+/*! @brief Set the INT15 field to a new value. */
+#define DMA_WR_INT_INT15(base, value) (DMA_RMW_INT(base, (DMA_INT_INT15_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK), DMA_INT_INT15(value)))
+#define DMA_BWR_INT_INT15(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ERR - Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ERR - Error Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERR provides a bit map for the 16 channels, signaling the presence of an
+ * error for each channel. The eDMA engine signals the occurrence of an error
+ * condition by setting the appropriate bit in this register. The outputs of this
+ * register are enabled by the contents of the EEI, and then routed to the
+ * interrupt controller. During the execution of the interrupt-service routine associated
+ * with any DMA errors, it is software's responsibility to clear the appropriate
+ * bit, negating the error-interrupt request. Typically, a write to the CERR in
+ * the interrupt-service routine is used for this purpose. The normal DMA channel
+ * completion indicators (setting the transfer control descriptor DONE flag and
+ * the possible assertion of an interrupt request) are not affected when an error
+ * is detected. The contents of this register can also be polled because a
+ * non-zero value indicates the presence of a channel error regardless of the state of
+ * the EEI. The state of any given channel's error indicators is affected by
+ * writes to this register; it is also affected by writes to the CERR. On writes to
+ * the ERR, a one in any bit position clears the corresponding channel's error
+ * status. A zero in any bit position has no affect on the corresponding channel's
+ * current error status. The CERR is provided so the error indicator for a single
+ * channel can easily be cleared.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ERR register
+ */
+/*@{*/
+#define DMA_RD_ERR(base)         (DMA_ERR_REG(base))
+#define DMA_WR_ERR(base, value)  (DMA_ERR_REG(base) = (value))
+#define DMA_RMW_ERR(base, mask, value) (DMA_WR_ERR(base, (DMA_RD_ERR(base) & ~(mask)) | (value)))
+#define DMA_SET_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) |  (value)))
+#define DMA_CLR_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) & ~(value)))
+#define DMA_TOG_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ERR bitfields
+ */
+
+/*!
+ * @name Register DMA_ERR, field ERR0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR0 field. */
+#define DMA_RD_ERR_ERR0(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR0_MASK) >> DMA_ERR_ERR0_SHIFT)
+#define DMA_BRD_ERR_ERR0(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR0_SHIFT))
+
+/*! @brief Set the ERR0 field to a new value. */
+#define DMA_WR_ERR_ERR0(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR0(value)))
+#define DMA_BWR_ERR_ERR0(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR1 field. */
+#define DMA_RD_ERR_ERR1(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR1_MASK) >> DMA_ERR_ERR1_SHIFT)
+#define DMA_BRD_ERR_ERR1(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR1_SHIFT))
+
+/*! @brief Set the ERR1 field to a new value. */
+#define DMA_WR_ERR_ERR1(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR1_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR1(value)))
+#define DMA_BWR_ERR_ERR1(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR2 field. */
+#define DMA_RD_ERR_ERR2(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR2_MASK) >> DMA_ERR_ERR2_SHIFT)
+#define DMA_BRD_ERR_ERR2(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR2_SHIFT))
+
+/*! @brief Set the ERR2 field to a new value. */
+#define DMA_WR_ERR_ERR2(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR2_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR2(value)))
+#define DMA_BWR_ERR_ERR2(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR3 field. */
+#define DMA_RD_ERR_ERR3(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR3_MASK) >> DMA_ERR_ERR3_SHIFT)
+#define DMA_BRD_ERR_ERR3(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR3_SHIFT))
+
+/*! @brief Set the ERR3 field to a new value. */
+#define DMA_WR_ERR_ERR3(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR3_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR3(value)))
+#define DMA_BWR_ERR_ERR3(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR4[4] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR4 field. */
+#define DMA_RD_ERR_ERR4(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR4_MASK) >> DMA_ERR_ERR4_SHIFT)
+#define DMA_BRD_ERR_ERR4(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR4_SHIFT))
+
+/*! @brief Set the ERR4 field to a new value. */
+#define DMA_WR_ERR_ERR4(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR4_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR4(value)))
+#define DMA_BWR_ERR_ERR4(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR5[5] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR5 field. */
+#define DMA_RD_ERR_ERR5(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR5_MASK) >> DMA_ERR_ERR5_SHIFT)
+#define DMA_BRD_ERR_ERR5(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR5_SHIFT))
+
+/*! @brief Set the ERR5 field to a new value. */
+#define DMA_WR_ERR_ERR5(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR5_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR5(value)))
+#define DMA_BWR_ERR_ERR5(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR6[6] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR6 field. */
+#define DMA_RD_ERR_ERR6(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR6_MASK) >> DMA_ERR_ERR6_SHIFT)
+#define DMA_BRD_ERR_ERR6(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR6_SHIFT))
+
+/*! @brief Set the ERR6 field to a new value. */
+#define DMA_WR_ERR_ERR6(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR6_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR6(value)))
+#define DMA_BWR_ERR_ERR6(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR7[7] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR7 field. */
+#define DMA_RD_ERR_ERR7(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR7_MASK) >> DMA_ERR_ERR7_SHIFT)
+#define DMA_BRD_ERR_ERR7(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR7_SHIFT))
+
+/*! @brief Set the ERR7 field to a new value. */
+#define DMA_WR_ERR_ERR7(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR7_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR7(value)))
+#define DMA_BWR_ERR_ERR7(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR8[8] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR8 field. */
+#define DMA_RD_ERR_ERR8(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR8_MASK) >> DMA_ERR_ERR8_SHIFT)
+#define DMA_BRD_ERR_ERR8(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR8_SHIFT))
+
+/*! @brief Set the ERR8 field to a new value. */
+#define DMA_WR_ERR_ERR8(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR8_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR8(value)))
+#define DMA_BWR_ERR_ERR8(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR9[9] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR9 field. */
+#define DMA_RD_ERR_ERR9(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR9_MASK) >> DMA_ERR_ERR9_SHIFT)
+#define DMA_BRD_ERR_ERR9(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR9_SHIFT))
+
+/*! @brief Set the ERR9 field to a new value. */
+#define DMA_WR_ERR_ERR9(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR9_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR9(value)))
+#define DMA_BWR_ERR_ERR9(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR10[10] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR10 field. */
+#define DMA_RD_ERR_ERR10(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR10_MASK) >> DMA_ERR_ERR10_SHIFT)
+#define DMA_BRD_ERR_ERR10(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR10_SHIFT))
+
+/*! @brief Set the ERR10 field to a new value. */
+#define DMA_WR_ERR_ERR10(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR10_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR10(value)))
+#define DMA_BWR_ERR_ERR10(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR11[11] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR11 field. */
+#define DMA_RD_ERR_ERR11(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR11_MASK) >> DMA_ERR_ERR11_SHIFT)
+#define DMA_BRD_ERR_ERR11(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR11_SHIFT))
+
+/*! @brief Set the ERR11 field to a new value. */
+#define DMA_WR_ERR_ERR11(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR11_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR11(value)))
+#define DMA_BWR_ERR_ERR11(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR12[12] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR12 field. */
+#define DMA_RD_ERR_ERR12(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR12_MASK) >> DMA_ERR_ERR12_SHIFT)
+#define DMA_BRD_ERR_ERR12(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR12_SHIFT))
+
+/*! @brief Set the ERR12 field to a new value. */
+#define DMA_WR_ERR_ERR12(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR12_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR12(value)))
+#define DMA_BWR_ERR_ERR12(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR13[13] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR13 field. */
+#define DMA_RD_ERR_ERR13(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR13_MASK) >> DMA_ERR_ERR13_SHIFT)
+#define DMA_BRD_ERR_ERR13(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR13_SHIFT))
+
+/*! @brief Set the ERR13 field to a new value. */
+#define DMA_WR_ERR_ERR13(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR13_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR13(value)))
+#define DMA_BWR_ERR_ERR13(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR14[14] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR14 field. */
+#define DMA_RD_ERR_ERR14(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR14_MASK) >> DMA_ERR_ERR14_SHIFT)
+#define DMA_BRD_ERR_ERR14(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR14_SHIFT))
+
+/*! @brief Set the ERR14 field to a new value. */
+#define DMA_WR_ERR_ERR14(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR14_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR14(value)))
+#define DMA_BWR_ERR_ERR14(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR15[15] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR15 field. */
+#define DMA_RD_ERR_ERR15(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR15_MASK) >> DMA_ERR_ERR15_SHIFT)
+#define DMA_BRD_ERR_ERR15(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR15_SHIFT))
+
+/*! @brief Set the ERR15 field to a new value. */
+#define DMA_WR_ERR_ERR15(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR15_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK), DMA_ERR_ERR15(value)))
+#define DMA_BWR_ERR_ERR15(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_HRS - Hardware Request Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_HRS - Hardware Request Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The HRS register provides a bit map for the DMA channels, signaling the
+ * presence of a hardware request for each channel. The hardware request status bits
+ * reflect the current state of the register and qualified (via the ERQ fields)
+ * DMA request signals as seen by the DMA's arbitration logic. This view into the
+ * hardware request signals may be used for debug purposes. These bits reflect the
+ * state of the request as seen by the arbitration logic. Therefore, this status
+ * is affected by the ERQ bits.
+ */
+/*!
+ * @name Constants and macros for entire DMA_HRS register
+ */
+/*@{*/
+#define DMA_RD_HRS(base)         (DMA_HRS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_HRS bitfields
+ */
+
+/*!
+ * @name Register DMA_HRS, field HRS0[0] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 0 is not present
+ * - 0b1 - A hardware service request for channel 0 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS0 field. */
+#define DMA_RD_HRS_HRS0(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS0_MASK) >> DMA_HRS_HRS0_SHIFT)
+#define DMA_BRD_HRS_HRS0(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS1[1] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 1 is not present
+ * - 0b1 - A hardware service request for channel 1 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS1 field. */
+#define DMA_RD_HRS_HRS1(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS1_MASK) >> DMA_HRS_HRS1_SHIFT)
+#define DMA_BRD_HRS_HRS1(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS2[2] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 2 is not present
+ * - 0b1 - A hardware service request for channel 2 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS2 field. */
+#define DMA_RD_HRS_HRS2(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS2_MASK) >> DMA_HRS_HRS2_SHIFT)
+#define DMA_BRD_HRS_HRS2(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS2_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS3[3] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 3 is not present
+ * - 0b1 - A hardware service request for channel 3 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS3 field. */
+#define DMA_RD_HRS_HRS3(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS3_MASK) >> DMA_HRS_HRS3_SHIFT)
+#define DMA_BRD_HRS_HRS3(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS3_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS4[4] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 4 is not present
+ * - 0b1 - A hardware service request for channel 4 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS4 field. */
+#define DMA_RD_HRS_HRS4(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS4_MASK) >> DMA_HRS_HRS4_SHIFT)
+#define DMA_BRD_HRS_HRS4(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS4_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS5[5] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 5 is not present
+ * - 0b1 - A hardware service request for channel 5 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS5 field. */
+#define DMA_RD_HRS_HRS5(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS5_MASK) >> DMA_HRS_HRS5_SHIFT)
+#define DMA_BRD_HRS_HRS5(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS5_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS6[6] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 6 is not present
+ * - 0b1 - A hardware service request for channel 6 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS6 field. */
+#define DMA_RD_HRS_HRS6(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS6_MASK) >> DMA_HRS_HRS6_SHIFT)
+#define DMA_BRD_HRS_HRS6(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS6_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS7[7] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 7 is not present
+ * - 0b1 - A hardware service request for channel 7 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS7 field. */
+#define DMA_RD_HRS_HRS7(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS7_MASK) >> DMA_HRS_HRS7_SHIFT)
+#define DMA_BRD_HRS_HRS7(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS7_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS8[8] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 8 is not present
+ * - 0b1 - A hardware service request for channel 8 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS8 field. */
+#define DMA_RD_HRS_HRS8(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS8_MASK) >> DMA_HRS_HRS8_SHIFT)
+#define DMA_BRD_HRS_HRS8(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS8_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS9[9] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 9 is not present
+ * - 0b1 - A hardware service request for channel 9 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS9 field. */
+#define DMA_RD_HRS_HRS9(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS9_MASK) >> DMA_HRS_HRS9_SHIFT)
+#define DMA_BRD_HRS_HRS9(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS9_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS10[10] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 10 is not present
+ * - 0b1 - A hardware service request for channel 10 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS10 field. */
+#define DMA_RD_HRS_HRS10(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS10_MASK) >> DMA_HRS_HRS10_SHIFT)
+#define DMA_BRD_HRS_HRS10(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS10_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS11[11] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 11 is not present
+ * - 0b1 - A hardware service request for channel 11 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS11 field. */
+#define DMA_RD_HRS_HRS11(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS11_MASK) >> DMA_HRS_HRS11_SHIFT)
+#define DMA_BRD_HRS_HRS11(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS11_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS12[12] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 12 is not present
+ * - 0b1 - A hardware service request for channel 12 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS12 field. */
+#define DMA_RD_HRS_HRS12(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS12_MASK) >> DMA_HRS_HRS12_SHIFT)
+#define DMA_BRD_HRS_HRS12(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS12_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS13[13] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 13 is not present
+ * - 0b1 - A hardware service request for channel 13 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS13 field. */
+#define DMA_RD_HRS_HRS13(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS13_MASK) >> DMA_HRS_HRS13_SHIFT)
+#define DMA_BRD_HRS_HRS13(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS13_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS14[14] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 14 is not present
+ * - 0b1 - A hardware service request for channel 14 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS14 field. */
+#define DMA_RD_HRS_HRS14(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS14_MASK) >> DMA_HRS_HRS14_SHIFT)
+#define DMA_BRD_HRS_HRS14(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS14_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS15[15] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 15 is not present
+ * - 0b1 - A hardware service request for channel 15 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS15 field. */
+#define DMA_RD_HRS_HRS15(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS15_MASK) >> DMA_HRS_HRS15_SHIFT)
+#define DMA_BRD_HRS_HRS15(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS15_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI3 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI3 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI3 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI3(base)     (DMA_DCHPRI3_REG(base))
+#define DMA_WR_DCHPRI3(base, value) (DMA_DCHPRI3_REG(base) = (value))
+#define DMA_RMW_DCHPRI3(base, mask, value) (DMA_WR_DCHPRI3(base, (DMA_RD_DCHPRI3(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) |  (value)))
+#define DMA_CLR_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) & ~(value)))
+#define DMA_TOG_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI3 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI3, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_CHPRI field. */
+#define DMA_RD_DCHPRI3_CHPRI(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_CHPRI_MASK) >> DMA_DCHPRI3_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI3_CHPRI(base) (DMA_RD_DCHPRI3_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI3_CHPRI(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_CHPRI_MASK, DMA_DCHPRI3_CHPRI(value)))
+#define DMA_BWR_DCHPRI3_CHPRI(base, value) (DMA_WR_DCHPRI3_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI3, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_DPA field. */
+#define DMA_RD_DCHPRI3_DPA(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_DPA_MASK) >> DMA_DCHPRI3_DPA_SHIFT)
+#define DMA_BRD_DCHPRI3_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI3_DPA(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_DPA_MASK, DMA_DCHPRI3_DPA(value)))
+#define DMA_BWR_DCHPRI3_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI3, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_ECP field. */
+#define DMA_RD_DCHPRI3_ECP(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_ECP_MASK) >> DMA_DCHPRI3_ECP_SHIFT)
+#define DMA_BRD_DCHPRI3_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI3_ECP(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_ECP_MASK, DMA_DCHPRI3_ECP(value)))
+#define DMA_BWR_DCHPRI3_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI2 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI2 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI2 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI2(base)     (DMA_DCHPRI2_REG(base))
+#define DMA_WR_DCHPRI2(base, value) (DMA_DCHPRI2_REG(base) = (value))
+#define DMA_RMW_DCHPRI2(base, mask, value) (DMA_WR_DCHPRI2(base, (DMA_RD_DCHPRI2(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) |  (value)))
+#define DMA_CLR_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) & ~(value)))
+#define DMA_TOG_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI2 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI2, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_CHPRI field. */
+#define DMA_RD_DCHPRI2_CHPRI(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_CHPRI_MASK) >> DMA_DCHPRI2_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI2_CHPRI(base) (DMA_RD_DCHPRI2_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI2_CHPRI(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_CHPRI_MASK, DMA_DCHPRI2_CHPRI(value)))
+#define DMA_BWR_DCHPRI2_CHPRI(base, value) (DMA_WR_DCHPRI2_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI2, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_DPA field. */
+#define DMA_RD_DCHPRI2_DPA(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_DPA_MASK) >> DMA_DCHPRI2_DPA_SHIFT)
+#define DMA_BRD_DCHPRI2_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI2_DPA(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_DPA_MASK, DMA_DCHPRI2_DPA(value)))
+#define DMA_BWR_DCHPRI2_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI2, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_ECP field. */
+#define DMA_RD_DCHPRI2_ECP(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_ECP_MASK) >> DMA_DCHPRI2_ECP_SHIFT)
+#define DMA_BRD_DCHPRI2_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI2_ECP(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_ECP_MASK, DMA_DCHPRI2_ECP(value)))
+#define DMA_BWR_DCHPRI2_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI1 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI1 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI1 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI1(base)     (DMA_DCHPRI1_REG(base))
+#define DMA_WR_DCHPRI1(base, value) (DMA_DCHPRI1_REG(base) = (value))
+#define DMA_RMW_DCHPRI1(base, mask, value) (DMA_WR_DCHPRI1(base, (DMA_RD_DCHPRI1(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) |  (value)))
+#define DMA_CLR_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) & ~(value)))
+#define DMA_TOG_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI1 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI1, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_CHPRI field. */
+#define DMA_RD_DCHPRI1_CHPRI(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_CHPRI_MASK) >> DMA_DCHPRI1_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI1_CHPRI(base) (DMA_RD_DCHPRI1_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI1_CHPRI(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_CHPRI_MASK, DMA_DCHPRI1_CHPRI(value)))
+#define DMA_BWR_DCHPRI1_CHPRI(base, value) (DMA_WR_DCHPRI1_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI1, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_DPA field. */
+#define DMA_RD_DCHPRI1_DPA(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_DPA_MASK) >> DMA_DCHPRI1_DPA_SHIFT)
+#define DMA_BRD_DCHPRI1_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI1_DPA(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_DPA_MASK, DMA_DCHPRI1_DPA(value)))
+#define DMA_BWR_DCHPRI1_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI1, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_ECP field. */
+#define DMA_RD_DCHPRI1_ECP(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_ECP_MASK) >> DMA_DCHPRI1_ECP_SHIFT)
+#define DMA_BRD_DCHPRI1_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI1_ECP(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_ECP_MASK, DMA_DCHPRI1_ECP(value)))
+#define DMA_BWR_DCHPRI1_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI0 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI0 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI0 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI0(base)     (DMA_DCHPRI0_REG(base))
+#define DMA_WR_DCHPRI0(base, value) (DMA_DCHPRI0_REG(base) = (value))
+#define DMA_RMW_DCHPRI0(base, mask, value) (DMA_WR_DCHPRI0(base, (DMA_RD_DCHPRI0(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) |  (value)))
+#define DMA_CLR_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) & ~(value)))
+#define DMA_TOG_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI0 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI0, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_CHPRI field. */
+#define DMA_RD_DCHPRI0_CHPRI(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_CHPRI_MASK) >> DMA_DCHPRI0_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI0_CHPRI(base) (DMA_RD_DCHPRI0_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI0_CHPRI(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_CHPRI_MASK, DMA_DCHPRI0_CHPRI(value)))
+#define DMA_BWR_DCHPRI0_CHPRI(base, value) (DMA_WR_DCHPRI0_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI0, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_DPA field. */
+#define DMA_RD_DCHPRI0_DPA(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_DPA_MASK) >> DMA_DCHPRI0_DPA_SHIFT)
+#define DMA_BRD_DCHPRI0_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI0_DPA(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_DPA_MASK, DMA_DCHPRI0_DPA(value)))
+#define DMA_BWR_DCHPRI0_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI0, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_ECP field. */
+#define DMA_RD_DCHPRI0_ECP(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_ECP_MASK) >> DMA_DCHPRI0_ECP_SHIFT)
+#define DMA_BRD_DCHPRI0_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI0_ECP(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_ECP_MASK, DMA_DCHPRI0_ECP(value)))
+#define DMA_BWR_DCHPRI0_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI7 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI7 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI7 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI7(base)     (DMA_DCHPRI7_REG(base))
+#define DMA_WR_DCHPRI7(base, value) (DMA_DCHPRI7_REG(base) = (value))
+#define DMA_RMW_DCHPRI7(base, mask, value) (DMA_WR_DCHPRI7(base, (DMA_RD_DCHPRI7(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) |  (value)))
+#define DMA_CLR_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) & ~(value)))
+#define DMA_TOG_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI7 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI7, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_CHPRI field. */
+#define DMA_RD_DCHPRI7_CHPRI(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_CHPRI_MASK) >> DMA_DCHPRI7_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI7_CHPRI(base) (DMA_RD_DCHPRI7_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI7_CHPRI(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_CHPRI_MASK, DMA_DCHPRI7_CHPRI(value)))
+#define DMA_BWR_DCHPRI7_CHPRI(base, value) (DMA_WR_DCHPRI7_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI7, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_DPA field. */
+#define DMA_RD_DCHPRI7_DPA(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_DPA_MASK) >> DMA_DCHPRI7_DPA_SHIFT)
+#define DMA_BRD_DCHPRI7_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI7_DPA(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_DPA_MASK, DMA_DCHPRI7_DPA(value)))
+#define DMA_BWR_DCHPRI7_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI7, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_ECP field. */
+#define DMA_RD_DCHPRI7_ECP(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_ECP_MASK) >> DMA_DCHPRI7_ECP_SHIFT)
+#define DMA_BRD_DCHPRI7_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI7_ECP(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_ECP_MASK, DMA_DCHPRI7_ECP(value)))
+#define DMA_BWR_DCHPRI7_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI6 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI6 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI6 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI6(base)     (DMA_DCHPRI6_REG(base))
+#define DMA_WR_DCHPRI6(base, value) (DMA_DCHPRI6_REG(base) = (value))
+#define DMA_RMW_DCHPRI6(base, mask, value) (DMA_WR_DCHPRI6(base, (DMA_RD_DCHPRI6(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) |  (value)))
+#define DMA_CLR_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) & ~(value)))
+#define DMA_TOG_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI6 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI6, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_CHPRI field. */
+#define DMA_RD_DCHPRI6_CHPRI(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_CHPRI_MASK) >> DMA_DCHPRI6_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI6_CHPRI(base) (DMA_RD_DCHPRI6_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI6_CHPRI(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_CHPRI_MASK, DMA_DCHPRI6_CHPRI(value)))
+#define DMA_BWR_DCHPRI6_CHPRI(base, value) (DMA_WR_DCHPRI6_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI6, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_DPA field. */
+#define DMA_RD_DCHPRI6_DPA(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_DPA_MASK) >> DMA_DCHPRI6_DPA_SHIFT)
+#define DMA_BRD_DCHPRI6_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI6_DPA(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_DPA_MASK, DMA_DCHPRI6_DPA(value)))
+#define DMA_BWR_DCHPRI6_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI6, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_ECP field. */
+#define DMA_RD_DCHPRI6_ECP(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_ECP_MASK) >> DMA_DCHPRI6_ECP_SHIFT)
+#define DMA_BRD_DCHPRI6_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI6_ECP(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_ECP_MASK, DMA_DCHPRI6_ECP(value)))
+#define DMA_BWR_DCHPRI6_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI5 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI5 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI5 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI5(base)     (DMA_DCHPRI5_REG(base))
+#define DMA_WR_DCHPRI5(base, value) (DMA_DCHPRI5_REG(base) = (value))
+#define DMA_RMW_DCHPRI5(base, mask, value) (DMA_WR_DCHPRI5(base, (DMA_RD_DCHPRI5(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) |  (value)))
+#define DMA_CLR_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) & ~(value)))
+#define DMA_TOG_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI5 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI5, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_CHPRI field. */
+#define DMA_RD_DCHPRI5_CHPRI(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_CHPRI_MASK) >> DMA_DCHPRI5_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI5_CHPRI(base) (DMA_RD_DCHPRI5_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI5_CHPRI(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_CHPRI_MASK, DMA_DCHPRI5_CHPRI(value)))
+#define DMA_BWR_DCHPRI5_CHPRI(base, value) (DMA_WR_DCHPRI5_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI5, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_DPA field. */
+#define DMA_RD_DCHPRI5_DPA(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_DPA_MASK) >> DMA_DCHPRI5_DPA_SHIFT)
+#define DMA_BRD_DCHPRI5_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI5_DPA(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_DPA_MASK, DMA_DCHPRI5_DPA(value)))
+#define DMA_BWR_DCHPRI5_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI5, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_ECP field. */
+#define DMA_RD_DCHPRI5_ECP(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_ECP_MASK) >> DMA_DCHPRI5_ECP_SHIFT)
+#define DMA_BRD_DCHPRI5_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI5_ECP(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_ECP_MASK, DMA_DCHPRI5_ECP(value)))
+#define DMA_BWR_DCHPRI5_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI4 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI4 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI4 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI4(base)     (DMA_DCHPRI4_REG(base))
+#define DMA_WR_DCHPRI4(base, value) (DMA_DCHPRI4_REG(base) = (value))
+#define DMA_RMW_DCHPRI4(base, mask, value) (DMA_WR_DCHPRI4(base, (DMA_RD_DCHPRI4(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) |  (value)))
+#define DMA_CLR_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) & ~(value)))
+#define DMA_TOG_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI4 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI4, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_CHPRI field. */
+#define DMA_RD_DCHPRI4_CHPRI(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_CHPRI_MASK) >> DMA_DCHPRI4_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI4_CHPRI(base) (DMA_RD_DCHPRI4_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI4_CHPRI(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_CHPRI_MASK, DMA_DCHPRI4_CHPRI(value)))
+#define DMA_BWR_DCHPRI4_CHPRI(base, value) (DMA_WR_DCHPRI4_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI4, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_DPA field. */
+#define DMA_RD_DCHPRI4_DPA(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_DPA_MASK) >> DMA_DCHPRI4_DPA_SHIFT)
+#define DMA_BRD_DCHPRI4_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI4_DPA(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_DPA_MASK, DMA_DCHPRI4_DPA(value)))
+#define DMA_BWR_DCHPRI4_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI4, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_ECP field. */
+#define DMA_RD_DCHPRI4_ECP(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_ECP_MASK) >> DMA_DCHPRI4_ECP_SHIFT)
+#define DMA_BRD_DCHPRI4_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI4_ECP(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_ECP_MASK, DMA_DCHPRI4_ECP(value)))
+#define DMA_BWR_DCHPRI4_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI11 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI11 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI11 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI11(base)    (DMA_DCHPRI11_REG(base))
+#define DMA_WR_DCHPRI11(base, value) (DMA_DCHPRI11_REG(base) = (value))
+#define DMA_RMW_DCHPRI11(base, mask, value) (DMA_WR_DCHPRI11(base, (DMA_RD_DCHPRI11(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) |  (value)))
+#define DMA_CLR_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) & ~(value)))
+#define DMA_TOG_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI11 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI11, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_CHPRI field. */
+#define DMA_RD_DCHPRI11_CHPRI(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_CHPRI_MASK) >> DMA_DCHPRI11_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI11_CHPRI(base) (DMA_RD_DCHPRI11_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI11_CHPRI(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_CHPRI_MASK, DMA_DCHPRI11_CHPRI(value)))
+#define DMA_BWR_DCHPRI11_CHPRI(base, value) (DMA_WR_DCHPRI11_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI11, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_DPA field. */
+#define DMA_RD_DCHPRI11_DPA(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_DPA_MASK) >> DMA_DCHPRI11_DPA_SHIFT)
+#define DMA_BRD_DCHPRI11_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI11_DPA(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_DPA_MASK, DMA_DCHPRI11_DPA(value)))
+#define DMA_BWR_DCHPRI11_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI11, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_ECP field. */
+#define DMA_RD_DCHPRI11_ECP(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_ECP_MASK) >> DMA_DCHPRI11_ECP_SHIFT)
+#define DMA_BRD_DCHPRI11_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI11_ECP(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_ECP_MASK, DMA_DCHPRI11_ECP(value)))
+#define DMA_BWR_DCHPRI11_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI10 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI10 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI10 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI10(base)    (DMA_DCHPRI10_REG(base))
+#define DMA_WR_DCHPRI10(base, value) (DMA_DCHPRI10_REG(base) = (value))
+#define DMA_RMW_DCHPRI10(base, mask, value) (DMA_WR_DCHPRI10(base, (DMA_RD_DCHPRI10(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) |  (value)))
+#define DMA_CLR_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) & ~(value)))
+#define DMA_TOG_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI10 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI10, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_CHPRI field. */
+#define DMA_RD_DCHPRI10_CHPRI(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_CHPRI_MASK) >> DMA_DCHPRI10_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI10_CHPRI(base) (DMA_RD_DCHPRI10_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI10_CHPRI(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_CHPRI_MASK, DMA_DCHPRI10_CHPRI(value)))
+#define DMA_BWR_DCHPRI10_CHPRI(base, value) (DMA_WR_DCHPRI10_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI10, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_DPA field. */
+#define DMA_RD_DCHPRI10_DPA(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_DPA_MASK) >> DMA_DCHPRI10_DPA_SHIFT)
+#define DMA_BRD_DCHPRI10_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI10_DPA(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_DPA_MASK, DMA_DCHPRI10_DPA(value)))
+#define DMA_BWR_DCHPRI10_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI10, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_ECP field. */
+#define DMA_RD_DCHPRI10_ECP(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_ECP_MASK) >> DMA_DCHPRI10_ECP_SHIFT)
+#define DMA_BRD_DCHPRI10_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI10_ECP(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_ECP_MASK, DMA_DCHPRI10_ECP(value)))
+#define DMA_BWR_DCHPRI10_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI9 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI9 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI9 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI9(base)     (DMA_DCHPRI9_REG(base))
+#define DMA_WR_DCHPRI9(base, value) (DMA_DCHPRI9_REG(base) = (value))
+#define DMA_RMW_DCHPRI9(base, mask, value) (DMA_WR_DCHPRI9(base, (DMA_RD_DCHPRI9(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) |  (value)))
+#define DMA_CLR_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) & ~(value)))
+#define DMA_TOG_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI9 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI9, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_CHPRI field. */
+#define DMA_RD_DCHPRI9_CHPRI(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_CHPRI_MASK) >> DMA_DCHPRI9_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI9_CHPRI(base) (DMA_RD_DCHPRI9_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI9_CHPRI(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_CHPRI_MASK, DMA_DCHPRI9_CHPRI(value)))
+#define DMA_BWR_DCHPRI9_CHPRI(base, value) (DMA_WR_DCHPRI9_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI9, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_DPA field. */
+#define DMA_RD_DCHPRI9_DPA(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_DPA_MASK) >> DMA_DCHPRI9_DPA_SHIFT)
+#define DMA_BRD_DCHPRI9_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI9_DPA(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_DPA_MASK, DMA_DCHPRI9_DPA(value)))
+#define DMA_BWR_DCHPRI9_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI9, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_ECP field. */
+#define DMA_RD_DCHPRI9_ECP(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_ECP_MASK) >> DMA_DCHPRI9_ECP_SHIFT)
+#define DMA_BRD_DCHPRI9_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI9_ECP(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_ECP_MASK, DMA_DCHPRI9_ECP(value)))
+#define DMA_BWR_DCHPRI9_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI8 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI8 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI8 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI8(base)     (DMA_DCHPRI8_REG(base))
+#define DMA_WR_DCHPRI8(base, value) (DMA_DCHPRI8_REG(base) = (value))
+#define DMA_RMW_DCHPRI8(base, mask, value) (DMA_WR_DCHPRI8(base, (DMA_RD_DCHPRI8(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) |  (value)))
+#define DMA_CLR_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) & ~(value)))
+#define DMA_TOG_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI8 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI8, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_CHPRI field. */
+#define DMA_RD_DCHPRI8_CHPRI(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_CHPRI_MASK) >> DMA_DCHPRI8_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI8_CHPRI(base) (DMA_RD_DCHPRI8_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI8_CHPRI(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_CHPRI_MASK, DMA_DCHPRI8_CHPRI(value)))
+#define DMA_BWR_DCHPRI8_CHPRI(base, value) (DMA_WR_DCHPRI8_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI8, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_DPA field. */
+#define DMA_RD_DCHPRI8_DPA(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_DPA_MASK) >> DMA_DCHPRI8_DPA_SHIFT)
+#define DMA_BRD_DCHPRI8_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI8_DPA(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_DPA_MASK, DMA_DCHPRI8_DPA(value)))
+#define DMA_BWR_DCHPRI8_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI8, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_ECP field. */
+#define DMA_RD_DCHPRI8_ECP(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_ECP_MASK) >> DMA_DCHPRI8_ECP_SHIFT)
+#define DMA_BRD_DCHPRI8_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI8_ECP(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_ECP_MASK, DMA_DCHPRI8_ECP(value)))
+#define DMA_BWR_DCHPRI8_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI15 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI15 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI15 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI15(base)    (DMA_DCHPRI15_REG(base))
+#define DMA_WR_DCHPRI15(base, value) (DMA_DCHPRI15_REG(base) = (value))
+#define DMA_RMW_DCHPRI15(base, mask, value) (DMA_WR_DCHPRI15(base, (DMA_RD_DCHPRI15(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) |  (value)))
+#define DMA_CLR_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) & ~(value)))
+#define DMA_TOG_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI15 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI15, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_CHPRI field. */
+#define DMA_RD_DCHPRI15_CHPRI(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_CHPRI_MASK) >> DMA_DCHPRI15_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI15_CHPRI(base) (DMA_RD_DCHPRI15_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI15_CHPRI(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_CHPRI_MASK, DMA_DCHPRI15_CHPRI(value)))
+#define DMA_BWR_DCHPRI15_CHPRI(base, value) (DMA_WR_DCHPRI15_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI15, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_DPA field. */
+#define DMA_RD_DCHPRI15_DPA(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_DPA_MASK) >> DMA_DCHPRI15_DPA_SHIFT)
+#define DMA_BRD_DCHPRI15_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI15_DPA(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_DPA_MASK, DMA_DCHPRI15_DPA(value)))
+#define DMA_BWR_DCHPRI15_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI15, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_ECP field. */
+#define DMA_RD_DCHPRI15_ECP(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_ECP_MASK) >> DMA_DCHPRI15_ECP_SHIFT)
+#define DMA_BRD_DCHPRI15_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI15_ECP(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_ECP_MASK, DMA_DCHPRI15_ECP(value)))
+#define DMA_BWR_DCHPRI15_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI14 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI14 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI14 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI14(base)    (DMA_DCHPRI14_REG(base))
+#define DMA_WR_DCHPRI14(base, value) (DMA_DCHPRI14_REG(base) = (value))
+#define DMA_RMW_DCHPRI14(base, mask, value) (DMA_WR_DCHPRI14(base, (DMA_RD_DCHPRI14(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) |  (value)))
+#define DMA_CLR_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) & ~(value)))
+#define DMA_TOG_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI14 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI14, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_CHPRI field. */
+#define DMA_RD_DCHPRI14_CHPRI(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_CHPRI_MASK) >> DMA_DCHPRI14_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI14_CHPRI(base) (DMA_RD_DCHPRI14_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI14_CHPRI(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_CHPRI_MASK, DMA_DCHPRI14_CHPRI(value)))
+#define DMA_BWR_DCHPRI14_CHPRI(base, value) (DMA_WR_DCHPRI14_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI14, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_DPA field. */
+#define DMA_RD_DCHPRI14_DPA(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_DPA_MASK) >> DMA_DCHPRI14_DPA_SHIFT)
+#define DMA_BRD_DCHPRI14_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI14_DPA(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_DPA_MASK, DMA_DCHPRI14_DPA(value)))
+#define DMA_BWR_DCHPRI14_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI14, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_ECP field. */
+#define DMA_RD_DCHPRI14_ECP(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_ECP_MASK) >> DMA_DCHPRI14_ECP_SHIFT)
+#define DMA_BRD_DCHPRI14_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI14_ECP(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_ECP_MASK, DMA_DCHPRI14_ECP(value)))
+#define DMA_BWR_DCHPRI14_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI13 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI13 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI13 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI13(base)    (DMA_DCHPRI13_REG(base))
+#define DMA_WR_DCHPRI13(base, value) (DMA_DCHPRI13_REG(base) = (value))
+#define DMA_RMW_DCHPRI13(base, mask, value) (DMA_WR_DCHPRI13(base, (DMA_RD_DCHPRI13(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) |  (value)))
+#define DMA_CLR_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) & ~(value)))
+#define DMA_TOG_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI13 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI13, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_CHPRI field. */
+#define DMA_RD_DCHPRI13_CHPRI(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_CHPRI_MASK) >> DMA_DCHPRI13_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI13_CHPRI(base) (DMA_RD_DCHPRI13_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI13_CHPRI(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_CHPRI_MASK, DMA_DCHPRI13_CHPRI(value)))
+#define DMA_BWR_DCHPRI13_CHPRI(base, value) (DMA_WR_DCHPRI13_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI13, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_DPA field. */
+#define DMA_RD_DCHPRI13_DPA(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_DPA_MASK) >> DMA_DCHPRI13_DPA_SHIFT)
+#define DMA_BRD_DCHPRI13_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI13_DPA(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_DPA_MASK, DMA_DCHPRI13_DPA(value)))
+#define DMA_BWR_DCHPRI13_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI13, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_ECP field. */
+#define DMA_RD_DCHPRI13_ECP(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_ECP_MASK) >> DMA_DCHPRI13_ECP_SHIFT)
+#define DMA_BRD_DCHPRI13_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI13_ECP(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_ECP_MASK, DMA_DCHPRI13_ECP(value)))
+#define DMA_BWR_DCHPRI13_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI12 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI12 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI12 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI12(base)    (DMA_DCHPRI12_REG(base))
+#define DMA_WR_DCHPRI12(base, value) (DMA_DCHPRI12_REG(base) = (value))
+#define DMA_RMW_DCHPRI12(base, mask, value) (DMA_WR_DCHPRI12(base, (DMA_RD_DCHPRI12(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) |  (value)))
+#define DMA_CLR_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) & ~(value)))
+#define DMA_TOG_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI12 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI12, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_CHPRI field. */
+#define DMA_RD_DCHPRI12_CHPRI(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_CHPRI_MASK) >> DMA_DCHPRI12_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI12_CHPRI(base) (DMA_RD_DCHPRI12_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI12_CHPRI(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_CHPRI_MASK, DMA_DCHPRI12_CHPRI(value)))
+#define DMA_BWR_DCHPRI12_CHPRI(base, value) (DMA_WR_DCHPRI12_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI12, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_DPA field. */
+#define DMA_RD_DCHPRI12_DPA(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_DPA_MASK) >> DMA_DCHPRI12_DPA_SHIFT)
+#define DMA_BRD_DCHPRI12_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI12_DPA(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_DPA_MASK, DMA_DCHPRI12_DPA(value)))
+#define DMA_BWR_DCHPRI12_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI12, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_ECP field. */
+#define DMA_RD_DCHPRI12_ECP(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_ECP_MASK) >> DMA_DCHPRI12_ECP_SHIFT)
+#define DMA_BRD_DCHPRI12_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI12_ECP(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_ECP_MASK, DMA_DCHPRI12_ECP(value)))
+#define DMA_BWR_DCHPRI12_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SADDR - TCD Source Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SADDR - TCD Source Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SADDR register
+ */
+/*@{*/
+#define DMA_RD_SADDR(base, index) (DMA_SADDR_REG(base, index))
+#define DMA_WR_SADDR(base, index, value) (DMA_SADDR_REG(base, index) = (value))
+#define DMA_RMW_SADDR(base, index, mask, value) (DMA_WR_SADDR(base, index, (DMA_RD_SADDR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) |  (value)))
+#define DMA_CLR_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) & ~(value)))
+#define DMA_TOG_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SOFF - TCD Signed Source Address Offset
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SOFF - TCD Signed Source Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SOFF register
+ */
+/*@{*/
+#define DMA_RD_SOFF(base, index) (DMA_SOFF_REG(base, index))
+#define DMA_WR_SOFF(base, index, value) (DMA_SOFF_REG(base, index) = (value))
+#define DMA_RMW_SOFF(base, index, mask, value) (DMA_WR_SOFF(base, index, (DMA_RD_SOFF(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) |  (value)))
+#define DMA_CLR_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) & ~(value)))
+#define DMA_TOG_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ATTR - TCD Transfer Attributes
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ATTR - TCD Transfer Attributes (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_ATTR register
+ */
+/*@{*/
+#define DMA_RD_ATTR(base, index) (DMA_ATTR_REG(base, index))
+#define DMA_WR_ATTR(base, index, value) (DMA_ATTR_REG(base, index) = (value))
+#define DMA_RMW_ATTR(base, index, mask, value) (DMA_WR_ATTR(base, index, (DMA_RD_ATTR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) |  (value)))
+#define DMA_CLR_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) & ~(value)))
+#define DMA_TOG_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ATTR bitfields
+ */
+
+/*!
+ * @name Register DMA_ATTR, field DSIZE[2:0] (RW)
+ *
+ * See the SSIZE definition
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_DSIZE field. */
+#define DMA_RD_ATTR_DSIZE(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_DSIZE_MASK) >> DMA_ATTR_DSIZE_SHIFT)
+#define DMA_BRD_ATTR_DSIZE(base, index) (DMA_RD_ATTR_DSIZE(base, index))
+
+/*! @brief Set the DSIZE field to a new value. */
+#define DMA_WR_ATTR_DSIZE(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_DSIZE_MASK, DMA_ATTR_DSIZE(value)))
+#define DMA_BWR_ATTR_DSIZE(base, index, value) (DMA_WR_ATTR_DSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field DMOD[7:3] (RW)
+ *
+ * See the SMOD definition
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_DMOD field. */
+#define DMA_RD_ATTR_DMOD(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_DMOD_MASK) >> DMA_ATTR_DMOD_SHIFT)
+#define DMA_BRD_ATTR_DMOD(base, index) (DMA_RD_ATTR_DMOD(base, index))
+
+/*! @brief Set the DMOD field to a new value. */
+#define DMA_WR_ATTR_DMOD(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_DMOD_MASK, DMA_ATTR_DMOD(value)))
+#define DMA_BWR_ATTR_DMOD(base, index, value) (DMA_WR_ATTR_DMOD(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field SSIZE[10:8] (RW)
+ *
+ * The attempted use of a Reserved encoding causes a configuration error.
+ *
+ * Values:
+ * - 0b000 - 8-bit
+ * - 0b001 - 16-bit
+ * - 0b010 - 32-bit
+ * - 0b011 - Reserved
+ * - 0b100 - 16-byte
+ * - 0b101 - 32-byte
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_SSIZE field. */
+#define DMA_RD_ATTR_SSIZE(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_SSIZE_MASK) >> DMA_ATTR_SSIZE_SHIFT)
+#define DMA_BRD_ATTR_SSIZE(base, index) (DMA_RD_ATTR_SSIZE(base, index))
+
+/*! @brief Set the SSIZE field to a new value. */
+#define DMA_WR_ATTR_SSIZE(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_SSIZE_MASK, DMA_ATTR_SSIZE(value)))
+#define DMA_BWR_ATTR_SSIZE(base, index, value) (DMA_WR_ATTR_SSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field SMOD[15:11] (RW)
+ *
+ * Values:
+ * - 0b00000 - Source address modulo feature is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_SMOD field. */
+#define DMA_RD_ATTR_SMOD(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_SMOD_MASK) >> DMA_ATTR_SMOD_SHIFT)
+#define DMA_BRD_ATTR_SMOD(base, index) (DMA_RD_ATTR_SMOD(base, index))
+
+/*! @brief Set the SMOD field to a new value. */
+#define DMA_WR_ATTR_SMOD(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_SMOD_MASK, DMA_ATTR_SMOD(value)))
+#define DMA_BWR_ATTR_SMOD(base, index, value) (DMA_WR_ATTR_SMOD(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
+ * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
+ * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
+ * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLOFFYES register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLOFFYES(base, index) (DMA_NBYTES_MLOFFYES_REG(base, index))
+#define DMA_WR_NBYTES_MLOFFYES(base, index, value) (DMA_NBYTES_MLOFFYES_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLOFFYES(base, index, mask, value) (DMA_WR_NBYTES_MLOFFYES(base, index, (DMA_RD_NBYTES_MLOFFYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_NBYTES_MLOFFYES bitfields
+ */
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted.
+ * (Although, it may be stalled by using the bandwidth control field, or via
+ * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
+ * written back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_NBYTES field. */
+#define DMA_RD_NBYTES_MLOFFYES_NBYTES(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) >> DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_NBYTES(base, index) (DMA_RD_NBYTES_MLOFFYES_NBYTES(base, index))
+
+/*! @brief Set the NBYTES field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_NBYTES(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_NBYTES_MASK, DMA_NBYTES_MLOFFYES_NBYTES(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_NBYTES(base, index, value) (DMA_WR_NBYTES_MLOFFYES_NBYTES(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_MLOFF field. */
+#define DMA_RD_NBYTES_MLOFFYES_MLOFF(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) >> DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_MLOFF(base, index) (DMA_RD_NBYTES_MLOFFYES_MLOFF(base, index))
+
+/*! @brief Set the MLOFF field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_MLOFF(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_MLOFF_MASK, DMA_NBYTES_MLOFFYES_MLOFF(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_MLOFF(base, index, value) (DMA_WR_NBYTES_MLOFFYES_MLOFF(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the DADDR
+ * - 0b1 - The minor loop offset is applied to the DADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_DMLOE field. */
+#define DMA_RD_NBYTES_MLOFFYES_DMLOE(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) >> DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_DMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))
+
+/*! @brief Set the DMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_DMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_DMLOE_MASK, DMA_NBYTES_MLOFFYES_DMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_DMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_DMLOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the SADDR
+ * - 0b1 - The minor loop offset is applied to the SADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_SMLOE field. */
+#define DMA_RD_NBYTES_MLOFFYES_SMLOE(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) >> DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_SMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))
+
+/*! @brief Set the SMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_SMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_SMLOE_MASK, DMA_NBYTES_MLOFFYES_SMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_SMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_SMLOE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
+ * register to use depends on whether minor loop mapping is disabled, enabled but not
+ * used for this channel, or enabled and used. TCD word 2 is defined as follows
+ * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
+ * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
+ * for TCD word 2's definition.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLNO register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLNO(base, index) (DMA_NBYTES_MLNO_REG(base, index))
+#define DMA_WR_NBYTES_MLNO(base, index, value) (DMA_NBYTES_MLNO_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLNO(base, index, mask, value) (DMA_WR_NBYTES_MLNO(base, index, (DMA_RD_NBYTES_MLNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
+ * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
+ * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
+ * the TCD_NBYTES_MLNO register description.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLOFFNO register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLOFFNO(base, index) (DMA_NBYTES_MLOFFNO_REG(base, index))
+#define DMA_WR_NBYTES_MLOFFNO(base, index, value) (DMA_NBYTES_MLOFFNO_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLOFFNO(base, index, mask, value) (DMA_WR_NBYTES_MLOFFNO(base, index, (DMA_RD_NBYTES_MLOFFNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_NBYTES_MLOFFNO bitfields
+ */
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted;
+ * although, it may be stalled by using the bandwidth control field, or via
+ * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
+ * back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_NBYTES field. */
+#define DMA_RD_NBYTES_MLOFFNO_NBYTES(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) >> DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_NBYTES(base, index) (DMA_RD_NBYTES_MLOFFNO_NBYTES(base, index))
+
+/*! @brief Set the NBYTES field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_NBYTES(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_NBYTES_MASK, DMA_NBYTES_MLOFFNO_NBYTES(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_NBYTES(base, index, value) (DMA_WR_NBYTES_MLOFFNO_NBYTES(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the DADDR
+ * - 0b1 - The minor loop offset is applied to the DADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_DMLOE field. */
+#define DMA_RD_NBYTES_MLOFFNO_DMLOE(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) >> DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_DMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))
+
+/*! @brief Set the DMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_DMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_DMLOE_MASK, DMA_NBYTES_MLOFFNO_DMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_DMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_DMLOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the SADDR
+ * - 0b1 - The minor loop offset is applied to the SADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_SMLOE field. */
+#define DMA_RD_NBYTES_MLOFFNO_SMLOE(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) >> DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_SMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))
+
+/*! @brief Set the SMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_SMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_SMLOE_MASK, DMA_NBYTES_MLOFFNO_SMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_SMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_SMLOE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SLAST - TCD Last Source Address Adjustment
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SLAST - TCD Last Source Address Adjustment (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SLAST register
+ */
+/*@{*/
+#define DMA_RD_SLAST(base, index) (DMA_SLAST_REG(base, index))
+#define DMA_WR_SLAST(base, index, value) (DMA_SLAST_REG(base, index) = (value))
+#define DMA_RMW_SLAST(base, index, mask, value) (DMA_WR_SLAST(base, index, (DMA_RD_SLAST(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) |  (value)))
+#define DMA_CLR_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) & ~(value)))
+#define DMA_TOG_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DADDR - TCD Destination Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DADDR - TCD Destination Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DADDR register
+ */
+/*@{*/
+#define DMA_RD_DADDR(base, index) (DMA_DADDR_REG(base, index))
+#define DMA_WR_DADDR(base, index, value) (DMA_DADDR_REG(base, index) = (value))
+#define DMA_RMW_DADDR(base, index, mask, value) (DMA_WR_DADDR(base, index, (DMA_RD_DADDR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) |  (value)))
+#define DMA_CLR_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) & ~(value)))
+#define DMA_TOG_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DOFF - TCD Signed Destination Address Offset
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DOFF - TCD Signed Destination Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DOFF register
+ */
+/*@{*/
+#define DMA_RD_DOFF(base, index) (DMA_DOFF_REG(base, index))
+#define DMA_WR_DOFF(base, index, value) (DMA_DOFF_REG(base, index) = (value))
+#define DMA_RMW_DOFF(base, index, mask, value) (DMA_WR_DOFF(base, index, (DMA_RD_DOFF(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) |  (value)))
+#define DMA_CLR_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) & ~(value)))
+#define DMA_TOG_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
+ * follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CITER_ELINKNO register
+ */
+/*@{*/
+#define DMA_RD_CITER_ELINKNO(base, index) (DMA_CITER_ELINKNO_REG(base, index))
+#define DMA_WR_CITER_ELINKNO(base, index, value) (DMA_CITER_ELINKNO_REG(base, index) = (value))
+#define DMA_RMW_CITER_ELINKNO(base, index, mask, value) (DMA_WR_CITER_ELINKNO(base, index, (DMA_RD_CITER_ELINKNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) |  (value)))
+#define DMA_CLR_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) & ~(value)))
+#define DMA_TOG_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_CITER_ELINKNO, field CITER[14:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKNO_CITER field. */
+#define DMA_RD_CITER_ELINKNO_CITER(base, index) ((DMA_CITER_ELINKNO_REG(base, index) & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT)
+#define DMA_BRD_CITER_ELINKNO_CITER(base, index) (DMA_RD_CITER_ELINKNO_CITER(base, index))
+
+/*! @brief Set the CITER field to a new value. */
+#define DMA_WR_CITER_ELINKNO_CITER(base, index, value) (DMA_RMW_CITER_ELINKNO(base, index, DMA_CITER_ELINKNO_CITER_MASK, DMA_CITER_ELINKNO_CITER(value)))
+#define DMA_BWR_CITER_ELINKNO_CITER(base, index, value) (DMA_WR_CITER_ELINKNO_CITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKNO_ELINK field. */
+#define DMA_RD_CITER_ELINKNO_ELINK(base, index) ((DMA_CITER_ELINKNO_REG(base, index) & DMA_CITER_ELINKNO_ELINK_MASK) >> DMA_CITER_ELINKNO_ELINK_SHIFT)
+#define DMA_BRD_CITER_ELINKNO_ELINK(base, index) (BITBAND_ACCESS16(&DMA_CITER_ELINKNO_REG(base, index), DMA_CITER_ELINKNO_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_CITER_ELINKNO_ELINK(base, index, value) (DMA_RMW_CITER_ELINKNO(base, index, DMA_CITER_ELINKNO_ELINK_MASK, DMA_CITER_ELINKNO_ELINK(value)))
+#define DMA_BWR_CITER_ELINKNO_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CITER_ELINKNO_REG(base, index), DMA_CITER_ELINKNO_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CITER_ELINKYES register
+ */
+/*@{*/
+#define DMA_RD_CITER_ELINKYES(base, index) (DMA_CITER_ELINKYES_REG(base, index))
+#define DMA_WR_CITER_ELINKYES(base, index, value) (DMA_CITER_ELINKYES_REG(base, index) = (value))
+#define DMA_RMW_CITER_ELINKYES(base, index, mask, value) (DMA_WR_CITER_ELINKYES(base, index, (DMA_RD_CITER_ELINKYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) |  (value)))
+#define DMA_CLR_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) & ~(value)))
+#define DMA_TOG_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field CITER[8:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_CITER field. */
+#define DMA_RD_CITER_ELINKYES_CITER(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_CITER(base, index) (DMA_RD_CITER_ELINKYES_CITER(base, index))
+
+/*! @brief Set the CITER field to a new value. */
+#define DMA_WR_CITER_ELINKYES_CITER(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_CITER_MASK, DMA_CITER_ELINKYES_CITER(value)))
+#define DMA_BWR_CITER_ELINKYES_CITER(base, index, value) (DMA_WR_CITER_ELINKYES_CITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request to the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_LINKCH field. */
+#define DMA_RD_CITER_ELINKYES_LINKCH(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_LINKCH_MASK) >> DMA_CITER_ELINKYES_LINKCH_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_LINKCH(base, index) (DMA_RD_CITER_ELINKYES_LINKCH(base, index))
+
+/*! @brief Set the LINKCH field to a new value. */
+#define DMA_WR_CITER_ELINKYES_LINKCH(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_LINKCH_MASK, DMA_CITER_ELINKYES_LINKCH(value)))
+#define DMA_BWR_CITER_ELINKYES_LINKCH(base, index, value) (DMA_WR_CITER_ELINKYES_LINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_ELINK field. */
+#define DMA_RD_CITER_ELINKYES_ELINK(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_ELINK_MASK) >> DMA_CITER_ELINKYES_ELINK_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_ELINK(base, index) (BITBAND_ACCESS16(&DMA_CITER_ELINKYES_REG(base, index), DMA_CITER_ELINKYES_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_CITER_ELINKYES_ELINK(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_ELINK_MASK, DMA_CITER_ELINKYES_ELINK(value)))
+#define DMA_BWR_CITER_ELINKYES_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CITER_ELINKYES_REG(base, index), DMA_CITER_ELINKYES_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DLAST_SGA register
+ */
+/*@{*/
+#define DMA_RD_DLAST_SGA(base, index) (DMA_DLAST_SGA_REG(base, index))
+#define DMA_WR_DLAST_SGA(base, index, value) (DMA_DLAST_SGA_REG(base, index) = (value))
+#define DMA_RMW_DLAST_SGA(base, index, mask, value) (DMA_WR_DLAST_SGA(base, index, (DMA_RD_DLAST_SGA(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) |  (value)))
+#define DMA_CLR_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) & ~(value)))
+#define DMA_TOG_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CSR - TCD Control and Status
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CSR - TCD Control and Status (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_CSR register
+ */
+/*@{*/
+#define DMA_RD_CSR(base, index)  (DMA_CSR_REG(base, index))
+#define DMA_WR_CSR(base, index, value) (DMA_CSR_REG(base, index) = (value))
+#define DMA_RMW_CSR(base, index, mask, value) (DMA_WR_CSR(base, index, (DMA_RD_CSR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) |  (value)))
+#define DMA_CLR_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) & ~(value)))
+#define DMA_TOG_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CSR bitfields
+ */
+
+/*!
+ * @name Register DMA_CSR, field START[0] (RW)
+ *
+ * If this flag is set, the channel is requesting service. The eDMA hardware
+ * automatically clears this flag after the channel begins execution.
+ *
+ * Values:
+ * - 0b0 - The channel is not explicitly started
+ * - 0b1 - The channel is explicitly started via a software initiated service
+ *     request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_START field. */
+#define DMA_RD_CSR_START(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_START_MASK) >> DMA_CSR_START_SHIFT)
+#define DMA_BRD_CSR_START(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_START_SHIFT))
+
+/*! @brief Set the START field to a new value. */
+#define DMA_WR_CSR_START(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_START_MASK, DMA_CSR_START(value)))
+#define DMA_BWR_CSR_START(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_START_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field INTMAJOR[1] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT when the current major iteration count reaches
+ * zero.
+ *
+ * Values:
+ * - 0b0 - The end-of-major loop interrupt is disabled
+ * - 0b1 - The end-of-major loop interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_INTMAJOR field. */
+#define DMA_RD_CSR_INTMAJOR(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_INTMAJOR_MASK) >> DMA_CSR_INTMAJOR_SHIFT)
+#define DMA_BRD_CSR_INTMAJOR(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTMAJOR_SHIFT))
+
+/*! @brief Set the INTMAJOR field to a new value. */
+#define DMA_WR_CSR_INTMAJOR(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_INTMAJOR_MASK, DMA_CSR_INTMAJOR(value)))
+#define DMA_BWR_CSR_INTMAJOR(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTMAJOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field INTHALF[2] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT register when the current major iteration count
+ * reaches the halfway point. Specifically, the comparison performed by the eDMA
+ * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
+ * provided to support double-buffered (aka ping-pong) schemes or other types of data
+ * movement where the processor needs an early indication of the transfer's
+ * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
+ *
+ * Values:
+ * - 0b0 - The half-point interrupt is disabled
+ * - 0b1 - The half-point interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_INTHALF field. */
+#define DMA_RD_CSR_INTHALF(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_INTHALF_MASK) >> DMA_CSR_INTHALF_SHIFT)
+#define DMA_BRD_CSR_INTHALF(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTHALF_SHIFT))
+
+/*! @brief Set the INTHALF field to a new value. */
+#define DMA_WR_CSR_INTHALF(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_INTHALF_MASK, DMA_CSR_INTHALF(value)))
+#define DMA_BWR_CSR_INTHALF(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTHALF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field DREQ[3] (RW)
+ *
+ * If this flag is set, the eDMA hardware automatically clears the corresponding
+ * ERQ bit when the current major iteration count reaches zero.
+ *
+ * Values:
+ * - 0b0 - The channel's ERQ bit is not affected
+ * - 0b1 - The channel's ERQ bit is cleared when the major loop is complete
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_DREQ field. */
+#define DMA_RD_CSR_DREQ(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_DREQ_MASK) >> DMA_CSR_DREQ_SHIFT)
+#define DMA_BRD_CSR_DREQ(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DREQ_SHIFT))
+
+/*! @brief Set the DREQ field to a new value. */
+#define DMA_WR_CSR_DREQ(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_DREQ_MASK, DMA_CSR_DREQ(value)))
+#define DMA_BWR_CSR_DREQ(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field ESG[4] (RW)
+ *
+ * As the channel completes the major loop, this flag enables scatter/gather
+ * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
+ * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
+ * loaded as the transfer control descriptor into the local memory. To support the
+ * dynamic scatter/gather coherency model, this field is forced to zero when
+ * written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0b0 - The current channel's TCD is normal format.
+ * - 0b1 - The current channel's TCD specifies a scatter gather format. The
+ *     DLASTSGA field provides a memory pointer to the next TCD to be loaded into
+ *     this channel after the major loop completes its execution.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_ESG field. */
+#define DMA_RD_CSR_ESG(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_ESG_MASK) >> DMA_CSR_ESG_SHIFT)
+#define DMA_BRD_CSR_ESG(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ESG_SHIFT))
+
+/*! @brief Set the ESG field to a new value. */
+#define DMA_WR_CSR_ESG(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_ESG_MASK, DMA_CSR_ESG(value)))
+#define DMA_BWR_CSR_ESG(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ESG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field MAJORELINK[5] (RW)
+ *
+ * As the channel completes the major loop, this flag enables the linking to
+ * another channel, defined by MAJORLINKCH. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. To support the dynamic linking coherency model,
+ * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_MAJORELINK field. */
+#define DMA_RD_CSR_MAJORELINK(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_MAJORELINK_MASK) >> DMA_CSR_MAJORELINK_SHIFT)
+#define DMA_BRD_CSR_MAJORELINK(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_MAJORELINK_SHIFT))
+
+/*! @brief Set the MAJORELINK field to a new value. */
+#define DMA_WR_CSR_MAJORELINK(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_MAJORELINK_MASK, DMA_CSR_MAJORELINK(value)))
+#define DMA_BWR_CSR_MAJORELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_MAJORELINK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field ACTIVE[6] (RW)
+ *
+ * This flag signals the channel is currently in execution. It is set when
+ * channel service begins, and the eDMA clears it as the minor loop completes or if
+ * any error condition is detected. This bit resets to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_ACTIVE field. */
+#define DMA_RD_CSR_ACTIVE(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_ACTIVE_MASK) >> DMA_CSR_ACTIVE_SHIFT)
+#define DMA_BRD_CSR_ACTIVE(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ACTIVE_SHIFT))
+
+/*! @brief Set the ACTIVE field to a new value. */
+#define DMA_WR_CSR_ACTIVE(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_ACTIVE_MASK, DMA_CSR_ACTIVE(value)))
+#define DMA_BWR_CSR_ACTIVE(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ACTIVE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field DONE[7] (RW)
+ *
+ * This flag indicates the eDMA has completed the major loop. The eDMA engine
+ * sets it as the CITER count reaches zero; The software clears it, or the hardware
+ * when the channel is activated. This bit must be cleared to write the
+ * MAJORELINK or ESG bits.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_DONE field. */
+#define DMA_RD_CSR_DONE(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT)
+#define DMA_BRD_CSR_DONE(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DONE_SHIFT))
+
+/*! @brief Set the DONE field to a new value. */
+#define DMA_WR_CSR_DONE(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_DONE_MASK, DMA_CSR_DONE(value)))
+#define DMA_BWR_CSR_DONE(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DONE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field MAJORLINKCH[11:8] (RW)
+ *
+ * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
+ * performed after the major loop counter is exhausted. else After the major loop
+ * counter is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_MAJORLINKCH field. */
+#define DMA_RD_CSR_MAJORLINKCH(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_MAJORLINKCH_MASK) >> DMA_CSR_MAJORLINKCH_SHIFT)
+#define DMA_BRD_CSR_MAJORLINKCH(base, index) (DMA_RD_CSR_MAJORLINKCH(base, index))
+
+/*! @brief Set the MAJORLINKCH field to a new value. */
+#define DMA_WR_CSR_MAJORLINKCH(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_MAJORLINKCH_MASK, DMA_CSR_MAJORLINKCH(value)))
+#define DMA_BWR_CSR_MAJORLINKCH(base, index, value) (DMA_WR_CSR_MAJORLINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field BWC[15:14] (RW)
+ *
+ * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
+ * the eDMA processes the minor loop, it continuously generates read/write
+ * sequences until the minor count is exhausted. This field forces the eDMA to stall
+ * after the completion of each read/write access to control the bus request
+ * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
+ * this field is ignored between the first and second transfers and after the
+ * last write of each minor loop. This behavior is a side effect of reducing
+ * start-up latency.
+ *
+ * Values:
+ * - 0b00 - No eDMA engine stalls
+ * - 0b01 - Reserved
+ * - 0b10 - eDMA engine stalls for 4 cycles after each r/w
+ * - 0b11 - eDMA engine stalls for 8 cycles after each r/w
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_BWC field. */
+#define DMA_RD_CSR_BWC(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_BWC_MASK) >> DMA_CSR_BWC_SHIFT)
+#define DMA_BRD_CSR_BWC(base, index) (DMA_RD_CSR_BWC(base, index))
+
+/*! @brief Set the BWC field to a new value. */
+#define DMA_WR_CSR_BWC(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_BWC_MASK, DMA_CSR_BWC(value)))
+#define DMA_BWR_CSR_BWC(base, index, value) (DMA_WR_CSR_BWC(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
+ * follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_BITER_ELINKYES register
+ */
+/*@{*/
+#define DMA_RD_BITER_ELINKYES(base, index) (DMA_BITER_ELINKYES_REG(base, index))
+#define DMA_WR_BITER_ELINKYES(base, index, value) (DMA_BITER_ELINKYES_REG(base, index) = (value))
+#define DMA_RMW_BITER_ELINKYES(base, index, mask, value) (DMA_WR_BITER_ELINKYES(base, index, (DMA_RD_BITER_ELINKYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) |  (value)))
+#define DMA_CLR_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) & ~(value)))
+#define DMA_TOG_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_BITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field BITER[8:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_BITER field. */
+#define DMA_RD_BITER_ELINKYES_BITER(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_BITER_MASK) >> DMA_BITER_ELINKYES_BITER_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_BITER(base, index) (DMA_RD_BITER_ELINKYES_BITER(base, index))
+
+/*! @brief Set the BITER field to a new value. */
+#define DMA_WR_BITER_ELINKYES_BITER(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_BITER_MASK, DMA_BITER_ELINKYES_BITER(value)))
+#define DMA_BWR_BITER_ELINKYES_BITER(base, index, value) (DMA_WR_BITER_ELINKYES_BITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START]
+ * bit. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the major
+ * iteration count is exhausted, the contents of this field is reloaded into the
+ * CITER field.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_LINKCH field. */
+#define DMA_RD_BITER_ELINKYES_LINKCH(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_LINKCH_MASK) >> DMA_BITER_ELINKYES_LINKCH_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_LINKCH(base, index) (DMA_RD_BITER_ELINKYES_LINKCH(base, index))
+
+/*! @brief Set the LINKCH field to a new value. */
+#define DMA_WR_BITER_ELINKYES_LINKCH(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_LINKCH_MASK, DMA_BITER_ELINKYES_LINKCH(value)))
+#define DMA_BWR_BITER_ELINKYES_LINKCH(base, index, value) (DMA_WR_BITER_ELINKYES_LINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking disables, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded into
+ * the CITER field.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_ELINK field. */
+#define DMA_RD_BITER_ELINKYES_ELINK(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_ELINK_MASK) >> DMA_BITER_ELINKYES_ELINK_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_ELINK(base, index) (BITBAND_ACCESS16(&DMA_BITER_ELINKYES_REG(base, index), DMA_BITER_ELINKYES_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_BITER_ELINKYES_ELINK(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_ELINK_MASK, DMA_BITER_ELINKYES_ELINK(value)))
+#define DMA_BWR_BITER_ELINKYES_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_BITER_ELINKYES_REG(base, index), DMA_BITER_ELINKYES_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
+ * as follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_BITER_ELINKNO register
+ */
+/*@{*/
+#define DMA_RD_BITER_ELINKNO(base, index) (DMA_BITER_ELINKNO_REG(base, index))
+#define DMA_WR_BITER_ELINKNO(base, index, value) (DMA_BITER_ELINKNO_REG(base, index) = (value))
+#define DMA_RMW_BITER_ELINKNO(base, index, mask, value) (DMA_WR_BITER_ELINKNO(base, index, (DMA_RD_BITER_ELINKNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) |  (value)))
+#define DMA_CLR_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) & ~(value)))
+#define DMA_TOG_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_BITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_BITER_ELINKNO, field BITER[14:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKNO_BITER field. */
+#define DMA_RD_BITER_ELINKNO_BITER(base, index) ((DMA_BITER_ELINKNO_REG(base, index) & DMA_BITER_ELINKNO_BITER_MASK) >> DMA_BITER_ELINKNO_BITER_SHIFT)
+#define DMA_BRD_BITER_ELINKNO_BITER(base, index) (DMA_RD_BITER_ELINKNO_BITER(base, index))
+
+/*! @brief Set the BITER field to a new value. */
+#define DMA_WR_BITER_ELINKNO_BITER(base, index, value) (DMA_RMW_BITER_ELINKNO(base, index, DMA_BITER_ELINKNO_BITER_MASK, DMA_BITER_ELINKNO_BITER(value)))
+#define DMA_BWR_BITER_ELINKNO_BITER(base, index, value) (DMA_WR_BITER_ELINKNO_BITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded
+ * into the CITER field.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKNO_ELINK field. */
+#define DMA_RD_BITER_ELINKNO_ELINK(base, index) ((DMA_BITER_ELINKNO_REG(base, index) & DMA_BITER_ELINKNO_ELINK_MASK) >> DMA_BITER_ELINKNO_ELINK_SHIFT)
+#define DMA_BRD_BITER_ELINKNO_ELINK(base, index) (BITBAND_ACCESS16(&DMA_BITER_ELINKNO_REG(base, index), DMA_BITER_ELINKNO_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_BITER_ELINKNO_ELINK(base, index, value) (DMA_RMW_BITER_ELINKNO(base, index, DMA_BITER_ELINKNO_ELINK_MASK, DMA_BITER_ELINKNO_ELINK(value)))
+#define DMA_BWR_BITER_ELINKNO_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_BITER_ELINKNO_REG(base, index), DMA_BITER_ELINKNO_ELINK_SHIFT) = (value))
+/*@}*/
+
+/* Register macros for indexed access to DMA channel priority registers */
+/*
+ * Constants and macros for entire DMA_DCHPRIn register
+ */
+#define DMA_DCHPRIn_INDEX(channel)          (((channel) & ~0x03U) | (3 - ((channel) & 0x03U)))
+#define DMA_DCHPRIn_REG(base, index)        (((volatile uint8_t *)&DMA_DCHPRI3_REG(base))[DMA_DCHPRIn_INDEX(index)])
+#define DMA_RD_DCHPRIn(base, index)         (DMA_DCHPRIn_REG((base), (index)))
+#define DMA_WR_DCHPRIn(base, index, value)  (DMA_DCHPRIn_REG((base), (index)) = (value))
+#define DMA_SET_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) |  (value)))
+#define DMA_CLR_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) & ~(value)))
+#define DMA_TOG_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) ^  (value)))
+
+/*
+ * Register DMA_DCHPRIn, bit field CHPRI
+ */
+/* Read current value of the CHPRI bit field. */
+#define DMA_RD_DCHPRIn_CHPRI(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_CHPRI_MASK) >> DMA_DCHPRI0_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRIn_CHPRI(base, index) (DMA_RD_DCHPRIn_CHPRI((base), (index)))
+
+/* Set the CHPRI bit field to a new value. */
+#define DMA_WR_DCHPRIn_CHPRI(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_CHPRI_MASK) | DMA_DCHPRI0_CHPRI(value)))
+#define DMA_BWR_DCHPRIn_CHPRI(base, index, value) (DMA_WR_DCHPRIn_CHPRI((base), (index), (value)))
+
+/*
+ * Register DMA_DCHPRIn, bit field DPA
+ */
+/* Read current value of the DPA bit field. */
+#define DMA_RD_DCHPRIn_DPA(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_DPA_MASK) >> DMA_DCHPRI0_DPA_SHIFT)
+#define DMA_BRD_DCHPRIn_DPA(base, index) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_DPA_SHIFT))
+
+/* Set the DPA bit field to a new value. */
+#define DMA_WR_DCHPRIn_DPA(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_DPA_MASK) | DMA_DCHPRI0_DPA(value)))
+#define DMA_BWR_DCHPRIn_DPA(base, index, value) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_DPA_SHIFT) = (value))
+
+/*
+ * Register DMA_DCHPRIn, bit field ECP
+ */
+/* Read current value of the ECP bit field. */
+#define DMA_RD_DCHPRIn_ECP(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_ECP_MASK) >> DMA_DCHPRI0_ECP_SHIFT)
+#define DMA_BRD_DCHPRIn_ECP(base, index) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_ECP_SHIFT))
+
+/* Set the ECP bit field to a new value. */
+#define DMA_WR_DCHPRIn_ECP(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_ECP_MASK) | DMA_DCHPRI0_ECP(value)))
+#define DMA_BWR_DCHPRIn_ECP(base, index, value) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_ECP_SHIFT) = (value))
+
+/*
+ * MK64F12 DMAMUX
+ *
+ * DMA channel multiplexor
+ *
+ * Registers defined in this header file:
+ * - DMAMUX_CHCFG - Channel Configuration register
+ */
+
+#define DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
+#define DMAMUX_IDX (0U) /*!< Instance number for DMAMUX. */
+
+/*******************************************************************************
+ * DMAMUX_CHCFG - Channel Configuration register
+ ******************************************************************************/
+
+/*!
+ * @brief DMAMUX_CHCFG - Channel Configuration register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Each of the DMA channels can be independently enabled/disabled and associated
+ * with one of the DMA slots (peripheral slots or always-on slots) in the
+ * system. Setting multiple CHCFG registers with the same source value will result in
+ * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
+ * Before changing the trigger or source settings, a DMA channel must be disabled
+ * via CHCFGn[ENBL].
+ */
+/*!
+ * @name Constants and macros for entire DMAMUX_CHCFG register
+ */
+/*@{*/
+#define DMAMUX_RD_CHCFG(base, index) (DMAMUX_CHCFG_REG(base, index))
+#define DMAMUX_WR_CHCFG(base, index, value) (DMAMUX_CHCFG_REG(base, index) = (value))
+#define DMAMUX_RMW_CHCFG(base, index, mask, value) (DMAMUX_WR_CHCFG(base, index, (DMAMUX_RD_CHCFG(base, index) & ~(mask)) | (value)))
+#define DMAMUX_SET_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) |  (value)))
+#define DMAMUX_CLR_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) & ~(value)))
+#define DMAMUX_TOG_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMAMUX_CHCFG bitfields
+ */
+
+/*!
+ * @name Register DMAMUX_CHCFG, field SOURCE[5:0] (RW)
+ *
+ * Specifies which DMA source, if any, is routed to a particular DMA channel.
+ * See your device's chip configuration details for information about the
+ * peripherals and their slot numbers.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_SOURCE field. */
+#define DMAMUX_RD_CHCFG_SOURCE(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT)
+#define DMAMUX_BRD_CHCFG_SOURCE(base, index) (DMAMUX_RD_CHCFG_SOURCE(base, index))
+
+/*! @brief Set the SOURCE field to a new value. */
+#define DMAMUX_WR_CHCFG_SOURCE(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_SOURCE_MASK, DMAMUX_CHCFG_SOURCE(value)))
+#define DMAMUX_BWR_CHCFG_SOURCE(base, index, value) (DMAMUX_WR_CHCFG_SOURCE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field TRIG[6] (RW)
+ *
+ * Enables the periodic trigger capability for the triggered DMA channel.
+ *
+ * Values:
+ * - 0b0 - Triggering is disabled. If triggering is disabled and ENBL is set,
+ *     the DMA Channel will simply route the specified source to the DMA channel.
+ *     (Normal mode)
+ * - 0b1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
+ *     DMAMUX is in Periodic Trigger mode.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_TRIG field. */
+#define DMAMUX_RD_CHCFG_TRIG(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_TRIG_MASK) >> DMAMUX_CHCFG_TRIG_SHIFT)
+#define DMAMUX_BRD_CHCFG_TRIG(base, index) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT))
+
+/*! @brief Set the TRIG field to a new value. */
+#define DMAMUX_WR_CHCFG_TRIG(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_TRIG_MASK, DMAMUX_CHCFG_TRIG(value)))
+#define DMAMUX_BWR_CHCFG_TRIG(base, index, value) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field ENBL[7] (RW)
+ *
+ * Enables the DMA channel.
+ *
+ * Values:
+ * - 0b0 - DMA channel is disabled. This mode is primarily used during
+ *     configuration of the DMAMux. The DMA has separate channel enables/disables, which
+ *     should be used to disable or reconfigure a DMA channel.
+ * - 0b1 - DMA channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_ENBL field. */
+#define DMAMUX_RD_CHCFG_ENBL(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT)
+#define DMAMUX_BRD_CHCFG_ENBL(base, index) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT))
+
+/*! @brief Set the ENBL field to a new value. */
+#define DMAMUX_WR_CHCFG_ENBL(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_ENBL_MASK, DMAMUX_CHCFG_ENBL(value)))
+#define DMAMUX_BWR_CHCFG_ENBL(base, index, value) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 ENET
+ *
+ * Ethernet MAC-NET Core
+ *
+ * Registers defined in this header file:
+ * - ENET_EIR - Interrupt Event Register
+ * - ENET_EIMR - Interrupt Mask Register
+ * - ENET_RDAR - Receive Descriptor Active Register
+ * - ENET_TDAR - Transmit Descriptor Active Register
+ * - ENET_ECR - Ethernet Control Register
+ * - ENET_MMFR - MII Management Frame Register
+ * - ENET_MSCR - MII Speed Control Register
+ * - ENET_MIBC - MIB Control Register
+ * - ENET_RCR - Receive Control Register
+ * - ENET_TCR - Transmit Control Register
+ * - ENET_PALR - Physical Address Lower Register
+ * - ENET_PAUR - Physical Address Upper Register
+ * - ENET_OPD - Opcode/Pause Duration Register
+ * - ENET_IAUR - Descriptor Individual Upper Address Register
+ * - ENET_IALR - Descriptor Individual Lower Address Register
+ * - ENET_GAUR - Descriptor Group Upper Address Register
+ * - ENET_GALR - Descriptor Group Lower Address Register
+ * - ENET_TFWR - Transmit FIFO Watermark Register
+ * - ENET_RDSR - Receive Descriptor Ring Start Register
+ * - ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ * - ENET_MRBR - Maximum Receive Buffer Size Register
+ * - ENET_RSFL - Receive FIFO Section Full Threshold
+ * - ENET_RSEM - Receive FIFO Section Empty Threshold
+ * - ENET_RAEM - Receive FIFO Almost Empty Threshold
+ * - ENET_RAFL - Receive FIFO Almost Full Threshold
+ * - ENET_TSEM - Transmit FIFO Section Empty Threshold
+ * - ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ * - ENET_TAFL - Transmit FIFO Almost Full Threshold
+ * - ENET_TIPG - Transmit Inter-Packet Gap
+ * - ENET_FTRL - Frame Truncation Length
+ * - ENET_TACC - Transmit Accelerator Function Configuration
+ * - ENET_RACC - Receive Accelerator Function Configuration
+ * - ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ * - ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ * - ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ * - ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ * - ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ * - ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ * - ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ * - ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ * - ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ * - ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ * - ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ * - ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ * - ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ * - ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ * - ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ * - ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ * - ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ * - ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ * - ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ * - ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ * - ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ * - ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ * - ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ * - ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ * - ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ * - ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ * - ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ * - ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ * - ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ * - ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ * - ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ * - ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ * - ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ * - ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ * - ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ * - ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ * - ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ * - ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ * - ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ * - ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ * - ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ * - ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ * - ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ * - ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ * - ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ * - ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ * - ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ * - ENET_ATCR - Adjustable Timer Control Register
+ * - ENET_ATVR - Timer Value Register
+ * - ENET_ATOFF - Timer Offset Register
+ * - ENET_ATPER - Timer Period Register
+ * - ENET_ATCOR - Timer Correction Register
+ * - ENET_ATINC - Time-Stamping Clock Period Register
+ * - ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ * - ENET_TGSR - Timer Global Status Register
+ * - ENET_TCSR - Timer Control Status Register
+ * - ENET_TCCR - Timer Compare Capture Register
+ */
+
+#define ENET_INSTANCE_COUNT (1U) /*!< Number of instances of the ENET module. */
+#define ENET_IDX (0U) /*!< Instance number for ENET. */
+
+/*******************************************************************************
+ * ENET_EIR - Interrupt Event Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_EIR - Interrupt Event Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an event occurs that sets a bit in EIR, an interrupt occurs if the
+ * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
+ * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
+ * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
+ * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
+ * Legacy mode does not require these flags to be enabled.
+ */
+/*!
+ * @name Constants and macros for entire ENET_EIR register
+ */
+/*@{*/
+#define ENET_RD_EIR(base)        (ENET_EIR_REG(base))
+#define ENET_WR_EIR(base, value) (ENET_EIR_REG(base) = (value))
+#define ENET_RMW_EIR(base, mask, value) (ENET_WR_EIR(base, (ENET_RD_EIR(base) & ~(mask)) | (value)))
+#define ENET_SET_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) |  (value)))
+#define ENET_CLR_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) & ~(value)))
+#define ENET_TOG_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_EIR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
+ *
+ * The adjustable timer reached the period event. A period event interrupt can
+ * be generated if ATCR[PEREN] is set and the timer wraps according to the
+ * periodic setting in the ATPER register. Set the timer period value before setting
+ * ATCR[PEREN].
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TS_TIMER field. */
+#define ENET_RD_EIR_TS_TIMER(base) ((ENET_EIR_REG(base) & ENET_EIR_TS_TIMER_MASK) >> ENET_EIR_TS_TIMER_SHIFT)
+#define ENET_BRD_EIR_TS_TIMER(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_TIMER_SHIFT))
+
+/*! @brief Set the TS_TIMER field to a new value. */
+#define ENET_WR_EIR_TS_TIMER(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TS_TIMER(value)))
+#define ENET_BWR_EIR_TS_TIMER(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_TIMER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
+ *
+ * Indicates that the timestamp of the last transmitted timing frame is
+ * available in the ATSTMP register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TS_AVAIL field. */
+#define ENET_RD_EIR_TS_AVAIL(base) ((ENET_EIR_REG(base) & ENET_EIR_TS_AVAIL_MASK) >> ENET_EIR_TS_AVAIL_SHIFT)
+#define ENET_BRD_EIR_TS_AVAIL(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_AVAIL_SHIFT))
+
+/*! @brief Set the TS_AVAIL field to a new value. */
+#define ENET_WR_EIR_TS_AVAIL(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TS_AVAIL_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TS_AVAIL(value)))
+#define ENET_BWR_EIR_TS_AVAIL(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_AVAIL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field WAKEUP[17] (W1C)
+ *
+ * Read-only status bit to indicate that a magic packet has been detected. Will
+ * act only if ECR[MAGICEN] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_WAKEUP field. */
+#define ENET_RD_EIR_WAKEUP(base) ((ENET_EIR_REG(base) & ENET_EIR_WAKEUP_MASK) >> ENET_EIR_WAKEUP_SHIFT)
+#define ENET_BRD_EIR_WAKEUP(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_WAKEUP_SHIFT))
+
+/*! @brief Set the WAKEUP field to a new value. */
+#define ENET_WR_EIR_WAKEUP(base, value) (ENET_RMW_EIR(base, (ENET_EIR_WAKEUP_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_WAKEUP(value)))
+#define ENET_BWR_EIR_WAKEUP(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_WAKEUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field PLR[18] (W1C)
+ *
+ * Indicates a frame was received with a payload length error. See Frame
+ * Length/Type Verification: Payload Length Check for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_PLR field. */
+#define ENET_RD_EIR_PLR(base) ((ENET_EIR_REG(base) & ENET_EIR_PLR_MASK) >> ENET_EIR_PLR_SHIFT)
+#define ENET_BRD_EIR_PLR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_PLR_SHIFT))
+
+/*! @brief Set the PLR field to a new value. */
+#define ENET_WR_EIR_PLR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_PLR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_PLR(value)))
+#define ENET_BWR_EIR_PLR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_PLR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field UN[19] (W1C)
+ *
+ * Indicates the transmit FIFO became empty before the complete frame was
+ * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
+ * frame is discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_UN field. */
+#define ENET_RD_EIR_UN(base) ((ENET_EIR_REG(base) & ENET_EIR_UN_MASK) >> ENET_EIR_UN_SHIFT)
+#define ENET_BRD_EIR_UN(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_UN_SHIFT))
+
+/*! @brief Set the UN field to a new value. */
+#define ENET_WR_EIR_UN(base, value) (ENET_RMW_EIR(base, (ENET_EIR_UN_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_UN(value)))
+#define ENET_BWR_EIR_UN(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_UN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RL[20] (W1C)
+ *
+ * Indicates a collision occurred on each of 16 successive attempts to transmit
+ * the frame. The frame is discarded without being transmitted and transmission
+ * of the next frame commences. This error can only occur in half-duplex mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RL field. */
+#define ENET_RD_EIR_RL(base) ((ENET_EIR_REG(base) & ENET_EIR_RL_MASK) >> ENET_EIR_RL_SHIFT)
+#define ENET_BRD_EIR_RL(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RL_SHIFT))
+
+/*! @brief Set the RL field to a new value. */
+#define ENET_WR_EIR_RL(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RL_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RL(value)))
+#define ENET_BWR_EIR_RL(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field LC[21] (W1C)
+ *
+ * Indicates a collision occurred beyond the collision window (slot time) in
+ * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
+ * frame is discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_LC field. */
+#define ENET_RD_EIR_LC(base) ((ENET_EIR_REG(base) & ENET_EIR_LC_MASK) >> ENET_EIR_LC_SHIFT)
+#define ENET_BRD_EIR_LC(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_LC_SHIFT))
+
+/*! @brief Set the LC field to a new value. */
+#define ENET_WR_EIR_LC(base, value) (ENET_RMW_EIR(base, (ENET_EIR_LC_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_LC(value)))
+#define ENET_BWR_EIR_LC(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_LC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field EBERR[22] (W1C)
+ *
+ * Indicates a system bus error occurred when a uDMA transaction is underway.
+ * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
+ * MAC. When this occurs, software must ensure proper actions, possibly resetting
+ * the system, to resume normal operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_EBERR field. */
+#define ENET_RD_EIR_EBERR(base) ((ENET_EIR_REG(base) & ENET_EIR_EBERR_MASK) >> ENET_EIR_EBERR_SHIFT)
+#define ENET_BRD_EIR_EBERR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_EBERR_SHIFT))
+
+/*! @brief Set the EBERR field to a new value. */
+#define ENET_WR_EIR_EBERR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_EBERR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_EBERR(value)))
+#define ENET_BWR_EIR_EBERR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_EBERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field MII[23] (W1C)
+ *
+ * Indicates that the MII has completed the data transfer requested.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_MII field. */
+#define ENET_RD_EIR_MII(base) ((ENET_EIR_REG(base) & ENET_EIR_MII_MASK) >> ENET_EIR_MII_SHIFT)
+#define ENET_BRD_EIR_MII(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_MII_SHIFT))
+
+/*! @brief Set the MII field to a new value. */
+#define ENET_WR_EIR_MII(base, value) (ENET_RMW_EIR(base, (ENET_EIR_MII_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_MII(value)))
+#define ENET_BWR_EIR_MII(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_MII_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RXB[24] (W1C)
+ *
+ * Indicates a receive buffer descriptor is not the last in the frame has been
+ * updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RXB field. */
+#define ENET_RD_EIR_RXB(base) ((ENET_EIR_REG(base) & ENET_EIR_RXB_MASK) >> ENET_EIR_RXB_SHIFT)
+#define ENET_BRD_EIR_RXB(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXB_SHIFT))
+
+/*! @brief Set the RXB field to a new value. */
+#define ENET_WR_EIR_RXB(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RXB_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RXB(value)))
+#define ENET_BWR_EIR_RXB(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RXF[25] (W1C)
+ *
+ * Indicates a frame has been received and the last corresponding buffer
+ * descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RXF field. */
+#define ENET_RD_EIR_RXF(base) ((ENET_EIR_REG(base) & ENET_EIR_RXF_MASK) >> ENET_EIR_RXF_SHIFT)
+#define ENET_BRD_EIR_RXF(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXF_SHIFT))
+
+/*! @brief Set the RXF field to a new value. */
+#define ENET_WR_EIR_RXF(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RXF_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RXF(value)))
+#define ENET_BWR_EIR_RXF(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TXB[26] (W1C)
+ *
+ * Indicates a transmit buffer descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TXB field. */
+#define ENET_RD_EIR_TXB(base) ((ENET_EIR_REG(base) & ENET_EIR_TXB_MASK) >> ENET_EIR_TXB_SHIFT)
+#define ENET_BRD_EIR_TXB(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXB_SHIFT))
+
+/*! @brief Set the TXB field to a new value. */
+#define ENET_WR_EIR_TXB(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TXB_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TXB(value)))
+#define ENET_BWR_EIR_TXB(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TXF[27] (W1C)
+ *
+ * Indicates a frame has been transmitted and the last corresponding buffer
+ * descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TXF field. */
+#define ENET_RD_EIR_TXF(base) ((ENET_EIR_REG(base) & ENET_EIR_TXF_MASK) >> ENET_EIR_TXF_SHIFT)
+#define ENET_BRD_EIR_TXF(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXF_SHIFT))
+
+/*! @brief Set the TXF field to a new value. */
+#define ENET_WR_EIR_TXF(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TXF_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TXF(value)))
+#define ENET_BWR_EIR_TXF(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field GRA[28] (W1C)
+ *
+ * This interrupt is asserted after the transmitter is put into a pause state
+ * after completion of the frame currently being transmitted. See Graceful Transmit
+ * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
+ * asserted only when the TX transitions into the stopped state. If this bit is
+ * cleared by writing 1 and the TX is still stopped, the bit is not set again.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_GRA field. */
+#define ENET_RD_EIR_GRA(base) ((ENET_EIR_REG(base) & ENET_EIR_GRA_MASK) >> ENET_EIR_GRA_SHIFT)
+#define ENET_BRD_EIR_GRA(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_GRA_SHIFT))
+
+/*! @brief Set the GRA field to a new value. */
+#define ENET_WR_EIR_GRA(base, value) (ENET_RMW_EIR(base, (ENET_EIR_GRA_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_GRA(value)))
+#define ENET_BWR_EIR_GRA(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_GRA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field BABT[29] (W1C)
+ *
+ * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
+ * this condition is caused when a frame that is too long is placed into the
+ * transmit data buffer(s). Truncation does not occur.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_BABT field. */
+#define ENET_RD_EIR_BABT(base) ((ENET_EIR_REG(base) & ENET_EIR_BABT_MASK) >> ENET_EIR_BABT_SHIFT)
+#define ENET_BRD_EIR_BABT(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABT_SHIFT))
+
+/*! @brief Set the BABT field to a new value. */
+#define ENET_WR_EIR_BABT(base, value) (ENET_RMW_EIR(base, (ENET_EIR_BABT_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABR_MASK), ENET_EIR_BABT(value)))
+#define ENET_BWR_EIR_BABT(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field BABR[30] (W1C)
+ *
+ * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_BABR field. */
+#define ENET_RD_EIR_BABR(base) ((ENET_EIR_REG(base) & ENET_EIR_BABR_MASK) >> ENET_EIR_BABR_SHIFT)
+#define ENET_BRD_EIR_BABR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABR_SHIFT))
+
+/*! @brief Set the BABR field to a new value. */
+#define ENET_WR_EIR_BABR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_BABR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK), ENET_EIR_BABR(value)))
+#define ENET_BWR_EIR_BABR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_EIMR - Interrupt Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_EIMR - Interrupt Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * EIMR controls which interrupt events are allowed to generate actual
+ * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
+ * and EIMR registers are set, an interrupt is generated. The interrupt signal
+ * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
+ * 0 is written to the EIMR field.
+ */
+/*!
+ * @name Constants and macros for entire ENET_EIMR register
+ */
+/*@{*/
+#define ENET_RD_EIMR(base)       (ENET_EIMR_REG(base))
+#define ENET_WR_EIMR(base, value) (ENET_EIMR_REG(base) = (value))
+#define ENET_RMW_EIMR(base, mask, value) (ENET_WR_EIMR(base, (ENET_RD_EIMR(base) & ~(mask)) | (value)))
+#define ENET_SET_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) |  (value)))
+#define ENET_CLR_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) & ~(value)))
+#define ENET_TOG_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_EIMR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_TIMER field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TS_TIMER field. */
+#define ENET_RD_EIMR_TS_TIMER(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TS_TIMER_MASK) >> ENET_EIMR_TS_TIMER_SHIFT)
+#define ENET_BRD_EIMR_TS_TIMER(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_TIMER_SHIFT))
+
+/*! @brief Set the TS_TIMER field to a new value. */
+#define ENET_WR_EIMR_TS_TIMER(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TS_TIMER_MASK, ENET_EIMR_TS_TIMER(value)))
+#define ENET_BWR_EIMR_TS_TIMER(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_TIMER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TS_AVAIL field. */
+#define ENET_RD_EIMR_TS_AVAIL(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TS_AVAIL_MASK) >> ENET_EIMR_TS_AVAIL_SHIFT)
+#define ENET_BRD_EIMR_TS_AVAIL(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_AVAIL_SHIFT))
+
+/*! @brief Set the TS_AVAIL field to a new value. */
+#define ENET_WR_EIMR_TS_AVAIL(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TS_AVAIL_MASK, ENET_EIMR_TS_AVAIL(value)))
+#define ENET_BWR_EIMR_TS_AVAIL(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_AVAIL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field WAKEUP[17] (RW)
+ *
+ * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR WAKEUP field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_WAKEUP field. */
+#define ENET_RD_EIMR_WAKEUP(base) ((ENET_EIMR_REG(base) & ENET_EIMR_WAKEUP_MASK) >> ENET_EIMR_WAKEUP_SHIFT)
+#define ENET_BRD_EIMR_WAKEUP(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_WAKEUP_SHIFT))
+
+/*! @brief Set the WAKEUP field to a new value. */
+#define ENET_WR_EIMR_WAKEUP(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_WAKEUP_MASK, ENET_EIMR_WAKEUP(value)))
+#define ENET_BWR_EIMR_WAKEUP(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_WAKEUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field PLR[18] (RW)
+ *
+ * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR PLR field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_PLR field. */
+#define ENET_RD_EIMR_PLR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_PLR_MASK) >> ENET_EIMR_PLR_SHIFT)
+#define ENET_BRD_EIMR_PLR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_PLR_SHIFT))
+
+/*! @brief Set the PLR field to a new value. */
+#define ENET_WR_EIMR_PLR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_PLR_MASK, ENET_EIMR_PLR(value)))
+#define ENET_BWR_EIMR_PLR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_PLR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field UN[19] (RW)
+ *
+ * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR UN field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_UN field. */
+#define ENET_RD_EIMR_UN(base) ((ENET_EIMR_REG(base) & ENET_EIMR_UN_MASK) >> ENET_EIMR_UN_SHIFT)
+#define ENET_BRD_EIMR_UN(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_UN_SHIFT))
+
+/*! @brief Set the UN field to a new value. */
+#define ENET_WR_EIMR_UN(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_UN_MASK, ENET_EIMR_UN(value)))
+#define ENET_BWR_EIMR_UN(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_UN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RL[20] (RW)
+ *
+ * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR RL field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RL field. */
+#define ENET_RD_EIMR_RL(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RL_MASK) >> ENET_EIMR_RL_SHIFT)
+#define ENET_BRD_EIMR_RL(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RL_SHIFT))
+
+/*! @brief Set the RL field to a new value. */
+#define ENET_WR_EIMR_RL(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RL_MASK, ENET_EIMR_RL(value)))
+#define ENET_BWR_EIMR_RL(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field LC[21] (RW)
+ *
+ * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR LC field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_LC field. */
+#define ENET_RD_EIMR_LC(base) ((ENET_EIMR_REG(base) & ENET_EIMR_LC_MASK) >> ENET_EIMR_LC_SHIFT)
+#define ENET_BRD_EIMR_LC(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_LC_SHIFT))
+
+/*! @brief Set the LC field to a new value. */
+#define ENET_WR_EIMR_LC(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_LC_MASK, ENET_EIMR_LC(value)))
+#define ENET_BWR_EIMR_LC(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_LC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field EBERR[22] (RW)
+ *
+ * Corresponds to interrupt source EIR[EBERR] and determines whether an
+ * interrupt condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR EBERR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_EBERR field. */
+#define ENET_RD_EIMR_EBERR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_EBERR_MASK) >> ENET_EIMR_EBERR_SHIFT)
+#define ENET_BRD_EIMR_EBERR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_EBERR_SHIFT))
+
+/*! @brief Set the EBERR field to a new value. */
+#define ENET_WR_EIMR_EBERR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_EBERR_MASK, ENET_EIMR_EBERR(value)))
+#define ENET_BWR_EIMR_EBERR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_EBERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field MII[23] (RW)
+ *
+ * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR MII field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_MII field. */
+#define ENET_RD_EIMR_MII(base) ((ENET_EIMR_REG(base) & ENET_EIMR_MII_MASK) >> ENET_EIMR_MII_SHIFT)
+#define ENET_BRD_EIMR_MII(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_MII_SHIFT))
+
+/*! @brief Set the MII field to a new value. */
+#define ENET_WR_EIMR_MII(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_MII_MASK, ENET_EIMR_MII(value)))
+#define ENET_BWR_EIMR_MII(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_MII_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RXB[24] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXB field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RXB field. */
+#define ENET_RD_EIMR_RXB(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RXB_MASK) >> ENET_EIMR_RXB_SHIFT)
+#define ENET_BRD_EIMR_RXB(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXB_SHIFT))
+
+/*! @brief Set the RXB field to a new value. */
+#define ENET_WR_EIMR_RXB(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RXB_MASK, ENET_EIMR_RXB(value)))
+#define ENET_BWR_EIMR_RXB(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RXF[25] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RXF field. */
+#define ENET_RD_EIMR_RXF(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RXF_MASK) >> ENET_EIMR_RXF_SHIFT)
+#define ENET_BRD_EIMR_RXF(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXF_SHIFT))
+
+/*! @brief Set the RXF field to a new value. */
+#define ENET_WR_EIMR_RXF(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RXF_MASK, ENET_EIMR_RXF(value)))
+#define ENET_BWR_EIMR_RXF(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TXB[26] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TXB field. */
+#define ENET_RD_EIMR_TXB(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TXB_MASK) >> ENET_EIMR_TXB_SHIFT)
+#define ENET_BRD_EIMR_TXB(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXB_SHIFT))
+
+/*! @brief Set the TXB field to a new value. */
+#define ENET_WR_EIMR_TXB(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TXB_MASK, ENET_EIMR_TXB(value)))
+#define ENET_BWR_EIMR_TXB(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TXF[27] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TXF field. */
+#define ENET_RD_EIMR_TXF(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TXF_MASK) >> ENET_EIMR_TXF_SHIFT)
+#define ENET_BRD_EIMR_TXF(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXF_SHIFT))
+
+/*! @brief Set the TXF field to a new value. */
+#define ENET_WR_EIMR_TXF(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TXF_MASK, ENET_EIMR_TXF(value)))
+#define ENET_BWR_EIMR_TXF(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field GRA[28] (RW)
+ *
+ * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR GRA field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_GRA field. */
+#define ENET_RD_EIMR_GRA(base) ((ENET_EIMR_REG(base) & ENET_EIMR_GRA_MASK) >> ENET_EIMR_GRA_SHIFT)
+#define ENET_BRD_EIMR_GRA(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_GRA_SHIFT))
+
+/*! @brief Set the GRA field to a new value. */
+#define ENET_WR_EIMR_GRA(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_GRA_MASK, ENET_EIMR_GRA(value)))
+#define ENET_BWR_EIMR_GRA(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_GRA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field BABT[29] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABT
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_BABT field. */
+#define ENET_RD_EIMR_BABT(base) ((ENET_EIMR_REG(base) & ENET_EIMR_BABT_MASK) >> ENET_EIMR_BABT_SHIFT)
+#define ENET_BRD_EIMR_BABT(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABT_SHIFT))
+
+/*! @brief Set the BABT field to a new value. */
+#define ENET_WR_EIMR_BABT(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_BABT_MASK, ENET_EIMR_BABT(value)))
+#define ENET_BWR_EIMR_BABT(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field BABR[30] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_BABR field. */
+#define ENET_RD_EIMR_BABR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_BABR_MASK) >> ENET_EIMR_BABR_SHIFT)
+#define ENET_BRD_EIMR_BABR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABR_SHIFT))
+
+/*! @brief Set the BABR field to a new value. */
+#define ENET_WR_EIMR_BABR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_BABR_MASK, ENET_EIMR_BABR(value)))
+#define ENET_BWR_EIMR_BABR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RDAR - Receive Descriptor Active Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RDAR - Receive Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDAR is a command register, written by the user, to indicate that the receive
+ * descriptor ring has been updated, that is, that the driver produced empty
+ * receive buffers with the empty bit set.
+ */
+/*!
+ * @name Constants and macros for entire ENET_RDAR register
+ */
+/*@{*/
+#define ENET_RD_RDAR(base)       (ENET_RDAR_REG(base))
+#define ENET_WR_RDAR(base, value) (ENET_RDAR_REG(base) = (value))
+#define ENET_RMW_RDAR(base, mask, value) (ENET_WR_RDAR(base, (ENET_RD_RDAR(base) & ~(mask)) | (value)))
+#define ENET_SET_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) |  (value)))
+#define ENET_CLR_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) & ~(value)))
+#define ENET_TOG_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDAR, field RDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This field is cleared by the MAC device when no additional empty
+ * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
+ * from set to cleared or when ECR[RESET] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RDAR_RDAR field. */
+#define ENET_RD_RDAR_RDAR(base) ((ENET_RDAR_REG(base) & ENET_RDAR_RDAR_MASK) >> ENET_RDAR_RDAR_SHIFT)
+#define ENET_BRD_RDAR_RDAR(base) (BITBAND_ACCESS32(&ENET_RDAR_REG(base), ENET_RDAR_RDAR_SHIFT))
+
+/*! @brief Set the RDAR field to a new value. */
+#define ENET_WR_RDAR_RDAR(base, value) (ENET_RMW_RDAR(base, ENET_RDAR_RDAR_MASK, ENET_RDAR_RDAR(value)))
+#define ENET_BWR_RDAR_RDAR(base, value) (BITBAND_ACCESS32(&ENET_RDAR_REG(base), ENET_RDAR_RDAR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TDAR - Transmit Descriptor Active Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TDAR - Transmit Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The TDAR is a command register that the user writes to indicate that the
+ * transmit descriptor ring has been updated, that is, that transmit buffers have
+ * been produced by the driver with the ready bit set in the buffer descriptor. The
+ * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
+ * cleared, or when ECR[RESET] is set.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TDAR register
+ */
+/*@{*/
+#define ENET_RD_TDAR(base)       (ENET_TDAR_REG(base))
+#define ENET_WR_TDAR(base, value) (ENET_TDAR_REG(base) = (value))
+#define ENET_RMW_TDAR(base, mask, value) (ENET_WR_TDAR(base, (ENET_RD_TDAR(base) & ~(mask)) | (value)))
+#define ENET_SET_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) |  (value)))
+#define ENET_CLR_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) & ~(value)))
+#define ENET_TOG_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDAR, field TDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This bit is cleared by the MAC device when no additional ready descriptors
+ * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
+ * set to cleared or when ECR[RESET] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TDAR_TDAR field. */
+#define ENET_RD_TDAR_TDAR(base) ((ENET_TDAR_REG(base) & ENET_TDAR_TDAR_MASK) >> ENET_TDAR_TDAR_SHIFT)
+#define ENET_BRD_TDAR_TDAR(base) (BITBAND_ACCESS32(&ENET_TDAR_REG(base), ENET_TDAR_TDAR_SHIFT))
+
+/*! @brief Set the TDAR field to a new value. */
+#define ENET_WR_TDAR_TDAR(base, value) (ENET_RMW_TDAR(base, ENET_TDAR_TDAR_MASK, ENET_TDAR_TDAR(value)))
+#define ENET_BWR_TDAR_TDAR(base, value) (BITBAND_ACCESS32(&ENET_TDAR_REG(base), ENET_TDAR_TDAR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ECR - Ethernet Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ECR - Ethernet Control Register (RW)
+ *
+ * Reset value: 0xF0000000U
+ *
+ * ECR is a read/write user register, though hardware may also alter fields in
+ * this register. It controls many of the high level features of the Ethernet MAC,
+ * including legacy FEC support through the EN1588 field.
+ */
+/*!
+ * @name Constants and macros for entire ENET_ECR register
+ */
+/*@{*/
+#define ENET_RD_ECR(base)        (ENET_ECR_REG(base))
+#define ENET_WR_ECR(base, value) (ENET_ECR_REG(base) = (value))
+#define ENET_RMW_ECR(base, mask, value) (ENET_WR_ECR(base, (ENET_RD_ECR(base) & ~(mask)) | (value)))
+#define ENET_SET_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) |  (value)))
+#define ENET_CLR_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) & ~(value)))
+#define ENET_TOG_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ECR bitfields
+ */
+
+/*!
+ * @name Register ENET_ECR, field RESET[0] (RW)
+ *
+ * When this field is set, it clears the ETHEREN field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_RESET field. */
+#define ENET_RD_ECR_RESET(base) ((ENET_ECR_REG(base) & ENET_ECR_RESET_MASK) >> ENET_ECR_RESET_SHIFT)
+#define ENET_BRD_ECR_RESET(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_RESET_SHIFT))
+
+/*! @brief Set the RESET field to a new value. */
+#define ENET_WR_ECR_RESET(base, value) (ENET_RMW_ECR(base, ENET_ECR_RESET_MASK, ENET_ECR_RESET(value)))
+#define ENET_BWR_ECR_RESET(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_RESET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field ETHEREN[1] (RW)
+ *
+ * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
+ * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
+ * descriptor, and FIFO control logic are reset, including the buffer descriptor and
+ * FIFO pointers. Hardware clears this field under the following conditions: RESET
+ * is set by software An error condition causes the EBERR field to set. ETHEREN
+ * must be set at the very last step during ENET
+ * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
+ * is cleared to 0 by software then then next time ETHEREN is set, the EIR
+ * interrupts must cleared to 0 due to previous pending interrupts.
+ *
+ * Values:
+ * - 0b0 - Reception immediately stops and transmission stops after a bad CRC is
+ *     appended to any currently transmitted frame.
+ * - 0b1 - MAC is enabled, and reception and transmission are possible.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_ETHEREN field. */
+#define ENET_RD_ECR_ETHEREN(base) ((ENET_ECR_REG(base) & ENET_ECR_ETHEREN_MASK) >> ENET_ECR_ETHEREN_SHIFT)
+#define ENET_BRD_ECR_ETHEREN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_ETHEREN_SHIFT))
+
+/*! @brief Set the ETHEREN field to a new value. */
+#define ENET_WR_ECR_ETHEREN(base, value) (ENET_RMW_ECR(base, ENET_ECR_ETHEREN_MASK, ENET_ECR_ETHEREN(value)))
+#define ENET_BWR_ECR_ETHEREN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_ETHEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field MAGICEN[2] (RW)
+ *
+ * Enables/disables magic packet detection. MAGICEN is relevant only if the
+ * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
+ * sleep mode and magic packet detection.
+ *
+ * Values:
+ * - 0b0 - Magic detection logic disabled.
+ * - 0b1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a
+ *     frame is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_MAGICEN field. */
+#define ENET_RD_ECR_MAGICEN(base) ((ENET_ECR_REG(base) & ENET_ECR_MAGICEN_MASK) >> ENET_ECR_MAGICEN_SHIFT)
+#define ENET_BRD_ECR_MAGICEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_MAGICEN_SHIFT))
+
+/*! @brief Set the MAGICEN field to a new value. */
+#define ENET_WR_ECR_MAGICEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_MAGICEN_MASK, ENET_ECR_MAGICEN(value)))
+#define ENET_BWR_ECR_MAGICEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_MAGICEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field SLEEP[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operating mode.
+ * - 0b1 - Sleep mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_SLEEP field. */
+#define ENET_RD_ECR_SLEEP(base) ((ENET_ECR_REG(base) & ENET_ECR_SLEEP_MASK) >> ENET_ECR_SLEEP_SHIFT)
+#define ENET_BRD_ECR_SLEEP(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_SLEEP_SHIFT))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define ENET_WR_ECR_SLEEP(base, value) (ENET_RMW_ECR(base, ENET_ECR_SLEEP_MASK, ENET_ECR_SLEEP(value)))
+#define ENET_BWR_ECR_SLEEP(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_SLEEP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field EN1588[4] (RW)
+ *
+ * Enables enhanced functionality of the MAC.
+ *
+ * Values:
+ * - 0b0 - Legacy FEC buffer descriptors and functions enabled.
+ * - 0b1 - Enhanced frame time-stamping functions enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_EN1588 field. */
+#define ENET_RD_ECR_EN1588(base) ((ENET_ECR_REG(base) & ENET_ECR_EN1588_MASK) >> ENET_ECR_EN1588_SHIFT)
+#define ENET_BRD_ECR_EN1588(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_EN1588_SHIFT))
+
+/*! @brief Set the EN1588 field to a new value. */
+#define ENET_WR_ECR_EN1588(base, value) (ENET_RMW_ECR(base, ENET_ECR_EN1588_MASK, ENET_ECR_EN1588(value)))
+#define ENET_BWR_ECR_EN1588(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_EN1588_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field DBGEN[6] (RW)
+ *
+ * Enables the MAC to enter hardware freeze mode when the device enters debug
+ * mode.
+ *
+ * Values:
+ * - 0b0 - MAC continues operation in debug mode.
+ * - 0b1 - MAC enters hardware freeze mode when the processor is in debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_DBGEN field. */
+#define ENET_RD_ECR_DBGEN(base) ((ENET_ECR_REG(base) & ENET_ECR_DBGEN_MASK) >> ENET_ECR_DBGEN_SHIFT)
+#define ENET_BRD_ECR_DBGEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBGEN_SHIFT))
+
+/*! @brief Set the DBGEN field to a new value. */
+#define ENET_WR_ECR_DBGEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_DBGEN_MASK, ENET_ECR_DBGEN(value)))
+#define ENET_BWR_ECR_DBGEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field STOPEN[7] (RW)
+ *
+ * Controls device behavior in doze mode. In doze mode, if this field is set
+ * then all the clocks of the ENET assembly are disabled, except the RMII /MII
+ * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
+ * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
+ * can still wake the system after receiving a magic packet in stop mode. MAGICEN
+ * must be set prior to entering sleep/stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_STOPEN field. */
+#define ENET_RD_ECR_STOPEN(base) ((ENET_ECR_REG(base) & ENET_ECR_STOPEN_MASK) >> ENET_ECR_STOPEN_SHIFT)
+#define ENET_BRD_ECR_STOPEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_STOPEN_SHIFT))
+
+/*! @brief Set the STOPEN field to a new value. */
+#define ENET_WR_ECR_STOPEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_STOPEN_MASK, ENET_ECR_STOPEN(value)))
+#define ENET_BWR_ECR_STOPEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_STOPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field DBSWP[8] (RW)
+ *
+ * Swaps the byte locations of the buffer descriptors. This field must be
+ * written to 1 after reset.
+ *
+ * Values:
+ * - 0b0 - The buffer descriptor bytes are not swapped to support big-endian
+ *     devices.
+ * - 0b1 - The buffer descriptor bytes are swapped to support little-endian
+ *     devices.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_DBSWP field. */
+#define ENET_RD_ECR_DBSWP(base) ((ENET_ECR_REG(base) & ENET_ECR_DBSWP_MASK) >> ENET_ECR_DBSWP_SHIFT)
+#define ENET_BRD_ECR_DBSWP(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBSWP_SHIFT))
+
+/*! @brief Set the DBSWP field to a new value. */
+#define ENET_WR_ECR_DBSWP(base, value) (ENET_RMW_ECR(base, ENET_ECR_DBSWP_MASK, ENET_ECR_DBSWP(value)))
+#define ENET_BWR_ECR_DBSWP(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBSWP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MMFR - MII Management Frame Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MMFR - MII Management Frame Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Writing to MMFR triggers a management frame transaction to the PHY device
+ * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
+ * during a write to MMFR, an MII frame is generated with the data previously written
+ * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
+ * MSCR is currently zero. If the MMFR register is written while frame generation is
+ * in progress, the frame contents are altered. Software must use the EIR[MII]
+ * interrupt indication to avoid writing to the MMFR register while frame
+ * generation is in progress.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MMFR register
+ */
+/*@{*/
+#define ENET_RD_MMFR(base)       (ENET_MMFR_REG(base))
+#define ENET_WR_MMFR(base, value) (ENET_MMFR_REG(base) = (value))
+#define ENET_RMW_MMFR(base, mask, value) (ENET_WR_MMFR(base, (ENET_RD_MMFR(base) & ~(mask)) | (value)))
+#define ENET_SET_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) |  (value)))
+#define ENET_CLR_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) & ~(value)))
+#define ENET_TOG_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MMFR bitfields
+ */
+
+/*!
+ * @name Register ENET_MMFR, field DATA[15:0] (RW)
+ *
+ * This is the field for data to be written to or read from the PHY register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_DATA field. */
+#define ENET_RD_MMFR_DATA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT)
+#define ENET_BRD_MMFR_DATA(base) (ENET_RD_MMFR_DATA(base))
+
+/*! @brief Set the DATA field to a new value. */
+#define ENET_WR_MMFR_DATA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_DATA_MASK, ENET_MMFR_DATA(value)))
+#define ENET_BWR_MMFR_DATA(base, value) (ENET_WR_MMFR_DATA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field TA[17:16] (RW)
+ *
+ * This field must be programmed to 10 to generate a valid MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_TA field. */
+#define ENET_RD_MMFR_TA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_TA_MASK) >> ENET_MMFR_TA_SHIFT)
+#define ENET_BRD_MMFR_TA(base) (ENET_RD_MMFR_TA(base))
+
+/*! @brief Set the TA field to a new value. */
+#define ENET_WR_MMFR_TA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_TA_MASK, ENET_MMFR_TA(value)))
+#define ENET_BWR_MMFR_TA(base, value) (ENET_WR_MMFR_TA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field RA[22:18] (RW)
+ *
+ * Specifies one of up to 32 registers within the specified PHY device.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_RA field. */
+#define ENET_RD_MMFR_RA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_RA_MASK) >> ENET_MMFR_RA_SHIFT)
+#define ENET_BRD_MMFR_RA(base) (ENET_RD_MMFR_RA(base))
+
+/*! @brief Set the RA field to a new value. */
+#define ENET_WR_MMFR_RA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_RA_MASK, ENET_MMFR_RA(value)))
+#define ENET_BWR_MMFR_RA(base, value) (ENET_WR_MMFR_RA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field PA[27:23] (RW)
+ *
+ * Specifies one of up to 32 attached PHY devices.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_PA field. */
+#define ENET_RD_MMFR_PA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_PA_MASK) >> ENET_MMFR_PA_SHIFT)
+#define ENET_BRD_MMFR_PA(base) (ENET_RD_MMFR_PA(base))
+
+/*! @brief Set the PA field to a new value. */
+#define ENET_WR_MMFR_PA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_PA_MASK, ENET_MMFR_PA(value)))
+#define ENET_BWR_MMFR_PA(base, value) (ENET_WR_MMFR_PA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field OP[29:28] (RW)
+ *
+ * Determines the frame operation.
+ *
+ * Values:
+ * - 0b00 - Write frame operation, but not MII compliant.
+ * - 0b01 - Write frame operation for a valid MII management frame.
+ * - 0b10 - Read frame operation for a valid MII management frame.
+ * - 0b11 - Read frame operation, but not MII compliant.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_OP field. */
+#define ENET_RD_MMFR_OP(base) ((ENET_MMFR_REG(base) & ENET_MMFR_OP_MASK) >> ENET_MMFR_OP_SHIFT)
+#define ENET_BRD_MMFR_OP(base) (ENET_RD_MMFR_OP(base))
+
+/*! @brief Set the OP field to a new value. */
+#define ENET_WR_MMFR_OP(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_OP_MASK, ENET_MMFR_OP(value)))
+#define ENET_BWR_MMFR_OP(base, value) (ENET_WR_MMFR_OP(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field ST[31:30] (RW)
+ *
+ * These fields must be programmed to 01 for a valid MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_ST field. */
+#define ENET_RD_MMFR_ST(base) ((ENET_MMFR_REG(base) & ENET_MMFR_ST_MASK) >> ENET_MMFR_ST_SHIFT)
+#define ENET_BRD_MMFR_ST(base) (ENET_RD_MMFR_ST(base))
+
+/*! @brief Set the ST field to a new value. */
+#define ENET_WR_MMFR_ST(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_ST_MASK, ENET_MMFR_ST(value)))
+#define ENET_BWR_MMFR_ST(base, value) (ENET_WR_MMFR_ST(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MSCR - MII Speed Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MSCR - MII Speed Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * MSCR provides control of the MII clock (MDC pin) frequency and allows a
+ * preamble drop on the MII management frame. The MII_SPEED field must be programmed
+ * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
+ * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
+ * a non-zero value to source a read or write management frame. After the
+ * management frame is complete, the MSCR register may optionally be cleared to turn
+ * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
+ * changes during operation. This change takes effect following a rising or falling
+ * edge of MDC. If the internal module clock is 25 MHz, programming this register
+ * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
+ * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
+ * MII_SPEED as a function of internal module clock frequency. Programming Examples
+ * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
+ * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
+ * 0xD 2.36 MHz
+ */
+/*!
+ * @name Constants and macros for entire ENET_MSCR register
+ */
+/*@{*/
+#define ENET_RD_MSCR(base)       (ENET_MSCR_REG(base))
+#define ENET_WR_MSCR(base, value) (ENET_MSCR_REG(base) = (value))
+#define ENET_RMW_MSCR(base, mask, value) (ENET_WR_MSCR(base, (ENET_RD_MSCR(base) & ~(mask)) | (value)))
+#define ENET_SET_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) |  (value)))
+#define ENET_CLR_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) & ~(value)))
+#define ENET_TOG_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MSCR bitfields
+ */
+
+/*!
+ * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
+ *
+ * Controls the frequency of the MII management interface clock (MDC) relative
+ * to the internal module clock. A value of 0 in this field turns off MDC and
+ * leaves it in low voltage state. Any non-zero value results in the MDC frequency
+ * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_MII_SPEED field. */
+#define ENET_RD_MSCR_MII_SPEED(base) ((ENET_MSCR_REG(base) & ENET_MSCR_MII_SPEED_MASK) >> ENET_MSCR_MII_SPEED_SHIFT)
+#define ENET_BRD_MSCR_MII_SPEED(base) (ENET_RD_MSCR_MII_SPEED(base))
+
+/*! @brief Set the MII_SPEED field to a new value. */
+#define ENET_WR_MSCR_MII_SPEED(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_MII_SPEED_MASK, ENET_MSCR_MII_SPEED(value)))
+#define ENET_BWR_MSCR_MII_SPEED(base, value) (ENET_WR_MSCR_MII_SPEED(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
+ *
+ * Enables/disables prepending a preamble to the MII management frame. The MII
+ * standard allows the preamble to be dropped if the attached PHY devices do not
+ * require it.
+ *
+ * Values:
+ * - 0b0 - Preamble enabled.
+ * - 0b1 - Preamble (32 ones) is not prepended to the MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_DIS_PRE field. */
+#define ENET_RD_MSCR_DIS_PRE(base) ((ENET_MSCR_REG(base) & ENET_MSCR_DIS_PRE_MASK) >> ENET_MSCR_DIS_PRE_SHIFT)
+#define ENET_BRD_MSCR_DIS_PRE(base) (BITBAND_ACCESS32(&ENET_MSCR_REG(base), ENET_MSCR_DIS_PRE_SHIFT))
+
+/*! @brief Set the DIS_PRE field to a new value. */
+#define ENET_WR_MSCR_DIS_PRE(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_DIS_PRE_MASK, ENET_MSCR_DIS_PRE(value)))
+#define ENET_BWR_MSCR_DIS_PRE(base, value) (BITBAND_ACCESS32(&ENET_MSCR_REG(base), ENET_MSCR_DIS_PRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
+ *
+ * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
+ * output. Depending on the host bus frequency, the setting may need to be
+ * increased.
+ *
+ * Values:
+ * - 0b000 - 1 internal module clock cycle
+ * - 0b001 - 2 internal module clock cycles
+ * - 0b010 - 3 internal module clock cycles
+ * - 0b111 - 8 internal module clock cycles
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_HOLDTIME field. */
+#define ENET_RD_MSCR_HOLDTIME(base) ((ENET_MSCR_REG(base) & ENET_MSCR_HOLDTIME_MASK) >> ENET_MSCR_HOLDTIME_SHIFT)
+#define ENET_BRD_MSCR_HOLDTIME(base) (ENET_RD_MSCR_HOLDTIME(base))
+
+/*! @brief Set the HOLDTIME field to a new value. */
+#define ENET_WR_MSCR_HOLDTIME(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_HOLDTIME_MASK, ENET_MSCR_HOLDTIME(value)))
+#define ENET_BWR_MSCR_HOLDTIME(base, value) (ENET_WR_MSCR_HOLDTIME(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MIBC - MIB Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MIBC - MIB Control Register (RW)
+ *
+ * Reset value: 0xC0000000U
+ *
+ * MIBC is a read/write register controlling and observing the state of the MIB
+ * block. Access this register to disable the MIB block operation or clear the
+ * MIB counters. The MIB_DIS field resets to 1.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MIBC register
+ */
+/*@{*/
+#define ENET_RD_MIBC(base)       (ENET_MIBC_REG(base))
+#define ENET_WR_MIBC(base, value) (ENET_MIBC_REG(base) = (value))
+#define ENET_RMW_MIBC(base, mask, value) (ENET_WR_MIBC(base, (ENET_RD_MIBC(base) & ~(mask)) | (value)))
+#define ENET_SET_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) |  (value)))
+#define ENET_CLR_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) & ~(value)))
+#define ENET_TOG_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MIBC bitfields
+ */
+
+/*!
+ * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
+ *
+ * If set, all statistics counters are reset to 0. This field is not
+ * self-clearing. To clear the MIB counters set and then clear the field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_CLEAR field. */
+#define ENET_RD_MIBC_MIB_CLEAR(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_CLEAR_MASK) >> ENET_MIBC_MIB_CLEAR_SHIFT)
+#define ENET_BRD_MIBC_MIB_CLEAR(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_CLEAR_SHIFT))
+
+/*! @brief Set the MIB_CLEAR field to a new value. */
+#define ENET_WR_MIBC_MIB_CLEAR(base, value) (ENET_RMW_MIBC(base, ENET_MIBC_MIB_CLEAR_MASK, ENET_MIBC_MIB_CLEAR(value)))
+#define ENET_BWR_MIBC_MIB_CLEAR(base, value) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_CLEAR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
+ *
+ * If this status field is set, the MIB block is not currently updating any MIB
+ * counters.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_IDLE field. */
+#define ENET_RD_MIBC_MIB_IDLE(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_IDLE_MASK) >> ENET_MIBC_MIB_IDLE_SHIFT)
+#define ENET_BRD_MIBC_MIB_IDLE(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
+ *
+ * If this control field is set, the MIB logic halts and does not update any MIB
+ * counters.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_DIS field. */
+#define ENET_RD_MIBC_MIB_DIS(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_DIS_MASK) >> ENET_MIBC_MIB_DIS_SHIFT)
+#define ENET_BRD_MIBC_MIB_DIS(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_DIS_SHIFT))
+
+/*! @brief Set the MIB_DIS field to a new value. */
+#define ENET_WR_MIBC_MIB_DIS(base, value) (ENET_RMW_MIBC(base, ENET_MIBC_MIB_DIS_MASK, ENET_MIBC_MIB_DIS(value)))
+#define ENET_BWR_MIBC_MIB_DIS(base, value) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_DIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RCR - Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RCR - Receive Control Register (RW)
+ *
+ * Reset value: 0x05EE0001U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RCR register
+ */
+/*@{*/
+#define ENET_RD_RCR(base)        (ENET_RCR_REG(base))
+#define ENET_WR_RCR(base, value) (ENET_RCR_REG(base) = (value))
+#define ENET_RMW_RCR(base, mask, value) (ENET_WR_RCR(base, (ENET_RD_RCR(base) & ~(mask)) | (value)))
+#define ENET_SET_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) |  (value)))
+#define ENET_CLR_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) & ~(value)))
+#define ENET_TOG_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RCR bitfields
+ */
+
+/*!
+ * @name Register ENET_RCR, field LOOP[0] (RW)
+ *
+ * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
+ * RMII_MODE must be written to 0.
+ *
+ * Values:
+ * - 0b0 - Loopback disabled.
+ * - 0b1 - Transmitted frames are looped back internal to the device and
+ *     transmit MII output signals are not asserted. DRT must be cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_LOOP field. */
+#define ENET_RD_RCR_LOOP(base) ((ENET_RCR_REG(base) & ENET_RCR_LOOP_MASK) >> ENET_RCR_LOOP_SHIFT)
+#define ENET_BRD_RCR_LOOP(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_LOOP_SHIFT))
+
+/*! @brief Set the LOOP field to a new value. */
+#define ENET_WR_RCR_LOOP(base, value) (ENET_RMW_RCR(base, ENET_RCR_LOOP_MASK, ENET_RCR_LOOP(value)))
+#define ENET_BWR_RCR_LOOP(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_LOOP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field DRT[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Receive path operates independently of transmit. Used for full-duplex
+ *     or to monitor transmit activity in half-duplex mode.
+ * - 0b1 - Disable reception of frames while transmitting. Normally used for
+ *     half-duplex mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_DRT field. */
+#define ENET_RD_RCR_DRT(base) ((ENET_RCR_REG(base) & ENET_RCR_DRT_MASK) >> ENET_RCR_DRT_SHIFT)
+#define ENET_BRD_RCR_DRT(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_DRT_SHIFT))
+
+/*! @brief Set the DRT field to a new value. */
+#define ENET_WR_RCR_DRT(base, value) (ENET_RMW_RCR(base, ENET_RCR_DRT_MASK, ENET_RCR_DRT(value)))
+#define ENET_BWR_RCR_DRT(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_DRT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field MII_MODE[2] (RW)
+ *
+ * This field must always be set.
+ *
+ * Values:
+ * - 0b0 - Reserved.
+ * - 0b1 - MII or RMII mode, as indicated by the RMII_MODE field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_MII_MODE field. */
+#define ENET_RD_RCR_MII_MODE(base) ((ENET_RCR_REG(base) & ENET_RCR_MII_MODE_MASK) >> ENET_RCR_MII_MODE_SHIFT)
+#define ENET_BRD_RCR_MII_MODE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_MII_MODE_SHIFT))
+
+/*! @brief Set the MII_MODE field to a new value. */
+#define ENET_WR_RCR_MII_MODE(base, value) (ENET_RMW_RCR(base, ENET_RCR_MII_MODE_MASK, ENET_RCR_MII_MODE(value)))
+#define ENET_BWR_RCR_MII_MODE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_MII_MODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PROM[3] (RW)
+ *
+ * All frames are accepted regardless of address matching.
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PROM field. */
+#define ENET_RD_RCR_PROM(base) ((ENET_RCR_REG(base) & ENET_RCR_PROM_MASK) >> ENET_RCR_PROM_SHIFT)
+#define ENET_BRD_RCR_PROM(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PROM_SHIFT))
+
+/*! @brief Set the PROM field to a new value. */
+#define ENET_WR_RCR_PROM(base, value) (ENET_RMW_RCR(base, ENET_RCR_PROM_MASK, ENET_RCR_PROM(value)))
+#define ENET_BWR_RCR_PROM(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PROM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field BC_REJ[4] (RW)
+ *
+ * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
+ * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
+ * broadcast DA are accepted and the MISS (M) is set in the receive buffer
+ * descriptor.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_BC_REJ field. */
+#define ENET_RD_RCR_BC_REJ(base) ((ENET_RCR_REG(base) & ENET_RCR_BC_REJ_MASK) >> ENET_RCR_BC_REJ_SHIFT)
+#define ENET_BRD_RCR_BC_REJ(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_BC_REJ_SHIFT))
+
+/*! @brief Set the BC_REJ field to a new value. */
+#define ENET_WR_RCR_BC_REJ(base, value) (ENET_RMW_RCR(base, ENET_RCR_BC_REJ_MASK, ENET_RCR_BC_REJ(value)))
+#define ENET_BWR_RCR_BC_REJ(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_BC_REJ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field FCE[5] (RW)
+ *
+ * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
+ * transmitter stops transmitting data frames for a given duration.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_FCE field. */
+#define ENET_RD_RCR_FCE(base) ((ENET_RCR_REG(base) & ENET_RCR_FCE_MASK) >> ENET_RCR_FCE_SHIFT)
+#define ENET_BRD_RCR_FCE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_FCE_SHIFT))
+
+/*! @brief Set the FCE field to a new value. */
+#define ENET_WR_RCR_FCE(base, value) (ENET_RMW_RCR(base, ENET_RCR_FCE_MASK, ENET_RCR_FCE(value)))
+#define ENET_BWR_RCR_FCE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_FCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field RMII_MODE[8] (RW)
+ *
+ * Specifies whether the MAC is configured for MII mode or RMII operation .
+ *
+ * Values:
+ * - 0b0 - MAC configured for MII mode.
+ * - 0b1 - MAC configured for RMII operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_RMII_MODE field. */
+#define ENET_RD_RCR_RMII_MODE(base) ((ENET_RCR_REG(base) & ENET_RCR_RMII_MODE_MASK) >> ENET_RCR_RMII_MODE_SHIFT)
+#define ENET_BRD_RCR_RMII_MODE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_MODE_SHIFT))
+
+/*! @brief Set the RMII_MODE field to a new value. */
+#define ENET_WR_RCR_RMII_MODE(base, value) (ENET_RMW_RCR(base, ENET_RCR_RMII_MODE_MASK, ENET_RCR_RMII_MODE(value)))
+#define ENET_BWR_RCR_RMII_MODE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_MODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field RMII_10T[9] (RW)
+ *
+ * Enables 10-Mbps mode of the RMII .
+ *
+ * Values:
+ * - 0b0 - 100 Mbps operation.
+ * - 0b1 - 10 Mbps operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_RMII_10T field. */
+#define ENET_RD_RCR_RMII_10T(base) ((ENET_RCR_REG(base) & ENET_RCR_RMII_10T_MASK) >> ENET_RCR_RMII_10T_SHIFT)
+#define ENET_BRD_RCR_RMII_10T(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_10T_SHIFT))
+
+/*! @brief Set the RMII_10T field to a new value. */
+#define ENET_WR_RCR_RMII_10T(base, value) (ENET_RMW_RCR(base, ENET_RCR_RMII_10T_MASK, ENET_RCR_RMII_10T(value)))
+#define ENET_BWR_RCR_RMII_10T(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_10T_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PADEN[12] (RW)
+ *
+ * Specifies whether the MAC removes padding from received frames.
+ *
+ * Values:
+ * - 0b0 - No padding is removed on receive by the MAC.
+ * - 0b1 - Padding is removed from received frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PADEN field. */
+#define ENET_RD_RCR_PADEN(base) ((ENET_RCR_REG(base) & ENET_RCR_PADEN_MASK) >> ENET_RCR_PADEN_SHIFT)
+#define ENET_BRD_RCR_PADEN(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PADEN_SHIFT))
+
+/*! @brief Set the PADEN field to a new value. */
+#define ENET_WR_RCR_PADEN(base, value) (ENET_RMW_RCR(base, ENET_RCR_PADEN_MASK, ENET_RCR_PADEN(value)))
+#define ENET_BWR_RCR_PADEN(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PADEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PAUFWD[13] (RW)
+ *
+ * Specifies whether pause frames are terminated or forwarded.
+ *
+ * Values:
+ * - 0b0 - Pause frames are terminated and discarded in the MAC.
+ * - 0b1 - Pause frames are forwarded to the user application.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PAUFWD field. */
+#define ENET_RD_RCR_PAUFWD(base) ((ENET_RCR_REG(base) & ENET_RCR_PAUFWD_MASK) >> ENET_RCR_PAUFWD_SHIFT)
+#define ENET_BRD_RCR_PAUFWD(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PAUFWD_SHIFT))
+
+/*! @brief Set the PAUFWD field to a new value. */
+#define ENET_WR_RCR_PAUFWD(base, value) (ENET_RMW_RCR(base, ENET_RCR_PAUFWD_MASK, ENET_RCR_PAUFWD(value)))
+#define ENET_BWR_RCR_PAUFWD(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PAUFWD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field CRCFWD[14] (RW)
+ *
+ * Specifies whether the CRC field of received frames is transmitted or
+ * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
+ * field is checked and always terminated and removed.
+ *
+ * Values:
+ * - 0b0 - The CRC field of received frames is transmitted to the user
+ *     application.
+ * - 0b1 - The CRC field is stripped from the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_CRCFWD field. */
+#define ENET_RD_RCR_CRCFWD(base) ((ENET_RCR_REG(base) & ENET_RCR_CRCFWD_MASK) >> ENET_RCR_CRCFWD_SHIFT)
+#define ENET_BRD_RCR_CRCFWD(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CRCFWD_SHIFT))
+
+/*! @brief Set the CRCFWD field to a new value. */
+#define ENET_WR_RCR_CRCFWD(base, value) (ENET_RMW_RCR(base, ENET_RCR_CRCFWD_MASK, ENET_RCR_CRCFWD(value)))
+#define ENET_BWR_RCR_CRCFWD(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CRCFWD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field CFEN[15] (RW)
+ *
+ * Enables/disables the MAC control frame.
+ *
+ * Values:
+ * - 0b0 - MAC control frames with any opcode other than 0x0001 (pause frame)
+ *     are accepted and forwarded to the client interface.
+ * - 0b1 - MAC control frames with any opcode other than 0x0001 (pause frame)
+ *     are silently discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_CFEN field. */
+#define ENET_RD_RCR_CFEN(base) ((ENET_RCR_REG(base) & ENET_RCR_CFEN_MASK) >> ENET_RCR_CFEN_SHIFT)
+#define ENET_BRD_RCR_CFEN(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CFEN_SHIFT))
+
+/*! @brief Set the CFEN field to a new value. */
+#define ENET_WR_RCR_CFEN(base, value) (ENET_RMW_RCR(base, ENET_RCR_CFEN_MASK, ENET_RCR_CFEN(value)))
+#define ENET_BWR_RCR_CFEN(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
+ *
+ * Resets to decimal 1518. Length is measured starting at DA and includes the
+ * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
+ * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
+ * to occur and set the LG field in the end of frame receive buffer descriptor.
+ * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
+ * supported.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_MAX_FL field. */
+#define ENET_RD_RCR_MAX_FL(base) ((ENET_RCR_REG(base) & ENET_RCR_MAX_FL_MASK) >> ENET_RCR_MAX_FL_SHIFT)
+#define ENET_BRD_RCR_MAX_FL(base) (ENET_RD_RCR_MAX_FL(base))
+
+/*! @brief Set the MAX_FL field to a new value. */
+#define ENET_WR_RCR_MAX_FL(base, value) (ENET_RMW_RCR(base, ENET_RCR_MAX_FL_MASK, ENET_RCR_MAX_FL(value)))
+#define ENET_BWR_RCR_MAX_FL(base, value) (ENET_WR_RCR_MAX_FL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field NLC[30] (RW)
+ *
+ * Enables/disables a payload length check.
+ *
+ * Values:
+ * - 0b0 - The payload length check is disabled.
+ * - 0b1 - The core checks the frame's payload length with the frame length/type
+ *     field. Errors are indicated in the EIR[PLC] field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_NLC field. */
+#define ENET_RD_RCR_NLC(base) ((ENET_RCR_REG(base) & ENET_RCR_NLC_MASK) >> ENET_RCR_NLC_SHIFT)
+#define ENET_BRD_RCR_NLC(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_NLC_SHIFT))
+
+/*! @brief Set the NLC field to a new value. */
+#define ENET_WR_RCR_NLC(base, value) (ENET_RMW_RCR(base, ENET_RCR_NLC_MASK, ENET_RCR_NLC(value)))
+#define ENET_BWR_RCR_NLC(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_NLC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field GRS[31] (RO)
+ *
+ * Read-only status indicating that the MAC receive datapath is stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_GRS field. */
+#define ENET_RD_RCR_GRS(base) ((ENET_RCR_REG(base) & ENET_RCR_GRS_MASK) >> ENET_RCR_GRS_SHIFT)
+#define ENET_BRD_RCR_GRS(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_GRS_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCR - Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCR - Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR is read/write and configures the transmit block. This register is cleared
+ * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCR register
+ */
+/*@{*/
+#define ENET_RD_TCR(base)        (ENET_TCR_REG(base))
+#define ENET_WR_TCR(base, value) (ENET_TCR_REG(base) = (value))
+#define ENET_RMW_TCR(base, mask, value) (ENET_WR_TCR(base, (ENET_RD_TCR(base) & ~(mask)) | (value)))
+#define ENET_SET_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) |  (value)))
+#define ENET_CLR_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) & ~(value)))
+#define ENET_TOG_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TCR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCR, field GTS[0] (RW)
+ *
+ * When this field is set, MAC stops transmission after any frame currently
+ * transmitted is complete and EIR[GRA] is set. If frame transmission is not
+ * currently underway, the GRA interrupt is asserted immediately. After transmission
+ * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
+ * transmitted. If an early collision occurs during transmission when GTS is set,
+ * transmission stops after the collision. The frame is transmitted again after GTS is
+ * cleared. There may be old frames in the transmit FIFO that transmit when GTS
+ * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_GTS field. */
+#define ENET_RD_TCR_GTS(base) ((ENET_TCR_REG(base) & ENET_TCR_GTS_MASK) >> ENET_TCR_GTS_SHIFT)
+#define ENET_BRD_TCR_GTS(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_GTS_SHIFT))
+
+/*! @brief Set the GTS field to a new value. */
+#define ENET_WR_TCR_GTS(base, value) (ENET_RMW_TCR(base, ENET_TCR_GTS_MASK, ENET_TCR_GTS(value)))
+#define ENET_BWR_TCR_GTS(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_GTS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field FDEN[2] (RW)
+ *
+ * If this field is set, frames transmit independent of carrier sense and
+ * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_FDEN field. */
+#define ENET_RD_TCR_FDEN(base) ((ENET_TCR_REG(base) & ENET_TCR_FDEN_MASK) >> ENET_TCR_FDEN_SHIFT)
+#define ENET_BRD_TCR_FDEN(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_FDEN_SHIFT))
+
+/*! @brief Set the FDEN field to a new value. */
+#define ENET_WR_TCR_FDEN(base, value) (ENET_RMW_TCR(base, ENET_TCR_FDEN_MASK, ENET_TCR_FDEN(value)))
+#define ENET_BWR_TCR_FDEN(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_FDEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
+ *
+ * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
+ * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
+ * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
+ * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
+ * the MAC may continue transmitting a MAC control PAUSE frame.
+ *
+ * Values:
+ * - 0b0 - No PAUSE frame transmitted.
+ * - 0b1 - The MAC stops transmission of data frames after the current
+ *     transmission is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_TFC_PAUSE field. */
+#define ENET_RD_TCR_TFC_PAUSE(base) ((ENET_TCR_REG(base) & ENET_TCR_TFC_PAUSE_MASK) >> ENET_TCR_TFC_PAUSE_SHIFT)
+#define ENET_BRD_TCR_TFC_PAUSE(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_TFC_PAUSE_SHIFT))
+
+/*! @brief Set the TFC_PAUSE field to a new value. */
+#define ENET_WR_TCR_TFC_PAUSE(base, value) (ENET_RMW_TCR(base, ENET_TCR_TFC_PAUSE_MASK, ENET_TCR_TFC_PAUSE(value)))
+#define ENET_BWR_TCR_TFC_PAUSE(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_TFC_PAUSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
+ *
+ * This status field is set when a full-duplex flow control pause frame is
+ * received and the transmitter pauses for the duration defined in this pause frame.
+ * This field automatically clears when the pause duration is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_RFC_PAUSE field. */
+#define ENET_RD_TCR_RFC_PAUSE(base) ((ENET_TCR_REG(base) & ENET_TCR_RFC_PAUSE_MASK) >> ENET_TCR_RFC_PAUSE_SHIFT)
+#define ENET_BRD_TCR_RFC_PAUSE(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_RFC_PAUSE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
+ *
+ * If ADDINS is set, indicates the MAC address that overwrites the source MAC
+ * address.
+ *
+ * Values:
+ * - 0b000 - Node MAC address programmed on PADDR1/2 registers.
+ * - 0b100 - Reserved.
+ * - 0b101 - Reserved.
+ * - 0b110 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_ADDSEL field. */
+#define ENET_RD_TCR_ADDSEL(base) ((ENET_TCR_REG(base) & ENET_TCR_ADDSEL_MASK) >> ENET_TCR_ADDSEL_SHIFT)
+#define ENET_BRD_TCR_ADDSEL(base) (ENET_RD_TCR_ADDSEL(base))
+
+/*! @brief Set the ADDSEL field to a new value. */
+#define ENET_WR_TCR_ADDSEL(base, value) (ENET_RMW_TCR(base, ENET_TCR_ADDSEL_MASK, ENET_TCR_ADDSEL(value)))
+#define ENET_BWR_TCR_ADDSEL(base, value) (ENET_WR_TCR_ADDSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field ADDINS[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The source MAC address is not modified by the MAC.
+ * - 0b1 - The MAC overwrites the source MAC address with the programmed MAC
+ *     address according to ADDSEL.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_ADDINS field. */
+#define ENET_RD_TCR_ADDINS(base) ((ENET_TCR_REG(base) & ENET_TCR_ADDINS_MASK) >> ENET_TCR_ADDINS_SHIFT)
+#define ENET_BRD_TCR_ADDINS(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_ADDINS_SHIFT))
+
+/*! @brief Set the ADDINS field to a new value. */
+#define ENET_WR_TCR_ADDINS(base, value) (ENET_RMW_TCR(base, ENET_TCR_ADDINS_MASK, ENET_TCR_ADDINS(value)))
+#define ENET_BWR_TCR_ADDINS(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_ADDINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field CRCFWD[9] (RW)
+ *
+ * Values:
+ * - 0b0 - TxBD[TC] controls whether the frame has a CRC from the application.
+ * - 0b1 - The transmitter does not append any CRC to transmitted frames, as it
+ *     is expecting a frame with CRC from the application.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_CRCFWD field. */
+#define ENET_RD_TCR_CRCFWD(base) ((ENET_TCR_REG(base) & ENET_TCR_CRCFWD_MASK) >> ENET_TCR_CRCFWD_SHIFT)
+#define ENET_BRD_TCR_CRCFWD(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_CRCFWD_SHIFT))
+
+/*! @brief Set the CRCFWD field to a new value. */
+#define ENET_WR_TCR_CRCFWD(base, value) (ENET_RMW_TCR(base, ENET_TCR_CRCFWD_MASK, ENET_TCR_CRCFWD(value)))
+#define ENET_BWR_TCR_CRCFWD(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_CRCFWD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_PALR - Physical Address Lower Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_PALR - Physical Address Lower Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
+ * in the address recognition process to compare with the destination address
+ * (DA) field of receive frames with an individual DA. In addition, this register
+ * is used in bytes 0 through 3 of the six-byte source address field when
+ * transmitting PAUSE frames. This register is not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_PALR register
+ */
+/*@{*/
+#define ENET_RD_PALR(base)       (ENET_PALR_REG(base))
+#define ENET_WR_PALR(base, value) (ENET_PALR_REG(base) = (value))
+#define ENET_RMW_PALR(base, mask, value) (ENET_WR_PALR(base, (ENET_RD_PALR(base) & ~(mask)) | (value)))
+#define ENET_SET_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) |  (value)))
+#define ENET_CLR_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) & ~(value)))
+#define ENET_TOG_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_PAUR - Physical Address Upper Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_PAUR - Physical Address Upper Register (RW)
+ *
+ * Reset value: 0x00008808U
+ *
+ * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
+ * the address recognition process to compare with the destination address (DA)
+ * field of receive frames with an individual DA. In addition, this register is
+ * used in bytes 4 and 5 of the six-byte source address field when transmitting
+ * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
+ * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
+ * you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_PAUR register
+ */
+/*@{*/
+#define ENET_RD_PAUR(base)       (ENET_PAUR_REG(base))
+#define ENET_WR_PAUR(base, value) (ENET_PAUR_REG(base) = (value))
+#define ENET_RMW_PAUR(base, mask, value) (ENET_WR_PAUR(base, (ENET_RD_PAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) |  (value)))
+#define ENET_CLR_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) & ~(value)))
+#define ENET_TOG_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_PAUR bitfields
+ */
+
+/*!
+ * @name Register ENET_PAUR, field TYPE[15:0] (RO)
+ *
+ * These fields have a constant value of 0x8808.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_PAUR_TYPE field. */
+#define ENET_RD_PAUR_TYPE(base) ((ENET_PAUR_REG(base) & ENET_PAUR_TYPE_MASK) >> ENET_PAUR_TYPE_SHIFT)
+#define ENET_BRD_PAUR_TYPE(base) (ENET_RD_PAUR_TYPE(base))
+/*@}*/
+
+/*!
+ * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
+ *
+ * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
+ * for exact match, and the source address field in PAUSE frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_PAUR_PADDR2 field. */
+#define ENET_RD_PAUR_PADDR2(base) ((ENET_PAUR_REG(base) & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT)
+#define ENET_BRD_PAUR_PADDR2(base) (ENET_RD_PAUR_PADDR2(base))
+
+/*! @brief Set the PADDR2 field to a new value. */
+#define ENET_WR_PAUR_PADDR2(base, value) (ENET_RMW_PAUR(base, ENET_PAUR_PADDR2_MASK, ENET_PAUR_PADDR2(value)))
+#define ENET_BWR_PAUR_PADDR2(base, value) (ENET_WR_PAUR_PADDR2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_OPD - Opcode/Pause Duration Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_OPD - Opcode/Pause Duration Register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * OPD is read/write accessible. This register contains the 16-bit opcode and
+ * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
+ * field is a constant value, 0x0001. When another node detects a PAUSE frame,
+ * that node pauses transmission for the duration specified in the pause duration
+ * field. The lower 16 bits of this register are not reset and you must initialize
+ * it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_OPD register
+ */
+/*@{*/
+#define ENET_RD_OPD(base)        (ENET_OPD_REG(base))
+#define ENET_WR_OPD(base, value) (ENET_OPD_REG(base) = (value))
+#define ENET_RMW_OPD(base, mask, value) (ENET_WR_OPD(base, (ENET_RD_OPD(base) & ~(mask)) | (value)))
+#define ENET_SET_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) |  (value)))
+#define ENET_CLR_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) & ~(value)))
+#define ENET_TOG_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_OPD bitfields
+ */
+
+/*!
+ * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
+ *
+ * Pause duration field used in PAUSE frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_OPD_PAUSE_DUR field. */
+#define ENET_RD_OPD_PAUSE_DUR(base) ((ENET_OPD_REG(base) & ENET_OPD_PAUSE_DUR_MASK) >> ENET_OPD_PAUSE_DUR_SHIFT)
+#define ENET_BRD_OPD_PAUSE_DUR(base) (ENET_RD_OPD_PAUSE_DUR(base))
+
+/*! @brief Set the PAUSE_DUR field to a new value. */
+#define ENET_WR_OPD_PAUSE_DUR(base, value) (ENET_RMW_OPD(base, ENET_OPD_PAUSE_DUR_MASK, ENET_OPD_PAUSE_DUR(value)))
+#define ENET_BWR_OPD_PAUSE_DUR(base, value) (ENET_WR_OPD_PAUSE_DUR(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_OPD, field OPCODE[31:16] (RO)
+ *
+ * These fields have a constant value of 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_OPD_OPCODE field. */
+#define ENET_RD_OPD_OPCODE(base) ((ENET_OPD_REG(base) & ENET_OPD_OPCODE_MASK) >> ENET_OPD_OPCODE_SHIFT)
+#define ENET_BRD_OPD_OPCODE(base) (ENET_RD_OPD_OPCODE(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IAUR - Descriptor Individual Upper Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IAUR - Descriptor Individual Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the destination address (DA) field of receive frames with an individual
+ * DA. This register is not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IAUR register
+ */
+/*@{*/
+#define ENET_RD_IAUR(base)       (ENET_IAUR_REG(base))
+#define ENET_WR_IAUR(base, value) (ENET_IAUR_REG(base) = (value))
+#define ENET_RMW_IAUR(base, mask, value) (ENET_WR_IAUR(base, (ENET_RD_IAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) |  (value)))
+#define ENET_CLR_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) & ~(value)))
+#define ENET_TOG_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IALR - Descriptor Individual Lower Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IALR - Descriptor Individual Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IALR contains the lower 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the DA field of receive frames with an individual DA. This register is
+ * not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IALR register
+ */
+/*@{*/
+#define ENET_RD_IALR(base)       (ENET_IALR_REG(base))
+#define ENET_WR_IALR(base, value) (ENET_IALR_REG(base) = (value))
+#define ENET_RMW_IALR(base, mask, value) (ENET_WR_IALR(base, (ENET_RD_IALR(base) & ~(mask)) | (value)))
+#define ENET_SET_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) |  (value)))
+#define ENET_CLR_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) & ~(value)))
+#define ENET_TOG_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_GAUR - Descriptor Group Upper Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_GAUR - Descriptor Group Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+/*!
+ * @name Constants and macros for entire ENET_GAUR register
+ */
+/*@{*/
+#define ENET_RD_GAUR(base)       (ENET_GAUR_REG(base))
+#define ENET_WR_GAUR(base, value) (ENET_GAUR_REG(base) = (value))
+#define ENET_RMW_GAUR(base, mask, value) (ENET_WR_GAUR(base, (ENET_RD_GAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) |  (value)))
+#define ENET_CLR_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) & ~(value)))
+#define ENET_TOG_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_GALR - Descriptor Group Lower Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_GALR - Descriptor Group Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GALR contains the lower 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+/*!
+ * @name Constants and macros for entire ENET_GALR register
+ */
+/*@{*/
+#define ENET_RD_GALR(base)       (ENET_GALR_REG(base))
+#define ENET_WR_GALR(base, value) (ENET_GALR_REG(base) = (value))
+#define ENET_RMW_GALR(base, mask, value) (ENET_WR_GALR(base, (ENET_RD_GALR(base) & ~(mask)) | (value)))
+#define ENET_SET_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) |  (value)))
+#define ENET_CLR_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) & ~(value)))
+#define ENET_TOG_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TFWR - Transmit FIFO Watermark Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TFWR - Transmit FIFO Watermark Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
+ * in the transmit FIFO before transmission of a frame can begin. This allows you
+ * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
+ * latency (TFWR = 11) due to contention for the system bus. Setting the
+ * watermark to a high value minimizes the risk of transmit FIFO underrun due to
+ * contention for the system bus. The byte counts associated with the TFWR field may need
+ * to be modified to match a given system requirement. For example, worst case
+ * bus access latency by the transmit data DMA channel. When the FIFO level
+ * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
+ * transmit control logic starts frame transmission even before the end-of-frame is
+ * available in the FIFO (cut-through operation). If a complete frame has a size
+ * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
+ * to the line. To enable store and forward on the Transmit path, set STR_FWD to
+ * '1'. In this case, the MAC starts to transmit data only when a complete frame
+ * is stored in the Transmit FIFO.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TFWR register
+ */
+/*@{*/
+#define ENET_RD_TFWR(base)       (ENET_TFWR_REG(base))
+#define ENET_WR_TFWR(base, value) (ENET_TFWR_REG(base) = (value))
+#define ENET_RMW_TFWR(base, mask, value) (ENET_WR_TFWR(base, (ENET_RD_TFWR(base) & ~(mask)) | (value)))
+#define ENET_SET_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) |  (value)))
+#define ENET_CLR_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) & ~(value)))
+#define ENET_TOG_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TFWR bitfields
+ */
+
+/*!
+ * @name Register ENET_TFWR, field TFWR[5:0] (RW)
+ *
+ * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
+ * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
+ * begins. If a frame with less than the threshold is written, it is still sent
+ * independently of this threshold setting. The threshold is relevant only if the
+ * frame is larger than the threshold given. This chip may not support the maximum
+ * number of bytes written shown below. See the chip-specific information for the
+ * ENET module for this value.
+ *
+ * Values:
+ * - 0b000000 - 64 bytes written.
+ * - 0b000001 - 64 bytes written.
+ * - 0b000010 - 128 bytes written.
+ * - 0b000011 - 192 bytes written.
+ * - 0b111110 - 3968 bytes written.
+ * - 0b111111 - 4032 bytes written.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TFWR_TFWR field. */
+#define ENET_RD_TFWR_TFWR(base) ((ENET_TFWR_REG(base) & ENET_TFWR_TFWR_MASK) >> ENET_TFWR_TFWR_SHIFT)
+#define ENET_BRD_TFWR_TFWR(base) (ENET_RD_TFWR_TFWR(base))
+
+/*! @brief Set the TFWR field to a new value. */
+#define ENET_WR_TFWR_TFWR(base, value) (ENET_RMW_TFWR(base, ENET_TFWR_TFWR_MASK, ENET_TFWR_TFWR(value)))
+#define ENET_BWR_TFWR_TFWR(base, value) (ENET_WR_TFWR_TFWR(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TFWR, field STRFWD[8] (RW)
+ *
+ * Values:
+ * - 0b0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
+ * - 0b1 - Enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TFWR_STRFWD field. */
+#define ENET_RD_TFWR_STRFWD(base) ((ENET_TFWR_REG(base) & ENET_TFWR_STRFWD_MASK) >> ENET_TFWR_STRFWD_SHIFT)
+#define ENET_BRD_TFWR_STRFWD(base) (BITBAND_ACCESS32(&ENET_TFWR_REG(base), ENET_TFWR_STRFWD_SHIFT))
+
+/*! @brief Set the STRFWD field to a new value. */
+#define ENET_WR_TFWR_STRFWD(base, value) (ENET_RMW_TFWR(base, ENET_TFWR_STRFWD_MASK, ENET_TFWR_STRFWD(value)))
+#define ENET_BWR_TFWR_STRFWD(base, value) (BITBAND_ACCESS32(&ENET_TFWR_REG(base), ENET_TFWR_STRFWD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RDSR - Receive Descriptor Ring Start Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RDSR - Receive Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDSR points to the beginning of the circular receive buffer descriptor queue
+ * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
+ * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
+ * by 16. This register must be initialized prior to operation
+ */
+/*!
+ * @name Constants and macros for entire ENET_RDSR register
+ */
+/*@{*/
+#define ENET_RD_RDSR(base)       (ENET_RDSR_REG(base))
+#define ENET_WR_RDSR(base, value) (ENET_RDSR_REG(base) = (value))
+#define ENET_RMW_RDSR(base, mask, value) (ENET_WR_RDSR(base, (ENET_RD_RDSR(base) & ~(mask)) | (value)))
+#define ENET_SET_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) |  (value)))
+#define ENET_CLR_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) & ~(value)))
+#define ENET_TOG_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the receive buffer descriptor queue.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RDSR_R_DES_START field. */
+#define ENET_RD_RDSR_R_DES_START(base) ((ENET_RDSR_REG(base) & ENET_RDSR_R_DES_START_MASK) >> ENET_RDSR_R_DES_START_SHIFT)
+#define ENET_BRD_RDSR_R_DES_START(base) (ENET_RD_RDSR_R_DES_START(base))
+
+/*! @brief Set the R_DES_START field to a new value. */
+#define ENET_WR_RDSR_R_DES_START(base, value) (ENET_RMW_RDSR(base, ENET_RDSR_R_DES_START_MASK, ENET_RDSR_R_DES_START(value)))
+#define ENET_BWR_RDSR_R_DES_START(base, value) (ENET_WR_RDSR_R_DES_START(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TDSR provides a pointer to the beginning of the circular transmit buffer
+ * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
+ * must be zero); however, it is recommended to be 128-bit aligned, that is,
+ * evenly divisible by 16. This register must be initialized prior to operation.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TDSR register
+ */
+/*@{*/
+#define ENET_RD_TDSR(base)       (ENET_TDSR_REG(base))
+#define ENET_WR_TDSR(base, value) (ENET_TDSR_REG(base) = (value))
+#define ENET_RMW_TDSR(base, mask, value) (ENET_WR_TDSR(base, (ENET_RD_TDSR(base) & ~(mask)) | (value)))
+#define ENET_SET_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) |  (value)))
+#define ENET_CLR_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) & ~(value)))
+#define ENET_TOG_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the transmit buffer descriptor queue.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TDSR_X_DES_START field. */
+#define ENET_RD_TDSR_X_DES_START(base) ((ENET_TDSR_REG(base) & ENET_TDSR_X_DES_START_MASK) >> ENET_TDSR_X_DES_START_SHIFT)
+#define ENET_BRD_TDSR_X_DES_START(base) (ENET_RD_TDSR_X_DES_START(base))
+
+/*! @brief Set the X_DES_START field to a new value. */
+#define ENET_WR_TDSR_X_DES_START(base, value) (ENET_RMW_TDSR(base, ENET_TDSR_X_DES_START_MASK, ENET_TDSR_X_DES_START(value)))
+#define ENET_BWR_TDSR_X_DES_START(base, value) (ENET_WR_TDSR_X_DES_START(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MRBR - Maximum Receive Buffer Size Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MRBR - Maximum Receive Buffer Size Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MRBR is a user-programmable register that dictates the maximum size of
+ * all receive buffers. This value should take into consideration that the receive
+ * CRC is always written into the last receive buffer. To allow one maximum size
+ * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
+ * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
+ * set to zero by the device. To minimize bus usage (descriptor fetches), set
+ * MRBR greater than or equal to 256 bytes. This register must be initialized
+ * before operation.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MRBR register
+ */
+/*@{*/
+#define ENET_RD_MRBR(base)       (ENET_MRBR_REG(base))
+#define ENET_WR_MRBR(base, value) (ENET_MRBR_REG(base) = (value))
+#define ENET_RMW_MRBR(base, mask, value) (ENET_WR_MRBR(base, (ENET_RD_MRBR(base) & ~(mask)) | (value)))
+#define ENET_SET_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) |  (value)))
+#define ENET_CLR_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) & ~(value)))
+#define ENET_TOG_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MRBR bitfields
+ */
+
+/*!
+ * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
+ *
+ * Receive buffer size in bytes.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field. */
+#define ENET_RD_MRBR_R_BUF_SIZE(base) ((ENET_MRBR_REG(base) & ENET_MRBR_R_BUF_SIZE_MASK) >> ENET_MRBR_R_BUF_SIZE_SHIFT)
+#define ENET_BRD_MRBR_R_BUF_SIZE(base) (ENET_RD_MRBR_R_BUF_SIZE(base))
+
+/*! @brief Set the R_BUF_SIZE field to a new value. */
+#define ENET_WR_MRBR_R_BUF_SIZE(base, value) (ENET_RMW_MRBR(base, ENET_MRBR_R_BUF_SIZE_MASK, ENET_MRBR_R_BUF_SIZE(value)))
+#define ENET_BWR_MRBR_R_BUF_SIZE(base, value) (ENET_WR_MRBR_R_BUF_SIZE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RSFL - Receive FIFO Section Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RSFL - Receive FIFO Section Full Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RSFL register
+ */
+/*@{*/
+#define ENET_RD_RSFL(base)       (ENET_RSFL_REG(base))
+#define ENET_WR_RSFL(base, value) (ENET_RSFL_REG(base) = (value))
+#define ENET_RMW_RSFL(base, mask, value) (ENET_WR_RSFL(base, (ENET_RD_RSFL(base) & ~(mask)) | (value)))
+#define ENET_SET_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) |  (value)))
+#define ENET_CLR_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) & ~(value)))
+#define ENET_TOG_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RSFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
+ * this field to enable store and forward on the RX FIFO. When programming a value
+ * greater than 0 (cut-through operation), it must be greater than
+ * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
+ * in the Receive FIFO (cut-through operation).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field. */
+#define ENET_RD_RSFL_RX_SECTION_FULL(base) ((ENET_RSFL_REG(base) & ENET_RSFL_RX_SECTION_FULL_MASK) >> ENET_RSFL_RX_SECTION_FULL_SHIFT)
+#define ENET_BRD_RSFL_RX_SECTION_FULL(base) (ENET_RD_RSFL_RX_SECTION_FULL(base))
+
+/*! @brief Set the RX_SECTION_FULL field to a new value. */
+#define ENET_WR_RSFL_RX_SECTION_FULL(base, value) (ENET_RMW_RSFL(base, ENET_RSFL_RX_SECTION_FULL_MASK, ENET_RSFL_RX_SECTION_FULL(value)))
+#define ENET_BWR_RSFL_RX_SECTION_FULL(base, value) (ENET_WR_RSFL_RX_SECTION_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RSEM - Receive FIFO Section Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RSEM register
+ */
+/*@{*/
+#define ENET_RD_RSEM(base)       (ENET_RSEM_REG(base))
+#define ENET_WR_RSEM(base, value) (ENET_RSEM_REG(base) = (value))
+#define ENET_RMW_RSEM(base, mask, value) (ENET_WR_RSEM(base, (ENET_RD_RSEM(base) & ~(mask)) | (value)))
+#define ENET_SET_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) |  (value)))
+#define ENET_CLR_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) & ~(value)))
+#define ENET_TOG_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
+ * FIFO has reached this level, a pause frame will be issued. A value of 0
+ * disables automatic pause frame generation. When the FIFO level goes below the value
+ * programmed in this field, an XON pause frame is issued to indicate the FIFO
+ * congestion is cleared to the remote Ethernet client. The section-empty
+ * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field. */
+#define ENET_RD_RSEM_RX_SECTION_EMPTY(base) ((ENET_RSEM_REG(base) & ENET_RSEM_RX_SECTION_EMPTY_MASK) >> ENET_RSEM_RX_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_RSEM_RX_SECTION_EMPTY(base) (ENET_RD_RSEM_RX_SECTION_EMPTY(base))
+
+/*! @brief Set the RX_SECTION_EMPTY field to a new value. */
+#define ENET_WR_RSEM_RX_SECTION_EMPTY(base, value) (ENET_RMW_RSEM(base, ENET_RSEM_RX_SECTION_EMPTY_MASK, ENET_RSEM_RX_SECTION_EMPTY(value)))
+#define ENET_BWR_RSEM_RX_SECTION_EMPTY(base, value) (ENET_WR_RSEM_RX_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
+ *
+ * Defines number of frames in the receive FIFO, independent of its size, that
+ * can be accepted. If the limit is reached, reception will continue normally,
+ * however a pause frame will be triggered to indicate a possible congestion to the
+ * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
+ * frame generation
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field. */
+#define ENET_RD_RSEM_STAT_SECTION_EMPTY(base) ((ENET_RSEM_REG(base) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) >> ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_RSEM_STAT_SECTION_EMPTY(base) (ENET_RD_RSEM_STAT_SECTION_EMPTY(base))
+
+/*! @brief Set the STAT_SECTION_EMPTY field to a new value. */
+#define ENET_WR_RSEM_STAT_SECTION_EMPTY(base, value) (ENET_RMW_RSEM(base, ENET_RSEM_STAT_SECTION_EMPTY_MASK, ENET_RSEM_STAT_SECTION_EMPTY(value)))
+#define ENET_BWR_RSEM_STAT_SECTION_EMPTY(base, value) (ENET_WR_RSEM_STAT_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RAEM - Receive FIFO Almost Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RAEM register
+ */
+/*@{*/
+#define ENET_RD_RAEM(base)       (ENET_RAEM_REG(base))
+#define ENET_WR_RAEM(base, value) (ENET_RAEM_REG(base) = (value))
+#define ENET_RMW_RAEM(base, mask, value) (ENET_WR_RAEM(base, (ENET_RD_RAEM(base) & ~(mask)) | (value)))
+#define ENET_SET_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) |  (value)))
+#define ENET_CLR_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) & ~(value)))
+#define ENET_TOG_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field and the end-of-frame has
+ * not been received for the frame yet, the core receive read control stops FIFO
+ * read (and subsequently stops transferring data to the MAC client
+ * application). It continues to deliver the frame, if again more data than the threshold or
+ * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field. */
+#define ENET_RD_RAEM_RX_ALMOST_EMPTY(base) ((ENET_RAEM_REG(base) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) >> ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)
+#define ENET_BRD_RAEM_RX_ALMOST_EMPTY(base) (ENET_RD_RAEM_RX_ALMOST_EMPTY(base))
+
+/*! @brief Set the RX_ALMOST_EMPTY field to a new value. */
+#define ENET_WR_RAEM_RX_ALMOST_EMPTY(base, value) (ENET_RMW_RAEM(base, ENET_RAEM_RX_ALMOST_EMPTY_MASK, ENET_RAEM_RX_ALMOST_EMPTY(value)))
+#define ENET_BWR_RAEM_RX_ALMOST_EMPTY(base, value) (ENET_WR_RAEM_RX_ALMOST_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RAFL - Receive FIFO Almost Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RAFL register
+ */
+/*@{*/
+#define ENET_RD_RAFL(base)       (ENET_RAFL_REG(base))
+#define ENET_WR_RAFL(base, value) (ENET_RAFL_REG(base) = (value))
+#define ENET_RMW_RAFL(base, mask, value) (ENET_WR_RAFL(base, (ENET_RD_RAFL(base) & ~(mask)) | (value)))
+#define ENET_SET_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) |  (value)))
+#define ENET_CLR_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) & ~(value)))
+#define ENET_TOG_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
+ * truncates the received frame to avoid FIFO overflow. The corresponding error
+ * status will be set when the frame is delivered to the application. A minimum
+ * value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field. */
+#define ENET_RD_RAFL_RX_ALMOST_FULL(base) ((ENET_RAFL_REG(base) & ENET_RAFL_RX_ALMOST_FULL_MASK) >> ENET_RAFL_RX_ALMOST_FULL_SHIFT)
+#define ENET_BRD_RAFL_RX_ALMOST_FULL(base) (ENET_RD_RAFL_RX_ALMOST_FULL(base))
+
+/*! @brief Set the RX_ALMOST_FULL field to a new value. */
+#define ENET_WR_RAFL_RX_ALMOST_FULL(base, value) (ENET_RMW_RAFL(base, ENET_RAFL_RX_ALMOST_FULL_MASK, ENET_RAFL_RX_ALMOST_FULL(value)))
+#define ENET_BWR_RAFL_RX_ALMOST_FULL(base, value) (ENET_WR_RAFL_RX_ALMOST_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TSEM - Transmit FIFO Section Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TSEM register
+ */
+/*@{*/
+#define ENET_RD_TSEM(base)       (ENET_TSEM_REG(base))
+#define ENET_WR_TSEM(base, value) (ENET_TSEM_REG(base) = (value))
+#define ENET_RMW_TSEM(base, mask, value) (ENET_WR_TSEM(base, (ENET_RD_TSEM(base) & ~(mask)) | (value)))
+#define ENET_SET_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) |  (value)))
+#define ENET_CLR_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) & ~(value)))
+#define ENET_TOG_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field. */
+#define ENET_RD_TSEM_TX_SECTION_EMPTY(base) ((ENET_TSEM_REG(base) & ENET_TSEM_TX_SECTION_EMPTY_MASK) >> ENET_TSEM_TX_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_TSEM_TX_SECTION_EMPTY(base) (ENET_RD_TSEM_TX_SECTION_EMPTY(base))
+
+/*! @brief Set the TX_SECTION_EMPTY field to a new value. */
+#define ENET_WR_TSEM_TX_SECTION_EMPTY(base, value) (ENET_RMW_TSEM(base, ENET_TSEM_TX_SECTION_EMPTY_MASK, ENET_TSEM_TX_SECTION_EMPTY(value)))
+#define ENET_BWR_TSEM_TX_SECTION_EMPTY(base, value) (ENET_WR_TSEM_TX_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TAEM register
+ */
+/*@{*/
+#define ENET_RD_TAEM(base)       (ENET_TAEM_REG(base))
+#define ENET_WR_TAEM(base, value) (ENET_TAEM_REG(base) = (value))
+#define ENET_RMW_TAEM(base, mask, value) (ENET_WR_TAEM(base, (ENET_RD_TAEM(base) & ~(mask)) | (value)))
+#define ENET_SET_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) |  (value)))
+#define ENET_CLR_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) & ~(value)))
+#define ENET_TOG_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field, and no end-of-frame is
+ * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
+ * stops reading the FIFO and transmits a frame with an MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A minimum value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field. */
+#define ENET_RD_TAEM_TX_ALMOST_EMPTY(base) ((ENET_TAEM_REG(base) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) >> ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)
+#define ENET_BRD_TAEM_TX_ALMOST_EMPTY(base) (ENET_RD_TAEM_TX_ALMOST_EMPTY(base))
+
+/*! @brief Set the TX_ALMOST_EMPTY field to a new value. */
+#define ENET_WR_TAEM_TX_ALMOST_EMPTY(base, value) (ENET_RMW_TAEM(base, ENET_TAEM_TX_ALMOST_EMPTY_MASK, ENET_TAEM_TX_ALMOST_EMPTY(value)))
+#define ENET_BWR_TAEM_TX_ALMOST_EMPTY(base, value) (ENET_WR_TAEM_TX_ALMOST_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TAFL - Transmit FIFO Almost Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000008U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TAFL register
+ */
+/*@{*/
+#define ENET_RD_TAFL(base)       (ENET_TAFL_REG(base))
+#define ENET_WR_TAFL(base, value) (ENET_TAFL_REG(base) = (value))
+#define ENET_RMW_TAFL(base, mask, value) (ENET_WR_TAFL(base, (ENET_RD_TAFL(base) & ~(mask)) | (value)))
+#define ENET_SET_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) |  (value)))
+#define ENET_CLR_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) & ~(value)))
+#define ENET_TOG_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
+ * value of six is required . A recommended value of at least 8 should be set
+ * allowing a latency of two clock cycles to the application. If more latency is
+ * required the value can be increased as necessary (latency = TAFL - 5). When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
+ * application does not react on this signal, the FIFO write control logic, to
+ * avoid FIFO overflow, truncates the current frame and sets the error status. As a
+ * result, the frame will be transmitted with an GMII/MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A FIFO overflow is a fatal error and requires
+ * a global reset on the transmit datapath or at least deassertion of ETHEREN.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field. */
+#define ENET_RD_TAFL_TX_ALMOST_FULL(base) ((ENET_TAFL_REG(base) & ENET_TAFL_TX_ALMOST_FULL_MASK) >> ENET_TAFL_TX_ALMOST_FULL_SHIFT)
+#define ENET_BRD_TAFL_TX_ALMOST_FULL(base) (ENET_RD_TAFL_TX_ALMOST_FULL(base))
+
+/*! @brief Set the TX_ALMOST_FULL field to a new value. */
+#define ENET_WR_TAFL_TX_ALMOST_FULL(base, value) (ENET_RMW_TAFL(base, ENET_TAFL_TX_ALMOST_FULL_MASK, ENET_TAFL_TX_ALMOST_FULL(value)))
+#define ENET_BWR_TAFL_TX_ALMOST_FULL(base, value) (ENET_WR_TAFL_TX_ALMOST_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TIPG - Transmit Inter-Packet Gap
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TIPG - Transmit Inter-Packet Gap (RW)
+ *
+ * Reset value: 0x0000000CU
+ */
+/*!
+ * @name Constants and macros for entire ENET_TIPG register
+ */
+/*@{*/
+#define ENET_RD_TIPG(base)       (ENET_TIPG_REG(base))
+#define ENET_WR_TIPG(base, value) (ENET_TIPG_REG(base) = (value))
+#define ENET_RMW_TIPG(base, mask, value) (ENET_WR_TIPG(base, (ENET_RD_TIPG(base) & ~(mask)) | (value)))
+#define ENET_SET_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) |  (value)))
+#define ENET_CLR_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) & ~(value)))
+#define ENET_TOG_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TIPG bitfields
+ */
+
+/*!
+ * @name Register ENET_TIPG, field IPG[4:0] (RW)
+ *
+ * Indicates the IPG, in bytes, between transmitted frames. Valid values range
+ * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
+ * 27, the IPG is 27.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TIPG_IPG field. */
+#define ENET_RD_TIPG_IPG(base) ((ENET_TIPG_REG(base) & ENET_TIPG_IPG_MASK) >> ENET_TIPG_IPG_SHIFT)
+#define ENET_BRD_TIPG_IPG(base) (ENET_RD_TIPG_IPG(base))
+
+/*! @brief Set the IPG field to a new value. */
+#define ENET_WR_TIPG_IPG(base, value) (ENET_RMW_TIPG(base, ENET_TIPG_IPG_MASK, ENET_TIPG_IPG(value)))
+#define ENET_BWR_TIPG_IPG(base, value) (ENET_WR_TIPG_IPG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_FTRL - Frame Truncation Length
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_FTRL - Frame Truncation Length (RW)
+ *
+ * Reset value: 0x000007FFU
+ */
+/*!
+ * @name Constants and macros for entire ENET_FTRL register
+ */
+/*@{*/
+#define ENET_RD_FTRL(base)       (ENET_FTRL_REG(base))
+#define ENET_WR_FTRL(base, value) (ENET_FTRL_REG(base) = (value))
+#define ENET_RMW_FTRL(base, mask, value) (ENET_WR_FTRL(base, (ENET_RD_FTRL(base) & ~(mask)) | (value)))
+#define ENET_SET_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) |  (value)))
+#define ENET_CLR_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) & ~(value)))
+#define ENET_TOG_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_FTRL bitfields
+ */
+
+/*!
+ * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
+ *
+ * Indicates the value a receive frame is truncated, if it is greater than this
+ * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
+ * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
+ * less data, guaranteeing that it never receives more than the set limit.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_FTRL_TRUNC_FL field. */
+#define ENET_RD_FTRL_TRUNC_FL(base) ((ENET_FTRL_REG(base) & ENET_FTRL_TRUNC_FL_MASK) >> ENET_FTRL_TRUNC_FL_SHIFT)
+#define ENET_BRD_FTRL_TRUNC_FL(base) (ENET_RD_FTRL_TRUNC_FL(base))
+
+/*! @brief Set the TRUNC_FL field to a new value. */
+#define ENET_WR_FTRL_TRUNC_FL(base, value) (ENET_RMW_FTRL(base, ENET_FTRL_TRUNC_FL_MASK, ENET_FTRL_TRUNC_FL(value)))
+#define ENET_BWR_FTRL_TRUNC_FL(base, value) (ENET_WR_FTRL_TRUNC_FL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TACC - Transmit Accelerator Function Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TACC - Transmit Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TACC controls accelerator actions when sending frames. The register can be
+ * changed before or after each frame, but it must remain unmodified during frame
+ * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
+ * checksum feature.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TACC register
+ */
+/*@{*/
+#define ENET_RD_TACC(base)       (ENET_TACC_REG(base))
+#define ENET_WR_TACC(base, value) (ENET_TACC_REG(base) = (value))
+#define ENET_RMW_TACC(base, mask, value) (ENET_WR_TACC(base, (ENET_RD_TACC(base) & ~(mask)) | (value)))
+#define ENET_SET_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) |  (value)))
+#define ENET_CLR_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) & ~(value)))
+#define ENET_TOG_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TACC bitfields
+ */
+
+/*!
+ * @name Register ENET_TACC, field SHIFT16[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Indicates to the transmit data FIFO that the written frames contain
+ *     two additional octets before the frame data. This means the actual frame
+ *     begins at bit 16 of the first word written into the FIFO. This function
+ *     allows putting the frame payload on a 32-bit boundary in memory, as the
+ *     14-byte Ethernet header is extended to a 16-byte header.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_SHIFT16 field. */
+#define ENET_RD_TACC_SHIFT16(base) ((ENET_TACC_REG(base) & ENET_TACC_SHIFT16_MASK) >> ENET_TACC_SHIFT16_SHIFT)
+#define ENET_BRD_TACC_SHIFT16(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_SHIFT16_SHIFT))
+
+/*! @brief Set the SHIFT16 field to a new value. */
+#define ENET_WR_TACC_SHIFT16(base, value) (ENET_RMW_TACC(base, ENET_TACC_SHIFT16_MASK, ENET_TACC_SHIFT16(value)))
+#define ENET_BWR_TACC_SHIFT16(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_SHIFT16_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TACC, field IPCHK[3] (RW)
+ *
+ * Enables insertion of IP header checksum.
+ *
+ * Values:
+ * - 0b0 - Checksum is not inserted.
+ * - 0b1 - If an IP frame is transmitted, the checksum is inserted
+ *     automatically. The IP header checksum field must be cleared. If a non-IP frame is
+ *     transmitted the frame is not modified.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_IPCHK field. */
+#define ENET_RD_TACC_IPCHK(base) ((ENET_TACC_REG(base) & ENET_TACC_IPCHK_MASK) >> ENET_TACC_IPCHK_SHIFT)
+#define ENET_BRD_TACC_IPCHK(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_IPCHK_SHIFT))
+
+/*! @brief Set the IPCHK field to a new value. */
+#define ENET_WR_TACC_IPCHK(base, value) (ENET_RMW_TACC(base, ENET_TACC_IPCHK_MASK, ENET_TACC_IPCHK(value)))
+#define ENET_BWR_TACC_IPCHK(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_IPCHK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TACC, field PROCHK[4] (RW)
+ *
+ * Enables insertion of protocol checksum.
+ *
+ * Values:
+ * - 0b0 - Checksum not inserted.
+ * - 0b1 - If an IP frame with a known protocol is transmitted, the checksum is
+ *     inserted automatically into the frame. The checksum field must be cleared.
+ *     The other frames are not modified.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_PROCHK field. */
+#define ENET_RD_TACC_PROCHK(base) ((ENET_TACC_REG(base) & ENET_TACC_PROCHK_MASK) >> ENET_TACC_PROCHK_SHIFT)
+#define ENET_BRD_TACC_PROCHK(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_PROCHK_SHIFT))
+
+/*! @brief Set the PROCHK field to a new value. */
+#define ENET_WR_TACC_PROCHK(base, value) (ENET_RMW_TACC(base, ENET_TACC_PROCHK_MASK, ENET_TACC_PROCHK(value)))
+#define ENET_BWR_TACC_PROCHK(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_PROCHK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RACC - Receive Accelerator Function Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RACC - Receive Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RACC register
+ */
+/*@{*/
+#define ENET_RD_RACC(base)       (ENET_RACC_REG(base))
+#define ENET_WR_RACC(base, value) (ENET_RACC_REG(base) = (value))
+#define ENET_RMW_RACC(base, mask, value) (ENET_WR_RACC(base, (ENET_RD_RACC(base) & ~(mask)) | (value)))
+#define ENET_SET_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) |  (value)))
+#define ENET_CLR_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) & ~(value)))
+#define ENET_TOG_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RACC bitfields
+ */
+
+/*!
+ * @name Register ENET_RACC, field PADREM[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Padding not removed.
+ * - 0b1 - Any bytes following the IP payload section of the frame are removed
+ *     from the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_PADREM field. */
+#define ENET_RD_RACC_PADREM(base) ((ENET_RACC_REG(base) & ENET_RACC_PADREM_MASK) >> ENET_RACC_PADREM_SHIFT)
+#define ENET_BRD_RACC_PADREM(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PADREM_SHIFT))
+
+/*! @brief Set the PADREM field to a new value. */
+#define ENET_WR_RACC_PADREM(base, value) (ENET_RMW_RACC(base, ENET_RACC_PADREM_MASK, ENET_RACC_PADREM(value)))
+#define ENET_BWR_RACC_PADREM(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PADREM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field IPDIS[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with wrong IPv4 header checksum are not discarded.
+ * - 0b1 - If an IPv4 frame is received with a mismatching header checksum, the
+ *     frame is discarded. IPv6 has no header checksum and is not affected by
+ *     this setting. Discarding is only available when the RX FIFO operates in store
+ *     and forward mode (RSFL cleared).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_IPDIS field. */
+#define ENET_RD_RACC_IPDIS(base) ((ENET_RACC_REG(base) & ENET_RACC_IPDIS_MASK) >> ENET_RACC_IPDIS_SHIFT)
+#define ENET_BRD_RACC_IPDIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_IPDIS_SHIFT))
+
+/*! @brief Set the IPDIS field to a new value. */
+#define ENET_WR_RACC_IPDIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_IPDIS_MASK, ENET_RACC_IPDIS(value)))
+#define ENET_BWR_RACC_IPDIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_IPDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field PRODIS[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with wrong checksum are not discarded.
+ * - 0b1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong
+ *     TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only
+ *     available when the RX FIFO operates in store and forward mode (RSFL cleared).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_PRODIS field. */
+#define ENET_RD_RACC_PRODIS(base) ((ENET_RACC_REG(base) & ENET_RACC_PRODIS_MASK) >> ENET_RACC_PRODIS_SHIFT)
+#define ENET_BRD_RACC_PRODIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PRODIS_SHIFT))
+
+/*! @brief Set the PRODIS field to a new value. */
+#define ENET_WR_RACC_PRODIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_PRODIS_MASK, ENET_RACC_PRODIS(value)))
+#define ENET_BWR_RACC_PRODIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PRODIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field LINEDIS[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with errors are not discarded.
+ * - 0b1 - Any frame received with a CRC, length, or PHY error is automatically
+ *     discarded and not forwarded to the user application interface.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_LINEDIS field. */
+#define ENET_RD_RACC_LINEDIS(base) ((ENET_RACC_REG(base) & ENET_RACC_LINEDIS_MASK) >> ENET_RACC_LINEDIS_SHIFT)
+#define ENET_BRD_RACC_LINEDIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_LINEDIS_SHIFT))
+
+/*! @brief Set the LINEDIS field to a new value. */
+#define ENET_WR_RACC_LINEDIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_LINEDIS_MASK, ENET_RACC_LINEDIS(value)))
+#define ENET_BWR_RACC_LINEDIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_LINEDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field SHIFT16[7] (RW)
+ *
+ * When this field is set, the actual frame data starts at bit 16 of the first
+ * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
+ * This function only affects the FIFO storage and has no influence on the
+ * statistics, which use the actual length of the frame received.
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Instructs the MAC to write two additional bytes in front of each
+ *     frame received into the RX FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_SHIFT16 field. */
+#define ENET_RD_RACC_SHIFT16(base) ((ENET_RACC_REG(base) & ENET_RACC_SHIFT16_MASK) >> ENET_RACC_SHIFT16_SHIFT)
+#define ENET_BRD_RACC_SHIFT16(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_SHIFT16_SHIFT))
+
+/*! @brief Set the SHIFT16 field to a new value. */
+#define ENET_WR_RACC_SHIFT16(base, value) (ENET_RMW_RACC(base, ENET_RACC_SHIFT16_MASK, ENET_RACC_SHIFT16(value)))
+#define ENET_BWR_RACC_SHIFT16(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_SHIFT16_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_PACKETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_PACKETS(base) (ENET_RMON_T_PACKETS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field. */
+#define ENET_RD_RMON_T_PACKETS_TXPKTS(base) ((ENET_RMON_T_PACKETS_REG(base) & ENET_RMON_T_PACKETS_TXPKTS_MASK) >> ENET_RMON_T_PACKETS_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_PACKETS_TXPKTS(base) (ENET_RD_RMON_T_PACKETS_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RMON Tx Broadcast Packets
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_BC_PKT(base) (ENET_RMON_T_BC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field. */
+#define ENET_RD_RMON_T_BC_PKT_TXPKTS(base) ((ENET_RMON_T_BC_PKT_REG(base) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) >> ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_BC_PKT_TXPKTS(base) (ENET_RD_RMON_T_BC_PKT_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_MC_PKT(base) (ENET_RMON_T_MC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field. */
+#define ENET_RD_RMON_T_MC_PKT_TXPKTS(base) ((ENET_RMON_T_MC_PKT_REG(base) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) >> ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_MC_PKT_TXPKTS(base) (ENET_RD_RMON_T_MC_PKT_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_CRC_ALIGN(base) (ENET_RMON_T_CRC_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field. */
+#define ENET_RD_RMON_T_CRC_ALIGN_TXPKTS(base) ((ENET_RMON_T_CRC_ALIGN_REG(base) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) >> ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_CRC_ALIGN_TXPKTS(base) (ENET_RD_RMON_T_CRC_ALIGN_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_UNDERSIZE(base) (ENET_RMON_T_UNDERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field. */
+#define ENET_RD_RMON_T_UNDERSIZE_TXPKTS(base) ((ENET_RMON_T_UNDERSIZE_REG(base) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) >> ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_UNDERSIZE_TXPKTS(base) (ENET_RD_RMON_T_UNDERSIZE_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_OVERSIZE(base) (ENET_RMON_T_OVERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field. */
+#define ENET_RD_RMON_T_OVERSIZE_TXPKTS(base) ((ENET_RMON_T_OVERSIZE_REG(base) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) >> ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_OVERSIZE_TXPKTS(base) (ENET_RD_RMON_T_OVERSIZE_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_FRAG register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_FRAG(base) (ENET_RMON_T_FRAG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field. */
+#define ENET_RD_RMON_T_FRAG_TXPKTS(base) ((ENET_RMON_T_FRAG_REG(base) & ENET_RMON_T_FRAG_TXPKTS_MASK) >> ENET_RMON_T_FRAG_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_FRAG_TXPKTS(base) (ENET_RD_RMON_T_FRAG_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_JAB register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_JAB(base) (ENET_RMON_T_JAB_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field. */
+#define ENET_RD_RMON_T_JAB_TXPKTS(base) ((ENET_RMON_T_JAB_REG(base) & ENET_RMON_T_JAB_TXPKTS_MASK) >> ENET_RMON_T_JAB_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_JAB_TXPKTS(base) (ENET_RD_RMON_T_JAB_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_COL register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_COL(base) (ENET_RMON_T_COL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_COL bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field. */
+#define ENET_RD_RMON_T_COL_TXPKTS(base) ((ENET_RMON_T_COL_REG(base) & ENET_RMON_T_COL_TXPKTS_MASK) >> ENET_RMON_T_COL_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_COL_TXPKTS(base) (ENET_RD_RMON_T_COL_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P64 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P64(base) (ENET_RMON_T_P64_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field. */
+#define ENET_RD_RMON_T_P64_TXPKTS(base) ((ENET_RMON_T_P64_REG(base) & ENET_RMON_T_P64_TXPKTS_MASK) >> ENET_RMON_T_P64_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P64_TXPKTS(base) (ENET_RD_RMON_T_P64_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P65TO127(base) (ENET_RMON_T_P65TO127_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field. */
+#define ENET_RD_RMON_T_P65TO127_TXPKTS(base) ((ENET_RMON_T_P65TO127_REG(base) & ENET_RMON_T_P65TO127_TXPKTS_MASK) >> ENET_RMON_T_P65TO127_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P65TO127_TXPKTS(base) (ENET_RD_RMON_T_P65TO127_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P128TO255(base) (ENET_RMON_T_P128TO255_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field. */
+#define ENET_RD_RMON_T_P128TO255_TXPKTS(base) ((ENET_RMON_T_P128TO255_REG(base) & ENET_RMON_T_P128TO255_TXPKTS_MASK) >> ENET_RMON_T_P128TO255_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P128TO255_TXPKTS(base) (ENET_RD_RMON_T_P128TO255_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P256TO511(base) (ENET_RMON_T_P256TO511_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field. */
+#define ENET_RD_RMON_T_P256TO511_TXPKTS(base) ((ENET_RMON_T_P256TO511_REG(base) & ENET_RMON_T_P256TO511_TXPKTS_MASK) >> ENET_RMON_T_P256TO511_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P256TO511_TXPKTS(base) (ENET_RD_RMON_T_P256TO511_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P512TO1023(base) (ENET_RMON_T_P512TO1023_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field. */
+#define ENET_RD_RMON_T_P512TO1023_TXPKTS(base) ((ENET_RMON_T_P512TO1023_REG(base) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) >> ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P512TO1023_TXPKTS(base) (ENET_RD_RMON_T_P512TO1023_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P1024TO2047(base) (ENET_RMON_T_P1024TO2047_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field. */
+#define ENET_RD_RMON_T_P1024TO2047_TXPKTS(base) ((ENET_RMON_T_P1024TO2047_REG(base) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) >> ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P1024TO2047_TXPKTS(base) (ENET_RD_RMON_T_P1024TO2047_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P_GTE2048(base) (ENET_RMON_T_P_GTE2048_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field. */
+#define ENET_RD_RMON_T_P_GTE2048_TXPKTS(base) ((ENET_RMON_T_P_GTE2048_REG(base) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) >> ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P_GTE2048_TXPKTS(base) (ENET_RD_RMON_T_P_GTE2048_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OCTETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_OCTETS(base) (ENET_RMON_T_OCTETS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_FRAME_OK(base) (ENET_IEEE_T_FRAME_OK_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field. */
+#define ENET_RD_IEEE_T_FRAME_OK_COUNT(base) ((ENET_IEEE_T_FRAME_OK_REG(base) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) >> ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_FRAME_OK_COUNT(base) (ENET_RD_IEEE_T_FRAME_OK_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_1COL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_1COL(base) (ENET_IEEE_T_1COL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_1COL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field. */
+#define ENET_RD_IEEE_T_1COL_COUNT(base) ((ENET_IEEE_T_1COL_REG(base) & ENET_IEEE_T_1COL_COUNT_MASK) >> ENET_IEEE_T_1COL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_1COL_COUNT(base) (ENET_RD_IEEE_T_1COL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_MCOL(base) (ENET_IEEE_T_MCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field. */
+#define ENET_RD_IEEE_T_MCOL_COUNT(base) ((ENET_IEEE_T_MCOL_REG(base) & ENET_IEEE_T_MCOL_COUNT_MASK) >> ENET_IEEE_T_MCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_MCOL_COUNT(base) (ENET_RD_IEEE_T_MCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_DEF register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_DEF(base) (ENET_IEEE_T_DEF_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_DEF bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field. */
+#define ENET_RD_IEEE_T_DEF_COUNT(base) ((ENET_IEEE_T_DEF_REG(base) & ENET_IEEE_T_DEF_COUNT_MASK) >> ENET_IEEE_T_DEF_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_DEF_COUNT(base) (ENET_RD_IEEE_T_DEF_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_LCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_LCOL(base) (ENET_IEEE_T_LCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field. */
+#define ENET_RD_IEEE_T_LCOL_COUNT(base) ((ENET_IEEE_T_LCOL_REG(base) & ENET_IEEE_T_LCOL_COUNT_MASK) >> ENET_IEEE_T_LCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_LCOL_COUNT(base) (ENET_RD_IEEE_T_LCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_EXCOL(base) (ENET_IEEE_T_EXCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field. */
+#define ENET_RD_IEEE_T_EXCOL_COUNT(base) ((ENET_IEEE_T_EXCOL_REG(base) & ENET_IEEE_T_EXCOL_COUNT_MASK) >> ENET_IEEE_T_EXCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_EXCOL_COUNT(base) (ENET_RD_IEEE_T_EXCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MACERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_MACERR(base) (ENET_IEEE_T_MACERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field. */
+#define ENET_RD_IEEE_T_MACERR_COUNT(base) ((ENET_IEEE_T_MACERR_REG(base) & ENET_IEEE_T_MACERR_COUNT_MASK) >> ENET_IEEE_T_MACERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_MACERR_COUNT(base) (ENET_RD_IEEE_T_MACERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_CSERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_CSERR(base) (ENET_IEEE_T_CSERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field. */
+#define ENET_RD_IEEE_T_CSERR_COUNT(base) ((ENET_IEEE_T_CSERR_REG(base) & ENET_IEEE_T_CSERR_COUNT_MASK) >> ENET_IEEE_T_CSERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_CSERR_COUNT(base) (ENET_RD_IEEE_T_CSERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_FDXFC(base) (ENET_IEEE_T_FDXFC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field. */
+#define ENET_RD_IEEE_T_FDXFC_COUNT(base) ((ENET_IEEE_T_FDXFC_REG(base) & ENET_IEEE_T_FDXFC_COUNT_MASK) >> ENET_IEEE_T_FDXFC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_FDXFC_COUNT(base) (ENET_RD_IEEE_T_FDXFC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counts total octets (includes header and FCS fields).
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_OCTETS_OK(base) (ENET_IEEE_T_OCTETS_OK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_PACKETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_PACKETS(base) (ENET_RMON_R_PACKETS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field. */
+#define ENET_RD_RMON_R_PACKETS_COUNT(base) ((ENET_RMON_R_PACKETS_REG(base) & ENET_RMON_R_PACKETS_COUNT_MASK) >> ENET_RMON_R_PACKETS_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_PACKETS_COUNT(base) (ENET_RD_RMON_R_PACKETS_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_BC_PKT(base) (ENET_RMON_R_BC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field. */
+#define ENET_RD_RMON_R_BC_PKT_COUNT(base) ((ENET_RMON_R_BC_PKT_REG(base) & ENET_RMON_R_BC_PKT_COUNT_MASK) >> ENET_RMON_R_BC_PKT_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_BC_PKT_COUNT(base) (ENET_RD_RMON_R_BC_PKT_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_MC_PKT(base) (ENET_RMON_R_MC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field. */
+#define ENET_RD_RMON_R_MC_PKT_COUNT(base) ((ENET_RMON_R_MC_PKT_REG(base) & ENET_RMON_R_MC_PKT_COUNT_MASK) >> ENET_RMON_R_MC_PKT_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_MC_PKT_COUNT(base) (ENET_RD_RMON_R_MC_PKT_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_CRC_ALIGN(base) (ENET_RMON_R_CRC_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field. */
+#define ENET_RD_RMON_R_CRC_ALIGN_COUNT(base) ((ENET_RMON_R_CRC_ALIGN_REG(base) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) >> ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_CRC_ALIGN_COUNT(base) (ENET_RD_RMON_R_CRC_ALIGN_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_UNDERSIZE(base) (ENET_RMON_R_UNDERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field. */
+#define ENET_RD_RMON_R_UNDERSIZE_COUNT(base) ((ENET_RMON_R_UNDERSIZE_REG(base) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) >> ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_UNDERSIZE_COUNT(base) (ENET_RD_RMON_R_UNDERSIZE_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_OVERSIZE(base) (ENET_RMON_R_OVERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field. */
+#define ENET_RD_RMON_R_OVERSIZE_COUNT(base) ((ENET_RMON_R_OVERSIZE_REG(base) & ENET_RMON_R_OVERSIZE_COUNT_MASK) >> ENET_RMON_R_OVERSIZE_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_OVERSIZE_COUNT(base) (ENET_RD_RMON_R_OVERSIZE_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_FRAG register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_FRAG(base) (ENET_RMON_R_FRAG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field. */
+#define ENET_RD_RMON_R_FRAG_COUNT(base) ((ENET_RMON_R_FRAG_REG(base) & ENET_RMON_R_FRAG_COUNT_MASK) >> ENET_RMON_R_FRAG_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_FRAG_COUNT(base) (ENET_RD_RMON_R_FRAG_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_JAB register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_JAB(base) (ENET_RMON_R_JAB_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_JAB_COUNT field. */
+#define ENET_RD_RMON_R_JAB_COUNT(base) ((ENET_RMON_R_JAB_REG(base) & ENET_RMON_R_JAB_COUNT_MASK) >> ENET_RMON_R_JAB_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_JAB_COUNT(base) (ENET_RD_RMON_R_JAB_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P64 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P64(base) (ENET_RMON_R_P64_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P64_COUNT field. */
+#define ENET_RD_RMON_R_P64_COUNT(base) ((ENET_RMON_R_P64_REG(base) & ENET_RMON_R_P64_COUNT_MASK) >> ENET_RMON_R_P64_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P64_COUNT(base) (ENET_RD_RMON_R_P64_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P65TO127(base) (ENET_RMON_R_P65TO127_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field. */
+#define ENET_RD_RMON_R_P65TO127_COUNT(base) ((ENET_RMON_R_P65TO127_REG(base) & ENET_RMON_R_P65TO127_COUNT_MASK) >> ENET_RMON_R_P65TO127_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P65TO127_COUNT(base) (ENET_RD_RMON_R_P65TO127_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P128TO255(base) (ENET_RMON_R_P128TO255_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field. */
+#define ENET_RD_RMON_R_P128TO255_COUNT(base) ((ENET_RMON_R_P128TO255_REG(base) & ENET_RMON_R_P128TO255_COUNT_MASK) >> ENET_RMON_R_P128TO255_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P128TO255_COUNT(base) (ENET_RD_RMON_R_P128TO255_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P256TO511(base) (ENET_RMON_R_P256TO511_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field. */
+#define ENET_RD_RMON_R_P256TO511_COUNT(base) ((ENET_RMON_R_P256TO511_REG(base) & ENET_RMON_R_P256TO511_COUNT_MASK) >> ENET_RMON_R_P256TO511_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P256TO511_COUNT(base) (ENET_RD_RMON_R_P256TO511_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P512TO1023(base) (ENET_RMON_R_P512TO1023_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field. */
+#define ENET_RD_RMON_R_P512TO1023_COUNT(base) ((ENET_RMON_R_P512TO1023_REG(base) & ENET_RMON_R_P512TO1023_COUNT_MASK) >> ENET_RMON_R_P512TO1023_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P512TO1023_COUNT(base) (ENET_RD_RMON_R_P512TO1023_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P1024TO2047(base) (ENET_RMON_R_P1024TO2047_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field. */
+#define ENET_RD_RMON_R_P1024TO2047_COUNT(base) ((ENET_RMON_R_P1024TO2047_REG(base) & ENET_RMON_R_P1024TO2047_COUNT_MASK) >> ENET_RMON_R_P1024TO2047_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P1024TO2047_COUNT(base) (ENET_RD_RMON_R_P1024TO2047_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P_GTE2048 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P_GTE2048(base) (ENET_RMON_R_P_GTE2048_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P_GTE2048, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P_GTE2048_COUNT field. */
+#define ENET_RD_RMON_R_P_GTE2048_COUNT(base) ((ENET_RMON_R_P_GTE2048_REG(base) & ENET_RMON_R_P_GTE2048_COUNT_MASK) >> ENET_RMON_R_P_GTE2048_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P_GTE2048_COUNT(base) (ENET_RD_RMON_R_P_GTE2048_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OCTETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_OCTETS(base) (ENET_RMON_R_OCTETS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counter increments if a frame with invalid or missing SFD character is
+ * detected and has been dropped. None of the other counters increments if this counter
+ * increments.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_DROP register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_DROP(base) (ENET_IEEE_R_DROP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_DROP bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field. */
+#define ENET_RD_IEEE_R_DROP_COUNT(base) ((ENET_IEEE_R_DROP_REG(base) & ENET_IEEE_R_DROP_COUNT_MASK) >> ENET_IEEE_R_DROP_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_DROP_COUNT(base) (ENET_RD_IEEE_R_DROP_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_FRAME_OK(base) (ENET_IEEE_R_FRAME_OK_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field. */
+#define ENET_RD_IEEE_R_FRAME_OK_COUNT(base) ((ENET_IEEE_R_FRAME_OK_REG(base) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) >> ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_FRAME_OK_COUNT(base) (ENET_RD_IEEE_R_FRAME_OK_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_CRC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_CRC(base) (ENET_IEEE_R_CRC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_CRC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field. */
+#define ENET_RD_IEEE_R_CRC_COUNT(base) ((ENET_IEEE_R_CRC_REG(base) & ENET_IEEE_R_CRC_COUNT_MASK) >> ENET_IEEE_R_CRC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_CRC_COUNT(base) (ENET_RD_IEEE_R_CRC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_ALIGN(base) (ENET_IEEE_R_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field. */
+#define ENET_RD_IEEE_R_ALIGN_COUNT(base) ((ENET_IEEE_R_ALIGN_REG(base) & ENET_IEEE_R_ALIGN_COUNT_MASK) >> ENET_IEEE_R_ALIGN_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_ALIGN_COUNT(base) (ENET_RD_IEEE_R_ALIGN_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_MACERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_MACERR(base) (ENET_IEEE_R_MACERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field. */
+#define ENET_RD_IEEE_R_MACERR_COUNT(base) ((ENET_IEEE_R_MACERR_REG(base) & ENET_IEEE_R_MACERR_COUNT_MASK) >> ENET_IEEE_R_MACERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_MACERR_COUNT(base) (ENET_RD_IEEE_R_MACERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_FDXFC(base) (ENET_IEEE_R_FDXFC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field. */
+#define ENET_RD_IEEE_R_FDXFC_COUNT(base) ((ENET_IEEE_R_FDXFC_REG(base) & ENET_IEEE_R_FDXFC_COUNT_MASK) >> ENET_IEEE_R_FDXFC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_FDXFC_COUNT(base) (ENET_RD_IEEE_R_FDXFC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_OCTETS_OK(base) (ENET_IEEE_R_OCTETS_OK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATCR - Adjustable Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATCR - Adjustable Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * ATCR command fields can trigger the corresponding events directly. It is not
+ * necessary to preserve any of the configuration fields when a command field is
+ * set in the register, that is, no read-modify-write is required. The fields are
+ * automatically cleared after the command completes.
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATCR register
+ */
+/*@{*/
+#define ENET_RD_ATCR(base)       (ENET_ATCR_REG(base))
+#define ENET_WR_ATCR(base, value) (ENET_ATCR_REG(base) = (value))
+#define ENET_RMW_ATCR(base, mask, value) (ENET_WR_ATCR(base, (ENET_RD_ATCR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) |  (value)))
+#define ENET_CLR_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) & ~(value)))
+#define ENET_TOG_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATCR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCR, field EN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer stops at the current value.
+ * - 0b1 - The timer starts incrementing.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_EN field. */
+#define ENET_RD_ATCR_EN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_EN_MASK) >> ENET_ATCR_EN_SHIFT)
+#define ENET_BRD_ATCR_EN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_EN_SHIFT))
+
+/*! @brief Set the EN field to a new value. */
+#define ENET_WR_ATCR_EN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_EN_MASK, ENET_ATCR_EN(value)))
+#define ENET_BWR_ATCR_EN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field OFFEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - The timer can be reset to zero when the given offset time is reached
+ *     (offset event). The field is cleared when the offset event is reached, so
+ *     no further event occurs until the field is set again. The timer offset
+ *     value must be set before setting this field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_OFFEN field. */
+#define ENET_RD_ATCR_OFFEN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_OFFEN_MASK) >> ENET_ATCR_OFFEN_SHIFT)
+#define ENET_BRD_ATCR_OFFEN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFEN_SHIFT))
+
+/*! @brief Set the OFFEN field to a new value. */
+#define ENET_WR_ATCR_OFFEN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_OFFEN_MASK, ENET_ATCR_OFFEN(value)))
+#define ENET_BWR_ATCR_OFFEN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field OFFRST[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer is not affected and no action occurs, besides clearing
+ *     OFFEN, when the offset is reached.
+ * - 0b1 - If OFFEN is set, the timer resets to zero when the offset setting is
+ *     reached. The offset event does not cause a timer interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_OFFRST field. */
+#define ENET_RD_ATCR_OFFRST(base) ((ENET_ATCR_REG(base) & ENET_ATCR_OFFRST_MASK) >> ENET_ATCR_OFFRST_SHIFT)
+#define ENET_BRD_ATCR_OFFRST(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFRST_SHIFT))
+
+/*! @brief Set the OFFRST field to a new value. */
+#define ENET_WR_ATCR_OFFRST(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_OFFRST_MASK, ENET_ATCR_OFFRST(value)))
+#define ENET_BWR_ATCR_OFFRST(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field PEREN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the
+ *     event signal output is asserted when the timer wraps around according to the
+ *     periodic setting ATPER. The timer period value must be set before setting
+ *     this bit. Not all devices contain the event signal output. See the chip
+ *     configuration details.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_PEREN field. */
+#define ENET_RD_ATCR_PEREN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_PEREN_MASK) >> ENET_ATCR_PEREN_SHIFT)
+#define ENET_BRD_ATCR_PEREN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PEREN_SHIFT))
+
+/*! @brief Set the PEREN field to a new value. */
+#define ENET_WR_ATCR_PEREN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_PEREN_MASK, ENET_ATCR_PEREN(value)))
+#define ENET_BWR_ATCR_PEREN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field PINPER[7] (RW)
+ *
+ * Enables event signal output assertion on period event. Not all devices
+ * contain the event signal output. See the chip configuration details.
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - Enable.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_PINPER field. */
+#define ENET_RD_ATCR_PINPER(base) ((ENET_ATCR_REG(base) & ENET_ATCR_PINPER_MASK) >> ENET_ATCR_PINPER_SHIFT)
+#define ENET_BRD_ATCR_PINPER(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PINPER_SHIFT))
+
+/*! @brief Set the PINPER field to a new value. */
+#define ENET_WR_ATCR_PINPER(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_PINPER_MASK, ENET_ATCR_PINPER(value)))
+#define ENET_BWR_ATCR_PINPER(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PINPER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field RESTART[9] (RW)
+ *
+ * Resets the timer to zero. This has no effect on the counter enable. If the
+ * counter is enabled when this field is set, the timer is reset to zero and starts
+ * counting from there. When set, all other fields are ignored during a write.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_RESTART field. */
+#define ENET_RD_ATCR_RESTART(base) ((ENET_ATCR_REG(base) & ENET_ATCR_RESTART_MASK) >> ENET_ATCR_RESTART_SHIFT)
+#define ENET_BRD_ATCR_RESTART(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_RESTART_SHIFT))
+
+/*! @brief Set the RESTART field to a new value. */
+#define ENET_WR_ATCR_RESTART(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_RESTART_MASK, ENET_ATCR_RESTART(value)))
+#define ENET_BWR_ATCR_RESTART(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_RESTART_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field CAPTURE[11] (RW)
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - The current time is captured and can be read from the ATVR register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_CAPTURE field. */
+#define ENET_RD_ATCR_CAPTURE(base) ((ENET_ATCR_REG(base) & ENET_ATCR_CAPTURE_MASK) >> ENET_ATCR_CAPTURE_SHIFT)
+#define ENET_BRD_ATCR_CAPTURE(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_CAPTURE_SHIFT))
+
+/*! @brief Set the CAPTURE field to a new value. */
+#define ENET_WR_ATCR_CAPTURE(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_CAPTURE_MASK, ENET_ATCR_CAPTURE(value)))
+#define ENET_BWR_ATCR_CAPTURE(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_CAPTURE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field SLAVE[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer is active and all configuration fields in this register are
+ *     relevant.
+ * - 0b1 - The internal timer is disabled and the externally provided timer
+ *     value is used. All other fields, except CAPTURE, in this register have no
+ *     effect. CAPTURE can still be used to capture the current timer value.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_SLAVE field. */
+#define ENET_RD_ATCR_SLAVE(base) ((ENET_ATCR_REG(base) & ENET_ATCR_SLAVE_MASK) >> ENET_ATCR_SLAVE_SHIFT)
+#define ENET_BRD_ATCR_SLAVE(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_SLAVE_SHIFT))
+
+/*! @brief Set the SLAVE field to a new value. */
+#define ENET_WR_ATCR_SLAVE(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_SLAVE_MASK, ENET_ATCR_SLAVE(value)))
+#define ENET_BWR_ATCR_SLAVE(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_SLAVE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATVR - Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATVR - Timer Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATVR register
+ */
+/*@{*/
+#define ENET_RD_ATVR(base)       (ENET_ATVR_REG(base))
+#define ENET_WR_ATVR(base, value) (ENET_ATVR_REG(base) = (value))
+#define ENET_RMW_ATVR(base, mask, value) (ENET_WR_ATVR(base, (ENET_RD_ATVR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) |  (value)))
+#define ENET_CLR_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) & ~(value)))
+#define ENET_TOG_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATOFF - Timer Offset Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATOFF - Timer Offset Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATOFF register
+ */
+/*@{*/
+#define ENET_RD_ATOFF(base)      (ENET_ATOFF_REG(base))
+#define ENET_WR_ATOFF(base, value) (ENET_ATOFF_REG(base) = (value))
+#define ENET_RMW_ATOFF(base, mask, value) (ENET_WR_ATOFF(base, (ENET_RD_ATOFF(base) & ~(mask)) | (value)))
+#define ENET_SET_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) |  (value)))
+#define ENET_CLR_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) & ~(value)))
+#define ENET_TOG_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATPER - Timer Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATPER - Timer Period Register (RW)
+ *
+ * Reset value: 0x3B9ACA00U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATPER register
+ */
+/*@{*/
+#define ENET_RD_ATPER(base)      (ENET_ATPER_REG(base))
+#define ENET_WR_ATPER(base, value) (ENET_ATPER_REG(base) = (value))
+#define ENET_RMW_ATPER(base, mask, value) (ENET_WR_ATPER(base, (ENET_RD_ATPER(base) & ~(mask)) | (value)))
+#define ENET_SET_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) |  (value)))
+#define ENET_CLR_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) & ~(value)))
+#define ENET_TOG_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATCOR - Timer Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATCOR - Timer Correction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATCOR register
+ */
+/*@{*/
+#define ENET_RD_ATCOR(base)      (ENET_ATCOR_REG(base))
+#define ENET_WR_ATCOR(base, value) (ENET_ATCOR_REG(base) = (value))
+#define ENET_RMW_ATCOR(base, mask, value) (ENET_WR_ATCOR(base, (ENET_RD_ATCOR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) |  (value)))
+#define ENET_CLR_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) & ~(value)))
+#define ENET_TOG_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATCOR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCOR, field COR[30:0] (RW)
+ *
+ * Defines after how many timer clock cycles (ts_clk) the correction counter
+ * should be reset and trigger a correction increment on the timer. The amount of
+ * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
+ * counter and no corrections occur. This value is given in clock cycles, not in
+ * nanoseconds as all other values.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCOR_COR field. */
+#define ENET_RD_ATCOR_COR(base) ((ENET_ATCOR_REG(base) & ENET_ATCOR_COR_MASK) >> ENET_ATCOR_COR_SHIFT)
+#define ENET_BRD_ATCOR_COR(base) (ENET_RD_ATCOR_COR(base))
+
+/*! @brief Set the COR field to a new value. */
+#define ENET_WR_ATCOR_COR(base, value) (ENET_RMW_ATCOR(base, ENET_ATCOR_COR_MASK, ENET_ATCOR_COR(value)))
+#define ENET_BWR_ATCOR_COR(base, value) (ENET_WR_ATCOR_COR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATINC - Time-Stamping Clock Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATINC - Time-Stamping Clock Period Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATINC register
+ */
+/*@{*/
+#define ENET_RD_ATINC(base)      (ENET_ATINC_REG(base))
+#define ENET_WR_ATINC(base, value) (ENET_ATINC_REG(base) = (value))
+#define ENET_RMW_ATINC(base, mask, value) (ENET_WR_ATINC(base, (ENET_RD_ATINC(base) & ~(mask)) | (value)))
+#define ENET_SET_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) |  (value)))
+#define ENET_CLR_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) & ~(value)))
+#define ENET_TOG_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATINC bitfields
+ */
+
+/*!
+ * @name Register ENET_ATINC, field INC[6:0] (RW)
+ *
+ * The timer increments by this amount each clock cycle. For example, set to 10
+ * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
+ * that is an integer fraction of the period set in ATPER.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATINC_INC field. */
+#define ENET_RD_ATINC_INC(base) ((ENET_ATINC_REG(base) & ENET_ATINC_INC_MASK) >> ENET_ATINC_INC_SHIFT)
+#define ENET_BRD_ATINC_INC(base) (ENET_RD_ATINC_INC(base))
+
+/*! @brief Set the INC field to a new value. */
+#define ENET_WR_ATINC_INC(base, value) (ENET_RMW_ATINC(base, ENET_ATINC_INC_MASK, ENET_ATINC_INC(value)))
+#define ENET_BWR_ATINC_INC(base, value) (ENET_WR_ATINC_INC(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
+ *
+ * This value is added every time the correction timer expires (every clock
+ * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
+ * than INC speeds up the timer.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATINC_INC_CORR field. */
+#define ENET_RD_ATINC_INC_CORR(base) ((ENET_ATINC_REG(base) & ENET_ATINC_INC_CORR_MASK) >> ENET_ATINC_INC_CORR_SHIFT)
+#define ENET_BRD_ATINC_INC_CORR(base) (ENET_RD_ATINC_INC_CORR(base))
+
+/*! @brief Set the INC_CORR field to a new value. */
+#define ENET_WR_ATINC_INC_CORR(base, value) (ENET_RMW_ATINC(base, ENET_ATINC_INC_CORR_MASK, ENET_ATINC_INC_CORR(value)))
+#define ENET_BWR_ATINC_INC_CORR(base, value) (ENET_WR_ATINC_INC_CORR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATSTMP register
+ */
+/*@{*/
+#define ENET_RD_ATSTMP(base)     (ENET_ATSTMP_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TGSR - Timer Global Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TGSR - Timer Global Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TGSR register
+ */
+/*@{*/
+#define ENET_RD_TGSR(base)       (ENET_TGSR_REG(base))
+#define ENET_WR_TGSR(base, value) (ENET_TGSR_REG(base) = (value))
+#define ENET_RMW_TGSR(base, mask, value) (ENET_WR_TGSR(base, (ENET_RD_TGSR(base) & ~(mask)) | (value)))
+#define ENET_SET_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) |  (value)))
+#define ENET_CLR_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) & ~(value)))
+#define ENET_TOG_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TGSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TGSR, field TF0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 0 is clear
+ * - 0b1 - Timer Flag for Channel 0 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF0 field. */
+#define ENET_RD_TGSR_TF0(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF0_MASK) >> ENET_TGSR_TF0_SHIFT)
+#define ENET_BRD_TGSR_TF0(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF0_SHIFT))
+
+/*! @brief Set the TF0 field to a new value. */
+#define ENET_WR_TGSR_TF0(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF2_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF0(value)))
+#define ENET_BWR_TGSR_TF0(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 1 is clear
+ * - 0b1 - Timer Flag for Channel 1 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF1 field. */
+#define ENET_RD_TGSR_TF1(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF1_MASK) >> ENET_TGSR_TF1_SHIFT)
+#define ENET_BRD_TGSR_TF1(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF1_SHIFT))
+
+/*! @brief Set the TF1 field to a new value. */
+#define ENET_WR_TGSR_TF1(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF1_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF2_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF1(value)))
+#define ENET_BWR_TGSR_TF1(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 2 is clear
+ * - 0b1 - Timer Flag for Channel 2 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF2 field. */
+#define ENET_RD_TGSR_TF2(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF2_MASK) >> ENET_TGSR_TF2_SHIFT)
+#define ENET_BRD_TGSR_TF2(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF2_SHIFT))
+
+/*! @brief Set the TF2 field to a new value. */
+#define ENET_WR_TGSR_TF2(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF2_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF2(value)))
+#define ENET_BWR_TGSR_TF2(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 3 is clear
+ * - 0b1 - Timer Flag for Channel 3 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF3 field. */
+#define ENET_RD_TGSR_TF3(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF3_MASK) >> ENET_TGSR_TF3_SHIFT)
+#define ENET_BRD_TGSR_TF3(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF3_SHIFT))
+
+/*! @brief Set the TF3 field to a new value. */
+#define ENET_WR_TGSR_TF3(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF3_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF2_MASK), ENET_TGSR_TF3(value)))
+#define ENET_BWR_TGSR_TF3(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF3_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCSR - Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCSR - Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCSR register
+ */
+/*@{*/
+#define ENET_RD_TCSR(base, index) (ENET_TCSR_REG(base, index))
+#define ENET_WR_TCSR(base, index, value) (ENET_TCSR_REG(base, index) = (value))
+#define ENET_RMW_TCSR(base, index, mask, value) (ENET_WR_TCSR(base, index, (ENET_RD_TCSR(base, index) & ~(mask)) | (value)))
+#define ENET_SET_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) |  (value)))
+#define ENET_CLR_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) & ~(value)))
+#define ENET_TOG_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TCSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCSR, field TDRE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA request is disabled
+ * - 0b1 - DMA request is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TDRE field. */
+#define ENET_RD_TCSR_TDRE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TDRE_MASK) >> ENET_TCSR_TDRE_SHIFT)
+#define ENET_BRD_TCSR_TDRE(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TDRE_SHIFT))
+
+/*! @brief Set the TDRE field to a new value. */
+#define ENET_WR_TCSR_TDRE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TDRE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TDRE(value)))
+#define ENET_BWR_TCSR_TDRE(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TDRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TMODE[5:2] (RW)
+ *
+ * Updating the Timer Mode field takes a few cycles to register because it is
+ * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
+ * from the 1588 clock domain. When changing Timer Mode, always disable the
+ * channel and read this register to verify the channel is disabled first.
+ *
+ * Values:
+ * - 0b0000 - Timer Channel is disabled.
+ * - 0b0001 - Timer Channel is configured for Input Capture on rising edge
+ * - 0b0010 - Timer Channel is configured for Input Capture on falling edge
+ * - 0b0011 - Timer Channel is configured for Input Capture on both edges
+ * - 0b0100 - Timer Channel is configured for Output Compare - software only
+ * - 0b0101 - Timer Channel is configured for Output Compare - toggle output on
+ *     compare
+ * - 0b0110 - Timer Channel is configured for Output Compare - clear output on
+ *     compare
+ * - 0b0111 - Timer Channel is configured for Output Compare - set output on
+ *     compare
+ * - 0b1000 - Reserved
+ * - 0b1010 - Timer Channel is configured for Output Compare - clear output on
+ *     compare, set output on overflow
+ * - 0b10x1 - Timer Channel is configured for Output Compare - set output on
+ *     compare, clear output on overflow
+ * - 0b1100 - Reserved
+ * - 0b1110 - Timer Channel is configured for Output Compare - pulse output low
+ *     on compare for one 1588 clock cycle
+ * - 0b1111 - Timer Channel is configured for Output Compare - pulse output high
+ *     on compare for one 1588 clock cycle
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TMODE field. */
+#define ENET_RD_TCSR_TMODE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TMODE_MASK) >> ENET_TCSR_TMODE_SHIFT)
+#define ENET_BRD_TCSR_TMODE(base, index) (ENET_RD_TCSR_TMODE(base, index))
+
+/*! @brief Set the TMODE field to a new value. */
+#define ENET_WR_TCSR_TMODE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TMODE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TMODE(value)))
+#define ENET_BWR_TCSR_TMODE(base, index, value) (ENET_WR_TCSR_TMODE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TIE[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled
+ * - 0b1 - Interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TIE field. */
+#define ENET_RD_TCSR_TIE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TIE_MASK) >> ENET_TCSR_TIE_SHIFT)
+#define ENET_BRD_TCSR_TIE(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define ENET_WR_TCSR_TIE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TIE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TIE(value)))
+#define ENET_BWR_TCSR_TIE(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TF[7] (W1C)
+ *
+ * Sets when input capture or output compare occurs. This flag is double
+ * buffered between the module clock and 1588 clock domains. When this field is 1, it
+ * can be cleared to 0 by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - Input Capture or Output Compare has not occurred
+ * - 0b1 - Input Capture or Output Compare has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TF field. */
+#define ENET_RD_TCSR_TF(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TF_MASK) >> ENET_TCSR_TF_SHIFT)
+#define ENET_BRD_TCSR_TF(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TF_SHIFT))
+
+/*! @brief Set the TF field to a new value. */
+#define ENET_WR_TCSR_TF(base, index, value) (ENET_RMW_TCSR(base, index, ENET_TCSR_TF_MASK, ENET_TCSR_TF(value)))
+#define ENET_BWR_TCSR_TF(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCCR - Timer Compare Capture Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCCR - Timer Compare Capture Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCCR register
+ */
+/*@{*/
+#define ENET_RD_TCCR(base, index) (ENET_TCCR_REG(base, index))
+#define ENET_WR_TCCR(base, index, value) (ENET_TCCR_REG(base, index) = (value))
+#define ENET_RMW_TCCR(base, index, mask, value) (ENET_WR_TCCR(base, index, (ENET_RD_TCCR(base, index) & ~(mask)) | (value)))
+#define ENET_SET_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) |  (value)))
+#define ENET_CLR_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) & ~(value)))
+#define ENET_TOG_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 EWM
+ *
+ * External Watchdog Monitor
+ *
+ * Registers defined in this header file:
+ * - EWM_CTRL - Control Register
+ * - EWM_SERV - Service Register
+ * - EWM_CMPL - Compare Low Register
+ * - EWM_CMPH - Compare High Register
+ */
+
+#define EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
+#define EWM_IDX (0U) /*!< Instance number for EWM. */
+
+/*******************************************************************************
+ * EWM_CTRL - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CTRL - Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
+ * written once after a CPU reset. Modifying these bits more than once, generates
+ * a bus transfer error.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CTRL register
+ */
+/*@{*/
+#define EWM_RD_CTRL(base)        (EWM_CTRL_REG(base))
+#define EWM_WR_CTRL(base, value) (EWM_CTRL_REG(base) = (value))
+#define EWM_RMW_CTRL(base, mask, value) (EWM_WR_CTRL(base, (EWM_RD_CTRL(base) & ~(mask)) | (value)))
+#define EWM_SET_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) |  (value)))
+#define EWM_CLR_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) & ~(value)))
+#define EWM_TOG_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual EWM_CTRL bitfields
+ */
+
+/*!
+ * @name Register EWM_CTRL, field EWMEN[0] (RW)
+ *
+ * This bit when set, enables the EWM module. This resets the EWM counter to
+ * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
+ * therefore it cannot be enabled until a reset occurs, due to the write-once
+ * nature of this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_EWMEN field. */
+#define EWM_RD_CTRL_EWMEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_EWMEN_MASK) >> EWM_CTRL_EWMEN_SHIFT)
+#define EWM_BRD_CTRL_EWMEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_EWMEN_SHIFT))
+
+/*! @brief Set the EWMEN field to a new value. */
+#define EWM_WR_CTRL_EWMEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_EWMEN_MASK, EWM_CTRL_EWMEN(value)))
+#define EWM_BWR_CTRL_EWMEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_EWMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field ASSIN[1] (RW)
+ *
+ * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
+ * inverts the assert state to a logic one.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_ASSIN field. */
+#define EWM_RD_CTRL_ASSIN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_ASSIN_MASK) >> EWM_CTRL_ASSIN_SHIFT)
+#define EWM_BRD_CTRL_ASSIN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_ASSIN_SHIFT))
+
+/*! @brief Set the ASSIN field to a new value. */
+#define EWM_WR_CTRL_ASSIN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_ASSIN_MASK, EWM_CTRL_ASSIN(value)))
+#define EWM_BWR_CTRL_ASSIN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_ASSIN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field INEN[2] (RW)
+ *
+ * This bit when set, enables the EWM_in port.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_INEN field. */
+#define EWM_RD_CTRL_INEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_INEN_MASK) >> EWM_CTRL_INEN_SHIFT)
+#define EWM_BRD_CTRL_INEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INEN_SHIFT))
+
+/*! @brief Set the INEN field to a new value. */
+#define EWM_WR_CTRL_INEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_INEN_MASK, EWM_CTRL_INEN(value)))
+#define EWM_BWR_CTRL_INEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field INTEN[3] (RW)
+ *
+ * This bit when set and EWM_out is asserted, an interrupt request is generated.
+ * To de-assert interrupt request, user should clear this bit by writing 0.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_INTEN field. */
+#define EWM_RD_CTRL_INTEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_INTEN_MASK) >> EWM_CTRL_INTEN_SHIFT)
+#define EWM_BRD_CTRL_INTEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INTEN_SHIFT))
+
+/*! @brief Set the INTEN field to a new value. */
+#define EWM_WR_CTRL_INTEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_INTEN_MASK, EWM_CTRL_INTEN(value)))
+#define EWM_BWR_CTRL_INTEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INTEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_SERV - Service Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_SERV - Service Register (WORZ)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERV register provides the interface from the CPU to the EWM module. It
+ * is write-only and reads of this register return zero.
+ */
+/*!
+ * @name Constants and macros for entire EWM_SERV register
+ */
+/*@{*/
+#define EWM_RD_SERV(base)        (EWM_SERV_REG(base))
+#define EWM_WR_SERV(base, value) (EWM_SERV_REG(base) = (value))
+#define EWM_RMW_SERV(base, mask, value) (EWM_WR_SERV(base, (EWM_RD_SERV(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_CMPL - Compare Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CMPL - Compare Low Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CMPL register is reset to zero after a CPU reset. This provides no
+ * minimum time for the CPU to service the EWM counter. This register can be written
+ * only once after a CPU reset. Writing this register more than once generates a
+ * bus transfer error.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CMPL register
+ */
+/*@{*/
+#define EWM_RD_CMPL(base)        (EWM_CMPL_REG(base))
+#define EWM_WR_CMPL(base, value) (EWM_CMPL_REG(base) = (value))
+#define EWM_RMW_CMPL(base, mask, value) (EWM_WR_CMPL(base, (EWM_RD_CMPL(base) & ~(mask)) | (value)))
+#define EWM_SET_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) |  (value)))
+#define EWM_CLR_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) & ~(value)))
+#define EWM_TOG_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_CMPH - Compare High Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CMPH - Compare High Register (RW)
+ *
+ * Reset value: 0xFFU
+ *
+ * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
+ * of 256 clocks time, for the CPU to service the EWM counter. This register can
+ * be written only once after a CPU reset. Writing this register more than once
+ * generates a bus transfer error. The valid values for CMPH are up to 0xFE
+ * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
+ * if EWM counter is greater than CMPH.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CMPH register
+ */
+/*@{*/
+#define EWM_RD_CMPH(base)        (EWM_CMPH_REG(base))
+#define EWM_WR_CMPH(base, value) (EWM_CMPH_REG(base) = (value))
+#define EWM_RMW_CMPH(base, mask, value) (EWM_WR_CMPH(base, (EWM_RD_CMPH(base) & ~(mask)) | (value)))
+#define EWM_SET_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) |  (value)))
+#define EWM_CLR_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) & ~(value)))
+#define EWM_TOG_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FB
+ *
+ * FlexBus external bus interface
+ *
+ * Registers defined in this header file:
+ * - FB_CSAR - Chip Select Address Register
+ * - FB_CSMR - Chip Select Mask Register
+ * - FB_CSCR - Chip Select Control Register
+ * - FB_CSPMCR - Chip Select port Multiplexing Control Register
+ */
+
+#define FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
+#define FB_IDX (0U) /*!< Instance number for FB. */
+
+/*******************************************************************************
+ * FB_CSAR - Chip Select Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSAR - Chip Select Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the associated chip-select's base address.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSAR register
+ */
+/*@{*/
+#define FB_RD_CSAR(base, index)  (FB_CSAR_REG(base, index))
+#define FB_WR_CSAR(base, index, value) (FB_CSAR_REG(base, index) = (value))
+#define FB_RMW_CSAR(base, index, mask, value) (FB_WR_CSAR(base, index, (FB_RD_CSAR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) |  (value)))
+#define FB_CLR_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) & ~(value)))
+#define FB_TOG_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSAR bitfields
+ */
+
+/*!
+ * @name Register FB_CSAR, field BA[31:16] (RW)
+ *
+ * Defines the base address for memory dedicated to the associated chip-select.
+ * BA is compared to bits 31-16 on the internal address bus to determine if the
+ * associated chip-select's memory is being accessed. Because the FlexBus module
+ * is one of the slaves connected to the crossbar switch, it is only accessible
+ * within a certain memory range. See the chip memory map for the applicable
+ * FlexBus "expansion" address range for which the chip-selects can be active. Set the
+ * CSARn and CSMRn registers appropriately before accessing this region.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSAR_BA field. */
+#define FB_RD_CSAR_BA(base, index) ((FB_CSAR_REG(base, index) & FB_CSAR_BA_MASK) >> FB_CSAR_BA_SHIFT)
+#define FB_BRD_CSAR_BA(base, index) (FB_RD_CSAR_BA(base, index))
+
+/*! @brief Set the BA field to a new value. */
+#define FB_WR_CSAR_BA(base, index, value) (FB_RMW_CSAR(base, index, FB_CSAR_BA_MASK, FB_CSAR_BA(value)))
+#define FB_BWR_CSAR_BA(base, index, value) (FB_WR_CSAR_BA(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSMR - Chip Select Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSMR - Chip Select Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the address mask and allowable access types for the associated
+ * chip-select.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSMR register
+ */
+/*@{*/
+#define FB_RD_CSMR(base, index)  (FB_CSMR_REG(base, index))
+#define FB_WR_CSMR(base, index, value) (FB_CSMR_REG(base, index) = (value))
+#define FB_RMW_CSMR(base, index, mask, value) (FB_WR_CSMR(base, index, (FB_RD_CSMR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) |  (value)))
+#define FB_CLR_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) & ~(value)))
+#define FB_TOG_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSMR bitfields
+ */
+
+/*!
+ * @name Register FB_CSMR, field V[0] (RW)
+ *
+ * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
+ * Programmed chip-selects do not assert until the V bit is 1b (except for
+ * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
+ * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
+ * select initialization sequence to allow other chip selects to function as
+ * programmed.
+ *
+ * Values:
+ * - 0b0 - Chip-select is invalid.
+ * - 0b1 - Chip-select is valid.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_V field. */
+#define FB_RD_CSMR_V(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_V_MASK) >> FB_CSMR_V_SHIFT)
+#define FB_BRD_CSMR_V(base, index) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_V_SHIFT))
+
+/*! @brief Set the V field to a new value. */
+#define FB_WR_CSMR_V(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_V_MASK, FB_CSMR_V(value)))
+#define FB_BWR_CSMR_V(base, index, value) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_V_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSMR, field WP[8] (RW)
+ *
+ * Controls write accesses to the address range in the corresponding CSAR.
+ *
+ * Values:
+ * - 0b0 - Write accesses are allowed.
+ * - 0b1 - Write accesses are not allowed. Attempting to write to the range of
+ *     addresses for which the WP bit is set results in a bus error termination of
+ *     the internal cycle and no external cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_WP field. */
+#define FB_RD_CSMR_WP(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_WP_MASK) >> FB_CSMR_WP_SHIFT)
+#define FB_BRD_CSMR_WP(base, index) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_WP_SHIFT))
+
+/*! @brief Set the WP field to a new value. */
+#define FB_WR_CSMR_WP(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_WP_MASK, FB_CSMR_WP(value)))
+#define FB_BWR_CSMR_WP(base, index, value) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_WP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSMR, field BAM[31:16] (RW)
+ *
+ * Defines the associated chip-select's block size by masking address bits.
+ *
+ * Values:
+ * - 0b0000000000000000 - The corresponding address bit in CSAR is used in the
+ *     chip-select decode.
+ * - 0b0000000000000001 - The corresponding address bit in CSAR is a don't care
+ *     in the chip-select decode.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_BAM field. */
+#define FB_RD_CSMR_BAM(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_BAM_MASK) >> FB_CSMR_BAM_SHIFT)
+#define FB_BRD_CSMR_BAM(base, index) (FB_RD_CSMR_BAM(base, index))
+
+/*! @brief Set the BAM field to a new value. */
+#define FB_WR_CSMR_BAM(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_BAM_MASK, FB_CSMR_BAM(value)))
+#define FB_BWR_CSMR_BAM(base, index, value) (FB_WR_CSMR_BAM(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSCR - Chip Select Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSCR - Chip Select Control Register (RW)
+ *
+ * Reset value: 0x003FFC00U
+ *
+ * Controls the auto-acknowledge, address setup and hold times, port size, burst
+ * capability, and number of wait states for the associated chip select. To
+ * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
+ * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
+ * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
+ * particular chip for information on the exact CSCR0 reset value.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSCR register
+ */
+/*@{*/
+#define FB_RD_CSCR(base, index)  (FB_CSCR_REG(base, index))
+#define FB_WR_CSCR(base, index, value) (FB_CSCR_REG(base, index) = (value))
+#define FB_RMW_CSCR(base, index, mask, value) (FB_WR_CSCR(base, index, (FB_RD_CSCR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) |  (value)))
+#define FB_CLR_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) & ~(value)))
+#define FB_TOG_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSCR, field BSTW[3] (RW)
+ *
+ * Specifies whether burst writes are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0b0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst writes. For example, a 32-bit write to an
+ *     8-bit port takes four byte writes.
+ * - 0b1 - Enabled. Enables burst write of data larger than the specified port
+ *     size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to
+ *     8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BSTW field. */
+#define FB_RD_CSCR_BSTW(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BSTW_MASK) >> FB_CSCR_BSTW_SHIFT)
+#define FB_BRD_CSCR_BSTW(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTW_SHIFT))
+
+/*! @brief Set the BSTW field to a new value. */
+#define FB_WR_CSCR_BSTW(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BSTW_MASK, FB_CSCR_BSTW(value)))
+#define FB_BWR_CSCR_BSTW(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BSTR[4] (RW)
+ *
+ * Specifies whether burst reads are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0b0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst reads. For example, a 32-bit read from an
+ *     8-bit port is broken into four 8-bit reads.
+ * - 0b1 - Enabled. Enables data burst reads larger than the specified port
+ *     size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
+ *     ports, and line reads from 8-, 16-, and 32-bit ports.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BSTR field. */
+#define FB_RD_CSCR_BSTR(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BSTR_MASK) >> FB_CSCR_BSTR_SHIFT)
+#define FB_BRD_CSCR_BSTR(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTR_SHIFT))
+
+/*! @brief Set the BSTR field to a new value. */
+#define FB_WR_CSCR_BSTR(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BSTR_MASK, FB_CSCR_BSTR(value)))
+#define FB_BWR_CSCR_BSTR(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BEM[5] (RW)
+ *
+ * Specifies whether the corresponding FB_BE is asserted for read accesses.
+ * Certain memories have byte enables that must be asserted during reads and writes.
+ * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
+ * of byte enable support for these SRAMs.
+ *
+ * Values:
+ * - 0b0 - FB_BE is asserted for data write only.
+ * - 0b1 - FB_BE is asserted for data read and write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BEM field. */
+#define FB_RD_CSCR_BEM(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BEM_MASK) >> FB_CSCR_BEM_SHIFT)
+#define FB_BRD_CSCR_BEM(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BEM_SHIFT))
+
+/*! @brief Set the BEM field to a new value. */
+#define FB_WR_CSCR_BEM(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BEM_MASK, FB_CSCR_BEM(value)))
+#define FB_BWR_CSCR_BEM(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BEM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field PS[7:6] (RW)
+ *
+ * Specifies the data port width of the associated chip-select, and determines
+ * where data is driven during write cycles and where data is sampled during read
+ * cycles.
+ *
+ * Values:
+ * - 0b00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
+ * - 0b01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24]
+ *     when BLS is 0b, or FB_D[7:0] when BLS is 1b.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_PS field. */
+#define FB_RD_CSCR_PS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_PS_MASK) >> FB_CSCR_PS_SHIFT)
+#define FB_BRD_CSCR_PS(base, index) (FB_RD_CSCR_PS(base, index))
+
+/*! @brief Set the PS field to a new value. */
+#define FB_WR_CSCR_PS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_PS_MASK, FB_CSCR_PS(value)))
+#define FB_BWR_CSCR_PS(base, index, value) (FB_WR_CSCR_PS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field AA[8] (RW)
+ *
+ * Asserts the internal transfer acknowledge for accesses specified by the
+ * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
+ * asserts an external FB_TA before the wait-state countdown asserts the
+ * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
+ * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
+ *
+ * Values:
+ * - 0b0 - Disabled. No internal transfer acknowledge is asserted and the cycle
+ *     is terminated externally.
+ * - 0b1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_AA field. */
+#define FB_RD_CSCR_AA(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_AA_MASK) >> FB_CSCR_AA_SHIFT)
+#define FB_BRD_CSCR_AA(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_AA_SHIFT))
+
+/*! @brief Set the AA field to a new value. */
+#define FB_WR_CSCR_AA(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_AA_MASK, FB_CSCR_AA(value)))
+#define FB_BWR_CSCR_AA(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_AA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BLS[9] (RW)
+ *
+ * Specifies if data on FB_AD appears left-aligned or right-aligned during the
+ * data phase of a FlexBus access.
+ *
+ * Values:
+ * - 0b0 - Not shifted. Data is left-aligned on FB_AD.
+ * - 0b1 - Shifted. Data is right-aligned on FB_AD.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BLS field. */
+#define FB_RD_CSCR_BLS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BLS_MASK) >> FB_CSCR_BLS_SHIFT)
+#define FB_BRD_CSCR_BLS(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BLS_SHIFT))
+
+/*! @brief Set the BLS field to a new value. */
+#define FB_WR_CSCR_BLS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BLS_MASK, FB_CSCR_BLS(value)))
+#define FB_BWR_CSCR_BLS(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field WS[15:10] (RW)
+ *
+ * Specifies the number of wait states inserted after FlexBus asserts the
+ * associated chip-select and before an internal transfer acknowledge is generated (WS
+ * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_WS field. */
+#define FB_RD_CSCR_WS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_WS_MASK) >> FB_CSCR_WS_SHIFT)
+#define FB_BRD_CSCR_WS(base, index) (FB_RD_CSCR_WS(base, index))
+
+/*! @brief Set the WS field to a new value. */
+#define FB_WR_CSCR_WS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_WS_MASK, FB_CSCR_WS(value)))
+#define FB_BWR_CSCR_WS(base, index, value) (FB_WR_CSCR_WS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field WRAH[17:16] (RW)
+ *
+ * Controls the address, data, and attribute hold time after the termination of
+ * a write cycle that hits in the associated chip-select's address space. The
+ * hold time applies only at the end of a transfer. Therefore, during a burst
+ * transfer or a transfer to a port size smaller than the transfer size, the hold time
+ * is only added after the last bus cycle.
+ *
+ * Values:
+ * - 0b00 - 1 cycle (default for all but FB_CS0 )
+ * - 0b01 - 2 cycles
+ * - 0b10 - 3 cycles
+ * - 0b11 - 4 cycles (default for FB_CS0 )
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_WRAH field. */
+#define FB_RD_CSCR_WRAH(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_WRAH_MASK) >> FB_CSCR_WRAH_SHIFT)
+#define FB_BRD_CSCR_WRAH(base, index) (FB_RD_CSCR_WRAH(base, index))
+
+/*! @brief Set the WRAH field to a new value. */
+#define FB_WR_CSCR_WRAH(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_WRAH_MASK, FB_CSCR_WRAH(value)))
+#define FB_BWR_CSCR_WRAH(base, index, value) (FB_WR_CSCR_WRAH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field RDAH[19:18] (RW)
+ *
+ * Controls the address and attribute hold time after the termination during a
+ * read cycle that hits in the associated chip-select's address space. The hold
+ * time applies only at the end of a transfer. Therefore, during a burst transfer
+ * or a transfer to a port size smaller than the transfer size, the hold time is
+ * only added after the last bus cycle. The number of cycles the address and
+ * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
+ *
+ * Values:
+ * - 0b00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
+ * - 0b01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
+ * - 0b10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
+ * - 0b11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_RDAH field. */
+#define FB_RD_CSCR_RDAH(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_RDAH_MASK) >> FB_CSCR_RDAH_SHIFT)
+#define FB_BRD_CSCR_RDAH(base, index) (FB_RD_CSCR_RDAH(base, index))
+
+/*! @brief Set the RDAH field to a new value. */
+#define FB_WR_CSCR_RDAH(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_RDAH_MASK, FB_CSCR_RDAH(value)))
+#define FB_BWR_CSCR_RDAH(base, index, value) (FB_WR_CSCR_RDAH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field ASET[21:20] (RW)
+ *
+ * Controls when the chip-select is asserted with respect to assertion of a
+ * valid address and attributes.
+ *
+ * Values:
+ * - 0b00 - Assert FB_CSn on the first rising clock edge after the address is
+ *     asserted (default for all but FB_CS0 ).
+ * - 0b01 - Assert FB_CSn on the second rising clock edge after the address is
+ *     asserted.
+ * - 0b10 - Assert FB_CSn on the third rising clock edge after the address is
+ *     asserted.
+ * - 0b11 - Assert FB_CSn on the fourth rising clock edge after the address is
+ *     asserted (default for FB_CS0 ).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_ASET field. */
+#define FB_RD_CSCR_ASET(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_ASET_MASK) >> FB_CSCR_ASET_SHIFT)
+#define FB_BRD_CSCR_ASET(base, index) (FB_RD_CSCR_ASET(base, index))
+
+/*! @brief Set the ASET field to a new value. */
+#define FB_WR_CSCR_ASET(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_ASET_MASK, FB_CSCR_ASET(value)))
+#define FB_BWR_CSCR_ASET(base, index, value) (FB_WR_CSCR_ASET(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field EXTS[22] (RW)
+ *
+ * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
+ * /FB_ALE is asserted.
+ *
+ * Values:
+ * - 0b0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
+ * - 0b1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive
+ *     clock edge after FB_CSn asserts.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_EXTS field. */
+#define FB_RD_CSCR_EXTS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_EXTS_MASK) >> FB_CSCR_EXTS_SHIFT)
+#define FB_BRD_CSCR_EXTS(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_EXTS_SHIFT))
+
+/*! @brief Set the EXTS field to a new value. */
+#define FB_WR_CSCR_EXTS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_EXTS_MASK, FB_CSCR_EXTS(value)))
+#define FB_BWR_CSCR_EXTS(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_EXTS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field SWSEN[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled. A number of wait states (specified by WS) are inserted
+ *     before an internal transfer acknowledge is generated for all transfers.
+ * - 0b1 - Enabled. A number of wait states (specified by SWS) are inserted
+ *     before an internal transfer acknowledge is generated for burst transfer
+ *     secondary terminations.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_SWSEN field. */
+#define FB_RD_CSCR_SWSEN(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_SWSEN_MASK) >> FB_CSCR_SWSEN_SHIFT)
+#define FB_BRD_CSCR_SWSEN(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_SWSEN_SHIFT))
+
+/*! @brief Set the SWSEN field to a new value. */
+#define FB_WR_CSCR_SWSEN(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_SWSEN_MASK, FB_CSCR_SWSEN(value)))
+#define FB_BWR_CSCR_SWSEN(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_SWSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field SWS[31:26] (RW)
+ *
+ * Used only when the SWSEN bit is 1b. Specifies the number of wait states
+ * inserted before an internal transfer acknowledge is generated for a burst transfer
+ * (except for the first termination, which is controlled by WS).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_SWS field. */
+#define FB_RD_CSCR_SWS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_SWS_MASK) >> FB_CSCR_SWS_SHIFT)
+#define FB_BRD_CSCR_SWS(base, index) (FB_RD_CSCR_SWS(base, index))
+
+/*! @brief Set the SWS field to a new value. */
+#define FB_WR_CSCR_SWS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_SWS_MASK, FB_CSCR_SWS(value)))
+#define FB_BWR_CSCR_SWS(base, index, value) (FB_WR_CSCR_SWS(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSPMCR - Chip Select port Multiplexing Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
+ * do any of the following: Write to a reserved address Write to a reserved
+ * field in this register, or Access this register using a size other than 32 bits.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSPMCR register
+ */
+/*@{*/
+#define FB_RD_CSPMCR(base)       (FB_CSPMCR_REG(base))
+#define FB_WR_CSPMCR(base, value) (FB_CSPMCR_REG(base) = (value))
+#define FB_RMW_CSPMCR(base, mask, value) (FB_WR_CSPMCR(base, (FB_RD_CSPMCR(base) & ~(mask)) | (value)))
+#define FB_SET_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) |  (value)))
+#define FB_CLR_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) & ~(value)))
+#define FB_TOG_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSPMCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
+ *
+ * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
+ * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
+ * bus hangs during a transfer.
+ *
+ * Values:
+ * - 0b0000 - FB_TA
+ * - 0b0001 - FB_CS3 . You must also write 1b to CSCR[AA].
+ * - 0b0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
+#define FB_RD_CSPMCR_GROUP5(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP5_MASK) >> FB_CSPMCR_GROUP5_SHIFT)
+#define FB_BRD_CSPMCR_GROUP5(base) (FB_RD_CSPMCR_GROUP5(base))
+
+/*! @brief Set the GROUP5 field to a new value. */
+#define FB_WR_CSPMCR_GROUP5(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP5_MASK, FB_CSPMCR_GROUP5(value)))
+#define FB_BWR_CSPMCR_GROUP5(base, value) (FB_WR_CSPMCR_GROUP5(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
+ *
+ * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_TBST
+ * - 0b0001 - FB_CS2
+ * - 0b0010 - FB_BE_15_8
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
+#define FB_RD_CSPMCR_GROUP4(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP4_MASK) >> FB_CSPMCR_GROUP4_SHIFT)
+#define FB_BRD_CSPMCR_GROUP4(base) (FB_RD_CSPMCR_GROUP4(base))
+
+/*! @brief Set the GROUP4 field to a new value. */
+#define FB_WR_CSPMCR_GROUP4(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP4_MASK, FB_CSPMCR_GROUP4(value)))
+#define FB_BWR_CSPMCR_GROUP4(base, value) (FB_WR_CSPMCR_GROUP4(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
+ *
+ * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_CS5
+ * - 0b0001 - FB_TSIZ1
+ * - 0b0010 - FB_BE_23_16
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
+#define FB_RD_CSPMCR_GROUP3(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP3_MASK) >> FB_CSPMCR_GROUP3_SHIFT)
+#define FB_BRD_CSPMCR_GROUP3(base) (FB_RD_CSPMCR_GROUP3(base))
+
+/*! @brief Set the GROUP3 field to a new value. */
+#define FB_WR_CSPMCR_GROUP3(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP3_MASK, FB_CSPMCR_GROUP3(value)))
+#define FB_BWR_CSPMCR_GROUP3(base, value) (FB_WR_CSPMCR_GROUP3(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
+ *
+ * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_CS4
+ * - 0b0001 - FB_TSIZ0
+ * - 0b0010 - FB_BE_31_24
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
+#define FB_RD_CSPMCR_GROUP2(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP2_MASK) >> FB_CSPMCR_GROUP2_SHIFT)
+#define FB_BRD_CSPMCR_GROUP2(base) (FB_RD_CSPMCR_GROUP2(base))
+
+/*! @brief Set the GROUP2 field to a new value. */
+#define FB_WR_CSPMCR_GROUP2(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP2_MASK, FB_CSPMCR_GROUP2(value)))
+#define FB_BWR_CSPMCR_GROUP2(base, value) (FB_WR_CSPMCR_GROUP2(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
+ *
+ * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
+ *
+ * Values:
+ * - 0b0000 - FB_ALE
+ * - 0b0001 - FB_CS1
+ * - 0b0010 - FB_TS
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
+#define FB_RD_CSPMCR_GROUP1(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP1_MASK) >> FB_CSPMCR_GROUP1_SHIFT)
+#define FB_BRD_CSPMCR_GROUP1(base) (FB_RD_CSPMCR_GROUP1(base))
+
+/*! @brief Set the GROUP1 field to a new value. */
+#define FB_WR_CSPMCR_GROUP1(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP1_MASK, FB_CSPMCR_GROUP1(value)))
+#define FB_BWR_CSPMCR_GROUP1(base, value) (FB_WR_CSPMCR_GROUP1(base, value))
+/*@}*/
+
+/*
+ * MK64F12 FMC
+ *
+ * Flash Memory Controller
+ *
+ * Registers defined in this header file:
+ * - FMC_PFAPR - Flash Access Protection Register
+ * - FMC_PFB0CR - Flash Bank 0 Control Register
+ * - FMC_PFB1CR - Flash Bank 1 Control Register
+ * - FMC_TAGVDW0S - Cache Tag Storage
+ * - FMC_TAGVDW1S - Cache Tag Storage
+ * - FMC_TAGVDW2S - Cache Tag Storage
+ * - FMC_TAGVDW3S - Cache Tag Storage
+ * - FMC_DATA_U - Cache Data Storage (upper word)
+ * - FMC_DATA_L - Cache Data Storage (lower word)
+ */
+
+#define FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */
+#define FMC_IDX (0U) /*!< Instance number for FMC. */
+
+/*******************************************************************************
+ * FMC_PFAPR - Flash Access Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFAPR - Flash Access Protection Register (RW)
+ *
+ * Reset value: 0x00F8003FU
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFAPR register
+ */
+/*@{*/
+#define FMC_RD_PFAPR(base)       (FMC_PFAPR_REG(base))
+#define FMC_WR_PFAPR(base, value) (FMC_PFAPR_REG(base) = (value))
+#define FMC_RMW_PFAPR(base, mask, value) (FMC_WR_PFAPR(base, (FMC_RD_PFAPR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) |  (value)))
+#define FMC_CLR_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) & ~(value)))
+#define FMC_TOG_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFAPR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M0AP field. */
+#define FMC_RD_PFAPR_M0AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M0AP_MASK) >> FMC_PFAPR_M0AP_SHIFT)
+#define FMC_BRD_PFAPR_M0AP(base) (FMC_RD_PFAPR_M0AP(base))
+
+/*! @brief Set the M0AP field to a new value. */
+#define FMC_WR_PFAPR_M0AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M0AP_MASK, FMC_PFAPR_M0AP(value)))
+#define FMC_BWR_PFAPR_M0AP(base, value) (FMC_WR_PFAPR_M0AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M1AP field. */
+#define FMC_RD_PFAPR_M1AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M1AP_MASK) >> FMC_PFAPR_M1AP_SHIFT)
+#define FMC_BRD_PFAPR_M1AP(base) (FMC_RD_PFAPR_M1AP(base))
+
+/*! @brief Set the M1AP field to a new value. */
+#define FMC_WR_PFAPR_M1AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M1AP_MASK, FMC_PFAPR_M1AP(value)))
+#define FMC_BWR_PFAPR_M1AP(base, value) (FMC_WR_PFAPR_M1AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M2AP field. */
+#define FMC_RD_PFAPR_M2AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M2AP_MASK) >> FMC_PFAPR_M2AP_SHIFT)
+#define FMC_BRD_PFAPR_M2AP(base) (FMC_RD_PFAPR_M2AP(base))
+
+/*! @brief Set the M2AP field to a new value. */
+#define FMC_WR_PFAPR_M2AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M2AP_MASK, FMC_PFAPR_M2AP(value)))
+#define FMC_BWR_PFAPR_M2AP(base, value) (FMC_WR_PFAPR_M2AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M3AP field. */
+#define FMC_RD_PFAPR_M3AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M3AP_MASK) >> FMC_PFAPR_M3AP_SHIFT)
+#define FMC_BRD_PFAPR_M3AP(base) (FMC_RD_PFAPR_M3AP(base))
+
+/*! @brief Set the M3AP field to a new value. */
+#define FMC_WR_PFAPR_M3AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M3AP_MASK, FMC_PFAPR_M3AP(value)))
+#define FMC_BWR_PFAPR_M3AP(base, value) (FMC_WR_PFAPR_M3AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M4AP field. */
+#define FMC_RD_PFAPR_M4AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M4AP_MASK) >> FMC_PFAPR_M4AP_SHIFT)
+#define FMC_BRD_PFAPR_M4AP(base) (FMC_RD_PFAPR_M4AP(base))
+
+/*! @brief Set the M4AP field to a new value. */
+#define FMC_WR_PFAPR_M4AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M4AP_MASK, FMC_PFAPR_M4AP(value)))
+#define FMC_BWR_PFAPR_M4AP(base, value) (FMC_WR_PFAPR_M4AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M5AP field. */
+#define FMC_RD_PFAPR_M5AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M5AP_MASK) >> FMC_PFAPR_M5AP_SHIFT)
+#define FMC_BRD_PFAPR_M5AP(base) (FMC_RD_PFAPR_M5AP(base))
+
+/*! @brief Set the M5AP field to a new value. */
+#define FMC_WR_PFAPR_M5AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M5AP_MASK, FMC_PFAPR_M5AP(value)))
+#define FMC_BWR_PFAPR_M5AP(base, value) (FMC_WR_PFAPR_M5AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M6AP field. */
+#define FMC_RD_PFAPR_M6AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M6AP_MASK) >> FMC_PFAPR_M6AP_SHIFT)
+#define FMC_BRD_PFAPR_M6AP(base) (FMC_RD_PFAPR_M6AP(base))
+
+/*! @brief Set the M6AP field to a new value. */
+#define FMC_WR_PFAPR_M6AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M6AP_MASK, FMC_PFAPR_M6AP(value)))
+#define FMC_BWR_PFAPR_M6AP(base, value) (FMC_WR_PFAPR_M6AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master.
+ * - 0b01 - Only read accesses may be performed by this master.
+ * - 0b10 - Only write accesses may be performed by this master.
+ * - 0b11 - Both read and write accesses may be performed by this master.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M7AP field. */
+#define FMC_RD_PFAPR_M7AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M7AP_MASK) >> FMC_PFAPR_M7AP_SHIFT)
+#define FMC_BRD_PFAPR_M7AP(base) (FMC_RD_PFAPR_M7AP(base))
+
+/*! @brief Set the M7AP field to a new value. */
+#define FMC_WR_PFAPR_M7AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M7AP_MASK, FMC_PFAPR_M7AP(value)))
+#define FMC_BWR_PFAPR_M7AP(base, value) (FMC_WR_PFAPR_M7AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M0PFD[16] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M0PFD field. */
+#define FMC_RD_PFAPR_M0PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M0PFD_MASK) >> FMC_PFAPR_M0PFD_SHIFT)
+#define FMC_BRD_PFAPR_M0PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M0PFD_SHIFT))
+
+/*! @brief Set the M0PFD field to a new value. */
+#define FMC_WR_PFAPR_M0PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M0PFD_MASK, FMC_PFAPR_M0PFD(value)))
+#define FMC_BWR_PFAPR_M0PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M0PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M1PFD[17] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M1PFD field. */
+#define FMC_RD_PFAPR_M1PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M1PFD_MASK) >> FMC_PFAPR_M1PFD_SHIFT)
+#define FMC_BRD_PFAPR_M1PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M1PFD_SHIFT))
+
+/*! @brief Set the M1PFD field to a new value. */
+#define FMC_WR_PFAPR_M1PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M1PFD_MASK, FMC_PFAPR_M1PFD(value)))
+#define FMC_BWR_PFAPR_M1PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M1PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M2PFD[18] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M2PFD field. */
+#define FMC_RD_PFAPR_M2PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M2PFD_MASK) >> FMC_PFAPR_M2PFD_SHIFT)
+#define FMC_BRD_PFAPR_M2PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M2PFD_SHIFT))
+
+/*! @brief Set the M2PFD field to a new value. */
+#define FMC_WR_PFAPR_M2PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M2PFD_MASK, FMC_PFAPR_M2PFD(value)))
+#define FMC_BWR_PFAPR_M2PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M2PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M3PFD[19] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M3PFD field. */
+#define FMC_RD_PFAPR_M3PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M3PFD_MASK) >> FMC_PFAPR_M3PFD_SHIFT)
+#define FMC_BRD_PFAPR_M3PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M3PFD_SHIFT))
+
+/*! @brief Set the M3PFD field to a new value. */
+#define FMC_WR_PFAPR_M3PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M3PFD_MASK, FMC_PFAPR_M3PFD(value)))
+#define FMC_BWR_PFAPR_M3PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M3PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M4PFD[20] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M4PFD field. */
+#define FMC_RD_PFAPR_M4PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M4PFD_MASK) >> FMC_PFAPR_M4PFD_SHIFT)
+#define FMC_BRD_PFAPR_M4PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M4PFD_SHIFT))
+
+/*! @brief Set the M4PFD field to a new value. */
+#define FMC_WR_PFAPR_M4PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M4PFD_MASK, FMC_PFAPR_M4PFD(value)))
+#define FMC_BWR_PFAPR_M4PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M4PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M5PFD[21] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M5PFD field. */
+#define FMC_RD_PFAPR_M5PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M5PFD_MASK) >> FMC_PFAPR_M5PFD_SHIFT)
+#define FMC_BRD_PFAPR_M5PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M5PFD_SHIFT))
+
+/*! @brief Set the M5PFD field to a new value. */
+#define FMC_WR_PFAPR_M5PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M5PFD_MASK, FMC_PFAPR_M5PFD(value)))
+#define FMC_BWR_PFAPR_M5PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M5PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M6PFD[22] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M6PFD field. */
+#define FMC_RD_PFAPR_M6PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M6PFD_MASK) >> FMC_PFAPR_M6PFD_SHIFT)
+#define FMC_BRD_PFAPR_M6PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M6PFD_SHIFT))
+
+/*! @brief Set the M6PFD field to a new value. */
+#define FMC_WR_PFAPR_M6PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M6PFD_MASK, FMC_PFAPR_M6PFD(value)))
+#define FMC_BWR_PFAPR_M6PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M6PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M7PFD[23] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M7PFD field. */
+#define FMC_RD_PFAPR_M7PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M7PFD_MASK) >> FMC_PFAPR_M7PFD_SHIFT)
+#define FMC_BRD_PFAPR_M7PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M7PFD_SHIFT))
+
+/*! @brief Set the M7PFD field to a new value. */
+#define FMC_WR_PFAPR_M7PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M7PFD_MASK, FMC_PFAPR_M7PFD(value)))
+#define FMC_BWR_PFAPR_M7PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M7PFD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_PFB0CR - Flash Bank 0 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFB0CR - Flash Bank 0 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFB0CR register
+ */
+/*@{*/
+#define FMC_RD_PFB0CR(base)      (FMC_PFB0CR_REG(base))
+#define FMC_WR_PFB0CR(base, value) (FMC_PFB0CR_REG(base) = (value))
+#define FMC_RMW_PFB0CR(base, mask, value) (FMC_WR_PFB0CR(base, (FMC_RD_PFB0CR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) |  (value)))
+#define FMC_CLR_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) & ~(value)))
+#define FMC_TOG_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFB0CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry page buffer is enabled in response
+ * to flash read accesses. Its operation is independent from bank 1's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0b0 - Single entry buffer is disabled.
+ * - 0b1 - Single entry buffer is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */
+#define FMC_RD_PFB0CR_B0SEBE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0SEBE_MASK) >> FMC_PFB0CR_B0SEBE_SHIFT)
+#define FMC_BRD_PFB0CR_B0SEBE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0SEBE_SHIFT))
+
+/*! @brief Set the B0SEBE field to a new value. */
+#define FMC_WR_PFB0CR_B0SEBE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0SEBE_MASK, FMC_PFB0CR_B0SEBE(value)))
+#define FMC_BWR_PFB0CR_B0SEBE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0SEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to instruction fetches.
+ * - 0b1 - Enable prefetches in response to instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */
+#define FMC_RD_PFB0CR_B0IPE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0IPE_MASK) >> FMC_PFB0CR_B0IPE_SHIFT)
+#define FMC_BRD_PFB0CR_B0IPE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0IPE_SHIFT))
+
+/*! @brief Set the B0IPE field to a new value. */
+#define FMC_WR_PFB0CR_B0IPE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0IPE_MASK, FMC_PFB0CR_B0IPE(value)))
+#define FMC_BWR_PFB0CR_B0IPE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0IPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to data references.
+ * - 0b1 - Enable prefetches in response to data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */
+#define FMC_RD_PFB0CR_B0DPE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0DPE_MASK) >> FMC_PFB0CR_B0DPE_SHIFT)
+#define FMC_BRD_PFB0CR_B0DPE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DPE_SHIFT))
+
+/*! @brief Set the B0DPE field to a new value. */
+#define FMC_WR_PFB0CR_B0DPE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0DPE_MASK, FMC_PFB0CR_B0DPE(value)))
+#define FMC_BWR_PFB0CR_B0DPE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache instruction fetches.
+ * - 0b1 - Cache instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */
+#define FMC_RD_PFB0CR_B0ICE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0ICE_MASK) >> FMC_PFB0CR_B0ICE_SHIFT)
+#define FMC_BRD_PFB0CR_B0ICE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0ICE_SHIFT))
+
+/*! @brief Set the B0ICE field to a new value. */
+#define FMC_WR_PFB0CR_B0ICE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0ICE_MASK, FMC_PFB0CR_B0ICE(value)))
+#define FMC_BWR_PFB0CR_B0ICE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0ICE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache data references.
+ * - 0b1 - Cache data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */
+#define FMC_RD_PFB0CR_B0DCE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0DCE_MASK) >> FMC_PFB0CR_B0DCE_SHIFT)
+#define FMC_BRD_PFB0CR_B0DCE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DCE_SHIFT))
+
+/*! @brief Set the B0DCE field to a new value. */
+#define FMC_WR_PFB0CR_B0DCE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0DCE_MASK, FMC_PFB0CR_B0DCE(value)))
+#define FMC_BWR_PFB0CR_B0DCE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
+ *
+ * This 3-bit field defines the replacement algorithm for accesses that are
+ * cached.
+ *
+ * Values:
+ * - 0b000 - LRU replacement algorithm per set across all four ways
+ * - 0b001 - Reserved
+ * - 0b010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
+ * - 0b011 - Independent LRU with ways [0-2] for ifetches, [3] for data
+ * - 0b1xx - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_CRC field. */
+#define FMC_RD_PFB0CR_CRC(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_CRC_MASK) >> FMC_PFB0CR_CRC_SHIFT)
+#define FMC_BRD_PFB0CR_CRC(base) (FMC_RD_PFB0CR_CRC(base))
+
+/*! @brief Set the CRC field to a new value. */
+#define FMC_WR_PFB0CR_CRC(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CRC_MASK, FMC_PFB0CR_CRC(value)))
+#define FMC_BWR_PFB0CR_CRC(base, value) (FMC_WR_PFB0CR_CRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 0 memory.
+ *
+ * Values:
+ * - 0b00 - 32 bits
+ * - 0b01 - 64 bits
+ * - 0b10 - 128 bits
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0MW field. */
+#define FMC_RD_PFB0CR_B0MW(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0MW_MASK) >> FMC_PFB0CR_B0MW_SHIFT)
+#define FMC_BRD_PFB0CR_B0MW(base) (FMC_RD_PFB0CR_B0MW(base))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
+ *
+ * This bit determines if the FMC's prefetch speculation buffer and the single
+ * entry page buffer are to be invalidated (cleared). When this bit is written,
+ * the speculation buffer and single entry buffer are immediately cleared. This bit
+ * always reads as zero.
+ *
+ * Values:
+ * - 0b0 - Speculation buffer and single entry buffer are not affected.
+ * - 0b1 - Invalidate (clear) speculation buffer and single entry buffer.
+ */
+/*@{*/
+/*! @brief Set the S_B_INV field to a new value. */
+#define FMC_WR_PFB0CR_S_B_INV(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_S_B_INV_MASK, FMC_PFB0CR_S_B_INV(value)))
+#define FMC_BWR_PFB0CR_S_B_INV(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_S_B_INV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
+ *
+ * These bits determine if the given cache way is to be invalidated (cleared).
+ * When a bit within this field is written, the corresponding cache way is
+ * immediately invalidated: the way's tag, data, and valid contents are cleared. This
+ * field always reads as zero. Cache invalidation takes precedence over locking.
+ * The cache is invalidated by system reset. System software is required to
+ * maintain memory coherency when any segment of the flash memory is programmed or
+ * erased. Accordingly, cache invalidations must occur after a programming or erase
+ * event is completed and before the new memory image is accessed. The bit setting
+ * definitions are for each bit in the field.
+ *
+ * Values:
+ * - 0b0000 - No cache way invalidation for the corresponding cache
+ * - 0b0001 - Invalidate cache way for the corresponding cache: clear the tag,
+ *     data, and vld bits of ways selected
+ */
+/*@{*/
+/*! @brief Set the CINV_WAY field to a new value. */
+#define FMC_WR_PFB0CR_CINV_WAY(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY(value)))
+#define FMC_BWR_PFB0CR_CINV_WAY(base, value) (FMC_WR_PFB0CR_CINV_WAY(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
+ *
+ * These bits determine if the given cache way is locked such that its contents
+ * will not be displaced by future misses. The bit setting definitions are for
+ * each bit in the field.
+ *
+ * Values:
+ * - 0b0000 - Cache way is unlocked and may be displaced
+ * - 0b0001 - Cache way is locked and its contents are not displaced
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */
+#define FMC_RD_PFB0CR_CLCK_WAY(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_CLCK_WAY_MASK) >> FMC_PFB0CR_CLCK_WAY_SHIFT)
+#define FMC_BRD_PFB0CR_CLCK_WAY(base) (FMC_RD_PFB0CR_CLCK_WAY(base))
+
+/*! @brief Set the CLCK_WAY field to a new value. */
+#define FMC_WR_PFB0CR_CLCK_WAY(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CLCK_WAY_MASK, FMC_PFB0CR_CLCK_WAY(value)))
+#define FMC_BWR_PFB0CR_CLCK_WAY(base, value) (FMC_WR_PFB0CR_CLCK_WAY(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 0 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */
+#define FMC_RD_PFB0CR_B0RWSC(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0RWSC_MASK) >> FMC_PFB0CR_B0RWSC_SHIFT)
+#define FMC_BRD_PFB0CR_B0RWSC(base) (FMC_RD_PFB0CR_B0RWSC(base))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_PFB1CR - Flash Bank 1 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFB1CR - Flash Bank 1 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ *
+ * This register has a format similar to that for PFB0CR, except it controls the
+ * operation of flash bank 1, and the "global" cache control fields are empty.
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFB1CR register
+ */
+/*@{*/
+#define FMC_RD_PFB1CR(base)      (FMC_PFB1CR_REG(base))
+#define FMC_WR_PFB1CR(base, value) (FMC_PFB1CR_REG(base) = (value))
+#define FMC_RMW_PFB1CR(base, mask, value) (FMC_WR_PFB1CR(base, (FMC_RD_PFB1CR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) |  (value)))
+#define FMC_CLR_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) & ~(value)))
+#define FMC_TOG_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFB1CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry buffer is enabled in response to
+ * flash read accesses. Its operation is independent from bank 0's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0b0 - Single entry buffer is disabled.
+ * - 0b1 - Single entry buffer is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */
+#define FMC_RD_PFB1CR_B1SEBE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1SEBE_MASK) >> FMC_PFB1CR_B1SEBE_SHIFT)
+#define FMC_BRD_PFB1CR_B1SEBE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1SEBE_SHIFT))
+
+/*! @brief Set the B1SEBE field to a new value. */
+#define FMC_WR_PFB1CR_B1SEBE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1SEBE_MASK, FMC_PFB1CR_B1SEBE(value)))
+#define FMC_BWR_PFB1CR_B1SEBE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1SEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to instruction fetches.
+ * - 0b1 - Enable prefetches in response to instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */
+#define FMC_RD_PFB1CR_B1IPE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1IPE_MASK) >> FMC_PFB1CR_B1IPE_SHIFT)
+#define FMC_BRD_PFB1CR_B1IPE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1IPE_SHIFT))
+
+/*! @brief Set the B1IPE field to a new value. */
+#define FMC_WR_PFB1CR_B1IPE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1IPE_MASK, FMC_PFB1CR_B1IPE(value)))
+#define FMC_BWR_PFB1CR_B1IPE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1IPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to data references.
+ * - 0b1 - Enable prefetches in response to data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */
+#define FMC_RD_PFB1CR_B1DPE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1DPE_MASK) >> FMC_PFB1CR_B1DPE_SHIFT)
+#define FMC_BRD_PFB1CR_B1DPE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DPE_SHIFT))
+
+/*! @brief Set the B1DPE field to a new value. */
+#define FMC_WR_PFB1CR_B1DPE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1DPE_MASK, FMC_PFB1CR_B1DPE(value)))
+#define FMC_BWR_PFB1CR_B1DPE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache instruction fetches.
+ * - 0b1 - Cache instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */
+#define FMC_RD_PFB1CR_B1ICE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1ICE_MASK) >> FMC_PFB1CR_B1ICE_SHIFT)
+#define FMC_BRD_PFB1CR_B1ICE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1ICE_SHIFT))
+
+/*! @brief Set the B1ICE field to a new value. */
+#define FMC_WR_PFB1CR_B1ICE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1ICE_MASK, FMC_PFB1CR_B1ICE(value)))
+#define FMC_BWR_PFB1CR_B1ICE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1ICE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache data references.
+ * - 0b1 - Cache data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */
+#define FMC_RD_PFB1CR_B1DCE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1DCE_MASK) >> FMC_PFB1CR_B1DCE_SHIFT)
+#define FMC_BRD_PFB1CR_B1DCE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DCE_SHIFT))
+
+/*! @brief Set the B1DCE field to a new value. */
+#define FMC_WR_PFB1CR_B1DCE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1DCE_MASK, FMC_PFB1CR_B1DCE(value)))
+#define FMC_BWR_PFB1CR_B1DCE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 1 memory.
+ *
+ * Values:
+ * - 0b00 - 32 bits
+ * - 0b01 - 64 bits
+ * - 0b10 - 128 bits
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1MW field. */
+#define FMC_RD_PFB1CR_B1MW(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1MW_MASK) >> FMC_PFB1CR_B1MW_SHIFT)
+#define FMC_BRD_PFB1CR_B1MW(base) (FMC_RD_PFB1CR_B1MW(base))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 1 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */
+#define FMC_RD_PFB1CR_B1RWSC(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1RWSC_MASK) >> FMC_PFB1CR_B1RWSC_SHIFT)
+#define FMC_BRD_PFB1CR_B1RWSC(base) (FMC_RD_PFB1CR_B1RWSC(base))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW0S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW0S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW0S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW0S(base, index) (FMC_TAGVDW0S_REG(base, index))
+#define FMC_WR_TAGVDW0S(base, index, value) (FMC_TAGVDW0S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW0S(base, index, mask, value) (FMC_WR_TAGVDW0S(base, index, (FMC_RD_TAGVDW0S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW0S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW0S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW0S_valid field. */
+#define FMC_RD_TAGVDW0S_valid(base, index) ((FMC_TAGVDW0S_REG(base, index) & FMC_TAGVDW0S_valid_MASK) >> FMC_TAGVDW0S_valid_SHIFT)
+#define FMC_BRD_TAGVDW0S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW0S_REG(base, index), FMC_TAGVDW0S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW0S_valid(base, index, value) (FMC_RMW_TAGVDW0S(base, index, FMC_TAGVDW0S_valid_MASK, FMC_TAGVDW0S_valid(value)))
+#define FMC_BWR_TAGVDW0S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW0S_REG(base, index), FMC_TAGVDW0S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW0S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW0S_tag field. */
+#define FMC_RD_TAGVDW0S_tag(base, index) ((FMC_TAGVDW0S_REG(base, index) & FMC_TAGVDW0S_tag_MASK) >> FMC_TAGVDW0S_tag_SHIFT)
+#define FMC_BRD_TAGVDW0S_tag(base, index) (FMC_RD_TAGVDW0S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW0S_tag(base, index, value) (FMC_RMW_TAGVDW0S(base, index, FMC_TAGVDW0S_tag_MASK, FMC_TAGVDW0S_tag(value)))
+#define FMC_BWR_TAGVDW0S_tag(base, index, value) (FMC_WR_TAGVDW0S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW1S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW1S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW1S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW1S(base, index) (FMC_TAGVDW1S_REG(base, index))
+#define FMC_WR_TAGVDW1S(base, index, value) (FMC_TAGVDW1S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW1S(base, index, mask, value) (FMC_WR_TAGVDW1S(base, index, (FMC_RD_TAGVDW1S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW1S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW1S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW1S_valid field. */
+#define FMC_RD_TAGVDW1S_valid(base, index) ((FMC_TAGVDW1S_REG(base, index) & FMC_TAGVDW1S_valid_MASK) >> FMC_TAGVDW1S_valid_SHIFT)
+#define FMC_BRD_TAGVDW1S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW1S_REG(base, index), FMC_TAGVDW1S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW1S_valid(base, index, value) (FMC_RMW_TAGVDW1S(base, index, FMC_TAGVDW1S_valid_MASK, FMC_TAGVDW1S_valid(value)))
+#define FMC_BWR_TAGVDW1S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW1S_REG(base, index), FMC_TAGVDW1S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW1S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW1S_tag field. */
+#define FMC_RD_TAGVDW1S_tag(base, index) ((FMC_TAGVDW1S_REG(base, index) & FMC_TAGVDW1S_tag_MASK) >> FMC_TAGVDW1S_tag_SHIFT)
+#define FMC_BRD_TAGVDW1S_tag(base, index) (FMC_RD_TAGVDW1S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW1S_tag(base, index, value) (FMC_RMW_TAGVDW1S(base, index, FMC_TAGVDW1S_tag_MASK, FMC_TAGVDW1S_tag(value)))
+#define FMC_BWR_TAGVDW1S_tag(base, index, value) (FMC_WR_TAGVDW1S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW2S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW2S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW2S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW2S(base, index) (FMC_TAGVDW2S_REG(base, index))
+#define FMC_WR_TAGVDW2S(base, index, value) (FMC_TAGVDW2S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW2S(base, index, mask, value) (FMC_WR_TAGVDW2S(base, index, (FMC_RD_TAGVDW2S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW2S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW2S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW2S_valid field. */
+#define FMC_RD_TAGVDW2S_valid(base, index) ((FMC_TAGVDW2S_REG(base, index) & FMC_TAGVDW2S_valid_MASK) >> FMC_TAGVDW2S_valid_SHIFT)
+#define FMC_BRD_TAGVDW2S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW2S_REG(base, index), FMC_TAGVDW2S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW2S_valid(base, index, value) (FMC_RMW_TAGVDW2S(base, index, FMC_TAGVDW2S_valid_MASK, FMC_TAGVDW2S_valid(value)))
+#define FMC_BWR_TAGVDW2S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW2S_REG(base, index), FMC_TAGVDW2S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW2S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW2S_tag field. */
+#define FMC_RD_TAGVDW2S_tag(base, index) ((FMC_TAGVDW2S_REG(base, index) & FMC_TAGVDW2S_tag_MASK) >> FMC_TAGVDW2S_tag_SHIFT)
+#define FMC_BRD_TAGVDW2S_tag(base, index) (FMC_RD_TAGVDW2S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW2S_tag(base, index, value) (FMC_RMW_TAGVDW2S(base, index, FMC_TAGVDW2S_tag_MASK, FMC_TAGVDW2S_tag(value)))
+#define FMC_BWR_TAGVDW2S_tag(base, index, value) (FMC_WR_TAGVDW2S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW3S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW3S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW3S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW3S(base, index) (FMC_TAGVDW3S_REG(base, index))
+#define FMC_WR_TAGVDW3S(base, index, value) (FMC_TAGVDW3S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW3S(base, index, mask, value) (FMC_WR_TAGVDW3S(base, index, (FMC_RD_TAGVDW3S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW3S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW3S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW3S_valid field. */
+#define FMC_RD_TAGVDW3S_valid(base, index) ((FMC_TAGVDW3S_REG(base, index) & FMC_TAGVDW3S_valid_MASK) >> FMC_TAGVDW3S_valid_SHIFT)
+#define FMC_BRD_TAGVDW3S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW3S_REG(base, index), FMC_TAGVDW3S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW3S_valid(base, index, value) (FMC_RMW_TAGVDW3S(base, index, FMC_TAGVDW3S_valid_MASK, FMC_TAGVDW3S_valid(value)))
+#define FMC_BWR_TAGVDW3S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW3S_REG(base, index), FMC_TAGVDW3S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW3S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW3S_tag field. */
+#define FMC_RD_TAGVDW3S_tag(base, index) ((FMC_TAGVDW3S_REG(base, index) & FMC_TAGVDW3S_tag_MASK) >> FMC_TAGVDW3S_tag_SHIFT)
+#define FMC_BRD_TAGVDW3S_tag(base, index) (FMC_RD_TAGVDW3S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW3S_tag(base, index, value) (FMC_RMW_TAGVDW3S(base, index, FMC_TAGVDW3S_tag_MASK, FMC_TAGVDW3S_tag(value)))
+#define FMC_BWR_TAGVDW3S_tag(base, index, value) (FMC_WR_TAGVDW3S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_DATA_U - Cache Data Storage (upper word)
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_DATA_U - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_DATA_U register
+ */
+/*@{*/
+#define FMC_RD_DATA_U(base, index, index2) (FMC_DATA_U_REG(base, index, index2))
+#define FMC_WR_DATA_U(base, index, index2, value) (FMC_DATA_U_REG(base, index, index2) = (value))
+#define FMC_RMW_DATA_U(base, index, index2, mask, value) (FMC_WR_DATA_U(base, index, index2, (FMC_RD_DATA_U(base, index, index2) & ~(mask)) | (value)))
+#define FMC_SET_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) |  (value)))
+#define FMC_CLR_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) & ~(value)))
+#define FMC_TOG_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_DATA_L - Cache Data Storage (lower word)
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_DATA_L - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_DATA_L register
+ */
+/*@{*/
+#define FMC_RD_DATA_L(base, index, index2) (FMC_DATA_L_REG(base, index, index2))
+#define FMC_WR_DATA_L(base, index, index2, value) (FMC_DATA_L_REG(base, index, index2) = (value))
+#define FMC_RMW_DATA_L(base, index, index2, mask, value) (FMC_WR_DATA_L(base, index, index2, (FMC_RD_DATA_L(base, index, index2) & ~(mask)) | (value)))
+#define FMC_SET_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) |  (value)))
+#define FMC_CLR_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) & ~(value)))
+#define FMC_TOG_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FTFE
+ *
+ * Flash Memory Interface
+ *
+ * Registers defined in this header file:
+ * - FTFE_FSTAT - Flash Status Register
+ * - FTFE_FCNFG - Flash Configuration Register
+ * - FTFE_FSEC - Flash Security Register
+ * - FTFE_FOPT - Flash Option Register
+ * - FTFE_FCCOB3 - Flash Common Command Object Registers
+ * - FTFE_FCCOB2 - Flash Common Command Object Registers
+ * - FTFE_FCCOB1 - Flash Common Command Object Registers
+ * - FTFE_FCCOB0 - Flash Common Command Object Registers
+ * - FTFE_FCCOB7 - Flash Common Command Object Registers
+ * - FTFE_FCCOB6 - Flash Common Command Object Registers
+ * - FTFE_FCCOB5 - Flash Common Command Object Registers
+ * - FTFE_FCCOB4 - Flash Common Command Object Registers
+ * - FTFE_FCCOBB - Flash Common Command Object Registers
+ * - FTFE_FCCOBA - Flash Common Command Object Registers
+ * - FTFE_FCCOB9 - Flash Common Command Object Registers
+ * - FTFE_FCCOB8 - Flash Common Command Object Registers
+ * - FTFE_FPROT3 - Program Flash Protection Registers
+ * - FTFE_FPROT2 - Program Flash Protection Registers
+ * - FTFE_FPROT1 - Program Flash Protection Registers
+ * - FTFE_FPROT0 - Program Flash Protection Registers
+ * - FTFE_FEPROT - EEPROM Protection Register
+ * - FTFE_FDPROT - Data Flash Protection Register
+ */
+
+#define FTFE_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFE module. */
+#define FTFE_IDX (0U) /*!< Instance number for FTFE. */
+
+/*******************************************************************************
+ * FTFE_FSTAT - Flash Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FSTAT - Flash Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FSTAT register reports the operational status of the FTFE module. The
+ * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0
+ * bit is read only. The unassigned bits read 0 and are not writable. When set, the
+ * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this
+ * register prevent the launch of any more commands or writes to the FlexRAM (when
+ * EEERDY is set) until the flag is cleared (by writing a one to it).
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FSTAT register
+ */
+/*@{*/
+#define FTFE_RD_FSTAT(base)      (FTFE_FSTAT_REG(base))
+#define FTFE_WR_FSTAT(base, value) (FTFE_FSTAT_REG(base) = (value))
+#define FTFE_RMW_FSTAT(base, mask, value) (FTFE_WR_FSTAT(base, (FTFE_RD_FSTAT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) |  (value)))
+#define FTFE_CLR_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) & ~(value)))
+#define FTFE_TOG_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FSTAT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO)
+ *
+ * The MGSTAT0 status flag is set if an error is detected during execution of an
+ * FTFE command or during the flash reset sequence. As a status flag, this bit
+ * cannot (and need not) be cleared by the user like the other error flags in this
+ * register. The value of the MGSTAT0 bit for "command-N" is valid only at the
+ * end of the "command-N" execution when CCIF=1 and before the next command has
+ * been launched. At some point during the execution of "command-N+1," the previous
+ * result is discarded and any previous error is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field. */
+#define FTFE_RD_FSTAT_MGSTAT0(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_MGSTAT0_MASK) >> FTFE_FSTAT_MGSTAT0_SHIFT)
+#define FTFE_BRD_FSTAT_MGSTAT0(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_MGSTAT0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C)
+ *
+ * The FPVIOL error bit indicates an attempt was made to program or erase an
+ * address in a protected area of program flash or data flash memory during a
+ * command write sequence or a write was attempted to a protected area of the FlexRAM
+ * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared
+ * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a
+ * 0 to the FPVIOL bit has no effect.
+ *
+ * Values:
+ * - 0b0 - No protection violation detected
+ * - 0b1 - Protection violation detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_FPVIOL field. */
+#define FTFE_RD_FSTAT_FPVIOL(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_FPVIOL_MASK) >> FTFE_FSTAT_FPVIOL_SHIFT)
+#define FTFE_BRD_FSTAT_FPVIOL(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_FPVIOL_SHIFT))
+
+/*! @brief Set the FPVIOL field to a new value. */
+#define FTFE_WR_FSTAT_FPVIOL(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_FPVIOL(value)))
+#define FTFE_BWR_FSTAT_FPVIOL(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_FPVIOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field ACCERR[5] (W1C)
+ *
+ * The ACCERR error bit indicates an illegal access has occurred to an FTFE
+ * resource caused by a violation of the command write sequence or issuing an illegal
+ * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch
+ * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
+ * ACCERR bit has no effect.
+ *
+ * Values:
+ * - 0b0 - No access error detected
+ * - 0b1 - Access error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_ACCERR field. */
+#define FTFE_RD_FSTAT_ACCERR(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_ACCERR_MASK) >> FTFE_FSTAT_ACCERR_SHIFT)
+#define FTFE_BRD_FSTAT_ACCERR(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_ACCERR_SHIFT))
+
+/*! @brief Set the ACCERR field to a new value. */
+#define FTFE_WR_FSTAT_ACCERR(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_ACCERR(value)))
+#define FTFE_BWR_FSTAT_ACCERR(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_ACCERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C)
+ *
+ * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE
+ * resource that was being manipulated by an FTFE command (CCIF=0). Any
+ * simultaneous access is detected as a collision error by the block arbitration logic. The
+ * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by
+ * writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
+ *
+ * Values:
+ * - 0b0 - No collision error detected
+ * - 0b1 - Collision error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_RDCOLERR field. */
+#define FTFE_RD_FSTAT_RDCOLERR(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_RDCOLERR_MASK) >> FTFE_FSTAT_RDCOLERR_SHIFT)
+#define FTFE_BRD_FSTAT_RDCOLERR(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_RDCOLERR_SHIFT))
+
+/*! @brief Set the RDCOLERR field to a new value. */
+#define FTFE_WR_FSTAT_RDCOLERR(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_RDCOLERR(value)))
+#define FTFE_BWR_FSTAT_RDCOLERR(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_RDCOLERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field CCIF[7] (W1C)
+ *
+ * The CCIF flag indicates that a FTFE command or EEPROM file system operation
+ * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a
+ * command, and CCIF stays low until command completion or command violation. The
+ * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE,
+ * and CCIF stays low until the EEPROM file system has created the associated
+ * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory
+ * controller at the end of the reset initialization sequence. Depending on how
+ * quickly the read occurs after reset release, the user may or may not see the 0
+ * hardware reset value.
+ *
+ * Values:
+ * - 0b0 - FTFE command or EEPROM file system operation in progress
+ * - 0b1 - FTFE command or EEPROM file system operation has completed
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_CCIF field. */
+#define FTFE_RD_FSTAT_CCIF(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_CCIF_MASK) >> FTFE_FSTAT_CCIF_SHIFT)
+#define FTFE_BRD_FSTAT_CCIF(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_CCIF_SHIFT))
+
+/*! @brief Set the CCIF field to a new value. */
+#define FTFE_WR_FSTAT_CCIF(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_CCIF_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_RDCOLERR_MASK), FTFE_FSTAT_CCIF(value)))
+#define FTFE_BWR_FSTAT_CCIF(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_CCIF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCNFG - Flash Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCNFG - Flash Configuration Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides information on the current functional state of the
+ * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write
+ * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned
+ * bits read as noted and are not writable. The reset values for the SWAP, PFLSH,
+ * RAMRDY, and EEERDY bits are determined during the reset sequence.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCNFG register
+ */
+/*@{*/
+#define FTFE_RD_FCNFG(base)      (FTFE_FCNFG_REG(base))
+#define FTFE_WR_FCNFG(base, value) (FTFE_FCNFG_REG(base) = (value))
+#define FTFE_RMW_FCNFG(base, mask, value) (FTFE_WR_FCNFG(base, (FTFE_RD_FCNFG(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) |  (value)))
+#define FTFE_CLR_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) & ~(value)))
+#define FTFE_TOG_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FCNFG bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCNFG, field EEERDY[0] (RO)
+ *
+ * For devices with FlexNVM: This flag indicates if the EEPROM backup data has
+ * been copied to the FlexRAM and is therefore available for read access. During
+ * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if
+ * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM:
+ * This bit is reserved.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FlexRAM is not available for EEPROM
+ *     operation.
+ * - 0b1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations
+ *     where: reads from the FlexRAM return data previously written to the
+ *     FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the
+ *     written data in the FlexRAM and EEPROM backup.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_EEERDY field. */
+#define FTFE_RD_FCNFG_EEERDY(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_EEERDY_MASK) >> FTFE_FCNFG_EEERDY_SHIFT)
+#define FTFE_BRD_FCNFG_EEERDY(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_EEERDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field RAMRDY[1] (RO)
+ *
+ * This flag indicates the current status of the FlexRAM/ programming
+ * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally
+ * controlled by the Set FlexRAM Function command. During the reset sequence, the
+ * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will
+ * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is
+ * cleared if the Program Partition command is run to partition the FlexNVM block
+ * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks
+ * command or execution of the erase-all operation triggered external to the FTFE.
+ * For devices without FlexNVM: This bit should always be set.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FlexRAM is not available for traditional
+ *     RAM access. For devices without FlexNVM: Programming acceleration RAM is not
+ *     available.
+ * - 0b1 - For devices with FlexNVM: FlexRAM is available as traditional RAM
+ *     only; writes to the FlexRAM do not trigger EEPROM operations. For devices
+ *     without FlexNVM: Programming acceleration RAM is available.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_RAMRDY field. */
+#define FTFE_RD_FCNFG_RAMRDY(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_RAMRDY_MASK) >> FTFE_FCNFG_RAMRDY_SHIFT)
+#define FTFE_BRD_FCNFG_RAMRDY(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RAMRDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field PFLSH[2] (RO)
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FTFE configuration supports two program
+ *     flash blocks and two FlexNVM blocks For devices with program flash only:
+ *     Reserved
+ * - 0b1 - For devices with FlexNVM: Reserved For devices with program flash
+ *     only: FTFE configuration supports four program flash blocks
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_PFLSH field. */
+#define FTFE_RD_FCNFG_PFLSH(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_PFLSH_MASK) >> FTFE_FCNFG_PFLSH_SHIFT)
+#define FTFE_BRD_FCNFG_PFLSH(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_PFLSH_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field SWAP[3] (RO)
+ *
+ * The SWAP flag indicates which half of the program flash space is located at
+ * relative address 0x0000. The state of the SWAP flag is set by the FTFE during
+ * the reset sequence. See for information on swap management.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: Program flash 0 block is located at
+ *     relative address 0x0000 For devices with program flash only: Program flash 0
+ *     block is located at relative address 0x0000
+ * - 0b1 - For devices with FlexNVM: Reserved For devices with program flash
+ *     only: Program flash 1 block is located at relative address 0x0000
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_SWAP field. */
+#define FTFE_RD_FCNFG_SWAP(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_SWAP_MASK) >> FTFE_FCNFG_SWAP_SHIFT)
+#define FTFE_BRD_FCNFG_SWAP(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_SWAP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW)
+ *
+ * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector
+ * command while it is executing.
+ *
+ * Values:
+ * - 0b0 - No suspend requested
+ * - 0b1 - Suspend the current Erase Flash Sector command execution.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_ERSSUSP field. */
+#define FTFE_RD_FCNFG_ERSSUSP(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_ERSSUSP_MASK) >> FTFE_FCNFG_ERSSUSP_SHIFT)
+#define FTFE_BRD_FCNFG_ERSSUSP(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSSUSP_SHIFT))
+
+/*! @brief Set the ERSSUSP field to a new value. */
+#define FTFE_WR_FCNFG_ERSSUSP(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_ERSSUSP_MASK, FTFE_FCNFG_ERSSUSP(value)))
+#define FTFE_BWR_FCNFG_ERSSUSP(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSSUSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO)
+ *
+ * This bit issues a request to the memory controller to execute the Erase All
+ * Blocks command and release security. ERSAREQ is not directly writable but is
+ * under indirect user control. Refer to the device's Chip Configuration details on
+ * how to request this command. The ERSAREQ bit sets when an erase all request
+ * is triggered external to the FTFE and CCIF is set (no command is currently
+ * being executed). ERSAREQ is cleared by the FTFE when the operation completes.
+ *
+ * Values:
+ * - 0b0 - No request or request complete
+ * - 0b1 - Request to: run the Erase All Blocks command, verify the erased
+ *     state, program the security byte in the Flash Configuration Field to the
+ *     unsecure state, and release MCU security by setting the FSEC[SEC] field to the
+ *     unsecure state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_ERSAREQ field. */
+#define FTFE_RD_FCNFG_ERSAREQ(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_ERSAREQ_MASK) >> FTFE_FCNFG_ERSAREQ_SHIFT)
+#define FTFE_BRD_FCNFG_ERSAREQ(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSAREQ_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW)
+ *
+ * The RDCOLLIE bit controls interrupt generation when an FTFE read collision
+ * error occurs.
+ *
+ * Values:
+ * - 0b0 - Read collision error interrupt disabled
+ * - 0b1 - Read collision error interrupt enabled. An interrupt request is
+ *     generated whenever an FTFE read collision error is detected (see the
+ *     description of FSTAT[RDCOLERR]).
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field. */
+#define FTFE_RD_FCNFG_RDCOLLIE(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_RDCOLLIE_MASK) >> FTFE_FCNFG_RDCOLLIE_SHIFT)
+#define FTFE_BRD_FCNFG_RDCOLLIE(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RDCOLLIE_SHIFT))
+
+/*! @brief Set the RDCOLLIE field to a new value. */
+#define FTFE_WR_FCNFG_RDCOLLIE(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_RDCOLLIE_MASK, FTFE_FCNFG_RDCOLLIE(value)))
+#define FTFE_BWR_FCNFG_RDCOLLIE(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RDCOLLIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field CCIE[7] (RW)
+ *
+ * The CCIE bit controls interrupt generation when an FTFE command completes.
+ *
+ * Values:
+ * - 0b0 - Command complete interrupt disabled
+ * - 0b1 - Command complete interrupt enabled. An interrupt request is generated
+ *     whenever the FSTAT[CCIF] flag is set.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_CCIE field. */
+#define FTFE_RD_FCNFG_CCIE(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_CCIE_MASK) >> FTFE_FCNFG_CCIE_SHIFT)
+#define FTFE_BRD_FCNFG_CCIE(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_CCIE_SHIFT))
+
+/*! @brief Set the CCIE field to a new value. */
+#define FTFE_WR_FCNFG_CCIE(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_CCIE_MASK, FTFE_FCNFG_CCIE(value)))
+#define FTFE_BWR_FCNFG_CCIE(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_CCIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FSEC - Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FSEC - Flash Security Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This read-only register holds all bits associated with the security of the
+ * MCU and FTFE module. During the reset sequence, the register is loaded with the
+ * contents of the flash security byte in the Flash Configuration Field located
+ * in program flash memory. The Flash basis for the values is signified by X in
+ * the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FSEC register
+ */
+/*@{*/
+#define FTFE_RD_FSEC(base)       (FTFE_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FSEC bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSEC, field SEC[1:0] (RO)
+ *
+ * These bits define the security state of the MCU. In the secure state, the MCU
+ * limits access to FTFE module resources. The limitations are defined per
+ * device and are detailed in the Chip Configuration details. If the FTFE module is
+ * unsecured using backdoor key access, the SEC bits are forced to 10b.
+ *
+ * Values:
+ * - 0b00 - MCU security status is secure
+ * - 0b01 - MCU security status is secure
+ * - 0b10 - MCU security status is unsecure (The standard shipping condition of
+ *     the FTFE is unsecure.)
+ * - 0b11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_SEC field. */
+#define FTFE_RD_FSEC_SEC(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_SEC_MASK) >> FTFE_FSEC_SEC_SHIFT)
+#define FTFE_BRD_FSEC_SEC(base) (FTFE_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field FSLACC[3:2] (RO)
+ *
+ * These bits enable or disable access to the flash memory contents during
+ * returned part failure analysis at Freescale. When SEC is secure and FSLACC is
+ * denied, access to the program flash contents is denied and any failure analysis
+ * performed by Freescale factory test must begin with a full erase to unsecure the
+ * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is
+ * granted), Freescale factory testing has visibility of the current flash
+ * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to
+ * secure. When the SEC field is set to unsecure, the FSLACC setting does not
+ * matter.
+ *
+ * Values:
+ * - 0b00 - Freescale factory access granted
+ * - 0b01 - Freescale factory access denied
+ * - 0b10 - Freescale factory access denied
+ * - 0b11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_FSLACC field. */
+#define FTFE_RD_FSEC_FSLACC(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_FSLACC_MASK) >> FTFE_FSEC_FSLACC_SHIFT)
+#define FTFE_BRD_FSEC_FSLACC(base) (FTFE_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field MEEN[5:4] (RO)
+ *
+ * Enables and disables mass erase capability of the FTFE module. The state of
+ * the MEEN bits is only relevant when the SEC bits are set to secure outside of
+ * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does
+ * not matter.
+ *
+ * Values:
+ * - 0b00 - Mass erase is enabled
+ * - 0b01 - Mass erase is enabled
+ * - 0b10 - Mass erase is disabled
+ * - 0b11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_MEEN field. */
+#define FTFE_RD_FSEC_MEEN(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_MEEN_MASK) >> FTFE_FSEC_MEEN_SHIFT)
+#define FTFE_BRD_FSEC_MEEN(base) (FTFE_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field KEYEN[7:6] (RO)
+ *
+ * These bits enable and disable backdoor key access to the FTFE module.
+ *
+ * Values:
+ * - 0b00 - Backdoor key access disabled
+ * - 0b01 - Backdoor key access disabled (preferred KEYEN state to disable
+ *     backdoor key access)
+ * - 0b10 - Backdoor key access enabled
+ * - 0b11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_KEYEN field. */
+#define FTFE_RD_FSEC_KEYEN(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_KEYEN_MASK) >> FTFE_FSEC_KEYEN_SHIFT)
+#define FTFE_BRD_FSEC_KEYEN(base) (FTFE_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FOPT - Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FOPT - Flash Option Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * The flash option register allows the MCU to customize its operations by
+ * examining the state of these read-only bits, which are loaded from NVM at reset.
+ * The function of the bits is defined in the device's Chip Configuration details.
+ * All bits in the register are read-only. During the reset sequence, the
+ * register is loaded from the flash nonvolatile option byte in the Flash Configuration
+ * Field located in program flash memory. The flash basis for the values is
+ * signified by X in the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FOPT register
+ */
+/*@{*/
+#define FTFE_RD_FOPT(base)       (FTFE_FOPT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB3 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB3 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB3 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB3(base)     (FTFE_FCCOB3_REG(base))
+#define FTFE_WR_FCCOB3(base, value) (FTFE_FCCOB3_REG(base) = (value))
+#define FTFE_RMW_FCCOB3(base, mask, value) (FTFE_WR_FCCOB3(base, (FTFE_RD_FCCOB3(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) |  (value)))
+#define FTFE_CLR_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) & ~(value)))
+#define FTFE_TOG_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB2 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB2 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB2 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB2(base)     (FTFE_FCCOB2_REG(base))
+#define FTFE_WR_FCCOB2(base, value) (FTFE_FCCOB2_REG(base) = (value))
+#define FTFE_RMW_FCCOB2(base, mask, value) (FTFE_WR_FCCOB2(base, (FTFE_RD_FCCOB2(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) |  (value)))
+#define FTFE_CLR_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) & ~(value)))
+#define FTFE_TOG_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB1 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB1 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB1 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB1(base)     (FTFE_FCCOB1_REG(base))
+#define FTFE_WR_FCCOB1(base, value) (FTFE_FCCOB1_REG(base) = (value))
+#define FTFE_RMW_FCCOB1(base, mask, value) (FTFE_WR_FCCOB1(base, (FTFE_RD_FCCOB1(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) |  (value)))
+#define FTFE_CLR_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) & ~(value)))
+#define FTFE_TOG_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB0 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB0 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB0 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB0(base)     (FTFE_FCCOB0_REG(base))
+#define FTFE_WR_FCCOB0(base, value) (FTFE_FCCOB0_REG(base) = (value))
+#define FTFE_RMW_FCCOB0(base, mask, value) (FTFE_WR_FCCOB0(base, (FTFE_RD_FCCOB0(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) |  (value)))
+#define FTFE_CLR_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) & ~(value)))
+#define FTFE_TOG_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB7 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB7 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB7 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB7(base)     (FTFE_FCCOB7_REG(base))
+#define FTFE_WR_FCCOB7(base, value) (FTFE_FCCOB7_REG(base) = (value))
+#define FTFE_RMW_FCCOB7(base, mask, value) (FTFE_WR_FCCOB7(base, (FTFE_RD_FCCOB7(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) |  (value)))
+#define FTFE_CLR_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) & ~(value)))
+#define FTFE_TOG_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB6 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB6 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB6 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB6(base)     (FTFE_FCCOB6_REG(base))
+#define FTFE_WR_FCCOB6(base, value) (FTFE_FCCOB6_REG(base) = (value))
+#define FTFE_RMW_FCCOB6(base, mask, value) (FTFE_WR_FCCOB6(base, (FTFE_RD_FCCOB6(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) |  (value)))
+#define FTFE_CLR_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) & ~(value)))
+#define FTFE_TOG_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB5 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB5 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB5 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB5(base)     (FTFE_FCCOB5_REG(base))
+#define FTFE_WR_FCCOB5(base, value) (FTFE_FCCOB5_REG(base) = (value))
+#define FTFE_RMW_FCCOB5(base, mask, value) (FTFE_WR_FCCOB5(base, (FTFE_RD_FCCOB5(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) |  (value)))
+#define FTFE_CLR_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) & ~(value)))
+#define FTFE_TOG_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB4 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB4 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB4 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB4(base)     (FTFE_FCCOB4_REG(base))
+#define FTFE_WR_FCCOB4(base, value) (FTFE_FCCOB4_REG(base) = (value))
+#define FTFE_RMW_FCCOB4(base, mask, value) (FTFE_WR_FCCOB4(base, (FTFE_RD_FCCOB4(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) |  (value)))
+#define FTFE_CLR_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) & ~(value)))
+#define FTFE_TOG_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOBB - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOBB - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBB register
+ */
+/*@{*/
+#define FTFE_RD_FCCOBB(base)     (FTFE_FCCOBB_REG(base))
+#define FTFE_WR_FCCOBB(base, value) (FTFE_FCCOBB_REG(base) = (value))
+#define FTFE_RMW_FCCOBB(base, mask, value) (FTFE_WR_FCCOBB(base, (FTFE_RD_FCCOBB(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) |  (value)))
+#define FTFE_CLR_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) & ~(value)))
+#define FTFE_TOG_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOBA - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOBA - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBA register
+ */
+/*@{*/
+#define FTFE_RD_FCCOBA(base)     (FTFE_FCCOBA_REG(base))
+#define FTFE_WR_FCCOBA(base, value) (FTFE_FCCOBA_REG(base) = (value))
+#define FTFE_RMW_FCCOBA(base, mask, value) (FTFE_WR_FCCOBA(base, (FTFE_RD_FCCOBA(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) |  (value)))
+#define FTFE_CLR_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) & ~(value)))
+#define FTFE_TOG_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB9 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB9 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB9 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB9(base)     (FTFE_FCCOB9_REG(base))
+#define FTFE_WR_FCCOB9(base, value) (FTFE_FCCOB9_REG(base) = (value))
+#define FTFE_RMW_FCCOB9(base, mask, value) (FTFE_WR_FCCOB9(base, (FTFE_RD_FCCOB9(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) |  (value)))
+#define FTFE_CLR_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) & ~(value)))
+#define FTFE_TOG_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB8 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB8 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB8 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB8(base)     (FTFE_FCCOB8_REG(base))
+#define FTFE_WR_FCCOB8(base, value) (FTFE_FCCOB8_REG(base) = (value))
+#define FTFE_RMW_FCCOB8(base, mask, value) (FTFE_WR_FCCOB8(base, (FTFE_RD_FCCOB8(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) |  (value)))
+#define FTFE_CLR_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) & ~(value)))
+#define FTFE_TOG_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT3 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT3 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT3 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT3(base)     (FTFE_FPROT3_REG(base))
+#define FTFE_WR_FPROT3(base, value) (FTFE_FPROT3_REG(base) = (value))
+#define FTFE_RMW_FPROT3(base, mask, value) (FTFE_WR_FPROT3(base, (FTFE_RD_FPROT3(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) |  (value)))
+#define FTFE_CLR_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) & ~(value)))
+#define FTFE_TOG_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT2 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT2 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT2 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT2(base)     (FTFE_FPROT2_REG(base))
+#define FTFE_WR_FPROT2(base, value) (FTFE_FPROT2_REG(base) = (value))
+#define FTFE_RMW_FPROT2(base, mask, value) (FTFE_WR_FPROT2(base, (FTFE_RD_FPROT2(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) |  (value)))
+#define FTFE_CLR_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) & ~(value)))
+#define FTFE_TOG_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT1 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT1 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT1 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT1(base)     (FTFE_FPROT1_REG(base))
+#define FTFE_WR_FPROT1(base, value) (FTFE_FPROT1_REG(base) = (value))
+#define FTFE_RMW_FPROT1(base, mask, value) (FTFE_WR_FPROT1(base, (FTFE_RD_FPROT1(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) |  (value)))
+#define FTFE_CLR_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) & ~(value)))
+#define FTFE_TOG_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT0 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT0 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT0 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT0(base)     (FTFE_FPROT0_REG(base))
+#define FTFE_WR_FPROT0(base, value) (FTFE_FPROT0_REG(base) = (value))
+#define FTFE_RMW_FPROT0(base, mask, value) (FTFE_WR_FPROT0(base, (FTFE_RD_FPROT0(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) |  (value)))
+#define FTFE_CLR_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) & ~(value)))
+#define FTFE_TOG_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FEPROT - EEPROM Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FEPROT - EEPROM Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of
+ * the FlexRAM are protected against program and erase operations. Protected
+ * EEPROM regions cannot have their content changed by writing to it. Unprotected
+ * regions can be changed by writing to the FlexRAM. For devices with program flash
+ * only: This register is reserved and not used.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FEPROT register
+ */
+/*@{*/
+#define FTFE_RD_FEPROT(base)     (FTFE_FEPROT_REG(base))
+#define FTFE_WR_FEPROT(base, value) (FTFE_FEPROT_REG(base) = (value))
+#define FTFE_RMW_FEPROT(base, mask, value) (FTFE_WR_FEPROT(base, (FTFE_RD_FEPROT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) |  (value)))
+#define FTFE_CLR_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) & ~(value)))
+#define FTFE_TOG_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FDPROT - Data Flash Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FDPROT - Data Flash Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FDPROT register defines which data flash regions are protected against
+ * program and erase operations. Protected Flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by both program and erase
+ * operations.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FDPROT register
+ */
+/*@{*/
+#define FTFE_RD_FDPROT(base)     (FTFE_FDPROT_REG(base))
+#define FTFE_WR_FDPROT(base, value) (FTFE_FDPROT_REG(base) = (value))
+#define FTFE_RMW_FDPROT(base, mask, value) (FTFE_WR_FDPROT(base, (FTFE_RD_FDPROT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) |  (value)))
+#define FTFE_CLR_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) & ~(value)))
+#define FTFE_TOG_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FTM
+ *
+ * FlexTimer Module
+ *
+ * Registers defined in this header file:
+ * - FTM_SC - Status And Control
+ * - FTM_CNT - Counter
+ * - FTM_MOD - Modulo
+ * - FTM_CnSC - Channel (n) Status And Control
+ * - FTM_CnV - Channel (n) Value
+ * - FTM_CNTIN - Counter Initial Value
+ * - FTM_STATUS - Capture And Compare Status
+ * - FTM_MODE - Features Mode Selection
+ * - FTM_SYNC - Synchronization
+ * - FTM_OUTINIT - Initial State For Channels Output
+ * - FTM_OUTMASK - Output Mask
+ * - FTM_COMBINE - Function For Linked Channels
+ * - FTM_DEADTIME - Deadtime Insertion Control
+ * - FTM_EXTTRIG - FTM External Trigger
+ * - FTM_POL - Channels Polarity
+ * - FTM_FMS - Fault Mode Status
+ * - FTM_FILTER - Input Capture Filter Control
+ * - FTM_FLTCTRL - Fault Control
+ * - FTM_QDCTRL - Quadrature Decoder Control And Status
+ * - FTM_CONF - Configuration
+ * - FTM_FLTPOL - FTM Fault Input Polarity
+ * - FTM_SYNCONF - Synchronization Configuration
+ * - FTM_INVCTRL - FTM Inverting Control
+ * - FTM_SWOCTRL - FTM Software Output Control
+ * - FTM_PWMLOAD - FTM PWM Load
+ */
+
+#define FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
+#define FTM0_IDX (0U) /*!< Instance number for FTM0. */
+#define FTM1_IDX (1U) /*!< Instance number for FTM1. */
+#define FTM2_IDX (2U) /*!< Instance number for FTM2. */
+#define FTM3_IDX (3U) /*!< Instance number for FTM3. */
+
+/*******************************************************************************
+ * FTM_SC - Status And Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SC - Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * SC contains the overflow status flag and control bits used to configure the
+ * interrupt enable, FTM configuration, clock source, and prescaler factor. These
+ * controls relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SC register
+ */
+/*@{*/
+#define FTM_RD_SC(base)          (FTM_SC_REG(base))
+#define FTM_WR_SC(base, value)   (FTM_SC_REG(base) = (value))
+#define FTM_RMW_SC(base, mask, value) (FTM_WR_SC(base, (FTM_RD_SC(base) & ~(mask)) | (value)))
+#define FTM_SET_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) |  (value)))
+#define FTM_CLR_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) & ~(value)))
+#define FTM_TOG_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SC bitfields
+ */
+
+/*!
+ * @name Register FTM_SC, field PS[2:0] (RW)
+ *
+ * Selects one of 8 division factors for the clock source selected by CLKS. The
+ * new prescaler factor affects the clock source on the next system clock cycle
+ * after the new value is updated into the register bits. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b000 - Divide by 1
+ * - 0b001 - Divide by 2
+ * - 0b010 - Divide by 4
+ * - 0b011 - Divide by 8
+ * - 0b100 - Divide by 16
+ * - 0b101 - Divide by 32
+ * - 0b110 - Divide by 64
+ * - 0b111 - Divide by 128
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_PS field. */
+#define FTM_RD_SC_PS(base)   ((FTM_SC_REG(base) & FTM_SC_PS_MASK) >> FTM_SC_PS_SHIFT)
+#define FTM_BRD_SC_PS(base)  (FTM_RD_SC_PS(base))
+
+/*! @brief Set the PS field to a new value. */
+#define FTM_WR_SC_PS(base, value) (FTM_RMW_SC(base, FTM_SC_PS_MASK, FTM_SC_PS(value)))
+#define FTM_BWR_SC_PS(base, value) (FTM_WR_SC_PS(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field CLKS[4:3] (RW)
+ *
+ * Selects one of the three FTM counter clock sources. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b00 - No clock selected. This in effect disables the FTM counter.
+ * - 0b01 - System clock
+ * - 0b10 - Fixed frequency clock
+ * - 0b11 - External clock
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_CLKS field. */
+#define FTM_RD_SC_CLKS(base) ((FTM_SC_REG(base) & FTM_SC_CLKS_MASK) >> FTM_SC_CLKS_SHIFT)
+#define FTM_BRD_SC_CLKS(base) (FTM_RD_SC_CLKS(base))
+
+/*! @brief Set the CLKS field to a new value. */
+#define FTM_WR_SC_CLKS(base, value) (FTM_RMW_SC(base, FTM_SC_CLKS_MASK, FTM_SC_CLKS(value)))
+#define FTM_BWR_SC_CLKS(base, value) (FTM_WR_SC_CLKS(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field CPWMS[5] (RW)
+ *
+ * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
+ * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ *
+ * Values:
+ * - 0b0 - FTM counter operates in Up Counting mode.
+ * - 0b1 - FTM counter operates in Up-Down Counting mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_CPWMS field. */
+#define FTM_RD_SC_CPWMS(base) ((FTM_SC_REG(base) & FTM_SC_CPWMS_MASK) >> FTM_SC_CPWMS_SHIFT)
+#define FTM_BRD_SC_CPWMS(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_CPWMS_SHIFT))
+
+/*! @brief Set the CPWMS field to a new value. */
+#define FTM_WR_SC_CPWMS(base, value) (FTM_RMW_SC(base, FTM_SC_CPWMS_MASK, FTM_SC_CPWMS(value)))
+#define FTM_BWR_SC_CPWMS(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_CPWMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field TOIE[6] (RW)
+ *
+ * Enables FTM overflow interrupts.
+ *
+ * Values:
+ * - 0b0 - Disable TOF interrupts. Use software polling.
+ * - 0b1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_TOIE field. */
+#define FTM_RD_SC_TOIE(base) ((FTM_SC_REG(base) & FTM_SC_TOIE_MASK) >> FTM_SC_TOIE_SHIFT)
+#define FTM_BRD_SC_TOIE(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOIE_SHIFT))
+
+/*! @brief Set the TOIE field to a new value. */
+#define FTM_WR_SC_TOIE(base, value) (FTM_RMW_SC(base, FTM_SC_TOIE_MASK, FTM_SC_TOIE(value)))
+#define FTM_BWR_SC_TOIE(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field TOF[7] (ROWZ)
+ *
+ * Set by hardware when the FTM counter passes the value in the MOD register.
+ * The TOF bit is cleared by reading the SC register while TOF is set and then
+ * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
+ * occurs between the read and write operations, the write operation has no
+ * effect; therefore, TOF remains set indicating an overflow has occurred. In this
+ * case, a TOF interrupt request is not lost due to the clearing sequence for a
+ * previous TOF.
+ *
+ * Values:
+ * - 0b0 - FTM counter has not overflowed.
+ * - 0b1 - FTM counter has overflowed.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_TOF field. */
+#define FTM_RD_SC_TOF(base)  ((FTM_SC_REG(base) & FTM_SC_TOF_MASK) >> FTM_SC_TOF_SHIFT)
+#define FTM_BRD_SC_TOF(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOF_SHIFT))
+
+/*! @brief Set the TOF field to a new value. */
+#define FTM_WR_SC_TOF(base, value) (FTM_RMW_SC(base, FTM_SC_TOF_MASK, FTM_SC_TOF(value)))
+#define FTM_BWR_SC_TOF(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CNT - Counter
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CNT - Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CNT register contains the FTM counter value. Reset clears the CNT
+ * register. Writing any value to COUNT updates the counter with its initial value,
+ * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
+ * may read.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CNT register
+ */
+/*@{*/
+#define FTM_RD_CNT(base)         (FTM_CNT_REG(base))
+#define FTM_WR_CNT(base, value)  (FTM_CNT_REG(base) = (value))
+#define FTM_RMW_CNT(base, mask, value) (FTM_WR_CNT(base, (FTM_RD_CNT(base) & ~(mask)) | (value)))
+#define FTM_SET_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) |  (value)))
+#define FTM_CLR_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) & ~(value)))
+#define FTM_TOG_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CNT bitfields
+ */
+
+/*!
+ * @name Register FTM_CNT, field COUNT[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CNT_COUNT field. */
+#define FTM_RD_CNT_COUNT(base) ((FTM_CNT_REG(base) & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT)
+#define FTM_BRD_CNT_COUNT(base) (FTM_RD_CNT_COUNT(base))
+
+/*! @brief Set the COUNT field to a new value. */
+#define FTM_WR_CNT_COUNT(base, value) (FTM_RMW_CNT(base, FTM_CNT_COUNT_MASK, FTM_CNT_COUNT(value)))
+#define FTM_BWR_CNT_COUNT(base, value) (FTM_WR_CNT_COUNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_MOD - Modulo
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_MOD - Modulo (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Modulo register contains the modulo value for the FTM counter. After the
+ * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
+ * the next clock, and the next value of FTM counter depends on the selected
+ * counting method; see Counter. Writing to the MOD register latches the value into a
+ * buffer. The MOD register is updated with the value of its write buffer
+ * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
+ * mechanism may be manually reset by writing to the SC register whether BDM is
+ * active or not. Initialize the FTM counter, by writing to CNT, before writing
+ * to the MOD register to avoid confusion about when the first counter overflow
+ * will occur.
+ */
+/*!
+ * @name Constants and macros for entire FTM_MOD register
+ */
+/*@{*/
+#define FTM_RD_MOD(base)         (FTM_MOD_REG(base))
+#define FTM_WR_MOD(base, value)  (FTM_MOD_REG(base) = (value))
+#define FTM_RMW_MOD(base, mask, value) (FTM_WR_MOD(base, (FTM_RD_MOD(base) & ~(mask)) | (value)))
+#define FTM_SET_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) |  (value)))
+#define FTM_CLR_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) & ~(value)))
+#define FTM_TOG_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_MOD bitfields
+ */
+
+/*!
+ * @name Register FTM_MOD, field MOD[15:0] (RW)
+ *
+ * Modulo Value
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MOD_MOD field. */
+#define FTM_RD_MOD_MOD(base) ((FTM_MOD_REG(base) & FTM_MOD_MOD_MASK) >> FTM_MOD_MOD_SHIFT)
+#define FTM_BRD_MOD_MOD(base) (FTM_RD_MOD_MOD(base))
+
+/*! @brief Set the MOD field to a new value. */
+#define FTM_WR_MOD_MOD(base, value) (FTM_RMW_MOD(base, FTM_MOD_MOD_MASK, FTM_MOD_MOD(value)))
+#define FTM_BWR_MOD_MOD(base, value) (FTM_WR_MOD_MOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CnSC - Channel (n) Status And Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CnSC - Channel (n) Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CnSC contains the channel-interrupt-status flag and control bits used to
+ * configure the interrupt enable, channel configuration, and pin function. Mode,
+ * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
+ * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
+ * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
+ * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
+ * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
+ * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
+ * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
+ * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
+ * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
+ * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
+ * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
+ * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
+ * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
+ * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
+ * Enabled Rising and falling edges
+ */
+/*!
+ * @name Constants and macros for entire FTM_CnSC register
+ */
+/*@{*/
+#define FTM_RD_CnSC(base, index) (FTM_CnSC_REG(base, index))
+#define FTM_WR_CnSC(base, index, value) (FTM_CnSC_REG(base, index) = (value))
+#define FTM_RMW_CnSC(base, index, mask, value) (FTM_WR_CnSC(base, index, (FTM_RD_CnSC(base, index) & ~(mask)) | (value)))
+#define FTM_SET_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) |  (value)))
+#define FTM_CLR_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) & ~(value)))
+#define FTM_TOG_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CnSC bitfields
+ */
+
+/*!
+ * @name Register FTM_CnSC, field DMA[0] (RW)
+ *
+ * Enables DMA transfers for the channel.
+ *
+ * Values:
+ * - 0b0 - Disable DMA transfers.
+ * - 0b1 - Enable DMA transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_DMA field. */
+#define FTM_RD_CnSC_DMA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_DMA_MASK) >> FTM_CnSC_DMA_SHIFT)
+#define FTM_BRD_CnSC_DMA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define FTM_WR_CnSC_DMA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_DMA_MASK, FTM_CnSC_DMA(value)))
+#define FTM_BWR_CnSC_DMA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_DMA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field ELSA[2] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_ELSA field. */
+#define FTM_RD_CnSC_ELSA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_ELSA_MASK) >> FTM_CnSC_ELSA_SHIFT)
+#define FTM_BRD_CnSC_ELSA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSA_SHIFT))
+
+/*! @brief Set the ELSA field to a new value. */
+#define FTM_WR_CnSC_ELSA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_ELSA_MASK, FTM_CnSC_ELSA(value)))
+#define FTM_BWR_CnSC_ELSA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field ELSB[3] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_ELSB field. */
+#define FTM_RD_CnSC_ELSB(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_ELSB_MASK) >> FTM_CnSC_ELSB_SHIFT)
+#define FTM_BRD_CnSC_ELSB(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSB_SHIFT))
+
+/*! @brief Set the ELSB field to a new value. */
+#define FTM_WR_CnSC_ELSB(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_ELSB_MASK, FTM_CnSC_ELSB(value)))
+#define FTM_BWR_CnSC_ELSB(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field MSA[4] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_MSA field. */
+#define FTM_RD_CnSC_MSA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_MSA_MASK) >> FTM_CnSC_MSA_SHIFT)
+#define FTM_BRD_CnSC_MSA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSA_SHIFT))
+
+/*! @brief Set the MSA field to a new value. */
+#define FTM_WR_CnSC_MSA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_MSA_MASK, FTM_CnSC_MSA(value)))
+#define FTM_BWR_CnSC_MSA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field MSB[5] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_MSB field. */
+#define FTM_RD_CnSC_MSB(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_MSB_MASK) >> FTM_CnSC_MSB_SHIFT)
+#define FTM_BRD_CnSC_MSB(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSB_SHIFT))
+
+/*! @brief Set the MSB field to a new value. */
+#define FTM_WR_CnSC_MSB(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_MSB_MASK, FTM_CnSC_MSB(value)))
+#define FTM_BWR_CnSC_MSB(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field CHIE[6] (RW)
+ *
+ * Enables channel interrupts.
+ *
+ * Values:
+ * - 0b0 - Disable channel interrupts. Use software polling.
+ * - 0b1 - Enable channel interrupts.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_CHIE field. */
+#define FTM_RD_CnSC_CHIE(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_CHIE_MASK) >> FTM_CnSC_CHIE_SHIFT)
+#define FTM_BRD_CnSC_CHIE(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHIE_SHIFT))
+
+/*! @brief Set the CHIE field to a new value. */
+#define FTM_WR_CnSC_CHIE(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_CHIE_MASK, FTM_CnSC_CHIE(value)))
+#define FTM_BWR_CnSC_CHIE(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field CHF[7] (ROWZ)
+ *
+ * Set by hardware when an event occurs on the channel. CHF is cleared by
+ * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
+ * Writing a 1 to CHF has no effect. If another event occurs between the read and
+ * write operations, the write operation has no effect; therefore, CHF remains set
+ * indicating an event has occurred. In this case a CHF interrupt request is not
+ * lost due to the clearing sequence for a previous CHF.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_CHF field. */
+#define FTM_RD_CnSC_CHF(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_CHF_MASK) >> FTM_CnSC_CHF_SHIFT)
+#define FTM_BRD_CnSC_CHF(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHF_SHIFT))
+
+/*! @brief Set the CHF field to a new value. */
+#define FTM_WR_CnSC_CHF(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_CHF_MASK, FTM_CnSC_CHF(value)))
+#define FTM_BWR_CnSC_CHF(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CnV - Channel (n) Value
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CnV - Channel (n) Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the captured FTM counter value for the input modes or
+ * the match value for the output modes. In Input Capture, Capture Test, and
+ * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
+ * writing to a CnV register latches the value into a buffer. A CnV register is
+ * updated with the value of its write buffer according to Registers updated from
+ * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
+ * reset by writing to the CnSC register whether BDM mode is active or not.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CnV register
+ */
+/*@{*/
+#define FTM_RD_CnV(base, index)  (FTM_CnV_REG(base, index))
+#define FTM_WR_CnV(base, index, value) (FTM_CnV_REG(base, index) = (value))
+#define FTM_RMW_CnV(base, index, mask, value) (FTM_WR_CnV(base, index, (FTM_RD_CnV(base, index) & ~(mask)) | (value)))
+#define FTM_SET_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) |  (value)))
+#define FTM_CLR_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) & ~(value)))
+#define FTM_TOG_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CnV bitfields
+ */
+
+/*!
+ * @name Register FTM_CnV, field VAL[15:0] (RW)
+ *
+ * Captured FTM counter value of the input modes or the match value for the
+ * output modes
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnV_VAL field. */
+#define FTM_RD_CnV_VAL(base, index) ((FTM_CnV_REG(base, index) & FTM_CnV_VAL_MASK) >> FTM_CnV_VAL_SHIFT)
+#define FTM_BRD_CnV_VAL(base, index) (FTM_RD_CnV_VAL(base, index))
+
+/*! @brief Set the VAL field to a new value. */
+#define FTM_WR_CnV_VAL(base, index, value) (FTM_RMW_CnV(base, index, FTM_CnV_VAL_MASK, FTM_CnV_VAL(value)))
+#define FTM_BWR_CnV_VAL(base, index, value) (FTM_WR_CnV_VAL(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CNTIN - Counter Initial Value
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CNTIN - Counter Initial Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Counter Initial Value register contains the initial value for the FTM
+ * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
+ * register is updated with the value of its write buffer according to Registers
+ * updated from write buffers. When the FTM clock is initially selected, by
+ * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
+ * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
+ * write the new value to the the CNTIN register and then initialize the FTM
+ * counter by writing any value to the CNT register.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CNTIN register
+ */
+/*@{*/
+#define FTM_RD_CNTIN(base)       (FTM_CNTIN_REG(base))
+#define FTM_WR_CNTIN(base, value) (FTM_CNTIN_REG(base) = (value))
+#define FTM_RMW_CNTIN(base, mask, value) (FTM_WR_CNTIN(base, (FTM_RD_CNTIN(base) & ~(mask)) | (value)))
+#define FTM_SET_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) |  (value)))
+#define FTM_CLR_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) & ~(value)))
+#define FTM_TOG_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CNTIN bitfields
+ */
+
+/*!
+ * @name Register FTM_CNTIN, field INIT[15:0] (RW)
+ *
+ * Initial Value Of The FTM Counter
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CNTIN_INIT field. */
+#define FTM_RD_CNTIN_INIT(base) ((FTM_CNTIN_REG(base) & FTM_CNTIN_INIT_MASK) >> FTM_CNTIN_INIT_SHIFT)
+#define FTM_BRD_CNTIN_INIT(base) (FTM_RD_CNTIN_INIT(base))
+
+/*! @brief Set the INIT field to a new value. */
+#define FTM_WR_CNTIN_INIT(base, value) (FTM_RMW_CNTIN(base, FTM_CNTIN_INIT_MASK, FTM_CNTIN_INIT(value)))
+#define FTM_BWR_CNTIN_INIT(base, value) (FTM_WR_CNTIN_INIT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_STATUS - Capture And Compare Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_STATUS - Capture And Compare Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
+ * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
+ * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
+ * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
+ * STATUS. Hardware sets the individual channel flags when an event occurs on the
+ * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
+ * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
+ * occurs between the read and write operations, the write operation has no effect;
+ * therefore, CHnF remains set indicating an event has occurred. In this case, a
+ * CHnF interrupt request is not lost due to the clearing sequence for a previous
+ * CHnF. The STATUS register should be used only in Combine mode.
+ */
+/*!
+ * @name Constants and macros for entire FTM_STATUS register
+ */
+/*@{*/
+#define FTM_RD_STATUS(base)      (FTM_STATUS_REG(base))
+#define FTM_WR_STATUS(base, value) (FTM_STATUS_REG(base) = (value))
+#define FTM_RMW_STATUS(base, mask, value) (FTM_WR_STATUS(base, (FTM_RD_STATUS(base) & ~(mask)) | (value)))
+#define FTM_SET_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) |  (value)))
+#define FTM_CLR_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) & ~(value)))
+#define FTM_TOG_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_STATUS bitfields
+ */
+
+/*!
+ * @name Register FTM_STATUS, field CH0F[0] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH0F field. */
+#define FTM_RD_STATUS_CH0F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH0F_MASK) >> FTM_STATUS_CH0F_SHIFT)
+#define FTM_BRD_STATUS_CH0F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH0F_SHIFT))
+
+/*! @brief Set the CH0F field to a new value. */
+#define FTM_WR_STATUS_CH0F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH0F(value)))
+#define FTM_BWR_STATUS_CH0F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH0F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH1F[1] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH1F field. */
+#define FTM_RD_STATUS_CH1F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH1F_MASK) >> FTM_STATUS_CH1F_SHIFT)
+#define FTM_BRD_STATUS_CH1F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH1F_SHIFT))
+
+/*! @brief Set the CH1F field to a new value. */
+#define FTM_WR_STATUS_CH1F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH1F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH1F(value)))
+#define FTM_BWR_STATUS_CH1F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH1F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH2F[2] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH2F field. */
+#define FTM_RD_STATUS_CH2F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH2F_MASK) >> FTM_STATUS_CH2F_SHIFT)
+#define FTM_BRD_STATUS_CH2F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH2F_SHIFT))
+
+/*! @brief Set the CH2F field to a new value. */
+#define FTM_WR_STATUS_CH2F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH2F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH2F(value)))
+#define FTM_BWR_STATUS_CH2F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH2F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH3F[3] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH3F field. */
+#define FTM_RD_STATUS_CH3F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH3F_MASK) >> FTM_STATUS_CH3F_SHIFT)
+#define FTM_BRD_STATUS_CH3F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH3F_SHIFT))
+
+/*! @brief Set the CH3F field to a new value. */
+#define FTM_WR_STATUS_CH3F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH3F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH3F(value)))
+#define FTM_BWR_STATUS_CH3F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH3F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH4F[4] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH4F field. */
+#define FTM_RD_STATUS_CH4F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH4F_MASK) >> FTM_STATUS_CH4F_SHIFT)
+#define FTM_BRD_STATUS_CH4F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH4F_SHIFT))
+
+/*! @brief Set the CH4F field to a new value. */
+#define FTM_WR_STATUS_CH4F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH4F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH4F(value)))
+#define FTM_BWR_STATUS_CH4F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH4F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH5F[5] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH5F field. */
+#define FTM_RD_STATUS_CH5F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH5F_MASK) >> FTM_STATUS_CH5F_SHIFT)
+#define FTM_BRD_STATUS_CH5F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH5F_SHIFT))
+
+/*! @brief Set the CH5F field to a new value. */
+#define FTM_WR_STATUS_CH5F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH5F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH5F(value)))
+#define FTM_BWR_STATUS_CH5F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH5F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH6F[6] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH6F field. */
+#define FTM_RD_STATUS_CH6F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH6F_MASK) >> FTM_STATUS_CH6F_SHIFT)
+#define FTM_BRD_STATUS_CH6F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH6F_SHIFT))
+
+/*! @brief Set the CH6F field to a new value. */
+#define FTM_WR_STATUS_CH6F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH6F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH6F(value)))
+#define FTM_BWR_STATUS_CH6F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH6F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH7F[7] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH7F field. */
+#define FTM_RD_STATUS_CH7F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH7F_MASK) >> FTM_STATUS_CH7F_SHIFT)
+#define FTM_BRD_STATUS_CH7F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH7F_SHIFT))
+
+/*! @brief Set the CH7F field to a new value. */
+#define FTM_WR_STATUS_CH7F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH7F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK), FTM_STATUS_CH7F(value)))
+#define FTM_BWR_STATUS_CH7F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH7F_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_MODE - Features Mode Selection
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_MODE - Features Mode Selection (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * This register contains the global enable bit for FTM-specific features and
+ * the control bits used to configure: Fault control mode and interrupt Capture
+ * Test mode PWM synchronization Write protection Channel output initialization
+ * These controls relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire FTM_MODE register
+ */
+/*@{*/
+#define FTM_RD_MODE(base)        (FTM_MODE_REG(base))
+#define FTM_WR_MODE(base, value) (FTM_MODE_REG(base) = (value))
+#define FTM_RMW_MODE(base, mask, value) (FTM_WR_MODE(base, (FTM_RD_MODE(base) & ~(mask)) | (value)))
+#define FTM_SET_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) |  (value)))
+#define FTM_CLR_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) & ~(value)))
+#define FTM_TOG_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_MODE bitfields
+ */
+
+/*!
+ * @name Register FTM_MODE, field FTMEN[0] (RW)
+ *
+ * This field is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Only the TPM-compatible registers (first set of registers) can be
+ *     used without any restriction. Do not use the FTM-specific registers.
+ * - 0b1 - All registers including the FTM-specific registers (second set of
+ *     registers) are available for use with no restrictions.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FTMEN field. */
+#define FTM_RD_MODE_FTMEN(base) ((FTM_MODE_REG(base) & FTM_MODE_FTMEN_MASK) >> FTM_MODE_FTMEN_SHIFT)
+#define FTM_BRD_MODE_FTMEN(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FTMEN_SHIFT))
+
+/*! @brief Set the FTMEN field to a new value. */
+#define FTM_WR_MODE_FTMEN(base, value) (FTM_RMW_MODE(base, FTM_MODE_FTMEN_MASK, FTM_MODE_FTMEN(value)))
+#define FTM_BWR_MODE_FTMEN(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FTMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field INIT[1] (RW)
+ *
+ * When a 1 is written to INIT bit the channels output is initialized according
+ * to the state of their corresponding bit in the OUTINIT register. Writing a 0
+ * to INIT bit has no effect. The INIT bit is always read as 0.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_INIT field. */
+#define FTM_RD_MODE_INIT(base) ((FTM_MODE_REG(base) & FTM_MODE_INIT_MASK) >> FTM_MODE_INIT_SHIFT)
+#define FTM_BRD_MODE_INIT(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_INIT_SHIFT))
+
+/*! @brief Set the INIT field to a new value. */
+#define FTM_WR_MODE_INIT(base, value) (FTM_RMW_MODE(base, FTM_MODE_INIT_MASK, FTM_MODE_INIT(value)))
+#define FTM_BWR_MODE_INIT(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_INIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field WPDIS[2] (RW)
+ *
+ * When write protection is enabled (WPDIS = 0), write protected bits cannot be
+ * written. When write protection is disabled (WPDIS = 1), write protected bits
+ * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
+ * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
+ * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
+ *
+ * Values:
+ * - 0b0 - Write protection is enabled.
+ * - 0b1 - Write protection is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_WPDIS field. */
+#define FTM_RD_MODE_WPDIS(base) ((FTM_MODE_REG(base) & FTM_MODE_WPDIS_MASK) >> FTM_MODE_WPDIS_SHIFT)
+#define FTM_BRD_MODE_WPDIS(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_WPDIS_SHIFT))
+
+/*! @brief Set the WPDIS field to a new value. */
+#define FTM_WR_MODE_WPDIS(base, value) (FTM_RMW_MODE(base, FTM_MODE_WPDIS_MASK, FTM_MODE_WPDIS(value)))
+#define FTM_BWR_MODE_WPDIS(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_WPDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field PWMSYNC[3] (RW)
+ *
+ * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
+ * synchronization. See PWM synchronization. The PWMSYNC bit configures the
+ * synchronization when SYNCMODE is 0.
+ *
+ * Values:
+ * - 0b0 - No restrictions. Software and hardware triggers can be used by MOD,
+ *     CnV, OUTMASK, and FTM counter synchronization.
+ * - 0b1 - Software trigger can only be used by MOD and CnV synchronization, and
+ *     hardware triggers can only be used by OUTMASK and FTM counter
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_PWMSYNC field. */
+#define FTM_RD_MODE_PWMSYNC(base) ((FTM_MODE_REG(base) & FTM_MODE_PWMSYNC_MASK) >> FTM_MODE_PWMSYNC_SHIFT)
+#define FTM_BRD_MODE_PWMSYNC(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_PWMSYNC_SHIFT))
+
+/*! @brief Set the PWMSYNC field to a new value. */
+#define FTM_WR_MODE_PWMSYNC(base, value) (FTM_RMW_MODE(base, FTM_MODE_PWMSYNC_MASK, FTM_MODE_PWMSYNC(value)))
+#define FTM_BWR_MODE_PWMSYNC(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_PWMSYNC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field CAPTEST[4] (RW)
+ *
+ * Enables the capture test mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Capture test mode is disabled.
+ * - 0b1 - Capture test mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_CAPTEST field. */
+#define FTM_RD_MODE_CAPTEST(base) ((FTM_MODE_REG(base) & FTM_MODE_CAPTEST_MASK) >> FTM_MODE_CAPTEST_SHIFT)
+#define FTM_BRD_MODE_CAPTEST(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_CAPTEST_SHIFT))
+
+/*! @brief Set the CAPTEST field to a new value. */
+#define FTM_WR_MODE_CAPTEST(base, value) (FTM_RMW_MODE(base, FTM_MODE_CAPTEST_MASK, FTM_MODE_CAPTEST(value)))
+#define FTM_BWR_MODE_CAPTEST(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_CAPTEST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field FAULTM[6:5] (RW)
+ *
+ * Defines the FTM fault control mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b00 - Fault control is disabled for all channels.
+ * - 0b01 - Fault control is enabled for even channels only (channels 0, 2, 4,
+ *     and 6), and the selected mode is the manual fault clearing.
+ * - 0b10 - Fault control is enabled for all channels, and the selected mode is
+ *     the manual fault clearing.
+ * - 0b11 - Fault control is enabled for all channels, and the selected mode is
+ *     the automatic fault clearing.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FAULTM field. */
+#define FTM_RD_MODE_FAULTM(base) ((FTM_MODE_REG(base) & FTM_MODE_FAULTM_MASK) >> FTM_MODE_FAULTM_SHIFT)
+#define FTM_BRD_MODE_FAULTM(base) (FTM_RD_MODE_FAULTM(base))
+
+/*! @brief Set the FAULTM field to a new value. */
+#define FTM_WR_MODE_FAULTM(base, value) (FTM_RMW_MODE(base, FTM_MODE_FAULTM_MASK, FTM_MODE_FAULTM(value)))
+#define FTM_BWR_MODE_FAULTM(base, value) (FTM_WR_MODE_FAULTM(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field FAULTIE[7] (RW)
+ *
+ * Enables the generation of an interrupt when a fault is detected by FTM and
+ * the FTM fault control is enabled.
+ *
+ * Values:
+ * - 0b0 - Fault control interrupt is disabled.
+ * - 0b1 - Fault control interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FAULTIE field. */
+#define FTM_RD_MODE_FAULTIE(base) ((FTM_MODE_REG(base) & FTM_MODE_FAULTIE_MASK) >> FTM_MODE_FAULTIE_SHIFT)
+#define FTM_BRD_MODE_FAULTIE(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FAULTIE_SHIFT))
+
+/*! @brief Set the FAULTIE field to a new value. */
+#define FTM_WR_MODE_FAULTIE(base, value) (FTM_RMW_MODE(base, FTM_MODE_FAULTIE_MASK, FTM_MODE_FAULTIE(value)))
+#define FTM_BWR_MODE_FAULTIE(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FAULTIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SYNC - Synchronization
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SYNC - Synchronization (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the PWM synchronization. A synchronization event can
+ * perform the synchronized update of MOD, CV, and OUTMASK registers with the
+ * value of their write buffer and the FTM counter initialization. The software
+ * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
+ * potential conflict if used together when SYNCMODE = 0. Use only hardware or
+ * software triggers but not both at the same time, otherwise unpredictable behavior
+ * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
+ * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
+ * all enabled channels simultaneously. The use of the loading point selection
+ * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
+ * bits, is likely to result in unpredictable behavior. The synchronization
+ * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
+ * register) bits. See PWM synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SYNC register
+ */
+/*@{*/
+#define FTM_RD_SYNC(base)        (FTM_SYNC_REG(base))
+#define FTM_WR_SYNC(base, value) (FTM_SYNC_REG(base) = (value))
+#define FTM_RMW_SYNC(base, mask, value) (FTM_WR_SYNC(base, (FTM_RD_SYNC(base) & ~(mask)) | (value)))
+#define FTM_SET_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) |  (value)))
+#define FTM_CLR_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) & ~(value)))
+#define FTM_TOG_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SYNC bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNC, field CNTMIN[0] (RW)
+ *
+ * Selects the minimum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMIN is one, the selected loading point is when the
+ * FTM counter reaches its minimum value (CNTIN register).
+ *
+ * Values:
+ * - 0b0 - The minimum loading point is disabled.
+ * - 0b1 - The minimum loading point is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_CNTMIN field. */
+#define FTM_RD_SYNC_CNTMIN(base) ((FTM_SYNC_REG(base) & FTM_SYNC_CNTMIN_MASK) >> FTM_SYNC_CNTMIN_SHIFT)
+#define FTM_BRD_SYNC_CNTMIN(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMIN_SHIFT))
+
+/*! @brief Set the CNTMIN field to a new value. */
+#define FTM_WR_SYNC_CNTMIN(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_CNTMIN_MASK, FTM_SYNC_CNTMIN(value)))
+#define FTM_BWR_SYNC_CNTMIN(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMIN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field CNTMAX[1] (RW)
+ *
+ * Selects the maximum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
+ * counter reaches its maximum value (MOD register).
+ *
+ * Values:
+ * - 0b0 - The maximum loading point is disabled.
+ * - 0b1 - The maximum loading point is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_CNTMAX field. */
+#define FTM_RD_SYNC_CNTMAX(base) ((FTM_SYNC_REG(base) & FTM_SYNC_CNTMAX_MASK) >> FTM_SYNC_CNTMAX_SHIFT)
+#define FTM_BRD_SYNC_CNTMAX(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMAX_SHIFT))
+
+/*! @brief Set the CNTMAX field to a new value. */
+#define FTM_WR_SYNC_CNTMAX(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_CNTMAX_MASK, FTM_SYNC_CNTMAX(value)))
+#define FTM_BWR_SYNC_CNTMAX(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMAX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field REINIT[2] (RW)
+ *
+ * Determines if the FTM counter is reinitialized when the selected trigger for
+ * the synchronization is detected. The REINIT bit configures the synchronization
+ * when SYNCMODE is zero.
+ *
+ * Values:
+ * - 0b0 - FTM counter continues to count normally.
+ * - 0b1 - FTM counter is updated with its initial value when the selected
+ *     trigger is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_REINIT field. */
+#define FTM_RD_SYNC_REINIT(base) ((FTM_SYNC_REG(base) & FTM_SYNC_REINIT_MASK) >> FTM_SYNC_REINIT_SHIFT)
+#define FTM_BRD_SYNC_REINIT(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_REINIT_SHIFT))
+
+/*! @brief Set the REINIT field to a new value. */
+#define FTM_WR_SYNC_REINIT(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_REINIT_MASK, FTM_SYNC_REINIT(value)))
+#define FTM_BWR_SYNC_REINIT(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_REINIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
+ *
+ * Selects when the OUTMASK register is updated with the value of its buffer.
+ *
+ * Values:
+ * - 0b0 - OUTMASK register is updated with the value of its buffer in all
+ *     rising edges of the system clock.
+ * - 0b1 - OUTMASK register is updated with the value of its buffer only by the
+ *     PWM synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */
+#define FTM_RD_SYNC_SYNCHOM(base) ((FTM_SYNC_REG(base) & FTM_SYNC_SYNCHOM_MASK) >> FTM_SYNC_SYNCHOM_SHIFT)
+#define FTM_BRD_SYNC_SYNCHOM(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SYNCHOM_SHIFT))
+
+/*! @brief Set the SYNCHOM field to a new value. */
+#define FTM_WR_SYNC_SYNCHOM(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_SYNCHOM_MASK, FTM_SYNC_SYNCHOM(value)))
+#define FTM_BWR_SYNC_SYNCHOM(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SYNCHOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG0[4] (RW)
+ *
+ * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
+ * occurs when a rising edge is detected at the trigger 0 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG0 field. */
+#define FTM_RD_SYNC_TRIG0(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG0_MASK) >> FTM_SYNC_TRIG0_SHIFT)
+#define FTM_BRD_SYNC_TRIG0(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG0_SHIFT))
+
+/*! @brief Set the TRIG0 field to a new value. */
+#define FTM_WR_SYNC_TRIG0(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG0_MASK, FTM_SYNC_TRIG0(value)))
+#define FTM_BWR_SYNC_TRIG0(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG1[5] (RW)
+ *
+ * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
+ * happens when a rising edge is detected at the trigger 1 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG1 field. */
+#define FTM_RD_SYNC_TRIG1(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG1_MASK) >> FTM_SYNC_TRIG1_SHIFT)
+#define FTM_BRD_SYNC_TRIG1(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG1_SHIFT))
+
+/*! @brief Set the TRIG1 field to a new value. */
+#define FTM_WR_SYNC_TRIG1(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG1_MASK, FTM_SYNC_TRIG1(value)))
+#define FTM_BWR_SYNC_TRIG1(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG2[6] (RW)
+ *
+ * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
+ * happens when a rising edge is detected at the trigger 2 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG2 field. */
+#define FTM_RD_SYNC_TRIG2(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG2_MASK) >> FTM_SYNC_TRIG2_SHIFT)
+#define FTM_BRD_SYNC_TRIG2(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG2_SHIFT))
+
+/*! @brief Set the TRIG2 field to a new value. */
+#define FTM_WR_SYNC_TRIG2(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG2_MASK, FTM_SYNC_TRIG2(value)))
+#define FTM_BWR_SYNC_TRIG2(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field SWSYNC[7] (RW)
+ *
+ * Selects the software trigger as the PWM synchronization trigger. The software
+ * trigger happens when a 1 is written to SWSYNC bit.
+ *
+ * Values:
+ * - 0b0 - Software trigger is not selected.
+ * - 0b1 - Software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_SWSYNC field. */
+#define FTM_RD_SYNC_SWSYNC(base) ((FTM_SYNC_REG(base) & FTM_SYNC_SWSYNC_MASK) >> FTM_SYNC_SWSYNC_SHIFT)
+#define FTM_BRD_SYNC_SWSYNC(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SWSYNC_SHIFT))
+
+/*! @brief Set the SWSYNC field to a new value. */
+#define FTM_WR_SYNC_SWSYNC(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_SWSYNC_MASK, FTM_SYNC_SWSYNC(value)))
+#define FTM_BWR_SYNC_SWSYNC(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SWSYNC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_OUTINIT - Initial State For Channels Output
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_OUTINIT - Initial State For Channels Output (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire FTM_OUTINIT register
+ */
+/*@{*/
+#define FTM_RD_OUTINIT(base)     (FTM_OUTINIT_REG(base))
+#define FTM_WR_OUTINIT(base, value) (FTM_OUTINIT_REG(base) = (value))
+#define FTM_RMW_OUTINIT(base, mask, value) (FTM_WR_OUTINIT(base, (FTM_RD_OUTINIT(base) & ~(mask)) | (value)))
+#define FTM_SET_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) |  (value)))
+#define FTM_CLR_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) & ~(value)))
+#define FTM_TOG_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_OUTINIT bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */
+#define FTM_RD_OUTINIT_CH0OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH0OI_MASK) >> FTM_OUTINIT_CH0OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH0OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH0OI_SHIFT))
+
+/*! @brief Set the CH0OI field to a new value. */
+#define FTM_WR_OUTINIT_CH0OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH0OI_MASK, FTM_OUTINIT_CH0OI(value)))
+#define FTM_BWR_OUTINIT_CH0OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH0OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */
+#define FTM_RD_OUTINIT_CH1OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH1OI_MASK) >> FTM_OUTINIT_CH1OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH1OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH1OI_SHIFT))
+
+/*! @brief Set the CH1OI field to a new value. */
+#define FTM_WR_OUTINIT_CH1OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH1OI_MASK, FTM_OUTINIT_CH1OI(value)))
+#define FTM_BWR_OUTINIT_CH1OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH1OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */
+#define FTM_RD_OUTINIT_CH2OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH2OI_MASK) >> FTM_OUTINIT_CH2OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH2OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH2OI_SHIFT))
+
+/*! @brief Set the CH2OI field to a new value. */
+#define FTM_WR_OUTINIT_CH2OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH2OI_MASK, FTM_OUTINIT_CH2OI(value)))
+#define FTM_BWR_OUTINIT_CH2OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH2OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */
+#define FTM_RD_OUTINIT_CH3OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH3OI_MASK) >> FTM_OUTINIT_CH3OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH3OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH3OI_SHIFT))
+
+/*! @brief Set the CH3OI field to a new value. */
+#define FTM_WR_OUTINIT_CH3OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH3OI_MASK, FTM_OUTINIT_CH3OI(value)))
+#define FTM_BWR_OUTINIT_CH3OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH3OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */
+#define FTM_RD_OUTINIT_CH4OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH4OI_MASK) >> FTM_OUTINIT_CH4OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH4OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH4OI_SHIFT))
+
+/*! @brief Set the CH4OI field to a new value. */
+#define FTM_WR_OUTINIT_CH4OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH4OI_MASK, FTM_OUTINIT_CH4OI(value)))
+#define FTM_BWR_OUTINIT_CH4OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH4OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */
+#define FTM_RD_OUTINIT_CH5OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH5OI_MASK) >> FTM_OUTINIT_CH5OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH5OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH5OI_SHIFT))
+
+/*! @brief Set the CH5OI field to a new value. */
+#define FTM_WR_OUTINIT_CH5OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH5OI_MASK, FTM_OUTINIT_CH5OI(value)))
+#define FTM_BWR_OUTINIT_CH5OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH5OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */
+#define FTM_RD_OUTINIT_CH6OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH6OI_MASK) >> FTM_OUTINIT_CH6OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH6OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH6OI_SHIFT))
+
+/*! @brief Set the CH6OI field to a new value. */
+#define FTM_WR_OUTINIT_CH6OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH6OI_MASK, FTM_OUTINIT_CH6OI(value)))
+#define FTM_BWR_OUTINIT_CH6OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH6OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */
+#define FTM_RD_OUTINIT_CH7OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH7OI_MASK) >> FTM_OUTINIT_CH7OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH7OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH7OI_SHIFT))
+
+/*! @brief Set the CH7OI field to a new value. */
+#define FTM_WR_OUTINIT_CH7OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH7OI_MASK, FTM_OUTINIT_CH7OI(value)))
+#define FTM_BWR_OUTINIT_CH7OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH7OI_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_OUTMASK - Output Mask
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_OUTMASK - Output Mask (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides a mask for each FTM channel. The mask of a channel
+ * determines if its output responds, that is, it is masked or not, when a match
+ * occurs. This feature is used for BLDC control where the PWM signal is presented
+ * to an electric motor at specific times to provide electronic commutation. Any
+ * write to the OUTMASK register, stores the value in its write buffer. The
+ * register is updated with the value of its write buffer according to PWM
+ * synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_OUTMASK register
+ */
+/*@{*/
+#define FTM_RD_OUTMASK(base)     (FTM_OUTMASK_REG(base))
+#define FTM_WR_OUTMASK(base, value) (FTM_OUTMASK_REG(base) = (value))
+#define FTM_RMW_OUTMASK(base, mask, value) (FTM_WR_OUTMASK(base, (FTM_RD_OUTMASK(base) & ~(mask)) | (value)))
+#define FTM_SET_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) |  (value)))
+#define FTM_CLR_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) & ~(value)))
+#define FTM_TOG_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_OUTMASK bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */
+#define FTM_RD_OUTMASK_CH0OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH0OM_MASK) >> FTM_OUTMASK_CH0OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH0OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH0OM_SHIFT))
+
+/*! @brief Set the CH0OM field to a new value. */
+#define FTM_WR_OUTMASK_CH0OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH0OM_MASK, FTM_OUTMASK_CH0OM(value)))
+#define FTM_BWR_OUTMASK_CH0OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH0OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */
+#define FTM_RD_OUTMASK_CH1OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH1OM_MASK) >> FTM_OUTMASK_CH1OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH1OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH1OM_SHIFT))
+
+/*! @brief Set the CH1OM field to a new value. */
+#define FTM_WR_OUTMASK_CH1OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH1OM_MASK, FTM_OUTMASK_CH1OM(value)))
+#define FTM_BWR_OUTMASK_CH1OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH1OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */
+#define FTM_RD_OUTMASK_CH2OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH2OM_MASK) >> FTM_OUTMASK_CH2OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH2OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH2OM_SHIFT))
+
+/*! @brief Set the CH2OM field to a new value. */
+#define FTM_WR_OUTMASK_CH2OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH2OM_MASK, FTM_OUTMASK_CH2OM(value)))
+#define FTM_BWR_OUTMASK_CH2OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH2OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */
+#define FTM_RD_OUTMASK_CH3OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH3OM_MASK) >> FTM_OUTMASK_CH3OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH3OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH3OM_SHIFT))
+
+/*! @brief Set the CH3OM field to a new value. */
+#define FTM_WR_OUTMASK_CH3OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH3OM_MASK, FTM_OUTMASK_CH3OM(value)))
+#define FTM_BWR_OUTMASK_CH3OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH3OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */
+#define FTM_RD_OUTMASK_CH4OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH4OM_MASK) >> FTM_OUTMASK_CH4OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH4OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH4OM_SHIFT))
+
+/*! @brief Set the CH4OM field to a new value. */
+#define FTM_WR_OUTMASK_CH4OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH4OM_MASK, FTM_OUTMASK_CH4OM(value)))
+#define FTM_BWR_OUTMASK_CH4OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH4OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */
+#define FTM_RD_OUTMASK_CH5OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH5OM_MASK) >> FTM_OUTMASK_CH5OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH5OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH5OM_SHIFT))
+
+/*! @brief Set the CH5OM field to a new value. */
+#define FTM_WR_OUTMASK_CH5OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH5OM_MASK, FTM_OUTMASK_CH5OM(value)))
+#define FTM_BWR_OUTMASK_CH5OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH5OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */
+#define FTM_RD_OUTMASK_CH6OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH6OM_MASK) >> FTM_OUTMASK_CH6OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH6OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH6OM_SHIFT))
+
+/*! @brief Set the CH6OM field to a new value. */
+#define FTM_WR_OUTMASK_CH6OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH6OM_MASK, FTM_OUTMASK_CH6OM(value)))
+#define FTM_BWR_OUTMASK_CH6OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH6OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */
+#define FTM_RD_OUTMASK_CH7OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH7OM_MASK) >> FTM_OUTMASK_CH7OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH7OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH7OM_SHIFT))
+
+/*! @brief Set the CH7OM field to a new value. */
+#define FTM_WR_OUTMASK_CH7OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH7OM_MASK, FTM_OUTMASK_CH7OM(value)))
+#define FTM_BWR_OUTMASK_CH7OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH7OM_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_COMBINE - Function For Linked Channels
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_COMBINE - Function For Linked Channels (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the control bits used to configure the fault control,
+ * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
+ * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
+ * 4, and 6.
+ */
+/*!
+ * @name Constants and macros for entire FTM_COMBINE register
+ */
+/*@{*/
+#define FTM_RD_COMBINE(base)     (FTM_COMBINE_REG(base))
+#define FTM_WR_COMBINE(base, value) (FTM_COMBINE_REG(base) = (value))
+#define FTM_RMW_COMBINE(base, mask, value) (FTM_WR_COMBINE(base, (FTM_RD_COMBINE(base) & ~(mask)) | (value)))
+#define FTM_SET_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) |  (value)))
+#define FTM_CLR_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) & ~(value)))
+#define FTM_TOG_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_COMBINE bitfields
+ */
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */
+#define FTM_RD_COMBINE_COMBINE0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE0_MASK) >> FTM_COMBINE_COMBINE0_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE0_SHIFT))
+
+/*! @brief Set the COMBINE0 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE0_MASK, FTM_COMBINE_COMBINE0(value)))
+#define FTM_BWR_COMBINE_COMBINE0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP0[1] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP0 field. */
+#define FTM_RD_COMBINE_COMP0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP0_MASK) >> FTM_COMBINE_COMP0_SHIFT)
+#define FTM_BRD_COMBINE_COMP0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP0_SHIFT))
+
+/*! @brief Set the COMP0 field to a new value. */
+#define FTM_WR_COMBINE_COMP0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP0_MASK, FTM_COMBINE_COMP0(value)))
+#define FTM_BWR_COMBINE_COMP0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */
+#define FTM_RD_COMBINE_DECAPEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN0_MASK) >> FTM_COMBINE_DECAPEN0_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN0_SHIFT))
+
+/*! @brief Set the DECAPEN0 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN0_MASK, FTM_COMBINE_DECAPEN0(value)))
+#define FTM_BWR_COMBINE_DECAPEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP0[3] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */
+#define FTM_RD_COMBINE_DECAP0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP0_MASK) >> FTM_COMBINE_DECAP0_SHIFT)
+#define FTM_BRD_COMBINE_DECAP0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP0_SHIFT))
+
+/*! @brief Set the DECAP0 field to a new value. */
+#define FTM_WR_COMBINE_DECAP0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP0_MASK, FTM_COMBINE_DECAP0(value)))
+#define FTM_BWR_COMBINE_DECAP0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN0[4] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */
+#define FTM_RD_COMBINE_DTEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN0_MASK) >> FTM_COMBINE_DTEN0_SHIFT)
+#define FTM_BRD_COMBINE_DTEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN0_SHIFT))
+
+/*! @brief Set the DTEN0 field to a new value. */
+#define FTM_WR_COMBINE_DTEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN0_MASK, FTM_COMBINE_DTEN0(value)))
+#define FTM_BWR_COMBINE_DTEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */
+#define FTM_RD_COMBINE_SYNCEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN0_MASK) >> FTM_COMBINE_SYNCEN0_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN0_SHIFT))
+
+/*! @brief Set the SYNCEN0 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN0_MASK, FTM_COMBINE_SYNCEN0(value)))
+#define FTM_BWR_COMBINE_SYNCEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */
+#define FTM_RD_COMBINE_FAULTEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN0_MASK) >> FTM_COMBINE_FAULTEN0_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN0_SHIFT))
+
+/*! @brief Set the FAULTEN0 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN0_MASK, FTM_COMBINE_FAULTEN0(value)))
+#define FTM_BWR_COMBINE_FAULTEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */
+#define FTM_RD_COMBINE_COMBINE1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE1_MASK) >> FTM_COMBINE_COMBINE1_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE1_SHIFT))
+
+/*! @brief Set the COMBINE1 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE1_MASK, FTM_COMBINE_COMBINE1(value)))
+#define FTM_BWR_COMBINE_COMBINE1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP1[9] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP1 field. */
+#define FTM_RD_COMBINE_COMP1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP1_MASK) >> FTM_COMBINE_COMP1_SHIFT)
+#define FTM_BRD_COMBINE_COMP1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP1_SHIFT))
+
+/*! @brief Set the COMP1 field to a new value. */
+#define FTM_WR_COMBINE_COMP1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP1_MASK, FTM_COMBINE_COMP1(value)))
+#define FTM_BWR_COMBINE_COMP1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */
+#define FTM_RD_COMBINE_DECAPEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN1_MASK) >> FTM_COMBINE_DECAPEN1_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN1_SHIFT))
+
+/*! @brief Set the DECAPEN1 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN1_MASK, FTM_COMBINE_DECAPEN1(value)))
+#define FTM_BWR_COMBINE_DECAPEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP1[11] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */
+#define FTM_RD_COMBINE_DECAP1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP1_MASK) >> FTM_COMBINE_DECAP1_SHIFT)
+#define FTM_BRD_COMBINE_DECAP1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP1_SHIFT))
+
+/*! @brief Set the DECAP1 field to a new value. */
+#define FTM_WR_COMBINE_DECAP1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP1_MASK, FTM_COMBINE_DECAP1(value)))
+#define FTM_BWR_COMBINE_DECAP1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN1[12] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */
+#define FTM_RD_COMBINE_DTEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN1_MASK) >> FTM_COMBINE_DTEN1_SHIFT)
+#define FTM_BRD_COMBINE_DTEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN1_SHIFT))
+
+/*! @brief Set the DTEN1 field to a new value. */
+#define FTM_WR_COMBINE_DTEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN1_MASK, FTM_COMBINE_DTEN1(value)))
+#define FTM_BWR_COMBINE_DTEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */
+#define FTM_RD_COMBINE_SYNCEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN1_MASK) >> FTM_COMBINE_SYNCEN1_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN1_SHIFT))
+
+/*! @brief Set the SYNCEN1 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN1_MASK, FTM_COMBINE_SYNCEN1(value)))
+#define FTM_BWR_COMBINE_SYNCEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */
+#define FTM_RD_COMBINE_FAULTEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN1_MASK) >> FTM_COMBINE_FAULTEN1_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN1_SHIFT))
+
+/*! @brief Set the FAULTEN1 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN1_MASK, FTM_COMBINE_FAULTEN1(value)))
+#define FTM_BWR_COMBINE_FAULTEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */
+#define FTM_RD_COMBINE_COMBINE2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE2_MASK) >> FTM_COMBINE_COMBINE2_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE2_SHIFT))
+
+/*! @brief Set the COMBINE2 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE2_MASK, FTM_COMBINE_COMBINE2(value)))
+#define FTM_BWR_COMBINE_COMBINE2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP2[17] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP2 field. */
+#define FTM_RD_COMBINE_COMP2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP2_MASK) >> FTM_COMBINE_COMP2_SHIFT)
+#define FTM_BRD_COMBINE_COMP2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP2_SHIFT))
+
+/*! @brief Set the COMP2 field to a new value. */
+#define FTM_WR_COMBINE_COMP2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP2_MASK, FTM_COMBINE_COMP2(value)))
+#define FTM_BWR_COMBINE_COMP2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */
+#define FTM_RD_COMBINE_DECAPEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN2_MASK) >> FTM_COMBINE_DECAPEN2_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN2_SHIFT))
+
+/*! @brief Set the DECAPEN2 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN2_MASK, FTM_COMBINE_DECAPEN2(value)))
+#define FTM_BWR_COMBINE_DECAPEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP2[19] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */
+#define FTM_RD_COMBINE_DECAP2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP2_MASK) >> FTM_COMBINE_DECAP2_SHIFT)
+#define FTM_BRD_COMBINE_DECAP2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP2_SHIFT))
+
+/*! @brief Set the DECAP2 field to a new value. */
+#define FTM_WR_COMBINE_DECAP2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP2_MASK, FTM_COMBINE_DECAP2(value)))
+#define FTM_BWR_COMBINE_DECAP2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN2[20] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */
+#define FTM_RD_COMBINE_DTEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN2_MASK) >> FTM_COMBINE_DTEN2_SHIFT)
+#define FTM_BRD_COMBINE_DTEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN2_SHIFT))
+
+/*! @brief Set the DTEN2 field to a new value. */
+#define FTM_WR_COMBINE_DTEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN2_MASK, FTM_COMBINE_DTEN2(value)))
+#define FTM_BWR_COMBINE_DTEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */
+#define FTM_RD_COMBINE_SYNCEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN2_MASK) >> FTM_COMBINE_SYNCEN2_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN2_SHIFT))
+
+/*! @brief Set the SYNCEN2 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN2_MASK, FTM_COMBINE_SYNCEN2(value)))
+#define FTM_BWR_COMBINE_SYNCEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */
+#define FTM_RD_COMBINE_FAULTEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN2_MASK) >> FTM_COMBINE_FAULTEN2_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN2_SHIFT))
+
+/*! @brief Set the FAULTEN2 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN2_MASK, FTM_COMBINE_FAULTEN2(value)))
+#define FTM_BWR_COMBINE_FAULTEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */
+#define FTM_RD_COMBINE_COMBINE3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE3_MASK) >> FTM_COMBINE_COMBINE3_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE3_SHIFT))
+
+/*! @brief Set the COMBINE3 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE3_MASK, FTM_COMBINE_COMBINE3(value)))
+#define FTM_BWR_COMBINE_COMBINE3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP3[25] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP3 field. */
+#define FTM_RD_COMBINE_COMP3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP3_MASK) >> FTM_COMBINE_COMP3_SHIFT)
+#define FTM_BRD_COMBINE_COMP3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP3_SHIFT))
+
+/*! @brief Set the COMP3 field to a new value. */
+#define FTM_WR_COMBINE_COMP3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP3_MASK, FTM_COMBINE_COMP3(value)))
+#define FTM_BWR_COMBINE_COMP3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */
+#define FTM_RD_COMBINE_DECAPEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN3_MASK) >> FTM_COMBINE_DECAPEN3_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN3_SHIFT))
+
+/*! @brief Set the DECAPEN3 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN3_MASK, FTM_COMBINE_DECAPEN3(value)))
+#define FTM_BWR_COMBINE_DECAPEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP3[27] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */
+#define FTM_RD_COMBINE_DECAP3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP3_MASK) >> FTM_COMBINE_DECAP3_SHIFT)
+#define FTM_BRD_COMBINE_DECAP3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP3_SHIFT))
+
+/*! @brief Set the DECAP3 field to a new value. */
+#define FTM_WR_COMBINE_DECAP3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP3_MASK, FTM_COMBINE_DECAP3(value)))
+#define FTM_BWR_COMBINE_DECAP3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN3[28] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */
+#define FTM_RD_COMBINE_DTEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN3_MASK) >> FTM_COMBINE_DTEN3_SHIFT)
+#define FTM_BRD_COMBINE_DTEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN3_SHIFT))
+
+/*! @brief Set the DTEN3 field to a new value. */
+#define FTM_WR_COMBINE_DTEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN3_MASK, FTM_COMBINE_DTEN3(value)))
+#define FTM_BWR_COMBINE_DTEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */
+#define FTM_RD_COMBINE_SYNCEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN3_MASK) >> FTM_COMBINE_SYNCEN3_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN3_SHIFT))
+
+/*! @brief Set the SYNCEN3 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN3_MASK, FTM_COMBINE_SYNCEN3(value)))
+#define FTM_BWR_COMBINE_SYNCEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */
+#define FTM_RD_COMBINE_FAULTEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN3_MASK) >> FTM_COMBINE_FAULTEN3_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN3_SHIFT))
+
+/*! @brief Set the FAULTEN3 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN3_MASK, FTM_COMBINE_FAULTEN3(value)))
+#define FTM_BWR_COMBINE_FAULTEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN3_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_DEADTIME - Deadtime Insertion Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_DEADTIME - Deadtime Insertion Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the deadtime prescaler factor and deadtime value. All
+ * FTM channels use this clock prescaler and this deadtime value for the deadtime
+ * insertion.
+ */
+/*!
+ * @name Constants and macros for entire FTM_DEADTIME register
+ */
+/*@{*/
+#define FTM_RD_DEADTIME(base)    (FTM_DEADTIME_REG(base))
+#define FTM_WR_DEADTIME(base, value) (FTM_DEADTIME_REG(base) = (value))
+#define FTM_RMW_DEADTIME(base, mask, value) (FTM_WR_DEADTIME(base, (FTM_RD_DEADTIME(base) & ~(mask)) | (value)))
+#define FTM_SET_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) |  (value)))
+#define FTM_CLR_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) & ~(value)))
+#define FTM_TOG_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_DEADTIME bitfields
+ */
+
+/*!
+ * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
+ *
+ * Selects the deadtime insertion value for the deadtime counter. The deadtime
+ * counter is clocked by a scaled version of the system clock. See the description
+ * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
+ * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
+ * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
+ * This pattern continues up to a possible 63 counts. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */
+#define FTM_RD_DEADTIME_DTVAL(base) ((FTM_DEADTIME_REG(base) & FTM_DEADTIME_DTVAL_MASK) >> FTM_DEADTIME_DTVAL_SHIFT)
+#define FTM_BRD_DEADTIME_DTVAL(base) (FTM_RD_DEADTIME_DTVAL(base))
+
+/*! @brief Set the DTVAL field to a new value. */
+#define FTM_WR_DEADTIME_DTVAL(base, value) (FTM_RMW_DEADTIME(base, FTM_DEADTIME_DTVAL_MASK, FTM_DEADTIME_DTVAL(value)))
+#define FTM_BWR_DEADTIME_DTVAL(base, value) (FTM_WR_DEADTIME_DTVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
+ *
+ * Selects the division factor of the system clock. This prescaled clock is used
+ * by the deadtime counter. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0x - Divide the system clock by 1.
+ * - 0b10 - Divide the system clock by 4.
+ * - 0b11 - Divide the system clock by 16.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_DEADTIME_DTPS field. */
+#define FTM_RD_DEADTIME_DTPS(base) ((FTM_DEADTIME_REG(base) & FTM_DEADTIME_DTPS_MASK) >> FTM_DEADTIME_DTPS_SHIFT)
+#define FTM_BRD_DEADTIME_DTPS(base) (FTM_RD_DEADTIME_DTPS(base))
+
+/*! @brief Set the DTPS field to a new value. */
+#define FTM_WR_DEADTIME_DTPS(base, value) (FTM_RMW_DEADTIME(base, FTM_DEADTIME_DTPS_MASK, FTM_DEADTIME_DTPS(value)))
+#define FTM_BWR_DEADTIME_DTPS(base, value) (FTM_WR_DEADTIME_DTPS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_EXTTRIG - FTM External Trigger
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_EXTTRIG - FTM External Trigger (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register: Indicates when a channel trigger was generated Enables the
+ * generation of a trigger when the FTM counter is equal to its initial value
+ * Selects which channels are used in the generation of the channel triggers Several
+ * channels can be selected to generate multiple triggers in one PWM period.
+ * Channels 6 and 7 are not used to generate channel triggers.
+ */
+/*!
+ * @name Constants and macros for entire FTM_EXTTRIG register
+ */
+/*@{*/
+#define FTM_RD_EXTTRIG(base)     (FTM_EXTTRIG_REG(base))
+#define FTM_WR_EXTTRIG(base, value) (FTM_EXTTRIG_REG(base) = (value))
+#define FTM_RMW_EXTTRIG(base, mask, value) (FTM_WR_EXTTRIG(base, (FTM_RD_EXTTRIG(base) & ~(mask)) | (value)))
+#define FTM_SET_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) |  (value)))
+#define FTM_CLR_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) & ~(value)))
+#define FTM_TOG_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_EXTTRIG bitfields
+ */
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */
+#define FTM_RD_EXTTRIG_CH2TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH2TRIG_MASK) >> FTM_EXTTRIG_CH2TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH2TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH2TRIG_SHIFT))
+
+/*! @brief Set the CH2TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH2TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH2TRIG_MASK, FTM_EXTTRIG_CH2TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH2TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH2TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */
+#define FTM_RD_EXTTRIG_CH3TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH3TRIG_MASK) >> FTM_EXTTRIG_CH3TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH3TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH3TRIG_SHIFT))
+
+/*! @brief Set the CH3TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH3TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH3TRIG_MASK, FTM_EXTTRIG_CH3TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH3TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH3TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */
+#define FTM_RD_EXTTRIG_CH4TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH4TRIG_MASK) >> FTM_EXTTRIG_CH4TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH4TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH4TRIG_SHIFT))
+
+/*! @brief Set the CH4TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH4TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH4TRIG_MASK, FTM_EXTTRIG_CH4TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH4TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH4TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */
+#define FTM_RD_EXTTRIG_CH5TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH5TRIG_MASK) >> FTM_EXTTRIG_CH5TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH5TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH5TRIG_SHIFT))
+
+/*! @brief Set the CH5TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH5TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH5TRIG_MASK, FTM_EXTTRIG_CH5TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH5TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH5TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */
+#define FTM_RD_EXTTRIG_CH0TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH0TRIG_MASK) >> FTM_EXTTRIG_CH0TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH0TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH0TRIG_SHIFT))
+
+/*! @brief Set the CH0TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH0TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH0TRIG_MASK, FTM_EXTTRIG_CH0TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH0TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH0TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */
+#define FTM_RD_EXTTRIG_CH1TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH1TRIG_MASK) >> FTM_EXTTRIG_CH1TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH1TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH1TRIG_SHIFT))
+
+/*! @brief Set the CH1TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH1TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH1TRIG_MASK, FTM_EXTTRIG_CH1TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH1TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH1TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
+ *
+ * Enables the generation of the trigger when the FTM counter is equal to the
+ * CNTIN register.
+ *
+ * Values:
+ * - 0b0 - The generation of initialization trigger is disabled.
+ * - 0b1 - The generation of initialization trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */
+#define FTM_RD_EXTTRIG_INITTRIGEN(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_INITTRIGEN_MASK) >> FTM_EXTTRIG_INITTRIGEN_SHIFT)
+#define FTM_BRD_EXTTRIG_INITTRIGEN(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_INITTRIGEN_SHIFT))
+
+/*! @brief Set the INITTRIGEN field to a new value. */
+#define FTM_WR_EXTTRIG_INITTRIGEN(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_INITTRIGEN_MASK, FTM_EXTTRIG_INITTRIGEN(value)))
+#define FTM_BWR_EXTTRIG_INITTRIGEN(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_INITTRIGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
+ *
+ * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
+ * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
+ * has no effect. If another channel trigger is generated before the clearing
+ * sequence is completed, the sequence is reset so TRIGF remains set after the clear
+ * sequence is completed for the earlier TRIGF.
+ *
+ * Values:
+ * - 0b0 - No channel trigger was generated.
+ * - 0b1 - A channel trigger was generated.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */
+#define FTM_RD_EXTTRIG_TRIGF(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_TRIGF_MASK) >> FTM_EXTTRIG_TRIGF_SHIFT)
+#define FTM_BRD_EXTTRIG_TRIGF(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_TRIGF_SHIFT))
+
+/*! @brief Set the TRIGF field to a new value. */
+#define FTM_WR_EXTTRIG_TRIGF(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_TRIGF_MASK, FTM_EXTTRIG_TRIGF(value)))
+#define FTM_BWR_EXTTRIG_TRIGF(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_TRIGF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_POL - Channels Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_POL - Channels Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the output polarity of the FTM channels. The safe value
+ * that is driven in a channel output when the fault control is enabled and a
+ * fault condition is detected is the inactive state of the channel. That is, the
+ * safe value of a channel is the value of its POL bit.
+ */
+/*!
+ * @name Constants and macros for entire FTM_POL register
+ */
+/*@{*/
+#define FTM_RD_POL(base)         (FTM_POL_REG(base))
+#define FTM_WR_POL(base, value)  (FTM_POL_REG(base) = (value))
+#define FTM_RMW_POL(base, mask, value) (FTM_WR_POL(base, (FTM_RD_POL(base) & ~(mask)) | (value)))
+#define FTM_SET_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) |  (value)))
+#define FTM_CLR_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) & ~(value)))
+#define FTM_TOG_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_POL bitfields
+ */
+
+/*!
+ * @name Register FTM_POL, field POL0[0] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL0 field. */
+#define FTM_RD_POL_POL0(base) ((FTM_POL_REG(base) & FTM_POL_POL0_MASK) >> FTM_POL_POL0_SHIFT)
+#define FTM_BRD_POL_POL0(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL0_SHIFT))
+
+/*! @brief Set the POL0 field to a new value. */
+#define FTM_WR_POL_POL0(base, value) (FTM_RMW_POL(base, FTM_POL_POL0_MASK, FTM_POL_POL0(value)))
+#define FTM_BWR_POL_POL0(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL1[1] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL1 field. */
+#define FTM_RD_POL_POL1(base) ((FTM_POL_REG(base) & FTM_POL_POL1_MASK) >> FTM_POL_POL1_SHIFT)
+#define FTM_BRD_POL_POL1(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL1_SHIFT))
+
+/*! @brief Set the POL1 field to a new value. */
+#define FTM_WR_POL_POL1(base, value) (FTM_RMW_POL(base, FTM_POL_POL1_MASK, FTM_POL_POL1(value)))
+#define FTM_BWR_POL_POL1(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL2[2] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL2 field. */
+#define FTM_RD_POL_POL2(base) ((FTM_POL_REG(base) & FTM_POL_POL2_MASK) >> FTM_POL_POL2_SHIFT)
+#define FTM_BRD_POL_POL2(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL2_SHIFT))
+
+/*! @brief Set the POL2 field to a new value. */
+#define FTM_WR_POL_POL2(base, value) (FTM_RMW_POL(base, FTM_POL_POL2_MASK, FTM_POL_POL2(value)))
+#define FTM_BWR_POL_POL2(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL3[3] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL3 field. */
+#define FTM_RD_POL_POL3(base) ((FTM_POL_REG(base) & FTM_POL_POL3_MASK) >> FTM_POL_POL3_SHIFT)
+#define FTM_BRD_POL_POL3(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL3_SHIFT))
+
+/*! @brief Set the POL3 field to a new value. */
+#define FTM_WR_POL_POL3(base, value) (FTM_RMW_POL(base, FTM_POL_POL3_MASK, FTM_POL_POL3(value)))
+#define FTM_BWR_POL_POL3(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL4[4] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL4 field. */
+#define FTM_RD_POL_POL4(base) ((FTM_POL_REG(base) & FTM_POL_POL4_MASK) >> FTM_POL_POL4_SHIFT)
+#define FTM_BRD_POL_POL4(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL4_SHIFT))
+
+/*! @brief Set the POL4 field to a new value. */
+#define FTM_WR_POL_POL4(base, value) (FTM_RMW_POL(base, FTM_POL_POL4_MASK, FTM_POL_POL4(value)))
+#define FTM_BWR_POL_POL4(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL5[5] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL5 field. */
+#define FTM_RD_POL_POL5(base) ((FTM_POL_REG(base) & FTM_POL_POL5_MASK) >> FTM_POL_POL5_SHIFT)
+#define FTM_BRD_POL_POL5(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL5_SHIFT))
+
+/*! @brief Set the POL5 field to a new value. */
+#define FTM_WR_POL_POL5(base, value) (FTM_RMW_POL(base, FTM_POL_POL5_MASK, FTM_POL_POL5(value)))
+#define FTM_BWR_POL_POL5(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL6[6] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL6 field. */
+#define FTM_RD_POL_POL6(base) ((FTM_POL_REG(base) & FTM_POL_POL6_MASK) >> FTM_POL_POL6_SHIFT)
+#define FTM_BRD_POL_POL6(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL6_SHIFT))
+
+/*! @brief Set the POL6 field to a new value. */
+#define FTM_WR_POL_POL6(base, value) (FTM_RMW_POL(base, FTM_POL_POL6_MASK, FTM_POL_POL6(value)))
+#define FTM_BWR_POL_POL6(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL7[7] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL7 field. */
+#define FTM_RD_POL_POL7(base) ((FTM_POL_REG(base) & FTM_POL_POL7_MASK) >> FTM_POL_POL7_SHIFT)
+#define FTM_BRD_POL_POL7(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL7_SHIFT))
+
+/*! @brief Set the POL7 field to a new value. */
+#define FTM_WR_POL_POL7(base, value) (FTM_RMW_POL(base, FTM_POL_POL7_MASK, FTM_POL_POL7(value)))
+#define FTM_BWR_POL_POL7(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FMS - Fault Mode Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FMS - Fault Mode Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the fault detection flags, write protection enable
+ * bit, and the logic OR of the enabled fault inputs.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FMS register
+ */
+/*@{*/
+#define FTM_RD_FMS(base)         (FTM_FMS_REG(base))
+#define FTM_WR_FMS(base, value)  (FTM_FMS_REG(base) = (value))
+#define FTM_RMW_FMS(base, mask, value) (FTM_WR_FMS(base, (FTM_RD_FMS(base) & ~(mask)) | (value)))
+#define FTM_SET_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) |  (value)))
+#define FTM_CLR_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) & ~(value)))
+#define FTM_TOG_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FMS bitfields
+ */
+
+/*!
+ * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
+ * by reading the FMS register while FAULTF0 is set and then writing a 0 to
+ * FAULTF0 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF0 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF0 field. */
+#define FTM_RD_FMS_FAULTF0(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF0_MASK) >> FTM_FMS_FAULTF0_SHIFT)
+#define FTM_BRD_FMS_FAULTF0(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF0_SHIFT))
+
+/*! @brief Set the FAULTF0 field to a new value. */
+#define FTM_WR_FMS_FAULTF0(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF0_MASK, FTM_FMS_FAULTF0(value)))
+#define FTM_BWR_FMS_FAULTF0(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
+ * by reading the FMS register while FAULTF1 is set and then writing a 0 to
+ * FAULTF1 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF1 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF1 field. */
+#define FTM_RD_FMS_FAULTF1(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF1_MASK) >> FTM_FMS_FAULTF1_SHIFT)
+#define FTM_BRD_FMS_FAULTF1(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF1_SHIFT))
+
+/*! @brief Set the FAULTF1 field to a new value. */
+#define FTM_WR_FMS_FAULTF1(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF1_MASK, FTM_FMS_FAULTF1(value)))
+#define FTM_BWR_FMS_FAULTF1(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
+ * by reading the FMS register while FAULTF2 is set and then writing a 0 to
+ * FAULTF2 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF2 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF2 field. */
+#define FTM_RD_FMS_FAULTF2(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF2_MASK) >> FTM_FMS_FAULTF2_SHIFT)
+#define FTM_BRD_FMS_FAULTF2(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF2_SHIFT))
+
+/*! @brief Set the FAULTF2 field to a new value. */
+#define FTM_WR_FMS_FAULTF2(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF2_MASK, FTM_FMS_FAULTF2(value)))
+#define FTM_BWR_FMS_FAULTF2(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
+ * by reading the FMS register while FAULTF3 is set and then writing a 0 to
+ * FAULTF3 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF3 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF3 field. */
+#define FTM_RD_FMS_FAULTF3(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF3_MASK) >> FTM_FMS_FAULTF3_SHIFT)
+#define FTM_BRD_FMS_FAULTF3(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF3_SHIFT))
+
+/*! @brief Set the FAULTF3 field to a new value. */
+#define FTM_WR_FMS_FAULTF3(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF3_MASK, FTM_FMS_FAULTF3(value)))
+#define FTM_BWR_FMS_FAULTF3(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTIN[5] (RO)
+ *
+ * Represents the logic OR of the enabled fault inputs after their filter (if
+ * their filter is enabled) when fault control is enabled.
+ *
+ * Values:
+ * - 0b0 - The logic OR of the enabled fault inputs is 0.
+ * - 0b1 - The logic OR of the enabled fault inputs is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTIN field. */
+#define FTM_RD_FMS_FAULTIN(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTIN_MASK) >> FTM_FMS_FAULTIN_SHIFT)
+#define FTM_BRD_FMS_FAULTIN(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTIN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field WPEN[6] (RW)
+ *
+ * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
+ * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
+ * WPDIS. Writing 0 to WPEN has no effect.
+ *
+ * Values:
+ * - 0b0 - Write protection is disabled. Write protected bits can be written.
+ * - 0b1 - Write protection is enabled. Write protected bits cannot be written.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_WPEN field. */
+#define FTM_RD_FMS_WPEN(base) ((FTM_FMS_REG(base) & FTM_FMS_WPEN_MASK) >> FTM_FMS_WPEN_SHIFT)
+#define FTM_BRD_FMS_WPEN(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_WPEN_SHIFT))
+
+/*! @brief Set the WPEN field to a new value. */
+#define FTM_WR_FMS_WPEN(base, value) (FTM_RMW_FMS(base, FTM_FMS_WPEN_MASK, FTM_FMS_WPEN(value)))
+#define FTM_BWR_FMS_WPEN(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_WPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
+ *
+ * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
+ * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
+ * a 0 to FAULTF while there is no existing fault condition at the enabled fault
+ * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
+ * detected in an enabled fault input before the clearing sequence is completed, the
+ * sequence is reset so FAULTF remains set after the clearing sequence is
+ * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
+ * are cleared individually.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected.
+ * - 0b1 - A fault condition was detected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF field. */
+#define FTM_RD_FMS_FAULTF(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF_MASK) >> FTM_FMS_FAULTF_SHIFT)
+#define FTM_BRD_FMS_FAULTF(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF_SHIFT))
+
+/*! @brief Set the FAULTF field to a new value. */
+#define FTM_WR_FMS_FAULTF(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF_MASK, FTM_FMS_FAULTF(value)))
+#define FTM_BWR_FMS_FAULTF(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FILTER - Input Capture Filter Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FILTER - Input Capture Filter Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the inputs of channels. Channels
+ * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
+ * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
+ * in input modes. Failure to do this could result in a missing valid signal.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FILTER register
+ */
+/*@{*/
+#define FTM_RD_FILTER(base)      (FTM_FILTER_REG(base))
+#define FTM_WR_FILTER(base, value) (FTM_FILTER_REG(base) = (value))
+#define FTM_RMW_FILTER(base, mask, value) (FTM_WR_FILTER(base, (FTM_RD_FILTER(base) & ~(mask)) | (value)))
+#define FTM_SET_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) |  (value)))
+#define FTM_CLR_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) & ~(value)))
+#define FTM_TOG_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FILTER bitfields
+ */
+
+/*!
+ * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */
+#define FTM_RD_FILTER_CH0FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH0FVAL_MASK) >> FTM_FILTER_CH0FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH0FVAL(base) (FTM_RD_FILTER_CH0FVAL(base))
+
+/*! @brief Set the CH0FVAL field to a new value. */
+#define FTM_WR_FILTER_CH0FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH0FVAL_MASK, FTM_FILTER_CH0FVAL(value)))
+#define FTM_BWR_FILTER_CH0FVAL(base, value) (FTM_WR_FILTER_CH0FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */
+#define FTM_RD_FILTER_CH1FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH1FVAL_MASK) >> FTM_FILTER_CH1FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH1FVAL(base) (FTM_RD_FILTER_CH1FVAL(base))
+
+/*! @brief Set the CH1FVAL field to a new value. */
+#define FTM_WR_FILTER_CH1FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH1FVAL_MASK, FTM_FILTER_CH1FVAL(value)))
+#define FTM_BWR_FILTER_CH1FVAL(base, value) (FTM_WR_FILTER_CH1FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */
+#define FTM_RD_FILTER_CH2FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH2FVAL_MASK) >> FTM_FILTER_CH2FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH2FVAL(base) (FTM_RD_FILTER_CH2FVAL(base))
+
+/*! @brief Set the CH2FVAL field to a new value. */
+#define FTM_WR_FILTER_CH2FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH2FVAL_MASK, FTM_FILTER_CH2FVAL(value)))
+#define FTM_BWR_FILTER_CH2FVAL(base, value) (FTM_WR_FILTER_CH2FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */
+#define FTM_RD_FILTER_CH3FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH3FVAL_MASK) >> FTM_FILTER_CH3FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH3FVAL(base) (FTM_RD_FILTER_CH3FVAL(base))
+
+/*! @brief Set the CH3FVAL field to a new value. */
+#define FTM_WR_FILTER_CH3FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH3FVAL_MASK, FTM_FILTER_CH3FVAL(value)))
+#define FTM_BWR_FILTER_CH3FVAL(base, value) (FTM_WR_FILTER_CH3FVAL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FLTCTRL - Fault Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FLTCTRL - Fault Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the fault inputs, enables the
+ * fault inputs and the fault inputs filter.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FLTCTRL register
+ */
+/*@{*/
+#define FTM_RD_FLTCTRL(base)     (FTM_FLTCTRL_REG(base))
+#define FTM_WR_FLTCTRL(base, value) (FTM_FLTCTRL_REG(base) = (value))
+#define FTM_RMW_FLTCTRL(base, mask, value) (FTM_WR_FLTCTRL(base, (FTM_RD_FLTCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) |  (value)))
+#define FTM_CLR_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) & ~(value)))
+#define FTM_TOG_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FLTCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */
+#define FTM_RD_FLTCTRL_FAULT0EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT0EN_MASK) >> FTM_FLTCTRL_FAULT0EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT0EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT0EN_SHIFT))
+
+/*! @brief Set the FAULT0EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT0EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT0EN_MASK, FTM_FLTCTRL_FAULT0EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT0EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */
+#define FTM_RD_FLTCTRL_FAULT1EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT1EN_MASK) >> FTM_FLTCTRL_FAULT1EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT1EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT1EN_SHIFT))
+
+/*! @brief Set the FAULT1EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT1EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT1EN_MASK, FTM_FLTCTRL_FAULT1EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT1EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */
+#define FTM_RD_FLTCTRL_FAULT2EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT2EN_MASK) >> FTM_FLTCTRL_FAULT2EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT2EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT2EN_SHIFT))
+
+/*! @brief Set the FAULT2EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT2EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT2EN_MASK, FTM_FLTCTRL_FAULT2EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT2EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */
+#define FTM_RD_FLTCTRL_FAULT3EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT3EN_MASK) >> FTM_FLTCTRL_FAULT3EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT3EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT3EN_SHIFT))
+
+/*! @brief Set the FAULT3EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT3EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT3EN_MASK, FTM_FLTCTRL_FAULT3EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT3EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT3EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */
+#define FTM_RD_FLTCTRL_FFLTR0EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR0EN_MASK) >> FTM_FLTCTRL_FFLTR0EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR0EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR0EN_SHIFT))
+
+/*! @brief Set the FFLTR0EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR0EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR0EN_MASK, FTM_FLTCTRL_FFLTR0EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR0EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */
+#define FTM_RD_FLTCTRL_FFLTR1EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR1EN_MASK) >> FTM_FLTCTRL_FFLTR1EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR1EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR1EN_SHIFT))
+
+/*! @brief Set the FFLTR1EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR1EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR1EN_MASK, FTM_FLTCTRL_FFLTR1EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR1EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */
+#define FTM_RD_FLTCTRL_FFLTR2EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR2EN_MASK) >> FTM_FLTCTRL_FFLTR2EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR2EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR2EN_SHIFT))
+
+/*! @brief Set the FFLTR2EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR2EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR2EN_MASK, FTM_FLTCTRL_FFLTR2EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR2EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */
+#define FTM_RD_FLTCTRL_FFLTR3EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR3EN_MASK) >> FTM_FLTCTRL_FFLTR3EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR3EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR3EN_SHIFT))
+
+/*! @brief Set the FFLTR3EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR3EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR3EN_MASK, FTM_FLTCTRL_FFLTR3EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR3EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR3EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
+ *
+ * Selects the filter value for the fault inputs. The fault filter is disabled
+ * when the value is zero. Writing to this field has immediate effect and must be
+ * done only when the fault control or all fault inputs are disabled. Failure to
+ * do this could result in a missing fault detection.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */
+#define FTM_RD_FLTCTRL_FFVAL(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFVAL_MASK) >> FTM_FLTCTRL_FFVAL_SHIFT)
+#define FTM_BRD_FLTCTRL_FFVAL(base) (FTM_RD_FLTCTRL_FFVAL(base))
+
+/*! @brief Set the FFVAL field to a new value. */
+#define FTM_WR_FLTCTRL_FFVAL(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFVAL_MASK, FTM_FLTCTRL_FFVAL(value)))
+#define FTM_BWR_FLTCTRL_FFVAL(base, value) (FTM_WR_FLTCTRL_FFVAL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_QDCTRL - Quadrature Decoder Control And Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has the control and status bits for the Quadrature Decoder mode.
+ */
+/*!
+ * @name Constants and macros for entire FTM_QDCTRL register
+ */
+/*@{*/
+#define FTM_RD_QDCTRL(base)      (FTM_QDCTRL_REG(base))
+#define FTM_WR_QDCTRL(base, value) (FTM_QDCTRL_REG(base) = (value))
+#define FTM_RMW_QDCTRL(base, mask, value) (FTM_WR_QDCTRL(base, (FTM_RD_QDCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) |  (value)))
+#define FTM_CLR_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) & ~(value)))
+#define FTM_TOG_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_QDCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
+ *
+ * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
+ * signals control the FTM counter direction. The Quadrature Decoder mode has
+ * precedence over the other modes. See #ModeSel1Table. This field is write protected.
+ * It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Quadrature Decoder mode is disabled.
+ * - 0b1 - Quadrature Decoder mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */
+#define FTM_RD_QDCTRL_QUADEN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADEN_MASK) >> FTM_QDCTRL_QUADEN_SHIFT)
+#define FTM_BRD_QDCTRL_QUADEN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADEN_SHIFT))
+
+/*! @brief Set the QUADEN field to a new value. */
+#define FTM_WR_QDCTRL_QUADEN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_QUADEN_MASK, FTM_QDCTRL_QUADEN(value)))
+#define FTM_BWR_QDCTRL_QUADEN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
+ *
+ * Indicates if the TOF bit was set on the top or the bottom of counting.
+ *
+ * Values:
+ * - 0b0 - TOF bit was set on the bottom of counting. There was an FTM counter
+ *     decrement and FTM counter changes from its minimum value (CNTIN register)
+ *     to its maximum value (MOD register).
+ * - 0b1 - TOF bit was set on the top of counting. There was an FTM counter
+ *     increment and FTM counter changes from its maximum value (MOD register) to its
+ *     minimum value (CNTIN register).
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */
+#define FTM_RD_QDCTRL_TOFDIR(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_TOFDIR_MASK) >> FTM_QDCTRL_TOFDIR_SHIFT)
+#define FTM_BRD_QDCTRL_TOFDIR(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_TOFDIR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
+ *
+ * Indicates the counting direction.
+ *
+ * Values:
+ * - 0b0 - Counting direction is decreasing (FTM counter decrement).
+ * - 0b1 - Counting direction is increasing (FTM counter increment).
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */
+#define FTM_RD_QDCTRL_QUADIR(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADIR_MASK) >> FTM_QDCTRL_QUADIR_SHIFT)
+#define FTM_BRD_QDCTRL_QUADIR(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADIR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
+ *
+ * Selects the encoding mode used in the Quadrature Decoder mode.
+ *
+ * Values:
+ * - 0b0 - Phase A and phase B encoding mode.
+ * - 0b1 - Count and direction encoding mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */
+#define FTM_RD_QDCTRL_QUADMODE(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADMODE_MASK) >> FTM_QDCTRL_QUADMODE_SHIFT)
+#define FTM_BRD_QDCTRL_QUADMODE(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADMODE_SHIFT))
+
+/*! @brief Set the QUADMODE field to a new value. */
+#define FTM_WR_QDCTRL_QUADMODE(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_QUADMODE_MASK, FTM_QDCTRL_QUADMODE(value)))
+#define FTM_BWR_QDCTRL_QUADMODE(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase B input.
+ *
+ * Values:
+ * - 0b0 - Normal polarity. Phase B input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 0b1 - Inverted polarity. Phase B input signal is inverted before
+ *     identifying the rising and falling edges of this signal.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */
+#define FTM_RD_QDCTRL_PHBPOL(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHBPOL_MASK) >> FTM_QDCTRL_PHBPOL_SHIFT)
+#define FTM_BRD_QDCTRL_PHBPOL(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBPOL_SHIFT))
+
+/*! @brief Set the PHBPOL field to a new value. */
+#define FTM_WR_QDCTRL_PHBPOL(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHBPOL_MASK, FTM_QDCTRL_PHBPOL(value)))
+#define FTM_BWR_QDCTRL_PHBPOL(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase A input.
+ *
+ * Values:
+ * - 0b0 - Normal polarity. Phase A input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 0b1 - Inverted polarity. Phase A input signal is inverted before
+ *     identifying the rising and falling edges of this signal.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */
+#define FTM_RD_QDCTRL_PHAPOL(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHAPOL_MASK) >> FTM_QDCTRL_PHAPOL_SHIFT)
+#define FTM_BRD_QDCTRL_PHAPOL(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAPOL_SHIFT))
+
+/*! @brief Set the PHAPOL field to a new value. */
+#define FTM_WR_QDCTRL_PHAPOL(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHAPOL_MASK, FTM_QDCTRL_PHAPOL(value)))
+#define FTM_BWR_QDCTRL_PHAPOL(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase B input. The filter value
+ * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
+ * filter is also disabled when CH1FVAL is zero.
+ *
+ * Values:
+ * - 0b0 - Phase B input filter is disabled.
+ * - 0b1 - Phase B input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */
+#define FTM_RD_QDCTRL_PHBFLTREN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHBFLTREN_MASK) >> FTM_QDCTRL_PHBFLTREN_SHIFT)
+#define FTM_BRD_QDCTRL_PHBFLTREN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBFLTREN_SHIFT))
+
+/*! @brief Set the PHBFLTREN field to a new value. */
+#define FTM_WR_QDCTRL_PHBFLTREN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHBFLTREN_MASK, FTM_QDCTRL_PHBFLTREN(value)))
+#define FTM_BWR_QDCTRL_PHBFLTREN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBFLTREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase A input. The filter value
+ * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
+ * filter is also disabled when CH0FVAL is zero.
+ *
+ * Values:
+ * - 0b0 - Phase A input filter is disabled.
+ * - 0b1 - Phase A input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */
+#define FTM_RD_QDCTRL_PHAFLTREN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHAFLTREN_MASK) >> FTM_QDCTRL_PHAFLTREN_SHIFT)
+#define FTM_BRD_QDCTRL_PHAFLTREN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAFLTREN_SHIFT))
+
+/*! @brief Set the PHAFLTREN field to a new value. */
+#define FTM_WR_QDCTRL_PHAFLTREN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHAFLTREN_MASK, FTM_QDCTRL_PHAFLTREN(value)))
+#define FTM_BWR_QDCTRL_PHAFLTREN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAFLTREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CONF - Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CONF - Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the number of times that the FTM counter overflow
+ * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
+ * of an external global time base, and the global time base signal generation.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CONF register
+ */
+/*@{*/
+#define FTM_RD_CONF(base)        (FTM_CONF_REG(base))
+#define FTM_WR_CONF(base, value) (FTM_CONF_REG(base) = (value))
+#define FTM_RMW_CONF(base, mask, value) (FTM_WR_CONF(base, (FTM_RD_CONF(base) & ~(mask)) | (value)))
+#define FTM_SET_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) |  (value)))
+#define FTM_CLR_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) & ~(value)))
+#define FTM_TOG_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CONF bitfields
+ */
+
+/*!
+ * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
+ *
+ * Selects the ratio between the number of counter overflows to the number of
+ * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
+ * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
+ * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
+ * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
+ * first counter overflow but not for the next 3 overflows. This pattern continues
+ * up to a maximum of 31.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_NUMTOF field. */
+#define FTM_RD_CONF_NUMTOF(base) ((FTM_CONF_REG(base) & FTM_CONF_NUMTOF_MASK) >> FTM_CONF_NUMTOF_SHIFT)
+#define FTM_BRD_CONF_NUMTOF(base) (FTM_RD_CONF_NUMTOF(base))
+
+/*! @brief Set the NUMTOF field to a new value. */
+#define FTM_WR_CONF_NUMTOF(base, value) (FTM_RMW_CONF(base, FTM_CONF_NUMTOF_MASK, FTM_CONF_NUMTOF(value)))
+#define FTM_BWR_CONF_NUMTOF(base, value) (FTM_WR_CONF_NUMTOF(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
+ *
+ * Selects the FTM behavior in BDM mode. See BDM mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_BDMMODE field. */
+#define FTM_RD_CONF_BDMMODE(base) ((FTM_CONF_REG(base) & FTM_CONF_BDMMODE_MASK) >> FTM_CONF_BDMMODE_SHIFT)
+#define FTM_BRD_CONF_BDMMODE(base) (FTM_RD_CONF_BDMMODE(base))
+
+/*! @brief Set the BDMMODE field to a new value. */
+#define FTM_WR_CONF_BDMMODE(base, value) (FTM_RMW_CONF(base, FTM_CONF_BDMMODE_MASK, FTM_CONF_BDMMODE(value)))
+#define FTM_BWR_CONF_BDMMODE(base, value) (FTM_WR_CONF_BDMMODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field GTBEEN[9] (RW)
+ *
+ * Configures the FTM to use an external global time base signal that is
+ * generated by another FTM.
+ *
+ * Values:
+ * - 0b0 - Use of an external global time base is disabled.
+ * - 0b1 - Use of an external global time base is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_GTBEEN field. */
+#define FTM_RD_CONF_GTBEEN(base) ((FTM_CONF_REG(base) & FTM_CONF_GTBEEN_MASK) >> FTM_CONF_GTBEEN_SHIFT)
+#define FTM_BRD_CONF_GTBEEN(base) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEEN_SHIFT))
+
+/*! @brief Set the GTBEEN field to a new value. */
+#define FTM_WR_CONF_GTBEEN(base, value) (FTM_RMW_CONF(base, FTM_CONF_GTBEEN_MASK, FTM_CONF_GTBEEN(value)))
+#define FTM_BWR_CONF_GTBEEN(base, value) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field GTBEOUT[10] (RW)
+ *
+ * Enables the global time base signal generation to other FTMs.
+ *
+ * Values:
+ * - 0b0 - A global time base signal generation is disabled.
+ * - 0b1 - A global time base signal generation is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_GTBEOUT field. */
+#define FTM_RD_CONF_GTBEOUT(base) ((FTM_CONF_REG(base) & FTM_CONF_GTBEOUT_MASK) >> FTM_CONF_GTBEOUT_SHIFT)
+#define FTM_BRD_CONF_GTBEOUT(base) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEOUT_SHIFT))
+
+/*! @brief Set the GTBEOUT field to a new value. */
+#define FTM_WR_CONF_GTBEOUT(base, value) (FTM_RMW_CONF(base, FTM_CONF_GTBEOUT_MASK, FTM_CONF_GTBEOUT(value)))
+#define FTM_BWR_CONF_GTBEOUT(base, value) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEOUT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FLTPOL - FTM Fault Input Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FLTPOL - FTM Fault Input Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the fault inputs polarity.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FLTPOL register
+ */
+/*@{*/
+#define FTM_RD_FLTPOL(base)      (FTM_FLTPOL_REG(base))
+#define FTM_WR_FLTPOL(base, value) (FTM_FLTPOL_REG(base) = (value))
+#define FTM_RMW_FLTPOL(base, mask, value) (FTM_WR_FLTPOL(base, (FTM_RD_FLTPOL(base) & ~(mask)) | (value)))
+#define FTM_SET_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) |  (value)))
+#define FTM_CLR_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) & ~(value)))
+#define FTM_TOG_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FLTPOL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */
+#define FTM_RD_FLTPOL_FLT0POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT0POL_MASK) >> FTM_FLTPOL_FLT0POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT0POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT0POL_SHIFT))
+
+/*! @brief Set the FLT0POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT0POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT0POL_MASK, FTM_FLTPOL_FLT0POL(value)))
+#define FTM_BWR_FLTPOL_FLT0POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT0POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */
+#define FTM_RD_FLTPOL_FLT1POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT1POL_MASK) >> FTM_FLTPOL_FLT1POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT1POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT1POL_SHIFT))
+
+/*! @brief Set the FLT1POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT1POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT1POL_MASK, FTM_FLTPOL_FLT1POL(value)))
+#define FTM_BWR_FLTPOL_FLT1POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT1POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */
+#define FTM_RD_FLTPOL_FLT2POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT2POL_MASK) >> FTM_FLTPOL_FLT2POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT2POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT2POL_SHIFT))
+
+/*! @brief Set the FLT2POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT2POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT2POL_MASK, FTM_FLTPOL_FLT2POL(value)))
+#define FTM_BWR_FLTPOL_FLT2POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT2POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */
+#define FTM_RD_FLTPOL_FLT3POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT3POL_MASK) >> FTM_FLTPOL_FLT3POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT3POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT3POL_SHIFT))
+
+/*! @brief Set the FLT3POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT3POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT3POL_MASK, FTM_FLTPOL_FLT3POL(value)))
+#define FTM_BWR_FLTPOL_FLT3POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT3POL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SYNCONF - Synchronization Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SYNCONF - Synchronization Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
+ * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
+ * 0, 1, 2, when the hardware trigger j is detected.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SYNCONF register
+ */
+/*@{*/
+#define FTM_RD_SYNCONF(base)     (FTM_SYNCONF_REG(base))
+#define FTM_WR_SYNCONF(base, value) (FTM_SYNCONF_REG(base) = (value))
+#define FTM_RMW_SYNCONF(base, mask, value) (FTM_WR_SYNCONF(base, (FTM_RD_SYNCONF(base) & ~(mask)) | (value)))
+#define FTM_SET_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) |  (value)))
+#define FTM_CLR_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) & ~(value)))
+#define FTM_TOG_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SYNCONF bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - FTM clears the TRIGj bit when the hardware trigger j is detected,
+ *     where j = 0, 1,2.
+ * - 0b1 - FTM does not clear the TRIGj bit when the hardware trigger j is
+ *     detected, where j = 0, 1,2.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */
+#define FTM_RD_SYNCONF_HWTRIGMODE(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWTRIGMODE_MASK) >> FTM_SYNCONF_HWTRIGMODE_SHIFT)
+#define FTM_BRD_SYNCONF_HWTRIGMODE(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWTRIGMODE_SHIFT))
+
+/*! @brief Set the HWTRIGMODE field to a new value. */
+#define FTM_WR_SYNCONF_HWTRIGMODE(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWTRIGMODE_MASK, FTM_SYNCONF_HWTRIGMODE(value)))
+#define FTM_BWR_SYNCONF_HWTRIGMODE(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWTRIGMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
+ *
+ * Values:
+ * - 0b0 - CNTIN register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - CNTIN register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */
+#define FTM_RD_SYNCONF_CNTINC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_CNTINC_MASK) >> FTM_SYNCONF_CNTINC_SHIFT)
+#define FTM_BRD_SYNCONF_CNTINC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_CNTINC_SHIFT))
+
+/*! @brief Set the CNTINC field to a new value. */
+#define FTM_WR_SYNCONF_CNTINC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_CNTINC_MASK, FTM_SYNCONF_CNTINC(value)))
+#define FTM_BWR_SYNCONF_CNTINC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_CNTINC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field INVC[4] (RW)
+ *
+ * Values:
+ * - 0b0 - INVCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - INVCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_INVC field. */
+#define FTM_RD_SYNCONF_INVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_INVC_MASK) >> FTM_SYNCONF_INVC_SHIFT)
+#define FTM_BRD_SYNCONF_INVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_INVC_SHIFT))
+
+/*! @brief Set the INVC field to a new value. */
+#define FTM_WR_SYNCONF_INVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_INVC_MASK, FTM_SYNCONF_INVC(value)))
+#define FTM_BWR_SYNCONF_INVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_INVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOC[5] (RW)
+ *
+ * Values:
+ * - 0b0 - SWOCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - SWOCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWOC field. */
+#define FTM_RD_SYNCONF_SWOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWOC_MASK) >> FTM_SYNCONF_SWOC_SHIFT)
+#define FTM_BRD_SYNCONF_SWOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOC_SHIFT))
+
+/*! @brief Set the SWOC field to a new value. */
+#define FTM_WR_SYNCONF_SWOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWOC_MASK, FTM_SYNCONF_SWOC(value)))
+#define FTM_BWR_SYNCONF_SWOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
+ *
+ * Selects the PWM Synchronization mode.
+ *
+ * Values:
+ * - 0b0 - Legacy PWM synchronization is selected.
+ * - 0b1 - Enhanced PWM synchronization is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */
+#define FTM_RD_SYNCONF_SYNCMODE(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SYNCMODE_MASK) >> FTM_SYNCONF_SYNCMODE_SHIFT)
+#define FTM_BRD_SYNCONF_SYNCMODE(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SYNCMODE_SHIFT))
+
+/*! @brief Set the SYNCMODE field to a new value. */
+#define FTM_WR_SYNCONF_SYNCMODE(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SYNCMODE_MASK, FTM_SYNCONF_SYNCMODE(value)))
+#define FTM_BWR_SYNCONF_SYNCMODE(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SYNCMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
+ *
+ * FTM counter synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the FTM counter
+ *     synchronization.
+ * - 0b1 - The software trigger activates the FTM counter synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */
+#define FTM_RD_SYNCONF_SWRSTCNT(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWRSTCNT_MASK) >> FTM_SYNCONF_SWRSTCNT_SHIFT)
+#define FTM_BRD_SYNCONF_SWRSTCNT(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWRSTCNT_SHIFT))
+
+/*! @brief Set the SWRSTCNT field to a new value. */
+#define FTM_WR_SYNCONF_SWRSTCNT(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWRSTCNT_MASK, FTM_SYNCONF_SWRSTCNT(value)))
+#define FTM_BWR_SYNCONF_SWRSTCNT(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWRSTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by the software
+ * trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 0b1 - The software trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */
+#define FTM_RD_SYNCONF_SWWRBUF(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWWRBUF_MASK) >> FTM_SYNCONF_SWWRBUF_SHIFT)
+#define FTM_BRD_SYNCONF_SWWRBUF(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWWRBUF_SHIFT))
+
+/*! @brief Set the SWWRBUF field to a new value. */
+#define FTM_WR_SYNCONF_SWWRBUF(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWWRBUF_MASK, FTM_SYNCONF_SWWRBUF(value)))
+#define FTM_BWR_SYNCONF_SWWRBUF(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWWRBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOM[10] (RW)
+ *
+ * Output mask synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the OUTMASK register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWOM field. */
+#define FTM_RD_SYNCONF_SWOM(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWOM_MASK) >> FTM_SYNCONF_SWOM_SHIFT)
+#define FTM_BRD_SYNCONF_SWOM(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOM_SHIFT))
+
+/*! @brief Set the SWOM field to a new value. */
+#define FTM_WR_SYNCONF_SWOM(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWOM_MASK, FTM_SYNCONF_SWOM(value)))
+#define FTM_BWR_SYNCONF_SWOM(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
+ *
+ * Inverting control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the INVCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */
+#define FTM_RD_SYNCONF_SWINVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWINVC_MASK) >> FTM_SYNCONF_SWINVC_SHIFT)
+#define FTM_BRD_SYNCONF_SWINVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWINVC_SHIFT))
+
+/*! @brief Set the SWINVC field to a new value. */
+#define FTM_WR_SYNCONF_SWINVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWINVC_MASK, FTM_SYNCONF_SWINVC(value)))
+#define FTM_BWR_SYNCONF_SWINVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWINVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
+ *
+ * Software output control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the SWOCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */
+#define FTM_RD_SYNCONF_SWSOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWSOC_MASK) >> FTM_SYNCONF_SWSOC_SHIFT)
+#define FTM_BRD_SYNCONF_SWSOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWSOC_SHIFT))
+
+/*! @brief Set the SWSOC field to a new value. */
+#define FTM_WR_SYNCONF_SWSOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWSOC_MASK, FTM_SYNCONF_SWSOC(value)))
+#define FTM_BWR_SYNCONF_SWSOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWSOC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
+ *
+ * FTM counter synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the FTM counter synchronization.
+ * - 0b1 - A hardware trigger activates the FTM counter synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */
+#define FTM_RD_SYNCONF_HWRSTCNT(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWRSTCNT_MASK) >> FTM_SYNCONF_HWRSTCNT_SHIFT)
+#define FTM_BRD_SYNCONF_HWRSTCNT(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWRSTCNT_SHIFT))
+
+/*! @brief Set the HWRSTCNT field to a new value. */
+#define FTM_WR_SYNCONF_HWRSTCNT(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWRSTCNT_MASK, FTM_SYNCONF_HWRSTCNT(value)))
+#define FTM_BWR_SYNCONF_HWRSTCNT(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWRSTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by a hardware
+ * trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */
+#define FTM_RD_SYNCONF_HWWRBUF(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWWRBUF_MASK) >> FTM_SYNCONF_HWWRBUF_SHIFT)
+#define FTM_BRD_SYNCONF_HWWRBUF(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWWRBUF_SHIFT))
+
+/*! @brief Set the HWWRBUF field to a new value. */
+#define FTM_WR_SYNCONF_HWWRBUF(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWWRBUF_MASK, FTM_SYNCONF_HWWRBUF(value)))
+#define FTM_BWR_SYNCONF_HWWRBUF(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWWRBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWOM[18] (RW)
+ *
+ * Output mask synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the OUTMASK register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWOM field. */
+#define FTM_RD_SYNCONF_HWOM(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWOM_MASK) >> FTM_SYNCONF_HWOM_SHIFT)
+#define FTM_BRD_SYNCONF_HWOM(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWOM_SHIFT))
+
+/*! @brief Set the HWOM field to a new value. */
+#define FTM_WR_SYNCONF_HWOM(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWOM_MASK, FTM_SYNCONF_HWOM(value)))
+#define FTM_BWR_SYNCONF_HWOM(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
+ *
+ * Inverting control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the INVCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */
+#define FTM_RD_SYNCONF_HWINVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWINVC_MASK) >> FTM_SYNCONF_HWINVC_SHIFT)
+#define FTM_BRD_SYNCONF_HWINVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWINVC_SHIFT))
+
+/*! @brief Set the HWINVC field to a new value. */
+#define FTM_WR_SYNCONF_HWINVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWINVC_MASK, FTM_SYNCONF_HWINVC(value)))
+#define FTM_BWR_SYNCONF_HWINVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWINVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
+ *
+ * Software output control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the SWOCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */
+#define FTM_RD_SYNCONF_HWSOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWSOC_MASK) >> FTM_SYNCONF_HWSOC_SHIFT)
+#define FTM_BRD_SYNCONF_HWSOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWSOC_SHIFT))
+
+/*! @brief Set the HWSOC field to a new value. */
+#define FTM_WR_SYNCONF_HWSOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWSOC_MASK, FTM_SYNCONF_HWSOC(value)))
+#define FTM_BWR_SYNCONF_HWSOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWSOC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_INVCTRL - FTM Inverting Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_INVCTRL - FTM Inverting Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls when the channel (n) output becomes the channel (n+1)
+ * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
+ * bit enables the inverting operation for the corresponding pair channels m. This
+ * register has a write buffer. The INVmEN bit is updated by the INVCTRL
+ * register synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_INVCTRL register
+ */
+/*@{*/
+#define FTM_RD_INVCTRL(base)     (FTM_INVCTRL_REG(base))
+#define FTM_WR_INVCTRL(base, value) (FTM_INVCTRL_REG(base) = (value))
+#define FTM_RMW_INVCTRL(base, mask, value) (FTM_WR_INVCTRL(base, (FTM_RD_INVCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) |  (value)))
+#define FTM_CLR_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) & ~(value)))
+#define FTM_TOG_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_INVCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */
+#define FTM_RD_INVCTRL_INV0EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV0EN_MASK) >> FTM_INVCTRL_INV0EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV0EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV0EN_SHIFT))
+
+/*! @brief Set the INV0EN field to a new value. */
+#define FTM_WR_INVCTRL_INV0EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV0EN_MASK, FTM_INVCTRL_INV0EN(value)))
+#define FTM_BWR_INVCTRL_INV0EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */
+#define FTM_RD_INVCTRL_INV1EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV1EN_MASK) >> FTM_INVCTRL_INV1EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV1EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV1EN_SHIFT))
+
+/*! @brief Set the INV1EN field to a new value. */
+#define FTM_WR_INVCTRL_INV1EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV1EN_MASK, FTM_INVCTRL_INV1EN(value)))
+#define FTM_BWR_INVCTRL_INV1EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */
+#define FTM_RD_INVCTRL_INV2EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV2EN_MASK) >> FTM_INVCTRL_INV2EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV2EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV2EN_SHIFT))
+
+/*! @brief Set the INV2EN field to a new value. */
+#define FTM_WR_INVCTRL_INV2EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV2EN_MASK, FTM_INVCTRL_INV2EN(value)))
+#define FTM_BWR_INVCTRL_INV2EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */
+#define FTM_RD_INVCTRL_INV3EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV3EN_MASK) >> FTM_INVCTRL_INV3EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV3EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV3EN_SHIFT))
+
+/*! @brief Set the INV3EN field to a new value. */
+#define FTM_WR_INVCTRL_INV3EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV3EN_MASK, FTM_INVCTRL_INV3EN(value)))
+#define FTM_BWR_INVCTRL_INV3EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV3EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SWOCTRL - FTM Software Output Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SWOCTRL - FTM Software Output Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register enables software control of channel (n) output and defines the
+ * value forced to the channel (n) output: The CHnOC bits enable the control of
+ * the corresponding channel (n) output by software. The CHnOCV bits select the
+ * value that is forced at the corresponding channel (n) output. This register has
+ * a write buffer. The fields are updated by the SWOCTRL register synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SWOCTRL register
+ */
+/*@{*/
+#define FTM_RD_SWOCTRL(base)     (FTM_SWOCTRL_REG(base))
+#define FTM_WR_SWOCTRL(base, value) (FTM_SWOCTRL_REG(base) = (value))
+#define FTM_RMW_SWOCTRL(base, mask, value) (FTM_WR_SWOCTRL(base, (FTM_RD_SWOCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) |  (value)))
+#define FTM_CLR_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) & ~(value)))
+#define FTM_TOG_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SWOCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */
+#define FTM_RD_SWOCTRL_CH0OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH0OC_MASK) >> FTM_SWOCTRL_CH0OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH0OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OC_SHIFT))
+
+/*! @brief Set the CH0OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH0OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH0OC_MASK, FTM_SWOCTRL_CH0OC(value)))
+#define FTM_BWR_SWOCTRL_CH0OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */
+#define FTM_RD_SWOCTRL_CH1OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH1OC_MASK) >> FTM_SWOCTRL_CH1OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH1OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OC_SHIFT))
+
+/*! @brief Set the CH1OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH1OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH1OC_MASK, FTM_SWOCTRL_CH1OC(value)))
+#define FTM_BWR_SWOCTRL_CH1OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */
+#define FTM_RD_SWOCTRL_CH2OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH2OC_MASK) >> FTM_SWOCTRL_CH2OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH2OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OC_SHIFT))
+
+/*! @brief Set the CH2OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH2OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH2OC_MASK, FTM_SWOCTRL_CH2OC(value)))
+#define FTM_BWR_SWOCTRL_CH2OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */
+#define FTM_RD_SWOCTRL_CH3OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH3OC_MASK) >> FTM_SWOCTRL_CH3OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH3OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OC_SHIFT))
+
+/*! @brief Set the CH3OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH3OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH3OC_MASK, FTM_SWOCTRL_CH3OC(value)))
+#define FTM_BWR_SWOCTRL_CH3OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */
+#define FTM_RD_SWOCTRL_CH4OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH4OC_MASK) >> FTM_SWOCTRL_CH4OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH4OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OC_SHIFT))
+
+/*! @brief Set the CH4OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH4OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH4OC_MASK, FTM_SWOCTRL_CH4OC(value)))
+#define FTM_BWR_SWOCTRL_CH4OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */
+#define FTM_RD_SWOCTRL_CH5OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH5OC_MASK) >> FTM_SWOCTRL_CH5OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH5OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OC_SHIFT))
+
+/*! @brief Set the CH5OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH5OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH5OC_MASK, FTM_SWOCTRL_CH5OC(value)))
+#define FTM_BWR_SWOCTRL_CH5OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */
+#define FTM_RD_SWOCTRL_CH6OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH6OC_MASK) >> FTM_SWOCTRL_CH6OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH6OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OC_SHIFT))
+
+/*! @brief Set the CH6OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH6OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH6OC_MASK, FTM_SWOCTRL_CH6OC(value)))
+#define FTM_BWR_SWOCTRL_CH6OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */
+#define FTM_RD_SWOCTRL_CH7OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH7OC_MASK) >> FTM_SWOCTRL_CH7OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH7OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OC_SHIFT))
+
+/*! @brief Set the CH7OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH7OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH7OC_MASK, FTM_SWOCTRL_CH7OC(value)))
+#define FTM_BWR_SWOCTRL_CH7OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */
+#define FTM_RD_SWOCTRL_CH0OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH0OCV_MASK) >> FTM_SWOCTRL_CH0OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH0OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OCV_SHIFT))
+
+/*! @brief Set the CH0OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH0OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH0OCV_MASK, FTM_SWOCTRL_CH0OCV(value)))
+#define FTM_BWR_SWOCTRL_CH0OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */
+#define FTM_RD_SWOCTRL_CH1OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH1OCV_MASK) >> FTM_SWOCTRL_CH1OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH1OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OCV_SHIFT))
+
+/*! @brief Set the CH1OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH1OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH1OCV_MASK, FTM_SWOCTRL_CH1OCV(value)))
+#define FTM_BWR_SWOCTRL_CH1OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */
+#define FTM_RD_SWOCTRL_CH2OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH2OCV_MASK) >> FTM_SWOCTRL_CH2OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH2OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OCV_SHIFT))
+
+/*! @brief Set the CH2OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH2OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH2OCV_MASK, FTM_SWOCTRL_CH2OCV(value)))
+#define FTM_BWR_SWOCTRL_CH2OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */
+#define FTM_RD_SWOCTRL_CH3OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH3OCV_MASK) >> FTM_SWOCTRL_CH3OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH3OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OCV_SHIFT))
+
+/*! @brief Set the CH3OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH3OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH3OCV_MASK, FTM_SWOCTRL_CH3OCV(value)))
+#define FTM_BWR_SWOCTRL_CH3OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */
+#define FTM_RD_SWOCTRL_CH4OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH4OCV_MASK) >> FTM_SWOCTRL_CH4OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH4OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OCV_SHIFT))
+
+/*! @brief Set the CH4OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH4OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH4OCV_MASK, FTM_SWOCTRL_CH4OCV(value)))
+#define FTM_BWR_SWOCTRL_CH4OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */
+#define FTM_RD_SWOCTRL_CH5OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH5OCV_MASK) >> FTM_SWOCTRL_CH5OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH5OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OCV_SHIFT))
+
+/*! @brief Set the CH5OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH5OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH5OCV_MASK, FTM_SWOCTRL_CH5OCV(value)))
+#define FTM_BWR_SWOCTRL_CH5OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */
+#define FTM_RD_SWOCTRL_CH6OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH6OCV_MASK) >> FTM_SWOCTRL_CH6OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH6OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OCV_SHIFT))
+
+/*! @brief Set the CH6OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH6OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH6OCV_MASK, FTM_SWOCTRL_CH6OCV(value)))
+#define FTM_BWR_SWOCTRL_CH6OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */
+#define FTM_RD_SWOCTRL_CH7OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH7OCV_MASK) >> FTM_SWOCTRL_CH7OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH7OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OCV_SHIFT))
+
+/*! @brief Set the CH7OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH7OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH7OCV_MASK, FTM_SWOCTRL_CH7OCV(value)))
+#define FTM_BWR_SWOCTRL_CH7OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OCV_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_PWMLOAD - FTM PWM Load
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_PWMLOAD - FTM PWM Load (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
+ * values of their write buffers when the FTM counter changes from the MOD
+ * register value to its next value or when a channel (j) match occurs. A match occurs
+ * for the channel (j) when FTM counter = C(j)V.
+ */
+/*!
+ * @name Constants and macros for entire FTM_PWMLOAD register
+ */
+/*@{*/
+#define FTM_RD_PWMLOAD(base)     (FTM_PWMLOAD_REG(base))
+#define FTM_WR_PWMLOAD(base, value) (FTM_PWMLOAD_REG(base) = (value))
+#define FTM_RMW_PWMLOAD(base, mask, value) (FTM_WR_PWMLOAD(base, (FTM_RD_PWMLOAD(base) & ~(mask)) | (value)))
+#define FTM_SET_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) |  (value)))
+#define FTM_CLR_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) & ~(value)))
+#define FTM_TOG_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_PWMLOAD bitfields
+ */
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */
+#define FTM_RD_PWMLOAD_CH0SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH0SEL_MASK) >> FTM_PWMLOAD_CH0SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH0SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH0SEL_SHIFT))
+
+/*! @brief Set the CH0SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH0SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH0SEL_MASK, FTM_PWMLOAD_CH0SEL(value)))
+#define FTM_BWR_PWMLOAD_CH0SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH0SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */
+#define FTM_RD_PWMLOAD_CH1SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH1SEL_MASK) >> FTM_PWMLOAD_CH1SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH1SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH1SEL_SHIFT))
+
+/*! @brief Set the CH1SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH1SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH1SEL_MASK, FTM_PWMLOAD_CH1SEL(value)))
+#define FTM_BWR_PWMLOAD_CH1SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH1SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */
+#define FTM_RD_PWMLOAD_CH2SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH2SEL_MASK) >> FTM_PWMLOAD_CH2SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH2SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH2SEL_SHIFT))
+
+/*! @brief Set the CH2SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH2SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH2SEL_MASK, FTM_PWMLOAD_CH2SEL(value)))
+#define FTM_BWR_PWMLOAD_CH2SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH2SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */
+#define FTM_RD_PWMLOAD_CH3SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH3SEL_MASK) >> FTM_PWMLOAD_CH3SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH3SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH3SEL_SHIFT))
+
+/*! @brief Set the CH3SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH3SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH3SEL_MASK, FTM_PWMLOAD_CH3SEL(value)))
+#define FTM_BWR_PWMLOAD_CH3SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH3SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */
+#define FTM_RD_PWMLOAD_CH4SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH4SEL_MASK) >> FTM_PWMLOAD_CH4SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH4SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH4SEL_SHIFT))
+
+/*! @brief Set the CH4SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH4SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH4SEL_MASK, FTM_PWMLOAD_CH4SEL(value)))
+#define FTM_BWR_PWMLOAD_CH4SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH4SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */
+#define FTM_RD_PWMLOAD_CH5SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH5SEL_MASK) >> FTM_PWMLOAD_CH5SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH5SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH5SEL_SHIFT))
+
+/*! @brief Set the CH5SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH5SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH5SEL_MASK, FTM_PWMLOAD_CH5SEL(value)))
+#define FTM_BWR_PWMLOAD_CH5SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH5SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */
+#define FTM_RD_PWMLOAD_CH6SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH6SEL_MASK) >> FTM_PWMLOAD_CH6SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH6SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH6SEL_SHIFT))
+
+/*! @brief Set the CH6SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH6SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH6SEL_MASK, FTM_PWMLOAD_CH6SEL(value)))
+#define FTM_BWR_PWMLOAD_CH6SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH6SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */
+#define FTM_RD_PWMLOAD_CH7SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH7SEL_MASK) >> FTM_PWMLOAD_CH7SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH7SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH7SEL_SHIFT))
+
+/*! @brief Set the CH7SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH7SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH7SEL_MASK, FTM_PWMLOAD_CH7SEL(value)))
+#define FTM_BWR_PWMLOAD_CH7SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH7SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
+ *
+ * Enables the loading of the MOD, CNTIN, and CV registers with the values of
+ * their write buffers.
+ *
+ * Values:
+ * - 0b0 - Loading updated values is disabled.
+ * - 0b1 - Loading updated values is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */
+#define FTM_RD_PWMLOAD_LDOK(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_LDOK_MASK) >> FTM_PWMLOAD_LDOK_SHIFT)
+#define FTM_BRD_PWMLOAD_LDOK(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_LDOK_SHIFT))
+
+/*! @brief Set the LDOK field to a new value. */
+#define FTM_WR_PWMLOAD_LDOK(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_LDOK_MASK, FTM_PWMLOAD_LDOK(value)))
+#define FTM_BWR_PWMLOAD_LDOK(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_LDOK_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 GPIO
+ *
+ * General Purpose Input/Output
+ *
+ * Registers defined in this header file:
+ * - GPIO_PDOR - Port Data Output Register
+ * - GPIO_PSOR - Port Set Output Register
+ * - GPIO_PCOR - Port Clear Output Register
+ * - GPIO_PTOR - Port Toggle Output Register
+ * - GPIO_PDIR - Port Data Input Register
+ * - GPIO_PDDR - Port Data Direction Register
+ */
+
+#define GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
+#define GPIOA_IDX (0U) /*!< Instance number for GPIOA. */
+#define GPIOB_IDX (1U) /*!< Instance number for GPIOB. */
+#define GPIOC_IDX (2U) /*!< Instance number for GPIOC. */
+#define GPIOD_IDX (3U) /*!< Instance number for GPIOD. */
+#define GPIOE_IDX (4U) /*!< Instance number for GPIOE. */
+
+/*******************************************************************************
+ * GPIO_PDOR - Port Data Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDOR - Port Data Output Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the logic levels that are driven on each
+ * general-purpose output pins. Do not modify pin configuration registers associated with
+ * pins not available in your selected package. All unbonded pins not available in
+ * your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDOR register
+ */
+/*@{*/
+#define GPIO_RD_PDOR(base)       (GPIO_PDOR_REG(base))
+#define GPIO_WR_PDOR(base, value) (GPIO_PDOR_REG(base) = (value))
+#define GPIO_RMW_PDOR(base, mask, value) (GPIO_WR_PDOR(base, (GPIO_RD_PDOR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) |  (value)))
+#define GPIO_CLR_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) & ~(value)))
+#define GPIO_TOG_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PSOR - Port Set Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PSOR - Port Set Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to set the fields of the PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PSOR register
+ */
+/*@{*/
+#define GPIO_RD_PSOR(base)       (GPIO_PSOR_REG(base))
+#define GPIO_WR_PSOR(base, value) (GPIO_PSOR_REG(base) = (value))
+#define GPIO_RMW_PSOR(base, mask, value) (GPIO_WR_PSOR(base, (GPIO_RD_PSOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PCOR - Port Clear Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PCOR - Port Clear Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to clear the fields of PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PCOR register
+ */
+/*@{*/
+#define GPIO_RD_PCOR(base)       (GPIO_PCOR_REG(base))
+#define GPIO_WR_PCOR(base, value) (GPIO_PCOR_REG(base) = (value))
+#define GPIO_RMW_PCOR(base, mask, value) (GPIO_WR_PCOR(base, (GPIO_RD_PCOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PTOR - Port Toggle Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PTOR - Port Toggle Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PTOR register
+ */
+/*@{*/
+#define GPIO_RD_PTOR(base)       (GPIO_PTOR_REG(base))
+#define GPIO_WR_PTOR(base, value) (GPIO_PTOR_REG(base) = (value))
+#define GPIO_RMW_PTOR(base, mask, value) (GPIO_WR_PTOR(base, (GPIO_RD_PTOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDIR - Port Data Input Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDIR - Port Data Input Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Do not modify pin configuration registers associated with pins not available
+ * in your selected package. All unbonded pins not available in your package will
+ * default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDIR register
+ */
+/*@{*/
+#define GPIO_RD_PDIR(base)       (GPIO_PDIR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDDR - Port Data Direction Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDDR - Port Data Direction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The PDDR configures the individual port pins for input or output.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDDR register
+ */
+/*@{*/
+#define GPIO_RD_PDDR(base)       (GPIO_PDDR_REG(base))
+#define GPIO_WR_PDDR(base, value) (GPIO_PDDR_REG(base) = (value))
+#define GPIO_RMW_PDDR(base, mask, value) (GPIO_WR_PDDR(base, (GPIO_RD_PDDR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) |  (value)))
+#define GPIO_CLR_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) & ~(value)))
+#define GPIO_TOG_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 I2C
+ *
+ * Inter-Integrated Circuit
+ *
+ * Registers defined in this header file:
+ * - I2C_A1 - I2C Address Register 1
+ * - I2C_F - I2C Frequency Divider register
+ * - I2C_C1 - I2C Control Register 1
+ * - I2C_S - I2C Status register
+ * - I2C_D - I2C Data I/O register
+ * - I2C_C2 - I2C Control Register 2
+ * - I2C_FLT - I2C Programmable Input Glitch Filter register
+ * - I2C_RA - I2C Range Address register
+ * - I2C_SMB - I2C SMBus Control and Status register
+ * - I2C_A2 - I2C Address Register 2
+ * - I2C_SLTH - I2C SCL Low Timeout Register High
+ * - I2C_SLTL - I2C SCL Low Timeout Register Low
+ */
+
+#define I2C_INSTANCE_COUNT (3U) /*!< Number of instances of the I2C module. */
+#define I2C0_IDX (0U) /*!< Instance number for I2C0. */
+#define I2C1_IDX (1U) /*!< Instance number for I2C1. */
+#define I2C2_IDX (2U) /*!< Instance number for I2C2. */
+
+/*******************************************************************************
+ * I2C_A1 - I2C Address Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A1 - I2C Address Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the slave address to be used by the I2C module.
+ */
+/*!
+ * @name Constants and macros for entire I2C_A1 register
+ */
+/*@{*/
+#define I2C_RD_A1(base)          (I2C_A1_REG(base))
+#define I2C_WR_A1(base, value)   (I2C_A1_REG(base) = (value))
+#define I2C_RMW_A1(base, mask, value) (I2C_WR_A1(base, (I2C_RD_A1(base) & ~(mask)) | (value)))
+#define I2C_SET_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) |  (value)))
+#define I2C_CLR_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) & ~(value)))
+#define I2C_TOG_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A1 bitfields
+ */
+
+/*!
+ * @name Register I2C_A1, field AD[7:1] (RW)
+ *
+ * Contains the primary slave address used by the I2C module when it is
+ * addressed as a slave. This field is used in the 7-bit address scheme and the lower
+ * seven bits in the 10-bit address scheme.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A1_AD field. */
+#define I2C_RD_A1_AD(base)   ((I2C_A1_REG(base) & I2C_A1_AD_MASK) >> I2C_A1_AD_SHIFT)
+#define I2C_BRD_A1_AD(base)  (I2C_RD_A1_AD(base))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_A1_AD(base, value) (I2C_RMW_A1(base, I2C_A1_AD_MASK, I2C_A1_AD(value)))
+#define I2C_BWR_A1_AD(base, value) (I2C_WR_A1_AD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_F - I2C Frequency Divider register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_F - I2C Frequency Divider register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_F register
+ */
+/*@{*/
+#define I2C_RD_F(base)           (I2C_F_REG(base))
+#define I2C_WR_F(base, value)    (I2C_F_REG(base) = (value))
+#define I2C_RMW_F(base, mask, value) (I2C_WR_F(base, (I2C_RD_F(base) & ~(mask)) | (value)))
+#define I2C_SET_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) |  (value)))
+#define I2C_CLR_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) & ~(value)))
+#define I2C_TOG_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_F bitfields
+ */
+
+/*!
+ * @name Register I2C_F, field ICR[5:0] (RW)
+ *
+ * Prescales the I2C module clock for bit rate selection. This field and the
+ * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
+ * time, and the SCL stop hold time. For a list of values corresponding to each ICR
+ * setting, see I2C divider and hold values. The SCL divider multiplied by
+ * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
+ * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
+ * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
+ * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
+ * the delay from the falling edge of SDA (I2C data) while SCL is high (start
+ * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
+ * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
+ * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
+ * data) while SCL is high (stop condition). SCL stop hold time = I2C module
+ * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
+ * speed is 8 MHz, the following table shows the possible hold time values with
+ * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
+ * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h
+ * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
+ * 1.125 4.750 5.125
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_ICR field. */
+#define I2C_RD_F_ICR(base)   ((I2C_F_REG(base) & I2C_F_ICR_MASK) >> I2C_F_ICR_SHIFT)
+#define I2C_BRD_F_ICR(base)  (I2C_RD_F_ICR(base))
+
+/*! @brief Set the ICR field to a new value. */
+#define I2C_WR_F_ICR(base, value) (I2C_RMW_F(base, I2C_F_ICR_MASK, I2C_F_ICR(value)))
+#define I2C_BWR_F_ICR(base, value) (I2C_WR_F_ICR(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_F, field MULT[7:6] (RW)
+ *
+ * Defines the multiplier factor (mul). This factor is used along with the SCL
+ * divider to generate the I2C baud rate.
+ *
+ * Values:
+ * - 0b00 - mul = 1
+ * - 0b01 - mul = 2
+ * - 0b10 - mul = 4
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_MULT field. */
+#define I2C_RD_F_MULT(base)  ((I2C_F_REG(base) & I2C_F_MULT_MASK) >> I2C_F_MULT_SHIFT)
+#define I2C_BRD_F_MULT(base) (I2C_RD_F_MULT(base))
+
+/*! @brief Set the MULT field to a new value. */
+#define I2C_WR_F_MULT(base, value) (I2C_RMW_F(base, I2C_F_MULT_MASK, I2C_F_MULT(value)))
+#define I2C_BWR_F_MULT(base, value) (I2C_WR_F_MULT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C1 - I2C Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C1 - I2C Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C1 register
+ */
+/*@{*/
+#define I2C_RD_C1(base)          (I2C_C1_REG(base))
+#define I2C_WR_C1(base, value)   (I2C_C1_REG(base) = (value))
+#define I2C_RMW_C1(base, mask, value) (I2C_WR_C1(base, (I2C_RD_C1(base) & ~(mask)) | (value)))
+#define I2C_SET_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) |  (value)))
+#define I2C_CLR_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) & ~(value)))
+#define I2C_TOG_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C1 bitfields
+ */
+
+/*!
+ * @name Register I2C_C1, field DMAEN[0] (RW)
+ *
+ * Enables or disables the DMA function.
+ *
+ * Values:
+ * - 0b0 - All DMA signalling disabled.
+ * - 0b1 - DMA transfer is enabled. While SMB[FACK] = 0, the following
+ *     conditions trigger the DMA request: a data byte is received, and either address or
+ *     data is transmitted. (ACK/NACK is automatic) the first byte received
+ *     matches the A1 register or is a general call address. If any address matching
+ *     occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
+ *     from master to slave, then it is not required to check S[SRW]. With this
+ *     assumption, DMA can also be used in this case. In other cases, if the master
+ *     reads data from the slave, then it is required to rewrite the C1 register
+ *     operation. With this assumption, DMA cannot be used. When FACK = 1, an
+ *     address or a data byte is transmitted.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_DMAEN field. */
+#define I2C_RD_C1_DMAEN(base) ((I2C_C1_REG(base) & I2C_C1_DMAEN_MASK) >> I2C_C1_DMAEN_SHIFT)
+#define I2C_BRD_C1_DMAEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define I2C_WR_C1_DMAEN(base, value) (I2C_RMW_C1(base, I2C_C1_DMAEN_MASK, I2C_C1_DMAEN(value)))
+#define I2C_BWR_C1_DMAEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field WUEN[1] (RW)
+ *
+ * The I2C module can wake the MCU from low power mode with no peripheral bus
+ * running when slave address matching occurs.
+ *
+ * Values:
+ * - 0b0 - Normal operation. No interrupt generated when address matching in low
+ *     power mode.
+ * - 0b1 - Enables the wakeup function in low power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_WUEN field. */
+#define I2C_RD_C1_WUEN(base) ((I2C_C1_REG(base) & I2C_C1_WUEN_MASK) >> I2C_C1_WUEN_SHIFT)
+#define I2C_BRD_C1_WUEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT))
+
+/*! @brief Set the WUEN field to a new value. */
+#define I2C_WR_C1_WUEN(base, value) (I2C_RMW_C1(base, I2C_C1_WUEN_MASK, I2C_C1_WUEN(value)))
+#define I2C_BWR_C1_WUEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field RSTA[2] (WORZ)
+ *
+ * Writing 1 to this bit generates a repeated START condition provided it is the
+ * current master. This bit will always be read as 0. Attempting a repeat at the
+ * wrong time results in loss of arbitration.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define I2C_WR_C1_RSTA(base, value) (I2C_RMW_C1(base, I2C_C1_RSTA_MASK, I2C_C1_RSTA(value)))
+#define I2C_BWR_C1_RSTA(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_RSTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TXAK[3] (RW)
+ *
+ * Specifies the value driven onto the SDA during data acknowledge cycles for
+ * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
+ * generation. SCL is held low until TXAK is written.
+ *
+ * Values:
+ * - 0b0 - An acknowledge signal is sent to the bus on the following receiving
+ *     byte (if FACK is cleared) or the current receiving byte (if FACK is set).
+ * - 0b1 - No acknowledge signal is sent to the bus on the following receiving
+ *     data byte (if FACK is cleared) or the current receiving data byte (if FACK
+ *     is set).
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TXAK field. */
+#define I2C_RD_C1_TXAK(base) ((I2C_C1_REG(base) & I2C_C1_TXAK_MASK) >> I2C_C1_TXAK_SHIFT)
+#define I2C_BRD_C1_TXAK(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT))
+
+/*! @brief Set the TXAK field to a new value. */
+#define I2C_WR_C1_TXAK(base, value) (I2C_RMW_C1(base, I2C_C1_TXAK_MASK, I2C_C1_TXAK(value)))
+#define I2C_BWR_C1_TXAK(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TX[4] (RW)
+ *
+ * Selects the direction of master and slave transfers. In master mode this bit
+ * must be set according to the type of transfer required. Therefore, for address
+ * cycles, this bit is always set. When addressed as a slave this bit must be
+ * set by software according to the SRW bit in the status register.
+ *
+ * Values:
+ * - 0b0 - Receive
+ * - 0b1 - Transmit
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TX field. */
+#define I2C_RD_C1_TX(base)   ((I2C_C1_REG(base) & I2C_C1_TX_MASK) >> I2C_C1_TX_SHIFT)
+#define I2C_BRD_C1_TX(base)  (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT))
+
+/*! @brief Set the TX field to a new value. */
+#define I2C_WR_C1_TX(base, value) (I2C_RMW_C1(base, I2C_C1_TX_MASK, I2C_C1_TX(value)))
+#define I2C_BWR_C1_TX(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field MST[5] (RW)
+ *
+ * When MST is changed from 0 to 1, a START signal is generated on the bus and
+ * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
+ * generated and the mode of operation changes from master to slave.
+ *
+ * Values:
+ * - 0b0 - Slave mode
+ * - 0b1 - Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_MST field. */
+#define I2C_RD_C1_MST(base)  ((I2C_C1_REG(base) & I2C_C1_MST_MASK) >> I2C_C1_MST_SHIFT)
+#define I2C_BRD_C1_MST(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT))
+
+/*! @brief Set the MST field to a new value. */
+#define I2C_WR_C1_MST(base, value) (I2C_RMW_C1(base, I2C_C1_MST_MASK, I2C_C1_MST(value)))
+#define I2C_BWR_C1_MST(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICIE[6] (RW)
+ *
+ * Enables I2C interrupt requests.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICIE field. */
+#define I2C_RD_C1_IICIE(base) ((I2C_C1_REG(base) & I2C_C1_IICIE_MASK) >> I2C_C1_IICIE_SHIFT)
+#define I2C_BRD_C1_IICIE(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT))
+
+/*! @brief Set the IICIE field to a new value. */
+#define I2C_WR_C1_IICIE(base, value) (I2C_RMW_C1(base, I2C_C1_IICIE_MASK, I2C_C1_IICIE(value)))
+#define I2C_BWR_C1_IICIE(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICEN[7] (RW)
+ *
+ * Enables I2C module operation.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICEN field. */
+#define I2C_RD_C1_IICEN(base) ((I2C_C1_REG(base) & I2C_C1_IICEN_MASK) >> I2C_C1_IICEN_SHIFT)
+#define I2C_BRD_C1_IICEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT))
+
+/*! @brief Set the IICEN field to a new value. */
+#define I2C_WR_C1_IICEN(base, value) (I2C_RMW_C1(base, I2C_C1_IICEN_MASK, I2C_C1_IICEN(value)))
+#define I2C_BWR_C1_IICEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_S - I2C Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_S - I2C Status register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire I2C_S register
+ */
+/*@{*/
+#define I2C_RD_S(base)           (I2C_S_REG(base))
+#define I2C_WR_S(base, value)    (I2C_S_REG(base) = (value))
+#define I2C_RMW_S(base, mask, value) (I2C_WR_S(base, (I2C_RD_S(base) & ~(mask)) | (value)))
+#define I2C_SET_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) |  (value)))
+#define I2C_CLR_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) & ~(value)))
+#define I2C_TOG_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_S bitfields
+ */
+
+/*!
+ * @name Register I2C_S, field RXAK[0] (RO)
+ *
+ * Values:
+ * - 0b0 - Acknowledge signal was received after the completion of one byte of
+ *     data transmission on the bus
+ * - 0b1 - No acknowledge signal detected
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RXAK field. */
+#define I2C_RD_S_RXAK(base)  ((I2C_S_REG(base) & I2C_S_RXAK_MASK) >> I2C_S_RXAK_SHIFT)
+#define I2C_BRD_S_RXAK(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RXAK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IICIF[1] (W1C)
+ *
+ * This bit sets when an interrupt is pending. This bit must be cleared by
+ * software by writing 1 to it, such as in the interrupt routine. One of the following
+ * events can set this bit: One byte transfer, including ACK/NACK bit, completes
+ * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
+ * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
+ * completes if FACK is 1. Match of slave address to calling address including
+ * primary slave address, range slave address , alert response address, second
+ * slave address, or general call address. Arbitration lost In SMBus mode, any
+ * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
+ * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
+ * start detection interrupt: In the interrupt service routine, first clear the
+ * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
+ * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
+ * asserted again.
+ *
+ * Values:
+ * - 0b0 - No interrupt pending
+ * - 0b1 - Interrupt pending
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IICIF field. */
+#define I2C_RD_S_IICIF(base) ((I2C_S_REG(base) & I2C_S_IICIF_MASK) >> I2C_S_IICIF_SHIFT)
+#define I2C_BRD_S_IICIF(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT))
+
+/*! @brief Set the IICIF field to a new value. */
+#define I2C_WR_S_IICIF(base, value) (I2C_RMW_S(base, (I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IICIF(value)))
+#define I2C_BWR_S_IICIF(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field SRW[2] (RO)
+ *
+ * When addressed as a slave, SRW indicates the value of the R/W command bit of
+ * the calling address sent to the master.
+ *
+ * Values:
+ * - 0b0 - Slave receive, master writing to slave
+ * - 0b1 - Slave transmit, master reading from slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_SRW field. */
+#define I2C_RD_S_SRW(base)   ((I2C_S_REG(base) & I2C_S_SRW_MASK) >> I2C_S_SRW_SHIFT)
+#define I2C_BRD_S_SRW(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_SRW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field RAM[3] (RW)
+ *
+ * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
+ * Any nonzero calling address is received that matches the address in the RA
+ * register. The calling address is within the range of values of the A1 and RA
+ * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
+ * Writing the C1 register with any value clears this bit to 0.
+ *
+ * Values:
+ * - 0b0 - Not addressed
+ * - 0b1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RAM field. */
+#define I2C_RD_S_RAM(base)   ((I2C_S_REG(base) & I2C_S_RAM_MASK) >> I2C_S_RAM_SHIFT)
+#define I2C_BRD_S_RAM(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RAM_SHIFT))
+
+/*! @brief Set the RAM field to a new value. */
+#define I2C_WR_S_RAM(base, value) (I2C_RMW_S(base, (I2C_S_RAM_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_RAM(value)))
+#define I2C_BWR_S_RAM(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RAM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field ARBL[4] (W1C)
+ *
+ * This bit is set by hardware when the arbitration procedure is lost. The ARBL
+ * bit must be cleared by software, by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - Standard bus operation.
+ * - 0b1 - Loss of arbitration.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_ARBL field. */
+#define I2C_RD_S_ARBL(base)  ((I2C_S_REG(base) & I2C_S_ARBL_MASK) >> I2C_S_ARBL_SHIFT)
+#define I2C_BRD_S_ARBL(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT))
+
+/*! @brief Set the ARBL field to a new value. */
+#define I2C_WR_S_ARBL(base, value) (I2C_RMW_S(base, (I2C_S_ARBL_MASK | I2C_S_IICIF_MASK), I2C_S_ARBL(value)))
+#define I2C_BWR_S_ARBL(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field BUSY[5] (RO)
+ *
+ * Indicates the status of the bus regardless of slave or master mode. This bit
+ * is set when a START signal is detected and cleared when a STOP signal is
+ * detected.
+ *
+ * Values:
+ * - 0b0 - Bus is idle
+ * - 0b1 - Bus is busy
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_BUSY field. */
+#define I2C_RD_S_BUSY(base)  ((I2C_S_REG(base) & I2C_S_BUSY_MASK) >> I2C_S_BUSY_SHIFT)
+#define I2C_BRD_S_BUSY(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_BUSY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IAAS[6] (RW)
+ *
+ * This bit is set by one of the following conditions: The calling address
+ * matches the programmed primary slave address in the A1 register, or matches the
+ * range address in the RA register (which must be set to a nonzero value and under
+ * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
+ * received. SMB[SIICAEN] is set and the calling address matches the second programmed
+ * slave address. ALERTEN is set and an SMBus alert response address is received
+ * RMEN is set and an address is received that is within the range between the
+ * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
+ * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
+ * value clears this bit.
+ *
+ * Values:
+ * - 0b0 - Not addressed
+ * - 0b1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IAAS field. */
+#define I2C_RD_S_IAAS(base)  ((I2C_S_REG(base) & I2C_S_IAAS_MASK) >> I2C_S_IAAS_SHIFT)
+#define I2C_BRD_S_IAAS(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT))
+
+/*! @brief Set the IAAS field to a new value. */
+#define I2C_WR_S_IAAS(base, value) (I2C_RMW_S(base, (I2C_S_IAAS_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IAAS(value)))
+#define I2C_BWR_S_IAAS(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field TCF[7] (RO)
+ *
+ * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
+ * This bit is valid only during or immediately following a transfer to or from
+ * the I2C module. TCF is cleared by reading the I2C data register in receive mode
+ * or by writing to the I2C data register in transmit mode.
+ *
+ * Values:
+ * - 0b0 - Transfer in progress
+ * - 0b1 - Transfer complete
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_TCF field. */
+#define I2C_RD_S_TCF(base)   ((I2C_S_REG(base) & I2C_S_TCF_MASK) >> I2C_S_TCF_SHIFT)
+#define I2C_BRD_S_TCF(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_TCF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_D - I2C Data I/O register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_D - I2C Data I/O register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_D register
+ */
+/*@{*/
+#define I2C_RD_D(base)           (I2C_D_REG(base))
+#define I2C_WR_D(base, value)    (I2C_D_REG(base) = (value))
+#define I2C_RMW_D(base, mask, value) (I2C_WR_D(base, (I2C_RD_D(base) & ~(mask)) | (value)))
+#define I2C_SET_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) |  (value)))
+#define I2C_CLR_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) & ~(value)))
+#define I2C_TOG_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C2 - I2C Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C2 - I2C Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C2 register
+ */
+/*@{*/
+#define I2C_RD_C2(base)          (I2C_C2_REG(base))
+#define I2C_WR_C2(base, value)   (I2C_C2_REG(base) = (value))
+#define I2C_RMW_C2(base, mask, value) (I2C_WR_C2(base, (I2C_RD_C2(base) & ~(mask)) | (value)))
+#define I2C_SET_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) |  (value)))
+#define I2C_CLR_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) & ~(value)))
+#define I2C_TOG_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C2 bitfields
+ */
+
+/*!
+ * @name Register I2C_C2, field AD[2:0] (RW)
+ *
+ * Contains the upper three bits of the slave address in the 10-bit address
+ * scheme. This field is valid only while the ADEXT bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_AD field. */
+#define I2C_RD_C2_AD(base)   ((I2C_C2_REG(base) & I2C_C2_AD_MASK) >> I2C_C2_AD_SHIFT)
+#define I2C_BRD_C2_AD(base)  (I2C_RD_C2_AD(base))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_C2_AD(base, value) (I2C_RMW_C2(base, I2C_C2_AD_MASK, I2C_C2_AD(value)))
+#define I2C_BWR_C2_AD(base, value) (I2C_WR_C2_AD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field RMEN[3] (RW)
+ *
+ * This bit controls the slave address matching for addresses between the values
+ * of the A1 and RA registers. When this bit is set, a slave address matching
+ * occurs for any address greater than the value of the A1 register and less than
+ * or equal to the value of the RA register.
+ *
+ * Values:
+ * - 0b0 - Range mode disabled. No address matching occurs for an address within
+ *     the range of values of the A1 and RA registers.
+ * - 0b1 - Range mode enabled. Address matching occurs when a slave receives an
+ *     address within the range of values of the A1 and RA registers.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_RMEN field. */
+#define I2C_RD_C2_RMEN(base) ((I2C_C2_REG(base) & I2C_C2_RMEN_MASK) >> I2C_C2_RMEN_SHIFT)
+#define I2C_BRD_C2_RMEN(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT))
+
+/*! @brief Set the RMEN field to a new value. */
+#define I2C_WR_C2_RMEN(base, value) (I2C_RMW_C2(base, I2C_C2_RMEN_MASK, I2C_C2_RMEN(value)))
+#define I2C_BWR_C2_RMEN(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field SBRC[4] (RW)
+ *
+ * Enables independent slave mode baud rate at maximum frequency, which forces
+ * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
+ * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
+ * capture the master's data at only 10 kbit/s.
+ *
+ * Values:
+ * - 0b0 - The slave baud rate follows the master baud rate and clock stretching
+ *     may occur
+ * - 0b1 - Slave baud rate is independent of the master baud rate
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_SBRC field. */
+#define I2C_RD_C2_SBRC(base) ((I2C_C2_REG(base) & I2C_C2_SBRC_MASK) >> I2C_C2_SBRC_SHIFT)
+#define I2C_BRD_C2_SBRC(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT))
+
+/*! @brief Set the SBRC field to a new value. */
+#define I2C_WR_C2_SBRC(base, value) (I2C_RMW_C2(base, I2C_C2_SBRC_MASK, I2C_C2_SBRC(value)))
+#define I2C_BWR_C2_SBRC(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field HDRS[5] (RW)
+ *
+ * Controls the drive capability of the I2C pads.
+ *
+ * Values:
+ * - 0b0 - Normal drive mode
+ * - 0b1 - High drive mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_HDRS field. */
+#define I2C_RD_C2_HDRS(base) ((I2C_C2_REG(base) & I2C_C2_HDRS_MASK) >> I2C_C2_HDRS_SHIFT)
+#define I2C_BRD_C2_HDRS(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT))
+
+/*! @brief Set the HDRS field to a new value. */
+#define I2C_WR_C2_HDRS(base, value) (I2C_RMW_C2(base, I2C_C2_HDRS_MASK, I2C_C2_HDRS(value)))
+#define I2C_BWR_C2_HDRS(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field ADEXT[6] (RW)
+ *
+ * Controls the number of bits used for the slave address.
+ *
+ * Values:
+ * - 0b0 - 7-bit address scheme
+ * - 0b1 - 10-bit address scheme
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_ADEXT field. */
+#define I2C_RD_C2_ADEXT(base) ((I2C_C2_REG(base) & I2C_C2_ADEXT_MASK) >> I2C_C2_ADEXT_SHIFT)
+#define I2C_BRD_C2_ADEXT(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT))
+
+/*! @brief Set the ADEXT field to a new value. */
+#define I2C_WR_C2_ADEXT(base, value) (I2C_RMW_C2(base, I2C_C2_ADEXT_MASK, I2C_C2_ADEXT(value)))
+#define I2C_BWR_C2_ADEXT(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field GCAEN[7] (RW)
+ *
+ * Enables general call address.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_GCAEN field. */
+#define I2C_RD_C2_GCAEN(base) ((I2C_C2_REG(base) & I2C_C2_GCAEN_MASK) >> I2C_C2_GCAEN_SHIFT)
+#define I2C_BRD_C2_GCAEN(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT))
+
+/*! @brief Set the GCAEN field to a new value. */
+#define I2C_WR_C2_GCAEN(base, value) (I2C_RMW_C2(base, I2C_C2_GCAEN_MASK, I2C_C2_GCAEN(value)))
+#define I2C_BWR_C2_GCAEN(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_FLT - I2C Programmable Input Glitch Filter register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_FLT register
+ */
+/*@{*/
+#define I2C_RD_FLT(base)         (I2C_FLT_REG(base))
+#define I2C_WR_FLT(base, value)  (I2C_FLT_REG(base) = (value))
+#define I2C_RMW_FLT(base, mask, value) (I2C_WR_FLT(base, (I2C_RD_FLT(base) & ~(mask)) | (value)))
+#define I2C_SET_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) |  (value)))
+#define I2C_CLR_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) & ~(value)))
+#define I2C_TOG_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_FLT bitfields
+ */
+
+/*!
+ * @name Register I2C_FLT, field FLT[3:0] (RW)
+ *
+ * Controls the width of the glitch, in terms of I2C module clock cycles, that
+ * the filter must absorb. For any glitch whose size is less than or equal to this
+ * width setting, the filter does not allow the glitch to pass.
+ *
+ * Values:
+ * - 0b0000 - No filter/bypass
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_FLT field. */
+#define I2C_RD_FLT_FLT(base) ((I2C_FLT_REG(base) & I2C_FLT_FLT_MASK) >> I2C_FLT_FLT_SHIFT)
+#define I2C_BRD_FLT_FLT(base) (I2C_RD_FLT_FLT(base))
+
+/*! @brief Set the FLT field to a new value. */
+#define I2C_WR_FLT_FLT(base, value) (I2C_RMW_FLT(base, (I2C_FLT_FLT_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_FLT(value)))
+#define I2C_BWR_FLT_FLT(base, value) (I2C_WR_FLT_FLT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STARTF[4] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's start status is detected. The
+ * STARTF bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No start happens on I2C bus
+ * - 0b1 - Start detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STARTF field. */
+#define I2C_RD_FLT_STARTF(base) ((I2C_FLT_REG(base) & I2C_FLT_STARTF_MASK) >> I2C_FLT_STARTF_SHIFT)
+#define I2C_BRD_FLT_STARTF(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT))
+
+/*! @brief Set the STARTF field to a new value. */
+#define I2C_WR_FLT_STARTF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_STARTF(value)))
+#define I2C_BWR_FLT_STARTF(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SSIE[5] (RW)
+ *
+ * This bit enables the interrupt for I2C bus stop or start detection. To clear
+ * the I2C bus stop or start detection interrupt: In the interrupt service
+ * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
+ * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
+ * is asserted again.
+ *
+ * Values:
+ * - 0b0 - Stop or start detection interrupt is disabled
+ * - 0b1 - Stop or start detection interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SSIE field. */
+#define I2C_RD_FLT_SSIE(base) ((I2C_FLT_REG(base) & I2C_FLT_SSIE_MASK) >> I2C_FLT_SSIE_SHIFT)
+#define I2C_BRD_FLT_SSIE(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT))
+
+/*! @brief Set the SSIE field to a new value. */
+#define I2C_WR_FLT_SSIE(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SSIE_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SSIE(value)))
+#define I2C_BWR_FLT_SSIE(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STOPF[6] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
+ * bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No stop happens on I2C bus
+ * - 0b1 - Stop detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STOPF field. */
+#define I2C_RD_FLT_STOPF(base) ((I2C_FLT_REG(base) & I2C_FLT_STOPF_MASK) >> I2C_FLT_STOPF_SHIFT)
+#define I2C_BRD_FLT_STOPF(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT))
+
+/*! @brief Set the STOPF field to a new value. */
+#define I2C_WR_FLT_STOPF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK), I2C_FLT_STOPF(value)))
+#define I2C_BWR_FLT_STOPF(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SHEN[7] (RW)
+ *
+ * Set this bit to hold off entry to stop mode when any data transmission or
+ * reception is occurring. The following scenario explains the holdoff
+ * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
+ * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
+ * byte currently being transferred, including both address and data, completes
+ * its transfer. The I2C slave or master acknowledges that the in-transfer byte
+ * completed its transfer and acknowledges the request to enter stop mode. After
+ * receiving the I2C module's acknowledgment of the request to enter stop mode,
+ * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
+ * is set to 1 and the I2C module is in an idle or disabled state when the MCU
+ * signals to enter stop mode, the module immediately acknowledges the request to
+ * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
+ * reception that was suspended by stop mode entry was incomplete: To resume the
+ * overall transmission or reception after the MCU exits stop mode, software must
+ * reinitialize the transfer by resending the address of the slave. If the I2C
+ * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
+ * system software will receive the interrupt triggered by the I2C Status Register's
+ * TCF bit after the MCU wakes from the stop mode.
+ *
+ * Values:
+ * - 0b0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
+ * - 0b1 - Stop holdoff is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SHEN field. */
+#define I2C_RD_FLT_SHEN(base) ((I2C_FLT_REG(base) & I2C_FLT_SHEN_MASK) >> I2C_FLT_SHEN_SHIFT)
+#define I2C_BRD_FLT_SHEN(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT))
+
+/*! @brief Set the SHEN field to a new value. */
+#define I2C_WR_FLT_SHEN(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SHEN_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SHEN(value)))
+#define I2C_BWR_FLT_SHEN(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_RA - I2C Range Address register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_RA - I2C Range Address register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_RA register
+ */
+/*@{*/
+#define I2C_RD_RA(base)          (I2C_RA_REG(base))
+#define I2C_WR_RA(base, value)   (I2C_RA_REG(base) = (value))
+#define I2C_RMW_RA(base, mask, value) (I2C_WR_RA(base, (I2C_RD_RA(base) & ~(mask)) | (value)))
+#define I2C_SET_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) |  (value)))
+#define I2C_CLR_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) & ~(value)))
+#define I2C_TOG_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_RA bitfields
+ */
+
+/*!
+ * @name Register I2C_RA, field RAD[7:1] (RW)
+ *
+ * This field contains the slave address to be used by the I2C module. The field
+ * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
+ * value write enables this register. This register value can be considered as a
+ * maximum boundary in the range matching mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_RA_RAD field. */
+#define I2C_RD_RA_RAD(base)  ((I2C_RA_REG(base) & I2C_RA_RAD_MASK) >> I2C_RA_RAD_SHIFT)
+#define I2C_BRD_RA_RAD(base) (I2C_RD_RA_RAD(base))
+
+/*! @brief Set the RAD field to a new value. */
+#define I2C_WR_RA_RAD(base, value) (I2C_RMW_RA(base, I2C_RA_RAD_MASK, I2C_RA_RAD(value)))
+#define I2C_BWR_RA_RAD(base, value) (I2C_WR_RA_RAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SMB - I2C SMBus Control and Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SMB - I2C SMBus Control and Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When the SCL and SDA signals are held high for a length of time greater than
+ * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
+ * while the system is detecting how long these signals are being held high, a
+ * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
+ * bus transmission process with the idle bus state. When the TCKSEL bit is set,
+ * there is no need to monitor the SHTF1 bit because the bus speed is too high to
+ * match the protocol of SMBus.
+ */
+/*!
+ * @name Constants and macros for entire I2C_SMB register
+ */
+/*@{*/
+#define I2C_RD_SMB(base)         (I2C_SMB_REG(base))
+#define I2C_WR_SMB(base, value)  (I2C_SMB_REG(base) = (value))
+#define I2C_RMW_SMB(base, mask, value) (I2C_WR_SMB(base, (I2C_RD_SMB(base) & ~(mask)) | (value)))
+#define I2C_SET_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) |  (value)))
+#define I2C_CLR_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) & ~(value)))
+#define I2C_TOG_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_SMB bitfields
+ */
+
+/*!
+ * @name Register I2C_SMB, field SHTF2IE[0] (RW)
+ *
+ * Enables SCL high and SDA low timeout interrupt.
+ *
+ * Values:
+ * - 0b0 - SHTF2 interrupt is disabled
+ * - 0b1 - SHTF2 interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2IE field. */
+#define I2C_RD_SMB_SHTF2IE(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2IE_MASK) >> I2C_SMB_SHTF2IE_SHIFT)
+#define I2C_BRD_SMB_SHTF2IE(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT))
+
+/*! @brief Set the SHTF2IE field to a new value. */
+#define I2C_WR_SMB_SHTF2IE(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2IE_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2IE(value)))
+#define I2C_BWR_SMB_SHTF2IE(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF2[1] (W1C)
+ *
+ * This bit sets when SCL is held high and SDA is held low more than clock *
+ * LoValue / 512. Software clears this bit by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No SCL high and SDA low timeout occurs
+ * - 0b1 - SCL high and SDA low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2 field. */
+#define I2C_RD_SMB_SHTF2(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2_MASK) >> I2C_SMB_SHTF2_SHIFT)
+#define I2C_BRD_SMB_SHTF2(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT))
+
+/*! @brief Set the SHTF2 field to a new value. */
+#define I2C_WR_SMB_SHTF2(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2(value)))
+#define I2C_BWR_SMB_SHTF2(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF1[2] (RO)
+ *
+ * This read-only bit sets when SCL and SDA are held high more than clock *
+ * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
+ *
+ * Values:
+ * - 0b0 - No SCL high and SDA high timeout occurs
+ * - 0b1 - SCL high and SDA high timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF1 field. */
+#define I2C_RD_SMB_SHTF1(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF1_MASK) >> I2C_SMB_SHTF1_SHIFT)
+#define I2C_BRD_SMB_SHTF1(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SLTF[3] (W1C)
+ *
+ * This bit is set when the SLT register (consisting of the SLTH and SLTL
+ * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
+ * Software clears this bit by writing a logic 1 to it. The low timeout function
+ * is disabled when the SLT register's value is 0.
+ *
+ * Values:
+ * - 0b0 - No low timeout occurs
+ * - 0b1 - Low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SLTF field. */
+#define I2C_RD_SMB_SLTF(base) ((I2C_SMB_REG(base) & I2C_SMB_SLTF_MASK) >> I2C_SMB_SLTF_SHIFT)
+#define I2C_BRD_SMB_SLTF(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT))
+
+/*! @brief Set the SLTF field to a new value. */
+#define I2C_WR_SMB_SLTF(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SLTF_MASK | I2C_SMB_SHTF2_MASK), I2C_SMB_SLTF(value)))
+#define I2C_BWR_SMB_SLTF(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field TCKSEL[4] (RW)
+ *
+ * Selects the clock source of the timeout counter.
+ *
+ * Values:
+ * - 0b0 - Timeout counter counts at the frequency of the I2C module clock / 64
+ * - 0b1 - Timeout counter counts at the frequency of the I2C module clock
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_TCKSEL field. */
+#define I2C_RD_SMB_TCKSEL(base) ((I2C_SMB_REG(base) & I2C_SMB_TCKSEL_MASK) >> I2C_SMB_TCKSEL_SHIFT)
+#define I2C_BRD_SMB_TCKSEL(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT))
+
+/*! @brief Set the TCKSEL field to a new value. */
+#define I2C_WR_SMB_TCKSEL(base, value) (I2C_RMW_SMB(base, (I2C_SMB_TCKSEL_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_TCKSEL(value)))
+#define I2C_BWR_SMB_TCKSEL(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SIICAEN[5] (RW)
+ *
+ * Enables or disables SMBus device default address.
+ *
+ * Values:
+ * - 0b0 - I2C address register 2 matching is disabled
+ * - 0b1 - I2C address register 2 matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SIICAEN field. */
+#define I2C_RD_SMB_SIICAEN(base) ((I2C_SMB_REG(base) & I2C_SMB_SIICAEN_MASK) >> I2C_SMB_SIICAEN_SHIFT)
+#define I2C_BRD_SMB_SIICAEN(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT))
+
+/*! @brief Set the SIICAEN field to a new value. */
+#define I2C_WR_SMB_SIICAEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SIICAEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SIICAEN(value)))
+#define I2C_BWR_SMB_SIICAEN(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field ALERTEN[6] (RW)
+ *
+ * Enables or disables SMBus alert response address matching. After the host
+ * responds to a device that used the alert response address, you must use software
+ * to put the device's address on the bus. The alert protocol is described in the
+ * SMBus specification.
+ *
+ * Values:
+ * - 0b0 - SMBus alert response address matching is disabled
+ * - 0b1 - SMBus alert response address matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_ALERTEN field. */
+#define I2C_RD_SMB_ALERTEN(base) ((I2C_SMB_REG(base) & I2C_SMB_ALERTEN_MASK) >> I2C_SMB_ALERTEN_SHIFT)
+#define I2C_BRD_SMB_ALERTEN(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT))
+
+/*! @brief Set the ALERTEN field to a new value. */
+#define I2C_WR_SMB_ALERTEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_ALERTEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_ALERTEN(value)))
+#define I2C_BWR_SMB_ALERTEN(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field FACK[7] (RW)
+ *
+ * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
+ * according to the result of receiving data byte.
+ *
+ * Values:
+ * - 0b0 - An ACK or NACK is sent on the following receiving data byte
+ * - 0b1 - Writing 0 to TXAK after receiving a data byte generates an ACK.
+ *     Writing 1 to TXAK after receiving a data byte generates a NACK.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_FACK field. */
+#define I2C_RD_SMB_FACK(base) ((I2C_SMB_REG(base) & I2C_SMB_FACK_MASK) >> I2C_SMB_FACK_SHIFT)
+#define I2C_BRD_SMB_FACK(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT))
+
+/*! @brief Set the FACK field to a new value. */
+#define I2C_WR_SMB_FACK(base, value) (I2C_RMW_SMB(base, (I2C_SMB_FACK_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_FACK(value)))
+#define I2C_BWR_SMB_FACK(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_A2 - I2C Address Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A2 - I2C Address Register 2 (RW)
+ *
+ * Reset value: 0xC2U
+ */
+/*!
+ * @name Constants and macros for entire I2C_A2 register
+ */
+/*@{*/
+#define I2C_RD_A2(base)          (I2C_A2_REG(base))
+#define I2C_WR_A2(base, value)   (I2C_A2_REG(base) = (value))
+#define I2C_RMW_A2(base, mask, value) (I2C_WR_A2(base, (I2C_RD_A2(base) & ~(mask)) | (value)))
+#define I2C_SET_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) |  (value)))
+#define I2C_CLR_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) & ~(value)))
+#define I2C_TOG_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A2 bitfields
+ */
+
+/*!
+ * @name Register I2C_A2, field SAD[7:1] (RW)
+ *
+ * Contains the slave address used by the SMBus. This field is used on the
+ * device default address or other related addresses.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A2_SAD field. */
+#define I2C_RD_A2_SAD(base)  ((I2C_A2_REG(base) & I2C_A2_SAD_MASK) >> I2C_A2_SAD_SHIFT)
+#define I2C_BRD_A2_SAD(base) (I2C_RD_A2_SAD(base))
+
+/*! @brief Set the SAD field to a new value. */
+#define I2C_WR_A2_SAD(base, value) (I2C_RMW_A2(base, I2C_A2_SAD_MASK, I2C_A2_SAD(value)))
+#define I2C_BWR_A2_SAD(base, value) (I2C_WR_A2_SAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTH - I2C SCL Low Timeout Register High
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTH - I2C SCL Low Timeout Register High (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTH register
+ */
+/*@{*/
+#define I2C_RD_SLTH(base)        (I2C_SLTH_REG(base))
+#define I2C_WR_SLTH(base, value) (I2C_SLTH_REG(base) = (value))
+#define I2C_RMW_SLTH(base, mask, value) (I2C_WR_SLTH(base, (I2C_RD_SLTH(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) |  (value)))
+#define I2C_CLR_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) & ~(value)))
+#define I2C_TOG_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTL - I2C SCL Low Timeout Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTL register
+ */
+/*@{*/
+#define I2C_RD_SLTL(base)        (I2C_SLTL_REG(base))
+#define I2C_WR_SLTL(base, value) (I2C_SLTL_REG(base) = (value))
+#define I2C_RMW_SLTL(base, mask, value) (I2C_WR_SLTL(base, (I2C_RD_SLTL(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) |  (value)))
+#define I2C_CLR_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) & ~(value)))
+#define I2C_TOG_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 I2S
+ *
+ * Inter-IC Sound / Synchronous Audio Interface
+ *
+ * Registers defined in this header file:
+ * - I2S_TCSR - SAI Transmit Control Register
+ * - I2S_TCR1 - SAI Transmit Configuration 1 Register
+ * - I2S_TCR2 - SAI Transmit Configuration 2 Register
+ * - I2S_TCR3 - SAI Transmit Configuration 3 Register
+ * - I2S_TCR4 - SAI Transmit Configuration 4 Register
+ * - I2S_TCR5 - SAI Transmit Configuration 5 Register
+ * - I2S_TDR - SAI Transmit Data Register
+ * - I2S_TFR - SAI Transmit FIFO Register
+ * - I2S_TMR - SAI Transmit Mask Register
+ * - I2S_RCSR - SAI Receive Control Register
+ * - I2S_RCR1 - SAI Receive Configuration 1 Register
+ * - I2S_RCR2 - SAI Receive Configuration 2 Register
+ * - I2S_RCR3 - SAI Receive Configuration 3 Register
+ * - I2S_RCR4 - SAI Receive Configuration 4 Register
+ * - I2S_RCR5 - SAI Receive Configuration 5 Register
+ * - I2S_RDR - SAI Receive Data Register
+ * - I2S_RFR - SAI Receive FIFO Register
+ * - I2S_RMR - SAI Receive Mask Register
+ * - I2S_MCR - SAI MCLK Control Register
+ * - I2S_MDR - SAI MCLK Divide Register
+ */
+
+#define I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */
+#define I2S0_IDX (0U) /*!< Instance number for I2S0. */
+
+/*******************************************************************************
+ * I2S_TCSR - SAI Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCSR - SAI Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCSR register
+ */
+/*@{*/
+#define I2S_RD_TCSR(base)        (I2S_TCSR_REG(base))
+#define I2S_WR_TCSR(base, value) (I2S_TCSR_REG(base) = (value))
+#define I2S_RMW_TCSR(base, mask, value) (I2S_WR_TCSR(base, (I2S_RD_TCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) |  (value)))
+#define I2S_CLR_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) & ~(value)))
+#define I2S_TOG_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_TCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRDE field. */
+#define I2S_RD_TCSR_FRDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRDE_MASK) >> I2S_TCSR_FRDE_SHIFT)
+#define I2S_BRD_TCSR_FRDE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRDE_SHIFT))
+
+/*! @brief Set the FRDE field to a new value. */
+#define I2S_WR_TCSR_FRDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FRDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FRDE(value)))
+#define I2S_BWR_TCSR_FRDE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWDE field. */
+#define I2S_RD_TCSR_FWDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWDE_MASK) >> I2S_TCSR_FWDE_SHIFT)
+#define I2S_BRD_TCSR_FWDE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_TCSR_FWDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWDE(value)))
+#define I2S_BWR_TCSR_FWDE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRIE field. */
+#define I2S_RD_TCSR_FRIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRIE_MASK) >> I2S_TCSR_FRIE_SHIFT)
+#define I2S_BRD_TCSR_FRIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRIE_SHIFT))
+
+/*! @brief Set the FRIE field to a new value. */
+#define I2S_WR_TCSR_FRIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FRIE(value)))
+#define I2S_BWR_TCSR_FRIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWIE field. */
+#define I2S_RD_TCSR_FWIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWIE_MASK) >> I2S_TCSR_FWIE_SHIFT)
+#define I2S_BRD_TCSR_FWIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_TCSR_FWIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWIE(value)))
+#define I2S_BWR_TCSR_FWIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEIE field. */
+#define I2S_RD_TCSR_FEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEIE_MASK) >> I2S_TCSR_FEIE_SHIFT)
+#define I2S_BRD_TCSR_FEIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_TCSR_FEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEIE(value)))
+#define I2S_BWR_TCSR_FEIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEIE field. */
+#define I2S_RD_TCSR_SEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEIE_MASK) >> I2S_TCSR_SEIE_SHIFT)
+#define I2S_BRD_TCSR_SEIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_TCSR_SEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEIE(value)))
+#define I2S_BWR_TCSR_SEIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSIE field. */
+#define I2S_RD_TCSR_WSIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSIE_MASK) >> I2S_TCSR_WSIE_SHIFT)
+#define I2S_BRD_TCSR_WSIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_TCSR_WSIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_WSIE(value)))
+#define I2S_BWR_TCSR_WSIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled transmit channel FIFO is
+ * less than or equal to the transmit FIFO watermark.
+ *
+ * Values:
+ * - 0b0 - Transmit FIFO watermark has not been reached.
+ * - 0b1 - Transmit FIFO watermark has been reached.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRF field. */
+#define I2S_RD_TCSR_FRF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRF_MASK) >> I2S_TCSR_FRF_SHIFT)
+#define I2S_BRD_TCSR_FRF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled transmit FIFO is empty.
+ *
+ * Values:
+ * - 0b0 - No enabled transmit FIFO is empty.
+ * - 0b1 - Enabled transmit FIFO is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWF field. */
+#define I2S_RD_TCSR_FWF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWF_MASK) >> I2S_TCSR_FWF_SHIFT)
+#define I2S_BRD_TCSR_FWF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
+ * field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Transmit underrun not detected.
+ * - 0b1 - Transmit underrun detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEF field. */
+#define I2S_RD_TCSR_FEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEF_MASK) >> I2S_TCSR_FEF_SHIFT)
+#define I2S_BRD_TCSR_FEF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_TCSR_FEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEF(value)))
+#define I2S_BWR_TCSR_FEF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Sync error not detected.
+ * - 0b1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEF field. */
+#define I2S_RD_TCSR_SEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEF_MASK) >> I2S_TCSR_SEF_SHIFT)
+#define I2S_BRD_TCSR_SEF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_TCSR_SEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEF(value)))
+#define I2S_BWR_TCSR_SEF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Start of word not detected.
+ * - 0b1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSF field. */
+#define I2S_RD_TCSR_WSF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSF_MASK) >> I2S_TCSR_WSF_SHIFT)
+#define I2S_BRD_TCSR_WSF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_TCSR_WSF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK), I2S_TCSR_WSF(value)))
+#define I2S_BWR_TCSR_WSF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SR[24] (RW)
+ *
+ * When set, resets the internal transmitter logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SR field. */
+#define I2S_RD_TCSR_SR(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SR_MASK) >> I2S_TCSR_SR_SHIFT)
+#define I2S_BRD_TCSR_SR(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_TCSR_SR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SR(value)))
+#define I2S_BWR_TCSR_SR(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the transmitter is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_TCSR_FR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FR(value)))
+#define I2S_BWR_TCSR_FR(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field BCE[28] (RW)
+ *
+ * Enables the transmit bit clock, separately from the TE. This field is
+ * automatically set whenever TE is set. When software clears this field, the transmit
+ * bit clock remains enabled, and this bit remains set, until the end of the
+ * current frame.
+ *
+ * Values:
+ * - 0b0 - Transmit bit clock is disabled.
+ * - 0b1 - Transmit bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_BCE field. */
+#define I2S_RD_TCSR_BCE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_BCE_MASK) >> I2S_TCSR_BCE_SHIFT)
+#define I2S_BRD_TCSR_BCE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_TCSR_BCE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_BCE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_BCE(value)))
+#define I2S_BWR_TCSR_BCE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables transmitter operation in Debug mode. The transmit bit clock
+ * is not affected by debug mode.
+ *
+ * Values:
+ * - 0b0 - Transmitter is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 0b1 - Transmitter is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_DBGE field. */
+#define I2S_RD_TCSR_DBGE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_DBGE_MASK) >> I2S_TCSR_DBGE_SHIFT)
+#define I2S_BRD_TCSR_DBGE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_TCSR_DBGE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_DBGE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_DBGE(value)))
+#define I2S_BWR_TCSR_DBGE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field STOPE[30] (RW)
+ *
+ * Configures transmitter operation in Stop mode. This field is ignored and the
+ * transmitter is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0b0 - Transmitter disabled in Stop mode.
+ * - 0b1 - Transmitter enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_STOPE field. */
+#define I2S_RD_TCSR_STOPE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_STOPE_MASK) >> I2S_TCSR_STOPE_SHIFT)
+#define I2S_BRD_TCSR_STOPE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_TCSR_STOPE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_STOPE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_STOPE(value)))
+#define I2S_BWR_TCSR_STOPE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field TE[31] (RW)
+ *
+ * Enables/disables the transmitter. When software clears this field, the
+ * transmitter remains enabled, and this bit remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0b0 - Transmitter is disabled.
+ * - 0b1 - Transmitter is enabled, or transmitter has been disabled and has not
+ *     yet reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_TE field. */
+#define I2S_RD_TCSR_TE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_TE_MASK) >> I2S_TCSR_TE_SHIFT)
+#define I2S_BRD_TCSR_TE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT))
+
+/*! @brief Set the TE field to a new value. */
+#define I2S_WR_TCSR_TE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_TE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_TE(value)))
+#define I2S_BWR_TCSR_TE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR1 - SAI Transmit Configuration 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR1 register
+ */
+/*@{*/
+#define I2S_RD_TCR1(base)        (I2S_TCR1_REG(base))
+#define I2S_WR_TCR1(base, value) (I2S_TCR1_REG(base) = (value))
+#define I2S_RMW_TCR1(base, mask, value) (I2S_WR_TCR1(base, (I2S_RD_TCR1(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) |  (value)))
+#define I2S_CLR_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) & ~(value)))
+#define I2S_TOG_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR1, field TFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled transmit channels.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR1_TFW field. */
+#define I2S_RD_TCR1_TFW(base) ((I2S_TCR1_REG(base) & I2S_TCR1_TFW_MASK) >> I2S_TCR1_TFW_SHIFT)
+#define I2S_BRD_TCR1_TFW(base) (I2S_RD_TCR1_TFW(base))
+
+/*! @brief Set the TFW field to a new value. */
+#define I2S_WR_TCR1_TFW(base, value) (I2S_RMW_TCR1(base, I2S_TCR1_TFW_MASK, I2S_TCR1_TFW(value)))
+#define I2S_BWR_TCR1_TFW(base, value) (I2S_WR_TCR1_TFW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR2 - SAI Transmit Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR2 register
+ */
+/*@{*/
+#define I2S_RD_TCR2(base)        (I2S_TCR2_REG(base))
+#define I2S_WR_TCR2(base, value) (I2S_TCR2_REG(base) = (value))
+#define I2S_RMW_TCR2(base, mask, value) (I2S_WR_TCR2(base, (I2S_RD_TCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) |  (value)))
+#define I2S_CLR_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) & ~(value)))
+#define I2S_TOG_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_DIV field. */
+#define I2S_RD_TCR2_DIV(base) ((I2S_TCR2_REG(base) & I2S_TCR2_DIV_MASK) >> I2S_TCR2_DIV_SHIFT)
+#define I2S_BRD_TCR2_DIV(base) (I2S_RD_TCR2_DIV(base))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_TCR2_DIV(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_DIV_MASK, I2S_TCR2_DIV(value)))
+#define I2S_BWR_TCR2_DIV(base, value) (I2S_WR_TCR2_DIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is generated externally in Slave mode.
+ * - 0b1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCD field. */
+#define I2S_RD_TCR2_BCD(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCD_MASK) >> I2S_TCR2_BCD_SHIFT)
+#define I2S_BRD_TCR2_BCD(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_TCR2_BCD(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCD_MASK, I2S_TCR2_BCD(value)))
+#define I2S_BWR_TCR2_BCD(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 0b1 - Bit clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCP field. */
+#define I2S_RD_TCR2_BCP(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCP_MASK) >> I2S_TCR2_BCP_SHIFT)
+#define I2S_BRD_TCR2_BCP(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_TCR2_BCP(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCP_MASK, I2S_TCR2_BCP(value)))
+#define I2S_BWR_TCR2_BCP(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 0b00 - Bus Clock selected.
+ * - 0b01 - Master Clock (MCLK) 1 option selected.
+ * - 0b10 - Master Clock (MCLK) 2 option selected.
+ * - 0b11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_MSEL field. */
+#define I2S_RD_TCR2_MSEL(base) ((I2S_TCR2_REG(base) & I2S_TCR2_MSEL_MASK) >> I2S_TCR2_MSEL_SHIFT)
+#define I2S_BRD_TCR2_MSEL(base) (I2S_RD_TCR2_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_TCR2_MSEL(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_MSEL_MASK, I2S_TCR2_MSEL(value)))
+#define I2S_BWR_TCR2_MSEL(base, value) (I2S_WR_TCR2_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the
+ * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
+ * input as if the clock was externally generated). This has the effect of
+ * decreasing the data input setup time, but increasing the data output valid time. The
+ * slave mode timing from the datasheet should be used for the transmitter when
+ * this bit is set. In synchronous mode, this bit allows the transmitter to use
+ * the slave mode timing from the datasheet, while the receiver uses the master
+ * mode timing. This field has no effect when configured for an externally generated
+ * bit clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCI field. */
+#define I2S_RD_TCR2_BCI(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCI_MASK) >> I2S_TCR2_BCI_SHIFT)
+#define I2S_BRD_TCR2_BCI(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_TCR2_BCI(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCI_MASK, I2S_TCR2_BCI(value)))
+#define I2S_BWR_TCR2_BCI(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the transmitter. When the transmitter
+ * is configured in asynchronous mode and this bit is set, the transmitter is
+ * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the transmitter continues to use the
+ * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
+ * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
+ * the same value. When both are set, the transmitter and receiver are both
+ * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
+ * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
+ * peripheral.
+ *
+ * Values:
+ * - 0b0 - Use the normal bit clock source.
+ * - 0b1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCS field. */
+#define I2S_RD_TCR2_BCS(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCS_MASK) >> I2S_TCR2_BCS_SHIFT)
+#define I2S_BRD_TCR2_BCS(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_TCR2_BCS(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCS_MASK, I2S_TCR2_BCS(value)))
+#define I2S_BWR_TCR2_BCS(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the receiver or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 0b00 - Asynchronous mode.
+ * - 0b01 - Synchronous with receiver.
+ * - 0b10 - Synchronous with another SAI transmitter.
+ * - 0b11 - Synchronous with another SAI receiver.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_SYNC field. */
+#define I2S_RD_TCR2_SYNC(base) ((I2S_TCR2_REG(base) & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT)
+#define I2S_BRD_TCR2_SYNC(base) (I2S_RD_TCR2_SYNC(base))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_TCR2_SYNC(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_SYNC_MASK, I2S_TCR2_SYNC(value)))
+#define I2S_BWR_TCR2_SYNC(base, value) (I2S_WR_TCR2_SYNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR3 - SAI Transmit Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR3 register
+ */
+/*@{*/
+#define I2S_RD_TCR3(base)        (I2S_TCR3_REG(base))
+#define I2S_WR_TCR3(base, value) (I2S_TCR3_REG(base) = (value))
+#define I2S_RMW_TCR3(base, mask, value) (I2S_WR_TCR3(base, (I2S_RD_TCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) |  (value)))
+#define I2S_CLR_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) & ~(value)))
+#define I2S_TOG_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word sets the start of word flag. The value written must be
+ * one less than the word number. For example, writing 0 configures the first
+ * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
+ * start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_WDFL field. */
+#define I2S_RD_TCR3_WDFL(base) ((I2S_TCR3_REG(base) & I2S_TCR3_WDFL_MASK) >> I2S_TCR3_WDFL_SHIFT)
+#define I2S_BRD_TCR3_WDFL(base) (I2S_RD_TCR3_WDFL(base))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_TCR3_WDFL(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_WDFL_MASK, I2S_TCR3_WDFL(value)))
+#define I2S_BWR_TCR3_WDFL(base, value) (I2S_WR_TCR3_WDFL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR3, field TCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for transmit operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0b00 - Transmit data channel N is disabled.
+ * - 0b01 - Transmit data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_TCE field. */
+#define I2S_RD_TCR3_TCE(base) ((I2S_TCR3_REG(base) & I2S_TCR3_TCE_MASK) >> I2S_TCR3_TCE_SHIFT)
+#define I2S_BRD_TCR3_TCE(base) (I2S_RD_TCR3_TCE(base))
+
+/*! @brief Set the TCE field to a new value. */
+#define I2S_WR_TCR3_TCE(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_TCE_MASK, I2S_TCR3_TCE(value)))
+#define I2S_BWR_TCR3_TCE(base, value) (I2S_WR_TCR3_TCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR4 - SAI Transmit Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR4 register
+ */
+/*@{*/
+#define I2S_RD_TCR4(base)        (I2S_TCR4_REG(base))
+#define I2S_WR_TCR4(base, value) (I2S_TCR4_REG(base) = (value))
+#define I2S_RMW_TCR4(base, mask, value) (I2S_WR_TCR4(base, (I2S_RD_TCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) |  (value)))
+#define I2S_CLR_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) & ~(value)))
+#define I2S_TOG_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is generated externally in Slave mode.
+ * - 0b1 - Frame sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSD field. */
+#define I2S_RD_TCR4_FSD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSD_MASK) >> I2S_TCR4_FSD_SHIFT)
+#define I2S_BRD_TCR4_FSD(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_TCR4_FSD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSD_MASK, I2S_TCR4_FSD(value)))
+#define I2S_BWR_TCR4_FSD(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is active high.
+ * - 0b1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSP field. */
+#define I2S_RD_TCR4_FSP(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSP_MASK) >> I2S_TCR4_FSP_SHIFT)
+#define I2S_BRD_TCR4_FSP(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_TCR4_FSP(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSP_MASK, I2S_TCR4_FSP(value)))
+#define I2S_BWR_TCR4_FSP(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Frame sync asserts with the first bit of the frame.
+ * - 0b1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSE field. */
+#define I2S_RD_TCR4_FSE(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSE_MASK) >> I2S_TCR4_FSE_SHIFT)
+#define I2S_BRD_TCR4_FSE(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_TCR4_FSE(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSE_MASK, I2S_TCR4_FSE(value)))
+#define I2S_BWR_TCR4_FSE(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is transmitted first.
+ *
+ * Values:
+ * - 0b0 - LSB is transmitted first.
+ * - 0b1 - MSB is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_MF field. */
+#define I2S_RD_TCR4_MF(base) ((I2S_TCR4_REG(base) & I2S_TCR4_MF_MASK) >> I2S_TCR4_MF_SHIFT)
+#define I2S_BRD_TCR4_MF(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_TCR4_MF(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_MF_MASK, I2S_TCR4_MF(value)))
+#define I2S_BWR_TCR4_MF(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_SYWD field. */
+#define I2S_RD_TCR4_SYWD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_SYWD_MASK) >> I2S_TCR4_SYWD_SHIFT)
+#define I2S_BRD_TCR4_SYWD(base) (I2S_RD_TCR4_SYWD(base))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_TCR4_SYWD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_SYWD_MASK, I2S_TCR4_SYWD(value)))
+#define I2S_BWR_TCR4_SYWD(base, value) (I2S_WR_TCR4_SYWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FRSZ field. */
+#define I2S_RD_TCR4_FRSZ(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FRSZ_MASK) >> I2S_TCR4_FRSZ_SHIFT)
+#define I2S_BRD_TCR4_FRSZ(base) (I2S_RD_TCR4_FRSZ(base))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_TCR4_FRSZ(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FRSZ_MASK, I2S_TCR4_FRSZ(value)))
+#define I2S_BWR_TCR4_FRSZ(base, value) (I2S_WR_TCR4_FRSZ(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR5 - SAI Transmit Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR5 register
+ */
+/*@{*/
+#define I2S_RD_TCR5(base)        (I2S_TCR5_REG(base))
+#define I2S_WR_TCR5(base, value) (I2S_TCR5_REG(base) = (value))
+#define I2S_RMW_TCR5(base, mask, value) (I2S_WR_TCR5(base, (I2S_RD_TCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) |  (value)))
+#define I2S_CLR_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) & ~(value)))
+#define I2S_TOG_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit transmitted for each word in the
+ * frame. If configured for MSB First, the index of the next bit transmitted is
+ * one less than the current bit transmitted. If configured for LSB First, the
+ * index of the next bit transmitted is one more than the current bit transmitted.
+ * The value written must be greater than or equal to the word width when
+ * configured for MSB First. The value written must be less than or equal to 31-word width
+ * when configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_FBT field. */
+#define I2S_RD_TCR5_FBT(base) ((I2S_TCR5_REG(base) & I2S_TCR5_FBT_MASK) >> I2S_TCR5_FBT_SHIFT)
+#define I2S_BRD_TCR5_FBT(base) (I2S_RD_TCR5_FBT(base))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_TCR5_FBT(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_FBT_MASK, I2S_TCR5_FBT(value)))
+#define I2S_BWR_TCR5_FBT(base, value) (I2S_WR_TCR5_FBT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_W0W field. */
+#define I2S_RD_TCR5_W0W(base) ((I2S_TCR5_REG(base) & I2S_TCR5_W0W_MASK) >> I2S_TCR5_W0W_SHIFT)
+#define I2S_BRD_TCR5_W0W(base) (I2S_RD_TCR5_W0W(base))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_TCR5_W0W(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_W0W_MASK, I2S_TCR5_W0W(value)))
+#define I2S_BWR_TCR5_W0W(base, value) (I2S_WR_TCR5_W0W(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_WNW field. */
+#define I2S_RD_TCR5_WNW(base) ((I2S_TCR5_REG(base) & I2S_TCR5_WNW_MASK) >> I2S_TCR5_WNW_SHIFT)
+#define I2S_BRD_TCR5_WNW(base) (I2S_RD_TCR5_WNW(base))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_TCR5_WNW(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_WNW_MASK, I2S_TCR5_WNW(value)))
+#define I2S_BWR_TCR5_WNW(base, value) (I2S_WR_TCR5_WNW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TDR - SAI Transmit Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TDR - SAI Transmit Data Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TDR register
+ */
+/*@{*/
+#define I2S_RD_TDR(base, index)  (I2S_TDR_REG(base, index))
+#define I2S_WR_TDR(base, index, value) (I2S_TDR_REG(base, index) = (value))
+#define I2S_RMW_TDR(base, index, mask, value) (I2S_WR_TDR(base, index, (I2S_RD_TDR(base, index) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TFR - SAI Transmit FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TFR - SAI Transmit FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TFR register
+ */
+/*@{*/
+#define I2S_RD_TFR(base, index)  (I2S_TFR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TFR bitfields
+ */
+
+/*!
+ * @name Register I2S_TFR, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for transmit data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TFR_RFP field. */
+#define I2S_RD_TFR_RFP(base, index) ((I2S_TFR_REG(base, index) & I2S_TFR_RFP_MASK) >> I2S_TFR_RFP_SHIFT)
+#define I2S_BRD_TFR_RFP(base, index) (I2S_RD_TFR_RFP(base, index))
+/*@}*/
+
+/*!
+ * @name Register I2S_TFR, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for transmit data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TFR_WFP field. */
+#define I2S_RD_TFR_WFP(base, index) ((I2S_TFR_REG(base, index) & I2S_TFR_WFP_MASK) >> I2S_TFR_WFP_SHIFT)
+#define I2S_BRD_TFR_WFP(base, index) (I2S_RD_TFR_WFP(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TMR - SAI Transmit Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TMR - SAI Transmit Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When TCSR[TE] is first set At
+ * the end of each frame. This allows the masked words in each frame to change
+ * from frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TMR register
+ */
+/*@{*/
+#define I2S_RD_TMR(base)         (I2S_TMR_REG(base))
+#define I2S_WR_TMR(base, value)  (I2S_TMR_REG(base) = (value))
+#define I2S_RMW_TMR(base, mask, value) (I2S_WR_TMR(base, (I2S_RD_TMR(base) & ~(mask)) | (value)))
+#define I2S_SET_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) |  (value)))
+#define I2S_CLR_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) & ~(value)))
+#define I2S_TOG_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCSR - SAI Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCSR - SAI Receive Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCSR register
+ */
+/*@{*/
+#define I2S_RD_RCSR(base)        (I2S_RCSR_REG(base))
+#define I2S_WR_RCSR(base, value) (I2S_RCSR_REG(base) = (value))
+#define I2S_RMW_RCSR(base, mask, value) (I2S_WR_RCSR(base, (I2S_RD_RCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) |  (value)))
+#define I2S_CLR_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) & ~(value)))
+#define I2S_TOG_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_RCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRDE field. */
+#define I2S_RD_RCSR_FRDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRDE_MASK) >> I2S_RCSR_FRDE_SHIFT)
+#define I2S_BRD_RCSR_FRDE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRDE_SHIFT))
+
+/*! @brief Set the FRDE field to a new value. */
+#define I2S_WR_RCSR_FRDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FRDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FRDE(value)))
+#define I2S_BWR_RCSR_FRDE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWDE field. */
+#define I2S_RD_RCSR_FWDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWDE_MASK) >> I2S_RCSR_FWDE_SHIFT)
+#define I2S_BRD_RCSR_FWDE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_RCSR_FWDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWDE(value)))
+#define I2S_BWR_RCSR_FWDE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRIE field. */
+#define I2S_RD_RCSR_FRIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRIE_MASK) >> I2S_RCSR_FRIE_SHIFT)
+#define I2S_BRD_RCSR_FRIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRIE_SHIFT))
+
+/*! @brief Set the FRIE field to a new value. */
+#define I2S_WR_RCSR_FRIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FRIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FRIE(value)))
+#define I2S_BWR_RCSR_FRIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWIE field. */
+#define I2S_RD_RCSR_FWIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWIE_MASK) >> I2S_RCSR_FWIE_SHIFT)
+#define I2S_BRD_RCSR_FWIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_RCSR_FWIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWIE(value)))
+#define I2S_BWR_RCSR_FWIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEIE field. */
+#define I2S_RD_RCSR_FEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEIE_MASK) >> I2S_RCSR_FEIE_SHIFT)
+#define I2S_BRD_RCSR_FEIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_RCSR_FEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEIE(value)))
+#define I2S_BWR_RCSR_FEIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEIE field. */
+#define I2S_RD_RCSR_SEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEIE_MASK) >> I2S_RCSR_SEIE_SHIFT)
+#define I2S_BRD_RCSR_SEIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_RCSR_SEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEIE(value)))
+#define I2S_BWR_RCSR_SEIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSIE field. */
+#define I2S_RD_RCSR_WSIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSIE_MASK) >> I2S_RCSR_WSIE_SHIFT)
+#define I2S_BRD_RCSR_WSIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_RCSR_WSIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_WSIE(value)))
+#define I2S_BWR_RCSR_WSIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled receive channel FIFO is
+ * greater than the receive FIFO watermark.
+ *
+ * Values:
+ * - 0b0 - Receive FIFO watermark not reached.
+ * - 0b1 - Receive FIFO watermark has been reached.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRF field. */
+#define I2S_RD_RCSR_FRF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRF_MASK) >> I2S_RCSR_FRF_SHIFT)
+#define I2S_BRD_RCSR_FRF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled receive FIFO is full.
+ *
+ * Values:
+ * - 0b0 - No enabled receive FIFO is full.
+ * - 0b1 - Enabled receive FIFO is full.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWF field. */
+#define I2S_RD_RCSR_FWF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWF_MASK) >> I2S_RCSR_FWF_SHIFT)
+#define I2S_BRD_RCSR_FWF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
+ * this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Receive overflow not detected.
+ * - 0b1 - Receive overflow detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEF field. */
+#define I2S_RD_RCSR_FEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEF_MASK) >> I2S_RCSR_FEF_SHIFT)
+#define I2S_BRD_RCSR_FEF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_RCSR_FEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEF(value)))
+#define I2S_BWR_RCSR_FEF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Sync error not detected.
+ * - 0b1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEF field. */
+#define I2S_RD_RCSR_SEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEF_MASK) >> I2S_RCSR_SEF_SHIFT)
+#define I2S_BRD_RCSR_SEF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_RCSR_SEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEF(value)))
+#define I2S_BWR_RCSR_SEF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Start of word not detected.
+ * - 0b1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSF field. */
+#define I2S_RD_RCSR_WSF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSF_MASK) >> I2S_RCSR_WSF_SHIFT)
+#define I2S_BRD_RCSR_WSF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_RCSR_WSF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK), I2S_RCSR_WSF(value)))
+#define I2S_BWR_RCSR_WSF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SR[24] (RW)
+ *
+ * Resets the internal receiver logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SR field. */
+#define I2S_RD_RCSR_SR(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SR_MASK) >> I2S_RCSR_SR_SHIFT)
+#define I2S_BRD_RCSR_SR(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_RCSR_SR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SR(value)))
+#define I2S_BWR_RCSR_SR(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the receiver is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_RCSR_FR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FR(value)))
+#define I2S_BWR_RCSR_FR(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field BCE[28] (RW)
+ *
+ * Enables the receive bit clock, separately from RE. This field is
+ * automatically set whenever RE is set. When software clears this field, the receive bit
+ * clock remains enabled, and this field remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0b0 - Receive bit clock is disabled.
+ * - 0b1 - Receive bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_BCE field. */
+#define I2S_RD_RCSR_BCE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_BCE_MASK) >> I2S_RCSR_BCE_SHIFT)
+#define I2S_BRD_RCSR_BCE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_RCSR_BCE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_BCE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_BCE(value)))
+#define I2S_BWR_RCSR_BCE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables receiver operation in Debug mode. The receive bit clock is
+ * not affected by Debug mode.
+ *
+ * Values:
+ * - 0b0 - Receiver is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 0b1 - Receiver is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_DBGE field. */
+#define I2S_RD_RCSR_DBGE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_DBGE_MASK) >> I2S_RCSR_DBGE_SHIFT)
+#define I2S_BRD_RCSR_DBGE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_RCSR_DBGE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_DBGE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_DBGE(value)))
+#define I2S_BWR_RCSR_DBGE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field STOPE[30] (RW)
+ *
+ * Configures receiver operation in Stop mode. This bit is ignored and the
+ * receiver is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0b0 - Receiver disabled in Stop mode.
+ * - 0b1 - Receiver enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_STOPE field. */
+#define I2S_RD_RCSR_STOPE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_STOPE_MASK) >> I2S_RCSR_STOPE_SHIFT)
+#define I2S_BRD_RCSR_STOPE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_RCSR_STOPE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_STOPE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_STOPE(value)))
+#define I2S_BWR_RCSR_STOPE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field RE[31] (RW)
+ *
+ * Enables/disables the receiver. When software clears this field, the receiver
+ * remains enabled, and this bit remains set, until the end of the current frame.
+ *
+ * Values:
+ * - 0b0 - Receiver is disabled.
+ * - 0b1 - Receiver is enabled, or receiver has been disabled and has not yet
+ *     reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_RE field. */
+#define I2S_RD_RCSR_RE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_RE_MASK) >> I2S_RCSR_RE_SHIFT)
+#define I2S_BRD_RCSR_RE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT))
+
+/*! @brief Set the RE field to a new value. */
+#define I2S_WR_RCSR_RE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_RE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_RE(value)))
+#define I2S_BWR_RCSR_RE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR1 - SAI Receive Configuration 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR1 register
+ */
+/*@{*/
+#define I2S_RD_RCR1(base)        (I2S_RCR1_REG(base))
+#define I2S_WR_RCR1(base, value) (I2S_RCR1_REG(base) = (value))
+#define I2S_RMW_RCR1(base, mask, value) (I2S_WR_RCR1(base, (I2S_RD_RCR1(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) |  (value)))
+#define I2S_CLR_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) & ~(value)))
+#define I2S_TOG_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR1, field RFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled receiver channels.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR1_RFW field. */
+#define I2S_RD_RCR1_RFW(base) ((I2S_RCR1_REG(base) & I2S_RCR1_RFW_MASK) >> I2S_RCR1_RFW_SHIFT)
+#define I2S_BRD_RCR1_RFW(base) (I2S_RD_RCR1_RFW(base))
+
+/*! @brief Set the RFW field to a new value. */
+#define I2S_WR_RCR1_RFW(base, value) (I2S_RMW_RCR1(base, I2S_RCR1_RFW_MASK, I2S_RCR1_RFW(value)))
+#define I2S_BWR_RCR1_RFW(base, value) (I2S_WR_RCR1_RFW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR2 - SAI Receive Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR2 register
+ */
+/*@{*/
+#define I2S_RD_RCR2(base)        (I2S_RCR2_REG(base))
+#define I2S_WR_RCR2(base, value) (I2S_RCR2_REG(base) = (value))
+#define I2S_RMW_RCR2(base, mask, value) (I2S_WR_RCR2(base, (I2S_RD_RCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) |  (value)))
+#define I2S_CLR_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) & ~(value)))
+#define I2S_TOG_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_DIV field. */
+#define I2S_RD_RCR2_DIV(base) ((I2S_RCR2_REG(base) & I2S_RCR2_DIV_MASK) >> I2S_RCR2_DIV_SHIFT)
+#define I2S_BRD_RCR2_DIV(base) (I2S_RD_RCR2_DIV(base))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_RCR2_DIV(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_DIV_MASK, I2S_RCR2_DIV(value)))
+#define I2S_BWR_RCR2_DIV(base, value) (I2S_WR_RCR2_DIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is generated externally in Slave mode.
+ * - 0b1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCD field. */
+#define I2S_RD_RCR2_BCD(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCD_MASK) >> I2S_RCR2_BCD_SHIFT)
+#define I2S_BRD_RCR2_BCD(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_RCR2_BCD(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCD_MASK, I2S_RCR2_BCD(value)))
+#define I2S_BWR_RCR2_BCD(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit Clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 0b1 - Bit Clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCP field. */
+#define I2S_RD_RCR2_BCP(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCP_MASK) >> I2S_RCR2_BCP_SHIFT)
+#define I2S_BRD_RCR2_BCP(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_RCR2_BCP(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCP_MASK, I2S_RCR2_BCP(value)))
+#define I2S_BWR_RCR2_BCP(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 0b00 - Bus Clock selected.
+ * - 0b01 - Master Clock (MCLK) 1 option selected.
+ * - 0b10 - Master Clock (MCLK) 2 option selected.
+ * - 0b11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_MSEL field. */
+#define I2S_RD_RCR2_MSEL(base) ((I2S_RCR2_REG(base) & I2S_RCR2_MSEL_MASK) >> I2S_RCR2_MSEL_SHIFT)
+#define I2S_BRD_RCR2_MSEL(base) (I2S_RD_RCR2_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_RCR2_MSEL(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_MSEL_MASK, I2S_RCR2_MSEL(value)))
+#define I2S_BWR_RCR2_MSEL(base, value) (I2S_WR_RCR2_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the receiver
+ * is delayed by the pad output delay (the receiver is clocked by the pad input
+ * as if the clock was externally generated). This has the effect of decreasing
+ * the data input setup time, but increasing the data output valid time. The slave
+ * mode timing from the datasheet should be used for the receiver when this bit
+ * is set. In synchronous mode, this bit allows the receiver to use the slave mode
+ * timing from the datasheet, while the transmitter uses the master mode timing.
+ * This field has no effect when configured for an externally generated bit
+ * clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCI field. */
+#define I2S_RD_RCR2_BCI(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCI_MASK) >> I2S_RCR2_BCI_SHIFT)
+#define I2S_BRD_RCR2_BCI(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_RCR2_BCI(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCI_MASK, I2S_RCR2_BCI(value)))
+#define I2S_BWR_RCR2_BCI(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the receiver. When the receiver is
+ * configured in asynchronous mode and this bit is set, the receiver is clocked by
+ * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the receiver continues to use the receiver
+ * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
+ * mode, the transmitter BCS field and receiver BCS field must be set to the same
+ * value. When both are set, the transmitter and receiver are both clocked by the
+ * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
+ * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
+ *
+ * Values:
+ * - 0b0 - Use the normal bit clock source.
+ * - 0b1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCS field. */
+#define I2S_RD_RCR2_BCS(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCS_MASK) >> I2S_RCR2_BCS_SHIFT)
+#define I2S_BRD_RCR2_BCS(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_RCR2_BCS(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCS_MASK, I2S_RCR2_BCS(value)))
+#define I2S_BWR_RCR2_BCS(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the transmitter or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 0b00 - Asynchronous mode.
+ * - 0b01 - Synchronous with transmitter.
+ * - 0b10 - Synchronous with another SAI receiver.
+ * - 0b11 - Synchronous with another SAI transmitter.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_SYNC field. */
+#define I2S_RD_RCR2_SYNC(base) ((I2S_RCR2_REG(base) & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT)
+#define I2S_BRD_RCR2_SYNC(base) (I2S_RD_RCR2_SYNC(base))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_RCR2_SYNC(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_SYNC_MASK, I2S_RCR2_SYNC(value)))
+#define I2S_BWR_RCR2_SYNC(base, value) (I2S_WR_RCR2_SYNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR3 - SAI Receive Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR3 register
+ */
+/*@{*/
+#define I2S_RD_RCR3(base)        (I2S_RCR3_REG(base))
+#define I2S_WR_RCR3(base, value) (I2S_RCR3_REG(base) = (value))
+#define I2S_RMW_RCR3(base, mask, value) (I2S_WR_RCR3(base, (I2S_RD_RCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) |  (value)))
+#define I2S_CLR_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) & ~(value)))
+#define I2S_TOG_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word the start of word flag is set. The value written should
+ * be one less than the word number (for example, write zero to configure for
+ * the first word in the frame). When configured to a value greater than the Frame
+ * Size field, then the start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_WDFL field. */
+#define I2S_RD_RCR3_WDFL(base) ((I2S_RCR3_REG(base) & I2S_RCR3_WDFL_MASK) >> I2S_RCR3_WDFL_SHIFT)
+#define I2S_BRD_RCR3_WDFL(base) (I2S_RD_RCR3_WDFL(base))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_RCR3_WDFL(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_WDFL_MASK, I2S_RCR3_WDFL(value)))
+#define I2S_BWR_RCR3_WDFL(base, value) (I2S_WR_RCR3_WDFL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR3, field RCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for receive operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0b00 - Receive data channel N is disabled.
+ * - 0b01 - Receive data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_RCE field. */
+#define I2S_RD_RCR3_RCE(base) ((I2S_RCR3_REG(base) & I2S_RCR3_RCE_MASK) >> I2S_RCR3_RCE_SHIFT)
+#define I2S_BRD_RCR3_RCE(base) (I2S_RD_RCR3_RCE(base))
+
+/*! @brief Set the RCE field to a new value. */
+#define I2S_WR_RCR3_RCE(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_RCE_MASK, I2S_RCR3_RCE(value)))
+#define I2S_BWR_RCR3_RCE(base, value) (I2S_WR_RCR3_RCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR4 - SAI Receive Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR4 register
+ */
+/*@{*/
+#define I2S_RD_RCR4(base)        (I2S_RCR4_REG(base))
+#define I2S_WR_RCR4(base, value) (I2S_RCR4_REG(base) = (value))
+#define I2S_RMW_RCR4(base, mask, value) (I2S_WR_RCR4(base, (I2S_RD_RCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) |  (value)))
+#define I2S_CLR_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) & ~(value)))
+#define I2S_TOG_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame Sync is generated externally in Slave mode.
+ * - 0b1 - Frame Sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSD field. */
+#define I2S_RD_RCR4_FSD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSD_MASK) >> I2S_RCR4_FSD_SHIFT)
+#define I2S_BRD_RCR4_FSD(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_RCR4_FSD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSD_MASK, I2S_RCR4_FSD(value)))
+#define I2S_BWR_RCR4_FSD(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is active high.
+ * - 0b1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSP field. */
+#define I2S_RD_RCR4_FSP(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSP_MASK) >> I2S_RCR4_FSP_SHIFT)
+#define I2S_BRD_RCR4_FSP(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_RCR4_FSP(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSP_MASK, I2S_RCR4_FSP(value)))
+#define I2S_BWR_RCR4_FSP(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Frame sync asserts with the first bit of the frame.
+ * - 0b1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSE field. */
+#define I2S_RD_RCR4_FSE(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSE_MASK) >> I2S_RCR4_FSE_SHIFT)
+#define I2S_BRD_RCR4_FSE(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_RCR4_FSE(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSE_MASK, I2S_RCR4_FSE(value)))
+#define I2S_BWR_RCR4_FSE(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is received first.
+ *
+ * Values:
+ * - 0b0 - LSB is received first.
+ * - 0b1 - MSB is received first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_MF field. */
+#define I2S_RD_RCR4_MF(base) ((I2S_RCR4_REG(base) & I2S_RCR4_MF_MASK) >> I2S_RCR4_MF_SHIFT)
+#define I2S_BRD_RCR4_MF(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_RCR4_MF(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_MF_MASK, I2S_RCR4_MF(value)))
+#define I2S_BWR_RCR4_MF(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_SYWD field. */
+#define I2S_RD_RCR4_SYWD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_SYWD_MASK) >> I2S_RCR4_SYWD_SHIFT)
+#define I2S_BRD_RCR4_SYWD(base) (I2S_RD_RCR4_SYWD(base))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_RCR4_SYWD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_SYWD_MASK, I2S_RCR4_SYWD(value)))
+#define I2S_BWR_RCR4_SYWD(base, value) (I2S_WR_RCR4_SYWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FRSZ field. */
+#define I2S_RD_RCR4_FRSZ(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FRSZ_MASK) >> I2S_RCR4_FRSZ_SHIFT)
+#define I2S_BRD_RCR4_FRSZ(base) (I2S_RD_RCR4_FRSZ(base))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_RCR4_FRSZ(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FRSZ_MASK, I2S_RCR4_FRSZ(value)))
+#define I2S_BWR_RCR4_FRSZ(base, value) (I2S_WR_RCR4_FRSZ(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR5 - SAI Receive Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR5 register
+ */
+/*@{*/
+#define I2S_RD_RCR5(base)        (I2S_RCR5_REG(base))
+#define I2S_WR_RCR5(base, value) (I2S_RCR5_REG(base) = (value))
+#define I2S_RMW_RCR5(base, mask, value) (I2S_WR_RCR5(base, (I2S_RD_RCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) |  (value)))
+#define I2S_CLR_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) & ~(value)))
+#define I2S_TOG_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit received for each word in the
+ * frame. If configured for MSB First, the index of the next bit received is one less
+ * than the current bit received. If configured for LSB First, the index of the
+ * next bit received is one more than the current bit received. The value written
+ * must be greater than or equal to the word width when configured for MSB
+ * First. The value written must be less than or equal to 31-word width when
+ * configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_FBT field. */
+#define I2S_RD_RCR5_FBT(base) ((I2S_RCR5_REG(base) & I2S_RCR5_FBT_MASK) >> I2S_RCR5_FBT_SHIFT)
+#define I2S_BRD_RCR5_FBT(base) (I2S_RD_RCR5_FBT(base))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_RCR5_FBT(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_FBT_MASK, I2S_RCR5_FBT(value)))
+#define I2S_BWR_RCR5_FBT(base, value) (I2S_WR_RCR5_FBT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_W0W field. */
+#define I2S_RD_RCR5_W0W(base) ((I2S_RCR5_REG(base) & I2S_RCR5_W0W_MASK) >> I2S_RCR5_W0W_SHIFT)
+#define I2S_BRD_RCR5_W0W(base) (I2S_RD_RCR5_W0W(base))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_RCR5_W0W(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_W0W_MASK, I2S_RCR5_W0W(value)))
+#define I2S_BWR_RCR5_W0W(base, value) (I2S_WR_RCR5_W0W(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_WNW field. */
+#define I2S_RD_RCR5_WNW(base) ((I2S_RCR5_REG(base) & I2S_RCR5_WNW_MASK) >> I2S_RCR5_WNW_SHIFT)
+#define I2S_BRD_RCR5_WNW(base) (I2S_RD_RCR5_WNW(base))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_RCR5_WNW(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_WNW_MASK, I2S_RCR5_WNW(value)))
+#define I2S_BWR_RCR5_WNW(base, value) (I2S_WR_RCR5_WNW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RDR - SAI Receive Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RDR - SAI Receive Data Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Reading this register introduces one additional peripheral clock wait state
+ * on each read.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RDR register
+ */
+/*@{*/
+#define I2S_RD_RDR(base, index)  (I2S_RDR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RFR - SAI Receive FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RFR - SAI Receive FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RFR register
+ */
+/*@{*/
+#define I2S_RD_RFR(base, index)  (I2S_RFR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RFR bitfields
+ */
+
+/*!
+ * @name Register I2S_RFR, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for receive data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RFR_RFP field. */
+#define I2S_RD_RFR_RFP(base, index) ((I2S_RFR_REG(base, index) & I2S_RFR_RFP_MASK) >> I2S_RFR_RFP_SHIFT)
+#define I2S_BRD_RFR_RFP(base, index) (I2S_RD_RFR_RFP(base, index))
+/*@}*/
+
+/*!
+ * @name Register I2S_RFR, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for receive data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RFR_WFP field. */
+#define I2S_RD_RFR_WFP(base, index) ((I2S_RFR_REG(base, index) & I2S_RFR_WFP_MASK) >> I2S_RFR_WFP_SHIFT)
+#define I2S_BRD_RFR_WFP(base, index) (I2S_RD_RFR_WFP(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RMR - SAI Receive Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RMR - SAI Receive Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When RCSR[RE] is first set At
+ * the end of each frame This allows the masked words in each frame to change from
+ * frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RMR register
+ */
+/*@{*/
+#define I2S_RD_RMR(base)         (I2S_RMR_REG(base))
+#define I2S_WR_RMR(base, value)  (I2S_RMR_REG(base) = (value))
+#define I2S_RMW_RMR(base, mask, value) (I2S_WR_RMR(base, (I2S_RD_RMR(base) & ~(mask)) | (value)))
+#define I2S_SET_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) |  (value)))
+#define I2S_CLR_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) & ~(value)))
+#define I2S_TOG_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MCR - SAI MCLK Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MCR - SAI MCLK Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Control Register (MCR) controls the clock source and direction of
+ * the audio master clock.
+ */
+/*!
+ * @name Constants and macros for entire I2S_MCR register
+ */
+/*@{*/
+#define I2S_RD_MCR(base)         (I2S_MCR_REG(base))
+#define I2S_WR_MCR(base, value)  (I2S_MCR_REG(base) = (value))
+#define I2S_RMW_MCR(base, mask, value) (I2S_WR_MCR(base, (I2S_RD_MCR(base) & ~(mask)) | (value)))
+#define I2S_SET_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) |  (value)))
+#define I2S_CLR_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) & ~(value)))
+#define I2S_TOG_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MCR bitfields
+ */
+
+/*!
+ * @name Register I2S_MCR, field MICS[25:24] (RW)
+ *
+ * Selects the clock input to the MCLK divider. This field cannot be changed
+ * while the MCLK divider is enabled. See the chip configuration details for
+ * information about the connections to these inputs.
+ *
+ * Values:
+ * - 0b00 - MCLK divider input clock 0 selected.
+ * - 0b01 - MCLK divider input clock 1 selected.
+ * - 0b10 - MCLK divider input clock 2 selected.
+ * - 0b11 - MCLK divider input clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MICS field. */
+#define I2S_RD_MCR_MICS(base) ((I2S_MCR_REG(base) & I2S_MCR_MICS_MASK) >> I2S_MCR_MICS_SHIFT)
+#define I2S_BRD_MCR_MICS(base) (I2S_RD_MCR_MICS(base))
+
+/*! @brief Set the MICS field to a new value. */
+#define I2S_WR_MCR_MICS(base, value) (I2S_RMW_MCR(base, I2S_MCR_MICS_MASK, I2S_MCR_MICS(value)))
+#define I2S_BWR_MCR_MICS(base, value) (I2S_WR_MCR_MICS(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field MOE[30] (RW)
+ *
+ * Enables the MCLK divider and configures the MCLK signal pin as an output.
+ * When software clears this field, it remains set until the MCLK divider is fully
+ * disabled.
+ *
+ * Values:
+ * - 0b0 - MCLK signal pin is configured as an input that bypasses the MCLK
+ *     divider.
+ * - 0b1 - MCLK signal pin is configured as an output from the MCLK divider and
+ *     the MCLK divider is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MOE field. */
+#define I2S_RD_MCR_MOE(base) ((I2S_MCR_REG(base) & I2S_MCR_MOE_MASK) >> I2S_MCR_MOE_SHIFT)
+#define I2S_BRD_MCR_MOE(base) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT))
+
+/*! @brief Set the MOE field to a new value. */
+#define I2S_WR_MCR_MOE(base, value) (I2S_RMW_MCR(base, I2S_MCR_MOE_MASK, I2S_MCR_MOE(value)))
+#define I2S_BWR_MCR_MOE(base, value) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field DUF[31] (RO)
+ *
+ * Provides the status of on-the-fly updates to the MCLK divider ratio.
+ *
+ * Values:
+ * - 0b0 - MCLK divider ratio is not being updated currently.
+ * - 0b1 - MCLK divider ratio is updating on-the-fly. Further updates to the
+ *     MCLK divider ratio are blocked while this flag remains set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_DUF field. */
+#define I2S_RD_MCR_DUF(base) ((I2S_MCR_REG(base) & I2S_MCR_DUF_MASK) >> I2S_MCR_DUF_SHIFT)
+#define I2S_BRD_MCR_DUF(base) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_DUF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MDR - SAI MCLK Divide Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MDR - SAI MCLK Divide Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
+ * MDR can be changed when the MCLK divider clock is enabled, additional writes
+ * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
+ * divided clock is disabled do not set MCR[DUF].
+ */
+/*!
+ * @name Constants and macros for entire I2S_MDR register
+ */
+/*@{*/
+#define I2S_RD_MDR(base)         (I2S_MDR_REG(base))
+#define I2S_WR_MDR(base, value)  (I2S_MDR_REG(base) = (value))
+#define I2S_RMW_MDR(base, mask, value) (I2S_WR_MDR(base, (I2S_RD_MDR(base) & ~(mask)) | (value)))
+#define I2S_SET_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) |  (value)))
+#define I2S_CLR_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) & ~(value)))
+#define I2S_TOG_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MDR bitfields
+ */
+
+/*!
+ * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MDR_DIVIDE field. */
+#define I2S_RD_MDR_DIVIDE(base) ((I2S_MDR_REG(base) & I2S_MDR_DIVIDE_MASK) >> I2S_MDR_DIVIDE_SHIFT)
+#define I2S_BRD_MDR_DIVIDE(base) (I2S_RD_MDR_DIVIDE(base))
+
+/*! @brief Set the DIVIDE field to a new value. */
+#define I2S_WR_MDR_DIVIDE(base, value) (I2S_RMW_MDR(base, I2S_MDR_DIVIDE_MASK, I2S_MDR_DIVIDE(value)))
+#define I2S_BWR_MDR_DIVIDE(base, value) (I2S_WR_MDR_DIVIDE(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MDR, field FRACT[19:12] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MDR_FRACT field. */
+#define I2S_RD_MDR_FRACT(base) ((I2S_MDR_REG(base) & I2S_MDR_FRACT_MASK) >> I2S_MDR_FRACT_SHIFT)
+#define I2S_BRD_MDR_FRACT(base) (I2S_RD_MDR_FRACT(base))
+
+/*! @brief Set the FRACT field to a new value. */
+#define I2S_WR_MDR_FRACT(base, value) (I2S_RMW_MDR(base, I2S_MDR_FRACT_MASK, I2S_MDR_FRACT(value)))
+#define I2S_BWR_MDR_FRACT(base, value) (I2S_WR_MDR_FRACT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 LLWU
+ *
+ * Low leakage wakeup unit
+ *
+ * Registers defined in this header file:
+ * - LLWU_PE1 - LLWU Pin Enable 1 register
+ * - LLWU_PE2 - LLWU Pin Enable 2 register
+ * - LLWU_PE3 - LLWU Pin Enable 3 register
+ * - LLWU_PE4 - LLWU Pin Enable 4 register
+ * - LLWU_ME - LLWU Module Enable register
+ * - LLWU_F1 - LLWU Flag 1 register
+ * - LLWU_F2 - LLWU Flag 2 register
+ * - LLWU_F3 - LLWU Flag 3 register
+ * - LLWU_FILT1 - LLWU Pin Filter 1 register
+ * - LLWU_FILT2 - LLWU Pin Filter 2 register
+ * - LLWU_RST - LLWU Reset Enable register
+ */
+
+#define LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
+#define LLWU_IDX (0U) /*!< Instance number for LLWU. */
+
+/*******************************************************************************
+ * LLWU_PE1 - LLWU Pin Enable 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE1 - LLWU Pin Enable 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE1 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE1 register
+ */
+/*@{*/
+#define LLWU_RD_PE1(base)        (LLWU_PE1_REG(base))
+#define LLWU_WR_PE1(base, value) (LLWU_PE1_REG(base) = (value))
+#define LLWU_RMW_PE1(base, mask, value) (LLWU_WR_PE1(base, (LLWU_RD_PE1(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) |  (value)))
+#define LLWU_CLR_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) & ~(value)))
+#define LLWU_TOG_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
+#define LLWU_RD_PE1_WUPE0(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE0_MASK) >> LLWU_PE1_WUPE0_SHIFT)
+#define LLWU_BRD_PE1_WUPE0(base) (LLWU_RD_PE1_WUPE0(base))
+
+/*! @brief Set the WUPE0 field to a new value. */
+#define LLWU_WR_PE1_WUPE0(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE0_MASK, LLWU_PE1_WUPE0(value)))
+#define LLWU_BWR_PE1_WUPE0(base, value) (LLWU_WR_PE1_WUPE0(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
+#define LLWU_RD_PE1_WUPE1(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE1_MASK) >> LLWU_PE1_WUPE1_SHIFT)
+#define LLWU_BRD_PE1_WUPE1(base) (LLWU_RD_PE1_WUPE1(base))
+
+/*! @brief Set the WUPE1 field to a new value. */
+#define LLWU_WR_PE1_WUPE1(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE1_MASK, LLWU_PE1_WUPE1(value)))
+#define LLWU_BWR_PE1_WUPE1(base, value) (LLWU_WR_PE1_WUPE1(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
+#define LLWU_RD_PE1_WUPE2(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE2_MASK) >> LLWU_PE1_WUPE2_SHIFT)
+#define LLWU_BRD_PE1_WUPE2(base) (LLWU_RD_PE1_WUPE2(base))
+
+/*! @brief Set the WUPE2 field to a new value. */
+#define LLWU_WR_PE1_WUPE2(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE2_MASK, LLWU_PE1_WUPE2(value)))
+#define LLWU_BWR_PE1_WUPE2(base, value) (LLWU_WR_PE1_WUPE2(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
+#define LLWU_RD_PE1_WUPE3(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE3_MASK) >> LLWU_PE1_WUPE3_SHIFT)
+#define LLWU_BRD_PE1_WUPE3(base) (LLWU_RD_PE1_WUPE3(base))
+
+/*! @brief Set the WUPE3 field to a new value. */
+#define LLWU_WR_PE1_WUPE3(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE3_MASK, LLWU_PE1_WUPE3(value)))
+#define LLWU_BWR_PE1_WUPE3(base, value) (LLWU_WR_PE1_WUPE3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE2 - LLWU Pin Enable 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE2 - LLWU Pin Enable 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE2 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE2 register
+ */
+/*@{*/
+#define LLWU_RD_PE2(base)        (LLWU_PE2_REG(base))
+#define LLWU_WR_PE2(base, value) (LLWU_PE2_REG(base) = (value))
+#define LLWU_RMW_PE2(base, mask, value) (LLWU_WR_PE2(base, (LLWU_RD_PE2(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) |  (value)))
+#define LLWU_CLR_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) & ~(value)))
+#define LLWU_TOG_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
+#define LLWU_RD_PE2_WUPE4(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE4_MASK) >> LLWU_PE2_WUPE4_SHIFT)
+#define LLWU_BRD_PE2_WUPE4(base) (LLWU_RD_PE2_WUPE4(base))
+
+/*! @brief Set the WUPE4 field to a new value. */
+#define LLWU_WR_PE2_WUPE4(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE4_MASK, LLWU_PE2_WUPE4(value)))
+#define LLWU_BWR_PE2_WUPE4(base, value) (LLWU_WR_PE2_WUPE4(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
+#define LLWU_RD_PE2_WUPE5(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE5_MASK) >> LLWU_PE2_WUPE5_SHIFT)
+#define LLWU_BRD_PE2_WUPE5(base) (LLWU_RD_PE2_WUPE5(base))
+
+/*! @brief Set the WUPE5 field to a new value. */
+#define LLWU_WR_PE2_WUPE5(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE5_MASK, LLWU_PE2_WUPE5(value)))
+#define LLWU_BWR_PE2_WUPE5(base, value) (LLWU_WR_PE2_WUPE5(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
+#define LLWU_RD_PE2_WUPE6(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE6_MASK) >> LLWU_PE2_WUPE6_SHIFT)
+#define LLWU_BRD_PE2_WUPE6(base) (LLWU_RD_PE2_WUPE6(base))
+
+/*! @brief Set the WUPE6 field to a new value. */
+#define LLWU_WR_PE2_WUPE6(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE6_MASK, LLWU_PE2_WUPE6(value)))
+#define LLWU_BWR_PE2_WUPE6(base, value) (LLWU_WR_PE2_WUPE6(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
+#define LLWU_RD_PE2_WUPE7(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE7_MASK) >> LLWU_PE2_WUPE7_SHIFT)
+#define LLWU_BRD_PE2_WUPE7(base) (LLWU_RD_PE2_WUPE7(base))
+
+/*! @brief Set the WUPE7 field to a new value. */
+#define LLWU_WR_PE2_WUPE7(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE7_MASK, LLWU_PE2_WUPE7(value)))
+#define LLWU_BWR_PE2_WUPE7(base, value) (LLWU_WR_PE2_WUPE7(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE3 - LLWU Pin Enable 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE3 - LLWU Pin Enable 3 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE3 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE3 register
+ */
+/*@{*/
+#define LLWU_RD_PE3(base)        (LLWU_PE3_REG(base))
+#define LLWU_WR_PE3(base, value) (LLWU_PE3_REG(base) = (value))
+#define LLWU_RMW_PE3(base, mask, value) (LLWU_WR_PE3(base, (LLWU_RD_PE3(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) |  (value)))
+#define LLWU_CLR_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) & ~(value)))
+#define LLWU_TOG_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
+#define LLWU_RD_PE3_WUPE8(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE8_MASK) >> LLWU_PE3_WUPE8_SHIFT)
+#define LLWU_BRD_PE3_WUPE8(base) (LLWU_RD_PE3_WUPE8(base))
+
+/*! @brief Set the WUPE8 field to a new value. */
+#define LLWU_WR_PE3_WUPE8(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE8_MASK, LLWU_PE3_WUPE8(value)))
+#define LLWU_BWR_PE3_WUPE8(base, value) (LLWU_WR_PE3_WUPE8(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
+#define LLWU_RD_PE3_WUPE9(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE9_MASK) >> LLWU_PE3_WUPE9_SHIFT)
+#define LLWU_BRD_PE3_WUPE9(base) (LLWU_RD_PE3_WUPE9(base))
+
+/*! @brief Set the WUPE9 field to a new value. */
+#define LLWU_WR_PE3_WUPE9(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE9_MASK, LLWU_PE3_WUPE9(value)))
+#define LLWU_BWR_PE3_WUPE9(base, value) (LLWU_WR_PE3_WUPE9(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
+#define LLWU_RD_PE3_WUPE10(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE10_MASK) >> LLWU_PE3_WUPE10_SHIFT)
+#define LLWU_BRD_PE3_WUPE10(base) (LLWU_RD_PE3_WUPE10(base))
+
+/*! @brief Set the WUPE10 field to a new value. */
+#define LLWU_WR_PE3_WUPE10(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE10_MASK, LLWU_PE3_WUPE10(value)))
+#define LLWU_BWR_PE3_WUPE10(base, value) (LLWU_WR_PE3_WUPE10(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
+#define LLWU_RD_PE3_WUPE11(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE11_MASK) >> LLWU_PE3_WUPE11_SHIFT)
+#define LLWU_BRD_PE3_WUPE11(base) (LLWU_RD_PE3_WUPE11(base))
+
+/*! @brief Set the WUPE11 field to a new value. */
+#define LLWU_WR_PE3_WUPE11(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE11_MASK, LLWU_PE3_WUPE11(value)))
+#define LLWU_BWR_PE3_WUPE11(base, value) (LLWU_WR_PE3_WUPE11(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE4 - LLWU Pin Enable 4 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE4 - LLWU Pin Enable 4 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE4 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE4 register
+ */
+/*@{*/
+#define LLWU_RD_PE4(base)        (LLWU_PE4_REG(base))
+#define LLWU_WR_PE4(base, value) (LLWU_PE4_REG(base) = (value))
+#define LLWU_RMW_PE4(base, mask, value) (LLWU_WR_PE4(base, (LLWU_RD_PE4(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) |  (value)))
+#define LLWU_CLR_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) & ~(value)))
+#define LLWU_TOG_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE4 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
+#define LLWU_RD_PE4_WUPE12(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE12_MASK) >> LLWU_PE4_WUPE12_SHIFT)
+#define LLWU_BRD_PE4_WUPE12(base) (LLWU_RD_PE4_WUPE12(base))
+
+/*! @brief Set the WUPE12 field to a new value. */
+#define LLWU_WR_PE4_WUPE12(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE12_MASK, LLWU_PE4_WUPE12(value)))
+#define LLWU_BWR_PE4_WUPE12(base, value) (LLWU_WR_PE4_WUPE12(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
+#define LLWU_RD_PE4_WUPE13(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE13_MASK) >> LLWU_PE4_WUPE13_SHIFT)
+#define LLWU_BRD_PE4_WUPE13(base) (LLWU_RD_PE4_WUPE13(base))
+
+/*! @brief Set the WUPE13 field to a new value. */
+#define LLWU_WR_PE4_WUPE13(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE13_MASK, LLWU_PE4_WUPE13(value)))
+#define LLWU_BWR_PE4_WUPE13(base, value) (LLWU_WR_PE4_WUPE13(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
+#define LLWU_RD_PE4_WUPE14(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE14_MASK) >> LLWU_PE4_WUPE14_SHIFT)
+#define LLWU_BRD_PE4_WUPE14(base) (LLWU_RD_PE4_WUPE14(base))
+
+/*! @brief Set the WUPE14 field to a new value. */
+#define LLWU_WR_PE4_WUPE14(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE14_MASK, LLWU_PE4_WUPE14(value)))
+#define LLWU_BWR_PE4_WUPE14(base, value) (LLWU_WR_PE4_WUPE14(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
+#define LLWU_RD_PE4_WUPE15(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE15_MASK) >> LLWU_PE4_WUPE15_SHIFT)
+#define LLWU_BRD_PE4_WUPE15(base) (LLWU_RD_PE4_WUPE15(base))
+
+/*! @brief Set the WUPE15 field to a new value. */
+#define LLWU_WR_PE4_WUPE15(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE15_MASK, LLWU_PE4_WUPE15(value)))
+#define LLWU_BWR_PE4_WUPE15(base, value) (LLWU_WR_PE4_WUPE15(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_ME - LLWU Module Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_ME - LLWU Module Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_ME contains the bits to enable the internal module flag as a wakeup
+ * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
+ * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
+ * reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
+ * RCM implements many of the reset functions for the chip. See the chip's reset
+ * chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_ME register
+ */
+/*@{*/
+#define LLWU_RD_ME(base)         (LLWU_ME_REG(base))
+#define LLWU_WR_ME(base, value)  (LLWU_ME_REG(base) = (value))
+#define LLWU_RMW_ME(base, mask, value) (LLWU_WR_ME(base, (LLWU_RD_ME(base) & ~(mask)) | (value)))
+#define LLWU_SET_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) |  (value)))
+#define LLWU_CLR_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) & ~(value)))
+#define LLWU_TOG_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_ME bitfields
+ */
+
+/*!
+ * @name Register LLWU_ME, field WUME0[0] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME0 field. */
+#define LLWU_RD_ME_WUME0(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME0_MASK) >> LLWU_ME_WUME0_SHIFT)
+#define LLWU_BRD_ME_WUME0(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT))
+
+/*! @brief Set the WUME0 field to a new value. */
+#define LLWU_WR_ME_WUME0(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME0_MASK, LLWU_ME_WUME0(value)))
+#define LLWU_BWR_ME_WUME0(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME1[1] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME1 field. */
+#define LLWU_RD_ME_WUME1(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME1_MASK) >> LLWU_ME_WUME1_SHIFT)
+#define LLWU_BRD_ME_WUME1(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT))
+
+/*! @brief Set the WUME1 field to a new value. */
+#define LLWU_WR_ME_WUME1(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME1_MASK, LLWU_ME_WUME1(value)))
+#define LLWU_BWR_ME_WUME1(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME2[2] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME2 field. */
+#define LLWU_RD_ME_WUME2(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME2_MASK) >> LLWU_ME_WUME2_SHIFT)
+#define LLWU_BRD_ME_WUME2(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT))
+
+/*! @brief Set the WUME2 field to a new value. */
+#define LLWU_WR_ME_WUME2(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME2_MASK, LLWU_ME_WUME2(value)))
+#define LLWU_BWR_ME_WUME2(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME3[3] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME3 field. */
+#define LLWU_RD_ME_WUME3(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME3_MASK) >> LLWU_ME_WUME3_SHIFT)
+#define LLWU_BRD_ME_WUME3(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT))
+
+/*! @brief Set the WUME3 field to a new value. */
+#define LLWU_WR_ME_WUME3(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME3_MASK, LLWU_ME_WUME3(value)))
+#define LLWU_BWR_ME_WUME3(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME4[4] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME4 field. */
+#define LLWU_RD_ME_WUME4(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME4_MASK) >> LLWU_ME_WUME4_SHIFT)
+#define LLWU_BRD_ME_WUME4(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT))
+
+/*! @brief Set the WUME4 field to a new value. */
+#define LLWU_WR_ME_WUME4(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME4_MASK, LLWU_ME_WUME4(value)))
+#define LLWU_BWR_ME_WUME4(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME5[5] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME5 field. */
+#define LLWU_RD_ME_WUME5(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME5_MASK) >> LLWU_ME_WUME5_SHIFT)
+#define LLWU_BRD_ME_WUME5(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT))
+
+/*! @brief Set the WUME5 field to a new value. */
+#define LLWU_WR_ME_WUME5(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME5_MASK, LLWU_ME_WUME5(value)))
+#define LLWU_BWR_ME_WUME5(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME6[6] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME6 field. */
+#define LLWU_RD_ME_WUME6(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME6_MASK) >> LLWU_ME_WUME6_SHIFT)
+#define LLWU_BRD_ME_WUME6(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT))
+
+/*! @brief Set the WUME6 field to a new value. */
+#define LLWU_WR_ME_WUME6(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME6_MASK, LLWU_ME_WUME6(value)))
+#define LLWU_BWR_ME_WUME6(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME7[7] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME7 field. */
+#define LLWU_RD_ME_WUME7(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME7_MASK) >> LLWU_ME_WUME7_SHIFT)
+#define LLWU_BRD_ME_WUME7(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT))
+
+/*! @brief Set the WUME7 field to a new value. */
+#define LLWU_WR_ME_WUME7(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME7_MASK, LLWU_ME_WUME7(value)))
+#define LLWU_BWR_ME_WUME7(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F1 - LLWU Flag 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F1 - LLWU Flag 1 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F1 register
+ */
+/*@{*/
+#define LLWU_RD_F1(base)         (LLWU_F1_REG(base))
+#define LLWU_WR_F1(base, value)  (LLWU_F1_REG(base) = (value))
+#define LLWU_RMW_F1(base, mask, value) (LLWU_WR_F1(base, (LLWU_RD_F1(base) & ~(mask)) | (value)))
+#define LLWU_SET_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) |  (value)))
+#define LLWU_CLR_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) & ~(value)))
+#define LLWU_TOG_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F1, field WUF0[0] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF0.
+ *
+ * Values:
+ * - 0b0 - LLWU_P0 input was not a wakeup source
+ * - 0b1 - LLWU_P0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF0 field. */
+#define LLWU_RD_F1_WUF0(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF0_MASK) >> LLWU_F1_WUF0_SHIFT)
+#define LLWU_BRD_F1_WUF0(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT))
+
+/*! @brief Set the WUF0 field to a new value. */
+#define LLWU_WR_F1_WUF0(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF0(value)))
+#define LLWU_BWR_F1_WUF0(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF1[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF1.
+ *
+ * Values:
+ * - 0b0 - LLWU_P1 input was not a wakeup source
+ * - 0b1 - LLWU_P1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF1 field. */
+#define LLWU_RD_F1_WUF1(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF1_MASK) >> LLWU_F1_WUF1_SHIFT)
+#define LLWU_BRD_F1_WUF1(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT))
+
+/*! @brief Set the WUF1 field to a new value. */
+#define LLWU_WR_F1_WUF1(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF1_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF1(value)))
+#define LLWU_BWR_F1_WUF1(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF2[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF2.
+ *
+ * Values:
+ * - 0b0 - LLWU_P2 input was not a wakeup source
+ * - 0b1 - LLWU_P2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF2 field. */
+#define LLWU_RD_F1_WUF2(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF2_MASK) >> LLWU_F1_WUF2_SHIFT)
+#define LLWU_BRD_F1_WUF2(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT))
+
+/*! @brief Set the WUF2 field to a new value. */
+#define LLWU_WR_F1_WUF2(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF2_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF2(value)))
+#define LLWU_BWR_F1_WUF2(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF3[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF3.
+ *
+ * Values:
+ * - 0b0 - LLWU_P3 input was not a wake-up source
+ * - 0b1 - LLWU_P3 input was a wake-up source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF3 field. */
+#define LLWU_RD_F1_WUF3(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF3_MASK) >> LLWU_F1_WUF3_SHIFT)
+#define LLWU_BRD_F1_WUF3(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT))
+
+/*! @brief Set the WUF3 field to a new value. */
+#define LLWU_WR_F1_WUF3(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF3_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF3(value)))
+#define LLWU_BWR_F1_WUF3(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF4[4] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF4.
+ *
+ * Values:
+ * - 0b0 - LLWU_P4 input was not a wakeup source
+ * - 0b1 - LLWU_P4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF4 field. */
+#define LLWU_RD_F1_WUF4(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF4_MASK) >> LLWU_F1_WUF4_SHIFT)
+#define LLWU_BRD_F1_WUF4(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT))
+
+/*! @brief Set the WUF4 field to a new value. */
+#define LLWU_WR_F1_WUF4(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF4_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF4(value)))
+#define LLWU_BWR_F1_WUF4(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF5[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF5.
+ *
+ * Values:
+ * - 0b0 - LLWU_P5 input was not a wakeup source
+ * - 0b1 - LLWU_P5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF5 field. */
+#define LLWU_RD_F1_WUF5(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF5_MASK) >> LLWU_F1_WUF5_SHIFT)
+#define LLWU_BRD_F1_WUF5(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT))
+
+/*! @brief Set the WUF5 field to a new value. */
+#define LLWU_WR_F1_WUF5(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF5_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF5(value)))
+#define LLWU_BWR_F1_WUF5(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF6[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF6.
+ *
+ * Values:
+ * - 0b0 - LLWU_P6 input was not a wakeup source
+ * - 0b1 - LLWU_P6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF6 field. */
+#define LLWU_RD_F1_WUF6(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF6_MASK) >> LLWU_F1_WUF6_SHIFT)
+#define LLWU_BRD_F1_WUF6(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT))
+
+/*! @brief Set the WUF6 field to a new value. */
+#define LLWU_WR_F1_WUF6(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF6_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF6(value)))
+#define LLWU_BWR_F1_WUF6(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF7[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF7.
+ *
+ * Values:
+ * - 0b0 - LLWU_P7 input was not a wakeup source
+ * - 0b1 - LLWU_P7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF7 field. */
+#define LLWU_RD_F1_WUF7(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF7_MASK) >> LLWU_F1_WUF7_SHIFT)
+#define LLWU_BRD_F1_WUF7(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT))
+
+/*! @brief Set the WUF7 field to a new value. */
+#define LLWU_WR_F1_WUF7(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF7_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK), LLWU_F1_WUF7(value)))
+#define LLWU_BWR_F1_WUF7(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F2 - LLWU Flag 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F2 - LLWU Flag 2 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F2 register
+ */
+/*@{*/
+#define LLWU_RD_F2(base)         (LLWU_F2_REG(base))
+#define LLWU_WR_F2(base, value)  (LLWU_F2_REG(base) = (value))
+#define LLWU_RMW_F2(base, mask, value) (LLWU_WR_F2(base, (LLWU_RD_F2(base) & ~(mask)) | (value)))
+#define LLWU_SET_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) |  (value)))
+#define LLWU_CLR_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) & ~(value)))
+#define LLWU_TOG_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F2, field WUF8[0] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF8.
+ *
+ * Values:
+ * - 0b0 - LLWU_P8 input was not a wakeup source
+ * - 0b1 - LLWU_P8 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF8 field. */
+#define LLWU_RD_F2_WUF8(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF8_MASK) >> LLWU_F2_WUF8_SHIFT)
+#define LLWU_BRD_F2_WUF8(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT))
+
+/*! @brief Set the WUF8 field to a new value. */
+#define LLWU_WR_F2_WUF8(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF8(value)))
+#define LLWU_BWR_F2_WUF8(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF9[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF9.
+ *
+ * Values:
+ * - 0b0 - LLWU_P9 input was not a wakeup source
+ * - 0b1 - LLWU_P9 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF9 field. */
+#define LLWU_RD_F2_WUF9(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF9_MASK) >> LLWU_F2_WUF9_SHIFT)
+#define LLWU_BRD_F2_WUF9(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT))
+
+/*! @brief Set the WUF9 field to a new value. */
+#define LLWU_WR_F2_WUF9(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF9_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF9(value)))
+#define LLWU_BWR_F2_WUF9(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF10[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF10.
+ *
+ * Values:
+ * - 0b0 - LLWU_P10 input was not a wakeup source
+ * - 0b1 - LLWU_P10 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF10 field. */
+#define LLWU_RD_F2_WUF10(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF10_MASK) >> LLWU_F2_WUF10_SHIFT)
+#define LLWU_BRD_F2_WUF10(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT))
+
+/*! @brief Set the WUF10 field to a new value. */
+#define LLWU_WR_F2_WUF10(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF10_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF10(value)))
+#define LLWU_BWR_F2_WUF10(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF11[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF11.
+ *
+ * Values:
+ * - 0b0 - LLWU_P11 input was not a wakeup source
+ * - 0b1 - LLWU_P11 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF11 field. */
+#define LLWU_RD_F2_WUF11(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF11_MASK) >> LLWU_F2_WUF11_SHIFT)
+#define LLWU_BRD_F2_WUF11(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT))
+
+/*! @brief Set the WUF11 field to a new value. */
+#define LLWU_WR_F2_WUF11(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF11_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF11(value)))
+#define LLWU_BWR_F2_WUF11(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF12[4] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF12.
+ *
+ * Values:
+ * - 0b0 - LLWU_P12 input was not a wakeup source
+ * - 0b1 - LLWU_P12 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF12 field. */
+#define LLWU_RD_F2_WUF12(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF12_MASK) >> LLWU_F2_WUF12_SHIFT)
+#define LLWU_BRD_F2_WUF12(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT))
+
+/*! @brief Set the WUF12 field to a new value. */
+#define LLWU_WR_F2_WUF12(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF12_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF12(value)))
+#define LLWU_BWR_F2_WUF12(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF13[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF13.
+ *
+ * Values:
+ * - 0b0 - LLWU_P13 input was not a wakeup source
+ * - 0b1 - LLWU_P13 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF13 field. */
+#define LLWU_RD_F2_WUF13(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF13_MASK) >> LLWU_F2_WUF13_SHIFT)
+#define LLWU_BRD_F2_WUF13(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT))
+
+/*! @brief Set the WUF13 field to a new value. */
+#define LLWU_WR_F2_WUF13(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF13_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF13(value)))
+#define LLWU_BWR_F2_WUF13(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF14[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF14.
+ *
+ * Values:
+ * - 0b0 - LLWU_P14 input was not a wakeup source
+ * - 0b1 - LLWU_P14 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF14 field. */
+#define LLWU_RD_F2_WUF14(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF14_MASK) >> LLWU_F2_WUF14_SHIFT)
+#define LLWU_BRD_F2_WUF14(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT))
+
+/*! @brief Set the WUF14 field to a new value. */
+#define LLWU_WR_F2_WUF14(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF14_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF14(value)))
+#define LLWU_BWR_F2_WUF14(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF15[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF15.
+ *
+ * Values:
+ * - 0b0 - LLWU_P15 input was not a wakeup source
+ * - 0b1 - LLWU_P15 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF15 field. */
+#define LLWU_RD_F2_WUF15(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF15_MASK) >> LLWU_F2_WUF15_SHIFT)
+#define LLWU_BRD_F2_WUF15(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT))
+
+/*! @brief Set the WUF15 field to a new value. */
+#define LLWU_WR_F2_WUF15(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF15_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK), LLWU_F2_WUF15(value)))
+#define LLWU_BWR_F2_WUF15(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F3 - LLWU Flag 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F3 - LLWU Flag 3 register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
+ * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
+ * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
+ * For internal peripherals that are capable of running in a low-leakage power
+ * mode, such as a real time clock module or CMP module, the flag from the
+ * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
+ * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
+ * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
+ * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
+ * the IntroductionInformation found here describes the registers of the Reset
+ * Control Module (RCM). The RCM implements many of the reset functions for the
+ * chip. See the chip's reset chapter for more information. details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F3 register
+ */
+/*@{*/
+#define LLWU_RD_F3(base)         (LLWU_F3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F3, field MWUF0[0] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 0 input was not a wakeup source
+ * - 0b1 - Module 0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF0 field. */
+#define LLWU_RD_F3_MWUF0(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF0_MASK) >> LLWU_F3_MWUF0_SHIFT)
+#define LLWU_BRD_F3_MWUF0(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF1[1] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 1 input was not a wakeup source
+ * - 0b1 - Module 1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF1 field. */
+#define LLWU_RD_F3_MWUF1(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF1_MASK) >> LLWU_F3_MWUF1_SHIFT)
+#define LLWU_BRD_F3_MWUF1(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF2[2] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 2 input was not a wakeup source
+ * - 0b1 - Module 2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF2 field. */
+#define LLWU_RD_F3_MWUF2(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF2_MASK) >> LLWU_F3_MWUF2_SHIFT)
+#define LLWU_BRD_F3_MWUF2(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF2_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF3[3] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 3 input was not a wakeup source
+ * - 0b1 - Module 3 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF3 field. */
+#define LLWU_RD_F3_MWUF3(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF3_MASK) >> LLWU_F3_MWUF3_SHIFT)
+#define LLWU_BRD_F3_MWUF3(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF3_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF4[4] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 4 input was not a wakeup source
+ * - 0b1 - Module 4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF4 field. */
+#define LLWU_RD_F3_MWUF4(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF4_MASK) >> LLWU_F3_MWUF4_SHIFT)
+#define LLWU_BRD_F3_MWUF4(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF4_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF5[5] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 5 input was not a wakeup source
+ * - 0b1 - Module 5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF5 field. */
+#define LLWU_RD_F3_MWUF5(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF5_MASK) >> LLWU_F3_MWUF5_SHIFT)
+#define LLWU_BRD_F3_MWUF5(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF5_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF6[6] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 6 input was not a wakeup source
+ * - 0b1 - Module 6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF6 field. */
+#define LLWU_RD_F3_MWUF6(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF6_MASK) >> LLWU_F3_MWUF6_SHIFT)
+#define LLWU_BRD_F3_MWUF6(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF6_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF7[7] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 7 input was not a wakeup source
+ * - 0b1 - Module 7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF7 field. */
+#define LLWU_RD_F3_MWUF7(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF7_MASK) >> LLWU_F3_MWUF7_SHIFT)
+#define LLWU_BRD_F3_MWUF7(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF7_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT1 - LLWU Pin Filter 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT1 is a control and status register that is used to enable/disable
+ * the digital filter 1 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT1 register
+ */
+/*@{*/
+#define LLWU_RD_FILT1(base)      (LLWU_FILT1_REG(base))
+#define LLWU_WR_FILT1(base, value) (LLWU_FILT1_REG(base) = (value))
+#define LLWU_RMW_FILT1(base, mask, value) (LLWU_WR_FILT1(base, (LLWU_RD_FILT1(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) |  (value)))
+#define LLWU_CLR_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) & ~(value)))
+#define LLWU_TOG_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0b0000 - Select LLWU_P0 for filter
+ * - 0b1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
+#define LLWU_RD_FILT1_FILTSEL(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTSEL_MASK) >> LLWU_FILT1_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT1_FILTSEL(base) (LLWU_RD_FILT1_FILTSEL(base))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT1_FILTSEL(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTSEL(value)))
+#define LLWU_BWR_FILT1_FILTSEL(base, value) (LLWU_WR_FILT1_FILTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 0b00 - Filter disabled
+ * - 0b01 - Filter posedge detect enabled
+ * - 0b10 - Filter negedge detect enabled
+ * - 0b11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTE field. */
+#define LLWU_RD_FILT1_FILTE(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTE_MASK) >> LLWU_FILT1_FILTE_SHIFT)
+#define LLWU_BRD_FILT1_FILTE(base) (LLWU_RD_FILT1_FILTE(base))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT1_FILTE(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTE_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTE(value)))
+#define LLWU_BWR_FILT1_FILTE(base, value) (LLWU_WR_FILT1_FILTE(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0b0 - Pin Filter 1 was not a wakeup source
+ * - 0b1 - Pin Filter 1 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTF field. */
+#define LLWU_RD_FILT1_FILTF(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTF_MASK) >> LLWU_FILT1_FILTF_SHIFT)
+#define LLWU_BRD_FILT1_FILTF(base) (BITBAND_ACCESS8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT1_FILTF(base, value) (LLWU_RMW_FILT1(base, LLWU_FILT1_FILTF_MASK, LLWU_FILT1_FILTF(value)))
+#define LLWU_BWR_FILT1_FILTF(base, value) (BITBAND_ACCESS8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT2 - LLWU Pin Filter 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT2 is a control and status register that is used to enable/disable
+ * the digital filter 2 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT2 register
+ */
+/*@{*/
+#define LLWU_RD_FILT2(base)      (LLWU_FILT2_REG(base))
+#define LLWU_WR_FILT2(base, value) (LLWU_FILT2_REG(base) = (value))
+#define LLWU_RMW_FILT2(base, mask, value) (LLWU_WR_FILT2(base, (LLWU_RD_FILT2(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) |  (value)))
+#define LLWU_CLR_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) & ~(value)))
+#define LLWU_TOG_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0b0000 - Select LLWU_P0 for filter
+ * - 0b1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
+#define LLWU_RD_FILT2_FILTSEL(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTSEL_MASK) >> LLWU_FILT2_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT2_FILTSEL(base) (LLWU_RD_FILT2_FILTSEL(base))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT2_FILTSEL(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTSEL_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTSEL(value)))
+#define LLWU_BWR_FILT2_FILTSEL(base, value) (LLWU_WR_FILT2_FILTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 0b00 - Filter disabled
+ * - 0b01 - Filter posedge detect enabled
+ * - 0b10 - Filter negedge detect enabled
+ * - 0b11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTE field. */
+#define LLWU_RD_FILT2_FILTE(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTE_MASK) >> LLWU_FILT2_FILTE_SHIFT)
+#define LLWU_BRD_FILT2_FILTE(base) (LLWU_RD_FILT2_FILTE(base))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT2_FILTE(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTE_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTE(value)))
+#define LLWU_BWR_FILT2_FILTE(base, value) (LLWU_WR_FILT2_FILTE(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0b0 - Pin Filter 2 was not a wakeup source
+ * - 0b1 - Pin Filter 2 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTF field. */
+#define LLWU_RD_FILT2_FILTF(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTF_MASK) >> LLWU_FILT2_FILTF_SHIFT)
+#define LLWU_BRD_FILT2_FILTF(base) (BITBAND_ACCESS8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT2_FILTF(base, value) (LLWU_RMW_FILT2(base, LLWU_FILT2_FILTF_MASK, LLWU_FILT2_FILTF(value)))
+#define LLWU_BWR_FILT2_FILTF(base, value) (BITBAND_ACCESS8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_RST - LLWU Reset Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_RST - LLWU Reset Enable register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * LLWU_RST is a control register that is used to enable/disable the digital
+ * filter for the external pin detect and RESET pin. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_RST register
+ */
+/*@{*/
+#define LLWU_RD_RST(base)        (LLWU_RST_REG(base))
+#define LLWU_WR_RST(base, value) (LLWU_RST_REG(base) = (value))
+#define LLWU_RMW_RST(base, mask, value) (LLWU_WR_RST(base, (LLWU_RD_RST(base) & ~(mask)) | (value)))
+#define LLWU_SET_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) |  (value)))
+#define LLWU_CLR_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) & ~(value)))
+#define LLWU_TOG_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_RST bitfields
+ */
+
+/*!
+ * @name Register LLWU_RST, field RSTFILT[0] (RW)
+ *
+ * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
+ * VLLS1 modes.
+ *
+ * Values:
+ * - 0b0 - Filter not enabled
+ * - 0b1 - Filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_RST_RSTFILT field. */
+#define LLWU_RD_RST_RSTFILT(base) ((LLWU_RST_REG(base) & LLWU_RST_RSTFILT_MASK) >> LLWU_RST_RSTFILT_SHIFT)
+#define LLWU_BRD_RST_RSTFILT(base) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_RSTFILT_SHIFT))
+
+/*! @brief Set the RSTFILT field to a new value. */
+#define LLWU_WR_RST_RSTFILT(base, value) (LLWU_RMW_RST(base, LLWU_RST_RSTFILT_MASK, LLWU_RST_RSTFILT(value)))
+#define LLWU_BWR_RST_RSTFILT(base, value) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_RSTFILT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_RST, field LLRSTE[1] (RW)
+ *
+ * This bit must be set to allow the device to be reset while in a low-leakage
+ * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
+ * also be enabled in the explicit port mux control.
+ *
+ * Values:
+ * - 0b0 - RESET pin not enabled as a leakage mode exit source
+ * - 0b1 - RESET pin enabled as a low leakage mode exit source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_RST_LLRSTE field. */
+#define LLWU_RD_RST_LLRSTE(base) ((LLWU_RST_REG(base) & LLWU_RST_LLRSTE_MASK) >> LLWU_RST_LLRSTE_SHIFT)
+#define LLWU_BRD_RST_LLRSTE(base) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_LLRSTE_SHIFT))
+
+/*! @brief Set the LLRSTE field to a new value. */
+#define LLWU_WR_RST_LLRSTE(base, value) (LLWU_RMW_RST(base, LLWU_RST_LLRSTE_MASK, LLWU_RST_LLRSTE(value)))
+#define LLWU_BWR_RST_LLRSTE(base, value) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_LLRSTE_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 LPTMR
+ *
+ * Low Power Timer
+ *
+ * Registers defined in this header file:
+ * - LPTMR_CSR - Low Power Timer Control Status Register
+ * - LPTMR_PSR - Low Power Timer Prescale Register
+ * - LPTMR_CMR - Low Power Timer Compare Register
+ * - LPTMR_CNR - Low Power Timer Counter Register
+ */
+
+#define LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
+#define LPTMR0_IDX (0U) /*!< Instance number for LPTMR0. */
+
+/*******************************************************************************
+ * LPTMR_CSR - Low Power Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CSR - Low Power Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CSR register
+ */
+/*@{*/
+#define LPTMR_RD_CSR(base)       (LPTMR_CSR_REG(base))
+#define LPTMR_WR_CSR(base, value) (LPTMR_CSR_REG(base) = (value))
+#define LPTMR_RMW_CSR(base, mask, value) (LPTMR_WR_CSR(base, (LPTMR_RD_CSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) |  (value)))
+#define LPTMR_CLR_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) & ~(value)))
+#define LPTMR_TOG_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CSR, field TEN[0] (RW)
+ *
+ * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
+ * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
+ * CSR[5:1] must not be altered.
+ *
+ * Values:
+ * - 0b0 - LPTMR is disabled and internal logic is reset.
+ * - 0b1 - LPTMR is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TEN field. */
+#define LPTMR_RD_CSR_TEN(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TEN_MASK) >> LPTMR_CSR_TEN_SHIFT)
+#define LPTMR_BRD_CSR_TEN(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT))
+
+/*! @brief Set the TEN field to a new value. */
+#define LPTMR_WR_CSR_TEN(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TEN_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TEN(value)))
+#define LPTMR_BWR_CSR_TEN(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TMS[1] (RW)
+ *
+ * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
+ * disabled.
+ *
+ * Values:
+ * - 0b0 - Time Counter mode.
+ * - 0b1 - Pulse Counter mode.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TMS field. */
+#define LPTMR_RD_CSR_TMS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TMS_MASK) >> LPTMR_CSR_TMS_SHIFT)
+#define LPTMR_BRD_CSR_TMS(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT))
+
+/*! @brief Set the TMS field to a new value. */
+#define LPTMR_WR_CSR_TMS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TMS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TMS(value)))
+#define LPTMR_BWR_CSR_TMS(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TFC[2] (RW)
+ *
+ * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
+ * TFC configures the CNR to reset on overflow. TFC must be altered only when the
+ * LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - CNR is reset whenever TCF is set.
+ * - 0b1 - CNR is reset on overflow.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TFC field. */
+#define LPTMR_RD_CSR_TFC(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TFC_MASK) >> LPTMR_CSR_TFC_SHIFT)
+#define LPTMR_BRD_CSR_TFC(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT))
+
+/*! @brief Set the TFC field to a new value. */
+#define LPTMR_WR_CSR_TFC(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TFC_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TFC(value)))
+#define LPTMR_BWR_CSR_TFC(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPP[3] (RW)
+ *
+ * Configures the polarity of the input source in Pulse Counter mode. TPP must
+ * be changed only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - Pulse Counter input source is active-high, and the CNR will increment
+ *     on the rising-edge.
+ * - 0b1 - Pulse Counter input source is active-low, and the CNR will increment
+ *     on the falling-edge.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPP field. */
+#define LPTMR_RD_CSR_TPP(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPP_MASK) >> LPTMR_CSR_TPP_SHIFT)
+#define LPTMR_BRD_CSR_TPP(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT))
+
+/*! @brief Set the TPP field to a new value. */
+#define LPTMR_WR_CSR_TPP(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPP_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPP(value)))
+#define LPTMR_BWR_CSR_TPP(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPS[5:4] (RW)
+ *
+ * Configures the input source to be used in Pulse Counter mode. TPS must be
+ * altered only when the LPTMR is disabled. The input connections vary by device.
+ * See the chip configuration details for information on the connections to these
+ * inputs.
+ *
+ * Values:
+ * - 0b00 - Pulse counter input 0 is selected.
+ * - 0b01 - Pulse counter input 1 is selected.
+ * - 0b10 - Pulse counter input 2 is selected.
+ * - 0b11 - Pulse counter input 3 is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPS field. */
+#define LPTMR_RD_CSR_TPS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPS_MASK) >> LPTMR_CSR_TPS_SHIFT)
+#define LPTMR_BRD_CSR_TPS(base) (LPTMR_RD_CSR_TPS(base))
+
+/*! @brief Set the TPS field to a new value. */
+#define LPTMR_WR_CSR_TPS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPS(value)))
+#define LPTMR_BWR_CSR_TPS(base, value) (LPTMR_WR_CSR_TPS(base, value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TIE[6] (RW)
+ *
+ * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
+ *
+ * Values:
+ * - 0b0 - Timer interrupt disabled.
+ * - 0b1 - Timer interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TIE field. */
+#define LPTMR_RD_CSR_TIE(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TIE_MASK) >> LPTMR_CSR_TIE_SHIFT)
+#define LPTMR_BRD_CSR_TIE(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define LPTMR_WR_CSR_TIE(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TIE_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TIE(value)))
+#define LPTMR_BWR_CSR_TIE(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TCF[7] (W1C)
+ *
+ * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
+ * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
+ *
+ * Values:
+ * - 0b0 - The value of CNR is not equal to CMR and increments.
+ * - 0b1 - The value of CNR is equal to CMR and increments.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TCF field. */
+#define LPTMR_RD_CSR_TCF(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TCF_MASK) >> LPTMR_CSR_TCF_SHIFT)
+#define LPTMR_BRD_CSR_TCF(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT))
+
+/*! @brief Set the TCF field to a new value. */
+#define LPTMR_WR_CSR_TCF(base, value) (LPTMR_RMW_CSR(base, LPTMR_CSR_TCF_MASK, LPTMR_CSR_TCF(value)))
+#define LPTMR_BWR_CSR_TCF(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_PSR - Low Power Timer Prescale Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_PSR - Low Power Timer Prescale Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_PSR register
+ */
+/*@{*/
+#define LPTMR_RD_PSR(base)       (LPTMR_PSR_REG(base))
+#define LPTMR_WR_PSR(base, value) (LPTMR_PSR_REG(base) = (value))
+#define LPTMR_RMW_PSR(base, mask, value) (LPTMR_WR_PSR(base, (LPTMR_RD_PSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) |  (value)))
+#define LPTMR_CLR_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) & ~(value)))
+#define LPTMR_TOG_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_PSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_PSR, field PCS[1:0] (RW)
+ *
+ * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
+ * be altered only when the LPTMR is disabled. The clock connections vary by
+ * device. See the chip configuration details for information on the connections to
+ * these inputs.
+ *
+ * Values:
+ * - 0b00 - Prescaler/glitch filter clock 0 selected.
+ * - 0b01 - Prescaler/glitch filter clock 1 selected.
+ * - 0b10 - Prescaler/glitch filter clock 2 selected.
+ * - 0b11 - Prescaler/glitch filter clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PCS field. */
+#define LPTMR_RD_PSR_PCS(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PCS_MASK) >> LPTMR_PSR_PCS_SHIFT)
+#define LPTMR_BRD_PSR_PCS(base) (LPTMR_RD_PSR_PCS(base))
+
+/*! @brief Set the PCS field to a new value. */
+#define LPTMR_WR_PSR_PCS(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PCS_MASK, LPTMR_PSR_PCS(value)))
+#define LPTMR_BWR_PSR_PCS(base, value) (LPTMR_WR_PSR_PCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PBYP[2] (RW)
+ *
+ * When PBYP is set, the selected prescaler clock in Time Counter mode or
+ * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
+ * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
+ * must be altered only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - Prescaler/glitch filter is enabled.
+ * - 0b1 - Prescaler/glitch filter is bypassed.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PBYP field. */
+#define LPTMR_RD_PSR_PBYP(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PBYP_MASK) >> LPTMR_PSR_PBYP_SHIFT)
+#define LPTMR_BRD_PSR_PBYP(base) (BITBAND_ACCESS32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT))
+
+/*! @brief Set the PBYP field to a new value. */
+#define LPTMR_WR_PSR_PBYP(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PBYP_MASK, LPTMR_PSR_PBYP(value)))
+#define LPTMR_BWR_PSR_PBYP(base, value) (BITBAND_ACCESS32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
+ *
+ * Configures the size of the Prescaler in Time Counter mode or width of the
+ * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
+ * is disabled.
+ *
+ * Values:
+ * - 0b0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
+ *     support this configuration.
+ * - 0b0001 - Prescaler divides the prescaler clock by 4; glitch filter
+ *     recognizes change on input pin after 2 rising clock edges.
+ * - 0b0010 - Prescaler divides the prescaler clock by 8; glitch filter
+ *     recognizes change on input pin after 4 rising clock edges.
+ * - 0b0011 - Prescaler divides the prescaler clock by 16; glitch filter
+ *     recognizes change on input pin after 8 rising clock edges.
+ * - 0b0100 - Prescaler divides the prescaler clock by 32; glitch filter
+ *     recognizes change on input pin after 16 rising clock edges.
+ * - 0b0101 - Prescaler divides the prescaler clock by 64; glitch filter
+ *     recognizes change on input pin after 32 rising clock edges.
+ * - 0b0110 - Prescaler divides the prescaler clock by 128; glitch filter
+ *     recognizes change on input pin after 64 rising clock edges.
+ * - 0b0111 - Prescaler divides the prescaler clock by 256; glitch filter
+ *     recognizes change on input pin after 128 rising clock edges.
+ * - 0b1000 - Prescaler divides the prescaler clock by 512; glitch filter
+ *     recognizes change on input pin after 256 rising clock edges.
+ * - 0b1001 - Prescaler divides the prescaler clock by 1024; glitch filter
+ *     recognizes change on input pin after 512 rising clock edges.
+ * - 0b1010 - Prescaler divides the prescaler clock by 2048; glitch filter
+ *     recognizes change on input pin after 1024 rising clock edges.
+ * - 0b1011 - Prescaler divides the prescaler clock by 4096; glitch filter
+ *     recognizes change on input pin after 2048 rising clock edges.
+ * - 0b1100 - Prescaler divides the prescaler clock by 8192; glitch filter
+ *     recognizes change on input pin after 4096 rising clock edges.
+ * - 0b1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
+ *     recognizes change on input pin after 8192 rising clock edges.
+ * - 0b1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
+ *     recognizes change on input pin after 16,384 rising clock edges.
+ * - 0b1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
+ *     recognizes change on input pin after 32,768 rising clock edges.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
+#define LPTMR_RD_PSR_PRESCALE(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PRESCALE_MASK) >> LPTMR_PSR_PRESCALE_SHIFT)
+#define LPTMR_BRD_PSR_PRESCALE(base) (LPTMR_RD_PSR_PRESCALE(base))
+
+/*! @brief Set the PRESCALE field to a new value. */
+#define LPTMR_WR_PSR_PRESCALE(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PRESCALE_MASK, LPTMR_PSR_PRESCALE(value)))
+#define LPTMR_BWR_PSR_PRESCALE(base, value) (LPTMR_WR_PSR_PRESCALE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CMR - Low Power Timer Compare Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CMR - Low Power Timer Compare Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CMR register
+ */
+/*@{*/
+#define LPTMR_RD_CMR(base)       (LPTMR_CMR_REG(base))
+#define LPTMR_WR_CMR(base, value) (LPTMR_CMR_REG(base) = (value))
+#define LPTMR_RMW_CMR(base, mask, value) (LPTMR_WR_CMR(base, (LPTMR_RD_CMR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) |  (value)))
+#define LPTMR_CLR_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) & ~(value)))
+#define LPTMR_TOG_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CMR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
+ *
+ * When the LPTMR is enabled and the CNR equals the value in the CMR and
+ * increments, TCF is set and the hardware trigger asserts until the next time the CNR
+ * increments. If the CMR is 0, the hardware trigger will remain asserted until
+ * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
+ * when TCF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
+#define LPTMR_RD_CMR_COMPARE(base) ((LPTMR_CMR_REG(base) & LPTMR_CMR_COMPARE_MASK) >> LPTMR_CMR_COMPARE_SHIFT)
+#define LPTMR_BRD_CMR_COMPARE(base) (LPTMR_RD_CMR_COMPARE(base))
+
+/*! @brief Set the COMPARE field to a new value. */
+#define LPTMR_WR_CMR_COMPARE(base, value) (LPTMR_RMW_CMR(base, LPTMR_CMR_COMPARE_MASK, LPTMR_CMR_COMPARE(value)))
+#define LPTMR_BWR_CMR_COMPARE(base, value) (LPTMR_WR_CMR_COMPARE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CNR - Low Power Timer Counter Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CNR - Low Power Timer Counter Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CNR register
+ */
+/*@{*/
+#define LPTMR_RD_CNR(base)       (LPTMR_CNR_REG(base))
+#define LPTMR_WR_CNR(base, value) (LPTMR_CNR_REG(base) = (value))
+#define LPTMR_RMW_CNR(base, mask, value) (LPTMR_WR_CNR(base, (LPTMR_RD_CNR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) |  (value)))
+#define LPTMR_CLR_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) & ~(value)))
+#define LPTMR_TOG_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CNR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
+#define LPTMR_RD_CNR_COUNTER(base) ((LPTMR_CNR_REG(base) & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT)
+#define LPTMR_BRD_CNR_COUNTER(base) (LPTMR_RD_CNR_COUNTER(base))
+
+/*! @brief Set the COUNTER field to a new value. */
+#define LPTMR_WR_CNR_COUNTER(base, value) (LPTMR_RMW_CNR(base, LPTMR_CNR_COUNTER_MASK, LPTMR_CNR_COUNTER(value)))
+#define LPTMR_BWR_CNR_COUNTER(base, value) (LPTMR_WR_CNR_COUNTER(base, value))
+/*@}*/
+
+/*
+ * MK64F12 MCG
+ *
+ * Multipurpose Clock Generator module
+ *
+ * Registers defined in this header file:
+ * - MCG_C1 - MCG Control 1 Register
+ * - MCG_C2 - MCG Control 2 Register
+ * - MCG_C3 - MCG Control 3 Register
+ * - MCG_C4 - MCG Control 4 Register
+ * - MCG_C5 - MCG Control 5 Register
+ * - MCG_C6 - MCG Control 6 Register
+ * - MCG_S - MCG Status Register
+ * - MCG_SC - MCG Status and Control Register
+ * - MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ * - MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ * - MCG_C7 - MCG Control 7 Register
+ * - MCG_C8 - MCG Control 8 Register
+ */
+
+#define MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */
+#define MCG_IDX (0U) /*!< Instance number for MCG. */
+
+/*******************************************************************************
+ * MCG_C1 - MCG Control 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C1 - MCG Control 1 Register (RW)
+ *
+ * Reset value: 0x04U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C1 register
+ */
+/*@{*/
+#define MCG_RD_C1(base)          (MCG_C1_REG(base))
+#define MCG_WR_C1(base, value)   (MCG_C1_REG(base) = (value))
+#define MCG_RMW_C1(base, mask, value) (MCG_WR_C1(base, (MCG_RD_C1(base) & ~(mask)) | (value)))
+#define MCG_SET_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) |  (value)))
+#define MCG_CLR_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) & ~(value)))
+#define MCG_TOG_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C1 bitfields
+ */
+
+/*!
+ * @name Register MCG_C1, field IREFSTEN[0] (RW)
+ *
+ * Controls whether or not the internal reference clock remains enabled when the
+ * MCG enters Stop mode.
+ *
+ * Values:
+ * - 0b0 - Internal reference clock is disabled in Stop mode.
+ * - 0b1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
+ *     if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFSTEN field. */
+#define MCG_RD_C1_IREFSTEN(base) ((MCG_C1_REG(base) & MCG_C1_IREFSTEN_MASK) >> MCG_C1_IREFSTEN_SHIFT)
+#define MCG_BRD_C1_IREFSTEN(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT))
+
+/*! @brief Set the IREFSTEN field to a new value. */
+#define MCG_WR_C1_IREFSTEN(base, value) (MCG_RMW_C1(base, MCG_C1_IREFSTEN_MASK, MCG_C1_IREFSTEN(value)))
+#define MCG_BWR_C1_IREFSTEN(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IRCLKEN[1] (RW)
+ *
+ * Enables the internal reference clock for use as MCGIRCLK.
+ *
+ * Values:
+ * - 0b0 - MCGIRCLK inactive.
+ * - 0b1 - MCGIRCLK active.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IRCLKEN field. */
+#define MCG_RD_C1_IRCLKEN(base) ((MCG_C1_REG(base) & MCG_C1_IRCLKEN_MASK) >> MCG_C1_IRCLKEN_SHIFT)
+#define MCG_BRD_C1_IRCLKEN(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT))
+
+/*! @brief Set the IRCLKEN field to a new value. */
+#define MCG_WR_C1_IRCLKEN(base, value) (MCG_RMW_C1(base, MCG_C1_IRCLKEN_MASK, MCG_C1_IRCLKEN(value)))
+#define MCG_BWR_C1_IRCLKEN(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IREFS[2] (RW)
+ *
+ * Selects the reference clock source for the FLL.
+ *
+ * Values:
+ * - 0b0 - External reference clock is selected.
+ * - 0b1 - The slow internal reference clock is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFS field. */
+#define MCG_RD_C1_IREFS(base) ((MCG_C1_REG(base) & MCG_C1_IREFS_MASK) >> MCG_C1_IREFS_SHIFT)
+#define MCG_BRD_C1_IREFS(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT))
+
+/*! @brief Set the IREFS field to a new value. */
+#define MCG_WR_C1_IREFS(base, value) (MCG_RMW_C1(base, MCG_C1_IREFS_MASK, MCG_C1_IREFS(value)))
+#define MCG_BWR_C1_IREFS(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field FRDIV[5:3] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the FLL.
+ * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
+ * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
+ * not required to meet this range, but it is recommended in the cases when trying
+ * to enter a FLL mode from FBE).
+ *
+ * Values:
+ * - 0b000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
+ *     values, Divide Factor is 32.
+ * - 0b001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
+ *     values, Divide Factor is 64.
+ * - 0b010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
+ *     values, Divide Factor is 128.
+ * - 0b011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
+ *     values, Divide Factor is 256.
+ * - 0b100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
+ *     values, Divide Factor is 512.
+ * - 0b101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
+ *     values, Divide Factor is 1024.
+ * - 0b110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
+ *     values, Divide Factor is 1280 .
+ * - 0b111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other
+ *     RANGE values, Divide Factor is 1536 .
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_FRDIV field. */
+#define MCG_RD_C1_FRDIV(base) ((MCG_C1_REG(base) & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
+#define MCG_BRD_C1_FRDIV(base) (MCG_RD_C1_FRDIV(base))
+
+/*! @brief Set the FRDIV field to a new value. */
+#define MCG_WR_C1_FRDIV(base, value) (MCG_RMW_C1(base, MCG_C1_FRDIV_MASK, MCG_C1_FRDIV(value)))
+#define MCG_BWR_C1_FRDIV(base, value) (MCG_WR_C1_FRDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field CLKS[7:6] (RW)
+ *
+ * Selects the clock source for MCGOUTCLK .
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS
+ *     control bit).
+ * - 0b01 - Encoding 1 - Internal reference clock is selected.
+ * - 0b10 - Encoding 2 - External reference clock is selected.
+ * - 0b11 - Encoding 3 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_CLKS field. */
+#define MCG_RD_C1_CLKS(base) ((MCG_C1_REG(base) & MCG_C1_CLKS_MASK) >> MCG_C1_CLKS_SHIFT)
+#define MCG_BRD_C1_CLKS(base) (MCG_RD_C1_CLKS(base))
+
+/*! @brief Set the CLKS field to a new value. */
+#define MCG_WR_C1_CLKS(base, value) (MCG_RMW_C1(base, MCG_C1_CLKS_MASK, MCG_C1_CLKS(value)))
+#define MCG_BWR_C1_CLKS(base, value) (MCG_WR_C1_CLKS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C2 - MCG Control 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C2 - MCG Control 2 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C2 register
+ */
+/*@{*/
+#define MCG_RD_C2(base)          (MCG_C2_REG(base))
+#define MCG_WR_C2(base, value)   (MCG_C2_REG(base) = (value))
+#define MCG_RMW_C2(base, mask, value) (MCG_WR_C2(base, (MCG_RD_C2(base) & ~(mask)) | (value)))
+#define MCG_SET_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) |  (value)))
+#define MCG_CLR_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) & ~(value)))
+#define MCG_TOG_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C2 bitfields
+ */
+
+/*!
+ * @name Register MCG_C2, field IRCS[0] (RW)
+ *
+ * Selects between the fast or slow internal reference clock source.
+ *
+ * Values:
+ * - 0b0 - Slow internal reference clock selected.
+ * - 0b1 - Fast internal reference clock selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_IRCS field. */
+#define MCG_RD_C2_IRCS(base) ((MCG_C2_REG(base) & MCG_C2_IRCS_MASK) >> MCG_C2_IRCS_SHIFT)
+#define MCG_BRD_C2_IRCS(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT))
+
+/*! @brief Set the IRCS field to a new value. */
+#define MCG_WR_C2_IRCS(base, value) (MCG_RMW_C2(base, MCG_C2_IRCS_MASK, MCG_C2_IRCS(value)))
+#define MCG_BWR_C2_IRCS(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field LP[1] (RW)
+ *
+ * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
+ * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
+ * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
+ * other MCG mode, LP bit has no affect.
+ *
+ * Values:
+ * - 0b0 - FLL or PLL is not disabled in bypass modes.
+ * - 0b1 - FLL or PLL is disabled in bypass modes (lower power)
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_LP field. */
+#define MCG_RD_C2_LP(base)   ((MCG_C2_REG(base) & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
+#define MCG_BRD_C2_LP(base)  (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT))
+
+/*! @brief Set the LP field to a new value. */
+#define MCG_WR_C2_LP(base, value) (MCG_RMW_C2(base, MCG_C2_LP_MASK, MCG_C2_LP(value)))
+#define MCG_BWR_C2_LP(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field EREFS[2] (RW)
+ *
+ * Selects the source for the external reference clock. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0b0 - External reference clock requested.
+ * - 0b1 - Oscillator requested.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_EREFS field. */
+#define MCG_RD_C2_EREFS(base) ((MCG_C2_REG(base) & MCG_C2_EREFS_MASK) >> MCG_C2_EREFS_SHIFT)
+#define MCG_BRD_C2_EREFS(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT))
+
+/*! @brief Set the EREFS field to a new value. */
+#define MCG_WR_C2_EREFS(base, value) (MCG_RMW_C2(base, MCG_C2_EREFS_MASK, MCG_C2_EREFS(value)))
+#define MCG_BWR_C2_EREFS(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field HGO[3] (RW)
+ *
+ * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0b0 - Configure crystal oscillator for low-power operation.
+ * - 0b1 - Configure crystal oscillator for high-gain operation.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_HGO field. */
+#define MCG_RD_C2_HGO(base)  ((MCG_C2_REG(base) & MCG_C2_HGO_MASK) >> MCG_C2_HGO_SHIFT)
+#define MCG_BRD_C2_HGO(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT))
+
+/*! @brief Set the HGO field to a new value. */
+#define MCG_WR_C2_HGO(base, value) (MCG_RMW_C2(base, MCG_C2_HGO_MASK, MCG_C2_HGO(value)))
+#define MCG_BWR_C2_HGO(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field RANGE[5:4] (RW)
+ *
+ * Selects the frequency range for the crystal oscillator or external clock
+ * source. See the Oscillator (OSC) chapter for more details and the device data
+ * sheet for the frequency ranges used.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Low frequency range selected for the crystal oscillator
+ *     .
+ * - 0b01 - Encoding 1 - High frequency range selected for the crystal
+ *     oscillator .
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_RANGE field. */
+#define MCG_RD_C2_RANGE(base) ((MCG_C2_REG(base) & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
+#define MCG_BRD_C2_RANGE(base) (MCG_RD_C2_RANGE(base))
+
+/*! @brief Set the RANGE field to a new value. */
+#define MCG_WR_C2_RANGE(base, value) (MCG_RMW_C2(base, MCG_C2_RANGE_MASK, MCG_C2_RANGE(value)))
+#define MCG_BWR_C2_RANGE(base, value) (MCG_WR_C2_RANGE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field FCFTRIM[6] (RW)
+ *
+ * FCFTRIM controls the smallest adjustment of the fast internal reference clock
+ * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
+ * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_FCFTRIM field. */
+#define MCG_RD_C2_FCFTRIM(base) ((MCG_C2_REG(base) & MCG_C2_FCFTRIM_MASK) >> MCG_C2_FCFTRIM_SHIFT)
+#define MCG_BRD_C2_FCFTRIM(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT))
+
+/*! @brief Set the FCFTRIM field to a new value. */
+#define MCG_WR_C2_FCFTRIM(base, value) (MCG_RMW_C2(base, MCG_C2_FCFTRIM_MASK, MCG_C2_FCFTRIM(value)))
+#define MCG_BWR_C2_FCFTRIM(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field LOCRE0[7] (RW)
+ *
+ * Determines whether an interrupt or a reset request is made following a loss
+ * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
+ * set.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a loss of OSC0 external reference
+ *     clock.
+ * - 0b1 - Generate a reset request on a loss of OSC0 external reference clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_LOCRE0 field. */
+#define MCG_RD_C2_LOCRE0(base) ((MCG_C2_REG(base) & MCG_C2_LOCRE0_MASK) >> MCG_C2_LOCRE0_SHIFT)
+#define MCG_BRD_C2_LOCRE0(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT))
+
+/*! @brief Set the LOCRE0 field to a new value. */
+#define MCG_WR_C2_LOCRE0(base, value) (MCG_RMW_C2(base, MCG_C2_LOCRE0_MASK, MCG_C2_LOCRE0(value)))
+#define MCG_BWR_C2_LOCRE0(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C3 - MCG Control 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C3 - MCG Control 3 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C3 register
+ */
+/*@{*/
+#define MCG_RD_C3(base)          (MCG_C3_REG(base))
+#define MCG_WR_C3(base, value)   (MCG_C3_REG(base) = (value))
+#define MCG_RMW_C3(base, mask, value) (MCG_WR_C3(base, (MCG_RD_C3(base) & ~(mask)) | (value)))
+#define MCG_SET_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) |  (value)))
+#define MCG_CLR_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) & ~(value)))
+#define MCG_TOG_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C4 - MCG Control 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C4 - MCG Control 4 Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Reset values for DRST and DMX32 bits are 0.
+ */
+/*!
+ * @name Constants and macros for entire MCG_C4 register
+ */
+/*@{*/
+#define MCG_RD_C4(base)          (MCG_C4_REG(base))
+#define MCG_WR_C4(base, value)   (MCG_C4_REG(base) = (value))
+#define MCG_RMW_C4(base, mask, value) (MCG_WR_C4(base, (MCG_RD_C4(base) & ~(mask)) | (value)))
+#define MCG_SET_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) |  (value)))
+#define MCG_CLR_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) & ~(value)))
+#define MCG_TOG_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C4 bitfields
+ */
+
+/*!
+ * @name Register MCG_C4, field SCFTRIM[0] (RW)
+ *
+ * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
+ * location . controls the smallest adjustment of the slow internal reference
+ * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
+ * decreases the period by the smallest amount possible. If an SCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_SCFTRIM field. */
+#define MCG_RD_C4_SCFTRIM(base) ((MCG_C4_REG(base) & MCG_C4_SCFTRIM_MASK) >> MCG_C4_SCFTRIM_SHIFT)
+#define MCG_BRD_C4_SCFTRIM(base) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT))
+
+/*! @brief Set the SCFTRIM field to a new value. */
+#define MCG_WR_C4_SCFTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_SCFTRIM_MASK, MCG_C4_SCFTRIM(value)))
+#define MCG_BWR_C4_SCFTRIM(base, value) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field FCTRIM[4:1] (RW)
+ *
+ * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
+ * location. controls the fast internal reference clock frequency by controlling
+ * the fast internal reference clock period. The FCTRIM bits are binary weighted,
+ * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
+ * increases the period, and decreasing the value decreases the period. If an
+ * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
+ * responsibility to copy that value from the nonvolatile memory location to this register.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_FCTRIM field. */
+#define MCG_RD_C4_FCTRIM(base) ((MCG_C4_REG(base) & MCG_C4_FCTRIM_MASK) >> MCG_C4_FCTRIM_SHIFT)
+#define MCG_BRD_C4_FCTRIM(base) (MCG_RD_C4_FCTRIM(base))
+
+/*! @brief Set the FCTRIM field to a new value. */
+#define MCG_WR_C4_FCTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_FCTRIM_MASK, MCG_C4_FCTRIM(value)))
+#define MCG_BWR_C4_FCTRIM(base, value) (MCG_WR_C4_FCTRIM(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
+ *
+ * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
+ * LP bit is set, writes to the DRS bits are ignored. The DRST read field
+ * indicates the current frequency range for DCOOUT. The DRST field does not update
+ * immediately after a write to the DRS field due to internal synchronization between
+ * clock domains. See the DCO Frequency Range table for more details.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Low range (reset default).
+ * - 0b01 - Encoding 1 - Mid range.
+ * - 0b10 - Encoding 2 - Mid-high range.
+ * - 0b11 - Encoding 3 - High range.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_DRST_DRS field. */
+#define MCG_RD_C4_DRST_DRS(base) ((MCG_C4_REG(base) & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
+#define MCG_BRD_C4_DRST_DRS(base) (MCG_RD_C4_DRST_DRS(base))
+
+/*! @brief Set the DRST_DRS field to a new value. */
+#define MCG_WR_C4_DRST_DRS(base, value) (MCG_RMW_C4(base, MCG_C4_DRST_DRS_MASK, MCG_C4_DRST_DRS(value)))
+#define MCG_BWR_C4_DRST_DRS(base, value) (MCG_WR_C4_DRST_DRS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field DMX32[7] (RW)
+ *
+ * The DMX32 bit controls whether the DCO frequency range is narrowed to its
+ * maximum frequency with a 32.768 kHz reference. The following table identifies
+ * settings for the DCO frequency range. The system clocks derived from this source
+ * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
+ * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
+ * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
+ * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
+ * 80-100 MHz 1 32.768 kHz 2929 96 MHz
+ *
+ * Values:
+ * - 0b0 - DCO has a default range of 25%.
+ * - 0b1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_DMX32 field. */
+#define MCG_RD_C4_DMX32(base) ((MCG_C4_REG(base) & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
+#define MCG_BRD_C4_DMX32(base) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT))
+
+/*! @brief Set the DMX32 field to a new value. */
+#define MCG_WR_C4_DMX32(base, value) (MCG_RMW_C4(base, MCG_C4_DMX32_MASK, MCG_C4_DMX32(value)))
+#define MCG_BWR_C4_DMX32(base, value) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C5 - MCG Control 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C5 - MCG Control 5 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C5 register
+ */
+/*@{*/
+#define MCG_RD_C5(base)          (MCG_C5_REG(base))
+#define MCG_WR_C5(base, value)   (MCG_C5_REG(base) = (value))
+#define MCG_RMW_C5(base, mask, value) (MCG_WR_C5(base, (MCG_RD_C5(base) & ~(mask)) | (value)))
+#define MCG_SET_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) |  (value)))
+#define MCG_CLR_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) & ~(value)))
+#define MCG_TOG_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C5 bitfields
+ */
+
+/*!
+ * @name Register MCG_C5, field PRDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the PLL.
+ * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
+ * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
+ * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
+ * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
+ * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
+ * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
+ * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
+ * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
+ * Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PRDIV0 field. */
+#define MCG_RD_C5_PRDIV0(base) ((MCG_C5_REG(base) & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
+#define MCG_BRD_C5_PRDIV0(base) (MCG_RD_C5_PRDIV0(base))
+
+/*! @brief Set the PRDIV0 field to a new value. */
+#define MCG_WR_C5_PRDIV0(base, value) (MCG_RMW_C5(base, MCG_C5_PRDIV0_MASK, MCG_C5_PRDIV0(value)))
+#define MCG_BWR_C5_PRDIV0(base, value) (MCG_WR_C5_PRDIV0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C5, field PLLSTEN0[5] (RW)
+ *
+ * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
+ * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
+ * has no affect and does not enable the PLL Clock to run if it is written to 1.
+ *
+ * Values:
+ * - 0b0 - MCGPLLCLK is disabled in any of the Stop modes.
+ * - 0b1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */
+#define MCG_RD_C5_PLLSTEN0(base) ((MCG_C5_REG(base) & MCG_C5_PLLSTEN0_MASK) >> MCG_C5_PLLSTEN0_SHIFT)
+#define MCG_BRD_C5_PLLSTEN0(base) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLSTEN0_SHIFT))
+
+/*! @brief Set the PLLSTEN0 field to a new value. */
+#define MCG_WR_C5_PLLSTEN0(base, value) (MCG_RMW_C5(base, MCG_C5_PLLSTEN0_MASK, MCG_C5_PLLSTEN0(value)))
+#define MCG_BWR_C5_PLLSTEN0(base, value) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLSTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C5, field PLLCLKEN0[6] (RW)
+ *
+ * Enables the PLL independent of PLLS and enables the PLL clock for use as
+ * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
+ * PLL reference clock in the range of 2 - 4 MHz range prior to setting the
+ * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
+ * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
+ * and the external oscillator is being used as the reference clock, the OSCINIT 0
+ * bit should be checked to make sure it is set.
+ *
+ * Values:
+ * - 0b0 - MCGPLLCLK is inactive.
+ * - 0b1 - MCGPLLCLK is active.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */
+#define MCG_RD_C5_PLLCLKEN0(base) ((MCG_C5_REG(base) & MCG_C5_PLLCLKEN0_MASK) >> MCG_C5_PLLCLKEN0_SHIFT)
+#define MCG_BRD_C5_PLLCLKEN0(base) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLCLKEN0_SHIFT))
+
+/*! @brief Set the PLLCLKEN0 field to a new value. */
+#define MCG_WR_C5_PLLCLKEN0(base, value) (MCG_RMW_C5(base, MCG_C5_PLLCLKEN0_MASK, MCG_C5_PLLCLKEN0(value)))
+#define MCG_BWR_C5_PLLCLKEN0(base, value) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLCLKEN0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C6 - MCG Control 6 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C6 - MCG Control 6 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C6 register
+ */
+/*@{*/
+#define MCG_RD_C6(base)          (MCG_C6_REG(base))
+#define MCG_WR_C6(base, value)   (MCG_C6_REG(base) = (value))
+#define MCG_RMW_C6(base, mask, value) (MCG_WR_C6(base, (MCG_RD_C6(base) & ~(mask)) | (value)))
+#define MCG_SET_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) |  (value)))
+#define MCG_CLR_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) & ~(value)))
+#define MCG_TOG_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C6 bitfields
+ */
+
+/*!
+ * @name Register MCG_C6, field VDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
+ * establish the multiplication factor (M) applied to the reference clock frequency.
+ * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
+ * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
+ * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
+ * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
+ * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
+ * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
+ * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_VDIV0 field. */
+#define MCG_RD_C6_VDIV0(base) ((MCG_C6_REG(base) & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
+#define MCG_BRD_C6_VDIV0(base) (MCG_RD_C6_VDIV0(base))
+
+/*! @brief Set the VDIV0 field to a new value. */
+#define MCG_WR_C6_VDIV0(base, value) (MCG_RMW_C6(base, MCG_C6_VDIV0_MASK, MCG_C6_VDIV0(value)))
+#define MCG_BWR_C6_VDIV0(base, value) (MCG_WR_C6_VDIV0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field CME0[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the OSC0 external reference
+ * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
+ * generated following a loss of OSC0 indication. The CME0 bit must only be set
+ * to a logic 1 when the MCG is in an operational mode that uses the external
+ * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
+ * the value of the RANGE0 bits in the C2 register should not be changed. CME0
+ * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur while in Stop mode. CME0 should also be set to a
+ * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
+ *
+ * Values:
+ * - 0b0 - External clock monitor is disabled for OSC0.
+ * - 0b1 - External clock monitor is enabled for OSC0.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_CME0 field. */
+#define MCG_RD_C6_CME0(base) ((MCG_C6_REG(base) & MCG_C6_CME0_MASK) >> MCG_C6_CME0_SHIFT)
+#define MCG_BRD_C6_CME0(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_CME0_SHIFT))
+
+/*! @brief Set the CME0 field to a new value. */
+#define MCG_WR_C6_CME0(base, value) (MCG_RMW_C6(base, MCG_C6_CME0_MASK, MCG_C6_CME0(value)))
+#define MCG_BWR_C6_CME0(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_CME0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field PLLS[6] (RW)
+ *
+ * Controls whether the PLL or FLL output is selected as the MCG source when
+ * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
+ * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
+ *
+ * Values:
+ * - 0b0 - FLL is selected.
+ * - 0b1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
+ *     to generate a PLL reference clock in the range of 2-4 MHz prior to
+ *     setting the PLLS bit).
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_PLLS field. */
+#define MCG_RD_C6_PLLS(base) ((MCG_C6_REG(base) & MCG_C6_PLLS_MASK) >> MCG_C6_PLLS_SHIFT)
+#define MCG_BRD_C6_PLLS(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_PLLS_SHIFT))
+
+/*! @brief Set the PLLS field to a new value. */
+#define MCG_WR_C6_PLLS(base, value) (MCG_RMW_C6(base, MCG_C6_PLLS_MASK, MCG_C6_PLLS(value)))
+#define MCG_BWR_C6_PLLS(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_PLLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field LOLIE0[7] (RW)
+ *
+ * Determines if an interrupt request is made following a loss of lock
+ * indication. This bit only has an effect when LOLS 0 is set.
+ *
+ * Values:
+ * - 0b0 - No interrupt request is generated on loss of lock.
+ * - 0b1 - Generate an interrupt request on loss of lock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_LOLIE0 field. */
+#define MCG_RD_C6_LOLIE0(base) ((MCG_C6_REG(base) & MCG_C6_LOLIE0_MASK) >> MCG_C6_LOLIE0_SHIFT)
+#define MCG_BRD_C6_LOLIE0(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_LOLIE0_SHIFT))
+
+/*! @brief Set the LOLIE0 field to a new value. */
+#define MCG_WR_C6_LOLIE0(base, value) (MCG_RMW_C6(base, MCG_C6_LOLIE0_MASK, MCG_C6_LOLIE0(value)))
+#define MCG_BWR_C6_LOLIE0(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_LOLIE0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_S - MCG Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_S - MCG Status Register (RW)
+ *
+ * Reset value: 0x10U
+ */
+/*!
+ * @name Constants and macros for entire MCG_S register
+ */
+/*@{*/
+#define MCG_RD_S(base)           (MCG_S_REG(base))
+#define MCG_WR_S(base, value)    (MCG_S_REG(base) = (value))
+#define MCG_RMW_S(base, mask, value) (MCG_WR_S(base, (MCG_RD_S(base) & ~(mask)) | (value)))
+#define MCG_SET_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) |  (value)))
+#define MCG_CLR_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) & ~(value)))
+#define MCG_TOG_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_S bitfields
+ */
+
+/*!
+ * @name Register MCG_S, field IRCST[0] (RO)
+ *
+ * The IRCST bit indicates the current source for the internal reference clock
+ * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
+ * to the IRCS bit due to internal synchronization between clock domains. The
+ * IRCST bit will only be updated if the internal reference clock is enabled,
+ * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
+ * bit .
+ *
+ * Values:
+ * - 0b0 - Source of internal reference clock is the slow clock (32 kHz IRC).
+ * - 0b1 - Source of internal reference clock is the fast clock (4 MHz IRC).
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_IRCST field. */
+#define MCG_RD_S_IRCST(base) ((MCG_S_REG(base) & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT)
+#define MCG_BRD_S_IRCST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_IRCST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field OSCINIT0[1] (RO)
+ *
+ * This bit, which resets to 0, is set to 1 after the initialization cycles of
+ * the crystal oscillator clock have completed. After being set, the bit is
+ * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
+ * description for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_OSCINIT0 field. */
+#define MCG_RD_S_OSCINIT0(base) ((MCG_S_REG(base) & MCG_S_OSCINIT0_MASK) >> MCG_S_OSCINIT0_SHIFT)
+#define MCG_BRD_S_OSCINIT0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_OSCINIT0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field CLKST[3:2] (RO)
+ *
+ * These bits indicate the current clock mode. The CLKST bits do not update
+ * immediately after a write to the CLKS bits due to internal synchronization between
+ * clock domains.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Output of the FLL is selected (reset default).
+ * - 0b01 - Encoding 1 - Internal reference clock is selected.
+ * - 0b10 - Encoding 2 - External reference clock is selected.
+ * - 0b11 - Encoding 3 - Output of the PLL is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_CLKST field. */
+#define MCG_RD_S_CLKST(base) ((MCG_S_REG(base) & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
+#define MCG_BRD_S_CLKST(base) (MCG_RD_S_CLKST(base))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field IREFST[4] (RO)
+ *
+ * This bit indicates the current source for the FLL reference clock. The IREFST
+ * bit does not update immediately after a write to the IREFS bit due to
+ * internal synchronization between clock domains.
+ *
+ * Values:
+ * - 0b0 - Source of FLL reference clock is the external reference clock.
+ * - 0b1 - Source of FLL reference clock is the internal reference clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_IREFST field. */
+#define MCG_RD_S_IREFST(base) ((MCG_S_REG(base) & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
+#define MCG_BRD_S_IREFST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_IREFST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field PLLST[5] (RO)
+ *
+ * This bit indicates the clock source selected by PLLS . The PLLST bit does not
+ * update immediately after a write to the PLLS bit due to internal
+ * synchronization between clock domains.
+ *
+ * Values:
+ * - 0b0 - Source of PLLS clock is FLL clock.
+ * - 0b1 - Source of PLLS clock is PLL output clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_PLLST field. */
+#define MCG_RD_S_PLLST(base) ((MCG_S_REG(base) & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT)
+#define MCG_BRD_S_PLLST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_PLLST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field LOCK0[6] (RO)
+ *
+ * This bit indicates whether the PLL has acquired lock. Lock detection is only
+ * enabled when the PLL is enabled (either through clock mode selection or
+ * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
+ * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
+ * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
+ * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
+ * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
+ * reference clock will also cause the LOCK0 bit to clear until the PLL has
+ * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
+ * the lock status bit to clear and stay cleared until the Stop mode is exited
+ * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
+ * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
+ * again.
+ *
+ * Values:
+ * - 0b0 - PLL is currently unlocked.
+ * - 0b1 - PLL is currently locked.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_LOCK0 field. */
+#define MCG_RD_S_LOCK0(base) ((MCG_S_REG(base) & MCG_S_LOCK0_MASK) >> MCG_S_LOCK0_SHIFT)
+#define MCG_BRD_S_LOCK0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOCK0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field LOLS0[7] (W1C)
+ *
+ * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
+ * if after acquiring lock, the PLL output frequency has fallen outside the lock
+ * exit frequency tolerance, D unl . LOLIE determines whether an interrupt
+ * request is made when LOLS is set. LOLRE determines whether a reset request is made
+ * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
+ * when set. Writing a logic 0 to this bit has no effect.
+ *
+ * Values:
+ * - 0b0 - PLL has not lost lock since LOLS 0 was last cleared.
+ * - 0b1 - PLL has lost lock since LOLS 0 was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_LOLS0 field. */
+#define MCG_RD_S_LOLS0(base) ((MCG_S_REG(base) & MCG_S_LOLS0_MASK) >> MCG_S_LOLS0_SHIFT)
+#define MCG_BRD_S_LOLS0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOLS0_SHIFT))
+
+/*! @brief Set the LOLS0 field to a new value. */
+#define MCG_WR_S_LOLS0(base, value) (MCG_RMW_S(base, MCG_S_LOLS0_MASK, MCG_S_LOLS0(value)))
+#define MCG_BWR_S_LOLS0(base, value) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOLS0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_SC - MCG Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_SC - MCG Status and Control Register (RW)
+ *
+ * Reset value: 0x02U
+ */
+/*!
+ * @name Constants and macros for entire MCG_SC register
+ */
+/*@{*/
+#define MCG_RD_SC(base)          (MCG_SC_REG(base))
+#define MCG_WR_SC(base, value)   (MCG_SC_REG(base) = (value))
+#define MCG_RMW_SC(base, mask, value) (MCG_WR_SC(base, (MCG_RD_SC(base) & ~(mask)) | (value)))
+#define MCG_SET_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) |  (value)))
+#define MCG_CLR_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) & ~(value)))
+#define MCG_TOG_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_SC bitfields
+ */
+
+/*!
+ * @name Register MCG_SC, field LOCS0[0] (W1C)
+ *
+ * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
+ * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
+ * logic 1 to it when set.
+ *
+ * Values:
+ * - 0b0 - Loss of OSC0 has not occurred.
+ * - 0b1 - Loss of OSC0 has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_LOCS0 field. */
+#define MCG_RD_SC_LOCS0(base) ((MCG_SC_REG(base) & MCG_SC_LOCS0_MASK) >> MCG_SC_LOCS0_SHIFT)
+#define MCG_BRD_SC_LOCS0(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT))
+
+/*! @brief Set the LOCS0 field to a new value. */
+#define MCG_WR_SC_LOCS0(base, value) (MCG_RMW_SC(base, MCG_SC_LOCS0_MASK, MCG_SC_LOCS0(value)))
+#define MCG_BWR_SC_LOCS0(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field FCRDIV[3:1] (RW)
+ *
+ * Selects the amount to divide down the fast internal reference clock. The
+ * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
+ * divider when the Fast IRC is enabled is not supported).
+ *
+ * Values:
+ * - 0b000 - Divide Factor is 1
+ * - 0b001 - Divide Factor is 2.
+ * - 0b010 - Divide Factor is 4.
+ * - 0b011 - Divide Factor is 8.
+ * - 0b100 - Divide Factor is 16
+ * - 0b101 - Divide Factor is 32
+ * - 0b110 - Divide Factor is 64
+ * - 0b111 - Divide Factor is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FCRDIV field. */
+#define MCG_RD_SC_FCRDIV(base) ((MCG_SC_REG(base) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
+#define MCG_BRD_SC_FCRDIV(base) (MCG_RD_SC_FCRDIV(base))
+
+/*! @brief Set the FCRDIV field to a new value. */
+#define MCG_WR_SC_FCRDIV(base, value) (MCG_RMW_SC(base, (MCG_SC_FCRDIV_MASK | MCG_SC_LOCS0_MASK), MCG_SC_FCRDIV(value)))
+#define MCG_BWR_SC_FCRDIV(base, value) (MCG_WR_SC_FCRDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field FLTPRSRV[4] (RW)
+ *
+ * This bit will prevent the FLL filter values from resetting allowing the FLL
+ * output frequency to remain the same during clock mode changes where the FLL/DCO
+ * output is still valid. (Note: This requires that the FLL reference frequency
+ * to remain the same as what it was prior to the new clock mode switch.
+ * Otherwise FLL filter and frequency values will change.)
+ *
+ * Values:
+ * - 0b0 - FLL filter and FLL frequency will reset on changes to currect clock
+ *     mode.
+ * - 0b1 - Fll filter and FLL frequency retain their previous values during new
+ *     clock mode change.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FLTPRSRV field. */
+#define MCG_RD_SC_FLTPRSRV(base) ((MCG_SC_REG(base) & MCG_SC_FLTPRSRV_MASK) >> MCG_SC_FLTPRSRV_SHIFT)
+#define MCG_BRD_SC_FLTPRSRV(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT))
+
+/*! @brief Set the FLTPRSRV field to a new value. */
+#define MCG_WR_SC_FLTPRSRV(base, value) (MCG_RMW_SC(base, (MCG_SC_FLTPRSRV_MASK | MCG_SC_LOCS0_MASK), MCG_SC_FLTPRSRV(value)))
+#define MCG_BWR_SC_FLTPRSRV(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATMF[5] (RW)
+ *
+ * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
+ * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
+ * registers is detected or the MCG enters into any Stop mode. A write to ATMF
+ * clears the flag.
+ *
+ * Values:
+ * - 0b0 - Automatic Trim Machine completed normally.
+ * - 0b1 - Automatic Trim Machine failed.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATMF field. */
+#define MCG_RD_SC_ATMF(base) ((MCG_SC_REG(base) & MCG_SC_ATMF_MASK) >> MCG_SC_ATMF_SHIFT)
+#define MCG_BRD_SC_ATMF(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT))
+
+/*! @brief Set the ATMF field to a new value. */
+#define MCG_WR_SC_ATMF(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMF(value)))
+#define MCG_BWR_SC_ATMF(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATMS[6] (RW)
+ *
+ * Selects the IRCS clock for Auto Trim Test.
+ *
+ * Values:
+ * - 0b0 - 32 kHz Internal Reference Clock selected.
+ * - 0b1 - 4 MHz Internal Reference Clock selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATMS field. */
+#define MCG_RD_SC_ATMS(base) ((MCG_SC_REG(base) & MCG_SC_ATMS_MASK) >> MCG_SC_ATMS_SHIFT)
+#define MCG_BRD_SC_ATMS(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT))
+
+/*! @brief Set the ATMS field to a new value. */
+#define MCG_WR_SC_ATMS(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMS(value)))
+#define MCG_BWR_SC_ATMS(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATME[7] (RW)
+ *
+ * Enables the Auto Trim Machine to start automatically trimming the selected
+ * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
+ * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
+ * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
+ * operation and clears this bit.
+ *
+ * Values:
+ * - 0b0 - Auto Trim Machine disabled.
+ * - 0b1 - Auto Trim Machine enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATME field. */
+#define MCG_RD_SC_ATME(base) ((MCG_SC_REG(base) & MCG_SC_ATME_MASK) >> MCG_SC_ATME_SHIFT)
+#define MCG_BRD_SC_ATME(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT))
+
+/*! @brief Set the ATME field to a new value. */
+#define MCG_WR_SC_ATME(base, value) (MCG_RMW_SC(base, (MCG_SC_ATME_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATME(value)))
+#define MCG_BWR_SC_ATME(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_ATCVH register
+ */
+/*@{*/
+#define MCG_RD_ATCVH(base)       (MCG_ATCVH_REG(base))
+#define MCG_WR_ATCVH(base, value) (MCG_ATCVH_REG(base) = (value))
+#define MCG_RMW_ATCVH(base, mask, value) (MCG_WR_ATCVH(base, (MCG_RD_ATCVH(base) & ~(mask)) | (value)))
+#define MCG_SET_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) |  (value)))
+#define MCG_CLR_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) & ~(value)))
+#define MCG_TOG_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_ATCVL register
+ */
+/*@{*/
+#define MCG_RD_ATCVL(base)       (MCG_ATCVL_REG(base))
+#define MCG_WR_ATCVL(base, value) (MCG_ATCVL_REG(base) = (value))
+#define MCG_RMW_ATCVL(base, mask, value) (MCG_WR_ATCVL(base, (MCG_RD_ATCVL(base) & ~(mask)) | (value)))
+#define MCG_SET_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) |  (value)))
+#define MCG_CLR_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) & ~(value)))
+#define MCG_TOG_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C7 - MCG Control 7 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C7 - MCG Control 7 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C7 register
+ */
+/*@{*/
+#define MCG_RD_C7(base)          (MCG_C7_REG(base))
+#define MCG_WR_C7(base, value)   (MCG_C7_REG(base) = (value))
+#define MCG_RMW_C7(base, mask, value) (MCG_WR_C7(base, (MCG_RD_C7(base) & ~(mask)) | (value)))
+#define MCG_SET_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) |  (value)))
+#define MCG_CLR_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) & ~(value)))
+#define MCG_TOG_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C7 bitfields
+ */
+
+/*!
+ * @name Register MCG_C7, field OSCSEL[1:0] (RW)
+ *
+ * Selects the MCG FLL external reference clock
+ *
+ * Values:
+ * - 0b00 - Selects Oscillator (OSCCLK0).
+ * - 0b01 - Selects 32 kHz RTC Oscillator.
+ * - 0b10 - Selects Oscillator (OSCCLK1).
+ * - 0b11 - RESERVED
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C7_OSCSEL field. */
+#define MCG_RD_C7_OSCSEL(base) ((MCG_C7_REG(base) & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
+#define MCG_BRD_C7_OSCSEL(base) (MCG_RD_C7_OSCSEL(base))
+
+/*! @brief Set the OSCSEL field to a new value. */
+#define MCG_WR_C7_OSCSEL(base, value) (MCG_RMW_C7(base, MCG_C7_OSCSEL_MASK, MCG_C7_OSCSEL(value)))
+#define MCG_BWR_C7_OSCSEL(base, value) (MCG_WR_C7_OSCSEL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C8 - MCG Control 8 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C8 - MCG Control 8 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C8 register
+ */
+/*@{*/
+#define MCG_RD_C8(base)          (MCG_C8_REG(base))
+#define MCG_WR_C8(base, value)   (MCG_C8_REG(base) = (value))
+#define MCG_RMW_C8(base, mask, value) (MCG_WR_C8(base, (MCG_RD_C8(base) & ~(mask)) | (value)))
+#define MCG_SET_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) |  (value)))
+#define MCG_CLR_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) & ~(value)))
+#define MCG_TOG_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C8 bitfields
+ */
+
+/*!
+ * @name Register MCG_C8, field LOCS1[0] (W1C)
+ *
+ * This bit indicates when a loss of clock has occurred. This bit is cleared by
+ * writing a logic 1 to it when set.
+ *
+ * Values:
+ * - 0b0 - Loss of RTC has not occur.
+ * - 0b1 - Loss of RTC has occur
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOCS1 field. */
+#define MCG_RD_C8_LOCS1(base) ((MCG_C8_REG(base) & MCG_C8_LOCS1_MASK) >> MCG_C8_LOCS1_SHIFT)
+#define MCG_BRD_C8_LOCS1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT))
+
+/*! @brief Set the LOCS1 field to a new value. */
+#define MCG_WR_C8_LOCS1(base, value) (MCG_RMW_C8(base, MCG_C8_LOCS1_MASK, MCG_C8_LOCS1(value)))
+#define MCG_BWR_C8_LOCS1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field CME1[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the output of the RTC
+ * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
+ * reset request is generated following a loss of RTC clock indication. The CME1
+ * bit should be set to a logic 1 when the MCG is in an operational mode that uses
+ * the RTC as its external reference clock or if the RTC is operational. CME1 bit
+ * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
+ * before entering VLPR or VLPW power modes.
+ *
+ * Values:
+ * - 0b0 - External clock monitor is disabled for RTC clock.
+ * - 0b1 - External clock monitor is enabled for RTC clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_CME1 field. */
+#define MCG_RD_C8_CME1(base) ((MCG_C8_REG(base) & MCG_C8_CME1_MASK) >> MCG_C8_CME1_SHIFT)
+#define MCG_BRD_C8_CME1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT))
+
+/*! @brief Set the CME1 field to a new value. */
+#define MCG_WR_C8_CME1(base, value) (MCG_RMW_C8(base, (MCG_C8_CME1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_CME1(value)))
+#define MCG_BWR_C8_CME1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field LOLRE[6] (RW)
+ *
+ * Determines if an interrupt or a reset request is made following a PLL loss of
+ * lock.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a PLL loss of lock indication. The
+ *     PLL loss of lock interrupt enable bit must also be set to generate the
+ *     interrupt request.
+ * - 0b1 - Generate a reset request on a PLL loss of lock indication.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOLRE field. */
+#define MCG_RD_C8_LOLRE(base) ((MCG_C8_REG(base) & MCG_C8_LOLRE_MASK) >> MCG_C8_LOLRE_SHIFT)
+#define MCG_BRD_C8_LOLRE(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOLRE_SHIFT))
+
+/*! @brief Set the LOLRE field to a new value. */
+#define MCG_WR_C8_LOLRE(base, value) (MCG_RMW_C8(base, (MCG_C8_LOLRE_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOLRE(value)))
+#define MCG_BWR_C8_LOLRE(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOLRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field LOCRE1[7] (RW)
+ *
+ * Determines if a interrupt or a reset request is made following a loss of RTC
+ * external reference clock. The LOCRE1 only has an affect when CME1 is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a loss of RTC external reference
+ *     clock.
+ * - 0b1 - Generate a reset request on a loss of RTC external reference clock
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOCRE1 field. */
+#define MCG_RD_C8_LOCRE1(base) ((MCG_C8_REG(base) & MCG_C8_LOCRE1_MASK) >> MCG_C8_LOCRE1_SHIFT)
+#define MCG_BRD_C8_LOCRE1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT))
+
+/*! @brief Set the LOCRE1 field to a new value. */
+#define MCG_WR_C8_LOCRE1(base, value) (MCG_RMW_C8(base, (MCG_C8_LOCRE1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOCRE1(value)))
+#define MCG_BWR_C8_LOCRE1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 MCM
+ *
+ * Core Platform Miscellaneous Control Module
+ *
+ * Registers defined in this header file:
+ * - MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ * - MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ * - MCM_CR - Control Register
+ * - MCM_ISCR - Interrupt Status Register
+ * - MCM_ETBCC - ETB Counter Control register
+ * - MCM_ETBRL - ETB Reload register
+ * - MCM_ETBCNT - ETB Counter Value register
+ * - MCM_PID - Process ID register
+ */
+
+#define MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
+#define MCM_IDX (0U) /*!< Instance number for MCM. */
+
+/*******************************************************************************
+ * MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
+ *
+ * Reset value: 0x001FU
+ *
+ * PLASC is a 16-bit read-only register identifying the presence/absence of bus
+ * slave connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLASC register
+ */
+/*@{*/
+#define MCM_RD_PLASC(base)       (MCM_PLASC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLASC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLASC, field ASC[7:0] (RO)
+ *
+ * Values:
+ * - 0b00000000 - A bus slave connection to AXBS input port n is absent
+ * - 0b00000001 - A bus slave connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLASC_ASC field. */
+#define MCM_RD_PLASC_ASC(base) ((MCM_PLASC_REG(base) & MCM_PLASC_ASC_MASK) >> MCM_PLASC_ASC_SHIFT)
+#define MCM_BRD_PLASC_ASC(base) (MCM_RD_PLASC_ASC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
+ *
+ * Reset value: 0x0037U
+ *
+ * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
+ * master connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLAMC register
+ */
+/*@{*/
+#define MCM_RD_PLAMC(base)       (MCM_PLAMC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLAMC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLAMC, field AMC[7:0] (RO)
+ *
+ * Values:
+ * - 0b00000000 - A bus master connection to AXBS input port n is absent
+ * - 0b00000001 - A bus master connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLAMC_AMC field. */
+#define MCM_RD_PLAMC_AMC(base) ((MCM_PLAMC_REG(base) & MCM_PLAMC_AMC_MASK) >> MCM_PLAMC_AMC_SHIFT)
+#define MCM_BRD_PLAMC_AMC(base) (MCM_RD_PLAMC_AMC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_CR - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CR defines the arbitration and protection schemes for the two system RAM
+ * arrays.
+ */
+/*!
+ * @name Constants and macros for entire MCM_CR register
+ */
+/*@{*/
+#define MCM_RD_CR(base)          (MCM_CR_REG(base))
+#define MCM_WR_CR(base, value)   (MCM_CR_REG(base) = (value))
+#define MCM_RMW_CR(base, mask, value) (MCM_WR_CR(base, (MCM_RD_CR(base) & ~(mask)) | (value)))
+#define MCM_SET_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) |  (value)))
+#define MCM_CLR_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) & ~(value)))
+#define MCM_TOG_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_CR bitfields
+ */
+
+/*!
+ * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_U array.
+ *
+ * Values:
+ * - 0b00 - Round robin
+ * - 0b01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 0b10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 0b11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMUAP field. */
+#define MCM_RD_CR_SRAMUAP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMUAP_MASK) >> MCM_CR_SRAMUAP_SHIFT)
+#define MCM_BRD_CR_SRAMUAP(base) (MCM_RD_CR_SRAMUAP(base))
+
+/*! @brief Set the SRAMUAP field to a new value. */
+#define MCM_WR_CR_SRAMUAP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMUAP_MASK, MCM_CR_SRAMUAP(value)))
+#define MCM_BWR_CR_SRAMUAP(base, value) (MCM_WR_CR_SRAMUAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMUWP[26] (RW)
+ *
+ * When this bit is set, writes to SRAM_U array generates a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMUWP field. */
+#define MCM_RD_CR_SRAMUWP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMUWP_MASK) >> MCM_CR_SRAMUWP_SHIFT)
+#define MCM_BRD_CR_SRAMUWP(base) (MCM_RD_CR_SRAMUWP(base))
+
+/*! @brief Set the SRAMUWP field to a new value. */
+#define MCM_WR_CR_SRAMUWP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMUWP_MASK, MCM_CR_SRAMUWP(value)))
+#define MCM_BWR_CR_SRAMUWP(base, value) (MCM_WR_CR_SRAMUWP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_L array.
+ *
+ * Values:
+ * - 0b00 - Round robin
+ * - 0b01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 0b10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 0b11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMLAP field. */
+#define MCM_RD_CR_SRAMLAP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMLAP_MASK) >> MCM_CR_SRAMLAP_SHIFT)
+#define MCM_BRD_CR_SRAMLAP(base) (MCM_RD_CR_SRAMLAP(base))
+
+/*! @brief Set the SRAMLAP field to a new value. */
+#define MCM_WR_CR_SRAMLAP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMLAP_MASK, MCM_CR_SRAMLAP(value)))
+#define MCM_BWR_CR_SRAMLAP(base, value) (MCM_WR_CR_SRAMLAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMLWP[30] (RW)
+ *
+ * When this bit is set, writes to SRAM_L array generates a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMLWP field. */
+#define MCM_RD_CR_SRAMLWP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMLWP_MASK) >> MCM_CR_SRAMLWP_SHIFT)
+#define MCM_BRD_CR_SRAMLWP(base) (MCM_RD_CR_SRAMLWP(base))
+
+/*! @brief Set the SRAMLWP field to a new value. */
+#define MCM_WR_CR_SRAMLWP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMLWP_MASK, MCM_CR_SRAMLWP(value)))
+#define MCM_BWR_CR_SRAMLWP(base, value) (MCM_WR_CR_SRAMLWP(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ISCR - Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ISCR - Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ISCR register
+ */
+/*@{*/
+#define MCM_RD_ISCR(base)        (MCM_ISCR_REG(base))
+#define MCM_WR_ISCR(base, value) (MCM_ISCR_REG(base) = (value))
+#define MCM_RMW_ISCR(base, mask, value) (MCM_WR_ISCR(base, (MCM_RD_ISCR(base) & ~(mask)) | (value)))
+#define MCM_SET_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) |  (value)))
+#define MCM_CLR_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) & ~(value)))
+#define MCM_TOG_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ISCR bitfields
+ */
+
+/*!
+ * @name Register MCM_ISCR, field IRQ[1] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0b0 - No pending interrupt
+ * - 0b1 - Due to the ETB counter expiring, a normal interrupt is pending
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_IRQ field. */
+#define MCM_RD_ISCR_IRQ(base) ((MCM_ISCR_REG(base) & MCM_ISCR_IRQ_MASK) >> MCM_ISCR_IRQ_SHIFT)
+#define MCM_BRD_ISCR_IRQ(base) (MCM_RD_ISCR_IRQ(base))
+
+/*! @brief Set the IRQ field to a new value. */
+#define MCM_WR_ISCR_IRQ(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_IRQ(value)))
+#define MCM_BWR_ISCR_IRQ(base, value) (MCM_WR_ISCR_IRQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field NMI[2] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0b0 - No pending NMI
+ * - 0b1 - Due to the ETB counter expiring, an NMI is pending
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_NMI field. */
+#define MCM_RD_ISCR_NMI(base) ((MCM_ISCR_REG(base) & MCM_ISCR_NMI_MASK) >> MCM_ISCR_NMI_SHIFT)
+#define MCM_BRD_ISCR_NMI(base) (MCM_RD_ISCR_NMI(base))
+
+/*! @brief Set the NMI field to a new value. */
+#define MCM_WR_ISCR_NMI(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_NMI_MASK | MCM_ISCR_IRQ_MASK), MCM_ISCR_NMI(value)))
+#define MCM_BWR_ISCR_NMI(base, value) (MCM_WR_ISCR_NMI(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field DHREQ[3] (RO)
+ *
+ * Indicates that a debug halt request is initiated due to a ETB counter
+ * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
+ * counter is disabled or when the ETB counter is reloaded.
+ *
+ * Values:
+ * - 0b0 - No debug halt request
+ * - 0b1 - Debug halt request initiated
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_DHREQ field. */
+#define MCM_RD_ISCR_DHREQ(base) ((MCM_ISCR_REG(base) & MCM_ISCR_DHREQ_MASK) >> MCM_ISCR_DHREQ_SHIFT)
+#define MCM_BRD_ISCR_DHREQ(base) (MCM_RD_ISCR_DHREQ(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIOC[8] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
+ * illegal operation has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IOC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIOC field. */
+#define MCM_RD_ISCR_FIOC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIOC_MASK) >> MCM_ISCR_FIOC_SHIFT)
+#define MCM_BRD_ISCR_FIOC(base) (MCM_RD_ISCR_FIOC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FDZC[9] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
+ * divide by zero has been detected in the processor's FPU. Once set, this bit remains
+ * set until software clears the FPSCR[DZC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FDZC field. */
+#define MCM_RD_ISCR_FDZC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FDZC_MASK) >> MCM_ISCR_FDZC_SHIFT)
+#define MCM_BRD_ISCR_FDZC(base) (MCM_RD_ISCR_FDZC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FOFC[10] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
+ * overflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[OFC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FOFC field. */
+#define MCM_RD_ISCR_FOFC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FOFC_MASK) >> MCM_ISCR_FOFC_SHIFT)
+#define MCM_BRD_ISCR_FOFC(base) (MCM_RD_ISCR_FOFC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FUFC[11] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
+ * underflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[UFC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FUFC field. */
+#define MCM_RD_ISCR_FUFC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FUFC_MASK) >> MCM_ISCR_FUFC_SHIFT)
+#define MCM_BRD_ISCR_FUFC(base) (MCM_RD_ISCR_FUFC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIXC[12] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
+ * inexact number has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IXC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIXC field. */
+#define MCM_RD_ISCR_FIXC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIXC_MASK) >> MCM_ISCR_FIXC_SHIFT)
+#define MCM_BRD_ISCR_FIXC(base) (MCM_RD_ISCR_FIXC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIDC[15] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
+ * denormalized number has been detected in the processor's FPU. Once set, this
+ * bit remains set until software clears the FPSCR[IDC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIDC field. */
+#define MCM_RD_ISCR_FIDC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIDC_MASK) >> MCM_ISCR_FIDC_SHIFT)
+#define MCM_BRD_ISCR_FIDC(base) (MCM_RD_ISCR_FIDC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIOCE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIOCE field. */
+#define MCM_RD_ISCR_FIOCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIOCE_MASK) >> MCM_ISCR_FIOCE_SHIFT)
+#define MCM_BRD_ISCR_FIOCE(base) (MCM_RD_ISCR_FIOCE(base))
+
+/*! @brief Set the FIOCE field to a new value. */
+#define MCM_WR_ISCR_FIOCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIOCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIOCE(value)))
+#define MCM_BWR_ISCR_FIOCE(base, value) (MCM_WR_ISCR_FIOCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FDZCE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FDZCE field. */
+#define MCM_RD_ISCR_FDZCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FDZCE_MASK) >> MCM_ISCR_FDZCE_SHIFT)
+#define MCM_BRD_ISCR_FDZCE(base) (MCM_RD_ISCR_FDZCE(base))
+
+/*! @brief Set the FDZCE field to a new value. */
+#define MCM_WR_ISCR_FDZCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FDZCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FDZCE(value)))
+#define MCM_BWR_ISCR_FDZCE(base, value) (MCM_WR_ISCR_FDZCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FOFCE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FOFCE field. */
+#define MCM_RD_ISCR_FOFCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FOFCE_MASK) >> MCM_ISCR_FOFCE_SHIFT)
+#define MCM_BRD_ISCR_FOFCE(base) (MCM_RD_ISCR_FOFCE(base))
+
+/*! @brief Set the FOFCE field to a new value. */
+#define MCM_WR_ISCR_FOFCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FOFCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FOFCE(value)))
+#define MCM_BWR_ISCR_FOFCE(base, value) (MCM_WR_ISCR_FOFCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FUFCE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FUFCE field. */
+#define MCM_RD_ISCR_FUFCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FUFCE_MASK) >> MCM_ISCR_FUFCE_SHIFT)
+#define MCM_BRD_ISCR_FUFCE(base) (MCM_RD_ISCR_FUFCE(base))
+
+/*! @brief Set the FUFCE field to a new value. */
+#define MCM_WR_ISCR_FUFCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FUFCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FUFCE(value)))
+#define MCM_BWR_ISCR_FUFCE(base, value) (MCM_WR_ISCR_FUFCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIXCE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIXCE field. */
+#define MCM_RD_ISCR_FIXCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIXCE_MASK) >> MCM_ISCR_FIXCE_SHIFT)
+#define MCM_BRD_ISCR_FIXCE(base) (MCM_RD_ISCR_FIXCE(base))
+
+/*! @brief Set the FIXCE field to a new value. */
+#define MCM_WR_ISCR_FIXCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIXCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIXCE(value)))
+#define MCM_BWR_ISCR_FIXCE(base, value) (MCM_WR_ISCR_FIXCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIDCE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIDCE field. */
+#define MCM_RD_ISCR_FIDCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIDCE_MASK) >> MCM_ISCR_FIDCE_SHIFT)
+#define MCM_BRD_ISCR_FIDCE(base) (MCM_RD_ISCR_FIDCE(base))
+
+/*! @brief Set the FIDCE field to a new value. */
+#define MCM_WR_ISCR_FIDCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIDCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIDCE(value)))
+#define MCM_BWR_ISCR_FIDCE(base, value) (MCM_WR_ISCR_FIDCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBCC - ETB Counter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBCC - ETB Counter Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBCC register
+ */
+/*@{*/
+#define MCM_RD_ETBCC(base)       (MCM_ETBCC_REG(base))
+#define MCM_WR_ETBCC(base, value) (MCM_ETBCC_REG(base) = (value))
+#define MCM_RMW_ETBCC(base, mask, value) (MCM_WR_ETBCC(base, (MCM_RD_ETBCC(base) & ~(mask)) | (value)))
+#define MCM_SET_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) |  (value)))
+#define MCM_CLR_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) & ~(value)))
+#define MCM_TOG_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBCC bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCC, field CNTEN[0] (RW)
+ *
+ * Enables the ETB counter.
+ *
+ * Values:
+ * - 0b0 - ETB counter disabled
+ * - 0b1 - ETB counter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_CNTEN field. */
+#define MCM_RD_ETBCC_CNTEN(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_CNTEN_MASK) >> MCM_ETBCC_CNTEN_SHIFT)
+#define MCM_BRD_ETBCC_CNTEN(base) (MCM_RD_ETBCC_CNTEN(base))
+
+/*! @brief Set the CNTEN field to a new value. */
+#define MCM_WR_ETBCC_CNTEN(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_CNTEN_MASK, MCM_ETBCC_CNTEN(value)))
+#define MCM_BWR_ETBCC_CNTEN(base, value) (MCM_WR_ETBCC_CNTEN(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
+ *
+ * Values:
+ * - 0b00 - No response when the ETB count expires
+ * - 0b01 - Generate a normal interrupt when the ETB count expires
+ * - 0b10 - Generate an NMI when the ETB count expires
+ * - 0b11 - Generate a debug halt when the ETB count expires
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_RSPT field. */
+#define MCM_RD_ETBCC_RSPT(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_RSPT_MASK) >> MCM_ETBCC_RSPT_SHIFT)
+#define MCM_BRD_ETBCC_RSPT(base) (MCM_RD_ETBCC_RSPT(base))
+
+/*! @brief Set the RSPT field to a new value. */
+#define MCM_WR_ETBCC_RSPT(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_RSPT_MASK, MCM_ETBCC_RSPT(value)))
+#define MCM_BWR_ETBCC_RSPT(base, value) (MCM_WR_ETBCC_RSPT(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field RLRQ[3] (RW)
+ *
+ * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
+ * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
+ * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
+ * If debug halt was enabled and a debug halt request was asserted on counter
+ * expiration, setting this bit clears the debug halt request.
+ *
+ * Values:
+ * - 0b0 - No effect
+ * - 0b1 - Clears pending debug halt, NMI, or IRQ interrupt requests
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_RLRQ field. */
+#define MCM_RD_ETBCC_RLRQ(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_RLRQ_MASK) >> MCM_ETBCC_RLRQ_SHIFT)
+#define MCM_BRD_ETBCC_RLRQ(base) (MCM_RD_ETBCC_RLRQ(base))
+
+/*! @brief Set the RLRQ field to a new value. */
+#define MCM_WR_ETBCC_RLRQ(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_RLRQ_MASK, MCM_ETBCC_RLRQ(value)))
+#define MCM_BWR_ETBCC_RLRQ(base, value) (MCM_WR_ETBCC_RLRQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field ETDIS[4] (RW)
+ *
+ * Disables the trace path from ETM to TPIU.
+ *
+ * Values:
+ * - 0b0 - ETM-to-TPIU trace path enabled
+ * - 0b1 - ETM-to-TPIU trace path disabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_ETDIS field. */
+#define MCM_RD_ETBCC_ETDIS(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_ETDIS_MASK) >> MCM_ETBCC_ETDIS_SHIFT)
+#define MCM_BRD_ETBCC_ETDIS(base) (MCM_RD_ETBCC_ETDIS(base))
+
+/*! @brief Set the ETDIS field to a new value. */
+#define MCM_WR_ETBCC_ETDIS(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_ETDIS_MASK, MCM_ETBCC_ETDIS(value)))
+#define MCM_BWR_ETBCC_ETDIS(base, value) (MCM_WR_ETBCC_ETDIS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field ITDIS[5] (RW)
+ *
+ * Disables the trace path from ITM to TPIU.
+ *
+ * Values:
+ * - 0b0 - ITM-to-TPIU trace path enabled
+ * - 0b1 - ITM-to-TPIU trace path disabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_ITDIS field. */
+#define MCM_RD_ETBCC_ITDIS(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_ITDIS_MASK) >> MCM_ETBCC_ITDIS_SHIFT)
+#define MCM_BRD_ETBCC_ITDIS(base) (MCM_RD_ETBCC_ITDIS(base))
+
+/*! @brief Set the ITDIS field to a new value. */
+#define MCM_WR_ETBCC_ITDIS(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_ITDIS_MASK, MCM_ETBCC_ITDIS(value)))
+#define MCM_BWR_ETBCC_ITDIS(base, value) (MCM_WR_ETBCC_ITDIS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBRL - ETB Reload register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBRL - ETB Reload register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBRL register
+ */
+/*@{*/
+#define MCM_RD_ETBRL(base)       (MCM_ETBRL_REG(base))
+#define MCM_WR_ETBRL(base, value) (MCM_ETBRL_REG(base) = (value))
+#define MCM_RMW_ETBRL(base, mask, value) (MCM_WR_ETBRL(base, (MCM_RD_ETBRL(base) & ~(mask)) | (value)))
+#define MCM_SET_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) |  (value)))
+#define MCM_CLR_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) & ~(value)))
+#define MCM_TOG_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBRL bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
+ *
+ * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
+ * value to this field results in a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBRL_RELOAD field. */
+#define MCM_RD_ETBRL_RELOAD(base) ((MCM_ETBRL_REG(base) & MCM_ETBRL_RELOAD_MASK) >> MCM_ETBRL_RELOAD_SHIFT)
+#define MCM_BRD_ETBRL_RELOAD(base) (MCM_RD_ETBRL_RELOAD(base))
+
+/*! @brief Set the RELOAD field to a new value. */
+#define MCM_WR_ETBRL_RELOAD(base, value) (MCM_RMW_ETBRL(base, MCM_ETBRL_RELOAD_MASK, MCM_ETBRL_RELOAD(value)))
+#define MCM_BWR_ETBRL_RELOAD(base, value) (MCM_WR_ETBRL_RELOAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBCNT - ETB Counter Value register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBCNT - ETB Counter Value register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBCNT register
+ */
+/*@{*/
+#define MCM_RD_ETBCNT(base)      (MCM_ETBCNT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBCNT bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
+ *
+ * Indicates the current 0-mod-4 value of the counter.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCNT_COUNTER field. */
+#define MCM_RD_ETBCNT_COUNTER(base) ((MCM_ETBCNT_REG(base) & MCM_ETBCNT_COUNTER_MASK) >> MCM_ETBCNT_COUNTER_SHIFT)
+#define MCM_BRD_ETBCNT_COUNTER(base) (MCM_RD_ETBCNT_COUNTER(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PID - Process ID register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PID - Process ID register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register drives the M0_PID and M1_PID values in the Memory Protection
+ * Unit(MPU). System software loads this register before passing control to a given
+ * user mode process. If the PID of the process does not match the value in this
+ * register, a bus error occurs. See the MPU chapter for more details.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PID register
+ */
+/*@{*/
+#define MCM_RD_PID(base)         (MCM_PID_REG(base))
+#define MCM_WR_PID(base, value)  (MCM_PID_REG(base) = (value))
+#define MCM_RMW_PID(base, mask, value) (MCM_WR_PID(base, (MCM_RD_PID(base) & ~(mask)) | (value)))
+#define MCM_SET_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) |  (value)))
+#define MCM_CLR_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) & ~(value)))
+#define MCM_TOG_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PID bitfields
+ */
+
+/*!
+ * @name Register MCM_PID, field PID[7:0] (RW)
+ *
+ * Drives the M0_PID and M1_PID values in the MPU.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PID_PID field. */
+#define MCM_RD_PID_PID(base) ((MCM_PID_REG(base) & MCM_PID_PID_MASK) >> MCM_PID_PID_SHIFT)
+#define MCM_BRD_PID_PID(base) (MCM_RD_PID_PID(base))
+
+/*! @brief Set the PID field to a new value. */
+#define MCM_WR_PID_PID(base, value) (MCM_RMW_PID(base, MCM_PID_PID_MASK, MCM_PID_PID(value)))
+#define MCM_BWR_PID_PID(base, value) (MCM_WR_PID_PID(base, value))
+/*@}*/
+
+/*
+ * MK64F12 MPU
+ *
+ * Memory protection unit
+ *
+ * Registers defined in this header file:
+ * - MPU_CESR - Control/Error Status Register
+ * - MPU_EAR - Error Address Register, slave port n
+ * - MPU_EDR - Error Detail Register, slave port n
+ * - MPU_WORD - Region Descriptor n, Word 0
+ * - MPU_RGDAAC - Region Descriptor Alternate Access Control n
+ */
+
+#define MPU_INSTANCE_COUNT (1U) /*!< Number of instances of the MPU module. */
+#define MPU_IDX (0U) /*!< Instance number for MPU. */
+
+/*******************************************************************************
+ * MPU_CESR - Control/Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_CESR - Control/Error Status Register (RW)
+ *
+ * Reset value: 0x00815101U
+ */
+/*!
+ * @name Constants and macros for entire MPU_CESR register
+ */
+/*@{*/
+#define MPU_RD_CESR(base)        (MPU_CESR_REG(base))
+#define MPU_WR_CESR(base, value) (MPU_CESR_REG(base) = (value))
+#define MPU_RMW_CESR(base, mask, value) (MPU_WR_CESR(base, (MPU_RD_CESR(base) & ~(mask)) | (value)))
+#define MPU_SET_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) |  (value)))
+#define MPU_CLR_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) & ~(value)))
+#define MPU_TOG_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_CESR bitfields
+ */
+
+/*!
+ * @name Register MPU_CESR, field VLD[0] (RW)
+ *
+ * Global enable/disable for the MPU.
+ *
+ * Values:
+ * - 0b0 - MPU is disabled. All accesses from all bus masters are allowed.
+ * - 0b1 - MPU is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_VLD field. */
+#define MPU_RD_CESR_VLD(base) ((MPU_CESR_REG(base) & MPU_CESR_VLD_MASK) >> MPU_CESR_VLD_SHIFT)
+#define MPU_BRD_CESR_VLD(base) (BITBAND_ACCESS32(&MPU_CESR_REG(base), MPU_CESR_VLD_SHIFT))
+
+/*! @brief Set the VLD field to a new value. */
+#define MPU_WR_CESR_VLD(base, value) (MPU_RMW_CESR(base, (MPU_CESR_VLD_MASK | MPU_CESR_SPERR_MASK), MPU_CESR_VLD(value)))
+#define MPU_BWR_CESR_VLD(base, value) (BITBAND_ACCESS32(&MPU_CESR_REG(base), MPU_CESR_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field NRGD[11:8] (RO)
+ *
+ * Indicates the number of region descriptors implemented in the MPU.
+ *
+ * Values:
+ * - 0b0000 - 8 region descriptors
+ * - 0b0001 - 12 region descriptors
+ * - 0b0010 - 16 region descriptors
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_NRGD field. */
+#define MPU_RD_CESR_NRGD(base) ((MPU_CESR_REG(base) & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT)
+#define MPU_BRD_CESR_NRGD(base) (MPU_RD_CESR_NRGD(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field NSP[15:12] (RO)
+ *
+ * Specifies the number of slave ports connected to the MPU.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_NSP field. */
+#define MPU_RD_CESR_NSP(base) ((MPU_CESR_REG(base) & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT)
+#define MPU_BRD_CESR_NSP(base) (MPU_RD_CESR_NSP(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field HRL[19:16] (RO)
+ *
+ * Specifies the MPU's hardware and definition revision level. It can be read by
+ * software to determine the functional definition of the module.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_HRL field. */
+#define MPU_RD_CESR_HRL(base) ((MPU_CESR_REG(base) & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT)
+#define MPU_BRD_CESR_HRL(base) (MPU_RD_CESR_HRL(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field SPERR[31:27] (W1C)
+ *
+ * Indicates a captured error in EARn and EDRn. This bit is set when the
+ * hardware detects an error and records the faulting address and attributes. It is
+ * cleared by writing one to it. If another error is captured at the exact same cycle
+ * as the write, the flag remains set. A find-first-one instruction or
+ * equivalent can detect the presence of a captured error. The following shows the
+ * correspondence between the bit number and slave port number: Bit 31 corresponds to
+ * slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
+ * port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
+ *
+ * Values:
+ * - 0b00000 - No error has occurred for slave port n.
+ * - 0b00001 - An error has occurred for slave port n.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_SPERR field. */
+#define MPU_RD_CESR_SPERR(base) ((MPU_CESR_REG(base) & MPU_CESR_SPERR_MASK) >> MPU_CESR_SPERR_SHIFT)
+#define MPU_BRD_CESR_SPERR(base) (MPU_RD_CESR_SPERR(base))
+
+/*! @brief Set the SPERR field to a new value. */
+#define MPU_WR_CESR_SPERR(base, value) (MPU_RMW_CESR(base, MPU_CESR_SPERR_MASK, MPU_CESR_SPERR(value)))
+#define MPU_BWR_CESR_SPERR(base, value) (MPU_WR_CESR_SPERR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_EAR - Error Address Register, slave port n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_EAR - Error Address Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, the 32-bit reference
+ * address is captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] set. Additional information about the faulting access is captured in
+ * the corresponding EDRn at the same time. This register and the corresponding
+ * EDRn contain the most recent access error; there are no hardware interlocks with
+ * CESR[SPERR], as the error registers are always loaded upon the occurrence of
+ * each protection violation.
+ */
+/*!
+ * @name Constants and macros for entire MPU_EAR register
+ */
+/*@{*/
+#define MPU_RD_EAR(base, index)  (MPU_EAR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_EDR - Error Detail Register, slave port n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_EDR - Error Detail Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, 32 bits of error detail
+ * are captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] is set. Information on the faulting address is captured in the
+ * corresponding EARn register at the same time. This register and the corresponding EARn
+ * register contain the most recent access error; there are no hardware interlocks
+ * with CESR[SPERR] as the error registers are always loaded upon the occurrence
+ * of each protection violation.
+ */
+/*!
+ * @name Constants and macros for entire MPU_EDR register
+ */
+/*@{*/
+#define MPU_RD_EDR(base, index)  (MPU_EDR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_EDR bitfields
+ */
+
+/*!
+ * @name Register MPU_EDR, field ERW[0] (RO)
+ *
+ * Indicates the access type of the faulting reference.
+ *
+ * Values:
+ * - 0b0 - Read
+ * - 0b1 - Write
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_ERW field. */
+#define MPU_RD_EDR_ERW(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT)
+#define MPU_BRD_EDR_ERW(base, index) (BITBAND_ACCESS32(&MPU_EDR_REG(base, index), MPU_EDR_ERW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EATTR[3:1] (RO)
+ *
+ * Indicates attribute information about the faulting reference. All other
+ * encodings are reserved.
+ *
+ * Values:
+ * - 0b000 - User mode, instruction access
+ * - 0b001 - User mode, data access
+ * - 0b010 - Supervisor mode, instruction access
+ * - 0b011 - Supervisor mode, data access
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EATTR field. */
+#define MPU_RD_EDR_EATTR(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT)
+#define MPU_BRD_EDR_EATTR(base, index) (MPU_RD_EDR_EATTR(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EMN[7:4] (RO)
+ *
+ * Indicates the bus master that generated the access error.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EMN field. */
+#define MPU_RD_EDR_EMN(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT)
+#define MPU_BRD_EDR_EMN(base, index) (MPU_RD_EDR_EMN(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EPID[15:8] (RO)
+ *
+ * Records the process identifier of the faulting reference. The process
+ * identifier is typically driven only by processor cores; for other bus masters, this
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EPID field. */
+#define MPU_RD_EDR_EPID(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT)
+#define MPU_BRD_EDR_EPID(base, index) (MPU_RD_EDR_EPID(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EACD[31:16] (RO)
+ *
+ * Indicates the region descriptor with the access error. If EDRn contains a
+ * captured error and EACD is cleared, an access did not hit in any region
+ * descriptor. If only a single EACD bit is set, the protection error was caused by a
+ * single non-overlapping region descriptor. If two or more EACD bits are set, the
+ * protection error was caused by an overlapping set of region descriptors.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EACD field. */
+#define MPU_RD_EDR_EACD(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EACD_MASK) >> MPU_EDR_EACD_SHIFT)
+#define MPU_BRD_EDR_EACD(base, index) (MPU_RD_EDR_EACD(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_WORD - Region Descriptor n, Word 0
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_WORD - Region Descriptor n, Word 0 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The first word of the region descriptor defines the 0-modulo-32 byte start
+ * address of the memory region. Writes to this register clear the region
+ * descriptor's valid bit (RGDn_WORD3[VLD]).
+ */
+/*!
+ * @name Constants and macros for entire MPU_WORD register
+ */
+/*@{*/
+#define MPU_RD_WORD(base, index, index2) (MPU_WORD_REG(base, index, index2))
+#define MPU_WR_WORD(base, index, index2, value) (MPU_WORD_REG(base, index, index2) = (value))
+#define MPU_RMW_WORD(base, index, index2, mask, value) (MPU_WR_WORD(base, index, index2, (MPU_RD_WORD(base, index, index2) & ~(mask)) | (value)))
+#define MPU_SET_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) |  (value)))
+#define MPU_CLR_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) & ~(value)))
+#define MPU_TOG_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_WORD bitfields
+ */
+
+/*!
+ * @name Register MPU_WORD, field VLD[0] (RW)
+ *
+ * Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
+ * bit.
+ *
+ * Values:
+ * - 0b0 - Region descriptor is invalid
+ * - 0b1 - Region descriptor is valid
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_VLD field. */
+#define MPU_RD_WORD_VLD(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_VLD_MASK) >> MPU_WORD_VLD_SHIFT)
+#define MPU_BRD_WORD_VLD(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_VLD_SHIFT))
+
+/*! @brief Set the VLD field to a new value. */
+#define MPU_WR_WORD_VLD(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_VLD_MASK, MPU_WORD_VLD(value)))
+#define MPU_BWR_WORD_VLD(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0UM field. */
+#define MPU_RD_WORD_M0UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0UM_MASK) >> MPU_WORD_M0UM_SHIFT)
+#define MPU_BRD_WORD_M0UM(base, index, index2) (MPU_RD_WORD_M0UM(base, index, index2))
+
+/*! @brief Set the M0UM field to a new value. */
+#define MPU_WR_WORD_M0UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0UM_MASK, MPU_WORD_M0UM(value)))
+#define MPU_BWR_WORD_M0UM(base, index, index2, value) (MPU_WR_WORD_M0UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0SM field. */
+#define MPU_RD_WORD_M0SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0SM_MASK) >> MPU_WORD_M0SM_SHIFT)
+#define MPU_BRD_WORD_M0SM(base, index, index2) (MPU_RD_WORD_M0SM(base, index, index2))
+
+/*! @brief Set the M0SM field to a new value. */
+#define MPU_WR_WORD_M0SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0SM_MASK, MPU_WORD_M0SM(value)))
+#define MPU_BWR_WORD_M0SM(base, index, index2, value) (MPU_WR_WORD_M0SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0PE[5] (RW)
+ *
+ * See M0PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0PE field. */
+#define MPU_RD_WORD_M0PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0PE_MASK) >> MPU_WORD_M0PE_SHIFT)
+#define MPU_BRD_WORD_M0PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M0PE_SHIFT))
+
+/*! @brief Set the M0PE field to a new value. */
+#define MPU_WR_WORD_M0PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0PE_MASK, MPU_WORD_M0PE(value)))
+#define MPU_BWR_WORD_M0PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M0PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field ENDADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 31-modulo-32 byte end address of the
+ * memory region. The MPU does not verify that ENDADDR >= SRTADDR.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_ENDADDR field. */
+#define MPU_RD_WORD_ENDADDR(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_ENDADDR_MASK) >> MPU_WORD_ENDADDR_SHIFT)
+#define MPU_BRD_WORD_ENDADDR(base, index, index2) (MPU_RD_WORD_ENDADDR(base, index, index2))
+
+/*! @brief Set the ENDADDR field to a new value. */
+#define MPU_WR_WORD_ENDADDR(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_ENDADDR_MASK, MPU_WORD_ENDADDR(value)))
+#define MPU_BWR_WORD_ENDADDR(base, index, index2, value) (MPU_WR_WORD_ENDADDR(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field SRTADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 0-modulo-32 byte start address of
+ * the memory region.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_SRTADDR field. */
+#define MPU_RD_WORD_SRTADDR(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_SRTADDR_MASK) >> MPU_WORD_SRTADDR_SHIFT)
+#define MPU_BRD_WORD_SRTADDR(base, index, index2) (MPU_RD_WORD_SRTADDR(base, index, index2))
+
+/*! @brief Set the SRTADDR field to a new value. */
+#define MPU_WR_WORD_SRTADDR(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_SRTADDR_MASK, MPU_WORD_SRTADDR(value)))
+#define MPU_BWR_WORD_SRTADDR(base, index, index2, value) (MPU_WR_WORD_SRTADDR(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1UM field. */
+#define MPU_RD_WORD_M1UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1UM_MASK) >> MPU_WORD_M1UM_SHIFT)
+#define MPU_BRD_WORD_M1UM(base, index, index2) (MPU_RD_WORD_M1UM(base, index, index2))
+
+/*! @brief Set the M1UM field to a new value. */
+#define MPU_WR_WORD_M1UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1UM_MASK, MPU_WORD_M1UM(value)))
+#define MPU_BWR_WORD_M1UM(base, index, index2, value) (MPU_WR_WORD_M1UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1SM field. */
+#define MPU_RD_WORD_M1SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1SM_MASK) >> MPU_WORD_M1SM_SHIFT)
+#define MPU_BRD_WORD_M1SM(base, index, index2) (MPU_RD_WORD_M1SM(base, index, index2))
+
+/*! @brief Set the M1SM field to a new value. */
+#define MPU_WR_WORD_M1SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1SM_MASK, MPU_WORD_M1SM(value)))
+#define MPU_BWR_WORD_M1SM(base, index, index2, value) (MPU_WR_WORD_M1SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1PE field. */
+#define MPU_RD_WORD_M1PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1PE_MASK) >> MPU_WORD_M1PE_SHIFT)
+#define MPU_BRD_WORD_M1PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M1PE_SHIFT))
+
+/*! @brief Set the M1PE field to a new value. */
+#define MPU_WR_WORD_M1PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1PE_MASK, MPU_WORD_M1PE(value)))
+#define MPU_BWR_WORD_M1PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M1PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2UM field. */
+#define MPU_RD_WORD_M2UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2UM_MASK) >> MPU_WORD_M2UM_SHIFT)
+#define MPU_BRD_WORD_M2UM(base, index, index2) (MPU_RD_WORD_M2UM(base, index, index2))
+
+/*! @brief Set the M2UM field to a new value. */
+#define MPU_WR_WORD_M2UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2UM_MASK, MPU_WORD_M2UM(value)))
+#define MPU_BWR_WORD_M2UM(base, index, index2, value) (MPU_WR_WORD_M2UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2SM field. */
+#define MPU_RD_WORD_M2SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2SM_MASK) >> MPU_WORD_M2SM_SHIFT)
+#define MPU_BRD_WORD_M2SM(base, index, index2) (MPU_RD_WORD_M2SM(base, index, index2))
+
+/*! @brief Set the M2SM field to a new value. */
+#define MPU_WR_WORD_M2SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2SM_MASK, MPU_WORD_M2SM(value)))
+#define MPU_BWR_WORD_M2SM(base, index, index2, value) (MPU_WR_WORD_M2SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field PIDMASK[23:16] (RW)
+ *
+ * Provides a masking capability so that multiple process identifiers can be
+ * included as part of the region hit determination. If a bit in PIDMASK is set,
+ * then the corresponding PID bit is ignored in the comparison. This field and PID
+ * are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
+ * more information on the handling of the PID and PIDMASK, see "Access Evaluation
+ * - Hit Determination."
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_PIDMASK field. */
+#define MPU_RD_WORD_PIDMASK(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_PIDMASK_MASK) >> MPU_WORD_PIDMASK_SHIFT)
+#define MPU_BRD_WORD_PIDMASK(base, index, index2) (MPU_RD_WORD_PIDMASK(base, index, index2))
+
+/*! @brief Set the PIDMASK field to a new value. */
+#define MPU_WR_WORD_PIDMASK(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_PIDMASK_MASK, MPU_WORD_PIDMASK(value)))
+#define MPU_BWR_WORD_PIDMASK(base, index, index2, value) (MPU_WR_WORD_PIDMASK(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2PE field. */
+#define MPU_RD_WORD_M2PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2PE_MASK) >> MPU_WORD_M2PE_SHIFT)
+#define MPU_BRD_WORD_M2PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M2PE_SHIFT))
+
+/*! @brief Set the M2PE field to a new value. */
+#define MPU_WR_WORD_M2PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2PE_MASK, MPU_WORD_M2PE(value)))
+#define MPU_BWR_WORD_M2PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M2PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in User mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0b000 - An attempted access of that mode may be terminated with an access
+ *     error (if not allowed by another descriptor) and the access not performed.
+ * - 0b001 - Allows the given access type to occur
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3UM field. */
+#define MPU_RD_WORD_M3UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3UM_MASK) >> MPU_WORD_M3UM_SHIFT)
+#define MPU_BRD_WORD_M3UM(base, index, index2) (MPU_RD_WORD_M3UM(base, index, index2))
+
+/*! @brief Set the M3UM field to a new value. */
+#define MPU_WR_WORD_M3UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3UM_MASK, MPU_WORD_M3UM(value)))
+#define MPU_BWR_WORD_M3UM(base, index, index2, value) (MPU_WR_WORD_M3UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 0b00 - r/w/x; read, write and execute allowed
+ * - 0b01 - r/x; read and execute allowed, but no write
+ * - 0b10 - r/w; read and write allowed, but no execute
+ * - 0b11 - Same as User mode defined in M3UM
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3SM field. */
+#define MPU_RD_WORD_M3SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3SM_MASK) >> MPU_WORD_M3SM_SHIFT)
+#define MPU_BRD_WORD_M3SM(base, index, index2) (MPU_RD_WORD_M3SM(base, index, index2))
+
+/*! @brief Set the M3SM field to a new value. */
+#define MPU_WR_WORD_M3SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3SM_MASK, MPU_WORD_M3SM(value)))
+#define MPU_BWR_WORD_M3SM(base, index, index2, value) (MPU_WR_WORD_M3SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the process identifier in the evaluation
+ * - 0b1 - Include the process identifier and mask (RGDn_WORD3) in the region
+ *     hit evaluation
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3PE field. */
+#define MPU_RD_WORD_M3PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3PE_MASK) >> MPU_WORD_M3PE_SHIFT)
+#define MPU_BRD_WORD_M3PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M3PE_SHIFT))
+
+/*! @brief Set the M3PE field to a new value. */
+#define MPU_WR_WORD_M3PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3PE_MASK, MPU_WORD_M3PE(value)))
+#define MPU_BWR_WORD_M3PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M3PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field PID[31:24] (RW)
+ *
+ * Specifies the process identifier that is included in the region hit
+ * determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
+ * field.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_PID field. */
+#define MPU_RD_WORD_PID(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_PID_MASK) >> MPU_WORD_PID_SHIFT)
+#define MPU_BRD_WORD_PID(base, index, index2) (MPU_RD_WORD_PID(base, index, index2))
+
+/*! @brief Set the PID field to a new value. */
+#define MPU_WR_WORD_PID(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_PID_MASK, MPU_WORD_PID(value)))
+#define MPU_BWR_WORD_PID(base, index, index2, value) (MPU_WR_WORD_PID(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 4 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M4WE field. */
+#define MPU_RD_WORD_M4WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M4WE_MASK) >> MPU_WORD_M4WE_SHIFT)
+#define MPU_BRD_WORD_M4WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4WE_SHIFT))
+
+/*! @brief Set the M4WE field to a new value. */
+#define MPU_WR_WORD_M4WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M4WE_MASK, MPU_WORD_M4WE(value)))
+#define MPU_BWR_WORD_M4WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 4 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M4RE field. */
+#define MPU_RD_WORD_M4RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M4RE_MASK) >> MPU_WORD_M4RE_SHIFT)
+#define MPU_BRD_WORD_M4RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4RE_SHIFT))
+
+/*! @brief Set the M4RE field to a new value. */
+#define MPU_WR_WORD_M4RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M4RE_MASK, MPU_WORD_M4RE(value)))
+#define MPU_BWR_WORD_M4RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 5 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M5WE field. */
+#define MPU_RD_WORD_M5WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M5WE_MASK) >> MPU_WORD_M5WE_SHIFT)
+#define MPU_BRD_WORD_M5WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5WE_SHIFT))
+
+/*! @brief Set the M5WE field to a new value. */
+#define MPU_WR_WORD_M5WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M5WE_MASK, MPU_WORD_M5WE(value)))
+#define MPU_BWR_WORD_M5WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 5 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M5RE field. */
+#define MPU_RD_WORD_M5RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M5RE_MASK) >> MPU_WORD_M5RE_SHIFT)
+#define MPU_BRD_WORD_M5RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5RE_SHIFT))
+
+/*! @brief Set the M5RE field to a new value. */
+#define MPU_WR_WORD_M5RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M5RE_MASK, MPU_WORD_M5RE(value)))
+#define MPU_BWR_WORD_M5RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 6 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M6WE field. */
+#define MPU_RD_WORD_M6WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M6WE_MASK) >> MPU_WORD_M6WE_SHIFT)
+#define MPU_BRD_WORD_M6WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6WE_SHIFT))
+
+/*! @brief Set the M6WE field to a new value. */
+#define MPU_WR_WORD_M6WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M6WE_MASK, MPU_WORD_M6WE(value)))
+#define MPU_BWR_WORD_M6WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 6 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M6RE field. */
+#define MPU_RD_WORD_M6RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M6RE_MASK) >> MPU_WORD_M6RE_SHIFT)
+#define MPU_BRD_WORD_M6RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6RE_SHIFT))
+
+/*! @brief Set the M6RE field to a new value. */
+#define MPU_WR_WORD_M6RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M6RE_MASK, MPU_WORD_M6RE(value)))
+#define MPU_BWR_WORD_M6RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 7 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M7WE field. */
+#define MPU_RD_WORD_M7WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M7WE_MASK) >> MPU_WORD_M7WE_SHIFT)
+#define MPU_BRD_WORD_M7WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7WE_SHIFT))
+
+/*! @brief Set the M7WE field to a new value. */
+#define MPU_WR_WORD_M7WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M7WE_MASK, MPU_WORD_M7WE(value)))
+#define MPU_BWR_WORD_M7WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 7 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M7RE field. */
+#define MPU_RD_WORD_M7RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M7RE_MASK) >> MPU_WORD_M7RE_SHIFT)
+#define MPU_BRD_WORD_M7RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7RE_SHIFT))
+
+/*! @brief Set the M7RE field to a new value. */
+#define MPU_WR_WORD_M7RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M7RE_MASK, MPU_WORD_M7RE(value)))
+#define MPU_BWR_WORD_M7RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_RGDAAC - Region Descriptor Alternate Access Control n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_RGDAAC - Region Descriptor Alternate Access Control n (RW)
+ *
+ * Reset value: 0x0061F7DFU
+ *
+ * Because software may adjust only the access controls within a region
+ * descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
+ * this 32-bit entity is available. Writing to this register does not affect the
+ * descriptor's valid bit.
+ */
+/*!
+ * @name Constants and macros for entire MPU_RGDAAC register
+ */
+/*@{*/
+#define MPU_RD_RGDAAC(base, index) (MPU_RGDAAC_REG(base, index))
+#define MPU_WR_RGDAAC(base, index, value) (MPU_RGDAAC_REG(base, index) = (value))
+#define MPU_RMW_RGDAAC(base, index, mask, value) (MPU_WR_RGDAAC(base, index, (MPU_RD_RGDAAC(base, index) & ~(mask)) | (value)))
+#define MPU_SET_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) |  (value)))
+#define MPU_CLR_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) & ~(value)))
+#define MPU_TOG_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_RGDAAC bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDAAC, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0UM field. */
+#define MPU_RD_RGDAAC_M0UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0UM_MASK) >> MPU_RGDAAC_M0UM_SHIFT)
+#define MPU_BRD_RGDAAC_M0UM(base, index) (MPU_RD_RGDAAC_M0UM(base, index))
+
+/*! @brief Set the M0UM field to a new value. */
+#define MPU_WR_RGDAAC_M0UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0UM_MASK, MPU_RGDAAC_M0UM(value)))
+#define MPU_BWR_RGDAAC_M0UM(base, index, value) (MPU_WR_RGDAAC_M0UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0SM field. */
+#define MPU_RD_RGDAAC_M0SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0SM_MASK) >> MPU_RGDAAC_M0SM_SHIFT)
+#define MPU_BRD_RGDAAC_M0SM(base, index) (MPU_RD_RGDAAC_M0SM(base, index))
+
+/*! @brief Set the M0SM field to a new value. */
+#define MPU_WR_RGDAAC_M0SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0SM_MASK, MPU_RGDAAC_M0SM(value)))
+#define MPU_BWR_RGDAAC_M0SM(base, index, value) (MPU_WR_RGDAAC_M0SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M0PE[5] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0PE field. */
+#define MPU_RD_RGDAAC_M0PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0PE_MASK) >> MPU_RGDAAC_M0PE_SHIFT)
+#define MPU_BRD_RGDAAC_M0PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M0PE_SHIFT))
+
+/*! @brief Set the M0PE field to a new value. */
+#define MPU_WR_RGDAAC_M0PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0PE_MASK, MPU_RGDAAC_M0PE(value)))
+#define MPU_BWR_RGDAAC_M0PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M0PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1UM field. */
+#define MPU_RD_RGDAAC_M1UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1UM_MASK) >> MPU_RGDAAC_M1UM_SHIFT)
+#define MPU_BRD_RGDAAC_M1UM(base, index) (MPU_RD_RGDAAC_M1UM(base, index))
+
+/*! @brief Set the M1UM field to a new value. */
+#define MPU_WR_RGDAAC_M1UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1UM_MASK, MPU_RGDAAC_M1UM(value)))
+#define MPU_BWR_RGDAAC_M1UM(base, index, value) (MPU_WR_RGDAAC_M1UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1SM field. */
+#define MPU_RD_RGDAAC_M1SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1SM_MASK) >> MPU_RGDAAC_M1SM_SHIFT)
+#define MPU_BRD_RGDAAC_M1SM(base, index) (MPU_RD_RGDAAC_M1SM(base, index))
+
+/*! @brief Set the M1SM field to a new value. */
+#define MPU_WR_RGDAAC_M1SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1SM_MASK, MPU_RGDAAC_M1SM(value)))
+#define MPU_BWR_RGDAAC_M1SM(base, index, value) (MPU_WR_RGDAAC_M1SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1PE field. */
+#define MPU_RD_RGDAAC_M1PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1PE_MASK) >> MPU_RGDAAC_M1PE_SHIFT)
+#define MPU_BRD_RGDAAC_M1PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M1PE_SHIFT))
+
+/*! @brief Set the M1PE field to a new value. */
+#define MPU_WR_RGDAAC_M1PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1PE_MASK, MPU_RGDAAC_M1PE(value)))
+#define MPU_BWR_RGDAAC_M1PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M1PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2UM field. */
+#define MPU_RD_RGDAAC_M2UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2UM_MASK) >> MPU_RGDAAC_M2UM_SHIFT)
+#define MPU_BRD_RGDAAC_M2UM(base, index) (MPU_RD_RGDAAC_M2UM(base, index))
+
+/*! @brief Set the M2UM field to a new value. */
+#define MPU_WR_RGDAAC_M2UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2UM_MASK, MPU_RGDAAC_M2UM(value)))
+#define MPU_BWR_RGDAAC_M2UM(base, index, value) (MPU_WR_RGDAAC_M2UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2SM field. */
+#define MPU_RD_RGDAAC_M2SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2SM_MASK) >> MPU_RGDAAC_M2SM_SHIFT)
+#define MPU_BRD_RGDAAC_M2SM(base, index) (MPU_RD_RGDAAC_M2SM(base, index))
+
+/*! @brief Set the M2SM field to a new value. */
+#define MPU_WR_RGDAAC_M2SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2SM_MASK, MPU_RGDAAC_M2SM(value)))
+#define MPU_BWR_RGDAAC_M2SM(base, index, value) (MPU_WR_RGDAAC_M2SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2PE field. */
+#define MPU_RD_RGDAAC_M2PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2PE_MASK) >> MPU_RGDAAC_M2PE_SHIFT)
+#define MPU_BRD_RGDAAC_M2PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M2PE_SHIFT))
+
+/*! @brief Set the M2PE field to a new value. */
+#define MPU_WR_RGDAAC_M2PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2PE_MASK, MPU_RGDAAC_M2PE(value)))
+#define MPU_BWR_RGDAAC_M2PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M2PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in user mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0b000 - An attempted access of that mode may be terminated with an access
+ *     error (if not allowed by another descriptor) and the access not performed.
+ * - 0b001 - Allows the given access type to occur
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3UM field. */
+#define MPU_RD_RGDAAC_M3UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3UM_MASK) >> MPU_RGDAAC_M3UM_SHIFT)
+#define MPU_BRD_RGDAAC_M3UM(base, index) (MPU_RD_RGDAAC_M3UM(base, index))
+
+/*! @brief Set the M3UM field to a new value. */
+#define MPU_WR_RGDAAC_M3UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3UM_MASK, MPU_RGDAAC_M3UM(value)))
+#define MPU_BWR_RGDAAC_M3UM(base, index, value) (MPU_WR_RGDAAC_M3UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 0b00 - r/w/x; read, write and execute allowed
+ * - 0b01 - r/x; read and execute allowed, but no write
+ * - 0b10 - r/w; read and write allowed, but no execute
+ * - 0b11 - Same as User mode defined in M3UM
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3SM field. */
+#define MPU_RD_RGDAAC_M3SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3SM_MASK) >> MPU_RGDAAC_M3SM_SHIFT)
+#define MPU_BRD_RGDAAC_M3SM(base, index) (MPU_RD_RGDAAC_M3SM(base, index))
+
+/*! @brief Set the M3SM field to a new value. */
+#define MPU_WR_RGDAAC_M3SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3SM_MASK, MPU_RGDAAC_M3SM(value)))
+#define MPU_BWR_RGDAAC_M3SM(base, index, value) (MPU_WR_RGDAAC_M3SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the process identifier in the evaluation
+ * - 0b1 - Include the process identifier and mask (RGDn.RGDAAC) in the region
+ *     hit evaluation
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3PE field. */
+#define MPU_RD_RGDAAC_M3PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3PE_MASK) >> MPU_RGDAAC_M3PE_SHIFT)
+#define MPU_BRD_RGDAAC_M3PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M3PE_SHIFT))
+
+/*! @brief Set the M3PE field to a new value. */
+#define MPU_WR_RGDAAC_M3PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3PE_MASK, MPU_RGDAAC_M3PE(value)))
+#define MPU_BWR_RGDAAC_M3PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M3PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 4 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M4WE field. */
+#define MPU_RD_RGDAAC_M4WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M4WE_MASK) >> MPU_RGDAAC_M4WE_SHIFT)
+#define MPU_BRD_RGDAAC_M4WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4WE_SHIFT))
+
+/*! @brief Set the M4WE field to a new value. */
+#define MPU_WR_RGDAAC_M4WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M4WE_MASK, MPU_RGDAAC_M4WE(value)))
+#define MPU_BWR_RGDAAC_M4WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 4 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M4RE field. */
+#define MPU_RD_RGDAAC_M4RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M4RE_MASK) >> MPU_RGDAAC_M4RE_SHIFT)
+#define MPU_BRD_RGDAAC_M4RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4RE_SHIFT))
+
+/*! @brief Set the M4RE field to a new value. */
+#define MPU_WR_RGDAAC_M4RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M4RE_MASK, MPU_RGDAAC_M4RE(value)))
+#define MPU_BWR_RGDAAC_M4RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 5 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M5WE field. */
+#define MPU_RD_RGDAAC_M5WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M5WE_MASK) >> MPU_RGDAAC_M5WE_SHIFT)
+#define MPU_BRD_RGDAAC_M5WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5WE_SHIFT))
+
+/*! @brief Set the M5WE field to a new value. */
+#define MPU_WR_RGDAAC_M5WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M5WE_MASK, MPU_RGDAAC_M5WE(value)))
+#define MPU_BWR_RGDAAC_M5WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 5 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M5RE field. */
+#define MPU_RD_RGDAAC_M5RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M5RE_MASK) >> MPU_RGDAAC_M5RE_SHIFT)
+#define MPU_BRD_RGDAAC_M5RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5RE_SHIFT))
+
+/*! @brief Set the M5RE field to a new value. */
+#define MPU_WR_RGDAAC_M5RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M5RE_MASK, MPU_RGDAAC_M5RE(value)))
+#define MPU_BWR_RGDAAC_M5RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 6 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M6WE field. */
+#define MPU_RD_RGDAAC_M6WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M6WE_MASK) >> MPU_RGDAAC_M6WE_SHIFT)
+#define MPU_BRD_RGDAAC_M6WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6WE_SHIFT))
+
+/*! @brief Set the M6WE field to a new value. */
+#define MPU_WR_RGDAAC_M6WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M6WE_MASK, MPU_RGDAAC_M6WE(value)))
+#define MPU_BWR_RGDAAC_M6WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 6 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M6RE field. */
+#define MPU_RD_RGDAAC_M6RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M6RE_MASK) >> MPU_RGDAAC_M6RE_SHIFT)
+#define MPU_BRD_RGDAAC_M6RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6RE_SHIFT))
+
+/*! @brief Set the M6RE field to a new value. */
+#define MPU_WR_RGDAAC_M6RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M6RE_MASK, MPU_RGDAAC_M6RE(value)))
+#define MPU_BWR_RGDAAC_M6RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 7 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M7WE field. */
+#define MPU_RD_RGDAAC_M7WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M7WE_MASK) >> MPU_RGDAAC_M7WE_SHIFT)
+#define MPU_BRD_RGDAAC_M7WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7WE_SHIFT))
+
+/*! @brief Set the M7WE field to a new value. */
+#define MPU_WR_RGDAAC_M7WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M7WE_MASK, MPU_RGDAAC_M7WE(value)))
+#define MPU_BWR_RGDAAC_M7WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 7 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M7RE field. */
+#define MPU_RD_RGDAAC_M7RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M7RE_MASK) >> MPU_RGDAAC_M7RE_SHIFT)
+#define MPU_BRD_RGDAAC_M7RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7RE_SHIFT))
+
+/*! @brief Set the M7RE field to a new value. */
+#define MPU_WR_RGDAAC_M7RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M7RE_MASK, MPU_RGDAAC_M7RE(value)))
+#define MPU_BWR_RGDAAC_M7RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7RE_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 NV
+ *
+ * Flash configuration field
+ *
+ * Registers defined in this header file:
+ * - NV_BACKKEY3 - Backdoor Comparison Key 3.
+ * - NV_BACKKEY2 - Backdoor Comparison Key 2.
+ * - NV_BACKKEY1 - Backdoor Comparison Key 1.
+ * - NV_BACKKEY0 - Backdoor Comparison Key 0.
+ * - NV_BACKKEY7 - Backdoor Comparison Key 7.
+ * - NV_BACKKEY6 - Backdoor Comparison Key 6.
+ * - NV_BACKKEY5 - Backdoor Comparison Key 5.
+ * - NV_BACKKEY4 - Backdoor Comparison Key 4.
+ * - NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ * - NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ * - NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ * - NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ * - NV_FSEC - Non-volatile Flash Security Register
+ * - NV_FOPT - Non-volatile Flash Option Register
+ * - NV_FEPROT - Non-volatile EERAM Protection Register
+ * - NV_FDPROT - Non-volatile D-Flash Protection Register
+ */
+
+#define NV_INSTANCE_COUNT (1U) /*!< Number of instances of the NV module. */
+#define FTFE_FlashConfig_IDX (0U) /*!< Instance number for FTFE_FlashConfig. */
+
+/*******************************************************************************
+ * NV_BACKKEY3 - Backdoor Comparison Key 3.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY3 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY3(base)     (NV_BACKKEY3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY2 - Backdoor Comparison Key 2.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY2 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY2(base)     (NV_BACKKEY2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY1 - Backdoor Comparison Key 1.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY1 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY1(base)     (NV_BACKKEY1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY0 - Backdoor Comparison Key 0.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY0 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY0(base)     (NV_BACKKEY0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY7 - Backdoor Comparison Key 7.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY7 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY7(base)     (NV_BACKKEY7_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY6 - Backdoor Comparison Key 6.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY6 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY6(base)     (NV_BACKKEY6_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY5 - Backdoor Comparison Key 5.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY5 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY5(base)     (NV_BACKKEY5_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY4 - Backdoor Comparison Key 4.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY4 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY4(base)     (NV_BACKKEY4_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT3 register
+ */
+/*@{*/
+#define NV_RD_FPROT3(base)       (NV_FPROT3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT2 register
+ */
+/*@{*/
+#define NV_RD_FPROT2(base)       (NV_FPROT2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT1 register
+ */
+/*@{*/
+#define NV_RD_FPROT1(base)       (NV_FPROT1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT0 register
+ */
+/*@{*/
+#define NV_RD_FPROT0(base)       (NV_FPROT0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FSEC - Non-volatile Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FSEC - Non-volatile Flash Security Register (RO)
+ *
+ * Reset value: 0xFFU
+ *
+ * Allows the user to customize the operation of the MCU at boot time
+ */
+/*!
+ * @name Constants and macros for entire NV_FSEC register
+ */
+/*@{*/
+#define NV_RD_FSEC(base)         (NV_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FSEC bitfields
+ */
+
+/*!
+ * @name Register NV_FSEC, field SEC[1:0] (RO)
+ *
+ * Values:
+ * - 0b10 - MCU security status is unsecure
+ * - 0b11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_SEC field. */
+#define NV_RD_FSEC_SEC(base) ((NV_FSEC_REG(base) & NV_FSEC_SEC_MASK) >> NV_FSEC_SEC_SHIFT)
+#define NV_BRD_FSEC_SEC(base) (NV_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field FSLACC[3:2] (RO)
+ *
+ * Values:
+ * - 0b10 - Freescale factory access denied
+ * - 0b11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_FSLACC field. */
+#define NV_RD_FSEC_FSLACC(base) ((NV_FSEC_REG(base) & NV_FSEC_FSLACC_MASK) >> NV_FSEC_FSLACC_SHIFT)
+#define NV_BRD_FSEC_FSLACC(base) (NV_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field MEEN[5:4] (RO)
+ *
+ * Values:
+ * - 0b10 - Mass erase is disabled
+ * - 0b11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_MEEN field. */
+#define NV_RD_FSEC_MEEN(base) ((NV_FSEC_REG(base) & NV_FSEC_MEEN_MASK) >> NV_FSEC_MEEN_SHIFT)
+#define NV_BRD_FSEC_MEEN(base) (NV_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field KEYEN[7:6] (RO)
+ *
+ * Values:
+ * - 0b10 - Backdoor key access enabled
+ * - 0b11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_KEYEN field. */
+#define NV_RD_FSEC_KEYEN(base) ((NV_FSEC_REG(base) & NV_FSEC_KEYEN_MASK) >> NV_FSEC_KEYEN_SHIFT)
+#define NV_BRD_FSEC_KEYEN(base) (NV_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FOPT - Non-volatile Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FOPT - Non-volatile Flash Option Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FOPT register
+ */
+/*@{*/
+#define NV_RD_FOPT(base)         (NV_FOPT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FOPT bitfields
+ */
+
+/*!
+ * @name Register NV_FOPT, field LPBOOT[0] (RO)
+ *
+ * Values:
+ * - 0b0 - Low-power boot
+ * - 0b1 - Normal boot
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_LPBOOT field. */
+#define NV_RD_FOPT_LPBOOT(base) ((NV_FOPT_REG(base) & NV_FOPT_LPBOOT_MASK) >> NV_FOPT_LPBOOT_SHIFT)
+#define NV_BRD_FOPT_LPBOOT(base) (BITBAND_ACCESS8(&NV_FOPT_REG(base), NV_FOPT_LPBOOT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register NV_FOPT, field EZPORT_DIS[1] (RO)
+ *
+ * Values:
+ * - 0b0 - EzPort operation is disabled
+ * - 0b1 - EzPort operation is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_EZPORT_DIS field. */
+#define NV_RD_FOPT_EZPORT_DIS(base) ((NV_FOPT_REG(base) & NV_FOPT_EZPORT_DIS_MASK) >> NV_FOPT_EZPORT_DIS_SHIFT)
+#define NV_BRD_FOPT_EZPORT_DIS(base) (BITBAND_ACCESS8(&NV_FOPT_REG(base), NV_FOPT_EZPORT_DIS_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FEPROT - Non-volatile EERAM Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FEPROT - Non-volatile EERAM Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FEPROT register
+ */
+/*@{*/
+#define NV_RD_FEPROT(base)       (NV_FEPROT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FDPROT - Non-volatile D-Flash Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FDPROT - Non-volatile D-Flash Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FDPROT register
+ */
+/*@{*/
+#define NV_RD_FDPROT(base)       (NV_FDPROT_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 OSC
+ *
+ * Oscillator
+ *
+ * Registers defined in this header file:
+ * - OSC_CR - OSC Control Register
+ */
+
+#define OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */
+#define OSC_IDX (0U) /*!< Instance number for OSC. */
+
+/*******************************************************************************
+ * OSC_CR - OSC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief OSC_CR - OSC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * After OSC is enabled and starts generating the clocks, the configurations
+ * such as low power and frequency range, must not be changed.
+ */
+/*!
+ * @name Constants and macros for entire OSC_CR register
+ */
+/*@{*/
+#define OSC_RD_CR(base)          (OSC_CR_REG(base))
+#define OSC_WR_CR(base, value)   (OSC_CR_REG(base) = (value))
+#define OSC_RMW_CR(base, mask, value) (OSC_WR_CR(base, (OSC_RD_CR(base) & ~(mask)) | (value)))
+#define OSC_SET_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) |  (value)))
+#define OSC_CLR_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) & ~(value)))
+#define OSC_TOG_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual OSC_CR bitfields
+ */
+
+/*!
+ * @name Register OSC_CR, field SC16P[0] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 16 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC16P field. */
+#define OSC_RD_CR_SC16P(base) ((OSC_CR_REG(base) & OSC_CR_SC16P_MASK) >> OSC_CR_SC16P_SHIFT)
+#define OSC_BRD_CR_SC16P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT))
+
+/*! @brief Set the SC16P field to a new value. */
+#define OSC_WR_CR_SC16P(base, value) (OSC_RMW_CR(base, OSC_CR_SC16P_MASK, OSC_CR_SC16P(value)))
+#define OSC_BWR_CR_SC16P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC8P[1] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 8 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC8P field. */
+#define OSC_RD_CR_SC8P(base) ((OSC_CR_REG(base) & OSC_CR_SC8P_MASK) >> OSC_CR_SC8P_SHIFT)
+#define OSC_BRD_CR_SC8P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT))
+
+/*! @brief Set the SC8P field to a new value. */
+#define OSC_WR_CR_SC8P(base, value) (OSC_RMW_CR(base, OSC_CR_SC8P_MASK, OSC_CR_SC8P(value)))
+#define OSC_BWR_CR_SC8P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC4P[2] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 4 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC4P field. */
+#define OSC_RD_CR_SC4P(base) ((OSC_CR_REG(base) & OSC_CR_SC4P_MASK) >> OSC_CR_SC4P_SHIFT)
+#define OSC_BRD_CR_SC4P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT))
+
+/*! @brief Set the SC4P field to a new value. */
+#define OSC_WR_CR_SC4P(base, value) (OSC_RMW_CR(base, OSC_CR_SC4P_MASK, OSC_CR_SC4P(value)))
+#define OSC_BWR_CR_SC4P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC2P[3] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 2 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC2P field. */
+#define OSC_RD_CR_SC2P(base) ((OSC_CR_REG(base) & OSC_CR_SC2P_MASK) >> OSC_CR_SC2P_SHIFT)
+#define OSC_BRD_CR_SC2P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT))
+
+/*! @brief Set the SC2P field to a new value. */
+#define OSC_WR_CR_SC2P(base, value) (OSC_RMW_CR(base, OSC_CR_SC2P_MASK, OSC_CR_SC2P(value)))
+#define OSC_BWR_CR_SC2P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field EREFSTEN[5] (RW)
+ *
+ * Controls whether or not the external reference clock (OSCERCLK) remains
+ * enabled when MCU enters Stop mode.
+ *
+ * Values:
+ * - 0b0 - External reference clock is disabled in Stop mode.
+ * - 0b1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
+ *     before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_EREFSTEN field. */
+#define OSC_RD_CR_EREFSTEN(base) ((OSC_CR_REG(base) & OSC_CR_EREFSTEN_MASK) >> OSC_CR_EREFSTEN_SHIFT)
+#define OSC_BRD_CR_EREFSTEN(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT))
+
+/*! @brief Set the EREFSTEN field to a new value. */
+#define OSC_WR_CR_EREFSTEN(base, value) (OSC_RMW_CR(base, OSC_CR_EREFSTEN_MASK, OSC_CR_EREFSTEN(value)))
+#define OSC_BWR_CR_EREFSTEN(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field ERCLKEN[7] (RW)
+ *
+ * Enables external reference clock (OSCERCLK).
+ *
+ * Values:
+ * - 0b0 - External reference clock is inactive.
+ * - 0b1 - External reference clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_ERCLKEN field. */
+#define OSC_RD_CR_ERCLKEN(base) ((OSC_CR_REG(base) & OSC_CR_ERCLKEN_MASK) >> OSC_CR_ERCLKEN_SHIFT)
+#define OSC_BRD_CR_ERCLKEN(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT))
+
+/*! @brief Set the ERCLKEN field to a new value. */
+#define OSC_WR_CR_ERCLKEN(base, value) (OSC_RMW_CR(base, OSC_CR_ERCLKEN_MASK, OSC_CR_ERCLKEN(value)))
+#define OSC_BWR_CR_ERCLKEN(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PDB
+ *
+ * Programmable Delay Block
+ *
+ * Registers defined in this header file:
+ * - PDB_SC - Status and Control register
+ * - PDB_MOD - Modulus register
+ * - PDB_CNT - Counter register
+ * - PDB_IDLY - Interrupt Delay register
+ * - PDB_C1 - Channel n Control register 1
+ * - PDB_S - Channel n Status register
+ * - PDB_DLY - Channel n Delay 0 register
+ * - PDB_INTC - DAC Interval Trigger n Control register
+ * - PDB_INT - DAC Interval n register
+ * - PDB_POEN - Pulse-Out n Enable register
+ * - PDB_PODLY - Pulse-Out n Delay register
+ */
+
+#define PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */
+#define PDB0_IDX (0U) /*!< Instance number for PDB0. */
+
+/*******************************************************************************
+ * PDB_SC - Status and Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_SC - Status and Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_SC register
+ */
+/*@{*/
+#define PDB_RD_SC(base)          (PDB_SC_REG(base))
+#define PDB_WR_SC(base, value)   (PDB_SC_REG(base) = (value))
+#define PDB_RMW_SC(base, mask, value) (PDB_WR_SC(base, (PDB_RD_SC(base) & ~(mask)) | (value)))
+#define PDB_SET_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) |  (value)))
+#define PDB_CLR_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) & ~(value)))
+#define PDB_TOG_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_SC bitfields
+ */
+
+/*!
+ * @name Register PDB_SC, field LDOK[0] (RW)
+ *
+ * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
+ * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
+ * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
+ * written to the LDOK field, the values in the buffers of above registers are
+ * not effective and the buffers cannot be written until the values in buffers are
+ * loaded into their internal registers. LDOK can be written only when PDBEN is
+ * set or it can be written at the same time with PDBEN being written to 1. It is
+ * automatically cleared when the values in buffers are loaded into the internal
+ * registers or the PDBEN is cleared. Writing 0 to it has no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_LDOK field. */
+#define PDB_RD_SC_LDOK(base) ((PDB_SC_REG(base) & PDB_SC_LDOK_MASK) >> PDB_SC_LDOK_SHIFT)
+#define PDB_BRD_SC_LDOK(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_LDOK_SHIFT))
+
+/*! @brief Set the LDOK field to a new value. */
+#define PDB_WR_SC_LDOK(base, value) (PDB_RMW_SC(base, PDB_SC_LDOK_MASK, PDB_SC_LDOK(value)))
+#define PDB_BWR_SC_LDOK(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_LDOK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field CONT[1] (RW)
+ *
+ * Enables the PDB operation in Continuous mode.
+ *
+ * Values:
+ * - 0b0 - PDB operation in One-Shot mode
+ * - 0b1 - PDB operation in Continuous mode
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_CONT field. */
+#define PDB_RD_SC_CONT(base) ((PDB_SC_REG(base) & PDB_SC_CONT_MASK) >> PDB_SC_CONT_SHIFT)
+#define PDB_BRD_SC_CONT(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_CONT_SHIFT))
+
+/*! @brief Set the CONT field to a new value. */
+#define PDB_WR_SC_CONT(base, value) (PDB_RMW_SC(base, PDB_SC_CONT_MASK, PDB_SC_CONT(value)))
+#define PDB_BWR_SC_CONT(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_CONT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field MULT[3:2] (RW)
+ *
+ * Selects the multiplication factor of the prescaler divider for the counter
+ * clock.
+ *
+ * Values:
+ * - 0b00 - Multiplication factor is 1.
+ * - 0b01 - Multiplication factor is 10.
+ * - 0b10 - Multiplication factor is 20.
+ * - 0b11 - Multiplication factor is 40.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_MULT field. */
+#define PDB_RD_SC_MULT(base) ((PDB_SC_REG(base) & PDB_SC_MULT_MASK) >> PDB_SC_MULT_SHIFT)
+#define PDB_BRD_SC_MULT(base) (PDB_RD_SC_MULT(base))
+
+/*! @brief Set the MULT field to a new value. */
+#define PDB_WR_SC_MULT(base, value) (PDB_RMW_SC(base, PDB_SC_MULT_MASK, PDB_SC_MULT(value)))
+#define PDB_BWR_SC_MULT(base, value) (PDB_WR_SC_MULT(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBIE[5] (RW)
+ *
+ * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
+ * generates a PDB interrupt.
+ *
+ * Values:
+ * - 0b0 - PDB interrupt disabled.
+ * - 0b1 - PDB interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBIE field. */
+#define PDB_RD_SC_PDBIE(base) ((PDB_SC_REG(base) & PDB_SC_PDBIE_MASK) >> PDB_SC_PDBIE_SHIFT)
+#define PDB_BRD_SC_PDBIE(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIE_SHIFT))
+
+/*! @brief Set the PDBIE field to a new value. */
+#define PDB_WR_SC_PDBIE(base, value) (PDB_RMW_SC(base, PDB_SC_PDBIE_MASK, PDB_SC_PDBIE(value)))
+#define PDB_BWR_SC_PDBIE(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBIF[6] (RW)
+ *
+ * This field is set when the counter value is equal to the IDLY register.
+ * Writing zero clears this field.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBIF field. */
+#define PDB_RD_SC_PDBIF(base) ((PDB_SC_REG(base) & PDB_SC_PDBIF_MASK) >> PDB_SC_PDBIF_SHIFT)
+#define PDB_BRD_SC_PDBIF(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIF_SHIFT))
+
+/*! @brief Set the PDBIF field to a new value. */
+#define PDB_WR_SC_PDBIF(base, value) (PDB_RMW_SC(base, PDB_SC_PDBIF_MASK, PDB_SC_PDBIF(value)))
+#define PDB_BWR_SC_PDBIF(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - PDB disabled. Counter is off.
+ * - 0b1 - PDB enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBEN field. */
+#define PDB_RD_SC_PDBEN(base) ((PDB_SC_REG(base) & PDB_SC_PDBEN_MASK) >> PDB_SC_PDBEN_SHIFT)
+#define PDB_BRD_SC_PDBEN(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEN_SHIFT))
+
+/*! @brief Set the PDBEN field to a new value. */
+#define PDB_WR_SC_PDBEN(base, value) (PDB_RMW_SC(base, PDB_SC_PDBEN_MASK, PDB_SC_PDBEN(value)))
+#define PDB_BWR_SC_PDBEN(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field TRGSEL[11:8] (RW)
+ *
+ * Selects the trigger input source for the PDB. The trigger input source can be
+ * internal or external (EXTRG pin), or the software trigger. Refer to chip
+ * configuration details for the actual PDB input trigger connections.
+ *
+ * Values:
+ * - 0b0000 - Trigger-In 0 is selected.
+ * - 0b0001 - Trigger-In 1 is selected.
+ * - 0b0010 - Trigger-In 2 is selected.
+ * - 0b0011 - Trigger-In 3 is selected.
+ * - 0b0100 - Trigger-In 4 is selected.
+ * - 0b0101 - Trigger-In 5 is selected.
+ * - 0b0110 - Trigger-In 6 is selected.
+ * - 0b0111 - Trigger-In 7 is selected.
+ * - 0b1000 - Trigger-In 8 is selected.
+ * - 0b1001 - Trigger-In 9 is selected.
+ * - 0b1010 - Trigger-In 10 is selected.
+ * - 0b1011 - Trigger-In 11 is selected.
+ * - 0b1100 - Trigger-In 12 is selected.
+ * - 0b1101 - Trigger-In 13 is selected.
+ * - 0b1110 - Trigger-In 14 is selected.
+ * - 0b1111 - Software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_TRGSEL field. */
+#define PDB_RD_SC_TRGSEL(base) ((PDB_SC_REG(base) & PDB_SC_TRGSEL_MASK) >> PDB_SC_TRGSEL_SHIFT)
+#define PDB_BRD_SC_TRGSEL(base) (PDB_RD_SC_TRGSEL(base))
+
+/*! @brief Set the TRGSEL field to a new value. */
+#define PDB_WR_SC_TRGSEL(base, value) (PDB_RMW_SC(base, PDB_SC_TRGSEL_MASK, PDB_SC_TRGSEL(value)))
+#define PDB_BWR_SC_TRGSEL(base, value) (PDB_WR_SC_TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PRESCALER[14:12] (RW)
+ *
+ * Values:
+ * - 0b000 - Counting uses the peripheral clock divided by multiplication factor
+ *     selected by MULT.
+ * - 0b001 - Counting uses the peripheral clock divided by twice of the
+ *     multiplication factor selected by MULT.
+ * - 0b010 - Counting uses the peripheral clock divided by four times of the
+ *     multiplication factor selected by MULT.
+ * - 0b011 - Counting uses the peripheral clock divided by eight times of the
+ *     multiplication factor selected by MULT.
+ * - 0b100 - Counting uses the peripheral clock divided by 16 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b101 - Counting uses the peripheral clock divided by 32 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b110 - Counting uses the peripheral clock divided by 64 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b111 - Counting uses the peripheral clock divided by 128 times of the
+ *     multiplication factor selected by MULT.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PRESCALER field. */
+#define PDB_RD_SC_PRESCALER(base) ((PDB_SC_REG(base) & PDB_SC_PRESCALER_MASK) >> PDB_SC_PRESCALER_SHIFT)
+#define PDB_BRD_SC_PRESCALER(base) (PDB_RD_SC_PRESCALER(base))
+
+/*! @brief Set the PRESCALER field to a new value. */
+#define PDB_WR_SC_PRESCALER(base, value) (PDB_RMW_SC(base, PDB_SC_PRESCALER_MASK, PDB_SC_PRESCALER(value)))
+#define PDB_BWR_SC_PRESCALER(base, value) (PDB_WR_SC_PRESCALER(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field DMAEN[15] (RW)
+ *
+ * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
+ * interrupt.
+ *
+ * Values:
+ * - 0b0 - DMA disabled.
+ * - 0b1 - DMA enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_DMAEN field. */
+#define PDB_RD_SC_DMAEN(base) ((PDB_SC_REG(base) & PDB_SC_DMAEN_MASK) >> PDB_SC_DMAEN_SHIFT)
+#define PDB_BRD_SC_DMAEN(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define PDB_WR_SC_DMAEN(base, value) (PDB_RMW_SC(base, PDB_SC_DMAEN_MASK, PDB_SC_DMAEN(value)))
+#define PDB_BWR_SC_DMAEN(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field SWTRIG[16] (WORZ)
+ *
+ * When PDB is enabled and the software trigger is selected as the trigger input
+ * source, writing 1 to this field resets and restarts the counter. Writing 0 to
+ * this field has no effect. Reading this field results 0.
+ */
+/*@{*/
+/*! @brief Set the SWTRIG field to a new value. */
+#define PDB_WR_SC_SWTRIG(base, value) (PDB_RMW_SC(base, PDB_SC_SWTRIG_MASK, PDB_SC_SWTRIG(value)))
+#define PDB_BWR_SC_SWTRIG(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_SWTRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBEIE[17] (RW)
+ *
+ * Enables the PDB sequence error interrupt. When this field is set, any of the
+ * PDB channel sequence error flags generates a PDB sequence error interrupt.
+ *
+ * Values:
+ * - 0b0 - PDB sequence error interrupt disabled.
+ * - 0b1 - PDB sequence error interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBEIE field. */
+#define PDB_RD_SC_PDBEIE(base) ((PDB_SC_REG(base) & PDB_SC_PDBEIE_MASK) >> PDB_SC_PDBEIE_SHIFT)
+#define PDB_BRD_SC_PDBEIE(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEIE_SHIFT))
+
+/*! @brief Set the PDBEIE field to a new value. */
+#define PDB_WR_SC_PDBEIE(base, value) (PDB_RMW_SC(base, PDB_SC_PDBEIE_MASK, PDB_SC_PDBEIE(value)))
+#define PDB_BWR_SC_PDBEIE(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field LDMOD[19:18] (RW)
+ *
+ * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
+ * after 1 is written to LDOK.
+ *
+ * Values:
+ * - 0b00 - The internal registers are loaded with the values from their buffers
+ *     immediately after 1 is written to LDOK.
+ * - 0b01 - The internal registers are loaded with the values from their buffers
+ *     when the PDB counter reaches the MOD register value after 1 is written to
+ *     LDOK.
+ * - 0b10 - The internal registers are loaded with the values from their buffers
+ *     when a trigger input event is detected after 1 is written to LDOK.
+ * - 0b11 - The internal registers are loaded with the values from their buffers
+ *     when either the PDB counter reaches the MOD register value or a trigger
+ *     input event is detected, after 1 is written to LDOK.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_LDMOD field. */
+#define PDB_RD_SC_LDMOD(base) ((PDB_SC_REG(base) & PDB_SC_LDMOD_MASK) >> PDB_SC_LDMOD_SHIFT)
+#define PDB_BRD_SC_LDMOD(base) (PDB_RD_SC_LDMOD(base))
+
+/*! @brief Set the LDMOD field to a new value. */
+#define PDB_WR_SC_LDMOD(base, value) (PDB_RMW_SC(base, PDB_SC_LDMOD_MASK, PDB_SC_LDMOD(value)))
+#define PDB_BWR_SC_LDMOD(base, value) (PDB_WR_SC_LDMOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_MOD - Modulus register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_MOD - Modulus register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+/*!
+ * @name Constants and macros for entire PDB_MOD register
+ */
+/*@{*/
+#define PDB_RD_MOD(base)         (PDB_MOD_REG(base))
+#define PDB_WR_MOD(base, value)  (PDB_MOD_REG(base) = (value))
+#define PDB_RMW_MOD(base, mask, value) (PDB_WR_MOD(base, (PDB_RD_MOD(base) & ~(mask)) | (value)))
+#define PDB_SET_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) |  (value)))
+#define PDB_CLR_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) & ~(value)))
+#define PDB_TOG_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_MOD bitfields
+ */
+
+/*!
+ * @name Register PDB_MOD, field MOD[15:0] (RW)
+ *
+ * Specifies the period of the counter. When the counter reaches this value, it
+ * will be reset back to zero. If the PDB is in Continuous mode, the count begins
+ * anew. Reading this field returns the value of the internal register that is
+ * effective for the current cycle of PDB.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_MOD_MOD field. */
+#define PDB_RD_MOD_MOD(base) ((PDB_MOD_REG(base) & PDB_MOD_MOD_MASK) >> PDB_MOD_MOD_SHIFT)
+#define PDB_BRD_MOD_MOD(base) (PDB_RD_MOD_MOD(base))
+
+/*! @brief Set the MOD field to a new value. */
+#define PDB_WR_MOD_MOD(base, value) (PDB_RMW_MOD(base, PDB_MOD_MOD_MASK, PDB_MOD_MOD(value)))
+#define PDB_BWR_MOD_MOD(base, value) (PDB_WR_MOD_MOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_CNT - Counter register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_CNT - Counter register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_CNT register
+ */
+/*@{*/
+#define PDB_RD_CNT(base)         (PDB_CNT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_CNT bitfields
+ */
+
+/*!
+ * @name Register PDB_CNT, field CNT[15:0] (RO)
+ *
+ * Contains the current value of the counter.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_CNT_CNT field. */
+#define PDB_RD_CNT_CNT(base) ((PDB_CNT_REG(base) & PDB_CNT_CNT_MASK) >> PDB_CNT_CNT_SHIFT)
+#define PDB_BRD_CNT_CNT(base) (PDB_RD_CNT_CNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_IDLY - Interrupt Delay register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_IDLY - Interrupt Delay register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+/*!
+ * @name Constants and macros for entire PDB_IDLY register
+ */
+/*@{*/
+#define PDB_RD_IDLY(base)        (PDB_IDLY_REG(base))
+#define PDB_WR_IDLY(base, value) (PDB_IDLY_REG(base) = (value))
+#define PDB_RMW_IDLY(base, mask, value) (PDB_WR_IDLY(base, (PDB_RD_IDLY(base) & ~(mask)) | (value)))
+#define PDB_SET_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) |  (value)))
+#define PDB_CLR_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) & ~(value)))
+#define PDB_TOG_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_IDLY bitfields
+ */
+
+/*!
+ * @name Register PDB_IDLY, field IDLY[15:0] (RW)
+ *
+ * Specifies the delay value to schedule the PDB interrupt. It can be used to
+ * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
+ * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
+ * this field returns the value of internal register that is effective for the
+ * current cycle of the PDB.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_IDLY_IDLY field. */
+#define PDB_RD_IDLY_IDLY(base) ((PDB_IDLY_REG(base) & PDB_IDLY_IDLY_MASK) >> PDB_IDLY_IDLY_SHIFT)
+#define PDB_BRD_IDLY_IDLY(base) (PDB_RD_IDLY_IDLY(base))
+
+/*! @brief Set the IDLY field to a new value. */
+#define PDB_WR_IDLY_IDLY(base, value) (PDB_RMW_IDLY(base, PDB_IDLY_IDLY_MASK, PDB_IDLY_IDLY(value)))
+#define PDB_BWR_IDLY_IDLY(base, value) (PDB_WR_IDLY_IDLY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_C1 - Channel n Control register 1
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_C1 - Channel n Control register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PDB channel has one control register, CHnC1. The bits in this register
+ * control the functionality of each PDB channel operation.
+ */
+/*!
+ * @name Constants and macros for entire PDB_C1 register
+ */
+/*@{*/
+#define PDB_RD_C1(base, index)   (PDB_C1_REG(base, index))
+#define PDB_WR_C1(base, index, value) (PDB_C1_REG(base, index) = (value))
+#define PDB_RMW_C1(base, index, mask, value) (PDB_WR_C1(base, index, (PDB_RD_C1(base, index) & ~(mask)) | (value)))
+#define PDB_SET_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) |  (value)))
+#define PDB_CLR_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) & ~(value)))
+#define PDB_TOG_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_C1 bitfields
+ */
+
+/*!
+ * @name Register PDB_C1, field EN[7:0] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
+ * bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger disabled.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_EN field. */
+#define PDB_RD_C1_EN(base, index) ((PDB_C1_REG(base, index) & PDB_C1_EN_MASK) >> PDB_C1_EN_SHIFT)
+#define PDB_BRD_C1_EN(base, index) (PDB_RD_C1_EN(base, index))
+
+/*! @brief Set the EN field to a new value. */
+#define PDB_WR_C1_EN(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_EN_MASK, PDB_C1_EN(value)))
+#define PDB_BWR_C1_EN(base, index, value) (PDB_WR_C1_EN(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_C1, field TOS[15:8] (RW)
+ *
+ * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
+ * implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger is in bypassed mode.
+ *     The pre-trigger asserts one peripheral clock cycle after a rising edge is
+ *     detected on selected trigger input source or software trigger is selected
+ *     and SWTRIG is written with 1.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger asserts when the
+ *     counter reaches the channel delay register and one peripheral clock cycle after
+ *     a rising edge is detected on selected trigger input source or software
+ *     trigger is selected and SETRIG is written with 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_TOS field. */
+#define PDB_RD_C1_TOS(base, index) ((PDB_C1_REG(base, index) & PDB_C1_TOS_MASK) >> PDB_C1_TOS_SHIFT)
+#define PDB_BRD_C1_TOS(base, index) (PDB_RD_C1_TOS(base, index))
+
+/*! @brief Set the TOS field to a new value. */
+#define PDB_WR_C1_TOS(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_TOS_MASK, PDB_C1_TOS(value)))
+#define PDB_BWR_C1_TOS(base, index, value) (PDB_WR_C1_TOS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_C1, field BB[23:16] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
+ * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
+ * enables the ADC conversions complete to trigger the next PDB channel
+ * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
+ * set of configuration and results registers. Application code must only enable
+ * the back-to-back operation of the PDB pre-triggers at the leading of the
+ * back-to-back connection chain.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger back-to-back operation
+ *     disabled.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger back-to-back operation
+ *     enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_BB field. */
+#define PDB_RD_C1_BB(base, index) ((PDB_C1_REG(base, index) & PDB_C1_BB_MASK) >> PDB_C1_BB_SHIFT)
+#define PDB_BRD_C1_BB(base, index) (PDB_RD_C1_BB(base, index))
+
+/*! @brief Set the BB field to a new value. */
+#define PDB_WR_C1_BB(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_BB_MASK, PDB_C1_BB(value)))
+#define PDB_BWR_C1_BB(base, index, value) (PDB_WR_C1_BB(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_S - Channel n Status register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_S - Channel n Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_S register
+ */
+/*@{*/
+#define PDB_RD_S(base, index)    (PDB_S_REG(base, index))
+#define PDB_WR_S(base, index, value) (PDB_S_REG(base, index) = (value))
+#define PDB_RMW_S(base, index, mask, value) (PDB_WR_S(base, index, (PDB_RD_S(base, index) & ~(mask)) | (value)))
+#define PDB_SET_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) |  (value)))
+#define PDB_CLR_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) & ~(value)))
+#define PDB_TOG_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_S bitfields
+ */
+
+/*!
+ * @name Register PDB_S, field ERR[7:0] (RW)
+ *
+ * Only the lower M bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - Sequence error not detected on PDB channel's corresponding
+ *     pre-trigger.
+ * - 0b00000001 - Sequence error detected on PDB channel's corresponding
+ *     pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from
+ *     PDB channel n. When one conversion, which is triggered by one of the
+ *     pre-triggers from PDB channel n, is in progress, new trigger from PDB
+ *     channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is
+ *     set. Writing 0's to clear the sequence error flags.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_S_ERR field. */
+#define PDB_RD_S_ERR(base, index) ((PDB_S_REG(base, index) & PDB_S_ERR_MASK) >> PDB_S_ERR_SHIFT)
+#define PDB_BRD_S_ERR(base, index) (PDB_RD_S_ERR(base, index))
+
+/*! @brief Set the ERR field to a new value. */
+#define PDB_WR_S_ERR(base, index, value) (PDB_RMW_S(base, index, PDB_S_ERR_MASK, PDB_S_ERR(value)))
+#define PDB_BWR_S_ERR(base, index, value) (PDB_WR_S_ERR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_S, field CF[23:16] (RW)
+ *
+ * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
+ * clear these bits.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_S_CF field. */
+#define PDB_RD_S_CF(base, index) ((PDB_S_REG(base, index) & PDB_S_CF_MASK) >> PDB_S_CF_SHIFT)
+#define PDB_BRD_S_CF(base, index) (PDB_RD_S_CF(base, index))
+
+/*! @brief Set the CF field to a new value. */
+#define PDB_WR_S_CF(base, index, value) (PDB_RMW_S(base, index, PDB_S_CF_MASK, PDB_S_CF(value)))
+#define PDB_BWR_S_CF(base, index, value) (PDB_WR_S_CF(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_DLY - Channel n Delay 0 register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_DLY - Channel n Delay 0 register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_DLY register
+ */
+/*@{*/
+#define PDB_RD_DLY(base, index, index2) (PDB_DLY_REG(base, index, index2))
+#define PDB_WR_DLY(base, index, index2, value) (PDB_DLY_REG(base, index, index2) = (value))
+#define PDB_RMW_DLY(base, index, index2, mask, value) (PDB_WR_DLY(base, index, index2, (PDB_RD_DLY(base, index, index2) & ~(mask)) | (value)))
+#define PDB_SET_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) |  (value)))
+#define PDB_CLR_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) & ~(value)))
+#define PDB_TOG_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_DLY bitfields
+ */
+
+/*!
+ * @name Register PDB_DLY, field DLY[15:0] (RW)
+ *
+ * Specifies the delay value for the channel's corresponding pre-trigger. The
+ * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
+ * the value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_DLY_DLY field. */
+#define PDB_RD_DLY_DLY(base, index, index2) ((PDB_DLY_REG(base, index, index2) & PDB_DLY_DLY_MASK) >> PDB_DLY_DLY_SHIFT)
+#define PDB_BRD_DLY_DLY(base, index, index2) (PDB_RD_DLY_DLY(base, index, index2))
+
+/*! @brief Set the DLY field to a new value. */
+#define PDB_WR_DLY_DLY(base, index, index2, value) (PDB_RMW_DLY(base, index, index2, PDB_DLY_DLY_MASK, PDB_DLY_DLY(value)))
+#define PDB_BWR_DLY_DLY(base, index, index2, value) (PDB_WR_DLY_DLY(base, index, index2, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_INTC - DAC Interval Trigger n Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_INTC - DAC Interval Trigger n Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_INTC register
+ */
+/*@{*/
+#define PDB_RD_INTC(base, index) (PDB_INTC_REG(base, index))
+#define PDB_WR_INTC(base, index, value) (PDB_INTC_REG(base, index) = (value))
+#define PDB_RMW_INTC(base, index, mask, value) (PDB_WR_INTC(base, index, (PDB_RD_INTC(base, index) & ~(mask)) | (value)))
+#define PDB_SET_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) |  (value)))
+#define PDB_CLR_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) & ~(value)))
+#define PDB_TOG_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_INTC bitfields
+ */
+
+/*!
+ * @name Register PDB_INTC, field TOE[0] (RW)
+ *
+ * This bit enables the DAC interval trigger.
+ *
+ * Values:
+ * - 0b0 - DAC interval trigger disabled.
+ * - 0b1 - DAC interval trigger enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INTC_TOE field. */
+#define PDB_RD_INTC_TOE(base, index) ((PDB_INTC_REG(base, index) & PDB_INTC_TOE_MASK) >> PDB_INTC_TOE_SHIFT)
+#define PDB_BRD_INTC_TOE(base, index) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_TOE_SHIFT))
+
+/*! @brief Set the TOE field to a new value. */
+#define PDB_WR_INTC_TOE(base, index, value) (PDB_RMW_INTC(base, index, PDB_INTC_TOE_MASK, PDB_INTC_TOE(value)))
+#define PDB_BWR_INTC_TOE(base, index, value) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_TOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_INTC, field EXT[1] (RW)
+ *
+ * Enables the external trigger for DAC interval counter.
+ *
+ * Values:
+ * - 0b0 - DAC external trigger input disabled. DAC interval counter is reset
+ *     and counting starts when a rising edge is detected on selected trigger input
+ *     source or software trigger is selected and SWTRIG is written with 1.
+ * - 0b1 - DAC external trigger input enabled. DAC interval counter is bypassed
+ *     and DAC external trigger input triggers the DAC interval trigger.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INTC_EXT field. */
+#define PDB_RD_INTC_EXT(base, index) ((PDB_INTC_REG(base, index) & PDB_INTC_EXT_MASK) >> PDB_INTC_EXT_SHIFT)
+#define PDB_BRD_INTC_EXT(base, index) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_EXT_SHIFT))
+
+/*! @brief Set the EXT field to a new value. */
+#define PDB_WR_INTC_EXT(base, index, value) (PDB_RMW_INTC(base, index, PDB_INTC_EXT_MASK, PDB_INTC_EXT(value)))
+#define PDB_BWR_INTC_EXT(base, index, value) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_EXT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_INT - DAC Interval n register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_INT - DAC Interval n register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_INT register
+ */
+/*@{*/
+#define PDB_RD_INT(base, index)  (PDB_INT_REG(base, index))
+#define PDB_WR_INT(base, index, value) (PDB_INT_REG(base, index) = (value))
+#define PDB_RMW_INT(base, index, mask, value) (PDB_WR_INT(base, index, (PDB_RD_INT(base, index) & ~(mask)) | (value)))
+#define PDB_SET_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) |  (value)))
+#define PDB_CLR_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) & ~(value)))
+#define PDB_TOG_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_INT bitfields
+ */
+
+/*!
+ * @name Register PDB_INT, field INT[15:0] (RW)
+ *
+ * Specifies the interval value for DAC interval trigger. DAC interval trigger
+ * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
+ * Reading this field returns the value of internal register that is effective
+ * for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INT_INT field. */
+#define PDB_RD_INT_INT(base, index) ((PDB_INT_REG(base, index) & PDB_INT_INT_MASK) >> PDB_INT_INT_SHIFT)
+#define PDB_BRD_INT_INT(base, index) (PDB_RD_INT_INT(base, index))
+
+/*! @brief Set the INT field to a new value. */
+#define PDB_WR_INT_INT(base, index, value) (PDB_RMW_INT(base, index, PDB_INT_INT_MASK, PDB_INT_INT(value)))
+#define PDB_BWR_INT_INT(base, index, value) (PDB_WR_INT_INT(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_POEN - Pulse-Out n Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_POEN - Pulse-Out n Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_POEN register
+ */
+/*@{*/
+#define PDB_RD_POEN(base)        (PDB_POEN_REG(base))
+#define PDB_WR_POEN(base, value) (PDB_POEN_REG(base) = (value))
+#define PDB_RMW_POEN(base, mask, value) (PDB_WR_POEN(base, (PDB_RD_POEN(base) & ~(mask)) | (value)))
+#define PDB_SET_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) |  (value)))
+#define PDB_CLR_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) & ~(value)))
+#define PDB_TOG_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_POEN bitfields
+ */
+
+/*!
+ * @name Register PDB_POEN, field POEN[7:0] (RW)
+ *
+ * Enables the pulse output. Only lower Y bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB Pulse-Out disabled
+ * - 0b00000001 - PDB Pulse-Out enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_POEN_POEN field. */
+#define PDB_RD_POEN_POEN(base) ((PDB_POEN_REG(base) & PDB_POEN_POEN_MASK) >> PDB_POEN_POEN_SHIFT)
+#define PDB_BRD_POEN_POEN(base) (PDB_RD_POEN_POEN(base))
+
+/*! @brief Set the POEN field to a new value. */
+#define PDB_WR_POEN_POEN(base, value) (PDB_RMW_POEN(base, PDB_POEN_POEN_MASK, PDB_POEN_POEN(value)))
+#define PDB_BWR_POEN_POEN(base, value) (PDB_WR_POEN_POEN(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_PODLY - Pulse-Out n Delay register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_PODLY - Pulse-Out n Delay register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_PODLY register
+ */
+/*@{*/
+#define PDB_RD_PODLY(base, index) (PDB_PODLY_REG(base, index))
+#define PDB_WR_PODLY(base, index, value) (PDB_PODLY_REG(base, index) = (value))
+#define PDB_RMW_PODLY(base, index, mask, value) (PDB_WR_PODLY(base, index, (PDB_RD_PODLY(base, index) & ~(mask)) | (value)))
+#define PDB_SET_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) |  (value)))
+#define PDB_CLR_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) & ~(value)))
+#define PDB_TOG_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_PODLY bitfields
+ */
+
+/*!
+ * @name Register PDB_PODLY, field DLY2[15:0] (RW)
+ *
+ * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
+ * low when the PDB counter is equal to the DLY2. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_PODLY_DLY2 field. */
+#define PDB_RD_PODLY_DLY2(base, index) ((PDB_PODLY_REG(base, index) & PDB_PODLY_DLY2_MASK) >> PDB_PODLY_DLY2_SHIFT)
+#define PDB_BRD_PODLY_DLY2(base, index) (PDB_RD_PODLY_DLY2(base, index))
+
+/*! @brief Set the DLY2 field to a new value. */
+#define PDB_WR_PODLY_DLY2(base, index, value) (PDB_RMW_PODLY(base, index, PDB_PODLY_DLY2_MASK, PDB_PODLY_DLY2(value)))
+#define PDB_BWR_PODLY_DLY2(base, index, value) (PDB_WR_PODLY_DLY2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_PODLY, field DLY1[31:16] (RW)
+ *
+ * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
+ * high when the PDB counter is equal to the DLY1. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_PODLY_DLY1 field. */
+#define PDB_RD_PODLY_DLY1(base, index) ((PDB_PODLY_REG(base, index) & PDB_PODLY_DLY1_MASK) >> PDB_PODLY_DLY1_SHIFT)
+#define PDB_BRD_PODLY_DLY1(base, index) (PDB_RD_PODLY_DLY1(base, index))
+
+/*! @brief Set the DLY1 field to a new value. */
+#define PDB_WR_PODLY_DLY1(base, index, value) (PDB_RMW_PODLY(base, index, PDB_PODLY_DLY1_MASK, PDB_PODLY_DLY1(value)))
+#define PDB_BWR_PODLY_DLY1(base, index, value) (PDB_WR_PODLY_DLY1(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 PIT
+ *
+ * Periodic Interrupt Timer
+ *
+ * Registers defined in this header file:
+ * - PIT_MCR - PIT Module Control Register
+ * - PIT_LDVAL - Timer Load Value Register
+ * - PIT_CVAL - Current Timer Value Register
+ * - PIT_TCTRL - Timer Control Register
+ * - PIT_TFLG - Timer Flag Register
+ */
+
+#define PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
+#define PIT_IDX (0U) /*!< Instance number for PIT. */
+
+/*******************************************************************************
+ * PIT_MCR - PIT Module Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_MCR - PIT Module Control Register (RW)
+ *
+ * Reset value: 0x00000006U
+ *
+ * This register enables or disables the PIT timer clocks and controls the
+ * timers when the PIT enters the Debug mode.
+ */
+/*!
+ * @name Constants and macros for entire PIT_MCR register
+ */
+/*@{*/
+#define PIT_RD_MCR(base)         (PIT_MCR_REG(base))
+#define PIT_WR_MCR(base, value)  (PIT_MCR_REG(base) = (value))
+#define PIT_RMW_MCR(base, mask, value) (PIT_WR_MCR(base, (PIT_RD_MCR(base) & ~(mask)) | (value)))
+#define PIT_SET_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) |  (value)))
+#define PIT_CLR_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) & ~(value)))
+#define PIT_TOG_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_MCR bitfields
+ */
+
+/*!
+ * @name Register PIT_MCR, field FRZ[0] (RW)
+ *
+ * Allows the timers to be stopped when the device enters the Debug mode.
+ *
+ * Values:
+ * - 0b0 - Timers continue to run in Debug mode.
+ * - 0b1 - Timers are stopped in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_FRZ field. */
+#define PIT_RD_MCR_FRZ(base) ((PIT_MCR_REG(base) & PIT_MCR_FRZ_MASK) >> PIT_MCR_FRZ_SHIFT)
+#define PIT_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define PIT_WR_MCR_FRZ(base, value) (PIT_RMW_MCR(base, PIT_MCR_FRZ_MASK, PIT_MCR_FRZ(value)))
+#define PIT_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_MCR, field MDIS[1] (RW)
+ *
+ * Disables the standard timers. This field must be enabled before any other
+ * setup is done.
+ *
+ * Values:
+ * - 0b0 - Clock for standard PIT timers is enabled.
+ * - 0b1 - Clock for standard PIT timers is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_MDIS field. */
+#define PIT_RD_MCR_MDIS(base) ((PIT_MCR_REG(base) & PIT_MCR_MDIS_MASK) >> PIT_MCR_MDIS_SHIFT)
+#define PIT_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define PIT_WR_MCR_MDIS(base, value) (PIT_RMW_MCR(base, PIT_MCR_MDIS_MASK, PIT_MCR_MDIS(value)))
+#define PIT_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_LDVAL - Timer Load Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_LDVAL - Timer Load Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers select the timeout period for the timer interrupts.
+ */
+/*!
+ * @name Constants and macros for entire PIT_LDVAL register
+ */
+/*@{*/
+#define PIT_RD_LDVAL(base, index) (PIT_LDVAL_REG(base, index))
+#define PIT_WR_LDVAL(base, index, value) (PIT_LDVAL_REG(base, index) = (value))
+#define PIT_RMW_LDVAL(base, index, mask, value) (PIT_WR_LDVAL(base, index, (PIT_RD_LDVAL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) |  (value)))
+#define PIT_CLR_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) & ~(value)))
+#define PIT_TOG_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_CVAL - Current Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_CVAL - Current Timer Value Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the current timer position.
+ */
+/*!
+ * @name Constants and macros for entire PIT_CVAL register
+ */
+/*@{*/
+#define PIT_RD_CVAL(base, index) (PIT_CVAL_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TCTRL - Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TCTRL - Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the control bits for each timer.
+ */
+/*!
+ * @name Constants and macros for entire PIT_TCTRL register
+ */
+/*@{*/
+#define PIT_RD_TCTRL(base, index) (PIT_TCTRL_REG(base, index))
+#define PIT_WR_TCTRL(base, index, value) (PIT_TCTRL_REG(base, index) = (value))
+#define PIT_RMW_TCTRL(base, index, mask, value) (PIT_WR_TCTRL(base, index, (PIT_RD_TCTRL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) |  (value)))
+#define PIT_CLR_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) & ~(value)))
+#define PIT_TOG_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TCTRL bitfields
+ */
+
+/*!
+ * @name Register PIT_TCTRL, field TEN[0] (RW)
+ *
+ * Enables or disables the timer.
+ *
+ * Values:
+ * - 0b0 - Timer n is disabled.
+ * - 0b1 - Timer n is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TEN field. */
+#define PIT_RD_TCTRL_TEN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TEN_MASK) >> PIT_TCTRL_TEN_SHIFT)
+#define PIT_BRD_TCTRL_TEN(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT))
+
+/*! @brief Set the TEN field to a new value. */
+#define PIT_WR_TCTRL_TEN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TEN_MASK, PIT_TCTRL_TEN(value)))
+#define PIT_BWR_TCTRL_TEN(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field TIE[1] (RW)
+ *
+ * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
+ * will immediately cause an interrupt event. To avoid this, the associated
+ * TFLGn[TIF] must be cleared first.
+ *
+ * Values:
+ * - 0b0 - Interrupt requests from Timer n are disabled.
+ * - 0b1 - Interrupt will be requested whenever TIF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TIE field. */
+#define PIT_RD_TCTRL_TIE(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TIE_MASK) >> PIT_TCTRL_TIE_SHIFT)
+#define PIT_BRD_TCTRL_TIE(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define PIT_WR_TCTRL_TIE(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TIE_MASK, PIT_TCTRL_TIE(value)))
+#define PIT_BWR_TCTRL_TIE(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field CHN[2] (RW)
+ *
+ * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
+ * Timer 0 cannot be chained.
+ *
+ * Values:
+ * - 0b0 - Timer is not chained.
+ * - 0b1 - Timer is chained to previous timer. For example, for Channel 2, if
+ *     this field is set, Timer 2 is chained to Timer 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_CHN field. */
+#define PIT_RD_TCTRL_CHN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_CHN_MASK) >> PIT_TCTRL_CHN_SHIFT)
+#define PIT_BRD_TCTRL_CHN(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT))
+
+/*! @brief Set the CHN field to a new value. */
+#define PIT_WR_TCTRL_CHN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_CHN_MASK, PIT_TCTRL_CHN(value)))
+#define PIT_BWR_TCTRL_CHN(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TFLG - Timer Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TFLG - Timer Flag Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers hold the PIT interrupt flags.
+ */
+/*!
+ * @name Constants and macros for entire PIT_TFLG register
+ */
+/*@{*/
+#define PIT_RD_TFLG(base, index) (PIT_TFLG_REG(base, index))
+#define PIT_WR_TFLG(base, index, value) (PIT_TFLG_REG(base, index) = (value))
+#define PIT_RMW_TFLG(base, index, mask, value) (PIT_WR_TFLG(base, index, (PIT_RD_TFLG(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) |  (value)))
+#define PIT_CLR_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) & ~(value)))
+#define PIT_TOG_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TFLG bitfields
+ */
+
+/*!
+ * @name Register PIT_TFLG, field TIF[0] (W1C)
+ *
+ * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
+ * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
+ * interrupt request.
+ *
+ * Values:
+ * - 0b0 - Timeout has not yet occurred.
+ * - 0b1 - Timeout has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TFLG_TIF field. */
+#define PIT_RD_TFLG_TIF(base, index) ((PIT_TFLG_REG(base, index) & PIT_TFLG_TIF_MASK) >> PIT_TFLG_TIF_SHIFT)
+#define PIT_BRD_TFLG_TIF(base, index) (BITBAND_ACCESS32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT))
+
+/*! @brief Set the TIF field to a new value. */
+#define PIT_WR_TFLG_TIF(base, index, value) (PIT_RMW_TFLG(base, index, PIT_TFLG_TIF_MASK, PIT_TFLG_TIF(value)))
+#define PIT_BWR_TFLG_TIF(base, index, value) (BITBAND_ACCESS32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PMC
+ *
+ * Power Management Controller
+ *
+ * Registers defined in this header file:
+ * - PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ * - PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ * - PMC_REGSC - Regulator Status And Control register
+ */
+
+#define PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
+#define PMC_IDX (0U) /*!< Instance number for PMC. */
+
+/*******************************************************************************
+ * PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
+ *
+ * Reset value: 0x10U
+ *
+ * This register contains status and control bits to support the low voltage
+ * detect function. This register should be written during the reset initialization
+ * program to set the desired controls even if the desired settings are the same
+ * as the reset settings. While the device is in the very low power or low
+ * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
+ * systems that must have LVD always on, configure the Power Mode Protection
+ * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
+ * low leakage modes from being enabled. See the device's data sheet for the
+ * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
+ * register's other bits are reset on Chip Reset Not VLLS. For more information
+ * about these reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC1 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC1(base)      (PMC_LVDSC1_REG(base))
+#define PMC_WR_LVDSC1(base, value) (PMC_LVDSC1_REG(base) = (value))
+#define PMC_RMW_LVDSC1(base, mask, value) (PMC_WR_LVDSC1(base, (PMC_RD_LVDSC1(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) |  (value)))
+#define PMC_CLR_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) & ~(value)))
+#define PMC_TOG_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC1 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
+ *
+ * Selects the LVD trip point voltage (V LVD ).
+ *
+ * Values:
+ * - 0b00 - Low trip point selected (V LVD = V LVDL )
+ * - 0b01 - High trip point selected (V LVD = V LVDH )
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
+#define PMC_RD_LVDSC1_LVDV(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDV_MASK) >> PMC_LVDSC1_LVDV_SHIFT)
+#define PMC_BRD_LVDSC1_LVDV(base) (PMC_RD_LVDSC1_LVDV(base))
+
+/*! @brief Set the LVDV field to a new value. */
+#define PMC_WR_LVDSC1_LVDV(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDV_MASK, PMC_LVDSC1_LVDV(value)))
+#define PMC_BWR_LVDSC1_LVDV(base, value) (PMC_WR_LVDSC1_LVDV(base, value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
+ *
+ * This write-once bit enables LVDF events to generate a hardware reset.
+ * Additional writes are ignored.
+ *
+ * Values:
+ * - 0b0 - LVDF does not generate hardware resets
+ * - 0b1 - Force an MCU reset when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
+#define PMC_RD_LVDSC1_LVDRE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDRE_MASK) >> PMC_LVDSC1_LVDRE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDRE(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT))
+
+/*! @brief Set the LVDRE field to a new value. */
+#define PMC_WR_LVDSC1_LVDRE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDRE_MASK, PMC_LVDSC1_LVDRE(value)))
+#define PMC_BWR_LVDSC1_LVDRE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVDF.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupt disabled (use polling)
+ * - 0b1 - Request a hardware interrupt when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
+#define PMC_RD_LVDSC1_LVDIE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDIE_MASK) >> PMC_LVDSC1_LVDIE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDIE(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT))
+
+/*! @brief Set the LVDIE field to a new value. */
+#define PMC_WR_LVDSC1_LVDIE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDIE_MASK, PMC_LVDSC1_LVDIE(value)))
+#define PMC_BWR_LVDSC1_LVDIE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage detection errors.
+ * Write 1 to clear LVDF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVDACK field to a new value. */
+#define PMC_WR_LVDSC1_LVDACK(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDACK_MASK, PMC_LVDSC1_LVDACK(value)))
+#define PMC_BWR_LVDSC1_LVDACK(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage detect event.
+ *
+ * Values:
+ * - 0b0 - Low-voltage event not detected
+ * - 0b1 - Low-voltage event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
+#define PMC_RD_LVDSC1_LVDF(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDF_MASK) >> PMC_LVDSC1_LVDF_SHIFT)
+#define PMC_BRD_LVDSC1_LVDF(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains status and control bits to support the low voltage
+ * warning function. While the device is in the very low power or low leakage modes,
+ * the LVD system is disabled regardless of LVDSC2 settings. See the device's
+ * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
+ * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
+ * register are reset on Chip Reset Not VLLS. For more information about these
+ * reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC2 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC2(base)      (PMC_LVDSC2_REG(base))
+#define PMC_WR_LVDSC2(base, value) (PMC_LVDSC2_REG(base) = (value))
+#define PMC_RMW_LVDSC2(base, mask, value) (PMC_WR_LVDSC2(base, (PMC_RD_LVDSC2(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) |  (value)))
+#define PMC_CLR_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) & ~(value)))
+#define PMC_TOG_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC2 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
+ *
+ * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
+ * depends on LVDSC1[LVDV].
+ *
+ * Values:
+ * - 0b00 - Low trip point selected (VLVW = VLVW1)
+ * - 0b01 - Mid 1 trip point selected (VLVW = VLVW2)
+ * - 0b10 - Mid 2 trip point selected (VLVW = VLVW3)
+ * - 0b11 - High trip point selected (VLVW = VLVW4)
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
+#define PMC_RD_LVDSC2_LVWV(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWV_MASK) >> PMC_LVDSC2_LVWV_SHIFT)
+#define PMC_BRD_LVDSC2_LVWV(base) (PMC_RD_LVDSC2_LVWV(base))
+
+/*! @brief Set the LVWV field to a new value. */
+#define PMC_WR_LVDSC2_LVWV(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWV_MASK, PMC_LVDSC2_LVWV(value)))
+#define PMC_BWR_LVDSC2_LVWV(base, value) (PMC_WR_LVDSC2_LVWV(base, value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVWF.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupt disabled (use polling)
+ * - 0b1 - Request a hardware interrupt when LVWF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
+#define PMC_RD_LVDSC2_LVWIE(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWIE_MASK) >> PMC_LVDSC2_LVWIE_SHIFT)
+#define PMC_BRD_LVDSC2_LVWIE(base) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT))
+
+/*! @brief Set the LVWIE field to a new value. */
+#define PMC_WR_LVDSC2_LVWIE(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWIE_MASK, PMC_LVDSC2_LVWIE(value)))
+#define PMC_BWR_LVDSC2_LVWIE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage warning errors.
+ * Write 1 to clear LVWF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVWACK field to a new value. */
+#define PMC_WR_LVDSC2_LVWACK(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWACK_MASK, PMC_LVDSC2_LVWACK(value)))
+#define PMC_BWR_LVDSC2_LVWACK(base, value) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage warning event. LVWF is
+ * set when VSupply transitions below the trip point, or after reset and VSupply is
+ * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
+ * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
+ * LVWACK first.
+ *
+ * Values:
+ * - 0b0 - Low-voltage warning event not detected
+ * - 0b1 - Low-voltage warning event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
+#define PMC_RD_LVDSC2_LVWF(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWF_MASK) >> PMC_LVDSC2_LVWF_SHIFT)
+#define PMC_BRD_LVDSC2_LVWF(base) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_REGSC - Regulator Status And Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_REGSC - Regulator Status And Control register (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * The PMC contains an internal voltage regulator. The voltage regulator design
+ * uses a bandgap reference that is also available through a buffer as input to
+ * certain internal peripherals, such as the CMP and ADC. The internal regulator
+ * provides a status bit (REGONS) indicating the regulator is in run regulation.
+ * This register is reset on Chip Reset Not VLLS and by reset types that trigger
+ * Chip Reset not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire PMC_REGSC register
+ */
+/*@{*/
+#define PMC_RD_REGSC(base)       (PMC_REGSC_REG(base))
+#define PMC_WR_REGSC(base, value) (PMC_REGSC_REG(base) = (value))
+#define PMC_RMW_REGSC(base, mask, value) (PMC_WR_REGSC(base, (PMC_RD_REGSC(base) & ~(mask)) | (value)))
+#define PMC_SET_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) |  (value)))
+#define PMC_CLR_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) & ~(value)))
+#define PMC_TOG_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_REGSC bitfields
+ */
+
+/*!
+ * @name Register PMC_REGSC, field BGBE[0] (RW)
+ *
+ * Enables the bandgap buffer.
+ *
+ * Values:
+ * - 0b0 - Bandgap buffer not enabled
+ * - 0b1 - Bandgap buffer enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGBE field. */
+#define PMC_RD_REGSC_BGBE(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGBE_MASK) >> PMC_REGSC_BGBE_SHIFT)
+#define PMC_BRD_REGSC_BGBE(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT))
+
+/*! @brief Set the BGBE field to a new value. */
+#define PMC_WR_REGSC_BGBE(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGBE_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGBE(value)))
+#define PMC_BWR_REGSC_BGBE(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field REGONS[2] (RO)
+ *
+ * This read-only field provides the current status of the internal voltage
+ * regulator.
+ *
+ * Values:
+ * - 0b0 - Regulator is in stop regulation or in transition to/from it
+ * - 0b1 - Regulator is in run regulation
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_REGONS field. */
+#define PMC_RD_REGSC_REGONS(base) ((PMC_REGSC_REG(base) & PMC_REGSC_REGONS_MASK) >> PMC_REGSC_REGONS_SHIFT)
+#define PMC_BRD_REGSC_REGONS(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_REGONS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field ACKISO[3] (W1C)
+ *
+ * Reading this field indicates whether certain peripherals and the I/O pads are
+ * in a latched state as a result of having been in a VLLS mode. Writing 1 to
+ * this field when it is set releases the I/O pads and certain peripherals to their
+ * normal run mode state. After recovering from a VLLS mode, user should restore
+ * chip configuration before clearing ACKISO. In particular, pin configuration
+ * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
+ * being falsely set when ACKISO is cleared.
+ *
+ * Values:
+ * - 0b0 - Peripherals and I/O pads are in normal run state.
+ * - 0b1 - Certain peripherals and I/O pads are in an isolated and latched state.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_ACKISO field. */
+#define PMC_RD_REGSC_ACKISO(base) ((PMC_REGSC_REG(base) & PMC_REGSC_ACKISO_MASK) >> PMC_REGSC_ACKISO_SHIFT)
+#define PMC_BRD_REGSC_ACKISO(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT))
+
+/*! @brief Set the ACKISO field to a new value. */
+#define PMC_WR_REGSC_ACKISO(base, value) (PMC_RMW_REGSC(base, PMC_REGSC_ACKISO_MASK, PMC_REGSC_ACKISO(value)))
+#define PMC_BWR_REGSC_ACKISO(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field BGEN[4] (RW)
+ *
+ * BGEN controls whether the bandgap is enabled in lower power modes of
+ * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
+ * reference in low power modes of operation, set BGEN to continue to enable the
+ * bandgap operation. When the bandgap voltage reference is not needed in low
+ * power modes, clear BGEN to avoid excess power consumption.
+ *
+ * Values:
+ * - 0b0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
+ * - 0b1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGEN field. */
+#define PMC_RD_REGSC_BGEN(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGEN_MASK) >> PMC_REGSC_BGEN_SHIFT)
+#define PMC_BRD_REGSC_BGEN(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT))
+
+/*! @brief Set the BGEN field to a new value. */
+#define PMC_WR_REGSC_BGEN(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGEN_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGEN(value)))
+#define PMC_BWR_REGSC_BGEN(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PORT
+ *
+ * Pin Control and Interrupts
+ *
+ * Registers defined in this header file:
+ * - PORT_PCR - Pin Control Register n
+ * - PORT_GPCLR - Global Pin Control Low Register
+ * - PORT_GPCHR - Global Pin Control High Register
+ * - PORT_ISFR - Interrupt Status Flag Register
+ * - PORT_DFER - Digital Filter Enable Register
+ * - PORT_DFCR - Digital Filter Clock Register
+ * - PORT_DFWR - Digital Filter Width Register
+ */
+
+#define PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
+#define PORTA_IDX (0U) /*!< Instance number for PORTA. */
+#define PORTB_IDX (1U) /*!< Instance number for PORTB. */
+#define PORTC_IDX (2U) /*!< Instance number for PORTC. */
+#define PORTD_IDX (3U) /*!< Instance number for PORTD. */
+#define PORTE_IDX (4U) /*!< Instance number for PORTE. */
+
+/*******************************************************************************
+ * PORT_PCR - Pin Control Register n
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_PCR - Pin Control Register n (RW)
+ *
+ * Reset value: 0x00000746U
+ *
+ * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
+ * this device. See the GPIO Configuration section for details on the available
+ * functions for each pin. Do not modify pin configuration registers associated
+ * with pins not available in your selected package. All unbonded pins not
+ * available in your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire PORT_PCR register
+ */
+/*@{*/
+#define PORT_RD_PCR(base, index) (PORT_PCR_REG(base, index))
+#define PORT_WR_PCR(base, index, value) (PORT_PCR_REG(base, index) = (value))
+#define PORT_RMW_PCR(base, index, mask, value) (PORT_WR_PCR(base, index, (PORT_RD_PCR(base, index) & ~(mask)) | (value)))
+#define PORT_SET_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) |  (value)))
+#define PORT_CLR_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) & ~(value)))
+#define PORT_TOG_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_PCR bitfields
+ */
+
+/*!
+ * @name Register PORT_PCR, field PS[0] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Internal pulldown resistor is enabled on the corresponding pin, if
+ *     the corresponding PE field is set.
+ * - 0b1 - Internal pullup resistor is enabled on the corresponding pin, if the
+ *     corresponding PE field is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PS field. */
+#define PORT_RD_PCR_PS(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PS_MASK) >> PORT_PCR_PS_SHIFT)
+#define PORT_BRD_PCR_PS(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT))
+
+/*! @brief Set the PS field to a new value. */
+#define PORT_WR_PCR_PS(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PS_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PS(value)))
+#define PORT_BWR_PCR_PS(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PE[1] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Internal pullup or pulldown resistor is not enabled on the
+ *     corresponding pin.
+ * - 0b1 - Internal pullup or pulldown resistor is enabled on the corresponding
+ *     pin, if the pin is configured as a digital input.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PE field. */
+#define PORT_RD_PCR_PE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PE_MASK) >> PORT_PCR_PE_SHIFT)
+#define PORT_BRD_PCR_PE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT))
+
+/*! @brief Set the PE field to a new value. */
+#define PORT_WR_PCR_PE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PE(value)))
+#define PORT_BWR_PCR_PE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field SRE[2] (RW)
+ *
+ * Slew rate configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Fast slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ * - 0b1 - Slow slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_SRE field. */
+#define PORT_RD_PCR_SRE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_SRE_MASK) >> PORT_PCR_SRE_SHIFT)
+#define PORT_BRD_PCR_SRE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT))
+
+/*! @brief Set the SRE field to a new value. */
+#define PORT_WR_PCR_SRE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_SRE(value)))
+#define PORT_BWR_PCR_SRE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PFE[4] (RW)
+ *
+ * Passive filter configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Passive input filter is disabled on the corresponding pin.
+ * - 0b1 - Passive input filter is enabled on the corresponding pin, if the pin
+ *     is configured as a digital input. Refer to the device data sheet for
+ *     filter characteristics.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PFE field. */
+#define PORT_RD_PCR_PFE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PFE_MASK) >> PORT_PCR_PFE_SHIFT)
+#define PORT_BRD_PCR_PFE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT))
+
+/*! @brief Set the PFE field to a new value. */
+#define PORT_WR_PCR_PFE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PFE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PFE(value)))
+#define PORT_BWR_PCR_PFE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ODE[5] (RW)
+ *
+ * Open drain configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Open drain output is disabled on the corresponding pin.
+ * - 0b1 - Open drain output is enabled on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ODE field. */
+#define PORT_RD_PCR_ODE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ODE_MASK) >> PORT_PCR_ODE_SHIFT)
+#define PORT_BRD_PCR_ODE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ODE_SHIFT))
+
+/*! @brief Set the ODE field to a new value. */
+#define PORT_WR_PCR_ODE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_ODE(value)))
+#define PORT_BWR_PCR_ODE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field DSE[6] (RW)
+ *
+ * Drive strength configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Low drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ * - 0b1 - High drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_DSE field. */
+#define PORT_RD_PCR_DSE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_DSE_MASK) >> PORT_PCR_DSE_SHIFT)
+#define PORT_BRD_PCR_DSE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT))
+
+/*! @brief Set the DSE field to a new value. */
+#define PORT_WR_PCR_DSE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_DSE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_DSE(value)))
+#define PORT_BWR_PCR_DSE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field MUX[10:8] (RW)
+ *
+ * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
+ * reserved and may result in configuring the pin for a different pin muxing
+ * slot. The corresponding pin is configured in the following pin muxing slot as
+ * follows:
+ *
+ * Values:
+ * - 0b000 - Pin disabled (analog).
+ * - 0b001 - Alternative 1 (GPIO).
+ * - 0b010 - Alternative 2 (chip-specific).
+ * - 0b011 - Alternative 3 (chip-specific).
+ * - 0b100 - Alternative 4 (chip-specific).
+ * - 0b101 - Alternative 5 (chip-specific).
+ * - 0b110 - Alternative 6 (chip-specific).
+ * - 0b111 - Alternative 7 (chip-specific).
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_MUX field. */
+#define PORT_RD_PCR_MUX(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_MUX_MASK) >> PORT_PCR_MUX_SHIFT)
+#define PORT_BRD_PCR_MUX(base, index) (PORT_RD_PCR_MUX(base, index))
+
+/*! @brief Set the MUX field to a new value. */
+#define PORT_WR_PCR_MUX(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_MUX_MASK | PORT_PCR_ISF_MASK), PORT_PCR_MUX(value)))
+#define PORT_BWR_PCR_MUX(base, index, value) (PORT_WR_PCR_MUX(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field LK[15] (RW)
+ *
+ * Values:
+ * - 0b0 - Pin Control Register fields [15:0] are not locked.
+ * - 0b1 - Pin Control Register fields [15:0] are locked and cannot be updated
+ *     until the next system reset.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_LK field. */
+#define PORT_RD_PCR_LK(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_LK_MASK) >> PORT_PCR_LK_SHIFT)
+#define PORT_BRD_PCR_LK(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_LK_SHIFT))
+
+/*! @brief Set the LK field to a new value. */
+#define PORT_WR_PCR_LK(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_LK_MASK | PORT_PCR_ISF_MASK), PORT_PCR_LK(value)))
+#define PORT_BWR_PCR_LK(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_LK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field IRQC[19:16] (RW)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * corresponding pin is configured to generate interrupt/DMA request as follows:
+ *
+ * Values:
+ * - 0b0000 - Interrupt/DMA request disabled.
+ * - 0b0001 - DMA request on rising edge.
+ * - 0b0010 - DMA request on falling edge.
+ * - 0b0011 - DMA request on either edge.
+ * - 0b1000 - Interrupt when logic 0.
+ * - 0b1001 - Interrupt on rising-edge.
+ * - 0b1010 - Interrupt on falling-edge.
+ * - 0b1011 - Interrupt on either edge.
+ * - 0b1100 - Interrupt when logic 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_IRQC field. */
+#define PORT_RD_PCR_IRQC(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_IRQC_MASK) >> PORT_PCR_IRQC_SHIFT)
+#define PORT_BRD_PCR_IRQC(base, index) (PORT_RD_PCR_IRQC(base, index))
+
+/*! @brief Set the IRQC field to a new value. */
+#define PORT_WR_PCR_IRQC(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_IRQC_MASK | PORT_PCR_ISF_MASK), PORT_PCR_IRQC(value)))
+#define PORT_BWR_PCR_IRQC(base, index, value) (PORT_WR_PCR_IRQC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ISF[24] (W1C)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Configured interrupt is not detected.
+ * - 0b1 - Configured interrupt is detected. If the pin is configured to
+ *     generate a DMA request, then the corresponding flag will be cleared automatically
+ *     at the completion of the requested DMA transfer. Otherwise, the flag
+ *     remains set until a logic 1 is written to the flag. If the pin is configured
+ *     for a level sensitive interrupt and the pin remains asserted, then the flag
+ *     is set again immediately after it is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ISF field. */
+#define PORT_RD_PCR_ISF(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ISF_MASK) >> PORT_PCR_ISF_SHIFT)
+#define PORT_BRD_PCR_ISF(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT))
+
+/*! @brief Set the ISF field to a new value. */
+#define PORT_WR_PCR_ISF(base, index, value) (PORT_RMW_PCR(base, index, PORT_PCR_ISF_MASK, PORT_PCR_ISF(value)))
+#define PORT_BWR_PCR_ISF(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCLR - Global Pin Control Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCLR - Global Pin Control Low Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCLR register
+ */
+/*@{*/
+#define PORT_RD_GPCLR(base)      (PORT_GPCLR_REG(base))
+#define PORT_WR_GPCLR(base, value) (PORT_GPCLR_REG(base) = (value))
+#define PORT_RMW_GPCLR(base, mask, value) (PORT_WR_GPCLR(base, (PORT_RD_GPCLR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCLR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCLR_GPWD(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWD_MASK, PORT_GPCLR_GPWD(value)))
+#define PORT_BWR_GPCLR_GPWD(base, value) (PORT_WR_GPCLR_GPWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
+ *     the value in GPWD.
+ * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
+ *     value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCLR_GPWE(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWE_MASK, PORT_GPCLR_GPWE(value)))
+#define PORT_BWR_GPCLR_GPWE(base, value) (PORT_WR_GPCLR_GPWE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCHR - Global Pin Control High Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCHR - Global Pin Control High Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCHR register
+ */
+/*@{*/
+#define PORT_RD_GPCHR(base)      (PORT_GPCHR_REG(base))
+#define PORT_WR_GPCHR(base, value) (PORT_GPCHR_REG(base) = (value))
+#define PORT_RMW_GPCHR(base, mask, value) (PORT_WR_GPCHR(base, (PORT_RD_GPCHR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCHR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCHR_GPWD(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWD_MASK, PORT_GPCHR_GPWD(value)))
+#define PORT_BWR_GPCHR_GPWD(base, value) (PORT_WR_GPCHR_GPWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
+ *     the value in GPWD.
+ * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
+ *     value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCHR_GPWE(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWE_MASK, PORT_GPCHR_GPWE(value)))
+#define PORT_BWR_GPCHR_GPWE(base, value) (PORT_WR_GPCHR_GPWE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_ISFR - Interrupt Status Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_ISFR - Interrupt Status Flag Register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * Interrupt Status Flag for each pin is also visible in the corresponding Pin
+ * Control Register, and each flag can be cleared in either location.
+ */
+/*!
+ * @name Constants and macros for entire PORT_ISFR register
+ */
+/*@{*/
+#define PORT_RD_ISFR(base)       (PORT_ISFR_REG(base))
+#define PORT_WR_ISFR(base, value) (PORT_ISFR_REG(base) = (value))
+#define PORT_RMW_ISFR(base, mask, value) (PORT_WR_ISFR(base, (PORT_RD_ISFR(base) & ~(mask)) | (value)))
+#define PORT_SET_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) |  (value)))
+#define PORT_CLR_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) & ~(value)))
+#define PORT_TOG_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFER - Digital Filter Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFER - Digital Filter Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The corresponding bit is read only for pins that do not support a digital
+ * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
+ * the pins that support digital filter. The digital filter configuration is valid
+ * in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFER register
+ */
+/*@{*/
+#define PORT_RD_DFER(base)       (PORT_DFER_REG(base))
+#define PORT_WR_DFER(base, value) (PORT_DFER_REG(base) = (value))
+#define PORT_RMW_DFER(base, mask, value) (PORT_WR_DFER(base, (PORT_RD_DFER(base) & ~(mask)) | (value)))
+#define PORT_SET_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) |  (value)))
+#define PORT_CLR_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) & ~(value)))
+#define PORT_TOG_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFCR - Digital Filter Clock Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFCR - Digital Filter Clock Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFCR register
+ */
+/*@{*/
+#define PORT_RD_DFCR(base)       (PORT_DFCR_REG(base))
+#define PORT_WR_DFCR(base, value) (PORT_DFCR_REG(base) = (value))
+#define PORT_RMW_DFCR(base, mask, value) (PORT_WR_DFCR(base, (PORT_RD_DFCR(base) & ~(mask)) | (value)))
+#define PORT_SET_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) |  (value)))
+#define PORT_CLR_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) & ~(value)))
+#define PORT_TOG_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_DFCR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFCR, field CS[0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the clock source for the digital input filters. Changing the filter
+ * clock source must be done only when all digital filters are disabled.
+ *
+ * Values:
+ * - 0b0 - Digital filters are clocked by the bus clock.
+ * - 0b1 - Digital filters are clocked by the 1 kHz LPO clock.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_DFCR_CS field. */
+#define PORT_RD_DFCR_CS(base) ((PORT_DFCR_REG(base) & PORT_DFCR_CS_MASK) >> PORT_DFCR_CS_SHIFT)
+#define PORT_BRD_DFCR_CS(base) (BITBAND_ACCESS32(&PORT_DFCR_REG(base), PORT_DFCR_CS_SHIFT))
+
+/*! @brief Set the CS field to a new value. */
+#define PORT_WR_DFCR_CS(base, value) (PORT_RMW_DFCR(base, PORT_DFCR_CS_MASK, PORT_DFCR_CS(value)))
+#define PORT_BWR_DFCR_CS(base, value) (BITBAND_ACCESS32(&PORT_DFCR_REG(base), PORT_DFCR_CS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFWR - Digital Filter Width Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFWR - Digital Filter Width Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFWR register
+ */
+/*@{*/
+#define PORT_RD_DFWR(base)       (PORT_DFWR_REG(base))
+#define PORT_WR_DFWR(base, value) (PORT_DFWR_REG(base) = (value))
+#define PORT_RMW_DFWR(base, mask, value) (PORT_WR_DFWR(base, (PORT_RD_DFWR(base) & ~(mask)) | (value)))
+#define PORT_SET_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) |  (value)))
+#define PORT_CLR_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) & ~(value)))
+#define PORT_TOG_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_DFWR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFWR, field FILT[4:0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the maximum size of the glitches, in clock cycles, that the digital
+ * filter absorbs for the enabled digital filters. Glitches that are longer than
+ * this register setting will pass through the digital filter, and glitches that
+ * are equal to or less than this register setting are filtered. Changing the
+ * filter length must be done only after all filters are disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_DFWR_FILT field. */
+#define PORT_RD_DFWR_FILT(base) ((PORT_DFWR_REG(base) & PORT_DFWR_FILT_MASK) >> PORT_DFWR_FILT_SHIFT)
+#define PORT_BRD_DFWR_FILT(base) (PORT_RD_DFWR_FILT(base))
+
+/*! @brief Set the FILT field to a new value. */
+#define PORT_WR_DFWR_FILT(base, value) (PORT_RMW_DFWR(base, PORT_DFWR_FILT_MASK, PORT_DFWR_FILT(value)))
+#define PORT_BWR_DFWR_FILT(base, value) (PORT_WR_DFWR_FILT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 RCM
+ *
+ * Reset Control Module
+ *
+ * Registers defined in this header file:
+ * - RCM_SRS0 - System Reset Status Register 0
+ * - RCM_SRS1 - System Reset Status Register 1
+ * - RCM_RPFC - Reset Pin Filter Control register
+ * - RCM_RPFW - Reset Pin Filter Width register
+ * - RCM_MR - Mode Register
+ */
+
+#define RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */
+#define RCM_IDX (0U) /*!< Instance number for RCM. */
+
+/*******************************************************************************
+ * RCM_SRS0 - System Reset Status Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS0 - System Reset Status Register 0 (RO)
+ *
+ * Reset value: 0x82U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
+ * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS0 register
+ */
+/*@{*/
+#define RCM_RD_SRS0(base)        (RCM_SRS0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS0 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS0, field WAKEUP[0] (RO)
+ *
+ * Indicates a reset has been caused by an enabled LLWU module wakeup source
+ * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
+ * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
+ * mode causes a reset. This bit is cleared by any reset except WAKEUP.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by LLWU module wakeup source
+ * - 0b1 - Reset caused by LLWU module wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WAKEUP field. */
+#define RCM_RD_SRS0_WAKEUP(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WAKEUP_MASK) >> RCM_SRS0_WAKEUP_SHIFT)
+#define RCM_BRD_SRS0_WAKEUP(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_WAKEUP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LVD[1] (RO)
+ *
+ * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
+ * an LVD reset occurs. This field is also set by POR.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by LVD trip or POR
+ * - 0b1 - Reset caused by LVD trip or POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LVD field. */
+#define RCM_RD_SRS0_LVD(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LVD_MASK) >> RCM_SRS0_LVD_SHIFT)
+#define RCM_BRD_SRS0_LVD(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LVD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LOC[2] (RO)
+ *
+ * Indicates a reset has been caused by a loss of external clock. The MCG clock
+ * monitor must be enabled for a loss of clock to be detected. Refer to the
+ * detailed MCG description for information on enabling the clock monitor.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by a loss of external clock.
+ * - 0b1 - Reset caused by a loss of external clock.
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LOC field. */
+#define RCM_RD_SRS0_LOC(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOC_MASK) >> RCM_SRS0_LOC_SHIFT)
+#define RCM_BRD_SRS0_LOC(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LOC_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LOL[3] (RO)
+ *
+ * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
+ * MCG description for information on the loss-of-clock event.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by a loss of lock in the PLL
+ * - 0b1 - Reset caused by a loss of lock in the PLL
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LOL field. */
+#define RCM_RD_SRS0_LOL(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOL_MASK) >> RCM_SRS0_LOL_SHIFT)
+#define RCM_BRD_SRS0_LOL(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LOL_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field WDOG[5] (RO)
+ *
+ * Indicates a reset has been caused by the watchdog timer Computer Operating
+ * Properly (COP) timing out. This reset source can be blocked by disabling the COP
+ * watchdog: write 00 to SIM_COPCTRL[COPT].
+ *
+ * Values:
+ * - 0b0 - Reset not caused by watchdog timeout
+ * - 0b1 - Reset caused by watchdog timeout
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WDOG field. */
+#define RCM_RD_SRS0_WDOG(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WDOG_MASK) >> RCM_SRS0_WDOG_SHIFT)
+#define RCM_BRD_SRS0_WDOG(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_WDOG_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field PIN[6] (RO)
+ *
+ * Indicates a reset has been caused by an active-low level on the external
+ * RESET pin.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by external reset pin
+ * - 0b1 - Reset caused by external reset pin
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_PIN field. */
+#define RCM_RD_SRS0_PIN(base) ((RCM_SRS0_REG(base) & RCM_SRS0_PIN_MASK) >> RCM_SRS0_PIN_SHIFT)
+#define RCM_BRD_SRS0_PIN(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_PIN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field POR[7] (RO)
+ *
+ * Indicates a reset has been caused by the power-on detection logic. Because
+ * the internal supply voltage was ramping up at the time, the low-voltage reset
+ * (LVD) status bit is also set to indicate that the reset occurred while the
+ * internal supply was below the LVD threshold.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by POR
+ * - 0b1 - Reset caused by POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_POR field. */
+#define RCM_RD_SRS0_POR(base) ((RCM_SRS0_REG(base) & RCM_SRS0_POR_MASK) >> RCM_SRS0_POR_SHIFT)
+#define RCM_BRD_SRS0_POR(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_POR_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_SRS1 - System Reset Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS1 - System Reset Status Register 1 (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS1 register
+ */
+/*@{*/
+#define RCM_RD_SRS1(base)        (RCM_SRS1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS1 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS1, field JTAG[0] (RO)
+ *
+ * Indicates a reset has been caused by JTAG selection of certain IR codes:
+ * EZPORT, EXTEST, HIGHZ, and CLAMP.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by JTAG
+ * - 0b1 - Reset caused by JTAG
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_JTAG field. */
+#define RCM_RD_SRS1_JTAG(base) ((RCM_SRS1_REG(base) & RCM_SRS1_JTAG_MASK) >> RCM_SRS1_JTAG_SHIFT)
+#define RCM_BRD_SRS1_JTAG(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_JTAG_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field LOCKUP[1] (RO)
+ *
+ * Indicates a reset has been caused by the ARM core indication of a LOCKUP
+ * event.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by core LOCKUP event
+ * - 0b1 - Reset caused by core LOCKUP event
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_LOCKUP field. */
+#define RCM_RD_SRS1_LOCKUP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_LOCKUP_MASK) >> RCM_SRS1_LOCKUP_SHIFT)
+#define RCM_BRD_SRS1_LOCKUP(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_LOCKUP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SW[2] (RO)
+ *
+ * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
+ * Application Interrupt and Reset Control Register in the ARM core.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by software setting of SYSRESETREQ bit
+ * - 0b1 - Reset caused by software setting of SYSRESETREQ bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SW field. */
+#define RCM_RD_SRS1_SW(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SW_MASK) >> RCM_SRS1_SW_SHIFT)
+#define RCM_BRD_SRS1_SW(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_SW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field MDM_AP[3] (RO)
+ *
+ * Indicates a reset has been caused by the host debugger system setting of the
+ * System Reset Request bit in the MDM-AP Control Register.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by host debugger system setting of the System Reset
+ *     Request bit
+ * - 0b1 - Reset caused by host debugger system setting of the System Reset
+ *     Request bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_MDM_AP field. */
+#define RCM_RD_SRS1_MDM_AP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_MDM_AP_MASK) >> RCM_SRS1_MDM_AP_SHIFT)
+#define RCM_BRD_SRS1_MDM_AP(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_MDM_AP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field EZPT[4] (RO)
+ *
+ * Indicates a reset has been caused by EzPort receiving the RESET command while
+ * the device is in EzPort mode.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by EzPort receiving the RESET command while the
+ *     device is in EzPort mode
+ * - 0b1 - Reset caused by EzPort receiving the RESET command while the device
+ *     is in EzPort mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_EZPT field. */
+#define RCM_RD_SRS1_EZPT(base) ((RCM_SRS1_REG(base) & RCM_SRS1_EZPT_MASK) >> RCM_SRS1_EZPT_SHIFT)
+#define RCM_BRD_SRS1_EZPT(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_EZPT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SACKERR[5] (RO)
+ *
+ * Indicates that after an attempt to enter Stop mode, a reset has been caused
+ * by a failure of one or more peripherals to acknowledge within approximately one
+ * second to enter stop mode.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by peripheral failure to acknowledge attempt to
+ *     enter stop mode
+ * - 0b1 - Reset caused by peripheral failure to acknowledge attempt to enter
+ *     stop mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SACKERR field. */
+#define RCM_RD_SRS1_SACKERR(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SACKERR_MASK) >> RCM_SRS1_SACKERR_SHIFT)
+#define RCM_BRD_SRS1_SACKERR(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_SACKERR_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFC - Reset Pin Filter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFC - Reset Pin Filter Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
+ * other reset types. The bus clock filter is reset when disabled or when entering
+ * stop mode. The LPO filter is reset when disabled or when entering any low
+ * leakage stop mode .
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFC register
+ */
+/*@{*/
+#define RCM_RD_RPFC(base)        (RCM_RPFC_REG(base))
+#define RCM_WR_RPFC(base, value) (RCM_RPFC_REG(base) = (value))
+#define RCM_RMW_RPFC(base, mask, value) (RCM_WR_RPFC(base, (RCM_RD_RPFC(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) |  (value)))
+#define RCM_CLR_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) & ~(value)))
+#define RCM_TOG_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFC bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
+ *
+ * Selects how the reset pin filter is enabled in run and wait modes.
+ *
+ * Values:
+ * - 0b00 - All filtering disabled
+ * - 0b01 - Bus clock filter enabled for normal operation
+ * - 0b10 - LPO clock filter enabled for normal operation
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */
+#define RCM_RD_RPFC_RSTFLTSRW(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSRW_MASK) >> RCM_RPFC_RSTFLTSRW_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSRW(base) (RCM_RD_RPFC_RSTFLTSRW(base))
+
+/*! @brief Set the RSTFLTSRW field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSRW(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSRW_MASK, RCM_RPFC_RSTFLTSRW(value)))
+#define RCM_BWR_RPFC_RSTFLTSRW(base, value) (RCM_WR_RPFC_RSTFLTSRW(base, value))
+/*@}*/
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
+ *
+ * Selects how the reset pin filter is enabled in Stop and VLPS modes
+ *
+ * Values:
+ * - 0b0 - All filtering disabled
+ * - 0b1 - LPO clock filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */
+#define RCM_RD_RPFC_RSTFLTSS(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSS_MASK) >> RCM_RPFC_RSTFLTSS_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSS(base) (BITBAND_ACCESS8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT))
+
+/*! @brief Set the RSTFLTSS field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSS(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSS_MASK, RCM_RPFC_RSTFLTSS(value)))
+#define RCM_BWR_RPFC_RSTFLTSS(base, value) (BITBAND_ACCESS8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFW - Reset Pin Filter Width register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFW - Reset Pin Filter Width register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
+ * They are unaffected by other reset types.
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFW register
+ */
+/*@{*/
+#define RCM_RD_RPFW(base)        (RCM_RPFW_REG(base))
+#define RCM_WR_RPFW(base, value) (RCM_RPFW_REG(base) = (value))
+#define RCM_RMW_RPFW(base, mask, value) (RCM_WR_RPFW(base, (RCM_RD_RPFW(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) |  (value)))
+#define RCM_CLR_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) & ~(value)))
+#define RCM_TOG_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFW bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
+ *
+ * Selects the reset pin bus clock filter width.
+ *
+ * Values:
+ * - 0b00000 - Bus clock filter count is 1
+ * - 0b00001 - Bus clock filter count is 2
+ * - 0b00010 - Bus clock filter count is 3
+ * - 0b00011 - Bus clock filter count is 4
+ * - 0b00100 - Bus clock filter count is 5
+ * - 0b00101 - Bus clock filter count is 6
+ * - 0b00110 - Bus clock filter count is 7
+ * - 0b00111 - Bus clock filter count is 8
+ * - 0b01000 - Bus clock filter count is 9
+ * - 0b01001 - Bus clock filter count is 10
+ * - 0b01010 - Bus clock filter count is 11
+ * - 0b01011 - Bus clock filter count is 12
+ * - 0b01100 - Bus clock filter count is 13
+ * - 0b01101 - Bus clock filter count is 14
+ * - 0b01110 - Bus clock filter count is 15
+ * - 0b01111 - Bus clock filter count is 16
+ * - 0b10000 - Bus clock filter count is 17
+ * - 0b10001 - Bus clock filter count is 18
+ * - 0b10010 - Bus clock filter count is 19
+ * - 0b10011 - Bus clock filter count is 20
+ * - 0b10100 - Bus clock filter count is 21
+ * - 0b10101 - Bus clock filter count is 22
+ * - 0b10110 - Bus clock filter count is 23
+ * - 0b10111 - Bus clock filter count is 24
+ * - 0b11000 - Bus clock filter count is 25
+ * - 0b11001 - Bus clock filter count is 26
+ * - 0b11010 - Bus clock filter count is 27
+ * - 0b11011 - Bus clock filter count is 28
+ * - 0b11100 - Bus clock filter count is 29
+ * - 0b11101 - Bus clock filter count is 30
+ * - 0b11110 - Bus clock filter count is 31
+ * - 0b11111 - Bus clock filter count is 32
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */
+#define RCM_RD_RPFW_RSTFLTSEL(base) ((RCM_RPFW_REG(base) & RCM_RPFW_RSTFLTSEL_MASK) >> RCM_RPFW_RSTFLTSEL_SHIFT)
+#define RCM_BRD_RPFW_RSTFLTSEL(base) (RCM_RD_RPFW_RSTFLTSEL(base))
+
+/*! @brief Set the RSTFLTSEL field to a new value. */
+#define RCM_WR_RPFW_RSTFLTSEL(base, value) (RCM_RMW_RPFW(base, RCM_RPFW_RSTFLTSEL_MASK, RCM_RPFW_RSTFLTSEL(value)))
+#define RCM_BWR_RPFW_RSTFLTSEL(base, value) (RCM_WR_RPFW_RSTFLTSEL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_MR - Mode Register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_MR - Mode Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the state of the
+ * mode pins during the last Chip Reset.
+ */
+/*!
+ * @name Constants and macros for entire RCM_MR register
+ */
+/*@{*/
+#define RCM_RD_MR(base)          (RCM_MR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_MR bitfields
+ */
+
+/*!
+ * @name Register RCM_MR, field EZP_MS[1] (RO)
+ *
+ * Reflects the state of the EZP_MS pin during the last Chip Reset
+ *
+ * Values:
+ * - 0b0 - Pin deasserted (logic 1)
+ * - 0b1 - Pin asserted (logic 0)
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_MR_EZP_MS field. */
+#define RCM_RD_MR_EZP_MS(base) ((RCM_MR_REG(base) & RCM_MR_EZP_MS_MASK) >> RCM_MR_EZP_MS_SHIFT)
+#define RCM_BRD_MR_EZP_MS(base) (BITBAND_ACCESS8(&RCM_MR_REG(base), RCM_MR_EZP_MS_SHIFT))
+/*@}*/
+
+/*
+ * MK64F12 RFSYS
+ *
+ * System register file
+ *
+ * Registers defined in this header file:
+ * - RFSYS_REG - Register file register
+ */
+
+#define RFSYS_INSTANCE_COUNT (1U) /*!< Number of instances of the RFSYS module. */
+#define RFSYS_IDX (0U) /*!< Instance number for RFSYS. */
+
+/*******************************************************************************
+ * RFSYS_REG - Register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFSYS_REG - Register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFSYS_REG register
+ */
+/*@{*/
+#define RFSYS_RD_REG(base, index) (RFSYS_REG_REG(base, index))
+#define RFSYS_WR_REG(base, index, value) (RFSYS_REG_REG(base, index) = (value))
+#define RFSYS_RMW_REG(base, index, mask, value) (RFSYS_WR_REG(base, index, (RFSYS_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFSYS_SET_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) |  (value)))
+#define RFSYS_CLR_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) & ~(value)))
+#define RFSYS_TOG_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFSYS_REG bitfields
+ */
+
+/*!
+ * @name Register RFSYS_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LL field. */
+#define RFSYS_RD_REG_LL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LL_MASK) >> RFSYS_REG_LL_SHIFT)
+#define RFSYS_BRD_REG_LL(base, index) (RFSYS_RD_REG_LL(base, index))
+
+/*! @brief Set the LL field to a new value. */
+#define RFSYS_WR_REG_LL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LL_MASK, RFSYS_REG_LL(value)))
+#define RFSYS_BWR_REG_LL(base, index, value) (RFSYS_WR_REG_LL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LH field. */
+#define RFSYS_RD_REG_LH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LH_MASK) >> RFSYS_REG_LH_SHIFT)
+#define RFSYS_BRD_REG_LH(base, index) (RFSYS_RD_REG_LH(base, index))
+
+/*! @brief Set the LH field to a new value. */
+#define RFSYS_WR_REG_LH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LH_MASK, RFSYS_REG_LH(value)))
+#define RFSYS_BWR_REG_LH(base, index, value) (RFSYS_WR_REG_LH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HL field. */
+#define RFSYS_RD_REG_HL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HL_MASK) >> RFSYS_REG_HL_SHIFT)
+#define RFSYS_BRD_REG_HL(base, index) (RFSYS_RD_REG_HL(base, index))
+
+/*! @brief Set the HL field to a new value. */
+#define RFSYS_WR_REG_HL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HL_MASK, RFSYS_REG_HL(value)))
+#define RFSYS_BWR_REG_HL(base, index, value) (RFSYS_WR_REG_HL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HH field. */
+#define RFSYS_RD_REG_HH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HH_MASK) >> RFSYS_REG_HH_SHIFT)
+#define RFSYS_BRD_REG_HH(base, index) (RFSYS_RD_REG_HH(base, index))
+
+/*! @brief Set the HH field to a new value. */
+#define RFSYS_WR_REG_HH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HH_MASK, RFSYS_REG_HH(value)))
+#define RFSYS_BWR_REG_HH(base, index, value) (RFSYS_WR_REG_HH(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 RFVBAT
+ *
+ * VBAT register file
+ *
+ * Registers defined in this header file:
+ * - RFVBAT_REG - VBAT register file register
+ */
+
+#define RFVBAT_INSTANCE_COUNT (1U) /*!< Number of instances of the RFVBAT module. */
+#define RFVBAT_IDX (0U) /*!< Instance number for RFVBAT. */
+
+/*******************************************************************************
+ * RFVBAT_REG - VBAT register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFVBAT_REG - VBAT register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFVBAT_REG register
+ */
+/*@{*/
+#define RFVBAT_RD_REG(base, index) (RFVBAT_REG_REG(base, index))
+#define RFVBAT_WR_REG(base, index, value) (RFVBAT_REG_REG(base, index) = (value))
+#define RFVBAT_RMW_REG(base, index, mask, value) (RFVBAT_WR_REG(base, index, (RFVBAT_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFVBAT_SET_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) |  (value)))
+#define RFVBAT_CLR_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) & ~(value)))
+#define RFVBAT_TOG_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFVBAT_REG bitfields
+ */
+
+/*!
+ * @name Register RFVBAT_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_LL field. */
+#define RFVBAT_RD_REG_LL(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_LL_MASK) >> RFVBAT_REG_LL_SHIFT)
+#define RFVBAT_BRD_REG_LL(base, index) (RFVBAT_RD_REG_LL(base, index))
+
+/*! @brief Set the LL field to a new value. */
+#define RFVBAT_WR_REG_LL(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_LL_MASK, RFVBAT_REG_LL(value)))
+#define RFVBAT_BWR_REG_LL(base, index, value) (RFVBAT_WR_REG_LL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_LH field. */
+#define RFVBAT_RD_REG_LH(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_LH_MASK) >> RFVBAT_REG_LH_SHIFT)
+#define RFVBAT_BRD_REG_LH(base, index) (RFVBAT_RD_REG_LH(base, index))
+
+/*! @brief Set the LH field to a new value. */
+#define RFVBAT_WR_REG_LH(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_LH_MASK, RFVBAT_REG_LH(value)))
+#define RFVBAT_BWR_REG_LH(base, index, value) (RFVBAT_WR_REG_LH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_HL field. */
+#define RFVBAT_RD_REG_HL(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_HL_MASK) >> RFVBAT_REG_HL_SHIFT)
+#define RFVBAT_BRD_REG_HL(base, index) (RFVBAT_RD_REG_HL(base, index))
+
+/*! @brief Set the HL field to a new value. */
+#define RFVBAT_WR_REG_HL(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_HL_MASK, RFVBAT_REG_HL(value)))
+#define RFVBAT_BWR_REG_HL(base, index, value) (RFVBAT_WR_REG_HL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_HH field. */
+#define RFVBAT_RD_REG_HH(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_HH_MASK) >> RFVBAT_REG_HH_SHIFT)
+#define RFVBAT_BRD_REG_HH(base, index) (RFVBAT_RD_REG_HH(base, index))
+
+/*! @brief Set the HH field to a new value. */
+#define RFVBAT_WR_REG_HH(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_HH_MASK, RFVBAT_REG_HH(value)))
+#define RFVBAT_BWR_REG_HH(base, index, value) (RFVBAT_WR_REG_HH(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 RNG
+ *
+ * Random Number Generator Accelerator
+ *
+ * Registers defined in this header file:
+ * - RNG_CR - RNGA Control Register
+ * - RNG_SR - RNGA Status Register
+ * - RNG_ER - RNGA Entropy Register
+ * - RNG_OR - RNGA Output Register
+ */
+
+#define RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
+#define RNG_IDX (0U) /*!< Instance number for RNG. */
+
+/*******************************************************************************
+ * RNG_CR - RNGA Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_CR - RNGA Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the operation of RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_CR register
+ */
+/*@{*/
+#define RNG_RD_CR(base)          (RNG_CR_REG(base))
+#define RNG_WR_CR(base, value)   (RNG_CR_REG(base) = (value))
+#define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value)))
+#define RNG_SET_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) |  (value)))
+#define RNG_CLR_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) & ~(value)))
+#define RNG_TOG_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RNG_CR bitfields
+ */
+
+/*!
+ * @name Register RNG_CR, field GO[0] (RW)
+ *
+ * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
+ * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
+ * OR[RANDOUT] with data.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_GO field. */
+#define RNG_RD_CR_GO(base)   ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT)
+#define RNG_BRD_CR_GO(base)  (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_GO_SHIFT))
+
+/*! @brief Set the GO field to a new value. */
+#define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value)))
+#define RNG_BWR_CR_GO(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_GO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field HA[1] (RW)
+ *
+ * Enables notification of security violations (via SR[SECV]). A security
+ * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
+ * After enabling notification of security violations, you must reset RNGA to
+ * disable them again.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_HA field. */
+#define RNG_RD_CR_HA(base)   ((RNG_CR_REG(base) & RNG_CR_HA_MASK) >> RNG_CR_HA_SHIFT)
+#define RNG_BRD_CR_HA(base)  (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_HA_SHIFT))
+
+/*! @brief Set the HA field to a new value. */
+#define RNG_WR_CR_HA(base, value) (RNG_RMW_CR(base, RNG_CR_HA_MASK, RNG_CR_HA(value)))
+#define RNG_BWR_CR_HA(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_HA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field INTM[2] (RW)
+ *
+ * Masks the triggering of an error interrupt to the interrupt controller when
+ * an OR underflow condition occurs. An OR underflow condition occurs when you
+ * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
+ *
+ * Values:
+ * - 0b0 - Not masked
+ * - 0b1 - Masked
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_INTM field. */
+#define RNG_RD_CR_INTM(base) ((RNG_CR_REG(base) & RNG_CR_INTM_MASK) >> RNG_CR_INTM_SHIFT)
+#define RNG_BRD_CR_INTM(base) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_INTM_SHIFT))
+
+/*! @brief Set the INTM field to a new value. */
+#define RNG_WR_CR_INTM(base, value) (RNG_RMW_CR(base, RNG_CR_INTM_MASK, RNG_CR_INTM(value)))
+#define RNG_BWR_CR_INTM(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_INTM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field CLRI[3] (WORZ)
+ *
+ * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
+ *
+ * Values:
+ * - 0b0 - Do not clear the interrupt.
+ * - 0b1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
+ *     the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
+ */
+/*@{*/
+/*! @brief Set the CLRI field to a new value. */
+#define RNG_WR_CR_CLRI(base, value) (RNG_RMW_CR(base, RNG_CR_CLRI_MASK, RNG_CR_CLRI(value)))
+#define RNG_BWR_CR_CLRI(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_CLRI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field SLP[4] (RW)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_SLP field. */
+#define RNG_RD_CR_SLP(base)  ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT)
+#define RNG_BRD_CR_SLP(base) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_SLP_SHIFT))
+
+/*! @brief Set the SLP field to a new value. */
+#define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value)))
+#define RNG_BWR_CR_SLP(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_SLP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_SR - RNGA Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_SR - RNGA Status Register (RO)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Indicates the status of RNGA. This register is read-only.
+ */
+/*!
+ * @name Constants and macros for entire RNG_SR register
+ */
+/*@{*/
+#define RNG_RD_SR(base)          (RNG_SR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RNG_SR bitfields
+ */
+
+/*!
+ * @name Register RNG_SR, field SECV[0] (RO)
+ *
+ * Used only when high assurance is enabled (CR[HA]). Indicates that a security
+ * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
+ * RNGA.
+ *
+ * Values:
+ * - 0b0 - No security violation
+ * - 0b1 - Security violation
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SECV field. */
+#define RNG_RD_SR_SECV(base) ((RNG_SR_REG(base) & RNG_SR_SECV_MASK) >> RNG_SR_SECV_SHIFT)
+#define RNG_BRD_SR_SECV(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_SECV_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field LRS[1] (RO)
+ *
+ * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
+ * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
+ * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
+ * After you read this register, RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_LRS field. */
+#define RNG_RD_SR_LRS(base)  ((RNG_SR_REG(base) & RNG_SR_LRS_MASK) >> RNG_SR_LRS_SHIFT)
+#define RNG_BRD_SR_LRS(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_LRS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field ORU[2] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last read
+ * this register (SR) or RNGA was reset, regardless of whether the error
+ * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
+ * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
+ * field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_ORU field. */
+#define RNG_RD_SR_ORU(base)  ((RNG_SR_REG(base) & RNG_SR_ORU_MASK) >> RNG_SR_ORU_SHIFT)
+#define RNG_BRD_SR_ORU(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_ORU_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field ERRI[3] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last
+ * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
+ * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
+ * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
+ * indicator (via CR[CLRI]), RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_ERRI field. */
+#define RNG_RD_SR_ERRI(base) ((RNG_SR_REG(base) & RNG_SR_ERRI_MASK) >> RNG_SR_ERRI_SHIFT)
+#define RNG_BRD_SR_ERRI(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_ERRI_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field SLP[4] (RO)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SLP field. */
+#define RNG_RD_SR_SLP(base)  ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT)
+#define RNG_BRD_SR_SLP(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_SLP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
+ *
+ * Indicates the number of random-data words that are in OR[RANDOUT], which
+ * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
+ * is not 0, then the contents of a random number contained in OR[RANDOUT] are
+ * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
+ *
+ * Values:
+ * - 0b00000000 - No words (empty)
+ * - 0b00000001 - One word (valid)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_LVL field. */
+#define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT)
+#define RNG_BRD_SR_OREG_LVL(base) (RNG_RD_SR_OREG_LVL(base))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
+ *
+ * Indicates the size of the Output (OR) register in terms of the number of
+ * 32-bit random-data words it can hold.
+ *
+ * Values:
+ * - 0b00000001 - One word (this value is fixed)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
+#define RNG_RD_SR_OREG_SIZE(base) ((RNG_SR_REG(base) & RNG_SR_OREG_SIZE_MASK) >> RNG_SR_OREG_SIZE_SHIFT)
+#define RNG_BRD_SR_OREG_SIZE(base) (RNG_RD_SR_OREG_SIZE(base))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_ER - RNGA Entropy Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_ER - RNGA Entropy Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies an entropy value that RNGA uses in addition to its ring oscillators
+ * to seed its pseudorandom algorithm. This is a write-only register; reads
+ * return all zeros.
+ */
+/*!
+ * @name Constants and macros for entire RNG_ER register
+ */
+/*@{*/
+#define RNG_RD_ER(base)          (RNG_ER_REG(base))
+#define RNG_WR_ER(base, value)   (RNG_ER_REG(base) = (value))
+#define RNG_RMW_ER(base, mask, value) (RNG_WR_ER(base, (RNG_RD_ER(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_OR - RNGA Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_OR - RNGA Output Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Stores a random-data word generated by RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_OR register
+ */
+/*@{*/
+#define RNG_RD_OR(base)          (RNG_OR_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 RTC
+ *
+ * Secure Real Time Clock
+ *
+ * Registers defined in this header file:
+ * - RTC_TSR - RTC Time Seconds Register
+ * - RTC_TPR - RTC Time Prescaler Register
+ * - RTC_TAR - RTC Time Alarm Register
+ * - RTC_TCR - RTC Time Compensation Register
+ * - RTC_CR - RTC Control Register
+ * - RTC_SR - RTC Status Register
+ * - RTC_LR - RTC Lock Register
+ * - RTC_IER - RTC Interrupt Enable Register
+ * - RTC_WAR - RTC Write Access Register
+ * - RTC_RAR - RTC Read Access Register
+ */
+
+#define RTC_INSTANCE_COUNT (1U) /*!< Number of instances of the RTC module. */
+#define RTC_IDX (0U) /*!< Instance number for RTC. */
+
+/*******************************************************************************
+ * RTC_TSR - RTC Time Seconds Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TSR - RTC Time Seconds Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TSR register
+ */
+/*@{*/
+#define RTC_RD_TSR(base)         (RTC_TSR_REG(base))
+#define RTC_WR_TSR(base, value)  (RTC_TSR_REG(base) = (value))
+#define RTC_RMW_TSR(base, mask, value) (RTC_WR_TSR(base, (RTC_RD_TSR(base) & ~(mask)) | (value)))
+#define RTC_SET_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) |  (value)))
+#define RTC_CLR_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) & ~(value)))
+#define RTC_TOG_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TPR - RTC Time Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TPR - RTC Time Prescaler Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TPR register
+ */
+/*@{*/
+#define RTC_RD_TPR(base)         (RTC_TPR_REG(base))
+#define RTC_WR_TPR(base, value)  (RTC_TPR_REG(base) = (value))
+#define RTC_RMW_TPR(base, mask, value) (RTC_WR_TPR(base, (RTC_RD_TPR(base) & ~(mask)) | (value)))
+#define RTC_SET_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) |  (value)))
+#define RTC_CLR_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) & ~(value)))
+#define RTC_TOG_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TPR bitfields
+ */
+
+/*!
+ * @name Register RTC_TPR, field TPR[15:0] (RW)
+ *
+ * When the time counter is enabled, the TPR is read only and increments every
+ * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
+ * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
+ * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
+ * to a logic zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TPR_TPR field. */
+#define RTC_RD_TPR_TPR(base) ((RTC_TPR_REG(base) & RTC_TPR_TPR_MASK) >> RTC_TPR_TPR_SHIFT)
+#define RTC_BRD_TPR_TPR(base) (RTC_RD_TPR_TPR(base))
+
+/*! @brief Set the TPR field to a new value. */
+#define RTC_WR_TPR_TPR(base, value) (RTC_RMW_TPR(base, RTC_TPR_TPR_MASK, RTC_TPR_TPR(value)))
+#define RTC_BWR_TPR_TPR(base, value) (RTC_WR_TPR_TPR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TAR - RTC Time Alarm Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TAR - RTC Time Alarm Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TAR register
+ */
+/*@{*/
+#define RTC_RD_TAR(base)         (RTC_TAR_REG(base))
+#define RTC_WR_TAR(base, value)  (RTC_TAR_REG(base) = (value))
+#define RTC_RMW_TAR(base, mask, value) (RTC_WR_TAR(base, (RTC_RD_TAR(base) & ~(mask)) | (value)))
+#define RTC_SET_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) |  (value)))
+#define RTC_CLR_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) & ~(value)))
+#define RTC_TOG_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TCR - RTC Time Compensation Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TCR - RTC Time Compensation Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TCR register
+ */
+/*@{*/
+#define RTC_RD_TCR(base)         (RTC_TCR_REG(base))
+#define RTC_WR_TCR(base, value)  (RTC_TCR_REG(base) = (value))
+#define RTC_RMW_TCR(base, mask, value) (RTC_WR_TCR(base, (RTC_RD_TCR(base) & ~(mask)) | (value)))
+#define RTC_SET_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) |  (value)))
+#define RTC_CLR_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) & ~(value)))
+#define RTC_TOG_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TCR bitfields
+ */
+
+/*!
+ * @name Register RTC_TCR, field TCR[7:0] (RW)
+ *
+ * Configures the number of 32.768 kHz clock cycles in each second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ *
+ * Values:
+ * - 0b10000000 - Time Prescaler Register overflows every 32896 clock cycles.
+ * - 0b11111111 - Time Prescaler Register overflows every 32769 clock cycles.
+ * - 0b00000000 - Time Prescaler Register overflows every 32768 clock cycles.
+ * - 0b00000001 - Time Prescaler Register overflows every 32767 clock cycles.
+ * - 0b01111111 - Time Prescaler Register overflows every 32641 clock cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCR field. */
+#define RTC_RD_TCR_TCR(base) ((RTC_TCR_REG(base) & RTC_TCR_TCR_MASK) >> RTC_TCR_TCR_SHIFT)
+#define RTC_BRD_TCR_TCR(base) (RTC_RD_TCR_TCR(base))
+
+/*! @brief Set the TCR field to a new value. */
+#define RTC_WR_TCR_TCR(base, value) (RTC_RMW_TCR(base, RTC_TCR_TCR_MASK, RTC_TCR_TCR(value)))
+#define RTC_BWR_TCR_TCR(base, value) (RTC_WR_TCR_TCR(base, value))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIR[15:8] (RW)
+ *
+ * Configures the compensation interval in seconds from 1 to 256 to control how
+ * frequently the TCR should adjust the number of 32.768 kHz cycles in each
+ * second. The value written should be one less than the number of seconds. For
+ * example, write zero to configure for a compensation interval of one second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIR field. */
+#define RTC_RD_TCR_CIR(base) ((RTC_TCR_REG(base) & RTC_TCR_CIR_MASK) >> RTC_TCR_CIR_SHIFT)
+#define RTC_BRD_TCR_CIR(base) (RTC_RD_TCR_CIR(base))
+
+/*! @brief Set the CIR field to a new value. */
+#define RTC_WR_TCR_CIR(base, value) (RTC_RMW_TCR(base, RTC_TCR_CIR_MASK, RTC_TCR_CIR(value)))
+#define RTC_BWR_TCR_CIR(base, value) (RTC_WR_TCR_CIR(base, value))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field TCV[23:16] (RO)
+ *
+ * Current value used by the compensation logic for the present second interval.
+ * Updated once a second if the CIC equals 0 with the contents of the TCR field.
+ * If the CIC does not equal zero then it is loaded with zero (compensation is
+ * not enabled for that second increment).
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCV field. */
+#define RTC_RD_TCR_TCV(base) ((RTC_TCR_REG(base) & RTC_TCR_TCV_MASK) >> RTC_TCR_TCV_SHIFT)
+#define RTC_BRD_TCR_TCV(base) (RTC_RD_TCR_TCV(base))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIC[31:24] (RO)
+ *
+ * Current value of the compensation interval counter. If the compensation
+ * interval counter equals zero then it is loaded with the contents of the CIR. If the
+ * CIC does not equal zero then it is decremented once a second.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIC field. */
+#define RTC_RD_TCR_CIC(base) ((RTC_TCR_REG(base) & RTC_TCR_CIC_MASK) >> RTC_TCR_CIC_SHIFT)
+#define RTC_BRD_TCR_CIC(base) (RTC_RD_TCR_CIC(base))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_CR - RTC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_CR - RTC Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_CR register
+ */
+/*@{*/
+#define RTC_RD_CR(base)          (RTC_CR_REG(base))
+#define RTC_WR_CR(base, value)   (RTC_CR_REG(base) = (value))
+#define RTC_RMW_CR(base, mask, value) (RTC_WR_CR(base, (RTC_RD_CR(base) & ~(mask)) | (value)))
+#define RTC_SET_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) |  (value)))
+#define RTC_CLR_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) & ~(value)))
+#define RTC_TOG_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_CR bitfields
+ */
+
+/*!
+ * @name Register RTC_CR, field SWR[0] (RW)
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
+ *     RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
+ *     explicitly clearing it.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SWR field. */
+#define RTC_RD_CR_SWR(base)  ((RTC_CR_REG(base) & RTC_CR_SWR_MASK) >> RTC_CR_SWR_SHIFT)
+#define RTC_BRD_CR_SWR(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT))
+
+/*! @brief Set the SWR field to a new value. */
+#define RTC_WR_CR_SWR(base, value) (RTC_RMW_CR(base, RTC_CR_SWR_MASK, RTC_CR_SWR(value)))
+#define RTC_BWR_CR_SWR(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPE[1] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0b0 - Wakeup pin is disabled.
+ * - 0b1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPE field. */
+#define RTC_RD_CR_WPE(base)  ((RTC_CR_REG(base) & RTC_CR_WPE_MASK) >> RTC_CR_WPE_SHIFT)
+#define RTC_BRD_CR_WPE(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT))
+
+/*! @brief Set the WPE field to a new value. */
+#define RTC_WR_CR_WPE(base, value) (RTC_RMW_CR(base, RTC_CR_WPE_MASK, RTC_CR_WPE(value)))
+#define RTC_BWR_CR_WPE(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SUP[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Non-supervisor mode write accesses are not supported and generate a
+ *     bus error.
+ * - 0b1 - Non-supervisor mode write accesses are supported.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SUP field. */
+#define RTC_RD_CR_SUP(base)  ((RTC_CR_REG(base) & RTC_CR_SUP_MASK) >> RTC_CR_SUP_SHIFT)
+#define RTC_BRD_CR_SUP(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT))
+
+/*! @brief Set the SUP field to a new value. */
+#define RTC_WR_CR_SUP(base, value) (RTC_RMW_CR(base, RTC_CR_SUP_MASK, RTC_CR_SUP(value)))
+#define RTC_BWR_CR_SUP(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field UM[3] (RW)
+ *
+ * Allows SR[TCE] to be written even when the Status Register is locked. When
+ * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
+ * the SR[TCE] is clear.
+ *
+ * Values:
+ * - 0b0 - Registers cannot be written when locked.
+ * - 0b1 - Registers can be written when locked under limited conditions.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_UM field. */
+#define RTC_RD_CR_UM(base)   ((RTC_CR_REG(base) & RTC_CR_UM_MASK) >> RTC_CR_UM_SHIFT)
+#define RTC_BRD_CR_UM(base)  (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT))
+
+/*! @brief Set the UM field to a new value. */
+#define RTC_WR_CR_UM(base, value) (RTC_RMW_CR(base, RTC_CR_UM_MASK, RTC_CR_UM(value)))
+#define RTC_BWR_CR_UM(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPS[4] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0b0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ * - 0b1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup
+ *     pin is turned on and the 32kHz clock is output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPS field. */
+#define RTC_RD_CR_WPS(base)  ((RTC_CR_REG(base) & RTC_CR_WPS_MASK) >> RTC_CR_WPS_SHIFT)
+#define RTC_BRD_CR_WPS(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT))
+
+/*! @brief Set the WPS field to a new value. */
+#define RTC_WR_CR_WPS(base, value) (RTC_RMW_CR(base, RTC_CR_WPS_MASK, RTC_CR_WPS(value)))
+#define RTC_BWR_CR_WPS(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field OSCE[8] (RW)
+ *
+ * Values:
+ * - 0b0 - 32.768 kHz oscillator is disabled.
+ * - 0b1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
+ *     oscillator startup time before enabling the time counter to allow the 32.768
+ *     kHz clock time to stabilize.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_OSCE field. */
+#define RTC_RD_CR_OSCE(base) ((RTC_CR_REG(base) & RTC_CR_OSCE_MASK) >> RTC_CR_OSCE_SHIFT)
+#define RTC_BRD_CR_OSCE(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT))
+
+/*! @brief Set the OSCE field to a new value. */
+#define RTC_WR_CR_OSCE(base, value) (RTC_RMW_CR(base, RTC_CR_OSCE_MASK, RTC_CR_OSCE(value)))
+#define RTC_BWR_CR_OSCE(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field CLKO[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The 32 kHz clock is output to other peripherals.
+ * - 0b1 - The 32 kHz clock is not output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_CLKO field. */
+#define RTC_RD_CR_CLKO(base) ((RTC_CR_REG(base) & RTC_CR_CLKO_MASK) >> RTC_CR_CLKO_SHIFT)
+#define RTC_BRD_CR_CLKO(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT))
+
+/*! @brief Set the CLKO field to a new value. */
+#define RTC_WR_CR_CLKO(base, value) (RTC_RMW_CR(base, RTC_CR_CLKO_MASK, RTC_CR_CLKO(value)))
+#define RTC_BWR_CR_CLKO(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC16P[10] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC16P field. */
+#define RTC_RD_CR_SC16P(base) ((RTC_CR_REG(base) & RTC_CR_SC16P_MASK) >> RTC_CR_SC16P_SHIFT)
+#define RTC_BRD_CR_SC16P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT))
+
+/*! @brief Set the SC16P field to a new value. */
+#define RTC_WR_CR_SC16P(base, value) (RTC_RMW_CR(base, RTC_CR_SC16P_MASK, RTC_CR_SC16P(value)))
+#define RTC_BWR_CR_SC16P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC8P[11] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC8P field. */
+#define RTC_RD_CR_SC8P(base) ((RTC_CR_REG(base) & RTC_CR_SC8P_MASK) >> RTC_CR_SC8P_SHIFT)
+#define RTC_BRD_CR_SC8P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT))
+
+/*! @brief Set the SC8P field to a new value. */
+#define RTC_WR_CR_SC8P(base, value) (RTC_RMW_CR(base, RTC_CR_SC8P_MASK, RTC_CR_SC8P(value)))
+#define RTC_BWR_CR_SC8P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC4P[12] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC4P field. */
+#define RTC_RD_CR_SC4P(base) ((RTC_CR_REG(base) & RTC_CR_SC4P_MASK) >> RTC_CR_SC4P_SHIFT)
+#define RTC_BRD_CR_SC4P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT))
+
+/*! @brief Set the SC4P field to a new value. */
+#define RTC_WR_CR_SC4P(base, value) (RTC_RMW_CR(base, RTC_CR_SC4P_MASK, RTC_CR_SC4P(value)))
+#define RTC_BWR_CR_SC4P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC2P[13] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC2P field. */
+#define RTC_RD_CR_SC2P(base) ((RTC_CR_REG(base) & RTC_CR_SC2P_MASK) >> RTC_CR_SC2P_SHIFT)
+#define RTC_BRD_CR_SC2P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT))
+
+/*! @brief Set the SC2P field to a new value. */
+#define RTC_WR_CR_SC2P(base, value) (RTC_RMW_CR(base, RTC_CR_SC2P_MASK, RTC_CR_SC2P(value)))
+#define RTC_BWR_CR_SC2P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_SR - RTC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_SR - RTC Status Register (RW)
+ *
+ * Reset value: 0x00000001U
+ */
+/*!
+ * @name Constants and macros for entire RTC_SR register
+ */
+/*@{*/
+#define RTC_RD_SR(base)          (RTC_SR_REG(base))
+#define RTC_WR_SR(base, value)   (RTC_SR_REG(base) = (value))
+#define RTC_RMW_SR(base, mask, value) (RTC_WR_SR(base, (RTC_RD_SR(base) & ~(mask)) | (value)))
+#define RTC_SET_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) |  (value)))
+#define RTC_CLR_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) & ~(value)))
+#define RTC_TOG_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_SR bitfields
+ */
+
+/*!
+ * @name Register RTC_SR, field TIF[0] (RO)
+ *
+ * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
+ * do not increment and read as zero when this bit is set. This bit is cleared by
+ * writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0b0 - Time is valid.
+ * - 0b1 - Time is invalid and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TIF field. */
+#define RTC_RD_SR_TIF(base)  ((RTC_SR_REG(base) & RTC_SR_TIF_MASK) >> RTC_SR_TIF_SHIFT)
+#define RTC_BRD_SR_TIF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TIF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TOF[1] (RO)
+ *
+ * Time overflow flag is set when the time counter is enabled and overflows. The
+ * TSR and TPR do not increment and read as zero when this bit is set. This bit
+ * is cleared by writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0b0 - Time overflow has not occurred.
+ * - 0b1 - Time overflow has occurred and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TOF field. */
+#define RTC_RD_SR_TOF(base)  ((RTC_SR_REG(base) & RTC_SR_TOF_MASK) >> RTC_SR_TOF_SHIFT)
+#define RTC_BRD_SR_TOF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TOF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TAF[2] (RO)
+ *
+ * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
+ * increments. This bit is cleared by writing the TAR register.
+ *
+ * Values:
+ * - 0b0 - Time alarm has not occurred.
+ * - 0b1 - Time alarm has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TAF field. */
+#define RTC_RD_SR_TAF(base)  ((RTC_SR_REG(base) & RTC_SR_TAF_MASK) >> RTC_SR_TAF_SHIFT)
+#define RTC_BRD_SR_TAF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TAF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TCE[4] (RW)
+ *
+ * When time counter is disabled the TSR register and TPR register are
+ * writeable, but do not increment. When time counter is enabled the TSR register and TPR
+ * register are not writeable, but increment.
+ *
+ * Values:
+ * - 0b0 - Time counter is disabled.
+ * - 0b1 - Time counter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TCE field. */
+#define RTC_RD_SR_TCE(base)  ((RTC_SR_REG(base) & RTC_SR_TCE_MASK) >> RTC_SR_TCE_SHIFT)
+#define RTC_BRD_SR_TCE(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT))
+
+/*! @brief Set the TCE field to a new value. */
+#define RTC_WR_SR_TCE(base, value) (RTC_RMW_SR(base, RTC_SR_TCE_MASK, RTC_SR_TCE(value)))
+#define RTC_BWR_SR_TCE(base, value) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_LR - RTC Lock Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_LR - RTC Lock Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_LR register
+ */
+/*@{*/
+#define RTC_RD_LR(base)          (RTC_LR_REG(base))
+#define RTC_WR_LR(base, value)   (RTC_LR_REG(base) = (value))
+#define RTC_RMW_LR(base, mask, value) (RTC_WR_LR(base, (RTC_RD_LR(base) & ~(mask)) | (value)))
+#define RTC_SET_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) |  (value)))
+#define RTC_CLR_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) & ~(value)))
+#define RTC_TOG_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_LR bitfields
+ */
+
+/*!
+ * @name Register RTC_LR, field TCL[3] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Time Compensation Register is locked and writes are ignored.
+ * - 0b1 - Time Compensation Register is not locked and writes complete as
+ *     normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_TCL field. */
+#define RTC_RD_LR_TCL(base)  ((RTC_LR_REG(base) & RTC_LR_TCL_MASK) >> RTC_LR_TCL_SHIFT)
+#define RTC_BRD_LR_TCL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT))
+
+/*! @brief Set the TCL field to a new value. */
+#define RTC_WR_LR_TCL(base, value) (RTC_RMW_LR(base, RTC_LR_TCL_MASK, RTC_LR_TCL(value)))
+#define RTC_BWR_LR_TCL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field CRL[4] (RW)
+ *
+ * After being cleared, this bit can only be set by VBAT POR.
+ *
+ * Values:
+ * - 0b0 - Control Register is locked and writes are ignored.
+ * - 0b1 - Control Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_CRL field. */
+#define RTC_RD_LR_CRL(base)  ((RTC_LR_REG(base) & RTC_LR_CRL_MASK) >> RTC_LR_CRL_SHIFT)
+#define RTC_BRD_LR_CRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT))
+
+/*! @brief Set the CRL field to a new value. */
+#define RTC_WR_LR_CRL(base, value) (RTC_RMW_LR(base, RTC_LR_CRL_MASK, RTC_LR_CRL(value)))
+#define RTC_BWR_LR_CRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field SRL[5] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Status Register is locked and writes are ignored.
+ * - 0b1 - Status Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_SRL field. */
+#define RTC_RD_LR_SRL(base)  ((RTC_LR_REG(base) & RTC_LR_SRL_MASK) >> RTC_LR_SRL_SHIFT)
+#define RTC_BRD_LR_SRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT))
+
+/*! @brief Set the SRL field to a new value. */
+#define RTC_WR_LR_SRL(base, value) (RTC_RMW_LR(base, RTC_LR_SRL_MASK, RTC_LR_SRL(value)))
+#define RTC_BWR_LR_SRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field LRL[6] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Lock Register is locked and writes are ignored.
+ * - 0b1 - Lock Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_LRL field. */
+#define RTC_RD_LR_LRL(base)  ((RTC_LR_REG(base) & RTC_LR_LRL_MASK) >> RTC_LR_LRL_SHIFT)
+#define RTC_BRD_LR_LRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT))
+
+/*! @brief Set the LRL field to a new value. */
+#define RTC_WR_LR_LRL(base, value) (RTC_RMW_LR(base, RTC_LR_LRL_MASK, RTC_LR_LRL(value)))
+#define RTC_BWR_LR_LRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_IER - RTC Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_IER - RTC Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00000007U
+ */
+/*!
+ * @name Constants and macros for entire RTC_IER register
+ */
+/*@{*/
+#define RTC_RD_IER(base)         (RTC_IER_REG(base))
+#define RTC_WR_IER(base, value)  (RTC_IER_REG(base) = (value))
+#define RTC_RMW_IER(base, mask, value) (RTC_WR_IER(base, (RTC_RD_IER(base) & ~(mask)) | (value)))
+#define RTC_SET_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) |  (value)))
+#define RTC_CLR_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) & ~(value)))
+#define RTC_TOG_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_IER bitfields
+ */
+
+/*!
+ * @name Register RTC_IER, field TIIE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Time invalid flag does not generate an interrupt.
+ * - 0b1 - Time invalid flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TIIE field. */
+#define RTC_RD_IER_TIIE(base) ((RTC_IER_REG(base) & RTC_IER_TIIE_MASK) >> RTC_IER_TIIE_SHIFT)
+#define RTC_BRD_IER_TIIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT))
+
+/*! @brief Set the TIIE field to a new value. */
+#define RTC_WR_IER_TIIE(base, value) (RTC_RMW_IER(base, RTC_IER_TIIE_MASK, RTC_IER_TIIE(value)))
+#define RTC_BWR_IER_TIIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TOIE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Time overflow flag does not generate an interrupt.
+ * - 0b1 - Time overflow flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TOIE field. */
+#define RTC_RD_IER_TOIE(base) ((RTC_IER_REG(base) & RTC_IER_TOIE_MASK) >> RTC_IER_TOIE_SHIFT)
+#define RTC_BRD_IER_TOIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT))
+
+/*! @brief Set the TOIE field to a new value. */
+#define RTC_WR_IER_TOIE(base, value) (RTC_RMW_IER(base, RTC_IER_TOIE_MASK, RTC_IER_TOIE(value)))
+#define RTC_BWR_IER_TOIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TAIE[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Time alarm flag does not generate an interrupt.
+ * - 0b1 - Time alarm flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TAIE field. */
+#define RTC_RD_IER_TAIE(base) ((RTC_IER_REG(base) & RTC_IER_TAIE_MASK) >> RTC_IER_TAIE_SHIFT)
+#define RTC_BRD_IER_TAIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT))
+
+/*! @brief Set the TAIE field to a new value. */
+#define RTC_WR_IER_TAIE(base, value) (RTC_RMW_IER(base, RTC_IER_TAIE_MASK, RTC_IER_TAIE(value)))
+#define RTC_BWR_IER_TAIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TSIE[4] (RW)
+ *
+ * The seconds interrupt is an edge-sensitive interrupt with a dedicated
+ * interrupt vector. It is generated once a second and requires no software overhead
+ * (there is no corresponding status flag to clear).
+ *
+ * Values:
+ * - 0b0 - Seconds interrupt is disabled.
+ * - 0b1 - Seconds interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TSIE field. */
+#define RTC_RD_IER_TSIE(base) ((RTC_IER_REG(base) & RTC_IER_TSIE_MASK) >> RTC_IER_TSIE_SHIFT)
+#define RTC_BRD_IER_TSIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT))
+
+/*! @brief Set the TSIE field to a new value. */
+#define RTC_WR_IER_TSIE(base, value) (RTC_RMW_IER(base, RTC_IER_TSIE_MASK, RTC_IER_TSIE(value)))
+#define RTC_BWR_IER_TSIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field WPON[7] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices. Whenever the
+ * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - If the wakeup pin is enabled, then the wakeup pin will assert.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_WPON field. */
+#define RTC_RD_IER_WPON(base) ((RTC_IER_REG(base) & RTC_IER_WPON_MASK) >> RTC_IER_WPON_SHIFT)
+#define RTC_BRD_IER_WPON(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT))
+
+/*! @brief Set the WPON field to a new value. */
+#define RTC_WR_IER_WPON(base, value) (RTC_RMW_IER(base, RTC_IER_WPON_MASK, RTC_IER_WPON(value)))
+#define RTC_BWR_IER_WPON(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_WAR - RTC Write Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_WAR - RTC Write Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_WAR register
+ */
+/*@{*/
+#define RTC_RD_WAR(base)         (RTC_WAR_REG(base))
+#define RTC_WR_WAR(base, value)  (RTC_WAR_REG(base) = (value))
+#define RTC_RMW_WAR(base, mask, value) (RTC_WR_WAR(base, (RTC_RD_WAR(base) & ~(mask)) | (value)))
+#define RTC_SET_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) |  (value)))
+#define RTC_CLR_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) & ~(value)))
+#define RTC_TOG_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_WAR bitfields
+ */
+
+/*!
+ * @name Register RTC_WAR, field TSRW[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Seconds Register are ignored.
+ * - 0b1 - Writes to the Time Seconds Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TSRW field. */
+#define RTC_RD_WAR_TSRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TSRW_MASK) >> RTC_WAR_TSRW_SHIFT)
+#define RTC_BRD_WAR_TSRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TSRW_SHIFT))
+
+/*! @brief Set the TSRW field to a new value. */
+#define RTC_WR_WAR_TSRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TSRW_MASK, RTC_WAR_TSRW(value)))
+#define RTC_BWR_WAR_TSRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TSRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TPRW[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Prescaler Register are ignored.
+ * - 0b1 - Writes to the Time Prescaler Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TPRW field. */
+#define RTC_RD_WAR_TPRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TPRW_MASK) >> RTC_WAR_TPRW_SHIFT)
+#define RTC_BRD_WAR_TPRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TPRW_SHIFT))
+
+/*! @brief Set the TPRW field to a new value. */
+#define RTC_WR_WAR_TPRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TPRW_MASK, RTC_WAR_TPRW(value)))
+#define RTC_BWR_WAR_TPRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TPRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TARW[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Alarm Register are ignored.
+ * - 0b1 - Writes to the Time Alarm Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TARW field. */
+#define RTC_RD_WAR_TARW(base) ((RTC_WAR_REG(base) & RTC_WAR_TARW_MASK) >> RTC_WAR_TARW_SHIFT)
+#define RTC_BRD_WAR_TARW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TARW_SHIFT))
+
+/*! @brief Set the TARW field to a new value. */
+#define RTC_WR_WAR_TARW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TARW_MASK, RTC_WAR_TARW(value)))
+#define RTC_BWR_WAR_TARW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TARW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TCRW[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Compensation Register are ignored.
+ * - 0b1 - Writes to the Time Compensation Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TCRW field. */
+#define RTC_RD_WAR_TCRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TCRW_MASK) >> RTC_WAR_TCRW_SHIFT)
+#define RTC_BRD_WAR_TCRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TCRW_SHIFT))
+
+/*! @brief Set the TCRW field to a new value. */
+#define RTC_WR_WAR_TCRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TCRW_MASK, RTC_WAR_TCRW(value)))
+#define RTC_BWR_WAR_TCRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TCRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field CRW[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Control Register are ignored.
+ * - 0b1 - Writes to the Control Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_CRW field. */
+#define RTC_RD_WAR_CRW(base) ((RTC_WAR_REG(base) & RTC_WAR_CRW_MASK) >> RTC_WAR_CRW_SHIFT)
+#define RTC_BRD_WAR_CRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_CRW_SHIFT))
+
+/*! @brief Set the CRW field to a new value. */
+#define RTC_WR_WAR_CRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_CRW_MASK, RTC_WAR_CRW(value)))
+#define RTC_BWR_WAR_CRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_CRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field SRW[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Status Register are ignored.
+ * - 0b1 - Writes to the Status Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_SRW field. */
+#define RTC_RD_WAR_SRW(base) ((RTC_WAR_REG(base) & RTC_WAR_SRW_MASK) >> RTC_WAR_SRW_SHIFT)
+#define RTC_BRD_WAR_SRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_SRW_SHIFT))
+
+/*! @brief Set the SRW field to a new value. */
+#define RTC_WR_WAR_SRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_SRW_MASK, RTC_WAR_SRW(value)))
+#define RTC_BWR_WAR_SRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_SRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field LRW[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Lock Register are ignored.
+ * - 0b1 - Writes to the Lock Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_LRW field. */
+#define RTC_RD_WAR_LRW(base) ((RTC_WAR_REG(base) & RTC_WAR_LRW_MASK) >> RTC_WAR_LRW_SHIFT)
+#define RTC_BRD_WAR_LRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_LRW_SHIFT))
+
+/*! @brief Set the LRW field to a new value. */
+#define RTC_WR_WAR_LRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_LRW_MASK, RTC_WAR_LRW(value)))
+#define RTC_BWR_WAR_LRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_LRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field IERW[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Interupt Enable Register are ignored.
+ * - 0b1 - Writes to the Interrupt Enable Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_IERW field. */
+#define RTC_RD_WAR_IERW(base) ((RTC_WAR_REG(base) & RTC_WAR_IERW_MASK) >> RTC_WAR_IERW_SHIFT)
+#define RTC_BRD_WAR_IERW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_IERW_SHIFT))
+
+/*! @brief Set the IERW field to a new value. */
+#define RTC_WR_WAR_IERW(base, value) (RTC_RMW_WAR(base, RTC_WAR_IERW_MASK, RTC_WAR_IERW(value)))
+#define RTC_BWR_WAR_IERW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_IERW_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_RAR - RTC Read Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_RAR - RTC Read Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_RAR register
+ */
+/*@{*/
+#define RTC_RD_RAR(base)         (RTC_RAR_REG(base))
+#define RTC_WR_RAR(base, value)  (RTC_RAR_REG(base) = (value))
+#define RTC_RMW_RAR(base, mask, value) (RTC_WR_RAR(base, (RTC_RD_RAR(base) & ~(mask)) | (value)))
+#define RTC_SET_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) |  (value)))
+#define RTC_CLR_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) & ~(value)))
+#define RTC_TOG_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_RAR bitfields
+ */
+
+/*!
+ * @name Register RTC_RAR, field TSRR[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Seconds Register are ignored.
+ * - 0b1 - Reads to the Time Seconds Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TSRR field. */
+#define RTC_RD_RAR_TSRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TSRR_MASK) >> RTC_RAR_TSRR_SHIFT)
+#define RTC_BRD_RAR_TSRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TSRR_SHIFT))
+
+/*! @brief Set the TSRR field to a new value. */
+#define RTC_WR_RAR_TSRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TSRR_MASK, RTC_RAR_TSRR(value)))
+#define RTC_BWR_RAR_TSRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TSRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TPRR[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Pprescaler Register are ignored.
+ * - 0b1 - Reads to the Time Prescaler Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TPRR field. */
+#define RTC_RD_RAR_TPRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TPRR_MASK) >> RTC_RAR_TPRR_SHIFT)
+#define RTC_BRD_RAR_TPRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TPRR_SHIFT))
+
+/*! @brief Set the TPRR field to a new value. */
+#define RTC_WR_RAR_TPRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TPRR_MASK, RTC_RAR_TPRR(value)))
+#define RTC_BWR_RAR_TPRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TPRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TARR[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Alarm Register are ignored.
+ * - 0b1 - Reads to the Time Alarm Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TARR field. */
+#define RTC_RD_RAR_TARR(base) ((RTC_RAR_REG(base) & RTC_RAR_TARR_MASK) >> RTC_RAR_TARR_SHIFT)
+#define RTC_BRD_RAR_TARR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TARR_SHIFT))
+
+/*! @brief Set the TARR field to a new value. */
+#define RTC_WR_RAR_TARR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TARR_MASK, RTC_RAR_TARR(value)))
+#define RTC_BWR_RAR_TARR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TARR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TCRR[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Compensation Register are ignored.
+ * - 0b1 - Reads to the Time Compensation Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TCRR field. */
+#define RTC_RD_RAR_TCRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TCRR_MASK) >> RTC_RAR_TCRR_SHIFT)
+#define RTC_BRD_RAR_TCRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TCRR_SHIFT))
+
+/*! @brief Set the TCRR field to a new value. */
+#define RTC_WR_RAR_TCRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TCRR_MASK, RTC_RAR_TCRR(value)))
+#define RTC_BWR_RAR_TCRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TCRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field CRR[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Control Register are ignored.
+ * - 0b1 - Reads to the Control Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_CRR field. */
+#define RTC_RD_RAR_CRR(base) ((RTC_RAR_REG(base) & RTC_RAR_CRR_MASK) >> RTC_RAR_CRR_SHIFT)
+#define RTC_BRD_RAR_CRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_CRR_SHIFT))
+
+/*! @brief Set the CRR field to a new value. */
+#define RTC_WR_RAR_CRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_CRR_MASK, RTC_RAR_CRR(value)))
+#define RTC_BWR_RAR_CRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_CRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field SRR[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Status Register are ignored.
+ * - 0b1 - Reads to the Status Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_SRR field. */
+#define RTC_RD_RAR_SRR(base) ((RTC_RAR_REG(base) & RTC_RAR_SRR_MASK) >> RTC_RAR_SRR_SHIFT)
+#define RTC_BRD_RAR_SRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_SRR_SHIFT))
+
+/*! @brief Set the SRR field to a new value. */
+#define RTC_WR_RAR_SRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_SRR_MASK, RTC_RAR_SRR(value)))
+#define RTC_BWR_RAR_SRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_SRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field LRR[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Lock Register are ignored.
+ * - 0b1 - Reads to the Lock Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_LRR field. */
+#define RTC_RD_RAR_LRR(base) ((RTC_RAR_REG(base) & RTC_RAR_LRR_MASK) >> RTC_RAR_LRR_SHIFT)
+#define RTC_BRD_RAR_LRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_LRR_SHIFT))
+
+/*! @brief Set the LRR field to a new value. */
+#define RTC_WR_RAR_LRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_LRR_MASK, RTC_RAR_LRR(value)))
+#define RTC_BWR_RAR_LRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_LRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field IERR[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Interrupt Enable Register are ignored.
+ * - 0b1 - Reads to the Interrupt Enable Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_IERR field. */
+#define RTC_RD_RAR_IERR(base) ((RTC_RAR_REG(base) & RTC_RAR_IERR_MASK) >> RTC_RAR_IERR_SHIFT)
+#define RTC_BRD_RAR_IERR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_IERR_SHIFT))
+
+/*! @brief Set the IERR field to a new value. */
+#define RTC_WR_RAR_IERR(base, value) (RTC_RMW_RAR(base, RTC_RAR_IERR_MASK, RTC_RAR_IERR(value)))
+#define RTC_BWR_RAR_IERR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_IERR_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 SDHC
+ *
+ * Secured Digital Host Controller
+ *
+ * Registers defined in this header file:
+ * - SDHC_DSADDR - DMA System Address register
+ * - SDHC_BLKATTR - Block Attributes register
+ * - SDHC_CMDARG - Command Argument register
+ * - SDHC_XFERTYP - Transfer Type register
+ * - SDHC_CMDRSP - Command Response 0
+ * - SDHC_DATPORT - Buffer Data Port register
+ * - SDHC_PRSSTAT - Present State register
+ * - SDHC_PROCTL - Protocol Control register
+ * - SDHC_SYSCTL - System Control register
+ * - SDHC_IRQSTAT - Interrupt Status register
+ * - SDHC_IRQSTATEN - Interrupt Status Enable register
+ * - SDHC_IRQSIGEN - Interrupt Signal Enable register
+ * - SDHC_AC12ERR - Auto CMD12 Error Status Register
+ * - SDHC_HTCAPBLT - Host Controller Capabilities
+ * - SDHC_WML - Watermark Level Register
+ * - SDHC_FEVT - Force Event register
+ * - SDHC_ADMAES - ADMA Error Status register
+ * - SDHC_ADSADDR - ADMA System Addressregister
+ * - SDHC_VENDOR - Vendor Specific register
+ * - SDHC_MMCBOOT - MMC Boot register
+ * - SDHC_HOSTVER - Host Controller Version
+ */
+
+#define SDHC_INSTANCE_COUNT (1U) /*!< Number of instances of the SDHC module. */
+#define SDHC_IDX (0U) /*!< Instance number for SDHC. */
+
+/*******************************************************************************
+ * SDHC_DSADDR - DMA System Address register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_DSADDR - DMA System Address register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for DMA
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_DSADDR register
+ */
+/*@{*/
+#define SDHC_RD_DSADDR(base)     (SDHC_DSADDR_REG(base))
+#define SDHC_WR_DSADDR(base, value) (SDHC_DSADDR_REG(base) = (value))
+#define SDHC_RMW_DSADDR(base, mask, value) (SDHC_WR_DSADDR(base, (SDHC_RD_DSADDR(base) & ~(mask)) | (value)))
+#define SDHC_SET_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) |  (value)))
+#define SDHC_CLR_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) & ~(value)))
+#define SDHC_TOG_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_DSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
+ *
+ * Contains the 32-bit system memory address for a DMA transfer. Because the
+ * address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
+ * When the SDHC stops a DMA transfer, this register points to the system address
+ * of the next contiguous data position. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read operation
+ * during transfers may return an invalid value. The host driver shall initialize
+ * this register before starting a DMA transaction. After DMA has stopped, the
+ * system address of the next contiguous data position can be read from this register.
+ * This register is protected during a data transfer. When data lines are
+ * active, write to this register is ignored. The host driver shall wait, until
+ * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
+ * not support a virtual memory system. It supports only continuous physical
+ * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
+ * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
+ * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
+ * automatically alters the value of internal address counter, so SW cannot
+ * change this register when IRQSTAT[TC] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_DSADDR_DSADDR field. */
+#define SDHC_RD_DSADDR_DSADDR(base) ((SDHC_DSADDR_REG(base) & SDHC_DSADDR_DSADDR_MASK) >> SDHC_DSADDR_DSADDR_SHIFT)
+#define SDHC_BRD_DSADDR_DSADDR(base) (SDHC_RD_DSADDR_DSADDR(base))
+
+/*! @brief Set the DSADDR field to a new value. */
+#define SDHC_WR_DSADDR_DSADDR(base, value) (SDHC_RMW_DSADDR(base, SDHC_DSADDR_DSADDR_MASK, SDHC_DSADDR_DSADDR(value)))
+#define SDHC_BWR_DSADDR_DSADDR(base, value) (SDHC_WR_DSADDR_DSADDR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_BLKATTR - Block Attributes register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_BLKATTR - Block Attributes register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to configure the number of data blocks and the number
+ * of bytes in each block.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_BLKATTR register
+ */
+/*@{*/
+#define SDHC_RD_BLKATTR(base)    (SDHC_BLKATTR_REG(base))
+#define SDHC_WR_BLKATTR(base, value) (SDHC_BLKATTR_REG(base) = (value))
+#define SDHC_RMW_BLKATTR(base, mask, value) (SDHC_WR_BLKATTR(base, (SDHC_RD_BLKATTR(base) & ~(mask)) | (value)))
+#define SDHC_SET_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) |  (value)))
+#define SDHC_CLR_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) & ~(value)))
+#define SDHC_TOG_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_BLKATTR bitfields
+ */
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
+ *
+ * Specifies the block size for block data transfers. Values ranging from 1 byte
+ * up to the maximum buffer size can be set. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read
+ * operations during transfers may return an invalid value, and write operations will be
+ * ignored.
+ *
+ * Values:
+ * - 0b0000000000000 - No data transfer.
+ * - 0b0000000000001 - 1 Byte
+ * - 0b0000000000010 - 2 Bytes
+ * - 0b0000000000011 - 3 Bytes
+ * - 0b0000000000100 - 4 Bytes
+ * - 0b0000111111111 - 511 Bytes
+ * - 0b0001000000000 - 512 Bytes
+ * - 0b0100000000000 - 2048 Bytes
+ * - 0b1000000000000 - 4096 Bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field. */
+#define SDHC_RD_BLKATTR_BLKSIZE(base) ((SDHC_BLKATTR_REG(base) & SDHC_BLKATTR_BLKSIZE_MASK) >> SDHC_BLKATTR_BLKSIZE_SHIFT)
+#define SDHC_BRD_BLKATTR_BLKSIZE(base) (SDHC_RD_BLKATTR_BLKSIZE(base))
+
+/*! @brief Set the BLKSIZE field to a new value. */
+#define SDHC_WR_BLKATTR_BLKSIZE(base, value) (SDHC_RMW_BLKATTR(base, SDHC_BLKATTR_BLKSIZE_MASK, SDHC_BLKATTR_BLKSIZE(value)))
+#define SDHC_BWR_BLKATTR_BLKSIZE(base, value) (SDHC_WR_BLKATTR_BLKSIZE(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
+ *
+ * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
+ * multiple block transfers. For single block transfer, this register will
+ * always read as 1. The host driver shall set this register to a value between 1 and
+ * the maximum block count. The SDHC decrements the block count after each block
+ * transfer and stops when the count reaches zero. Setting the block count to 0
+ * results in no data blocks being transferred. This register must be accessed
+ * only when no transaction is executing, that is, after transactions are stopped.
+ * During data transfer, read operations on this register may return an invalid
+ * value and write operations are ignored. When saving transfer content as a result
+ * of a suspend command, the number of blocks yet to be transferred can be
+ * determined by reading this register. The reading of this register must be applied
+ * after transfer is paused by stop at block gap operation and before sending the
+ * command marked as suspend. This is because when suspend command is sent out,
+ * SDHC will regard the current transfer as aborted and change BLKCNT back to its
+ * original value instead of keeping the dynamical indicator of remained block
+ * count. When restoring transfer content prior to issuing a resume command, the
+ * host driver shall restore the previously saved block count. Although the BLKCNT
+ * field is 0 after reset, the read of reset value is 0x1. This is because when
+ * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
+ * BLKCNT is always 1.
+ *
+ * Values:
+ * - 0b0000000000000000 - Stop count.
+ * - 0b0000000000000001 - 1 block
+ * - 0b0000000000000010 - 2 blocks
+ * - 0b1111111111111111 - 65535 blocks
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_BLKATTR_BLKCNT field. */
+#define SDHC_RD_BLKATTR_BLKCNT(base) ((SDHC_BLKATTR_REG(base) & SDHC_BLKATTR_BLKCNT_MASK) >> SDHC_BLKATTR_BLKCNT_SHIFT)
+#define SDHC_BRD_BLKATTR_BLKCNT(base) (SDHC_RD_BLKATTR_BLKCNT(base))
+
+/*! @brief Set the BLKCNT field to a new value. */
+#define SDHC_WR_BLKATTR_BLKCNT(base, value) (SDHC_RMW_BLKATTR(base, SDHC_BLKATTR_BLKCNT_MASK, SDHC_BLKATTR_BLKCNT(value)))
+#define SDHC_BWR_BLKATTR_BLKCNT(base, value) (SDHC_WR_BLKATTR_BLKCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_CMDARG - Command Argument register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_CMDARG - Command Argument register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the SD/MMC command argument.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_CMDARG register
+ */
+/*@{*/
+#define SDHC_RD_CMDARG(base)     (SDHC_CMDARG_REG(base))
+#define SDHC_WR_CMDARG(base, value) (SDHC_CMDARG_REG(base) = (value))
+#define SDHC_RMW_CMDARG(base, mask, value) (SDHC_WR_CMDARG(base, (SDHC_RD_CMDARG(base) & ~(mask)) | (value)))
+#define SDHC_SET_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) |  (value)))
+#define SDHC_CLR_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) & ~(value)))
+#define SDHC_TOG_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_XFERTYP - Transfer Type register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_XFERTYP - Transfer Type register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to control the operation of data transfers. The host
+ * driver shall set this register before issuing a command followed by a data
+ * transfer, or before issuing a resume command. To prevent data loss, the SDHC
+ * prevents writing to the bits that are involved in the data transfer of this
+ * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
+ * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
+ * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
+ * send a command with data by writing to this register is ignored; when
+ * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
+ * data transfer involved, it is mandatory that the block size is nonzero.
+ * Besides, block count must also be nonzero, or indicated as single block transfer
+ * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
+ * this register is 0 when written), otherwise SDHC will ignore the sending of
+ * this command and do nothing. For write command, with all above restrictions, it
+ * is also mandatory that the write protect switch is not active (WPSPL bit of
+ * Present State Register is 1), otherwise SDHC will also ignore the command. If
+ * the commands with data transfer does not receive the response in 64 clock
+ * cycles, that is, response time-out, SDHC will regard the external device does not
+ * accept the command and abort the data transfer. In this scenario, the driver
+ * must issue the command again to retry the transfer. It is also possible that,
+ * for some reason, the card responds to the command but SDHC does not receive the
+ * response, and if it is internal DMA (either simple DMA or ADMA) read
+ * operation, the external system memory is over-written by the internal DMA with data
+ * sent back from the card. The following table shows the summary of how register
+ * settings determine the type of data transfer. Transfer Type register setting for
+ * various transfer types Multi/Single block select Block count enable Block
+ * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
+ * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
+ * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
+ * in regards to XFERTYP[RSPTYP] as well as the name of the response type.
+ * Relationship between parameters and the name of the response type Response type
+ * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
+ * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
+ * the SDIO specification, response type notation for R5b is not defined. R5
+ * includes R5b in the SDIO specification. But R5b is defined in this specification
+ * to specify that the SDHC will check the busy status after receiving a
+ * response. For example, usually CMD52 is used with R5, but the I/O abort command shall
+ * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
+ * The CRC check shall be disabled for these response types.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_XFERTYP register
+ */
+/*@{*/
+#define SDHC_RD_XFERTYP(base)    (SDHC_XFERTYP_REG(base))
+#define SDHC_WR_XFERTYP(base, value) (SDHC_XFERTYP_REG(base) = (value))
+#define SDHC_RMW_XFERTYP(base, mask, value) (SDHC_WR_XFERTYP(base, (SDHC_RD_XFERTYP(base) & ~(mask)) | (value)))
+#define SDHC_SET_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) |  (value)))
+#define SDHC_CLR_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) & ~(value)))
+#define SDHC_TOG_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_XFERTYP bitfields
+ */
+
+/*!
+ * @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
+ *
+ * Enables DMA functionality. If this bit is set to 1, a DMA operation shall
+ * begin when the host driver sets the DPSEL bit of this register. Whether the
+ * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DMAEN field. */
+#define SDHC_RD_XFERTYP_DMAEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DMAEN_MASK) >> SDHC_XFERTYP_DMAEN_SHIFT)
+#define SDHC_BRD_XFERTYP_DMAEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define SDHC_WR_XFERTYP_DMAEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DMAEN_MASK, SDHC_XFERTYP_DMAEN(value)))
+#define SDHC_BWR_XFERTYP_DMAEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field BCEN[1] (RW)
+ *
+ * Used to enable the Block Count register, which is only relevant for multiple
+ * block transfers. When this bit is 0, the internal counter for block is
+ * disabled, which is useful in executing an infinite transfer.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_BCEN field. */
+#define SDHC_RD_XFERTYP_BCEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_BCEN_MASK) >> SDHC_XFERTYP_BCEN_SHIFT)
+#define SDHC_BRD_XFERTYP_BCEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_BCEN_SHIFT))
+
+/*! @brief Set the BCEN field to a new value. */
+#define SDHC_WR_XFERTYP_BCEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_BCEN_MASK, SDHC_XFERTYP_BCEN(value)))
+#define SDHC_BWR_XFERTYP_BCEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_BCEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
+ *
+ * Multiple block transfers for memory require a CMD12 to stop the transaction.
+ * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
+ * last block transfer has completed. The host driver shall not set this bit to
+ * issue commands that do not require CMD12 to stop a multiple block data
+ * transfer. In particular, secure commands defined in File Security Specification (see
+ * reference list) do not require CMD12. In single block transfer, the SDHC will
+ * ignore this bit whether it is set or not.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_AC12EN field. */
+#define SDHC_RD_XFERTYP_AC12EN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_AC12EN_MASK) >> SDHC_XFERTYP_AC12EN_SHIFT)
+#define SDHC_BRD_XFERTYP_AC12EN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_AC12EN_SHIFT))
+
+/*! @brief Set the AC12EN field to a new value. */
+#define SDHC_WR_XFERTYP_AC12EN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_AC12EN_MASK, SDHC_XFERTYP_AC12EN(value)))
+#define SDHC_BWR_XFERTYP_AC12EN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_AC12EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
+ *
+ * Defines the direction of DAT line data transfers. The bit is set to 1 by the
+ * host driver to transfer data from the SD card to the SDHC and is set to 0 for
+ * all other commands.
+ *
+ * Values:
+ * - 0b0 - Write host to card.
+ * - 0b1 - Read card to host.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DTDSEL field. */
+#define SDHC_RD_XFERTYP_DTDSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DTDSEL_MASK) >> SDHC_XFERTYP_DTDSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_DTDSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DTDSEL_SHIFT))
+
+/*! @brief Set the DTDSEL field to a new value. */
+#define SDHC_WR_XFERTYP_DTDSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DTDSEL_MASK, SDHC_XFERTYP_DTDSEL(value)))
+#define SDHC_BWR_XFERTYP_DTDSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DTDSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
+ *
+ * Enables multiple block DAT line data transfers. For any other commands, this
+ * bit shall be set to 0. If this bit is 0, it is not necessary to set the block
+ * count register.
+ *
+ * Values:
+ * - 0b0 - Single block.
+ * - 0b1 - Multiple blocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_MSBSEL field. */
+#define SDHC_RD_XFERTYP_MSBSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_MSBSEL_MASK) >> SDHC_XFERTYP_MSBSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_MSBSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_MSBSEL_SHIFT))
+
+/*! @brief Set the MSBSEL field to a new value. */
+#define SDHC_WR_XFERTYP_MSBSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_MSBSEL_MASK, SDHC_XFERTYP_MSBSEL(value)))
+#define SDHC_BWR_XFERTYP_MSBSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_MSBSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
+ *
+ * Values:
+ * - 0b00 - No response.
+ * - 0b01 - Response length 136.
+ * - 0b10 - Response length 48.
+ * - 0b11 - Response length 48, check busy after response.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_RSPTYP field. */
+#define SDHC_RD_XFERTYP_RSPTYP(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_RSPTYP_MASK) >> SDHC_XFERTYP_RSPTYP_SHIFT)
+#define SDHC_BRD_XFERTYP_RSPTYP(base) (SDHC_RD_XFERTYP_RSPTYP(base))
+
+/*! @brief Set the RSPTYP field to a new value. */
+#define SDHC_WR_XFERTYP_RSPTYP(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_RSPTYP_MASK, SDHC_XFERTYP_RSPTYP(value)))
+#define SDHC_BWR_XFERTYP_RSPTYP(base, value) (SDHC_WR_XFERTYP_RSPTYP(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
+ *
+ * If this bit is set to 1, the SDHC shall check the CRC field in the response.
+ * If an error is detected, it is reported as a Command CRC Error. If this bit is
+ * set to 0, the CRC field is not checked. The number of bits checked by the CRC
+ * field value changes according to the length of the response.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CCCEN field. */
+#define SDHC_RD_XFERTYP_CCCEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CCCEN_MASK) >> SDHC_XFERTYP_CCCEN_SHIFT)
+#define SDHC_BRD_XFERTYP_CCCEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CCCEN_SHIFT))
+
+/*! @brief Set the CCCEN field to a new value. */
+#define SDHC_WR_XFERTYP_CCCEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CCCEN_MASK, SDHC_XFERTYP_CCCEN(value)))
+#define SDHC_BWR_XFERTYP_CCCEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CCCEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CICEN[20] (RW)
+ *
+ * If this bit is set to 1, the SDHC will check the index field in the response
+ * to see if it has the same value as the command index. If it is not, it is
+ * reported as a command index error. If this bit is set to 0, the index field is not
+ * checked.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CICEN field. */
+#define SDHC_RD_XFERTYP_CICEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CICEN_MASK) >> SDHC_XFERTYP_CICEN_SHIFT)
+#define SDHC_BRD_XFERTYP_CICEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CICEN_SHIFT))
+
+/*! @brief Set the CICEN field to a new value. */
+#define SDHC_WR_XFERTYP_CICEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CICEN_MASK, SDHC_XFERTYP_CICEN(value)))
+#define SDHC_BWR_XFERTYP_CICEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CICEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
+ *
+ * This bit is set to 1 to indicate that data is present and shall be
+ * transferred using the DAT line. It is set to 0 for the following: Commands using only
+ * the CMD line, for example: CMD52. Commands with no data transfer, but using the
+ * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
+ * this bit shall be set, and other bits in this register shall be set the same
+ * as when the transfer was initially launched. When the Write Protect switch is
+ * on, that is, the WPSPL bit is active as 0, any command with a write operation
+ * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
+ * 0, writes to the register Transfer Type are ignored.
+ *
+ * Values:
+ * - 0b0 - No data present.
+ * - 0b1 - Data present.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DPSEL field. */
+#define SDHC_RD_XFERTYP_DPSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DPSEL_MASK) >> SDHC_XFERTYP_DPSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_DPSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DPSEL_SHIFT))
+
+/*! @brief Set the DPSEL field to a new value. */
+#define SDHC_WR_XFERTYP_DPSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DPSEL_MASK, SDHC_XFERTYP_DPSEL(value)))
+#define SDHC_BWR_XFERTYP_DPSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DPSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
+ *
+ * There are three types of special commands: suspend, resume, and abort. These
+ * bits shall be set to 00b for all other commands. Suspend command: If the
+ * suspend command succeeds, the SDHC shall assume that the card bus has been released
+ * and that it is possible to issue the next command which uses the DAT line.
+ * Because the SDHC does not monitor the content of command response, it does not
+ * know if the suspend command succeeded or not. It is the host driver's
+ * responsibility to check the status of the suspend command and send another command
+ * marked as suspend to inform the SDHC that a suspend command was successfully
+ * issued. After the end bit of command is sent, the SDHC deasserts read wait for read
+ * transactions and stops checking busy for write transactions. In 4-bit mode,
+ * the interrupt cycle starts. If the suspend command fails, the SDHC will
+ * maintain its current state, and the host driver shall restart the transfer by setting
+ * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
+ * restoring the registers saved before sending the suspend command and then sends
+ * the resume command. The SDHC will check for a pending busy state before
+ * starting write transfers. Abort command: If this command is set when executing a
+ * read transfer, the SDHC will stop reads to the buffer. If this command is set
+ * when executing a write transfer, the SDHC will stop driving the DAT line. After
+ * issuing the abort command, the host driver must issue a software reset (abort
+ * transaction).
+ *
+ * Values:
+ * - 0b00 - Normal other commands.
+ * - 0b01 - Suspend CMD52 for writing bus suspend in CCCR.
+ * - 0b10 - Resume CMD52 for writing function select in CCCR.
+ * - 0b11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CMDTYP field. */
+#define SDHC_RD_XFERTYP_CMDTYP(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CMDTYP_MASK) >> SDHC_XFERTYP_CMDTYP_SHIFT)
+#define SDHC_BRD_XFERTYP_CMDTYP(base) (SDHC_RD_XFERTYP_CMDTYP(base))
+
+/*! @brief Set the CMDTYP field to a new value. */
+#define SDHC_WR_XFERTYP_CMDTYP(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CMDTYP_MASK, SDHC_XFERTYP_CMDTYP(value)))
+#define SDHC_BWR_XFERTYP_CMDTYP(base, value) (SDHC_WR_XFERTYP_CMDTYP(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
+ *
+ * These bits shall be set to the command number that is specified in bits 45-40
+ * of the command-format in the SD Memory Card Physical Layer Specification and
+ * SDIO Card Specification.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CMDINX field. */
+#define SDHC_RD_XFERTYP_CMDINX(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CMDINX_MASK) >> SDHC_XFERTYP_CMDINX_SHIFT)
+#define SDHC_BRD_XFERTYP_CMDINX(base) (SDHC_RD_XFERTYP_CMDINX(base))
+
+/*! @brief Set the CMDINX field to a new value. */
+#define SDHC_WR_XFERTYP_CMDINX(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CMDINX_MASK, SDHC_XFERTYP_CMDINX(value)))
+#define SDHC_BWR_XFERTYP_CMDINX(base, value) (SDHC_WR_XFERTYP_CMDINX(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_CMDRSP - Command Response 0
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_CMDRSP - Command Response 0 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 0 of the response bits from the card.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP register
+ */
+/*@{*/
+#define SDHC_RD_CMDRSP(base, index) (SDHC_CMDRSP_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_DATPORT - Buffer Data Port register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_DATPORT - Buffer Data Port register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This is a 32-bit data port register used to access the internal buffer and it
+ * cannot be updated in Idle mode.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_DATPORT register
+ */
+/*@{*/
+#define SDHC_RD_DATPORT(base)    (SDHC_DATPORT_REG(base))
+#define SDHC_WR_DATPORT(base, value) (SDHC_DATPORT_REG(base) = (value))
+#define SDHC_RMW_DATPORT(base, mask, value) (SDHC_WR_DATPORT(base, (SDHC_RD_DATPORT(base) & ~(mask)) | (value)))
+#define SDHC_SET_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) |  (value)))
+#define SDHC_CLR_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) & ~(value)))
+#define SDHC_TOG_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_PRSSTAT - Present State register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_PRSSTAT - Present State register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The host driver can get status of the SDHC from this 32-bit read-only
+ * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
+ * SDIO) when the DAT lines are busy during a data transfer. These commands can be
+ * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
+ * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
+ * Physical Specification may add other commands to this list in the future.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_PRSSTAT register
+ */
+/*@{*/
+#define SDHC_RD_PRSSTAT(base)    (SDHC_PRSSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_PRSSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
+ *
+ * If this status bit is 0, it indicates that the CMD line is not in use and the
+ * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
+ * immediately after the Transfer Type register is written. This bit is cleared when
+ * the command response is received. Even if the CDIHB bit is set to 1, Commands
+ * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
+ * generates a command complete interrupt in the interrupt status register. If the
+ * SDHC cannot issue the command because of a command conflict error (see
+ * command CRC error) or because of a command not issued by auto CMD12 error, this bit
+ * will remain 1 and the command complete is not set. The status of issuing an
+ * auto CMD12 does not show on this bit.
+ *
+ * Values:
+ * - 0b0 - Can issue command using only CMD line.
+ * - 0b1 - Cannot issue command.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CIHB field. */
+#define SDHC_RD_PRSSTAT_CIHB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CIHB_MASK) >> SDHC_PRSSTAT_CIHB_SHIFT)
+#define SDHC_BRD_PRSSTAT_CIHB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CIHB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
+ *
+ * This status bit is generated if either the DLA or the RTA is set to 1. If
+ * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
+ * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
+ * the case when the command busy is finished, changing from 1 to 0 generates a
+ * transfer complete interrupt in the Interrupt Status register. The SD host
+ * driver can save registers for a suspend transaction after this bit has changed
+ * from 1 to 0.
+ *
+ * Values:
+ * - 0b0 - Can issue command which uses the DAT line.
+ * - 0b1 - Cannot issue command which uses the DAT line.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CDIHB field. */
+#define SDHC_RD_PRSSTAT_CDIHB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CDIHB_MASK) >> SDHC_PRSSTAT_CDIHB_SHIFT)
+#define SDHC_BRD_PRSSTAT_CDIHB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CDIHB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLA[2] (RO)
+ *
+ * Indicates whether one of the DAT lines on the SD bus is in use. In the case
+ * of read transactions: This status indicates whether a read transfer is
+ * executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
+ * generates a block gap event interrupt in the Interrupt Status register. This bit
+ * will be set in either of the following cases: After the end bit of the read
+ * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
+ * will be cleared in either of the following cases: When the end bit of the last
+ * data block is sent from the SD bus to the SDHC. When the read wait state is
+ * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
+ * the next block gap by driving read wait at the start of the interrupt cycle.
+ * If the read wait signal is already driven (data buffer cannot receive data),
+ * the SDHC can wait for a current block gap by continuing to drive the read wait
+ * signal. It is necessary to support read wait to use the suspend / resume
+ * function. This bit will remain 1 during read wait. In the case of write
+ * transactions: This status indicates that a write transfer is executing on the SD bus.
+ * Changes in this value from 1 to 0 generate a transfer complete interrupt in the
+ * interrupt status register. This bit will be set in either of the following
+ * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
+ * continue a write transfer. This bit will be cleared in either of the
+ * following cases: When the SD card releases write busy of the last data block, the SDHC
+ * will also detect if the output is not busy. If the SD card does not drive the
+ * busy signal after the CRC status is received, the SDHC shall assume the card
+ * drive "Not busy". When the SD card releases write busy, prior to waiting for
+ * write transfer, and as a result of a stop at block gap request. In the case of
+ * command with busy pending: This status indicates that a busy state follows the
+ * command and the data line is in use. This bit will be cleared when the DAT0
+ * line is released.
+ *
+ * Values:
+ * - 0b0 - DAT line inactive.
+ * - 0b1 - DAT line active.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_DLA field. */
+#define SDHC_RD_PRSSTAT_DLA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_DLA_MASK) >> SDHC_PRSSTAT_DLA_SHIFT)
+#define SDHC_BRD_PRSSTAT_DLA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_DLA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
+ *
+ * Indicates that the internal card clock is stable. This bit is for the host
+ * driver to poll clock status when changing the clock frequency. It is recommended
+ * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
+ * frequency is changing.
+ *
+ * Values:
+ * - 0b0 - Clock is changing frequency and not stable.
+ * - 0b1 - Clock is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_SDSTB field. */
+#define SDHC_RD_PRSSTAT_SDSTB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_SDSTB_MASK) >> SDHC_PRSSTAT_SDSTB_SHIFT)
+#define SDHC_BRD_PRSSTAT_SDSTB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_SDSTB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
+ *
+ * Indicates that the bus clock is internally gated off. This bit is for the
+ * host driver to debug.
+ *
+ * Values:
+ * - 0b0 - Bus clock is active.
+ * - 0b1 - Bus clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field. */
+#define SDHC_RD_PRSSTAT_IPGOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_IPGOFF_MASK) >> SDHC_PRSSTAT_IPGOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_IPGOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_IPGOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
+ *
+ * Indicates that the system clock is internally gated off. This bit is for the
+ * host driver to debug during a data transfer.
+ *
+ * Values:
+ * - 0b0 - System clock is active.
+ * - 0b1 - System clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field. */
+#define SDHC_RD_PRSSTAT_HCKOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_HCKOFF_MASK) >> SDHC_PRSSTAT_HCKOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_HCKOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_HCKOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
+ *
+ * Indicates that the is internally gated off. This bit is for the host driver
+ * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
+ * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
+ * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
+ * clock SDHC clock bus clock
+ *
+ * Values:
+ * - 0b0 - SDHC clock is active.
+ * - 0b1 - SDHC clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_PEROFF field. */
+#define SDHC_RD_PRSSTAT_PEROFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_PEROFF_MASK) >> SDHC_PRSSTAT_PEROFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_PEROFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_PEROFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
+ *
+ * Indicates that the SD clock is internally gated off, because of buffer
+ * over/under-run or read pause without read wait assertion, or the driver has cleared
+ * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
+ * data transaction on the SD bus.
+ *
+ * Values:
+ * - 0b0 - SD clock is active.
+ * - 0b1 - SD clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_SDOFF field. */
+#define SDHC_RD_PRSSTAT_SDOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_SDOFF_MASK) >> SDHC_PRSSTAT_SDOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_SDOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_SDOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field WTA[8] (RO)
+ *
+ * Indicates that a write transfer is active. If this bit is 0, it means no
+ * valid write data exists in the SDHC. This bit is set in either of the following
+ * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
+ * restart a write transfer. This bit is cleared in either of the following
+ * cases: After getting the CRC status of the last data block as specified by the
+ * transfer count (single and multiple). After getting the CRC status of any block
+ * where data transmission is about to be stopped by a stop at block gap request.
+ * During a write transaction, a block gap event interrupt is generated when this
+ * bit is changed to 0, as result of the stop at block gap request being set.
+ * This status is useful for the host driver in determining when to issue commands
+ * during write busy state.
+ *
+ * Values:
+ * - 0b0 - No valid data.
+ * - 0b1 - Transferring data.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_WTA field. */
+#define SDHC_RD_PRSSTAT_WTA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_WTA_MASK) >> SDHC_PRSSTAT_WTA_SHIFT)
+#define SDHC_BRD_PRSSTAT_WTA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_WTA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field RTA[9] (RO)
+ *
+ * Used for detecting completion of a read transfer. This bit is set for either
+ * of the following conditions: After the end bit of the read command. When
+ * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
+ * interrupt is generated when this bit changes to 0. This bit is cleared for either of
+ * the following conditions: When the last data block as specified by block
+ * length is transferred to the system, that is, all data are read away from SDHC
+ * internal buffer. When all valid data blocks have been transferred from SDHC
+ * internal buffer to the system and no current block transfers are being sent as a
+ * result of the stop at block gap request being set to 1.
+ *
+ * Values:
+ * - 0b0 - No valid data.
+ * - 0b1 - Transferring data.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_RTA field. */
+#define SDHC_RD_PRSSTAT_RTA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_RTA_MASK) >> SDHC_PRSSTAT_RTA_SHIFT)
+#define SDHC_BRD_PRSSTAT_RTA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_RTA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
+ *
+ * Used for non-DMA write transfers. The SDHC can implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates whether space is
+ * available for write data. If this bit is 1, valid data greater than the watermark
+ * level can be written to the buffer. This read-only flag indicates whether
+ * space is available for write data.
+ *
+ * Values:
+ * - 0b0 - Write disable, the buffer can hold valid data less than the write
+ *     watermark level.
+ * - 0b1 - Write enable, the buffer can hold valid data greater than the write
+ *     watermark level.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_BWEN field. */
+#define SDHC_RD_PRSSTAT_BWEN(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_BWEN_MASK) >> SDHC_PRSSTAT_BWEN_SHIFT)
+#define SDHC_BRD_PRSSTAT_BWEN(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_BWEN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BREN[11] (RO)
+ *
+ * Used for non-DMA read transfers. The SDHC may implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates that valid data exists
+ * in the host side buffer. If this bit is high, valid data greater than the
+ * watermark level exist in the buffer. This read-only flag indicates that valid
+ * data exists in the host side buffer.
+ *
+ * Values:
+ * - 0b0 - Read disable, valid data less than the watermark level exist in the
+ *     buffer.
+ * - 0b1 - Read enable, valid data greater than the watermark level exist in the
+ *     buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_BREN field. */
+#define SDHC_RD_PRSSTAT_BREN(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_BREN_MASK) >> SDHC_PRSSTAT_BREN_SHIFT)
+#define SDHC_BRD_PRSSTAT_BREN(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_BREN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CINS[16] (RO)
+ *
+ * Indicates whether a card has been inserted. The SDHC debounces this signal so
+ * that the host driver will not need to wait for it to stabilize. Changing from
+ * a 0 to 1 generates a card insertion interrupt in the Interrupt Status
+ * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
+ * Status register. A write to the force event register does not effect this bit.
+ * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
+ * bit.
+ *
+ * Values:
+ * - 0b0 - Power on reset or no card.
+ * - 0b1 - Card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CINS field. */
+#define SDHC_RD_PRSSTAT_CINS(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CINS_MASK) >> SDHC_PRSSTAT_CINS_SHIFT)
+#define SDHC_BRD_PRSSTAT_CINS(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CINS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
+ *
+ * Used to check the CMD line level to recover from errors, and for debugging.
+ * The reset value is effected by the external pullup/pulldown resistor, by
+ * default, the read value of this bit after reset is 1b, when the command line is
+ * pulled up.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CLSL field. */
+#define SDHC_RD_PRSSTAT_CLSL(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CLSL_MASK) >> SDHC_PRSSTAT_CLSL_SHIFT)
+#define SDHC_BRD_PRSSTAT_CLSL(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CLSL_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
+ *
+ * Used to check the DAT line level to recover from errors, and for debugging.
+ * This is especially useful in detecting the busy signal level from DAT[0]. The
+ * reset value is effected by the external pullup/pulldown resistors. By default,
+ * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
+ * down and the other lines are pulled up.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_DLSL field. */
+#define SDHC_RD_PRSSTAT_DLSL(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_DLSL_MASK) >> SDHC_PRSSTAT_DLSL_SHIFT)
+#define SDHC_BRD_PRSSTAT_DLSL(base) (SDHC_RD_PRSSTAT_DLSL(base))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_PROCTL - Protocol Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_PROCTL - Protocol Control register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * There are three cases to restart the transfer after stop at the block gap.
+ * Which case is appropriate depends on whether the SDHC issues a suspend command
+ * or the SD card accepts the suspend command: If the host driver does not issue a
+ * suspend command, the continue request shall be used to restart the transfer.
+ * If the host driver issues a suspend command and the SD card accepts it, a
+ * resume command shall be used to restart the transfer. If the host driver issues a
+ * suspend command and the SD card does not accept it, the continue request shall
+ * be used to restart the transfer. Any time stop at block gap request stops the
+ * data transfer, the host driver shall wait for a transfer complete (in the
+ * interrupt status register), before attempting to restart the transfer. When
+ * restarting the data transfer by continue request, the host driver shall clear the
+ * stop at block gap request before or simultaneously.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_PROCTL register
+ */
+/*@{*/
+#define SDHC_RD_PROCTL(base)     (SDHC_PROCTL_REG(base))
+#define SDHC_WR_PROCTL(base, value) (SDHC_PROCTL_REG(base) = (value))
+#define SDHC_RMW_PROCTL(base, mask, value) (SDHC_WR_PROCTL(base, (SDHC_RD_PROCTL(base) & ~(mask)) | (value)))
+#define SDHC_SET_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) |  (value)))
+#define SDHC_CLR_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) & ~(value)))
+#define SDHC_TOG_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_PROCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_PROCTL, field LCTL[0] (RW)
+ *
+ * This bit, fully controlled by the host driver, is used to caution the user
+ * not to remove the card while the card is being accessed. If the software is
+ * going to issue multiple SD commands, this bit can be set during all these
+ * transactions. It is not necessary to change for each transaction. When the software
+ * issues multiple SD commands, setting the bit once before the first command is
+ * sufficient: it is not necessary to reset the bit between commands.
+ *
+ * Values:
+ * - 0b0 - LED off.
+ * - 0b1 - LED on.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_LCTL field. */
+#define SDHC_RD_PROCTL_LCTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_LCTL_MASK) >> SDHC_PROCTL_LCTL_SHIFT)
+#define SDHC_BRD_PROCTL_LCTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_LCTL_SHIFT))
+
+/*! @brief Set the LCTL field to a new value. */
+#define SDHC_WR_PROCTL_LCTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_LCTL_MASK, SDHC_PROCTL_LCTL(value)))
+#define SDHC_BWR_PROCTL_LCTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_LCTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field DTW[2:1] (RW)
+ *
+ * Selects the data width of the SD bus for a data transfer. The host driver
+ * shall set it to match the data width of the card. Possible data transfer width is
+ * 1-bit, 4-bits or 8-bits.
+ *
+ * Values:
+ * - 0b00 - 1-bit mode
+ * - 0b01 - 4-bit mode
+ * - 0b10 - 8-bit mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_DTW field. */
+#define SDHC_RD_PROCTL_DTW(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_DTW_MASK) >> SDHC_PROCTL_DTW_SHIFT)
+#define SDHC_BRD_PROCTL_DTW(base) (SDHC_RD_PROCTL_DTW(base))
+
+/*! @brief Set the DTW field to a new value. */
+#define SDHC_WR_PROCTL_DTW(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_DTW_MASK, SDHC_PROCTL_DTW(value)))
+#define SDHC_BWR_PROCTL_DTW(base, value) (SDHC_WR_PROCTL_DTW(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field D3CD[3] (RW)
+ *
+ * If this bit is set, DAT3 should be pulled down to act as a card detection
+ * pin. Be cautious when using this feature, because DAT3 is also a chip-select for
+ * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
+ * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
+ * is used.
+ *
+ * Values:
+ * - 0b0 - DAT3 does not monitor card Insertion.
+ * - 0b1 - DAT3 as card detection pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_D3CD field. */
+#define SDHC_RD_PROCTL_D3CD(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_D3CD_MASK) >> SDHC_PROCTL_D3CD_SHIFT)
+#define SDHC_BRD_PROCTL_D3CD(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_D3CD_SHIFT))
+
+/*! @brief Set the D3CD field to a new value. */
+#define SDHC_WR_PROCTL_D3CD(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_D3CD_MASK, SDHC_PROCTL_D3CD(value)))
+#define SDHC_BWR_PROCTL_D3CD(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_D3CD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
+ *
+ * The SDHC supports all four endian modes in data transfer.
+ *
+ * Values:
+ * - 0b00 - Big endian mode
+ * - 0b01 - Half word big endian mode
+ * - 0b10 - Little endian mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_EMODE field. */
+#define SDHC_RD_PROCTL_EMODE(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_EMODE_MASK) >> SDHC_PROCTL_EMODE_SHIFT)
+#define SDHC_BRD_PROCTL_EMODE(base) (SDHC_RD_PROCTL_EMODE(base))
+
+/*! @brief Set the EMODE field to a new value. */
+#define SDHC_WR_PROCTL_EMODE(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_EMODE_MASK, SDHC_PROCTL_EMODE(value)))
+#define SDHC_BWR_PROCTL_EMODE(base, value) (SDHC_WR_PROCTL_EMODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CDTL[6] (RW)
+ *
+ * Enabled while the CDSS is set to 1 and it indicates card insertion.
+ *
+ * Values:
+ * - 0b0 - Card detect test level is 0, no card inserted.
+ * - 0b1 - Card detect test level is 1, card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CDTL field. */
+#define SDHC_RD_PROCTL_CDTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CDTL_MASK) >> SDHC_PROCTL_CDTL_SHIFT)
+#define SDHC_BRD_PROCTL_CDTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDTL_SHIFT))
+
+/*! @brief Set the CDTL field to a new value. */
+#define SDHC_WR_PROCTL_CDTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CDTL_MASK, SDHC_PROCTL_CDTL(value)))
+#define SDHC_BWR_PROCTL_CDTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CDSS[7] (RW)
+ *
+ * Selects the source for the card detection.
+ *
+ * Values:
+ * - 0b0 - Card detection level is selected for normal purpose.
+ * - 0b1 - Card detection test level is selected for test purpose.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CDSS field. */
+#define SDHC_RD_PROCTL_CDSS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CDSS_MASK) >> SDHC_PROCTL_CDSS_SHIFT)
+#define SDHC_BRD_PROCTL_CDSS(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDSS_SHIFT))
+
+/*! @brief Set the CDSS field to a new value. */
+#define SDHC_WR_PROCTL_CDSS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CDSS_MASK, SDHC_PROCTL_CDSS(value)))
+#define SDHC_BWR_PROCTL_CDSS(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDSS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
+ *
+ * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
+ * operation.
+ *
+ * Values:
+ * - 0b00 - No DMA or simple DMA is selected.
+ * - 0b01 - ADMA1 is selected.
+ * - 0b10 - ADMA2 is selected.
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_DMAS field. */
+#define SDHC_RD_PROCTL_DMAS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT)
+#define SDHC_BRD_PROCTL_DMAS(base) (SDHC_RD_PROCTL_DMAS(base))
+
+/*! @brief Set the DMAS field to a new value. */
+#define SDHC_WR_PROCTL_DMAS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_DMAS_MASK, SDHC_PROCTL_DMAS(value)))
+#define SDHC_BWR_PROCTL_DMAS(base, value) (SDHC_WR_PROCTL_DMAS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
+ *
+ * Used to stop executing a transaction at the next block gap for both DMA and
+ * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
+ * transfer completion, the host driver shall leave this bit set to 1. Clearing both
+ * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
+ * Wait is used to stop the read transaction at the block gap. The SDHC will
+ * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
+ * that SDIO card support read wait. Therefore, the host driver shall not set
+ * this bit during read transfers unless the SDIO card supports read wait and has
+ * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
+ * the read operation during block gap. In the case of write transfers in which
+ * the host driver writes data to the data port register, the host driver shall set
+ * this bit after all block data is written. If this bit is set to 1, the host
+ * driver shall not write data to the Data Port register after a block is sent.
+ * Once this bit is set, the host driver shall not clear this bit before
+ * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
+ * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
+ *
+ * Values:
+ * - 0b0 - Transfer
+ * - 0b1 - Stop
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_SABGREQ field. */
+#define SDHC_RD_PROCTL_SABGREQ(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_SABGREQ_MASK) >> SDHC_PROCTL_SABGREQ_SHIFT)
+#define SDHC_BRD_PROCTL_SABGREQ(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_SABGREQ_SHIFT))
+
+/*! @brief Set the SABGREQ field to a new value. */
+#define SDHC_WR_PROCTL_SABGREQ(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_SABGREQ_MASK, SDHC_PROCTL_SABGREQ(value)))
+#define SDHC_BWR_PROCTL_SABGREQ(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_SABGREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CREQ[17] (RW)
+ *
+ * Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
+ * When a suspend operation is not accepted by the card, it is also by setting this
+ * bit to restart the paused transfer. To cancel stop at the block gap, set
+ * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
+ * automatically clears this bit, therefore it is not necessary for the host driver to
+ * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
+ * request is ignored.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Restart
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CREQ field. */
+#define SDHC_RD_PROCTL_CREQ(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CREQ_MASK) >> SDHC_PROCTL_CREQ_SHIFT)
+#define SDHC_BRD_PROCTL_CREQ(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CREQ_SHIFT))
+
+/*! @brief Set the CREQ field to a new value. */
+#define SDHC_WR_PROCTL_CREQ(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CREQ_MASK, SDHC_PROCTL_CREQ(value)))
+#define SDHC_BWR_PROCTL_CREQ(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field RWCTL[18] (RW)
+ *
+ * The read wait function is optional for SDIO cards. If the card supports read
+ * wait, set this bit to enable use of the read wait protocol to stop read data
+ * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
+ * read data, which restricts commands generation. When the host driver detects an
+ * SDIO card insertion, it shall set this bit according to the CCCR of the card.
+ * If the card does not support read wait, this bit shall never be set to 1,
+ * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
+ * during read operation is also supported, but the SDHC will stop the SD Clock
+ * to pause reading operation.
+ *
+ * Values:
+ * - 0b0 - Disable read wait control, and stop SD clock at block gap when
+ *     SABGREQ is set.
+ * - 0b1 - Enable read wait control, and assert read wait without stopping SD
+ *     clock at block gap when SABGREQ bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_RWCTL field. */
+#define SDHC_RD_PROCTL_RWCTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_RWCTL_MASK) >> SDHC_PROCTL_RWCTL_SHIFT)
+#define SDHC_BRD_PROCTL_RWCTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_RWCTL_SHIFT))
+
+/*! @brief Set the RWCTL field to a new value. */
+#define SDHC_WR_PROCTL_RWCTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_RWCTL_MASK, SDHC_PROCTL_RWCTL(value)))
+#define SDHC_BWR_PROCTL_RWCTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_RWCTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field IABG[19] (RW)
+ *
+ * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
+ * interrupt cycle. Setting to 1 enables interrupt detection at the block gap
+ * for a multiple block transfer. Setting to 0 disables interrupt detection during
+ * a multiple block transfer. If the SDIO card can't signal an interrupt during a
+ * multiple block transfer, this bit must be set to 0 to avoid an inadvertent
+ * interrupt. When the host driver detects an SDIO card insertion, it shall set
+ * this bit according to the CCCR of the card.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_IABG field. */
+#define SDHC_RD_PROCTL_IABG(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_IABG_MASK) >> SDHC_PROCTL_IABG_SHIFT)
+#define SDHC_BRD_PROCTL_IABG(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_IABG_SHIFT))
+
+/*! @brief Set the IABG field to a new value. */
+#define SDHC_WR_PROCTL_IABG(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_IABG_MASK, SDHC_PROCTL_IABG(value)))
+#define SDHC_BWR_PROCTL_IABG(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_IABG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINT[24] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
+ * (Wake Up Support) in CIS is set to 1. When this bit is set, the card
+ * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
+ * the wakeup feature is not enabled, the SD_CLK must be active to assert the
+ * card interrupt status and the SDHC interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECINT field. */
+#define SDHC_RD_PROCTL_WECINT(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECINT_MASK) >> SDHC_PROCTL_WECINT_SHIFT)
+#define SDHC_BRD_PROCTL_WECINT(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINT_SHIFT))
+
+/*! @brief Set the WECINT field to a new value. */
+#define SDHC_WR_PROCTL_WECINT(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECINT_MASK, SDHC_PROCTL_WECINT(value)))
+#define SDHC_BWR_PROCTL_WECINT(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINS[25] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
+ * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
+ * interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECINS field. */
+#define SDHC_RD_PROCTL_WECINS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECINS_MASK) >> SDHC_PROCTL_WECINS_SHIFT)
+#define SDHC_BRD_PROCTL_WECINS(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINS_SHIFT))
+
+/*! @brief Set the WECINS field to a new value. */
+#define SDHC_WR_PROCTL_WECINS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECINS_MASK, SDHC_PROCTL_WECINS(value)))
+#define SDHC_BWR_PROCTL_WECINS(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECRM[26] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
+ * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECRM field. */
+#define SDHC_RD_PROCTL_WECRM(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECRM_MASK) >> SDHC_PROCTL_WECRM_SHIFT)
+#define SDHC_BRD_PROCTL_WECRM(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECRM_SHIFT))
+
+/*! @brief Set the WECRM field to a new value. */
+#define SDHC_WR_PROCTL_WECRM(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECRM_MASK, SDHC_PROCTL_WECRM(value)))
+#define SDHC_BWR_PROCTL_WECRM(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECRM_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_SYSCTL - System Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_SYSCTL - System Control register (RW)
+ *
+ * Reset value: 0x00008008U
+ */
+/*!
+ * @name Constants and macros for entire SDHC_SYSCTL register
+ */
+/*@{*/
+#define SDHC_RD_SYSCTL(base)     (SDHC_SYSCTL_REG(base))
+#define SDHC_WR_SYSCTL(base, value) (SDHC_SYSCTL_REG(base) = (value))
+#define SDHC_RMW_SYSCTL(base, mask, value) (SDHC_WR_SYSCTL(base, (SDHC_RD_SYSCTL(base) & ~(mask)) | (value)))
+#define SDHC_SET_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) |  (value)))
+#define SDHC_CLR_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) & ~(value)))
+#define SDHC_TOG_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_SYSCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
+ *
+ * If this bit is set, bus clock will always be active and no automatic gating
+ * is applied. The bus clock will be internally gated off, if none of the
+ * following factors are met: The cmd part is reset, or Data part is reset, or Soft
+ * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
+ * request is just set, or This bit is set, or Card insertion is detected, or Card
+ * removal is detected, or Card external interrupt is detected, or The SDHC
+ * clock is not gated off The bus clock will not be auto gated off if the SDHC clock
+ * is not gated off. So clearing only this bit has no effect unless the PEREN bit
+ * is also cleared.
+ *
+ * Values:
+ * - 0b0 - Bus clock will be internally gated off.
+ * - 0b1 - Bus clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_IPGEN field. */
+#define SDHC_RD_SYSCTL_IPGEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_IPGEN_MASK) >> SDHC_SYSCTL_IPGEN_SHIFT)
+#define SDHC_BRD_SYSCTL_IPGEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_IPGEN_SHIFT))
+
+/*! @brief Set the IPGEN field to a new value. */
+#define SDHC_WR_SYSCTL_IPGEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_IPGEN_MASK, SDHC_SYSCTL_IPGEN(value)))
+#define SDHC_BWR_SYSCTL_IPGEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_IPGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
+ *
+ * If this bit is set, system clock will always be active and no automatic
+ * gating is applied. When this bit is cleared, system clock will be automatically off
+ * when no data transfer is on the SD bus.
+ *
+ * Values:
+ * - 0b0 - System clock will be internally gated off.
+ * - 0b1 - System clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_HCKEN field. */
+#define SDHC_RD_SYSCTL_HCKEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_HCKEN_MASK) >> SDHC_SYSCTL_HCKEN_SHIFT)
+#define SDHC_BRD_SYSCTL_HCKEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_HCKEN_SHIFT))
+
+/*! @brief Set the HCKEN field to a new value. */
+#define SDHC_WR_SYSCTL_HCKEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_HCKEN_MASK, SDHC_SYSCTL_HCKEN(value)))
+#define SDHC_BWR_SYSCTL_HCKEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_HCKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field PEREN[2] (RW)
+ *
+ * If this bit is set, SDHC clock will always be active and no automatic gating
+ * is applied. Thus the SDCLK is active except for when auto gating-off during
+ * buffer danger (buffer about to over-run or under-run). When this bit is cleared,
+ * the SDHC clock will be automatically off whenever there is no transaction on
+ * the SD bus. Because this bit is only a feature enabling bit, clearing this bit
+ * does not stop SDCLK immediately. The SDHC clock will be internally gated off,
+ * if none of the following factors are met: The cmd part is reset, or Data part
+ * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
+ * just updated, or Continue request is just set, or This bit is set, or Card
+ * insertion is detected, or Card removal is detected, or Card external interrupt is
+ * detected, or 80 clocks for initialization phase is ongoing
+ *
+ * Values:
+ * - 0b0 - SDHC clock will be internally gated off.
+ * - 0b1 - SDHC clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_PEREN field. */
+#define SDHC_RD_SYSCTL_PEREN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_PEREN_MASK) >> SDHC_SYSCTL_PEREN_SHIFT)
+#define SDHC_BRD_SYSCTL_PEREN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_PEREN_SHIFT))
+
+/*! @brief Set the PEREN field to a new value. */
+#define SDHC_WR_SYSCTL_PEREN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_PEREN_MASK, SDHC_SYSCTL_PEREN(value)))
+#define SDHC_BWR_SYSCTL_PEREN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_PEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
+ *
+ * The host controller shall stop SDCLK when writing this bit to 0. SDCLK
+ * frequency can be changed when this bit is 0. Then, the host controller shall
+ * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
+ * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
+ * power.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field. */
+#define SDHC_RD_SYSCTL_SDCLKEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_SDCLKEN_MASK) >> SDHC_SYSCTL_SDCLKEN_SHIFT)
+#define SDHC_BRD_SYSCTL_SDCLKEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_SDCLKEN_SHIFT))
+
+/*! @brief Set the SDCLKEN field to a new value. */
+#define SDHC_WR_SYSCTL_SDCLKEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_SDCLKEN_MASK, SDHC_SYSCTL_SDCLKEN(value)))
+#define SDHC_BWR_SYSCTL_SDCLKEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_SDCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
+ *
+ * Used to provide a more exact divisor to generate the desired SD clock
+ * frequency. Note the divider can even support odd divisor without deterioration of
+ * duty cycle. The setting are as following:
+ *
+ * Values:
+ * - 0b0000 - Divisor by 1.
+ * - 0b0001 - Divisor by 2.
+ * - 0b1110 - Divisor by 15.
+ * - 0b1111 - Divisor by 16.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_DVS field. */
+#define SDHC_RD_SYSCTL_DVS(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_DVS_MASK) >> SDHC_SYSCTL_DVS_SHIFT)
+#define SDHC_BRD_SYSCTL_DVS(base) (SDHC_RD_SYSCTL_DVS(base))
+
+/*! @brief Set the DVS field to a new value. */
+#define SDHC_WR_SYSCTL_DVS(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_DVS_MASK, SDHC_SYSCTL_DVS(value)))
+#define SDHC_BWR_SYSCTL_DVS(base, value) (SDHC_WR_SYSCTL_DVS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
+ *
+ * Used to select the frequency of the SDCLK pin. The frequency is not
+ * programmed directly. Rather this register holds the prescaler (this register) and
+ * divisor (next register) of the base clock frequency register. Setting 00h bypasses
+ * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
+ * behavior of this prescaler is undefined. The two default divider values can
+ * be calculated by the frequency of SDHC clock and the following divisor bits.
+ * The frequency of SDCLK is set by the following formula: Clock frequency = (Base
+ * clock) / (prescaler x divisor) For example, if the base clock frequency is 96
+ * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
+ * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
+ * less than or equal to the target. Similarly, to approach a clock value of 400
+ * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
+ * value of 400 kHz. The reset value of this field is 80h, so if the input base
+ * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
+ * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
+ * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
+ * never exceed this limit. Only the following settings are allowed:
+ *
+ * Values:
+ * - 0b00000001 - Base clock divided by 2.
+ * - 0b00000010 - Base clock divided by 4.
+ * - 0b00000100 - Base clock divided by 8.
+ * - 0b00001000 - Base clock divided by 16.
+ * - 0b00010000 - Base clock divided by 32.
+ * - 0b00100000 - Base clock divided by 64.
+ * - 0b01000000 - Base clock divided by 128.
+ * - 0b10000000 - Base clock divided by 256.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field. */
+#define SDHC_RD_SYSCTL_SDCLKFS(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_SDCLKFS_MASK) >> SDHC_SYSCTL_SDCLKFS_SHIFT)
+#define SDHC_BRD_SYSCTL_SDCLKFS(base) (SDHC_RD_SYSCTL_SDCLKFS(base))
+
+/*! @brief Set the SDCLKFS field to a new value. */
+#define SDHC_WR_SYSCTL_SDCLKFS(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_SDCLKFS_MASK, SDHC_SYSCTL_SDCLKFS(value)))
+#define SDHC_BWR_SYSCTL_SDCLKFS(base, value) (SDHC_WR_SYSCTL_SDCLKFS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
+ *
+ * Determines the interval by which DAT line timeouts are detected. See
+ * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
+ * clock frequency will be generated by dividing the base clock SDCLK value by this
+ * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
+ * time-out events.
+ *
+ * Values:
+ * - 0b0000 - SDCLK x 2 13
+ * - 0b0001 - SDCLK x 2 14
+ * - 0b1110 - SDCLK x 2 27
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_DTOCV field. */
+#define SDHC_RD_SYSCTL_DTOCV(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_DTOCV_MASK) >> SDHC_SYSCTL_DTOCV_SHIFT)
+#define SDHC_BRD_SYSCTL_DTOCV(base) (SDHC_RD_SYSCTL_DTOCV(base))
+
+/*! @brief Set the DTOCV field to a new value. */
+#define SDHC_WR_SYSCTL_DTOCV(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_DTOCV_MASK, SDHC_SYSCTL_DTOCV(value)))
+#define SDHC_BWR_SYSCTL_DTOCV(base, value) (SDHC_WR_SYSCTL_DTOCV(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
+ *
+ * Effects the entire host controller except for the card detection circuit.
+ * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
+ * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
+ * reset this bit to 0 when the capabilities registers are valid and the host driver
+ * can read them. Additional use of software reset for all does not affect the
+ * value of the capabilities registers. After this bit is set, it is recommended
+ * that the host driver reset the external card and reinitialize it.
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define SDHC_WR_SYSCTL_RSTA(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTA_MASK, SDHC_SYSCTL_RSTA(value)))
+#define SDHC_BWR_SYSCTL_RSTA(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
+ *
+ * Only part of the command circuit is reset. The following registers and bits
+ * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTC field to a new value. */
+#define SDHC_WR_SYSCTL_RSTC(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTC_MASK, SDHC_SYSCTL_RSTC(value)))
+#define SDHC_BWR_SYSCTL_RSTC(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
+ *
+ * Only part of the data circuit is reset. DMA circuit is also reset. The
+ * following registers and bits are cleared by this bit: Data Port register Buffer Is
+ * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
+ * Enable Read Transfer Active Write Transfer Active DAT Line Active Command
+ * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
+ * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
+ * Block Gap Event Transfer Complete
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTD field to a new value. */
+#define SDHC_WR_SYSCTL_RSTD(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTD_MASK, SDHC_SYSCTL_RSTD(value)))
+#define SDHC_BWR_SYSCTL_RSTD(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field INITA[27] (RW)
+ *
+ * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
+ * are sent, this bit is self-cleared. This bit is very useful during the card
+ * power-up period when 74 SD-clocks are needed and the clock auto gating feature
+ * is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
+ * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
+ * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
+ * when command line or data lines are active, write to this bit is not allowed.
+ * On the otherhand, when this bit is set, that is, during intialization active
+ * period, it is allowed to issue command, and the command bit stream will appear
+ * on the CMD pad after all 80 clock cycles are done. So when this command ends,
+ * the driver can make sure the 80 clock cycles are sent out. This is very useful
+ * when the driver needs send 80 cycles to the card and does not want to wait
+ * till this bit is self-cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_INITA field. */
+#define SDHC_RD_SYSCTL_INITA(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_INITA_MASK) >> SDHC_SYSCTL_INITA_SHIFT)
+#define SDHC_BRD_SYSCTL_INITA(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_INITA_SHIFT))
+
+/*! @brief Set the INITA field to a new value. */
+#define SDHC_WR_SYSCTL_INITA(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_INITA_MASK, SDHC_SYSCTL_INITA(value)))
+#define SDHC_BWR_SYSCTL_INITA(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_INITA_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSTAT - Interrupt Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * An interrupt is generated when the Normal Interrupt Signal Enable is enabled
+ * and at least one of the status bits is set to 1. For all bits, writing 1 to a
+ * bit clears it; writing to 0 keeps the bit unchanged. More than one status can
+ * be cleared with a single register write. For Card Interrupt, before writing 1
+ * to clear, it is required that the card stops asserting the interrupt, meaning
+ * that when the Card Driver services the interrupt condition, otherwise the CINT
+ * bit will be asserted again. The table below shows the relationship between
+ * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
+ * complete Command timeout error Meaning of the status 0 0 X X 1 Response not
+ * received within 64 SDCLK cycles 1 0 Response received The table below shows the
+ * relationship between the Transfer Complete and the Data Timeout Error. SDHC status
+ * for data timeout error/transfer complete bit combinations Transfer complete
+ * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
+ * transfer 1 X Data transfer complete The table below shows the relationship between
+ * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
+ * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
+ * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
+ * CMD line conflict
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTAT register
+ */
+/*@{*/
+#define SDHC_RD_IRQSTAT(base)    (SDHC_IRQSTAT_REG(base))
+#define SDHC_WR_IRQSTAT(base, value) (SDHC_IRQSTAT_REG(base) = (value))
+#define SDHC_RMW_IRQSTAT(base, mask, value) (SDHC_WR_IRQSTAT(base, (SDHC_RD_IRQSTAT(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) |  (value)))
+#define SDHC_CLR_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) & ~(value)))
+#define SDHC_TOG_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CC[0] (W1C)
+ *
+ * This bit is set when you receive the end bit of the command response, except
+ * Auto CMD12. See PRSSTAT[CIHB].
+ *
+ * Values:
+ * - 0b0 - Command not complete.
+ * - 0b1 - Command complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CC field. */
+#define SDHC_RD_IRQSTAT_CC(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CC_MASK) >> SDHC_IRQSTAT_CC_SHIFT)
+#define SDHC_BRD_IRQSTAT_CC(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CC_SHIFT))
+
+/*! @brief Set the CC field to a new value. */
+#define SDHC_WR_IRQSTAT_CC(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CC(value)))
+#define SDHC_BWR_IRQSTAT_CC(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field TC[1] (W1C)
+ *
+ * This bit is set when a read or write transfer is completed. In the case of a
+ * read transaction: This bit is set at the falling edge of the read transfer
+ * active status. There are two cases in which this interrupt is generated. The
+ * first is when a data transfer is completed as specified by the data length, after
+ * the last data has been read to the host system. The second is when data has
+ * stopped at the block gap and completed the data transfer by setting
+ * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
+ * transaction: This bit is set at the falling edge of the DAT line active
+ * status. There are two cases in which this interrupt is generated. The first is when
+ * the last data is written to the SD card as specified by the data length and
+ * the busy signal is released. The second is when data transfers are stopped at
+ * the block gap, by setting PROCTL[SABGREQ], and the data transfers are
+ * completed,after valid data is written to the SD card and the busy signal released.
+ *
+ * Values:
+ * - 0b0 - Transfer not complete.
+ * - 0b1 - Transfer complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_TC field. */
+#define SDHC_RD_IRQSTAT_TC(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_TC_MASK) >> SDHC_IRQSTAT_TC_SHIFT)
+#define SDHC_BRD_IRQSTAT_TC(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_TC_SHIFT))
+
+/*! @brief Set the TC field to a new value. */
+#define SDHC_WR_IRQSTAT_TC(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_TC(value)))
+#define SDHC_BWR_IRQSTAT_TC(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_TC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
+ *
+ * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
+ * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
+ * set to 1. In the case of a read transaction: This bit is set at the falling
+ * edge of the DAT line active status, when the transaction is stopped at SD Bus
+ * timing. The read wait must be supported in order to use this function. In the
+ * case of write transaction: This bit is set at the falling edge of write transfer
+ * active status, after getting CRC status at SD bus timing.
+ *
+ * Values:
+ * - 0b0 - No block gap event.
+ * - 0b1 - Transaction stopped at block gap.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BGE field. */
+#define SDHC_RD_IRQSTAT_BGE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BGE_MASK) >> SDHC_IRQSTAT_BGE_SHIFT)
+#define SDHC_BRD_IRQSTAT_BGE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BGE_SHIFT))
+
+/*! @brief Set the BGE field to a new value. */
+#define SDHC_WR_IRQSTAT_BGE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BGE(value)))
+#define SDHC_BWR_IRQSTAT_BGE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
+ *
+ * Occurs only when the internal DMA finishes the data transfer successfully.
+ * Whenever errors occur during data transfer, this bit will not be set. Instead,
+ * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
+ * this bit will be set.
+ *
+ * Values:
+ * - 0b0 - No DMA Interrupt.
+ * - 0b1 - DMA Interrupt is generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DINT field. */
+#define SDHC_RD_IRQSTAT_DINT(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DINT_MASK) >> SDHC_IRQSTAT_DINT_SHIFT)
+#define SDHC_BRD_IRQSTAT_DINT(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DINT_SHIFT))
+
+/*! @brief Set the DINT field to a new value. */
+#define SDHC_WR_IRQSTAT_DINT(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DINT(value)))
+#define SDHC_BWR_IRQSTAT_DINT(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
+ *
+ * This status bit is set if the Buffer Write Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0b0 - Not ready to write buffer.
+ * - 0b1 - Ready to write buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BWR field. */
+#define SDHC_RD_IRQSTAT_BWR(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BWR_MASK) >> SDHC_IRQSTAT_BWR_SHIFT)
+#define SDHC_BRD_IRQSTAT_BWR(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BWR_SHIFT))
+
+/*! @brief Set the BWR field to a new value. */
+#define SDHC_WR_IRQSTAT_BWR(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BWR(value)))
+#define SDHC_BWR_IRQSTAT_BWR(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BWR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
+ *
+ * This status bit is set if the Buffer Read Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0b0 - Not ready to read buffer.
+ * - 0b1 - Ready to read buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BRR field. */
+#define SDHC_RD_IRQSTAT_BRR(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BRR_MASK) >> SDHC_IRQSTAT_BRR_SHIFT)
+#define SDHC_BRD_IRQSTAT_BRR(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BRR_SHIFT))
+
+/*! @brief Set the BRR field to a new value. */
+#define SDHC_WR_IRQSTAT_BRR(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BRR(value)))
+#define SDHC_BWR_IRQSTAT_BRR(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 0 to 1. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if a card is inserted. To leave it cleared,
+ * clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0b0 - Card state unstable or removed.
+ * - 0b1 - Card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CINS field. */
+#define SDHC_RD_IRQSTAT_CINS(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CINS_MASK) >> SDHC_IRQSTAT_CINS_SHIFT)
+#define SDHC_BRD_IRQSTAT_CINS(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINS_SHIFT))
+
+/*! @brief Set the CINS field to a new value. */
+#define SDHC_WR_IRQSTAT_CINS(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CINS(value)))
+#define SDHC_BWR_IRQSTAT_CINS(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 1 to 0. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if no card is inserted. To leave it cleared,
+ * clear the Card Removal Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0b0 - Card state unstable or inserted.
+ * - 0b1 - Card removed.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CRM field. */
+#define SDHC_RD_IRQSTAT_CRM(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CRM_MASK) >> SDHC_IRQSTAT_CRM_SHIFT)
+#define SDHC_BRD_IRQSTAT_CRM(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CRM_SHIFT))
+
+/*! @brief Set the CRM field to a new value. */
+#define SDHC_WR_IRQSTAT_CRM(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CRM(value)))
+#define SDHC_BWR_IRQSTAT_CRM(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CRM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
+ *
+ * This status bit is set when an interrupt signal is detected from the external
+ * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
+ * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
+ * during the interrupt cycle, so the interrupt from card can only be sampled
+ * during interrupt cycle, introducing some delay between the interrupt signal from
+ * the SDIO card and the interrupt to the host system. Writing this bit to 1 can
+ * clear this bit, but as the interrupt factor from the SDIO card does not clear,
+ * this bit is set again. To clear this bit, it is required to reset the interrupt
+ * factor from the external card followed by a writing 1 to this bit. When this
+ * status has been set, and the host driver needs to service this interrupt, the
+ * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
+ * 0 to stop driving the interrupt signal to the host system. After completion
+ * of the card interrupt service (it must reset the interrupt factors in the SDIO
+ * card and the interrupt signal may not be asserted), write 1 to clear this bit,
+ * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
+ * signal again.
+ *
+ * Values:
+ * - 0b0 - No Card Interrupt.
+ * - 0b1 - Generate Card Interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CINT field. */
+#define SDHC_RD_IRQSTAT_CINT(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CINT_MASK) >> SDHC_IRQSTAT_CINT_SHIFT)
+#define SDHC_BRD_IRQSTAT_CINT(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINT_SHIFT))
+
+/*! @brief Set the CINT field to a new value. */
+#define SDHC_WR_IRQSTAT_CINT(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CINT(value)))
+#define SDHC_BWR_IRQSTAT_CINT(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
+ *
+ * Occurs only if no response is returned within 64 SDCLK cycles from the end
+ * bit of the command. If the SDHC detects a CMD line conflict, in which case a
+ * Command CRC Error shall also be set, this bit shall be set without waiting for 64
+ * SDCLK cycles. This is because the command will be aborted by the SDHC.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CTOE field. */
+#define SDHC_RD_IRQSTAT_CTOE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CTOE_MASK) >> SDHC_IRQSTAT_CTOE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CTOE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CTOE_SHIFT))
+
+/*! @brief Set the CTOE field to a new value. */
+#define SDHC_WR_IRQSTAT_CTOE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CTOE(value)))
+#define SDHC_BWR_IRQSTAT_CTOE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
+ *
+ * Command CRC Error is generated in two cases. If a response is returned and
+ * the Command Timeout Error is set to 0, indicating no time-out, this bit is set
+ * when detecting a CRC error in the command response. The SDHC detects a CMD line
+ * conflict by monitoring the CMD line when a command is issued. If the SDHC
+ * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
+ * then the SDHC shall abort the command (Stop driving CMD line) and set this bit
+ * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
+ * conflict.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - CRC Error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CCE field. */
+#define SDHC_RD_IRQSTAT_CCE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CCE_MASK) >> SDHC_IRQSTAT_CCE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CCE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CCE_SHIFT))
+
+/*! @brief Set the CCE field to a new value. */
+#define SDHC_WR_IRQSTAT_CCE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CCE(value)))
+#define SDHC_BWR_IRQSTAT_CCE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
+ *
+ * Occurs when detecting that the end bit of a command response is 0.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - End Bit Error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CEBE field. */
+#define SDHC_RD_IRQSTAT_CEBE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CEBE_MASK) >> SDHC_IRQSTAT_CEBE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CEBE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CEBE_SHIFT))
+
+/*! @brief Set the CEBE field to a new value. */
+#define SDHC_WR_IRQSTAT_CEBE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CEBE(value)))
+#define SDHC_BWR_IRQSTAT_CEBE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
+ *
+ * Occurs if a Command Index error occurs in the command response.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CIE field. */
+#define SDHC_RD_IRQSTAT_CIE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CIE_MASK) >> SDHC_IRQSTAT_CIE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CIE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CIE_SHIFT))
+
+/*! @brief Set the CIE field to a new value. */
+#define SDHC_WR_IRQSTAT_CIE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CIE(value)))
+#define SDHC_BWR_IRQSTAT_CIE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
+ *
+ * Occurs when detecting one of following time-out conditions. Busy time-out for
+ * R1b,R5b type Busy time-out after Write CRC status Read Data time-out
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DTOE field. */
+#define SDHC_RD_IRQSTAT_DTOE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DTOE_MASK) >> SDHC_IRQSTAT_DTOE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DTOE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DTOE_SHIFT))
+
+/*! @brief Set the DTOE field to a new value. */
+#define SDHC_WR_IRQSTAT_DTOE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DTOE(value)))
+#define SDHC_BWR_IRQSTAT_DTOE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
+ *
+ * Occurs when detecting a CRC error when transferring read data, which uses the
+ * DAT line, or when detecting the Write CRC status having a value other than
+ * 010.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DCE field. */
+#define SDHC_RD_IRQSTAT_DCE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DCE_MASK) >> SDHC_IRQSTAT_DCE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DCE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DCE_SHIFT))
+
+/*! @brief Set the DCE field to a new value. */
+#define SDHC_WR_IRQSTAT_DCE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DCE(value)))
+#define SDHC_BWR_IRQSTAT_DCE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
+ *
+ * Occurs either when detecting 0 at the end bit position of read data, which
+ * uses the DAT line, or at the end bit position of the CRC.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DEBE field. */
+#define SDHC_RD_IRQSTAT_DEBE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DEBE_MASK) >> SDHC_IRQSTAT_DEBE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DEBE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DEBE_SHIFT))
+
+/*! @brief Set the DEBE field to a new value. */
+#define SDHC_WR_IRQSTAT_DEBE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DEBE(value)))
+#define SDHC_BWR_IRQSTAT_DEBE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
+ *
+ * Occurs when detecting that one of the bits in the Auto CMD12 Error Status
+ * register has changed from 0 to 1. This bit is set to 1, not only when the errors
+ * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
+ * previous command error.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_AC12E field. */
+#define SDHC_RD_IRQSTAT_AC12E(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_AC12E_MASK) >> SDHC_IRQSTAT_AC12E_SHIFT)
+#define SDHC_BRD_IRQSTAT_AC12E(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_AC12E_SHIFT))
+
+/*! @brief Set the AC12E field to a new value. */
+#define SDHC_WR_IRQSTAT_AC12E(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_AC12E(value)))
+#define SDHC_BWR_IRQSTAT_AC12E(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_AC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
+ *
+ * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
+ * some error occurs in the data transfer. This error can be caused by either
+ * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
+ * Address register is the next fetch address where the error occurs. Because any
+ * error corrupts the whole data block, the host driver shall restart the transfer
+ * from the corrupted block boundary. The address of the block boundary can be
+ * calculated either from the current DSADDR value or from the remaining number of
+ * blocks and the block size.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DMAE field. */
+#define SDHC_RD_IRQSTAT_DMAE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DMAE_MASK) >> SDHC_IRQSTAT_DMAE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DMAE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DMAE_SHIFT))
+
+/*! @brief Set the DMAE field to a new value. */
+#define SDHC_WR_IRQSTAT_DMAE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DMAE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK), SDHC_IRQSTAT_DMAE(value)))
+#define SDHC_BWR_IRQSTAT_DMAE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DMAE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSTATEN - Interrupt Status Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
+ *
+ * Reset value: 0x117F013FU
+ *
+ * Setting the bits in this register to 1 enables the corresponding interrupt
+ * status to be set by the specified event. If any bit is cleared, the
+ * corresponding interrupt status bit is also cleared, that is, when the bit in this register
+ * is cleared, the corresponding bit in interrupt status register is always 0.
+ * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
+ * card interrupt signal during the interrupt period and hold its value in the
+ * flip-flop. There will be some delays on the card interrupt, asserted from the card,
+ * to the time the host system is informed. To detect a CMD line conflict, the
+ * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTATEN register
+ */
+/*@{*/
+#define SDHC_RD_IRQSTATEN(base)  (SDHC_IRQSTATEN_REG(base))
+#define SDHC_WR_IRQSTATEN(base, value) (SDHC_IRQSTATEN_REG(base) = (value))
+#define SDHC_RMW_IRQSTATEN(base, mask, value) (SDHC_WR_IRQSTATEN(base, (SDHC_RD_IRQSTATEN(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) |  (value)))
+#define SDHC_CLR_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) & ~(value)))
+#define SDHC_TOG_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSTATEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field. */
+#define SDHC_RD_IRQSTATEN_CCSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CCSEN_MASK) >> SDHC_IRQSTATEN_CCSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CCSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCSEN_SHIFT))
+
+/*! @brief Set the CCSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CCSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CCSEN_MASK, SDHC_IRQSTATEN_CCSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CCSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field. */
+#define SDHC_RD_IRQSTATEN_TCSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_TCSEN_MASK) >> SDHC_IRQSTATEN_TCSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_TCSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_TCSEN_SHIFT))
+
+/*! @brief Set the TCSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_TCSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_TCSEN_MASK, SDHC_IRQSTATEN_TCSEN(value)))
+#define SDHC_BWR_IRQSTATEN_TCSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_TCSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field. */
+#define SDHC_RD_IRQSTATEN_BGESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BGESEN_MASK) >> SDHC_IRQSTATEN_BGESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BGESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BGESEN_SHIFT))
+
+/*! @brief Set the BGESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BGESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BGESEN_MASK, SDHC_IRQSTATEN_BGESEN(value)))
+#define SDHC_BWR_IRQSTATEN_BGESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BGESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field. */
+#define SDHC_RD_IRQSTATEN_DINTSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DINTSEN_MASK) >> SDHC_IRQSTATEN_DINTSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DINTSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DINTSEN_SHIFT))
+
+/*! @brief Set the DINTSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DINTSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DINTSEN_MASK, SDHC_IRQSTATEN_DINTSEN(value)))
+#define SDHC_BWR_IRQSTATEN_DINTSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DINTSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field. */
+#define SDHC_RD_IRQSTATEN_BWRSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BWRSEN_MASK) >> SDHC_IRQSTATEN_BWRSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BWRSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BWRSEN_SHIFT))
+
+/*! @brief Set the BWRSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BWRSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BWRSEN_MASK, SDHC_IRQSTATEN_BWRSEN(value)))
+#define SDHC_BWR_IRQSTATEN_BWRSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BWRSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field. */
+#define SDHC_RD_IRQSTATEN_BRRSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BRRSEN_MASK) >> SDHC_IRQSTATEN_BRRSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BRRSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BRRSEN_SHIFT))
+
+/*! @brief Set the BRRSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BRRSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BRRSEN_MASK, SDHC_IRQSTATEN_BRRSEN(value)))
+#define SDHC_BWR_IRQSTATEN_BRRSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BRRSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field. */
+#define SDHC_RD_IRQSTATEN_CINSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CINSEN_MASK) >> SDHC_IRQSTATEN_CINSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CINSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINSEN_SHIFT))
+
+/*! @brief Set the CINSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CINSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CINSEN_MASK, SDHC_IRQSTATEN_CINSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CINSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field. */
+#define SDHC_RD_IRQSTATEN_CRMSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CRMSEN_MASK) >> SDHC_IRQSTATEN_CRMSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CRMSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CRMSEN_SHIFT))
+
+/*! @brief Set the CRMSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CRMSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CRMSEN_MASK, SDHC_IRQSTATEN_CRMSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CRMSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CRMSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
+ *
+ * If this bit is set to 0, the SDHC will clear the interrupt request to the
+ * system. The card interrupt detection is stopped when this bit is cleared and
+ * restarted when this bit is set to 1. The host driver must clear the this bit
+ * before servicing the card interrupt and must set this bit again after all interrupt
+ * requests from the card are cleared to prevent inadvertent interrupts.
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field. */
+#define SDHC_RD_IRQSTATEN_CINTSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CINTSEN_MASK) >> SDHC_IRQSTATEN_CINTSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CINTSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINTSEN_SHIFT))
+
+/*! @brief Set the CINTSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CINTSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CINTSEN_MASK, SDHC_IRQSTATEN_CINTSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CINTSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINTSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field. */
+#define SDHC_RD_IRQSTATEN_CTOESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CTOESEN_MASK) >> SDHC_IRQSTATEN_CTOESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CTOESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CTOESEN_SHIFT))
+
+/*! @brief Set the CTOESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CTOESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CTOESEN_MASK, SDHC_IRQSTATEN_CTOESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CTOESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CTOESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field. */
+#define SDHC_RD_IRQSTATEN_CCESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CCESEN_MASK) >> SDHC_IRQSTATEN_CCESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CCESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCESEN_SHIFT))
+
+/*! @brief Set the CCESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CCESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CCESEN_MASK, SDHC_IRQSTATEN_CCESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CCESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field. */
+#define SDHC_RD_IRQSTATEN_CEBESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CEBESEN_MASK) >> SDHC_IRQSTATEN_CEBESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CEBESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CEBESEN_SHIFT))
+
+/*! @brief Set the CEBESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CEBESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CEBESEN_MASK, SDHC_IRQSTATEN_CEBESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CEBESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CEBESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field. */
+#define SDHC_RD_IRQSTATEN_CIESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CIESEN_MASK) >> SDHC_IRQSTATEN_CIESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CIESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CIESEN_SHIFT))
+
+/*! @brief Set the CIESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CIESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CIESEN_MASK, SDHC_IRQSTATEN_CIESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CIESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CIESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field. */
+#define SDHC_RD_IRQSTATEN_DTOESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DTOESEN_MASK) >> SDHC_IRQSTATEN_DTOESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DTOESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DTOESEN_SHIFT))
+
+/*! @brief Set the DTOESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DTOESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DTOESEN_MASK, SDHC_IRQSTATEN_DTOESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DTOESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DTOESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field. */
+#define SDHC_RD_IRQSTATEN_DCESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DCESEN_MASK) >> SDHC_IRQSTATEN_DCESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DCESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DCESEN_SHIFT))
+
+/*! @brief Set the DCESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DCESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DCESEN_MASK, SDHC_IRQSTATEN_DCESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DCESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DCESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field. */
+#define SDHC_RD_IRQSTATEN_DEBESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DEBESEN_MASK) >> SDHC_IRQSTATEN_DEBESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DEBESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DEBESEN_SHIFT))
+
+/*! @brief Set the DEBESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DEBESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DEBESEN_MASK, SDHC_IRQSTATEN_DEBESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DEBESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DEBESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field. */
+#define SDHC_RD_IRQSTATEN_AC12ESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_AC12ESEN_MASK) >> SDHC_IRQSTATEN_AC12ESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_AC12ESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_AC12ESEN_SHIFT))
+
+/*! @brief Set the AC12ESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_AC12ESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_AC12ESEN_MASK, SDHC_IRQSTATEN_AC12ESEN(value)))
+#define SDHC_BWR_IRQSTATEN_AC12ESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_AC12ESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field. */
+#define SDHC_RD_IRQSTATEN_DMAESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DMAESEN_MASK) >> SDHC_IRQSTATEN_DMAESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DMAESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DMAESEN_SHIFT))
+
+/*! @brief Set the DMAESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DMAESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DMAESEN_MASK, SDHC_IRQSTATEN_DMAESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DMAESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DMAESEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSIGEN - Interrupt Signal Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to select which interrupt status is indicated to the
+ * host system as the interrupt. All of these status bits share the same interrupt
+ * line. Setting any of these bits to 1 enables interrupt generation. The
+ * corresponding status register bit will generate an interrupt when the corresponding
+ * interrupt signal enable bit is set.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSIGEN register
+ */
+/*@{*/
+#define SDHC_RD_IRQSIGEN(base)   (SDHC_IRQSIGEN_REG(base))
+#define SDHC_WR_IRQSIGEN(base, value) (SDHC_IRQSIGEN_REG(base) = (value))
+#define SDHC_RMW_IRQSIGEN(base, mask, value) (SDHC_WR_IRQSIGEN(base, (SDHC_RD_IRQSIGEN(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) |  (value)))
+#define SDHC_CLR_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) & ~(value)))
+#define SDHC_TOG_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSIGEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field. */
+#define SDHC_RD_IRQSIGEN_CCIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CCIEN_MASK) >> SDHC_IRQSIGEN_CCIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CCIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCIEN_SHIFT))
+
+/*! @brief Set the CCIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CCIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CCIEN_MASK, SDHC_IRQSIGEN_CCIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CCIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field. */
+#define SDHC_RD_IRQSIGEN_TCIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_TCIEN_MASK) >> SDHC_IRQSIGEN_TCIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_TCIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_TCIEN_SHIFT))
+
+/*! @brief Set the TCIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_TCIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_TCIEN_MASK, SDHC_IRQSIGEN_TCIEN(value)))
+#define SDHC_BWR_IRQSIGEN_TCIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_TCIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field. */
+#define SDHC_RD_IRQSIGEN_BGEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BGEIEN_MASK) >> SDHC_IRQSIGEN_BGEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BGEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BGEIEN_SHIFT))
+
+/*! @brief Set the BGEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BGEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BGEIEN_MASK, SDHC_IRQSIGEN_BGEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BGEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BGEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field. */
+#define SDHC_RD_IRQSIGEN_DINTIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DINTIEN_MASK) >> SDHC_IRQSIGEN_DINTIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DINTIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DINTIEN_SHIFT))
+
+/*! @brief Set the DINTIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DINTIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DINTIEN_MASK, SDHC_IRQSIGEN_DINTIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DINTIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DINTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field. */
+#define SDHC_RD_IRQSIGEN_BWRIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BWRIEN_MASK) >> SDHC_IRQSIGEN_BWRIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BWRIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BWRIEN_SHIFT))
+
+/*! @brief Set the BWRIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BWRIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BWRIEN_MASK, SDHC_IRQSIGEN_BWRIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BWRIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BWRIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field. */
+#define SDHC_RD_IRQSIGEN_BRRIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BRRIEN_MASK) >> SDHC_IRQSIGEN_BRRIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BRRIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BRRIEN_SHIFT))
+
+/*! @brief Set the BRRIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BRRIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BRRIEN_MASK, SDHC_IRQSIGEN_BRRIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BRRIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BRRIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field. */
+#define SDHC_RD_IRQSIGEN_CINSIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CINSIEN_MASK) >> SDHC_IRQSIGEN_CINSIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CINSIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINSIEN_SHIFT))
+
+/*! @brief Set the CINSIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CINSIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CINSIEN_MASK, SDHC_IRQSIGEN_CINSIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CINSIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINSIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field. */
+#define SDHC_RD_IRQSIGEN_CRMIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CRMIEN_MASK) >> SDHC_IRQSIGEN_CRMIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CRMIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CRMIEN_SHIFT))
+
+/*! @brief Set the CRMIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CRMIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CRMIEN_MASK, SDHC_IRQSIGEN_CRMIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CRMIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CRMIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field. */
+#define SDHC_RD_IRQSIGEN_CINTIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CINTIEN_MASK) >> SDHC_IRQSIGEN_CINTIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CINTIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINTIEN_SHIFT))
+
+/*! @brief Set the CINTIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CINTIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CINTIEN_MASK, SDHC_IRQSIGEN_CINTIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CINTIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field. */
+#define SDHC_RD_IRQSIGEN_CTOEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CTOEIEN_MASK) >> SDHC_IRQSIGEN_CTOEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CTOEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CTOEIEN_SHIFT))
+
+/*! @brief Set the CTOEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CTOEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CTOEIEN_MASK, SDHC_IRQSIGEN_CTOEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CTOEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CTOEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field. */
+#define SDHC_RD_IRQSIGEN_CCEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CCEIEN_MASK) >> SDHC_IRQSIGEN_CCEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CCEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCEIEN_SHIFT))
+
+/*! @brief Set the CCEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CCEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CCEIEN_MASK, SDHC_IRQSIGEN_CCEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CCEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field. */
+#define SDHC_RD_IRQSIGEN_CEBEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CEBEIEN_MASK) >> SDHC_IRQSIGEN_CEBEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CEBEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CEBEIEN_SHIFT))
+
+/*! @brief Set the CEBEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CEBEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CEBEIEN_MASK, SDHC_IRQSIGEN_CEBEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CEBEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CEBEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field. */
+#define SDHC_RD_IRQSIGEN_CIEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CIEIEN_MASK) >> SDHC_IRQSIGEN_CIEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CIEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CIEIEN_SHIFT))
+
+/*! @brief Set the CIEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CIEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CIEIEN_MASK, SDHC_IRQSIGEN_CIEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CIEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CIEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field. */
+#define SDHC_RD_IRQSIGEN_DTOEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DTOEIEN_MASK) >> SDHC_IRQSIGEN_DTOEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DTOEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DTOEIEN_SHIFT))
+
+/*! @brief Set the DTOEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DTOEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DTOEIEN_MASK, SDHC_IRQSIGEN_DTOEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DTOEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DTOEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field. */
+#define SDHC_RD_IRQSIGEN_DCEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DCEIEN_MASK) >> SDHC_IRQSIGEN_DCEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DCEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DCEIEN_SHIFT))
+
+/*! @brief Set the DCEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DCEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DCEIEN_MASK, SDHC_IRQSIGEN_DCEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DCEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DCEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field. */
+#define SDHC_RD_IRQSIGEN_DEBEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DEBEIEN_MASK) >> SDHC_IRQSIGEN_DEBEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DEBEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DEBEIEN_SHIFT))
+
+/*! @brief Set the DEBEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DEBEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DEBEIEN_MASK, SDHC_IRQSIGEN_DEBEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DEBEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DEBEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field. */
+#define SDHC_RD_IRQSIGEN_AC12EIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_AC12EIEN_MASK) >> SDHC_IRQSIGEN_AC12EIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_AC12EIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_AC12EIEN_SHIFT))
+
+/*! @brief Set the AC12EIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_AC12EIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_AC12EIEN_MASK, SDHC_IRQSIGEN_AC12EIEN(value)))
+#define SDHC_BWR_IRQSIGEN_AC12EIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_AC12EIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field. */
+#define SDHC_RD_IRQSIGEN_DMAEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DMAEIEN_MASK) >> SDHC_IRQSIGEN_DMAEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DMAEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DMAEIEN_SHIFT))
+
+/*! @brief Set the DMAEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DMAEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DMAEIEN_MASK, SDHC_IRQSIGEN_DMAEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DMAEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DMAEIEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_AC12ERR - Auto CMD12 Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the AC12ESEN bit in the Status register is set, the host driver shall
+ * check this register to identify what kind of error the Auto CMD12 indicated.
+ * This register is valid only when the Auto CMD12 Error status bit is set. The
+ * following table shows the relationship between the Auto CMGD12 CRC error and the
+ * Auto CMD12 command timeout error. Relationship between Command CRC Error and
+ * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
+ * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
+ * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
+ * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
+ * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
+ * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
+ * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
+ * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
+ * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
+ * command that can't be issued. Clear bit 7 if there is no command to issue. The
+ * timing for generating the auto CMD12 error and writing to the command register
+ * are asynchronous. After that, bit 7 shall be sampled when the driver is not
+ * writing to the command register. So it is suggested to read this register only
+ * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
+ * of the error bits (0-4) is set to 1. The command not issued by auto CMD12
+ * error does not generate an interrupt.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_AC12ERR register
+ */
+/*@{*/
+#define SDHC_RD_AC12ERR(base)    (SDHC_AC12ERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_AC12ERR bitfields
+ */
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
+ *
+ * If memory multiple block data transfer is not started, due to a command
+ * error, this bit is not set because it is not necessary to issue an auto CMD12.
+ * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
+ * multiple block data transfer due to some error. If this bit is set to 1, other
+ * error status bits (1-4) have no meaning.
+ *
+ * Values:
+ * - 0b0 - Executed.
+ * - 0b1 - Not executed.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12NE field. */
+#define SDHC_RD_AC12ERR_AC12NE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12NE_MASK) >> SDHC_AC12ERR_AC12NE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12NE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12NE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
+ *
+ * Occurs if no response is returned within 64 SDCLK cycles from the end bit of
+ * the command. If this bit is set to 1, the other error status bits (2-4) have
+ * no meaning.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12TOE field. */
+#define SDHC_RD_AC12ERR_AC12TOE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12TOE_MASK) >> SDHC_AC12ERR_AC12TOE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12TOE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12TOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
+ *
+ * Occurs when detecting that the end bit of command response is 0 which must be
+ * 1.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - End bit error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12EBE field. */
+#define SDHC_RD_AC12ERR_AC12EBE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12EBE_MASK) >> SDHC_AC12ERR_AC12EBE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12EBE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12EBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
+ *
+ * Occurs when detecting a CRC error in the command response.
+ *
+ * Values:
+ * - 0b0 - No CRC error.
+ * - 0b1 - CRC error met in Auto CMD12 response.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12CE field. */
+#define SDHC_RD_AC12ERR_AC12CE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12CE_MASK) >> SDHC_AC12ERR_AC12CE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12CE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12CE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
+ *
+ * Occurs if the command index error occurs in response to a command.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error, the CMD index in response is not CMD12.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12IE field. */
+#define SDHC_RD_AC12ERR_AC12IE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12IE_MASK) >> SDHC_AC12ERR_AC12IE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12IE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12IE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
+ *
+ * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
+ * error (D04-D01) in this register.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Not issued.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field. */
+#define SDHC_RD_AC12ERR_CNIBAC12E(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_CNIBAC12E_MASK) >> SDHC_AC12ERR_CNIBAC12E_SHIFT)
+#define SDHC_BRD_AC12ERR_CNIBAC12E(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_CNIBAC12E_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_HTCAPBLT - Host Controller Capabilities
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_HTCAPBLT - Host Controller Capabilities (RO)
+ *
+ * Reset value: 0x07F30000U
+ *
+ * This register provides the host driver with information specific to the SDHC
+ * implementation. The value in this register is the power-on-reset value, and
+ * does not change with a software reset. Any write to this register is ignored.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_HTCAPBLT register
+ */
+/*@{*/
+#define SDHC_RD_HTCAPBLT(base)   (SDHC_HTCAPBLT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_HTCAPBLT bitfields
+ */
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
+ *
+ * This value indicates the maximum block size that the host driver can read and
+ * write to the buffer in the SDHC. The buffer shall transfer block size without
+ * wait cycles.
+ *
+ * Values:
+ * - 0b000 - 512 bytes
+ * - 0b001 - 1024 bytes
+ * - 0b010 - 2048 bytes
+ * - 0b011 - 4096 bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_MBL field. */
+#define SDHC_RD_HTCAPBLT_MBL(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_MBL_MASK) >> SDHC_HTCAPBLT_MBL_SHIFT)
+#define SDHC_BRD_HTCAPBLT_MBL(base) (SDHC_RD_HTCAPBLT_MBL(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
+ *
+ * This bit indicates whether the SDHC supports the ADMA feature.
+ *
+ * Values:
+ * - 0b0 - Advanced DMA not supported.
+ * - 0b1 - Advanced DMA supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field. */
+#define SDHC_RD_HTCAPBLT_ADMAS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_ADMAS_MASK) >> SDHC_HTCAPBLT_ADMAS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_ADMAS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_ADMAS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
+ *
+ * This bit indicates whether the SDHC supports high speed mode and the host
+ * system can supply a SD Clock frequency from 25 MHz to 50 MHz.
+ *
+ * Values:
+ * - 0b0 - High speed not supported.
+ * - 0b1 - High speed supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_HSS field. */
+#define SDHC_RD_HTCAPBLT_HSS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_HSS_MASK) >> SDHC_HTCAPBLT_HSS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_HSS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_HSS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
+ *
+ * This bit indicates whether the SDHC is capable of using the internal DMA to
+ * transfer data between system memory and the data buffer directly.
+ *
+ * Values:
+ * - 0b0 - DMA not supported.
+ * - 0b1 - DMA supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_DMAS field. */
+#define SDHC_RD_HTCAPBLT_DMAS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_DMAS_MASK) >> SDHC_HTCAPBLT_DMAS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_DMAS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_DMAS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
+ *
+ * This bit indicates whether the SDHC supports suspend / resume functionality.
+ * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
+ * are not supported, and the host driver shall not issue either suspend or
+ * resume commands.
+ *
+ * Values:
+ * - 0b0 - Not supported.
+ * - 0b1 - Supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_SRS field. */
+#define SDHC_RD_HTCAPBLT_SRS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_SRS_MASK) >> SDHC_HTCAPBLT_SRS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_SRS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_SRS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
+ *
+ * This bit shall depend on the host system ability.
+ *
+ * Values:
+ * - 0b0 - 3.3 V not supported.
+ * - 0b1 - 3.3 V supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_VS33 field. */
+#define SDHC_RD_HTCAPBLT_VS33(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_VS33_MASK) >> SDHC_HTCAPBLT_VS33_SHIFT)
+#define SDHC_BRD_HTCAPBLT_VS33(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_VS33_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_WML - Watermark Level Register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_WML - Watermark Level Register (RW)
+ *
+ * Reset value: 0x00100010U
+ *
+ * Both write and read watermark levels (FIFO threshold) are configurable. There
+ * value can range from 1 to 128 words. Both write and read burst lengths are
+ * also configurable. There value can range from 1 to 31 words.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_WML register
+ */
+/*@{*/
+#define SDHC_RD_WML(base)        (SDHC_WML_REG(base))
+#define SDHC_WR_WML(base, value) (SDHC_WML_REG(base) = (value))
+#define SDHC_RMW_WML(base, mask, value) (SDHC_WR_WML(base, (SDHC_RD_WML(base) & ~(mask)) | (value)))
+#define SDHC_SET_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) |  (value)))
+#define SDHC_CLR_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) & ~(value)))
+#define SDHC_TOG_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_WML bitfields
+ */
+
+/*!
+ * @name Register SDHC_WML, field RDWML[7:0] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * read operation. Also the number of words as a sequence of read bursts in
+ * back-to-back mode. The maximum legal value for the read water mark level is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_WML_RDWML field. */
+#define SDHC_RD_WML_RDWML(base) ((SDHC_WML_REG(base) & SDHC_WML_RDWML_MASK) >> SDHC_WML_RDWML_SHIFT)
+#define SDHC_BRD_WML_RDWML(base) (SDHC_RD_WML_RDWML(base))
+
+/*! @brief Set the RDWML field to a new value. */
+#define SDHC_WR_WML_RDWML(base, value) (SDHC_RMW_WML(base, SDHC_WML_RDWML_MASK, SDHC_WML_RDWML(value)))
+#define SDHC_BWR_WML_RDWML(base, value) (SDHC_WR_WML_RDWML(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_WML, field WRWML[23:16] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * write operation. Also the number of words as a sequence of write bursts in
+ * back-to-back mode. The maximum legal value for the write watermark level is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_WML_WRWML field. */
+#define SDHC_RD_WML_WRWML(base) ((SDHC_WML_REG(base) & SDHC_WML_WRWML_MASK) >> SDHC_WML_WRWML_SHIFT)
+#define SDHC_BRD_WML_WRWML(base) (SDHC_RD_WML_WRWML(base))
+
+/*! @brief Set the WRWML field to a new value. */
+#define SDHC_WR_WML_WRWML(base, value) (SDHC_RMW_WML(base, SDHC_WML_WRWML_MASK, SDHC_WML_WRWML(value)))
+#define SDHC_BWR_WML_WRWML(base, value) (SDHC_WR_WML_WRWML(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_FEVT - Force Event register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_FEVT - Force Event register (WO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Force Event (FEVT) register is not a physically implemented register.
+ * Rather, it is an address at which the Interrupt Status register can be written if
+ * the corresponding bit of the Interrupt Status Enable register is set. This
+ * register is a write only register and writing 0 to it has no effect. Writing 1
+ * to this register actually sets the corresponding bit of Interrupt Status
+ * register. A read from this register always results in 0's. To change the
+ * corresponding status bits in the interrupt status register, make sure to set
+ * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
+ * short pulse on the DAT[1] line, and the driver may treat this interrupt as a
+ * normal interrupt. The interrupt service routine may skip polling the card
+ * interrupt factor as the interrupt is selfcleared.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_FEVT register
+ */
+/*@{*/
+#define SDHC_RD_FEVT(base)       (SDHC_FEVT_REG(base))
+#define SDHC_WR_FEVT(base, value) (SDHC_FEVT_REG(base) = (value))
+#define SDHC_RMW_FEVT(base, mask, value) (SDHC_WR_FEVT(base, (SDHC_RD_FEVT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_FEVT bitfields
+ */
+
+/*!
+ * @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
+ *
+ * Forces AC12ERR[AC12NE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12NE field to a new value. */
+#define SDHC_WR_FEVT_AC12NE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12NE_MASK, SDHC_FEVT_AC12NE(value)))
+#define SDHC_BWR_FEVT_AC12NE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12NE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
+ *
+ * Forces AC12ERR[AC12TOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12TOE field to a new value. */
+#define SDHC_WR_FEVT_AC12TOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12TOE_MASK, SDHC_FEVT_AC12TOE(value)))
+#define SDHC_BWR_FEVT_AC12TOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12TOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
+ *
+ * Forces AC12ERR[AC12CE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12CE field to a new value. */
+#define SDHC_WR_FEVT_AC12CE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12CE_MASK, SDHC_FEVT_AC12CE(value)))
+#define SDHC_BWR_FEVT_AC12CE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12CE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
+ *
+ * Forces AC12ERR[AC12EBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12EBE field to a new value. */
+#define SDHC_WR_FEVT_AC12EBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12EBE_MASK, SDHC_FEVT_AC12EBE(value)))
+#define SDHC_BWR_FEVT_AC12EBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12EBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
+ *
+ * Forces AC12ERR[AC12IE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12IE field to a new value. */
+#define SDHC_WR_FEVT_AC12IE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12IE_MASK, SDHC_FEVT_AC12IE(value)))
+#define SDHC_BWR_FEVT_AC12IE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
+ *
+ * Forces AC12ERR[CNIBAC12E] to be set.
+ */
+/*@{*/
+/*! @brief Set the CNIBAC12E field to a new value. */
+#define SDHC_WR_FEVT_CNIBAC12E(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CNIBAC12E_MASK, SDHC_FEVT_CNIBAC12E(value)))
+#define SDHC_BWR_FEVT_CNIBAC12E(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CNIBAC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CTOE[16] (WORZ)
+ *
+ * Forces IRQSTAT[CTOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CTOE field to a new value. */
+#define SDHC_WR_FEVT_CTOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CTOE_MASK, SDHC_FEVT_CTOE(value)))
+#define SDHC_BWR_FEVT_CTOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CCE[17] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CCE field to a new value. */
+#define SDHC_WR_FEVT_CCE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CCE_MASK, SDHC_FEVT_CCE(value)))
+#define SDHC_BWR_FEVT_CCE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CEBE[18] (WORZ)
+ *
+ * Forces IRQSTAT[CEBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CEBE field to a new value. */
+#define SDHC_WR_FEVT_CEBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CEBE_MASK, SDHC_FEVT_CEBE(value)))
+#define SDHC_BWR_FEVT_CEBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CIE[19] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CIE field to a new value. */
+#define SDHC_WR_FEVT_CIE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CIE_MASK, SDHC_FEVT_CIE(value)))
+#define SDHC_BWR_FEVT_CIE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DTOE[20] (WORZ)
+ *
+ * Forces IRQSTAT[DTOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DTOE field to a new value. */
+#define SDHC_WR_FEVT_DTOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DTOE_MASK, SDHC_FEVT_DTOE(value)))
+#define SDHC_BWR_FEVT_DTOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DCE[21] (WORZ)
+ *
+ * Forces IRQSTAT[DCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DCE field to a new value. */
+#define SDHC_WR_FEVT_DCE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DCE_MASK, SDHC_FEVT_DCE(value)))
+#define SDHC_BWR_FEVT_DCE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DEBE[22] (WORZ)
+ *
+ * Forces IRQSTAT[DEBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DEBE field to a new value. */
+#define SDHC_WR_FEVT_DEBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DEBE_MASK, SDHC_FEVT_DEBE(value)))
+#define SDHC_BWR_FEVT_DEBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12E[24] (WORZ)
+ *
+ * Forces IRQSTAT[AC12E] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12E field to a new value. */
+#define SDHC_WR_FEVT_AC12E(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12E_MASK, SDHC_FEVT_AC12E(value)))
+#define SDHC_BWR_FEVT_AC12E(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DMAE[28] (WORZ)
+ *
+ * Forces the DMAE bit of Interrupt Status Register to be set.
+ */
+/*@{*/
+/*! @brief Set the DMAE field to a new value. */
+#define SDHC_WR_FEVT_DMAE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DMAE_MASK, SDHC_FEVT_DMAE(value)))
+#define SDHC_BWR_FEVT_DMAE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DMAE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CINT[31] (WORZ)
+ *
+ * Writing 1 to this bit generates a short low-level pulse on the internal
+ * DAT[1] line, as if a self-clearing interrupt was received from the external card.
+ * If enabled, the CINT bit will be set and the interrupt service routine may
+ * treat this interrupt as a normal interrupt from the external card.
+ */
+/*@{*/
+/*! @brief Set the CINT field to a new value. */
+#define SDHC_WR_FEVT_CINT(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CINT_MASK, SDHC_FEVT_CINT(value)))
+#define SDHC_BWR_FEVT_CINT(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CINT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_ADMAES - ADMA Error Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_ADMAES - ADMA Error Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an ADMA error interrupt has occurred, the ADMA Error States field in
+ * this register holds the ADMA state and the ADMA System Address register holds the
+ * address around the error descriptor. For recovering from this error, the host
+ * driver requires the ADMA state to identify the error descriptor address as
+ * follows: ST_STOP: Previous location set in the ADMA System Address register is
+ * the error descriptor address. ST_FDS: Current location set in the ADMA System
+ * Address register is the error descriptor address. ST_CADR: This state is never
+ * set because it only increments the descriptor pointer and doesn't generate an
+ * ADMA error. ST_TFR: Previous location set in the ADMA System Address register
+ * is the error descriptor address. In case of a write operation, the host driver
+ * must use the ACMD22 to get the number of the written block, rather than using
+ * this information, because unwritten data may exist in the host controller.
+ * The host controller generates the ADMA error interrupt when it detects invalid
+ * descriptor data (valid = 0) in the ST_FDS state. The host driver can
+ * distinguish this error by reading the valid bit of the error descriptor. ADMA Error
+ * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
+ * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
+ * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
+ * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
+ * (Transfer Data) Holds the address of the next executable descriptor command
+ */
+/*!
+ * @name Constants and macros for entire SDHC_ADMAES register
+ */
+/*@{*/
+#define SDHC_RD_ADMAES(base)     (SDHC_ADMAES_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_ADMAES bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
+ *
+ * Indicates the state of the ADMA when an error has occurred during an ADMA
+ * data transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMAES field. */
+#define SDHC_RD_ADMAES_ADMAES(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMAES_MASK) >> SDHC_ADMAES_ADMAES_SHIFT)
+#define SDHC_BRD_ADMAES_ADMAES(base) (SDHC_RD_ADMAES_ADMAES(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMALME[2] (RO)
+ *
+ * This error occurs in the following 2 cases: While the block count enable is
+ * being set, the total data length specified by the descriptor table is different
+ * from that specified by the block count and block length. Total data length
+ * can not be divided by the block length.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMALME field. */
+#define SDHC_RD_ADMAES_ADMALME(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMALME_MASK) >> SDHC_ADMAES_ADMALME_SHIFT)
+#define SDHC_BRD_ADMAES_ADMALME(base) (BITBAND_ACCESS32(&SDHC_ADMAES_REG(base), SDHC_ADMAES_ADMALME_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
+ *
+ * This error occurs when an invalid descriptor is fetched by ADMA.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMADCE field. */
+#define SDHC_RD_ADMAES_ADMADCE(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMADCE_MASK) >> SDHC_ADMAES_ADMADCE_SHIFT)
+#define SDHC_BRD_ADMAES_ADMADCE(base) (BITBAND_ACCESS32(&SDHC_ADMAES_REG(base), SDHC_ADMAES_ADMADCE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_ADSADDR - ADMA System Addressregister
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_ADSADDR - ADMA System Addressregister (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for ADMA
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_ADSADDR register
+ */
+/*@{*/
+#define SDHC_RD_ADSADDR(base)    (SDHC_ADSADDR_REG(base))
+#define SDHC_WR_ADSADDR(base, value) (SDHC_ADSADDR_REG(base) = (value))
+#define SDHC_RMW_ADSADDR(base, mask, value) (SDHC_WR_ADSADDR(base, (SDHC_RD_ADSADDR(base) & ~(mask)) | (value)))
+#define SDHC_SET_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) |  (value)))
+#define SDHC_CLR_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) & ~(value)))
+#define SDHC_TOG_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_ADSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
+ *
+ * Holds the word address of the executing command in the descriptor table. At
+ * the start of ADMA, the host driver shall set the start address of the
+ * Descriptor table. The ADMA engine increments this register address whenever fetching a
+ * descriptor command. When the ADMA is stopped at the block gap, this register
+ * indicates the address of the next executable descriptor command. When the ADMA
+ * error interrupt is generated, this register shall hold the valid descriptor
+ * address depending on the ADMA state. The lower 2 bits of this register is tied
+ * to '0' so the ADMA address is always word-aligned. Because this register
+ * supports dynamic address reflecting, when TC bit is set, it automatically alters the
+ * value of internal address counter, so SW cannot change this register when TC
+ * bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADSADDR_ADSADDR field. */
+#define SDHC_RD_ADSADDR_ADSADDR(base) ((SDHC_ADSADDR_REG(base) & SDHC_ADSADDR_ADSADDR_MASK) >> SDHC_ADSADDR_ADSADDR_SHIFT)
+#define SDHC_BRD_ADSADDR_ADSADDR(base) (SDHC_RD_ADSADDR_ADSADDR(base))
+
+/*! @brief Set the ADSADDR field to a new value. */
+#define SDHC_WR_ADSADDR_ADSADDR(base, value) (SDHC_RMW_ADSADDR(base, SDHC_ADSADDR_ADSADDR_MASK, SDHC_ADSADDR_ADSADDR(value)))
+#define SDHC_BWR_ADSADDR_ADSADDR(base, value) (SDHC_WR_ADSADDR_ADSADDR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_VENDOR - Vendor Specific register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_VENDOR - Vendor Specific register (RW)
+ *
+ * Reset value: 0x00000001U
+ *
+ * This register contains the vendor-specific control/status register.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_VENDOR register
+ */
+/*@{*/
+#define SDHC_RD_VENDOR(base)     (SDHC_VENDOR_REG(base))
+#define SDHC_WR_VENDOR(base, value) (SDHC_VENDOR_REG(base) = (value))
+#define SDHC_RMW_VENDOR(base, mask, value) (SDHC_WR_VENDOR(base, (SDHC_RD_VENDOR(base) & ~(mask)) | (value)))
+#define SDHC_SET_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) |  (value)))
+#define SDHC_CLR_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) & ~(value)))
+#define SDHC_TOG_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_VENDOR bitfields
+ */
+
+/*!
+ * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
+ *
+ * Enables the request to external DMA. When the internal DMA (either simple DMA
+ * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
+ * request when the internal buffer is ready. This bit is particularly useful when
+ * transferring data by CPU polling mode, and it is not allowed to send out the
+ * external DMA request. By default, this bit is set.
+ *
+ * Values:
+ * - 0b0 - In any scenario, SDHC does not send out the external DMA request.
+ * - 0b1 - When internal DMA is not active, the external DMA request will be
+ *     sent out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field. */
+#define SDHC_RD_VENDOR_EXTDMAEN(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_EXTDMAEN_MASK) >> SDHC_VENDOR_EXTDMAEN_SHIFT)
+#define SDHC_BRD_VENDOR_EXTDMAEN(base) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXTDMAEN_SHIFT))
+
+/*! @brief Set the EXTDMAEN field to a new value. */
+#define SDHC_WR_VENDOR_EXTDMAEN(base, value) (SDHC_RMW_VENDOR(base, SDHC_VENDOR_EXTDMAEN_MASK, SDHC_VENDOR_EXTDMAEN(value)))
+#define SDHC_BWR_VENDOR_EXTDMAEN(base, value) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXTDMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
+ *
+ * This bit must be set before S/W issues CMD53 multi-block read with exact
+ * block number. This bit must not be set if the CMD53 multi-block read is not exact
+ * block number.
+ *
+ * Values:
+ * - 0b0 - None exact block read.
+ * - 0b1 - Exact block read for SDIO CMD53.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_EXBLKNU field. */
+#define SDHC_RD_VENDOR_EXBLKNU(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_EXBLKNU_MASK) >> SDHC_VENDOR_EXBLKNU_SHIFT)
+#define SDHC_BRD_VENDOR_EXBLKNU(base) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXBLKNU_SHIFT))
+
+/*! @brief Set the EXBLKNU field to a new value. */
+#define SDHC_WR_VENDOR_EXBLKNU(base, value) (SDHC_RMW_VENDOR(base, SDHC_VENDOR_EXBLKNU_MASK, SDHC_VENDOR_EXBLKNU(value)))
+#define SDHC_BWR_VENDOR_EXBLKNU(base, value) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXBLKNU_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
+ *
+ * Internal state value, reflecting the corresponding state value selected by
+ * Debug Select field. This field is read-only and write to this field does not
+ * have effect.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_INTSTVAL field. */
+#define SDHC_RD_VENDOR_INTSTVAL(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_INTSTVAL_MASK) >> SDHC_VENDOR_INTSTVAL_SHIFT)
+#define SDHC_BRD_VENDOR_INTSTVAL(base) (SDHC_RD_VENDOR_INTSTVAL(base))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_MMCBOOT - MMC Boot register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_MMCBOOT - MMC Boot register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the MMC fast boot control register.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_MMCBOOT register
+ */
+/*@{*/
+#define SDHC_RD_MMCBOOT(base)    (SDHC_MMCBOOT_REG(base))
+#define SDHC_WR_MMCBOOT(base, value) (SDHC_MMCBOOT_REG(base) = (value))
+#define SDHC_RMW_MMCBOOT(base, mask, value) (SDHC_WR_MMCBOOT(base, (SDHC_RD_MMCBOOT(base) & ~(mask)) | (value)))
+#define SDHC_SET_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) |  (value)))
+#define SDHC_CLR_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) & ~(value)))
+#define SDHC_TOG_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_MMCBOOT bitfields
+ */
+
+/*!
+ * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
+ *
+ * Values:
+ * - 0b0000 - SDCLK x 2^8
+ * - 0b0001 - SDCLK x 2^9
+ * - 0b0010 - SDCLK x 2^10
+ * - 0b0011 - SDCLK x 2^11
+ * - 0b0100 - SDCLK x 2^12
+ * - 0b0101 - SDCLK x 2^13
+ * - 0b0110 - SDCLK x 2^14
+ * - 0b0111 - SDCLK x 2^15
+ * - 0b1110 - SDCLK x 2^22
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field. */
+#define SDHC_RD_MMCBOOT_DTOCVACK(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_DTOCVACK_MASK) >> SDHC_MMCBOOT_DTOCVACK_SHIFT)
+#define SDHC_BRD_MMCBOOT_DTOCVACK(base) (SDHC_RD_MMCBOOT_DTOCVACK(base))
+
+/*! @brief Set the DTOCVACK field to a new value. */
+#define SDHC_WR_MMCBOOT_DTOCVACK(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_DTOCVACK_MASK, SDHC_MMCBOOT_DTOCVACK(value)))
+#define SDHC_BWR_MMCBOOT_DTOCVACK(base, value) (SDHC_WR_MMCBOOT_DTOCVACK(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
+ *
+ * Values:
+ * - 0b0 - No ack.
+ * - 0b1 - Ack.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field. */
+#define SDHC_RD_MMCBOOT_BOOTACK(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTACK_MASK) >> SDHC_MMCBOOT_BOOTACK_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTACK(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTACK_SHIFT))
+
+/*! @brief Set the BOOTACK field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTACK(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTACK_MASK, SDHC_MMCBOOT_BOOTACK(value)))
+#define SDHC_BWR_MMCBOOT_BOOTACK(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal boot.
+ * - 0b1 - Alternative boot.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field. */
+#define SDHC_RD_MMCBOOT_BOOTMODE(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTMODE_MASK) >> SDHC_MMCBOOT_BOOTMODE_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTMODE(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTMODE_SHIFT))
+
+/*! @brief Set the BOOTMODE field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTMODE(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTMODE_MASK, SDHC_MMCBOOT_BOOTMODE(value)))
+#define SDHC_BWR_MMCBOOT_BOOTMODE(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Fast boot disable.
+ * - 0b1 - Fast boot enable.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field. */
+#define SDHC_RD_MMCBOOT_BOOTEN(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTEN_MASK) >> SDHC_MMCBOOT_BOOTEN_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTEN(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTEN_SHIFT))
+
+/*! @brief Set the BOOTEN field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTEN(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTEN_MASK, SDHC_MMCBOOT_BOOTEN(value)))
+#define SDHC_BWR_MMCBOOT_BOOTEN(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
+ *
+ * When boot, enable auto stop at block gap function. This function will be
+ * triggered, and host will stop at block gap when received card block cnt is equal
+ * to BOOTBLKCNT.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field. */
+#define SDHC_RD_MMCBOOT_AUTOSABGEN(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_AUTOSABGEN_MASK) >> SDHC_MMCBOOT_AUTOSABGEN_SHIFT)
+#define SDHC_BRD_MMCBOOT_AUTOSABGEN(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_AUTOSABGEN_SHIFT))
+
+/*! @brief Set the AUTOSABGEN field to a new value. */
+#define SDHC_WR_MMCBOOT_AUTOSABGEN(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_AUTOSABGEN_MASK, SDHC_MMCBOOT_AUTOSABGEN(value)))
+#define SDHC_BWR_MMCBOOT_AUTOSABGEN(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_AUTOSABGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
+ *
+ * Defines the stop at block gap value of automatic mode. When received card
+ * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field. */
+#define SDHC_RD_MMCBOOT_BOOTBLKCNT(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTBLKCNT_MASK) >> SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTBLKCNT(base) (SDHC_RD_MMCBOOT_BOOTBLKCNT(base))
+
+/*! @brief Set the BOOTBLKCNT field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTBLKCNT(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTBLKCNT_MASK, SDHC_MMCBOOT_BOOTBLKCNT(value)))
+#define SDHC_BWR_MMCBOOT_BOOTBLKCNT(base, value) (SDHC_WR_MMCBOOT_BOOTBLKCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_HOSTVER - Host Controller Version
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_HOSTVER - Host Controller Version (RO)
+ *
+ * Reset value: 0x00001201U
+ *
+ * This register contains the vendor host controller version information. All
+ * bits are read only and will read the same as the power-reset value.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_HOSTVER register
+ */
+/*@{*/
+#define SDHC_RD_HOSTVER(base)    (SDHC_HOSTVER_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_HOSTVER bitfields
+ */
+
+/*!
+ * @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
+ *
+ * These status bits indicate the host controller specification version.
+ *
+ * Values:
+ * - 0b00000001 - SD host specification version 2.0, supports test event
+ *     register and ADMA.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HOSTVER_SVN field. */
+#define SDHC_RD_HOSTVER_SVN(base) ((SDHC_HOSTVER_REG(base) & SDHC_HOSTVER_SVN_MASK) >> SDHC_HOSTVER_SVN_SHIFT)
+#define SDHC_BRD_HOSTVER_SVN(base) (SDHC_RD_HOSTVER_SVN(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
+ *
+ * These status bits are reserved for the vendor version number. The host driver
+ * shall not use this status.
+ *
+ * Values:
+ * - 0b00000000 - Freescale SDHC version 1.0
+ * - 0b00010000 - Freescale SDHC version 2.0
+ * - 0b00010001 - Freescale SDHC version 2.1
+ * - 0b00010010 - Freescale SDHC version 2.2
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HOSTVER_VVN field. */
+#define SDHC_RD_HOSTVER_VVN(base) ((SDHC_HOSTVER_REG(base) & SDHC_HOSTVER_VVN_MASK) >> SDHC_HOSTVER_VVN_SHIFT)
+#define SDHC_BRD_HOSTVER_VVN(base) (SDHC_RD_HOSTVER_VVN(base))
+/*@}*/
+
+/*
+ * MK64F12 SIM
+ *
+ * System Integration Module
+ *
+ * Registers defined in this header file:
+ * - SIM_SOPT1 - System Options Register 1
+ * - SIM_SOPT1CFG - SOPT1 Configuration Register
+ * - SIM_SOPT2 - System Options Register 2
+ * - SIM_SOPT4 - System Options Register 4
+ * - SIM_SOPT5 - System Options Register 5
+ * - SIM_SOPT7 - System Options Register 7
+ * - SIM_SDID - System Device Identification Register
+ * - SIM_SCGC1 - System Clock Gating Control Register 1
+ * - SIM_SCGC2 - System Clock Gating Control Register 2
+ * - SIM_SCGC3 - System Clock Gating Control Register 3
+ * - SIM_SCGC4 - System Clock Gating Control Register 4
+ * - SIM_SCGC5 - System Clock Gating Control Register 5
+ * - SIM_SCGC6 - System Clock Gating Control Register 6
+ * - SIM_SCGC7 - System Clock Gating Control Register 7
+ * - SIM_CLKDIV1 - System Clock Divider Register 1
+ * - SIM_CLKDIV2 - System Clock Divider Register 2
+ * - SIM_FCFG1 - Flash Configuration Register 1
+ * - SIM_FCFG2 - Flash Configuration Register 2
+ * - SIM_UIDH - Unique Identification Register High
+ * - SIM_UIDMH - Unique Identification Register Mid-High
+ * - SIM_UIDML - Unique Identification Register Mid Low
+ * - SIM_UIDL - Unique Identification Register Low
+ */
+
+#define SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */
+#define SIM_IDX (0U) /*!< Instance number for SIM. */
+
+/*******************************************************************************
+ * SIM_SOPT1 - System Options Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1 - System Options Register 1 (RW)
+ *
+ * Reset value: 0x80000000U
+ *
+ * The SOPT1 register is only reset on POR or LVD.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1 register
+ */
+/*@{*/
+#define SIM_RD_SOPT1(base)       (SIM_SOPT1_REG(base))
+#define SIM_WR_SOPT1(base, value) (SIM_SOPT1_REG(base) = (value))
+#define SIM_RMW_SOPT1(base, mask, value) (SIM_WR_SOPT1(base, (SIM_RD_SOPT1(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) |  (value)))
+#define SIM_CLR_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) & ~(value)))
+#define SIM_TOG_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
+ *
+ * This field specifies the amount of system RAM available on the device.
+ *
+ * Values:
+ * - 0b0001 - 8 KB
+ * - 0b0011 - 16 KB
+ * - 0b0100 - 24 KB
+ * - 0b0101 - 32 KB
+ * - 0b0110 - 48 KB
+ * - 0b0111 - 64 KB
+ * - 0b1000 - 96 KB
+ * - 0b1001 - 128 KB
+ * - 0b1011 - 256 KB
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */
+#define SIM_RD_SOPT1_RAMSIZE(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_RAMSIZE_MASK) >> SIM_SOPT1_RAMSIZE_SHIFT)
+#define SIM_BRD_SOPT1_RAMSIZE(base) (SIM_RD_SOPT1_RAMSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
+ *
+ * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
+ * only on POR/LVD.
+ *
+ * Values:
+ * - 0b00 - System oscillator (OSC32KCLK)
+ * - 0b01 - Reserved
+ * - 0b10 - RTC 32.768kHz oscillator
+ * - 0b11 - LPO 1 kHz
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */
+#define SIM_RD_SOPT1_OSC32KSEL(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
+#define SIM_BRD_SOPT1_OSC32KSEL(base) (SIM_RD_SOPT1_OSC32KSEL(base))
+
+/*! @brief Set the OSC32KSEL field to a new value. */
+#define SIM_WR_SOPT1_OSC32KSEL(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_OSC32KSEL_MASK, SIM_SOPT1_OSC32KSEL(value)))
+#define SIM_BWR_SOPT1_OSC32KSEL(base, value) (SIM_WR_SOPT1_OSC32KSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * VLPR and VLPW modes.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator not in standby during VLPR and VLPW modes.
+ * - 0b1 - USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */
+#define SIM_RD_SOPT1_USBVSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBVSTBY_MASK) >> SIM_SOPT1_USBVSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBVSTBY(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT))
+
+/*! @brief Set the USBVSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBVSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBVSTBY_MASK, SIM_SOPT1_USBVSTBY(value)))
+#define SIM_BWR_SOPT1_USBVSTBY(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * Stop, VLPS, LLS and VLLS modes.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ * - 0b1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */
+#define SIM_RD_SOPT1_USBSSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBSSTBY_MASK) >> SIM_SOPT1_USBSSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBSSTBY(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT))
+
+/*! @brief Set the USBSSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBSSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBSSTBY_MASK, SIM_SOPT1_USBSSTBY(value)))
+#define SIM_BWR_SOPT1_USBSSTBY(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
+ *
+ * Controls whether the USB voltage regulator is enabled.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator is disabled.
+ * - 0b1 - USB voltage regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */
+#define SIM_RD_SOPT1_USBREGEN(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBREGEN_MASK) >> SIM_SOPT1_USBREGEN_SHIFT)
+#define SIM_BRD_SOPT1_USBREGEN(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT))
+
+/*! @brief Set the USBREGEN field to a new value. */
+#define SIM_WR_SOPT1_USBREGEN(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBREGEN_MASK, SIM_SOPT1_USBREGEN(value)))
+#define SIM_BWR_SOPT1_USBREGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT1CFG - SOPT1 Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The SOPT1CFG register is reset on System Reset not VLLS.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1CFG register
+ */
+/*@{*/
+#define SIM_RD_SOPT1CFG(base)    (SIM_SOPT1CFG_REG(base))
+#define SIM_WR_SOPT1CFG(base, value) (SIM_SOPT1CFG_REG(base) = (value))
+#define SIM_RMW_SOPT1CFG(base, mask, value) (SIM_WR_SOPT1CFG(base, (SIM_RD_SOPT1CFG(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) |  (value)))
+#define SIM_CLR_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) & ~(value)))
+#define SIM_TOG_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1CFG bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
+ *
+ * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
+ * register bit clears after a write to USBREGEN.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBREGEN cannot be written.
+ * - 0b1 - SOPT1 USBREGEN can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */
+#define SIM_RD_SOPT1CFG_URWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_URWE_MASK) >> SIM_SOPT1CFG_URWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_URWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT))
+
+/*! @brief Set the URWE field to a new value. */
+#define SIM_WR_SOPT1CFG_URWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_URWE_MASK, SIM_SOPT1CFG_URWE(value)))
+#define SIM_BWR_SOPT1CFG_URWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
+ *
+ * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
+ * This register bit clears after a write to USBVSTBY.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBVSTBY cannot be written.
+ * - 0b1 - SOPT1 USBVSTBY can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */
+#define SIM_RD_SOPT1CFG_UVSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_UVSWE_MASK) >> SIM_SOPT1CFG_UVSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_UVSWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT))
+
+/*! @brief Set the UVSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_UVSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_UVSWE_MASK, SIM_SOPT1CFG_UVSWE(value)))
+#define SIM_BWR_SOPT1CFG_UVSWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
+ *
+ * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
+ * This register bit clears after a write to USBSSTBY.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBSSTBY cannot be written.
+ * - 0b1 - SOPT1 USBSSTBY can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */
+#define SIM_RD_SOPT1CFG_USSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_USSWE_MASK) >> SIM_SOPT1CFG_USSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_USSWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT))
+
+/*! @brief Set the USSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_USSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_USSWE_MASK, SIM_SOPT1CFG_USSWE(value)))
+#define SIM_BWR_SOPT1CFG_USSWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT2 - System Options Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT2 - System Options Register 2 (RW)
+ *
+ * Reset value: 0x00001000U
+ *
+ * SOPT2 contains the controls for selecting many of the module clock source
+ * options on this device. See the Clock Distribution chapter for more information
+ * including clocking diagrams and definitions of device clocks.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT2 register
+ */
+/*@{*/
+#define SIM_RD_SOPT2(base)       (SIM_SOPT2_REG(base))
+#define SIM_WR_SOPT2(base, value) (SIM_SOPT2_REG(base) = (value))
+#define SIM_RMW_SOPT2(base, mask, value) (SIM_WR_SOPT2(base, (SIM_RD_SOPT2(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) |  (value)))
+#define SIM_CLR_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) & ~(value)))
+#define SIM_TOG_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
+ *
+ * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
+ * RTC_CLKOUT pin.
+ *
+ * Values:
+ * - 0b0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
+ * - 0b1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */
+#define SIM_RD_SOPT2_RTCCLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RTCCLKOUTSEL_MASK) >> SIM_SOPT2_RTCCLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_RTCCLKOUTSEL(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT))
+
+/*! @brief Set the RTCCLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_RTCCLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RTCCLKOUTSEL_MASK, SIM_SOPT2_RTCCLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_RTCCLKOUTSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
+ *
+ * Selects the clock to output on the CLKOUT pin.
+ *
+ * Values:
+ * - 0b000 - FlexBus CLKOUT
+ * - 0b001 - Reserved
+ * - 0b010 - Flash clock
+ * - 0b011 - LPO clock (1 kHz)
+ * - 0b100 - MCGIRCLK
+ * - 0b101 - RTC 32.768kHz clock
+ * - 0b110 - OSCERCLK0
+ * - 0b111 - IRC 48 MHz clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */
+#define SIM_RD_SOPT2_CLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_CLKOUTSEL_MASK) >> SIM_SOPT2_CLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_CLKOUTSEL(base) (SIM_RD_SOPT2_CLKOUTSEL(base))
+
+/*! @brief Set the CLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_CLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_CLKOUTSEL_MASK, SIM_SOPT2_CLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_CLKOUTSEL(base, value) (SIM_WR_SOPT2_CLKOUTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
+ *
+ * If flash security is enabled, then this field affects what CPU operations can
+ * access off-chip via the FlexBus interface. This field has no effect if flash
+ * security is not enabled.
+ *
+ * Values:
+ * - 0b00 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 0b01 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 0b10 - Off-chip instruction accesses are disallowed. Data accesses are
+ *     allowed.
+ * - 0b11 - Off-chip instruction accesses and data accesses are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_FBSL field. */
+#define SIM_RD_SOPT2_FBSL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_FBSL_MASK) >> SIM_SOPT2_FBSL_SHIFT)
+#define SIM_BRD_SOPT2_FBSL(base) (SIM_RD_SOPT2_FBSL(base))
+
+/*! @brief Set the FBSL field to a new value. */
+#define SIM_WR_SOPT2_FBSL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_FBSL_MASK, SIM_SOPT2_FBSL(value)))
+#define SIM_BWR_SOPT2_FBSL(base, value) (SIM_WR_SOPT2_FBSL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
+ *
+ * Controls the output drive strength of the PTD7 pin by selecting either one or
+ * two pads to drive it.
+ *
+ * Values:
+ * - 0b0 - Single-pad drive strength for PTD7.
+ * - 0b1 - Double pad drive strength for PTD7.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_PTD7PAD field. */
+#define SIM_RD_SOPT2_PTD7PAD(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_PTD7PAD_MASK) >> SIM_SOPT2_PTD7PAD_SHIFT)
+#define SIM_BRD_SOPT2_PTD7PAD(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_PTD7PAD_SHIFT))
+
+/*! @brief Set the PTD7PAD field to a new value. */
+#define SIM_WR_SOPT2_PTD7PAD(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_PTD7PAD_MASK, SIM_SOPT2_PTD7PAD(value)))
+#define SIM_BWR_SOPT2_PTD7PAD(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_PTD7PAD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
+ *
+ * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
+ * clock source.
+ *
+ * Values:
+ * - 0b0 - MCGOUTCLK
+ * - 0b1 - Core/system clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */
+#define SIM_RD_SOPT2_TRACECLKSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TRACECLKSEL_MASK) >> SIM_SOPT2_TRACECLKSEL_SHIFT)
+#define SIM_BRD_SOPT2_TRACECLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_TRACECLKSEL_SHIFT))
+
+/*! @brief Set the TRACECLKSEL field to a new value. */
+#define SIM_WR_SOPT2_TRACECLKSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TRACECLKSEL_MASK, SIM_SOPT2_TRACECLKSEL(value)))
+#define SIM_BWR_SOPT2_TRACECLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_TRACECLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
+ *
+ * Selects the high frequency clock for various peripheral clocking options.
+ *
+ * Values:
+ * - 0b00 - MCGFLLCLK clock
+ * - 0b01 - MCGPLLCLK clock
+ * - 0b10 - Reserved
+ * - 0b11 - IRC48 MHz clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */
+#define SIM_RD_SOPT2_PLLFLLSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
+#define SIM_BRD_SOPT2_PLLFLLSEL(base) (SIM_RD_SOPT2_PLLFLLSEL(base))
+
+/*! @brief Set the PLLFLLSEL field to a new value. */
+#define SIM_WR_SOPT2_PLLFLLSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_PLLFLLSEL_MASK, SIM_SOPT2_PLLFLLSEL(value)))
+#define SIM_BWR_SOPT2_PLLFLLSEL(base, value) (SIM_WR_SOPT2_PLLFLLSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field USBSRC[18] (RW)
+ *
+ * Selects the clock source for the USB 48 MHz clock.
+ *
+ * Values:
+ * - 0b0 - External bypass clock (USB_CLKIN).
+ * - 0b1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
+ *     SIM_CLKDIV2[USBFRAC, USBDIV].
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_USBSRC field. */
+#define SIM_RD_SOPT2_USBSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_USBSRC_MASK) >> SIM_SOPT2_USBSRC_SHIFT)
+#define SIM_BRD_SOPT2_USBSRC(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT))
+
+/*! @brief Set the USBSRC field to a new value. */
+#define SIM_WR_SOPT2_USBSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_USBSRC_MASK, SIM_SOPT2_USBSRC(value)))
+#define SIM_BWR_SOPT2_USBSRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field RMIISRC[19] (RW)
+ *
+ * Selects the clock source for the Ethernet RMII interface
+ *
+ * Values:
+ * - 0b0 - EXTAL clock
+ * - 0b1 - External bypass clock (ENET_1588_CLKIN).
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RMIISRC field. */
+#define SIM_RD_SOPT2_RMIISRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RMIISRC_MASK) >> SIM_SOPT2_RMIISRC_SHIFT)
+#define SIM_BRD_SOPT2_RMIISRC(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RMIISRC_SHIFT))
+
+/*! @brief Set the RMIISRC field to a new value. */
+#define SIM_WR_SOPT2_RMIISRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RMIISRC_MASK, SIM_SOPT2_RMIISRC(value)))
+#define SIM_BWR_SOPT2_RMIISRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RMIISRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
+ *
+ * Selects the clock source for the Ethernet timestamp clock.
+ *
+ * Values:
+ * - 0b00 - Core/system clock.
+ * - 0b01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 0b10 - OSCERCLK clock
+ * - 0b11 - External bypass clock (ENET_1588_CLKIN).
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TIMESRC field. */
+#define SIM_RD_SOPT2_TIMESRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TIMESRC_MASK) >> SIM_SOPT2_TIMESRC_SHIFT)
+#define SIM_BRD_SOPT2_TIMESRC(base) (SIM_RD_SOPT2_TIMESRC(base))
+
+/*! @brief Set the TIMESRC field to a new value. */
+#define SIM_WR_SOPT2_TIMESRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TIMESRC_MASK, SIM_SOPT2_TIMESRC(value)))
+#define SIM_BWR_SOPT2_TIMESRC(base, value) (SIM_WR_SOPT2_TIMESRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
+ *
+ * Selects the clock source for the SDHC clock .
+ *
+ * Values:
+ * - 0b00 - Core/system clock.
+ * - 0b01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 0b10 - OSCERCLK clock
+ * - 0b11 - External bypass clock (SDHC0_CLKIN)
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_SDHCSRC field. */
+#define SIM_RD_SOPT2_SDHCSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_SDHCSRC_MASK) >> SIM_SOPT2_SDHCSRC_SHIFT)
+#define SIM_BRD_SOPT2_SDHCSRC(base) (SIM_RD_SOPT2_SDHCSRC(base))
+
+/*! @brief Set the SDHCSRC field to a new value. */
+#define SIM_WR_SOPT2_SDHCSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_SDHCSRC_MASK, SIM_SOPT2_SDHCSRC(value)))
+#define SIM_BWR_SOPT2_SDHCSRC(base, value) (SIM_WR_SOPT2_SDHCSRC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT4 - System Options Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT4 - System Options Register 4 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT4 register
+ */
+/*@{*/
+#define SIM_RD_SOPT4(base)       (SIM_SOPT4_REG(base))
+#define SIM_WR_SOPT4(base, value) (SIM_SOPT4_REG(base) = (value))
+#define SIM_RMW_SOPT4(base, mask, value) (SIM_WR_SOPT4(base, (SIM_RD_SOPT4(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) |  (value)))
+#define SIM_CLR_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) & ~(value)))
+#define SIM_TOG_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
+ *
+ * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */
+#define SIM_RD_SOPT4_FTM0FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT0_MASK) >> SIM_SOPT4_FTM0FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT0_SHIFT))
+
+/*! @brief Set the FTM0FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT0_MASK, SIM_SOPT4_FTM0FLT0(value)))
+#define SIM_BWR_SOPT4_FTM0FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
+ *
+ * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT1 pin
+ * - 0b1 - CMP1 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */
+#define SIM_RD_SOPT4_FTM0FLT1(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT1_MASK) >> SIM_SOPT4_FTM0FLT1_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT1(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT1_SHIFT))
+
+/*! @brief Set the FTM0FLT1 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT1(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT1_MASK, SIM_SOPT4_FTM0FLT1(value)))
+#define SIM_BWR_SOPT4_FTM0FLT1(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
+ *
+ * Selects the source of FTM0 fault 2. The pin source for fault 2 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT2 pin
+ * - 0b1 - CMP2 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. */
+#define SIM_RD_SOPT4_FTM0FLT2(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT2_MASK) >> SIM_SOPT4_FTM0FLT2_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT2(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT2_SHIFT))
+
+/*! @brief Set the FTM0FLT2 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT2(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT2_MASK, SIM_SOPT4_FTM0FLT2(value)))
+#define SIM_BWR_SOPT4_FTM0FLT2(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
+ *
+ * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM1_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */
+#define SIM_RD_SOPT4_FTM1FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1FLT0_MASK) >> SIM_SOPT4_FTM1FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM1FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1FLT0_SHIFT))
+
+/*! @brief Set the FTM1FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM1FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1FLT0_MASK, SIM_SOPT4_FTM1FLT0(value)))
+#define SIM_BWR_SOPT4_FTM1FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
+ *
+ * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0b0 - FTM2_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */
+#define SIM_RD_SOPT4_FTM2FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2FLT0_MASK) >> SIM_SOPT4_FTM2FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM2FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2FLT0_SHIFT))
+
+/*! @brief Set the FTM2FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM2FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2FLT0_MASK, SIM_SOPT4_FTM2FLT0(value)))
+#define SIM_BWR_SOPT4_FTM2FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
+ *
+ * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0b0 - FTM3_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */
+#define SIM_RD_SOPT4_FTM3FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3FLT0_MASK) >> SIM_SOPT4_FTM3FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM3FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3FLT0_SHIFT))
+
+/*! @brief Set the FTM3FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM3FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3FLT0_MASK, SIM_SOPT4_FTM3FLT0(value)))
+#define SIM_BWR_SOPT4_FTM3FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
+ *
+ * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0b00 - FTM1_CH0 signal
+ * - 0b01 - CMP0 output
+ * - 0b10 - CMP1 output
+ * - 0b11 - USB start of frame pulse
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */
+#define SIM_RD_SOPT4_FTM1CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1CH0SRC_MASK) >> SIM_SOPT4_FTM1CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM1CH0SRC(base) (SIM_RD_SOPT4_FTM1CH0SRC(base))
+
+/*! @brief Set the FTM1CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM1CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1CH0SRC_MASK, SIM_SOPT4_FTM1CH0SRC(value)))
+#define SIM_BWR_SOPT4_FTM1CH0SRC(base, value) (SIM_WR_SOPT4_FTM1CH0SRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
+ *
+ * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0b00 - FTM2_CH0 signal
+ * - 0b01 - CMP0 output
+ * - 0b10 - CMP1 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */
+#define SIM_RD_SOPT4_FTM2CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2CH0SRC_MASK) >> SIM_SOPT4_FTM2CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM2CH0SRC(base) (SIM_RD_SOPT4_FTM2CH0SRC(base))
+
+/*! @brief Set the FTM2CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM2CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2CH0SRC_MASK, SIM_SOPT4_FTM2CH0SRC(value)))
+#define SIM_BWR_SOPT4_FTM2CH0SRC(base, value) (SIM_WR_SOPT4_FTM2CH0SRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM0 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM_CLK0 pin
+ * - 0b1 - FTM_CLK1 pin
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */
+#define SIM_RD_SOPT4_FTM0CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0CLKSEL_MASK) >> SIM_SOPT4_FTM0CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM0CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0CLKSEL_SHIFT))
+
+/*! @brief Set the FTM0CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM0CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0CLKSEL_MASK, SIM_SOPT4_FTM0CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM0CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM1 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM_CLK0 pin
+ * - 0b1 - FTM_CLK1 pin
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */
+#define SIM_RD_SOPT4_FTM1CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1CLKSEL_MASK) >> SIM_SOPT4_FTM1CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM1CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1CLKSEL_SHIFT))
+
+/*! @brief Set the FTM1CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM1CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1CLKSEL_MASK, SIM_SOPT4_FTM1CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM1CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM2 module. The
+ * selected pin must also be configured for the FTM2 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM2 external clock driven by FTM_CLK0 pin.
+ * - 0b1 - FTM2 external clock driven by FTM_CLK1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */
+#define SIM_RD_SOPT4_FTM2CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2CLKSEL_MASK) >> SIM_SOPT4_FTM2CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM2CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2CLKSEL_SHIFT))
+
+/*! @brief Set the FTM2CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM2CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2CLKSEL_MASK, SIM_SOPT4_FTM2CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM2CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM3 module. The
+ * selected pin must also be configured for the FTM3 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM3 external clock driven by FTM_CLK0 pin.
+ * - 0b1 - FTM3 external clock driven by FTM_CLK1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */
+#define SIM_RD_SOPT4_FTM3CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3CLKSEL_MASK) >> SIM_SOPT4_FTM3CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM3CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3CLKSEL_SHIFT))
+
+/*! @brief Set the FTM3CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM3CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3CLKSEL_MASK, SIM_SOPT4_FTM3CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM3CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 0.
+ *
+ * Values:
+ * - 0b0 - HSCMP0 output drives FTM0 hardware trigger 0
+ * - 0b1 - FTM1 channel match drives FTM0 hardware trigger 0
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */
+#define SIM_RD_SOPT4_FTM0TRG0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0TRG0SRC_MASK) >> SIM_SOPT4_FTM0TRG0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM0TRG0SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG0SRC_SHIFT))
+
+/*! @brief Set the FTM0TRG0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM0TRG0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0TRG0SRC_MASK, SIM_SOPT4_FTM0TRG0SRC(value)))
+#define SIM_BWR_SOPT4_FTM0TRG0SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG0SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 1.
+ *
+ * Values:
+ * - 0b0 - PDB output trigger 1 drives FTM0 hardware trigger 1
+ * - 0b1 - FTM2 channel match drives FTM0 hardware trigger 1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */
+#define SIM_RD_SOPT4_FTM0TRG1SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0TRG1SRC_MASK) >> SIM_SOPT4_FTM0TRG1SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM0TRG1SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG1SRC_SHIFT))
+
+/*! @brief Set the FTM0TRG1SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM0TRG1SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0TRG1SRC_MASK, SIM_SOPT4_FTM0TRG1SRC(value)))
+#define SIM_BWR_SOPT4_FTM0TRG1SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG1SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 0.
+ *
+ * Values:
+ * - 0b0 - Reserved
+ * - 0b1 - FTM1 channel match drives FTM3 hardware trigger 0
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */
+#define SIM_RD_SOPT4_FTM3TRG0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3TRG0SRC_MASK) >> SIM_SOPT4_FTM3TRG0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM3TRG0SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG0SRC_SHIFT))
+
+/*! @brief Set the FTM3TRG0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM3TRG0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3TRG0SRC_MASK, SIM_SOPT4_FTM3TRG0SRC(value)))
+#define SIM_BWR_SOPT4_FTM3TRG0SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG0SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 1.
+ *
+ * Values:
+ * - 0b0 - Reserved
+ * - 0b1 - FTM2 channel match drives FTM3 hardware trigger 1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */
+#define SIM_RD_SOPT4_FTM3TRG1SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3TRG1SRC_MASK) >> SIM_SOPT4_FTM3TRG1SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM3TRG1SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG1SRC_SHIFT))
+
+/*! @brief Set the FTM3TRG1SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM3TRG1SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3TRG1SRC_MASK, SIM_SOPT4_FTM3TRG1SRC(value)))
+#define SIM_BWR_SOPT4_FTM3TRG1SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG1SRC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT5 - System Options Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT5 - System Options Register 5 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT5 register
+ */
+/*@{*/
+#define SIM_RD_SOPT5(base)       (SIM_SOPT5_REG(base))
+#define SIM_WR_SOPT5(base, value) (SIM_SOPT5_REG(base) = (value))
+#define SIM_RMW_SOPT5(base, mask, value) (SIM_WR_SOPT5(base, (SIM_RD_SOPT5(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) |  (value)))
+#define SIM_CLR_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) & ~(value)))
+#define SIM_TOG_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
+ *
+ * Selects the source for the UART 0 transmit data.
+ *
+ * Values:
+ * - 0b00 - UART0_TX pin
+ * - 0b01 - UART0_TX pin modulated with FTM1 channel 0 output
+ * - 0b10 - UART0_TX pin modulated with FTM2 channel 0 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */
+#define SIM_RD_SOPT5_UART0TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART0TXSRC_MASK) >> SIM_SOPT5_UART0TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART0TXSRC(base) (SIM_RD_SOPT5_UART0TXSRC(base))
+
+/*! @brief Set the UART0TXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART0TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART0TXSRC_MASK, SIM_SOPT5_UART0TXSRC(value)))
+#define SIM_BWR_SOPT5_UART0TXSRC(base, value) (SIM_WR_SOPT5_UART0TXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
+ *
+ * Selects the source for the UART 0 receive data.
+ *
+ * Values:
+ * - 0b00 - UART0_RX pin
+ * - 0b01 - CMP0
+ * - 0b10 - CMP1
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */
+#define SIM_RD_SOPT5_UART0RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART0RXSRC_MASK) >> SIM_SOPT5_UART0RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART0RXSRC(base) (SIM_RD_SOPT5_UART0RXSRC(base))
+
+/*! @brief Set the UART0RXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART0RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART0RXSRC_MASK, SIM_SOPT5_UART0RXSRC(value)))
+#define SIM_BWR_SOPT5_UART0RXSRC(base, value) (SIM_WR_SOPT5_UART0RXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
+ *
+ * Selects the source for the UART 1 transmit data.
+ *
+ * Values:
+ * - 0b00 - UART1_TX pin
+ * - 0b01 - UART1_TX pin modulated with FTM1 channel 0 output
+ * - 0b10 - UART1_TX pin modulated with FTM2 channel 0 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */
+#define SIM_RD_SOPT5_UART1TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART1TXSRC_MASK) >> SIM_SOPT5_UART1TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART1TXSRC(base) (SIM_RD_SOPT5_UART1TXSRC(base))
+
+/*! @brief Set the UART1TXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART1TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART1TXSRC_MASK, SIM_SOPT5_UART1TXSRC(value)))
+#define SIM_BWR_SOPT5_UART1TXSRC(base, value) (SIM_WR_SOPT5_UART1TXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
+ *
+ * Selects the source for the UART 1 receive data.
+ *
+ * Values:
+ * - 0b00 - UART1_RX pin
+ * - 0b01 - CMP0
+ * - 0b10 - CMP1
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */
+#define SIM_RD_SOPT5_UART1RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART1RXSRC_MASK) >> SIM_SOPT5_UART1RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART1RXSRC(base) (SIM_RD_SOPT5_UART1RXSRC(base))
+
+/*! @brief Set the UART1RXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART1RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART1RXSRC_MASK, SIM_SOPT5_UART1RXSRC(value)))
+#define SIM_BWR_SOPT5_UART1RXSRC(base, value) (SIM_WR_SOPT5_UART1RXSRC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT7 - System Options Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT7 - System Options Register 7 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT7 register
+ */
+/*@{*/
+#define SIM_RD_SOPT7(base)       (SIM_SOPT7_REG(base))
+#define SIM_WR_SOPT7(base, value) (SIM_SOPT7_REG(base) = (value))
+#define SIM_RMW_SOPT7(base, mask, value) (SIM_WR_SOPT7(base, (SIM_RD_SOPT7(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) |  (value)))
+#define SIM_CLR_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) & ~(value)))
+#define SIM_TOG_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
+ *
+ * Selects the ADC0 trigger source when alternative triggers are functional in
+ * stop and VLPS modes. .
+ *
+ * Values:
+ * - 0b0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0b0001 - High speed comparator 0 output
+ * - 0b0010 - High speed comparator 1 output
+ * - 0b0011 - High speed comparator 2 output
+ * - 0b0100 - PIT trigger 0
+ * - 0b0101 - PIT trigger 1
+ * - 0b0110 - PIT trigger 2
+ * - 0b0111 - PIT trigger 3
+ * - 0b1000 - FTM0 trigger
+ * - 0b1001 - FTM1 trigger
+ * - 0b1010 - FTM2 trigger
+ * - 0b1011 - FTM3 trigger
+ * - 0b1100 - RTC alarm
+ * - 0b1101 - RTC seconds
+ * - 0b1110 - Low-power timer (LPTMR) trigger
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */
+#define SIM_RD_SOPT7_ADC0TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0TRGSEL_MASK) >> SIM_SOPT7_ADC0TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0TRGSEL(base) (SIM_RD_SOPT7_ADC0TRGSEL(base))
+
+/*! @brief Set the ADC0TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0TRGSEL_MASK, SIM_SOPT7_ADC0TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0TRGSEL(base, value) (SIM_WR_SOPT7_ADC0TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
+ *
+ * Selects the ADC0 pre-trigger source when alternative triggers are enabled
+ * through ADC0ALTTRGEN.
+ *
+ * Values:
+ * - 0b0 - Pre-trigger A
+ * - 0b1 - Pre-trigger B
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC0PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0PRETRGSEL_MASK) >> SIM_SOPT7_ADC0PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0PRETRGSEL(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT))
+
+/*! @brief Set the ADC0PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0PRETRGSEL_MASK, SIM_SOPT7_ADC0PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0PRETRGSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
+ *
+ * Enable alternative conversion triggers for ADC0.
+ *
+ * Values:
+ * - 0b0 - PDB trigger selected for ADC0.
+ * - 0b1 - Alternate trigger selected for ADC0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC0ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0ALTTRGEN_MASK) >> SIM_SOPT7_ADC0ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC0ALTTRGEN(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT))
+
+/*! @brief Set the ADC0ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC0ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0ALTTRGEN_MASK, SIM_SOPT7_ADC0ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC0ALTTRGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
+ *
+ * Selects the ADC1 trigger source when alternative triggers are functional in
+ * stop and VLPS modes.
+ *
+ * Values:
+ * - 0b0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0b0001 - High speed comparator 0 output
+ * - 0b0010 - High speed comparator 1 output
+ * - 0b0011 - High speed comparator 2 output
+ * - 0b0100 - PIT trigger 0
+ * - 0b0101 - PIT trigger 1
+ * - 0b0110 - PIT trigger 2
+ * - 0b0111 - PIT trigger 3
+ * - 0b1000 - FTM0 trigger
+ * - 0b1001 - FTM1 trigger
+ * - 0b1010 - FTM2 trigger
+ * - 0b1011 - FTM3 trigger
+ * - 0b1100 - RTC alarm
+ * - 0b1101 - RTC seconds
+ * - 0b1110 - Low-power timer (LPTMR) trigger
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */
+#define SIM_RD_SOPT7_ADC1TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1TRGSEL_MASK) >> SIM_SOPT7_ADC1TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC1TRGSEL(base) (SIM_RD_SOPT7_ADC1TRGSEL(base))
+
+/*! @brief Set the ADC1TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC1TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1TRGSEL_MASK, SIM_SOPT7_ADC1TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC1TRGSEL(base, value) (SIM_WR_SOPT7_ADC1TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
+ *
+ * Selects the ADC1 pre-trigger source when alternative triggers are enabled
+ * through ADC1ALTTRGEN.
+ *
+ * Values:
+ * - 0b0 - Pre-trigger A selected for ADC1.
+ * - 0b1 - Pre-trigger B selected for ADC1.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC1PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1PRETRGSEL_MASK) >> SIM_SOPT7_ADC1PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC1PRETRGSEL(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1PRETRGSEL_SHIFT))
+
+/*! @brief Set the ADC1PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC1PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1PRETRGSEL_MASK, SIM_SOPT7_ADC1PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC1PRETRGSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1PRETRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
+ *
+ * Enable alternative conversion triggers for ADC1.
+ *
+ * Values:
+ * - 0b0 - PDB trigger selected for ADC1
+ * - 0b1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC1ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1ALTTRGEN_MASK) >> SIM_SOPT7_ADC1ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC1ALTTRGEN(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1ALTTRGEN_SHIFT))
+
+/*! @brief Set the ADC1ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC1ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1ALTTRGEN_MASK, SIM_SOPT7_ADC1ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC1ALTTRGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1ALTTRGEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SDID - System Device Identification Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SDID - System Device Identification Register (RO)
+ *
+ * Reset value: 0x00000380U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SDID register
+ */
+/*@{*/
+#define SIM_RD_SDID(base)        (SIM_SDID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SDID bitfields
+ */
+
+/*!
+ * @name Register SIM_SDID, field PINID[3:0] (RO)
+ *
+ * Specifies the pincount of the device.
+ *
+ * Values:
+ * - 0b0000 - Reserved
+ * - 0b0001 - Reserved
+ * - 0b0010 - 32-pin
+ * - 0b0011 - Reserved
+ * - 0b0100 - 48-pin
+ * - 0b0101 - 64-pin
+ * - 0b0110 - 80-pin
+ * - 0b0111 - 81-pin or 121-pin
+ * - 0b1000 - 100-pin
+ * - 0b1001 - 121-pin
+ * - 0b1010 - 144-pin
+ * - 0b1011 - Custom pinout (WLCSP)
+ * - 0b1100 - 169-pin
+ * - 0b1101 - Reserved
+ * - 0b1110 - 256-pin
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_PINID field. */
+#define SIM_RD_SDID_PINID(base) ((SIM_SDID_REG(base) & SIM_SDID_PINID_MASK) >> SIM_SDID_PINID_SHIFT)
+#define SIM_BRD_SDID_PINID(base) (SIM_RD_SDID_PINID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMID[6:4] (RO)
+ *
+ * This field is maintained for compatibility only, but has been superceded by
+ * the SERIESID, FAMILYID and SUBFAMID fields in this register.
+ *
+ * Values:
+ * - 0b000 - K1x Family (without tamper)
+ * - 0b001 - K2x Family (without tamper)
+ * - 0b010 - K3x Family or K1x/K6x Family (with tamper)
+ * - 0b011 - K4x Family or K2x Family (with tamper)
+ * - 0b100 - K6x Family (without tamper)
+ * - 0b101 - K7x Family
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMID field. */
+#define SIM_RD_SDID_FAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMID_MASK) >> SIM_SDID_FAMID_SHIFT)
+#define SIM_BRD_SDID_FAMID(base) (SIM_RD_SDID_FAMID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field DIEID[11:7] (RO)
+ *
+ * Specifies the silicon feature set identication number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_DIEID field. */
+#define SIM_RD_SDID_DIEID(base) ((SIM_SDID_REG(base) & SIM_SDID_DIEID_MASK) >> SIM_SDID_DIEID_SHIFT)
+#define SIM_BRD_SDID_DIEID(base) (SIM_RD_SDID_DIEID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field REVID[15:12] (RO)
+ *
+ * Specifies the silicon implementation number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_REVID field. */
+#define SIM_RD_SDID_REVID(base) ((SIM_SDID_REG(base) & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT)
+#define SIM_BRD_SDID_REVID(base) (SIM_RD_SDID_REVID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SERIESID[23:20] (RO)
+ *
+ * Specifies the Kinetis series of the device.
+ *
+ * Values:
+ * - 0b0000 - Kinetis K series
+ * - 0b0001 - Kinetis L series
+ * - 0b0101 - Kinetis W series
+ * - 0b0110 - Kinetis V series
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SERIESID field. */
+#define SIM_RD_SDID_SERIESID(base) ((SIM_SDID_REG(base) & SIM_SDID_SERIESID_MASK) >> SIM_SDID_SERIESID_SHIFT)
+#define SIM_BRD_SDID_SERIESID(base) (SIM_RD_SDID_SERIESID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
+ *
+ * Specifies the Kinetis sub-family of the device.
+ *
+ * Values:
+ * - 0b0000 - Kx0 Subfamily
+ * - 0b0001 - Kx1 Subfamily (tamper detect)
+ * - 0b0010 - Kx2 Subfamily
+ * - 0b0011 - Kx3 Subfamily (tamper detect)
+ * - 0b0100 - Kx4 Subfamily
+ * - 0b0101 - Kx5 Subfamily (tamper detect)
+ * - 0b0110 - Kx6 Subfamily
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SUBFAMID field. */
+#define SIM_RD_SDID_SUBFAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_SUBFAMID_MASK) >> SIM_SDID_SUBFAMID_SHIFT)
+#define SIM_BRD_SDID_SUBFAMID(base) (SIM_RD_SDID_SUBFAMID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
+ *
+ * Specifies the Kinetis family of the device.
+ *
+ * Values:
+ * - 0b0001 - K1x Family
+ * - 0b0010 - K2x Family
+ * - 0b0011 - K3x Family
+ * - 0b0100 - K4x Family
+ * - 0b0110 - K6x Family
+ * - 0b0111 - K7x Family
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMILYID field. */
+#define SIM_RD_SDID_FAMILYID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMILYID_MASK) >> SIM_SDID_FAMILYID_SHIFT)
+#define SIM_BRD_SDID_FAMILYID(base) (SIM_RD_SDID_FAMILYID(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC1 - System Clock Gating Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC1 register
+ */
+/*@{*/
+#define SIM_RD_SCGC1(base)       (SIM_SCGC1_REG(base))
+#define SIM_WR_SCGC1(base, value) (SIM_SCGC1_REG(base) = (value))
+#define SIM_RMW_SCGC1(base, mask, value) (SIM_WR_SCGC1(base, (SIM_RD_SCGC1(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) |  (value)))
+#define SIM_CLR_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) & ~(value)))
+#define SIM_TOG_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) ^  (value)))
+/*@}*/
+
+/* Unified clock gate bit access macros */
+#define SIM_SCGC_BIT_REG(base, index)        (*((volatile uint32_t *)&SIM_SCGC1_REG(base) + (((uint32_t)(index) >> 5) - 0U)))
+#define SIM_SCGC_BIT_SHIFT(index)            ((uint32_t)(index) & ((1U << 5) - 1U))
+#define SIM_RD_SCGC_BIT(base, index)         (SIM_SCGC_BIT_REG((base), (index)) & (1U << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BRD_SCGC_BIT(base, index)        (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_WR_SCGC_BIT(base, index, value)  (SIM_SCGC_BIT_REG((base), (index)) = (SIM_SCGC_BIT_REG((base), (index)) & ~(1U << SIM_SCGC_BIT_SHIFT(index))) | ((uint32_t)(value) << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BWR_SCGC_BIT(base, index, value) (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)) = (uint32_t)(value))
+
+/*
+ * Constants & macros for individual SIM_SCGC1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC1, field I2C2[6] (RW)
+ *
+ * This bit controls the clock gate to the I2C2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_I2C2 field. */
+#define SIM_RD_SCGC1_I2C2(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_I2C2_MASK) >> SIM_SCGC1_I2C2_SHIFT)
+#define SIM_BRD_SCGC1_I2C2(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_I2C2_SHIFT))
+
+/*! @brief Set the I2C2 field to a new value. */
+#define SIM_WR_SCGC1_I2C2(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_I2C2_MASK, SIM_SCGC1_I2C2(value)))
+#define SIM_BWR_SCGC1_I2C2(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_I2C2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC1, field UART4[10] (RW)
+ *
+ * This bit controls the clock gate to the UART4 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_UART4 field. */
+#define SIM_RD_SCGC1_UART4(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_UART4_MASK) >> SIM_SCGC1_UART4_SHIFT)
+#define SIM_BRD_SCGC1_UART4(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART4_SHIFT))
+
+/*! @brief Set the UART4 field to a new value. */
+#define SIM_WR_SCGC1_UART4(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_UART4_MASK, SIM_SCGC1_UART4(value)))
+#define SIM_BWR_SCGC1_UART4(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC1, field UART5[11] (RW)
+ *
+ * This bit controls the clock gate to the UART5 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_UART5 field. */
+#define SIM_RD_SCGC1_UART5(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_UART5_MASK) >> SIM_SCGC1_UART5_SHIFT)
+#define SIM_BRD_SCGC1_UART5(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART5_SHIFT))
+
+/*! @brief Set the UART5 field to a new value. */
+#define SIM_WR_SCGC1_UART5(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_UART5_MASK, SIM_SCGC1_UART5(value)))
+#define SIM_BWR_SCGC1_UART5(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART5_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC2 - System Clock Gating Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
+ * AIPS1, define the clock gate control bits in the SCGC2. When accessing through
+ * AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC2 register
+ */
+/*@{*/
+#define SIM_RD_SCGC2(base)       (SIM_SCGC2_REG(base))
+#define SIM_WR_SCGC2(base, value) (SIM_SCGC2_REG(base) = (value))
+#define SIM_RMW_SCGC2(base, mask, value) (SIM_WR_SCGC2(base, (SIM_RD_SCGC2(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) |  (value)))
+#define SIM_CLR_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) & ~(value)))
+#define SIM_TOG_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC2, field ENET[0] (RW)
+ *
+ * This bit controls the clock gate to the ENET module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_ENET field. */
+#define SIM_RD_SCGC2_ENET(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_ENET_MASK) >> SIM_SCGC2_ENET_SHIFT)
+#define SIM_BRD_SCGC2_ENET(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_ENET_SHIFT))
+
+/*! @brief Set the ENET field to a new value. */
+#define SIM_WR_SCGC2_ENET(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_ENET_MASK, SIM_SCGC2_ENET(value)))
+#define SIM_BWR_SCGC2_ENET(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_ENET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC2, field DAC0[12] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_DAC0 field. */
+#define SIM_RD_SCGC2_DAC0(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_DAC0_MASK) >> SIM_SCGC2_DAC0_SHIFT)
+#define SIM_BRD_SCGC2_DAC0(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC0_SHIFT))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC2_DAC0(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_DAC0_MASK, SIM_SCGC2_DAC0(value)))
+#define SIM_BWR_SCGC2_DAC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC2, field DAC1[13] (RW)
+ *
+ * This bit controls the clock gate to the DAC1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_DAC1 field. */
+#define SIM_RD_SCGC2_DAC1(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_DAC1_MASK) >> SIM_SCGC2_DAC1_SHIFT)
+#define SIM_BRD_SCGC2_DAC1(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC1_SHIFT))
+
+/*! @brief Set the DAC1 field to a new value. */
+#define SIM_WR_SCGC2_DAC1(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_DAC1_MASK, SIM_SCGC2_DAC1(value)))
+#define SIM_BWR_SCGC2_DAC1(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC3 - System Clock Gating Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
+ * through AIPS1, define the clock gate control bits in the SCGC3. When accessing
+ * through AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC3 register
+ */
+/*@{*/
+#define SIM_RD_SCGC3(base)       (SIM_SCGC3_REG(base))
+#define SIM_WR_SCGC3(base, value) (SIM_SCGC3_REG(base) = (value))
+#define SIM_RMW_SCGC3(base, mask, value) (SIM_WR_SCGC3(base, (SIM_RD_SCGC3(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) |  (value)))
+#define SIM_CLR_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) & ~(value)))
+#define SIM_TOG_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC3 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC3, field RNGA[0] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_RNGA field. */
+#define SIM_RD_SCGC3_RNGA(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_RNGA_MASK) >> SIM_SCGC3_RNGA_SHIFT)
+#define SIM_BRD_SCGC3_RNGA(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_RNGA_SHIFT))
+
+/*! @brief Set the RNGA field to a new value. */
+#define SIM_WR_SCGC3_RNGA(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_RNGA_MASK, SIM_SCGC3_RNGA(value)))
+#define SIM_BWR_SCGC3_RNGA(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_RNGA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field SPI2[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_SPI2 field. */
+#define SIM_RD_SCGC3_SPI2(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_SPI2_MASK) >> SIM_SCGC3_SPI2_SHIFT)
+#define SIM_BRD_SCGC3_SPI2(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SPI2_SHIFT))
+
+/*! @brief Set the SPI2 field to a new value. */
+#define SIM_WR_SCGC3_SPI2(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_SPI2_MASK, SIM_SCGC3_SPI2(value)))
+#define SIM_BWR_SCGC3_SPI2(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SPI2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field SDHC[17] (RW)
+ *
+ * This bit controls the clock gate to the SDHC module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_SDHC field. */
+#define SIM_RD_SCGC3_SDHC(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_SDHC_MASK) >> SIM_SCGC3_SDHC_SHIFT)
+#define SIM_BRD_SCGC3_SDHC(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SDHC_SHIFT))
+
+/*! @brief Set the SDHC field to a new value. */
+#define SIM_WR_SCGC3_SDHC(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_SDHC_MASK, SIM_SCGC3_SDHC(value)))
+#define SIM_BWR_SCGC3_SDHC(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SDHC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field FTM2[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_FTM2 field. */
+#define SIM_RD_SCGC3_FTM2(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_FTM2_MASK) >> SIM_SCGC3_FTM2_SHIFT)
+#define SIM_BRD_SCGC3_FTM2(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM2_SHIFT))
+
+/*! @brief Set the FTM2 field to a new value. */
+#define SIM_WR_SCGC3_FTM2(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_FTM2_MASK, SIM_SCGC3_FTM2(value)))
+#define SIM_BWR_SCGC3_FTM2(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field FTM3[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM3 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_FTM3 field. */
+#define SIM_RD_SCGC3_FTM3(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_FTM3_MASK) >> SIM_SCGC3_FTM3_SHIFT)
+#define SIM_BRD_SCGC3_FTM3(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM3_SHIFT))
+
+/*! @brief Set the FTM3 field to a new value. */
+#define SIM_WR_SCGC3_FTM3(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_FTM3_MASK, SIM_SCGC3_FTM3(value)))
+#define SIM_BWR_SCGC3_FTM3(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field ADC1[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_ADC1 field. */
+#define SIM_RD_SCGC3_ADC1(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_ADC1_MASK) >> SIM_SCGC3_ADC1_SHIFT)
+#define SIM_BRD_SCGC3_ADC1(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_ADC1_SHIFT))
+
+/*! @brief Set the ADC1 field to a new value. */
+#define SIM_WR_SCGC3_ADC1(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_ADC1_MASK, SIM_SCGC3_ADC1(value)))
+#define SIM_BWR_SCGC3_ADC1(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_ADC1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC4 - System Clock Gating Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
+ *
+ * Reset value: 0xF0100030U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC4 register
+ */
+/*@{*/
+#define SIM_RD_SCGC4(base)       (SIM_SCGC4_REG(base))
+#define SIM_WR_SCGC4(base, value) (SIM_SCGC4_REG(base) = (value))
+#define SIM_RMW_SCGC4(base, mask, value) (SIM_WR_SCGC4(base, (SIM_RD_SCGC4(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) |  (value)))
+#define SIM_CLR_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) & ~(value)))
+#define SIM_TOG_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC4, field EWM[1] (RW)
+ *
+ * This bit controls the clock gate to the EWM module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_EWM field. */
+#define SIM_RD_SCGC4_EWM(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_EWM_MASK) >> SIM_SCGC4_EWM_SHIFT)
+#define SIM_BRD_SCGC4_EWM(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_EWM_SHIFT))
+
+/*! @brief Set the EWM field to a new value. */
+#define SIM_WR_SCGC4_EWM(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_EWM_MASK, SIM_SCGC4_EWM(value)))
+#define SIM_BWR_SCGC4_EWM(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_EWM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMT[2] (RW)
+ *
+ * This bit controls the clock gate to the CMT module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMT field. */
+#define SIM_RD_SCGC4_CMT(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMT_MASK) >> SIM_SCGC4_CMT_SHIFT)
+#define SIM_BRD_SCGC4_CMT(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT))
+
+/*! @brief Set the CMT field to a new value. */
+#define SIM_WR_SCGC4_CMT(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMT_MASK, SIM_SCGC4_CMT(value)))
+#define SIM_BWR_SCGC4_CMT(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C0[6] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C0 field. */
+#define SIM_RD_SCGC4_I2C0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C0_MASK) >> SIM_SCGC4_I2C0_SHIFT)
+#define SIM_BRD_SCGC4_I2C0(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT))
+
+/*! @brief Set the I2C0 field to a new value. */
+#define SIM_WR_SCGC4_I2C0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C0_MASK, SIM_SCGC4_I2C0(value)))
+#define SIM_BWR_SCGC4_I2C0(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C1[7] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C1 field. */
+#define SIM_RD_SCGC4_I2C1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C1_MASK) >> SIM_SCGC4_I2C1_SHIFT)
+#define SIM_BRD_SCGC4_I2C1(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT))
+
+/*! @brief Set the I2C1 field to a new value. */
+#define SIM_WR_SCGC4_I2C1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C1_MASK, SIM_SCGC4_I2C1(value)))
+#define SIM_BWR_SCGC4_I2C1(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART0[10] (RW)
+ *
+ * This bit controls the clock gate to the UART0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART0 field. */
+#define SIM_RD_SCGC4_UART0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT)
+#define SIM_BRD_SCGC4_UART0(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART0_SHIFT))
+
+/*! @brief Set the UART0 field to a new value. */
+#define SIM_WR_SCGC4_UART0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART0_MASK, SIM_SCGC4_UART0(value)))
+#define SIM_BWR_SCGC4_UART0(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART1[11] (RW)
+ *
+ * This bit controls the clock gate to the UART1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART1 field. */
+#define SIM_RD_SCGC4_UART1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT)
+#define SIM_BRD_SCGC4_UART1(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART1_SHIFT))
+
+/*! @brief Set the UART1 field to a new value. */
+#define SIM_WR_SCGC4_UART1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART1_MASK, SIM_SCGC4_UART1(value)))
+#define SIM_BWR_SCGC4_UART1(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART2[12] (RW)
+ *
+ * This bit controls the clock gate to the UART2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART2 field. */
+#define SIM_RD_SCGC4_UART2(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT)
+#define SIM_BRD_SCGC4_UART2(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT))
+
+/*! @brief Set the UART2 field to a new value. */
+#define SIM_WR_SCGC4_UART2(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART2_MASK, SIM_SCGC4_UART2(value)))
+#define SIM_BWR_SCGC4_UART2(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART3[13] (RW)
+ *
+ * This bit controls the clock gate to the UART3 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART3 field. */
+#define SIM_RD_SCGC4_UART3(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART3_MASK) >> SIM_SCGC4_UART3_SHIFT)
+#define SIM_BRD_SCGC4_UART3(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART3_SHIFT))
+
+/*! @brief Set the UART3 field to a new value. */
+#define SIM_WR_SCGC4_UART3(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART3_MASK, SIM_SCGC4_UART3(value)))
+#define SIM_BWR_SCGC4_UART3(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field USBOTG[18] (RW)
+ *
+ * This bit controls the clock gate to the USB module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_USBOTG field. */
+#define SIM_RD_SCGC4_USBOTG(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_USBOTG_MASK) >> SIM_SCGC4_USBOTG_SHIFT)
+#define SIM_BRD_SCGC4_USBOTG(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBOTG_SHIFT))
+
+/*! @brief Set the USBOTG field to a new value. */
+#define SIM_WR_SCGC4_USBOTG(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_USBOTG_MASK, SIM_SCGC4_USBOTG(value)))
+#define SIM_BWR_SCGC4_USBOTG(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBOTG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMP[19] (RW)
+ *
+ * This bit controls the clock gate to the comparator module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMP field. */
+#define SIM_RD_SCGC4_CMP(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMP_MASK) >> SIM_SCGC4_CMP_SHIFT)
+#define SIM_BRD_SCGC4_CMP(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT))
+
+/*! @brief Set the CMP field to a new value. */
+#define SIM_WR_SCGC4_CMP(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMP_MASK, SIM_SCGC4_CMP(value)))
+#define SIM_BWR_SCGC4_CMP(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field VREF[20] (RW)
+ *
+ * This bit controls the clock gate to the VREF module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_VREF field. */
+#define SIM_RD_SCGC4_VREF(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_VREF_MASK) >> SIM_SCGC4_VREF_SHIFT)
+#define SIM_BRD_SCGC4_VREF(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT))
+
+/*! @brief Set the VREF field to a new value. */
+#define SIM_WR_SCGC4_VREF(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_VREF_MASK, SIM_SCGC4_VREF(value)))
+#define SIM_BWR_SCGC4_VREF(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC5 - System Clock Gating Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
+ *
+ * Reset value: 0x00040182U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC5 register
+ */
+/*@{*/
+#define SIM_RD_SCGC5(base)       (SIM_SCGC5_REG(base))
+#define SIM_WR_SCGC5(base, value) (SIM_SCGC5_REG(base) = (value))
+#define SIM_RMW_SCGC5(base, mask, value) (SIM_WR_SCGC5(base, (SIM_RD_SCGC5(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) |  (value)))
+#define SIM_CLR_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) & ~(value)))
+#define SIM_TOG_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC5, field LPTMR[0] (RW)
+ *
+ * This bit controls software access to the Low Power Timer module.
+ *
+ * Values:
+ * - 0b0 - Access disabled
+ * - 0b1 - Access enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_LPTMR field. */
+#define SIM_RD_SCGC5_LPTMR(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPTMR_MASK) >> SIM_SCGC5_LPTMR_SHIFT)
+#define SIM_BRD_SCGC5_LPTMR(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT))
+
+/*! @brief Set the LPTMR field to a new value. */
+#define SIM_WR_SCGC5_LPTMR(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPTMR_MASK, SIM_SCGC5_LPTMR(value)))
+#define SIM_BWR_SCGC5_LPTMR(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTA[9] (RW)
+ *
+ * This bit controls the clock gate to the Port A module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTA field. */
+#define SIM_RD_SCGC5_PORTA(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTA_MASK) >> SIM_SCGC5_PORTA_SHIFT)
+#define SIM_BRD_SCGC5_PORTA(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT))
+
+/*! @brief Set the PORTA field to a new value. */
+#define SIM_WR_SCGC5_PORTA(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTA_MASK, SIM_SCGC5_PORTA(value)))
+#define SIM_BWR_SCGC5_PORTA(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTB[10] (RW)
+ *
+ * This bit controls the clock gate to the Port B module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTB field. */
+#define SIM_RD_SCGC5_PORTB(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTB_MASK) >> SIM_SCGC5_PORTB_SHIFT)
+#define SIM_BRD_SCGC5_PORTB(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT))
+
+/*! @brief Set the PORTB field to a new value. */
+#define SIM_WR_SCGC5_PORTB(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTB_MASK, SIM_SCGC5_PORTB(value)))
+#define SIM_BWR_SCGC5_PORTB(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTC[11] (RW)
+ *
+ * This bit controls the clock gate to the Port C module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTC field. */
+#define SIM_RD_SCGC5_PORTC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTC_MASK) >> SIM_SCGC5_PORTC_SHIFT)
+#define SIM_BRD_SCGC5_PORTC(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT))
+
+/*! @brief Set the PORTC field to a new value. */
+#define SIM_WR_SCGC5_PORTC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTC_MASK, SIM_SCGC5_PORTC(value)))
+#define SIM_BWR_SCGC5_PORTC(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTD[12] (RW)
+ *
+ * This bit controls the clock gate to the Port D module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTD field. */
+#define SIM_RD_SCGC5_PORTD(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTD_MASK) >> SIM_SCGC5_PORTD_SHIFT)
+#define SIM_BRD_SCGC5_PORTD(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT))
+
+/*! @brief Set the PORTD field to a new value. */
+#define SIM_WR_SCGC5_PORTD(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTD_MASK, SIM_SCGC5_PORTD(value)))
+#define SIM_BWR_SCGC5_PORTD(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTE[13] (RW)
+ *
+ * This bit controls the clock gate to the Port E module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTE field. */
+#define SIM_RD_SCGC5_PORTE(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTE_MASK) >> SIM_SCGC5_PORTE_SHIFT)
+#define SIM_BRD_SCGC5_PORTE(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT))
+
+/*! @brief Set the PORTE field to a new value. */
+#define SIM_WR_SCGC5_PORTE(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTE_MASK, SIM_SCGC5_PORTE(value)))
+#define SIM_BWR_SCGC5_PORTE(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC6 - System Clock Gating Control Register 6
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
+ *
+ * Reset value: 0x40000001U
+ *
+ * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
+ * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
+ * When accessing through AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC6 register
+ */
+/*@{*/
+#define SIM_RD_SCGC6(base)       (SIM_SCGC6_REG(base))
+#define SIM_WR_SCGC6(base, value) (SIM_SCGC6_REG(base) = (value))
+#define SIM_RMW_SCGC6(base, mask, value) (SIM_WR_SCGC6(base, (SIM_RD_SCGC6(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) |  (value)))
+#define SIM_CLR_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) & ~(value)))
+#define SIM_TOG_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC6 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC6, field FTF[0] (RW)
+ *
+ * This bit controls the clock gate to the flash memory. Flash reads are still
+ * supported while the flash memory is clock gated, but entry into low power modes
+ * is blocked.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTF field. */
+#define SIM_RD_SCGC6_FTF(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTF_MASK) >> SIM_SCGC6_FTF_SHIFT)
+#define SIM_BRD_SCGC6_FTF(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT))
+
+/*! @brief Set the FTF field to a new value. */
+#define SIM_WR_SCGC6_FTF(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTF_MASK, SIM_SCGC6_FTF(value)))
+#define SIM_BWR_SCGC6_FTF(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA Mux module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */
+#define SIM_RD_SCGC6_DMAMUX(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DMAMUX_MASK) >> SIM_SCGC6_DMAMUX_SHIFT)
+#define SIM_BRD_SCGC6_DMAMUX(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT))
+
+/*! @brief Set the DMAMUX field to a new value. */
+#define SIM_WR_SCGC6_DMAMUX(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DMAMUX_MASK, SIM_SCGC6_DMAMUX(value)))
+#define SIM_BWR_SCGC6_DMAMUX(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
+ *
+ * This bit controls the clock gate to the FlexCAN0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. */
+#define SIM_RD_SCGC6_FLEXCAN0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FLEXCAN0_MASK) >> SIM_SCGC6_FLEXCAN0_SHIFT)
+#define SIM_BRD_SCGC6_FLEXCAN0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FLEXCAN0_SHIFT))
+
+/*! @brief Set the FLEXCAN0 field to a new value. */
+#define SIM_WR_SCGC6_FLEXCAN0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FLEXCAN0_MASK, SIM_SCGC6_FLEXCAN0(value)))
+#define SIM_BWR_SCGC6_FLEXCAN0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FLEXCAN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RNGA[9] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RNGA field. */
+#define SIM_RD_SCGC6_RNGA(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RNGA_MASK) >> SIM_SCGC6_RNGA_SHIFT)
+#define SIM_BRD_SCGC6_RNGA(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RNGA_SHIFT))
+
+/*! @brief Set the RNGA field to a new value. */
+#define SIM_WR_SCGC6_RNGA(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RNGA_MASK, SIM_SCGC6_RNGA(value)))
+#define SIM_BWR_SCGC6_RNGA(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RNGA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field SPI0[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_SPI0 field. */
+#define SIM_RD_SCGC6_SPI0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI0_MASK) >> SIM_SCGC6_SPI0_SHIFT)
+#define SIM_BRD_SCGC6_SPI0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT))
+
+/*! @brief Set the SPI0 field to a new value. */
+#define SIM_WR_SCGC6_SPI0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI0_MASK, SIM_SCGC6_SPI0(value)))
+#define SIM_BWR_SCGC6_SPI0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field SPI1[13] (RW)
+ *
+ * This bit controls the clock gate to the SPI1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_SPI1 field. */
+#define SIM_RD_SCGC6_SPI1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI1_MASK) >> SIM_SCGC6_SPI1_SHIFT)
+#define SIM_BRD_SCGC6_SPI1(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT))
+
+/*! @brief Set the SPI1 field to a new value. */
+#define SIM_WR_SCGC6_SPI1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI1_MASK, SIM_SCGC6_SPI1(value)))
+#define SIM_BWR_SCGC6_SPI1(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field I2S[15] (RW)
+ *
+ * This bit controls the clock gate to the I 2 S module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_I2S field. */
+#define SIM_RD_SCGC6_I2S(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_I2S_MASK) >> SIM_SCGC6_I2S_SHIFT)
+#define SIM_BRD_SCGC6_I2S(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT))
+
+/*! @brief Set the I2S field to a new value. */
+#define SIM_WR_SCGC6_I2S(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_I2S_MASK, SIM_SCGC6_I2S(value)))
+#define SIM_BWR_SCGC6_I2S(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field CRC[18] (RW)
+ *
+ * This bit controls the clock gate to the CRC module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_CRC field. */
+#define SIM_RD_SCGC6_CRC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_CRC_MASK) >> SIM_SCGC6_CRC_SHIFT)
+#define SIM_BRD_SCGC6_CRC(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_CRC_SHIFT))
+
+/*! @brief Set the CRC field to a new value. */
+#define SIM_WR_SCGC6_CRC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_CRC_MASK, SIM_SCGC6_CRC(value)))
+#define SIM_BWR_SCGC6_CRC(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_CRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field USBDCD[21] (RW)
+ *
+ * This bit controls the clock gate to the USB DCD module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_USBDCD field. */
+#define SIM_RD_SCGC6_USBDCD(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_USBDCD_MASK) >> SIM_SCGC6_USBDCD_SHIFT)
+#define SIM_BRD_SCGC6_USBDCD(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_USBDCD_SHIFT))
+
+/*! @brief Set the USBDCD field to a new value. */
+#define SIM_WR_SCGC6_USBDCD(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_USBDCD_MASK, SIM_SCGC6_USBDCD(value)))
+#define SIM_BWR_SCGC6_USBDCD(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_USBDCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PDB[22] (RW)
+ *
+ * This bit controls the clock gate to the PDB module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PDB field. */
+#define SIM_RD_SCGC6_PDB(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PDB_MASK) >> SIM_SCGC6_PDB_SHIFT)
+#define SIM_BRD_SCGC6_PDB(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PDB_SHIFT))
+
+/*! @brief Set the PDB field to a new value. */
+#define SIM_WR_SCGC6_PDB(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PDB_MASK, SIM_SCGC6_PDB(value)))
+#define SIM_BWR_SCGC6_PDB(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PDB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PIT[23] (RW)
+ *
+ * This bit controls the clock gate to the PIT module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PIT field. */
+#define SIM_RD_SCGC6_PIT(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PIT_MASK) >> SIM_SCGC6_PIT_SHIFT)
+#define SIM_BRD_SCGC6_PIT(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT))
+
+/*! @brief Set the PIT field to a new value. */
+#define SIM_WR_SCGC6_PIT(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PIT_MASK, SIM_SCGC6_PIT(value)))
+#define SIM_BWR_SCGC6_PIT(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM0[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM0 field. */
+#define SIM_RD_SCGC6_FTM0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM0_MASK) >> SIM_SCGC6_FTM0_SHIFT)
+#define SIM_BRD_SCGC6_FTM0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM0_SHIFT))
+
+/*! @brief Set the FTM0 field to a new value. */
+#define SIM_WR_SCGC6_FTM0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM0_MASK, SIM_SCGC6_FTM0(value)))
+#define SIM_BWR_SCGC6_FTM0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM1[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM1 field. */
+#define SIM_RD_SCGC6_FTM1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM1_MASK) >> SIM_SCGC6_FTM1_SHIFT)
+#define SIM_BRD_SCGC6_FTM1(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM1_SHIFT))
+
+/*! @brief Set the FTM1 field to a new value. */
+#define SIM_WR_SCGC6_FTM1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM1_MASK, SIM_SCGC6_FTM1(value)))
+#define SIM_BWR_SCGC6_FTM1(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM2[26] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM2 field. */
+#define SIM_RD_SCGC6_FTM2(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM2_MASK) >> SIM_SCGC6_FTM2_SHIFT)
+#define SIM_BRD_SCGC6_FTM2(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM2_SHIFT))
+
+/*! @brief Set the FTM2 field to a new value. */
+#define SIM_WR_SCGC6_FTM2(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM2_MASK, SIM_SCGC6_FTM2(value)))
+#define SIM_BWR_SCGC6_FTM2(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field ADC0[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_ADC0 field. */
+#define SIM_RD_SCGC6_ADC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_ADC0_MASK) >> SIM_SCGC6_ADC0_SHIFT)
+#define SIM_BRD_SCGC6_ADC0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT))
+
+/*! @brief Set the ADC0 field to a new value. */
+#define SIM_WR_SCGC6_ADC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_ADC0_MASK, SIM_SCGC6_ADC0(value)))
+#define SIM_BWR_SCGC6_ADC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RTC[29] (RW)
+ *
+ * This bit controls software access and interrupts to the RTC module.
+ *
+ * Values:
+ * - 0b0 - Access and interrupts disabled
+ * - 0b1 - Access and interrupts enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RTC field. */
+#define SIM_RD_SCGC6_RTC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RTC_MASK) >> SIM_SCGC6_RTC_SHIFT)
+#define SIM_BRD_SCGC6_RTC(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT))
+
+/*! @brief Set the RTC field to a new value. */
+#define SIM_WR_SCGC6_RTC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RTC_MASK, SIM_SCGC6_RTC(value)))
+#define SIM_BWR_SCGC6_RTC(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DAC0[31] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DAC0 field. */
+#define SIM_RD_SCGC6_DAC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DAC0_MASK) >> SIM_SCGC6_DAC0_SHIFT)
+#define SIM_BRD_SCGC6_DAC0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC6_DAC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DAC0_MASK, SIM_SCGC6_DAC0(value)))
+#define SIM_BWR_SCGC6_DAC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC7 - System Clock Gating Control Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
+ *
+ * Reset value: 0x00000006U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC7 register
+ */
+/*@{*/
+#define SIM_RD_SCGC7(base)       (SIM_SCGC7_REG(base))
+#define SIM_WR_SCGC7(base, value) (SIM_SCGC7_REG(base) = (value))
+#define SIM_RMW_SCGC7(base, mask, value) (SIM_WR_SCGC7(base, (SIM_RD_SCGC7(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) |  (value)))
+#define SIM_CLR_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) & ~(value)))
+#define SIM_TOG_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
+ *
+ * This bit controls the clock gate to the FlexBus module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */
+#define SIM_RD_SCGC7_FLEXBUS(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_FLEXBUS_MASK) >> SIM_SCGC7_FLEXBUS_SHIFT)
+#define SIM_BRD_SCGC7_FLEXBUS(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_FLEXBUS_SHIFT))
+
+/*! @brief Set the FLEXBUS field to a new value. */
+#define SIM_WR_SCGC7_FLEXBUS(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_FLEXBUS_MASK, SIM_SCGC7_FLEXBUS(value)))
+#define SIM_BWR_SCGC7_FLEXBUS(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_FLEXBUS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC7, field DMA[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_DMA field. */
+#define SIM_RD_SCGC7_DMA(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_DMA_MASK) >> SIM_SCGC7_DMA_SHIFT)
+#define SIM_BRD_SCGC7_DMA(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define SIM_WR_SCGC7_DMA(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_DMA_MASK, SIM_SCGC7_DMA(value)))
+#define SIM_BWR_SCGC7_DMA(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC7, field MPU[2] (RW)
+ *
+ * This bit controls the clock gate to the MPU module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_MPU field. */
+#define SIM_RD_SCGC7_MPU(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_MPU_MASK) >> SIM_SCGC7_MPU_SHIFT)
+#define SIM_BRD_SCGC7_MPU(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_MPU_SHIFT))
+
+/*! @brief Set the MPU field to a new value. */
+#define SIM_WR_SCGC7_MPU(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_MPU_MASK, SIM_SCGC7_MPU(value)))
+#define SIM_BWR_SCGC7_MPU(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_MPU_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV1 - System Clock Divider Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * When updating CLKDIV1, update all fields using the one write command.
+ * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
+ * write to be ignored. The maximum divide ratio that can be programmed between
+ * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
+ * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
+ * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
+ * mode.
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV1 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV1(base)     (SIM_CLKDIV1_REG(base))
+#define SIM_WR_CLKDIV1(base, value) (SIM_CLKDIV1_REG(base) = (value))
+#define SIM_RMW_CLKDIV1(base, mask, value) (SIM_WR_CLKDIV1(base, (SIM_RD_CLKDIV1(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) |  (value)))
+#define SIM_CLR_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) & ~(value)))
+#define SIM_TOG_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV1 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
+ *
+ * This field sets the divide value for the flash clock from MCGOUTCLK. At the
+ * end of reset, it is loaded with either 0001 or 1111 depending on
+ * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
+ * frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */
+#define SIM_RD_CLKDIV1_OUTDIV4(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV4(base) (SIM_RD_CLKDIV1_OUTDIV4(base))
+
+/*! @brief Set the OUTDIV4 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV4(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV4_MASK, SIM_CLKDIV1_OUTDIV4(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV4(base, value) (SIM_WR_CLKDIV1_OUTDIV4(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
+ *
+ * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
+ * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
+ * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
+ * divide of the system clock frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */
+#define SIM_RD_CLKDIV1_OUTDIV3(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV3(base) (SIM_RD_CLKDIV1_OUTDIV3(base))
+
+/*! @brief Set the OUTDIV3 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV3(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV3_MASK, SIM_CLKDIV1_OUTDIV3(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV3(base, value) (SIM_WR_CLKDIV1_OUTDIV3(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
+ *
+ * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
+ * of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
+ * frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */
+#define SIM_RD_CLKDIV1_OUTDIV2(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV2(base) (SIM_RD_CLKDIV1_OUTDIV2(base))
+
+/*! @brief Set the OUTDIV2 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV2(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV2_MASK, SIM_CLKDIV1_OUTDIV2(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV2(base, value) (SIM_WR_CLKDIV1_OUTDIV2(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
+ *
+ * This field sets the divide value for the core/system clock from MCGOUTCLK. At
+ * the end of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT].
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */
+#define SIM_RD_CLKDIV1_OUTDIV1(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV1(base) (SIM_RD_CLKDIV1_OUTDIV1(base))
+
+/*! @brief Set the OUTDIV1 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV1(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV1_MASK, SIM_CLKDIV1_OUTDIV1(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV1(base, value) (SIM_WR_CLKDIV1_OUTDIV1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV2 - System Clock Divider Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV2 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV2(base)     (SIM_CLKDIV2_REG(base))
+#define SIM_WR_CLKDIV2(base, value) (SIM_CLKDIV2_REG(base) = (value))
+#define SIM_RMW_CLKDIV2(base, mask, value) (SIM_WR_CLKDIV2(base, (SIM_RD_CLKDIV2(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) |  (value)))
+#define SIM_CLR_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) & ~(value)))
+#define SIM_TOG_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV2 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
+ *
+ * This field sets the fraction multiply value for the fractional clock divider
+ * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
+ * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. */
+#define SIM_RD_CLKDIV2_USBFRAC(base) ((SIM_CLKDIV2_REG(base) & SIM_CLKDIV2_USBFRAC_MASK) >> SIM_CLKDIV2_USBFRAC_SHIFT)
+#define SIM_BRD_CLKDIV2_USBFRAC(base) (BITBAND_ACCESS32(&SIM_CLKDIV2_REG(base), SIM_CLKDIV2_USBFRAC_SHIFT))
+
+/*! @brief Set the USBFRAC field to a new value. */
+#define SIM_WR_CLKDIV2_USBFRAC(base, value) (SIM_RMW_CLKDIV2(base, SIM_CLKDIV2_USBFRAC_MASK, SIM_CLKDIV2_USBFRAC(value)))
+#define SIM_BWR_CLKDIV2_USBFRAC(base, value) (BITBAND_ACCESS32(&SIM_CLKDIV2_REG(base), SIM_CLKDIV2_USBFRAC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
+ *
+ * This field sets the divide value for the fractional clock divider when the
+ * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
+ * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV2_USBDIV field. */
+#define SIM_RD_CLKDIV2_USBDIV(base) ((SIM_CLKDIV2_REG(base) & SIM_CLKDIV2_USBDIV_MASK) >> SIM_CLKDIV2_USBDIV_SHIFT)
+#define SIM_BRD_CLKDIV2_USBDIV(base) (SIM_RD_CLKDIV2_USBDIV(base))
+
+/*! @brief Set the USBDIV field to a new value. */
+#define SIM_WR_CLKDIV2_USBDIV(base, value) (SIM_RMW_CLKDIV2(base, SIM_CLKDIV2_USBDIV_MASK, SIM_CLKDIV2_USBDIV(value)))
+#define SIM_BWR_CLKDIV2_USBDIV(base, value) (SIM_WR_CLKDIV2_USBDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG1 - Flash Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG1 - Flash Configuration Register 1 (RW)
+ *
+ * Reset value: 0xFF0F0F00U
+ *
+ * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
+ * user programming in user IFR via the PGMPART flash command. For devices with
+ * program flash only:
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG1 register
+ */
+/*@{*/
+#define SIM_RD_FCFG1(base)       (SIM_FCFG1_REG(base))
+#define SIM_WR_FCFG1(base, value) (SIM_FCFG1_REG(base) = (value))
+#define SIM_RMW_FCFG1(base, mask, value) (SIM_WR_FCFG1(base, (SIM_RD_FCFG1(base) & ~(mask)) | (value)))
+#define SIM_SET_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) |  (value)))
+#define SIM_CLR_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) & ~(value)))
+#define SIM_TOG_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG1 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
+ *
+ * Flash accesses are disabled (and generate a bus error) and the Flash memory
+ * is placed in a low power state. This bit should not be changed during VLP
+ * modes. Relocate the interrupt vectors out of Flash memory before disabling the
+ * Flash.
+ *
+ * Values:
+ * - 0b0 - Flash is enabled
+ * - 0b1 - Flash is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */
+#define SIM_RD_FCFG1_FLASHDIS(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDIS_MASK) >> SIM_FCFG1_FLASHDIS_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDIS(base) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT))
+
+/*! @brief Set the FLASHDIS field to a new value. */
+#define SIM_WR_FCFG1_FLASHDIS(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDIS_MASK, SIM_FCFG1_FLASHDIS(value)))
+#define SIM_BWR_FCFG1_FLASHDIS(base, value) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
+ *
+ * When set, Flash memory is disabled for the duration of Wait mode. An attempt
+ * by the DMA or other bus master to access the Flash when the Flash is disabled
+ * will result in a bus error. This bit should be clear during VLP modes. The
+ * Flash will be automatically enabled again at the end of Wait mode so interrupt
+ * vectors do not need to be relocated out of Flash memory. The wakeup time from
+ * Wait mode is extended when this bit is set.
+ *
+ * Values:
+ * - 0b0 - Flash remains enabled during Wait mode
+ * - 0b1 - Flash is disabled for the duration of Wait mode
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */
+#define SIM_RD_FCFG1_FLASHDOZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDOZE_MASK) >> SIM_FCFG1_FLASHDOZE_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDOZE(base) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT))
+
+/*! @brief Set the FLASHDOZE field to a new value. */
+#define SIM_WR_FCFG1_FLASHDOZE(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDOZE_MASK, SIM_FCFG1_FLASHDOZE(value)))
+#define SIM_BWR_FCFG1_FLASHDOZE(base, value) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
+ *
+ * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
+ * description in FTFE chapter. For devices without FlexNVM: Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_DEPART field. */
+#define SIM_RD_FCFG1_DEPART(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT)
+#define SIM_BRD_FCFG1_DEPART(base) (SIM_RD_FCFG1_DEPART(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
+ *
+ * EEPROM data size .
+ *
+ * Values:
+ * - 0b0000 - 16 KB
+ * - 0b0001 - 8 KB
+ * - 0b0010 - 4 KB
+ * - 0b0011 - 2 KB
+ * - 0b0100 - 1 KB
+ * - 0b0101 - 512 Bytes
+ * - 0b0110 - 256 Bytes
+ * - 0b0111 - 128 Bytes
+ * - 0b1000 - 64 Bytes
+ * - 0b1001 - 32 Bytes
+ * - 0b1111 - 0 Bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_EESIZE field. */
+#define SIM_RD_FCFG1_EESIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_EESIZE_MASK) >> SIM_FCFG1_EESIZE_SHIFT)
+#define SIM_BRD_FCFG1_EESIZE(base) (SIM_RD_FCFG1_EESIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
+ *
+ * This field specifies the amount of program flash memory available on the
+ * device . Undefined values are reserved.
+ *
+ * Values:
+ * - 0b0011 - 32 KB of program flash memory
+ * - 0b0101 - 64 KB of program flash memory
+ * - 0b0111 - 128 KB of program flash memory
+ * - 0b1001 - 256 KB of program flash memory
+ * - 0b1011 - 512 KB of program flash memory
+ * - 0b1101 - 1024 KB of program flash memory
+ * - 0b1111 - 1024 KB of program flash memory
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */
+#define SIM_RD_FCFG1_PFSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT)
+#define SIM_BRD_FCFG1_PFSIZE(base) (SIM_RD_FCFG1_PFSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
+ *
+ * This field specifies the amount of FlexNVM memory available on the device .
+ * Undefined values are reserved.
+ *
+ * Values:
+ * - 0b0000 - 0 KB of FlexNVM
+ * - 0b0011 - 32 KB of FlexNVM
+ * - 0b0101 - 64 KB of FlexNVM
+ * - 0b0111 - 128 KB of FlexNVM
+ * - 0b1001 - 256 KB of FlexNVM
+ * - 0b1011 - 512 KB of FlexNVM
+ * - 0b1111 - 512 KB of FlexNVM
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_NVMSIZE field. */
+#define SIM_RD_FCFG1_NVMSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_NVMSIZE_MASK) >> SIM_FCFG1_NVMSIZE_SHIFT)
+#define SIM_BRD_FCFG1_NVMSIZE(base) (SIM_RD_FCFG1_NVMSIZE(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG2 - Flash Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG2 - Flash Configuration Register 2 (RO)
+ *
+ * Reset value: 0x7F7F0000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG2 register
+ */
+/*@{*/
+#define SIM_RD_FCFG2(base)       (SIM_FCFG2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG2 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
+ *
+ * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
+ * the FlexNVM base address indicates the first invalid address of the FlexNVM
+ * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
+ * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
+ * for a device with 256 KB FlexNVM. For devices with program flash only: This
+ * field equals zero if there is only one program flash block, otherwise it equals
+ * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
+ * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
+ * the MAXADDR1 value for a device with 512 KB program flash memory across two
+ * flash blocks and no FlexNVM.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */
+#define SIM_RD_FCFG2_MAXADDR1(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR1_MASK) >> SIM_FCFG2_MAXADDR1_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR1(base) (SIM_RD_FCFG2_MAXADDR1(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field PFLSH[23] (RO)
+ *
+ * For devices with FlexNVM, this bit is always clear. For devices without
+ * FlexNVM, this bit is always set.
+ *
+ * Values:
+ * - 0b0 - Device supports FlexNVM
+ * - 0b1 - Program Flash only, device does not support FlexNVM
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_PFLSH field. */
+#define SIM_RD_FCFG2_PFLSH(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_PFLSH_MASK) >> SIM_FCFG2_PFLSH_SHIFT)
+#define SIM_BRD_FCFG2_PFLSH(base) (BITBAND_ACCESS32(&SIM_FCFG2_REG(base), SIM_FCFG2_PFLSH_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
+ *
+ * This field concatenated with 13 trailing zeros indicates the first invalid
+ * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
+ * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
+ * value for a device with 256 KB program flash in flash block 0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */
+#define SIM_RD_FCFG2_MAXADDR0(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR0_MASK) >> SIM_FCFG2_MAXADDR0_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR0(base) (SIM_RD_FCFG2_MAXADDR0(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDH - Unique Identification Register High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDH - Unique Identification Register High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDH register
+ */
+/*@{*/
+#define SIM_RD_UIDH(base)        (SIM_UIDH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDMH - Unique Identification Register Mid-High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDMH - Unique Identification Register Mid-High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDMH register
+ */
+/*@{*/
+#define SIM_RD_UIDMH(base)       (SIM_UIDMH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDML - Unique Identification Register Mid Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDML - Unique Identification Register Mid Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDML register
+ */
+/*@{*/
+#define SIM_RD_UIDML(base)       (SIM_UIDML_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDL - Unique Identification Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDL - Unique Identification Register Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDL register
+ */
+/*@{*/
+#define SIM_RD_UIDL(base)        (SIM_UIDL_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 SMC
+ *
+ * System Mode Controller
+ *
+ * Registers defined in this header file:
+ * - SMC_PMPROT - Power Mode Protection register
+ * - SMC_PMCTRL - Power Mode Control register
+ * - SMC_VLLSCTRL - VLLS Control register
+ * - SMC_PMSTAT - Power Mode Status register
+ */
+
+#define SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
+#define SMC_IDX (0U) /*!< Instance number for SMC. */
+
+/*******************************************************************************
+ * SMC_PMPROT - Power Mode Protection register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMPROT - Power Mode Protection register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides protection for entry into any low-power run or stop
+ * mode. The enabling of the low-power run or stop mode occurs by configuring the
+ * Power Mode Control register (PMCTRL). The PMPROT register can be written only
+ * once after any system reset. If the MCU is configured for a disallowed or
+ * reserved power mode, the MCU remains in its current power mode. For example, if the
+ * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
+ * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
+ * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
+ * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
+ * that do not trigger Chip Reset not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMPROT register
+ */
+/*@{*/
+#define SMC_RD_PMPROT(base)      (SMC_PMPROT_REG(base))
+#define SMC_WR_PMPROT(base, value) (SMC_PMPROT_REG(base) = (value))
+#define SMC_RMW_PMPROT(base, mask, value) (SMC_WR_PMPROT(base, (SMC_RD_PMPROT(base) & ~(mask)) | (value)))
+#define SMC_SET_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) |  (value)))
+#define SMC_CLR_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) & ~(value)))
+#define SMC_TOG_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMPROT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMPROT, field AVLLS[1] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write once
+ * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
+ *
+ * Values:
+ * - 0b0 - Any VLLSx mode is not allowed
+ * - 0b1 - Any VLLSx mode is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
+#define SMC_RD_PMPROT_AVLLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLLS_MASK) >> SMC_PMPROT_AVLLS_SHIFT)
+#define SMC_BRD_PMPROT_AVLLS(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT))
+
+/*! @brief Set the AVLLS field to a new value. */
+#define SMC_WR_PMPROT_AVLLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLLS_MASK, SMC_PMPROT_AVLLS(value)))
+#define SMC_BWR_PMPROT_AVLLS(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field ALLS[3] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any low-leakage stop mode (LLS).
+ *
+ * Values:
+ * - 0b0 - LLS is not allowed
+ * - 0b1 - LLS is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_ALLS field. */
+#define SMC_RD_PMPROT_ALLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_ALLS_MASK) >> SMC_PMPROT_ALLS_SHIFT)
+#define SMC_BRD_PMPROT_ALLS(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT))
+
+/*! @brief Set the ALLS field to a new value. */
+#define SMC_WR_PMPROT_ALLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_ALLS_MASK, SMC_PMPROT_ALLS(value)))
+#define SMC_BWR_PMPROT_ALLS(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field AVLP[5] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
+ *
+ * Values:
+ * - 0b0 - VLPR, VLPW, and VLPS are not allowed.
+ * - 0b1 - VLPR, VLPW, and VLPS are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLP field. */
+#define SMC_RD_PMPROT_AVLP(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLP_MASK) >> SMC_PMPROT_AVLP_SHIFT)
+#define SMC_BRD_PMPROT_AVLP(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT))
+
+/*! @brief Set the AVLP field to a new value. */
+#define SMC_WR_PMPROT_AVLP(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLP_MASK, SMC_PMPROT_AVLP(value)))
+#define SMC_BWR_PMPROT_AVLP(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMCTRL - Power Mode Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMCTRL - Power Mode Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The PMCTRL register controls entry into low-power Run and Stop modes,
+ * provided that the selected power mode is allowed via an appropriate setting of the
+ * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
+ * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
+ * that do not trigger Chip POR not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMCTRL register
+ */
+/*@{*/
+#define SMC_RD_PMCTRL(base)      (SMC_PMCTRL_REG(base))
+#define SMC_WR_PMCTRL(base, value) (SMC_PMCTRL_REG(base) = (value))
+#define SMC_RMW_PMCTRL(base, mask, value) (SMC_WR_PMCTRL(base, (SMC_RD_PMCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) |  (value)))
+#define SMC_CLR_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) & ~(value)))
+#define SMC_TOG_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
+ *
+ * When written, controls entry into the selected stop mode when Sleep-Now or
+ * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
+ * blocked if the protection level has not been enabled using the PMPROT register.
+ * After any system reset, this field is cleared by hardware on any successful write
+ * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
+ * register is used to further select the particular VLLS submode which will be
+ * entered.
+ *
+ * Values:
+ * - 0b000 - Normal Stop (STOP)
+ * - 0b001 - Reserved
+ * - 0b010 - Very-Low-Power Stop (VLPS)
+ * - 0b011 - Low-Leakage Stop (LLS)
+ * - 0b100 - Very-Low-Leakage Stop (VLLSx)
+ * - 0b101 - Reserved
+ * - 0b110 - Reseved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
+#define SMC_RD_PMCTRL_STOPM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPM_MASK) >> SMC_PMCTRL_STOPM_SHIFT)
+#define SMC_BRD_PMCTRL_STOPM(base) (SMC_RD_PMCTRL_STOPM(base))
+
+/*! @brief Set the STOPM field to a new value. */
+#define SMC_WR_PMCTRL_STOPM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_STOPM_MASK, SMC_PMCTRL_STOPM(value)))
+#define SMC_BWR_PMCTRL_STOPM(base, value) (SMC_WR_PMCTRL_STOPM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPA[3] (RO)
+ *
+ * When set, this read-only status bit indicates an interrupt or reset occured
+ * during the previous stop mode entry sequence, preventing the system from
+ * entering that mode. This field is cleared by hardware at the beginning of any stop
+ * mode entry sequence and is set if the sequence was aborted.
+ *
+ * Values:
+ * - 0b0 - The previous stop mode entry was successsful.
+ * - 0b1 - The previous stop mode entry was aborted.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
+#define SMC_RD_PMCTRL_STOPA(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPA_MASK) >> SMC_PMCTRL_STOPA_SHIFT)
+#define SMC_BRD_PMCTRL_STOPA(base) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_STOPA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
+ *
+ * When written, causes entry into the selected run mode. Writes to this field
+ * are blocked if the protection level has not been enabled using the PMPROT
+ * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
+ * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
+ *
+ * Values:
+ * - 0b00 - Normal Run mode (RUN)
+ * - 0b01 - Reserved
+ * - 0b10 - Very-Low-Power Run mode (VLPR)
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
+#define SMC_RD_PMCTRL_RUNM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_RUNM_MASK) >> SMC_PMCTRL_RUNM_SHIFT)
+#define SMC_BRD_PMCTRL_RUNM(base) (SMC_RD_PMCTRL_RUNM(base))
+
+/*! @brief Set the RUNM field to a new value. */
+#define SMC_WR_PMCTRL_RUNM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_RUNM_MASK, SMC_PMCTRL_RUNM(value)))
+#define SMC_BWR_PMCTRL_RUNM(base, value) (SMC_WR_PMCTRL_RUNM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
+ *
+ * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
+ * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
+ * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
+ * the LPWUI setting. LPWUI must be modified only while the system is in RUN
+ * mode, that is, when PMSTAT=RUN.
+ *
+ * Values:
+ * - 0b0 - The system remains in a VLP mode on an interrupt
+ * - 0b1 - The system exits to Normal RUN mode on an interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_LPWUI field. */
+#define SMC_RD_PMCTRL_LPWUI(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_LPWUI_MASK) >> SMC_PMCTRL_LPWUI_SHIFT)
+#define SMC_BRD_PMCTRL_LPWUI(base) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_LPWUI_SHIFT))
+
+/*! @brief Set the LPWUI field to a new value. */
+#define SMC_WR_PMCTRL_LPWUI(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_LPWUI_MASK, SMC_PMCTRL_LPWUI(value)))
+#define SMC_BWR_PMCTRL_LPWUI(base, value) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_LPWUI_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_VLLSCTRL - VLLS Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_VLLSCTRL - VLLS Control register (RW)
+ *
+ * Reset value: 0x03U
+ *
+ * The VLLSCTRL register controls features related to VLLS modes. This register
+ * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
+ * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
+ * the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_VLLSCTRL register
+ */
+/*@{*/
+#define SMC_RD_VLLSCTRL(base)    (SMC_VLLSCTRL_REG(base))
+#define SMC_WR_VLLSCTRL(base, value) (SMC_VLLSCTRL_REG(base) = (value))
+#define SMC_RMW_VLLSCTRL(base, mask, value) (SMC_WR_VLLSCTRL(base, (SMC_RD_VLLSCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) |  (value)))
+#define SMC_CLR_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) & ~(value)))
+#define SMC_TOG_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_VLLSCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
+ *
+ * Controls which VLLS sub-mode to enter if STOPM=VLLS.
+ *
+ * Values:
+ * - 0b000 - VLLS0
+ * - 0b001 - VLLS1
+ * - 0b010 - VLLS2
+ * - 0b011 - VLLS3
+ * - 0b100 - Reserved
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_VLLSCTRL_VLLSM field. */
+#define SMC_RD_VLLSCTRL_VLLSM(base) ((SMC_VLLSCTRL_REG(base) & SMC_VLLSCTRL_VLLSM_MASK) >> SMC_VLLSCTRL_VLLSM_SHIFT)
+#define SMC_BRD_VLLSCTRL_VLLSM(base) (SMC_RD_VLLSCTRL_VLLSM(base))
+
+/*! @brief Set the VLLSM field to a new value. */
+#define SMC_WR_VLLSCTRL_VLLSM(base, value) (SMC_RMW_VLLSCTRL(base, SMC_VLLSCTRL_VLLSM_MASK, SMC_VLLSCTRL_VLLSM(value)))
+#define SMC_BWR_VLLSCTRL_VLLSM(base, value) (SMC_WR_VLLSCTRL_VLLSM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
+ *
+ * Controls whether the POR detect circuit (for brown-out detection) is enabled
+ * in VLLS0 mode.
+ *
+ * Values:
+ * - 0b0 - POR detect circuit is enabled in VLLS0.
+ * - 0b1 - POR detect circuit is disabled in VLLS0.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_VLLSCTRL_PORPO field. */
+#define SMC_RD_VLLSCTRL_PORPO(base) ((SMC_VLLSCTRL_REG(base) & SMC_VLLSCTRL_PORPO_MASK) >> SMC_VLLSCTRL_PORPO_SHIFT)
+#define SMC_BRD_VLLSCTRL_PORPO(base) (BITBAND_ACCESS8(&SMC_VLLSCTRL_REG(base), SMC_VLLSCTRL_PORPO_SHIFT))
+
+/*! @brief Set the PORPO field to a new value. */
+#define SMC_WR_VLLSCTRL_PORPO(base, value) (SMC_RMW_VLLSCTRL(base, SMC_VLLSCTRL_PORPO_MASK, SMC_VLLSCTRL_PORPO(value)))
+#define SMC_BWR_VLLSCTRL_PORPO(base, value) (BITBAND_ACCESS8(&SMC_VLLSCTRL_REG(base), SMC_VLLSCTRL_PORPO_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMSTAT - Power Mode Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMSTAT - Power Mode Status register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * PMSTAT is a read-only, one-hot register which indicates the current power
+ * mode of the system. This register is reset on Chip POR not VLLS and by reset
+ * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
+ * trigger Chip POR not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMSTAT register
+ */
+/*@{*/
+#define SMC_RD_PMSTAT(base)      (SMC_PMSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMSTAT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
+ *
+ * When debug is enabled, the PMSTAT will not update to STOP or VLPS
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */
+#define SMC_RD_PMSTAT_PMSTAT(base) ((SMC_PMSTAT_REG(base) & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT)
+#define SMC_BRD_PMSTAT_PMSTAT(base) (SMC_RD_PMSTAT_PMSTAT(base))
+/*@}*/
+
+/*
+ * MK64F12 SPI
+ *
+ * Serial Peripheral Interface
+ *
+ * Registers defined in this header file:
+ * - SPI_MCR - Module Configuration Register
+ * - SPI_TCR - Transfer Count Register
+ * - SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
+ * - SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ * - SPI_SR - Status Register
+ * - SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ * - SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ * - SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ * - SPI_POPR - POP RX FIFO Register
+ * - SPI_TXFR0 - Transmit FIFO Registers
+ * - SPI_TXFR1 - Transmit FIFO Registers
+ * - SPI_TXFR2 - Transmit FIFO Registers
+ * - SPI_TXFR3 - Transmit FIFO Registers
+ * - SPI_RXFR0 - Receive FIFO Registers
+ * - SPI_RXFR1 - Receive FIFO Registers
+ * - SPI_RXFR2 - Receive FIFO Registers
+ * - SPI_RXFR3 - Receive FIFO Registers
+ */
+
+#define SPI_INSTANCE_COUNT (3U) /*!< Number of instances of the SPI module. */
+#define SPI0_IDX (0U) /*!< Instance number for SPI0. */
+#define SPI1_IDX (1U) /*!< Instance number for SPI1. */
+#define SPI2_IDX (2U) /*!< Instance number for SPI2. */
+
+/*******************************************************************************
+ * SPI_MCR - Module Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0x00004001U
+ *
+ * Contains bits to configure various attributes associated with the module
+ * operations. The HALT and MDIS bits can be changed at any time, but the effect
+ * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
+ * MCR can be changed, while the module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_MCR register
+ */
+/*@{*/
+#define SPI_RD_MCR(base)         (SPI_MCR_REG(base))
+#define SPI_WR_MCR(base, value)  (SPI_MCR_REG(base) = (value))
+#define SPI_RMW_MCR(base, mask, value) (SPI_WR_MCR(base, (SPI_RD_MCR(base) & ~(mask)) | (value)))
+#define SPI_SET_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) |  (value)))
+#define SPI_CLR_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) & ~(value)))
+#define SPI_TOG_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_MCR bitfields
+ */
+
+/*!
+ * @name Register SPI_MCR, field HALT[0] (RW)
+ *
+ * The HALT bit starts and stops frame transfers. See Start and Stop of Module
+ * transfers
+ *
+ * Values:
+ * - 0b0 - Start transfers.
+ * - 0b1 - Stop transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_HALT field. */
+#define SPI_RD_MCR_HALT(base) ((SPI_MCR_REG(base) & SPI_MCR_HALT_MASK) >> SPI_MCR_HALT_SHIFT)
+#define SPI_BRD_MCR_HALT(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define SPI_WR_MCR_HALT(base, value) (SPI_RMW_MCR(base, SPI_MCR_HALT_MASK, SPI_MCR_HALT(value)))
+#define SPI_BWR_MCR_HALT(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
+ *
+ * Controls when the module master samples SIN in Modified Transfer Format. This
+ * field is valid only when CPHA bit in CTARn[CPHA] is 0.
+ *
+ * Values:
+ * - 0b00 - 0 protocol clock cycles between SCK edge and SIN sample
+ * - 0b01 - 1 protocol clock cycle between SCK edge and SIN sample
+ * - 0b10 - 2 protocol clock cycles between SCK edge and SIN sample
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_SMPL_PT field. */
+#define SPI_RD_MCR_SMPL_PT(base) ((SPI_MCR_REG(base) & SPI_MCR_SMPL_PT_MASK) >> SPI_MCR_SMPL_PT_SHIFT)
+#define SPI_BRD_MCR_SMPL_PT(base) (SPI_RD_MCR_SMPL_PT(base))
+
+/*! @brief Set the SMPL_PT field to a new value. */
+#define SPI_WR_MCR_SMPL_PT(base, value) (SPI_RMW_MCR(base, SPI_MCR_SMPL_PT_MASK, SPI_MCR_SMPL_PT(value)))
+#define SPI_BWR_MCR_SMPL_PT(base, value) (SPI_WR_MCR_SMPL_PT(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
+ *
+ * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
+ * CLR_RXF bit is always read as zero.
+ *
+ * Values:
+ * - 0b0 - Do not clear the RX FIFO counter.
+ * - 0b1 - Clear the RX FIFO counter.
+ */
+/*@{*/
+/*! @brief Set the CLR_RXF field to a new value. */
+#define SPI_WR_MCR_CLR_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_RXF_MASK, SPI_MCR_CLR_RXF(value)))
+#define SPI_BWR_MCR_CLR_RXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CLR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
+ *
+ * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
+ * CLR_TXF bit is always read as zero.
+ *
+ * Values:
+ * - 0b0 - Do not clear the TX FIFO counter.
+ * - 0b1 - Clear the TX FIFO counter.
+ */
+/*@{*/
+/*! @brief Set the CLR_TXF field to a new value. */
+#define SPI_WR_MCR_CLR_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_TXF_MASK, SPI_MCR_CLR_TXF(value)))
+#define SPI_BWR_MCR_CLR_TXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CLR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DIS_RXF[12] (RW)
+ *
+ * When the RX FIFO is disabled, the receive part of the module operates as a
+ * simplified double-buffered SPI. This bit can only be written when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0b0 - RX FIFO is enabled.
+ * - 0b1 - RX FIFO is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DIS_RXF field. */
+#define SPI_RD_MCR_DIS_RXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_RXF_MASK) >> SPI_MCR_DIS_RXF_SHIFT)
+#define SPI_BRD_MCR_DIS_RXF(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT))
+
+/*! @brief Set the DIS_RXF field to a new value. */
+#define SPI_WR_MCR_DIS_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_RXF_MASK, SPI_MCR_DIS_RXF(value)))
+#define SPI_BWR_MCR_DIS_RXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DIS_TXF[13] (RW)
+ *
+ * When the TX FIFO is disabled, the transmit part of the module operates as a
+ * simplified double-buffered SPI. This bit can be written only when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0b0 - TX FIFO is enabled.
+ * - 0b1 - TX FIFO is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DIS_TXF field. */
+#define SPI_RD_MCR_DIS_TXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_TXF_MASK) >> SPI_MCR_DIS_TXF_SHIFT)
+#define SPI_BRD_MCR_DIS_TXF(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT))
+
+/*! @brief Set the DIS_TXF field to a new value. */
+#define SPI_WR_MCR_DIS_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_TXF_MASK, SPI_MCR_DIS_TXF(value)))
+#define SPI_BWR_MCR_DIS_TXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MDIS[14] (RW)
+ *
+ * Allows the clock to be stopped to the non-memory mapped logic in the module
+ * effectively putting it in a software-controlled power-saving state. The reset
+ * value of the MDIS bit is parameterized, with a default reset value of 0. When
+ * the module is used in Slave Mode, we recommend leaving this bit 0, because a
+ * slave doesn't have control over master transactions.
+ *
+ * Values:
+ * - 0b0 - Enables the module clocks.
+ * - 0b1 - Allows external logic to disable the module clocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MDIS field. */
+#define SPI_RD_MCR_MDIS(base) ((SPI_MCR_REG(base) & SPI_MCR_MDIS_MASK) >> SPI_MCR_MDIS_SHIFT)
+#define SPI_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define SPI_WR_MCR_MDIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_MDIS_MASK, SPI_MCR_MDIS(value)))
+#define SPI_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DOZE[15] (RW)
+ *
+ * Provides support for an externally controlled Doze mode power-saving
+ * mechanism.
+ *
+ * Values:
+ * - 0b0 - Doze mode has no effect on the module.
+ * - 0b1 - Doze mode disables the module.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DOZE field. */
+#define SPI_RD_MCR_DOZE(base) ((SPI_MCR_REG(base) & SPI_MCR_DOZE_MASK) >> SPI_MCR_DOZE_SHIFT)
+#define SPI_BRD_MCR_DOZE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT))
+
+/*! @brief Set the DOZE field to a new value. */
+#define SPI_WR_MCR_DOZE(base, value) (SPI_RMW_MCR(base, SPI_MCR_DOZE_MASK, SPI_MCR_DOZE(value)))
+#define SPI_BWR_MCR_DOZE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field PCSIS[21:16] (RW)
+ *
+ * Determines the inactive state of PCSx.
+ *
+ * Values:
+ * - 0b000000 - The inactive state of PCSx is low.
+ * - 0b000001 - The inactive state of PCSx is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_PCSIS field. */
+#define SPI_RD_MCR_PCSIS(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSIS_MASK) >> SPI_MCR_PCSIS_SHIFT)
+#define SPI_BRD_MCR_PCSIS(base) (SPI_RD_MCR_PCSIS(base))
+
+/*! @brief Set the PCSIS field to a new value. */
+#define SPI_WR_MCR_PCSIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSIS_MASK, SPI_MCR_PCSIS(value)))
+#define SPI_BWR_MCR_PCSIS(base, value) (SPI_WR_MCR_PCSIS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field ROOE[24] (RW)
+ *
+ * In the RX FIFO overflow condition, configures the module to ignore the
+ * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
+ * is received, the data from the transfer, generating the overflow, is ignored
+ * or shifted into the shift register.
+ *
+ * Values:
+ * - 0b0 - Incoming data is ignored.
+ * - 0b1 - Incoming data is shifted into the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_ROOE field. */
+#define SPI_RD_MCR_ROOE(base) ((SPI_MCR_REG(base) & SPI_MCR_ROOE_MASK) >> SPI_MCR_ROOE_SHIFT)
+#define SPI_BRD_MCR_ROOE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT))
+
+/*! @brief Set the ROOE field to a new value. */
+#define SPI_WR_MCR_ROOE(base, value) (SPI_RMW_MCR(base, SPI_MCR_ROOE_MASK, SPI_MCR_ROOE(value)))
+#define SPI_BWR_MCR_ROOE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field PCSSE[25] (RW)
+ *
+ * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
+ *
+ * Values:
+ * - 0b0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
+ * - 0b1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_PCSSE field. */
+#define SPI_RD_MCR_PCSSE(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSSE_MASK) >> SPI_MCR_PCSSE_SHIFT)
+#define SPI_BRD_MCR_PCSSE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_PCSSE_SHIFT))
+
+/*! @brief Set the PCSSE field to a new value. */
+#define SPI_WR_MCR_PCSSE(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSSE_MASK, SPI_MCR_PCSSE(value)))
+#define SPI_BWR_MCR_PCSSE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_PCSSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MTFE[26] (RW)
+ *
+ * Enables a modified transfer format to be used.
+ *
+ * Values:
+ * - 0b0 - Modified SPI transfer format disabled.
+ * - 0b1 - Modified SPI transfer format enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MTFE field. */
+#define SPI_RD_MCR_MTFE(base) ((SPI_MCR_REG(base) & SPI_MCR_MTFE_MASK) >> SPI_MCR_MTFE_SHIFT)
+#define SPI_BRD_MCR_MTFE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT))
+
+/*! @brief Set the MTFE field to a new value. */
+#define SPI_WR_MCR_MTFE(base, value) (SPI_RMW_MCR(base, SPI_MCR_MTFE_MASK, SPI_MCR_MTFE(value)))
+#define SPI_BWR_MCR_MTFE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field FRZ[27] (RW)
+ *
+ * Enables transfers to be stopped on the next frame boundary when the device
+ * enters Debug mode.
+ *
+ * Values:
+ * - 0b0 - Do not halt serial transfers in Debug mode.
+ * - 0b1 - Halt serial transfers in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_FRZ field. */
+#define SPI_RD_MCR_FRZ(base) ((SPI_MCR_REG(base) & SPI_MCR_FRZ_MASK) >> SPI_MCR_FRZ_SHIFT)
+#define SPI_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define SPI_WR_MCR_FRZ(base, value) (SPI_RMW_MCR(base, SPI_MCR_FRZ_MASK, SPI_MCR_FRZ(value)))
+#define SPI_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DCONF[29:28] (RO)
+ *
+ * Selects among the different configurations of the module.
+ *
+ * Values:
+ * - 0b00 - SPI
+ * - 0b01 - Reserved
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DCONF field. */
+#define SPI_RD_MCR_DCONF(base) ((SPI_MCR_REG(base) & SPI_MCR_DCONF_MASK) >> SPI_MCR_DCONF_SHIFT)
+#define SPI_BRD_MCR_DCONF(base) (SPI_RD_MCR_DCONF(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
+ *
+ * Enables the Serial Communication Clock (SCK) to run continuously.
+ *
+ * Values:
+ * - 0b0 - Continuous SCK disabled.
+ * - 0b1 - Continuous SCK enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */
+#define SPI_RD_MCR_CONT_SCKE(base) ((SPI_MCR_REG(base) & SPI_MCR_CONT_SCKE_MASK) >> SPI_MCR_CONT_SCKE_SHIFT)
+#define SPI_BRD_MCR_CONT_SCKE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT))
+
+/*! @brief Set the CONT_SCKE field to a new value. */
+#define SPI_WR_MCR_CONT_SCKE(base, value) (SPI_RMW_MCR(base, SPI_MCR_CONT_SCKE_MASK, SPI_MCR_CONT_SCKE(value)))
+#define SPI_BWR_MCR_CONT_SCKE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MSTR[31] (RW)
+ *
+ * Enables either Master mode (if supported) or Slave mode (if supported)
+ * operation.
+ *
+ * Values:
+ * - 0b0 - Enables Slave mode
+ * - 0b1 - Enables Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MSTR field. */
+#define SPI_RD_MCR_MSTR(base) ((SPI_MCR_REG(base) & SPI_MCR_MSTR_MASK) >> SPI_MCR_MSTR_SHIFT)
+#define SPI_BRD_MCR_MSTR(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT))
+
+/*! @brief Set the MSTR field to a new value. */
+#define SPI_WR_MCR_MSTR(base, value) (SPI_RMW_MCR(base, SPI_MCR_MSTR_MASK, SPI_MCR_MSTR(value)))
+#define SPI_BWR_MCR_MSTR(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TCR - Transfer Count Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TCR - Transfer Count Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR contains a counter that indicates the number of SPI transfers made. The
+ * transfer counter is intended to assist in queue management. Do not write the
+ * TCR when the module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TCR register
+ */
+/*@{*/
+#define SPI_RD_TCR(base)         (SPI_TCR_REG(base))
+#define SPI_WR_TCR(base, value)  (SPI_TCR_REG(base) = (value))
+#define SPI_RMW_TCR(base, mask, value) (SPI_WR_TCR(base, (SPI_RD_TCR(base) & ~(mask)) | (value)))
+#define SPI_SET_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) |  (value)))
+#define SPI_CLR_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) & ~(value)))
+#define SPI_TOG_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TCR bitfields
+ */
+
+/*!
+ * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
+ *
+ * Counts the number of SPI transfers the module makes. The SPI_TCNT field
+ * increments every time the last bit of an SPI frame is transmitted. A value written
+ * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
+ * the beginning of the frame when the CTCNT field is set in the executing SPI
+ * command. The Transfer Counter wraps around; incrementing the counter past 65535
+ * resets the counter to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */
+#define SPI_RD_TCR_SPI_TCNT(base) ((SPI_TCR_REG(base) & SPI_TCR_SPI_TCNT_MASK) >> SPI_TCR_SPI_TCNT_SHIFT)
+#define SPI_BRD_TCR_SPI_TCNT(base) (SPI_RD_TCR_SPI_TCNT(base))
+
+/*! @brief Set the SPI_TCNT field to a new value. */
+#define SPI_WR_TCR_SPI_TCNT(base, value) (SPI_RMW_TCR(base, SPI_TCR_SPI_TCNT_MASK, SPI_TCR_SPI_TCNT(value)))
+#define SPI_BWR_TCR_SPI_TCNT(base, value) (SPI_WR_TCR_SPI_TCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * When the module is configured as an SPI bus slave, the CTAR0 register is used.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CTAR_SLAVE register
+ */
+/*@{*/
+#define SPI_RD_CTAR_SLAVE(base, index) (SPI_CTAR_SLAVE_REG(base, index))
+#define SPI_WR_CTAR_SLAVE(base, index, value) (SPI_CTAR_SLAVE_REG(base, index) = (value))
+#define SPI_RMW_CTAR_SLAVE(base, index, mask, value) (SPI_WR_CTAR_SLAVE(base, index, (SPI_RD_CTAR_SLAVE(base, index) & ~(mask)) | (value)))
+#define SPI_SET_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) |  (value)))
+#define SPI_CLR_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) & ~(value)))
+#define SPI_TOG_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CTAR_SLAVE bitfields
+ */
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0b0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 0b1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_CPHA field. */
+#define SPI_RD_CTAR_SLAVE_CPHA(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPHA_MASK) >> SPI_CTAR_SLAVE_CPHA_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_CPHA(base, index) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_CTAR_SLAVE_CPHA(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPHA_MASK, SPI_CTAR_SLAVE_CPHA(value)))
+#define SPI_BWR_CTAR_SLAVE_CPHA(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0b0 - The inactive state value of SCK is low.
+ * - 0b1 - The inactive state value of SCK is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_CPOL field. */
+#define SPI_RD_CTAR_SLAVE_CPOL(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPOL_MASK) >> SPI_CTAR_SLAVE_CPOL_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_CPOL(base, index) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_CTAR_SLAVE_CPOL(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPOL_MASK, SPI_CTAR_SLAVE_CPOL(value)))
+#define SPI_BWR_CTAR_SLAVE_CPOL(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field FMSZ[31:27] (RW)
+ *
+ * The number of bits transfered per frame is equal to the FMSZ field value plus
+ * 1. Note that the minimum valid value of frame size is 4.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_FMSZ field. */
+#define SPI_RD_CTAR_SLAVE_FMSZ(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_FMSZ(base, index) (SPI_RD_CTAR_SLAVE_FMSZ(base, index))
+
+/*! @brief Set the FMSZ field to a new value. */
+#define SPI_WR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_FMSZ_MASK, SPI_CTAR_SLAVE_FMSZ(value)))
+#define SPI_BWR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_WR_CTAR_SLAVE_FMSZ(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * CTAR registers are used to define different transfer attributes. Do not write
+ * to the CTAR registers while the module is in the Running state. In Master
+ * mode, the CTAR registers define combinations of transfer attributes such as frame
+ * size, clock phase and polarity, data bit ordering, baud rate, and various
+ * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
+ * slave transfer attributes. When the module is configured as an SPI master, the
+ * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
+ * registers is used. When the module is configured as an SPI bus slave, it uses
+ * the CTAR0 register.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CTAR register
+ */
+/*@{*/
+#define SPI_RD_CTAR(base, index) (SPI_CTAR_REG(base, index))
+#define SPI_WR_CTAR(base, index, value) (SPI_CTAR_REG(base, index) = (value))
+#define SPI_RMW_CTAR(base, index, mask, value) (SPI_WR_CTAR(base, index, (SPI_RD_CTAR(base, index) & ~(mask)) | (value)))
+#define SPI_SET_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) |  (value)))
+#define SPI_CLR_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) & ~(value)))
+#define SPI_TOG_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CTAR bitfields
+ */
+
+/*!
+ * @name Register SPI_CTAR, field BR[3:0] (RW)
+ *
+ * Selects the scaler value for the baud rate. This field is used only in master
+ * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
+ * generate the frequency of the SCK. The baud rate is computed according to the
+ * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
+ * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
+ * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
+ * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_BR field. */
+#define SPI_RD_CTAR_BR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_BR_MASK) >> SPI_CTAR_BR_SHIFT)
+#define SPI_BRD_CTAR_BR(base, index) (SPI_RD_CTAR_BR(base, index))
+
+/*! @brief Set the BR field to a new value. */
+#define SPI_WR_CTAR_BR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_BR_MASK, SPI_CTAR_BR(value)))
+#define SPI_BWR_CTAR_BR(base, index, value) (SPI_WR_CTAR_BR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field DT[7:4] (RW)
+ *
+ * Selects the Delay after Transfer Scaler. This field is used only in master
+ * mode. The Delay after Transfer is the time between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the next
+ * frame. In the Continuous Serial Communications Clock operation, the DT value
+ * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
+ * protocol clock period, and it is computed according to the following
+ * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
+ * field description for scaler values.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_DT field. */
+#define SPI_RD_CTAR_DT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DT_MASK) >> SPI_CTAR_DT_SHIFT)
+#define SPI_BRD_CTAR_DT(base, index) (SPI_RD_CTAR_DT(base, index))
+
+/*! @brief Set the DT field to a new value. */
+#define SPI_WR_CTAR_DT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DT_MASK, SPI_CTAR_DT(value)))
+#define SPI_BWR_CTAR_DT(base, index, value) (SPI_WR_CTAR_DT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field ASC[11:8] (RW)
+ *
+ * Selects the scaler value for the After SCK Delay. This field is used only in
+ * master mode. The After SCK Delay is the delay between the last edge of SCK and
+ * the negation of PCS. The delay is a multiple of the protocol clock period,
+ * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
+ * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
+ * scaler values. Refer After SCK Delay (tASC ) for more details.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_ASC field. */
+#define SPI_RD_CTAR_ASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_ASC_MASK) >> SPI_CTAR_ASC_SHIFT)
+#define SPI_BRD_CTAR_ASC(base, index) (SPI_RD_CTAR_ASC(base, index))
+
+/*! @brief Set the ASC field to a new value. */
+#define SPI_WR_CTAR_ASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_ASC_MASK, SPI_CTAR_ASC(value)))
+#define SPI_BWR_CTAR_ASC(base, index, value) (SPI_WR_CTAR_ASC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CSSCK[15:12] (RW)
+ *
+ * Selects the scaler value for the PCS to SCK delay. This field is used only in
+ * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
+ * and the first edge of the SCK. The delay is a multiple of the protocol clock
+ * period, and it is computed according to the following equation: t CSC = (1/fP )
+ * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
+ * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
+ * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
+ * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
+ * details.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CSSCK field. */
+#define SPI_RD_CTAR_CSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CSSCK_MASK) >> SPI_CTAR_CSSCK_SHIFT)
+#define SPI_BRD_CTAR_CSSCK(base, index) (SPI_RD_CTAR_CSSCK(base, index))
+
+/*! @brief Set the CSSCK field to a new value. */
+#define SPI_WR_CTAR_CSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CSSCK_MASK, SPI_CTAR_CSSCK(value)))
+#define SPI_BWR_CTAR_CSSCK(base, index, value) (SPI_WR_CTAR_CSSCK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PBR[17:16] (RW)
+ *
+ * Selects the prescaler value for the baud rate. This field is used only in
+ * master mode. The baud rate is the frequency of the SCK. The protocol clock is
+ * divided by the prescaler value before the baud rate selection takes place. See
+ * the BR field description for details on how to compute the baud rate.
+ *
+ * Values:
+ * - 0b00 - Baud Rate Prescaler value is 2.
+ * - 0b01 - Baud Rate Prescaler value is 3.
+ * - 0b10 - Baud Rate Prescaler value is 5.
+ * - 0b11 - Baud Rate Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PBR field. */
+#define SPI_RD_CTAR_PBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PBR_MASK) >> SPI_CTAR_PBR_SHIFT)
+#define SPI_BRD_CTAR_PBR(base, index) (SPI_RD_CTAR_PBR(base, index))
+
+/*! @brief Set the PBR field to a new value. */
+#define SPI_WR_CTAR_PBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PBR_MASK, SPI_CTAR_PBR(value)))
+#define SPI_BWR_CTAR_PBR(base, index, value) (SPI_WR_CTAR_PBR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PDT[19:18] (RW)
+ *
+ * Selects the prescaler value for the delay between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the
+ * next frame. The PDT field is only used in master mode. See the DT field
+ * description for details on how to compute the Delay after Transfer. Refer Delay after
+ * Transfer (tDT ) for more details.
+ *
+ * Values:
+ * - 0b00 - Delay after Transfer Prescaler value is 1.
+ * - 0b01 - Delay after Transfer Prescaler value is 3.
+ * - 0b10 - Delay after Transfer Prescaler value is 5.
+ * - 0b11 - Delay after Transfer Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PDT field. */
+#define SPI_RD_CTAR_PDT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PDT_MASK) >> SPI_CTAR_PDT_SHIFT)
+#define SPI_BRD_CTAR_PDT(base, index) (SPI_RD_CTAR_PDT(base, index))
+
+/*! @brief Set the PDT field to a new value. */
+#define SPI_WR_CTAR_PDT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PDT_MASK, SPI_CTAR_PDT(value)))
+#define SPI_BWR_CTAR_PDT(base, index, value) (SPI_WR_CTAR_PDT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PASC[21:20] (RW)
+ *
+ * Selects the prescaler value for the delay between the last edge of SCK and
+ * the negation of PCS. See the ASC field description for information on how to
+ * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
+ *
+ * Values:
+ * - 0b00 - Delay after Transfer Prescaler value is 1.
+ * - 0b01 - Delay after Transfer Prescaler value is 3.
+ * - 0b10 - Delay after Transfer Prescaler value is 5.
+ * - 0b11 - Delay after Transfer Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PASC field. */
+#define SPI_RD_CTAR_PASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PASC_MASK) >> SPI_CTAR_PASC_SHIFT)
+#define SPI_BRD_CTAR_PASC(base, index) (SPI_RD_CTAR_PASC(base, index))
+
+/*! @brief Set the PASC field to a new value. */
+#define SPI_WR_CTAR_PASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PASC_MASK, SPI_CTAR_PASC(value)))
+#define SPI_BWR_CTAR_PASC(base, index, value) (SPI_WR_CTAR_PASC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PCSSCK[23:22] (RW)
+ *
+ * Selects the prescaler value for the delay between assertion of PCS and the
+ * first edge of the SCK. See the CSSCK field description for information on how to
+ * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
+ *
+ * Values:
+ * - 0b00 - PCS to SCK Prescaler value is 1.
+ * - 0b01 - PCS to SCK Prescaler value is 3.
+ * - 0b10 - PCS to SCK Prescaler value is 5.
+ * - 0b11 - PCS to SCK Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PCSSCK field. */
+#define SPI_RD_CTAR_PCSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PCSSCK_MASK) >> SPI_CTAR_PCSSCK_SHIFT)
+#define SPI_BRD_CTAR_PCSSCK(base, index) (SPI_RD_CTAR_PCSSCK(base, index))
+
+/*! @brief Set the PCSSCK field to a new value. */
+#define SPI_WR_CTAR_PCSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PCSSCK_MASK, SPI_CTAR_PCSSCK(value)))
+#define SPI_BWR_CTAR_PCSSCK(base, index, value) (SPI_WR_CTAR_PCSSCK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field LSBFE[24] (RW)
+ *
+ * Specifies whether the LSB or MSB of the frame is transferred first.
+ *
+ * Values:
+ * - 0b0 - Data is transferred MSB first.
+ * - 0b1 - Data is transferred LSB first.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_LSBFE field. */
+#define SPI_RD_CTAR_LSBFE(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_LSBFE_MASK) >> SPI_CTAR_LSBFE_SHIFT)
+#define SPI_BRD_CTAR_LSBFE(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT))
+
+/*! @brief Set the LSBFE field to a new value. */
+#define SPI_WR_CTAR_LSBFE(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_LSBFE_MASK, SPI_CTAR_LSBFE(value)))
+#define SPI_BWR_CTAR_LSBFE(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0b0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 0b1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CPHA field. */
+#define SPI_RD_CTAR_CPHA(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPHA_MASK) >> SPI_CTAR_CPHA_SHIFT)
+#define SPI_BRD_CTAR_CPHA(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_CTAR_CPHA(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPHA_MASK, SPI_CTAR_CPHA(value)))
+#define SPI_BWR_CTAR_CPHA(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). This bit
+ * is used in both master and slave mode. For successful communication between
+ * serial devices, the devices must have identical clock polarities. When the
+ * Continuous Selection Format is selected, switching between clock polarities
+ * without stopping the module can cause errors in the transfer due to the peripheral
+ * device interpreting the switch of clock polarity as a valid clock edge. In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0b0 - The inactive state value of SCK is low.
+ * - 0b1 - The inactive state value of SCK is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CPOL field. */
+#define SPI_RD_CTAR_CPOL(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPOL_MASK) >> SPI_CTAR_CPOL_SHIFT)
+#define SPI_BRD_CTAR_CPOL(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_CTAR_CPOL(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPOL_MASK, SPI_CTAR_CPOL(value)))
+#define SPI_BWR_CTAR_CPOL(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field FMSZ[30:27] (RW)
+ *
+ * The number of bits transferred per frame is equal to the FMSZ value plus 1.
+ * Regardless of the transmission mode, the minimum valid frame size value is 4.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_FMSZ field. */
+#define SPI_RD_CTAR_FMSZ(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT)
+#define SPI_BRD_CTAR_FMSZ(base, index) (SPI_RD_CTAR_FMSZ(base, index))
+
+/*! @brief Set the FMSZ field to a new value. */
+#define SPI_WR_CTAR_FMSZ(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_FMSZ_MASK, SPI_CTAR_FMSZ(value)))
+#define SPI_BWR_CTAR_FMSZ(base, index, value) (SPI_WR_CTAR_FMSZ(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field DBR[31] (RW)
+ *
+ * Doubles the effective baud rate of the Serial Communications Clock (SCK).
+ * This field is used only in master mode. It effectively halves the Baud Rate
+ * division ratio, supporting faster frequencies, and odd division ratios for the
+ * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
+ * Serial Communications Clock (SCK) depends on the value in the Baud Rate
+ * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
+ * description for details on how to compute the baud rate. SPI SCK Duty Cycle
+ * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
+ * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
+ *
+ * Values:
+ * - 0b0 - The baud rate is computed normally with a 50/50 duty cycle.
+ * - 0b1 - The baud rate is doubled with the duty cycle depending on the Baud
+ *     Rate Prescaler.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_DBR field. */
+#define SPI_RD_CTAR_DBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DBR_MASK) >> SPI_CTAR_DBR_SHIFT)
+#define SPI_BRD_CTAR_DBR(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT))
+
+/*! @brief Set the DBR field to a new value. */
+#define SPI_WR_CTAR_DBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DBR_MASK, SPI_CTAR_DBR(value)))
+#define SPI_BWR_CTAR_DBR(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_SR - Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_SR - Status Register (RW)
+ *
+ * Reset value: 0x02000000U
+ *
+ * SR contains status and flag bits. The bits reflect the status of the module
+ * and indicate the occurrence of events that can generate interrupt or DMA
+ * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
+ * to a flag bit has no effect. This register may not be writable in Module
+ * Disable mode due to the use of power saving mechanisms.
+ */
+/*!
+ * @name Constants and macros for entire SPI_SR register
+ */
+/*@{*/
+#define SPI_RD_SR(base)          (SPI_SR_REG(base))
+#define SPI_WR_SR(base, value)   (SPI_SR_REG(base) = (value))
+#define SPI_RMW_SR(base, mask, value) (SPI_WR_SR(base, (SPI_RD_SR(base) & ~(mask)) | (value)))
+#define SPI_SET_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) |  (value)))
+#define SPI_CLR_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) & ~(value)))
+#define SPI_TOG_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_SR bitfields
+ */
+
+/*!
+ * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
+ *
+ * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
+ * The POPNXTPTR is updated when the POPR is read.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_POPNXTPTR field. */
+#define SPI_RD_SR_POPNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_POPNXTPTR_MASK) >> SPI_SR_POPNXTPTR_SHIFT)
+#define SPI_BRD_SR_POPNXTPTR(base) (SPI_RD_SR_POPNXTPTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RXCTR[7:4] (RO)
+ *
+ * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
+ * every time the POPR is read. The RXCTR is incremented every time data is
+ * transferred from the shift register to the RX FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RXCTR field. */
+#define SPI_RD_SR_RXCTR(base) ((SPI_SR_REG(base) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT)
+#define SPI_BRD_SR_RXCTR(base) (SPI_RD_SR_RXCTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
+ *
+ * Indicates which TX FIFO entry is transmitted during the next transfer. The
+ * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
+ * the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXNXTPTR field. */
+#define SPI_RD_SR_TXNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_TXNXTPTR_MASK) >> SPI_SR_TXNXTPTR_SHIFT)
+#define SPI_BRD_SR_TXNXTPTR(base) (SPI_RD_SR_TXNXTPTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXCTR[15:12] (RO)
+ *
+ * Indicates the number of valid entries in the TX FIFO. The TXCTR is
+ * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
+ * command is executed and the SPI data is transferred to the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXCTR field. */
+#define SPI_RD_SR_TXCTR(base) ((SPI_SR_REG(base) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT)
+#define SPI_BRD_SR_TXCTR(base) (SPI_RD_SR_TXCTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RFDF[17] (W1C)
+ *
+ * Provides a method for the module to request that entries be removed from the
+ * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller when
+ * the RX FIFO is empty.
+ *
+ * Values:
+ * - 0b0 - RX FIFO is empty.
+ * - 0b1 - RX FIFO is not empty.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RFDF field. */
+#define SPI_RD_SR_RFDF(base) ((SPI_SR_REG(base) & SPI_SR_RFDF_MASK) >> SPI_SR_RFDF_SHIFT)
+#define SPI_BRD_SR_RFDF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT))
+
+/*! @brief Set the RFDF field to a new value. */
+#define SPI_WR_SR_RFDF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFDF(value)))
+#define SPI_BWR_SR_RFDF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RFOF[19] (W1C)
+ *
+ * Indicates an overflow condition in the RX FIFO. The field is set when the RX
+ * FIFO and shift register are full and a transfer is initiated. The bit remains
+ * set until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - No Rx FIFO overflow.
+ * - 0b1 - Rx FIFO overflow has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RFOF field. */
+#define SPI_RD_SR_RFOF(base) ((SPI_SR_REG(base) & SPI_SR_RFOF_MASK) >> SPI_SR_RFOF_SHIFT)
+#define SPI_BRD_SR_RFOF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT))
+
+/*! @brief Set the RFOF field to a new value. */
+#define SPI_WR_SR_RFOF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFOF(value)))
+#define SPI_BWR_SR_RFOF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TFFF[25] (W1C)
+ *
+ * Provides a method for the module to request more entries to be added to the
+ * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller to
+ * the TX FIFO full request.
+ *
+ * Values:
+ * - 0b0 - TX FIFO is full.
+ * - 0b1 - TX FIFO is not full.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TFFF field. */
+#define SPI_RD_SR_TFFF(base) ((SPI_SR_REG(base) & SPI_SR_TFFF_MASK) >> SPI_SR_TFFF_SHIFT)
+#define SPI_BRD_SR_TFFF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT))
+
+/*! @brief Set the TFFF field to a new value. */
+#define SPI_WR_SR_TFFF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFFF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFFF(value)))
+#define SPI_BWR_SR_TFFF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TFUF[27] (W1C)
+ *
+ * Indicates an underflow condition in the TX FIFO. The transmit underflow
+ * condition is detected only for SPI blocks operating in Slave mode and SPI
+ * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
+ * is empty and an external SPI master initiates a transfer. The TFUF bit remains
+ * set until cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No TX FIFO underflow.
+ * - 0b1 - TX FIFO underflow has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TFUF field. */
+#define SPI_RD_SR_TFUF(base) ((SPI_SR_REG(base) & SPI_SR_TFUF_MASK) >> SPI_SR_TFUF_SHIFT)
+#define SPI_BRD_SR_TFUF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT))
+
+/*! @brief Set the TFUF field to a new value. */
+#define SPI_WR_SR_TFUF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFUF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFUF(value)))
+#define SPI_BWR_SR_TFUF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field EOQF[28] (W1C)
+ *
+ * Indicates that the last entry in a queue has been transmitted when the module
+ * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
+ * set in the command halfword and the end of the transfer is reached. The EOQF
+ * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
+ * the TXRXS bit is automatically cleared.
+ *
+ * Values:
+ * - 0b0 - EOQ is not set in the executing command.
+ * - 0b1 - EOQ is set in the executing SPI command.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_EOQF field. */
+#define SPI_RD_SR_EOQF(base) ((SPI_SR_REG(base) & SPI_SR_EOQF_MASK) >> SPI_SR_EOQF_SHIFT)
+#define SPI_BRD_SR_EOQF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT))
+
+/*! @brief Set the EOQF field to a new value. */
+#define SPI_WR_SR_EOQF(base, value) (SPI_RMW_SR(base, (SPI_SR_EOQF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_EOQF(value)))
+#define SPI_BWR_SR_EOQF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXRXS[30] (W1C)
+ *
+ * Reflects the run status of the module.
+ *
+ * Values:
+ * - 0b0 - Transmit and receive operations are disabled (The module is in
+ *     Stopped state).
+ * - 0b1 - Transmit and receive operations are enabled (The module is in Running
+ *     state).
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXRXS field. */
+#define SPI_RD_SR_TXRXS(base) ((SPI_SR_REG(base) & SPI_SR_TXRXS_MASK) >> SPI_SR_TXRXS_SHIFT)
+#define SPI_BRD_SR_TXRXS(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT))
+
+/*! @brief Set the TXRXS field to a new value. */
+#define SPI_WR_SR_TXRXS(base, value) (SPI_RMW_SR(base, (SPI_SR_TXRXS_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TCF_MASK), SPI_SR_TXRXS(value)))
+#define SPI_BWR_SR_TXRXS(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TCF[31] (W1C)
+ *
+ * Indicates that all bits in a frame have been shifted out. TCF remains set
+ * until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - Transfer not complete.
+ * - 0b1 - Transfer complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TCF field. */
+#define SPI_RD_SR_TCF(base)  ((SPI_SR_REG(base) & SPI_SR_TCF_MASK) >> SPI_SR_TCF_SHIFT)
+#define SPI_BRD_SR_TCF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT))
+
+/*! @brief Set the TCF field to a new value. */
+#define SPI_WR_SR_TCF(base, value) (SPI_RMW_SR(base, (SPI_SR_TCF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK), SPI_SR_TCF(value)))
+#define SPI_BWR_SR_TCF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RSER controls DMA and interrupt requests. Do not write to the RSER while the
+ * module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RSER register
+ */
+/*@{*/
+#define SPI_RD_RSER(base)        (SPI_RSER_REG(base))
+#define SPI_WR_RSER(base, value) (SPI_RSER_REG(base) = (value))
+#define SPI_RMW_RSER(base, mask, value) (SPI_WR_RSER(base, (SPI_RD_RSER(base) & ~(mask)) | (value)))
+#define SPI_SET_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) |  (value)))
+#define SPI_CLR_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) & ~(value)))
+#define SPI_TOG_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_RSER bitfields
+ */
+
+/*!
+ * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When the
+ * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
+ * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - Interrupt request.
+ * - 0b1 - DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */
+#define SPI_RD_RSER_RFDF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_DIRS_MASK) >> SPI_RSER_RFDF_DIRS_SHIFT)
+#define SPI_BRD_RSER_RFDF_DIRS(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT))
+
+/*! @brief Set the RFDF_DIRS field to a new value. */
+#define SPI_WR_RSER_RFDF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_DIRS_MASK, SPI_RSER_RFDF_DIRS(value)))
+#define SPI_BWR_RSER_RFDF_DIRS(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field RFDF_RE[17] (RW)
+ *
+ * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - RFDF interrupt or DMA requests are disabled.
+ * - 0b1 - RFDF interrupt or DMA requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFDF_RE field. */
+#define SPI_RD_RSER_RFDF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_RE_MASK) >> SPI_RSER_RFDF_RE_SHIFT)
+#define SPI_BRD_RSER_RFDF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT))
+
+/*! @brief Set the RFDF_RE field to a new value. */
+#define SPI_WR_RSER_RFDF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_RE_MASK, SPI_RSER_RFDF_RE(value)))
+#define SPI_BWR_RSER_RFDF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field RFOF_RE[19] (RW)
+ *
+ * Enables the RFOF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - RFOF interrupt requests are disabled.
+ * - 0b1 - RFOF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFOF_RE field. */
+#define SPI_RD_RSER_RFOF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFOF_RE_MASK) >> SPI_RSER_RFOF_RE_SHIFT)
+#define SPI_BRD_RSER_RFOF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT))
+
+/*! @brief Set the RFOF_RE field to a new value. */
+#define SPI_WR_RSER_RFOF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFOF_RE_MASK, SPI_RSER_RFOF_RE(value)))
+#define SPI_BWR_RSER_RFOF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When
+ * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
+ * interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - TFFF flag generates interrupt requests.
+ * - 0b1 - TFFF flag generates DMA requests.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */
+#define SPI_RD_RSER_TFFF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_DIRS_MASK) >> SPI_RSER_TFFF_DIRS_SHIFT)
+#define SPI_BRD_RSER_TFFF_DIRS(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT))
+
+/*! @brief Set the TFFF_DIRS field to a new value. */
+#define SPI_WR_RSER_TFFF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_DIRS_MASK, SPI_RSER_TFFF_DIRS(value)))
+#define SPI_BWR_RSER_TFFF_DIRS(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFFF_RE[25] (RW)
+ *
+ * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - TFFF interrupts or DMA requests are disabled.
+ * - 0b1 - TFFF interrupts or DMA requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFFF_RE field. */
+#define SPI_RD_RSER_TFFF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_RE_MASK) >> SPI_RSER_TFFF_RE_SHIFT)
+#define SPI_BRD_RSER_TFFF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT))
+
+/*! @brief Set the TFFF_RE field to a new value. */
+#define SPI_WR_RSER_TFFF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_RE_MASK, SPI_RSER_TFFF_RE(value)))
+#define SPI_BWR_RSER_TFFF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFUF_RE[27] (RW)
+ *
+ * Enables the TFUF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - TFUF interrupt requests are disabled.
+ * - 0b1 - TFUF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFUF_RE field. */
+#define SPI_RD_RSER_TFUF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFUF_RE_MASK) >> SPI_RSER_TFUF_RE_SHIFT)
+#define SPI_BRD_RSER_TFUF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT))
+
+/*! @brief Set the TFUF_RE field to a new value. */
+#define SPI_WR_RSER_TFUF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFUF_RE_MASK, SPI_RSER_TFUF_RE(value)))
+#define SPI_BWR_RSER_TFUF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field EOQF_RE[28] (RW)
+ *
+ * Enables the EOQF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - EOQF interrupt requests are disabled.
+ * - 0b1 - EOQF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_EOQF_RE field. */
+#define SPI_RD_RSER_EOQF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_EOQF_RE_MASK) >> SPI_RSER_EOQF_RE_SHIFT)
+#define SPI_BRD_RSER_EOQF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT))
+
+/*! @brief Set the EOQF_RE field to a new value. */
+#define SPI_WR_RSER_EOQF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_EOQF_RE_MASK, SPI_RSER_EOQF_RE(value)))
+#define SPI_BWR_RSER_EOQF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TCF_RE[31] (RW)
+ *
+ * Enables TCF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - TCF interrupt requests are disabled.
+ * - 0b1 - TCF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TCF_RE field. */
+#define SPI_RD_RSER_TCF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TCF_RE_MASK) >> SPI_RSER_TCF_RE_SHIFT)
+#define SPI_BRD_RSER_TCF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT))
+
+/*! @brief Set the TCF_RE field to a new value. */
+#define SPI_WR_RSER_TCF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TCF_RE_MASK, SPI_RSER_TCF_RE(value)))
+#define SPI_BWR_RSER_TCF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
+ * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
+ * can be used as data, supporting up to 32-bit frame operation. A read access
+ * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
+ * writing to this register does not update the FIFO. Therefore, any reads performed
+ * while the module is disabled return the last PUSHR write performed while the
+ * module was still enabled.
+ */
+/*!
+ * @name Constants and macros for entire SPI_PUSHR register
+ */
+/*@{*/
+#define SPI_RD_PUSHR(base)       (SPI_PUSHR_REG(base))
+#define SPI_WR_PUSHR(base, value) (SPI_PUSHR_REG(base) = (value))
+#define SPI_RMW_PUSHR(base, mask, value) (SPI_WR_PUSHR(base, (SPI_RD_PUSHR(base) & ~(mask)) | (value)))
+#define SPI_SET_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) |  (value)))
+#define SPI_CLR_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) & ~(value)))
+#define SPI_TOG_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_PUSHR bitfields
+ */
+
+/*!
+ * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
+ *
+ * Holds SPI data to be transferred according to the associated SPI command.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_TXDATA field. */
+#define SPI_RD_PUSHR_TXDATA(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_TXDATA_MASK) >> SPI_PUSHR_TXDATA_SHIFT)
+#define SPI_BRD_PUSHR_TXDATA(base) (SPI_RD_PUSHR_TXDATA(base))
+
+/*! @brief Set the TXDATA field to a new value. */
+#define SPI_WR_PUSHR_TXDATA(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_TXDATA_MASK, SPI_PUSHR_TXDATA(value)))
+#define SPI_BWR_PUSHR_TXDATA(base, value) (SPI_WR_PUSHR_TXDATA(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field PCS[21:16] (RW)
+ *
+ * Select which PCS signals are to be asserted for the transfer. Refer to the
+ * chip configuration details for the number of PCS signals used in this MCU.
+ *
+ * Values:
+ * - 0b000000 - Negate the PCS[x] signal.
+ * - 0b000001 - Assert the PCS[x] signal.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_PCS field. */
+#define SPI_RD_PUSHR_PCS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_PCS_MASK) >> SPI_PUSHR_PCS_SHIFT)
+#define SPI_BRD_PUSHR_PCS(base) (SPI_RD_PUSHR_PCS(base))
+
+/*! @brief Set the PCS field to a new value. */
+#define SPI_WR_PUSHR_PCS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_PCS_MASK, SPI_PUSHR_PCS(value)))
+#define SPI_BWR_PUSHR_PCS(base, value) (SPI_WR_PUSHR_PCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CTCNT[26] (RW)
+ *
+ * Clears the TCNT field in the TCR register. The TCNT field is cleared before
+ * the module starts transmitting the current SPI frame.
+ *
+ * Values:
+ * - 0b0 - Do not clear the TCR[TCNT] field.
+ * - 0b1 - Clear the TCR[TCNT] field.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CTCNT field. */
+#define SPI_RD_PUSHR_CTCNT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTCNT_MASK) >> SPI_PUSHR_CTCNT_SHIFT)
+#define SPI_BRD_PUSHR_CTCNT(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT))
+
+/*! @brief Set the CTCNT field to a new value. */
+#define SPI_WR_PUSHR_CTCNT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTCNT_MASK, SPI_PUSHR_CTCNT(value)))
+#define SPI_BWR_PUSHR_CTCNT(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field EOQ[27] (RW)
+ *
+ * Host software uses this bit to signal to the module that the current SPI
+ * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
+ * SR is set.
+ *
+ * Values:
+ * - 0b0 - The SPI data is not the last data to transfer.
+ * - 0b1 - The SPI data is the last data to transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_EOQ field. */
+#define SPI_RD_PUSHR_EOQ(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_EOQ_MASK) >> SPI_PUSHR_EOQ_SHIFT)
+#define SPI_BRD_PUSHR_EOQ(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT))
+
+/*! @brief Set the EOQ field to a new value. */
+#define SPI_WR_PUSHR_EOQ(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_EOQ_MASK, SPI_PUSHR_EOQ(value)))
+#define SPI_BWR_PUSHR_EOQ(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
+ *
+ * Selects which CTAR to use in master mode to specify the transfer attributes
+ * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
+ * configuration details to determine how many CTARs this device has. You should
+ * not program a value in this field for a register that is not present.
+ *
+ * Values:
+ * - 0b000 - CTAR0
+ * - 0b001 - CTAR1
+ * - 0b010 - Reserved
+ * - 0b011 - Reserved
+ * - 0b100 - Reserved
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CTAS field. */
+#define SPI_RD_PUSHR_CTAS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTAS_MASK) >> SPI_PUSHR_CTAS_SHIFT)
+#define SPI_BRD_PUSHR_CTAS(base) (SPI_RD_PUSHR_CTAS(base))
+
+/*! @brief Set the CTAS field to a new value. */
+#define SPI_WR_PUSHR_CTAS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTAS_MASK, SPI_PUSHR_CTAS(value)))
+#define SPI_BWR_PUSHR_CTAS(base, value) (SPI_WR_PUSHR_CTAS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CONT[31] (RW)
+ *
+ * Selects a continuous selection format. The bit is used in SPI Master mode.
+ * The bit enables the selected PCS signals to remain asserted between transfers.
+ *
+ * Values:
+ * - 0b0 - Return PCSn signals to their inactive state between transfers.
+ * - 0b1 - Keep PCSn signals asserted between transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CONT field. */
+#define SPI_RD_PUSHR_CONT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CONT_MASK) >> SPI_PUSHR_CONT_SHIFT)
+#define SPI_BRD_PUSHR_CONT(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT))
+
+/*! @brief Set the CONT field to a new value. */
+#define SPI_WR_PUSHR_CONT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CONT_MASK, SPI_PUSHR_CONT(value)))
+#define SPI_BWR_PUSHR_CONT(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
+ * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
+ * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
+ * SPI Frame operation.
+ */
+/*!
+ * @name Constants and macros for entire SPI_PUSHR_SLAVE register
+ */
+/*@{*/
+#define SPI_RD_PUSHR_SLAVE(base) (SPI_PUSHR_SLAVE_REG(base))
+#define SPI_WR_PUSHR_SLAVE(base, value) (SPI_PUSHR_SLAVE_REG(base) = (value))
+#define SPI_RMW_PUSHR_SLAVE(base, mask, value) (SPI_WR_PUSHR_SLAVE(base, (SPI_RD_PUSHR_SLAVE(base) & ~(mask)) | (value)))
+#define SPI_SET_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) |  (value)))
+#define SPI_CLR_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) & ~(value)))
+#define SPI_TOG_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_POPR - POP RX FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_POPR - POP RX FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
+ * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
+ * this register will generate a Transfer Error.
+ */
+/*!
+ * @name Constants and macros for entire SPI_POPR register
+ */
+/*@{*/
+#define SPI_RD_POPR(base)        (SPI_POPR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR0 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR0 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR0 register
+ */
+/*@{*/
+#define SPI_RD_TXFR0(base)       (SPI_TXFR0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR0 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR0, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR0_TXDATA field. */
+#define SPI_RD_TXFR0_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXDATA_MASK) >> SPI_TXFR0_TXDATA_SHIFT)
+#define SPI_BRD_TXFR0_TXDATA(base) (SPI_RD_TXFR0_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR0, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR0_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR0_TXCMD_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXCMD_TXDATA_MASK) >> SPI_TXFR0_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR0_TXCMD_TXDATA(base) (SPI_RD_TXFR0_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR1 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR1 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR1 register
+ */
+/*@{*/
+#define SPI_RD_TXFR1(base)       (SPI_TXFR1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR1 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR1, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR1_TXDATA field. */
+#define SPI_RD_TXFR1_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXDATA_MASK) >> SPI_TXFR1_TXDATA_SHIFT)
+#define SPI_BRD_TXFR1_TXDATA(base) (SPI_RD_TXFR1_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR1, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR1_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR1_TXCMD_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXCMD_TXDATA_MASK) >> SPI_TXFR1_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR1_TXCMD_TXDATA(base) (SPI_RD_TXFR1_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR2 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR2 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR2 register
+ */
+/*@{*/
+#define SPI_RD_TXFR2(base)       (SPI_TXFR2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR2 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR2, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR2_TXDATA field. */
+#define SPI_RD_TXFR2_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXDATA_MASK) >> SPI_TXFR2_TXDATA_SHIFT)
+#define SPI_BRD_TXFR2_TXDATA(base) (SPI_RD_TXFR2_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR2, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR2_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR2_TXCMD_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXCMD_TXDATA_MASK) >> SPI_TXFR2_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR2_TXCMD_TXDATA(base) (SPI_RD_TXFR2_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR3 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR3 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR3 register
+ */
+/*@{*/
+#define SPI_RD_TXFR3(base)       (SPI_TXFR3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR3 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR3, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR3_TXDATA field. */
+#define SPI_RD_TXFR3_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXDATA_MASK) >> SPI_TXFR3_TXDATA_SHIFT)
+#define SPI_BRD_TXFR3_TXDATA(base) (SPI_RD_TXFR3_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR3, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR3_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR3_TXCMD_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXCMD_TXDATA_MASK) >> SPI_TXFR3_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR3_TXCMD_TXDATA(base) (SPI_RD_TXFR3_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR0 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR0 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR0 register
+ */
+/*@{*/
+#define SPI_RD_RXFR0(base)       (SPI_RXFR0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR1 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR1 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR1 register
+ */
+/*@{*/
+#define SPI_RD_RXFR1(base)       (SPI_RXFR1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR2 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR2 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR2 register
+ */
+/*@{*/
+#define SPI_RD_RXFR2(base)       (SPI_RXFR2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR3 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR3 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR3 register
+ */
+/*@{*/
+#define SPI_RD_RXFR3(base)       (SPI_RXFR3_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 UART
+ *
+ * Serial Communication Interface
+ *
+ * Registers defined in this header file:
+ * - UART_BDH - UART Baud Rate Registers: High
+ * - UART_BDL - UART Baud Rate Registers: Low
+ * - UART_C1 - UART Control Register 1
+ * - UART_C2 - UART Control Register 2
+ * - UART_S1 - UART Status Register 1
+ * - UART_S2 - UART Status Register 2
+ * - UART_C3 - UART Control Register 3
+ * - UART_D - UART Data Register
+ * - UART_MA1 - UART Match Address Registers 1
+ * - UART_MA2 - UART Match Address Registers 2
+ * - UART_C4 - UART Control Register 4
+ * - UART_C5 - UART Control Register 5
+ * - UART_ED - UART Extended Data Register
+ * - UART_MODEM - UART Modem Register
+ * - UART_IR - UART Infrared Register
+ * - UART_PFIFO - UART FIFO Parameters
+ * - UART_CFIFO - UART FIFO Control Register
+ * - UART_SFIFO - UART FIFO Status Register
+ * - UART_TWFIFO - UART FIFO Transmit Watermark
+ * - UART_TCFIFO - UART FIFO Transmit Count
+ * - UART_RWFIFO - UART FIFO Receive Watermark
+ * - UART_RCFIFO - UART FIFO Receive Count
+ * - UART_C7816 - UART 7816 Control Register
+ * - UART_IE7816 - UART 7816 Interrupt Enable Register
+ * - UART_IS7816 - UART 7816 Interrupt Status Register
+ * - UART_WP7816T0 - UART 7816 Wait Parameter Register
+ * - UART_WP7816T1 - UART 7816 Wait Parameter Register
+ * - UART_WN7816 - UART 7816 Wait N Register
+ * - UART_WF7816 - UART 7816 Wait FD Register
+ * - UART_ET7816 - UART 7816 Error Threshold Register
+ * - UART_TL7816 - UART 7816 Transmit Length Register
+ */
+
+#define UART_INSTANCE_COUNT (6U) /*!< Number of instances of the UART module. */
+#define UART0_IDX (0U) /*!< Instance number for UART0. */
+#define UART1_IDX (1U) /*!< Instance number for UART1. */
+#define UART2_IDX (2U) /*!< Instance number for UART2. */
+#define UART3_IDX (3U) /*!< Instance number for UART3. */
+#define UART4_IDX (4U) /*!< Instance number for UART4. */
+#define UART5_IDX (5U) /*!< Instance number for UART5. */
+
+/*******************************************************************************
+ * UART_BDH - UART Baud Rate Registers: High
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDH - UART Baud Rate Registers: High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register, along with the BDL register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting
+ * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
+ * to BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is,
+ * when C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDH register
+ */
+/*@{*/
+#define UART_RD_BDH(base)        (UART_BDH_REG(base))
+#define UART_WR_BDH(base, value) (UART_BDH_REG(base) = (value))
+#define UART_RMW_BDH(base, mask, value) (UART_WR_BDH(base, (UART_RD_BDH(base) & ~(mask)) | (value)))
+#define UART_SET_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) |  (value)))
+#define UART_CLR_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) & ~(value)))
+#define UART_TOG_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_BDH bitfields
+ */
+
+/*!
+ * @name Register UART_BDH, field SBR[4:0] (RW)
+ *
+ * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
+ * generation for details. The baud rate generator is disabled until C2[TE] or
+ * C2[RE] is set for the first time after reset.The baud rate generator is disabled
+ * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
+ * writing to BDH puts the data in a temporary location until BDL is written.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBR field. */
+#define UART_RD_BDH_SBR(base) ((UART_BDH_REG(base) & UART_BDH_SBR_MASK) >> UART_BDH_SBR_SHIFT)
+#define UART_BRD_BDH_SBR(base) (UART_RD_BDH_SBR(base))
+
+/*! @brief Set the SBR field to a new value. */
+#define UART_WR_BDH_SBR(base, value) (UART_RMW_BDH(base, UART_BDH_SBR_MASK, UART_BDH_SBR(value)))
+#define UART_BWR_BDH_SBR(base, value) (UART_WR_BDH_SBR(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field SBNS[5] (RW)
+ *
+ * SBNS selects the number of stop bits present in a data frame. This field
+ * valid for all 8, 9 and 10 bit data formats available. This field is not valid when
+ * C7816[ISO7816E] is enabled.
+ *
+ * Values:
+ * - 0b0 - Data frame consists of a single stop bit.
+ * - 0b1 - Data frame consists of two stop bits.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBNS field. */
+#define UART_RD_BDH_SBNS(base) ((UART_BDH_REG(base) & UART_BDH_SBNS_MASK) >> UART_BDH_SBNS_SHIFT)
+#define UART_BRD_BDH_SBNS(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_SBNS_SHIFT))
+
+/*! @brief Set the SBNS field to a new value. */
+#define UART_WR_BDH_SBNS(base, value) (UART_RMW_BDH(base, UART_BDH_SBNS_MASK, UART_BDH_SBNS(value)))
+#define UART_BWR_BDH_SBNS(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_SBNS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field RXEDGIE[6] (RW)
+ *
+ * Enables the receive input active edge, RXEDGIF, to generate interrupt
+ * requests.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupts from RXEDGIF disabled using polling.
+ * - 0b1 - RXEDGIF interrupt request enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_RXEDGIE field. */
+#define UART_RD_BDH_RXEDGIE(base) ((UART_BDH_REG(base) & UART_BDH_RXEDGIE_MASK) >> UART_BDH_RXEDGIE_SHIFT)
+#define UART_BRD_BDH_RXEDGIE(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT))
+
+/*! @brief Set the RXEDGIE field to a new value. */
+#define UART_WR_BDH_RXEDGIE(base, value) (UART_RMW_BDH(base, UART_BDH_RXEDGIE_MASK, UART_BDH_RXEDGIE(value)))
+#define UART_BWR_BDH_RXEDGIE(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field LBKDIE[7] (RW)
+ *
+ * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
+ * based on the state of LBKDDMAS. or DMA transfer requests,
+ *
+ * Values:
+ * - 0b0 - LBKDIF interrupt and DMA transfer requests disabled.
+ * - 0b1 - LBKDIF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_LBKDIE field. */
+#define UART_RD_BDH_LBKDIE(base) ((UART_BDH_REG(base) & UART_BDH_LBKDIE_MASK) >> UART_BDH_LBKDIE_SHIFT)
+#define UART_BRD_BDH_LBKDIE(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_LBKDIE_SHIFT))
+
+/*! @brief Set the LBKDIE field to a new value. */
+#define UART_WR_BDH_LBKDIE(base, value) (UART_RMW_BDH(base, UART_BDH_LBKDIE_MASK, UART_BDH_LBKDIE(value)))
+#define UART_BWR_BDH_LBKDIE(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_LBKDIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_BDL - UART Baud Rate Registers: Low
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDL - UART Baud Rate Registers: Low (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * This register, along with the BDH register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
+ * first write to BDH to buffer the high half of the new value and then write to
+ * BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is, when
+ * C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDL register
+ */
+/*@{*/
+#define UART_RD_BDL(base)        (UART_BDL_REG(base))
+#define UART_WR_BDL(base, value) (UART_BDL_REG(base) = (value))
+#define UART_RMW_BDL(base, mask, value) (UART_WR_BDL(base, (UART_RD_BDL(base) & ~(mask)) | (value)))
+#define UART_SET_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) |  (value)))
+#define UART_CLR_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) & ~(value)))
+#define UART_TOG_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C1 - UART Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C1 - UART Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This read/write register controls various optional features of the UART
+ * system.
+ */
+/*!
+ * @name Constants and macros for entire UART_C1 register
+ */
+/*@{*/
+#define UART_RD_C1(base)         (UART_C1_REG(base))
+#define UART_WR_C1(base, value)  (UART_C1_REG(base) = (value))
+#define UART_RMW_C1(base, mask, value) (UART_WR_C1(base, (UART_RD_C1(base) & ~(mask)) | (value)))
+#define UART_SET_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) |  (value)))
+#define UART_CLR_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) & ~(value)))
+#define UART_TOG_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C1 bitfields
+ */
+
+/*!
+ * @name Register UART_C1, field PT[0] (RW)
+ *
+ * Determines whether the UART generates and checks for even parity or odd
+ * parity. With even parity, an even number of 1s clears the parity bit and an odd
+ * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
+ * parity bit and an even number of 1s sets the parity bit. This field must be
+ * cleared when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Even parity.
+ * - 0b1 - Odd parity.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PT field. */
+#define UART_RD_C1_PT(base)  ((UART_C1_REG(base) & UART_C1_PT_MASK) >> UART_C1_PT_SHIFT)
+#define UART_BRD_C1_PT(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PT_SHIFT))
+
+/*! @brief Set the PT field to a new value. */
+#define UART_WR_C1_PT(base, value) (UART_RMW_C1(base, UART_C1_PT_MASK, UART_C1_PT(value)))
+#define UART_BWR_C1_PT(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field PE[1] (RW)
+ *
+ * Enables the parity function. When parity is enabled, parity function inserts
+ * a parity bit in the bit position immediately preceding the stop bit. This
+ * field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Parity function disabled.
+ * - 0b1 - Parity function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PE field. */
+#define UART_RD_C1_PE(base)  ((UART_C1_REG(base) & UART_C1_PE_MASK) >> UART_C1_PE_SHIFT)
+#define UART_BRD_C1_PE(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PE_SHIFT))
+
+/*! @brief Set the PE field to a new value. */
+#define UART_WR_C1_PE(base, value) (UART_RMW_C1(base, UART_C1_PE_MASK, UART_C1_PE(value)))
+#define UART_BWR_C1_PE(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field ILT[2] (RW)
+ *
+ * Determines when the receiver starts counting logic 1s as idle character bits.
+ * The count begins either after a valid start bit or after the stop bit. If the
+ * count begins after the start bit, then a string of logic 1s preceding the
+ * stop bit can cause false recognition of an idle character. Beginning the count
+ * after the stop bit avoids false idle character recognition, but requires
+ * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
+ * logic of 1'b0 is automatically shifted after a received stop bit, therefore
+ * resetting the idle count. In case the UART is programmed for IDLE line wakeup
+ * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
+ * logic 1s as idle character bits. In idle line wakeup, an idle character is
+ * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
+ * and C4[M10] fields.
+ *
+ * Values:
+ * - 0b0 - Idle character bit count starts after start bit.
+ * - 0b1 - Idle character bit count starts after stop bit.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_ILT field. */
+#define UART_RD_C1_ILT(base) ((UART_C1_REG(base) & UART_C1_ILT_MASK) >> UART_C1_ILT_SHIFT)
+#define UART_BRD_C1_ILT(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_ILT_SHIFT))
+
+/*! @brief Set the ILT field to a new value. */
+#define UART_WR_C1_ILT(base, value) (UART_RMW_C1(base, UART_C1_ILT_MASK, UART_C1_ILT(value)))
+#define UART_BWR_C1_ILT(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_ILT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field WAKE[3] (RW)
+ *
+ * Determines which condition wakes the UART: Address mark in the most
+ * significant bit position of a received data character, or An idle condition on the
+ * receive pin input signal.
+ *
+ * Values:
+ * - 0b0 - Idle line wakeup.
+ * - 0b1 - Address mark wakeup.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_WAKE field. */
+#define UART_RD_C1_WAKE(base) ((UART_C1_REG(base) & UART_C1_WAKE_MASK) >> UART_C1_WAKE_SHIFT)
+#define UART_BRD_C1_WAKE(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT))
+
+/*! @brief Set the WAKE field to a new value. */
+#define UART_WR_C1_WAKE(base, value) (UART_RMW_C1(base, UART_C1_WAKE_MASK, UART_C1_WAKE(value)))
+#define UART_BWR_C1_WAKE(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field M[4] (RW)
+ *
+ * This field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) +
+ *     stop.
+ * - 0b1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_M field. */
+#define UART_RD_C1_M(base)   ((UART_C1_REG(base) & UART_C1_M_MASK) >> UART_C1_M_SHIFT)
+#define UART_BRD_C1_M(base)  (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_M_SHIFT))
+
+/*! @brief Set the M field to a new value. */
+#define UART_WR_C1_M(base, value) (UART_RMW_C1(base, UART_C1_M_MASK, UART_C1_M(value)))
+#define UART_BWR_C1_M(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_M_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field RSRC[5] (RW)
+ *
+ * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
+ * is set, the RSRC field determines the source for the receiver shift register
+ * input.
+ *
+ * Values:
+ * - 0b0 - Selects internal loop back mode. The receiver input is internally
+ *     connected to transmitter output.
+ * - 0b1 - Single wire UART mode where the receiver input is connected to the
+ *     transmit pin input signal.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_RSRC field. */
+#define UART_RD_C1_RSRC(base) ((UART_C1_REG(base) & UART_C1_RSRC_MASK) >> UART_C1_RSRC_SHIFT)
+#define UART_BRD_C1_RSRC(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT))
+
+/*! @brief Set the RSRC field to a new value. */
+#define UART_WR_C1_RSRC(base, value) (UART_RMW_C1(base, UART_C1_RSRC_MASK, UART_C1_RSRC(value)))
+#define UART_BWR_C1_RSRC(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field UARTSWAI[6] (RW)
+ *
+ * Values:
+ * - 0b0 - UART clock continues to run in Wait mode.
+ * - 0b1 - UART clock freezes while CPU is in Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_UARTSWAI field. */
+#define UART_RD_C1_UARTSWAI(base) ((UART_C1_REG(base) & UART_C1_UARTSWAI_MASK) >> UART_C1_UARTSWAI_SHIFT)
+#define UART_BRD_C1_UARTSWAI(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_UARTSWAI_SHIFT))
+
+/*! @brief Set the UARTSWAI field to a new value. */
+#define UART_WR_C1_UARTSWAI(base, value) (UART_RMW_C1(base, UART_C1_UARTSWAI_MASK, UART_C1_UARTSWAI(value)))
+#define UART_BWR_C1_UARTSWAI(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_UARTSWAI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field LOOPS[7] (RW)
+ *
+ * When LOOPS is set, the RxD pin is disconnected from the UART and the
+ * transmitter output is internally connected to the receiver input. The transmitter and
+ * the receiver must be enabled to use the loop function.
+ *
+ * Values:
+ * - 0b0 - Normal operation.
+ * - 0b1 - Loop mode where transmitter output is internally connected to
+ *     receiver input. The receiver input is determined by RSRC.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_LOOPS field. */
+#define UART_RD_C1_LOOPS(base) ((UART_C1_REG(base) & UART_C1_LOOPS_MASK) >> UART_C1_LOOPS_SHIFT)
+#define UART_BRD_C1_LOOPS(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT))
+
+/*! @brief Set the LOOPS field to a new value. */
+#define UART_WR_C1_LOOPS(base, value) (UART_RMW_C1(base, UART_C1_LOOPS_MASK, UART_C1_LOOPS(value)))
+#define UART_BWR_C1_LOOPS(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C2 - UART Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C2 - UART Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register can be read or written at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_C2 register
+ */
+/*@{*/
+#define UART_RD_C2(base)         (UART_C2_REG(base))
+#define UART_WR_C2(base, value)  (UART_C2_REG(base) = (value))
+#define UART_RMW_C2(base, mask, value) (UART_WR_C2(base, (UART_RD_C2(base) & ~(mask)) | (value)))
+#define UART_SET_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) |  (value)))
+#define UART_CLR_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) & ~(value)))
+#define UART_TOG_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C2 bitfields
+ */
+
+/*!
+ * @name Register UART_C2, field SBK[0] (RW)
+ *
+ * Toggling SBK sends one break character from the following: See Transmitting
+ * break characters for the number of logic 0s for the different configurations.
+ * Toggling implies clearing the SBK field before the break character has finished
+ * transmitting. As long as SBK is set, the transmitter continues to send
+ * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
+ * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
+ * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
+ * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
+ * C7816[ISO_7816E] is set.
+ *
+ * Values:
+ * - 0b0 - Normal transmitter operation.
+ * - 0b1 - Queue break characters to be sent.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_SBK field. */
+#define UART_RD_C2_SBK(base) ((UART_C2_REG(base) & UART_C2_SBK_MASK) >> UART_C2_SBK_SHIFT)
+#define UART_BRD_C2_SBK(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_SBK_SHIFT))
+
+/*! @brief Set the SBK field to a new value. */
+#define UART_WR_C2_SBK(base, value) (UART_RMW_C2(base, UART_C2_SBK_MASK, UART_C2_SBK(value)))
+#define UART_BWR_C2_SBK(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_SBK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RWU[1] (RW)
+ *
+ * This field can be set to place the UART receiver in a standby state. RWU
+ * automatically clears when an RWU event occurs, that is, an IDLE event when
+ * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
+ * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
+ * on idle) if the channel is currently not idle. This can be determined by
+ * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
+ * idle, it is possible that the UART will discard data. This is because the data
+ * must be received or a LIN break detected after an IDLE is detected before IDLE
+ * is allowed to reasserted.
+ *
+ * Values:
+ * - 0b0 - Normal operation.
+ * - 0b1 - RWU enables the wakeup function and inhibits further receiver
+ *     interrupt requests. Normally, hardware wakes the receiver by automatically
+ *     clearing RWU.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RWU field. */
+#define UART_RD_C2_RWU(base) ((UART_C2_REG(base) & UART_C2_RWU_MASK) >> UART_C2_RWU_SHIFT)
+#define UART_BRD_C2_RWU(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RWU_SHIFT))
+
+/*! @brief Set the RWU field to a new value. */
+#define UART_WR_C2_RWU(base, value) (UART_RMW_C2(base, UART_C2_RWU_MASK, UART_C2_RWU(value)))
+#define UART_BWR_C2_RWU(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RWU_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RE[2] (RW)
+ *
+ * Enables the UART receiver.
+ *
+ * Values:
+ * - 0b0 - Receiver off.
+ * - 0b1 - Receiver on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RE field. */
+#define UART_RD_C2_RE(base)  ((UART_C2_REG(base) & UART_C2_RE_MASK) >> UART_C2_RE_SHIFT)
+#define UART_BRD_C2_RE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RE_SHIFT))
+
+/*! @brief Set the RE field to a new value. */
+#define UART_WR_C2_RE(base, value) (UART_RMW_C2(base, UART_C2_RE_MASK, UART_C2_RE(value)))
+#define UART_BWR_C2_RE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TE[3] (RW)
+ *
+ * Enables the UART transmitter. TE can be used to queue an idle preamble by
+ * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
+ * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
+ * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
+ * additional characters are transmitted.
+ *
+ * Values:
+ * - 0b0 - Transmitter off.
+ * - 0b1 - Transmitter on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TE field. */
+#define UART_RD_C2_TE(base)  ((UART_C2_REG(base) & UART_C2_TE_MASK) >> UART_C2_TE_SHIFT)
+#define UART_BRD_C2_TE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TE_SHIFT))
+
+/*! @brief Set the TE field to a new value. */
+#define UART_WR_C2_TE(base, value) (UART_RMW_C2(base, UART_C2_TE_MASK, UART_C2_TE(value)))
+#define UART_BWR_C2_TE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field ILIE[4] (RW)
+ *
+ * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
+ * transfer requests based on the state of C5[ILDMAS].
+ *
+ * Values:
+ * - 0b0 - IDLE interrupt requests disabled. and DMA transfer
+ * - 0b1 - IDLE interrupt requests enabled. or DMA transfer
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_ILIE field. */
+#define UART_RD_C2_ILIE(base) ((UART_C2_REG(base) & UART_C2_ILIE_MASK) >> UART_C2_ILIE_SHIFT)
+#define UART_BRD_C2_ILIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT))
+
+/*! @brief Set the ILIE field to a new value. */
+#define UART_WR_C2_ILIE(base, value) (UART_RMW_C2(base, UART_C2_ILIE_MASK, UART_C2_ILIE(value)))
+#define UART_BWR_C2_ILIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RIE[5] (RW)
+ *
+ * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[RDMAS].
+ *
+ * Values:
+ * - 0b0 - RDRF interrupt and DMA transfer requests disabled.
+ * - 0b1 - RDRF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RIE field. */
+#define UART_RD_C2_RIE(base) ((UART_C2_REG(base) & UART_C2_RIE_MASK) >> UART_C2_RIE_SHIFT)
+#define UART_BRD_C2_RIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RIE_SHIFT))
+
+/*! @brief Set the RIE field to a new value. */
+#define UART_WR_C2_RIE(base, value) (UART_RMW_C2(base, UART_C2_RIE_MASK, UART_C2_RIE(value)))
+#define UART_BWR_C2_RIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TCIE[6] (RW)
+ *
+ * Enables the transmission complete flag, S1[TC], to generate interrupt
+ * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
+ * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
+ * written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0b0 - TC interrupt and DMA transfer requests disabled.
+ * - 0b1 - TC interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TCIE field. */
+#define UART_RD_C2_TCIE(base) ((UART_C2_REG(base) & UART_C2_TCIE_MASK) >> UART_C2_TCIE_SHIFT)
+#define UART_BRD_C2_TCIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT))
+
+/*! @brief Set the TCIE field to a new value. */
+#define UART_WR_C2_TCIE(base, value) (UART_RMW_C2(base, UART_C2_TCIE_MASK, UART_C2_TCIE(value)))
+#define UART_BWR_C2_TCIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TIE[7] (RW)
+ *
+ * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
+ * must be cleared, and D[D] must not be written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0b0 - TDRE interrupt and DMA transfer requests disabled.
+ * - 0b1 - TDRE interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TIE field. */
+#define UART_RD_C2_TIE(base) ((UART_C2_REG(base) & UART_C2_TIE_MASK) >> UART_C2_TIE_SHIFT)
+#define UART_BRD_C2_TIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define UART_WR_C2_TIE(base, value) (UART_RMW_C2(base, UART_C2_TIE_MASK, UART_C2_TIE(value)))
+#define UART_BWR_C2_TIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S1 - UART Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S1 - UART Status Register 1 (RO)
+ *
+ * Reset value: 0xC0U
+ *
+ * The S1 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. This register can also be polled by the MCU to check the
+ * status of its fields. To clear a flag, the status register should be read followed
+ * by a read or write to D register, depending on the interrupt flag type. Other
+ * instructions can be executed between the two steps as long the handling of
+ * I/O is not compromised, but the order of operations is important for flag
+ * clearing. When a flag is configured to trigger a DMA request, assertion of the
+ * associated DMA done signal from the DMA controller clears the flag. If the
+ * condition that results in the assertion of the flag, interrupt, or DMA request is not
+ * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
+ * reasserts. For example, if the DMA or interrupt service routine fails to write
+ * sufficient data to the transmit buffer to raise it above the watermark level, the
+ * flag reasserts and generates another interrupt or DMA request. Reading an
+ * empty data register to clear one of the flags of the S1 register causes the FIFO
+ * pointers to become misaligned. A receive FIFO flush reinitializes the
+ * pointers. A better way to prevent this situation is to always leave one byte in FIFO
+ * and this byte will be read eventually in clearing the flag bit.
+ */
+/*!
+ * @name Constants and macros for entire UART_S1 register
+ */
+/*@{*/
+#define UART_RD_S1(base)         (UART_S1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S1 bitfields
+ */
+
+/*!
+ * @name Register UART_S1, field PF[0] (RO)
+ *
+ * PF is set when PE is set and the parity of the received data does not match
+ * its parity bit. The PF is not set in the case of an overrun condition. When PF
+ * is set, it indicates only that a dataword was received with parity error since
+ * the last time it was cleared. There is no guarantee that the first dataword
+ * read from the receive buffer has a parity error or that there is only one
+ * dataword in the buffer that was received with a parity error, unless the receive
+ * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
+ * disabled, Within the receive buffer structure the received dataword is tagged
+ * if it is received with a parity error. This information is available by reading
+ * the ED register prior to reading the D register.
+ *
+ * Values:
+ * - 0b0 - No parity error detected since the last time this flag was cleared.
+ *     If the receive buffer has a depth greater than 1, then there may be data in
+ *     the receive buffer what was received with a parity error.
+ * - 0b1 - At least one dataword was received with a parity error since the last
+ *     time this flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_PF field. */
+#define UART_RD_S1_PF(base)  ((UART_S1_REG(base) & UART_S1_PF_MASK) >> UART_S1_PF_SHIFT)
+#define UART_BRD_S1_PF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_PF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field FE[1] (RO)
+ *
+ * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
+ * then FE will set when a logic 0 is accepted for either of the two stop bits.
+ * FE does not set in the case of an overrun or while the LIN break detect feature
+ * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
+ * cleared. To clear FE, read S1 with FE set and then read D. The last data in the
+ * receive buffer represents the data that was received with the frame error
+ * enabled. Framing errors are not supported when 7816E is set/enabled. However, if
+ * this flag is set, data is still not received in 7816 mode.
+ *
+ * Values:
+ * - 0b0 - No framing error detected.
+ * - 0b1 - Framing error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_FE field. */
+#define UART_RD_S1_FE(base)  ((UART_S1_REG(base) & UART_S1_FE_MASK) >> UART_S1_FE_SHIFT)
+#define UART_BRD_S1_FE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_FE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field NF[2] (RO)
+ *
+ * NF is set when the UART detects noise on the receiver input. NF does not
+ * become set in the case of an overrun or while the LIN break detect feature is
+ * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
+ * been received with noise since the last time it was cleared. There is no
+ * guarantee that the first dataword read from the receive buffer has noise or that there
+ * is only one dataword in the buffer that was received with noise unless the
+ * receive buffer has a depth of one. To clear NF, read S1 and then read D.
+ *
+ * Values:
+ * - 0b0 - No noise detected since the last time this flag was cleared. If the
+ *     receive buffer has a depth greater than 1 then there may be data in the
+ *     receiver buffer that was received with noise.
+ * - 0b1 - At least one dataword was received with noise detected since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_NF field. */
+#define UART_RD_S1_NF(base)  ((UART_S1_REG(base) & UART_S1_NF_MASK) >> UART_S1_NF_SHIFT)
+#define UART_BRD_S1_NF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_NF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field OR[3] (RO)
+ *
+ * OR is set when software fails to prevent the receive data register from
+ * overflowing with data. The OR bit is set immediately after the stop bit has been
+ * completely received for the dataword that overflows the buffer and all the other
+ * error flags (FE, NF, and PF) are prevented from setting. The data in the
+ * shift register is lost, but the data already in the UART data registers is not
+ * affected. If the OR flag is set, no data is stored in the data buffer even if
+ * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
+ * flags are blocked from asserting, that is, transition from an inactive to an
+ * active state. To clear OR, read S1 when OR is set and then read D. See
+ * functional description for more details regarding the operation of the OR bit.If
+ * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
+ * is not cleared before the next data character is received. In 7816 mode, it is
+ * possible to configure a NACK to be returned by programing C7816[ONACK].
+ *
+ * Values:
+ * - 0b0 - No overrun has occurred since the last time the flag was cleared.
+ * - 0b1 - Overrun has occurred or the overrun flag has not been cleared since
+ *     the last overrun occured.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_OR field. */
+#define UART_RD_S1_OR(base)  ((UART_S1_REG(base) & UART_S1_OR_MASK) >> UART_S1_OR_SHIFT)
+#define UART_BRD_S1_OR(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_OR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field IDLE[4] (RO)
+ *
+ * After the IDLE flag is cleared, a frame must be received (although not
+ * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
+ * break character must set the S2[LBKDIF] flag before an idle condition can set the
+ * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
+ * IDLE is set when either of the following appear on the receiver input: 10
+ * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
+ * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
+ * detection is not supported when 7816E is set/enabled and hence this flag is
+ * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
+ * flag if RWUID is set, else the IDLE flag does not become set.
+ *
+ * Values:
+ * - 0b0 - Receiver input is either active now or has never become active since
+ *     the IDLE flag was last cleared.
+ * - 0b1 - Receiver input has become idle or the flag has not been cleared since
+ *     it last asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_IDLE field. */
+#define UART_RD_S1_IDLE(base) ((UART_S1_REG(base) & UART_S1_IDLE_MASK) >> UART_S1_IDLE_SHIFT)
+#define UART_BRD_S1_IDLE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field RDRF[5] (RO)
+ *
+ * RDRF is set when the number of datawords in the receive buffer is equal to or
+ * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
+ * process of being received is not included in the count. To clear RDRF, read S1
+ * when RDRF is set and then read D. For more efficient interrupt and DMA
+ * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
+ * Then read S1 and the final data value, resulting in the clearing of the RDRF
+ * flag. Even if RDRF is set, data will continue to be received until an overrun
+ * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
+ * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
+ * buffer but over-write each other.
+ *
+ * Values:
+ * - 0b0 - The number of datawords in the receive buffer is less than the number
+ *     indicated by RXWATER.
+ * - 0b1 - The number of datawords in the receive buffer is equal to or greater
+ *     than the number indicated by RXWATER at some point in time since this flag
+ *     was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_RDRF field. */
+#define UART_RD_S1_RDRF(base) ((UART_S1_REG(base) & UART_S1_RDRF_MASK) >> UART_S1_RDRF_SHIFT)
+#define UART_BRD_S1_RDRF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_RDRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TC[6] (RO)
+ *
+ * TC is set when the transmit buffer is empty and no data, preamble, or break
+ * character is being transmitted. When TC is set, the transmit data output signal
+ * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
+ * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
+ * set after any NACK signal has been received, but prior to any corresponding
+ * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
+ * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
+ * in C2.
+ *
+ * Values:
+ * - 0b0 - Transmitter active (sending data, a preamble, or a break).
+ * - 0b1 - Transmitter idle (transmission activity complete).
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TC field. */
+#define UART_RD_S1_TC(base)  ((UART_S1_REG(base) & UART_S1_TC_MASK) >> UART_S1_TC_SHIFT)
+#define UART_BRD_S1_TC(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_TC_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TDRE[7] (RO)
+ *
+ * TDRE will set when the number of datawords in the transmit buffer (D and
+ * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
+ * character that is in the process of being transmitted is not included in the count.
+ * To clear TDRE, read S1 when TDRE is set and then write to the UART data
+ * register (D). For more efficient interrupt servicing, all data except the final value
+ * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
+ * before writing the final data value, resulting in the clearing of the TRDE
+ * flag. This is more efficient because the TDRE reasserts until the watermark has
+ * been exceeded. So, attempting to clear the TDRE with every write will be
+ * ineffective until sufficient data has been written.
+ *
+ * Values:
+ * - 0b0 - The amount of data in the transmit buffer is greater than the value
+ *     indicated by TWFIFO[TXWATER].
+ * - 0b1 - The amount of data in the transmit buffer is less than or equal to
+ *     the value indicated by TWFIFO[TXWATER] at some point in time since the flag
+ *     has been cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TDRE field. */
+#define UART_RD_S1_TDRE(base) ((UART_S1_REG(base) & UART_S1_TDRE_MASK) >> UART_S1_TDRE_SHIFT)
+#define UART_BRD_S1_TDRE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_TDRE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S2 - UART Status Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S2 - UART Status Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The S2 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. Also, this register can be polled by the MCU to check the
+ * status of these bits. This register can be read or written at any time, with the
+ * exception of the MSBF and RXINV bits, which should be changed by the user only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_S2 register
+ */
+/*@{*/
+#define UART_RD_S2(base)         (UART_S2_REG(base))
+#define UART_WR_S2(base, value)  (UART_S2_REG(base) = (value))
+#define UART_RMW_S2(base, mask, value) (UART_WR_S2(base, (UART_RD_S2(base) & ~(mask)) | (value)))
+#define UART_SET_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) |  (value)))
+#define UART_CLR_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) & ~(value)))
+#define UART_TOG_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S2 bitfields
+ */
+
+/*!
+ * @name Register UART_S2, field RAF[0] (RO)
+ *
+ * RAF is set when the UART receiver detects a logic 0 during the RT1 time
+ * period of the start bit search. RAF is cleared when the receiver detects an idle
+ * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
+ * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
+ * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
+ * to configure the guard time to 12. However, if a NACK is required to be
+ * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
+ * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
+ * prior to actually being inactive.
+ *
+ * Values:
+ * - 0b0 - UART receiver idle/inactive waiting for a start bit.
+ * - 0b1 - UART receiver active, RxD input not idle.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RAF field. */
+#define UART_RD_S2_RAF(base) ((UART_S2_REG(base) & UART_S2_RAF_MASK) >> UART_S2_RAF_SHIFT)
+#define UART_BRD_S2_RAF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RAF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field LBKDE[1] (RW)
+ *
+ * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
+ * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
+ * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
+ *
+ * Values:
+ * - 0b0 - Break character detection is disabled.
+ * - 0b1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
+ *     12 bits time if C1[M] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_LBKDE field. */
+#define UART_RD_S2_LBKDE(base) ((UART_S2_REG(base) & UART_S2_LBKDE_MASK) >> UART_S2_LBKDE_SHIFT)
+#define UART_BRD_S2_LBKDE(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDE_SHIFT))
+
+/*! @brief Set the LBKDE field to a new value. */
+#define UART_WR_S2_LBKDE(base, value) (UART_RMW_S2(base, (UART_S2_LBKDE_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_LBKDE(value)))
+#define UART_BWR_S2_LBKDE(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field BRK13[2] (RW)
+ *
+ * Determines whether the transmit break character is 10, 11, or 12 bits long,
+ * or 13 or 14 bits long. See for the length of the break character for the
+ * different configurations. The detection of a framing error is not affected by this
+ * field. Transmitting break characters
+ *
+ * Values:
+ * - 0b0 - Break character is 10, 11, or 12 bits long.
+ * - 0b1 - Break character is 13 or 14 bits long.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_BRK13 field. */
+#define UART_RD_S2_BRK13(base) ((UART_S2_REG(base) & UART_S2_BRK13_MASK) >> UART_S2_BRK13_SHIFT)
+#define UART_BRD_S2_BRK13(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT))
+
+/*! @brief Set the BRK13 field to a new value. */
+#define UART_WR_S2_BRK13(base, value) (UART_RMW_S2(base, (UART_S2_BRK13_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_BRK13(value)))
+#define UART_BWR_S2_BRK13(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RWUID[3] (RW)
+ *
+ * When RWU is set and WAKE is cleared, this field controls whether the idle
+ * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - S1[IDLE] is not set upon detection of an idle character.
+ * - 0b1 - S1[IDLE] is set upon detection of an idle character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RWUID field. */
+#define UART_RD_S2_RWUID(base) ((UART_S2_REG(base) & UART_S2_RWUID_MASK) >> UART_S2_RWUID_SHIFT)
+#define UART_BRD_S2_RWUID(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT))
+
+/*! @brief Set the RWUID field to a new value. */
+#define UART_WR_S2_RWUID(base, value) (UART_RMW_S2(base, (UART_S2_RWUID_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RWUID(value)))
+#define UART_BWR_S2_RWUID(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the received data input. In NRZ
+ * format, a one is represented by a mark and a zero is represented by a space for
+ * normal polarity, and the opposite for inverted polarity. In IrDA format, a
+ * zero is represented by short high pulse in the middle of a bit time remaining
+ * idle low for a one for normal polarity. A zero is represented by a short low
+ * pulse in the middle of a bit time remaining idle high for a one for inverted
+ * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
+ * enabled and an initial character is detected in T = 0 protocol mode. Setting
+ * RXINV inverts the RxD input for data bits, start and stop bits, break, and
+ * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
+ * are inverted.
+ *
+ * Values:
+ * - 0b0 - Receive data is not inverted.
+ * - 0b1 - Receive data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXINV field. */
+#define UART_RD_S2_RXINV(base) ((UART_S2_REG(base) & UART_S2_RXINV_MASK) >> UART_S2_RXINV_SHIFT)
+#define UART_BRD_S2_RXINV(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT))
+
+/*! @brief Set the RXINV field to a new value. */
+#define UART_WR_S2_RXINV(base, value) (UART_RMW_S2(base, (UART_S2_RXINV_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RXINV(value)))
+#define UART_BWR_S2_RXINV(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field MSBF[5] (RW)
+ *
+ * Setting this field reverses the order of the bits that are transmitted and
+ * received on the wire. This field does not affect the polarity of the bits, the
+ * location of the parity bit, or the location of the start or stop bits. This
+ * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
+ * an initial character is detected in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0b0 - LSB (bit0) is the first bit that is transmitted following the start
+ *     bit. Further, the first bit received after the start bit is identified as
+ *     bit0.
+ * - 0b1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted
+ *     following the start bit, depending on the setting of C1[M] and C1[PE]. Further,
+ *     the first bit received after the start bit is identified as bit8, bit7, or
+ *     bit6, depending on the setting of C1[M] and C1[PE].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_MSBF field. */
+#define UART_RD_S2_MSBF(base) ((UART_S2_REG(base) & UART_S2_MSBF_MASK) >> UART_S2_MSBF_SHIFT)
+#define UART_BRD_S2_MSBF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT))
+
+/*! @brief Set the MSBF field to a new value. */
+#define UART_WR_S2_MSBF(base, value) (UART_RMW_S2(base, (UART_S2_MSBF_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_MSBF(value)))
+#define UART_BWR_S2_MSBF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXEDGIF[6] (W1C)
+ *
+ * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
+ * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
+ * to it. See for additional details. RXEDGIF description The active edge is
+ * detected only in two wire mode and on receiving data coming from the RxD pin.
+ *
+ * Values:
+ * - 0b0 - No active edge on the receive pin has occurred.
+ * - 0b1 - An active edge on the receive pin has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXEDGIF field. */
+#define UART_RD_S2_RXEDGIF(base) ((UART_S2_REG(base) & UART_S2_RXEDGIF_MASK) >> UART_S2_RXEDGIF_SHIFT)
+#define UART_BRD_S2_RXEDGIF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT))
+
+/*! @brief Set the RXEDGIF field to a new value. */
+#define UART_WR_S2_RXEDGIF(base, value) (UART_RMW_S2(base, (UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RXEDGIF(value)))
+#define UART_BWR_S2_RXEDGIF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field LBKDIF[7] (W1C)
+ *
+ * LBKDIF is set when LBKDE is set and a LIN break character is detected on the
+ * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
+ * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
+ * last LIN break character. LBKDIF is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - No LIN break character detected.
+ * - 0b1 - LIN break character detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_LBKDIF field. */
+#define UART_RD_S2_LBKDIF(base) ((UART_S2_REG(base) & UART_S2_LBKDIF_MASK) >> UART_S2_LBKDIF_SHIFT)
+#define UART_BRD_S2_LBKDIF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDIF_SHIFT))
+
+/*! @brief Set the LBKDIF field to a new value. */
+#define UART_WR_S2_LBKDIF(base, value) (UART_RMW_S2(base, (UART_S2_LBKDIF_MASK | UART_S2_RXEDGIF_MASK), UART_S2_LBKDIF(value)))
+#define UART_BWR_S2_LBKDIF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDIF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C3 - UART Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C3 - UART Control Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_C3 register
+ */
+/*@{*/
+#define UART_RD_C3(base)         (UART_C3_REG(base))
+#define UART_WR_C3(base, value)  (UART_C3_REG(base) = (value))
+#define UART_RMW_C3(base, mask, value) (UART_WR_C3(base, (UART_RD_C3(base) & ~(mask)) | (value)))
+#define UART_SET_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) |  (value)))
+#define UART_CLR_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) & ~(value)))
+#define UART_TOG_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C3 bitfields
+ */
+
+/*!
+ * @name Register UART_C3, field PEIE[0] (RW)
+ *
+ * Enables the parity error flag, S1[PF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - PF interrupt requests are disabled.
+ * - 0b1 - PF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_PEIE field. */
+#define UART_RD_C3_PEIE(base) ((UART_C3_REG(base) & UART_C3_PEIE_MASK) >> UART_C3_PEIE_SHIFT)
+#define UART_BRD_C3_PEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT))
+
+/*! @brief Set the PEIE field to a new value. */
+#define UART_WR_C3_PEIE(base, value) (UART_RMW_C3(base, UART_C3_PEIE_MASK, UART_C3_PEIE(value)))
+#define UART_BWR_C3_PEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field FEIE[1] (RW)
+ *
+ * Enables the framing error flag, S1[FE], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - FE interrupt requests are disabled.
+ * - 0b1 - FE interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_FEIE field. */
+#define UART_RD_C3_FEIE(base) ((UART_C3_REG(base) & UART_C3_FEIE_MASK) >> UART_C3_FEIE_SHIFT)
+#define UART_BRD_C3_FEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define UART_WR_C3_FEIE(base, value) (UART_RMW_C3(base, UART_C3_FEIE_MASK, UART_C3_FEIE(value)))
+#define UART_BWR_C3_FEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field NEIE[2] (RW)
+ *
+ * Enables the noise flag, S1[NF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - NF interrupt requests are disabled.
+ * - 0b1 - NF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_NEIE field. */
+#define UART_RD_C3_NEIE(base) ((UART_C3_REG(base) & UART_C3_NEIE_MASK) >> UART_C3_NEIE_SHIFT)
+#define UART_BRD_C3_NEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT))
+
+/*! @brief Set the NEIE field to a new value. */
+#define UART_WR_C3_NEIE(base, value) (UART_RMW_C3(base, UART_C3_NEIE_MASK, UART_C3_NEIE(value)))
+#define UART_BWR_C3_NEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field ORIE[3] (RW)
+ *
+ * Enables the overrun error flag, S1[OR], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - OR interrupts are disabled.
+ * - 0b1 - OR interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_ORIE field. */
+#define UART_RD_C3_ORIE(base) ((UART_C3_REG(base) & UART_C3_ORIE_MASK) >> UART_C3_ORIE_SHIFT)
+#define UART_BRD_C3_ORIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT))
+
+/*! @brief Set the ORIE field to a new value. */
+#define UART_WR_C3_ORIE(base, value) (UART_RMW_C3(base, UART_C3_ORIE_MASK, UART_C3_ORIE(value)))
+#define UART_BWR_C3_ORIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the transmitted data output. In
+ * NRZ format, a one is represented by a mark and a zero is represented by a space
+ * for normal polarity, and the opposite for inverted polarity. In IrDA format,
+ * a zero is represented by short high pulse in the middle of a bit time
+ * remaining idle low for a one for normal polarity, and a zero is represented by short
+ * low pulse in the middle of a bit time remaining idle high for a one for
+ * inverted polarity. This field is automatically set when C7816[INIT] and
+ * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
+ * Setting TXINV inverts all transmitted values, including idle, break, start, and
+ * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
+ * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
+ * the transmitted data bits and parity bit are inverted.
+ *
+ * Values:
+ * - 0b0 - Transmit data is not inverted.
+ * - 0b1 - Transmit data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXINV field. */
+#define UART_RD_C3_TXINV(base) ((UART_C3_REG(base) & UART_C3_TXINV_MASK) >> UART_C3_TXINV_SHIFT)
+#define UART_BRD_C3_TXINV(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT))
+
+/*! @brief Set the TXINV field to a new value. */
+#define UART_WR_C3_TXINV(base, value) (UART_RMW_C3(base, UART_C3_TXINV_MASK, UART_C3_TXINV(value)))
+#define UART_BWR_C3_TXINV(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXDIR[5] (RW)
+ *
+ * Determines whether the TXD pin is used as an input or output in the
+ * single-wire mode of operation. This field is relevant only to the single wire mode.
+ * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
+ * automatically cleared after the requested block is transmitted. This condition is
+ * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
+ * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
+ * being transmitted, the hardware automatically overrides this field as needed. In
+ * this situation, TXDIR does not reflect the temporary state associated with
+ * the NACK.
+ *
+ * Values:
+ * - 0b0 - TXD pin is an input in single wire mode.
+ * - 0b1 - TXD pin is an output in single wire mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXDIR field. */
+#define UART_RD_C3_TXDIR(base) ((UART_C3_REG(base) & UART_C3_TXDIR_MASK) >> UART_C3_TXDIR_SHIFT)
+#define UART_BRD_C3_TXDIR(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT))
+
+/*! @brief Set the TXDIR field to a new value. */
+#define UART_WR_C3_TXDIR(base, value) (UART_RMW_C3(base, UART_C3_TXDIR_MASK, UART_C3_TXDIR(value)))
+#define UART_BWR_C3_TXDIR(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field T8[6] (RW)
+ *
+ * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
+ * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
+ * same as in the previous transmission, T8 does not have to be rewritten. The same
+ * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
+ * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
+ * the remaining data.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_T8 field. */
+#define UART_RD_C3_T8(base)  ((UART_C3_REG(base) & UART_C3_T8_MASK) >> UART_C3_T8_SHIFT)
+#define UART_BRD_C3_T8(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_T8_SHIFT))
+
+/*! @brief Set the T8 field to a new value. */
+#define UART_WR_C3_T8(base, value) (UART_RMW_C3(base, UART_C3_T8_MASK, UART_C3_T8(value)))
+#define UART_BWR_C3_T8(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_T8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field R8[7] (RO)
+ *
+ * R8 is the ninth data bit received when the UART is configured for 9-bit data
+ * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
+ * current data value in the UARTx_D register. To read the 9th bit, read the
+ * value of UARTx_C3[R8], then read the UARTx_D register.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_R8 field. */
+#define UART_RD_C3_R8(base)  ((UART_C3_REG(base) & UART_C3_R8_MASK) >> UART_C3_R8_SHIFT)
+#define UART_BRD_C3_R8(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_R8_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_D - UART Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_D - UART Data Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is actually two separate registers. Reads return the contents
+ * of the read-only receive data register and writes go to the write-only transmit
+ * data register. In 8-bit or 9-bit data format, only UART data register (D)
+ * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
+ * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
+ * register, only if the ninth bit of data needs to be captured. Similarly, the
+ * ED register needs to be read, prior to the D register, only if the additional
+ * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
+ * bit cleared) if the parity is enabled, you get seven data bits and one parity
+ * bit. That one parity bit is loaded into the D register. So, for the data bits,
+ * mask off the parity bit from the value you read out of this register. When
+ * transmitting in 9-bit data format and using 8-bit write instructions, write first
+ * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
+ * C3[T8] stores the data in a temporary register. If D register is written first,
+ * and then the new data on data bus is stored in D, the temporary value written by
+ * the last write to C3[T8] gets stored in the C3[T8] register.
+ */
+/*!
+ * @name Constants and macros for entire UART_D register
+ */
+/*@{*/
+#define UART_RD_D(base)          (UART_D_REG(base))
+#define UART_WR_D(base, value)   (UART_D_REG(base) = (value))
+#define UART_RMW_D(base, mask, value) (UART_WR_D(base, (UART_RD_D(base) & ~(mask)) | (value)))
+#define UART_SET_D(base, value)  (UART_WR_D(base, UART_RD_D(base) |  (value)))
+#define UART_CLR_D(base, value)  (UART_WR_D(base, UART_RD_D(base) & ~(value)))
+#define UART_TOG_D(base, value)  (UART_WR_D(base, UART_RD_D(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA1 - UART Match Address Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA1 - UART Match Address Registers 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MA1 and MA2 registers are compared to input data addresses when the most
+ * significant bit is set and the associated C4[MAEN] field is set. If a match
+ * occurs, the following data is transferred to the data register. If a match
+ * fails, the following data is discarded. These registers can be read and written at
+ * anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA1 register
+ */
+/*@{*/
+#define UART_RD_MA1(base)        (UART_MA1_REG(base))
+#define UART_WR_MA1(base, value) (UART_MA1_REG(base) = (value))
+#define UART_RMW_MA1(base, mask, value) (UART_WR_MA1(base, (UART_RD_MA1(base) & ~(mask)) | (value)))
+#define UART_SET_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) |  (value)))
+#define UART_CLR_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) & ~(value)))
+#define UART_TOG_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA2 - UART Match Address Registers 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA2 - UART Match Address Registers 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * These registers can be read and written at anytime. The MA1 and MA2 registers
+ * are compared to input data addresses when the most significant bit is set and
+ * the associated C4[MAEN] field is set. If a match occurs, the following data
+ * is transferred to the data register. If a match fails, the following data is
+ * discarded.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA2 register
+ */
+/*@{*/
+#define UART_RD_MA2(base)        (UART_MA2_REG(base))
+#define UART_WR_MA2(base, value) (UART_MA2_REG(base) = (value))
+#define UART_RMW_MA2(base, mask, value) (UART_WR_MA2(base, (UART_RD_MA2(base) & ~(mask)) | (value)))
+#define UART_SET_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) |  (value)))
+#define UART_CLR_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) & ~(value)))
+#define UART_TOG_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C4 - UART Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C4 - UART Control Register 4 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C4 register
+ */
+/*@{*/
+#define UART_RD_C4(base)         (UART_C4_REG(base))
+#define UART_WR_C4(base, value)  (UART_C4_REG(base) = (value))
+#define UART_RMW_C4(base, mask, value) (UART_WR_C4(base, (UART_RD_C4(base) & ~(mask)) | (value)))
+#define UART_SET_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) |  (value)))
+#define UART_CLR_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) & ~(value)))
+#define UART_TOG_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C4 bitfields
+ */
+
+/*!
+ * @name Register UART_C4, field BRFA[4:0] (RW)
+ *
+ * This bit field is used to add more timing resolution to the average baud
+ * frequency, in increments of 1/32. See Baud rate generation for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_BRFA field. */
+#define UART_RD_C4_BRFA(base) ((UART_C4_REG(base) & UART_C4_BRFA_MASK) >> UART_C4_BRFA_SHIFT)
+#define UART_BRD_C4_BRFA(base) (UART_RD_C4_BRFA(base))
+
+/*! @brief Set the BRFA field to a new value. */
+#define UART_WR_C4_BRFA(base, value) (UART_RMW_C4(base, UART_C4_BRFA_MASK, UART_C4_BRFA(value)))
+#define UART_BWR_C4_BRFA(base, value) (UART_WR_C4_BRFA(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field M10[5] (RW)
+ *
+ * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
+ * This tenth bit is generated and interpreted as a parity bit. The M10 field
+ * does not affect the LIN send or detect break behavior. If M10 is set, then both
+ * C1[M] and C1[PE] must also be set. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
+ *
+ * Values:
+ * - 0b0 - The parity bit is the ninth bit in the serial transmission.
+ * - 0b1 - The parity bit is the tenth bit in the serial transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_M10 field. */
+#define UART_RD_C4_M10(base) ((UART_C4_REG(base) & UART_C4_M10_MASK) >> UART_C4_M10_SHIFT)
+#define UART_BRD_C4_M10(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_M10_SHIFT))
+
+/*! @brief Set the M10 field to a new value. */
+#define UART_WR_C4_M10(base, value) (UART_RMW_C4(base, UART_C4_M10_MASK, UART_C4_M10(value)))
+#define UART_BWR_C4_M10(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_M10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN2[6] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0b0 - All data received is transferred to the data buffer if MAEN1 is
+ *     cleared.
+ * - 0b1 - All data received with the most significant bit cleared, is
+ *     discarded. All data received with the most significant bit set, is compared with
+ *     contents of MA2 register. If no match occurs, the data is discarded. If a
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN2 field. */
+#define UART_RD_C4_MAEN2(base) ((UART_C4_REG(base) & UART_C4_MAEN2_MASK) >> UART_C4_MAEN2_SHIFT)
+#define UART_BRD_C4_MAEN2(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT))
+
+/*! @brief Set the MAEN2 field to a new value. */
+#define UART_WR_C4_MAEN2(base, value) (UART_RMW_C4(base, UART_C4_MAEN2_MASK, UART_C4_MAEN2(value)))
+#define UART_BWR_C4_MAEN2(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN1[7] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0b0 - All data received is transferred to the data buffer if MAEN2 is
+ *     cleared.
+ * - 0b1 - All data received with the most significant bit cleared, is
+ *     discarded. All data received with the most significant bit set, is compared with
+ *     contents of MA1 register. If no match occurs, the data is discarded. If
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN1 field. */
+#define UART_RD_C4_MAEN1(base) ((UART_C4_REG(base) & UART_C4_MAEN1_MASK) >> UART_C4_MAEN1_SHIFT)
+#define UART_BRD_C4_MAEN1(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT))
+
+/*! @brief Set the MAEN1 field to a new value. */
+#define UART_WR_C4_MAEN1(base, value) (UART_RMW_C4(base, UART_C4_MAEN1_MASK, UART_C4_MAEN1(value)))
+#define UART_BWR_C4_MAEN1(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C5 - UART Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C5 - UART Control Register 5 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C5 register
+ */
+/*@{*/
+#define UART_RD_C5(base)         (UART_C5_REG(base))
+#define UART_WR_C5(base, value)  (UART_C5_REG(base) = (value))
+#define UART_RMW_C5(base, mask, value) (UART_WR_C5(base, (UART_RD_C5(base) & ~(mask)) | (value)))
+#define UART_SET_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) |  (value)))
+#define UART_CLR_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) & ~(value)))
+#define UART_TOG_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C5 bitfields
+ */
+
+/*!
+ * @name Register UART_C5, field LBKDDMAS[3] (RW)
+ *
+ * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
+ * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
+ * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
+ * of the state of LBKDDMAS.
+ *
+ * Values:
+ * - 0b0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
+ *     asserted to request an interrupt service.
+ * - 0b1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal
+ *     is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_LBKDDMAS field. */
+#define UART_RD_C5_LBKDDMAS(base) ((UART_C5_REG(base) & UART_C5_LBKDDMAS_MASK) >> UART_C5_LBKDDMAS_SHIFT)
+#define UART_BRD_C5_LBKDDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_LBKDDMAS_SHIFT))
+
+/*! @brief Set the LBKDDMAS field to a new value. */
+#define UART_WR_C5_LBKDDMAS(base, value) (UART_RMW_C5(base, UART_C5_LBKDDMAS_MASK, UART_C5_LBKDDMAS(value)))
+#define UART_BWR_C5_LBKDDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_LBKDDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field ILDMAS[4] (RW)
+ *
+ * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
+ * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
+ * DMA and IDLE interrupt request signals are not asserted, regardless of the state
+ * of ILDMAS.
+ *
+ * Values:
+ * - 0b0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal
+ *     is asserted to request an interrupt service.
+ * - 0b1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_ILDMAS field. */
+#define UART_RD_C5_ILDMAS(base) ((UART_C5_REG(base) & UART_C5_ILDMAS_MASK) >> UART_C5_ILDMAS_SHIFT)
+#define UART_BRD_C5_ILDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_ILDMAS_SHIFT))
+
+/*! @brief Set the ILDMAS field to a new value. */
+#define UART_WR_C5_ILDMAS(base, value) (UART_RMW_C5(base, UART_C5_ILDMAS_MASK, UART_C5_ILDMAS(value)))
+#define UART_BWR_C5_ILDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_ILDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field RDMAS[5] (RW)
+ *
+ * Configures the receiver data register full flag, S1[RDRF], to generate
+ * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
+ * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
+ * regardless of the state of RDMAS.
+ *
+ * Values:
+ * - 0b0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
+ *     asserted to request an interrupt service.
+ * - 0b1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_RDMAS field. */
+#define UART_RD_C5_RDMAS(base) ((UART_C5_REG(base) & UART_C5_RDMAS_MASK) >> UART_C5_RDMAS_SHIFT)
+#define UART_BRD_C5_RDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT))
+
+/*! @brief Set the RDMAS field to a new value. */
+#define UART_WR_C5_RDMAS(base, value) (UART_RMW_C5(base, UART_C5_RDMAS_MASK, UART_C5_RDMAS(value)))
+#define UART_BWR_C5_RDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TCDMAS[6] (RW)
+ *
+ * Configures the transmission complete flag, S1[TC], to generate interrupt or
+ * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
+ * interrupt request signals are not asserted when the S1[TC] flag is set, regardless
+ * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
+ * must be cleared, and D must not be written unless a DMA request is being serviced.
+ *
+ * Values:
+ * - 0b0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt
+ *     request signal is asserted to request an interrupt service.
+ * - 0b1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TCDMAS field. */
+#define UART_RD_C5_TCDMAS(base) ((UART_C5_REG(base) & UART_C5_TCDMAS_MASK) >> UART_C5_TCDMAS_SHIFT)
+#define UART_BRD_C5_TCDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TCDMAS_SHIFT))
+
+/*! @brief Set the TCDMAS field to a new value. */
+#define UART_WR_C5_TCDMAS(base, value) (UART_RMW_C5(base, UART_C5_TCDMAS_MASK, UART_C5_TCDMAS(value)))
+#define UART_BWR_C5_TCDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TCDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TDMAS[7] (RW)
+ *
+ * Configures the transmit data register empty flag, S1[TDRE], to generate
+ * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
+ * TDRE interrupt request signals are not asserted when the TDRE flag is set,
+ * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
+ * must be cleared, and D must not be written unless a DMA request is being
+ * serviced.
+ *
+ * Values:
+ * - 0b0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
+ *     request signal is asserted to request interrupt service.
+ * - 0b1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TDMAS field. */
+#define UART_RD_C5_TDMAS(base) ((UART_C5_REG(base) & UART_C5_TDMAS_MASK) >> UART_C5_TDMAS_SHIFT)
+#define UART_BRD_C5_TDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT))
+
+/*! @brief Set the TDMAS field to a new value. */
+#define UART_WR_C5_TDMAS(base, value) (UART_RMW_C5(base, UART_C5_TDMAS_MASK, UART_C5_TDMAS(value)))
+#define UART_BWR_C5_TDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ED - UART Extended Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ED - UART Extended Data Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains additional information flags that are stored with a
+ * received dataword. This register may be read at any time but contains valid data
+ * only if there is a dataword in the receive FIFO. The data contained in this
+ * register represents additional information regarding the conditions on which a
+ * dataword was received. The importance of this data varies with the
+ * application, and in some cases maybe completely optional. These fields automatically
+ * update to reflect the conditions of the next dataword whenever D is read. If
+ * S1[NF] and S1[PF] have not been set since the last time the receive buffer was
+ * empty, the NOISY and PARITYE fields will be zero.
+ */
+/*!
+ * @name Constants and macros for entire UART_ED register
+ */
+/*@{*/
+#define UART_RD_ED(base)         (UART_ED_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ED bitfields
+ */
+
+/*!
+ * @name Register UART_ED, field PARITYE[6] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with a
+ * parity error.
+ *
+ * Values:
+ * - 0b0 - The dataword was received without a parity error.
+ * - 0b1 - The dataword was received with a parity error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ED_PARITYE field. */
+#define UART_RD_ED_PARITYE(base) ((UART_ED_REG(base) & UART_ED_PARITYE_MASK) >> UART_ED_PARITYE_SHIFT)
+#define UART_BRD_ED_PARITYE(base) (BITBAND_ACCESS8(&UART_ED_REG(base), UART_ED_PARITYE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_ED, field NOISY[7] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with
+ * noise.
+ *
+ * Values:
+ * - 0b0 - The dataword was received without noise.
+ * - 0b1 - The data was received with noise.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ED_NOISY field. */
+#define UART_RD_ED_NOISY(base) ((UART_ED_REG(base) & UART_ED_NOISY_MASK) >> UART_ED_NOISY_SHIFT)
+#define UART_BRD_ED_NOISY(base) (BITBAND_ACCESS8(&UART_ED_REG(base), UART_ED_NOISY_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MODEM - UART Modem Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MODEM - UART Modem Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MODEM register controls options for setting the modem configuration.
+ * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
+ * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
+ * ISO-7816 protocol does not use the RTS and CTS signals.
+ */
+/*!
+ * @name Constants and macros for entire UART_MODEM register
+ */
+/*@{*/
+#define UART_RD_MODEM(base)      (UART_MODEM_REG(base))
+#define UART_WR_MODEM(base, value) (UART_MODEM_REG(base) = (value))
+#define UART_RMW_MODEM(base, mask, value) (UART_WR_MODEM(base, (UART_RD_MODEM(base) & ~(mask)) | (value)))
+#define UART_SET_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) |  (value)))
+#define UART_CLR_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) & ~(value)))
+#define UART_TOG_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_MODEM bitfields
+ */
+
+/*!
+ * @name Register UART_MODEM, field TXCTSE[0] (RW)
+ *
+ * TXCTSE controls the operation of the transmitter. TXCTSE can be set
+ * independently from the state of TXRTSE and RXRTSE.
+ *
+ * Values:
+ * - 0b0 - CTS has no effect on the transmitter.
+ * - 0b1 - Enables clear-to-send operation. The transmitter checks the state of
+ *     CTS each time it is ready to send a character. If CTS is asserted, the
+ *     character is sent. If CTS is deasserted, the signal TXD remains in the mark
+ *     state and transmission is delayed until CTS is asserted. Changes in CTS as
+ *     a character is being sent do not affect its transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXCTSE field. */
+#define UART_RD_MODEM_TXCTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_TXCTSE_MASK) >> UART_MODEM_TXCTSE_SHIFT)
+#define UART_BRD_MODEM_TXCTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXCTSE_SHIFT))
+
+/*! @brief Set the TXCTSE field to a new value. */
+#define UART_WR_MODEM_TXCTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXCTSE_MASK, UART_MODEM_TXCTSE(value)))
+#define UART_BWR_MODEM_TXCTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXCTSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field TXRTSE[1] (RW)
+ *
+ * Controls RTS before and after a transmission.
+ *
+ * Values:
+ * - 0b0 - The transmitter has no effect on RTS.
+ * - 0b1 - When a character is placed into an empty transmitter data buffer ,
+ *     RTS asserts one bit time before the start bit is transmitted. RTS deasserts
+ *     one bit time after all characters in the transmitter data buffer and shift
+ *     register are completely sent, including the last stop bit. (FIFO) (FIFO)
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXRTSE field. */
+#define UART_RD_MODEM_TXRTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_TXRTSE_MASK) >> UART_MODEM_TXRTSE_SHIFT)
+#define UART_BRD_MODEM_TXRTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSE_SHIFT))
+
+/*! @brief Set the TXRTSE field to a new value. */
+#define UART_WR_MODEM_TXRTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXRTSE_MASK, UART_MODEM_TXRTSE(value)))
+#define UART_BWR_MODEM_TXRTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field TXRTSPOL[2] (RW)
+ *
+ * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
+ * polarity of the receiver RTS. RTS will remain negated in the active low state
+ * unless TXRTSE is set.
+ *
+ * Values:
+ * - 0b0 - Transmitter RTS is active low.
+ * - 0b1 - Transmitter RTS is active high.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXRTSPOL field. */
+#define UART_RD_MODEM_TXRTSPOL(base) ((UART_MODEM_REG(base) & UART_MODEM_TXRTSPOL_MASK) >> UART_MODEM_TXRTSPOL_SHIFT)
+#define UART_BRD_MODEM_TXRTSPOL(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSPOL_SHIFT))
+
+/*! @brief Set the TXRTSPOL field to a new value. */
+#define UART_WR_MODEM_TXRTSPOL(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXRTSPOL_MASK, UART_MODEM_TXRTSPOL(value)))
+#define UART_BWR_MODEM_TXRTSPOL(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field RXRTSE[3] (RW)
+ *
+ * Allows the RTS output to control the CTS input of the transmitting device to
+ * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
+ *
+ * Values:
+ * - 0b0 - The receiver has no effect on RTS.
+ * - 0b1 - RTS is deasserted if the number of characters in the receiver data
+ *     register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
+ *     when the number of characters in the receiver data register (FIFO) is
+ *     less than RWFIFO[RXWATER].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_RXRTSE field. */
+#define UART_RD_MODEM_RXRTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_RXRTSE_MASK) >> UART_MODEM_RXRTSE_SHIFT)
+#define UART_BRD_MODEM_RXRTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_RXRTSE_SHIFT))
+
+/*! @brief Set the RXRTSE field to a new value. */
+#define UART_WR_MODEM_RXRTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_RXRTSE_MASK, UART_MODEM_RXRTSE(value)))
+#define UART_BWR_MODEM_RXRTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_RXRTSE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IR - UART Infrared Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IR - UART Infrared Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IR register controls options for setting the infrared configuration.
+ */
+/*!
+ * @name Constants and macros for entire UART_IR register
+ */
+/*@{*/
+#define UART_RD_IR(base)         (UART_IR_REG(base))
+#define UART_WR_IR(base, value)  (UART_IR_REG(base) = (value))
+#define UART_RMW_IR(base, mask, value) (UART_WR_IR(base, (UART_RD_IR(base) & ~(mask)) | (value)))
+#define UART_SET_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) |  (value)))
+#define UART_CLR_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) & ~(value)))
+#define UART_TOG_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IR bitfields
+ */
+
+/*!
+ * @name Register UART_IR, field TNP[1:0] (RW)
+ *
+ * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
+ *
+ * Values:
+ * - 0b00 - 3/16.
+ * - 0b01 - 1/16.
+ * - 0b10 - 1/32.
+ * - 0b11 - 1/4.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IR_TNP field. */
+#define UART_RD_IR_TNP(base) ((UART_IR_REG(base) & UART_IR_TNP_MASK) >> UART_IR_TNP_SHIFT)
+#define UART_BRD_IR_TNP(base) (UART_RD_IR_TNP(base))
+
+/*! @brief Set the TNP field to a new value. */
+#define UART_WR_IR_TNP(base, value) (UART_RMW_IR(base, UART_IR_TNP_MASK, UART_IR_TNP(value)))
+#define UART_BWR_IR_TNP(base, value) (UART_WR_IR_TNP(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_IR, field IREN[2] (RW)
+ *
+ * Enables/disables the infrared modulation/demodulation.
+ *
+ * Values:
+ * - 0b0 - IR disabled.
+ * - 0b1 - IR enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IR_IREN field. */
+#define UART_RD_IR_IREN(base) ((UART_IR_REG(base) & UART_IR_IREN_MASK) >> UART_IR_IREN_SHIFT)
+#define UART_BRD_IR_IREN(base) (BITBAND_ACCESS8(&UART_IR_REG(base), UART_IR_IREN_SHIFT))
+
+/*! @brief Set the IREN field to a new value. */
+#define UART_WR_IR_IREN(base, value) (UART_RMW_IR(base, UART_IR_IREN_MASK, UART_IR_IREN(value)))
+#define UART_BWR_IR_IREN(base, value) (BITBAND_ACCESS8(&UART_IR_REG(base), UART_IR_IREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_PFIFO - UART FIFO Parameters
+ ******************************************************************************/
+
+/*!
+ * @brief UART_PFIFO - UART FIFO Parameters (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability for the programmer to turn on and off FIFO
+ * functionality. It also provides the size of the FIFO that has been
+ * implemented. This register may be read at any time. This register must be written only
+ * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
+ * empty.
+ */
+/*!
+ * @name Constants and macros for entire UART_PFIFO register
+ */
+/*@{*/
+#define UART_RD_PFIFO(base)      (UART_PFIFO_REG(base))
+#define UART_WR_PFIFO(base, value) (UART_PFIFO_REG(base) = (value))
+#define UART_RMW_PFIFO(base, mask, value) (UART_WR_PFIFO(base, (UART_RD_PFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) |  (value)))
+#define UART_CLR_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) & ~(value)))
+#define UART_TOG_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_PFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
+ *
+ * The maximum number of receive datawords that can be stored in the receive
+ * buffer before an overrun occurs. This field is read only.
+ *
+ * Values:
+ * - 0b000 - Receive FIFO/Buffer depth = 1 dataword.
+ * - 0b001 - Receive FIFO/Buffer depth = 4 datawords.
+ * - 0b010 - Receive FIFO/Buffer depth = 8 datawords.
+ * - 0b011 - Receive FIFO/Buffer depth = 16 datawords.
+ * - 0b100 - Receive FIFO/Buffer depth = 32 datawords.
+ * - 0b101 - Receive FIFO/Buffer depth = 64 datawords.
+ * - 0b110 - Receive FIFO/Buffer depth = 128 datawords.
+ * - 0b111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. */
+#define UART_RD_PFIFO_RXFIFOSIZE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_RXFIFOSIZE_MASK) >> UART_PFIFO_RXFIFOSIZE_SHIFT)
+#define UART_BRD_PFIFO_RXFIFOSIZE(base) (UART_RD_PFIFO_RXFIFOSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field RXFE[3] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the receive buffer is
+ * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
+ * If this field is not set, the receive buffer operates as a FIFO of depth one
+ * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
+ * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
+ * commands must be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0b0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
+ * - 0b1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_RXFE field. */
+#define UART_RD_PFIFO_RXFE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_RXFE_MASK) >> UART_PFIFO_RXFE_SHIFT)
+#define UART_BRD_PFIFO_RXFE(base) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_RXFE_SHIFT))
+
+/*! @brief Set the RXFE field to a new value. */
+#define UART_WR_PFIFO_RXFE(base, value) (UART_RMW_PFIFO(base, UART_PFIFO_RXFE_MASK, UART_PFIFO_RXFE(value)))
+#define UART_BWR_PFIFO_RXFE(base, value) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_RXFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
+ *
+ * The maximum number of transmit datawords that can be stored in the transmit
+ * buffer. This field is read only.
+ *
+ * Values:
+ * - 0b000 - Transmit FIFO/Buffer depth = 1 dataword.
+ * - 0b001 - Transmit FIFO/Buffer depth = 4 datawords.
+ * - 0b010 - Transmit FIFO/Buffer depth = 8 datawords.
+ * - 0b011 - Transmit FIFO/Buffer depth = 16 datawords.
+ * - 0b100 - Transmit FIFO/Buffer depth = 32 datawords.
+ * - 0b101 - Transmit FIFO/Buffer depth = 64 datawords.
+ * - 0b110 - Transmit FIFO/Buffer depth = 128 datawords.
+ * - 0b111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. */
+#define UART_RD_PFIFO_TXFIFOSIZE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_TXFIFOSIZE_MASK) >> UART_PFIFO_TXFIFOSIZE_SHIFT)
+#define UART_BRD_PFIFO_TXFIFOSIZE(base) (UART_RD_PFIFO_TXFIFOSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field TXFE[7] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the transmit buffer
+ * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
+ * field is not set, the transmit buffer operates as a FIFO of depth one dataword
+ * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
+ * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
+ * be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0b0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
+ * - 0b1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_TXFE field. */
+#define UART_RD_PFIFO_TXFE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_TXFE_MASK) >> UART_PFIFO_TXFE_SHIFT)
+#define UART_BRD_PFIFO_TXFE(base) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_TXFE_SHIFT))
+
+/*! @brief Set the TXFE field to a new value. */
+#define UART_WR_PFIFO_TXFE(base, value) (UART_RMW_PFIFO(base, UART_PFIFO_TXFE_MASK, UART_PFIFO_TXFE(value)))
+#define UART_BWR_PFIFO_TXFE(base, value) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_TXFE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_CFIFO - UART FIFO Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_CFIFO - UART FIFO Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to program various control fields for FIFO
+ * operation. This register may be read or written at any time. Note that
+ * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
+ * to prevent unintended/unpredictable behavior. Therefore, it is recommended that
+ * TE and RE be cleared prior to flushing the corresponding FIFO.
+ */
+/*!
+ * @name Constants and macros for entire UART_CFIFO register
+ */
+/*@{*/
+#define UART_RD_CFIFO(base)      (UART_CFIFO_REG(base))
+#define UART_WR_CFIFO(base, value) (UART_CFIFO_REG(base) = (value))
+#define UART_RMW_CFIFO(base, mask, value) (UART_WR_CFIFO(base, (UART_RD_CFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) |  (value)))
+#define UART_CLR_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) & ~(value)))
+#define UART_TOG_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_CFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_CFIFO, field RXUFE[0] (RW)
+ *
+ * When this field is set, the RXUF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - RXUF flag does not generate an interrupt to the host.
+ * - 0b1 - RXUF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_RXUFE field. */
+#define UART_RD_CFIFO_RXUFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_RXUFE_MASK) >> UART_CFIFO_RXUFE_SHIFT)
+#define UART_BRD_CFIFO_RXUFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXUFE_SHIFT))
+
+/*! @brief Set the RXUFE field to a new value. */
+#define UART_WR_CFIFO_RXUFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXUFE_MASK, UART_CFIFO_RXUFE(value)))
+#define UART_BWR_CFIFO_RXUFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXUFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field TXOFE[1] (RW)
+ *
+ * When this field is set, the TXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - TXOF flag does not generate an interrupt to the host.
+ * - 0b1 - TXOF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_TXOFE field. */
+#define UART_RD_CFIFO_TXOFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_TXOFE_MASK) >> UART_CFIFO_TXOFE_SHIFT)
+#define UART_BRD_CFIFO_TXOFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXOFE_SHIFT))
+
+/*! @brief Set the TXOFE field to a new value. */
+#define UART_WR_CFIFO_TXOFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_TXOFE_MASK, UART_CFIFO_TXOFE(value)))
+#define UART_BWR_CFIFO_TXOFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXOFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field RXOFE[2] (RW)
+ *
+ * When this field is set, the RXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - RXOF flag does not generate an interrupt to the host.
+ * - 0b1 - RXOF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_RXOFE field. */
+#define UART_RD_CFIFO_RXOFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_RXOFE_MASK) >> UART_CFIFO_RXOFE_SHIFT)
+#define UART_BRD_CFIFO_RXOFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXOFE_SHIFT))
+
+/*! @brief Set the RXOFE field to a new value. */
+#define UART_WR_CFIFO_RXOFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXOFE_MASK, UART_CFIFO_RXOFE(value)))
+#define UART_BWR_CFIFO_RXOFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXOFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the receive
+ * FIFO/buffer to be flushed. This does not affect data that is in the receive shift
+ * register.
+ *
+ * Values:
+ * - 0b0 - No flush operation occurs.
+ * - 0b1 - All data in the receive FIFO/buffer is cleared out.
+ */
+/*@{*/
+/*! @brief Set the RXFLUSH field to a new value. */
+#define UART_WR_CFIFO_RXFLUSH(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXFLUSH_MASK, UART_CFIFO_RXFLUSH(value)))
+#define UART_BWR_CFIFO_RXFLUSH(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXFLUSH_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the transmit
+ * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
+ * register.
+ *
+ * Values:
+ * - 0b0 - No flush operation occurs.
+ * - 0b1 - All data in the transmit FIFO/Buffer is cleared out.
+ */
+/*@{*/
+/*! @brief Set the TXFLUSH field to a new value. */
+#define UART_WR_CFIFO_TXFLUSH(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_TXFLUSH_MASK, UART_CFIFO_TXFLUSH(value)))
+#define UART_BWR_CFIFO_TXFLUSH(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXFLUSH_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_SFIFO - UART FIFO Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_SFIFO - UART FIFO Status Register (RW)
+ *
+ * Reset value: 0xC0U
+ *
+ * This register provides status information regarding the transmit and receiver
+ * buffers/FIFOs, including interrupt information. This register may be written
+ * to or read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_SFIFO register
+ */
+/*@{*/
+#define UART_RD_SFIFO(base)      (UART_SFIFO_REG(base))
+#define UART_WR_SFIFO(base, value) (UART_SFIFO_REG(base) = (value))
+#define UART_RMW_SFIFO(base, mask, value) (UART_WR_SFIFO(base, (UART_RD_SFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) |  (value)))
+#define UART_CLR_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) & ~(value)))
+#define UART_TOG_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_SFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_SFIFO, field RXUF[0] (W1C)
+ *
+ * Indicates that more data has been read from the receive buffer than was
+ * present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No receive buffer underflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one receive buffer underflow has occurred since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXUF field. */
+#define UART_RD_SFIFO_RXUF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXUF_MASK) >> UART_SFIFO_RXUF_SHIFT)
+#define UART_BRD_SFIFO_RXUF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXUF_SHIFT))
+
+/*! @brief Set the RXUF field to a new value. */
+#define UART_WR_SFIFO_RXUF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_RXUF_MASK | UART_SFIFO_TXOF_MASK | UART_SFIFO_RXOF_MASK), UART_SFIFO_RXUF(value)))
+#define UART_BWR_SFIFO_RXUF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field TXOF[1] (W1C)
+ *
+ * Indicates that more data has been written to the transmit buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
+ * flag is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No transmit buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one transmit buffer overflow has occurred since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_TXOF field. */
+#define UART_RD_SFIFO_TXOF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_TXOF_MASK) >> UART_SFIFO_TXOF_SHIFT)
+#define UART_BRD_SFIFO_TXOF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXOF_SHIFT))
+
+/*! @brief Set the TXOF field to a new value. */
+#define UART_WR_SFIFO_TXOF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_TXOF_MASK | UART_SFIFO_RXUF_MASK | UART_SFIFO_RXOF_MASK), UART_SFIFO_TXOF(value)))
+#define UART_BWR_SFIFO_TXOF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field RXOF[2] (W1C)
+ *
+ * Indicates that more data has been written to the receive buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No receive buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one receive buffer overflow has occurred since the last time
+ *     the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXOF field. */
+#define UART_RD_SFIFO_RXOF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXOF_MASK) >> UART_SFIFO_RXOF_SHIFT)
+#define UART_BRD_SFIFO_RXOF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXOF_SHIFT))
+
+/*! @brief Set the RXOF field to a new value. */
+#define UART_WR_SFIFO_RXOF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_RXOF_MASK | UART_SFIFO_RXUF_MASK | UART_SFIFO_TXOF_MASK), UART_SFIFO_RXOF(value)))
+#define UART_BWR_SFIFO_RXOF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field RXEMPT[6] (RO)
+ *
+ * Asserts when there is no data in the receive FIFO/Buffer. This field does not
+ * take into account data that is in the receive shift register.
+ *
+ * Values:
+ * - 0b0 - Receive buffer is not empty.
+ * - 0b1 - Receive buffer is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXEMPT field. */
+#define UART_RD_SFIFO_RXEMPT(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXEMPT_MASK) >> UART_SFIFO_RXEMPT_SHIFT)
+#define UART_BRD_SFIFO_RXEMPT(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXEMPT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field TXEMPT[7] (RO)
+ *
+ * Asserts when there is no data in the Transmit FIFO/buffer. This field does
+ * not take into account data that is in the transmit shift register.
+ *
+ * Values:
+ * - 0b0 - Transmit buffer is not empty.
+ * - 0b1 - Transmit buffer is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_TXEMPT field. */
+#define UART_RD_SFIFO_TXEMPT(base) ((UART_SFIFO_REG(base) & UART_SFIFO_TXEMPT_MASK) >> UART_SFIFO_TXEMPT_SHIFT)
+#define UART_BRD_SFIFO_TXEMPT(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXEMPT_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TWFIFO - UART FIFO Transmit Watermark
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TWFIFO - UART FIFO Transmit Watermark (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of needing additional transmit data. This register may be read at any
+ * time but must be written only when C2[TE] is not set. Changing the value of the
+ * watermark will not clear the S1[TDRE] flag.
+ */
+/*!
+ * @name Constants and macros for entire UART_TWFIFO register
+ */
+/*@{*/
+#define UART_RD_TWFIFO(base)     (UART_TWFIFO_REG(base))
+#define UART_WR_TWFIFO(base, value) (UART_TWFIFO_REG(base) = (value))
+#define UART_RMW_TWFIFO(base, mask, value) (UART_WR_TWFIFO(base, (UART_RD_TWFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) |  (value)))
+#define UART_CLR_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) & ~(value)))
+#define UART_TOG_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TCFIFO - UART FIFO Transmit Count
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TCFIFO - UART FIFO Transmit Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the transmit buffer/FIFO. It may be read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_TCFIFO register
+ */
+/*@{*/
+#define UART_RD_TCFIFO(base)     (UART_TCFIFO_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * UART_RWFIFO - UART FIFO Receive Watermark
+ ******************************************************************************/
+
+/*!
+ * @brief UART_RWFIFO - UART FIFO Receive Watermark (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of the need to remove data from the receiver FIFO/buffer. This register
+ * may be read at any time but must be written only when C2[RE] is not asserted.
+ * Changing the value in this register will not clear S1[RDRF].
+ */
+/*!
+ * @name Constants and macros for entire UART_RWFIFO register
+ */
+/*@{*/
+#define UART_RD_RWFIFO(base)     (UART_RWFIFO_REG(base))
+#define UART_WR_RWFIFO(base, value) (UART_RWFIFO_REG(base) = (value))
+#define UART_RMW_RWFIFO(base, mask, value) (UART_WR_RWFIFO(base, (UART_RD_RWFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) |  (value)))
+#define UART_CLR_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) & ~(value)))
+#define UART_TOG_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_RCFIFO - UART FIFO Receive Count
+ ******************************************************************************/
+
+/*!
+ * @brief UART_RCFIFO - UART FIFO Receive Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the receive FIFO/buffer. It may be read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_RCFIFO register
+ */
+/*@{*/
+#define UART_RD_RCFIFO(base)     (UART_RCFIFO_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C7816 - UART 7816 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C7816 - UART 7816 Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The C7816 register is the primary control register for ISO-7816 specific
+ * functionality. This register is specific to 7816 functionality and the values in
+ * this register have no effect on UART operation and should be ignored if
+ * ISO_7816E is not set/enabled. This register may be read at any time but values must
+ * be changed only when ISO_7816E is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_C7816 register
+ */
+/*@{*/
+#define UART_RD_C7816(base)      (UART_C7816_REG(base))
+#define UART_WR_C7816(base, value) (UART_C7816_REG(base) = (value))
+#define UART_RMW_C7816(base, mask, value) (UART_WR_C7816(base, (UART_RD_C7816(base) & ~(mask)) | (value)))
+#define UART_SET_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) |  (value)))
+#define UART_CLR_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) & ~(value)))
+#define UART_TOG_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C7816 bitfields
+ */
+
+/*!
+ * @name Register UART_C7816, field ISO_7816E[0] (RW)
+ *
+ * Indicates that the UART is operating according to the ISO-7816 protocol. This
+ * field must be modified only when no transmit or receive is occurring. If this
+ * field is changed during a data transfer, the data being transmitted or
+ * received may be transferred incorrectly.
+ *
+ * Values:
+ * - 0b0 - ISO-7816 functionality is turned off/not enabled.
+ * - 0b1 - ISO-7816 functionality is turned on/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ISO_7816E field. */
+#define UART_RD_C7816_ISO_7816E(base) ((UART_C7816_REG(base) & UART_C7816_ISO_7816E_MASK) >> UART_C7816_ISO_7816E_SHIFT)
+#define UART_BRD_C7816_ISO_7816E(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT))
+
+/*! @brief Set the ISO_7816E field to a new value. */
+#define UART_WR_C7816_ISO_7816E(base, value) (UART_RMW_C7816(base, UART_C7816_ISO_7816E_MASK, UART_C7816_ISO_7816E(value)))
+#define UART_BWR_C7816_ISO_7816E(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field TTYPE[1] (RW)
+ *
+ * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
+ * for more details.
+ *
+ * Values:
+ * - 0b0 - T = 0 per the ISO-7816 specification.
+ * - 0b1 - T = 1 per the ISO-7816 specification.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_TTYPE field. */
+#define UART_RD_C7816_TTYPE(base) ((UART_C7816_REG(base) & UART_C7816_TTYPE_MASK) >> UART_C7816_TTYPE_SHIFT)
+#define UART_BRD_C7816_TTYPE(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT))
+
+/*! @brief Set the TTYPE field to a new value. */
+#define UART_WR_C7816_TTYPE(base, value) (UART_RMW_C7816(base, UART_C7816_TTYPE_MASK, UART_C7816_TTYPE(value)))
+#define UART_BWR_C7816_TTYPE(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field INIT[2] (RW)
+ *
+ * When this field is set, all received characters are searched for a valid
+ * initial character. If an invalid initial character is identified, and ANACK is
+ * set, a NACK is sent. All received data is discarded and error flags blocked
+ * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
+ * until a valid initial character is detected. Upon detecting a valid initial
+ * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
+ * automatically updated to reflect the initial character that was received. The
+ * actual INIT data value is not stored in the receive buffer. Additionally, upon
+ * detection of a valid initial character, IS7816[INITD] is set and an interrupt
+ * issued as programmed by IE7816[INITDE]. When a valid initial character is
+ * detected, INIT is automatically cleared. This Initial Character Detect feature is
+ * supported only in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0b0 - Normal operating mode. Receiver does not seek to identify initial
+ *     character.
+ * - 0b1 - Receiver searches for initial character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_INIT field. */
+#define UART_RD_C7816_INIT(base) ((UART_C7816_REG(base) & UART_C7816_INIT_MASK) >> UART_C7816_INIT_SHIFT)
+#define UART_BRD_C7816_INIT(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT))
+
+/*! @brief Set the INIT field to a new value. */
+#define UART_WR_C7816_INIT(base, value) (UART_RMW_C7816(base, UART_C7816_INIT_MASK, UART_C7816_INIT(value)))
+#define UART_BWR_C7816_INIT(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ANACK[3] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a parity error occurs or if INIT is set and an invalid initial character is
+ * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
+ * attempts to retransmit the data indefinitely. To stop retransmission attempts,
+ * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
+ *
+ * Values:
+ * - 0b0 - No NACK is automatically generated.
+ * - 0b1 - A NACK is automatically generated if a parity error is detected or if
+ *     an invalid initial character is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ANACK field. */
+#define UART_RD_C7816_ANACK(base) ((UART_C7816_REG(base) & UART_C7816_ANACK_MASK) >> UART_C7816_ANACK_SHIFT)
+#define UART_BRD_C7816_ANACK(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT))
+
+/*! @brief Set the ANACK field to a new value. */
+#define UART_WR_C7816_ANACK(base, value) (UART_RMW_C7816(base, UART_C7816_ANACK_MASK, UART_C7816_ANACK(value)))
+#define UART_BWR_C7816_ANACK(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ONACK[4] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
+ * this results in the transmitter resending the packet that overflowed until the
+ * retransmit threshold for that transmitter is reached. A NACK is generated only
+ * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
+ * considerations
+ *
+ * Values:
+ * - 0b0 - The received data does not generate a NACK when the receipt of the
+ *     data results in an overflow event.
+ * - 0b1 - If the receiver buffer overflows, a NACK is automatically sent on a
+ *     received character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ONACK field. */
+#define UART_RD_C7816_ONACK(base) ((UART_C7816_REG(base) & UART_C7816_ONACK_MASK) >> UART_C7816_ONACK_SHIFT)
+#define UART_BRD_C7816_ONACK(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT))
+
+/*! @brief Set the ONACK field to a new value. */
+#define UART_WR_C7816_ONACK(base, value) (UART_RMW_C7816(base, UART_C7816_ONACK_MASK, UART_C7816_ONACK(value)))
+#define UART_BWR_C7816_ONACK(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IE7816 - UART 7816 Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IE7816 register controls which flags result in an interrupt being issued.
+ * This register is specific to 7816 functionality, the corresponding flags that
+ * drive the interrupts are not asserted when 7816E is not set/enabled. However,
+ * these flags may remain set if they are asserted while 7816E was set and not
+ * subsequently cleared. This register may be read or written to at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_IE7816 register
+ */
+/*@{*/
+#define UART_RD_IE7816(base)     (UART_IE7816_REG(base))
+#define UART_WR_IE7816(base, value) (UART_IE7816_REG(base) = (value))
+#define UART_RMW_IE7816(base, mask, value) (UART_WR_IE7816(base, (UART_RD_IE7816(base) & ~(mask)) | (value)))
+#define UART_SET_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) |  (value)))
+#define UART_CLR_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) & ~(value)))
+#define UART_TOG_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IE7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IE7816, field RXTE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[RXT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[RXT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_RXTE field. */
+#define UART_RD_IE7816_RXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_RXTE_MASK) >> UART_IE7816_RXTE_SHIFT)
+#define UART_BRD_IE7816_RXTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT))
+
+/*! @brief Set the RXTE field to a new value. */
+#define UART_WR_IE7816_RXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_RXTE_MASK, UART_IE7816_RXTE(value)))
+#define UART_BWR_IE7816_RXTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field TXTE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[TXT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[TXT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_TXTE field. */
+#define UART_RD_IE7816_TXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_TXTE_MASK) >> UART_IE7816_TXTE_SHIFT)
+#define UART_BRD_IE7816_TXTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT))
+
+/*! @brief Set the TXTE field to a new value. */
+#define UART_WR_IE7816_TXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_TXTE_MASK, UART_IE7816_TXTE(value)))
+#define UART_BWR_IE7816_TXTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field GTVE[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[GTV] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[GTV] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_GTVE field. */
+#define UART_RD_IE7816_GTVE(base) ((UART_IE7816_REG(base) & UART_IE7816_GTVE_MASK) >> UART_IE7816_GTVE_SHIFT)
+#define UART_BRD_IE7816_GTVE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT))
+
+/*! @brief Set the GTVE field to a new value. */
+#define UART_WR_IE7816_GTVE(base, value) (UART_RMW_IE7816(base, UART_IE7816_GTVE_MASK, UART_IE7816_GTVE(value)))
+#define UART_BWR_IE7816_GTVE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field INITDE[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[INITD] does not result in the generation of
+ *     an interrupt.
+ * - 0b1 - The assertion of IS7816[INITD] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_INITDE field. */
+#define UART_RD_IE7816_INITDE(base) ((UART_IE7816_REG(base) & UART_IE7816_INITDE_MASK) >> UART_IE7816_INITDE_SHIFT)
+#define UART_BRD_IE7816_INITDE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT))
+
+/*! @brief Set the INITDE field to a new value. */
+#define UART_WR_IE7816_INITDE(base, value) (UART_RMW_IE7816(base, UART_IE7816_INITDE_MASK, UART_IE7816_INITDE(value)))
+#define UART_BWR_IE7816_INITDE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field BWTE[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[BWT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[BWT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_BWTE field. */
+#define UART_RD_IE7816_BWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_BWTE_MASK) >> UART_IE7816_BWTE_SHIFT)
+#define UART_BRD_IE7816_BWTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT))
+
+/*! @brief Set the BWTE field to a new value. */
+#define UART_WR_IE7816_BWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_BWTE_MASK, UART_IE7816_BWTE(value)))
+#define UART_BWR_IE7816_BWTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field CWTE[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[CWT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[CWT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_CWTE field. */
+#define UART_RD_IE7816_CWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_CWTE_MASK) >> UART_IE7816_CWTE_SHIFT)
+#define UART_BRD_IE7816_CWTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT))
+
+/*! @brief Set the CWTE field to a new value. */
+#define UART_WR_IE7816_CWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_CWTE_MASK, UART_IE7816_CWTE(value)))
+#define UART_BWR_IE7816_CWTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field WTE[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[WT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[WT] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_WTE field. */
+#define UART_RD_IE7816_WTE(base) ((UART_IE7816_REG(base) & UART_IE7816_WTE_MASK) >> UART_IE7816_WTE_SHIFT)
+#define UART_BRD_IE7816_WTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT))
+
+/*! @brief Set the WTE field to a new value. */
+#define UART_WR_IE7816_WTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_WTE_MASK, UART_IE7816_WTE(value)))
+#define UART_BWR_IE7816_WTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IS7816 - UART 7816 Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IS7816 - UART 7816 Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IS7816 register provides a mechanism to read and clear the interrupt
+ * flags. All flags/interrupts are cleared by writing a 1 to the field location.
+ * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
+ * the flag condition that occurred since the last time the bit was cleared, not
+ * that the condition currently exists. The status flags are set regardless of
+ * whether the corresponding field in the IE7816 is set or cleared. The IE7816
+ * controls only if an interrupt is issued to the host processor. This register is
+ * specific to 7816 functionality and the values in this register have no affect on
+ * UART operation and should be ignored if 7816E is not set/enabled. This
+ * register may be read or written at anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_IS7816 register
+ */
+/*@{*/
+#define UART_RD_IS7816(base)     (UART_IS7816_REG(base))
+#define UART_WR_IS7816(base, value) (UART_IS7816_REG(base) = (value))
+#define UART_RMW_IS7816(base, mask, value) (UART_WR_IS7816(base, (UART_RD_IS7816(base) & ~(mask)) | (value)))
+#define UART_SET_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) |  (value)))
+#define UART_CLR_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) & ~(value)))
+#define UART_TOG_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IS7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IS7816, field RXT[0] (W1C)
+ *
+ * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
+ * generated in response to parity errors on received data. This flag requires ANACK
+ * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
+ * Clearing this field also resets the counter keeping track of consecutive NACKS. The
+ * UART will continue to attempt to receive data regardless of whether this flag
+ * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
+ * or packet is received without needing to issue a NACK, the internal NACK
+ * detection counter is cleared and the count restarts from zero on the next
+ * transmitted NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - The number of consecutive NACKS generated as a result of parity
+ *     errors and buffer overruns is less than or equal to the value in
+ *     ET7816[RXTHRESHOLD].
+ * - 0b1 - The number of consecutive NACKS generated as a result of parity
+ *     errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_RXT field. */
+#define UART_RD_IS7816_RXT(base) ((UART_IS7816_REG(base) & UART_IS7816_RXT_MASK) >> UART_IS7816_RXT_SHIFT)
+#define UART_BRD_IS7816_RXT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT))
+
+/*! @brief Set the RXT field to a new value. */
+#define UART_WR_IS7816_RXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_RXT(value)))
+#define UART_BWR_IS7816_RXT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field TXT[1] (W1C)
+ *
+ * Indicates that the transmit NACK threshold has been exceeded as indicated by
+ * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
+ * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
+ * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
+ * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
+ * internal NACK detection counter is cleared and the count restarts from zero on
+ * the next received NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - The number of retries and corresponding NACKS does not exceed the
+ *     value in ET7816[TXTHRESHOLD].
+ * - 0b1 - The number of retries and corresponding NACKS exceeds the value in
+ *     ET7816[TXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_TXT field. */
+#define UART_RD_IS7816_TXT(base) ((UART_IS7816_REG(base) & UART_IS7816_TXT_MASK) >> UART_IS7816_TXT_SHIFT)
+#define UART_BRD_IS7816_TXT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT))
+
+/*! @brief Set the TXT field to a new value. */
+#define UART_WR_IS7816_TXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_TXT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_TXT(value)))
+#define UART_BWR_IS7816_TXT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field GTV[2] (W1C)
+ *
+ * Indicates that one or more of the character guard time, block guard time, or
+ * guard time are violated. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - A guard time (GT, CGT, or BGT) has not been violated.
+ * - 0b1 - A guard time (GT, CGT, or BGT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_GTV field. */
+#define UART_RD_IS7816_GTV(base) ((UART_IS7816_REG(base) & UART_IS7816_GTV_MASK) >> UART_IS7816_GTV_SHIFT)
+#define UART_BRD_IS7816_GTV(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT))
+
+/*! @brief Set the GTV field to a new value. */
+#define UART_WR_IS7816_GTV(base, value) (UART_RMW_IS7816(base, (UART_IS7816_GTV_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_GTV(value)))
+#define UART_BWR_IS7816_GTV(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field INITD[4] (W1C)
+ *
+ * Indicates that a valid initial character is received. This interrupt is
+ * cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - A valid initial character has not been received.
+ * - 0b1 - A valid initial character has been received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_INITD field. */
+#define UART_RD_IS7816_INITD(base) ((UART_IS7816_REG(base) & UART_IS7816_INITD_MASK) >> UART_IS7816_INITD_SHIFT)
+#define UART_BRD_IS7816_INITD(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT))
+
+/*! @brief Set the INITD field to a new value. */
+#define UART_WR_IS7816_INITD(base, value) (UART_RMW_IS7816(base, (UART_IS7816_INITD_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_INITD(value)))
+#define UART_BWR_IS7816_INITD(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field BWT[5] (W1C)
+ *
+ * Indicates that the block wait time, the time between the leading edge of
+ * first received character of a block and the leading edge of the last character the
+ * previously transmitted block, has exceeded the programmed value. This flag
+ * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - Block wait time (BWT) has not been violated.
+ * - 0b1 - Block wait time (BWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_BWT field. */
+#define UART_RD_IS7816_BWT(base) ((UART_IS7816_REG(base) & UART_IS7816_BWT_MASK) >> UART_IS7816_BWT_SHIFT)
+#define UART_BRD_IS7816_BWT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT))
+
+/*! @brief Set the BWT field to a new value. */
+#define UART_WR_IS7816_BWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_BWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_BWT(value)))
+#define UART_BWR_IS7816_BWT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field CWT[6] (W1C)
+ *
+ * Indicates that the character wait time, the time between the leading edges of
+ * two consecutive characters in a block, has exceeded the programmed value.
+ * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
+ * writing 1.
+ *
+ * Values:
+ * - 0b0 - Character wait time (CWT) has not been violated.
+ * - 0b1 - Character wait time (CWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_CWT field. */
+#define UART_RD_IS7816_CWT(base) ((UART_IS7816_REG(base) & UART_IS7816_CWT_MASK) >> UART_IS7816_CWT_SHIFT)
+#define UART_BRD_IS7816_CWT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT))
+
+/*! @brief Set the CWT field to a new value. */
+#define UART_WR_IS7816_CWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_CWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_CWT(value)))
+#define UART_BWR_IS7816_CWT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field WT[7] (W1C)
+ *
+ * Indicates that the wait time, the time between the leading edge of a
+ * character being transmitted and the leading edge of the next response character, has
+ * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
+ * This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - Wait time (WT) has not been violated.
+ * - 0b1 - Wait time (WT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_WT field. */
+#define UART_RD_IS7816_WT(base) ((UART_IS7816_REG(base) & UART_IS7816_WT_MASK) >> UART_IS7816_WT_SHIFT)
+#define UART_BRD_IS7816_WT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT))
+
+/*! @brief Set the WT field to a new value. */
+#define UART_WR_IS7816_WT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_WT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK), UART_IS7816_WT(value)))
+#define UART_BWR_IS7816_WT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816T0 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816T0 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816T0 register
+ */
+/*@{*/
+#define UART_RD_WP7816T0(base)   (UART_WP7816T0_REG(base))
+#define UART_WR_WP7816T0(base, value) (UART_WP7816T0_REG(base) = (value))
+#define UART_RMW_WP7816T0(base, mask, value) (UART_WR_WP7816T0(base, (UART_RD_WP7816T0(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) |  (value)))
+#define UART_CLR_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) & ~(value)))
+#define UART_TOG_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816T1 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816T1 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816T1 register
+ */
+/*@{*/
+#define UART_RD_WP7816T1(base)   (UART_WP7816T1_REG(base))
+#define UART_WR_WP7816T1(base, value) (UART_WP7816T1_REG(base) = (value))
+#define UART_RMW_WP7816T1(base, mask, value) (UART_WR_WP7816T1(base, (UART_RD_WP7816T1(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) |  (value)))
+#define UART_CLR_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) & ~(value)))
+#define UART_TOG_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_WP7816T1 bitfields
+ */
+
+/*!
+ * @name Register UART_WP7816T1, field BWI[3:0] (RW)
+ *
+ * Used to calculate the value used for the BWT counter. It represent a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816T1_BWI field. */
+#define UART_RD_WP7816T1_BWI(base) ((UART_WP7816T1_REG(base) & UART_WP7816T1_BWI_MASK) >> UART_WP7816T1_BWI_SHIFT)
+#define UART_BRD_WP7816T1_BWI(base) (UART_RD_WP7816T1_BWI(base))
+
+/*! @brief Set the BWI field to a new value. */
+#define UART_WR_WP7816T1_BWI(base, value) (UART_RMW_WP7816T1(base, UART_WP7816T1_BWI_MASK, UART_WP7816T1_BWI(value)))
+#define UART_BWR_WP7816T1_BWI(base, value) (UART_WR_WP7816T1_BWI(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_WP7816T1, field CWI[7:4] (RW)
+ *
+ * Used to calculate the value used for the CWT counter. It represents a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816T1_CWI field. */
+#define UART_RD_WP7816T1_CWI(base) ((UART_WP7816T1_REG(base) & UART_WP7816T1_CWI_MASK) >> UART_WP7816T1_CWI_SHIFT)
+#define UART_BRD_WP7816T1_CWI(base) (UART_RD_WP7816T1_CWI(base))
+
+/*! @brief Set the CWI field to a new value. */
+#define UART_WR_WP7816T1_CWI(base, value) (UART_RMW_WP7816T1(base, UART_WP7816T1_CWI_MASK, UART_WP7816T1_CWI(value)))
+#define UART_BWR_WP7816T1_CWI(base, value) (UART_WR_WP7816T1_CWI(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WN7816 - UART 7816 Wait N Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WN7816 - UART 7816 Wait N Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The WN7816 register contains a parameter that is used in the calculation of
+ * the guard time counter. This register may be read at any time. This register
+ * must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WN7816 register
+ */
+/*@{*/
+#define UART_RD_WN7816(base)     (UART_WN7816_REG(base))
+#define UART_WR_WN7816(base, value) (UART_WN7816_REG(base) = (value))
+#define UART_RMW_WN7816(base, mask, value) (UART_WR_WN7816(base, (UART_RD_WN7816(base) & ~(mask)) | (value)))
+#define UART_SET_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) |  (value)))
+#define UART_CLR_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) & ~(value)))
+#define UART_TOG_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WF7816 - UART 7816 Wait FD Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WF7816 - UART 7816 Wait FD Register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * The WF7816 contains parameters that are used in the generation of various
+ * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WF7816 register
+ */
+/*@{*/
+#define UART_RD_WF7816(base)     (UART_WF7816_REG(base))
+#define UART_WR_WF7816(base, value) (UART_WF7816_REG(base) = (value))
+#define UART_RMW_WF7816(base, mask, value) (UART_WR_WF7816(base, (UART_RD_WF7816(base) & ~(mask)) | (value)))
+#define UART_SET_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) |  (value)))
+#define UART_CLR_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) & ~(value)))
+#define UART_TOG_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ET7816 - UART 7816 Error Threshold Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ET7816 - UART 7816 Error Threshold Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The ET7816 register contains fields that determine the number of NACKs that
+ * must be received or transmitted before the host processor is notified. This
+ * register may be read at anytime. This register must be written to only when
+ * C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_ET7816 register
+ */
+/*@{*/
+#define UART_RD_ET7816(base)     (UART_ET7816_REG(base))
+#define UART_WR_ET7816(base, value) (UART_ET7816_REG(base) = (value))
+#define UART_RMW_ET7816(base, mask, value) (UART_WR_ET7816(base, (UART_RD_ET7816(base) & ~(mask)) | (value)))
+#define UART_SET_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) |  (value)))
+#define UART_CLR_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) & ~(value)))
+#define UART_TOG_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ET7816 bitfields
+ */
+
+/*!
+ * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
+ *
+ * The value written to this field indicates the maximum number of consecutive
+ * NACKs generated as a result of a parity error or receiver buffer overruns
+ * before the host processor is notified. After the counter exceeds that value in the
+ * field, the IS7816[RXT] is asserted. This field is meaningful only when
+ * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
+ * NACKs that have been transmitted since the last successful reception. This
+ * counter saturates at 4'hF and does not wrap around. Regardless of the number of
+ * NACKs sent, the UART continues to receive valid packets indefinitely. For
+ * additional information, see IS7816[RXT] field description.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */
+#define UART_RD_ET7816_RXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_RXTHRESHOLD_MASK) >> UART_ET7816_RXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_RXTHRESHOLD(base) (UART_RD_ET7816_RXTHRESHOLD(base))
+
+/*! @brief Set the RXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_RXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_RXTHRESHOLD_MASK, UART_ET7816_RXTHRESHOLD(value)))
+#define UART_BWR_ET7816_RXTHRESHOLD(base, value) (UART_WR_ET7816_RXTHRESHOLD(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
+ *
+ * The value written to this field indicates the maximum number of failed
+ * attempts (NACKs) a transmitted character can have before the host processor is
+ * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
+ * The value read from this field represents the number of consecutive NACKs
+ * that have been received since the last successful transmission. This counter
+ * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
+ * received, the UART continues to retransmit indefinitely. This flag only
+ * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
+ * description.
+ *
+ * Values:
+ * - 0b0000 - TXT asserts on the first NACK that is received.
+ * - 0b0001 - TXT asserts on the second NACK that is received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */
+#define UART_RD_ET7816_TXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_TXTHRESHOLD_MASK) >> UART_ET7816_TXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_TXTHRESHOLD(base) (UART_RD_ET7816_TXTHRESHOLD(base))
+
+/*! @brief Set the TXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_TXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_TXTHRESHOLD_MASK, UART_ET7816_TXTHRESHOLD(value)))
+#define UART_BWR_ET7816_TXTHRESHOLD(base, value) (UART_WR_ET7816_TXTHRESHOLD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TL7816 - UART 7816 Transmit Length Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TL7816 - UART 7816 Transmit Length Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The TL7816 register is used to indicate the number of characters contained in
+ * the block being transmitted. This register is used only when C7816[TTYPE] =
+ * 1. This register may be read at anytime. This register must be written only
+ * when C2[TE] is not enabled.
+ */
+/*!
+ * @name Constants and macros for entire UART_TL7816 register
+ */
+/*@{*/
+#define UART_RD_TL7816(base)     (UART_TL7816_REG(base))
+#define UART_WR_TL7816(base, value) (UART_TL7816_REG(base) = (value))
+#define UART_RMW_TL7816(base, mask, value) (UART_WR_TL7816(base, (UART_RD_TL7816(base) & ~(mask)) | (value)))
+#define UART_SET_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) |  (value)))
+#define UART_CLR_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) & ~(value)))
+#define UART_TOG_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 USB
+ *
+ * Universal Serial Bus, OTG Capable Controller
+ *
+ * Registers defined in this header file:
+ * - USB_PERID - Peripheral ID register
+ * - USB_IDCOMP - Peripheral ID Complement register
+ * - USB_REV - Peripheral Revision register
+ * - USB_ADDINFO - Peripheral Additional Info register
+ * - USB_OTGISTAT - OTG Interrupt Status register
+ * - USB_OTGICR - OTG Interrupt Control register
+ * - USB_OTGSTAT - OTG Status register
+ * - USB_OTGCTL - OTG Control register
+ * - USB_ISTAT - Interrupt Status register
+ * - USB_INTEN - Interrupt Enable register
+ * - USB_ERRSTAT - Error Interrupt Status register
+ * - USB_ERREN - Error Interrupt Enable register
+ * - USB_STAT - Status register
+ * - USB_CTL - Control register
+ * - USB_ADDR - Address register
+ * - USB_BDTPAGE1 - BDT Page register 1
+ * - USB_FRMNUML - Frame Number register Low
+ * - USB_FRMNUMH - Frame Number register High
+ * - USB_TOKEN - Token register
+ * - USB_SOFTHLD - SOF Threshold register
+ * - USB_BDTPAGE2 - BDT Page Register 2
+ * - USB_BDTPAGE3 - BDT Page Register 3
+ * - USB_ENDPT - Endpoint Control register
+ * - USB_USBCTRL - USB Control register
+ * - USB_OBSERVE - USB OTG Observe register
+ * - USB_CONTROL - USB OTG Control register
+ * - USB_USBTRC0 - USB Transceiver Control register 0
+ * - USB_USBFRMADJUST - Frame Adjust Register
+ * - USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ * - USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ * - USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ */
+
+#define USB_INSTANCE_COUNT (1U) /*!< Number of instances of the USB module. */
+#define USB0_IDX (0U) /*!< Instance number for USB0. */
+
+/*******************************************************************************
+ * USB_PERID - Peripheral ID register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_PERID - Peripheral ID register (RO)
+ *
+ * Reset value: 0x04U
+ *
+ * Reads back the value of 0x04. This value is defined for the USB peripheral.
+ */
+/*!
+ * @name Constants and macros for entire USB_PERID register
+ */
+/*@{*/
+#define USB_RD_PERID(base)       (USB_PERID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_PERID bitfields
+ */
+
+/*!
+ * @name Register USB_PERID, field ID[5:0] (RO)
+ *
+ * This field always reads 0x4h.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_PERID_ID field. */
+#define USB_RD_PERID_ID(base) ((USB_PERID_REG(base) & USB_PERID_ID_MASK) >> USB_PERID_ID_SHIFT)
+#define USB_BRD_PERID_ID(base) (USB_RD_PERID_ID(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_IDCOMP - Peripheral ID Complement register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_IDCOMP - Peripheral ID Complement register (RO)
+ *
+ * Reset value: 0xFBU
+ *
+ * Reads back the complement of the Peripheral ID register. For the USB
+ * peripheral, the value is 0xFB.
+ */
+/*!
+ * @name Constants and macros for entire USB_IDCOMP register
+ */
+/*@{*/
+#define USB_RD_IDCOMP(base)      (USB_IDCOMP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_IDCOMP bitfields
+ */
+
+/*!
+ * @name Register USB_IDCOMP, field NID[5:0] (RO)
+ *
+ * Ones' complement of PERID[ID]. bits.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_IDCOMP_NID field. */
+#define USB_RD_IDCOMP_NID(base) ((USB_IDCOMP_REG(base) & USB_IDCOMP_NID_MASK) >> USB_IDCOMP_NID_SHIFT)
+#define USB_BRD_IDCOMP_NID(base) (USB_RD_IDCOMP_NID(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_REV - Peripheral Revision register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_REV - Peripheral Revision register (RO)
+ *
+ * Reset value: 0x33U
+ *
+ * Contains the revision number of the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_REV register
+ */
+/*@{*/
+#define USB_RD_REV(base)         (USB_REV_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDINFO - Peripheral Additional Info register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDINFO - Peripheral Additional Info register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with
+ * the Host Enable bit.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDINFO register
+ */
+/*@{*/
+#define USB_RD_ADDINFO(base)     (USB_ADDINFO_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDINFO bitfields
+ */
+
+/*!
+ * @name Register USB_ADDINFO, field IEHOST[0] (RO)
+ *
+ * This bit is set if host mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IEHOST field. */
+#define USB_RD_ADDINFO_IEHOST(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IEHOST_MASK) >> USB_ADDINFO_IEHOST_SHIFT)
+#define USB_BRD_ADDINFO_IEHOST(base) (BITBAND_ACCESS8(&USB_ADDINFO_REG(base), USB_ADDINFO_IEHOST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_ADDINFO, field IRQNUM[7:3] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IRQNUM field. */
+#define USB_RD_ADDINFO_IRQNUM(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IRQNUM_MASK) >> USB_ADDINFO_IRQNUM_SHIFT)
+#define USB_BRD_ADDINFO_IRQNUM(base) (USB_RD_ADDINFO_IRQNUM(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGISTAT - OTG Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGISTAT - OTG Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Records changes of the ID sense and VBUS signals. Software can read this
+ * register to determine the event that triggers an interrupt. Only bits that have
+ * changed since the last software read are set. Writing a one to a bit clears the
+ * associated interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGISTAT register
+ */
+/*@{*/
+#define USB_RD_OTGISTAT(base)    (USB_OTGISTAT_REG(base))
+#define USB_WR_OTGISTAT(base, value) (USB_OTGISTAT_REG(base) = (value))
+#define USB_RMW_OTGISTAT(base, mask, value) (USB_WR_OTGISTAT(base, (USB_RD_OTGISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) |  (value)))
+#define USB_CLR_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) & ~(value)))
+#define USB_TOG_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on an A device.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field. */
+#define USB_RD_OTGISTAT_AVBUSCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_AVBUSCHG_MASK) >> USB_OTGISTAT_AVBUSCHG_SHIFT)
+#define USB_BRD_OTGISTAT_AVBUSCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_AVBUSCHG_SHIFT))
+
+/*! @brief Set the AVBUSCHG field to a new value. */
+#define USB_WR_OTGISTAT_AVBUSCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_AVBUSCHG_MASK, USB_OTGISTAT_AVBUSCHG(value)))
+#define USB_BWR_OTGISTAT_AVBUSCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_AVBUSCHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on a B device.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field. */
+#define USB_RD_OTGISTAT_B_SESS_CHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_B_SESS_CHG_MASK) >> USB_OTGISTAT_B_SESS_CHG_SHIFT)
+#define USB_BRD_OTGISTAT_B_SESS_CHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_B_SESS_CHG_SHIFT))
+
+/*! @brief Set the B_SESS_CHG field to a new value. */
+#define USB_WR_OTGISTAT_B_SESS_CHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_B_SESS_CHG_MASK, USB_OTGISTAT_B_SESS_CHG(value)))
+#define USB_BWR_OTGISTAT_B_SESS_CHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_B_SESS_CHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW)
+ *
+ * This bit is set when a change in VBUS is detected indicating a session valid
+ * or a session no longer valid.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field. */
+#define USB_RD_OTGISTAT_SESSVLDCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_SESSVLDCHG_MASK) >> USB_OTGISTAT_SESSVLDCHG_SHIFT)
+#define USB_BRD_OTGISTAT_SESSVLDCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_SESSVLDCHG_SHIFT))
+
+/*! @brief Set the SESSVLDCHG field to a new value. */
+#define USB_WR_OTGISTAT_SESSVLDCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_SESSVLDCHG_MASK, USB_OTGISTAT_SESSVLDCHG(value)))
+#define USB_BWR_OTGISTAT_SESSVLDCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_SESSVLDCHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW)
+ *
+ * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits)
+ * are stable without change for 1 millisecond, and the value of the line state
+ * is different from the last time when the line state was stable. It is set on
+ * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
+ * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt
+ * can be used in detecting Reset, Resume, Connect, and Data Line Pulse
+ * signaling.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field. */
+#define USB_RD_OTGISTAT_LINE_STATE_CHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_LINE_STATE_CHG_MASK) >> USB_OTGISTAT_LINE_STATE_CHG_SHIFT)
+#define USB_BRD_OTGISTAT_LINE_STATE_CHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_LINE_STATE_CHG_SHIFT))
+
+/*! @brief Set the LINE_STATE_CHG field to a new value. */
+#define USB_WR_OTGISTAT_LINE_STATE_CHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_LINE_STATE_CHG_MASK, USB_OTGISTAT_LINE_STATE_CHG(value)))
+#define USB_BWR_OTGISTAT_LINE_STATE_CHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_LINE_STATE_CHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW)
+ *
+ * This bit is set when the 1 millisecond timer expires. This bit stays asserted
+ * until cleared by software. The interrupt must be serviced every millisecond
+ * to avoid losing 1msec counts.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_ONEMSEC field. */
+#define USB_RD_OTGISTAT_ONEMSEC(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_ONEMSEC_MASK) >> USB_OTGISTAT_ONEMSEC_SHIFT)
+#define USB_BRD_OTGISTAT_ONEMSEC(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_ONEMSEC_SHIFT))
+
+/*! @brief Set the ONEMSEC field to a new value. */
+#define USB_WR_OTGISTAT_ONEMSEC(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_ONEMSEC_MASK, USB_OTGISTAT_ONEMSEC(value)))
+#define USB_BWR_OTGISTAT_ONEMSEC(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_ONEMSEC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field IDCHG[7] (RW)
+ *
+ * This bit is set when a change in the ID Signal from the USB connector is
+ * sensed.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_IDCHG field. */
+#define USB_RD_OTGISTAT_IDCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_IDCHG_MASK) >> USB_OTGISTAT_IDCHG_SHIFT)
+#define USB_BRD_OTGISTAT_IDCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_IDCHG_SHIFT))
+
+/*! @brief Set the IDCHG field to a new value. */
+#define USB_WR_OTGISTAT_IDCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_IDCHG_MASK, USB_OTGISTAT_IDCHG(value)))
+#define USB_BWR_OTGISTAT_IDCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_IDCHG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGICR - OTG Interrupt Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGICR - OTG Interrupt Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Enables the corresponding interrupt status bits defined in the OTG Interrupt
+ * Status Register.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGICR register
+ */
+/*@{*/
+#define USB_RD_OTGICR(base)      (USB_OTGICR_REG(base))
+#define USB_WR_OTGICR(base, value) (USB_OTGICR_REG(base) = (value))
+#define USB_RMW_OTGICR(base, mask, value) (USB_WR_OTGICR(base, (USB_RD_OTGICR(base) & ~(mask)) | (value)))
+#define USB_SET_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) |  (value)))
+#define USB_CLR_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) & ~(value)))
+#define USB_TOG_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGICR bitfields
+ */
+
+/*!
+ * @name Register USB_OTGICR, field AVBUSEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the AVBUSCHG interrupt.
+ * - 0b1 - Enables the AVBUSCHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_AVBUSEN field. */
+#define USB_RD_OTGICR_AVBUSEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_AVBUSEN_MASK) >> USB_OTGICR_AVBUSEN_SHIFT)
+#define USB_BRD_OTGICR_AVBUSEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_AVBUSEN_SHIFT))
+
+/*! @brief Set the AVBUSEN field to a new value. */
+#define USB_WR_OTGICR_AVBUSEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_AVBUSEN_MASK, USB_OTGICR_AVBUSEN(value)))
+#define USB_BWR_OTGICR_AVBUSEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_AVBUSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field BSESSEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the B_SESS_CHG interrupt.
+ * - 0b1 - Enables the B_SESS_CHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_BSESSEN field. */
+#define USB_RD_OTGICR_BSESSEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_BSESSEN_MASK) >> USB_OTGICR_BSESSEN_SHIFT)
+#define USB_BRD_OTGICR_BSESSEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_BSESSEN_SHIFT))
+
+/*! @brief Set the BSESSEN field to a new value. */
+#define USB_WR_OTGICR_BSESSEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_BSESSEN_MASK, USB_OTGICR_BSESSEN(value)))
+#define USB_BWR_OTGICR_BSESSEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_BSESSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field SESSVLDEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the SESSVLDCHG interrupt.
+ * - 0b1 - Enables the SESSVLDCHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_SESSVLDEN field. */
+#define USB_RD_OTGICR_SESSVLDEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_SESSVLDEN_MASK) >> USB_OTGICR_SESSVLDEN_SHIFT)
+#define USB_BRD_OTGICR_SESSVLDEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_SESSVLDEN_SHIFT))
+
+/*! @brief Set the SESSVLDEN field to a new value. */
+#define USB_WR_OTGICR_SESSVLDEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_SESSVLDEN_MASK, USB_OTGICR_SESSVLDEN(value)))
+#define USB_BWR_OTGICR_SESSVLDEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_SESSVLDEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field LINESTATEEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the LINE_STAT_CHG interrupt.
+ * - 0b1 - Enables the LINE_STAT_CHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_LINESTATEEN field. */
+#define USB_RD_OTGICR_LINESTATEEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_LINESTATEEN_MASK) >> USB_OTGICR_LINESTATEEN_SHIFT)
+#define USB_BRD_OTGICR_LINESTATEEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_LINESTATEEN_SHIFT))
+
+/*! @brief Set the LINESTATEEN field to a new value. */
+#define USB_WR_OTGICR_LINESTATEEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_LINESTATEEN_MASK, USB_OTGICR_LINESTATEEN(value)))
+#define USB_BWR_OTGICR_LINESTATEEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_LINESTATEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field ONEMSECEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Diables the 1ms timer interrupt.
+ * - 0b1 - Enables the 1ms timer interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_ONEMSECEN field. */
+#define USB_RD_OTGICR_ONEMSECEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_ONEMSECEN_MASK) >> USB_OTGICR_ONEMSECEN_SHIFT)
+#define USB_BRD_OTGICR_ONEMSECEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_ONEMSECEN_SHIFT))
+
+/*! @brief Set the ONEMSECEN field to a new value. */
+#define USB_WR_OTGICR_ONEMSECEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_ONEMSECEN_MASK, USB_OTGICR_ONEMSECEN(value)))
+#define USB_BWR_OTGICR_ONEMSECEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_ONEMSECEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field IDEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The ID interrupt is disabled
+ * - 0b1 - The ID interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_IDEN field. */
+#define USB_RD_OTGICR_IDEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_IDEN_MASK) >> USB_OTGICR_IDEN_SHIFT)
+#define USB_BRD_OTGICR_IDEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_IDEN_SHIFT))
+
+/*! @brief Set the IDEN field to a new value. */
+#define USB_WR_OTGICR_IDEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_IDEN_MASK, USB_OTGICR_IDEN(value)))
+#define USB_BWR_OTGICR_IDEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_IDEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGSTAT - OTG Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGSTAT - OTG Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Displays the actual value from the external comparator outputs of the ID pin
+ * and VBUS.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGSTAT register
+ */
+/*@{*/
+#define USB_RD_OTGSTAT(base)     (USB_OTGSTAT_REG(base))
+#define USB_WR_OTGSTAT(base, value) (USB_OTGSTAT_REG(base) = (value))
+#define USB_RMW_OTGSTAT(base, mask, value) (USB_WR_OTGSTAT(base, (USB_RD_OTGSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) |  (value)))
+#define USB_CLR_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) & ~(value)))
+#define USB_TOG_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is below the A VBUS Valid threshold.
+ * - 0b1 - The VBUS voltage is above the A VBUS Valid threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field. */
+#define USB_RD_OTGSTAT_AVBUSVLD(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_AVBUSVLD_MASK) >> USB_OTGSTAT_AVBUSVLD_SHIFT)
+#define USB_BRD_OTGSTAT_AVBUSVLD(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_AVBUSVLD_SHIFT))
+
+/*! @brief Set the AVBUSVLD field to a new value. */
+#define USB_WR_OTGSTAT_AVBUSVLD(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_AVBUSVLD_MASK, USB_OTGSTAT_AVBUSVLD(value)))
+#define USB_BWR_OTGSTAT_AVBUSVLD(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_AVBUSVLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field BSESSEND[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is above the B session end threshold.
+ * - 0b1 - The VBUS voltage is below the B session end threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_BSESSEND field. */
+#define USB_RD_OTGSTAT_BSESSEND(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_BSESSEND_MASK) >> USB_OTGSTAT_BSESSEND_SHIFT)
+#define USB_BRD_OTGSTAT_BSESSEND(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_BSESSEND_SHIFT))
+
+/*! @brief Set the BSESSEND field to a new value. */
+#define USB_WR_OTGSTAT_BSESSEND(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_BSESSEND_MASK, USB_OTGSTAT_BSESSEND(value)))
+#define USB_BWR_OTGSTAT_BSESSEND(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_BSESSEND_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is below the B session valid threshold
+ * - 0b1 - The VBUS voltage is above the B session valid threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_SESS_VLD field. */
+#define USB_RD_OTGSTAT_SESS_VLD(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_SESS_VLD_MASK) >> USB_OTGSTAT_SESS_VLD_SHIFT)
+#define USB_BRD_OTGSTAT_SESS_VLD(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_SESS_VLD_SHIFT))
+
+/*! @brief Set the SESS_VLD field to a new value. */
+#define USB_WR_OTGSTAT_SESS_VLD(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_SESS_VLD_MASK, USB_OTGSTAT_SESS_VLD(value)))
+#define USB_BWR_OTGSTAT_SESS_VLD(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_SESS_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
+ *
+ * Indicates that the internal signals that control the LINE_STATE_CHG field of
+ * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG
+ * field and then read this field. If this field reads as 1, then the value of
+ * LINE_STATE_CHG can be considered stable.
+ *
+ * Values:
+ * - 0b0 - The LINE_STAT_CHG bit is not yet stable.
+ * - 0b1 - The LINE_STAT_CHG bit has been debounced and is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field. */
+#define USB_RD_OTGSTAT_LINESTATESTABLE(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_LINESTATESTABLE_MASK) >> USB_OTGSTAT_LINESTATESTABLE_SHIFT)
+#define USB_BRD_OTGSTAT_LINESTATESTABLE(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_LINESTATESTABLE_SHIFT))
+
+/*! @brief Set the LINESTATESTABLE field to a new value. */
+#define USB_WR_OTGSTAT_LINESTATESTABLE(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_LINESTATESTABLE_MASK, USB_OTGSTAT_LINESTATESTABLE(value)))
+#define USB_BWR_OTGSTAT_LINESTATESTABLE(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_LINESTATESTABLE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW)
+ *
+ * This bit is reserved for the 1ms count, but it is not useful to software.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field. */
+#define USB_RD_OTGSTAT_ONEMSECEN(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_ONEMSECEN_MASK) >> USB_OTGSTAT_ONEMSECEN_SHIFT)
+#define USB_BRD_OTGSTAT_ONEMSECEN(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ONEMSECEN_SHIFT))
+
+/*! @brief Set the ONEMSECEN field to a new value. */
+#define USB_WR_OTGSTAT_ONEMSECEN(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_ONEMSECEN_MASK, USB_OTGSTAT_ONEMSECEN(value)))
+#define USB_BWR_OTGSTAT_ONEMSECEN(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ONEMSECEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field ID[7] (RW)
+ *
+ * Indicates the current state of the ID pin on the USB connector
+ *
+ * Values:
+ * - 0b0 - Indicates a Type A cable is plugged into the USB connector.
+ * - 0b1 - Indicates no cable is attached or a Type B cable is plugged into the
+ *     USB connector.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_ID field. */
+#define USB_RD_OTGSTAT_ID(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_ID_MASK) >> USB_OTGSTAT_ID_SHIFT)
+#define USB_BRD_OTGSTAT_ID(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ID_SHIFT))
+
+/*! @brief Set the ID field to a new value. */
+#define USB_WR_OTGSTAT_ID(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_ID_MASK, USB_OTGSTAT_ID(value)))
+#define USB_BWR_OTGSTAT_ID(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ID_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGCTL - OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGCTL - OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Controls the operation of VBUS and Data Line termination resistors.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGCTL register
+ */
+/*@{*/
+#define USB_RD_OTGCTL(base)      (USB_OTGCTL_REG(base))
+#define USB_WR_OTGCTL(base, value) (USB_OTGCTL_REG(base) = (value))
+#define USB_RMW_OTGCTL(base, mask, value) (USB_WR_OTGCTL(base, (USB_RD_OTGCTL(base) & ~(mask)) | (value)))
+#define USB_SET_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) |  (value)))
+#define USB_CLR_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) & ~(value)))
+#define USB_TOG_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGCTL bitfields
+ */
+
+/*!
+ * @name Register USB_OTGCTL, field OTGEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then
+ *     the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+
+ *     and D- Data Line pull-down resistors are engaged.
+ * - 0b1 - The pull-up and pull-down controls in this register are used.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_OTGEN field. */
+#define USB_RD_OTGCTL_OTGEN(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_OTGEN_MASK) >> USB_OTGCTL_OTGEN_SHIFT)
+#define USB_BRD_OTGCTL_OTGEN(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_OTGEN_SHIFT))
+
+/*! @brief Set the OTGEN field to a new value. */
+#define USB_WR_OTGCTL_OTGEN(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_OTGEN_MASK, USB_OTGCTL_OTGEN(value)))
+#define USB_BWR_OTGCTL_OTGEN(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_OTGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DMLOW[4] (RW)
+ *
+ * Values:
+ * - 0b0 - D- pulldown resistor is not enabled.
+ * - 0b1 - D- pulldown resistor is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DMLOW field. */
+#define USB_RD_OTGCTL_DMLOW(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DMLOW_MASK) >> USB_OTGCTL_DMLOW_SHIFT)
+#define USB_BRD_OTGCTL_DMLOW(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DMLOW_SHIFT))
+
+/*! @brief Set the DMLOW field to a new value. */
+#define USB_WR_OTGCTL_DMLOW(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DMLOW_MASK, USB_OTGCTL_DMLOW(value)))
+#define USB_BWR_OTGCTL_DMLOW(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DMLOW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DPLOW[5] (RW)
+ *
+ * This bit should always be enabled together with bit 4 (DMLOW)
+ *
+ * Values:
+ * - 0b0 - D+ pulldown resistor is not enabled.
+ * - 0b1 - D+ pulldown resistor is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPLOW field. */
+#define USB_RD_OTGCTL_DPLOW(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPLOW_MASK) >> USB_OTGCTL_DPLOW_SHIFT)
+#define USB_BRD_OTGCTL_DPLOW(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPLOW_SHIFT))
+
+/*! @brief Set the DPLOW field to a new value. */
+#define USB_WR_OTGCTL_DPLOW(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPLOW_MASK, USB_OTGCTL_DPLOW(value)))
+#define USB_BWR_OTGCTL_DPLOW(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPLOW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DPHIGH[7] (RW)
+ *
+ * Values:
+ * - 0b0 - D+ pullup resistor is not enabled
+ * - 0b1 - D+ pullup resistor is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPHIGH field. */
+#define USB_RD_OTGCTL_DPHIGH(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPHIGH_MASK) >> USB_OTGCTL_DPHIGH_SHIFT)
+#define USB_BRD_OTGCTL_DPHIGH(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT))
+
+/*! @brief Set the DPHIGH field to a new value. */
+#define USB_WR_OTGCTL_DPHIGH(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPHIGH_MASK, USB_OTGCTL_DPHIGH(value)))
+#define USB_BWR_OTGCTL_DPHIGH(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ISTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ISTAT - Interrupt Status register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains fields for each of the interrupt sources within the USB Module. Each
+ * of these fields are qualified with their respective interrupt enable bits.
+ * All fields of this register are logically OR'd together along with the OTG
+ * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the
+ * processor's interrupt controller. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ISTAT register
+ */
+/*@{*/
+#define USB_RD_ISTAT(base)       (USB_ISTAT_REG(base))
+#define USB_WR_ISTAT(base, value) (USB_ISTAT_REG(base) = (value))
+#define USB_RMW_ISTAT(base, mask, value) (USB_WR_ISTAT(base, (USB_RD_ISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) |  (value)))
+#define USB_CLR_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) & ~(value)))
+#define USB_TOG_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ISTAT, field USBRST[0] (W1C)
+ *
+ * This bit is set when the USB Module has decoded a valid USB reset. This
+ * informs the processor that it should write 0x00 into the address register and
+ * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5
+ * microseconds. It is not asserted again until the USB reset condition has been
+ * removed and then reasserted.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_USBRST field. */
+#define USB_RD_ISTAT_USBRST(base) ((USB_ISTAT_REG(base) & USB_ISTAT_USBRST_MASK) >> USB_ISTAT_USBRST_SHIFT)
+#define USB_BRD_ISTAT_USBRST(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT))
+
+/*! @brief Set the USBRST field to a new value. */
+#define USB_WR_ISTAT_USBRST(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_USBRST(value)))
+#define USB_BWR_ISTAT_USBRST(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ERROR[1] (W1C)
+ *
+ * This bit is set when any of the error conditions within Error Interrupt
+ * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register
+ * to determine the source of the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ERROR field. */
+#define USB_RD_ISTAT_ERROR(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ERROR_MASK) >> USB_ISTAT_ERROR_SHIFT)
+#define USB_BRD_ISTAT_ERROR(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT))
+
+/*! @brief Set the ERROR field to a new value. */
+#define USB_WR_ISTAT_ERROR(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ERROR_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ERROR(value)))
+#define USB_BWR_ISTAT_ERROR(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SOFTOK[2] (W1C)
+ *
+ * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In
+ * Host mode this field is set when the SOF threshold is reached, so that
+ * software can prepare for the next SOF.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SOFTOK field. */
+#define USB_RD_ISTAT_SOFTOK(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SOFTOK_MASK) >> USB_ISTAT_SOFTOK_SHIFT)
+#define USB_BRD_ISTAT_SOFTOK(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT))
+
+/*! @brief Set the SOFTOK field to a new value. */
+#define USB_WR_ISTAT_SOFTOK(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SOFTOK_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SOFTOK(value)))
+#define USB_BWR_ISTAT_SOFTOK(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field TOKDNE[3] (W1C)
+ *
+ * This bit is set when the current token being processed has completed. The
+ * processor must immediately read the STATUS (STAT) register to determine the
+ * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes
+ * STAT to be cleared or the STAT holding register to be loaded into the STAT
+ * register.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_TOKDNE field. */
+#define USB_RD_ISTAT_TOKDNE(base) ((USB_ISTAT_REG(base) & USB_ISTAT_TOKDNE_MASK) >> USB_ISTAT_TOKDNE_SHIFT)
+#define USB_BRD_ISTAT_TOKDNE(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT))
+
+/*! @brief Set the TOKDNE field to a new value. */
+#define USB_WR_ISTAT_TOKDNE(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_TOKDNE_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_TOKDNE(value)))
+#define USB_BWR_ISTAT_TOKDNE(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SLEEP[4] (W1C)
+ *
+ * This bit is set when the USB Module detects a constant idle on the USB bus
+ * for 3 ms. The sleep timer is reset by activity on the USB bus.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SLEEP field. */
+#define USB_RD_ISTAT_SLEEP(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SLEEP_MASK) >> USB_ISTAT_SLEEP_SHIFT)
+#define USB_BRD_ISTAT_SLEEP(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define USB_WR_ISTAT_SLEEP(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SLEEP_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SLEEP(value)))
+#define USB_BWR_ISTAT_SLEEP(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field RESUME[5] (W1C)
+ *
+ * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us.
+ * When not in suspend mode this interrupt must be disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_RESUME field. */
+#define USB_RD_ISTAT_RESUME(base) ((USB_ISTAT_REG(base) & USB_ISTAT_RESUME_MASK) >> USB_ISTAT_RESUME_SHIFT)
+#define USB_BRD_ISTAT_RESUME(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_ISTAT_RESUME(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_RESUME_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_RESUME(value)))
+#define USB_BWR_ISTAT_RESUME(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ATTACH[6] (W1C)
+ *
+ * This bit is set when the USB Module detects an attach of a USB device. This
+ * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a
+ * peripheral is now present and must be configured; it is asserted if there have
+ * been no transitions on the USB for 2.5 us and the current bus state is not SE0."
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ATTACH field. */
+#define USB_RD_ISTAT_ATTACH(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ATTACH_MASK) >> USB_ISTAT_ATTACH_SHIFT)
+#define USB_BRD_ISTAT_ATTACH(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ATTACH_SHIFT))
+
+/*! @brief Set the ATTACH field to a new value. */
+#define USB_WR_ISTAT_ATTACH(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ATTACH_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ATTACH(value)))
+#define USB_BWR_ISTAT_ATTACH(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ATTACH_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field STALL[7] (W1C)
+ *
+ * In Target mode this bit is asserted when a STALL handshake is sent by the
+ * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge
+ * during the handshake phase of a USB transaction.This interrupt can be used to
+ * determine whether the last USB transaction was completed successfully or
+ * stalled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_STALL field. */
+#define USB_RD_ISTAT_STALL(base) ((USB_ISTAT_REG(base) & USB_ISTAT_STALL_MASK) >> USB_ISTAT_STALL_SHIFT)
+#define USB_BRD_ISTAT_STALL(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT))
+
+/*! @brief Set the STALL field to a new value. */
+#define USB_WR_ISTAT_STALL(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_STALL_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK), USB_ISTAT_STALL(value)))
+#define USB_BWR_ISTAT_STALL(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_INTEN - Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_INTEN - Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable fields for each of the interrupt sources within the USB
+ * Module. Setting any of these bits enables the respective interrupt source in the
+ * ISTAT register. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_INTEN register
+ */
+/*@{*/
+#define USB_RD_INTEN(base)       (USB_INTEN_REG(base))
+#define USB_WR_INTEN(base, value) (USB_INTEN_REG(base) = (value))
+#define USB_RMW_INTEN(base, mask, value) (USB_WR_INTEN(base, (USB_RD_INTEN(base) & ~(mask)) | (value)))
+#define USB_SET_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) |  (value)))
+#define USB_CLR_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) & ~(value)))
+#define USB_TOG_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_INTEN bitfields
+ */
+
+/*!
+ * @name Register USB_INTEN, field USBRSTEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the USBRST interrupt.
+ * - 0b1 - Enables the USBRST interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_USBRSTEN field. */
+#define USB_RD_INTEN_USBRSTEN(base) ((USB_INTEN_REG(base) & USB_INTEN_USBRSTEN_MASK) >> USB_INTEN_USBRSTEN_SHIFT)
+#define USB_BRD_INTEN_USBRSTEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT))
+
+/*! @brief Set the USBRSTEN field to a new value. */
+#define USB_WR_INTEN_USBRSTEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_USBRSTEN_MASK, USB_INTEN_USBRSTEN(value)))
+#define USB_BWR_INTEN_USBRSTEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ERROREN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the ERROR interrupt.
+ * - 0b1 - Enables the ERROR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ERROREN field. */
+#define USB_RD_INTEN_ERROREN(base) ((USB_INTEN_REG(base) & USB_INTEN_ERROREN_MASK) >> USB_INTEN_ERROREN_SHIFT)
+#define USB_BRD_INTEN_ERROREN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT))
+
+/*! @brief Set the ERROREN field to a new value. */
+#define USB_WR_INTEN_ERROREN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ERROREN_MASK, USB_INTEN_ERROREN(value)))
+#define USB_BWR_INTEN_ERROREN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SOFTOKEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disbles the SOFTOK interrupt.
+ * - 0b1 - Enables the SOFTOK interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SOFTOKEN field. */
+#define USB_RD_INTEN_SOFTOKEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SOFTOKEN_MASK) >> USB_INTEN_SOFTOKEN_SHIFT)
+#define USB_BRD_INTEN_SOFTOKEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT))
+
+/*! @brief Set the SOFTOKEN field to a new value. */
+#define USB_WR_INTEN_SOFTOKEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SOFTOKEN_MASK, USB_INTEN_SOFTOKEN(value)))
+#define USB_BWR_INTEN_SOFTOKEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field TOKDNEEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the TOKDNE interrupt.
+ * - 0b1 - Enables the TOKDNE interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_TOKDNEEN field. */
+#define USB_RD_INTEN_TOKDNEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_TOKDNEEN_MASK) >> USB_INTEN_TOKDNEEN_SHIFT)
+#define USB_BRD_INTEN_TOKDNEEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT))
+
+/*! @brief Set the TOKDNEEN field to a new value. */
+#define USB_WR_INTEN_TOKDNEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_TOKDNEEN_MASK, USB_INTEN_TOKDNEEN(value)))
+#define USB_BWR_INTEN_TOKDNEEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SLEEPEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the SLEEP interrupt.
+ * - 0b1 - Enables the SLEEP interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SLEEPEN field. */
+#define USB_RD_INTEN_SLEEPEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SLEEPEN_MASK) >> USB_INTEN_SLEEPEN_SHIFT)
+#define USB_BRD_INTEN_SLEEPEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT))
+
+/*! @brief Set the SLEEPEN field to a new value. */
+#define USB_WR_INTEN_SLEEPEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SLEEPEN_MASK, USB_INTEN_SLEEPEN(value)))
+#define USB_BWR_INTEN_SLEEPEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field RESUMEEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the RESUME interrupt.
+ * - 0b1 - Enables the RESUME interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_RESUMEEN field. */
+#define USB_RD_INTEN_RESUMEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_RESUMEEN_MASK) >> USB_INTEN_RESUMEEN_SHIFT)
+#define USB_BRD_INTEN_RESUMEEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT))
+
+/*! @brief Set the RESUMEEN field to a new value. */
+#define USB_WR_INTEN_RESUMEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_RESUMEEN_MASK, USB_INTEN_RESUMEEN(value)))
+#define USB_BWR_INTEN_RESUMEEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ATTACHEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the ATTACH interrupt.
+ * - 0b1 - Enables the ATTACH interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ATTACHEN field. */
+#define USB_RD_INTEN_ATTACHEN(base) ((USB_INTEN_REG(base) & USB_INTEN_ATTACHEN_MASK) >> USB_INTEN_ATTACHEN_SHIFT)
+#define USB_BRD_INTEN_ATTACHEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ATTACHEN_SHIFT))
+
+/*! @brief Set the ATTACHEN field to a new value. */
+#define USB_WR_INTEN_ATTACHEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ATTACHEN_MASK, USB_INTEN_ATTACHEN(value)))
+#define USB_BWR_INTEN_ATTACHEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ATTACHEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field STALLEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Diasbles the STALL interrupt.
+ * - 0b1 - Enables the STALL interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_STALLEN field. */
+#define USB_RD_INTEN_STALLEN(base) ((USB_INTEN_REG(base) & USB_INTEN_STALLEN_MASK) >> USB_INTEN_STALLEN_SHIFT)
+#define USB_BRD_INTEN_STALLEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT))
+
+/*! @brief Set the STALLEN field to a new value. */
+#define USB_WR_INTEN_STALLEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_STALLEN_MASK, USB_INTEN_STALLEN(value)))
+#define USB_BWR_INTEN_STALLEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERRSTAT - Error Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERRSTAT - Error Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error sources within the USB Module.
+ * Each of these bits are qualified with their respective error enable bits. All
+ * bits of this register are logically OR'd together and the result placed in the
+ * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. Each bit is set
+ * as soon as the error condition is detected. Therefore, the interrupt does not
+ * typically correspond with the end of a token being processed. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERRSTAT register
+ */
+/*@{*/
+#define USB_RD_ERRSTAT(base)     (USB_ERRSTAT_REG(base))
+#define USB_WR_ERRSTAT(base, value) (USB_ERRSTAT_REG(base) = (value))
+#define USB_RMW_ERRSTAT(base, mask, value) (USB_WR_ERRSTAT(base, (USB_RD_ERRSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) |  (value)))
+#define USB_CLR_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) & ~(value)))
+#define USB_TOG_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERRSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ERRSTAT, field PIDERR[0] (W1C)
+ *
+ * This bit is set when the PID check field fails.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_PIDERR field. */
+#define USB_RD_ERRSTAT_PIDERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_PIDERR_MASK) >> USB_ERRSTAT_PIDERR_SHIFT)
+#define USB_BRD_ERRSTAT_PIDERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT))
+
+/*! @brief Set the PIDERR field to a new value. */
+#define USB_WR_ERRSTAT_PIDERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_PIDERR(value)))
+#define USB_BWR_ERRSTAT_PIDERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C)
+ *
+ * This error interrupt has two functions. When the USB Module is operating in
+ * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token
+ * packets generated by the host. If set the token packet was rejected due to a
+ * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this
+ * interrupt detects End Of Frame (EOF) error conditions. This occurs when the
+ * USB Module is transmitting or receiving data and the SOF counter reaches zero.
+ * This interrupt is useful when developing USB packet scheduling software to
+ * ensure that no USB transactions cross the start of the next frame.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC5EOF field. */
+#define USB_RD_ERRSTAT_CRC5EOF(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC5EOF_MASK) >> USB_ERRSTAT_CRC5EOF_SHIFT)
+#define USB_BRD_ERRSTAT_CRC5EOF(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5EOF_SHIFT))
+
+/*! @brief Set the CRC5EOF field to a new value. */
+#define USB_WR_ERRSTAT_CRC5EOF(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC5EOF(value)))
+#define USB_BWR_ERRSTAT_CRC5EOF(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5EOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC16[2] (W1C)
+ *
+ * This bit is set when a data packet is rejected due to a CRC16 error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC16 field. */
+#define USB_RD_ERRSTAT_CRC16(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC16_MASK) >> USB_ERRSTAT_CRC16_SHIFT)
+#define USB_BRD_ERRSTAT_CRC16(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT))
+
+/*! @brief Set the CRC16 field to a new value. */
+#define USB_WR_ERRSTAT_CRC16(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC16(value)))
+#define USB_BWR_ERRSTAT_CRC16(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DFN8[3] (W1C)
+ *
+ * This bit is set if the data field received was not 8 bits in length. USB
+ * Specification 1.0 requires that data fields be an integral number of bytes. If the
+ * data field was not an integral number of bytes, this bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DFN8 field. */
+#define USB_RD_ERRSTAT_DFN8(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DFN8_MASK) >> USB_ERRSTAT_DFN8_SHIFT)
+#define USB_BRD_ERRSTAT_DFN8(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT))
+
+/*! @brief Set the DFN8 field to a new value. */
+#define USB_WR_ERRSTAT_DFN8(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DFN8(value)))
+#define USB_BWR_ERRSTAT_DFN8(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTOERR[4] (W1C)
+ *
+ * This bit is set when a bus turnaround timeout error occurs. The USB module
+ * contains a bus turnaround timer that keeps track of the amount of time elapsed
+ * between the token and data phases of a SETUP or OUT TOKEN or the data and
+ * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the
+ * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTOERR field. */
+#define USB_RD_ERRSTAT_BTOERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTOERR_MASK) >> USB_ERRSTAT_BTOERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTOERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT))
+
+/*! @brief Set the BTOERR field to a new value. */
+#define USB_WR_ERRSTAT_BTOERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_BTOERR(value)))
+#define USB_BWR_ERRSTAT_BTOERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DMAERR[5] (W1C)
+ *
+ * This bit is set if the USB Module has requested a DMA access to read a new
+ * BDT but has not been given the bus before it needs to receive or transmit data.
+ * If processing a TX transfer this would cause a transmit data underflow
+ * condition. If processing a RX transfer this would cause a receive data overflow
+ * condition. This interrupt is useful when developing device arbitration hardware for
+ * the microprocessor and the USB module to minimize bus request and bus grant
+ * latency. This bit is also set if a data packet to or from the host is larger
+ * than the buffer size allocated in the BDT. In this case the data packet is
+ * truncated as it is put in buffer memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DMAERR field. */
+#define USB_RD_ERRSTAT_DMAERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DMAERR_MASK) >> USB_ERRSTAT_DMAERR_SHIFT)
+#define USB_BRD_ERRSTAT_DMAERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT))
+
+/*! @brief Set the DMAERR field to a new value. */
+#define USB_WR_ERRSTAT_DMAERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DMAERR(value)))
+#define USB_BWR_ERRSTAT_DMAERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTSERR[7] (W1C)
+ *
+ * This bit is set when a bit stuff error is detected. If set, the corresponding
+ * packet is rejected due to the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTSERR field. */
+#define USB_RD_ERRSTAT_BTSERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTSERR_MASK) >> USB_ERRSTAT_BTSERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTSERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT))
+
+/*! @brief Set the BTSERR field to a new value. */
+#define USB_WR_ERRSTAT_BTSERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTSERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK), USB_ERRSTAT_BTSERR(value)))
+#define USB_BWR_ERRSTAT_BTSERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERREN - Error Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERREN - Error Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error interrupt sources within the USB
+ * module. Setting any of these bits enables the respective interrupt source in
+ * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore,
+ * the interrupt does not typically correspond with the end of a token being
+ * processed. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERREN register
+ */
+/*@{*/
+#define USB_RD_ERREN(base)       (USB_ERREN_REG(base))
+#define USB_WR_ERREN(base, value) (USB_ERREN_REG(base) = (value))
+#define USB_RMW_ERREN(base, mask, value) (USB_WR_ERREN(base, (USB_RD_ERREN(base) & ~(mask)) | (value)))
+#define USB_SET_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) |  (value)))
+#define USB_CLR_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) & ~(value)))
+#define USB_TOG_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERREN bitfields
+ */
+
+/*!
+ * @name Register USB_ERREN, field PIDERREN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the PIDERR interrupt.
+ * - 0b1 - Enters the PIDERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_PIDERREN field. */
+#define USB_RD_ERREN_PIDERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_PIDERREN_MASK) >> USB_ERREN_PIDERREN_SHIFT)
+#define USB_BRD_ERREN_PIDERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT))
+
+/*! @brief Set the PIDERREN field to a new value. */
+#define USB_WR_ERREN_PIDERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_PIDERREN_MASK, USB_ERREN_PIDERREN(value)))
+#define USB_BWR_ERREN_PIDERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC5EOFEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the CRC5/EOF interrupt.
+ * - 0b1 - Enables the CRC5/EOF interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC5EOFEN field. */
+#define USB_RD_ERREN_CRC5EOFEN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC5EOFEN_MASK) >> USB_ERREN_CRC5EOFEN_SHIFT)
+#define USB_BRD_ERREN_CRC5EOFEN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT))
+
+/*! @brief Set the CRC5EOFEN field to a new value. */
+#define USB_WR_ERREN_CRC5EOFEN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC5EOFEN_MASK, USB_ERREN_CRC5EOFEN(value)))
+#define USB_BWR_ERREN_CRC5EOFEN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC16EN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the CRC16 interrupt.
+ * - 0b1 - Enables the CRC16 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC16EN field. */
+#define USB_RD_ERREN_CRC16EN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC16EN_MASK) >> USB_ERREN_CRC16EN_SHIFT)
+#define USB_BRD_ERREN_CRC16EN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT))
+
+/*! @brief Set the CRC16EN field to a new value. */
+#define USB_WR_ERREN_CRC16EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC16EN_MASK, USB_ERREN_CRC16EN(value)))
+#define USB_BWR_ERREN_CRC16EN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DFN8EN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the DFN8 interrupt.
+ * - 0b1 - Enables the DFN8 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DFN8EN field. */
+#define USB_RD_ERREN_DFN8EN(base) ((USB_ERREN_REG(base) & USB_ERREN_DFN8EN_MASK) >> USB_ERREN_DFN8EN_SHIFT)
+#define USB_BRD_ERREN_DFN8EN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT))
+
+/*! @brief Set the DFN8EN field to a new value. */
+#define USB_WR_ERREN_DFN8EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DFN8EN_MASK, USB_ERREN_DFN8EN(value)))
+#define USB_BWR_ERREN_DFN8EN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTOERREN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the BTOERR interrupt.
+ * - 0b1 - Enables the BTOERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTOERREN field. */
+#define USB_RD_ERREN_BTOERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTOERREN_MASK) >> USB_ERREN_BTOERREN_SHIFT)
+#define USB_BRD_ERREN_BTOERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT))
+
+/*! @brief Set the BTOERREN field to a new value. */
+#define USB_WR_ERREN_BTOERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTOERREN_MASK, USB_ERREN_BTOERREN(value)))
+#define USB_BWR_ERREN_BTOERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DMAERREN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the DMAERR interrupt.
+ * - 0b1 - Enables the DMAERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DMAERREN field. */
+#define USB_RD_ERREN_DMAERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_DMAERREN_MASK) >> USB_ERREN_DMAERREN_SHIFT)
+#define USB_BRD_ERREN_DMAERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT))
+
+/*! @brief Set the DMAERREN field to a new value. */
+#define USB_WR_ERREN_DMAERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DMAERREN_MASK, USB_ERREN_DMAERREN(value)))
+#define USB_BWR_ERREN_DMAERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTSERREN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the BTSERR interrupt.
+ * - 0b1 - Enables the BTSERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTSERREN field. */
+#define USB_RD_ERREN_BTSERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTSERREN_MASK) >> USB_ERREN_BTSERREN_SHIFT)
+#define USB_BRD_ERREN_BTSERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT))
+
+/*! @brief Set the BTSERREN field to a new value. */
+#define USB_WR_ERREN_BTSERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTSERREN_MASK, USB_ERREN_BTSERREN(value)))
+#define USB_BWR_ERREN_BTSERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_STAT - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_STAT - Status register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * Reports the transaction status within the USB module. When the processor's
+ * interrupt controller has received a TOKDNE, interrupt the Status Register must
+ * be read to determine the status of the previous endpoint communication. The
+ * data in the status register is valid when TOKDNE interrupt is asserted. The
+ * Status register is actually a read window into a status FIFO maintained by the USB
+ * module. When the USB module uses a BD, it updates the Status register. If
+ * another USB transaction is performed before the TOKDNE interrupt is serviced, the
+ * USB module stores the status of the next transaction in the STAT FIFO. Thus
+ * STAT is actually a four byte FIFO that allows the processor core to process one
+ * transaction while the SIE is processing the next transaction. Clearing the
+ * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents
+ * of the next STAT value. If the data in the STAT holding register is valid, the
+ * SIE immediately reasserts to TOKDNE interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_STAT register
+ */
+/*@{*/
+#define USB_RD_STAT(base)        (USB_STAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_STAT bitfields
+ */
+
+/*!
+ * @name Register USB_STAT, field ODD[2] (RO)
+ *
+ * This bit is set if the last buffer descriptor updated was in the odd bank of
+ * the BDT.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ODD field. */
+#define USB_RD_STAT_ODD(base) ((USB_STAT_REG(base) & USB_STAT_ODD_MASK) >> USB_STAT_ODD_SHIFT)
+#define USB_BRD_STAT_ODD(base) (BITBAND_ACCESS8(&USB_STAT_REG(base), USB_STAT_ODD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field TX[3] (RO)
+ *
+ * Values:
+ * - 0b0 - The most recent transaction was a receive operation.
+ * - 0b1 - The most recent transaction was a transmit operation.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_TX field. */
+#define USB_RD_STAT_TX(base) ((USB_STAT_REG(base) & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT)
+#define USB_BRD_STAT_TX(base) (BITBAND_ACCESS8(&USB_STAT_REG(base), USB_STAT_TX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field ENDP[7:4] (RO)
+ *
+ * This four-bit field encodes the endpoint address that received or transmitted
+ * the previous token. This allows the processor core to determine the BDT entry
+ * that was updated by the last USB transaction.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ENDP field. */
+#define USB_RD_STAT_ENDP(base) ((USB_STAT_REG(base) & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT)
+#define USB_BRD_STAT_ENDP(base) (USB_RD_STAT_ENDP(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CTL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CTL - Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides various control and configuration information for the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_CTL register
+ */
+/*@{*/
+#define USB_RD_CTL(base)         (USB_CTL_REG(base))
+#define USB_WR_CTL(base, value)  (USB_CTL_REG(base) = (value))
+#define USB_RMW_CTL(base, mask, value) (USB_WR_CTL(base, (USB_RD_CTL(base) & ~(mask)) | (value)))
+#define USB_SET_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) |  (value)))
+#define USB_CLR_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) & ~(value)))
+#define USB_TOG_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CTL bitfields
+ */
+
+/*!
+ * @name Register USB_CTL, field USBENSOFEN[0] (RW)
+ *
+ * Setting this bit enables the USB-FS to operate; clearing it disables the
+ * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs.
+ * Therefore, setting this bit resets much of the logic in the SIE. When host mode
+ * is enabled, clearing this bit causes the SIE to stop sending SOF tokens.
+ *
+ * Values:
+ * - 0b0 - Disables the USB Module.
+ * - 0b1 - Enables the USB Module.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_USBENSOFEN field. */
+#define USB_RD_CTL_USBENSOFEN(base) ((USB_CTL_REG(base) & USB_CTL_USBENSOFEN_MASK) >> USB_CTL_USBENSOFEN_SHIFT)
+#define USB_BRD_CTL_USBENSOFEN(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT))
+
+/*! @brief Set the USBENSOFEN field to a new value. */
+#define USB_WR_CTL_USBENSOFEN(base, value) (USB_RMW_CTL(base, USB_CTL_USBENSOFEN_MASK, USB_CTL_USBENSOFEN(value)))
+#define USB_BWR_CTL_USBENSOFEN(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field ODDRST[1] (RW)
+ *
+ * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which
+ * then specifies the EVEN BDT bank.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_ODDRST field. */
+#define USB_RD_CTL_ODDRST(base) ((USB_CTL_REG(base) & USB_CTL_ODDRST_MASK) >> USB_CTL_ODDRST_SHIFT)
+#define USB_BRD_CTL_ODDRST(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT))
+
+/*! @brief Set the ODDRST field to a new value. */
+#define USB_WR_CTL_ODDRST(base, value) (USB_RMW_CTL(base, USB_CTL_ODDRST_MASK, USB_CTL_ODDRST(value)))
+#define USB_BWR_CTL_ODDRST(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field RESUME[2] (RW)
+ *
+ * When set to 1 this bit enables the USB Module to execute resume signaling.
+ * This allows the USB Module to perform remote wake-up. Software must set RESUME
+ * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN
+ * bit is set, the USB module appends a Low Speed End of Packet to the Resume
+ * signaling when the RESUME bit is cleared. For more information on RESUME
+ * signaling see Section 7.1.4.5 of the USB specification version 1.0.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_RESUME field. */
+#define USB_RD_CTL_RESUME(base) ((USB_CTL_REG(base) & USB_CTL_RESUME_MASK) >> USB_CTL_RESUME_SHIFT)
+#define USB_BRD_CTL_RESUME(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESUME_SHIFT))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_CTL_RESUME(base, value) (USB_RMW_CTL(base, USB_CTL_RESUME_MASK, USB_CTL_RESUME(value)))
+#define USB_BWR_CTL_RESUME(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESUME_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field HOSTMODEEN[3] (RW)
+ *
+ * When set to 1, this bit enables the USB Module to operate in Host mode. In
+ * host mode, the USB module performs USB transactions under the programmed control
+ * of the host processor.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_HOSTMODEEN field. */
+#define USB_RD_CTL_HOSTMODEEN(base) ((USB_CTL_REG(base) & USB_CTL_HOSTMODEEN_MASK) >> USB_CTL_HOSTMODEEN_SHIFT)
+#define USB_BRD_CTL_HOSTMODEEN(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_HOSTMODEEN_SHIFT))
+
+/*! @brief Set the HOSTMODEEN field to a new value. */
+#define USB_WR_CTL_HOSTMODEEN(base, value) (USB_RMW_CTL(base, USB_CTL_HOSTMODEEN_MASK, USB_CTL_HOSTMODEEN(value)))
+#define USB_BWR_CTL_HOSTMODEEN(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_HOSTMODEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field RESET[4] (RW)
+ *
+ * Setting this bit enables the USB Module to generate USB reset signaling. This
+ * allows the USB Module to reset USB peripherals. This control signal is only
+ * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the
+ * required amount of time and then clear it to 0 to end reset signaling. For more
+ * information on reset signaling see Section 7.1.4.3 of the USB specification version
+ * 1.0.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_RESET field. */
+#define USB_RD_CTL_RESET(base) ((USB_CTL_REG(base) & USB_CTL_RESET_MASK) >> USB_CTL_RESET_SHIFT)
+#define USB_BRD_CTL_RESET(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESET_SHIFT))
+
+/*! @brief Set the RESET field to a new value. */
+#define USB_WR_CTL_RESET(base, value) (USB_RMW_CTL(base, USB_CTL_RESET_MASK, USB_CTL_RESET(value)))
+#define USB_BWR_CTL_RESET(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW)
+ *
+ * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB
+ * token. Software must not write more token commands to the Token Register when
+ * TOKEN_BUSY is set. Software should check this field before writing any tokens
+ * to the Token Register to ensure that token commands are not lost. In Target
+ * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and
+ * reception. Clearing this bit allows the SIE to continue token processing. This bit
+ * is set by the SIE when a SETUP Token is received allowing software to dequeue
+ * any pending packet transactions in the BDT before resuming token processing.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field. */
+#define USB_RD_CTL_TXSUSPENDTOKENBUSY(base) ((USB_CTL_REG(base) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) >> USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)
+#define USB_BRD_CTL_TXSUSPENDTOKENBUSY(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))
+
+/*! @brief Set the TXSUSPENDTOKENBUSY field to a new value. */
+#define USB_WR_CTL_TXSUSPENDTOKENBUSY(base, value) (USB_RMW_CTL(base, USB_CTL_TXSUSPENDTOKENBUSY_MASK, USB_CTL_TXSUSPENDTOKENBUSY(value)))
+#define USB_BWR_CTL_TXSUSPENDTOKENBUSY(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field SE0[6] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_SE0 field. */
+#define USB_RD_CTL_SE0(base) ((USB_CTL_REG(base) & USB_CTL_SE0_MASK) >> USB_CTL_SE0_SHIFT)
+#define USB_BRD_CTL_SE0(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT))
+
+/*! @brief Set the SE0 field to a new value. */
+#define USB_WR_CTL_SE0(base, value) (USB_RMW_CTL(base, USB_CTL_SE0_MASK, USB_CTL_SE0(value)))
+#define USB_BWR_CTL_SE0(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field JSTATE[7] (RW)
+ *
+ * The polarity of this signal is affected by the current state of LSEN .
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_JSTATE field. */
+#define USB_RD_CTL_JSTATE(base) ((USB_CTL_REG(base) & USB_CTL_JSTATE_MASK) >> USB_CTL_JSTATE_SHIFT)
+#define USB_BRD_CTL_JSTATE(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT))
+
+/*! @brief Set the JSTATE field to a new value. */
+#define USB_WR_CTL_JSTATE(base, value) (USB_RMW_CTL(base, USB_CTL_JSTATE_MASK, USB_CTL_JSTATE(value)))
+#define USB_BWR_CTL_JSTATE(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDR - Address register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDR - Address register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Holds the unique USB address that the USB module decodes when in Peripheral
+ * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module
+ * transmits this address with a TOKEN packet. This enables the USB module to
+ * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1.
+ * The Address register is reset to 0x00 after the reset input becomes active or
+ * the USB module decodes a USB reset signal. This action initializes the Address
+ * register to decode address 0x00 as required by the USB specification.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDR register
+ */
+/*@{*/
+#define USB_RD_ADDR(base)        (USB_ADDR_REG(base))
+#define USB_WR_ADDR(base, value) (USB_ADDR_REG(base) = (value))
+#define USB_RMW_ADDR(base, mask, value) (USB_WR_ADDR(base, (USB_RD_ADDR(base) & ~(mask)) | (value)))
+#define USB_SET_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) |  (value)))
+#define USB_CLR_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) & ~(value)))
+#define USB_TOG_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDR bitfields
+ */
+
+/*!
+ * @name Register USB_ADDR, field ADDR[6:0] (RW)
+ *
+ * Defines the USB address that the USB module decodes in peripheral mode, or
+ * transmits when in host mode.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_ADDR field. */
+#define USB_RD_ADDR_ADDR(base) ((USB_ADDR_REG(base) & USB_ADDR_ADDR_MASK) >> USB_ADDR_ADDR_SHIFT)
+#define USB_BRD_ADDR_ADDR(base) (USB_RD_ADDR_ADDR(base))
+
+/*! @brief Set the ADDR field to a new value. */
+#define USB_WR_ADDR_ADDR(base, value) (USB_RMW_ADDR(base, USB_ADDR_ADDR_MASK, USB_ADDR_ADDR(value)))
+#define USB_BWR_ADDR_ADDR(base, value) (USB_WR_ADDR_ADDR(base, value))
+/*@}*/
+
+/*!
+ * @name Register USB_ADDR, field LSEN[7] (RW)
+ *
+ * Informs the USB module that the next token command written to the token
+ * register must be performed at low speed. This enables the USB module to perform the
+ * necessary preamble required for low-speed data transmissions.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_LSEN field. */
+#define USB_RD_ADDR_LSEN(base) ((USB_ADDR_REG(base) & USB_ADDR_LSEN_MASK) >> USB_ADDR_LSEN_SHIFT)
+#define USB_BRD_ADDR_LSEN(base) (BITBAND_ACCESS8(&USB_ADDR_REG(base), USB_ADDR_LSEN_SHIFT))
+
+/*! @brief Set the LSEN field to a new value. */
+#define USB_WR_ADDR_LSEN(base, value) (USB_RMW_ADDR(base, USB_ADDR_LSEN_MASK, USB_ADDR_LSEN(value)))
+#define USB_BWR_ADDR_LSEN(base, value) (BITBAND_ACCESS8(&USB_ADDR_REG(base), USB_ADDR_LSEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE1 - BDT Page register 1
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE1 - BDT Page register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides address bits 15 through 9 of the base address where the current
+ * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor
+ * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so
+ * bits 8 through 0 of the base address are always zero.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE1 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE1(base)    (USB_BDTPAGE1_REG(base))
+#define USB_WR_BDTPAGE1(base, value) (USB_BDTPAGE1_REG(base) = (value))
+#define USB_RMW_BDTPAGE1(base, mask, value) (USB_WR_BDTPAGE1(base, (USB_RD_BDTPAGE1(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) |  (value)))
+#define USB_CLR_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) & ~(value)))
+#define USB_TOG_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_BDTPAGE1 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW)
+ *
+ * Provides address bits 15 through 9 of the BDT base address.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_BDTPAGE1_BDTBA field. */
+#define USB_RD_BDTPAGE1_BDTBA(base) ((USB_BDTPAGE1_REG(base) & USB_BDTPAGE1_BDTBA_MASK) >> USB_BDTPAGE1_BDTBA_SHIFT)
+#define USB_BRD_BDTPAGE1_BDTBA(base) (USB_RD_BDTPAGE1_BDTBA(base))
+
+/*! @brief Set the BDTBA field to a new value. */
+#define USB_WR_BDTPAGE1_BDTBA(base, value) (USB_RMW_BDTPAGE1(base, USB_BDTPAGE1_BDTBA_MASK, USB_BDTPAGE1_BDTBA(value)))
+#define USB_BWR_BDTPAGE1_BDTBA(base, value) (USB_WR_BDTPAGE1_BDTBA(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUML - Frame Number register Low
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUML - Frame Number register Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUML register
+ */
+/*@{*/
+#define USB_RD_FRMNUML(base)     (USB_FRMNUML_REG(base))
+#define USB_WR_FRMNUML(base, value) (USB_FRMNUML_REG(base) = (value))
+#define USB_RMW_FRMNUML(base, mask, value) (USB_WR_FRMNUML(base, (USB_RD_FRMNUML(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) |  (value)))
+#define USB_CLR_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) & ~(value)))
+#define USB_TOG_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUMH - Frame Number register High
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUMH - Frame Number register High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUMH register
+ */
+/*@{*/
+#define USB_RD_FRMNUMH(base)     (USB_FRMNUMH_REG(base))
+#define USB_WR_FRMNUMH(base, value) (USB_FRMNUMH_REG(base) = (value))
+#define USB_RMW_FRMNUMH(base, mask, value) (USB_WR_FRMNUMH(base, (USB_RD_FRMNUMH(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) |  (value)))
+#define USB_CLR_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) & ~(value)))
+#define USB_TOG_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_FRMNUMH bitfields
+ */
+
+/*!
+ * @name Register USB_FRMNUMH, field FRM[2:0] (RW)
+ *
+ * This 3-bit field and the 8-bit field in the Frame Number Register Low are
+ * used to compute the address where the current Buffer Descriptor Table (BDT)
+ * resides in system memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_FRMNUMH_FRM field. */
+#define USB_RD_FRMNUMH_FRM(base) ((USB_FRMNUMH_REG(base) & USB_FRMNUMH_FRM_MASK) >> USB_FRMNUMH_FRM_SHIFT)
+#define USB_BRD_FRMNUMH_FRM(base) (USB_RD_FRMNUMH_FRM(base))
+
+/*! @brief Set the FRM field to a new value. */
+#define USB_WR_FRMNUMH_FRM(base, value) (USB_RMW_FRMNUMH(base, USB_FRMNUMH_FRM_MASK, USB_FRMNUMH_FRM(value)))
+#define USB_BWR_FRMNUMH_FRM(base, value) (USB_WR_FRMNUMH_FRM(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_TOKEN - Token register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_TOKEN - Token register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the
+ * software needs to execute a USB transaction to a peripheral, it writes the
+ * TOKEN type and endpoint to this register. After this register has been written,
+ * the USB module begins the specified USB transaction to the address contained in
+ * the address register. The processor core must always check that the
+ * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register.
+ * This ensures that the token commands are not overwritten before they can be
+ * executed. The address register and endpoint control register 0 are also used when
+ * performing a token command and therefore must also be written before the
+ * Token Register. The address register is used to select the USB peripheral address
+ * transmitted by the token command. The endpoint control register determines the
+ * handshake and retry policies used during the transfer.
+ */
+/*!
+ * @name Constants and macros for entire USB_TOKEN register
+ */
+/*@{*/
+#define USB_RD_TOKEN(base)       (USB_TOKEN_REG(base))
+#define USB_WR_TOKEN(base, value) (USB_TOKEN_REG(base) = (value))
+#define USB_RMW_TOKEN(base, mask, value) (USB_WR_TOKEN(base, (USB_RD_TOKEN(base) & ~(mask)) | (value)))
+#define USB_SET_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) |  (value)))
+#define USB_CLR_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) & ~(value)))
+#define USB_TOG_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_TOKEN bitfields
+ */
+
+/*!
+ * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW)
+ *
+ * Holds the Endpoint address for the token command. The four bit value written
+ * must be a valid endpoint.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_TOKEN_TOKENENDPT field. */
+#define USB_RD_TOKEN_TOKENENDPT(base) ((USB_TOKEN_REG(base) & USB_TOKEN_TOKENENDPT_MASK) >> USB_TOKEN_TOKENENDPT_SHIFT)
+#define USB_BRD_TOKEN_TOKENENDPT(base) (USB_RD_TOKEN_TOKENENDPT(base))
+
+/*! @brief Set the TOKENENDPT field to a new value. */
+#define USB_WR_TOKEN_TOKENENDPT(base, value) (USB_RMW_TOKEN(base, USB_TOKEN_TOKENENDPT_MASK, USB_TOKEN_TOKENENDPT(value)))
+#define USB_BWR_TOKEN_TOKENENDPT(base, value) (USB_WR_TOKEN_TOKENENDPT(base, value))
+/*@}*/
+
+/*!
+ * @name Register USB_TOKEN, field TOKENPID[7:4] (RW)
+ *
+ * Contains the token type executed by the USB module.
+ *
+ * Values:
+ * - 0b0001 - OUT Token. USB Module performs an OUT (TX) transaction.
+ * - 0b1001 - IN Token. USB Module performs an In (RX) transaction.
+ * - 0b1101 - SETUP Token. USB Module performs a SETUP (TX) transaction
+ */
+/*@{*/
+/*! @brief Read current value of the USB_TOKEN_TOKENPID field. */
+#define USB_RD_TOKEN_TOKENPID(base) ((USB_TOKEN_REG(base) & USB_TOKEN_TOKENPID_MASK) >> USB_TOKEN_TOKENPID_SHIFT)
+#define USB_BRD_TOKEN_TOKENPID(base) (USB_RD_TOKEN_TOKENPID(base))
+
+/*! @brief Set the TOKENPID field to a new value. */
+#define USB_WR_TOKEN_TOKENPID(base, value) (USB_RMW_TOKEN(base, USB_TOKEN_TOKENPID_MASK, USB_TOKEN_TOKENPID(value)))
+#define USB_BWR_TOKEN_TOKENPID(base, value) (USB_WR_TOKEN_TOKENPID(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_SOFTHLD - SOF Threshold register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_SOFTHLD - SOF Threshold register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in
+ * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The
+ * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with
+ * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF)
+ * token is transmitted. The SOF threshold register is used to program the number
+ * of USB byte times before the SOF to stop initiating token packet transactions.
+ * This register must be set to a value that ensures that other packets are not
+ * actively being transmitted when the SOF time counts to zero. When the SOF
+ * counter reaches the threshold value, no more tokens are transmitted until after the
+ * SOF has been transmitted. The value programmed into the threshold register
+ * must reserve enough time to ensure the worst case transaction completes. In
+ * general the worst case transaction is an IN token followed by a data packet from
+ * the target followed by the response from the host. The actual time required is
+ * a function of the maximum packet size on the bus. Typical values for the SOF
+ * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26;
+ * 8-byte packets=18.
+ */
+/*!
+ * @name Constants and macros for entire USB_SOFTHLD register
+ */
+/*@{*/
+#define USB_RD_SOFTHLD(base)     (USB_SOFTHLD_REG(base))
+#define USB_WR_SOFTHLD(base, value) (USB_SOFTHLD_REG(base) = (value))
+#define USB_RMW_SOFTHLD(base, mask, value) (USB_WR_SOFTHLD(base, (USB_RD_SOFTHLD(base) & ~(mask)) | (value)))
+#define USB_SET_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) |  (value)))
+#define USB_CLR_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) & ~(value)))
+#define USB_TOG_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE2 - BDT Page Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE2 - BDT Page Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE2 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE2(base)    (USB_BDTPAGE2_REG(base))
+#define USB_WR_BDTPAGE2(base, value) (USB_BDTPAGE2_REG(base) = (value))
+#define USB_RMW_BDTPAGE2(base, mask, value) (USB_WR_BDTPAGE2(base, (USB_RD_BDTPAGE2(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) |  (value)))
+#define USB_CLR_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) & ~(value)))
+#define USB_TOG_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE3 - BDT Page Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE3 - BDT Page Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE3 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE3(base)    (USB_BDTPAGE3_REG(base))
+#define USB_WR_BDTPAGE3(base, value) (USB_BDTPAGE3_REG(base) = (value))
+#define USB_RMW_BDTPAGE3(base, mask, value) (USB_WR_BDTPAGE3(base, (USB_RD_BDTPAGE3(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) |  (value)))
+#define USB_CLR_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) & ~(value)))
+#define USB_TOG_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ENDPT - Endpoint Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ENDPT - Endpoint Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains the endpoint control bits for each of the 16 endpoints available
+ * within the USB module for a decoded address. The format for these registers is
+ * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control
+ * pipe 0, which is required for all USB functions. Therefore, after a USBRST
+ * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode
+ * ENDPT0 is used to determine the handshake, retry and low speed
+ * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
+ * bit should be 1. For Isochronous transfers it should be 0. Common values to
+ * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
+ * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and
+ * EPTXEN define if an endpoint is enabled and define the direction of the endpoint.
+ * The endpoint enable/direction control is defined in the following table.
+ * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint
+ * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only
+ * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and
+ * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP)
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire USB_ENDPT register
+ */
+/*@{*/
+#define USB_RD_ENDPT(base, index) (USB_ENDPT_REG(base, index))
+#define USB_WR_ENDPT(base, index, value) (USB_ENDPT_REG(base, index) = (value))
+#define USB_RMW_ENDPT(base, index, mask, value) (USB_WR_ENDPT(base, index, (USB_RD_ENDPT(base, index) & ~(mask)) | (value)))
+#define USB_SET_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) |  (value)))
+#define USB_CLR_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) & ~(value)))
+#define USB_TOG_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ENDPT bitfields
+ */
+
+/*!
+ * @name Register USB_ENDPT, field EPHSHK[0] (RW)
+ *
+ * When set this bit enables an endpoint to perform handshaking during a
+ * transaction to this endpoint. This bit is generally 1 unless the endpoint is
+ * Isochronous.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPHSHK field. */
+#define USB_RD_ENDPT_EPHSHK(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPHSHK_MASK) >> USB_ENDPT_EPHSHK_SHIFT)
+#define USB_BRD_ENDPT_EPHSHK(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT))
+
+/*! @brief Set the EPHSHK field to a new value. */
+#define USB_WR_ENDPT_EPHSHK(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPHSHK_MASK, USB_ENDPT_EPHSHK(value)))
+#define USB_BWR_ENDPT_EPHSHK(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPSTALL[1] (RW)
+ *
+ * When set this bit indicates that the endpoint is called. This bit has
+ * priority over all other control bits in the EndPoint Enable Register, but it is only
+ * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB
+ * Module to return a STALL handshake. After an endpoint is stalled it requires
+ * intervention from the Host Controller.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPSTALL field. */
+#define USB_RD_ENDPT_EPSTALL(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPSTALL_MASK) >> USB_ENDPT_EPSTALL_SHIFT)
+#define USB_BRD_ENDPT_EPSTALL(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT))
+
+/*! @brief Set the EPSTALL field to a new value. */
+#define USB_WR_ENDPT_EPSTALL(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPSTALL_MASK, USB_ENDPT_EPSTALL(value)))
+#define USB_BWR_ENDPT_EPSTALL(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPTXEN[2] (RW)
+ *
+ * This bit, when set, enables the endpoint for TX transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPTXEN field. */
+#define USB_RD_ENDPT_EPTXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPTXEN_MASK) >> USB_ENDPT_EPTXEN_SHIFT)
+#define USB_BRD_ENDPT_EPTXEN(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT))
+
+/*! @brief Set the EPTXEN field to a new value. */
+#define USB_WR_ENDPT_EPTXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPTXEN_MASK, USB_ENDPT_EPTXEN(value)))
+#define USB_BWR_ENDPT_EPTXEN(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPRXEN[3] (RW)
+ *
+ * This bit, when set, enables the endpoint for RX transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPRXEN field. */
+#define USB_RD_ENDPT_EPRXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPRXEN_MASK) >> USB_ENDPT_EPRXEN_SHIFT)
+#define USB_BRD_ENDPT_EPRXEN(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT))
+
+/*! @brief Set the EPRXEN field to a new value. */
+#define USB_WR_ENDPT_EPRXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPRXEN_MASK, USB_ENDPT_EPRXEN(value)))
+#define USB_BWR_ENDPT_EPRXEN(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPCTLDIS[4] (RW)
+ *
+ * This bit, when set, disables control (SETUP) transfers. When cleared, control
+ * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
+ * are also set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPCTLDIS field. */
+#define USB_RD_ENDPT_EPCTLDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPCTLDIS_MASK) >> USB_ENDPT_EPCTLDIS_SHIFT)
+#define USB_BRD_ENDPT_EPCTLDIS(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT))
+
+/*! @brief Set the EPCTLDIS field to a new value. */
+#define USB_WR_ENDPT_EPCTLDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPCTLDIS_MASK, USB_ENDPT_EPCTLDIS(value)))
+#define USB_BWR_ENDPT_EPCTLDIS(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field RETRYDIS[6] (RW)
+ *
+ * This is a Host mode only bit and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed
+ * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID
+ * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When
+ * this bit is cleared, NAKed transactions are retried in hardware. This bit must
+ * be set when the host is attempting to poll an interrupt endpoint.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_RETRYDIS field. */
+#define USB_RD_ENDPT_RETRYDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_RETRYDIS_MASK) >> USB_ENDPT_RETRYDIS_SHIFT)
+#define USB_BRD_ENDPT_RETRYDIS(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_RETRYDIS_SHIFT))
+
+/*! @brief Set the RETRYDIS field to a new value. */
+#define USB_WR_ENDPT_RETRYDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_RETRYDIS_MASK, USB_ENDPT_RETRYDIS(value)))
+#define USB_BWR_ENDPT_RETRYDIS(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_RETRYDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field HOSTWOHUB[7] (RW)
+ *
+ * This is a Host mode only field and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a
+ * directly connected low speed device. When cleared, the host produces the
+ * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed
+ * device as required to communicate with a low speed device through a hub.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_HOSTWOHUB field. */
+#define USB_RD_ENDPT_HOSTWOHUB(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_HOSTWOHUB_MASK) >> USB_ENDPT_HOSTWOHUB_SHIFT)
+#define USB_BRD_ENDPT_HOSTWOHUB(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_HOSTWOHUB_SHIFT))
+
+/*! @brief Set the HOSTWOHUB field to a new value. */
+#define USB_WR_ENDPT_HOSTWOHUB(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_HOSTWOHUB_MASK, USB_ENDPT_HOSTWOHUB(value)))
+#define USB_BWR_ENDPT_HOSTWOHUB(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_HOSTWOHUB_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBCTRL - USB Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBCTRL - USB Control register (RW)
+ *
+ * Reset value: 0xC0U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBCTRL register
+ */
+/*@{*/
+#define USB_RD_USBCTRL(base)     (USB_USBCTRL_REG(base))
+#define USB_WR_USBCTRL(base, value) (USB_USBCTRL_REG(base) = (value))
+#define USB_RMW_USBCTRL(base, mask, value) (USB_WR_USBCTRL(base, (USB_RD_USBCTRL(base) & ~(mask)) | (value)))
+#define USB_SET_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) |  (value)))
+#define USB_CLR_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) & ~(value)))
+#define USB_TOG_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBCTRL bitfields
+ */
+
+/*!
+ * @name Register USB_USBCTRL, field PDE[6] (RW)
+ *
+ * Enables the weak pulldowns on the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - Weak pulldowns are disabled on D+ and D-.
+ * - 0b1 - Weak pulldowns are enabled on D+ and D-.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_PDE field. */
+#define USB_RD_USBCTRL_PDE(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_PDE_MASK) >> USB_USBCTRL_PDE_SHIFT)
+#define USB_BRD_USBCTRL_PDE(base) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT))
+
+/*! @brief Set the PDE field to a new value. */
+#define USB_WR_USBCTRL_PDE(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_PDE_MASK, USB_USBCTRL_PDE(value)))
+#define USB_BWR_USBCTRL_PDE(base, value) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_USBCTRL, field SUSP[7] (RW)
+ *
+ * Places the USB transceiver into the suspend state.
+ *
+ * Values:
+ * - 0b0 - USB transceiver is not in suspend state.
+ * - 0b1 - USB transceiver is in suspend state.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_SUSP field. */
+#define USB_RD_USBCTRL_SUSP(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_SUSP_MASK) >> USB_USBCTRL_SUSP_SHIFT)
+#define USB_BRD_USBCTRL_SUSP(base) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT))
+
+/*! @brief Set the SUSP field to a new value. */
+#define USB_WR_USBCTRL_SUSP(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_SUSP_MASK, USB_USBCTRL_SUSP(value)))
+#define USB_BWR_USBCTRL_SUSP(base, value) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OBSERVE - USB OTG Observe register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OBSERVE - USB OTG Observe register (RO)
+ *
+ * Reset value: 0x50U
+ *
+ * Provides visibility on the state of the pull-ups and pull-downs at the
+ * transceiver. Useful when interfacing to an external OTG control module via a serial
+ * interface.
+ */
+/*!
+ * @name Constants and macros for entire USB_OBSERVE register
+ */
+/*@{*/
+#define USB_RD_OBSERVE(base)     (USB_OBSERVE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OBSERVE bitfields
+ */
+
+/*!
+ * @name Register USB_OBSERVE, field DMPD[4] (RO)
+ *
+ * Provides observability of the D- Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D- pulldown disabled.
+ * - 0b1 - D- pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DMPD field. */
+#define USB_RD_OBSERVE_DMPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DMPD_MASK) >> USB_OBSERVE_DMPD_SHIFT)
+#define USB_BRD_OBSERVE_DMPD(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DMPD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPD[6] (RO)
+ *
+ * Provides observability of the D+ Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D+ pulldown disabled.
+ * - 0b1 - D+ pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPD field. */
+#define USB_RD_OBSERVE_DPPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPD_MASK) >> USB_OBSERVE_DPPD_SHIFT)
+#define USB_BRD_OBSERVE_DPPD(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPU[7] (RO)
+ *
+ * Provides observability of the D+ Pullup enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D+ pullup disabled.
+ * - 0b1 - D+ pullup enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPU field. */
+#define USB_RD_OBSERVE_DPPU(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPU_MASK) >> USB_OBSERVE_DPPU_SHIFT)
+#define USB_BRD_OBSERVE_DPPU(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPU_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CONTROL - USB OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CONTROL - USB OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_CONTROL register
+ */
+/*@{*/
+#define USB_RD_CONTROL(base)     (USB_CONTROL_REG(base))
+#define USB_WR_CONTROL(base, value) (USB_CONTROL_REG(base) = (value))
+#define USB_RMW_CONTROL(base, mask, value) (USB_WR_CONTROL(base, (USB_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USB_SET_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) |  (value)))
+#define USB_CLR_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) & ~(value)))
+#define USB_TOG_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW)
+ *
+ * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG
+ * device mode.
+ *
+ * Values:
+ * - 0b0 - DP Pullup in non-OTG device mode is not enabled.
+ * - 0b1 - DP Pullup in non-OTG device mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field. */
+#define USB_RD_CONTROL_DPPULLUPNONOTG(base) ((USB_CONTROL_REG(base) & USB_CONTROL_DPPULLUPNONOTG_MASK) >> USB_CONTROL_DPPULLUPNONOTG_SHIFT)
+#define USB_BRD_CONTROL_DPPULLUPNONOTG(base) (BITBAND_ACCESS8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT))
+
+/*! @brief Set the DPPULLUPNONOTG field to a new value. */
+#define USB_WR_CONTROL_DPPULLUPNONOTG(base, value) (USB_RMW_CONTROL(base, USB_CONTROL_DPPULLUPNONOTG_MASK, USB_CONTROL_DPPULLUPNONOTG(value)))
+#define USB_BWR_CONTROL_DPPULLUPNONOTG(base, value) (BITBAND_ACCESS8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBTRC0 - USB Transceiver Control register 0
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBTRC0 - USB Transceiver Control register 0 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Includes signals for basic operation of the on-chip USB Full Speed
+ * transceiver and configuration of the USB data connection that are not otherwise included
+ * in the USB Full Speed controller registers.
+ */
+/*!
+ * @name Constants and macros for entire USB_USBTRC0 register
+ */
+/*@{*/
+#define USB_RD_USBTRC0(base)     (USB_USBTRC0_REG(base))
+#define USB_WR_USBTRC0(base, value) (USB_USBTRC0_REG(base) = (value))
+#define USB_RMW_USBTRC0(base, mask, value) (USB_WR_USBTRC0(base, (USB_RD_USBTRC0(base) & ~(mask)) | (value)))
+#define USB_SET_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) |  (value)))
+#define USB_CLR_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) & ~(value)))
+#define USB_TOG_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBTRC0 bitfields
+ */
+
+/*!
+ * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No interrupt was generated.
+ * - 0b1 - Interrupt was generated because of the USB asynchronous interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field. */
+#define USB_RD_USBTRC0_USB_RESUME_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_RESUME_INT_MASK) >> USB_USBTRC0_USB_RESUME_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_RESUME_INT(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_RESUME_INT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field SYNC_DET[1] (RO)
+ *
+ * Values:
+ * - 0b0 - Synchronous interrupt has not been detected.
+ * - 0b1 - Synchronous interrupt has been detected.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_SYNC_DET field. */
+#define USB_RD_USBTRC0_SYNC_DET(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_SYNC_DET_MASK) >> USB_USBTRC0_SYNC_DET_SHIFT)
+#define USB_BRD_USBTRC0_SYNC_DET(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_SYNC_DET_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO)
+ *
+ * This read-only field will be set to value high at 1'b1 when any of USB clock
+ * recovery interrupt conditions are detected and those interrupts are unmasked.
+ * For customer use the only unmasked USB clock recovery interrupt condition
+ * results from an overflow of the frequency trim setting values indicating that the
+ * frequency trim calculated is out of the adjustment range of the IRC48M output
+ * clock. To clear this bit after it has been set, Write 0xFF to register
+ * USB_CLK_RECOVER_INT_STATUS.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field. */
+#define USB_RD_USBTRC0_USB_CLK_RECOVERY_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) >> USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_CLK_RECOVERY_INT(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESMEN[5] (RW)
+ *
+ * This bit, when set, allows the USB module to send an asynchronous wakeup
+ * event to the MCU upon detection of resume signaling on the USB bus. The MCU then
+ * re-enables clocks to the USB module. It is used for low-power suspend mode when
+ * USB module clocks are stopped or the USB transceiver is in Suspend mode.
+ * Async wakeup only works in device mode.
+ *
+ * Values:
+ * - 0b0 - USB asynchronous wakeup from suspend mode disabled.
+ * - 0b1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous
+ *     resume interrupt differs from the synchronous resume interrupt in that it
+ *     asynchronously detects K-state using the unfiltered state of the D+ and D-
+ *     pins. This interrupt should only be enabled when the Transceiver is
+ *     suspended.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USBRESMEN field. */
+#define USB_RD_USBTRC0_USBRESMEN(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USBRESMEN_MASK) >> USB_USBTRC0_USBRESMEN_SHIFT)
+#define USB_BRD_USBTRC0_USBRESMEN(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT))
+
+/*! @brief Set the USBRESMEN field to a new value. */
+#define USB_WR_USBTRC0_USBRESMEN(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESMEN_MASK, USB_USBTRC0_USBRESMEN(value)))
+#define USB_BWR_USBTRC0_USBRESMEN(base, value) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESET[7] (WO)
+ *
+ * Generates a hard reset to USBOTG. After this bit is set and the reset occurs,
+ * this bit is automatically cleared. This bit is always read as zero. Wait two
+ * USB clock cycles after setting this bit.
+ *
+ * Values:
+ * - 0b0 - Normal USB module operation.
+ * - 0b1 - Returns the USB module to its reset state.
+ */
+/*@{*/
+/*! @brief Set the USBRESET field to a new value. */
+#define USB_WR_USBTRC0_USBRESET(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESET_MASK, USB_USBTRC0_USBRESET(value)))
+#define USB_BWR_USBTRC0_USBRESET(base, value) (USB_WR_USBTRC0_USBRESET(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBFRMADJUST - Frame Adjust Register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBFRMADJUST - Frame Adjust Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBFRMADJUST register
+ */
+/*@{*/
+#define USB_RD_USBFRMADJUST(base) (USB_USBFRMADJUST_REG(base))
+#define USB_WR_USBFRMADJUST(base, value) (USB_USBFRMADJUST_REG(base) = (value))
+#define USB_RMW_USBFRMADJUST(base, mask, value) (USB_WR_USBFRMADJUST(base, (USB_RD_USBFRMADJUST(base) & ~(mask)) | (value)))
+#define USB_SET_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) |  (value)))
+#define USB_CLR_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) & ~(value)))
+#define USB_TOG_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Signals in this register control the crystal-less USB clock mode in which the
+ * internal IRC48M oscillator is tuned to match the clock extracted from the
+ * incoming USB data stream. The IRC48M internal oscillator module must be enabled
+ * in register USB_CLK_RECOVER_IRC_EN for this mode.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_CTRL(base) (USB_CLK_RECOVER_CTRL_REG(base))
+#define USB_WR_CLK_RECOVER_CTRL(base, value) (USB_CLK_RECOVER_CTRL_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_CTRL(base, mask, value) (USB_WR_CLK_RECOVER_CTRL(base, (USB_RD_CLK_RECOVER_CTRL(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW)
+ *
+ * IRC48 has a default trim fine value whose default value is factory trimmed
+ * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz
+ * and keeps updating the trim fine value accordingly
+ *
+ * Values:
+ * - 0b0 - Trim fine adjustment always works based on the previous updated trim
+ *     fine value (default)
+ * - 0b1 - Trim fine restarts from the IFR trim value whenever
+ *     bus_reset/bus_resume is detected or module enable is desasserted
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))
+
+/*! @brief Set the RESTART_IFRTRIM_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW)
+ *
+ * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock.
+ * It has two phases after user enables clock_recover_en bit, rough phase and
+ * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine
+ * value is different during these two phases. The step in rough phase is larger
+ * than that in tracking phase. Switch back to rough stage whenever USB bus reset
+ * or bus resume occurs.
+ *
+ * Values:
+ * - 0b0 - Always works in tracking phase after the 1st time rough to track
+ *     transition (default)
+ * - 0b1 - Go back to rough stage whenever bus reset or bus resume occurs
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))
+
+/*! @brief Set the RESET_RESUME_ROUGH_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW)
+ *
+ * This bit must be enabled if user wants to use the crystal-less USB mode for
+ * the Full Speed USB controller and transceiver. This bit should not be set for
+ * USB host mode or OTG.
+ *
+ * Values:
+ * - 0b0 - Disable clock recovery block (default)
+ * - 0b1 - Enable clock recovery block
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) >> USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))
+
+/*! @brief Set the CLOCK_RECOVER_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * Controls basic operation of the on-chip IRC48M module used to produce nominal
+ * 48MHz clocks for USB crystal-less operation and other functions. See
+ * additional information about the IRC48M operation in the Clock Distribution chapter.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_IRC_EN(base) (USB_CLK_RECOVER_IRC_EN_REG(base))
+#define USB_WR_CLK_RECOVER_IRC_EN(base, value) (USB_CLK_RECOVER_IRC_EN_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_IRC_EN(base, mask, value) (USB_WR_CLK_RECOVER_IRC_EN(base, (USB_RD_CLK_RECOVER_IRC_EN(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW)
+ *
+ * This bit is used to enable the local analog regulator for IRC48Mhz module.
+ * This bit must be set if user wants to use the crystal-less USB clock
+ * configuration.
+ *
+ * Values:
+ * - 0b0 - IRC48M local regulator is disabled
+ * - 0b1 - IRC48M local regulator is enabled (default)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_REG_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_REG_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))
+
+/*! @brief Set the REG_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_REG_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_REG_EN_MASK, USB_CLK_RECOVER_IRC_EN_REG_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_REG_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
+ *
+ * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
+ * crystal-less USB. It can only be used for FS USB device mode operation. This
+ * bit must be set before using the crystal-less USB clock configuration.
+ *
+ * Values:
+ * - 0b0 - Disable the IRC48M module (default)
+ * - 0b1 - Enable the IRC48M module
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_IRC_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_IRC_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))
+
+/*! @brief Set the IRC_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK, USB_CLK_RECOVER_IRC_EN_IRC_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * A Write operation with value high at 1'b1 on any combination of individual
+ * bits will clear those bits.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_INT_STATUS(base) (USB_CLK_RECOVER_INT_STATUS_REG(base))
+#define USB_WR_CLK_RECOVER_INT_STATUS(base, value) (USB_CLK_RECOVER_INT_STATUS_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_INT_STATUS(base, mask, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, (USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C)
+ *
+ * Indicates that the USB clock recovery algorithm has detected that the
+ * frequency trim adjustment needed for the IRC48M output clock is outside the available
+ * TRIM_FINE adjustment range for the IRC48M module.
+ *
+ * Values:
+ * - 0b0 - No interrupt is reported
+ * - 0b1 - Unmasked interrupt has been generated
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field. */
+#define USB_RD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) ((USB_CLK_RECOVER_INT_STATUS_REG(base) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) >> USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)
+#define USB_BRD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))
+
+/*! @brief Set the OVF_ERROR field to a new value. */
+#define USB_WR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (USB_RMW_CLK_RECOVER_INT_STATUS(base, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(value)))
+#define USB_BWR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 USBDCD
+ *
+ * USB Device Charger Detection module
+ *
+ * Registers defined in this header file:
+ * - USBDCD_CONTROL - Control register
+ * - USBDCD_CLOCK - Clock register
+ * - USBDCD_STATUS - Status register
+ * - USBDCD_TIMER0 - TIMER0 register
+ * - USBDCD_TIMER1 - TIMER1 register
+ * - USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ * - USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ */
+
+#define USBDCD_INSTANCE_COUNT (1U) /*!< Number of instances of the USBDCD module. */
+#define USBDCD_IDX (0U) /*!< Instance number for USBDCD. */
+
+/*******************************************************************************
+ * USBDCD_CONTROL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_CONTROL - Control register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Contains the control and interrupt bit fields.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_CONTROL register
+ */
+/*@{*/
+#define USBDCD_RD_CONTROL(base)  (USBDCD_CONTROL_REG(base))
+#define USBDCD_WR_CONTROL(base, value) (USBDCD_CONTROL_REG(base) = (value))
+#define USBDCD_RMW_CONTROL(base, mask, value) (USBDCD_WR_CONTROL(base, (USBDCD_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USBDCD_SET_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) |  (value)))
+#define USBDCD_CLR_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) & ~(value)))
+#define USBDCD_TOG_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CONTROL, field IACK[0] (WORZ)
+ *
+ * Determines whether the interrupt is cleared.
+ *
+ * Values:
+ * - 0b0 - Do not clear the interrupt.
+ * - 0b1 - Clear the IF bit (interrupt flag).
+ */
+/*@{*/
+/*! @brief Set the IACK field to a new value. */
+#define USBDCD_WR_CONTROL_IACK(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_IACK_MASK, USBDCD_CONTROL_IACK(value)))
+#define USBDCD_BWR_CONTROL_IACK(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field IF[8] (RO)
+ *
+ * Determines whether an interrupt is pending.
+ *
+ * Values:
+ * - 0b0 - No interrupt is pending.
+ * - 0b1 - An interrupt is pending.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_IF field. */
+#define USBDCD_RD_CONTROL_IF(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_IF_MASK) >> USBDCD_CONTROL_IF_SHIFT)
+#define USBDCD_BRD_CONTROL_IF(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field IE[16] (RW)
+ *
+ * Enables/disables interrupts to the system.
+ *
+ * Values:
+ * - 0b0 - Disable interrupts to the system.
+ * - 0b1 - Enable interrupts to the system.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_IE field. */
+#define USBDCD_RD_CONTROL_IE(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_IE_MASK) >> USBDCD_CONTROL_IE_SHIFT)
+#define USBDCD_BRD_CONTROL_IE(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IE_SHIFT))
+
+/*! @brief Set the IE field to a new value. */
+#define USBDCD_WR_CONTROL_IE(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_IE_MASK, USBDCD_CONTROL_IE(value)))
+#define USBDCD_BWR_CONTROL_IE(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field BC12[17] (RW)
+ *
+ * BC1.2 compatibility. This bit cannot be changed after start detection.
+ *
+ * Values:
+ * - 0b0 - Compatible with BC1.1 (default)
+ * - 0b1 - Compatible with BC1.2
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_BC12 field. */
+#define USBDCD_RD_CONTROL_BC12(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_BC12_MASK) >> USBDCD_CONTROL_BC12_SHIFT)
+#define USBDCD_BRD_CONTROL_BC12(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_BC12_SHIFT))
+
+/*! @brief Set the BC12 field to a new value. */
+#define USBDCD_WR_CONTROL_BC12(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_BC12_MASK, USBDCD_CONTROL_BC12(value)))
+#define USBDCD_BWR_CONTROL_BC12(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_BC12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field START[24] (WORZ)
+ *
+ * Determines whether the charger detection sequence is initiated.
+ *
+ * Values:
+ * - 0b0 - Do not start the sequence. Writes of this value have no effect.
+ * - 0b1 - Initiate the charger detection sequence. If the sequence is already
+ *     running, writes of this value have no effect.
+ */
+/*@{*/
+/*! @brief Set the START field to a new value. */
+#define USBDCD_WR_CONTROL_START(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_START_MASK, USBDCD_CONTROL_START(value)))
+#define USBDCD_BWR_CONTROL_START(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_START_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field SR[25] (WORZ)
+ *
+ * Determines whether a software reset is performed.
+ *
+ * Values:
+ * - 0b0 - Do not perform a software reset.
+ * - 0b1 - Perform a software reset.
+ */
+/*@{*/
+/*! @brief Set the SR field to a new value. */
+#define USBDCD_WR_CONTROL_SR(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_SR_MASK, USBDCD_CONTROL_SR(value)))
+#define USBDCD_BWR_CONTROL_SR(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_SR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_CLOCK - Clock register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_CLOCK - Clock register (RW)
+ *
+ * Reset value: 0x000000C1U
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_CLOCK register
+ */
+/*@{*/
+#define USBDCD_RD_CLOCK(base)    (USBDCD_CLOCK_REG(base))
+#define USBDCD_WR_CLOCK(base, value) (USBDCD_CLOCK_REG(base) = (value))
+#define USBDCD_RMW_CLOCK(base, mask, value) (USBDCD_WR_CLOCK(base, (USBDCD_RD_CLOCK(base) & ~(mask)) | (value)))
+#define USBDCD_SET_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) |  (value)))
+#define USBDCD_CLR_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) & ~(value)))
+#define USBDCD_TOG_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_CLOCK bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW)
+ *
+ * Specifies the unit of measure for the clock speed.
+ *
+ * Values:
+ * - 0b0 - kHz Speed (between 1 kHz and 1023 kHz)
+ * - 0b1 - MHz Speed (between 1 MHz and 1023 MHz)
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field. */
+#define USBDCD_RD_CLOCK_CLOCK_UNIT(base) ((USBDCD_CLOCK_REG(base) & USBDCD_CLOCK_CLOCK_UNIT_MASK) >> USBDCD_CLOCK_CLOCK_UNIT_SHIFT)
+#define USBDCD_BRD_CLOCK_CLOCK_UNIT(base) (BITBAND_ACCESS32(&USBDCD_CLOCK_REG(base), USBDCD_CLOCK_CLOCK_UNIT_SHIFT))
+
+/*! @brief Set the CLOCK_UNIT field to a new value. */
+#define USBDCD_WR_CLOCK_CLOCK_UNIT(base, value) (USBDCD_RMW_CLOCK(base, USBDCD_CLOCK_CLOCK_UNIT_MASK, USBDCD_CLOCK_CLOCK_UNIT(value)))
+#define USBDCD_BWR_CLOCK_CLOCK_UNIT(base, value) (BITBAND_ACCESS32(&USBDCD_CLOCK_REG(base), USBDCD_CLOCK_CLOCK_UNIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW)
+ *
+ * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to
+ * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples
+ * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz:
+ * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100)
+ * For 500 kHz: 0b01_1111_0100 (500)
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field. */
+#define USBDCD_RD_CLOCK_CLOCK_SPEED(base) ((USBDCD_CLOCK_REG(base) & USBDCD_CLOCK_CLOCK_SPEED_MASK) >> USBDCD_CLOCK_CLOCK_SPEED_SHIFT)
+#define USBDCD_BRD_CLOCK_CLOCK_SPEED(base) (USBDCD_RD_CLOCK_CLOCK_SPEED(base))
+
+/*! @brief Set the CLOCK_SPEED field to a new value. */
+#define USBDCD_WR_CLOCK_CLOCK_SPEED(base, value) (USBDCD_RMW_CLOCK(base, USBDCD_CLOCK_CLOCK_SPEED_MASK, USBDCD_CLOCK_CLOCK_SPEED(value)))
+#define USBDCD_BWR_CLOCK_CLOCK_SPEED(base, value) (USBDCD_WR_CLOCK_CLOCK_SPEED(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_STATUS - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_STATUS - Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Provides the current state of the module for system software monitoring.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_STATUS register
+ */
+/*@{*/
+#define USBDCD_RD_STATUS(base)   (USBDCD_STATUS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_STATUS bitfields
+ */
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO)
+ *
+ * Reports how the charger detection is attached.
+ *
+ * Values:
+ * - 0b00 - No results to report.
+ * - 0b01 - Attached to a standard host. Must comply with USB 2.0 by drawing
+ *     only 2.5 mA (max) until connected.
+ * - 0b10 - Attached to a charging port. The exact meaning depends on bit 18: 0:
+ *     Attached to either a charging host or a dedicated charger. The charger
+ *     type detection has not completed. 1: Attached to a charging host. The
+ *     charger type detection has completed.
+ * - 0b11 - Attached to a dedicated charger.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_SEQ_RES field. */
+#define USBDCD_RD_STATUS_SEQ_RES(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_SEQ_RES_MASK) >> USBDCD_STATUS_SEQ_RES_SHIFT)
+#define USBDCD_BRD_STATUS_SEQ_RES(base) (USBDCD_RD_STATUS_SEQ_RES(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO)
+ *
+ * Indicates the status of the charger detection sequence.
+ *
+ * Values:
+ * - 0b00 - The module is either not enabled, or the module is enabled but the
+ *     data pins have not yet been detected.
+ * - 0b01 - Data pin contact detection is complete.
+ * - 0b10 - Charging port detection is complete.
+ * - 0b11 - Charger type detection is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field. */
+#define USBDCD_RD_STATUS_SEQ_STAT(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_SEQ_STAT_MASK) >> USBDCD_STATUS_SEQ_STAT_SHIFT)
+#define USBDCD_BRD_STATUS_SEQ_STAT(base) (USBDCD_RD_STATUS_SEQ_STAT(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field ERR[20] (RO)
+ *
+ * Indicates whether there is an error in the detection sequence.
+ *
+ * Values:
+ * - 0b0 - No sequence errors.
+ * - 0b1 - Error in the detection sequence. See the SEQ_STAT field to determine
+ *     the phase in which the error occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_ERR field. */
+#define USBDCD_RD_STATUS_ERR(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_ERR_MASK) >> USBDCD_STATUS_ERR_SHIFT)
+#define USBDCD_BRD_STATUS_ERR(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field TO[21] (RO)
+ *
+ * Indicates whether the detection sequence has passed the timeout threshhold.
+ *
+ * Values:
+ * - 0b0 - The detection sequence has not been running for over 1 s.
+ * - 0b1 - It has been over 1 s since the data pin contact was detected and
+ *     debounced.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_TO field. */
+#define USBDCD_RD_STATUS_TO(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_TO_MASK) >> USBDCD_STATUS_TO_SHIFT)
+#define USBDCD_BRD_STATUS_TO(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_TO_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field ACTIVE[22] (RO)
+ *
+ * Indicates whether the sequence is running.
+ *
+ * Values:
+ * - 0b0 - The sequence is not running.
+ * - 0b1 - The sequence is running.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_ACTIVE field. */
+#define USBDCD_RD_STATUS_ACTIVE(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_ACTIVE_MASK) >> USBDCD_STATUS_ACTIVE_SHIFT)
+#define USBDCD_BRD_STATUS_ACTIVE(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_ACTIVE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER0 - TIMER0 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER0 - TIMER0 register (RW)
+ *
+ * Reset value: 0x00100000U
+ *
+ * TIMER0 has an TSEQ_INIT field that represents the system latency in ms.
+ * Latency is measured from the time when VBUS goes active until the time system
+ * software initiates charger detection sequence in USBDCD module. When software sets
+ * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized
+ * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery
+ * Charging Specification requires the entire sequence, including TSEQ_INIT, to be
+ * completed in 1s or less.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER0 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER0(base)   (USBDCD_TIMER0_REG(base))
+#define USBDCD_WR_TIMER0(base, value) (USBDCD_TIMER0_REG(base) = (value))
+#define USBDCD_RMW_TIMER0(base, mask, value) (USBDCD_WR_TIMER0(base, (USBDCD_RD_TIMER0(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) |  (value)))
+#define USBDCD_CLR_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) & ~(value)))
+#define USBDCD_TOG_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER0 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO)
+ *
+ * Displays the amount of elapsed time since the event of setting the START bit
+ * plus the value of TSEQ_INIT. The timer is automatically initialized with the
+ * value of TSEQ_INIT before starting to count. This timer enables compliance with
+ * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging
+ * Specification. If the timer reaches the one second limit, the module triggers
+ * an interrupt and sets the error flag STATUS[ERR]. The timer continues
+ * counting throughout the charger detection sequence, even when control has been passed
+ * to software. As long as the module is active, the timer continues to count
+ * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not
+ * rollover to zero. A software reset clears the timer.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER0_TUNITCON field. */
+#define USBDCD_RD_TIMER0_TUNITCON(base) ((USBDCD_TIMER0_REG(base) & USBDCD_TIMER0_TUNITCON_MASK) >> USBDCD_TIMER0_TUNITCON_SHIFT)
+#define USBDCD_BRD_TIMER0_TUNITCON(base) (USBDCD_RD_TIMER0_TUNITCON(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW)
+ *
+ * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS
+ * goes active to the time system software initiates the charger detection
+ * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit
+ * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid
+ * values are 0-1023, but the USB Battery Charging Specification requires the
+ * entire sequence, including TSEQ_INIT, to be completed in 1s or less.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field. */
+#define USBDCD_RD_TIMER0_TSEQ_INIT(base) ((USBDCD_TIMER0_REG(base) & USBDCD_TIMER0_TSEQ_INIT_MASK) >> USBDCD_TIMER0_TSEQ_INIT_SHIFT)
+#define USBDCD_BRD_TIMER0_TSEQ_INIT(base) (USBDCD_RD_TIMER0_TSEQ_INIT(base))
+
+/*! @brief Set the TSEQ_INIT field to a new value. */
+#define USBDCD_WR_TIMER0_TSEQ_INIT(base, value) (USBDCD_RMW_TIMER0(base, USBDCD_TIMER0_TSEQ_INIT_MASK, USBDCD_TIMER0_TSEQ_INIT(value)))
+#define USBDCD_BWR_TIMER0_TSEQ_INIT(base, value) (USBDCD_WR_TIMER0_TSEQ_INIT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER1 - TIMER1 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER1 - TIMER1 register (RW)
+ *
+ * Reset value: 0x000A0028U
+ *
+ * TIMER1 contains timing parameters. Note that register values can be written
+ * that are not compliant with the USB Battery Charging Specification, so care
+ * should be taken when overwriting the default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER1 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER1(base)   (USBDCD_TIMER1_REG(base))
+#define USBDCD_WR_TIMER1(base, value) (USBDCD_TIMER1_REG(base) = (value))
+#define USBDCD_RMW_TIMER1(base, mask, value) (USBDCD_WR_TIMER1(base, (USBDCD_RD_TIMER1(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) |  (value)))
+#define USBDCD_CLR_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) & ~(value)))
+#define USBDCD_TOG_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER1 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW)
+ *
+ * This timing parameter is used after detection of the data pin. See "Charging
+ * Port Detection". Valid values are 1-1023, but the USB Battery Charging
+ * Specification requires a minimum value of 40 ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field. */
+#define USBDCD_RD_TIMER1_TVDPSRC_ON(base) ((USBDCD_TIMER1_REG(base) & USBDCD_TIMER1_TVDPSRC_ON_MASK) >> USBDCD_TIMER1_TVDPSRC_ON_SHIFT)
+#define USBDCD_BRD_TIMER1_TVDPSRC_ON(base) (USBDCD_RD_TIMER1_TVDPSRC_ON(base))
+
+/*! @brief Set the TVDPSRC_ON field to a new value. */
+#define USBDCD_WR_TIMER1_TVDPSRC_ON(base, value) (USBDCD_RMW_TIMER1(base, USBDCD_TIMER1_TVDPSRC_ON_MASK, USBDCD_TIMER1_TVDPSRC_ON(value)))
+#define USBDCD_BWR_TIMER1_TVDPSRC_ON(base, value) (USBDCD_WR_TIMER1_TVDPSRC_ON(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW)
+ *
+ * Sets the time period (ms) to debounce the D+ signal during the data pin
+ * contact detection phase. See "Debouncing the data pin contact" Valid values are
+ * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10
+ * ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field. */
+#define USBDCD_RD_TIMER1_TDCD_DBNC(base) ((USBDCD_TIMER1_REG(base) & USBDCD_TIMER1_TDCD_DBNC_MASK) >> USBDCD_TIMER1_TDCD_DBNC_SHIFT)
+#define USBDCD_BRD_TIMER1_TDCD_DBNC(base) (USBDCD_RD_TIMER1_TDCD_DBNC(base))
+
+/*! @brief Set the TDCD_DBNC field to a new value. */
+#define USBDCD_WR_TIMER1_TDCD_DBNC(base, value) (USBDCD_RMW_TIMER1(base, USBDCD_TIMER1_TDCD_DBNC_MASK, USBDCD_TIMER1_TDCD_DBNC(value)))
+#define USBDCD_BWR_TIMER1_TDCD_DBNC(base, value) (USBDCD_WR_TIMER1_TDCD_DBNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW)
+ *
+ * Reset value: 0x00280001U
+ *
+ * TIMER2_BC11 contains timing parameters for USB Battery Charging
+ * Specification, v1.1. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC11 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER2_BC11(base) (USBDCD_TIMER2_BC11_REG(base))
+#define USBDCD_WR_TIMER2_BC11(base, value) (USBDCD_TIMER2_BC11_REG(base) = (value))
+#define USBDCD_RMW_TIMER2_BC11(base, mask, value) (USBDCD_WR_TIMER2_BC11(base, (USBDCD_RD_TIMER2_BC11(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) |  (value)))
+#define USBDCD_CLR_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) & ~(value)))
+#define USBDCD_TOG_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after the device
+ * connects to the USB bus until checking the state of the D- line to determine the
+ * type of charging port. See "Charger Type Detection." Valid values are 1-15ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field. */
+#define USBDCD_RD_TIMER2_BC11_CHECK_DM(base) ((USBDCD_TIMER2_BC11_REG(base) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) >> USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)
+#define USBDCD_BRD_TIMER2_BC11_CHECK_DM(base) (USBDCD_RD_TIMER2_BC11_CHECK_DM(base))
+
+/*! @brief Set the CHECK_DM field to a new value. */
+#define USBDCD_WR_TIMER2_BC11_CHECK_DM(base, value) (USBDCD_RMW_TIMER2_BC11(base, USBDCD_TIMER2_BC11_CHECK_DM_MASK, USBDCD_TIMER2_BC11_CHECK_DM(value)))
+#define USBDCD_BWR_TIMER2_BC11_CHECK_DM(base, value) (USBDCD_WR_TIMER2_BC11_CHECK_DM(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW)
+ *
+ * Sets the time period (ms) that the module waits after charging port detection
+ * before system software must enable the D+ pullup to connect to the USB host.
+ * Valid values are 1-1023, but the USB Battery Charging Specification requires a
+ * minimum value of 40 ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field. */
+#define USBDCD_RD_TIMER2_BC11_TVDPSRC_CON(base) ((USBDCD_TIMER2_BC11_REG(base) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) >> USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)
+#define USBDCD_BRD_TIMER2_BC11_TVDPSRC_CON(base) (USBDCD_RD_TIMER2_BC11_TVDPSRC_CON(base))
+
+/*! @brief Set the TVDPSRC_CON field to a new value. */
+#define USBDCD_WR_TIMER2_BC11_TVDPSRC_CON(base, value) (USBDCD_RMW_TIMER2_BC11(base, USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK, USBDCD_TIMER2_BC11_TVDPSRC_CON(value)))
+#define USBDCD_BWR_TIMER2_BC11_TVDPSRC_CON(base, value) (USBDCD_WR_TIMER2_BC11_TVDPSRC_CON(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW)
+ *
+ * Reset value: 0x00010028U
+ *
+ * TIMER2_BC12 contains timing parameters for USB Battery Charging
+ * Specification, v1.2. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC12 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER2_BC12(base) (USBDCD_TIMER2_BC12_REG(base))
+#define USBDCD_WR_TIMER2_BC12(base, value) (USBDCD_TIMER2_BC12_REG(base) = (value))
+#define USBDCD_RMW_TIMER2_BC12(base, mask, value) (USBDCD_WR_TIMER2_BC12(base, (USBDCD_RD_TIMER2_BC12(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) |  (value)))
+#define USBDCD_CLR_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) & ~(value)))
+#define USBDCD_TOG_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid
+ * values are 0-40ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field. */
+#define USBDCD_RD_TIMER2_BC12_TVDMSRC_ON(base) ((USBDCD_TIMER2_BC12_REG(base) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) >> USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)
+#define USBDCD_BRD_TIMER2_BC12_TVDMSRC_ON(base) (USBDCD_RD_TIMER2_BC12_TVDMSRC_ON(base))
+
+/*! @brief Set the TVDMSRC_ON field to a new value. */
+#define USBDCD_WR_TIMER2_BC12_TVDMSRC_ON(base, value) (USBDCD_RMW_TIMER2_BC12(base, USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK, USBDCD_TIMER2_BC12_TVDMSRC_ON(value)))
+#define USBDCD_BWR_TIMER2_BC12_TVDMSRC_ON(base, value) (USBDCD_WR_TIMER2_BC12_TVDMSRC_ON(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after primary detection
+ * before start to secondary detection. Valid values are 1-1023ms. Default is
+ * 1ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field. */
+#define USBDCD_RD_TIMER2_BC12_TWAIT_AFTER_PRD(base) ((USBDCD_TIMER2_BC12_REG(base) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) >> USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)
+#define USBDCD_BRD_TIMER2_BC12_TWAIT_AFTER_PRD(base) (USBDCD_RD_TIMER2_BC12_TWAIT_AFTER_PRD(base))
+
+/*! @brief Set the TWAIT_AFTER_PRD field to a new value. */
+#define USBDCD_WR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value) (USBDCD_RMW_TIMER2_BC12(base, USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK, USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(value)))
+#define USBDCD_BWR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value) (USBDCD_WR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value))
+/*@}*/
+
+/*
+ * MK64F12 VREF
+ *
+ * Voltage Reference
+ *
+ * Registers defined in this header file:
+ * - VREF_TRM - VREF Trim Register
+ * - VREF_SC - VREF Status and Control Register
+ */
+
+#define VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
+#define VREF_IDX (0U) /*!< Instance number for VREF. */
+
+/*******************************************************************************
+ * VREF_TRM - VREF Trim Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_TRM - VREF Trim Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains bits that contain the trim data for the Voltage
+ * Reference.
+ */
+/*!
+ * @name Constants and macros for entire VREF_TRM register
+ */
+/*@{*/
+#define VREF_RD_TRM(base)        (VREF_TRM_REG(base))
+#define VREF_WR_TRM(base, value) (VREF_TRM_REG(base) = (value))
+#define VREF_RMW_TRM(base, mask, value) (VREF_WR_TRM(base, (VREF_RD_TRM(base) & ~(mask)) | (value)))
+#define VREF_SET_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) |  (value)))
+#define VREF_CLR_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) & ~(value)))
+#define VREF_TOG_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_TRM bitfields
+ */
+
+/*!
+ * @name Register VREF_TRM, field TRIM[5:0] (RW)
+ *
+ * These bits change the resulting VREF by approximately +/- 0.5 mV for each
+ * step. Min = minimum and max = maximum voltage reference output. For minimum and
+ * maximum voltage reference output values, refer to the Data Sheet for this chip.
+ *
+ * Values:
+ * - 0b000000 - Min
+ * - 0b111111 - Max
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_TRIM field. */
+#define VREF_RD_TRM_TRIM(base) ((VREF_TRM_REG(base) & VREF_TRM_TRIM_MASK) >> VREF_TRM_TRIM_SHIFT)
+#define VREF_BRD_TRM_TRIM(base) (VREF_RD_TRM_TRIM(base))
+
+/*! @brief Set the TRIM field to a new value. */
+#define VREF_WR_TRM_TRIM(base, value) (VREF_RMW_TRM(base, VREF_TRM_TRIM_MASK, VREF_TRM_TRIM(value)))
+#define VREF_BWR_TRM_TRIM(base, value) (VREF_WR_TRM_TRIM(base, value))
+/*@}*/
+
+/*!
+ * @name Register VREF_TRM, field CHOPEN[6] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0b0 - Chop oscillator is disabled.
+ * - 0b1 - Chop oscillator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_CHOPEN field. */
+#define VREF_RD_TRM_CHOPEN(base) ((VREF_TRM_REG(base) & VREF_TRM_CHOPEN_MASK) >> VREF_TRM_CHOPEN_SHIFT)
+#define VREF_BRD_TRM_CHOPEN(base) (BITBAND_ACCESS8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT))
+
+/*! @brief Set the CHOPEN field to a new value. */
+#define VREF_WR_TRM_CHOPEN(base, value) (VREF_RMW_TRM(base, VREF_TRM_CHOPEN_MASK, VREF_TRM_CHOPEN(value)))
+#define VREF_BWR_TRM_CHOPEN(base, value) (BITBAND_ACCESS8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * VREF_SC - VREF Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_SC - VREF Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the control bits used to enable the internal voltage
+ * reference and to select the buffer mode to be used.
+ */
+/*!
+ * @name Constants and macros for entire VREF_SC register
+ */
+/*@{*/
+#define VREF_RD_SC(base)         (VREF_SC_REG(base))
+#define VREF_WR_SC(base, value)  (VREF_SC_REG(base) = (value))
+#define VREF_RMW_SC(base, mask, value) (VREF_WR_SC(base, (VREF_RD_SC(base) & ~(mask)) | (value)))
+#define VREF_SET_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) |  (value)))
+#define VREF_CLR_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) & ~(value)))
+#define VREF_TOG_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_SC bitfields
+ */
+
+/*!
+ * @name Register VREF_SC, field MODE_LV[1:0] (RW)
+ *
+ * These bits select the buffer modes for the Voltage Reference module.
+ *
+ * Values:
+ * - 0b00 - Bandgap on only, for stabilization and startup
+ * - 0b01 - High power buffer mode enabled
+ * - 0b10 - Low-power buffer mode enabled
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_MODE_LV field. */
+#define VREF_RD_SC_MODE_LV(base) ((VREF_SC_REG(base) & VREF_SC_MODE_LV_MASK) >> VREF_SC_MODE_LV_SHIFT)
+#define VREF_BRD_SC_MODE_LV(base) (VREF_RD_SC_MODE_LV(base))
+
+/*! @brief Set the MODE_LV field to a new value. */
+#define VREF_WR_SC_MODE_LV(base, value) (VREF_RMW_SC(base, VREF_SC_MODE_LV_MASK, VREF_SC_MODE_LV(value)))
+#define VREF_BWR_SC_MODE_LV(base, value) (VREF_WR_SC_MODE_LV(base, value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFST[2] (RO)
+ *
+ * This bit indicates that the bandgap reference within the Voltage Reference
+ * module has completed its startup and stabilization.
+ *
+ * Values:
+ * - 0b0 - The module is disabled or not stable.
+ * - 0b1 - The module is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFST field. */
+#define VREF_RD_SC_VREFST(base) ((VREF_SC_REG(base) & VREF_SC_VREFST_MASK) >> VREF_SC_VREFST_SHIFT)
+#define VREF_BRD_SC_VREFST(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field ICOMPEN[5] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_ICOMPEN field. */
+#define VREF_RD_SC_ICOMPEN(base) ((VREF_SC_REG(base) & VREF_SC_ICOMPEN_MASK) >> VREF_SC_ICOMPEN_SHIFT)
+#define VREF_BRD_SC_ICOMPEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT))
+
+/*! @brief Set the ICOMPEN field to a new value. */
+#define VREF_WR_SC_ICOMPEN(base, value) (VREF_RMW_SC(base, VREF_SC_ICOMPEN_MASK, VREF_SC_ICOMPEN(value)))
+#define VREF_BWR_SC_ICOMPEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field REGEN[6] (RW)
+ *
+ * This bit is used to enable the internal 1.75 V regulator to produce a
+ * constant internal voltage supply in order to reduce the sensitivity to external
+ * supply noise and variation. If it is desired to keep the regulator enabled in very
+ * low power modes, refer to the Chip Configuration details for a description on
+ * how this can be achieved. This bit is set during factory trimming of the VREF
+ * voltage. This bit should be written to 1 to achieve the performance stated in
+ * the data sheet.
+ *
+ * Values:
+ * - 0b0 - Internal 1.75 V regulator is disabled.
+ * - 0b1 - Internal 1.75 V regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_REGEN field. */
+#define VREF_RD_SC_REGEN(base) ((VREF_SC_REG(base) & VREF_SC_REGEN_MASK) >> VREF_SC_REGEN_SHIFT)
+#define VREF_BRD_SC_REGEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT))
+
+/*! @brief Set the REGEN field to a new value. */
+#define VREF_WR_SC_REGEN(base, value) (VREF_RMW_SC(base, VREF_SC_REGEN_MASK, VREF_SC_REGEN(value)))
+#define VREF_BWR_SC_REGEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFEN[7] (RW)
+ *
+ * This bit is used to enable the bandgap reference within the Voltage Reference
+ * module. After the VREF is enabled, turning off the clock to the VREF module
+ * via the corresponding clock gate register will not disable the VREF. VREF must
+ * be disabled via this VREFEN bit.
+ *
+ * Values:
+ * - 0b0 - The module is disabled.
+ * - 0b1 - The module is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFEN field. */
+#define VREF_RD_SC_VREFEN(base) ((VREF_SC_REG(base) & VREF_SC_VREFEN_MASK) >> VREF_SC_VREFEN_SHIFT)
+#define VREF_BRD_SC_VREFEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT))
+
+/*! @brief Set the VREFEN field to a new value. */
+#define VREF_WR_SC_VREFEN(base, value) (VREF_RMW_SC(base, VREF_SC_VREFEN_MASK, VREF_SC_VREFEN(value)))
+#define VREF_BWR_SC_VREFEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 WDOG
+ *
+ * Generation 2008 Watchdog Timer
+ *
+ * Registers defined in this header file:
+ * - WDOG_STCTRLH - Watchdog Status and Control Register High
+ * - WDOG_STCTRLL - Watchdog Status and Control Register Low
+ * - WDOG_TOVALH - Watchdog Time-out Value Register High
+ * - WDOG_TOVALL - Watchdog Time-out Value Register Low
+ * - WDOG_WINH - Watchdog Window Register High
+ * - WDOG_WINL - Watchdog Window Register Low
+ * - WDOG_REFRESH - Watchdog Refresh register
+ * - WDOG_UNLOCK - Watchdog Unlock register
+ * - WDOG_TMROUTH - Watchdog Timer Output Register High
+ * - WDOG_TMROUTL - Watchdog Timer Output Register Low
+ * - WDOG_RSTCNT - Watchdog Reset Count register
+ * - WDOG_PRESC - Watchdog Prescaler register
+ */
+
+#define WDOG_INSTANCE_COUNT (1U) /*!< Number of instances of the WDOG module. */
+#define WDOG_IDX (0U) /*!< Instance number for WDOG. */
+
+/*******************************************************************************
+ * WDOG_STCTRLH - Watchdog Status and Control Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
+ *
+ * Reset value: 0x01D3U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLH register
+ */
+/*@{*/
+#define WDOG_RD_STCTRLH(base)    (WDOG_STCTRLH_REG(base))
+#define WDOG_WR_STCTRLH(base, value) (WDOG_STCTRLH_REG(base) = (value))
+#define WDOG_RMW_STCTRLH(base, mask, value) (WDOG_WR_STCTRLH(base, (WDOG_RD_STCTRLH(base) & ~(mask)) | (value)))
+#define WDOG_SET_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) |  (value)))
+#define WDOG_CLR_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) & ~(value)))
+#define WDOG_TOG_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_STCTRLH bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
+ *
+ * Enables or disables the WDOG's operation. In the disabled state, the watchdog
+ * timer is kept in the reset state, but the other exception conditions can
+ * still trigger a reset/interrupt. A change in the value of this bit must be held
+ * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled.
+ * - 0b1 - WDOG is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. */
+#define WDOG_RD_STCTRLH_WDOGEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WDOGEN_MASK) >> WDOG_STCTRLH_WDOGEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WDOGEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WDOGEN_SHIFT))
+
+/*! @brief Set the WDOGEN field to a new value. */
+#define WDOG_WR_STCTRLH_WDOGEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WDOGEN_MASK, WDOG_STCTRLH_WDOGEN(value)))
+#define WDOG_BWR_STCTRLH_WDOGEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WDOGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
+ *
+ * Selects clock source for the WDOG timer and other internal timing operations.
+ *
+ * Values:
+ * - 0b0 - WDOG clock sourced from LPO .
+ * - 0b1 - WDOG clock sourced from alternate clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. */
+#define WDOG_RD_STCTRLH_CLKSRC(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_CLKSRC_MASK) >> WDOG_STCTRLH_CLKSRC_SHIFT)
+#define WDOG_BRD_STCTRLH_CLKSRC(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_CLKSRC_SHIFT))
+
+/*! @brief Set the CLKSRC field to a new value. */
+#define WDOG_WR_STCTRLH_CLKSRC(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_CLKSRC_MASK, WDOG_STCTRLH_CLKSRC(value)))
+#define WDOG_BWR_STCTRLH_CLKSRC(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_CLKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
+ *
+ * Used to enable the debug breadcrumbs feature. A change in this bit is updated
+ * immediately, as opposed to updating after WCT.
+ *
+ * Values:
+ * - 0b0 - WDOG time-out generates reset only.
+ * - 0b1 - WDOG time-out initially generates an interrupt. After WCT, it
+ *     generates a reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. */
+#define WDOG_RD_STCTRLH_IRQRSTEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_IRQRSTEN_MASK) >> WDOG_STCTRLH_IRQRSTEN_SHIFT)
+#define WDOG_BRD_STCTRLH_IRQRSTEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_IRQRSTEN_SHIFT))
+
+/*! @brief Set the IRQRSTEN field to a new value. */
+#define WDOG_WR_STCTRLH_IRQRSTEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_IRQRSTEN_MASK, WDOG_STCTRLH_IRQRSTEN(value)))
+#define WDOG_BWR_STCTRLH_IRQRSTEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_IRQRSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
+ *
+ * Enables Windowing mode.
+ *
+ * Values:
+ * - 0b0 - Windowing mode is disabled.
+ * - 0b1 - Windowing mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WINEN field. */
+#define WDOG_RD_STCTRLH_WINEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WINEN_MASK) >> WDOG_STCTRLH_WINEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WINEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WINEN_SHIFT))
+
+/*! @brief Set the WINEN field to a new value. */
+#define WDOG_WR_STCTRLH_WINEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WINEN_MASK, WDOG_STCTRLH_WINEN(value)))
+#define WDOG_BWR_STCTRLH_WINEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WINEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
+ *
+ * Enables updates to watchdog write-once registers, after the reset-triggered
+ * initial configuration window (WCT) closes, through unlock sequence.
+ *
+ * Values:
+ * - 0b0 - No further updates allowed to WDOG write-once registers.
+ * - 0b1 - WDOG write-once registers can be unlocked for updating.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. */
+#define WDOG_RD_STCTRLH_ALLOWUPDATE(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_ALLOWUPDATE_MASK) >> WDOG_STCTRLH_ALLOWUPDATE_SHIFT)
+#define WDOG_BRD_STCTRLH_ALLOWUPDATE(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_ALLOWUPDATE_SHIFT))
+
+/*! @brief Set the ALLOWUPDATE field to a new value. */
+#define WDOG_WR_STCTRLH_ALLOWUPDATE(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_ALLOWUPDATE_MASK, WDOG_STCTRLH_ALLOWUPDATE(value)))
+#define WDOG_BWR_STCTRLH_ALLOWUPDATE(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_ALLOWUPDATE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
+ *
+ * Enables or disables WDOG in Debug mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Debug mode.
+ * - 0b1 - WDOG is enabled in CPU Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_DBGEN field. */
+#define WDOG_RD_STCTRLH_DBGEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_DBGEN_MASK) >> WDOG_STCTRLH_DBGEN_SHIFT)
+#define WDOG_BRD_STCTRLH_DBGEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DBGEN_SHIFT))
+
+/*! @brief Set the DBGEN field to a new value. */
+#define WDOG_WR_STCTRLH_DBGEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_DBGEN_MASK, WDOG_STCTRLH_DBGEN(value)))
+#define WDOG_BWR_STCTRLH_DBGEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DBGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
+ *
+ * Enables or disables WDOG in Stop mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Stop mode.
+ * - 0b1 - WDOG is enabled in CPU Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_STOPEN field. */
+#define WDOG_RD_STCTRLH_STOPEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_STOPEN_MASK) >> WDOG_STCTRLH_STOPEN_SHIFT)
+#define WDOG_BRD_STCTRLH_STOPEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_STOPEN_SHIFT))
+
+/*! @brief Set the STOPEN field to a new value. */
+#define WDOG_WR_STCTRLH_STOPEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_STOPEN_MASK, WDOG_STCTRLH_STOPEN(value)))
+#define WDOG_BWR_STCTRLH_STOPEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_STOPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
+ *
+ * Enables or disables WDOG in Wait mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Wait mode.
+ * - 0b1 - WDOG is enabled in CPU Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WAITEN field. */
+#define WDOG_RD_STCTRLH_WAITEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WAITEN_MASK) >> WDOG_STCTRLH_WAITEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WAITEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WAITEN_SHIFT))
+
+/*! @brief Set the WAITEN field to a new value. */
+#define WDOG_WR_STCTRLH_WAITEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WAITEN_MASK, WDOG_STCTRLH_WAITEN(value)))
+#define WDOG_BWR_STCTRLH_WAITEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WAITEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
+ *
+ * Puts the watchdog in the functional test mode. In this mode, the watchdog
+ * timer and the associated compare and reset generation logic is tested for correct
+ * operation. The clock for the timer is switched from the main watchdog clock
+ * to the fast clock input for watchdog functional test. The TESTSEL bit selects
+ * the test to be run.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. */
+#define WDOG_RD_STCTRLH_TESTWDOG(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_TESTWDOG_MASK) >> WDOG_STCTRLH_TESTWDOG_SHIFT)
+#define WDOG_BRD_STCTRLH_TESTWDOG(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTWDOG_SHIFT))
+
+/*! @brief Set the TESTWDOG field to a new value. */
+#define WDOG_WR_STCTRLH_TESTWDOG(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_TESTWDOG_MASK, WDOG_STCTRLH_TESTWDOG(value)))
+#define WDOG_BWR_STCTRLH_TESTWDOG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTWDOG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
+ *
+ * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
+ * timer.
+ *
+ * Values:
+ * - 0b0 - Quick test. The timer runs in normal operation. You can load a small
+ *     time-out value to do a quick test.
+ * - 0b1 - Byte test. Puts the timer in the byte test mode where individual
+ *     bytes of the timer are enabled for operation and are compared for time-out
+ *     against the corresponding byte of the programmed time-out value. Select the
+ *     byte through BYTESEL[1:0] for testing.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. */
+#define WDOG_RD_STCTRLH_TESTSEL(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_TESTSEL_MASK) >> WDOG_STCTRLH_TESTSEL_SHIFT)
+#define WDOG_BRD_STCTRLH_TESTSEL(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTSEL_SHIFT))
+
+/*! @brief Set the TESTSEL field to a new value. */
+#define WDOG_WR_STCTRLH_TESTSEL(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_TESTSEL_MASK, WDOG_STCTRLH_TESTSEL(value)))
+#define WDOG_BWR_STCTRLH_TESTSEL(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
+ *
+ * This 2-bit field selects the byte to be tested when the watchdog is in the
+ * byte test mode.
+ *
+ * Values:
+ * - 0b00 - Byte 0 selected
+ * - 0b01 - Byte 1 selected
+ * - 0b10 - Byte 2 selected
+ * - 0b11 - Byte 3 selected
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. */
+#define WDOG_RD_STCTRLH_BYTESEL(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_BYTESEL_MASK) >> WDOG_STCTRLH_BYTESEL_SHIFT)
+#define WDOG_BRD_STCTRLH_BYTESEL(base) (WDOG_RD_STCTRLH_BYTESEL(base))
+
+/*! @brief Set the BYTESEL field to a new value. */
+#define WDOG_WR_STCTRLH_BYTESEL(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_BYTESEL_MASK, WDOG_STCTRLH_BYTESEL(value)))
+#define WDOG_BWR_STCTRLH_BYTESEL(base, value) (WDOG_WR_STCTRLH_BYTESEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
+ *
+ * Allows the WDOG's functional test mode to be disabled permanently. After it
+ * is set, it can only be cleared by a reset. It cannot be unlocked for editing
+ * after it is set.
+ *
+ * Values:
+ * - 0b0 - WDOG functional test mode is not disabled.
+ * - 0b1 - WDOG functional test mode is disabled permanently until reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. */
+#define WDOG_RD_STCTRLH_DISTESTWDOG(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_DISTESTWDOG_MASK) >> WDOG_STCTRLH_DISTESTWDOG_SHIFT)
+#define WDOG_BRD_STCTRLH_DISTESTWDOG(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DISTESTWDOG_SHIFT))
+
+/*! @brief Set the DISTESTWDOG field to a new value. */
+#define WDOG_WR_STCTRLH_DISTESTWDOG(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_DISTESTWDOG_MASK, WDOG_STCTRLH_DISTESTWDOG(value)))
+#define WDOG_BWR_STCTRLH_DISTESTWDOG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DISTESTWDOG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_STCTRLL - Watchdog Status and Control Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
+ *
+ * Reset value: 0x0001U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLL register
+ */
+/*@{*/
+#define WDOG_RD_STCTRLL(base)    (WDOG_STCTRLL_REG(base))
+#define WDOG_WR_STCTRLL(base, value) (WDOG_STCTRLL_REG(base) = (value))
+#define WDOG_RMW_STCTRLL(base, mask, value) (WDOG_WR_STCTRLL(base, (WDOG_RD_STCTRLL(base) & ~(mask)) | (value)))
+#define WDOG_SET_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) |  (value)))
+#define WDOG_CLR_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) & ~(value)))
+#define WDOG_TOG_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_STCTRLL bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
+ *
+ * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
+ * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
+ * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
+ * bit. It also gets cleared on a system reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLL_INTFLG field. */
+#define WDOG_RD_STCTRLL_INTFLG(base) ((WDOG_STCTRLL_REG(base) & WDOG_STCTRLL_INTFLG_MASK) >> WDOG_STCTRLL_INTFLG_SHIFT)
+#define WDOG_BRD_STCTRLL_INTFLG(base) (BITBAND_ACCESS16(&WDOG_STCTRLL_REG(base), WDOG_STCTRLL_INTFLG_SHIFT))
+
+/*! @brief Set the INTFLG field to a new value. */
+#define WDOG_WR_STCTRLL_INTFLG(base, value) (WDOG_RMW_STCTRLL(base, WDOG_STCTRLL_INTFLG_MASK, WDOG_STCTRLL_INTFLG(value)))
+#define WDOG_BWR_STCTRLL_INTFLG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLL_REG(base), WDOG_STCTRLL_INTFLG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TOVALH - Watchdog Time-out Value Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
+ *
+ * Reset value: 0x004CU
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TOVALH register
+ */
+/*@{*/
+#define WDOG_RD_TOVALH(base)     (WDOG_TOVALH_REG(base))
+#define WDOG_WR_TOVALH(base, value) (WDOG_TOVALH_REG(base) = (value))
+#define WDOG_RMW_TOVALH(base, mask, value) (WDOG_WR_TOVALH(base, (WDOG_RD_TOVALH(base) & ~(mask)) | (value)))
+#define WDOG_SET_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) |  (value)))
+#define WDOG_CLR_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) & ~(value)))
+#define WDOG_TOG_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TOVALL - Watchdog Time-out Value Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
+ *
+ * Reset value: 0x4B4CU
+ *
+ * The time-out value of the watchdog must be set to a minimum of four watchdog
+ * clock cycles. This is to take into account the delay in new settings taking
+ * effect in the watchdog clock domain.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TOVALL register
+ */
+/*@{*/
+#define WDOG_RD_TOVALL(base)     (WDOG_TOVALL_REG(base))
+#define WDOG_WR_TOVALL(base, value) (WDOG_TOVALL_REG(base) = (value))
+#define WDOG_RMW_TOVALL(base, mask, value) (WDOG_WR_TOVALL(base, (WDOG_RD_TOVALL(base) & ~(mask)) | (value)))
+#define WDOG_SET_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) |  (value)))
+#define WDOG_CLR_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) & ~(value)))
+#define WDOG_TOG_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_WINH - Watchdog Window Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_WINH - Watchdog Window Register High (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_WINH register
+ */
+/*@{*/
+#define WDOG_RD_WINH(base)       (WDOG_WINH_REG(base))
+#define WDOG_WR_WINH(base, value) (WDOG_WINH_REG(base) = (value))
+#define WDOG_RMW_WINH(base, mask, value) (WDOG_WR_WINH(base, (WDOG_RD_WINH(base) & ~(mask)) | (value)))
+#define WDOG_SET_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) |  (value)))
+#define WDOG_CLR_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) & ~(value)))
+#define WDOG_TOG_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_WINL - Watchdog Window Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_WINL - Watchdog Window Register Low (RW)
+ *
+ * Reset value: 0x0010U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_WINL register
+ */
+/*@{*/
+#define WDOG_RD_WINL(base)       (WDOG_WINL_REG(base))
+#define WDOG_WR_WINL(base, value) (WDOG_WINL_REG(base) = (value))
+#define WDOG_RMW_WINL(base, mask, value) (WDOG_WR_WINL(base, (WDOG_RD_WINL(base) & ~(mask)) | (value)))
+#define WDOG_SET_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) |  (value)))
+#define WDOG_CLR_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) & ~(value)))
+#define WDOG_TOG_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_REFRESH - Watchdog Refresh register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_REFRESH - Watchdog Refresh register (RW)
+ *
+ * Reset value: 0xB480U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_REFRESH register
+ */
+/*@{*/
+#define WDOG_RD_REFRESH(base)    (WDOG_REFRESH_REG(base))
+#define WDOG_WR_REFRESH(base, value) (WDOG_REFRESH_REG(base) = (value))
+#define WDOG_RMW_REFRESH(base, mask, value) (WDOG_WR_REFRESH(base, (WDOG_RD_REFRESH(base) & ~(mask)) | (value)))
+#define WDOG_SET_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) |  (value)))
+#define WDOG_CLR_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) & ~(value)))
+#define WDOG_TOG_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_UNLOCK - Watchdog Unlock register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_UNLOCK - Watchdog Unlock register (RW)
+ *
+ * Reset value: 0xD928U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_UNLOCK register
+ */
+/*@{*/
+#define WDOG_RD_UNLOCK(base)     (WDOG_UNLOCK_REG(base))
+#define WDOG_WR_UNLOCK(base, value) (WDOG_UNLOCK_REG(base) = (value))
+#define WDOG_RMW_UNLOCK(base, mask, value) (WDOG_WR_UNLOCK(base, (WDOG_RD_UNLOCK(base) & ~(mask)) | (value)))
+#define WDOG_SET_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) |  (value)))
+#define WDOG_CLR_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) & ~(value)))
+#define WDOG_TOG_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TMROUTH - Watchdog Timer Output Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTH register
+ */
+/*@{*/
+#define WDOG_RD_TMROUTH(base)    (WDOG_TMROUTH_REG(base))
+#define WDOG_WR_TMROUTH(base, value) (WDOG_TMROUTH_REG(base) = (value))
+#define WDOG_RMW_TMROUTH(base, mask, value) (WDOG_WR_TMROUTH(base, (WDOG_RD_TMROUTH(base) & ~(mask)) | (value)))
+#define WDOG_SET_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) |  (value)))
+#define WDOG_CLR_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) & ~(value)))
+#define WDOG_TOG_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TMROUTL - Watchdog Timer Output Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
+ * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
+ * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
+ * the watchdog timer.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTL register
+ */
+/*@{*/
+#define WDOG_RD_TMROUTL(base)    (WDOG_TMROUTL_REG(base))
+#define WDOG_WR_TMROUTL(base, value) (WDOG_TMROUTL_REG(base) = (value))
+#define WDOG_RMW_TMROUTL(base, mask, value) (WDOG_WR_TMROUTL(base, (WDOG_RD_TMROUTL(base) & ~(mask)) | (value)))
+#define WDOG_SET_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) |  (value)))
+#define WDOG_CLR_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) & ~(value)))
+#define WDOG_TOG_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_RSTCNT - Watchdog Reset Count register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_RSTCNT - Watchdog Reset Count register (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_RSTCNT register
+ */
+/*@{*/
+#define WDOG_RD_RSTCNT(base)     (WDOG_RSTCNT_REG(base))
+#define WDOG_WR_RSTCNT(base, value) (WDOG_RSTCNT_REG(base) = (value))
+#define WDOG_RMW_RSTCNT(base, mask, value) (WDOG_WR_RSTCNT(base, (WDOG_RD_RSTCNT(base) & ~(mask)) | (value)))
+#define WDOG_SET_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) |  (value)))
+#define WDOG_CLR_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) & ~(value)))
+#define WDOG_TOG_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_PRESC - Watchdog Prescaler register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_PRESC - Watchdog Prescaler register (RW)
+ *
+ * Reset value: 0x0400U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_PRESC register
+ */
+/*@{*/
+#define WDOG_RD_PRESC(base)      (WDOG_PRESC_REG(base))
+#define WDOG_WR_PRESC(base, value) (WDOG_PRESC_REG(base) = (value))
+#define WDOG_RMW_PRESC(base, mask, value) (WDOG_WR_PRESC(base, (WDOG_RD_PRESC(base) & ~(mask)) | (value)))
+#define WDOG_SET_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) |  (value)))
+#define WDOG_CLR_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) & ~(value)))
+#define WDOG_TOG_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_PRESC bitfields
+ */
+
+/*!
+ * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
+ *
+ * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
+ * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
+ * 1) to provide the prescaled WDOG_CLK.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_PRESC_PRESCVAL field. */
+#define WDOG_RD_PRESC_PRESCVAL(base) ((WDOG_PRESC_REG(base) & WDOG_PRESC_PRESCVAL_MASK) >> WDOG_PRESC_PRESCVAL_SHIFT)
+#define WDOG_BRD_PRESC_PRESCVAL(base) (WDOG_RD_PRESC_PRESCVAL(base))
+
+/*! @brief Set the PRESCVAL field to a new value. */
+#define WDOG_WR_PRESC_PRESCVAL(base, value) (WDOG_RMW_PRESC(base, WDOG_PRESC_PRESCVAL_MASK, WDOG_PRESC_PRESCVAL(value)))
+#define WDOG_BWR_PRESC_PRESCVAL(base, value) (WDOG_WR_PRESC_PRESCVAL(base, value))
+/*@}*/
+
+/* Instance numbers for core modules */
+#define JTAG_IDX (0) /*!< Instance number for JTAG. */
+#define TPIU_IDX (0) /*!< Instance number for TPIU. */
+#define SCB_IDX (0) /*!< Instance number for SCB. */
+#define CoreDebug_IDX (0) /*!< Instance number for CoreDebug. */
+
+#if defined(__IAR_SYSTEMS_ICC__)
+  /* Restore checking of "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)" */
+  #pragma diag_default=pm008
+#endif
+
+#endif /* __MK64F12_EXTENSION_H__ */
+/* EOF */
diff --git a/Workspace/4part1/SDK/platform/devices/MK64F12/include/MK64F12_features.h b/Workspace/4part1/SDK/platform/devices/MK64F12/include/MK64F12_features.h
new file mode 100644
index 0000000..9c826df
--- /dev/null
+++ b/Workspace/4part1/SDK/platform/devices/MK64F12/include/MK64F12_features.h
@@ -0,0 +1,1901 @@
+/*
+** ###################################################################
+**     Version:             rev. 2.14, 2015-06-08
+**     Build:               b150715
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-01-30)
+**         Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.6 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.7 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.8 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.9 (2015-01-21)
+**         Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
+**     - rev. 2.10 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**     - rev. 2.11 (2015-05-19)
+**         FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
+**         Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
+**         Added features for PDB and PORT.
+**     - rev. 2.12 (2015-05-25)
+**         Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
+**     - rev. 2.13 (2015-05-27)
+**         Several USB features added.
+**     - rev. 2.14 (2015-06-08)
+**         FTM features BUS_CLOCK and FAST_CLOCK removed.
+**
+** ###################################################################
+*/
+
+#if !defined(__FSL_MK64F12_FEATURES_H__)
+#define __FSL_MK64F12_FEATURES_H__
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* FLEXCAN module features */
+
+/* @brief Message buffer size */
+#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
+/* @brief Has doze mode support (register bit field MCR[DOZE]). */
+#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
+/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
+#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
+/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
+/* @brief Has extended bit timing register (register CBT). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
+/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
+#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
+/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
+#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
+/* @brief Number of interrupt vectors. */
+#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* SOC module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief ACMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_ACMP_COUNT (0)
+    /* @brief ADC16 availability on the SoC. */
+    #define FSL_FEATURE_SOC_ADC16_COUNT (2)
+    /* @brief AFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_AFE_COUNT (0)
+    /* @brief AIPS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AIPS_COUNT (2)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (0)
+    /* @brief AXBS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AXBS_COUNT (1)
+    /* @brief CADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CADC_COUNT (0)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief MMCAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
+    /* @brief CMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMP_COUNT (3)
+    /* @brief CMT availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMT_COUNT (1)
+    /* @brief CNC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CNC_COUNT (0)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief DAC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DAC_COUNT (2)
+    /* @brief DCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DCDC_COUNT (0)
+    /* @brief DDR availability on the SoC. */
+    #define FSL_FEATURE_SOC_DDR_COUNT (0)
+    /* @brief DMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMA_COUNT (0)
+    /* @brief DMAMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+    /* @brief DRY availability on the SoC. */
+    #define FSL_FEATURE_SOC_DRY_COUNT (0)
+    /* @brief DSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_DSPI_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EMVSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+    /* @brief ENC availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENC_COUNT (0)
+    /* @brief ENET availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENET_COUNT (1)
+    /* @brief EWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EWM_COUNT (1)
+    /* @brief FB availability on the SoC. */
+    #define FSL_FEATURE_SOC_FB_COUNT (1)
+    /* @brief FGPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+    /* @brief FLEXIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FSKDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+    /* @brief FTFA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFA_COUNT (0)
+    /* @brief FTFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFE_COUNT (1)
+    /* @brief FTFL availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFL_COUNT (0)
+    /* @brief FTM availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTM_COUNT (4)
+    /* @brief FTMRA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+    /* @brief FTMRE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+    /* @brief FTMRH availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief HSADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_HSADC_COUNT (0)
+    /* @brief I2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2C_COUNT (3)
+    /* @brief I2S availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2S_COUNT (1)
+    /* @brief ICS availability on the SoC. */
+    #define FSL_FEATURE_SOC_ICS_COUNT (0)
+    /* @brief IRQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_IRQ_COUNT (0)
+    /* @brief KBI availability on the SoC. */
+    #define FSL_FEATURE_SOC_KBI_COUNT (0)
+    /* @brief SLCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_SLCD_COUNT (0)
+    /* @brief LCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LCDC_COUNT (0)
+    /* @brief LDO availability on the SoC. */
+    #define FSL_FEATURE_SOC_LDO_COUNT (0)
+    /* @brief LLWU availability on the SoC. */
+    #define FSL_FEATURE_SOC_LLWU_COUNT (1)
+    /* @brief LMEM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LMEM_COUNT (0)
+    /* @brief LPSCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPTPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (0)
+    /* @brief LTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LTC_COUNT (0)
+    /* @brief MC availability on the SoC. */
+    #define FSL_FEATURE_SOC_MC_COUNT (0)
+    /* @brief MCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCG_COUNT (1)
+    /* @brief MCGLITE availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+    /* @brief MCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCM_COUNT (1)
+    /* @brief MMAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMAU_COUNT (0)
+    /* @brief MMDVSQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+    /* @brief MPU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MPU_COUNT (1)
+    /* @brief MSCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+    /* @brief MTB availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTB_COUNT (0)
+    /* @brief MTBDWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
+    /* @brief NFC availability on the SoC. */
+    #define FSL_FEATURE_SOC_NFC_COUNT (0)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+    /* @brief OSC availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSC_COUNT (1)
+    /* @brief OTFAD availability on the SoC. */
+    #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+    /* @brief PDB availability on the SoC. */
+    #define FSL_FEATURE_SOC_PDB_COUNT (1)
+    /* @brief PGA availability on the SoC. */
+    #define FSL_FEATURE_SOC_PGA_COUNT (0)
+    /* @brief PIT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PIT_COUNT (1)
+    /* @brief PMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_PMC_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (0)
+    /* @brief PWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWT_COUNT (0)
+    /* @brief QuadSPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+    /* @brief RCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RCM_COUNT (1)
+    /* @brief RFSYS availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+    /* @brief RFVBAT availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+    /* @brief RNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNG_COUNT (1)
+    /* @brief RNGB availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNGB_COUNT (0)
+    /* @brief ROM availability on the SoC. */
+    #define FSL_FEATURE_SOC_ROM_COUNT (0)
+    /* @brief RSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RSIM_COUNT (0)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCI_COUNT (0)
+    /* @brief SDHC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDHC_COUNT (1)
+    /* @brief SDRAM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+    /* @brief SIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SIM_COUNT (1)
+    /* @brief SMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMC_COUNT (1)
+    /* @brief SPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPI_COUNT (0)
+    /* @brief TMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_TMR_COUNT (0)
+    /* @brief TPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_TPM_COUNT (0)
+    /* @brief TRIAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+    /* @brief TRNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRNG_COUNT (0)
+    /* @brief TSI availability on the SoC. */
+    #define FSL_FEATURE_SOC_TSI_COUNT (0)
+    /* @brief UART availability on the SoC. */
+    #define FSL_FEATURE_SOC_UART_COUNT (6)
+    /* @brief USB availability on the SoC. */
+    #define FSL_FEATURE_SOC_USB_COUNT (1)
+    /* @brief USBDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+    /* @brief USBHSDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+    /* @brief USBPHY availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+    /* @brief VREF availability on the SoC. */
+    #define FSL_FEATURE_SOC_VREF_COUNT (1)
+    /* @brief WDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_WDOG_COUNT (1)
+    /* @brief XBAR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XBAR_COUNT (0)
+    /* @brief XCVR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XCVR_COUNT (0)
+    /* @brief ZLL availability on the SoC. */
+    #define FSL_FEATURE_SOC_ZLL_COUNT (0)
+#elif defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12)
+    /* @brief ACMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_ACMP_COUNT (0)
+    /* @brief ADC16 availability on the SoC. */
+    #define FSL_FEATURE_SOC_ADC16_COUNT (2)
+    /* @brief AFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_AFE_COUNT (0)
+    /* @brief AIPS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AIPS_COUNT (2)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (0)
+    /* @brief AXBS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AXBS_COUNT (1)
+    /* @brief CADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CADC_COUNT (0)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief MMCAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
+    /* @brief CMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMP_COUNT (3)
+    /* @brief CMT availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMT_COUNT (1)
+    /* @brief CNC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CNC_COUNT (0)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief DAC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DAC_COUNT (1)
+    /* @brief DCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DCDC_COUNT (0)
+    /* @brief DDR availability on the SoC. */
+    #define FSL_FEATURE_SOC_DDR_COUNT (0)
+    /* @brief DMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMA_COUNT (0)
+    /* @brief DMAMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+    /* @brief DRY availability on the SoC. */
+    #define FSL_FEATURE_SOC_DRY_COUNT (0)
+    /* @brief DSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_DSPI_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EMVSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+    /* @brief ENC availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENC_COUNT (0)
+    /* @brief ENET availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENET_COUNT (1)
+    /* @brief EWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EWM_COUNT (1)
+    /* @brief FB availability on the SoC. */
+    #define FSL_FEATURE_SOC_FB_COUNT (1)
+    /* @brief FGPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+    /* @brief FLEXIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FSKDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+    /* @brief FTFA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFA_COUNT (0)
+    /* @brief FTFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFE_COUNT (1)
+    /* @brief FTFL availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFL_COUNT (0)
+    /* @brief FTM availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTM_COUNT (4)
+    /* @brief FTMRA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+    /* @brief FTMRE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+    /* @brief FTMRH availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief HSADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_HSADC_COUNT (0)
+    /* @brief I2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2C_COUNT (3)
+    /* @brief I2S availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2S_COUNT (1)
+    /* @brief ICS availability on the SoC. */
+    #define FSL_FEATURE_SOC_ICS_COUNT (0)
+    /* @brief IRQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_IRQ_COUNT (0)
+    /* @brief KBI availability on the SoC. */
+    #define FSL_FEATURE_SOC_KBI_COUNT (0)
+    /* @brief SLCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_SLCD_COUNT (0)
+    /* @brief LCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LCDC_COUNT (0)
+    /* @brief LDO availability on the SoC. */
+    #define FSL_FEATURE_SOC_LDO_COUNT (0)
+    /* @brief LLWU availability on the SoC. */
+    #define FSL_FEATURE_SOC_LLWU_COUNT (1)
+    /* @brief LMEM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LMEM_COUNT (0)
+    /* @brief LPSCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPTPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (0)
+    /* @brief LTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LTC_COUNT (0)
+    /* @brief MC availability on the SoC. */
+    #define FSL_FEATURE_SOC_MC_COUNT (0)
+    /* @brief MCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCG_COUNT (1)
+    /* @brief MCGLITE availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+    /* @brief MCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCM_COUNT (1)
+    /* @brief MMAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMAU_COUNT (0)
+    /* @brief MMDVSQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+    /* @brief MPU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MPU_COUNT (1)
+    /* @brief MSCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+    /* @brief MTB availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTB_COUNT (0)
+    /* @brief MTBDWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
+    /* @brief NFC availability on the SoC. */
+    #define FSL_FEATURE_SOC_NFC_COUNT (0)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+    /* @brief OSC availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSC_COUNT (1)
+    /* @brief OTFAD availability on the SoC. */
+    #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+    /* @brief PDB availability on the SoC. */
+    #define FSL_FEATURE_SOC_PDB_COUNT (1)
+    /* @brief PGA availability on the SoC. */
+    #define FSL_FEATURE_SOC_PGA_COUNT (0)
+    /* @brief PIT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PIT_COUNT (1)
+    /* @brief PMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_PMC_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (0)
+    /* @brief PWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWT_COUNT (0)
+    /* @brief QuadSPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+    /* @brief RCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RCM_COUNT (1)
+    /* @brief RFSYS availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+    /* @brief RFVBAT availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+    /* @brief RNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNG_COUNT (1)
+    /* @brief RNGB availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNGB_COUNT (0)
+    /* @brief ROM availability on the SoC. */
+    #define FSL_FEATURE_SOC_ROM_COUNT (0)
+    /* @brief RSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RSIM_COUNT (0)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCI_COUNT (0)
+    /* @brief SDHC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDHC_COUNT (1)
+    /* @brief SDRAM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+    /* @brief SIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SIM_COUNT (1)
+    /* @brief SMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMC_COUNT (1)
+    /* @brief SPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPI_COUNT (0)
+    /* @brief TMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_TMR_COUNT (0)
+    /* @brief TPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_TPM_COUNT (0)
+    /* @brief TRIAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+    /* @brief TRNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRNG_COUNT (0)
+    /* @brief TSI availability on the SoC. */
+    #define FSL_FEATURE_SOC_TSI_COUNT (0)
+    /* @brief UART availability on the SoC. */
+    #define FSL_FEATURE_SOC_UART_COUNT (6)
+    /* @brief USB availability on the SoC. */
+    #define FSL_FEATURE_SOC_USB_COUNT (1)
+    /* @brief USBDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+    /* @brief USBHSDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+    /* @brief USBPHY availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+    /* @brief VREF availability on the SoC. */
+    #define FSL_FEATURE_SOC_VREF_COUNT (1)
+    /* @brief WDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_WDOG_COUNT (1)
+    /* @brief XBAR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XBAR_COUNT (0)
+    /* @brief XCVR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XCVR_COUNT (0)
+    /* @brief ZLL availability on the SoC. */
+    #define FSL_FEATURE_SOC_ZLL_COUNT (0)
+#endif
+
+/* CRC module features */
+
+/* @brief Has data register with name CRC */
+#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (DMA_INSTANCE_COUNT * 16)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (DMAMUX_INSTANCE_COUNT * 16)
+/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+
+/* ENET module features */
+
+/* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */
+#define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0)
+/* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */
+#define FSL_FEATURE_ENET_SUPPORT_PTP (1)
+/* @brief Number of associated interrupt vectors. */
+#define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
+/* @brief Errata 2597: No support for IEEE 1588 timestamp timer overflow interrupt. */
+#define FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT_ERRATA_2579 (0)
+/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
+#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
+
+/* EWM module features */
+
+/* @brief Has clock prescaler (register CLKPRESCALER). */
+#define FSL_FEATURE_EWM_HAS_PRESCALER  (0)
+
+/* FLEXBUS module features */
+
+/* No feature definitions */
+
+/* FLASH module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (0)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (1)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (131072)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00020000)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0001C000)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00018000)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00010000)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00000000)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00020000)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+#elif defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (0)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (1)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+#endif
+
+/* FTM module features */
+
+/* @brief Number of channels. */
+#define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
+#define FSL_FEATURE_FTM_CHANNEL_COUNTx { 8, 2, 2, 8 }
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
+
+/* SAI module features */
+
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+#define FSL_FEATURE_SAI_FIFO_COUNT (8)
+/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
+#define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
+#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
+/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
+#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
+/* @brief Ihe interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
+
+/* LLWU module features */
+
+/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+/* @brief Has pins 8-15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+/* @brief Maximum number of internal modules connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+/* @brief Number of digital filters. */
+#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+/* @brief Has MF5 register. */
+#define FSL_FEATURE_LLWU_HAS_MF (0)
+/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1)
+/* @brief Has external pin 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
+/* @brief Has external pin 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
+/* @brief Has external pin 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
+/* @brief Has external pin 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
+/* @brief Has external pin 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
+/* @brief Has external pin 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
+/* @brief Has external pin 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
+/* @brief Has external pin 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
+/* @brief Has external pin 8 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
+/* @brief Has external pin 9 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
+/* @brief Has external pin 10 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
+/* @brief Has external pin 11 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
+/* @brief Has external pin 12 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
+/* @brief Has external pin 13 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
+/* @brief Has external pin 14 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
+/* @brief Has external pin 15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
+/* @brief Has external pin 16 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+/* @brief Has external pin 17 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+/* @brief Has external pin 18 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+/* @brief Has external pin 19 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+/* @brief Has external pin 20 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+/* @brief Has external pin 21 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+/* @brief Has external pin 22 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+/* @brief Has external pin 23 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+/* @brief Has external pin 24 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+/* @brief Has external pin 25 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+/* @brief Has external pin 26 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+/* @brief Has external pin 27 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+/* @brief Has external pin 28 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+/* @brief Has external pin 29 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+/* @brief Has external pin 30 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+/* @brief Has external pin 31 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+/* @brief Has internal module 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+/* @brief Has internal module 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+/* @brief Has internal module 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+/* @brief Has internal module 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+/* @brief Has internal module 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
+/* @brief Has internal module 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+/* @brief Has internal module 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+/* @brief Has internal module 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+
+/* MCG module features */
+
+/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
+/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
+/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
+/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
+/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
+/* @brief The PLL clock is divided by 2 before VCO divider. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
+/* @brief FRDIV supports 1280. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
+/* @brief FRDIV supports 1536. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
+#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
+/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
+#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
+/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_PLL1 (0)
+/* @brief Has 48MHz internal oscillator. */
+#define FSL_FEATURE_MCG_HAS_IRC_48M (1)
+/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_OSC1 (0)
+/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
+#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
+/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
+#define FSL_FEATURE_MCG_HAS_LOLRE (1)
+/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
+#define FSL_FEATURE_MCG_USE_OSCSEL (1)
+/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
+#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
+/* @brief TBD */
+#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL (1)
+/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
+/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
+/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
+#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
+/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
+#define FSL_FEATURE_MCG_HAS_FLL (1)
+/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
+/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
+#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
+/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
+/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
+/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
+#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
+/* @brief Has external clock monitor (register bit C6[CME]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
+/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
+#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
+/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
+#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
+/* @brief Has PEI mode or PBI mode. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
+/* @brief Reset clock mode is BLPI. */
+#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
+
+/* MPU module features */
+
+/* @brief Specifies number of descriptors available. */
+#define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12)
+/* @brief Has process identifier support. */
+#define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1)
+/* @brief Has master 0. */
+#define FSL_FEATURE_MPU_HAS_MASTER0 (1)
+/* @brief Has master 1. */
+#define FSL_FEATURE_MPU_HAS_MASTER1 (1)
+/* @brief Has master 2. */
+#define FSL_FEATURE_MPU_HAS_MASTER2 (1)
+/* @brief Has master 3. */
+#define FSL_FEATURE_MPU_HAS_MASTER3 (1)
+/* @brief Has master 4. */
+#define FSL_FEATURE_MPU_HAS_MASTER4 (1)
+/* @brief Has master 5. */
+#define FSL_FEATURE_MPU_HAS_MASTER5 (1)
+/* @brief Has master 6. */
+#define FSL_FEATURE_MPU_HAS_MASTER6 (0)
+/* @brief Has master 7. */
+#define FSL_FEATURE_MPU_HAS_MASTER7 (0)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
+
+/* OSC module features */
+
+/* @brief Has OSC1 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC1 (0)
+/* @brief Has OSC0 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC0 (0)
+/* @brief Has OSC external oscillator (without index). */
+#define FSL_FEATURE_OSC_HAS_OSC (1)
+/* @brief Number of OSC external oscillators. */
+#define FSL_FEATURE_OSC_OSC_COUNT (1)
+/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
+#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
+
+/* PDB module features */
+
+/* @brief Define the count of supporting ADC pre-trigger for each channel. */
+#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2)
+/* @brief Has DAC support. */
+#define FSL_FEATURE_PDB_HAS_DAC (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (4)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (1)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (1)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (1)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (1)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (1)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (0)
+
+/* RTC module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \
+    defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12)
+    /* @brief Has wakeup pin (bit field CR[WPS]). */
+    #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+    /* @brief Has low power features (registers MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+    /* @brief Has read/write access control (registers WAR and RAR). */
+    #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+    /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_SECURITY (1)
+#elif defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief Has wakeup pin (bit field CR[WPS]). */
+    #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+    /* @brief Has low power features (registers MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+    /* @brief Has read/write access control (registers WAR and RAR). */
+    #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+    /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_SECURITY (0)
+#endif
+
+/* SDHC module features */
+
+/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
+#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1)
+/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
+#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0)
+/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
+#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (1)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
+
+/* DSPI module features */
+
+/* @brief Receive/transmit FIFO size in number of items. */
+#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
+#define FSL_FEATURE_DSPI_FIFO_SIZEx { 4, 1, 1 }
+/* @brief Maximum transfer data width in bits. */
+#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
+/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
+#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
+/* @brief Number of chip select pins. */
+#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
+/* @brief Has chip select strobe capability on the PCS5 pin. */
+#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
+/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+/* @brief Has 16-bit data transfer support. */
+#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (0) : \
+    ((x) == 2 ? (0) : (-1))))
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
+
+/* UART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_HAS_FIFO (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_UART_IS_SCI (0)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_FIFO_SIZE (8)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
+/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
+#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (1) : \
+    ((x) == 2 ? (1) : \
+    ((x) == 3 ? (1) : \
+    ((x) == 4 ? (0) : \
+    ((x) == 5 ? (0) : (-1)))))))
+
+/* USB module features */
+
+/* @brief HOST mode enabled */
+#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
+/* @brief OTG mode enabled */
+#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
+/* @brief Has KEEP_ALIVE_CTRL register */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
+/* @brief Has the Dynamic SOF threshold compare support */
+#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
+/* @brief Has the VBUS detect support */
+#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
+/* @brief Has the IRC48M module clock support */
+#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief Describes the set of SC[MODE_LV] bitfield values */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+
+/* WDOG module features */
+
+/* @brief Watchdog is available. */
+#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
+/* @brief Has Wait mode support. */
+#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
+
+#endif /* __FSL_MK64F12_FEATURES_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/Workspace/4part1/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h b/Workspace/4part1/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
new file mode 100644
index 0000000..0044bbf
--- /dev/null
+++ b/Workspace/4part1/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
@@ -0,0 +1,111 @@
+/*
+** ###################################################################
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Register bit field access macros.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+#ifndef _FSL_BITACCESS_H
+#define _FSL_BITACCESS_H  1
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/**
+ * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+#endif /* _FSL_BITACCESS_H */
+
+/******************************************************************************/
diff --git a/Workspace/4part1/SDK/platform/devices/fsl_device_registers.h b/Workspace/4part1/SDK/platform/devices/fsl_device_registers.h
new file mode 100644
index 0000000..abeb4ac
--- /dev/null
+++ b/Workspace/4part1/SDK/platform/devices/fsl_device_registers.h
@@ -0,0 +1,1083 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2014-05-15
+**     Build:               b141209
+**
+**     Abstract:
+**         Common include file for CMSIS register access layer headers.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-05-15)
+**         Customer release.
+**
+** ###################################################################
+*/
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \
+    defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10))
+
+    #define K02F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK02F12810/include/MK02F12810.h"
+    /* Extension register definitions */
+    #include "MK02F12810/include/MK02F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK02F12810/include/MK02F12810_features.h"
+
+#elif (defined(CPU_MK10DN512VLK10) || defined(CPU_MK10DN512VLL10) || defined(CPU_MK10DX128VLQ10) || \
+    defined(CPU_MK10DX256VLQ10) || defined(CPU_MK10DN512VLQ10) || defined(CPU_MK10DN512VMC10) || \
+    defined(CPU_MK10DX128VMD10) || defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10))
+
+    #define K10D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK10D10/include/MK10D10.h"
+    /* Extension register definitions */
+    #include "MK10D10/include/MK10D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK10D10/include/MK10D10_features.h"
+
+#elif (defined(CPU_MK11DX128AVLK5) || defined(CPU_MK11DX256AVLK5) || defined(CPU_MK11DN512AVLK5) || \
+    defined(CPU_MK11DX128AVMC5) || defined(CPU_MK11DX256AVMC5) || defined(CPU_MK11DN512AVMC5))
+
+    #define K11DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK11DA5/include/MK11DA5.h"
+    /* Extension register definitions */
+    #include "MK11DA5/include/MK11DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK11DA5/include/MK11DA5_features.h"
+
+#elif (defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DX256VLK10) || defined(CPU_MK20DN512VLL10) || \
+    defined(CPU_MK20DX256VLL10) || defined(CPU_MK20DX128VLQ10) || defined(CPU_MK20DX256VLQ10) || \
+    defined(CPU_MK20DN512VLQ10) || defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || \
+    defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || defined(CPU_MK20DN512VMD10))
+
+    #define K20D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D10/include/MK20D10.h"
+    /* Extension register definitions */
+    #include "MK20D10/include/MK20D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D10/include/MK20D10_features.h"
+
+#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \
+    defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
+    defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
+    defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
+    defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \
+    defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
+    defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \
+    defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
+    defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
+    defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5))
+
+    #define K20D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D5/include/MK20D5.h"
+    /* Extension register definitions */
+    #include "MK20D5/include/MK20D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D5/include/MK20D5_features.h"
+
+#elif (defined(CPU_MK21DX128AVLK5) || defined(CPU_MK21DX256AVLK5) || defined(CPU_MK21DN512AVLK5) || \
+    defined(CPU_MK21DX128AVMC5) || defined(CPU_MK21DX256AVMC5) || defined(CPU_MK21DN512AVMC5))
+
+    #define K21DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21DA5/include/MK21DA5.h"
+    /* Extension register definitions */
+    #include "MK21DA5/include/MK21DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21DA5/include/MK21DA5_features.h"
+
+#elif (defined(CPU_MK21FX512AVLQ12) || defined(CPU_MK21FN1M0AVLQ12) || defined(CPU_MK21FX512AVMC12) || \
+    defined(CPU_MK21FN1M0AVMC12) || defined(CPU_MK21FX512AVMD12) || defined(CPU_MK21FN1M0AVMD12))
+
+    #define K21FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21FA12/include/MK21FA12.h"
+    /* Extension register definitions */
+    #include "MK21FA12/include/MK21FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21FA12/include/MK21FA12_features.h"
+
+#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \
+    defined(CPU_MK22FN128VMP10))
+
+    #define K22F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F12810/include/MK22F12810.h"
+    /* Extension register definitions */
+    #include "MK22F12810/include/MK22F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F12810/include/MK22F12810_features.h"
+
+#elif (defined(CPU_MK22FX512AVLH12) || defined(CPU_MK22FN1M0AVLH12) || defined(CPU_MK22FX512AVLK12) || \
+    defined(CPU_MK22FN1M0AVLK12) || defined(CPU_MK22FX512AVLL12) || defined(CPU_MK22FN1M0AVLL12) || \
+    defined(CPU_MK22FX512AVLQ12) || defined(CPU_MK22FN1M0AVLQ12) || defined(CPU_MK22FX512AVMC12) || \
+    defined(CPU_MK22FN1M0AVMC12) || defined(CPU_MK22FX512AVMD12) || defined(CPU_MK22FN1M0AVMD12))
+
+    #define K22FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22FA12/include/MK22FA12.h"
+    /* Extension register definitions */
+    #include "MK22FA12/include/MK22FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22FA12/include/MK22FA12_features.h"
+
+#elif (defined(CPU_MK22FN256CAH12) || defined(CPU_MK22FN128CAH12) || defined(CPU_MK22FN256VDC12) || \
+    defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12))
+
+    #define K22F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F25612/include/MK22F25612.h"
+    /* Extension register definitions */
+    #include "MK22F25612/include/MK22F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F25612/include/MK22F25612_features.h"
+
+#elif (defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
+    defined(CPU_MK22FN512VLL12) || defined(CPU_MK22FN512VMP12))
+
+    #define K22F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F51212/include/MK22F51212.h"
+    /* Extension register definitions */
+    #include "MK22F51212/include/MK22F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F51212/include/MK22F51212_features.h"
+
+#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12))
+
+    #define K24F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F12/include/MK24F12.h"
+    /* Extension register definitions */
+    #include "MK24F12/include/MK24F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F12/include/MK24F12_features.h"
+
+#elif (defined(CPU_MK24FN256VDC12))
+
+    #define K24F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F25612/include/MK24F25612.h"
+    /* Extension register definitions */
+    #include "MK24F25612/include/MK24F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F25612/include/MK24F25612_features.h"
+
+#elif (defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VLQ18) || defined(CPU_MK26FN2M0VMD18) || \
+    defined(CPU_MK26FN2M0VMI18))
+
+    #define K26F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK26F18/include/MK26F18.h"
+    /* Extension register definitions */
+    #include "MK26F18/include/MK26F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK26F18/include/MK26F18_features.h"
+
+#elif (defined(CPU_MK30DN512VLK10) || defined(CPU_MK30DN512VLL10) || defined(CPU_MK30DX128VLQ10) || \
+    defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMC10) || \
+    defined(CPU_MK30DX128VMD10) || defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10))
+
+    #define K30D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK30D10/include/MK30D10.h"
+    /* Extension register definitions */
+    #include "MK30D10/include/MK30D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK30D10/include/MK30D10_features.h"
+
+#elif (defined(CPU_MK40DN512VLK10) || defined(CPU_MK40DN512VLL10) || defined(CPU_MK40DX128VLQ10) || \
+    defined(CPU_MK40DX256VLQ10) || defined(CPU_MK40DN512VLQ10) || defined(CPU_MK40DN512VMC10) || \
+    defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || defined(CPU_MK40DN512VMD10))
+
+    #define K40D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK40D10/include/MK40D10.h"
+    /* Extension register definitions */
+    #include "MK40D10/include/MK40D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK40D10/include/MK40D10_features.h"
+
+#elif (defined(CPU_MK50DX256CLL10) || defined(CPU_MK50DN512CLL10) || defined(CPU_MK50DN512CLQ10) || \
+    defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || defined(CPU_MK50DN512CMD10) || \
+    defined(CPU_MK50DX256CMD10) || defined(CPU_MK50DX256CLK10))
+
+    #define K50D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK50D10/include/MK50D10.h"
+    /* Extension register definitions */
+    #include "MK50D10/include/MK50D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK50D10/include/MK50D10_features.h"
+
+#elif (defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10) || defined(CPU_MK51DN256CLQ10) || \
+    defined(CPU_MK51DN512CLQ10) || defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || \
+    defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10) || defined(CPU_MK51DX256CLK10))
+
+    #define K51D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK51D10/include/MK51D10.h"
+    /* Extension register definitions */
+    #include "MK51D10/include/MK51D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK51D10/include/MK51D10_features.h"
+
+#elif (defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10))
+
+    #define K52D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK52D10/include/MK52D10.h"
+    /* Extension register definitions */
+    #include "MK52D10/include/MK52D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK52D10/include/MK52D10_features.h"
+
+#elif (defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || defined(CPU_MK53DN512CMD10) || \
+    defined(CPU_MK53DX256CMD10))
+
+    #define K53D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK53D10/include/MK53D10.h"
+    /* Extension register definitions */
+    #include "MK53D10/include/MK53D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK53D10/include/MK53D10_features.h"
+
+#elif (defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DN512VLL10) || \
+    defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DN512VLQ10) || \
+    defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || defined(CPU_MK60DN512VMC10) || \
+    defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10))
+
+    #define K60D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK60D10/include/MK60D10.h"
+    /* Extension register definitions */
+    #include "MK60D10/include/MK60D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK60D10/include/MK60D10_features.h"
+
+#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12))
+
+    #define K63F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK63F12/include/MK63F12.h"
+    /* Extension register definitions */
+    #include "MK63F12/include/MK63F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK63F12/include/MK63F12_features.h"
+
+#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
+    defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12))
+
+
+    #define K64F12_SERIES
+    /* CMSIS-style register definitions */
+    #include "MK64F12/include/MK64F12.h"
+    /* Extension register definitions */
+    #include "MK64F12/include/MK64F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK64F12/include/MK64F12_features.h"
+
+#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
+    defined(CPU_MK65FX1M0VMI18))
+
+    #define K65F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK65F18/include/MK65F18.h"
+    /* Extension register definitions */
+    #include "MK65F18/include/MK65F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK65F18/include/MK65F18_features.h"
+
+#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
+    defined(CPU_MK66FX1M0VMD18))
+
+    #define K66F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK66F18/include/MK66F18.h"
+    /* Extension register definitions */
+    #include "MK66F18/include/MK66F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK66F18/include/MK66F18_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12))
+
+    #define K70F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F12/include/MK70F12.h"
+    /* Extension register definitions */
+    #include "MK70F12/include/MK70F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F12/include/MK70F12_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+
+    #define K70F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F15/include/MK70F15.h"
+    /* Extension register definitions */
+    #include "MK70F15/include/MK70F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F15/include/MK70F15_features.h"
+
+#elif (defined(CPU_MK80FN256CAx15) || defined(CPU_MK80FN256VDC15) || defined(CPU_MK80FN256VLL15) || \
+    defined(CPU_MK80FN256VLQ15))
+
+    #define K80F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK80F25615/include/MK80F25615.h"
+    /* Extension register definitions */
+    #include "MK80F25615/include/MK80F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK80F25615/include/MK80F25615_features.h"
+
+#elif (defined(CPU_MK81FN256CAx15) || defined(CPU_MK81FN256VDC15) || defined(CPU_MK81FN256VLL15) || \
+    defined(CPU_MK81FN256VLQ15))
+
+    #define K81F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK81F25615/include/MK81F25615.h"
+    /* Extension register definitions */
+    #include "MK81F25615/include/MK81F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK81F25615/include/MK81F25615_features.h"
+
+#elif (defined(CPU_MK82FN256CAx15) || defined(CPU_MK82FN256VDC15) || defined(CPU_MK82FN256VLL15) || \
+    defined(CPU_MK82FN256VLQ15))
+
+    #define K82F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK82F25615/include/MK82F25615.h"
+    /* Extension register definitions */
+    #include "MK82F25615/include/MK82F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK82F25615/include/MK82F25615_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC2) || defined(CPU_MKE02Z32VLC2) || defined(CPU_MKE02Z16VLC2) || \
+    defined(CPU_MKE02Z64VLD2) || defined(CPU_MKE02Z32VLD2) || defined(CPU_MKE02Z16VLD2) || \
+    defined(CPU_MKE02Z64VLH2) || defined(CPU_MKE02Z64VQH2) || defined(CPU_MKE02Z32VLH2) || \
+    defined(CPU_MKE02Z32VQH2))
+
+    #define KE02Z2_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z2/include/MKE02Z2.h"
+    /* Extension register definitions */
+    #include "MKE02Z2/include/MKE02Z2_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z2/include/MKE02Z2_features.h"
+
+#elif (defined(CPU_SKEAZN64MLC2) || defined(CPU_SKEAZN32MLC2) || defined(CPU_SKEAZN16MLC2) || \
+    defined(CPU_SKEAZN64MLD2) || defined(CPU_SKEAZN32MLD2) || defined(CPU_SKEAZN16MLD2) || \
+    defined(CPU_SKEAZN64MLH2) || defined(CPU_SKEAZN32MLH2))
+
+    #define SKEAZN642_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN642/include/SKEAZN642.h"
+    /* Extension register definitions */
+    #include "SKEAZN642/include/SKEAZN642_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN642/include/SKEAZN642_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC4) || defined(CPU_MKE02Z32VLC4) || defined(CPU_MKE02Z16VLC4) || \
+    defined(CPU_MKE02Z64VLD4) || defined(CPU_MKE02Z32VLD4) || defined(CPU_MKE02Z16VLD4) || \
+    defined(CPU_MKE02Z64VLH4) || defined(CPU_MKE02Z64VQH4) || defined(CPU_MKE02Z32VLH4) || \
+    defined(CPU_MKE02Z32VQH4))
+
+    #define KE02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z4/include/MKE02Z4.h"
+    /* Extension register definitions */
+    #include "MKE02Z4/include/MKE02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z4/include/MKE02Z4_features.h"
+
+#elif (defined(CPU_MKE04Z128VLD4) || defined(CPU_MKE04Z64VLD4) || defined(CPU_MKE04Z128VLK4) || \
+    defined(CPU_MKE04Z64VLK4) || defined(CPU_MKE04Z128VQH4) || defined(CPU_MKE04Z64VQH4) || \
+    defined(CPU_MKE04Z128VLH4) || defined(CPU_MKE04Z64VLH4))
+
+    #define KE04Z1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284.h"
+    /* Extension register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_features.h"
+
+#elif (defined(CPU_MKE04Z8VFK4) || defined(CPU_MKE04Z8VTG4) || defined(CPU_MKE04Z8VWJ4))
+
+    #define KE04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z4/include/MKE04Z4.h"
+    /* Extension register definitions */
+    #include "MKE04Z4/include/MKE04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z4/include/MKE04Z4_features.h"
+
+#elif (defined(CPU_SKEAZN8MFK) || defined(CPU_SKEAZN8MTG))
+
+    #define SKEAZN84_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN84/include/SKEAZN84.h"
+    /* Extension register definitions */
+    #include "SKEAZN84/include/SKEAZN84_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN84/include/SKEAZN84_features.h"
+
+#elif (defined(CPU_MKE06Z128VLD4) || defined(CPU_MKE06Z64VLD4) || defined(CPU_MKE06Z128VLK4) || \
+    defined(CPU_MKE06Z64VLK4) || defined(CPU_MKE06Z128VQH4) || defined(CPU_MKE06Z64VQH4) || \
+    defined(CPU_MKE06Z128VLH4) || defined(CPU_MKE06Z64VLH4))
+
+    #define KE06Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE06Z4/include/MKE06Z4.h"
+    /* Extension register definitions */
+    #include "MKE06Z4/include/MKE06Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE06Z4/include/MKE06Z4_features.h"
+
+#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
+    defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \
+    defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4))
+
+    #define KL02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL02Z4/include/MKL02Z4.h"
+    /* Extension register definitions */
+    #include "MKL02Z4/include/MKL02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL02Z4/include/MKL02Z4_features.h"
+
+#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \
+    defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \
+    defined(CPU_MKL03Z32VFK4))
+
+    #define KL03Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL03Z4/include/MKL03Z4.h"
+    /* Extension register definitions */
+    #include "MKL03Z4/include/MKL03Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL03Z4/include/MKL03Z4_features.h"
+
+#elif (defined(CPU_MKL04Z8VFK4) || defined(CPU_MKL04Z16VFK4) || defined(CPU_MKL04Z32VFK4) || \
+    defined(CPU_MKL04Z8VLC4) || defined(CPU_MKL04Z16VLC4) || defined(CPU_MKL04Z32VLC4) || \
+    defined(CPU_MKL04Z8VFM4) || defined(CPU_MKL04Z16VFM4) || defined(CPU_MKL04Z32VFM4) || \
+    defined(CPU_MKL04Z16VLF4) || defined(CPU_MKL04Z32VLF4))
+
+    #define KL04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL04Z4/include/MKL04Z4.h"
+    /* Extension register definitions */
+    #include "MKL04Z4/include/MKL04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL04Z4/include/MKL04Z4_features.h"
+
+#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \
+    defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
+    defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
+    defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4))
+
+    #define KL05Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL05Z4/include/MKL05Z4.h"
+    /* Extension register definitions */
+    #include "MKL05Z4/include/MKL05Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL05Z4/include/MKL05Z4_features.h"
+
+#elif (defined(CPU_MKL13Z32VFM4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z32VFT4) || \
+    defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z32VLH4) || defined(CPU_MKL13Z64VLH4) || \
+    defined(CPU_MKL13Z32VLK4) || defined(CPU_MKL13Z64VLK4) || defined(CPU_MKL13Z32VMP4) || \
+    defined(CPU_MKL13Z64VMP4))
+
+    #define KL13Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL13Z644/include/MKL13Z644.h"
+    /* Extension register definitions */
+    #include "MKL13Z644/include/MKL13Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL13Z644/include/MKL13Z644_features.h"
+
+#elif (defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || defined(CPU_MKL14Z32VFT4) || \
+    defined(CPU_MKL14Z64VFT4) || defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || \
+    defined(CPU_MKL14Z32VLK4) || defined(CPU_MKL14Z64VLK4))
+
+    #define KL14Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL14Z4/include/MKL14Z4.h"
+    /* Extension register definitions */
+    #include "MKL14Z4/include/MKL14Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL14Z4/include/MKL14Z4_features.h"
+
+#elif (defined(CPU_MKL15Z128CAD4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || \
+    defined(CPU_MKL15Z128VFM4) || defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || \
+    defined(CPU_MKL15Z128VFT4) || defined(CPU_MKL15Z32VLH4) || defined(CPU_MKL15Z64VLH4) || \
+    defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || defined(CPU_MKL15Z64VLK4) || \
+    defined(CPU_MKL15Z128VLK4))
+
+    #define KL15Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL15Z4/include/MKL15Z4.h"
+    /* Extension register definitions */
+    #include "MKL15Z4/include/MKL15Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL15Z4/include/MKL15Z4_features.h"
+
+#elif (defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || \
+    defined(CPU_MKL16Z32VFT4) || defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || \
+    defined(CPU_MKL16Z32VLH4) || defined(CPU_MKL16Z64VLH4) || defined(CPU_MKL16Z128VLH4) || \
+    defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VMP4))
+
+    #define KL16Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL16Z4/include/MKL16Z4.h"
+    /* Extension register definitions */
+    #include "MKL16Z4/include/MKL16Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL16Z4/include/MKL16Z4_features.h"
+
+#elif (defined(CPU_MKL17Z128VFM4) || defined(CPU_MKL17Z256VFM4) || defined(CPU_MKL17Z128VFT4) || \
+    defined(CPU_MKL17Z256VFT4) || defined(CPU_MKL17Z128VLH4) || defined(CPU_MKL17Z256VLH4) || \
+    defined(CPU_MKL17Z128VMP4) || defined(CPU_MKL17Z256VMP4))
+
+    #define KL17Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z4/include/MKL17Z4.h"
+    /* Extension register definitions */
+    #include "MKL17Z4/include/MKL17Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z4/include/MKL17Z4_features.h"
+
+#elif (defined(CPU_MKL17Z32VDA4) || defined(CPU_MKL17Z64VDA4) || defined(CPU_MKL17Z32VFM4) || \
+    defined(CPU_MKL17Z64VFM4) || defined(CPU_MKL17Z32VFT4) || defined(CPU_MKL17Z64VFT4) || \
+    defined(CPU_MKL17Z32VLH4) || defined(CPU_MKL17Z64VLH4) || defined(CPU_MKL17Z32VMP4) || \
+    defined(CPU_MKL17Z64VMP4))
+
+    #define KL17Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z644/include/MKL17Z644.h"
+    /* Extension register definitions */
+    #include "MKL17Z644/include/MKL17Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z644/include/MKL17Z644_features.h"
+
+#elif (defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || defined(CPU_MKL24Z32VFT4) || \
+    defined(CPU_MKL24Z64VFT4) || defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || \
+    defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4))
+
+    #define KL24Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL24Z4/include/MKL24Z4.h"
+    /* Extension register definitions */
+    #include "MKL24Z4/include/MKL24Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL24Z4/include/MKL24Z4_features.h"
+
+#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
+    defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
+    defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
+    defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
+
+    #define KL25Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL25Z4/include/MKL25Z4.h"
+    /* Extension register definitions */
+    #include "MKL25Z4/include/MKL25Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL25Z4/include/MKL25Z4_features.h"
+
+
+#elif (defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || \
+    defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || \
+    defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || \
+    defined(CPU_MKL26Z128VLH4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z128VLL4) || \
+    defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
+    defined(CPU_MKL26Z256VMP4))
+
+    #define KL26Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL26Z4/include/MKL26Z4.h"
+    /* Extension register definitions */
+    #include "MKL26Z4/include/MKL26Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL26Z4/include/MKL26Z4_features.h"
+
+#elif (defined(CPU_MKL27Z128VFM4) || defined(CPU_MKL27Z256VFM4) || defined(CPU_MKL27Z128VFT4) || \
+    defined(CPU_MKL27Z256VFT4) || defined(CPU_MKL27Z128VLH4) || defined(CPU_MKL27Z256VLH4) || \
+    defined(CPU_MKL27Z128VMP4) || defined(CPU_MKL27Z256VMP4))
+
+    #define KL27Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z4/include/MKL27Z4.h"
+    /* Extension register definitions */
+    #include "MKL27Z4/include/MKL27Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z4/include/MKL27Z4_features.h"
+
+#elif (defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z64VDA4) || defined(CPU_MKL27Z32VFM4) || \
+    defined(CPU_MKL27Z64VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z64VFT4) || \
+    defined(CPU_MKL27Z32VLH4) || defined(CPU_MKL27Z64VLH4) || defined(CPU_MKL27Z32VMP4) || \
+    defined(CPU_MKL27Z64VMP4))
+
+    #define KL27Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z644/include/MKL27Z644.h"
+    /* Extension register definitions */
+    #include "MKL27Z644/include/MKL27Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z644/include/MKL27Z644_features.h"
+
+#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \
+    defined(CPU_MKL33Z256VMP4))
+
+    #define KL33Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z4/include/MKL33Z4.h"
+    /* Extension register definitions */
+    #include "MKL33Z4/include/MKL33Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z4/include/MKL33Z4_features.h"
+
+#elif (defined(CPU_MKL33Z32VFT4) || defined(CPU_MKL33Z64VFT4) || defined(CPU_MKL33Z32VLH4) || \
+    defined(CPU_MKL33Z64VLH4) || defined(CPU_MKL33Z32VLK4) || defined(CPU_MKL33Z64VLK4) || \
+    defined(CPU_MKL33Z32VMP4) || defined(CPU_MKL33Z64VMP4))
+
+    #define KL33Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z644/include/MKL33Z644.h"
+    /* Extension register definitions */
+    #include "MKL33Z644/include/MKL33Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z644/include/MKL33Z644_features.h"
+
+#elif (defined(CPU_MKL34Z64VLH4) || defined(CPU_MKL34Z64VLL4))
+
+    #define KL34Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL34Z4/include/MKL34Z4.h"
+    /* Extension register definitions */
+    #include "MKL34Z4/include/MKL34Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL34Z4/include/MKL34Z4_features.h"
+
+#elif (defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || \
+    defined(CPU_MKL36Z64VLL4) || defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || \
+    defined(CPU_MKL36Z128VMC4) || defined(CPU_MKL36Z256VMC4) || defined(CPU_MKL36Z256VMP4))
+
+    #define KL36Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL36Z4/include/MKL36Z4.h"
+    /* Extension register definitions */
+    #include "MKL36Z4/include/MKL36Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL36Z4/include/MKL36Z4_features.h"
+
+#elif (defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z128VMP4) || \
+    defined(CPU_MKL43Z256VMP4))
+
+    #define KL43Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL43Z4/include/MKL43Z4.h"
+    /* Extension register definitions */
+    #include "MKL43Z4/include/MKL43Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL43Z4/include/MKL43Z4_features.h"
+
+#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
+    defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \
+    defined(CPU_MKL46Z256VMP4))
+
+    #define KL46Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL46Z4/include/MKL46Z4.h"
+    /* Extension register definitions */
+    #include "MKL46Z4/include/MKL46Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL46Z4/include/MKL46Z4_features.h"
+
+#elif (defined(CPU_MKM14Z128AHH5) || defined(CPU_MKM14Z64AHH5))
+
+    #define KM14ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5.h"
+    /* Extension register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_features.h"
+
+#elif (defined(CPU_MKM33Z128ALH5) || defined(CPU_MKM33Z64ALH5) || defined(CPU_MKM33Z128ALL5) || \
+    defined(CPU_MKM33Z64ALL5))
+
+    #define KM33ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5.h"
+    /* Extension register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z128ALL5))
+
+    #define KM34ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5.h"
+    /* Extension register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z256VLL7) || defined(CPU_MKM34Z256VLQ7))
+
+    #define KM34Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34Z7/include/MKM34Z7.h"
+    /* Extension register definitions */
+    #include "MKM34Z7/include/MKM34Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34Z7/include/MKM34Z7_features.h"
+
+#elif (defined(CPU_MKV10Z16VFM7) || defined(CPU_MKV10Z16VLC7) || defined(CPU_MKV10Z16VLF7) || \
+    defined(CPU_MKV10Z32VFM7) || defined(CPU_MKV10Z32VLC7) || defined(CPU_MKV10Z32VLF7))
+
+    #define KV10Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z7/include/MKV10Z7.h"
+    /* Extension register definitions */
+    #include "MKV10Z7/include/MKV10Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z7/include/MKV10Z7_features.h"
+
+#elif (defined(CPU_MKV10Z128VFM7) || defined(CPU_MKV10Z128VLC7) || defined(CPU_MKV10Z128VLF7) || \
+    defined(CPU_MKV10Z128VLH7) || defined(CPU_MKV10Z64VFM7) || defined(CPU_MKV10Z64VLC7) || \
+    defined(CPU_MKV10Z64VLF7) || defined(CPU_MKV10Z64VLH7))
+
+    #define KV10Z1287_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z1287/include/MKV10Z1287.h"
+    /* Extension register definitions */
+    #include "MKV10Z1287/include/MKV10Z1287_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z1287/include/MKV10Z1287_features.h"
+
+#elif (defined(CPU_MKV11Z128VFM7) || defined(CPU_MKV11Z128VLC7) || defined(CPU_MKV11Z128VLF7) || \
+    defined(CPU_MKV11Z128VLH7) || defined(CPU_MKV11Z64VFM7) || defined(CPU_MKV11Z64VLC7) || \
+    defined(CPU_MKV11Z64VLF7) || defined(CPU_MKV11Z64VLH7))
+
+    #define KV11Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV11Z7/include/MKV11Z7.h"
+    /* Extension register definitions */
+    #include "MKV11Z7/include/MKV11Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV11Z7/include/MKV11Z7_features.h"
+
+#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
+    defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10))
+
+    #define KV30F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV30F12810/include/MKV30F12810.h"
+    /* Extension register definitions */
+    #include "MKV30F12810/include/MKV30F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV30F12810/include/MKV30F12810_features.h"
+
+#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10))
+
+    #define KV31F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F12810/include/MKV31F12810.h"
+    /* Extension register definitions */
+    #include "MKV31F12810/include/MKV31F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F12810/include/MKV31F12810_features.h"
+
+#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12))
+
+    #define KV31F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F25612/include/MKV31F25612.h"
+    /* Extension register definitions */
+    #include "MKV31F25612/include/MKV31F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F25612/include/MKV31F25612_features.h"
+
+#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12))
+
+    #define KV31F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F51212/include/MKV31F51212.h"
+    /* Extension register definitions */
+    #include "MKV31F51212/include/MKV31F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F51212/include/MKV31F51212_features.h"
+
+#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
+    defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15))
+
+    #define KV40F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV40F15/include/MKV40F15.h"
+    /* Extension register definitions */
+    #include "MKV40F15/include/MKV40F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV40F15/include/MKV40F15_features.h"
+
+#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15))
+
+    #define KV43F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV43F15/include/MKV43F15.h"
+    /* Extension register definitions */
+    #include "MKV43F15/include/MKV43F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV43F15/include/MKV43F15_features.h"
+
+#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15))
+
+    #define KV44F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV44F15/include/MKV44F15.h"
+    /* Extension register definitions */
+    #include "MKV44F15/include/MKV44F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV44F15/include/MKV44F15_features.h"
+
+#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \
+    defined(CPU_MKV45F256VLL15))
+
+    #define KV45F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV45F15/include/MKV45F15.h"
+    /* Extension register definitions */
+    #include "MKV45F15/include/MKV45F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV45F15/include/MKV45F15_features.h"
+
+#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \
+    defined(CPU_MKV46F256VLL15))
+
+    #define KV46F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV46F15/include/MKV46F15.h"
+    /* Extension register definitions */
+    #include "MKV46F15/include/MKV46F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV46F15/include/MKV46F15_features.h"
+
+#elif (defined(CPU_MKW01Z128CHN4))
+
+    #define KW01Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW01Z4/include/MKW01Z4.h"
+    /* Extension register definitions */
+    #include "MKW01Z4/include/MKW01Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW01Z4/include/MKW01Z4_features.h"
+
+#elif (defined(CPU_MKW20Z160VHT4))
+
+    #define KW20Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW20Z4/include/MKW20Z4.h"
+    /* Extension register definitions */
+    #include "MKW20Z4/include/MKW20Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW20Z4/include/MKW20Z4_features.h"
+
+#elif (defined(CPU_MKW21D256VHA5) || defined(CPU_MKW21D512VHA5))
+
+    #define KW21D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW21D5/include/MKW21D5.h"
+    /* Extension register definitions */
+    #include "MKW21D5/include/MKW21D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW21D5/include/MKW21D5_features.h"
+
+#elif (defined(CPU_MKW22D512VHA5))
+
+    #define KW22D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW22D5/include/MKW22D5.h"
+    /* Extension register definitions */
+    #include "MKW22D5/include/MKW22D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW22D5/include/MKW22D5_features.h"
+
+#elif (defined(CPU_MKW24D512VHA5))
+
+    #define KW24D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW24D5/include/MKW24D5.h"
+    /* Extension register definitions */
+    #include "MKW24D5/include/MKW24D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW24D5/include/MKW24D5_features.h"
+
+#elif (defined(CPU_MKW30Z160VHM4))
+
+    #define KW30Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW30Z4/include/MKW30Z4.h"
+    /* Extension register definitions */
+    #include "MKW30Z4/include/MKW30Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW30Z4/include/MKW30Z4_features.h"
+
+#elif (defined(CPU_MKW40Z160VHT4))
+
+    #define KW40Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW40Z4/include/MKW40Z4.h"
+    /* Extension register definitions */
+    #include "MKW40Z4/include/MKW40Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW40Z4/include/MKW40Z4_features.h"
+
+#elif (defined(CPU_SKEAZ128MLH) || defined(CPU_SKEAZ64MLH) || defined(CPU_SKEAZ128MLK) || \
+    defined(CPU_SKEAZ64MLK))
+
+    #define SKEAZ1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284.h"
+    /* Extension register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/Workspace/4part1/Sources/main.c b/Workspace/4part1/Sources/main.c
new file mode 100644
index 0000000..3ba0e3e
--- /dev/null
+++ b/Workspace/4part1/Sources/main.c
@@ -0,0 +1,54 @@
+#include "fsl_device_registers.h"
+#include "fsl_gpio_hal.h"
+#include "fsl_sim_hal.h"
+#include "fsl_port_hal.h"
+#include "fsl_pit_hal.h"
+
+
+
+
+#define PORT_PIN	      0x1A
+#define PIT_Module        0
+#define PIT_Period        60000
+#define SIM_BASE          (0x40047000u)
+#define PORTE_BASE        (0x4004D000u)
+#define PTE_BASE          (0x400FF100u)
+#define PIT_BASE          (0x40037000u)
+
+#define PIT_Overflow      PIT_HAL_IsIntPending(PIT_BASE, 0)
+
+void PIT_Delay (long pit_delay);
+
+
+int main(void)
+{
+
+  SIM_HAL_EnableClock(SIM_BASE, kSimClockGatePortE); // Enable Port E Clock Gate
+  SIM_HAL_EnableClock(SIM_BASE, kSimClockGatePit0); // Enable PIT Clock Gates
+
+  PORT_HAL_SetMuxMode(PORTE_BASE, PORT_PIN, kPortMuxAsGpio);           // Configure PORTE, Pin 26, MUX as a GPIO
+
+  GPIO_HAL_SetPinDir(PTE_BASE, PORT_PIN, kGpioDigitalOutput);          // Configure PORTE, Pin 26, as an Output
+
+
+  // Initialize PIT 0
+  PIT_HAL_SetTimerRunInDebugCmd(PIT_BASE, true);                       // Allow PIT timer to run in Debug Mode
+  PIT_HAL_Enable(PIT_BASE);                                            // Enables PIT timers
+  PIT_HAL_StopTimer(PIT_BASE, PIT_Module);                             // Disable PIT0 Timer
+  PIT_HAL_SetTimerPeriodByCount(PIT_BASE, PIT_Module, PIT_Period);     // PIT0 Timer count value, PIT Period=1ms, busclk=60,000,000Hz, Period=1ms/(1/60000000Hz)=60000
+  PIT_HAL_StartTimer(PIT_BASE, PIT_Module);                            // Start PIT0 Timer
+
+
+  for (;;)
+  {
+
+    PIT_Delay(100);                                                      // Delay 100ms
+    GPIO_HAL_TogglePinOutput(PTE_BASE, PORT_PIN);                        // Toggle GREEN LED
+
+  }
+
+  return 0;                                                            // Main.c return
+}
+
+void PIT_Delay (long pit_delay)                                      // Delay in multiples of 1ms (e.g. use 1000 for 1 second)
+{long pit_i; for (pit_i=0;pit_i<pit_delay;pit_i++) {while (!PIT_Overflow); PIT_HAL_ClearIntFlag(PIT_BASE, PIT_Module);}}
diff --git a/Workspace/ADC/.cproject b/Workspace/ADC/.cproject
new file mode 100644
index 0000000..a42b8dc
--- /dev/null
+++ b/Workspace/ADC/.cproject
@@ -0,0 +1,133 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<macros>
+					<stringMacro name="PROJECT_KSDK_PATH" type="VALUE_TEXT" value="${KSDK_PATH}"/>
+				</macros>
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="ADC" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.138424891" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.671934056" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1175035411" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
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+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1925652539" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.max" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.11219160" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.67316860" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.12133355" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.hard" valueType="enumerated"/>
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+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.312855577" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
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+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.1774832244" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1114519651" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
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+							<builder buildPath="${workspace_loc:/GPIO}/Debug" id="ilg.gnuarmeclipse.managedbuild.cross.builder.2018125917" keepEnvironmentInBuildfile="false" name="Gnu Make Builder" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.2120002892" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
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+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1276352763" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.830299569" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.282145612" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.2110003551" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.1898028372" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.338169926" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1783546987" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1190073944" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.805423770" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.1404268138" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
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+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="GPIO.ilg.gnuarmeclipse.managedbuild.cross.target.elf.1672910064" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1102412416;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.13072522">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1648336251;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.1060554805">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="refreshScope"/>
+	<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+</cproject>
diff --git a/Workspace/ADC/.cwGeneratedFileSetLog b/Workspace/ADC/.cwGeneratedFileSetLog
new file mode 100644
index 0000000..da94cd8
--- /dev/null
+++ b/Workspace/ADC/.cwGeneratedFileSetLog
@@ -0,0 +1,19 @@
+Sources/main.c
+Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
+SDK/platform/devices/MK64F12/include/MK64F12_extension.h
+SDK/platform/CMSIS/Include/arm_math.h
+SDK/platform/CMSIS/Include/core_cmSimd.h
+SDK/platform/devices/MK64F12/include/MK64F12.h
+SDK/platform/CMSIS/Include/core_cm4.h
+SDK/platform/CMSIS/Include/arm_common_tables.h
+SDK/platform/devices/MK64F12/include/MK64F12_features.h
+SDK/platform/devices/fsl_device_registers.h
+SDK/platform/CMSIS/Include/arm_const_structs.h
+SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
+SDK/platform/CMSIS/Include/core_cmFunc.h
+SDK/platform/CMSIS/Include/core_cmInstr.h
+Project_Settings/Startup_Code/system_MK64F12.h
+Project_Settings/Startup_Code/startup.c
+Project_Settings/Startup_Code/startup_MK64F12.S
+Project_Settings/Startup_Code/startup.h
+Project_Settings/Startup_Code/system_MK64F12.c
\ No newline at end of file
diff --git a/Workspace/ADC/.project b/Workspace/ADC/.project
new file mode 100644
index 0000000..88e906f
--- /dev/null
+++ b/Workspace/ADC/.project
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>ADC</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<variableList>
+		<variable>
+			<name>PROJECT_KSDK_PATH</name>
+			<value>file:/C:/Freescale/KSDK_1.3.0</value>
+		</variable>
+	</variableList>
+</projectDescription>
diff --git a/Workspace/ADC/.settings/com.freescale.processorexpert.derivative.prefs b/Workspace/ADC/.settings/com.freescale.processorexpert.derivative.prefs
new file mode 100644
index 0000000..60d5016
--- /dev/null
+++ b/Workspace/ADC/.settings/com.freescale.processorexpert.derivative.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+versionGenerated/versionGenerated=1.0.0.RT7_b1550-0615
diff --git a/Workspace/ADC/.settings/language.settings.xml b/Workspace/ADC/.settings/language.settings.xml
new file mode 100644
index 0000000..3d7e4f0
--- /dev/null
+++ b/Workspace/ADC/.settings/language.settings.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1934412843581466030" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings Cross ARM" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/Workspace/ADC/Debug/ADC.elf b/Workspace/ADC/Debug/ADC.elf
new file mode 100644
index 0000000..3e62446
Binary files /dev/null and b/Workspace/ADC/Debug/ADC.elf differ
diff --git a/Workspace/ADC/Debug/ADC.map b/Workspace/ADC/Debug/ADC.map
new file mode 100644
index 0000000..296c780
--- /dev/null
+++ b/Workspace/ADC/Debug/ADC.map
@@ -0,0 +1,622 @@
+Archive member included because of file (symbol)
+
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+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (exit)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_global_impure_ptr)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (__libc_init_array)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (memset)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_exit)
+
+Discarded input sections
+
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+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.extab     0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
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+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data._impure_ptr
+                0x00000000        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .eh_frame      0x00000000        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+m_interrupts     0x00000000         0x00000400         xr
+m_flash_config   0x00000400         0x00000010         xr
+m_text           0x00000410         0x000ffbf0         xr
+m_data           0x1fff0000         0x00010000         rw
+m_data_2         0x20000000         0x00030000         rw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+LOAD ./Sources/main.o
+LOAD ./Project_Settings/Startup_Code/startup.o
+LOAD ./Project_Settings/Startup_Code/startup_MK64F12.o
+LOAD ./Project_Settings/Startup_Code/system_MK64F12.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libstdc++_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libm.a
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000400                HEAP_SIZE = DEFINED (__heap_size__)?__heap_size__:0x400
+                0x00000400                STACK_SIZE = DEFINED (__stack_size__)?__stack_size__:0x400
+                0x00000000                M_VECTOR_RAM_SIZE = DEFINED (__ram_vector_table__)?0x400:0x0
+
+.interrupts     0x00000000      0x400
+                0x00000000                __VECTOR_TABLE = .
+                0x00000000                . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector    0x00000000      0x400 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000000                __isr_vector
+                0x00000400                . = ALIGN (0x4)
+
+.flash_config   0x00000400       0x10
+                0x00000400                . = ALIGN (0x4)
+ *(.FlashConfig)
+ .FlashConfig   0x00000400       0x10 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000410                . = ALIGN (0x4)
+
+.text           0x00000410      0x458
+                0x00000410                . = ALIGN (0x4)
+ *(.text)
+ .text          0x00000410       0x54 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .text          0x00000464       0x74 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00000464                _start
+                0x00000464                _mainCRTStartup
+ .text          0x000004d8       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x000004d8                Reset_Handler
+                0x000004e8                DebugMon_Handler
+                0x000004e8                I2C0_IRQHandler
+                0x000004e8                HardFault_Handler
+                0x000004e8                SysTick_Handler
+                0x000004e8                UART3_RX_TX_IRQHandler
+                0x000004e8                PendSV_Handler
+                0x000004e8                NMI_Handler
+                0x000004e8                UART0_RX_TX_IRQHandler
+                0x000004e8                I2C1_IRQHandler
+                0x000004e8                DMA2_IRQHandler
+                0x000004e8                ENET_Error_IRQHandler
+                0x000004e8                CAN0_Tx_Warning_IRQHandler
+                0x000004e8                PIT0_IRQHandler
+                0x000004e8                CAN0_ORed_Message_buffer_IRQHandler
+                0x000004e8                CMP2_IRQHandler
+                0x000004e8                LLWU_IRQHandler
+                0x000004e8                ENET_Receive_IRQHandler
+                0x000004e8                ENET_1588_Timer_IRQHandler
+                0x000004e8                UART2_RX_TX_IRQHandler
+                0x000004e8                SWI_IRQHandler
+                0x000004e8                ADC0_IRQHandler
+                0x000004e8                UsageFault_Handler
+                0x000004e8                I2S0_Tx_IRQHandler
+                0x000004e8                CMT_IRQHandler
+                0x000004e8                UART4_RX_TX_IRQHandler
+                0x000004e8                SPI1_IRQHandler
+                0x000004e8                DefaultISR
+                0x000004e8                DMA9_IRQHandler
+                0x000004e8                DMA14_IRQHandler
+                0x000004e8                CMP1_IRQHandler
+                0x000004e8                Reserved71_IRQHandler
+                0x000004e8                PORTD_IRQHandler
+                0x000004e8                PORTB_IRQHandler
+                0x000004e8                UART4_ERR_IRQHandler
+                0x000004e8                ADC1_IRQHandler
+                0x000004e8                I2C2_IRQHandler
+                0x000004e8                PIT2_IRQHandler
+                0x000004e8                I2S0_Rx_IRQHandler
+                0x000004e8                DMA5_IRQHandler
+                0x000004e8                RTC_IRQHandler
+                0x000004e8                PDB0_IRQHandler
+                0x000004e8                CAN0_Rx_Warning_IRQHandler
+                0x000004e8                FTM1_IRQHandler
+                0x000004e8                UART5_RX_TX_IRQHandler
+                0x000004e8                UART3_ERR_IRQHandler
+                0x000004e8                PIT3_IRQHandler
+                0x000004e8                SDHC_IRQHandler
+                0x000004e8                RTC_Seconds_IRQHandler
+                0x000004e8                MCG_IRQHandler
+                0x000004e8                FTFE_IRQHandler
+                0x000004e8                UART2_ERR_IRQHandler
+                0x000004e8                DMA11_IRQHandler
+                0x000004e8                UART5_ERR_IRQHandler
+                0x000004e8                Read_Collision_IRQHandler
+                0x000004e8                DMA7_IRQHandler
+                0x000004e8                ENET_Transmit_IRQHandler
+                0x000004e8                USBDCD_IRQHandler
+                0x000004e8                USB0_IRQHandler
+                0x000004e8                SPI2_IRQHandler
+                0x000004e8                WDOG_EWM_IRQHandler
+                0x000004e8                MemManage_Handler
+                0x000004e8                SVC_Handler
+                0x000004e8                DMA13_IRQHandler
+                0x000004e8                DMA3_IRQHandler
+                0x000004e8                UART0_LON_IRQHandler
+                0x000004e8                RNG_IRQHandler
+                0x000004e8                DMA0_IRQHandler
+                0x000004e8                DMA15_IRQHandler
+                0x000004e8                DAC0_IRQHandler
+                0x000004e8                CAN0_Error_IRQHandler
+                0x000004e8                DMA4_IRQHandler
+                0x000004e8                PIT1_IRQHandler
+                0x000004e8                UART0_ERR_IRQHandler
+                0x000004e8                DMA_Error_IRQHandler
+                0x000004e8                LVD_LVW_IRQHandler
+                0x000004e8                SPI0_IRQHandler
+                0x000004e8                FTM0_IRQHandler
+                0x000004e8                PORTA_IRQHandler
+                0x000004e8                DAC1_IRQHandler
+                0x000004e8                MCM_IRQHandler
+                0x000004e8                DMA12_IRQHandler
+                0x000004e8                CAN0_Bus_Off_IRQHandler
+                0x000004e8                FTM3_IRQHandler
+                0x000004e8                PORTE_IRQHandler
+                0x000004e8                FTM2_IRQHandler
+                0x000004e8                LPTMR0_IRQHandler
+                0x000004e8                BusFault_Handler
+                0x000004e8                DMA8_IRQHandler
+                0x000004e8                DMA10_IRQHandler
+                0x000004e8                CAN0_Wake_Up_IRQHandler
+                0x000004e8                UART1_ERR_IRQHandler
+                0x000004e8                UART1_RX_TX_IRQHandler
+                0x000004e8                CMP0_IRQHandler
+                0x000004e8                PORTC_IRQHandler
+                0x000004e8                DMA6_IRQHandler
+                0x000004e8                DMA1_IRQHandler
+ *(.text*)
+ .text.main     0x000004ec       0xfc ./Sources/main.o
+                0x000004ec                main
+ .text.ADC_read16b
+                0x000005e8       0x3c ./Sources/main.o
+                0x000005e8                ADC_read16b
+ .text.uart_putchar
+                0x00000624       0x30 ./Sources/main.o
+                0x00000624                uart_putchar
+ .text.put      0x00000654       0x28 ./Sources/main.o
+                0x00000654                put
+ .text.DelayFunction
+                0x0000067c       0x24 ./Sources/main.o
+                0x0000067c                DelayFunction
+ .text.init_data_bss
+                0x000006a0       0xcc ./Project_Settings/Startup_Code/startup.o
+                0x000006a0                init_data_bss
+ .text.SystemInit
+                0x0000076c       0x3c ./Project_Settings/Startup_Code/system_MK64F12.o
+                0x0000076c                SystemInit
+ .text.exit     0x000007a8       0x28 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+                0x000007a8                exit
+ .text.__libc_init_array
+                0x000007d0       0x4c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                0x000007d0                __libc_init_array
+ .text.memset   0x0000081c       0x10 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                0x0000081c                memset
+ .text._exit    0x0000082c        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                0x0000082c                _exit
+ *(.rodata)
+ .rodata        0x00000830       0x18 ./Sources/main.o
+ *(.rodata*)
+ .rodata.str1.1
+                0x00000848        0x2 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *fill*         0x0000084a        0x2 
+ .rodata._global_impure_ptr
+                0x0000084c        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                0x0000084c                _global_impure_ptr
+ *(.glue_7)
+ .glue_7        0x00000000        0x0 linker stubs
+ *(.glue_7t)
+ .glue_7t       0x00000000        0x0 linker stubs
+ *(.eh_frame)
+ .eh_frame      0x00000850        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.init)
+ .init          0x00000850        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x00000850                _init
+ .init          0x00000854        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ *(.fini)
+ .fini          0x0000085c        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x0000085c                _fini
+ .fini          0x00000860        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000868                . = ALIGN (0x4)
+
+.vfp11_veneer   0x00000868        0x0
+ .vfp11_veneer  0x00000000        0x0 linker stubs
+
+.v4_bx          0x00000868        0x0
+ .v4_bx         0x00000000        0x0 linker stubs
+
+.iplt           0x00000868        0x0
+ .iplt          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM            0x00000868        0x8
+                0x00000868                __exidx_start = .
+ *(.ARM.exidx*)
+ .ARM.exidx     0x00000868        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00000870                __exidx_end = .
+
+.rel.dyn        0x00000870        0x0
+ .rel.iplt      0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ctors          0x00000870        0x0
+                0x00000870                __CTOR_LIST__ = .
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+                0x00000870                __CTOR_END__ = .
+
+.dtors          0x00000870        0x0
+                0x00000870                __DTOR_LIST__ = .
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+                0x00000870                __DTOR_END__ = .
+
+.preinit_array  0x00000870        0x0
+                0x00000870                PROVIDE (__preinit_array_start, .)
+ *(.preinit_array*)
+                0x00000870                PROVIDE (__preinit_array_end, .)
+
+.init_array     0x00000870        0x4
+                0x00000870                PROVIDE (__init_array_start, .)
+ *(SORT(.init_array.*))
+ *(.init_array*)
+ .init_array    0x00000870        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x00000874                PROVIDE (__init_array_end, .)
+
+.fini_array     0x00000874        0x4
+                0x00000874                PROVIDE (__fini_array_start, .)
+ *(SORT(.fini_array.*))
+ *(.fini_array*)
+ .fini_array    0x00000874        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x00000878                PROVIDE (__fini_array_end, .)
+                0x00000878                __etext = .
+                0x00000878                __DATA_ROM = .
+
+.interrupts_ram
+                0x1fff0000        0x0
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __VECTOR_RAM__ = .
+                0x1fff0000                __interrupts_ram_start__ = .
+ *(.m_interrupts_ram)
+                0x1fff0000                . = (. + M_VECTOR_RAM_SIZE)
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __interrupts_ram_end__ = .
+                0x00000000                __VECTOR_RAM = DEFINED (__ram_vector_table__)?__VECTOR_RAM__:ORIGIN (m_interrupts)
+                0x00000000                __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED (__ram_vector_table__)?(__interrupts_ram_end__ - __interrupts_ram_start__):0x0
+
+.data           0x1fff0000       0x64 load address 0x00000878
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __DATA_RAM = .
+                0x1fff0000                __data_start__ = .
+ *(.data)
+ *(.data*)
+ .data.impure_data
+                0x1fff0000       0x60 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *(.jcr*)
+ .jcr           0x1fff0060        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .jcr           0x1fff0060        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __data_end__ = .
+                0x000008dc                __DATA_END = (__DATA_ROM + (__data_end__ - __data_start__))
+                0x00100000                text_end = (ORIGIN (m_text) + 0xffbf0)
+                0x00000001                ASSERT ((__DATA_END <= text_end), region m_text overflowed with text and data)
+
+.igot.plt       0x1fff0064        0x0 load address 0x000008dc
+ .igot.plt      0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.bss            0x1fff0064       0x1c load address 0x000008dc
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __START_BSS = .
+                0x1fff0064                __bss_start__ = .
+ *(.bss)
+ .bss           0x1fff0064       0x1c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.bss*)
+ *(COMMON)
+                0x1fff0080                . = ALIGN (0x4)
+                0x1fff0080                __bss_end__ = .
+                0x1fff0080                __END_BSS = .
+
+.heap           0x20000000      0x400
+                0x20000000                . = ALIGN (0x8)
+                0x20000000                __end__ = .
+                0x20000000                PROVIDE (end, .)
+                0x20000000                __HeapBase = .
+                0x20000400                . = (. + HEAP_SIZE)
+ *fill*         0x20000000      0x400 
+                0x20000400                __HeapLimit = .
+
+.stack          0x20000400      0x400
+                0x20000400                . = ALIGN (0x8)
+                0x20000800                . = (. + STACK_SIZE)
+ *fill*         0x20000400      0x400 
+                0x20030000                __StackTop = (ORIGIN (m_data_2) + 0x30000)
+                0x2002fc00                __StackLimit = (__StackTop - STACK_SIZE)
+                0x20030000                PROVIDE (__stack, __StackTop)
+
+.ARM.attributes
+                0x00000000       0x30
+ *(.ARM.attributes)
+ .ARM.attributes
+                0x00000000       0x22 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .ARM.attributes
+                0x00000022       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .ARM.attributes
+                0x00000056       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.attributes
+                0x00000076       0x39 ./Sources/main.o
+ .ARM.attributes
+                0x000000af       0x39 ./Project_Settings/Startup_Code/startup.o
+ .ARM.attributes
+                0x000000e8       0x1f ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .ARM.attributes
+                0x00000107       0x39 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .ARM.attributes
+                0x00000140       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .ARM.attributes
+                0x00000174       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .ARM.attributes
+                0x000001a8       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .ARM.attributes
+                0x000001dc       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .ARM.attributes
+                0x00000210       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .ARM.attributes
+                0x00000244       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .ARM.attributes
+                0x00000278       0x22 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000001                ASSERT ((__StackLimit >= __HeapLimit), region m_data_2 overflowed with stack and heap)
+OUTPUT(ADC.elf elf32-littlearm)
+
+.debug_info     0x00000000     0x1207
+ .debug_info    0x00000000      0x799 ./Sources/main.o
+ .debug_info    0x00000799      0x3a7 ./Project_Settings/Startup_Code/startup.o
+ .debug_info    0x00000b40       0xb7 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_info    0x00000bf7      0x610 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_abbrev   0x00000000      0x3cf
+ .debug_abbrev  0x00000000      0x1a7 ./Sources/main.o
+ .debug_abbrev  0x000001a7       0xfa ./Project_Settings/Startup_Code/startup.o
+ .debug_abbrev  0x000002a1       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_abbrev  0x000002b5      0x11a ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_aranges  0x00000000       0xa8
+ .debug_aranges
+                0x00000000       0x40 ./Sources/main.o
+ .debug_aranges
+                0x00000040       0x20 ./Project_Settings/Startup_Code/startup.o
+ .debug_aranges
+                0x00000060       0x20 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_aranges
+                0x00000080       0x28 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_ranges   0x00000000       0x58
+ .debug_ranges  0x00000000       0x30 ./Sources/main.o
+ .debug_ranges  0x00000030       0x10 ./Project_Settings/Startup_Code/startup.o
+ .debug_ranges  0x00000040       0x18 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_macro    0x00000000    0x30d8e
+ .debug_macro   0x00000000       0x8d ./Sources/main.o
+ .debug_macro   0x0000008d      0x856 ./Sources/main.o
+ .debug_macro   0x000008e3       0x16 ./Sources/main.o
+ .debug_macro   0x000008f9       0x16 ./Sources/main.o
+ .debug_macro   0x0000090f       0x44 ./Sources/main.o
+ .debug_macro   0x00000953      0x209 ./Sources/main.o
+ .debug_macro   0x00000b5c       0x56 ./Sources/main.o
+ .debug_macro   0x00000bb2       0x3b ./Sources/main.o
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+ .debug_macro   0x00000c21       0x26 ./Sources/main.o
+ .debug_macro   0x00000c47      0xd1d ./Sources/main.o
+ .debug_macro   0x00001964       0x78 ./Sources/main.o
+ .debug_macro   0x000019dc    0x1773b ./Sources/main.o
+ .debug_macro   0x00019117      0x171 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019288       0x11 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019299       0x58 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000192f1       0x35 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019326       0xa3 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193c9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193df      0x10e ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000194ed       0x7f ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0001956c       0x52 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195be       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195d4       0x43 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019617      0x180 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019797       0x22 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197b9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197cf    0x16273 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0002fa42     0x1182 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00030bc4      0x162 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00030d26       0x68 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_line     0x00000000      0xa05
+ .debug_line    0x00000000      0x2b8 ./Sources/main.o
+ .debug_line    0x000002b8      0x358 ./Project_Settings/Startup_Code/startup.o
+ .debug_line    0x00000610       0x6a ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_line    0x0000067a      0x38b ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_str      0x00000000   0x19cbbd
+ .debug_str     0x00000000    0x8fc12 ./Sources/main.o
+                              0x8fd9a (size before relaxing)
+ .debug_str     0x0008fc12   0x10cec1 ./Project_Settings/Startup_Code/startup.o
+                             0x19caa5 (size before relaxing)
+ .debug_str     0x0019cad3       0xea ./Project_Settings/Startup_Code/system_MK64F12.o
+                             0x19cb60 (size before relaxing)
+
+.comment        0x00000000       0x70
+ .comment       0x00000000       0x70 ./Sources/main.o
+                                 0x71 (size before relaxing)
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/startup.o
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_frame    0x00000000      0x1a4
+ .debug_frame   0x00000000       0xa0 ./Sources/main.o
+ .debug_frame   0x000000a0       0x2c ./Project_Settings/Startup_Code/startup.o
+ .debug_frame   0x000000cc       0x44 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_frame   0x00000110       0x28 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .debug_frame   0x00000138       0x2c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .debug_frame   0x00000164       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .debug_frame   0x00000184       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
diff --git a/Workspace/ADC/Debug/GPIO.map b/Workspace/ADC/Debug/GPIO.map
new file mode 100644
index 0000000..4bbb008
--- /dev/null
+++ b/Workspace/ADC/Debug/GPIO.map
@@ -0,0 +1,622 @@
+Archive member included because of file (symbol)
+
+c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (exit)
+c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_global_impure_ptr)
+c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (__libc_init_array)
+c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (memset)
+c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_exit)
+
+Discarded input sections
+
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+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .data          0x00000000        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.extab     0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .group         0x00000000        0x8 ./Sources/main.o
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+ .debug_macro   0x00000000       0x52 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x16 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x43 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000      0x180 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x22 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x16 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000    0x16273 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000     0x1182 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data._impure_ptr
+                0x00000000        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .eh_frame      0x00000000        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+m_interrupts     0x00000000         0x00000400         xr
+m_flash_config   0x00000400         0x00000010         xr
+m_text           0x00000410         0x000ffbf0         xr
+m_data           0x1fff0000         0x00010000         rw
+m_data_2         0x20000000         0x00030000         rw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+LOAD ./Sources/main.o
+LOAD ./Project_Settings/Startup_Code/startup.o
+LOAD ./Project_Settings/Startup_Code/startup_MK64F12.o
+LOAD ./Project_Settings/Startup_Code/system_MK64F12.o
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libstdc++_s.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libm.a
+START GROUP
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000400                HEAP_SIZE = DEFINED (__heap_size__)?__heap_size__:0x400
+                0x00000400                STACK_SIZE = DEFINED (__stack_size__)?__stack_size__:0x400
+                0x00000000                M_VECTOR_RAM_SIZE = DEFINED (__ram_vector_table__)?0x400:0x0
+
+.interrupts     0x00000000      0x400
+                0x00000000                __VECTOR_TABLE = .
+                0x00000000                . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector    0x00000000      0x400 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000000                __isr_vector
+                0x00000400                . = ALIGN (0x4)
+
+.flash_config   0x00000400       0x10
+                0x00000400                . = ALIGN (0x4)
+ *(.FlashConfig)
+ .FlashConfig   0x00000400       0x10 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000410                . = ALIGN (0x4)
+
+.text           0x00000410      0x458
+                0x00000410                . = ALIGN (0x4)
+ *(.text)
+ .text          0x00000410       0x54 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .text          0x00000464       0x74 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00000464                _start
+                0x00000464                _mainCRTStartup
+ .text          0x000004d8       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x000004d8                Reset_Handler
+                0x000004e8                DebugMon_Handler
+                0x000004e8                I2C0_IRQHandler
+                0x000004e8                HardFault_Handler
+                0x000004e8                SysTick_Handler
+                0x000004e8                UART3_RX_TX_IRQHandler
+                0x000004e8                PendSV_Handler
+                0x000004e8                NMI_Handler
+                0x000004e8                UART0_RX_TX_IRQHandler
+                0x000004e8                I2C1_IRQHandler
+                0x000004e8                DMA2_IRQHandler
+                0x000004e8                ENET_Error_IRQHandler
+                0x000004e8                CAN0_Tx_Warning_IRQHandler
+                0x000004e8                PIT0_IRQHandler
+                0x000004e8                CAN0_ORed_Message_buffer_IRQHandler
+                0x000004e8                CMP2_IRQHandler
+                0x000004e8                LLWU_IRQHandler
+                0x000004e8                ENET_Receive_IRQHandler
+                0x000004e8                ENET_1588_Timer_IRQHandler
+                0x000004e8                UART2_RX_TX_IRQHandler
+                0x000004e8                SWI_IRQHandler
+                0x000004e8                ADC0_IRQHandler
+                0x000004e8                UsageFault_Handler
+                0x000004e8                I2S0_Tx_IRQHandler
+                0x000004e8                CMT_IRQHandler
+                0x000004e8                UART4_RX_TX_IRQHandler
+                0x000004e8                SPI1_IRQHandler
+                0x000004e8                DefaultISR
+                0x000004e8                DMA9_IRQHandler
+                0x000004e8                DMA14_IRQHandler
+                0x000004e8                CMP1_IRQHandler
+                0x000004e8                Reserved71_IRQHandler
+                0x000004e8                PORTD_IRQHandler
+                0x000004e8                PORTB_IRQHandler
+                0x000004e8                UART4_ERR_IRQHandler
+                0x000004e8                ADC1_IRQHandler
+                0x000004e8                I2C2_IRQHandler
+                0x000004e8                PIT2_IRQHandler
+                0x000004e8                I2S0_Rx_IRQHandler
+                0x000004e8                DMA5_IRQHandler
+                0x000004e8                RTC_IRQHandler
+                0x000004e8                PDB0_IRQHandler
+                0x000004e8                CAN0_Rx_Warning_IRQHandler
+                0x000004e8                FTM1_IRQHandler
+                0x000004e8                UART5_RX_TX_IRQHandler
+                0x000004e8                UART3_ERR_IRQHandler
+                0x000004e8                PIT3_IRQHandler
+                0x000004e8                SDHC_IRQHandler
+                0x000004e8                RTC_Seconds_IRQHandler
+                0x000004e8                MCG_IRQHandler
+                0x000004e8                FTFE_IRQHandler
+                0x000004e8                UART2_ERR_IRQHandler
+                0x000004e8                DMA11_IRQHandler
+                0x000004e8                UART5_ERR_IRQHandler
+                0x000004e8                Read_Collision_IRQHandler
+                0x000004e8                DMA7_IRQHandler
+                0x000004e8                ENET_Transmit_IRQHandler
+                0x000004e8                USBDCD_IRQHandler
+                0x000004e8                USB0_IRQHandler
+                0x000004e8                SPI2_IRQHandler
+                0x000004e8                WDOG_EWM_IRQHandler
+                0x000004e8                MemManage_Handler
+                0x000004e8                SVC_Handler
+                0x000004e8                DMA13_IRQHandler
+                0x000004e8                DMA3_IRQHandler
+                0x000004e8                UART0_LON_IRQHandler
+                0x000004e8                RNG_IRQHandler
+                0x000004e8                DMA0_IRQHandler
+                0x000004e8                DMA15_IRQHandler
+                0x000004e8                DAC0_IRQHandler
+                0x000004e8                CAN0_Error_IRQHandler
+                0x000004e8                DMA4_IRQHandler
+                0x000004e8                PIT1_IRQHandler
+                0x000004e8                UART0_ERR_IRQHandler
+                0x000004e8                DMA_Error_IRQHandler
+                0x000004e8                LVD_LVW_IRQHandler
+                0x000004e8                SPI0_IRQHandler
+                0x000004e8                FTM0_IRQHandler
+                0x000004e8                PORTA_IRQHandler
+                0x000004e8                DAC1_IRQHandler
+                0x000004e8                MCM_IRQHandler
+                0x000004e8                DMA12_IRQHandler
+                0x000004e8                CAN0_Bus_Off_IRQHandler
+                0x000004e8                FTM3_IRQHandler
+                0x000004e8                PORTE_IRQHandler
+                0x000004e8                FTM2_IRQHandler
+                0x000004e8                LPTMR0_IRQHandler
+                0x000004e8                BusFault_Handler
+                0x000004e8                DMA8_IRQHandler
+                0x000004e8                DMA10_IRQHandler
+                0x000004e8                CAN0_Wake_Up_IRQHandler
+                0x000004e8                UART1_ERR_IRQHandler
+                0x000004e8                UART1_RX_TX_IRQHandler
+                0x000004e8                CMP0_IRQHandler
+                0x000004e8                PORTC_IRQHandler
+                0x000004e8                DMA6_IRQHandler
+                0x000004e8                DMA1_IRQHandler
+ *(.text*)
+ .text.main     0x000004ec       0xfc ./Sources/main.o
+                0x000004ec                main
+ .text.ADC_read16b
+                0x000005e8       0x3c ./Sources/main.o
+                0x000005e8                ADC_read16b
+ .text.uart_putchar
+                0x00000624       0x30 ./Sources/main.o
+                0x00000624                uart_putchar
+ .text.put      0x00000654       0x28 ./Sources/main.o
+                0x00000654                put
+ .text.DelayFunction
+                0x0000067c       0x24 ./Sources/main.o
+                0x0000067c                DelayFunction
+ .text.init_data_bss
+                0x000006a0       0xcc ./Project_Settings/Startup_Code/startup.o
+                0x000006a0                init_data_bss
+ .text.SystemInit
+                0x0000076c       0x3c ./Project_Settings/Startup_Code/system_MK64F12.o
+                0x0000076c                SystemInit
+ .text.exit     0x000007a8       0x28 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+                0x000007a8                exit
+ .text.__libc_init_array
+                0x000007d0       0x4c c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                0x000007d0                __libc_init_array
+ .text.memset   0x0000081c       0x10 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                0x0000081c                memset
+ .text._exit    0x0000082c        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                0x0000082c                _exit
+ *(.rodata)
+ .rodata        0x00000830       0x18 ./Sources/main.o
+ *(.rodata*)
+ .rodata.str1.1
+                0x00000848        0x2 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *fill*         0x0000084a        0x2 
+ .rodata._global_impure_ptr
+                0x0000084c        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                0x0000084c                _global_impure_ptr
+ *(.glue_7)
+ .glue_7        0x00000000        0x0 linker stubs
+ *(.glue_7t)
+ .glue_7t       0x00000000        0x0 linker stubs
+ *(.eh_frame)
+ .eh_frame      0x00000850        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.init)
+ .init          0x00000850        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x00000850                _init
+ .init          0x00000854        0x8 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ *(.fini)
+ .fini          0x0000085c        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x0000085c                _fini
+ .fini          0x00000860        0x8 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000868                . = ALIGN (0x4)
+
+.vfp11_veneer   0x00000868        0x0
+ .vfp11_veneer  0x00000000        0x0 linker stubs
+
+.v4_bx          0x00000868        0x0
+ .v4_bx         0x00000000        0x0 linker stubs
+
+.iplt           0x00000868        0x0
+ .iplt          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM            0x00000868        0x8
+                0x00000868                __exidx_start = .
+ *(.ARM.exidx*)
+ .ARM.exidx     0x00000868        0x8 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00000870                __exidx_end = .
+
+.rel.dyn        0x00000870        0x0
+ .rel.iplt      0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ctors          0x00000870        0x0
+                0x00000870                __CTOR_LIST__ = .
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+                0x00000870                __CTOR_END__ = .
+
+.dtors          0x00000870        0x0
+                0x00000870                __DTOR_LIST__ = .
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+                0x00000870                __DTOR_END__ = .
+
+.preinit_array  0x00000870        0x0
+                0x00000870                PROVIDE (__preinit_array_start, .)
+ *(.preinit_array*)
+                0x00000870                PROVIDE (__preinit_array_end, .)
+
+.init_array     0x00000870        0x4
+                0x00000870                PROVIDE (__init_array_start, .)
+ *(SORT(.init_array.*))
+ *(.init_array*)
+ .init_array    0x00000870        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x00000874                PROVIDE (__init_array_end, .)
+
+.fini_array     0x00000874        0x4
+                0x00000874                PROVIDE (__fini_array_start, .)
+ *(SORT(.fini_array.*))
+ *(.fini_array*)
+ .fini_array    0x00000874        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x00000878                PROVIDE (__fini_array_end, .)
+                0x00000878                __etext = .
+                0x00000878                __DATA_ROM = .
+
+.interrupts_ram
+                0x1fff0000        0x0
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __VECTOR_RAM__ = .
+                0x1fff0000                __interrupts_ram_start__ = .
+ *(.m_interrupts_ram)
+                0x1fff0000                . = (. + M_VECTOR_RAM_SIZE)
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __interrupts_ram_end__ = .
+                0x00000000                __VECTOR_RAM = DEFINED (__ram_vector_table__)?__VECTOR_RAM__:ORIGIN (m_interrupts)
+                0x00000000                __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED (__ram_vector_table__)?(__interrupts_ram_end__ - __interrupts_ram_start__):0x0
+
+.data           0x1fff0000       0x64 load address 0x00000878
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __DATA_RAM = .
+                0x1fff0000                __data_start__ = .
+ *(.data)
+ *(.data*)
+ .data.impure_data
+                0x1fff0000       0x60 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *(.jcr*)
+ .jcr           0x1fff0060        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .jcr           0x1fff0060        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __data_end__ = .
+                0x000008dc                __DATA_END = (__DATA_ROM + (__data_end__ - __data_start__))
+                0x00100000                text_end = (ORIGIN (m_text) + 0xffbf0)
+                0x00000001                ASSERT ((__DATA_END <= text_end), region m_text overflowed with text and data)
+
+.igot.plt       0x1fff0064        0x0 load address 0x000008dc
+ .igot.plt      0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.bss            0x1fff0064       0x1c load address 0x000008dc
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __START_BSS = .
+                0x1fff0064                __bss_start__ = .
+ *(.bss)
+ .bss           0x1fff0064       0x1c c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.bss*)
+ *(COMMON)
+                0x1fff0080                . = ALIGN (0x4)
+                0x1fff0080                __bss_end__ = .
+                0x1fff0080                __END_BSS = .
+
+.heap           0x20000000      0x400
+                0x20000000                . = ALIGN (0x8)
+                0x20000000                __end__ = .
+                0x20000000                PROVIDE (end, .)
+                0x20000000                __HeapBase = .
+                0x20000400                . = (. + HEAP_SIZE)
+ *fill*         0x20000000      0x400 
+                0x20000400                __HeapLimit = .
+
+.stack          0x20000400      0x400
+                0x20000400                . = ALIGN (0x8)
+                0x20000800                . = (. + STACK_SIZE)
+ *fill*         0x20000400      0x400 
+                0x20030000                __StackTop = (ORIGIN (m_data_2) + 0x30000)
+                0x2002fc00                __StackLimit = (__StackTop - STACK_SIZE)
+                0x20030000                PROVIDE (__stack, __StackTop)
+
+.ARM.attributes
+                0x00000000       0x30
+ *(.ARM.attributes)
+ .ARM.attributes
+                0x00000000       0x22 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .ARM.attributes
+                0x00000022       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .ARM.attributes
+                0x00000056       0x20 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.attributes
+                0x00000076       0x39 ./Sources/main.o
+ .ARM.attributes
+                0x000000af       0x39 ./Project_Settings/Startup_Code/startup.o
+ .ARM.attributes
+                0x000000e8       0x1f ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .ARM.attributes
+                0x00000107       0x39 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .ARM.attributes
+                0x00000140       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .ARM.attributes
+                0x00000174       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .ARM.attributes
+                0x000001a8       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .ARM.attributes
+                0x000001dc       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .ARM.attributes
+                0x00000210       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .ARM.attributes
+                0x00000244       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .ARM.attributes
+                0x00000278       0x22 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000001                ASSERT ((__StackLimit >= __HeapLimit), region m_data_2 overflowed with stack and heap)
+OUTPUT(GPIO.elf elf32-littlearm)
+
+.debug_info     0x00000000     0x11e3
+ .debug_info    0x00000000      0x799 ./Sources/main.o
+ .debug_info    0x00000799      0x3a7 ./Project_Settings/Startup_Code/startup.o
+ .debug_info    0x00000b40       0x93 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_info    0x00000bd3      0x610 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_abbrev   0x00000000      0x3cf
+ .debug_abbrev  0x00000000      0x1a7 ./Sources/main.o
+ .debug_abbrev  0x000001a7       0xfa ./Project_Settings/Startup_Code/startup.o
+ .debug_abbrev  0x000002a1       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_abbrev  0x000002b5      0x11a ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_aranges  0x00000000       0xa8
+ .debug_aranges
+                0x00000000       0x40 ./Sources/main.o
+ .debug_aranges
+                0x00000040       0x20 ./Project_Settings/Startup_Code/startup.o
+ .debug_aranges
+                0x00000060       0x20 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_aranges
+                0x00000080       0x28 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_ranges   0x00000000       0x58
+ .debug_ranges  0x00000000       0x30 ./Sources/main.o
+ .debug_ranges  0x00000030       0x10 ./Project_Settings/Startup_Code/startup.o
+ .debug_ranges  0x00000040       0x18 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_macro    0x00000000    0x30d8e
+ .debug_macro   0x00000000       0x8d ./Sources/main.o
+ .debug_macro   0x0000008d      0x856 ./Sources/main.o
+ .debug_macro   0x000008e3       0x16 ./Sources/main.o
+ .debug_macro   0x000008f9       0x16 ./Sources/main.o
+ .debug_macro   0x0000090f       0x44 ./Sources/main.o
+ .debug_macro   0x00000953      0x209 ./Sources/main.o
+ .debug_macro   0x00000b5c       0x56 ./Sources/main.o
+ .debug_macro   0x00000bb2       0x3b ./Sources/main.o
+ .debug_macro   0x00000bed       0x34 ./Sources/main.o
+ .debug_macro   0x00000c21       0x26 ./Sources/main.o
+ .debug_macro   0x00000c47      0xd1d ./Sources/main.o
+ .debug_macro   0x00001964       0x78 ./Sources/main.o
+ .debug_macro   0x000019dc    0x1773b ./Sources/main.o
+ .debug_macro   0x00019117      0x171 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019288       0x11 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019299       0x58 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000192f1       0x35 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019326       0xa3 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193c9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193df      0x10e ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000194ed       0x7f ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0001956c       0x52 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195be       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195d4       0x43 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019617      0x180 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019797       0x22 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197b9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197cf    0x16273 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0002fa42     0x1182 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00030bc4      0x162 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00030d26       0x68 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_line     0x00000000      0xa29
+ .debug_line    0x00000000      0x2c4 ./Sources/main.o
+ .debug_line    0x000002c4      0x364 ./Project_Settings/Startup_Code/startup.o
+ .debug_line    0x00000628       0x6a ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_line    0x00000692      0x397 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_str      0x00000000   0x19cbd0
+ .debug_str     0x00000000    0x8fbed ./Sources/main.o
+                              0x8fd75 (size before relaxing)
+ .debug_str     0x0008fbed   0x10cef9 ./Project_Settings/Startup_Code/startup.o
+                             0x19ca81 (size before relaxing)
+ .debug_str     0x0019cae6       0xea ./Project_Settings/Startup_Code/system_MK64F12.o
+                             0x19cb3c (size before relaxing)
+
+.comment        0x00000000       0x70
+ .comment       0x00000000       0x70 ./Sources/main.o
+                                 0x71 (size before relaxing)
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/startup.o
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_frame    0x00000000      0x1a4
+ .debug_frame   0x00000000       0xa0 ./Sources/main.o
+ .debug_frame   0x000000a0       0x2c ./Project_Settings/Startup_Code/startup.o
+ .debug_frame   0x000000cc       0x44 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_frame   0x00000110       0x28 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .debug_frame   0x00000138       0x2c c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .debug_frame   0x00000164       0x20 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .debug_frame   0x00000184       0x20 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
diff --git a/Workspace/ADC/Debug/Project_Settings/Startup_Code/startup.d b/Workspace/ADC/Debug/Project_Settings/Startup_Code/startup.d
new file mode 100644
index 0000000..09df623
--- /dev/null
+++ b/Workspace/ADC/Debug/Project_Settings/Startup_Code/startup.d
@@ -0,0 +1,38 @@
+Project_Settings/Startup_Code/startup.o: \
+ ../Project_Settings/Startup_Code/startup.c \
+ ../Project_Settings/Startup_Code/startup.h \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h
+
+../Project_Settings/Startup_Code/startup.h:
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
diff --git a/Workspace/ADC/Debug/Project_Settings/Startup_Code/startup.o b/Workspace/ADC/Debug/Project_Settings/Startup_Code/startup.o
new file mode 100644
index 0000000..6fdf251
Binary files /dev/null and b/Workspace/ADC/Debug/Project_Settings/Startup_Code/startup.o differ
diff --git a/Workspace/ADC/Debug/Project_Settings/Startup_Code/startup_MK64F12.d b/Workspace/ADC/Debug/Project_Settings/Startup_Code/startup_MK64F12.d
new file mode 100644
index 0000000..15e90f1
--- /dev/null
+++ b/Workspace/ADC/Debug/Project_Settings/Startup_Code/startup_MK64F12.d
@@ -0,0 +1,2 @@
+Project_Settings/Startup_Code/startup_MK64F12.o: \
+ ../Project_Settings/Startup_Code/startup_MK64F12.S
diff --git a/Workspace/ADC/Debug/Project_Settings/Startup_Code/startup_MK64F12.o b/Workspace/ADC/Debug/Project_Settings/Startup_Code/startup_MK64F12.o
new file mode 100644
index 0000000..ff2a602
Binary files /dev/null and b/Workspace/ADC/Debug/Project_Settings/Startup_Code/startup_MK64F12.o differ
diff --git a/Workspace/ADC/Debug/Project_Settings/Startup_Code/subdir.mk b/Workspace/ADC/Debug/Project_Settings/Startup_Code/subdir.mk
new file mode 100644
index 0000000..40dfadd
--- /dev/null
+++ b/Workspace/ADC/Debug/Project_Settings/Startup_Code/subdir.mk
@@ -0,0 +1,41 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Project_Settings/Startup_Code/startup.c \
+../Project_Settings/Startup_Code/system_MK64F12.c 
+
+S_UPPER_SRCS += \
+../Project_Settings/Startup_Code/startup_MK64F12.S 
+
+OBJS += \
+./Project_Settings/Startup_Code/startup.o \
+./Project_Settings/Startup_Code/startup_MK64F12.o \
+./Project_Settings/Startup_Code/system_MK64F12.o 
+
+C_DEPS += \
+./Project_Settings/Startup_Code/startup.d \
+./Project_Settings/Startup_Code/system_MK64F12.d 
+
+S_UPPER_DEPS += \
+./Project_Settings/Startup_Code/startup_MK64F12.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Project_Settings/Startup_Code/%.o: ../Project_Settings/Startup_Code/%.c
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM C Compiler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -I"C:\Freescale\KSDK_1.1.0/platform/devices/MK64F12/startup" -I"C:\Freescale\KSDK_1.1.0/platform/devices" -I"C:\Freescale\KSDK_1.1.0/platform/devices/MK64F12/startup/gcc" -std=c99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+Project_Settings/Startup_Code/%.o: ../Project_Settings/Startup_Code/%.S
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM GNU Assembler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+
diff --git a/Workspace/ADC/Debug/Project_Settings/Startup_Code/system_MK64F12.d b/Workspace/ADC/Debug/Project_Settings/Startup_Code/system_MK64F12.d
new file mode 100644
index 0000000..d0e2961
--- /dev/null
+++ b/Workspace/ADC/Debug/Project_Settings/Startup_Code/system_MK64F12.d
@@ -0,0 +1,35 @@
+Project_Settings/Startup_Code/system_MK64F12.o: \
+ ../Project_Settings/Startup_Code/system_MK64F12.c \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
diff --git a/Workspace/ADC/Debug/Project_Settings/Startup_Code/system_MK64F12.o b/Workspace/ADC/Debug/Project_Settings/Startup_Code/system_MK64F12.o
new file mode 100644
index 0000000..b36e2f0
Binary files /dev/null and b/Workspace/ADC/Debug/Project_Settings/Startup_Code/system_MK64F12.o differ
diff --git a/Workspace/ADC/Debug/Sources/main.d b/Workspace/ADC/Debug/Sources/main.d
new file mode 100644
index 0000000..6984a8b
--- /dev/null
+++ b/Workspace/ADC/Debug/Sources/main.d
@@ -0,0 +1,19 @@
+Sources/main.o: ../Sources/main.c \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
diff --git a/Workspace/ADC/Debug/Sources/main.o b/Workspace/ADC/Debug/Sources/main.o
new file mode 100644
index 0000000..05d596d
Binary files /dev/null and b/Workspace/ADC/Debug/Sources/main.o differ
diff --git a/Workspace/ADC/Debug/Sources/subdir.mk b/Workspace/ADC/Debug/Sources/subdir.mk
new file mode 100644
index 0000000..a3f42b3
--- /dev/null
+++ b/Workspace/ADC/Debug/Sources/subdir.mk
@@ -0,0 +1,24 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Sources/main.c 
+
+OBJS += \
+./Sources/main.o 
+
+C_DEPS += \
+./Sources/main.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Sources/%.o: ../Sources/%.c
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM C Compiler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -I"C:\Freescale\KSDK_1.1.0/platform/devices/MK64F12/startup" -I"C:\Freescale\KSDK_1.1.0/platform/devices" -I"C:\Freescale\KSDK_1.1.0/platform/devices/MK64F12/startup/gcc" -std=c99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+
diff --git a/Workspace/ADC/Debug/makefile b/Workspace/ADC/Debug/makefile
new file mode 100644
index 0000000..fcdc087
--- /dev/null
+++ b/Workspace/ADC/Debug/makefile
@@ -0,0 +1,77 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include Sources/subdir.mk
+-include Project_Settings/Startup_Code/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C++_DEPS)),)
+-include $(C++_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+ifneq ($(strip $(ASM_DEPS)),)
+-include $(ASM_DEPS)
+endif
+ifneq ($(strip $(CC_DEPS)),)
+-include $(CC_DEPS)
+endif
+ifneq ($(strip $(CPP_DEPS)),)
+-include $(CPP_DEPS)
+endif
+ifneq ($(strip $(CXX_DEPS)),)
+-include $(CXX_DEPS)
+endif
+ifneq ($(strip $(C_UPPER_DEPS)),)
+-include $(C_UPPER_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables 
+SECONDARY_SIZE += \
+ADC.siz \
+
+
+# All Target
+all: ADC.elf secondary-outputs
+
+# Tool invocations
+ADC.elf: $(OBJS) $(USER_OBJS)
+	@echo 'Building target: $@'
+	@echo 'Invoking: Cross ARM C++ Linker'
+	arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -T "MK64FN1M0xxx12_flash.ld" -Xlinker --gc-sections -L"C:/Users/Akash/Desktop/Lab 4 595/ECE595_Lab4_Updated_Akash_Dewant/Workspace_Akash/ADC/Project_Settings/Linker_Files" -Wl,-Map,"ADC.map" -specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs -o "ADC.elf" $(OBJS) $(USER_OBJS) $(LIBS)
+	@echo 'Finished building target: $@'
+	@echo ' '
+
+ADC.siz: ADC.elf
+	@echo 'Invoking: Cross ARM GNU Print Size'
+	arm-none-eabi-size --format=berkeley "ADC.elf"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+# Other Targets
+clean:
+	-$(RM) $(SECONDARY_SIZE)$(C++_DEPS)$(OBJS)$(C_DEPS)$(ASM_DEPS)$(CC_DEPS)$(CPP_DEPS)$(CXX_DEPS)$(C_UPPER_DEPS)$(S_UPPER_DEPS) ADC.elf
+	-@echo ' '
+
+secondary-outputs: $(SECONDARY_SIZE)
+
+.PHONY: all clean dependents
+.SECONDARY:
+
+-include ../makefile.targets
diff --git a/Workspace/ADC/Debug/objects.mk b/Workspace/ADC/Debug/objects.mk
new file mode 100644
index 0000000..742c2da
--- /dev/null
+++ b/Workspace/ADC/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/Workspace/ADC/Debug/sources.mk b/Workspace/ADC/Debug/sources.mk
new file mode 100644
index 0000000..80f8a41
--- /dev/null
+++ b/Workspace/ADC/Debug/sources.mk
@@ -0,0 +1,31 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ELF_SRCS := 
+O_SRCS := 
+CPP_SRCS := 
+C_UPPER_SRCS := 
+C_SRCS := 
+S_UPPER_SRCS := 
+OBJ_SRCS := 
+ASM_SRCS := 
+CXX_SRCS := 
+C++_SRCS := 
+CC_SRCS := 
+SECONDARY_SIZE := 
+C++_DEPS := 
+OBJS := 
+C_DEPS := 
+ASM_DEPS := 
+CC_DEPS := 
+CPP_DEPS := 
+CXX_DEPS := 
+C_UPPER_DEPS := 
+S_UPPER_DEPS := 
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Sources \
+Project_Settings/Startup_Code \
+
diff --git a/Workspace/ADC/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch b/Workspace/ADC/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch
new file mode 100644
index 0000000..cae21a4
--- /dev/null
+++ b/Workspace/ADC/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doConnectToRunning" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f kinetis.cfg"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/GPIO.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="GPIO"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/GPIO"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/ADC/Project_Settings/Debugger/GPIO_Debug_Segger.launch b/Workspace/ADC/Project_Settings/Debugger/GPIO_Debug_Segger.launch
new file mode 100644
index 0000000..68923d5
--- /dev/null
+++ b/Workspace/ADC/Project_Settings/Debugger/GPIO_Debug_Segger.launch
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.jlink.launchConfigurationType">
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="MK64FN1M0xxx12"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="1000"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM J-Link"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/GPIO.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="GPIO"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/GPIO"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/ADC/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld b/Workspace/ADC/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
new file mode 100644
index 0000000..506082b
--- /dev/null
+++ b/Workspace/ADC/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
@@ -0,0 +1,245 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150624
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
+  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0
+  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
+  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+  } > m_data_2
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data_2
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
+}
+
diff --git a/Workspace/ADC/Project_Settings/Startup_Code/startup.c b/Workspace/ADC/Project_Settings/Startup_Code/startup.c
new file mode 100644
index 0000000..b89e7fc
--- /dev/null
+++ b/Workspace/ADC/Project_Settings/Startup_Code/startup.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "startup.h"
+#include "fsl_device_registers.h"
+
+#if (defined(__ICCARM__))
+    #pragma section = ".data"
+    #pragma section = ".data_init"
+    #pragma section = ".bss"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : init_data_bss
+ * Description   : Make necessary initializations for RAM.
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ *
+ * Tool Chians:
+ *   __GNUC__   : GCC
+ *   __CC_ARM   : KEIL
+ *   __ICCARM__ : IAR
+ *
+ *END**************************************************************************/
+void init_data_bss(void)
+{
+    uint32_t n; 
+    
+    /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+    #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base  
+    #define __VECTOR_RAM Image$$VECTOR_RAM$$Base  
+    #define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];  
+    extern uint32_t __VECTOR_RAM[];  
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif
+
+    if (__VECTOR_RAM != __VECTOR_TABLE)
+    {   
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+    else
+    {
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_TABLE;
+    }
+
+#if !defined(__CC_ARM) && !defined(__ICCARM__)
+    
+    /* Declare pointers for various data sections. These pointers
+     * are initialized using values pulled in from the linker file */
+    uint8_t * data_ram, * data_rom, * data_rom_end;
+    uint8_t * bss_start, * bss_end;
+
+    /* Get the addresses for the .data section (initialized data section) */
+#if defined(__GNUC__)
+    extern uint32_t __DATA_ROM[];
+    extern uint32_t __DATA_RAM[];
+    extern char __DATA_END[];
+    data_ram = (uint8_t *)__DATA_RAM;
+    data_rom = (uint8_t *)__DATA_ROM;
+    data_rom_end  = (uint8_t *)__DATA_END;
+    n = data_rom_end - data_rom;
+#endif
+
+    /* Copy initialized data from ROM to RAM */
+    while (n--)
+    {
+        *data_ram++ = *data_rom++;
+    }   
+    
+    /* Get the addresses for the .bss section (zero-initialized data) */
+#if defined(__GNUC__)
+    extern char __START_BSS[];
+    extern char __END_BSS[];
+    bss_start = (uint8_t *)__START_BSS;
+    bss_end = (uint8_t *)__END_BSS;
+#endif
+		
+    /* Clear the zero-initialized data section */
+    n = bss_end - bss_start;
+    while(n--)
+    {
+        *bss_start++ = 0;
+    }
+#endif /* !__CC_ARM && !__ICCARM__*/
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/Workspace/ADC/Project_Settings/Startup_Code/startup.h b/Workspace/ADC/Project_Settings/Startup_Code/startup.h
new file mode 100644
index 0000000..17ad55f
--- /dev/null
+++ b/Workspace/ADC/Project_Settings/Startup_Code/startup.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _STARTUP_H_
+#define _STARTUP_H_
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Make necessary initializations for RAM.
+ *
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ */
+void init_data_bss(void);
+
+#endif /* _STARTUP_H_*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/Workspace/ADC/Project_Settings/Startup_Code/startup_MK64F12.S b/Workspace/ADC/Project_Settings/Startup_Code/startup_MK64F12.S
new file mode 100644
index 0000000..aebe2e6
--- /dev/null
+++ b/Workspace/ADC/Project_Settings/Startup_Code/startup_MK64F12.S
@@ -0,0 +1,457 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK64F12.s                                                           */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK64F12                                                                     */
+/*  @version: 2.8                                                                         */
+/*  @date:    2015-2-19                                                                   */
+/*  @build:   b150225                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_IRQHandler                                 /* DMA Channel 0 Transfer Complete*/
+    .long   DMA1_IRQHandler                                 /* DMA Channel 1 Transfer Complete*/
+    .long   DMA2_IRQHandler                                 /* DMA Channel 2 Transfer Complete*/
+    .long   DMA3_IRQHandler                                 /* DMA Channel 3 Transfer Complete*/
+    .long   DMA4_IRQHandler                                 /* DMA Channel 4 Transfer Complete*/
+    .long   DMA5_IRQHandler                                 /* DMA Channel 5 Transfer Complete*/
+    .long   DMA6_IRQHandler                                 /* DMA Channel 6 Transfer Complete*/
+    .long   DMA7_IRQHandler                                 /* DMA Channel 7 Transfer Complete*/
+    .long   DMA8_IRQHandler                                 /* DMA Channel 8 Transfer Complete*/
+    .long   DMA9_IRQHandler                                 /* DMA Channel 9 Transfer Complete*/
+    .long   DMA10_IRQHandler                                /* DMA Channel 10 Transfer Complete*/
+    .long   DMA11_IRQHandler                                /* DMA Channel 11 Transfer Complete*/
+    .long   DMA12_IRQHandler                                /* DMA Channel 12 Transfer Complete*/
+    .long   DMA13_IRQHandler                                /* DMA Channel 13 Transfer Complete*/
+    .long   DMA14_IRQHandler                                /* DMA Channel 14 Transfer Complete*/
+    .long   DMA15_IRQHandler                                /* DMA Channel 15 Transfer Complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA Error Interrupt*/
+    .long   MCM_IRQHandler                                  /* Normal Interrupt*/
+    .long   FTFE_IRQHandler                                 /* FTFE Command complete interrupt*/
+    .long   Read_Collision_IRQHandler                       /* Read Collision Interrupt*/
+    .long   LVD_LVW_IRQHandler                              /* Low Voltage Detect, Low Voltage Warning*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup Unit*/
+    .long   WDOG_EWM_IRQHandler                             /* WDOG Interrupt*/
+    .long   RNG_IRQHandler                                  /* RNG Interrupt*/
+    .long   I2C0_IRQHandler                                 /* I2C0 interrupt*/
+    .long   I2C1_IRQHandler                                 /* I2C1 interrupt*/
+    .long   SPI0_IRQHandler                                 /* SPI0 Interrupt*/
+    .long   SPI1_IRQHandler                                 /* SPI1 Interrupt*/
+    .long   I2S0_Tx_IRQHandler                              /* I2S0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* I2S0 receive interrupt*/
+    .long   UART0_LON_IRQHandler                            /* UART0 LON interrupt*/
+    .long   UART0_RX_TX_IRQHandler                          /* UART0 Receive/Transmit interrupt*/
+    .long   UART0_ERR_IRQHandler                            /* UART0 Error interrupt*/
+    .long   UART1_RX_TX_IRQHandler                          /* UART1 Receive/Transmit interrupt*/
+    .long   UART1_ERR_IRQHandler                            /* UART1 Error interrupt*/
+    .long   UART2_RX_TX_IRQHandler                          /* UART2 Receive/Transmit interrupt*/
+    .long   UART2_ERR_IRQHandler                            /* UART2 Error interrupt*/
+    .long   UART3_RX_TX_IRQHandler                          /* UART3 Receive/Transmit interrupt*/
+    .long   UART3_ERR_IRQHandler                            /* UART3 Error interrupt*/
+    .long   ADC0_IRQHandler                                 /* ADC0 interrupt*/
+    .long   CMP0_IRQHandler                                 /* CMP0 interrupt*/
+    .long   CMP1_IRQHandler                                 /* CMP1 interrupt*/
+    .long   FTM0_IRQHandler                                 /* FTM0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FTM1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FTM2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* CMT interrupt*/
+    .long   RTC_IRQHandler                                  /* RTC interrupt*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds interrupt*/
+    .long   PIT0_IRQHandler                                 /* PIT timer channel 0 interrupt*/
+    .long   PIT1_IRQHandler                                 /* PIT timer channel 1 interrupt*/
+    .long   PIT2_IRQHandler                                 /* PIT timer channel 2 interrupt*/
+    .long   PIT3_IRQHandler                                 /* PIT timer channel 3 interrupt*/
+    .long   PDB0_IRQHandler                                 /* PDB0 Interrupt*/
+    .long   USB0_IRQHandler                                 /* USB0 interrupt*/
+    .long   USBDCD_IRQHandler                               /* USBDCD Interrupt*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt 71*/
+    .long   DAC0_IRQHandler                                 /* DAC0 interrupt*/
+    .long   MCG_IRQHandler                                  /* MCG Interrupt*/
+    .long   LPTMR0_IRQHandler                               /* LPTimer interrupt*/
+    .long   PORTA_IRQHandler                                /* Port A interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* SPI2 Interrupt*/
+    .long   UART4_RX_TX_IRQHandler                          /* UART4 Receive/Transmit interrupt*/
+    .long   UART4_ERR_IRQHandler                            /* UART4 Error interrupt*/
+    .long   UART5_RX_TX_IRQHandler                          /* UART5 Receive/Transmit interrupt*/
+    .long   UART5_ERR_IRQHandler                            /* UART5 Error interrupt*/
+    .long   CMP2_IRQHandler                                 /* CMP2 interrupt*/
+    .long   FTM3_IRQHandler                                 /* FTM3 fault, overflow and channels interrupt*/
+    .long   DAC1_IRQHandler                                 /* DAC1 interrupt*/
+    .long   ADC1_IRQHandler                                 /* ADC1 interrupt*/
+    .long   I2C2_IRQHandler                                 /* I2C2 interrupt*/
+    .long   CAN0_ORed_Message_buffer_IRQHandler             /* CAN0 OR'd message buffers interrupt*/
+    .long   CAN0_Bus_Off_IRQHandler                         /* CAN0 bus off interrupt*/
+    .long   CAN0_Error_IRQHandler                           /* CAN0 error interrupt*/
+    .long   CAN0_Tx_Warning_IRQHandler                      /* CAN0 Tx warning interrupt*/
+    .long   CAN0_Rx_Warning_IRQHandler                      /* CAN0 Rx warning interrupt*/
+    .long   CAN0_Wake_Up_IRQHandler                         /* CAN0 wake up interrupt*/
+    .long   SDHC_IRQHandler                                 /* SDHC interrupt*/
+    .long   ENET_1588_Timer_IRQHandler                      /* Ethernet MAC IEEE 1588 Timer Interrupt*/
+    .long   ENET_Transmit_IRQHandler                        /* Ethernet MAC Transmit Interrupt*/
+    .long   ENET_Receive_IRQHandler                         /* Ethernet MAC Receive Interrupt*/
+    .long   ENET_Error_IRQHandler                           /* Ethernet MAC Error and miscelaneous Interrupt*/
+    .long   DefaultISR                                      /* 102*/
+    .long   DefaultISR                                      /* 103*/
+    .long   DefaultISR                                      /* 104*/
+    .long   DefaultISR                                      /* 105*/
+    .long   DefaultISR                                      /* 106*/
+    .long   DefaultISR                                      /* 107*/
+    .long   DefaultISR                                      /* 108*/
+    .long   DefaultISR                                      /* 109*/
+    .long   DefaultISR                                      /* 110*/
+    .long   DefaultISR                                      /* 111*/
+    .long   DefaultISR                                      /* 112*/
+    .long   DefaultISR                                      /* 113*/
+    .long   DefaultISR                                      /* 114*/
+    .long   DefaultISR                                      /* 115*/
+    .long   DefaultISR                                      /* 116*/
+    .long   DefaultISR                                      /* 117*/
+    .long   DefaultISR                                      /* 118*/
+    .long   DefaultISR                                      /* 119*/
+    .long   DefaultISR                                      /* 120*/
+    .long   DefaultISR                                      /* 121*/
+    .long   DefaultISR                                      /* 122*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+    .long   DefaultISR                                      /* 240*/
+    .long   DefaultISR                                      /* 241*/
+    .long   DefaultISR                                      /* 242*/
+    .long   DefaultISR                                      /* 243*/
+    .long   DefaultISR                                      /* 244*/
+    .long   DefaultISR                                      /* 245*/
+    .long   DefaultISR                                      /* 246*/
+    .long   DefaultISR                                      /* 247*/
+    .long   DefaultISR                                      /* 248*/
+    .long   DefaultISR                                      /* 249*/
+    .long   DefaultISR                                      /* 250*/
+    .long   DefaultISR                                      /* 251*/
+    .long   DefaultISR                                      /* 252*/
+    .long   DefaultISR                                      /* 253*/
+    .long   DefaultISR                                      /* 254*/
+    .long   0xFFFFFFFF                                      /*  Reserved for user TRIM value*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_IRQHandler
+    def_irq_handler    DMA1_IRQHandler
+    def_irq_handler    DMA2_IRQHandler
+    def_irq_handler    DMA3_IRQHandler
+    def_irq_handler    DMA4_IRQHandler
+    def_irq_handler    DMA5_IRQHandler
+    def_irq_handler    DMA6_IRQHandler
+    def_irq_handler    DMA7_IRQHandler
+    def_irq_handler    DMA8_IRQHandler
+    def_irq_handler    DMA9_IRQHandler
+    def_irq_handler    DMA10_IRQHandler
+    def_irq_handler    DMA11_IRQHandler
+    def_irq_handler    DMA12_IRQHandler
+    def_irq_handler    DMA13_IRQHandler
+    def_irq_handler    DMA14_IRQHandler
+    def_irq_handler    DMA15_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFE_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    RNG_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    UART0_LON_IRQHandler
+    def_irq_handler    UART0_RX_TX_IRQHandler
+    def_irq_handler    UART0_ERR_IRQHandler
+    def_irq_handler    UART1_RX_TX_IRQHandler
+    def_irq_handler    UART1_ERR_IRQHandler
+    def_irq_handler    UART2_RX_TX_IRQHandler
+    def_irq_handler    UART2_ERR_IRQHandler
+    def_irq_handler    UART3_RX_TX_IRQHandler
+    def_irq_handler    UART3_ERR_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    PIT1_IRQHandler
+    def_irq_handler    PIT2_IRQHandler
+    def_irq_handler    PIT3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    UART4_RX_TX_IRQHandler
+    def_irq_handler    UART4_ERR_IRQHandler
+    def_irq_handler    UART5_RX_TX_IRQHandler
+    def_irq_handler    UART5_ERR_IRQHandler
+    def_irq_handler    CMP2_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    DAC1_IRQHandler
+    def_irq_handler    ADC1_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    CAN0_ORed_Message_buffer_IRQHandler
+    def_irq_handler    CAN0_Bus_Off_IRQHandler
+    def_irq_handler    CAN0_Error_IRQHandler
+    def_irq_handler    CAN0_Tx_Warning_IRQHandler
+    def_irq_handler    CAN0_Rx_Warning_IRQHandler
+    def_irq_handler    CAN0_Wake_Up_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    ENET_1588_Timer_IRQHandler
+    def_irq_handler    ENET_Transmit_IRQHandler
+    def_irq_handler    ENET_Receive_IRQHandler
+    def_irq_handler    ENET_Error_IRQHandler
+
+    .end
diff --git a/Workspace/ADC/Project_Settings/Startup_Code/system_MK64F12.c b/Workspace/ADC/Project_Settings/Startup_Code/system_MK64F12.c
new file mode 100644
index 0000000..e3c1376
--- /dev/null
+++ b/Workspace/ADC/Project_Settings/Startup_Code/system_MK64F12.c
@@ -0,0 +1,414 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief Device specific configuration file for MK64F12 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+#if (DISABLE_WDOG)
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+  /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+  WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+                 WDOG_STCTRLH_WAITEN_MASK |
+                 WDOG_STCTRLH_STOPEN_MASK |
+                 WDOG_STCTRLH_ALLOWUPDATE_MASK |
+                 WDOG_STCTRLH_CLKSRC_MASK |
+                 0x0100U;
+#endif /* (DISABLE_WDOG) */
+#ifdef CLOCK_SETUP
+  if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
+  {
+    if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
+    {
+       PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO:  Only has an effect if recovering from VLLSx.*/
+    }
+  } else {
+#ifdef SYSTEM_RTC_CR_VALUE
+    SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
+    if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
+      RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
+      RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
+      RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
+    }
+#endif
+  }
+
+  /* Power mode protection initialization */
+#ifdef SYSTEM_SMC_PMPROT_VALUE
+  SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
+#endif
+
+  /* System clock initialization */
+  /* Internal reference clock trim initialization */
+#if defined(SLOW_TRIM_ADDRESS)
+  if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) {                              /* Skip if non-volatile flash memory is erased */
+    MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
+  #endif /* defined(SLOW_TRIM_ADDRESS) */
+  #if defined(SLOW_FINE_TRIM_ADDRESS)
+    MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
+  #endif
+  #if defined(FAST_TRIM_ADDRESS)
+    MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
+  #endif
+  #if defined(FAST_FINE_TRIM_ADDRESS)
+    MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
+  #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
+#if defined(SLOW_TRIM_ADDRESS)
+  }
+  #endif /* defined(SLOW_TRIM_ADDRESS) */
+
+  /* Set system prescalers and clock sources */
+  SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
+  SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
+  SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+  /* Set MCG and OSC */
+#if  ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+  /* PORTA_PCR19: ISF=0,MUX=0 */
+  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
+  MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+  /* Check that the source of the FLL reference clock is the requested one. */
+  if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+    }
+  } else {
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+    }
+  }
+  MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+  MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+  OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
+  #if (MCG_MODE == MCG_MODE_BLPI)
+  /* BLPI specific */
+  MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
+  #endif
+
+#else /* MCG_MODE */
+  /* Set MCG and OSC */
+#if  (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+  /* PORTA_PCR19: ISF=0,MUX=0 */
+  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
+  MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+  OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
+  #if (MCG_MODE == MCG_MODE_PEE)
+  MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
+  #else
+  MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+  #endif
+  if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
+    while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
+    }
+  }
+  /* Check that the source of the FLL reference clock is the requested one. */
+  if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+    }
+  } else {
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+    }
+  }
+  MCG->C4 = ((SYSTEM_MCG_C4_VALUE)  & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+#endif /* MCG_MODE */
+
+  /* Common for all MCG modes */
+
+  /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
+  MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
+  MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+  if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
+    MCG->C5 |= MCG_C5_PLLCLKEN0_MASK;  /* PLL clock enable in mode other than PEE or PBE */
+  }
+  /* BLPE, PEE and PBE MCG mode specific */
+
+#if (MCG_MODE == MCG_MODE_BLPE)
+  MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
+#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
+  MCG->C6 |= (MCG_C6_PLLS_MASK);       /* Set C6 (PLL select, VCO divider etc.) */
+  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
+  }
+  #if (MCG_MODE == MCG_MODE_PEE)
+  MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
+  #endif
+#endif
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
+  }
+  /* Use LPTMR to wait for 1ms dor FLL clock stabilization */
+  SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;   /* Alow software control of LPMTR */
+  LPTMR0->CMR = LPTMR_CMR_COMPARE(0);  /* Default 1 LPO tick */
+  LPTMR0->CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00));
+  LPTMR0->PSR = (LPTMR_PSR_PCS(0x01) | LPTMR_PSR_PBYP_MASK); /* Clock source: LPO, Prescaler bypass enable */
+  LPTMR0->CSR = LPTMR_CSR_TEN_MASK;    /* LPMTR enable */
+  while((LPTMR0_CSR & LPTMR_CSR_TCF_MASK) == 0u) {
+  }
+  LPTMR0_CSR = 0x00;                   /* Disable LPTMR */
+  SIM_SCGC5 &= (uint32_t)~(uint32_t)SIM_SCGC5_LPTMR_MASK;
+#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
+  }
+#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+  }
+#elif (MCG_MODE == MCG_MODE_PEE)
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
+  }
+#endif
+#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
+  SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
+  while(SMC->PMSTAT != 0x04U) {        /* Wait until the system is in VLPR mode */
+  }
+#endif
+
+#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
+  SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
+#endif
+
+  /* PLL loss of lock interrupt request initialization */
+  if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
+    NVIC_EnableIRQ(MCG_IRQn);          /* Enable PLL loss of lock interrupt request */
+  }
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+  uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
+  uint16_t Divider;
+
+  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
+    /* Output of FLL or PLL is selected */
+    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
+      /* FLL is selected */
+      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+        case 0x00U:
+          MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+          break;
+        case 0x01U:
+          MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+          break;
+        case 0x02U:
+        default:
+          MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+          break;
+        }
+        if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
+          switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
+          case 0x38U:
+            Divider = 1536U;
+            break;
+          case 0x30U:
+            Divider = 1280U;
+            break;
+          default:
+            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+            break;
+          }
+        } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+          Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+        }
+        MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+        MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+      /* Select correct multiplier to calculate the MCG output clock  */
+      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+        case 0x00U:
+          MCGOUTClock *= 640U;
+          break;
+        case 0x20U:
+          MCGOUTClock *= 1280U;
+          break;
+        case 0x40U:
+          MCGOUTClock *= 1920U;
+          break;
+        case 0x60U:
+          MCGOUTClock *= 2560U;
+          break;
+        case 0x80U:
+          MCGOUTClock *= 732U;
+          break;
+        case 0xA0U:
+          MCGOUTClock *= 1464U;
+          break;
+        case 0xC0U:
+          MCGOUTClock *= 2197U;
+          break;
+        case 0xE0U:
+          MCGOUTClock *= 2929U;
+          break;
+        default:
+          break;
+      }
+    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+      /* PLL is selected */
+      Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
+      MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+      Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
+      MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
+    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
+    /* Internal reference clock is selected */
+    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+      Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+      MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
+    /* External reference clock is selected */
+    switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+    case 0x00U:
+      MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
+      break;
+    case 0x01U:
+      MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+      break;
+    case 0x02U:
+    default:
+      MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+      break;
+    }
+  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    /* Reserved value */
+    return;
+  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+  SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/Workspace/ADC/Project_Settings/Startup_Code/system_MK64F12.h b/Workspace/ADC/Project_Settings/Startup_Code/system_MK64F12.h
new file mode 100644
index 0000000..d6a5f05
--- /dev/null
+++ b/Workspace/ADC/Project_Settings/Startup_Code/system_MK64F12.h
@@ -0,0 +1,352 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief Device specific configuration file for MK64F12 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK64F12_H_
+#define SYSTEM_MK64F12_H_                        /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG                 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI                   0U
+#define MCG_MODE_FBI                   1U
+#define MCG_MODE_BLPI                  2U
+#define MCG_MODE_FEE                   3U
+#define MCG_MODE_FBE                   4U
+#define MCG_MODE_BLPE                  5U
+#define MCG_MODE_PBE                   6U
+#define MCG_MODE_PEE                   7U
+
+/* Predefined clock setups
+   0 ... Default  part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock = 20.97152MHz
+         Bus clock  = 20.97152MHz
+   1 ... Maximum achievable clock frequency configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+   2 ... Chip internaly clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   3 ... Chip externally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: RTC oscillator reference clock
+         Core clock = 0.032768MHz
+         Bus clock  = 0.032768MHz
+   4 ... USB clock setup
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+ */
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ                50000000u           /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_XTAL32k_CLK_HZ             32768u              /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+#define CPU_INT_SLOW_CLK_HZ            32768u              /* Value of the slow internal oscillator clock frequency in Hz  */
+#define CPU_INT_FAST_CLK_HZ            4000000u            /* Value of the fast internal oscillator clock frequency in Hz  */
+#define CPU_INT_IRC_CLK_HZ             48000000u           /* Value of the 48M internal oscillator clock frequency in Hz  */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE            0x0300U             /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE        0x2AU               /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */                             /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */                        /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */                             /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */                        /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_FEI /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x06U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00110000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00U               /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 1)
+  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 2)
+  #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_BLPI /* Clock generator mode */
+  /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x46U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00040000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 3)
+  #define DEFAULT_SYSTEM_CLOCK         32768u              /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_BLPE /* Clock generator mode */
+  /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x82U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x02U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=1 */
+  #define SYSTEM_MCG_C7_VALUE          0x01U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00U               /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 4)
+  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
+  #define SYSTEM_SIM_CLKDIV2_VALUE     0x09U               /* SIM_CLKDIV2 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
+#endif
+#else
+  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* #if !defined(SYSTEM_MK64F12_H_) */
diff --git a/Workspace/ADC/SDK/platform/CMSIS/Include/arm_common_tables.h b/Workspace/ADC/SDK/platform/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000..039cc3d
--- /dev/null
+++ b/Workspace/ADC/SDK/platform/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/Workspace/ADC/SDK/platform/CMSIS/Include/arm_const_structs.h b/Workspace/ADC/SDK/platform/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 0000000..726d06e
--- /dev/null
+++ b/Workspace/ADC/SDK/platform/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/Workspace/ADC/SDK/platform/CMSIS/Include/arm_math.h b/Workspace/ADC/SDK/platform/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000..e4b2f62
--- /dev/null
+++ b/Workspace/ADC/SDK/platform/CMSIS/Include/arm_math.h
@@ -0,0 +1,7556 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_math.h
+*
+* Description:	Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   * 
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   * 
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+  #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31	   0x400000
+#define TABLE_SPACING_Q15	   0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+#elif defined __GNUC__
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__			/* Cosmic */
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+#elif defined __TASKING__
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+//#define __CLZ __clz
+//#endif
+
+//note: function can be removed when all toolchain support __CLZ for Cortex-M0
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+      ((q15_t) x * (q15_t) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		 *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15( 
+    const arm_cfft_instance_q15 * S, 
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31( 
+    const arm_cfft_instance_q31 * S, 
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+  
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in >= 0.0f)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+   
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("push")         \
+         _Pragma ("O1")
+    #else
+      #define LOW_OPTIMIZATION_ENTER 
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_EXIT \
+         _Pragma ("pop")
+    #else
+      #define LOW_OPTIMIZATION_EXIT  
+    #endif
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)		// Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)		// TASKING
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/Workspace/ADC/SDK/platform/CMSIS/Include/core_cm4.h b/Workspace/ADC/SDK/platform/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000..9749c27
--- /dev/null
+++ b/Workspace/ADC/SDK/platform/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1858 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)IRQn < 0) {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)IRQn < 0) {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                             /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Workspace/ADC/SDK/platform/CMSIS/Include/core_cmFunc.h b/Workspace/ADC/SDK/platform/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000..b6ad0a4
--- /dev/null
+++ b/Workspace/ADC/SDK/platform/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,664 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+    or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+	or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/Workspace/ADC/SDK/platform/CMSIS/Include/core_cmInstr.h b/Workspace/ADC/SDK/platform/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000..fca425c
--- /dev/null
+++ b/Workspace/ADC/SDK/platform/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,916 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+  return(result);
+}
+#endif
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+#endif
+  return(result);
+}
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/Workspace/ADC/SDK/platform/CMSIS/Include/core_cmSimd.h b/Workspace/ADC/SDK/platform/CMSIS/Include/core_cmSimd.h
new file mode 100644
index 0000000..7b8e37f
--- /dev/null
+++ b/Workspace/ADC/SDK/platform/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/Workspace/ADC/SDK/platform/devices/MK64F12/include/MK64F12.h b/Workspace/ADC/SDK/platform/devices/MK64F12/include/MK64F12.h
new file mode 100644
index 0000000..3114ad7
--- /dev/null
+++ b/Workspace/ADC/SDK/platform/devices/MK64F12/include/MK64F12.h
@@ -0,0 +1,18767 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MK64F12
+**
+**     Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12.h
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief CMSIS Peripheral Access Layer for MK64F12
+ *
+ * CMSIS Peripheral Access Layer for MK64F12
+ */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCU activation
+   ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MK64F12_H_)  /* Check if memory map has not been already included */
+#define MK64F12_H_
+#define MCU_MK64F12
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+  #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0008u
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ *        bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ *        0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return  Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 102                /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_IRQn                    = 0,                /**< DMA Channel 0 Transfer Complete */
+  DMA1_IRQn                    = 1,                /**< DMA Channel 1 Transfer Complete */
+  DMA2_IRQn                    = 2,                /**< DMA Channel 2 Transfer Complete */
+  DMA3_IRQn                    = 3,                /**< DMA Channel 3 Transfer Complete */
+  DMA4_IRQn                    = 4,                /**< DMA Channel 4 Transfer Complete */
+  DMA5_IRQn                    = 5,                /**< DMA Channel 5 Transfer Complete */
+  DMA6_IRQn                    = 6,                /**< DMA Channel 6 Transfer Complete */
+  DMA7_IRQn                    = 7,                /**< DMA Channel 7 Transfer Complete */
+  DMA8_IRQn                    = 8,                /**< DMA Channel 8 Transfer Complete */
+  DMA9_IRQn                    = 9,                /**< DMA Channel 9 Transfer Complete */
+  DMA10_IRQn                   = 10,               /**< DMA Channel 10 Transfer Complete */
+  DMA11_IRQn                   = 11,               /**< DMA Channel 11 Transfer Complete */
+  DMA12_IRQn                   = 12,               /**< DMA Channel 12 Transfer Complete */
+  DMA13_IRQn                   = 13,               /**< DMA Channel 13 Transfer Complete */
+  DMA14_IRQn                   = 14,               /**< DMA Channel 14 Transfer Complete */
+  DMA15_IRQn                   = 15,               /**< DMA Channel 15 Transfer Complete */
+  DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
+  MCM_IRQn                     = 17,               /**< Normal Interrupt */
+  FTFE_IRQn                    = 18,               /**< FTFE Command complete interrupt */
+  Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
+  LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
+  LLWU_IRQn                    = 21,               /**< Low Leakage Wakeup Unit */
+  WDOG_EWM_IRQn                = 22,               /**< WDOG Interrupt */
+  RNG_IRQn                     = 23,               /**< RNG Interrupt */
+  I2C0_IRQn                    = 24,               /**< I2C0 interrupt */
+  I2C1_IRQn                    = 25,               /**< I2C1 interrupt */
+  SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
+  SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
+  I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
+  I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
+  UART0_LON_IRQn               = 30,               /**< UART0 LON interrupt */
+  UART0_RX_TX_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
+  UART0_ERR_IRQn               = 32,               /**< UART0 Error interrupt */
+  UART1_RX_TX_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
+  UART1_ERR_IRQn               = 34,               /**< UART1 Error interrupt */
+  UART2_RX_TX_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
+  UART2_ERR_IRQn               = 36,               /**< UART2 Error interrupt */
+  UART3_RX_TX_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
+  UART3_ERR_IRQn               = 38,               /**< UART3 Error interrupt */
+  ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
+  CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
+  FTM0_IRQn                    = 42,               /**< FTM0 fault, overflow and channels interrupt */
+  FTM1_IRQn                    = 43,               /**< FTM1 fault, overflow and channels interrupt */
+  FTM2_IRQn                    = 44,               /**< FTM2 fault, overflow and channels interrupt */
+  CMT_IRQn                     = 45,               /**< CMT interrupt */
+  RTC_IRQn                     = 46,               /**< RTC interrupt */
+  RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
+  PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
+  PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
+  PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
+  PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
+  PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
+  USB0_IRQn                    = 53,               /**< USB0 interrupt */
+  USBDCD_IRQn                  = 54,               /**< USBDCD Interrupt */
+  Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
+  DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
+  MCG_IRQn                     = 57,               /**< MCG Interrupt */
+  LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
+  PORTA_IRQn                   = 59,               /**< Port A interrupt */
+  PORTB_IRQn                   = 60,               /**< Port B interrupt */
+  PORTC_IRQn                   = 61,               /**< Port C interrupt */
+  PORTD_IRQn                   = 62,               /**< Port D interrupt */
+  PORTE_IRQn                   = 63,               /**< Port E interrupt */
+  SWI_IRQn                     = 64,               /**< Software interrupt */
+  SPI2_IRQn                    = 65,               /**< SPI2 Interrupt */
+  UART4_RX_TX_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
+  UART4_ERR_IRQn               = 67,               /**< UART4 Error interrupt */
+  UART5_RX_TX_IRQn             = 68,               /**< UART5 Receive/Transmit interrupt */
+  UART5_ERR_IRQn               = 69,               /**< UART5 Error interrupt */
+  CMP2_IRQn                    = 70,               /**< CMP2 interrupt */
+  FTM3_IRQn                    = 71,               /**< FTM3 fault, overflow and channels interrupt */
+  DAC1_IRQn                    = 72,               /**< DAC1 interrupt */
+  ADC1_IRQn                    = 73,               /**< ADC1 interrupt */
+  I2C2_IRQn                    = 74,               /**< I2C2 interrupt */
+  CAN0_ORed_Message_buffer_IRQn = 75,              /**< CAN0 OR'd message buffers interrupt */
+  CAN0_Bus_Off_IRQn            = 76,               /**< CAN0 bus off interrupt */
+  CAN0_Error_IRQn              = 77,               /**< CAN0 error interrupt */
+  CAN0_Tx_Warning_IRQn         = 78,               /**< CAN0 Tx warning interrupt */
+  CAN0_Rx_Warning_IRQn         = 79,               /**< CAN0 Rx warning interrupt */
+  CAN0_Wake_Up_IRQn            = 80,               /**< CAN0 wake up interrupt */
+  SDHC_IRQn                    = 81,               /**< SDHC interrupt */
+  ENET_1588_Timer_IRQn         = 82,               /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+  ENET_Transmit_IRQn           = 83,               /**< Ethernet MAC Transmit Interrupt */
+  ENET_Receive_IRQn            = 84,               /**< Ethernet MAC Receive Interrupt */
+  ENET_Error_IRQn              = 85                /**< Ethernet MAC Error and miscelaneous Interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_MK64F12.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index)                  ((base)->SC1[index])
+#define ADC_SC1_COUNT                            2
+#define ADC_CFG1_REG(base)                       ((base)->CFG1)
+#define ADC_CFG2_REG(base)                       ((base)->CFG2)
+#define ADC_R_REG(base,index)                    ((base)->R[index])
+#define ADC_R_COUNT                              2
+#define ADC_CV1_REG(base)                        ((base)->CV1)
+#define ADC_CV2_REG(base)                        ((base)->CV2)
+#define ADC_SC2_REG(base)                        ((base)->SC2)
+#define ADC_SC3_REG(base)                        ((base)->SC3)
+#define ADC_OFS_REG(base)                        ((base)->OFS)
+#define ADC_PG_REG(base)                         ((base)->PG)
+#define ADC_MG_REG(base)                         ((base)->MG)
+#define ADC_CLPD_REG(base)                       ((base)->CLPD)
+#define ADC_CLPS_REG(base)                       ((base)->CLPS)
+#define ADC_CLP4_REG(base)                       ((base)->CLP4)
+#define ADC_CLP3_REG(base)                       ((base)->CLP3)
+#define ADC_CLP2_REG(base)                       ((base)->CLP2)
+#define ADC_CLP1_REG(base)                       ((base)->CLP1)
+#define ADC_CLP0_REG(base)                       ((base)->CLP0)
+#define ADC_CLMD_REG(base)                       ((base)->CLMD)
+#define ADC_CLMS_REG(base)                       ((base)->CLMS)
+#define ADC_CLM4_REG(base)                       ((base)->CLM4)
+#define ADC_CLM3_REG(base)                       ((base)->CLM3)
+#define ADC_CLM2_REG(base)                       ((base)->CLM2)
+#define ADC_CLM1_REG(base)                       ((base)->CLM1)
+#define ADC_CLM0_REG(base)                       ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK                        0x1Fu
+#define ADC_SC1_ADCH_SHIFT                       0
+#define ADC_SC1_ADCH_WIDTH                       5
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        0x20u
+#define ADC_SC1_DIFF_SHIFT                       5
+#define ADC_SC1_DIFF_WIDTH                       1
+#define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK                        0x40u
+#define ADC_SC1_AIEN_SHIFT                       6
+#define ADC_SC1_AIEN_WIDTH                       1
+#define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK                        0x80u
+#define ADC_SC1_COCO_SHIFT                       7
+#define ADC_SC1_COCO_WIDTH                       1
+#define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK                     0x3u
+#define ADC_CFG1_ADICLK_SHIFT                    0
+#define ADC_CFG1_ADICLK_WIDTH                    2
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       0xCu
+#define ADC_CFG1_MODE_SHIFT                      2
+#define ADC_CFG1_MODE_WIDTH                      2
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     0x10u
+#define ADC_CFG1_ADLSMP_SHIFT                    4
+#define ADC_CFG1_ADLSMP_WIDTH                    1
+#define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK                       0x60u
+#define ADC_CFG1_ADIV_SHIFT                      5
+#define ADC_CFG1_ADIV_WIDTH                      2
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      0x80u
+#define ADC_CFG1_ADLPC_SHIFT                     7
+#define ADC_CFG1_ADLPC_WIDTH                     1
+#define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK                     0x3u
+#define ADC_CFG2_ADLSTS_SHIFT                    0
+#define ADC_CFG2_ADLSTS_WIDTH                    2
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      0x4u
+#define ADC_CFG2_ADHSC_SHIFT                     2
+#define ADC_CFG2_ADHSC_WIDTH                     1
+#define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK                    0x8u
+#define ADC_CFG2_ADACKEN_SHIFT                   3
+#define ADC_CFG2_ADACKEN_WIDTH                   1
+#define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK                     0x10u
+#define ADC_CFG2_MUXSEL_SHIFT                    4
+#define ADC_CFG2_MUXSEL_WIDTH                    1
+#define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
+/* R Bit Fields */
+#define ADC_R_D_MASK                             0xFFFFu
+#define ADC_R_D_SHIFT                            0
+#define ADC_R_D_WIDTH                            16
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK                          0xFFFFu
+#define ADC_CV1_CV_SHIFT                         0
+#define ADC_CV1_CV_WIDTH                         16
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK                          0xFFFFu
+#define ADC_CV2_CV_SHIFT                         0
+#define ADC_CV2_CV_WIDTH                         16
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK                      0x3u
+#define ADC_SC2_REFSEL_SHIFT                     0
+#define ADC_SC2_REFSEL_WIDTH                     2
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       0x4u
+#define ADC_SC2_DMAEN_SHIFT                      2
+#define ADC_SC2_DMAEN_WIDTH                      1
+#define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK                       0x8u
+#define ADC_SC2_ACREN_SHIFT                      3
+#define ADC_SC2_ACREN_WIDTH                      1
+#define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK                       0x10u
+#define ADC_SC2_ACFGT_SHIFT                      4
+#define ADC_SC2_ACFGT_WIDTH                      1
+#define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK                        0x20u
+#define ADC_SC2_ACFE_SHIFT                       5
+#define ADC_SC2_ACFE_WIDTH                       1
+#define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK                       0x40u
+#define ADC_SC2_ADTRG_SHIFT                      6
+#define ADC_SC2_ADTRG_WIDTH                      1
+#define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK                       0x80u
+#define ADC_SC2_ADACT_SHIFT                      7
+#define ADC_SC2_ADACT_WIDTH                      1
+#define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK                        0x3u
+#define ADC_SC3_AVGS_SHIFT                       0
+#define ADC_SC3_AVGS_WIDTH                       2
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        0x4u
+#define ADC_SC3_AVGE_SHIFT                       2
+#define ADC_SC3_AVGE_WIDTH                       1
+#define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK                        0x8u
+#define ADC_SC3_ADCO_SHIFT                       3
+#define ADC_SC3_ADCO_WIDTH                       1
+#define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK                        0x40u
+#define ADC_SC3_CALF_SHIFT                       6
+#define ADC_SC3_CALF_WIDTH                       1
+#define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK                         0x80u
+#define ADC_SC3_CAL_SHIFT                        7
+#define ADC_SC3_CAL_WIDTH                        1
+#define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK                         0xFFFFu
+#define ADC_OFS_OFS_SHIFT                        0
+#define ADC_OFS_OFS_WIDTH                        16
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK                           0xFFFFu
+#define ADC_PG_PG_SHIFT                          0
+#define ADC_PG_PG_WIDTH                          16
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK                           0xFFFFu
+#define ADC_MG_MG_SHIFT                          0
+#define ADC_MG_MG_WIDTH                          16
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK                       0x3Fu
+#define ADC_CLPD_CLPD_SHIFT                      0
+#define ADC_CLPD_CLPD_WIDTH                      6
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK                       0x3Fu
+#define ADC_CLPS_CLPS_SHIFT                      0
+#define ADC_CLPS_CLPS_WIDTH                      6
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK                       0x3FFu
+#define ADC_CLP4_CLP4_SHIFT                      0
+#define ADC_CLP4_CLP4_WIDTH                      10
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK                       0x1FFu
+#define ADC_CLP3_CLP3_SHIFT                      0
+#define ADC_CLP3_CLP3_WIDTH                      9
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK                       0xFFu
+#define ADC_CLP2_CLP2_SHIFT                      0
+#define ADC_CLP2_CLP2_WIDTH                      8
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK                       0x7Fu
+#define ADC_CLP1_CLP1_SHIFT                      0
+#define ADC_CLP1_CLP1_WIDTH                      7
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK                       0x3Fu
+#define ADC_CLP0_CLP0_SHIFT                      0
+#define ADC_CLP0_CLP0_WIDTH                      6
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK                       0x3Fu
+#define ADC_CLMD_CLMD_SHIFT                      0
+#define ADC_CLMD_CLMD_WIDTH                      6
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK                       0x3Fu
+#define ADC_CLMS_CLMS_SHIFT                      0
+#define ADC_CLMS_CLMS_WIDTH                      6
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK                       0x3FFu
+#define ADC_CLM4_CLM4_SHIFT                      0
+#define ADC_CLM4_CLM4_WIDTH                      10
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK                       0x1FFu
+#define ADC_CLM3_CLM3_SHIFT                      0
+#define ADC_CLM3_CLM3_WIDTH                      9
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK                       0xFFu
+#define ADC_CLM2_CLM2_SHIFT                      0
+#define ADC_CLM2_CLM2_WIDTH                      8
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK                       0x7Fu
+#define ADC_CLM1_CLM1_SHIFT                      0
+#define ADC_CLM1_CLM1_WIDTH                      7
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK                       0x3Fu
+#define ADC_CLM0_CLM0_SHIFT                      0
+#define ADC_CLM0_CLM0_WIDTH                      6
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR                            (ADC0)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_Type *)ADC1_BASE)
+#define ADC1_BASE_PTR                            (ADC1)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A                                ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B                                ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1                                ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2                                ADC_CFG2_REG(ADC0)
+#define ADC0_RA                                  ADC_R_REG(ADC0,0)
+#define ADC0_RB                                  ADC_R_REG(ADC0,1)
+#define ADC0_CV1                                 ADC_CV1_REG(ADC0)
+#define ADC0_CV2                                 ADC_CV2_REG(ADC0)
+#define ADC0_SC2                                 ADC_SC2_REG(ADC0)
+#define ADC0_SC3                                 ADC_SC3_REG(ADC0)
+#define ADC0_OFS                                 ADC_OFS_REG(ADC0)
+#define ADC0_PG                                  ADC_PG_REG(ADC0)
+#define ADC0_MG                                  ADC_MG_REG(ADC0)
+#define ADC0_CLPD                                ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS                                ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4                                ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3                                ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2                                ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1                                ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0                                ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD                                ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS                                ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4                                ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3                                ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2                                ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1                                ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0                                ADC_CLM0_REG(ADC0)
+/* ADC1 */
+#define ADC1_SC1A                                ADC_SC1_REG(ADC1,0)
+#define ADC1_SC1B                                ADC_SC1_REG(ADC1,1)
+#define ADC1_CFG1                                ADC_CFG1_REG(ADC1)
+#define ADC1_CFG2                                ADC_CFG2_REG(ADC1)
+#define ADC1_RA                                  ADC_R_REG(ADC1,0)
+#define ADC1_RB                                  ADC_R_REG(ADC1,1)
+#define ADC1_CV1                                 ADC_CV1_REG(ADC1)
+#define ADC1_CV2                                 ADC_CV2_REG(ADC1)
+#define ADC1_SC2                                 ADC_SC2_REG(ADC1)
+#define ADC1_SC3                                 ADC_SC3_REG(ADC1)
+#define ADC1_OFS                                 ADC_OFS_REG(ADC1)
+#define ADC1_PG                                  ADC_PG_REG(ADC1)
+#define ADC1_MG                                  ADC_MG_REG(ADC1)
+#define ADC1_CLPD                                ADC_CLPD_REG(ADC1)
+#define ADC1_CLPS                                ADC_CLPS_REG(ADC1)
+#define ADC1_CLP4                                ADC_CLP4_REG(ADC1)
+#define ADC1_CLP3                                ADC_CLP3_REG(ADC1)
+#define ADC1_CLP2                                ADC_CLP2_REG(ADC1)
+#define ADC1_CLP1                                ADC_CLP1_REG(ADC1)
+#define ADC1_CLP0                                ADC_CLP0_REG(ADC1)
+#define ADC1_CLMD                                ADC_CLMD_REG(ADC1)
+#define ADC1_CLMS                                ADC_CLMS_REG(ADC1)
+#define ADC1_CLM4                                ADC_CLM4_REG(ADC1)
+#define ADC1_CLM3                                ADC_CLM3_REG(ADC1)
+#define ADC1_CLM2                                ADC_CLM2_REG(ADC1)
+#define ADC1_CLM1                                ADC_CLM1_REG(ADC1)
+#define ADC1_CLM0                                ADC_CLM0_REG(ADC1)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index)                          ADC_SC1_REG(ADC0,index)
+#define ADC1_SC1(index)                          ADC_SC1_REG(ADC1,index)
+#define ADC0_R(index)                            ADC_R_REG(ADC0,index)
+#define ADC1_R(index)                            ADC_R_REG(ADC1,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPRA;                              /**< Master Privilege Register A, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PACRA;                             /**< Peripheral Access Control Register, offset: 0x20 */
+  __IO uint32_t PACRB;                             /**< Peripheral Access Control Register, offset: 0x24 */
+  __IO uint32_t PACRC;                             /**< Peripheral Access Control Register, offset: 0x28 */
+  __IO uint32_t PACRD;                             /**< Peripheral Access Control Register, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PACRE;                             /**< Peripheral Access Control Register, offset: 0x40 */
+  __IO uint32_t PACRF;                             /**< Peripheral Access Control Register, offset: 0x44 */
+  __IO uint32_t PACRG;                             /**< Peripheral Access Control Register, offset: 0x48 */
+  __IO uint32_t PACRH;                             /**< Peripheral Access Control Register, offset: 0x4C */
+  __IO uint32_t PACRI;                             /**< Peripheral Access Control Register, offset: 0x50 */
+  __IO uint32_t PACRJ;                             /**< Peripheral Access Control Register, offset: 0x54 */
+  __IO uint32_t PACRK;                             /**< Peripheral Access Control Register, offset: 0x58 */
+  __IO uint32_t PACRL;                             /**< Peripheral Access Control Register, offset: 0x5C */
+  __IO uint32_t PACRM;                             /**< Peripheral Access Control Register, offset: 0x60 */
+  __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
+  __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
+  __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t PACRU;                             /**< Peripheral Access Control Register, offset: 0x80 */
+} AIPS_Type, *AIPS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register accessors */
+#define AIPS_MPRA_REG(base)                      ((base)->MPRA)
+#define AIPS_PACRA_REG(base)                     ((base)->PACRA)
+#define AIPS_PACRB_REG(base)                     ((base)->PACRB)
+#define AIPS_PACRC_REG(base)                     ((base)->PACRC)
+#define AIPS_PACRD_REG(base)                     ((base)->PACRD)
+#define AIPS_PACRE_REG(base)                     ((base)->PACRE)
+#define AIPS_PACRF_REG(base)                     ((base)->PACRF)
+#define AIPS_PACRG_REG(base)                     ((base)->PACRG)
+#define AIPS_PACRH_REG(base)                     ((base)->PACRH)
+#define AIPS_PACRI_REG(base)                     ((base)->PACRI)
+#define AIPS_PACRJ_REG(base)                     ((base)->PACRJ)
+#define AIPS_PACRK_REG(base)                     ((base)->PACRK)
+#define AIPS_PACRL_REG(base)                     ((base)->PACRL)
+#define AIPS_PACRM_REG(base)                     ((base)->PACRM)
+#define AIPS_PACRN_REG(base)                     ((base)->PACRN)
+#define AIPS_PACRO_REG(base)                     ((base)->PACRO)
+#define AIPS_PACRP_REG(base)                     ((base)->PACRP)
+#define AIPS_PACRU_REG(base)                     ((base)->PACRU)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/* MPRA Bit Fields */
+#define AIPS_MPRA_MPL5_MASK                      0x100u
+#define AIPS_MPRA_MPL5_SHIFT                     8
+#define AIPS_MPRA_MPL5_WIDTH                     1
+#define AIPS_MPRA_MPL5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL5_SHIFT))&AIPS_MPRA_MPL5_MASK)
+#define AIPS_MPRA_MTW5_MASK                      0x200u
+#define AIPS_MPRA_MTW5_SHIFT                     9
+#define AIPS_MPRA_MTW5_WIDTH                     1
+#define AIPS_MPRA_MTW5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW5_SHIFT))&AIPS_MPRA_MTW5_MASK)
+#define AIPS_MPRA_MTR5_MASK                      0x400u
+#define AIPS_MPRA_MTR5_SHIFT                     10
+#define AIPS_MPRA_MTR5_WIDTH                     1
+#define AIPS_MPRA_MTR5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR5_SHIFT))&AIPS_MPRA_MTR5_MASK)
+#define AIPS_MPRA_MPL4_MASK                      0x1000u
+#define AIPS_MPRA_MPL4_SHIFT                     12
+#define AIPS_MPRA_MPL4_WIDTH                     1
+#define AIPS_MPRA_MPL4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL4_SHIFT))&AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MTW4_MASK                      0x2000u
+#define AIPS_MPRA_MTW4_SHIFT                     13
+#define AIPS_MPRA_MTW4_WIDTH                     1
+#define AIPS_MPRA_MTW4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW4_SHIFT))&AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTR4_MASK                      0x4000u
+#define AIPS_MPRA_MTR4_SHIFT                     14
+#define AIPS_MPRA_MTR4_WIDTH                     1
+#define AIPS_MPRA_MTR4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR4_SHIFT))&AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MPL3_MASK                      0x10000u
+#define AIPS_MPRA_MPL3_SHIFT                     16
+#define AIPS_MPRA_MPL3_WIDTH                     1
+#define AIPS_MPRA_MPL3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL3_SHIFT))&AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MTW3_MASK                      0x20000u
+#define AIPS_MPRA_MTW3_SHIFT                     17
+#define AIPS_MPRA_MTW3_WIDTH                     1
+#define AIPS_MPRA_MTW3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW3_SHIFT))&AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTR3_MASK                      0x40000u
+#define AIPS_MPRA_MTR3_SHIFT                     18
+#define AIPS_MPRA_MTR3_WIDTH                     1
+#define AIPS_MPRA_MTR3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR3_SHIFT))&AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MPL2_MASK                      0x100000u
+#define AIPS_MPRA_MPL2_SHIFT                     20
+#define AIPS_MPRA_MPL2_WIDTH                     1
+#define AIPS_MPRA_MPL2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL2_SHIFT))&AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MTW2_MASK                      0x200000u
+#define AIPS_MPRA_MTW2_SHIFT                     21
+#define AIPS_MPRA_MTW2_WIDTH                     1
+#define AIPS_MPRA_MTW2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW2_SHIFT))&AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTR2_MASK                      0x400000u
+#define AIPS_MPRA_MTR2_SHIFT                     22
+#define AIPS_MPRA_MTR2_WIDTH                     1
+#define AIPS_MPRA_MTR2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR2_SHIFT))&AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MPL1_MASK                      0x1000000u
+#define AIPS_MPRA_MPL1_SHIFT                     24
+#define AIPS_MPRA_MPL1_WIDTH                     1
+#define AIPS_MPRA_MPL1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL1_SHIFT))&AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MTW1_MASK                      0x2000000u
+#define AIPS_MPRA_MTW1_SHIFT                     25
+#define AIPS_MPRA_MTW1_WIDTH                     1
+#define AIPS_MPRA_MTW1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW1_SHIFT))&AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTR1_MASK                      0x4000000u
+#define AIPS_MPRA_MTR1_SHIFT                     26
+#define AIPS_MPRA_MTR1_WIDTH                     1
+#define AIPS_MPRA_MTR1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR1_SHIFT))&AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MPL0_MASK                      0x10000000u
+#define AIPS_MPRA_MPL0_SHIFT                     28
+#define AIPS_MPRA_MPL0_WIDTH                     1
+#define AIPS_MPRA_MPL0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL0_SHIFT))&AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MTW0_MASK                      0x20000000u
+#define AIPS_MPRA_MTW0_SHIFT                     29
+#define AIPS_MPRA_MTW0_WIDTH                     1
+#define AIPS_MPRA_MTW0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW0_SHIFT))&AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTR0_MASK                      0x40000000u
+#define AIPS_MPRA_MTR0_SHIFT                     30
+#define AIPS_MPRA_MTR0_WIDTH                     1
+#define AIPS_MPRA_MTR0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR0_SHIFT))&AIPS_MPRA_MTR0_MASK)
+/* PACRA Bit Fields */
+#define AIPS_PACRA_TP7_MASK                      0x1u
+#define AIPS_PACRA_TP7_SHIFT                     0
+#define AIPS_PACRA_TP7_WIDTH                     1
+#define AIPS_PACRA_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP7_SHIFT))&AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_WP7_MASK                      0x2u
+#define AIPS_PACRA_WP7_SHIFT                     1
+#define AIPS_PACRA_WP7_WIDTH                     1
+#define AIPS_PACRA_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP7_SHIFT))&AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_SP7_MASK                      0x4u
+#define AIPS_PACRA_SP7_SHIFT                     2
+#define AIPS_PACRA_SP7_WIDTH                     1
+#define AIPS_PACRA_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP7_SHIFT))&AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_TP6_MASK                      0x10u
+#define AIPS_PACRA_TP6_SHIFT                     4
+#define AIPS_PACRA_TP6_WIDTH                     1
+#define AIPS_PACRA_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP6_SHIFT))&AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_WP6_MASK                      0x20u
+#define AIPS_PACRA_WP6_SHIFT                     5
+#define AIPS_PACRA_WP6_WIDTH                     1
+#define AIPS_PACRA_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP6_SHIFT))&AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_SP6_MASK                      0x40u
+#define AIPS_PACRA_SP6_SHIFT                     6
+#define AIPS_PACRA_SP6_WIDTH                     1
+#define AIPS_PACRA_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP6_SHIFT))&AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_TP5_MASK                      0x100u
+#define AIPS_PACRA_TP5_SHIFT                     8
+#define AIPS_PACRA_TP5_WIDTH                     1
+#define AIPS_PACRA_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP5_SHIFT))&AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_WP5_MASK                      0x200u
+#define AIPS_PACRA_WP5_SHIFT                     9
+#define AIPS_PACRA_WP5_WIDTH                     1
+#define AIPS_PACRA_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP5_SHIFT))&AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_SP5_MASK                      0x400u
+#define AIPS_PACRA_SP5_SHIFT                     10
+#define AIPS_PACRA_SP5_WIDTH                     1
+#define AIPS_PACRA_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP5_SHIFT))&AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_TP4_MASK                      0x1000u
+#define AIPS_PACRA_TP4_SHIFT                     12
+#define AIPS_PACRA_TP4_WIDTH                     1
+#define AIPS_PACRA_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP4_SHIFT))&AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_WP4_MASK                      0x2000u
+#define AIPS_PACRA_WP4_SHIFT                     13
+#define AIPS_PACRA_WP4_WIDTH                     1
+#define AIPS_PACRA_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP4_SHIFT))&AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_SP4_MASK                      0x4000u
+#define AIPS_PACRA_SP4_SHIFT                     14
+#define AIPS_PACRA_SP4_WIDTH                     1
+#define AIPS_PACRA_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP4_SHIFT))&AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_TP3_MASK                      0x10000u
+#define AIPS_PACRA_TP3_SHIFT                     16
+#define AIPS_PACRA_TP3_WIDTH                     1
+#define AIPS_PACRA_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP3_SHIFT))&AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_WP3_MASK                      0x20000u
+#define AIPS_PACRA_WP3_SHIFT                     17
+#define AIPS_PACRA_WP3_WIDTH                     1
+#define AIPS_PACRA_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP3_SHIFT))&AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_SP3_MASK                      0x40000u
+#define AIPS_PACRA_SP3_SHIFT                     18
+#define AIPS_PACRA_SP3_WIDTH                     1
+#define AIPS_PACRA_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP3_SHIFT))&AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_TP2_MASK                      0x100000u
+#define AIPS_PACRA_TP2_SHIFT                     20
+#define AIPS_PACRA_TP2_WIDTH                     1
+#define AIPS_PACRA_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP2_SHIFT))&AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_WP2_MASK                      0x200000u
+#define AIPS_PACRA_WP2_SHIFT                     21
+#define AIPS_PACRA_WP2_WIDTH                     1
+#define AIPS_PACRA_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP2_SHIFT))&AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_SP2_MASK                      0x400000u
+#define AIPS_PACRA_SP2_SHIFT                     22
+#define AIPS_PACRA_SP2_WIDTH                     1
+#define AIPS_PACRA_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP2_SHIFT))&AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_TP1_MASK                      0x1000000u
+#define AIPS_PACRA_TP1_SHIFT                     24
+#define AIPS_PACRA_TP1_WIDTH                     1
+#define AIPS_PACRA_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP1_SHIFT))&AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_WP1_MASK                      0x2000000u
+#define AIPS_PACRA_WP1_SHIFT                     25
+#define AIPS_PACRA_WP1_WIDTH                     1
+#define AIPS_PACRA_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP1_SHIFT))&AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_SP1_MASK                      0x4000000u
+#define AIPS_PACRA_SP1_SHIFT                     26
+#define AIPS_PACRA_SP1_WIDTH                     1
+#define AIPS_PACRA_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP1_SHIFT))&AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_TP0_MASK                      0x10000000u
+#define AIPS_PACRA_TP0_SHIFT                     28
+#define AIPS_PACRA_TP0_WIDTH                     1
+#define AIPS_PACRA_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP0_SHIFT))&AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_WP0_MASK                      0x20000000u
+#define AIPS_PACRA_WP0_SHIFT                     29
+#define AIPS_PACRA_WP0_WIDTH                     1
+#define AIPS_PACRA_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP0_SHIFT))&AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_SP0_MASK                      0x40000000u
+#define AIPS_PACRA_SP0_SHIFT                     30
+#define AIPS_PACRA_SP0_WIDTH                     1
+#define AIPS_PACRA_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP0_SHIFT))&AIPS_PACRA_SP0_MASK)
+/* PACRB Bit Fields */
+#define AIPS_PACRB_TP7_MASK                      0x1u
+#define AIPS_PACRB_TP7_SHIFT                     0
+#define AIPS_PACRB_TP7_WIDTH                     1
+#define AIPS_PACRB_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP7_SHIFT))&AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_WP7_MASK                      0x2u
+#define AIPS_PACRB_WP7_SHIFT                     1
+#define AIPS_PACRB_WP7_WIDTH                     1
+#define AIPS_PACRB_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP7_SHIFT))&AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_SP7_MASK                      0x4u
+#define AIPS_PACRB_SP7_SHIFT                     2
+#define AIPS_PACRB_SP7_WIDTH                     1
+#define AIPS_PACRB_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP7_SHIFT))&AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_TP6_MASK                      0x10u
+#define AIPS_PACRB_TP6_SHIFT                     4
+#define AIPS_PACRB_TP6_WIDTH                     1
+#define AIPS_PACRB_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP6_SHIFT))&AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_WP6_MASK                      0x20u
+#define AIPS_PACRB_WP6_SHIFT                     5
+#define AIPS_PACRB_WP6_WIDTH                     1
+#define AIPS_PACRB_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP6_SHIFT))&AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_SP6_MASK                      0x40u
+#define AIPS_PACRB_SP6_SHIFT                     6
+#define AIPS_PACRB_SP6_WIDTH                     1
+#define AIPS_PACRB_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP6_SHIFT))&AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_TP5_MASK                      0x100u
+#define AIPS_PACRB_TP5_SHIFT                     8
+#define AIPS_PACRB_TP5_WIDTH                     1
+#define AIPS_PACRB_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP5_SHIFT))&AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_WP5_MASK                      0x200u
+#define AIPS_PACRB_WP5_SHIFT                     9
+#define AIPS_PACRB_WP5_WIDTH                     1
+#define AIPS_PACRB_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP5_SHIFT))&AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_SP5_MASK                      0x400u
+#define AIPS_PACRB_SP5_SHIFT                     10
+#define AIPS_PACRB_SP5_WIDTH                     1
+#define AIPS_PACRB_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP5_SHIFT))&AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_TP4_MASK                      0x1000u
+#define AIPS_PACRB_TP4_SHIFT                     12
+#define AIPS_PACRB_TP4_WIDTH                     1
+#define AIPS_PACRB_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP4_SHIFT))&AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_WP4_MASK                      0x2000u
+#define AIPS_PACRB_WP4_SHIFT                     13
+#define AIPS_PACRB_WP4_WIDTH                     1
+#define AIPS_PACRB_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP4_SHIFT))&AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_SP4_MASK                      0x4000u
+#define AIPS_PACRB_SP4_SHIFT                     14
+#define AIPS_PACRB_SP4_WIDTH                     1
+#define AIPS_PACRB_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP4_SHIFT))&AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_TP3_MASK                      0x10000u
+#define AIPS_PACRB_TP3_SHIFT                     16
+#define AIPS_PACRB_TP3_WIDTH                     1
+#define AIPS_PACRB_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP3_SHIFT))&AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_WP3_MASK                      0x20000u
+#define AIPS_PACRB_WP3_SHIFT                     17
+#define AIPS_PACRB_WP3_WIDTH                     1
+#define AIPS_PACRB_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP3_SHIFT))&AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_SP3_MASK                      0x40000u
+#define AIPS_PACRB_SP3_SHIFT                     18
+#define AIPS_PACRB_SP3_WIDTH                     1
+#define AIPS_PACRB_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP3_SHIFT))&AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_TP2_MASK                      0x100000u
+#define AIPS_PACRB_TP2_SHIFT                     20
+#define AIPS_PACRB_TP2_WIDTH                     1
+#define AIPS_PACRB_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP2_SHIFT))&AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_WP2_MASK                      0x200000u
+#define AIPS_PACRB_WP2_SHIFT                     21
+#define AIPS_PACRB_WP2_WIDTH                     1
+#define AIPS_PACRB_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP2_SHIFT))&AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_SP2_MASK                      0x400000u
+#define AIPS_PACRB_SP2_SHIFT                     22
+#define AIPS_PACRB_SP2_WIDTH                     1
+#define AIPS_PACRB_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP2_SHIFT))&AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_TP1_MASK                      0x1000000u
+#define AIPS_PACRB_TP1_SHIFT                     24
+#define AIPS_PACRB_TP1_WIDTH                     1
+#define AIPS_PACRB_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP1_SHIFT))&AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_WP1_MASK                      0x2000000u
+#define AIPS_PACRB_WP1_SHIFT                     25
+#define AIPS_PACRB_WP1_WIDTH                     1
+#define AIPS_PACRB_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP1_SHIFT))&AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_SP1_MASK                      0x4000000u
+#define AIPS_PACRB_SP1_SHIFT                     26
+#define AIPS_PACRB_SP1_WIDTH                     1
+#define AIPS_PACRB_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP1_SHIFT))&AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_TP0_MASK                      0x10000000u
+#define AIPS_PACRB_TP0_SHIFT                     28
+#define AIPS_PACRB_TP0_WIDTH                     1
+#define AIPS_PACRB_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP0_SHIFT))&AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_WP0_MASK                      0x20000000u
+#define AIPS_PACRB_WP0_SHIFT                     29
+#define AIPS_PACRB_WP0_WIDTH                     1
+#define AIPS_PACRB_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP0_SHIFT))&AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_SP0_MASK                      0x40000000u
+#define AIPS_PACRB_SP0_SHIFT                     30
+#define AIPS_PACRB_SP0_WIDTH                     1
+#define AIPS_PACRB_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP0_SHIFT))&AIPS_PACRB_SP0_MASK)
+/* PACRC Bit Fields */
+#define AIPS_PACRC_TP7_MASK                      0x1u
+#define AIPS_PACRC_TP7_SHIFT                     0
+#define AIPS_PACRC_TP7_WIDTH                     1
+#define AIPS_PACRC_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP7_SHIFT))&AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_WP7_MASK                      0x2u
+#define AIPS_PACRC_WP7_SHIFT                     1
+#define AIPS_PACRC_WP7_WIDTH                     1
+#define AIPS_PACRC_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP7_SHIFT))&AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_SP7_MASK                      0x4u
+#define AIPS_PACRC_SP7_SHIFT                     2
+#define AIPS_PACRC_SP7_WIDTH                     1
+#define AIPS_PACRC_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP7_SHIFT))&AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_TP6_MASK                      0x10u
+#define AIPS_PACRC_TP6_SHIFT                     4
+#define AIPS_PACRC_TP6_WIDTH                     1
+#define AIPS_PACRC_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP6_SHIFT))&AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_WP6_MASK                      0x20u
+#define AIPS_PACRC_WP6_SHIFT                     5
+#define AIPS_PACRC_WP6_WIDTH                     1
+#define AIPS_PACRC_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP6_SHIFT))&AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_SP6_MASK                      0x40u
+#define AIPS_PACRC_SP6_SHIFT                     6
+#define AIPS_PACRC_SP6_WIDTH                     1
+#define AIPS_PACRC_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP6_SHIFT))&AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_TP5_MASK                      0x100u
+#define AIPS_PACRC_TP5_SHIFT                     8
+#define AIPS_PACRC_TP5_WIDTH                     1
+#define AIPS_PACRC_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP5_SHIFT))&AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_WP5_MASK                      0x200u
+#define AIPS_PACRC_WP5_SHIFT                     9
+#define AIPS_PACRC_WP5_WIDTH                     1
+#define AIPS_PACRC_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP5_SHIFT))&AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_SP5_MASK                      0x400u
+#define AIPS_PACRC_SP5_SHIFT                     10
+#define AIPS_PACRC_SP5_WIDTH                     1
+#define AIPS_PACRC_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP5_SHIFT))&AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_TP4_MASK                      0x1000u
+#define AIPS_PACRC_TP4_SHIFT                     12
+#define AIPS_PACRC_TP4_WIDTH                     1
+#define AIPS_PACRC_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP4_SHIFT))&AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_WP4_MASK                      0x2000u
+#define AIPS_PACRC_WP4_SHIFT                     13
+#define AIPS_PACRC_WP4_WIDTH                     1
+#define AIPS_PACRC_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP4_SHIFT))&AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_SP4_MASK                      0x4000u
+#define AIPS_PACRC_SP4_SHIFT                     14
+#define AIPS_PACRC_SP4_WIDTH                     1
+#define AIPS_PACRC_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP4_SHIFT))&AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_TP3_MASK                      0x10000u
+#define AIPS_PACRC_TP3_SHIFT                     16
+#define AIPS_PACRC_TP3_WIDTH                     1
+#define AIPS_PACRC_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP3_SHIFT))&AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_WP3_MASK                      0x20000u
+#define AIPS_PACRC_WP3_SHIFT                     17
+#define AIPS_PACRC_WP3_WIDTH                     1
+#define AIPS_PACRC_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP3_SHIFT))&AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_SP3_MASK                      0x40000u
+#define AIPS_PACRC_SP3_SHIFT                     18
+#define AIPS_PACRC_SP3_WIDTH                     1
+#define AIPS_PACRC_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP3_SHIFT))&AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_TP2_MASK                      0x100000u
+#define AIPS_PACRC_TP2_SHIFT                     20
+#define AIPS_PACRC_TP2_WIDTH                     1
+#define AIPS_PACRC_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP2_SHIFT))&AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_WP2_MASK                      0x200000u
+#define AIPS_PACRC_WP2_SHIFT                     21
+#define AIPS_PACRC_WP2_WIDTH                     1
+#define AIPS_PACRC_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP2_SHIFT))&AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_SP2_MASK                      0x400000u
+#define AIPS_PACRC_SP2_SHIFT                     22
+#define AIPS_PACRC_SP2_WIDTH                     1
+#define AIPS_PACRC_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP2_SHIFT))&AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_TP1_MASK                      0x1000000u
+#define AIPS_PACRC_TP1_SHIFT                     24
+#define AIPS_PACRC_TP1_WIDTH                     1
+#define AIPS_PACRC_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP1_SHIFT))&AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_WP1_MASK                      0x2000000u
+#define AIPS_PACRC_WP1_SHIFT                     25
+#define AIPS_PACRC_WP1_WIDTH                     1
+#define AIPS_PACRC_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP1_SHIFT))&AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_SP1_MASK                      0x4000000u
+#define AIPS_PACRC_SP1_SHIFT                     26
+#define AIPS_PACRC_SP1_WIDTH                     1
+#define AIPS_PACRC_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP1_SHIFT))&AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_TP0_MASK                      0x10000000u
+#define AIPS_PACRC_TP0_SHIFT                     28
+#define AIPS_PACRC_TP0_WIDTH                     1
+#define AIPS_PACRC_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP0_SHIFT))&AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_WP0_MASK                      0x20000000u
+#define AIPS_PACRC_WP0_SHIFT                     29
+#define AIPS_PACRC_WP0_WIDTH                     1
+#define AIPS_PACRC_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP0_SHIFT))&AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_SP0_MASK                      0x40000000u
+#define AIPS_PACRC_SP0_SHIFT                     30
+#define AIPS_PACRC_SP0_WIDTH                     1
+#define AIPS_PACRC_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP0_SHIFT))&AIPS_PACRC_SP0_MASK)
+/* PACRD Bit Fields */
+#define AIPS_PACRD_TP7_MASK                      0x1u
+#define AIPS_PACRD_TP7_SHIFT                     0
+#define AIPS_PACRD_TP7_WIDTH                     1
+#define AIPS_PACRD_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP7_SHIFT))&AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_WP7_MASK                      0x2u
+#define AIPS_PACRD_WP7_SHIFT                     1
+#define AIPS_PACRD_WP7_WIDTH                     1
+#define AIPS_PACRD_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP7_SHIFT))&AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_SP7_MASK                      0x4u
+#define AIPS_PACRD_SP7_SHIFT                     2
+#define AIPS_PACRD_SP7_WIDTH                     1
+#define AIPS_PACRD_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP7_SHIFT))&AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_TP6_MASK                      0x10u
+#define AIPS_PACRD_TP6_SHIFT                     4
+#define AIPS_PACRD_TP6_WIDTH                     1
+#define AIPS_PACRD_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP6_SHIFT))&AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_WP6_MASK                      0x20u
+#define AIPS_PACRD_WP6_SHIFT                     5
+#define AIPS_PACRD_WP6_WIDTH                     1
+#define AIPS_PACRD_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP6_SHIFT))&AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_SP6_MASK                      0x40u
+#define AIPS_PACRD_SP6_SHIFT                     6
+#define AIPS_PACRD_SP6_WIDTH                     1
+#define AIPS_PACRD_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP6_SHIFT))&AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_TP5_MASK                      0x100u
+#define AIPS_PACRD_TP5_SHIFT                     8
+#define AIPS_PACRD_TP5_WIDTH                     1
+#define AIPS_PACRD_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP5_SHIFT))&AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_WP5_MASK                      0x200u
+#define AIPS_PACRD_WP5_SHIFT                     9
+#define AIPS_PACRD_WP5_WIDTH                     1
+#define AIPS_PACRD_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP5_SHIFT))&AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_SP5_MASK                      0x400u
+#define AIPS_PACRD_SP5_SHIFT                     10
+#define AIPS_PACRD_SP5_WIDTH                     1
+#define AIPS_PACRD_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP5_SHIFT))&AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_TP4_MASK                      0x1000u
+#define AIPS_PACRD_TP4_SHIFT                     12
+#define AIPS_PACRD_TP4_WIDTH                     1
+#define AIPS_PACRD_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP4_SHIFT))&AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_WP4_MASK                      0x2000u
+#define AIPS_PACRD_WP4_SHIFT                     13
+#define AIPS_PACRD_WP4_WIDTH                     1
+#define AIPS_PACRD_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP4_SHIFT))&AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_SP4_MASK                      0x4000u
+#define AIPS_PACRD_SP4_SHIFT                     14
+#define AIPS_PACRD_SP4_WIDTH                     1
+#define AIPS_PACRD_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP4_SHIFT))&AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_TP3_MASK                      0x10000u
+#define AIPS_PACRD_TP3_SHIFT                     16
+#define AIPS_PACRD_TP3_WIDTH                     1
+#define AIPS_PACRD_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP3_SHIFT))&AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_WP3_MASK                      0x20000u
+#define AIPS_PACRD_WP3_SHIFT                     17
+#define AIPS_PACRD_WP3_WIDTH                     1
+#define AIPS_PACRD_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP3_SHIFT))&AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_SP3_MASK                      0x40000u
+#define AIPS_PACRD_SP3_SHIFT                     18
+#define AIPS_PACRD_SP3_WIDTH                     1
+#define AIPS_PACRD_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP3_SHIFT))&AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_TP2_MASK                      0x100000u
+#define AIPS_PACRD_TP2_SHIFT                     20
+#define AIPS_PACRD_TP2_WIDTH                     1
+#define AIPS_PACRD_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP2_SHIFT))&AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_WP2_MASK                      0x200000u
+#define AIPS_PACRD_WP2_SHIFT                     21
+#define AIPS_PACRD_WP2_WIDTH                     1
+#define AIPS_PACRD_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP2_SHIFT))&AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_SP2_MASK                      0x400000u
+#define AIPS_PACRD_SP2_SHIFT                     22
+#define AIPS_PACRD_SP2_WIDTH                     1
+#define AIPS_PACRD_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP2_SHIFT))&AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_TP1_MASK                      0x1000000u
+#define AIPS_PACRD_TP1_SHIFT                     24
+#define AIPS_PACRD_TP1_WIDTH                     1
+#define AIPS_PACRD_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP1_SHIFT))&AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_WP1_MASK                      0x2000000u
+#define AIPS_PACRD_WP1_SHIFT                     25
+#define AIPS_PACRD_WP1_WIDTH                     1
+#define AIPS_PACRD_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP1_SHIFT))&AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_SP1_MASK                      0x4000000u
+#define AIPS_PACRD_SP1_SHIFT                     26
+#define AIPS_PACRD_SP1_WIDTH                     1
+#define AIPS_PACRD_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP1_SHIFT))&AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_TP0_MASK                      0x10000000u
+#define AIPS_PACRD_TP0_SHIFT                     28
+#define AIPS_PACRD_TP0_WIDTH                     1
+#define AIPS_PACRD_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP0_SHIFT))&AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_WP0_MASK                      0x20000000u
+#define AIPS_PACRD_WP0_SHIFT                     29
+#define AIPS_PACRD_WP0_WIDTH                     1
+#define AIPS_PACRD_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP0_SHIFT))&AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_SP0_MASK                      0x40000000u
+#define AIPS_PACRD_SP0_SHIFT                     30
+#define AIPS_PACRD_SP0_WIDTH                     1
+#define AIPS_PACRD_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP0_SHIFT))&AIPS_PACRD_SP0_MASK)
+/* PACRE Bit Fields */
+#define AIPS_PACRE_TP7_MASK                      0x1u
+#define AIPS_PACRE_TP7_SHIFT                     0
+#define AIPS_PACRE_TP7_WIDTH                     1
+#define AIPS_PACRE_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP7_SHIFT))&AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_WP7_MASK                      0x2u
+#define AIPS_PACRE_WP7_SHIFT                     1
+#define AIPS_PACRE_WP7_WIDTH                     1
+#define AIPS_PACRE_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP7_SHIFT))&AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_SP7_MASK                      0x4u
+#define AIPS_PACRE_SP7_SHIFT                     2
+#define AIPS_PACRE_SP7_WIDTH                     1
+#define AIPS_PACRE_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP7_SHIFT))&AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_TP6_MASK                      0x10u
+#define AIPS_PACRE_TP6_SHIFT                     4
+#define AIPS_PACRE_TP6_WIDTH                     1
+#define AIPS_PACRE_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP6_SHIFT))&AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_WP6_MASK                      0x20u
+#define AIPS_PACRE_WP6_SHIFT                     5
+#define AIPS_PACRE_WP6_WIDTH                     1
+#define AIPS_PACRE_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP6_SHIFT))&AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_SP6_MASK                      0x40u
+#define AIPS_PACRE_SP6_SHIFT                     6
+#define AIPS_PACRE_SP6_WIDTH                     1
+#define AIPS_PACRE_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP6_SHIFT))&AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_TP5_MASK                      0x100u
+#define AIPS_PACRE_TP5_SHIFT                     8
+#define AIPS_PACRE_TP5_WIDTH                     1
+#define AIPS_PACRE_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP5_SHIFT))&AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_WP5_MASK                      0x200u
+#define AIPS_PACRE_WP5_SHIFT                     9
+#define AIPS_PACRE_WP5_WIDTH                     1
+#define AIPS_PACRE_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP5_SHIFT))&AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_SP5_MASK                      0x400u
+#define AIPS_PACRE_SP5_SHIFT                     10
+#define AIPS_PACRE_SP5_WIDTH                     1
+#define AIPS_PACRE_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP5_SHIFT))&AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_TP4_MASK                      0x1000u
+#define AIPS_PACRE_TP4_SHIFT                     12
+#define AIPS_PACRE_TP4_WIDTH                     1
+#define AIPS_PACRE_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP4_SHIFT))&AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_WP4_MASK                      0x2000u
+#define AIPS_PACRE_WP4_SHIFT                     13
+#define AIPS_PACRE_WP4_WIDTH                     1
+#define AIPS_PACRE_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP4_SHIFT))&AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_SP4_MASK                      0x4000u
+#define AIPS_PACRE_SP4_SHIFT                     14
+#define AIPS_PACRE_SP4_WIDTH                     1
+#define AIPS_PACRE_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP4_SHIFT))&AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_TP3_MASK                      0x10000u
+#define AIPS_PACRE_TP3_SHIFT                     16
+#define AIPS_PACRE_TP3_WIDTH                     1
+#define AIPS_PACRE_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP3_SHIFT))&AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_WP3_MASK                      0x20000u
+#define AIPS_PACRE_WP3_SHIFT                     17
+#define AIPS_PACRE_WP3_WIDTH                     1
+#define AIPS_PACRE_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP3_SHIFT))&AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_SP3_MASK                      0x40000u
+#define AIPS_PACRE_SP3_SHIFT                     18
+#define AIPS_PACRE_SP3_WIDTH                     1
+#define AIPS_PACRE_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP3_SHIFT))&AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_TP2_MASK                      0x100000u
+#define AIPS_PACRE_TP2_SHIFT                     20
+#define AIPS_PACRE_TP2_WIDTH                     1
+#define AIPS_PACRE_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP2_SHIFT))&AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_WP2_MASK                      0x200000u
+#define AIPS_PACRE_WP2_SHIFT                     21
+#define AIPS_PACRE_WP2_WIDTH                     1
+#define AIPS_PACRE_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP2_SHIFT))&AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_SP2_MASK                      0x400000u
+#define AIPS_PACRE_SP2_SHIFT                     22
+#define AIPS_PACRE_SP2_WIDTH                     1
+#define AIPS_PACRE_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP2_SHIFT))&AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_TP1_MASK                      0x1000000u
+#define AIPS_PACRE_TP1_SHIFT                     24
+#define AIPS_PACRE_TP1_WIDTH                     1
+#define AIPS_PACRE_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP1_SHIFT))&AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_WP1_MASK                      0x2000000u
+#define AIPS_PACRE_WP1_SHIFT                     25
+#define AIPS_PACRE_WP1_WIDTH                     1
+#define AIPS_PACRE_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP1_SHIFT))&AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_SP1_MASK                      0x4000000u
+#define AIPS_PACRE_SP1_SHIFT                     26
+#define AIPS_PACRE_SP1_WIDTH                     1
+#define AIPS_PACRE_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP1_SHIFT))&AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_TP0_MASK                      0x10000000u
+#define AIPS_PACRE_TP0_SHIFT                     28
+#define AIPS_PACRE_TP0_WIDTH                     1
+#define AIPS_PACRE_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP0_SHIFT))&AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_WP0_MASK                      0x20000000u
+#define AIPS_PACRE_WP0_SHIFT                     29
+#define AIPS_PACRE_WP0_WIDTH                     1
+#define AIPS_PACRE_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP0_SHIFT))&AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_SP0_MASK                      0x40000000u
+#define AIPS_PACRE_SP0_SHIFT                     30
+#define AIPS_PACRE_SP0_WIDTH                     1
+#define AIPS_PACRE_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP0_SHIFT))&AIPS_PACRE_SP0_MASK)
+/* PACRF Bit Fields */
+#define AIPS_PACRF_TP7_MASK                      0x1u
+#define AIPS_PACRF_TP7_SHIFT                     0
+#define AIPS_PACRF_TP7_WIDTH                     1
+#define AIPS_PACRF_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP7_SHIFT))&AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_WP7_MASK                      0x2u
+#define AIPS_PACRF_WP7_SHIFT                     1
+#define AIPS_PACRF_WP7_WIDTH                     1
+#define AIPS_PACRF_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP7_SHIFT))&AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_SP7_MASK                      0x4u
+#define AIPS_PACRF_SP7_SHIFT                     2
+#define AIPS_PACRF_SP7_WIDTH                     1
+#define AIPS_PACRF_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP7_SHIFT))&AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_TP6_MASK                      0x10u
+#define AIPS_PACRF_TP6_SHIFT                     4
+#define AIPS_PACRF_TP6_WIDTH                     1
+#define AIPS_PACRF_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP6_SHIFT))&AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_WP6_MASK                      0x20u
+#define AIPS_PACRF_WP6_SHIFT                     5
+#define AIPS_PACRF_WP6_WIDTH                     1
+#define AIPS_PACRF_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP6_SHIFT))&AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_SP6_MASK                      0x40u
+#define AIPS_PACRF_SP6_SHIFT                     6
+#define AIPS_PACRF_SP6_WIDTH                     1
+#define AIPS_PACRF_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP6_SHIFT))&AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_TP5_MASK                      0x100u
+#define AIPS_PACRF_TP5_SHIFT                     8
+#define AIPS_PACRF_TP5_WIDTH                     1
+#define AIPS_PACRF_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP5_SHIFT))&AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_WP5_MASK                      0x200u
+#define AIPS_PACRF_WP5_SHIFT                     9
+#define AIPS_PACRF_WP5_WIDTH                     1
+#define AIPS_PACRF_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP5_SHIFT))&AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_SP5_MASK                      0x400u
+#define AIPS_PACRF_SP5_SHIFT                     10
+#define AIPS_PACRF_SP5_WIDTH                     1
+#define AIPS_PACRF_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP5_SHIFT))&AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_TP4_MASK                      0x1000u
+#define AIPS_PACRF_TP4_SHIFT                     12
+#define AIPS_PACRF_TP4_WIDTH                     1
+#define AIPS_PACRF_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP4_SHIFT))&AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_WP4_MASK                      0x2000u
+#define AIPS_PACRF_WP4_SHIFT                     13
+#define AIPS_PACRF_WP4_WIDTH                     1
+#define AIPS_PACRF_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP4_SHIFT))&AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_SP4_MASK                      0x4000u
+#define AIPS_PACRF_SP4_SHIFT                     14
+#define AIPS_PACRF_SP4_WIDTH                     1
+#define AIPS_PACRF_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP4_SHIFT))&AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_TP3_MASK                      0x10000u
+#define AIPS_PACRF_TP3_SHIFT                     16
+#define AIPS_PACRF_TP3_WIDTH                     1
+#define AIPS_PACRF_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP3_SHIFT))&AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_WP3_MASK                      0x20000u
+#define AIPS_PACRF_WP3_SHIFT                     17
+#define AIPS_PACRF_WP3_WIDTH                     1
+#define AIPS_PACRF_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP3_SHIFT))&AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_SP3_MASK                      0x40000u
+#define AIPS_PACRF_SP3_SHIFT                     18
+#define AIPS_PACRF_SP3_WIDTH                     1
+#define AIPS_PACRF_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP3_SHIFT))&AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_TP2_MASK                      0x100000u
+#define AIPS_PACRF_TP2_SHIFT                     20
+#define AIPS_PACRF_TP2_WIDTH                     1
+#define AIPS_PACRF_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP2_SHIFT))&AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_WP2_MASK                      0x200000u
+#define AIPS_PACRF_WP2_SHIFT                     21
+#define AIPS_PACRF_WP2_WIDTH                     1
+#define AIPS_PACRF_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP2_SHIFT))&AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_SP2_MASK                      0x400000u
+#define AIPS_PACRF_SP2_SHIFT                     22
+#define AIPS_PACRF_SP2_WIDTH                     1
+#define AIPS_PACRF_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP2_SHIFT))&AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_TP1_MASK                      0x1000000u
+#define AIPS_PACRF_TP1_SHIFT                     24
+#define AIPS_PACRF_TP1_WIDTH                     1
+#define AIPS_PACRF_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP1_SHIFT))&AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_WP1_MASK                      0x2000000u
+#define AIPS_PACRF_WP1_SHIFT                     25
+#define AIPS_PACRF_WP1_WIDTH                     1
+#define AIPS_PACRF_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP1_SHIFT))&AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_SP1_MASK                      0x4000000u
+#define AIPS_PACRF_SP1_SHIFT                     26
+#define AIPS_PACRF_SP1_WIDTH                     1
+#define AIPS_PACRF_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP1_SHIFT))&AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_TP0_MASK                      0x10000000u
+#define AIPS_PACRF_TP0_SHIFT                     28
+#define AIPS_PACRF_TP0_WIDTH                     1
+#define AIPS_PACRF_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP0_SHIFT))&AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_WP0_MASK                      0x20000000u
+#define AIPS_PACRF_WP0_SHIFT                     29
+#define AIPS_PACRF_WP0_WIDTH                     1
+#define AIPS_PACRF_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP0_SHIFT))&AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_SP0_MASK                      0x40000000u
+#define AIPS_PACRF_SP0_SHIFT                     30
+#define AIPS_PACRF_SP0_WIDTH                     1
+#define AIPS_PACRF_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP0_SHIFT))&AIPS_PACRF_SP0_MASK)
+/* PACRG Bit Fields */
+#define AIPS_PACRG_TP7_MASK                      0x1u
+#define AIPS_PACRG_TP7_SHIFT                     0
+#define AIPS_PACRG_TP7_WIDTH                     1
+#define AIPS_PACRG_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP7_SHIFT))&AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_WP7_MASK                      0x2u
+#define AIPS_PACRG_WP7_SHIFT                     1
+#define AIPS_PACRG_WP7_WIDTH                     1
+#define AIPS_PACRG_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP7_SHIFT))&AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_SP7_MASK                      0x4u
+#define AIPS_PACRG_SP7_SHIFT                     2
+#define AIPS_PACRG_SP7_WIDTH                     1
+#define AIPS_PACRG_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP7_SHIFT))&AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_TP6_MASK                      0x10u
+#define AIPS_PACRG_TP6_SHIFT                     4
+#define AIPS_PACRG_TP6_WIDTH                     1
+#define AIPS_PACRG_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP6_SHIFT))&AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_WP6_MASK                      0x20u
+#define AIPS_PACRG_WP6_SHIFT                     5
+#define AIPS_PACRG_WP6_WIDTH                     1
+#define AIPS_PACRG_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP6_SHIFT))&AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_SP6_MASK                      0x40u
+#define AIPS_PACRG_SP6_SHIFT                     6
+#define AIPS_PACRG_SP6_WIDTH                     1
+#define AIPS_PACRG_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP6_SHIFT))&AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_TP5_MASK                      0x100u
+#define AIPS_PACRG_TP5_SHIFT                     8
+#define AIPS_PACRG_TP5_WIDTH                     1
+#define AIPS_PACRG_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP5_SHIFT))&AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_WP5_MASK                      0x200u
+#define AIPS_PACRG_WP5_SHIFT                     9
+#define AIPS_PACRG_WP5_WIDTH                     1
+#define AIPS_PACRG_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP5_SHIFT))&AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_SP5_MASK                      0x400u
+#define AIPS_PACRG_SP5_SHIFT                     10
+#define AIPS_PACRG_SP5_WIDTH                     1
+#define AIPS_PACRG_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP5_SHIFT))&AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_TP4_MASK                      0x1000u
+#define AIPS_PACRG_TP4_SHIFT                     12
+#define AIPS_PACRG_TP4_WIDTH                     1
+#define AIPS_PACRG_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP4_SHIFT))&AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_WP4_MASK                      0x2000u
+#define AIPS_PACRG_WP4_SHIFT                     13
+#define AIPS_PACRG_WP4_WIDTH                     1
+#define AIPS_PACRG_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP4_SHIFT))&AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_SP4_MASK                      0x4000u
+#define AIPS_PACRG_SP4_SHIFT                     14
+#define AIPS_PACRG_SP4_WIDTH                     1
+#define AIPS_PACRG_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP4_SHIFT))&AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_TP3_MASK                      0x10000u
+#define AIPS_PACRG_TP3_SHIFT                     16
+#define AIPS_PACRG_TP3_WIDTH                     1
+#define AIPS_PACRG_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP3_SHIFT))&AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_WP3_MASK                      0x20000u
+#define AIPS_PACRG_WP3_SHIFT                     17
+#define AIPS_PACRG_WP3_WIDTH                     1
+#define AIPS_PACRG_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP3_SHIFT))&AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_SP3_MASK                      0x40000u
+#define AIPS_PACRG_SP3_SHIFT                     18
+#define AIPS_PACRG_SP3_WIDTH                     1
+#define AIPS_PACRG_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP3_SHIFT))&AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_TP2_MASK                      0x100000u
+#define AIPS_PACRG_TP2_SHIFT                     20
+#define AIPS_PACRG_TP2_WIDTH                     1
+#define AIPS_PACRG_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP2_SHIFT))&AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_WP2_MASK                      0x200000u
+#define AIPS_PACRG_WP2_SHIFT                     21
+#define AIPS_PACRG_WP2_WIDTH                     1
+#define AIPS_PACRG_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP2_SHIFT))&AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_SP2_MASK                      0x400000u
+#define AIPS_PACRG_SP2_SHIFT                     22
+#define AIPS_PACRG_SP2_WIDTH                     1
+#define AIPS_PACRG_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP2_SHIFT))&AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_TP1_MASK                      0x1000000u
+#define AIPS_PACRG_TP1_SHIFT                     24
+#define AIPS_PACRG_TP1_WIDTH                     1
+#define AIPS_PACRG_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP1_SHIFT))&AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_WP1_MASK                      0x2000000u
+#define AIPS_PACRG_WP1_SHIFT                     25
+#define AIPS_PACRG_WP1_WIDTH                     1
+#define AIPS_PACRG_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP1_SHIFT))&AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_SP1_MASK                      0x4000000u
+#define AIPS_PACRG_SP1_SHIFT                     26
+#define AIPS_PACRG_SP1_WIDTH                     1
+#define AIPS_PACRG_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP1_SHIFT))&AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_TP0_MASK                      0x10000000u
+#define AIPS_PACRG_TP0_SHIFT                     28
+#define AIPS_PACRG_TP0_WIDTH                     1
+#define AIPS_PACRG_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP0_SHIFT))&AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_WP0_MASK                      0x20000000u
+#define AIPS_PACRG_WP0_SHIFT                     29
+#define AIPS_PACRG_WP0_WIDTH                     1
+#define AIPS_PACRG_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP0_SHIFT))&AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_SP0_MASK                      0x40000000u
+#define AIPS_PACRG_SP0_SHIFT                     30
+#define AIPS_PACRG_SP0_WIDTH                     1
+#define AIPS_PACRG_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP0_SHIFT))&AIPS_PACRG_SP0_MASK)
+/* PACRH Bit Fields */
+#define AIPS_PACRH_TP7_MASK                      0x1u
+#define AIPS_PACRH_TP7_SHIFT                     0
+#define AIPS_PACRH_TP7_WIDTH                     1
+#define AIPS_PACRH_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP7_SHIFT))&AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_WP7_MASK                      0x2u
+#define AIPS_PACRH_WP7_SHIFT                     1
+#define AIPS_PACRH_WP7_WIDTH                     1
+#define AIPS_PACRH_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP7_SHIFT))&AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_SP7_MASK                      0x4u
+#define AIPS_PACRH_SP7_SHIFT                     2
+#define AIPS_PACRH_SP7_WIDTH                     1
+#define AIPS_PACRH_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP7_SHIFT))&AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_TP6_MASK                      0x10u
+#define AIPS_PACRH_TP6_SHIFT                     4
+#define AIPS_PACRH_TP6_WIDTH                     1
+#define AIPS_PACRH_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP6_SHIFT))&AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_WP6_MASK                      0x20u
+#define AIPS_PACRH_WP6_SHIFT                     5
+#define AIPS_PACRH_WP6_WIDTH                     1
+#define AIPS_PACRH_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP6_SHIFT))&AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_SP6_MASK                      0x40u
+#define AIPS_PACRH_SP6_SHIFT                     6
+#define AIPS_PACRH_SP6_WIDTH                     1
+#define AIPS_PACRH_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP6_SHIFT))&AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_TP5_MASK                      0x100u
+#define AIPS_PACRH_TP5_SHIFT                     8
+#define AIPS_PACRH_TP5_WIDTH                     1
+#define AIPS_PACRH_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP5_SHIFT))&AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_WP5_MASK                      0x200u
+#define AIPS_PACRH_WP5_SHIFT                     9
+#define AIPS_PACRH_WP5_WIDTH                     1
+#define AIPS_PACRH_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP5_SHIFT))&AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_SP5_MASK                      0x400u
+#define AIPS_PACRH_SP5_SHIFT                     10
+#define AIPS_PACRH_SP5_WIDTH                     1
+#define AIPS_PACRH_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP5_SHIFT))&AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_TP4_MASK                      0x1000u
+#define AIPS_PACRH_TP4_SHIFT                     12
+#define AIPS_PACRH_TP4_WIDTH                     1
+#define AIPS_PACRH_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP4_SHIFT))&AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_WP4_MASK                      0x2000u
+#define AIPS_PACRH_WP4_SHIFT                     13
+#define AIPS_PACRH_WP4_WIDTH                     1
+#define AIPS_PACRH_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP4_SHIFT))&AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_SP4_MASK                      0x4000u
+#define AIPS_PACRH_SP4_SHIFT                     14
+#define AIPS_PACRH_SP4_WIDTH                     1
+#define AIPS_PACRH_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP4_SHIFT))&AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_TP3_MASK                      0x10000u
+#define AIPS_PACRH_TP3_SHIFT                     16
+#define AIPS_PACRH_TP3_WIDTH                     1
+#define AIPS_PACRH_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP3_SHIFT))&AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_WP3_MASK                      0x20000u
+#define AIPS_PACRH_WP3_SHIFT                     17
+#define AIPS_PACRH_WP3_WIDTH                     1
+#define AIPS_PACRH_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP3_SHIFT))&AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_SP3_MASK                      0x40000u
+#define AIPS_PACRH_SP3_SHIFT                     18
+#define AIPS_PACRH_SP3_WIDTH                     1
+#define AIPS_PACRH_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP3_SHIFT))&AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_TP2_MASK                      0x100000u
+#define AIPS_PACRH_TP2_SHIFT                     20
+#define AIPS_PACRH_TP2_WIDTH                     1
+#define AIPS_PACRH_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP2_SHIFT))&AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_WP2_MASK                      0x200000u
+#define AIPS_PACRH_WP2_SHIFT                     21
+#define AIPS_PACRH_WP2_WIDTH                     1
+#define AIPS_PACRH_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP2_SHIFT))&AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_SP2_MASK                      0x400000u
+#define AIPS_PACRH_SP2_SHIFT                     22
+#define AIPS_PACRH_SP2_WIDTH                     1
+#define AIPS_PACRH_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP2_SHIFT))&AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_TP1_MASK                      0x1000000u
+#define AIPS_PACRH_TP1_SHIFT                     24
+#define AIPS_PACRH_TP1_WIDTH                     1
+#define AIPS_PACRH_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP1_SHIFT))&AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_WP1_MASK                      0x2000000u
+#define AIPS_PACRH_WP1_SHIFT                     25
+#define AIPS_PACRH_WP1_WIDTH                     1
+#define AIPS_PACRH_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP1_SHIFT))&AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_SP1_MASK                      0x4000000u
+#define AIPS_PACRH_SP1_SHIFT                     26
+#define AIPS_PACRH_SP1_WIDTH                     1
+#define AIPS_PACRH_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP1_SHIFT))&AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_TP0_MASK                      0x10000000u
+#define AIPS_PACRH_TP0_SHIFT                     28
+#define AIPS_PACRH_TP0_WIDTH                     1
+#define AIPS_PACRH_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP0_SHIFT))&AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_WP0_MASK                      0x20000000u
+#define AIPS_PACRH_WP0_SHIFT                     29
+#define AIPS_PACRH_WP0_WIDTH                     1
+#define AIPS_PACRH_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP0_SHIFT))&AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_SP0_MASK                      0x40000000u
+#define AIPS_PACRH_SP0_SHIFT                     30
+#define AIPS_PACRH_SP0_WIDTH                     1
+#define AIPS_PACRH_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP0_SHIFT))&AIPS_PACRH_SP0_MASK)
+/* PACRI Bit Fields */
+#define AIPS_PACRI_TP7_MASK                      0x1u
+#define AIPS_PACRI_TP7_SHIFT                     0
+#define AIPS_PACRI_TP7_WIDTH                     1
+#define AIPS_PACRI_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP7_SHIFT))&AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_WP7_MASK                      0x2u
+#define AIPS_PACRI_WP7_SHIFT                     1
+#define AIPS_PACRI_WP7_WIDTH                     1
+#define AIPS_PACRI_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP7_SHIFT))&AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_SP7_MASK                      0x4u
+#define AIPS_PACRI_SP7_SHIFT                     2
+#define AIPS_PACRI_SP7_WIDTH                     1
+#define AIPS_PACRI_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP7_SHIFT))&AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_TP6_MASK                      0x10u
+#define AIPS_PACRI_TP6_SHIFT                     4
+#define AIPS_PACRI_TP6_WIDTH                     1
+#define AIPS_PACRI_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP6_SHIFT))&AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_WP6_MASK                      0x20u
+#define AIPS_PACRI_WP6_SHIFT                     5
+#define AIPS_PACRI_WP6_WIDTH                     1
+#define AIPS_PACRI_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP6_SHIFT))&AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_SP6_MASK                      0x40u
+#define AIPS_PACRI_SP6_SHIFT                     6
+#define AIPS_PACRI_SP6_WIDTH                     1
+#define AIPS_PACRI_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP6_SHIFT))&AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_TP5_MASK                      0x100u
+#define AIPS_PACRI_TP5_SHIFT                     8
+#define AIPS_PACRI_TP5_WIDTH                     1
+#define AIPS_PACRI_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP5_SHIFT))&AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_WP5_MASK                      0x200u
+#define AIPS_PACRI_WP5_SHIFT                     9
+#define AIPS_PACRI_WP5_WIDTH                     1
+#define AIPS_PACRI_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP5_SHIFT))&AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_SP5_MASK                      0x400u
+#define AIPS_PACRI_SP5_SHIFT                     10
+#define AIPS_PACRI_SP5_WIDTH                     1
+#define AIPS_PACRI_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP5_SHIFT))&AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_TP4_MASK                      0x1000u
+#define AIPS_PACRI_TP4_SHIFT                     12
+#define AIPS_PACRI_TP4_WIDTH                     1
+#define AIPS_PACRI_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP4_SHIFT))&AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_WP4_MASK                      0x2000u
+#define AIPS_PACRI_WP4_SHIFT                     13
+#define AIPS_PACRI_WP4_WIDTH                     1
+#define AIPS_PACRI_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP4_SHIFT))&AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_SP4_MASK                      0x4000u
+#define AIPS_PACRI_SP4_SHIFT                     14
+#define AIPS_PACRI_SP4_WIDTH                     1
+#define AIPS_PACRI_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP4_SHIFT))&AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_TP3_MASK                      0x10000u
+#define AIPS_PACRI_TP3_SHIFT                     16
+#define AIPS_PACRI_TP3_WIDTH                     1
+#define AIPS_PACRI_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP3_SHIFT))&AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_WP3_MASK                      0x20000u
+#define AIPS_PACRI_WP3_SHIFT                     17
+#define AIPS_PACRI_WP3_WIDTH                     1
+#define AIPS_PACRI_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP3_SHIFT))&AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_SP3_MASK                      0x40000u
+#define AIPS_PACRI_SP3_SHIFT                     18
+#define AIPS_PACRI_SP3_WIDTH                     1
+#define AIPS_PACRI_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP3_SHIFT))&AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_TP2_MASK                      0x100000u
+#define AIPS_PACRI_TP2_SHIFT                     20
+#define AIPS_PACRI_TP2_WIDTH                     1
+#define AIPS_PACRI_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP2_SHIFT))&AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_WP2_MASK                      0x200000u
+#define AIPS_PACRI_WP2_SHIFT                     21
+#define AIPS_PACRI_WP2_WIDTH                     1
+#define AIPS_PACRI_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP2_SHIFT))&AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_SP2_MASK                      0x400000u
+#define AIPS_PACRI_SP2_SHIFT                     22
+#define AIPS_PACRI_SP2_WIDTH                     1
+#define AIPS_PACRI_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP2_SHIFT))&AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_TP1_MASK                      0x1000000u
+#define AIPS_PACRI_TP1_SHIFT                     24
+#define AIPS_PACRI_TP1_WIDTH                     1
+#define AIPS_PACRI_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP1_SHIFT))&AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_WP1_MASK                      0x2000000u
+#define AIPS_PACRI_WP1_SHIFT                     25
+#define AIPS_PACRI_WP1_WIDTH                     1
+#define AIPS_PACRI_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP1_SHIFT))&AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_SP1_MASK                      0x4000000u
+#define AIPS_PACRI_SP1_SHIFT                     26
+#define AIPS_PACRI_SP1_WIDTH                     1
+#define AIPS_PACRI_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP1_SHIFT))&AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_TP0_MASK                      0x10000000u
+#define AIPS_PACRI_TP0_SHIFT                     28
+#define AIPS_PACRI_TP0_WIDTH                     1
+#define AIPS_PACRI_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP0_SHIFT))&AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_WP0_MASK                      0x20000000u
+#define AIPS_PACRI_WP0_SHIFT                     29
+#define AIPS_PACRI_WP0_WIDTH                     1
+#define AIPS_PACRI_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP0_SHIFT))&AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_SP0_MASK                      0x40000000u
+#define AIPS_PACRI_SP0_SHIFT                     30
+#define AIPS_PACRI_SP0_WIDTH                     1
+#define AIPS_PACRI_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP0_SHIFT))&AIPS_PACRI_SP0_MASK)
+/* PACRJ Bit Fields */
+#define AIPS_PACRJ_TP7_MASK                      0x1u
+#define AIPS_PACRJ_TP7_SHIFT                     0
+#define AIPS_PACRJ_TP7_WIDTH                     1
+#define AIPS_PACRJ_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP7_SHIFT))&AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_WP7_MASK                      0x2u
+#define AIPS_PACRJ_WP7_SHIFT                     1
+#define AIPS_PACRJ_WP7_WIDTH                     1
+#define AIPS_PACRJ_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP7_SHIFT))&AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_SP7_MASK                      0x4u
+#define AIPS_PACRJ_SP7_SHIFT                     2
+#define AIPS_PACRJ_SP7_WIDTH                     1
+#define AIPS_PACRJ_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP7_SHIFT))&AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_TP6_MASK                      0x10u
+#define AIPS_PACRJ_TP6_SHIFT                     4
+#define AIPS_PACRJ_TP6_WIDTH                     1
+#define AIPS_PACRJ_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP6_SHIFT))&AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_WP6_MASK                      0x20u
+#define AIPS_PACRJ_WP6_SHIFT                     5
+#define AIPS_PACRJ_WP6_WIDTH                     1
+#define AIPS_PACRJ_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP6_SHIFT))&AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_SP6_MASK                      0x40u
+#define AIPS_PACRJ_SP6_SHIFT                     6
+#define AIPS_PACRJ_SP6_WIDTH                     1
+#define AIPS_PACRJ_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP6_SHIFT))&AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_TP5_MASK                      0x100u
+#define AIPS_PACRJ_TP5_SHIFT                     8
+#define AIPS_PACRJ_TP5_WIDTH                     1
+#define AIPS_PACRJ_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP5_SHIFT))&AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_WP5_MASK                      0x200u
+#define AIPS_PACRJ_WP5_SHIFT                     9
+#define AIPS_PACRJ_WP5_WIDTH                     1
+#define AIPS_PACRJ_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP5_SHIFT))&AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_SP5_MASK                      0x400u
+#define AIPS_PACRJ_SP5_SHIFT                     10
+#define AIPS_PACRJ_SP5_WIDTH                     1
+#define AIPS_PACRJ_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP5_SHIFT))&AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_TP4_MASK                      0x1000u
+#define AIPS_PACRJ_TP4_SHIFT                     12
+#define AIPS_PACRJ_TP4_WIDTH                     1
+#define AIPS_PACRJ_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP4_SHIFT))&AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_WP4_MASK                      0x2000u
+#define AIPS_PACRJ_WP4_SHIFT                     13
+#define AIPS_PACRJ_WP4_WIDTH                     1
+#define AIPS_PACRJ_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP4_SHIFT))&AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_SP4_MASK                      0x4000u
+#define AIPS_PACRJ_SP4_SHIFT                     14
+#define AIPS_PACRJ_SP4_WIDTH                     1
+#define AIPS_PACRJ_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP4_SHIFT))&AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_TP3_MASK                      0x10000u
+#define AIPS_PACRJ_TP3_SHIFT                     16
+#define AIPS_PACRJ_TP3_WIDTH                     1
+#define AIPS_PACRJ_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP3_SHIFT))&AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_WP3_MASK                      0x20000u
+#define AIPS_PACRJ_WP3_SHIFT                     17
+#define AIPS_PACRJ_WP3_WIDTH                     1
+#define AIPS_PACRJ_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP3_SHIFT))&AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_SP3_MASK                      0x40000u
+#define AIPS_PACRJ_SP3_SHIFT                     18
+#define AIPS_PACRJ_SP3_WIDTH                     1
+#define AIPS_PACRJ_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP3_SHIFT))&AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_TP2_MASK                      0x100000u
+#define AIPS_PACRJ_TP2_SHIFT                     20
+#define AIPS_PACRJ_TP2_WIDTH                     1
+#define AIPS_PACRJ_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP2_SHIFT))&AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_WP2_MASK                      0x200000u
+#define AIPS_PACRJ_WP2_SHIFT                     21
+#define AIPS_PACRJ_WP2_WIDTH                     1
+#define AIPS_PACRJ_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP2_SHIFT))&AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_SP2_MASK                      0x400000u
+#define AIPS_PACRJ_SP2_SHIFT                     22
+#define AIPS_PACRJ_SP2_WIDTH                     1
+#define AIPS_PACRJ_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP2_SHIFT))&AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_TP1_MASK                      0x1000000u
+#define AIPS_PACRJ_TP1_SHIFT                     24
+#define AIPS_PACRJ_TP1_WIDTH                     1
+#define AIPS_PACRJ_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP1_SHIFT))&AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_WP1_MASK                      0x2000000u
+#define AIPS_PACRJ_WP1_SHIFT                     25
+#define AIPS_PACRJ_WP1_WIDTH                     1
+#define AIPS_PACRJ_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP1_SHIFT))&AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_SP1_MASK                      0x4000000u
+#define AIPS_PACRJ_SP1_SHIFT                     26
+#define AIPS_PACRJ_SP1_WIDTH                     1
+#define AIPS_PACRJ_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP1_SHIFT))&AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_TP0_MASK                      0x10000000u
+#define AIPS_PACRJ_TP0_SHIFT                     28
+#define AIPS_PACRJ_TP0_WIDTH                     1
+#define AIPS_PACRJ_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP0_SHIFT))&AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_WP0_MASK                      0x20000000u
+#define AIPS_PACRJ_WP0_SHIFT                     29
+#define AIPS_PACRJ_WP0_WIDTH                     1
+#define AIPS_PACRJ_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP0_SHIFT))&AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_SP0_MASK                      0x40000000u
+#define AIPS_PACRJ_SP0_SHIFT                     30
+#define AIPS_PACRJ_SP0_WIDTH                     1
+#define AIPS_PACRJ_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP0_SHIFT))&AIPS_PACRJ_SP0_MASK)
+/* PACRK Bit Fields */
+#define AIPS_PACRK_TP7_MASK                      0x1u
+#define AIPS_PACRK_TP7_SHIFT                     0
+#define AIPS_PACRK_TP7_WIDTH                     1
+#define AIPS_PACRK_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP7_SHIFT))&AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_WP7_MASK                      0x2u
+#define AIPS_PACRK_WP7_SHIFT                     1
+#define AIPS_PACRK_WP7_WIDTH                     1
+#define AIPS_PACRK_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP7_SHIFT))&AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_SP7_MASK                      0x4u
+#define AIPS_PACRK_SP7_SHIFT                     2
+#define AIPS_PACRK_SP7_WIDTH                     1
+#define AIPS_PACRK_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP7_SHIFT))&AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_TP6_MASK                      0x10u
+#define AIPS_PACRK_TP6_SHIFT                     4
+#define AIPS_PACRK_TP6_WIDTH                     1
+#define AIPS_PACRK_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP6_SHIFT))&AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_WP6_MASK                      0x20u
+#define AIPS_PACRK_WP6_SHIFT                     5
+#define AIPS_PACRK_WP6_WIDTH                     1
+#define AIPS_PACRK_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP6_SHIFT))&AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_SP6_MASK                      0x40u
+#define AIPS_PACRK_SP6_SHIFT                     6
+#define AIPS_PACRK_SP6_WIDTH                     1
+#define AIPS_PACRK_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP6_SHIFT))&AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_TP5_MASK                      0x100u
+#define AIPS_PACRK_TP5_SHIFT                     8
+#define AIPS_PACRK_TP5_WIDTH                     1
+#define AIPS_PACRK_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP5_SHIFT))&AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_WP5_MASK                      0x200u
+#define AIPS_PACRK_WP5_SHIFT                     9
+#define AIPS_PACRK_WP5_WIDTH                     1
+#define AIPS_PACRK_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP5_SHIFT))&AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_SP5_MASK                      0x400u
+#define AIPS_PACRK_SP5_SHIFT                     10
+#define AIPS_PACRK_SP5_WIDTH                     1
+#define AIPS_PACRK_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP5_SHIFT))&AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_TP4_MASK                      0x1000u
+#define AIPS_PACRK_TP4_SHIFT                     12
+#define AIPS_PACRK_TP4_WIDTH                     1
+#define AIPS_PACRK_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP4_SHIFT))&AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_WP4_MASK                      0x2000u
+#define AIPS_PACRK_WP4_SHIFT                     13
+#define AIPS_PACRK_WP4_WIDTH                     1
+#define AIPS_PACRK_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP4_SHIFT))&AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_SP4_MASK                      0x4000u
+#define AIPS_PACRK_SP4_SHIFT                     14
+#define AIPS_PACRK_SP4_WIDTH                     1
+#define AIPS_PACRK_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP4_SHIFT))&AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_TP3_MASK                      0x10000u
+#define AIPS_PACRK_TP3_SHIFT                     16
+#define AIPS_PACRK_TP3_WIDTH                     1
+#define AIPS_PACRK_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP3_SHIFT))&AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_WP3_MASK                      0x20000u
+#define AIPS_PACRK_WP3_SHIFT                     17
+#define AIPS_PACRK_WP3_WIDTH                     1
+#define AIPS_PACRK_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP3_SHIFT))&AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_SP3_MASK                      0x40000u
+#define AIPS_PACRK_SP3_SHIFT                     18
+#define AIPS_PACRK_SP3_WIDTH                     1
+#define AIPS_PACRK_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP3_SHIFT))&AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_TP2_MASK                      0x100000u
+#define AIPS_PACRK_TP2_SHIFT                     20
+#define AIPS_PACRK_TP2_WIDTH                     1
+#define AIPS_PACRK_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP2_SHIFT))&AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_WP2_MASK                      0x200000u
+#define AIPS_PACRK_WP2_SHIFT                     21
+#define AIPS_PACRK_WP2_WIDTH                     1
+#define AIPS_PACRK_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP2_SHIFT))&AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_SP2_MASK                      0x400000u
+#define AIPS_PACRK_SP2_SHIFT                     22
+#define AIPS_PACRK_SP2_WIDTH                     1
+#define AIPS_PACRK_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP2_SHIFT))&AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_TP1_MASK                      0x1000000u
+#define AIPS_PACRK_TP1_SHIFT                     24
+#define AIPS_PACRK_TP1_WIDTH                     1
+#define AIPS_PACRK_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP1_SHIFT))&AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_WP1_MASK                      0x2000000u
+#define AIPS_PACRK_WP1_SHIFT                     25
+#define AIPS_PACRK_WP1_WIDTH                     1
+#define AIPS_PACRK_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP1_SHIFT))&AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_SP1_MASK                      0x4000000u
+#define AIPS_PACRK_SP1_SHIFT                     26
+#define AIPS_PACRK_SP1_WIDTH                     1
+#define AIPS_PACRK_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP1_SHIFT))&AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_TP0_MASK                      0x10000000u
+#define AIPS_PACRK_TP0_SHIFT                     28
+#define AIPS_PACRK_TP0_WIDTH                     1
+#define AIPS_PACRK_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP0_SHIFT))&AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_WP0_MASK                      0x20000000u
+#define AIPS_PACRK_WP0_SHIFT                     29
+#define AIPS_PACRK_WP0_WIDTH                     1
+#define AIPS_PACRK_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP0_SHIFT))&AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_SP0_MASK                      0x40000000u
+#define AIPS_PACRK_SP0_SHIFT                     30
+#define AIPS_PACRK_SP0_WIDTH                     1
+#define AIPS_PACRK_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP0_SHIFT))&AIPS_PACRK_SP0_MASK)
+/* PACRL Bit Fields */
+#define AIPS_PACRL_TP7_MASK                      0x1u
+#define AIPS_PACRL_TP7_SHIFT                     0
+#define AIPS_PACRL_TP7_WIDTH                     1
+#define AIPS_PACRL_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP7_SHIFT))&AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_WP7_MASK                      0x2u
+#define AIPS_PACRL_WP7_SHIFT                     1
+#define AIPS_PACRL_WP7_WIDTH                     1
+#define AIPS_PACRL_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP7_SHIFT))&AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_SP7_MASK                      0x4u
+#define AIPS_PACRL_SP7_SHIFT                     2
+#define AIPS_PACRL_SP7_WIDTH                     1
+#define AIPS_PACRL_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP7_SHIFT))&AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_TP6_MASK                      0x10u
+#define AIPS_PACRL_TP6_SHIFT                     4
+#define AIPS_PACRL_TP6_WIDTH                     1
+#define AIPS_PACRL_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP6_SHIFT))&AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_WP6_MASK                      0x20u
+#define AIPS_PACRL_WP6_SHIFT                     5
+#define AIPS_PACRL_WP6_WIDTH                     1
+#define AIPS_PACRL_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP6_SHIFT))&AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_SP6_MASK                      0x40u
+#define AIPS_PACRL_SP6_SHIFT                     6
+#define AIPS_PACRL_SP6_WIDTH                     1
+#define AIPS_PACRL_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP6_SHIFT))&AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_TP5_MASK                      0x100u
+#define AIPS_PACRL_TP5_SHIFT                     8
+#define AIPS_PACRL_TP5_WIDTH                     1
+#define AIPS_PACRL_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP5_SHIFT))&AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_WP5_MASK                      0x200u
+#define AIPS_PACRL_WP5_SHIFT                     9
+#define AIPS_PACRL_WP5_WIDTH                     1
+#define AIPS_PACRL_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP5_SHIFT))&AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_SP5_MASK                      0x400u
+#define AIPS_PACRL_SP5_SHIFT                     10
+#define AIPS_PACRL_SP5_WIDTH                     1
+#define AIPS_PACRL_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP5_SHIFT))&AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_TP4_MASK                      0x1000u
+#define AIPS_PACRL_TP4_SHIFT                     12
+#define AIPS_PACRL_TP4_WIDTH                     1
+#define AIPS_PACRL_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP4_SHIFT))&AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_WP4_MASK                      0x2000u
+#define AIPS_PACRL_WP4_SHIFT                     13
+#define AIPS_PACRL_WP4_WIDTH                     1
+#define AIPS_PACRL_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP4_SHIFT))&AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_SP4_MASK                      0x4000u
+#define AIPS_PACRL_SP4_SHIFT                     14
+#define AIPS_PACRL_SP4_WIDTH                     1
+#define AIPS_PACRL_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP4_SHIFT))&AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_TP3_MASK                      0x10000u
+#define AIPS_PACRL_TP3_SHIFT                     16
+#define AIPS_PACRL_TP3_WIDTH                     1
+#define AIPS_PACRL_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP3_SHIFT))&AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_WP3_MASK                      0x20000u
+#define AIPS_PACRL_WP3_SHIFT                     17
+#define AIPS_PACRL_WP3_WIDTH                     1
+#define AIPS_PACRL_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP3_SHIFT))&AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_SP3_MASK                      0x40000u
+#define AIPS_PACRL_SP3_SHIFT                     18
+#define AIPS_PACRL_SP3_WIDTH                     1
+#define AIPS_PACRL_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP3_SHIFT))&AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_TP2_MASK                      0x100000u
+#define AIPS_PACRL_TP2_SHIFT                     20
+#define AIPS_PACRL_TP2_WIDTH                     1
+#define AIPS_PACRL_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP2_SHIFT))&AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_WP2_MASK                      0x200000u
+#define AIPS_PACRL_WP2_SHIFT                     21
+#define AIPS_PACRL_WP2_WIDTH                     1
+#define AIPS_PACRL_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP2_SHIFT))&AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_SP2_MASK                      0x400000u
+#define AIPS_PACRL_SP2_SHIFT                     22
+#define AIPS_PACRL_SP2_WIDTH                     1
+#define AIPS_PACRL_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP2_SHIFT))&AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_TP1_MASK                      0x1000000u
+#define AIPS_PACRL_TP1_SHIFT                     24
+#define AIPS_PACRL_TP1_WIDTH                     1
+#define AIPS_PACRL_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP1_SHIFT))&AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_WP1_MASK                      0x2000000u
+#define AIPS_PACRL_WP1_SHIFT                     25
+#define AIPS_PACRL_WP1_WIDTH                     1
+#define AIPS_PACRL_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP1_SHIFT))&AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_SP1_MASK                      0x4000000u
+#define AIPS_PACRL_SP1_SHIFT                     26
+#define AIPS_PACRL_SP1_WIDTH                     1
+#define AIPS_PACRL_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP1_SHIFT))&AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_TP0_MASK                      0x10000000u
+#define AIPS_PACRL_TP0_SHIFT                     28
+#define AIPS_PACRL_TP0_WIDTH                     1
+#define AIPS_PACRL_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP0_SHIFT))&AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_WP0_MASK                      0x20000000u
+#define AIPS_PACRL_WP0_SHIFT                     29
+#define AIPS_PACRL_WP0_WIDTH                     1
+#define AIPS_PACRL_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP0_SHIFT))&AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_SP0_MASK                      0x40000000u
+#define AIPS_PACRL_SP0_SHIFT                     30
+#define AIPS_PACRL_SP0_WIDTH                     1
+#define AIPS_PACRL_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP0_SHIFT))&AIPS_PACRL_SP0_MASK)
+/* PACRM Bit Fields */
+#define AIPS_PACRM_TP7_MASK                      0x1u
+#define AIPS_PACRM_TP7_SHIFT                     0
+#define AIPS_PACRM_TP7_WIDTH                     1
+#define AIPS_PACRM_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP7_SHIFT))&AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_WP7_MASK                      0x2u
+#define AIPS_PACRM_WP7_SHIFT                     1
+#define AIPS_PACRM_WP7_WIDTH                     1
+#define AIPS_PACRM_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP7_SHIFT))&AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_SP7_MASK                      0x4u
+#define AIPS_PACRM_SP7_SHIFT                     2
+#define AIPS_PACRM_SP7_WIDTH                     1
+#define AIPS_PACRM_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP7_SHIFT))&AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_TP6_MASK                      0x10u
+#define AIPS_PACRM_TP6_SHIFT                     4
+#define AIPS_PACRM_TP6_WIDTH                     1
+#define AIPS_PACRM_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP6_SHIFT))&AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_WP6_MASK                      0x20u
+#define AIPS_PACRM_WP6_SHIFT                     5
+#define AIPS_PACRM_WP6_WIDTH                     1
+#define AIPS_PACRM_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP6_SHIFT))&AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_SP6_MASK                      0x40u
+#define AIPS_PACRM_SP6_SHIFT                     6
+#define AIPS_PACRM_SP6_WIDTH                     1
+#define AIPS_PACRM_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP6_SHIFT))&AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_TP5_MASK                      0x100u
+#define AIPS_PACRM_TP5_SHIFT                     8
+#define AIPS_PACRM_TP5_WIDTH                     1
+#define AIPS_PACRM_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP5_SHIFT))&AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_WP5_MASK                      0x200u
+#define AIPS_PACRM_WP5_SHIFT                     9
+#define AIPS_PACRM_WP5_WIDTH                     1
+#define AIPS_PACRM_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP5_SHIFT))&AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_SP5_MASK                      0x400u
+#define AIPS_PACRM_SP5_SHIFT                     10
+#define AIPS_PACRM_SP5_WIDTH                     1
+#define AIPS_PACRM_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP5_SHIFT))&AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_TP4_MASK                      0x1000u
+#define AIPS_PACRM_TP4_SHIFT                     12
+#define AIPS_PACRM_TP4_WIDTH                     1
+#define AIPS_PACRM_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP4_SHIFT))&AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_WP4_MASK                      0x2000u
+#define AIPS_PACRM_WP4_SHIFT                     13
+#define AIPS_PACRM_WP4_WIDTH                     1
+#define AIPS_PACRM_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP4_SHIFT))&AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_SP4_MASK                      0x4000u
+#define AIPS_PACRM_SP4_SHIFT                     14
+#define AIPS_PACRM_SP4_WIDTH                     1
+#define AIPS_PACRM_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP4_SHIFT))&AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_TP3_MASK                      0x10000u
+#define AIPS_PACRM_TP3_SHIFT                     16
+#define AIPS_PACRM_TP3_WIDTH                     1
+#define AIPS_PACRM_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP3_SHIFT))&AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_WP3_MASK                      0x20000u
+#define AIPS_PACRM_WP3_SHIFT                     17
+#define AIPS_PACRM_WP3_WIDTH                     1
+#define AIPS_PACRM_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP3_SHIFT))&AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_SP3_MASK                      0x40000u
+#define AIPS_PACRM_SP3_SHIFT                     18
+#define AIPS_PACRM_SP3_WIDTH                     1
+#define AIPS_PACRM_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP3_SHIFT))&AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_TP2_MASK                      0x100000u
+#define AIPS_PACRM_TP2_SHIFT                     20
+#define AIPS_PACRM_TP2_WIDTH                     1
+#define AIPS_PACRM_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP2_SHIFT))&AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_WP2_MASK                      0x200000u
+#define AIPS_PACRM_WP2_SHIFT                     21
+#define AIPS_PACRM_WP2_WIDTH                     1
+#define AIPS_PACRM_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP2_SHIFT))&AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_SP2_MASK                      0x400000u
+#define AIPS_PACRM_SP2_SHIFT                     22
+#define AIPS_PACRM_SP2_WIDTH                     1
+#define AIPS_PACRM_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP2_SHIFT))&AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_TP1_MASK                      0x1000000u
+#define AIPS_PACRM_TP1_SHIFT                     24
+#define AIPS_PACRM_TP1_WIDTH                     1
+#define AIPS_PACRM_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP1_SHIFT))&AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_WP1_MASK                      0x2000000u
+#define AIPS_PACRM_WP1_SHIFT                     25
+#define AIPS_PACRM_WP1_WIDTH                     1
+#define AIPS_PACRM_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP1_SHIFT))&AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_SP1_MASK                      0x4000000u
+#define AIPS_PACRM_SP1_SHIFT                     26
+#define AIPS_PACRM_SP1_WIDTH                     1
+#define AIPS_PACRM_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP1_SHIFT))&AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_TP0_MASK                      0x10000000u
+#define AIPS_PACRM_TP0_SHIFT                     28
+#define AIPS_PACRM_TP0_WIDTH                     1
+#define AIPS_PACRM_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP0_SHIFT))&AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_WP0_MASK                      0x20000000u
+#define AIPS_PACRM_WP0_SHIFT                     29
+#define AIPS_PACRM_WP0_WIDTH                     1
+#define AIPS_PACRM_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP0_SHIFT))&AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_SP0_MASK                      0x40000000u
+#define AIPS_PACRM_SP0_SHIFT                     30
+#define AIPS_PACRM_SP0_WIDTH                     1
+#define AIPS_PACRM_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP0_SHIFT))&AIPS_PACRM_SP0_MASK)
+/* PACRN Bit Fields */
+#define AIPS_PACRN_TP7_MASK                      0x1u
+#define AIPS_PACRN_TP7_SHIFT                     0
+#define AIPS_PACRN_TP7_WIDTH                     1
+#define AIPS_PACRN_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP7_SHIFT))&AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_WP7_MASK                      0x2u
+#define AIPS_PACRN_WP7_SHIFT                     1
+#define AIPS_PACRN_WP7_WIDTH                     1
+#define AIPS_PACRN_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP7_SHIFT))&AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_SP7_MASK                      0x4u
+#define AIPS_PACRN_SP7_SHIFT                     2
+#define AIPS_PACRN_SP7_WIDTH                     1
+#define AIPS_PACRN_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP7_SHIFT))&AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_TP6_MASK                      0x10u
+#define AIPS_PACRN_TP6_SHIFT                     4
+#define AIPS_PACRN_TP6_WIDTH                     1
+#define AIPS_PACRN_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP6_SHIFT))&AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_WP6_MASK                      0x20u
+#define AIPS_PACRN_WP6_SHIFT                     5
+#define AIPS_PACRN_WP6_WIDTH                     1
+#define AIPS_PACRN_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP6_SHIFT))&AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_SP6_MASK                      0x40u
+#define AIPS_PACRN_SP6_SHIFT                     6
+#define AIPS_PACRN_SP6_WIDTH                     1
+#define AIPS_PACRN_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP6_SHIFT))&AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_TP5_MASK                      0x100u
+#define AIPS_PACRN_TP5_SHIFT                     8
+#define AIPS_PACRN_TP5_WIDTH                     1
+#define AIPS_PACRN_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP5_SHIFT))&AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_WP5_MASK                      0x200u
+#define AIPS_PACRN_WP5_SHIFT                     9
+#define AIPS_PACRN_WP5_WIDTH                     1
+#define AIPS_PACRN_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP5_SHIFT))&AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_SP5_MASK                      0x400u
+#define AIPS_PACRN_SP5_SHIFT                     10
+#define AIPS_PACRN_SP5_WIDTH                     1
+#define AIPS_PACRN_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP5_SHIFT))&AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_TP4_MASK                      0x1000u
+#define AIPS_PACRN_TP4_SHIFT                     12
+#define AIPS_PACRN_TP4_WIDTH                     1
+#define AIPS_PACRN_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP4_SHIFT))&AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_WP4_MASK                      0x2000u
+#define AIPS_PACRN_WP4_SHIFT                     13
+#define AIPS_PACRN_WP4_WIDTH                     1
+#define AIPS_PACRN_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP4_SHIFT))&AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_SP4_MASK                      0x4000u
+#define AIPS_PACRN_SP4_SHIFT                     14
+#define AIPS_PACRN_SP4_WIDTH                     1
+#define AIPS_PACRN_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP4_SHIFT))&AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_TP3_MASK                      0x10000u
+#define AIPS_PACRN_TP3_SHIFT                     16
+#define AIPS_PACRN_TP3_WIDTH                     1
+#define AIPS_PACRN_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP3_SHIFT))&AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_WP3_MASK                      0x20000u
+#define AIPS_PACRN_WP3_SHIFT                     17
+#define AIPS_PACRN_WP3_WIDTH                     1
+#define AIPS_PACRN_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP3_SHIFT))&AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_SP3_MASK                      0x40000u
+#define AIPS_PACRN_SP3_SHIFT                     18
+#define AIPS_PACRN_SP3_WIDTH                     1
+#define AIPS_PACRN_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP3_SHIFT))&AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_TP2_MASK                      0x100000u
+#define AIPS_PACRN_TP2_SHIFT                     20
+#define AIPS_PACRN_TP2_WIDTH                     1
+#define AIPS_PACRN_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP2_SHIFT))&AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_WP2_MASK                      0x200000u
+#define AIPS_PACRN_WP2_SHIFT                     21
+#define AIPS_PACRN_WP2_WIDTH                     1
+#define AIPS_PACRN_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP2_SHIFT))&AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_SP2_MASK                      0x400000u
+#define AIPS_PACRN_SP2_SHIFT                     22
+#define AIPS_PACRN_SP2_WIDTH                     1
+#define AIPS_PACRN_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP2_SHIFT))&AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_TP1_MASK                      0x1000000u
+#define AIPS_PACRN_TP1_SHIFT                     24
+#define AIPS_PACRN_TP1_WIDTH                     1
+#define AIPS_PACRN_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP1_SHIFT))&AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_WP1_MASK                      0x2000000u
+#define AIPS_PACRN_WP1_SHIFT                     25
+#define AIPS_PACRN_WP1_WIDTH                     1
+#define AIPS_PACRN_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP1_SHIFT))&AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_SP1_MASK                      0x4000000u
+#define AIPS_PACRN_SP1_SHIFT                     26
+#define AIPS_PACRN_SP1_WIDTH                     1
+#define AIPS_PACRN_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP1_SHIFT))&AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_TP0_MASK                      0x10000000u
+#define AIPS_PACRN_TP0_SHIFT                     28
+#define AIPS_PACRN_TP0_WIDTH                     1
+#define AIPS_PACRN_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP0_SHIFT))&AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_WP0_MASK                      0x20000000u
+#define AIPS_PACRN_WP0_SHIFT                     29
+#define AIPS_PACRN_WP0_WIDTH                     1
+#define AIPS_PACRN_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP0_SHIFT))&AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_SP0_MASK                      0x40000000u
+#define AIPS_PACRN_SP0_SHIFT                     30
+#define AIPS_PACRN_SP0_WIDTH                     1
+#define AIPS_PACRN_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP0_SHIFT))&AIPS_PACRN_SP0_MASK)
+/* PACRO Bit Fields */
+#define AIPS_PACRO_TP7_MASK                      0x1u
+#define AIPS_PACRO_TP7_SHIFT                     0
+#define AIPS_PACRO_TP7_WIDTH                     1
+#define AIPS_PACRO_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP7_SHIFT))&AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_WP7_MASK                      0x2u
+#define AIPS_PACRO_WP7_SHIFT                     1
+#define AIPS_PACRO_WP7_WIDTH                     1
+#define AIPS_PACRO_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP7_SHIFT))&AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_SP7_MASK                      0x4u
+#define AIPS_PACRO_SP7_SHIFT                     2
+#define AIPS_PACRO_SP7_WIDTH                     1
+#define AIPS_PACRO_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP7_SHIFT))&AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_TP6_MASK                      0x10u
+#define AIPS_PACRO_TP6_SHIFT                     4
+#define AIPS_PACRO_TP6_WIDTH                     1
+#define AIPS_PACRO_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP6_SHIFT))&AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_WP6_MASK                      0x20u
+#define AIPS_PACRO_WP6_SHIFT                     5
+#define AIPS_PACRO_WP6_WIDTH                     1
+#define AIPS_PACRO_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP6_SHIFT))&AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_SP6_MASK                      0x40u
+#define AIPS_PACRO_SP6_SHIFT                     6
+#define AIPS_PACRO_SP6_WIDTH                     1
+#define AIPS_PACRO_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP6_SHIFT))&AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_TP5_MASK                      0x100u
+#define AIPS_PACRO_TP5_SHIFT                     8
+#define AIPS_PACRO_TP5_WIDTH                     1
+#define AIPS_PACRO_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP5_SHIFT))&AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_WP5_MASK                      0x200u
+#define AIPS_PACRO_WP5_SHIFT                     9
+#define AIPS_PACRO_WP5_WIDTH                     1
+#define AIPS_PACRO_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP5_SHIFT))&AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_SP5_MASK                      0x400u
+#define AIPS_PACRO_SP5_SHIFT                     10
+#define AIPS_PACRO_SP5_WIDTH                     1
+#define AIPS_PACRO_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP5_SHIFT))&AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_TP4_MASK                      0x1000u
+#define AIPS_PACRO_TP4_SHIFT                     12
+#define AIPS_PACRO_TP4_WIDTH                     1
+#define AIPS_PACRO_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP4_SHIFT))&AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_WP4_MASK                      0x2000u
+#define AIPS_PACRO_WP4_SHIFT                     13
+#define AIPS_PACRO_WP4_WIDTH                     1
+#define AIPS_PACRO_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP4_SHIFT))&AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_SP4_MASK                      0x4000u
+#define AIPS_PACRO_SP4_SHIFT                     14
+#define AIPS_PACRO_SP4_WIDTH                     1
+#define AIPS_PACRO_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP4_SHIFT))&AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_TP3_MASK                      0x10000u
+#define AIPS_PACRO_TP3_SHIFT                     16
+#define AIPS_PACRO_TP3_WIDTH                     1
+#define AIPS_PACRO_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP3_SHIFT))&AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_WP3_MASK                      0x20000u
+#define AIPS_PACRO_WP3_SHIFT                     17
+#define AIPS_PACRO_WP3_WIDTH                     1
+#define AIPS_PACRO_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP3_SHIFT))&AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_SP3_MASK                      0x40000u
+#define AIPS_PACRO_SP3_SHIFT                     18
+#define AIPS_PACRO_SP3_WIDTH                     1
+#define AIPS_PACRO_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP3_SHIFT))&AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_TP2_MASK                      0x100000u
+#define AIPS_PACRO_TP2_SHIFT                     20
+#define AIPS_PACRO_TP2_WIDTH                     1
+#define AIPS_PACRO_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP2_SHIFT))&AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_WP2_MASK                      0x200000u
+#define AIPS_PACRO_WP2_SHIFT                     21
+#define AIPS_PACRO_WP2_WIDTH                     1
+#define AIPS_PACRO_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP2_SHIFT))&AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_SP2_MASK                      0x400000u
+#define AIPS_PACRO_SP2_SHIFT                     22
+#define AIPS_PACRO_SP2_WIDTH                     1
+#define AIPS_PACRO_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP2_SHIFT))&AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_TP1_MASK                      0x1000000u
+#define AIPS_PACRO_TP1_SHIFT                     24
+#define AIPS_PACRO_TP1_WIDTH                     1
+#define AIPS_PACRO_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP1_SHIFT))&AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_WP1_MASK                      0x2000000u
+#define AIPS_PACRO_WP1_SHIFT                     25
+#define AIPS_PACRO_WP1_WIDTH                     1
+#define AIPS_PACRO_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP1_SHIFT))&AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_SP1_MASK                      0x4000000u
+#define AIPS_PACRO_SP1_SHIFT                     26
+#define AIPS_PACRO_SP1_WIDTH                     1
+#define AIPS_PACRO_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP1_SHIFT))&AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_TP0_MASK                      0x10000000u
+#define AIPS_PACRO_TP0_SHIFT                     28
+#define AIPS_PACRO_TP0_WIDTH                     1
+#define AIPS_PACRO_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP0_SHIFT))&AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_WP0_MASK                      0x20000000u
+#define AIPS_PACRO_WP0_SHIFT                     29
+#define AIPS_PACRO_WP0_WIDTH                     1
+#define AIPS_PACRO_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP0_SHIFT))&AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_SP0_MASK                      0x40000000u
+#define AIPS_PACRO_SP0_SHIFT                     30
+#define AIPS_PACRO_SP0_WIDTH                     1
+#define AIPS_PACRO_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP0_SHIFT))&AIPS_PACRO_SP0_MASK)
+/* PACRP Bit Fields */
+#define AIPS_PACRP_TP7_MASK                      0x1u
+#define AIPS_PACRP_TP7_SHIFT                     0
+#define AIPS_PACRP_TP7_WIDTH                     1
+#define AIPS_PACRP_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP7_SHIFT))&AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_WP7_MASK                      0x2u
+#define AIPS_PACRP_WP7_SHIFT                     1
+#define AIPS_PACRP_WP7_WIDTH                     1
+#define AIPS_PACRP_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP7_SHIFT))&AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_SP7_MASK                      0x4u
+#define AIPS_PACRP_SP7_SHIFT                     2
+#define AIPS_PACRP_SP7_WIDTH                     1
+#define AIPS_PACRP_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP7_SHIFT))&AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_TP6_MASK                      0x10u
+#define AIPS_PACRP_TP6_SHIFT                     4
+#define AIPS_PACRP_TP6_WIDTH                     1
+#define AIPS_PACRP_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP6_SHIFT))&AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_WP6_MASK                      0x20u
+#define AIPS_PACRP_WP6_SHIFT                     5
+#define AIPS_PACRP_WP6_WIDTH                     1
+#define AIPS_PACRP_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP6_SHIFT))&AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_SP6_MASK                      0x40u
+#define AIPS_PACRP_SP6_SHIFT                     6
+#define AIPS_PACRP_SP6_WIDTH                     1
+#define AIPS_PACRP_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP6_SHIFT))&AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_TP5_MASK                      0x100u
+#define AIPS_PACRP_TP5_SHIFT                     8
+#define AIPS_PACRP_TP5_WIDTH                     1
+#define AIPS_PACRP_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP5_SHIFT))&AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_WP5_MASK                      0x200u
+#define AIPS_PACRP_WP5_SHIFT                     9
+#define AIPS_PACRP_WP5_WIDTH                     1
+#define AIPS_PACRP_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP5_SHIFT))&AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_SP5_MASK                      0x400u
+#define AIPS_PACRP_SP5_SHIFT                     10
+#define AIPS_PACRP_SP5_WIDTH                     1
+#define AIPS_PACRP_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP5_SHIFT))&AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_TP4_MASK                      0x1000u
+#define AIPS_PACRP_TP4_SHIFT                     12
+#define AIPS_PACRP_TP4_WIDTH                     1
+#define AIPS_PACRP_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP4_SHIFT))&AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_WP4_MASK                      0x2000u
+#define AIPS_PACRP_WP4_SHIFT                     13
+#define AIPS_PACRP_WP4_WIDTH                     1
+#define AIPS_PACRP_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP4_SHIFT))&AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_SP4_MASK                      0x4000u
+#define AIPS_PACRP_SP4_SHIFT                     14
+#define AIPS_PACRP_SP4_WIDTH                     1
+#define AIPS_PACRP_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP4_SHIFT))&AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_TP3_MASK                      0x10000u
+#define AIPS_PACRP_TP3_SHIFT                     16
+#define AIPS_PACRP_TP3_WIDTH                     1
+#define AIPS_PACRP_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP3_SHIFT))&AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_WP3_MASK                      0x20000u
+#define AIPS_PACRP_WP3_SHIFT                     17
+#define AIPS_PACRP_WP3_WIDTH                     1
+#define AIPS_PACRP_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP3_SHIFT))&AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_SP3_MASK                      0x40000u
+#define AIPS_PACRP_SP3_SHIFT                     18
+#define AIPS_PACRP_SP3_WIDTH                     1
+#define AIPS_PACRP_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP3_SHIFT))&AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_TP2_MASK                      0x100000u
+#define AIPS_PACRP_TP2_SHIFT                     20
+#define AIPS_PACRP_TP2_WIDTH                     1
+#define AIPS_PACRP_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP2_SHIFT))&AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_WP2_MASK                      0x200000u
+#define AIPS_PACRP_WP2_SHIFT                     21
+#define AIPS_PACRP_WP2_WIDTH                     1
+#define AIPS_PACRP_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP2_SHIFT))&AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_SP2_MASK                      0x400000u
+#define AIPS_PACRP_SP2_SHIFT                     22
+#define AIPS_PACRP_SP2_WIDTH                     1
+#define AIPS_PACRP_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP2_SHIFT))&AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_TP1_MASK                      0x1000000u
+#define AIPS_PACRP_TP1_SHIFT                     24
+#define AIPS_PACRP_TP1_WIDTH                     1
+#define AIPS_PACRP_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP1_SHIFT))&AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_WP1_MASK                      0x2000000u
+#define AIPS_PACRP_WP1_SHIFT                     25
+#define AIPS_PACRP_WP1_WIDTH                     1
+#define AIPS_PACRP_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP1_SHIFT))&AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_SP1_MASK                      0x4000000u
+#define AIPS_PACRP_SP1_SHIFT                     26
+#define AIPS_PACRP_SP1_WIDTH                     1
+#define AIPS_PACRP_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP1_SHIFT))&AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_TP0_MASK                      0x10000000u
+#define AIPS_PACRP_TP0_SHIFT                     28
+#define AIPS_PACRP_TP0_WIDTH                     1
+#define AIPS_PACRP_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP0_SHIFT))&AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_WP0_MASK                      0x20000000u
+#define AIPS_PACRP_WP0_SHIFT                     29
+#define AIPS_PACRP_WP0_WIDTH                     1
+#define AIPS_PACRP_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP0_SHIFT))&AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_SP0_MASK                      0x40000000u
+#define AIPS_PACRP_SP0_SHIFT                     30
+#define AIPS_PACRP_SP0_WIDTH                     1
+#define AIPS_PACRP_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP0_SHIFT))&AIPS_PACRP_SP0_MASK)
+/* PACRU Bit Fields */
+#define AIPS_PACRU_TP1_MASK                      0x1000000u
+#define AIPS_PACRU_TP1_SHIFT                     24
+#define AIPS_PACRU_TP1_WIDTH                     1
+#define AIPS_PACRU_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_TP1_SHIFT))&AIPS_PACRU_TP1_MASK)
+#define AIPS_PACRU_WP1_MASK                      0x2000000u
+#define AIPS_PACRU_WP1_SHIFT                     25
+#define AIPS_PACRU_WP1_WIDTH                     1
+#define AIPS_PACRU_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_WP1_SHIFT))&AIPS_PACRU_WP1_MASK)
+#define AIPS_PACRU_SP1_MASK                      0x4000000u
+#define AIPS_PACRU_SP1_SHIFT                     26
+#define AIPS_PACRU_SP1_WIDTH                     1
+#define AIPS_PACRU_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_SP1_SHIFT))&AIPS_PACRU_SP1_MASK)
+#define AIPS_PACRU_TP0_MASK                      0x10000000u
+#define AIPS_PACRU_TP0_SHIFT                     28
+#define AIPS_PACRU_TP0_WIDTH                     1
+#define AIPS_PACRU_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_TP0_SHIFT))&AIPS_PACRU_TP0_MASK)
+#define AIPS_PACRU_WP0_MASK                      0x20000000u
+#define AIPS_PACRU_WP0_SHIFT                     29
+#define AIPS_PACRU_WP0_WIDTH                     1
+#define AIPS_PACRU_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_WP0_SHIFT))&AIPS_PACRU_WP0_MASK)
+#define AIPS_PACRU_SP0_MASK                      0x40000000u
+#define AIPS_PACRU_SP0_SHIFT                     30
+#define AIPS_PACRU_SP0_WIDTH                     1
+#define AIPS_PACRU_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_SP0_SHIFT))&AIPS_PACRU_SP0_MASK)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base address */
+#define AIPS0_BASE                               (0x40000000u)
+/** Peripheral AIPS0 base pointer */
+#define AIPS0                                    ((AIPS_Type *)AIPS0_BASE)
+#define AIPS0_BASE_PTR                           (AIPS0)
+/** Peripheral AIPS1 base address */
+#define AIPS1_BASE                               (0x40080000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1                                    ((AIPS_Type *)AIPS1_BASE)
+#define AIPS1_BASE_PTR                           (AIPS1)
+/** Array initializer of AIPS peripheral base addresses */
+#define AIPS_BASE_ADDRS                          { AIPS0_BASE, AIPS1_BASE }
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS                           { AIPS0, AIPS1 }
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register instance definitions */
+/* AIPS0 */
+#define AIPS0_MPRA                               AIPS_MPRA_REG(AIPS0)
+#define AIPS0_PACRA                              AIPS_PACRA_REG(AIPS0)
+#define AIPS0_PACRB                              AIPS_PACRB_REG(AIPS0)
+#define AIPS0_PACRC                              AIPS_PACRC_REG(AIPS0)
+#define AIPS0_PACRD                              AIPS_PACRD_REG(AIPS0)
+#define AIPS0_PACRE                              AIPS_PACRE_REG(AIPS0)
+#define AIPS0_PACRF                              AIPS_PACRF_REG(AIPS0)
+#define AIPS0_PACRG                              AIPS_PACRG_REG(AIPS0)
+#define AIPS0_PACRH                              AIPS_PACRH_REG(AIPS0)
+#define AIPS0_PACRI                              AIPS_PACRI_REG(AIPS0)
+#define AIPS0_PACRJ                              AIPS_PACRJ_REG(AIPS0)
+#define AIPS0_PACRK                              AIPS_PACRK_REG(AIPS0)
+#define AIPS0_PACRL                              AIPS_PACRL_REG(AIPS0)
+#define AIPS0_PACRM                              AIPS_PACRM_REG(AIPS0)
+#define AIPS0_PACRN                              AIPS_PACRN_REG(AIPS0)
+#define AIPS0_PACRO                              AIPS_PACRO_REG(AIPS0)
+#define AIPS0_PACRP                              AIPS_PACRP_REG(AIPS0)
+#define AIPS0_PACRU                              AIPS_PACRU_REG(AIPS0)
+/* AIPS1 */
+#define AIPS1_MPRA                               AIPS_MPRA_REG(AIPS1)
+#define AIPS1_PACRA                              AIPS_PACRA_REG(AIPS1)
+#define AIPS1_PACRB                              AIPS_PACRB_REG(AIPS1)
+#define AIPS1_PACRC                              AIPS_PACRC_REG(AIPS1)
+#define AIPS1_PACRD                              AIPS_PACRD_REG(AIPS1)
+#define AIPS1_PACRE                              AIPS_PACRE_REG(AIPS1)
+#define AIPS1_PACRF                              AIPS_PACRF_REG(AIPS1)
+#define AIPS1_PACRG                              AIPS_PACRG_REG(AIPS1)
+#define AIPS1_PACRH                              AIPS_PACRH_REG(AIPS1)
+#define AIPS1_PACRI                              AIPS_PACRI_REG(AIPS1)
+#define AIPS1_PACRJ                              AIPS_PACRJ_REG(AIPS1)
+#define AIPS1_PACRK                              AIPS_PACRK_REG(AIPS1)
+#define AIPS1_PACRL                              AIPS_PACRL_REG(AIPS1)
+#define AIPS1_PACRM                              AIPS_PACRM_REG(AIPS1)
+#define AIPS1_PACRN                              AIPS_PACRN_REG(AIPS1)
+#define AIPS1_PACRO                              AIPS_PACRO_REG(AIPS1)
+#define AIPS1_PACRP                              AIPS_PACRP_REG(AIPS1)
+#define AIPS1_PACRU                              AIPS_PACRU_REG(AIPS1)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t PRS;                               /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CRS;                               /**< Control Register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_1[236];
+  } SLAVE[5];
+       uint8_t RESERVED_0[768];
+  __IO uint32_t MGPCR0;                            /**< Master General Purpose Control Register, offset: 0x800 */
+       uint8_t RESERVED_1[252];
+  __IO uint32_t MGPCR1;                            /**< Master General Purpose Control Register, offset: 0x900 */
+       uint8_t RESERVED_2[252];
+  __IO uint32_t MGPCR2;                            /**< Master General Purpose Control Register, offset: 0xA00 */
+       uint8_t RESERVED_3[252];
+  __IO uint32_t MGPCR3;                            /**< Master General Purpose Control Register, offset: 0xB00 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t MGPCR4;                            /**< Master General Purpose Control Register, offset: 0xC00 */
+       uint8_t RESERVED_5[252];
+  __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
+} AXBS_Type, *AXBS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register accessors */
+#define AXBS_PRS_REG(base,index)                 ((base)->SLAVE[index].PRS)
+#define AXBS_PRS_COUNT                           5
+#define AXBS_CRS_REG(base,index)                 ((base)->SLAVE[index].CRS)
+#define AXBS_CRS_COUNT                           5
+#define AXBS_MGPCR0_REG(base)                    ((base)->MGPCR0)
+#define AXBS_MGPCR1_REG(base)                    ((base)->MGPCR1)
+#define AXBS_MGPCR2_REG(base)                    ((base)->MGPCR2)
+#define AXBS_MGPCR3_REG(base)                    ((base)->MGPCR3)
+#define AXBS_MGPCR4_REG(base)                    ((base)->MGPCR4)
+#define AXBS_MGPCR5_REG(base)                    ((base)->MGPCR5)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/* PRS Bit Fields */
+#define AXBS_PRS_M0_MASK                         0x7u
+#define AXBS_PRS_M0_SHIFT                        0
+#define AXBS_PRS_M0_WIDTH                        3
+#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK                         0x70u
+#define AXBS_PRS_M1_SHIFT                        4
+#define AXBS_PRS_M1_WIDTH                        3
+#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK                         0x700u
+#define AXBS_PRS_M2_SHIFT                        8
+#define AXBS_PRS_M2_WIDTH                        3
+#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK                         0x7000u
+#define AXBS_PRS_M3_SHIFT                        12
+#define AXBS_PRS_M3_WIDTH                        3
+#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK                         0x70000u
+#define AXBS_PRS_M4_SHIFT                        16
+#define AXBS_PRS_M4_WIDTH                        3
+#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK                         0x700000u
+#define AXBS_PRS_M5_SHIFT                        20
+#define AXBS_PRS_M5_WIDTH                        3
+#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
+/* CRS Bit Fields */
+#define AXBS_CRS_PARK_MASK                       0x7u
+#define AXBS_CRS_PARK_SHIFT                      0
+#define AXBS_CRS_PARK_WIDTH                      3
+#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK                       0x30u
+#define AXBS_CRS_PCTL_SHIFT                      4
+#define AXBS_CRS_PCTL_WIDTH                      2
+#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK                        0x300u
+#define AXBS_CRS_ARB_SHIFT                       8
+#define AXBS_CRS_ARB_WIDTH                       2
+#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK                        0x40000000u
+#define AXBS_CRS_HLP_SHIFT                       30
+#define AXBS_CRS_HLP_WIDTH                       1
+#define AXBS_CRS_HLP(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_HLP_SHIFT))&AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_RO_MASK                         0x80000000u
+#define AXBS_CRS_RO_SHIFT                        31
+#define AXBS_CRS_RO_WIDTH                        1
+#define AXBS_CRS_RO(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_RO_SHIFT))&AXBS_CRS_RO_MASK)
+/* MGPCR0 Bit Fields */
+#define AXBS_MGPCR0_AULB_MASK                    0x7u
+#define AXBS_MGPCR0_AULB_SHIFT                   0
+#define AXBS_MGPCR0_AULB_WIDTH                   3
+#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
+/* MGPCR1 Bit Fields */
+#define AXBS_MGPCR1_AULB_MASK                    0x7u
+#define AXBS_MGPCR1_AULB_SHIFT                   0
+#define AXBS_MGPCR1_AULB_WIDTH                   3
+#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
+/* MGPCR2 Bit Fields */
+#define AXBS_MGPCR2_AULB_MASK                    0x7u
+#define AXBS_MGPCR2_AULB_SHIFT                   0
+#define AXBS_MGPCR2_AULB_WIDTH                   3
+#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
+/* MGPCR3 Bit Fields */
+#define AXBS_MGPCR3_AULB_MASK                    0x7u
+#define AXBS_MGPCR3_AULB_SHIFT                   0
+#define AXBS_MGPCR3_AULB_WIDTH                   3
+#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
+/* MGPCR4 Bit Fields */
+#define AXBS_MGPCR4_AULB_MASK                    0x7u
+#define AXBS_MGPCR4_AULB_SHIFT                   0
+#define AXBS_MGPCR4_AULB_WIDTH                   3
+#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
+/* MGPCR5 Bit Fields */
+#define AXBS_MGPCR5_AULB_MASK                    0x7u
+#define AXBS_MGPCR5_AULB_SHIFT                   0
+#define AXBS_MGPCR5_AULB_WIDTH                   3
+#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS base address */
+#define AXBS_BASE                                (0x40004000u)
+/** Peripheral AXBS base pointer */
+#define AXBS                                     ((AXBS_Type *)AXBS_BASE)
+#define AXBS_BASE_PTR                            (AXBS)
+/** Array initializer of AXBS peripheral base addresses */
+#define AXBS_BASE_ADDRS                          { AXBS_BASE }
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASE_PTRS                           { AXBS }
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register instance definitions */
+/* AXBS */
+#define AXBS_PRS0                                AXBS_PRS_REG(AXBS,0)
+#define AXBS_CRS0                                AXBS_CRS_REG(AXBS,0)
+#define AXBS_PRS1                                AXBS_PRS_REG(AXBS,1)
+#define AXBS_CRS1                                AXBS_CRS_REG(AXBS,1)
+#define AXBS_PRS2                                AXBS_PRS_REG(AXBS,2)
+#define AXBS_CRS2                                AXBS_CRS_REG(AXBS,2)
+#define AXBS_PRS3                                AXBS_PRS_REG(AXBS,3)
+#define AXBS_CRS3                                AXBS_CRS_REG(AXBS,3)
+#define AXBS_PRS4                                AXBS_PRS_REG(AXBS,4)
+#define AXBS_CRS4                                AXBS_CRS_REG(AXBS,4)
+#define AXBS_MGPCR0                              AXBS_MGPCR0_REG(AXBS)
+#define AXBS_MGPCR1                              AXBS_MGPCR1_REG(AXBS)
+#define AXBS_MGPCR2                              AXBS_MGPCR2_REG(AXBS)
+#define AXBS_MGPCR3                              AXBS_MGPCR3_REG(AXBS)
+#define AXBS_MGPCR4                              AXBS_MGPCR4_REG(AXBS)
+#define AXBS_MGPCR5                              AXBS_MGPCR5_REG(AXBS)
+
+/* AXBS - Register array accessors */
+#define AXBS_PRS(index)                          AXBS_PRS_REG(AXBS,index)
+#define AXBS_CRS(index)                          AXBS_CRS_REG(AXBS,index)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
+  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
+  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
+  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
+  __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
+  __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
+  __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
+  __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
+  __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
+       uint8_t RESERVED_4[48];
+  struct {                                         /* offset: 0x80, array step: 0x10 */
+    __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+    __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+    __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+    __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+  } MB[16];
+       uint8_t RESERVED_5[1792];
+  __IO uint32_t RXIMR[16];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_Type, *CAN_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register accessors */
+#define CAN_MCR_REG(base)                        ((base)->MCR)
+#define CAN_CTRL1_REG(base)                      ((base)->CTRL1)
+#define CAN_TIMER_REG(base)                      ((base)->TIMER)
+#define CAN_RXMGMASK_REG(base)                   ((base)->RXMGMASK)
+#define CAN_RX14MASK_REG(base)                   ((base)->RX14MASK)
+#define CAN_RX15MASK_REG(base)                   ((base)->RX15MASK)
+#define CAN_ECR_REG(base)                        ((base)->ECR)
+#define CAN_ESR1_REG(base)                       ((base)->ESR1)
+#define CAN_IMASK1_REG(base)                     ((base)->IMASK1)
+#define CAN_IFLAG1_REG(base)                     ((base)->IFLAG1)
+#define CAN_CTRL2_REG(base)                      ((base)->CTRL2)
+#define CAN_ESR2_REG(base)                       ((base)->ESR2)
+#define CAN_CRCR_REG(base)                       ((base)->CRCR)
+#define CAN_RXFGMASK_REG(base)                   ((base)->RXFGMASK)
+#define CAN_RXFIR_REG(base)                      ((base)->RXFIR)
+#define CAN_CS_REG(base,index)                   ((base)->MB[index].CS)
+#define CAN_CS_COUNT                             16
+#define CAN_ID_REG(base,index)                   ((base)->MB[index].ID)
+#define CAN_ID_COUNT                             16
+#define CAN_WORD0_REG(base,index)                ((base)->MB[index].WORD0)
+#define CAN_WORD0_COUNT                          16
+#define CAN_WORD1_REG(base,index)                ((base)->MB[index].WORD1)
+#define CAN_WORD1_COUNT                          16
+#define CAN_RXIMR_REG(base,index)                ((base)->RXIMR[index])
+#define CAN_RXIMR_COUNT                          16
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define CAN_MCR_MAXMB_MASK                       0x7Fu
+#define CAN_MCR_MAXMB_SHIFT                      0
+#define CAN_MCR_MAXMB_WIDTH                      7
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK                        0x300u
+#define CAN_MCR_IDAM_SHIFT                       8
+#define CAN_MCR_IDAM_WIDTH                       2
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK                         0x1000u
+#define CAN_MCR_AEN_SHIFT                        12
+#define CAN_MCR_AEN_WIDTH                        1
+#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK                     0x2000u
+#define CAN_MCR_LPRIOEN_SHIFT                    13
+#define CAN_MCR_LPRIOEN_WIDTH                    1
+#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_IRMQ_MASK                        0x10000u
+#define CAN_MCR_IRMQ_SHIFT                       16
+#define CAN_MCR_IRMQ_WIDTH                       1
+#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK                      0x20000u
+#define CAN_MCR_SRXDIS_SHIFT                     17
+#define CAN_MCR_SRXDIS_WIDTH                     1
+#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_WAKSRC_MASK                      0x80000u
+#define CAN_MCR_WAKSRC_SHIFT                     19
+#define CAN_MCR_WAKSRC_WIDTH                     1
+#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKSRC_SHIFT))&CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_LPMACK_MASK                      0x100000u
+#define CAN_MCR_LPMACK_SHIFT                     20
+#define CAN_MCR_LPMACK_WIDTH                     1
+#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK                       0x200000u
+#define CAN_MCR_WRNEN_SHIFT                      21
+#define CAN_MCR_WRNEN_WIDTH                      1
+#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SLFWAK_MASK                      0x400000u
+#define CAN_MCR_SLFWAK_SHIFT                     22
+#define CAN_MCR_SLFWAK_WIDTH                     1
+#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SLFWAK_SHIFT))&CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SUPV_MASK                        0x800000u
+#define CAN_MCR_SUPV_SHIFT                       23
+#define CAN_MCR_SUPV_WIDTH                       1
+#define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
+#define CAN_MCR_FRZACK_MASK                      0x1000000u
+#define CAN_MCR_FRZACK_SHIFT                     24
+#define CAN_MCR_FRZACK_WIDTH                     1
+#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK                     0x2000000u
+#define CAN_MCR_SOFTRST_SHIFT                    25
+#define CAN_MCR_SOFTRST_WIDTH                    1
+#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_WAKMSK_MASK                      0x4000000u
+#define CAN_MCR_WAKMSK_SHIFT                     26
+#define CAN_MCR_WAKMSK_WIDTH                     1
+#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKMSK_SHIFT))&CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_NOTRDY_MASK                      0x8000000u
+#define CAN_MCR_NOTRDY_SHIFT                     27
+#define CAN_MCR_NOTRDY_WIDTH                     1
+#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK                        0x10000000u
+#define CAN_MCR_HALT_SHIFT                       28
+#define CAN_MCR_HALT_WIDTH                       1
+#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK                        0x20000000u
+#define CAN_MCR_RFEN_SHIFT                       29
+#define CAN_MCR_RFEN_WIDTH                       1
+#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK                         0x40000000u
+#define CAN_MCR_FRZ_SHIFT                        30
+#define CAN_MCR_FRZ_WIDTH                        1
+#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK                        0x80000000u
+#define CAN_MCR_MDIS_SHIFT                       31
+#define CAN_MCR_MDIS_WIDTH                       1
+#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
+/* CTRL1 Bit Fields */
+#define CAN_CTRL1_PROPSEG_MASK                   0x7u
+#define CAN_CTRL1_PROPSEG_SHIFT                  0
+#define CAN_CTRL1_PROPSEG_WIDTH                  3
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK                       0x8u
+#define CAN_CTRL1_LOM_SHIFT                      3
+#define CAN_CTRL1_LOM_WIDTH                      1
+#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK                      0x10u
+#define CAN_CTRL1_LBUF_SHIFT                     4
+#define CAN_CTRL1_LBUF_WIDTH                     1
+#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK                      0x20u
+#define CAN_CTRL1_TSYN_SHIFT                     5
+#define CAN_CTRL1_TSYN_WIDTH                     1
+#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK                   0x40u
+#define CAN_CTRL1_BOFFREC_SHIFT                  6
+#define CAN_CTRL1_BOFFREC_WIDTH                  1
+#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK                       0x80u
+#define CAN_CTRL1_SMP_SHIFT                      7
+#define CAN_CTRL1_SMP_WIDTH                      1
+#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK                   0x400u
+#define CAN_CTRL1_RWRNMSK_SHIFT                  10
+#define CAN_CTRL1_RWRNMSK_WIDTH                  1
+#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK                   0x800u
+#define CAN_CTRL1_TWRNMSK_SHIFT                  11
+#define CAN_CTRL1_TWRNMSK_WIDTH                  1
+#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK                       0x1000u
+#define CAN_CTRL1_LPB_SHIFT                      12
+#define CAN_CTRL1_LPB_WIDTH                      1
+#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_CLKSRC_MASK                    0x2000u
+#define CAN_CTRL1_CLKSRC_SHIFT                   13
+#define CAN_CTRL1_CLKSRC_WIDTH                   1
+#define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_ERRMSK_MASK                    0x4000u
+#define CAN_CTRL1_ERRMSK_SHIFT                   14
+#define CAN_CTRL1_ERRMSK_WIDTH                   1
+#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK                   0x8000u
+#define CAN_CTRL1_BOFFMSK_SHIFT                  15
+#define CAN_CTRL1_BOFFMSK_WIDTH                  1
+#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK                     0x70000u
+#define CAN_CTRL1_PSEG2_SHIFT                    16
+#define CAN_CTRL1_PSEG2_WIDTH                    3
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK                     0x380000u
+#define CAN_CTRL1_PSEG1_SHIFT                    19
+#define CAN_CTRL1_PSEG1_WIDTH                    3
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK                       0xC00000u
+#define CAN_CTRL1_RJW_SHIFT                      22
+#define CAN_CTRL1_RJW_WIDTH                      2
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
+#define CAN_CTRL1_PRESDIV_SHIFT                  24
+#define CAN_CTRL1_PRESDIV_WIDTH                  8
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
+/* TIMER Bit Fields */
+#define CAN_TIMER_TIMER_MASK                     0xFFFFu
+#define CAN_TIMER_TIMER_SHIFT                    0
+#define CAN_TIMER_TIMER_WIDTH                    16
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
+/* RXMGMASK Bit Fields */
+#define CAN_RXMGMASK_MG_MASK                     0xFFFFFFFFu
+#define CAN_RXMGMASK_MG_SHIFT                    0
+#define CAN_RXMGMASK_MG_WIDTH                    32
+#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
+/* RX14MASK Bit Fields */
+#define CAN_RX14MASK_RX14M_MASK                  0xFFFFFFFFu
+#define CAN_RX14MASK_RX14M_SHIFT                 0
+#define CAN_RX14MASK_RX14M_WIDTH                 32
+#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
+/* RX15MASK Bit Fields */
+#define CAN_RX15MASK_RX15M_MASK                  0xFFFFFFFFu
+#define CAN_RX15MASK_RX15M_SHIFT                 0
+#define CAN_RX15MASK_RX15M_WIDTH                 32
+#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
+/* ECR Bit Fields */
+#define CAN_ECR_TXERRCNT_MASK                    0xFFu
+#define CAN_ECR_TXERRCNT_SHIFT                   0
+#define CAN_ECR_TXERRCNT_WIDTH                   8
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK                    0xFF00u
+#define CAN_ECR_RXERRCNT_SHIFT                   8
+#define CAN_ECR_RXERRCNT_WIDTH                   8
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
+/* ESR1 Bit Fields */
+#define CAN_ESR1_WAKINT_MASK                     0x1u
+#define CAN_ESR1_WAKINT_SHIFT                    0
+#define CAN_ESR1_WAKINT_WIDTH                    1
+#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_WAKINT_SHIFT))&CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_ERRINT_MASK                     0x2u
+#define CAN_ESR1_ERRINT_SHIFT                    1
+#define CAN_ESR1_ERRINT_WIDTH                    1
+#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK                    0x4u
+#define CAN_ESR1_BOFFINT_SHIFT                   2
+#define CAN_ESR1_BOFFINT_WIDTH                   1
+#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK                         0x8u
+#define CAN_ESR1_RX_SHIFT                        3
+#define CAN_ESR1_RX_WIDTH                        1
+#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK                    0x30u
+#define CAN_ESR1_FLTCONF_SHIFT                   4
+#define CAN_ESR1_FLTCONF_WIDTH                   2
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK                         0x40u
+#define CAN_ESR1_TX_SHIFT                        6
+#define CAN_ESR1_TX_WIDTH                        1
+#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK                       0x80u
+#define CAN_ESR1_IDLE_SHIFT                      7
+#define CAN_ESR1_IDLE_WIDTH                      1
+#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK                      0x100u
+#define CAN_ESR1_RXWRN_SHIFT                     8
+#define CAN_ESR1_RXWRN_WIDTH                     1
+#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK                      0x200u
+#define CAN_ESR1_TXWRN_SHIFT                     9
+#define CAN_ESR1_TXWRN_WIDTH                     1
+#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK                     0x400u
+#define CAN_ESR1_STFERR_SHIFT                    10
+#define CAN_ESR1_STFERR_WIDTH                    1
+#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK                     0x800u
+#define CAN_ESR1_FRMERR_SHIFT                    11
+#define CAN_ESR1_FRMERR_WIDTH                    1
+#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK                     0x1000u
+#define CAN_ESR1_CRCERR_SHIFT                    12
+#define CAN_ESR1_CRCERR_WIDTH                    1
+#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK                     0x2000u
+#define CAN_ESR1_ACKERR_SHIFT                    13
+#define CAN_ESR1_ACKERR_WIDTH                    1
+#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK                    0x4000u
+#define CAN_ESR1_BIT0ERR_SHIFT                   14
+#define CAN_ESR1_BIT0ERR_WIDTH                   1
+#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK                    0x8000u
+#define CAN_ESR1_BIT1ERR_SHIFT                   15
+#define CAN_ESR1_BIT1ERR_WIDTH                   1
+#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK                    0x10000u
+#define CAN_ESR1_RWRNINT_SHIFT                   16
+#define CAN_ESR1_RWRNINT_WIDTH                   1
+#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK                    0x20000u
+#define CAN_ESR1_TWRNINT_SHIFT                   17
+#define CAN_ESR1_TWRNINT_WIDTH                   1
+#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK                      0x40000u
+#define CAN_ESR1_SYNCH_SHIFT                     18
+#define CAN_ESR1_SYNCH_WIDTH                     1
+#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
+/* IMASK1 Bit Fields */
+#define CAN_IMASK1_BUFLM_MASK                    0xFFFFFFFFu
+#define CAN_IMASK1_BUFLM_SHIFT                   0
+#define CAN_IMASK1_BUFLM_WIDTH                   32
+#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
+/* IFLAG1 Bit Fields */
+#define CAN_IFLAG1_BUF0I_MASK                    0x1u
+#define CAN_IFLAG1_BUF0I_SHIFT                   0
+#define CAN_IFLAG1_BUF0I_WIDTH                   1
+#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF4TO1I_MASK                 0x1Eu
+#define CAN_IFLAG1_BUF4TO1I_SHIFT                1
+#define CAN_IFLAG1_BUF4TO1I_WIDTH                4
+#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK                    0x20u
+#define CAN_IFLAG1_BUF5I_SHIFT                   5
+#define CAN_IFLAG1_BUF5I_WIDTH                   1
+#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK                    0x40u
+#define CAN_IFLAG1_BUF6I_SHIFT                   6
+#define CAN_IFLAG1_BUF6I_WIDTH                   1
+#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK                    0x80u
+#define CAN_IFLAG1_BUF7I_SHIFT                   7
+#define CAN_IFLAG1_BUF7I_WIDTH                   1
+#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK                0xFFFFFF00u
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               8
+#define CAN_IFLAG1_BUF31TO8I_WIDTH               24
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
+/* CTRL2 Bit Fields */
+#define CAN_CTRL2_EACEN_MASK                     0x10000u
+#define CAN_CTRL2_EACEN_SHIFT                    16
+#define CAN_CTRL2_EACEN_WIDTH                    1
+#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK                       0x20000u
+#define CAN_CTRL2_RRS_SHIFT                      17
+#define CAN_CTRL2_RRS_WIDTH                      1
+#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK                       0x40000u
+#define CAN_CTRL2_MRP_SHIFT                      18
+#define CAN_CTRL2_MRP_WIDTH                      1
+#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK                      0xF80000u
+#define CAN_CTRL2_TASD_SHIFT                     19
+#define CAN_CTRL2_TASD_WIDTH                     5
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK                      0xF000000u
+#define CAN_CTRL2_RFFN_SHIFT                     24
+#define CAN_CTRL2_RFFN_WIDTH                     4
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK                    0x10000000u
+#define CAN_CTRL2_WRMFRZ_SHIFT                   28
+#define CAN_CTRL2_WRMFRZ_WIDTH                   1
+#define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_WRMFRZ_SHIFT))&CAN_CTRL2_WRMFRZ_MASK)
+/* ESR2 Bit Fields */
+#define CAN_ESR2_IMB_MASK                        0x2000u
+#define CAN_ESR2_IMB_SHIFT                       13
+#define CAN_ESR2_IMB_WIDTH                       1
+#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK                        0x4000u
+#define CAN_ESR2_VPS_SHIFT                       14
+#define CAN_ESR2_VPS_WIDTH                       1
+#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK                       0x7F0000u
+#define CAN_ESR2_LPTM_SHIFT                      16
+#define CAN_ESR2_LPTM_WIDTH                      7
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
+/* CRCR Bit Fields */
+#define CAN_CRCR_TXCRC_MASK                      0x7FFFu
+#define CAN_CRCR_TXCRC_SHIFT                     0
+#define CAN_CRCR_TXCRC_WIDTH                     15
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK                      0x7F0000u
+#define CAN_CRCR_MBCRC_SHIFT                     16
+#define CAN_CRCR_MBCRC_WIDTH                     7
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
+/* RXFGMASK Bit Fields */
+#define CAN_RXFGMASK_FGM_MASK                    0xFFFFFFFFu
+#define CAN_RXFGMASK_FGM_SHIFT                   0
+#define CAN_RXFGMASK_FGM_WIDTH                   32
+#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
+/* RXFIR Bit Fields */
+#define CAN_RXFIR_IDHIT_MASK                     0x1FFu
+#define CAN_RXFIR_IDHIT_SHIFT                    0
+#define CAN_RXFIR_IDHIT_WIDTH                    9
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
+/* CS Bit Fields */
+#define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
+#define CAN_CS_TIME_STAMP_SHIFT                  0
+#define CAN_CS_TIME_STAMP_WIDTH                  16
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK                          0xF0000u
+#define CAN_CS_DLC_SHIFT                         16
+#define CAN_CS_DLC_WIDTH                         4
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK                          0x100000u
+#define CAN_CS_RTR_SHIFT                         20
+#define CAN_CS_RTR_WIDTH                         1
+#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_RTR_SHIFT))&CAN_CS_RTR_MASK)
+#define CAN_CS_IDE_MASK                          0x200000u
+#define CAN_CS_IDE_SHIFT                         21
+#define CAN_CS_IDE_WIDTH                         1
+#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_IDE_SHIFT))&CAN_CS_IDE_MASK)
+#define CAN_CS_SRR_MASK                          0x400000u
+#define CAN_CS_SRR_SHIFT                         22
+#define CAN_CS_SRR_WIDTH                         1
+#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_SRR_SHIFT))&CAN_CS_SRR_MASK)
+#define CAN_CS_CODE_MASK                         0xF000000u
+#define CAN_CS_CODE_SHIFT                        24
+#define CAN_CS_CODE_WIDTH                        4
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
+/* ID Bit Fields */
+#define CAN_ID_EXT_MASK                          0x3FFFFu
+#define CAN_ID_EXT_SHIFT                         0
+#define CAN_ID_EXT_WIDTH                         18
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK                          0x1FFC0000u
+#define CAN_ID_STD_SHIFT                         18
+#define CAN_ID_STD_WIDTH                         11
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK                         0xE0000000u
+#define CAN_ID_PRIO_SHIFT                        29
+#define CAN_ID_PRIO_WIDTH                        3
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
+/* WORD0 Bit Fields */
+#define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              0
+#define CAN_WORD0_DATA_BYTE_3_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              8
+#define CAN_WORD0_DATA_BYTE_2_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              16
+#define CAN_WORD0_DATA_BYTE_1_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              24
+#define CAN_WORD0_DATA_BYTE_0_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
+/* WORD1 Bit Fields */
+#define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              0
+#define CAN_WORD1_DATA_BYTE_7_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              8
+#define CAN_WORD1_DATA_BYTE_6_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              16
+#define CAN_WORD1_DATA_BYTE_5_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              24
+#define CAN_WORD1_DATA_BYTE_4_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
+/* RXIMR Bit Fields */
+#define CAN_RXIMR_MI_MASK                        0xFFFFFFFFu
+#define CAN_RXIMR_MI_SHIFT                       0
+#define CAN_RXIMR_MI_WIDTH                       32
+#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+#define CAN0_BASE_PTR                            (CAN0)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS                      { CAN0_Rx_Warning_IRQn }
+#define CAN_Tx_Warning_IRQS                      { CAN0_Tx_Warning_IRQn }
+#define CAN_Wake_Up_IRQS                         { CAN0_Wake_Up_IRQn }
+#define CAN_Error_IRQS                           { CAN0_Error_IRQn }
+#define CAN_Bus_Off_IRQS                         { CAN0_Bus_Off_IRQn }
+#define CAN_ORed_Message_buffer_IRQS             { CAN0_ORed_Message_buffer_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register instance definitions */
+/* CAN0 */
+#define CAN0_MCR                                 CAN_MCR_REG(CAN0)
+#define CAN0_CTRL1                               CAN_CTRL1_REG(CAN0)
+#define CAN0_TIMER                               CAN_TIMER_REG(CAN0)
+#define CAN0_RXMGMASK                            CAN_RXMGMASK_REG(CAN0)
+#define CAN0_RX14MASK                            CAN_RX14MASK_REG(CAN0)
+#define CAN0_RX15MASK                            CAN_RX15MASK_REG(CAN0)
+#define CAN0_ECR                                 CAN_ECR_REG(CAN0)
+#define CAN0_ESR1                                CAN_ESR1_REG(CAN0)
+#define CAN0_IMASK1                              CAN_IMASK1_REG(CAN0)
+#define CAN0_IFLAG1                              CAN_IFLAG1_REG(CAN0)
+#define CAN0_CTRL2                               CAN_CTRL2_REG(CAN0)
+#define CAN0_ESR2                                CAN_ESR2_REG(CAN0)
+#define CAN0_CRCR                                CAN_CRCR_REG(CAN0)
+#define CAN0_RXFGMASK                            CAN_RXFGMASK_REG(CAN0)
+#define CAN0_RXFIR                               CAN_RXFIR_REG(CAN0)
+#define CAN0_CS0                                 CAN_CS_REG(CAN0,0)
+#define CAN0_ID0                                 CAN_ID_REG(CAN0,0)
+#define CAN0_WORD00                              CAN_WORD0_REG(CAN0,0)
+#define CAN0_WORD10                              CAN_WORD1_REG(CAN0,0)
+#define CAN0_CS1                                 CAN_CS_REG(CAN0,1)
+#define CAN0_ID1                                 CAN_ID_REG(CAN0,1)
+#define CAN0_WORD01                              CAN_WORD0_REG(CAN0,1)
+#define CAN0_WORD11                              CAN_WORD1_REG(CAN0,1)
+#define CAN0_CS2                                 CAN_CS_REG(CAN0,2)
+#define CAN0_ID2                                 CAN_ID_REG(CAN0,2)
+#define CAN0_WORD02                              CAN_WORD0_REG(CAN0,2)
+#define CAN0_WORD12                              CAN_WORD1_REG(CAN0,2)
+#define CAN0_CS3                                 CAN_CS_REG(CAN0,3)
+#define CAN0_ID3                                 CAN_ID_REG(CAN0,3)
+#define CAN0_WORD03                              CAN_WORD0_REG(CAN0,3)
+#define CAN0_WORD13                              CAN_WORD1_REG(CAN0,3)
+#define CAN0_CS4                                 CAN_CS_REG(CAN0,4)
+#define CAN0_ID4                                 CAN_ID_REG(CAN0,4)
+#define CAN0_WORD04                              CAN_WORD0_REG(CAN0,4)
+#define CAN0_WORD14                              CAN_WORD1_REG(CAN0,4)
+#define CAN0_CS5                                 CAN_CS_REG(CAN0,5)
+#define CAN0_ID5                                 CAN_ID_REG(CAN0,5)
+#define CAN0_WORD05                              CAN_WORD0_REG(CAN0,5)
+#define CAN0_WORD15                              CAN_WORD1_REG(CAN0,5)
+#define CAN0_CS6                                 CAN_CS_REG(CAN0,6)
+#define CAN0_ID6                                 CAN_ID_REG(CAN0,6)
+#define CAN0_WORD06                              CAN_WORD0_REG(CAN0,6)
+#define CAN0_WORD16                              CAN_WORD1_REG(CAN0,6)
+#define CAN0_CS7                                 CAN_CS_REG(CAN0,7)
+#define CAN0_ID7                                 CAN_ID_REG(CAN0,7)
+#define CAN0_WORD07                              CAN_WORD0_REG(CAN0,7)
+#define CAN0_WORD17                              CAN_WORD1_REG(CAN0,7)
+#define CAN0_CS8                                 CAN_CS_REG(CAN0,8)
+#define CAN0_ID8                                 CAN_ID_REG(CAN0,8)
+#define CAN0_WORD08                              CAN_WORD0_REG(CAN0,8)
+#define CAN0_WORD18                              CAN_WORD1_REG(CAN0,8)
+#define CAN0_CS9                                 CAN_CS_REG(CAN0,9)
+#define CAN0_ID9                                 CAN_ID_REG(CAN0,9)
+#define CAN0_WORD09                              CAN_WORD0_REG(CAN0,9)
+#define CAN0_WORD19                              CAN_WORD1_REG(CAN0,9)
+#define CAN0_CS10                                CAN_CS_REG(CAN0,10)
+#define CAN0_ID10                                CAN_ID_REG(CAN0,10)
+#define CAN0_WORD010                             CAN_WORD0_REG(CAN0,10)
+#define CAN0_WORD110                             CAN_WORD1_REG(CAN0,10)
+#define CAN0_CS11                                CAN_CS_REG(CAN0,11)
+#define CAN0_ID11                                CAN_ID_REG(CAN0,11)
+#define CAN0_WORD011                             CAN_WORD0_REG(CAN0,11)
+#define CAN0_WORD111                             CAN_WORD1_REG(CAN0,11)
+#define CAN0_CS12                                CAN_CS_REG(CAN0,12)
+#define CAN0_ID12                                CAN_ID_REG(CAN0,12)
+#define CAN0_WORD012                             CAN_WORD0_REG(CAN0,12)
+#define CAN0_WORD112                             CAN_WORD1_REG(CAN0,12)
+#define CAN0_CS13                                CAN_CS_REG(CAN0,13)
+#define CAN0_ID13                                CAN_ID_REG(CAN0,13)
+#define CAN0_WORD013                             CAN_WORD0_REG(CAN0,13)
+#define CAN0_WORD113                             CAN_WORD1_REG(CAN0,13)
+#define CAN0_CS14                                CAN_CS_REG(CAN0,14)
+#define CAN0_ID14                                CAN_ID_REG(CAN0,14)
+#define CAN0_WORD014                             CAN_WORD0_REG(CAN0,14)
+#define CAN0_WORD114                             CAN_WORD1_REG(CAN0,14)
+#define CAN0_CS15                                CAN_CS_REG(CAN0,15)
+#define CAN0_ID15                                CAN_ID_REG(CAN0,15)
+#define CAN0_WORD015                             CAN_WORD0_REG(CAN0,15)
+#define CAN0_WORD115                             CAN_WORD1_REG(CAN0,15)
+#define CAN0_RXIMR0                              CAN_RXIMR_REG(CAN0,0)
+#define CAN0_RXIMR1                              CAN_RXIMR_REG(CAN0,1)
+#define CAN0_RXIMR2                              CAN_RXIMR_REG(CAN0,2)
+#define CAN0_RXIMR3                              CAN_RXIMR_REG(CAN0,3)
+#define CAN0_RXIMR4                              CAN_RXIMR_REG(CAN0,4)
+#define CAN0_RXIMR5                              CAN_RXIMR_REG(CAN0,5)
+#define CAN0_RXIMR6                              CAN_RXIMR_REG(CAN0,6)
+#define CAN0_RXIMR7                              CAN_RXIMR_REG(CAN0,7)
+#define CAN0_RXIMR8                              CAN_RXIMR_REG(CAN0,8)
+#define CAN0_RXIMR9                              CAN_RXIMR_REG(CAN0,9)
+#define CAN0_RXIMR10                             CAN_RXIMR_REG(CAN0,10)
+#define CAN0_RXIMR11                             CAN_RXIMR_REG(CAN0,11)
+#define CAN0_RXIMR12                             CAN_RXIMR_REG(CAN0,12)
+#define CAN0_RXIMR13                             CAN_RXIMR_REG(CAN0,13)
+#define CAN0_RXIMR14                             CAN_RXIMR_REG(CAN0,14)
+#define CAN0_RXIMR15                             CAN_RXIMR_REG(CAN0,15)
+
+/* CAN - Register array accessors */
+#define CAN0_CS(index)                           CAN_CS_REG(CAN0,index)
+#define CAN0_ID(index)                           CAN_ID_REG(CAN0,index)
+#define CAN0_WORD0(index)                        CAN_WORD0_REG(CAN0,index)
+#define CAN0_WORD1(index)                        CAN_WORD1_REG(CAN0,index)
+#define CAN0_RXIMR(index)                        CAN_RXIMR_REG(CAN0,index)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+  __O  uint32_t DIRECT[16];                        /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[2048];
+  __O  uint32_t LDR_CASR;                          /**< Status register - Load Register command, offset: 0x840 */
+  __O  uint32_t LDR_CAA;                           /**< Accumulator register - Load Register command, offset: 0x844 */
+  __O  uint32_t LDR_CA[9];                         /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
+       uint8_t RESERVED_1[20];
+  __I  uint32_t STR_CASR;                          /**< Status register - Store Register command, offset: 0x880 */
+  __I  uint32_t STR_CAA;                           /**< Accumulator register - Store Register command, offset: 0x884 */
+  __I  uint32_t STR_CA[9];                         /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
+       uint8_t RESERVED_2[20];
+  __O  uint32_t ADR_CASR;                          /**< Status register - Add Register command, offset: 0x8C0 */
+  __O  uint32_t ADR_CAA;                           /**< Accumulator register - Add to register command, offset: 0x8C4 */
+  __O  uint32_t ADR_CA[9];                         /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
+       uint8_t RESERVED_3[20];
+  __O  uint32_t RADR_CASR;                         /**< Status register - Reverse and Add to Register command, offset: 0x900 */
+  __O  uint32_t RADR_CAA;                          /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
+  __O  uint32_t RADR_CA[9];                        /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
+       uint8_t RESERVED_4[84];
+  __O  uint32_t XOR_CASR;                          /**< Status register - Exclusive Or command, offset: 0x980 */
+  __O  uint32_t XOR_CAA;                           /**< Accumulator register - Exclusive Or command, offset: 0x984 */
+  __O  uint32_t XOR_CA[9];                         /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
+       uint8_t RESERVED_5[20];
+  __O  uint32_t ROTL_CASR;                         /**< Status register - Rotate Left command, offset: 0x9C0 */
+  __O  uint32_t ROTL_CAA;                          /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
+  __O  uint32_t ROTL_CA[9];                        /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
+       uint8_t RESERVED_6[276];
+  __O  uint32_t AESC_CASR;                         /**< Status register - AES Column Operation command, offset: 0xB00 */
+  __O  uint32_t AESC_CAA;                          /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
+  __O  uint32_t AESC_CA[9];                        /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
+       uint8_t RESERVED_7[20];
+  __O  uint32_t AESIC_CASR;                        /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
+  __O  uint32_t AESIC_CAA;                         /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
+  __O  uint32_t AESIC_CA[9];                       /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
+} CAU_Type, *CAU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register accessors */
+#define CAU_DIRECT_REG(base,index)               ((base)->DIRECT[index])
+#define CAU_DIRECT_COUNT                         16
+#define CAU_LDR_CASR_REG(base)                   ((base)->LDR_CASR)
+#define CAU_LDR_CAA_REG(base)                    ((base)->LDR_CAA)
+#define CAU_LDR_CA_REG(base,index)               ((base)->LDR_CA[index])
+#define CAU_LDR_CA_COUNT                         9
+#define CAU_STR_CASR_REG(base)                   ((base)->STR_CASR)
+#define CAU_STR_CAA_REG(base)                    ((base)->STR_CAA)
+#define CAU_STR_CA_REG(base,index)               ((base)->STR_CA[index])
+#define CAU_STR_CA_COUNT                         9
+#define CAU_ADR_CASR_REG(base)                   ((base)->ADR_CASR)
+#define CAU_ADR_CAA_REG(base)                    ((base)->ADR_CAA)
+#define CAU_ADR_CA_REG(base,index)               ((base)->ADR_CA[index])
+#define CAU_ADR_CA_COUNT                         9
+#define CAU_RADR_CASR_REG(base)                  ((base)->RADR_CASR)
+#define CAU_RADR_CAA_REG(base)                   ((base)->RADR_CAA)
+#define CAU_RADR_CA_REG(base,index)              ((base)->RADR_CA[index])
+#define CAU_RADR_CA_COUNT                        9
+#define CAU_XOR_CASR_REG(base)                   ((base)->XOR_CASR)
+#define CAU_XOR_CAA_REG(base)                    ((base)->XOR_CAA)
+#define CAU_XOR_CA_REG(base,index)               ((base)->XOR_CA[index])
+#define CAU_XOR_CA_COUNT                         9
+#define CAU_ROTL_CASR_REG(base)                  ((base)->ROTL_CASR)
+#define CAU_ROTL_CAA_REG(base)                   ((base)->ROTL_CAA)
+#define CAU_ROTL_CA_REG(base,index)              ((base)->ROTL_CA[index])
+#define CAU_ROTL_CA_COUNT                        9
+#define CAU_AESC_CASR_REG(base)                  ((base)->AESC_CASR)
+#define CAU_AESC_CAA_REG(base)                   ((base)->AESC_CAA)
+#define CAU_AESC_CA_REG(base,index)              ((base)->AESC_CA[index])
+#define CAU_AESC_CA_COUNT                        9
+#define CAU_AESIC_CASR_REG(base)                 ((base)->AESIC_CASR)
+#define CAU_AESIC_CAA_REG(base)                  ((base)->AESIC_CAA)
+#define CAU_AESIC_CA_REG(base,index)             ((base)->AESIC_CA[index])
+#define CAU_AESIC_CA_COUNT                       9
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/* DIRECT Bit Fields */
+#define CAU_DIRECT_CAU_DIRECT0_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT0_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT0_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT0(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
+#define CAU_DIRECT_CAU_DIRECT1_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT1_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT1_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT1(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
+#define CAU_DIRECT_CAU_DIRECT2_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT2_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT2_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT2(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
+#define CAU_DIRECT_CAU_DIRECT3_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT3_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT3_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT3(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
+#define CAU_DIRECT_CAU_DIRECT4_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT4_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT4_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT4(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
+#define CAU_DIRECT_CAU_DIRECT5_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT5_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT5_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT5(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
+#define CAU_DIRECT_CAU_DIRECT6_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT6_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT6_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT6(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
+#define CAU_DIRECT_CAU_DIRECT7_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT7_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT7_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT7(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
+#define CAU_DIRECT_CAU_DIRECT8_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT8_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT8_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT8(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
+#define CAU_DIRECT_CAU_DIRECT9_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT9_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT9_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT9(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
+#define CAU_DIRECT_CAU_DIRECT10_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT10_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT10_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT10(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
+#define CAU_DIRECT_CAU_DIRECT11_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT11_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT11_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT11(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
+#define CAU_DIRECT_CAU_DIRECT12_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT12_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT12_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT12(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
+#define CAU_DIRECT_CAU_DIRECT13_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT13_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT13_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT13(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
+#define CAU_DIRECT_CAU_DIRECT14_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT14_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT14_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT14(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
+#define CAU_DIRECT_CAU_DIRECT15_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT15_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT15_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT15(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
+/* LDR_CASR Bit Fields */
+#define CAU_LDR_CASR_IC_MASK                     0x1u
+#define CAU_LDR_CASR_IC_SHIFT                    0
+#define CAU_LDR_CASR_IC_WIDTH                    1
+#define CAU_LDR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_IC_SHIFT))&CAU_LDR_CASR_IC_MASK)
+#define CAU_LDR_CASR_DPE_MASK                    0x2u
+#define CAU_LDR_CASR_DPE_SHIFT                   1
+#define CAU_LDR_CASR_DPE_WIDTH                   1
+#define CAU_LDR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_DPE_SHIFT))&CAU_LDR_CASR_DPE_MASK)
+#define CAU_LDR_CASR_VER_MASK                    0xF0000000u
+#define CAU_LDR_CASR_VER_SHIFT                   28
+#define CAU_LDR_CASR_VER_WIDTH                   4
+#define CAU_LDR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
+/* LDR_CAA Bit Fields */
+#define CAU_LDR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_LDR_CAA_ACC_SHIFT                    0
+#define CAU_LDR_CAA_ACC_WIDTH                    32
+#define CAU_LDR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
+/* LDR_CA Bit Fields */
+#define CAU_LDR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA0_SHIFT                     0
+#define CAU_LDR_CA_CA0_WIDTH                     32
+#define CAU_LDR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
+#define CAU_LDR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA1_SHIFT                     0
+#define CAU_LDR_CA_CA1_WIDTH                     32
+#define CAU_LDR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
+#define CAU_LDR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA2_SHIFT                     0
+#define CAU_LDR_CA_CA2_WIDTH                     32
+#define CAU_LDR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
+#define CAU_LDR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA3_SHIFT                     0
+#define CAU_LDR_CA_CA3_WIDTH                     32
+#define CAU_LDR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
+#define CAU_LDR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA4_SHIFT                     0
+#define CAU_LDR_CA_CA4_WIDTH                     32
+#define CAU_LDR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
+#define CAU_LDR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA5_SHIFT                     0
+#define CAU_LDR_CA_CA5_WIDTH                     32
+#define CAU_LDR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
+#define CAU_LDR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA6_SHIFT                     0
+#define CAU_LDR_CA_CA6_WIDTH                     32
+#define CAU_LDR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
+#define CAU_LDR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA7_SHIFT                     0
+#define CAU_LDR_CA_CA7_WIDTH                     32
+#define CAU_LDR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
+#define CAU_LDR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA8_SHIFT                     0
+#define CAU_LDR_CA_CA8_WIDTH                     32
+#define CAU_LDR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
+/* STR_CASR Bit Fields */
+#define CAU_STR_CASR_IC_MASK                     0x1u
+#define CAU_STR_CASR_IC_SHIFT                    0
+#define CAU_STR_CASR_IC_WIDTH                    1
+#define CAU_STR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_IC_SHIFT))&CAU_STR_CASR_IC_MASK)
+#define CAU_STR_CASR_DPE_MASK                    0x2u
+#define CAU_STR_CASR_DPE_SHIFT                   1
+#define CAU_STR_CASR_DPE_WIDTH                   1
+#define CAU_STR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_DPE_SHIFT))&CAU_STR_CASR_DPE_MASK)
+#define CAU_STR_CASR_VER_MASK                    0xF0000000u
+#define CAU_STR_CASR_VER_SHIFT                   28
+#define CAU_STR_CASR_VER_WIDTH                   4
+#define CAU_STR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
+/* STR_CAA Bit Fields */
+#define CAU_STR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_STR_CAA_ACC_SHIFT                    0
+#define CAU_STR_CAA_ACC_WIDTH                    32
+#define CAU_STR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
+/* STR_CA Bit Fields */
+#define CAU_STR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA0_SHIFT                     0
+#define CAU_STR_CA_CA0_WIDTH                     32
+#define CAU_STR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
+#define CAU_STR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA1_SHIFT                     0
+#define CAU_STR_CA_CA1_WIDTH                     32
+#define CAU_STR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
+#define CAU_STR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA2_SHIFT                     0
+#define CAU_STR_CA_CA2_WIDTH                     32
+#define CAU_STR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
+#define CAU_STR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA3_SHIFT                     0
+#define CAU_STR_CA_CA3_WIDTH                     32
+#define CAU_STR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
+#define CAU_STR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA4_SHIFT                     0
+#define CAU_STR_CA_CA4_WIDTH                     32
+#define CAU_STR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
+#define CAU_STR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA5_SHIFT                     0
+#define CAU_STR_CA_CA5_WIDTH                     32
+#define CAU_STR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
+#define CAU_STR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA6_SHIFT                     0
+#define CAU_STR_CA_CA6_WIDTH                     32
+#define CAU_STR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
+#define CAU_STR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA7_SHIFT                     0
+#define CAU_STR_CA_CA7_WIDTH                     32
+#define CAU_STR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
+#define CAU_STR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA8_SHIFT                     0
+#define CAU_STR_CA_CA8_WIDTH                     32
+#define CAU_STR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
+/* ADR_CASR Bit Fields */
+#define CAU_ADR_CASR_IC_MASK                     0x1u
+#define CAU_ADR_CASR_IC_SHIFT                    0
+#define CAU_ADR_CASR_IC_WIDTH                    1
+#define CAU_ADR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_IC_SHIFT))&CAU_ADR_CASR_IC_MASK)
+#define CAU_ADR_CASR_DPE_MASK                    0x2u
+#define CAU_ADR_CASR_DPE_SHIFT                   1
+#define CAU_ADR_CASR_DPE_WIDTH                   1
+#define CAU_ADR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_DPE_SHIFT))&CAU_ADR_CASR_DPE_MASK)
+#define CAU_ADR_CASR_VER_MASK                    0xF0000000u
+#define CAU_ADR_CASR_VER_SHIFT                   28
+#define CAU_ADR_CASR_VER_WIDTH                   4
+#define CAU_ADR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
+/* ADR_CAA Bit Fields */
+#define CAU_ADR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_ADR_CAA_ACC_SHIFT                    0
+#define CAU_ADR_CAA_ACC_WIDTH                    32
+#define CAU_ADR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
+/* ADR_CA Bit Fields */
+#define CAU_ADR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA0_SHIFT                     0
+#define CAU_ADR_CA_CA0_WIDTH                     32
+#define CAU_ADR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
+#define CAU_ADR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA1_SHIFT                     0
+#define CAU_ADR_CA_CA1_WIDTH                     32
+#define CAU_ADR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
+#define CAU_ADR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA2_SHIFT                     0
+#define CAU_ADR_CA_CA2_WIDTH                     32
+#define CAU_ADR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
+#define CAU_ADR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA3_SHIFT                     0
+#define CAU_ADR_CA_CA3_WIDTH                     32
+#define CAU_ADR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
+#define CAU_ADR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA4_SHIFT                     0
+#define CAU_ADR_CA_CA4_WIDTH                     32
+#define CAU_ADR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
+#define CAU_ADR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA5_SHIFT                     0
+#define CAU_ADR_CA_CA5_WIDTH                     32
+#define CAU_ADR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
+#define CAU_ADR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA6_SHIFT                     0
+#define CAU_ADR_CA_CA6_WIDTH                     32
+#define CAU_ADR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
+#define CAU_ADR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA7_SHIFT                     0
+#define CAU_ADR_CA_CA7_WIDTH                     32
+#define CAU_ADR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
+#define CAU_ADR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA8_SHIFT                     0
+#define CAU_ADR_CA_CA8_WIDTH                     32
+#define CAU_ADR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
+/* RADR_CASR Bit Fields */
+#define CAU_RADR_CASR_IC_MASK                    0x1u
+#define CAU_RADR_CASR_IC_SHIFT                   0
+#define CAU_RADR_CASR_IC_WIDTH                   1
+#define CAU_RADR_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_IC_SHIFT))&CAU_RADR_CASR_IC_MASK)
+#define CAU_RADR_CASR_DPE_MASK                   0x2u
+#define CAU_RADR_CASR_DPE_SHIFT                  1
+#define CAU_RADR_CASR_DPE_WIDTH                  1
+#define CAU_RADR_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_DPE_SHIFT))&CAU_RADR_CASR_DPE_MASK)
+#define CAU_RADR_CASR_VER_MASK                   0xF0000000u
+#define CAU_RADR_CASR_VER_SHIFT                  28
+#define CAU_RADR_CASR_VER_WIDTH                  4
+#define CAU_RADR_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
+/* RADR_CAA Bit Fields */
+#define CAU_RADR_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_RADR_CAA_ACC_SHIFT                   0
+#define CAU_RADR_CAA_ACC_WIDTH                   32
+#define CAU_RADR_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
+/* RADR_CA Bit Fields */
+#define CAU_RADR_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA0_SHIFT                    0
+#define CAU_RADR_CA_CA0_WIDTH                    32
+#define CAU_RADR_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
+#define CAU_RADR_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA1_SHIFT                    0
+#define CAU_RADR_CA_CA1_WIDTH                    32
+#define CAU_RADR_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
+#define CAU_RADR_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA2_SHIFT                    0
+#define CAU_RADR_CA_CA2_WIDTH                    32
+#define CAU_RADR_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
+#define CAU_RADR_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA3_SHIFT                    0
+#define CAU_RADR_CA_CA3_WIDTH                    32
+#define CAU_RADR_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
+#define CAU_RADR_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA4_SHIFT                    0
+#define CAU_RADR_CA_CA4_WIDTH                    32
+#define CAU_RADR_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
+#define CAU_RADR_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA5_SHIFT                    0
+#define CAU_RADR_CA_CA5_WIDTH                    32
+#define CAU_RADR_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
+#define CAU_RADR_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA6_SHIFT                    0
+#define CAU_RADR_CA_CA6_WIDTH                    32
+#define CAU_RADR_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
+#define CAU_RADR_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA7_SHIFT                    0
+#define CAU_RADR_CA_CA7_WIDTH                    32
+#define CAU_RADR_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
+#define CAU_RADR_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA8_SHIFT                    0
+#define CAU_RADR_CA_CA8_WIDTH                    32
+#define CAU_RADR_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
+/* XOR_CASR Bit Fields */
+#define CAU_XOR_CASR_IC_MASK                     0x1u
+#define CAU_XOR_CASR_IC_SHIFT                    0
+#define CAU_XOR_CASR_IC_WIDTH                    1
+#define CAU_XOR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_IC_SHIFT))&CAU_XOR_CASR_IC_MASK)
+#define CAU_XOR_CASR_DPE_MASK                    0x2u
+#define CAU_XOR_CASR_DPE_SHIFT                   1
+#define CAU_XOR_CASR_DPE_WIDTH                   1
+#define CAU_XOR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_DPE_SHIFT))&CAU_XOR_CASR_DPE_MASK)
+#define CAU_XOR_CASR_VER_MASK                    0xF0000000u
+#define CAU_XOR_CASR_VER_SHIFT                   28
+#define CAU_XOR_CASR_VER_WIDTH                   4
+#define CAU_XOR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
+/* XOR_CAA Bit Fields */
+#define CAU_XOR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_XOR_CAA_ACC_SHIFT                    0
+#define CAU_XOR_CAA_ACC_WIDTH                    32
+#define CAU_XOR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
+/* XOR_CA Bit Fields */
+#define CAU_XOR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA0_SHIFT                     0
+#define CAU_XOR_CA_CA0_WIDTH                     32
+#define CAU_XOR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
+#define CAU_XOR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA1_SHIFT                     0
+#define CAU_XOR_CA_CA1_WIDTH                     32
+#define CAU_XOR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
+#define CAU_XOR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA2_SHIFT                     0
+#define CAU_XOR_CA_CA2_WIDTH                     32
+#define CAU_XOR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
+#define CAU_XOR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA3_SHIFT                     0
+#define CAU_XOR_CA_CA3_WIDTH                     32
+#define CAU_XOR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
+#define CAU_XOR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA4_SHIFT                     0
+#define CAU_XOR_CA_CA4_WIDTH                     32
+#define CAU_XOR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
+#define CAU_XOR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA5_SHIFT                     0
+#define CAU_XOR_CA_CA5_WIDTH                     32
+#define CAU_XOR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
+#define CAU_XOR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA6_SHIFT                     0
+#define CAU_XOR_CA_CA6_WIDTH                     32
+#define CAU_XOR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
+#define CAU_XOR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA7_SHIFT                     0
+#define CAU_XOR_CA_CA7_WIDTH                     32
+#define CAU_XOR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
+#define CAU_XOR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA8_SHIFT                     0
+#define CAU_XOR_CA_CA8_WIDTH                     32
+#define CAU_XOR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
+/* ROTL_CASR Bit Fields */
+#define CAU_ROTL_CASR_IC_MASK                    0x1u
+#define CAU_ROTL_CASR_IC_SHIFT                   0
+#define CAU_ROTL_CASR_IC_WIDTH                   1
+#define CAU_ROTL_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_IC_SHIFT))&CAU_ROTL_CASR_IC_MASK)
+#define CAU_ROTL_CASR_DPE_MASK                   0x2u
+#define CAU_ROTL_CASR_DPE_SHIFT                  1
+#define CAU_ROTL_CASR_DPE_WIDTH                  1
+#define CAU_ROTL_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_DPE_SHIFT))&CAU_ROTL_CASR_DPE_MASK)
+#define CAU_ROTL_CASR_VER_MASK                   0xF0000000u
+#define CAU_ROTL_CASR_VER_SHIFT                  28
+#define CAU_ROTL_CASR_VER_WIDTH                  4
+#define CAU_ROTL_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
+/* ROTL_CAA Bit Fields */
+#define CAU_ROTL_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_ROTL_CAA_ACC_SHIFT                   0
+#define CAU_ROTL_CAA_ACC_WIDTH                   32
+#define CAU_ROTL_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
+/* ROTL_CA Bit Fields */
+#define CAU_ROTL_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA0_SHIFT                    0
+#define CAU_ROTL_CA_CA0_WIDTH                    32
+#define CAU_ROTL_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
+#define CAU_ROTL_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA1_SHIFT                    0
+#define CAU_ROTL_CA_CA1_WIDTH                    32
+#define CAU_ROTL_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
+#define CAU_ROTL_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA2_SHIFT                    0
+#define CAU_ROTL_CA_CA2_WIDTH                    32
+#define CAU_ROTL_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
+#define CAU_ROTL_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA3_SHIFT                    0
+#define CAU_ROTL_CA_CA3_WIDTH                    32
+#define CAU_ROTL_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
+#define CAU_ROTL_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA4_SHIFT                    0
+#define CAU_ROTL_CA_CA4_WIDTH                    32
+#define CAU_ROTL_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
+#define CAU_ROTL_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA5_SHIFT                    0
+#define CAU_ROTL_CA_CA5_WIDTH                    32
+#define CAU_ROTL_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
+#define CAU_ROTL_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA6_SHIFT                    0
+#define CAU_ROTL_CA_CA6_WIDTH                    32
+#define CAU_ROTL_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
+#define CAU_ROTL_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA7_SHIFT                    0
+#define CAU_ROTL_CA_CA7_WIDTH                    32
+#define CAU_ROTL_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
+#define CAU_ROTL_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA8_SHIFT                    0
+#define CAU_ROTL_CA_CA8_WIDTH                    32
+#define CAU_ROTL_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
+/* AESC_CASR Bit Fields */
+#define CAU_AESC_CASR_IC_MASK                    0x1u
+#define CAU_AESC_CASR_IC_SHIFT                   0
+#define CAU_AESC_CASR_IC_WIDTH                   1
+#define CAU_AESC_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_IC_SHIFT))&CAU_AESC_CASR_IC_MASK)
+#define CAU_AESC_CASR_DPE_MASK                   0x2u
+#define CAU_AESC_CASR_DPE_SHIFT                  1
+#define CAU_AESC_CASR_DPE_WIDTH                  1
+#define CAU_AESC_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_DPE_SHIFT))&CAU_AESC_CASR_DPE_MASK)
+#define CAU_AESC_CASR_VER_MASK                   0xF0000000u
+#define CAU_AESC_CASR_VER_SHIFT                  28
+#define CAU_AESC_CASR_VER_WIDTH                  4
+#define CAU_AESC_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
+/* AESC_CAA Bit Fields */
+#define CAU_AESC_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_AESC_CAA_ACC_SHIFT                   0
+#define CAU_AESC_CAA_ACC_WIDTH                   32
+#define CAU_AESC_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
+/* AESC_CA Bit Fields */
+#define CAU_AESC_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA0_SHIFT                    0
+#define CAU_AESC_CA_CA0_WIDTH                    32
+#define CAU_AESC_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
+#define CAU_AESC_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA1_SHIFT                    0
+#define CAU_AESC_CA_CA1_WIDTH                    32
+#define CAU_AESC_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
+#define CAU_AESC_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA2_SHIFT                    0
+#define CAU_AESC_CA_CA2_WIDTH                    32
+#define CAU_AESC_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
+#define CAU_AESC_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA3_SHIFT                    0
+#define CAU_AESC_CA_CA3_WIDTH                    32
+#define CAU_AESC_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
+#define CAU_AESC_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA4_SHIFT                    0
+#define CAU_AESC_CA_CA4_WIDTH                    32
+#define CAU_AESC_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
+#define CAU_AESC_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA5_SHIFT                    0
+#define CAU_AESC_CA_CA5_WIDTH                    32
+#define CAU_AESC_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
+#define CAU_AESC_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA6_SHIFT                    0
+#define CAU_AESC_CA_CA6_WIDTH                    32
+#define CAU_AESC_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
+#define CAU_AESC_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA7_SHIFT                    0
+#define CAU_AESC_CA_CA7_WIDTH                    32
+#define CAU_AESC_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
+#define CAU_AESC_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA8_SHIFT                    0
+#define CAU_AESC_CA_CA8_WIDTH                    32
+#define CAU_AESC_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
+/* AESIC_CASR Bit Fields */
+#define CAU_AESIC_CASR_IC_MASK                   0x1u
+#define CAU_AESIC_CASR_IC_SHIFT                  0
+#define CAU_AESIC_CASR_IC_WIDTH                  1
+#define CAU_AESIC_CASR_IC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_IC_SHIFT))&CAU_AESIC_CASR_IC_MASK)
+#define CAU_AESIC_CASR_DPE_MASK                  0x2u
+#define CAU_AESIC_CASR_DPE_SHIFT                 1
+#define CAU_AESIC_CASR_DPE_WIDTH                 1
+#define CAU_AESIC_CASR_DPE(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_DPE_SHIFT))&CAU_AESIC_CASR_DPE_MASK)
+#define CAU_AESIC_CASR_VER_MASK                  0xF0000000u
+#define CAU_AESIC_CASR_VER_SHIFT                 28
+#define CAU_AESIC_CASR_VER_WIDTH                 4
+#define CAU_AESIC_CASR_VER(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
+/* AESIC_CAA Bit Fields */
+#define CAU_AESIC_CAA_ACC_MASK                   0xFFFFFFFFu
+#define CAU_AESIC_CAA_ACC_SHIFT                  0
+#define CAU_AESIC_CAA_ACC_WIDTH                  32
+#define CAU_AESIC_CAA_ACC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
+/* AESIC_CA Bit Fields */
+#define CAU_AESIC_CA_CA0_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA0_SHIFT                   0
+#define CAU_AESIC_CA_CA0_WIDTH                   32
+#define CAU_AESIC_CA_CA0(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
+#define CAU_AESIC_CA_CA1_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA1_SHIFT                   0
+#define CAU_AESIC_CA_CA1_WIDTH                   32
+#define CAU_AESIC_CA_CA1(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
+#define CAU_AESIC_CA_CA2_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA2_SHIFT                   0
+#define CAU_AESIC_CA_CA2_WIDTH                   32
+#define CAU_AESIC_CA_CA2(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
+#define CAU_AESIC_CA_CA3_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA3_SHIFT                   0
+#define CAU_AESIC_CA_CA3_WIDTH                   32
+#define CAU_AESIC_CA_CA3(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
+#define CAU_AESIC_CA_CA4_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA4_SHIFT                   0
+#define CAU_AESIC_CA_CA4_WIDTH                   32
+#define CAU_AESIC_CA_CA4(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
+#define CAU_AESIC_CA_CA5_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA5_SHIFT                   0
+#define CAU_AESIC_CA_CA5_WIDTH                   32
+#define CAU_AESIC_CA_CA5(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
+#define CAU_AESIC_CA_CA6_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA6_SHIFT                   0
+#define CAU_AESIC_CA_CA6_WIDTH                   32
+#define CAU_AESIC_CA_CA6(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
+#define CAU_AESIC_CA_CA7_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA7_SHIFT                   0
+#define CAU_AESIC_CA_CA7_WIDTH                   32
+#define CAU_AESIC_CA_CA7(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
+#define CAU_AESIC_CA_CA8_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA8_SHIFT                   0
+#define CAU_AESIC_CA_CA8_WIDTH                   32
+#define CAU_AESIC_CA_CA8(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+/** Peripheral CAU base address */
+#define CAU_BASE                                 (0xE0081000u)
+/** Peripheral CAU base pointer */
+#define CAU                                      ((CAU_Type *)CAU_BASE)
+#define CAU_BASE_PTR                             (CAU)
+/** Array initializer of CAU peripheral base addresses */
+#define CAU_BASE_ADDRS                           { CAU_BASE }
+/** Array initializer of CAU peripheral base pointers */
+#define CAU_BASE_PTRS                            { CAU }
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register instance definitions */
+/* CAU */
+#define CAU_DIRECT0                              CAU_DIRECT_REG(CAU,0)
+#define CAU_DIRECT1                              CAU_DIRECT_REG(CAU,1)
+#define CAU_DIRECT2                              CAU_DIRECT_REG(CAU,2)
+#define CAU_DIRECT3                              CAU_DIRECT_REG(CAU,3)
+#define CAU_DIRECT4                              CAU_DIRECT_REG(CAU,4)
+#define CAU_DIRECT5                              CAU_DIRECT_REG(CAU,5)
+#define CAU_DIRECT6                              CAU_DIRECT_REG(CAU,6)
+#define CAU_DIRECT7                              CAU_DIRECT_REG(CAU,7)
+#define CAU_DIRECT8                              CAU_DIRECT_REG(CAU,8)
+#define CAU_DIRECT9                              CAU_DIRECT_REG(CAU,9)
+#define CAU_DIRECT10                             CAU_DIRECT_REG(CAU,10)
+#define CAU_DIRECT11                             CAU_DIRECT_REG(CAU,11)
+#define CAU_DIRECT12                             CAU_DIRECT_REG(CAU,12)
+#define CAU_DIRECT13                             CAU_DIRECT_REG(CAU,13)
+#define CAU_DIRECT14                             CAU_DIRECT_REG(CAU,14)
+#define CAU_DIRECT15                             CAU_DIRECT_REG(CAU,15)
+#define CAU_LDR_CASR                             CAU_LDR_CASR_REG(CAU)
+#define CAU_LDR_CAA                              CAU_LDR_CAA_REG(CAU)
+#define CAU_LDR_CA0                              CAU_LDR_CA_REG(CAU,0)
+#define CAU_LDR_CA1                              CAU_LDR_CA_REG(CAU,1)
+#define CAU_LDR_CA2                              CAU_LDR_CA_REG(CAU,2)
+#define CAU_LDR_CA3                              CAU_LDR_CA_REG(CAU,3)
+#define CAU_LDR_CA4                              CAU_LDR_CA_REG(CAU,4)
+#define CAU_LDR_CA5                              CAU_LDR_CA_REG(CAU,5)
+#define CAU_LDR_CA6                              CAU_LDR_CA_REG(CAU,6)
+#define CAU_LDR_CA7                              CAU_LDR_CA_REG(CAU,7)
+#define CAU_LDR_CA8                              CAU_LDR_CA_REG(CAU,8)
+#define CAU_STR_CASR                             CAU_STR_CASR_REG(CAU)
+#define CAU_STR_CAA                              CAU_STR_CAA_REG(CAU)
+#define CAU_STR_CA0                              CAU_STR_CA_REG(CAU,0)
+#define CAU_STR_CA1                              CAU_STR_CA_REG(CAU,1)
+#define CAU_STR_CA2                              CAU_STR_CA_REG(CAU,2)
+#define CAU_STR_CA3                              CAU_STR_CA_REG(CAU,3)
+#define CAU_STR_CA4                              CAU_STR_CA_REG(CAU,4)
+#define CAU_STR_CA5                              CAU_STR_CA_REG(CAU,5)
+#define CAU_STR_CA6                              CAU_STR_CA_REG(CAU,6)
+#define CAU_STR_CA7                              CAU_STR_CA_REG(CAU,7)
+#define CAU_STR_CA8                              CAU_STR_CA_REG(CAU,8)
+#define CAU_ADR_CASR                             CAU_ADR_CASR_REG(CAU)
+#define CAU_ADR_CAA                              CAU_ADR_CAA_REG(CAU)
+#define CAU_ADR_CA0                              CAU_ADR_CA_REG(CAU,0)
+#define CAU_ADR_CA1                              CAU_ADR_CA_REG(CAU,1)
+#define CAU_ADR_CA2                              CAU_ADR_CA_REG(CAU,2)
+#define CAU_ADR_CA3                              CAU_ADR_CA_REG(CAU,3)
+#define CAU_ADR_CA4                              CAU_ADR_CA_REG(CAU,4)
+#define CAU_ADR_CA5                              CAU_ADR_CA_REG(CAU,5)
+#define CAU_ADR_CA6                              CAU_ADR_CA_REG(CAU,6)
+#define CAU_ADR_CA7                              CAU_ADR_CA_REG(CAU,7)
+#define CAU_ADR_CA8                              CAU_ADR_CA_REG(CAU,8)
+#define CAU_RADR_CASR                            CAU_RADR_CASR_REG(CAU)
+#define CAU_RADR_CAA                             CAU_RADR_CAA_REG(CAU)
+#define CAU_RADR_CA0                             CAU_RADR_CA_REG(CAU,0)
+#define CAU_RADR_CA1                             CAU_RADR_CA_REG(CAU,1)
+#define CAU_RADR_CA2                             CAU_RADR_CA_REG(CAU,2)
+#define CAU_RADR_CA3                             CAU_RADR_CA_REG(CAU,3)
+#define CAU_RADR_CA4                             CAU_RADR_CA_REG(CAU,4)
+#define CAU_RADR_CA5                             CAU_RADR_CA_REG(CAU,5)
+#define CAU_RADR_CA6                             CAU_RADR_CA_REG(CAU,6)
+#define CAU_RADR_CA7                             CAU_RADR_CA_REG(CAU,7)
+#define CAU_RADR_CA8                             CAU_RADR_CA_REG(CAU,8)
+#define CAU_XOR_CASR                             CAU_XOR_CASR_REG(CAU)
+#define CAU_XOR_CAA                              CAU_XOR_CAA_REG(CAU)
+#define CAU_XOR_CA0                              CAU_XOR_CA_REG(CAU,0)
+#define CAU_XOR_CA1                              CAU_XOR_CA_REG(CAU,1)
+#define CAU_XOR_CA2                              CAU_XOR_CA_REG(CAU,2)
+#define CAU_XOR_CA3                              CAU_XOR_CA_REG(CAU,3)
+#define CAU_XOR_CA4                              CAU_XOR_CA_REG(CAU,4)
+#define CAU_XOR_CA5                              CAU_XOR_CA_REG(CAU,5)
+#define CAU_XOR_CA6                              CAU_XOR_CA_REG(CAU,6)
+#define CAU_XOR_CA7                              CAU_XOR_CA_REG(CAU,7)
+#define CAU_XOR_CA8                              CAU_XOR_CA_REG(CAU,8)
+#define CAU_ROTL_CASR                            CAU_ROTL_CASR_REG(CAU)
+#define CAU_ROTL_CAA                             CAU_ROTL_CAA_REG(CAU)
+#define CAU_ROTL_CA0                             CAU_ROTL_CA_REG(CAU,0)
+#define CAU_ROTL_CA1                             CAU_ROTL_CA_REG(CAU,1)
+#define CAU_ROTL_CA2                             CAU_ROTL_CA_REG(CAU,2)
+#define CAU_ROTL_CA3                             CAU_ROTL_CA_REG(CAU,3)
+#define CAU_ROTL_CA4                             CAU_ROTL_CA_REG(CAU,4)
+#define CAU_ROTL_CA5                             CAU_ROTL_CA_REG(CAU,5)
+#define CAU_ROTL_CA6                             CAU_ROTL_CA_REG(CAU,6)
+#define CAU_ROTL_CA7                             CAU_ROTL_CA_REG(CAU,7)
+#define CAU_ROTL_CA8                             CAU_ROTL_CA_REG(CAU,8)
+#define CAU_AESC_CASR                            CAU_AESC_CASR_REG(CAU)
+#define CAU_AESC_CAA                             CAU_AESC_CAA_REG(CAU)
+#define CAU_AESC_CA0                             CAU_AESC_CA_REG(CAU,0)
+#define CAU_AESC_CA1                             CAU_AESC_CA_REG(CAU,1)
+#define CAU_AESC_CA2                             CAU_AESC_CA_REG(CAU,2)
+#define CAU_AESC_CA3                             CAU_AESC_CA_REG(CAU,3)
+#define CAU_AESC_CA4                             CAU_AESC_CA_REG(CAU,4)
+#define CAU_AESC_CA5                             CAU_AESC_CA_REG(CAU,5)
+#define CAU_AESC_CA6                             CAU_AESC_CA_REG(CAU,6)
+#define CAU_AESC_CA7                             CAU_AESC_CA_REG(CAU,7)
+#define CAU_AESC_CA8                             CAU_AESC_CA_REG(CAU,8)
+#define CAU_AESIC_CASR                           CAU_AESIC_CASR_REG(CAU)
+#define CAU_AESIC_CAA                            CAU_AESIC_CAA_REG(CAU)
+#define CAU_AESIC_CA0                            CAU_AESIC_CA_REG(CAU,0)
+#define CAU_AESIC_CA1                            CAU_AESIC_CA_REG(CAU,1)
+#define CAU_AESIC_CA2                            CAU_AESIC_CA_REG(CAU,2)
+#define CAU_AESIC_CA3                            CAU_AESIC_CA_REG(CAU,3)
+#define CAU_AESIC_CA4                            CAU_AESIC_CA_REG(CAU,4)
+#define CAU_AESIC_CA5                            CAU_AESIC_CA_REG(CAU,5)
+#define CAU_AESIC_CA6                            CAU_AESIC_CA_REG(CAU,6)
+#define CAU_AESIC_CA7                            CAU_AESIC_CA_REG(CAU,7)
+#define CAU_AESIC_CA8                            CAU_AESIC_CA_REG(CAU,8)
+
+/* CAU - Register array accessors */
+#define CAU_DIRECT(index)                        CAU_DIRECT_REG(CAU,index)
+#define CAU_LDR_CA(index)                        CAU_LDR_CA_REG(CAU,index)
+#define CAU_STR_CA(index)                        CAU_STR_CA_REG(CAU,index)
+#define CAU_ADR_CA(index)                        CAU_ADR_CA_REG(CAU,index)
+#define CAU_RADR_CA(index)                       CAU_RADR_CA_REG(CAU,index)
+#define CAU_XOR_CA(index)                        CAU_XOR_CA_REG(CAU,index)
+#define CAU_ROTL_CA(index)                       CAU_ROTL_CA_REG(CAU,index)
+#define CAU_AESC_CA(index)                       CAU_AESC_CA_REG(CAU,index)
+#define CAU_AESIC_CA(index)                      CAU_AESIC_CA_REG(CAU,index)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base)                        ((base)->CR0)
+#define CMP_CR1_REG(base)                        ((base)->CR1)
+#define CMP_FPR_REG(base)                        ((base)->FPR)
+#define CMP_SCR_REG(base)                        ((base)->SCR)
+#define CMP_DACCR_REG(base)                      ((base)->DACCR)
+#define CMP_MUXCR_REG(base)                      ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK                     0x3u
+#define CMP_CR0_HYSTCTR_SHIFT                    0
+#define CMP_CR0_HYSTCTR_WIDTH                    2
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT                 4
+#define CMP_CR0_FILTER_CNT_WIDTH                 3
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK                          0x1u
+#define CMP_CR1_EN_SHIFT                         0
+#define CMP_CR1_EN_WIDTH                         1
+#define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK                         0x2u
+#define CMP_CR1_OPE_SHIFT                        1
+#define CMP_CR1_OPE_WIDTH                        1
+#define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK                         0x4u
+#define CMP_CR1_COS_SHIFT                        2
+#define CMP_CR1_COS_WIDTH                        1
+#define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK                         0x8u
+#define CMP_CR1_INV_SHIFT                        3
+#define CMP_CR1_INV_WIDTH                        1
+#define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK                       0x10u
+#define CMP_CR1_PMODE_SHIFT                      4
+#define CMP_CR1_PMODE_WIDTH                      1
+#define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
+#define CMP_CR1_WE_MASK                          0x40u
+#define CMP_CR1_WE_SHIFT                         6
+#define CMP_CR1_WE_WIDTH                         1
+#define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK                          0x80u
+#define CMP_CR1_SE_SHIFT                         7
+#define CMP_CR1_SE_WIDTH                         1
+#define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK                    0xFFu
+#define CMP_FPR_FILT_PER_SHIFT                   0
+#define CMP_FPR_FILT_PER_WIDTH                   8
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK                        0x1u
+#define CMP_SCR_COUT_SHIFT                       0
+#define CMP_SCR_COUT_WIDTH                       1
+#define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK                         0x2u
+#define CMP_SCR_CFF_SHIFT                        1
+#define CMP_SCR_CFF_WIDTH                        1
+#define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK                         0x4u
+#define CMP_SCR_CFR_SHIFT                        2
+#define CMP_SCR_CFR_WIDTH                        1
+#define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK                         0x8u
+#define CMP_SCR_IEF_SHIFT                        3
+#define CMP_SCR_IEF_WIDTH                        1
+#define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK                         0x10u
+#define CMP_SCR_IER_SHIFT                        4
+#define CMP_SCR_IER_WIDTH                        1
+#define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK                       0x40u
+#define CMP_SCR_DMAEN_SHIFT                      6
+#define CMP_SCR_DMAEN_WIDTH                      1
+#define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK                     0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT                    0
+#define CMP_DACCR_VOSEL_WIDTH                    6
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     0x40u
+#define CMP_DACCR_VRSEL_SHIFT                    6
+#define CMP_DACCR_VRSEL_WIDTH                    1
+#define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK                     0x80u
+#define CMP_DACCR_DACEN_SHIFT                    7
+#define CMP_DACCR_DACEN_WIDTH                    1
+#define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK                      0x7u
+#define CMP_MUXCR_MSEL_SHIFT                     0
+#define CMP_MUXCR_MSEL_WIDTH                     3
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      0x38u
+#define CMP_MUXCR_PSEL_SHIFT                     3
+#define CMP_MUXCR_PSEL_WIDTH                     3
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK                      0x80u
+#define CMP_MUXCR_PSTM_SHIFT                     7
+#define CMP_MUXCR_PSTM_WIDTH                     1
+#define CMP_MUXCR_PSTM(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSTM_SHIFT))&CMP_MUXCR_PSTM_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR                            (CMP0)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE                                (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1                                     ((CMP_Type *)CMP1_BASE)
+#define CMP1_BASE_PTR                            (CMP1)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE                                (0x40073010u)
+/** Peripheral CMP2 base pointer */
+#define CMP2                                     ((CMP_Type *)CMP2_BASE)
+#define CMP2_BASE_PTR                            (CMP2)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS                           { CMP0_BASE, CMP1_BASE, CMP2_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS                            { CMP0, CMP1, CMP2 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0                                 CMP_CR0_REG(CMP0)
+#define CMP0_CR1                                 CMP_CR1_REG(CMP0)
+#define CMP0_FPR                                 CMP_FPR_REG(CMP0)
+#define CMP0_SCR                                 CMP_SCR_REG(CMP0)
+#define CMP0_DACCR                               CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR                               CMP_MUXCR_REG(CMP0)
+/* CMP1 */
+#define CMP1_CR0                                 CMP_CR0_REG(CMP1)
+#define CMP1_CR1                                 CMP_CR1_REG(CMP1)
+#define CMP1_FPR                                 CMP_FPR_REG(CMP1)
+#define CMP1_SCR                                 CMP_SCR_REG(CMP1)
+#define CMP1_DACCR                               CMP_DACCR_REG(CMP1)
+#define CMP1_MUXCR                               CMP_MUXCR_REG(CMP1)
+/* CMP2 */
+#define CMP2_CR0                                 CMP_CR0_REG(CMP2)
+#define CMP2_CR1                                 CMP_CR1_REG(CMP2)
+#define CMP2_FPR                                 CMP_FPR_REG(CMP2)
+#define CMP2_SCR                                 CMP_SCR_REG(CMP2)
+#define CMP2_DACCR                               CMP_DACCR_REG(CMP2)
+#define CMP2_MUXCR                               CMP_MUXCR_REG(CMP2)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CGH1;                               /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+  __IO uint8_t CGL1;                               /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+  __IO uint8_t CGH2;                               /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+  __IO uint8_t CGL2;                               /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+  __IO uint8_t OC;                                 /**< CMT Output Control Register, offset: 0x4 */
+  __IO uint8_t MSC;                                /**< CMT Modulator Status and Control Register, offset: 0x5 */
+  __IO uint8_t CMD1;                               /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+  __IO uint8_t CMD2;                               /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+  __IO uint8_t CMD3;                               /**< CMT Modulator Data Register Space High, offset: 0x8 */
+  __IO uint8_t CMD4;                               /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+  __IO uint8_t PPS;                                /**< CMT Primary Prescaler Register, offset: 0xA */
+  __IO uint8_t DMA;                                /**< CMT Direct Memory Access Register, offset: 0xB */
+} CMT_Type, *CMT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register accessors */
+#define CMT_CGH1_REG(base)                       ((base)->CGH1)
+#define CMT_CGL1_REG(base)                       ((base)->CGL1)
+#define CMT_CGH2_REG(base)                       ((base)->CGH2)
+#define CMT_CGL2_REG(base)                       ((base)->CGL2)
+#define CMT_OC_REG(base)                         ((base)->OC)
+#define CMT_MSC_REG(base)                        ((base)->MSC)
+#define CMT_CMD1_REG(base)                       ((base)->CMD1)
+#define CMT_CMD2_REG(base)                       ((base)->CMD2)
+#define CMT_CMD3_REG(base)                       ((base)->CMD3)
+#define CMT_CMD4_REG(base)                       ((base)->CMD4)
+#define CMT_PPS_REG(base)                        ((base)->PPS)
+#define CMT_DMA_REG(base)                        ((base)->DMA)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK                         0xFFu
+#define CMT_CGH1_PH_SHIFT                        0
+#define CMT_CGH1_PH_WIDTH                        8
+#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK                         0xFFu
+#define CMT_CGL1_PL_SHIFT                        0
+#define CMT_CGL1_PL_WIDTH                        8
+#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK                         0xFFu
+#define CMT_CGH2_SH_SHIFT                        0
+#define CMT_CGH2_SH_WIDTH                        8
+#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK                         0xFFu
+#define CMT_CGL2_SL_SHIFT                        0
+#define CMT_CGL2_SL_WIDTH                        8
+#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK                       0x20u
+#define CMT_OC_IROPEN_SHIFT                      5
+#define CMT_OC_IROPEN_WIDTH                      1
+#define CMT_OC_IROPEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROPEN_SHIFT))&CMT_OC_IROPEN_MASK)
+#define CMT_OC_CMTPOL_MASK                       0x40u
+#define CMT_OC_CMTPOL_SHIFT                      6
+#define CMT_OC_CMTPOL_WIDTH                      1
+#define CMT_OC_CMTPOL(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_OC_CMTPOL_SHIFT))&CMT_OC_CMTPOL_MASK)
+#define CMT_OC_IROL_MASK                         0x80u
+#define CMT_OC_IROL_SHIFT                        7
+#define CMT_OC_IROL_WIDTH                        1
+#define CMT_OC_IROL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROL_SHIFT))&CMT_OC_IROL_MASK)
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK                       0x1u
+#define CMT_MSC_MCGEN_SHIFT                      0
+#define CMT_MSC_MCGEN_WIDTH                      1
+#define CMT_MSC_MCGEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_MCGEN_SHIFT))&CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_EOCIE_MASK                       0x2u
+#define CMT_MSC_EOCIE_SHIFT                      1
+#define CMT_MSC_EOCIE_WIDTH                      1
+#define CMT_MSC_EOCIE(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCIE_SHIFT))&CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_FSK_MASK                         0x4u
+#define CMT_MSC_FSK_SHIFT                        2
+#define CMT_MSC_FSK_WIDTH                        1
+#define CMT_MSC_FSK(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_MSC_FSK_SHIFT))&CMT_MSC_FSK_MASK)
+#define CMT_MSC_BASE_MASK                        0x8u
+#define CMT_MSC_BASE_SHIFT                       3
+#define CMT_MSC_BASE_WIDTH                       1
+#define CMT_MSC_BASE(x)                          (((uint8_t)(((uint8_t)(x))<<CMT_MSC_BASE_SHIFT))&CMT_MSC_BASE_MASK)
+#define CMT_MSC_EXSPC_MASK                       0x10u
+#define CMT_MSC_EXSPC_SHIFT                      4
+#define CMT_MSC_EXSPC_WIDTH                      1
+#define CMT_MSC_EXSPC(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EXSPC_SHIFT))&CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_CMTDIV_MASK                      0x60u
+#define CMT_MSC_CMTDIV_SHIFT                     5
+#define CMT_MSC_CMTDIV_WIDTH                     2
+#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK                        0x80u
+#define CMT_MSC_EOCF_SHIFT                       7
+#define CMT_MSC_EOCF_WIDTH                       1
+#define CMT_MSC_EOCF(x)                          (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCF_SHIFT))&CMT_MSC_EOCF_MASK)
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK                         0xFFu
+#define CMT_CMD1_MB_SHIFT                        0
+#define CMT_CMD1_MB_WIDTH                        8
+#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK                         0xFFu
+#define CMT_CMD2_MB_SHIFT                        0
+#define CMT_CMD2_MB_WIDTH                        8
+#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK                         0xFFu
+#define CMT_CMD3_SB_SHIFT                        0
+#define CMT_CMD3_SB_WIDTH                        8
+#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK                         0xFFu
+#define CMT_CMD4_SB_SHIFT                        0
+#define CMT_CMD4_SB_WIDTH                        8
+#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK                      0xFu
+#define CMT_PPS_PPSDIV_SHIFT                     0
+#define CMT_PPS_PPSDIV_WIDTH                     4
+#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK                         0x1u
+#define CMT_DMA_DMA_SHIFT                        0
+#define CMT_DMA_DMA_WIDTH                        1
+#define CMT_DMA_DMA(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_DMA_DMA_SHIFT))&CMT_DMA_DMA_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE                                 (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT                                      ((CMT_Type *)CMT_BASE)
+#define CMT_BASE_PTR                             (CMT)
+/** Array initializer of CMT peripheral base addresses */
+#define CMT_BASE_ADDRS                           { CMT_BASE }
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASE_PTRS                            { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS                                 { CMT_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register instance definitions */
+/* CMT */
+#define CMT_CGH1                                 CMT_CGH1_REG(CMT)
+#define CMT_CGL1                                 CMT_CGL1_REG(CMT)
+#define CMT_CGH2                                 CMT_CGH2_REG(CMT)
+#define CMT_CGL2                                 CMT_CGL2_REG(CMT)
+#define CMT_OC                                   CMT_OC_REG(CMT)
+#define CMT_MSC                                  CMT_MSC_REG(CMT)
+#define CMT_CMD1                                 CMT_CMD1_REG(CMT)
+#define CMT_CMD2                                 CMT_CMD2_REG(CMT)
+#define CMT_CMD3                                 CMT_CMD3_REG(CMT)
+#define CMT_CMD4                                 CMT_CMD4_REG(CMT)
+#define CMT_PPS                                  CMT_PPS_REG(CMT)
+#define CMT_DMA                                  CMT_DMA_REG(CMT)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type, *CRC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register accessors */
+#define CRC_DATAL_REG(base)                      ((base)->ACCESS16BIT.DATAL)
+#define CRC_DATAH_REG(base)                      ((base)->ACCESS16BIT.DATAH)
+#define CRC_DATA_REG(base)                       ((base)->DATA)
+#define CRC_DATALL_REG(base)                     ((base)->ACCESS8BIT.DATALL)
+#define CRC_DATALU_REG(base)                     ((base)->ACCESS8BIT.DATALU)
+#define CRC_DATAHL_REG(base)                     ((base)->ACCESS8BIT.DATAHL)
+#define CRC_DATAHU_REG(base)                     ((base)->ACCESS8BIT.DATAHU)
+#define CRC_GPOLYL_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYL)
+#define CRC_GPOLYH_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYH)
+#define CRC_GPOLY_REG(base)                      ((base)->GPOLY)
+#define CRC_GPOLYLL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
+#define CRC_GPOLYLU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
+#define CRC_GPOLYHL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
+#define CRC_GPOLYHU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
+#define CRC_CTRL_REG(base)                       ((base)->CTRL)
+#define CRC_CTRLHU_REG(base)                     ((base)->CTRL_ACCESS8BIT.CTRLHU)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK                     0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT                    0
+#define CRC_DATAL_DATAL_WIDTH                    16
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK                     0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT                    0
+#define CRC_DATAH_DATAH_WIDTH                    16
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK                         0xFFu
+#define CRC_DATA_LL_SHIFT                        0
+#define CRC_DATA_LL_WIDTH                        8
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         0xFF00u
+#define CRC_DATA_LU_SHIFT                        8
+#define CRC_DATA_LU_WIDTH                        8
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         0xFF0000u
+#define CRC_DATA_HL_SHIFT                        16
+#define CRC_DATA_HL_WIDTH                        8
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         0xFF000000u
+#define CRC_DATA_HU_SHIFT                        24
+#define CRC_DATA_HU_WIDTH                        8
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK                   0xFFu
+#define CRC_DATALL_DATALL_SHIFT                  0
+#define CRC_DATALL_DATALL_WIDTH                  8
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK                   0xFFu
+#define CRC_DATALU_DATALU_SHIFT                  0
+#define CRC_DATALU_DATALU_WIDTH                  8
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK                   0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT                  0
+#define CRC_DATAHL_DATAHL_WIDTH                  8
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK                   0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT                  0
+#define CRC_DATAHU_DATAHU_WIDTH                  8
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT                  0
+#define CRC_GPOLYL_GPOLYL_WIDTH                  16
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT                  0
+#define CRC_GPOLYH_GPOLYH_WIDTH                  16
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK                       0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT                      0
+#define CRC_GPOLY_LOW_WIDTH                      16
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT                     16
+#define CRC_GPOLY_HIGH_WIDTH                     16
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                0
+#define CRC_GPOLYLL_GPOLYLL_WIDTH                8
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                0
+#define CRC_GPOLYLU_GPOLYLU_WIDTH                8
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                0
+#define CRC_GPOLYHL_GPOLYHL_WIDTH                8
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                0
+#define CRC_GPOLYHU_GPOLYHU_WIDTH                8
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK                       0x1000000u
+#define CRC_CTRL_TCRC_SHIFT                      24
+#define CRC_CTRL_TCRC_WIDTH                      1
+#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK                        0x2000000u
+#define CRC_CTRL_WAS_SHIFT                       25
+#define CRC_CTRL_WAS_WIDTH                       1
+#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK                       0x4000000u
+#define CRC_CTRL_FXOR_SHIFT                      26
+#define CRC_CTRL_FXOR_WIDTH                      1
+#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK                       0x30000000u
+#define CRC_CTRL_TOTR_SHIFT                      28
+#define CRC_CTRL_TOTR_WIDTH                      2
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        0xC0000000u
+#define CRC_CTRL_TOT_SHIFT                       30
+#define CRC_CTRL_TOT_WIDTH                       2
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK                     0x1u
+#define CRC_CTRLHU_TCRC_SHIFT                    0
+#define CRC_CTRLHU_TCRC_WIDTH                    1
+#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TCRC_SHIFT))&CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK                      0x2u
+#define CRC_CTRLHU_WAS_SHIFT                     1
+#define CRC_CTRLHU_WAS_WIDTH                     1
+#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_WAS_SHIFT))&CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK                     0x4u
+#define CRC_CTRLHU_FXOR_SHIFT                    2
+#define CRC_CTRLHU_FXOR_WIDTH                    1
+#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_FXOR_SHIFT))&CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK                     0x30u
+#define CRC_CTRLHU_TOTR_SHIFT                    4
+#define CRC_CTRLHU_TOTR_WIDTH                    2
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      0xC0u
+#define CRC_CTRLHU_TOT_SHIFT                     6
+#define CRC_CTRLHU_TOT_WIDTH                     2
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+#define CRC_BASE_PTR                             (CRC0)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register instance definitions */
+/* CRC */
+#define CRC_DATA                                 CRC_DATA_REG(CRC0)
+#define CRC_DATAL                                CRC_DATAL_REG(CRC0)
+#define CRC_DATALL                               CRC_DATALL_REG(CRC0)
+#define CRC_DATALU                               CRC_DATALU_REG(CRC0)
+#define CRC_DATAH                                CRC_DATAH_REG(CRC0)
+#define CRC_DATAHL                               CRC_DATAHL_REG(CRC0)
+#define CRC_DATAHU                               CRC_DATAHU_REG(CRC0)
+#define CRC_GPOLY                                CRC_GPOLY_REG(CRC0)
+#define CRC_GPOLYL                               CRC_GPOLYL_REG(CRC0)
+#define CRC_GPOLYLL                              CRC_GPOLYLL_REG(CRC0)
+#define CRC_GPOLYLU                              CRC_GPOLYLU_REG(CRC0)
+#define CRC_GPOLYH                               CRC_GPOLYH_REG(CRC0)
+#define CRC_GPOLYHL                              CRC_GPOLYHL_REG(CRC0)
+#define CRC_GPOLYHU                              CRC_GPOLYHU_REG(CRC0)
+#define CRC_CTRL                                 CRC_CTRL_REG(CRC0)
+#define CRC_CTRLHU                               CRC_CTRLHU_REG(CRC0)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[16];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index)                 ((base)->DAT[index].DATL)
+#define DAC_DATL_COUNT                           16
+#define DAC_DATH_REG(base,index)                 ((base)->DAT[index].DATH)
+#define DAC_DATH_COUNT                           16
+#define DAC_SR_REG(base)                         ((base)->SR)
+#define DAC_C0_REG(base)                         ((base)->C0)
+#define DAC_C1_REG(base)                         ((base)->C1)
+#define DAC_C2_REG(base)                         ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK                      0xFFu
+#define DAC_DATL_DATA0_SHIFT                     0
+#define DAC_DATL_DATA0_WIDTH                     8
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK                      0xFu
+#define DAC_DATH_DATA1_SHIFT                     0
+#define DAC_DATH_DATA1_WIDTH                     4
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK                    0x1u
+#define DAC_SR_DACBFRPBF_SHIFT                   0
+#define DAC_SR_DACBFRPBF_WIDTH                   1
+#define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK                    0x2u
+#define DAC_SR_DACBFRPTF_SHIFT                   1
+#define DAC_SR_DACBFRPTF_WIDTH                   1
+#define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK                     0x4u
+#define DAC_SR_DACBFWMF_SHIFT                    2
+#define DAC_SR_DACBFWMF_WIDTH                    1
+#define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFWMF_SHIFT))&DAC_SR_DACBFWMF_MASK)
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK                     0x1u
+#define DAC_C0_DACBBIEN_SHIFT                    0
+#define DAC_C0_DACBBIEN_WIDTH                    1
+#define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK                     0x2u
+#define DAC_C0_DACBTIEN_SHIFT                    1
+#define DAC_C0_DACBTIEN_WIDTH                    1
+#define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK                     0x4u
+#define DAC_C0_DACBWIEN_SHIFT                    2
+#define DAC_C0_DACBWIEN_WIDTH                    1
+#define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBWIEN_SHIFT))&DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK                         0x8u
+#define DAC_C0_LPEN_SHIFT                        3
+#define DAC_C0_LPEN_WIDTH                        1
+#define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK                     0x10u
+#define DAC_C0_DACSWTRG_SHIFT                    4
+#define DAC_C0_DACSWTRG_WIDTH                    1
+#define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK                    0x20u
+#define DAC_C0_DACTRGSEL_SHIFT                   5
+#define DAC_C0_DACTRGSEL_WIDTH                   1
+#define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK                       0x40u
+#define DAC_C0_DACRFS_SHIFT                      6
+#define DAC_C0_DACRFS_WIDTH                      1
+#define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK                        0x80u
+#define DAC_C0_DACEN_SHIFT                       7
+#define DAC_C0_DACEN_WIDTH                       1
+#define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK                      0x1u
+#define DAC_C1_DACBFEN_SHIFT                     0
+#define DAC_C1_DACBFEN_WIDTH                     1
+#define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK                      0x6u
+#define DAC_C1_DACBFMD_SHIFT                     1
+#define DAC_C1_DACBFMD_WIDTH                     2
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK                      0x18u
+#define DAC_C1_DACBFWM_SHIFT                     3
+#define DAC_C1_DACBFWM_WIDTH                     2
+#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK                        0x80u
+#define DAC_C1_DMAEN_SHIFT                       7
+#define DAC_C1_DMAEN_WIDTH                       1
+#define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK                      0xFu
+#define DAC_C2_DACBFUP_SHIFT                     0
+#define DAC_C2_DACBFUP_WIDTH                     4
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      0xF0u
+#define DAC_C2_DACBFRP_SHIFT                     4
+#define DAC_C2_DACBFRP_WIDTH                     4
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR                            (DAC0)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE                                (0x400CD000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1                                     ((DAC_Type *)DAC1_BASE)
+#define DAC1_BASE_PTR                            (DAC1)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS                           { DAC0_BASE, DAC1_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS                            { DAC0, DAC1 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn, DAC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L                               DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H                               DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L                               DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H                               DAC_DATH_REG(DAC0,1)
+#define DAC0_DAT2L                               DAC_DATL_REG(DAC0,2)
+#define DAC0_DAT2H                               DAC_DATH_REG(DAC0,2)
+#define DAC0_DAT3L                               DAC_DATL_REG(DAC0,3)
+#define DAC0_DAT3H                               DAC_DATH_REG(DAC0,3)
+#define DAC0_DAT4L                               DAC_DATL_REG(DAC0,4)
+#define DAC0_DAT4H                               DAC_DATH_REG(DAC0,4)
+#define DAC0_DAT5L                               DAC_DATL_REG(DAC0,5)
+#define DAC0_DAT5H                               DAC_DATH_REG(DAC0,5)
+#define DAC0_DAT6L                               DAC_DATL_REG(DAC0,6)
+#define DAC0_DAT6H                               DAC_DATH_REG(DAC0,6)
+#define DAC0_DAT7L                               DAC_DATL_REG(DAC0,7)
+#define DAC0_DAT7H                               DAC_DATH_REG(DAC0,7)
+#define DAC0_DAT8L                               DAC_DATL_REG(DAC0,8)
+#define DAC0_DAT8H                               DAC_DATH_REG(DAC0,8)
+#define DAC0_DAT9L                               DAC_DATL_REG(DAC0,9)
+#define DAC0_DAT9H                               DAC_DATH_REG(DAC0,9)
+#define DAC0_DAT10L                              DAC_DATL_REG(DAC0,10)
+#define DAC0_DAT10H                              DAC_DATH_REG(DAC0,10)
+#define DAC0_DAT11L                              DAC_DATL_REG(DAC0,11)
+#define DAC0_DAT11H                              DAC_DATH_REG(DAC0,11)
+#define DAC0_DAT12L                              DAC_DATL_REG(DAC0,12)
+#define DAC0_DAT12H                              DAC_DATH_REG(DAC0,12)
+#define DAC0_DAT13L                              DAC_DATL_REG(DAC0,13)
+#define DAC0_DAT13H                              DAC_DATH_REG(DAC0,13)
+#define DAC0_DAT14L                              DAC_DATL_REG(DAC0,14)
+#define DAC0_DAT14H                              DAC_DATH_REG(DAC0,14)
+#define DAC0_DAT15L                              DAC_DATL_REG(DAC0,15)
+#define DAC0_DAT15H                              DAC_DATH_REG(DAC0,15)
+#define DAC0_SR                                  DAC_SR_REG(DAC0)
+#define DAC0_C0                                  DAC_C0_REG(DAC0)
+#define DAC0_C1                                  DAC_C1_REG(DAC0)
+#define DAC0_C2                                  DAC_C2_REG(DAC0)
+/* DAC1 */
+#define DAC1_DAT0L                               DAC_DATL_REG(DAC1,0)
+#define DAC1_DAT0H                               DAC_DATH_REG(DAC1,0)
+#define DAC1_DAT1L                               DAC_DATL_REG(DAC1,1)
+#define DAC1_DAT1H                               DAC_DATH_REG(DAC1,1)
+#define DAC1_DAT2L                               DAC_DATL_REG(DAC1,2)
+#define DAC1_DAT2H                               DAC_DATH_REG(DAC1,2)
+#define DAC1_DAT3L                               DAC_DATL_REG(DAC1,3)
+#define DAC1_DAT3H                               DAC_DATH_REG(DAC1,3)
+#define DAC1_DAT4L                               DAC_DATL_REG(DAC1,4)
+#define DAC1_DAT4H                               DAC_DATH_REG(DAC1,4)
+#define DAC1_DAT5L                               DAC_DATL_REG(DAC1,5)
+#define DAC1_DAT5H                               DAC_DATH_REG(DAC1,5)
+#define DAC1_DAT6L                               DAC_DATL_REG(DAC1,6)
+#define DAC1_DAT6H                               DAC_DATH_REG(DAC1,6)
+#define DAC1_DAT7L                               DAC_DATL_REG(DAC1,7)
+#define DAC1_DAT7H                               DAC_DATH_REG(DAC1,7)
+#define DAC1_DAT8L                               DAC_DATL_REG(DAC1,8)
+#define DAC1_DAT8H                               DAC_DATH_REG(DAC1,8)
+#define DAC1_DAT9L                               DAC_DATL_REG(DAC1,9)
+#define DAC1_DAT9H                               DAC_DATH_REG(DAC1,9)
+#define DAC1_DAT10L                              DAC_DATL_REG(DAC1,10)
+#define DAC1_DAT10H                              DAC_DATH_REG(DAC1,10)
+#define DAC1_DAT11L                              DAC_DATL_REG(DAC1,11)
+#define DAC1_DAT11H                              DAC_DATH_REG(DAC1,11)
+#define DAC1_DAT12L                              DAC_DATL_REG(DAC1,12)
+#define DAC1_DAT12H                              DAC_DATH_REG(DAC1,12)
+#define DAC1_DAT13L                              DAC_DATL_REG(DAC1,13)
+#define DAC1_DAT13H                              DAC_DATH_REG(DAC1,13)
+#define DAC1_DAT14L                              DAC_DATL_REG(DAC1,14)
+#define DAC1_DAT14H                              DAC_DATH_REG(DAC1,14)
+#define DAC1_DAT15L                              DAC_DATL_REG(DAC1,15)
+#define DAC1_DAT15H                              DAC_DATH_REG(DAC1,15)
+#define DAC1_SR                                  DAC_SR_REG(DAC1)
+#define DAC1_C0                                  DAC_C0_REG(DAC1)
+#define DAC1_C1                                  DAC_C1_REG(DAC1)
+#define DAC1_C2                                  DAC_C2_REG(DAC1)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index)                         DAC_DATL_REG(DAC0,index)
+#define DAC1_DATL(index)                         DAC_DATL_REG(DAC1,index)
+#define DAC0_DATH(index)                         DAC_DATH_REG(DAC0,index)
+#define DAC1_DATH(index)                         DAC_DATH_REG(DAC1,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[200];
+  __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /**< Channel n Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /**< Channel n Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /**< Channel n Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /**< Channel n Priority Register, offset: 0x107 */
+  __IO uint8_t DCHPRI11;                           /**< Channel n Priority Register, offset: 0x108 */
+  __IO uint8_t DCHPRI10;                           /**< Channel n Priority Register, offset: 0x109 */
+  __IO uint8_t DCHPRI9;                            /**< Channel n Priority Register, offset: 0x10A */
+  __IO uint8_t DCHPRI8;                            /**< Channel n Priority Register, offset: 0x10B */
+  __IO uint8_t DCHPRI15;                           /**< Channel n Priority Register, offset: 0x10C */
+  __IO uint8_t DCHPRI14;                           /**< Channel n Priority Register, offset: 0x10D */
+  __IO uint8_t DCHPRI13;                           /**< Channel n Priority Register, offset: 0x10E */
+  __IO uint8_t DCHPRI12;                           /**< Channel n Priority Register, offset: 0x10F */
+       uint8_t RESERVED_6[3824];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[16];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_CR_REG(base)                         ((base)->CR)
+#define DMA_ES_REG(base)                         ((base)->ES)
+#define DMA_ERQ_REG(base)                        ((base)->ERQ)
+#define DMA_EEI_REG(base)                        ((base)->EEI)
+#define DMA_CEEI_REG(base)                       ((base)->CEEI)
+#define DMA_SEEI_REG(base)                       ((base)->SEEI)
+#define DMA_CERQ_REG(base)                       ((base)->CERQ)
+#define DMA_SERQ_REG(base)                       ((base)->SERQ)
+#define DMA_CDNE_REG(base)                       ((base)->CDNE)
+#define DMA_SSRT_REG(base)                       ((base)->SSRT)
+#define DMA_CERR_REG(base)                       ((base)->CERR)
+#define DMA_CINT_REG(base)                       ((base)->CINT)
+#define DMA_INT_REG(base)                        ((base)->INT)
+#define DMA_ERR_REG(base)                        ((base)->ERR)
+#define DMA_HRS_REG(base)                        ((base)->HRS)
+#define DMA_DCHPRI3_REG(base)                    ((base)->DCHPRI3)
+#define DMA_DCHPRI2_REG(base)                    ((base)->DCHPRI2)
+#define DMA_DCHPRI1_REG(base)                    ((base)->DCHPRI1)
+#define DMA_DCHPRI0_REG(base)                    ((base)->DCHPRI0)
+#define DMA_DCHPRI7_REG(base)                    ((base)->DCHPRI7)
+#define DMA_DCHPRI6_REG(base)                    ((base)->DCHPRI6)
+#define DMA_DCHPRI5_REG(base)                    ((base)->DCHPRI5)
+#define DMA_DCHPRI4_REG(base)                    ((base)->DCHPRI4)
+#define DMA_DCHPRI11_REG(base)                   ((base)->DCHPRI11)
+#define DMA_DCHPRI10_REG(base)                   ((base)->DCHPRI10)
+#define DMA_DCHPRI9_REG(base)                    ((base)->DCHPRI9)
+#define DMA_DCHPRI8_REG(base)                    ((base)->DCHPRI8)
+#define DMA_DCHPRI15_REG(base)                   ((base)->DCHPRI15)
+#define DMA_DCHPRI14_REG(base)                   ((base)->DCHPRI14)
+#define DMA_DCHPRI13_REG(base)                   ((base)->DCHPRI13)
+#define DMA_DCHPRI12_REG(base)                   ((base)->DCHPRI12)
+#define DMA_SADDR_REG(base,index)                ((base)->TCD[index].SADDR)
+#define DMA_SADDR_COUNT                          16
+#define DMA_SOFF_REG(base,index)                 ((base)->TCD[index].SOFF)
+#define DMA_SOFF_COUNT                           16
+#define DMA_ATTR_REG(base,index)                 ((base)->TCD[index].ATTR)
+#define DMA_ATTR_COUNT                           16
+#define DMA_NBYTES_MLNO_REG(base,index)          ((base)->TCD[index].NBYTES_MLNO)
+#define DMA_NBYTES_MLNO_COUNT                    16
+#define DMA_NBYTES_MLOFFNO_REG(base,index)       ((base)->TCD[index].NBYTES_MLOFFNO)
+#define DMA_NBYTES_MLOFFNO_COUNT                 16
+#define DMA_NBYTES_MLOFFYES_REG(base,index)      ((base)->TCD[index].NBYTES_MLOFFYES)
+#define DMA_NBYTES_MLOFFYES_COUNT                16
+#define DMA_SLAST_REG(base,index)                ((base)->TCD[index].SLAST)
+#define DMA_SLAST_COUNT                          16
+#define DMA_DADDR_REG(base,index)                ((base)->TCD[index].DADDR)
+#define DMA_DADDR_COUNT                          16
+#define DMA_DOFF_REG(base,index)                 ((base)->TCD[index].DOFF)
+#define DMA_DOFF_COUNT                           16
+#define DMA_CITER_ELINKNO_REG(base,index)        ((base)->TCD[index].CITER_ELINKNO)
+#define DMA_CITER_ELINKNO_COUNT                  16
+#define DMA_CITER_ELINKYES_REG(base,index)       ((base)->TCD[index].CITER_ELINKYES)
+#define DMA_CITER_ELINKYES_COUNT                 16
+#define DMA_DLAST_SGA_REG(base,index)            ((base)->TCD[index].DLAST_SGA)
+#define DMA_DLAST_SGA_COUNT                      16
+#define DMA_CSR_REG(base,index)                  ((base)->TCD[index].CSR)
+#define DMA_CSR_COUNT                            16
+#define DMA_BITER_ELINKNO_REG(base,index)        ((base)->TCD[index].BITER_ELINKNO)
+#define DMA_BITER_ELINKNO_COUNT                  16
+#define DMA_BITER_ELINKYES_REG(base,index)       ((base)->TCD[index].BITER_ELINKYES)
+#define DMA_BITER_ELINKYES_COUNT                 16
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK                         0x2u
+#define DMA_CR_EDBG_SHIFT                        1
+#define DMA_CR_EDBG_WIDTH                        1
+#define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK                         0x4u
+#define DMA_CR_ERCA_SHIFT                        2
+#define DMA_CR_ERCA_WIDTH                        1
+#define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK                          0x10u
+#define DMA_CR_HOE_SHIFT                         4
+#define DMA_CR_HOE_WIDTH                         1
+#define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK                         0x20u
+#define DMA_CR_HALT_SHIFT                        5
+#define DMA_CR_HALT_WIDTH                        1
+#define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK                          0x40u
+#define DMA_CR_CLM_SHIFT                         6
+#define DMA_CR_CLM_WIDTH                         1
+#define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK                         0x80u
+#define DMA_CR_EMLM_SHIFT                        7
+#define DMA_CR_EMLM_WIDTH                        1
+#define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK                          0x10000u
+#define DMA_CR_ECX_SHIFT                         16
+#define DMA_CR_ECX_WIDTH                         1
+#define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK                           0x20000u
+#define DMA_CR_CX_SHIFT                          17
+#define DMA_CR_CX_WIDTH                          1
+#define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK                          0x1u
+#define DMA_ES_DBE_SHIFT                         0
+#define DMA_ES_DBE_WIDTH                         1
+#define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK                          0x2u
+#define DMA_ES_SBE_SHIFT                         1
+#define DMA_ES_SBE_WIDTH                         1
+#define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK                          0x4u
+#define DMA_ES_SGE_SHIFT                         2
+#define DMA_ES_SGE_WIDTH                         1
+#define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK                          0x8u
+#define DMA_ES_NCE_SHIFT                         3
+#define DMA_ES_NCE_WIDTH                         1
+#define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK                          0x10u
+#define DMA_ES_DOE_SHIFT                         4
+#define DMA_ES_DOE_WIDTH                         1
+#define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK                          0x20u
+#define DMA_ES_DAE_SHIFT                         5
+#define DMA_ES_DAE_WIDTH                         1
+#define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK                          0x40u
+#define DMA_ES_SOE_SHIFT                         6
+#define DMA_ES_SOE_WIDTH                         1
+#define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK                          0x80u
+#define DMA_ES_SAE_SHIFT                         7
+#define DMA_ES_SAE_WIDTH                         1
+#define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK                       0xF00u
+#define DMA_ES_ERRCHN_SHIFT                      8
+#define DMA_ES_ERRCHN_WIDTH                      4
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          0x4000u
+#define DMA_ES_CPE_SHIFT                         14
+#define DMA_ES_CPE_WIDTH                         1
+#define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK                          0x10000u
+#define DMA_ES_ECX_SHIFT                         16
+#define DMA_ES_ECX_WIDTH                         1
+#define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK                          0x80000000u
+#define DMA_ES_VLD_SHIFT                         31
+#define DMA_ES_VLD_WIDTH                         1
+#define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK                        0x1u
+#define DMA_ERQ_ERQ0_SHIFT                       0
+#define DMA_ERQ_ERQ0_WIDTH                       1
+#define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK                        0x2u
+#define DMA_ERQ_ERQ1_SHIFT                       1
+#define DMA_ERQ_ERQ1_WIDTH                       1
+#define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK                        0x4u
+#define DMA_ERQ_ERQ2_SHIFT                       2
+#define DMA_ERQ_ERQ2_WIDTH                       1
+#define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK                        0x8u
+#define DMA_ERQ_ERQ3_SHIFT                       3
+#define DMA_ERQ_ERQ3_WIDTH                       1
+#define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK                        0x10u
+#define DMA_ERQ_ERQ4_SHIFT                       4
+#define DMA_ERQ_ERQ4_WIDTH                       1
+#define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK                        0x20u
+#define DMA_ERQ_ERQ5_SHIFT                       5
+#define DMA_ERQ_ERQ5_WIDTH                       1
+#define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK                        0x40u
+#define DMA_ERQ_ERQ6_SHIFT                       6
+#define DMA_ERQ_ERQ6_WIDTH                       1
+#define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK                        0x80u
+#define DMA_ERQ_ERQ7_SHIFT                       7
+#define DMA_ERQ_ERQ7_WIDTH                       1
+#define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK                        0x100u
+#define DMA_ERQ_ERQ8_SHIFT                       8
+#define DMA_ERQ_ERQ8_WIDTH                       1
+#define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK                        0x200u
+#define DMA_ERQ_ERQ9_SHIFT                       9
+#define DMA_ERQ_ERQ9_WIDTH                       1
+#define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK                       0x400u
+#define DMA_ERQ_ERQ10_SHIFT                      10
+#define DMA_ERQ_ERQ10_WIDTH                      1
+#define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK                       0x800u
+#define DMA_ERQ_ERQ11_SHIFT                      11
+#define DMA_ERQ_ERQ11_WIDTH                      1
+#define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK                       0x1000u
+#define DMA_ERQ_ERQ12_SHIFT                      12
+#define DMA_ERQ_ERQ12_WIDTH                      1
+#define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK                       0x2000u
+#define DMA_ERQ_ERQ13_SHIFT                      13
+#define DMA_ERQ_ERQ13_WIDTH                      1
+#define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK                       0x4000u
+#define DMA_ERQ_ERQ14_SHIFT                      14
+#define DMA_ERQ_ERQ14_WIDTH                      1
+#define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK                       0x8000u
+#define DMA_ERQ_ERQ15_SHIFT                      15
+#define DMA_ERQ_ERQ15_WIDTH                      1
+#define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK                        0x1u
+#define DMA_EEI_EEI0_SHIFT                       0
+#define DMA_EEI_EEI0_WIDTH                       1
+#define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK                        0x2u
+#define DMA_EEI_EEI1_SHIFT                       1
+#define DMA_EEI_EEI1_WIDTH                       1
+#define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK                        0x4u
+#define DMA_EEI_EEI2_SHIFT                       2
+#define DMA_EEI_EEI2_WIDTH                       1
+#define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK                        0x8u
+#define DMA_EEI_EEI3_SHIFT                       3
+#define DMA_EEI_EEI3_WIDTH                       1
+#define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK                        0x10u
+#define DMA_EEI_EEI4_SHIFT                       4
+#define DMA_EEI_EEI4_WIDTH                       1
+#define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK                        0x20u
+#define DMA_EEI_EEI5_SHIFT                       5
+#define DMA_EEI_EEI5_WIDTH                       1
+#define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK                        0x40u
+#define DMA_EEI_EEI6_SHIFT                       6
+#define DMA_EEI_EEI6_WIDTH                       1
+#define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK                        0x80u
+#define DMA_EEI_EEI7_SHIFT                       7
+#define DMA_EEI_EEI7_WIDTH                       1
+#define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK                        0x100u
+#define DMA_EEI_EEI8_SHIFT                       8
+#define DMA_EEI_EEI8_WIDTH                       1
+#define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK                        0x200u
+#define DMA_EEI_EEI9_SHIFT                       9
+#define DMA_EEI_EEI9_WIDTH                       1
+#define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK                       0x400u
+#define DMA_EEI_EEI10_SHIFT                      10
+#define DMA_EEI_EEI10_WIDTH                      1
+#define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK                       0x800u
+#define DMA_EEI_EEI11_SHIFT                      11
+#define DMA_EEI_EEI11_WIDTH                      1
+#define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK                       0x1000u
+#define DMA_EEI_EEI12_SHIFT                      12
+#define DMA_EEI_EEI12_WIDTH                      1
+#define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK                       0x2000u
+#define DMA_EEI_EEI13_SHIFT                      13
+#define DMA_EEI_EEI13_WIDTH                      1
+#define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK                       0x4000u
+#define DMA_EEI_EEI14_SHIFT                      14
+#define DMA_EEI_EEI14_WIDTH                      1
+#define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK                       0x8000u
+#define DMA_EEI_EEI15_SHIFT                      15
+#define DMA_EEI_EEI15_WIDTH                      1
+#define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK                       0xFu
+#define DMA_CEEI_CEEI_SHIFT                      0
+#define DMA_CEEI_CEEI_WIDTH                      4
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       0x40u
+#define DMA_CEEI_CAEE_SHIFT                      6
+#define DMA_CEEI_CAEE_WIDTH                      1
+#define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK                        0x80u
+#define DMA_CEEI_NOP_SHIFT                       7
+#define DMA_CEEI_NOP_WIDTH                       1
+#define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK                       0xFu
+#define DMA_SEEI_SEEI_SHIFT                      0
+#define DMA_SEEI_SEEI_WIDTH                      4
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       0x40u
+#define DMA_SEEI_SAEE_SHIFT                      6
+#define DMA_SEEI_SAEE_WIDTH                      1
+#define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK                        0x80u
+#define DMA_SEEI_NOP_SHIFT                       7
+#define DMA_SEEI_NOP_WIDTH                       1
+#define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK                       0xFu
+#define DMA_CERQ_CERQ_SHIFT                      0
+#define DMA_CERQ_CERQ_WIDTH                      4
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       0x40u
+#define DMA_CERQ_CAER_SHIFT                      6
+#define DMA_CERQ_CAER_WIDTH                      1
+#define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK                        0x80u
+#define DMA_CERQ_NOP_SHIFT                       7
+#define DMA_CERQ_NOP_WIDTH                       1
+#define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK                       0xFu
+#define DMA_SERQ_SERQ_SHIFT                      0
+#define DMA_SERQ_SERQ_WIDTH                      4
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       0x40u
+#define DMA_SERQ_SAER_SHIFT                      6
+#define DMA_SERQ_SAER_WIDTH                      1
+#define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK                        0x80u
+#define DMA_SERQ_NOP_SHIFT                       7
+#define DMA_SERQ_NOP_WIDTH                       1
+#define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK                       0xFu
+#define DMA_CDNE_CDNE_SHIFT                      0
+#define DMA_CDNE_CDNE_WIDTH                      4
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       0x40u
+#define DMA_CDNE_CADN_SHIFT                      6
+#define DMA_CDNE_CADN_WIDTH                      1
+#define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK                        0x80u
+#define DMA_CDNE_NOP_SHIFT                       7
+#define DMA_CDNE_NOP_WIDTH                       1
+#define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK                       0xFu
+#define DMA_SSRT_SSRT_SHIFT                      0
+#define DMA_SSRT_SSRT_WIDTH                      4
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       0x40u
+#define DMA_SSRT_SAST_SHIFT                      6
+#define DMA_SSRT_SAST_WIDTH                      1
+#define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK                        0x80u
+#define DMA_SSRT_NOP_SHIFT                       7
+#define DMA_SSRT_NOP_WIDTH                       1
+#define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK                       0xFu
+#define DMA_CERR_CERR_SHIFT                      0
+#define DMA_CERR_CERR_WIDTH                      4
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       0x40u
+#define DMA_CERR_CAEI_SHIFT                      6
+#define DMA_CERR_CAEI_WIDTH                      1
+#define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK                        0x80u
+#define DMA_CERR_NOP_SHIFT                       7
+#define DMA_CERR_NOP_WIDTH                       1
+#define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK                       0xFu
+#define DMA_CINT_CINT_SHIFT                      0
+#define DMA_CINT_CINT_WIDTH                      4
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       0x40u
+#define DMA_CINT_CAIR_SHIFT                      6
+#define DMA_CINT_CAIR_WIDTH                      1
+#define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK                        0x80u
+#define DMA_CINT_NOP_SHIFT                       7
+#define DMA_CINT_NOP_WIDTH                       1
+#define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK                        0x1u
+#define DMA_INT_INT0_SHIFT                       0
+#define DMA_INT_INT0_WIDTH                       1
+#define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK                        0x2u
+#define DMA_INT_INT1_SHIFT                       1
+#define DMA_INT_INT1_WIDTH                       1
+#define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK                        0x4u
+#define DMA_INT_INT2_SHIFT                       2
+#define DMA_INT_INT2_WIDTH                       1
+#define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK                        0x8u
+#define DMA_INT_INT3_SHIFT                       3
+#define DMA_INT_INT3_WIDTH                       1
+#define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK                        0x10u
+#define DMA_INT_INT4_SHIFT                       4
+#define DMA_INT_INT4_WIDTH                       1
+#define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK                        0x20u
+#define DMA_INT_INT5_SHIFT                       5
+#define DMA_INT_INT5_WIDTH                       1
+#define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK                        0x40u
+#define DMA_INT_INT6_SHIFT                       6
+#define DMA_INT_INT6_WIDTH                       1
+#define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK                        0x80u
+#define DMA_INT_INT7_SHIFT                       7
+#define DMA_INT_INT7_WIDTH                       1
+#define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK                        0x100u
+#define DMA_INT_INT8_SHIFT                       8
+#define DMA_INT_INT8_WIDTH                       1
+#define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK                        0x200u
+#define DMA_INT_INT9_SHIFT                       9
+#define DMA_INT_INT9_WIDTH                       1
+#define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK                       0x400u
+#define DMA_INT_INT10_SHIFT                      10
+#define DMA_INT_INT10_WIDTH                      1
+#define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK                       0x800u
+#define DMA_INT_INT11_SHIFT                      11
+#define DMA_INT_INT11_WIDTH                      1
+#define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK                       0x1000u
+#define DMA_INT_INT12_SHIFT                      12
+#define DMA_INT_INT12_WIDTH                      1
+#define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK                       0x2000u
+#define DMA_INT_INT13_SHIFT                      13
+#define DMA_INT_INT13_WIDTH                      1
+#define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK                       0x4000u
+#define DMA_INT_INT14_SHIFT                      14
+#define DMA_INT_INT14_WIDTH                      1
+#define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK                       0x8000u
+#define DMA_INT_INT15_SHIFT                      15
+#define DMA_INT_INT15_WIDTH                      1
+#define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK                        0x1u
+#define DMA_ERR_ERR0_SHIFT                       0
+#define DMA_ERR_ERR0_WIDTH                       1
+#define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK                        0x2u
+#define DMA_ERR_ERR1_SHIFT                       1
+#define DMA_ERR_ERR1_WIDTH                       1
+#define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK                        0x4u
+#define DMA_ERR_ERR2_SHIFT                       2
+#define DMA_ERR_ERR2_WIDTH                       1
+#define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK                        0x8u
+#define DMA_ERR_ERR3_SHIFT                       3
+#define DMA_ERR_ERR3_WIDTH                       1
+#define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK                        0x10u
+#define DMA_ERR_ERR4_SHIFT                       4
+#define DMA_ERR_ERR4_WIDTH                       1
+#define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK                        0x20u
+#define DMA_ERR_ERR5_SHIFT                       5
+#define DMA_ERR_ERR5_WIDTH                       1
+#define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK                        0x40u
+#define DMA_ERR_ERR6_SHIFT                       6
+#define DMA_ERR_ERR6_WIDTH                       1
+#define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK                        0x80u
+#define DMA_ERR_ERR7_SHIFT                       7
+#define DMA_ERR_ERR7_WIDTH                       1
+#define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK                        0x100u
+#define DMA_ERR_ERR8_SHIFT                       8
+#define DMA_ERR_ERR8_WIDTH                       1
+#define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK                        0x200u
+#define DMA_ERR_ERR9_SHIFT                       9
+#define DMA_ERR_ERR9_WIDTH                       1
+#define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK                       0x400u
+#define DMA_ERR_ERR10_SHIFT                      10
+#define DMA_ERR_ERR10_WIDTH                      1
+#define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK                       0x800u
+#define DMA_ERR_ERR11_SHIFT                      11
+#define DMA_ERR_ERR11_WIDTH                      1
+#define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK                       0x1000u
+#define DMA_ERR_ERR12_SHIFT                      12
+#define DMA_ERR_ERR12_WIDTH                      1
+#define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK                       0x2000u
+#define DMA_ERR_ERR13_SHIFT                      13
+#define DMA_ERR_ERR13_WIDTH                      1
+#define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK                       0x4000u
+#define DMA_ERR_ERR14_SHIFT                      14
+#define DMA_ERR_ERR14_WIDTH                      1
+#define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK                       0x8000u
+#define DMA_ERR_ERR15_SHIFT                      15
+#define DMA_ERR_ERR15_WIDTH                      1
+#define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK                        0x1u
+#define DMA_HRS_HRS0_SHIFT                       0
+#define DMA_HRS_HRS0_WIDTH                       1
+#define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK                        0x2u
+#define DMA_HRS_HRS1_SHIFT                       1
+#define DMA_HRS_HRS1_WIDTH                       1
+#define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK                        0x4u
+#define DMA_HRS_HRS2_SHIFT                       2
+#define DMA_HRS_HRS2_WIDTH                       1
+#define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK                        0x8u
+#define DMA_HRS_HRS3_SHIFT                       3
+#define DMA_HRS_HRS3_WIDTH                       1
+#define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK                        0x10u
+#define DMA_HRS_HRS4_SHIFT                       4
+#define DMA_HRS_HRS4_WIDTH                       1
+#define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK                        0x20u
+#define DMA_HRS_HRS5_SHIFT                       5
+#define DMA_HRS_HRS5_WIDTH                       1
+#define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK                        0x40u
+#define DMA_HRS_HRS6_SHIFT                       6
+#define DMA_HRS_HRS6_WIDTH                       1
+#define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK                        0x80u
+#define DMA_HRS_HRS7_SHIFT                       7
+#define DMA_HRS_HRS7_WIDTH                       1
+#define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK                        0x100u
+#define DMA_HRS_HRS8_SHIFT                       8
+#define DMA_HRS_HRS8_WIDTH                       1
+#define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK                        0x200u
+#define DMA_HRS_HRS9_SHIFT                       9
+#define DMA_HRS_HRS9_WIDTH                       1
+#define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK                       0x400u
+#define DMA_HRS_HRS10_SHIFT                      10
+#define DMA_HRS_HRS10_WIDTH                      1
+#define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK                       0x800u
+#define DMA_HRS_HRS11_SHIFT                      11
+#define DMA_HRS_HRS11_WIDTH                      1
+#define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK                       0x1000u
+#define DMA_HRS_HRS12_SHIFT                      12
+#define DMA_HRS_HRS12_WIDTH                      1
+#define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK                       0x2000u
+#define DMA_HRS_HRS13_SHIFT                      13
+#define DMA_HRS_HRS13_WIDTH                      1
+#define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK                       0x4000u
+#define DMA_HRS_HRS14_SHIFT                      14
+#define DMA_HRS_HRS14_WIDTH                      1
+#define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK                       0x8000u
+#define DMA_HRS_HRS15_SHIFT                      15
+#define DMA_HRS_HRS15_WIDTH                      1
+#define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT                  0
+#define DMA_DCHPRI3_CHPRI_WIDTH                  4
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     0x40u
+#define DMA_DCHPRI3_DPA_SHIFT                    6
+#define DMA_DCHPRI3_DPA_WIDTH                    1
+#define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_DPA_SHIFT))&DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK                     0x80u
+#define DMA_DCHPRI3_ECP_SHIFT                    7
+#define DMA_DCHPRI3_ECP_WIDTH                    1
+#define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_ECP_SHIFT))&DMA_DCHPRI3_ECP_MASK)
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT                  0
+#define DMA_DCHPRI2_CHPRI_WIDTH                  4
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     0x40u
+#define DMA_DCHPRI2_DPA_SHIFT                    6
+#define DMA_DCHPRI2_DPA_WIDTH                    1
+#define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_DPA_SHIFT))&DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK                     0x80u
+#define DMA_DCHPRI2_ECP_SHIFT                    7
+#define DMA_DCHPRI2_ECP_WIDTH                    1
+#define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_ECP_SHIFT))&DMA_DCHPRI2_ECP_MASK)
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT                  0
+#define DMA_DCHPRI1_CHPRI_WIDTH                  4
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     0x40u
+#define DMA_DCHPRI1_DPA_SHIFT                    6
+#define DMA_DCHPRI1_DPA_WIDTH                    1
+#define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_DPA_SHIFT))&DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK                     0x80u
+#define DMA_DCHPRI1_ECP_SHIFT                    7
+#define DMA_DCHPRI1_ECP_WIDTH                    1
+#define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_ECP_SHIFT))&DMA_DCHPRI1_ECP_MASK)
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT                  0
+#define DMA_DCHPRI0_CHPRI_WIDTH                  4
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     0x40u
+#define DMA_DCHPRI0_DPA_SHIFT                    6
+#define DMA_DCHPRI0_DPA_WIDTH                    1
+#define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_DPA_SHIFT))&DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK                     0x80u
+#define DMA_DCHPRI0_ECP_SHIFT                    7
+#define DMA_DCHPRI0_ECP_WIDTH                    1
+#define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_ECP_SHIFT))&DMA_DCHPRI0_ECP_MASK)
+/* DCHPRI7 Bit Fields */
+#define DMA_DCHPRI7_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI7_CHPRI_SHIFT                  0
+#define DMA_DCHPRI7_CHPRI_WIDTH                  4
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     0x40u
+#define DMA_DCHPRI7_DPA_SHIFT                    6
+#define DMA_DCHPRI7_DPA_WIDTH                    1
+#define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_DPA_SHIFT))&DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK                     0x80u
+#define DMA_DCHPRI7_ECP_SHIFT                    7
+#define DMA_DCHPRI7_ECP_WIDTH                    1
+#define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_ECP_SHIFT))&DMA_DCHPRI7_ECP_MASK)
+/* DCHPRI6 Bit Fields */
+#define DMA_DCHPRI6_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI6_CHPRI_SHIFT                  0
+#define DMA_DCHPRI6_CHPRI_WIDTH                  4
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     0x40u
+#define DMA_DCHPRI6_DPA_SHIFT                    6
+#define DMA_DCHPRI6_DPA_WIDTH                    1
+#define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_DPA_SHIFT))&DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK                     0x80u
+#define DMA_DCHPRI6_ECP_SHIFT                    7
+#define DMA_DCHPRI6_ECP_WIDTH                    1
+#define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_ECP_SHIFT))&DMA_DCHPRI6_ECP_MASK)
+/* DCHPRI5 Bit Fields */
+#define DMA_DCHPRI5_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI5_CHPRI_SHIFT                  0
+#define DMA_DCHPRI5_CHPRI_WIDTH                  4
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     0x40u
+#define DMA_DCHPRI5_DPA_SHIFT                    6
+#define DMA_DCHPRI5_DPA_WIDTH                    1
+#define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_DPA_SHIFT))&DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK                     0x80u
+#define DMA_DCHPRI5_ECP_SHIFT                    7
+#define DMA_DCHPRI5_ECP_WIDTH                    1
+#define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_ECP_SHIFT))&DMA_DCHPRI5_ECP_MASK)
+/* DCHPRI4 Bit Fields */
+#define DMA_DCHPRI4_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI4_CHPRI_SHIFT                  0
+#define DMA_DCHPRI4_CHPRI_WIDTH                  4
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     0x40u
+#define DMA_DCHPRI4_DPA_SHIFT                    6
+#define DMA_DCHPRI4_DPA_WIDTH                    1
+#define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_DPA_SHIFT))&DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK                     0x80u
+#define DMA_DCHPRI4_ECP_SHIFT                    7
+#define DMA_DCHPRI4_ECP_WIDTH                    1
+#define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_ECP_SHIFT))&DMA_DCHPRI4_ECP_MASK)
+/* DCHPRI11 Bit Fields */
+#define DMA_DCHPRI11_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI11_CHPRI_SHIFT                 0
+#define DMA_DCHPRI11_CHPRI_WIDTH                 4
+#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK                    0x40u
+#define DMA_DCHPRI11_DPA_SHIFT                   6
+#define DMA_DCHPRI11_DPA_WIDTH                   1
+#define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_DPA_SHIFT))&DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_ECP_MASK                    0x80u
+#define DMA_DCHPRI11_ECP_SHIFT                   7
+#define DMA_DCHPRI11_ECP_WIDTH                   1
+#define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_ECP_SHIFT))&DMA_DCHPRI11_ECP_MASK)
+/* DCHPRI10 Bit Fields */
+#define DMA_DCHPRI10_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI10_CHPRI_SHIFT                 0
+#define DMA_DCHPRI10_CHPRI_WIDTH                 4
+#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK                    0x40u
+#define DMA_DCHPRI10_DPA_SHIFT                   6
+#define DMA_DCHPRI10_DPA_WIDTH                   1
+#define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_DPA_SHIFT))&DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_ECP_MASK                    0x80u
+#define DMA_DCHPRI10_ECP_SHIFT                   7
+#define DMA_DCHPRI10_ECP_WIDTH                   1
+#define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_ECP_SHIFT))&DMA_DCHPRI10_ECP_MASK)
+/* DCHPRI9 Bit Fields */
+#define DMA_DCHPRI9_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI9_CHPRI_SHIFT                  0
+#define DMA_DCHPRI9_CHPRI_WIDTH                  4
+#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK                     0x40u
+#define DMA_DCHPRI9_DPA_SHIFT                    6
+#define DMA_DCHPRI9_DPA_WIDTH                    1
+#define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_DPA_SHIFT))&DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_ECP_MASK                     0x80u
+#define DMA_DCHPRI9_ECP_SHIFT                    7
+#define DMA_DCHPRI9_ECP_WIDTH                    1
+#define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_ECP_SHIFT))&DMA_DCHPRI9_ECP_MASK)
+/* DCHPRI8 Bit Fields */
+#define DMA_DCHPRI8_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI8_CHPRI_SHIFT                  0
+#define DMA_DCHPRI8_CHPRI_WIDTH                  4
+#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK                     0x40u
+#define DMA_DCHPRI8_DPA_SHIFT                    6
+#define DMA_DCHPRI8_DPA_WIDTH                    1
+#define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_DPA_SHIFT))&DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_ECP_MASK                     0x80u
+#define DMA_DCHPRI8_ECP_SHIFT                    7
+#define DMA_DCHPRI8_ECP_WIDTH                    1
+#define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_ECP_SHIFT))&DMA_DCHPRI8_ECP_MASK)
+/* DCHPRI15 Bit Fields */
+#define DMA_DCHPRI15_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI15_CHPRI_SHIFT                 0
+#define DMA_DCHPRI15_CHPRI_WIDTH                 4
+#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK                    0x40u
+#define DMA_DCHPRI15_DPA_SHIFT                   6
+#define DMA_DCHPRI15_DPA_WIDTH                   1
+#define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_DPA_SHIFT))&DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_ECP_MASK                    0x80u
+#define DMA_DCHPRI15_ECP_SHIFT                   7
+#define DMA_DCHPRI15_ECP_WIDTH                   1
+#define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_ECP_SHIFT))&DMA_DCHPRI15_ECP_MASK)
+/* DCHPRI14 Bit Fields */
+#define DMA_DCHPRI14_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI14_CHPRI_SHIFT                 0
+#define DMA_DCHPRI14_CHPRI_WIDTH                 4
+#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK                    0x40u
+#define DMA_DCHPRI14_DPA_SHIFT                   6
+#define DMA_DCHPRI14_DPA_WIDTH                   1
+#define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_DPA_SHIFT))&DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_ECP_MASK                    0x80u
+#define DMA_DCHPRI14_ECP_SHIFT                   7
+#define DMA_DCHPRI14_ECP_WIDTH                   1
+#define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_ECP_SHIFT))&DMA_DCHPRI14_ECP_MASK)
+/* DCHPRI13 Bit Fields */
+#define DMA_DCHPRI13_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI13_CHPRI_SHIFT                 0
+#define DMA_DCHPRI13_CHPRI_WIDTH                 4
+#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK                    0x40u
+#define DMA_DCHPRI13_DPA_SHIFT                   6
+#define DMA_DCHPRI13_DPA_WIDTH                   1
+#define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_DPA_SHIFT))&DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_ECP_MASK                    0x80u
+#define DMA_DCHPRI13_ECP_SHIFT                   7
+#define DMA_DCHPRI13_ECP_WIDTH                   1
+#define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_ECP_SHIFT))&DMA_DCHPRI13_ECP_MASK)
+/* DCHPRI12 Bit Fields */
+#define DMA_DCHPRI12_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI12_CHPRI_SHIFT                 0
+#define DMA_DCHPRI12_CHPRI_WIDTH                 4
+#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK                    0x40u
+#define DMA_DCHPRI12_DPA_SHIFT                   6
+#define DMA_DCHPRI12_DPA_WIDTH                   1
+#define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_DPA_SHIFT))&DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_ECP_MASK                    0x80u
+#define DMA_DCHPRI12_ECP_SHIFT                   7
+#define DMA_DCHPRI12_ECP_WIDTH                   1
+#define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_ECP_SHIFT))&DMA_DCHPRI12_ECP_MASK)
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK                     0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT                    0
+#define DMA_SADDR_SADDR_WIDTH                    32
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK                       0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT                      0
+#define DMA_SOFF_SOFF_WIDTH                      16
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK                      0x7u
+#define DMA_ATTR_DSIZE_SHIFT                     0
+#define DMA_ATTR_DSIZE_WIDTH                     3
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       0xF8u
+#define DMA_ATTR_DMOD_SHIFT                      3
+#define DMA_ATTR_DMOD_WIDTH                      5
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      0x700u
+#define DMA_ATTR_SSIZE_SHIFT                     8
+#define DMA_ATTR_SSIZE_WIDTH                     3
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       0xF800u
+#define DMA_ATTR_SMOD_SHIFT                      11
+#define DMA_ATTR_SMOD_WIDTH                      5
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             0
+#define DMA_NBYTES_MLNO_NBYTES_WIDTH             32
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          0
+#define DMA_NBYTES_MLOFFNO_NBYTES_WIDTH          30
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           30
+#define DMA_NBYTES_MLOFFNO_DMLOE_WIDTH           1
+#define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           31
+#define DMA_NBYTES_MLOFFNO_SMLOE_WIDTH           1
+#define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         0
+#define DMA_NBYTES_MLOFFYES_NBYTES_WIDTH         10
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          10
+#define DMA_NBYTES_MLOFFYES_MLOFF_WIDTH          20
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          30
+#define DMA_NBYTES_MLOFFYES_DMLOE_WIDTH          1
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          31
+#define DMA_NBYTES_MLOFFYES_SMLOE_WIDTH          1
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK                     0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT                    0
+#define DMA_SLAST_SLAST_WIDTH                    32
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK                     0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT                    0
+#define DMA_DADDR_DADDR_WIDTH                    32
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK                       0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT                      0
+#define DMA_DOFF_DOFF_WIDTH                      16
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK             0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT            0
+#define DMA_CITER_ELINKNO_CITER_WIDTH            15
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            15
+#define DMA_CITER_ELINKNO_ELINK_WIDTH            1
+#define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_ELINK_SHIFT))&DMA_CITER_ELINKNO_ELINK_MASK)
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK            0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT           0
+#define DMA_CITER_ELINKYES_CITER_WIDTH           9
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_CITER_ELINKYES_LINKCH_WIDTH          4
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           15
+#define DMA_CITER_ELINKYES_ELINK_WIDTH           1
+#define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_ELINK_SHIFT))&DMA_CITER_ELINKYES_ELINK_MASK)
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             0
+#define DMA_DLAST_SGA_DLASTSGA_WIDTH             32
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK                       0x1u
+#define DMA_CSR_START_SHIFT                      0
+#define DMA_CSR_START_WIDTH                      1
+#define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_CSR_START_SHIFT))&DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK                    0x2u
+#define DMA_CSR_INTMAJOR_SHIFT                   1
+#define DMA_CSR_INTMAJOR_WIDTH                   1
+#define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTMAJOR_SHIFT))&DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK                     0x4u
+#define DMA_CSR_INTHALF_SHIFT                    2
+#define DMA_CSR_INTHALF_WIDTH                    1
+#define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTHALF_SHIFT))&DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK                        0x8u
+#define DMA_CSR_DREQ_SHIFT                       3
+#define DMA_CSR_DREQ_WIDTH                       1
+#define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DREQ_SHIFT))&DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK                         0x10u
+#define DMA_CSR_ESG_SHIFT                        4
+#define DMA_CSR_ESG_WIDTH                        1
+#define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ESG_SHIFT))&DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK                  0x20u
+#define DMA_CSR_MAJORELINK_SHIFT                 5
+#define DMA_CSR_MAJORELINK_WIDTH                 1
+#define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORELINK_SHIFT))&DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK                      0x40u
+#define DMA_CSR_ACTIVE_SHIFT                     6
+#define DMA_CSR_ACTIVE_WIDTH                     1
+#define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ACTIVE_SHIFT))&DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK                        0x80u
+#define DMA_CSR_DONE_SHIFT                       7
+#define DMA_CSR_DONE_WIDTH                       1
+#define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DONE_SHIFT))&DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK                 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT                8
+#define DMA_CSR_MAJORLINKCH_WIDTH                4
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         0xC000u
+#define DMA_CSR_BWC_SHIFT                        14
+#define DMA_CSR_BWC_WIDTH                        2
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK             0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT            0
+#define DMA_BITER_ELINKNO_BITER_WIDTH            15
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            15
+#define DMA_BITER_ELINKNO_ELINK_WIDTH            1
+#define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_ELINK_SHIFT))&DMA_BITER_ELINKNO_ELINK_MASK)
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK            0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT           0
+#define DMA_BITER_ELINKYES_BITER_WIDTH           9
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_BITER_ELINKYES_LINKCH_WIDTH          4
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           15
+#define DMA_BITER_ELINKYES_ELINK_WIDTH           1
+#define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_ELINK_SHIFT))&DMA_BITER_ELINKYES_ELINK_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR                             (DMA0)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_CR                                   DMA_CR_REG(DMA0)
+#define DMA_ES                                   DMA_ES_REG(DMA0)
+#define DMA_ERQ                                  DMA_ERQ_REG(DMA0)
+#define DMA_EEI                                  DMA_EEI_REG(DMA0)
+#define DMA_CEEI                                 DMA_CEEI_REG(DMA0)
+#define DMA_SEEI                                 DMA_SEEI_REG(DMA0)
+#define DMA_CERQ                                 DMA_CERQ_REG(DMA0)
+#define DMA_SERQ                                 DMA_SERQ_REG(DMA0)
+#define DMA_CDNE                                 DMA_CDNE_REG(DMA0)
+#define DMA_SSRT                                 DMA_SSRT_REG(DMA0)
+#define DMA_CERR                                 DMA_CERR_REG(DMA0)
+#define DMA_CINT                                 DMA_CINT_REG(DMA0)
+#define DMA_INT                                  DMA_INT_REG(DMA0)
+#define DMA_ERR                                  DMA_ERR_REG(DMA0)
+#define DMA_HRS                                  DMA_HRS_REG(DMA0)
+#define DMA_DCHPRI3                              DMA_DCHPRI3_REG(DMA0)
+#define DMA_DCHPRI2                              DMA_DCHPRI2_REG(DMA0)
+#define DMA_DCHPRI1                              DMA_DCHPRI1_REG(DMA0)
+#define DMA_DCHPRI0                              DMA_DCHPRI0_REG(DMA0)
+#define DMA_DCHPRI7                              DMA_DCHPRI7_REG(DMA0)
+#define DMA_DCHPRI6                              DMA_DCHPRI6_REG(DMA0)
+#define DMA_DCHPRI5                              DMA_DCHPRI5_REG(DMA0)
+#define DMA_DCHPRI4                              DMA_DCHPRI4_REG(DMA0)
+#define DMA_DCHPRI11                             DMA_DCHPRI11_REG(DMA0)
+#define DMA_DCHPRI10                             DMA_DCHPRI10_REG(DMA0)
+#define DMA_DCHPRI9                              DMA_DCHPRI9_REG(DMA0)
+#define DMA_DCHPRI8                              DMA_DCHPRI8_REG(DMA0)
+#define DMA_DCHPRI15                             DMA_DCHPRI15_REG(DMA0)
+#define DMA_DCHPRI14                             DMA_DCHPRI14_REG(DMA0)
+#define DMA_DCHPRI13                             DMA_DCHPRI13_REG(DMA0)
+#define DMA_DCHPRI12                             DMA_DCHPRI12_REG(DMA0)
+#define DMA_TCD0_SADDR                           DMA_SADDR_REG(DMA0,0)
+#define DMA_TCD0_SOFF                            DMA_SOFF_REG(DMA0,0)
+#define DMA_TCD0_ATTR                            DMA_ATTR_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,0)
+#define DMA_TCD0_SLAST                           DMA_SLAST_REG(DMA0,0)
+#define DMA_TCD0_DADDR                           DMA_DADDR_REG(DMA0,0)
+#define DMA_TCD0_DOFF                            DMA_DOFF_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD0_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,0)
+#define DMA_TCD0_CSR                             DMA_CSR_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD1_SADDR                           DMA_SADDR_REG(DMA0,1)
+#define DMA_TCD1_SOFF                            DMA_SOFF_REG(DMA0,1)
+#define DMA_TCD1_ATTR                            DMA_ATTR_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,1)
+#define DMA_TCD1_SLAST                           DMA_SLAST_REG(DMA0,1)
+#define DMA_TCD1_DADDR                           DMA_DADDR_REG(DMA0,1)
+#define DMA_TCD1_DOFF                            DMA_DOFF_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD1_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,1)
+#define DMA_TCD1_CSR                             DMA_CSR_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD2_SADDR                           DMA_SADDR_REG(DMA0,2)
+#define DMA_TCD2_SOFF                            DMA_SOFF_REG(DMA0,2)
+#define DMA_TCD2_ATTR                            DMA_ATTR_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,2)
+#define DMA_TCD2_SLAST                           DMA_SLAST_REG(DMA0,2)
+#define DMA_TCD2_DADDR                           DMA_DADDR_REG(DMA0,2)
+#define DMA_TCD2_DOFF                            DMA_DOFF_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD2_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,2)
+#define DMA_TCD2_CSR                             DMA_CSR_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD3_SADDR                           DMA_SADDR_REG(DMA0,3)
+#define DMA_TCD3_SOFF                            DMA_SOFF_REG(DMA0,3)
+#define DMA_TCD3_ATTR                            DMA_ATTR_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,3)
+#define DMA_TCD3_SLAST                           DMA_SLAST_REG(DMA0,3)
+#define DMA_TCD3_DADDR                           DMA_DADDR_REG(DMA0,3)
+#define DMA_TCD3_DOFF                            DMA_DOFF_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD3_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,3)
+#define DMA_TCD3_CSR                             DMA_CSR_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD4_SADDR                           DMA_SADDR_REG(DMA0,4)
+#define DMA_TCD4_SOFF                            DMA_SOFF_REG(DMA0,4)
+#define DMA_TCD4_ATTR                            DMA_ATTR_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,4)
+#define DMA_TCD4_SLAST                           DMA_SLAST_REG(DMA0,4)
+#define DMA_TCD4_DADDR                           DMA_DADDR_REG(DMA0,4)
+#define DMA_TCD4_DOFF                            DMA_DOFF_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD4_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,4)
+#define DMA_TCD4_CSR                             DMA_CSR_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD5_SADDR                           DMA_SADDR_REG(DMA0,5)
+#define DMA_TCD5_SOFF                            DMA_SOFF_REG(DMA0,5)
+#define DMA_TCD5_ATTR                            DMA_ATTR_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,5)
+#define DMA_TCD5_SLAST                           DMA_SLAST_REG(DMA0,5)
+#define DMA_TCD5_DADDR                           DMA_DADDR_REG(DMA0,5)
+#define DMA_TCD5_DOFF                            DMA_DOFF_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD5_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,5)
+#define DMA_TCD5_CSR                             DMA_CSR_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD6_SADDR                           DMA_SADDR_REG(DMA0,6)
+#define DMA_TCD6_SOFF                            DMA_SOFF_REG(DMA0,6)
+#define DMA_TCD6_ATTR                            DMA_ATTR_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,6)
+#define DMA_TCD6_SLAST                           DMA_SLAST_REG(DMA0,6)
+#define DMA_TCD6_DADDR                           DMA_DADDR_REG(DMA0,6)
+#define DMA_TCD6_DOFF                            DMA_DOFF_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD6_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,6)
+#define DMA_TCD6_CSR                             DMA_CSR_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD7_SADDR                           DMA_SADDR_REG(DMA0,7)
+#define DMA_TCD7_SOFF                            DMA_SOFF_REG(DMA0,7)
+#define DMA_TCD7_ATTR                            DMA_ATTR_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,7)
+#define DMA_TCD7_SLAST                           DMA_SLAST_REG(DMA0,7)
+#define DMA_TCD7_DADDR                           DMA_DADDR_REG(DMA0,7)
+#define DMA_TCD7_DOFF                            DMA_DOFF_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD7_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,7)
+#define DMA_TCD7_CSR                             DMA_CSR_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD8_SADDR                           DMA_SADDR_REG(DMA0,8)
+#define DMA_TCD8_SOFF                            DMA_SOFF_REG(DMA0,8)
+#define DMA_TCD8_ATTR                            DMA_ATTR_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,8)
+#define DMA_TCD8_SLAST                           DMA_SLAST_REG(DMA0,8)
+#define DMA_TCD8_DADDR                           DMA_DADDR_REG(DMA0,8)
+#define DMA_TCD8_DOFF                            DMA_DOFF_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD8_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,8)
+#define DMA_TCD8_CSR                             DMA_CSR_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD9_SADDR                           DMA_SADDR_REG(DMA0,9)
+#define DMA_TCD9_SOFF                            DMA_SOFF_REG(DMA0,9)
+#define DMA_TCD9_ATTR                            DMA_ATTR_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,9)
+#define DMA_TCD9_SLAST                           DMA_SLAST_REG(DMA0,9)
+#define DMA_TCD9_DADDR                           DMA_DADDR_REG(DMA0,9)
+#define DMA_TCD9_DOFF                            DMA_DOFF_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD9_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,9)
+#define DMA_TCD9_CSR                             DMA_CSR_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD10_SADDR                          DMA_SADDR_REG(DMA0,10)
+#define DMA_TCD10_SOFF                           DMA_SOFF_REG(DMA0,10)
+#define DMA_TCD10_ATTR                           DMA_ATTR_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,10)
+#define DMA_TCD10_SLAST                          DMA_SLAST_REG(DMA0,10)
+#define DMA_TCD10_DADDR                          DMA_DADDR_REG(DMA0,10)
+#define DMA_TCD10_DOFF                           DMA_DOFF_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD10_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,10)
+#define DMA_TCD10_CSR                            DMA_CSR_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD11_SADDR                          DMA_SADDR_REG(DMA0,11)
+#define DMA_TCD11_SOFF                           DMA_SOFF_REG(DMA0,11)
+#define DMA_TCD11_ATTR                           DMA_ATTR_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,11)
+#define DMA_TCD11_SLAST                          DMA_SLAST_REG(DMA0,11)
+#define DMA_TCD11_DADDR                          DMA_DADDR_REG(DMA0,11)
+#define DMA_TCD11_DOFF                           DMA_DOFF_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD11_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,11)
+#define DMA_TCD11_CSR                            DMA_CSR_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD12_SADDR                          DMA_SADDR_REG(DMA0,12)
+#define DMA_TCD12_SOFF                           DMA_SOFF_REG(DMA0,12)
+#define DMA_TCD12_ATTR                           DMA_ATTR_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,12)
+#define DMA_TCD12_SLAST                          DMA_SLAST_REG(DMA0,12)
+#define DMA_TCD12_DADDR                          DMA_DADDR_REG(DMA0,12)
+#define DMA_TCD12_DOFF                           DMA_DOFF_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD12_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,12)
+#define DMA_TCD12_CSR                            DMA_CSR_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD13_SADDR                          DMA_SADDR_REG(DMA0,13)
+#define DMA_TCD13_SOFF                           DMA_SOFF_REG(DMA0,13)
+#define DMA_TCD13_ATTR                           DMA_ATTR_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,13)
+#define DMA_TCD13_SLAST                          DMA_SLAST_REG(DMA0,13)
+#define DMA_TCD13_DADDR                          DMA_DADDR_REG(DMA0,13)
+#define DMA_TCD13_DOFF                           DMA_DOFF_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD13_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,13)
+#define DMA_TCD13_CSR                            DMA_CSR_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD14_SADDR                          DMA_SADDR_REG(DMA0,14)
+#define DMA_TCD14_SOFF                           DMA_SOFF_REG(DMA0,14)
+#define DMA_TCD14_ATTR                           DMA_ATTR_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,14)
+#define DMA_TCD14_SLAST                          DMA_SLAST_REG(DMA0,14)
+#define DMA_TCD14_DADDR                          DMA_DADDR_REG(DMA0,14)
+#define DMA_TCD14_DOFF                           DMA_DOFF_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD14_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,14)
+#define DMA_TCD14_CSR                            DMA_CSR_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD15_SADDR                          DMA_SADDR_REG(DMA0,15)
+#define DMA_TCD15_SOFF                           DMA_SOFF_REG(DMA0,15)
+#define DMA_TCD15_ATTR                           DMA_ATTR_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,15)
+#define DMA_TCD15_SLAST                          DMA_SLAST_REG(DMA0,15)
+#define DMA_TCD15_DADDR                          DMA_DADDR_REG(DMA0,15)
+#define DMA_TCD15_DOFF                           DMA_DOFF_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,15)
+#define DMA_TCD15_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,15)
+#define DMA_TCD15_CSR                            DMA_CSR_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,15)
+
+/* DMA - Register array accessors */
+#define DMA_SADDR(index)                         DMA_SADDR_REG(DMA0,index)
+#define DMA_SOFF(index)                          DMA_SOFF_REG(DMA0,index)
+#define DMA_ATTR(index)                          DMA_ATTR_REG(DMA0,index)
+#define DMA_NBYTES_MLNO(index)                   DMA_NBYTES_MLNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFNO(index)                DMA_NBYTES_MLOFFNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFYES(index)               DMA_NBYTES_MLOFFYES_REG(DMA0,index)
+#define DMA_SLAST(index)                         DMA_SLAST_REG(DMA0,index)
+#define DMA_DADDR(index)                         DMA_DADDR_REG(DMA0,index)
+#define DMA_DOFF(index)                          DMA_DOFF_REG(DMA0,index)
+#define DMA_CITER_ELINKNO(index)                 DMA_CITER_ELINKNO_REG(DMA0,index)
+#define DMA_CITER_ELINKYES(index)                DMA_CITER_ELINKYES_REG(DMA0,index)
+#define DMA_DLAST_SGA(index)                     DMA_DLAST_SGA_REG(DMA0,index)
+#define DMA_CSR(index)                           DMA_CSR_REG(DMA0,index)
+#define DMA_BITER_ELINKNO(index)                 DMA_BITER_ELINKNO_REG(DMA0,index)
+#define DMA_BITER_ELINKYES(index)                DMA_BITER_ELINKYES_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[16];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index)             ((base)->CHCFG[index])
+#define DMAMUX_CHCFG_COUNT                       16
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT                0
+#define DMAMUX_CHCFG_SOURCE_WIDTH                6
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT                  6
+#define DMAMUX_CHCFG_TRIG_WIDTH                  1
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT                  7
+#define DMAMUX_CHCFG_ENBL_WIDTH                  1
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE                              (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
+#define DMAMUX_BASE_PTR                          (DMAMUX)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { DMAMUX }
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX */
+#define DMAMUX_CHCFG0                            DMAMUX_CHCFG_REG(DMAMUX,0)
+#define DMAMUX_CHCFG1                            DMAMUX_CHCFG_REG(DMAMUX,1)
+#define DMAMUX_CHCFG2                            DMAMUX_CHCFG_REG(DMAMUX,2)
+#define DMAMUX_CHCFG3                            DMAMUX_CHCFG_REG(DMAMUX,3)
+#define DMAMUX_CHCFG4                            DMAMUX_CHCFG_REG(DMAMUX,4)
+#define DMAMUX_CHCFG5                            DMAMUX_CHCFG_REG(DMAMUX,5)
+#define DMAMUX_CHCFG6                            DMAMUX_CHCFG_REG(DMAMUX,6)
+#define DMAMUX_CHCFG7                            DMAMUX_CHCFG_REG(DMAMUX,7)
+#define DMAMUX_CHCFG8                            DMAMUX_CHCFG_REG(DMAMUX,8)
+#define DMAMUX_CHCFG9                            DMAMUX_CHCFG_REG(DMAMUX,9)
+#define DMAMUX_CHCFG10                           DMAMUX_CHCFG_REG(DMAMUX,10)
+#define DMAMUX_CHCFG11                           DMAMUX_CHCFG_REG(DMAMUX,11)
+#define DMAMUX_CHCFG12                           DMAMUX_CHCFG_REG(DMAMUX,12)
+#define DMAMUX_CHCFG13                           DMAMUX_CHCFG_REG(DMAMUX,13)
+#define DMAMUX_CHCFG14                           DMAMUX_CHCFG_REG(DMAMUX,14)
+#define DMAMUX_CHCFG15                           DMAMUX_CHCFG_REG(DMAMUX,15)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX_CHCFG(index)                      DMAMUX_CHCFG_REG(DMAMUX,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4];
+  __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
+  __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register, offset: 0x10 */
+  __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register, offset: 0x14 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
+  __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
+       uint8_t RESERVED_4[28];
+  __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
+       uint8_t RESERVED_5[28];
+  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
+  __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
+  __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
+       uint8_t RESERVED_8[40];
+  __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+  __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+  __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
+  __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
+       uint8_t RESERVED_9[28];
+  __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
+       uint8_t RESERVED_10[56];
+  __IO uint32_t RDSR;                              /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+  __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+  __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+  __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+  __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+  __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+  __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+  __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+  __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+  __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+  __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
+       uint8_t RESERVED_12[12];
+  __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+  __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+       uint8_t RESERVED_13[60];
+  __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
+  __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
+  __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
+  __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
+  __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
+  __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
+  __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
+  __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
+  __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
+  __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
+  __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
+  __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
+  __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
+  __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
+  __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
+  __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
+  __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
+       uint8_t RESERVED_14[4];
+  __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
+  __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
+  __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
+  __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
+  __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
+  __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
+  __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
+  __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
+       uint8_t RESERVED_15[4];
+  __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
+  __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
+       uint8_t RESERVED_16[12];
+  __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
+  __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
+  __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
+  __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
+  __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
+  __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
+  __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
+  __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
+       uint8_t RESERVED_17[4];
+  __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
+  __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
+  __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
+  __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
+  __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
+  __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
+  __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
+  __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
+  __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
+  __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
+  __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
+  __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
+  __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
+  __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
+  __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
+       uint8_t RESERVED_18[284];
+  __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
+  __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
+  __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
+  __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
+  __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
+  __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
+  __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+       uint8_t RESERVED_19[488];
+  __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
+  struct {                                         /* offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+  } CHANNEL[4];
+} ENET_Type, *ENET_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register accessors */
+#define ENET_EIR_REG(base)                       ((base)->EIR)
+#define ENET_EIMR_REG(base)                      ((base)->EIMR)
+#define ENET_RDAR_REG(base)                      ((base)->RDAR)
+#define ENET_TDAR_REG(base)                      ((base)->TDAR)
+#define ENET_ECR_REG(base)                       ((base)->ECR)
+#define ENET_MMFR_REG(base)                      ((base)->MMFR)
+#define ENET_MSCR_REG(base)                      ((base)->MSCR)
+#define ENET_MIBC_REG(base)                      ((base)->MIBC)
+#define ENET_RCR_REG(base)                       ((base)->RCR)
+#define ENET_TCR_REG(base)                       ((base)->TCR)
+#define ENET_PALR_REG(base)                      ((base)->PALR)
+#define ENET_PAUR_REG(base)                      ((base)->PAUR)
+#define ENET_OPD_REG(base)                       ((base)->OPD)
+#define ENET_IAUR_REG(base)                      ((base)->IAUR)
+#define ENET_IALR_REG(base)                      ((base)->IALR)
+#define ENET_GAUR_REG(base)                      ((base)->GAUR)
+#define ENET_GALR_REG(base)                      ((base)->GALR)
+#define ENET_TFWR_REG(base)                      ((base)->TFWR)
+#define ENET_RDSR_REG(base)                      ((base)->RDSR)
+#define ENET_TDSR_REG(base)                      ((base)->TDSR)
+#define ENET_MRBR_REG(base)                      ((base)->MRBR)
+#define ENET_RSFL_REG(base)                      ((base)->RSFL)
+#define ENET_RSEM_REG(base)                      ((base)->RSEM)
+#define ENET_RAEM_REG(base)                      ((base)->RAEM)
+#define ENET_RAFL_REG(base)                      ((base)->RAFL)
+#define ENET_TSEM_REG(base)                      ((base)->TSEM)
+#define ENET_TAEM_REG(base)                      ((base)->TAEM)
+#define ENET_TAFL_REG(base)                      ((base)->TAFL)
+#define ENET_TIPG_REG(base)                      ((base)->TIPG)
+#define ENET_FTRL_REG(base)                      ((base)->FTRL)
+#define ENET_TACC_REG(base)                      ((base)->TACC)
+#define ENET_RACC_REG(base)                      ((base)->RACC)
+#define ENET_RMON_T_PACKETS_REG(base)            ((base)->RMON_T_PACKETS)
+#define ENET_RMON_T_BC_PKT_REG(base)             ((base)->RMON_T_BC_PKT)
+#define ENET_RMON_T_MC_PKT_REG(base)             ((base)->RMON_T_MC_PKT)
+#define ENET_RMON_T_CRC_ALIGN_REG(base)          ((base)->RMON_T_CRC_ALIGN)
+#define ENET_RMON_T_UNDERSIZE_REG(base)          ((base)->RMON_T_UNDERSIZE)
+#define ENET_RMON_T_OVERSIZE_REG(base)           ((base)->RMON_T_OVERSIZE)
+#define ENET_RMON_T_FRAG_REG(base)               ((base)->RMON_T_FRAG)
+#define ENET_RMON_T_JAB_REG(base)                ((base)->RMON_T_JAB)
+#define ENET_RMON_T_COL_REG(base)                ((base)->RMON_T_COL)
+#define ENET_RMON_T_P64_REG(base)                ((base)->RMON_T_P64)
+#define ENET_RMON_T_P65TO127_REG(base)           ((base)->RMON_T_P65TO127)
+#define ENET_RMON_T_P128TO255_REG(base)          ((base)->RMON_T_P128TO255)
+#define ENET_RMON_T_P256TO511_REG(base)          ((base)->RMON_T_P256TO511)
+#define ENET_RMON_T_P512TO1023_REG(base)         ((base)->RMON_T_P512TO1023)
+#define ENET_RMON_T_P1024TO2047_REG(base)        ((base)->RMON_T_P1024TO2047)
+#define ENET_RMON_T_P_GTE2048_REG(base)          ((base)->RMON_T_P_GTE2048)
+#define ENET_RMON_T_OCTETS_REG(base)             ((base)->RMON_T_OCTETS)
+#define ENET_IEEE_T_FRAME_OK_REG(base)           ((base)->IEEE_T_FRAME_OK)
+#define ENET_IEEE_T_1COL_REG(base)               ((base)->IEEE_T_1COL)
+#define ENET_IEEE_T_MCOL_REG(base)               ((base)->IEEE_T_MCOL)
+#define ENET_IEEE_T_DEF_REG(base)                ((base)->IEEE_T_DEF)
+#define ENET_IEEE_T_LCOL_REG(base)               ((base)->IEEE_T_LCOL)
+#define ENET_IEEE_T_EXCOL_REG(base)              ((base)->IEEE_T_EXCOL)
+#define ENET_IEEE_T_MACERR_REG(base)             ((base)->IEEE_T_MACERR)
+#define ENET_IEEE_T_CSERR_REG(base)              ((base)->IEEE_T_CSERR)
+#define ENET_IEEE_T_FDXFC_REG(base)              ((base)->IEEE_T_FDXFC)
+#define ENET_IEEE_T_OCTETS_OK_REG(base)          ((base)->IEEE_T_OCTETS_OK)
+#define ENET_RMON_R_PACKETS_REG(base)            ((base)->RMON_R_PACKETS)
+#define ENET_RMON_R_BC_PKT_REG(base)             ((base)->RMON_R_BC_PKT)
+#define ENET_RMON_R_MC_PKT_REG(base)             ((base)->RMON_R_MC_PKT)
+#define ENET_RMON_R_CRC_ALIGN_REG(base)          ((base)->RMON_R_CRC_ALIGN)
+#define ENET_RMON_R_UNDERSIZE_REG(base)          ((base)->RMON_R_UNDERSIZE)
+#define ENET_RMON_R_OVERSIZE_REG(base)           ((base)->RMON_R_OVERSIZE)
+#define ENET_RMON_R_FRAG_REG(base)               ((base)->RMON_R_FRAG)
+#define ENET_RMON_R_JAB_REG(base)                ((base)->RMON_R_JAB)
+#define ENET_RMON_R_P64_REG(base)                ((base)->RMON_R_P64)
+#define ENET_RMON_R_P65TO127_REG(base)           ((base)->RMON_R_P65TO127)
+#define ENET_RMON_R_P128TO255_REG(base)          ((base)->RMON_R_P128TO255)
+#define ENET_RMON_R_P256TO511_REG(base)          ((base)->RMON_R_P256TO511)
+#define ENET_RMON_R_P512TO1023_REG(base)         ((base)->RMON_R_P512TO1023)
+#define ENET_RMON_R_P1024TO2047_REG(base)        ((base)->RMON_R_P1024TO2047)
+#define ENET_RMON_R_P_GTE2048_REG(base)          ((base)->RMON_R_P_GTE2048)
+#define ENET_RMON_R_OCTETS_REG(base)             ((base)->RMON_R_OCTETS)
+#define ENET_IEEE_R_DROP_REG(base)               ((base)->IEEE_R_DROP)
+#define ENET_IEEE_R_FRAME_OK_REG(base)           ((base)->IEEE_R_FRAME_OK)
+#define ENET_IEEE_R_CRC_REG(base)                ((base)->IEEE_R_CRC)
+#define ENET_IEEE_R_ALIGN_REG(base)              ((base)->IEEE_R_ALIGN)
+#define ENET_IEEE_R_MACERR_REG(base)             ((base)->IEEE_R_MACERR)
+#define ENET_IEEE_R_FDXFC_REG(base)              ((base)->IEEE_R_FDXFC)
+#define ENET_IEEE_R_OCTETS_OK_REG(base)          ((base)->IEEE_R_OCTETS_OK)
+#define ENET_ATCR_REG(base)                      ((base)->ATCR)
+#define ENET_ATVR_REG(base)                      ((base)->ATVR)
+#define ENET_ATOFF_REG(base)                     ((base)->ATOFF)
+#define ENET_ATPER_REG(base)                     ((base)->ATPER)
+#define ENET_ATCOR_REG(base)                     ((base)->ATCOR)
+#define ENET_ATINC_REG(base)                     ((base)->ATINC)
+#define ENET_ATSTMP_REG(base)                    ((base)->ATSTMP)
+#define ENET_TGSR_REG(base)                      ((base)->TGSR)
+#define ENET_TCSR_REG(base,index)                ((base)->CHANNEL[index].TCSR)
+#define ENET_TCSR_COUNT                          4
+#define ENET_TCCR_REG(base,index)                ((base)->CHANNEL[index].TCCR)
+#define ENET_TCCR_COUNT                          4
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/* EIR Bit Fields */
+#define ENET_EIR_TS_TIMER_MASK                   0x8000u
+#define ENET_EIR_TS_TIMER_SHIFT                  15
+#define ENET_EIR_TS_TIMER_WIDTH                  1
+#define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_TIMER_SHIFT))&ENET_EIR_TS_TIMER_MASK)
+#define ENET_EIR_TS_AVAIL_MASK                   0x10000u
+#define ENET_EIR_TS_AVAIL_SHIFT                  16
+#define ENET_EIR_TS_AVAIL_WIDTH                  1
+#define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_AVAIL_SHIFT))&ENET_EIR_TS_AVAIL_MASK)
+#define ENET_EIR_WAKEUP_MASK                     0x20000u
+#define ENET_EIR_WAKEUP_SHIFT                    17
+#define ENET_EIR_WAKEUP_WIDTH                    1
+#define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_EIR_WAKEUP_SHIFT))&ENET_EIR_WAKEUP_MASK)
+#define ENET_EIR_PLR_MASK                        0x40000u
+#define ENET_EIR_PLR_SHIFT                       18
+#define ENET_EIR_PLR_WIDTH                       1
+#define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_PLR_SHIFT))&ENET_EIR_PLR_MASK)
+#define ENET_EIR_UN_MASK                         0x80000u
+#define ENET_EIR_UN_SHIFT                        19
+#define ENET_EIR_UN_WIDTH                        1
+#define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_UN_SHIFT))&ENET_EIR_UN_MASK)
+#define ENET_EIR_RL_MASK                         0x100000u
+#define ENET_EIR_RL_SHIFT                        20
+#define ENET_EIR_RL_WIDTH                        1
+#define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RL_SHIFT))&ENET_EIR_RL_MASK)
+#define ENET_EIR_LC_MASK                         0x200000u
+#define ENET_EIR_LC_SHIFT                        21
+#define ENET_EIR_LC_WIDTH                        1
+#define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_LC_SHIFT))&ENET_EIR_LC_MASK)
+#define ENET_EIR_EBERR_MASK                      0x400000u
+#define ENET_EIR_EBERR_SHIFT                     22
+#define ENET_EIR_EBERR_WIDTH                     1
+#define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIR_EBERR_SHIFT))&ENET_EIR_EBERR_MASK)
+#define ENET_EIR_MII_MASK                        0x800000u
+#define ENET_EIR_MII_SHIFT                       23
+#define ENET_EIR_MII_WIDTH                       1
+#define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_MII_SHIFT))&ENET_EIR_MII_MASK)
+#define ENET_EIR_RXB_MASK                        0x1000000u
+#define ENET_EIR_RXB_SHIFT                       24
+#define ENET_EIR_RXB_WIDTH                       1
+#define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXB_SHIFT))&ENET_EIR_RXB_MASK)
+#define ENET_EIR_RXF_MASK                        0x2000000u
+#define ENET_EIR_RXF_SHIFT                       25
+#define ENET_EIR_RXF_WIDTH                       1
+#define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXF_SHIFT))&ENET_EIR_RXF_MASK)
+#define ENET_EIR_TXB_MASK                        0x4000000u
+#define ENET_EIR_TXB_SHIFT                       26
+#define ENET_EIR_TXB_WIDTH                       1
+#define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXB_SHIFT))&ENET_EIR_TXB_MASK)
+#define ENET_EIR_TXF_MASK                        0x8000000u
+#define ENET_EIR_TXF_SHIFT                       27
+#define ENET_EIR_TXF_WIDTH                       1
+#define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXF_SHIFT))&ENET_EIR_TXF_MASK)
+#define ENET_EIR_GRA_MASK                        0x10000000u
+#define ENET_EIR_GRA_SHIFT                       28
+#define ENET_EIR_GRA_WIDTH                       1
+#define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_GRA_SHIFT))&ENET_EIR_GRA_MASK)
+#define ENET_EIR_BABT_MASK                       0x20000000u
+#define ENET_EIR_BABT_SHIFT                      29
+#define ENET_EIR_BABT_WIDTH                      1
+#define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABT_SHIFT))&ENET_EIR_BABT_MASK)
+#define ENET_EIR_BABR_MASK                       0x40000000u
+#define ENET_EIR_BABR_SHIFT                      30
+#define ENET_EIR_BABR_WIDTH                      1
+#define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABR_SHIFT))&ENET_EIR_BABR_MASK)
+/* EIMR Bit Fields */
+#define ENET_EIMR_TS_TIMER_MASK                  0x8000u
+#define ENET_EIMR_TS_TIMER_SHIFT                 15
+#define ENET_EIMR_TS_TIMER_WIDTH                 1
+#define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_TIMER_SHIFT))&ENET_EIMR_TS_TIMER_MASK)
+#define ENET_EIMR_TS_AVAIL_MASK                  0x10000u
+#define ENET_EIMR_TS_AVAIL_SHIFT                 16
+#define ENET_EIMR_TS_AVAIL_WIDTH                 1
+#define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_AVAIL_SHIFT))&ENET_EIMR_TS_AVAIL_MASK)
+#define ENET_EIMR_WAKEUP_MASK                    0x20000u
+#define ENET_EIMR_WAKEUP_SHIFT                   17
+#define ENET_EIMR_WAKEUP_WIDTH                   1
+#define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_WAKEUP_SHIFT))&ENET_EIMR_WAKEUP_MASK)
+#define ENET_EIMR_PLR_MASK                       0x40000u
+#define ENET_EIMR_PLR_SHIFT                      18
+#define ENET_EIMR_PLR_WIDTH                      1
+#define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_PLR_SHIFT))&ENET_EIMR_PLR_MASK)
+#define ENET_EIMR_UN_MASK                        0x80000u
+#define ENET_EIMR_UN_SHIFT                       19
+#define ENET_EIMR_UN_WIDTH                       1
+#define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_UN_SHIFT))&ENET_EIMR_UN_MASK)
+#define ENET_EIMR_RL_MASK                        0x100000u
+#define ENET_EIMR_RL_SHIFT                       20
+#define ENET_EIMR_RL_WIDTH                       1
+#define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RL_SHIFT))&ENET_EIMR_RL_MASK)
+#define ENET_EIMR_LC_MASK                        0x200000u
+#define ENET_EIMR_LC_SHIFT                       21
+#define ENET_EIMR_LC_WIDTH                       1
+#define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_LC_SHIFT))&ENET_EIMR_LC_MASK)
+#define ENET_EIMR_EBERR_MASK                     0x400000u
+#define ENET_EIMR_EBERR_SHIFT                    22
+#define ENET_EIMR_EBERR_WIDTH                    1
+#define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_EBERR_SHIFT))&ENET_EIMR_EBERR_MASK)
+#define ENET_EIMR_MII_MASK                       0x800000u
+#define ENET_EIMR_MII_SHIFT                      23
+#define ENET_EIMR_MII_WIDTH                      1
+#define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_MII_SHIFT))&ENET_EIMR_MII_MASK)
+#define ENET_EIMR_RXB_MASK                       0x1000000u
+#define ENET_EIMR_RXB_SHIFT                      24
+#define ENET_EIMR_RXB_WIDTH                      1
+#define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXB_SHIFT))&ENET_EIMR_RXB_MASK)
+#define ENET_EIMR_RXF_MASK                       0x2000000u
+#define ENET_EIMR_RXF_SHIFT                      25
+#define ENET_EIMR_RXF_WIDTH                      1
+#define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXF_SHIFT))&ENET_EIMR_RXF_MASK)
+#define ENET_EIMR_TXB_MASK                       0x4000000u
+#define ENET_EIMR_TXB_SHIFT                      26
+#define ENET_EIMR_TXB_WIDTH                      1
+#define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXB_SHIFT))&ENET_EIMR_TXB_MASK)
+#define ENET_EIMR_TXF_MASK                       0x8000000u
+#define ENET_EIMR_TXF_SHIFT                      27
+#define ENET_EIMR_TXF_WIDTH                      1
+#define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXF_SHIFT))&ENET_EIMR_TXF_MASK)
+#define ENET_EIMR_GRA_MASK                       0x10000000u
+#define ENET_EIMR_GRA_SHIFT                      28
+#define ENET_EIMR_GRA_WIDTH                      1
+#define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_GRA_SHIFT))&ENET_EIMR_GRA_MASK)
+#define ENET_EIMR_BABT_MASK                      0x20000000u
+#define ENET_EIMR_BABT_SHIFT                     29
+#define ENET_EIMR_BABT_WIDTH                     1
+#define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABT_SHIFT))&ENET_EIMR_BABT_MASK)
+#define ENET_EIMR_BABR_MASK                      0x40000000u
+#define ENET_EIMR_BABR_SHIFT                     30
+#define ENET_EIMR_BABR_WIDTH                     1
+#define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABR_SHIFT))&ENET_EIMR_BABR_MASK)
+/* RDAR Bit Fields */
+#define ENET_RDAR_RDAR_MASK                      0x1000000u
+#define ENET_RDAR_RDAR_SHIFT                     24
+#define ENET_RDAR_RDAR_WIDTH                     1
+#define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RDAR_RDAR_SHIFT))&ENET_RDAR_RDAR_MASK)
+/* TDAR Bit Fields */
+#define ENET_TDAR_TDAR_MASK                      0x1000000u
+#define ENET_TDAR_TDAR_SHIFT                     24
+#define ENET_TDAR_TDAR_WIDTH                     1
+#define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TDAR_TDAR_SHIFT))&ENET_TDAR_TDAR_MASK)
+/* ECR Bit Fields */
+#define ENET_ECR_RESET_MASK                      0x1u
+#define ENET_ECR_RESET_SHIFT                     0
+#define ENET_ECR_RESET_WIDTH                     1
+#define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_RESET_SHIFT))&ENET_ECR_RESET_MASK)
+#define ENET_ECR_ETHEREN_MASK                    0x2u
+#define ENET_ECR_ETHEREN_SHIFT                   1
+#define ENET_ECR_ETHEREN_WIDTH                   1
+#define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ECR_ETHEREN_SHIFT))&ENET_ECR_ETHEREN_MASK)
+#define ENET_ECR_MAGICEN_MASK                    0x4u
+#define ENET_ECR_MAGICEN_SHIFT                   2
+#define ENET_ECR_MAGICEN_WIDTH                   1
+#define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ECR_MAGICEN_SHIFT))&ENET_ECR_MAGICEN_MASK)
+#define ENET_ECR_SLEEP_MASK                      0x8u
+#define ENET_ECR_SLEEP_SHIFT                     3
+#define ENET_ECR_SLEEP_WIDTH                     1
+#define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_SLEEP_SHIFT))&ENET_ECR_SLEEP_MASK)
+#define ENET_ECR_EN1588_MASK                     0x10u
+#define ENET_ECR_EN1588_SHIFT                    4
+#define ENET_ECR_EN1588_WIDTH                    1
+#define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ECR_EN1588_SHIFT))&ENET_ECR_EN1588_MASK)
+#define ENET_ECR_DBGEN_MASK                      0x40u
+#define ENET_ECR_DBGEN_SHIFT                     6
+#define ENET_ECR_DBGEN_WIDTH                     1
+#define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBGEN_SHIFT))&ENET_ECR_DBGEN_MASK)
+#define ENET_ECR_STOPEN_MASK                     0x80u
+#define ENET_ECR_STOPEN_SHIFT                    7
+#define ENET_ECR_STOPEN_WIDTH                    1
+#define ENET_ECR_STOPEN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ECR_STOPEN_SHIFT))&ENET_ECR_STOPEN_MASK)
+#define ENET_ECR_DBSWP_MASK                      0x100u
+#define ENET_ECR_DBSWP_SHIFT                     8
+#define ENET_ECR_DBSWP_WIDTH                     1
+#define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBSWP_SHIFT))&ENET_ECR_DBSWP_MASK)
+/* MMFR Bit Fields */
+#define ENET_MMFR_DATA_MASK                      0xFFFFu
+#define ENET_MMFR_DATA_SHIFT                     0
+#define ENET_MMFR_DATA_WIDTH                     16
+#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK                        0x30000u
+#define ENET_MMFR_TA_SHIFT                       16
+#define ENET_MMFR_TA_WIDTH                       2
+#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK                        0x7C0000u
+#define ENET_MMFR_RA_SHIFT                       18
+#define ENET_MMFR_RA_WIDTH                       5
+#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK                        0xF800000u
+#define ENET_MMFR_PA_SHIFT                       23
+#define ENET_MMFR_PA_WIDTH                       5
+#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK                        0x30000000u
+#define ENET_MMFR_OP_SHIFT                       28
+#define ENET_MMFR_OP_WIDTH                       2
+#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK                        0xC0000000u
+#define ENET_MMFR_ST_SHIFT                       30
+#define ENET_MMFR_ST_WIDTH                       2
+#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
+/* MSCR Bit Fields */
+#define ENET_MSCR_MII_SPEED_MASK                 0x7Eu
+#define ENET_MSCR_MII_SPEED_SHIFT                1
+#define ENET_MSCR_MII_SPEED_WIDTH                6
+#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE_MASK                   0x80u
+#define ENET_MSCR_DIS_PRE_SHIFT                  7
+#define ENET_MSCR_DIS_PRE_WIDTH                  1
+#define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_DIS_PRE_SHIFT))&ENET_MSCR_DIS_PRE_MASK)
+#define ENET_MSCR_HOLDTIME_MASK                  0x700u
+#define ENET_MSCR_HOLDTIME_SHIFT                 8
+#define ENET_MSCR_HOLDTIME_WIDTH                 3
+#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
+/* MIBC Bit Fields */
+#define ENET_MIBC_MIB_CLEAR_MASK                 0x20000000u
+#define ENET_MIBC_MIB_CLEAR_SHIFT                29
+#define ENET_MIBC_MIB_CLEAR_WIDTH                1
+#define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_CLEAR_SHIFT))&ENET_MIBC_MIB_CLEAR_MASK)
+#define ENET_MIBC_MIB_IDLE_MASK                  0x40000000u
+#define ENET_MIBC_MIB_IDLE_SHIFT                 30
+#define ENET_MIBC_MIB_IDLE_WIDTH                 1
+#define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_IDLE_SHIFT))&ENET_MIBC_MIB_IDLE_MASK)
+#define ENET_MIBC_MIB_DIS_MASK                   0x80000000u
+#define ENET_MIBC_MIB_DIS_SHIFT                  31
+#define ENET_MIBC_MIB_DIS_WIDTH                  1
+#define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_DIS_SHIFT))&ENET_MIBC_MIB_DIS_MASK)
+/* RCR Bit Fields */
+#define ENET_RCR_LOOP_MASK                       0x1u
+#define ENET_RCR_LOOP_SHIFT                      0
+#define ENET_RCR_LOOP_WIDTH                      1
+#define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_LOOP_SHIFT))&ENET_RCR_LOOP_MASK)
+#define ENET_RCR_DRT_MASK                        0x2u
+#define ENET_RCR_DRT_SHIFT                       1
+#define ENET_RCR_DRT_WIDTH                       1
+#define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_DRT_SHIFT))&ENET_RCR_DRT_MASK)
+#define ENET_RCR_MII_MODE_MASK                   0x4u
+#define ENET_RCR_MII_MODE_SHIFT                  2
+#define ENET_RCR_MII_MODE_WIDTH                  1
+#define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MII_MODE_SHIFT))&ENET_RCR_MII_MODE_MASK)
+#define ENET_RCR_PROM_MASK                       0x8u
+#define ENET_RCR_PROM_SHIFT                      3
+#define ENET_RCR_PROM_WIDTH                      1
+#define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PROM_SHIFT))&ENET_RCR_PROM_MASK)
+#define ENET_RCR_BC_REJ_MASK                     0x10u
+#define ENET_RCR_BC_REJ_SHIFT                    4
+#define ENET_RCR_BC_REJ_WIDTH                    1
+#define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_BC_REJ_SHIFT))&ENET_RCR_BC_REJ_MASK)
+#define ENET_RCR_FCE_MASK                        0x20u
+#define ENET_RCR_FCE_SHIFT                       5
+#define ENET_RCR_FCE_WIDTH                       1
+#define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_FCE_SHIFT))&ENET_RCR_FCE_MASK)
+#define ENET_RCR_RMII_MODE_MASK                  0x100u
+#define ENET_RCR_RMII_MODE_SHIFT                 8
+#define ENET_RCR_RMII_MODE_WIDTH                 1
+#define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_MODE_SHIFT))&ENET_RCR_RMII_MODE_MASK)
+#define ENET_RCR_RMII_10T_MASK                   0x200u
+#define ENET_RCR_RMII_10T_SHIFT                  9
+#define ENET_RCR_RMII_10T_WIDTH                  1
+#define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_10T_SHIFT))&ENET_RCR_RMII_10T_MASK)
+#define ENET_RCR_PADEN_MASK                      0x1000u
+#define ENET_RCR_PADEN_SHIFT                     12
+#define ENET_RCR_PADEN_WIDTH                     1
+#define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PADEN_SHIFT))&ENET_RCR_PADEN_MASK)
+#define ENET_RCR_PAUFWD_MASK                     0x2000u
+#define ENET_RCR_PAUFWD_SHIFT                    13
+#define ENET_RCR_PAUFWD_WIDTH                    1
+#define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PAUFWD_SHIFT))&ENET_RCR_PAUFWD_MASK)
+#define ENET_RCR_CRCFWD_MASK                     0x4000u
+#define ENET_RCR_CRCFWD_SHIFT                    14
+#define ENET_RCR_CRCFWD_WIDTH                    1
+#define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CRCFWD_SHIFT))&ENET_RCR_CRCFWD_MASK)
+#define ENET_RCR_CFEN_MASK                       0x8000u
+#define ENET_RCR_CFEN_SHIFT                      15
+#define ENET_RCR_CFEN_WIDTH                      1
+#define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CFEN_SHIFT))&ENET_RCR_CFEN_MASK)
+#define ENET_RCR_MAX_FL_MASK                     0x3FFF0000u
+#define ENET_RCR_MAX_FL_SHIFT                    16
+#define ENET_RCR_MAX_FL_WIDTH                    14
+#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC_MASK                        0x40000000u
+#define ENET_RCR_NLC_SHIFT                       30
+#define ENET_RCR_NLC_WIDTH                       1
+#define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_NLC_SHIFT))&ENET_RCR_NLC_MASK)
+#define ENET_RCR_GRS_MASK                        0x80000000u
+#define ENET_RCR_GRS_SHIFT                       31
+#define ENET_RCR_GRS_WIDTH                       1
+#define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_GRS_SHIFT))&ENET_RCR_GRS_MASK)
+/* TCR Bit Fields */
+#define ENET_TCR_GTS_MASK                        0x1u
+#define ENET_TCR_GTS_SHIFT                       0
+#define ENET_TCR_GTS_WIDTH                       1
+#define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_TCR_GTS_SHIFT))&ENET_TCR_GTS_MASK)
+#define ENET_TCR_FDEN_MASK                       0x4u
+#define ENET_TCR_FDEN_SHIFT                      2
+#define ENET_TCR_FDEN_WIDTH                      1
+#define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCR_FDEN_SHIFT))&ENET_TCR_FDEN_MASK)
+#define ENET_TCR_TFC_PAUSE_MASK                  0x8u
+#define ENET_TCR_TFC_PAUSE_SHIFT                 3
+#define ENET_TCR_TFC_PAUSE_WIDTH                 1
+#define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_TCR_TFC_PAUSE_SHIFT))&ENET_TCR_TFC_PAUSE_MASK)
+#define ENET_TCR_RFC_PAUSE_MASK                  0x10u
+#define ENET_TCR_RFC_PAUSE_SHIFT                 4
+#define ENET_TCR_RFC_PAUSE_WIDTH                 1
+#define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_TCR_RFC_PAUSE_SHIFT))&ENET_TCR_RFC_PAUSE_MASK)
+#define ENET_TCR_ADDSEL_MASK                     0xE0u
+#define ENET_TCR_ADDSEL_SHIFT                    5
+#define ENET_TCR_ADDSEL_WIDTH                    3
+#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS_MASK                     0x100u
+#define ENET_TCR_ADDINS_SHIFT                    8
+#define ENET_TCR_ADDINS_WIDTH                    1
+#define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDINS_SHIFT))&ENET_TCR_ADDINS_MASK)
+#define ENET_TCR_CRCFWD_MASK                     0x200u
+#define ENET_TCR_CRCFWD_SHIFT                    9
+#define ENET_TCR_CRCFWD_WIDTH                    1
+#define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_CRCFWD_SHIFT))&ENET_TCR_CRCFWD_MASK)
+/* PALR Bit Fields */
+#define ENET_PALR_PADDR1_MASK                    0xFFFFFFFFu
+#define ENET_PALR_PADDR1_SHIFT                   0
+#define ENET_PALR_PADDR1_WIDTH                   32
+#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
+/* PAUR Bit Fields */
+#define ENET_PAUR_TYPE_MASK                      0xFFFFu
+#define ENET_PAUR_TYPE_SHIFT                     0
+#define ENET_PAUR_TYPE_WIDTH                     16
+#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK                    0xFFFF0000u
+#define ENET_PAUR_PADDR2_SHIFT                   16
+#define ENET_PAUR_PADDR2_WIDTH                   16
+#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
+/* OPD Bit Fields */
+#define ENET_OPD_PAUSE_DUR_MASK                  0xFFFFu
+#define ENET_OPD_PAUSE_DUR_SHIFT                 0
+#define ENET_OPD_PAUSE_DUR_WIDTH                 16
+#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK                     0xFFFF0000u
+#define ENET_OPD_OPCODE_SHIFT                    16
+#define ENET_OPD_OPCODE_WIDTH                    16
+#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
+/* IAUR Bit Fields */
+#define ENET_IAUR_IADDR1_MASK                    0xFFFFFFFFu
+#define ENET_IAUR_IADDR1_SHIFT                   0
+#define ENET_IAUR_IADDR1_WIDTH                   32
+#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
+/* IALR Bit Fields */
+#define ENET_IALR_IADDR2_MASK                    0xFFFFFFFFu
+#define ENET_IALR_IADDR2_SHIFT                   0
+#define ENET_IALR_IADDR2_WIDTH                   32
+#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
+/* GAUR Bit Fields */
+#define ENET_GAUR_GADDR1_MASK                    0xFFFFFFFFu
+#define ENET_GAUR_GADDR1_SHIFT                   0
+#define ENET_GAUR_GADDR1_WIDTH                   32
+#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
+/* GALR Bit Fields */
+#define ENET_GALR_GADDR2_MASK                    0xFFFFFFFFu
+#define ENET_GALR_GADDR2_SHIFT                   0
+#define ENET_GALR_GADDR2_WIDTH                   32
+#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
+/* TFWR Bit Fields */
+#define ENET_TFWR_TFWR_MASK                      0x3Fu
+#define ENET_TFWR_TFWR_SHIFT                     0
+#define ENET_TFWR_TFWR_WIDTH                     6
+#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD_MASK                    0x100u
+#define ENET_TFWR_STRFWD_SHIFT                   8
+#define ENET_TFWR_STRFWD_WIDTH                   1
+#define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_STRFWD_SHIFT))&ENET_TFWR_STRFWD_MASK)
+/* RDSR Bit Fields */
+#define ENET_RDSR_R_DES_START_MASK               0xFFFFFFF8u
+#define ENET_RDSR_R_DES_START_SHIFT              3
+#define ENET_RDSR_R_DES_START_WIDTH              29
+#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
+/* TDSR Bit Fields */
+#define ENET_TDSR_X_DES_START_MASK               0xFFFFFFF8u
+#define ENET_TDSR_X_DES_START_SHIFT              3
+#define ENET_TDSR_X_DES_START_WIDTH              29
+#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
+/* MRBR Bit Fields */
+#define ENET_MRBR_R_BUF_SIZE_MASK                0x3FF0u
+#define ENET_MRBR_R_BUF_SIZE_SHIFT               4
+#define ENET_MRBR_R_BUF_SIZE_WIDTH               10
+#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
+/* RSFL Bit Fields */
+#define ENET_RSFL_RX_SECTION_FULL_MASK           0xFFu
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT          0
+#define ENET_RSFL_RX_SECTION_FULL_WIDTH          8
+#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
+/* RSEM Bit Fields */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         0
+#define ENET_RSEM_RX_SECTION_EMPTY_WIDTH         8
+#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK        0x1F0000u
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       16
+#define ENET_RSEM_STAT_SECTION_EMPTY_WIDTH       5
+#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+/* RAEM Bit Fields */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          0
+#define ENET_RAEM_RX_ALMOST_EMPTY_WIDTH          8
+#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+/* RAFL Bit Fields */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK            0xFFu
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           0
+#define ENET_RAFL_RX_ALMOST_FULL_WIDTH           8
+#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
+/* TSEM Bit Fields */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         0
+#define ENET_TSEM_TX_SECTION_EMPTY_WIDTH         8
+#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
+/* TAEM Bit Fields */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          0
+#define ENET_TAEM_TX_ALMOST_EMPTY_WIDTH          8
+#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+/* TAFL Bit Fields */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK            0xFFu
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           0
+#define ENET_TAFL_TX_ALMOST_FULL_WIDTH           8
+#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
+/* TIPG Bit Fields */
+#define ENET_TIPG_IPG_MASK                       0x1Fu
+#define ENET_TIPG_IPG_SHIFT                      0
+#define ENET_TIPG_IPG_WIDTH                      5
+#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
+/* FTRL Bit Fields */
+#define ENET_FTRL_TRUNC_FL_MASK                  0x3FFFu
+#define ENET_FTRL_TRUNC_FL_SHIFT                 0
+#define ENET_FTRL_TRUNC_FL_WIDTH                 14
+#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
+/* TACC Bit Fields */
+#define ENET_TACC_SHIFT16_MASK                   0x1u
+#define ENET_TACC_SHIFT16_SHIFT                  0
+#define ENET_TACC_SHIFT16_WIDTH                  1
+#define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_TACC_SHIFT16_SHIFT))&ENET_TACC_SHIFT16_MASK)
+#define ENET_TACC_IPCHK_MASK                     0x8u
+#define ENET_TACC_IPCHK_SHIFT                    3
+#define ENET_TACC_IPCHK_WIDTH                    1
+#define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TACC_IPCHK_SHIFT))&ENET_TACC_IPCHK_MASK)
+#define ENET_TACC_PROCHK_MASK                    0x10u
+#define ENET_TACC_PROCHK_SHIFT                   4
+#define ENET_TACC_PROCHK_WIDTH                   1
+#define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_TACC_PROCHK_SHIFT))&ENET_TACC_PROCHK_MASK)
+/* RACC Bit Fields */
+#define ENET_RACC_PADREM_MASK                    0x1u
+#define ENET_RACC_PADREM_SHIFT                   0
+#define ENET_RACC_PADREM_WIDTH                   1
+#define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PADREM_SHIFT))&ENET_RACC_PADREM_MASK)
+#define ENET_RACC_IPDIS_MASK                     0x2u
+#define ENET_RACC_IPDIS_SHIFT                    1
+#define ENET_RACC_IPDIS_WIDTH                    1
+#define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RACC_IPDIS_SHIFT))&ENET_RACC_IPDIS_MASK)
+#define ENET_RACC_PRODIS_MASK                    0x4u
+#define ENET_RACC_PRODIS_SHIFT                   2
+#define ENET_RACC_PRODIS_WIDTH                   1
+#define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PRODIS_SHIFT))&ENET_RACC_PRODIS_MASK)
+#define ENET_RACC_LINEDIS_MASK                   0x40u
+#define ENET_RACC_LINEDIS_SHIFT                  6
+#define ENET_RACC_LINEDIS_WIDTH                  1
+#define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RACC_LINEDIS_SHIFT))&ENET_RACC_LINEDIS_MASK)
+#define ENET_RACC_SHIFT16_MASK                   0x80u
+#define ENET_RACC_SHIFT16_SHIFT                  7
+#define ENET_RACC_SHIFT16_WIDTH                  1
+#define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RACC_SHIFT16_SHIFT))&ENET_RACC_SHIFT16_MASK)
+/* RMON_T_PACKETS Bit Fields */
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK          0xFFFFu
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         0
+#define ENET_RMON_T_PACKETS_TXPKTS_WIDTH         16
+#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
+/* RMON_T_BC_PKT Bit Fields */
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           0xFFFFu
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          0
+#define ENET_RMON_T_BC_PKT_TXPKTS_WIDTH          16
+#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+/* RMON_T_MC_PKT Bit Fields */
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           0xFFFFu
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          0
+#define ENET_RMON_T_MC_PKT_TXPKTS_WIDTH          16
+#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+/* RMON_T_CRC_ALIGN Bit Fields */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       0
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_WIDTH       16
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+/* RMON_T_UNDERSIZE Bit Fields */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       0
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_WIDTH       16
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+/* RMON_T_OVERSIZE Bit Fields */
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         0xFFFFu
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        0
+#define ENET_RMON_T_OVERSIZE_TXPKTS_WIDTH        16
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+/* RMON_T_FRAG Bit Fields */
+#define ENET_RMON_T_FRAG_TXPKTS_MASK             0xFFFFu
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            0
+#define ENET_RMON_T_FRAG_TXPKTS_WIDTH            16
+#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
+/* RMON_T_JAB Bit Fields */
+#define ENET_RMON_T_JAB_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT             0
+#define ENET_RMON_T_JAB_TXPKTS_WIDTH             16
+#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
+/* RMON_T_COL Bit Fields */
+#define ENET_RMON_T_COL_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_COL_TXPKTS_SHIFT             0
+#define ENET_RMON_T_COL_TXPKTS_WIDTH             16
+#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
+/* RMON_T_P64 Bit Fields */
+#define ENET_RMON_T_P64_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_P64_TXPKTS_SHIFT             0
+#define ENET_RMON_T_P64_TXPKTS_WIDTH             16
+#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
+/* RMON_T_P65TO127 Bit Fields */
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK         0xFFFFu
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        0
+#define ENET_RMON_T_P65TO127_TXPKTS_WIDTH        16
+#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
+/* RMON_T_P128TO255 Bit Fields */
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P128TO255_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
+/* RMON_T_P256TO511 Bit Fields */
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P256TO511_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
+/* RMON_T_P512TO1023 Bit Fields */
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       0xFFFFu
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      0
+#define ENET_RMON_T_P512TO1023_TXPKTS_WIDTH      16
+#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+/* RMON_T_P1024TO2047 Bit Fields */
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      0xFFFFu
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     0
+#define ENET_RMON_T_P1024TO2047_TXPKTS_WIDTH     16
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+/* RMON_T_P_GTE2048 Bit Fields */
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P_GTE2048_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+/* RMON_T_OCTETS Bit Fields */
+#define ENET_RMON_T_OCTETS_TXOCTS_MASK           0xFFFFFFFFu
+#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          0
+#define ENET_RMON_T_OCTETS_TXOCTS_WIDTH          32
+#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
+/* IEEE_T_FRAME_OK Bit Fields */
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          0xFFFFu
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         0
+#define ENET_IEEE_T_FRAME_OK_COUNT_WIDTH         16
+#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+/* IEEE_T_1COL Bit Fields */
+#define ENET_IEEE_T_1COL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_1COL_COUNT_SHIFT             0
+#define ENET_IEEE_T_1COL_COUNT_WIDTH             16
+#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
+/* IEEE_T_MCOL Bit Fields */
+#define ENET_IEEE_T_MCOL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT             0
+#define ENET_IEEE_T_MCOL_COUNT_WIDTH             16
+#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
+/* IEEE_T_DEF Bit Fields */
+#define ENET_IEEE_T_DEF_COUNT_MASK               0xFFFFu
+#define ENET_IEEE_T_DEF_COUNT_SHIFT              0
+#define ENET_IEEE_T_DEF_COUNT_WIDTH              16
+#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
+/* IEEE_T_LCOL Bit Fields */
+#define ENET_IEEE_T_LCOL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT             0
+#define ENET_IEEE_T_LCOL_COUNT_WIDTH             16
+#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
+/* IEEE_T_EXCOL Bit Fields */
+#define ENET_IEEE_T_EXCOL_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            0
+#define ENET_IEEE_T_EXCOL_COUNT_WIDTH            16
+#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
+/* IEEE_T_MACERR Bit Fields */
+#define ENET_IEEE_T_MACERR_COUNT_MASK            0xFFFFu
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT           0
+#define ENET_IEEE_T_MACERR_COUNT_WIDTH           16
+#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
+/* IEEE_T_CSERR Bit Fields */
+#define ENET_IEEE_T_CSERR_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT            0
+#define ENET_IEEE_T_CSERR_COUNT_WIDTH            16
+#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
+/* IEEE_T_FDXFC Bit Fields */
+#define ENET_IEEE_T_FDXFC_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            0
+#define ENET_IEEE_T_FDXFC_COUNT_WIDTH            16
+#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
+/* IEEE_T_OCTETS_OK Bit Fields */
+#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        0
+#define ENET_IEEE_T_OCTETS_OK_COUNT_WIDTH        32
+#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+/* RMON_R_PACKETS Bit Fields */
+#define ENET_RMON_R_PACKETS_COUNT_MASK           0xFFFFu
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT          0
+#define ENET_RMON_R_PACKETS_COUNT_WIDTH          16
+#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
+/* RMON_R_BC_PKT Bit Fields */
+#define ENET_RMON_R_BC_PKT_COUNT_MASK            0xFFFFu
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           0
+#define ENET_RMON_R_BC_PKT_COUNT_WIDTH           16
+#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
+/* RMON_R_MC_PKT Bit Fields */
+#define ENET_RMON_R_MC_PKT_COUNT_MASK            0xFFFFu
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           0
+#define ENET_RMON_R_MC_PKT_COUNT_WIDTH           16
+#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
+/* RMON_R_CRC_ALIGN Bit Fields */
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        0
+#define ENET_RMON_R_CRC_ALIGN_COUNT_WIDTH        16
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+/* RMON_R_UNDERSIZE Bit Fields */
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        0
+#define ENET_RMON_R_UNDERSIZE_COUNT_WIDTH        16
+#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+/* RMON_R_OVERSIZE Bit Fields */
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK          0xFFFFu
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         0
+#define ENET_RMON_R_OVERSIZE_COUNT_WIDTH         16
+#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
+/* RMON_R_FRAG Bit Fields */
+#define ENET_RMON_R_FRAG_COUNT_MASK              0xFFFFu
+#define ENET_RMON_R_FRAG_COUNT_SHIFT             0
+#define ENET_RMON_R_FRAG_COUNT_WIDTH             16
+#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
+/* RMON_R_JAB Bit Fields */
+#define ENET_RMON_R_JAB_COUNT_MASK               0xFFFFu
+#define ENET_RMON_R_JAB_COUNT_SHIFT              0
+#define ENET_RMON_R_JAB_COUNT_WIDTH              16
+#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
+/* RMON_R_P64 Bit Fields */
+#define ENET_RMON_R_P64_COUNT_MASK               0xFFFFu
+#define ENET_RMON_R_P64_COUNT_SHIFT              0
+#define ENET_RMON_R_P64_COUNT_WIDTH              16
+#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
+/* RMON_R_P65TO127 Bit Fields */
+#define ENET_RMON_R_P65TO127_COUNT_MASK          0xFFFFu
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT         0
+#define ENET_RMON_R_P65TO127_COUNT_WIDTH         16
+#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
+/* RMON_R_P128TO255 Bit Fields */
+#define ENET_RMON_R_P128TO255_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT        0
+#define ENET_RMON_R_P128TO255_COUNT_WIDTH        16
+#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
+/* RMON_R_P256TO511 Bit Fields */
+#define ENET_RMON_R_P256TO511_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT        0
+#define ENET_RMON_R_P256TO511_COUNT_WIDTH        16
+#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
+/* RMON_R_P512TO1023 Bit Fields */
+#define ENET_RMON_R_P512TO1023_COUNT_MASK        0xFFFFu
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       0
+#define ENET_RMON_R_P512TO1023_COUNT_WIDTH       16
+#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
+/* RMON_R_P1024TO2047 Bit Fields */
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK       0xFFFFu
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      0
+#define ENET_RMON_R_P1024TO2047_COUNT_WIDTH      16
+#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
+/* RMON_R_P_GTE2048 Bit Fields */
+#define ENET_RMON_R_P_GTE2048_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        0
+#define ENET_RMON_R_P_GTE2048_COUNT_WIDTH        16
+#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
+/* RMON_R_OCTETS Bit Fields */
+#define ENET_RMON_R_OCTETS_COUNT_MASK            0xFFFFFFFFu
+#define ENET_RMON_R_OCTETS_COUNT_SHIFT           0
+#define ENET_RMON_R_OCTETS_COUNT_WIDTH           32
+#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
+/* IEEE_R_DROP Bit Fields */
+#define ENET_IEEE_R_DROP_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_R_DROP_COUNT_SHIFT             0
+#define ENET_IEEE_R_DROP_COUNT_WIDTH             16
+#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
+/* IEEE_R_FRAME_OK Bit Fields */
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          0xFFFFu
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         0
+#define ENET_IEEE_R_FRAME_OK_COUNT_WIDTH         16
+#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+/* IEEE_R_CRC Bit Fields */
+#define ENET_IEEE_R_CRC_COUNT_MASK               0xFFFFu
+#define ENET_IEEE_R_CRC_COUNT_SHIFT              0
+#define ENET_IEEE_R_CRC_COUNT_WIDTH              16
+#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
+/* IEEE_R_ALIGN Bit Fields */
+#define ENET_IEEE_R_ALIGN_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            0
+#define ENET_IEEE_R_ALIGN_COUNT_WIDTH            16
+#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
+/* IEEE_R_MACERR Bit Fields */
+#define ENET_IEEE_R_MACERR_COUNT_MASK            0xFFFFu
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT           0
+#define ENET_IEEE_R_MACERR_COUNT_WIDTH           16
+#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
+/* IEEE_R_FDXFC Bit Fields */
+#define ENET_IEEE_R_FDXFC_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            0
+#define ENET_IEEE_R_FDXFC_COUNT_WIDTH            16
+#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
+/* IEEE_R_OCTETS_OK Bit Fields */
+#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        0
+#define ENET_IEEE_R_OCTETS_OK_COUNT_WIDTH        32
+#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+/* ATCR Bit Fields */
+#define ENET_ATCR_EN_MASK                        0x1u
+#define ENET_ATCR_EN_SHIFT                       0
+#define ENET_ATCR_EN_WIDTH                       1
+#define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_EN_SHIFT))&ENET_ATCR_EN_MASK)
+#define ENET_ATCR_OFFEN_MASK                     0x4u
+#define ENET_ATCR_OFFEN_SHIFT                    2
+#define ENET_ATCR_OFFEN_WIDTH                    1
+#define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFEN_SHIFT))&ENET_ATCR_OFFEN_MASK)
+#define ENET_ATCR_OFFRST_MASK                    0x8u
+#define ENET_ATCR_OFFRST_SHIFT                   3
+#define ENET_ATCR_OFFRST_WIDTH                   1
+#define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFRST_SHIFT))&ENET_ATCR_OFFRST_MASK)
+#define ENET_ATCR_PEREN_MASK                     0x10u
+#define ENET_ATCR_PEREN_SHIFT                    4
+#define ENET_ATCR_PEREN_WIDTH                    1
+#define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PEREN_SHIFT))&ENET_ATCR_PEREN_MASK)
+#define ENET_ATCR_PINPER_MASK                    0x80u
+#define ENET_ATCR_PINPER_SHIFT                   7
+#define ENET_ATCR_PINPER_WIDTH                   1
+#define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PINPER_SHIFT))&ENET_ATCR_PINPER_MASK)
+#define ENET_ATCR_RESTART_MASK                   0x200u
+#define ENET_ATCR_RESTART_SHIFT                  9
+#define ENET_ATCR_RESTART_WIDTH                  1
+#define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_RESTART_SHIFT))&ENET_ATCR_RESTART_MASK)
+#define ENET_ATCR_CAPTURE_MASK                   0x800u
+#define ENET_ATCR_CAPTURE_SHIFT                  11
+#define ENET_ATCR_CAPTURE_WIDTH                  1
+#define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_CAPTURE_SHIFT))&ENET_ATCR_CAPTURE_MASK)
+#define ENET_ATCR_SLAVE_MASK                     0x2000u
+#define ENET_ATCR_SLAVE_SHIFT                    13
+#define ENET_ATCR_SLAVE_WIDTH                    1
+#define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_SLAVE_SHIFT))&ENET_ATCR_SLAVE_MASK)
+/* ATVR Bit Fields */
+#define ENET_ATVR_ATIME_MASK                     0xFFFFFFFFu
+#define ENET_ATVR_ATIME_SHIFT                    0
+#define ENET_ATVR_ATIME_WIDTH                    32
+#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
+/* ATOFF Bit Fields */
+#define ENET_ATOFF_OFFSET_MASK                   0xFFFFFFFFu
+#define ENET_ATOFF_OFFSET_SHIFT                  0
+#define ENET_ATOFF_OFFSET_WIDTH                  32
+#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
+/* ATPER Bit Fields */
+#define ENET_ATPER_PERIOD_MASK                   0xFFFFFFFFu
+#define ENET_ATPER_PERIOD_SHIFT                  0
+#define ENET_ATPER_PERIOD_WIDTH                  32
+#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
+/* ATCOR Bit Fields */
+#define ENET_ATCOR_COR_MASK                      0x7FFFFFFFu
+#define ENET_ATCOR_COR_SHIFT                     0
+#define ENET_ATCOR_COR_WIDTH                     31
+#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
+/* ATINC Bit Fields */
+#define ENET_ATINC_INC_MASK                      0x7Fu
+#define ENET_ATINC_INC_SHIFT                     0
+#define ENET_ATINC_INC_WIDTH                     7
+#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK                 0x7F00u
+#define ENET_ATINC_INC_CORR_SHIFT                8
+#define ENET_ATINC_INC_CORR_WIDTH                7
+#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
+/* ATSTMP Bit Fields */
+#define ENET_ATSTMP_TIMESTAMP_MASK               0xFFFFFFFFu
+#define ENET_ATSTMP_TIMESTAMP_SHIFT              0
+#define ENET_ATSTMP_TIMESTAMP_WIDTH              32
+#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
+/* TGSR Bit Fields */
+#define ENET_TGSR_TF0_MASK                       0x1u
+#define ENET_TGSR_TF0_SHIFT                      0
+#define ENET_TGSR_TF0_WIDTH                      1
+#define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF0_SHIFT))&ENET_TGSR_TF0_MASK)
+#define ENET_TGSR_TF1_MASK                       0x2u
+#define ENET_TGSR_TF1_SHIFT                      1
+#define ENET_TGSR_TF1_WIDTH                      1
+#define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF1_SHIFT))&ENET_TGSR_TF1_MASK)
+#define ENET_TGSR_TF2_MASK                       0x4u
+#define ENET_TGSR_TF2_SHIFT                      2
+#define ENET_TGSR_TF2_WIDTH                      1
+#define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF2_SHIFT))&ENET_TGSR_TF2_MASK)
+#define ENET_TGSR_TF3_MASK                       0x8u
+#define ENET_TGSR_TF3_SHIFT                      3
+#define ENET_TGSR_TF3_WIDTH                      1
+#define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF3_SHIFT))&ENET_TGSR_TF3_MASK)
+/* TCSR Bit Fields */
+#define ENET_TCSR_TDRE_MASK                      0x1u
+#define ENET_TCSR_TDRE_SHIFT                     0
+#define ENET_TCSR_TDRE_WIDTH                     1
+#define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TDRE_SHIFT))&ENET_TCSR_TDRE_MASK)
+#define ENET_TCSR_TMODE_MASK                     0x3Cu
+#define ENET_TCSR_TMODE_SHIFT                    2
+#define ENET_TCSR_TMODE_WIDTH                    4
+#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE_MASK                       0x40u
+#define ENET_TCSR_TIE_SHIFT                      6
+#define ENET_TCSR_TIE_WIDTH                      1
+#define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TIE_SHIFT))&ENET_TCSR_TIE_MASK)
+#define ENET_TCSR_TF_MASK                        0x80u
+#define ENET_TCSR_TF_SHIFT                       7
+#define ENET_TCSR_TF_WIDTH                       1
+#define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TF_SHIFT))&ENET_TCSR_TF_MASK)
+/* TCCR Bit Fields */
+#define ENET_TCCR_TCC_MASK                       0xFFFFFFFFu
+#define ENET_TCCR_TCC_SHIFT                      0
+#define ENET_TCCR_TCC_WIDTH                      32
+#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE                                (0x400C0000u)
+/** Peripheral ENET base pointer */
+#define ENET                                     ((ENET_Type *)ENET_BASE)
+#define ENET_BASE_PTR                            (ENET)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS                          { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS                           { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_Transmit_IRQS                       { ENET_Transmit_IRQn }
+#define ENET_Receive_IRQS                        { ENET_Receive_IRQn }
+#define ENET_Error_IRQS                          { ENET_Error_IRQn }
+#define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register instance definitions */
+/* ENET */
+#define ENET_EIR                                 ENET_EIR_REG(ENET)
+#define ENET_EIMR                                ENET_EIMR_REG(ENET)
+#define ENET_RDAR                                ENET_RDAR_REG(ENET)
+#define ENET_TDAR                                ENET_TDAR_REG(ENET)
+#define ENET_ECR                                 ENET_ECR_REG(ENET)
+#define ENET_MMFR                                ENET_MMFR_REG(ENET)
+#define ENET_MSCR                                ENET_MSCR_REG(ENET)
+#define ENET_MIBC                                ENET_MIBC_REG(ENET)
+#define ENET_RCR                                 ENET_RCR_REG(ENET)
+#define ENET_TCR                                 ENET_TCR_REG(ENET)
+#define ENET_PALR                                ENET_PALR_REG(ENET)
+#define ENET_PAUR                                ENET_PAUR_REG(ENET)
+#define ENET_OPD                                 ENET_OPD_REG(ENET)
+#define ENET_IAUR                                ENET_IAUR_REG(ENET)
+#define ENET_IALR                                ENET_IALR_REG(ENET)
+#define ENET_GAUR                                ENET_GAUR_REG(ENET)
+#define ENET_GALR                                ENET_GALR_REG(ENET)
+#define ENET_TFWR                                ENET_TFWR_REG(ENET)
+#define ENET_RDSR                                ENET_RDSR_REG(ENET)
+#define ENET_TDSR                                ENET_TDSR_REG(ENET)
+#define ENET_MRBR                                ENET_MRBR_REG(ENET)
+#define ENET_RSFL                                ENET_RSFL_REG(ENET)
+#define ENET_RSEM                                ENET_RSEM_REG(ENET)
+#define ENET_RAEM                                ENET_RAEM_REG(ENET)
+#define ENET_RAFL                                ENET_RAFL_REG(ENET)
+#define ENET_TSEM                                ENET_TSEM_REG(ENET)
+#define ENET_TAEM                                ENET_TAEM_REG(ENET)
+#define ENET_TAFL                                ENET_TAFL_REG(ENET)
+#define ENET_TIPG                                ENET_TIPG_REG(ENET)
+#define ENET_FTRL                                ENET_FTRL_REG(ENET)
+#define ENET_TACC                                ENET_TACC_REG(ENET)
+#define ENET_RACC                                ENET_RACC_REG(ENET)
+#define ENET_RMON_T_PACKETS                      ENET_RMON_T_PACKETS_REG(ENET)
+#define ENET_RMON_T_BC_PKT                       ENET_RMON_T_BC_PKT_REG(ENET)
+#define ENET_RMON_T_MC_PKT                       ENET_RMON_T_MC_PKT_REG(ENET)
+#define ENET_RMON_T_CRC_ALIGN                    ENET_RMON_T_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_T_UNDERSIZE                    ENET_RMON_T_UNDERSIZE_REG(ENET)
+#define ENET_RMON_T_OVERSIZE                     ENET_RMON_T_OVERSIZE_REG(ENET)
+#define ENET_RMON_T_FRAG                         ENET_RMON_T_FRAG_REG(ENET)
+#define ENET_RMON_T_JAB                          ENET_RMON_T_JAB_REG(ENET)
+#define ENET_RMON_T_COL                          ENET_RMON_T_COL_REG(ENET)
+#define ENET_RMON_T_P64                          ENET_RMON_T_P64_REG(ENET)
+#define ENET_RMON_T_P65TO127                     ENET_RMON_T_P65TO127_REG(ENET)
+#define ENET_RMON_T_P128TO255                    ENET_RMON_T_P128TO255_REG(ENET)
+#define ENET_RMON_T_P256TO511                    ENET_RMON_T_P256TO511_REG(ENET)
+#define ENET_RMON_T_P512TO1023                   ENET_RMON_T_P512TO1023_REG(ENET)
+#define ENET_RMON_T_P1024TO2047                  ENET_RMON_T_P1024TO2047_REG(ENET)
+#define ENET_RMON_T_P_GTE2048                    ENET_RMON_T_P_GTE2048_REG(ENET)
+#define ENET_RMON_T_OCTETS                       ENET_RMON_T_OCTETS_REG(ENET)
+#define ENET_IEEE_T_FRAME_OK                     ENET_IEEE_T_FRAME_OK_REG(ENET)
+#define ENET_IEEE_T_1COL                         ENET_IEEE_T_1COL_REG(ENET)
+#define ENET_IEEE_T_MCOL                         ENET_IEEE_T_MCOL_REG(ENET)
+#define ENET_IEEE_T_DEF                          ENET_IEEE_T_DEF_REG(ENET)
+#define ENET_IEEE_T_LCOL                         ENET_IEEE_T_LCOL_REG(ENET)
+#define ENET_IEEE_T_EXCOL                        ENET_IEEE_T_EXCOL_REG(ENET)
+#define ENET_IEEE_T_MACERR                       ENET_IEEE_T_MACERR_REG(ENET)
+#define ENET_IEEE_T_CSERR                        ENET_IEEE_T_CSERR_REG(ENET)
+#define ENET_IEEE_T_FDXFC                        ENET_IEEE_T_FDXFC_REG(ENET)
+#define ENET_IEEE_T_OCTETS_OK                    ENET_IEEE_T_OCTETS_OK_REG(ENET)
+#define ENET_RMON_R_PACKETS                      ENET_RMON_R_PACKETS_REG(ENET)
+#define ENET_RMON_R_BC_PKT                       ENET_RMON_R_BC_PKT_REG(ENET)
+#define ENET_RMON_R_MC_PKT                       ENET_RMON_R_MC_PKT_REG(ENET)
+#define ENET_RMON_R_CRC_ALIGN                    ENET_RMON_R_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_R_UNDERSIZE                    ENET_RMON_R_UNDERSIZE_REG(ENET)
+#define ENET_RMON_R_OVERSIZE                     ENET_RMON_R_OVERSIZE_REG(ENET)
+#define ENET_RMON_R_FRAG                         ENET_RMON_R_FRAG_REG(ENET)
+#define ENET_RMON_R_JAB                          ENET_RMON_R_JAB_REG(ENET)
+#define ENET_RMON_R_P64                          ENET_RMON_R_P64_REG(ENET)
+#define ENET_RMON_R_P65TO127                     ENET_RMON_R_P65TO127_REG(ENET)
+#define ENET_RMON_R_P128TO255                    ENET_RMON_R_P128TO255_REG(ENET)
+#define ENET_RMON_R_P256TO511                    ENET_RMON_R_P256TO511_REG(ENET)
+#define ENET_RMON_R_P512TO1023                   ENET_RMON_R_P512TO1023_REG(ENET)
+#define ENET_RMON_R_P1024TO2047                  ENET_RMON_R_P1024TO2047_REG(ENET)
+#define ENET_RMON_R_P_GTE2048                    ENET_RMON_R_P_GTE2048_REG(ENET)
+#define ENET_RMON_R_OCTETS                       ENET_RMON_R_OCTETS_REG(ENET)
+#define ENET_IEEE_R_DROP                         ENET_IEEE_R_DROP_REG(ENET)
+#define ENET_IEEE_R_FRAME_OK                     ENET_IEEE_R_FRAME_OK_REG(ENET)
+#define ENET_IEEE_R_CRC                          ENET_IEEE_R_CRC_REG(ENET)
+#define ENET_IEEE_R_ALIGN                        ENET_IEEE_R_ALIGN_REG(ENET)
+#define ENET_IEEE_R_MACERR                       ENET_IEEE_R_MACERR_REG(ENET)
+#define ENET_IEEE_R_FDXFC                        ENET_IEEE_R_FDXFC_REG(ENET)
+#define ENET_IEEE_R_OCTETS_OK                    ENET_IEEE_R_OCTETS_OK_REG(ENET)
+#define ENET_ATCR                                ENET_ATCR_REG(ENET)
+#define ENET_ATVR                                ENET_ATVR_REG(ENET)
+#define ENET_ATOFF                               ENET_ATOFF_REG(ENET)
+#define ENET_ATPER                               ENET_ATPER_REG(ENET)
+#define ENET_ATCOR                               ENET_ATCOR_REG(ENET)
+#define ENET_ATINC                               ENET_ATINC_REG(ENET)
+#define ENET_ATSTMP                              ENET_ATSTMP_REG(ENET)
+#define ENET_TGSR                                ENET_TGSR_REG(ENET)
+#define ENET_TCSR0                               ENET_TCSR_REG(ENET,0)
+#define ENET_TCCR0                               ENET_TCCR_REG(ENET,0)
+#define ENET_TCSR1                               ENET_TCSR_REG(ENET,1)
+#define ENET_TCCR1                               ENET_TCCR_REG(ENET,1)
+#define ENET_TCSR2                               ENET_TCSR_REG(ENET,2)
+#define ENET_TCCR2                               ENET_TCCR_REG(ENET,2)
+#define ENET_TCSR3                               ENET_TCSR_REG(ENET,3)
+#define ENET_TCCR3                               ENET_TCCR_REG(ENET,3)
+
+/* ENET - Register array accessors */
+#define ENET_TCSR(index)                         ENET_TCSR_REG(ENET,index)
+#define ENET_TCCR(index)                         ENET_TCCR_REG(ENET,index)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
+} EWM_Type, *EWM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register accessors */
+#define EWM_CTRL_REG(base)                       ((base)->CTRL)
+#define EWM_SERV_REG(base)                       ((base)->SERV)
+#define EWM_CMPL_REG(base)                       ((base)->CMPL)
+#define EWM_CMPH_REG(base)                       ((base)->CMPH)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK                      0x1u
+#define EWM_CTRL_EWMEN_SHIFT                     0
+#define EWM_CTRL_EWMEN_WIDTH                     1
+#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK                      0x2u
+#define EWM_CTRL_ASSIN_SHIFT                     1
+#define EWM_CTRL_ASSIN_WIDTH                     1
+#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK                       0x4u
+#define EWM_CTRL_INEN_SHIFT                      2
+#define EWM_CTRL_INEN_WIDTH                      1
+#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK                      0x8u
+#define EWM_CTRL_INTEN_SHIFT                     3
+#define EWM_CTRL_INTEN_WIDTH                     1
+#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK                    0xFFu
+#define EWM_SERV_SERVICE_SHIFT                   0
+#define EWM_SERV_SERVICE_WIDTH                   8
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK                   0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT                  0
+#define EWM_CMPL_COMPAREL_WIDTH                  8
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK                   0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT                  0
+#define EWM_CMPH_COMPAREH_WIDTH                  8
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE                                 (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM                                      ((EWM_Type *)EWM_BASE)
+#define EWM_BASE_PTR                             (EWM)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS                           { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS                            { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS                                 { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register instance definitions */
+/* EWM */
+#define EWM_CTRL                                 EWM_CTRL_REG(EWM)
+#define EWM_SERV                                 EWM_SERV_REG(EWM)
+#define EWM_CMPL                                 EWM_CMPL_REG(EWM)
+#define EWM_CMPH                                 EWM_CMPH_REG(EWM)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0xC */
+    __IO uint32_t CSAR;                              /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+    __IO uint32_t CSMR;                              /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+    __IO uint32_t CSCR;                              /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+  } CS[6];
+       uint8_t RESERVED_0[24];
+  __IO uint32_t CSPMCR;                            /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type, *FB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register accessors */
+#define FB_CSAR_REG(base,index)                  ((base)->CS[index].CSAR)
+#define FB_CSAR_COUNT                            6
+#define FB_CSMR_REG(base,index)                  ((base)->CS[index].CSMR)
+#define FB_CSMR_COUNT                            6
+#define FB_CSCR_REG(base,index)                  ((base)->CS[index].CSCR)
+#define FB_CSCR_COUNT                            6
+#define FB_CSPMCR_REG(base)                      ((base)->CSPMCR)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK                          0xFFFF0000u
+#define FB_CSAR_BA_SHIFT                         16
+#define FB_CSAR_BA_WIDTH                         16
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
+/* CSMR Bit Fields */
+#define FB_CSMR_V_MASK                           0x1u
+#define FB_CSMR_V_SHIFT                          0
+#define FB_CSMR_V_WIDTH                          1
+#define FB_CSMR_V(x)                             (((uint32_t)(((uint32_t)(x))<<FB_CSMR_V_SHIFT))&FB_CSMR_V_MASK)
+#define FB_CSMR_WP_MASK                          0x100u
+#define FB_CSMR_WP_SHIFT                         8
+#define FB_CSMR_WP_WIDTH                         1
+#define FB_CSMR_WP(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSMR_WP_SHIFT))&FB_CSMR_WP_MASK)
+#define FB_CSMR_BAM_MASK                         0xFFFF0000u
+#define FB_CSMR_BAM_SHIFT                        16
+#define FB_CSMR_BAM_WIDTH                        16
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
+/* CSCR Bit Fields */
+#define FB_CSCR_BSTW_MASK                        0x8u
+#define FB_CSCR_BSTW_SHIFT                       3
+#define FB_CSCR_BSTW_WIDTH                       1
+#define FB_CSCR_BSTW(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTW_SHIFT))&FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTR_MASK                        0x10u
+#define FB_CSCR_BSTR_SHIFT                       4
+#define FB_CSCR_BSTR_WIDTH                       1
+#define FB_CSCR_BSTR(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTR_SHIFT))&FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BEM_MASK                         0x20u
+#define FB_CSCR_BEM_SHIFT                        5
+#define FB_CSCR_BEM_WIDTH                        1
+#define FB_CSCR_BEM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BEM_SHIFT))&FB_CSCR_BEM_MASK)
+#define FB_CSCR_PS_MASK                          0xC0u
+#define FB_CSCR_PS_SHIFT                         6
+#define FB_CSCR_PS_WIDTH                         2
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK                          0x100u
+#define FB_CSCR_AA_SHIFT                         8
+#define FB_CSCR_AA_WIDTH                         1
+#define FB_CSCR_AA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_AA_SHIFT))&FB_CSCR_AA_MASK)
+#define FB_CSCR_BLS_MASK                         0x200u
+#define FB_CSCR_BLS_SHIFT                        9
+#define FB_CSCR_BLS_WIDTH                        1
+#define FB_CSCR_BLS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BLS_SHIFT))&FB_CSCR_BLS_MASK)
+#define FB_CSCR_WS_MASK                          0xFC00u
+#define FB_CSCR_WS_SHIFT                         10
+#define FB_CSCR_WS_WIDTH                         6
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        0x30000u
+#define FB_CSCR_WRAH_SHIFT                       16
+#define FB_CSCR_WRAH_WIDTH                       2
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        0xC0000u
+#define FB_CSCR_RDAH_SHIFT                       18
+#define FB_CSCR_RDAH_WIDTH                       2
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        0x300000u
+#define FB_CSCR_ASET_SHIFT                       20
+#define FB_CSCR_ASET_WIDTH                       2
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK                        0x400000u
+#define FB_CSCR_EXTS_SHIFT                       22
+#define FB_CSCR_EXTS_WIDTH                       1
+#define FB_CSCR_EXTS(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_EXTS_SHIFT))&FB_CSCR_EXTS_MASK)
+#define FB_CSCR_SWSEN_MASK                       0x800000u
+#define FB_CSCR_SWSEN_SHIFT                      23
+#define FB_CSCR_SWSEN_WIDTH                      1
+#define FB_CSCR_SWSEN(x)                         (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWSEN_SHIFT))&FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWS_MASK                         0xFC000000u
+#define FB_CSCR_SWS_SHIFT                        26
+#define FB_CSCR_SWS_WIDTH                        6
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
+/* CSPMCR Bit Fields */
+#define FB_CSPMCR_GROUP5_MASK                    0xF000u
+#define FB_CSPMCR_GROUP5_SHIFT                   12
+#define FB_CSPMCR_GROUP5_WIDTH                   4
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    0xF0000u
+#define FB_CSPMCR_GROUP4_SHIFT                   16
+#define FB_CSPMCR_GROUP4_WIDTH                   4
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    0xF00000u
+#define FB_CSPMCR_GROUP3_SHIFT                   20
+#define FB_CSPMCR_GROUP3_WIDTH                   4
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    0xF000000u
+#define FB_CSPMCR_GROUP2_SHIFT                   24
+#define FB_CSPMCR_GROUP2_WIDTH                   4
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    0xF0000000u
+#define FB_CSPMCR_GROUP1_SHIFT                   28
+#define FB_CSPMCR_GROUP1_WIDTH                   4
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE                                  (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB                                       ((FB_Type *)FB_BASE)
+#define FB_BASE_PTR                              (FB)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS                            { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS                             { FB }
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register instance definitions */
+/* FB */
+#define FB_CSAR0                                 FB_CSAR_REG(FB,0)
+#define FB_CSMR0                                 FB_CSMR_REG(FB,0)
+#define FB_CSCR0                                 FB_CSCR_REG(FB,0)
+#define FB_CSAR1                                 FB_CSAR_REG(FB,1)
+#define FB_CSMR1                                 FB_CSMR_REG(FB,1)
+#define FB_CSCR1                                 FB_CSCR_REG(FB,1)
+#define FB_CSAR2                                 FB_CSAR_REG(FB,2)
+#define FB_CSMR2                                 FB_CSMR_REG(FB,2)
+#define FB_CSCR2                                 FB_CSCR_REG(FB,2)
+#define FB_CSAR3                                 FB_CSAR_REG(FB,3)
+#define FB_CSMR3                                 FB_CSMR_REG(FB,3)
+#define FB_CSCR3                                 FB_CSCR_REG(FB,3)
+#define FB_CSAR4                                 FB_CSAR_REG(FB,4)
+#define FB_CSMR4                                 FB_CSMR_REG(FB,4)
+#define FB_CSCR4                                 FB_CSCR_REG(FB,4)
+#define FB_CSAR5                                 FB_CSAR_REG(FB,5)
+#define FB_CSMR5                                 FB_CSMR_REG(FB,5)
+#define FB_CSCR5                                 FB_CSCR_REG(FB,5)
+#define FB_CSPMCR                                FB_CSPMCR_REG(FB)
+
+/* FB - Register array accessors */
+#define FB_CSAR(index)                           FB_CSAR_REG(FB,index)
+#define FB_CSMR(index)                           FB_CSMR_REG(FB,index)
+#define FB_CSCR(index)                           FB_CSCR_REG(FB,index)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PFAPR;                             /**< Flash Access Protection Register, offset: 0x0 */
+  __IO uint32_t PFB0CR;                            /**< Flash Bank 0 Control Register, offset: 0x4 */
+  __IO uint32_t PFB1CR;                            /**< Flash Bank 1 Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[244];
+  __IO uint32_t TAGVDW0S[4];                       /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+  __IO uint32_t TAGVDW1S[4];                       /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
+  __IO uint32_t TAGVDW2S[4];                       /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+  __IO uint32_t TAGVDW3S[4];                       /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
+       uint8_t RESERVED_1[192];
+  struct {                                         /* offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_U;                            /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_L;                            /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
+  } SET[4][4];
+} FMC_Type, *FMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register accessors */
+#define FMC_PFAPR_REG(base)                      ((base)->PFAPR)
+#define FMC_PFB0CR_REG(base)                     ((base)->PFB0CR)
+#define FMC_PFB1CR_REG(base)                     ((base)->PFB1CR)
+#define FMC_TAGVDW0S_REG(base,index)             ((base)->TAGVDW0S[index])
+#define FMC_TAGVDW0S_COUNT                       4
+#define FMC_TAGVDW1S_REG(base,index)             ((base)->TAGVDW1S[index])
+#define FMC_TAGVDW1S_COUNT                       4
+#define FMC_TAGVDW2S_REG(base,index)             ((base)->TAGVDW2S[index])
+#define FMC_TAGVDW2S_COUNT                       4
+#define FMC_TAGVDW3S_REG(base,index)             ((base)->TAGVDW3S[index])
+#define FMC_TAGVDW3S_COUNT                       4
+#define FMC_DATA_U_REG(base,index,index2)        ((base)->SET[index][index2].DATA_U)
+#define FMC_DATA_U_COUNT                         4
+#define FMC_DATA_U_COUNT2                        4
+#define FMC_DATA_L_REG(base,index,index2)        ((base)->SET[index][index2].DATA_L)
+#define FMC_DATA_L_COUNT                         4
+#define FMC_DATA_L_COUNT2                        4
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK                      0x3u
+#define FMC_PFAPR_M0AP_SHIFT                     0
+#define FMC_PFAPR_M0AP_WIDTH                     2
+#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK                      0xCu
+#define FMC_PFAPR_M1AP_SHIFT                     2
+#define FMC_PFAPR_M1AP_WIDTH                     2
+#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK                      0x30u
+#define FMC_PFAPR_M2AP_SHIFT                     4
+#define FMC_PFAPR_M2AP_WIDTH                     2
+#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK                      0xC0u
+#define FMC_PFAPR_M3AP_SHIFT                     6
+#define FMC_PFAPR_M3AP_WIDTH                     2
+#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK                      0x300u
+#define FMC_PFAPR_M4AP_SHIFT                     8
+#define FMC_PFAPR_M4AP_WIDTH                     2
+#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK                      0xC00u
+#define FMC_PFAPR_M5AP_SHIFT                     10
+#define FMC_PFAPR_M5AP_WIDTH                     2
+#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK                      0x3000u
+#define FMC_PFAPR_M6AP_SHIFT                     12
+#define FMC_PFAPR_M6AP_WIDTH                     2
+#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK                      0xC000u
+#define FMC_PFAPR_M7AP_SHIFT                     14
+#define FMC_PFAPR_M7AP_WIDTH                     2
+#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK                     0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT                    16
+#define FMC_PFAPR_M0PFD_WIDTH                    1
+#define FMC_PFAPR_M0PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0PFD_SHIFT))&FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK                     0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT                    17
+#define FMC_PFAPR_M1PFD_WIDTH                    1
+#define FMC_PFAPR_M1PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1PFD_SHIFT))&FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK                     0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT                    18
+#define FMC_PFAPR_M2PFD_WIDTH                    1
+#define FMC_PFAPR_M2PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2PFD_SHIFT))&FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK                     0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT                    19
+#define FMC_PFAPR_M3PFD_WIDTH                    1
+#define FMC_PFAPR_M3PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3PFD_SHIFT))&FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M4PFD_MASK                     0x100000u
+#define FMC_PFAPR_M4PFD_SHIFT                    20
+#define FMC_PFAPR_M4PFD_WIDTH                    1
+#define FMC_PFAPR_M4PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4PFD_SHIFT))&FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M5PFD_MASK                     0x200000u
+#define FMC_PFAPR_M5PFD_SHIFT                    21
+#define FMC_PFAPR_M5PFD_WIDTH                    1
+#define FMC_PFAPR_M5PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5PFD_SHIFT))&FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M6PFD_MASK                     0x400000u
+#define FMC_PFAPR_M6PFD_SHIFT                    22
+#define FMC_PFAPR_M6PFD_WIDTH                    1
+#define FMC_PFAPR_M6PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6PFD_SHIFT))&FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M7PFD_MASK                     0x800000u
+#define FMC_PFAPR_M7PFD_SHIFT                    23
+#define FMC_PFAPR_M7PFD_WIDTH                    1
+#define FMC_PFAPR_M7PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7PFD_SHIFT))&FMC_PFAPR_M7PFD_MASK)
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK                   0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT                  0
+#define FMC_PFB0CR_B0SEBE_WIDTH                  1
+#define FMC_PFB0CR_B0SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0SEBE_SHIFT))&FMC_PFB0CR_B0SEBE_MASK)
+#define FMC_PFB0CR_B0IPE_MASK                    0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT                   1
+#define FMC_PFB0CR_B0IPE_WIDTH                   1
+#define FMC_PFB0CR_B0IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0IPE_SHIFT))&FMC_PFB0CR_B0IPE_MASK)
+#define FMC_PFB0CR_B0DPE_MASK                    0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT                   2
+#define FMC_PFB0CR_B0DPE_WIDTH                   1
+#define FMC_PFB0CR_B0DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DPE_SHIFT))&FMC_PFB0CR_B0DPE_MASK)
+#define FMC_PFB0CR_B0ICE_MASK                    0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT                   3
+#define FMC_PFB0CR_B0ICE_WIDTH                   1
+#define FMC_PFB0CR_B0ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0ICE_SHIFT))&FMC_PFB0CR_B0ICE_MASK)
+#define FMC_PFB0CR_B0DCE_MASK                    0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT                   4
+#define FMC_PFB0CR_B0DCE_WIDTH                   1
+#define FMC_PFB0CR_B0DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DCE_SHIFT))&FMC_PFB0CR_B0DCE_MASK)
+#define FMC_PFB0CR_CRC_MASK                      0xE0u
+#define FMC_PFB0CR_CRC_SHIFT                     5
+#define FMC_PFB0CR_CRC_WIDTH                     3
+#define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK                     0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT                    17
+#define FMC_PFB0CR_B0MW_WIDTH                    2
+#define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK                  0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT                 19
+#define FMC_PFB0CR_S_B_INV_WIDTH                 1
+#define FMC_PFB0CR_S_B_INV(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_S_B_INV_SHIFT))&FMC_PFB0CR_S_B_INV_MASK)
+#define FMC_PFB0CR_CINV_WAY_MASK                 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT                20
+#define FMC_PFB0CR_CINV_WAY_WIDTH                4
+#define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK                 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT                24
+#define FMC_PFB0CR_CLCK_WAY_WIDTH                4
+#define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK                   0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT                  28
+#define FMC_PFB0CR_B0RWSC_WIDTH                  4
+#define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* PFB1CR Bit Fields */
+#define FMC_PFB1CR_B1SEBE_MASK                   0x1u
+#define FMC_PFB1CR_B1SEBE_SHIFT                  0
+#define FMC_PFB1CR_B1SEBE_WIDTH                  1
+#define FMC_PFB1CR_B1SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1SEBE_SHIFT))&FMC_PFB1CR_B1SEBE_MASK)
+#define FMC_PFB1CR_B1IPE_MASK                    0x2u
+#define FMC_PFB1CR_B1IPE_SHIFT                   1
+#define FMC_PFB1CR_B1IPE_WIDTH                   1
+#define FMC_PFB1CR_B1IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1IPE_SHIFT))&FMC_PFB1CR_B1IPE_MASK)
+#define FMC_PFB1CR_B1DPE_MASK                    0x4u
+#define FMC_PFB1CR_B1DPE_SHIFT                   2
+#define FMC_PFB1CR_B1DPE_WIDTH                   1
+#define FMC_PFB1CR_B1DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DPE_SHIFT))&FMC_PFB1CR_B1DPE_MASK)
+#define FMC_PFB1CR_B1ICE_MASK                    0x8u
+#define FMC_PFB1CR_B1ICE_SHIFT                   3
+#define FMC_PFB1CR_B1ICE_WIDTH                   1
+#define FMC_PFB1CR_B1ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1ICE_SHIFT))&FMC_PFB1CR_B1ICE_MASK)
+#define FMC_PFB1CR_B1DCE_MASK                    0x10u
+#define FMC_PFB1CR_B1DCE_SHIFT                   4
+#define FMC_PFB1CR_B1DCE_WIDTH                   1
+#define FMC_PFB1CR_B1DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DCE_SHIFT))&FMC_PFB1CR_B1DCE_MASK)
+#define FMC_PFB1CR_B1MW_MASK                     0x60000u
+#define FMC_PFB1CR_B1MW_SHIFT                    17
+#define FMC_PFB1CR_B1MW_WIDTH                    2
+#define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK                   0xF0000000u
+#define FMC_PFB1CR_B1RWSC_SHIFT                  28
+#define FMC_PFB1CR_B1RWSC_WIDTH                  4
+#define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
+/* TAGVDW0S Bit Fields */
+#define FMC_TAGVDW0S_valid_MASK                  0x1u
+#define FMC_TAGVDW0S_valid_SHIFT                 0
+#define FMC_TAGVDW0S_valid_WIDTH                 1
+#define FMC_TAGVDW0S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_valid_SHIFT))&FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW0S_tag_SHIFT                   5
+#define FMC_TAGVDW0S_tag_WIDTH                   14
+#define FMC_TAGVDW0S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
+/* TAGVDW1S Bit Fields */
+#define FMC_TAGVDW1S_valid_MASK                  0x1u
+#define FMC_TAGVDW1S_valid_SHIFT                 0
+#define FMC_TAGVDW1S_valid_WIDTH                 1
+#define FMC_TAGVDW1S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_valid_SHIFT))&FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW1S_tag_SHIFT                   5
+#define FMC_TAGVDW1S_tag_WIDTH                   14
+#define FMC_TAGVDW1S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
+/* TAGVDW2S Bit Fields */
+#define FMC_TAGVDW2S_valid_MASK                  0x1u
+#define FMC_TAGVDW2S_valid_SHIFT                 0
+#define FMC_TAGVDW2S_valid_WIDTH                 1
+#define FMC_TAGVDW2S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_valid_SHIFT))&FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW2S_tag_SHIFT                   5
+#define FMC_TAGVDW2S_tag_WIDTH                   14
+#define FMC_TAGVDW2S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
+/* TAGVDW3S Bit Fields */
+#define FMC_TAGVDW3S_valid_MASK                  0x1u
+#define FMC_TAGVDW3S_valid_SHIFT                 0
+#define FMC_TAGVDW3S_valid_WIDTH                 1
+#define FMC_TAGVDW3S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_valid_SHIFT))&FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW3S_tag_SHIFT                   5
+#define FMC_TAGVDW3S_tag_WIDTH                   14
+#define FMC_TAGVDW3S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
+/* DATA_U Bit Fields */
+#define FMC_DATA_U_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_U_data_SHIFT                    0
+#define FMC_DATA_U_data_WIDTH                    32
+#define FMC_DATA_U_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
+/* DATA_L Bit Fields */
+#define FMC_DATA_L_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_L_data_SHIFT                    0
+#define FMC_DATA_L_data_WIDTH                    32
+#define FMC_DATA_L_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE                                 (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC                                      ((FMC_Type *)FMC_BASE)
+#define FMC_BASE_PTR                             (FMC)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS                           { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS                            { FMC }
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register instance definitions */
+/* FMC */
+#define FMC_PFAPR                                FMC_PFAPR_REG(FMC)
+#define FMC_PFB0CR                               FMC_PFB0CR_REG(FMC)
+#define FMC_PFB1CR                               FMC_PFB1CR_REG(FMC)
+#define FMC_TAGVDW0S0                            FMC_TAGVDW0S_REG(FMC,0)
+#define FMC_TAGVDW0S1                            FMC_TAGVDW0S_REG(FMC,1)
+#define FMC_TAGVDW0S2                            FMC_TAGVDW0S_REG(FMC,2)
+#define FMC_TAGVDW0S3                            FMC_TAGVDW0S_REG(FMC,3)
+#define FMC_TAGVDW1S0                            FMC_TAGVDW1S_REG(FMC,0)
+#define FMC_TAGVDW1S1                            FMC_TAGVDW1S_REG(FMC,1)
+#define FMC_TAGVDW1S2                            FMC_TAGVDW1S_REG(FMC,2)
+#define FMC_TAGVDW1S3                            FMC_TAGVDW1S_REG(FMC,3)
+#define FMC_TAGVDW2S0                            FMC_TAGVDW2S_REG(FMC,0)
+#define FMC_TAGVDW2S1                            FMC_TAGVDW2S_REG(FMC,1)
+#define FMC_TAGVDW2S2                            FMC_TAGVDW2S_REG(FMC,2)
+#define FMC_TAGVDW2S3                            FMC_TAGVDW2S_REG(FMC,3)
+#define FMC_TAGVDW3S0                            FMC_TAGVDW3S_REG(FMC,0)
+#define FMC_TAGVDW3S1                            FMC_TAGVDW3S_REG(FMC,1)
+#define FMC_TAGVDW3S2                            FMC_TAGVDW3S_REG(FMC,2)
+#define FMC_TAGVDW3S3                            FMC_TAGVDW3S_REG(FMC,3)
+#define FMC_DATAW0S0U                            FMC_DATA_U_REG(FMC,0,0)
+#define FMC_DATAW0S0L                            FMC_DATA_L_REG(FMC,0,0)
+#define FMC_DATAW0S1U                            FMC_DATA_U_REG(FMC,0,1)
+#define FMC_DATAW0S1L                            FMC_DATA_L_REG(FMC,0,1)
+#define FMC_DATAW0S2U                            FMC_DATA_U_REG(FMC,0,2)
+#define FMC_DATAW0S2L                            FMC_DATA_L_REG(FMC,0,2)
+#define FMC_DATAW0S3U                            FMC_DATA_U_REG(FMC,0,3)
+#define FMC_DATAW0S3L                            FMC_DATA_L_REG(FMC,0,3)
+#define FMC_DATAW1S0U                            FMC_DATA_U_REG(FMC,1,0)
+#define FMC_DATAW1S0L                            FMC_DATA_L_REG(FMC,1,0)
+#define FMC_DATAW1S1U                            FMC_DATA_U_REG(FMC,1,1)
+#define FMC_DATAW1S1L                            FMC_DATA_L_REG(FMC,1,1)
+#define FMC_DATAW1S2U                            FMC_DATA_U_REG(FMC,1,2)
+#define FMC_DATAW1S2L                            FMC_DATA_L_REG(FMC,1,2)
+#define FMC_DATAW1S3U                            FMC_DATA_U_REG(FMC,1,3)
+#define FMC_DATAW1S3L                            FMC_DATA_L_REG(FMC,1,3)
+#define FMC_DATAW2S0U                            FMC_DATA_U_REG(FMC,2,0)
+#define FMC_DATAW2S0L                            FMC_DATA_L_REG(FMC,2,0)
+#define FMC_DATAW2S1U                            FMC_DATA_U_REG(FMC,2,1)
+#define FMC_DATAW2S1L                            FMC_DATA_L_REG(FMC,2,1)
+#define FMC_DATAW2S2U                            FMC_DATA_U_REG(FMC,2,2)
+#define FMC_DATAW2S2L                            FMC_DATA_L_REG(FMC,2,2)
+#define FMC_DATAW2S3U                            FMC_DATA_U_REG(FMC,2,3)
+#define FMC_DATAW2S3L                            FMC_DATA_L_REG(FMC,2,3)
+#define FMC_DATAW3S0U                            FMC_DATA_U_REG(FMC,3,0)
+#define FMC_DATAW3S0L                            FMC_DATA_L_REG(FMC,3,0)
+#define FMC_DATAW3S1U                            FMC_DATA_U_REG(FMC,3,1)
+#define FMC_DATAW3S1L                            FMC_DATA_L_REG(FMC,3,1)
+#define FMC_DATAW3S2U                            FMC_DATA_U_REG(FMC,3,2)
+#define FMC_DATAW3S2L                            FMC_DATA_L_REG(FMC,3,2)
+#define FMC_DATAW3S3U                            FMC_DATA_U_REG(FMC,3,3)
+#define FMC_DATAW3S3L                            FMC_DATA_L_REG(FMC,3,3)
+
+/* FMC - Register array accessors */
+#define FMC_TAGVDW0S(index)                      FMC_TAGVDW0S_REG(FMC,index)
+#define FMC_TAGVDW1S(index)                      FMC_TAGVDW1S_REG(FMC,index)
+#define FMC_TAGVDW2S(index)                      FMC_TAGVDW2S_REG(FMC,index)
+#define FMC_TAGVDW3S(index)                      FMC_TAGVDW3S_REG(FMC,index)
+#define FMC_DATA_U(index,index2)                 FMC_DATA_U_REG(FMC,index,index2)
+#define FMC_DATA_L(index,index2)                 FMC_DATA_L_REG(FMC,index,index2)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t FEPROT;                             /**< EEPROM Protection Register, offset: 0x16 */
+  __IO uint8_t FDPROT;                             /**< Data Flash Protection Register, offset: 0x17 */
+} FTFE_Type, *FTFE_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register accessors */
+#define FTFE_FSTAT_REG(base)                     ((base)->FSTAT)
+#define FTFE_FCNFG_REG(base)                     ((base)->FCNFG)
+#define FTFE_FSEC_REG(base)                      ((base)->FSEC)
+#define FTFE_FOPT_REG(base)                      ((base)->FOPT)
+#define FTFE_FCCOB3_REG(base)                    ((base)->FCCOB3)
+#define FTFE_FCCOB2_REG(base)                    ((base)->FCCOB2)
+#define FTFE_FCCOB1_REG(base)                    ((base)->FCCOB1)
+#define FTFE_FCCOB0_REG(base)                    ((base)->FCCOB0)
+#define FTFE_FCCOB7_REG(base)                    ((base)->FCCOB7)
+#define FTFE_FCCOB6_REG(base)                    ((base)->FCCOB6)
+#define FTFE_FCCOB5_REG(base)                    ((base)->FCCOB5)
+#define FTFE_FCCOB4_REG(base)                    ((base)->FCCOB4)
+#define FTFE_FCCOBB_REG(base)                    ((base)->FCCOBB)
+#define FTFE_FCCOBA_REG(base)                    ((base)->FCCOBA)
+#define FTFE_FCCOB9_REG(base)                    ((base)->FCCOB9)
+#define FTFE_FCCOB8_REG(base)                    ((base)->FCCOB8)
+#define FTFE_FPROT3_REG(base)                    ((base)->FPROT3)
+#define FTFE_FPROT2_REG(base)                    ((base)->FPROT2)
+#define FTFE_FPROT1_REG(base)                    ((base)->FPROT1)
+#define FTFE_FPROT0_REG(base)                    ((base)->FPROT0)
+#define FTFE_FEPROT_REG(base)                    ((base)->FEPROT)
+#define FTFE_FDPROT_REG(base)                    ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFE_FSTAT_MGSTAT0_MASK                  0x1u
+#define FTFE_FSTAT_MGSTAT0_SHIFT                 0
+#define FTFE_FSTAT_MGSTAT0_WIDTH                 1
+#define FTFE_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_MGSTAT0_SHIFT))&FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_FPVIOL_MASK                   0x10u
+#define FTFE_FSTAT_FPVIOL_SHIFT                  4
+#define FTFE_FSTAT_FPVIOL_WIDTH                  1
+#define FTFE_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_FPVIOL_SHIFT))&FTFE_FSTAT_FPVIOL_MASK)
+#define FTFE_FSTAT_ACCERR_MASK                   0x20u
+#define FTFE_FSTAT_ACCERR_SHIFT                  5
+#define FTFE_FSTAT_ACCERR_WIDTH                  1
+#define FTFE_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_ACCERR_SHIFT))&FTFE_FSTAT_ACCERR_MASK)
+#define FTFE_FSTAT_RDCOLERR_MASK                 0x40u
+#define FTFE_FSTAT_RDCOLERR_SHIFT                6
+#define FTFE_FSTAT_RDCOLERR_WIDTH                1
+#define FTFE_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_RDCOLERR_SHIFT))&FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFE_FSTAT_CCIF_MASK                     0x80u
+#define FTFE_FSTAT_CCIF_SHIFT                    7
+#define FTFE_FSTAT_CCIF_WIDTH                    1
+#define FTFE_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_CCIF_SHIFT))&FTFE_FSTAT_CCIF_MASK)
+/* FCNFG Bit Fields */
+#define FTFE_FCNFG_EEERDY_MASK                   0x1u
+#define FTFE_FCNFG_EEERDY_SHIFT                  0
+#define FTFE_FCNFG_EEERDY_WIDTH                  1
+#define FTFE_FCNFG_EEERDY(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_EEERDY_SHIFT))&FTFE_FCNFG_EEERDY_MASK)
+#define FTFE_FCNFG_RAMRDY_MASK                   0x2u
+#define FTFE_FCNFG_RAMRDY_SHIFT                  1
+#define FTFE_FCNFG_RAMRDY_WIDTH                  1
+#define FTFE_FCNFG_RAMRDY(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RAMRDY_SHIFT))&FTFE_FCNFG_RAMRDY_MASK)
+#define FTFE_FCNFG_PFLSH_MASK                    0x4u
+#define FTFE_FCNFG_PFLSH_SHIFT                   2
+#define FTFE_FCNFG_PFLSH_WIDTH                   1
+#define FTFE_FCNFG_PFLSH(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_PFLSH_SHIFT))&FTFE_FCNFG_PFLSH_MASK)
+#define FTFE_FCNFG_SWAP_MASK                     0x8u
+#define FTFE_FCNFG_SWAP_SHIFT                    3
+#define FTFE_FCNFG_SWAP_WIDTH                    1
+#define FTFE_FCNFG_SWAP(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_SWAP_SHIFT))&FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_ERSSUSP_MASK                  0x10u
+#define FTFE_FCNFG_ERSSUSP_SHIFT                 4
+#define FTFE_FCNFG_ERSSUSP_WIDTH                 1
+#define FTFE_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSSUSP_SHIFT))&FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSAREQ_MASK                  0x20u
+#define FTFE_FCNFG_ERSAREQ_SHIFT                 5
+#define FTFE_FCNFG_ERSAREQ_WIDTH                 1
+#define FTFE_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSAREQ_SHIFT))&FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_RDCOLLIE_MASK                 0x40u
+#define FTFE_FCNFG_RDCOLLIE_SHIFT                6
+#define FTFE_FCNFG_RDCOLLIE_WIDTH                1
+#define FTFE_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RDCOLLIE_SHIFT))&FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_CCIE_MASK                     0x80u
+#define FTFE_FCNFG_CCIE_SHIFT                    7
+#define FTFE_FCNFG_CCIE_WIDTH                    1
+#define FTFE_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_CCIE_SHIFT))&FTFE_FCNFG_CCIE_MASK)
+/* FSEC Bit Fields */
+#define FTFE_FSEC_SEC_MASK                       0x3u
+#define FTFE_FSEC_SEC_SHIFT                      0
+#define FTFE_FSEC_SEC_WIDTH                      2
+#define FTFE_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK                    0xCu
+#define FTFE_FSEC_FSLACC_SHIFT                   2
+#define FTFE_FSEC_FSLACC_WIDTH                   2
+#define FTFE_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK                      0x30u
+#define FTFE_FSEC_MEEN_SHIFT                     4
+#define FTFE_FSEC_MEEN_WIDTH                     2
+#define FTFE_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK                     0xC0u
+#define FTFE_FSEC_KEYEN_SHIFT                    6
+#define FTFE_FSEC_KEYEN_WIDTH                    2
+#define FTFE_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFE_FOPT_OPT_MASK                       0xFFu
+#define FTFE_FOPT_OPT_SHIFT                      0
+#define FTFE_FOPT_OPT_WIDTH                      8
+#define FTFE_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFE_FCCOB3_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB3_CCOBn_SHIFT                  0
+#define FTFE_FCCOB3_CCOBn_WIDTH                  8
+#define FTFE_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFE_FCCOB2_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB2_CCOBn_SHIFT                  0
+#define FTFE_FCCOB2_CCOBn_WIDTH                  8
+#define FTFE_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFE_FCCOB1_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB1_CCOBn_SHIFT                  0
+#define FTFE_FCCOB1_CCOBn_WIDTH                  8
+#define FTFE_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFE_FCCOB0_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB0_CCOBn_SHIFT                  0
+#define FTFE_FCCOB0_CCOBn_WIDTH                  8
+#define FTFE_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFE_FCCOB7_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB7_CCOBn_SHIFT                  0
+#define FTFE_FCCOB7_CCOBn_WIDTH                  8
+#define FTFE_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFE_FCCOB6_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB6_CCOBn_SHIFT                  0
+#define FTFE_FCCOB6_CCOBn_WIDTH                  8
+#define FTFE_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFE_FCCOB5_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB5_CCOBn_SHIFT                  0
+#define FTFE_FCCOB5_CCOBn_WIDTH                  8
+#define FTFE_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFE_FCCOB4_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB4_CCOBn_SHIFT                  0
+#define FTFE_FCCOB4_CCOBn_WIDTH                  8
+#define FTFE_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFE_FCCOBB_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBB_CCOBn_SHIFT                  0
+#define FTFE_FCCOBB_CCOBn_WIDTH                  8
+#define FTFE_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFE_FCCOBA_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBA_CCOBn_SHIFT                  0
+#define FTFE_FCCOBA_CCOBn_WIDTH                  8
+#define FTFE_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFE_FCCOB9_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB9_CCOBn_SHIFT                  0
+#define FTFE_FCCOB9_CCOBn_WIDTH                  8
+#define FTFE_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFE_FCCOB8_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB8_CCOBn_SHIFT                  0
+#define FTFE_FCCOB8_CCOBn_WIDTH                  8
+#define FTFE_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFE_FPROT3_PROT_MASK                    0xFFu
+#define FTFE_FPROT3_PROT_SHIFT                   0
+#define FTFE_FPROT3_PROT_WIDTH                   8
+#define FTFE_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFE_FPROT2_PROT_MASK                    0xFFu
+#define FTFE_FPROT2_PROT_SHIFT                   0
+#define FTFE_FPROT2_PROT_WIDTH                   8
+#define FTFE_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFE_FPROT1_PROT_MASK                    0xFFu
+#define FTFE_FPROT1_PROT_SHIFT                   0
+#define FTFE_FPROT1_PROT_WIDTH                   8
+#define FTFE_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFE_FPROT0_PROT_MASK                    0xFFu
+#define FTFE_FPROT0_PROT_SHIFT                   0
+#define FTFE_FPROT0_PROT_WIDTH                   8
+#define FTFE_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFE_FEPROT_EPROT_MASK                   0xFFu
+#define FTFE_FEPROT_EPROT_SHIFT                  0
+#define FTFE_FEPROT_EPROT_WIDTH                  8
+#define FTFE_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFE_FDPROT_DPROT_MASK                   0xFFu
+#define FTFE_FDPROT_DPROT_SHIFT                  0
+#define FTFE_FDPROT_DPROT_WIDTH                  8
+#define FTFE_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE                                (0x40020000u)
+/** Peripheral FTFE base pointer */
+#define FTFE                                     ((FTFE_Type *)FTFE_BASE)
+#define FTFE_BASE_PTR                            (FTFE)
+/** Array initializer of FTFE peripheral base addresses */
+#define FTFE_BASE_ADDRS                          { FTFE_BASE }
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASE_PTRS                           { FTFE }
+/** Interrupt vectors for the FTFE peripheral type */
+#define FTFE_COMMAND_COMPLETE_IRQS               { FTFE_IRQn }
+#define FTFE_READ_COLLISION_IRQS                 { Read_Collision_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register instance definitions */
+/* FTFE */
+#define FTFE_FSTAT                               FTFE_FSTAT_REG(FTFE)
+#define FTFE_FCNFG                               FTFE_FCNFG_REG(FTFE)
+#define FTFE_FSEC                                FTFE_FSEC_REG(FTFE)
+#define FTFE_FOPT                                FTFE_FOPT_REG(FTFE)
+#define FTFE_FCCOB3                              FTFE_FCCOB3_REG(FTFE)
+#define FTFE_FCCOB2                              FTFE_FCCOB2_REG(FTFE)
+#define FTFE_FCCOB1                              FTFE_FCCOB1_REG(FTFE)
+#define FTFE_FCCOB0                              FTFE_FCCOB0_REG(FTFE)
+#define FTFE_FCCOB7                              FTFE_FCCOB7_REG(FTFE)
+#define FTFE_FCCOB6                              FTFE_FCCOB6_REG(FTFE)
+#define FTFE_FCCOB5                              FTFE_FCCOB5_REG(FTFE)
+#define FTFE_FCCOB4                              FTFE_FCCOB4_REG(FTFE)
+#define FTFE_FCCOBB                              FTFE_FCCOBB_REG(FTFE)
+#define FTFE_FCCOBA                              FTFE_FCCOBA_REG(FTFE)
+#define FTFE_FCCOB9                              FTFE_FCCOB9_REG(FTFE)
+#define FTFE_FCCOB8                              FTFE_FCCOB8_REG(FTFE)
+#define FTFE_FPROT3                              FTFE_FPROT3_REG(FTFE)
+#define FTFE_FPROT2                              FTFE_FPROT2_REG(FTFE)
+#define FTFE_FPROT1                              FTFE_FPROT1_REG(FTFE)
+#define FTFE_FPROT0                              FTFE_FPROT0_REG(FTFE)
+#define FTFE_FEPROT                              FTFE_FEPROT_REG(FTFE)
+#define FTFE_FDPROT                              FTFE_FDPROT_REG(FTFE)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[8];
+  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
+  __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
+  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
+  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
+  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
+  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
+  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
+  __IO uint32_t DEADTIME;                          /**< Deadtime Insertion Control, offset: 0x68 */
+  __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
+  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
+  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
+  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
+  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+  __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
+  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
+  __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
+  __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
+  __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type, *FTM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register accessors */
+#define FTM_SC_REG(base)                         ((base)->SC)
+#define FTM_CNT_REG(base)                        ((base)->CNT)
+#define FTM_MOD_REG(base)                        ((base)->MOD)
+#define FTM_CnSC_REG(base,index)                 ((base)->CONTROLS[index].CnSC)
+#define FTM_CnSC_COUNT                           8
+#define FTM_CnV_REG(base,index)                  ((base)->CONTROLS[index].CnV)
+#define FTM_CnV_COUNT                            8
+#define FTM_CNTIN_REG(base)                      ((base)->CNTIN)
+#define FTM_STATUS_REG(base)                     ((base)->STATUS)
+#define FTM_MODE_REG(base)                       ((base)->MODE)
+#define FTM_SYNC_REG(base)                       ((base)->SYNC)
+#define FTM_OUTINIT_REG(base)                    ((base)->OUTINIT)
+#define FTM_OUTMASK_REG(base)                    ((base)->OUTMASK)
+#define FTM_COMBINE_REG(base)                    ((base)->COMBINE)
+#define FTM_DEADTIME_REG(base)                   ((base)->DEADTIME)
+#define FTM_EXTTRIG_REG(base)                    ((base)->EXTTRIG)
+#define FTM_POL_REG(base)                        ((base)->POL)
+#define FTM_FMS_REG(base)                        ((base)->FMS)
+#define FTM_FILTER_REG(base)                     ((base)->FILTER)
+#define FTM_FLTCTRL_REG(base)                    ((base)->FLTCTRL)
+#define FTM_QDCTRL_REG(base)                     ((base)->QDCTRL)
+#define FTM_CONF_REG(base)                       ((base)->CONF)
+#define FTM_FLTPOL_REG(base)                     ((base)->FLTPOL)
+#define FTM_SYNCONF_REG(base)                    ((base)->SYNCONF)
+#define FTM_INVCTRL_REG(base)                    ((base)->INVCTRL)
+#define FTM_SWOCTRL_REG(base)                    ((base)->SWOCTRL)
+#define FTM_PWMLOAD_REG(base)                    ((base)->PWMLOAD)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK                           0x7u
+#define FTM_SC_PS_SHIFT                          0
+#define FTM_SC_PS_WIDTH                          3
+#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK                         0x18u
+#define FTM_SC_CLKS_SHIFT                        3
+#define FTM_SC_CLKS_WIDTH                        2
+#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK                        0x20u
+#define FTM_SC_CPWMS_SHIFT                       5
+#define FTM_SC_CPWMS_WIDTH                       1
+#define FTM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK                         0x40u
+#define FTM_SC_TOIE_SHIFT                        6
+#define FTM_SC_TOIE_WIDTH                        1
+#define FTM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK                          0x80u
+#define FTM_SC_TOF_SHIFT                         7
+#define FTM_SC_TOF_WIDTH                         1
+#define FTM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK                       0xFFFFu
+#define FTM_CNT_COUNT_SHIFT                      0
+#define FTM_CNT_COUNT_WIDTH                      16
+#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK                         0xFFFFu
+#define FTM_MOD_MOD_SHIFT                        0
+#define FTM_MOD_MOD_WIDTH                        16
+#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK                        0x1u
+#define FTM_CnSC_DMA_SHIFT                       0
+#define FTM_CnSC_DMA_WIDTH                       1
+#define FTM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ELSA_MASK                       0x4u
+#define FTM_CnSC_ELSA_SHIFT                      2
+#define FTM_CnSC_ELSA_WIDTH                      1
+#define FTM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK                       0x8u
+#define FTM_CnSC_ELSB_SHIFT                      3
+#define FTM_CnSC_ELSB_WIDTH                      1
+#define FTM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK                        0x10u
+#define FTM_CnSC_MSA_SHIFT                       4
+#define FTM_CnSC_MSA_WIDTH                       1
+#define FTM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK                        0x20u
+#define FTM_CnSC_MSB_SHIFT                       5
+#define FTM_CnSC_MSB_WIDTH                       1
+#define FTM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK                       0x40u
+#define FTM_CnSC_CHIE_SHIFT                      6
+#define FTM_CnSC_CHIE_WIDTH                      1
+#define FTM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK                        0x80u
+#define FTM_CnSC_CHF_SHIFT                       7
+#define FTM_CnSC_CHF_WIDTH                       1
+#define FTM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK                         0xFFFFu
+#define FTM_CnV_VAL_SHIFT                        0
+#define FTM_CnV_VAL_WIDTH                        16
+#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK                      0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT                     0
+#define FTM_CNTIN_INIT_WIDTH                     16
+#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK                     0x1u
+#define FTM_STATUS_CH0F_SHIFT                    0
+#define FTM_STATUS_CH0F_WIDTH                    1
+#define FTM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK                     0x2u
+#define FTM_STATUS_CH1F_SHIFT                    1
+#define FTM_STATUS_CH1F_WIDTH                    1
+#define FTM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK                     0x4u
+#define FTM_STATUS_CH2F_SHIFT                    2
+#define FTM_STATUS_CH2F_WIDTH                    1
+#define FTM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK                     0x8u
+#define FTM_STATUS_CH3F_SHIFT                    3
+#define FTM_STATUS_CH3F_WIDTH                    1
+#define FTM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK                     0x10u
+#define FTM_STATUS_CH4F_SHIFT                    4
+#define FTM_STATUS_CH4F_WIDTH                    1
+#define FTM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK                     0x20u
+#define FTM_STATUS_CH5F_SHIFT                    5
+#define FTM_STATUS_CH5F_WIDTH                    1
+#define FTM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK                     0x40u
+#define FTM_STATUS_CH6F_SHIFT                    6
+#define FTM_STATUS_CH6F_WIDTH                    1
+#define FTM_STATUS_CH6F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK                     0x80u
+#define FTM_STATUS_CH7F_SHIFT                    7
+#define FTM_STATUS_CH7F_WIDTH                    1
+#define FTM_STATUS_CH7F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK                      0x1u
+#define FTM_MODE_FTMEN_SHIFT                     0
+#define FTM_MODE_FTMEN_WIDTH                     1
+#define FTM_MODE_FTMEN(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK                       0x2u
+#define FTM_MODE_INIT_SHIFT                      1
+#define FTM_MODE_INIT_WIDTH                      1
+#define FTM_MODE_INIT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK                      0x4u
+#define FTM_MODE_WPDIS_SHIFT                     2
+#define FTM_MODE_WPDIS_WIDTH                     1
+#define FTM_MODE_WPDIS(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK                    0x8u
+#define FTM_MODE_PWMSYNC_SHIFT                   3
+#define FTM_MODE_PWMSYNC_WIDTH                   1
+#define FTM_MODE_PWMSYNC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK                    0x10u
+#define FTM_MODE_CAPTEST_SHIFT                   4
+#define FTM_MODE_CAPTEST_WIDTH                   1
+#define FTM_MODE_CAPTEST(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK                     0x60u
+#define FTM_MODE_FAULTM_SHIFT                    5
+#define FTM_MODE_FAULTM_WIDTH                    2
+#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK                    0x80u
+#define FTM_MODE_FAULTIE_SHIFT                   7
+#define FTM_MODE_FAULTIE_WIDTH                   1
+#define FTM_MODE_FAULTIE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK                     0x1u
+#define FTM_SYNC_CNTMIN_SHIFT                    0
+#define FTM_SYNC_CNTMIN_WIDTH                    1
+#define FTM_SYNC_CNTMIN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK                     0x2u
+#define FTM_SYNC_CNTMAX_SHIFT                    1
+#define FTM_SYNC_CNTMAX_WIDTH                    1
+#define FTM_SYNC_CNTMAX(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK                     0x4u
+#define FTM_SYNC_REINIT_SHIFT                    2
+#define FTM_SYNC_REINIT_WIDTH                    1
+#define FTM_SYNC_REINIT(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK                    0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT                   3
+#define FTM_SYNC_SYNCHOM_WIDTH                   1
+#define FTM_SYNC_SYNCHOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK                      0x10u
+#define FTM_SYNC_TRIG0_SHIFT                     4
+#define FTM_SYNC_TRIG0_WIDTH                     1
+#define FTM_SYNC_TRIG0(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK                      0x20u
+#define FTM_SYNC_TRIG1_SHIFT                     5
+#define FTM_SYNC_TRIG1_WIDTH                     1
+#define FTM_SYNC_TRIG1(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK                      0x40u
+#define FTM_SYNC_TRIG2_SHIFT                     6
+#define FTM_SYNC_TRIG2_WIDTH                     1
+#define FTM_SYNC_TRIG2(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK                     0x80u
+#define FTM_SYNC_SWSYNC_SHIFT                    7
+#define FTM_SYNC_SWSYNC_WIDTH                    1
+#define FTM_SYNC_SWSYNC(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK                   0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT                  0
+#define FTM_OUTINIT_CH0OI_WIDTH                  1
+#define FTM_OUTINIT_CH0OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK                   0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT                  1
+#define FTM_OUTINIT_CH1OI_WIDTH                  1
+#define FTM_OUTINIT_CH1OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK                   0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT                  2
+#define FTM_OUTINIT_CH2OI_WIDTH                  1
+#define FTM_OUTINIT_CH2OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK                   0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT                  3
+#define FTM_OUTINIT_CH3OI_WIDTH                  1
+#define FTM_OUTINIT_CH3OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK                   0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT                  4
+#define FTM_OUTINIT_CH4OI_WIDTH                  1
+#define FTM_OUTINIT_CH4OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK                   0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT                  5
+#define FTM_OUTINIT_CH5OI_WIDTH                  1
+#define FTM_OUTINIT_CH5OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK                   0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT                  6
+#define FTM_OUTINIT_CH6OI_WIDTH                  1
+#define FTM_OUTINIT_CH6OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK                   0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT                  7
+#define FTM_OUTINIT_CH7OI_WIDTH                  1
+#define FTM_OUTINIT_CH7OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK                   0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT                  0
+#define FTM_OUTMASK_CH0OM_WIDTH                  1
+#define FTM_OUTMASK_CH0OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK                   0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT                  1
+#define FTM_OUTMASK_CH1OM_WIDTH                  1
+#define FTM_OUTMASK_CH1OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK                   0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT                  2
+#define FTM_OUTMASK_CH2OM_WIDTH                  1
+#define FTM_OUTMASK_CH2OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK                   0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT                  3
+#define FTM_OUTMASK_CH3OM_WIDTH                  1
+#define FTM_OUTMASK_CH3OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK                   0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT                  4
+#define FTM_OUTMASK_CH4OM_WIDTH                  1
+#define FTM_OUTMASK_CH4OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK                   0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT                  5
+#define FTM_OUTMASK_CH5OM_WIDTH                  1
+#define FTM_OUTMASK_CH5OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK                   0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT                  6
+#define FTM_OUTMASK_CH6OM_WIDTH                  1
+#define FTM_OUTMASK_CH6OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK                   0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT                  7
+#define FTM_OUTMASK_CH7OM_WIDTH                  1
+#define FTM_OUTMASK_CH7OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK                0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT               0
+#define FTM_COMBINE_COMBINE0_WIDTH               1
+#define FTM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK                   0x2u
+#define FTM_COMBINE_COMP0_SHIFT                  1
+#define FTM_COMBINE_COMP0_WIDTH                  1
+#define FTM_COMBINE_COMP0(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK                0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT               2
+#define FTM_COMBINE_DECAPEN0_WIDTH               1
+#define FTM_COMBINE_DECAPEN0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK                  0x8u
+#define FTM_COMBINE_DECAP0_SHIFT                 3
+#define FTM_COMBINE_DECAP0_WIDTH                 1
+#define FTM_COMBINE_DECAP0(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK                   0x10u
+#define FTM_COMBINE_DTEN0_SHIFT                  4
+#define FTM_COMBINE_DTEN0_WIDTH                  1
+#define FTM_COMBINE_DTEN0(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK                 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT                5
+#define FTM_COMBINE_SYNCEN0_WIDTH                1
+#define FTM_COMBINE_SYNCEN0(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK                0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT               6
+#define FTM_COMBINE_FAULTEN0_WIDTH               1
+#define FTM_COMBINE_FAULTEN0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK                0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT               8
+#define FTM_COMBINE_COMBINE1_WIDTH               1
+#define FTM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK                   0x200u
+#define FTM_COMBINE_COMP1_SHIFT                  9
+#define FTM_COMBINE_COMP1_WIDTH                  1
+#define FTM_COMBINE_COMP1(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK                0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT               10
+#define FTM_COMBINE_DECAPEN1_WIDTH               1
+#define FTM_COMBINE_DECAPEN1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK                  0x800u
+#define FTM_COMBINE_DECAP1_SHIFT                 11
+#define FTM_COMBINE_DECAP1_WIDTH                 1
+#define FTM_COMBINE_DECAP1(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK                   0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT                  12
+#define FTM_COMBINE_DTEN1_WIDTH                  1
+#define FTM_COMBINE_DTEN1(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK                 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT                13
+#define FTM_COMBINE_SYNCEN1_WIDTH                1
+#define FTM_COMBINE_SYNCEN1(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK                0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT               14
+#define FTM_COMBINE_FAULTEN1_WIDTH               1
+#define FTM_COMBINE_FAULTEN1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK                0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT               16
+#define FTM_COMBINE_COMBINE2_WIDTH               1
+#define FTM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK                   0x20000u
+#define FTM_COMBINE_COMP2_SHIFT                  17
+#define FTM_COMBINE_COMP2_WIDTH                  1
+#define FTM_COMBINE_COMP2(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK                0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT               18
+#define FTM_COMBINE_DECAPEN2_WIDTH               1
+#define FTM_COMBINE_DECAPEN2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK                  0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT                 19
+#define FTM_COMBINE_DECAP2_WIDTH                 1
+#define FTM_COMBINE_DECAP2(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK                   0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT                  20
+#define FTM_COMBINE_DTEN2_WIDTH                  1
+#define FTM_COMBINE_DTEN2(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK                 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT                21
+#define FTM_COMBINE_SYNCEN2_WIDTH                1
+#define FTM_COMBINE_SYNCEN2(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK                0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT               22
+#define FTM_COMBINE_FAULTEN2_WIDTH               1
+#define FTM_COMBINE_FAULTEN2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK                0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT               24
+#define FTM_COMBINE_COMBINE3_WIDTH               1
+#define FTM_COMBINE_COMBINE3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK                   0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT                  25
+#define FTM_COMBINE_COMP3_WIDTH                  1
+#define FTM_COMBINE_COMP3(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK                0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT               26
+#define FTM_COMBINE_DECAPEN3_WIDTH               1
+#define FTM_COMBINE_DECAPEN3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK                  0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT                 27
+#define FTM_COMBINE_DECAP3_WIDTH                 1
+#define FTM_COMBINE_DECAP3(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK                   0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT                  28
+#define FTM_COMBINE_DTEN3_WIDTH                  1
+#define FTM_COMBINE_DTEN3(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK                 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT                29
+#define FTM_COMBINE_SYNCEN3_WIDTH                1
+#define FTM_COMBINE_SYNCEN3(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK                0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT               30
+#define FTM_COMBINE_FAULTEN3_WIDTH               1
+#define FTM_COMBINE_FAULTEN3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK                  0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT                 0
+#define FTM_DEADTIME_DTVAL_WIDTH                 6
+#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK                   0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT                  6
+#define FTM_DEADTIME_DTPS_WIDTH                  2
+#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK                 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT                0
+#define FTM_EXTTRIG_CH2TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH2TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK                 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT                1
+#define FTM_EXTTRIG_CH3TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH3TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK                 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT                2
+#define FTM_EXTTRIG_CH4TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH4TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK                 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT                3
+#define FTM_EXTTRIG_CH5TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH5TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK                 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT                4
+#define FTM_EXTTRIG_CH0TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH0TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK                 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT                5
+#define FTM_EXTTRIG_CH1TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH1TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK              0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT             6
+#define FTM_EXTTRIG_INITTRIGEN_WIDTH             1
+#define FTM_EXTTRIG_INITTRIGEN(x)                (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK                   0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT                  7
+#define FTM_EXTTRIG_TRIGF_WIDTH                  1
+#define FTM_EXTTRIG_TRIGF(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK                        0x1u
+#define FTM_POL_POL0_SHIFT                       0
+#define FTM_POL_POL0_WIDTH                       1
+#define FTM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK                        0x2u
+#define FTM_POL_POL1_SHIFT                       1
+#define FTM_POL_POL1_WIDTH                       1
+#define FTM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK                        0x4u
+#define FTM_POL_POL2_SHIFT                       2
+#define FTM_POL_POL2_WIDTH                       1
+#define FTM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK                        0x8u
+#define FTM_POL_POL3_SHIFT                       3
+#define FTM_POL_POL3_WIDTH                       1
+#define FTM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK                        0x10u
+#define FTM_POL_POL4_SHIFT                       4
+#define FTM_POL_POL4_WIDTH                       1
+#define FTM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK                        0x20u
+#define FTM_POL_POL5_SHIFT                       5
+#define FTM_POL_POL5_WIDTH                       1
+#define FTM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK                        0x40u
+#define FTM_POL_POL6_SHIFT                       6
+#define FTM_POL_POL6_WIDTH                       1
+#define FTM_POL_POL6(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK                        0x80u
+#define FTM_POL_POL7_SHIFT                       7
+#define FTM_POL_POL7_WIDTH                       1
+#define FTM_POL_POL7(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK                     0x1u
+#define FTM_FMS_FAULTF0_SHIFT                    0
+#define FTM_FMS_FAULTF0_WIDTH                    1
+#define FTM_FMS_FAULTF0(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK                     0x2u
+#define FTM_FMS_FAULTF1_SHIFT                    1
+#define FTM_FMS_FAULTF1_WIDTH                    1
+#define FTM_FMS_FAULTF1(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK                     0x4u
+#define FTM_FMS_FAULTF2_SHIFT                    2
+#define FTM_FMS_FAULTF2_WIDTH                    1
+#define FTM_FMS_FAULTF2(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK                     0x8u
+#define FTM_FMS_FAULTF3_SHIFT                    3
+#define FTM_FMS_FAULTF3_WIDTH                    1
+#define FTM_FMS_FAULTF3(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK                     0x20u
+#define FTM_FMS_FAULTIN_SHIFT                    5
+#define FTM_FMS_FAULTIN_WIDTH                    1
+#define FTM_FMS_FAULTIN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK                        0x40u
+#define FTM_FMS_WPEN_SHIFT                       6
+#define FTM_FMS_WPEN_WIDTH                       1
+#define FTM_FMS_WPEN(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK                      0x80u
+#define FTM_FMS_FAULTF_SHIFT                     7
+#define FTM_FMS_FAULTF_WIDTH                     1
+#define FTM_FMS_FAULTF(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK                  0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT                 0
+#define FTM_FILTER_CH0FVAL_WIDTH                 4
+#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK                  0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT                 4
+#define FTM_FILTER_CH1FVAL_WIDTH                 4
+#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK                  0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT                 8
+#define FTM_FILTER_CH2FVAL_WIDTH                 4
+#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK                  0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT                 12
+#define FTM_FILTER_CH3FVAL_WIDTH                 4
+#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK                0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT               0
+#define FTM_FLTCTRL_FAULT0EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT0EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK                0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT               1
+#define FTM_FLTCTRL_FAULT1EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT1EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK                0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT               2
+#define FTM_FLTCTRL_FAULT2EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT2EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK                0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT               3
+#define FTM_FLTCTRL_FAULT3EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT3EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK                0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT               4
+#define FTM_FLTCTRL_FFLTR0EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR0EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK                0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT               5
+#define FTM_FLTCTRL_FFLTR1EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR1EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK                0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT               6
+#define FTM_FLTCTRL_FFLTR2EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR2EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK                0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT               7
+#define FTM_FLTCTRL_FFLTR3EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR3EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK                   0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT                  8
+#define FTM_FLTCTRL_FFVAL_WIDTH                  4
+#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK                   0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT                  0
+#define FTM_QDCTRL_QUADEN_WIDTH                  1
+#define FTM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK                   0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT                  1
+#define FTM_QDCTRL_TOFDIR_WIDTH                  1
+#define FTM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK                   0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT                  2
+#define FTM_QDCTRL_QUADIR_WIDTH                  1
+#define FTM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK                 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT                3
+#define FTM_QDCTRL_QUADMODE_WIDTH                1
+#define FTM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK                   0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT                  4
+#define FTM_QDCTRL_PHBPOL_WIDTH                  1
+#define FTM_QDCTRL_PHBPOL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK                   0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT                  5
+#define FTM_QDCTRL_PHAPOL_WIDTH                  1
+#define FTM_QDCTRL_PHAPOL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK                0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT               6
+#define FTM_QDCTRL_PHBFLTREN_WIDTH               1
+#define FTM_QDCTRL_PHBFLTREN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK                0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT               7
+#define FTM_QDCTRL_PHAFLTREN_WIDTH               1
+#define FTM_QDCTRL_PHAFLTREN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK                     0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT                    0
+#define FTM_CONF_NUMTOF_WIDTH                    5
+#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK                    0xC0u
+#define FTM_CONF_BDMMODE_SHIFT                   6
+#define FTM_CONF_BDMMODE_WIDTH                   2
+#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK                     0x200u
+#define FTM_CONF_GTBEEN_SHIFT                    9
+#define FTM_CONF_GTBEEN_WIDTH                    1
+#define FTM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK                    0x400u
+#define FTM_CONF_GTBEOUT_SHIFT                   10
+#define FTM_CONF_GTBEOUT_WIDTH                   1
+#define FTM_CONF_GTBEOUT(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK                  0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT                 0
+#define FTM_FLTPOL_FLT0POL_WIDTH                 1
+#define FTM_FLTPOL_FLT0POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK                  0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT                 1
+#define FTM_FLTPOL_FLT1POL_WIDTH                 1
+#define FTM_FLTPOL_FLT1POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK                  0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT                 2
+#define FTM_FLTPOL_FLT2POL_WIDTH                 1
+#define FTM_FLTPOL_FLT2POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK                  0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT                 3
+#define FTM_FLTPOL_FLT3POL_WIDTH                 1
+#define FTM_FLTPOL_FLT3POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK              0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT             0
+#define FTM_SYNCONF_HWTRIGMODE_WIDTH             1
+#define FTM_SYNCONF_HWTRIGMODE(x)                (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK                  0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT                 2
+#define FTM_SYNCONF_CNTINC_WIDTH                 1
+#define FTM_SYNCONF_CNTINC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK                    0x10u
+#define FTM_SYNCONF_INVC_SHIFT                   4
+#define FTM_SYNCONF_INVC_WIDTH                   1
+#define FTM_SYNCONF_INVC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK                    0x20u
+#define FTM_SYNCONF_SWOC_SHIFT                   5
+#define FTM_SYNCONF_SWOC_WIDTH                   1
+#define FTM_SYNCONF_SWOC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK                0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT               7
+#define FTM_SYNCONF_SYNCMODE_WIDTH               1
+#define FTM_SYNCONF_SYNCMODE(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK                0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT               8
+#define FTM_SYNCONF_SWRSTCNT_WIDTH               1
+#define FTM_SYNCONF_SWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK                 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT                9
+#define FTM_SYNCONF_SWWRBUF_WIDTH                1
+#define FTM_SYNCONF_SWWRBUF(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK                    0x400u
+#define FTM_SYNCONF_SWOM_SHIFT                   10
+#define FTM_SYNCONF_SWOM_WIDTH                   1
+#define FTM_SYNCONF_SWOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK                  0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT                 11
+#define FTM_SYNCONF_SWINVC_WIDTH                 1
+#define FTM_SYNCONF_SWINVC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK                   0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT                  12
+#define FTM_SYNCONF_SWSOC_WIDTH                  1
+#define FTM_SYNCONF_SWSOC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK                0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT               16
+#define FTM_SYNCONF_HWRSTCNT_WIDTH               1
+#define FTM_SYNCONF_HWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK                 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT                17
+#define FTM_SYNCONF_HWWRBUF_WIDTH                1
+#define FTM_SYNCONF_HWWRBUF(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK                    0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT                   18
+#define FTM_SYNCONF_HWOM_WIDTH                   1
+#define FTM_SYNCONF_HWOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK                  0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT                 19
+#define FTM_SYNCONF_HWINVC_WIDTH                 1
+#define FTM_SYNCONF_HWINVC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK                   0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT                  20
+#define FTM_SYNCONF_HWSOC_WIDTH                  1
+#define FTM_SYNCONF_HWSOC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK                  0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT                 0
+#define FTM_INVCTRL_INV0EN_WIDTH                 1
+#define FTM_INVCTRL_INV0EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK                  0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT                 1
+#define FTM_INVCTRL_INV1EN_WIDTH                 1
+#define FTM_INVCTRL_INV1EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK                  0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT                 2
+#define FTM_INVCTRL_INV2EN_WIDTH                 1
+#define FTM_INVCTRL_INV2EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK                  0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT                 3
+#define FTM_INVCTRL_INV3EN_WIDTH                 1
+#define FTM_INVCTRL_INV3EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK                   0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT                  0
+#define FTM_SWOCTRL_CH0OC_WIDTH                  1
+#define FTM_SWOCTRL_CH0OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK                   0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT                  1
+#define FTM_SWOCTRL_CH1OC_WIDTH                  1
+#define FTM_SWOCTRL_CH1OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK                   0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT                  2
+#define FTM_SWOCTRL_CH2OC_WIDTH                  1
+#define FTM_SWOCTRL_CH2OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK                   0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT                  3
+#define FTM_SWOCTRL_CH3OC_WIDTH                  1
+#define FTM_SWOCTRL_CH3OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK                   0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT                  4
+#define FTM_SWOCTRL_CH4OC_WIDTH                  1
+#define FTM_SWOCTRL_CH4OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK                   0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT                  5
+#define FTM_SWOCTRL_CH5OC_WIDTH                  1
+#define FTM_SWOCTRL_CH5OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK                   0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT                  6
+#define FTM_SWOCTRL_CH6OC_WIDTH                  1
+#define FTM_SWOCTRL_CH6OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK                   0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT                  7
+#define FTM_SWOCTRL_CH7OC_WIDTH                  1
+#define FTM_SWOCTRL_CH7OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK                  0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT                 8
+#define FTM_SWOCTRL_CH0OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH0OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK                  0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT                 9
+#define FTM_SWOCTRL_CH1OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH1OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK                  0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT                 10
+#define FTM_SWOCTRL_CH2OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH2OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK                  0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT                 11
+#define FTM_SWOCTRL_CH3OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH3OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK                  0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT                 12
+#define FTM_SWOCTRL_CH4OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH4OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK                  0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT                 13
+#define FTM_SWOCTRL_CH5OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH5OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK                  0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT                 14
+#define FTM_SWOCTRL_CH6OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH6OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK                  0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT                 15
+#define FTM_SWOCTRL_CH7OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH7OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK                  0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT                 0
+#define FTM_PWMLOAD_CH0SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH0SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK                  0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT                 1
+#define FTM_PWMLOAD_CH1SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH1SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK                  0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT                 2
+#define FTM_PWMLOAD_CH2SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH2SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK                  0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT                 3
+#define FTM_PWMLOAD_CH3SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH3SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK                  0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT                 4
+#define FTM_PWMLOAD_CH4SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH4SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK                  0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT                 5
+#define FTM_PWMLOAD_CH5SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH5SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK                  0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT                 6
+#define FTM_PWMLOAD_CH6SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH6SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK                  0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT                 7
+#define FTM_PWMLOAD_CH7SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH7SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK                    0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT                   9
+#define FTM_PWMLOAD_LDOK_WIDTH                   1
+#define FTM_PWMLOAD_LDOK(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE                                (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0                                     ((FTM_Type *)FTM0_BASE)
+#define FTM0_BASE_PTR                            (FTM0)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE                                (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1                                     ((FTM_Type *)FTM1_BASE)
+#define FTM1_BASE_PTR                            (FTM1)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE                                (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2                                     ((FTM_Type *)FTM2_BASE)
+#define FTM2_BASE_PTR                            (FTM2)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE                                (0x400B9000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3                                     ((FTM_Type *)FTM3_BASE)
+#define FTM3_BASE_PTR                            (FTM3)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS                           { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS                            { FTM0, FTM1, FTM2, FTM3 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS                                 { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register instance definitions */
+/* FTM0 */
+#define FTM0_SC                                  FTM_SC_REG(FTM0)
+#define FTM0_CNT                                 FTM_CNT_REG(FTM0)
+#define FTM0_MOD                                 FTM_MOD_REG(FTM0)
+#define FTM0_C0SC                                FTM_CnSC_REG(FTM0,0)
+#define FTM0_C0V                                 FTM_CnV_REG(FTM0,0)
+#define FTM0_C1SC                                FTM_CnSC_REG(FTM0,1)
+#define FTM0_C1V                                 FTM_CnV_REG(FTM0,1)
+#define FTM0_C2SC                                FTM_CnSC_REG(FTM0,2)
+#define FTM0_C2V                                 FTM_CnV_REG(FTM0,2)
+#define FTM0_C3SC                                FTM_CnSC_REG(FTM0,3)
+#define FTM0_C3V                                 FTM_CnV_REG(FTM0,3)
+#define FTM0_C4SC                                FTM_CnSC_REG(FTM0,4)
+#define FTM0_C4V                                 FTM_CnV_REG(FTM0,4)
+#define FTM0_C5SC                                FTM_CnSC_REG(FTM0,5)
+#define FTM0_C5V                                 FTM_CnV_REG(FTM0,5)
+#define FTM0_C6SC                                FTM_CnSC_REG(FTM0,6)
+#define FTM0_C6V                                 FTM_CnV_REG(FTM0,6)
+#define FTM0_C7SC                                FTM_CnSC_REG(FTM0,7)
+#define FTM0_C7V                                 FTM_CnV_REG(FTM0,7)
+#define FTM0_CNTIN                               FTM_CNTIN_REG(FTM0)
+#define FTM0_STATUS                              FTM_STATUS_REG(FTM0)
+#define FTM0_MODE                                FTM_MODE_REG(FTM0)
+#define FTM0_SYNC                                FTM_SYNC_REG(FTM0)
+#define FTM0_OUTINIT                             FTM_OUTINIT_REG(FTM0)
+#define FTM0_OUTMASK                             FTM_OUTMASK_REG(FTM0)
+#define FTM0_COMBINE                             FTM_COMBINE_REG(FTM0)
+#define FTM0_DEADTIME                            FTM_DEADTIME_REG(FTM0)
+#define FTM0_EXTTRIG                             FTM_EXTTRIG_REG(FTM0)
+#define FTM0_POL                                 FTM_POL_REG(FTM0)
+#define FTM0_FMS                                 FTM_FMS_REG(FTM0)
+#define FTM0_FILTER                              FTM_FILTER_REG(FTM0)
+#define FTM0_FLTCTRL                             FTM_FLTCTRL_REG(FTM0)
+#define FTM0_QDCTRL                              FTM_QDCTRL_REG(FTM0)
+#define FTM0_CONF                                FTM_CONF_REG(FTM0)
+#define FTM0_FLTPOL                              FTM_FLTPOL_REG(FTM0)
+#define FTM0_SYNCONF                             FTM_SYNCONF_REG(FTM0)
+#define FTM0_INVCTRL                             FTM_INVCTRL_REG(FTM0)
+#define FTM0_SWOCTRL                             FTM_SWOCTRL_REG(FTM0)
+#define FTM0_PWMLOAD                             FTM_PWMLOAD_REG(FTM0)
+/* FTM1 */
+#define FTM1_SC                                  FTM_SC_REG(FTM1)
+#define FTM1_CNT                                 FTM_CNT_REG(FTM1)
+#define FTM1_MOD                                 FTM_MOD_REG(FTM1)
+#define FTM1_C0SC                                FTM_CnSC_REG(FTM1,0)
+#define FTM1_C0V                                 FTM_CnV_REG(FTM1,0)
+#define FTM1_C1SC                                FTM_CnSC_REG(FTM1,1)
+#define FTM1_C1V                                 FTM_CnV_REG(FTM1,1)
+#define FTM1_CNTIN                               FTM_CNTIN_REG(FTM1)
+#define FTM1_STATUS                              FTM_STATUS_REG(FTM1)
+#define FTM1_MODE                                FTM_MODE_REG(FTM1)
+#define FTM1_SYNC                                FTM_SYNC_REG(FTM1)
+#define FTM1_OUTINIT                             FTM_OUTINIT_REG(FTM1)
+#define FTM1_OUTMASK                             FTM_OUTMASK_REG(FTM1)
+#define FTM1_COMBINE                             FTM_COMBINE_REG(FTM1)
+#define FTM1_DEADTIME                            FTM_DEADTIME_REG(FTM1)
+#define FTM1_EXTTRIG                             FTM_EXTTRIG_REG(FTM1)
+#define FTM1_POL                                 FTM_POL_REG(FTM1)
+#define FTM1_FMS                                 FTM_FMS_REG(FTM1)
+#define FTM1_FILTER                              FTM_FILTER_REG(FTM1)
+#define FTM1_FLTCTRL                             FTM_FLTCTRL_REG(FTM1)
+#define FTM1_QDCTRL                              FTM_QDCTRL_REG(FTM1)
+#define FTM1_CONF                                FTM_CONF_REG(FTM1)
+#define FTM1_FLTPOL                              FTM_FLTPOL_REG(FTM1)
+#define FTM1_SYNCONF                             FTM_SYNCONF_REG(FTM1)
+#define FTM1_INVCTRL                             FTM_INVCTRL_REG(FTM1)
+#define FTM1_SWOCTRL                             FTM_SWOCTRL_REG(FTM1)
+#define FTM1_PWMLOAD                             FTM_PWMLOAD_REG(FTM1)
+/* FTM2 */
+#define FTM2_SC                                  FTM_SC_REG(FTM2)
+#define FTM2_CNT                                 FTM_CNT_REG(FTM2)
+#define FTM2_MOD                                 FTM_MOD_REG(FTM2)
+#define FTM2_C0SC                                FTM_CnSC_REG(FTM2,0)
+#define FTM2_C0V                                 FTM_CnV_REG(FTM2,0)
+#define FTM2_C1SC                                FTM_CnSC_REG(FTM2,1)
+#define FTM2_C1V                                 FTM_CnV_REG(FTM2,1)
+#define FTM2_CNTIN                               FTM_CNTIN_REG(FTM2)
+#define FTM2_STATUS                              FTM_STATUS_REG(FTM2)
+#define FTM2_MODE                                FTM_MODE_REG(FTM2)
+#define FTM2_SYNC                                FTM_SYNC_REG(FTM2)
+#define FTM2_OUTINIT                             FTM_OUTINIT_REG(FTM2)
+#define FTM2_OUTMASK                             FTM_OUTMASK_REG(FTM2)
+#define FTM2_COMBINE                             FTM_COMBINE_REG(FTM2)
+#define FTM2_DEADTIME                            FTM_DEADTIME_REG(FTM2)
+#define FTM2_EXTTRIG                             FTM_EXTTRIG_REG(FTM2)
+#define FTM2_POL                                 FTM_POL_REG(FTM2)
+#define FTM2_FMS                                 FTM_FMS_REG(FTM2)
+#define FTM2_FILTER                              FTM_FILTER_REG(FTM2)
+#define FTM2_FLTCTRL                             FTM_FLTCTRL_REG(FTM2)
+#define FTM2_QDCTRL                              FTM_QDCTRL_REG(FTM2)
+#define FTM2_CONF                                FTM_CONF_REG(FTM2)
+#define FTM2_FLTPOL                              FTM_FLTPOL_REG(FTM2)
+#define FTM2_SYNCONF                             FTM_SYNCONF_REG(FTM2)
+#define FTM2_INVCTRL                             FTM_INVCTRL_REG(FTM2)
+#define FTM2_SWOCTRL                             FTM_SWOCTRL_REG(FTM2)
+#define FTM2_PWMLOAD                             FTM_PWMLOAD_REG(FTM2)
+/* FTM3 */
+#define FTM3_SC                                  FTM_SC_REG(FTM3)
+#define FTM3_CNT                                 FTM_CNT_REG(FTM3)
+#define FTM3_MOD                                 FTM_MOD_REG(FTM3)
+#define FTM3_C0SC                                FTM_CnSC_REG(FTM3,0)
+#define FTM3_C0V                                 FTM_CnV_REG(FTM3,0)
+#define FTM3_C1SC                                FTM_CnSC_REG(FTM3,1)
+#define FTM3_C1V                                 FTM_CnV_REG(FTM3,1)
+#define FTM3_C2SC                                FTM_CnSC_REG(FTM3,2)
+#define FTM3_C2V                                 FTM_CnV_REG(FTM3,2)
+#define FTM3_C3SC                                FTM_CnSC_REG(FTM3,3)
+#define FTM3_C3V                                 FTM_CnV_REG(FTM3,3)
+#define FTM3_C4SC                                FTM_CnSC_REG(FTM3,4)
+#define FTM3_C4V                                 FTM_CnV_REG(FTM3,4)
+#define FTM3_C5SC                                FTM_CnSC_REG(FTM3,5)
+#define FTM3_C5V                                 FTM_CnV_REG(FTM3,5)
+#define FTM3_C6SC                                FTM_CnSC_REG(FTM3,6)
+#define FTM3_C6V                                 FTM_CnV_REG(FTM3,6)
+#define FTM3_C7SC                                FTM_CnSC_REG(FTM3,7)
+#define FTM3_C7V                                 FTM_CnV_REG(FTM3,7)
+#define FTM3_CNTIN                               FTM_CNTIN_REG(FTM3)
+#define FTM3_STATUS                              FTM_STATUS_REG(FTM3)
+#define FTM3_MODE                                FTM_MODE_REG(FTM3)
+#define FTM3_SYNC                                FTM_SYNC_REG(FTM3)
+#define FTM3_OUTINIT                             FTM_OUTINIT_REG(FTM3)
+#define FTM3_OUTMASK                             FTM_OUTMASK_REG(FTM3)
+#define FTM3_COMBINE                             FTM_COMBINE_REG(FTM3)
+#define FTM3_DEADTIME                            FTM_DEADTIME_REG(FTM3)
+#define FTM3_EXTTRIG                             FTM_EXTTRIG_REG(FTM3)
+#define FTM3_POL                                 FTM_POL_REG(FTM3)
+#define FTM3_FMS                                 FTM_FMS_REG(FTM3)
+#define FTM3_FILTER                              FTM_FILTER_REG(FTM3)
+#define FTM3_FLTCTRL                             FTM_FLTCTRL_REG(FTM3)
+#define FTM3_QDCTRL                              FTM_QDCTRL_REG(FTM3)
+#define FTM3_CONF                                FTM_CONF_REG(FTM3)
+#define FTM3_FLTPOL                              FTM_FLTPOL_REG(FTM3)
+#define FTM3_SYNCONF                             FTM_SYNCONF_REG(FTM3)
+#define FTM3_INVCTRL                             FTM_INVCTRL_REG(FTM3)
+#define FTM3_SWOCTRL                             FTM_SWOCTRL_REG(FTM3)
+#define FTM3_PWMLOAD                             FTM_PWMLOAD_REG(FTM3)
+
+/* FTM - Register array accessors */
+#define FTM0_CnSC(index)                         FTM_CnSC_REG(FTM0,index)
+#define FTM1_CnSC(index)                         FTM_CnSC_REG(FTM1,index)
+#define FTM2_CnSC(index)                         FTM_CnSC_REG(FTM2,index)
+#define FTM3_CnSC(index)                         FTM_CnSC_REG(FTM3,index)
+#define FTM0_CnV(index)                          FTM_CnV_REG(FTM0,index)
+#define FTM1_CnV(index)                          FTM_CnV_REG(FTM1,index)
+#define FTM2_CnV(index)                          FTM_CnV_REG(FTM2,index)
+#define FTM3_CnV(index)                          FTM_CnV_REG(FTM3,index)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base)                      ((base)->PDOR)
+#define GPIO_PSOR_REG(base)                      ((base)->PSOR)
+#define GPIO_PCOR_REG(base)                      ((base)->PCOR)
+#define GPIO_PTOR_REG(base)                      ((base)->PTOR)
+#define GPIO_PDIR_REG(base)                      ((base)->PDIR)
+#define GPIO_PDDR_REG(base)                      ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT                      0
+#define GPIO_PDOR_PDO_WIDTH                      32
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT                     0
+#define GPIO_PSOR_PTSO_WIDTH                     32
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT                     0
+#define GPIO_PCOR_PTCO_WIDTH                     32
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT                     0
+#define GPIO_PTOR_PTTO_WIDTH                     32
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT                      0
+#define GPIO_PDIR_PDI_WIDTH                      32
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT                      0
+#define GPIO_PDDR_PDD_WIDTH                      32
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE                                 (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA                                      ((GPIO_Type *)PTA_BASE)
+#define PTA_BASE_PTR                             (PTA)
+/** Peripheral PTB base address */
+#define PTB_BASE                                 (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB                                      ((GPIO_Type *)PTB_BASE)
+#define PTB_BASE_PTR                             (PTB)
+/** Peripheral PTC base address */
+#define PTC_BASE                                 (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC                                      ((GPIO_Type *)PTC_BASE)
+#define PTC_BASE_PTR                             (PTC)
+/** Peripheral PTD base address */
+#define PTD_BASE                                 (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD                                      ((GPIO_Type *)PTD_BASE)
+#define PTD_BASE_PTR                             (PTD)
+/** Peripheral PTE base address */
+#define PTE_BASE                                 (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE                                      ((GPIO_Type *)PTE_BASE)
+#define PTE_BASE_PTR                             (PTE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { PTA, PTB, PTC, PTD, PTE }
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* PTA */
+#define GPIOA_PDOR                               GPIO_PDOR_REG(PTA)
+#define GPIOA_PSOR                               GPIO_PSOR_REG(PTA)
+#define GPIOA_PCOR                               GPIO_PCOR_REG(PTA)
+#define GPIOA_PTOR                               GPIO_PTOR_REG(PTA)
+#define GPIOA_PDIR                               GPIO_PDIR_REG(PTA)
+#define GPIOA_PDDR                               GPIO_PDDR_REG(PTA)
+/* PTB */
+#define GPIOB_PDOR                               GPIO_PDOR_REG(PTB)
+#define GPIOB_PSOR                               GPIO_PSOR_REG(PTB)
+#define GPIOB_PCOR                               GPIO_PCOR_REG(PTB)
+#define GPIOB_PTOR                               GPIO_PTOR_REG(PTB)
+#define GPIOB_PDIR                               GPIO_PDIR_REG(PTB)
+#define GPIOB_PDDR                               GPIO_PDDR_REG(PTB)
+/* PTC */
+#define GPIOC_PDOR                               GPIO_PDOR_REG(PTC)
+#define GPIOC_PSOR                               GPIO_PSOR_REG(PTC)
+#define GPIOC_PCOR                               GPIO_PCOR_REG(PTC)
+#define GPIOC_PTOR                               GPIO_PTOR_REG(PTC)
+#define GPIOC_PDIR                               GPIO_PDIR_REG(PTC)
+#define GPIOC_PDDR                               GPIO_PDDR_REG(PTC)
+/* PTD */
+#define GPIOD_PDOR                               GPIO_PDOR_REG(PTD)
+#define GPIOD_PSOR                               GPIO_PSOR_REG(PTD)
+#define GPIOD_PCOR                               GPIO_PCOR_REG(PTD)
+#define GPIOD_PTOR                               GPIO_PTOR_REG(PTD)
+#define GPIOD_PDIR                               GPIO_PDIR_REG(PTD)
+#define GPIOD_PDDR                               GPIO_PDDR_REG(PTD)
+/* PTE */
+#define GPIOE_PDOR                               GPIO_PDOR_REG(PTE)
+#define GPIOE_PSOR                               GPIO_PSOR_REG(PTE)
+#define GPIOE_PCOR                               GPIO_PCOR_REG(PTE)
+#define GPIOE_PTOR                               GPIO_PTOR_REG(PTE)
+#define GPIOE_PDIR                               GPIO_PDIR_REG(PTE)
+#define GPIOE_PDDR                               GPIO_PDDR_REG(PTE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base)                         ((base)->A1)
+#define I2C_F_REG(base)                          ((base)->F)
+#define I2C_C1_REG(base)                         ((base)->C1)
+#define I2C_S_REG(base)                          ((base)->S)
+#define I2C_D_REG(base)                          ((base)->D)
+#define I2C_C2_REG(base)                         ((base)->C2)
+#define I2C_FLT_REG(base)                        ((base)->FLT)
+#define I2C_RA_REG(base)                         ((base)->RA)
+#define I2C_SMB_REG(base)                        ((base)->SMB)
+#define I2C_A2_REG(base)                         ((base)->A2)
+#define I2C_SLTH_REG(base)                       ((base)->SLTH)
+#define I2C_SLTL_REG(base)                       ((base)->SLTL)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK                           0xFEu
+#define I2C_A1_AD_SHIFT                          1
+#define I2C_A1_AD_WIDTH                          7
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK                           0x3Fu
+#define I2C_F_ICR_SHIFT                          0
+#define I2C_F_ICR_WIDTH                          6
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          0xC0u
+#define I2C_F_MULT_SHIFT                         6
+#define I2C_F_MULT_WIDTH                         2
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK                        0x1u
+#define I2C_C1_DMAEN_SHIFT                       0
+#define I2C_C1_DMAEN_WIDTH                       1
+#define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_DMAEN_SHIFT))&I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK                         0x2u
+#define I2C_C1_WUEN_SHIFT                        1
+#define I2C_C1_WUEN_WIDTH                        1
+#define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_WUEN_SHIFT))&I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK                         0x4u
+#define I2C_C1_RSTA_SHIFT                        2
+#define I2C_C1_RSTA_WIDTH                        1
+#define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_RSTA_SHIFT))&I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK                         0x8u
+#define I2C_C1_TXAK_SHIFT                        3
+#define I2C_C1_TXAK_WIDTH                        1
+#define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_TXAK_SHIFT))&I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK                           0x10u
+#define I2C_C1_TX_SHIFT                          4
+#define I2C_C1_TX_WIDTH                          1
+#define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C1_TX_SHIFT))&I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK                          0x20u
+#define I2C_C1_MST_SHIFT                         5
+#define I2C_C1_MST_WIDTH                         1
+#define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_C1_MST_SHIFT))&I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK                        0x40u
+#define I2C_C1_IICIE_SHIFT                       6
+#define I2C_C1_IICIE_WIDTH                       1
+#define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICIE_SHIFT))&I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK                        0x80u
+#define I2C_C1_IICEN_SHIFT                       7
+#define I2C_C1_IICEN_WIDTH                       1
+#define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICEN_SHIFT))&I2C_C1_IICEN_MASK)
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK                          0x1u
+#define I2C_S_RXAK_SHIFT                         0
+#define I2C_S_RXAK_WIDTH                         1
+#define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_RXAK_SHIFT))&I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK                         0x2u
+#define I2C_S_IICIF_SHIFT                        1
+#define I2C_S_IICIF_WIDTH                        1
+#define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_S_IICIF_SHIFT))&I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK                           0x4u
+#define I2C_S_SRW_SHIFT                          2
+#define I2C_S_SRW_WIDTH                          1
+#define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_SRW_SHIFT))&I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK                           0x8u
+#define I2C_S_RAM_SHIFT                          3
+#define I2C_S_RAM_WIDTH                          1
+#define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_RAM_SHIFT))&I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK                          0x10u
+#define I2C_S_ARBL_SHIFT                         4
+#define I2C_S_ARBL_WIDTH                         1
+#define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_ARBL_SHIFT))&I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK                          0x20u
+#define I2C_S_BUSY_SHIFT                         5
+#define I2C_S_BUSY_WIDTH                         1
+#define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_BUSY_SHIFT))&I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK                          0x40u
+#define I2C_S_IAAS_SHIFT                         6
+#define I2C_S_IAAS_WIDTH                         1
+#define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_IAAS_SHIFT))&I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK                           0x80u
+#define I2C_S_TCF_SHIFT                          7
+#define I2C_S_TCF_WIDTH                          1
+#define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_TCF_SHIFT))&I2C_S_TCF_MASK)
+/* D Bit Fields */
+#define I2C_D_DATA_MASK                          0xFFu
+#define I2C_D_DATA_SHIFT                         0
+#define I2C_D_DATA_WIDTH                         8
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK                           0x7u
+#define I2C_C2_AD_SHIFT                          0
+#define I2C_C2_AD_WIDTH                          3
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         0x8u
+#define I2C_C2_RMEN_SHIFT                        3
+#define I2C_C2_RMEN_WIDTH                        1
+#define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_RMEN_SHIFT))&I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK                         0x10u
+#define I2C_C2_SBRC_SHIFT                        4
+#define I2C_C2_SBRC_WIDTH                        1
+#define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_SBRC_SHIFT))&I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK                         0x20u
+#define I2C_C2_HDRS_SHIFT                        5
+#define I2C_C2_HDRS_WIDTH                        1
+#define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_HDRS_SHIFT))&I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK                        0x40u
+#define I2C_C2_ADEXT_SHIFT                       6
+#define I2C_C2_ADEXT_WIDTH                       1
+#define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_ADEXT_SHIFT))&I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK                        0x80u
+#define I2C_C2_GCAEN_SHIFT                       7
+#define I2C_C2_GCAEN_WIDTH                       1
+#define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_GCAEN_SHIFT))&I2C_C2_GCAEN_MASK)
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK                         0xFu
+#define I2C_FLT_FLT_SHIFT                        0
+#define I2C_FLT_FLT_WIDTH                        4
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK                      0x10u
+#define I2C_FLT_STARTF_SHIFT                     4
+#define I2C_FLT_STARTF_WIDTH                     1
+#define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STARTF_SHIFT))&I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK                        0x20u
+#define I2C_FLT_SSIE_SHIFT                       5
+#define I2C_FLT_SSIE_WIDTH                       1
+#define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SSIE_SHIFT))&I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK                       0x40u
+#define I2C_FLT_STOPF_SHIFT                      6
+#define I2C_FLT_STOPF_WIDTH                      1
+#define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STOPF_SHIFT))&I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK                        0x80u
+#define I2C_FLT_SHEN_SHIFT                       7
+#define I2C_FLT_SHEN_WIDTH                       1
+#define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SHEN_SHIFT))&I2C_FLT_SHEN_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK                          0xFEu
+#define I2C_RA_RAD_SHIFT                         1
+#define I2C_RA_RAD_WIDTH                         7
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK                     0x1u
+#define I2C_SMB_SHTF2IE_SHIFT                    0
+#define I2C_SMB_SHTF2IE_WIDTH                    1
+#define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2IE_SHIFT))&I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK                       0x2u
+#define I2C_SMB_SHTF2_SHIFT                      1
+#define I2C_SMB_SHTF2_WIDTH                      1
+#define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2_SHIFT))&I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK                       0x4u
+#define I2C_SMB_SHTF1_SHIFT                      2
+#define I2C_SMB_SHTF1_WIDTH                      1
+#define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF1_SHIFT))&I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK                        0x8u
+#define I2C_SMB_SLTF_SHIFT                       3
+#define I2C_SMB_SLTF_WIDTH                       1
+#define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SLTF_SHIFT))&I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK                      0x10u
+#define I2C_SMB_TCKSEL_SHIFT                     4
+#define I2C_SMB_TCKSEL_WIDTH                     1
+#define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_SMB_TCKSEL_SHIFT))&I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK                     0x20u
+#define I2C_SMB_SIICAEN_SHIFT                    5
+#define I2C_SMB_SIICAEN_WIDTH                    1
+#define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SIICAEN_SHIFT))&I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK                     0x40u
+#define I2C_SMB_ALERTEN_SHIFT                    6
+#define I2C_SMB_ALERTEN_WIDTH                    1
+#define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_ALERTEN_SHIFT))&I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK                        0x80u
+#define I2C_SMB_FACK_SHIFT                       7
+#define I2C_SMB_FACK_WIDTH                       1
+#define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_FACK_SHIFT))&I2C_SMB_FACK_MASK)
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK                          0xFEu
+#define I2C_A2_SAD_SHIFT                         1
+#define I2C_A2_SAD_WIDTH                         7
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK                       0xFFu
+#define I2C_SLTH_SSLT_SHIFT                      0
+#define I2C_SLTH_SSLT_WIDTH                      8
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK                       0xFFu
+#define I2C_SLTL_SSLT_SHIFT                      0
+#define I2C_SLTL_SSLT_WIDTH                      8
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR                            (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR                            (I2C1)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x400E6000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+#define I2C2_BASE_PTR                            (I2C2)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1                                  I2C_A1_REG(I2C0)
+#define I2C0_F                                   I2C_F_REG(I2C0)
+#define I2C0_C1                                  I2C_C1_REG(I2C0)
+#define I2C0_S                                   I2C_S_REG(I2C0)
+#define I2C0_D                                   I2C_D_REG(I2C0)
+#define I2C0_C2                                  I2C_C2_REG(I2C0)
+#define I2C0_FLT                                 I2C_FLT_REG(I2C0)
+#define I2C0_RA                                  I2C_RA_REG(I2C0)
+#define I2C0_SMB                                 I2C_SMB_REG(I2C0)
+#define I2C0_A2                                  I2C_A2_REG(I2C0)
+#define I2C0_SLTH                                I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL                                I2C_SLTL_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1                                  I2C_A1_REG(I2C1)
+#define I2C1_F                                   I2C_F_REG(I2C1)
+#define I2C1_C1                                  I2C_C1_REG(I2C1)
+#define I2C1_S                                   I2C_S_REG(I2C1)
+#define I2C1_D                                   I2C_D_REG(I2C1)
+#define I2C1_C2                                  I2C_C2_REG(I2C1)
+#define I2C1_FLT                                 I2C_FLT_REG(I2C1)
+#define I2C1_RA                                  I2C_RA_REG(I2C1)
+#define I2C1_SMB                                 I2C_SMB_REG(I2C1)
+#define I2C1_A2                                  I2C_A2_REG(I2C1)
+#define I2C1_SLTH                                I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL                                I2C_SLTL_REG(I2C1)
+/* I2C2 */
+#define I2C2_A1                                  I2C_A1_REG(I2C2)
+#define I2C2_F                                   I2C_F_REG(I2C2)
+#define I2C2_C1                                  I2C_C1_REG(I2C2)
+#define I2C2_S                                   I2C_S_REG(I2C2)
+#define I2C2_D                                   I2C_D_REG(I2C2)
+#define I2C2_C2                                  I2C_C2_REG(I2C2)
+#define I2C2_FLT                                 I2C_FLT_REG(I2C2)
+#define I2C2_RA                                  I2C_RA_REG(I2C2)
+#define I2C2_SMB                                 I2C_SMB_REG(I2C2)
+#define I2C2_A2                                  I2C_A2_REG(I2C2)
+#define I2C2_SLTH                                I2C_SLTH_REG(I2C2)
+#define I2C2_SLTL                                I2C_SLTL_REG(I2C2)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
+  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t TDR[2];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __I  uint32_t TFR[2];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_3[28];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
+  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t RDR[2];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[24];
+  __I  uint32_t RFR[2];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_6[24];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
+  __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base)                       ((base)->TCSR)
+#define I2S_TCR1_REG(base)                       ((base)->TCR1)
+#define I2S_TCR2_REG(base)                       ((base)->TCR2)
+#define I2S_TCR3_REG(base)                       ((base)->TCR3)
+#define I2S_TCR4_REG(base)                       ((base)->TCR4)
+#define I2S_TCR5_REG(base)                       ((base)->TCR5)
+#define I2S_TDR_REG(base,index)                  ((base)->TDR[index])
+#define I2S_TDR_COUNT                            2
+#define I2S_TFR_REG(base,index)                  ((base)->TFR[index])
+#define I2S_TFR_COUNT                            2
+#define I2S_TMR_REG(base)                        ((base)->TMR)
+#define I2S_RCSR_REG(base)                       ((base)->RCSR)
+#define I2S_RCR1_REG(base)                       ((base)->RCR1)
+#define I2S_RCR2_REG(base)                       ((base)->RCR2)
+#define I2S_RCR3_REG(base)                       ((base)->RCR3)
+#define I2S_RCR4_REG(base)                       ((base)->RCR4)
+#define I2S_RCR5_REG(base)                       ((base)->RCR5)
+#define I2S_RDR_REG(base,index)                  ((base)->RDR[index])
+#define I2S_RDR_COUNT                            2
+#define I2S_RFR_REG(base,index)                  ((base)->RFR[index])
+#define I2S_RFR_COUNT                            2
+#define I2S_RMR_REG(base)                        ((base)->RMR)
+#define I2S_MCR_REG(base)                        ((base)->MCR)
+#define I2S_MDR_REG(base)                        ((base)->MDR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK                       0x1u
+#define I2S_TCSR_FRDE_SHIFT                      0
+#define I2S_TCSR_FRDE_WIDTH                      1
+#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRDE_SHIFT))&I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK                       0x2u
+#define I2S_TCSR_FWDE_SHIFT                      1
+#define I2S_TCSR_FWDE_WIDTH                      1
+#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK                       0x100u
+#define I2S_TCSR_FRIE_SHIFT                      8
+#define I2S_TCSR_FRIE_WIDTH                      1
+#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRIE_SHIFT))&I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK                       0x200u
+#define I2S_TCSR_FWIE_SHIFT                      9
+#define I2S_TCSR_FWIE_WIDTH                      1
+#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK                       0x400u
+#define I2S_TCSR_FEIE_SHIFT                      10
+#define I2S_TCSR_FEIE_WIDTH                      1
+#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK                       0x800u
+#define I2S_TCSR_SEIE_SHIFT                      11
+#define I2S_TCSR_SEIE_WIDTH                      1
+#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK                       0x1000u
+#define I2S_TCSR_WSIE_SHIFT                      12
+#define I2S_TCSR_WSIE_WIDTH                      1
+#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK                        0x10000u
+#define I2S_TCSR_FRF_SHIFT                       16
+#define I2S_TCSR_FRF_WIDTH                       1
+#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRF_SHIFT))&I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK                        0x20000u
+#define I2S_TCSR_FWF_SHIFT                       17
+#define I2S_TCSR_FWF_WIDTH                       1
+#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK                        0x40000u
+#define I2S_TCSR_FEF_SHIFT                       18
+#define I2S_TCSR_FEF_WIDTH                       1
+#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK                        0x80000u
+#define I2S_TCSR_SEF_SHIFT                       19
+#define I2S_TCSR_SEF_WIDTH                       1
+#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK                        0x100000u
+#define I2S_TCSR_WSF_SHIFT                       20
+#define I2S_TCSR_WSF_WIDTH                       1
+#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK                         0x1000000u
+#define I2S_TCSR_SR_SHIFT                        24
+#define I2S_TCSR_SR_WIDTH                        1
+#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK                         0x2000000u
+#define I2S_TCSR_FR_SHIFT                        25
+#define I2S_TCSR_FR_WIDTH                        1
+#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK                        0x10000000u
+#define I2S_TCSR_BCE_SHIFT                       28
+#define I2S_TCSR_BCE_WIDTH                       1
+#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK                       0x20000000u
+#define I2S_TCSR_DBGE_SHIFT                      29
+#define I2S_TCSR_DBGE_WIDTH                      1
+#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK                      0x40000000u
+#define I2S_TCSR_STOPE_SHIFT                     30
+#define I2S_TCSR_STOPE_WIDTH                     1
+#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK                         0x80000000u
+#define I2S_TCSR_TE_SHIFT                        31
+#define I2S_TCSR_TE_WIDTH                        1
+#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK                        0x7u
+#define I2S_TCR1_TFW_SHIFT                       0
+#define I2S_TCR1_TFW_WIDTH                       3
+#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK                        0xFFu
+#define I2S_TCR2_DIV_SHIFT                       0
+#define I2S_TCR2_DIV_WIDTH                       8
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        0x1000000u
+#define I2S_TCR2_BCD_SHIFT                       24
+#define I2S_TCR2_BCD_WIDTH                       1
+#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK                        0x2000000u
+#define I2S_TCR2_BCP_SHIFT                       25
+#define I2S_TCR2_BCP_WIDTH                       1
+#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK                       0xC000000u
+#define I2S_TCR2_MSEL_SHIFT                      26
+#define I2S_TCR2_MSEL_WIDTH                      2
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK                        0x10000000u
+#define I2S_TCR2_BCI_SHIFT                       28
+#define I2S_TCR2_BCI_WIDTH                       1
+#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK                        0x20000000u
+#define I2S_TCR2_BCS_SHIFT                       29
+#define I2S_TCR2_BCS_WIDTH                       1
+#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK                       0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT                      30
+#define I2S_TCR2_SYNC_WIDTH                      2
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK                       0x1Fu
+#define I2S_TCR3_WDFL_SHIFT                      0
+#define I2S_TCR3_WDFL_WIDTH                      5
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        0x30000u
+#define I2S_TCR3_TCE_SHIFT                       16
+#define I2S_TCR3_TCE_WIDTH                       2
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK                        0x1u
+#define I2S_TCR4_FSD_SHIFT                       0
+#define I2S_TCR4_FSD_WIDTH                       1
+#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK                        0x2u
+#define I2S_TCR4_FSP_SHIFT                       1
+#define I2S_TCR4_FSP_WIDTH                       1
+#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSE_MASK                        0x8u
+#define I2S_TCR4_FSE_SHIFT                       3
+#define I2S_TCR4_FSE_WIDTH                       1
+#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK                         0x10u
+#define I2S_TCR4_MF_SHIFT                        4
+#define I2S_TCR4_MF_WIDTH                        1
+#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK                       0x1F00u
+#define I2S_TCR4_SYWD_SHIFT                      8
+#define I2S_TCR4_SYWD_WIDTH                      5
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT                      16
+#define I2S_TCR4_FRSZ_WIDTH                      5
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK                        0x1F00u
+#define I2S_TCR5_FBT_SHIFT                       8
+#define I2S_TCR5_FBT_WIDTH                       5
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        0x1F0000u
+#define I2S_TCR5_W0W_SHIFT                       16
+#define I2S_TCR5_W0W_WIDTH                       5
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        0x1F000000u
+#define I2S_TCR5_WNW_SHIFT                       24
+#define I2S_TCR5_WNW_WIDTH                       5
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT                        0
+#define I2S_TDR_TDR_WIDTH                        32
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK                         0xFu
+#define I2S_TFR_RFP_SHIFT                        0
+#define I2S_TFR_RFP_WIDTH                        4
+#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK                         0xF0000u
+#define I2S_TFR_WFP_SHIFT                        16
+#define I2S_TFR_WFP_WIDTH                        4
+#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK                         0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT                        0
+#define I2S_TMR_TWM_WIDTH                        32
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK                       0x1u
+#define I2S_RCSR_FRDE_SHIFT                      0
+#define I2S_RCSR_FRDE_WIDTH                      1
+#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRDE_SHIFT))&I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK                       0x2u
+#define I2S_RCSR_FWDE_SHIFT                      1
+#define I2S_RCSR_FWDE_WIDTH                      1
+#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK                       0x100u
+#define I2S_RCSR_FRIE_SHIFT                      8
+#define I2S_RCSR_FRIE_WIDTH                      1
+#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRIE_SHIFT))&I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK                       0x200u
+#define I2S_RCSR_FWIE_SHIFT                      9
+#define I2S_RCSR_FWIE_WIDTH                      1
+#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK                       0x400u
+#define I2S_RCSR_FEIE_SHIFT                      10
+#define I2S_RCSR_FEIE_WIDTH                      1
+#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK                       0x800u
+#define I2S_RCSR_SEIE_SHIFT                      11
+#define I2S_RCSR_SEIE_WIDTH                      1
+#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK                       0x1000u
+#define I2S_RCSR_WSIE_SHIFT                      12
+#define I2S_RCSR_WSIE_WIDTH                      1
+#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK                        0x10000u
+#define I2S_RCSR_FRF_SHIFT                       16
+#define I2S_RCSR_FRF_WIDTH                       1
+#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRF_SHIFT))&I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK                        0x20000u
+#define I2S_RCSR_FWF_SHIFT                       17
+#define I2S_RCSR_FWF_WIDTH                       1
+#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK                        0x40000u
+#define I2S_RCSR_FEF_SHIFT                       18
+#define I2S_RCSR_FEF_WIDTH                       1
+#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK                        0x80000u
+#define I2S_RCSR_SEF_SHIFT                       19
+#define I2S_RCSR_SEF_WIDTH                       1
+#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK                        0x100000u
+#define I2S_RCSR_WSF_SHIFT                       20
+#define I2S_RCSR_WSF_WIDTH                       1
+#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK                         0x1000000u
+#define I2S_RCSR_SR_SHIFT                        24
+#define I2S_RCSR_SR_WIDTH                        1
+#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK                         0x2000000u
+#define I2S_RCSR_FR_SHIFT                        25
+#define I2S_RCSR_FR_WIDTH                        1
+#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK                        0x10000000u
+#define I2S_RCSR_BCE_SHIFT                       28
+#define I2S_RCSR_BCE_WIDTH                       1
+#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK                       0x20000000u
+#define I2S_RCSR_DBGE_SHIFT                      29
+#define I2S_RCSR_DBGE_WIDTH                      1
+#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK                      0x40000000u
+#define I2S_RCSR_STOPE_SHIFT                     30
+#define I2S_RCSR_STOPE_WIDTH                     1
+#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK                         0x80000000u
+#define I2S_RCSR_RE_SHIFT                        31
+#define I2S_RCSR_RE_WIDTH                        1
+#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK                        0x7u
+#define I2S_RCR1_RFW_SHIFT                       0
+#define I2S_RCR1_RFW_WIDTH                       3
+#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK                        0xFFu
+#define I2S_RCR2_DIV_SHIFT                       0
+#define I2S_RCR2_DIV_WIDTH                       8
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        0x1000000u
+#define I2S_RCR2_BCD_SHIFT                       24
+#define I2S_RCR2_BCD_WIDTH                       1
+#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK                        0x2000000u
+#define I2S_RCR2_BCP_SHIFT                       25
+#define I2S_RCR2_BCP_WIDTH                       1
+#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK                       0xC000000u
+#define I2S_RCR2_MSEL_SHIFT                      26
+#define I2S_RCR2_MSEL_WIDTH                      2
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK                        0x10000000u
+#define I2S_RCR2_BCI_SHIFT                       28
+#define I2S_RCR2_BCI_WIDTH                       1
+#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK                        0x20000000u
+#define I2S_RCR2_BCS_SHIFT                       29
+#define I2S_RCR2_BCS_WIDTH                       1
+#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK                       0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT                      30
+#define I2S_RCR2_SYNC_WIDTH                      2
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK                       0x1Fu
+#define I2S_RCR3_WDFL_SHIFT                      0
+#define I2S_RCR3_WDFL_WIDTH                      5
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        0x30000u
+#define I2S_RCR3_RCE_SHIFT                       16
+#define I2S_RCR3_RCE_WIDTH                       2
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK                        0x1u
+#define I2S_RCR4_FSD_SHIFT                       0
+#define I2S_RCR4_FSD_WIDTH                       1
+#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK                        0x2u
+#define I2S_RCR4_FSP_SHIFT                       1
+#define I2S_RCR4_FSP_WIDTH                       1
+#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSE_MASK                        0x8u
+#define I2S_RCR4_FSE_SHIFT                       3
+#define I2S_RCR4_FSE_WIDTH                       1
+#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK                         0x10u
+#define I2S_RCR4_MF_SHIFT                        4
+#define I2S_RCR4_MF_WIDTH                        1
+#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK                       0x1F00u
+#define I2S_RCR4_SYWD_SHIFT                      8
+#define I2S_RCR4_SYWD_WIDTH                      5
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT                      16
+#define I2S_RCR4_FRSZ_WIDTH                      5
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK                        0x1F00u
+#define I2S_RCR5_FBT_SHIFT                       8
+#define I2S_RCR5_FBT_WIDTH                       5
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        0x1F0000u
+#define I2S_RCR5_W0W_SHIFT                       16
+#define I2S_RCR5_W0W_WIDTH                       5
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        0x1F000000u
+#define I2S_RCR5_WNW_SHIFT                       24
+#define I2S_RCR5_WNW_WIDTH                       5
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT                        0
+#define I2S_RDR_RDR_WIDTH                        32
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK                         0xFu
+#define I2S_RFR_RFP_SHIFT                        0
+#define I2S_RFR_RFP_WIDTH                        4
+#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK                         0xF0000u
+#define I2S_RFR_WFP_SHIFT                        16
+#define I2S_RFR_WFP_WIDTH                        4
+#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK                         0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT                        0
+#define I2S_RMR_RWM_WIDTH                        32
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK                        0x3000000u
+#define I2S_MCR_MICS_SHIFT                       24
+#define I2S_MCR_MICS_WIDTH                       2
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK                         0x40000000u
+#define I2S_MCR_MOE_SHIFT                        30
+#define I2S_MCR_MOE_WIDTH                        1
+#define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MOE_SHIFT))&I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK                         0x80000000u
+#define I2S_MCR_DUF_SHIFT                        31
+#define I2S_MCR_DUF_WIDTH                        1
+#define I2S_MCR_DUF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_DUF_SHIFT))&I2S_MCR_DUF_MASK)
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK                      0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT                     0
+#define I2S_MDR_DIVIDE_WIDTH                     12
+#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK                       0xFF000u
+#define I2S_MDR_FRACT_SHIFT                      12
+#define I2S_MDR_FRACT_WIDTH                      8
+#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR                            (I2S0)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS                              { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS                              { I2S0_Tx_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR                                I2S_TCSR_REG(I2S0)
+#define I2S0_TCR1                                I2S_TCR1_REG(I2S0)
+#define I2S0_TCR2                                I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3                                I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4                                I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5                                I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0                                I2S_TDR_REG(I2S0,0)
+#define I2S0_TDR1                                I2S_TDR_REG(I2S0,1)
+#define I2S0_TFR0                                I2S_TFR_REG(I2S0,0)
+#define I2S0_TFR1                                I2S_TFR_REG(I2S0,1)
+#define I2S0_TMR                                 I2S_TMR_REG(I2S0)
+#define I2S0_RCSR                                I2S_RCSR_REG(I2S0)
+#define I2S0_RCR1                                I2S_RCR1_REG(I2S0)
+#define I2S0_RCR2                                I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3                                I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4                                I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5                                I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0                                I2S_RDR_REG(I2S0,0)
+#define I2S0_RDR1                                I2S_RDR_REG(I2S0,1)
+#define I2S0_RFR0                                I2S_RFR_REG(I2S0,0)
+#define I2S0_RFR1                                I2S_RFR_REG(I2S0,1)
+#define I2S0_RMR                                 I2S_RMR_REG(I2S0)
+#define I2S0_MCR                                 I2S_MCR_REG(I2S0)
+#define I2S0_MDR                                 I2S_MDR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index)                          I2S_TDR_REG(I2S0,index)
+#define I2S0_TFR(index)                          I2S_TFR_REG(I2S0,index)
+#define I2S0_RDR(index)                          I2S_RDR_REG(I2S0,index)
+#define I2S0_RFR(index)                          I2S_RFR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
+  __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
+  __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
+  __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
+  __IO uint8_t RST;                                /**< LLWU Reset Enable register, offset: 0xA */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base)                       ((base)->PE1)
+#define LLWU_PE2_REG(base)                       ((base)->PE2)
+#define LLWU_PE3_REG(base)                       ((base)->PE3)
+#define LLWU_PE4_REG(base)                       ((base)->PE4)
+#define LLWU_ME_REG(base)                        ((base)->ME)
+#define LLWU_F1_REG(base)                        ((base)->F1)
+#define LLWU_F2_REG(base)                        ((base)->F2)
+#define LLWU_F3_REG(base)                        ((base)->F3)
+#define LLWU_FILT1_REG(base)                     ((base)->FILT1)
+#define LLWU_FILT2_REG(base)                     ((base)->FILT2)
+#define LLWU_RST_REG(base)                       ((base)->RST)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK                      0x3u
+#define LLWU_PE1_WUPE0_SHIFT                     0
+#define LLWU_PE1_WUPE0_WIDTH                     2
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      0xCu
+#define LLWU_PE1_WUPE1_SHIFT                     2
+#define LLWU_PE1_WUPE1_WIDTH                     2
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      0x30u
+#define LLWU_PE1_WUPE2_SHIFT                     4
+#define LLWU_PE1_WUPE2_WIDTH                     2
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      0xC0u
+#define LLWU_PE1_WUPE3_SHIFT                     6
+#define LLWU_PE1_WUPE3_WIDTH                     2
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK                      0x3u
+#define LLWU_PE2_WUPE4_SHIFT                     0
+#define LLWU_PE2_WUPE4_WIDTH                     2
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      0xCu
+#define LLWU_PE2_WUPE5_SHIFT                     2
+#define LLWU_PE2_WUPE5_WIDTH                     2
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      0x30u
+#define LLWU_PE2_WUPE6_SHIFT                     4
+#define LLWU_PE2_WUPE6_WIDTH                     2
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      0xC0u
+#define LLWU_PE2_WUPE7_SHIFT                     6
+#define LLWU_PE2_WUPE7_WIDTH                     2
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK                      0x3u
+#define LLWU_PE3_WUPE8_SHIFT                     0
+#define LLWU_PE3_WUPE8_WIDTH                     2
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      0xCu
+#define LLWU_PE3_WUPE9_SHIFT                     2
+#define LLWU_PE3_WUPE9_WIDTH                     2
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     0x30u
+#define LLWU_PE3_WUPE10_SHIFT                    4
+#define LLWU_PE3_WUPE10_WIDTH                    2
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     0xC0u
+#define LLWU_PE3_WUPE11_SHIFT                    6
+#define LLWU_PE3_WUPE11_WIDTH                    2
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK                     0x3u
+#define LLWU_PE4_WUPE12_SHIFT                    0
+#define LLWU_PE4_WUPE12_WIDTH                    2
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     0xCu
+#define LLWU_PE4_WUPE13_SHIFT                    2
+#define LLWU_PE4_WUPE13_WIDTH                    2
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     0x30u
+#define LLWU_PE4_WUPE14_SHIFT                    4
+#define LLWU_PE4_WUPE14_WIDTH                    2
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     0xC0u
+#define LLWU_PE4_WUPE15_SHIFT                    6
+#define LLWU_PE4_WUPE15_WIDTH                    2
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK                       0x1u
+#define LLWU_ME_WUME0_SHIFT                      0
+#define LLWU_ME_WUME0_WIDTH                      1
+#define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK                       0x2u
+#define LLWU_ME_WUME1_SHIFT                      1
+#define LLWU_ME_WUME1_WIDTH                      1
+#define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK                       0x4u
+#define LLWU_ME_WUME2_SHIFT                      2
+#define LLWU_ME_WUME2_WIDTH                      1
+#define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK                       0x8u
+#define LLWU_ME_WUME3_SHIFT                      3
+#define LLWU_ME_WUME3_WIDTH                      1
+#define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK                       0x10u
+#define LLWU_ME_WUME4_SHIFT                      4
+#define LLWU_ME_WUME4_WIDTH                      1
+#define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK                       0x20u
+#define LLWU_ME_WUME5_SHIFT                      5
+#define LLWU_ME_WUME5_WIDTH                      1
+#define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK                       0x40u
+#define LLWU_ME_WUME6_SHIFT                      6
+#define LLWU_ME_WUME6_WIDTH                      1
+#define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK                       0x80u
+#define LLWU_ME_WUME7_SHIFT                      7
+#define LLWU_ME_WUME7_WIDTH                      1
+#define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK                        0x1u
+#define LLWU_F1_WUF0_SHIFT                       0
+#define LLWU_F1_WUF0_WIDTH                       1
+#define LLWU_F1_WUF0(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF0_SHIFT))&LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK                        0x2u
+#define LLWU_F1_WUF1_SHIFT                       1
+#define LLWU_F1_WUF1_WIDTH                       1
+#define LLWU_F1_WUF1(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF1_SHIFT))&LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK                        0x4u
+#define LLWU_F1_WUF2_SHIFT                       2
+#define LLWU_F1_WUF2_WIDTH                       1
+#define LLWU_F1_WUF2(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF2_SHIFT))&LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK                        0x8u
+#define LLWU_F1_WUF3_SHIFT                       3
+#define LLWU_F1_WUF3_WIDTH                       1
+#define LLWU_F1_WUF3(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF3_SHIFT))&LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK                        0x10u
+#define LLWU_F1_WUF4_SHIFT                       4
+#define LLWU_F1_WUF4_WIDTH                       1
+#define LLWU_F1_WUF4(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF4_SHIFT))&LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK                        0x20u
+#define LLWU_F1_WUF5_SHIFT                       5
+#define LLWU_F1_WUF5_WIDTH                       1
+#define LLWU_F1_WUF5(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF5_SHIFT))&LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK                        0x40u
+#define LLWU_F1_WUF6_SHIFT                       6
+#define LLWU_F1_WUF6_WIDTH                       1
+#define LLWU_F1_WUF6(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF6_SHIFT))&LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK                        0x80u
+#define LLWU_F1_WUF7_SHIFT                       7
+#define LLWU_F1_WUF7_WIDTH                       1
+#define LLWU_F1_WUF7(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF7_SHIFT))&LLWU_F1_WUF7_MASK)
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK                        0x1u
+#define LLWU_F2_WUF8_SHIFT                       0
+#define LLWU_F2_WUF8_WIDTH                       1
+#define LLWU_F2_WUF8(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF8_SHIFT))&LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK                        0x2u
+#define LLWU_F2_WUF9_SHIFT                       1
+#define LLWU_F2_WUF9_WIDTH                       1
+#define LLWU_F2_WUF9(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF9_SHIFT))&LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK                       0x4u
+#define LLWU_F2_WUF10_SHIFT                      2
+#define LLWU_F2_WUF10_WIDTH                      1
+#define LLWU_F2_WUF10(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF10_SHIFT))&LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK                       0x8u
+#define LLWU_F2_WUF11_SHIFT                      3
+#define LLWU_F2_WUF11_WIDTH                      1
+#define LLWU_F2_WUF11(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF11_SHIFT))&LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK                       0x10u
+#define LLWU_F2_WUF12_SHIFT                      4
+#define LLWU_F2_WUF12_WIDTH                      1
+#define LLWU_F2_WUF12(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF12_SHIFT))&LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK                       0x20u
+#define LLWU_F2_WUF13_SHIFT                      5
+#define LLWU_F2_WUF13_WIDTH                      1
+#define LLWU_F2_WUF13(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF13_SHIFT))&LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK                       0x40u
+#define LLWU_F2_WUF14_SHIFT                      6
+#define LLWU_F2_WUF14_WIDTH                      1
+#define LLWU_F2_WUF14(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF14_SHIFT))&LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK                       0x80u
+#define LLWU_F2_WUF15_SHIFT                      7
+#define LLWU_F2_WUF15_WIDTH                      1
+#define LLWU_F2_WUF15(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF15_SHIFT))&LLWU_F2_WUF15_MASK)
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK                       0x1u
+#define LLWU_F3_MWUF0_SHIFT                      0
+#define LLWU_F3_MWUF0_WIDTH                      1
+#define LLWU_F3_MWUF0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF0_SHIFT))&LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK                       0x2u
+#define LLWU_F3_MWUF1_SHIFT                      1
+#define LLWU_F3_MWUF1_WIDTH                      1
+#define LLWU_F3_MWUF1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF1_SHIFT))&LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK                       0x4u
+#define LLWU_F3_MWUF2_SHIFT                      2
+#define LLWU_F3_MWUF2_WIDTH                      1
+#define LLWU_F3_MWUF2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF2_SHIFT))&LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK                       0x8u
+#define LLWU_F3_MWUF3_SHIFT                      3
+#define LLWU_F3_MWUF3_WIDTH                      1
+#define LLWU_F3_MWUF3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF3_SHIFT))&LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK                       0x10u
+#define LLWU_F3_MWUF4_SHIFT                      4
+#define LLWU_F3_MWUF4_WIDTH                      1
+#define LLWU_F3_MWUF4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF4_SHIFT))&LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK                       0x20u
+#define LLWU_F3_MWUF5_SHIFT                      5
+#define LLWU_F3_MWUF5_WIDTH                      1
+#define LLWU_F3_MWUF5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF5_SHIFT))&LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK                       0x40u
+#define LLWU_F3_MWUF6_SHIFT                      6
+#define LLWU_F3_MWUF6_WIDTH                      1
+#define LLWU_F3_MWUF6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF6_SHIFT))&LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK                       0x80u
+#define LLWU_F3_MWUF7_SHIFT                      7
+#define LLWU_F3_MWUF7_WIDTH                      1
+#define LLWU_F3_MWUF7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF7_SHIFT))&LLWU_F3_MWUF7_MASK)
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK                  0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT                 0
+#define LLWU_FILT1_FILTSEL_WIDTH                 4
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    0x60u
+#define LLWU_FILT1_FILTE_SHIFT                   5
+#define LLWU_FILT1_FILTE_WIDTH                   2
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK                    0x80u
+#define LLWU_FILT1_FILTF_SHIFT                   7
+#define LLWU_FILT1_FILTF_WIDTH                   1
+#define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK                  0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT                 0
+#define LLWU_FILT2_FILTSEL_WIDTH                 4
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    0x60u
+#define LLWU_FILT2_FILTE_SHIFT                   5
+#define LLWU_FILT2_FILTE_WIDTH                   2
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK                    0x80u
+#define LLWU_FILT2_FILTF_SHIFT                   7
+#define LLWU_FILT2_FILTF_WIDTH                   1
+#define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK                    0x1u
+#define LLWU_RST_RSTFILT_SHIFT                   0
+#define LLWU_RST_RSTFILT_WIDTH                   1
+#define LLWU_RST_RSTFILT(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_RST_RSTFILT_SHIFT))&LLWU_RST_RSTFILT_MASK)
+#define LLWU_RST_LLRSTE_MASK                     0x2u
+#define LLWU_RST_LLRSTE_SHIFT                    1
+#define LLWU_RST_LLRSTE_WIDTH                    1
+#define LLWU_RST_LLRSTE(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_RST_LLRSTE_SHIFT))&LLWU_RST_LLRSTE_MASK)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR                            (LLWU)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1                                 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2                                 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3                                 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4                                 LLWU_PE4_REG(LLWU)
+#define LLWU_ME                                  LLWU_ME_REG(LLWU)
+#define LLWU_F1                                  LLWU_F1_REG(LLWU)
+#define LLWU_F2                                  LLWU_F2_REG(LLWU)
+#define LLWU_F3                                  LLWU_F3_REG(LLWU)
+#define LLWU_FILT1                               LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2                               LLWU_FILT2_REG(LLWU)
+#define LLWU_RST                                 LLWU_RST_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base)                      ((base)->CSR)
+#define LPTMR_PSR_REG(base)                      ((base)->PSR)
+#define LPTMR_CMR_REG(base)                      ((base)->CMR)
+#define LPTMR_CNR_REG(base)                      ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK                       0x1u
+#define LPTMR_CSR_TEN_SHIFT                      0
+#define LPTMR_CSR_TEN_WIDTH                      1
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK                       0x2u
+#define LPTMR_CSR_TMS_SHIFT                      1
+#define LPTMR_CSR_TMS_WIDTH                      1
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK                       0x4u
+#define LPTMR_CSR_TFC_SHIFT                      2
+#define LPTMR_CSR_TFC_WIDTH                      1
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK                       0x8u
+#define LPTMR_CSR_TPP_SHIFT                      3
+#define LPTMR_CSR_TPP_WIDTH                      1
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK                       0x30u
+#define LPTMR_CSR_TPS_SHIFT                      4
+#define LPTMR_CSR_TPS_WIDTH                      2
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       0x40u
+#define LPTMR_CSR_TIE_SHIFT                      6
+#define LPTMR_CSR_TIE_WIDTH                      1
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK                       0x80u
+#define LPTMR_CSR_TCF_SHIFT                      7
+#define LPTMR_CSR_TCF_WIDTH                      1
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK                       0x3u
+#define LPTMR_PSR_PCS_SHIFT                      0
+#define LPTMR_PSR_PCS_WIDTH                      2
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      0x4u
+#define LPTMR_PSR_PBYP_SHIFT                     2
+#define LPTMR_PSR_PBYP_WIDTH                     1
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK                  0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT                 3
+#define LPTMR_PSR_PRESCALE_WIDTH                 4
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT                  0
+#define LPTMR_CMR_COMPARE_WIDTH                  16
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT                  0
+#define LPTMR_CNR_COUNTER_WIDTH                  16
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR                          (LPTMR0)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR                               LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR                               LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR                               LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR                               LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
+  __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
+  __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
+  __IO uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+  __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+  __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
+  __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base)                         ((base)->C1)
+#define MCG_C2_REG(base)                         ((base)->C2)
+#define MCG_C3_REG(base)                         ((base)->C3)
+#define MCG_C4_REG(base)                         ((base)->C4)
+#define MCG_C5_REG(base)                         ((base)->C5)
+#define MCG_C6_REG(base)                         ((base)->C6)
+#define MCG_S_REG(base)                          ((base)->S)
+#define MCG_SC_REG(base)                         ((base)->SC)
+#define MCG_ATCVH_REG(base)                      ((base)->ATCVH)
+#define MCG_ATCVL_REG(base)                      ((base)->ATCVL)
+#define MCG_C7_REG(base)                         ((base)->C7)
+#define MCG_C8_REG(base)                         ((base)->C8)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK                     0x1u
+#define MCG_C1_IREFSTEN_SHIFT                    0
+#define MCG_C1_IREFSTEN_WIDTH                    1
+#define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK                      0x2u
+#define MCG_C1_IRCLKEN_SHIFT                     1
+#define MCG_C1_IRCLKEN_WIDTH                     1
+#define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK                        0x4u
+#define MCG_C1_IREFS_SHIFT                       2
+#define MCG_C1_IREFS_WIDTH                       1
+#define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFS_SHIFT))&MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK                        0x38u
+#define MCG_C1_FRDIV_SHIFT                       3
+#define MCG_C1_FRDIV_WIDTH                       3
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         0xC0u
+#define MCG_C1_CLKS_SHIFT                        6
+#define MCG_C1_CLKS_WIDTH                        2
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK                         0x1u
+#define MCG_C2_IRCS_SHIFT                        0
+#define MCG_C2_IRCS_WIDTH                        1
+#define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK                           0x2u
+#define MCG_C2_LP_SHIFT                          1
+#define MCG_C2_LP_WIDTH                          1
+#define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x))<<MCG_C2_LP_SHIFT))&MCG_C2_LP_MASK)
+#define MCG_C2_EREFS_MASK                        0x4u
+#define MCG_C2_EREFS_SHIFT                       2
+#define MCG_C2_EREFS_WIDTH                       1
+#define MCG_C2_EREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS_SHIFT))&MCG_C2_EREFS_MASK)
+#define MCG_C2_HGO_MASK                          0x8u
+#define MCG_C2_HGO_SHIFT                         3
+#define MCG_C2_HGO_WIDTH                         1
+#define MCG_C2_HGO(x)                            (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO_SHIFT))&MCG_C2_HGO_MASK)
+#define MCG_C2_RANGE_MASK                        0x30u
+#define MCG_C2_RANGE_SHIFT                       4
+#define MCG_C2_RANGE_WIDTH                       2
+#define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK                      0x40u
+#define MCG_C2_FCFTRIM_SHIFT                     6
+#define MCG_C2_FCFTRIM_WIDTH                     1
+#define MCG_C2_FCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C2_FCFTRIM_SHIFT))&MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK                       0x80u
+#define MCG_C2_LOCRE0_SHIFT                      7
+#define MCG_C2_LOCRE0_WIDTH                      1
+#define MCG_C2_LOCRE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_LOCRE0_SHIFT))&MCG_C2_LOCRE0_MASK)
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK                       0xFFu
+#define MCG_C3_SCTRIM_SHIFT                      0
+#define MCG_C3_SCTRIM_WIDTH                      8
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK                      0x1u
+#define MCG_C4_SCFTRIM_SHIFT                     0
+#define MCG_C4_SCFTRIM_WIDTH                     1
+#define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C4_SCFTRIM_SHIFT))&MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK                       0x1Eu
+#define MCG_C4_FCTRIM_SHIFT                      1
+#define MCG_C4_FCTRIM_WIDTH                      4
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     0x60u
+#define MCG_C4_DRST_DRS_SHIFT                    5
+#define MCG_C4_DRST_DRS_WIDTH                    2
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK                        0x80u
+#define MCG_C4_DMX32_SHIFT                       7
+#define MCG_C4_DMX32_WIDTH                       1
+#define MCG_C4_DMX32(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C4_DMX32_SHIFT))&MCG_C4_DMX32_MASK)
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK                       0x1Fu
+#define MCG_C5_PRDIV0_SHIFT                      0
+#define MCG_C5_PRDIV0_WIDTH                      5
+#define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK                     0x20u
+#define MCG_C5_PLLSTEN0_SHIFT                    5
+#define MCG_C5_PLLSTEN0_WIDTH                    1
+#define MCG_C5_PLLSTEN0(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLSTEN0_SHIFT))&MCG_C5_PLLSTEN0_MASK)
+#define MCG_C5_PLLCLKEN0_MASK                    0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT                   6
+#define MCG_C5_PLLCLKEN0_WIDTH                   1
+#define MCG_C5_PLLCLKEN0(x)                      (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLCLKEN0_SHIFT))&MCG_C5_PLLCLKEN0_MASK)
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK                        0x1Fu
+#define MCG_C6_VDIV0_SHIFT                       0
+#define MCG_C6_VDIV0_WIDTH                       5
+#define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK                         0x20u
+#define MCG_C6_CME0_SHIFT                        5
+#define MCG_C6_CME0_WIDTH                        1
+#define MCG_C6_CME0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_CME0_SHIFT))&MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK                         0x40u
+#define MCG_C6_PLLS_SHIFT                        6
+#define MCG_C6_PLLS_WIDTH                        1
+#define MCG_C6_PLLS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_PLLS_SHIFT))&MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK                       0x80u
+#define MCG_C6_LOLIE0_SHIFT                      7
+#define MCG_C6_LOLIE0_WIDTH                      1
+#define MCG_C6_LOLIE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C6_LOLIE0_SHIFT))&MCG_C6_LOLIE0_MASK)
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK                         0x1u
+#define MCG_S_IRCST_SHIFT                        0
+#define MCG_S_IRCST_WIDTH                        1
+#define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_IRCST_SHIFT))&MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK                      0x2u
+#define MCG_S_OSCINIT0_SHIFT                     1
+#define MCG_S_OSCINIT0_WIDTH                     1
+#define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK                         0xCu
+#define MCG_S_CLKST_SHIFT                        2
+#define MCG_S_CLKST_WIDTH                        2
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK                        0x10u
+#define MCG_S_IREFST_SHIFT                       4
+#define MCG_S_IREFST_WIDTH                       1
+#define MCG_S_IREFST(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_S_IREFST_SHIFT))&MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK                         0x20u
+#define MCG_S_PLLST_SHIFT                        5
+#define MCG_S_PLLST_WIDTH                        1
+#define MCG_S_PLLST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_PLLST_SHIFT))&MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK                         0x40u
+#define MCG_S_LOCK0_SHIFT                        6
+#define MCG_S_LOCK0_WIDTH                        1
+#define MCG_S_LOCK0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOCK0_SHIFT))&MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK                         0x80u
+#define MCG_S_LOLS0_SHIFT                        7
+#define MCG_S_LOLS0_WIDTH                        1
+#define MCG_S_LOLS0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOLS0_SHIFT))&MCG_S_LOLS0_MASK)
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK                        0x1u
+#define MCG_SC_LOCS0_SHIFT                       0
+#define MCG_SC_LOCS0_WIDTH                       1
+#define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_SC_LOCS0_SHIFT))&MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK                       0xEu
+#define MCG_SC_FCRDIV_SHIFT                      1
+#define MCG_SC_FCRDIV_WIDTH                      3
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK                     0x10u
+#define MCG_SC_FLTPRSRV_SHIFT                    4
+#define MCG_SC_FLTPRSRV_WIDTH                    1
+#define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_SC_FLTPRSRV_SHIFT))&MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK                         0x20u
+#define MCG_SC_ATMF_SHIFT                        5
+#define MCG_SC_ATMF_WIDTH                        1
+#define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMF_SHIFT))&MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK                         0x40u
+#define MCG_SC_ATMS_SHIFT                        6
+#define MCG_SC_ATMS_WIDTH                        1
+#define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMS_SHIFT))&MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK                         0x80u
+#define MCG_SC_ATME_SHIFT                        7
+#define MCG_SC_ATME_WIDTH                        1
+#define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATME_SHIFT))&MCG_SC_ATME_MASK)
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK                     0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT                    0
+#define MCG_ATCVH_ATCVH_WIDTH                    8
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK                     0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT                    0
+#define MCG_ATCVL_ATCVL_WIDTH                    8
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK                       0x3u
+#define MCG_C7_OSCSEL_SHIFT                      0
+#define MCG_C7_OSCSEL_WIDTH                      2
+#define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK                        0x1u
+#define MCG_C8_LOCS1_SHIFT                       0
+#define MCG_C8_LOCS1_WIDTH                       1
+#define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCS1_SHIFT))&MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK                         0x20u
+#define MCG_C8_CME1_SHIFT                        5
+#define MCG_C8_CME1_WIDTH                        1
+#define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C8_CME1_SHIFT))&MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK                        0x40u
+#define MCG_C8_LOLRE_SHIFT                       6
+#define MCG_C8_LOLRE_WIDTH                       1
+#define MCG_C8_LOLRE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOLRE_SHIFT))&MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK                       0x80u
+#define MCG_C8_LOCRE1_SHIFT                      7
+#define MCG_C8_LOCRE1_WIDTH                      1
+#define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCRE1_SHIFT))&MCG_C8_LOCRE1_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR                             (MCG)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS                           { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS                            { MCG }
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1                                   MCG_C1_REG(MCG)
+#define MCG_C2                                   MCG_C2_REG(MCG)
+#define MCG_C3                                   MCG_C3_REG(MCG)
+#define MCG_C4                                   MCG_C4_REG(MCG)
+#define MCG_C5                                   MCG_C5_REG(MCG)
+#define MCG_C6                                   MCG_C6_REG(MCG)
+#define MCG_S                                    MCG_S_REG(MCG)
+#define MCG_SC                                   MCG_SC_REG(MCG)
+#define MCG_ATCVH                                MCG_ATCVH_REG(MCG)
+#define MCG_ATCVL                                MCG_ATCVL_REG(MCG)
+#define MCG_C7                                   MCG_C7_REG(MCG)
+#define MCG_C8                                   MCG_C8_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t CR;                                /**< Control Register, offset: 0xC */
+  __IO uint32_t ISCR;                              /**< Interrupt Status Register, offset: 0x10 */
+  __IO uint32_t ETBCC;                             /**< ETB Counter Control register, offset: 0x14 */
+  __IO uint32_t ETBRL;                             /**< ETB Reload register, offset: 0x18 */
+  __I  uint32_t ETBCNT;                            /**< ETB Counter Value register, offset: 0x1C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PID;                               /**< Process ID register, offset: 0x30 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base)                      ((base)->PLASC)
+#define MCM_PLAMC_REG(base)                      ((base)->PLAMC)
+#define MCM_CR_REG(base)                         ((base)->CR)
+#define MCM_ISCR_REG(base)                       ((base)->ISCR)
+#define MCM_ETBCC_REG(base)                      ((base)->ETBCC)
+#define MCM_ETBRL_REG(base)                      ((base)->ETBRL)
+#define MCM_ETBCNT_REG(base)                     ((base)->ETBCNT)
+#define MCM_PID_REG(base)                        ((base)->PID)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK                       0xFFu
+#define MCM_PLASC_ASC_SHIFT                      0
+#define MCM_PLASC_ASC_WIDTH                      8
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK                       0xFFu
+#define MCM_PLAMC_AMC_SHIFT                      0
+#define MCM_PLAMC_AMC_WIDTH                      8
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* CR Bit Fields */
+#define MCM_CR_SRAMUAP_MASK                      0x3000000u
+#define MCM_CR_SRAMUAP_SHIFT                     24
+#define MCM_CR_SRAMUAP_WIDTH                     2
+#define MCM_CR_SRAMUAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP_MASK                      0x4000000u
+#define MCM_CR_SRAMUWP_SHIFT                     26
+#define MCM_CR_SRAMUWP_WIDTH                     1
+#define MCM_CR_SRAMUWP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUWP_SHIFT))&MCM_CR_SRAMUWP_MASK)
+#define MCM_CR_SRAMLAP_MASK                      0x30000000u
+#define MCM_CR_SRAMLAP_SHIFT                     28
+#define MCM_CR_SRAMLAP_WIDTH                     2
+#define MCM_CR_SRAMLAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP_MASK                      0x40000000u
+#define MCM_CR_SRAMLWP_SHIFT                     30
+#define MCM_CR_SRAMLWP_WIDTH                     1
+#define MCM_CR_SRAMLWP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLWP_SHIFT))&MCM_CR_SRAMLWP_MASK)
+/* ISCR Bit Fields */
+#define MCM_ISCR_IRQ_MASK                        0x2u
+#define MCM_ISCR_IRQ_SHIFT                       1
+#define MCM_ISCR_IRQ_WIDTH                       1
+#define MCM_ISCR_IRQ(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_IRQ_SHIFT))&MCM_ISCR_IRQ_MASK)
+#define MCM_ISCR_NMI_MASK                        0x4u
+#define MCM_ISCR_NMI_SHIFT                       2
+#define MCM_ISCR_NMI_WIDTH                       1
+#define MCM_ISCR_NMI(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_NMI_SHIFT))&MCM_ISCR_NMI_MASK)
+#define MCM_ISCR_DHREQ_MASK                      0x8u
+#define MCM_ISCR_DHREQ_SHIFT                     3
+#define MCM_ISCR_DHREQ_WIDTH                     1
+#define MCM_ISCR_DHREQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_DHREQ_SHIFT))&MCM_ISCR_DHREQ_MASK)
+#define MCM_ISCR_FIOC_MASK                       0x100u
+#define MCM_ISCR_FIOC_SHIFT                      8
+#define MCM_ISCR_FIOC_WIDTH                      1
+#define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FDZC_MASK                       0x200u
+#define MCM_ISCR_FDZC_SHIFT                      9
+#define MCM_ISCR_FDZC_WIDTH                      1
+#define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FOFC_MASK                       0x400u
+#define MCM_ISCR_FOFC_SHIFT                      10
+#define MCM_ISCR_FOFC_WIDTH                      1
+#define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FUFC_MASK                       0x800u
+#define MCM_ISCR_FUFC_SHIFT                      11
+#define MCM_ISCR_FUFC_WIDTH                      1
+#define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FIXC_MASK                       0x1000u
+#define MCM_ISCR_FIXC_SHIFT                      12
+#define MCM_ISCR_FIXC_WIDTH                      1
+#define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIDC_MASK                       0x8000u
+#define MCM_ISCR_FIDC_SHIFT                      15
+#define MCM_ISCR_FIDC_WIDTH                      1
+#define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIOCE_MASK                      0x1000000u
+#define MCM_ISCR_FIOCE_SHIFT                     24
+#define MCM_ISCR_FIOCE_WIDTH                     1
+#define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FDZCE_MASK                      0x2000000u
+#define MCM_ISCR_FDZCE_SHIFT                     25
+#define MCM_ISCR_FDZCE_WIDTH                     1
+#define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FOFCE_MASK                      0x4000000u
+#define MCM_ISCR_FOFCE_SHIFT                     26
+#define MCM_ISCR_FOFCE_WIDTH                     1
+#define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FUFCE_MASK                      0x8000000u
+#define MCM_ISCR_FUFCE_SHIFT                     27
+#define MCM_ISCR_FUFCE_WIDTH                     1
+#define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FIXCE_MASK                      0x10000000u
+#define MCM_ISCR_FIXCE_SHIFT                     28
+#define MCM_ISCR_FIXCE_WIDTH                     1
+#define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIDCE_MASK                      0x80000000u
+#define MCM_ISCR_FIDCE_SHIFT                     31
+#define MCM_ISCR_FIDCE_WIDTH                     1
+#define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
+/* ETBCC Bit Fields */
+#define MCM_ETBCC_CNTEN_MASK                     0x1u
+#define MCM_ETBCC_CNTEN_SHIFT                    0
+#define MCM_ETBCC_CNTEN_WIDTH                    1
+#define MCM_ETBCC_CNTEN(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_CNTEN_SHIFT))&MCM_ETBCC_CNTEN_MASK)
+#define MCM_ETBCC_RSPT_MASK                      0x6u
+#define MCM_ETBCC_RSPT_SHIFT                     1
+#define MCM_ETBCC_RSPT_WIDTH                     2
+#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK                      0x8u
+#define MCM_ETBCC_RLRQ_SHIFT                     3
+#define MCM_ETBCC_RLRQ_WIDTH                     1
+#define MCM_ETBCC_RLRQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RLRQ_SHIFT))&MCM_ETBCC_RLRQ_MASK)
+#define MCM_ETBCC_ETDIS_MASK                     0x10u
+#define MCM_ETBCC_ETDIS_SHIFT                    4
+#define MCM_ETBCC_ETDIS_WIDTH                    1
+#define MCM_ETBCC_ETDIS(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ETDIS_SHIFT))&MCM_ETBCC_ETDIS_MASK)
+#define MCM_ETBCC_ITDIS_MASK                     0x20u
+#define MCM_ETBCC_ITDIS_SHIFT                    5
+#define MCM_ETBCC_ITDIS_WIDTH                    1
+#define MCM_ETBCC_ITDIS(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ITDIS_SHIFT))&MCM_ETBCC_ITDIS_MASK)
+/* ETBRL Bit Fields */
+#define MCM_ETBRL_RELOAD_MASK                    0x7FFu
+#define MCM_ETBRL_RELOAD_SHIFT                   0
+#define MCM_ETBRL_RELOAD_WIDTH                   11
+#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
+/* ETBCNT Bit Fields */
+#define MCM_ETBCNT_COUNTER_MASK                  0x7FFu
+#define MCM_ETBCNT_COUNTER_SHIFT                 0
+#define MCM_ETBCNT_COUNTER_WIDTH                 11
+#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
+/* PID Bit Fields */
+#define MCM_PID_PID_MASK                         0xFFu
+#define MCM_PID_PID_SHIFT                        0
+#define MCM_PID_PID_WIDTH                        8
+#define MCM_PID_PID(x)                           (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR                             (MCM)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { MCM }
+/** Interrupt vectors for the MCM peripheral type */
+#define MCM_IRQS                                 { MCM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC                                MCM_PLASC_REG(MCM)
+#define MCM_PLAMC                                MCM_PLAMC_REG(MCM)
+#define MCM_CR                                   MCM_CR_REG(MCM)
+#define MCM_ISCR                                 MCM_ISCR_REG(MCM)
+#define MCM_ETBCC                                MCM_ETBCC_REG(MCM)
+#define MCM_ETBRL                                MCM_ETBRL_REG(MCM)
+#define MCM_ETBCNT                               MCM_ETBCNT_REG(MCM)
+#define MCM_PID                                  MCM_PID_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
+ * @{
+ */
+
+/** MPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} MPU_Type, *MPU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register accessors */
+#define MPU_CESR_REG(base)                       ((base)->CESR)
+#define MPU_EAR_REG(base,index)                  ((base)->SP[index].EAR)
+#define MPU_EAR_COUNT                            5
+#define MPU_EDR_REG(base,index)                  ((base)->SP[index].EDR)
+#define MPU_EDR_COUNT                            5
+#define MPU_WORD_REG(base,index,index2)          ((base)->WORD[index][index2])
+#define MPU_WORD_COUNT                           12
+#define MPU_WORD_COUNT2                          4
+#define MPU_RGDAAC_REG(base,index)               ((base)->RGDAAC[index])
+#define MPU_RGDAAC_COUNT                         12
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Masks MPU Register Masks
+ * @{
+ */
+
+/* CESR Bit Fields */
+#define MPU_CESR_VLD_MASK                        0x1u
+#define MPU_CESR_VLD_SHIFT                       0
+#define MPU_CESR_VLD_WIDTH                       1
+#define MPU_CESR_VLD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_VLD_SHIFT))&MPU_CESR_VLD_MASK)
+#define MPU_CESR_NRGD_MASK                       0xF00u
+#define MPU_CESR_NRGD_SHIFT                      8
+#define MPU_CESR_NRGD_WIDTH                      4
+#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
+#define MPU_CESR_NSP_MASK                        0xF000u
+#define MPU_CESR_NSP_SHIFT                       12
+#define MPU_CESR_NSP_WIDTH                       4
+#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
+#define MPU_CESR_HRL_MASK                        0xF0000u
+#define MPU_CESR_HRL_SHIFT                       16
+#define MPU_CESR_HRL_WIDTH                       4
+#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
+#define MPU_CESR_SPERR_MASK                      0xF8000000u
+#define MPU_CESR_SPERR_SHIFT                     27
+#define MPU_CESR_SPERR_WIDTH                     5
+#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
+/* EAR Bit Fields */
+#define MPU_EAR_EADDR_MASK                       0xFFFFFFFFu
+#define MPU_EAR_EADDR_SHIFT                      0
+#define MPU_EAR_EADDR_WIDTH                      32
+#define MPU_EAR_EADDR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
+/* EDR Bit Fields */
+#define MPU_EDR_ERW_MASK                         0x1u
+#define MPU_EDR_ERW_SHIFT                        0
+#define MPU_EDR_ERW_WIDTH                        1
+#define MPU_EDR_ERW(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_ERW_SHIFT))&MPU_EDR_ERW_MASK)
+#define MPU_EDR_EATTR_MASK                       0xEu
+#define MPU_EDR_EATTR_SHIFT                      1
+#define MPU_EDR_EATTR_WIDTH                      3
+#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
+#define MPU_EDR_EMN_MASK                         0xF0u
+#define MPU_EDR_EMN_SHIFT                        4
+#define MPU_EDR_EMN_WIDTH                        4
+#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
+#define MPU_EDR_EPID_MASK                        0xFF00u
+#define MPU_EDR_EPID_SHIFT                       8
+#define MPU_EDR_EPID_WIDTH                       8
+#define MPU_EDR_EPID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
+#define MPU_EDR_EACD_MASK                        0xFFFF0000u
+#define MPU_EDR_EACD_SHIFT                       16
+#define MPU_EDR_EACD_WIDTH                       16
+#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
+/* WORD Bit Fields */
+#define MPU_WORD_VLD_MASK                        0x1u
+#define MPU_WORD_VLD_SHIFT                       0
+#define MPU_WORD_VLD_WIDTH                       1
+#define MPU_WORD_VLD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_VLD_SHIFT))&MPU_WORD_VLD_MASK)
+#define MPU_WORD_M0UM_MASK                       0x7u
+#define MPU_WORD_M0UM_SHIFT                      0
+#define MPU_WORD_M0UM_WIDTH                      3
+#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
+#define MPU_WORD_M0SM_MASK                       0x18u
+#define MPU_WORD_M0SM_SHIFT                      3
+#define MPU_WORD_M0SM_WIDTH                      2
+#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
+#define MPU_WORD_M0PE_MASK                       0x20u
+#define MPU_WORD_M0PE_SHIFT                      5
+#define MPU_WORD_M0PE_WIDTH                      1
+#define MPU_WORD_M0PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0PE_SHIFT))&MPU_WORD_M0PE_MASK)
+#define MPU_WORD_ENDADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_ENDADDR_SHIFT                   5
+#define MPU_WORD_ENDADDR_WIDTH                   27
+#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
+#define MPU_WORD_SRTADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_SRTADDR_SHIFT                   5
+#define MPU_WORD_SRTADDR_WIDTH                   27
+#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
+#define MPU_WORD_M1UM_MASK                       0x1C0u
+#define MPU_WORD_M1UM_SHIFT                      6
+#define MPU_WORD_M1UM_WIDTH                      3
+#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
+#define MPU_WORD_M1SM_MASK                       0x600u
+#define MPU_WORD_M1SM_SHIFT                      9
+#define MPU_WORD_M1SM_WIDTH                      2
+#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
+#define MPU_WORD_M1PE_MASK                       0x800u
+#define MPU_WORD_M1PE_SHIFT                      11
+#define MPU_WORD_M1PE_WIDTH                      1
+#define MPU_WORD_M1PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1PE_SHIFT))&MPU_WORD_M1PE_MASK)
+#define MPU_WORD_M2UM_MASK                       0x7000u
+#define MPU_WORD_M2UM_SHIFT                      12
+#define MPU_WORD_M2UM_WIDTH                      3
+#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
+#define MPU_WORD_M2SM_MASK                       0x18000u
+#define MPU_WORD_M2SM_SHIFT                      15
+#define MPU_WORD_M2SM_WIDTH                      2
+#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
+#define MPU_WORD_PIDMASK_MASK                    0xFF0000u
+#define MPU_WORD_PIDMASK_SHIFT                   16
+#define MPU_WORD_PIDMASK_WIDTH                   8
+#define MPU_WORD_PIDMASK(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
+#define MPU_WORD_M2PE_MASK                       0x20000u
+#define MPU_WORD_M2PE_SHIFT                      17
+#define MPU_WORD_M2PE_WIDTH                      1
+#define MPU_WORD_M2PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2PE_SHIFT))&MPU_WORD_M2PE_MASK)
+#define MPU_WORD_M3UM_MASK                       0x1C0000u
+#define MPU_WORD_M3UM_SHIFT                      18
+#define MPU_WORD_M3UM_WIDTH                      3
+#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
+#define MPU_WORD_M3SM_MASK                       0x600000u
+#define MPU_WORD_M3SM_SHIFT                      21
+#define MPU_WORD_M3SM_WIDTH                      2
+#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
+#define MPU_WORD_M3PE_MASK                       0x800000u
+#define MPU_WORD_M3PE_SHIFT                      23
+#define MPU_WORD_M3PE_WIDTH                      1
+#define MPU_WORD_M3PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3PE_SHIFT))&MPU_WORD_M3PE_MASK)
+#define MPU_WORD_PID_MASK                        0xFF000000u
+#define MPU_WORD_PID_SHIFT                       24
+#define MPU_WORD_PID_WIDTH                       8
+#define MPU_WORD_PID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
+#define MPU_WORD_M4WE_MASK                       0x1000000u
+#define MPU_WORD_M4WE_SHIFT                      24
+#define MPU_WORD_M4WE_WIDTH                      1
+#define MPU_WORD_M4WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4WE_SHIFT))&MPU_WORD_M4WE_MASK)
+#define MPU_WORD_M4RE_MASK                       0x2000000u
+#define MPU_WORD_M4RE_SHIFT                      25
+#define MPU_WORD_M4RE_WIDTH                      1
+#define MPU_WORD_M4RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4RE_SHIFT))&MPU_WORD_M4RE_MASK)
+#define MPU_WORD_M5WE_MASK                       0x4000000u
+#define MPU_WORD_M5WE_SHIFT                      26
+#define MPU_WORD_M5WE_WIDTH                      1
+#define MPU_WORD_M5WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5WE_SHIFT))&MPU_WORD_M5WE_MASK)
+#define MPU_WORD_M5RE_MASK                       0x8000000u
+#define MPU_WORD_M5RE_SHIFT                      27
+#define MPU_WORD_M5RE_WIDTH                      1
+#define MPU_WORD_M5RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5RE_SHIFT))&MPU_WORD_M5RE_MASK)
+#define MPU_WORD_M6WE_MASK                       0x10000000u
+#define MPU_WORD_M6WE_SHIFT                      28
+#define MPU_WORD_M6WE_WIDTH                      1
+#define MPU_WORD_M6WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6WE_SHIFT))&MPU_WORD_M6WE_MASK)
+#define MPU_WORD_M6RE_MASK                       0x20000000u
+#define MPU_WORD_M6RE_SHIFT                      29
+#define MPU_WORD_M6RE_WIDTH                      1
+#define MPU_WORD_M6RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6RE_SHIFT))&MPU_WORD_M6RE_MASK)
+#define MPU_WORD_M7WE_MASK                       0x40000000u
+#define MPU_WORD_M7WE_SHIFT                      30
+#define MPU_WORD_M7WE_WIDTH                      1
+#define MPU_WORD_M7WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7WE_SHIFT))&MPU_WORD_M7WE_MASK)
+#define MPU_WORD_M7RE_MASK                       0x80000000u
+#define MPU_WORD_M7RE_SHIFT                      31
+#define MPU_WORD_M7RE_WIDTH                      1
+#define MPU_WORD_M7RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7RE_SHIFT))&MPU_WORD_M7RE_MASK)
+/* RGDAAC Bit Fields */
+#define MPU_RGDAAC_M0UM_MASK                     0x7u
+#define MPU_RGDAAC_M0UM_SHIFT                    0
+#define MPU_RGDAAC_M0UM_WIDTH                    3
+#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
+#define MPU_RGDAAC_M0SM_MASK                     0x18u
+#define MPU_RGDAAC_M0SM_SHIFT                    3
+#define MPU_RGDAAC_M0SM_WIDTH                    2
+#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
+#define MPU_RGDAAC_M0PE_MASK                     0x20u
+#define MPU_RGDAAC_M0PE_SHIFT                    5
+#define MPU_RGDAAC_M0PE_WIDTH                    1
+#define MPU_RGDAAC_M0PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0PE_SHIFT))&MPU_RGDAAC_M0PE_MASK)
+#define MPU_RGDAAC_M1UM_MASK                     0x1C0u
+#define MPU_RGDAAC_M1UM_SHIFT                    6
+#define MPU_RGDAAC_M1UM_WIDTH                    3
+#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
+#define MPU_RGDAAC_M1SM_MASK                     0x600u
+#define MPU_RGDAAC_M1SM_SHIFT                    9
+#define MPU_RGDAAC_M1SM_WIDTH                    2
+#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
+#define MPU_RGDAAC_M1PE_MASK                     0x800u
+#define MPU_RGDAAC_M1PE_SHIFT                    11
+#define MPU_RGDAAC_M1PE_WIDTH                    1
+#define MPU_RGDAAC_M1PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1PE_SHIFT))&MPU_RGDAAC_M1PE_MASK)
+#define MPU_RGDAAC_M2UM_MASK                     0x7000u
+#define MPU_RGDAAC_M2UM_SHIFT                    12
+#define MPU_RGDAAC_M2UM_WIDTH                    3
+#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
+#define MPU_RGDAAC_M2SM_MASK                     0x18000u
+#define MPU_RGDAAC_M2SM_SHIFT                    15
+#define MPU_RGDAAC_M2SM_WIDTH                    2
+#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
+#define MPU_RGDAAC_M2PE_MASK                     0x20000u
+#define MPU_RGDAAC_M2PE_SHIFT                    17
+#define MPU_RGDAAC_M2PE_WIDTH                    1
+#define MPU_RGDAAC_M2PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2PE_SHIFT))&MPU_RGDAAC_M2PE_MASK)
+#define MPU_RGDAAC_M3UM_MASK                     0x1C0000u
+#define MPU_RGDAAC_M3UM_SHIFT                    18
+#define MPU_RGDAAC_M3UM_WIDTH                    3
+#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
+#define MPU_RGDAAC_M3SM_MASK                     0x600000u
+#define MPU_RGDAAC_M3SM_SHIFT                    21
+#define MPU_RGDAAC_M3SM_WIDTH                    2
+#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
+#define MPU_RGDAAC_M3PE_MASK                     0x800000u
+#define MPU_RGDAAC_M3PE_SHIFT                    23
+#define MPU_RGDAAC_M3PE_WIDTH                    1
+#define MPU_RGDAAC_M3PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3PE_SHIFT))&MPU_RGDAAC_M3PE_MASK)
+#define MPU_RGDAAC_M4WE_MASK                     0x1000000u
+#define MPU_RGDAAC_M4WE_SHIFT                    24
+#define MPU_RGDAAC_M4WE_WIDTH                    1
+#define MPU_RGDAAC_M4WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4WE_SHIFT))&MPU_RGDAAC_M4WE_MASK)
+#define MPU_RGDAAC_M4RE_MASK                     0x2000000u
+#define MPU_RGDAAC_M4RE_SHIFT                    25
+#define MPU_RGDAAC_M4RE_WIDTH                    1
+#define MPU_RGDAAC_M4RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4RE_SHIFT))&MPU_RGDAAC_M4RE_MASK)
+#define MPU_RGDAAC_M5WE_MASK                     0x4000000u
+#define MPU_RGDAAC_M5WE_SHIFT                    26
+#define MPU_RGDAAC_M5WE_WIDTH                    1
+#define MPU_RGDAAC_M5WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5WE_SHIFT))&MPU_RGDAAC_M5WE_MASK)
+#define MPU_RGDAAC_M5RE_MASK                     0x8000000u
+#define MPU_RGDAAC_M5RE_SHIFT                    27
+#define MPU_RGDAAC_M5RE_WIDTH                    1
+#define MPU_RGDAAC_M5RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5RE_SHIFT))&MPU_RGDAAC_M5RE_MASK)
+#define MPU_RGDAAC_M6WE_MASK                     0x10000000u
+#define MPU_RGDAAC_M6WE_SHIFT                    28
+#define MPU_RGDAAC_M6WE_WIDTH                    1
+#define MPU_RGDAAC_M6WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6WE_SHIFT))&MPU_RGDAAC_M6WE_MASK)
+#define MPU_RGDAAC_M6RE_MASK                     0x20000000u
+#define MPU_RGDAAC_M6RE_SHIFT                    29
+#define MPU_RGDAAC_M6RE_WIDTH                    1
+#define MPU_RGDAAC_M6RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6RE_SHIFT))&MPU_RGDAAC_M6RE_MASK)
+#define MPU_RGDAAC_M7WE_MASK                     0x40000000u
+#define MPU_RGDAAC_M7WE_SHIFT                    30
+#define MPU_RGDAAC_M7WE_WIDTH                    1
+#define MPU_RGDAAC_M7WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7WE_SHIFT))&MPU_RGDAAC_M7WE_MASK)
+#define MPU_RGDAAC_M7RE_MASK                     0x80000000u
+#define MPU_RGDAAC_M7RE_SHIFT                    31
+#define MPU_RGDAAC_M7RE_WIDTH                    1
+#define MPU_RGDAAC_M7RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7RE_SHIFT))&MPU_RGDAAC_M7RE_MASK)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Masks */
+
+
+/* MPU - Peripheral instance base addresses */
+/** Peripheral MPU base address */
+#define MPU_BASE                                 (0x4000D000u)
+/** Peripheral MPU base pointer */
+#define MPU                                      ((MPU_Type *)MPU_BASE)
+#define MPU_BASE_PTR                             (MPU)
+/** Array initializer of MPU peripheral base addresses */
+#define MPU_BASE_ADDRS                           { MPU_BASE }
+/** Array initializer of MPU peripheral base pointers */
+#define MPU_BASE_PTRS                            { MPU }
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register instance definitions */
+/* MPU */
+#define MPU_CESR                                 MPU_CESR_REG(MPU)
+#define MPU_EAR0                                 MPU_EAR_REG(MPU,0)
+#define MPU_EDR0                                 MPU_EDR_REG(MPU,0)
+#define MPU_EAR1                                 MPU_EAR_REG(MPU,1)
+#define MPU_EDR1                                 MPU_EDR_REG(MPU,1)
+#define MPU_EAR2                                 MPU_EAR_REG(MPU,2)
+#define MPU_EDR2                                 MPU_EDR_REG(MPU,2)
+#define MPU_EAR3                                 MPU_EAR_REG(MPU,3)
+#define MPU_EDR3                                 MPU_EDR_REG(MPU,3)
+#define MPU_EAR4                                 MPU_EAR_REG(MPU,4)
+#define MPU_EDR4                                 MPU_EDR_REG(MPU,4)
+#define MPU_RGD0_WORD0                           MPU_WORD_REG(MPU,0,0)
+#define MPU_RGD0_WORD1                           MPU_WORD_REG(MPU,0,1)
+#define MPU_RGD0_WORD2                           MPU_WORD_REG(MPU,0,2)
+#define MPU_RGD0_WORD3                           MPU_WORD_REG(MPU,0,3)
+#define MPU_RGD1_WORD0                           MPU_WORD_REG(MPU,1,0)
+#define MPU_RGD1_WORD1                           MPU_WORD_REG(MPU,1,1)
+#define MPU_RGD1_WORD2                           MPU_WORD_REG(MPU,1,2)
+#define MPU_RGD1_WORD3                           MPU_WORD_REG(MPU,1,3)
+#define MPU_RGD2_WORD0                           MPU_WORD_REG(MPU,2,0)
+#define MPU_RGD2_WORD1                           MPU_WORD_REG(MPU,2,1)
+#define MPU_RGD2_WORD2                           MPU_WORD_REG(MPU,2,2)
+#define MPU_RGD2_WORD3                           MPU_WORD_REG(MPU,2,3)
+#define MPU_RGD3_WORD0                           MPU_WORD_REG(MPU,3,0)
+#define MPU_RGD3_WORD1                           MPU_WORD_REG(MPU,3,1)
+#define MPU_RGD3_WORD2                           MPU_WORD_REG(MPU,3,2)
+#define MPU_RGD3_WORD3                           MPU_WORD_REG(MPU,3,3)
+#define MPU_RGD4_WORD0                           MPU_WORD_REG(MPU,4,0)
+#define MPU_RGD4_WORD1                           MPU_WORD_REG(MPU,4,1)
+#define MPU_RGD4_WORD2                           MPU_WORD_REG(MPU,4,2)
+#define MPU_RGD4_WORD3                           MPU_WORD_REG(MPU,4,3)
+#define MPU_RGD5_WORD0                           MPU_WORD_REG(MPU,5,0)
+#define MPU_RGD5_WORD1                           MPU_WORD_REG(MPU,5,1)
+#define MPU_RGD5_WORD2                           MPU_WORD_REG(MPU,5,2)
+#define MPU_RGD5_WORD3                           MPU_WORD_REG(MPU,5,3)
+#define MPU_RGD6_WORD0                           MPU_WORD_REG(MPU,6,0)
+#define MPU_RGD6_WORD1                           MPU_WORD_REG(MPU,6,1)
+#define MPU_RGD6_WORD2                           MPU_WORD_REG(MPU,6,2)
+#define MPU_RGD6_WORD3                           MPU_WORD_REG(MPU,6,3)
+#define MPU_RGD7_WORD0                           MPU_WORD_REG(MPU,7,0)
+#define MPU_RGD7_WORD1                           MPU_WORD_REG(MPU,7,1)
+#define MPU_RGD7_WORD2                           MPU_WORD_REG(MPU,7,2)
+#define MPU_RGD7_WORD3                           MPU_WORD_REG(MPU,7,3)
+#define MPU_RGD8_WORD0                           MPU_WORD_REG(MPU,8,0)
+#define MPU_RGD8_WORD1                           MPU_WORD_REG(MPU,8,1)
+#define MPU_RGD8_WORD2                           MPU_WORD_REG(MPU,8,2)
+#define MPU_RGD8_WORD3                           MPU_WORD_REG(MPU,8,3)
+#define MPU_RGD9_WORD0                           MPU_WORD_REG(MPU,9,0)
+#define MPU_RGD9_WORD1                           MPU_WORD_REG(MPU,9,1)
+#define MPU_RGD9_WORD2                           MPU_WORD_REG(MPU,9,2)
+#define MPU_RGD9_WORD3                           MPU_WORD_REG(MPU,9,3)
+#define MPU_RGD10_WORD0                          MPU_WORD_REG(MPU,10,0)
+#define MPU_RGD10_WORD1                          MPU_WORD_REG(MPU,10,1)
+#define MPU_RGD10_WORD2                          MPU_WORD_REG(MPU,10,2)
+#define MPU_RGD10_WORD3                          MPU_WORD_REG(MPU,10,3)
+#define MPU_RGD11_WORD0                          MPU_WORD_REG(MPU,11,0)
+#define MPU_RGD11_WORD1                          MPU_WORD_REG(MPU,11,1)
+#define MPU_RGD11_WORD2                          MPU_WORD_REG(MPU,11,2)
+#define MPU_RGD11_WORD3                          MPU_WORD_REG(MPU,11,3)
+#define MPU_RGDAAC0                              MPU_RGDAAC_REG(MPU,0)
+#define MPU_RGDAAC1                              MPU_RGDAAC_REG(MPU,1)
+#define MPU_RGDAAC2                              MPU_RGDAAC_REG(MPU,2)
+#define MPU_RGDAAC3                              MPU_RGDAAC_REG(MPU,3)
+#define MPU_RGDAAC4                              MPU_RGDAAC_REG(MPU,4)
+#define MPU_RGDAAC5                              MPU_RGDAAC_REG(MPU,5)
+#define MPU_RGDAAC6                              MPU_RGDAAC_REG(MPU,6)
+#define MPU_RGDAAC7                              MPU_RGDAAC_REG(MPU,7)
+#define MPU_RGDAAC8                              MPU_RGDAAC_REG(MPU,8)
+#define MPU_RGDAAC9                              MPU_RGDAAC_REG(MPU,9)
+#define MPU_RGDAAC10                             MPU_RGDAAC_REG(MPU,10)
+#define MPU_RGDAAC11                             MPU_RGDAAC_REG(MPU,11)
+
+/* MPU - Register array accessors */
+#define MPU_EAR(index)                           MPU_EAR_REG(MPU,index)
+#define MPU_EDR(index)                           MPU_EDR_REG(MPU,index)
+#define MPU_WORD(index,index2)                   MPU_WORD_REG(MPU,index,index2)
+#define MPU_RGDAAC(index)                        MPU_RGDAAC_REG(MPU,index)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+  __I  uint8_t FEPROT;                             /**< Non-volatile EERAM Protection Register, offset: 0xE */
+  __I  uint8_t FDPROT;                             /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base)                    ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base)                    ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base)                    ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base)                    ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base)                    ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base)                    ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base)                    ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base)                    ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base)                      ((base)->FPROT3)
+#define NV_FPROT2_REG(base)                      ((base)->FPROT2)
+#define NV_FPROT1_REG(base)                      ((base)->FPROT1)
+#define NV_FPROT0_REG(base)                      ((base)->FPROT0)
+#define NV_FSEC_REG(base)                        ((base)->FSEC)
+#define NV_FOPT_REG(base)                        ((base)->FOPT)
+#define NV_FEPROT_REG(base)                      ((base)->FEPROT)
+#define NV_FDPROT_REG(base)                      ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK                     0xFFu
+#define NV_BACKKEY3_KEY_SHIFT                    0
+#define NV_BACKKEY3_KEY_WIDTH                    8
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK                     0xFFu
+#define NV_BACKKEY2_KEY_SHIFT                    0
+#define NV_BACKKEY2_KEY_WIDTH                    8
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK                     0xFFu
+#define NV_BACKKEY1_KEY_SHIFT                    0
+#define NV_BACKKEY1_KEY_WIDTH                    8
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK                     0xFFu
+#define NV_BACKKEY0_KEY_SHIFT                    0
+#define NV_BACKKEY0_KEY_WIDTH                    8
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK                     0xFFu
+#define NV_BACKKEY7_KEY_SHIFT                    0
+#define NV_BACKKEY7_KEY_WIDTH                    8
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK                     0xFFu
+#define NV_BACKKEY6_KEY_SHIFT                    0
+#define NV_BACKKEY6_KEY_WIDTH                    8
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK                     0xFFu
+#define NV_BACKKEY5_KEY_SHIFT                    0
+#define NV_BACKKEY5_KEY_WIDTH                    8
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK                     0xFFu
+#define NV_BACKKEY4_KEY_SHIFT                    0
+#define NV_BACKKEY4_KEY_WIDTH                    8
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK                      0xFFu
+#define NV_FPROT3_PROT_SHIFT                     0
+#define NV_FPROT3_PROT_WIDTH                     8
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK                      0xFFu
+#define NV_FPROT2_PROT_SHIFT                     0
+#define NV_FPROT2_PROT_WIDTH                     8
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK                      0xFFu
+#define NV_FPROT1_PROT_SHIFT                     0
+#define NV_FPROT1_PROT_WIDTH                     8
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK                      0xFFu
+#define NV_FPROT0_PROT_SHIFT                     0
+#define NV_FPROT0_PROT_WIDTH                     8
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK                         0x3u
+#define NV_FSEC_SEC_SHIFT                        0
+#define NV_FSEC_SEC_WIDTH                        2
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      0xCu
+#define NV_FSEC_FSLACC_SHIFT                     2
+#define NV_FSEC_FSLACC_WIDTH                     2
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        0x30u
+#define NV_FSEC_MEEN_SHIFT                       4
+#define NV_FSEC_MEEN_WIDTH                       2
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       0xC0u
+#define NV_FSEC_KEYEN_SHIFT                      6
+#define NV_FSEC_KEYEN_WIDTH                      2
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK                      0x1u
+#define NV_FOPT_LPBOOT_SHIFT                     0
+#define NV_FOPT_LPBOOT_WIDTH                     1
+#define NV_FOPT_LPBOOT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT_SHIFT))&NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK                  0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT                 1
+#define NV_FOPT_EZPORT_DIS_WIDTH                 1
+#define NV_FOPT_EZPORT_DIS(x)                    (((uint8_t)(((uint8_t)(x))<<NV_FOPT_EZPORT_DIS_SHIFT))&NV_FOPT_EZPORT_DIS_MASK)
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK                     0xFFu
+#define NV_FEPROT_EPROT_SHIFT                    0
+#define NV_FEPROT_EPROT_WIDTH                    8
+#define NV_FEPROT_EPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK                     0xFFu
+#define NV_FDPROT_DPROT_SHIFT                    0
+#define NV_FDPROT_DPROT_WIDTH                    8
+#define NV_FDPROT_DPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFE_FlashConfig base address */
+#define FTFE_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFE_FlashConfig base pointer */
+#define FTFE_FlashConfig                         ((NV_Type *)FTFE_FlashConfig_BASE)
+#define FTFE_FlashConfig_BASE_PTR                (FTFE_FlashConfig)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS                            { FTFE_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS                             { FTFE_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFE_FlashConfig */
+#define NV_BACKKEY3                              NV_BACKKEY3_REG(FTFE_FlashConfig)
+#define NV_BACKKEY2                              NV_BACKKEY2_REG(FTFE_FlashConfig)
+#define NV_BACKKEY1                              NV_BACKKEY1_REG(FTFE_FlashConfig)
+#define NV_BACKKEY0                              NV_BACKKEY0_REG(FTFE_FlashConfig)
+#define NV_BACKKEY7                              NV_BACKKEY7_REG(FTFE_FlashConfig)
+#define NV_BACKKEY6                              NV_BACKKEY6_REG(FTFE_FlashConfig)
+#define NV_BACKKEY5                              NV_BACKKEY5_REG(FTFE_FlashConfig)
+#define NV_BACKKEY4                              NV_BACKKEY4_REG(FTFE_FlashConfig)
+#define NV_FPROT3                                NV_FPROT3_REG(FTFE_FlashConfig)
+#define NV_FPROT2                                NV_FPROT2_REG(FTFE_FlashConfig)
+#define NV_FPROT1                                NV_FPROT1_REG(FTFE_FlashConfig)
+#define NV_FPROT0                                NV_FPROT0_REG(FTFE_FlashConfig)
+#define NV_FSEC                                  NV_FSEC_REG(FTFE_FlashConfig)
+#define NV_FOPT                                  NV_FOPT_REG(FTFE_FlashConfig)
+#define NV_FEPROT                                NV_FEPROT_REG(FTFE_FlashConfig)
+#define NV_FDPROT                                NV_FDPROT_REG(FTFE_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base)                         ((base)->CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK                        0x1u
+#define OSC_CR_SC16P_SHIFT                       0
+#define OSC_CR_SC16P_WIDTH                       1
+#define OSC_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK                         0x2u
+#define OSC_CR_SC8P_SHIFT                        1
+#define OSC_CR_SC8P_WIDTH                        1
+#define OSC_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK                         0x4u
+#define OSC_CR_SC4P_SHIFT                        2
+#define OSC_CR_SC4P_WIDTH                        1
+#define OSC_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK                         0x8u
+#define OSC_CR_SC2P_SHIFT                        3
+#define OSC_CR_SC2P_WIDTH                        1
+#define OSC_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK                     0x20u
+#define OSC_CR_EREFSTEN_SHIFT                    5
+#define OSC_CR_EREFSTEN_WIDTH                    1
+#define OSC_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK                      0x80u
+#define OSC_CR_ERCLKEN_SHIFT                     7
+#define OSC_CR_ERCLKEN_WIDTH                     1
+#define OSC_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE                                 (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC                                      ((OSC_Type *)OSC_BASE)
+#define OSC_BASE_PTR                             (OSC)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS                           { OSC_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS                            { OSC }
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC */
+#define OSC_CR                                   OSC_CR_REG(OSC)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control register, offset: 0x0 */
+  __IO uint32_t MOD;                               /**< Modulus register, offset: 0x4 */
+  __I  uint32_t CNT;                               /**< Counter register, offset: 0x8 */
+  __IO uint32_t IDLY;                              /**< Interrupt Delay register, offset: 0xC */
+  struct {                                         /* offset: 0x10, array step: 0x28 */
+    __IO uint32_t C1;                                /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+    __IO uint32_t S;                                 /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+    __IO uint32_t DLY[2];                            /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+         uint8_t RESERVED_0[24];
+  } CH[2];
+       uint8_t RESERVED_0[240];
+  struct {                                         /* offset: 0x150, array step: 0x8 */
+    __IO uint32_t INTC;                              /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+    __IO uint32_t INT;                               /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+  } DAC[2];
+       uint8_t RESERVED_1[48];
+  __IO uint32_t POEN;                              /**< Pulse-Out n Enable register, offset: 0x190 */
+  __IO uint32_t PODLY[3];                          /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type, *PDB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register accessors */
+#define PDB_SC_REG(base)                         ((base)->SC)
+#define PDB_MOD_REG(base)                        ((base)->MOD)
+#define PDB_CNT_REG(base)                        ((base)->CNT)
+#define PDB_IDLY_REG(base)                       ((base)->IDLY)
+#define PDB_C1_REG(base,index)                   ((base)->CH[index].C1)
+#define PDB_C1_COUNT                             2
+#define PDB_S_REG(base,index)                    ((base)->CH[index].S)
+#define PDB_S_COUNT                              2
+#define PDB_DLY_REG(base,index,index2)           ((base)->CH[index].DLY[index2])
+#define PDB_DLY_COUNT                            2
+#define PDB_DLY_COUNT2                           2
+#define PDB_INTC_REG(base,index)                 ((base)->DAC[index].INTC)
+#define PDB_INTC_COUNT                           2
+#define PDB_INT_REG(base,index)                  ((base)->DAC[index].INT)
+#define PDB_INT_COUNT                            2
+#define PDB_POEN_REG(base)                       ((base)->POEN)
+#define PDB_PODLY_REG(base,index)                ((base)->PODLY[index])
+#define PDB_PODLY_COUNT                          3
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK                         0x1u
+#define PDB_SC_LDOK_SHIFT                        0
+#define PDB_SC_LDOK_WIDTH                        1
+#define PDB_SC_LDOK(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK                         0x2u
+#define PDB_SC_CONT_SHIFT                        1
+#define PDB_SC_CONT_WIDTH                        1
+#define PDB_SC_CONT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK                         0xCu
+#define PDB_SC_MULT_SHIFT                        2
+#define PDB_SC_MULT_WIDTH                        2
+#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK                        0x20u
+#define PDB_SC_PDBIE_SHIFT                       5
+#define PDB_SC_PDBIE_WIDTH                       1
+#define PDB_SC_PDBIE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK                        0x40u
+#define PDB_SC_PDBIF_SHIFT                       6
+#define PDB_SC_PDBIF_WIDTH                       1
+#define PDB_SC_PDBIF(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK                        0x80u
+#define PDB_SC_PDBEN_SHIFT                       7
+#define PDB_SC_PDBEN_WIDTH                       1
+#define PDB_SC_PDBEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK                       0xF00u
+#define PDB_SC_TRGSEL_SHIFT                      8
+#define PDB_SC_TRGSEL_WIDTH                      4
+#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK                    0x7000u
+#define PDB_SC_PRESCALER_SHIFT                   12
+#define PDB_SC_PRESCALER_WIDTH                   3
+#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK                        0x8000u
+#define PDB_SC_DMAEN_SHIFT                       15
+#define PDB_SC_DMAEN_WIDTH                       1
+#define PDB_SC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK                       0x10000u
+#define PDB_SC_SWTRIG_SHIFT                      16
+#define PDB_SC_SWTRIG_WIDTH                      1
+#define PDB_SC_SWTRIG(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK                       0x20000u
+#define PDB_SC_PDBEIE_SHIFT                      17
+#define PDB_SC_PDBEIE_WIDTH                      1
+#define PDB_SC_PDBEIE(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK                        0xC0000u
+#define PDB_SC_LDMOD_SHIFT                       18
+#define PDB_SC_LDMOD_WIDTH                       2
+#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK                         0xFFFFu
+#define PDB_MOD_MOD_SHIFT                        0
+#define PDB_MOD_MOD_WIDTH                        16
+#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK                         0xFFFFu
+#define PDB_CNT_CNT_SHIFT                        0
+#define PDB_CNT_CNT_WIDTH                        16
+#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK                       0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT                      0
+#define PDB_IDLY_IDLY_WIDTH                      16
+#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK                           0xFFu
+#define PDB_C1_EN_SHIFT                          0
+#define PDB_C1_EN_WIDTH                          8
+#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK                          0xFF00u
+#define PDB_C1_TOS_SHIFT                         8
+#define PDB_C1_TOS_WIDTH                         8
+#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK                           0xFF0000u
+#define PDB_C1_BB_SHIFT                          16
+#define PDB_C1_BB_WIDTH                          8
+#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK                           0xFFu
+#define PDB_S_ERR_SHIFT                          0
+#define PDB_S_ERR_WIDTH                          8
+#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK                            0xFF0000u
+#define PDB_S_CF_SHIFT                           16
+#define PDB_S_CF_WIDTH                           8
+#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK                         0xFFFFu
+#define PDB_DLY_DLY_SHIFT                        0
+#define PDB_DLY_DLY_WIDTH                        16
+#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* INTC Bit Fields */
+#define PDB_INTC_TOE_MASK                        0x1u
+#define PDB_INTC_TOE_SHIFT                       0
+#define PDB_INTC_TOE_WIDTH                       1
+#define PDB_INTC_TOE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_TOE_SHIFT))&PDB_INTC_TOE_MASK)
+#define PDB_INTC_EXT_MASK                        0x2u
+#define PDB_INTC_EXT_SHIFT                       1
+#define PDB_INTC_EXT_WIDTH                       1
+#define PDB_INTC_EXT(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_EXT_SHIFT))&PDB_INTC_EXT_MASK)
+/* INT Bit Fields */
+#define PDB_INT_INT_MASK                         0xFFFFu
+#define PDB_INT_INT_SHIFT                        0
+#define PDB_INT_INT_WIDTH                        16
+#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK                       0xFFu
+#define PDB_POEN_POEN_SHIFT                      0
+#define PDB_POEN_POEN_WIDTH                      8
+#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK                      0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT                     0
+#define PDB_PODLY_DLY2_WIDTH                     16
+#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK                      0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT                     16
+#define PDB_PODLY_DLY1_WIDTH                     16
+#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE                                (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0                                     ((PDB_Type *)PDB0_BASE)
+#define PDB0_BASE_PTR                            (PDB0)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS                           { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS                            { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS                                 { PDB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register instance definitions */
+/* PDB0 */
+#define PDB0_SC                                  PDB_SC_REG(PDB0)
+#define PDB0_MOD                                 PDB_MOD_REG(PDB0)
+#define PDB0_CNT                                 PDB_CNT_REG(PDB0)
+#define PDB0_IDLY                                PDB_IDLY_REG(PDB0)
+#define PDB0_CH0C1                               PDB_C1_REG(PDB0,0)
+#define PDB0_CH0S                                PDB_S_REG(PDB0,0)
+#define PDB0_CH0DLY0                             PDB_DLY_REG(PDB0,0,0)
+#define PDB0_CH0DLY1                             PDB_DLY_REG(PDB0,0,1)
+#define PDB0_CH1C1                               PDB_C1_REG(PDB0,1)
+#define PDB0_CH1S                                PDB_S_REG(PDB0,1)
+#define PDB0_CH1DLY0                             PDB_DLY_REG(PDB0,1,0)
+#define PDB0_CH1DLY1                             PDB_DLY_REG(PDB0,1,1)
+#define PDB0_DACINTC0                            PDB_INTC_REG(PDB0,0)
+#define PDB0_DACINT0                             PDB_INT_REG(PDB0,0)
+#define PDB0_DACINTC1                            PDB_INTC_REG(PDB0,1)
+#define PDB0_DACINT1                             PDB_INT_REG(PDB0,1)
+#define PDB0_POEN                                PDB_POEN_REG(PDB0)
+#define PDB0_PO0DLY                              PDB_PODLY_REG(PDB0,0)
+#define PDB0_PO1DLY                              PDB_PODLY_REG(PDB0,1)
+#define PDB0_PO2DLY                              PDB_PODLY_REG(PDB0,2)
+
+/* PDB - Register array accessors */
+#define PDB0_C1(index)                           PDB_C1_REG(PDB0,index)
+#define PDB0_S(index)                            PDB_S_REG(PDB0,index)
+#define PDB0_DLY(index,index2)                   PDB_DLY_REG(PDB0,index,index2)
+#define PDB0_INTC(index)                         PDB_INTC_REG(PDB0,index)
+#define PDB0_INT(index)                          PDB_INT_REG(PDB0,index)
+#define PDB0_PODLY(index)                        PDB_PODLY_REG(PDB0,index)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[252];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[4];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base)                        ((base)->MCR)
+#define PIT_LDVAL_REG(base,index)                ((base)->CHANNEL[index].LDVAL)
+#define PIT_LDVAL_COUNT                          4
+#define PIT_CVAL_REG(base,index)                 ((base)->CHANNEL[index].CVAL)
+#define PIT_CVAL_COUNT                           4
+#define PIT_TCTRL_REG(base,index)                ((base)->CHANNEL[index].TCTRL)
+#define PIT_TCTRL_COUNT                          4
+#define PIT_TFLG_REG(base,index)                 ((base)->CHANNEL[index].TFLG)
+#define PIT_TFLG_COUNT                           4
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK                         0x1u
+#define PIT_MCR_FRZ_SHIFT                        0
+#define PIT_MCR_FRZ_WIDTH                        1
+#define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK                        0x2u
+#define PIT_MCR_MDIS_SHIFT                       1
+#define PIT_MCR_MDIS_WIDTH                       1
+#define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT                      0
+#define PIT_LDVAL_TSV_WIDTH                      32
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT                       0
+#define PIT_CVAL_TVL_WIDTH                       32
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK                       0x1u
+#define PIT_TCTRL_TEN_SHIFT                      0
+#define PIT_TCTRL_TEN_WIDTH                      1
+#define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK                       0x2u
+#define PIT_TCTRL_TIE_SHIFT                      1
+#define PIT_TCTRL_TIE_WIDTH                      1
+#define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK                       0x4u
+#define PIT_TCTRL_CHN_SHIFT                      2
+#define PIT_TCTRL_CHN_WIDTH                      1
+#define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK                        0x1u
+#define PIT_TFLG_TIF_SHIFT                       0
+#define PIT_TFLG_TIF_WIDTH                       1
+#define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR                             (PIT)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS                           { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR                                  PIT_MCR_REG(PIT)
+#define PIT_LDVAL0                               PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0                                PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0                               PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0                                PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1                               PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1                                PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1                               PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1                                PIT_TFLG_REG(PIT,1)
+#define PIT_LDVAL2                               PIT_LDVAL_REG(PIT,2)
+#define PIT_CVAL2                                PIT_CVAL_REG(PIT,2)
+#define PIT_TCTRL2                               PIT_TCTRL_REG(PIT,2)
+#define PIT_TFLG2                                PIT_TFLG_REG(PIT,2)
+#define PIT_LDVAL3                               PIT_LDVAL_REG(PIT,3)
+#define PIT_CVAL3                                PIT_CVAL_REG(PIT,3)
+#define PIT_TCTRL3                               PIT_TCTRL_REG(PIT,3)
+#define PIT_TFLG3                                PIT_TFLG_REG(PIT,3)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index)                         PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index)                          PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index)                         PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index)                          PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base)                     ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base)                     ((base)->LVDSC2)
+#define PMC_REGSC_REG(base)                      ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK                     0x3u
+#define PMC_LVDSC1_LVDV_SHIFT                    0
+#define PMC_LVDSC1_LVDV_WIDTH                    2
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT                   4
+#define PMC_LVDSC1_LVDRE_WIDTH                   1
+#define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK                    0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT                   5
+#define PMC_LVDSC1_LVDIE_WIDTH                   1
+#define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK                   0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT                  6
+#define PMC_LVDSC1_LVDACK_WIDTH                  1
+#define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK                     0x80u
+#define PMC_LVDSC1_LVDF_SHIFT                    7
+#define PMC_LVDSC1_LVDF_WIDTH                    1
+#define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK                     0x3u
+#define PMC_LVDSC2_LVWV_SHIFT                    0
+#define PMC_LVDSC2_LVWV_WIDTH                    2
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT                   5
+#define PMC_LVDSC2_LVWIE_WIDTH                   1
+#define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK                   0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT                  6
+#define PMC_LVDSC2_LVWACK_WIDTH                  1
+#define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK                     0x80u
+#define PMC_LVDSC2_LVWF_SHIFT                    7
+#define PMC_LVDSC2_LVWF_WIDTH                    1
+#define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK                      0x1u
+#define PMC_REGSC_BGBE_SHIFT                     0
+#define PMC_REGSC_BGBE_WIDTH                     1
+#define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK                    0x4u
+#define PMC_REGSC_REGONS_SHIFT                   2
+#define PMC_REGSC_REGONS_WIDTH                   1
+#define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK                    0x8u
+#define PMC_REGSC_ACKISO_SHIFT                   3
+#define PMC_REGSC_ACKISO_WIDTH                   1
+#define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK                      0x10u
+#define PMC_REGSC_BGEN_SHIFT                     4
+#define PMC_REGSC_BGEN_WIDTH                     1
+#define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR                             (PMC)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS                           { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { LVD_LVW_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1                               PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2                               PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC                                PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
+  __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
+  __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index)                 ((base)->PCR[index])
+#define PORT_PCR_COUNT                           32
+#define PORT_GPCLR_REG(base)                     ((base)->GPCLR)
+#define PORT_GPCHR_REG(base)                     ((base)->GPCHR)
+#define PORT_ISFR_REG(base)                      ((base)->ISFR)
+#define PORT_DFER_REG(base)                      ((base)->DFER)
+#define PORT_DFCR_REG(base)                      ((base)->DFCR)
+#define PORT_DFWR_REG(base)                      ((base)->DFWR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK                         0x1u
+#define PORT_PCR_PS_SHIFT                        0
+#define PORT_PCR_PS_WIDTH                        1
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK                         0x2u
+#define PORT_PCR_PE_SHIFT                        1
+#define PORT_PCR_PE_WIDTH                        1
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK                        0x4u
+#define PORT_PCR_SRE_SHIFT                       2
+#define PORT_PCR_SRE_WIDTH                       1
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK                        0x10u
+#define PORT_PCR_PFE_SHIFT                       4
+#define PORT_PCR_PFE_WIDTH                       1
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK                        0x20u
+#define PORT_PCR_ODE_SHIFT                       5
+#define PORT_PCR_ODE_WIDTH                       1
+#define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK                        0x40u
+#define PORT_PCR_DSE_SHIFT                       6
+#define PORT_PCR_DSE_WIDTH                       1
+#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK                        0x700u
+#define PORT_PCR_MUX_SHIFT                       8
+#define PORT_PCR_MUX_WIDTH                       3
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK                         0x8000u
+#define PORT_PCR_LK_SHIFT                        15
+#define PORT_PCR_LK_WIDTH                        1
+#define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK                       0xF0000u
+#define PORT_PCR_IRQC_SHIFT                      16
+#define PORT_PCR_IRQC_WIDTH                      4
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        0x1000000u
+#define PORT_PCR_ISF_SHIFT                       24
+#define PORT_PCR_ISF_WIDTH                       1
+#define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT                    0
+#define PORT_GPCLR_GPWD_WIDTH                    16
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT                    16
+#define PORT_GPCLR_GPWE_WIDTH                    16
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT                    0
+#define PORT_GPCHR_GPWD_WIDTH                    16
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT                    16
+#define PORT_GPCHR_GPWE_WIDTH                    16
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT                      0
+#define PORT_ISFR_ISF_WIDTH                      32
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK                       0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT                      0
+#define PORT_DFER_DFE_WIDTH                      32
+#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK                        0x1u
+#define PORT_DFCR_CS_SHIFT                       0
+#define PORT_DFCR_CS_WIDTH                       1
+#define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK                      0x1Fu
+#define PORT_DFWR_FILT_SHIFT                     0
+#define PORT_DFWR_FILT_WIDTH                     5
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR                           (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR                           (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR                           (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR                           (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR                           (PORTE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0                               PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1                               PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2                               PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3                               PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4                               PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5                               PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6                               PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7                               PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8                               PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9                               PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10                              PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11                              PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12                              PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13                              PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14                              PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15                              PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16                              PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17                              PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18                              PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19                              PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20                              PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21                              PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22                              PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23                              PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24                              PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25                              PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26                              PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27                              PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28                              PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29                              PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30                              PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31                              PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR                              PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR                              PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR                               PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0                               PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1                               PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2                               PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3                               PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4                               PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5                               PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6                               PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7                               PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8                               PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9                               PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10                              PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11                              PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12                              PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13                              PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14                              PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15                              PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16                              PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17                              PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18                              PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19                              PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20                              PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21                              PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22                              PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23                              PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24                              PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25                              PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26                              PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27                              PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28                              PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29                              PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30                              PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31                              PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR                              PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR                              PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR                               PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0                               PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1                               PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2                               PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3                               PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4                               PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5                               PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6                               PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7                               PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8                               PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9                               PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10                              PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11                              PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12                              PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13                              PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14                              PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15                              PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16                              PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17                              PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18                              PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19                              PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20                              PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21                              PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22                              PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23                              PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24                              PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25                              PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26                              PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27                              PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28                              PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29                              PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30                              PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31                              PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR                              PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR                              PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR                               PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0                               PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1                               PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2                               PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3                               PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4                               PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5                               PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6                               PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7                               PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8                               PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9                               PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10                              PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11                              PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12                              PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13                              PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14                              PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15                              PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16                              PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17                              PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18                              PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19                              PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20                              PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21                              PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22                              PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23                              PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24                              PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25                              PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26                              PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27                              PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28                              PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29                              PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30                              PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31                              PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR                              PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR                              PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR                               PORT_ISFR_REG(PORTD)
+#define PORTD_DFER                               PORT_DFER_REG(PORTD)
+#define PORTD_DFCR                               PORT_DFCR_REG(PORTD)
+#define PORTD_DFWR                               PORT_DFWR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0                               PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1                               PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2                               PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3                               PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4                               PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5                               PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6                               PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7                               PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8                               PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9                               PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10                              PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11                              PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12                              PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13                              PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14                              PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15                              PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16                              PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17                              PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18                              PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19                              PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20                              PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21                              PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22                              PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23                              PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24                              PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25                              PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26                              PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27                              PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28                              PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29                              PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30                              PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31                              PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR                              PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR                              PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR                               PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index)                         PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index)                         PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index)                         PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index)                         PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index)                         PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+       uint8_t RESERVED_1[1];
+  __I  uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base)                       ((base)->SRS0)
+#define RCM_SRS1_REG(base)                       ((base)->SRS1)
+#define RCM_RPFC_REG(base)                       ((base)->RPFC)
+#define RCM_RPFW_REG(base)                       ((base)->RPFW)
+#define RCM_MR_REG(base)                         ((base)->MR)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK                     0x1u
+#define RCM_SRS0_WAKEUP_SHIFT                    0
+#define RCM_SRS0_WAKEUP_WIDTH                    1
+#define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK                        0x2u
+#define RCM_SRS0_LVD_SHIFT                       1
+#define RCM_SRS0_LVD_WIDTH                       1
+#define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK                        0x4u
+#define RCM_SRS0_LOC_SHIFT                       2
+#define RCM_SRS0_LOC_WIDTH                       1
+#define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOC_SHIFT))&RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK                        0x8u
+#define RCM_SRS0_LOL_SHIFT                       3
+#define RCM_SRS0_LOL_WIDTH                       1
+#define RCM_SRS0_LOL(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOL_SHIFT))&RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK                       0x20u
+#define RCM_SRS0_WDOG_SHIFT                      5
+#define RCM_SRS0_WDOG_WIDTH                      1
+#define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK                        0x40u
+#define RCM_SRS0_PIN_SHIFT                       6
+#define RCM_SRS0_PIN_WIDTH                       1
+#define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK                        0x80u
+#define RCM_SRS0_POR_SHIFT                       7
+#define RCM_SRS0_POR_WIDTH                       1
+#define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK                       0x1u
+#define RCM_SRS1_JTAG_SHIFT                      0
+#define RCM_SRS1_JTAG_WIDTH                      1
+#define RCM_SRS1_JTAG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_JTAG_SHIFT))&RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK                     0x2u
+#define RCM_SRS1_LOCKUP_SHIFT                    1
+#define RCM_SRS1_LOCKUP_WIDTH                    1
+#define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK                         0x4u
+#define RCM_SRS1_SW_SHIFT                        2
+#define RCM_SRS1_SW_WIDTH                        1
+#define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK                     0x8u
+#define RCM_SRS1_MDM_AP_SHIFT                    3
+#define RCM_SRS1_MDM_AP_WIDTH                    1
+#define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK                       0x10u
+#define RCM_SRS1_EZPT_SHIFT                      4
+#define RCM_SRS1_EZPT_WIDTH                      1
+#define RCM_SRS1_EZPT(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_EZPT_SHIFT))&RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK                    0x20u
+#define RCM_SRS1_SACKERR_SHIFT                   5
+#define RCM_SRS1_SACKERR_WIDTH                   1
+#define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 0
+#define RCM_RPFC_RSTFLTSRW_WIDTH                 2
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK                   0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT                  2
+#define RCM_RPFC_RSTFLTSS_WIDTH                  1
+#define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 0
+#define RCM_RPFW_RSTFLTSEL_WIDTH                 5
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK                       0x2u
+#define RCM_MR_EZP_MS_SHIFT                      1
+#define RCM_MR_EZP_MS_WIDTH                      1
+#define RCM_MR_EZP_MS(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_MR_EZP_MS_SHIFT))&RCM_MR_EZP_MS_MASK)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR                             (RCM)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS                           { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS                            { RCM }
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0                                 RCM_SRS0_REG(RCM)
+#define RCM_SRS1                                 RCM_SRS1_REG(RCM)
+#define RCM_RPFC                                 RCM_RPFC_REG(RCM)
+#define RCM_RPFW                                 RCM_RPFW_REG(RCM)
+#define RCM_MR                                   RCM_MR_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index)                ((base)->REG[index])
+#define RFSYS_REG_COUNT                          8
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK                        0xFFu
+#define RFSYS_REG_LL_SHIFT                       0
+#define RFSYS_REG_LL_WIDTH                       8
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        0xFF00u
+#define RFSYS_REG_LH_SHIFT                       8
+#define RFSYS_REG_LH_WIDTH                       8
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        0xFF0000u
+#define RFSYS_REG_HL_SHIFT                       16
+#define RFSYS_REG_HL_WIDTH                       8
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        0xFF000000u
+#define RFSYS_REG_HH_SHIFT                       24
+#define RFSYS_REG_HH_WIDTH                       8
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR                           (RFSYS)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS                          { RFSYS }
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0                               RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1                               RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2                               RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3                               RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4                               RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5                               RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6                               RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7                               RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index)                         RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type, *RFVBAT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register accessors */
+#define RFVBAT_REG_REG(base,index)               ((base)->REG[index])
+#define RFVBAT_REG_COUNT                         8
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK                       0xFFu
+#define RFVBAT_REG_LL_SHIFT                      0
+#define RFVBAT_REG_LL_WIDTH                      8
+#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK                       0xFF00u
+#define RFVBAT_REG_LH_SHIFT                      8
+#define RFVBAT_REG_LH_WIDTH                      8
+#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK                       0xFF0000u
+#define RFVBAT_REG_HL_SHIFT                      16
+#define RFVBAT_REG_HL_WIDTH                      8
+#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK                       0xFF000000u
+#define RFVBAT_REG_HH_SHIFT                      24
+#define RFVBAT_REG_HH_WIDTH                      8
+#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE                              (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
+#define RFVBAT_BASE_PTR                          (RFVBAT)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS                        { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS                         { RFVBAT }
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register instance definitions */
+/* RFVBAT */
+#define RFVBAT_REG0                              RFVBAT_REG_REG(RFVBAT,0)
+#define RFVBAT_REG1                              RFVBAT_REG_REG(RFVBAT,1)
+#define RFVBAT_REG2                              RFVBAT_REG_REG(RFVBAT,2)
+#define RFVBAT_REG3                              RFVBAT_REG_REG(RFVBAT,3)
+#define RFVBAT_REG4                              RFVBAT_REG_REG(RFVBAT,4)
+#define RFVBAT_REG5                              RFVBAT_REG_REG(RFVBAT,5)
+#define RFVBAT_REG6                              RFVBAT_REG_REG(RFVBAT,6)
+#define RFVBAT_REG7                              RFVBAT_REG_REG(RFVBAT,7)
+
+/* RFVBAT - Register array accessors */
+#define RFVBAT_REG(index)                        RFVBAT_REG_REG(RFVBAT,index)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< RNGA Control Register, offset: 0x0 */
+  __I  uint32_t SR;                                /**< RNGA Status Register, offset: 0x4 */
+  __O  uint32_t ER;                                /**< RNGA Entropy Register, offset: 0x8 */
+  __I  uint32_t OR;                                /**< RNGA Output Register, offset: 0xC */
+} RNG_Type, *RNG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register accessors */
+#define RNG_CR_REG(base)                         ((base)->CR)
+#define RNG_SR_REG(base)                         ((base)->SR)
+#define RNG_ER_REG(base)                         ((base)->ER)
+#define RNG_OR_REG(base)                         ((base)->OR)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define RNG_CR_GO_MASK                           0x1u
+#define RNG_CR_GO_SHIFT                          0
+#define RNG_CR_GO_WIDTH                          1
+#define RNG_CR_GO(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_GO_SHIFT))&RNG_CR_GO_MASK)
+#define RNG_CR_HA_MASK                           0x2u
+#define RNG_CR_HA_SHIFT                          1
+#define RNG_CR_HA_WIDTH                          1
+#define RNG_CR_HA(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_HA_SHIFT))&RNG_CR_HA_MASK)
+#define RNG_CR_INTM_MASK                         0x4u
+#define RNG_CR_INTM_SHIFT                        2
+#define RNG_CR_INTM_WIDTH                        1
+#define RNG_CR_INTM(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_INTM_SHIFT))&RNG_CR_INTM_MASK)
+#define RNG_CR_CLRI_MASK                         0x8u
+#define RNG_CR_CLRI_SHIFT                        3
+#define RNG_CR_CLRI_WIDTH                        1
+#define RNG_CR_CLRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_CLRI_SHIFT))&RNG_CR_CLRI_MASK)
+#define RNG_CR_SLP_MASK                          0x10u
+#define RNG_CR_SLP_SHIFT                         4
+#define RNG_CR_SLP_WIDTH                         1
+#define RNG_CR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_CR_SLP_SHIFT))&RNG_CR_SLP_MASK)
+/* SR Bit Fields */
+#define RNG_SR_SECV_MASK                         0x1u
+#define RNG_SR_SECV_SHIFT                        0
+#define RNG_SR_SECV_WIDTH                        1
+#define RNG_SR_SECV(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_SECV_SHIFT))&RNG_SR_SECV_MASK)
+#define RNG_SR_LRS_MASK                          0x2u
+#define RNG_SR_LRS_SHIFT                         1
+#define RNG_SR_LRS_WIDTH                         1
+#define RNG_SR_LRS(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_LRS_SHIFT))&RNG_SR_LRS_MASK)
+#define RNG_SR_ORU_MASK                          0x4u
+#define RNG_SR_ORU_SHIFT                         2
+#define RNG_SR_ORU_WIDTH                         1
+#define RNG_SR_ORU(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_ORU_SHIFT))&RNG_SR_ORU_MASK)
+#define RNG_SR_ERRI_MASK                         0x8u
+#define RNG_SR_ERRI_SHIFT                        3
+#define RNG_SR_ERRI_WIDTH                        1
+#define RNG_SR_ERRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_ERRI_SHIFT))&RNG_SR_ERRI_MASK)
+#define RNG_SR_SLP_MASK                          0x10u
+#define RNG_SR_SLP_SHIFT                         4
+#define RNG_SR_SLP_WIDTH                         1
+#define RNG_SR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_SLP_SHIFT))&RNG_SR_SLP_MASK)
+#define RNG_SR_OREG_LVL_MASK                     0xFF00u
+#define RNG_SR_OREG_LVL_SHIFT                    8
+#define RNG_SR_OREG_LVL_WIDTH                    8
+#define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK                    0xFF0000u
+#define RNG_SR_OREG_SIZE_SHIFT                   16
+#define RNG_SR_OREG_SIZE_WIDTH                   8
+#define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
+/* ER Bit Fields */
+#define RNG_ER_EXT_ENT_MASK                      0xFFFFFFFFu
+#define RNG_ER_EXT_ENT_SHIFT                     0
+#define RNG_ER_EXT_ENT_WIDTH                     32
+#define RNG_ER_EXT_ENT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
+/* OR Bit Fields */
+#define RNG_OR_RANDOUT_MASK                      0xFFFFFFFFu
+#define RNG_OR_RANDOUT_SHIFT                     0
+#define RNG_OR_RANDOUT_WIDTH                     32
+#define RNG_OR_RANDOUT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE                                 (0x40029000u)
+/** Peripheral RNG base pointer */
+#define RNG                                      ((RNG_Type *)RNG_BASE)
+#define RNG_BASE_PTR                             (RNG)
+/** Array initializer of RNG peripheral base addresses */
+#define RNG_BASE_ADDRS                           { RNG_BASE }
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASE_PTRS                            { RNG }
+/** Interrupt vectors for the RNG peripheral type */
+#define RNG_IRQS                                 { RNG_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register instance definitions */
+/* RNG */
+#define RNG_CR                                   RNG_CR_REG(RNG)
+#define RNG_SR                                   RNG_SR_REG(RNG)
+#define RNG_ER                                   RNG_ER_REG(RNG)
+#define RNG_OR                                   RNG_OR_REG(RNG)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+       uint8_t RESERVED_0[2016];
+  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base)                        ((base)->TSR)
+#define RTC_TPR_REG(base)                        ((base)->TPR)
+#define RTC_TAR_REG(base)                        ((base)->TAR)
+#define RTC_TCR_REG(base)                        ((base)->TCR)
+#define RTC_CR_REG(base)                         ((base)->CR)
+#define RTC_SR_REG(base)                         ((base)->SR)
+#define RTC_LR_REG(base)                         ((base)->LR)
+#define RTC_IER_REG(base)                        ((base)->IER)
+#define RTC_WAR_REG(base)                        ((base)->WAR)
+#define RTC_RAR_REG(base)                        ((base)->RAR)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT                        0
+#define RTC_TSR_TSR_WIDTH                        32
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK                         0xFFFFu
+#define RTC_TPR_TPR_SHIFT                        0
+#define RTC_TPR_TPR_WIDTH                        16
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT                        0
+#define RTC_TAR_TAR_WIDTH                        32
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK                         0xFFu
+#define RTC_TCR_TCR_SHIFT                        0
+#define RTC_TCR_TCR_WIDTH                        8
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         0xFF00u
+#define RTC_TCR_CIR_SHIFT                        8
+#define RTC_TCR_CIR_WIDTH                        8
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         0xFF0000u
+#define RTC_TCR_TCV_SHIFT                        16
+#define RTC_TCR_TCV_WIDTH                        8
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         0xFF000000u
+#define RTC_TCR_CIC_SHIFT                        24
+#define RTC_TCR_CIC_WIDTH                        8
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK                          0x1u
+#define RTC_CR_SWR_SHIFT                         0
+#define RTC_CR_SWR_WIDTH                         1
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK                          0x2u
+#define RTC_CR_WPE_SHIFT                         1
+#define RTC_CR_WPE_WIDTH                         1
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK                          0x4u
+#define RTC_CR_SUP_SHIFT                         2
+#define RTC_CR_SUP_WIDTH                         1
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK                           0x8u
+#define RTC_CR_UM_SHIFT                          3
+#define RTC_CR_UM_WIDTH                          1
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK                          0x10u
+#define RTC_CR_WPS_SHIFT                         4
+#define RTC_CR_WPS_WIDTH                         1
+#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK                         0x100u
+#define RTC_CR_OSCE_SHIFT                        8
+#define RTC_CR_OSCE_WIDTH                        1
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK                         0x200u
+#define RTC_CR_CLKO_SHIFT                        9
+#define RTC_CR_CLKO_WIDTH                        1
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK                        0x400u
+#define RTC_CR_SC16P_SHIFT                       10
+#define RTC_CR_SC16P_WIDTH                       1
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK                         0x800u
+#define RTC_CR_SC8P_SHIFT                        11
+#define RTC_CR_SC8P_WIDTH                        1
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK                         0x1000u
+#define RTC_CR_SC4P_SHIFT                        12
+#define RTC_CR_SC4P_WIDTH                        1
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK                         0x2000u
+#define RTC_CR_SC2P_SHIFT                        13
+#define RTC_CR_SC2P_WIDTH                        1
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK                          0x1u
+#define RTC_SR_TIF_SHIFT                         0
+#define RTC_SR_TIF_WIDTH                         1
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK                          0x2u
+#define RTC_SR_TOF_SHIFT                         1
+#define RTC_SR_TOF_WIDTH                         1
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK                          0x4u
+#define RTC_SR_TAF_SHIFT                         2
+#define RTC_SR_TAF_WIDTH                         1
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK                          0x10u
+#define RTC_SR_TCE_SHIFT                         4
+#define RTC_SR_TCE_WIDTH                         1
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK                          0x8u
+#define RTC_LR_TCL_SHIFT                         3
+#define RTC_LR_TCL_WIDTH                         1
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK                          0x10u
+#define RTC_LR_CRL_SHIFT                         4
+#define RTC_LR_CRL_WIDTH                         1
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK                          0x20u
+#define RTC_LR_SRL_SHIFT                         5
+#define RTC_LR_SRL_WIDTH                         1
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK                          0x40u
+#define RTC_LR_LRL_SHIFT                         6
+#define RTC_LR_LRL_WIDTH                         1
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK                        0x1u
+#define RTC_IER_TIIE_SHIFT                       0
+#define RTC_IER_TIIE_WIDTH                       1
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK                        0x2u
+#define RTC_IER_TOIE_SHIFT                       1
+#define RTC_IER_TOIE_WIDTH                       1
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK                        0x4u
+#define RTC_IER_TAIE_SHIFT                       2
+#define RTC_IER_TAIE_WIDTH                       1
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK                        0x10u
+#define RTC_IER_TSIE_SHIFT                       4
+#define RTC_IER_TSIE_WIDTH                       1
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK                        0x80u
+#define RTC_IER_WPON_SHIFT                       7
+#define RTC_IER_WPON_WIDTH                       1
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK                        0x1u
+#define RTC_WAR_TSRW_SHIFT                       0
+#define RTC_WAR_TSRW_WIDTH                       1
+#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TSRW_SHIFT))&RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK                        0x2u
+#define RTC_WAR_TPRW_SHIFT                       1
+#define RTC_WAR_TPRW_WIDTH                       1
+#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TPRW_SHIFT))&RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK                        0x4u
+#define RTC_WAR_TARW_SHIFT                       2
+#define RTC_WAR_TARW_WIDTH                       1
+#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TARW_SHIFT))&RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK                        0x8u
+#define RTC_WAR_TCRW_SHIFT                       3
+#define RTC_WAR_TCRW_WIDTH                       1
+#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TCRW_SHIFT))&RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK                         0x10u
+#define RTC_WAR_CRW_SHIFT                        4
+#define RTC_WAR_CRW_WIDTH                        1
+#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_CRW_SHIFT))&RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK                         0x20u
+#define RTC_WAR_SRW_SHIFT                        5
+#define RTC_WAR_SRW_WIDTH                        1
+#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_SRW_SHIFT))&RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK                         0x40u
+#define RTC_WAR_LRW_SHIFT                        6
+#define RTC_WAR_LRW_WIDTH                        1
+#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_LRW_SHIFT))&RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK                        0x80u
+#define RTC_WAR_IERW_SHIFT                       7
+#define RTC_WAR_IERW_WIDTH                       1
+#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_IERW_SHIFT))&RTC_WAR_IERW_MASK)
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK                        0x1u
+#define RTC_RAR_TSRR_SHIFT                       0
+#define RTC_RAR_TSRR_WIDTH                       1
+#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TSRR_SHIFT))&RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK                        0x2u
+#define RTC_RAR_TPRR_SHIFT                       1
+#define RTC_RAR_TPRR_WIDTH                       1
+#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TPRR_SHIFT))&RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK                        0x4u
+#define RTC_RAR_TARR_SHIFT                       2
+#define RTC_RAR_TARR_WIDTH                       1
+#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TARR_SHIFT))&RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK                        0x8u
+#define RTC_RAR_TCRR_SHIFT                       3
+#define RTC_RAR_TCRR_WIDTH                       1
+#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TCRR_SHIFT))&RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK                         0x10u
+#define RTC_RAR_CRR_SHIFT                        4
+#define RTC_RAR_CRR_WIDTH                        1
+#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_CRR_SHIFT))&RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK                         0x20u
+#define RTC_RAR_SRR_SHIFT                        5
+#define RTC_RAR_SRR_WIDTH                        1
+#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_SRR_SHIFT))&RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK                         0x40u
+#define RTC_RAR_LRR_SHIFT                        6
+#define RTC_RAR_LRR_WIDTH                        1
+#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_LRR_SHIFT))&RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK                        0x80u
+#define RTC_RAR_IERR_SHIFT                       7
+#define RTC_RAR_IERR_WIDTH                       1
+#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_IERR_SHIFT))&RTC_RAR_IERR_MASK)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR                             (RTC)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR                                  RTC_TSR_REG(RTC)
+#define RTC_TPR                                  RTC_TPR_REG(RTC)
+#define RTC_TAR                                  RTC_TAR_REG(RTC)
+#define RTC_TCR                                  RTC_TCR_REG(RTC)
+#define RTC_CR                                   RTC_CR_REG(RTC)
+#define RTC_SR                                   RTC_SR_REG(RTC)
+#define RTC_LR                                   RTC_LR_REG(RTC)
+#define RTC_IER                                  RTC_IER_REG(RTC)
+#define RTC_WAR                                  RTC_WAR_REG(RTC)
+#define RTC_RAR                                  RTC_RAR_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
+ * @{
+ */
+
+/** SDHC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DSADDR;                            /**< DMA System Address register, offset: 0x0 */
+  __IO uint32_t BLKATTR;                           /**< Block Attributes register, offset: 0x4 */
+  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x8 */
+  __IO uint32_t XFERTYP;                           /**< Transfer Type register, offset: 0xC */
+  __I  uint32_t CMDRSP[4];                         /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t DATPORT;                           /**< Buffer Data Port register, offset: 0x20 */
+  __I  uint32_t PRSSTAT;                           /**< Present State register, offset: 0x24 */
+  __IO uint32_t PROCTL;                            /**< Protocol Control register, offset: 0x28 */
+  __IO uint32_t SYSCTL;                            /**< System Control register, offset: 0x2C */
+  __IO uint32_t IRQSTAT;                           /**< Interrupt Status register, offset: 0x30 */
+  __IO uint32_t IRQSTATEN;                         /**< Interrupt Status Enable register, offset: 0x34 */
+  __IO uint32_t IRQSIGEN;                          /**< Interrupt Signal Enable register, offset: 0x38 */
+  __I  uint32_t AC12ERR;                           /**< Auto CMD12 Error Status Register, offset: 0x3C */
+  __I  uint32_t HTCAPBLT;                          /**< Host Controller Capabilities, offset: 0x40 */
+  __IO uint32_t WML;                               /**< Watermark Level Register, offset: 0x44 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t FEVT;                              /**< Force Event register, offset: 0x50 */
+  __I  uint32_t ADMAES;                            /**< ADMA Error Status register, offset: 0x54 */
+  __IO uint32_t ADSADDR;                           /**< ADMA System Addressregister, offset: 0x58 */
+       uint8_t RESERVED_1[100];
+  __IO uint32_t VENDOR;                            /**< Vendor Specific register, offset: 0xC0 */
+  __IO uint32_t MMCBOOT;                           /**< MMC Boot register, offset: 0xC4 */
+       uint8_t RESERVED_2[52];
+  __I  uint32_t HOSTVER;                           /**< Host Controller Version, offset: 0xFC */
+} SDHC_Type, *SDHC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register accessors */
+#define SDHC_DSADDR_REG(base)                    ((base)->DSADDR)
+#define SDHC_BLKATTR_REG(base)                   ((base)->BLKATTR)
+#define SDHC_CMDARG_REG(base)                    ((base)->CMDARG)
+#define SDHC_XFERTYP_REG(base)                   ((base)->XFERTYP)
+#define SDHC_CMDRSP_REG(base,index)              ((base)->CMDRSP[index])
+#define SDHC_CMDRSP_COUNT                        4
+#define SDHC_DATPORT_REG(base)                   ((base)->DATPORT)
+#define SDHC_PRSSTAT_REG(base)                   ((base)->PRSSTAT)
+#define SDHC_PROCTL_REG(base)                    ((base)->PROCTL)
+#define SDHC_SYSCTL_REG(base)                    ((base)->SYSCTL)
+#define SDHC_IRQSTAT_REG(base)                   ((base)->IRQSTAT)
+#define SDHC_IRQSTATEN_REG(base)                 ((base)->IRQSTATEN)
+#define SDHC_IRQSIGEN_REG(base)                  ((base)->IRQSIGEN)
+#define SDHC_AC12ERR_REG(base)                   ((base)->AC12ERR)
+#define SDHC_HTCAPBLT_REG(base)                  ((base)->HTCAPBLT)
+#define SDHC_WML_REG(base)                       ((base)->WML)
+#define SDHC_FEVT_REG(base)                      ((base)->FEVT)
+#define SDHC_ADMAES_REG(base)                    ((base)->ADMAES)
+#define SDHC_ADSADDR_REG(base)                   ((base)->ADSADDR)
+#define SDHC_VENDOR_REG(base)                    ((base)->VENDOR)
+#define SDHC_MMCBOOT_REG(base)                   ((base)->MMCBOOT)
+#define SDHC_HOSTVER_REG(base)                   ((base)->HOSTVER)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/* DSADDR Bit Fields */
+#define SDHC_DSADDR_DSADDR_MASK                  0xFFFFFFFCu
+#define SDHC_DSADDR_DSADDR_SHIFT                 2
+#define SDHC_DSADDR_DSADDR_WIDTH                 30
+#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
+/* BLKATTR Bit Fields */
+#define SDHC_BLKATTR_BLKSIZE_MASK                0x1FFFu
+#define SDHC_BLKATTR_BLKSIZE_SHIFT               0
+#define SDHC_BLKATTR_BLKSIZE_WIDTH               13
+#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK                 0xFFFF0000u
+#define SDHC_BLKATTR_BLKCNT_SHIFT                16
+#define SDHC_BLKATTR_BLKCNT_WIDTH                16
+#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
+/* CMDARG Bit Fields */
+#define SDHC_CMDARG_CMDARG_MASK                  0xFFFFFFFFu
+#define SDHC_CMDARG_CMDARG_SHIFT                 0
+#define SDHC_CMDARG_CMDARG_WIDTH                 32
+#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
+/* XFERTYP Bit Fields */
+#define SDHC_XFERTYP_DMAEN_MASK                  0x1u
+#define SDHC_XFERTYP_DMAEN_SHIFT                 0
+#define SDHC_XFERTYP_DMAEN_WIDTH                 1
+#define SDHC_XFERTYP_DMAEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DMAEN_SHIFT))&SDHC_XFERTYP_DMAEN_MASK)
+#define SDHC_XFERTYP_BCEN_MASK                   0x2u
+#define SDHC_XFERTYP_BCEN_SHIFT                  1
+#define SDHC_XFERTYP_BCEN_WIDTH                  1
+#define SDHC_XFERTYP_BCEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_BCEN_SHIFT))&SDHC_XFERTYP_BCEN_MASK)
+#define SDHC_XFERTYP_AC12EN_MASK                 0x4u
+#define SDHC_XFERTYP_AC12EN_SHIFT                2
+#define SDHC_XFERTYP_AC12EN_WIDTH                1
+#define SDHC_XFERTYP_AC12EN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_AC12EN_SHIFT))&SDHC_XFERTYP_AC12EN_MASK)
+#define SDHC_XFERTYP_DTDSEL_MASK                 0x10u
+#define SDHC_XFERTYP_DTDSEL_SHIFT                4
+#define SDHC_XFERTYP_DTDSEL_WIDTH                1
+#define SDHC_XFERTYP_DTDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DTDSEL_SHIFT))&SDHC_XFERTYP_DTDSEL_MASK)
+#define SDHC_XFERTYP_MSBSEL_MASK                 0x20u
+#define SDHC_XFERTYP_MSBSEL_SHIFT                5
+#define SDHC_XFERTYP_MSBSEL_WIDTH                1
+#define SDHC_XFERTYP_MSBSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_MSBSEL_SHIFT))&SDHC_XFERTYP_MSBSEL_MASK)
+#define SDHC_XFERTYP_RSPTYP_MASK                 0x30000u
+#define SDHC_XFERTYP_RSPTYP_SHIFT                16
+#define SDHC_XFERTYP_RSPTYP_WIDTH                2
+#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK                  0x80000u
+#define SDHC_XFERTYP_CCCEN_SHIFT                 19
+#define SDHC_XFERTYP_CCCEN_WIDTH                 1
+#define SDHC_XFERTYP_CCCEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CCCEN_SHIFT))&SDHC_XFERTYP_CCCEN_MASK)
+#define SDHC_XFERTYP_CICEN_MASK                  0x100000u
+#define SDHC_XFERTYP_CICEN_SHIFT                 20
+#define SDHC_XFERTYP_CICEN_WIDTH                 1
+#define SDHC_XFERTYP_CICEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CICEN_SHIFT))&SDHC_XFERTYP_CICEN_MASK)
+#define SDHC_XFERTYP_DPSEL_MASK                  0x200000u
+#define SDHC_XFERTYP_DPSEL_SHIFT                 21
+#define SDHC_XFERTYP_DPSEL_WIDTH                 1
+#define SDHC_XFERTYP_DPSEL(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DPSEL_SHIFT))&SDHC_XFERTYP_DPSEL_MASK)
+#define SDHC_XFERTYP_CMDTYP_MASK                 0xC00000u
+#define SDHC_XFERTYP_CMDTYP_SHIFT                22
+#define SDHC_XFERTYP_CMDTYP_WIDTH                2
+#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK                 0x3F000000u
+#define SDHC_XFERTYP_CMDINX_SHIFT                24
+#define SDHC_XFERTYP_CMDINX_WIDTH                6
+#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
+/* CMDRSP Bit Fields */
+#define SDHC_CMDRSP_CMDRSP0_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP0_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP0_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP1_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP1_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP2_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP2_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP3_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP3_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
+/* DATPORT Bit Fields */
+#define SDHC_DATPORT_DATCONT_MASK                0xFFFFFFFFu
+#define SDHC_DATPORT_DATCONT_SHIFT               0
+#define SDHC_DATPORT_DATCONT_WIDTH               32
+#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
+/* PRSSTAT Bit Fields */
+#define SDHC_PRSSTAT_CIHB_MASK                   0x1u
+#define SDHC_PRSSTAT_CIHB_SHIFT                  0
+#define SDHC_PRSSTAT_CIHB_WIDTH                  1
+#define SDHC_PRSSTAT_CIHB(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CIHB_SHIFT))&SDHC_PRSSTAT_CIHB_MASK)
+#define SDHC_PRSSTAT_CDIHB_MASK                  0x2u
+#define SDHC_PRSSTAT_CDIHB_SHIFT                 1
+#define SDHC_PRSSTAT_CDIHB_WIDTH                 1
+#define SDHC_PRSSTAT_CDIHB(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CDIHB_SHIFT))&SDHC_PRSSTAT_CDIHB_MASK)
+#define SDHC_PRSSTAT_DLA_MASK                    0x4u
+#define SDHC_PRSSTAT_DLA_SHIFT                   2
+#define SDHC_PRSSTAT_DLA_WIDTH                   1
+#define SDHC_PRSSTAT_DLA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLA_SHIFT))&SDHC_PRSSTAT_DLA_MASK)
+#define SDHC_PRSSTAT_SDSTB_MASK                  0x8u
+#define SDHC_PRSSTAT_SDSTB_SHIFT                 3
+#define SDHC_PRSSTAT_SDSTB_WIDTH                 1
+#define SDHC_PRSSTAT_SDSTB(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDSTB_SHIFT))&SDHC_PRSSTAT_SDSTB_MASK)
+#define SDHC_PRSSTAT_IPGOFF_MASK                 0x10u
+#define SDHC_PRSSTAT_IPGOFF_SHIFT                4
+#define SDHC_PRSSTAT_IPGOFF_WIDTH                1
+#define SDHC_PRSSTAT_IPGOFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_IPGOFF_SHIFT))&SDHC_PRSSTAT_IPGOFF_MASK)
+#define SDHC_PRSSTAT_HCKOFF_MASK                 0x20u
+#define SDHC_PRSSTAT_HCKOFF_SHIFT                5
+#define SDHC_PRSSTAT_HCKOFF_WIDTH                1
+#define SDHC_PRSSTAT_HCKOFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_HCKOFF_SHIFT))&SDHC_PRSSTAT_HCKOFF_MASK)
+#define SDHC_PRSSTAT_PEROFF_MASK                 0x40u
+#define SDHC_PRSSTAT_PEROFF_SHIFT                6
+#define SDHC_PRSSTAT_PEROFF_WIDTH                1
+#define SDHC_PRSSTAT_PEROFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_PEROFF_SHIFT))&SDHC_PRSSTAT_PEROFF_MASK)
+#define SDHC_PRSSTAT_SDOFF_MASK                  0x80u
+#define SDHC_PRSSTAT_SDOFF_SHIFT                 7
+#define SDHC_PRSSTAT_SDOFF_WIDTH                 1
+#define SDHC_PRSSTAT_SDOFF(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDOFF_SHIFT))&SDHC_PRSSTAT_SDOFF_MASK)
+#define SDHC_PRSSTAT_WTA_MASK                    0x100u
+#define SDHC_PRSSTAT_WTA_SHIFT                   8
+#define SDHC_PRSSTAT_WTA_WIDTH                   1
+#define SDHC_PRSSTAT_WTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_WTA_SHIFT))&SDHC_PRSSTAT_WTA_MASK)
+#define SDHC_PRSSTAT_RTA_MASK                    0x200u
+#define SDHC_PRSSTAT_RTA_SHIFT                   9
+#define SDHC_PRSSTAT_RTA_WIDTH                   1
+#define SDHC_PRSSTAT_RTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_RTA_SHIFT))&SDHC_PRSSTAT_RTA_MASK)
+#define SDHC_PRSSTAT_BWEN_MASK                   0x400u
+#define SDHC_PRSSTAT_BWEN_SHIFT                  10
+#define SDHC_PRSSTAT_BWEN_WIDTH                  1
+#define SDHC_PRSSTAT_BWEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BWEN_SHIFT))&SDHC_PRSSTAT_BWEN_MASK)
+#define SDHC_PRSSTAT_BREN_MASK                   0x800u
+#define SDHC_PRSSTAT_BREN_SHIFT                  11
+#define SDHC_PRSSTAT_BREN_WIDTH                  1
+#define SDHC_PRSSTAT_BREN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BREN_SHIFT))&SDHC_PRSSTAT_BREN_MASK)
+#define SDHC_PRSSTAT_CINS_MASK                   0x10000u
+#define SDHC_PRSSTAT_CINS_SHIFT                  16
+#define SDHC_PRSSTAT_CINS_WIDTH                  1
+#define SDHC_PRSSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CINS_SHIFT))&SDHC_PRSSTAT_CINS_MASK)
+#define SDHC_PRSSTAT_CLSL_MASK                   0x800000u
+#define SDHC_PRSSTAT_CLSL_SHIFT                  23
+#define SDHC_PRSSTAT_CLSL_WIDTH                  1
+#define SDHC_PRSSTAT_CLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CLSL_SHIFT))&SDHC_PRSSTAT_CLSL_MASK)
+#define SDHC_PRSSTAT_DLSL_MASK                   0xFF000000u
+#define SDHC_PRSSTAT_DLSL_SHIFT                  24
+#define SDHC_PRSSTAT_DLSL_WIDTH                  8
+#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
+/* PROCTL Bit Fields */
+#define SDHC_PROCTL_LCTL_MASK                    0x1u
+#define SDHC_PROCTL_LCTL_SHIFT                   0
+#define SDHC_PROCTL_LCTL_WIDTH                   1
+#define SDHC_PROCTL_LCTL(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_LCTL_SHIFT))&SDHC_PROCTL_LCTL_MASK)
+#define SDHC_PROCTL_DTW_MASK                     0x6u
+#define SDHC_PROCTL_DTW_SHIFT                    1
+#define SDHC_PROCTL_DTW_WIDTH                    2
+#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK                    0x8u
+#define SDHC_PROCTL_D3CD_SHIFT                   3
+#define SDHC_PROCTL_D3CD_WIDTH                   1
+#define SDHC_PROCTL_D3CD(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_D3CD_SHIFT))&SDHC_PROCTL_D3CD_MASK)
+#define SDHC_PROCTL_EMODE_MASK                   0x30u
+#define SDHC_PROCTL_EMODE_SHIFT                  4
+#define SDHC_PROCTL_EMODE_WIDTH                  2
+#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK                    0x40u
+#define SDHC_PROCTL_CDTL_SHIFT                   6
+#define SDHC_PROCTL_CDTL_WIDTH                   1
+#define SDHC_PROCTL_CDTL(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDTL_SHIFT))&SDHC_PROCTL_CDTL_MASK)
+#define SDHC_PROCTL_CDSS_MASK                    0x80u
+#define SDHC_PROCTL_CDSS_SHIFT                   7
+#define SDHC_PROCTL_CDSS_WIDTH                   1
+#define SDHC_PROCTL_CDSS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDSS_SHIFT))&SDHC_PROCTL_CDSS_MASK)
+#define SDHC_PROCTL_DMAS_MASK                    0x300u
+#define SDHC_PROCTL_DMAS_SHIFT                   8
+#define SDHC_PROCTL_DMAS_WIDTH                   2
+#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK                 0x10000u
+#define SDHC_PROCTL_SABGREQ_SHIFT                16
+#define SDHC_PROCTL_SABGREQ_WIDTH                1
+#define SDHC_PROCTL_SABGREQ(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_SABGREQ_SHIFT))&SDHC_PROCTL_SABGREQ_MASK)
+#define SDHC_PROCTL_CREQ_MASK                    0x20000u
+#define SDHC_PROCTL_CREQ_SHIFT                   17
+#define SDHC_PROCTL_CREQ_WIDTH                   1
+#define SDHC_PROCTL_CREQ(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CREQ_SHIFT))&SDHC_PROCTL_CREQ_MASK)
+#define SDHC_PROCTL_RWCTL_MASK                   0x40000u
+#define SDHC_PROCTL_RWCTL_SHIFT                  18
+#define SDHC_PROCTL_RWCTL_WIDTH                  1
+#define SDHC_PROCTL_RWCTL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_RWCTL_SHIFT))&SDHC_PROCTL_RWCTL_MASK)
+#define SDHC_PROCTL_IABG_MASK                    0x80000u
+#define SDHC_PROCTL_IABG_SHIFT                   19
+#define SDHC_PROCTL_IABG_WIDTH                   1
+#define SDHC_PROCTL_IABG(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_IABG_SHIFT))&SDHC_PROCTL_IABG_MASK)
+#define SDHC_PROCTL_WECINT_MASK                  0x1000000u
+#define SDHC_PROCTL_WECINT_SHIFT                 24
+#define SDHC_PROCTL_WECINT_WIDTH                 1
+#define SDHC_PROCTL_WECINT(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINT_SHIFT))&SDHC_PROCTL_WECINT_MASK)
+#define SDHC_PROCTL_WECINS_MASK                  0x2000000u
+#define SDHC_PROCTL_WECINS_SHIFT                 25
+#define SDHC_PROCTL_WECINS_WIDTH                 1
+#define SDHC_PROCTL_WECINS(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINS_SHIFT))&SDHC_PROCTL_WECINS_MASK)
+#define SDHC_PROCTL_WECRM_MASK                   0x4000000u
+#define SDHC_PROCTL_WECRM_SHIFT                  26
+#define SDHC_PROCTL_WECRM_WIDTH                  1
+#define SDHC_PROCTL_WECRM(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECRM_SHIFT))&SDHC_PROCTL_WECRM_MASK)
+/* SYSCTL Bit Fields */
+#define SDHC_SYSCTL_IPGEN_MASK                   0x1u
+#define SDHC_SYSCTL_IPGEN_SHIFT                  0
+#define SDHC_SYSCTL_IPGEN_WIDTH                  1
+#define SDHC_SYSCTL_IPGEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_IPGEN_SHIFT))&SDHC_SYSCTL_IPGEN_MASK)
+#define SDHC_SYSCTL_HCKEN_MASK                   0x2u
+#define SDHC_SYSCTL_HCKEN_SHIFT                  1
+#define SDHC_SYSCTL_HCKEN_WIDTH                  1
+#define SDHC_SYSCTL_HCKEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_HCKEN_SHIFT))&SDHC_SYSCTL_HCKEN_MASK)
+#define SDHC_SYSCTL_PEREN_MASK                   0x4u
+#define SDHC_SYSCTL_PEREN_SHIFT                  2
+#define SDHC_SYSCTL_PEREN_WIDTH                  1
+#define SDHC_SYSCTL_PEREN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_PEREN_SHIFT))&SDHC_SYSCTL_PEREN_MASK)
+#define SDHC_SYSCTL_SDCLKEN_MASK                 0x8u
+#define SDHC_SYSCTL_SDCLKEN_SHIFT                3
+#define SDHC_SYSCTL_SDCLKEN_WIDTH                1
+#define SDHC_SYSCTL_SDCLKEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKEN_SHIFT))&SDHC_SYSCTL_SDCLKEN_MASK)
+#define SDHC_SYSCTL_DVS_MASK                     0xF0u
+#define SDHC_SYSCTL_DVS_SHIFT                    4
+#define SDHC_SYSCTL_DVS_WIDTH                    4
+#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK                 0xFF00u
+#define SDHC_SYSCTL_SDCLKFS_SHIFT                8
+#define SDHC_SYSCTL_SDCLKFS_WIDTH                8
+#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK                   0xF0000u
+#define SDHC_SYSCTL_DTOCV_SHIFT                  16
+#define SDHC_SYSCTL_DTOCV_WIDTH                  4
+#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK                    0x1000000u
+#define SDHC_SYSCTL_RSTA_SHIFT                   24
+#define SDHC_SYSCTL_RSTA_WIDTH                   1
+#define SDHC_SYSCTL_RSTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTA_SHIFT))&SDHC_SYSCTL_RSTA_MASK)
+#define SDHC_SYSCTL_RSTC_MASK                    0x2000000u
+#define SDHC_SYSCTL_RSTC_SHIFT                   25
+#define SDHC_SYSCTL_RSTC_WIDTH                   1
+#define SDHC_SYSCTL_RSTC(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTC_SHIFT))&SDHC_SYSCTL_RSTC_MASK)
+#define SDHC_SYSCTL_RSTD_MASK                    0x4000000u
+#define SDHC_SYSCTL_RSTD_SHIFT                   26
+#define SDHC_SYSCTL_RSTD_WIDTH                   1
+#define SDHC_SYSCTL_RSTD(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTD_SHIFT))&SDHC_SYSCTL_RSTD_MASK)
+#define SDHC_SYSCTL_INITA_MASK                   0x8000000u
+#define SDHC_SYSCTL_INITA_SHIFT                  27
+#define SDHC_SYSCTL_INITA_WIDTH                  1
+#define SDHC_SYSCTL_INITA(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_INITA_SHIFT))&SDHC_SYSCTL_INITA_MASK)
+/* IRQSTAT Bit Fields */
+#define SDHC_IRQSTAT_CC_MASK                     0x1u
+#define SDHC_IRQSTAT_CC_SHIFT                    0
+#define SDHC_IRQSTAT_CC_WIDTH                    1
+#define SDHC_IRQSTAT_CC(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CC_SHIFT))&SDHC_IRQSTAT_CC_MASK)
+#define SDHC_IRQSTAT_TC_MASK                     0x2u
+#define SDHC_IRQSTAT_TC_SHIFT                    1
+#define SDHC_IRQSTAT_TC_WIDTH                    1
+#define SDHC_IRQSTAT_TC(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_TC_SHIFT))&SDHC_IRQSTAT_TC_MASK)
+#define SDHC_IRQSTAT_BGE_MASK                    0x4u
+#define SDHC_IRQSTAT_BGE_SHIFT                   2
+#define SDHC_IRQSTAT_BGE_WIDTH                   1
+#define SDHC_IRQSTAT_BGE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BGE_SHIFT))&SDHC_IRQSTAT_BGE_MASK)
+#define SDHC_IRQSTAT_DINT_MASK                   0x8u
+#define SDHC_IRQSTAT_DINT_SHIFT                  3
+#define SDHC_IRQSTAT_DINT_WIDTH                  1
+#define SDHC_IRQSTAT_DINT(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DINT_SHIFT))&SDHC_IRQSTAT_DINT_MASK)
+#define SDHC_IRQSTAT_BWR_MASK                    0x10u
+#define SDHC_IRQSTAT_BWR_SHIFT                   4
+#define SDHC_IRQSTAT_BWR_WIDTH                   1
+#define SDHC_IRQSTAT_BWR(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BWR_SHIFT))&SDHC_IRQSTAT_BWR_MASK)
+#define SDHC_IRQSTAT_BRR_MASK                    0x20u
+#define SDHC_IRQSTAT_BRR_SHIFT                   5
+#define SDHC_IRQSTAT_BRR_WIDTH                   1
+#define SDHC_IRQSTAT_BRR(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BRR_SHIFT))&SDHC_IRQSTAT_BRR_MASK)
+#define SDHC_IRQSTAT_CINS_MASK                   0x40u
+#define SDHC_IRQSTAT_CINS_SHIFT                  6
+#define SDHC_IRQSTAT_CINS_WIDTH                  1
+#define SDHC_IRQSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINS_SHIFT))&SDHC_IRQSTAT_CINS_MASK)
+#define SDHC_IRQSTAT_CRM_MASK                    0x80u
+#define SDHC_IRQSTAT_CRM_SHIFT                   7
+#define SDHC_IRQSTAT_CRM_WIDTH                   1
+#define SDHC_IRQSTAT_CRM(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CRM_SHIFT))&SDHC_IRQSTAT_CRM_MASK)
+#define SDHC_IRQSTAT_CINT_MASK                   0x100u
+#define SDHC_IRQSTAT_CINT_SHIFT                  8
+#define SDHC_IRQSTAT_CINT_WIDTH                  1
+#define SDHC_IRQSTAT_CINT(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINT_SHIFT))&SDHC_IRQSTAT_CINT_MASK)
+#define SDHC_IRQSTAT_CTOE_MASK                   0x10000u
+#define SDHC_IRQSTAT_CTOE_SHIFT                  16
+#define SDHC_IRQSTAT_CTOE_WIDTH                  1
+#define SDHC_IRQSTAT_CTOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CTOE_SHIFT))&SDHC_IRQSTAT_CTOE_MASK)
+#define SDHC_IRQSTAT_CCE_MASK                    0x20000u
+#define SDHC_IRQSTAT_CCE_SHIFT                   17
+#define SDHC_IRQSTAT_CCE_WIDTH                   1
+#define SDHC_IRQSTAT_CCE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CCE_SHIFT))&SDHC_IRQSTAT_CCE_MASK)
+#define SDHC_IRQSTAT_CEBE_MASK                   0x40000u
+#define SDHC_IRQSTAT_CEBE_SHIFT                  18
+#define SDHC_IRQSTAT_CEBE_WIDTH                  1
+#define SDHC_IRQSTAT_CEBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CEBE_SHIFT))&SDHC_IRQSTAT_CEBE_MASK)
+#define SDHC_IRQSTAT_CIE_MASK                    0x80000u
+#define SDHC_IRQSTAT_CIE_SHIFT                   19
+#define SDHC_IRQSTAT_CIE_WIDTH                   1
+#define SDHC_IRQSTAT_CIE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CIE_SHIFT))&SDHC_IRQSTAT_CIE_MASK)
+#define SDHC_IRQSTAT_DTOE_MASK                   0x100000u
+#define SDHC_IRQSTAT_DTOE_SHIFT                  20
+#define SDHC_IRQSTAT_DTOE_WIDTH                  1
+#define SDHC_IRQSTAT_DTOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DTOE_SHIFT))&SDHC_IRQSTAT_DTOE_MASK)
+#define SDHC_IRQSTAT_DCE_MASK                    0x200000u
+#define SDHC_IRQSTAT_DCE_SHIFT                   21
+#define SDHC_IRQSTAT_DCE_WIDTH                   1
+#define SDHC_IRQSTAT_DCE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DCE_SHIFT))&SDHC_IRQSTAT_DCE_MASK)
+#define SDHC_IRQSTAT_DEBE_MASK                   0x400000u
+#define SDHC_IRQSTAT_DEBE_SHIFT                  22
+#define SDHC_IRQSTAT_DEBE_WIDTH                  1
+#define SDHC_IRQSTAT_DEBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DEBE_SHIFT))&SDHC_IRQSTAT_DEBE_MASK)
+#define SDHC_IRQSTAT_AC12E_MASK                  0x1000000u
+#define SDHC_IRQSTAT_AC12E_SHIFT                 24
+#define SDHC_IRQSTAT_AC12E_WIDTH                 1
+#define SDHC_IRQSTAT_AC12E(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_AC12E_SHIFT))&SDHC_IRQSTAT_AC12E_MASK)
+#define SDHC_IRQSTAT_DMAE_MASK                   0x10000000u
+#define SDHC_IRQSTAT_DMAE_SHIFT                  28
+#define SDHC_IRQSTAT_DMAE_WIDTH                  1
+#define SDHC_IRQSTAT_DMAE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DMAE_SHIFT))&SDHC_IRQSTAT_DMAE_MASK)
+/* IRQSTATEN Bit Fields */
+#define SDHC_IRQSTATEN_CCSEN_MASK                0x1u
+#define SDHC_IRQSTATEN_CCSEN_SHIFT               0
+#define SDHC_IRQSTATEN_CCSEN_WIDTH               1
+#define SDHC_IRQSTATEN_CCSEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCSEN_SHIFT))&SDHC_IRQSTATEN_CCSEN_MASK)
+#define SDHC_IRQSTATEN_TCSEN_MASK                0x2u
+#define SDHC_IRQSTATEN_TCSEN_SHIFT               1
+#define SDHC_IRQSTATEN_TCSEN_WIDTH               1
+#define SDHC_IRQSTATEN_TCSEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_TCSEN_SHIFT))&SDHC_IRQSTATEN_TCSEN_MASK)
+#define SDHC_IRQSTATEN_BGESEN_MASK               0x4u
+#define SDHC_IRQSTATEN_BGESEN_SHIFT              2
+#define SDHC_IRQSTATEN_BGESEN_WIDTH              1
+#define SDHC_IRQSTATEN_BGESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BGESEN_SHIFT))&SDHC_IRQSTATEN_BGESEN_MASK)
+#define SDHC_IRQSTATEN_DINTSEN_MASK              0x8u
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT             3
+#define SDHC_IRQSTATEN_DINTSEN_WIDTH             1
+#define SDHC_IRQSTATEN_DINTSEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DINTSEN_SHIFT))&SDHC_IRQSTATEN_DINTSEN_MASK)
+#define SDHC_IRQSTATEN_BWRSEN_MASK               0x10u
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT              4
+#define SDHC_IRQSTATEN_BWRSEN_WIDTH              1
+#define SDHC_IRQSTATEN_BWRSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BWRSEN_SHIFT))&SDHC_IRQSTATEN_BWRSEN_MASK)
+#define SDHC_IRQSTATEN_BRRSEN_MASK               0x20u
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT              5
+#define SDHC_IRQSTATEN_BRRSEN_WIDTH              1
+#define SDHC_IRQSTATEN_BRRSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BRRSEN_SHIFT))&SDHC_IRQSTATEN_BRRSEN_MASK)
+#define SDHC_IRQSTATEN_CINSEN_MASK               0x40u
+#define SDHC_IRQSTATEN_CINSEN_SHIFT              6
+#define SDHC_IRQSTATEN_CINSEN_WIDTH              1
+#define SDHC_IRQSTATEN_CINSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINSEN_SHIFT))&SDHC_IRQSTATEN_CINSEN_MASK)
+#define SDHC_IRQSTATEN_CRMSEN_MASK               0x80u
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT              7
+#define SDHC_IRQSTATEN_CRMSEN_WIDTH              1
+#define SDHC_IRQSTATEN_CRMSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CRMSEN_SHIFT))&SDHC_IRQSTATEN_CRMSEN_MASK)
+#define SDHC_IRQSTATEN_CINTSEN_MASK              0x100u
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT             8
+#define SDHC_IRQSTATEN_CINTSEN_WIDTH             1
+#define SDHC_IRQSTATEN_CINTSEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINTSEN_SHIFT))&SDHC_IRQSTATEN_CINTSEN_MASK)
+#define SDHC_IRQSTATEN_CTOESEN_MASK              0x10000u
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT             16
+#define SDHC_IRQSTATEN_CTOESEN_WIDTH             1
+#define SDHC_IRQSTATEN_CTOESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CTOESEN_SHIFT))&SDHC_IRQSTATEN_CTOESEN_MASK)
+#define SDHC_IRQSTATEN_CCESEN_MASK               0x20000u
+#define SDHC_IRQSTATEN_CCESEN_SHIFT              17
+#define SDHC_IRQSTATEN_CCESEN_WIDTH              1
+#define SDHC_IRQSTATEN_CCESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCESEN_SHIFT))&SDHC_IRQSTATEN_CCESEN_MASK)
+#define SDHC_IRQSTATEN_CEBESEN_MASK              0x40000u
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT             18
+#define SDHC_IRQSTATEN_CEBESEN_WIDTH             1
+#define SDHC_IRQSTATEN_CEBESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CEBESEN_SHIFT))&SDHC_IRQSTATEN_CEBESEN_MASK)
+#define SDHC_IRQSTATEN_CIESEN_MASK               0x80000u
+#define SDHC_IRQSTATEN_CIESEN_SHIFT              19
+#define SDHC_IRQSTATEN_CIESEN_WIDTH              1
+#define SDHC_IRQSTATEN_CIESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CIESEN_SHIFT))&SDHC_IRQSTATEN_CIESEN_MASK)
+#define SDHC_IRQSTATEN_DTOESEN_MASK              0x100000u
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT             20
+#define SDHC_IRQSTATEN_DTOESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DTOESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DTOESEN_SHIFT))&SDHC_IRQSTATEN_DTOESEN_MASK)
+#define SDHC_IRQSTATEN_DCESEN_MASK               0x200000u
+#define SDHC_IRQSTATEN_DCESEN_SHIFT              21
+#define SDHC_IRQSTATEN_DCESEN_WIDTH              1
+#define SDHC_IRQSTATEN_DCESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DCESEN_SHIFT))&SDHC_IRQSTATEN_DCESEN_MASK)
+#define SDHC_IRQSTATEN_DEBESEN_MASK              0x400000u
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT             22
+#define SDHC_IRQSTATEN_DEBESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DEBESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DEBESEN_SHIFT))&SDHC_IRQSTATEN_DEBESEN_MASK)
+#define SDHC_IRQSTATEN_AC12ESEN_MASK             0x1000000u
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT            24
+#define SDHC_IRQSTATEN_AC12ESEN_WIDTH            1
+#define SDHC_IRQSTATEN_AC12ESEN(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_AC12ESEN_SHIFT))&SDHC_IRQSTATEN_AC12ESEN_MASK)
+#define SDHC_IRQSTATEN_DMAESEN_MASK              0x10000000u
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT             28
+#define SDHC_IRQSTATEN_DMAESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DMAESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DMAESEN_SHIFT))&SDHC_IRQSTATEN_DMAESEN_MASK)
+/* IRQSIGEN Bit Fields */
+#define SDHC_IRQSIGEN_CCIEN_MASK                 0x1u
+#define SDHC_IRQSIGEN_CCIEN_SHIFT                0
+#define SDHC_IRQSIGEN_CCIEN_WIDTH                1
+#define SDHC_IRQSIGEN_CCIEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCIEN_SHIFT))&SDHC_IRQSIGEN_CCIEN_MASK)
+#define SDHC_IRQSIGEN_TCIEN_MASK                 0x2u
+#define SDHC_IRQSIGEN_TCIEN_SHIFT                1
+#define SDHC_IRQSIGEN_TCIEN_WIDTH                1
+#define SDHC_IRQSIGEN_TCIEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_TCIEN_SHIFT))&SDHC_IRQSIGEN_TCIEN_MASK)
+#define SDHC_IRQSIGEN_BGEIEN_MASK                0x4u
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT               2
+#define SDHC_IRQSIGEN_BGEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BGEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BGEIEN_SHIFT))&SDHC_IRQSIGEN_BGEIEN_MASK)
+#define SDHC_IRQSIGEN_DINTIEN_MASK               0x8u
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT              3
+#define SDHC_IRQSIGEN_DINTIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DINTIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DINTIEN_SHIFT))&SDHC_IRQSIGEN_DINTIEN_MASK)
+#define SDHC_IRQSIGEN_BWRIEN_MASK                0x10u
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT               4
+#define SDHC_IRQSIGEN_BWRIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BWRIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BWRIEN_SHIFT))&SDHC_IRQSIGEN_BWRIEN_MASK)
+#define SDHC_IRQSIGEN_BRRIEN_MASK                0x20u
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT               5
+#define SDHC_IRQSIGEN_BRRIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BRRIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BRRIEN_SHIFT))&SDHC_IRQSIGEN_BRRIEN_MASK)
+#define SDHC_IRQSIGEN_CINSIEN_MASK               0x40u
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT              6
+#define SDHC_IRQSIGEN_CINSIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CINSIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINSIEN_SHIFT))&SDHC_IRQSIGEN_CINSIEN_MASK)
+#define SDHC_IRQSIGEN_CRMIEN_MASK                0x80u
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT               7
+#define SDHC_IRQSIGEN_CRMIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CRMIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CRMIEN_SHIFT))&SDHC_IRQSIGEN_CRMIEN_MASK)
+#define SDHC_IRQSIGEN_CINTIEN_MASK               0x100u
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT              8
+#define SDHC_IRQSIGEN_CINTIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CINTIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINTIEN_SHIFT))&SDHC_IRQSIGEN_CINTIEN_MASK)
+#define SDHC_IRQSIGEN_CTOEIEN_MASK               0x10000u
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT              16
+#define SDHC_IRQSIGEN_CTOEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CTOEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CTOEIEN_SHIFT))&SDHC_IRQSIGEN_CTOEIEN_MASK)
+#define SDHC_IRQSIGEN_CCEIEN_MASK                0x20000u
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT               17
+#define SDHC_IRQSIGEN_CCEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CCEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCEIEN_SHIFT))&SDHC_IRQSIGEN_CCEIEN_MASK)
+#define SDHC_IRQSIGEN_CEBEIEN_MASK               0x40000u
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT              18
+#define SDHC_IRQSIGEN_CEBEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CEBEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CEBEIEN_SHIFT))&SDHC_IRQSIGEN_CEBEIEN_MASK)
+#define SDHC_IRQSIGEN_CIEIEN_MASK                0x80000u
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT               19
+#define SDHC_IRQSIGEN_CIEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CIEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CIEIEN_SHIFT))&SDHC_IRQSIGEN_CIEIEN_MASK)
+#define SDHC_IRQSIGEN_DTOEIEN_MASK               0x100000u
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT              20
+#define SDHC_IRQSIGEN_DTOEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DTOEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DTOEIEN_SHIFT))&SDHC_IRQSIGEN_DTOEIEN_MASK)
+#define SDHC_IRQSIGEN_DCEIEN_MASK                0x200000u
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT               21
+#define SDHC_IRQSIGEN_DCEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_DCEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DCEIEN_SHIFT))&SDHC_IRQSIGEN_DCEIEN_MASK)
+#define SDHC_IRQSIGEN_DEBEIEN_MASK               0x400000u
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT              22
+#define SDHC_IRQSIGEN_DEBEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DEBEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DEBEIEN_SHIFT))&SDHC_IRQSIGEN_DEBEIEN_MASK)
+#define SDHC_IRQSIGEN_AC12EIEN_MASK              0x1000000u
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT             24
+#define SDHC_IRQSIGEN_AC12EIEN_WIDTH             1
+#define SDHC_IRQSIGEN_AC12EIEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_AC12EIEN_SHIFT))&SDHC_IRQSIGEN_AC12EIEN_MASK)
+#define SDHC_IRQSIGEN_DMAEIEN_MASK               0x10000000u
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT              28
+#define SDHC_IRQSIGEN_DMAEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DMAEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DMAEIEN_SHIFT))&SDHC_IRQSIGEN_DMAEIEN_MASK)
+/* AC12ERR Bit Fields */
+#define SDHC_AC12ERR_AC12NE_MASK                 0x1u
+#define SDHC_AC12ERR_AC12NE_SHIFT                0
+#define SDHC_AC12ERR_AC12NE_WIDTH                1
+#define SDHC_AC12ERR_AC12NE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12NE_SHIFT))&SDHC_AC12ERR_AC12NE_MASK)
+#define SDHC_AC12ERR_AC12TOE_MASK                0x2u
+#define SDHC_AC12ERR_AC12TOE_SHIFT               1
+#define SDHC_AC12ERR_AC12TOE_WIDTH               1
+#define SDHC_AC12ERR_AC12TOE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12TOE_SHIFT))&SDHC_AC12ERR_AC12TOE_MASK)
+#define SDHC_AC12ERR_AC12EBE_MASK                0x4u
+#define SDHC_AC12ERR_AC12EBE_SHIFT               2
+#define SDHC_AC12ERR_AC12EBE_WIDTH               1
+#define SDHC_AC12ERR_AC12EBE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12EBE_SHIFT))&SDHC_AC12ERR_AC12EBE_MASK)
+#define SDHC_AC12ERR_AC12CE_MASK                 0x8u
+#define SDHC_AC12ERR_AC12CE_SHIFT                3
+#define SDHC_AC12ERR_AC12CE_WIDTH                1
+#define SDHC_AC12ERR_AC12CE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12CE_SHIFT))&SDHC_AC12ERR_AC12CE_MASK)
+#define SDHC_AC12ERR_AC12IE_MASK                 0x10u
+#define SDHC_AC12ERR_AC12IE_SHIFT                4
+#define SDHC_AC12ERR_AC12IE_WIDTH                1
+#define SDHC_AC12ERR_AC12IE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12IE_SHIFT))&SDHC_AC12ERR_AC12IE_MASK)
+#define SDHC_AC12ERR_CNIBAC12E_MASK              0x80u
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT             7
+#define SDHC_AC12ERR_CNIBAC12E_WIDTH             1
+#define SDHC_AC12ERR_CNIBAC12E(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_CNIBAC12E_SHIFT))&SDHC_AC12ERR_CNIBAC12E_MASK)
+/* HTCAPBLT Bit Fields */
+#define SDHC_HTCAPBLT_MBL_MASK                   0x70000u
+#define SDHC_HTCAPBLT_MBL_SHIFT                  16
+#define SDHC_HTCAPBLT_MBL_WIDTH                  3
+#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK                 0x100000u
+#define SDHC_HTCAPBLT_ADMAS_SHIFT                20
+#define SDHC_HTCAPBLT_ADMAS_WIDTH                1
+#define SDHC_HTCAPBLT_ADMAS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_ADMAS_SHIFT))&SDHC_HTCAPBLT_ADMAS_MASK)
+#define SDHC_HTCAPBLT_HSS_MASK                   0x200000u
+#define SDHC_HTCAPBLT_HSS_SHIFT                  21
+#define SDHC_HTCAPBLT_HSS_WIDTH                  1
+#define SDHC_HTCAPBLT_HSS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_HSS_SHIFT))&SDHC_HTCAPBLT_HSS_MASK)
+#define SDHC_HTCAPBLT_DMAS_MASK                  0x400000u
+#define SDHC_HTCAPBLT_DMAS_SHIFT                 22
+#define SDHC_HTCAPBLT_DMAS_WIDTH                 1
+#define SDHC_HTCAPBLT_DMAS(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_DMAS_SHIFT))&SDHC_HTCAPBLT_DMAS_MASK)
+#define SDHC_HTCAPBLT_SRS_MASK                   0x800000u
+#define SDHC_HTCAPBLT_SRS_SHIFT                  23
+#define SDHC_HTCAPBLT_SRS_WIDTH                  1
+#define SDHC_HTCAPBLT_SRS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_SRS_SHIFT))&SDHC_HTCAPBLT_SRS_MASK)
+#define SDHC_HTCAPBLT_VS33_MASK                  0x1000000u
+#define SDHC_HTCAPBLT_VS33_SHIFT                 24
+#define SDHC_HTCAPBLT_VS33_WIDTH                 1
+#define SDHC_HTCAPBLT_VS33(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_VS33_SHIFT))&SDHC_HTCAPBLT_VS33_MASK)
+/* WML Bit Fields */
+#define SDHC_WML_RDWML_MASK                      0xFFu
+#define SDHC_WML_RDWML_SHIFT                     0
+#define SDHC_WML_RDWML_WIDTH                     8
+#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK                      0xFF0000u
+#define SDHC_WML_WRWML_SHIFT                     16
+#define SDHC_WML_WRWML_WIDTH                     8
+#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
+/* FEVT Bit Fields */
+#define SDHC_FEVT_AC12NE_MASK                    0x1u
+#define SDHC_FEVT_AC12NE_SHIFT                   0
+#define SDHC_FEVT_AC12NE_WIDTH                   1
+#define SDHC_FEVT_AC12NE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12NE_SHIFT))&SDHC_FEVT_AC12NE_MASK)
+#define SDHC_FEVT_AC12TOE_MASK                   0x2u
+#define SDHC_FEVT_AC12TOE_SHIFT                  1
+#define SDHC_FEVT_AC12TOE_WIDTH                  1
+#define SDHC_FEVT_AC12TOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12TOE_SHIFT))&SDHC_FEVT_AC12TOE_MASK)
+#define SDHC_FEVT_AC12CE_MASK                    0x4u
+#define SDHC_FEVT_AC12CE_SHIFT                   2
+#define SDHC_FEVT_AC12CE_WIDTH                   1
+#define SDHC_FEVT_AC12CE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12CE_SHIFT))&SDHC_FEVT_AC12CE_MASK)
+#define SDHC_FEVT_AC12EBE_MASK                   0x8u
+#define SDHC_FEVT_AC12EBE_SHIFT                  3
+#define SDHC_FEVT_AC12EBE_WIDTH                  1
+#define SDHC_FEVT_AC12EBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12EBE_SHIFT))&SDHC_FEVT_AC12EBE_MASK)
+#define SDHC_FEVT_AC12IE_MASK                    0x10u
+#define SDHC_FEVT_AC12IE_SHIFT                   4
+#define SDHC_FEVT_AC12IE_WIDTH                   1
+#define SDHC_FEVT_AC12IE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12IE_SHIFT))&SDHC_FEVT_AC12IE_MASK)
+#define SDHC_FEVT_CNIBAC12E_MASK                 0x80u
+#define SDHC_FEVT_CNIBAC12E_SHIFT                7
+#define SDHC_FEVT_CNIBAC12E_WIDTH                1
+#define SDHC_FEVT_CNIBAC12E(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CNIBAC12E_SHIFT))&SDHC_FEVT_CNIBAC12E_MASK)
+#define SDHC_FEVT_CTOE_MASK                      0x10000u
+#define SDHC_FEVT_CTOE_SHIFT                     16
+#define SDHC_FEVT_CTOE_WIDTH                     1
+#define SDHC_FEVT_CTOE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CTOE_SHIFT))&SDHC_FEVT_CTOE_MASK)
+#define SDHC_FEVT_CCE_MASK                       0x20000u
+#define SDHC_FEVT_CCE_SHIFT                      17
+#define SDHC_FEVT_CCE_WIDTH                      1
+#define SDHC_FEVT_CCE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CCE_SHIFT))&SDHC_FEVT_CCE_MASK)
+#define SDHC_FEVT_CEBE_MASK                      0x40000u
+#define SDHC_FEVT_CEBE_SHIFT                     18
+#define SDHC_FEVT_CEBE_WIDTH                     1
+#define SDHC_FEVT_CEBE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CEBE_SHIFT))&SDHC_FEVT_CEBE_MASK)
+#define SDHC_FEVT_CIE_MASK                       0x80000u
+#define SDHC_FEVT_CIE_SHIFT                      19
+#define SDHC_FEVT_CIE_WIDTH                      1
+#define SDHC_FEVT_CIE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CIE_SHIFT))&SDHC_FEVT_CIE_MASK)
+#define SDHC_FEVT_DTOE_MASK                      0x100000u
+#define SDHC_FEVT_DTOE_SHIFT                     20
+#define SDHC_FEVT_DTOE_WIDTH                     1
+#define SDHC_FEVT_DTOE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DTOE_SHIFT))&SDHC_FEVT_DTOE_MASK)
+#define SDHC_FEVT_DCE_MASK                       0x200000u
+#define SDHC_FEVT_DCE_SHIFT                      21
+#define SDHC_FEVT_DCE_WIDTH                      1
+#define SDHC_FEVT_DCE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DCE_SHIFT))&SDHC_FEVT_DCE_MASK)
+#define SDHC_FEVT_DEBE_MASK                      0x400000u
+#define SDHC_FEVT_DEBE_SHIFT                     22
+#define SDHC_FEVT_DEBE_WIDTH                     1
+#define SDHC_FEVT_DEBE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DEBE_SHIFT))&SDHC_FEVT_DEBE_MASK)
+#define SDHC_FEVT_AC12E_MASK                     0x1000000u
+#define SDHC_FEVT_AC12E_SHIFT                    24
+#define SDHC_FEVT_AC12E_WIDTH                    1
+#define SDHC_FEVT_AC12E(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12E_SHIFT))&SDHC_FEVT_AC12E_MASK)
+#define SDHC_FEVT_DMAE_MASK                      0x10000000u
+#define SDHC_FEVT_DMAE_SHIFT                     28
+#define SDHC_FEVT_DMAE_WIDTH                     1
+#define SDHC_FEVT_DMAE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DMAE_SHIFT))&SDHC_FEVT_DMAE_MASK)
+#define SDHC_FEVT_CINT_MASK                      0x80000000u
+#define SDHC_FEVT_CINT_SHIFT                     31
+#define SDHC_FEVT_CINT_WIDTH                     1
+#define SDHC_FEVT_CINT(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CINT_SHIFT))&SDHC_FEVT_CINT_MASK)
+/* ADMAES Bit Fields */
+#define SDHC_ADMAES_ADMAES_MASK                  0x3u
+#define SDHC_ADMAES_ADMAES_SHIFT                 0
+#define SDHC_ADMAES_ADMAES_WIDTH                 2
+#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK                 0x4u
+#define SDHC_ADMAES_ADMALME_SHIFT                2
+#define SDHC_ADMAES_ADMALME_WIDTH                1
+#define SDHC_ADMAES_ADMALME(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMALME_SHIFT))&SDHC_ADMAES_ADMALME_MASK)
+#define SDHC_ADMAES_ADMADCE_MASK                 0x8u
+#define SDHC_ADMAES_ADMADCE_SHIFT                3
+#define SDHC_ADMAES_ADMADCE_WIDTH                1
+#define SDHC_ADMAES_ADMADCE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMADCE_SHIFT))&SDHC_ADMAES_ADMADCE_MASK)
+/* ADSADDR Bit Fields */
+#define SDHC_ADSADDR_ADSADDR_MASK                0xFFFFFFFCu
+#define SDHC_ADSADDR_ADSADDR_SHIFT               2
+#define SDHC_ADSADDR_ADSADDR_WIDTH               30
+#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
+/* VENDOR Bit Fields */
+#define SDHC_VENDOR_EXTDMAEN_MASK                0x1u
+#define SDHC_VENDOR_EXTDMAEN_SHIFT               0
+#define SDHC_VENDOR_EXTDMAEN_WIDTH               1
+#define SDHC_VENDOR_EXTDMAEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXTDMAEN_SHIFT))&SDHC_VENDOR_EXTDMAEN_MASK)
+#define SDHC_VENDOR_EXBLKNU_MASK                 0x2u
+#define SDHC_VENDOR_EXBLKNU_SHIFT                1
+#define SDHC_VENDOR_EXBLKNU_WIDTH                1
+#define SDHC_VENDOR_EXBLKNU(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXBLKNU_SHIFT))&SDHC_VENDOR_EXBLKNU_MASK)
+#define SDHC_VENDOR_INTSTVAL_MASK                0xFF0000u
+#define SDHC_VENDOR_INTSTVAL_SHIFT               16
+#define SDHC_VENDOR_INTSTVAL_WIDTH               8
+#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
+/* MMCBOOT Bit Fields */
+#define SDHC_MMCBOOT_DTOCVACK_MASK               0xFu
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT              0
+#define SDHC_MMCBOOT_DTOCVACK_WIDTH              4
+#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK                0x10u
+#define SDHC_MMCBOOT_BOOTACK_SHIFT               4
+#define SDHC_MMCBOOT_BOOTACK_WIDTH               1
+#define SDHC_MMCBOOT_BOOTACK(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTACK_SHIFT))&SDHC_MMCBOOT_BOOTACK_MASK)
+#define SDHC_MMCBOOT_BOOTMODE_MASK               0x20u
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT              5
+#define SDHC_MMCBOOT_BOOTMODE_WIDTH              1
+#define SDHC_MMCBOOT_BOOTMODE(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTMODE_SHIFT))&SDHC_MMCBOOT_BOOTMODE_MASK)
+#define SDHC_MMCBOOT_BOOTEN_MASK                 0x40u
+#define SDHC_MMCBOOT_BOOTEN_SHIFT                6
+#define SDHC_MMCBOOT_BOOTEN_WIDTH                1
+#define SDHC_MMCBOOT_BOOTEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTEN_SHIFT))&SDHC_MMCBOOT_BOOTEN_MASK)
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK             0x80u
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            7
+#define SDHC_MMCBOOT_AUTOSABGEN_WIDTH            1
+#define SDHC_MMCBOOT_AUTOSABGEN(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_AUTOSABGEN_SHIFT))&SDHC_MMCBOOT_AUTOSABGEN_MASK)
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             0xFFFF0000u
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            16
+#define SDHC_MMCBOOT_BOOTBLKCNT_WIDTH            16
+#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+/* HOSTVER Bit Fields */
+#define SDHC_HOSTVER_SVN_MASK                    0xFFu
+#define SDHC_HOSTVER_SVN_SHIFT                   0
+#define SDHC_HOSTVER_SVN_WIDTH                   8
+#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK                    0xFF00u
+#define SDHC_HOSTVER_VVN_SHIFT                   8
+#define SDHC_HOSTVER_VVN_WIDTH                   8
+#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/** Peripheral SDHC base address */
+#define SDHC_BASE                                (0x400B1000u)
+/** Peripheral SDHC base pointer */
+#define SDHC                                     ((SDHC_Type *)SDHC_BASE)
+#define SDHC_BASE_PTR                            (SDHC)
+/** Array initializer of SDHC peripheral base addresses */
+#define SDHC_BASE_ADDRS                          { SDHC_BASE }
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASE_PTRS                           { SDHC }
+/** Interrupt vectors for the SDHC peripheral type */
+#define SDHC_IRQS                                { SDHC_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register instance definitions */
+/* SDHC */
+#define SDHC_DSADDR                              SDHC_DSADDR_REG(SDHC)
+#define SDHC_BLKATTR                             SDHC_BLKATTR_REG(SDHC)
+#define SDHC_CMDARG                              SDHC_CMDARG_REG(SDHC)
+#define SDHC_XFERTYP                             SDHC_XFERTYP_REG(SDHC)
+#define SDHC_CMDRSP0                             SDHC_CMDRSP_REG(SDHC,0)
+#define SDHC_CMDRSP1                             SDHC_CMDRSP_REG(SDHC,1)
+#define SDHC_CMDRSP2                             SDHC_CMDRSP_REG(SDHC,2)
+#define SDHC_CMDRSP3                             SDHC_CMDRSP_REG(SDHC,3)
+#define SDHC_DATPORT                             SDHC_DATPORT_REG(SDHC)
+#define SDHC_PRSSTAT                             SDHC_PRSSTAT_REG(SDHC)
+#define SDHC_PROCTL                              SDHC_PROCTL_REG(SDHC)
+#define SDHC_SYSCTL                              SDHC_SYSCTL_REG(SDHC)
+#define SDHC_IRQSTAT                             SDHC_IRQSTAT_REG(SDHC)
+#define SDHC_IRQSTATEN                           SDHC_IRQSTATEN_REG(SDHC)
+#define SDHC_IRQSIGEN                            SDHC_IRQSIGEN_REG(SDHC)
+#define SDHC_AC12ERR                             SDHC_AC12ERR_REG(SDHC)
+#define SDHC_HTCAPBLT                            SDHC_HTCAPBLT_REG(SDHC)
+#define SDHC_WML                                 SDHC_WML_REG(SDHC)
+#define SDHC_FEVT                                SDHC_FEVT_REG(SDHC)
+#define SDHC_ADMAES                              SDHC_ADMAES_REG(SDHC)
+#define SDHC_ADSADDR                             SDHC_ADSADDR_REG(SDHC)
+#define SDHC_VENDOR                              SDHC_VENDOR_REG(SDHC)
+#define SDHC_MMCBOOT                             SDHC_MMCBOOT_REG(SDHC)
+#define SDHC_HOSTVER                             SDHC_HOSTVER_REG(SDHC)
+
+/* SDHC - Register array accessors */
+#define SDHC_CMDRSP(index)                       SDHC_CMDRSP_REG(SDHC,index)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
+       uint8_t RESERVED_0[4092];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+  __IO uint32_t SCGC1;                             /**< System Clock Gating Control Register 1, offset: 0x1028 */
+  __IO uint32_t SCGC2;                             /**< System Clock Gating Control Register 2, offset: 0x102C */
+  __IO uint32_t SCGC3;                             /**< System Clock Gating Control Register 3, offset: 0x1030 */
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+  __IO uint32_t CLKDIV2;                           /**< System Clock Divider Register 2, offset: 0x1048 */
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+  __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base)                      ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base)                   ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base)                      ((base)->SOPT2)
+#define SIM_SOPT4_REG(base)                      ((base)->SOPT4)
+#define SIM_SOPT5_REG(base)                      ((base)->SOPT5)
+#define SIM_SOPT7_REG(base)                      ((base)->SOPT7)
+#define SIM_SDID_REG(base)                       ((base)->SDID)
+#define SIM_SCGC1_REG(base)                      ((base)->SCGC1)
+#define SIM_SCGC2_REG(base)                      ((base)->SCGC2)
+#define SIM_SCGC3_REG(base)                      ((base)->SCGC3)
+#define SIM_SCGC4_REG(base)                      ((base)->SCGC4)
+#define SIM_SCGC5_REG(base)                      ((base)->SCGC5)
+#define SIM_SCGC6_REG(base)                      ((base)->SCGC6)
+#define SIM_SCGC7_REG(base)                      ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base)                    ((base)->CLKDIV1)
+#define SIM_CLKDIV2_REG(base)                    ((base)->CLKDIV2)
+#define SIM_FCFG1_REG(base)                      ((base)->FCFG1)
+#define SIM_FCFG2_REG(base)                      ((base)->FCFG2)
+#define SIM_UIDH_REG(base)                       ((base)->UIDH)
+#define SIM_UIDMH_REG(base)                      ((base)->UIDMH)
+#define SIM_UIDML_REG(base)                      ((base)->UIDML)
+#define SIM_UIDL_REG(base)                       ((base)->UIDL)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK                   0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT                  12
+#define SIM_SOPT1_RAMSIZE_WIDTH                  4
+#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT                18
+#define SIM_SOPT1_OSC32KSEL_WIDTH                2
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK                  0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT                 29
+#define SIM_SOPT1_USBVSTBY_WIDTH                 1
+#define SIM_SOPT1_USBVSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBVSTBY_SHIFT))&SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK                  0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT                 30
+#define SIM_SOPT1_USBSSTBY_WIDTH                 1
+#define SIM_SOPT1_USBSSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBSSTBY_SHIFT))&SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK                  0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT                 31
+#define SIM_SOPT1_USBREGEN_WIDTH                 1
+#define SIM_SOPT1_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBREGEN_SHIFT))&SIM_SOPT1_USBREGEN_MASK)
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK                   0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT                  24
+#define SIM_SOPT1CFG_URWE_WIDTH                  1
+#define SIM_SOPT1CFG_URWE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_URWE_SHIFT))&SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK                  0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT                 25
+#define SIM_SOPT1CFG_UVSWE_WIDTH                 1
+#define SIM_SOPT1CFG_UVSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_UVSWE_SHIFT))&SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK                  0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT                 26
+#define SIM_SOPT1CFG_USSWE_WIDTH                 1
+#define SIM_SOPT1CFG_USSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_USSWE_SHIFT))&SIM_SOPT1CFG_USSWE_MASK)
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
+#define SIM_SOPT2_RTCCLKOUTSEL_WIDTH             1
+#define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                5
+#define SIM_SOPT2_CLKOUTSEL_WIDTH                3
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK                      0x300u
+#define SIM_SOPT2_FBSL_SHIFT                     8
+#define SIM_SOPT2_FBSL_WIDTH                     2
+#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK                   0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT                  11
+#define SIM_SOPT2_PTD7PAD_WIDTH                  1
+#define SIM_SOPT2_PTD7PAD(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PTD7PAD_SHIFT))&SIM_SOPT2_PTD7PAD_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK               0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT              12
+#define SIM_SOPT2_TRACECLKSEL_WIDTH              1
+#define SIM_SOPT2_TRACECLKSEL(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TRACECLKSEL_SHIFT))&SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK                 0x30000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                16
+#define SIM_SOPT2_PLLFLLSEL_WIDTH                2
+#define SIM_SOPT2_PLLFLLSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK                    0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT                   18
+#define SIM_SOPT2_USBSRC_WIDTH                   1
+#define SIM_SOPT2_USBSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_RMIISRC_MASK                   0x80000u
+#define SIM_SOPT2_RMIISRC_SHIFT                  19
+#define SIM_SOPT2_RMIISRC_WIDTH                  1
+#define SIM_SOPT2_RMIISRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RMIISRC_SHIFT))&SIM_SOPT2_RMIISRC_MASK)
+#define SIM_SOPT2_TIMESRC_MASK                   0x300000u
+#define SIM_SOPT2_TIMESRC_SHIFT                  20
+#define SIM_SOPT2_TIMESRC_WIDTH                  2
+#define SIM_SOPT2_TIMESRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK                   0x30000000u
+#define SIM_SOPT2_SDHCSRC_SHIFT                  28
+#define SIM_SOPT2_SDHCSRC_WIDTH                  2
+#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK                  0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT                 0
+#define SIM_SOPT4_FTM0FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT0_SHIFT))&SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK                  0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT                 1
+#define SIM_SOPT4_FTM0FLT1_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT1_SHIFT))&SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM0FLT2_MASK                  0x4u
+#define SIM_SOPT4_FTM0FLT2_SHIFT                 2
+#define SIM_SOPT4_FTM0FLT2_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT2(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT2_SHIFT))&SIM_SOPT4_FTM0FLT2_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK                  0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT                 4
+#define SIM_SOPT4_FTM1FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM1FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1FLT0_SHIFT))&SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_MASK                  0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT                 8
+#define SIM_SOPT4_FTM2FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM2FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2FLT0_SHIFT))&SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM3FLT0_MASK                  0x1000u
+#define SIM_SOPT4_FTM3FLT0_SHIFT                 12
+#define SIM_SOPT4_FTM3FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM3FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3FLT0_SHIFT))&SIM_SOPT4_FTM3FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK                0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT               18
+#define SIM_SOPT4_FTM1CH0SRC_WIDTH               2
+#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK                0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT               20
+#define SIM_SOPT4_FTM2CH0SRC_WIDTH               2
+#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK                0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT               24
+#define SIM_SOPT4_FTM0CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0CLKSEL_SHIFT))&SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK                0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT               25
+#define SIM_SOPT4_FTM1CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CLKSEL_SHIFT))&SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_MASK                0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT               26
+#define SIM_SOPT4_FTM2CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CLKSEL_SHIFT))&SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM3CLKSEL_MASK                0x8000000u
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT               27
+#define SIM_SOPT4_FTM3CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM3CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3CLKSEL_SHIFT))&SIM_SOPT4_FTM3CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK               0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT              28
+#define SIM_SOPT4_FTM0TRG0SRC_WIDTH              1
+#define SIM_SOPT4_FTM0TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG0SRC_SHIFT))&SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_MASK               0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT              29
+#define SIM_SOPT4_FTM0TRG1SRC_WIDTH              1
+#define SIM_SOPT4_FTM0TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG1SRC_SHIFT))&SIM_SOPT4_FTM0TRG1SRC_MASK)
+#define SIM_SOPT4_FTM3TRG0SRC_MASK               0x40000000u
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT              30
+#define SIM_SOPT4_FTM3TRG0SRC_WIDTH              1
+#define SIM_SOPT4_FTM3TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG0SRC_SHIFT))&SIM_SOPT4_FTM3TRG0SRC_MASK)
+#define SIM_SOPT4_FTM3TRG1SRC_MASK               0x80000000u
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT              31
+#define SIM_SOPT4_FTM3TRG1SRC_WIDTH              1
+#define SIM_SOPT4_FTM3TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG1SRC_SHIFT))&SIM_SOPT4_FTM3TRG1SRC_MASK)
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK                0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT               0
+#define SIM_SOPT5_UART0TXSRC_WIDTH               2
+#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK                0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT               2
+#define SIM_SOPT5_UART0RXSRC_WIDTH               2
+#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK                0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT               4
+#define SIM_SOPT5_UART1TXSRC_WIDTH               2
+#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK                0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT               6
+#define SIM_SOPT5_UART1RXSRC_WIDTH               2
+#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
+#define SIM_SOPT7_ADC0TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
+#define SIM_SOPT7_ADC0PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
+#define SIM_SOPT7_ADC0ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_MASK                0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT               8
+#define SIM_SOPT7_ADC1TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK             0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            12
+#define SIM_SOPT7_ADC1PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC1PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1PRETRGSEL_SHIFT))&SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK              0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             15
+#define SIM_SOPT7_ADC1ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC1ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1ALTTRGEN_SHIFT))&SIM_SOPT7_ADC1ALTTRGEN_MASK)
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK                      0xFu
+#define SIM_SDID_PINID_SHIFT                     0
+#define SIM_SDID_PINID_WIDTH                     4
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK                      0x70u
+#define SIM_SDID_FAMID_SHIFT                     4
+#define SIM_SDID_FAMID_WIDTH                     3
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK                      0xF80u
+#define SIM_SDID_DIEID_SHIFT                     7
+#define SIM_SDID_DIEID_WIDTH                     5
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      0xF000u
+#define SIM_SDID_REVID_SHIFT                     12
+#define SIM_SDID_REVID_WIDTH                     4
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK                   0xF00000u
+#define SIM_SDID_SERIESID_SHIFT                  20
+#define SIM_SDID_SERIESID_WIDTH                  4
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT                  24
+#define SIM_SDID_SUBFAMID_WIDTH                  4
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK                   0xF0000000u
+#define SIM_SDID_FAMILYID_SHIFT                  28
+#define SIM_SDID_FAMILYID_WIDTH                  4
+#define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
+/* SCGC1 Bit Fields */
+#define SIM_SCGC1_I2C2_MASK                      0x40u
+#define SIM_SCGC1_I2C2_SHIFT                     6
+#define SIM_SCGC1_I2C2_WIDTH                     1
+#define SIM_SCGC1_I2C2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_I2C2_SHIFT))&SIM_SCGC1_I2C2_MASK)
+#define SIM_SCGC1_UART4_MASK                     0x400u
+#define SIM_SCGC1_UART4_SHIFT                    10
+#define SIM_SCGC1_UART4_WIDTH                    1
+#define SIM_SCGC1_UART4(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART4_SHIFT))&SIM_SCGC1_UART4_MASK)
+#define SIM_SCGC1_UART5_MASK                     0x800u
+#define SIM_SCGC1_UART5_SHIFT                    11
+#define SIM_SCGC1_UART5_WIDTH                    1
+#define SIM_SCGC1_UART5(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART5_SHIFT))&SIM_SCGC1_UART5_MASK)
+/* SCGC2 Bit Fields */
+#define SIM_SCGC2_ENET_MASK                      0x1u
+#define SIM_SCGC2_ENET_SHIFT                     0
+#define SIM_SCGC2_ENET_WIDTH                     1
+#define SIM_SCGC2_ENET(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_ENET_SHIFT))&SIM_SCGC2_ENET_MASK)
+#define SIM_SCGC2_DAC0_MASK                      0x1000u
+#define SIM_SCGC2_DAC0_SHIFT                     12
+#define SIM_SCGC2_DAC0_WIDTH                     1
+#define SIM_SCGC2_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC0_SHIFT))&SIM_SCGC2_DAC0_MASK)
+#define SIM_SCGC2_DAC1_MASK                      0x2000u
+#define SIM_SCGC2_DAC1_SHIFT                     13
+#define SIM_SCGC2_DAC1_WIDTH                     1
+#define SIM_SCGC2_DAC1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC1_SHIFT))&SIM_SCGC2_DAC1_MASK)
+/* SCGC3 Bit Fields */
+#define SIM_SCGC3_RNGA_MASK                      0x1u
+#define SIM_SCGC3_RNGA_SHIFT                     0
+#define SIM_SCGC3_RNGA_WIDTH                     1
+#define SIM_SCGC3_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_RNGA_SHIFT))&SIM_SCGC3_RNGA_MASK)
+#define SIM_SCGC3_SPI2_MASK                      0x1000u
+#define SIM_SCGC3_SPI2_SHIFT                     12
+#define SIM_SCGC3_SPI2_WIDTH                     1
+#define SIM_SCGC3_SPI2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SPI2_SHIFT))&SIM_SCGC3_SPI2_MASK)
+#define SIM_SCGC3_SDHC_MASK                      0x20000u
+#define SIM_SCGC3_SDHC_SHIFT                     17
+#define SIM_SCGC3_SDHC_WIDTH                     1
+#define SIM_SCGC3_SDHC(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SDHC_SHIFT))&SIM_SCGC3_SDHC_MASK)
+#define SIM_SCGC3_FTM2_MASK                      0x1000000u
+#define SIM_SCGC3_FTM2_SHIFT                     24
+#define SIM_SCGC3_FTM2_WIDTH                     1
+#define SIM_SCGC3_FTM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM2_SHIFT))&SIM_SCGC3_FTM2_MASK)
+#define SIM_SCGC3_FTM3_MASK                      0x2000000u
+#define SIM_SCGC3_FTM3_SHIFT                     25
+#define SIM_SCGC3_FTM3_WIDTH                     1
+#define SIM_SCGC3_FTM3(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM3_SHIFT))&SIM_SCGC3_FTM3_MASK)
+#define SIM_SCGC3_ADC1_MASK                      0x8000000u
+#define SIM_SCGC3_ADC1_SHIFT                     27
+#define SIM_SCGC3_ADC1_WIDTH                     1
+#define SIM_SCGC3_ADC1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_ADC1_SHIFT))&SIM_SCGC3_ADC1_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK                       0x2u
+#define SIM_SCGC4_EWM_SHIFT                      1
+#define SIM_SCGC4_EWM_WIDTH                      1
+#define SIM_SCGC4_EWM(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_EWM_SHIFT))&SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_CMT_MASK                       0x4u
+#define SIM_SCGC4_CMT_SHIFT                      2
+#define SIM_SCGC4_CMT_WIDTH                      1
+#define SIM_SCGC4_CMT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMT_SHIFT))&SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_I2C0_MASK                      0x40u
+#define SIM_SCGC4_I2C0_SHIFT                     6
+#define SIM_SCGC4_I2C0_WIDTH                     1
+#define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C0_SHIFT))&SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK                      0x80u
+#define SIM_SCGC4_I2C1_SHIFT                     7
+#define SIM_SCGC4_I2C1_WIDTH                     1
+#define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C1_SHIFT))&SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK                     0x400u
+#define SIM_SCGC4_UART0_SHIFT                    10
+#define SIM_SCGC4_UART0_WIDTH                    1
+#define SIM_SCGC4_UART0(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART0_SHIFT))&SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK                     0x800u
+#define SIM_SCGC4_UART1_SHIFT                    11
+#define SIM_SCGC4_UART1_WIDTH                    1
+#define SIM_SCGC4_UART1(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART1_SHIFT))&SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK                     0x1000u
+#define SIM_SCGC4_UART2_SHIFT                    12
+#define SIM_SCGC4_UART2_WIDTH                    1
+#define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_UART3_MASK                     0x2000u
+#define SIM_SCGC4_UART3_SHIFT                    13
+#define SIM_SCGC4_UART3_WIDTH                    1
+#define SIM_SCGC4_UART3(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART3_SHIFT))&SIM_SCGC4_UART3_MASK)
+#define SIM_SCGC4_USBOTG_MASK                    0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT                   18
+#define SIM_SCGC4_USBOTG_WIDTH                   1
+#define SIM_SCGC4_USBOTG(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBOTG_SHIFT))&SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK                       0x80000u
+#define SIM_SCGC4_CMP_SHIFT                      19
+#define SIM_SCGC4_CMP_WIDTH                      1
+#define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK                      0x100000u
+#define SIM_SCGC4_VREF_SHIFT                     20
+#define SIM_SCGC4_VREF_WIDTH                     1
+#define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_VREF_SHIFT))&SIM_SCGC4_VREF_MASK)
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK                     0x1u
+#define SIM_SCGC5_LPTMR_SHIFT                    0
+#define SIM_SCGC5_LPTMR_WIDTH                    1
+#define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_PORTA_MASK                     0x200u
+#define SIM_SCGC5_PORTA_SHIFT                    9
+#define SIM_SCGC5_PORTA_WIDTH                    1
+#define SIM_SCGC5_PORTA(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK                     0x400u
+#define SIM_SCGC5_PORTB_SHIFT                    10
+#define SIM_SCGC5_PORTB_WIDTH                    1
+#define SIM_SCGC5_PORTB(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK                     0x800u
+#define SIM_SCGC5_PORTC_SHIFT                    11
+#define SIM_SCGC5_PORTC_WIDTH                    1
+#define SIM_SCGC5_PORTC(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK                     0x1000u
+#define SIM_SCGC5_PORTD_SHIFT                    12
+#define SIM_SCGC5_PORTD_WIDTH                    1
+#define SIM_SCGC5_PORTD(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK                     0x2000u
+#define SIM_SCGC5_PORTE_SHIFT                    13
+#define SIM_SCGC5_PORTE_WIDTH                    1
+#define SIM_SCGC5_PORTE(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK                       0x1u
+#define SIM_SCGC6_FTF_SHIFT                      0
+#define SIM_SCGC6_FTF_WIDTH                      1
+#define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK                    0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT                   1
+#define SIM_SCGC6_DMAMUX_WIDTH                   1
+#define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_FLEXCAN0_MASK                  0x10u
+#define SIM_SCGC6_FLEXCAN0_SHIFT                 4
+#define SIM_SCGC6_FLEXCAN0_WIDTH                 1
+#define SIM_SCGC6_FLEXCAN0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FLEXCAN0_SHIFT))&SIM_SCGC6_FLEXCAN0_MASK)
+#define SIM_SCGC6_RNGA_MASK                      0x200u
+#define SIM_SCGC6_RNGA_SHIFT                     9
+#define SIM_SCGC6_RNGA_WIDTH                     1
+#define SIM_SCGC6_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RNGA_SHIFT))&SIM_SCGC6_RNGA_MASK)
+#define SIM_SCGC6_SPI0_MASK                      0x1000u
+#define SIM_SCGC6_SPI0_SHIFT                     12
+#define SIM_SCGC6_SPI0_WIDTH                     1
+#define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI0_SHIFT))&SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK                      0x2000u
+#define SIM_SCGC6_SPI1_SHIFT                     13
+#define SIM_SCGC6_SPI1_WIDTH                     1
+#define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI1_SHIFT))&SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_I2S_MASK                       0x8000u
+#define SIM_SCGC6_I2S_SHIFT                      15
+#define SIM_SCGC6_I2S_WIDTH                      1
+#define SIM_SCGC6_I2S(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S_SHIFT))&SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK                       0x40000u
+#define SIM_SCGC6_CRC_SHIFT                      18
+#define SIM_SCGC6_CRC_WIDTH                      1
+#define SIM_SCGC6_CRC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_CRC_SHIFT))&SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_USBDCD_MASK                    0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT                   21
+#define SIM_SCGC6_USBDCD_WIDTH                   1
+#define SIM_SCGC6_USBDCD(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_USBDCD_SHIFT))&SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_PDB_MASK                       0x400000u
+#define SIM_SCGC6_PDB_SHIFT                      22
+#define SIM_SCGC6_PDB_WIDTH                      1
+#define SIM_SCGC6_PDB(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PDB_SHIFT))&SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK                       0x800000u
+#define SIM_SCGC6_PIT_SHIFT                      23
+#define SIM_SCGC6_PIT_WIDTH                      1
+#define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK                      0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT                     24
+#define SIM_SCGC6_FTM0_WIDTH                     1
+#define SIM_SCGC6_FTM0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM0_SHIFT))&SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK                      0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT                     25
+#define SIM_SCGC6_FTM1_WIDTH                     1
+#define SIM_SCGC6_FTM1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM1_SHIFT))&SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM2_MASK                      0x4000000u
+#define SIM_SCGC6_FTM2_SHIFT                     26
+#define SIM_SCGC6_FTM2_WIDTH                     1
+#define SIM_SCGC6_FTM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM2_SHIFT))&SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_ADC0_MASK                      0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT                     27
+#define SIM_SCGC6_ADC0_WIDTH                     1
+#define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK                       0x20000000u
+#define SIM_SCGC6_RTC_SHIFT                      29
+#define SIM_SCGC6_RTC_WIDTH                      1
+#define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK                      0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT                     31
+#define SIM_SCGC6_DAC0_WIDTH                     1
+#define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_FLEXBUS_MASK                   0x1u
+#define SIM_SCGC7_FLEXBUS_SHIFT                  0
+#define SIM_SCGC7_FLEXBUS_WIDTH                  1
+#define SIM_SCGC7_FLEXBUS(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_FLEXBUS_SHIFT))&SIM_SCGC7_FLEXBUS_MASK)
+#define SIM_SCGC7_DMA_MASK                       0x2u
+#define SIM_SCGC7_DMA_SHIFT                      1
+#define SIM_SCGC7_DMA_WIDTH                      1
+#define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_MPU_MASK                       0x4u
+#define SIM_SCGC7_MPU_SHIFT                      2
+#define SIM_SCGC7_MPU_WIDTH                      1
+#define SIM_SCGC7_MPU(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_MPU_SHIFT))&SIM_SCGC7_MPU_MASK)
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
+#define SIM_CLKDIV1_OUTDIV4_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK                 0xF00000u
+#define SIM_CLKDIV1_OUTDIV3_SHIFT                20
+#define SIM_CLKDIV1_OUTDIV3_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV3(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK                 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT                24
+#define SIM_CLKDIV1_OUTDIV2_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
+#define SIM_CLKDIV1_OUTDIV1_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK                 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT                0
+#define SIM_CLKDIV2_USBFRAC_WIDTH                1
+#define SIM_CLKDIV2_USBFRAC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBFRAC_SHIFT))&SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK                  0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT                 1
+#define SIM_CLKDIV2_USBDIV_WIDTH                 3
+#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK                  0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT                 0
+#define SIM_FCFG1_FLASHDIS_WIDTH                 1
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT                1
+#define SIM_FCFG1_FLASHDOZE_WIDTH                1
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_DEPART_MASK                    0xF00u
+#define SIM_FCFG1_DEPART_SHIFT                   8
+#define SIM_FCFG1_DEPART_WIDTH                   4
+#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK                    0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT                   16
+#define SIM_FCFG1_EESIZE_WIDTH                   4
+#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT                   24
+#define SIM_FCFG1_PFSIZE_WIDTH                   4
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK                   0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT                  28
+#define SIM_FCFG1_NVMSIZE_WIDTH                  4
+#define SIM_FCFG1_NVMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK                  0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT                 16
+#define SIM_FCFG2_MAXADDR1_WIDTH                 7
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK                     0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT                    23
+#define SIM_FCFG2_PFLSH_WIDTH                    1
+#define SIM_FCFG2_PFLSH(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_PFLSH_SHIFT))&SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK                  0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT                 24
+#define SIM_FCFG2_MAXADDR0_WIDTH                 7
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT                       0
+#define SIM_UIDH_UID_WIDTH                       32
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT                      0
+#define SIM_UIDMH_UID_WIDTH                      32
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT                      0
+#define SIM_UIDML_UID_WIDTH                      32
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT                       0
+#define SIM_UIDL_UID_WIDTH                       32
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR                             (SIM)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1                                SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG                             SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2                                SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4                                SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5                                SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7                                SIM_SOPT7_REG(SIM)
+#define SIM_SDID                                 SIM_SDID_REG(SIM)
+#define SIM_SCGC1                                SIM_SCGC1_REG(SIM)
+#define SIM_SCGC2                                SIM_SCGC2_REG(SIM)
+#define SIM_SCGC3                                SIM_SCGC3_REG(SIM)
+#define SIM_SCGC4                                SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5                                SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6                                SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7                                SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1                              SIM_CLKDIV1_REG(SIM)
+#define SIM_CLKDIV2                              SIM_CLKDIV2_REG(SIM)
+#define SIM_FCFG1                                SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2                                SIM_FCFG2_REG(SIM)
+#define SIM_UIDH                                 SIM_UIDH_REG(SIM)
+#define SIM_UIDMH                                SIM_UIDMH_REG(SIM)
+#define SIM_UIDML                                SIM_UIDML_REG(SIM)
+#define SIM_UIDL                                 SIM_UIDL_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t VLLSCTRL;                           /**< VLLS Control register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base)                     ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base)                     ((base)->PMCTRL)
+#define SMC_VLLSCTRL_REG(base)                   ((base)->VLLSCTRL)
+#define SMC_PMSTAT_REG(base)                     ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK                    0x2u
+#define SMC_PMPROT_AVLLS_SHIFT                   1
+#define SMC_PMPROT_AVLLS_WIDTH                   1
+#define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK                     0x8u
+#define SMC_PMPROT_ALLS_SHIFT                    3
+#define SMC_PMPROT_ALLS_WIDTH                    1
+#define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK                     0x20u
+#define SMC_PMPROT_AVLP_SHIFT                    5
+#define SMC_PMPROT_AVLP_WIDTH                    1
+#define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK                    0x7u
+#define SMC_PMCTRL_STOPM_SHIFT                   0
+#define SMC_PMCTRL_STOPM_WIDTH                   3
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK                    0x8u
+#define SMC_PMCTRL_STOPA_SHIFT                   3
+#define SMC_PMCTRL_STOPA_WIDTH                   1
+#define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK                     0x60u
+#define SMC_PMCTRL_RUNM_SHIFT                    5
+#define SMC_PMCTRL_RUNM_WIDTH                    2
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK                    0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT                   7
+#define SMC_PMCTRL_LPWUI_WIDTH                   1
+#define SMC_PMCTRL_LPWUI(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_LPWUI_SHIFT))&SMC_PMCTRL_LPWUI_MASK)
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK                  0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT                 0
+#define SMC_VLLSCTRL_VLLSM_WIDTH                 3
+#define SMC_VLLSCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK                  0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT                 5
+#define SMC_VLLSCTRL_PORPO_WIDTH                 1
+#define SMC_VLLSCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_PORPO_SHIFT))&SMC_VLLSCTRL_PORPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK                   0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT                  0
+#define SMC_PMSTAT_PMSTAT_WIDTH                  7
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR                             (SMC)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC }
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT                               SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL                               SMC_PMCTRL_REG(SMC)
+#define SMC_VLLSCTRL                             SMC_VLLSCTRL_REG(SMC)
+#define SMC_PMSTAT                               SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+    __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+  };
+       uint8_t RESERVED_1[24];
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
+  __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+  union {                                          /* offset: 0x34 */
+    __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+    __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+  };
+  __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
+  __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
+  __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
+  __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
+  __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
+       uint8_t RESERVED_2[48];
+  __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
+  __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
+  __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
+  __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_MCR_REG(base)                        ((base)->MCR)
+#define SPI_TCR_REG(base)                        ((base)->TCR)
+#define SPI_CTAR_REG(base,index2)                ((base)->CTAR[index2])
+#define SPI_CTAR_COUNT                           2
+#define SPI_CTAR_SLAVE_REG(base,index2)          ((base)->CTAR_SLAVE[index2])
+#define SPI_CTAR_SLAVE_COUNT                     1
+#define SPI_SR_REG(base)                         ((base)->SR)
+#define SPI_RSER_REG(base)                       ((base)->RSER)
+#define SPI_PUSHR_REG(base)                      ((base)->PUSHR)
+#define SPI_PUSHR_SLAVE_REG(base)                ((base)->PUSHR_SLAVE)
+#define SPI_POPR_REG(base)                       ((base)->POPR)
+#define SPI_TXFR0_REG(base)                      ((base)->TXFR0)
+#define SPI_TXFR1_REG(base)                      ((base)->TXFR1)
+#define SPI_TXFR2_REG(base)                      ((base)->TXFR2)
+#define SPI_TXFR3_REG(base)                      ((base)->TXFR3)
+#define SPI_RXFR0_REG(base)                      ((base)->RXFR0)
+#define SPI_RXFR1_REG(base)                      ((base)->RXFR1)
+#define SPI_RXFR2_REG(base)                      ((base)->RXFR2)
+#define SPI_RXFR3_REG(base)                      ((base)->RXFR3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK                        0x1u
+#define SPI_MCR_HALT_SHIFT                       0
+#define SPI_MCR_HALT_WIDTH                       1
+#define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_HALT_SHIFT))&SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK                     0x300u
+#define SPI_MCR_SMPL_PT_SHIFT                    8
+#define SPI_MCR_SMPL_PT_WIDTH                    2
+#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK                     0x400u
+#define SPI_MCR_CLR_RXF_SHIFT                    10
+#define SPI_MCR_CLR_RXF_WIDTH                    1
+#define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_RXF_SHIFT))&SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK                     0x800u
+#define SPI_MCR_CLR_TXF_SHIFT                    11
+#define SPI_MCR_CLR_TXF_WIDTH                    1
+#define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_TXF_SHIFT))&SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK                     0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT                    12
+#define SPI_MCR_DIS_RXF_WIDTH                    1
+#define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_RXF_SHIFT))&SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK                     0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT                    13
+#define SPI_MCR_DIS_TXF_WIDTH                    1
+#define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_TXF_SHIFT))&SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK                        0x4000u
+#define SPI_MCR_MDIS_SHIFT                       14
+#define SPI_MCR_MDIS_WIDTH                       1
+#define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MDIS_SHIFT))&SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK                        0x8000u
+#define SPI_MCR_DOZE_SHIFT                       15
+#define SPI_MCR_DOZE_WIDTH                       1
+#define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DOZE_SHIFT))&SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK                       0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT                      16
+#define SPI_MCR_PCSIS_WIDTH                      6
+#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK                        0x1000000u
+#define SPI_MCR_ROOE_SHIFT                       24
+#define SPI_MCR_ROOE_WIDTH                       1
+#define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_ROOE_SHIFT))&SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK                       0x2000000u
+#define SPI_MCR_PCSSE_SHIFT                      25
+#define SPI_MCR_PCSSE_WIDTH                      1
+#define SPI_MCR_PCSSE(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSSE_SHIFT))&SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK                        0x4000000u
+#define SPI_MCR_MTFE_SHIFT                       26
+#define SPI_MCR_MTFE_WIDTH                       1
+#define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MTFE_SHIFT))&SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK                         0x8000000u
+#define SPI_MCR_FRZ_SHIFT                        27
+#define SPI_MCR_FRZ_WIDTH                        1
+#define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_MCR_FRZ_SHIFT))&SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK                       0x30000000u
+#define SPI_MCR_DCONF_SHIFT                      28
+#define SPI_MCR_DCONF_WIDTH                      2
+#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK                   0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT                  30
+#define SPI_MCR_CONT_SCKE_WIDTH                  1
+#define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CONT_SCKE_SHIFT))&SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK                        0x80000000u
+#define SPI_MCR_MSTR_SHIFT                       31
+#define SPI_MCR_MSTR_WIDTH                       1
+#define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MSTR_SHIFT))&SPI_MCR_MSTR_MASK)
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK                    0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT                   16
+#define SPI_TCR_SPI_TCNT_WIDTH                   16
+#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK                         0xFu
+#define SPI_CTAR_BR_SHIFT                        0
+#define SPI_CTAR_BR_WIDTH                        4
+#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK                         0xF0u
+#define SPI_CTAR_DT_SHIFT                        4
+#define SPI_CTAR_DT_WIDTH                        4
+#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK                        0xF00u
+#define SPI_CTAR_ASC_SHIFT                       8
+#define SPI_CTAR_ASC_WIDTH                       4
+#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK                      0xF000u
+#define SPI_CTAR_CSSCK_SHIFT                     12
+#define SPI_CTAR_CSSCK_WIDTH                     4
+#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK                        0x30000u
+#define SPI_CTAR_PBR_SHIFT                       16
+#define SPI_CTAR_PBR_WIDTH                       2
+#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK                        0xC0000u
+#define SPI_CTAR_PDT_SHIFT                       18
+#define SPI_CTAR_PDT_WIDTH                       2
+#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK                       0x300000u
+#define SPI_CTAR_PASC_SHIFT                      20
+#define SPI_CTAR_PASC_WIDTH                      2
+#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK                     0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT                    22
+#define SPI_CTAR_PCSSCK_WIDTH                    2
+#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK                      0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT                     24
+#define SPI_CTAR_LSBFE_WIDTH                     1
+#define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_LSBFE_SHIFT))&SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK                       0x2000000u
+#define SPI_CTAR_CPHA_SHIFT                      25
+#define SPI_CTAR_CPHA_WIDTH                      1
+#define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPHA_SHIFT))&SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK                       0x4000000u
+#define SPI_CTAR_CPOL_SHIFT                      26
+#define SPI_CTAR_CPOL_WIDTH                      1
+#define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPOL_SHIFT))&SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK                       0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT                      27
+#define SPI_CTAR_FMSZ_WIDTH                      4
+#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK                        0x80000000u
+#define SPI_CTAR_DBR_SHIFT                       31
+#define SPI_CTAR_DBR_WIDTH                       1
+#define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DBR_SHIFT))&SPI_CTAR_DBR_MASK)
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK                 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT                25
+#define SPI_CTAR_SLAVE_CPHA_WIDTH                1
+#define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPHA_SHIFT))&SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK                 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT                26
+#define SPI_CTAR_SLAVE_CPOL_WIDTH                1
+#define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPOL_SHIFT))&SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK                 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT                27
+#define SPI_CTAR_SLAVE_FMSZ_WIDTH                5
+#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK                    0xFu
+#define SPI_SR_POPNXTPTR_SHIFT                   0
+#define SPI_SR_POPNXTPTR_WIDTH                   4
+#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK                        0xF0u
+#define SPI_SR_RXCTR_SHIFT                       4
+#define SPI_SR_RXCTR_WIDTH                       4
+#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK                     0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT                    8
+#define SPI_SR_TXNXTPTR_WIDTH                    4
+#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK                        0xF000u
+#define SPI_SR_TXCTR_SHIFT                       12
+#define SPI_SR_TXCTR_WIDTH                       4
+#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK                         0x20000u
+#define SPI_SR_RFDF_SHIFT                        17
+#define SPI_SR_RFDF_WIDTH                        1
+#define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFDF_SHIFT))&SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK                         0x80000u
+#define SPI_SR_RFOF_SHIFT                        19
+#define SPI_SR_RFOF_WIDTH                        1
+#define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFOF_SHIFT))&SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK                         0x2000000u
+#define SPI_SR_TFFF_SHIFT                        25
+#define SPI_SR_TFFF_WIDTH                        1
+#define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK                         0x8000000u
+#define SPI_SR_TFUF_SHIFT                        27
+#define SPI_SR_TFUF_WIDTH                        1
+#define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFUF_SHIFT))&SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK                         0x10000000u
+#define SPI_SR_EOQF_SHIFT                        28
+#define SPI_SR_EOQF_WIDTH                        1
+#define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_EOQF_SHIFT))&SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK                        0x40000000u
+#define SPI_SR_TXRXS_SHIFT                       30
+#define SPI_SR_TXRXS_WIDTH                       1
+#define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXRXS_SHIFT))&SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK                          0x80000000u
+#define SPI_SR_TCF_SHIFT                         31
+#define SPI_SR_TCF_WIDTH                         1
+#define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x))<<SPI_SR_TCF_SHIFT))&SPI_SR_TCF_MASK)
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK                  0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT                 16
+#define SPI_RSER_RFDF_DIRS_WIDTH                 1
+#define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_DIRS_SHIFT))&SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK                    0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT                   17
+#define SPI_RSER_RFDF_RE_WIDTH                   1
+#define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_RE_SHIFT))&SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK                    0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT                   19
+#define SPI_RSER_RFOF_RE_WIDTH                   1
+#define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFOF_RE_SHIFT))&SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK                  0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT                 24
+#define SPI_RSER_TFFF_DIRS_WIDTH                 1
+#define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_DIRS_SHIFT))&SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK                    0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT                   25
+#define SPI_RSER_TFFF_RE_WIDTH                   1
+#define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK                    0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT                   27
+#define SPI_RSER_TFUF_RE_WIDTH                   1
+#define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFUF_RE_SHIFT))&SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK                    0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT                   28
+#define SPI_RSER_EOQF_RE_WIDTH                   1
+#define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_EOQF_RE_SHIFT))&SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK                     0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT                    31
+#define SPI_RSER_TCF_RE_WIDTH                    1
+#define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TCF_RE_SHIFT))&SPI_RSER_TCF_RE_MASK)
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK                    0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT                   0
+#define SPI_PUSHR_TXDATA_WIDTH                   16
+#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK                       0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT                      16
+#define SPI_PUSHR_PCS_WIDTH                      6
+#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK                     0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT                    26
+#define SPI_PUSHR_CTCNT_WIDTH                    1
+#define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTCNT_SHIFT))&SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK                       0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT                      27
+#define SPI_PUSHR_EOQ_WIDTH                      1
+#define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_EOQ_SHIFT))&SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK                      0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT                     28
+#define SPI_PUSHR_CTAS_WIDTH                     3
+#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK                      0x80000000u
+#define SPI_PUSHR_CONT_SHIFT                     31
+#define SPI_PUSHR_CONT_WIDTH                     1
+#define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CONT_SHIFT))&SPI_PUSHR_CONT_MASK)
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK              0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             0
+#define SPI_PUSHR_SLAVE_TXDATA_WIDTH             32
+#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK                     0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT                    0
+#define SPI_POPR_RXDATA_WIDTH                    32
+#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT                   0
+#define SPI_TXFR0_TXDATA_WIDTH                   16
+#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR0_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT                   0
+#define SPI_TXFR1_TXDATA_WIDTH                   16
+#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR1_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT                   0
+#define SPI_TXFR2_TXDATA_WIDTH                   16
+#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR2_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT                   0
+#define SPI_TXFR3_TXDATA_WIDTH                   16
+#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR3_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT                   0
+#define SPI_RXFR0_RXDATA_WIDTH                   32
+#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT                   0
+#define SPI_RXFR1_RXDATA_WIDTH                   32
+#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT                   0
+#define SPI_RXFR2_RXDATA_WIDTH                   32
+#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT                   0
+#define SPI_RXFR3_RXDATA_WIDTH                   32
+#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR                            (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR                            (SPI1)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x400AC000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+#define SPI2_BASE_PTR                            (SPI2)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_MCR                                 SPI_MCR_REG(SPI0)
+#define SPI0_TCR                                 SPI_TCR_REG(SPI0)
+#define SPI0_CTAR0                               SPI_CTAR_REG(SPI0,0)
+#define SPI0_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI0,0)
+#define SPI0_CTAR1                               SPI_CTAR_REG(SPI0,1)
+#define SPI0_SR                                  SPI_SR_REG(SPI0)
+#define SPI0_RSER                                SPI_RSER_REG(SPI0)
+#define SPI0_PUSHR                               SPI_PUSHR_REG(SPI0)
+#define SPI0_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI0)
+#define SPI0_POPR                                SPI_POPR_REG(SPI0)
+#define SPI0_TXFR0                               SPI_TXFR0_REG(SPI0)
+#define SPI0_TXFR1                               SPI_TXFR1_REG(SPI0)
+#define SPI0_TXFR2                               SPI_TXFR2_REG(SPI0)
+#define SPI0_TXFR3                               SPI_TXFR3_REG(SPI0)
+#define SPI0_RXFR0                               SPI_RXFR0_REG(SPI0)
+#define SPI0_RXFR1                               SPI_RXFR1_REG(SPI0)
+#define SPI0_RXFR2                               SPI_RXFR2_REG(SPI0)
+#define SPI0_RXFR3                               SPI_RXFR3_REG(SPI0)
+/* SPI1 */
+#define SPI1_MCR                                 SPI_MCR_REG(SPI1)
+#define SPI1_TCR                                 SPI_TCR_REG(SPI1)
+#define SPI1_CTAR0                               SPI_CTAR_REG(SPI1,0)
+#define SPI1_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI1,0)
+#define SPI1_CTAR1                               SPI_CTAR_REG(SPI1,1)
+#define SPI1_SR                                  SPI_SR_REG(SPI1)
+#define SPI1_RSER                                SPI_RSER_REG(SPI1)
+#define SPI1_PUSHR                               SPI_PUSHR_REG(SPI1)
+#define SPI1_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI1)
+#define SPI1_POPR                                SPI_POPR_REG(SPI1)
+#define SPI1_TXFR0                               SPI_TXFR0_REG(SPI1)
+#define SPI1_TXFR1                               SPI_TXFR1_REG(SPI1)
+#define SPI1_TXFR2                               SPI_TXFR2_REG(SPI1)
+#define SPI1_TXFR3                               SPI_TXFR3_REG(SPI1)
+#define SPI1_RXFR0                               SPI_RXFR0_REG(SPI1)
+#define SPI1_RXFR1                               SPI_RXFR1_REG(SPI1)
+#define SPI1_RXFR2                               SPI_RXFR2_REG(SPI1)
+#define SPI1_RXFR3                               SPI_RXFR3_REG(SPI1)
+/* SPI2 */
+#define SPI2_MCR                                 SPI_MCR_REG(SPI2)
+#define SPI2_TCR                                 SPI_TCR_REG(SPI2)
+#define SPI2_CTAR0                               SPI_CTAR_REG(SPI2,0)
+#define SPI2_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI2,0)
+#define SPI2_CTAR1                               SPI_CTAR_REG(SPI2,1)
+#define SPI2_SR                                  SPI_SR_REG(SPI2)
+#define SPI2_RSER                                SPI_RSER_REG(SPI2)
+#define SPI2_PUSHR                               SPI_PUSHR_REG(SPI2)
+#define SPI2_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI2)
+#define SPI2_POPR                                SPI_POPR_REG(SPI2)
+#define SPI2_TXFR0                               SPI_TXFR0_REG(SPI2)
+#define SPI2_TXFR1                               SPI_TXFR1_REG(SPI2)
+#define SPI2_TXFR2                               SPI_TXFR2_REG(SPI2)
+#define SPI2_TXFR3                               SPI_TXFR3_REG(SPI2)
+#define SPI2_RXFR0                               SPI_RXFR0_REG(SPI2)
+#define SPI2_RXFR1                               SPI_RXFR1_REG(SPI2)
+#define SPI2_RXFR2                               SPI_RXFR2_REG(SPI2)
+#define SPI2_RXFR3                               SPI_RXFR3_REG(SPI2)
+
+/* SPI - Register array accessors */
+#define SPI0_CTAR(index2)                        SPI_CTAR_REG(SPI0,index2)
+#define SPI1_CTAR(index2)                        SPI_CTAR_REG(SPI1,index2)
+#define SPI2_CTAR(index2)                        SPI_CTAR_REG(SPI2,index2)
+#define SPI0_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI0,index2)
+#define SPI1_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI1,index2)
+#define SPI2_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI2,index2)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
+  __I  uint8_t ED;                                 /**< UART Extended Data Register, offset: 0xC */
+  __IO uint8_t MODEM;                              /**< UART Modem Register, offset: 0xD */
+  __IO uint8_t IR;                                 /**< UART Infrared Register, offset: 0xE */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t PFIFO;                              /**< UART FIFO Parameters, offset: 0x10 */
+  __IO uint8_t CFIFO;                              /**< UART FIFO Control Register, offset: 0x11 */
+  __IO uint8_t SFIFO;                              /**< UART FIFO Status Register, offset: 0x12 */
+  __IO uint8_t TWFIFO;                             /**< UART FIFO Transmit Watermark, offset: 0x13 */
+  __I  uint8_t TCFIFO;                             /**< UART FIFO Transmit Count, offset: 0x14 */
+  __IO uint8_t RWFIFO;                             /**< UART FIFO Receive Watermark, offset: 0x15 */
+  __I  uint8_t RCFIFO;                             /**< UART FIFO Receive Count, offset: 0x16 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
+  __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+  __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+  union {                                          /* offset: 0x1B */
+    __IO uint8_t WP7816T0;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+    __IO uint8_t WP7816T1;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+  };
+  __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
+  __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
+  __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
+  __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base)                       ((base)->BDH)
+#define UART_BDL_REG(base)                       ((base)->BDL)
+#define UART_C1_REG(base)                        ((base)->C1)
+#define UART_C2_REG(base)                        ((base)->C2)
+#define UART_S1_REG(base)                        ((base)->S1)
+#define UART_S2_REG(base)                        ((base)->S2)
+#define UART_C3_REG(base)                        ((base)->C3)
+#define UART_D_REG(base)                         ((base)->D)
+#define UART_MA1_REG(base)                       ((base)->MA1)
+#define UART_MA2_REG(base)                       ((base)->MA2)
+#define UART_C4_REG(base)                        ((base)->C4)
+#define UART_C5_REG(base)                        ((base)->C5)
+#define UART_ED_REG(base)                        ((base)->ED)
+#define UART_MODEM_REG(base)                     ((base)->MODEM)
+#define UART_IR_REG(base)                        ((base)->IR)
+#define UART_PFIFO_REG(base)                     ((base)->PFIFO)
+#define UART_CFIFO_REG(base)                     ((base)->CFIFO)
+#define UART_SFIFO_REG(base)                     ((base)->SFIFO)
+#define UART_TWFIFO_REG(base)                    ((base)->TWFIFO)
+#define UART_TCFIFO_REG(base)                    ((base)->TCFIFO)
+#define UART_RWFIFO_REG(base)                    ((base)->RWFIFO)
+#define UART_RCFIFO_REG(base)                    ((base)->RCFIFO)
+#define UART_C7816_REG(base)                     ((base)->C7816)
+#define UART_IE7816_REG(base)                    ((base)->IE7816)
+#define UART_IS7816_REG(base)                    ((base)->IS7816)
+#define UART_WP7816T0_REG(base)                  ((base)->WP7816T0)
+#define UART_WP7816T1_REG(base)                  ((base)->WP7816T1)
+#define UART_WN7816_REG(base)                    ((base)->WN7816)
+#define UART_WF7816_REG(base)                    ((base)->WF7816)
+#define UART_ET7816_REG(base)                    ((base)->ET7816)
+#define UART_TL7816_REG(base)                    ((base)->TL7816)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK                        0x1Fu
+#define UART_BDH_SBR_SHIFT                       0
+#define UART_BDH_SBR_WIDTH                       5
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK                       0x20u
+#define UART_BDH_SBNS_SHIFT                      5
+#define UART_BDH_SBNS_WIDTH                      1
+#define UART_BDH_SBNS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBNS_SHIFT))&UART_BDH_SBNS_MASK)
+#define UART_BDH_RXEDGIE_MASK                    0x40u
+#define UART_BDH_RXEDGIE_SHIFT                   6
+#define UART_BDH_RXEDGIE_WIDTH                   1
+#define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK                     0x80u
+#define UART_BDH_LBKDIE_SHIFT                    7
+#define UART_BDH_LBKDIE_WIDTH                    1
+#define UART_BDH_LBKDIE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_BDH_LBKDIE_SHIFT))&UART_BDH_LBKDIE_MASK)
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK                        0xFFu
+#define UART_BDL_SBR_SHIFT                       0
+#define UART_BDL_SBR_WIDTH                       8
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK                          0x1u
+#define UART_C1_PT_SHIFT                         0
+#define UART_C1_PT_WIDTH                         1
+#define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
+#define UART_C1_PE_MASK                          0x2u
+#define UART_C1_PE_SHIFT                         1
+#define UART_C1_PE_WIDTH                         1
+#define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK                         0x4u
+#define UART_C1_ILT_SHIFT                        2
+#define UART_C1_ILT_WIDTH                        1
+#define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK                        0x8u
+#define UART_C1_WAKE_SHIFT                       3
+#define UART_C1_WAKE_WIDTH                       1
+#define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK                           0x10u
+#define UART_C1_M_SHIFT                          4
+#define UART_C1_M_WIDTH                          1
+#define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK                        0x20u
+#define UART_C1_RSRC_SHIFT                       5
+#define UART_C1_RSRC_WIDTH                       1
+#define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK                    0x40u
+#define UART_C1_UARTSWAI_SHIFT                   6
+#define UART_C1_UARTSWAI_WIDTH                   1
+#define UART_C1_UARTSWAI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C1_UARTSWAI_SHIFT))&UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK                       0x80u
+#define UART_C1_LOOPS_SHIFT                      7
+#define UART_C1_LOOPS_WIDTH                      1
+#define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK                         0x1u
+#define UART_C2_SBK_SHIFT                        0
+#define UART_C2_SBK_WIDTH                        1
+#define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK                         0x2u
+#define UART_C2_RWU_SHIFT                        1
+#define UART_C2_RWU_WIDTH                        1
+#define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK                          0x4u
+#define UART_C2_RE_SHIFT                         2
+#define UART_C2_RE_WIDTH                         1
+#define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
+#define UART_C2_TE_MASK                          0x8u
+#define UART_C2_TE_SHIFT                         3
+#define UART_C2_TE_WIDTH                         1
+#define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK                        0x10u
+#define UART_C2_ILIE_SHIFT                       4
+#define UART_C2_ILIE_WIDTH                       1
+#define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK                         0x20u
+#define UART_C2_RIE_SHIFT                        5
+#define UART_C2_RIE_WIDTH                        1
+#define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK                        0x40u
+#define UART_C2_TCIE_SHIFT                       6
+#define UART_C2_TCIE_WIDTH                       1
+#define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK                         0x80u
+#define UART_C2_TIE_SHIFT                        7
+#define UART_C2_TIE_WIDTH                        1
+#define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK                          0x1u
+#define UART_S1_PF_SHIFT                         0
+#define UART_S1_PF_WIDTH                         1
+#define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
+#define UART_S1_FE_MASK                          0x2u
+#define UART_S1_FE_SHIFT                         1
+#define UART_S1_FE_WIDTH                         1
+#define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
+#define UART_S1_NF_MASK                          0x4u
+#define UART_S1_NF_SHIFT                         2
+#define UART_S1_NF_WIDTH                         1
+#define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
+#define UART_S1_OR_MASK                          0x8u
+#define UART_S1_OR_SHIFT                         3
+#define UART_S1_OR_WIDTH                         1
+#define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK                        0x10u
+#define UART_S1_IDLE_SHIFT                       4
+#define UART_S1_IDLE_WIDTH                       1
+#define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK                        0x20u
+#define UART_S1_RDRF_SHIFT                       5
+#define UART_S1_RDRF_WIDTH                       1
+#define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK                          0x40u
+#define UART_S1_TC_SHIFT                         6
+#define UART_S1_TC_WIDTH                         1
+#define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK                        0x80u
+#define UART_S1_TDRE_SHIFT                       7
+#define UART_S1_TDRE_WIDTH                       1
+#define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK                         0x1u
+#define UART_S2_RAF_SHIFT                        0
+#define UART_S2_RAF_WIDTH                        1
+#define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK                       0x2u
+#define UART_S2_LBKDE_SHIFT                      1
+#define UART_S2_LBKDE_WIDTH                      1
+#define UART_S2_LBKDE(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDE_SHIFT))&UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK                       0x4u
+#define UART_S2_BRK13_SHIFT                      2
+#define UART_S2_BRK13_WIDTH                      1
+#define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK                       0x8u
+#define UART_S2_RWUID_SHIFT                      3
+#define UART_S2_RWUID_WIDTH                      1
+#define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK                       0x10u
+#define UART_S2_RXINV_SHIFT                      4
+#define UART_S2_RXINV_WIDTH                      1
+#define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK                        0x20u
+#define UART_S2_MSBF_SHIFT                       5
+#define UART_S2_MSBF_WIDTH                       1
+#define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S2_MSBF_SHIFT))&UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK                     0x40u
+#define UART_S2_RXEDGIF_SHIFT                    6
+#define UART_S2_RXEDGIF_WIDTH                    1
+#define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK                      0x80u
+#define UART_S2_LBKDIF_SHIFT                     7
+#define UART_S2_LBKDIF_WIDTH                     1
+#define UART_S2_LBKDIF(x)                        (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDIF_SHIFT))&UART_S2_LBKDIF_MASK)
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK                        0x1u
+#define UART_C3_PEIE_SHIFT                       0
+#define UART_C3_PEIE_WIDTH                       1
+#define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK                        0x2u
+#define UART_C3_FEIE_SHIFT                       1
+#define UART_C3_FEIE_WIDTH                       1
+#define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK                        0x4u
+#define UART_C3_NEIE_SHIFT                       2
+#define UART_C3_NEIE_WIDTH                       1
+#define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK                        0x8u
+#define UART_C3_ORIE_SHIFT                       3
+#define UART_C3_ORIE_WIDTH                       1
+#define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK                       0x10u
+#define UART_C3_TXINV_SHIFT                      4
+#define UART_C3_TXINV_WIDTH                      1
+#define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK                       0x20u
+#define UART_C3_TXDIR_SHIFT                      5
+#define UART_C3_TXDIR_WIDTH                      1
+#define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK                          0x40u
+#define UART_C3_T8_SHIFT                         6
+#define UART_C3_T8_WIDTH                         1
+#define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
+#define UART_C3_R8_MASK                          0x80u
+#define UART_C3_R8_SHIFT                         7
+#define UART_C3_R8_WIDTH                         1
+#define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
+/* D Bit Fields */
+#define UART_D_RT_MASK                           0xFFu
+#define UART_D_RT_SHIFT                          0
+#define UART_D_RT_WIDTH                          8
+#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK                         0xFFu
+#define UART_MA1_MA_SHIFT                        0
+#define UART_MA1_MA_WIDTH                        8
+#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK                         0xFFu
+#define UART_MA2_MA_SHIFT                        0
+#define UART_MA2_MA_WIDTH                        8
+#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK                        0x1Fu
+#define UART_C4_BRFA_SHIFT                       0
+#define UART_C4_BRFA_WIDTH                       5
+#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK                         0x20u
+#define UART_C4_M10_SHIFT                        5
+#define UART_C4_M10_WIDTH                        1
+#define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C4_M10_SHIFT))&UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK                       0x40u
+#define UART_C4_MAEN2_SHIFT                      6
+#define UART_C4_MAEN2_WIDTH                      1
+#define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN2_SHIFT))&UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK                       0x80u
+#define UART_C4_MAEN1_SHIFT                      7
+#define UART_C4_MAEN1_WIDTH                      1
+#define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN1_SHIFT))&UART_C4_MAEN1_MASK)
+/* C5 Bit Fields */
+#define UART_C5_LBKDDMAS_MASK                    0x8u
+#define UART_C5_LBKDDMAS_SHIFT                   3
+#define UART_C5_LBKDDMAS_WIDTH                   1
+#define UART_C5_LBKDDMAS(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C5_LBKDDMAS_SHIFT))&UART_C5_LBKDDMAS_MASK)
+#define UART_C5_ILDMAS_MASK                      0x10u
+#define UART_C5_ILDMAS_SHIFT                     4
+#define UART_C5_ILDMAS_WIDTH                     1
+#define UART_C5_ILDMAS(x)                        (((uint8_t)(((uint8_t)(x))<<UART_C5_ILDMAS_SHIFT))&UART_C5_ILDMAS_MASK)
+#define UART_C5_RDMAS_MASK                       0x20u
+#define UART_C5_RDMAS_SHIFT                      5
+#define UART_C5_RDMAS_WIDTH                      1
+#define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_RDMAS_SHIFT))&UART_C5_RDMAS_MASK)
+#define UART_C5_TCDMAS_MASK                      0x40u
+#define UART_C5_TCDMAS_SHIFT                     6
+#define UART_C5_TCDMAS_WIDTH                     1
+#define UART_C5_TCDMAS(x)                        (((uint8_t)(((uint8_t)(x))<<UART_C5_TCDMAS_SHIFT))&UART_C5_TCDMAS_MASK)
+#define UART_C5_TDMAS_MASK                       0x80u
+#define UART_C5_TDMAS_SHIFT                      7
+#define UART_C5_TDMAS_WIDTH                      1
+#define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_TDMAS_SHIFT))&UART_C5_TDMAS_MASK)
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK                     0x40u
+#define UART_ED_PARITYE_SHIFT                    6
+#define UART_ED_PARITYE_WIDTH                    1
+#define UART_ED_PARITYE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_ED_PARITYE_SHIFT))&UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK                       0x80u
+#define UART_ED_NOISY_SHIFT                      7
+#define UART_ED_NOISY_WIDTH                      1
+#define UART_ED_NOISY(x)                         (((uint8_t)(((uint8_t)(x))<<UART_ED_NOISY_SHIFT))&UART_ED_NOISY_MASK)
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK                   0x1u
+#define UART_MODEM_TXCTSE_SHIFT                  0
+#define UART_MODEM_TXCTSE_WIDTH                  1
+#define UART_MODEM_TXCTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXCTSE_SHIFT))&UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK                   0x2u
+#define UART_MODEM_TXRTSE_SHIFT                  1
+#define UART_MODEM_TXRTSE_WIDTH                  1
+#define UART_MODEM_TXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSE_SHIFT))&UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK                 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT                2
+#define UART_MODEM_TXRTSPOL_WIDTH                1
+#define UART_MODEM_TXRTSPOL(x)                   (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSPOL_SHIFT))&UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK                   0x8u
+#define UART_MODEM_RXRTSE_SHIFT                  3
+#define UART_MODEM_RXRTSE_WIDTH                  1
+#define UART_MODEM_RXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_RXRTSE_SHIFT))&UART_MODEM_RXRTSE_MASK)
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK                         0x3u
+#define UART_IR_TNP_SHIFT                        0
+#define UART_IR_TNP_WIDTH                        2
+#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK                        0x4u
+#define UART_IR_IREN_SHIFT                       2
+#define UART_IR_IREN_WIDTH                       1
+#define UART_IR_IREN(x)                          (((uint8_t)(((uint8_t)(x))<<UART_IR_IREN_SHIFT))&UART_IR_IREN_MASK)
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK               0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT              0
+#define UART_PFIFO_RXFIFOSIZE_WIDTH              3
+#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK                     0x8u
+#define UART_PFIFO_RXFE_SHIFT                    3
+#define UART_PFIFO_RXFE_WIDTH                    1
+#define UART_PFIFO_RXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFE_SHIFT))&UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK               0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT              4
+#define UART_PFIFO_TXFIFOSIZE_WIDTH              3
+#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK                     0x80u
+#define UART_PFIFO_TXFE_SHIFT                    7
+#define UART_PFIFO_TXFE_WIDTH                    1
+#define UART_PFIFO_TXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFE_SHIFT))&UART_PFIFO_TXFE_MASK)
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK                    0x1u
+#define UART_CFIFO_RXUFE_SHIFT                   0
+#define UART_CFIFO_RXUFE_WIDTH                   1
+#define UART_CFIFO_RXUFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXUFE_SHIFT))&UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK                    0x2u
+#define UART_CFIFO_TXOFE_SHIFT                   1
+#define UART_CFIFO_TXOFE_WIDTH                   1
+#define UART_CFIFO_TXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXOFE_SHIFT))&UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXOFE_MASK                    0x4u
+#define UART_CFIFO_RXOFE_SHIFT                   2
+#define UART_CFIFO_RXOFE_WIDTH                   1
+#define UART_CFIFO_RXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXOFE_SHIFT))&UART_CFIFO_RXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK                  0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT                 6
+#define UART_CFIFO_RXFLUSH_WIDTH                 1
+#define UART_CFIFO_RXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXFLUSH_SHIFT))&UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK                  0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT                 7
+#define UART_CFIFO_TXFLUSH_WIDTH                 1
+#define UART_CFIFO_TXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXFLUSH_SHIFT))&UART_CFIFO_TXFLUSH_MASK)
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK                     0x1u
+#define UART_SFIFO_RXUF_SHIFT                    0
+#define UART_SFIFO_RXUF_WIDTH                    1
+#define UART_SFIFO_RXUF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXUF_SHIFT))&UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK                     0x2u
+#define UART_SFIFO_TXOF_SHIFT                    1
+#define UART_SFIFO_TXOF_WIDTH                    1
+#define UART_SFIFO_TXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXOF_SHIFT))&UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXOF_MASK                     0x4u
+#define UART_SFIFO_RXOF_SHIFT                    2
+#define UART_SFIFO_RXOF_WIDTH                    1
+#define UART_SFIFO_RXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXOF_SHIFT))&UART_SFIFO_RXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK                   0x40u
+#define UART_SFIFO_RXEMPT_SHIFT                  6
+#define UART_SFIFO_RXEMPT_WIDTH                  1
+#define UART_SFIFO_RXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXEMPT_SHIFT))&UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK                   0x80u
+#define UART_SFIFO_TXEMPT_SHIFT                  7
+#define UART_SFIFO_TXEMPT_WIDTH                  1
+#define UART_SFIFO_TXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXEMPT_SHIFT))&UART_SFIFO_TXEMPT_MASK)
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK                 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT                0
+#define UART_TWFIFO_TXWATER_WIDTH                8
+#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK                 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT                0
+#define UART_TCFIFO_TXCOUNT_WIDTH                8
+#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK                 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT                0
+#define UART_RWFIFO_RXWATER_WIDTH                8
+#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK                 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT                0
+#define UART_RCFIFO_RXCOUNT_WIDTH                8
+#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK                0x1u
+#define UART_C7816_ISO_7816E_SHIFT               0
+#define UART_C7816_ISO_7816E_WIDTH               1
+#define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x))<<UART_C7816_ISO_7816E_SHIFT))&UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK                    0x2u
+#define UART_C7816_TTYPE_SHIFT                   1
+#define UART_C7816_TTYPE_WIDTH                   1
+#define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_TTYPE_SHIFT))&UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK                     0x4u
+#define UART_C7816_INIT_SHIFT                    2
+#define UART_C7816_INIT_WIDTH                    1
+#define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_C7816_INIT_SHIFT))&UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK                    0x8u
+#define UART_C7816_ANACK_SHIFT                   3
+#define UART_C7816_ANACK_WIDTH                   1
+#define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ANACK_SHIFT))&UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK                    0x10u
+#define UART_C7816_ONACK_SHIFT                   4
+#define UART_C7816_ONACK_WIDTH                   1
+#define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ONACK_SHIFT))&UART_C7816_ONACK_MASK)
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK                    0x1u
+#define UART_IE7816_RXTE_SHIFT                   0
+#define UART_IE7816_RXTE_WIDTH                   1
+#define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_RXTE_SHIFT))&UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK                    0x2u
+#define UART_IE7816_TXTE_SHIFT                   1
+#define UART_IE7816_TXTE_WIDTH                   1
+#define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_TXTE_SHIFT))&UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK                    0x4u
+#define UART_IE7816_GTVE_SHIFT                   2
+#define UART_IE7816_GTVE_WIDTH                   1
+#define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_GTVE_SHIFT))&UART_IE7816_GTVE_MASK)
+#define UART_IE7816_INITDE_MASK                  0x10u
+#define UART_IE7816_INITDE_SHIFT                 4
+#define UART_IE7816_INITDE_WIDTH                 1
+#define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x))<<UART_IE7816_INITDE_SHIFT))&UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK                    0x20u
+#define UART_IE7816_BWTE_SHIFT                   5
+#define UART_IE7816_BWTE_WIDTH                   1
+#define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_BWTE_SHIFT))&UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK                    0x40u
+#define UART_IE7816_CWTE_SHIFT                   6
+#define UART_IE7816_CWTE_WIDTH                   1
+#define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_CWTE_SHIFT))&UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK                     0x80u
+#define UART_IE7816_WTE_SHIFT                    7
+#define UART_IE7816_WTE_WIDTH                    1
+#define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IE7816_WTE_SHIFT))&UART_IE7816_WTE_MASK)
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK                     0x1u
+#define UART_IS7816_RXT_SHIFT                    0
+#define UART_IS7816_RXT_WIDTH                    1
+#define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_RXT_SHIFT))&UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK                     0x2u
+#define UART_IS7816_TXT_SHIFT                    1
+#define UART_IS7816_TXT_WIDTH                    1
+#define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_TXT_SHIFT))&UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK                     0x4u
+#define UART_IS7816_GTV_SHIFT                    2
+#define UART_IS7816_GTV_WIDTH                    1
+#define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_GTV_SHIFT))&UART_IS7816_GTV_MASK)
+#define UART_IS7816_INITD_MASK                   0x10u
+#define UART_IS7816_INITD_SHIFT                  4
+#define UART_IS7816_INITD_WIDTH                  1
+#define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x))<<UART_IS7816_INITD_SHIFT))&UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK                     0x20u
+#define UART_IS7816_BWT_SHIFT                    5
+#define UART_IS7816_BWT_WIDTH                    1
+#define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_BWT_SHIFT))&UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK                     0x40u
+#define UART_IS7816_CWT_SHIFT                    6
+#define UART_IS7816_CWT_WIDTH                    1
+#define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_CWT_SHIFT))&UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK                      0x80u
+#define UART_IS7816_WT_SHIFT                     7
+#define UART_IS7816_WT_WIDTH                     1
+#define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x))<<UART_IS7816_WT_SHIFT))&UART_IS7816_WT_MASK)
+/* WP7816T0 Bit Fields */
+#define UART_WP7816T0_WI_MASK                    0xFFu
+#define UART_WP7816T0_WI_SHIFT                   0
+#define UART_WP7816T0_WI_WIDTH                   8
+#define UART_WP7816T0_WI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
+/* WP7816T1 Bit Fields */
+#define UART_WP7816T1_BWI_MASK                   0xFu
+#define UART_WP7816T1_BWI_SHIFT                  0
+#define UART_WP7816T1_BWI_WIDTH                  4
+#define UART_WP7816T1_BWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
+#define UART_WP7816T1_CWI_MASK                   0xF0u
+#define UART_WP7816T1_CWI_SHIFT                  4
+#define UART_WP7816T1_CWI_WIDTH                  4
+#define UART_WP7816T1_CWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK                     0xFFu
+#define UART_WN7816_GTN_SHIFT                    0
+#define UART_WN7816_GTN_WIDTH                    8
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK                    0xFFu
+#define UART_WF7816_GTFD_SHIFT                   0
+#define UART_WF7816_GTFD_WIDTH                   8
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK             0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT            0
+#define UART_ET7816_RXTHRESHOLD_WIDTH            4
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK             0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT            4
+#define UART_ET7816_TXTHRESHOLD_WIDTH            4
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK                    0xFFu
+#define UART_TL7816_TLEN_SHIFT                   0
+#define UART_TL7816_TLEN_WIDTH                   8
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0                                    ((UART_Type *)UART0_BASE)
+#define UART0_BASE_PTR                           (UART0)
+/** Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1                                    ((UART_Type *)UART1_BASE)
+#define UART1_BASE_PTR                           (UART1)
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR                           (UART2)
+/** Peripheral UART3 base address */
+#define UART3_BASE                               (0x4006D000u)
+/** Peripheral UART3 base pointer */
+#define UART3                                    ((UART_Type *)UART3_BASE)
+#define UART3_BASE_PTR                           (UART3)
+/** Peripheral UART4 base address */
+#define UART4_BASE                               (0x400EA000u)
+/** Peripheral UART4 base pointer */
+#define UART4                                    ((UART_Type *)UART4_BASE)
+#define UART4_BASE_PTR                           (UART4)
+/** Peripheral UART5 base address */
+#define UART5_BASE                               (0x400EB000u)
+/** Peripheral UART5 base pointer */
+#define UART5                                    ((UART_Type *)UART5_BASE)
+#define UART5_BASE_PTR                           (UART5)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS                           { UART0, UART1, UART2, UART3, UART4, UART5 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS                          { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
+#define UART_ERR_IRQS                            { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
+#define UART_LON_IRQS                            { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART0 */
+#define UART0_BDH                                UART_BDH_REG(UART0)
+#define UART0_BDL                                UART_BDL_REG(UART0)
+#define UART0_C1                                 UART_C1_REG(UART0)
+#define UART0_C2                                 UART_C2_REG(UART0)
+#define UART0_S1                                 UART_S1_REG(UART0)
+#define UART0_S2                                 UART_S2_REG(UART0)
+#define UART0_C3                                 UART_C3_REG(UART0)
+#define UART0_D                                  UART_D_REG(UART0)
+#define UART0_MA1                                UART_MA1_REG(UART0)
+#define UART0_MA2                                UART_MA2_REG(UART0)
+#define UART0_C4                                 UART_C4_REG(UART0)
+#define UART0_C5                                 UART_C5_REG(UART0)
+#define UART0_ED                                 UART_ED_REG(UART0)
+#define UART0_MODEM                              UART_MODEM_REG(UART0)
+#define UART0_IR                                 UART_IR_REG(UART0)
+#define UART0_PFIFO                              UART_PFIFO_REG(UART0)
+#define UART0_CFIFO                              UART_CFIFO_REG(UART0)
+#define UART0_SFIFO                              UART_SFIFO_REG(UART0)
+#define UART0_TWFIFO                             UART_TWFIFO_REG(UART0)
+#define UART0_TCFIFO                             UART_TCFIFO_REG(UART0)
+#define UART0_RWFIFO                             UART_RWFIFO_REG(UART0)
+#define UART0_RCFIFO                             UART_RCFIFO_REG(UART0)
+#define UART0_C7816                              UART_C7816_REG(UART0)
+#define UART0_IE7816                             UART_IE7816_REG(UART0)
+#define UART0_IS7816                             UART_IS7816_REG(UART0)
+#define UART0_WP7816T0                           UART_WP7816T0_REG(UART0)
+#define UART0_WP7816T1                           UART_WP7816T1_REG(UART0)
+#define UART0_WN7816                             UART_WN7816_REG(UART0)
+#define UART0_WF7816                             UART_WF7816_REG(UART0)
+#define UART0_ET7816                             UART_ET7816_REG(UART0)
+#define UART0_TL7816                             UART_TL7816_REG(UART0)
+/* UART1 */
+#define UART1_BDH                                UART_BDH_REG(UART1)
+#define UART1_BDL                                UART_BDL_REG(UART1)
+#define UART1_C1                                 UART_C1_REG(UART1)
+#define UART1_C2                                 UART_C2_REG(UART1)
+#define UART1_S1                                 UART_S1_REG(UART1)
+#define UART1_S2                                 UART_S2_REG(UART1)
+#define UART1_C3                                 UART_C3_REG(UART1)
+#define UART1_D                                  UART_D_REG(UART1)
+#define UART1_MA1                                UART_MA1_REG(UART1)
+#define UART1_MA2                                UART_MA2_REG(UART1)
+#define UART1_C4                                 UART_C4_REG(UART1)
+#define UART1_C5                                 UART_C5_REG(UART1)
+#define UART1_ED                                 UART_ED_REG(UART1)
+#define UART1_MODEM                              UART_MODEM_REG(UART1)
+#define UART1_IR                                 UART_IR_REG(UART1)
+#define UART1_PFIFO                              UART_PFIFO_REG(UART1)
+#define UART1_CFIFO                              UART_CFIFO_REG(UART1)
+#define UART1_SFIFO                              UART_SFIFO_REG(UART1)
+#define UART1_TWFIFO                             UART_TWFIFO_REG(UART1)
+#define UART1_TCFIFO                             UART_TCFIFO_REG(UART1)
+#define UART1_RWFIFO                             UART_RWFIFO_REG(UART1)
+#define UART1_RCFIFO                             UART_RCFIFO_REG(UART1)
+/* UART2 */
+#define UART2_BDH                                UART_BDH_REG(UART2)
+#define UART2_BDL                                UART_BDL_REG(UART2)
+#define UART2_C1                                 UART_C1_REG(UART2)
+#define UART2_C2                                 UART_C2_REG(UART2)
+#define UART2_S1                                 UART_S1_REG(UART2)
+#define UART2_S2                                 UART_S2_REG(UART2)
+#define UART2_C3                                 UART_C3_REG(UART2)
+#define UART2_D                                  UART_D_REG(UART2)
+#define UART2_MA1                                UART_MA1_REG(UART2)
+#define UART2_MA2                                UART_MA2_REG(UART2)
+#define UART2_C4                                 UART_C4_REG(UART2)
+#define UART2_C5                                 UART_C5_REG(UART2)
+#define UART2_ED                                 UART_ED_REG(UART2)
+#define UART2_MODEM                              UART_MODEM_REG(UART2)
+#define UART2_IR                                 UART_IR_REG(UART2)
+#define UART2_PFIFO                              UART_PFIFO_REG(UART2)
+#define UART2_CFIFO                              UART_CFIFO_REG(UART2)
+#define UART2_SFIFO                              UART_SFIFO_REG(UART2)
+#define UART2_TWFIFO                             UART_TWFIFO_REG(UART2)
+#define UART2_TCFIFO                             UART_TCFIFO_REG(UART2)
+#define UART2_RWFIFO                             UART_RWFIFO_REG(UART2)
+#define UART2_RCFIFO                             UART_RCFIFO_REG(UART2)
+/* UART3 */
+#define UART3_BDH                                UART_BDH_REG(UART3)
+#define UART3_BDL                                UART_BDL_REG(UART3)
+#define UART3_C1                                 UART_C1_REG(UART3)
+#define UART3_C2                                 UART_C2_REG(UART3)
+#define UART3_S1                                 UART_S1_REG(UART3)
+#define UART3_S2                                 UART_S2_REG(UART3)
+#define UART3_C3                                 UART_C3_REG(UART3)
+#define UART3_D                                  UART_D_REG(UART3)
+#define UART3_MA1                                UART_MA1_REG(UART3)
+#define UART3_MA2                                UART_MA2_REG(UART3)
+#define UART3_C4                                 UART_C4_REG(UART3)
+#define UART3_C5                                 UART_C5_REG(UART3)
+#define UART3_ED                                 UART_ED_REG(UART3)
+#define UART3_MODEM                              UART_MODEM_REG(UART3)
+#define UART3_IR                                 UART_IR_REG(UART3)
+#define UART3_PFIFO                              UART_PFIFO_REG(UART3)
+#define UART3_CFIFO                              UART_CFIFO_REG(UART3)
+#define UART3_SFIFO                              UART_SFIFO_REG(UART3)
+#define UART3_TWFIFO                             UART_TWFIFO_REG(UART3)
+#define UART3_TCFIFO                             UART_TCFIFO_REG(UART3)
+#define UART3_RWFIFO                             UART_RWFIFO_REG(UART3)
+#define UART3_RCFIFO                             UART_RCFIFO_REG(UART3)
+/* UART4 */
+#define UART4_BDH                                UART_BDH_REG(UART4)
+#define UART4_BDL                                UART_BDL_REG(UART4)
+#define UART4_C1                                 UART_C1_REG(UART4)
+#define UART4_C2                                 UART_C2_REG(UART4)
+#define UART4_S1                                 UART_S1_REG(UART4)
+#define UART4_S2                                 UART_S2_REG(UART4)
+#define UART4_C3                                 UART_C3_REG(UART4)
+#define UART4_D                                  UART_D_REG(UART4)
+#define UART4_MA1                                UART_MA1_REG(UART4)
+#define UART4_MA2                                UART_MA2_REG(UART4)
+#define UART4_C4                                 UART_C4_REG(UART4)
+#define UART4_C5                                 UART_C5_REG(UART4)
+#define UART4_ED                                 UART_ED_REG(UART4)
+#define UART4_MODEM                              UART_MODEM_REG(UART4)
+#define UART4_IR                                 UART_IR_REG(UART4)
+#define UART4_PFIFO                              UART_PFIFO_REG(UART4)
+#define UART4_CFIFO                              UART_CFIFO_REG(UART4)
+#define UART4_SFIFO                              UART_SFIFO_REG(UART4)
+#define UART4_TWFIFO                             UART_TWFIFO_REG(UART4)
+#define UART4_TCFIFO                             UART_TCFIFO_REG(UART4)
+#define UART4_RWFIFO                             UART_RWFIFO_REG(UART4)
+#define UART4_RCFIFO                             UART_RCFIFO_REG(UART4)
+/* UART5 */
+#define UART5_BDH                                UART_BDH_REG(UART5)
+#define UART5_BDL                                UART_BDL_REG(UART5)
+#define UART5_C1                                 UART_C1_REG(UART5)
+#define UART5_C2                                 UART_C2_REG(UART5)
+#define UART5_S1                                 UART_S1_REG(UART5)
+#define UART5_S2                                 UART_S2_REG(UART5)
+#define UART5_C3                                 UART_C3_REG(UART5)
+#define UART5_D                                  UART_D_REG(UART5)
+#define UART5_MA1                                UART_MA1_REG(UART5)
+#define UART5_MA2                                UART_MA2_REG(UART5)
+#define UART5_C4                                 UART_C4_REG(UART5)
+#define UART5_C5                                 UART_C5_REG(UART5)
+#define UART5_ED                                 UART_ED_REG(UART5)
+#define UART5_MODEM                              UART_MODEM_REG(UART5)
+#define UART5_IR                                 UART_IR_REG(UART5)
+#define UART5_PFIFO                              UART_PFIFO_REG(UART5)
+#define UART5_CFIFO                              UART_CFIFO_REG(UART5)
+#define UART5_SFIFO                              UART_SFIFO_REG(UART5)
+#define UART5_TWFIFO                             UART_TWFIFO_REG(UART5)
+#define UART5_TCFIFO                             UART_TCFIFO_REG(UART5)
+#define UART5_RWFIFO                             UART_RWFIFO_REG(UART5)
+#define UART5_RCFIFO                             UART_RCFIFO_REG(UART5)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[3];
+  __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t OTGICR;                             /**< OTG Interrupt Control register, offset: 0x14 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_7[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_11[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_16[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t SOFTHLD;                            /**< SOF Threshold register, offset: 0xAC */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_20[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_21[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_22[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_25[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
+       uint8_t RESERVED_26[43];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_27[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48M oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_28[23];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base)                      ((base)->PERID)
+#define USB_IDCOMP_REG(base)                     ((base)->IDCOMP)
+#define USB_REV_REG(base)                        ((base)->REV)
+#define USB_ADDINFO_REG(base)                    ((base)->ADDINFO)
+#define USB_OTGISTAT_REG(base)                   ((base)->OTGISTAT)
+#define USB_OTGICR_REG(base)                     ((base)->OTGICR)
+#define USB_OTGSTAT_REG(base)                    ((base)->OTGSTAT)
+#define USB_OTGCTL_REG(base)                     ((base)->OTGCTL)
+#define USB_ISTAT_REG(base)                      ((base)->ISTAT)
+#define USB_INTEN_REG(base)                      ((base)->INTEN)
+#define USB_ERRSTAT_REG(base)                    ((base)->ERRSTAT)
+#define USB_ERREN_REG(base)                      ((base)->ERREN)
+#define USB_STAT_REG(base)                       ((base)->STAT)
+#define USB_CTL_REG(base)                        ((base)->CTL)
+#define USB_ADDR_REG(base)                       ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base)                   ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base)                    ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base)                    ((base)->FRMNUMH)
+#define USB_TOKEN_REG(base)                      ((base)->TOKEN)
+#define USB_SOFTHLD_REG(base)                    ((base)->SOFTHLD)
+#define USB_BDTPAGE2_REG(base)                   ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base)                   ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index)                ((base)->ENDPOINT[index].ENDPT)
+#define USB_ENDPT_COUNT                          16
+#define USB_USBCTRL_REG(base)                    ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base)                    ((base)->OBSERVE)
+#define USB_CONTROL_REG(base)                    ((base)->CONTROL)
+#define USB_USBTRC0_REG(base)                    ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base)               ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base)           ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base)         ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base)     ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK                        0x3Fu
+#define USB_PERID_ID_SHIFT                       0
+#define USB_PERID_ID_WIDTH                       6
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK                      0x3Fu
+#define USB_IDCOMP_NID_SHIFT                     0
+#define USB_IDCOMP_NID_WIDTH                     6
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK                         0xFFu
+#define USB_REV_REV_SHIFT                        0
+#define USB_REV_REV_WIDTH                        8
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK                  0x1u
+#define USB_ADDINFO_IEHOST_SHIFT                 0
+#define USB_ADDINFO_IEHOST_WIDTH                 1
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
+#define USB_ADDINFO_IRQNUM_MASK                  0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT                 3
+#define USB_ADDINFO_IRQNUM_WIDTH                 5
+#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK               0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT              0
+#define USB_OTGISTAT_AVBUSCHG_WIDTH              1
+#define USB_OTGISTAT_AVBUSCHG(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_AVBUSCHG_SHIFT))&USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK             0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT            2
+#define USB_OTGISTAT_B_SESS_CHG_WIDTH            1
+#define USB_OTGISTAT_B_SESS_CHG(x)               (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_B_SESS_CHG_SHIFT))&USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK             0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT            3
+#define USB_OTGISTAT_SESSVLDCHG_WIDTH            1
+#define USB_OTGISTAT_SESSVLDCHG(x)               (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_SESSVLDCHG_SHIFT))&USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK         0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        5
+#define USB_OTGISTAT_LINE_STATE_CHG_WIDTH        1
+#define USB_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK                0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT               6
+#define USB_OTGISTAT_ONEMSEC_WIDTH               1
+#define USB_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK                  0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT                 7
+#define USB_OTGISTAT_IDCHG_WIDTH                 1
+#define USB_OTGISTAT_IDCHG(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_IDCHG_SHIFT))&USB_OTGISTAT_IDCHG_MASK)
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK                  0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT                 0
+#define USB_OTGICR_AVBUSEN_WIDTH                 1
+#define USB_OTGICR_AVBUSEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_AVBUSEN_SHIFT))&USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK                  0x4u
+#define USB_OTGICR_BSESSEN_SHIFT                 2
+#define USB_OTGICR_BSESSEN_WIDTH                 1
+#define USB_OTGICR_BSESSEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_BSESSEN_SHIFT))&USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK                0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT               3
+#define USB_OTGICR_SESSVLDEN_WIDTH               1
+#define USB_OTGICR_SESSVLDEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_SESSVLDEN_SHIFT))&USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK              0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT             5
+#define USB_OTGICR_LINESTATEEN_WIDTH             1
+#define USB_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK                0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT               6
+#define USB_OTGICR_ONEMSECEN_WIDTH               1
+#define USB_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK                     0x80u
+#define USB_OTGICR_IDEN_SHIFT                    7
+#define USB_OTGICR_IDEN_WIDTH                    1
+#define USB_OTGICR_IDEN(x)                       (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_IDEN_SHIFT))&USB_OTGICR_IDEN_MASK)
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK                0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT               0
+#define USB_OTGSTAT_AVBUSVLD_WIDTH               1
+#define USB_OTGSTAT_AVBUSVLD(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_AVBUSVLD_SHIFT))&USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK                0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT               2
+#define USB_OTGSTAT_BSESSEND_WIDTH               1
+#define USB_OTGSTAT_BSESSEND(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_BSESSEND_SHIFT))&USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK                0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT               3
+#define USB_OTGSTAT_SESS_VLD_WIDTH               1
+#define USB_OTGSTAT_SESS_VLD(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_SESS_VLD_SHIFT))&USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK         0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        5
+#define USB_OTGSTAT_LINESTATESTABLE_WIDTH        1
+#define USB_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK               0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT              6
+#define USB_OTGSTAT_ONEMSECEN_WIDTH              1
+#define USB_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK                      0x80u
+#define USB_OTGSTAT_ID_SHIFT                     7
+#define USB_OTGSTAT_ID_WIDTH                     1
+#define USB_OTGSTAT_ID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ID_SHIFT))&USB_OTGSTAT_ID_MASK)
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK                    0x4u
+#define USB_OTGCTL_OTGEN_SHIFT                   2
+#define USB_OTGCTL_OTGEN_WIDTH                   1
+#define USB_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK                    0x10u
+#define USB_OTGCTL_DMLOW_SHIFT                   4
+#define USB_OTGCTL_DMLOW_WIDTH                   1
+#define USB_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK                    0x20u
+#define USB_OTGCTL_DPLOW_SHIFT                   5
+#define USB_OTGCTL_DPLOW_WIDTH                   1
+#define USB_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK                   0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT                  7
+#define USB_OTGCTL_DPHIGH_WIDTH                  1
+#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK                    0x1u
+#define USB_ISTAT_USBRST_SHIFT                   0
+#define USB_ISTAT_USBRST_WIDTH                   1
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK                     0x2u
+#define USB_ISTAT_ERROR_SHIFT                    1
+#define USB_ISTAT_ERROR_WIDTH                    1
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK                    0x4u
+#define USB_ISTAT_SOFTOK_SHIFT                   2
+#define USB_ISTAT_SOFTOK_WIDTH                   1
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK                    0x8u
+#define USB_ISTAT_TOKDNE_SHIFT                   3
+#define USB_ISTAT_TOKDNE_WIDTH                   1
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK                     0x10u
+#define USB_ISTAT_SLEEP_SHIFT                    4
+#define USB_ISTAT_SLEEP_WIDTH                    1
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK                    0x20u
+#define USB_ISTAT_RESUME_SHIFT                   5
+#define USB_ISTAT_RESUME_WIDTH                   1
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK                    0x40u
+#define USB_ISTAT_ATTACH_SHIFT                   6
+#define USB_ISTAT_ATTACH_WIDTH                   1
+#define USB_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK                     0x80u
+#define USB_ISTAT_STALL_SHIFT                    7
+#define USB_ISTAT_STALL_WIDTH                    1
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK                  0x1u
+#define USB_INTEN_USBRSTEN_SHIFT                 0
+#define USB_INTEN_USBRSTEN_WIDTH                 1
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK                   0x2u
+#define USB_INTEN_ERROREN_SHIFT                  1
+#define USB_INTEN_ERROREN_WIDTH                  1
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK                  0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT                 2
+#define USB_INTEN_SOFTOKEN_WIDTH                 1
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK                  0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT                 3
+#define USB_INTEN_TOKDNEEN_WIDTH                 1
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK                   0x10u
+#define USB_INTEN_SLEEPEN_SHIFT                  4
+#define USB_INTEN_SLEEPEN_WIDTH                  1
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK                  0x20u
+#define USB_INTEN_RESUMEEN_SHIFT                 5
+#define USB_INTEN_RESUMEEN_WIDTH                 1
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK                  0x40u
+#define USB_INTEN_ATTACHEN_SHIFT                 6
+#define USB_INTEN_ATTACHEN_WIDTH                 1
+#define USB_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK                   0x80u
+#define USB_INTEN_STALLEN_SHIFT                  7
+#define USB_INTEN_STALLEN_WIDTH                  1
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK                  0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT                 0
+#define USB_ERRSTAT_PIDERR_WIDTH                 1
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK                 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT                1
+#define USB_ERRSTAT_CRC5EOF_WIDTH                1
+#define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK                   0x4u
+#define USB_ERRSTAT_CRC16_SHIFT                  2
+#define USB_ERRSTAT_CRC16_WIDTH                  1
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK                    0x8u
+#define USB_ERRSTAT_DFN8_SHIFT                   3
+#define USB_ERRSTAT_DFN8_WIDTH                   1
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK                  0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT                 4
+#define USB_ERRSTAT_BTOERR_WIDTH                 1
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK                  0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT                 5
+#define USB_ERRSTAT_DMAERR_WIDTH                 1
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK                  0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT                 7
+#define USB_ERRSTAT_BTSERR_WIDTH                 1
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK                  0x1u
+#define USB_ERREN_PIDERREN_SHIFT                 0
+#define USB_ERREN_PIDERREN_WIDTH                 1
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK                 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT                1
+#define USB_ERREN_CRC5EOFEN_WIDTH                1
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK                   0x4u
+#define USB_ERREN_CRC16EN_SHIFT                  2
+#define USB_ERREN_CRC16EN_WIDTH                  1
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK                    0x8u
+#define USB_ERREN_DFN8EN_SHIFT                   3
+#define USB_ERREN_DFN8EN_WIDTH                   1
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK                  0x10u
+#define USB_ERREN_BTOERREN_SHIFT                 4
+#define USB_ERREN_BTOERREN_WIDTH                 1
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK                  0x20u
+#define USB_ERREN_DMAERREN_SHIFT                 5
+#define USB_ERREN_DMAERREN_WIDTH                 1
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK                  0x80u
+#define USB_ERREN_BTSERREN_SHIFT                 7
+#define USB_ERREN_BTSERREN_WIDTH                 1
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK                        0x4u
+#define USB_STAT_ODD_SHIFT                       2
+#define USB_STAT_ODD_WIDTH                       1
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK                         0x8u
+#define USB_STAT_TX_SHIFT                        3
+#define USB_STAT_TX_WIDTH                        1
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK                       0xF0u
+#define USB_STAT_ENDP_SHIFT                      4
+#define USB_STAT_ENDP_WIDTH                      4
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK                  0x1u
+#define USB_CTL_USBENSOFEN_SHIFT                 0
+#define USB_CTL_USBENSOFEN_WIDTH                 1
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK                      0x2u
+#define USB_CTL_ODDRST_SHIFT                     1
+#define USB_CTL_ODDRST_WIDTH                     1
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK                      0x4u
+#define USB_CTL_RESUME_SHIFT                     2
+#define USB_CTL_RESUME_WIDTH                     1
+#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK                  0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT                 3
+#define USB_CTL_HOSTMODEEN_WIDTH                 1
+#define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK                       0x10u
+#define USB_CTL_RESET_SHIFT                      4
+#define USB_CTL_RESET_WIDTH                      1
+#define USB_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
+#define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH         1
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK                         0x40u
+#define USB_CTL_SE0_SHIFT                        6
+#define USB_CTL_SE0_WIDTH                        1
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK                      0x80u
+#define USB_CTL_JSTATE_SHIFT                     7
+#define USB_CTL_JSTATE_WIDTH                     1
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK                       0x7Fu
+#define USB_ADDR_ADDR_SHIFT                      0
+#define USB_ADDR_ADDR_WIDTH                      7
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK                       0x80u
+#define USB_ADDR_LSEN_SHIFT                      7
+#define USB_ADDR_LSEN_WIDTH                      1
+#define USB_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT                 1
+#define USB_BDTPAGE1_BDTBA_WIDTH                 7
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK                     0xFFu
+#define USB_FRMNUML_FRM_SHIFT                    0
+#define USB_FRMNUML_FRM_WIDTH                    8
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK                     0x7u
+#define USB_FRMNUMH_FRM_SHIFT                    0
+#define USB_FRMNUMH_FRM_WIDTH                    3
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK                0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT               0
+#define USB_TOKEN_TOKENENDPT_WIDTH               4
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT                 4
+#define USB_TOKEN_TOKENPID_WIDTH                 4
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK                     0xFFu
+#define USB_SOFTHLD_CNT_SHIFT                    0
+#define USB_SOFTHLD_CNT_WIDTH                    8
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT                 0
+#define USB_BDTPAGE2_BDTBA_WIDTH                 8
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT                 0
+#define USB_BDTPAGE3_BDTBA_WIDTH                 8
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK                    0x1u
+#define USB_ENDPT_EPHSHK_SHIFT                   0
+#define USB_ENDPT_EPHSHK_WIDTH                   1
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK                   0x2u
+#define USB_ENDPT_EPSTALL_SHIFT                  1
+#define USB_ENDPT_EPSTALL_WIDTH                  1
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK                    0x4u
+#define USB_ENDPT_EPTXEN_SHIFT                   2
+#define USB_ENDPT_EPTXEN_WIDTH                   1
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK                    0x8u
+#define USB_ENDPT_EPRXEN_SHIFT                   3
+#define USB_ENDPT_EPRXEN_WIDTH                   1
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK                  0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT                 4
+#define USB_ENDPT_EPCTLDIS_WIDTH                 1
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK                  0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT                 6
+#define USB_ENDPT_RETRYDIS_WIDTH                 1
+#define USB_ENDPT_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK                 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT                7
+#define USB_ENDPT_HOSTWOHUB_WIDTH                1
+#define USB_ENDPT_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK                     0x40u
+#define USB_USBCTRL_PDE_SHIFT                    6
+#define USB_USBCTRL_PDE_WIDTH                    1
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK                    0x80u
+#define USB_USBCTRL_SUSP_SHIFT                   7
+#define USB_USBCTRL_SUSP_WIDTH                   1
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK                    0x10u
+#define USB_OBSERVE_DMPD_SHIFT                   4
+#define USB_OBSERVE_DMPD_WIDTH                   1
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK                    0x40u
+#define USB_OBSERVE_DPPD_SHIFT                   6
+#define USB_OBSERVE_DPPD_WIDTH                   1
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK                    0x80u
+#define USB_OBSERVE_DPPU_SHIFT                   7
+#define USB_OBSERVE_DPPU_WIDTH                   1
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
+#define USB_CONTROL_DPPULLUPNONOTG_WIDTH         1
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
+#define USB_USBTRC0_USB_RESUME_INT_WIDTH         1
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK                0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT               1
+#define USB_USBTRC0_SYNC_DET_WIDTH               1
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   2
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH   1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))&USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK               0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT              5
+#define USB_USBTRC0_USBRESMEN_WIDTH              1
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK                0x80u
+#define USB_USBTRC0_USBRESET_SHIFT               7
+#define USB_USBTRC0_USBRESET_WIDTH               1
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK                0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT               0
+#define USB_USBFRMADJUST_ADJ_WIDTH               8
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))&USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK       0x1u
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      0
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH 1
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))&USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR                            (USB0)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID                               USB_PERID_REG(USB0)
+#define USB0_IDCOMP                              USB_IDCOMP_REG(USB0)
+#define USB0_REV                                 USB_REV_REG(USB0)
+#define USB0_ADDINFO                             USB_ADDINFO_REG(USB0)
+#define USB0_OTGISTAT                            USB_OTGISTAT_REG(USB0)
+#define USB0_OTGICR                              USB_OTGICR_REG(USB0)
+#define USB0_OTGSTAT                             USB_OTGSTAT_REG(USB0)
+#define USB0_OTGCTL                              USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT                               USB_ISTAT_REG(USB0)
+#define USB0_INTEN                               USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT                             USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN                               USB_ERREN_REG(USB0)
+#define USB0_STAT                                USB_STAT_REG(USB0)
+#define USB0_CTL                                 USB_CTL_REG(USB0)
+#define USB0_ADDR                                USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1                            USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML                             USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH                             USB_FRMNUMH_REG(USB0)
+#define USB0_TOKEN                               USB_TOKEN_REG(USB0)
+#define USB0_SOFTHLD                             USB_SOFTHLD_REG(USB0)
+#define USB0_BDTPAGE2                            USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3                            USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0                              USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1                              USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2                              USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3                              USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4                              USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5                              USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6                              USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7                              USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8                              USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9                              USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10                             USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11                             USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12                             USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13                             USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14                             USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15                             USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL                             USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE                             USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL                             USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0                             USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST                        USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL                    USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN                  USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS              USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index)                        USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
+  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
+  __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
+  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
+  union {                                          /* offset: 0x18 */
+    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
+    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
+  };
+} USBDCD_Type, *USBDCD_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register accessors */
+#define USBDCD_CONTROL_REG(base)                 ((base)->CONTROL)
+#define USBDCD_CLOCK_REG(base)                   ((base)->CLOCK)
+#define USBDCD_STATUS_REG(base)                  ((base)->STATUS)
+#define USBDCD_TIMER0_REG(base)                  ((base)->TIMER0)
+#define USBDCD_TIMER1_REG(base)                  ((base)->TIMER1)
+#define USBDCD_TIMER2_BC11_REG(base)             ((base)->TIMER2_BC11)
+#define USBDCD_TIMER2_BC12_REG(base)             ((base)->TIMER2_BC12)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK                 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT                0
+#define USBDCD_CONTROL_IACK_WIDTH                1
+#define USBDCD_CONTROL_IACK(x)                   (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IACK_SHIFT))&USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IF_MASK                   0x100u
+#define USBDCD_CONTROL_IF_SHIFT                  8
+#define USBDCD_CONTROL_IF_WIDTH                  1
+#define USBDCD_CONTROL_IF(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IF_SHIFT))&USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IE_MASK                   0x10000u
+#define USBDCD_CONTROL_IE_SHIFT                  16
+#define USBDCD_CONTROL_IE_WIDTH                  1
+#define USBDCD_CONTROL_IE(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IE_SHIFT))&USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_BC12_MASK                 0x20000u
+#define USBDCD_CONTROL_BC12_SHIFT                17
+#define USBDCD_CONTROL_BC12_WIDTH                1
+#define USBDCD_CONTROL_BC12(x)                   (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_BC12_SHIFT))&USBDCD_CONTROL_BC12_MASK)
+#define USBDCD_CONTROL_START_MASK                0x1000000u
+#define USBDCD_CONTROL_START_SHIFT               24
+#define USBDCD_CONTROL_START_WIDTH               1
+#define USBDCD_CONTROL_START(x)                  (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_START_SHIFT))&USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_SR_MASK                   0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT                  25
+#define USBDCD_CONTROL_SR_WIDTH                  1
+#define USBDCD_CONTROL_SR(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_SR_SHIFT))&USBDCD_CONTROL_SR_MASK)
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK             0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            0
+#define USBDCD_CLOCK_CLOCK_UNIT_WIDTH            1
+#define USBDCD_CLOCK_CLOCK_UNIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_UNIT_SHIFT))&USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK            0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           2
+#define USBDCD_CLOCK_CLOCK_SPEED_WIDTH           10
+#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK               0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT              16
+#define USBDCD_STATUS_SEQ_RES_WIDTH              2
+#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK              0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT             18
+#define USBDCD_STATUS_SEQ_STAT_WIDTH             2
+#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK                   0x100000u
+#define USBDCD_STATUS_ERR_SHIFT                  20
+#define USBDCD_STATUS_ERR_WIDTH                  1
+#define USBDCD_STATUS_ERR(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ERR_SHIFT))&USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_TO_MASK                    0x200000u
+#define USBDCD_STATUS_TO_SHIFT                   21
+#define USBDCD_STATUS_TO_WIDTH                   1
+#define USBDCD_STATUS_TO(x)                      (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_TO_SHIFT))&USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_ACTIVE_MASK                0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT               22
+#define USBDCD_STATUS_ACTIVE_WIDTH               1
+#define USBDCD_STATUS_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ACTIVE_SHIFT))&USBDCD_STATUS_ACTIVE_MASK)
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK              0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT             0
+#define USBDCD_TIMER0_TUNITCON_WIDTH             12
+#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK             0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            16
+#define USBDCD_TIMER0_TSEQ_INIT_WIDTH            10
+#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK            0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           0
+#define USBDCD_TIMER1_TVDPSRC_ON_WIDTH           10
+#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK             0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            16
+#define USBDCD_TIMER1_TDCD_DBNC_WIDTH            10
+#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2_BC11 Bit Fields */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK         0xFu
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        0
+#define USBDCD_TIMER2_BC11_CHECK_DM_WIDTH        4
+#define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      0x3FF0000u
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     16
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_WIDTH     10
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+/* TIMER2_BC12 Bit Fields */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       0x3FFu
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      0
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_WIDTH      10
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  0x3FF0000u
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_WIDTH 10
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE                              (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD                                   ((USBDCD_Type *)USBDCD_BASE)
+#define USBDCD_BASE_PTR                          (USBDCD)
+/** Array initializer of USBDCD peripheral base addresses */
+#define USBDCD_BASE_ADDRS                        { USBDCD_BASE }
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASE_PTRS                         { USBDCD }
+/** Interrupt vectors for the USBDCD peripheral type */
+#define USBDCD_IRQS                              { USBDCD_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register instance definitions */
+/* USBDCD */
+#define USBDCD_CONTROL                           USBDCD_CONTROL_REG(USBDCD)
+#define USBDCD_CLOCK                             USBDCD_CLOCK_REG(USBDCD)
+#define USBDCD_STATUS                            USBDCD_STATUS_REG(USBDCD)
+#define USBDCD_TIMER0                            USBDCD_TIMER0_REG(USBDCD)
+#define USBDCD_TIMER1                            USBDCD_TIMER1_REG(USBDCD)
+#define USBDCD_TIMER2_BC11                       USBDCD_TIMER2_BC11_REG(USBDCD)
+#define USBDCD_TIMER2_BC12                       USBDCD_TIMER2_BC12_REG(USBDCD)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base)                       ((base)->TRM)
+#define VREF_SC_REG(base)                        ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK                       0x3Fu
+#define VREF_TRM_TRIM_SHIFT                      0
+#define VREF_TRM_TRIM_WIDTH                      6
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     0x40u
+#define VREF_TRM_CHOPEN_SHIFT                    6
+#define VREF_TRM_CHOPEN_WIDTH                    1
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_TRM_CHOPEN_SHIFT))&VREF_TRM_CHOPEN_MASK)
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK                     0x3u
+#define VREF_SC_MODE_LV_SHIFT                    0
+#define VREF_SC_MODE_LV_WIDTH                    2
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      0x4u
+#define VREF_SC_VREFST_SHIFT                     2
+#define VREF_SC_VREFST_WIDTH                     1
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFST_SHIFT))&VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK                     0x20u
+#define VREF_SC_ICOMPEN_SHIFT                    5
+#define VREF_SC_ICOMPEN_WIDTH                    1
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_ICOMPEN_SHIFT))&VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK                       0x40u
+#define VREF_SC_REGEN_SHIFT                      6
+#define VREF_SC_REGEN_WIDTH                      1
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_SC_REGEN_SHIFT))&VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK                      0x80u
+#define VREF_SC_VREFEN_SHIFT                     7
+#define VREF_SC_VREFEN_WIDTH                     1
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFEN_SHIFT))&VREF_SC_VREFEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR                            (VREF)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM                                 VREF_TRM_REG(VREF)
+#define VREF_SC                                  VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t STCTRLH;                           /**< Watchdog Status and Control Register High, offset: 0x0 */
+  __IO uint16_t STCTRLL;                           /**< Watchdog Status and Control Register Low, offset: 0x2 */
+  __IO uint16_t TOVALH;                            /**< Watchdog Time-out Value Register High, offset: 0x4 */
+  __IO uint16_t TOVALL;                            /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+  __IO uint16_t WINH;                              /**< Watchdog Window Register High, offset: 0x8 */
+  __IO uint16_t WINL;                              /**< Watchdog Window Register Low, offset: 0xA */
+  __IO uint16_t REFRESH;                           /**< Watchdog Refresh register, offset: 0xC */
+  __IO uint16_t UNLOCK;                            /**< Watchdog Unlock register, offset: 0xE */
+  __IO uint16_t TMROUTH;                           /**< Watchdog Timer Output Register High, offset: 0x10 */
+  __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
+  __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
+  __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type, *WDOG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register accessors */
+#define WDOG_STCTRLH_REG(base)                   ((base)->STCTRLH)
+#define WDOG_STCTRLL_REG(base)                   ((base)->STCTRLL)
+#define WDOG_TOVALH_REG(base)                    ((base)->TOVALH)
+#define WDOG_TOVALL_REG(base)                    ((base)->TOVALL)
+#define WDOG_WINH_REG(base)                      ((base)->WINH)
+#define WDOG_WINL_REG(base)                      ((base)->WINL)
+#define WDOG_REFRESH_REG(base)                   ((base)->REFRESH)
+#define WDOG_UNLOCK_REG(base)                    ((base)->UNLOCK)
+#define WDOG_TMROUTH_REG(base)                   ((base)->TMROUTH)
+#define WDOG_TMROUTL_REG(base)                   ((base)->TMROUTL)
+#define WDOG_RSTCNT_REG(base)                    ((base)->RSTCNT)
+#define WDOG_PRESC_REG(base)                     ((base)->PRESC)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK                 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT                0
+#define WDOG_STCTRLH_WDOGEN_WIDTH                1
+#define WDOG_STCTRLH_WDOGEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WDOGEN_SHIFT))&WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK                 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT                1
+#define WDOG_STCTRLH_CLKSRC_WIDTH                1
+#define WDOG_STCTRLH_CLKSRC(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_CLKSRC_SHIFT))&WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK               0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT              2
+#define WDOG_STCTRLH_IRQRSTEN_WIDTH              1
+#define WDOG_STCTRLH_IRQRSTEN(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_IRQRSTEN_SHIFT))&WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK                  0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT                 3
+#define WDOG_STCTRLH_WINEN_WIDTH                 1
+#define WDOG_STCTRLH_WINEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WINEN_SHIFT))&WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK            0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           4
+#define WDOG_STCTRLH_ALLOWUPDATE_WIDTH           1
+#define WDOG_STCTRLH_ALLOWUPDATE(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_ALLOWUPDATE_SHIFT))&WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK                  0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT                 5
+#define WDOG_STCTRLH_DBGEN_WIDTH                 1
+#define WDOG_STCTRLH_DBGEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DBGEN_SHIFT))&WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK                 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT                6
+#define WDOG_STCTRLH_STOPEN_WIDTH                1
+#define WDOG_STCTRLH_STOPEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_STOPEN_SHIFT))&WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK                 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT                7
+#define WDOG_STCTRLH_WAITEN_WIDTH                1
+#define WDOG_STCTRLH_WAITEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WAITEN_SHIFT))&WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK               0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT              10
+#define WDOG_STCTRLH_TESTWDOG_WIDTH              1
+#define WDOG_STCTRLH_TESTWDOG(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTWDOG_SHIFT))&WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK                0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT               11
+#define WDOG_STCTRLH_TESTSEL_WIDTH               1
+#define WDOG_STCTRLH_TESTSEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTSEL_SHIFT))&WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK                0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT               12
+#define WDOG_STCTRLH_BYTESEL_WIDTH               2
+#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK            0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT           14
+#define WDOG_STCTRLH_DISTESTWDOG_WIDTH           1
+#define WDOG_STCTRLH_DISTESTWDOG(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DISTESTWDOG_SHIFT))&WDOG_STCTRLH_DISTESTWDOG_MASK)
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK                 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT                15
+#define WDOG_STCTRLL_INTFLG_WIDTH                1
+#define WDOG_STCTRLL_INTFLG(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLL_INTFLG_SHIFT))&WDOG_STCTRLL_INTFLG_MASK)
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK               0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              0
+#define WDOG_TOVALH_TOVALHIGH_WIDTH              16
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK                0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT               0
+#define WDOG_TOVALL_TOVALLOW_WIDTH               16
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK                   0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT                  0
+#define WDOG_WINH_WINHIGH_WIDTH                  16
+#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK                    0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT                   0
+#define WDOG_WINL_WINLOW_WIDTH                   16
+#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK            0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT           0
+#define WDOG_REFRESH_WDOGREFRESH_WIDTH           16
+#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK              0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             0
+#define WDOG_UNLOCK_WDOGUNLOCK_WIDTH             16
+#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK           0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          0
+#define WDOG_TMROUTH_TIMEROUTHIGH_WIDTH          16
+#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK            0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           0
+#define WDOG_TMROUTL_TIMEROUTLOW_WIDTH           16
+#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK                  0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT                 0
+#define WDOG_RSTCNT_RSTCNT_WIDTH                 16
+#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK                 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT                8
+#define WDOG_PRESC_PRESCVAL_WIDTH                3
+#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+#define WDOG_BASE_PTR                            (WDOG)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS                          { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS                           { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS                                { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register instance definitions */
+/* WDOG */
+#define WDOG_STCTRLH                             WDOG_STCTRLH_REG(WDOG)
+#define WDOG_STCTRLL                             WDOG_STCTRLL_REG(WDOG)
+#define WDOG_TOVALH                              WDOG_TOVALH_REG(WDOG)
+#define WDOG_TOVALL                              WDOG_TOVALL_REG(WDOG)
+#define WDOG_WINH                                WDOG_WINH_REG(WDOG)
+#define WDOG_WINL                                WDOG_WINL_REG(WDOG)
+#define WDOG_REFRESH                             WDOG_REFRESH_REG(WDOG)
+#define WDOG_UNLOCK                              WDOG_UNLOCK_REG(WDOG)
+#define WDOG_TMROUTH                             WDOG_TMROUTH_REG(WDOG)
+#define WDOG_TMROUTL                             WDOG_TMROUTL_REG(WDOG)
+#define WDOG_RSTCNT                              WDOG_RSTCNT_REG(WDOG)
+#define WDOG_PRESC                               WDOG_PRESC_REG(WDOG)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Backward Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define DMA_EARS_REG(base)                       This_symbol_has_been_deprecated
+#define DMA_EARS                                 This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_SHIFT                  This_symbol_has_been_deprecated
+#define ENET_RMON_T_DROP_REG(base)               This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP_REG(base)               This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE_REG(base)                This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0_REG(base)            This_symbol_has_been_deprecated
+#define ENET_RMON_R_DROP_REG(base)               ENET_IEEE_R_DROP_REG(base)
+#define ENET_RMON_R_FRAME_OK_REG(base)           ENET_IEEE_R_FRAME_OK_REG(base)
+#define ENET_RMON_T_DROP                         This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP                         This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE                          This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0                      This_symbol_has_been_deprecated
+#define MCG_C9_REG(base)                         This_symbol_has_been_deprecated
+#define MCG_C2_EREFS0_MASK                       MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT                      MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK                         MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT                        MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK                       MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT                      MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x)                         MCG_C2_RANGE(x)
+#define MCG_C9                                   This_symbol_has_been_deprecated
+#define MCM_PLACR_REG(base)                      This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_MASK                       This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_SHIFT                      This_symbol_has_been_deprecated
+#define MCM_PLACR                                This_symbol_has_been_deprecated
+#define ADC_BASES                    ADC_BASE_PTRS
+#define AIPS_BASES                   AIPS_BASE_PTRS
+#define AXBS_BASES                   AXBS_BASE_PTRS
+#define CAN_BASES                    CAN_BASE_PTRS
+#define CAU_BASES                    CAU_BASE_PTRS
+#define CMP_BASES                    CMP_BASE_PTRS
+#define CMT_BASES                    CMT_BASE_PTRS
+#define CRC_BASES                    CRC_BASE_PTRS
+#define DAC_BASES                    DAC_BASE_PTRS
+#define DMA_BASES                    DMA_BASE_PTRS
+#define DMAMUX_BASES                 DMAMUX_BASE_PTRS
+#define ENET_BASES                   ENET_BASE_PTRS
+#define EWM_BASES                    EWM_BASE_PTRS
+#define FB_BASES                     FB_BASE_PTRS
+#define FMC_BASES                    FMC_BASE_PTRS
+#define FTFE_BASES                   FTFE_BASE_PTRS
+#define FTM_BASES                    FTM_BASE_PTRS
+#define GPIO_BASES                   GPIO_BASE_PTRS
+#define I2C_BASES                    I2C_BASE_PTRS
+#define I2S_BASES                    I2S_BASE_PTRS
+#define LLWU_BASES                   LLWU_BASE_PTRS
+#define LPTMR_BASES                  LPTMR_BASE_PTRS
+#define MCG_BASES                    MCG_BASE_PTRS
+#define MCM_ISR_REG(base)            MCM_ISCR_REG(base)
+#define MCM_ISR_FIOC_MASK            MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT           MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK            MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT           MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK            MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT           MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK            MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT           MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK            MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT           MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK            MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT           MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK           MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT          MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK           MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT          MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK           MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT          MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK           MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT          MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK           MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT          MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK           MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT          MCM_ISCR_FIDCE_SHIFT
+#define MCM_BASES                    MCM_BASE_PTRS
+#define MPU_BASES                    MPU_BASE_PTRS
+#define NV_BASES                     NV_BASE_PTRS
+#define OSC_BASES                    OSC_BASE_PTRS
+#define PDB_BASES                    PDB_BASE_PTRS
+#define PIT_BASES                    PIT_BASE_PTRS
+#define PMC_BASES                    PMC_BASE_PTRS
+#define PORT_BASES                   PORT_BASE_PTRS
+#define RCM_BASES                    RCM_BASE_PTRS
+#define RFSYS_BASES                  RFSYS_BASE_PTRS
+#define RFVBAT_BASES                 RFVBAT_BASE_PTRS
+#define RNG_BASES                    RNG_BASE_PTRS
+#define RTC_BASES                    RTC_BASE_PTRS
+#define SDHC_BASES                   SDHC_BASE_PTRS
+#define SIM_BASES                    SIM_BASE_PTRS
+#define SMC_BASES                    SMC_BASE_PTRS
+#define SPI_BASES                    SPI_BASE_PTRS
+#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
+#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
+#define UART_WP7816_T_TYPE0_WI_MASK  UART_WP7816T0_WI_MASK
+#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
+#define UART_WP7816_T_TYPE0_WI(x)    UART_WP7816T0_WI(x)
+#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
+#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
+#define UART_WP7816_T_TYPE1_BWI(x)   UART_WP7816T1_BWI(x)
+#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
+#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
+#define UART_WP7816_T_TYPE1_CWI(x)   UART_WP7816T1_CWI(x)
+#define UART_BASES                   UART_BASE_PTRS
+#define USB_BASES                    USB_BASE_PTRS
+#define USBDCD_BASES                 USBDCD_BASE_PTRS
+#define VREF_BASES                   VREF_BASE_PTRS
+#define WDOG_BASES                   WDOG_BASE_PTRS
+#define Watchdog_IRQn                WDOG_EWM_IRQn
+#define Watchdog_IRQHandler          WDOG_EWM_IRQHandler
+#define LPTimer_IRQn                 LPTMR0_IRQn
+#define LPTimer_IRQHandler           LPTMR0_IRQHandler
+#define LLW_IRQn                     LLWU_IRQn
+#define LLW_IRQHandler               LLWU_IRQHandler
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MK64F12_H_) */
+  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+  #if (MCU_MEM_MAP_VERSION != 0x0200u)
+    #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+      #warning There are included two not compatible versions of memory maps. Please check possible differences.
+    #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+  #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
+#endif  /* #if !defined(MK64F12_H_) */
+
+/* MK64F12.h, eof. */
diff --git a/Workspace/ADC/SDK/platform/devices/MK64F12/include/MK64F12_extension.h b/Workspace/ADC/SDK/platform/devices/MK64F12/include/MK64F12_extension.h
new file mode 100644
index 0000000..c47b6c4
--- /dev/null
+++ b/Workspace/ADC/SDK/platform/devices/MK64F12/include/MK64F12_extension.h
@@ -0,0 +1,63846 @@
+/*
+** ###################################################################
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150612
+**
+**     Abstract:
+**         Extension to the CMSIS register access layer header.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __MK64F12_EXTENSION_H__
+#define __MK64F12_EXTENSION_H__
+
+#include "MK64F12.h"
+#include "fsl_bitaccess.h"
+
+#if defined(__IAR_SYSTEMS_ICC__)
+  /*
+   * Suppress "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)"
+   * as some register descriptions contain code examples
+   */
+  #pragma diag_suppress=pm008
+#endif
+
+/*
+ * MK64F12 ADC
+ *
+ * Analog-to-Digital Converter
+ *
+ * Registers defined in this header file:
+ * - ADC_SC1 - ADC Status and Control Registers 1
+ * - ADC_CFG1 - ADC Configuration Register 1
+ * - ADC_CFG2 - ADC Configuration Register 2
+ * - ADC_R - ADC Data Result Register
+ * - ADC_CV1 - Compare Value Registers
+ * - ADC_CV2 - Compare Value Registers
+ * - ADC_SC2 - Status and Control Register 2
+ * - ADC_SC3 - Status and Control Register 3
+ * - ADC_OFS - ADC Offset Correction Register
+ * - ADC_PG - ADC Plus-Side Gain Register
+ * - ADC_MG - ADC Minus-Side Gain Register
+ * - ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ */
+
+#define ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
+#define ADC0_IDX (0U) /*!< Instance number for ADC0. */
+#define ADC1_IDX (1U) /*!< Instance number for ADC1. */
+
+/*******************************************************************************
+ * ADC_SC1 - ADC Status and Control Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC1 - ADC Status and Control Registers 1 (RW)
+ *
+ * Reset value: 0x0000001FU
+ *
+ * SC1A is used for both software and hardware trigger modes of operation. To
+ * allow sequential conversions of the ADC to be triggered by internal peripherals,
+ * the ADC can have more than one status and control register: one for each
+ * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
+ * for use only in hardware trigger mode. See the chip configuration information
+ * about the number of SC1n registers specific to this device. The SC1n registers
+ * have identical fields, and are used in a "ping-pong" approach to control ADC
+ * operation. At any one point in time, only one of the SC1n registers is actively
+ * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
+ * a conversion is allowed, and vice-versa for any of the SC1n registers specific
+ * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
+ * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
+ * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
+ * value other than all 1s. Writing any of the SC1n registers while that specific
+ * SC1n register is actively controlling a conversion aborts the current conversion.
+ * None of the SC1B-SC1n registers are used for software trigger operation and
+ * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC1 register
+ */
+/*@{*/
+#define ADC_RD_SC1(base, index)  (ADC_SC1_REG(base, index))
+#define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value))
+#define ADC_RMW_SC1(base, index, mask, value) (ADC_WR_SC1(base, index, (ADC_RD_SC1(base, index) & ~(mask)) | (value)))
+#define ADC_SET_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) |  (value)))
+#define ADC_CLR_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) & ~(value)))
+#define ADC_TOG_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC1 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC1, field ADCH[4:0] (RW)
+ *
+ * Selects one of the input channels. The input channel decode depends on the
+ * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
+ * DADMx. Some of the input channel options in the bitfield-setting descriptions might
+ * not be available for your device. For the actual ADC channel assignments for
+ * your device, see the Chip Configuration details. The successive approximation
+ * converter subsystem is turned off when the channel select bits are all set,
+ * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
+ * isolation of the input channel from all sources. Terminating continuous
+ * conversions this way prevents an additional single conversion from being performed. It
+ * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
+ * when continuous conversions are not enabled because the module automatically
+ * enters a low-power state when a conversion completes.
+ *
+ * Values:
+ * - 0b00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
+ *     selected as input.
+ * - 0b00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
+ *     selected as input.
+ * - 0b00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
+ *     selected as input.
+ * - 0b00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
+ *     selected as input.
+ * - 0b00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b11000 - Reserved.
+ * - 0b11001 - Reserved.
+ * - 0b11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input;
+ *     when DIFF=1, Temp Sensor (differential) is selected as input.
+ * - 0b11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
+ *     DIFF=1, Bandgap (differential) is selected as input.
+ * - 0b11100 - Reserved.
+ * - 0b11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
+ *     (differential) is selected as input. Voltage reference selected is determined
+ *     by SC2[REFSEL].
+ * - 0b11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
+ *     reserved. Voltage reference selected is determined by SC2[REFSEL].
+ * - 0b11111 - Module is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_ADCH field. */
+#define ADC_RD_SC1_ADCH(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_ADCH_MASK) >> ADC_SC1_ADCH_SHIFT)
+#define ADC_BRD_SC1_ADCH(base, index) (ADC_RD_SC1_ADCH(base, index))
+
+/*! @brief Set the ADCH field to a new value. */
+#define ADC_WR_SC1_ADCH(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_ADCH_MASK, ADC_SC1_ADCH(value)))
+#define ADC_BWR_SC1_ADCH(base, index, value) (ADC_WR_SC1_ADCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field DIFF[5] (RW)
+ *
+ * Configures the ADC to operate in differential mode. When enabled, this mode
+ * automatically selects from the differential channels, and changes the
+ * conversion algorithm and the number of cycles to complete a conversion.
+ *
+ * Values:
+ * - 0b0 - Single-ended conversions and input channels are selected.
+ * - 0b1 - Differential conversions and input channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_DIFF field. */
+#define ADC_RD_SC1_DIFF(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_DIFF_MASK) >> ADC_SC1_DIFF_SHIFT)
+#define ADC_BRD_SC1_DIFF(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT))
+
+/*! @brief Set the DIFF field to a new value. */
+#define ADC_WR_SC1_DIFF(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_DIFF_MASK, ADC_SC1_DIFF(value)))
+#define ADC_BWR_SC1_DIFF(base, index, value) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field AIEN[6] (RW)
+ *
+ * Enables conversion complete interrupts. When COCO becomes set while the
+ * respective AIEN is high, an interrupt is asserted.
+ *
+ * Values:
+ * - 0b0 - Conversion complete interrupt is disabled.
+ * - 0b1 - Conversion complete interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_AIEN field. */
+#define ADC_RD_SC1_AIEN(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIEN_SHIFT)
+#define ADC_BRD_SC1_AIEN(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT))
+
+/*! @brief Set the AIEN field to a new value. */
+#define ADC_WR_SC1_AIEN(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_AIEN_MASK, ADC_SC1_AIEN(value)))
+#define ADC_BWR_SC1_AIEN(base, index, value) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field COCO[7] (RO)
+ *
+ * This is a read-only field that is set each time a conversion is completed
+ * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
+ * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
+ * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
+ * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
+ * COCO is set upon completion of the selected number of conversions (determined
+ * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
+ * COCO is cleared when the respective SC1n register is written or when the
+ * respective Rn register is read.
+ *
+ * Values:
+ * - 0b0 - Conversion is not completed.
+ * - 0b1 - Conversion is completed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_COCO field. */
+#define ADC_RD_SC1_COCO(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_COCO_MASK) >> ADC_SC1_COCO_SHIFT)
+#define ADC_BRD_SC1_COCO(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG1 - ADC Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG1 - ADC Configuration Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The configuration Register 1 (CFG1) selects the mode of operation, clock
+ * source, clock divide, and configuration for low power or long sample time.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG1 register
+ */
+/*@{*/
+#define ADC_RD_CFG1(base)        (ADC_CFG1_REG(base))
+#define ADC_WR_CFG1(base, value) (ADC_CFG1_REG(base) = (value))
+#define ADC_RMW_CFG1(base, mask, value) (ADC_WR_CFG1(base, (ADC_RD_CFG1(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) |  (value)))
+#define ADC_CLR_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) & ~(value)))
+#define ADC_TOG_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
+ *
+ * Selects the input clock source to generate the internal clock, ADCK. Note
+ * that when the ADACK clock source is selected, it is not required to be active
+ * prior to conversion start. When it is selected and it is not active prior to a
+ * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
+ * the start of a conversion and deactivated when conversions are terminated. In
+ * this case, there is an associated clock startup delay each time the clock
+ * source is re-activated.
+ *
+ * Values:
+ * - 0b00 - Bus clock
+ * - 0b01 - Alternate clock 2 (ALTCLK2)
+ * - 0b10 - Alternate clock (ALTCLK)
+ * - 0b11 - Asynchronous clock (ADACK)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADICLK field. */
+#define ADC_RD_CFG1_ADICLK(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADICLK_MASK) >> ADC_CFG1_ADICLK_SHIFT)
+#define ADC_BRD_CFG1_ADICLK(base) (ADC_RD_CFG1_ADICLK(base))
+
+/*! @brief Set the ADICLK field to a new value. */
+#define ADC_WR_CFG1_ADICLK(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADICLK_MASK, ADC_CFG1_ADICLK(value)))
+#define ADC_BWR_CFG1_ADICLK(base, value) (ADC_WR_CFG1_ADICLK(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field MODE[3:2] (RW)
+ *
+ * Selects the ADC resolution mode.
+ *
+ * Values:
+ * - 0b00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
+ *     differential 9-bit conversion with 2's complement output.
+ * - 0b01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it
+ *     is differential 13-bit conversion with 2's complement output.
+ * - 0b10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it
+ *     is differential 11-bit conversion with 2's complement output
+ * - 0b11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it
+ *     is differential 16-bit conversion with 2's complement output
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_MODE field. */
+#define ADC_RD_CFG1_MODE(base) ((ADC_CFG1_REG(base) & ADC_CFG1_MODE_MASK) >> ADC_CFG1_MODE_SHIFT)
+#define ADC_BRD_CFG1_MODE(base) (ADC_RD_CFG1_MODE(base))
+
+/*! @brief Set the MODE field to a new value. */
+#define ADC_WR_CFG1_MODE(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_MODE_MASK, ADC_CFG1_MODE(value)))
+#define ADC_BWR_CFG1_MODE(base, value) (ADC_WR_CFG1_MODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLSMP[4] (RW)
+ *
+ * Selects between different sample times based on the conversion mode selected.
+ * This field adjusts the sample period to allow higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption if
+ * continuous conversions are enabled and high conversion rates are not required.
+ * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
+ * extent of the long sample time.
+ *
+ * Values:
+ * - 0b0 - Short sample time.
+ * - 0b1 - Long sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
+#define ADC_RD_CFG1_ADLSMP(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLSMP_MASK) >> ADC_CFG1_ADLSMP_SHIFT)
+#define ADC_BRD_CFG1_ADLSMP(base) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT))
+
+/*! @brief Set the ADLSMP field to a new value. */
+#define ADC_WR_CFG1_ADLSMP(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLSMP_MASK, ADC_CFG1_ADLSMP(value)))
+#define ADC_BWR_CFG1_ADLSMP(base, value) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADIV[6:5] (RW)
+ *
+ * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
+ *
+ * Values:
+ * - 0b00 - The divide ratio is 1 and the clock rate is input clock.
+ * - 0b01 - The divide ratio is 2 and the clock rate is (input clock)/2.
+ * - 0b10 - The divide ratio is 4 and the clock rate is (input clock)/4.
+ * - 0b11 - The divide ratio is 8 and the clock rate is (input clock)/8.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADIV field. */
+#define ADC_RD_CFG1_ADIV(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT)
+#define ADC_BRD_CFG1_ADIV(base) (ADC_RD_CFG1_ADIV(base))
+
+/*! @brief Set the ADIV field to a new value. */
+#define ADC_WR_CFG1_ADIV(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADIV_MASK, ADC_CFG1_ADIV(value)))
+#define ADC_BWR_CFG1_ADIV(base, value) (ADC_WR_CFG1_ADIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLPC[7] (RW)
+ *
+ * Controls the power configuration of the successive approximation converter.
+ * This optimizes power consumption when higher sample rates are not required.
+ *
+ * Values:
+ * - 0b0 - Normal power configuration.
+ * - 0b1 - Low-power configuration. The power is reduced at the expense of
+ *     maximum clock speed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLPC field. */
+#define ADC_RD_CFG1_ADLPC(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLPC_MASK) >> ADC_CFG1_ADLPC_SHIFT)
+#define ADC_BRD_CFG1_ADLPC(base) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT))
+
+/*! @brief Set the ADLPC field to a new value. */
+#define ADC_WR_CFG1_ADLPC(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLPC_MASK, ADC_CFG1_ADLPC(value)))
+#define ADC_BWR_CFG1_ADLPC(base, value) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG2 - ADC Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG2 - ADC Configuration Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Configuration Register 2 (CFG2) selects the special high-speed configuration
+ * for very high speed conversions and selects the long sample time duration
+ * during long sample mode.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG2 register
+ */
+/*@{*/
+#define ADC_RD_CFG2(base)        (ADC_CFG2_REG(base))
+#define ADC_WR_CFG2(base, value) (ADC_CFG2_REG(base) = (value))
+#define ADC_RMW_CFG2(base, mask, value) (ADC_WR_CFG2(base, (ADC_RD_CFG2(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) |  (value)))
+#define ADC_CLR_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) & ~(value)))
+#define ADC_TOG_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
+ *
+ * Selects between the extended sample times when long sample time is selected,
+ * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption when
+ * continuous conversions are enabled if high conversion rates are not required.
+ *
+ * Values:
+ * - 0b00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
+ *     total.
+ * - 0b01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
+ * - 0b10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
+ * - 0b11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
+#define ADC_RD_CFG2_ADLSTS(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADLSTS_MASK) >> ADC_CFG2_ADLSTS_SHIFT)
+#define ADC_BRD_CFG2_ADLSTS(base) (ADC_RD_CFG2_ADLSTS(base))
+
+/*! @brief Set the ADLSTS field to a new value. */
+#define ADC_WR_CFG2_ADLSTS(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADLSTS_MASK, ADC_CFG2_ADLSTS(value)))
+#define ADC_BWR_CFG2_ADLSTS(base, value) (ADC_WR_CFG2_ADLSTS(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADHSC[2] (RW)
+ *
+ * Configures the ADC for very high-speed operation. The conversion sequence is
+ * altered with 2 ADCK cycles added to the conversion time to allow higher speed
+ * conversion clocks.
+ *
+ * Values:
+ * - 0b0 - Normal conversion sequence selected.
+ * - 0b1 - High-speed conversion sequence selected with 2 additional ADCK cycles
+ *     to total conversion time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADHSC field. */
+#define ADC_RD_CFG2_ADHSC(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADHSC_MASK) >> ADC_CFG2_ADHSC_SHIFT)
+#define ADC_BRD_CFG2_ADHSC(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT))
+
+/*! @brief Set the ADHSC field to a new value. */
+#define ADC_WR_CFG2_ADHSC(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADHSC_MASK, ADC_CFG2_ADHSC(value)))
+#define ADC_BWR_CFG2_ADHSC(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADACKEN[3] (RW)
+ *
+ * Enables the asynchronous clock source and the clock source output regardless
+ * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
+ * asynchronous clock may be used by other modules. See chip configuration
+ * information. Setting this field allows the clock to be used even while the ADC is
+ * idle or operating from a different clock source. Also, latency of initiating a
+ * single or first-continuous conversion with the asynchronous clock selected is
+ * reduced because the ADACK clock is already operational.
+ *
+ * Values:
+ * - 0b0 - Asynchronous clock output disabled; Asynchronous clock is enabled
+ *     only if selected by ADICLK and a conversion is active.
+ * - 0b1 - Asynchronous clock and clock output is enabled regardless of the
+ *     state of the ADC.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
+#define ADC_RD_CFG2_ADACKEN(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADACKEN_MASK) >> ADC_CFG2_ADACKEN_SHIFT)
+#define ADC_BRD_CFG2_ADACKEN(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT))
+
+/*! @brief Set the ADACKEN field to a new value. */
+#define ADC_WR_CFG2_ADACKEN(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADACKEN_MASK, ADC_CFG2_ADACKEN(value)))
+#define ADC_BWR_CFG2_ADACKEN(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field MUXSEL[4] (RW)
+ *
+ * Changes the ADC mux setting to select between alternate sets of ADC channels.
+ *
+ * Values:
+ * - 0b0 - ADxxa channels are selected.
+ * - 0b1 - ADxxb channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
+#define ADC_RD_CFG2_MUXSEL(base) ((ADC_CFG2_REG(base) & ADC_CFG2_MUXSEL_MASK) >> ADC_CFG2_MUXSEL_SHIFT)
+#define ADC_BRD_CFG2_MUXSEL(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT))
+
+/*! @brief Set the MUXSEL field to a new value. */
+#define ADC_WR_CFG2_MUXSEL(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_MUXSEL_MASK, ADC_CFG2_MUXSEL(value)))
+#define ADC_BWR_CFG2_MUXSEL(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_R - ADC Data Result Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_R - ADC Data Result Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The data result registers (Rn) contain the result of an ADC conversion of the
+ * channel selected by the corresponding status and channel control register
+ * (SC1A:SC1n). For every status and channel control register, there is a
+ * corresponding data result register. Unused bits in R n are cleared in unsigned
+ * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
+ * For example, when configured for 10-bit single-ended mode, D[15:10] are
+ * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
+ * that is, bit 10 extended through bit 15. The following table describes the
+ * behavior of the data result registers in the different modes of operation. Data
+ * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
+ * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
+ * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
+ * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
+ * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
+ * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
+ * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
+ * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
+ * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
+ * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
+ * 2's complement data if indicated
+ */
+/*!
+ * @name Constants and macros for entire ADC_R register
+ */
+/*@{*/
+#define ADC_RD_R(base, index)    (ADC_R_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_R bitfields
+ */
+
+/*!
+ * @name Register ADC_R, field D[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_R_D field. */
+#define ADC_RD_R_D(base, index) ((ADC_R_REG(base, index) & ADC_R_D_MASK) >> ADC_R_D_SHIFT)
+#define ADC_BRD_R_D(base, index) (ADC_RD_R_D(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV1 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV1 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV1 register
+ */
+/*@{*/
+#define ADC_RD_CV1(base)         (ADC_CV1_REG(base))
+#define ADC_WR_CV1(base, value)  (ADC_CV1_REG(base) = (value))
+#define ADC_RMW_CV1(base, mask, value) (ADC_WR_CV1(base, (ADC_RD_CV1(base) & ~(mask)) | (value)))
+#define ADC_SET_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) |  (value)))
+#define ADC_CLR_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) & ~(value)))
+#define ADC_TOG_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV1, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV1_CV field. */
+#define ADC_RD_CV1_CV(base)  ((ADC_CV1_REG(base) & ADC_CV1_CV_MASK) >> ADC_CV1_CV_SHIFT)
+#define ADC_BRD_CV1_CV(base) (ADC_RD_CV1_CV(base))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV1_CV(base, value) (ADC_RMW_CV1(base, ADC_CV1_CV_MASK, ADC_CV1_CV(value)))
+#define ADC_BWR_CV1_CV(base, value) (ADC_WR_CV1_CV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV2 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV2 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV2 register
+ */
+/*@{*/
+#define ADC_RD_CV2(base)         (ADC_CV2_REG(base))
+#define ADC_WR_CV2(base, value)  (ADC_CV2_REG(base) = (value))
+#define ADC_RMW_CV2(base, mask, value) (ADC_WR_CV2(base, (ADC_RD_CV2(base) & ~(mask)) | (value)))
+#define ADC_SET_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) |  (value)))
+#define ADC_CLR_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) & ~(value)))
+#define ADC_TOG_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV2, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV2_CV field. */
+#define ADC_RD_CV2_CV(base)  ((ADC_CV2_REG(base) & ADC_CV2_CV_MASK) >> ADC_CV2_CV_SHIFT)
+#define ADC_BRD_CV2_CV(base) (ADC_RD_CV2_CV(base))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV2_CV(base, value) (ADC_RMW_CV2(base, ADC_CV2_CV_MASK, ADC_CV2_CV(value)))
+#define ADC_BWR_CV2_CV(base, value) (ADC_WR_CV2_CV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC2 - Status and Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC2 - Status and Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The status and control register 2 (SC2) contains the conversion active,
+ * hardware/software trigger select, compare function, and voltage reference select of
+ * the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC2 register
+ */
+/*@{*/
+#define ADC_RD_SC2(base)         (ADC_SC2_REG(base))
+#define ADC_WR_SC2(base, value)  (ADC_SC2_REG(base) = (value))
+#define ADC_RMW_SC2(base, mask, value) (ADC_WR_SC2(base, (ADC_RD_SC2(base) & ~(mask)) | (value)))
+#define ADC_SET_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) |  (value)))
+#define ADC_CLR_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) & ~(value)))
+#define ADC_TOG_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC2 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC2, field REFSEL[1:0] (RW)
+ *
+ * Selects the voltage reference source used for conversions.
+ *
+ * Values:
+ * - 0b00 - Default voltage reference pin pair, that is, external pins VREFH and
+ *     VREFL
+ * - 0b01 - Alternate reference pair, that is, VALTH and VALTL . This pair may
+ *     be additional external pins or internal sources depending on the MCU
+ *     configuration. See the chip configuration information for details specific to
+ *     this MCU
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_REFSEL field. */
+#define ADC_RD_SC2_REFSEL(base) ((ADC_SC2_REG(base) & ADC_SC2_REFSEL_MASK) >> ADC_SC2_REFSEL_SHIFT)
+#define ADC_BRD_SC2_REFSEL(base) (ADC_RD_SC2_REFSEL(base))
+
+/*! @brief Set the REFSEL field to a new value. */
+#define ADC_WR_SC2_REFSEL(base, value) (ADC_RMW_SC2(base, ADC_SC2_REFSEL_MASK, ADC_SC2_REFSEL(value)))
+#define ADC_BWR_SC2_REFSEL(base, value) (ADC_WR_SC2_REFSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field DMAEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled and will assert the ADC DMA request during an ADC
+ *     conversion complete event noted when any of the SC1n[COCO] flags is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_DMAEN field. */
+#define ADC_RD_SC2_DMAEN(base) ((ADC_SC2_REG(base) & ADC_SC2_DMAEN_MASK) >> ADC_SC2_DMAEN_SHIFT)
+#define ADC_BRD_SC2_DMAEN(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define ADC_WR_SC2_DMAEN(base, value) (ADC_RMW_SC2(base, ADC_SC2_DMAEN_MASK, ADC_SC2_DMAEN(value)))
+#define ADC_BWR_SC2_DMAEN(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACREN[3] (RW)
+ *
+ * Configures the compare function to check if the conversion result of the
+ * input being monitored is either between or outside the range formed by CV1 and CV2
+ * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
+ * effect.
+ *
+ * Values:
+ * - 0b0 - Range function disabled. Only CV1 is compared.
+ * - 0b1 - Range function enabled. Both CV1 and CV2 are compared.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACREN field. */
+#define ADC_RD_SC2_ACREN(base) ((ADC_SC2_REG(base) & ADC_SC2_ACREN_MASK) >> ADC_SC2_ACREN_SHIFT)
+#define ADC_BRD_SC2_ACREN(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT))
+
+/*! @brief Set the ACREN field to a new value. */
+#define ADC_WR_SC2_ACREN(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACREN_MASK, ADC_SC2_ACREN(value)))
+#define ADC_BWR_SC2_ACREN(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFGT[4] (RW)
+ *
+ * Configures the compare function to check the conversion result relative to
+ * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
+ * have any effect.
+ *
+ * Values:
+ * - 0b0 - Configures less than threshold, outside range not inclusive and
+ *     inside range not inclusive; functionality based on the values placed in CV1 and
+ *     CV2.
+ * - 0b1 - Configures greater than or equal to threshold, outside and inside
+ *     ranges inclusive; functionality based on the values placed in CV1 and CV2.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFGT field. */
+#define ADC_RD_SC2_ACFGT(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFGT_MASK) >> ADC_SC2_ACFGT_SHIFT)
+#define ADC_BRD_SC2_ACFGT(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT))
+
+/*! @brief Set the ACFGT field to a new value. */
+#define ADC_WR_SC2_ACFGT(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFGT_MASK, ADC_SC2_ACFGT(value)))
+#define ADC_BWR_SC2_ACFGT(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFE[5] (RW)
+ *
+ * Enables the compare function.
+ *
+ * Values:
+ * - 0b0 - Compare function disabled.
+ * - 0b1 - Compare function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFE field. */
+#define ADC_RD_SC2_ACFE(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFE_MASK) >> ADC_SC2_ACFE_SHIFT)
+#define ADC_BRD_SC2_ACFE(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT))
+
+/*! @brief Set the ACFE field to a new value. */
+#define ADC_WR_SC2_ACFE(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFE_MASK, ADC_SC2_ACFE(value)))
+#define ADC_BWR_SC2_ACFE(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADTRG[6] (RW)
+ *
+ * Selects the type of trigger used for initiating a conversion. Two types of
+ * trigger are selectable: Software trigger: When software trigger is selected, a
+ * conversion is initiated following a write to SC1A. Hardware trigger: When
+ * hardware trigger is selected, a conversion is initiated following the assertion of
+ * the ADHWT input after a pulse of the ADHWTSn input.
+ *
+ * Values:
+ * - 0b0 - Software trigger selected.
+ * - 0b1 - Hardware trigger selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADTRG field. */
+#define ADC_RD_SC2_ADTRG(base) ((ADC_SC2_REG(base) & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT)
+#define ADC_BRD_SC2_ADTRG(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT))
+
+/*! @brief Set the ADTRG field to a new value. */
+#define ADC_WR_SC2_ADTRG(base, value) (ADC_RMW_SC2(base, ADC_SC2_ADTRG_MASK, ADC_SC2_ADTRG(value)))
+#define ADC_BWR_SC2_ADTRG(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADACT[7] (RO)
+ *
+ * Indicates that a conversion or hardware averaging is in progress. ADACT is
+ * set when a conversion is initiated and cleared when a conversion is completed or
+ * aborted.
+ *
+ * Values:
+ * - 0b0 - Conversion not in progress.
+ * - 0b1 - Conversion in progress.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADACT field. */
+#define ADC_RD_SC2_ADACT(base) ((ADC_SC2_REG(base) & ADC_SC2_ADACT_MASK) >> ADC_SC2_ADACT_SHIFT)
+#define ADC_BRD_SC2_ADACT(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADACT_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC3 - Status and Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC3 - Status and Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Status and Control Register 3 (SC3) controls the calibration, continuous
+ * convert, and hardware averaging functions of the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC3 register
+ */
+/*@{*/
+#define ADC_RD_SC3(base)         (ADC_SC3_REG(base))
+#define ADC_WR_SC3(base, value)  (ADC_SC3_REG(base) = (value))
+#define ADC_RMW_SC3(base, mask, value) (ADC_WR_SC3(base, (ADC_RD_SC3(base) & ~(mask)) | (value)))
+#define ADC_SET_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) |  (value)))
+#define ADC_CLR_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) & ~(value)))
+#define ADC_TOG_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC3 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC3, field AVGS[1:0] (RW)
+ *
+ * Determines how many ADC conversions will be averaged to create the ADC
+ * average result.
+ *
+ * Values:
+ * - 0b00 - 4 samples averaged.
+ * - 0b01 - 8 samples averaged.
+ * - 0b10 - 16 samples averaged.
+ * - 0b11 - 32 samples averaged.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGS field. */
+#define ADC_RD_SC3_AVGS(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGS_MASK) >> ADC_SC3_AVGS_SHIFT)
+#define ADC_BRD_SC3_AVGS(base) (ADC_RD_SC3_AVGS(base))
+
+/*! @brief Set the AVGS field to a new value. */
+#define ADC_WR_SC3_AVGS(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGS_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGS(value)))
+#define ADC_BWR_SC3_AVGS(base, value) (ADC_WR_SC3_AVGS(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field AVGE[2] (RW)
+ *
+ * Enables the hardware average function of the ADC.
+ *
+ * Values:
+ * - 0b0 - Hardware average function disabled.
+ * - 0b1 - Hardware average function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGE field. */
+#define ADC_RD_SC3_AVGE(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGE_MASK) >> ADC_SC3_AVGE_SHIFT)
+#define ADC_BRD_SC3_AVGE(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT))
+
+/*! @brief Set the AVGE field to a new value. */
+#define ADC_WR_SC3_AVGE(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGE_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGE(value)))
+#define ADC_BWR_SC3_AVGE(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field ADCO[3] (RW)
+ *
+ * Enables continuous conversions.
+ *
+ * Values:
+ * - 0b0 - One conversion or one set of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ * - 0b1 - Continuous conversions or sets of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_ADCO field. */
+#define ADC_RD_SC3_ADCO(base) ((ADC_SC3_REG(base) & ADC_SC3_ADCO_MASK) >> ADC_SC3_ADCO_SHIFT)
+#define ADC_BRD_SC3_ADCO(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT))
+
+/*! @brief Set the ADCO field to a new value. */
+#define ADC_WR_SC3_ADCO(base, value) (ADC_RMW_SC3(base, (ADC_SC3_ADCO_MASK | ADC_SC3_CALF_MASK), ADC_SC3_ADCO(value)))
+#define ADC_BWR_SC3_ADCO(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CALF[6] (W1C)
+ *
+ * Displays the result of the calibration sequence. The calibration sequence
+ * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
+ * entered before the calibration sequence completes. Writing 1 to CALF clears it.
+ *
+ * Values:
+ * - 0b0 - Calibration completed normally.
+ * - 0b1 - Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CALF field. */
+#define ADC_RD_SC3_CALF(base) ((ADC_SC3_REG(base) & ADC_SC3_CALF_MASK) >> ADC_SC3_CALF_SHIFT)
+#define ADC_BRD_SC3_CALF(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT))
+
+/*! @brief Set the CALF field to a new value. */
+#define ADC_WR_SC3_CALF(base, value) (ADC_RMW_SC3(base, ADC_SC3_CALF_MASK, ADC_SC3_CALF(value)))
+#define ADC_BWR_SC3_CALF(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CAL[7] (RW)
+ *
+ * Begins the calibration sequence when set. This field stays set while the
+ * calibration is in progress and is cleared when the calibration sequence is
+ * completed. CALF must be checked to determine the result of the calibration sequence.
+ * Once started, the calibration routine cannot be interrupted by writes to the
+ * ADC registers or the results will be invalid and CALF will set. Setting CAL
+ * will abort any current conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CAL field. */
+#define ADC_RD_SC3_CAL(base) ((ADC_SC3_REG(base) & ADC_SC3_CAL_MASK) >> ADC_SC3_CAL_SHIFT)
+#define ADC_BRD_SC3_CAL(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT))
+
+/*! @brief Set the CAL field to a new value. */
+#define ADC_WR_SC3_CAL(base, value) (ADC_RMW_SC3(base, (ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK), ADC_SC3_CAL(value)))
+#define ADC_BWR_SC3_CAL(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_OFS - ADC Offset Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_OFS - ADC Offset Correction Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * The ADC Offset Correction Register (OFS) contains the user-selected or
+ * calibration-generated offset error correction value. This register is a 2's
+ * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
+ * conversion and the result is transferred into the result registers, Rn. If the
+ * result is greater than the maximum or less than the minimum result value, it is
+ * forced to the appropriate limit for the current mode of operation.
+ */
+/*!
+ * @name Constants and macros for entire ADC_OFS register
+ */
+/*@{*/
+#define ADC_RD_OFS(base)         (ADC_OFS_REG(base))
+#define ADC_WR_OFS(base, value)  (ADC_OFS_REG(base) = (value))
+#define ADC_RMW_OFS(base, mask, value) (ADC_WR_OFS(base, (ADC_RD_OFS(base) & ~(mask)) | (value)))
+#define ADC_SET_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) |  (value)))
+#define ADC_CLR_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) & ~(value)))
+#define ADC_TOG_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_OFS bitfields
+ */
+
+/*!
+ * @name Register ADC_OFS, field OFS[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_OFS_OFS field. */
+#define ADC_RD_OFS_OFS(base) ((ADC_OFS_REG(base) & ADC_OFS_OFS_MASK) >> ADC_OFS_OFS_SHIFT)
+#define ADC_BRD_OFS_OFS(base) (ADC_RD_OFS_OFS(base))
+
+/*! @brief Set the OFS field to a new value. */
+#define ADC_WR_OFS_OFS(base, value) (ADC_RMW_OFS(base, ADC_OFS_OFS_MASK, ADC_OFS_OFS(value)))
+#define ADC_BWR_OFS_OFS(base, value) (ADC_WR_OFS_OFS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_PG - ADC Plus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_PG - ADC Plus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Plus-Side Gain Register (PG) contains the gain error correction for the
+ * plus-side input in differential mode or the overall conversion in single-ended
+ * mode. PG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
+ * written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_PG register
+ */
+/*@{*/
+#define ADC_RD_PG(base)          (ADC_PG_REG(base))
+#define ADC_WR_PG(base, value)   (ADC_PG_REG(base) = (value))
+#define ADC_RMW_PG(base, mask, value) (ADC_WR_PG(base, (ADC_RD_PG(base) & ~(mask)) | (value)))
+#define ADC_SET_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) |  (value)))
+#define ADC_CLR_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) & ~(value)))
+#define ADC_TOG_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_PG bitfields
+ */
+
+/*!
+ * @name Register ADC_PG, field PG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_PG_PG field. */
+#define ADC_RD_PG_PG(base)   ((ADC_PG_REG(base) & ADC_PG_PG_MASK) >> ADC_PG_PG_SHIFT)
+#define ADC_BRD_PG_PG(base)  (ADC_RD_PG_PG(base))
+
+/*! @brief Set the PG field to a new value. */
+#define ADC_WR_PG_PG(base, value) (ADC_RMW_PG(base, ADC_PG_PG_MASK, ADC_PG_PG(value)))
+#define ADC_BWR_PG_PG(base, value) (ADC_WR_PG_PG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_MG - ADC Minus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_MG - ADC Minus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Minus-Side Gain Register (MG) contains the gain error correction for the
+ * minus-side input in differential mode. This register is ignored in
+ * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
+ * be written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_MG register
+ */
+/*@{*/
+#define ADC_RD_MG(base)          (ADC_MG_REG(base))
+#define ADC_WR_MG(base, value)   (ADC_MG_REG(base) = (value))
+#define ADC_RMW_MG(base, mask, value) (ADC_WR_MG(base, (ADC_RD_MG(base) & ~(mask)) | (value)))
+#define ADC_SET_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) |  (value)))
+#define ADC_CLR_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) & ~(value)))
+#define ADC_TOG_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_MG bitfields
+ */
+
+/*!
+ * @name Register ADC_MG, field MG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_MG_MG field. */
+#define ADC_RD_MG_MG(base)   ((ADC_MG_REG(base) & ADC_MG_MG_MASK) >> ADC_MG_MG_SHIFT)
+#define ADC_BRD_MG_MG(base)  (ADC_RD_MG_MG(base))
+
+/*! @brief Set the MG field to a new value. */
+#define ADC_WR_MG_MG(base, value) (ADC_RMW_MG(base, ADC_MG_MG_MASK, ADC_MG_MG(value)))
+#define ADC_BWR_MG_MG(base, value) (ADC_WR_MG_MG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
+ * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
+ * when the self-calibration sequence is done, that is, CAL is cleared. If these
+ * registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPD register
+ */
+/*@{*/
+#define ADC_RD_CLPD(base)        (ADC_CLPD_REG(base))
+#define ADC_WR_CLPD(base, value) (ADC_CLPD_REG(base) = (value))
+#define ADC_RMW_CLPD(base, mask, value) (ADC_WR_CLPD(base, (ADC_RD_CLPD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) |  (value)))
+#define ADC_CLR_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) & ~(value)))
+#define ADC_TOG_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPD, field CLPD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPD_CLPD field. */
+#define ADC_RD_CLPD_CLPD(base) ((ADC_CLPD_REG(base) & ADC_CLPD_CLPD_MASK) >> ADC_CLPD_CLPD_SHIFT)
+#define ADC_BRD_CLPD_CLPD(base) (ADC_RD_CLPD_CLPD(base))
+
+/*! @brief Set the CLPD field to a new value. */
+#define ADC_WR_CLPD_CLPD(base, value) (ADC_RMW_CLPD(base, ADC_CLPD_CLPD_MASK, ADC_CLPD_CLPD(value)))
+#define ADC_BWR_CLPD_CLPD(base, value) (ADC_WR_CLPD_CLPD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPS register
+ */
+/*@{*/
+#define ADC_RD_CLPS(base)        (ADC_CLPS_REG(base))
+#define ADC_WR_CLPS(base, value) (ADC_CLPS_REG(base) = (value))
+#define ADC_RMW_CLPS(base, mask, value) (ADC_WR_CLPS(base, (ADC_RD_CLPS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) |  (value)))
+#define ADC_CLR_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) & ~(value)))
+#define ADC_TOG_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPS, field CLPS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPS_CLPS field. */
+#define ADC_RD_CLPS_CLPS(base) ((ADC_CLPS_REG(base) & ADC_CLPS_CLPS_MASK) >> ADC_CLPS_CLPS_SHIFT)
+#define ADC_BRD_CLPS_CLPS(base) (ADC_RD_CLPS_CLPS(base))
+
+/*! @brief Set the CLPS field to a new value. */
+#define ADC_WR_CLPS_CLPS(base, value) (ADC_RMW_CLPS(base, ADC_CLPS_CLPS_MASK, ADC_CLPS_CLPS(value)))
+#define ADC_BWR_CLPS_CLPS(base, value) (ADC_WR_CLPS_CLPS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP4 register
+ */
+/*@{*/
+#define ADC_RD_CLP4(base)        (ADC_CLP4_REG(base))
+#define ADC_WR_CLP4(base, value) (ADC_CLP4_REG(base) = (value))
+#define ADC_RMW_CLP4(base, mask, value) (ADC_WR_CLP4(base, (ADC_RD_CLP4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) |  (value)))
+#define ADC_CLR_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) & ~(value)))
+#define ADC_TOG_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP4, field CLP4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP4_CLP4 field. */
+#define ADC_RD_CLP4_CLP4(base) ((ADC_CLP4_REG(base) & ADC_CLP4_CLP4_MASK) >> ADC_CLP4_CLP4_SHIFT)
+#define ADC_BRD_CLP4_CLP4(base) (ADC_RD_CLP4_CLP4(base))
+
+/*! @brief Set the CLP4 field to a new value. */
+#define ADC_WR_CLP4_CLP4(base, value) (ADC_RMW_CLP4(base, ADC_CLP4_CLP4_MASK, ADC_CLP4_CLP4(value)))
+#define ADC_BWR_CLP4_CLP4(base, value) (ADC_WR_CLP4_CLP4(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP3 register
+ */
+/*@{*/
+#define ADC_RD_CLP3(base)        (ADC_CLP3_REG(base))
+#define ADC_WR_CLP3(base, value) (ADC_CLP3_REG(base) = (value))
+#define ADC_RMW_CLP3(base, mask, value) (ADC_WR_CLP3(base, (ADC_RD_CLP3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) |  (value)))
+#define ADC_CLR_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) & ~(value)))
+#define ADC_TOG_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP3, field CLP3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP3_CLP3 field. */
+#define ADC_RD_CLP3_CLP3(base) ((ADC_CLP3_REG(base) & ADC_CLP3_CLP3_MASK) >> ADC_CLP3_CLP3_SHIFT)
+#define ADC_BRD_CLP3_CLP3(base) (ADC_RD_CLP3_CLP3(base))
+
+/*! @brief Set the CLP3 field to a new value. */
+#define ADC_WR_CLP3_CLP3(base, value) (ADC_RMW_CLP3(base, ADC_CLP3_CLP3_MASK, ADC_CLP3_CLP3(value)))
+#define ADC_BWR_CLP3_CLP3(base, value) (ADC_WR_CLP3_CLP3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP2 register
+ */
+/*@{*/
+#define ADC_RD_CLP2(base)        (ADC_CLP2_REG(base))
+#define ADC_WR_CLP2(base, value) (ADC_CLP2_REG(base) = (value))
+#define ADC_RMW_CLP2(base, mask, value) (ADC_WR_CLP2(base, (ADC_RD_CLP2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) |  (value)))
+#define ADC_CLR_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) & ~(value)))
+#define ADC_TOG_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP2, field CLP2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP2_CLP2 field. */
+#define ADC_RD_CLP2_CLP2(base) ((ADC_CLP2_REG(base) & ADC_CLP2_CLP2_MASK) >> ADC_CLP2_CLP2_SHIFT)
+#define ADC_BRD_CLP2_CLP2(base) (ADC_RD_CLP2_CLP2(base))
+
+/*! @brief Set the CLP2 field to a new value. */
+#define ADC_WR_CLP2_CLP2(base, value) (ADC_RMW_CLP2(base, ADC_CLP2_CLP2_MASK, ADC_CLP2_CLP2(value)))
+#define ADC_BWR_CLP2_CLP2(base, value) (ADC_WR_CLP2_CLP2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP1 register
+ */
+/*@{*/
+#define ADC_RD_CLP1(base)        (ADC_CLP1_REG(base))
+#define ADC_WR_CLP1(base, value) (ADC_CLP1_REG(base) = (value))
+#define ADC_RMW_CLP1(base, mask, value) (ADC_WR_CLP1(base, (ADC_RD_CLP1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) |  (value)))
+#define ADC_CLR_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) & ~(value)))
+#define ADC_TOG_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP1, field CLP1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP1_CLP1 field. */
+#define ADC_RD_CLP1_CLP1(base) ((ADC_CLP1_REG(base) & ADC_CLP1_CLP1_MASK) >> ADC_CLP1_CLP1_SHIFT)
+#define ADC_BRD_CLP1_CLP1(base) (ADC_RD_CLP1_CLP1(base))
+
+/*! @brief Set the CLP1 field to a new value. */
+#define ADC_WR_CLP1_CLP1(base, value) (ADC_RMW_CLP1(base, ADC_CLP1_CLP1_MASK, ADC_CLP1_CLP1(value)))
+#define ADC_BWR_CLP1_CLP1(base, value) (ADC_WR_CLP1_CLP1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP0 register
+ */
+/*@{*/
+#define ADC_RD_CLP0(base)        (ADC_CLP0_REG(base))
+#define ADC_WR_CLP0(base, value) (ADC_CLP0_REG(base) = (value))
+#define ADC_RMW_CLP0(base, mask, value) (ADC_WR_CLP0(base, (ADC_RD_CLP0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) |  (value)))
+#define ADC_CLR_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) & ~(value)))
+#define ADC_TOG_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP0, field CLP0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP0_CLP0 field. */
+#define ADC_RD_CLP0_CLP0(base) ((ADC_CLP0_REG(base) & ADC_CLP0_CLP0_MASK) >> ADC_CLP0_CLP0_SHIFT)
+#define ADC_BRD_CLP0_CLP0(base) (ADC_RD_CLP0_CLP0(base))
+
+/*! @brief Set the CLP0 field to a new value. */
+#define ADC_WR_CLP0_CLP0(base, value) (ADC_RMW_CLP0(base, ADC_CLP0_CLP0_MASK, ADC_CLP0_CLP0(value)))
+#define ADC_BWR_CLP0_CLP0(base, value) (ADC_WR_CLP0_CLP0(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Minus-Side General Calibration Value (CLMx) registers contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
+ * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
+ * set when the self-calibration sequence is done, that is, CAL is cleared. If
+ * these registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMD register
+ */
+/*@{*/
+#define ADC_RD_CLMD(base)        (ADC_CLMD_REG(base))
+#define ADC_WR_CLMD(base, value) (ADC_CLMD_REG(base) = (value))
+#define ADC_RMW_CLMD(base, mask, value) (ADC_WR_CLMD(base, (ADC_RD_CLMD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) |  (value)))
+#define ADC_CLR_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) & ~(value)))
+#define ADC_TOG_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMD, field CLMD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMD_CLMD field. */
+#define ADC_RD_CLMD_CLMD(base) ((ADC_CLMD_REG(base) & ADC_CLMD_CLMD_MASK) >> ADC_CLMD_CLMD_SHIFT)
+#define ADC_BRD_CLMD_CLMD(base) (ADC_RD_CLMD_CLMD(base))
+
+/*! @brief Set the CLMD field to a new value. */
+#define ADC_WR_CLMD_CLMD(base, value) (ADC_RMW_CLMD(base, ADC_CLMD_CLMD_MASK, ADC_CLMD_CLMD(value)))
+#define ADC_BWR_CLMD_CLMD(base, value) (ADC_WR_CLMD_CLMD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMS register
+ */
+/*@{*/
+#define ADC_RD_CLMS(base)        (ADC_CLMS_REG(base))
+#define ADC_WR_CLMS(base, value) (ADC_CLMS_REG(base) = (value))
+#define ADC_RMW_CLMS(base, mask, value) (ADC_WR_CLMS(base, (ADC_RD_CLMS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) |  (value)))
+#define ADC_CLR_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) & ~(value)))
+#define ADC_TOG_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMS, field CLMS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMS_CLMS field. */
+#define ADC_RD_CLMS_CLMS(base) ((ADC_CLMS_REG(base) & ADC_CLMS_CLMS_MASK) >> ADC_CLMS_CLMS_SHIFT)
+#define ADC_BRD_CLMS_CLMS(base) (ADC_RD_CLMS_CLMS(base))
+
+/*! @brief Set the CLMS field to a new value. */
+#define ADC_WR_CLMS_CLMS(base, value) (ADC_RMW_CLMS(base, ADC_CLMS_CLMS_MASK, ADC_CLMS_CLMS(value)))
+#define ADC_BWR_CLMS_CLMS(base, value) (ADC_WR_CLMS_CLMS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM4 register
+ */
+/*@{*/
+#define ADC_RD_CLM4(base)        (ADC_CLM4_REG(base))
+#define ADC_WR_CLM4(base, value) (ADC_CLM4_REG(base) = (value))
+#define ADC_RMW_CLM4(base, mask, value) (ADC_WR_CLM4(base, (ADC_RD_CLM4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) |  (value)))
+#define ADC_CLR_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) & ~(value)))
+#define ADC_TOG_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM4, field CLM4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM4_CLM4 field. */
+#define ADC_RD_CLM4_CLM4(base) ((ADC_CLM4_REG(base) & ADC_CLM4_CLM4_MASK) >> ADC_CLM4_CLM4_SHIFT)
+#define ADC_BRD_CLM4_CLM4(base) (ADC_RD_CLM4_CLM4(base))
+
+/*! @brief Set the CLM4 field to a new value. */
+#define ADC_WR_CLM4_CLM4(base, value) (ADC_RMW_CLM4(base, ADC_CLM4_CLM4_MASK, ADC_CLM4_CLM4(value)))
+#define ADC_BWR_CLM4_CLM4(base, value) (ADC_WR_CLM4_CLM4(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM3 register
+ */
+/*@{*/
+#define ADC_RD_CLM3(base)        (ADC_CLM3_REG(base))
+#define ADC_WR_CLM3(base, value) (ADC_CLM3_REG(base) = (value))
+#define ADC_RMW_CLM3(base, mask, value) (ADC_WR_CLM3(base, (ADC_RD_CLM3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) |  (value)))
+#define ADC_CLR_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) & ~(value)))
+#define ADC_TOG_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM3, field CLM3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM3_CLM3 field. */
+#define ADC_RD_CLM3_CLM3(base) ((ADC_CLM3_REG(base) & ADC_CLM3_CLM3_MASK) >> ADC_CLM3_CLM3_SHIFT)
+#define ADC_BRD_CLM3_CLM3(base) (ADC_RD_CLM3_CLM3(base))
+
+/*! @brief Set the CLM3 field to a new value. */
+#define ADC_WR_CLM3_CLM3(base, value) (ADC_RMW_CLM3(base, ADC_CLM3_CLM3_MASK, ADC_CLM3_CLM3(value)))
+#define ADC_BWR_CLM3_CLM3(base, value) (ADC_WR_CLM3_CLM3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM2 register
+ */
+/*@{*/
+#define ADC_RD_CLM2(base)        (ADC_CLM2_REG(base))
+#define ADC_WR_CLM2(base, value) (ADC_CLM2_REG(base) = (value))
+#define ADC_RMW_CLM2(base, mask, value) (ADC_WR_CLM2(base, (ADC_RD_CLM2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) |  (value)))
+#define ADC_CLR_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) & ~(value)))
+#define ADC_TOG_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM2, field CLM2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM2_CLM2 field. */
+#define ADC_RD_CLM2_CLM2(base) ((ADC_CLM2_REG(base) & ADC_CLM2_CLM2_MASK) >> ADC_CLM2_CLM2_SHIFT)
+#define ADC_BRD_CLM2_CLM2(base) (ADC_RD_CLM2_CLM2(base))
+
+/*! @brief Set the CLM2 field to a new value. */
+#define ADC_WR_CLM2_CLM2(base, value) (ADC_RMW_CLM2(base, ADC_CLM2_CLM2_MASK, ADC_CLM2_CLM2(value)))
+#define ADC_BWR_CLM2_CLM2(base, value) (ADC_WR_CLM2_CLM2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM1 register
+ */
+/*@{*/
+#define ADC_RD_CLM1(base)        (ADC_CLM1_REG(base))
+#define ADC_WR_CLM1(base, value) (ADC_CLM1_REG(base) = (value))
+#define ADC_RMW_CLM1(base, mask, value) (ADC_WR_CLM1(base, (ADC_RD_CLM1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) |  (value)))
+#define ADC_CLR_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) & ~(value)))
+#define ADC_TOG_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM1, field CLM1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM1_CLM1 field. */
+#define ADC_RD_CLM1_CLM1(base) ((ADC_CLM1_REG(base) & ADC_CLM1_CLM1_MASK) >> ADC_CLM1_CLM1_SHIFT)
+#define ADC_BRD_CLM1_CLM1(base) (ADC_RD_CLM1_CLM1(base))
+
+/*! @brief Set the CLM1 field to a new value. */
+#define ADC_WR_CLM1_CLM1(base, value) (ADC_RMW_CLM1(base, ADC_CLM1_CLM1_MASK, ADC_CLM1_CLM1(value)))
+#define ADC_BWR_CLM1_CLM1(base, value) (ADC_WR_CLM1_CLM1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM0 register
+ */
+/*@{*/
+#define ADC_RD_CLM0(base)        (ADC_CLM0_REG(base))
+#define ADC_WR_CLM0(base, value) (ADC_CLM0_REG(base) = (value))
+#define ADC_RMW_CLM0(base, mask, value) (ADC_WR_CLM0(base, (ADC_RD_CLM0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) |  (value)))
+#define ADC_CLR_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) & ~(value)))
+#define ADC_TOG_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM0, field CLM0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM0_CLM0 field. */
+#define ADC_RD_CLM0_CLM0(base) ((ADC_CLM0_REG(base) & ADC_CLM0_CLM0_MASK) >> ADC_CLM0_CLM0_SHIFT)
+#define ADC_BRD_CLM0_CLM0(base) (ADC_RD_CLM0_CLM0(base))
+
+/*! @brief Set the CLM0 field to a new value. */
+#define ADC_WR_CLM0_CLM0(base, value) (ADC_RMW_CLM0(base, ADC_CLM0_CLM0_MASK, ADC_CLM0_CLM0(value)))
+#define ADC_BWR_CLM0_CLM0(base, value) (ADC_WR_CLM0_CLM0(base, value))
+/*@}*/
+
+/*
+ * MK64F12 AIPS
+ *
+ * AIPS-Lite Bridge
+ *
+ * Registers defined in this header file:
+ * - AIPS_MPRA - Master Privilege Register A
+ * - AIPS_PACRA - Peripheral Access Control Register
+ * - AIPS_PACRB - Peripheral Access Control Register
+ * - AIPS_PACRC - Peripheral Access Control Register
+ * - AIPS_PACRD - Peripheral Access Control Register
+ * - AIPS_PACRE - Peripheral Access Control Register
+ * - AIPS_PACRF - Peripheral Access Control Register
+ * - AIPS_PACRG - Peripheral Access Control Register
+ * - AIPS_PACRH - Peripheral Access Control Register
+ * - AIPS_PACRI - Peripheral Access Control Register
+ * - AIPS_PACRJ - Peripheral Access Control Register
+ * - AIPS_PACRK - Peripheral Access Control Register
+ * - AIPS_PACRL - Peripheral Access Control Register
+ * - AIPS_PACRM - Peripheral Access Control Register
+ * - AIPS_PACRN - Peripheral Access Control Register
+ * - AIPS_PACRO - Peripheral Access Control Register
+ * - AIPS_PACRP - Peripheral Access Control Register
+ * - AIPS_PACRU - Peripheral Access Control Register
+ */
+
+#define AIPS_INSTANCE_COUNT (2U) /*!< Number of instances of the AIPS module. */
+#define AIPS0_IDX (0U) /*!< Instance number for AIPS0. */
+#define AIPS1_IDX (1U) /*!< Instance number for AIPS1. */
+
+/*******************************************************************************
+ * AIPS_MPRA - Master Privilege Register A
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_MPRA - Master Privilege Register A (RW)
+ *
+ * Reset value: 0x77700000U
+ *
+ * The MPRA specifies identical 4-bit fields defining the access-privilege level
+ * associated with a bus master to various peripherals on the chip. The register
+ * provides one field per bus master. At reset, the default value loaded into
+ * the MPRA fields is chip-specific. See the chip configuration details for the
+ * value of a particular device. A register field that maps to an unimplemented
+ * master or peripheral behaves as read-only-zero. Each master is assigned a logical
+ * ID from 0 to 15. See the master logical ID assignment table in the
+ * chip-specific AIPS information.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_MPRA register
+ */
+/*@{*/
+#define AIPS_RD_MPRA(base)       (AIPS_MPRA_REG(base))
+#define AIPS_WR_MPRA(base, value) (AIPS_MPRA_REG(base) = (value))
+#define AIPS_RMW_MPRA(base, mask, value) (AIPS_WR_MPRA(base, (AIPS_RD_MPRA(base) & ~(mask)) | (value)))
+#define AIPS_SET_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) |  (value)))
+#define AIPS_CLR_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) & ~(value)))
+#define AIPS_TOG_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_MPRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_MPRA, field MPL5[8] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL5 field. */
+#define AIPS_RD_MPRA_MPL5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL5_MASK) >> AIPS_MPRA_MPL5_SHIFT)
+#define AIPS_BRD_MPRA_MPL5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL5_SHIFT))
+
+/*! @brief Set the MPL5 field to a new value. */
+#define AIPS_WR_MPRA_MPL5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL5_MASK, AIPS_MPRA_MPL5(value)))
+#define AIPS_BWR_MPRA_MPL5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW5[9] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW5 field. */
+#define AIPS_RD_MPRA_MTW5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW5_MASK) >> AIPS_MPRA_MTW5_SHIFT)
+#define AIPS_BRD_MPRA_MTW5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW5_SHIFT))
+
+/*! @brief Set the MTW5 field to a new value. */
+#define AIPS_WR_MPRA_MTW5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW5_MASK, AIPS_MPRA_MTW5(value)))
+#define AIPS_BWR_MPRA_MTW5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR5[10] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR5 field. */
+#define AIPS_RD_MPRA_MTR5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR5_MASK) >> AIPS_MPRA_MTR5_SHIFT)
+#define AIPS_BRD_MPRA_MTR5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR5_SHIFT))
+
+/*! @brief Set the MTR5 field to a new value. */
+#define AIPS_WR_MPRA_MTR5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR5_MASK, AIPS_MPRA_MTR5(value)))
+#define AIPS_BWR_MPRA_MTR5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL4[12] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL4 field. */
+#define AIPS_RD_MPRA_MPL4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL4_MASK) >> AIPS_MPRA_MPL4_SHIFT)
+#define AIPS_BRD_MPRA_MPL4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL4_SHIFT))
+
+/*! @brief Set the MPL4 field to a new value. */
+#define AIPS_WR_MPRA_MPL4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL4_MASK, AIPS_MPRA_MPL4(value)))
+#define AIPS_BWR_MPRA_MPL4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW4[13] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW4 field. */
+#define AIPS_RD_MPRA_MTW4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW4_MASK) >> AIPS_MPRA_MTW4_SHIFT)
+#define AIPS_BRD_MPRA_MTW4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW4_SHIFT))
+
+/*! @brief Set the MTW4 field to a new value. */
+#define AIPS_WR_MPRA_MTW4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW4_MASK, AIPS_MPRA_MTW4(value)))
+#define AIPS_BWR_MPRA_MTW4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR4[14] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR4 field. */
+#define AIPS_RD_MPRA_MTR4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR4_MASK) >> AIPS_MPRA_MTR4_SHIFT)
+#define AIPS_BRD_MPRA_MTR4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR4_SHIFT))
+
+/*! @brief Set the MTR4 field to a new value. */
+#define AIPS_WR_MPRA_MTR4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR4_MASK, AIPS_MPRA_MTR4(value)))
+#define AIPS_BWR_MPRA_MTR4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL3[16] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL3 field. */
+#define AIPS_RD_MPRA_MPL3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL3_MASK) >> AIPS_MPRA_MPL3_SHIFT)
+#define AIPS_BRD_MPRA_MPL3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL3_SHIFT))
+
+/*! @brief Set the MPL3 field to a new value. */
+#define AIPS_WR_MPRA_MPL3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL3_MASK, AIPS_MPRA_MPL3(value)))
+#define AIPS_BWR_MPRA_MPL3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW3[17] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW3 field. */
+#define AIPS_RD_MPRA_MTW3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW3_MASK) >> AIPS_MPRA_MTW3_SHIFT)
+#define AIPS_BRD_MPRA_MTW3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW3_SHIFT))
+
+/*! @brief Set the MTW3 field to a new value. */
+#define AIPS_WR_MPRA_MTW3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW3_MASK, AIPS_MPRA_MTW3(value)))
+#define AIPS_BWR_MPRA_MTW3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR3[18] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR3 field. */
+#define AIPS_RD_MPRA_MTR3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR3_MASK) >> AIPS_MPRA_MTR3_SHIFT)
+#define AIPS_BRD_MPRA_MTR3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR3_SHIFT))
+
+/*! @brief Set the MTR3 field to a new value. */
+#define AIPS_WR_MPRA_MTR3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR3_MASK, AIPS_MPRA_MTR3(value)))
+#define AIPS_BWR_MPRA_MTR3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL2[20] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL2 field. */
+#define AIPS_RD_MPRA_MPL2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL2_MASK) >> AIPS_MPRA_MPL2_SHIFT)
+#define AIPS_BRD_MPRA_MPL2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL2_SHIFT))
+
+/*! @brief Set the MPL2 field to a new value. */
+#define AIPS_WR_MPRA_MPL2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL2_MASK, AIPS_MPRA_MPL2(value)))
+#define AIPS_BWR_MPRA_MPL2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW2[21] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW2 field. */
+#define AIPS_RD_MPRA_MTW2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW2_MASK) >> AIPS_MPRA_MTW2_SHIFT)
+#define AIPS_BRD_MPRA_MTW2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW2_SHIFT))
+
+/*! @brief Set the MTW2 field to a new value. */
+#define AIPS_WR_MPRA_MTW2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW2_MASK, AIPS_MPRA_MTW2(value)))
+#define AIPS_BWR_MPRA_MTW2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR2[22] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR2 field. */
+#define AIPS_RD_MPRA_MTR2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR2_MASK) >> AIPS_MPRA_MTR2_SHIFT)
+#define AIPS_BRD_MPRA_MTR2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR2_SHIFT))
+
+/*! @brief Set the MTR2 field to a new value. */
+#define AIPS_WR_MPRA_MTR2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR2_MASK, AIPS_MPRA_MTR2(value)))
+#define AIPS_BWR_MPRA_MTR2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL1[24] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL1 field. */
+#define AIPS_RD_MPRA_MPL1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL1_MASK) >> AIPS_MPRA_MPL1_SHIFT)
+#define AIPS_BRD_MPRA_MPL1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL1_SHIFT))
+
+/*! @brief Set the MPL1 field to a new value. */
+#define AIPS_WR_MPRA_MPL1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL1_MASK, AIPS_MPRA_MPL1(value)))
+#define AIPS_BWR_MPRA_MPL1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW1[25] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW1 field. */
+#define AIPS_RD_MPRA_MTW1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW1_MASK) >> AIPS_MPRA_MTW1_SHIFT)
+#define AIPS_BRD_MPRA_MTW1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW1_SHIFT))
+
+/*! @brief Set the MTW1 field to a new value. */
+#define AIPS_WR_MPRA_MTW1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW1_MASK, AIPS_MPRA_MTW1(value)))
+#define AIPS_BWR_MPRA_MTW1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR1[26] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR1 field. */
+#define AIPS_RD_MPRA_MTR1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR1_MASK) >> AIPS_MPRA_MTR1_SHIFT)
+#define AIPS_BRD_MPRA_MTR1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR1_SHIFT))
+
+/*! @brief Set the MTR1 field to a new value. */
+#define AIPS_WR_MPRA_MTR1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR1_MASK, AIPS_MPRA_MTR1(value)))
+#define AIPS_BWR_MPRA_MTR1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL0[28] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL0 field. */
+#define AIPS_RD_MPRA_MPL0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL0_MASK) >> AIPS_MPRA_MPL0_SHIFT)
+#define AIPS_BRD_MPRA_MPL0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL0_SHIFT))
+
+/*! @brief Set the MPL0 field to a new value. */
+#define AIPS_WR_MPRA_MPL0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL0_MASK, AIPS_MPRA_MPL0(value)))
+#define AIPS_BWR_MPRA_MPL0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW0[29] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW0 field. */
+#define AIPS_RD_MPRA_MTW0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW0_MASK) >> AIPS_MPRA_MTW0_SHIFT)
+#define AIPS_BRD_MPRA_MTW0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW0_SHIFT))
+
+/*! @brief Set the MTW0 field to a new value. */
+#define AIPS_WR_MPRA_MTW0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW0_MASK, AIPS_MPRA_MTW0(value)))
+#define AIPS_BWR_MPRA_MTW0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR0[30] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR0 field. */
+#define AIPS_RD_MPRA_MTR0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR0_MASK) >> AIPS_MPRA_MTR0_SHIFT)
+#define AIPS_BRD_MPRA_MTR0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR0_SHIFT))
+
+/*! @brief Set the MTR0 field to a new value. */
+#define AIPS_WR_MPRA_MTR0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR0_MASK, AIPS_MPRA_MTR0(value)))
+#define AIPS_BWR_MPRA_MTR0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRA - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRA - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x50004000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRA register
+ */
+/*@{*/
+#define AIPS_RD_PACRA(base)      (AIPS_PACRA_REG(base))
+#define AIPS_WR_PACRA(base, value) (AIPS_PACRA_REG(base) = (value))
+#define AIPS_RMW_PACRA(base, mask, value) (AIPS_WR_PACRA(base, (AIPS_RD_PACRA(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) |  (value)))
+#define AIPS_CLR_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) & ~(value)))
+#define AIPS_TOG_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRA, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP7 field. */
+#define AIPS_RD_PACRA_TP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP7_MASK) >> AIPS_PACRA_TP7_SHIFT)
+#define AIPS_BRD_PACRA_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRA_TP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP7_MASK, AIPS_PACRA_TP7(value)))
+#define AIPS_BWR_PACRA_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP7 field. */
+#define AIPS_RD_PACRA_WP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP7_MASK) >> AIPS_PACRA_WP7_SHIFT)
+#define AIPS_BRD_PACRA_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRA_WP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP7_MASK, AIPS_PACRA_WP7(value)))
+#define AIPS_BWR_PACRA_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP7 field. */
+#define AIPS_RD_PACRA_SP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP7_MASK) >> AIPS_PACRA_SP7_SHIFT)
+#define AIPS_BRD_PACRA_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRA_SP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP7_MASK, AIPS_PACRA_SP7(value)))
+#define AIPS_BWR_PACRA_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP6 field. */
+#define AIPS_RD_PACRA_TP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP6_MASK) >> AIPS_PACRA_TP6_SHIFT)
+#define AIPS_BRD_PACRA_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRA_TP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP6_MASK, AIPS_PACRA_TP6(value)))
+#define AIPS_BWR_PACRA_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP6 field. */
+#define AIPS_RD_PACRA_WP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP6_MASK) >> AIPS_PACRA_WP6_SHIFT)
+#define AIPS_BRD_PACRA_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRA_WP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP6_MASK, AIPS_PACRA_WP6(value)))
+#define AIPS_BWR_PACRA_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP6 field. */
+#define AIPS_RD_PACRA_SP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP6_MASK) >> AIPS_PACRA_SP6_SHIFT)
+#define AIPS_BRD_PACRA_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRA_SP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP6_MASK, AIPS_PACRA_SP6(value)))
+#define AIPS_BWR_PACRA_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP5 field. */
+#define AIPS_RD_PACRA_TP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP5_MASK) >> AIPS_PACRA_TP5_SHIFT)
+#define AIPS_BRD_PACRA_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRA_TP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP5_MASK, AIPS_PACRA_TP5(value)))
+#define AIPS_BWR_PACRA_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP5 field. */
+#define AIPS_RD_PACRA_WP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP5_MASK) >> AIPS_PACRA_WP5_SHIFT)
+#define AIPS_BRD_PACRA_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRA_WP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP5_MASK, AIPS_PACRA_WP5(value)))
+#define AIPS_BWR_PACRA_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP5 field. */
+#define AIPS_RD_PACRA_SP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP5_MASK) >> AIPS_PACRA_SP5_SHIFT)
+#define AIPS_BRD_PACRA_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRA_SP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP5_MASK, AIPS_PACRA_SP5(value)))
+#define AIPS_BWR_PACRA_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP4 field. */
+#define AIPS_RD_PACRA_TP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP4_MASK) >> AIPS_PACRA_TP4_SHIFT)
+#define AIPS_BRD_PACRA_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRA_TP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP4_MASK, AIPS_PACRA_TP4(value)))
+#define AIPS_BWR_PACRA_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP4 field. */
+#define AIPS_RD_PACRA_WP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP4_MASK) >> AIPS_PACRA_WP4_SHIFT)
+#define AIPS_BRD_PACRA_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRA_WP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP4_MASK, AIPS_PACRA_WP4(value)))
+#define AIPS_BWR_PACRA_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP4 field. */
+#define AIPS_RD_PACRA_SP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP4_MASK) >> AIPS_PACRA_SP4_SHIFT)
+#define AIPS_BRD_PACRA_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRA_SP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP4_MASK, AIPS_PACRA_SP4(value)))
+#define AIPS_BWR_PACRA_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP3 field. */
+#define AIPS_RD_PACRA_TP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP3_MASK) >> AIPS_PACRA_TP3_SHIFT)
+#define AIPS_BRD_PACRA_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRA_TP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP3_MASK, AIPS_PACRA_TP3(value)))
+#define AIPS_BWR_PACRA_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP3 field. */
+#define AIPS_RD_PACRA_WP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP3_MASK) >> AIPS_PACRA_WP3_SHIFT)
+#define AIPS_BRD_PACRA_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRA_WP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP3_MASK, AIPS_PACRA_WP3(value)))
+#define AIPS_BWR_PACRA_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP3 field. */
+#define AIPS_RD_PACRA_SP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP3_MASK) >> AIPS_PACRA_SP3_SHIFT)
+#define AIPS_BRD_PACRA_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRA_SP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP3_MASK, AIPS_PACRA_SP3(value)))
+#define AIPS_BWR_PACRA_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP2 field. */
+#define AIPS_RD_PACRA_TP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP2_MASK) >> AIPS_PACRA_TP2_SHIFT)
+#define AIPS_BRD_PACRA_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRA_TP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP2_MASK, AIPS_PACRA_TP2(value)))
+#define AIPS_BWR_PACRA_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP2 field. */
+#define AIPS_RD_PACRA_WP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP2_MASK) >> AIPS_PACRA_WP2_SHIFT)
+#define AIPS_BRD_PACRA_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRA_WP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP2_MASK, AIPS_PACRA_WP2(value)))
+#define AIPS_BWR_PACRA_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP2 field. */
+#define AIPS_RD_PACRA_SP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP2_MASK) >> AIPS_PACRA_SP2_SHIFT)
+#define AIPS_BRD_PACRA_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRA_SP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP2_MASK, AIPS_PACRA_SP2(value)))
+#define AIPS_BWR_PACRA_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP1 field. */
+#define AIPS_RD_PACRA_TP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP1_MASK) >> AIPS_PACRA_TP1_SHIFT)
+#define AIPS_BRD_PACRA_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRA_TP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP1_MASK, AIPS_PACRA_TP1(value)))
+#define AIPS_BWR_PACRA_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP1 field. */
+#define AIPS_RD_PACRA_WP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP1_MASK) >> AIPS_PACRA_WP1_SHIFT)
+#define AIPS_BRD_PACRA_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRA_WP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP1_MASK, AIPS_PACRA_WP1(value)))
+#define AIPS_BWR_PACRA_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP1 field. */
+#define AIPS_RD_PACRA_SP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP1_MASK) >> AIPS_PACRA_SP1_SHIFT)
+#define AIPS_BRD_PACRA_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRA_SP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP1_MASK, AIPS_PACRA_SP1(value)))
+#define AIPS_BWR_PACRA_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP0 field. */
+#define AIPS_RD_PACRA_TP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP0_MASK) >> AIPS_PACRA_TP0_SHIFT)
+#define AIPS_BRD_PACRA_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRA_TP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP0_MASK, AIPS_PACRA_TP0(value)))
+#define AIPS_BWR_PACRA_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP0 field. */
+#define AIPS_RD_PACRA_WP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP0_MASK) >> AIPS_PACRA_WP0_SHIFT)
+#define AIPS_BRD_PACRA_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRA_WP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP0_MASK, AIPS_PACRA_WP0(value)))
+#define AIPS_BWR_PACRA_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP0 field. */
+#define AIPS_RD_PACRA_SP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP0_MASK) >> AIPS_PACRA_SP0_SHIFT)
+#define AIPS_BRD_PACRA_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRA_SP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP0_MASK, AIPS_PACRA_SP0(value)))
+#define AIPS_BWR_PACRA_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRB - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRB - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44004400U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRB register
+ */
+/*@{*/
+#define AIPS_RD_PACRB(base)      (AIPS_PACRB_REG(base))
+#define AIPS_WR_PACRB(base, value) (AIPS_PACRB_REG(base) = (value))
+#define AIPS_RMW_PACRB(base, mask, value) (AIPS_WR_PACRB(base, (AIPS_RD_PACRB(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) |  (value)))
+#define AIPS_CLR_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) & ~(value)))
+#define AIPS_TOG_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRB bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRB, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP7 field. */
+#define AIPS_RD_PACRB_TP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP7_MASK) >> AIPS_PACRB_TP7_SHIFT)
+#define AIPS_BRD_PACRB_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRB_TP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP7_MASK, AIPS_PACRB_TP7(value)))
+#define AIPS_BWR_PACRB_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP7 field. */
+#define AIPS_RD_PACRB_WP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP7_MASK) >> AIPS_PACRB_WP7_SHIFT)
+#define AIPS_BRD_PACRB_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRB_WP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP7_MASK, AIPS_PACRB_WP7(value)))
+#define AIPS_BWR_PACRB_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP7 field. */
+#define AIPS_RD_PACRB_SP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP7_MASK) >> AIPS_PACRB_SP7_SHIFT)
+#define AIPS_BRD_PACRB_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRB_SP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP7_MASK, AIPS_PACRB_SP7(value)))
+#define AIPS_BWR_PACRB_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP6 field. */
+#define AIPS_RD_PACRB_TP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP6_MASK) >> AIPS_PACRB_TP6_SHIFT)
+#define AIPS_BRD_PACRB_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRB_TP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP6_MASK, AIPS_PACRB_TP6(value)))
+#define AIPS_BWR_PACRB_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP6 field. */
+#define AIPS_RD_PACRB_WP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP6_MASK) >> AIPS_PACRB_WP6_SHIFT)
+#define AIPS_BRD_PACRB_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRB_WP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP6_MASK, AIPS_PACRB_WP6(value)))
+#define AIPS_BWR_PACRB_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP6 field. */
+#define AIPS_RD_PACRB_SP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP6_MASK) >> AIPS_PACRB_SP6_SHIFT)
+#define AIPS_BRD_PACRB_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRB_SP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP6_MASK, AIPS_PACRB_SP6(value)))
+#define AIPS_BWR_PACRB_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP5 field. */
+#define AIPS_RD_PACRB_TP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP5_MASK) >> AIPS_PACRB_TP5_SHIFT)
+#define AIPS_BRD_PACRB_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRB_TP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP5_MASK, AIPS_PACRB_TP5(value)))
+#define AIPS_BWR_PACRB_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP5 field. */
+#define AIPS_RD_PACRB_WP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP5_MASK) >> AIPS_PACRB_WP5_SHIFT)
+#define AIPS_BRD_PACRB_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRB_WP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP5_MASK, AIPS_PACRB_WP5(value)))
+#define AIPS_BWR_PACRB_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP5 field. */
+#define AIPS_RD_PACRB_SP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP5_MASK) >> AIPS_PACRB_SP5_SHIFT)
+#define AIPS_BRD_PACRB_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRB_SP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP5_MASK, AIPS_PACRB_SP5(value)))
+#define AIPS_BWR_PACRB_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP4 field. */
+#define AIPS_RD_PACRB_TP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP4_MASK) >> AIPS_PACRB_TP4_SHIFT)
+#define AIPS_BRD_PACRB_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRB_TP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP4_MASK, AIPS_PACRB_TP4(value)))
+#define AIPS_BWR_PACRB_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP4 field. */
+#define AIPS_RD_PACRB_WP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP4_MASK) >> AIPS_PACRB_WP4_SHIFT)
+#define AIPS_BRD_PACRB_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRB_WP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP4_MASK, AIPS_PACRB_WP4(value)))
+#define AIPS_BWR_PACRB_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP4 field. */
+#define AIPS_RD_PACRB_SP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP4_MASK) >> AIPS_PACRB_SP4_SHIFT)
+#define AIPS_BRD_PACRB_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRB_SP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP4_MASK, AIPS_PACRB_SP4(value)))
+#define AIPS_BWR_PACRB_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP3 field. */
+#define AIPS_RD_PACRB_TP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP3_MASK) >> AIPS_PACRB_TP3_SHIFT)
+#define AIPS_BRD_PACRB_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRB_TP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP3_MASK, AIPS_PACRB_TP3(value)))
+#define AIPS_BWR_PACRB_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP3 field. */
+#define AIPS_RD_PACRB_WP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP3_MASK) >> AIPS_PACRB_WP3_SHIFT)
+#define AIPS_BRD_PACRB_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRB_WP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP3_MASK, AIPS_PACRB_WP3(value)))
+#define AIPS_BWR_PACRB_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP3 field. */
+#define AIPS_RD_PACRB_SP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP3_MASK) >> AIPS_PACRB_SP3_SHIFT)
+#define AIPS_BRD_PACRB_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRB_SP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP3_MASK, AIPS_PACRB_SP3(value)))
+#define AIPS_BWR_PACRB_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP2 field. */
+#define AIPS_RD_PACRB_TP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP2_MASK) >> AIPS_PACRB_TP2_SHIFT)
+#define AIPS_BRD_PACRB_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRB_TP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP2_MASK, AIPS_PACRB_TP2(value)))
+#define AIPS_BWR_PACRB_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP2 field. */
+#define AIPS_RD_PACRB_WP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP2_MASK) >> AIPS_PACRB_WP2_SHIFT)
+#define AIPS_BRD_PACRB_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRB_WP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP2_MASK, AIPS_PACRB_WP2(value)))
+#define AIPS_BWR_PACRB_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP2 field. */
+#define AIPS_RD_PACRB_SP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP2_MASK) >> AIPS_PACRB_SP2_SHIFT)
+#define AIPS_BRD_PACRB_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRB_SP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP2_MASK, AIPS_PACRB_SP2(value)))
+#define AIPS_BWR_PACRB_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP1 field. */
+#define AIPS_RD_PACRB_TP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP1_MASK) >> AIPS_PACRB_TP1_SHIFT)
+#define AIPS_BRD_PACRB_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRB_TP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP1_MASK, AIPS_PACRB_TP1(value)))
+#define AIPS_BWR_PACRB_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP1 field. */
+#define AIPS_RD_PACRB_WP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP1_MASK) >> AIPS_PACRB_WP1_SHIFT)
+#define AIPS_BRD_PACRB_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRB_WP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP1_MASK, AIPS_PACRB_WP1(value)))
+#define AIPS_BWR_PACRB_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP1 field. */
+#define AIPS_RD_PACRB_SP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP1_MASK) >> AIPS_PACRB_SP1_SHIFT)
+#define AIPS_BRD_PACRB_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRB_SP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP1_MASK, AIPS_PACRB_SP1(value)))
+#define AIPS_BWR_PACRB_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP0 field. */
+#define AIPS_RD_PACRB_TP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP0_MASK) >> AIPS_PACRB_TP0_SHIFT)
+#define AIPS_BRD_PACRB_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRB_TP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP0_MASK, AIPS_PACRB_TP0(value)))
+#define AIPS_BWR_PACRB_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP0 field. */
+#define AIPS_RD_PACRB_WP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP0_MASK) >> AIPS_PACRB_WP0_SHIFT)
+#define AIPS_BRD_PACRB_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRB_WP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP0_MASK, AIPS_PACRB_WP0(value)))
+#define AIPS_BWR_PACRB_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP0 field. */
+#define AIPS_RD_PACRB_SP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP0_MASK) >> AIPS_PACRB_SP0_SHIFT)
+#define AIPS_BRD_PACRB_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRB_SP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP0_MASK, AIPS_PACRB_SP0(value)))
+#define AIPS_BWR_PACRB_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRC - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRC - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRC register
+ */
+/*@{*/
+#define AIPS_RD_PACRC(base)      (AIPS_PACRC_REG(base))
+#define AIPS_WR_PACRC(base, value) (AIPS_PACRC_REG(base) = (value))
+#define AIPS_RMW_PACRC(base, mask, value) (AIPS_WR_PACRC(base, (AIPS_RD_PACRC(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) |  (value)))
+#define AIPS_CLR_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) & ~(value)))
+#define AIPS_TOG_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRC bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRC, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP7 field. */
+#define AIPS_RD_PACRC_TP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP7_MASK) >> AIPS_PACRC_TP7_SHIFT)
+#define AIPS_BRD_PACRC_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRC_TP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP7_MASK, AIPS_PACRC_TP7(value)))
+#define AIPS_BWR_PACRC_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP7 field. */
+#define AIPS_RD_PACRC_WP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP7_MASK) >> AIPS_PACRC_WP7_SHIFT)
+#define AIPS_BRD_PACRC_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRC_WP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP7_MASK, AIPS_PACRC_WP7(value)))
+#define AIPS_BWR_PACRC_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP7 field. */
+#define AIPS_RD_PACRC_SP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP7_MASK) >> AIPS_PACRC_SP7_SHIFT)
+#define AIPS_BRD_PACRC_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRC_SP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP7_MASK, AIPS_PACRC_SP7(value)))
+#define AIPS_BWR_PACRC_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP6 field. */
+#define AIPS_RD_PACRC_TP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP6_MASK) >> AIPS_PACRC_TP6_SHIFT)
+#define AIPS_BRD_PACRC_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRC_TP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP6_MASK, AIPS_PACRC_TP6(value)))
+#define AIPS_BWR_PACRC_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP6 field. */
+#define AIPS_RD_PACRC_WP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP6_MASK) >> AIPS_PACRC_WP6_SHIFT)
+#define AIPS_BRD_PACRC_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRC_WP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP6_MASK, AIPS_PACRC_WP6(value)))
+#define AIPS_BWR_PACRC_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP6 field. */
+#define AIPS_RD_PACRC_SP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP6_MASK) >> AIPS_PACRC_SP6_SHIFT)
+#define AIPS_BRD_PACRC_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRC_SP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP6_MASK, AIPS_PACRC_SP6(value)))
+#define AIPS_BWR_PACRC_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP5 field. */
+#define AIPS_RD_PACRC_TP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP5_MASK) >> AIPS_PACRC_TP5_SHIFT)
+#define AIPS_BRD_PACRC_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRC_TP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP5_MASK, AIPS_PACRC_TP5(value)))
+#define AIPS_BWR_PACRC_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP5 field. */
+#define AIPS_RD_PACRC_WP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP5_MASK) >> AIPS_PACRC_WP5_SHIFT)
+#define AIPS_BRD_PACRC_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRC_WP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP5_MASK, AIPS_PACRC_WP5(value)))
+#define AIPS_BWR_PACRC_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP5 field. */
+#define AIPS_RD_PACRC_SP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP5_MASK) >> AIPS_PACRC_SP5_SHIFT)
+#define AIPS_BRD_PACRC_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRC_SP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP5_MASK, AIPS_PACRC_SP5(value)))
+#define AIPS_BWR_PACRC_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP4 field. */
+#define AIPS_RD_PACRC_TP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP4_MASK) >> AIPS_PACRC_TP4_SHIFT)
+#define AIPS_BRD_PACRC_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRC_TP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP4_MASK, AIPS_PACRC_TP4(value)))
+#define AIPS_BWR_PACRC_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP4 field. */
+#define AIPS_RD_PACRC_WP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP4_MASK) >> AIPS_PACRC_WP4_SHIFT)
+#define AIPS_BRD_PACRC_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRC_WP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP4_MASK, AIPS_PACRC_WP4(value)))
+#define AIPS_BWR_PACRC_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP4 field. */
+#define AIPS_RD_PACRC_SP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP4_MASK) >> AIPS_PACRC_SP4_SHIFT)
+#define AIPS_BRD_PACRC_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRC_SP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP4_MASK, AIPS_PACRC_SP4(value)))
+#define AIPS_BWR_PACRC_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP3 field. */
+#define AIPS_RD_PACRC_TP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP3_MASK) >> AIPS_PACRC_TP3_SHIFT)
+#define AIPS_BRD_PACRC_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRC_TP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP3_MASK, AIPS_PACRC_TP3(value)))
+#define AIPS_BWR_PACRC_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP3 field. */
+#define AIPS_RD_PACRC_WP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP3_MASK) >> AIPS_PACRC_WP3_SHIFT)
+#define AIPS_BRD_PACRC_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRC_WP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP3_MASK, AIPS_PACRC_WP3(value)))
+#define AIPS_BWR_PACRC_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP3 field. */
+#define AIPS_RD_PACRC_SP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP3_MASK) >> AIPS_PACRC_SP3_SHIFT)
+#define AIPS_BRD_PACRC_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRC_SP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP3_MASK, AIPS_PACRC_SP3(value)))
+#define AIPS_BWR_PACRC_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP2 field. */
+#define AIPS_RD_PACRC_TP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP2_MASK) >> AIPS_PACRC_TP2_SHIFT)
+#define AIPS_BRD_PACRC_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRC_TP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP2_MASK, AIPS_PACRC_TP2(value)))
+#define AIPS_BWR_PACRC_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP2 field. */
+#define AIPS_RD_PACRC_WP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP2_MASK) >> AIPS_PACRC_WP2_SHIFT)
+#define AIPS_BRD_PACRC_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRC_WP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP2_MASK, AIPS_PACRC_WP2(value)))
+#define AIPS_BWR_PACRC_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP2 field. */
+#define AIPS_RD_PACRC_SP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP2_MASK) >> AIPS_PACRC_SP2_SHIFT)
+#define AIPS_BRD_PACRC_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRC_SP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP2_MASK, AIPS_PACRC_SP2(value)))
+#define AIPS_BWR_PACRC_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP1 field. */
+#define AIPS_RD_PACRC_TP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP1_MASK) >> AIPS_PACRC_TP1_SHIFT)
+#define AIPS_BRD_PACRC_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRC_TP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP1_MASK, AIPS_PACRC_TP1(value)))
+#define AIPS_BWR_PACRC_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP1 field. */
+#define AIPS_RD_PACRC_WP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP1_MASK) >> AIPS_PACRC_WP1_SHIFT)
+#define AIPS_BRD_PACRC_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRC_WP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP1_MASK, AIPS_PACRC_WP1(value)))
+#define AIPS_BWR_PACRC_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP1 field. */
+#define AIPS_RD_PACRC_SP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP1_MASK) >> AIPS_PACRC_SP1_SHIFT)
+#define AIPS_BRD_PACRC_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRC_SP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP1_MASK, AIPS_PACRC_SP1(value)))
+#define AIPS_BWR_PACRC_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP0 field. */
+#define AIPS_RD_PACRC_TP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP0_MASK) >> AIPS_PACRC_TP0_SHIFT)
+#define AIPS_BRD_PACRC_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRC_TP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP0_MASK, AIPS_PACRC_TP0(value)))
+#define AIPS_BWR_PACRC_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP0 field. */
+#define AIPS_RD_PACRC_WP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP0_MASK) >> AIPS_PACRC_WP0_SHIFT)
+#define AIPS_BRD_PACRC_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRC_WP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP0_MASK, AIPS_PACRC_WP0(value)))
+#define AIPS_BWR_PACRC_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP0 field. */
+#define AIPS_RD_PACRC_SP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP0_MASK) >> AIPS_PACRC_SP0_SHIFT)
+#define AIPS_BRD_PACRC_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRC_SP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP0_MASK, AIPS_PACRC_SP0(value)))
+#define AIPS_BWR_PACRC_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRD - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRD - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRD register
+ */
+/*@{*/
+#define AIPS_RD_PACRD(base)      (AIPS_PACRD_REG(base))
+#define AIPS_WR_PACRD(base, value) (AIPS_PACRD_REG(base) = (value))
+#define AIPS_RMW_PACRD(base, mask, value) (AIPS_WR_PACRD(base, (AIPS_RD_PACRD(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) |  (value)))
+#define AIPS_CLR_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) & ~(value)))
+#define AIPS_TOG_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRD bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRD, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP7 field. */
+#define AIPS_RD_PACRD_TP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP7_MASK) >> AIPS_PACRD_TP7_SHIFT)
+#define AIPS_BRD_PACRD_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRD_TP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP7_MASK, AIPS_PACRD_TP7(value)))
+#define AIPS_BWR_PACRD_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP7 field. */
+#define AIPS_RD_PACRD_WP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP7_MASK) >> AIPS_PACRD_WP7_SHIFT)
+#define AIPS_BRD_PACRD_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRD_WP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP7_MASK, AIPS_PACRD_WP7(value)))
+#define AIPS_BWR_PACRD_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP7 field. */
+#define AIPS_RD_PACRD_SP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP7_MASK) >> AIPS_PACRD_SP7_SHIFT)
+#define AIPS_BRD_PACRD_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRD_SP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP7_MASK, AIPS_PACRD_SP7(value)))
+#define AIPS_BWR_PACRD_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP6 field. */
+#define AIPS_RD_PACRD_TP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP6_MASK) >> AIPS_PACRD_TP6_SHIFT)
+#define AIPS_BRD_PACRD_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRD_TP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP6_MASK, AIPS_PACRD_TP6(value)))
+#define AIPS_BWR_PACRD_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP6 field. */
+#define AIPS_RD_PACRD_WP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP6_MASK) >> AIPS_PACRD_WP6_SHIFT)
+#define AIPS_BRD_PACRD_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRD_WP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP6_MASK, AIPS_PACRD_WP6(value)))
+#define AIPS_BWR_PACRD_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP6 field. */
+#define AIPS_RD_PACRD_SP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP6_MASK) >> AIPS_PACRD_SP6_SHIFT)
+#define AIPS_BRD_PACRD_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRD_SP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP6_MASK, AIPS_PACRD_SP6(value)))
+#define AIPS_BWR_PACRD_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP5 field. */
+#define AIPS_RD_PACRD_TP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP5_MASK) >> AIPS_PACRD_TP5_SHIFT)
+#define AIPS_BRD_PACRD_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRD_TP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP5_MASK, AIPS_PACRD_TP5(value)))
+#define AIPS_BWR_PACRD_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP5 field. */
+#define AIPS_RD_PACRD_WP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP5_MASK) >> AIPS_PACRD_WP5_SHIFT)
+#define AIPS_BRD_PACRD_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRD_WP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP5_MASK, AIPS_PACRD_WP5(value)))
+#define AIPS_BWR_PACRD_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP5 field. */
+#define AIPS_RD_PACRD_SP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP5_MASK) >> AIPS_PACRD_SP5_SHIFT)
+#define AIPS_BRD_PACRD_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRD_SP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP5_MASK, AIPS_PACRD_SP5(value)))
+#define AIPS_BWR_PACRD_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP4 field. */
+#define AIPS_RD_PACRD_TP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP4_MASK) >> AIPS_PACRD_TP4_SHIFT)
+#define AIPS_BRD_PACRD_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRD_TP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP4_MASK, AIPS_PACRD_TP4(value)))
+#define AIPS_BWR_PACRD_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP4 field. */
+#define AIPS_RD_PACRD_WP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP4_MASK) >> AIPS_PACRD_WP4_SHIFT)
+#define AIPS_BRD_PACRD_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRD_WP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP4_MASK, AIPS_PACRD_WP4(value)))
+#define AIPS_BWR_PACRD_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP4 field. */
+#define AIPS_RD_PACRD_SP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP4_MASK) >> AIPS_PACRD_SP4_SHIFT)
+#define AIPS_BRD_PACRD_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRD_SP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP4_MASK, AIPS_PACRD_SP4(value)))
+#define AIPS_BWR_PACRD_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP3 field. */
+#define AIPS_RD_PACRD_TP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP3_MASK) >> AIPS_PACRD_TP3_SHIFT)
+#define AIPS_BRD_PACRD_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRD_TP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP3_MASK, AIPS_PACRD_TP3(value)))
+#define AIPS_BWR_PACRD_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP3 field. */
+#define AIPS_RD_PACRD_WP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP3_MASK) >> AIPS_PACRD_WP3_SHIFT)
+#define AIPS_BRD_PACRD_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRD_WP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP3_MASK, AIPS_PACRD_WP3(value)))
+#define AIPS_BWR_PACRD_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP3 field. */
+#define AIPS_RD_PACRD_SP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP3_MASK) >> AIPS_PACRD_SP3_SHIFT)
+#define AIPS_BRD_PACRD_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRD_SP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP3_MASK, AIPS_PACRD_SP3(value)))
+#define AIPS_BWR_PACRD_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP2 field. */
+#define AIPS_RD_PACRD_TP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP2_MASK) >> AIPS_PACRD_TP2_SHIFT)
+#define AIPS_BRD_PACRD_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRD_TP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP2_MASK, AIPS_PACRD_TP2(value)))
+#define AIPS_BWR_PACRD_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP2 field. */
+#define AIPS_RD_PACRD_WP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP2_MASK) >> AIPS_PACRD_WP2_SHIFT)
+#define AIPS_BRD_PACRD_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRD_WP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP2_MASK, AIPS_PACRD_WP2(value)))
+#define AIPS_BWR_PACRD_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP2 field. */
+#define AIPS_RD_PACRD_SP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP2_MASK) >> AIPS_PACRD_SP2_SHIFT)
+#define AIPS_BRD_PACRD_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRD_SP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP2_MASK, AIPS_PACRD_SP2(value)))
+#define AIPS_BWR_PACRD_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP1 field. */
+#define AIPS_RD_PACRD_TP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP1_MASK) >> AIPS_PACRD_TP1_SHIFT)
+#define AIPS_BRD_PACRD_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRD_TP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP1_MASK, AIPS_PACRD_TP1(value)))
+#define AIPS_BWR_PACRD_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP1 field. */
+#define AIPS_RD_PACRD_WP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP1_MASK) >> AIPS_PACRD_WP1_SHIFT)
+#define AIPS_BRD_PACRD_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRD_WP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP1_MASK, AIPS_PACRD_WP1(value)))
+#define AIPS_BWR_PACRD_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP1 field. */
+#define AIPS_RD_PACRD_SP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP1_MASK) >> AIPS_PACRD_SP1_SHIFT)
+#define AIPS_BRD_PACRD_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRD_SP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP1_MASK, AIPS_PACRD_SP1(value)))
+#define AIPS_BWR_PACRD_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP0 field. */
+#define AIPS_RD_PACRD_TP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP0_MASK) >> AIPS_PACRD_TP0_SHIFT)
+#define AIPS_BRD_PACRD_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRD_TP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP0_MASK, AIPS_PACRD_TP0(value)))
+#define AIPS_BWR_PACRD_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP0 field. */
+#define AIPS_RD_PACRD_WP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP0_MASK) >> AIPS_PACRD_WP0_SHIFT)
+#define AIPS_BRD_PACRD_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRD_WP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP0_MASK, AIPS_PACRD_WP0(value)))
+#define AIPS_BWR_PACRD_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP0 field. */
+#define AIPS_RD_PACRD_SP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP0_MASK) >> AIPS_PACRD_SP0_SHIFT)
+#define AIPS_BRD_PACRD_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRD_SP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP0_MASK, AIPS_PACRD_SP0(value)))
+#define AIPS_BWR_PACRD_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRE - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRE - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRE register
+ */
+/*@{*/
+#define AIPS_RD_PACRE(base)      (AIPS_PACRE_REG(base))
+#define AIPS_WR_PACRE(base, value) (AIPS_PACRE_REG(base) = (value))
+#define AIPS_RMW_PACRE(base, mask, value) (AIPS_WR_PACRE(base, (AIPS_RD_PACRE(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) |  (value)))
+#define AIPS_CLR_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) & ~(value)))
+#define AIPS_TOG_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRE bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRE, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP7 field. */
+#define AIPS_RD_PACRE_TP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP7_MASK) >> AIPS_PACRE_TP7_SHIFT)
+#define AIPS_BRD_PACRE_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRE_TP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP7_MASK, AIPS_PACRE_TP7(value)))
+#define AIPS_BWR_PACRE_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP7 field. */
+#define AIPS_RD_PACRE_WP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP7_MASK) >> AIPS_PACRE_WP7_SHIFT)
+#define AIPS_BRD_PACRE_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRE_WP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP7_MASK, AIPS_PACRE_WP7(value)))
+#define AIPS_BWR_PACRE_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP7 field. */
+#define AIPS_RD_PACRE_SP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP7_MASK) >> AIPS_PACRE_SP7_SHIFT)
+#define AIPS_BRD_PACRE_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRE_SP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP7_MASK, AIPS_PACRE_SP7(value)))
+#define AIPS_BWR_PACRE_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP6 field. */
+#define AIPS_RD_PACRE_TP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP6_MASK) >> AIPS_PACRE_TP6_SHIFT)
+#define AIPS_BRD_PACRE_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRE_TP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP6_MASK, AIPS_PACRE_TP6(value)))
+#define AIPS_BWR_PACRE_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP6 field. */
+#define AIPS_RD_PACRE_WP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP6_MASK) >> AIPS_PACRE_WP6_SHIFT)
+#define AIPS_BRD_PACRE_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRE_WP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP6_MASK, AIPS_PACRE_WP6(value)))
+#define AIPS_BWR_PACRE_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP6 field. */
+#define AIPS_RD_PACRE_SP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP6_MASK) >> AIPS_PACRE_SP6_SHIFT)
+#define AIPS_BRD_PACRE_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRE_SP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP6_MASK, AIPS_PACRE_SP6(value)))
+#define AIPS_BWR_PACRE_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP5 field. */
+#define AIPS_RD_PACRE_TP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP5_MASK) >> AIPS_PACRE_TP5_SHIFT)
+#define AIPS_BRD_PACRE_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRE_TP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP5_MASK, AIPS_PACRE_TP5(value)))
+#define AIPS_BWR_PACRE_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP5 field. */
+#define AIPS_RD_PACRE_WP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP5_MASK) >> AIPS_PACRE_WP5_SHIFT)
+#define AIPS_BRD_PACRE_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRE_WP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP5_MASK, AIPS_PACRE_WP5(value)))
+#define AIPS_BWR_PACRE_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP5 field. */
+#define AIPS_RD_PACRE_SP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP5_MASK) >> AIPS_PACRE_SP5_SHIFT)
+#define AIPS_BRD_PACRE_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRE_SP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP5_MASK, AIPS_PACRE_SP5(value)))
+#define AIPS_BWR_PACRE_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP4 field. */
+#define AIPS_RD_PACRE_TP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP4_MASK) >> AIPS_PACRE_TP4_SHIFT)
+#define AIPS_BRD_PACRE_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRE_TP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP4_MASK, AIPS_PACRE_TP4(value)))
+#define AIPS_BWR_PACRE_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP4 field. */
+#define AIPS_RD_PACRE_WP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP4_MASK) >> AIPS_PACRE_WP4_SHIFT)
+#define AIPS_BRD_PACRE_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRE_WP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP4_MASK, AIPS_PACRE_WP4(value)))
+#define AIPS_BWR_PACRE_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP4 field. */
+#define AIPS_RD_PACRE_SP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP4_MASK) >> AIPS_PACRE_SP4_SHIFT)
+#define AIPS_BRD_PACRE_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRE_SP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP4_MASK, AIPS_PACRE_SP4(value)))
+#define AIPS_BWR_PACRE_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP3 field. */
+#define AIPS_RD_PACRE_TP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP3_MASK) >> AIPS_PACRE_TP3_SHIFT)
+#define AIPS_BRD_PACRE_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRE_TP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP3_MASK, AIPS_PACRE_TP3(value)))
+#define AIPS_BWR_PACRE_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP3 field. */
+#define AIPS_RD_PACRE_WP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP3_MASK) >> AIPS_PACRE_WP3_SHIFT)
+#define AIPS_BRD_PACRE_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRE_WP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP3_MASK, AIPS_PACRE_WP3(value)))
+#define AIPS_BWR_PACRE_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP3 field. */
+#define AIPS_RD_PACRE_SP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP3_MASK) >> AIPS_PACRE_SP3_SHIFT)
+#define AIPS_BRD_PACRE_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRE_SP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP3_MASK, AIPS_PACRE_SP3(value)))
+#define AIPS_BWR_PACRE_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP2 field. */
+#define AIPS_RD_PACRE_TP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP2_MASK) >> AIPS_PACRE_TP2_SHIFT)
+#define AIPS_BRD_PACRE_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRE_TP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP2_MASK, AIPS_PACRE_TP2(value)))
+#define AIPS_BWR_PACRE_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP2 field. */
+#define AIPS_RD_PACRE_WP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP2_MASK) >> AIPS_PACRE_WP2_SHIFT)
+#define AIPS_BRD_PACRE_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRE_WP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP2_MASK, AIPS_PACRE_WP2(value)))
+#define AIPS_BWR_PACRE_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP2 field. */
+#define AIPS_RD_PACRE_SP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP2_MASK) >> AIPS_PACRE_SP2_SHIFT)
+#define AIPS_BRD_PACRE_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRE_SP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP2_MASK, AIPS_PACRE_SP2(value)))
+#define AIPS_BWR_PACRE_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP1 field. */
+#define AIPS_RD_PACRE_TP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP1_MASK) >> AIPS_PACRE_TP1_SHIFT)
+#define AIPS_BRD_PACRE_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRE_TP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP1_MASK, AIPS_PACRE_TP1(value)))
+#define AIPS_BWR_PACRE_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP1 field. */
+#define AIPS_RD_PACRE_WP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP1_MASK) >> AIPS_PACRE_WP1_SHIFT)
+#define AIPS_BRD_PACRE_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRE_WP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP1_MASK, AIPS_PACRE_WP1(value)))
+#define AIPS_BWR_PACRE_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP1 field. */
+#define AIPS_RD_PACRE_SP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP1_MASK) >> AIPS_PACRE_SP1_SHIFT)
+#define AIPS_BRD_PACRE_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRE_SP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP1_MASK, AIPS_PACRE_SP1(value)))
+#define AIPS_BWR_PACRE_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP0 field. */
+#define AIPS_RD_PACRE_TP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP0_MASK) >> AIPS_PACRE_TP0_SHIFT)
+#define AIPS_BRD_PACRE_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRE_TP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP0_MASK, AIPS_PACRE_TP0(value)))
+#define AIPS_BWR_PACRE_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP0 field. */
+#define AIPS_RD_PACRE_WP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP0_MASK) >> AIPS_PACRE_WP0_SHIFT)
+#define AIPS_BRD_PACRE_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRE_WP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP0_MASK, AIPS_PACRE_WP0(value)))
+#define AIPS_BWR_PACRE_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP0 field. */
+#define AIPS_RD_PACRE_SP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP0_MASK) >> AIPS_PACRE_SP0_SHIFT)
+#define AIPS_BRD_PACRE_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRE_SP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP0_MASK, AIPS_PACRE_SP0(value)))
+#define AIPS_BWR_PACRE_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRF - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRF - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRF register
+ */
+/*@{*/
+#define AIPS_RD_PACRF(base)      (AIPS_PACRF_REG(base))
+#define AIPS_WR_PACRF(base, value) (AIPS_PACRF_REG(base) = (value))
+#define AIPS_RMW_PACRF(base, mask, value) (AIPS_WR_PACRF(base, (AIPS_RD_PACRF(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) |  (value)))
+#define AIPS_CLR_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) & ~(value)))
+#define AIPS_TOG_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRF bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRF, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP7 field. */
+#define AIPS_RD_PACRF_TP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP7_MASK) >> AIPS_PACRF_TP7_SHIFT)
+#define AIPS_BRD_PACRF_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRF_TP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP7_MASK, AIPS_PACRF_TP7(value)))
+#define AIPS_BWR_PACRF_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP7 field. */
+#define AIPS_RD_PACRF_WP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP7_MASK) >> AIPS_PACRF_WP7_SHIFT)
+#define AIPS_BRD_PACRF_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRF_WP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP7_MASK, AIPS_PACRF_WP7(value)))
+#define AIPS_BWR_PACRF_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP7 field. */
+#define AIPS_RD_PACRF_SP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP7_MASK) >> AIPS_PACRF_SP7_SHIFT)
+#define AIPS_BRD_PACRF_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRF_SP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP7_MASK, AIPS_PACRF_SP7(value)))
+#define AIPS_BWR_PACRF_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP6 field. */
+#define AIPS_RD_PACRF_TP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP6_MASK) >> AIPS_PACRF_TP6_SHIFT)
+#define AIPS_BRD_PACRF_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRF_TP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP6_MASK, AIPS_PACRF_TP6(value)))
+#define AIPS_BWR_PACRF_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP6 field. */
+#define AIPS_RD_PACRF_WP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP6_MASK) >> AIPS_PACRF_WP6_SHIFT)
+#define AIPS_BRD_PACRF_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRF_WP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP6_MASK, AIPS_PACRF_WP6(value)))
+#define AIPS_BWR_PACRF_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP6 field. */
+#define AIPS_RD_PACRF_SP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP6_MASK) >> AIPS_PACRF_SP6_SHIFT)
+#define AIPS_BRD_PACRF_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRF_SP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP6_MASK, AIPS_PACRF_SP6(value)))
+#define AIPS_BWR_PACRF_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP5 field. */
+#define AIPS_RD_PACRF_TP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP5_MASK) >> AIPS_PACRF_TP5_SHIFT)
+#define AIPS_BRD_PACRF_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRF_TP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP5_MASK, AIPS_PACRF_TP5(value)))
+#define AIPS_BWR_PACRF_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP5 field. */
+#define AIPS_RD_PACRF_WP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP5_MASK) >> AIPS_PACRF_WP5_SHIFT)
+#define AIPS_BRD_PACRF_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRF_WP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP5_MASK, AIPS_PACRF_WP5(value)))
+#define AIPS_BWR_PACRF_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP5 field. */
+#define AIPS_RD_PACRF_SP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP5_MASK) >> AIPS_PACRF_SP5_SHIFT)
+#define AIPS_BRD_PACRF_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRF_SP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP5_MASK, AIPS_PACRF_SP5(value)))
+#define AIPS_BWR_PACRF_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP4 field. */
+#define AIPS_RD_PACRF_TP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP4_MASK) >> AIPS_PACRF_TP4_SHIFT)
+#define AIPS_BRD_PACRF_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRF_TP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP4_MASK, AIPS_PACRF_TP4(value)))
+#define AIPS_BWR_PACRF_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP4 field. */
+#define AIPS_RD_PACRF_WP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP4_MASK) >> AIPS_PACRF_WP4_SHIFT)
+#define AIPS_BRD_PACRF_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRF_WP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP4_MASK, AIPS_PACRF_WP4(value)))
+#define AIPS_BWR_PACRF_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP4 field. */
+#define AIPS_RD_PACRF_SP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP4_MASK) >> AIPS_PACRF_SP4_SHIFT)
+#define AIPS_BRD_PACRF_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRF_SP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP4_MASK, AIPS_PACRF_SP4(value)))
+#define AIPS_BWR_PACRF_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP3 field. */
+#define AIPS_RD_PACRF_TP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP3_MASK) >> AIPS_PACRF_TP3_SHIFT)
+#define AIPS_BRD_PACRF_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRF_TP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP3_MASK, AIPS_PACRF_TP3(value)))
+#define AIPS_BWR_PACRF_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP3 field. */
+#define AIPS_RD_PACRF_WP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP3_MASK) >> AIPS_PACRF_WP3_SHIFT)
+#define AIPS_BRD_PACRF_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRF_WP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP3_MASK, AIPS_PACRF_WP3(value)))
+#define AIPS_BWR_PACRF_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP3 field. */
+#define AIPS_RD_PACRF_SP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP3_MASK) >> AIPS_PACRF_SP3_SHIFT)
+#define AIPS_BRD_PACRF_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRF_SP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP3_MASK, AIPS_PACRF_SP3(value)))
+#define AIPS_BWR_PACRF_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP2 field. */
+#define AIPS_RD_PACRF_TP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP2_MASK) >> AIPS_PACRF_TP2_SHIFT)
+#define AIPS_BRD_PACRF_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRF_TP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP2_MASK, AIPS_PACRF_TP2(value)))
+#define AIPS_BWR_PACRF_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP2 field. */
+#define AIPS_RD_PACRF_WP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP2_MASK) >> AIPS_PACRF_WP2_SHIFT)
+#define AIPS_BRD_PACRF_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRF_WP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP2_MASK, AIPS_PACRF_WP2(value)))
+#define AIPS_BWR_PACRF_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP2 field. */
+#define AIPS_RD_PACRF_SP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP2_MASK) >> AIPS_PACRF_SP2_SHIFT)
+#define AIPS_BRD_PACRF_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRF_SP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP2_MASK, AIPS_PACRF_SP2(value)))
+#define AIPS_BWR_PACRF_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP1 field. */
+#define AIPS_RD_PACRF_TP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP1_MASK) >> AIPS_PACRF_TP1_SHIFT)
+#define AIPS_BRD_PACRF_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRF_TP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP1_MASK, AIPS_PACRF_TP1(value)))
+#define AIPS_BWR_PACRF_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP1 field. */
+#define AIPS_RD_PACRF_WP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP1_MASK) >> AIPS_PACRF_WP1_SHIFT)
+#define AIPS_BRD_PACRF_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRF_WP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP1_MASK, AIPS_PACRF_WP1(value)))
+#define AIPS_BWR_PACRF_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP1 field. */
+#define AIPS_RD_PACRF_SP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP1_MASK) >> AIPS_PACRF_SP1_SHIFT)
+#define AIPS_BRD_PACRF_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRF_SP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP1_MASK, AIPS_PACRF_SP1(value)))
+#define AIPS_BWR_PACRF_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP0 field. */
+#define AIPS_RD_PACRF_TP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP0_MASK) >> AIPS_PACRF_TP0_SHIFT)
+#define AIPS_BRD_PACRF_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRF_TP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP0_MASK, AIPS_PACRF_TP0(value)))
+#define AIPS_BWR_PACRF_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP0 field. */
+#define AIPS_RD_PACRF_WP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP0_MASK) >> AIPS_PACRF_WP0_SHIFT)
+#define AIPS_BRD_PACRF_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRF_WP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP0_MASK, AIPS_PACRF_WP0(value)))
+#define AIPS_BWR_PACRF_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP0 field. */
+#define AIPS_RD_PACRF_SP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP0_MASK) >> AIPS_PACRF_SP0_SHIFT)
+#define AIPS_BRD_PACRF_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRF_SP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP0_MASK, AIPS_PACRF_SP0(value)))
+#define AIPS_BWR_PACRF_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRG - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRG - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRG register
+ */
+/*@{*/
+#define AIPS_RD_PACRG(base)      (AIPS_PACRG_REG(base))
+#define AIPS_WR_PACRG(base, value) (AIPS_PACRG_REG(base) = (value))
+#define AIPS_RMW_PACRG(base, mask, value) (AIPS_WR_PACRG(base, (AIPS_RD_PACRG(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) |  (value)))
+#define AIPS_CLR_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) & ~(value)))
+#define AIPS_TOG_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRG bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRG, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP7 field. */
+#define AIPS_RD_PACRG_TP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP7_MASK) >> AIPS_PACRG_TP7_SHIFT)
+#define AIPS_BRD_PACRG_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRG_TP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP7_MASK, AIPS_PACRG_TP7(value)))
+#define AIPS_BWR_PACRG_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP7 field. */
+#define AIPS_RD_PACRG_WP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP7_MASK) >> AIPS_PACRG_WP7_SHIFT)
+#define AIPS_BRD_PACRG_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRG_WP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP7_MASK, AIPS_PACRG_WP7(value)))
+#define AIPS_BWR_PACRG_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP7 field. */
+#define AIPS_RD_PACRG_SP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP7_MASK) >> AIPS_PACRG_SP7_SHIFT)
+#define AIPS_BRD_PACRG_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRG_SP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP7_MASK, AIPS_PACRG_SP7(value)))
+#define AIPS_BWR_PACRG_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP6 field. */
+#define AIPS_RD_PACRG_TP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP6_MASK) >> AIPS_PACRG_TP6_SHIFT)
+#define AIPS_BRD_PACRG_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRG_TP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP6_MASK, AIPS_PACRG_TP6(value)))
+#define AIPS_BWR_PACRG_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP6 field. */
+#define AIPS_RD_PACRG_WP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP6_MASK) >> AIPS_PACRG_WP6_SHIFT)
+#define AIPS_BRD_PACRG_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRG_WP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP6_MASK, AIPS_PACRG_WP6(value)))
+#define AIPS_BWR_PACRG_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP6 field. */
+#define AIPS_RD_PACRG_SP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP6_MASK) >> AIPS_PACRG_SP6_SHIFT)
+#define AIPS_BRD_PACRG_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRG_SP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP6_MASK, AIPS_PACRG_SP6(value)))
+#define AIPS_BWR_PACRG_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP5 field. */
+#define AIPS_RD_PACRG_TP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP5_MASK) >> AIPS_PACRG_TP5_SHIFT)
+#define AIPS_BRD_PACRG_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRG_TP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP5_MASK, AIPS_PACRG_TP5(value)))
+#define AIPS_BWR_PACRG_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP5 field. */
+#define AIPS_RD_PACRG_WP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP5_MASK) >> AIPS_PACRG_WP5_SHIFT)
+#define AIPS_BRD_PACRG_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRG_WP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP5_MASK, AIPS_PACRG_WP5(value)))
+#define AIPS_BWR_PACRG_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP5 field. */
+#define AIPS_RD_PACRG_SP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP5_MASK) >> AIPS_PACRG_SP5_SHIFT)
+#define AIPS_BRD_PACRG_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRG_SP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP5_MASK, AIPS_PACRG_SP5(value)))
+#define AIPS_BWR_PACRG_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP4 field. */
+#define AIPS_RD_PACRG_TP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP4_MASK) >> AIPS_PACRG_TP4_SHIFT)
+#define AIPS_BRD_PACRG_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRG_TP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP4_MASK, AIPS_PACRG_TP4(value)))
+#define AIPS_BWR_PACRG_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP4 field. */
+#define AIPS_RD_PACRG_WP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP4_MASK) >> AIPS_PACRG_WP4_SHIFT)
+#define AIPS_BRD_PACRG_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRG_WP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP4_MASK, AIPS_PACRG_WP4(value)))
+#define AIPS_BWR_PACRG_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP4 field. */
+#define AIPS_RD_PACRG_SP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP4_MASK) >> AIPS_PACRG_SP4_SHIFT)
+#define AIPS_BRD_PACRG_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRG_SP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP4_MASK, AIPS_PACRG_SP4(value)))
+#define AIPS_BWR_PACRG_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP3 field. */
+#define AIPS_RD_PACRG_TP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP3_MASK) >> AIPS_PACRG_TP3_SHIFT)
+#define AIPS_BRD_PACRG_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRG_TP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP3_MASK, AIPS_PACRG_TP3(value)))
+#define AIPS_BWR_PACRG_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP3 field. */
+#define AIPS_RD_PACRG_WP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP3_MASK) >> AIPS_PACRG_WP3_SHIFT)
+#define AIPS_BRD_PACRG_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRG_WP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP3_MASK, AIPS_PACRG_WP3(value)))
+#define AIPS_BWR_PACRG_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP3 field. */
+#define AIPS_RD_PACRG_SP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP3_MASK) >> AIPS_PACRG_SP3_SHIFT)
+#define AIPS_BRD_PACRG_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRG_SP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP3_MASK, AIPS_PACRG_SP3(value)))
+#define AIPS_BWR_PACRG_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP2 field. */
+#define AIPS_RD_PACRG_TP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP2_MASK) >> AIPS_PACRG_TP2_SHIFT)
+#define AIPS_BRD_PACRG_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRG_TP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP2_MASK, AIPS_PACRG_TP2(value)))
+#define AIPS_BWR_PACRG_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP2 field. */
+#define AIPS_RD_PACRG_WP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP2_MASK) >> AIPS_PACRG_WP2_SHIFT)
+#define AIPS_BRD_PACRG_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRG_WP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP2_MASK, AIPS_PACRG_WP2(value)))
+#define AIPS_BWR_PACRG_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP2 field. */
+#define AIPS_RD_PACRG_SP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP2_MASK) >> AIPS_PACRG_SP2_SHIFT)
+#define AIPS_BRD_PACRG_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRG_SP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP2_MASK, AIPS_PACRG_SP2(value)))
+#define AIPS_BWR_PACRG_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP1 field. */
+#define AIPS_RD_PACRG_TP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP1_MASK) >> AIPS_PACRG_TP1_SHIFT)
+#define AIPS_BRD_PACRG_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRG_TP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP1_MASK, AIPS_PACRG_TP1(value)))
+#define AIPS_BWR_PACRG_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP1 field. */
+#define AIPS_RD_PACRG_WP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP1_MASK) >> AIPS_PACRG_WP1_SHIFT)
+#define AIPS_BRD_PACRG_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRG_WP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP1_MASK, AIPS_PACRG_WP1(value)))
+#define AIPS_BWR_PACRG_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP1 field. */
+#define AIPS_RD_PACRG_SP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP1_MASK) >> AIPS_PACRG_SP1_SHIFT)
+#define AIPS_BRD_PACRG_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRG_SP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP1_MASK, AIPS_PACRG_SP1(value)))
+#define AIPS_BWR_PACRG_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP0 field. */
+#define AIPS_RD_PACRG_TP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP0_MASK) >> AIPS_PACRG_TP0_SHIFT)
+#define AIPS_BRD_PACRG_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRG_TP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP0_MASK, AIPS_PACRG_TP0(value)))
+#define AIPS_BWR_PACRG_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP0 field. */
+#define AIPS_RD_PACRG_WP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP0_MASK) >> AIPS_PACRG_WP0_SHIFT)
+#define AIPS_BRD_PACRG_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRG_WP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP0_MASK, AIPS_PACRG_WP0(value)))
+#define AIPS_BWR_PACRG_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP0 field. */
+#define AIPS_RD_PACRG_SP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP0_MASK) >> AIPS_PACRG_SP0_SHIFT)
+#define AIPS_BRD_PACRG_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRG_SP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP0_MASK, AIPS_PACRG_SP0(value)))
+#define AIPS_BWR_PACRG_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRH - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRH - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRH register
+ */
+/*@{*/
+#define AIPS_RD_PACRH(base)      (AIPS_PACRH_REG(base))
+#define AIPS_WR_PACRH(base, value) (AIPS_PACRH_REG(base) = (value))
+#define AIPS_RMW_PACRH(base, mask, value) (AIPS_WR_PACRH(base, (AIPS_RD_PACRH(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) |  (value)))
+#define AIPS_CLR_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) & ~(value)))
+#define AIPS_TOG_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRH bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRH, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP7 field. */
+#define AIPS_RD_PACRH_TP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP7_MASK) >> AIPS_PACRH_TP7_SHIFT)
+#define AIPS_BRD_PACRH_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRH_TP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP7_MASK, AIPS_PACRH_TP7(value)))
+#define AIPS_BWR_PACRH_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP7 field. */
+#define AIPS_RD_PACRH_WP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP7_MASK) >> AIPS_PACRH_WP7_SHIFT)
+#define AIPS_BRD_PACRH_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRH_WP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP7_MASK, AIPS_PACRH_WP7(value)))
+#define AIPS_BWR_PACRH_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP7 field. */
+#define AIPS_RD_PACRH_SP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP7_MASK) >> AIPS_PACRH_SP7_SHIFT)
+#define AIPS_BRD_PACRH_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRH_SP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP7_MASK, AIPS_PACRH_SP7(value)))
+#define AIPS_BWR_PACRH_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP6 field. */
+#define AIPS_RD_PACRH_TP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP6_MASK) >> AIPS_PACRH_TP6_SHIFT)
+#define AIPS_BRD_PACRH_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRH_TP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP6_MASK, AIPS_PACRH_TP6(value)))
+#define AIPS_BWR_PACRH_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP6 field. */
+#define AIPS_RD_PACRH_WP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP6_MASK) >> AIPS_PACRH_WP6_SHIFT)
+#define AIPS_BRD_PACRH_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRH_WP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP6_MASK, AIPS_PACRH_WP6(value)))
+#define AIPS_BWR_PACRH_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP6 field. */
+#define AIPS_RD_PACRH_SP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP6_MASK) >> AIPS_PACRH_SP6_SHIFT)
+#define AIPS_BRD_PACRH_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRH_SP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP6_MASK, AIPS_PACRH_SP6(value)))
+#define AIPS_BWR_PACRH_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP5 field. */
+#define AIPS_RD_PACRH_TP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP5_MASK) >> AIPS_PACRH_TP5_SHIFT)
+#define AIPS_BRD_PACRH_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRH_TP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP5_MASK, AIPS_PACRH_TP5(value)))
+#define AIPS_BWR_PACRH_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP5 field. */
+#define AIPS_RD_PACRH_WP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP5_MASK) >> AIPS_PACRH_WP5_SHIFT)
+#define AIPS_BRD_PACRH_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRH_WP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP5_MASK, AIPS_PACRH_WP5(value)))
+#define AIPS_BWR_PACRH_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP5 field. */
+#define AIPS_RD_PACRH_SP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP5_MASK) >> AIPS_PACRH_SP5_SHIFT)
+#define AIPS_BRD_PACRH_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRH_SP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP5_MASK, AIPS_PACRH_SP5(value)))
+#define AIPS_BWR_PACRH_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP4 field. */
+#define AIPS_RD_PACRH_TP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP4_MASK) >> AIPS_PACRH_TP4_SHIFT)
+#define AIPS_BRD_PACRH_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRH_TP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP4_MASK, AIPS_PACRH_TP4(value)))
+#define AIPS_BWR_PACRH_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP4 field. */
+#define AIPS_RD_PACRH_WP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP4_MASK) >> AIPS_PACRH_WP4_SHIFT)
+#define AIPS_BRD_PACRH_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRH_WP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP4_MASK, AIPS_PACRH_WP4(value)))
+#define AIPS_BWR_PACRH_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP4 field. */
+#define AIPS_RD_PACRH_SP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP4_MASK) >> AIPS_PACRH_SP4_SHIFT)
+#define AIPS_BRD_PACRH_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRH_SP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP4_MASK, AIPS_PACRH_SP4(value)))
+#define AIPS_BWR_PACRH_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP3 field. */
+#define AIPS_RD_PACRH_TP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP3_MASK) >> AIPS_PACRH_TP3_SHIFT)
+#define AIPS_BRD_PACRH_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRH_TP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP3_MASK, AIPS_PACRH_TP3(value)))
+#define AIPS_BWR_PACRH_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP3 field. */
+#define AIPS_RD_PACRH_WP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP3_MASK) >> AIPS_PACRH_WP3_SHIFT)
+#define AIPS_BRD_PACRH_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRH_WP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP3_MASK, AIPS_PACRH_WP3(value)))
+#define AIPS_BWR_PACRH_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP3 field. */
+#define AIPS_RD_PACRH_SP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP3_MASK) >> AIPS_PACRH_SP3_SHIFT)
+#define AIPS_BRD_PACRH_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRH_SP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP3_MASK, AIPS_PACRH_SP3(value)))
+#define AIPS_BWR_PACRH_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP2 field. */
+#define AIPS_RD_PACRH_TP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP2_MASK) >> AIPS_PACRH_TP2_SHIFT)
+#define AIPS_BRD_PACRH_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRH_TP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP2_MASK, AIPS_PACRH_TP2(value)))
+#define AIPS_BWR_PACRH_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP2 field. */
+#define AIPS_RD_PACRH_WP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP2_MASK) >> AIPS_PACRH_WP2_SHIFT)
+#define AIPS_BRD_PACRH_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRH_WP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP2_MASK, AIPS_PACRH_WP2(value)))
+#define AIPS_BWR_PACRH_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP2 field. */
+#define AIPS_RD_PACRH_SP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP2_MASK) >> AIPS_PACRH_SP2_SHIFT)
+#define AIPS_BRD_PACRH_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRH_SP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP2_MASK, AIPS_PACRH_SP2(value)))
+#define AIPS_BWR_PACRH_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP1 field. */
+#define AIPS_RD_PACRH_TP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP1_MASK) >> AIPS_PACRH_TP1_SHIFT)
+#define AIPS_BRD_PACRH_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRH_TP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP1_MASK, AIPS_PACRH_TP1(value)))
+#define AIPS_BWR_PACRH_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP1 field. */
+#define AIPS_RD_PACRH_WP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP1_MASK) >> AIPS_PACRH_WP1_SHIFT)
+#define AIPS_BRD_PACRH_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRH_WP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP1_MASK, AIPS_PACRH_WP1(value)))
+#define AIPS_BWR_PACRH_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP1 field. */
+#define AIPS_RD_PACRH_SP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP1_MASK) >> AIPS_PACRH_SP1_SHIFT)
+#define AIPS_BRD_PACRH_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRH_SP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP1_MASK, AIPS_PACRH_SP1(value)))
+#define AIPS_BWR_PACRH_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP0 field. */
+#define AIPS_RD_PACRH_TP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP0_MASK) >> AIPS_PACRH_TP0_SHIFT)
+#define AIPS_BRD_PACRH_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRH_TP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP0_MASK, AIPS_PACRH_TP0(value)))
+#define AIPS_BWR_PACRH_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP0 field. */
+#define AIPS_RD_PACRH_WP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP0_MASK) >> AIPS_PACRH_WP0_SHIFT)
+#define AIPS_BRD_PACRH_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRH_WP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP0_MASK, AIPS_PACRH_WP0(value)))
+#define AIPS_BWR_PACRH_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP0 field. */
+#define AIPS_RD_PACRH_SP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP0_MASK) >> AIPS_PACRH_SP0_SHIFT)
+#define AIPS_BRD_PACRH_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRH_SP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP0_MASK, AIPS_PACRH_SP0(value)))
+#define AIPS_BWR_PACRH_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRI - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRI - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRI register
+ */
+/*@{*/
+#define AIPS_RD_PACRI(base)      (AIPS_PACRI_REG(base))
+#define AIPS_WR_PACRI(base, value) (AIPS_PACRI_REG(base) = (value))
+#define AIPS_RMW_PACRI(base, mask, value) (AIPS_WR_PACRI(base, (AIPS_RD_PACRI(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) |  (value)))
+#define AIPS_CLR_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) & ~(value)))
+#define AIPS_TOG_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRI bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRI, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP7 field. */
+#define AIPS_RD_PACRI_TP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP7_MASK) >> AIPS_PACRI_TP7_SHIFT)
+#define AIPS_BRD_PACRI_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRI_TP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP7_MASK, AIPS_PACRI_TP7(value)))
+#define AIPS_BWR_PACRI_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP7 field. */
+#define AIPS_RD_PACRI_WP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP7_MASK) >> AIPS_PACRI_WP7_SHIFT)
+#define AIPS_BRD_PACRI_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRI_WP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP7_MASK, AIPS_PACRI_WP7(value)))
+#define AIPS_BWR_PACRI_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP7 field. */
+#define AIPS_RD_PACRI_SP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP7_MASK) >> AIPS_PACRI_SP7_SHIFT)
+#define AIPS_BRD_PACRI_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRI_SP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP7_MASK, AIPS_PACRI_SP7(value)))
+#define AIPS_BWR_PACRI_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP6 field. */
+#define AIPS_RD_PACRI_TP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP6_MASK) >> AIPS_PACRI_TP6_SHIFT)
+#define AIPS_BRD_PACRI_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRI_TP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP6_MASK, AIPS_PACRI_TP6(value)))
+#define AIPS_BWR_PACRI_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP6 field. */
+#define AIPS_RD_PACRI_WP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP6_MASK) >> AIPS_PACRI_WP6_SHIFT)
+#define AIPS_BRD_PACRI_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRI_WP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP6_MASK, AIPS_PACRI_WP6(value)))
+#define AIPS_BWR_PACRI_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP6 field. */
+#define AIPS_RD_PACRI_SP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP6_MASK) >> AIPS_PACRI_SP6_SHIFT)
+#define AIPS_BRD_PACRI_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRI_SP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP6_MASK, AIPS_PACRI_SP6(value)))
+#define AIPS_BWR_PACRI_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP5 field. */
+#define AIPS_RD_PACRI_TP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP5_MASK) >> AIPS_PACRI_TP5_SHIFT)
+#define AIPS_BRD_PACRI_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRI_TP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP5_MASK, AIPS_PACRI_TP5(value)))
+#define AIPS_BWR_PACRI_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP5 field. */
+#define AIPS_RD_PACRI_WP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP5_MASK) >> AIPS_PACRI_WP5_SHIFT)
+#define AIPS_BRD_PACRI_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRI_WP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP5_MASK, AIPS_PACRI_WP5(value)))
+#define AIPS_BWR_PACRI_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP5 field. */
+#define AIPS_RD_PACRI_SP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP5_MASK) >> AIPS_PACRI_SP5_SHIFT)
+#define AIPS_BRD_PACRI_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRI_SP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP5_MASK, AIPS_PACRI_SP5(value)))
+#define AIPS_BWR_PACRI_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP4 field. */
+#define AIPS_RD_PACRI_TP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP4_MASK) >> AIPS_PACRI_TP4_SHIFT)
+#define AIPS_BRD_PACRI_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRI_TP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP4_MASK, AIPS_PACRI_TP4(value)))
+#define AIPS_BWR_PACRI_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP4 field. */
+#define AIPS_RD_PACRI_WP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP4_MASK) >> AIPS_PACRI_WP4_SHIFT)
+#define AIPS_BRD_PACRI_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRI_WP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP4_MASK, AIPS_PACRI_WP4(value)))
+#define AIPS_BWR_PACRI_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP4 field. */
+#define AIPS_RD_PACRI_SP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP4_MASK) >> AIPS_PACRI_SP4_SHIFT)
+#define AIPS_BRD_PACRI_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRI_SP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP4_MASK, AIPS_PACRI_SP4(value)))
+#define AIPS_BWR_PACRI_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP3 field. */
+#define AIPS_RD_PACRI_TP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP3_MASK) >> AIPS_PACRI_TP3_SHIFT)
+#define AIPS_BRD_PACRI_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRI_TP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP3_MASK, AIPS_PACRI_TP3(value)))
+#define AIPS_BWR_PACRI_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP3 field. */
+#define AIPS_RD_PACRI_WP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP3_MASK) >> AIPS_PACRI_WP3_SHIFT)
+#define AIPS_BRD_PACRI_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRI_WP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP3_MASK, AIPS_PACRI_WP3(value)))
+#define AIPS_BWR_PACRI_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP3 field. */
+#define AIPS_RD_PACRI_SP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP3_MASK) >> AIPS_PACRI_SP3_SHIFT)
+#define AIPS_BRD_PACRI_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRI_SP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP3_MASK, AIPS_PACRI_SP3(value)))
+#define AIPS_BWR_PACRI_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP2 field. */
+#define AIPS_RD_PACRI_TP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP2_MASK) >> AIPS_PACRI_TP2_SHIFT)
+#define AIPS_BRD_PACRI_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRI_TP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP2_MASK, AIPS_PACRI_TP2(value)))
+#define AIPS_BWR_PACRI_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP2 field. */
+#define AIPS_RD_PACRI_WP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP2_MASK) >> AIPS_PACRI_WP2_SHIFT)
+#define AIPS_BRD_PACRI_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRI_WP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP2_MASK, AIPS_PACRI_WP2(value)))
+#define AIPS_BWR_PACRI_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP2 field. */
+#define AIPS_RD_PACRI_SP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP2_MASK) >> AIPS_PACRI_SP2_SHIFT)
+#define AIPS_BRD_PACRI_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRI_SP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP2_MASK, AIPS_PACRI_SP2(value)))
+#define AIPS_BWR_PACRI_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP1 field. */
+#define AIPS_RD_PACRI_TP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP1_MASK) >> AIPS_PACRI_TP1_SHIFT)
+#define AIPS_BRD_PACRI_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRI_TP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP1_MASK, AIPS_PACRI_TP1(value)))
+#define AIPS_BWR_PACRI_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP1 field. */
+#define AIPS_RD_PACRI_WP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP1_MASK) >> AIPS_PACRI_WP1_SHIFT)
+#define AIPS_BRD_PACRI_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRI_WP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP1_MASK, AIPS_PACRI_WP1(value)))
+#define AIPS_BWR_PACRI_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP1 field. */
+#define AIPS_RD_PACRI_SP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP1_MASK) >> AIPS_PACRI_SP1_SHIFT)
+#define AIPS_BRD_PACRI_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRI_SP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP1_MASK, AIPS_PACRI_SP1(value)))
+#define AIPS_BWR_PACRI_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP0 field. */
+#define AIPS_RD_PACRI_TP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP0_MASK) >> AIPS_PACRI_TP0_SHIFT)
+#define AIPS_BRD_PACRI_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRI_TP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP0_MASK, AIPS_PACRI_TP0(value)))
+#define AIPS_BWR_PACRI_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP0 field. */
+#define AIPS_RD_PACRI_WP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP0_MASK) >> AIPS_PACRI_WP0_SHIFT)
+#define AIPS_BRD_PACRI_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRI_WP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP0_MASK, AIPS_PACRI_WP0(value)))
+#define AIPS_BWR_PACRI_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP0 field. */
+#define AIPS_RD_PACRI_SP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP0_MASK) >> AIPS_PACRI_SP0_SHIFT)
+#define AIPS_BRD_PACRI_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRI_SP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP0_MASK, AIPS_PACRI_SP0(value)))
+#define AIPS_BWR_PACRI_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRJ - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRJ - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRJ register
+ */
+/*@{*/
+#define AIPS_RD_PACRJ(base)      (AIPS_PACRJ_REG(base))
+#define AIPS_WR_PACRJ(base, value) (AIPS_PACRJ_REG(base) = (value))
+#define AIPS_RMW_PACRJ(base, mask, value) (AIPS_WR_PACRJ(base, (AIPS_RD_PACRJ(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) |  (value)))
+#define AIPS_CLR_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) & ~(value)))
+#define AIPS_TOG_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRJ bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRJ, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP7 field. */
+#define AIPS_RD_PACRJ_TP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP7_MASK) >> AIPS_PACRJ_TP7_SHIFT)
+#define AIPS_BRD_PACRJ_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRJ_TP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP7_MASK, AIPS_PACRJ_TP7(value)))
+#define AIPS_BWR_PACRJ_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP7 field. */
+#define AIPS_RD_PACRJ_WP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP7_MASK) >> AIPS_PACRJ_WP7_SHIFT)
+#define AIPS_BRD_PACRJ_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRJ_WP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP7_MASK, AIPS_PACRJ_WP7(value)))
+#define AIPS_BWR_PACRJ_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP7 field. */
+#define AIPS_RD_PACRJ_SP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP7_MASK) >> AIPS_PACRJ_SP7_SHIFT)
+#define AIPS_BRD_PACRJ_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRJ_SP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP7_MASK, AIPS_PACRJ_SP7(value)))
+#define AIPS_BWR_PACRJ_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP6 field. */
+#define AIPS_RD_PACRJ_TP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP6_MASK) >> AIPS_PACRJ_TP6_SHIFT)
+#define AIPS_BRD_PACRJ_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRJ_TP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP6_MASK, AIPS_PACRJ_TP6(value)))
+#define AIPS_BWR_PACRJ_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP6 field. */
+#define AIPS_RD_PACRJ_WP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP6_MASK) >> AIPS_PACRJ_WP6_SHIFT)
+#define AIPS_BRD_PACRJ_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRJ_WP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP6_MASK, AIPS_PACRJ_WP6(value)))
+#define AIPS_BWR_PACRJ_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP6 field. */
+#define AIPS_RD_PACRJ_SP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP6_MASK) >> AIPS_PACRJ_SP6_SHIFT)
+#define AIPS_BRD_PACRJ_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRJ_SP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP6_MASK, AIPS_PACRJ_SP6(value)))
+#define AIPS_BWR_PACRJ_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP5 field. */
+#define AIPS_RD_PACRJ_TP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP5_MASK) >> AIPS_PACRJ_TP5_SHIFT)
+#define AIPS_BRD_PACRJ_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRJ_TP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP5_MASK, AIPS_PACRJ_TP5(value)))
+#define AIPS_BWR_PACRJ_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP5 field. */
+#define AIPS_RD_PACRJ_WP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP5_MASK) >> AIPS_PACRJ_WP5_SHIFT)
+#define AIPS_BRD_PACRJ_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRJ_WP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP5_MASK, AIPS_PACRJ_WP5(value)))
+#define AIPS_BWR_PACRJ_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP5 field. */
+#define AIPS_RD_PACRJ_SP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP5_MASK) >> AIPS_PACRJ_SP5_SHIFT)
+#define AIPS_BRD_PACRJ_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRJ_SP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP5_MASK, AIPS_PACRJ_SP5(value)))
+#define AIPS_BWR_PACRJ_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP4 field. */
+#define AIPS_RD_PACRJ_TP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP4_MASK) >> AIPS_PACRJ_TP4_SHIFT)
+#define AIPS_BRD_PACRJ_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRJ_TP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP4_MASK, AIPS_PACRJ_TP4(value)))
+#define AIPS_BWR_PACRJ_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP4 field. */
+#define AIPS_RD_PACRJ_WP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP4_MASK) >> AIPS_PACRJ_WP4_SHIFT)
+#define AIPS_BRD_PACRJ_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRJ_WP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP4_MASK, AIPS_PACRJ_WP4(value)))
+#define AIPS_BWR_PACRJ_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP4 field. */
+#define AIPS_RD_PACRJ_SP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP4_MASK) >> AIPS_PACRJ_SP4_SHIFT)
+#define AIPS_BRD_PACRJ_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRJ_SP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP4_MASK, AIPS_PACRJ_SP4(value)))
+#define AIPS_BWR_PACRJ_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP3 field. */
+#define AIPS_RD_PACRJ_TP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP3_MASK) >> AIPS_PACRJ_TP3_SHIFT)
+#define AIPS_BRD_PACRJ_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRJ_TP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP3_MASK, AIPS_PACRJ_TP3(value)))
+#define AIPS_BWR_PACRJ_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP3 field. */
+#define AIPS_RD_PACRJ_WP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP3_MASK) >> AIPS_PACRJ_WP3_SHIFT)
+#define AIPS_BRD_PACRJ_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRJ_WP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP3_MASK, AIPS_PACRJ_WP3(value)))
+#define AIPS_BWR_PACRJ_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP3 field. */
+#define AIPS_RD_PACRJ_SP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP3_MASK) >> AIPS_PACRJ_SP3_SHIFT)
+#define AIPS_BRD_PACRJ_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRJ_SP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP3_MASK, AIPS_PACRJ_SP3(value)))
+#define AIPS_BWR_PACRJ_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP2 field. */
+#define AIPS_RD_PACRJ_TP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP2_MASK) >> AIPS_PACRJ_TP2_SHIFT)
+#define AIPS_BRD_PACRJ_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRJ_TP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP2_MASK, AIPS_PACRJ_TP2(value)))
+#define AIPS_BWR_PACRJ_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP2 field. */
+#define AIPS_RD_PACRJ_WP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP2_MASK) >> AIPS_PACRJ_WP2_SHIFT)
+#define AIPS_BRD_PACRJ_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRJ_WP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP2_MASK, AIPS_PACRJ_WP2(value)))
+#define AIPS_BWR_PACRJ_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP2 field. */
+#define AIPS_RD_PACRJ_SP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP2_MASK) >> AIPS_PACRJ_SP2_SHIFT)
+#define AIPS_BRD_PACRJ_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRJ_SP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP2_MASK, AIPS_PACRJ_SP2(value)))
+#define AIPS_BWR_PACRJ_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP1 field. */
+#define AIPS_RD_PACRJ_TP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP1_MASK) >> AIPS_PACRJ_TP1_SHIFT)
+#define AIPS_BRD_PACRJ_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRJ_TP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP1_MASK, AIPS_PACRJ_TP1(value)))
+#define AIPS_BWR_PACRJ_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP1 field. */
+#define AIPS_RD_PACRJ_WP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP1_MASK) >> AIPS_PACRJ_WP1_SHIFT)
+#define AIPS_BRD_PACRJ_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRJ_WP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP1_MASK, AIPS_PACRJ_WP1(value)))
+#define AIPS_BWR_PACRJ_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP1 field. */
+#define AIPS_RD_PACRJ_SP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP1_MASK) >> AIPS_PACRJ_SP1_SHIFT)
+#define AIPS_BRD_PACRJ_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRJ_SP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP1_MASK, AIPS_PACRJ_SP1(value)))
+#define AIPS_BWR_PACRJ_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP0 field. */
+#define AIPS_RD_PACRJ_TP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP0_MASK) >> AIPS_PACRJ_TP0_SHIFT)
+#define AIPS_BRD_PACRJ_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRJ_TP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP0_MASK, AIPS_PACRJ_TP0(value)))
+#define AIPS_BWR_PACRJ_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP0 field. */
+#define AIPS_RD_PACRJ_WP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP0_MASK) >> AIPS_PACRJ_WP0_SHIFT)
+#define AIPS_BRD_PACRJ_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRJ_WP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP0_MASK, AIPS_PACRJ_WP0(value)))
+#define AIPS_BWR_PACRJ_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP0 field. */
+#define AIPS_RD_PACRJ_SP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP0_MASK) >> AIPS_PACRJ_SP0_SHIFT)
+#define AIPS_BRD_PACRJ_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRJ_SP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP0_MASK, AIPS_PACRJ_SP0(value)))
+#define AIPS_BWR_PACRJ_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRK - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRK - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRK register
+ */
+/*@{*/
+#define AIPS_RD_PACRK(base)      (AIPS_PACRK_REG(base))
+#define AIPS_WR_PACRK(base, value) (AIPS_PACRK_REG(base) = (value))
+#define AIPS_RMW_PACRK(base, mask, value) (AIPS_WR_PACRK(base, (AIPS_RD_PACRK(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) |  (value)))
+#define AIPS_CLR_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) & ~(value)))
+#define AIPS_TOG_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRK bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRK, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP7 field. */
+#define AIPS_RD_PACRK_TP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP7_MASK) >> AIPS_PACRK_TP7_SHIFT)
+#define AIPS_BRD_PACRK_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRK_TP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP7_MASK, AIPS_PACRK_TP7(value)))
+#define AIPS_BWR_PACRK_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP7 field. */
+#define AIPS_RD_PACRK_WP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP7_MASK) >> AIPS_PACRK_WP7_SHIFT)
+#define AIPS_BRD_PACRK_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRK_WP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP7_MASK, AIPS_PACRK_WP7(value)))
+#define AIPS_BWR_PACRK_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP7 field. */
+#define AIPS_RD_PACRK_SP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP7_MASK) >> AIPS_PACRK_SP7_SHIFT)
+#define AIPS_BRD_PACRK_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRK_SP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP7_MASK, AIPS_PACRK_SP7(value)))
+#define AIPS_BWR_PACRK_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP6 field. */
+#define AIPS_RD_PACRK_TP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP6_MASK) >> AIPS_PACRK_TP6_SHIFT)
+#define AIPS_BRD_PACRK_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRK_TP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP6_MASK, AIPS_PACRK_TP6(value)))
+#define AIPS_BWR_PACRK_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP6 field. */
+#define AIPS_RD_PACRK_WP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP6_MASK) >> AIPS_PACRK_WP6_SHIFT)
+#define AIPS_BRD_PACRK_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRK_WP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP6_MASK, AIPS_PACRK_WP6(value)))
+#define AIPS_BWR_PACRK_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP6 field. */
+#define AIPS_RD_PACRK_SP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP6_MASK) >> AIPS_PACRK_SP6_SHIFT)
+#define AIPS_BRD_PACRK_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRK_SP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP6_MASK, AIPS_PACRK_SP6(value)))
+#define AIPS_BWR_PACRK_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP5 field. */
+#define AIPS_RD_PACRK_TP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP5_MASK) >> AIPS_PACRK_TP5_SHIFT)
+#define AIPS_BRD_PACRK_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRK_TP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP5_MASK, AIPS_PACRK_TP5(value)))
+#define AIPS_BWR_PACRK_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP5 field. */
+#define AIPS_RD_PACRK_WP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP5_MASK) >> AIPS_PACRK_WP5_SHIFT)
+#define AIPS_BRD_PACRK_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRK_WP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP5_MASK, AIPS_PACRK_WP5(value)))
+#define AIPS_BWR_PACRK_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP5 field. */
+#define AIPS_RD_PACRK_SP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP5_MASK) >> AIPS_PACRK_SP5_SHIFT)
+#define AIPS_BRD_PACRK_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRK_SP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP5_MASK, AIPS_PACRK_SP5(value)))
+#define AIPS_BWR_PACRK_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP4 field. */
+#define AIPS_RD_PACRK_TP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP4_MASK) >> AIPS_PACRK_TP4_SHIFT)
+#define AIPS_BRD_PACRK_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRK_TP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP4_MASK, AIPS_PACRK_TP4(value)))
+#define AIPS_BWR_PACRK_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP4 field. */
+#define AIPS_RD_PACRK_WP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP4_MASK) >> AIPS_PACRK_WP4_SHIFT)
+#define AIPS_BRD_PACRK_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRK_WP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP4_MASK, AIPS_PACRK_WP4(value)))
+#define AIPS_BWR_PACRK_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP4 field. */
+#define AIPS_RD_PACRK_SP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP4_MASK) >> AIPS_PACRK_SP4_SHIFT)
+#define AIPS_BRD_PACRK_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRK_SP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP4_MASK, AIPS_PACRK_SP4(value)))
+#define AIPS_BWR_PACRK_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP3 field. */
+#define AIPS_RD_PACRK_TP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP3_MASK) >> AIPS_PACRK_TP3_SHIFT)
+#define AIPS_BRD_PACRK_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRK_TP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP3_MASK, AIPS_PACRK_TP3(value)))
+#define AIPS_BWR_PACRK_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP3 field. */
+#define AIPS_RD_PACRK_WP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP3_MASK) >> AIPS_PACRK_WP3_SHIFT)
+#define AIPS_BRD_PACRK_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRK_WP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP3_MASK, AIPS_PACRK_WP3(value)))
+#define AIPS_BWR_PACRK_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP3 field. */
+#define AIPS_RD_PACRK_SP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP3_MASK) >> AIPS_PACRK_SP3_SHIFT)
+#define AIPS_BRD_PACRK_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRK_SP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP3_MASK, AIPS_PACRK_SP3(value)))
+#define AIPS_BWR_PACRK_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP2 field. */
+#define AIPS_RD_PACRK_TP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP2_MASK) >> AIPS_PACRK_TP2_SHIFT)
+#define AIPS_BRD_PACRK_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRK_TP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP2_MASK, AIPS_PACRK_TP2(value)))
+#define AIPS_BWR_PACRK_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP2 field. */
+#define AIPS_RD_PACRK_WP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP2_MASK) >> AIPS_PACRK_WP2_SHIFT)
+#define AIPS_BRD_PACRK_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRK_WP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP2_MASK, AIPS_PACRK_WP2(value)))
+#define AIPS_BWR_PACRK_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP2 field. */
+#define AIPS_RD_PACRK_SP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP2_MASK) >> AIPS_PACRK_SP2_SHIFT)
+#define AIPS_BRD_PACRK_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRK_SP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP2_MASK, AIPS_PACRK_SP2(value)))
+#define AIPS_BWR_PACRK_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP1 field. */
+#define AIPS_RD_PACRK_TP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP1_MASK) >> AIPS_PACRK_TP1_SHIFT)
+#define AIPS_BRD_PACRK_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRK_TP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP1_MASK, AIPS_PACRK_TP1(value)))
+#define AIPS_BWR_PACRK_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP1 field. */
+#define AIPS_RD_PACRK_WP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP1_MASK) >> AIPS_PACRK_WP1_SHIFT)
+#define AIPS_BRD_PACRK_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRK_WP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP1_MASK, AIPS_PACRK_WP1(value)))
+#define AIPS_BWR_PACRK_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP1 field. */
+#define AIPS_RD_PACRK_SP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP1_MASK) >> AIPS_PACRK_SP1_SHIFT)
+#define AIPS_BRD_PACRK_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRK_SP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP1_MASK, AIPS_PACRK_SP1(value)))
+#define AIPS_BWR_PACRK_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP0 field. */
+#define AIPS_RD_PACRK_TP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP0_MASK) >> AIPS_PACRK_TP0_SHIFT)
+#define AIPS_BRD_PACRK_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRK_TP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP0_MASK, AIPS_PACRK_TP0(value)))
+#define AIPS_BWR_PACRK_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP0 field. */
+#define AIPS_RD_PACRK_WP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP0_MASK) >> AIPS_PACRK_WP0_SHIFT)
+#define AIPS_BRD_PACRK_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRK_WP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP0_MASK, AIPS_PACRK_WP0(value)))
+#define AIPS_BWR_PACRK_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP0 field. */
+#define AIPS_RD_PACRK_SP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP0_MASK) >> AIPS_PACRK_SP0_SHIFT)
+#define AIPS_BRD_PACRK_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRK_SP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP0_MASK, AIPS_PACRK_SP0(value)))
+#define AIPS_BWR_PACRK_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRL - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRL - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRL register
+ */
+/*@{*/
+#define AIPS_RD_PACRL(base)      (AIPS_PACRL_REG(base))
+#define AIPS_WR_PACRL(base, value) (AIPS_PACRL_REG(base) = (value))
+#define AIPS_RMW_PACRL(base, mask, value) (AIPS_WR_PACRL(base, (AIPS_RD_PACRL(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) |  (value)))
+#define AIPS_CLR_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) & ~(value)))
+#define AIPS_TOG_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRL bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRL, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP7 field. */
+#define AIPS_RD_PACRL_TP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP7_MASK) >> AIPS_PACRL_TP7_SHIFT)
+#define AIPS_BRD_PACRL_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRL_TP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP7_MASK, AIPS_PACRL_TP7(value)))
+#define AIPS_BWR_PACRL_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP7 field. */
+#define AIPS_RD_PACRL_WP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP7_MASK) >> AIPS_PACRL_WP7_SHIFT)
+#define AIPS_BRD_PACRL_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRL_WP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP7_MASK, AIPS_PACRL_WP7(value)))
+#define AIPS_BWR_PACRL_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP7 field. */
+#define AIPS_RD_PACRL_SP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP7_MASK) >> AIPS_PACRL_SP7_SHIFT)
+#define AIPS_BRD_PACRL_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRL_SP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP7_MASK, AIPS_PACRL_SP7(value)))
+#define AIPS_BWR_PACRL_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP6 field. */
+#define AIPS_RD_PACRL_TP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP6_MASK) >> AIPS_PACRL_TP6_SHIFT)
+#define AIPS_BRD_PACRL_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRL_TP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP6_MASK, AIPS_PACRL_TP6(value)))
+#define AIPS_BWR_PACRL_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP6 field. */
+#define AIPS_RD_PACRL_WP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP6_MASK) >> AIPS_PACRL_WP6_SHIFT)
+#define AIPS_BRD_PACRL_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRL_WP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP6_MASK, AIPS_PACRL_WP6(value)))
+#define AIPS_BWR_PACRL_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP6 field. */
+#define AIPS_RD_PACRL_SP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP6_MASK) >> AIPS_PACRL_SP6_SHIFT)
+#define AIPS_BRD_PACRL_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRL_SP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP6_MASK, AIPS_PACRL_SP6(value)))
+#define AIPS_BWR_PACRL_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP5 field. */
+#define AIPS_RD_PACRL_TP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP5_MASK) >> AIPS_PACRL_TP5_SHIFT)
+#define AIPS_BRD_PACRL_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRL_TP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP5_MASK, AIPS_PACRL_TP5(value)))
+#define AIPS_BWR_PACRL_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP5 field. */
+#define AIPS_RD_PACRL_WP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP5_MASK) >> AIPS_PACRL_WP5_SHIFT)
+#define AIPS_BRD_PACRL_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRL_WP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP5_MASK, AIPS_PACRL_WP5(value)))
+#define AIPS_BWR_PACRL_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP5 field. */
+#define AIPS_RD_PACRL_SP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP5_MASK) >> AIPS_PACRL_SP5_SHIFT)
+#define AIPS_BRD_PACRL_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRL_SP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP5_MASK, AIPS_PACRL_SP5(value)))
+#define AIPS_BWR_PACRL_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP4 field. */
+#define AIPS_RD_PACRL_TP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP4_MASK) >> AIPS_PACRL_TP4_SHIFT)
+#define AIPS_BRD_PACRL_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRL_TP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP4_MASK, AIPS_PACRL_TP4(value)))
+#define AIPS_BWR_PACRL_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP4 field. */
+#define AIPS_RD_PACRL_WP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP4_MASK) >> AIPS_PACRL_WP4_SHIFT)
+#define AIPS_BRD_PACRL_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRL_WP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP4_MASK, AIPS_PACRL_WP4(value)))
+#define AIPS_BWR_PACRL_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP4 field. */
+#define AIPS_RD_PACRL_SP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP4_MASK) >> AIPS_PACRL_SP4_SHIFT)
+#define AIPS_BRD_PACRL_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRL_SP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP4_MASK, AIPS_PACRL_SP4(value)))
+#define AIPS_BWR_PACRL_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP3 field. */
+#define AIPS_RD_PACRL_TP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP3_MASK) >> AIPS_PACRL_TP3_SHIFT)
+#define AIPS_BRD_PACRL_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRL_TP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP3_MASK, AIPS_PACRL_TP3(value)))
+#define AIPS_BWR_PACRL_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP3 field. */
+#define AIPS_RD_PACRL_WP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP3_MASK) >> AIPS_PACRL_WP3_SHIFT)
+#define AIPS_BRD_PACRL_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRL_WP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP3_MASK, AIPS_PACRL_WP3(value)))
+#define AIPS_BWR_PACRL_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP3 field. */
+#define AIPS_RD_PACRL_SP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP3_MASK) >> AIPS_PACRL_SP3_SHIFT)
+#define AIPS_BRD_PACRL_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRL_SP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP3_MASK, AIPS_PACRL_SP3(value)))
+#define AIPS_BWR_PACRL_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP2 field. */
+#define AIPS_RD_PACRL_TP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP2_MASK) >> AIPS_PACRL_TP2_SHIFT)
+#define AIPS_BRD_PACRL_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRL_TP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP2_MASK, AIPS_PACRL_TP2(value)))
+#define AIPS_BWR_PACRL_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP2 field. */
+#define AIPS_RD_PACRL_WP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP2_MASK) >> AIPS_PACRL_WP2_SHIFT)
+#define AIPS_BRD_PACRL_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRL_WP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP2_MASK, AIPS_PACRL_WP2(value)))
+#define AIPS_BWR_PACRL_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP2 field. */
+#define AIPS_RD_PACRL_SP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP2_MASK) >> AIPS_PACRL_SP2_SHIFT)
+#define AIPS_BRD_PACRL_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRL_SP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP2_MASK, AIPS_PACRL_SP2(value)))
+#define AIPS_BWR_PACRL_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP1 field. */
+#define AIPS_RD_PACRL_TP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP1_MASK) >> AIPS_PACRL_TP1_SHIFT)
+#define AIPS_BRD_PACRL_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRL_TP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP1_MASK, AIPS_PACRL_TP1(value)))
+#define AIPS_BWR_PACRL_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP1 field. */
+#define AIPS_RD_PACRL_WP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP1_MASK) >> AIPS_PACRL_WP1_SHIFT)
+#define AIPS_BRD_PACRL_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRL_WP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP1_MASK, AIPS_PACRL_WP1(value)))
+#define AIPS_BWR_PACRL_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP1 field. */
+#define AIPS_RD_PACRL_SP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP1_MASK) >> AIPS_PACRL_SP1_SHIFT)
+#define AIPS_BRD_PACRL_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRL_SP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP1_MASK, AIPS_PACRL_SP1(value)))
+#define AIPS_BWR_PACRL_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP0 field. */
+#define AIPS_RD_PACRL_TP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP0_MASK) >> AIPS_PACRL_TP0_SHIFT)
+#define AIPS_BRD_PACRL_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRL_TP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP0_MASK, AIPS_PACRL_TP0(value)))
+#define AIPS_BWR_PACRL_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP0 field. */
+#define AIPS_RD_PACRL_WP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP0_MASK) >> AIPS_PACRL_WP0_SHIFT)
+#define AIPS_BRD_PACRL_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRL_WP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP0_MASK, AIPS_PACRL_WP0(value)))
+#define AIPS_BWR_PACRL_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP0 field. */
+#define AIPS_RD_PACRL_SP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP0_MASK) >> AIPS_PACRL_SP0_SHIFT)
+#define AIPS_BRD_PACRL_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRL_SP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP0_MASK, AIPS_PACRL_SP0(value)))
+#define AIPS_BWR_PACRL_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRM - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRM - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRM register
+ */
+/*@{*/
+#define AIPS_RD_PACRM(base)      (AIPS_PACRM_REG(base))
+#define AIPS_WR_PACRM(base, value) (AIPS_PACRM_REG(base) = (value))
+#define AIPS_RMW_PACRM(base, mask, value) (AIPS_WR_PACRM(base, (AIPS_RD_PACRM(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) |  (value)))
+#define AIPS_CLR_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) & ~(value)))
+#define AIPS_TOG_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRM bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRM, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP7 field. */
+#define AIPS_RD_PACRM_TP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP7_MASK) >> AIPS_PACRM_TP7_SHIFT)
+#define AIPS_BRD_PACRM_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRM_TP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP7_MASK, AIPS_PACRM_TP7(value)))
+#define AIPS_BWR_PACRM_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP7 field. */
+#define AIPS_RD_PACRM_WP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP7_MASK) >> AIPS_PACRM_WP7_SHIFT)
+#define AIPS_BRD_PACRM_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRM_WP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP7_MASK, AIPS_PACRM_WP7(value)))
+#define AIPS_BWR_PACRM_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP7 field. */
+#define AIPS_RD_PACRM_SP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP7_MASK) >> AIPS_PACRM_SP7_SHIFT)
+#define AIPS_BRD_PACRM_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRM_SP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP7_MASK, AIPS_PACRM_SP7(value)))
+#define AIPS_BWR_PACRM_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP6 field. */
+#define AIPS_RD_PACRM_TP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP6_MASK) >> AIPS_PACRM_TP6_SHIFT)
+#define AIPS_BRD_PACRM_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRM_TP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP6_MASK, AIPS_PACRM_TP6(value)))
+#define AIPS_BWR_PACRM_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP6 field. */
+#define AIPS_RD_PACRM_WP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP6_MASK) >> AIPS_PACRM_WP6_SHIFT)
+#define AIPS_BRD_PACRM_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRM_WP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP6_MASK, AIPS_PACRM_WP6(value)))
+#define AIPS_BWR_PACRM_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP6 field. */
+#define AIPS_RD_PACRM_SP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP6_MASK) >> AIPS_PACRM_SP6_SHIFT)
+#define AIPS_BRD_PACRM_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRM_SP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP6_MASK, AIPS_PACRM_SP6(value)))
+#define AIPS_BWR_PACRM_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP5 field. */
+#define AIPS_RD_PACRM_TP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP5_MASK) >> AIPS_PACRM_TP5_SHIFT)
+#define AIPS_BRD_PACRM_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRM_TP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP5_MASK, AIPS_PACRM_TP5(value)))
+#define AIPS_BWR_PACRM_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP5 field. */
+#define AIPS_RD_PACRM_WP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP5_MASK) >> AIPS_PACRM_WP5_SHIFT)
+#define AIPS_BRD_PACRM_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRM_WP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP5_MASK, AIPS_PACRM_WP5(value)))
+#define AIPS_BWR_PACRM_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP5 field. */
+#define AIPS_RD_PACRM_SP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP5_MASK) >> AIPS_PACRM_SP5_SHIFT)
+#define AIPS_BRD_PACRM_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRM_SP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP5_MASK, AIPS_PACRM_SP5(value)))
+#define AIPS_BWR_PACRM_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP4 field. */
+#define AIPS_RD_PACRM_TP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP4_MASK) >> AIPS_PACRM_TP4_SHIFT)
+#define AIPS_BRD_PACRM_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRM_TP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP4_MASK, AIPS_PACRM_TP4(value)))
+#define AIPS_BWR_PACRM_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP4 field. */
+#define AIPS_RD_PACRM_WP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP4_MASK) >> AIPS_PACRM_WP4_SHIFT)
+#define AIPS_BRD_PACRM_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRM_WP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP4_MASK, AIPS_PACRM_WP4(value)))
+#define AIPS_BWR_PACRM_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP4 field. */
+#define AIPS_RD_PACRM_SP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP4_MASK) >> AIPS_PACRM_SP4_SHIFT)
+#define AIPS_BRD_PACRM_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRM_SP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP4_MASK, AIPS_PACRM_SP4(value)))
+#define AIPS_BWR_PACRM_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP3 field. */
+#define AIPS_RD_PACRM_TP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP3_MASK) >> AIPS_PACRM_TP3_SHIFT)
+#define AIPS_BRD_PACRM_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRM_TP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP3_MASK, AIPS_PACRM_TP3(value)))
+#define AIPS_BWR_PACRM_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP3 field. */
+#define AIPS_RD_PACRM_WP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP3_MASK) >> AIPS_PACRM_WP3_SHIFT)
+#define AIPS_BRD_PACRM_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRM_WP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP3_MASK, AIPS_PACRM_WP3(value)))
+#define AIPS_BWR_PACRM_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP3 field. */
+#define AIPS_RD_PACRM_SP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP3_MASK) >> AIPS_PACRM_SP3_SHIFT)
+#define AIPS_BRD_PACRM_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRM_SP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP3_MASK, AIPS_PACRM_SP3(value)))
+#define AIPS_BWR_PACRM_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP2 field. */
+#define AIPS_RD_PACRM_TP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP2_MASK) >> AIPS_PACRM_TP2_SHIFT)
+#define AIPS_BRD_PACRM_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRM_TP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP2_MASK, AIPS_PACRM_TP2(value)))
+#define AIPS_BWR_PACRM_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP2 field. */
+#define AIPS_RD_PACRM_WP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP2_MASK) >> AIPS_PACRM_WP2_SHIFT)
+#define AIPS_BRD_PACRM_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRM_WP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP2_MASK, AIPS_PACRM_WP2(value)))
+#define AIPS_BWR_PACRM_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP2 field. */
+#define AIPS_RD_PACRM_SP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP2_MASK) >> AIPS_PACRM_SP2_SHIFT)
+#define AIPS_BRD_PACRM_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRM_SP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP2_MASK, AIPS_PACRM_SP2(value)))
+#define AIPS_BWR_PACRM_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP1 field. */
+#define AIPS_RD_PACRM_TP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP1_MASK) >> AIPS_PACRM_TP1_SHIFT)
+#define AIPS_BRD_PACRM_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRM_TP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP1_MASK, AIPS_PACRM_TP1(value)))
+#define AIPS_BWR_PACRM_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP1 field. */
+#define AIPS_RD_PACRM_WP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP1_MASK) >> AIPS_PACRM_WP1_SHIFT)
+#define AIPS_BRD_PACRM_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRM_WP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP1_MASK, AIPS_PACRM_WP1(value)))
+#define AIPS_BWR_PACRM_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP1 field. */
+#define AIPS_RD_PACRM_SP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP1_MASK) >> AIPS_PACRM_SP1_SHIFT)
+#define AIPS_BRD_PACRM_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRM_SP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP1_MASK, AIPS_PACRM_SP1(value)))
+#define AIPS_BWR_PACRM_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP0 field. */
+#define AIPS_RD_PACRM_TP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP0_MASK) >> AIPS_PACRM_TP0_SHIFT)
+#define AIPS_BRD_PACRM_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRM_TP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP0_MASK, AIPS_PACRM_TP0(value)))
+#define AIPS_BWR_PACRM_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP0 field. */
+#define AIPS_RD_PACRM_WP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP0_MASK) >> AIPS_PACRM_WP0_SHIFT)
+#define AIPS_BRD_PACRM_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRM_WP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP0_MASK, AIPS_PACRM_WP0(value)))
+#define AIPS_BWR_PACRM_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP0 field. */
+#define AIPS_RD_PACRM_SP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP0_MASK) >> AIPS_PACRM_SP0_SHIFT)
+#define AIPS_BRD_PACRM_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRM_SP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP0_MASK, AIPS_PACRM_SP0(value)))
+#define AIPS_BWR_PACRM_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRN - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRN - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRN register
+ */
+/*@{*/
+#define AIPS_RD_PACRN(base)      (AIPS_PACRN_REG(base))
+#define AIPS_WR_PACRN(base, value) (AIPS_PACRN_REG(base) = (value))
+#define AIPS_RMW_PACRN(base, mask, value) (AIPS_WR_PACRN(base, (AIPS_RD_PACRN(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) |  (value)))
+#define AIPS_CLR_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) & ~(value)))
+#define AIPS_TOG_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRN bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRN, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP7 field. */
+#define AIPS_RD_PACRN_TP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP7_MASK) >> AIPS_PACRN_TP7_SHIFT)
+#define AIPS_BRD_PACRN_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRN_TP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP7_MASK, AIPS_PACRN_TP7(value)))
+#define AIPS_BWR_PACRN_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP7 field. */
+#define AIPS_RD_PACRN_WP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP7_MASK) >> AIPS_PACRN_WP7_SHIFT)
+#define AIPS_BRD_PACRN_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRN_WP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP7_MASK, AIPS_PACRN_WP7(value)))
+#define AIPS_BWR_PACRN_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP7 field. */
+#define AIPS_RD_PACRN_SP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP7_MASK) >> AIPS_PACRN_SP7_SHIFT)
+#define AIPS_BRD_PACRN_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRN_SP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP7_MASK, AIPS_PACRN_SP7(value)))
+#define AIPS_BWR_PACRN_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP6 field. */
+#define AIPS_RD_PACRN_TP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP6_MASK) >> AIPS_PACRN_TP6_SHIFT)
+#define AIPS_BRD_PACRN_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRN_TP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP6_MASK, AIPS_PACRN_TP6(value)))
+#define AIPS_BWR_PACRN_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP6 field. */
+#define AIPS_RD_PACRN_WP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP6_MASK) >> AIPS_PACRN_WP6_SHIFT)
+#define AIPS_BRD_PACRN_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRN_WP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP6_MASK, AIPS_PACRN_WP6(value)))
+#define AIPS_BWR_PACRN_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP6 field. */
+#define AIPS_RD_PACRN_SP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP6_MASK) >> AIPS_PACRN_SP6_SHIFT)
+#define AIPS_BRD_PACRN_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRN_SP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP6_MASK, AIPS_PACRN_SP6(value)))
+#define AIPS_BWR_PACRN_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP5 field. */
+#define AIPS_RD_PACRN_TP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP5_MASK) >> AIPS_PACRN_TP5_SHIFT)
+#define AIPS_BRD_PACRN_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRN_TP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP5_MASK, AIPS_PACRN_TP5(value)))
+#define AIPS_BWR_PACRN_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP5 field. */
+#define AIPS_RD_PACRN_WP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP5_MASK) >> AIPS_PACRN_WP5_SHIFT)
+#define AIPS_BRD_PACRN_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRN_WP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP5_MASK, AIPS_PACRN_WP5(value)))
+#define AIPS_BWR_PACRN_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP5 field. */
+#define AIPS_RD_PACRN_SP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP5_MASK) >> AIPS_PACRN_SP5_SHIFT)
+#define AIPS_BRD_PACRN_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRN_SP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP5_MASK, AIPS_PACRN_SP5(value)))
+#define AIPS_BWR_PACRN_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP4 field. */
+#define AIPS_RD_PACRN_TP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP4_MASK) >> AIPS_PACRN_TP4_SHIFT)
+#define AIPS_BRD_PACRN_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRN_TP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP4_MASK, AIPS_PACRN_TP4(value)))
+#define AIPS_BWR_PACRN_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP4 field. */
+#define AIPS_RD_PACRN_WP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP4_MASK) >> AIPS_PACRN_WP4_SHIFT)
+#define AIPS_BRD_PACRN_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRN_WP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP4_MASK, AIPS_PACRN_WP4(value)))
+#define AIPS_BWR_PACRN_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP4 field. */
+#define AIPS_RD_PACRN_SP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP4_MASK) >> AIPS_PACRN_SP4_SHIFT)
+#define AIPS_BRD_PACRN_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRN_SP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP4_MASK, AIPS_PACRN_SP4(value)))
+#define AIPS_BWR_PACRN_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP3 field. */
+#define AIPS_RD_PACRN_TP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP3_MASK) >> AIPS_PACRN_TP3_SHIFT)
+#define AIPS_BRD_PACRN_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRN_TP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP3_MASK, AIPS_PACRN_TP3(value)))
+#define AIPS_BWR_PACRN_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP3 field. */
+#define AIPS_RD_PACRN_WP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP3_MASK) >> AIPS_PACRN_WP3_SHIFT)
+#define AIPS_BRD_PACRN_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRN_WP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP3_MASK, AIPS_PACRN_WP3(value)))
+#define AIPS_BWR_PACRN_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP3 field. */
+#define AIPS_RD_PACRN_SP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP3_MASK) >> AIPS_PACRN_SP3_SHIFT)
+#define AIPS_BRD_PACRN_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRN_SP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP3_MASK, AIPS_PACRN_SP3(value)))
+#define AIPS_BWR_PACRN_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP2 field. */
+#define AIPS_RD_PACRN_TP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP2_MASK) >> AIPS_PACRN_TP2_SHIFT)
+#define AIPS_BRD_PACRN_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRN_TP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP2_MASK, AIPS_PACRN_TP2(value)))
+#define AIPS_BWR_PACRN_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP2 field. */
+#define AIPS_RD_PACRN_WP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP2_MASK) >> AIPS_PACRN_WP2_SHIFT)
+#define AIPS_BRD_PACRN_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRN_WP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP2_MASK, AIPS_PACRN_WP2(value)))
+#define AIPS_BWR_PACRN_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP2 field. */
+#define AIPS_RD_PACRN_SP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP2_MASK) >> AIPS_PACRN_SP2_SHIFT)
+#define AIPS_BRD_PACRN_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRN_SP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP2_MASK, AIPS_PACRN_SP2(value)))
+#define AIPS_BWR_PACRN_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP1 field. */
+#define AIPS_RD_PACRN_TP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP1_MASK) >> AIPS_PACRN_TP1_SHIFT)
+#define AIPS_BRD_PACRN_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRN_TP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP1_MASK, AIPS_PACRN_TP1(value)))
+#define AIPS_BWR_PACRN_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP1 field. */
+#define AIPS_RD_PACRN_WP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP1_MASK) >> AIPS_PACRN_WP1_SHIFT)
+#define AIPS_BRD_PACRN_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRN_WP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP1_MASK, AIPS_PACRN_WP1(value)))
+#define AIPS_BWR_PACRN_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP1 field. */
+#define AIPS_RD_PACRN_SP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP1_MASK) >> AIPS_PACRN_SP1_SHIFT)
+#define AIPS_BRD_PACRN_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRN_SP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP1_MASK, AIPS_PACRN_SP1(value)))
+#define AIPS_BWR_PACRN_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP0 field. */
+#define AIPS_RD_PACRN_TP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP0_MASK) >> AIPS_PACRN_TP0_SHIFT)
+#define AIPS_BRD_PACRN_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRN_TP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP0_MASK, AIPS_PACRN_TP0(value)))
+#define AIPS_BWR_PACRN_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP0 field. */
+#define AIPS_RD_PACRN_WP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP0_MASK) >> AIPS_PACRN_WP0_SHIFT)
+#define AIPS_BRD_PACRN_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRN_WP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP0_MASK, AIPS_PACRN_WP0(value)))
+#define AIPS_BWR_PACRN_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP0 field. */
+#define AIPS_RD_PACRN_SP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP0_MASK) >> AIPS_PACRN_SP0_SHIFT)
+#define AIPS_BRD_PACRN_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRN_SP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP0_MASK, AIPS_PACRN_SP0(value)))
+#define AIPS_BWR_PACRN_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRO - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRO - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRO register
+ */
+/*@{*/
+#define AIPS_RD_PACRO(base)      (AIPS_PACRO_REG(base))
+#define AIPS_WR_PACRO(base, value) (AIPS_PACRO_REG(base) = (value))
+#define AIPS_RMW_PACRO(base, mask, value) (AIPS_WR_PACRO(base, (AIPS_RD_PACRO(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) |  (value)))
+#define AIPS_CLR_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) & ~(value)))
+#define AIPS_TOG_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRO bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRO, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP7 field. */
+#define AIPS_RD_PACRO_TP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP7_MASK) >> AIPS_PACRO_TP7_SHIFT)
+#define AIPS_BRD_PACRO_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRO_TP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP7_MASK, AIPS_PACRO_TP7(value)))
+#define AIPS_BWR_PACRO_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP7 field. */
+#define AIPS_RD_PACRO_WP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP7_MASK) >> AIPS_PACRO_WP7_SHIFT)
+#define AIPS_BRD_PACRO_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRO_WP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP7_MASK, AIPS_PACRO_WP7(value)))
+#define AIPS_BWR_PACRO_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP7 field. */
+#define AIPS_RD_PACRO_SP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP7_MASK) >> AIPS_PACRO_SP7_SHIFT)
+#define AIPS_BRD_PACRO_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRO_SP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP7_MASK, AIPS_PACRO_SP7(value)))
+#define AIPS_BWR_PACRO_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP6 field. */
+#define AIPS_RD_PACRO_TP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP6_MASK) >> AIPS_PACRO_TP6_SHIFT)
+#define AIPS_BRD_PACRO_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRO_TP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP6_MASK, AIPS_PACRO_TP6(value)))
+#define AIPS_BWR_PACRO_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP6 field. */
+#define AIPS_RD_PACRO_WP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP6_MASK) >> AIPS_PACRO_WP6_SHIFT)
+#define AIPS_BRD_PACRO_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRO_WP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP6_MASK, AIPS_PACRO_WP6(value)))
+#define AIPS_BWR_PACRO_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP6 field. */
+#define AIPS_RD_PACRO_SP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP6_MASK) >> AIPS_PACRO_SP6_SHIFT)
+#define AIPS_BRD_PACRO_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRO_SP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP6_MASK, AIPS_PACRO_SP6(value)))
+#define AIPS_BWR_PACRO_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP5 field. */
+#define AIPS_RD_PACRO_TP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP5_MASK) >> AIPS_PACRO_TP5_SHIFT)
+#define AIPS_BRD_PACRO_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRO_TP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP5_MASK, AIPS_PACRO_TP5(value)))
+#define AIPS_BWR_PACRO_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP5 field. */
+#define AIPS_RD_PACRO_WP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP5_MASK) >> AIPS_PACRO_WP5_SHIFT)
+#define AIPS_BRD_PACRO_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRO_WP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP5_MASK, AIPS_PACRO_WP5(value)))
+#define AIPS_BWR_PACRO_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP5 field. */
+#define AIPS_RD_PACRO_SP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP5_MASK) >> AIPS_PACRO_SP5_SHIFT)
+#define AIPS_BRD_PACRO_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRO_SP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP5_MASK, AIPS_PACRO_SP5(value)))
+#define AIPS_BWR_PACRO_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP4 field. */
+#define AIPS_RD_PACRO_TP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP4_MASK) >> AIPS_PACRO_TP4_SHIFT)
+#define AIPS_BRD_PACRO_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRO_TP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP4_MASK, AIPS_PACRO_TP4(value)))
+#define AIPS_BWR_PACRO_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP4 field. */
+#define AIPS_RD_PACRO_WP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP4_MASK) >> AIPS_PACRO_WP4_SHIFT)
+#define AIPS_BRD_PACRO_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRO_WP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP4_MASK, AIPS_PACRO_WP4(value)))
+#define AIPS_BWR_PACRO_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP4 field. */
+#define AIPS_RD_PACRO_SP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP4_MASK) >> AIPS_PACRO_SP4_SHIFT)
+#define AIPS_BRD_PACRO_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRO_SP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP4_MASK, AIPS_PACRO_SP4(value)))
+#define AIPS_BWR_PACRO_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP3 field. */
+#define AIPS_RD_PACRO_TP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP3_MASK) >> AIPS_PACRO_TP3_SHIFT)
+#define AIPS_BRD_PACRO_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRO_TP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP3_MASK, AIPS_PACRO_TP3(value)))
+#define AIPS_BWR_PACRO_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP3 field. */
+#define AIPS_RD_PACRO_WP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP3_MASK) >> AIPS_PACRO_WP3_SHIFT)
+#define AIPS_BRD_PACRO_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRO_WP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP3_MASK, AIPS_PACRO_WP3(value)))
+#define AIPS_BWR_PACRO_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP3 field. */
+#define AIPS_RD_PACRO_SP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP3_MASK) >> AIPS_PACRO_SP3_SHIFT)
+#define AIPS_BRD_PACRO_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRO_SP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP3_MASK, AIPS_PACRO_SP3(value)))
+#define AIPS_BWR_PACRO_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP2 field. */
+#define AIPS_RD_PACRO_TP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP2_MASK) >> AIPS_PACRO_TP2_SHIFT)
+#define AIPS_BRD_PACRO_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRO_TP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP2_MASK, AIPS_PACRO_TP2(value)))
+#define AIPS_BWR_PACRO_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP2 field. */
+#define AIPS_RD_PACRO_WP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP2_MASK) >> AIPS_PACRO_WP2_SHIFT)
+#define AIPS_BRD_PACRO_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRO_WP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP2_MASK, AIPS_PACRO_WP2(value)))
+#define AIPS_BWR_PACRO_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP2 field. */
+#define AIPS_RD_PACRO_SP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP2_MASK) >> AIPS_PACRO_SP2_SHIFT)
+#define AIPS_BRD_PACRO_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRO_SP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP2_MASK, AIPS_PACRO_SP2(value)))
+#define AIPS_BWR_PACRO_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP1 field. */
+#define AIPS_RD_PACRO_TP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP1_MASK) >> AIPS_PACRO_TP1_SHIFT)
+#define AIPS_BRD_PACRO_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRO_TP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP1_MASK, AIPS_PACRO_TP1(value)))
+#define AIPS_BWR_PACRO_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP1 field. */
+#define AIPS_RD_PACRO_WP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP1_MASK) >> AIPS_PACRO_WP1_SHIFT)
+#define AIPS_BRD_PACRO_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRO_WP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP1_MASK, AIPS_PACRO_WP1(value)))
+#define AIPS_BWR_PACRO_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP1 field. */
+#define AIPS_RD_PACRO_SP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP1_MASK) >> AIPS_PACRO_SP1_SHIFT)
+#define AIPS_BRD_PACRO_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRO_SP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP1_MASK, AIPS_PACRO_SP1(value)))
+#define AIPS_BWR_PACRO_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP0 field. */
+#define AIPS_RD_PACRO_TP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP0_MASK) >> AIPS_PACRO_TP0_SHIFT)
+#define AIPS_BRD_PACRO_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRO_TP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP0_MASK, AIPS_PACRO_TP0(value)))
+#define AIPS_BWR_PACRO_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP0 field. */
+#define AIPS_RD_PACRO_WP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP0_MASK) >> AIPS_PACRO_WP0_SHIFT)
+#define AIPS_BRD_PACRO_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRO_WP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP0_MASK, AIPS_PACRO_WP0(value)))
+#define AIPS_BWR_PACRO_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP0 field. */
+#define AIPS_RD_PACRO_SP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP0_MASK) >> AIPS_PACRO_SP0_SHIFT)
+#define AIPS_BRD_PACRO_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRO_SP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP0_MASK, AIPS_PACRO_SP0(value)))
+#define AIPS_BWR_PACRO_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRP - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRP - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRP register
+ */
+/*@{*/
+#define AIPS_RD_PACRP(base)      (AIPS_PACRP_REG(base))
+#define AIPS_WR_PACRP(base, value) (AIPS_PACRP_REG(base) = (value))
+#define AIPS_RMW_PACRP(base, mask, value) (AIPS_WR_PACRP(base, (AIPS_RD_PACRP(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) |  (value)))
+#define AIPS_CLR_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) & ~(value)))
+#define AIPS_TOG_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRP bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRP, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP7 field. */
+#define AIPS_RD_PACRP_TP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP7_MASK) >> AIPS_PACRP_TP7_SHIFT)
+#define AIPS_BRD_PACRP_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRP_TP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP7_MASK, AIPS_PACRP_TP7(value)))
+#define AIPS_BWR_PACRP_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP7 field. */
+#define AIPS_RD_PACRP_WP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP7_MASK) >> AIPS_PACRP_WP7_SHIFT)
+#define AIPS_BRD_PACRP_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRP_WP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP7_MASK, AIPS_PACRP_WP7(value)))
+#define AIPS_BWR_PACRP_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP7 field. */
+#define AIPS_RD_PACRP_SP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP7_MASK) >> AIPS_PACRP_SP7_SHIFT)
+#define AIPS_BRD_PACRP_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRP_SP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP7_MASK, AIPS_PACRP_SP7(value)))
+#define AIPS_BWR_PACRP_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP6 field. */
+#define AIPS_RD_PACRP_TP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP6_MASK) >> AIPS_PACRP_TP6_SHIFT)
+#define AIPS_BRD_PACRP_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRP_TP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP6_MASK, AIPS_PACRP_TP6(value)))
+#define AIPS_BWR_PACRP_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP6 field. */
+#define AIPS_RD_PACRP_WP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP6_MASK) >> AIPS_PACRP_WP6_SHIFT)
+#define AIPS_BRD_PACRP_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRP_WP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP6_MASK, AIPS_PACRP_WP6(value)))
+#define AIPS_BWR_PACRP_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP6 field. */
+#define AIPS_RD_PACRP_SP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP6_MASK) >> AIPS_PACRP_SP6_SHIFT)
+#define AIPS_BRD_PACRP_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRP_SP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP6_MASK, AIPS_PACRP_SP6(value)))
+#define AIPS_BWR_PACRP_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP5 field. */
+#define AIPS_RD_PACRP_TP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP5_MASK) >> AIPS_PACRP_TP5_SHIFT)
+#define AIPS_BRD_PACRP_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRP_TP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP5_MASK, AIPS_PACRP_TP5(value)))
+#define AIPS_BWR_PACRP_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP5 field. */
+#define AIPS_RD_PACRP_WP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP5_MASK) >> AIPS_PACRP_WP5_SHIFT)
+#define AIPS_BRD_PACRP_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRP_WP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP5_MASK, AIPS_PACRP_WP5(value)))
+#define AIPS_BWR_PACRP_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP5 field. */
+#define AIPS_RD_PACRP_SP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP5_MASK) >> AIPS_PACRP_SP5_SHIFT)
+#define AIPS_BRD_PACRP_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRP_SP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP5_MASK, AIPS_PACRP_SP5(value)))
+#define AIPS_BWR_PACRP_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP4 field. */
+#define AIPS_RD_PACRP_TP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP4_MASK) >> AIPS_PACRP_TP4_SHIFT)
+#define AIPS_BRD_PACRP_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRP_TP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP4_MASK, AIPS_PACRP_TP4(value)))
+#define AIPS_BWR_PACRP_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP4 field. */
+#define AIPS_RD_PACRP_WP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP4_MASK) >> AIPS_PACRP_WP4_SHIFT)
+#define AIPS_BRD_PACRP_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRP_WP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP4_MASK, AIPS_PACRP_WP4(value)))
+#define AIPS_BWR_PACRP_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP4 field. */
+#define AIPS_RD_PACRP_SP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP4_MASK) >> AIPS_PACRP_SP4_SHIFT)
+#define AIPS_BRD_PACRP_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRP_SP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP4_MASK, AIPS_PACRP_SP4(value)))
+#define AIPS_BWR_PACRP_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP3 field. */
+#define AIPS_RD_PACRP_TP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP3_MASK) >> AIPS_PACRP_TP3_SHIFT)
+#define AIPS_BRD_PACRP_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRP_TP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP3_MASK, AIPS_PACRP_TP3(value)))
+#define AIPS_BWR_PACRP_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP3 field. */
+#define AIPS_RD_PACRP_WP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP3_MASK) >> AIPS_PACRP_WP3_SHIFT)
+#define AIPS_BRD_PACRP_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRP_WP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP3_MASK, AIPS_PACRP_WP3(value)))
+#define AIPS_BWR_PACRP_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP3 field. */
+#define AIPS_RD_PACRP_SP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP3_MASK) >> AIPS_PACRP_SP3_SHIFT)
+#define AIPS_BRD_PACRP_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRP_SP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP3_MASK, AIPS_PACRP_SP3(value)))
+#define AIPS_BWR_PACRP_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP2 field. */
+#define AIPS_RD_PACRP_TP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP2_MASK) >> AIPS_PACRP_TP2_SHIFT)
+#define AIPS_BRD_PACRP_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRP_TP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP2_MASK, AIPS_PACRP_TP2(value)))
+#define AIPS_BWR_PACRP_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP2 field. */
+#define AIPS_RD_PACRP_WP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP2_MASK) >> AIPS_PACRP_WP2_SHIFT)
+#define AIPS_BRD_PACRP_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRP_WP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP2_MASK, AIPS_PACRP_WP2(value)))
+#define AIPS_BWR_PACRP_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP2 field. */
+#define AIPS_RD_PACRP_SP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP2_MASK) >> AIPS_PACRP_SP2_SHIFT)
+#define AIPS_BRD_PACRP_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRP_SP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP2_MASK, AIPS_PACRP_SP2(value)))
+#define AIPS_BWR_PACRP_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP1 field. */
+#define AIPS_RD_PACRP_TP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP1_MASK) >> AIPS_PACRP_TP1_SHIFT)
+#define AIPS_BRD_PACRP_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRP_TP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP1_MASK, AIPS_PACRP_TP1(value)))
+#define AIPS_BWR_PACRP_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP1 field. */
+#define AIPS_RD_PACRP_WP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP1_MASK) >> AIPS_PACRP_WP1_SHIFT)
+#define AIPS_BRD_PACRP_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRP_WP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP1_MASK, AIPS_PACRP_WP1(value)))
+#define AIPS_BWR_PACRP_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP1 field. */
+#define AIPS_RD_PACRP_SP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP1_MASK) >> AIPS_PACRP_SP1_SHIFT)
+#define AIPS_BRD_PACRP_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRP_SP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP1_MASK, AIPS_PACRP_SP1(value)))
+#define AIPS_BWR_PACRP_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP0 field. */
+#define AIPS_RD_PACRP_TP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP0_MASK) >> AIPS_PACRP_TP0_SHIFT)
+#define AIPS_BRD_PACRP_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRP_TP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP0_MASK, AIPS_PACRP_TP0(value)))
+#define AIPS_BWR_PACRP_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP0 field. */
+#define AIPS_RD_PACRP_WP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP0_MASK) >> AIPS_PACRP_WP0_SHIFT)
+#define AIPS_BRD_PACRP_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRP_WP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP0_MASK, AIPS_PACRP_WP0(value)))
+#define AIPS_BWR_PACRP_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP0 field. */
+#define AIPS_RD_PACRP_SP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP0_MASK) >> AIPS_PACRP_SP0_SHIFT)
+#define AIPS_BRD_PACRP_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRP_SP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP0_MASK, AIPS_PACRP_SP0(value)))
+#define AIPS_BWR_PACRP_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRU - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRU - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44000000U
+ *
+ * PACRU defines the access levels for the two global spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRU register
+ */
+/*@{*/
+#define AIPS_RD_PACRU(base)      (AIPS_PACRU_REG(base))
+#define AIPS_WR_PACRU(base, value) (AIPS_PACRU_REG(base) = (value))
+#define AIPS_RMW_PACRU(base, mask, value) (AIPS_WR_PACRU(base, (AIPS_RD_PACRU(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) |  (value)))
+#define AIPS_CLR_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) & ~(value)))
+#define AIPS_TOG_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRU bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRU, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_TP1 field. */
+#define AIPS_RD_PACRU_TP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_TP1_MASK) >> AIPS_PACRU_TP1_SHIFT)
+#define AIPS_BRD_PACRU_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRU_TP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_TP1_MASK, AIPS_PACRU_TP1(value)))
+#define AIPS_BWR_PACRU_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_WP1 field. */
+#define AIPS_RD_PACRU_WP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_WP1_MASK) >> AIPS_PACRU_WP1_SHIFT)
+#define AIPS_BRD_PACRU_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRU_WP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_WP1_MASK, AIPS_PACRU_WP1(value)))
+#define AIPS_BWR_PACRU_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_SP1 field. */
+#define AIPS_RD_PACRU_SP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_SP1_MASK) >> AIPS_PACRU_SP1_SHIFT)
+#define AIPS_BRD_PACRU_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRU_SP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_SP1_MASK, AIPS_PACRU_SP1(value)))
+#define AIPS_BWR_PACRU_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_TP0 field. */
+#define AIPS_RD_PACRU_TP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_TP0_MASK) >> AIPS_PACRU_TP0_SHIFT)
+#define AIPS_BRD_PACRU_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRU_TP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_TP0_MASK, AIPS_PACRU_TP0(value)))
+#define AIPS_BWR_PACRU_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_WP0 field. */
+#define AIPS_RD_PACRU_WP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_WP0_MASK) >> AIPS_PACRU_WP0_SHIFT)
+#define AIPS_BRD_PACRU_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRU_WP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_WP0_MASK, AIPS_PACRU_WP0(value)))
+#define AIPS_BWR_PACRU_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_SP0 field. */
+#define AIPS_RD_PACRU_SP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_SP0_MASK) >> AIPS_PACRU_SP0_SHIFT)
+#define AIPS_BRD_PACRU_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRU_SP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_SP0_MASK, AIPS_PACRU_SP0(value)))
+#define AIPS_BWR_PACRU_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP0_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 AXBS
+ *
+ * Crossbar switch
+ *
+ * Registers defined in this header file:
+ * - AXBS_PRS - Priority Registers Slave
+ * - AXBS_CRS - Control Register
+ * - AXBS_MGPCR0 - Master General Purpose Control Register
+ * - AXBS_MGPCR1 - Master General Purpose Control Register
+ * - AXBS_MGPCR2 - Master General Purpose Control Register
+ * - AXBS_MGPCR3 - Master General Purpose Control Register
+ * - AXBS_MGPCR4 - Master General Purpose Control Register
+ * - AXBS_MGPCR5 - Master General Purpose Control Register
+ */
+
+#define AXBS_INSTANCE_COUNT (1U) /*!< Number of instances of the AXBS module. */
+#define AXBS_IDX (0U) /*!< Instance number for AXBS. */
+
+/*******************************************************************************
+ * AXBS_PRS - Priority Registers Slave
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_PRS - Priority Registers Slave (RW)
+ *
+ * Reset value: 0x00543210U
+ *
+ * The priority registers (PRSn) set the priority of each master port on a per
+ * slave port basis and reside in each slave port. The priority register can be
+ * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
+ * register can only be read; attempts to write to it have no effect on PRSn and
+ * result in a bus-error response to the master initiating the write. Two available
+ * masters must not be programmed with the same priority level. Attempts to
+ * program two or more masters with the same priority level result in a bus-error
+ * response and the PRSn is not updated. Valid values for the Mn priority fields
+ * depend on which masters are available on the chip. This information can be found in
+ * the chip-specific information for the crossbar. If the chip contains less
+ * than five masters, values 0 to 3 are valid. Writing other values will result in
+ * an error. If the chip contains five or more masters, valid values are 0 to n-1,
+ * where n is the number of masters attached to the AXBS module. Other values
+ * will result in an error.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_PRS register
+ */
+/*@{*/
+#define AXBS_RD_PRS(base, index) (AXBS_PRS_REG(base, index))
+#define AXBS_WR_PRS(base, index, value) (AXBS_PRS_REG(base, index) = (value))
+#define AXBS_RMW_PRS(base, index, mask, value) (AXBS_WR_PRS(base, index, (AXBS_RD_PRS(base, index) & ~(mask)) | (value)))
+#define AXBS_SET_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) |  (value)))
+#define AXBS_CLR_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) & ~(value)))
+#define AXBS_TOG_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_PRS bitfields
+ */
+
+/*!
+ * @name Register AXBS_PRS, field M0[2:0] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M0 field. */
+#define AXBS_RD_PRS_M0(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M0_MASK) >> AXBS_PRS_M0_SHIFT)
+#define AXBS_BRD_PRS_M0(base, index) (AXBS_RD_PRS_M0(base, index))
+
+/*! @brief Set the M0 field to a new value. */
+#define AXBS_WR_PRS_M0(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M0_MASK, AXBS_PRS_M0(value)))
+#define AXBS_BWR_PRS_M0(base, index, value) (AXBS_WR_PRS_M0(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M1[6:4] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M1 field. */
+#define AXBS_RD_PRS_M1(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M1_MASK) >> AXBS_PRS_M1_SHIFT)
+#define AXBS_BRD_PRS_M1(base, index) (AXBS_RD_PRS_M1(base, index))
+
+/*! @brief Set the M1 field to a new value. */
+#define AXBS_WR_PRS_M1(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M1_MASK, AXBS_PRS_M1(value)))
+#define AXBS_BWR_PRS_M1(base, index, value) (AXBS_WR_PRS_M1(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M2[10:8] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M2 field. */
+#define AXBS_RD_PRS_M2(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M2_MASK) >> AXBS_PRS_M2_SHIFT)
+#define AXBS_BRD_PRS_M2(base, index) (AXBS_RD_PRS_M2(base, index))
+
+/*! @brief Set the M2 field to a new value. */
+#define AXBS_WR_PRS_M2(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M2_MASK, AXBS_PRS_M2(value)))
+#define AXBS_BWR_PRS_M2(base, index, value) (AXBS_WR_PRS_M2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M3[14:12] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M3 field. */
+#define AXBS_RD_PRS_M3(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M3_MASK) >> AXBS_PRS_M3_SHIFT)
+#define AXBS_BRD_PRS_M3(base, index) (AXBS_RD_PRS_M3(base, index))
+
+/*! @brief Set the M3 field to a new value. */
+#define AXBS_WR_PRS_M3(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M3_MASK, AXBS_PRS_M3(value)))
+#define AXBS_BWR_PRS_M3(base, index, value) (AXBS_WR_PRS_M3(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M4[18:16] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M4 field. */
+#define AXBS_RD_PRS_M4(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M4_MASK) >> AXBS_PRS_M4_SHIFT)
+#define AXBS_BRD_PRS_M4(base, index) (AXBS_RD_PRS_M4(base, index))
+
+/*! @brief Set the M4 field to a new value. */
+#define AXBS_WR_PRS_M4(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M4_MASK, AXBS_PRS_M4(value)))
+#define AXBS_BWR_PRS_M4(base, index, value) (AXBS_WR_PRS_M4(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M5[22:20] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M5 field. */
+#define AXBS_RD_PRS_M5(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M5_MASK) >> AXBS_PRS_M5_SHIFT)
+#define AXBS_BRD_PRS_M5(base, index) (AXBS_RD_PRS_M5(base, index))
+
+/*! @brief Set the M5 field to a new value. */
+#define AXBS_WR_PRS_M5(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M5_MASK, AXBS_PRS_M5(value)))
+#define AXBS_BWR_PRS_M5(base, index, value) (AXBS_WR_PRS_M5(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_CRS - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_CRS - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers control several features of each slave port and must be
+ * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
+ * attempts to write to it have no effect and result in an error response.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_CRS register
+ */
+/*@{*/
+#define AXBS_RD_CRS(base, index) (AXBS_CRS_REG(base, index))
+#define AXBS_WR_CRS(base, index, value) (AXBS_CRS_REG(base, index) = (value))
+#define AXBS_RMW_CRS(base, index, mask, value) (AXBS_WR_CRS(base, index, (AXBS_RD_CRS(base, index) & ~(mask)) | (value)))
+#define AXBS_SET_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) |  (value)))
+#define AXBS_CLR_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) & ~(value)))
+#define AXBS_TOG_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_CRS bitfields
+ */
+
+/*!
+ * @name Register AXBS_CRS, field PARK[2:0] (RW)
+ *
+ * Determines which master port the current slave port parks on when no masters
+ * are actively making requests and the PCTL bits are cleared. Select only master
+ * ports that are present on the chip. Otherwise, undefined behavior might occur.
+ *
+ * Values:
+ * - 0b000 - Park on master port M0
+ * - 0b001 - Park on master port M1
+ * - 0b010 - Park on master port M2
+ * - 0b011 - Park on master port M3
+ * - 0b100 - Park on master port M4
+ * - 0b101 - Park on master port M5
+ * - 0b110 - Park on master port M6
+ * - 0b111 - Park on master port M7
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_PARK field. */
+#define AXBS_RD_CRS_PARK(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_PARK_MASK) >> AXBS_CRS_PARK_SHIFT)
+#define AXBS_BRD_CRS_PARK(base, index) (AXBS_RD_CRS_PARK(base, index))
+
+/*! @brief Set the PARK field to a new value. */
+#define AXBS_WR_CRS_PARK(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_PARK_MASK, AXBS_CRS_PARK(value)))
+#define AXBS_BWR_CRS_PARK(base, index, value) (AXBS_WR_CRS_PARK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field PCTL[5:4] (RW)
+ *
+ * Determines the slave port's parking control. The low-power park feature
+ * results in an overall power savings if the slave port is not saturated. However,
+ * this forces an extra latency clock when any master tries to access the slave
+ * port while not in use because it is not parked on any master.
+ *
+ * Values:
+ * - 0b00 - When no master makes a request, the arbiter parks the slave port on
+ *     the master port defined by the PARK field
+ * - 0b01 - When no master makes a request, the arbiter parks the slave port on
+ *     the last master to be in control of the slave port
+ * - 0b10 - When no master makes a request, the slave port is not parked on a
+ *     master and the arbiter drives all outputs to a constant safe state
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_PCTL field. */
+#define AXBS_RD_CRS_PCTL(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_PCTL_MASK) >> AXBS_CRS_PCTL_SHIFT)
+#define AXBS_BRD_CRS_PCTL(base, index) (AXBS_RD_CRS_PCTL(base, index))
+
+/*! @brief Set the PCTL field to a new value. */
+#define AXBS_WR_CRS_PCTL(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_PCTL_MASK, AXBS_CRS_PCTL(value)))
+#define AXBS_BWR_CRS_PCTL(base, index, value) (AXBS_WR_CRS_PCTL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field ARB[9:8] (RW)
+ *
+ * Selects the arbitration policy for the slave port.
+ *
+ * Values:
+ * - 0b00 - Fixed priority
+ * - 0b01 - Round-robin, or rotating, priority
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_ARB field. */
+#define AXBS_RD_CRS_ARB(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_ARB_MASK) >> AXBS_CRS_ARB_SHIFT)
+#define AXBS_BRD_CRS_ARB(base, index) (AXBS_RD_CRS_ARB(base, index))
+
+/*! @brief Set the ARB field to a new value. */
+#define AXBS_WR_CRS_ARB(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_ARB_MASK, AXBS_CRS_ARB(value)))
+#define AXBS_BWR_CRS_ARB(base, index, value) (AXBS_WR_CRS_ARB(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field HLP[30] (RW)
+ *
+ * Sets the initial arbitration priority for low power mode requests . Setting
+ * this bit will not affect the request for low power mode from attaining highest
+ * priority once it has control of the slave ports.
+ *
+ * Values:
+ * - 0b0 - The low power mode request has the highest priority for arbitration
+ *     on this slave port
+ * - 0b1 - The low power mode request has the lowest initial priority for
+ *     arbitration on this slave port
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_HLP field. */
+#define AXBS_RD_CRS_HLP(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_HLP_MASK) >> AXBS_CRS_HLP_SHIFT)
+#define AXBS_BRD_CRS_HLP(base, index) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_HLP_SHIFT))
+
+/*! @brief Set the HLP field to a new value. */
+#define AXBS_WR_CRS_HLP(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_HLP_MASK, AXBS_CRS_HLP(value)))
+#define AXBS_BWR_CRS_HLP(base, index, value) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_HLP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field RO[31] (RW)
+ *
+ * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
+ * only a hardware reset clears it.
+ *
+ * Values:
+ * - 0b0 - The slave port's registers are writeable
+ * - 0b1 - The slave port's registers are read-only and cannot be written.
+ *     Attempted writes have no effect on the registers and result in a bus error
+ *     response.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_RO field. */
+#define AXBS_RD_CRS_RO(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_RO_MASK) >> AXBS_CRS_RO_SHIFT)
+#define AXBS_BRD_CRS_RO(base, index) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_RO_SHIFT))
+
+/*! @brief Set the RO field to a new value. */
+#define AXBS_WR_CRS_RO(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_RO_MASK, AXBS_CRS_RO(value)))
+#define AXBS_BWR_CRS_RO(base, index, value) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_RO_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR0 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR0 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR0 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR0(base)     (AXBS_MGPCR0_REG(base))
+#define AXBS_WR_MGPCR0(base, value) (AXBS_MGPCR0_REG(base) = (value))
+#define AXBS_RMW_MGPCR0(base, mask, value) (AXBS_WR_MGPCR0(base, (AXBS_RD_MGPCR0(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) |  (value)))
+#define AXBS_CLR_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) & ~(value)))
+#define AXBS_TOG_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR0 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR0_AULB field. */
+#define AXBS_RD_MGPCR0_AULB(base) ((AXBS_MGPCR0_REG(base) & AXBS_MGPCR0_AULB_MASK) >> AXBS_MGPCR0_AULB_SHIFT)
+#define AXBS_BRD_MGPCR0_AULB(base) (AXBS_RD_MGPCR0_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR0_AULB(base, value) (AXBS_RMW_MGPCR0(base, AXBS_MGPCR0_AULB_MASK, AXBS_MGPCR0_AULB(value)))
+#define AXBS_BWR_MGPCR0_AULB(base, value) (AXBS_WR_MGPCR0_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR1 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR1 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR1 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR1(base)     (AXBS_MGPCR1_REG(base))
+#define AXBS_WR_MGPCR1(base, value) (AXBS_MGPCR1_REG(base) = (value))
+#define AXBS_RMW_MGPCR1(base, mask, value) (AXBS_WR_MGPCR1(base, (AXBS_RD_MGPCR1(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) |  (value)))
+#define AXBS_CLR_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) & ~(value)))
+#define AXBS_TOG_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR1 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR1_AULB field. */
+#define AXBS_RD_MGPCR1_AULB(base) ((AXBS_MGPCR1_REG(base) & AXBS_MGPCR1_AULB_MASK) >> AXBS_MGPCR1_AULB_SHIFT)
+#define AXBS_BRD_MGPCR1_AULB(base) (AXBS_RD_MGPCR1_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR1_AULB(base, value) (AXBS_RMW_MGPCR1(base, AXBS_MGPCR1_AULB_MASK, AXBS_MGPCR1_AULB(value)))
+#define AXBS_BWR_MGPCR1_AULB(base, value) (AXBS_WR_MGPCR1_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR2 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR2 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR2 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR2(base)     (AXBS_MGPCR2_REG(base))
+#define AXBS_WR_MGPCR2(base, value) (AXBS_MGPCR2_REG(base) = (value))
+#define AXBS_RMW_MGPCR2(base, mask, value) (AXBS_WR_MGPCR2(base, (AXBS_RD_MGPCR2(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) |  (value)))
+#define AXBS_CLR_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) & ~(value)))
+#define AXBS_TOG_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR2 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR2_AULB field. */
+#define AXBS_RD_MGPCR2_AULB(base) ((AXBS_MGPCR2_REG(base) & AXBS_MGPCR2_AULB_MASK) >> AXBS_MGPCR2_AULB_SHIFT)
+#define AXBS_BRD_MGPCR2_AULB(base) (AXBS_RD_MGPCR2_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR2_AULB(base, value) (AXBS_RMW_MGPCR2(base, AXBS_MGPCR2_AULB_MASK, AXBS_MGPCR2_AULB(value)))
+#define AXBS_BWR_MGPCR2_AULB(base, value) (AXBS_WR_MGPCR2_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR3 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR3 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR3 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR3(base)     (AXBS_MGPCR3_REG(base))
+#define AXBS_WR_MGPCR3(base, value) (AXBS_MGPCR3_REG(base) = (value))
+#define AXBS_RMW_MGPCR3(base, mask, value) (AXBS_WR_MGPCR3(base, (AXBS_RD_MGPCR3(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) |  (value)))
+#define AXBS_CLR_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) & ~(value)))
+#define AXBS_TOG_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR3 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR3_AULB field. */
+#define AXBS_RD_MGPCR3_AULB(base) ((AXBS_MGPCR3_REG(base) & AXBS_MGPCR3_AULB_MASK) >> AXBS_MGPCR3_AULB_SHIFT)
+#define AXBS_BRD_MGPCR3_AULB(base) (AXBS_RD_MGPCR3_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR3_AULB(base, value) (AXBS_RMW_MGPCR3(base, AXBS_MGPCR3_AULB_MASK, AXBS_MGPCR3_AULB(value)))
+#define AXBS_BWR_MGPCR3_AULB(base, value) (AXBS_WR_MGPCR3_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR4 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR4 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR4 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR4(base)     (AXBS_MGPCR4_REG(base))
+#define AXBS_WR_MGPCR4(base, value) (AXBS_MGPCR4_REG(base) = (value))
+#define AXBS_RMW_MGPCR4(base, mask, value) (AXBS_WR_MGPCR4(base, (AXBS_RD_MGPCR4(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) |  (value)))
+#define AXBS_CLR_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) & ~(value)))
+#define AXBS_TOG_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR4 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR4_AULB field. */
+#define AXBS_RD_MGPCR4_AULB(base) ((AXBS_MGPCR4_REG(base) & AXBS_MGPCR4_AULB_MASK) >> AXBS_MGPCR4_AULB_SHIFT)
+#define AXBS_BRD_MGPCR4_AULB(base) (AXBS_RD_MGPCR4_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR4_AULB(base, value) (AXBS_RMW_MGPCR4(base, AXBS_MGPCR4_AULB_MASK, AXBS_MGPCR4_AULB(value)))
+#define AXBS_BWR_MGPCR4_AULB(base, value) (AXBS_WR_MGPCR4_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR5 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR5 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR5 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR5(base)     (AXBS_MGPCR5_REG(base))
+#define AXBS_WR_MGPCR5(base, value) (AXBS_MGPCR5_REG(base) = (value))
+#define AXBS_RMW_MGPCR5(base, mask, value) (AXBS_WR_MGPCR5(base, (AXBS_RD_MGPCR5(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) |  (value)))
+#define AXBS_CLR_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) & ~(value)))
+#define AXBS_TOG_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR5 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR5_AULB field. */
+#define AXBS_RD_MGPCR5_AULB(base) ((AXBS_MGPCR5_REG(base) & AXBS_MGPCR5_AULB_MASK) >> AXBS_MGPCR5_AULB_SHIFT)
+#define AXBS_BRD_MGPCR5_AULB(base) (AXBS_RD_MGPCR5_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR5_AULB(base, value) (AXBS_RMW_MGPCR5(base, AXBS_MGPCR5_AULB_MASK, AXBS_MGPCR5_AULB(value)))
+#define AXBS_BWR_MGPCR5_AULB(base, value) (AXBS_WR_MGPCR5_AULB(base, value))
+/*@}*/
+
+/*
+ * MK64F12 CAN
+ *
+ * Flex Controller Area Network module
+ *
+ * Registers defined in this header file:
+ * - CAN_MCR - Module Configuration Register
+ * - CAN_CTRL1 - Control 1 register
+ * - CAN_TIMER - Free Running Timer
+ * - CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ * - CAN_RX14MASK - Rx 14 Mask register
+ * - CAN_RX15MASK - Rx 15 Mask register
+ * - CAN_ECR - Error Counter
+ * - CAN_ESR1 - Error and Status 1 register
+ * - CAN_IMASK1 - Interrupt Masks 1 register
+ * - CAN_IFLAG1 - Interrupt Flags 1 register
+ * - CAN_CTRL2 - Control 2 register
+ * - CAN_ESR2 - Error and Status 2 register
+ * - CAN_CRCR - CRC Register
+ * - CAN_RXFGMASK - Rx FIFO Global Mask register
+ * - CAN_RXFIR - Rx FIFO Information Register
+ * - CAN_CS - Message Buffer 0 CS Register
+ * - CAN_ID - Message Buffer 0 ID Register
+ * - CAN_WORD0 - Message Buffer 0 WORD0 Register
+ * - CAN_WORD1 - Message Buffer 0 WORD1 Register
+ * - CAN_RXIMR - Rx Individual Mask Registers
+ */
+
+#define CAN_INSTANCE_COUNT (1U) /*!< Number of instances of the CAN module. */
+#define CAN0_IDX (0U) /*!< Instance number for CAN0. */
+
+/*******************************************************************************
+ * CAN_MCR - Module Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0xD890000FU
+ *
+ * This register defines global system configurations, such as the module
+ * operation modes and the maximum message buffer configuration.
+ */
+/*!
+ * @name Constants and macros for entire CAN_MCR register
+ */
+/*@{*/
+#define CAN_RD_MCR(base)         (CAN_MCR_REG(base))
+#define CAN_WR_MCR(base, value)  (CAN_MCR_REG(base) = (value))
+#define CAN_RMW_MCR(base, mask, value) (CAN_WR_MCR(base, (CAN_RD_MCR(base) & ~(mask)) | (value)))
+#define CAN_SET_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) |  (value)))
+#define CAN_CLR_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) & ~(value)))
+#define CAN_TOG_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_MCR bitfields
+ */
+
+/*!
+ * @name Register CAN_MCR, field MAXMB[6:0] (RW)
+ *
+ * This 7-bit field defines the number of the last Message Buffers that will
+ * take part in the matching and arbitration processes. The reset value (0x0F) is
+ * equivalent to a 16 MB configuration. This field can be written only in Freeze
+ * mode because it is blocked by hardware in other modes. Number of the last MB =
+ * MAXMB MAXMB must be programmed with a value smaller than the parameter
+ * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
+ * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
+ * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
+ * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
+ * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
+ * Matching Timing").
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_MAXMB field. */
+#define CAN_RD_MCR_MAXMB(base) ((CAN_MCR_REG(base) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT)
+#define CAN_BRD_MCR_MAXMB(base) (CAN_RD_MCR_MAXMB(base))
+
+/*! @brief Set the MAXMB field to a new value. */
+#define CAN_WR_MCR_MAXMB(base, value) (CAN_RMW_MCR(base, CAN_MCR_MAXMB_MASK, CAN_MCR_MAXMB(value)))
+#define CAN_BWR_MCR_MAXMB(base, value) (CAN_WR_MCR_MAXMB(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field IDAM[9:8] (RW)
+ *
+ * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
+ * elements. Note that all elements of the table are configured at the same time by this
+ * field (they are all the same format). See Section "Rx FIFO Structure". This
+ * field can be written only in Freeze mode because it is blocked by hardware in
+ * other modes.
+ *
+ * Values:
+ * - 0b00 - Format A: One full ID (standard and extended) per ID Filter Table
+ *     element.
+ * - 0b01 - Format B: Two full standard IDs or two partial 14-bit (standard and
+ *     extended) IDs per ID Filter Table element.
+ * - 0b10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table
+ *     element.
+ * - 0b11 - Format D: All frames rejected.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_IDAM field. */
+#define CAN_RD_MCR_IDAM(base) ((CAN_MCR_REG(base) & CAN_MCR_IDAM_MASK) >> CAN_MCR_IDAM_SHIFT)
+#define CAN_BRD_MCR_IDAM(base) (CAN_RD_MCR_IDAM(base))
+
+/*! @brief Set the IDAM field to a new value. */
+#define CAN_WR_MCR_IDAM(base, value) (CAN_RMW_MCR(base, CAN_MCR_IDAM_MASK, CAN_MCR_IDAM(value)))
+#define CAN_BWR_MCR_IDAM(base, value) (CAN_WR_MCR_IDAM(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field AEN[12] (RW)
+ *
+ * This bit is supplied for backwards compatibility with legacy applications.
+ * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
+ * safe procedure for aborting a pending transmission, so that no frame is sent in
+ * the CAN bus without notification. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
+ * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
+ * used for updating Mailboxes configured for transmission. Writing the Abort code
+ * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Abort disabled.
+ * - 0b1 - Abort enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_AEN field. */
+#define CAN_RD_MCR_AEN(base) ((CAN_MCR_REG(base) & CAN_MCR_AEN_MASK) >> CAN_MCR_AEN_SHIFT)
+#define CAN_BRD_MCR_AEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_AEN_SHIFT))
+
+/*! @brief Set the AEN field to a new value. */
+#define CAN_WR_MCR_AEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_AEN_MASK, CAN_MCR_AEN(value)))
+#define CAN_BWR_MCR_AEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_AEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field LPRIOEN[13] (RW)
+ *
+ * This bit is provided for backwards compatibility with legacy applications. It
+ * controls whether the local priority feature is enabled or not. It is used to
+ * expand the ID used during the arbitration process. With this expanded ID
+ * concept, the arbitration process is done based on the full 32-bit word, but the
+ * actual transmitted ID still has 11-bit for standard frames and 29-bit for
+ * extended frames. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Local Priority disabled.
+ * - 0b1 - Local Priority enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_LPRIOEN field. */
+#define CAN_RD_MCR_LPRIOEN(base) ((CAN_MCR_REG(base) & CAN_MCR_LPRIOEN_MASK) >> CAN_MCR_LPRIOEN_SHIFT)
+#define CAN_BRD_MCR_LPRIOEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPRIOEN_SHIFT))
+
+/*! @brief Set the LPRIOEN field to a new value. */
+#define CAN_WR_MCR_LPRIOEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_LPRIOEN_MASK, CAN_MCR_LPRIOEN(value)))
+#define CAN_BWR_MCR_LPRIOEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPRIOEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field IRMQ[16] (RW)
+ *
+ * This bit indicates whether Rx matching process will be based either on
+ * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
+ * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Individual Rx masking and queue feature are disabled. For backward
+ *     compatibility with legacy applications, the reading of C/S word locks the MB
+ *     even if it is EMPTY.
+ * - 0b1 - Individual Rx masking and queue feature are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_IRMQ field. */
+#define CAN_RD_MCR_IRMQ(base) ((CAN_MCR_REG(base) & CAN_MCR_IRMQ_MASK) >> CAN_MCR_IRMQ_SHIFT)
+#define CAN_BRD_MCR_IRMQ(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_IRMQ_SHIFT))
+
+/*! @brief Set the IRMQ field to a new value. */
+#define CAN_WR_MCR_IRMQ(base, value) (CAN_RMW_MCR(base, CAN_MCR_IRMQ_MASK, CAN_MCR_IRMQ(value)))
+#define CAN_BWR_MCR_IRMQ(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_IRMQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SRXDIS[17] (RW)
+ *
+ * This bit defines whether FlexCAN is allowed to receive frames transmitted by
+ * itself. If this bit is asserted, frames transmitted by the module will not be
+ * stored in any MB, regardless if the MB is programmed with an ID that matches
+ * the transmitted frame, and no interrupt flag or interrupt signal will be
+ * generated due to the frame reception. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Self reception enabled.
+ * - 0b1 - Self reception disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SRXDIS field. */
+#define CAN_RD_MCR_SRXDIS(base) ((CAN_MCR_REG(base) & CAN_MCR_SRXDIS_MASK) >> CAN_MCR_SRXDIS_SHIFT)
+#define CAN_BRD_MCR_SRXDIS(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SRXDIS_SHIFT))
+
+/*! @brief Set the SRXDIS field to a new value. */
+#define CAN_WR_MCR_SRXDIS(base, value) (CAN_RMW_MCR(base, CAN_MCR_SRXDIS_MASK, CAN_MCR_SRXDIS(value)))
+#define CAN_BWR_MCR_SRXDIS(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SRXDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WAKSRC[19] (RW)
+ *
+ * This bit defines whether the integrated low-pass filter is applied to protect
+ * the Rx CAN input from spurious wake up. This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ * - 0b1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WAKSRC field. */
+#define CAN_RD_MCR_WAKSRC(base) ((CAN_MCR_REG(base) & CAN_MCR_WAKSRC_MASK) >> CAN_MCR_WAKSRC_SHIFT)
+#define CAN_BRD_MCR_WAKSRC(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKSRC_SHIFT))
+
+/*! @brief Set the WAKSRC field to a new value. */
+#define CAN_WR_MCR_WAKSRC(base, value) (CAN_RMW_MCR(base, CAN_MCR_WAKSRC_MASK, CAN_MCR_WAKSRC(value)))
+#define CAN_BWR_MCR_WAKSRC(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field LPMACK[20] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
+ * mode , Stop mode ). A low-power mode cannot be entered until all current
+ * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
+ * to know when FlexCAN has actually entered low power mode. LPMACK will be
+ * asserted within 180 CAN bits from the low-power mode request by the CPU, and
+ * negated within 2 CAN bits after the low-power mode request removal (see Section
+ * "Protocol Timing").
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not in a low-power mode.
+ * - 0b1 - FlexCAN is in a low-power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_LPMACK field. */
+#define CAN_RD_MCR_LPMACK(base) ((CAN_MCR_REG(base) & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT)
+#define CAN_BRD_MCR_LPMACK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPMACK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WRNEN[21] (RW)
+ *
+ * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
+ * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
+ * RWRNINT flags will always be zero, independent of the values of the error
+ * counters, and no warning interrupt will ever be generated. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
+ *     error counters.
+ * - 0b1 - TWRNINT and RWRNINT bits are set when the respective error counter
+ *     transitions from less than 96 to greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WRNEN field. */
+#define CAN_RD_MCR_WRNEN(base) ((CAN_MCR_REG(base) & CAN_MCR_WRNEN_MASK) >> CAN_MCR_WRNEN_SHIFT)
+#define CAN_BRD_MCR_WRNEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WRNEN_SHIFT))
+
+/*! @brief Set the WRNEN field to a new value. */
+#define CAN_WR_MCR_WRNEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_WRNEN_MASK, CAN_MCR_WRNEN(value)))
+#define CAN_BWR_MCR_WRNEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WRNEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SLFWAK[22] (RW)
+ *
+ * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
+ * other than Disable mode. When this feature is enabled, the FlexCAN module
+ * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
+ * If a wake up event is detected during Stop mode, then FlexCAN generates, if
+ * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
+ * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
+ * low-power mode other than Disable mode, this bit cannot be written as it is
+ * blocked by hardware.
+ *
+ * Values:
+ * - 0b0 - FlexCAN Self Wake Up feature is disabled.
+ * - 0b1 - FlexCAN Self Wake Up feature is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SLFWAK field. */
+#define CAN_RD_MCR_SLFWAK(base) ((CAN_MCR_REG(base) & CAN_MCR_SLFWAK_MASK) >> CAN_MCR_SLFWAK_SHIFT)
+#define CAN_BRD_MCR_SLFWAK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SLFWAK_SHIFT))
+
+/*! @brief Set the SLFWAK field to a new value. */
+#define CAN_WR_MCR_SLFWAK(base, value) (CAN_RMW_MCR(base, CAN_MCR_SLFWAK_MASK, CAN_MCR_SLFWAK(value)))
+#define CAN_BWR_MCR_SLFWAK(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SLFWAK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SUPV[23] (RW)
+ *
+ * This bit configures the FlexCAN to be either in Supervisor or User mode. The
+ * registers affected by this bit are marked as S/U in the Access Type column of
+ * the module memory map. Reset value of this bit is 1, so the affected registers
+ * start with Supervisor access allowance only . This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
+ *     Unrestricted accesses .
+ * - 0b1 - FlexCAN is in Supervisor mode. Affected registers allow only
+ *     Supervisor access. Unrestricted access behaves as though the access was done to an
+ *     unimplemented register location .
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SUPV field. */
+#define CAN_RD_MCR_SUPV(base) ((CAN_MCR_REG(base) & CAN_MCR_SUPV_MASK) >> CAN_MCR_SUPV_SHIFT)
+#define CAN_BRD_MCR_SUPV(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SUPV_SHIFT))
+
+/*! @brief Set the SUPV field to a new value. */
+#define CAN_WR_MCR_SUPV(base, value) (CAN_RMW_MCR(base, CAN_MCR_SUPV_MASK, CAN_MCR_SUPV(value)))
+#define CAN_BWR_MCR_SUPV(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SUPV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field FRZACK[24] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
+ * is stopped. The Freeze mode request cannot be granted until current
+ * transmission or reception processes have finished. Therefore the software can poll the
+ * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
+ * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
+ * running again. If Freeze mode is requested while FlexCAN is in a low power
+ * mode, then the FRZACK bit will be set only when the low-power mode is exited.
+ * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
+ * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
+ * mode request removal (see Section "Protocol Timing").
+ *
+ * Values:
+ * - 0b0 - FlexCAN not in Freeze mode, prescaler running.
+ * - 0b1 - FlexCAN in Freeze mode, prescaler stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_FRZACK field. */
+#define CAN_RD_MCR_FRZACK(base) ((CAN_MCR_REG(base) & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)
+#define CAN_BRD_MCR_FRZACK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZACK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SOFTRST[25] (RW)
+ *
+ * When this bit is asserted, FlexCAN resets its internal state machines and
+ * some of the memory mapped registers. The following registers are reset: MCR
+ * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
+ * CRCR. Configuration registers that control the interface to the CAN bus are
+ * not affected by soft reset. The following registers are unaffected: CTRL1,
+ * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
+ * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
+ * writes to the MCR Register, but it is also asserted when global soft reset is
+ * requested at MCU level . Because soft reset is synchronous and has to follow a
+ * request/acknowledge procedure across clock domains, it may take some time to
+ * fully propagate its effect. The SOFTRST bit remains asserted while reset is
+ * pending, and is automatically negated when reset completes. Therefore, software can
+ * poll this bit to know when the soft reset has completed. Soft reset cannot be
+ * applied while clocks are shut down in a low power mode. The module should be
+ * first removed from low power mode, and then soft reset can be applied.
+ *
+ * Values:
+ * - 0b0 - No reset request.
+ * - 0b1 - Resets the registers affected by soft reset.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SOFTRST field. */
+#define CAN_RD_MCR_SOFTRST(base) ((CAN_MCR_REG(base) & CAN_MCR_SOFTRST_MASK) >> CAN_MCR_SOFTRST_SHIFT)
+#define CAN_BRD_MCR_SOFTRST(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SOFTRST_SHIFT))
+
+/*! @brief Set the SOFTRST field to a new value. */
+#define CAN_WR_MCR_SOFTRST(base, value) (CAN_RMW_MCR(base, CAN_MCR_SOFTRST_MASK, CAN_MCR_SOFTRST(value)))
+#define CAN_BWR_MCR_SOFTRST(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SOFTRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WAKMSK[26] (RW)
+ *
+ * This bit enables the Wake Up Interrupt generation under Self Wake Up
+ * mechanism.
+ *
+ * Values:
+ * - 0b0 - Wake Up Interrupt is disabled.
+ * - 0b1 - Wake Up Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WAKMSK field. */
+#define CAN_RD_MCR_WAKMSK(base) ((CAN_MCR_REG(base) & CAN_MCR_WAKMSK_MASK) >> CAN_MCR_WAKMSK_SHIFT)
+#define CAN_BRD_MCR_WAKMSK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKMSK_SHIFT))
+
+/*! @brief Set the WAKMSK field to a new value. */
+#define CAN_WR_MCR_WAKMSK(base, value) (CAN_RMW_MCR(base, CAN_MCR_WAKMSK_MASK, CAN_MCR_WAKMSK(value)))
+#define CAN_BWR_MCR_WAKMSK(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field NOTRDY[27] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
+ * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN module is either in Normal mode, Listen-Only mode or
+ *     Loop-Back mode.
+ * - 0b1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_NOTRDY field. */
+#define CAN_RD_MCR_NOTRDY(base) ((CAN_MCR_REG(base) & CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT)
+#define CAN_BRD_MCR_NOTRDY(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_NOTRDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field HALT[28] (RW)
+ *
+ * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
+ * should clear it after initializing the Message Buffers and Control Register. No
+ * reception or transmission is performed by FlexCAN before this bit is cleared.
+ * Freeze mode cannot be entered while FlexCAN is in a low power mode.
+ *
+ * Values:
+ * - 0b0 - No Freeze mode request.
+ * - 0b1 - Enters Freeze mode if the FRZ bit is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_HALT field. */
+#define CAN_RD_MCR_HALT(base) ((CAN_MCR_REG(base) & CAN_MCR_HALT_MASK) >> CAN_MCR_HALT_SHIFT)
+#define CAN_BRD_MCR_HALT(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define CAN_WR_MCR_HALT(base, value) (CAN_RMW_MCR(base, CAN_MCR_HALT_MASK, CAN_MCR_HALT(value)))
+#define CAN_BWR_MCR_HALT(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field RFEN[29] (RW)
+ *
+ * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
+ * set, MBs 0 to 5 cannot be used for normal reception and transmission because
+ * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
+ * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
+ * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
+ * minimum number of peripheral clocks per CAN bit as described in the table
+ * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
+ * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Rx FIFO not enabled.
+ * - 0b1 - Rx FIFO enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_RFEN field. */
+#define CAN_RD_MCR_RFEN(base) ((CAN_MCR_REG(base) & CAN_MCR_RFEN_MASK) >> CAN_MCR_RFEN_SHIFT)
+#define CAN_BRD_MCR_RFEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_RFEN_SHIFT))
+
+/*! @brief Set the RFEN field to a new value. */
+#define CAN_WR_MCR_RFEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_RFEN_MASK, CAN_MCR_RFEN(value)))
+#define CAN_BWR_MCR_RFEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_RFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field FRZ[30] (RW)
+ *
+ * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
+ * Register is set or when Debug mode is requested at MCU level . When FRZ is
+ * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
+ * FlexCAN to exit from Freeze mode.
+ *
+ * Values:
+ * - 0b0 - Not enabled to enter Freeze mode.
+ * - 0b1 - Enabled to enter Freeze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_FRZ field. */
+#define CAN_RD_MCR_FRZ(base) ((CAN_MCR_REG(base) & CAN_MCR_FRZ_MASK) >> CAN_MCR_FRZ_SHIFT)
+#define CAN_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define CAN_WR_MCR_FRZ(base, value) (CAN_RMW_MCR(base, CAN_MCR_FRZ_MASK, CAN_MCR_FRZ(value)))
+#define CAN_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field MDIS[31] (RW)
+ *
+ * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
+ * disables the clocks to the CAN Protocol Engine and Controller Host Interface
+ * sub-modules. This is the only bit within this register not affected by soft
+ * reset.
+ *
+ * Values:
+ * - 0b0 - Enable the FlexCAN module.
+ * - 0b1 - Disable the FlexCAN module.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_MDIS field. */
+#define CAN_RD_MCR_MDIS(base) ((CAN_MCR_REG(base) & CAN_MCR_MDIS_MASK) >> CAN_MCR_MDIS_SHIFT)
+#define CAN_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define CAN_WR_MCR_MDIS(base, value) (CAN_RMW_MCR(base, CAN_MCR_MDIS_MASK, CAN_MCR_MDIS(value)))
+#define CAN_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CTRL1 - Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CTRL1 - Control 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is defined for specific FlexCAN control features related to the
+ * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
+ * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
+ * (Bus-Off, Error, Warning). It also determines the Division Factor for the
+ * clock prescaler.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CTRL1 register
+ */
+/*@{*/
+#define CAN_RD_CTRL1(base)       (CAN_CTRL1_REG(base))
+#define CAN_WR_CTRL1(base, value) (CAN_CTRL1_REG(base) = (value))
+#define CAN_RMW_CTRL1(base, mask, value) (CAN_WR_CTRL1(base, (CAN_RD_CTRL1(base) & ~(mask)) | (value)))
+#define CAN_SET_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) |  (value)))
+#define CAN_CLR_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) & ~(value)))
+#define CAN_TOG_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CTRL1 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
+ *
+ * This 3-bit field defines the length of the Propagation Segment in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Propagation
+ * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PROPSEG field. */
+#define CAN_RD_CTRL1_PROPSEG(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PROPSEG_MASK) >> CAN_CTRL1_PROPSEG_SHIFT)
+#define CAN_BRD_CTRL1_PROPSEG(base) (CAN_RD_CTRL1_PROPSEG(base))
+
+/*! @brief Set the PROPSEG field to a new value. */
+#define CAN_WR_CTRL1_PROPSEG(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PROPSEG_MASK, CAN_CTRL1_PROPSEG(value)))
+#define CAN_BWR_CTRL1_PROPSEG(base, value) (CAN_WR_CTRL1_PROPSEG(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LOM[3] (RW)
+ *
+ * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
+ * transmission is disabled, all error counters are frozen and the module operates
+ * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
+ * will be received. If FlexCAN detects a message that has not been acknowledged,
+ * it will flag a BIT0 error without changing the REC, as if it was trying to
+ * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
+ * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
+ * entered. There can be some delay between the Listen-Only mode request and
+ * acknowledge. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Listen-Only mode is deactivated.
+ * - 0b1 - FlexCAN module operates in Listen-Only mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LOM field. */
+#define CAN_RD_CTRL1_LOM(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LOM_MASK) >> CAN_CTRL1_LOM_SHIFT)
+#define CAN_BRD_CTRL1_LOM(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LOM_SHIFT))
+
+/*! @brief Set the LOM field to a new value. */
+#define CAN_WR_CTRL1_LOM(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LOM_MASK, CAN_CTRL1_LOM(value)))
+#define CAN_BWR_CTRL1_LOM(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LBUF[4] (RW)
+ *
+ * This bit defines the ordering mechanism for Message Buffer transmission. When
+ * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0b0 - Buffer with highest priority is transmitted first.
+ * - 0b1 - Lowest number buffer is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LBUF field. */
+#define CAN_RD_CTRL1_LBUF(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LBUF_MASK) >> CAN_CTRL1_LBUF_SHIFT)
+#define CAN_BRD_CTRL1_LBUF(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LBUF_SHIFT))
+
+/*! @brief Set the LBUF field to a new value. */
+#define CAN_WR_CTRL1_LBUF(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LBUF_MASK, CAN_CTRL1_LBUF(value)))
+#define CAN_BWR_CTRL1_LBUF(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field TSYN[5] (RW)
+ *
+ * This bit enables a mechanism that resets the free-running timer each time a
+ * message is received in Message Buffer 0. This feature provides means to
+ * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
+ * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
+ * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
+ * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Timer Sync feature disabled
+ * - 0b1 - Timer Sync feature enabled
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_TSYN field. */
+#define CAN_RD_CTRL1_TSYN(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_TSYN_MASK) >> CAN_CTRL1_TSYN_SHIFT)
+#define CAN_BRD_CTRL1_TSYN(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TSYN_SHIFT))
+
+/*! @brief Set the TSYN field to a new value. */
+#define CAN_WR_CTRL1_TSYN(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_TSYN_MASK, CAN_CTRL1_TSYN(value)))
+#define CAN_BWR_CTRL1_TSYN(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TSYN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
+ *
+ * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
+ * negated, automatic recovering from Bus Off state occurs according to the CAN
+ * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
+ * disabled and the module remains in Bus Off state until the bit is negated by the
+ * user. If the negation occurs before 128 sequences of 11 recessive bits are
+ * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
+ * never been asserted. If the negation occurs after 128 sequences of 11
+ * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
+ * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
+ * be re-asserted again during Bus Off, but it will be effective only the next
+ * time the module enters Bus Off. If BOFFREC was negated when the module entered
+ * Bus Off, asserting it during Bus Off will not be effective for the current Bus
+ * Off recovery.
+ *
+ * Values:
+ * - 0b0 - Automatic recovering from Bus Off state enabled, according to CAN
+ *     Spec 2.0 part B.
+ * - 0b1 - Automatic recovering from Bus Off state disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_BOFFREC field. */
+#define CAN_RD_CTRL1_BOFFREC(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_BOFFREC_MASK) >> CAN_CTRL1_BOFFREC_SHIFT)
+#define CAN_BRD_CTRL1_BOFFREC(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFREC_SHIFT))
+
+/*! @brief Set the BOFFREC field to a new value. */
+#define CAN_WR_CTRL1_BOFFREC(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_BOFFREC_MASK, CAN_CTRL1_BOFFREC(value)))
+#define CAN_BWR_CTRL1_BOFFREC(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFREC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field SMP[7] (RW)
+ *
+ * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
+ * be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0b0 - Just one sample is used to determine the bit value.
+ * - 0b1 - Three samples are used to determine the value of the received bit:
+ *     the regular one (sample point) and 2 preceding samples; a majority rule is
+ *     used.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_SMP field. */
+#define CAN_RD_CTRL1_SMP(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_SMP_MASK) >> CAN_CTRL1_SMP_SHIFT)
+#define CAN_BRD_CTRL1_SMP(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_SMP_SHIFT))
+
+/*! @brief Set the SMP field to a new value. */
+#define CAN_WR_CTRL1_SMP(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_SMP_MASK, CAN_CTRL1_SMP(value)))
+#define CAN_BWR_CTRL1_SMP(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_SMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
+ *
+ * This bit provides a mask for the Rx Warning Interrupt associated with the
+ * RWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Rx Warning Interrupt disabled.
+ * - 0b1 - Rx Warning Interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_RWRNMSK field. */
+#define CAN_RD_CTRL1_RWRNMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_RWRNMSK_MASK) >> CAN_CTRL1_RWRNMSK_SHIFT)
+#define CAN_BRD_CTRL1_RWRNMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_RWRNMSK_SHIFT))
+
+/*! @brief Set the RWRNMSK field to a new value. */
+#define CAN_WR_CTRL1_RWRNMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_RWRNMSK_MASK, CAN_CTRL1_RWRNMSK(value)))
+#define CAN_BWR_CTRL1_RWRNMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_RWRNMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
+ *
+ * This bit provides a mask for the Tx Warning Interrupt associated with the
+ * TWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Tx Warning Interrupt disabled.
+ * - 0b1 - Tx Warning Interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_TWRNMSK field. */
+#define CAN_RD_CTRL1_TWRNMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_TWRNMSK_MASK) >> CAN_CTRL1_TWRNMSK_SHIFT)
+#define CAN_BRD_CTRL1_TWRNMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TWRNMSK_SHIFT))
+
+/*! @brief Set the TWRNMSK field to a new value. */
+#define CAN_WR_CTRL1_TWRNMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_TWRNMSK_MASK, CAN_CTRL1_TWRNMSK(value)))
+#define CAN_BWR_CTRL1_TWRNMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TWRNMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LPB[12] (RW)
+ *
+ * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
+ * FlexCAN performs an internal loop back that can be used for self test operation.
+ * The bit stream output of the transmitter is fed back internally to the receiver
+ * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
+ * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
+ * and treats its own transmitted message as a message received from a remote
+ * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
+ * frame acknowledge field, generating an internal acknowledge bit to ensure proper
+ * reception of its own message. Both transmit and receive interrupts are
+ * generated. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
+ * this will impede the self reception of a transmitted message.
+ *
+ * Values:
+ * - 0b0 - Loop Back disabled.
+ * - 0b1 - Loop Back enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LPB field. */
+#define CAN_RD_CTRL1_LPB(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LPB_MASK) >> CAN_CTRL1_LPB_SHIFT)
+#define CAN_BRD_CTRL1_LPB(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LPB_SHIFT))
+
+/*! @brief Set the LPB field to a new value. */
+#define CAN_WR_CTRL1_LPB(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LPB_MASK, CAN_CTRL1_LPB(value)))
+#define CAN_BWR_CTRL1_LPB(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LPB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
+ *
+ * This bit selects the clock source to the CAN Protocol Engine (PE) to be
+ * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
+ * The selected clock is the one fed to the prescaler to generate the Serial Clock
+ * (Sclock). In order to guarantee reliable operation, this bit can be written
+ * only in Disable mode because it is blocked by hardware in other modes. See
+ * Section "Protocol Timing".
+ *
+ * Values:
+ * - 0b0 - The CAN engine clock source is the oscillator clock. Under this
+ *     condition, the oscillator clock frequency must be lower than the bus clock.
+ * - 0b1 - The CAN engine clock source is the peripheral clock.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_CLKSRC field. */
+#define CAN_RD_CTRL1_CLKSRC(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_CLKSRC_MASK) >> CAN_CTRL1_CLKSRC_SHIFT)
+#define CAN_BRD_CTRL1_CLKSRC(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_CLKSRC_SHIFT))
+
+/*! @brief Set the CLKSRC field to a new value. */
+#define CAN_WR_CTRL1_CLKSRC(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_CLKSRC_MASK, CAN_CTRL1_CLKSRC(value)))
+#define CAN_BWR_CTRL1_CLKSRC(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_CLKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
+ *
+ * This bit provides a mask for the Error Interrupt.
+ *
+ * Values:
+ * - 0b0 - Error interrupt disabled.
+ * - 0b1 - Error interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_ERRMSK field. */
+#define CAN_RD_CTRL1_ERRMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_ERRMSK_MASK) >> CAN_CTRL1_ERRMSK_SHIFT)
+#define CAN_BRD_CTRL1_ERRMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_ERRMSK_SHIFT))
+
+/*! @brief Set the ERRMSK field to a new value. */
+#define CAN_WR_CTRL1_ERRMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_ERRMSK_MASK, CAN_CTRL1_ERRMSK(value)))
+#define CAN_BWR_CTRL1_ERRMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_ERRMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
+ *
+ * This bit provides a mask for the Bus Off Interrupt.
+ *
+ * Values:
+ * - 0b0 - Bus Off interrupt disabled.
+ * - 0b1 - Bus Off interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_BOFFMSK field. */
+#define CAN_RD_CTRL1_BOFFMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_BOFFMSK_MASK) >> CAN_CTRL1_BOFFMSK_SHIFT)
+#define CAN_BRD_CTRL1_BOFFMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFMSK_SHIFT))
+
+/*! @brief Set the BOFFMSK field to a new value. */
+#define CAN_WR_CTRL1_BOFFMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_BOFFMSK_MASK, CAN_CTRL1_BOFFMSK(value)))
+#define CAN_BWR_CTRL1_BOFFMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
+ * time. The valid programmable values are 1-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 2 = (PSEG2 + 1) * Time-Quanta.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PSEG2 field. */
+#define CAN_RD_CTRL1_PSEG2(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PSEG2_MASK) >> CAN_CTRL1_PSEG2_SHIFT)
+#define CAN_BRD_CTRL1_PSEG2(base) (CAN_RD_CTRL1_PSEG2(base))
+
+/*! @brief Set the PSEG2 field to a new value. */
+#define CAN_WR_CTRL1_PSEG2(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PSEG2_MASK, CAN_CTRL1_PSEG2(value)))
+#define CAN_BWR_CTRL1_PSEG2(base, value) (CAN_WR_CTRL1_PSEG2(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 1 = (PSEG1 + 1) * Time-Quanta.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PSEG1 field. */
+#define CAN_RD_CTRL1_PSEG1(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PSEG1_MASK) >> CAN_CTRL1_PSEG1_SHIFT)
+#define CAN_BRD_CTRL1_PSEG1(base) (CAN_RD_CTRL1_PSEG1(base))
+
+/*! @brief Set the PSEG1 field to a new value. */
+#define CAN_WR_CTRL1_PSEG1(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PSEG1_MASK, CAN_CTRL1_PSEG1(value)))
+#define CAN_BWR_CTRL1_PSEG1(base, value) (CAN_WR_CTRL1_PSEG1(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field RJW[23:22] (RW)
+ *
+ * This 2-bit field defines the maximum number of time quanta that a bit time
+ * can be changed by one re-synchronization. One time quantum is equal to the
+ * Sclock period. The valid programmable values are 0-3. This field can be written
+ * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
+ * Width = RJW + 1.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_RJW field. */
+#define CAN_RD_CTRL1_RJW(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_RJW_MASK) >> CAN_CTRL1_RJW_SHIFT)
+#define CAN_BRD_CTRL1_RJW(base) (CAN_RD_CTRL1_RJW(base))
+
+/*! @brief Set the RJW field to a new value. */
+#define CAN_WR_CTRL1_RJW(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_RJW_MASK, CAN_CTRL1_RJW(value)))
+#define CAN_BWR_CTRL1_RJW(base, value) (CAN_WR_CTRL1_RJW(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
+ *
+ * This 8-bit field defines the ratio between the PE clock frequency and the
+ * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
+ * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
+ * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
+ * Sclock frequency equal to the PE clock frequency divided by 256. See Section
+ * "Protocol Timing". This field can be written only in Freeze mode because it is
+ * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
+ * (PRESDIV + 1)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PRESDIV field. */
+#define CAN_RD_CTRL1_PRESDIV(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PRESDIV_MASK) >> CAN_CTRL1_PRESDIV_SHIFT)
+#define CAN_BRD_CTRL1_PRESDIV(base) (CAN_RD_CTRL1_PRESDIV(base))
+
+/*! @brief Set the PRESDIV field to a new value. */
+#define CAN_WR_CTRL1_PRESDIV(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PRESDIV_MASK, CAN_CTRL1_PRESDIV(value)))
+#define CAN_BWR_CTRL1_PRESDIV(base, value) (CAN_WR_CTRL1_PRESDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_TIMER - Free Running Timer
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_TIMER - Free Running Timer (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register represents a 16-bit free running counter that can be read and
+ * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
+ * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
+ * defines the baud rate on the CAN bus. During a message transmission/reception,
+ * it increments by one for each bit that is received or transmitted. When there
+ * is no message on the bus, it counts using the previously programmed baud
+ * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
+ * timer value is captured when the second bit of the identifier field of any frame
+ * is on the CAN bus. This captured value is written into the Time Stamp entry
+ * in a message buffer after a successful reception or transmission of a message.
+ * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
+ * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
+ * can write to this register anytime. However, if the write occurs at the same
+ * time that the Timer is being reset by a reception in the first Mailbox, then
+ * the write value is discarded. Reading this register affects the Mailbox
+ * Unlocking procedure; see Section "Mailbox Lock Mechanism".
+ */
+/*!
+ * @name Constants and macros for entire CAN_TIMER register
+ */
+/*@{*/
+#define CAN_RD_TIMER(base)       (CAN_TIMER_REG(base))
+#define CAN_WR_TIMER(base, value) (CAN_TIMER_REG(base) = (value))
+#define CAN_RMW_TIMER(base, mask, value) (CAN_WR_TIMER(base, (CAN_RD_TIMER(base) & ~(mask)) | (value)))
+#define CAN_SET_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) |  (value)))
+#define CAN_CLR_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) & ~(value)))
+#define CAN_TOG_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_TIMER bitfields
+ */
+
+/*!
+ * @name Register CAN_TIMER, field TIMER[15:0] (RW)
+ *
+ * Contains the free-running counter value.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_TIMER_TIMER field. */
+#define CAN_RD_TIMER_TIMER(base) ((CAN_TIMER_REG(base) & CAN_TIMER_TIMER_MASK) >> CAN_TIMER_TIMER_SHIFT)
+#define CAN_BRD_TIMER_TIMER(base) (CAN_RD_TIMER_TIMER(base))
+
+/*! @brief Set the TIMER field to a new value. */
+#define CAN_WR_TIMER_TIMER(base, value) (CAN_RMW_TIMER(base, CAN_TIMER_TIMER_MASK, CAN_TIMER_TIMER(value)))
+#define CAN_BWR_TIMER_TIMER(base, value) (CAN_WR_TIMER_TIMER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RXMGMASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
+ * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
+ * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
+ * mask registers. This register can only be written in Freeze mode as it is
+ * blocked by hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXMGMASK register
+ */
+/*@{*/
+#define CAN_RD_RXMGMASK(base)    (CAN_RXMGMASK_REG(base))
+#define CAN_WR_RXMGMASK(base, value) (CAN_RXMGMASK_REG(base) = (value))
+#define CAN_RMW_RXMGMASK(base, mask, value) (CAN_WR_RXMGMASK(base, (CAN_RD_RXMGMASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) |  (value)))
+#define CAN_CLR_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) & ~(value)))
+#define CAN_TOG_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RX14MASK - Rx 14 Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RX14MASK - Rx 14 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX14MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
+ * is used to mask the filter fields of Message Buffer 14. This register can only
+ * be programmed while the module is in Freeze mode as it is blocked by hardware
+ * in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RX14MASK register
+ */
+/*@{*/
+#define CAN_RD_RX14MASK(base)    (CAN_RX14MASK_REG(base))
+#define CAN_WR_RX14MASK(base, value) (CAN_RX14MASK_REG(base) = (value))
+#define CAN_RMW_RX14MASK(base, mask, value) (CAN_WR_RX14MASK(base, (CAN_RD_RX14MASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) |  (value)))
+#define CAN_CLR_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) & ~(value)))
+#define CAN_TOG_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RX15MASK - Rx 15 Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RX15MASK - Rx 15 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX15MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
+ * is used to mask the filter fields of Message Buffer 15. This register can be
+ * programmed only while the module is in Freeze mode because it is blocked by
+ * hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RX15MASK register
+ */
+/*@{*/
+#define CAN_RD_RX15MASK(base)    (CAN_RX15MASK_REG(base))
+#define CAN_WR_RX15MASK(base, value) (CAN_RX15MASK_REG(base) = (value))
+#define CAN_RMW_RX15MASK(base, mask, value) (CAN_WR_RX15MASK(base, (CAN_RD_RX15MASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) |  (value)))
+#define CAN_CLR_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) & ~(value)))
+#define CAN_TOG_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ECR - Error Counter
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ECR - Error Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has two 8-bit fields reflecting the value of two FlexCAN error
+ * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
+ * (RXERRCNT field). The rules for increasing and decreasing these counters are
+ * described in the CAN protocol and are completely implemented in the FlexCAN
+ * module. Both counters are read-only except in Freeze mode, where they can be
+ * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
+ * for example, transmit Error Active or Error Passive flag, delay its
+ * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
+ * Off state. The following are the basic rules for FlexCAN bus state transitions:
+ * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
+ * 128, the FLTCONF field in the Error and Status Register is updated to reflect
+ * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
+ * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
+ * other already satisfies this condition, the FLTCONF field in the Error and
+ * Status Register is updated to reflect 'Error Active' state. If the value of
+ * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
+ * Register is updated to reflect 'Bus Off' state, and an interrupt may be
+ * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
+ * state, then TXERRCNT is cascaded together with another internal counter to count
+ * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
+ * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
+ * 11 such bits and then wraps around while incrementing the TXERRCNT. When
+ * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
+ * Register is updated to be 'Error Active' and both error counters are reset to zero.
+ * At any instance of dominant bit following a stream of less than 11
+ * consecutive recessive bits, the internal counter resets itself to zero without affecting
+ * the TXERRCNT value. If during system start-up, only one node is operating,
+ * then its TXERRCNT increases in each message it is trying to transmit, as a
+ * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
+ * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
+ * increment anymore by acknowledge errors. Therefore the device never goes to
+ * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
+ * is not incremented further, even if more errors are detected while being a
+ * receiver. At the next successful message reception, the counter is set to a value
+ * between 119 and 127 to resume to 'Error Active' state.
+ */
+/*!
+ * @name Constants and macros for entire CAN_ECR register
+ */
+/*@{*/
+#define CAN_RD_ECR(base)         (CAN_ECR_REG(base))
+#define CAN_WR_ECR(base, value)  (CAN_ECR_REG(base) = (value))
+#define CAN_RMW_ECR(base, mask, value) (CAN_WR_ECR(base, (CAN_RD_ECR(base) & ~(mask)) | (value)))
+#define CAN_SET_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) |  (value)))
+#define CAN_CLR_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) & ~(value)))
+#define CAN_TOG_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ECR bitfields
+ */
+
+/*!
+ * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ECR_TXERRCNT field. */
+#define CAN_RD_ECR_TXERRCNT(base) ((CAN_ECR_REG(base) & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT)
+#define CAN_BRD_ECR_TXERRCNT(base) (CAN_RD_ECR_TXERRCNT(base))
+
+/*! @brief Set the TXERRCNT field to a new value. */
+#define CAN_WR_ECR_TXERRCNT(base, value) (CAN_RMW_ECR(base, CAN_ECR_TXERRCNT_MASK, CAN_ECR_TXERRCNT(value)))
+#define CAN_BWR_ECR_TXERRCNT(base, value) (CAN_WR_ECR_TXERRCNT(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ECR_RXERRCNT field. */
+#define CAN_RD_ECR_RXERRCNT(base) ((CAN_ECR_REG(base) & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT)
+#define CAN_BRD_ECR_RXERRCNT(base) (CAN_RD_ECR_RXERRCNT(base))
+
+/*! @brief Set the RXERRCNT field to a new value. */
+#define CAN_WR_ECR_RXERRCNT(base, value) (CAN_RMW_ECR(base, CAN_ECR_RXERRCNT_MASK, CAN_ECR_RXERRCNT(value)))
+#define CAN_BWR_ECR_RXERRCNT(base, value) (CAN_WR_ECR_RXERRCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ESR1 - Error and Status 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ESR1 - Error and Status 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various error conditions, some general status of the
+ * device and it is the source of interrupts to the CPU. The CPU read action
+ * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
+ * that occurred since the last time the CPU read this register. Bits 9-3 are
+ * status bits. The following table shows the FlexCAN state variables and their
+ * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
+ * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
+ * Transmitting 1 0 0 1 Receiving
+ */
+/*!
+ * @name Constants and macros for entire CAN_ESR1 register
+ */
+/*@{*/
+#define CAN_RD_ESR1(base)        (CAN_ESR1_REG(base))
+#define CAN_WR_ESR1(base, value) (CAN_ESR1_REG(base) = (value))
+#define CAN_RMW_ESR1(base, mask, value) (CAN_WR_ESR1(base, (CAN_RD_ESR1(base) & ~(mask)) | (value)))
+#define CAN_SET_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) |  (value)))
+#define CAN_CLR_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) & ~(value)))
+#define CAN_TOG_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ESR1 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR1, field WAKINT[0] (W1C)
+ *
+ * This field applies when FlexCAN is in low-power mode under Self Wake Up
+ * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
+ * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
+ * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
+ * is masked. The CPU must clear this flag before disabling the bit. Otherwise
+ * it will be set when the SLFWAK is set again. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - Indicates a recessive to dominant transition was received on the CAN
+ *     bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_WAKINT field. */
+#define CAN_RD_ESR1_WAKINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_WAKINT_MASK) >> CAN_ESR1_WAKINT_SHIFT)
+#define CAN_BRD_ESR1_WAKINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_WAKINT_SHIFT))
+
+/*! @brief Set the WAKINT field to a new value. */
+#define CAN_WR_ESR1_WAKINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_WAKINT(value)))
+#define CAN_BWR_ESR1_WAKINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_WAKINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field ERRINT[1] (W1C)
+ *
+ * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
+ * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
+ * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - Indicates setting of any Error Bit in the Error and Status Register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_ERRINT field. */
+#define CAN_RD_ESR1_ERRINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_ERRINT_MASK) >> CAN_ESR1_ERRINT_SHIFT)
+#define CAN_BRD_ESR1_ERRINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ERRINT_SHIFT))
+
+/*! @brief Set the ERRINT field to a new value. */
+#define CAN_WR_ESR1_ERRINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_ERRINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_ERRINT(value)))
+#define CAN_BWR_ESR1_ERRINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ERRINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
+ *
+ * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
+ * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
+ * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - FlexCAN module entered Bus Off state.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BOFFINT field. */
+#define CAN_RD_ESR1_BOFFINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BOFFINT_MASK) >> CAN_ESR1_BOFFINT_SHIFT)
+#define CAN_BRD_ESR1_BOFFINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BOFFINT_SHIFT))
+
+/*! @brief Set the BOFFINT field to a new value. */
+#define CAN_WR_ESR1_BOFFINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_BOFFINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_BOFFINT(value)))
+#define CAN_BWR_ESR1_BOFFINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BOFFINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RX[3] (RO)
+ *
+ * This bit indicates if FlexCAN is receiving a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not receiving a message.
+ * - 0b1 - FlexCAN is receiving a message.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RX field. */
+#define CAN_RD_ESR1_RX(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RX_MASK) >> CAN_ESR1_RX_SHIFT)
+#define CAN_BRD_ESR1_RX(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
+ *
+ * This 2-bit field indicates the Confinement State of the FlexCAN module. If
+ * the LOM bit in the Control Register is asserted, after some delay that depends
+ * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
+ * same delay affects the way how FLTCONF reflects an update to ECR register by
+ * the CPU. It may be necessary up to one CAN bit time to get them coherent
+ * again. Because the Control Register is not affected by soft reset, the FLTCONF
+ * field will not be affected by soft reset if the LOM bit is asserted.
+ *
+ * Values:
+ * - 0b00 - Error Active
+ * - 0b01 - Error Passive
+ * - 0b1x - Bus Off
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_FLTCONF field. */
+#define CAN_RD_ESR1_FLTCONF(base) ((CAN_ESR1_REG(base) & CAN_ESR1_FLTCONF_MASK) >> CAN_ESR1_FLTCONF_SHIFT)
+#define CAN_BRD_ESR1_FLTCONF(base) (CAN_RD_ESR1_FLTCONF(base))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TX[6] (RO)
+ *
+ * This bit indicates if FlexCAN is transmitting a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not transmitting a message.
+ * - 0b1 - FlexCAN is transmitting a message.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TX field. */
+#define CAN_RD_ESR1_TX(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TX_MASK) >> CAN_ESR1_TX_SHIFT)
+#define CAN_BRD_ESR1_TX(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field IDLE[7] (RO)
+ *
+ * This bit indicates when CAN bus is in IDLE state. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - CAN bus is now IDLE.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_IDLE field. */
+#define CAN_RD_ESR1_IDLE(base) ((CAN_ESR1_REG(base) & CAN_ESR1_IDLE_MASK) >> CAN_ESR1_IDLE_SHIFT)
+#define CAN_BRD_ESR1_IDLE(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RXWRN[8] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * reception. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - RXERRCNT is greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RXWRN field. */
+#define CAN_RD_ESR1_RXWRN(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RXWRN_MASK) >> CAN_ESR1_RXWRN_SHIFT)
+#define CAN_BRD_ESR1_RXWRN(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RXWRN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TXWRN[9] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * transmission. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - TXERRCNT is greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TXWRN field. */
+#define CAN_RD_ESR1_TXWRN(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TXWRN_MASK) >> CAN_ESR1_TXWRN_SHIFT)
+#define CAN_BRD_ESR1_TXWRN(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TXWRN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field STFERR[10] (RO)
+ *
+ * This bit indicates that a Stuffing Error has been etected.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A Stuffing Error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_STFERR field. */
+#define CAN_RD_ESR1_STFERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_STFERR_MASK) >> CAN_ESR1_STFERR_SHIFT)
+#define CAN_BRD_ESR1_STFERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_STFERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field FRMERR[11] (RO)
+ *
+ * This bit indicates that a Form Error has been detected by the receiver node,
+ * that is, a fixed-form bit field contains at least one illegal bit.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A Form Error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_FRMERR field. */
+#define CAN_RD_ESR1_FRMERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_FRMERR_MASK) >> CAN_ESR1_FRMERR_SHIFT)
+#define CAN_BRD_ESR1_FRMERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_FRMERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field CRCERR[12] (RO)
+ *
+ * This bit indicates that a CRC Error has been detected by the receiver node,
+ * that is, the calculated CRC is different from the received.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A CRC error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_CRCERR field. */
+#define CAN_RD_ESR1_CRCERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_CRCERR_MASK) >> CAN_ESR1_CRCERR_SHIFT)
+#define CAN_BRD_ESR1_CRCERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_CRCERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field ACKERR[13] (RO)
+ *
+ * This bit indicates that an Acknowledge Error has been detected by the
+ * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - An ACK error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_ACKERR field. */
+#define CAN_RD_ESR1_ACKERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_ACKERR_MASK) >> CAN_ESR1_ACKERR_SHIFT)
+#define CAN_BRD_ESR1_ACKERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ACKERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - At least one bit sent as dominant is received as recessive.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BIT0ERR field. */
+#define CAN_RD_ESR1_BIT0ERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BIT0ERR_MASK) >> CAN_ESR1_BIT0ERR_SHIFT)
+#define CAN_BRD_ESR1_BIT0ERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BIT0ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message. This bit is not set by a transmitter in case of
+ * arbitration field or ACK slot, or in case of a node sending a passive error
+ * flag that detects dominant bits.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - At least one bit sent as recessive is received as dominant.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BIT1ERR field. */
+#define CAN_RD_ESR1_BIT1ERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BIT1ERR_MASK) >> CAN_ESR1_BIT1ERR_SHIFT)
+#define CAN_BRD_ESR1_BIT1ERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BIT1ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
+ * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
+ * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
+ * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - The Rx error counter transitioned from less than 96 to greater than
+ *     or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RWRNINT field. */
+#define CAN_RD_ESR1_RWRNINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RWRNINT_MASK) >> CAN_ESR1_RWRNINT_SHIFT)
+#define CAN_BRD_ESR1_RWRNINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RWRNINT_SHIFT))
+
+/*! @brief Set the RWRNINT field to a new value. */
+#define CAN_WR_ESR1_RWRNINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_RWRNINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_RWRNINT(value)))
+#define CAN_BWR_ESR1_RWRNINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RWRNINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
+ * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
+ * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
+ * is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This flag is not generated during Bus Off state. This bit is not
+ * updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - The Tx error counter transitioned from less than 96 to greater than
+ *     or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TWRNINT field. */
+#define CAN_RD_ESR1_TWRNINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TWRNINT_MASK) >> CAN_ESR1_TWRNINT_SHIFT)
+#define CAN_BRD_ESR1_TWRNINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TWRNINT_SHIFT))
+
+/*! @brief Set the TWRNINT field to a new value. */
+#define CAN_WR_ESR1_TWRNINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_TWRNINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK), CAN_ESR1_TWRNINT(value)))
+#define CAN_BWR_ESR1_TWRNINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TWRNINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field SYNCH[18] (RO)
+ *
+ * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
+ * bus and able to participate in the communication process. It is set and
+ * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not synchronized to the CAN bus.
+ * - 0b1 - FlexCAN is synchronized to the CAN bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_SYNCH field. */
+#define CAN_RD_ESR1_SYNCH(base) ((CAN_ESR1_REG(base) & CAN_ESR1_SYNCH_MASK) >> CAN_ESR1_SYNCH_SHIFT)
+#define CAN_BRD_ESR1_SYNCH(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_SYNCH_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_IMASK1 - Interrupt Masks 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_IMASK1 - Interrupt Masks 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register allows any number of a range of the 32 Message Buffer
+ * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
+ * bit per buffer, enabling the CPU to determine which buffer generates an
+ * interrupt after a successful transmission or reception, that is, when the
+ * corresponding IFLAG1 bit is set.
+ */
+/*!
+ * @name Constants and macros for entire CAN_IMASK1 register
+ */
+/*@{*/
+#define CAN_RD_IMASK1(base)      (CAN_IMASK1_REG(base))
+#define CAN_WR_IMASK1(base, value) (CAN_IMASK1_REG(base) = (value))
+#define CAN_RMW_IMASK1(base, mask, value) (CAN_WR_IMASK1(base, (CAN_RD_IMASK1(base) & ~(mask)) | (value)))
+#define CAN_SET_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) |  (value)))
+#define CAN_CLR_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) & ~(value)))
+#define CAN_TOG_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_IFLAG1 - Interrupt Flags 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the flags for the 32 Message Buffer interrupts for MB31
+ * to MB0. It contains one interrupt flag bit per buffer. Each successful
+ * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
+ * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
+ * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
+ * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
+ * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
+ * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
+ * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
+ * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
+ * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
+ * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
+ * the FIFO flags must be cleared. The same care must be taken when an RFFN
+ * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
+ * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
+ * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
+ * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
+ * they will remain set and be inconsistent with the number of MBs available.
+ */
+/*!
+ * @name Constants and macros for entire CAN_IFLAG1 register
+ */
+/*@{*/
+#define CAN_RD_IFLAG1(base)      (CAN_IFLAG1_REG(base))
+#define CAN_WR_IFLAG1(base, value) (CAN_IFLAG1_REG(base) = (value))
+#define CAN_RMW_IFLAG1(base, mask, value) (CAN_WR_IFLAG1(base, (CAN_RD_IFLAG1(base) & ~(mask)) | (value)))
+#define CAN_SET_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) |  (value)))
+#define CAN_CLR_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) & ~(value)))
+#define CAN_TOG_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_IFLAG1 bitfields
+ */
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
+ * set.
+ *
+ * Values:
+ * - 0b0 - The corresponding buffer has no occurrence of successfully completed
+ *     transmission or reception when MCR[RFEN]=0.
+ * - 0b1 - The corresponding buffer has successfully completed transmission or
+ *     reception when MCR[RFEN]=0.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF0I field. */
+#define CAN_RD_IFLAG1_BUF0I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF0I_MASK) >> CAN_IFLAG1_BUF0I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF0I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF0I_SHIFT))
+
+/*! @brief Set the BUF0I field to a new value. */
+#define CAN_WR_IFLAG1_BUF0I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF0I(value)))
+#define CAN_BWR_IFLAG1_BUF0I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF0I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
+ * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
+ * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
+ * when MCR[RFEN] is set.
+ *
+ * Values:
+ * - 0b0000 - The corresponding buffer has no occurrence of successfully
+ *     completed transmission or reception when MCR[RFEN]=0.
+ * - 0b0001 - The corresponding buffer has successfully completed transmission
+ *     or reception when MCR[RFEN]=0.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field. */
+#define CAN_RD_IFLAG1_BUF4TO1I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF4TO1I_MASK) >> CAN_IFLAG1_BUF4TO1I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF4TO1I(base) (CAN_RD_IFLAG1_BUF4TO1I(base))
+
+/*! @brief Set the BUF4TO1I field to a new value. */
+#define CAN_WR_IFLAG1_BUF4TO1I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF4TO1I(value)))
+#define CAN_BWR_IFLAG1_BUF4TO1I(base, value) (CAN_WR_IFLAG1_BUF4TO1I(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
+ * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
+ * least one frame is available to be read from the Rx FIFO.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB5 completing transmission/reception when
+ *     MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
+ * - 0b1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
+ *     available in the Rx FIFO when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF5I field. */
+#define CAN_RD_IFLAG1_BUF5I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF5I_MASK) >> CAN_IFLAG1_BUF5I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF5I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF5I_SHIFT))
+
+/*! @brief Set the BUF5I field to a new value. */
+#define CAN_WR_IFLAG1_BUF5I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF5I(value)))
+#define CAN_BWR_IFLAG1_BUF5I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF5I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
+ * when MCR[RFEN] is set. In this case, the flag indicates when the number of
+ * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
+ * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
+ * cleared while the number of unread messages is greater than 4, it does not
+ * assert again until the number of unread messages within the Rx FIFO is decreased
+ * to be equal to or less than 4.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB6 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
+ * - 0b1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     almost full when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF6I field. */
+#define CAN_RD_IFLAG1_BUF6I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF6I_MASK) >> CAN_IFLAG1_BUF6I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF6I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF6I_SHIFT))
+
+/*! @brief Set the BUF6I field to a new value. */
+#define CAN_WR_IFLAG1_BUF6I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF6I(value)))
+#define CAN_BWR_IFLAG1_BUF6I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF6I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
+ * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
+ * because the Rx FIFO is full. Note that the flag will not be asserted when the
+ * Rx FIFO is full and the message was captured by a Mailbox.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB7 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
+ * - 0b1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     overflow when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF7I field. */
+#define CAN_RD_IFLAG1_BUF7I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF7I_MASK) >> CAN_IFLAG1_BUF7I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF7I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF7I_SHIFT))
+
+/*! @brief Set the BUF7I field to a new value. */
+#define CAN_WR_IFLAG1_BUF7I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF7I(value)))
+#define CAN_BWR_IFLAG1_BUF7I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF7I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
+ *
+ * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
+ * MB8.
+ *
+ * Values:
+ * - 0b000000000000000000000000 - The corresponding buffer has no occurrence of
+ *     successfully completed transmission or reception.
+ * - 0b000000000000000000000001 - The corresponding buffer has successfully
+ *     completed transmission or reception.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field. */
+#define CAN_RD_IFLAG1_BUF31TO8I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF31TO8I_MASK) >> CAN_IFLAG1_BUF31TO8I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF31TO8I(base) (CAN_RD_IFLAG1_BUF31TO8I(base))
+
+/*! @brief Set the BUF31TO8I field to a new value. */
+#define CAN_WR_IFLAG1_BUF31TO8I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF31TO8I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK), CAN_IFLAG1_BUF31TO8I(value)))
+#define CAN_BWR_IFLAG1_BUF31TO8I(base, value) (CAN_WR_IFLAG1_BUF31TO8I(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CTRL2 - Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CTRL2 - Control 2 register (RW)
+ *
+ * Reset value: 0x00B00000U
+ *
+ * This register contains control bits for CAN errors, FIFO features, and mode
+ * selection.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CTRL2 register
+ */
+/*@{*/
+#define CAN_RD_CTRL2(base)       (CAN_CTRL2_REG(base))
+#define CAN_WR_CTRL2(base, value) (CAN_CTRL2_REG(base) = (value))
+#define CAN_RMW_CTRL2(base, mask, value) (CAN_WR_CTRL2(base, (CAN_RD_CTRL2(base) & ~(mask)) | (value)))
+#define CAN_SET_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) |  (value)))
+#define CAN_CLR_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) & ~(value)))
+#define CAN_TOG_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CTRL2 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL2, field EACEN[16] (RW)
+ *
+ * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
+ * filters with their corresponding bits in the incoming frame by the matching
+ * process. This bit does not affect matching for Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
+ *     compared despite mask bits.
+ * - 0b1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit
+ *     with their corresponding bits within the incoming frame. Mask bits do apply.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_EACEN field. */
+#define CAN_RD_CTRL2_EACEN(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_EACEN_MASK) >> CAN_CTRL2_EACEN_SHIFT)
+#define CAN_BRD_CTRL2_EACEN(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_EACEN_SHIFT))
+
+/*! @brief Set the EACEN field to a new value. */
+#define CAN_WR_CTRL2_EACEN(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_EACEN_MASK, CAN_CTRL2_EACEN(value)))
+#define CAN_BWR_CTRL2_EACEN(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_EACEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field RRS[17] (RW)
+ *
+ * If this bit is asserted Remote Request Frame is submitted to a matching
+ * process and stored in the corresponding Message Buffer in the same fashion of a
+ * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
+ * negated the Remote Request Frame is submitted to a matching process and an
+ * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
+ * is found with the same ID. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Remote Response Frame is generated.
+ * - 0b1 - Remote Request Frame is stored.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_RRS field. */
+#define CAN_RD_CTRL2_RRS(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_RRS_MASK) >> CAN_CTRL2_RRS_SHIFT)
+#define CAN_BRD_CTRL2_RRS(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_RRS_SHIFT))
+
+/*! @brief Set the RRS field to a new value. */
+#define CAN_WR_CTRL2_RRS(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_RRS_MASK, CAN_CTRL2_RRS(value)))
+#define CAN_BWR_CTRL2_RRS(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_RRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field MRP[18] (RW)
+ *
+ * If this bit is set the matching process starts from the Mailboxes and if no
+ * match occurs the matching continues on the Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Matching starts from Rx FIFO and continues on Mailboxes.
+ * - 0b1 - Matching starts from Mailboxes and continues on Rx FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_MRP field. */
+#define CAN_RD_CTRL2_MRP(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_MRP_MASK) >> CAN_CTRL2_MRP_SHIFT)
+#define CAN_BRD_CTRL2_MRP(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_MRP_SHIFT))
+
+/*! @brief Set the MRP field to a new value. */
+#define CAN_WR_CTRL2_MRP(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_MRP_MASK, CAN_CTRL2_MRP(value)))
+#define CAN_BWR_CTRL2_MRP(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_MRP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field TASD[23:19] (RW)
+ *
+ * This 5-bit field indicates how many CAN bits the Tx arbitration process start
+ * point can be delayed from the first bit of CRC field on CAN bus. This field
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes. This field is useful to optimize the transmit performance based on
+ * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
+ * The duration of an arbitration process, in terms of CAN bits, is directly
+ * proportional to the number of available MBs and CAN baud rate and inversely
+ * proportional to the peripheral clock frequency. The optimal arbitration timing is
+ * that in which the last MB is scanned right before the first bit of the
+ * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
+ * clock ratio is high and the CAN baud rate is low then the arbitration can be
+ * delayed and vice-versa. If TASD is 0 then the arbitration start is not
+ * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
+ * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
+ * the CPU can configure a Tx MB later and less time is reserved for
+ * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
+ * to find winner MBs in time to compete with other nodes for the CAN bus. If the
+ * arbitration ends too much time before the first bit of Intermission field then
+ * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
+ * not the best to be transmitted. The optimal configuration for TASD can be
+ * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
+ * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
+ * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
+ * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
+ * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
+ * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
+ * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
+ * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
+ * Timing" for more details.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_TASD field. */
+#define CAN_RD_CTRL2_TASD(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_TASD_MASK) >> CAN_CTRL2_TASD_SHIFT)
+#define CAN_BRD_CTRL2_TASD(base) (CAN_RD_CTRL2_TASD(base))
+
+/*! @brief Set the TASD field to a new value. */
+#define CAN_WR_CTRL2_TASD(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_TASD_MASK, CAN_CTRL2_TASD(value)))
+#define CAN_BWR_CTRL2_TASD(base, value) (CAN_WR_CTRL2_TASD(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
+ *
+ * This 4-bit field defines the number of Rx FIFO filters, as shown in the
+ * following table. The maximum selectable number of filters is determined by the MCU.
+ * This field can only be written in Freeze mode as it is blocked by hardware in
+ * other modes. This field must not be programmed with values that make the
+ * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
+ * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
+ * a memory space equivalent to two Message Buffers which means that the more
+ * filters are implemented the less Mailboxes will be available. Considering that
+ * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
+ * be programmed with a value correponding to a number of filters not greater
+ * than the number of available memory words which can be calculated as follows:
+ * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
+ * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
+ * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
+ * SETUP_MB value (memory space available) the exceeding ones will not be functional.
+ * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
+ * Filter Table Remaining Available MailboxesThe number of the last remaining
+ * available mailboxes is defined by the least value between the parameter
+ * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
+ * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
+ * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
+ * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
+ * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
+ * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
+ * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
+ * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
+ * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
+ * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
+ * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
+ * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
+ * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
+ * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
+ * 0-37 MB 38-63 Elements 0-31 Elements 32-127
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_RFFN field. */
+#define CAN_RD_CTRL2_RFFN(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT)
+#define CAN_BRD_CTRL2_RFFN(base) (CAN_RD_CTRL2_RFFN(base))
+
+/*! @brief Set the RFFN field to a new value. */
+#define CAN_WR_CTRL2_RFFN(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_RFFN_MASK, CAN_CTRL2_RFFN(value)))
+#define CAN_BWR_CTRL2_RFFN(base, value) (CAN_WR_CTRL2_RFFN(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
+ *
+ * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
+ * can only be written in Freeze mode and has no effect out of Freeze mode.
+ *
+ * Values:
+ * - 0b0 - Maintain the write access restrictions.
+ * - 0b1 - Enable unrestricted write access to FlexCAN memory.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_WRMFRZ field. */
+#define CAN_RD_CTRL2_WRMFRZ(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_WRMFRZ_MASK) >> CAN_CTRL2_WRMFRZ_SHIFT)
+#define CAN_BRD_CTRL2_WRMFRZ(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_WRMFRZ_SHIFT))
+
+/*! @brief Set the WRMFRZ field to a new value. */
+#define CAN_WR_CTRL2_WRMFRZ(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_WRMFRZ_MASK, CAN_CTRL2_WRMFRZ(value)))
+#define CAN_BWR_CTRL2_WRMFRZ(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_WRMFRZ_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ESR2 - Error and Status 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ESR2 - Error and Status 2 register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various interrupt flags and some general status.
+ */
+/*!
+ * @name Constants and macros for entire CAN_ESR2 register
+ */
+/*@{*/
+#define CAN_RD_ESR2(base)        (CAN_ESR2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ESR2 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR2, field IMB[13] (RO)
+ *
+ * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
+ * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
+ * following cases: During arbitration, if an LPTM is found and it is inactive. If
+ * IMB is not asserted and a frame is transmitted successfully. This bit is
+ * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
+ * mechanism have the following behavior: if an MB is successfully transmitted and
+ * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
+ * the index related to the MB just transmitted is loaded into ESR2[LPTM].
+ *
+ * Values:
+ * - 0b0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
+ * - 0b1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox.
+ *     LPTM content is the number of the first one.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_IMB field. */
+#define CAN_RD_ESR2_IMB(base) ((CAN_ESR2_REG(base) & CAN_ESR2_IMB_MASK) >> CAN_ESR2_IMB_SHIFT)
+#define CAN_BRD_ESR2_IMB(base) (BITBAND_ACCESS32(&CAN_ESR2_REG(base), CAN_ESR2_IMB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR2, field VPS[14] (RO)
+ *
+ * This bit indicates whether IMB and LPTM contents are currently valid or not.
+ * VPS is asserted upon every complete Tx arbitration process unless the CPU
+ * writes to Control and Status word of a Mailbox that has already been scanned, that
+ * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
+ * If there is no inactive Mailbox and only one Tx Mailbox that is being
+ * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
+ * arbitration process or upon a write to Control and Status word of any Mailbox.
+ * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
+ * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
+ * in C/S of a MB that is being transmitted (pending abort), or any write attempt
+ * into a Tx MB with IFLAG set is blocked.
+ *
+ * Values:
+ * - 0b0 - Contents of IMB and LPTM are invalid.
+ * - 0b1 - Contents of IMB and LPTM are valid.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_VPS field. */
+#define CAN_RD_ESR2_VPS(base) ((CAN_ESR2_REG(base) & CAN_ESR2_VPS_MASK) >> CAN_ESR2_VPS_SHIFT)
+#define CAN_BRD_ESR2_VPS(base) (BITBAND_ACCESS32(&CAN_ESR2_REG(base), CAN_ESR2_VPS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR2, field LPTM[22:16] (RO)
+ *
+ * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
+ * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
+ * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
+ * negated then the Mailbox indicated is the one that has the greatest arbitration
+ * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
+ * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
+ * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
+ * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
+ * updated with its Mailbox number.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_LPTM field. */
+#define CAN_RD_ESR2_LPTM(base) ((CAN_ESR2_REG(base) & CAN_ESR2_LPTM_MASK) >> CAN_ESR2_LPTM_SHIFT)
+#define CAN_BRD_ESR2_LPTM(base) (CAN_RD_ESR2_LPTM(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CRCR - CRC Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CRCR - CRC Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides information about the CRC of transmitted messages.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CRCR register
+ */
+/*@{*/
+#define CAN_RD_CRCR(base)        (CAN_CRCR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CRCR bitfields
+ */
+
+/*!
+ * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
+ *
+ * This field indicates the CRC value of the last message transmitted. This
+ * field is updated at the same time the Tx Interrupt Flag is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CRCR_TXCRC field. */
+#define CAN_RD_CRCR_TXCRC(base) ((CAN_CRCR_REG(base) & CAN_CRCR_TXCRC_MASK) >> CAN_CRCR_TXCRC_SHIFT)
+#define CAN_BRD_CRCR_TXCRC(base) (CAN_RD_CRCR_TXCRC(base))
+/*@}*/
+
+/*!
+ * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
+ *
+ * This field indicates the number of the Mailbox corresponding to the value in
+ * TXCRC field.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CRCR_MBCRC field. */
+#define CAN_RD_CRCR_MBCRC(base) ((CAN_CRCR_REG(base) & CAN_CRCR_MBCRC_MASK) >> CAN_CRCR_MBCRC_SHIFT)
+#define CAN_BRD_CRCR_MBCRC(base) (CAN_RD_CRCR_MBCRC(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXFGMASK - Rx FIFO Global Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
+ * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
+ * according to CTRL2[RFFN] field setting. This register can only be written in
+ * Freeze mode as it is blocked by hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXFGMASK register
+ */
+/*@{*/
+#define CAN_RD_RXFGMASK(base)    (CAN_RXFGMASK_REG(base))
+#define CAN_WR_RXFGMASK(base, value) (CAN_RXFGMASK_REG(base) = (value))
+#define CAN_RMW_RXFGMASK(base, mask, value) (CAN_WR_RXFGMASK(base, (CAN_RD_RXFGMASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) |  (value)))
+#define CAN_CLR_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) & ~(value)))
+#define CAN_TOG_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXFIR - Rx FIFO Information Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXFIR - Rx FIFO Information Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFIR provides information on Rx FIFO. This register is the port through
+ * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
+ * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
+ * well as its output is updated whenever the output of the Rx FIFO is updated
+ * with the next message. See Section "Rx FIFO" for instructions on reading this
+ * register.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXFIR register
+ */
+/*@{*/
+#define CAN_RD_RXFIR(base)       (CAN_RXFIR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_RXFIR bitfields
+ */
+
+/*!
+ * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
+ *
+ * This field indicates which Identifier Acceptance Filter was hit by the
+ * received message that is in the output of the Rx FIFO. If multiple filters match the
+ * incoming message ID then the first matching IDAF found (lowest number) by the
+ * matching process is indicated. This field is valid only while the
+ * IFLAG[BUF5I] is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_RXFIR_IDHIT field. */
+#define CAN_RD_RXFIR_IDHIT(base) ((CAN_RXFIR_REG(base) & CAN_RXFIR_IDHIT_MASK) >> CAN_RXFIR_IDHIT_SHIFT)
+#define CAN_BRD_RXFIR_IDHIT(base) (CAN_RD_RXFIR_IDHIT(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CS - Message Buffer 0 CS Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CS - Message Buffer 0 CS Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_CS register
+ */
+/*@{*/
+#define CAN_RD_CS(base, index)   (CAN_CS_REG(base, index))
+#define CAN_WR_CS(base, index, value) (CAN_CS_REG(base, index) = (value))
+#define CAN_RMW_CS(base, index, mask, value) (CAN_WR_CS(base, index, (CAN_RD_CS(base, index) & ~(mask)) | (value)))
+#define CAN_SET_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) |  (value)))
+#define CAN_CLR_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) & ~(value)))
+#define CAN_TOG_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CS bitfields
+ */
+
+/*!
+ * @name Register CAN_CS, field TIME_STAMP[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_TIME_STAMP field. */
+#define CAN_RD_CS_TIME_STAMP(base, index) ((CAN_CS_REG(base, index) & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT)
+#define CAN_BRD_CS_TIME_STAMP(base, index) (CAN_RD_CS_TIME_STAMP(base, index))
+
+/*! @brief Set the TIME_STAMP field to a new value. */
+#define CAN_WR_CS_TIME_STAMP(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_TIME_STAMP_MASK, CAN_CS_TIME_STAMP(value)))
+#define CAN_BWR_CS_TIME_STAMP(base, index, value) (CAN_WR_CS_TIME_STAMP(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field DLC[19:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_DLC field. */
+#define CAN_RD_CS_DLC(base, index) ((CAN_CS_REG(base, index) & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT)
+#define CAN_BRD_CS_DLC(base, index) (CAN_RD_CS_DLC(base, index))
+
+/*! @brief Set the DLC field to a new value. */
+#define CAN_WR_CS_DLC(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_DLC_MASK, CAN_CS_DLC(value)))
+#define CAN_BWR_CS_DLC(base, index, value) (CAN_WR_CS_DLC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field RTR[20] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_RTR field. */
+#define CAN_RD_CS_RTR(base, index) ((CAN_CS_REG(base, index) & CAN_CS_RTR_MASK) >> CAN_CS_RTR_SHIFT)
+#define CAN_BRD_CS_RTR(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_RTR_SHIFT))
+
+/*! @brief Set the RTR field to a new value. */
+#define CAN_WR_CS_RTR(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_RTR_MASK, CAN_CS_RTR(value)))
+#define CAN_BWR_CS_RTR(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_RTR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field IDE[21] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_IDE field. */
+#define CAN_RD_CS_IDE(base, index) ((CAN_CS_REG(base, index) & CAN_CS_IDE_MASK) >> CAN_CS_IDE_SHIFT)
+#define CAN_BRD_CS_IDE(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_IDE_SHIFT))
+
+/*! @brief Set the IDE field to a new value. */
+#define CAN_WR_CS_IDE(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_IDE_MASK, CAN_CS_IDE(value)))
+#define CAN_BWR_CS_IDE(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_IDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field SRR[22] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_SRR field. */
+#define CAN_RD_CS_SRR(base, index) ((CAN_CS_REG(base, index) & CAN_CS_SRR_MASK) >> CAN_CS_SRR_SHIFT)
+#define CAN_BRD_CS_SRR(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_SRR_SHIFT))
+
+/*! @brief Set the SRR field to a new value. */
+#define CAN_WR_CS_SRR(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_SRR_MASK, CAN_CS_SRR(value)))
+#define CAN_BWR_CS_SRR(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_SRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field CODE[27:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_CODE field. */
+#define CAN_RD_CS_CODE(base, index) ((CAN_CS_REG(base, index) & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT)
+#define CAN_BRD_CS_CODE(base, index) (CAN_RD_CS_CODE(base, index))
+
+/*! @brief Set the CODE field to a new value. */
+#define CAN_WR_CS_CODE(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_CODE_MASK, CAN_CS_CODE(value)))
+#define CAN_BWR_CS_CODE(base, index, value) (CAN_WR_CS_CODE(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ID - Message Buffer 0 ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ID - Message Buffer 0 ID Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_ID register
+ */
+/*@{*/
+#define CAN_RD_ID(base, index)   (CAN_ID_REG(base, index))
+#define CAN_WR_ID(base, index, value) (CAN_ID_REG(base, index) = (value))
+#define CAN_RMW_ID(base, index, mask, value) (CAN_WR_ID(base, index, (CAN_RD_ID(base, index) & ~(mask)) | (value)))
+#define CAN_SET_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) |  (value)))
+#define CAN_CLR_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) & ~(value)))
+#define CAN_TOG_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ID bitfields
+ */
+
+/*!
+ * @name Register CAN_ID, field EXT[17:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_EXT field. */
+#define CAN_RD_ID_EXT(base, index) ((CAN_ID_REG(base, index) & CAN_ID_EXT_MASK) >> CAN_ID_EXT_SHIFT)
+#define CAN_BRD_ID_EXT(base, index) (CAN_RD_ID_EXT(base, index))
+
+/*! @brief Set the EXT field to a new value. */
+#define CAN_WR_ID_EXT(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_EXT_MASK, CAN_ID_EXT(value)))
+#define CAN_BWR_ID_EXT(base, index, value) (CAN_WR_ID_EXT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ID, field STD[28:18] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_STD field. */
+#define CAN_RD_ID_STD(base, index) ((CAN_ID_REG(base, index) & CAN_ID_STD_MASK) >> CAN_ID_STD_SHIFT)
+#define CAN_BRD_ID_STD(base, index) (CAN_RD_ID_STD(base, index))
+
+/*! @brief Set the STD field to a new value. */
+#define CAN_WR_ID_STD(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_STD_MASK, CAN_ID_STD(value)))
+#define CAN_BWR_ID_STD(base, index, value) (CAN_WR_ID_STD(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ID, field PRIO[31:29] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_PRIO field. */
+#define CAN_RD_ID_PRIO(base, index) ((CAN_ID_REG(base, index) & CAN_ID_PRIO_MASK) >> CAN_ID_PRIO_SHIFT)
+#define CAN_BRD_ID_PRIO(base, index) (CAN_RD_ID_PRIO(base, index))
+
+/*! @brief Set the PRIO field to a new value. */
+#define CAN_WR_ID_PRIO(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_PRIO_MASK, CAN_ID_PRIO(value)))
+#define CAN_BWR_ID_PRIO(base, index, value) (CAN_WR_ID_PRIO(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_WORD0 - Message Buffer 0 WORD0 Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_WORD0 - Message Buffer 0 WORD0 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_WORD0 register
+ */
+/*@{*/
+#define CAN_RD_WORD0(base, index) (CAN_WORD0_REG(base, index))
+#define CAN_WR_WORD0(base, index, value) (CAN_WORD0_REG(base, index) = (value))
+#define CAN_RMW_WORD0(base, index, mask, value) (CAN_WR_WORD0(base, index, (CAN_RD_WORD0(base, index) & ~(mask)) | (value)))
+#define CAN_SET_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) |  (value)))
+#define CAN_CLR_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) & ~(value)))
+#define CAN_TOG_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_WORD0 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_3[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_3 field. */
+#define CAN_RD_WORD0_DATA_BYTE_3(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_3_MASK) >> CAN_WORD0_DATA_BYTE_3_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_3(base, index) (CAN_RD_WORD0_DATA_BYTE_3(base, index))
+
+/*! @brief Set the DATA_BYTE_3 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_3(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_3_MASK, CAN_WORD0_DATA_BYTE_3(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_3(base, index, value) (CAN_WR_WORD0_DATA_BYTE_3(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_2[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_2 field. */
+#define CAN_RD_WORD0_DATA_BYTE_2(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_2_MASK) >> CAN_WORD0_DATA_BYTE_2_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_2(base, index) (CAN_RD_WORD0_DATA_BYTE_2(base, index))
+
+/*! @brief Set the DATA_BYTE_2 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_2(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_2_MASK, CAN_WORD0_DATA_BYTE_2(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_2(base, index, value) (CAN_WR_WORD0_DATA_BYTE_2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_1[23:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_1 field. */
+#define CAN_RD_WORD0_DATA_BYTE_1(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_1_MASK) >> CAN_WORD0_DATA_BYTE_1_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_1(base, index) (CAN_RD_WORD0_DATA_BYTE_1(base, index))
+
+/*! @brief Set the DATA_BYTE_1 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_1(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_1_MASK, CAN_WORD0_DATA_BYTE_1(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_1(base, index, value) (CAN_WR_WORD0_DATA_BYTE_1(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_0[31:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_0 field. */
+#define CAN_RD_WORD0_DATA_BYTE_0(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_0_MASK) >> CAN_WORD0_DATA_BYTE_0_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_0(base, index) (CAN_RD_WORD0_DATA_BYTE_0(base, index))
+
+/*! @brief Set the DATA_BYTE_0 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_0(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_0_MASK, CAN_WORD0_DATA_BYTE_0(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_0(base, index, value) (CAN_WR_WORD0_DATA_BYTE_0(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_WORD1 - Message Buffer 0 WORD1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_WORD1 - Message Buffer 0 WORD1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_WORD1 register
+ */
+/*@{*/
+#define CAN_RD_WORD1(base, index) (CAN_WORD1_REG(base, index))
+#define CAN_WR_WORD1(base, index, value) (CAN_WORD1_REG(base, index) = (value))
+#define CAN_RMW_WORD1(base, index, mask, value) (CAN_WR_WORD1(base, index, (CAN_RD_WORD1(base, index) & ~(mask)) | (value)))
+#define CAN_SET_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) |  (value)))
+#define CAN_CLR_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) & ~(value)))
+#define CAN_TOG_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_WORD1 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_7[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_7 field. */
+#define CAN_RD_WORD1_DATA_BYTE_7(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_7_MASK) >> CAN_WORD1_DATA_BYTE_7_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_7(base, index) (CAN_RD_WORD1_DATA_BYTE_7(base, index))
+
+/*! @brief Set the DATA_BYTE_7 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_7(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_7_MASK, CAN_WORD1_DATA_BYTE_7(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_7(base, index, value) (CAN_WR_WORD1_DATA_BYTE_7(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_6[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_6 field. */
+#define CAN_RD_WORD1_DATA_BYTE_6(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_6_MASK) >> CAN_WORD1_DATA_BYTE_6_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_6(base, index) (CAN_RD_WORD1_DATA_BYTE_6(base, index))
+
+/*! @brief Set the DATA_BYTE_6 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_6(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_6_MASK, CAN_WORD1_DATA_BYTE_6(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_6(base, index, value) (CAN_WR_WORD1_DATA_BYTE_6(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_5[23:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_5 field. */
+#define CAN_RD_WORD1_DATA_BYTE_5(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_5_MASK) >> CAN_WORD1_DATA_BYTE_5_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_5(base, index) (CAN_RD_WORD1_DATA_BYTE_5(base, index))
+
+/*! @brief Set the DATA_BYTE_5 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_5(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_5_MASK, CAN_WORD1_DATA_BYTE_5(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_5(base, index, value) (CAN_WR_WORD1_DATA_BYTE_5(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_4[31:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_4 field. */
+#define CAN_RD_WORD1_DATA_BYTE_4(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_4_MASK) >> CAN_WORD1_DATA_BYTE_4_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_4(base, index) (CAN_RD_WORD1_DATA_BYTE_4(base, index))
+
+/*! @brief Set the DATA_BYTE_4 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_4(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_4_MASK, CAN_WORD1_DATA_BYTE_4(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_4(base, index, value) (CAN_WR_WORD1_DATA_BYTE_4(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXIMR - Rx Individual Mask Registers
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXIMR - Rx Individual Mask Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers are located in RAM. RXIMR are used as acceptance masks for ID
+ * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
+ * register is provided for each available Mailbox, providing ID masking
+ * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
+ * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
+ * Table elements on a one-to-one correspondence depending on the setting of
+ * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
+ * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
+ * are not affected by reset and must be explicitly initialized prior to any
+ * reception.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXIMR register
+ */
+/*@{*/
+#define CAN_RD_RXIMR(base, index) (CAN_RXIMR_REG(base, index))
+#define CAN_WR_RXIMR(base, index, value) (CAN_RXIMR_REG(base, index) = (value))
+#define CAN_RMW_RXIMR(base, index, mask, value) (CAN_WR_RXIMR(base, index, (CAN_RD_RXIMR(base, index) & ~(mask)) | (value)))
+#define CAN_SET_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) |  (value)))
+#define CAN_CLR_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) & ~(value)))
+#define CAN_TOG_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 CAU
+ *
+ * Memory Mapped Cryptographic Acceleration Unit (MMCAU)
+ *
+ * Registers defined in this header file:
+ * - CAU_DIRECT - Direct access register 0
+ * - CAU_LDR_CASR - Status register - Load Register command
+ * - CAU_LDR_CAA - Accumulator register - Load Register command
+ * - CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ * - CAU_STR_CASR - Status register - Store Register command
+ * - CAU_STR_CAA - Accumulator register - Store Register command
+ * - CAU_STR_CA - General Purpose Register 0 - Store Register command
+ * - CAU_ADR_CASR - Status register - Add Register command
+ * - CAU_ADR_CAA - Accumulator register - Add to register command
+ * - CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ * - CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ * - CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ * - CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ * - CAU_XOR_CASR - Status register - Exclusive Or command
+ * - CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ * - CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ * - CAU_ROTL_CASR - Status register - Rotate Left command
+ * - CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ * - CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ * - CAU_AESC_CASR - Status register - AES Column Operation command
+ * - CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ * - CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ * - CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ * - CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ * - CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ */
+
+#define CAU_INSTANCE_COUNT (1U) /*!< Number of instances of the CAU module. */
+#define CAU_IDX (0U) /*!< Instance number for CAU. */
+
+/*******************************************************************************
+ * CAU_DIRECT - Direct access register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_DIRECT - Direct access register 0 (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_DIRECT register
+ */
+/*@{*/
+#define CAU_WR_DIRECT(base, index, value) (CAU_DIRECT_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CASR - Status register - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CASR - Status register - Load Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CASR register
+ */
+/*@{*/
+#define CAU_WR_LDR_CASR(base, value) (CAU_LDR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_LDR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_LDR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_LDR_CASR_IC(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_IC(value)))
+#define CAU_BWR_LDR_CASR_IC(base, value) (CAU_WR_LDR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_LDR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_LDR_CASR_DPE(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_DPE(value)))
+#define CAU_BWR_LDR_CASR_DPE(base, value) (CAU_WR_LDR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_LDR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_LDR_CASR_VER(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_VER(value)))
+#define CAU_BWR_LDR_CASR_VER(base, value) (CAU_WR_LDR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CAA - Accumulator register - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CAA - Accumulator register - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CAA register
+ */
+/*@{*/
+#define CAU_WR_LDR_CAA(base, value) (CAU_LDR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CA - General Purpose Register 0 - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CA register
+ */
+/*@{*/
+#define CAU_WR_LDR_CA(base, index, value) (CAU_LDR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CASR - Status register - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CASR - Status register - Store Register command (RO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CASR register
+ */
+/*@{*/
+#define CAU_RD_STR_CASR(base)    (CAU_STR_CASR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_STR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_STR_CASR, field IC[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_IC field. */
+#define CAU_RD_STR_CASR_IC(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_IC_MASK) >> CAU_STR_CASR_IC_SHIFT)
+#define CAU_BRD_STR_CASR_IC(base) (CAU_RD_STR_CASR_IC(base))
+/*@}*/
+
+/*!
+ * @name Register CAU_STR_CASR, field DPE[1] (RO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_DPE field. */
+#define CAU_RD_STR_CASR_DPE(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_DPE_MASK) >> CAU_STR_CASR_DPE_SHIFT)
+#define CAU_BRD_STR_CASR_DPE(base) (CAU_RD_STR_CASR_DPE(base))
+/*@}*/
+
+/*!
+ * @name Register CAU_STR_CASR, field VER[31:28] (RO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_VER field. */
+#define CAU_RD_STR_CASR_VER(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_VER_MASK) >> CAU_STR_CASR_VER_SHIFT)
+#define CAU_BRD_STR_CASR_VER(base) (CAU_RD_STR_CASR_VER(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CAA - Accumulator register - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CAA - Accumulator register - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CAA register
+ */
+/*@{*/
+#define CAU_RD_STR_CAA(base)     (CAU_STR_CAA_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CA - General Purpose Register 0 - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CA - General Purpose Register 0 - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CA register
+ */
+/*@{*/
+#define CAU_RD_STR_CA(base, index) (CAU_STR_CA_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CASR - Status register - Add Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CASR - Status register - Add Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CASR register
+ */
+/*@{*/
+#define CAU_WR_ADR_CASR(base, value) (CAU_ADR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_ADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_ADR_CASR_IC(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_IC(value)))
+#define CAU_BWR_ADR_CASR_IC(base, value) (CAU_WR_ADR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_ADR_CASR_DPE(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_DPE(value)))
+#define CAU_BWR_ADR_CASR_DPE(base, value) (CAU_WR_ADR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_ADR_CASR_VER(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_VER(value)))
+#define CAU_BWR_ADR_CASR_VER(base, value) (CAU_WR_ADR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CAA - Accumulator register - Add to register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CAA - Accumulator register - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CAA register
+ */
+/*@{*/
+#define CAU_WR_ADR_CAA(base, value) (CAU_ADR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CA - General Purpose Register 0 - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CA register
+ */
+/*@{*/
+#define CAU_WR_ADR_CA(base, index, value) (CAU_ADR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CASR - Status register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CASR register
+ */
+/*@{*/
+#define CAU_WR_RADR_CASR(base, value) (CAU_RADR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_RADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_RADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_RADR_CASR_IC(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_IC(value)))
+#define CAU_BWR_RADR_CASR_IC(base, value) (CAU_WR_RADR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_RADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_RADR_CASR_DPE(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_DPE(value)))
+#define CAU_BWR_RADR_CASR_DPE(base, value) (CAU_WR_RADR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_RADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_RADR_CASR_VER(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_VER(value)))
+#define CAU_BWR_RADR_CASR_VER(base, value) (CAU_WR_RADR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CAA register
+ */
+/*@{*/
+#define CAU_WR_RADR_CAA(base, value) (CAU_RADR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CA register
+ */
+/*@{*/
+#define CAU_WR_RADR_CA(base, index, value) (CAU_RADR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CASR - Status register - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CASR - Status register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CASR register
+ */
+/*@{*/
+#define CAU_WR_XOR_CASR(base, value) (CAU_XOR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_XOR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_XOR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_XOR_CASR_IC(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_IC(value)))
+#define CAU_BWR_XOR_CASR_IC(base, value) (CAU_WR_XOR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_XOR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_XOR_CASR_DPE(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_DPE(value)))
+#define CAU_BWR_XOR_CASR_DPE(base, value) (CAU_WR_XOR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_XOR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_XOR_CASR_VER(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_VER(value)))
+#define CAU_BWR_XOR_CASR_VER(base, value) (CAU_WR_XOR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CAA register
+ */
+/*@{*/
+#define CAU_WR_XOR_CAA(base, value) (CAU_XOR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CA register
+ */
+/*@{*/
+#define CAU_WR_XOR_CA(base, index, value) (CAU_XOR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CASR - Status register - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CASR - Status register - Rotate Left command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CASR register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CASR(base, value) (CAU_ROTL_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_ROTL_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ROTL_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_ROTL_CASR_IC(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_IC(value)))
+#define CAU_BWR_ROTL_CASR_IC(base, value) (CAU_WR_ROTL_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ROTL_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_ROTL_CASR_DPE(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_DPE(value)))
+#define CAU_BWR_ROTL_CASR_DPE(base, value) (CAU_WR_ROTL_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_ROTL_CASR_VER(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_VER(value)))
+#define CAU_BWR_ROTL_CASR_VER(base, value) (CAU_WR_ROTL_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CAA register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CAA(base, value) (CAU_ROTL_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CA register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CA(base, index, value) (CAU_ROTL_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CASR - Status register - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CASR - Status register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CASR register
+ */
+/*@{*/
+#define CAU_WR_AESC_CASR(base, value) (CAU_AESC_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_AESC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_AESC_CASR_IC(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_IC(value)))
+#define CAU_BWR_AESC_CASR_IC(base, value) (CAU_WR_AESC_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_AESC_CASR_DPE(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_DPE(value)))
+#define CAU_BWR_AESC_CASR_DPE(base, value) (CAU_WR_AESC_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_AESC_CASR_VER(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_VER(value)))
+#define CAU_BWR_AESC_CASR_VER(base, value) (CAU_WR_AESC_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CAA register
+ */
+/*@{*/
+#define CAU_WR_AESC_CAA(base, value) (CAU_AESC_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CA register
+ */
+/*@{*/
+#define CAU_WR_AESC_CA(base, index, value) (CAU_AESC_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CASR - Status register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CASR register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CASR(base, value) (CAU_AESIC_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_AESIC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESIC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_AESIC_CASR_IC(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_IC(value)))
+#define CAU_BWR_AESIC_CASR_IC(base, value) (CAU_WR_AESIC_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESIC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_AESIC_CASR_DPE(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_DPE(value)))
+#define CAU_BWR_AESIC_CASR_DPE(base, value) (CAU_WR_AESIC_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_AESIC_CASR_VER(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_VER(value)))
+#define CAU_BWR_AESIC_CASR_VER(base, value) (CAU_WR_AESIC_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CAA register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CAA(base, value) (CAU_AESIC_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CA register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CA(base, index, value) (CAU_AESIC_CA_REG(base, index) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CMP
+ *
+ * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
+ *
+ * Registers defined in this header file:
+ * - CMP_CR0 - CMP Control Register 0
+ * - CMP_CR1 - CMP Control Register 1
+ * - CMP_FPR - CMP Filter Period Register
+ * - CMP_SCR - CMP Status and Control Register
+ * - CMP_DACCR - DAC Control Register
+ * - CMP_MUXCR - MUX Control Register
+ */
+
+#define CMP_INSTANCE_COUNT (3U) /*!< Number of instances of the CMP module. */
+#define CMP0_IDX (0U) /*!< Instance number for CMP0. */
+#define CMP1_IDX (1U) /*!< Instance number for CMP1. */
+#define CMP2_IDX (2U) /*!< Instance number for CMP2. */
+
+/*******************************************************************************
+ * CMP_CR0 - CMP Control Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR0 - CMP Control Register 0 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR0 register
+ */
+/*@{*/
+#define CMP_RD_CR0(base)         (CMP_CR0_REG(base))
+#define CMP_WR_CR0(base, value)  (CMP_CR0_REG(base) = (value))
+#define CMP_RMW_CR0(base, mask, value) (CMP_WR_CR0(base, (CMP_RD_CR0(base) & ~(mask)) | (value)))
+#define CMP_SET_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) |  (value)))
+#define CMP_CLR_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) & ~(value)))
+#define CMP_TOG_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR0 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
+ *
+ * Defines the programmable hysteresis level. The hysteresis values associated
+ * with each level are device-specific. See the Data Sheet of the device for the
+ * exact values.
+ *
+ * Values:
+ * - 0b00 - Level 0
+ * - 0b01 - Level 1
+ * - 0b10 - Level 2
+ * - 0b11 - Level 3
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
+#define CMP_RD_CR0_HYSTCTR(base) ((CMP_CR0_REG(base) & CMP_CR0_HYSTCTR_MASK) >> CMP_CR0_HYSTCTR_SHIFT)
+#define CMP_BRD_CR0_HYSTCTR(base) (CMP_RD_CR0_HYSTCTR(base))
+
+/*! @brief Set the HYSTCTR field to a new value. */
+#define CMP_WR_CR0_HYSTCTR(base, value) (CMP_RMW_CR0(base, CMP_CR0_HYSTCTR_MASK, CMP_CR0_HYSTCTR(value)))
+#define CMP_BWR_CR0_HYSTCTR(base, value) (CMP_WR_CR0_HYSTCTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
+ *
+ * Represents the number of consecutive samples that must agree prior to the
+ * comparator ouput filter accepting a new output state. For information regarding
+ * filter programming and latency, see the Functional descriptionThe CMP module
+ * can be used to compare two analog input voltages applied to INP and INM. .
+ *
+ * Values:
+ * - 0b000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not
+ *     a legal state, and is not recommended. If SE = 0, COUT = COUTA.
+ * - 0b001 - One sample must agree. The comparator output is simply sampled.
+ * - 0b010 - 2 consecutive samples must agree.
+ * - 0b011 - 3 consecutive samples must agree.
+ * - 0b100 - 4 consecutive samples must agree.
+ * - 0b101 - 5 consecutive samples must agree.
+ * - 0b110 - 6 consecutive samples must agree.
+ * - 0b111 - 7 consecutive samples must agree.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
+#define CMP_RD_CR0_FILTER_CNT(base) ((CMP_CR0_REG(base) & CMP_CR0_FILTER_CNT_MASK) >> CMP_CR0_FILTER_CNT_SHIFT)
+#define CMP_BRD_CR0_FILTER_CNT(base) (CMP_RD_CR0_FILTER_CNT(base))
+
+/*! @brief Set the FILTER_CNT field to a new value. */
+#define CMP_WR_CR0_FILTER_CNT(base, value) (CMP_RMW_CR0(base, CMP_CR0_FILTER_CNT_MASK, CMP_CR0_FILTER_CNT(value)))
+#define CMP_BWR_CR0_FILTER_CNT(base, value) (CMP_WR_CR0_FILTER_CNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_CR1 - CMP Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR1 - CMP Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR1 register
+ */
+/*@{*/
+#define CMP_RD_CR1(base)         (CMP_CR1_REG(base))
+#define CMP_WR_CR1(base, value)  (CMP_CR1_REG(base) = (value))
+#define CMP_RMW_CR1(base, mask, value) (CMP_WR_CR1(base, (CMP_RD_CR1(base) & ~(mask)) | (value)))
+#define CMP_SET_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) |  (value)))
+#define CMP_CLR_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) & ~(value)))
+#define CMP_TOG_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR1 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR1, field EN[0] (RW)
+ *
+ * Enables the Analog Comparator module. When the module is not enabled, it
+ * remains in the off state, and consumes no power. When the user selects the same
+ * input from analog mux to the positive and negative port, the comparator is
+ * disabled automatically.
+ *
+ * Values:
+ * - 0b0 - Analog Comparator is disabled.
+ * - 0b1 - Analog Comparator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_EN field. */
+#define CMP_RD_CR1_EN(base)  ((CMP_CR1_REG(base) & CMP_CR1_EN_MASK) >> CMP_CR1_EN_SHIFT)
+#define CMP_BRD_CR1_EN(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT))
+
+/*! @brief Set the EN field to a new value. */
+#define CMP_WR_CR1_EN(base, value) (CMP_RMW_CR1(base, CMP_CR1_EN_MASK, CMP_CR1_EN(value)))
+#define CMP_BWR_CR1_EN(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field OPE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - CMPO is not available on the associated CMPO output pin. If the
+ *     comparator does not own the pin, this field has no effect.
+ * - 0b1 - CMPO is available on the associated CMPO output pin. The comparator
+ *     output (CMPO) is driven out on the associated CMPO output pin if the
+ *     comparator owns the pin. If the comparator does not own the field, this bit has
+ *     no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_OPE field. */
+#define CMP_RD_CR1_OPE(base) ((CMP_CR1_REG(base) & CMP_CR1_OPE_MASK) >> CMP_CR1_OPE_SHIFT)
+#define CMP_BRD_CR1_OPE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT))
+
+/*! @brief Set the OPE field to a new value. */
+#define CMP_WR_CR1_OPE(base, value) (CMP_RMW_CR1(base, CMP_CR1_OPE_MASK, CMP_CR1_OPE(value)))
+#define CMP_BWR_CR1_OPE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field COS[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Set the filtered comparator output (CMPO) to equal COUT.
+ * - 0b1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_COS field. */
+#define CMP_RD_CR1_COS(base) ((CMP_CR1_REG(base) & CMP_CR1_COS_MASK) >> CMP_CR1_COS_SHIFT)
+#define CMP_BRD_CR1_COS(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT))
+
+/*! @brief Set the COS field to a new value. */
+#define CMP_WR_CR1_COS(base, value) (CMP_RMW_CR1(base, CMP_CR1_COS_MASK, CMP_CR1_COS(value)))
+#define CMP_BWR_CR1_COS(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field INV[3] (RW)
+ *
+ * Allows selection of the polarity of the analog comparator function. It is
+ * also driven to the COUT output, on both the device pin and as SCR[COUT], when
+ * OPE=0.
+ *
+ * Values:
+ * - 0b0 - Does not invert the comparator output.
+ * - 0b1 - Inverts the comparator output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_INV field. */
+#define CMP_RD_CR1_INV(base) ((CMP_CR1_REG(base) & CMP_CR1_INV_MASK) >> CMP_CR1_INV_SHIFT)
+#define CMP_BRD_CR1_INV(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT))
+
+/*! @brief Set the INV field to a new value. */
+#define CMP_WR_CR1_INV(base, value) (CMP_RMW_CR1(base, CMP_CR1_INV_MASK, CMP_CR1_INV(value)))
+#define CMP_BWR_CR1_INV(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field PMODE[4] (RW)
+ *
+ * See the electrical specifications table in the device Data Sheet for details.
+ *
+ * Values:
+ * - 0b0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
+ *     output propagation delay and lower current consumption.
+ * - 0b1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has
+ *     faster output propagation delay and higher current consumption.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_PMODE field. */
+#define CMP_RD_CR1_PMODE(base) ((CMP_CR1_REG(base) & CMP_CR1_PMODE_MASK) >> CMP_CR1_PMODE_SHIFT)
+#define CMP_BRD_CR1_PMODE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT))
+
+/*! @brief Set the PMODE field to a new value. */
+#define CMP_WR_CR1_PMODE(base, value) (CMP_RMW_CR1(base, CMP_CR1_PMODE_MASK, CMP_CR1_PMODE(value)))
+#define CMP_BWR_CR1_PMODE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field WE[6] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0b0 - Windowing mode is not selected.
+ * - 0b1 - Windowing mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_WE field. */
+#define CMP_RD_CR1_WE(base)  ((CMP_CR1_REG(base) & CMP_CR1_WE_MASK) >> CMP_CR1_WE_SHIFT)
+#define CMP_BRD_CR1_WE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT))
+
+/*! @brief Set the WE field to a new value. */
+#define CMP_WR_CR1_WE(base, value) (CMP_RMW_CR1(base, CMP_CR1_WE_MASK, CMP_CR1_WE(value)))
+#define CMP_BWR_CR1_WE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field SE[7] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0b0 - Sampling mode is not selected.
+ * - 0b1 - Sampling mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_SE field. */
+#define CMP_RD_CR1_SE(base)  ((CMP_CR1_REG(base) & CMP_CR1_SE_MASK) >> CMP_CR1_SE_SHIFT)
+#define CMP_BRD_CR1_SE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT))
+
+/*! @brief Set the SE field to a new value. */
+#define CMP_WR_CR1_SE(base, value) (CMP_RMW_CR1(base, CMP_CR1_SE_MASK, CMP_CR1_SE(value)))
+#define CMP_BWR_CR1_SE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_FPR - CMP Filter Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_FPR - CMP Filter Period Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_FPR register
+ */
+/*@{*/
+#define CMP_RD_FPR(base)         (CMP_FPR_REG(base))
+#define CMP_WR_FPR(base, value)  (CMP_FPR_REG(base) = (value))
+#define CMP_RMW_FPR(base, mask, value) (CMP_WR_FPR(base, (CMP_RD_FPR(base) & ~(mask)) | (value)))
+#define CMP_SET_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) |  (value)))
+#define CMP_CLR_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) & ~(value)))
+#define CMP_TOG_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_SCR - CMP Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_SCR - CMP Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_SCR register
+ */
+/*@{*/
+#define CMP_RD_SCR(base)         (CMP_SCR_REG(base))
+#define CMP_WR_SCR(base, value)  (CMP_SCR_REG(base) = (value))
+#define CMP_RMW_SCR(base, mask, value) (CMP_WR_SCR(base, (CMP_RD_SCR(base) & ~(mask)) | (value)))
+#define CMP_SET_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) |  (value)))
+#define CMP_CLR_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) & ~(value)))
+#define CMP_TOG_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_SCR bitfields
+ */
+
+/*!
+ * @name Register CMP_SCR, field COUT[0] (RO)
+ *
+ * Returns the current value of the Analog Comparator output, when read. The
+ * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
+ * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_COUT field. */
+#define CMP_RD_SCR_COUT(base) ((CMP_SCR_REG(base) & CMP_SCR_COUT_MASK) >> CMP_SCR_COUT_SHIFT)
+#define CMP_BRD_SCR_COUT(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_COUT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFF[1] (W1C)
+ *
+ * Detects a falling-edge on COUT, when set, during normal operation. CFF is
+ * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0b0 - Falling-edge on COUT has not been detected.
+ * - 0b1 - Falling-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFF field. */
+#define CMP_RD_SCR_CFF(base) ((CMP_SCR_REG(base) & CMP_SCR_CFF_MASK) >> CMP_SCR_CFF_SHIFT)
+#define CMP_BRD_SCR_CFF(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT))
+
+/*! @brief Set the CFF field to a new value. */
+#define CMP_WR_SCR_CFF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_CFF(value)))
+#define CMP_BWR_SCR_CFF(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFR[2] (W1C)
+ *
+ * Detects a rising-edge on COUT, when set, during normal operation. CFR is
+ * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0b0 - Rising-edge on COUT has not been detected.
+ * - 0b1 - Rising-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFR field. */
+#define CMP_RD_SCR_CFR(base) ((CMP_SCR_REG(base) & CMP_SCR_CFR_MASK) >> CMP_SCR_CFR_SHIFT)
+#define CMP_BRD_SCR_CFR(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT))
+
+/*! @brief Set the CFR field to a new value. */
+#define CMP_WR_SCR_CFR(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK), CMP_SCR_CFR(value)))
+#define CMP_BWR_SCR_CFR(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IEF[3] (RW)
+ *
+ * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFF is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled.
+ * - 0b1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IEF field. */
+#define CMP_RD_SCR_IEF(base) ((CMP_SCR_REG(base) & CMP_SCR_IEF_MASK) >> CMP_SCR_IEF_SHIFT)
+#define CMP_BRD_SCR_IEF(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT))
+
+/*! @brief Set the IEF field to a new value. */
+#define CMP_WR_SCR_IEF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IEF_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IEF(value)))
+#define CMP_BWR_SCR_IEF(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IER[4] (RW)
+ *
+ * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFR is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled.
+ * - 0b1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IER field. */
+#define CMP_RD_SCR_IER(base) ((CMP_SCR_REG(base) & CMP_SCR_IER_MASK) >> CMP_SCR_IER_SHIFT)
+#define CMP_BRD_SCR_IER(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT))
+
+/*! @brief Set the IER field to a new value. */
+#define CMP_WR_SCR_IER(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IER_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IER(value)))
+#define CMP_BWR_SCR_IER(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field DMAEN[6] (RW)
+ *
+ * Enables the DMA transfer triggered from the CMP module. When this field is
+ * set, a DMA request is asserted when CFR or CFF is set.
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_DMAEN field. */
+#define CMP_RD_SCR_DMAEN(base) ((CMP_SCR_REG(base) & CMP_SCR_DMAEN_MASK) >> CMP_SCR_DMAEN_SHIFT)
+#define CMP_BRD_SCR_DMAEN(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define CMP_WR_SCR_DMAEN(base, value) (CMP_RMW_SCR(base, (CMP_SCR_DMAEN_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_DMAEN(value)))
+#define CMP_BWR_SCR_DMAEN(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_DACCR - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_DACCR - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_DACCR register
+ */
+/*@{*/
+#define CMP_RD_DACCR(base)       (CMP_DACCR_REG(base))
+#define CMP_WR_DACCR(base, value) (CMP_DACCR_REG(base) = (value))
+#define CMP_RMW_DACCR(base, mask, value) (CMP_WR_DACCR(base, (CMP_RD_DACCR(base) & ~(mask)) | (value)))
+#define CMP_SET_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) |  (value)))
+#define CMP_CLR_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) & ~(value)))
+#define CMP_TOG_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_DACCR bitfields
+ */
+
+/*!
+ * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
+ *
+ * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
+ * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VOSEL field. */
+#define CMP_RD_DACCR_VOSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VOSEL_MASK) >> CMP_DACCR_VOSEL_SHIFT)
+#define CMP_BRD_DACCR_VOSEL(base) (CMP_RD_DACCR_VOSEL(base))
+
+/*! @brief Set the VOSEL field to a new value. */
+#define CMP_WR_DACCR_VOSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VOSEL_MASK, CMP_DACCR_VOSEL(value)))
+#define CMP_BWR_DACCR_VOSEL(base, value) (CMP_WR_DACCR_VOSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field VRSEL[6] (RW)
+ *
+ * Values:
+ * - 0b0 - V is selected as resistor ladder network supply reference V. in1 in
+ * - 0b1 - V is selected as resistor ladder network supply reference V. in2 in
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VRSEL field. */
+#define CMP_RD_DACCR_VRSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VRSEL_MASK) >> CMP_DACCR_VRSEL_SHIFT)
+#define CMP_BRD_DACCR_VRSEL(base) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT))
+
+/*! @brief Set the VRSEL field to a new value. */
+#define CMP_WR_DACCR_VRSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VRSEL_MASK, CMP_DACCR_VRSEL(value)))
+#define CMP_BWR_DACCR_VRSEL(base, value) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field DACEN[7] (RW)
+ *
+ * Enables the DAC. When the DAC is disabled, it is powered down to conserve
+ * power.
+ *
+ * Values:
+ * - 0b0 - DAC is disabled.
+ * - 0b1 - DAC is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_DACEN field. */
+#define CMP_RD_DACCR_DACEN(base) ((CMP_DACCR_REG(base) & CMP_DACCR_DACEN_MASK) >> CMP_DACCR_DACEN_SHIFT)
+#define CMP_BRD_DACCR_DACEN(base) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT))
+
+/*! @brief Set the DACEN field to a new value. */
+#define CMP_WR_DACCR_DACEN(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_DACEN_MASK, CMP_DACCR_DACEN(value)))
+#define CMP_BWR_DACCR_DACEN(base, value) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_MUXCR - MUX Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_MUXCR - MUX Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_MUXCR register
+ */
+/*@{*/
+#define CMP_RD_MUXCR(base)       (CMP_MUXCR_REG(base))
+#define CMP_WR_MUXCR(base, value) (CMP_MUXCR_REG(base) = (value))
+#define CMP_RMW_MUXCR(base, mask, value) (CMP_WR_MUXCR(base, (CMP_RD_MUXCR(base) & ~(mask)) | (value)))
+#define CMP_SET_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) |  (value)))
+#define CMP_CLR_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) & ~(value)))
+#define CMP_TOG_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_MUXCR bitfields
+ */
+
+/*!
+ * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
+ *
+ * Determines which input is selected for the minus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 0b000 - IN0
+ * - 0b001 - IN1
+ * - 0b010 - IN2
+ * - 0b011 - IN3
+ * - 0b100 - IN4
+ * - 0b101 - IN5
+ * - 0b110 - IN6
+ * - 0b111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_MSEL field. */
+#define CMP_RD_MUXCR_MSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_MSEL_MASK) >> CMP_MUXCR_MSEL_SHIFT)
+#define CMP_BRD_MUXCR_MSEL(base) (CMP_RD_MUXCR_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define CMP_WR_MUXCR_MSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_MSEL_MASK, CMP_MUXCR_MSEL(value)))
+#define CMP_BWR_MUXCR_MSEL(base, value) (CMP_WR_MUXCR_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
+ *
+ * Determines which input is selected for the plus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 0b000 - IN0
+ * - 0b001 - IN1
+ * - 0b010 - IN2
+ * - 0b011 - IN3
+ * - 0b100 - IN4
+ * - 0b101 - IN5
+ * - 0b110 - IN6
+ * - 0b111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSEL field. */
+#define CMP_RD_MUXCR_PSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSEL_MASK) >> CMP_MUXCR_PSEL_SHIFT)
+#define CMP_BRD_MUXCR_PSEL(base) (CMP_RD_MUXCR_PSEL(base))
+
+/*! @brief Set the PSEL field to a new value. */
+#define CMP_WR_MUXCR_PSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSEL_MASK, CMP_MUXCR_PSEL(value)))
+#define CMP_BWR_MUXCR_PSEL(base, value) (CMP_WR_MUXCR_PSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSTM[7] (RW)
+ *
+ * This bit is used to enable to MUX pass through mode. Pass through mode is
+ * always available but for some devices this feature must be always disabled due to
+ * the lack of package pins.
+ *
+ * Values:
+ * - 0b0 - Pass Through Mode is disabled.
+ * - 0b1 - Pass Through Mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSTM field. */
+#define CMP_RD_MUXCR_PSTM(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSTM_MASK) >> CMP_MUXCR_PSTM_SHIFT)
+#define CMP_BRD_MUXCR_PSTM(base) (BITBAND_ACCESS8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT))
+
+/*! @brief Set the PSTM field to a new value. */
+#define CMP_WR_MUXCR_PSTM(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSTM_MASK, CMP_MUXCR_PSTM(value)))
+#define CMP_BWR_MUXCR_PSTM(base, value) (BITBAND_ACCESS8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CMT
+ *
+ * Carrier Modulator Transmitter
+ *
+ * Registers defined in this header file:
+ * - CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ * - CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ * - CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ * - CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ * - CMT_OC - CMT Output Control Register
+ * - CMT_MSC - CMT Modulator Status and Control Register
+ * - CMT_CMD1 - CMT Modulator Data Register Mark High
+ * - CMT_CMD2 - CMT Modulator Data Register Mark Low
+ * - CMT_CMD3 - CMT Modulator Data Register Space High
+ * - CMT_CMD4 - CMT Modulator Data Register Space Low
+ * - CMT_PPS - CMT Primary Prescaler Register
+ * - CMT_DMA - CMT Direct Memory Access Register
+ */
+
+#define CMT_INSTANCE_COUNT (1U) /*!< Number of instances of the CMT module. */
+#define CMT_IDX (0U) /*!< Instance number for CMT. */
+
+/*******************************************************************************
+ * CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary high value for generating the carrier
+ * output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGH1 register
+ */
+/*@{*/
+#define CMT_RD_CGH1(base)        (CMT_CGH1_REG(base))
+#define CMT_WR_CGH1(base, value) (CMT_CGH1_REG(base) = (value))
+#define CMT_RMW_CGH1(base, mask, value) (CMT_WR_CGH1(base, (CMT_RD_CGH1(base) & ~(mask)) | (value)))
+#define CMT_SET_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) |  (value)))
+#define CMT_CLR_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) & ~(value)))
+#define CMT_TOG_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary low value for generating the carrier
+ * output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGL1 register
+ */
+/*@{*/
+#define CMT_RD_CGL1(base)        (CMT_CGL1_REG(base))
+#define CMT_WR_CGL1(base, value) (CMT_CGL1_REG(base) = (value))
+#define CMT_RMW_CGL1(base, mask, value) (CMT_WR_CGL1(base, (CMT_RD_CGL1(base) & ~(mask)) | (value)))
+#define CMT_SET_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) |  (value)))
+#define CMT_CLR_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) & ~(value)))
+#define CMT_TOG_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary high value for generating the
+ * carrier output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGH2 register
+ */
+/*@{*/
+#define CMT_RD_CGH2(base)        (CMT_CGH2_REG(base))
+#define CMT_WR_CGH2(base, value) (CMT_CGH2_REG(base) = (value))
+#define CMT_RMW_CGH2(base, mask, value) (CMT_WR_CGH2(base, (CMT_RD_CGH2(base) & ~(mask)) | (value)))
+#define CMT_SET_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) |  (value)))
+#define CMT_CLR_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) & ~(value)))
+#define CMT_TOG_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary low value for generating the
+ * carrier output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGL2 register
+ */
+/*@{*/
+#define CMT_RD_CGL2(base)        (CMT_CGL2_REG(base))
+#define CMT_WR_CGL2(base, value) (CMT_CGL2_REG(base) = (value))
+#define CMT_RMW_CGL2(base, mask, value) (CMT_WR_CGL2(base, (CMT_RD_CGL2(base) & ~(mask)) | (value)))
+#define CMT_SET_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) |  (value)))
+#define CMT_CLR_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) & ~(value)))
+#define CMT_TOG_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_OC - CMT Output Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_OC - CMT Output Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to control the IRO signal of the CMT module.
+ */
+/*!
+ * @name Constants and macros for entire CMT_OC register
+ */
+/*@{*/
+#define CMT_RD_OC(base)          (CMT_OC_REG(base))
+#define CMT_WR_OC(base, value)   (CMT_OC_REG(base) = (value))
+#define CMT_RMW_OC(base, mask, value) (CMT_WR_OC(base, (CMT_RD_OC(base) & ~(mask)) | (value)))
+#define CMT_SET_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) |  (value)))
+#define CMT_CLR_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) & ~(value)))
+#define CMT_TOG_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_OC bitfields
+ */
+
+/*!
+ * @name Register CMT_OC, field IROPEN[5] (RW)
+ *
+ * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
+ * output that drives out either the CMT transmitter output or the state of IROL
+ * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
+ * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
+ * signal is disabled, it is in a high-impedance state and is unable to draw any
+ * current. This signal is disabled during reset.
+ *
+ * Values:
+ * - 0b0 - The IRO signal is disabled.
+ * - 0b1 - The IRO signal is enabled as output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_IROPEN field. */
+#define CMT_RD_OC_IROPEN(base) ((CMT_OC_REG(base) & CMT_OC_IROPEN_MASK) >> CMT_OC_IROPEN_SHIFT)
+#define CMT_BRD_OC_IROPEN(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT))
+
+/*! @brief Set the IROPEN field to a new value. */
+#define CMT_WR_OC_IROPEN(base, value) (CMT_RMW_OC(base, CMT_OC_IROPEN_MASK, CMT_OC_IROPEN(value)))
+#define CMT_BWR_OC_IROPEN(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_OC, field CMTPOL[6] (RW)
+ *
+ * Controls the polarity of the IRO signal.
+ *
+ * Values:
+ * - 0b0 - The IRO signal is active-low.
+ * - 0b1 - The IRO signal is active-high.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_CMTPOL field. */
+#define CMT_RD_OC_CMTPOL(base) ((CMT_OC_REG(base) & CMT_OC_CMTPOL_MASK) >> CMT_OC_CMTPOL_SHIFT)
+#define CMT_BRD_OC_CMTPOL(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT))
+
+/*! @brief Set the CMTPOL field to a new value. */
+#define CMT_WR_OC_CMTPOL(base, value) (CMT_RMW_OC(base, CMT_OC_CMTPOL_MASK, CMT_OC_CMTPOL(value)))
+#define CMT_BWR_OC_CMTPOL(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_OC, field IROL[7] (RW)
+ *
+ * Reads the state of the IRO latch. Writing to IROL changes the state of the
+ * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_IROL field. */
+#define CMT_RD_OC_IROL(base) ((CMT_OC_REG(base) & CMT_OC_IROL_MASK) >> CMT_OC_IROL_SHIFT)
+#define CMT_BRD_OC_IROL(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT))
+
+/*! @brief Set the IROL field to a new value. */
+#define CMT_WR_OC_IROL(base, value) (CMT_RMW_OC(base, CMT_OC_IROL_MASK, CMT_OC_IROL(value)))
+#define CMT_BWR_OC_IROL(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_MSC - CMT Modulator Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_MSC - CMT Modulator Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the modulator and carrier generator enable (MCGEN),
+ * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
+ * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
+ * (EOCF) status bit.
+ */
+/*!
+ * @name Constants and macros for entire CMT_MSC register
+ */
+/*@{*/
+#define CMT_RD_MSC(base)         (CMT_MSC_REG(base))
+#define CMT_WR_MSC(base, value)  (CMT_MSC_REG(base) = (value))
+#define CMT_RMW_MSC(base, mask, value) (CMT_WR_MSC(base, (CMT_RD_MSC(base) & ~(mask)) | (value)))
+#define CMT_SET_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) |  (value)))
+#define CMT_CLR_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) & ~(value)))
+#define CMT_TOG_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_MSC bitfields
+ */
+
+/*!
+ * @name Register CMT_MSC, field MCGEN[0] (RW)
+ *
+ * Setting MCGEN will initialize the carrier generator and modulator and will
+ * enable all clocks. When enabled, the carrier generator and modulator will
+ * function continuously. When MCGEN is cleared, the current modulator cycle will be
+ * allowed to expire before all carrier and modulator clocks are disabled to save
+ * power and the modulator output is forced low. To prevent spurious operation,
+ * the user should initialize all data and control registers before enabling the
+ * system.
+ *
+ * Values:
+ * - 0b0 - Modulator and carrier generator disabled
+ * - 0b1 - Modulator and carrier generator enabled
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_MCGEN field. */
+#define CMT_RD_MSC_MCGEN(base) ((CMT_MSC_REG(base) & CMT_MSC_MCGEN_MASK) >> CMT_MSC_MCGEN_SHIFT)
+#define CMT_BRD_MSC_MCGEN(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT))
+
+/*! @brief Set the MCGEN field to a new value. */
+#define CMT_WR_MSC_MCGEN(base, value) (CMT_RMW_MSC(base, CMT_MSC_MCGEN_MASK, CMT_MSC_MCGEN(value)))
+#define CMT_BWR_MSC_MCGEN(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EOCIE[1] (RW)
+ *
+ * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
+ *
+ * Values:
+ * - 0b0 - CPU interrupt is disabled.
+ * - 0b1 - CPU interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EOCIE field. */
+#define CMT_RD_MSC_EOCIE(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCIE_MASK) >> CMT_MSC_EOCIE_SHIFT)
+#define CMT_BRD_MSC_EOCIE(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT))
+
+/*! @brief Set the EOCIE field to a new value. */
+#define CMT_WR_MSC_EOCIE(base, value) (CMT_RMW_MSC(base, CMT_MSC_EOCIE_MASK, CMT_MSC_EOCIE(value)))
+#define CMT_BWR_MSC_EOCIE(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field FSK[2] (RW)
+ *
+ * Enables FSK operation.
+ *
+ * Values:
+ * - 0b0 - The CMT operates in Time or Baseband mode.
+ * - 0b1 - The CMT operates in FSK mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_FSK field. */
+#define CMT_RD_MSC_FSK(base) ((CMT_MSC_REG(base) & CMT_MSC_FSK_MASK) >> CMT_MSC_FSK_SHIFT)
+#define CMT_BRD_MSC_FSK(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT))
+
+/*! @brief Set the FSK field to a new value. */
+#define CMT_WR_MSC_FSK(base, value) (CMT_RMW_MSC(base, CMT_MSC_FSK_MASK, CMT_MSC_FSK(value)))
+#define CMT_BWR_MSC_FSK(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field BASE[3] (RW)
+ *
+ * When set, BASE disables the carrier generator and forces the carrier output
+ * high for generation of baseband protocols. When BASE is cleared, the carrier
+ * generator is enabled and the carrier output toggles at the frequency determined
+ * by values stored in the carrier data registers. This field is cleared by
+ * reset. This field is not double-buffered and must not be written to during a
+ * transmission.
+ *
+ * Values:
+ * - 0b0 - Baseband mode is disabled.
+ * - 0b1 - Baseband mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_BASE field. */
+#define CMT_RD_MSC_BASE(base) ((CMT_MSC_REG(base) & CMT_MSC_BASE_MASK) >> CMT_MSC_BASE_SHIFT)
+#define CMT_BRD_MSC_BASE(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT))
+
+/*! @brief Set the BASE field to a new value. */
+#define CMT_WR_MSC_BASE(base, value) (CMT_RMW_MSC(base, CMT_MSC_BASE_MASK, CMT_MSC_BASE(value)))
+#define CMT_BWR_MSC_BASE(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EXSPC[4] (RW)
+ *
+ * Enables the extended space operation.
+ *
+ * Values:
+ * - 0b0 - Extended space is disabled.
+ * - 0b1 - Extended space is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EXSPC field. */
+#define CMT_RD_MSC_EXSPC(base) ((CMT_MSC_REG(base) & CMT_MSC_EXSPC_MASK) >> CMT_MSC_EXSPC_SHIFT)
+#define CMT_BRD_MSC_EXSPC(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT))
+
+/*! @brief Set the EXSPC field to a new value. */
+#define CMT_WR_MSC_EXSPC(base, value) (CMT_RMW_MSC(base, CMT_MSC_EXSPC_MASK, CMT_MSC_EXSPC(value)))
+#define CMT_BWR_MSC_EXSPC(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
+ *
+ * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
+ * divided by 2 ,4, or 8 . This field must not be changed during a transmission
+ * because it is not double-buffered.
+ *
+ * Values:
+ * - 0b00 - IF * 1
+ * - 0b01 - IF * 2
+ * - 0b10 - IF * 4
+ * - 0b11 - IF * 8
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_CMTDIV field. */
+#define CMT_RD_MSC_CMTDIV(base) ((CMT_MSC_REG(base) & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT)
+#define CMT_BRD_MSC_CMTDIV(base) (CMT_RD_MSC_CMTDIV(base))
+
+/*! @brief Set the CMTDIV field to a new value. */
+#define CMT_WR_MSC_CMTDIV(base, value) (CMT_RMW_MSC(base, CMT_MSC_CMTDIV_MASK, CMT_MSC_CMTDIV(value)))
+#define CMT_BWR_MSC_CMTDIV(base, value) (CMT_WR_MSC_CMTDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EOCF[7] (RO)
+ *
+ * Sets when: The modulator is not currently active and MCGEN is set to begin
+ * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
+ * set. This is recognized when a match occurs between the contents of the space
+ * period register and the down counter. At this time, the counter is
+ * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
+ * the space period register is loaded with, possibly new contents of the space
+ * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
+ * access of CMD2 or CMD4, or by the DMA transfer.
+ *
+ * Values:
+ * - 0b0 - End of modulation cycle has not occured since the flag last cleared.
+ * - 0b1 - End of modulator cycle has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EOCF field. */
+#define CMT_RD_MSC_EOCF(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCF_MASK) >> CMT_MSC_EOCF_SHIFT)
+#define CMT_BRD_MSC_EOCF(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD1 - CMT Modulator Data Register Mark High
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD1 register
+ */
+/*@{*/
+#define CMT_RD_CMD1(base)        (CMT_CMD1_REG(base))
+#define CMT_WR_CMD1(base, value) (CMT_CMD1_REG(base) = (value))
+#define CMT_RMW_CMD1(base, mask, value) (CMT_WR_CMD1(base, (CMT_RD_CMD1(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) |  (value)))
+#define CMT_CLR_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) & ~(value)))
+#define CMT_TOG_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD2 - CMT Modulator Data Register Mark Low
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD2 register
+ */
+/*@{*/
+#define CMT_RD_CMD2(base)        (CMT_CMD2_REG(base))
+#define CMT_WR_CMD2(base, value) (CMT_CMD2_REG(base) = (value))
+#define CMT_RMW_CMD2(base, mask, value) (CMT_WR_CMD2(base, (CMT_RD_CMD2(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) |  (value)))
+#define CMT_CLR_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) & ~(value)))
+#define CMT_TOG_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD3 - CMT Modulator Data Register Space High
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD3 - CMT Modulator Data Register Space High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD3 register
+ */
+/*@{*/
+#define CMT_RD_CMD3(base)        (CMT_CMD3_REG(base))
+#define CMT_WR_CMD3(base, value) (CMT_CMD3_REG(base) = (value))
+#define CMT_RMW_CMD3(base, mask, value) (CMT_WR_CMD3(base, (CMT_RD_CMD3(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) |  (value)))
+#define CMT_CLR_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) & ~(value)))
+#define CMT_TOG_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD4 - CMT Modulator Data Register Space Low
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD4 register
+ */
+/*@{*/
+#define CMT_RD_CMD4(base)        (CMT_CMD4_REG(base))
+#define CMT_WR_CMD4(base, value) (CMT_CMD4_REG(base) = (value))
+#define CMT_RMW_CMD4(base, mask, value) (CMT_WR_CMD4(base, (CMT_RD_CMD4(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) |  (value)))
+#define CMT_CLR_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) & ~(value)))
+#define CMT_TOG_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_PPS - CMT Primary Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_PPS - CMT Primary Prescaler Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to set the Primary Prescaler Divider field (PPSDIV).
+ */
+/*!
+ * @name Constants and macros for entire CMT_PPS register
+ */
+/*@{*/
+#define CMT_RD_PPS(base)         (CMT_PPS_REG(base))
+#define CMT_WR_PPS(base, value)  (CMT_PPS_REG(base) = (value))
+#define CMT_RMW_PPS(base, mask, value) (CMT_WR_PPS(base, (CMT_RD_PPS(base) & ~(mask)) | (value)))
+#define CMT_SET_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) |  (value)))
+#define CMT_CLR_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) & ~(value)))
+#define CMT_TOG_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_PPS bitfields
+ */
+
+/*!
+ * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
+ *
+ * Divides the CMT clock to generate the Intermediate Frequency clock enable to
+ * the secondary prescaler.
+ *
+ * Values:
+ * - 0b0000 - Bus clock * 1
+ * - 0b0001 - Bus clock * 2
+ * - 0b0010 - Bus clock * 3
+ * - 0b0011 - Bus clock * 4
+ * - 0b0100 - Bus clock * 5
+ * - 0b0101 - Bus clock * 6
+ * - 0b0110 - Bus clock * 7
+ * - 0b0111 - Bus clock * 8
+ * - 0b1000 - Bus clock * 9
+ * - 0b1001 - Bus clock * 10
+ * - 0b1010 - Bus clock * 11
+ * - 0b1011 - Bus clock * 12
+ * - 0b1100 - Bus clock * 13
+ * - 0b1101 - Bus clock * 14
+ * - 0b1110 - Bus clock * 15
+ * - 0b1111 - Bus clock * 16
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_PPS_PPSDIV field. */
+#define CMT_RD_PPS_PPSDIV(base) ((CMT_PPS_REG(base) & CMT_PPS_PPSDIV_MASK) >> CMT_PPS_PPSDIV_SHIFT)
+#define CMT_BRD_PPS_PPSDIV(base) (CMT_RD_PPS_PPSDIV(base))
+
+/*! @brief Set the PPSDIV field to a new value. */
+#define CMT_WR_PPS_PPSDIV(base, value) (CMT_RMW_PPS(base, CMT_PPS_PPSDIV_MASK, CMT_PPS_PPSDIV(value)))
+#define CMT_BWR_PPS_PPSDIV(base, value) (CMT_WR_PPS_PPSDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_DMA - CMT Direct Memory Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_DMA - CMT Direct Memory Access Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to enable/disable direct memory access (DMA).
+ */
+/*!
+ * @name Constants and macros for entire CMT_DMA register
+ */
+/*@{*/
+#define CMT_RD_DMA(base)         (CMT_DMA_REG(base))
+#define CMT_WR_DMA(base, value)  (CMT_DMA_REG(base) = (value))
+#define CMT_RMW_DMA(base, mask, value) (CMT_WR_DMA(base, (CMT_RD_DMA(base) & ~(mask)) | (value)))
+#define CMT_SET_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) |  (value)))
+#define CMT_CLR_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) & ~(value)))
+#define CMT_TOG_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_DMA bitfields
+ */
+
+/*!
+ * @name Register CMT_DMA, field DMA[0] (RW)
+ *
+ * Enables the DMA protocol.
+ *
+ * Values:
+ * - 0b0 - DMA transfer request and done are disabled.
+ * - 0b1 - DMA transfer request and done are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_DMA_DMA field. */
+#define CMT_RD_DMA_DMA(base) ((CMT_DMA_REG(base) & CMT_DMA_DMA_MASK) >> CMT_DMA_DMA_SHIFT)
+#define CMT_BRD_DMA_DMA(base) (BITBAND_ACCESS8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define CMT_WR_DMA_DMA(base, value) (CMT_RMW_DMA(base, CMT_DMA_DMA_MASK, CMT_DMA_DMA(value)))
+#define CMT_BWR_DMA_DMA(base, value) (BITBAND_ACCESS8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CRC
+ *
+ * Cyclic Redundancy Check
+ *
+ * Registers defined in this header file:
+ * - CRC_DATAL - CRC_DATAL register.
+ * - CRC_DATAH - CRC_DATAH register.
+ * - CRC_DATALL - CRC_DATALL register.
+ * - CRC_DATALU - CRC_DATALU register.
+ * - CRC_DATAHL - CRC_DATAHL register.
+ * - CRC_DATAHU - CRC_DATAHU register.
+ * - CRC_DATA - CRC Data register
+ * - CRC_GPOLY - CRC Polynomial register
+ * - CRC_GPOLYL - CRC_GPOLYL register.
+ * - CRC_GPOLYH - CRC_GPOLYH register.
+ * - CRC_GPOLYLL - CRC_GPOLYLL register.
+ * - CRC_GPOLYLU - CRC_GPOLYLU register.
+ * - CRC_GPOLYHL - CRC_GPOLYHL register.
+ * - CRC_GPOLYHU - CRC_GPOLYHU register.
+ * - CRC_CTRL - CRC Control register
+ * - CRC_CTRLHU - CRC_CTRLHU register.
+ */
+
+#define CRC_INSTANCE_COUNT (1U) /*!< Number of instances of the CRC module. */
+#define CRC_IDX (0U) /*!< Instance number for CRC. */
+
+/*******************************************************************************
+ * CRC_DATALL - CRC_DATALL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATALL - CRC_DATALL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATALL register
+ */
+/*@{*/
+#define CRC_RD_DATALL(base)      (CRC_DATALL_REG(base))
+#define CRC_WR_DATALL(base, value) (CRC_DATALL_REG(base) = (value))
+#define CRC_RMW_DATALL(base, mask, value) (CRC_WR_DATALL(base, (CRC_RD_DATALL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) |  (value)))
+#define CRC_CLR_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) & ~(value)))
+#define CRC_TOG_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAL - CRC_DATAL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAL - CRC_DATAL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAL register
+ */
+/*@{*/
+#define CRC_RD_DATAL(base)       (CRC_DATAL_REG(base))
+#define CRC_WR_DATAL(base, value) (CRC_DATAL_REG(base) = (value))
+#define CRC_RMW_DATAL(base, mask, value) (CRC_WR_DATAL(base, (CRC_RD_DATAL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) |  (value)))
+#define CRC_CLR_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) & ~(value)))
+#define CRC_TOG_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATA - CRC Data register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATA - CRC Data register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * The CRC Data register contains the value of the seed, data, and checksum.
+ * When CTRL[WAS] is set, any write to the data register is regarded as the seed
+ * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
+ * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
+ * not used for programming the seed value, and reads of these fields return an
+ * indeterminate value. In 32-bit CRC mode, all fields are used for programming
+ * the seed value. When programming data values, the values can be written 8 bits,
+ * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
+ * data value written first. After all data values are written, the CRC result
+ * can be read from this data register. In 16-bit CRC mode, the CRC result is
+ * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
+ * result. Reads of this register at any time return the intermediate CRC value,
+ * provided the CRC module is configured.
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATA register
+ */
+/*@{*/
+#define CRC_RD_DATA(base)        (CRC_DATA_REG(base))
+#define CRC_WR_DATA(base, value) (CRC_DATA_REG(base) = (value))
+#define CRC_RMW_DATA(base, mask, value) (CRC_WR_DATA(base, (CRC_RD_DATA(base) & ~(mask)) | (value)))
+#define CRC_SET_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) |  (value)))
+#define CRC_CLR_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) & ~(value)))
+#define CRC_TOG_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_DATA bitfields
+ */
+
+/*!
+ * @name Register CRC_DATA, field LL[7:0] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_LL field. */
+#define CRC_RD_DATA_LL(base) ((CRC_DATA_REG(base) & CRC_DATA_LL_MASK) >> CRC_DATA_LL_SHIFT)
+#define CRC_BRD_DATA_LL(base) (CRC_RD_DATA_LL(base))
+
+/*! @brief Set the LL field to a new value. */
+#define CRC_WR_DATA_LL(base, value) (CRC_RMW_DATA(base, CRC_DATA_LL_MASK, CRC_DATA_LL(value)))
+#define CRC_BWR_DATA_LL(base, value) (CRC_WR_DATA_LL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field LU[15:8] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_LU field. */
+#define CRC_RD_DATA_LU(base) ((CRC_DATA_REG(base) & CRC_DATA_LU_MASK) >> CRC_DATA_LU_SHIFT)
+#define CRC_BRD_DATA_LU(base) (CRC_RD_DATA_LU(base))
+
+/*! @brief Set the LU field to a new value. */
+#define CRC_WR_DATA_LU(base, value) (CRC_RMW_DATA(base, CRC_DATA_LU_MASK, CRC_DATA_LU(value)))
+#define CRC_BWR_DATA_LU(base, value) (CRC_WR_DATA_LU(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field HL[23:16] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_HL field. */
+#define CRC_RD_DATA_HL(base) ((CRC_DATA_REG(base) & CRC_DATA_HL_MASK) >> CRC_DATA_HL_SHIFT)
+#define CRC_BRD_DATA_HL(base) (CRC_RD_DATA_HL(base))
+
+/*! @brief Set the HL field to a new value. */
+#define CRC_WR_DATA_HL(base, value) (CRC_RMW_DATA(base, CRC_DATA_HL_MASK, CRC_DATA_HL(value)))
+#define CRC_BWR_DATA_HL(base, value) (CRC_WR_DATA_HL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field HU[31:24] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_HU field. */
+#define CRC_RD_DATA_HU(base) ((CRC_DATA_REG(base) & CRC_DATA_HU_MASK) >> CRC_DATA_HU_SHIFT)
+#define CRC_BRD_DATA_HU(base) (CRC_RD_DATA_HU(base))
+
+/*! @brief Set the HU field to a new value. */
+#define CRC_WR_DATA_HU(base, value) (CRC_RMW_DATA(base, CRC_DATA_HU_MASK, CRC_DATA_HU(value)))
+#define CRC_BWR_DATA_HU(base, value) (CRC_WR_DATA_HU(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATALU - CRC_DATALU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATALU - CRC_DATALU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATALU register
+ */
+/*@{*/
+#define CRC_RD_DATALU(base)      (CRC_DATALU_REG(base))
+#define CRC_WR_DATALU(base, value) (CRC_DATALU_REG(base) = (value))
+#define CRC_RMW_DATALU(base, mask, value) (CRC_WR_DATALU(base, (CRC_RD_DATALU(base) & ~(mask)) | (value)))
+#define CRC_SET_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) |  (value)))
+#define CRC_CLR_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) & ~(value)))
+#define CRC_TOG_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAHL - CRC_DATAHL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAHL - CRC_DATAHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAHL register
+ */
+/*@{*/
+#define CRC_RD_DATAHL(base)      (CRC_DATAHL_REG(base))
+#define CRC_WR_DATAHL(base, value) (CRC_DATAHL_REG(base) = (value))
+#define CRC_RMW_DATAHL(base, mask, value) (CRC_WR_DATAHL(base, (CRC_RD_DATAHL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) |  (value)))
+#define CRC_CLR_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) & ~(value)))
+#define CRC_TOG_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAH - CRC_DATAH register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAH - CRC_DATAH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAH register
+ */
+/*@{*/
+#define CRC_RD_DATAH(base)       (CRC_DATAH_REG(base))
+#define CRC_WR_DATAH(base, value) (CRC_DATAH_REG(base) = (value))
+#define CRC_RMW_DATAH(base, mask, value) (CRC_WR_DATAH(base, (CRC_RD_DATAH(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) |  (value)))
+#define CRC_CLR_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) & ~(value)))
+#define CRC_TOG_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAHU - CRC_DATAHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAHU - CRC_DATAHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAHU register
+ */
+/*@{*/
+#define CRC_RD_DATAHU(base)      (CRC_DATAHU_REG(base))
+#define CRC_WR_DATAHU(base, value) (CRC_DATAHU_REG(base) = (value))
+#define CRC_RMW_DATAHU(base, mask, value) (CRC_WR_DATAHU(base, (CRC_RD_DATAHU(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) |  (value)))
+#define CRC_CLR_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) & ~(value)))
+#define CRC_TOG_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYLL - CRC_GPOLYLL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYLL(base)     (CRC_GPOLYLL_REG(base))
+#define CRC_WR_GPOLYLL(base, value) (CRC_GPOLYLL_REG(base) = (value))
+#define CRC_RMW_GPOLYLL(base, mask, value) (CRC_WR_GPOLYLL(base, (CRC_RD_GPOLYLL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) |  (value)))
+#define CRC_CLR_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) & ~(value)))
+#define CRC_TOG_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLY - CRC Polynomial register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLY - CRC Polynomial register (RW)
+ *
+ * Reset value: 0x00001021U
+ *
+ * This register contains the value of the polynomial for the CRC calculation.
+ * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
+ * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
+ * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
+ * used in both 16- and 32-bit CRC modes.
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLY register
+ */
+/*@{*/
+#define CRC_RD_GPOLY(base)       (CRC_GPOLY_REG(base))
+#define CRC_WR_GPOLY(base, value) (CRC_GPOLY_REG(base) = (value))
+#define CRC_RMW_GPOLY(base, mask, value) (CRC_WR_GPOLY(base, (CRC_RD_GPOLY(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) |  (value)))
+#define CRC_CLR_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) & ~(value)))
+#define CRC_TOG_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_GPOLY bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLY, field LOW[15:0] (RW)
+ *
+ * Writable and readable in both 32-bit and 16-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_GPOLY_LOW field. */
+#define CRC_RD_GPOLY_LOW(base) ((CRC_GPOLY_REG(base) & CRC_GPOLY_LOW_MASK) >> CRC_GPOLY_LOW_SHIFT)
+#define CRC_BRD_GPOLY_LOW(base) (CRC_RD_GPOLY_LOW(base))
+
+/*! @brief Set the LOW field to a new value. */
+#define CRC_WR_GPOLY_LOW(base, value) (CRC_RMW_GPOLY(base, CRC_GPOLY_LOW_MASK, CRC_GPOLY_LOW(value)))
+#define CRC_BWR_GPOLY_LOW(base, value) (CRC_WR_GPOLY_LOW(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
+ *
+ * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
+ * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_GPOLY_HIGH field. */
+#define CRC_RD_GPOLY_HIGH(base) ((CRC_GPOLY_REG(base) & CRC_GPOLY_HIGH_MASK) >> CRC_GPOLY_HIGH_SHIFT)
+#define CRC_BRD_GPOLY_HIGH(base) (CRC_RD_GPOLY_HIGH(base))
+
+/*! @brief Set the HIGH field to a new value. */
+#define CRC_WR_GPOLY_HIGH(base, value) (CRC_RMW_GPOLY(base, CRC_GPOLY_HIGH_MASK, CRC_GPOLY_HIGH(value)))
+#define CRC_BWR_GPOLY_HIGH(base, value) (CRC_WR_GPOLY_HIGH(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYL - CRC_GPOLYL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYL - CRC_GPOLYL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYL(base)      (CRC_GPOLYL_REG(base))
+#define CRC_WR_GPOLYL(base, value) (CRC_GPOLYL_REG(base) = (value))
+#define CRC_RMW_GPOLYL(base, mask, value) (CRC_WR_GPOLYL(base, (CRC_RD_GPOLYL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) |  (value)))
+#define CRC_CLR_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) & ~(value)))
+#define CRC_TOG_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYLU - CRC_GPOLYLU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLU register
+ */
+/*@{*/
+#define CRC_RD_GPOLYLU(base)     (CRC_GPOLYLU_REG(base))
+#define CRC_WR_GPOLYLU(base, value) (CRC_GPOLYLU_REG(base) = (value))
+#define CRC_RMW_GPOLYLU(base, mask, value) (CRC_WR_GPOLYLU(base, (CRC_RD_GPOLYLU(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) |  (value)))
+#define CRC_CLR_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) & ~(value)))
+#define CRC_TOG_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYH - CRC_GPOLYH register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYH - CRC_GPOLYH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYH register
+ */
+/*@{*/
+#define CRC_RD_GPOLYH(base)      (CRC_GPOLYH_REG(base))
+#define CRC_WR_GPOLYH(base, value) (CRC_GPOLYH_REG(base) = (value))
+#define CRC_RMW_GPOLYH(base, mask, value) (CRC_WR_GPOLYH(base, (CRC_RD_GPOLYH(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) |  (value)))
+#define CRC_CLR_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) & ~(value)))
+#define CRC_TOG_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYHL - CRC_GPOLYHL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYHL(base)     (CRC_GPOLYHL_REG(base))
+#define CRC_WR_GPOLYHL(base, value) (CRC_GPOLYHL_REG(base) = (value))
+#define CRC_RMW_GPOLYHL(base, mask, value) (CRC_WR_GPOLYHL(base, (CRC_RD_GPOLYHL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) |  (value)))
+#define CRC_CLR_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) & ~(value)))
+#define CRC_TOG_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYHU - CRC_GPOLYHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHU register
+ */
+/*@{*/
+#define CRC_RD_GPOLYHU(base)     (CRC_GPOLYHU_REG(base))
+#define CRC_WR_GPOLYHU(base, value) (CRC_GPOLYHU_REG(base) = (value))
+#define CRC_RMW_GPOLYHU(base, mask, value) (CRC_WR_GPOLYHU(base, (CRC_RD_GPOLYHU(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) |  (value)))
+#define CRC_CLR_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) & ~(value)))
+#define CRC_TOG_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_CTRL - CRC Control register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_CTRL - CRC Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls the configuration and working of the CRC module.
+ * Appropriate bits must be set before starting a new CRC calculation. A new CRC
+ * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
+ * the CRC data register.
+ */
+/*!
+ * @name Constants and macros for entire CRC_CTRL register
+ */
+/*@{*/
+#define CRC_RD_CTRL(base)        (CRC_CTRL_REG(base))
+#define CRC_WR_CTRL(base, value) (CRC_CTRL_REG(base) = (value))
+#define CRC_RMW_CTRL(base, mask, value) (CRC_WR_CTRL(base, (CRC_RD_CTRL(base) & ~(mask)) | (value)))
+#define CRC_SET_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) |  (value)))
+#define CRC_CLR_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) & ~(value)))
+#define CRC_TOG_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_CTRL bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRL, field TCRC[24] (RW)
+ *
+ * Width of CRC protocol.
+ *
+ * Values:
+ * - 0b0 - 16-bit CRC protocol.
+ * - 0b1 - 32-bit CRC protocol.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TCRC field. */
+#define CRC_RD_CTRL_TCRC(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TCRC_MASK) >> CRC_CTRL_TCRC_SHIFT)
+#define CRC_BRD_CTRL_TCRC(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_TCRC_SHIFT))
+
+/*! @brief Set the TCRC field to a new value. */
+#define CRC_WR_CTRL_TCRC(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TCRC_MASK, CRC_CTRL_TCRC(value)))
+#define CRC_BWR_CTRL_TCRC(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_TCRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field WAS[25] (RW)
+ *
+ * When asserted, a value written to the CRC data register is considered a seed
+ * value. When deasserted, a value written to the CRC data register is taken as
+ * data for CRC computation.
+ *
+ * Values:
+ * - 0b0 - Writes to the CRC data register are data values.
+ * - 0b1 - Writes to the CRC data register are seed values.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_WAS field. */
+#define CRC_RD_CTRL_WAS(base) ((CRC_CTRL_REG(base) & CRC_CTRL_WAS_MASK) >> CRC_CTRL_WAS_SHIFT)
+#define CRC_BRD_CTRL_WAS(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_WAS_SHIFT))
+
+/*! @brief Set the WAS field to a new value. */
+#define CRC_WR_CTRL_WAS(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_WAS_MASK, CRC_CTRL_WAS(value)))
+#define CRC_BWR_CTRL_WAS(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_WAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field FXOR[26] (RW)
+ *
+ * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
+ * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
+ *
+ * Values:
+ * - 0b0 - No XOR on reading.
+ * - 0b1 - Invert or complement the read value of the CRC Data register.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_FXOR field. */
+#define CRC_RD_CTRL_FXOR(base) ((CRC_CTRL_REG(base) & CRC_CTRL_FXOR_MASK) >> CRC_CTRL_FXOR_SHIFT)
+#define CRC_BRD_CTRL_FXOR(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_FXOR_SHIFT))
+
+/*! @brief Set the FXOR field to a new value. */
+#define CRC_WR_CTRL_FXOR(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_FXOR_MASK, CRC_CTRL_FXOR(value)))
+#define CRC_BWR_CTRL_FXOR(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_FXOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field TOTR[29:28] (RW)
+ *
+ * Identifies the transpose configuration of the value read from the CRC Data
+ * register. See the description of the transpose feature for the available
+ * transpose options.
+ *
+ * Values:
+ * - 0b00 - No transposition.
+ * - 0b01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TOTR field. */
+#define CRC_RD_CTRL_TOTR(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT)
+#define CRC_BRD_CTRL_TOTR(base) (CRC_RD_CTRL_TOTR(base))
+
+/*! @brief Set the TOTR field to a new value. */
+#define CRC_WR_CTRL_TOTR(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TOTR_MASK, CRC_CTRL_TOTR(value)))
+#define CRC_BWR_CTRL_TOTR(base, value) (CRC_WR_CTRL_TOTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field TOT[31:30] (RW)
+ *
+ * Defines the transpose configuration of the data written to the CRC data
+ * register. See the description of the transpose feature for the available transpose
+ * options.
+ *
+ * Values:
+ * - 0b00 - No transposition.
+ * - 0b01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TOT field. */
+#define CRC_RD_CTRL_TOT(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TOT_MASK) >> CRC_CTRL_TOT_SHIFT)
+#define CRC_BRD_CTRL_TOT(base) (CRC_RD_CTRL_TOT(base))
+
+/*! @brief Set the TOT field to a new value. */
+#define CRC_WR_CTRL_TOT(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TOT_MASK, CRC_CTRL_TOT(value)))
+#define CRC_BWR_CTRL_TOT(base, value) (CRC_WR_CTRL_TOT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_CTRLHU - CRC_CTRLHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_CTRLHU - CRC_CTRLHU register. (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CRC_CTRLHU register
+ */
+/*@{*/
+#define CRC_RD_CTRLHU(base)      (CRC_CTRLHU_REG(base))
+#define CRC_WR_CTRLHU(base, value) (CRC_CTRLHU_REG(base) = (value))
+#define CRC_RMW_CTRLHU(base, mask, value) (CRC_WR_CTRLHU(base, (CRC_RD_CTRLHU(base) & ~(mask)) | (value)))
+#define CRC_SET_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) |  (value)))
+#define CRC_CLR_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) & ~(value)))
+#define CRC_TOG_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_CTRLHU bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRLHU, field TCRC[0] (RW)
+ *
+ * Values:
+ * - 0b0 - 16-bit CRC protocol.
+ * - 0b1 - 32-bit CRC protocol.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TCRC field. */
+#define CRC_RD_CTRLHU_TCRC(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TCRC_MASK) >> CRC_CTRLHU_TCRC_SHIFT)
+#define CRC_BRD_CTRLHU_TCRC(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_TCRC_SHIFT))
+
+/*! @brief Set the TCRC field to a new value. */
+#define CRC_WR_CTRLHU_TCRC(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TCRC_MASK, CRC_CTRLHU_TCRC(value)))
+#define CRC_BWR_CTRLHU_TCRC(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_TCRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field WAS[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Writes to CRC data register are data values.
+ * - 0b1 - Writes to CRC data reguster are seed values.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_WAS field. */
+#define CRC_RD_CTRLHU_WAS(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_WAS_MASK) >> CRC_CTRLHU_WAS_SHIFT)
+#define CRC_BRD_CTRLHU_WAS(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_WAS_SHIFT))
+
+/*! @brief Set the WAS field to a new value. */
+#define CRC_WR_CTRLHU_WAS(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_WAS_MASK, CRC_CTRLHU_WAS(value)))
+#define CRC_BWR_CTRLHU_WAS(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_WAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field FXOR[2] (RW)
+ *
+ * Values:
+ * - 0b0 - No XOR on reading.
+ * - 0b1 - Invert or complement the read value of CRC data register.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_FXOR field. */
+#define CRC_RD_CTRLHU_FXOR(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_FXOR_MASK) >> CRC_CTRLHU_FXOR_SHIFT)
+#define CRC_BRD_CTRLHU_FXOR(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_FXOR_SHIFT))
+
+/*! @brief Set the FXOR field to a new value. */
+#define CRC_WR_CTRLHU_FXOR(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_FXOR_MASK, CRC_CTRLHU_FXOR(value)))
+#define CRC_BWR_CTRLHU_FXOR(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_FXOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
+ *
+ * Values:
+ * - 0b00 - No Transposition.
+ * - 0b01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TOTR field. */
+#define CRC_RD_CTRLHU_TOTR(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TOTR_MASK) >> CRC_CTRLHU_TOTR_SHIFT)
+#define CRC_BRD_CTRLHU_TOTR(base) (CRC_RD_CTRLHU_TOTR(base))
+
+/*! @brief Set the TOTR field to a new value. */
+#define CRC_WR_CTRLHU_TOTR(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TOTR_MASK, CRC_CTRLHU_TOTR(value)))
+#define CRC_BWR_CTRLHU_TOTR(base, value) (CRC_WR_CTRLHU_TOTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
+ *
+ * Values:
+ * - 0b00 - No Transposition.
+ * - 0b01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TOT field. */
+#define CRC_RD_CTRLHU_TOT(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TOT_MASK) >> CRC_CTRLHU_TOT_SHIFT)
+#define CRC_BRD_CTRLHU_TOT(base) (CRC_RD_CTRLHU_TOT(base))
+
+/*! @brief Set the TOT field to a new value. */
+#define CRC_WR_CTRLHU_TOT(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TOT_MASK, CRC_CTRLHU_TOT(value)))
+#define CRC_BWR_CTRLHU_TOT(base, value) (CRC_WR_CTRLHU_TOT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 DAC
+ *
+ * 12-Bit Digital-to-Analog Converter
+ *
+ * Registers defined in this header file:
+ * - DAC_DATL - DAC Data Low Register
+ * - DAC_DATH - DAC Data High Register
+ * - DAC_SR - DAC Status Register
+ * - DAC_C0 - DAC Control Register
+ * - DAC_C1 - DAC Control Register 1
+ * - DAC_C2 - DAC Control Register 2
+ */
+
+#define DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
+#define DAC0_IDX (0U) /*!< Instance number for DAC0. */
+#define DAC1_IDX (1U) /*!< Instance number for DAC1. */
+
+/*******************************************************************************
+ * DAC_DATL - DAC Data Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATL - DAC Data Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATL register
+ */
+/*@{*/
+#define DAC_RD_DATL(base, index) (DAC_DATL_REG(base, index))
+#define DAC_WR_DATL(base, index, value) (DAC_DATL_REG(base, index) = (value))
+#define DAC_RMW_DATL(base, index, mask, value) (DAC_WR_DATL(base, index, (DAC_RD_DATL(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) |  (value)))
+#define DAC_CLR_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) & ~(value)))
+#define DAC_TOG_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_DATH - DAC Data High Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATH - DAC Data High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATH register
+ */
+/*@{*/
+#define DAC_RD_DATH(base, index) (DAC_DATH_REG(base, index))
+#define DAC_WR_DATH(base, index, value) (DAC_DATH_REG(base, index) = (value))
+#define DAC_RMW_DATH(base, index, mask, value) (DAC_WR_DATH(base, index, (DAC_RD_DATH(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) |  (value)))
+#define DAC_CLR_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) & ~(value)))
+#define DAC_TOG_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_DATH bitfields
+ */
+
+/*!
+ * @name Register DAC_DATH, field DATA1[3:0] (RW)
+ *
+ * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
+ * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
+ * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_DATH_DATA1 field. */
+#define DAC_RD_DATH_DATA1(base, index) ((DAC_DATH_REG(base, index) & DAC_DATH_DATA1_MASK) >> DAC_DATH_DATA1_SHIFT)
+#define DAC_BRD_DATH_DATA1(base, index) (DAC_RD_DATH_DATA1(base, index))
+
+/*! @brief Set the DATA1 field to a new value. */
+#define DAC_WR_DATH_DATA1(base, index, value) (DAC_RMW_DATH(base, index, DAC_DATH_DATA1_MASK, DAC_DATH_DATA1(value)))
+#define DAC_BWR_DATH_DATA1(base, index, value) (DAC_WR_DATH_DATA1(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_SR - DAC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_SR - DAC Status Register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
+ * request is done. Writing 0 to a field clears it whereas writing 1 has no
+ * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
+ * The flags are set only when the data buffer status is changed. Do not use
+ * 32/16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_SR register
+ */
+/*@{*/
+#define DAC_RD_SR(base)          (DAC_SR_REG(base))
+#define DAC_WR_SR(base, value)   (DAC_SR_REG(base) = (value))
+#define DAC_RMW_SR(base, mask, value) (DAC_WR_SR(base, (DAC_RD_SR(base) & ~(mask)) | (value)))
+#define DAC_SET_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) |  (value)))
+#define DAC_CLR_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) & ~(value)))
+#define DAC_TOG_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_SR bitfields
+ */
+
+/*!
+ * @name Register DAC_SR, field DACBFRPBF[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
+ * - 0b1 - The DAC buffer read pointer is equal to C2[DACBFUP].
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
+#define DAC_RD_SR_DACBFRPBF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPBF_MASK) >> DAC_SR_DACBFRPBF_SHIFT)
+#define DAC_BRD_SR_DACBFRPBF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT))
+
+/*! @brief Set the DACBFRPBF field to a new value. */
+#define DAC_WR_SR_DACBFRPBF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPBF_MASK, DAC_SR_DACBFRPBF(value)))
+#define DAC_BWR_SR_DACBFRPBF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFRPTF[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer is not zero.
+ * - 0b1 - The DAC buffer read pointer is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
+#define DAC_RD_SR_DACBFRPTF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPTF_MASK) >> DAC_SR_DACBFRPTF_SHIFT)
+#define DAC_BRD_SR_DACBFRPTF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT))
+
+/*! @brief Set the DACBFRPTF field to a new value. */
+#define DAC_WR_SR_DACBFRPTF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPTF_MASK, DAC_SR_DACBFRPTF(value)))
+#define DAC_BWR_SR_DACBFRPTF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFWMF[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer has not reached the watermark level.
+ * - 0b1 - The DAC buffer read pointer has reached the watermark level.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFWMF field. */
+#define DAC_RD_SR_DACBFWMF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFWMF_MASK) >> DAC_SR_DACBFWMF_SHIFT)
+#define DAC_BRD_SR_DACBFWMF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFWMF_SHIFT))
+
+/*! @brief Set the DACBFWMF field to a new value. */
+#define DAC_WR_SR_DACBFWMF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFWMF_MASK, DAC_SR_DACBFWMF(value)))
+#define DAC_BWR_SR_DACBFWMF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFWMF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C0 - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C0 - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_C0 register
+ */
+/*@{*/
+#define DAC_RD_C0(base)          (DAC_C0_REG(base))
+#define DAC_WR_C0(base, value)   (DAC_C0_REG(base) = (value))
+#define DAC_RMW_C0(base, mask, value) (DAC_WR_C0(base, (DAC_RD_C0(base) & ~(mask)) | (value)))
+#define DAC_SET_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) |  (value)))
+#define DAC_CLR_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) & ~(value)))
+#define DAC_TOG_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C0 bitfields
+ */
+
+/*!
+ * @name Register DAC_C0, field DACBBIEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer bottom flag interrupt is disabled.
+ * - 0b1 - The DAC buffer read pointer bottom flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBBIEN field. */
+#define DAC_RD_C0_DACBBIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBBIEN_MASK) >> DAC_C0_DACBBIEN_SHIFT)
+#define DAC_BRD_C0_DACBBIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT))
+
+/*! @brief Set the DACBBIEN field to a new value. */
+#define DAC_WR_C0_DACBBIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBBIEN_MASK, DAC_C0_DACBBIEN(value)))
+#define DAC_BWR_C0_DACBBIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBTIEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer top flag interrupt is disabled.
+ * - 0b1 - The DAC buffer read pointer top flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBTIEN field. */
+#define DAC_RD_C0_DACBTIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBTIEN_MASK) >> DAC_C0_DACBTIEN_SHIFT)
+#define DAC_BRD_C0_DACBTIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT))
+
+/*! @brief Set the DACBTIEN field to a new value. */
+#define DAC_WR_C0_DACBTIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBTIEN_MASK, DAC_C0_DACBTIEN(value)))
+#define DAC_BWR_C0_DACBTIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBWIEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer watermark interrupt is disabled.
+ * - 0b1 - The DAC buffer watermark interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBWIEN field. */
+#define DAC_RD_C0_DACBWIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBWIEN_MASK) >> DAC_C0_DACBWIEN_SHIFT)
+#define DAC_BRD_C0_DACBWIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBWIEN_SHIFT))
+
+/*! @brief Set the DACBWIEN field to a new value. */
+#define DAC_WR_C0_DACBWIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBWIEN_MASK, DAC_C0_DACBWIEN(value)))
+#define DAC_BWR_C0_DACBWIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBWIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field LPEN[3] (RW)
+ *
+ * See the 12-bit DAC electrical characteristics of the device data sheet for
+ * details on the impact of the modes below.
+ *
+ * Values:
+ * - 0b0 - High-Power mode
+ * - 0b1 - Low-Power mode
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_LPEN field. */
+#define DAC_RD_C0_LPEN(base) ((DAC_C0_REG(base) & DAC_C0_LPEN_MASK) >> DAC_C0_LPEN_SHIFT)
+#define DAC_BRD_C0_LPEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT))
+
+/*! @brief Set the LPEN field to a new value. */
+#define DAC_WR_C0_LPEN(base, value) (DAC_RMW_C0(base, DAC_C0_LPEN_MASK, DAC_C0_LPEN(value)))
+#define DAC_BWR_C0_LPEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
+ *
+ * Active high. This is a write-only field, which always reads 0. If DAC
+ * software trigger is selected and buffer is enabled, writing 1 to this field will
+ * advance the buffer read pointer once.
+ *
+ * Values:
+ * - 0b0 - The DAC soft trigger is not valid.
+ * - 0b1 - The DAC soft trigger is valid.
+ */
+/*@{*/
+/*! @brief Set the DACSWTRG field to a new value. */
+#define DAC_WR_C0_DACSWTRG(base, value) (DAC_RMW_C0(base, DAC_C0_DACSWTRG_MASK, DAC_C0_DACSWTRG(value)))
+#define DAC_BWR_C0_DACSWTRG(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACSWTRG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACTRGSEL[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC hardware trigger is selected.
+ * - 0b1 - The DAC software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
+#define DAC_RD_C0_DACTRGSEL(base) ((DAC_C0_REG(base) & DAC_C0_DACTRGSEL_MASK) >> DAC_C0_DACTRGSEL_SHIFT)
+#define DAC_BRD_C0_DACTRGSEL(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT))
+
+/*! @brief Set the DACTRGSEL field to a new value. */
+#define DAC_WR_C0_DACTRGSEL(base, value) (DAC_RMW_C0(base, DAC_C0_DACTRGSEL_MASK, DAC_C0_DACTRGSEL(value)))
+#define DAC_BWR_C0_DACTRGSEL(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACRFS[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC selects DACREF_1 as the reference voltage.
+ * - 0b1 - The DAC selects DACREF_2 as the reference voltage.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACRFS field. */
+#define DAC_RD_C0_DACRFS(base) ((DAC_C0_REG(base) & DAC_C0_DACRFS_MASK) >> DAC_C0_DACRFS_SHIFT)
+#define DAC_BRD_C0_DACRFS(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT))
+
+/*! @brief Set the DACRFS field to a new value. */
+#define DAC_WR_C0_DACRFS(base, value) (DAC_RMW_C0(base, DAC_C0_DACRFS_MASK, DAC_C0_DACRFS(value)))
+#define DAC_BWR_C0_DACRFS(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACEN[7] (RW)
+ *
+ * Starts the Programmable Reference Generator operation.
+ *
+ * Values:
+ * - 0b0 - The DAC system is disabled.
+ * - 0b1 - The DAC system is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACEN field. */
+#define DAC_RD_C0_DACEN(base) ((DAC_C0_REG(base) & DAC_C0_DACEN_MASK) >> DAC_C0_DACEN_SHIFT)
+#define DAC_BRD_C0_DACEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT))
+
+/*! @brief Set the DACEN field to a new value. */
+#define DAC_WR_C0_DACEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACEN_MASK, DAC_C0_DACEN(value)))
+#define DAC_BWR_C0_DACEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C1 - DAC Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C1 - DAC Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_C1 register
+ */
+/*@{*/
+#define DAC_RD_C1(base)          (DAC_C1_REG(base))
+#define DAC_WR_C1(base, value)   (DAC_C1_REG(base) = (value))
+#define DAC_RMW_C1(base, mask, value) (DAC_WR_C1(base, (DAC_RD_C1(base) & ~(mask)) | (value)))
+#define DAC_SET_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) |  (value)))
+#define DAC_CLR_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) & ~(value)))
+#define DAC_TOG_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C1 bitfields
+ */
+
+/*!
+ * @name Register DAC_C1, field DACBFEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Buffer read pointer is disabled. The converted data is always the
+ *     first word of the buffer.
+ * - 0b1 - Buffer read pointer is enabled. The converted data is the word that
+ *     the read pointer points to. It means converted data can be from any word of
+ *     the buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFEN field. */
+#define DAC_RD_C1_DACBFEN(base) ((DAC_C1_REG(base) & DAC_C1_DACBFEN_MASK) >> DAC_C1_DACBFEN_SHIFT)
+#define DAC_BRD_C1_DACBFEN(base) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT))
+
+/*! @brief Set the DACBFEN field to a new value. */
+#define DAC_WR_C1_DACBFEN(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFEN_MASK, DAC_C1_DACBFEN(value)))
+#define DAC_BWR_C1_DACBFEN(base, value) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFMD[2:1] (RW)
+ *
+ * Values:
+ * - 0b00 - Normal mode
+ * - 0b01 - Swing mode
+ * - 0b10 - One-Time Scan mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFMD field. */
+#define DAC_RD_C1_DACBFMD(base) ((DAC_C1_REG(base) & DAC_C1_DACBFMD_MASK) >> DAC_C1_DACBFMD_SHIFT)
+#define DAC_BRD_C1_DACBFMD(base) (DAC_RD_C1_DACBFMD(base))
+
+/*! @brief Set the DACBFMD field to a new value. */
+#define DAC_WR_C1_DACBFMD(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFMD_MASK, DAC_C1_DACBFMD(value)))
+#define DAC_BWR_C1_DACBFMD(base, value) (DAC_WR_C1_DACBFMD(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFWM[4:3] (RW)
+ *
+ * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
+ * the word defined by this field, which is 1-4 words away from the upper limit
+ * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
+ * watermark interrupt.
+ *
+ * Values:
+ * - 0b00 - 1 word
+ * - 0b01 - 2 words
+ * - 0b10 - 3 words
+ * - 0b11 - 4 words
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFWM field. */
+#define DAC_RD_C1_DACBFWM(base) ((DAC_C1_REG(base) & DAC_C1_DACBFWM_MASK) >> DAC_C1_DACBFWM_SHIFT)
+#define DAC_BRD_C1_DACBFWM(base) (DAC_RD_C1_DACBFWM(base))
+
+/*! @brief Set the DACBFWM field to a new value. */
+#define DAC_WR_C1_DACBFWM(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFWM_MASK, DAC_C1_DACBFWM(value)))
+#define DAC_BWR_C1_DACBFWM(base, value) (DAC_WR_C1_DACBFWM(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DMAEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled. When DMA is enabled, the DMA request will be
+ *     generated by original interrupts. The interrupts will not be presented on this
+ *     module at the same time.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DMAEN field. */
+#define DAC_RD_C1_DMAEN(base) ((DAC_C1_REG(base) & DAC_C1_DMAEN_MASK) >> DAC_C1_DMAEN_SHIFT)
+#define DAC_BRD_C1_DMAEN(base) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define DAC_WR_C1_DMAEN(base, value) (DAC_RMW_C1(base, DAC_C1_DMAEN_MASK, DAC_C1_DMAEN(value)))
+#define DAC_BWR_C1_DMAEN(base, value) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C2 - DAC Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C2 - DAC Control Register 2 (RW)
+ *
+ * Reset value: 0x0FU
+ */
+/*!
+ * @name Constants and macros for entire DAC_C2 register
+ */
+/*@{*/
+#define DAC_RD_C2(base)          (DAC_C2_REG(base))
+#define DAC_WR_C2(base, value)   (DAC_C2_REG(base) = (value))
+#define DAC_RMW_C2(base, mask, value) (DAC_WR_C2(base, (DAC_RD_C2(base) & ~(mask)) | (value)))
+#define DAC_SET_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) |  (value)))
+#define DAC_CLR_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) & ~(value)))
+#define DAC_TOG_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C2 bitfields
+ */
+
+/*!
+ * @name Register DAC_C2, field DACBFUP[3:0] (RW)
+ *
+ * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
+ * exceed it.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFUP field. */
+#define DAC_RD_C2_DACBFUP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFUP_MASK) >> DAC_C2_DACBFUP_SHIFT)
+#define DAC_BRD_C2_DACBFUP(base) (DAC_RD_C2_DACBFUP(base))
+
+/*! @brief Set the DACBFUP field to a new value. */
+#define DAC_WR_C2_DACBFUP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFUP_MASK, DAC_C2_DACBFUP(value)))
+#define DAC_BWR_C2_DACBFUP(base, value) (DAC_WR_C2_DACBFUP(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C2, field DACBFRP[7:4] (RW)
+ *
+ * Keeps the current value of the buffer read pointer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFRP field. */
+#define DAC_RD_C2_DACBFRP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT)
+#define DAC_BRD_C2_DACBFRP(base) (DAC_RD_C2_DACBFRP(base))
+
+/*! @brief Set the DACBFRP field to a new value. */
+#define DAC_WR_C2_DACBFRP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFRP_MASK, DAC_C2_DACBFRP(value)))
+#define DAC_BWR_C2_DACBFRP(base, value) (DAC_WR_C2_DACBFRP(base, value))
+/*@}*/
+
+/*
+ * MK64F12 DMA
+ *
+ * Enhanced direct memory access controller
+ *
+ * Registers defined in this header file:
+ * - DMA_CR - Control Register
+ * - DMA_ES - Error Status Register
+ * - DMA_ERQ - Enable Request Register
+ * - DMA_EEI - Enable Error Interrupt Register
+ * - DMA_CEEI - Clear Enable Error Interrupt Register
+ * - DMA_SEEI - Set Enable Error Interrupt Register
+ * - DMA_CERQ - Clear Enable Request Register
+ * - DMA_SERQ - Set Enable Request Register
+ * - DMA_CDNE - Clear DONE Status Bit Register
+ * - DMA_SSRT - Set START Bit Register
+ * - DMA_CERR - Clear Error Register
+ * - DMA_CINT - Clear Interrupt Request Register
+ * - DMA_INT - Interrupt Request Register
+ * - DMA_ERR - Error Register
+ * - DMA_HRS - Hardware Request Status Register
+ * - DMA_DCHPRI3 - Channel n Priority Register
+ * - DMA_DCHPRI2 - Channel n Priority Register
+ * - DMA_DCHPRI1 - Channel n Priority Register
+ * - DMA_DCHPRI0 - Channel n Priority Register
+ * - DMA_DCHPRI7 - Channel n Priority Register
+ * - DMA_DCHPRI6 - Channel n Priority Register
+ * - DMA_DCHPRI5 - Channel n Priority Register
+ * - DMA_DCHPRI4 - Channel n Priority Register
+ * - DMA_DCHPRI11 - Channel n Priority Register
+ * - DMA_DCHPRI10 - Channel n Priority Register
+ * - DMA_DCHPRI9 - Channel n Priority Register
+ * - DMA_DCHPRI8 - Channel n Priority Register
+ * - DMA_DCHPRI15 - Channel n Priority Register
+ * - DMA_DCHPRI14 - Channel n Priority Register
+ * - DMA_DCHPRI13 - Channel n Priority Register
+ * - DMA_DCHPRI12 - Channel n Priority Register
+ * - DMA_SADDR - TCD Source Address
+ * - DMA_SOFF - TCD Signed Source Address Offset
+ * - DMA_ATTR - TCD Transfer Attributes
+ * - DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ * - DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ * - DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ * - DMA_SLAST - TCD Last Source Address Adjustment
+ * - DMA_DADDR - TCD Destination Address
+ * - DMA_DOFF - TCD Signed Destination Address Offset
+ * - DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ * - DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ * - DMA_CSR - TCD Control and Status
+ * - DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ */
+
+#define DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
+#define DMA_IDX (0U) /*!< Instance number for DMA. */
+
+/*******************************************************************************
+ * DMA_CR - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CR defines the basic operating configuration of the DMA. Arbitration can
+ * be configured to use either a fixed-priority or a round-robin scheme. For
+ * fixed-priority arbitration, the highest priority channel requesting service is
+ * selected to execute. The channel priority registers assign the priorities; see
+ * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
+ * ignored and channels are cycled through (from high to low channel number)
+ * without regard to priority. For correct operation, writes to the CR register must
+ * be performed only when the DMA channels are inactive; that is, when
+ * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
+ * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
+ * minor loop completion. When minor loop offsets are enabled, the minor loop
+ * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
+ * destination address (TCDn_DADDR), or to both prior to the addresses being
+ * written back into the TCD. If the major loop is complete, the minor loop offset is
+ * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
+ * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
+ * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
+ * is used to specify multiple fields: a source enable bit (SMLOE) to specify
+ * the minor loop offset should be applied to the source address (TCDn_SADDR) upon
+ * minor loop completion, a destination enable bit (DMLOE) to specify the minor
+ * loop offset should be applied to the destination address (TCDn_DADDR) upon
+ * minor loop completion, and the sign extended minor loop offset value (MLOFF). The
+ * same offset value (MLOFF) is used for both source and destination minor loop
+ * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
+ * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
+ * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
+ * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
+ * assigned to the NBYTES field.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CR register
+ */
+/*@{*/
+#define DMA_RD_CR(base)          (DMA_CR_REG(base))
+#define DMA_WR_CR(base, value)   (DMA_CR_REG(base) = (value))
+#define DMA_RMW_CR(base, mask, value) (DMA_WR_CR(base, (DMA_RD_CR(base) & ~(mask)) | (value)))
+#define DMA_SET_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) |  (value)))
+#define DMA_CLR_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) & ~(value)))
+#define DMA_TOG_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CR bitfields
+ */
+
+/*!
+ * @name Register DMA_CR, field EDBG[1] (RW)
+ *
+ * Values:
+ * - 0b0 - When in debug mode, the DMA continues to operate.
+ * - 0b1 - When in debug mode, the DMA stalls the start of a new channel.
+ *     Executing channels are allowed to complete. Channel execution resumes when the
+ *     system exits debug mode or the EDBG bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_EDBG field. */
+#define DMA_RD_CR_EDBG(base) ((DMA_CR_REG(base) & DMA_CR_EDBG_MASK) >> DMA_CR_EDBG_SHIFT)
+#define DMA_BRD_CR_EDBG(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EDBG_SHIFT))
+
+/*! @brief Set the EDBG field to a new value. */
+#define DMA_WR_CR_EDBG(base, value) (DMA_RMW_CR(base, DMA_CR_EDBG_MASK, DMA_CR_EDBG(value)))
+#define DMA_BWR_CR_EDBG(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EDBG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field ERCA[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Fixed priority arbitration is used for channel selection .
+ * - 0b1 - Round robin arbitration is used for channel selection .
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_ERCA field. */
+#define DMA_RD_CR_ERCA(base) ((DMA_CR_REG(base) & DMA_CR_ERCA_MASK) >> DMA_CR_ERCA_SHIFT)
+#define DMA_BRD_CR_ERCA(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ERCA_SHIFT))
+
+/*! @brief Set the ERCA field to a new value. */
+#define DMA_WR_CR_ERCA(base, value) (DMA_RMW_CR(base, DMA_CR_ERCA_MASK, DMA_CR_ERCA(value)))
+#define DMA_BWR_CR_ERCA(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ERCA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field HOE[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Any error causes the HALT bit to set. Subsequently, all service
+ *     requests are ignored until the HALT bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_HOE field. */
+#define DMA_RD_CR_HOE(base)  ((DMA_CR_REG(base) & DMA_CR_HOE_MASK) >> DMA_CR_HOE_SHIFT)
+#define DMA_BRD_CR_HOE(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HOE_SHIFT))
+
+/*! @brief Set the HOE field to a new value. */
+#define DMA_WR_CR_HOE(base, value) (DMA_RMW_CR(base, DMA_CR_HOE_MASK, DMA_CR_HOE(value)))
+#define DMA_BWR_CR_HOE(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field HALT[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Stall the start of any new channels. Executing channels are allowed
+ *     to complete. Channel execution resumes when this bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_HALT field. */
+#define DMA_RD_CR_HALT(base) ((DMA_CR_REG(base) & DMA_CR_HALT_MASK) >> DMA_CR_HALT_SHIFT)
+#define DMA_BRD_CR_HALT(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define DMA_WR_CR_HALT(base, value) (DMA_RMW_CR(base, DMA_CR_HALT_MASK, DMA_CR_HALT(value)))
+#define DMA_BWR_CR_HALT(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field CLM[6] (RW)
+ *
+ * Values:
+ * - 0b0 - A minor loop channel link made to itself goes through channel
+ *     arbitration before being activated again.
+ * - 0b1 - A minor loop channel link made to itself does not go through channel
+ *     arbitration before being activated again. Upon minor loop completion, the
+ *     channel activates again if that channel has a minor loop channel link
+ *     enabled and the link channel is itself. This effectively applies the minor
+ *     loop offsets and restarts the next minor loop.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_CLM field. */
+#define DMA_RD_CR_CLM(base)  ((DMA_CR_REG(base) & DMA_CR_CLM_MASK) >> DMA_CR_CLM_SHIFT)
+#define DMA_BRD_CR_CLM(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CLM_SHIFT))
+
+/*! @brief Set the CLM field to a new value. */
+#define DMA_WR_CR_CLM(base, value) (DMA_RMW_CR(base, DMA_CR_CLM_MASK, DMA_CR_CLM(value)))
+#define DMA_BWR_CR_CLM(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CLM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field EMLM[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
+ * - 0b1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
+ *     an offset field, and the NBYTES field. The individual enable fields allow
+ *     the minor loop offset to be applied to the source address, the
+ *     destination address, or both. The NBYTES field is reduced when either offset is
+ *     enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_EMLM field. */
+#define DMA_RD_CR_EMLM(base) ((DMA_CR_REG(base) & DMA_CR_EMLM_MASK) >> DMA_CR_EMLM_SHIFT)
+#define DMA_BRD_CR_EMLM(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EMLM_SHIFT))
+
+/*! @brief Set the EMLM field to a new value. */
+#define DMA_WR_CR_EMLM(base, value) (DMA_RMW_CR(base, DMA_CR_EMLM_MASK, DMA_CR_EMLM(value)))
+#define DMA_BWR_CR_EMLM(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EMLM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field ECX[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Cancel the remaining data transfer in the same fashion as the CX bit.
+ *     Stop the executing channel and force the minor loop to finish. The cancel
+ *     takes effect after the last write of the current read/write sequence. The
+ *     ECX bit clears itself after the cancel is honored. In addition to
+ *     cancelling the transfer, ECX treats the cancel as an error condition, thus
+ *     updating the Error Status register (DMAx_ES) and generating an optional error
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_ECX field. */
+#define DMA_RD_CR_ECX(base)  ((DMA_CR_REG(base) & DMA_CR_ECX_MASK) >> DMA_CR_ECX_SHIFT)
+#define DMA_BRD_CR_ECX(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ECX_SHIFT))
+
+/*! @brief Set the ECX field to a new value. */
+#define DMA_WR_CR_ECX(base, value) (DMA_RMW_CR(base, DMA_CR_ECX_MASK, DMA_CR_ECX(value)))
+#define DMA_BWR_CR_ECX(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ECX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field CX[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Cancel the remaining data transfer. Stop the executing channel and
+ *     force the minor loop to finish. The cancel takes effect after the last write
+ *     of the current read/write sequence. The CX bit clears itself after the
+ *     cancel has been honored. This cancel retires the channel normally as if the
+ *     minor loop was completed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_CX field. */
+#define DMA_RD_CR_CX(base)   ((DMA_CR_REG(base) & DMA_CR_CX_MASK) >> DMA_CR_CX_SHIFT)
+#define DMA_BRD_CR_CX(base)  (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CX_SHIFT))
+
+/*! @brief Set the CX field to a new value. */
+#define DMA_WR_CR_CX(base, value) (DMA_RMW_CR(base, DMA_CR_CX_MASK, DMA_CR_CX(value)))
+#define DMA_BWR_CR_CX(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CX_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ES - Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ES - Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ES provides information concerning the last recorded channel error.
+ * Channel errors can be caused by: A configuration error, that is: An illegal setting
+ * in the transfer-control descriptor, or An illegal priority register setting
+ * in fixed-arbitration An error termination to a bus master read or write cycle
+ * See the Error Reporting and Handling section for more details.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ES register
+ */
+/*@{*/
+#define DMA_RD_ES(base)          (DMA_ES_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ES bitfields
+ */
+
+/*!
+ * @name Register DMA_ES, field DBE[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination bus error
+ * - 0b1 - The last recorded error was a bus error on a destination write
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DBE field. */
+#define DMA_RD_ES_DBE(base)  ((DMA_ES_REG(base) & DMA_ES_DBE_MASK) >> DMA_ES_DBE_SHIFT)
+#define DMA_BRD_ES_DBE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SBE[1] (RO)
+ *
+ * Values:
+ * - 0b0 - No source bus error
+ * - 0b1 - The last recorded error was a bus error on a source read
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SBE field. */
+#define DMA_RD_ES_SBE(base)  ((DMA_ES_REG(base) & DMA_ES_SBE_MASK) >> DMA_ES_SBE_SHIFT)
+#define DMA_BRD_ES_SBE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SGE[2] (RO)
+ *
+ * Values:
+ * - 0b0 - No scatter/gather configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DLASTSGA field. This field is checked at the beginning of a
+ *     scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled.
+ *     TCDn_DLASTSGA is not on a 32 byte boundary.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SGE field. */
+#define DMA_RD_ES_SGE(base)  ((DMA_ES_REG(base) & DMA_ES_SGE_MASK) >> DMA_ES_SGE_SHIFT)
+#define DMA_BRD_ES_SGE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SGE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field NCE[3] (RO)
+ *
+ * Values:
+ * - 0b0 - No NBYTES/CITER configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
+ *     TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
+ *     TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_NCE field. */
+#define DMA_RD_ES_NCE(base)  ((DMA_ES_REG(base) & DMA_ES_NCE_MASK) >> DMA_ES_NCE_SHIFT)
+#define DMA_BRD_ES_NCE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_NCE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field DOE[4] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination offset configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DOE field. */
+#define DMA_RD_ES_DOE(base)  ((DMA_ES_REG(base) & DMA_ES_DOE_MASK) >> DMA_ES_DOE_SHIFT)
+#define DMA_BRD_ES_DOE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field DAE[5] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination address configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DAE field. */
+#define DMA_RD_ES_DAE(base)  ((DMA_ES_REG(base) & DMA_ES_DAE_MASK) >> DMA_ES_DAE_SHIFT)
+#define DMA_BRD_ES_DAE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DAE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SOE[6] (RO)
+ *
+ * Values:
+ * - 0b0 - No source offset configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SOE field. */
+#define DMA_RD_ES_SOE(base)  ((DMA_ES_REG(base) & DMA_ES_SOE_MASK) >> DMA_ES_SOE_SHIFT)
+#define DMA_BRD_ES_SOE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SAE[7] (RO)
+ *
+ * Values:
+ * - 0b0 - No source address configuration error.
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SAE field. */
+#define DMA_RD_ES_SAE(base)  ((DMA_ES_REG(base) & DMA_ES_SAE_MASK) >> DMA_ES_SAE_SHIFT)
+#define DMA_BRD_ES_SAE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SAE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field ERRCHN[11:8] (RO)
+ *
+ * The channel number of the last recorded error (excluding CPE errors) or last
+ * recorded error canceled transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_ERRCHN field. */
+#define DMA_RD_ES_ERRCHN(base) ((DMA_ES_REG(base) & DMA_ES_ERRCHN_MASK) >> DMA_ES_ERRCHN_SHIFT)
+#define DMA_BRD_ES_ERRCHN(base) (DMA_RD_ES_ERRCHN(base))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field CPE[14] (RO)
+ *
+ * Values:
+ * - 0b0 - No channel priority error
+ * - 0b1 - The last recorded error was a configuration error in the channel
+ *     priorities . Channel priorities are not unique.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_CPE field. */
+#define DMA_RD_ES_CPE(base)  ((DMA_ES_REG(base) & DMA_ES_CPE_MASK) >> DMA_ES_CPE_SHIFT)
+#define DMA_BRD_ES_CPE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_CPE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field ECX[16] (RO)
+ *
+ * Values:
+ * - 0b0 - No canceled transfers
+ * - 0b1 - The last recorded entry was a canceled transfer by the error cancel
+ *     transfer input
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_ECX field. */
+#define DMA_RD_ES_ECX(base)  ((DMA_ES_REG(base) & DMA_ES_ECX_MASK) >> DMA_ES_ECX_SHIFT)
+#define DMA_BRD_ES_ECX(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_ECX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field VLD[31] (RO)
+ *
+ * Logical OR of all ERR status bits
+ *
+ * Values:
+ * - 0b0 - No ERR bits are set
+ * - 0b1 - At least one ERR bit is set indicating a valid error exists that has
+ *     not been cleared
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_VLD field. */
+#define DMA_RD_ES_VLD(base)  ((DMA_ES_REG(base) & DMA_ES_VLD_MASK) >> DMA_ES_VLD_SHIFT)
+#define DMA_BRD_ES_VLD(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_VLD_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ERQ - Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ERQ - Enable Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERQ register provides a bit map for the 16 implemented channels to enable
+ * the request signal for each channel. The state of any given channel enable is
+ * directly affected by writes to this register; it is also affected by writes
+ * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
+ * for a single channel can easily be modified without needing to perform a
+ * read-modify-write sequence to the ERQ. DMA request input signals and this enable
+ * request flag must be asserted before a channel's hardware service request is
+ * accepted. The state of the DMA enable request flag does not affect a channel
+ * service request made explicitly through software or a linked channel request.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ERQ register
+ */
+/*@{*/
+#define DMA_RD_ERQ(base)         (DMA_ERQ_REG(base))
+#define DMA_WR_ERQ(base, value)  (DMA_ERQ_REG(base) = (value))
+#define DMA_RMW_ERQ(base, mask, value) (DMA_WR_ERQ(base, (DMA_RD_ERQ(base) & ~(mask)) | (value)))
+#define DMA_SET_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) |  (value)))
+#define DMA_CLR_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) & ~(value)))
+#define DMA_TOG_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_ERQ, field ERQ0[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ0 field. */
+#define DMA_RD_ERQ_ERQ0(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ0_MASK) >> DMA_ERQ_ERQ0_SHIFT)
+#define DMA_BRD_ERQ_ERQ0(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ0_SHIFT))
+
+/*! @brief Set the ERQ0 field to a new value. */
+#define DMA_WR_ERQ_ERQ0(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ0_MASK, DMA_ERQ_ERQ0(value)))
+#define DMA_BWR_ERQ_ERQ0(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ1[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ1 field. */
+#define DMA_RD_ERQ_ERQ1(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ1_MASK) >> DMA_ERQ_ERQ1_SHIFT)
+#define DMA_BRD_ERQ_ERQ1(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ1_SHIFT))
+
+/*! @brief Set the ERQ1 field to a new value. */
+#define DMA_WR_ERQ_ERQ1(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ1_MASK, DMA_ERQ_ERQ1(value)))
+#define DMA_BWR_ERQ_ERQ1(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ2[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ2 field. */
+#define DMA_RD_ERQ_ERQ2(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ2_MASK) >> DMA_ERQ_ERQ2_SHIFT)
+#define DMA_BRD_ERQ_ERQ2(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ2_SHIFT))
+
+/*! @brief Set the ERQ2 field to a new value. */
+#define DMA_WR_ERQ_ERQ2(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ2_MASK, DMA_ERQ_ERQ2(value)))
+#define DMA_BWR_ERQ_ERQ2(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ3[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ3 field. */
+#define DMA_RD_ERQ_ERQ3(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ3_MASK) >> DMA_ERQ_ERQ3_SHIFT)
+#define DMA_BRD_ERQ_ERQ3(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ3_SHIFT))
+
+/*! @brief Set the ERQ3 field to a new value. */
+#define DMA_WR_ERQ_ERQ3(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ3_MASK, DMA_ERQ_ERQ3(value)))
+#define DMA_BWR_ERQ_ERQ3(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ4[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ4 field. */
+#define DMA_RD_ERQ_ERQ4(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ4_MASK) >> DMA_ERQ_ERQ4_SHIFT)
+#define DMA_BRD_ERQ_ERQ4(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ4_SHIFT))
+
+/*! @brief Set the ERQ4 field to a new value. */
+#define DMA_WR_ERQ_ERQ4(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ4_MASK, DMA_ERQ_ERQ4(value)))
+#define DMA_BWR_ERQ_ERQ4(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ5[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ5 field. */
+#define DMA_RD_ERQ_ERQ5(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ5_MASK) >> DMA_ERQ_ERQ5_SHIFT)
+#define DMA_BRD_ERQ_ERQ5(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ5_SHIFT))
+
+/*! @brief Set the ERQ5 field to a new value. */
+#define DMA_WR_ERQ_ERQ5(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ5_MASK, DMA_ERQ_ERQ5(value)))
+#define DMA_BWR_ERQ_ERQ5(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ6[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ6 field. */
+#define DMA_RD_ERQ_ERQ6(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ6_MASK) >> DMA_ERQ_ERQ6_SHIFT)
+#define DMA_BRD_ERQ_ERQ6(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ6_SHIFT))
+
+/*! @brief Set the ERQ6 field to a new value. */
+#define DMA_WR_ERQ_ERQ6(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ6_MASK, DMA_ERQ_ERQ6(value)))
+#define DMA_BWR_ERQ_ERQ6(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ7[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ7 field. */
+#define DMA_RD_ERQ_ERQ7(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ7_MASK) >> DMA_ERQ_ERQ7_SHIFT)
+#define DMA_BRD_ERQ_ERQ7(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ7_SHIFT))
+
+/*! @brief Set the ERQ7 field to a new value. */
+#define DMA_WR_ERQ_ERQ7(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ7_MASK, DMA_ERQ_ERQ7(value)))
+#define DMA_BWR_ERQ_ERQ7(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ8[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ8 field. */
+#define DMA_RD_ERQ_ERQ8(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ8_MASK) >> DMA_ERQ_ERQ8_SHIFT)
+#define DMA_BRD_ERQ_ERQ8(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ8_SHIFT))
+
+/*! @brief Set the ERQ8 field to a new value. */
+#define DMA_WR_ERQ_ERQ8(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ8_MASK, DMA_ERQ_ERQ8(value)))
+#define DMA_BWR_ERQ_ERQ8(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ9[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ9 field. */
+#define DMA_RD_ERQ_ERQ9(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ9_MASK) >> DMA_ERQ_ERQ9_SHIFT)
+#define DMA_BRD_ERQ_ERQ9(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ9_SHIFT))
+
+/*! @brief Set the ERQ9 field to a new value. */
+#define DMA_WR_ERQ_ERQ9(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ9_MASK, DMA_ERQ_ERQ9(value)))
+#define DMA_BWR_ERQ_ERQ9(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ10[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ10 field. */
+#define DMA_RD_ERQ_ERQ10(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ10_MASK) >> DMA_ERQ_ERQ10_SHIFT)
+#define DMA_BRD_ERQ_ERQ10(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ10_SHIFT))
+
+/*! @brief Set the ERQ10 field to a new value. */
+#define DMA_WR_ERQ_ERQ10(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ10_MASK, DMA_ERQ_ERQ10(value)))
+#define DMA_BWR_ERQ_ERQ10(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ11[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ11 field. */
+#define DMA_RD_ERQ_ERQ11(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ11_MASK) >> DMA_ERQ_ERQ11_SHIFT)
+#define DMA_BRD_ERQ_ERQ11(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ11_SHIFT))
+
+/*! @brief Set the ERQ11 field to a new value. */
+#define DMA_WR_ERQ_ERQ11(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ11_MASK, DMA_ERQ_ERQ11(value)))
+#define DMA_BWR_ERQ_ERQ11(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ12[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ12 field. */
+#define DMA_RD_ERQ_ERQ12(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ12_MASK) >> DMA_ERQ_ERQ12_SHIFT)
+#define DMA_BRD_ERQ_ERQ12(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ12_SHIFT))
+
+/*! @brief Set the ERQ12 field to a new value. */
+#define DMA_WR_ERQ_ERQ12(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ12_MASK, DMA_ERQ_ERQ12(value)))
+#define DMA_BWR_ERQ_ERQ12(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ13[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ13 field. */
+#define DMA_RD_ERQ_ERQ13(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ13_MASK) >> DMA_ERQ_ERQ13_SHIFT)
+#define DMA_BRD_ERQ_ERQ13(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ13_SHIFT))
+
+/*! @brief Set the ERQ13 field to a new value. */
+#define DMA_WR_ERQ_ERQ13(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ13_MASK, DMA_ERQ_ERQ13(value)))
+#define DMA_BWR_ERQ_ERQ13(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ14[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ14 field. */
+#define DMA_RD_ERQ_ERQ14(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ14_MASK) >> DMA_ERQ_ERQ14_SHIFT)
+#define DMA_BRD_ERQ_ERQ14(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ14_SHIFT))
+
+/*! @brief Set the ERQ14 field to a new value. */
+#define DMA_WR_ERQ_ERQ14(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ14_MASK, DMA_ERQ_ERQ14(value)))
+#define DMA_BWR_ERQ_ERQ14(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ15[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ15 field. */
+#define DMA_RD_ERQ_ERQ15(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ15_MASK) >> DMA_ERQ_ERQ15_SHIFT)
+#define DMA_BRD_ERQ_ERQ15(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ15_SHIFT))
+
+/*! @brief Set the ERQ15 field to a new value. */
+#define DMA_WR_ERQ_ERQ15(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ15_MASK, DMA_ERQ_ERQ15(value)))
+#define DMA_BWR_ERQ_ERQ15(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_EEI - Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_EEI - Enable Error Interrupt Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The EEI register provides a bit map for the 16 channels to enable the error
+ * interrupt signal for each channel. The state of any given channel's error
+ * interrupt enable is directly affected by writes to this register; it is also
+ * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
+ * interrupt enable for a single channel can easily be modified without the need to
+ * perform a read-modify-write sequence to the EEI register. The DMA error
+ * indicator and the error interrupt enable flag must be asserted before an error
+ * interrupt request for a given channel is asserted to the interrupt controller.
+ */
+/*!
+ * @name Constants and macros for entire DMA_EEI register
+ */
+/*@{*/
+#define DMA_RD_EEI(base)         (DMA_EEI_REG(base))
+#define DMA_WR_EEI(base, value)  (DMA_EEI_REG(base) = (value))
+#define DMA_RMW_EEI(base, mask, value) (DMA_WR_EEI(base, (DMA_RD_EEI(base) & ~(mask)) | (value)))
+#define DMA_SET_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) |  (value)))
+#define DMA_CLR_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) & ~(value)))
+#define DMA_TOG_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_EEI bitfields
+ */
+
+/*!
+ * @name Register DMA_EEI, field EEI0[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI0 field. */
+#define DMA_RD_EEI_EEI0(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI0_MASK) >> DMA_EEI_EEI0_SHIFT)
+#define DMA_BRD_EEI_EEI0(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI0_SHIFT))
+
+/*! @brief Set the EEI0 field to a new value. */
+#define DMA_WR_EEI_EEI0(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI0_MASK, DMA_EEI_EEI0(value)))
+#define DMA_BWR_EEI_EEI0(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI1[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI1 field. */
+#define DMA_RD_EEI_EEI1(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI1_MASK) >> DMA_EEI_EEI1_SHIFT)
+#define DMA_BRD_EEI_EEI1(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI1_SHIFT))
+
+/*! @brief Set the EEI1 field to a new value. */
+#define DMA_WR_EEI_EEI1(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI1_MASK, DMA_EEI_EEI1(value)))
+#define DMA_BWR_EEI_EEI1(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI2[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI2 field. */
+#define DMA_RD_EEI_EEI2(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI2_MASK) >> DMA_EEI_EEI2_SHIFT)
+#define DMA_BRD_EEI_EEI2(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI2_SHIFT))
+
+/*! @brief Set the EEI2 field to a new value. */
+#define DMA_WR_EEI_EEI2(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI2_MASK, DMA_EEI_EEI2(value)))
+#define DMA_BWR_EEI_EEI2(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI3[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI3 field. */
+#define DMA_RD_EEI_EEI3(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI3_MASK) >> DMA_EEI_EEI3_SHIFT)
+#define DMA_BRD_EEI_EEI3(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI3_SHIFT))
+
+/*! @brief Set the EEI3 field to a new value. */
+#define DMA_WR_EEI_EEI3(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI3_MASK, DMA_EEI_EEI3(value)))
+#define DMA_BWR_EEI_EEI3(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI4[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI4 field. */
+#define DMA_RD_EEI_EEI4(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI4_MASK) >> DMA_EEI_EEI4_SHIFT)
+#define DMA_BRD_EEI_EEI4(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI4_SHIFT))
+
+/*! @brief Set the EEI4 field to a new value. */
+#define DMA_WR_EEI_EEI4(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI4_MASK, DMA_EEI_EEI4(value)))
+#define DMA_BWR_EEI_EEI4(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI5[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI5 field. */
+#define DMA_RD_EEI_EEI5(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI5_MASK) >> DMA_EEI_EEI5_SHIFT)
+#define DMA_BRD_EEI_EEI5(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI5_SHIFT))
+
+/*! @brief Set the EEI5 field to a new value. */
+#define DMA_WR_EEI_EEI5(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI5_MASK, DMA_EEI_EEI5(value)))
+#define DMA_BWR_EEI_EEI5(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI6[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI6 field. */
+#define DMA_RD_EEI_EEI6(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI6_MASK) >> DMA_EEI_EEI6_SHIFT)
+#define DMA_BRD_EEI_EEI6(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI6_SHIFT))
+
+/*! @brief Set the EEI6 field to a new value. */
+#define DMA_WR_EEI_EEI6(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI6_MASK, DMA_EEI_EEI6(value)))
+#define DMA_BWR_EEI_EEI6(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI7[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI7 field. */
+#define DMA_RD_EEI_EEI7(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI7_MASK) >> DMA_EEI_EEI7_SHIFT)
+#define DMA_BRD_EEI_EEI7(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI7_SHIFT))
+
+/*! @brief Set the EEI7 field to a new value. */
+#define DMA_WR_EEI_EEI7(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI7_MASK, DMA_EEI_EEI7(value)))
+#define DMA_BWR_EEI_EEI7(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI8[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI8 field. */
+#define DMA_RD_EEI_EEI8(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI8_MASK) >> DMA_EEI_EEI8_SHIFT)
+#define DMA_BRD_EEI_EEI8(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI8_SHIFT))
+
+/*! @brief Set the EEI8 field to a new value. */
+#define DMA_WR_EEI_EEI8(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI8_MASK, DMA_EEI_EEI8(value)))
+#define DMA_BWR_EEI_EEI8(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI9[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI9 field. */
+#define DMA_RD_EEI_EEI9(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI9_MASK) >> DMA_EEI_EEI9_SHIFT)
+#define DMA_BRD_EEI_EEI9(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI9_SHIFT))
+
+/*! @brief Set the EEI9 field to a new value. */
+#define DMA_WR_EEI_EEI9(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI9_MASK, DMA_EEI_EEI9(value)))
+#define DMA_BWR_EEI_EEI9(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI10[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI10 field. */
+#define DMA_RD_EEI_EEI10(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI10_MASK) >> DMA_EEI_EEI10_SHIFT)
+#define DMA_BRD_EEI_EEI10(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI10_SHIFT))
+
+/*! @brief Set the EEI10 field to a new value. */
+#define DMA_WR_EEI_EEI10(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI10_MASK, DMA_EEI_EEI10(value)))
+#define DMA_BWR_EEI_EEI10(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI11[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI11 field. */
+#define DMA_RD_EEI_EEI11(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI11_MASK) >> DMA_EEI_EEI11_SHIFT)
+#define DMA_BRD_EEI_EEI11(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI11_SHIFT))
+
+/*! @brief Set the EEI11 field to a new value. */
+#define DMA_WR_EEI_EEI11(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI11_MASK, DMA_EEI_EEI11(value)))
+#define DMA_BWR_EEI_EEI11(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI12[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI12 field. */
+#define DMA_RD_EEI_EEI12(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI12_MASK) >> DMA_EEI_EEI12_SHIFT)
+#define DMA_BRD_EEI_EEI12(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI12_SHIFT))
+
+/*! @brief Set the EEI12 field to a new value. */
+#define DMA_WR_EEI_EEI12(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI12_MASK, DMA_EEI_EEI12(value)))
+#define DMA_BWR_EEI_EEI12(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI13[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI13 field. */
+#define DMA_RD_EEI_EEI13(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI13_MASK) >> DMA_EEI_EEI13_SHIFT)
+#define DMA_BRD_EEI_EEI13(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI13_SHIFT))
+
+/*! @brief Set the EEI13 field to a new value. */
+#define DMA_WR_EEI_EEI13(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI13_MASK, DMA_EEI_EEI13(value)))
+#define DMA_BWR_EEI_EEI13(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI14[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI14 field. */
+#define DMA_RD_EEI_EEI14(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI14_MASK) >> DMA_EEI_EEI14_SHIFT)
+#define DMA_BRD_EEI_EEI14(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI14_SHIFT))
+
+/*! @brief Set the EEI14 field to a new value. */
+#define DMA_WR_EEI_EEI14(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI14_MASK, DMA_EEI_EEI14(value)))
+#define DMA_BWR_EEI_EEI14(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI15[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI15 field. */
+#define DMA_RD_EEI_EEI15(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI15_MASK) >> DMA_EEI_EEI15_SHIFT)
+#define DMA_BRD_EEI_EEI15(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI15_SHIFT))
+
+/*! @brief Set the EEI15 field to a new value. */
+#define DMA_WR_EEI_EEI15(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI15_MASK, DMA_EEI_EEI15(value)))
+#define DMA_BWR_EEI_EEI15(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CEEI - Clear Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CEEI - Clear Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
+ * the EEI to disable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be cleared. Setting
+ * the CAEE bit provides a global clear function, forcing the EEI contents to be
+ * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
+ * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
+ * Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CEEI register
+ */
+/*@{*/
+#define DMA_RD_CEEI(base)        (DMA_CEEI_REG(base))
+#define DMA_WR_CEEI(base, value) (DMA_CEEI_REG(base) = (value))
+#define DMA_RMW_CEEI(base, mask, value) (DMA_WR_CEEI(base, (DMA_RD_CEEI(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in EEI
+ */
+/*@{*/
+/*! @brief Set the CEEI field to a new value. */
+#define DMA_WR_CEEI_CEEI(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_CEEI_MASK, DMA_CEEI_CEEI(value)))
+#define DMA_BWR_CEEI_CEEI(base, value) (DMA_WR_CEEI_CEEI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CEEI, field CAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the EEI bit specified in the CEEI field
+ * - 0b1 - Clear all bits in EEI
+ */
+/*@{*/
+/*! @brief Set the CAEE field to a new value. */
+#define DMA_WR_CEEI_CAEE(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_CAEE_MASK, DMA_CEEI_CAEE(value)))
+#define DMA_BWR_CEEI_CAEE(base, value) (BITBAND_ACCESS8(&DMA_CEEI_REG(base), DMA_CEEI_CAEE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CEEI_NOP(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_NOP_MASK, DMA_CEEI_NOP(value)))
+#define DMA_BWR_CEEI_NOP(base, value) (BITBAND_ACCESS8(&DMA_CEEI_REG(base), DMA_CEEI_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SEEI - Set Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SEEI - Set Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
+ * EEI to enable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be set. Setting the
+ * SAEE bit provides a global set function, forcing the entire EEI contents to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SEEI register
+ */
+/*@{*/
+#define DMA_RD_SEEI(base)        (DMA_SEEI_REG(base))
+#define DMA_WR_SEEI(base, value) (DMA_SEEI_REG(base) = (value))
+#define DMA_RMW_SEEI(base, mask, value) (DMA_WR_SEEI(base, (DMA_RD_SEEI(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in EEI
+ */
+/*@{*/
+/*! @brief Set the SEEI field to a new value. */
+#define DMA_WR_SEEI_SEEI(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_SEEI_MASK, DMA_SEEI_SEEI(value)))
+#define DMA_BWR_SEEI_SEEI(base, value) (DMA_WR_SEEI_SEEI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SEEI, field SAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the EEI bit specified in the SEEI field.
+ * - 0b1 - Sets all bits in EEI
+ */
+/*@{*/
+/*! @brief Set the SAEE field to a new value. */
+#define DMA_WR_SEEI_SAEE(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_SAEE_MASK, DMA_SEEI_SAEE(value)))
+#define DMA_BWR_SEEI_SAEE(base, value) (BITBAND_ACCESS8(&DMA_SEEI_REG(base), DMA_SEEI_SAEE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SEEI_NOP(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_NOP_MASK, DMA_SEEI_NOP(value)))
+#define DMA_BWR_SEEI_NOP(base, value) (BITBAND_ACCESS8(&DMA_SEEI_REG(base), DMA_SEEI_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CERQ - Clear Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CERQ - Clear Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERQ to disable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be cleared. Setting the
+ * CAER bit provides a global clear function, forcing the entire contents of the
+ * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
+ * command is ignored. This allows you to write multiple-byte registers as a 32-bit
+ * word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CERQ register
+ */
+/*@{*/
+#define DMA_RD_CERQ(base)        (DMA_CERQ_REG(base))
+#define DMA_WR_CERQ(base, value) (DMA_CERQ_REG(base) = (value))
+#define DMA_RMW_CERQ(base, mask, value) (DMA_WR_CERQ(base, (DMA_RD_CERQ(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERQ
+ */
+/*@{*/
+/*! @brief Set the CERQ field to a new value. */
+#define DMA_WR_CERQ_CERQ(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_CERQ_MASK, DMA_CERQ_CERQ(value)))
+#define DMA_BWR_CERQ_CERQ(base, value) (DMA_WR_CERQ_CERQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERQ, field CAER[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the ERQ bit specified in the CERQ field
+ * - 0b1 - Clear all bits in ERQ
+ */
+/*@{*/
+/*! @brief Set the CAER field to a new value. */
+#define DMA_WR_CERQ_CAER(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_CAER_MASK, DMA_CERQ_CAER(value)))
+#define DMA_BWR_CERQ_CAER(base, value) (BITBAND_ACCESS8(&DMA_CERQ_REG(base), DMA_CERQ_CAER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CERQ_NOP(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_NOP_MASK, DMA_CERQ_NOP(value)))
+#define DMA_BWR_CERQ_NOP(base, value) (BITBAND_ACCESS8(&DMA_CERQ_REG(base), DMA_CERQ_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SERQ - Set Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SERQ - Set Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
+ * ERQ to enable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
+ * bit provides a global set function, forcing the entire contents of ERQ to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SERQ register
+ */
+/*@{*/
+#define DMA_RD_SERQ(base)        (DMA_SERQ_REG(base))
+#define DMA_WR_SERQ(base, value) (DMA_SERQ_REG(base) = (value))
+#define DMA_RMW_SERQ(base, mask, value) (DMA_WR_SERQ(base, (DMA_RD_SERQ(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in ERQ
+ */
+/*@{*/
+/*! @brief Set the SERQ field to a new value. */
+#define DMA_WR_SERQ_SERQ(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_SERQ_MASK, DMA_SERQ_SERQ(value)))
+#define DMA_BWR_SERQ_SERQ(base, value) (DMA_WR_SERQ_SERQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SERQ, field SAER[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the ERQ bit specified in the SERQ field
+ * - 0b1 - Set all bits in ERQ
+ */
+/*@{*/
+/*! @brief Set the SAER field to a new value. */
+#define DMA_WR_SERQ_SAER(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_SAER_MASK, DMA_SERQ_SAER(value)))
+#define DMA_BWR_SERQ_SAER(base, value) (BITBAND_ACCESS8(&DMA_SERQ_REG(base), DMA_SERQ_SAER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SERQ_NOP(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_NOP_MASK, DMA_SERQ_NOP(value)))
+#define DMA_BWR_SERQ_NOP(base, value) (BITBAND_ACCESS8(&DMA_SERQ_REG(base), DMA_SERQ_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CDNE - Clear DONE Status Bit Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CDNE - Clear DONE Status Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
+ * the CADN bit provides a global clear function, forcing all DONE bits to be
+ * cleared. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CDNE register
+ */
+/*@{*/
+#define DMA_RD_CDNE(base)        (DMA_CDNE_REG(base))
+#define DMA_WR_CDNE(base, value) (DMA_CDNE_REG(base) = (value))
+#define DMA_RMW_CDNE(base, mask, value) (DMA_WR_CDNE(base, (DMA_RD_CDNE(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CDNE bitfields
+ */
+
+/*!
+ * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in TCDn_CSR[DONE]
+ */
+/*@{*/
+/*! @brief Set the CDNE field to a new value. */
+#define DMA_WR_CDNE_CDNE(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_CDNE_MASK, DMA_CDNE_CDNE(value)))
+#define DMA_BWR_CDNE_CDNE(base, value) (DMA_WR_CDNE_CDNE(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CDNE, field CADN[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
+ * - 0b1 - Clears all bits in TCDn_CSR[DONE]
+ */
+/*@{*/
+/*! @brief Set the CADN field to a new value. */
+#define DMA_WR_CDNE_CADN(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_CADN_MASK, DMA_CDNE_CADN(value)))
+#define DMA_BWR_CDNE_CADN(base, value) (BITBAND_ACCESS8(&DMA_CDNE_REG(base), DMA_CDNE_CADN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CDNE, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CDNE_NOP(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_NOP_MASK, DMA_CDNE_NOP(value)))
+#define DMA_BWR_CDNE_NOP(base, value) (BITBAND_ACCESS8(&DMA_CDNE_REG(base), DMA_CDNE_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SSRT - Set START Bit Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SSRT - Set START Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SSRT provides a simple memory-mapped mechanism to set the START bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * START bit in the corresponding transfer control descriptor to be set. Setting the
+ * SAST bit provides a global set function, forcing all START bits to be set. If
+ * the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SSRT register
+ */
+/*@{*/
+#define DMA_RD_SSRT(base)        (DMA_SSRT_REG(base))
+#define DMA_WR_SSRT(base, value) (DMA_SSRT_REG(base) = (value))
+#define DMA_RMW_SSRT(base, mask, value) (DMA_WR_SSRT(base, (DMA_RD_SSRT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SSRT bitfields
+ */
+
+/*!
+ * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in TCDn_CSR[START]
+ */
+/*@{*/
+/*! @brief Set the SSRT field to a new value. */
+#define DMA_WR_SSRT_SSRT(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_SSRT_MASK, DMA_SSRT_SSRT(value)))
+#define DMA_BWR_SSRT_SSRT(base, value) (DMA_WR_SSRT_SSRT(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SSRT, field SAST[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
+ * - 0b1 - Set all bits in TCDn_CSR[START]
+ */
+/*@{*/
+/*! @brief Set the SAST field to a new value. */
+#define DMA_WR_SSRT_SAST(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_SAST_MASK, DMA_SSRT_SAST(value)))
+#define DMA_BWR_SSRT_SAST(base, value) (BITBAND_ACCESS8(&DMA_SSRT_REG(base), DMA_SSRT_SAST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SSRT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SSRT_NOP(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_NOP_MASK, DMA_SSRT_NOP(value)))
+#define DMA_BWR_SSRT_NOP(base, value) (BITBAND_ACCESS8(&DMA_SSRT_REG(base), DMA_SSRT_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CERR - Clear Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CERR - Clear Error Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERR provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERR to disable the error condition flag for a given channel. The given value
+ * on a register write causes the corresponding bit in the ERR to be cleared.
+ * Setting the CAEI bit provides a global clear function, forcing the ERR contents
+ * to be cleared, clearing all channel error indicators. If the NOP bit is set,
+ * the command is ignored. This allows you to write multiple-byte registers as a
+ * 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CERR register
+ */
+/*@{*/
+#define DMA_RD_CERR(base)        (DMA_CERR_REG(base))
+#define DMA_WR_CERR(base, value) (DMA_CERR_REG(base) = (value))
+#define DMA_RMW_CERR(base, mask, value) (DMA_WR_CERR(base, (DMA_RD_CERR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CERR bitfields
+ */
+
+/*!
+ * @name Register DMA_CERR, field CERR[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERR
+ */
+/*@{*/
+/*! @brief Set the CERR field to a new value. */
+#define DMA_WR_CERR_CERR(base, value) (DMA_RMW_CERR(base, DMA_CERR_CERR_MASK, DMA_CERR_CERR(value)))
+#define DMA_BWR_CERR_CERR(base, value) (DMA_WR_CERR_CERR(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERR, field CAEI[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the ERR bit specified in the CERR field
+ * - 0b1 - Clear all bits in ERR
+ */
+/*@{*/
+/*! @brief Set the CAEI field to a new value. */
+#define DMA_WR_CERR_CAEI(base, value) (DMA_RMW_CERR(base, DMA_CERR_CAEI_MASK, DMA_CERR_CAEI(value)))
+#define DMA_BWR_CERR_CAEI(base, value) (BITBAND_ACCESS8(&DMA_CERR_REG(base), DMA_CERR_CAEI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERR, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CERR_NOP(base, value) (DMA_RMW_CERR(base, DMA_CERR_NOP_MASK, DMA_CERR_NOP(value)))
+#define DMA_BWR_CERR_NOP(base, value) (BITBAND_ACCESS8(&DMA_CERR_REG(base), DMA_CERR_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CINT - Clear Interrupt Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CINT - Clear Interrupt Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
+ * the INT to disable the interrupt request for a given channel. The given value
+ * on a register write causes the corresponding bit in the INT to be cleared.
+ * Setting the CAIR bit provides a global clear function, forcing the entire contents
+ * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
+ * bit is set, the command is ignored. This allows you to write multiple-byte
+ * registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CINT register
+ */
+/*@{*/
+#define DMA_RD_CINT(base)        (DMA_CINT_REG(base))
+#define DMA_WR_CINT(base, value) (DMA_CINT_REG(base) = (value))
+#define DMA_RMW_CINT(base, mask, value) (DMA_WR_CINT(base, (DMA_RD_CINT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CINT bitfields
+ */
+
+/*!
+ * @name Register DMA_CINT, field CINT[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in INT
+ */
+/*@{*/
+/*! @brief Set the CINT field to a new value. */
+#define DMA_WR_CINT_CINT(base, value) (DMA_RMW_CINT(base, DMA_CINT_CINT_MASK, DMA_CINT_CINT(value)))
+#define DMA_BWR_CINT_CINT(base, value) (DMA_WR_CINT_CINT(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CINT, field CAIR[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the INT bit specified in the CINT field
+ * - 0b1 - Clear all bits in INT
+ */
+/*@{*/
+/*! @brief Set the CAIR field to a new value. */
+#define DMA_WR_CINT_CAIR(base, value) (DMA_RMW_CINT(base, DMA_CINT_CAIR_MASK, DMA_CINT_CAIR(value)))
+#define DMA_BWR_CINT_CAIR(base, value) (BITBAND_ACCESS8(&DMA_CINT_REG(base), DMA_CINT_CAIR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CINT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CINT_NOP(base, value) (DMA_RMW_CINT(base, DMA_CINT_NOP_MASK, DMA_CINT_NOP(value)))
+#define DMA_BWR_CINT_NOP(base, value) (BITBAND_ACCESS8(&DMA_CINT_REG(base), DMA_CINT_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_INT - Interrupt Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_INT - Interrupt Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The INT register provides a bit map for the 16 channels signaling the
+ * presence of an interrupt request for each channel. Depending on the appropriate bit
+ * setting in the transfer-control descriptors, the eDMA engine generates an
+ * interrupt on data transfer completion. The outputs of this register are directly
+ * routed to the interrupt controller (INTC). During the interrupt-service routine
+ * associated with any given channel, it is the software's responsibility to
+ * clear the appropriate bit, negating the interrupt request. Typically, a write to
+ * the CINT register in the interrupt service routine is used for this purpose.
+ * The state of any given channel's interrupt request is directly affected by
+ * writes to this register; it is also affected by writes to the CINT register. On
+ * writes to INT, a 1 in any bit position clears the corresponding channel's
+ * interrupt request. A zero in any bit position has no affect on the corresponding
+ * channel's current interrupt status. The CINT register is provided so the interrupt
+ * request for a single channel can easily be cleared without the need to
+ * perform a read-modify-write sequence to the INT register.
+ */
+/*!
+ * @name Constants and macros for entire DMA_INT register
+ */
+/*@{*/
+#define DMA_RD_INT(base)         (DMA_INT_REG(base))
+#define DMA_WR_INT(base, value)  (DMA_INT_REG(base) = (value))
+#define DMA_RMW_INT(base, mask, value) (DMA_WR_INT(base, (DMA_RD_INT(base) & ~(mask)) | (value)))
+#define DMA_SET_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) |  (value)))
+#define DMA_CLR_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) & ~(value)))
+#define DMA_TOG_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_INT bitfields
+ */
+
+/*!
+ * @name Register DMA_INT, field INT0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT0 field. */
+#define DMA_RD_INT_INT0(base) ((DMA_INT_REG(base) & DMA_INT_INT0_MASK) >> DMA_INT_INT0_SHIFT)
+#define DMA_BRD_INT_INT0(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT0_SHIFT))
+
+/*! @brief Set the INT0 field to a new value. */
+#define DMA_WR_INT_INT0(base, value) (DMA_RMW_INT(base, (DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT0(value)))
+#define DMA_BWR_INT_INT0(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT1 field. */
+#define DMA_RD_INT_INT1(base) ((DMA_INT_REG(base) & DMA_INT_INT1_MASK) >> DMA_INT_INT1_SHIFT)
+#define DMA_BRD_INT_INT1(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT1_SHIFT))
+
+/*! @brief Set the INT1 field to a new value. */
+#define DMA_WR_INT_INT1(base, value) (DMA_RMW_INT(base, (DMA_INT_INT1_MASK | DMA_INT_INT0_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT1(value)))
+#define DMA_BWR_INT_INT1(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT2 field. */
+#define DMA_RD_INT_INT2(base) ((DMA_INT_REG(base) & DMA_INT_INT2_MASK) >> DMA_INT_INT2_SHIFT)
+#define DMA_BRD_INT_INT2(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT2_SHIFT))
+
+/*! @brief Set the INT2 field to a new value. */
+#define DMA_WR_INT_INT2(base, value) (DMA_RMW_INT(base, (DMA_INT_INT2_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT2(value)))
+#define DMA_BWR_INT_INT2(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT3 field. */
+#define DMA_RD_INT_INT3(base) ((DMA_INT_REG(base) & DMA_INT_INT3_MASK) >> DMA_INT_INT3_SHIFT)
+#define DMA_BRD_INT_INT3(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT3_SHIFT))
+
+/*! @brief Set the INT3 field to a new value. */
+#define DMA_WR_INT_INT3(base, value) (DMA_RMW_INT(base, (DMA_INT_INT3_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT3(value)))
+#define DMA_BWR_INT_INT3(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT4[4] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT4 field. */
+#define DMA_RD_INT_INT4(base) ((DMA_INT_REG(base) & DMA_INT_INT4_MASK) >> DMA_INT_INT4_SHIFT)
+#define DMA_BRD_INT_INT4(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT4_SHIFT))
+
+/*! @brief Set the INT4 field to a new value. */
+#define DMA_WR_INT_INT4(base, value) (DMA_RMW_INT(base, (DMA_INT_INT4_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT4(value)))
+#define DMA_BWR_INT_INT4(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT5[5] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT5 field. */
+#define DMA_RD_INT_INT5(base) ((DMA_INT_REG(base) & DMA_INT_INT5_MASK) >> DMA_INT_INT5_SHIFT)
+#define DMA_BRD_INT_INT5(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT5_SHIFT))
+
+/*! @brief Set the INT5 field to a new value. */
+#define DMA_WR_INT_INT5(base, value) (DMA_RMW_INT(base, (DMA_INT_INT5_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT5(value)))
+#define DMA_BWR_INT_INT5(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT6[6] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT6 field. */
+#define DMA_RD_INT_INT6(base) ((DMA_INT_REG(base) & DMA_INT_INT6_MASK) >> DMA_INT_INT6_SHIFT)
+#define DMA_BRD_INT_INT6(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT6_SHIFT))
+
+/*! @brief Set the INT6 field to a new value. */
+#define DMA_WR_INT_INT6(base, value) (DMA_RMW_INT(base, (DMA_INT_INT6_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT6(value)))
+#define DMA_BWR_INT_INT6(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT7[7] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT7 field. */
+#define DMA_RD_INT_INT7(base) ((DMA_INT_REG(base) & DMA_INT_INT7_MASK) >> DMA_INT_INT7_SHIFT)
+#define DMA_BRD_INT_INT7(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT7_SHIFT))
+
+/*! @brief Set the INT7 field to a new value. */
+#define DMA_WR_INT_INT7(base, value) (DMA_RMW_INT(base, (DMA_INT_INT7_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT7(value)))
+#define DMA_BWR_INT_INT7(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT8[8] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT8 field. */
+#define DMA_RD_INT_INT8(base) ((DMA_INT_REG(base) & DMA_INT_INT8_MASK) >> DMA_INT_INT8_SHIFT)
+#define DMA_BRD_INT_INT8(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT8_SHIFT))
+
+/*! @brief Set the INT8 field to a new value. */
+#define DMA_WR_INT_INT8(base, value) (DMA_RMW_INT(base, (DMA_INT_INT8_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT8(value)))
+#define DMA_BWR_INT_INT8(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT9[9] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT9 field. */
+#define DMA_RD_INT_INT9(base) ((DMA_INT_REG(base) & DMA_INT_INT9_MASK) >> DMA_INT_INT9_SHIFT)
+#define DMA_BRD_INT_INT9(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT9_SHIFT))
+
+/*! @brief Set the INT9 field to a new value. */
+#define DMA_WR_INT_INT9(base, value) (DMA_RMW_INT(base, (DMA_INT_INT9_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT9(value)))
+#define DMA_BWR_INT_INT9(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT10[10] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT10 field. */
+#define DMA_RD_INT_INT10(base) ((DMA_INT_REG(base) & DMA_INT_INT10_MASK) >> DMA_INT_INT10_SHIFT)
+#define DMA_BRD_INT_INT10(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT10_SHIFT))
+
+/*! @brief Set the INT10 field to a new value. */
+#define DMA_WR_INT_INT10(base, value) (DMA_RMW_INT(base, (DMA_INT_INT10_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT10(value)))
+#define DMA_BWR_INT_INT10(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT11[11] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT11 field. */
+#define DMA_RD_INT_INT11(base) ((DMA_INT_REG(base) & DMA_INT_INT11_MASK) >> DMA_INT_INT11_SHIFT)
+#define DMA_BRD_INT_INT11(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT11_SHIFT))
+
+/*! @brief Set the INT11 field to a new value. */
+#define DMA_WR_INT_INT11(base, value) (DMA_RMW_INT(base, (DMA_INT_INT11_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT11(value)))
+#define DMA_BWR_INT_INT11(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT12[12] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT12 field. */
+#define DMA_RD_INT_INT12(base) ((DMA_INT_REG(base) & DMA_INT_INT12_MASK) >> DMA_INT_INT12_SHIFT)
+#define DMA_BRD_INT_INT12(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT12_SHIFT))
+
+/*! @brief Set the INT12 field to a new value. */
+#define DMA_WR_INT_INT12(base, value) (DMA_RMW_INT(base, (DMA_INT_INT12_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT12(value)))
+#define DMA_BWR_INT_INT12(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT13[13] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT13 field. */
+#define DMA_RD_INT_INT13(base) ((DMA_INT_REG(base) & DMA_INT_INT13_MASK) >> DMA_INT_INT13_SHIFT)
+#define DMA_BRD_INT_INT13(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT13_SHIFT))
+
+/*! @brief Set the INT13 field to a new value. */
+#define DMA_WR_INT_INT13(base, value) (DMA_RMW_INT(base, (DMA_INT_INT13_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT13(value)))
+#define DMA_BWR_INT_INT13(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT14[14] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT14 field. */
+#define DMA_RD_INT_INT14(base) ((DMA_INT_REG(base) & DMA_INT_INT14_MASK) >> DMA_INT_INT14_SHIFT)
+#define DMA_BRD_INT_INT14(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT14_SHIFT))
+
+/*! @brief Set the INT14 field to a new value. */
+#define DMA_WR_INT_INT14(base, value) (DMA_RMW_INT(base, (DMA_INT_INT14_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT15_MASK), DMA_INT_INT14(value)))
+#define DMA_BWR_INT_INT14(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT15[15] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT15 field. */
+#define DMA_RD_INT_INT15(base) ((DMA_INT_REG(base) & DMA_INT_INT15_MASK) >> DMA_INT_INT15_SHIFT)
+#define DMA_BRD_INT_INT15(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT15_SHIFT))
+
+/*! @brief Set the INT15 field to a new value. */
+#define DMA_WR_INT_INT15(base, value) (DMA_RMW_INT(base, (DMA_INT_INT15_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK), DMA_INT_INT15(value)))
+#define DMA_BWR_INT_INT15(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ERR - Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ERR - Error Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERR provides a bit map for the 16 channels, signaling the presence of an
+ * error for each channel. The eDMA engine signals the occurrence of an error
+ * condition by setting the appropriate bit in this register. The outputs of this
+ * register are enabled by the contents of the EEI, and then routed to the
+ * interrupt controller. During the execution of the interrupt-service routine associated
+ * with any DMA errors, it is software's responsibility to clear the appropriate
+ * bit, negating the error-interrupt request. Typically, a write to the CERR in
+ * the interrupt-service routine is used for this purpose. The normal DMA channel
+ * completion indicators (setting the transfer control descriptor DONE flag and
+ * the possible assertion of an interrupt request) are not affected when an error
+ * is detected. The contents of this register can also be polled because a
+ * non-zero value indicates the presence of a channel error regardless of the state of
+ * the EEI. The state of any given channel's error indicators is affected by
+ * writes to this register; it is also affected by writes to the CERR. On writes to
+ * the ERR, a one in any bit position clears the corresponding channel's error
+ * status. A zero in any bit position has no affect on the corresponding channel's
+ * current error status. The CERR is provided so the error indicator for a single
+ * channel can easily be cleared.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ERR register
+ */
+/*@{*/
+#define DMA_RD_ERR(base)         (DMA_ERR_REG(base))
+#define DMA_WR_ERR(base, value)  (DMA_ERR_REG(base) = (value))
+#define DMA_RMW_ERR(base, mask, value) (DMA_WR_ERR(base, (DMA_RD_ERR(base) & ~(mask)) | (value)))
+#define DMA_SET_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) |  (value)))
+#define DMA_CLR_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) & ~(value)))
+#define DMA_TOG_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ERR bitfields
+ */
+
+/*!
+ * @name Register DMA_ERR, field ERR0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR0 field. */
+#define DMA_RD_ERR_ERR0(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR0_MASK) >> DMA_ERR_ERR0_SHIFT)
+#define DMA_BRD_ERR_ERR0(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR0_SHIFT))
+
+/*! @brief Set the ERR0 field to a new value. */
+#define DMA_WR_ERR_ERR0(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR0(value)))
+#define DMA_BWR_ERR_ERR0(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR1 field. */
+#define DMA_RD_ERR_ERR1(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR1_MASK) >> DMA_ERR_ERR1_SHIFT)
+#define DMA_BRD_ERR_ERR1(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR1_SHIFT))
+
+/*! @brief Set the ERR1 field to a new value. */
+#define DMA_WR_ERR_ERR1(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR1_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR1(value)))
+#define DMA_BWR_ERR_ERR1(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR2 field. */
+#define DMA_RD_ERR_ERR2(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR2_MASK) >> DMA_ERR_ERR2_SHIFT)
+#define DMA_BRD_ERR_ERR2(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR2_SHIFT))
+
+/*! @brief Set the ERR2 field to a new value. */
+#define DMA_WR_ERR_ERR2(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR2_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR2(value)))
+#define DMA_BWR_ERR_ERR2(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR3 field. */
+#define DMA_RD_ERR_ERR3(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR3_MASK) >> DMA_ERR_ERR3_SHIFT)
+#define DMA_BRD_ERR_ERR3(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR3_SHIFT))
+
+/*! @brief Set the ERR3 field to a new value. */
+#define DMA_WR_ERR_ERR3(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR3_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR3(value)))
+#define DMA_BWR_ERR_ERR3(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR4[4] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR4 field. */
+#define DMA_RD_ERR_ERR4(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR4_MASK) >> DMA_ERR_ERR4_SHIFT)
+#define DMA_BRD_ERR_ERR4(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR4_SHIFT))
+
+/*! @brief Set the ERR4 field to a new value. */
+#define DMA_WR_ERR_ERR4(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR4_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR4(value)))
+#define DMA_BWR_ERR_ERR4(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR5[5] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR5 field. */
+#define DMA_RD_ERR_ERR5(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR5_MASK) >> DMA_ERR_ERR5_SHIFT)
+#define DMA_BRD_ERR_ERR5(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR5_SHIFT))
+
+/*! @brief Set the ERR5 field to a new value. */
+#define DMA_WR_ERR_ERR5(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR5_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR5(value)))
+#define DMA_BWR_ERR_ERR5(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR6[6] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR6 field. */
+#define DMA_RD_ERR_ERR6(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR6_MASK) >> DMA_ERR_ERR6_SHIFT)
+#define DMA_BRD_ERR_ERR6(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR6_SHIFT))
+
+/*! @brief Set the ERR6 field to a new value. */
+#define DMA_WR_ERR_ERR6(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR6_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR6(value)))
+#define DMA_BWR_ERR_ERR6(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR7[7] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR7 field. */
+#define DMA_RD_ERR_ERR7(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR7_MASK) >> DMA_ERR_ERR7_SHIFT)
+#define DMA_BRD_ERR_ERR7(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR7_SHIFT))
+
+/*! @brief Set the ERR7 field to a new value. */
+#define DMA_WR_ERR_ERR7(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR7_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR7(value)))
+#define DMA_BWR_ERR_ERR7(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR8[8] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR8 field. */
+#define DMA_RD_ERR_ERR8(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR8_MASK) >> DMA_ERR_ERR8_SHIFT)
+#define DMA_BRD_ERR_ERR8(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR8_SHIFT))
+
+/*! @brief Set the ERR8 field to a new value. */
+#define DMA_WR_ERR_ERR8(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR8_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR8(value)))
+#define DMA_BWR_ERR_ERR8(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR9[9] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR9 field. */
+#define DMA_RD_ERR_ERR9(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR9_MASK) >> DMA_ERR_ERR9_SHIFT)
+#define DMA_BRD_ERR_ERR9(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR9_SHIFT))
+
+/*! @brief Set the ERR9 field to a new value. */
+#define DMA_WR_ERR_ERR9(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR9_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR9(value)))
+#define DMA_BWR_ERR_ERR9(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR10[10] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR10 field. */
+#define DMA_RD_ERR_ERR10(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR10_MASK) >> DMA_ERR_ERR10_SHIFT)
+#define DMA_BRD_ERR_ERR10(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR10_SHIFT))
+
+/*! @brief Set the ERR10 field to a new value. */
+#define DMA_WR_ERR_ERR10(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR10_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR10(value)))
+#define DMA_BWR_ERR_ERR10(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR11[11] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR11 field. */
+#define DMA_RD_ERR_ERR11(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR11_MASK) >> DMA_ERR_ERR11_SHIFT)
+#define DMA_BRD_ERR_ERR11(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR11_SHIFT))
+
+/*! @brief Set the ERR11 field to a new value. */
+#define DMA_WR_ERR_ERR11(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR11_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR11(value)))
+#define DMA_BWR_ERR_ERR11(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR12[12] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR12 field. */
+#define DMA_RD_ERR_ERR12(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR12_MASK) >> DMA_ERR_ERR12_SHIFT)
+#define DMA_BRD_ERR_ERR12(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR12_SHIFT))
+
+/*! @brief Set the ERR12 field to a new value. */
+#define DMA_WR_ERR_ERR12(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR12_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR12(value)))
+#define DMA_BWR_ERR_ERR12(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR13[13] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR13 field. */
+#define DMA_RD_ERR_ERR13(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR13_MASK) >> DMA_ERR_ERR13_SHIFT)
+#define DMA_BRD_ERR_ERR13(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR13_SHIFT))
+
+/*! @brief Set the ERR13 field to a new value. */
+#define DMA_WR_ERR_ERR13(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR13_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR13(value)))
+#define DMA_BWR_ERR_ERR13(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR14[14] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR14 field. */
+#define DMA_RD_ERR_ERR14(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR14_MASK) >> DMA_ERR_ERR14_SHIFT)
+#define DMA_BRD_ERR_ERR14(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR14_SHIFT))
+
+/*! @brief Set the ERR14 field to a new value. */
+#define DMA_WR_ERR_ERR14(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR14_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR14(value)))
+#define DMA_BWR_ERR_ERR14(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR15[15] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR15 field. */
+#define DMA_RD_ERR_ERR15(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR15_MASK) >> DMA_ERR_ERR15_SHIFT)
+#define DMA_BRD_ERR_ERR15(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR15_SHIFT))
+
+/*! @brief Set the ERR15 field to a new value. */
+#define DMA_WR_ERR_ERR15(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR15_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK), DMA_ERR_ERR15(value)))
+#define DMA_BWR_ERR_ERR15(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_HRS - Hardware Request Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_HRS - Hardware Request Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The HRS register provides a bit map for the DMA channels, signaling the
+ * presence of a hardware request for each channel. The hardware request status bits
+ * reflect the current state of the register and qualified (via the ERQ fields)
+ * DMA request signals as seen by the DMA's arbitration logic. This view into the
+ * hardware request signals may be used for debug purposes. These bits reflect the
+ * state of the request as seen by the arbitration logic. Therefore, this status
+ * is affected by the ERQ bits.
+ */
+/*!
+ * @name Constants and macros for entire DMA_HRS register
+ */
+/*@{*/
+#define DMA_RD_HRS(base)         (DMA_HRS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_HRS bitfields
+ */
+
+/*!
+ * @name Register DMA_HRS, field HRS0[0] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 0 is not present
+ * - 0b1 - A hardware service request for channel 0 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS0 field. */
+#define DMA_RD_HRS_HRS0(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS0_MASK) >> DMA_HRS_HRS0_SHIFT)
+#define DMA_BRD_HRS_HRS0(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS1[1] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 1 is not present
+ * - 0b1 - A hardware service request for channel 1 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS1 field. */
+#define DMA_RD_HRS_HRS1(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS1_MASK) >> DMA_HRS_HRS1_SHIFT)
+#define DMA_BRD_HRS_HRS1(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS2[2] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 2 is not present
+ * - 0b1 - A hardware service request for channel 2 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS2 field. */
+#define DMA_RD_HRS_HRS2(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS2_MASK) >> DMA_HRS_HRS2_SHIFT)
+#define DMA_BRD_HRS_HRS2(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS2_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS3[3] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 3 is not present
+ * - 0b1 - A hardware service request for channel 3 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS3 field. */
+#define DMA_RD_HRS_HRS3(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS3_MASK) >> DMA_HRS_HRS3_SHIFT)
+#define DMA_BRD_HRS_HRS3(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS3_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS4[4] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 4 is not present
+ * - 0b1 - A hardware service request for channel 4 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS4 field. */
+#define DMA_RD_HRS_HRS4(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS4_MASK) >> DMA_HRS_HRS4_SHIFT)
+#define DMA_BRD_HRS_HRS4(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS4_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS5[5] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 5 is not present
+ * - 0b1 - A hardware service request for channel 5 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS5 field. */
+#define DMA_RD_HRS_HRS5(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS5_MASK) >> DMA_HRS_HRS5_SHIFT)
+#define DMA_BRD_HRS_HRS5(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS5_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS6[6] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 6 is not present
+ * - 0b1 - A hardware service request for channel 6 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS6 field. */
+#define DMA_RD_HRS_HRS6(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS6_MASK) >> DMA_HRS_HRS6_SHIFT)
+#define DMA_BRD_HRS_HRS6(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS6_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS7[7] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 7 is not present
+ * - 0b1 - A hardware service request for channel 7 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS7 field. */
+#define DMA_RD_HRS_HRS7(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS7_MASK) >> DMA_HRS_HRS7_SHIFT)
+#define DMA_BRD_HRS_HRS7(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS7_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS8[8] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 8 is not present
+ * - 0b1 - A hardware service request for channel 8 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS8 field. */
+#define DMA_RD_HRS_HRS8(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS8_MASK) >> DMA_HRS_HRS8_SHIFT)
+#define DMA_BRD_HRS_HRS8(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS8_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS9[9] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 9 is not present
+ * - 0b1 - A hardware service request for channel 9 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS9 field. */
+#define DMA_RD_HRS_HRS9(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS9_MASK) >> DMA_HRS_HRS9_SHIFT)
+#define DMA_BRD_HRS_HRS9(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS9_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS10[10] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 10 is not present
+ * - 0b1 - A hardware service request for channel 10 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS10 field. */
+#define DMA_RD_HRS_HRS10(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS10_MASK) >> DMA_HRS_HRS10_SHIFT)
+#define DMA_BRD_HRS_HRS10(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS10_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS11[11] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 11 is not present
+ * - 0b1 - A hardware service request for channel 11 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS11 field. */
+#define DMA_RD_HRS_HRS11(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS11_MASK) >> DMA_HRS_HRS11_SHIFT)
+#define DMA_BRD_HRS_HRS11(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS11_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS12[12] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 12 is not present
+ * - 0b1 - A hardware service request for channel 12 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS12 field. */
+#define DMA_RD_HRS_HRS12(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS12_MASK) >> DMA_HRS_HRS12_SHIFT)
+#define DMA_BRD_HRS_HRS12(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS12_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS13[13] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 13 is not present
+ * - 0b1 - A hardware service request for channel 13 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS13 field. */
+#define DMA_RD_HRS_HRS13(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS13_MASK) >> DMA_HRS_HRS13_SHIFT)
+#define DMA_BRD_HRS_HRS13(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS13_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS14[14] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 14 is not present
+ * - 0b1 - A hardware service request for channel 14 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS14 field. */
+#define DMA_RD_HRS_HRS14(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS14_MASK) >> DMA_HRS_HRS14_SHIFT)
+#define DMA_BRD_HRS_HRS14(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS14_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS15[15] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 15 is not present
+ * - 0b1 - A hardware service request for channel 15 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS15 field. */
+#define DMA_RD_HRS_HRS15(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS15_MASK) >> DMA_HRS_HRS15_SHIFT)
+#define DMA_BRD_HRS_HRS15(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS15_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI3 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI3 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI3 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI3(base)     (DMA_DCHPRI3_REG(base))
+#define DMA_WR_DCHPRI3(base, value) (DMA_DCHPRI3_REG(base) = (value))
+#define DMA_RMW_DCHPRI3(base, mask, value) (DMA_WR_DCHPRI3(base, (DMA_RD_DCHPRI3(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) |  (value)))
+#define DMA_CLR_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) & ~(value)))
+#define DMA_TOG_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI3 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI3, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_CHPRI field. */
+#define DMA_RD_DCHPRI3_CHPRI(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_CHPRI_MASK) >> DMA_DCHPRI3_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI3_CHPRI(base) (DMA_RD_DCHPRI3_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI3_CHPRI(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_CHPRI_MASK, DMA_DCHPRI3_CHPRI(value)))
+#define DMA_BWR_DCHPRI3_CHPRI(base, value) (DMA_WR_DCHPRI3_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI3, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_DPA field. */
+#define DMA_RD_DCHPRI3_DPA(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_DPA_MASK) >> DMA_DCHPRI3_DPA_SHIFT)
+#define DMA_BRD_DCHPRI3_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI3_DPA(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_DPA_MASK, DMA_DCHPRI3_DPA(value)))
+#define DMA_BWR_DCHPRI3_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI3, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_ECP field. */
+#define DMA_RD_DCHPRI3_ECP(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_ECP_MASK) >> DMA_DCHPRI3_ECP_SHIFT)
+#define DMA_BRD_DCHPRI3_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI3_ECP(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_ECP_MASK, DMA_DCHPRI3_ECP(value)))
+#define DMA_BWR_DCHPRI3_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI2 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI2 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI2 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI2(base)     (DMA_DCHPRI2_REG(base))
+#define DMA_WR_DCHPRI2(base, value) (DMA_DCHPRI2_REG(base) = (value))
+#define DMA_RMW_DCHPRI2(base, mask, value) (DMA_WR_DCHPRI2(base, (DMA_RD_DCHPRI2(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) |  (value)))
+#define DMA_CLR_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) & ~(value)))
+#define DMA_TOG_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI2 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI2, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_CHPRI field. */
+#define DMA_RD_DCHPRI2_CHPRI(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_CHPRI_MASK) >> DMA_DCHPRI2_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI2_CHPRI(base) (DMA_RD_DCHPRI2_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI2_CHPRI(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_CHPRI_MASK, DMA_DCHPRI2_CHPRI(value)))
+#define DMA_BWR_DCHPRI2_CHPRI(base, value) (DMA_WR_DCHPRI2_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI2, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_DPA field. */
+#define DMA_RD_DCHPRI2_DPA(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_DPA_MASK) >> DMA_DCHPRI2_DPA_SHIFT)
+#define DMA_BRD_DCHPRI2_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI2_DPA(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_DPA_MASK, DMA_DCHPRI2_DPA(value)))
+#define DMA_BWR_DCHPRI2_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI2, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_ECP field. */
+#define DMA_RD_DCHPRI2_ECP(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_ECP_MASK) >> DMA_DCHPRI2_ECP_SHIFT)
+#define DMA_BRD_DCHPRI2_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI2_ECP(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_ECP_MASK, DMA_DCHPRI2_ECP(value)))
+#define DMA_BWR_DCHPRI2_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI1 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI1 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI1 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI1(base)     (DMA_DCHPRI1_REG(base))
+#define DMA_WR_DCHPRI1(base, value) (DMA_DCHPRI1_REG(base) = (value))
+#define DMA_RMW_DCHPRI1(base, mask, value) (DMA_WR_DCHPRI1(base, (DMA_RD_DCHPRI1(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) |  (value)))
+#define DMA_CLR_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) & ~(value)))
+#define DMA_TOG_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI1 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI1, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_CHPRI field. */
+#define DMA_RD_DCHPRI1_CHPRI(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_CHPRI_MASK) >> DMA_DCHPRI1_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI1_CHPRI(base) (DMA_RD_DCHPRI1_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI1_CHPRI(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_CHPRI_MASK, DMA_DCHPRI1_CHPRI(value)))
+#define DMA_BWR_DCHPRI1_CHPRI(base, value) (DMA_WR_DCHPRI1_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI1, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_DPA field. */
+#define DMA_RD_DCHPRI1_DPA(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_DPA_MASK) >> DMA_DCHPRI1_DPA_SHIFT)
+#define DMA_BRD_DCHPRI1_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI1_DPA(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_DPA_MASK, DMA_DCHPRI1_DPA(value)))
+#define DMA_BWR_DCHPRI1_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI1, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_ECP field. */
+#define DMA_RD_DCHPRI1_ECP(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_ECP_MASK) >> DMA_DCHPRI1_ECP_SHIFT)
+#define DMA_BRD_DCHPRI1_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI1_ECP(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_ECP_MASK, DMA_DCHPRI1_ECP(value)))
+#define DMA_BWR_DCHPRI1_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI0 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI0 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI0 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI0(base)     (DMA_DCHPRI0_REG(base))
+#define DMA_WR_DCHPRI0(base, value) (DMA_DCHPRI0_REG(base) = (value))
+#define DMA_RMW_DCHPRI0(base, mask, value) (DMA_WR_DCHPRI0(base, (DMA_RD_DCHPRI0(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) |  (value)))
+#define DMA_CLR_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) & ~(value)))
+#define DMA_TOG_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI0 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI0, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_CHPRI field. */
+#define DMA_RD_DCHPRI0_CHPRI(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_CHPRI_MASK) >> DMA_DCHPRI0_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI0_CHPRI(base) (DMA_RD_DCHPRI0_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI0_CHPRI(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_CHPRI_MASK, DMA_DCHPRI0_CHPRI(value)))
+#define DMA_BWR_DCHPRI0_CHPRI(base, value) (DMA_WR_DCHPRI0_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI0, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_DPA field. */
+#define DMA_RD_DCHPRI0_DPA(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_DPA_MASK) >> DMA_DCHPRI0_DPA_SHIFT)
+#define DMA_BRD_DCHPRI0_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI0_DPA(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_DPA_MASK, DMA_DCHPRI0_DPA(value)))
+#define DMA_BWR_DCHPRI0_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI0, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_ECP field. */
+#define DMA_RD_DCHPRI0_ECP(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_ECP_MASK) >> DMA_DCHPRI0_ECP_SHIFT)
+#define DMA_BRD_DCHPRI0_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI0_ECP(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_ECP_MASK, DMA_DCHPRI0_ECP(value)))
+#define DMA_BWR_DCHPRI0_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI7 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI7 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI7 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI7(base)     (DMA_DCHPRI7_REG(base))
+#define DMA_WR_DCHPRI7(base, value) (DMA_DCHPRI7_REG(base) = (value))
+#define DMA_RMW_DCHPRI7(base, mask, value) (DMA_WR_DCHPRI7(base, (DMA_RD_DCHPRI7(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) |  (value)))
+#define DMA_CLR_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) & ~(value)))
+#define DMA_TOG_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI7 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI7, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_CHPRI field. */
+#define DMA_RD_DCHPRI7_CHPRI(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_CHPRI_MASK) >> DMA_DCHPRI7_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI7_CHPRI(base) (DMA_RD_DCHPRI7_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI7_CHPRI(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_CHPRI_MASK, DMA_DCHPRI7_CHPRI(value)))
+#define DMA_BWR_DCHPRI7_CHPRI(base, value) (DMA_WR_DCHPRI7_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI7, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_DPA field. */
+#define DMA_RD_DCHPRI7_DPA(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_DPA_MASK) >> DMA_DCHPRI7_DPA_SHIFT)
+#define DMA_BRD_DCHPRI7_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI7_DPA(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_DPA_MASK, DMA_DCHPRI7_DPA(value)))
+#define DMA_BWR_DCHPRI7_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI7, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_ECP field. */
+#define DMA_RD_DCHPRI7_ECP(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_ECP_MASK) >> DMA_DCHPRI7_ECP_SHIFT)
+#define DMA_BRD_DCHPRI7_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI7_ECP(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_ECP_MASK, DMA_DCHPRI7_ECP(value)))
+#define DMA_BWR_DCHPRI7_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI6 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI6 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI6 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI6(base)     (DMA_DCHPRI6_REG(base))
+#define DMA_WR_DCHPRI6(base, value) (DMA_DCHPRI6_REG(base) = (value))
+#define DMA_RMW_DCHPRI6(base, mask, value) (DMA_WR_DCHPRI6(base, (DMA_RD_DCHPRI6(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) |  (value)))
+#define DMA_CLR_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) & ~(value)))
+#define DMA_TOG_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI6 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI6, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_CHPRI field. */
+#define DMA_RD_DCHPRI6_CHPRI(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_CHPRI_MASK) >> DMA_DCHPRI6_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI6_CHPRI(base) (DMA_RD_DCHPRI6_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI6_CHPRI(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_CHPRI_MASK, DMA_DCHPRI6_CHPRI(value)))
+#define DMA_BWR_DCHPRI6_CHPRI(base, value) (DMA_WR_DCHPRI6_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI6, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_DPA field. */
+#define DMA_RD_DCHPRI6_DPA(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_DPA_MASK) >> DMA_DCHPRI6_DPA_SHIFT)
+#define DMA_BRD_DCHPRI6_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI6_DPA(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_DPA_MASK, DMA_DCHPRI6_DPA(value)))
+#define DMA_BWR_DCHPRI6_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI6, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_ECP field. */
+#define DMA_RD_DCHPRI6_ECP(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_ECP_MASK) >> DMA_DCHPRI6_ECP_SHIFT)
+#define DMA_BRD_DCHPRI6_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI6_ECP(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_ECP_MASK, DMA_DCHPRI6_ECP(value)))
+#define DMA_BWR_DCHPRI6_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI5 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI5 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI5 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI5(base)     (DMA_DCHPRI5_REG(base))
+#define DMA_WR_DCHPRI5(base, value) (DMA_DCHPRI5_REG(base) = (value))
+#define DMA_RMW_DCHPRI5(base, mask, value) (DMA_WR_DCHPRI5(base, (DMA_RD_DCHPRI5(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) |  (value)))
+#define DMA_CLR_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) & ~(value)))
+#define DMA_TOG_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI5 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI5, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_CHPRI field. */
+#define DMA_RD_DCHPRI5_CHPRI(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_CHPRI_MASK) >> DMA_DCHPRI5_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI5_CHPRI(base) (DMA_RD_DCHPRI5_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI5_CHPRI(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_CHPRI_MASK, DMA_DCHPRI5_CHPRI(value)))
+#define DMA_BWR_DCHPRI5_CHPRI(base, value) (DMA_WR_DCHPRI5_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI5, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_DPA field. */
+#define DMA_RD_DCHPRI5_DPA(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_DPA_MASK) >> DMA_DCHPRI5_DPA_SHIFT)
+#define DMA_BRD_DCHPRI5_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI5_DPA(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_DPA_MASK, DMA_DCHPRI5_DPA(value)))
+#define DMA_BWR_DCHPRI5_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI5, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_ECP field. */
+#define DMA_RD_DCHPRI5_ECP(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_ECP_MASK) >> DMA_DCHPRI5_ECP_SHIFT)
+#define DMA_BRD_DCHPRI5_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI5_ECP(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_ECP_MASK, DMA_DCHPRI5_ECP(value)))
+#define DMA_BWR_DCHPRI5_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI4 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI4 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI4 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI4(base)     (DMA_DCHPRI4_REG(base))
+#define DMA_WR_DCHPRI4(base, value) (DMA_DCHPRI4_REG(base) = (value))
+#define DMA_RMW_DCHPRI4(base, mask, value) (DMA_WR_DCHPRI4(base, (DMA_RD_DCHPRI4(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) |  (value)))
+#define DMA_CLR_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) & ~(value)))
+#define DMA_TOG_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI4 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI4, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_CHPRI field. */
+#define DMA_RD_DCHPRI4_CHPRI(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_CHPRI_MASK) >> DMA_DCHPRI4_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI4_CHPRI(base) (DMA_RD_DCHPRI4_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI4_CHPRI(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_CHPRI_MASK, DMA_DCHPRI4_CHPRI(value)))
+#define DMA_BWR_DCHPRI4_CHPRI(base, value) (DMA_WR_DCHPRI4_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI4, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_DPA field. */
+#define DMA_RD_DCHPRI4_DPA(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_DPA_MASK) >> DMA_DCHPRI4_DPA_SHIFT)
+#define DMA_BRD_DCHPRI4_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI4_DPA(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_DPA_MASK, DMA_DCHPRI4_DPA(value)))
+#define DMA_BWR_DCHPRI4_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI4, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_ECP field. */
+#define DMA_RD_DCHPRI4_ECP(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_ECP_MASK) >> DMA_DCHPRI4_ECP_SHIFT)
+#define DMA_BRD_DCHPRI4_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI4_ECP(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_ECP_MASK, DMA_DCHPRI4_ECP(value)))
+#define DMA_BWR_DCHPRI4_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI11 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI11 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI11 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI11(base)    (DMA_DCHPRI11_REG(base))
+#define DMA_WR_DCHPRI11(base, value) (DMA_DCHPRI11_REG(base) = (value))
+#define DMA_RMW_DCHPRI11(base, mask, value) (DMA_WR_DCHPRI11(base, (DMA_RD_DCHPRI11(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) |  (value)))
+#define DMA_CLR_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) & ~(value)))
+#define DMA_TOG_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI11 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI11, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_CHPRI field. */
+#define DMA_RD_DCHPRI11_CHPRI(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_CHPRI_MASK) >> DMA_DCHPRI11_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI11_CHPRI(base) (DMA_RD_DCHPRI11_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI11_CHPRI(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_CHPRI_MASK, DMA_DCHPRI11_CHPRI(value)))
+#define DMA_BWR_DCHPRI11_CHPRI(base, value) (DMA_WR_DCHPRI11_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI11, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_DPA field. */
+#define DMA_RD_DCHPRI11_DPA(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_DPA_MASK) >> DMA_DCHPRI11_DPA_SHIFT)
+#define DMA_BRD_DCHPRI11_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI11_DPA(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_DPA_MASK, DMA_DCHPRI11_DPA(value)))
+#define DMA_BWR_DCHPRI11_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI11, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_ECP field. */
+#define DMA_RD_DCHPRI11_ECP(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_ECP_MASK) >> DMA_DCHPRI11_ECP_SHIFT)
+#define DMA_BRD_DCHPRI11_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI11_ECP(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_ECP_MASK, DMA_DCHPRI11_ECP(value)))
+#define DMA_BWR_DCHPRI11_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI10 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI10 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI10 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI10(base)    (DMA_DCHPRI10_REG(base))
+#define DMA_WR_DCHPRI10(base, value) (DMA_DCHPRI10_REG(base) = (value))
+#define DMA_RMW_DCHPRI10(base, mask, value) (DMA_WR_DCHPRI10(base, (DMA_RD_DCHPRI10(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) |  (value)))
+#define DMA_CLR_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) & ~(value)))
+#define DMA_TOG_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI10 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI10, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_CHPRI field. */
+#define DMA_RD_DCHPRI10_CHPRI(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_CHPRI_MASK) >> DMA_DCHPRI10_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI10_CHPRI(base) (DMA_RD_DCHPRI10_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI10_CHPRI(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_CHPRI_MASK, DMA_DCHPRI10_CHPRI(value)))
+#define DMA_BWR_DCHPRI10_CHPRI(base, value) (DMA_WR_DCHPRI10_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI10, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_DPA field. */
+#define DMA_RD_DCHPRI10_DPA(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_DPA_MASK) >> DMA_DCHPRI10_DPA_SHIFT)
+#define DMA_BRD_DCHPRI10_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI10_DPA(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_DPA_MASK, DMA_DCHPRI10_DPA(value)))
+#define DMA_BWR_DCHPRI10_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI10, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_ECP field. */
+#define DMA_RD_DCHPRI10_ECP(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_ECP_MASK) >> DMA_DCHPRI10_ECP_SHIFT)
+#define DMA_BRD_DCHPRI10_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI10_ECP(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_ECP_MASK, DMA_DCHPRI10_ECP(value)))
+#define DMA_BWR_DCHPRI10_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI9 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI9 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI9 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI9(base)     (DMA_DCHPRI9_REG(base))
+#define DMA_WR_DCHPRI9(base, value) (DMA_DCHPRI9_REG(base) = (value))
+#define DMA_RMW_DCHPRI9(base, mask, value) (DMA_WR_DCHPRI9(base, (DMA_RD_DCHPRI9(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) |  (value)))
+#define DMA_CLR_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) & ~(value)))
+#define DMA_TOG_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI9 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI9, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_CHPRI field. */
+#define DMA_RD_DCHPRI9_CHPRI(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_CHPRI_MASK) >> DMA_DCHPRI9_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI9_CHPRI(base) (DMA_RD_DCHPRI9_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI9_CHPRI(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_CHPRI_MASK, DMA_DCHPRI9_CHPRI(value)))
+#define DMA_BWR_DCHPRI9_CHPRI(base, value) (DMA_WR_DCHPRI9_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI9, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_DPA field. */
+#define DMA_RD_DCHPRI9_DPA(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_DPA_MASK) >> DMA_DCHPRI9_DPA_SHIFT)
+#define DMA_BRD_DCHPRI9_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI9_DPA(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_DPA_MASK, DMA_DCHPRI9_DPA(value)))
+#define DMA_BWR_DCHPRI9_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI9, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_ECP field. */
+#define DMA_RD_DCHPRI9_ECP(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_ECP_MASK) >> DMA_DCHPRI9_ECP_SHIFT)
+#define DMA_BRD_DCHPRI9_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI9_ECP(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_ECP_MASK, DMA_DCHPRI9_ECP(value)))
+#define DMA_BWR_DCHPRI9_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI8 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI8 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI8 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI8(base)     (DMA_DCHPRI8_REG(base))
+#define DMA_WR_DCHPRI8(base, value) (DMA_DCHPRI8_REG(base) = (value))
+#define DMA_RMW_DCHPRI8(base, mask, value) (DMA_WR_DCHPRI8(base, (DMA_RD_DCHPRI8(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) |  (value)))
+#define DMA_CLR_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) & ~(value)))
+#define DMA_TOG_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI8 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI8, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_CHPRI field. */
+#define DMA_RD_DCHPRI8_CHPRI(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_CHPRI_MASK) >> DMA_DCHPRI8_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI8_CHPRI(base) (DMA_RD_DCHPRI8_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI8_CHPRI(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_CHPRI_MASK, DMA_DCHPRI8_CHPRI(value)))
+#define DMA_BWR_DCHPRI8_CHPRI(base, value) (DMA_WR_DCHPRI8_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI8, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_DPA field. */
+#define DMA_RD_DCHPRI8_DPA(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_DPA_MASK) >> DMA_DCHPRI8_DPA_SHIFT)
+#define DMA_BRD_DCHPRI8_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI8_DPA(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_DPA_MASK, DMA_DCHPRI8_DPA(value)))
+#define DMA_BWR_DCHPRI8_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI8, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_ECP field. */
+#define DMA_RD_DCHPRI8_ECP(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_ECP_MASK) >> DMA_DCHPRI8_ECP_SHIFT)
+#define DMA_BRD_DCHPRI8_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI8_ECP(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_ECP_MASK, DMA_DCHPRI8_ECP(value)))
+#define DMA_BWR_DCHPRI8_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI15 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI15 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI15 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI15(base)    (DMA_DCHPRI15_REG(base))
+#define DMA_WR_DCHPRI15(base, value) (DMA_DCHPRI15_REG(base) = (value))
+#define DMA_RMW_DCHPRI15(base, mask, value) (DMA_WR_DCHPRI15(base, (DMA_RD_DCHPRI15(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) |  (value)))
+#define DMA_CLR_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) & ~(value)))
+#define DMA_TOG_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI15 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI15, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_CHPRI field. */
+#define DMA_RD_DCHPRI15_CHPRI(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_CHPRI_MASK) >> DMA_DCHPRI15_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI15_CHPRI(base) (DMA_RD_DCHPRI15_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI15_CHPRI(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_CHPRI_MASK, DMA_DCHPRI15_CHPRI(value)))
+#define DMA_BWR_DCHPRI15_CHPRI(base, value) (DMA_WR_DCHPRI15_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI15, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_DPA field. */
+#define DMA_RD_DCHPRI15_DPA(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_DPA_MASK) >> DMA_DCHPRI15_DPA_SHIFT)
+#define DMA_BRD_DCHPRI15_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI15_DPA(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_DPA_MASK, DMA_DCHPRI15_DPA(value)))
+#define DMA_BWR_DCHPRI15_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI15, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_ECP field. */
+#define DMA_RD_DCHPRI15_ECP(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_ECP_MASK) >> DMA_DCHPRI15_ECP_SHIFT)
+#define DMA_BRD_DCHPRI15_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI15_ECP(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_ECP_MASK, DMA_DCHPRI15_ECP(value)))
+#define DMA_BWR_DCHPRI15_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI14 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI14 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI14 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI14(base)    (DMA_DCHPRI14_REG(base))
+#define DMA_WR_DCHPRI14(base, value) (DMA_DCHPRI14_REG(base) = (value))
+#define DMA_RMW_DCHPRI14(base, mask, value) (DMA_WR_DCHPRI14(base, (DMA_RD_DCHPRI14(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) |  (value)))
+#define DMA_CLR_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) & ~(value)))
+#define DMA_TOG_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI14 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI14, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_CHPRI field. */
+#define DMA_RD_DCHPRI14_CHPRI(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_CHPRI_MASK) >> DMA_DCHPRI14_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI14_CHPRI(base) (DMA_RD_DCHPRI14_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI14_CHPRI(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_CHPRI_MASK, DMA_DCHPRI14_CHPRI(value)))
+#define DMA_BWR_DCHPRI14_CHPRI(base, value) (DMA_WR_DCHPRI14_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI14, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_DPA field. */
+#define DMA_RD_DCHPRI14_DPA(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_DPA_MASK) >> DMA_DCHPRI14_DPA_SHIFT)
+#define DMA_BRD_DCHPRI14_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI14_DPA(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_DPA_MASK, DMA_DCHPRI14_DPA(value)))
+#define DMA_BWR_DCHPRI14_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI14, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_ECP field. */
+#define DMA_RD_DCHPRI14_ECP(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_ECP_MASK) >> DMA_DCHPRI14_ECP_SHIFT)
+#define DMA_BRD_DCHPRI14_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI14_ECP(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_ECP_MASK, DMA_DCHPRI14_ECP(value)))
+#define DMA_BWR_DCHPRI14_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI13 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI13 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI13 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI13(base)    (DMA_DCHPRI13_REG(base))
+#define DMA_WR_DCHPRI13(base, value) (DMA_DCHPRI13_REG(base) = (value))
+#define DMA_RMW_DCHPRI13(base, mask, value) (DMA_WR_DCHPRI13(base, (DMA_RD_DCHPRI13(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) |  (value)))
+#define DMA_CLR_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) & ~(value)))
+#define DMA_TOG_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI13 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI13, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_CHPRI field. */
+#define DMA_RD_DCHPRI13_CHPRI(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_CHPRI_MASK) >> DMA_DCHPRI13_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI13_CHPRI(base) (DMA_RD_DCHPRI13_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI13_CHPRI(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_CHPRI_MASK, DMA_DCHPRI13_CHPRI(value)))
+#define DMA_BWR_DCHPRI13_CHPRI(base, value) (DMA_WR_DCHPRI13_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI13, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_DPA field. */
+#define DMA_RD_DCHPRI13_DPA(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_DPA_MASK) >> DMA_DCHPRI13_DPA_SHIFT)
+#define DMA_BRD_DCHPRI13_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI13_DPA(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_DPA_MASK, DMA_DCHPRI13_DPA(value)))
+#define DMA_BWR_DCHPRI13_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI13, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_ECP field. */
+#define DMA_RD_DCHPRI13_ECP(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_ECP_MASK) >> DMA_DCHPRI13_ECP_SHIFT)
+#define DMA_BRD_DCHPRI13_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI13_ECP(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_ECP_MASK, DMA_DCHPRI13_ECP(value)))
+#define DMA_BWR_DCHPRI13_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI12 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI12 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI12 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI12(base)    (DMA_DCHPRI12_REG(base))
+#define DMA_WR_DCHPRI12(base, value) (DMA_DCHPRI12_REG(base) = (value))
+#define DMA_RMW_DCHPRI12(base, mask, value) (DMA_WR_DCHPRI12(base, (DMA_RD_DCHPRI12(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) |  (value)))
+#define DMA_CLR_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) & ~(value)))
+#define DMA_TOG_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI12 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI12, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_CHPRI field. */
+#define DMA_RD_DCHPRI12_CHPRI(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_CHPRI_MASK) >> DMA_DCHPRI12_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI12_CHPRI(base) (DMA_RD_DCHPRI12_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI12_CHPRI(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_CHPRI_MASK, DMA_DCHPRI12_CHPRI(value)))
+#define DMA_BWR_DCHPRI12_CHPRI(base, value) (DMA_WR_DCHPRI12_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI12, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_DPA field. */
+#define DMA_RD_DCHPRI12_DPA(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_DPA_MASK) >> DMA_DCHPRI12_DPA_SHIFT)
+#define DMA_BRD_DCHPRI12_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI12_DPA(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_DPA_MASK, DMA_DCHPRI12_DPA(value)))
+#define DMA_BWR_DCHPRI12_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI12, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_ECP field. */
+#define DMA_RD_DCHPRI12_ECP(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_ECP_MASK) >> DMA_DCHPRI12_ECP_SHIFT)
+#define DMA_BRD_DCHPRI12_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI12_ECP(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_ECP_MASK, DMA_DCHPRI12_ECP(value)))
+#define DMA_BWR_DCHPRI12_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SADDR - TCD Source Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SADDR - TCD Source Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SADDR register
+ */
+/*@{*/
+#define DMA_RD_SADDR(base, index) (DMA_SADDR_REG(base, index))
+#define DMA_WR_SADDR(base, index, value) (DMA_SADDR_REG(base, index) = (value))
+#define DMA_RMW_SADDR(base, index, mask, value) (DMA_WR_SADDR(base, index, (DMA_RD_SADDR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) |  (value)))
+#define DMA_CLR_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) & ~(value)))
+#define DMA_TOG_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SOFF - TCD Signed Source Address Offset
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SOFF - TCD Signed Source Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SOFF register
+ */
+/*@{*/
+#define DMA_RD_SOFF(base, index) (DMA_SOFF_REG(base, index))
+#define DMA_WR_SOFF(base, index, value) (DMA_SOFF_REG(base, index) = (value))
+#define DMA_RMW_SOFF(base, index, mask, value) (DMA_WR_SOFF(base, index, (DMA_RD_SOFF(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) |  (value)))
+#define DMA_CLR_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) & ~(value)))
+#define DMA_TOG_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ATTR - TCD Transfer Attributes
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ATTR - TCD Transfer Attributes (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_ATTR register
+ */
+/*@{*/
+#define DMA_RD_ATTR(base, index) (DMA_ATTR_REG(base, index))
+#define DMA_WR_ATTR(base, index, value) (DMA_ATTR_REG(base, index) = (value))
+#define DMA_RMW_ATTR(base, index, mask, value) (DMA_WR_ATTR(base, index, (DMA_RD_ATTR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) |  (value)))
+#define DMA_CLR_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) & ~(value)))
+#define DMA_TOG_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ATTR bitfields
+ */
+
+/*!
+ * @name Register DMA_ATTR, field DSIZE[2:0] (RW)
+ *
+ * See the SSIZE definition
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_DSIZE field. */
+#define DMA_RD_ATTR_DSIZE(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_DSIZE_MASK) >> DMA_ATTR_DSIZE_SHIFT)
+#define DMA_BRD_ATTR_DSIZE(base, index) (DMA_RD_ATTR_DSIZE(base, index))
+
+/*! @brief Set the DSIZE field to a new value. */
+#define DMA_WR_ATTR_DSIZE(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_DSIZE_MASK, DMA_ATTR_DSIZE(value)))
+#define DMA_BWR_ATTR_DSIZE(base, index, value) (DMA_WR_ATTR_DSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field DMOD[7:3] (RW)
+ *
+ * See the SMOD definition
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_DMOD field. */
+#define DMA_RD_ATTR_DMOD(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_DMOD_MASK) >> DMA_ATTR_DMOD_SHIFT)
+#define DMA_BRD_ATTR_DMOD(base, index) (DMA_RD_ATTR_DMOD(base, index))
+
+/*! @brief Set the DMOD field to a new value. */
+#define DMA_WR_ATTR_DMOD(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_DMOD_MASK, DMA_ATTR_DMOD(value)))
+#define DMA_BWR_ATTR_DMOD(base, index, value) (DMA_WR_ATTR_DMOD(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field SSIZE[10:8] (RW)
+ *
+ * The attempted use of a Reserved encoding causes a configuration error.
+ *
+ * Values:
+ * - 0b000 - 8-bit
+ * - 0b001 - 16-bit
+ * - 0b010 - 32-bit
+ * - 0b011 - Reserved
+ * - 0b100 - 16-byte
+ * - 0b101 - 32-byte
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_SSIZE field. */
+#define DMA_RD_ATTR_SSIZE(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_SSIZE_MASK) >> DMA_ATTR_SSIZE_SHIFT)
+#define DMA_BRD_ATTR_SSIZE(base, index) (DMA_RD_ATTR_SSIZE(base, index))
+
+/*! @brief Set the SSIZE field to a new value. */
+#define DMA_WR_ATTR_SSIZE(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_SSIZE_MASK, DMA_ATTR_SSIZE(value)))
+#define DMA_BWR_ATTR_SSIZE(base, index, value) (DMA_WR_ATTR_SSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field SMOD[15:11] (RW)
+ *
+ * Values:
+ * - 0b00000 - Source address modulo feature is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_SMOD field. */
+#define DMA_RD_ATTR_SMOD(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_SMOD_MASK) >> DMA_ATTR_SMOD_SHIFT)
+#define DMA_BRD_ATTR_SMOD(base, index) (DMA_RD_ATTR_SMOD(base, index))
+
+/*! @brief Set the SMOD field to a new value. */
+#define DMA_WR_ATTR_SMOD(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_SMOD_MASK, DMA_ATTR_SMOD(value)))
+#define DMA_BWR_ATTR_SMOD(base, index, value) (DMA_WR_ATTR_SMOD(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
+ * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
+ * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
+ * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLOFFYES register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLOFFYES(base, index) (DMA_NBYTES_MLOFFYES_REG(base, index))
+#define DMA_WR_NBYTES_MLOFFYES(base, index, value) (DMA_NBYTES_MLOFFYES_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLOFFYES(base, index, mask, value) (DMA_WR_NBYTES_MLOFFYES(base, index, (DMA_RD_NBYTES_MLOFFYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_NBYTES_MLOFFYES bitfields
+ */
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted.
+ * (Although, it may be stalled by using the bandwidth control field, or via
+ * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
+ * written back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_NBYTES field. */
+#define DMA_RD_NBYTES_MLOFFYES_NBYTES(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) >> DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_NBYTES(base, index) (DMA_RD_NBYTES_MLOFFYES_NBYTES(base, index))
+
+/*! @brief Set the NBYTES field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_NBYTES(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_NBYTES_MASK, DMA_NBYTES_MLOFFYES_NBYTES(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_NBYTES(base, index, value) (DMA_WR_NBYTES_MLOFFYES_NBYTES(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_MLOFF field. */
+#define DMA_RD_NBYTES_MLOFFYES_MLOFF(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) >> DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_MLOFF(base, index) (DMA_RD_NBYTES_MLOFFYES_MLOFF(base, index))
+
+/*! @brief Set the MLOFF field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_MLOFF(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_MLOFF_MASK, DMA_NBYTES_MLOFFYES_MLOFF(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_MLOFF(base, index, value) (DMA_WR_NBYTES_MLOFFYES_MLOFF(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the DADDR
+ * - 0b1 - The minor loop offset is applied to the DADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_DMLOE field. */
+#define DMA_RD_NBYTES_MLOFFYES_DMLOE(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) >> DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_DMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))
+
+/*! @brief Set the DMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_DMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_DMLOE_MASK, DMA_NBYTES_MLOFFYES_DMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_DMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_DMLOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the SADDR
+ * - 0b1 - The minor loop offset is applied to the SADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_SMLOE field. */
+#define DMA_RD_NBYTES_MLOFFYES_SMLOE(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) >> DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_SMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))
+
+/*! @brief Set the SMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_SMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_SMLOE_MASK, DMA_NBYTES_MLOFFYES_SMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_SMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_SMLOE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
+ * register to use depends on whether minor loop mapping is disabled, enabled but not
+ * used for this channel, or enabled and used. TCD word 2 is defined as follows
+ * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
+ * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
+ * for TCD word 2's definition.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLNO register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLNO(base, index) (DMA_NBYTES_MLNO_REG(base, index))
+#define DMA_WR_NBYTES_MLNO(base, index, value) (DMA_NBYTES_MLNO_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLNO(base, index, mask, value) (DMA_WR_NBYTES_MLNO(base, index, (DMA_RD_NBYTES_MLNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
+ * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
+ * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
+ * the TCD_NBYTES_MLNO register description.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLOFFNO register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLOFFNO(base, index) (DMA_NBYTES_MLOFFNO_REG(base, index))
+#define DMA_WR_NBYTES_MLOFFNO(base, index, value) (DMA_NBYTES_MLOFFNO_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLOFFNO(base, index, mask, value) (DMA_WR_NBYTES_MLOFFNO(base, index, (DMA_RD_NBYTES_MLOFFNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_NBYTES_MLOFFNO bitfields
+ */
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted;
+ * although, it may be stalled by using the bandwidth control field, or via
+ * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
+ * back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_NBYTES field. */
+#define DMA_RD_NBYTES_MLOFFNO_NBYTES(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) >> DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_NBYTES(base, index) (DMA_RD_NBYTES_MLOFFNO_NBYTES(base, index))
+
+/*! @brief Set the NBYTES field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_NBYTES(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_NBYTES_MASK, DMA_NBYTES_MLOFFNO_NBYTES(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_NBYTES(base, index, value) (DMA_WR_NBYTES_MLOFFNO_NBYTES(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the DADDR
+ * - 0b1 - The minor loop offset is applied to the DADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_DMLOE field. */
+#define DMA_RD_NBYTES_MLOFFNO_DMLOE(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) >> DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_DMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))
+
+/*! @brief Set the DMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_DMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_DMLOE_MASK, DMA_NBYTES_MLOFFNO_DMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_DMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_DMLOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the SADDR
+ * - 0b1 - The minor loop offset is applied to the SADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_SMLOE field. */
+#define DMA_RD_NBYTES_MLOFFNO_SMLOE(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) >> DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_SMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))
+
+/*! @brief Set the SMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_SMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_SMLOE_MASK, DMA_NBYTES_MLOFFNO_SMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_SMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_SMLOE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SLAST - TCD Last Source Address Adjustment
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SLAST - TCD Last Source Address Adjustment (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SLAST register
+ */
+/*@{*/
+#define DMA_RD_SLAST(base, index) (DMA_SLAST_REG(base, index))
+#define DMA_WR_SLAST(base, index, value) (DMA_SLAST_REG(base, index) = (value))
+#define DMA_RMW_SLAST(base, index, mask, value) (DMA_WR_SLAST(base, index, (DMA_RD_SLAST(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) |  (value)))
+#define DMA_CLR_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) & ~(value)))
+#define DMA_TOG_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DADDR - TCD Destination Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DADDR - TCD Destination Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DADDR register
+ */
+/*@{*/
+#define DMA_RD_DADDR(base, index) (DMA_DADDR_REG(base, index))
+#define DMA_WR_DADDR(base, index, value) (DMA_DADDR_REG(base, index) = (value))
+#define DMA_RMW_DADDR(base, index, mask, value) (DMA_WR_DADDR(base, index, (DMA_RD_DADDR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) |  (value)))
+#define DMA_CLR_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) & ~(value)))
+#define DMA_TOG_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DOFF - TCD Signed Destination Address Offset
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DOFF - TCD Signed Destination Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DOFF register
+ */
+/*@{*/
+#define DMA_RD_DOFF(base, index) (DMA_DOFF_REG(base, index))
+#define DMA_WR_DOFF(base, index, value) (DMA_DOFF_REG(base, index) = (value))
+#define DMA_RMW_DOFF(base, index, mask, value) (DMA_WR_DOFF(base, index, (DMA_RD_DOFF(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) |  (value)))
+#define DMA_CLR_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) & ~(value)))
+#define DMA_TOG_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
+ * follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CITER_ELINKNO register
+ */
+/*@{*/
+#define DMA_RD_CITER_ELINKNO(base, index) (DMA_CITER_ELINKNO_REG(base, index))
+#define DMA_WR_CITER_ELINKNO(base, index, value) (DMA_CITER_ELINKNO_REG(base, index) = (value))
+#define DMA_RMW_CITER_ELINKNO(base, index, mask, value) (DMA_WR_CITER_ELINKNO(base, index, (DMA_RD_CITER_ELINKNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) |  (value)))
+#define DMA_CLR_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) & ~(value)))
+#define DMA_TOG_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_CITER_ELINKNO, field CITER[14:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKNO_CITER field. */
+#define DMA_RD_CITER_ELINKNO_CITER(base, index) ((DMA_CITER_ELINKNO_REG(base, index) & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT)
+#define DMA_BRD_CITER_ELINKNO_CITER(base, index) (DMA_RD_CITER_ELINKNO_CITER(base, index))
+
+/*! @brief Set the CITER field to a new value. */
+#define DMA_WR_CITER_ELINKNO_CITER(base, index, value) (DMA_RMW_CITER_ELINKNO(base, index, DMA_CITER_ELINKNO_CITER_MASK, DMA_CITER_ELINKNO_CITER(value)))
+#define DMA_BWR_CITER_ELINKNO_CITER(base, index, value) (DMA_WR_CITER_ELINKNO_CITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKNO_ELINK field. */
+#define DMA_RD_CITER_ELINKNO_ELINK(base, index) ((DMA_CITER_ELINKNO_REG(base, index) & DMA_CITER_ELINKNO_ELINK_MASK) >> DMA_CITER_ELINKNO_ELINK_SHIFT)
+#define DMA_BRD_CITER_ELINKNO_ELINK(base, index) (BITBAND_ACCESS16(&DMA_CITER_ELINKNO_REG(base, index), DMA_CITER_ELINKNO_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_CITER_ELINKNO_ELINK(base, index, value) (DMA_RMW_CITER_ELINKNO(base, index, DMA_CITER_ELINKNO_ELINK_MASK, DMA_CITER_ELINKNO_ELINK(value)))
+#define DMA_BWR_CITER_ELINKNO_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CITER_ELINKNO_REG(base, index), DMA_CITER_ELINKNO_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CITER_ELINKYES register
+ */
+/*@{*/
+#define DMA_RD_CITER_ELINKYES(base, index) (DMA_CITER_ELINKYES_REG(base, index))
+#define DMA_WR_CITER_ELINKYES(base, index, value) (DMA_CITER_ELINKYES_REG(base, index) = (value))
+#define DMA_RMW_CITER_ELINKYES(base, index, mask, value) (DMA_WR_CITER_ELINKYES(base, index, (DMA_RD_CITER_ELINKYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) |  (value)))
+#define DMA_CLR_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) & ~(value)))
+#define DMA_TOG_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field CITER[8:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_CITER field. */
+#define DMA_RD_CITER_ELINKYES_CITER(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_CITER(base, index) (DMA_RD_CITER_ELINKYES_CITER(base, index))
+
+/*! @brief Set the CITER field to a new value. */
+#define DMA_WR_CITER_ELINKYES_CITER(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_CITER_MASK, DMA_CITER_ELINKYES_CITER(value)))
+#define DMA_BWR_CITER_ELINKYES_CITER(base, index, value) (DMA_WR_CITER_ELINKYES_CITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request to the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_LINKCH field. */
+#define DMA_RD_CITER_ELINKYES_LINKCH(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_LINKCH_MASK) >> DMA_CITER_ELINKYES_LINKCH_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_LINKCH(base, index) (DMA_RD_CITER_ELINKYES_LINKCH(base, index))
+
+/*! @brief Set the LINKCH field to a new value. */
+#define DMA_WR_CITER_ELINKYES_LINKCH(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_LINKCH_MASK, DMA_CITER_ELINKYES_LINKCH(value)))
+#define DMA_BWR_CITER_ELINKYES_LINKCH(base, index, value) (DMA_WR_CITER_ELINKYES_LINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_ELINK field. */
+#define DMA_RD_CITER_ELINKYES_ELINK(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_ELINK_MASK) >> DMA_CITER_ELINKYES_ELINK_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_ELINK(base, index) (BITBAND_ACCESS16(&DMA_CITER_ELINKYES_REG(base, index), DMA_CITER_ELINKYES_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_CITER_ELINKYES_ELINK(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_ELINK_MASK, DMA_CITER_ELINKYES_ELINK(value)))
+#define DMA_BWR_CITER_ELINKYES_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CITER_ELINKYES_REG(base, index), DMA_CITER_ELINKYES_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DLAST_SGA register
+ */
+/*@{*/
+#define DMA_RD_DLAST_SGA(base, index) (DMA_DLAST_SGA_REG(base, index))
+#define DMA_WR_DLAST_SGA(base, index, value) (DMA_DLAST_SGA_REG(base, index) = (value))
+#define DMA_RMW_DLAST_SGA(base, index, mask, value) (DMA_WR_DLAST_SGA(base, index, (DMA_RD_DLAST_SGA(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) |  (value)))
+#define DMA_CLR_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) & ~(value)))
+#define DMA_TOG_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CSR - TCD Control and Status
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CSR - TCD Control and Status (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_CSR register
+ */
+/*@{*/
+#define DMA_RD_CSR(base, index)  (DMA_CSR_REG(base, index))
+#define DMA_WR_CSR(base, index, value) (DMA_CSR_REG(base, index) = (value))
+#define DMA_RMW_CSR(base, index, mask, value) (DMA_WR_CSR(base, index, (DMA_RD_CSR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) |  (value)))
+#define DMA_CLR_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) & ~(value)))
+#define DMA_TOG_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CSR bitfields
+ */
+
+/*!
+ * @name Register DMA_CSR, field START[0] (RW)
+ *
+ * If this flag is set, the channel is requesting service. The eDMA hardware
+ * automatically clears this flag after the channel begins execution.
+ *
+ * Values:
+ * - 0b0 - The channel is not explicitly started
+ * - 0b1 - The channel is explicitly started via a software initiated service
+ *     request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_START field. */
+#define DMA_RD_CSR_START(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_START_MASK) >> DMA_CSR_START_SHIFT)
+#define DMA_BRD_CSR_START(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_START_SHIFT))
+
+/*! @brief Set the START field to a new value. */
+#define DMA_WR_CSR_START(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_START_MASK, DMA_CSR_START(value)))
+#define DMA_BWR_CSR_START(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_START_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field INTMAJOR[1] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT when the current major iteration count reaches
+ * zero.
+ *
+ * Values:
+ * - 0b0 - The end-of-major loop interrupt is disabled
+ * - 0b1 - The end-of-major loop interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_INTMAJOR field. */
+#define DMA_RD_CSR_INTMAJOR(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_INTMAJOR_MASK) >> DMA_CSR_INTMAJOR_SHIFT)
+#define DMA_BRD_CSR_INTMAJOR(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTMAJOR_SHIFT))
+
+/*! @brief Set the INTMAJOR field to a new value. */
+#define DMA_WR_CSR_INTMAJOR(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_INTMAJOR_MASK, DMA_CSR_INTMAJOR(value)))
+#define DMA_BWR_CSR_INTMAJOR(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTMAJOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field INTHALF[2] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT register when the current major iteration count
+ * reaches the halfway point. Specifically, the comparison performed by the eDMA
+ * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
+ * provided to support double-buffered (aka ping-pong) schemes or other types of data
+ * movement where the processor needs an early indication of the transfer's
+ * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
+ *
+ * Values:
+ * - 0b0 - The half-point interrupt is disabled
+ * - 0b1 - The half-point interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_INTHALF field. */
+#define DMA_RD_CSR_INTHALF(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_INTHALF_MASK) >> DMA_CSR_INTHALF_SHIFT)
+#define DMA_BRD_CSR_INTHALF(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTHALF_SHIFT))
+
+/*! @brief Set the INTHALF field to a new value. */
+#define DMA_WR_CSR_INTHALF(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_INTHALF_MASK, DMA_CSR_INTHALF(value)))
+#define DMA_BWR_CSR_INTHALF(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTHALF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field DREQ[3] (RW)
+ *
+ * If this flag is set, the eDMA hardware automatically clears the corresponding
+ * ERQ bit when the current major iteration count reaches zero.
+ *
+ * Values:
+ * - 0b0 - The channel's ERQ bit is not affected
+ * - 0b1 - The channel's ERQ bit is cleared when the major loop is complete
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_DREQ field. */
+#define DMA_RD_CSR_DREQ(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_DREQ_MASK) >> DMA_CSR_DREQ_SHIFT)
+#define DMA_BRD_CSR_DREQ(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DREQ_SHIFT))
+
+/*! @brief Set the DREQ field to a new value. */
+#define DMA_WR_CSR_DREQ(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_DREQ_MASK, DMA_CSR_DREQ(value)))
+#define DMA_BWR_CSR_DREQ(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field ESG[4] (RW)
+ *
+ * As the channel completes the major loop, this flag enables scatter/gather
+ * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
+ * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
+ * loaded as the transfer control descriptor into the local memory. To support the
+ * dynamic scatter/gather coherency model, this field is forced to zero when
+ * written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0b0 - The current channel's TCD is normal format.
+ * - 0b1 - The current channel's TCD specifies a scatter gather format. The
+ *     DLASTSGA field provides a memory pointer to the next TCD to be loaded into
+ *     this channel after the major loop completes its execution.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_ESG field. */
+#define DMA_RD_CSR_ESG(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_ESG_MASK) >> DMA_CSR_ESG_SHIFT)
+#define DMA_BRD_CSR_ESG(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ESG_SHIFT))
+
+/*! @brief Set the ESG field to a new value. */
+#define DMA_WR_CSR_ESG(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_ESG_MASK, DMA_CSR_ESG(value)))
+#define DMA_BWR_CSR_ESG(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ESG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field MAJORELINK[5] (RW)
+ *
+ * As the channel completes the major loop, this flag enables the linking to
+ * another channel, defined by MAJORLINKCH. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. To support the dynamic linking coherency model,
+ * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_MAJORELINK field. */
+#define DMA_RD_CSR_MAJORELINK(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_MAJORELINK_MASK) >> DMA_CSR_MAJORELINK_SHIFT)
+#define DMA_BRD_CSR_MAJORELINK(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_MAJORELINK_SHIFT))
+
+/*! @brief Set the MAJORELINK field to a new value. */
+#define DMA_WR_CSR_MAJORELINK(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_MAJORELINK_MASK, DMA_CSR_MAJORELINK(value)))
+#define DMA_BWR_CSR_MAJORELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_MAJORELINK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field ACTIVE[6] (RW)
+ *
+ * This flag signals the channel is currently in execution. It is set when
+ * channel service begins, and the eDMA clears it as the minor loop completes or if
+ * any error condition is detected. This bit resets to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_ACTIVE field. */
+#define DMA_RD_CSR_ACTIVE(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_ACTIVE_MASK) >> DMA_CSR_ACTIVE_SHIFT)
+#define DMA_BRD_CSR_ACTIVE(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ACTIVE_SHIFT))
+
+/*! @brief Set the ACTIVE field to a new value. */
+#define DMA_WR_CSR_ACTIVE(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_ACTIVE_MASK, DMA_CSR_ACTIVE(value)))
+#define DMA_BWR_CSR_ACTIVE(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ACTIVE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field DONE[7] (RW)
+ *
+ * This flag indicates the eDMA has completed the major loop. The eDMA engine
+ * sets it as the CITER count reaches zero; The software clears it, or the hardware
+ * when the channel is activated. This bit must be cleared to write the
+ * MAJORELINK or ESG bits.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_DONE field. */
+#define DMA_RD_CSR_DONE(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT)
+#define DMA_BRD_CSR_DONE(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DONE_SHIFT))
+
+/*! @brief Set the DONE field to a new value. */
+#define DMA_WR_CSR_DONE(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_DONE_MASK, DMA_CSR_DONE(value)))
+#define DMA_BWR_CSR_DONE(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DONE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field MAJORLINKCH[11:8] (RW)
+ *
+ * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
+ * performed after the major loop counter is exhausted. else After the major loop
+ * counter is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_MAJORLINKCH field. */
+#define DMA_RD_CSR_MAJORLINKCH(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_MAJORLINKCH_MASK) >> DMA_CSR_MAJORLINKCH_SHIFT)
+#define DMA_BRD_CSR_MAJORLINKCH(base, index) (DMA_RD_CSR_MAJORLINKCH(base, index))
+
+/*! @brief Set the MAJORLINKCH field to a new value. */
+#define DMA_WR_CSR_MAJORLINKCH(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_MAJORLINKCH_MASK, DMA_CSR_MAJORLINKCH(value)))
+#define DMA_BWR_CSR_MAJORLINKCH(base, index, value) (DMA_WR_CSR_MAJORLINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field BWC[15:14] (RW)
+ *
+ * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
+ * the eDMA processes the minor loop, it continuously generates read/write
+ * sequences until the minor count is exhausted. This field forces the eDMA to stall
+ * after the completion of each read/write access to control the bus request
+ * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
+ * this field is ignored between the first and second transfers and after the
+ * last write of each minor loop. This behavior is a side effect of reducing
+ * start-up latency.
+ *
+ * Values:
+ * - 0b00 - No eDMA engine stalls
+ * - 0b01 - Reserved
+ * - 0b10 - eDMA engine stalls for 4 cycles after each r/w
+ * - 0b11 - eDMA engine stalls for 8 cycles after each r/w
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_BWC field. */
+#define DMA_RD_CSR_BWC(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_BWC_MASK) >> DMA_CSR_BWC_SHIFT)
+#define DMA_BRD_CSR_BWC(base, index) (DMA_RD_CSR_BWC(base, index))
+
+/*! @brief Set the BWC field to a new value. */
+#define DMA_WR_CSR_BWC(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_BWC_MASK, DMA_CSR_BWC(value)))
+#define DMA_BWR_CSR_BWC(base, index, value) (DMA_WR_CSR_BWC(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
+ * follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_BITER_ELINKYES register
+ */
+/*@{*/
+#define DMA_RD_BITER_ELINKYES(base, index) (DMA_BITER_ELINKYES_REG(base, index))
+#define DMA_WR_BITER_ELINKYES(base, index, value) (DMA_BITER_ELINKYES_REG(base, index) = (value))
+#define DMA_RMW_BITER_ELINKYES(base, index, mask, value) (DMA_WR_BITER_ELINKYES(base, index, (DMA_RD_BITER_ELINKYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) |  (value)))
+#define DMA_CLR_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) & ~(value)))
+#define DMA_TOG_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_BITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field BITER[8:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_BITER field. */
+#define DMA_RD_BITER_ELINKYES_BITER(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_BITER_MASK) >> DMA_BITER_ELINKYES_BITER_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_BITER(base, index) (DMA_RD_BITER_ELINKYES_BITER(base, index))
+
+/*! @brief Set the BITER field to a new value. */
+#define DMA_WR_BITER_ELINKYES_BITER(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_BITER_MASK, DMA_BITER_ELINKYES_BITER(value)))
+#define DMA_BWR_BITER_ELINKYES_BITER(base, index, value) (DMA_WR_BITER_ELINKYES_BITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START]
+ * bit. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the major
+ * iteration count is exhausted, the contents of this field is reloaded into the
+ * CITER field.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_LINKCH field. */
+#define DMA_RD_BITER_ELINKYES_LINKCH(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_LINKCH_MASK) >> DMA_BITER_ELINKYES_LINKCH_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_LINKCH(base, index) (DMA_RD_BITER_ELINKYES_LINKCH(base, index))
+
+/*! @brief Set the LINKCH field to a new value. */
+#define DMA_WR_BITER_ELINKYES_LINKCH(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_LINKCH_MASK, DMA_BITER_ELINKYES_LINKCH(value)))
+#define DMA_BWR_BITER_ELINKYES_LINKCH(base, index, value) (DMA_WR_BITER_ELINKYES_LINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking disables, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded into
+ * the CITER field.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_ELINK field. */
+#define DMA_RD_BITER_ELINKYES_ELINK(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_ELINK_MASK) >> DMA_BITER_ELINKYES_ELINK_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_ELINK(base, index) (BITBAND_ACCESS16(&DMA_BITER_ELINKYES_REG(base, index), DMA_BITER_ELINKYES_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_BITER_ELINKYES_ELINK(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_ELINK_MASK, DMA_BITER_ELINKYES_ELINK(value)))
+#define DMA_BWR_BITER_ELINKYES_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_BITER_ELINKYES_REG(base, index), DMA_BITER_ELINKYES_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
+ * as follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_BITER_ELINKNO register
+ */
+/*@{*/
+#define DMA_RD_BITER_ELINKNO(base, index) (DMA_BITER_ELINKNO_REG(base, index))
+#define DMA_WR_BITER_ELINKNO(base, index, value) (DMA_BITER_ELINKNO_REG(base, index) = (value))
+#define DMA_RMW_BITER_ELINKNO(base, index, mask, value) (DMA_WR_BITER_ELINKNO(base, index, (DMA_RD_BITER_ELINKNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) |  (value)))
+#define DMA_CLR_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) & ~(value)))
+#define DMA_TOG_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_BITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_BITER_ELINKNO, field BITER[14:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKNO_BITER field. */
+#define DMA_RD_BITER_ELINKNO_BITER(base, index) ((DMA_BITER_ELINKNO_REG(base, index) & DMA_BITER_ELINKNO_BITER_MASK) >> DMA_BITER_ELINKNO_BITER_SHIFT)
+#define DMA_BRD_BITER_ELINKNO_BITER(base, index) (DMA_RD_BITER_ELINKNO_BITER(base, index))
+
+/*! @brief Set the BITER field to a new value. */
+#define DMA_WR_BITER_ELINKNO_BITER(base, index, value) (DMA_RMW_BITER_ELINKNO(base, index, DMA_BITER_ELINKNO_BITER_MASK, DMA_BITER_ELINKNO_BITER(value)))
+#define DMA_BWR_BITER_ELINKNO_BITER(base, index, value) (DMA_WR_BITER_ELINKNO_BITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded
+ * into the CITER field.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKNO_ELINK field. */
+#define DMA_RD_BITER_ELINKNO_ELINK(base, index) ((DMA_BITER_ELINKNO_REG(base, index) & DMA_BITER_ELINKNO_ELINK_MASK) >> DMA_BITER_ELINKNO_ELINK_SHIFT)
+#define DMA_BRD_BITER_ELINKNO_ELINK(base, index) (BITBAND_ACCESS16(&DMA_BITER_ELINKNO_REG(base, index), DMA_BITER_ELINKNO_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_BITER_ELINKNO_ELINK(base, index, value) (DMA_RMW_BITER_ELINKNO(base, index, DMA_BITER_ELINKNO_ELINK_MASK, DMA_BITER_ELINKNO_ELINK(value)))
+#define DMA_BWR_BITER_ELINKNO_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_BITER_ELINKNO_REG(base, index), DMA_BITER_ELINKNO_ELINK_SHIFT) = (value))
+/*@}*/
+
+/* Register macros for indexed access to DMA channel priority registers */
+/*
+ * Constants and macros for entire DMA_DCHPRIn register
+ */
+#define DMA_DCHPRIn_INDEX(channel)          (((channel) & ~0x03U) | (3 - ((channel) & 0x03U)))
+#define DMA_DCHPRIn_REG(base, index)        (((volatile uint8_t *)&DMA_DCHPRI3_REG(base))[DMA_DCHPRIn_INDEX(index)])
+#define DMA_RD_DCHPRIn(base, index)         (DMA_DCHPRIn_REG((base), (index)))
+#define DMA_WR_DCHPRIn(base, index, value)  (DMA_DCHPRIn_REG((base), (index)) = (value))
+#define DMA_SET_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) |  (value)))
+#define DMA_CLR_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) & ~(value)))
+#define DMA_TOG_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) ^  (value)))
+
+/*
+ * Register DMA_DCHPRIn, bit field CHPRI
+ */
+/* Read current value of the CHPRI bit field. */
+#define DMA_RD_DCHPRIn_CHPRI(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_CHPRI_MASK) >> DMA_DCHPRI0_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRIn_CHPRI(base, index) (DMA_RD_DCHPRIn_CHPRI((base), (index)))
+
+/* Set the CHPRI bit field to a new value. */
+#define DMA_WR_DCHPRIn_CHPRI(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_CHPRI_MASK) | DMA_DCHPRI0_CHPRI(value)))
+#define DMA_BWR_DCHPRIn_CHPRI(base, index, value) (DMA_WR_DCHPRIn_CHPRI((base), (index), (value)))
+
+/*
+ * Register DMA_DCHPRIn, bit field DPA
+ */
+/* Read current value of the DPA bit field. */
+#define DMA_RD_DCHPRIn_DPA(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_DPA_MASK) >> DMA_DCHPRI0_DPA_SHIFT)
+#define DMA_BRD_DCHPRIn_DPA(base, index) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_DPA_SHIFT))
+
+/* Set the DPA bit field to a new value. */
+#define DMA_WR_DCHPRIn_DPA(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_DPA_MASK) | DMA_DCHPRI0_DPA(value)))
+#define DMA_BWR_DCHPRIn_DPA(base, index, value) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_DPA_SHIFT) = (value))
+
+/*
+ * Register DMA_DCHPRIn, bit field ECP
+ */
+/* Read current value of the ECP bit field. */
+#define DMA_RD_DCHPRIn_ECP(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_ECP_MASK) >> DMA_DCHPRI0_ECP_SHIFT)
+#define DMA_BRD_DCHPRIn_ECP(base, index) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_ECP_SHIFT))
+
+/* Set the ECP bit field to a new value. */
+#define DMA_WR_DCHPRIn_ECP(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_ECP_MASK) | DMA_DCHPRI0_ECP(value)))
+#define DMA_BWR_DCHPRIn_ECP(base, index, value) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_ECP_SHIFT) = (value))
+
+/*
+ * MK64F12 DMAMUX
+ *
+ * DMA channel multiplexor
+ *
+ * Registers defined in this header file:
+ * - DMAMUX_CHCFG - Channel Configuration register
+ */
+
+#define DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
+#define DMAMUX_IDX (0U) /*!< Instance number for DMAMUX. */
+
+/*******************************************************************************
+ * DMAMUX_CHCFG - Channel Configuration register
+ ******************************************************************************/
+
+/*!
+ * @brief DMAMUX_CHCFG - Channel Configuration register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Each of the DMA channels can be independently enabled/disabled and associated
+ * with one of the DMA slots (peripheral slots or always-on slots) in the
+ * system. Setting multiple CHCFG registers with the same source value will result in
+ * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
+ * Before changing the trigger or source settings, a DMA channel must be disabled
+ * via CHCFGn[ENBL].
+ */
+/*!
+ * @name Constants and macros for entire DMAMUX_CHCFG register
+ */
+/*@{*/
+#define DMAMUX_RD_CHCFG(base, index) (DMAMUX_CHCFG_REG(base, index))
+#define DMAMUX_WR_CHCFG(base, index, value) (DMAMUX_CHCFG_REG(base, index) = (value))
+#define DMAMUX_RMW_CHCFG(base, index, mask, value) (DMAMUX_WR_CHCFG(base, index, (DMAMUX_RD_CHCFG(base, index) & ~(mask)) | (value)))
+#define DMAMUX_SET_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) |  (value)))
+#define DMAMUX_CLR_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) & ~(value)))
+#define DMAMUX_TOG_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMAMUX_CHCFG bitfields
+ */
+
+/*!
+ * @name Register DMAMUX_CHCFG, field SOURCE[5:0] (RW)
+ *
+ * Specifies which DMA source, if any, is routed to a particular DMA channel.
+ * See your device's chip configuration details for information about the
+ * peripherals and their slot numbers.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_SOURCE field. */
+#define DMAMUX_RD_CHCFG_SOURCE(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT)
+#define DMAMUX_BRD_CHCFG_SOURCE(base, index) (DMAMUX_RD_CHCFG_SOURCE(base, index))
+
+/*! @brief Set the SOURCE field to a new value. */
+#define DMAMUX_WR_CHCFG_SOURCE(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_SOURCE_MASK, DMAMUX_CHCFG_SOURCE(value)))
+#define DMAMUX_BWR_CHCFG_SOURCE(base, index, value) (DMAMUX_WR_CHCFG_SOURCE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field TRIG[6] (RW)
+ *
+ * Enables the periodic trigger capability for the triggered DMA channel.
+ *
+ * Values:
+ * - 0b0 - Triggering is disabled. If triggering is disabled and ENBL is set,
+ *     the DMA Channel will simply route the specified source to the DMA channel.
+ *     (Normal mode)
+ * - 0b1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
+ *     DMAMUX is in Periodic Trigger mode.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_TRIG field. */
+#define DMAMUX_RD_CHCFG_TRIG(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_TRIG_MASK) >> DMAMUX_CHCFG_TRIG_SHIFT)
+#define DMAMUX_BRD_CHCFG_TRIG(base, index) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT))
+
+/*! @brief Set the TRIG field to a new value. */
+#define DMAMUX_WR_CHCFG_TRIG(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_TRIG_MASK, DMAMUX_CHCFG_TRIG(value)))
+#define DMAMUX_BWR_CHCFG_TRIG(base, index, value) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field ENBL[7] (RW)
+ *
+ * Enables the DMA channel.
+ *
+ * Values:
+ * - 0b0 - DMA channel is disabled. This mode is primarily used during
+ *     configuration of the DMAMux. The DMA has separate channel enables/disables, which
+ *     should be used to disable or reconfigure a DMA channel.
+ * - 0b1 - DMA channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_ENBL field. */
+#define DMAMUX_RD_CHCFG_ENBL(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT)
+#define DMAMUX_BRD_CHCFG_ENBL(base, index) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT))
+
+/*! @brief Set the ENBL field to a new value. */
+#define DMAMUX_WR_CHCFG_ENBL(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_ENBL_MASK, DMAMUX_CHCFG_ENBL(value)))
+#define DMAMUX_BWR_CHCFG_ENBL(base, index, value) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 ENET
+ *
+ * Ethernet MAC-NET Core
+ *
+ * Registers defined in this header file:
+ * - ENET_EIR - Interrupt Event Register
+ * - ENET_EIMR - Interrupt Mask Register
+ * - ENET_RDAR - Receive Descriptor Active Register
+ * - ENET_TDAR - Transmit Descriptor Active Register
+ * - ENET_ECR - Ethernet Control Register
+ * - ENET_MMFR - MII Management Frame Register
+ * - ENET_MSCR - MII Speed Control Register
+ * - ENET_MIBC - MIB Control Register
+ * - ENET_RCR - Receive Control Register
+ * - ENET_TCR - Transmit Control Register
+ * - ENET_PALR - Physical Address Lower Register
+ * - ENET_PAUR - Physical Address Upper Register
+ * - ENET_OPD - Opcode/Pause Duration Register
+ * - ENET_IAUR - Descriptor Individual Upper Address Register
+ * - ENET_IALR - Descriptor Individual Lower Address Register
+ * - ENET_GAUR - Descriptor Group Upper Address Register
+ * - ENET_GALR - Descriptor Group Lower Address Register
+ * - ENET_TFWR - Transmit FIFO Watermark Register
+ * - ENET_RDSR - Receive Descriptor Ring Start Register
+ * - ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ * - ENET_MRBR - Maximum Receive Buffer Size Register
+ * - ENET_RSFL - Receive FIFO Section Full Threshold
+ * - ENET_RSEM - Receive FIFO Section Empty Threshold
+ * - ENET_RAEM - Receive FIFO Almost Empty Threshold
+ * - ENET_RAFL - Receive FIFO Almost Full Threshold
+ * - ENET_TSEM - Transmit FIFO Section Empty Threshold
+ * - ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ * - ENET_TAFL - Transmit FIFO Almost Full Threshold
+ * - ENET_TIPG - Transmit Inter-Packet Gap
+ * - ENET_FTRL - Frame Truncation Length
+ * - ENET_TACC - Transmit Accelerator Function Configuration
+ * - ENET_RACC - Receive Accelerator Function Configuration
+ * - ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ * - ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ * - ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ * - ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ * - ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ * - ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ * - ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ * - ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ * - ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ * - ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ * - ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ * - ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ * - ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ * - ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ * - ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ * - ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ * - ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ * - ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ * - ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ * - ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ * - ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ * - ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ * - ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ * - ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ * - ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ * - ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ * - ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ * - ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ * - ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ * - ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ * - ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ * - ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ * - ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ * - ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ * - ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ * - ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ * - ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ * - ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ * - ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ * - ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ * - ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ * - ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ * - ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ * - ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ * - ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ * - ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ * - ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ * - ENET_ATCR - Adjustable Timer Control Register
+ * - ENET_ATVR - Timer Value Register
+ * - ENET_ATOFF - Timer Offset Register
+ * - ENET_ATPER - Timer Period Register
+ * - ENET_ATCOR - Timer Correction Register
+ * - ENET_ATINC - Time-Stamping Clock Period Register
+ * - ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ * - ENET_TGSR - Timer Global Status Register
+ * - ENET_TCSR - Timer Control Status Register
+ * - ENET_TCCR - Timer Compare Capture Register
+ */
+
+#define ENET_INSTANCE_COUNT (1U) /*!< Number of instances of the ENET module. */
+#define ENET_IDX (0U) /*!< Instance number for ENET. */
+
+/*******************************************************************************
+ * ENET_EIR - Interrupt Event Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_EIR - Interrupt Event Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an event occurs that sets a bit in EIR, an interrupt occurs if the
+ * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
+ * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
+ * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
+ * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
+ * Legacy mode does not require these flags to be enabled.
+ */
+/*!
+ * @name Constants and macros for entire ENET_EIR register
+ */
+/*@{*/
+#define ENET_RD_EIR(base)        (ENET_EIR_REG(base))
+#define ENET_WR_EIR(base, value) (ENET_EIR_REG(base) = (value))
+#define ENET_RMW_EIR(base, mask, value) (ENET_WR_EIR(base, (ENET_RD_EIR(base) & ~(mask)) | (value)))
+#define ENET_SET_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) |  (value)))
+#define ENET_CLR_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) & ~(value)))
+#define ENET_TOG_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_EIR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
+ *
+ * The adjustable timer reached the period event. A period event interrupt can
+ * be generated if ATCR[PEREN] is set and the timer wraps according to the
+ * periodic setting in the ATPER register. Set the timer period value before setting
+ * ATCR[PEREN].
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TS_TIMER field. */
+#define ENET_RD_EIR_TS_TIMER(base) ((ENET_EIR_REG(base) & ENET_EIR_TS_TIMER_MASK) >> ENET_EIR_TS_TIMER_SHIFT)
+#define ENET_BRD_EIR_TS_TIMER(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_TIMER_SHIFT))
+
+/*! @brief Set the TS_TIMER field to a new value. */
+#define ENET_WR_EIR_TS_TIMER(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TS_TIMER(value)))
+#define ENET_BWR_EIR_TS_TIMER(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_TIMER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
+ *
+ * Indicates that the timestamp of the last transmitted timing frame is
+ * available in the ATSTMP register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TS_AVAIL field. */
+#define ENET_RD_EIR_TS_AVAIL(base) ((ENET_EIR_REG(base) & ENET_EIR_TS_AVAIL_MASK) >> ENET_EIR_TS_AVAIL_SHIFT)
+#define ENET_BRD_EIR_TS_AVAIL(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_AVAIL_SHIFT))
+
+/*! @brief Set the TS_AVAIL field to a new value. */
+#define ENET_WR_EIR_TS_AVAIL(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TS_AVAIL_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TS_AVAIL(value)))
+#define ENET_BWR_EIR_TS_AVAIL(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_AVAIL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field WAKEUP[17] (W1C)
+ *
+ * Read-only status bit to indicate that a magic packet has been detected. Will
+ * act only if ECR[MAGICEN] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_WAKEUP field. */
+#define ENET_RD_EIR_WAKEUP(base) ((ENET_EIR_REG(base) & ENET_EIR_WAKEUP_MASK) >> ENET_EIR_WAKEUP_SHIFT)
+#define ENET_BRD_EIR_WAKEUP(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_WAKEUP_SHIFT))
+
+/*! @brief Set the WAKEUP field to a new value. */
+#define ENET_WR_EIR_WAKEUP(base, value) (ENET_RMW_EIR(base, (ENET_EIR_WAKEUP_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_WAKEUP(value)))
+#define ENET_BWR_EIR_WAKEUP(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_WAKEUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field PLR[18] (W1C)
+ *
+ * Indicates a frame was received with a payload length error. See Frame
+ * Length/Type Verification: Payload Length Check for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_PLR field. */
+#define ENET_RD_EIR_PLR(base) ((ENET_EIR_REG(base) & ENET_EIR_PLR_MASK) >> ENET_EIR_PLR_SHIFT)
+#define ENET_BRD_EIR_PLR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_PLR_SHIFT))
+
+/*! @brief Set the PLR field to a new value. */
+#define ENET_WR_EIR_PLR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_PLR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_PLR(value)))
+#define ENET_BWR_EIR_PLR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_PLR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field UN[19] (W1C)
+ *
+ * Indicates the transmit FIFO became empty before the complete frame was
+ * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
+ * frame is discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_UN field. */
+#define ENET_RD_EIR_UN(base) ((ENET_EIR_REG(base) & ENET_EIR_UN_MASK) >> ENET_EIR_UN_SHIFT)
+#define ENET_BRD_EIR_UN(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_UN_SHIFT))
+
+/*! @brief Set the UN field to a new value. */
+#define ENET_WR_EIR_UN(base, value) (ENET_RMW_EIR(base, (ENET_EIR_UN_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_UN(value)))
+#define ENET_BWR_EIR_UN(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_UN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RL[20] (W1C)
+ *
+ * Indicates a collision occurred on each of 16 successive attempts to transmit
+ * the frame. The frame is discarded without being transmitted and transmission
+ * of the next frame commences. This error can only occur in half-duplex mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RL field. */
+#define ENET_RD_EIR_RL(base) ((ENET_EIR_REG(base) & ENET_EIR_RL_MASK) >> ENET_EIR_RL_SHIFT)
+#define ENET_BRD_EIR_RL(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RL_SHIFT))
+
+/*! @brief Set the RL field to a new value. */
+#define ENET_WR_EIR_RL(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RL_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RL(value)))
+#define ENET_BWR_EIR_RL(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field LC[21] (W1C)
+ *
+ * Indicates a collision occurred beyond the collision window (slot time) in
+ * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
+ * frame is discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_LC field. */
+#define ENET_RD_EIR_LC(base) ((ENET_EIR_REG(base) & ENET_EIR_LC_MASK) >> ENET_EIR_LC_SHIFT)
+#define ENET_BRD_EIR_LC(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_LC_SHIFT))
+
+/*! @brief Set the LC field to a new value. */
+#define ENET_WR_EIR_LC(base, value) (ENET_RMW_EIR(base, (ENET_EIR_LC_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_LC(value)))
+#define ENET_BWR_EIR_LC(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_LC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field EBERR[22] (W1C)
+ *
+ * Indicates a system bus error occurred when a uDMA transaction is underway.
+ * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
+ * MAC. When this occurs, software must ensure proper actions, possibly resetting
+ * the system, to resume normal operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_EBERR field. */
+#define ENET_RD_EIR_EBERR(base) ((ENET_EIR_REG(base) & ENET_EIR_EBERR_MASK) >> ENET_EIR_EBERR_SHIFT)
+#define ENET_BRD_EIR_EBERR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_EBERR_SHIFT))
+
+/*! @brief Set the EBERR field to a new value. */
+#define ENET_WR_EIR_EBERR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_EBERR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_EBERR(value)))
+#define ENET_BWR_EIR_EBERR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_EBERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field MII[23] (W1C)
+ *
+ * Indicates that the MII has completed the data transfer requested.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_MII field. */
+#define ENET_RD_EIR_MII(base) ((ENET_EIR_REG(base) & ENET_EIR_MII_MASK) >> ENET_EIR_MII_SHIFT)
+#define ENET_BRD_EIR_MII(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_MII_SHIFT))
+
+/*! @brief Set the MII field to a new value. */
+#define ENET_WR_EIR_MII(base, value) (ENET_RMW_EIR(base, (ENET_EIR_MII_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_MII(value)))
+#define ENET_BWR_EIR_MII(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_MII_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RXB[24] (W1C)
+ *
+ * Indicates a receive buffer descriptor is not the last in the frame has been
+ * updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RXB field. */
+#define ENET_RD_EIR_RXB(base) ((ENET_EIR_REG(base) & ENET_EIR_RXB_MASK) >> ENET_EIR_RXB_SHIFT)
+#define ENET_BRD_EIR_RXB(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXB_SHIFT))
+
+/*! @brief Set the RXB field to a new value. */
+#define ENET_WR_EIR_RXB(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RXB_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RXB(value)))
+#define ENET_BWR_EIR_RXB(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RXF[25] (W1C)
+ *
+ * Indicates a frame has been received and the last corresponding buffer
+ * descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RXF field. */
+#define ENET_RD_EIR_RXF(base) ((ENET_EIR_REG(base) & ENET_EIR_RXF_MASK) >> ENET_EIR_RXF_SHIFT)
+#define ENET_BRD_EIR_RXF(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXF_SHIFT))
+
+/*! @brief Set the RXF field to a new value. */
+#define ENET_WR_EIR_RXF(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RXF_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RXF(value)))
+#define ENET_BWR_EIR_RXF(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TXB[26] (W1C)
+ *
+ * Indicates a transmit buffer descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TXB field. */
+#define ENET_RD_EIR_TXB(base) ((ENET_EIR_REG(base) & ENET_EIR_TXB_MASK) >> ENET_EIR_TXB_SHIFT)
+#define ENET_BRD_EIR_TXB(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXB_SHIFT))
+
+/*! @brief Set the TXB field to a new value. */
+#define ENET_WR_EIR_TXB(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TXB_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TXB(value)))
+#define ENET_BWR_EIR_TXB(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TXF[27] (W1C)
+ *
+ * Indicates a frame has been transmitted and the last corresponding buffer
+ * descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TXF field. */
+#define ENET_RD_EIR_TXF(base) ((ENET_EIR_REG(base) & ENET_EIR_TXF_MASK) >> ENET_EIR_TXF_SHIFT)
+#define ENET_BRD_EIR_TXF(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXF_SHIFT))
+
+/*! @brief Set the TXF field to a new value. */
+#define ENET_WR_EIR_TXF(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TXF_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TXF(value)))
+#define ENET_BWR_EIR_TXF(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field GRA[28] (W1C)
+ *
+ * This interrupt is asserted after the transmitter is put into a pause state
+ * after completion of the frame currently being transmitted. See Graceful Transmit
+ * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
+ * asserted only when the TX transitions into the stopped state. If this bit is
+ * cleared by writing 1 and the TX is still stopped, the bit is not set again.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_GRA field. */
+#define ENET_RD_EIR_GRA(base) ((ENET_EIR_REG(base) & ENET_EIR_GRA_MASK) >> ENET_EIR_GRA_SHIFT)
+#define ENET_BRD_EIR_GRA(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_GRA_SHIFT))
+
+/*! @brief Set the GRA field to a new value. */
+#define ENET_WR_EIR_GRA(base, value) (ENET_RMW_EIR(base, (ENET_EIR_GRA_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_GRA(value)))
+#define ENET_BWR_EIR_GRA(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_GRA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field BABT[29] (W1C)
+ *
+ * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
+ * this condition is caused when a frame that is too long is placed into the
+ * transmit data buffer(s). Truncation does not occur.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_BABT field. */
+#define ENET_RD_EIR_BABT(base) ((ENET_EIR_REG(base) & ENET_EIR_BABT_MASK) >> ENET_EIR_BABT_SHIFT)
+#define ENET_BRD_EIR_BABT(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABT_SHIFT))
+
+/*! @brief Set the BABT field to a new value. */
+#define ENET_WR_EIR_BABT(base, value) (ENET_RMW_EIR(base, (ENET_EIR_BABT_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABR_MASK), ENET_EIR_BABT(value)))
+#define ENET_BWR_EIR_BABT(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field BABR[30] (W1C)
+ *
+ * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_BABR field. */
+#define ENET_RD_EIR_BABR(base) ((ENET_EIR_REG(base) & ENET_EIR_BABR_MASK) >> ENET_EIR_BABR_SHIFT)
+#define ENET_BRD_EIR_BABR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABR_SHIFT))
+
+/*! @brief Set the BABR field to a new value. */
+#define ENET_WR_EIR_BABR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_BABR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK), ENET_EIR_BABR(value)))
+#define ENET_BWR_EIR_BABR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_EIMR - Interrupt Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_EIMR - Interrupt Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * EIMR controls which interrupt events are allowed to generate actual
+ * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
+ * and EIMR registers are set, an interrupt is generated. The interrupt signal
+ * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
+ * 0 is written to the EIMR field.
+ */
+/*!
+ * @name Constants and macros for entire ENET_EIMR register
+ */
+/*@{*/
+#define ENET_RD_EIMR(base)       (ENET_EIMR_REG(base))
+#define ENET_WR_EIMR(base, value) (ENET_EIMR_REG(base) = (value))
+#define ENET_RMW_EIMR(base, mask, value) (ENET_WR_EIMR(base, (ENET_RD_EIMR(base) & ~(mask)) | (value)))
+#define ENET_SET_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) |  (value)))
+#define ENET_CLR_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) & ~(value)))
+#define ENET_TOG_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_EIMR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_TIMER field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TS_TIMER field. */
+#define ENET_RD_EIMR_TS_TIMER(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TS_TIMER_MASK) >> ENET_EIMR_TS_TIMER_SHIFT)
+#define ENET_BRD_EIMR_TS_TIMER(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_TIMER_SHIFT))
+
+/*! @brief Set the TS_TIMER field to a new value. */
+#define ENET_WR_EIMR_TS_TIMER(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TS_TIMER_MASK, ENET_EIMR_TS_TIMER(value)))
+#define ENET_BWR_EIMR_TS_TIMER(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_TIMER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TS_AVAIL field. */
+#define ENET_RD_EIMR_TS_AVAIL(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TS_AVAIL_MASK) >> ENET_EIMR_TS_AVAIL_SHIFT)
+#define ENET_BRD_EIMR_TS_AVAIL(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_AVAIL_SHIFT))
+
+/*! @brief Set the TS_AVAIL field to a new value. */
+#define ENET_WR_EIMR_TS_AVAIL(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TS_AVAIL_MASK, ENET_EIMR_TS_AVAIL(value)))
+#define ENET_BWR_EIMR_TS_AVAIL(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_AVAIL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field WAKEUP[17] (RW)
+ *
+ * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR WAKEUP field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_WAKEUP field. */
+#define ENET_RD_EIMR_WAKEUP(base) ((ENET_EIMR_REG(base) & ENET_EIMR_WAKEUP_MASK) >> ENET_EIMR_WAKEUP_SHIFT)
+#define ENET_BRD_EIMR_WAKEUP(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_WAKEUP_SHIFT))
+
+/*! @brief Set the WAKEUP field to a new value. */
+#define ENET_WR_EIMR_WAKEUP(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_WAKEUP_MASK, ENET_EIMR_WAKEUP(value)))
+#define ENET_BWR_EIMR_WAKEUP(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_WAKEUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field PLR[18] (RW)
+ *
+ * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR PLR field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_PLR field. */
+#define ENET_RD_EIMR_PLR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_PLR_MASK) >> ENET_EIMR_PLR_SHIFT)
+#define ENET_BRD_EIMR_PLR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_PLR_SHIFT))
+
+/*! @brief Set the PLR field to a new value. */
+#define ENET_WR_EIMR_PLR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_PLR_MASK, ENET_EIMR_PLR(value)))
+#define ENET_BWR_EIMR_PLR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_PLR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field UN[19] (RW)
+ *
+ * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR UN field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_UN field. */
+#define ENET_RD_EIMR_UN(base) ((ENET_EIMR_REG(base) & ENET_EIMR_UN_MASK) >> ENET_EIMR_UN_SHIFT)
+#define ENET_BRD_EIMR_UN(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_UN_SHIFT))
+
+/*! @brief Set the UN field to a new value. */
+#define ENET_WR_EIMR_UN(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_UN_MASK, ENET_EIMR_UN(value)))
+#define ENET_BWR_EIMR_UN(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_UN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RL[20] (RW)
+ *
+ * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR RL field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RL field. */
+#define ENET_RD_EIMR_RL(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RL_MASK) >> ENET_EIMR_RL_SHIFT)
+#define ENET_BRD_EIMR_RL(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RL_SHIFT))
+
+/*! @brief Set the RL field to a new value. */
+#define ENET_WR_EIMR_RL(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RL_MASK, ENET_EIMR_RL(value)))
+#define ENET_BWR_EIMR_RL(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field LC[21] (RW)
+ *
+ * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR LC field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_LC field. */
+#define ENET_RD_EIMR_LC(base) ((ENET_EIMR_REG(base) & ENET_EIMR_LC_MASK) >> ENET_EIMR_LC_SHIFT)
+#define ENET_BRD_EIMR_LC(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_LC_SHIFT))
+
+/*! @brief Set the LC field to a new value. */
+#define ENET_WR_EIMR_LC(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_LC_MASK, ENET_EIMR_LC(value)))
+#define ENET_BWR_EIMR_LC(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_LC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field EBERR[22] (RW)
+ *
+ * Corresponds to interrupt source EIR[EBERR] and determines whether an
+ * interrupt condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR EBERR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_EBERR field. */
+#define ENET_RD_EIMR_EBERR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_EBERR_MASK) >> ENET_EIMR_EBERR_SHIFT)
+#define ENET_BRD_EIMR_EBERR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_EBERR_SHIFT))
+
+/*! @brief Set the EBERR field to a new value. */
+#define ENET_WR_EIMR_EBERR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_EBERR_MASK, ENET_EIMR_EBERR(value)))
+#define ENET_BWR_EIMR_EBERR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_EBERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field MII[23] (RW)
+ *
+ * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR MII field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_MII field. */
+#define ENET_RD_EIMR_MII(base) ((ENET_EIMR_REG(base) & ENET_EIMR_MII_MASK) >> ENET_EIMR_MII_SHIFT)
+#define ENET_BRD_EIMR_MII(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_MII_SHIFT))
+
+/*! @brief Set the MII field to a new value. */
+#define ENET_WR_EIMR_MII(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_MII_MASK, ENET_EIMR_MII(value)))
+#define ENET_BWR_EIMR_MII(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_MII_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RXB[24] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXB field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RXB field. */
+#define ENET_RD_EIMR_RXB(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RXB_MASK) >> ENET_EIMR_RXB_SHIFT)
+#define ENET_BRD_EIMR_RXB(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXB_SHIFT))
+
+/*! @brief Set the RXB field to a new value. */
+#define ENET_WR_EIMR_RXB(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RXB_MASK, ENET_EIMR_RXB(value)))
+#define ENET_BWR_EIMR_RXB(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RXF[25] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RXF field. */
+#define ENET_RD_EIMR_RXF(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RXF_MASK) >> ENET_EIMR_RXF_SHIFT)
+#define ENET_BRD_EIMR_RXF(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXF_SHIFT))
+
+/*! @brief Set the RXF field to a new value. */
+#define ENET_WR_EIMR_RXF(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RXF_MASK, ENET_EIMR_RXF(value)))
+#define ENET_BWR_EIMR_RXF(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TXB[26] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TXB field. */
+#define ENET_RD_EIMR_TXB(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TXB_MASK) >> ENET_EIMR_TXB_SHIFT)
+#define ENET_BRD_EIMR_TXB(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXB_SHIFT))
+
+/*! @brief Set the TXB field to a new value. */
+#define ENET_WR_EIMR_TXB(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TXB_MASK, ENET_EIMR_TXB(value)))
+#define ENET_BWR_EIMR_TXB(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TXF[27] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TXF field. */
+#define ENET_RD_EIMR_TXF(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TXF_MASK) >> ENET_EIMR_TXF_SHIFT)
+#define ENET_BRD_EIMR_TXF(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXF_SHIFT))
+
+/*! @brief Set the TXF field to a new value. */
+#define ENET_WR_EIMR_TXF(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TXF_MASK, ENET_EIMR_TXF(value)))
+#define ENET_BWR_EIMR_TXF(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field GRA[28] (RW)
+ *
+ * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR GRA field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_GRA field. */
+#define ENET_RD_EIMR_GRA(base) ((ENET_EIMR_REG(base) & ENET_EIMR_GRA_MASK) >> ENET_EIMR_GRA_SHIFT)
+#define ENET_BRD_EIMR_GRA(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_GRA_SHIFT))
+
+/*! @brief Set the GRA field to a new value. */
+#define ENET_WR_EIMR_GRA(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_GRA_MASK, ENET_EIMR_GRA(value)))
+#define ENET_BWR_EIMR_GRA(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_GRA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field BABT[29] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABT
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_BABT field. */
+#define ENET_RD_EIMR_BABT(base) ((ENET_EIMR_REG(base) & ENET_EIMR_BABT_MASK) >> ENET_EIMR_BABT_SHIFT)
+#define ENET_BRD_EIMR_BABT(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABT_SHIFT))
+
+/*! @brief Set the BABT field to a new value. */
+#define ENET_WR_EIMR_BABT(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_BABT_MASK, ENET_EIMR_BABT(value)))
+#define ENET_BWR_EIMR_BABT(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field BABR[30] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_BABR field. */
+#define ENET_RD_EIMR_BABR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_BABR_MASK) >> ENET_EIMR_BABR_SHIFT)
+#define ENET_BRD_EIMR_BABR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABR_SHIFT))
+
+/*! @brief Set the BABR field to a new value. */
+#define ENET_WR_EIMR_BABR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_BABR_MASK, ENET_EIMR_BABR(value)))
+#define ENET_BWR_EIMR_BABR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RDAR - Receive Descriptor Active Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RDAR - Receive Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDAR is a command register, written by the user, to indicate that the receive
+ * descriptor ring has been updated, that is, that the driver produced empty
+ * receive buffers with the empty bit set.
+ */
+/*!
+ * @name Constants and macros for entire ENET_RDAR register
+ */
+/*@{*/
+#define ENET_RD_RDAR(base)       (ENET_RDAR_REG(base))
+#define ENET_WR_RDAR(base, value) (ENET_RDAR_REG(base) = (value))
+#define ENET_RMW_RDAR(base, mask, value) (ENET_WR_RDAR(base, (ENET_RD_RDAR(base) & ~(mask)) | (value)))
+#define ENET_SET_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) |  (value)))
+#define ENET_CLR_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) & ~(value)))
+#define ENET_TOG_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDAR, field RDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This field is cleared by the MAC device when no additional empty
+ * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
+ * from set to cleared or when ECR[RESET] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RDAR_RDAR field. */
+#define ENET_RD_RDAR_RDAR(base) ((ENET_RDAR_REG(base) & ENET_RDAR_RDAR_MASK) >> ENET_RDAR_RDAR_SHIFT)
+#define ENET_BRD_RDAR_RDAR(base) (BITBAND_ACCESS32(&ENET_RDAR_REG(base), ENET_RDAR_RDAR_SHIFT))
+
+/*! @brief Set the RDAR field to a new value. */
+#define ENET_WR_RDAR_RDAR(base, value) (ENET_RMW_RDAR(base, ENET_RDAR_RDAR_MASK, ENET_RDAR_RDAR(value)))
+#define ENET_BWR_RDAR_RDAR(base, value) (BITBAND_ACCESS32(&ENET_RDAR_REG(base), ENET_RDAR_RDAR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TDAR - Transmit Descriptor Active Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TDAR - Transmit Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The TDAR is a command register that the user writes to indicate that the
+ * transmit descriptor ring has been updated, that is, that transmit buffers have
+ * been produced by the driver with the ready bit set in the buffer descriptor. The
+ * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
+ * cleared, or when ECR[RESET] is set.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TDAR register
+ */
+/*@{*/
+#define ENET_RD_TDAR(base)       (ENET_TDAR_REG(base))
+#define ENET_WR_TDAR(base, value) (ENET_TDAR_REG(base) = (value))
+#define ENET_RMW_TDAR(base, mask, value) (ENET_WR_TDAR(base, (ENET_RD_TDAR(base) & ~(mask)) | (value)))
+#define ENET_SET_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) |  (value)))
+#define ENET_CLR_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) & ~(value)))
+#define ENET_TOG_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDAR, field TDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This bit is cleared by the MAC device when no additional ready descriptors
+ * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
+ * set to cleared or when ECR[RESET] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TDAR_TDAR field. */
+#define ENET_RD_TDAR_TDAR(base) ((ENET_TDAR_REG(base) & ENET_TDAR_TDAR_MASK) >> ENET_TDAR_TDAR_SHIFT)
+#define ENET_BRD_TDAR_TDAR(base) (BITBAND_ACCESS32(&ENET_TDAR_REG(base), ENET_TDAR_TDAR_SHIFT))
+
+/*! @brief Set the TDAR field to a new value. */
+#define ENET_WR_TDAR_TDAR(base, value) (ENET_RMW_TDAR(base, ENET_TDAR_TDAR_MASK, ENET_TDAR_TDAR(value)))
+#define ENET_BWR_TDAR_TDAR(base, value) (BITBAND_ACCESS32(&ENET_TDAR_REG(base), ENET_TDAR_TDAR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ECR - Ethernet Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ECR - Ethernet Control Register (RW)
+ *
+ * Reset value: 0xF0000000U
+ *
+ * ECR is a read/write user register, though hardware may also alter fields in
+ * this register. It controls many of the high level features of the Ethernet MAC,
+ * including legacy FEC support through the EN1588 field.
+ */
+/*!
+ * @name Constants and macros for entire ENET_ECR register
+ */
+/*@{*/
+#define ENET_RD_ECR(base)        (ENET_ECR_REG(base))
+#define ENET_WR_ECR(base, value) (ENET_ECR_REG(base) = (value))
+#define ENET_RMW_ECR(base, mask, value) (ENET_WR_ECR(base, (ENET_RD_ECR(base) & ~(mask)) | (value)))
+#define ENET_SET_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) |  (value)))
+#define ENET_CLR_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) & ~(value)))
+#define ENET_TOG_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ECR bitfields
+ */
+
+/*!
+ * @name Register ENET_ECR, field RESET[0] (RW)
+ *
+ * When this field is set, it clears the ETHEREN field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_RESET field. */
+#define ENET_RD_ECR_RESET(base) ((ENET_ECR_REG(base) & ENET_ECR_RESET_MASK) >> ENET_ECR_RESET_SHIFT)
+#define ENET_BRD_ECR_RESET(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_RESET_SHIFT))
+
+/*! @brief Set the RESET field to a new value. */
+#define ENET_WR_ECR_RESET(base, value) (ENET_RMW_ECR(base, ENET_ECR_RESET_MASK, ENET_ECR_RESET(value)))
+#define ENET_BWR_ECR_RESET(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_RESET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field ETHEREN[1] (RW)
+ *
+ * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
+ * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
+ * descriptor, and FIFO control logic are reset, including the buffer descriptor and
+ * FIFO pointers. Hardware clears this field under the following conditions: RESET
+ * is set by software An error condition causes the EBERR field to set. ETHEREN
+ * must be set at the very last step during ENET
+ * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
+ * is cleared to 0 by software then then next time ETHEREN is set, the EIR
+ * interrupts must cleared to 0 due to previous pending interrupts.
+ *
+ * Values:
+ * - 0b0 - Reception immediately stops and transmission stops after a bad CRC is
+ *     appended to any currently transmitted frame.
+ * - 0b1 - MAC is enabled, and reception and transmission are possible.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_ETHEREN field. */
+#define ENET_RD_ECR_ETHEREN(base) ((ENET_ECR_REG(base) & ENET_ECR_ETHEREN_MASK) >> ENET_ECR_ETHEREN_SHIFT)
+#define ENET_BRD_ECR_ETHEREN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_ETHEREN_SHIFT))
+
+/*! @brief Set the ETHEREN field to a new value. */
+#define ENET_WR_ECR_ETHEREN(base, value) (ENET_RMW_ECR(base, ENET_ECR_ETHEREN_MASK, ENET_ECR_ETHEREN(value)))
+#define ENET_BWR_ECR_ETHEREN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_ETHEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field MAGICEN[2] (RW)
+ *
+ * Enables/disables magic packet detection. MAGICEN is relevant only if the
+ * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
+ * sleep mode and magic packet detection.
+ *
+ * Values:
+ * - 0b0 - Magic detection logic disabled.
+ * - 0b1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a
+ *     frame is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_MAGICEN field. */
+#define ENET_RD_ECR_MAGICEN(base) ((ENET_ECR_REG(base) & ENET_ECR_MAGICEN_MASK) >> ENET_ECR_MAGICEN_SHIFT)
+#define ENET_BRD_ECR_MAGICEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_MAGICEN_SHIFT))
+
+/*! @brief Set the MAGICEN field to a new value. */
+#define ENET_WR_ECR_MAGICEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_MAGICEN_MASK, ENET_ECR_MAGICEN(value)))
+#define ENET_BWR_ECR_MAGICEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_MAGICEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field SLEEP[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operating mode.
+ * - 0b1 - Sleep mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_SLEEP field. */
+#define ENET_RD_ECR_SLEEP(base) ((ENET_ECR_REG(base) & ENET_ECR_SLEEP_MASK) >> ENET_ECR_SLEEP_SHIFT)
+#define ENET_BRD_ECR_SLEEP(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_SLEEP_SHIFT))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define ENET_WR_ECR_SLEEP(base, value) (ENET_RMW_ECR(base, ENET_ECR_SLEEP_MASK, ENET_ECR_SLEEP(value)))
+#define ENET_BWR_ECR_SLEEP(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_SLEEP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field EN1588[4] (RW)
+ *
+ * Enables enhanced functionality of the MAC.
+ *
+ * Values:
+ * - 0b0 - Legacy FEC buffer descriptors and functions enabled.
+ * - 0b1 - Enhanced frame time-stamping functions enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_EN1588 field. */
+#define ENET_RD_ECR_EN1588(base) ((ENET_ECR_REG(base) & ENET_ECR_EN1588_MASK) >> ENET_ECR_EN1588_SHIFT)
+#define ENET_BRD_ECR_EN1588(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_EN1588_SHIFT))
+
+/*! @brief Set the EN1588 field to a new value. */
+#define ENET_WR_ECR_EN1588(base, value) (ENET_RMW_ECR(base, ENET_ECR_EN1588_MASK, ENET_ECR_EN1588(value)))
+#define ENET_BWR_ECR_EN1588(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_EN1588_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field DBGEN[6] (RW)
+ *
+ * Enables the MAC to enter hardware freeze mode when the device enters debug
+ * mode.
+ *
+ * Values:
+ * - 0b0 - MAC continues operation in debug mode.
+ * - 0b1 - MAC enters hardware freeze mode when the processor is in debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_DBGEN field. */
+#define ENET_RD_ECR_DBGEN(base) ((ENET_ECR_REG(base) & ENET_ECR_DBGEN_MASK) >> ENET_ECR_DBGEN_SHIFT)
+#define ENET_BRD_ECR_DBGEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBGEN_SHIFT))
+
+/*! @brief Set the DBGEN field to a new value. */
+#define ENET_WR_ECR_DBGEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_DBGEN_MASK, ENET_ECR_DBGEN(value)))
+#define ENET_BWR_ECR_DBGEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field STOPEN[7] (RW)
+ *
+ * Controls device behavior in doze mode. In doze mode, if this field is set
+ * then all the clocks of the ENET assembly are disabled, except the RMII /MII
+ * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
+ * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
+ * can still wake the system after receiving a magic packet in stop mode. MAGICEN
+ * must be set prior to entering sleep/stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_STOPEN field. */
+#define ENET_RD_ECR_STOPEN(base) ((ENET_ECR_REG(base) & ENET_ECR_STOPEN_MASK) >> ENET_ECR_STOPEN_SHIFT)
+#define ENET_BRD_ECR_STOPEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_STOPEN_SHIFT))
+
+/*! @brief Set the STOPEN field to a new value. */
+#define ENET_WR_ECR_STOPEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_STOPEN_MASK, ENET_ECR_STOPEN(value)))
+#define ENET_BWR_ECR_STOPEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_STOPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field DBSWP[8] (RW)
+ *
+ * Swaps the byte locations of the buffer descriptors. This field must be
+ * written to 1 after reset.
+ *
+ * Values:
+ * - 0b0 - The buffer descriptor bytes are not swapped to support big-endian
+ *     devices.
+ * - 0b1 - The buffer descriptor bytes are swapped to support little-endian
+ *     devices.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_DBSWP field. */
+#define ENET_RD_ECR_DBSWP(base) ((ENET_ECR_REG(base) & ENET_ECR_DBSWP_MASK) >> ENET_ECR_DBSWP_SHIFT)
+#define ENET_BRD_ECR_DBSWP(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBSWP_SHIFT))
+
+/*! @brief Set the DBSWP field to a new value. */
+#define ENET_WR_ECR_DBSWP(base, value) (ENET_RMW_ECR(base, ENET_ECR_DBSWP_MASK, ENET_ECR_DBSWP(value)))
+#define ENET_BWR_ECR_DBSWP(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBSWP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MMFR - MII Management Frame Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MMFR - MII Management Frame Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Writing to MMFR triggers a management frame transaction to the PHY device
+ * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
+ * during a write to MMFR, an MII frame is generated with the data previously written
+ * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
+ * MSCR is currently zero. If the MMFR register is written while frame generation is
+ * in progress, the frame contents are altered. Software must use the EIR[MII]
+ * interrupt indication to avoid writing to the MMFR register while frame
+ * generation is in progress.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MMFR register
+ */
+/*@{*/
+#define ENET_RD_MMFR(base)       (ENET_MMFR_REG(base))
+#define ENET_WR_MMFR(base, value) (ENET_MMFR_REG(base) = (value))
+#define ENET_RMW_MMFR(base, mask, value) (ENET_WR_MMFR(base, (ENET_RD_MMFR(base) & ~(mask)) | (value)))
+#define ENET_SET_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) |  (value)))
+#define ENET_CLR_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) & ~(value)))
+#define ENET_TOG_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MMFR bitfields
+ */
+
+/*!
+ * @name Register ENET_MMFR, field DATA[15:0] (RW)
+ *
+ * This is the field for data to be written to or read from the PHY register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_DATA field. */
+#define ENET_RD_MMFR_DATA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT)
+#define ENET_BRD_MMFR_DATA(base) (ENET_RD_MMFR_DATA(base))
+
+/*! @brief Set the DATA field to a new value. */
+#define ENET_WR_MMFR_DATA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_DATA_MASK, ENET_MMFR_DATA(value)))
+#define ENET_BWR_MMFR_DATA(base, value) (ENET_WR_MMFR_DATA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field TA[17:16] (RW)
+ *
+ * This field must be programmed to 10 to generate a valid MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_TA field. */
+#define ENET_RD_MMFR_TA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_TA_MASK) >> ENET_MMFR_TA_SHIFT)
+#define ENET_BRD_MMFR_TA(base) (ENET_RD_MMFR_TA(base))
+
+/*! @brief Set the TA field to a new value. */
+#define ENET_WR_MMFR_TA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_TA_MASK, ENET_MMFR_TA(value)))
+#define ENET_BWR_MMFR_TA(base, value) (ENET_WR_MMFR_TA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field RA[22:18] (RW)
+ *
+ * Specifies one of up to 32 registers within the specified PHY device.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_RA field. */
+#define ENET_RD_MMFR_RA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_RA_MASK) >> ENET_MMFR_RA_SHIFT)
+#define ENET_BRD_MMFR_RA(base) (ENET_RD_MMFR_RA(base))
+
+/*! @brief Set the RA field to a new value. */
+#define ENET_WR_MMFR_RA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_RA_MASK, ENET_MMFR_RA(value)))
+#define ENET_BWR_MMFR_RA(base, value) (ENET_WR_MMFR_RA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field PA[27:23] (RW)
+ *
+ * Specifies one of up to 32 attached PHY devices.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_PA field. */
+#define ENET_RD_MMFR_PA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_PA_MASK) >> ENET_MMFR_PA_SHIFT)
+#define ENET_BRD_MMFR_PA(base) (ENET_RD_MMFR_PA(base))
+
+/*! @brief Set the PA field to a new value. */
+#define ENET_WR_MMFR_PA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_PA_MASK, ENET_MMFR_PA(value)))
+#define ENET_BWR_MMFR_PA(base, value) (ENET_WR_MMFR_PA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field OP[29:28] (RW)
+ *
+ * Determines the frame operation.
+ *
+ * Values:
+ * - 0b00 - Write frame operation, but not MII compliant.
+ * - 0b01 - Write frame operation for a valid MII management frame.
+ * - 0b10 - Read frame operation for a valid MII management frame.
+ * - 0b11 - Read frame operation, but not MII compliant.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_OP field. */
+#define ENET_RD_MMFR_OP(base) ((ENET_MMFR_REG(base) & ENET_MMFR_OP_MASK) >> ENET_MMFR_OP_SHIFT)
+#define ENET_BRD_MMFR_OP(base) (ENET_RD_MMFR_OP(base))
+
+/*! @brief Set the OP field to a new value. */
+#define ENET_WR_MMFR_OP(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_OP_MASK, ENET_MMFR_OP(value)))
+#define ENET_BWR_MMFR_OP(base, value) (ENET_WR_MMFR_OP(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field ST[31:30] (RW)
+ *
+ * These fields must be programmed to 01 for a valid MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_ST field. */
+#define ENET_RD_MMFR_ST(base) ((ENET_MMFR_REG(base) & ENET_MMFR_ST_MASK) >> ENET_MMFR_ST_SHIFT)
+#define ENET_BRD_MMFR_ST(base) (ENET_RD_MMFR_ST(base))
+
+/*! @brief Set the ST field to a new value. */
+#define ENET_WR_MMFR_ST(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_ST_MASK, ENET_MMFR_ST(value)))
+#define ENET_BWR_MMFR_ST(base, value) (ENET_WR_MMFR_ST(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MSCR - MII Speed Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MSCR - MII Speed Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * MSCR provides control of the MII clock (MDC pin) frequency and allows a
+ * preamble drop on the MII management frame. The MII_SPEED field must be programmed
+ * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
+ * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
+ * a non-zero value to source a read or write management frame. After the
+ * management frame is complete, the MSCR register may optionally be cleared to turn
+ * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
+ * changes during operation. This change takes effect following a rising or falling
+ * edge of MDC. If the internal module clock is 25 MHz, programming this register
+ * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
+ * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
+ * MII_SPEED as a function of internal module clock frequency. Programming Examples
+ * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
+ * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
+ * 0xD 2.36 MHz
+ */
+/*!
+ * @name Constants and macros for entire ENET_MSCR register
+ */
+/*@{*/
+#define ENET_RD_MSCR(base)       (ENET_MSCR_REG(base))
+#define ENET_WR_MSCR(base, value) (ENET_MSCR_REG(base) = (value))
+#define ENET_RMW_MSCR(base, mask, value) (ENET_WR_MSCR(base, (ENET_RD_MSCR(base) & ~(mask)) | (value)))
+#define ENET_SET_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) |  (value)))
+#define ENET_CLR_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) & ~(value)))
+#define ENET_TOG_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MSCR bitfields
+ */
+
+/*!
+ * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
+ *
+ * Controls the frequency of the MII management interface clock (MDC) relative
+ * to the internal module clock. A value of 0 in this field turns off MDC and
+ * leaves it in low voltage state. Any non-zero value results in the MDC frequency
+ * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_MII_SPEED field. */
+#define ENET_RD_MSCR_MII_SPEED(base) ((ENET_MSCR_REG(base) & ENET_MSCR_MII_SPEED_MASK) >> ENET_MSCR_MII_SPEED_SHIFT)
+#define ENET_BRD_MSCR_MII_SPEED(base) (ENET_RD_MSCR_MII_SPEED(base))
+
+/*! @brief Set the MII_SPEED field to a new value. */
+#define ENET_WR_MSCR_MII_SPEED(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_MII_SPEED_MASK, ENET_MSCR_MII_SPEED(value)))
+#define ENET_BWR_MSCR_MII_SPEED(base, value) (ENET_WR_MSCR_MII_SPEED(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
+ *
+ * Enables/disables prepending a preamble to the MII management frame. The MII
+ * standard allows the preamble to be dropped if the attached PHY devices do not
+ * require it.
+ *
+ * Values:
+ * - 0b0 - Preamble enabled.
+ * - 0b1 - Preamble (32 ones) is not prepended to the MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_DIS_PRE field. */
+#define ENET_RD_MSCR_DIS_PRE(base) ((ENET_MSCR_REG(base) & ENET_MSCR_DIS_PRE_MASK) >> ENET_MSCR_DIS_PRE_SHIFT)
+#define ENET_BRD_MSCR_DIS_PRE(base) (BITBAND_ACCESS32(&ENET_MSCR_REG(base), ENET_MSCR_DIS_PRE_SHIFT))
+
+/*! @brief Set the DIS_PRE field to a new value. */
+#define ENET_WR_MSCR_DIS_PRE(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_DIS_PRE_MASK, ENET_MSCR_DIS_PRE(value)))
+#define ENET_BWR_MSCR_DIS_PRE(base, value) (BITBAND_ACCESS32(&ENET_MSCR_REG(base), ENET_MSCR_DIS_PRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
+ *
+ * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
+ * output. Depending on the host bus frequency, the setting may need to be
+ * increased.
+ *
+ * Values:
+ * - 0b000 - 1 internal module clock cycle
+ * - 0b001 - 2 internal module clock cycles
+ * - 0b010 - 3 internal module clock cycles
+ * - 0b111 - 8 internal module clock cycles
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_HOLDTIME field. */
+#define ENET_RD_MSCR_HOLDTIME(base) ((ENET_MSCR_REG(base) & ENET_MSCR_HOLDTIME_MASK) >> ENET_MSCR_HOLDTIME_SHIFT)
+#define ENET_BRD_MSCR_HOLDTIME(base) (ENET_RD_MSCR_HOLDTIME(base))
+
+/*! @brief Set the HOLDTIME field to a new value. */
+#define ENET_WR_MSCR_HOLDTIME(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_HOLDTIME_MASK, ENET_MSCR_HOLDTIME(value)))
+#define ENET_BWR_MSCR_HOLDTIME(base, value) (ENET_WR_MSCR_HOLDTIME(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MIBC - MIB Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MIBC - MIB Control Register (RW)
+ *
+ * Reset value: 0xC0000000U
+ *
+ * MIBC is a read/write register controlling and observing the state of the MIB
+ * block. Access this register to disable the MIB block operation or clear the
+ * MIB counters. The MIB_DIS field resets to 1.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MIBC register
+ */
+/*@{*/
+#define ENET_RD_MIBC(base)       (ENET_MIBC_REG(base))
+#define ENET_WR_MIBC(base, value) (ENET_MIBC_REG(base) = (value))
+#define ENET_RMW_MIBC(base, mask, value) (ENET_WR_MIBC(base, (ENET_RD_MIBC(base) & ~(mask)) | (value)))
+#define ENET_SET_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) |  (value)))
+#define ENET_CLR_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) & ~(value)))
+#define ENET_TOG_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MIBC bitfields
+ */
+
+/*!
+ * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
+ *
+ * If set, all statistics counters are reset to 0. This field is not
+ * self-clearing. To clear the MIB counters set and then clear the field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_CLEAR field. */
+#define ENET_RD_MIBC_MIB_CLEAR(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_CLEAR_MASK) >> ENET_MIBC_MIB_CLEAR_SHIFT)
+#define ENET_BRD_MIBC_MIB_CLEAR(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_CLEAR_SHIFT))
+
+/*! @brief Set the MIB_CLEAR field to a new value. */
+#define ENET_WR_MIBC_MIB_CLEAR(base, value) (ENET_RMW_MIBC(base, ENET_MIBC_MIB_CLEAR_MASK, ENET_MIBC_MIB_CLEAR(value)))
+#define ENET_BWR_MIBC_MIB_CLEAR(base, value) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_CLEAR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
+ *
+ * If this status field is set, the MIB block is not currently updating any MIB
+ * counters.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_IDLE field. */
+#define ENET_RD_MIBC_MIB_IDLE(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_IDLE_MASK) >> ENET_MIBC_MIB_IDLE_SHIFT)
+#define ENET_BRD_MIBC_MIB_IDLE(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
+ *
+ * If this control field is set, the MIB logic halts and does not update any MIB
+ * counters.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_DIS field. */
+#define ENET_RD_MIBC_MIB_DIS(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_DIS_MASK) >> ENET_MIBC_MIB_DIS_SHIFT)
+#define ENET_BRD_MIBC_MIB_DIS(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_DIS_SHIFT))
+
+/*! @brief Set the MIB_DIS field to a new value. */
+#define ENET_WR_MIBC_MIB_DIS(base, value) (ENET_RMW_MIBC(base, ENET_MIBC_MIB_DIS_MASK, ENET_MIBC_MIB_DIS(value)))
+#define ENET_BWR_MIBC_MIB_DIS(base, value) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_DIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RCR - Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RCR - Receive Control Register (RW)
+ *
+ * Reset value: 0x05EE0001U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RCR register
+ */
+/*@{*/
+#define ENET_RD_RCR(base)        (ENET_RCR_REG(base))
+#define ENET_WR_RCR(base, value) (ENET_RCR_REG(base) = (value))
+#define ENET_RMW_RCR(base, mask, value) (ENET_WR_RCR(base, (ENET_RD_RCR(base) & ~(mask)) | (value)))
+#define ENET_SET_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) |  (value)))
+#define ENET_CLR_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) & ~(value)))
+#define ENET_TOG_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RCR bitfields
+ */
+
+/*!
+ * @name Register ENET_RCR, field LOOP[0] (RW)
+ *
+ * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
+ * RMII_MODE must be written to 0.
+ *
+ * Values:
+ * - 0b0 - Loopback disabled.
+ * - 0b1 - Transmitted frames are looped back internal to the device and
+ *     transmit MII output signals are not asserted. DRT must be cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_LOOP field. */
+#define ENET_RD_RCR_LOOP(base) ((ENET_RCR_REG(base) & ENET_RCR_LOOP_MASK) >> ENET_RCR_LOOP_SHIFT)
+#define ENET_BRD_RCR_LOOP(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_LOOP_SHIFT))
+
+/*! @brief Set the LOOP field to a new value. */
+#define ENET_WR_RCR_LOOP(base, value) (ENET_RMW_RCR(base, ENET_RCR_LOOP_MASK, ENET_RCR_LOOP(value)))
+#define ENET_BWR_RCR_LOOP(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_LOOP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field DRT[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Receive path operates independently of transmit. Used for full-duplex
+ *     or to monitor transmit activity in half-duplex mode.
+ * - 0b1 - Disable reception of frames while transmitting. Normally used for
+ *     half-duplex mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_DRT field. */
+#define ENET_RD_RCR_DRT(base) ((ENET_RCR_REG(base) & ENET_RCR_DRT_MASK) >> ENET_RCR_DRT_SHIFT)
+#define ENET_BRD_RCR_DRT(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_DRT_SHIFT))
+
+/*! @brief Set the DRT field to a new value. */
+#define ENET_WR_RCR_DRT(base, value) (ENET_RMW_RCR(base, ENET_RCR_DRT_MASK, ENET_RCR_DRT(value)))
+#define ENET_BWR_RCR_DRT(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_DRT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field MII_MODE[2] (RW)
+ *
+ * This field must always be set.
+ *
+ * Values:
+ * - 0b0 - Reserved.
+ * - 0b1 - MII or RMII mode, as indicated by the RMII_MODE field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_MII_MODE field. */
+#define ENET_RD_RCR_MII_MODE(base) ((ENET_RCR_REG(base) & ENET_RCR_MII_MODE_MASK) >> ENET_RCR_MII_MODE_SHIFT)
+#define ENET_BRD_RCR_MII_MODE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_MII_MODE_SHIFT))
+
+/*! @brief Set the MII_MODE field to a new value. */
+#define ENET_WR_RCR_MII_MODE(base, value) (ENET_RMW_RCR(base, ENET_RCR_MII_MODE_MASK, ENET_RCR_MII_MODE(value)))
+#define ENET_BWR_RCR_MII_MODE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_MII_MODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PROM[3] (RW)
+ *
+ * All frames are accepted regardless of address matching.
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PROM field. */
+#define ENET_RD_RCR_PROM(base) ((ENET_RCR_REG(base) & ENET_RCR_PROM_MASK) >> ENET_RCR_PROM_SHIFT)
+#define ENET_BRD_RCR_PROM(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PROM_SHIFT))
+
+/*! @brief Set the PROM field to a new value. */
+#define ENET_WR_RCR_PROM(base, value) (ENET_RMW_RCR(base, ENET_RCR_PROM_MASK, ENET_RCR_PROM(value)))
+#define ENET_BWR_RCR_PROM(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PROM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field BC_REJ[4] (RW)
+ *
+ * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
+ * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
+ * broadcast DA are accepted and the MISS (M) is set in the receive buffer
+ * descriptor.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_BC_REJ field. */
+#define ENET_RD_RCR_BC_REJ(base) ((ENET_RCR_REG(base) & ENET_RCR_BC_REJ_MASK) >> ENET_RCR_BC_REJ_SHIFT)
+#define ENET_BRD_RCR_BC_REJ(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_BC_REJ_SHIFT))
+
+/*! @brief Set the BC_REJ field to a new value. */
+#define ENET_WR_RCR_BC_REJ(base, value) (ENET_RMW_RCR(base, ENET_RCR_BC_REJ_MASK, ENET_RCR_BC_REJ(value)))
+#define ENET_BWR_RCR_BC_REJ(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_BC_REJ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field FCE[5] (RW)
+ *
+ * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
+ * transmitter stops transmitting data frames for a given duration.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_FCE field. */
+#define ENET_RD_RCR_FCE(base) ((ENET_RCR_REG(base) & ENET_RCR_FCE_MASK) >> ENET_RCR_FCE_SHIFT)
+#define ENET_BRD_RCR_FCE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_FCE_SHIFT))
+
+/*! @brief Set the FCE field to a new value. */
+#define ENET_WR_RCR_FCE(base, value) (ENET_RMW_RCR(base, ENET_RCR_FCE_MASK, ENET_RCR_FCE(value)))
+#define ENET_BWR_RCR_FCE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_FCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field RMII_MODE[8] (RW)
+ *
+ * Specifies whether the MAC is configured for MII mode or RMII operation .
+ *
+ * Values:
+ * - 0b0 - MAC configured for MII mode.
+ * - 0b1 - MAC configured for RMII operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_RMII_MODE field. */
+#define ENET_RD_RCR_RMII_MODE(base) ((ENET_RCR_REG(base) & ENET_RCR_RMII_MODE_MASK) >> ENET_RCR_RMII_MODE_SHIFT)
+#define ENET_BRD_RCR_RMII_MODE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_MODE_SHIFT))
+
+/*! @brief Set the RMII_MODE field to a new value. */
+#define ENET_WR_RCR_RMII_MODE(base, value) (ENET_RMW_RCR(base, ENET_RCR_RMII_MODE_MASK, ENET_RCR_RMII_MODE(value)))
+#define ENET_BWR_RCR_RMII_MODE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_MODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field RMII_10T[9] (RW)
+ *
+ * Enables 10-Mbps mode of the RMII .
+ *
+ * Values:
+ * - 0b0 - 100 Mbps operation.
+ * - 0b1 - 10 Mbps operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_RMII_10T field. */
+#define ENET_RD_RCR_RMII_10T(base) ((ENET_RCR_REG(base) & ENET_RCR_RMII_10T_MASK) >> ENET_RCR_RMII_10T_SHIFT)
+#define ENET_BRD_RCR_RMII_10T(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_10T_SHIFT))
+
+/*! @brief Set the RMII_10T field to a new value. */
+#define ENET_WR_RCR_RMII_10T(base, value) (ENET_RMW_RCR(base, ENET_RCR_RMII_10T_MASK, ENET_RCR_RMII_10T(value)))
+#define ENET_BWR_RCR_RMII_10T(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_10T_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PADEN[12] (RW)
+ *
+ * Specifies whether the MAC removes padding from received frames.
+ *
+ * Values:
+ * - 0b0 - No padding is removed on receive by the MAC.
+ * - 0b1 - Padding is removed from received frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PADEN field. */
+#define ENET_RD_RCR_PADEN(base) ((ENET_RCR_REG(base) & ENET_RCR_PADEN_MASK) >> ENET_RCR_PADEN_SHIFT)
+#define ENET_BRD_RCR_PADEN(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PADEN_SHIFT))
+
+/*! @brief Set the PADEN field to a new value. */
+#define ENET_WR_RCR_PADEN(base, value) (ENET_RMW_RCR(base, ENET_RCR_PADEN_MASK, ENET_RCR_PADEN(value)))
+#define ENET_BWR_RCR_PADEN(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PADEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PAUFWD[13] (RW)
+ *
+ * Specifies whether pause frames are terminated or forwarded.
+ *
+ * Values:
+ * - 0b0 - Pause frames are terminated and discarded in the MAC.
+ * - 0b1 - Pause frames are forwarded to the user application.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PAUFWD field. */
+#define ENET_RD_RCR_PAUFWD(base) ((ENET_RCR_REG(base) & ENET_RCR_PAUFWD_MASK) >> ENET_RCR_PAUFWD_SHIFT)
+#define ENET_BRD_RCR_PAUFWD(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PAUFWD_SHIFT))
+
+/*! @brief Set the PAUFWD field to a new value. */
+#define ENET_WR_RCR_PAUFWD(base, value) (ENET_RMW_RCR(base, ENET_RCR_PAUFWD_MASK, ENET_RCR_PAUFWD(value)))
+#define ENET_BWR_RCR_PAUFWD(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PAUFWD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field CRCFWD[14] (RW)
+ *
+ * Specifies whether the CRC field of received frames is transmitted or
+ * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
+ * field is checked and always terminated and removed.
+ *
+ * Values:
+ * - 0b0 - The CRC field of received frames is transmitted to the user
+ *     application.
+ * - 0b1 - The CRC field is stripped from the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_CRCFWD field. */
+#define ENET_RD_RCR_CRCFWD(base) ((ENET_RCR_REG(base) & ENET_RCR_CRCFWD_MASK) >> ENET_RCR_CRCFWD_SHIFT)
+#define ENET_BRD_RCR_CRCFWD(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CRCFWD_SHIFT))
+
+/*! @brief Set the CRCFWD field to a new value. */
+#define ENET_WR_RCR_CRCFWD(base, value) (ENET_RMW_RCR(base, ENET_RCR_CRCFWD_MASK, ENET_RCR_CRCFWD(value)))
+#define ENET_BWR_RCR_CRCFWD(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CRCFWD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field CFEN[15] (RW)
+ *
+ * Enables/disables the MAC control frame.
+ *
+ * Values:
+ * - 0b0 - MAC control frames with any opcode other than 0x0001 (pause frame)
+ *     are accepted and forwarded to the client interface.
+ * - 0b1 - MAC control frames with any opcode other than 0x0001 (pause frame)
+ *     are silently discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_CFEN field. */
+#define ENET_RD_RCR_CFEN(base) ((ENET_RCR_REG(base) & ENET_RCR_CFEN_MASK) >> ENET_RCR_CFEN_SHIFT)
+#define ENET_BRD_RCR_CFEN(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CFEN_SHIFT))
+
+/*! @brief Set the CFEN field to a new value. */
+#define ENET_WR_RCR_CFEN(base, value) (ENET_RMW_RCR(base, ENET_RCR_CFEN_MASK, ENET_RCR_CFEN(value)))
+#define ENET_BWR_RCR_CFEN(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
+ *
+ * Resets to decimal 1518. Length is measured starting at DA and includes the
+ * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
+ * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
+ * to occur and set the LG field in the end of frame receive buffer descriptor.
+ * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
+ * supported.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_MAX_FL field. */
+#define ENET_RD_RCR_MAX_FL(base) ((ENET_RCR_REG(base) & ENET_RCR_MAX_FL_MASK) >> ENET_RCR_MAX_FL_SHIFT)
+#define ENET_BRD_RCR_MAX_FL(base) (ENET_RD_RCR_MAX_FL(base))
+
+/*! @brief Set the MAX_FL field to a new value. */
+#define ENET_WR_RCR_MAX_FL(base, value) (ENET_RMW_RCR(base, ENET_RCR_MAX_FL_MASK, ENET_RCR_MAX_FL(value)))
+#define ENET_BWR_RCR_MAX_FL(base, value) (ENET_WR_RCR_MAX_FL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field NLC[30] (RW)
+ *
+ * Enables/disables a payload length check.
+ *
+ * Values:
+ * - 0b0 - The payload length check is disabled.
+ * - 0b1 - The core checks the frame's payload length with the frame length/type
+ *     field. Errors are indicated in the EIR[PLC] field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_NLC field. */
+#define ENET_RD_RCR_NLC(base) ((ENET_RCR_REG(base) & ENET_RCR_NLC_MASK) >> ENET_RCR_NLC_SHIFT)
+#define ENET_BRD_RCR_NLC(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_NLC_SHIFT))
+
+/*! @brief Set the NLC field to a new value. */
+#define ENET_WR_RCR_NLC(base, value) (ENET_RMW_RCR(base, ENET_RCR_NLC_MASK, ENET_RCR_NLC(value)))
+#define ENET_BWR_RCR_NLC(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_NLC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field GRS[31] (RO)
+ *
+ * Read-only status indicating that the MAC receive datapath is stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_GRS field. */
+#define ENET_RD_RCR_GRS(base) ((ENET_RCR_REG(base) & ENET_RCR_GRS_MASK) >> ENET_RCR_GRS_SHIFT)
+#define ENET_BRD_RCR_GRS(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_GRS_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCR - Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCR - Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR is read/write and configures the transmit block. This register is cleared
+ * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCR register
+ */
+/*@{*/
+#define ENET_RD_TCR(base)        (ENET_TCR_REG(base))
+#define ENET_WR_TCR(base, value) (ENET_TCR_REG(base) = (value))
+#define ENET_RMW_TCR(base, mask, value) (ENET_WR_TCR(base, (ENET_RD_TCR(base) & ~(mask)) | (value)))
+#define ENET_SET_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) |  (value)))
+#define ENET_CLR_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) & ~(value)))
+#define ENET_TOG_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TCR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCR, field GTS[0] (RW)
+ *
+ * When this field is set, MAC stops transmission after any frame currently
+ * transmitted is complete and EIR[GRA] is set. If frame transmission is not
+ * currently underway, the GRA interrupt is asserted immediately. After transmission
+ * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
+ * transmitted. If an early collision occurs during transmission when GTS is set,
+ * transmission stops after the collision. The frame is transmitted again after GTS is
+ * cleared. There may be old frames in the transmit FIFO that transmit when GTS
+ * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_GTS field. */
+#define ENET_RD_TCR_GTS(base) ((ENET_TCR_REG(base) & ENET_TCR_GTS_MASK) >> ENET_TCR_GTS_SHIFT)
+#define ENET_BRD_TCR_GTS(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_GTS_SHIFT))
+
+/*! @brief Set the GTS field to a new value. */
+#define ENET_WR_TCR_GTS(base, value) (ENET_RMW_TCR(base, ENET_TCR_GTS_MASK, ENET_TCR_GTS(value)))
+#define ENET_BWR_TCR_GTS(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_GTS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field FDEN[2] (RW)
+ *
+ * If this field is set, frames transmit independent of carrier sense and
+ * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_FDEN field. */
+#define ENET_RD_TCR_FDEN(base) ((ENET_TCR_REG(base) & ENET_TCR_FDEN_MASK) >> ENET_TCR_FDEN_SHIFT)
+#define ENET_BRD_TCR_FDEN(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_FDEN_SHIFT))
+
+/*! @brief Set the FDEN field to a new value. */
+#define ENET_WR_TCR_FDEN(base, value) (ENET_RMW_TCR(base, ENET_TCR_FDEN_MASK, ENET_TCR_FDEN(value)))
+#define ENET_BWR_TCR_FDEN(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_FDEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
+ *
+ * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
+ * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
+ * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
+ * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
+ * the MAC may continue transmitting a MAC control PAUSE frame.
+ *
+ * Values:
+ * - 0b0 - No PAUSE frame transmitted.
+ * - 0b1 - The MAC stops transmission of data frames after the current
+ *     transmission is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_TFC_PAUSE field. */
+#define ENET_RD_TCR_TFC_PAUSE(base) ((ENET_TCR_REG(base) & ENET_TCR_TFC_PAUSE_MASK) >> ENET_TCR_TFC_PAUSE_SHIFT)
+#define ENET_BRD_TCR_TFC_PAUSE(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_TFC_PAUSE_SHIFT))
+
+/*! @brief Set the TFC_PAUSE field to a new value. */
+#define ENET_WR_TCR_TFC_PAUSE(base, value) (ENET_RMW_TCR(base, ENET_TCR_TFC_PAUSE_MASK, ENET_TCR_TFC_PAUSE(value)))
+#define ENET_BWR_TCR_TFC_PAUSE(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_TFC_PAUSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
+ *
+ * This status field is set when a full-duplex flow control pause frame is
+ * received and the transmitter pauses for the duration defined in this pause frame.
+ * This field automatically clears when the pause duration is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_RFC_PAUSE field. */
+#define ENET_RD_TCR_RFC_PAUSE(base) ((ENET_TCR_REG(base) & ENET_TCR_RFC_PAUSE_MASK) >> ENET_TCR_RFC_PAUSE_SHIFT)
+#define ENET_BRD_TCR_RFC_PAUSE(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_RFC_PAUSE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
+ *
+ * If ADDINS is set, indicates the MAC address that overwrites the source MAC
+ * address.
+ *
+ * Values:
+ * - 0b000 - Node MAC address programmed on PADDR1/2 registers.
+ * - 0b100 - Reserved.
+ * - 0b101 - Reserved.
+ * - 0b110 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_ADDSEL field. */
+#define ENET_RD_TCR_ADDSEL(base) ((ENET_TCR_REG(base) & ENET_TCR_ADDSEL_MASK) >> ENET_TCR_ADDSEL_SHIFT)
+#define ENET_BRD_TCR_ADDSEL(base) (ENET_RD_TCR_ADDSEL(base))
+
+/*! @brief Set the ADDSEL field to a new value. */
+#define ENET_WR_TCR_ADDSEL(base, value) (ENET_RMW_TCR(base, ENET_TCR_ADDSEL_MASK, ENET_TCR_ADDSEL(value)))
+#define ENET_BWR_TCR_ADDSEL(base, value) (ENET_WR_TCR_ADDSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field ADDINS[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The source MAC address is not modified by the MAC.
+ * - 0b1 - The MAC overwrites the source MAC address with the programmed MAC
+ *     address according to ADDSEL.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_ADDINS field. */
+#define ENET_RD_TCR_ADDINS(base) ((ENET_TCR_REG(base) & ENET_TCR_ADDINS_MASK) >> ENET_TCR_ADDINS_SHIFT)
+#define ENET_BRD_TCR_ADDINS(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_ADDINS_SHIFT))
+
+/*! @brief Set the ADDINS field to a new value. */
+#define ENET_WR_TCR_ADDINS(base, value) (ENET_RMW_TCR(base, ENET_TCR_ADDINS_MASK, ENET_TCR_ADDINS(value)))
+#define ENET_BWR_TCR_ADDINS(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_ADDINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field CRCFWD[9] (RW)
+ *
+ * Values:
+ * - 0b0 - TxBD[TC] controls whether the frame has a CRC from the application.
+ * - 0b1 - The transmitter does not append any CRC to transmitted frames, as it
+ *     is expecting a frame with CRC from the application.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_CRCFWD field. */
+#define ENET_RD_TCR_CRCFWD(base) ((ENET_TCR_REG(base) & ENET_TCR_CRCFWD_MASK) >> ENET_TCR_CRCFWD_SHIFT)
+#define ENET_BRD_TCR_CRCFWD(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_CRCFWD_SHIFT))
+
+/*! @brief Set the CRCFWD field to a new value. */
+#define ENET_WR_TCR_CRCFWD(base, value) (ENET_RMW_TCR(base, ENET_TCR_CRCFWD_MASK, ENET_TCR_CRCFWD(value)))
+#define ENET_BWR_TCR_CRCFWD(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_CRCFWD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_PALR - Physical Address Lower Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_PALR - Physical Address Lower Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
+ * in the address recognition process to compare with the destination address
+ * (DA) field of receive frames with an individual DA. In addition, this register
+ * is used in bytes 0 through 3 of the six-byte source address field when
+ * transmitting PAUSE frames. This register is not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_PALR register
+ */
+/*@{*/
+#define ENET_RD_PALR(base)       (ENET_PALR_REG(base))
+#define ENET_WR_PALR(base, value) (ENET_PALR_REG(base) = (value))
+#define ENET_RMW_PALR(base, mask, value) (ENET_WR_PALR(base, (ENET_RD_PALR(base) & ~(mask)) | (value)))
+#define ENET_SET_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) |  (value)))
+#define ENET_CLR_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) & ~(value)))
+#define ENET_TOG_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_PAUR - Physical Address Upper Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_PAUR - Physical Address Upper Register (RW)
+ *
+ * Reset value: 0x00008808U
+ *
+ * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
+ * the address recognition process to compare with the destination address (DA)
+ * field of receive frames with an individual DA. In addition, this register is
+ * used in bytes 4 and 5 of the six-byte source address field when transmitting
+ * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
+ * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
+ * you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_PAUR register
+ */
+/*@{*/
+#define ENET_RD_PAUR(base)       (ENET_PAUR_REG(base))
+#define ENET_WR_PAUR(base, value) (ENET_PAUR_REG(base) = (value))
+#define ENET_RMW_PAUR(base, mask, value) (ENET_WR_PAUR(base, (ENET_RD_PAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) |  (value)))
+#define ENET_CLR_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) & ~(value)))
+#define ENET_TOG_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_PAUR bitfields
+ */
+
+/*!
+ * @name Register ENET_PAUR, field TYPE[15:0] (RO)
+ *
+ * These fields have a constant value of 0x8808.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_PAUR_TYPE field. */
+#define ENET_RD_PAUR_TYPE(base) ((ENET_PAUR_REG(base) & ENET_PAUR_TYPE_MASK) >> ENET_PAUR_TYPE_SHIFT)
+#define ENET_BRD_PAUR_TYPE(base) (ENET_RD_PAUR_TYPE(base))
+/*@}*/
+
+/*!
+ * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
+ *
+ * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
+ * for exact match, and the source address field in PAUSE frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_PAUR_PADDR2 field. */
+#define ENET_RD_PAUR_PADDR2(base) ((ENET_PAUR_REG(base) & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT)
+#define ENET_BRD_PAUR_PADDR2(base) (ENET_RD_PAUR_PADDR2(base))
+
+/*! @brief Set the PADDR2 field to a new value. */
+#define ENET_WR_PAUR_PADDR2(base, value) (ENET_RMW_PAUR(base, ENET_PAUR_PADDR2_MASK, ENET_PAUR_PADDR2(value)))
+#define ENET_BWR_PAUR_PADDR2(base, value) (ENET_WR_PAUR_PADDR2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_OPD - Opcode/Pause Duration Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_OPD - Opcode/Pause Duration Register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * OPD is read/write accessible. This register contains the 16-bit opcode and
+ * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
+ * field is a constant value, 0x0001. When another node detects a PAUSE frame,
+ * that node pauses transmission for the duration specified in the pause duration
+ * field. The lower 16 bits of this register are not reset and you must initialize
+ * it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_OPD register
+ */
+/*@{*/
+#define ENET_RD_OPD(base)        (ENET_OPD_REG(base))
+#define ENET_WR_OPD(base, value) (ENET_OPD_REG(base) = (value))
+#define ENET_RMW_OPD(base, mask, value) (ENET_WR_OPD(base, (ENET_RD_OPD(base) & ~(mask)) | (value)))
+#define ENET_SET_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) |  (value)))
+#define ENET_CLR_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) & ~(value)))
+#define ENET_TOG_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_OPD bitfields
+ */
+
+/*!
+ * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
+ *
+ * Pause duration field used in PAUSE frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_OPD_PAUSE_DUR field. */
+#define ENET_RD_OPD_PAUSE_DUR(base) ((ENET_OPD_REG(base) & ENET_OPD_PAUSE_DUR_MASK) >> ENET_OPD_PAUSE_DUR_SHIFT)
+#define ENET_BRD_OPD_PAUSE_DUR(base) (ENET_RD_OPD_PAUSE_DUR(base))
+
+/*! @brief Set the PAUSE_DUR field to a new value. */
+#define ENET_WR_OPD_PAUSE_DUR(base, value) (ENET_RMW_OPD(base, ENET_OPD_PAUSE_DUR_MASK, ENET_OPD_PAUSE_DUR(value)))
+#define ENET_BWR_OPD_PAUSE_DUR(base, value) (ENET_WR_OPD_PAUSE_DUR(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_OPD, field OPCODE[31:16] (RO)
+ *
+ * These fields have a constant value of 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_OPD_OPCODE field. */
+#define ENET_RD_OPD_OPCODE(base) ((ENET_OPD_REG(base) & ENET_OPD_OPCODE_MASK) >> ENET_OPD_OPCODE_SHIFT)
+#define ENET_BRD_OPD_OPCODE(base) (ENET_RD_OPD_OPCODE(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IAUR - Descriptor Individual Upper Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IAUR - Descriptor Individual Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the destination address (DA) field of receive frames with an individual
+ * DA. This register is not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IAUR register
+ */
+/*@{*/
+#define ENET_RD_IAUR(base)       (ENET_IAUR_REG(base))
+#define ENET_WR_IAUR(base, value) (ENET_IAUR_REG(base) = (value))
+#define ENET_RMW_IAUR(base, mask, value) (ENET_WR_IAUR(base, (ENET_RD_IAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) |  (value)))
+#define ENET_CLR_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) & ~(value)))
+#define ENET_TOG_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IALR - Descriptor Individual Lower Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IALR - Descriptor Individual Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IALR contains the lower 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the DA field of receive frames with an individual DA. This register is
+ * not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IALR register
+ */
+/*@{*/
+#define ENET_RD_IALR(base)       (ENET_IALR_REG(base))
+#define ENET_WR_IALR(base, value) (ENET_IALR_REG(base) = (value))
+#define ENET_RMW_IALR(base, mask, value) (ENET_WR_IALR(base, (ENET_RD_IALR(base) & ~(mask)) | (value)))
+#define ENET_SET_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) |  (value)))
+#define ENET_CLR_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) & ~(value)))
+#define ENET_TOG_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_GAUR - Descriptor Group Upper Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_GAUR - Descriptor Group Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+/*!
+ * @name Constants and macros for entire ENET_GAUR register
+ */
+/*@{*/
+#define ENET_RD_GAUR(base)       (ENET_GAUR_REG(base))
+#define ENET_WR_GAUR(base, value) (ENET_GAUR_REG(base) = (value))
+#define ENET_RMW_GAUR(base, mask, value) (ENET_WR_GAUR(base, (ENET_RD_GAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) |  (value)))
+#define ENET_CLR_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) & ~(value)))
+#define ENET_TOG_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_GALR - Descriptor Group Lower Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_GALR - Descriptor Group Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GALR contains the lower 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+/*!
+ * @name Constants and macros for entire ENET_GALR register
+ */
+/*@{*/
+#define ENET_RD_GALR(base)       (ENET_GALR_REG(base))
+#define ENET_WR_GALR(base, value) (ENET_GALR_REG(base) = (value))
+#define ENET_RMW_GALR(base, mask, value) (ENET_WR_GALR(base, (ENET_RD_GALR(base) & ~(mask)) | (value)))
+#define ENET_SET_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) |  (value)))
+#define ENET_CLR_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) & ~(value)))
+#define ENET_TOG_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TFWR - Transmit FIFO Watermark Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TFWR - Transmit FIFO Watermark Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
+ * in the transmit FIFO before transmission of a frame can begin. This allows you
+ * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
+ * latency (TFWR = 11) due to contention for the system bus. Setting the
+ * watermark to a high value minimizes the risk of transmit FIFO underrun due to
+ * contention for the system bus. The byte counts associated with the TFWR field may need
+ * to be modified to match a given system requirement. For example, worst case
+ * bus access latency by the transmit data DMA channel. When the FIFO level
+ * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
+ * transmit control logic starts frame transmission even before the end-of-frame is
+ * available in the FIFO (cut-through operation). If a complete frame has a size
+ * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
+ * to the line. To enable store and forward on the Transmit path, set STR_FWD to
+ * '1'. In this case, the MAC starts to transmit data only when a complete frame
+ * is stored in the Transmit FIFO.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TFWR register
+ */
+/*@{*/
+#define ENET_RD_TFWR(base)       (ENET_TFWR_REG(base))
+#define ENET_WR_TFWR(base, value) (ENET_TFWR_REG(base) = (value))
+#define ENET_RMW_TFWR(base, mask, value) (ENET_WR_TFWR(base, (ENET_RD_TFWR(base) & ~(mask)) | (value)))
+#define ENET_SET_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) |  (value)))
+#define ENET_CLR_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) & ~(value)))
+#define ENET_TOG_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TFWR bitfields
+ */
+
+/*!
+ * @name Register ENET_TFWR, field TFWR[5:0] (RW)
+ *
+ * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
+ * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
+ * begins. If a frame with less than the threshold is written, it is still sent
+ * independently of this threshold setting. The threshold is relevant only if the
+ * frame is larger than the threshold given. This chip may not support the maximum
+ * number of bytes written shown below. See the chip-specific information for the
+ * ENET module for this value.
+ *
+ * Values:
+ * - 0b000000 - 64 bytes written.
+ * - 0b000001 - 64 bytes written.
+ * - 0b000010 - 128 bytes written.
+ * - 0b000011 - 192 bytes written.
+ * - 0b111110 - 3968 bytes written.
+ * - 0b111111 - 4032 bytes written.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TFWR_TFWR field. */
+#define ENET_RD_TFWR_TFWR(base) ((ENET_TFWR_REG(base) & ENET_TFWR_TFWR_MASK) >> ENET_TFWR_TFWR_SHIFT)
+#define ENET_BRD_TFWR_TFWR(base) (ENET_RD_TFWR_TFWR(base))
+
+/*! @brief Set the TFWR field to a new value. */
+#define ENET_WR_TFWR_TFWR(base, value) (ENET_RMW_TFWR(base, ENET_TFWR_TFWR_MASK, ENET_TFWR_TFWR(value)))
+#define ENET_BWR_TFWR_TFWR(base, value) (ENET_WR_TFWR_TFWR(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TFWR, field STRFWD[8] (RW)
+ *
+ * Values:
+ * - 0b0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
+ * - 0b1 - Enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TFWR_STRFWD field. */
+#define ENET_RD_TFWR_STRFWD(base) ((ENET_TFWR_REG(base) & ENET_TFWR_STRFWD_MASK) >> ENET_TFWR_STRFWD_SHIFT)
+#define ENET_BRD_TFWR_STRFWD(base) (BITBAND_ACCESS32(&ENET_TFWR_REG(base), ENET_TFWR_STRFWD_SHIFT))
+
+/*! @brief Set the STRFWD field to a new value. */
+#define ENET_WR_TFWR_STRFWD(base, value) (ENET_RMW_TFWR(base, ENET_TFWR_STRFWD_MASK, ENET_TFWR_STRFWD(value)))
+#define ENET_BWR_TFWR_STRFWD(base, value) (BITBAND_ACCESS32(&ENET_TFWR_REG(base), ENET_TFWR_STRFWD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RDSR - Receive Descriptor Ring Start Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RDSR - Receive Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDSR points to the beginning of the circular receive buffer descriptor queue
+ * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
+ * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
+ * by 16. This register must be initialized prior to operation
+ */
+/*!
+ * @name Constants and macros for entire ENET_RDSR register
+ */
+/*@{*/
+#define ENET_RD_RDSR(base)       (ENET_RDSR_REG(base))
+#define ENET_WR_RDSR(base, value) (ENET_RDSR_REG(base) = (value))
+#define ENET_RMW_RDSR(base, mask, value) (ENET_WR_RDSR(base, (ENET_RD_RDSR(base) & ~(mask)) | (value)))
+#define ENET_SET_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) |  (value)))
+#define ENET_CLR_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) & ~(value)))
+#define ENET_TOG_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the receive buffer descriptor queue.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RDSR_R_DES_START field. */
+#define ENET_RD_RDSR_R_DES_START(base) ((ENET_RDSR_REG(base) & ENET_RDSR_R_DES_START_MASK) >> ENET_RDSR_R_DES_START_SHIFT)
+#define ENET_BRD_RDSR_R_DES_START(base) (ENET_RD_RDSR_R_DES_START(base))
+
+/*! @brief Set the R_DES_START field to a new value. */
+#define ENET_WR_RDSR_R_DES_START(base, value) (ENET_RMW_RDSR(base, ENET_RDSR_R_DES_START_MASK, ENET_RDSR_R_DES_START(value)))
+#define ENET_BWR_RDSR_R_DES_START(base, value) (ENET_WR_RDSR_R_DES_START(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TDSR provides a pointer to the beginning of the circular transmit buffer
+ * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
+ * must be zero); however, it is recommended to be 128-bit aligned, that is,
+ * evenly divisible by 16. This register must be initialized prior to operation.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TDSR register
+ */
+/*@{*/
+#define ENET_RD_TDSR(base)       (ENET_TDSR_REG(base))
+#define ENET_WR_TDSR(base, value) (ENET_TDSR_REG(base) = (value))
+#define ENET_RMW_TDSR(base, mask, value) (ENET_WR_TDSR(base, (ENET_RD_TDSR(base) & ~(mask)) | (value)))
+#define ENET_SET_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) |  (value)))
+#define ENET_CLR_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) & ~(value)))
+#define ENET_TOG_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the transmit buffer descriptor queue.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TDSR_X_DES_START field. */
+#define ENET_RD_TDSR_X_DES_START(base) ((ENET_TDSR_REG(base) & ENET_TDSR_X_DES_START_MASK) >> ENET_TDSR_X_DES_START_SHIFT)
+#define ENET_BRD_TDSR_X_DES_START(base) (ENET_RD_TDSR_X_DES_START(base))
+
+/*! @brief Set the X_DES_START field to a new value. */
+#define ENET_WR_TDSR_X_DES_START(base, value) (ENET_RMW_TDSR(base, ENET_TDSR_X_DES_START_MASK, ENET_TDSR_X_DES_START(value)))
+#define ENET_BWR_TDSR_X_DES_START(base, value) (ENET_WR_TDSR_X_DES_START(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MRBR - Maximum Receive Buffer Size Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MRBR - Maximum Receive Buffer Size Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MRBR is a user-programmable register that dictates the maximum size of
+ * all receive buffers. This value should take into consideration that the receive
+ * CRC is always written into the last receive buffer. To allow one maximum size
+ * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
+ * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
+ * set to zero by the device. To minimize bus usage (descriptor fetches), set
+ * MRBR greater than or equal to 256 bytes. This register must be initialized
+ * before operation.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MRBR register
+ */
+/*@{*/
+#define ENET_RD_MRBR(base)       (ENET_MRBR_REG(base))
+#define ENET_WR_MRBR(base, value) (ENET_MRBR_REG(base) = (value))
+#define ENET_RMW_MRBR(base, mask, value) (ENET_WR_MRBR(base, (ENET_RD_MRBR(base) & ~(mask)) | (value)))
+#define ENET_SET_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) |  (value)))
+#define ENET_CLR_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) & ~(value)))
+#define ENET_TOG_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MRBR bitfields
+ */
+
+/*!
+ * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
+ *
+ * Receive buffer size in bytes.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field. */
+#define ENET_RD_MRBR_R_BUF_SIZE(base) ((ENET_MRBR_REG(base) & ENET_MRBR_R_BUF_SIZE_MASK) >> ENET_MRBR_R_BUF_SIZE_SHIFT)
+#define ENET_BRD_MRBR_R_BUF_SIZE(base) (ENET_RD_MRBR_R_BUF_SIZE(base))
+
+/*! @brief Set the R_BUF_SIZE field to a new value. */
+#define ENET_WR_MRBR_R_BUF_SIZE(base, value) (ENET_RMW_MRBR(base, ENET_MRBR_R_BUF_SIZE_MASK, ENET_MRBR_R_BUF_SIZE(value)))
+#define ENET_BWR_MRBR_R_BUF_SIZE(base, value) (ENET_WR_MRBR_R_BUF_SIZE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RSFL - Receive FIFO Section Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RSFL - Receive FIFO Section Full Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RSFL register
+ */
+/*@{*/
+#define ENET_RD_RSFL(base)       (ENET_RSFL_REG(base))
+#define ENET_WR_RSFL(base, value) (ENET_RSFL_REG(base) = (value))
+#define ENET_RMW_RSFL(base, mask, value) (ENET_WR_RSFL(base, (ENET_RD_RSFL(base) & ~(mask)) | (value)))
+#define ENET_SET_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) |  (value)))
+#define ENET_CLR_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) & ~(value)))
+#define ENET_TOG_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RSFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
+ * this field to enable store and forward on the RX FIFO. When programming a value
+ * greater than 0 (cut-through operation), it must be greater than
+ * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
+ * in the Receive FIFO (cut-through operation).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field. */
+#define ENET_RD_RSFL_RX_SECTION_FULL(base) ((ENET_RSFL_REG(base) & ENET_RSFL_RX_SECTION_FULL_MASK) >> ENET_RSFL_RX_SECTION_FULL_SHIFT)
+#define ENET_BRD_RSFL_RX_SECTION_FULL(base) (ENET_RD_RSFL_RX_SECTION_FULL(base))
+
+/*! @brief Set the RX_SECTION_FULL field to a new value. */
+#define ENET_WR_RSFL_RX_SECTION_FULL(base, value) (ENET_RMW_RSFL(base, ENET_RSFL_RX_SECTION_FULL_MASK, ENET_RSFL_RX_SECTION_FULL(value)))
+#define ENET_BWR_RSFL_RX_SECTION_FULL(base, value) (ENET_WR_RSFL_RX_SECTION_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RSEM - Receive FIFO Section Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RSEM register
+ */
+/*@{*/
+#define ENET_RD_RSEM(base)       (ENET_RSEM_REG(base))
+#define ENET_WR_RSEM(base, value) (ENET_RSEM_REG(base) = (value))
+#define ENET_RMW_RSEM(base, mask, value) (ENET_WR_RSEM(base, (ENET_RD_RSEM(base) & ~(mask)) | (value)))
+#define ENET_SET_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) |  (value)))
+#define ENET_CLR_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) & ~(value)))
+#define ENET_TOG_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
+ * FIFO has reached this level, a pause frame will be issued. A value of 0
+ * disables automatic pause frame generation. When the FIFO level goes below the value
+ * programmed in this field, an XON pause frame is issued to indicate the FIFO
+ * congestion is cleared to the remote Ethernet client. The section-empty
+ * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field. */
+#define ENET_RD_RSEM_RX_SECTION_EMPTY(base) ((ENET_RSEM_REG(base) & ENET_RSEM_RX_SECTION_EMPTY_MASK) >> ENET_RSEM_RX_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_RSEM_RX_SECTION_EMPTY(base) (ENET_RD_RSEM_RX_SECTION_EMPTY(base))
+
+/*! @brief Set the RX_SECTION_EMPTY field to a new value. */
+#define ENET_WR_RSEM_RX_SECTION_EMPTY(base, value) (ENET_RMW_RSEM(base, ENET_RSEM_RX_SECTION_EMPTY_MASK, ENET_RSEM_RX_SECTION_EMPTY(value)))
+#define ENET_BWR_RSEM_RX_SECTION_EMPTY(base, value) (ENET_WR_RSEM_RX_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
+ *
+ * Defines number of frames in the receive FIFO, independent of its size, that
+ * can be accepted. If the limit is reached, reception will continue normally,
+ * however a pause frame will be triggered to indicate a possible congestion to the
+ * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
+ * frame generation
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field. */
+#define ENET_RD_RSEM_STAT_SECTION_EMPTY(base) ((ENET_RSEM_REG(base) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) >> ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_RSEM_STAT_SECTION_EMPTY(base) (ENET_RD_RSEM_STAT_SECTION_EMPTY(base))
+
+/*! @brief Set the STAT_SECTION_EMPTY field to a new value. */
+#define ENET_WR_RSEM_STAT_SECTION_EMPTY(base, value) (ENET_RMW_RSEM(base, ENET_RSEM_STAT_SECTION_EMPTY_MASK, ENET_RSEM_STAT_SECTION_EMPTY(value)))
+#define ENET_BWR_RSEM_STAT_SECTION_EMPTY(base, value) (ENET_WR_RSEM_STAT_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RAEM - Receive FIFO Almost Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RAEM register
+ */
+/*@{*/
+#define ENET_RD_RAEM(base)       (ENET_RAEM_REG(base))
+#define ENET_WR_RAEM(base, value) (ENET_RAEM_REG(base) = (value))
+#define ENET_RMW_RAEM(base, mask, value) (ENET_WR_RAEM(base, (ENET_RD_RAEM(base) & ~(mask)) | (value)))
+#define ENET_SET_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) |  (value)))
+#define ENET_CLR_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) & ~(value)))
+#define ENET_TOG_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field and the end-of-frame has
+ * not been received for the frame yet, the core receive read control stops FIFO
+ * read (and subsequently stops transferring data to the MAC client
+ * application). It continues to deliver the frame, if again more data than the threshold or
+ * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field. */
+#define ENET_RD_RAEM_RX_ALMOST_EMPTY(base) ((ENET_RAEM_REG(base) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) >> ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)
+#define ENET_BRD_RAEM_RX_ALMOST_EMPTY(base) (ENET_RD_RAEM_RX_ALMOST_EMPTY(base))
+
+/*! @brief Set the RX_ALMOST_EMPTY field to a new value. */
+#define ENET_WR_RAEM_RX_ALMOST_EMPTY(base, value) (ENET_RMW_RAEM(base, ENET_RAEM_RX_ALMOST_EMPTY_MASK, ENET_RAEM_RX_ALMOST_EMPTY(value)))
+#define ENET_BWR_RAEM_RX_ALMOST_EMPTY(base, value) (ENET_WR_RAEM_RX_ALMOST_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RAFL - Receive FIFO Almost Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RAFL register
+ */
+/*@{*/
+#define ENET_RD_RAFL(base)       (ENET_RAFL_REG(base))
+#define ENET_WR_RAFL(base, value) (ENET_RAFL_REG(base) = (value))
+#define ENET_RMW_RAFL(base, mask, value) (ENET_WR_RAFL(base, (ENET_RD_RAFL(base) & ~(mask)) | (value)))
+#define ENET_SET_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) |  (value)))
+#define ENET_CLR_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) & ~(value)))
+#define ENET_TOG_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
+ * truncates the received frame to avoid FIFO overflow. The corresponding error
+ * status will be set when the frame is delivered to the application. A minimum
+ * value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field. */
+#define ENET_RD_RAFL_RX_ALMOST_FULL(base) ((ENET_RAFL_REG(base) & ENET_RAFL_RX_ALMOST_FULL_MASK) >> ENET_RAFL_RX_ALMOST_FULL_SHIFT)
+#define ENET_BRD_RAFL_RX_ALMOST_FULL(base) (ENET_RD_RAFL_RX_ALMOST_FULL(base))
+
+/*! @brief Set the RX_ALMOST_FULL field to a new value. */
+#define ENET_WR_RAFL_RX_ALMOST_FULL(base, value) (ENET_RMW_RAFL(base, ENET_RAFL_RX_ALMOST_FULL_MASK, ENET_RAFL_RX_ALMOST_FULL(value)))
+#define ENET_BWR_RAFL_RX_ALMOST_FULL(base, value) (ENET_WR_RAFL_RX_ALMOST_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TSEM - Transmit FIFO Section Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TSEM register
+ */
+/*@{*/
+#define ENET_RD_TSEM(base)       (ENET_TSEM_REG(base))
+#define ENET_WR_TSEM(base, value) (ENET_TSEM_REG(base) = (value))
+#define ENET_RMW_TSEM(base, mask, value) (ENET_WR_TSEM(base, (ENET_RD_TSEM(base) & ~(mask)) | (value)))
+#define ENET_SET_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) |  (value)))
+#define ENET_CLR_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) & ~(value)))
+#define ENET_TOG_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field. */
+#define ENET_RD_TSEM_TX_SECTION_EMPTY(base) ((ENET_TSEM_REG(base) & ENET_TSEM_TX_SECTION_EMPTY_MASK) >> ENET_TSEM_TX_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_TSEM_TX_SECTION_EMPTY(base) (ENET_RD_TSEM_TX_SECTION_EMPTY(base))
+
+/*! @brief Set the TX_SECTION_EMPTY field to a new value. */
+#define ENET_WR_TSEM_TX_SECTION_EMPTY(base, value) (ENET_RMW_TSEM(base, ENET_TSEM_TX_SECTION_EMPTY_MASK, ENET_TSEM_TX_SECTION_EMPTY(value)))
+#define ENET_BWR_TSEM_TX_SECTION_EMPTY(base, value) (ENET_WR_TSEM_TX_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TAEM register
+ */
+/*@{*/
+#define ENET_RD_TAEM(base)       (ENET_TAEM_REG(base))
+#define ENET_WR_TAEM(base, value) (ENET_TAEM_REG(base) = (value))
+#define ENET_RMW_TAEM(base, mask, value) (ENET_WR_TAEM(base, (ENET_RD_TAEM(base) & ~(mask)) | (value)))
+#define ENET_SET_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) |  (value)))
+#define ENET_CLR_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) & ~(value)))
+#define ENET_TOG_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field, and no end-of-frame is
+ * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
+ * stops reading the FIFO and transmits a frame with an MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A minimum value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field. */
+#define ENET_RD_TAEM_TX_ALMOST_EMPTY(base) ((ENET_TAEM_REG(base) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) >> ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)
+#define ENET_BRD_TAEM_TX_ALMOST_EMPTY(base) (ENET_RD_TAEM_TX_ALMOST_EMPTY(base))
+
+/*! @brief Set the TX_ALMOST_EMPTY field to a new value. */
+#define ENET_WR_TAEM_TX_ALMOST_EMPTY(base, value) (ENET_RMW_TAEM(base, ENET_TAEM_TX_ALMOST_EMPTY_MASK, ENET_TAEM_TX_ALMOST_EMPTY(value)))
+#define ENET_BWR_TAEM_TX_ALMOST_EMPTY(base, value) (ENET_WR_TAEM_TX_ALMOST_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TAFL - Transmit FIFO Almost Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000008U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TAFL register
+ */
+/*@{*/
+#define ENET_RD_TAFL(base)       (ENET_TAFL_REG(base))
+#define ENET_WR_TAFL(base, value) (ENET_TAFL_REG(base) = (value))
+#define ENET_RMW_TAFL(base, mask, value) (ENET_WR_TAFL(base, (ENET_RD_TAFL(base) & ~(mask)) | (value)))
+#define ENET_SET_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) |  (value)))
+#define ENET_CLR_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) & ~(value)))
+#define ENET_TOG_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
+ * value of six is required . A recommended value of at least 8 should be set
+ * allowing a latency of two clock cycles to the application. If more latency is
+ * required the value can be increased as necessary (latency = TAFL - 5). When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
+ * application does not react on this signal, the FIFO write control logic, to
+ * avoid FIFO overflow, truncates the current frame and sets the error status. As a
+ * result, the frame will be transmitted with an GMII/MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A FIFO overflow is a fatal error and requires
+ * a global reset on the transmit datapath or at least deassertion of ETHEREN.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field. */
+#define ENET_RD_TAFL_TX_ALMOST_FULL(base) ((ENET_TAFL_REG(base) & ENET_TAFL_TX_ALMOST_FULL_MASK) >> ENET_TAFL_TX_ALMOST_FULL_SHIFT)
+#define ENET_BRD_TAFL_TX_ALMOST_FULL(base) (ENET_RD_TAFL_TX_ALMOST_FULL(base))
+
+/*! @brief Set the TX_ALMOST_FULL field to a new value. */
+#define ENET_WR_TAFL_TX_ALMOST_FULL(base, value) (ENET_RMW_TAFL(base, ENET_TAFL_TX_ALMOST_FULL_MASK, ENET_TAFL_TX_ALMOST_FULL(value)))
+#define ENET_BWR_TAFL_TX_ALMOST_FULL(base, value) (ENET_WR_TAFL_TX_ALMOST_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TIPG - Transmit Inter-Packet Gap
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TIPG - Transmit Inter-Packet Gap (RW)
+ *
+ * Reset value: 0x0000000CU
+ */
+/*!
+ * @name Constants and macros for entire ENET_TIPG register
+ */
+/*@{*/
+#define ENET_RD_TIPG(base)       (ENET_TIPG_REG(base))
+#define ENET_WR_TIPG(base, value) (ENET_TIPG_REG(base) = (value))
+#define ENET_RMW_TIPG(base, mask, value) (ENET_WR_TIPG(base, (ENET_RD_TIPG(base) & ~(mask)) | (value)))
+#define ENET_SET_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) |  (value)))
+#define ENET_CLR_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) & ~(value)))
+#define ENET_TOG_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TIPG bitfields
+ */
+
+/*!
+ * @name Register ENET_TIPG, field IPG[4:0] (RW)
+ *
+ * Indicates the IPG, in bytes, between transmitted frames. Valid values range
+ * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
+ * 27, the IPG is 27.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TIPG_IPG field. */
+#define ENET_RD_TIPG_IPG(base) ((ENET_TIPG_REG(base) & ENET_TIPG_IPG_MASK) >> ENET_TIPG_IPG_SHIFT)
+#define ENET_BRD_TIPG_IPG(base) (ENET_RD_TIPG_IPG(base))
+
+/*! @brief Set the IPG field to a new value. */
+#define ENET_WR_TIPG_IPG(base, value) (ENET_RMW_TIPG(base, ENET_TIPG_IPG_MASK, ENET_TIPG_IPG(value)))
+#define ENET_BWR_TIPG_IPG(base, value) (ENET_WR_TIPG_IPG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_FTRL - Frame Truncation Length
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_FTRL - Frame Truncation Length (RW)
+ *
+ * Reset value: 0x000007FFU
+ */
+/*!
+ * @name Constants and macros for entire ENET_FTRL register
+ */
+/*@{*/
+#define ENET_RD_FTRL(base)       (ENET_FTRL_REG(base))
+#define ENET_WR_FTRL(base, value) (ENET_FTRL_REG(base) = (value))
+#define ENET_RMW_FTRL(base, mask, value) (ENET_WR_FTRL(base, (ENET_RD_FTRL(base) & ~(mask)) | (value)))
+#define ENET_SET_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) |  (value)))
+#define ENET_CLR_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) & ~(value)))
+#define ENET_TOG_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_FTRL bitfields
+ */
+
+/*!
+ * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
+ *
+ * Indicates the value a receive frame is truncated, if it is greater than this
+ * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
+ * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
+ * less data, guaranteeing that it never receives more than the set limit.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_FTRL_TRUNC_FL field. */
+#define ENET_RD_FTRL_TRUNC_FL(base) ((ENET_FTRL_REG(base) & ENET_FTRL_TRUNC_FL_MASK) >> ENET_FTRL_TRUNC_FL_SHIFT)
+#define ENET_BRD_FTRL_TRUNC_FL(base) (ENET_RD_FTRL_TRUNC_FL(base))
+
+/*! @brief Set the TRUNC_FL field to a new value. */
+#define ENET_WR_FTRL_TRUNC_FL(base, value) (ENET_RMW_FTRL(base, ENET_FTRL_TRUNC_FL_MASK, ENET_FTRL_TRUNC_FL(value)))
+#define ENET_BWR_FTRL_TRUNC_FL(base, value) (ENET_WR_FTRL_TRUNC_FL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TACC - Transmit Accelerator Function Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TACC - Transmit Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TACC controls accelerator actions when sending frames. The register can be
+ * changed before or after each frame, but it must remain unmodified during frame
+ * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
+ * checksum feature.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TACC register
+ */
+/*@{*/
+#define ENET_RD_TACC(base)       (ENET_TACC_REG(base))
+#define ENET_WR_TACC(base, value) (ENET_TACC_REG(base) = (value))
+#define ENET_RMW_TACC(base, mask, value) (ENET_WR_TACC(base, (ENET_RD_TACC(base) & ~(mask)) | (value)))
+#define ENET_SET_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) |  (value)))
+#define ENET_CLR_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) & ~(value)))
+#define ENET_TOG_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TACC bitfields
+ */
+
+/*!
+ * @name Register ENET_TACC, field SHIFT16[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Indicates to the transmit data FIFO that the written frames contain
+ *     two additional octets before the frame data. This means the actual frame
+ *     begins at bit 16 of the first word written into the FIFO. This function
+ *     allows putting the frame payload on a 32-bit boundary in memory, as the
+ *     14-byte Ethernet header is extended to a 16-byte header.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_SHIFT16 field. */
+#define ENET_RD_TACC_SHIFT16(base) ((ENET_TACC_REG(base) & ENET_TACC_SHIFT16_MASK) >> ENET_TACC_SHIFT16_SHIFT)
+#define ENET_BRD_TACC_SHIFT16(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_SHIFT16_SHIFT))
+
+/*! @brief Set the SHIFT16 field to a new value. */
+#define ENET_WR_TACC_SHIFT16(base, value) (ENET_RMW_TACC(base, ENET_TACC_SHIFT16_MASK, ENET_TACC_SHIFT16(value)))
+#define ENET_BWR_TACC_SHIFT16(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_SHIFT16_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TACC, field IPCHK[3] (RW)
+ *
+ * Enables insertion of IP header checksum.
+ *
+ * Values:
+ * - 0b0 - Checksum is not inserted.
+ * - 0b1 - If an IP frame is transmitted, the checksum is inserted
+ *     automatically. The IP header checksum field must be cleared. If a non-IP frame is
+ *     transmitted the frame is not modified.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_IPCHK field. */
+#define ENET_RD_TACC_IPCHK(base) ((ENET_TACC_REG(base) & ENET_TACC_IPCHK_MASK) >> ENET_TACC_IPCHK_SHIFT)
+#define ENET_BRD_TACC_IPCHK(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_IPCHK_SHIFT))
+
+/*! @brief Set the IPCHK field to a new value. */
+#define ENET_WR_TACC_IPCHK(base, value) (ENET_RMW_TACC(base, ENET_TACC_IPCHK_MASK, ENET_TACC_IPCHK(value)))
+#define ENET_BWR_TACC_IPCHK(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_IPCHK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TACC, field PROCHK[4] (RW)
+ *
+ * Enables insertion of protocol checksum.
+ *
+ * Values:
+ * - 0b0 - Checksum not inserted.
+ * - 0b1 - If an IP frame with a known protocol is transmitted, the checksum is
+ *     inserted automatically into the frame. The checksum field must be cleared.
+ *     The other frames are not modified.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_PROCHK field. */
+#define ENET_RD_TACC_PROCHK(base) ((ENET_TACC_REG(base) & ENET_TACC_PROCHK_MASK) >> ENET_TACC_PROCHK_SHIFT)
+#define ENET_BRD_TACC_PROCHK(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_PROCHK_SHIFT))
+
+/*! @brief Set the PROCHK field to a new value. */
+#define ENET_WR_TACC_PROCHK(base, value) (ENET_RMW_TACC(base, ENET_TACC_PROCHK_MASK, ENET_TACC_PROCHK(value)))
+#define ENET_BWR_TACC_PROCHK(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_PROCHK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RACC - Receive Accelerator Function Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RACC - Receive Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RACC register
+ */
+/*@{*/
+#define ENET_RD_RACC(base)       (ENET_RACC_REG(base))
+#define ENET_WR_RACC(base, value) (ENET_RACC_REG(base) = (value))
+#define ENET_RMW_RACC(base, mask, value) (ENET_WR_RACC(base, (ENET_RD_RACC(base) & ~(mask)) | (value)))
+#define ENET_SET_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) |  (value)))
+#define ENET_CLR_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) & ~(value)))
+#define ENET_TOG_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RACC bitfields
+ */
+
+/*!
+ * @name Register ENET_RACC, field PADREM[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Padding not removed.
+ * - 0b1 - Any bytes following the IP payload section of the frame are removed
+ *     from the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_PADREM field. */
+#define ENET_RD_RACC_PADREM(base) ((ENET_RACC_REG(base) & ENET_RACC_PADREM_MASK) >> ENET_RACC_PADREM_SHIFT)
+#define ENET_BRD_RACC_PADREM(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PADREM_SHIFT))
+
+/*! @brief Set the PADREM field to a new value. */
+#define ENET_WR_RACC_PADREM(base, value) (ENET_RMW_RACC(base, ENET_RACC_PADREM_MASK, ENET_RACC_PADREM(value)))
+#define ENET_BWR_RACC_PADREM(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PADREM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field IPDIS[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with wrong IPv4 header checksum are not discarded.
+ * - 0b1 - If an IPv4 frame is received with a mismatching header checksum, the
+ *     frame is discarded. IPv6 has no header checksum and is not affected by
+ *     this setting. Discarding is only available when the RX FIFO operates in store
+ *     and forward mode (RSFL cleared).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_IPDIS field. */
+#define ENET_RD_RACC_IPDIS(base) ((ENET_RACC_REG(base) & ENET_RACC_IPDIS_MASK) >> ENET_RACC_IPDIS_SHIFT)
+#define ENET_BRD_RACC_IPDIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_IPDIS_SHIFT))
+
+/*! @brief Set the IPDIS field to a new value. */
+#define ENET_WR_RACC_IPDIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_IPDIS_MASK, ENET_RACC_IPDIS(value)))
+#define ENET_BWR_RACC_IPDIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_IPDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field PRODIS[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with wrong checksum are not discarded.
+ * - 0b1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong
+ *     TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only
+ *     available when the RX FIFO operates in store and forward mode (RSFL cleared).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_PRODIS field. */
+#define ENET_RD_RACC_PRODIS(base) ((ENET_RACC_REG(base) & ENET_RACC_PRODIS_MASK) >> ENET_RACC_PRODIS_SHIFT)
+#define ENET_BRD_RACC_PRODIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PRODIS_SHIFT))
+
+/*! @brief Set the PRODIS field to a new value. */
+#define ENET_WR_RACC_PRODIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_PRODIS_MASK, ENET_RACC_PRODIS(value)))
+#define ENET_BWR_RACC_PRODIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PRODIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field LINEDIS[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with errors are not discarded.
+ * - 0b1 - Any frame received with a CRC, length, or PHY error is automatically
+ *     discarded and not forwarded to the user application interface.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_LINEDIS field. */
+#define ENET_RD_RACC_LINEDIS(base) ((ENET_RACC_REG(base) & ENET_RACC_LINEDIS_MASK) >> ENET_RACC_LINEDIS_SHIFT)
+#define ENET_BRD_RACC_LINEDIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_LINEDIS_SHIFT))
+
+/*! @brief Set the LINEDIS field to a new value. */
+#define ENET_WR_RACC_LINEDIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_LINEDIS_MASK, ENET_RACC_LINEDIS(value)))
+#define ENET_BWR_RACC_LINEDIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_LINEDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field SHIFT16[7] (RW)
+ *
+ * When this field is set, the actual frame data starts at bit 16 of the first
+ * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
+ * This function only affects the FIFO storage and has no influence on the
+ * statistics, which use the actual length of the frame received.
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Instructs the MAC to write two additional bytes in front of each
+ *     frame received into the RX FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_SHIFT16 field. */
+#define ENET_RD_RACC_SHIFT16(base) ((ENET_RACC_REG(base) & ENET_RACC_SHIFT16_MASK) >> ENET_RACC_SHIFT16_SHIFT)
+#define ENET_BRD_RACC_SHIFT16(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_SHIFT16_SHIFT))
+
+/*! @brief Set the SHIFT16 field to a new value. */
+#define ENET_WR_RACC_SHIFT16(base, value) (ENET_RMW_RACC(base, ENET_RACC_SHIFT16_MASK, ENET_RACC_SHIFT16(value)))
+#define ENET_BWR_RACC_SHIFT16(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_SHIFT16_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_PACKETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_PACKETS(base) (ENET_RMON_T_PACKETS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field. */
+#define ENET_RD_RMON_T_PACKETS_TXPKTS(base) ((ENET_RMON_T_PACKETS_REG(base) & ENET_RMON_T_PACKETS_TXPKTS_MASK) >> ENET_RMON_T_PACKETS_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_PACKETS_TXPKTS(base) (ENET_RD_RMON_T_PACKETS_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RMON Tx Broadcast Packets
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_BC_PKT(base) (ENET_RMON_T_BC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field. */
+#define ENET_RD_RMON_T_BC_PKT_TXPKTS(base) ((ENET_RMON_T_BC_PKT_REG(base) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) >> ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_BC_PKT_TXPKTS(base) (ENET_RD_RMON_T_BC_PKT_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_MC_PKT(base) (ENET_RMON_T_MC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field. */
+#define ENET_RD_RMON_T_MC_PKT_TXPKTS(base) ((ENET_RMON_T_MC_PKT_REG(base) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) >> ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_MC_PKT_TXPKTS(base) (ENET_RD_RMON_T_MC_PKT_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_CRC_ALIGN(base) (ENET_RMON_T_CRC_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field. */
+#define ENET_RD_RMON_T_CRC_ALIGN_TXPKTS(base) ((ENET_RMON_T_CRC_ALIGN_REG(base) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) >> ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_CRC_ALIGN_TXPKTS(base) (ENET_RD_RMON_T_CRC_ALIGN_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_UNDERSIZE(base) (ENET_RMON_T_UNDERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field. */
+#define ENET_RD_RMON_T_UNDERSIZE_TXPKTS(base) ((ENET_RMON_T_UNDERSIZE_REG(base) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) >> ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_UNDERSIZE_TXPKTS(base) (ENET_RD_RMON_T_UNDERSIZE_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_OVERSIZE(base) (ENET_RMON_T_OVERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field. */
+#define ENET_RD_RMON_T_OVERSIZE_TXPKTS(base) ((ENET_RMON_T_OVERSIZE_REG(base) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) >> ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_OVERSIZE_TXPKTS(base) (ENET_RD_RMON_T_OVERSIZE_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_FRAG register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_FRAG(base) (ENET_RMON_T_FRAG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field. */
+#define ENET_RD_RMON_T_FRAG_TXPKTS(base) ((ENET_RMON_T_FRAG_REG(base) & ENET_RMON_T_FRAG_TXPKTS_MASK) >> ENET_RMON_T_FRAG_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_FRAG_TXPKTS(base) (ENET_RD_RMON_T_FRAG_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_JAB register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_JAB(base) (ENET_RMON_T_JAB_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field. */
+#define ENET_RD_RMON_T_JAB_TXPKTS(base) ((ENET_RMON_T_JAB_REG(base) & ENET_RMON_T_JAB_TXPKTS_MASK) >> ENET_RMON_T_JAB_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_JAB_TXPKTS(base) (ENET_RD_RMON_T_JAB_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_COL register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_COL(base) (ENET_RMON_T_COL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_COL bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field. */
+#define ENET_RD_RMON_T_COL_TXPKTS(base) ((ENET_RMON_T_COL_REG(base) & ENET_RMON_T_COL_TXPKTS_MASK) >> ENET_RMON_T_COL_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_COL_TXPKTS(base) (ENET_RD_RMON_T_COL_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P64 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P64(base) (ENET_RMON_T_P64_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field. */
+#define ENET_RD_RMON_T_P64_TXPKTS(base) ((ENET_RMON_T_P64_REG(base) & ENET_RMON_T_P64_TXPKTS_MASK) >> ENET_RMON_T_P64_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P64_TXPKTS(base) (ENET_RD_RMON_T_P64_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P65TO127(base) (ENET_RMON_T_P65TO127_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field. */
+#define ENET_RD_RMON_T_P65TO127_TXPKTS(base) ((ENET_RMON_T_P65TO127_REG(base) & ENET_RMON_T_P65TO127_TXPKTS_MASK) >> ENET_RMON_T_P65TO127_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P65TO127_TXPKTS(base) (ENET_RD_RMON_T_P65TO127_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P128TO255(base) (ENET_RMON_T_P128TO255_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field. */
+#define ENET_RD_RMON_T_P128TO255_TXPKTS(base) ((ENET_RMON_T_P128TO255_REG(base) & ENET_RMON_T_P128TO255_TXPKTS_MASK) >> ENET_RMON_T_P128TO255_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P128TO255_TXPKTS(base) (ENET_RD_RMON_T_P128TO255_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P256TO511(base) (ENET_RMON_T_P256TO511_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field. */
+#define ENET_RD_RMON_T_P256TO511_TXPKTS(base) ((ENET_RMON_T_P256TO511_REG(base) & ENET_RMON_T_P256TO511_TXPKTS_MASK) >> ENET_RMON_T_P256TO511_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P256TO511_TXPKTS(base) (ENET_RD_RMON_T_P256TO511_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P512TO1023(base) (ENET_RMON_T_P512TO1023_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field. */
+#define ENET_RD_RMON_T_P512TO1023_TXPKTS(base) ((ENET_RMON_T_P512TO1023_REG(base) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) >> ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P512TO1023_TXPKTS(base) (ENET_RD_RMON_T_P512TO1023_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P1024TO2047(base) (ENET_RMON_T_P1024TO2047_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field. */
+#define ENET_RD_RMON_T_P1024TO2047_TXPKTS(base) ((ENET_RMON_T_P1024TO2047_REG(base) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) >> ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P1024TO2047_TXPKTS(base) (ENET_RD_RMON_T_P1024TO2047_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P_GTE2048(base) (ENET_RMON_T_P_GTE2048_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field. */
+#define ENET_RD_RMON_T_P_GTE2048_TXPKTS(base) ((ENET_RMON_T_P_GTE2048_REG(base) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) >> ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P_GTE2048_TXPKTS(base) (ENET_RD_RMON_T_P_GTE2048_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OCTETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_OCTETS(base) (ENET_RMON_T_OCTETS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_FRAME_OK(base) (ENET_IEEE_T_FRAME_OK_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field. */
+#define ENET_RD_IEEE_T_FRAME_OK_COUNT(base) ((ENET_IEEE_T_FRAME_OK_REG(base) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) >> ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_FRAME_OK_COUNT(base) (ENET_RD_IEEE_T_FRAME_OK_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_1COL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_1COL(base) (ENET_IEEE_T_1COL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_1COL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field. */
+#define ENET_RD_IEEE_T_1COL_COUNT(base) ((ENET_IEEE_T_1COL_REG(base) & ENET_IEEE_T_1COL_COUNT_MASK) >> ENET_IEEE_T_1COL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_1COL_COUNT(base) (ENET_RD_IEEE_T_1COL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_MCOL(base) (ENET_IEEE_T_MCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field. */
+#define ENET_RD_IEEE_T_MCOL_COUNT(base) ((ENET_IEEE_T_MCOL_REG(base) & ENET_IEEE_T_MCOL_COUNT_MASK) >> ENET_IEEE_T_MCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_MCOL_COUNT(base) (ENET_RD_IEEE_T_MCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_DEF register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_DEF(base) (ENET_IEEE_T_DEF_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_DEF bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field. */
+#define ENET_RD_IEEE_T_DEF_COUNT(base) ((ENET_IEEE_T_DEF_REG(base) & ENET_IEEE_T_DEF_COUNT_MASK) >> ENET_IEEE_T_DEF_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_DEF_COUNT(base) (ENET_RD_IEEE_T_DEF_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_LCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_LCOL(base) (ENET_IEEE_T_LCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field. */
+#define ENET_RD_IEEE_T_LCOL_COUNT(base) ((ENET_IEEE_T_LCOL_REG(base) & ENET_IEEE_T_LCOL_COUNT_MASK) >> ENET_IEEE_T_LCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_LCOL_COUNT(base) (ENET_RD_IEEE_T_LCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_EXCOL(base) (ENET_IEEE_T_EXCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field. */
+#define ENET_RD_IEEE_T_EXCOL_COUNT(base) ((ENET_IEEE_T_EXCOL_REG(base) & ENET_IEEE_T_EXCOL_COUNT_MASK) >> ENET_IEEE_T_EXCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_EXCOL_COUNT(base) (ENET_RD_IEEE_T_EXCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MACERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_MACERR(base) (ENET_IEEE_T_MACERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field. */
+#define ENET_RD_IEEE_T_MACERR_COUNT(base) ((ENET_IEEE_T_MACERR_REG(base) & ENET_IEEE_T_MACERR_COUNT_MASK) >> ENET_IEEE_T_MACERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_MACERR_COUNT(base) (ENET_RD_IEEE_T_MACERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_CSERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_CSERR(base) (ENET_IEEE_T_CSERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field. */
+#define ENET_RD_IEEE_T_CSERR_COUNT(base) ((ENET_IEEE_T_CSERR_REG(base) & ENET_IEEE_T_CSERR_COUNT_MASK) >> ENET_IEEE_T_CSERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_CSERR_COUNT(base) (ENET_RD_IEEE_T_CSERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_FDXFC(base) (ENET_IEEE_T_FDXFC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field. */
+#define ENET_RD_IEEE_T_FDXFC_COUNT(base) ((ENET_IEEE_T_FDXFC_REG(base) & ENET_IEEE_T_FDXFC_COUNT_MASK) >> ENET_IEEE_T_FDXFC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_FDXFC_COUNT(base) (ENET_RD_IEEE_T_FDXFC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counts total octets (includes header and FCS fields).
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_OCTETS_OK(base) (ENET_IEEE_T_OCTETS_OK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_PACKETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_PACKETS(base) (ENET_RMON_R_PACKETS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field. */
+#define ENET_RD_RMON_R_PACKETS_COUNT(base) ((ENET_RMON_R_PACKETS_REG(base) & ENET_RMON_R_PACKETS_COUNT_MASK) >> ENET_RMON_R_PACKETS_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_PACKETS_COUNT(base) (ENET_RD_RMON_R_PACKETS_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_BC_PKT(base) (ENET_RMON_R_BC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field. */
+#define ENET_RD_RMON_R_BC_PKT_COUNT(base) ((ENET_RMON_R_BC_PKT_REG(base) & ENET_RMON_R_BC_PKT_COUNT_MASK) >> ENET_RMON_R_BC_PKT_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_BC_PKT_COUNT(base) (ENET_RD_RMON_R_BC_PKT_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_MC_PKT(base) (ENET_RMON_R_MC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field. */
+#define ENET_RD_RMON_R_MC_PKT_COUNT(base) ((ENET_RMON_R_MC_PKT_REG(base) & ENET_RMON_R_MC_PKT_COUNT_MASK) >> ENET_RMON_R_MC_PKT_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_MC_PKT_COUNT(base) (ENET_RD_RMON_R_MC_PKT_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_CRC_ALIGN(base) (ENET_RMON_R_CRC_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field. */
+#define ENET_RD_RMON_R_CRC_ALIGN_COUNT(base) ((ENET_RMON_R_CRC_ALIGN_REG(base) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) >> ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_CRC_ALIGN_COUNT(base) (ENET_RD_RMON_R_CRC_ALIGN_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_UNDERSIZE(base) (ENET_RMON_R_UNDERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field. */
+#define ENET_RD_RMON_R_UNDERSIZE_COUNT(base) ((ENET_RMON_R_UNDERSIZE_REG(base) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) >> ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_UNDERSIZE_COUNT(base) (ENET_RD_RMON_R_UNDERSIZE_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_OVERSIZE(base) (ENET_RMON_R_OVERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field. */
+#define ENET_RD_RMON_R_OVERSIZE_COUNT(base) ((ENET_RMON_R_OVERSIZE_REG(base) & ENET_RMON_R_OVERSIZE_COUNT_MASK) >> ENET_RMON_R_OVERSIZE_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_OVERSIZE_COUNT(base) (ENET_RD_RMON_R_OVERSIZE_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_FRAG register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_FRAG(base) (ENET_RMON_R_FRAG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field. */
+#define ENET_RD_RMON_R_FRAG_COUNT(base) ((ENET_RMON_R_FRAG_REG(base) & ENET_RMON_R_FRAG_COUNT_MASK) >> ENET_RMON_R_FRAG_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_FRAG_COUNT(base) (ENET_RD_RMON_R_FRAG_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_JAB register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_JAB(base) (ENET_RMON_R_JAB_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_JAB_COUNT field. */
+#define ENET_RD_RMON_R_JAB_COUNT(base) ((ENET_RMON_R_JAB_REG(base) & ENET_RMON_R_JAB_COUNT_MASK) >> ENET_RMON_R_JAB_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_JAB_COUNT(base) (ENET_RD_RMON_R_JAB_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P64 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P64(base) (ENET_RMON_R_P64_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P64_COUNT field. */
+#define ENET_RD_RMON_R_P64_COUNT(base) ((ENET_RMON_R_P64_REG(base) & ENET_RMON_R_P64_COUNT_MASK) >> ENET_RMON_R_P64_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P64_COUNT(base) (ENET_RD_RMON_R_P64_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P65TO127(base) (ENET_RMON_R_P65TO127_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field. */
+#define ENET_RD_RMON_R_P65TO127_COUNT(base) ((ENET_RMON_R_P65TO127_REG(base) & ENET_RMON_R_P65TO127_COUNT_MASK) >> ENET_RMON_R_P65TO127_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P65TO127_COUNT(base) (ENET_RD_RMON_R_P65TO127_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P128TO255(base) (ENET_RMON_R_P128TO255_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field. */
+#define ENET_RD_RMON_R_P128TO255_COUNT(base) ((ENET_RMON_R_P128TO255_REG(base) & ENET_RMON_R_P128TO255_COUNT_MASK) >> ENET_RMON_R_P128TO255_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P128TO255_COUNT(base) (ENET_RD_RMON_R_P128TO255_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P256TO511(base) (ENET_RMON_R_P256TO511_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field. */
+#define ENET_RD_RMON_R_P256TO511_COUNT(base) ((ENET_RMON_R_P256TO511_REG(base) & ENET_RMON_R_P256TO511_COUNT_MASK) >> ENET_RMON_R_P256TO511_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P256TO511_COUNT(base) (ENET_RD_RMON_R_P256TO511_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P512TO1023(base) (ENET_RMON_R_P512TO1023_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field. */
+#define ENET_RD_RMON_R_P512TO1023_COUNT(base) ((ENET_RMON_R_P512TO1023_REG(base) & ENET_RMON_R_P512TO1023_COUNT_MASK) >> ENET_RMON_R_P512TO1023_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P512TO1023_COUNT(base) (ENET_RD_RMON_R_P512TO1023_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P1024TO2047(base) (ENET_RMON_R_P1024TO2047_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field. */
+#define ENET_RD_RMON_R_P1024TO2047_COUNT(base) ((ENET_RMON_R_P1024TO2047_REG(base) & ENET_RMON_R_P1024TO2047_COUNT_MASK) >> ENET_RMON_R_P1024TO2047_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P1024TO2047_COUNT(base) (ENET_RD_RMON_R_P1024TO2047_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P_GTE2048 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P_GTE2048(base) (ENET_RMON_R_P_GTE2048_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P_GTE2048, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P_GTE2048_COUNT field. */
+#define ENET_RD_RMON_R_P_GTE2048_COUNT(base) ((ENET_RMON_R_P_GTE2048_REG(base) & ENET_RMON_R_P_GTE2048_COUNT_MASK) >> ENET_RMON_R_P_GTE2048_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P_GTE2048_COUNT(base) (ENET_RD_RMON_R_P_GTE2048_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OCTETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_OCTETS(base) (ENET_RMON_R_OCTETS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counter increments if a frame with invalid or missing SFD character is
+ * detected and has been dropped. None of the other counters increments if this counter
+ * increments.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_DROP register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_DROP(base) (ENET_IEEE_R_DROP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_DROP bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field. */
+#define ENET_RD_IEEE_R_DROP_COUNT(base) ((ENET_IEEE_R_DROP_REG(base) & ENET_IEEE_R_DROP_COUNT_MASK) >> ENET_IEEE_R_DROP_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_DROP_COUNT(base) (ENET_RD_IEEE_R_DROP_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_FRAME_OK(base) (ENET_IEEE_R_FRAME_OK_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field. */
+#define ENET_RD_IEEE_R_FRAME_OK_COUNT(base) ((ENET_IEEE_R_FRAME_OK_REG(base) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) >> ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_FRAME_OK_COUNT(base) (ENET_RD_IEEE_R_FRAME_OK_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_CRC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_CRC(base) (ENET_IEEE_R_CRC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_CRC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field. */
+#define ENET_RD_IEEE_R_CRC_COUNT(base) ((ENET_IEEE_R_CRC_REG(base) & ENET_IEEE_R_CRC_COUNT_MASK) >> ENET_IEEE_R_CRC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_CRC_COUNT(base) (ENET_RD_IEEE_R_CRC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_ALIGN(base) (ENET_IEEE_R_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field. */
+#define ENET_RD_IEEE_R_ALIGN_COUNT(base) ((ENET_IEEE_R_ALIGN_REG(base) & ENET_IEEE_R_ALIGN_COUNT_MASK) >> ENET_IEEE_R_ALIGN_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_ALIGN_COUNT(base) (ENET_RD_IEEE_R_ALIGN_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_MACERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_MACERR(base) (ENET_IEEE_R_MACERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field. */
+#define ENET_RD_IEEE_R_MACERR_COUNT(base) ((ENET_IEEE_R_MACERR_REG(base) & ENET_IEEE_R_MACERR_COUNT_MASK) >> ENET_IEEE_R_MACERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_MACERR_COUNT(base) (ENET_RD_IEEE_R_MACERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_FDXFC(base) (ENET_IEEE_R_FDXFC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field. */
+#define ENET_RD_IEEE_R_FDXFC_COUNT(base) ((ENET_IEEE_R_FDXFC_REG(base) & ENET_IEEE_R_FDXFC_COUNT_MASK) >> ENET_IEEE_R_FDXFC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_FDXFC_COUNT(base) (ENET_RD_IEEE_R_FDXFC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_OCTETS_OK(base) (ENET_IEEE_R_OCTETS_OK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATCR - Adjustable Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATCR - Adjustable Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * ATCR command fields can trigger the corresponding events directly. It is not
+ * necessary to preserve any of the configuration fields when a command field is
+ * set in the register, that is, no read-modify-write is required. The fields are
+ * automatically cleared after the command completes.
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATCR register
+ */
+/*@{*/
+#define ENET_RD_ATCR(base)       (ENET_ATCR_REG(base))
+#define ENET_WR_ATCR(base, value) (ENET_ATCR_REG(base) = (value))
+#define ENET_RMW_ATCR(base, mask, value) (ENET_WR_ATCR(base, (ENET_RD_ATCR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) |  (value)))
+#define ENET_CLR_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) & ~(value)))
+#define ENET_TOG_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATCR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCR, field EN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer stops at the current value.
+ * - 0b1 - The timer starts incrementing.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_EN field. */
+#define ENET_RD_ATCR_EN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_EN_MASK) >> ENET_ATCR_EN_SHIFT)
+#define ENET_BRD_ATCR_EN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_EN_SHIFT))
+
+/*! @brief Set the EN field to a new value. */
+#define ENET_WR_ATCR_EN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_EN_MASK, ENET_ATCR_EN(value)))
+#define ENET_BWR_ATCR_EN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field OFFEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - The timer can be reset to zero when the given offset time is reached
+ *     (offset event). The field is cleared when the offset event is reached, so
+ *     no further event occurs until the field is set again. The timer offset
+ *     value must be set before setting this field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_OFFEN field. */
+#define ENET_RD_ATCR_OFFEN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_OFFEN_MASK) >> ENET_ATCR_OFFEN_SHIFT)
+#define ENET_BRD_ATCR_OFFEN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFEN_SHIFT))
+
+/*! @brief Set the OFFEN field to a new value. */
+#define ENET_WR_ATCR_OFFEN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_OFFEN_MASK, ENET_ATCR_OFFEN(value)))
+#define ENET_BWR_ATCR_OFFEN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field OFFRST[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer is not affected and no action occurs, besides clearing
+ *     OFFEN, when the offset is reached.
+ * - 0b1 - If OFFEN is set, the timer resets to zero when the offset setting is
+ *     reached. The offset event does not cause a timer interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_OFFRST field. */
+#define ENET_RD_ATCR_OFFRST(base) ((ENET_ATCR_REG(base) & ENET_ATCR_OFFRST_MASK) >> ENET_ATCR_OFFRST_SHIFT)
+#define ENET_BRD_ATCR_OFFRST(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFRST_SHIFT))
+
+/*! @brief Set the OFFRST field to a new value. */
+#define ENET_WR_ATCR_OFFRST(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_OFFRST_MASK, ENET_ATCR_OFFRST(value)))
+#define ENET_BWR_ATCR_OFFRST(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field PEREN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the
+ *     event signal output is asserted when the timer wraps around according to the
+ *     periodic setting ATPER. The timer period value must be set before setting
+ *     this bit. Not all devices contain the event signal output. See the chip
+ *     configuration details.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_PEREN field. */
+#define ENET_RD_ATCR_PEREN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_PEREN_MASK) >> ENET_ATCR_PEREN_SHIFT)
+#define ENET_BRD_ATCR_PEREN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PEREN_SHIFT))
+
+/*! @brief Set the PEREN field to a new value. */
+#define ENET_WR_ATCR_PEREN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_PEREN_MASK, ENET_ATCR_PEREN(value)))
+#define ENET_BWR_ATCR_PEREN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field PINPER[7] (RW)
+ *
+ * Enables event signal output assertion on period event. Not all devices
+ * contain the event signal output. See the chip configuration details.
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - Enable.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_PINPER field. */
+#define ENET_RD_ATCR_PINPER(base) ((ENET_ATCR_REG(base) & ENET_ATCR_PINPER_MASK) >> ENET_ATCR_PINPER_SHIFT)
+#define ENET_BRD_ATCR_PINPER(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PINPER_SHIFT))
+
+/*! @brief Set the PINPER field to a new value. */
+#define ENET_WR_ATCR_PINPER(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_PINPER_MASK, ENET_ATCR_PINPER(value)))
+#define ENET_BWR_ATCR_PINPER(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PINPER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field RESTART[9] (RW)
+ *
+ * Resets the timer to zero. This has no effect on the counter enable. If the
+ * counter is enabled when this field is set, the timer is reset to zero and starts
+ * counting from there. When set, all other fields are ignored during a write.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_RESTART field. */
+#define ENET_RD_ATCR_RESTART(base) ((ENET_ATCR_REG(base) & ENET_ATCR_RESTART_MASK) >> ENET_ATCR_RESTART_SHIFT)
+#define ENET_BRD_ATCR_RESTART(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_RESTART_SHIFT))
+
+/*! @brief Set the RESTART field to a new value. */
+#define ENET_WR_ATCR_RESTART(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_RESTART_MASK, ENET_ATCR_RESTART(value)))
+#define ENET_BWR_ATCR_RESTART(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_RESTART_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field CAPTURE[11] (RW)
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - The current time is captured and can be read from the ATVR register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_CAPTURE field. */
+#define ENET_RD_ATCR_CAPTURE(base) ((ENET_ATCR_REG(base) & ENET_ATCR_CAPTURE_MASK) >> ENET_ATCR_CAPTURE_SHIFT)
+#define ENET_BRD_ATCR_CAPTURE(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_CAPTURE_SHIFT))
+
+/*! @brief Set the CAPTURE field to a new value. */
+#define ENET_WR_ATCR_CAPTURE(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_CAPTURE_MASK, ENET_ATCR_CAPTURE(value)))
+#define ENET_BWR_ATCR_CAPTURE(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_CAPTURE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field SLAVE[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer is active and all configuration fields in this register are
+ *     relevant.
+ * - 0b1 - The internal timer is disabled and the externally provided timer
+ *     value is used. All other fields, except CAPTURE, in this register have no
+ *     effect. CAPTURE can still be used to capture the current timer value.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_SLAVE field. */
+#define ENET_RD_ATCR_SLAVE(base) ((ENET_ATCR_REG(base) & ENET_ATCR_SLAVE_MASK) >> ENET_ATCR_SLAVE_SHIFT)
+#define ENET_BRD_ATCR_SLAVE(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_SLAVE_SHIFT))
+
+/*! @brief Set the SLAVE field to a new value. */
+#define ENET_WR_ATCR_SLAVE(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_SLAVE_MASK, ENET_ATCR_SLAVE(value)))
+#define ENET_BWR_ATCR_SLAVE(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_SLAVE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATVR - Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATVR - Timer Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATVR register
+ */
+/*@{*/
+#define ENET_RD_ATVR(base)       (ENET_ATVR_REG(base))
+#define ENET_WR_ATVR(base, value) (ENET_ATVR_REG(base) = (value))
+#define ENET_RMW_ATVR(base, mask, value) (ENET_WR_ATVR(base, (ENET_RD_ATVR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) |  (value)))
+#define ENET_CLR_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) & ~(value)))
+#define ENET_TOG_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATOFF - Timer Offset Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATOFF - Timer Offset Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATOFF register
+ */
+/*@{*/
+#define ENET_RD_ATOFF(base)      (ENET_ATOFF_REG(base))
+#define ENET_WR_ATOFF(base, value) (ENET_ATOFF_REG(base) = (value))
+#define ENET_RMW_ATOFF(base, mask, value) (ENET_WR_ATOFF(base, (ENET_RD_ATOFF(base) & ~(mask)) | (value)))
+#define ENET_SET_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) |  (value)))
+#define ENET_CLR_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) & ~(value)))
+#define ENET_TOG_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATPER - Timer Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATPER - Timer Period Register (RW)
+ *
+ * Reset value: 0x3B9ACA00U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATPER register
+ */
+/*@{*/
+#define ENET_RD_ATPER(base)      (ENET_ATPER_REG(base))
+#define ENET_WR_ATPER(base, value) (ENET_ATPER_REG(base) = (value))
+#define ENET_RMW_ATPER(base, mask, value) (ENET_WR_ATPER(base, (ENET_RD_ATPER(base) & ~(mask)) | (value)))
+#define ENET_SET_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) |  (value)))
+#define ENET_CLR_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) & ~(value)))
+#define ENET_TOG_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATCOR - Timer Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATCOR - Timer Correction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATCOR register
+ */
+/*@{*/
+#define ENET_RD_ATCOR(base)      (ENET_ATCOR_REG(base))
+#define ENET_WR_ATCOR(base, value) (ENET_ATCOR_REG(base) = (value))
+#define ENET_RMW_ATCOR(base, mask, value) (ENET_WR_ATCOR(base, (ENET_RD_ATCOR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) |  (value)))
+#define ENET_CLR_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) & ~(value)))
+#define ENET_TOG_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATCOR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCOR, field COR[30:0] (RW)
+ *
+ * Defines after how many timer clock cycles (ts_clk) the correction counter
+ * should be reset and trigger a correction increment on the timer. The amount of
+ * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
+ * counter and no corrections occur. This value is given in clock cycles, not in
+ * nanoseconds as all other values.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCOR_COR field. */
+#define ENET_RD_ATCOR_COR(base) ((ENET_ATCOR_REG(base) & ENET_ATCOR_COR_MASK) >> ENET_ATCOR_COR_SHIFT)
+#define ENET_BRD_ATCOR_COR(base) (ENET_RD_ATCOR_COR(base))
+
+/*! @brief Set the COR field to a new value. */
+#define ENET_WR_ATCOR_COR(base, value) (ENET_RMW_ATCOR(base, ENET_ATCOR_COR_MASK, ENET_ATCOR_COR(value)))
+#define ENET_BWR_ATCOR_COR(base, value) (ENET_WR_ATCOR_COR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATINC - Time-Stamping Clock Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATINC - Time-Stamping Clock Period Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATINC register
+ */
+/*@{*/
+#define ENET_RD_ATINC(base)      (ENET_ATINC_REG(base))
+#define ENET_WR_ATINC(base, value) (ENET_ATINC_REG(base) = (value))
+#define ENET_RMW_ATINC(base, mask, value) (ENET_WR_ATINC(base, (ENET_RD_ATINC(base) & ~(mask)) | (value)))
+#define ENET_SET_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) |  (value)))
+#define ENET_CLR_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) & ~(value)))
+#define ENET_TOG_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATINC bitfields
+ */
+
+/*!
+ * @name Register ENET_ATINC, field INC[6:0] (RW)
+ *
+ * The timer increments by this amount each clock cycle. For example, set to 10
+ * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
+ * that is an integer fraction of the period set in ATPER.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATINC_INC field. */
+#define ENET_RD_ATINC_INC(base) ((ENET_ATINC_REG(base) & ENET_ATINC_INC_MASK) >> ENET_ATINC_INC_SHIFT)
+#define ENET_BRD_ATINC_INC(base) (ENET_RD_ATINC_INC(base))
+
+/*! @brief Set the INC field to a new value. */
+#define ENET_WR_ATINC_INC(base, value) (ENET_RMW_ATINC(base, ENET_ATINC_INC_MASK, ENET_ATINC_INC(value)))
+#define ENET_BWR_ATINC_INC(base, value) (ENET_WR_ATINC_INC(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
+ *
+ * This value is added every time the correction timer expires (every clock
+ * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
+ * than INC speeds up the timer.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATINC_INC_CORR field. */
+#define ENET_RD_ATINC_INC_CORR(base) ((ENET_ATINC_REG(base) & ENET_ATINC_INC_CORR_MASK) >> ENET_ATINC_INC_CORR_SHIFT)
+#define ENET_BRD_ATINC_INC_CORR(base) (ENET_RD_ATINC_INC_CORR(base))
+
+/*! @brief Set the INC_CORR field to a new value. */
+#define ENET_WR_ATINC_INC_CORR(base, value) (ENET_RMW_ATINC(base, ENET_ATINC_INC_CORR_MASK, ENET_ATINC_INC_CORR(value)))
+#define ENET_BWR_ATINC_INC_CORR(base, value) (ENET_WR_ATINC_INC_CORR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATSTMP register
+ */
+/*@{*/
+#define ENET_RD_ATSTMP(base)     (ENET_ATSTMP_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TGSR - Timer Global Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TGSR - Timer Global Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TGSR register
+ */
+/*@{*/
+#define ENET_RD_TGSR(base)       (ENET_TGSR_REG(base))
+#define ENET_WR_TGSR(base, value) (ENET_TGSR_REG(base) = (value))
+#define ENET_RMW_TGSR(base, mask, value) (ENET_WR_TGSR(base, (ENET_RD_TGSR(base) & ~(mask)) | (value)))
+#define ENET_SET_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) |  (value)))
+#define ENET_CLR_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) & ~(value)))
+#define ENET_TOG_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TGSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TGSR, field TF0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 0 is clear
+ * - 0b1 - Timer Flag for Channel 0 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF0 field. */
+#define ENET_RD_TGSR_TF0(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF0_MASK) >> ENET_TGSR_TF0_SHIFT)
+#define ENET_BRD_TGSR_TF0(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF0_SHIFT))
+
+/*! @brief Set the TF0 field to a new value. */
+#define ENET_WR_TGSR_TF0(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF2_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF0(value)))
+#define ENET_BWR_TGSR_TF0(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 1 is clear
+ * - 0b1 - Timer Flag for Channel 1 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF1 field. */
+#define ENET_RD_TGSR_TF1(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF1_MASK) >> ENET_TGSR_TF1_SHIFT)
+#define ENET_BRD_TGSR_TF1(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF1_SHIFT))
+
+/*! @brief Set the TF1 field to a new value. */
+#define ENET_WR_TGSR_TF1(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF1_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF2_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF1(value)))
+#define ENET_BWR_TGSR_TF1(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 2 is clear
+ * - 0b1 - Timer Flag for Channel 2 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF2 field. */
+#define ENET_RD_TGSR_TF2(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF2_MASK) >> ENET_TGSR_TF2_SHIFT)
+#define ENET_BRD_TGSR_TF2(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF2_SHIFT))
+
+/*! @brief Set the TF2 field to a new value. */
+#define ENET_WR_TGSR_TF2(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF2_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF2(value)))
+#define ENET_BWR_TGSR_TF2(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 3 is clear
+ * - 0b1 - Timer Flag for Channel 3 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF3 field. */
+#define ENET_RD_TGSR_TF3(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF3_MASK) >> ENET_TGSR_TF3_SHIFT)
+#define ENET_BRD_TGSR_TF3(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF3_SHIFT))
+
+/*! @brief Set the TF3 field to a new value. */
+#define ENET_WR_TGSR_TF3(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF3_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF2_MASK), ENET_TGSR_TF3(value)))
+#define ENET_BWR_TGSR_TF3(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF3_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCSR - Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCSR - Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCSR register
+ */
+/*@{*/
+#define ENET_RD_TCSR(base, index) (ENET_TCSR_REG(base, index))
+#define ENET_WR_TCSR(base, index, value) (ENET_TCSR_REG(base, index) = (value))
+#define ENET_RMW_TCSR(base, index, mask, value) (ENET_WR_TCSR(base, index, (ENET_RD_TCSR(base, index) & ~(mask)) | (value)))
+#define ENET_SET_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) |  (value)))
+#define ENET_CLR_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) & ~(value)))
+#define ENET_TOG_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TCSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCSR, field TDRE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA request is disabled
+ * - 0b1 - DMA request is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TDRE field. */
+#define ENET_RD_TCSR_TDRE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TDRE_MASK) >> ENET_TCSR_TDRE_SHIFT)
+#define ENET_BRD_TCSR_TDRE(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TDRE_SHIFT))
+
+/*! @brief Set the TDRE field to a new value. */
+#define ENET_WR_TCSR_TDRE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TDRE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TDRE(value)))
+#define ENET_BWR_TCSR_TDRE(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TDRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TMODE[5:2] (RW)
+ *
+ * Updating the Timer Mode field takes a few cycles to register because it is
+ * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
+ * from the 1588 clock domain. When changing Timer Mode, always disable the
+ * channel and read this register to verify the channel is disabled first.
+ *
+ * Values:
+ * - 0b0000 - Timer Channel is disabled.
+ * - 0b0001 - Timer Channel is configured for Input Capture on rising edge
+ * - 0b0010 - Timer Channel is configured for Input Capture on falling edge
+ * - 0b0011 - Timer Channel is configured for Input Capture on both edges
+ * - 0b0100 - Timer Channel is configured for Output Compare - software only
+ * - 0b0101 - Timer Channel is configured for Output Compare - toggle output on
+ *     compare
+ * - 0b0110 - Timer Channel is configured for Output Compare - clear output on
+ *     compare
+ * - 0b0111 - Timer Channel is configured for Output Compare - set output on
+ *     compare
+ * - 0b1000 - Reserved
+ * - 0b1010 - Timer Channel is configured for Output Compare - clear output on
+ *     compare, set output on overflow
+ * - 0b10x1 - Timer Channel is configured for Output Compare - set output on
+ *     compare, clear output on overflow
+ * - 0b1100 - Reserved
+ * - 0b1110 - Timer Channel is configured for Output Compare - pulse output low
+ *     on compare for one 1588 clock cycle
+ * - 0b1111 - Timer Channel is configured for Output Compare - pulse output high
+ *     on compare for one 1588 clock cycle
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TMODE field. */
+#define ENET_RD_TCSR_TMODE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TMODE_MASK) >> ENET_TCSR_TMODE_SHIFT)
+#define ENET_BRD_TCSR_TMODE(base, index) (ENET_RD_TCSR_TMODE(base, index))
+
+/*! @brief Set the TMODE field to a new value. */
+#define ENET_WR_TCSR_TMODE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TMODE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TMODE(value)))
+#define ENET_BWR_TCSR_TMODE(base, index, value) (ENET_WR_TCSR_TMODE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TIE[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled
+ * - 0b1 - Interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TIE field. */
+#define ENET_RD_TCSR_TIE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TIE_MASK) >> ENET_TCSR_TIE_SHIFT)
+#define ENET_BRD_TCSR_TIE(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define ENET_WR_TCSR_TIE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TIE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TIE(value)))
+#define ENET_BWR_TCSR_TIE(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TF[7] (W1C)
+ *
+ * Sets when input capture or output compare occurs. This flag is double
+ * buffered between the module clock and 1588 clock domains. When this field is 1, it
+ * can be cleared to 0 by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - Input Capture or Output Compare has not occurred
+ * - 0b1 - Input Capture or Output Compare has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TF field. */
+#define ENET_RD_TCSR_TF(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TF_MASK) >> ENET_TCSR_TF_SHIFT)
+#define ENET_BRD_TCSR_TF(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TF_SHIFT))
+
+/*! @brief Set the TF field to a new value. */
+#define ENET_WR_TCSR_TF(base, index, value) (ENET_RMW_TCSR(base, index, ENET_TCSR_TF_MASK, ENET_TCSR_TF(value)))
+#define ENET_BWR_TCSR_TF(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCCR - Timer Compare Capture Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCCR - Timer Compare Capture Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCCR register
+ */
+/*@{*/
+#define ENET_RD_TCCR(base, index) (ENET_TCCR_REG(base, index))
+#define ENET_WR_TCCR(base, index, value) (ENET_TCCR_REG(base, index) = (value))
+#define ENET_RMW_TCCR(base, index, mask, value) (ENET_WR_TCCR(base, index, (ENET_RD_TCCR(base, index) & ~(mask)) | (value)))
+#define ENET_SET_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) |  (value)))
+#define ENET_CLR_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) & ~(value)))
+#define ENET_TOG_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 EWM
+ *
+ * External Watchdog Monitor
+ *
+ * Registers defined in this header file:
+ * - EWM_CTRL - Control Register
+ * - EWM_SERV - Service Register
+ * - EWM_CMPL - Compare Low Register
+ * - EWM_CMPH - Compare High Register
+ */
+
+#define EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
+#define EWM_IDX (0U) /*!< Instance number for EWM. */
+
+/*******************************************************************************
+ * EWM_CTRL - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CTRL - Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
+ * written once after a CPU reset. Modifying these bits more than once, generates
+ * a bus transfer error.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CTRL register
+ */
+/*@{*/
+#define EWM_RD_CTRL(base)        (EWM_CTRL_REG(base))
+#define EWM_WR_CTRL(base, value) (EWM_CTRL_REG(base) = (value))
+#define EWM_RMW_CTRL(base, mask, value) (EWM_WR_CTRL(base, (EWM_RD_CTRL(base) & ~(mask)) | (value)))
+#define EWM_SET_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) |  (value)))
+#define EWM_CLR_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) & ~(value)))
+#define EWM_TOG_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual EWM_CTRL bitfields
+ */
+
+/*!
+ * @name Register EWM_CTRL, field EWMEN[0] (RW)
+ *
+ * This bit when set, enables the EWM module. This resets the EWM counter to
+ * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
+ * therefore it cannot be enabled until a reset occurs, due to the write-once
+ * nature of this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_EWMEN field. */
+#define EWM_RD_CTRL_EWMEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_EWMEN_MASK) >> EWM_CTRL_EWMEN_SHIFT)
+#define EWM_BRD_CTRL_EWMEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_EWMEN_SHIFT))
+
+/*! @brief Set the EWMEN field to a new value. */
+#define EWM_WR_CTRL_EWMEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_EWMEN_MASK, EWM_CTRL_EWMEN(value)))
+#define EWM_BWR_CTRL_EWMEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_EWMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field ASSIN[1] (RW)
+ *
+ * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
+ * inverts the assert state to a logic one.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_ASSIN field. */
+#define EWM_RD_CTRL_ASSIN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_ASSIN_MASK) >> EWM_CTRL_ASSIN_SHIFT)
+#define EWM_BRD_CTRL_ASSIN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_ASSIN_SHIFT))
+
+/*! @brief Set the ASSIN field to a new value. */
+#define EWM_WR_CTRL_ASSIN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_ASSIN_MASK, EWM_CTRL_ASSIN(value)))
+#define EWM_BWR_CTRL_ASSIN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_ASSIN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field INEN[2] (RW)
+ *
+ * This bit when set, enables the EWM_in port.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_INEN field. */
+#define EWM_RD_CTRL_INEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_INEN_MASK) >> EWM_CTRL_INEN_SHIFT)
+#define EWM_BRD_CTRL_INEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INEN_SHIFT))
+
+/*! @brief Set the INEN field to a new value. */
+#define EWM_WR_CTRL_INEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_INEN_MASK, EWM_CTRL_INEN(value)))
+#define EWM_BWR_CTRL_INEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field INTEN[3] (RW)
+ *
+ * This bit when set and EWM_out is asserted, an interrupt request is generated.
+ * To de-assert interrupt request, user should clear this bit by writing 0.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_INTEN field. */
+#define EWM_RD_CTRL_INTEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_INTEN_MASK) >> EWM_CTRL_INTEN_SHIFT)
+#define EWM_BRD_CTRL_INTEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INTEN_SHIFT))
+
+/*! @brief Set the INTEN field to a new value. */
+#define EWM_WR_CTRL_INTEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_INTEN_MASK, EWM_CTRL_INTEN(value)))
+#define EWM_BWR_CTRL_INTEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INTEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_SERV - Service Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_SERV - Service Register (WORZ)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERV register provides the interface from the CPU to the EWM module. It
+ * is write-only and reads of this register return zero.
+ */
+/*!
+ * @name Constants and macros for entire EWM_SERV register
+ */
+/*@{*/
+#define EWM_RD_SERV(base)        (EWM_SERV_REG(base))
+#define EWM_WR_SERV(base, value) (EWM_SERV_REG(base) = (value))
+#define EWM_RMW_SERV(base, mask, value) (EWM_WR_SERV(base, (EWM_RD_SERV(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_CMPL - Compare Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CMPL - Compare Low Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CMPL register is reset to zero after a CPU reset. This provides no
+ * minimum time for the CPU to service the EWM counter. This register can be written
+ * only once after a CPU reset. Writing this register more than once generates a
+ * bus transfer error.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CMPL register
+ */
+/*@{*/
+#define EWM_RD_CMPL(base)        (EWM_CMPL_REG(base))
+#define EWM_WR_CMPL(base, value) (EWM_CMPL_REG(base) = (value))
+#define EWM_RMW_CMPL(base, mask, value) (EWM_WR_CMPL(base, (EWM_RD_CMPL(base) & ~(mask)) | (value)))
+#define EWM_SET_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) |  (value)))
+#define EWM_CLR_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) & ~(value)))
+#define EWM_TOG_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_CMPH - Compare High Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CMPH - Compare High Register (RW)
+ *
+ * Reset value: 0xFFU
+ *
+ * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
+ * of 256 clocks time, for the CPU to service the EWM counter. This register can
+ * be written only once after a CPU reset. Writing this register more than once
+ * generates a bus transfer error. The valid values for CMPH are up to 0xFE
+ * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
+ * if EWM counter is greater than CMPH.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CMPH register
+ */
+/*@{*/
+#define EWM_RD_CMPH(base)        (EWM_CMPH_REG(base))
+#define EWM_WR_CMPH(base, value) (EWM_CMPH_REG(base) = (value))
+#define EWM_RMW_CMPH(base, mask, value) (EWM_WR_CMPH(base, (EWM_RD_CMPH(base) & ~(mask)) | (value)))
+#define EWM_SET_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) |  (value)))
+#define EWM_CLR_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) & ~(value)))
+#define EWM_TOG_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FB
+ *
+ * FlexBus external bus interface
+ *
+ * Registers defined in this header file:
+ * - FB_CSAR - Chip Select Address Register
+ * - FB_CSMR - Chip Select Mask Register
+ * - FB_CSCR - Chip Select Control Register
+ * - FB_CSPMCR - Chip Select port Multiplexing Control Register
+ */
+
+#define FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
+#define FB_IDX (0U) /*!< Instance number for FB. */
+
+/*******************************************************************************
+ * FB_CSAR - Chip Select Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSAR - Chip Select Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the associated chip-select's base address.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSAR register
+ */
+/*@{*/
+#define FB_RD_CSAR(base, index)  (FB_CSAR_REG(base, index))
+#define FB_WR_CSAR(base, index, value) (FB_CSAR_REG(base, index) = (value))
+#define FB_RMW_CSAR(base, index, mask, value) (FB_WR_CSAR(base, index, (FB_RD_CSAR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) |  (value)))
+#define FB_CLR_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) & ~(value)))
+#define FB_TOG_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSAR bitfields
+ */
+
+/*!
+ * @name Register FB_CSAR, field BA[31:16] (RW)
+ *
+ * Defines the base address for memory dedicated to the associated chip-select.
+ * BA is compared to bits 31-16 on the internal address bus to determine if the
+ * associated chip-select's memory is being accessed. Because the FlexBus module
+ * is one of the slaves connected to the crossbar switch, it is only accessible
+ * within a certain memory range. See the chip memory map for the applicable
+ * FlexBus "expansion" address range for which the chip-selects can be active. Set the
+ * CSARn and CSMRn registers appropriately before accessing this region.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSAR_BA field. */
+#define FB_RD_CSAR_BA(base, index) ((FB_CSAR_REG(base, index) & FB_CSAR_BA_MASK) >> FB_CSAR_BA_SHIFT)
+#define FB_BRD_CSAR_BA(base, index) (FB_RD_CSAR_BA(base, index))
+
+/*! @brief Set the BA field to a new value. */
+#define FB_WR_CSAR_BA(base, index, value) (FB_RMW_CSAR(base, index, FB_CSAR_BA_MASK, FB_CSAR_BA(value)))
+#define FB_BWR_CSAR_BA(base, index, value) (FB_WR_CSAR_BA(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSMR - Chip Select Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSMR - Chip Select Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the address mask and allowable access types for the associated
+ * chip-select.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSMR register
+ */
+/*@{*/
+#define FB_RD_CSMR(base, index)  (FB_CSMR_REG(base, index))
+#define FB_WR_CSMR(base, index, value) (FB_CSMR_REG(base, index) = (value))
+#define FB_RMW_CSMR(base, index, mask, value) (FB_WR_CSMR(base, index, (FB_RD_CSMR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) |  (value)))
+#define FB_CLR_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) & ~(value)))
+#define FB_TOG_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSMR bitfields
+ */
+
+/*!
+ * @name Register FB_CSMR, field V[0] (RW)
+ *
+ * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
+ * Programmed chip-selects do not assert until the V bit is 1b (except for
+ * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
+ * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
+ * select initialization sequence to allow other chip selects to function as
+ * programmed.
+ *
+ * Values:
+ * - 0b0 - Chip-select is invalid.
+ * - 0b1 - Chip-select is valid.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_V field. */
+#define FB_RD_CSMR_V(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_V_MASK) >> FB_CSMR_V_SHIFT)
+#define FB_BRD_CSMR_V(base, index) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_V_SHIFT))
+
+/*! @brief Set the V field to a new value. */
+#define FB_WR_CSMR_V(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_V_MASK, FB_CSMR_V(value)))
+#define FB_BWR_CSMR_V(base, index, value) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_V_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSMR, field WP[8] (RW)
+ *
+ * Controls write accesses to the address range in the corresponding CSAR.
+ *
+ * Values:
+ * - 0b0 - Write accesses are allowed.
+ * - 0b1 - Write accesses are not allowed. Attempting to write to the range of
+ *     addresses for which the WP bit is set results in a bus error termination of
+ *     the internal cycle and no external cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_WP field. */
+#define FB_RD_CSMR_WP(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_WP_MASK) >> FB_CSMR_WP_SHIFT)
+#define FB_BRD_CSMR_WP(base, index) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_WP_SHIFT))
+
+/*! @brief Set the WP field to a new value. */
+#define FB_WR_CSMR_WP(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_WP_MASK, FB_CSMR_WP(value)))
+#define FB_BWR_CSMR_WP(base, index, value) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_WP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSMR, field BAM[31:16] (RW)
+ *
+ * Defines the associated chip-select's block size by masking address bits.
+ *
+ * Values:
+ * - 0b0000000000000000 - The corresponding address bit in CSAR is used in the
+ *     chip-select decode.
+ * - 0b0000000000000001 - The corresponding address bit in CSAR is a don't care
+ *     in the chip-select decode.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_BAM field. */
+#define FB_RD_CSMR_BAM(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_BAM_MASK) >> FB_CSMR_BAM_SHIFT)
+#define FB_BRD_CSMR_BAM(base, index) (FB_RD_CSMR_BAM(base, index))
+
+/*! @brief Set the BAM field to a new value. */
+#define FB_WR_CSMR_BAM(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_BAM_MASK, FB_CSMR_BAM(value)))
+#define FB_BWR_CSMR_BAM(base, index, value) (FB_WR_CSMR_BAM(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSCR - Chip Select Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSCR - Chip Select Control Register (RW)
+ *
+ * Reset value: 0x003FFC00U
+ *
+ * Controls the auto-acknowledge, address setup and hold times, port size, burst
+ * capability, and number of wait states for the associated chip select. To
+ * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
+ * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
+ * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
+ * particular chip for information on the exact CSCR0 reset value.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSCR register
+ */
+/*@{*/
+#define FB_RD_CSCR(base, index)  (FB_CSCR_REG(base, index))
+#define FB_WR_CSCR(base, index, value) (FB_CSCR_REG(base, index) = (value))
+#define FB_RMW_CSCR(base, index, mask, value) (FB_WR_CSCR(base, index, (FB_RD_CSCR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) |  (value)))
+#define FB_CLR_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) & ~(value)))
+#define FB_TOG_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSCR, field BSTW[3] (RW)
+ *
+ * Specifies whether burst writes are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0b0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst writes. For example, a 32-bit write to an
+ *     8-bit port takes four byte writes.
+ * - 0b1 - Enabled. Enables burst write of data larger than the specified port
+ *     size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to
+ *     8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BSTW field. */
+#define FB_RD_CSCR_BSTW(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BSTW_MASK) >> FB_CSCR_BSTW_SHIFT)
+#define FB_BRD_CSCR_BSTW(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTW_SHIFT))
+
+/*! @brief Set the BSTW field to a new value. */
+#define FB_WR_CSCR_BSTW(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BSTW_MASK, FB_CSCR_BSTW(value)))
+#define FB_BWR_CSCR_BSTW(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BSTR[4] (RW)
+ *
+ * Specifies whether burst reads are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0b0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst reads. For example, a 32-bit read from an
+ *     8-bit port is broken into four 8-bit reads.
+ * - 0b1 - Enabled. Enables data burst reads larger than the specified port
+ *     size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
+ *     ports, and line reads from 8-, 16-, and 32-bit ports.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BSTR field. */
+#define FB_RD_CSCR_BSTR(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BSTR_MASK) >> FB_CSCR_BSTR_SHIFT)
+#define FB_BRD_CSCR_BSTR(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTR_SHIFT))
+
+/*! @brief Set the BSTR field to a new value. */
+#define FB_WR_CSCR_BSTR(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BSTR_MASK, FB_CSCR_BSTR(value)))
+#define FB_BWR_CSCR_BSTR(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BEM[5] (RW)
+ *
+ * Specifies whether the corresponding FB_BE is asserted for read accesses.
+ * Certain memories have byte enables that must be asserted during reads and writes.
+ * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
+ * of byte enable support for these SRAMs.
+ *
+ * Values:
+ * - 0b0 - FB_BE is asserted for data write only.
+ * - 0b1 - FB_BE is asserted for data read and write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BEM field. */
+#define FB_RD_CSCR_BEM(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BEM_MASK) >> FB_CSCR_BEM_SHIFT)
+#define FB_BRD_CSCR_BEM(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BEM_SHIFT))
+
+/*! @brief Set the BEM field to a new value. */
+#define FB_WR_CSCR_BEM(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BEM_MASK, FB_CSCR_BEM(value)))
+#define FB_BWR_CSCR_BEM(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BEM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field PS[7:6] (RW)
+ *
+ * Specifies the data port width of the associated chip-select, and determines
+ * where data is driven during write cycles and where data is sampled during read
+ * cycles.
+ *
+ * Values:
+ * - 0b00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
+ * - 0b01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24]
+ *     when BLS is 0b, or FB_D[7:0] when BLS is 1b.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_PS field. */
+#define FB_RD_CSCR_PS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_PS_MASK) >> FB_CSCR_PS_SHIFT)
+#define FB_BRD_CSCR_PS(base, index) (FB_RD_CSCR_PS(base, index))
+
+/*! @brief Set the PS field to a new value. */
+#define FB_WR_CSCR_PS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_PS_MASK, FB_CSCR_PS(value)))
+#define FB_BWR_CSCR_PS(base, index, value) (FB_WR_CSCR_PS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field AA[8] (RW)
+ *
+ * Asserts the internal transfer acknowledge for accesses specified by the
+ * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
+ * asserts an external FB_TA before the wait-state countdown asserts the
+ * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
+ * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
+ *
+ * Values:
+ * - 0b0 - Disabled. No internal transfer acknowledge is asserted and the cycle
+ *     is terminated externally.
+ * - 0b1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_AA field. */
+#define FB_RD_CSCR_AA(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_AA_MASK) >> FB_CSCR_AA_SHIFT)
+#define FB_BRD_CSCR_AA(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_AA_SHIFT))
+
+/*! @brief Set the AA field to a new value. */
+#define FB_WR_CSCR_AA(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_AA_MASK, FB_CSCR_AA(value)))
+#define FB_BWR_CSCR_AA(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_AA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BLS[9] (RW)
+ *
+ * Specifies if data on FB_AD appears left-aligned or right-aligned during the
+ * data phase of a FlexBus access.
+ *
+ * Values:
+ * - 0b0 - Not shifted. Data is left-aligned on FB_AD.
+ * - 0b1 - Shifted. Data is right-aligned on FB_AD.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BLS field. */
+#define FB_RD_CSCR_BLS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BLS_MASK) >> FB_CSCR_BLS_SHIFT)
+#define FB_BRD_CSCR_BLS(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BLS_SHIFT))
+
+/*! @brief Set the BLS field to a new value. */
+#define FB_WR_CSCR_BLS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BLS_MASK, FB_CSCR_BLS(value)))
+#define FB_BWR_CSCR_BLS(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field WS[15:10] (RW)
+ *
+ * Specifies the number of wait states inserted after FlexBus asserts the
+ * associated chip-select and before an internal transfer acknowledge is generated (WS
+ * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_WS field. */
+#define FB_RD_CSCR_WS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_WS_MASK) >> FB_CSCR_WS_SHIFT)
+#define FB_BRD_CSCR_WS(base, index) (FB_RD_CSCR_WS(base, index))
+
+/*! @brief Set the WS field to a new value. */
+#define FB_WR_CSCR_WS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_WS_MASK, FB_CSCR_WS(value)))
+#define FB_BWR_CSCR_WS(base, index, value) (FB_WR_CSCR_WS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field WRAH[17:16] (RW)
+ *
+ * Controls the address, data, and attribute hold time after the termination of
+ * a write cycle that hits in the associated chip-select's address space. The
+ * hold time applies only at the end of a transfer. Therefore, during a burst
+ * transfer or a transfer to a port size smaller than the transfer size, the hold time
+ * is only added after the last bus cycle.
+ *
+ * Values:
+ * - 0b00 - 1 cycle (default for all but FB_CS0 )
+ * - 0b01 - 2 cycles
+ * - 0b10 - 3 cycles
+ * - 0b11 - 4 cycles (default for FB_CS0 )
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_WRAH field. */
+#define FB_RD_CSCR_WRAH(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_WRAH_MASK) >> FB_CSCR_WRAH_SHIFT)
+#define FB_BRD_CSCR_WRAH(base, index) (FB_RD_CSCR_WRAH(base, index))
+
+/*! @brief Set the WRAH field to a new value. */
+#define FB_WR_CSCR_WRAH(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_WRAH_MASK, FB_CSCR_WRAH(value)))
+#define FB_BWR_CSCR_WRAH(base, index, value) (FB_WR_CSCR_WRAH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field RDAH[19:18] (RW)
+ *
+ * Controls the address and attribute hold time after the termination during a
+ * read cycle that hits in the associated chip-select's address space. The hold
+ * time applies only at the end of a transfer. Therefore, during a burst transfer
+ * or a transfer to a port size smaller than the transfer size, the hold time is
+ * only added after the last bus cycle. The number of cycles the address and
+ * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
+ *
+ * Values:
+ * - 0b00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
+ * - 0b01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
+ * - 0b10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
+ * - 0b11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_RDAH field. */
+#define FB_RD_CSCR_RDAH(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_RDAH_MASK) >> FB_CSCR_RDAH_SHIFT)
+#define FB_BRD_CSCR_RDAH(base, index) (FB_RD_CSCR_RDAH(base, index))
+
+/*! @brief Set the RDAH field to a new value. */
+#define FB_WR_CSCR_RDAH(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_RDAH_MASK, FB_CSCR_RDAH(value)))
+#define FB_BWR_CSCR_RDAH(base, index, value) (FB_WR_CSCR_RDAH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field ASET[21:20] (RW)
+ *
+ * Controls when the chip-select is asserted with respect to assertion of a
+ * valid address and attributes.
+ *
+ * Values:
+ * - 0b00 - Assert FB_CSn on the first rising clock edge after the address is
+ *     asserted (default for all but FB_CS0 ).
+ * - 0b01 - Assert FB_CSn on the second rising clock edge after the address is
+ *     asserted.
+ * - 0b10 - Assert FB_CSn on the third rising clock edge after the address is
+ *     asserted.
+ * - 0b11 - Assert FB_CSn on the fourth rising clock edge after the address is
+ *     asserted (default for FB_CS0 ).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_ASET field. */
+#define FB_RD_CSCR_ASET(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_ASET_MASK) >> FB_CSCR_ASET_SHIFT)
+#define FB_BRD_CSCR_ASET(base, index) (FB_RD_CSCR_ASET(base, index))
+
+/*! @brief Set the ASET field to a new value. */
+#define FB_WR_CSCR_ASET(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_ASET_MASK, FB_CSCR_ASET(value)))
+#define FB_BWR_CSCR_ASET(base, index, value) (FB_WR_CSCR_ASET(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field EXTS[22] (RW)
+ *
+ * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
+ * /FB_ALE is asserted.
+ *
+ * Values:
+ * - 0b0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
+ * - 0b1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive
+ *     clock edge after FB_CSn asserts.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_EXTS field. */
+#define FB_RD_CSCR_EXTS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_EXTS_MASK) >> FB_CSCR_EXTS_SHIFT)
+#define FB_BRD_CSCR_EXTS(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_EXTS_SHIFT))
+
+/*! @brief Set the EXTS field to a new value. */
+#define FB_WR_CSCR_EXTS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_EXTS_MASK, FB_CSCR_EXTS(value)))
+#define FB_BWR_CSCR_EXTS(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_EXTS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field SWSEN[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled. A number of wait states (specified by WS) are inserted
+ *     before an internal transfer acknowledge is generated for all transfers.
+ * - 0b1 - Enabled. A number of wait states (specified by SWS) are inserted
+ *     before an internal transfer acknowledge is generated for burst transfer
+ *     secondary terminations.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_SWSEN field. */
+#define FB_RD_CSCR_SWSEN(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_SWSEN_MASK) >> FB_CSCR_SWSEN_SHIFT)
+#define FB_BRD_CSCR_SWSEN(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_SWSEN_SHIFT))
+
+/*! @brief Set the SWSEN field to a new value. */
+#define FB_WR_CSCR_SWSEN(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_SWSEN_MASK, FB_CSCR_SWSEN(value)))
+#define FB_BWR_CSCR_SWSEN(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_SWSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field SWS[31:26] (RW)
+ *
+ * Used only when the SWSEN bit is 1b. Specifies the number of wait states
+ * inserted before an internal transfer acknowledge is generated for a burst transfer
+ * (except for the first termination, which is controlled by WS).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_SWS field. */
+#define FB_RD_CSCR_SWS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_SWS_MASK) >> FB_CSCR_SWS_SHIFT)
+#define FB_BRD_CSCR_SWS(base, index) (FB_RD_CSCR_SWS(base, index))
+
+/*! @brief Set the SWS field to a new value. */
+#define FB_WR_CSCR_SWS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_SWS_MASK, FB_CSCR_SWS(value)))
+#define FB_BWR_CSCR_SWS(base, index, value) (FB_WR_CSCR_SWS(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSPMCR - Chip Select port Multiplexing Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
+ * do any of the following: Write to a reserved address Write to a reserved
+ * field in this register, or Access this register using a size other than 32 bits.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSPMCR register
+ */
+/*@{*/
+#define FB_RD_CSPMCR(base)       (FB_CSPMCR_REG(base))
+#define FB_WR_CSPMCR(base, value) (FB_CSPMCR_REG(base) = (value))
+#define FB_RMW_CSPMCR(base, mask, value) (FB_WR_CSPMCR(base, (FB_RD_CSPMCR(base) & ~(mask)) | (value)))
+#define FB_SET_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) |  (value)))
+#define FB_CLR_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) & ~(value)))
+#define FB_TOG_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSPMCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
+ *
+ * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
+ * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
+ * bus hangs during a transfer.
+ *
+ * Values:
+ * - 0b0000 - FB_TA
+ * - 0b0001 - FB_CS3 . You must also write 1b to CSCR[AA].
+ * - 0b0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
+#define FB_RD_CSPMCR_GROUP5(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP5_MASK) >> FB_CSPMCR_GROUP5_SHIFT)
+#define FB_BRD_CSPMCR_GROUP5(base) (FB_RD_CSPMCR_GROUP5(base))
+
+/*! @brief Set the GROUP5 field to a new value. */
+#define FB_WR_CSPMCR_GROUP5(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP5_MASK, FB_CSPMCR_GROUP5(value)))
+#define FB_BWR_CSPMCR_GROUP5(base, value) (FB_WR_CSPMCR_GROUP5(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
+ *
+ * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_TBST
+ * - 0b0001 - FB_CS2
+ * - 0b0010 - FB_BE_15_8
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
+#define FB_RD_CSPMCR_GROUP4(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP4_MASK) >> FB_CSPMCR_GROUP4_SHIFT)
+#define FB_BRD_CSPMCR_GROUP4(base) (FB_RD_CSPMCR_GROUP4(base))
+
+/*! @brief Set the GROUP4 field to a new value. */
+#define FB_WR_CSPMCR_GROUP4(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP4_MASK, FB_CSPMCR_GROUP4(value)))
+#define FB_BWR_CSPMCR_GROUP4(base, value) (FB_WR_CSPMCR_GROUP4(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
+ *
+ * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_CS5
+ * - 0b0001 - FB_TSIZ1
+ * - 0b0010 - FB_BE_23_16
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
+#define FB_RD_CSPMCR_GROUP3(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP3_MASK) >> FB_CSPMCR_GROUP3_SHIFT)
+#define FB_BRD_CSPMCR_GROUP3(base) (FB_RD_CSPMCR_GROUP3(base))
+
+/*! @brief Set the GROUP3 field to a new value. */
+#define FB_WR_CSPMCR_GROUP3(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP3_MASK, FB_CSPMCR_GROUP3(value)))
+#define FB_BWR_CSPMCR_GROUP3(base, value) (FB_WR_CSPMCR_GROUP3(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
+ *
+ * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_CS4
+ * - 0b0001 - FB_TSIZ0
+ * - 0b0010 - FB_BE_31_24
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
+#define FB_RD_CSPMCR_GROUP2(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP2_MASK) >> FB_CSPMCR_GROUP2_SHIFT)
+#define FB_BRD_CSPMCR_GROUP2(base) (FB_RD_CSPMCR_GROUP2(base))
+
+/*! @brief Set the GROUP2 field to a new value. */
+#define FB_WR_CSPMCR_GROUP2(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP2_MASK, FB_CSPMCR_GROUP2(value)))
+#define FB_BWR_CSPMCR_GROUP2(base, value) (FB_WR_CSPMCR_GROUP2(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
+ *
+ * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
+ *
+ * Values:
+ * - 0b0000 - FB_ALE
+ * - 0b0001 - FB_CS1
+ * - 0b0010 - FB_TS
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
+#define FB_RD_CSPMCR_GROUP1(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP1_MASK) >> FB_CSPMCR_GROUP1_SHIFT)
+#define FB_BRD_CSPMCR_GROUP1(base) (FB_RD_CSPMCR_GROUP1(base))
+
+/*! @brief Set the GROUP1 field to a new value. */
+#define FB_WR_CSPMCR_GROUP1(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP1_MASK, FB_CSPMCR_GROUP1(value)))
+#define FB_BWR_CSPMCR_GROUP1(base, value) (FB_WR_CSPMCR_GROUP1(base, value))
+/*@}*/
+
+/*
+ * MK64F12 FMC
+ *
+ * Flash Memory Controller
+ *
+ * Registers defined in this header file:
+ * - FMC_PFAPR - Flash Access Protection Register
+ * - FMC_PFB0CR - Flash Bank 0 Control Register
+ * - FMC_PFB1CR - Flash Bank 1 Control Register
+ * - FMC_TAGVDW0S - Cache Tag Storage
+ * - FMC_TAGVDW1S - Cache Tag Storage
+ * - FMC_TAGVDW2S - Cache Tag Storage
+ * - FMC_TAGVDW3S - Cache Tag Storage
+ * - FMC_DATA_U - Cache Data Storage (upper word)
+ * - FMC_DATA_L - Cache Data Storage (lower word)
+ */
+
+#define FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */
+#define FMC_IDX (0U) /*!< Instance number for FMC. */
+
+/*******************************************************************************
+ * FMC_PFAPR - Flash Access Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFAPR - Flash Access Protection Register (RW)
+ *
+ * Reset value: 0x00F8003FU
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFAPR register
+ */
+/*@{*/
+#define FMC_RD_PFAPR(base)       (FMC_PFAPR_REG(base))
+#define FMC_WR_PFAPR(base, value) (FMC_PFAPR_REG(base) = (value))
+#define FMC_RMW_PFAPR(base, mask, value) (FMC_WR_PFAPR(base, (FMC_RD_PFAPR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) |  (value)))
+#define FMC_CLR_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) & ~(value)))
+#define FMC_TOG_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFAPR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M0AP field. */
+#define FMC_RD_PFAPR_M0AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M0AP_MASK) >> FMC_PFAPR_M0AP_SHIFT)
+#define FMC_BRD_PFAPR_M0AP(base) (FMC_RD_PFAPR_M0AP(base))
+
+/*! @brief Set the M0AP field to a new value. */
+#define FMC_WR_PFAPR_M0AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M0AP_MASK, FMC_PFAPR_M0AP(value)))
+#define FMC_BWR_PFAPR_M0AP(base, value) (FMC_WR_PFAPR_M0AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M1AP field. */
+#define FMC_RD_PFAPR_M1AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M1AP_MASK) >> FMC_PFAPR_M1AP_SHIFT)
+#define FMC_BRD_PFAPR_M1AP(base) (FMC_RD_PFAPR_M1AP(base))
+
+/*! @brief Set the M1AP field to a new value. */
+#define FMC_WR_PFAPR_M1AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M1AP_MASK, FMC_PFAPR_M1AP(value)))
+#define FMC_BWR_PFAPR_M1AP(base, value) (FMC_WR_PFAPR_M1AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M2AP field. */
+#define FMC_RD_PFAPR_M2AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M2AP_MASK) >> FMC_PFAPR_M2AP_SHIFT)
+#define FMC_BRD_PFAPR_M2AP(base) (FMC_RD_PFAPR_M2AP(base))
+
+/*! @brief Set the M2AP field to a new value. */
+#define FMC_WR_PFAPR_M2AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M2AP_MASK, FMC_PFAPR_M2AP(value)))
+#define FMC_BWR_PFAPR_M2AP(base, value) (FMC_WR_PFAPR_M2AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M3AP field. */
+#define FMC_RD_PFAPR_M3AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M3AP_MASK) >> FMC_PFAPR_M3AP_SHIFT)
+#define FMC_BRD_PFAPR_M3AP(base) (FMC_RD_PFAPR_M3AP(base))
+
+/*! @brief Set the M3AP field to a new value. */
+#define FMC_WR_PFAPR_M3AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M3AP_MASK, FMC_PFAPR_M3AP(value)))
+#define FMC_BWR_PFAPR_M3AP(base, value) (FMC_WR_PFAPR_M3AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M4AP field. */
+#define FMC_RD_PFAPR_M4AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M4AP_MASK) >> FMC_PFAPR_M4AP_SHIFT)
+#define FMC_BRD_PFAPR_M4AP(base) (FMC_RD_PFAPR_M4AP(base))
+
+/*! @brief Set the M4AP field to a new value. */
+#define FMC_WR_PFAPR_M4AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M4AP_MASK, FMC_PFAPR_M4AP(value)))
+#define FMC_BWR_PFAPR_M4AP(base, value) (FMC_WR_PFAPR_M4AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M5AP field. */
+#define FMC_RD_PFAPR_M5AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M5AP_MASK) >> FMC_PFAPR_M5AP_SHIFT)
+#define FMC_BRD_PFAPR_M5AP(base) (FMC_RD_PFAPR_M5AP(base))
+
+/*! @brief Set the M5AP field to a new value. */
+#define FMC_WR_PFAPR_M5AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M5AP_MASK, FMC_PFAPR_M5AP(value)))
+#define FMC_BWR_PFAPR_M5AP(base, value) (FMC_WR_PFAPR_M5AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M6AP field. */
+#define FMC_RD_PFAPR_M6AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M6AP_MASK) >> FMC_PFAPR_M6AP_SHIFT)
+#define FMC_BRD_PFAPR_M6AP(base) (FMC_RD_PFAPR_M6AP(base))
+
+/*! @brief Set the M6AP field to a new value. */
+#define FMC_WR_PFAPR_M6AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M6AP_MASK, FMC_PFAPR_M6AP(value)))
+#define FMC_BWR_PFAPR_M6AP(base, value) (FMC_WR_PFAPR_M6AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master.
+ * - 0b01 - Only read accesses may be performed by this master.
+ * - 0b10 - Only write accesses may be performed by this master.
+ * - 0b11 - Both read and write accesses may be performed by this master.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M7AP field. */
+#define FMC_RD_PFAPR_M7AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M7AP_MASK) >> FMC_PFAPR_M7AP_SHIFT)
+#define FMC_BRD_PFAPR_M7AP(base) (FMC_RD_PFAPR_M7AP(base))
+
+/*! @brief Set the M7AP field to a new value. */
+#define FMC_WR_PFAPR_M7AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M7AP_MASK, FMC_PFAPR_M7AP(value)))
+#define FMC_BWR_PFAPR_M7AP(base, value) (FMC_WR_PFAPR_M7AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M0PFD[16] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M0PFD field. */
+#define FMC_RD_PFAPR_M0PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M0PFD_MASK) >> FMC_PFAPR_M0PFD_SHIFT)
+#define FMC_BRD_PFAPR_M0PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M0PFD_SHIFT))
+
+/*! @brief Set the M0PFD field to a new value. */
+#define FMC_WR_PFAPR_M0PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M0PFD_MASK, FMC_PFAPR_M0PFD(value)))
+#define FMC_BWR_PFAPR_M0PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M0PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M1PFD[17] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M1PFD field. */
+#define FMC_RD_PFAPR_M1PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M1PFD_MASK) >> FMC_PFAPR_M1PFD_SHIFT)
+#define FMC_BRD_PFAPR_M1PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M1PFD_SHIFT))
+
+/*! @brief Set the M1PFD field to a new value. */
+#define FMC_WR_PFAPR_M1PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M1PFD_MASK, FMC_PFAPR_M1PFD(value)))
+#define FMC_BWR_PFAPR_M1PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M1PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M2PFD[18] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M2PFD field. */
+#define FMC_RD_PFAPR_M2PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M2PFD_MASK) >> FMC_PFAPR_M2PFD_SHIFT)
+#define FMC_BRD_PFAPR_M2PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M2PFD_SHIFT))
+
+/*! @brief Set the M2PFD field to a new value. */
+#define FMC_WR_PFAPR_M2PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M2PFD_MASK, FMC_PFAPR_M2PFD(value)))
+#define FMC_BWR_PFAPR_M2PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M2PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M3PFD[19] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M3PFD field. */
+#define FMC_RD_PFAPR_M3PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M3PFD_MASK) >> FMC_PFAPR_M3PFD_SHIFT)
+#define FMC_BRD_PFAPR_M3PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M3PFD_SHIFT))
+
+/*! @brief Set the M3PFD field to a new value. */
+#define FMC_WR_PFAPR_M3PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M3PFD_MASK, FMC_PFAPR_M3PFD(value)))
+#define FMC_BWR_PFAPR_M3PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M3PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M4PFD[20] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M4PFD field. */
+#define FMC_RD_PFAPR_M4PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M4PFD_MASK) >> FMC_PFAPR_M4PFD_SHIFT)
+#define FMC_BRD_PFAPR_M4PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M4PFD_SHIFT))
+
+/*! @brief Set the M4PFD field to a new value. */
+#define FMC_WR_PFAPR_M4PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M4PFD_MASK, FMC_PFAPR_M4PFD(value)))
+#define FMC_BWR_PFAPR_M4PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M4PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M5PFD[21] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M5PFD field. */
+#define FMC_RD_PFAPR_M5PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M5PFD_MASK) >> FMC_PFAPR_M5PFD_SHIFT)
+#define FMC_BRD_PFAPR_M5PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M5PFD_SHIFT))
+
+/*! @brief Set the M5PFD field to a new value. */
+#define FMC_WR_PFAPR_M5PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M5PFD_MASK, FMC_PFAPR_M5PFD(value)))
+#define FMC_BWR_PFAPR_M5PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M5PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M6PFD[22] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M6PFD field. */
+#define FMC_RD_PFAPR_M6PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M6PFD_MASK) >> FMC_PFAPR_M6PFD_SHIFT)
+#define FMC_BRD_PFAPR_M6PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M6PFD_SHIFT))
+
+/*! @brief Set the M6PFD field to a new value. */
+#define FMC_WR_PFAPR_M6PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M6PFD_MASK, FMC_PFAPR_M6PFD(value)))
+#define FMC_BWR_PFAPR_M6PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M6PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M7PFD[23] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M7PFD field. */
+#define FMC_RD_PFAPR_M7PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M7PFD_MASK) >> FMC_PFAPR_M7PFD_SHIFT)
+#define FMC_BRD_PFAPR_M7PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M7PFD_SHIFT))
+
+/*! @brief Set the M7PFD field to a new value. */
+#define FMC_WR_PFAPR_M7PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M7PFD_MASK, FMC_PFAPR_M7PFD(value)))
+#define FMC_BWR_PFAPR_M7PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M7PFD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_PFB0CR - Flash Bank 0 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFB0CR - Flash Bank 0 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFB0CR register
+ */
+/*@{*/
+#define FMC_RD_PFB0CR(base)      (FMC_PFB0CR_REG(base))
+#define FMC_WR_PFB0CR(base, value) (FMC_PFB0CR_REG(base) = (value))
+#define FMC_RMW_PFB0CR(base, mask, value) (FMC_WR_PFB0CR(base, (FMC_RD_PFB0CR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) |  (value)))
+#define FMC_CLR_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) & ~(value)))
+#define FMC_TOG_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFB0CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry page buffer is enabled in response
+ * to flash read accesses. Its operation is independent from bank 1's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0b0 - Single entry buffer is disabled.
+ * - 0b1 - Single entry buffer is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */
+#define FMC_RD_PFB0CR_B0SEBE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0SEBE_MASK) >> FMC_PFB0CR_B0SEBE_SHIFT)
+#define FMC_BRD_PFB0CR_B0SEBE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0SEBE_SHIFT))
+
+/*! @brief Set the B0SEBE field to a new value. */
+#define FMC_WR_PFB0CR_B0SEBE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0SEBE_MASK, FMC_PFB0CR_B0SEBE(value)))
+#define FMC_BWR_PFB0CR_B0SEBE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0SEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to instruction fetches.
+ * - 0b1 - Enable prefetches in response to instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */
+#define FMC_RD_PFB0CR_B0IPE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0IPE_MASK) >> FMC_PFB0CR_B0IPE_SHIFT)
+#define FMC_BRD_PFB0CR_B0IPE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0IPE_SHIFT))
+
+/*! @brief Set the B0IPE field to a new value. */
+#define FMC_WR_PFB0CR_B0IPE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0IPE_MASK, FMC_PFB0CR_B0IPE(value)))
+#define FMC_BWR_PFB0CR_B0IPE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0IPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to data references.
+ * - 0b1 - Enable prefetches in response to data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */
+#define FMC_RD_PFB0CR_B0DPE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0DPE_MASK) >> FMC_PFB0CR_B0DPE_SHIFT)
+#define FMC_BRD_PFB0CR_B0DPE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DPE_SHIFT))
+
+/*! @brief Set the B0DPE field to a new value. */
+#define FMC_WR_PFB0CR_B0DPE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0DPE_MASK, FMC_PFB0CR_B0DPE(value)))
+#define FMC_BWR_PFB0CR_B0DPE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache instruction fetches.
+ * - 0b1 - Cache instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */
+#define FMC_RD_PFB0CR_B0ICE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0ICE_MASK) >> FMC_PFB0CR_B0ICE_SHIFT)
+#define FMC_BRD_PFB0CR_B0ICE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0ICE_SHIFT))
+
+/*! @brief Set the B0ICE field to a new value. */
+#define FMC_WR_PFB0CR_B0ICE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0ICE_MASK, FMC_PFB0CR_B0ICE(value)))
+#define FMC_BWR_PFB0CR_B0ICE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0ICE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache data references.
+ * - 0b1 - Cache data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */
+#define FMC_RD_PFB0CR_B0DCE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0DCE_MASK) >> FMC_PFB0CR_B0DCE_SHIFT)
+#define FMC_BRD_PFB0CR_B0DCE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DCE_SHIFT))
+
+/*! @brief Set the B0DCE field to a new value. */
+#define FMC_WR_PFB0CR_B0DCE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0DCE_MASK, FMC_PFB0CR_B0DCE(value)))
+#define FMC_BWR_PFB0CR_B0DCE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
+ *
+ * This 3-bit field defines the replacement algorithm for accesses that are
+ * cached.
+ *
+ * Values:
+ * - 0b000 - LRU replacement algorithm per set across all four ways
+ * - 0b001 - Reserved
+ * - 0b010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
+ * - 0b011 - Independent LRU with ways [0-2] for ifetches, [3] for data
+ * - 0b1xx - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_CRC field. */
+#define FMC_RD_PFB0CR_CRC(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_CRC_MASK) >> FMC_PFB0CR_CRC_SHIFT)
+#define FMC_BRD_PFB0CR_CRC(base) (FMC_RD_PFB0CR_CRC(base))
+
+/*! @brief Set the CRC field to a new value. */
+#define FMC_WR_PFB0CR_CRC(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CRC_MASK, FMC_PFB0CR_CRC(value)))
+#define FMC_BWR_PFB0CR_CRC(base, value) (FMC_WR_PFB0CR_CRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 0 memory.
+ *
+ * Values:
+ * - 0b00 - 32 bits
+ * - 0b01 - 64 bits
+ * - 0b10 - 128 bits
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0MW field. */
+#define FMC_RD_PFB0CR_B0MW(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0MW_MASK) >> FMC_PFB0CR_B0MW_SHIFT)
+#define FMC_BRD_PFB0CR_B0MW(base) (FMC_RD_PFB0CR_B0MW(base))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
+ *
+ * This bit determines if the FMC's prefetch speculation buffer and the single
+ * entry page buffer are to be invalidated (cleared). When this bit is written,
+ * the speculation buffer and single entry buffer are immediately cleared. This bit
+ * always reads as zero.
+ *
+ * Values:
+ * - 0b0 - Speculation buffer and single entry buffer are not affected.
+ * - 0b1 - Invalidate (clear) speculation buffer and single entry buffer.
+ */
+/*@{*/
+/*! @brief Set the S_B_INV field to a new value. */
+#define FMC_WR_PFB0CR_S_B_INV(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_S_B_INV_MASK, FMC_PFB0CR_S_B_INV(value)))
+#define FMC_BWR_PFB0CR_S_B_INV(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_S_B_INV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
+ *
+ * These bits determine if the given cache way is to be invalidated (cleared).
+ * When a bit within this field is written, the corresponding cache way is
+ * immediately invalidated: the way's tag, data, and valid contents are cleared. This
+ * field always reads as zero. Cache invalidation takes precedence over locking.
+ * The cache is invalidated by system reset. System software is required to
+ * maintain memory coherency when any segment of the flash memory is programmed or
+ * erased. Accordingly, cache invalidations must occur after a programming or erase
+ * event is completed and before the new memory image is accessed. The bit setting
+ * definitions are for each bit in the field.
+ *
+ * Values:
+ * - 0b0000 - No cache way invalidation for the corresponding cache
+ * - 0b0001 - Invalidate cache way for the corresponding cache: clear the tag,
+ *     data, and vld bits of ways selected
+ */
+/*@{*/
+/*! @brief Set the CINV_WAY field to a new value. */
+#define FMC_WR_PFB0CR_CINV_WAY(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY(value)))
+#define FMC_BWR_PFB0CR_CINV_WAY(base, value) (FMC_WR_PFB0CR_CINV_WAY(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
+ *
+ * These bits determine if the given cache way is locked such that its contents
+ * will not be displaced by future misses. The bit setting definitions are for
+ * each bit in the field.
+ *
+ * Values:
+ * - 0b0000 - Cache way is unlocked and may be displaced
+ * - 0b0001 - Cache way is locked and its contents are not displaced
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */
+#define FMC_RD_PFB0CR_CLCK_WAY(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_CLCK_WAY_MASK) >> FMC_PFB0CR_CLCK_WAY_SHIFT)
+#define FMC_BRD_PFB0CR_CLCK_WAY(base) (FMC_RD_PFB0CR_CLCK_WAY(base))
+
+/*! @brief Set the CLCK_WAY field to a new value. */
+#define FMC_WR_PFB0CR_CLCK_WAY(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CLCK_WAY_MASK, FMC_PFB0CR_CLCK_WAY(value)))
+#define FMC_BWR_PFB0CR_CLCK_WAY(base, value) (FMC_WR_PFB0CR_CLCK_WAY(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 0 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */
+#define FMC_RD_PFB0CR_B0RWSC(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0RWSC_MASK) >> FMC_PFB0CR_B0RWSC_SHIFT)
+#define FMC_BRD_PFB0CR_B0RWSC(base) (FMC_RD_PFB0CR_B0RWSC(base))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_PFB1CR - Flash Bank 1 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFB1CR - Flash Bank 1 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ *
+ * This register has a format similar to that for PFB0CR, except it controls the
+ * operation of flash bank 1, and the "global" cache control fields are empty.
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFB1CR register
+ */
+/*@{*/
+#define FMC_RD_PFB1CR(base)      (FMC_PFB1CR_REG(base))
+#define FMC_WR_PFB1CR(base, value) (FMC_PFB1CR_REG(base) = (value))
+#define FMC_RMW_PFB1CR(base, mask, value) (FMC_WR_PFB1CR(base, (FMC_RD_PFB1CR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) |  (value)))
+#define FMC_CLR_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) & ~(value)))
+#define FMC_TOG_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFB1CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry buffer is enabled in response to
+ * flash read accesses. Its operation is independent from bank 0's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0b0 - Single entry buffer is disabled.
+ * - 0b1 - Single entry buffer is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */
+#define FMC_RD_PFB1CR_B1SEBE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1SEBE_MASK) >> FMC_PFB1CR_B1SEBE_SHIFT)
+#define FMC_BRD_PFB1CR_B1SEBE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1SEBE_SHIFT))
+
+/*! @brief Set the B1SEBE field to a new value. */
+#define FMC_WR_PFB1CR_B1SEBE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1SEBE_MASK, FMC_PFB1CR_B1SEBE(value)))
+#define FMC_BWR_PFB1CR_B1SEBE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1SEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to instruction fetches.
+ * - 0b1 - Enable prefetches in response to instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */
+#define FMC_RD_PFB1CR_B1IPE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1IPE_MASK) >> FMC_PFB1CR_B1IPE_SHIFT)
+#define FMC_BRD_PFB1CR_B1IPE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1IPE_SHIFT))
+
+/*! @brief Set the B1IPE field to a new value. */
+#define FMC_WR_PFB1CR_B1IPE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1IPE_MASK, FMC_PFB1CR_B1IPE(value)))
+#define FMC_BWR_PFB1CR_B1IPE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1IPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to data references.
+ * - 0b1 - Enable prefetches in response to data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */
+#define FMC_RD_PFB1CR_B1DPE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1DPE_MASK) >> FMC_PFB1CR_B1DPE_SHIFT)
+#define FMC_BRD_PFB1CR_B1DPE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DPE_SHIFT))
+
+/*! @brief Set the B1DPE field to a new value. */
+#define FMC_WR_PFB1CR_B1DPE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1DPE_MASK, FMC_PFB1CR_B1DPE(value)))
+#define FMC_BWR_PFB1CR_B1DPE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache instruction fetches.
+ * - 0b1 - Cache instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */
+#define FMC_RD_PFB1CR_B1ICE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1ICE_MASK) >> FMC_PFB1CR_B1ICE_SHIFT)
+#define FMC_BRD_PFB1CR_B1ICE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1ICE_SHIFT))
+
+/*! @brief Set the B1ICE field to a new value. */
+#define FMC_WR_PFB1CR_B1ICE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1ICE_MASK, FMC_PFB1CR_B1ICE(value)))
+#define FMC_BWR_PFB1CR_B1ICE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1ICE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache data references.
+ * - 0b1 - Cache data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */
+#define FMC_RD_PFB1CR_B1DCE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1DCE_MASK) >> FMC_PFB1CR_B1DCE_SHIFT)
+#define FMC_BRD_PFB1CR_B1DCE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DCE_SHIFT))
+
+/*! @brief Set the B1DCE field to a new value. */
+#define FMC_WR_PFB1CR_B1DCE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1DCE_MASK, FMC_PFB1CR_B1DCE(value)))
+#define FMC_BWR_PFB1CR_B1DCE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 1 memory.
+ *
+ * Values:
+ * - 0b00 - 32 bits
+ * - 0b01 - 64 bits
+ * - 0b10 - 128 bits
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1MW field. */
+#define FMC_RD_PFB1CR_B1MW(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1MW_MASK) >> FMC_PFB1CR_B1MW_SHIFT)
+#define FMC_BRD_PFB1CR_B1MW(base) (FMC_RD_PFB1CR_B1MW(base))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 1 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */
+#define FMC_RD_PFB1CR_B1RWSC(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1RWSC_MASK) >> FMC_PFB1CR_B1RWSC_SHIFT)
+#define FMC_BRD_PFB1CR_B1RWSC(base) (FMC_RD_PFB1CR_B1RWSC(base))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW0S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW0S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW0S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW0S(base, index) (FMC_TAGVDW0S_REG(base, index))
+#define FMC_WR_TAGVDW0S(base, index, value) (FMC_TAGVDW0S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW0S(base, index, mask, value) (FMC_WR_TAGVDW0S(base, index, (FMC_RD_TAGVDW0S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW0S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW0S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW0S_valid field. */
+#define FMC_RD_TAGVDW0S_valid(base, index) ((FMC_TAGVDW0S_REG(base, index) & FMC_TAGVDW0S_valid_MASK) >> FMC_TAGVDW0S_valid_SHIFT)
+#define FMC_BRD_TAGVDW0S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW0S_REG(base, index), FMC_TAGVDW0S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW0S_valid(base, index, value) (FMC_RMW_TAGVDW0S(base, index, FMC_TAGVDW0S_valid_MASK, FMC_TAGVDW0S_valid(value)))
+#define FMC_BWR_TAGVDW0S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW0S_REG(base, index), FMC_TAGVDW0S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW0S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW0S_tag field. */
+#define FMC_RD_TAGVDW0S_tag(base, index) ((FMC_TAGVDW0S_REG(base, index) & FMC_TAGVDW0S_tag_MASK) >> FMC_TAGVDW0S_tag_SHIFT)
+#define FMC_BRD_TAGVDW0S_tag(base, index) (FMC_RD_TAGVDW0S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW0S_tag(base, index, value) (FMC_RMW_TAGVDW0S(base, index, FMC_TAGVDW0S_tag_MASK, FMC_TAGVDW0S_tag(value)))
+#define FMC_BWR_TAGVDW0S_tag(base, index, value) (FMC_WR_TAGVDW0S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW1S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW1S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW1S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW1S(base, index) (FMC_TAGVDW1S_REG(base, index))
+#define FMC_WR_TAGVDW1S(base, index, value) (FMC_TAGVDW1S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW1S(base, index, mask, value) (FMC_WR_TAGVDW1S(base, index, (FMC_RD_TAGVDW1S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW1S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW1S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW1S_valid field. */
+#define FMC_RD_TAGVDW1S_valid(base, index) ((FMC_TAGVDW1S_REG(base, index) & FMC_TAGVDW1S_valid_MASK) >> FMC_TAGVDW1S_valid_SHIFT)
+#define FMC_BRD_TAGVDW1S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW1S_REG(base, index), FMC_TAGVDW1S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW1S_valid(base, index, value) (FMC_RMW_TAGVDW1S(base, index, FMC_TAGVDW1S_valid_MASK, FMC_TAGVDW1S_valid(value)))
+#define FMC_BWR_TAGVDW1S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW1S_REG(base, index), FMC_TAGVDW1S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW1S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW1S_tag field. */
+#define FMC_RD_TAGVDW1S_tag(base, index) ((FMC_TAGVDW1S_REG(base, index) & FMC_TAGVDW1S_tag_MASK) >> FMC_TAGVDW1S_tag_SHIFT)
+#define FMC_BRD_TAGVDW1S_tag(base, index) (FMC_RD_TAGVDW1S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW1S_tag(base, index, value) (FMC_RMW_TAGVDW1S(base, index, FMC_TAGVDW1S_tag_MASK, FMC_TAGVDW1S_tag(value)))
+#define FMC_BWR_TAGVDW1S_tag(base, index, value) (FMC_WR_TAGVDW1S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW2S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW2S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW2S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW2S(base, index) (FMC_TAGVDW2S_REG(base, index))
+#define FMC_WR_TAGVDW2S(base, index, value) (FMC_TAGVDW2S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW2S(base, index, mask, value) (FMC_WR_TAGVDW2S(base, index, (FMC_RD_TAGVDW2S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW2S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW2S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW2S_valid field. */
+#define FMC_RD_TAGVDW2S_valid(base, index) ((FMC_TAGVDW2S_REG(base, index) & FMC_TAGVDW2S_valid_MASK) >> FMC_TAGVDW2S_valid_SHIFT)
+#define FMC_BRD_TAGVDW2S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW2S_REG(base, index), FMC_TAGVDW2S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW2S_valid(base, index, value) (FMC_RMW_TAGVDW2S(base, index, FMC_TAGVDW2S_valid_MASK, FMC_TAGVDW2S_valid(value)))
+#define FMC_BWR_TAGVDW2S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW2S_REG(base, index), FMC_TAGVDW2S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW2S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW2S_tag field. */
+#define FMC_RD_TAGVDW2S_tag(base, index) ((FMC_TAGVDW2S_REG(base, index) & FMC_TAGVDW2S_tag_MASK) >> FMC_TAGVDW2S_tag_SHIFT)
+#define FMC_BRD_TAGVDW2S_tag(base, index) (FMC_RD_TAGVDW2S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW2S_tag(base, index, value) (FMC_RMW_TAGVDW2S(base, index, FMC_TAGVDW2S_tag_MASK, FMC_TAGVDW2S_tag(value)))
+#define FMC_BWR_TAGVDW2S_tag(base, index, value) (FMC_WR_TAGVDW2S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW3S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW3S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW3S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW3S(base, index) (FMC_TAGVDW3S_REG(base, index))
+#define FMC_WR_TAGVDW3S(base, index, value) (FMC_TAGVDW3S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW3S(base, index, mask, value) (FMC_WR_TAGVDW3S(base, index, (FMC_RD_TAGVDW3S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW3S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW3S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW3S_valid field. */
+#define FMC_RD_TAGVDW3S_valid(base, index) ((FMC_TAGVDW3S_REG(base, index) & FMC_TAGVDW3S_valid_MASK) >> FMC_TAGVDW3S_valid_SHIFT)
+#define FMC_BRD_TAGVDW3S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW3S_REG(base, index), FMC_TAGVDW3S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW3S_valid(base, index, value) (FMC_RMW_TAGVDW3S(base, index, FMC_TAGVDW3S_valid_MASK, FMC_TAGVDW3S_valid(value)))
+#define FMC_BWR_TAGVDW3S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW3S_REG(base, index), FMC_TAGVDW3S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW3S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW3S_tag field. */
+#define FMC_RD_TAGVDW3S_tag(base, index) ((FMC_TAGVDW3S_REG(base, index) & FMC_TAGVDW3S_tag_MASK) >> FMC_TAGVDW3S_tag_SHIFT)
+#define FMC_BRD_TAGVDW3S_tag(base, index) (FMC_RD_TAGVDW3S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW3S_tag(base, index, value) (FMC_RMW_TAGVDW3S(base, index, FMC_TAGVDW3S_tag_MASK, FMC_TAGVDW3S_tag(value)))
+#define FMC_BWR_TAGVDW3S_tag(base, index, value) (FMC_WR_TAGVDW3S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_DATA_U - Cache Data Storage (upper word)
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_DATA_U - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_DATA_U register
+ */
+/*@{*/
+#define FMC_RD_DATA_U(base, index, index2) (FMC_DATA_U_REG(base, index, index2))
+#define FMC_WR_DATA_U(base, index, index2, value) (FMC_DATA_U_REG(base, index, index2) = (value))
+#define FMC_RMW_DATA_U(base, index, index2, mask, value) (FMC_WR_DATA_U(base, index, index2, (FMC_RD_DATA_U(base, index, index2) & ~(mask)) | (value)))
+#define FMC_SET_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) |  (value)))
+#define FMC_CLR_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) & ~(value)))
+#define FMC_TOG_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_DATA_L - Cache Data Storage (lower word)
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_DATA_L - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_DATA_L register
+ */
+/*@{*/
+#define FMC_RD_DATA_L(base, index, index2) (FMC_DATA_L_REG(base, index, index2))
+#define FMC_WR_DATA_L(base, index, index2, value) (FMC_DATA_L_REG(base, index, index2) = (value))
+#define FMC_RMW_DATA_L(base, index, index2, mask, value) (FMC_WR_DATA_L(base, index, index2, (FMC_RD_DATA_L(base, index, index2) & ~(mask)) | (value)))
+#define FMC_SET_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) |  (value)))
+#define FMC_CLR_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) & ~(value)))
+#define FMC_TOG_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FTFE
+ *
+ * Flash Memory Interface
+ *
+ * Registers defined in this header file:
+ * - FTFE_FSTAT - Flash Status Register
+ * - FTFE_FCNFG - Flash Configuration Register
+ * - FTFE_FSEC - Flash Security Register
+ * - FTFE_FOPT - Flash Option Register
+ * - FTFE_FCCOB3 - Flash Common Command Object Registers
+ * - FTFE_FCCOB2 - Flash Common Command Object Registers
+ * - FTFE_FCCOB1 - Flash Common Command Object Registers
+ * - FTFE_FCCOB0 - Flash Common Command Object Registers
+ * - FTFE_FCCOB7 - Flash Common Command Object Registers
+ * - FTFE_FCCOB6 - Flash Common Command Object Registers
+ * - FTFE_FCCOB5 - Flash Common Command Object Registers
+ * - FTFE_FCCOB4 - Flash Common Command Object Registers
+ * - FTFE_FCCOBB - Flash Common Command Object Registers
+ * - FTFE_FCCOBA - Flash Common Command Object Registers
+ * - FTFE_FCCOB9 - Flash Common Command Object Registers
+ * - FTFE_FCCOB8 - Flash Common Command Object Registers
+ * - FTFE_FPROT3 - Program Flash Protection Registers
+ * - FTFE_FPROT2 - Program Flash Protection Registers
+ * - FTFE_FPROT1 - Program Flash Protection Registers
+ * - FTFE_FPROT0 - Program Flash Protection Registers
+ * - FTFE_FEPROT - EEPROM Protection Register
+ * - FTFE_FDPROT - Data Flash Protection Register
+ */
+
+#define FTFE_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFE module. */
+#define FTFE_IDX (0U) /*!< Instance number for FTFE. */
+
+/*******************************************************************************
+ * FTFE_FSTAT - Flash Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FSTAT - Flash Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FSTAT register reports the operational status of the FTFE module. The
+ * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0
+ * bit is read only. The unassigned bits read 0 and are not writable. When set, the
+ * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this
+ * register prevent the launch of any more commands or writes to the FlexRAM (when
+ * EEERDY is set) until the flag is cleared (by writing a one to it).
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FSTAT register
+ */
+/*@{*/
+#define FTFE_RD_FSTAT(base)      (FTFE_FSTAT_REG(base))
+#define FTFE_WR_FSTAT(base, value) (FTFE_FSTAT_REG(base) = (value))
+#define FTFE_RMW_FSTAT(base, mask, value) (FTFE_WR_FSTAT(base, (FTFE_RD_FSTAT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) |  (value)))
+#define FTFE_CLR_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) & ~(value)))
+#define FTFE_TOG_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FSTAT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO)
+ *
+ * The MGSTAT0 status flag is set if an error is detected during execution of an
+ * FTFE command or during the flash reset sequence. As a status flag, this bit
+ * cannot (and need not) be cleared by the user like the other error flags in this
+ * register. The value of the MGSTAT0 bit for "command-N" is valid only at the
+ * end of the "command-N" execution when CCIF=1 and before the next command has
+ * been launched. At some point during the execution of "command-N+1," the previous
+ * result is discarded and any previous error is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field. */
+#define FTFE_RD_FSTAT_MGSTAT0(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_MGSTAT0_MASK) >> FTFE_FSTAT_MGSTAT0_SHIFT)
+#define FTFE_BRD_FSTAT_MGSTAT0(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_MGSTAT0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C)
+ *
+ * The FPVIOL error bit indicates an attempt was made to program or erase an
+ * address in a protected area of program flash or data flash memory during a
+ * command write sequence or a write was attempted to a protected area of the FlexRAM
+ * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared
+ * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a
+ * 0 to the FPVIOL bit has no effect.
+ *
+ * Values:
+ * - 0b0 - No protection violation detected
+ * - 0b1 - Protection violation detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_FPVIOL field. */
+#define FTFE_RD_FSTAT_FPVIOL(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_FPVIOL_MASK) >> FTFE_FSTAT_FPVIOL_SHIFT)
+#define FTFE_BRD_FSTAT_FPVIOL(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_FPVIOL_SHIFT))
+
+/*! @brief Set the FPVIOL field to a new value. */
+#define FTFE_WR_FSTAT_FPVIOL(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_FPVIOL(value)))
+#define FTFE_BWR_FSTAT_FPVIOL(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_FPVIOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field ACCERR[5] (W1C)
+ *
+ * The ACCERR error bit indicates an illegal access has occurred to an FTFE
+ * resource caused by a violation of the command write sequence or issuing an illegal
+ * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch
+ * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
+ * ACCERR bit has no effect.
+ *
+ * Values:
+ * - 0b0 - No access error detected
+ * - 0b1 - Access error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_ACCERR field. */
+#define FTFE_RD_FSTAT_ACCERR(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_ACCERR_MASK) >> FTFE_FSTAT_ACCERR_SHIFT)
+#define FTFE_BRD_FSTAT_ACCERR(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_ACCERR_SHIFT))
+
+/*! @brief Set the ACCERR field to a new value. */
+#define FTFE_WR_FSTAT_ACCERR(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_ACCERR(value)))
+#define FTFE_BWR_FSTAT_ACCERR(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_ACCERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C)
+ *
+ * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE
+ * resource that was being manipulated by an FTFE command (CCIF=0). Any
+ * simultaneous access is detected as a collision error by the block arbitration logic. The
+ * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by
+ * writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
+ *
+ * Values:
+ * - 0b0 - No collision error detected
+ * - 0b1 - Collision error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_RDCOLERR field. */
+#define FTFE_RD_FSTAT_RDCOLERR(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_RDCOLERR_MASK) >> FTFE_FSTAT_RDCOLERR_SHIFT)
+#define FTFE_BRD_FSTAT_RDCOLERR(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_RDCOLERR_SHIFT))
+
+/*! @brief Set the RDCOLERR field to a new value. */
+#define FTFE_WR_FSTAT_RDCOLERR(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_RDCOLERR(value)))
+#define FTFE_BWR_FSTAT_RDCOLERR(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_RDCOLERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field CCIF[7] (W1C)
+ *
+ * The CCIF flag indicates that a FTFE command or EEPROM file system operation
+ * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a
+ * command, and CCIF stays low until command completion or command violation. The
+ * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE,
+ * and CCIF stays low until the EEPROM file system has created the associated
+ * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory
+ * controller at the end of the reset initialization sequence. Depending on how
+ * quickly the read occurs after reset release, the user may or may not see the 0
+ * hardware reset value.
+ *
+ * Values:
+ * - 0b0 - FTFE command or EEPROM file system operation in progress
+ * - 0b1 - FTFE command or EEPROM file system operation has completed
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_CCIF field. */
+#define FTFE_RD_FSTAT_CCIF(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_CCIF_MASK) >> FTFE_FSTAT_CCIF_SHIFT)
+#define FTFE_BRD_FSTAT_CCIF(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_CCIF_SHIFT))
+
+/*! @brief Set the CCIF field to a new value. */
+#define FTFE_WR_FSTAT_CCIF(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_CCIF_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_RDCOLERR_MASK), FTFE_FSTAT_CCIF(value)))
+#define FTFE_BWR_FSTAT_CCIF(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_CCIF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCNFG - Flash Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCNFG - Flash Configuration Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides information on the current functional state of the
+ * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write
+ * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned
+ * bits read as noted and are not writable. The reset values for the SWAP, PFLSH,
+ * RAMRDY, and EEERDY bits are determined during the reset sequence.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCNFG register
+ */
+/*@{*/
+#define FTFE_RD_FCNFG(base)      (FTFE_FCNFG_REG(base))
+#define FTFE_WR_FCNFG(base, value) (FTFE_FCNFG_REG(base) = (value))
+#define FTFE_RMW_FCNFG(base, mask, value) (FTFE_WR_FCNFG(base, (FTFE_RD_FCNFG(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) |  (value)))
+#define FTFE_CLR_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) & ~(value)))
+#define FTFE_TOG_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FCNFG bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCNFG, field EEERDY[0] (RO)
+ *
+ * For devices with FlexNVM: This flag indicates if the EEPROM backup data has
+ * been copied to the FlexRAM and is therefore available for read access. During
+ * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if
+ * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM:
+ * This bit is reserved.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FlexRAM is not available for EEPROM
+ *     operation.
+ * - 0b1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations
+ *     where: reads from the FlexRAM return data previously written to the
+ *     FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the
+ *     written data in the FlexRAM and EEPROM backup.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_EEERDY field. */
+#define FTFE_RD_FCNFG_EEERDY(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_EEERDY_MASK) >> FTFE_FCNFG_EEERDY_SHIFT)
+#define FTFE_BRD_FCNFG_EEERDY(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_EEERDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field RAMRDY[1] (RO)
+ *
+ * This flag indicates the current status of the FlexRAM/ programming
+ * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally
+ * controlled by the Set FlexRAM Function command. During the reset sequence, the
+ * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will
+ * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is
+ * cleared if the Program Partition command is run to partition the FlexNVM block
+ * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks
+ * command or execution of the erase-all operation triggered external to the FTFE.
+ * For devices without FlexNVM: This bit should always be set.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FlexRAM is not available for traditional
+ *     RAM access. For devices without FlexNVM: Programming acceleration RAM is not
+ *     available.
+ * - 0b1 - For devices with FlexNVM: FlexRAM is available as traditional RAM
+ *     only; writes to the FlexRAM do not trigger EEPROM operations. For devices
+ *     without FlexNVM: Programming acceleration RAM is available.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_RAMRDY field. */
+#define FTFE_RD_FCNFG_RAMRDY(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_RAMRDY_MASK) >> FTFE_FCNFG_RAMRDY_SHIFT)
+#define FTFE_BRD_FCNFG_RAMRDY(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RAMRDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field PFLSH[2] (RO)
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FTFE configuration supports two program
+ *     flash blocks and two FlexNVM blocks For devices with program flash only:
+ *     Reserved
+ * - 0b1 - For devices with FlexNVM: Reserved For devices with program flash
+ *     only: FTFE configuration supports four program flash blocks
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_PFLSH field. */
+#define FTFE_RD_FCNFG_PFLSH(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_PFLSH_MASK) >> FTFE_FCNFG_PFLSH_SHIFT)
+#define FTFE_BRD_FCNFG_PFLSH(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_PFLSH_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field SWAP[3] (RO)
+ *
+ * The SWAP flag indicates which half of the program flash space is located at
+ * relative address 0x0000. The state of the SWAP flag is set by the FTFE during
+ * the reset sequence. See for information on swap management.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: Program flash 0 block is located at
+ *     relative address 0x0000 For devices with program flash only: Program flash 0
+ *     block is located at relative address 0x0000
+ * - 0b1 - For devices with FlexNVM: Reserved For devices with program flash
+ *     only: Program flash 1 block is located at relative address 0x0000
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_SWAP field. */
+#define FTFE_RD_FCNFG_SWAP(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_SWAP_MASK) >> FTFE_FCNFG_SWAP_SHIFT)
+#define FTFE_BRD_FCNFG_SWAP(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_SWAP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW)
+ *
+ * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector
+ * command while it is executing.
+ *
+ * Values:
+ * - 0b0 - No suspend requested
+ * - 0b1 - Suspend the current Erase Flash Sector command execution.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_ERSSUSP field. */
+#define FTFE_RD_FCNFG_ERSSUSP(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_ERSSUSP_MASK) >> FTFE_FCNFG_ERSSUSP_SHIFT)
+#define FTFE_BRD_FCNFG_ERSSUSP(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSSUSP_SHIFT))
+
+/*! @brief Set the ERSSUSP field to a new value. */
+#define FTFE_WR_FCNFG_ERSSUSP(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_ERSSUSP_MASK, FTFE_FCNFG_ERSSUSP(value)))
+#define FTFE_BWR_FCNFG_ERSSUSP(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSSUSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO)
+ *
+ * This bit issues a request to the memory controller to execute the Erase All
+ * Blocks command and release security. ERSAREQ is not directly writable but is
+ * under indirect user control. Refer to the device's Chip Configuration details on
+ * how to request this command. The ERSAREQ bit sets when an erase all request
+ * is triggered external to the FTFE and CCIF is set (no command is currently
+ * being executed). ERSAREQ is cleared by the FTFE when the operation completes.
+ *
+ * Values:
+ * - 0b0 - No request or request complete
+ * - 0b1 - Request to: run the Erase All Blocks command, verify the erased
+ *     state, program the security byte in the Flash Configuration Field to the
+ *     unsecure state, and release MCU security by setting the FSEC[SEC] field to the
+ *     unsecure state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_ERSAREQ field. */
+#define FTFE_RD_FCNFG_ERSAREQ(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_ERSAREQ_MASK) >> FTFE_FCNFG_ERSAREQ_SHIFT)
+#define FTFE_BRD_FCNFG_ERSAREQ(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSAREQ_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW)
+ *
+ * The RDCOLLIE bit controls interrupt generation when an FTFE read collision
+ * error occurs.
+ *
+ * Values:
+ * - 0b0 - Read collision error interrupt disabled
+ * - 0b1 - Read collision error interrupt enabled. An interrupt request is
+ *     generated whenever an FTFE read collision error is detected (see the
+ *     description of FSTAT[RDCOLERR]).
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field. */
+#define FTFE_RD_FCNFG_RDCOLLIE(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_RDCOLLIE_MASK) >> FTFE_FCNFG_RDCOLLIE_SHIFT)
+#define FTFE_BRD_FCNFG_RDCOLLIE(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RDCOLLIE_SHIFT))
+
+/*! @brief Set the RDCOLLIE field to a new value. */
+#define FTFE_WR_FCNFG_RDCOLLIE(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_RDCOLLIE_MASK, FTFE_FCNFG_RDCOLLIE(value)))
+#define FTFE_BWR_FCNFG_RDCOLLIE(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RDCOLLIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field CCIE[7] (RW)
+ *
+ * The CCIE bit controls interrupt generation when an FTFE command completes.
+ *
+ * Values:
+ * - 0b0 - Command complete interrupt disabled
+ * - 0b1 - Command complete interrupt enabled. An interrupt request is generated
+ *     whenever the FSTAT[CCIF] flag is set.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_CCIE field. */
+#define FTFE_RD_FCNFG_CCIE(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_CCIE_MASK) >> FTFE_FCNFG_CCIE_SHIFT)
+#define FTFE_BRD_FCNFG_CCIE(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_CCIE_SHIFT))
+
+/*! @brief Set the CCIE field to a new value. */
+#define FTFE_WR_FCNFG_CCIE(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_CCIE_MASK, FTFE_FCNFG_CCIE(value)))
+#define FTFE_BWR_FCNFG_CCIE(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_CCIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FSEC - Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FSEC - Flash Security Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This read-only register holds all bits associated with the security of the
+ * MCU and FTFE module. During the reset sequence, the register is loaded with the
+ * contents of the flash security byte in the Flash Configuration Field located
+ * in program flash memory. The Flash basis for the values is signified by X in
+ * the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FSEC register
+ */
+/*@{*/
+#define FTFE_RD_FSEC(base)       (FTFE_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FSEC bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSEC, field SEC[1:0] (RO)
+ *
+ * These bits define the security state of the MCU. In the secure state, the MCU
+ * limits access to FTFE module resources. The limitations are defined per
+ * device and are detailed in the Chip Configuration details. If the FTFE module is
+ * unsecured using backdoor key access, the SEC bits are forced to 10b.
+ *
+ * Values:
+ * - 0b00 - MCU security status is secure
+ * - 0b01 - MCU security status is secure
+ * - 0b10 - MCU security status is unsecure (The standard shipping condition of
+ *     the FTFE is unsecure.)
+ * - 0b11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_SEC field. */
+#define FTFE_RD_FSEC_SEC(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_SEC_MASK) >> FTFE_FSEC_SEC_SHIFT)
+#define FTFE_BRD_FSEC_SEC(base) (FTFE_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field FSLACC[3:2] (RO)
+ *
+ * These bits enable or disable access to the flash memory contents during
+ * returned part failure analysis at Freescale. When SEC is secure and FSLACC is
+ * denied, access to the program flash contents is denied and any failure analysis
+ * performed by Freescale factory test must begin with a full erase to unsecure the
+ * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is
+ * granted), Freescale factory testing has visibility of the current flash
+ * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to
+ * secure. When the SEC field is set to unsecure, the FSLACC setting does not
+ * matter.
+ *
+ * Values:
+ * - 0b00 - Freescale factory access granted
+ * - 0b01 - Freescale factory access denied
+ * - 0b10 - Freescale factory access denied
+ * - 0b11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_FSLACC field. */
+#define FTFE_RD_FSEC_FSLACC(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_FSLACC_MASK) >> FTFE_FSEC_FSLACC_SHIFT)
+#define FTFE_BRD_FSEC_FSLACC(base) (FTFE_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field MEEN[5:4] (RO)
+ *
+ * Enables and disables mass erase capability of the FTFE module. The state of
+ * the MEEN bits is only relevant when the SEC bits are set to secure outside of
+ * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does
+ * not matter.
+ *
+ * Values:
+ * - 0b00 - Mass erase is enabled
+ * - 0b01 - Mass erase is enabled
+ * - 0b10 - Mass erase is disabled
+ * - 0b11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_MEEN field. */
+#define FTFE_RD_FSEC_MEEN(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_MEEN_MASK) >> FTFE_FSEC_MEEN_SHIFT)
+#define FTFE_BRD_FSEC_MEEN(base) (FTFE_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field KEYEN[7:6] (RO)
+ *
+ * These bits enable and disable backdoor key access to the FTFE module.
+ *
+ * Values:
+ * - 0b00 - Backdoor key access disabled
+ * - 0b01 - Backdoor key access disabled (preferred KEYEN state to disable
+ *     backdoor key access)
+ * - 0b10 - Backdoor key access enabled
+ * - 0b11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_KEYEN field. */
+#define FTFE_RD_FSEC_KEYEN(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_KEYEN_MASK) >> FTFE_FSEC_KEYEN_SHIFT)
+#define FTFE_BRD_FSEC_KEYEN(base) (FTFE_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FOPT - Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FOPT - Flash Option Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * The flash option register allows the MCU to customize its operations by
+ * examining the state of these read-only bits, which are loaded from NVM at reset.
+ * The function of the bits is defined in the device's Chip Configuration details.
+ * All bits in the register are read-only. During the reset sequence, the
+ * register is loaded from the flash nonvolatile option byte in the Flash Configuration
+ * Field located in program flash memory. The flash basis for the values is
+ * signified by X in the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FOPT register
+ */
+/*@{*/
+#define FTFE_RD_FOPT(base)       (FTFE_FOPT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB3 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB3 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB3 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB3(base)     (FTFE_FCCOB3_REG(base))
+#define FTFE_WR_FCCOB3(base, value) (FTFE_FCCOB3_REG(base) = (value))
+#define FTFE_RMW_FCCOB3(base, mask, value) (FTFE_WR_FCCOB3(base, (FTFE_RD_FCCOB3(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) |  (value)))
+#define FTFE_CLR_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) & ~(value)))
+#define FTFE_TOG_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB2 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB2 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB2 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB2(base)     (FTFE_FCCOB2_REG(base))
+#define FTFE_WR_FCCOB2(base, value) (FTFE_FCCOB2_REG(base) = (value))
+#define FTFE_RMW_FCCOB2(base, mask, value) (FTFE_WR_FCCOB2(base, (FTFE_RD_FCCOB2(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) |  (value)))
+#define FTFE_CLR_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) & ~(value)))
+#define FTFE_TOG_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB1 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB1 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB1 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB1(base)     (FTFE_FCCOB1_REG(base))
+#define FTFE_WR_FCCOB1(base, value) (FTFE_FCCOB1_REG(base) = (value))
+#define FTFE_RMW_FCCOB1(base, mask, value) (FTFE_WR_FCCOB1(base, (FTFE_RD_FCCOB1(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) |  (value)))
+#define FTFE_CLR_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) & ~(value)))
+#define FTFE_TOG_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB0 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB0 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB0 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB0(base)     (FTFE_FCCOB0_REG(base))
+#define FTFE_WR_FCCOB0(base, value) (FTFE_FCCOB0_REG(base) = (value))
+#define FTFE_RMW_FCCOB0(base, mask, value) (FTFE_WR_FCCOB0(base, (FTFE_RD_FCCOB0(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) |  (value)))
+#define FTFE_CLR_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) & ~(value)))
+#define FTFE_TOG_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB7 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB7 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB7 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB7(base)     (FTFE_FCCOB7_REG(base))
+#define FTFE_WR_FCCOB7(base, value) (FTFE_FCCOB7_REG(base) = (value))
+#define FTFE_RMW_FCCOB7(base, mask, value) (FTFE_WR_FCCOB7(base, (FTFE_RD_FCCOB7(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) |  (value)))
+#define FTFE_CLR_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) & ~(value)))
+#define FTFE_TOG_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB6 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB6 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB6 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB6(base)     (FTFE_FCCOB6_REG(base))
+#define FTFE_WR_FCCOB6(base, value) (FTFE_FCCOB6_REG(base) = (value))
+#define FTFE_RMW_FCCOB6(base, mask, value) (FTFE_WR_FCCOB6(base, (FTFE_RD_FCCOB6(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) |  (value)))
+#define FTFE_CLR_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) & ~(value)))
+#define FTFE_TOG_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB5 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB5 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB5 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB5(base)     (FTFE_FCCOB5_REG(base))
+#define FTFE_WR_FCCOB5(base, value) (FTFE_FCCOB5_REG(base) = (value))
+#define FTFE_RMW_FCCOB5(base, mask, value) (FTFE_WR_FCCOB5(base, (FTFE_RD_FCCOB5(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) |  (value)))
+#define FTFE_CLR_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) & ~(value)))
+#define FTFE_TOG_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB4 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB4 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB4 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB4(base)     (FTFE_FCCOB4_REG(base))
+#define FTFE_WR_FCCOB4(base, value) (FTFE_FCCOB4_REG(base) = (value))
+#define FTFE_RMW_FCCOB4(base, mask, value) (FTFE_WR_FCCOB4(base, (FTFE_RD_FCCOB4(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) |  (value)))
+#define FTFE_CLR_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) & ~(value)))
+#define FTFE_TOG_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOBB - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOBB - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBB register
+ */
+/*@{*/
+#define FTFE_RD_FCCOBB(base)     (FTFE_FCCOBB_REG(base))
+#define FTFE_WR_FCCOBB(base, value) (FTFE_FCCOBB_REG(base) = (value))
+#define FTFE_RMW_FCCOBB(base, mask, value) (FTFE_WR_FCCOBB(base, (FTFE_RD_FCCOBB(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) |  (value)))
+#define FTFE_CLR_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) & ~(value)))
+#define FTFE_TOG_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOBA - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOBA - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBA register
+ */
+/*@{*/
+#define FTFE_RD_FCCOBA(base)     (FTFE_FCCOBA_REG(base))
+#define FTFE_WR_FCCOBA(base, value) (FTFE_FCCOBA_REG(base) = (value))
+#define FTFE_RMW_FCCOBA(base, mask, value) (FTFE_WR_FCCOBA(base, (FTFE_RD_FCCOBA(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) |  (value)))
+#define FTFE_CLR_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) & ~(value)))
+#define FTFE_TOG_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB9 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB9 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB9 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB9(base)     (FTFE_FCCOB9_REG(base))
+#define FTFE_WR_FCCOB9(base, value) (FTFE_FCCOB9_REG(base) = (value))
+#define FTFE_RMW_FCCOB9(base, mask, value) (FTFE_WR_FCCOB9(base, (FTFE_RD_FCCOB9(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) |  (value)))
+#define FTFE_CLR_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) & ~(value)))
+#define FTFE_TOG_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB8 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB8 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB8 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB8(base)     (FTFE_FCCOB8_REG(base))
+#define FTFE_WR_FCCOB8(base, value) (FTFE_FCCOB8_REG(base) = (value))
+#define FTFE_RMW_FCCOB8(base, mask, value) (FTFE_WR_FCCOB8(base, (FTFE_RD_FCCOB8(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) |  (value)))
+#define FTFE_CLR_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) & ~(value)))
+#define FTFE_TOG_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT3 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT3 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT3 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT3(base)     (FTFE_FPROT3_REG(base))
+#define FTFE_WR_FPROT3(base, value) (FTFE_FPROT3_REG(base) = (value))
+#define FTFE_RMW_FPROT3(base, mask, value) (FTFE_WR_FPROT3(base, (FTFE_RD_FPROT3(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) |  (value)))
+#define FTFE_CLR_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) & ~(value)))
+#define FTFE_TOG_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT2 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT2 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT2 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT2(base)     (FTFE_FPROT2_REG(base))
+#define FTFE_WR_FPROT2(base, value) (FTFE_FPROT2_REG(base) = (value))
+#define FTFE_RMW_FPROT2(base, mask, value) (FTFE_WR_FPROT2(base, (FTFE_RD_FPROT2(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) |  (value)))
+#define FTFE_CLR_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) & ~(value)))
+#define FTFE_TOG_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT1 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT1 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT1 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT1(base)     (FTFE_FPROT1_REG(base))
+#define FTFE_WR_FPROT1(base, value) (FTFE_FPROT1_REG(base) = (value))
+#define FTFE_RMW_FPROT1(base, mask, value) (FTFE_WR_FPROT1(base, (FTFE_RD_FPROT1(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) |  (value)))
+#define FTFE_CLR_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) & ~(value)))
+#define FTFE_TOG_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT0 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT0 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT0 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT0(base)     (FTFE_FPROT0_REG(base))
+#define FTFE_WR_FPROT0(base, value) (FTFE_FPROT0_REG(base) = (value))
+#define FTFE_RMW_FPROT0(base, mask, value) (FTFE_WR_FPROT0(base, (FTFE_RD_FPROT0(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) |  (value)))
+#define FTFE_CLR_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) & ~(value)))
+#define FTFE_TOG_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FEPROT - EEPROM Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FEPROT - EEPROM Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of
+ * the FlexRAM are protected against program and erase operations. Protected
+ * EEPROM regions cannot have their content changed by writing to it. Unprotected
+ * regions can be changed by writing to the FlexRAM. For devices with program flash
+ * only: This register is reserved and not used.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FEPROT register
+ */
+/*@{*/
+#define FTFE_RD_FEPROT(base)     (FTFE_FEPROT_REG(base))
+#define FTFE_WR_FEPROT(base, value) (FTFE_FEPROT_REG(base) = (value))
+#define FTFE_RMW_FEPROT(base, mask, value) (FTFE_WR_FEPROT(base, (FTFE_RD_FEPROT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) |  (value)))
+#define FTFE_CLR_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) & ~(value)))
+#define FTFE_TOG_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FDPROT - Data Flash Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FDPROT - Data Flash Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FDPROT register defines which data flash regions are protected against
+ * program and erase operations. Protected Flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by both program and erase
+ * operations.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FDPROT register
+ */
+/*@{*/
+#define FTFE_RD_FDPROT(base)     (FTFE_FDPROT_REG(base))
+#define FTFE_WR_FDPROT(base, value) (FTFE_FDPROT_REG(base) = (value))
+#define FTFE_RMW_FDPROT(base, mask, value) (FTFE_WR_FDPROT(base, (FTFE_RD_FDPROT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) |  (value)))
+#define FTFE_CLR_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) & ~(value)))
+#define FTFE_TOG_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FTM
+ *
+ * FlexTimer Module
+ *
+ * Registers defined in this header file:
+ * - FTM_SC - Status And Control
+ * - FTM_CNT - Counter
+ * - FTM_MOD - Modulo
+ * - FTM_CnSC - Channel (n) Status And Control
+ * - FTM_CnV - Channel (n) Value
+ * - FTM_CNTIN - Counter Initial Value
+ * - FTM_STATUS - Capture And Compare Status
+ * - FTM_MODE - Features Mode Selection
+ * - FTM_SYNC - Synchronization
+ * - FTM_OUTINIT - Initial State For Channels Output
+ * - FTM_OUTMASK - Output Mask
+ * - FTM_COMBINE - Function For Linked Channels
+ * - FTM_DEADTIME - Deadtime Insertion Control
+ * - FTM_EXTTRIG - FTM External Trigger
+ * - FTM_POL - Channels Polarity
+ * - FTM_FMS - Fault Mode Status
+ * - FTM_FILTER - Input Capture Filter Control
+ * - FTM_FLTCTRL - Fault Control
+ * - FTM_QDCTRL - Quadrature Decoder Control And Status
+ * - FTM_CONF - Configuration
+ * - FTM_FLTPOL - FTM Fault Input Polarity
+ * - FTM_SYNCONF - Synchronization Configuration
+ * - FTM_INVCTRL - FTM Inverting Control
+ * - FTM_SWOCTRL - FTM Software Output Control
+ * - FTM_PWMLOAD - FTM PWM Load
+ */
+
+#define FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
+#define FTM0_IDX (0U) /*!< Instance number for FTM0. */
+#define FTM1_IDX (1U) /*!< Instance number for FTM1. */
+#define FTM2_IDX (2U) /*!< Instance number for FTM2. */
+#define FTM3_IDX (3U) /*!< Instance number for FTM3. */
+
+/*******************************************************************************
+ * FTM_SC - Status And Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SC - Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * SC contains the overflow status flag and control bits used to configure the
+ * interrupt enable, FTM configuration, clock source, and prescaler factor. These
+ * controls relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SC register
+ */
+/*@{*/
+#define FTM_RD_SC(base)          (FTM_SC_REG(base))
+#define FTM_WR_SC(base, value)   (FTM_SC_REG(base) = (value))
+#define FTM_RMW_SC(base, mask, value) (FTM_WR_SC(base, (FTM_RD_SC(base) & ~(mask)) | (value)))
+#define FTM_SET_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) |  (value)))
+#define FTM_CLR_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) & ~(value)))
+#define FTM_TOG_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SC bitfields
+ */
+
+/*!
+ * @name Register FTM_SC, field PS[2:0] (RW)
+ *
+ * Selects one of 8 division factors for the clock source selected by CLKS. The
+ * new prescaler factor affects the clock source on the next system clock cycle
+ * after the new value is updated into the register bits. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b000 - Divide by 1
+ * - 0b001 - Divide by 2
+ * - 0b010 - Divide by 4
+ * - 0b011 - Divide by 8
+ * - 0b100 - Divide by 16
+ * - 0b101 - Divide by 32
+ * - 0b110 - Divide by 64
+ * - 0b111 - Divide by 128
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_PS field. */
+#define FTM_RD_SC_PS(base)   ((FTM_SC_REG(base) & FTM_SC_PS_MASK) >> FTM_SC_PS_SHIFT)
+#define FTM_BRD_SC_PS(base)  (FTM_RD_SC_PS(base))
+
+/*! @brief Set the PS field to a new value. */
+#define FTM_WR_SC_PS(base, value) (FTM_RMW_SC(base, FTM_SC_PS_MASK, FTM_SC_PS(value)))
+#define FTM_BWR_SC_PS(base, value) (FTM_WR_SC_PS(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field CLKS[4:3] (RW)
+ *
+ * Selects one of the three FTM counter clock sources. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b00 - No clock selected. This in effect disables the FTM counter.
+ * - 0b01 - System clock
+ * - 0b10 - Fixed frequency clock
+ * - 0b11 - External clock
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_CLKS field. */
+#define FTM_RD_SC_CLKS(base) ((FTM_SC_REG(base) & FTM_SC_CLKS_MASK) >> FTM_SC_CLKS_SHIFT)
+#define FTM_BRD_SC_CLKS(base) (FTM_RD_SC_CLKS(base))
+
+/*! @brief Set the CLKS field to a new value. */
+#define FTM_WR_SC_CLKS(base, value) (FTM_RMW_SC(base, FTM_SC_CLKS_MASK, FTM_SC_CLKS(value)))
+#define FTM_BWR_SC_CLKS(base, value) (FTM_WR_SC_CLKS(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field CPWMS[5] (RW)
+ *
+ * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
+ * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ *
+ * Values:
+ * - 0b0 - FTM counter operates in Up Counting mode.
+ * - 0b1 - FTM counter operates in Up-Down Counting mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_CPWMS field. */
+#define FTM_RD_SC_CPWMS(base) ((FTM_SC_REG(base) & FTM_SC_CPWMS_MASK) >> FTM_SC_CPWMS_SHIFT)
+#define FTM_BRD_SC_CPWMS(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_CPWMS_SHIFT))
+
+/*! @brief Set the CPWMS field to a new value. */
+#define FTM_WR_SC_CPWMS(base, value) (FTM_RMW_SC(base, FTM_SC_CPWMS_MASK, FTM_SC_CPWMS(value)))
+#define FTM_BWR_SC_CPWMS(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_CPWMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field TOIE[6] (RW)
+ *
+ * Enables FTM overflow interrupts.
+ *
+ * Values:
+ * - 0b0 - Disable TOF interrupts. Use software polling.
+ * - 0b1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_TOIE field. */
+#define FTM_RD_SC_TOIE(base) ((FTM_SC_REG(base) & FTM_SC_TOIE_MASK) >> FTM_SC_TOIE_SHIFT)
+#define FTM_BRD_SC_TOIE(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOIE_SHIFT))
+
+/*! @brief Set the TOIE field to a new value. */
+#define FTM_WR_SC_TOIE(base, value) (FTM_RMW_SC(base, FTM_SC_TOIE_MASK, FTM_SC_TOIE(value)))
+#define FTM_BWR_SC_TOIE(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field TOF[7] (ROWZ)
+ *
+ * Set by hardware when the FTM counter passes the value in the MOD register.
+ * The TOF bit is cleared by reading the SC register while TOF is set and then
+ * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
+ * occurs between the read and write operations, the write operation has no
+ * effect; therefore, TOF remains set indicating an overflow has occurred. In this
+ * case, a TOF interrupt request is not lost due to the clearing sequence for a
+ * previous TOF.
+ *
+ * Values:
+ * - 0b0 - FTM counter has not overflowed.
+ * - 0b1 - FTM counter has overflowed.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_TOF field. */
+#define FTM_RD_SC_TOF(base)  ((FTM_SC_REG(base) & FTM_SC_TOF_MASK) >> FTM_SC_TOF_SHIFT)
+#define FTM_BRD_SC_TOF(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOF_SHIFT))
+
+/*! @brief Set the TOF field to a new value. */
+#define FTM_WR_SC_TOF(base, value) (FTM_RMW_SC(base, FTM_SC_TOF_MASK, FTM_SC_TOF(value)))
+#define FTM_BWR_SC_TOF(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CNT - Counter
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CNT - Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CNT register contains the FTM counter value. Reset clears the CNT
+ * register. Writing any value to COUNT updates the counter with its initial value,
+ * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
+ * may read.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CNT register
+ */
+/*@{*/
+#define FTM_RD_CNT(base)         (FTM_CNT_REG(base))
+#define FTM_WR_CNT(base, value)  (FTM_CNT_REG(base) = (value))
+#define FTM_RMW_CNT(base, mask, value) (FTM_WR_CNT(base, (FTM_RD_CNT(base) & ~(mask)) | (value)))
+#define FTM_SET_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) |  (value)))
+#define FTM_CLR_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) & ~(value)))
+#define FTM_TOG_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CNT bitfields
+ */
+
+/*!
+ * @name Register FTM_CNT, field COUNT[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CNT_COUNT field. */
+#define FTM_RD_CNT_COUNT(base) ((FTM_CNT_REG(base) & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT)
+#define FTM_BRD_CNT_COUNT(base) (FTM_RD_CNT_COUNT(base))
+
+/*! @brief Set the COUNT field to a new value. */
+#define FTM_WR_CNT_COUNT(base, value) (FTM_RMW_CNT(base, FTM_CNT_COUNT_MASK, FTM_CNT_COUNT(value)))
+#define FTM_BWR_CNT_COUNT(base, value) (FTM_WR_CNT_COUNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_MOD - Modulo
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_MOD - Modulo (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Modulo register contains the modulo value for the FTM counter. After the
+ * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
+ * the next clock, and the next value of FTM counter depends on the selected
+ * counting method; see Counter. Writing to the MOD register latches the value into a
+ * buffer. The MOD register is updated with the value of its write buffer
+ * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
+ * mechanism may be manually reset by writing to the SC register whether BDM is
+ * active or not. Initialize the FTM counter, by writing to CNT, before writing
+ * to the MOD register to avoid confusion about when the first counter overflow
+ * will occur.
+ */
+/*!
+ * @name Constants and macros for entire FTM_MOD register
+ */
+/*@{*/
+#define FTM_RD_MOD(base)         (FTM_MOD_REG(base))
+#define FTM_WR_MOD(base, value)  (FTM_MOD_REG(base) = (value))
+#define FTM_RMW_MOD(base, mask, value) (FTM_WR_MOD(base, (FTM_RD_MOD(base) & ~(mask)) | (value)))
+#define FTM_SET_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) |  (value)))
+#define FTM_CLR_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) & ~(value)))
+#define FTM_TOG_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_MOD bitfields
+ */
+
+/*!
+ * @name Register FTM_MOD, field MOD[15:0] (RW)
+ *
+ * Modulo Value
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MOD_MOD field. */
+#define FTM_RD_MOD_MOD(base) ((FTM_MOD_REG(base) & FTM_MOD_MOD_MASK) >> FTM_MOD_MOD_SHIFT)
+#define FTM_BRD_MOD_MOD(base) (FTM_RD_MOD_MOD(base))
+
+/*! @brief Set the MOD field to a new value. */
+#define FTM_WR_MOD_MOD(base, value) (FTM_RMW_MOD(base, FTM_MOD_MOD_MASK, FTM_MOD_MOD(value)))
+#define FTM_BWR_MOD_MOD(base, value) (FTM_WR_MOD_MOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CnSC - Channel (n) Status And Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CnSC - Channel (n) Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CnSC contains the channel-interrupt-status flag and control bits used to
+ * configure the interrupt enable, channel configuration, and pin function. Mode,
+ * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
+ * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
+ * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
+ * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
+ * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
+ * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
+ * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
+ * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
+ * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
+ * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
+ * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
+ * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
+ * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
+ * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
+ * Enabled Rising and falling edges
+ */
+/*!
+ * @name Constants and macros for entire FTM_CnSC register
+ */
+/*@{*/
+#define FTM_RD_CnSC(base, index) (FTM_CnSC_REG(base, index))
+#define FTM_WR_CnSC(base, index, value) (FTM_CnSC_REG(base, index) = (value))
+#define FTM_RMW_CnSC(base, index, mask, value) (FTM_WR_CnSC(base, index, (FTM_RD_CnSC(base, index) & ~(mask)) | (value)))
+#define FTM_SET_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) |  (value)))
+#define FTM_CLR_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) & ~(value)))
+#define FTM_TOG_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CnSC bitfields
+ */
+
+/*!
+ * @name Register FTM_CnSC, field DMA[0] (RW)
+ *
+ * Enables DMA transfers for the channel.
+ *
+ * Values:
+ * - 0b0 - Disable DMA transfers.
+ * - 0b1 - Enable DMA transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_DMA field. */
+#define FTM_RD_CnSC_DMA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_DMA_MASK) >> FTM_CnSC_DMA_SHIFT)
+#define FTM_BRD_CnSC_DMA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define FTM_WR_CnSC_DMA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_DMA_MASK, FTM_CnSC_DMA(value)))
+#define FTM_BWR_CnSC_DMA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_DMA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field ELSA[2] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_ELSA field. */
+#define FTM_RD_CnSC_ELSA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_ELSA_MASK) >> FTM_CnSC_ELSA_SHIFT)
+#define FTM_BRD_CnSC_ELSA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSA_SHIFT))
+
+/*! @brief Set the ELSA field to a new value. */
+#define FTM_WR_CnSC_ELSA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_ELSA_MASK, FTM_CnSC_ELSA(value)))
+#define FTM_BWR_CnSC_ELSA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field ELSB[3] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_ELSB field. */
+#define FTM_RD_CnSC_ELSB(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_ELSB_MASK) >> FTM_CnSC_ELSB_SHIFT)
+#define FTM_BRD_CnSC_ELSB(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSB_SHIFT))
+
+/*! @brief Set the ELSB field to a new value. */
+#define FTM_WR_CnSC_ELSB(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_ELSB_MASK, FTM_CnSC_ELSB(value)))
+#define FTM_BWR_CnSC_ELSB(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field MSA[4] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_MSA field. */
+#define FTM_RD_CnSC_MSA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_MSA_MASK) >> FTM_CnSC_MSA_SHIFT)
+#define FTM_BRD_CnSC_MSA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSA_SHIFT))
+
+/*! @brief Set the MSA field to a new value. */
+#define FTM_WR_CnSC_MSA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_MSA_MASK, FTM_CnSC_MSA(value)))
+#define FTM_BWR_CnSC_MSA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field MSB[5] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_MSB field. */
+#define FTM_RD_CnSC_MSB(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_MSB_MASK) >> FTM_CnSC_MSB_SHIFT)
+#define FTM_BRD_CnSC_MSB(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSB_SHIFT))
+
+/*! @brief Set the MSB field to a new value. */
+#define FTM_WR_CnSC_MSB(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_MSB_MASK, FTM_CnSC_MSB(value)))
+#define FTM_BWR_CnSC_MSB(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field CHIE[6] (RW)
+ *
+ * Enables channel interrupts.
+ *
+ * Values:
+ * - 0b0 - Disable channel interrupts. Use software polling.
+ * - 0b1 - Enable channel interrupts.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_CHIE field. */
+#define FTM_RD_CnSC_CHIE(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_CHIE_MASK) >> FTM_CnSC_CHIE_SHIFT)
+#define FTM_BRD_CnSC_CHIE(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHIE_SHIFT))
+
+/*! @brief Set the CHIE field to a new value. */
+#define FTM_WR_CnSC_CHIE(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_CHIE_MASK, FTM_CnSC_CHIE(value)))
+#define FTM_BWR_CnSC_CHIE(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field CHF[7] (ROWZ)
+ *
+ * Set by hardware when an event occurs on the channel. CHF is cleared by
+ * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
+ * Writing a 1 to CHF has no effect. If another event occurs between the read and
+ * write operations, the write operation has no effect; therefore, CHF remains set
+ * indicating an event has occurred. In this case a CHF interrupt request is not
+ * lost due to the clearing sequence for a previous CHF.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_CHF field. */
+#define FTM_RD_CnSC_CHF(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_CHF_MASK) >> FTM_CnSC_CHF_SHIFT)
+#define FTM_BRD_CnSC_CHF(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHF_SHIFT))
+
+/*! @brief Set the CHF field to a new value. */
+#define FTM_WR_CnSC_CHF(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_CHF_MASK, FTM_CnSC_CHF(value)))
+#define FTM_BWR_CnSC_CHF(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CnV - Channel (n) Value
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CnV - Channel (n) Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the captured FTM counter value for the input modes or
+ * the match value for the output modes. In Input Capture, Capture Test, and
+ * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
+ * writing to a CnV register latches the value into a buffer. A CnV register is
+ * updated with the value of its write buffer according to Registers updated from
+ * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
+ * reset by writing to the CnSC register whether BDM mode is active or not.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CnV register
+ */
+/*@{*/
+#define FTM_RD_CnV(base, index)  (FTM_CnV_REG(base, index))
+#define FTM_WR_CnV(base, index, value) (FTM_CnV_REG(base, index) = (value))
+#define FTM_RMW_CnV(base, index, mask, value) (FTM_WR_CnV(base, index, (FTM_RD_CnV(base, index) & ~(mask)) | (value)))
+#define FTM_SET_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) |  (value)))
+#define FTM_CLR_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) & ~(value)))
+#define FTM_TOG_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CnV bitfields
+ */
+
+/*!
+ * @name Register FTM_CnV, field VAL[15:0] (RW)
+ *
+ * Captured FTM counter value of the input modes or the match value for the
+ * output modes
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnV_VAL field. */
+#define FTM_RD_CnV_VAL(base, index) ((FTM_CnV_REG(base, index) & FTM_CnV_VAL_MASK) >> FTM_CnV_VAL_SHIFT)
+#define FTM_BRD_CnV_VAL(base, index) (FTM_RD_CnV_VAL(base, index))
+
+/*! @brief Set the VAL field to a new value. */
+#define FTM_WR_CnV_VAL(base, index, value) (FTM_RMW_CnV(base, index, FTM_CnV_VAL_MASK, FTM_CnV_VAL(value)))
+#define FTM_BWR_CnV_VAL(base, index, value) (FTM_WR_CnV_VAL(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CNTIN - Counter Initial Value
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CNTIN - Counter Initial Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Counter Initial Value register contains the initial value for the FTM
+ * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
+ * register is updated with the value of its write buffer according to Registers
+ * updated from write buffers. When the FTM clock is initially selected, by
+ * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
+ * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
+ * write the new value to the the CNTIN register and then initialize the FTM
+ * counter by writing any value to the CNT register.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CNTIN register
+ */
+/*@{*/
+#define FTM_RD_CNTIN(base)       (FTM_CNTIN_REG(base))
+#define FTM_WR_CNTIN(base, value) (FTM_CNTIN_REG(base) = (value))
+#define FTM_RMW_CNTIN(base, mask, value) (FTM_WR_CNTIN(base, (FTM_RD_CNTIN(base) & ~(mask)) | (value)))
+#define FTM_SET_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) |  (value)))
+#define FTM_CLR_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) & ~(value)))
+#define FTM_TOG_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CNTIN bitfields
+ */
+
+/*!
+ * @name Register FTM_CNTIN, field INIT[15:0] (RW)
+ *
+ * Initial Value Of The FTM Counter
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CNTIN_INIT field. */
+#define FTM_RD_CNTIN_INIT(base) ((FTM_CNTIN_REG(base) & FTM_CNTIN_INIT_MASK) >> FTM_CNTIN_INIT_SHIFT)
+#define FTM_BRD_CNTIN_INIT(base) (FTM_RD_CNTIN_INIT(base))
+
+/*! @brief Set the INIT field to a new value. */
+#define FTM_WR_CNTIN_INIT(base, value) (FTM_RMW_CNTIN(base, FTM_CNTIN_INIT_MASK, FTM_CNTIN_INIT(value)))
+#define FTM_BWR_CNTIN_INIT(base, value) (FTM_WR_CNTIN_INIT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_STATUS - Capture And Compare Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_STATUS - Capture And Compare Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
+ * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
+ * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
+ * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
+ * STATUS. Hardware sets the individual channel flags when an event occurs on the
+ * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
+ * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
+ * occurs between the read and write operations, the write operation has no effect;
+ * therefore, CHnF remains set indicating an event has occurred. In this case, a
+ * CHnF interrupt request is not lost due to the clearing sequence for a previous
+ * CHnF. The STATUS register should be used only in Combine mode.
+ */
+/*!
+ * @name Constants and macros for entire FTM_STATUS register
+ */
+/*@{*/
+#define FTM_RD_STATUS(base)      (FTM_STATUS_REG(base))
+#define FTM_WR_STATUS(base, value) (FTM_STATUS_REG(base) = (value))
+#define FTM_RMW_STATUS(base, mask, value) (FTM_WR_STATUS(base, (FTM_RD_STATUS(base) & ~(mask)) | (value)))
+#define FTM_SET_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) |  (value)))
+#define FTM_CLR_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) & ~(value)))
+#define FTM_TOG_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_STATUS bitfields
+ */
+
+/*!
+ * @name Register FTM_STATUS, field CH0F[0] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH0F field. */
+#define FTM_RD_STATUS_CH0F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH0F_MASK) >> FTM_STATUS_CH0F_SHIFT)
+#define FTM_BRD_STATUS_CH0F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH0F_SHIFT))
+
+/*! @brief Set the CH0F field to a new value. */
+#define FTM_WR_STATUS_CH0F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH0F(value)))
+#define FTM_BWR_STATUS_CH0F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH0F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH1F[1] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH1F field. */
+#define FTM_RD_STATUS_CH1F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH1F_MASK) >> FTM_STATUS_CH1F_SHIFT)
+#define FTM_BRD_STATUS_CH1F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH1F_SHIFT))
+
+/*! @brief Set the CH1F field to a new value. */
+#define FTM_WR_STATUS_CH1F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH1F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH1F(value)))
+#define FTM_BWR_STATUS_CH1F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH1F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH2F[2] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH2F field. */
+#define FTM_RD_STATUS_CH2F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH2F_MASK) >> FTM_STATUS_CH2F_SHIFT)
+#define FTM_BRD_STATUS_CH2F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH2F_SHIFT))
+
+/*! @brief Set the CH2F field to a new value. */
+#define FTM_WR_STATUS_CH2F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH2F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH2F(value)))
+#define FTM_BWR_STATUS_CH2F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH2F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH3F[3] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH3F field. */
+#define FTM_RD_STATUS_CH3F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH3F_MASK) >> FTM_STATUS_CH3F_SHIFT)
+#define FTM_BRD_STATUS_CH3F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH3F_SHIFT))
+
+/*! @brief Set the CH3F field to a new value. */
+#define FTM_WR_STATUS_CH3F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH3F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH3F(value)))
+#define FTM_BWR_STATUS_CH3F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH3F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH4F[4] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH4F field. */
+#define FTM_RD_STATUS_CH4F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH4F_MASK) >> FTM_STATUS_CH4F_SHIFT)
+#define FTM_BRD_STATUS_CH4F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH4F_SHIFT))
+
+/*! @brief Set the CH4F field to a new value. */
+#define FTM_WR_STATUS_CH4F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH4F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH4F(value)))
+#define FTM_BWR_STATUS_CH4F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH4F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH5F[5] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH5F field. */
+#define FTM_RD_STATUS_CH5F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH5F_MASK) >> FTM_STATUS_CH5F_SHIFT)
+#define FTM_BRD_STATUS_CH5F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH5F_SHIFT))
+
+/*! @brief Set the CH5F field to a new value. */
+#define FTM_WR_STATUS_CH5F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH5F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH5F(value)))
+#define FTM_BWR_STATUS_CH5F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH5F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH6F[6] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH6F field. */
+#define FTM_RD_STATUS_CH6F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH6F_MASK) >> FTM_STATUS_CH6F_SHIFT)
+#define FTM_BRD_STATUS_CH6F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH6F_SHIFT))
+
+/*! @brief Set the CH6F field to a new value. */
+#define FTM_WR_STATUS_CH6F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH6F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH6F(value)))
+#define FTM_BWR_STATUS_CH6F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH6F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH7F[7] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH7F field. */
+#define FTM_RD_STATUS_CH7F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH7F_MASK) >> FTM_STATUS_CH7F_SHIFT)
+#define FTM_BRD_STATUS_CH7F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH7F_SHIFT))
+
+/*! @brief Set the CH7F field to a new value. */
+#define FTM_WR_STATUS_CH7F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH7F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK), FTM_STATUS_CH7F(value)))
+#define FTM_BWR_STATUS_CH7F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH7F_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_MODE - Features Mode Selection
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_MODE - Features Mode Selection (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * This register contains the global enable bit for FTM-specific features and
+ * the control bits used to configure: Fault control mode and interrupt Capture
+ * Test mode PWM synchronization Write protection Channel output initialization
+ * These controls relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire FTM_MODE register
+ */
+/*@{*/
+#define FTM_RD_MODE(base)        (FTM_MODE_REG(base))
+#define FTM_WR_MODE(base, value) (FTM_MODE_REG(base) = (value))
+#define FTM_RMW_MODE(base, mask, value) (FTM_WR_MODE(base, (FTM_RD_MODE(base) & ~(mask)) | (value)))
+#define FTM_SET_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) |  (value)))
+#define FTM_CLR_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) & ~(value)))
+#define FTM_TOG_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_MODE bitfields
+ */
+
+/*!
+ * @name Register FTM_MODE, field FTMEN[0] (RW)
+ *
+ * This field is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Only the TPM-compatible registers (first set of registers) can be
+ *     used without any restriction. Do not use the FTM-specific registers.
+ * - 0b1 - All registers including the FTM-specific registers (second set of
+ *     registers) are available for use with no restrictions.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FTMEN field. */
+#define FTM_RD_MODE_FTMEN(base) ((FTM_MODE_REG(base) & FTM_MODE_FTMEN_MASK) >> FTM_MODE_FTMEN_SHIFT)
+#define FTM_BRD_MODE_FTMEN(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FTMEN_SHIFT))
+
+/*! @brief Set the FTMEN field to a new value. */
+#define FTM_WR_MODE_FTMEN(base, value) (FTM_RMW_MODE(base, FTM_MODE_FTMEN_MASK, FTM_MODE_FTMEN(value)))
+#define FTM_BWR_MODE_FTMEN(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FTMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field INIT[1] (RW)
+ *
+ * When a 1 is written to INIT bit the channels output is initialized according
+ * to the state of their corresponding bit in the OUTINIT register. Writing a 0
+ * to INIT bit has no effect. The INIT bit is always read as 0.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_INIT field. */
+#define FTM_RD_MODE_INIT(base) ((FTM_MODE_REG(base) & FTM_MODE_INIT_MASK) >> FTM_MODE_INIT_SHIFT)
+#define FTM_BRD_MODE_INIT(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_INIT_SHIFT))
+
+/*! @brief Set the INIT field to a new value. */
+#define FTM_WR_MODE_INIT(base, value) (FTM_RMW_MODE(base, FTM_MODE_INIT_MASK, FTM_MODE_INIT(value)))
+#define FTM_BWR_MODE_INIT(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_INIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field WPDIS[2] (RW)
+ *
+ * When write protection is enabled (WPDIS = 0), write protected bits cannot be
+ * written. When write protection is disabled (WPDIS = 1), write protected bits
+ * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
+ * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
+ * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
+ *
+ * Values:
+ * - 0b0 - Write protection is enabled.
+ * - 0b1 - Write protection is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_WPDIS field. */
+#define FTM_RD_MODE_WPDIS(base) ((FTM_MODE_REG(base) & FTM_MODE_WPDIS_MASK) >> FTM_MODE_WPDIS_SHIFT)
+#define FTM_BRD_MODE_WPDIS(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_WPDIS_SHIFT))
+
+/*! @brief Set the WPDIS field to a new value. */
+#define FTM_WR_MODE_WPDIS(base, value) (FTM_RMW_MODE(base, FTM_MODE_WPDIS_MASK, FTM_MODE_WPDIS(value)))
+#define FTM_BWR_MODE_WPDIS(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_WPDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field PWMSYNC[3] (RW)
+ *
+ * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
+ * synchronization. See PWM synchronization. The PWMSYNC bit configures the
+ * synchronization when SYNCMODE is 0.
+ *
+ * Values:
+ * - 0b0 - No restrictions. Software and hardware triggers can be used by MOD,
+ *     CnV, OUTMASK, and FTM counter synchronization.
+ * - 0b1 - Software trigger can only be used by MOD and CnV synchronization, and
+ *     hardware triggers can only be used by OUTMASK and FTM counter
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_PWMSYNC field. */
+#define FTM_RD_MODE_PWMSYNC(base) ((FTM_MODE_REG(base) & FTM_MODE_PWMSYNC_MASK) >> FTM_MODE_PWMSYNC_SHIFT)
+#define FTM_BRD_MODE_PWMSYNC(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_PWMSYNC_SHIFT))
+
+/*! @brief Set the PWMSYNC field to a new value. */
+#define FTM_WR_MODE_PWMSYNC(base, value) (FTM_RMW_MODE(base, FTM_MODE_PWMSYNC_MASK, FTM_MODE_PWMSYNC(value)))
+#define FTM_BWR_MODE_PWMSYNC(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_PWMSYNC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field CAPTEST[4] (RW)
+ *
+ * Enables the capture test mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Capture test mode is disabled.
+ * - 0b1 - Capture test mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_CAPTEST field. */
+#define FTM_RD_MODE_CAPTEST(base) ((FTM_MODE_REG(base) & FTM_MODE_CAPTEST_MASK) >> FTM_MODE_CAPTEST_SHIFT)
+#define FTM_BRD_MODE_CAPTEST(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_CAPTEST_SHIFT))
+
+/*! @brief Set the CAPTEST field to a new value. */
+#define FTM_WR_MODE_CAPTEST(base, value) (FTM_RMW_MODE(base, FTM_MODE_CAPTEST_MASK, FTM_MODE_CAPTEST(value)))
+#define FTM_BWR_MODE_CAPTEST(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_CAPTEST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field FAULTM[6:5] (RW)
+ *
+ * Defines the FTM fault control mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b00 - Fault control is disabled for all channels.
+ * - 0b01 - Fault control is enabled for even channels only (channels 0, 2, 4,
+ *     and 6), and the selected mode is the manual fault clearing.
+ * - 0b10 - Fault control is enabled for all channels, and the selected mode is
+ *     the manual fault clearing.
+ * - 0b11 - Fault control is enabled for all channels, and the selected mode is
+ *     the automatic fault clearing.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FAULTM field. */
+#define FTM_RD_MODE_FAULTM(base) ((FTM_MODE_REG(base) & FTM_MODE_FAULTM_MASK) >> FTM_MODE_FAULTM_SHIFT)
+#define FTM_BRD_MODE_FAULTM(base) (FTM_RD_MODE_FAULTM(base))
+
+/*! @brief Set the FAULTM field to a new value. */
+#define FTM_WR_MODE_FAULTM(base, value) (FTM_RMW_MODE(base, FTM_MODE_FAULTM_MASK, FTM_MODE_FAULTM(value)))
+#define FTM_BWR_MODE_FAULTM(base, value) (FTM_WR_MODE_FAULTM(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field FAULTIE[7] (RW)
+ *
+ * Enables the generation of an interrupt when a fault is detected by FTM and
+ * the FTM fault control is enabled.
+ *
+ * Values:
+ * - 0b0 - Fault control interrupt is disabled.
+ * - 0b1 - Fault control interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FAULTIE field. */
+#define FTM_RD_MODE_FAULTIE(base) ((FTM_MODE_REG(base) & FTM_MODE_FAULTIE_MASK) >> FTM_MODE_FAULTIE_SHIFT)
+#define FTM_BRD_MODE_FAULTIE(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FAULTIE_SHIFT))
+
+/*! @brief Set the FAULTIE field to a new value. */
+#define FTM_WR_MODE_FAULTIE(base, value) (FTM_RMW_MODE(base, FTM_MODE_FAULTIE_MASK, FTM_MODE_FAULTIE(value)))
+#define FTM_BWR_MODE_FAULTIE(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FAULTIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SYNC - Synchronization
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SYNC - Synchronization (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the PWM synchronization. A synchronization event can
+ * perform the synchronized update of MOD, CV, and OUTMASK registers with the
+ * value of their write buffer and the FTM counter initialization. The software
+ * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
+ * potential conflict if used together when SYNCMODE = 0. Use only hardware or
+ * software triggers but not both at the same time, otherwise unpredictable behavior
+ * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
+ * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
+ * all enabled channels simultaneously. The use of the loading point selection
+ * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
+ * bits, is likely to result in unpredictable behavior. The synchronization
+ * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
+ * register) bits. See PWM synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SYNC register
+ */
+/*@{*/
+#define FTM_RD_SYNC(base)        (FTM_SYNC_REG(base))
+#define FTM_WR_SYNC(base, value) (FTM_SYNC_REG(base) = (value))
+#define FTM_RMW_SYNC(base, mask, value) (FTM_WR_SYNC(base, (FTM_RD_SYNC(base) & ~(mask)) | (value)))
+#define FTM_SET_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) |  (value)))
+#define FTM_CLR_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) & ~(value)))
+#define FTM_TOG_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SYNC bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNC, field CNTMIN[0] (RW)
+ *
+ * Selects the minimum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMIN is one, the selected loading point is when the
+ * FTM counter reaches its minimum value (CNTIN register).
+ *
+ * Values:
+ * - 0b0 - The minimum loading point is disabled.
+ * - 0b1 - The minimum loading point is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_CNTMIN field. */
+#define FTM_RD_SYNC_CNTMIN(base) ((FTM_SYNC_REG(base) & FTM_SYNC_CNTMIN_MASK) >> FTM_SYNC_CNTMIN_SHIFT)
+#define FTM_BRD_SYNC_CNTMIN(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMIN_SHIFT))
+
+/*! @brief Set the CNTMIN field to a new value. */
+#define FTM_WR_SYNC_CNTMIN(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_CNTMIN_MASK, FTM_SYNC_CNTMIN(value)))
+#define FTM_BWR_SYNC_CNTMIN(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMIN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field CNTMAX[1] (RW)
+ *
+ * Selects the maximum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
+ * counter reaches its maximum value (MOD register).
+ *
+ * Values:
+ * - 0b0 - The maximum loading point is disabled.
+ * - 0b1 - The maximum loading point is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_CNTMAX field. */
+#define FTM_RD_SYNC_CNTMAX(base) ((FTM_SYNC_REG(base) & FTM_SYNC_CNTMAX_MASK) >> FTM_SYNC_CNTMAX_SHIFT)
+#define FTM_BRD_SYNC_CNTMAX(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMAX_SHIFT))
+
+/*! @brief Set the CNTMAX field to a new value. */
+#define FTM_WR_SYNC_CNTMAX(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_CNTMAX_MASK, FTM_SYNC_CNTMAX(value)))
+#define FTM_BWR_SYNC_CNTMAX(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMAX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field REINIT[2] (RW)
+ *
+ * Determines if the FTM counter is reinitialized when the selected trigger for
+ * the synchronization is detected. The REINIT bit configures the synchronization
+ * when SYNCMODE is zero.
+ *
+ * Values:
+ * - 0b0 - FTM counter continues to count normally.
+ * - 0b1 - FTM counter is updated with its initial value when the selected
+ *     trigger is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_REINIT field. */
+#define FTM_RD_SYNC_REINIT(base) ((FTM_SYNC_REG(base) & FTM_SYNC_REINIT_MASK) >> FTM_SYNC_REINIT_SHIFT)
+#define FTM_BRD_SYNC_REINIT(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_REINIT_SHIFT))
+
+/*! @brief Set the REINIT field to a new value. */
+#define FTM_WR_SYNC_REINIT(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_REINIT_MASK, FTM_SYNC_REINIT(value)))
+#define FTM_BWR_SYNC_REINIT(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_REINIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
+ *
+ * Selects when the OUTMASK register is updated with the value of its buffer.
+ *
+ * Values:
+ * - 0b0 - OUTMASK register is updated with the value of its buffer in all
+ *     rising edges of the system clock.
+ * - 0b1 - OUTMASK register is updated with the value of its buffer only by the
+ *     PWM synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */
+#define FTM_RD_SYNC_SYNCHOM(base) ((FTM_SYNC_REG(base) & FTM_SYNC_SYNCHOM_MASK) >> FTM_SYNC_SYNCHOM_SHIFT)
+#define FTM_BRD_SYNC_SYNCHOM(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SYNCHOM_SHIFT))
+
+/*! @brief Set the SYNCHOM field to a new value. */
+#define FTM_WR_SYNC_SYNCHOM(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_SYNCHOM_MASK, FTM_SYNC_SYNCHOM(value)))
+#define FTM_BWR_SYNC_SYNCHOM(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SYNCHOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG0[4] (RW)
+ *
+ * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
+ * occurs when a rising edge is detected at the trigger 0 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG0 field. */
+#define FTM_RD_SYNC_TRIG0(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG0_MASK) >> FTM_SYNC_TRIG0_SHIFT)
+#define FTM_BRD_SYNC_TRIG0(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG0_SHIFT))
+
+/*! @brief Set the TRIG0 field to a new value. */
+#define FTM_WR_SYNC_TRIG0(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG0_MASK, FTM_SYNC_TRIG0(value)))
+#define FTM_BWR_SYNC_TRIG0(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG1[5] (RW)
+ *
+ * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
+ * happens when a rising edge is detected at the trigger 1 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG1 field. */
+#define FTM_RD_SYNC_TRIG1(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG1_MASK) >> FTM_SYNC_TRIG1_SHIFT)
+#define FTM_BRD_SYNC_TRIG1(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG1_SHIFT))
+
+/*! @brief Set the TRIG1 field to a new value. */
+#define FTM_WR_SYNC_TRIG1(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG1_MASK, FTM_SYNC_TRIG1(value)))
+#define FTM_BWR_SYNC_TRIG1(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG2[6] (RW)
+ *
+ * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
+ * happens when a rising edge is detected at the trigger 2 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG2 field. */
+#define FTM_RD_SYNC_TRIG2(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG2_MASK) >> FTM_SYNC_TRIG2_SHIFT)
+#define FTM_BRD_SYNC_TRIG2(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG2_SHIFT))
+
+/*! @brief Set the TRIG2 field to a new value. */
+#define FTM_WR_SYNC_TRIG2(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG2_MASK, FTM_SYNC_TRIG2(value)))
+#define FTM_BWR_SYNC_TRIG2(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field SWSYNC[7] (RW)
+ *
+ * Selects the software trigger as the PWM synchronization trigger. The software
+ * trigger happens when a 1 is written to SWSYNC bit.
+ *
+ * Values:
+ * - 0b0 - Software trigger is not selected.
+ * - 0b1 - Software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_SWSYNC field. */
+#define FTM_RD_SYNC_SWSYNC(base) ((FTM_SYNC_REG(base) & FTM_SYNC_SWSYNC_MASK) >> FTM_SYNC_SWSYNC_SHIFT)
+#define FTM_BRD_SYNC_SWSYNC(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SWSYNC_SHIFT))
+
+/*! @brief Set the SWSYNC field to a new value. */
+#define FTM_WR_SYNC_SWSYNC(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_SWSYNC_MASK, FTM_SYNC_SWSYNC(value)))
+#define FTM_BWR_SYNC_SWSYNC(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SWSYNC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_OUTINIT - Initial State For Channels Output
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_OUTINIT - Initial State For Channels Output (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire FTM_OUTINIT register
+ */
+/*@{*/
+#define FTM_RD_OUTINIT(base)     (FTM_OUTINIT_REG(base))
+#define FTM_WR_OUTINIT(base, value) (FTM_OUTINIT_REG(base) = (value))
+#define FTM_RMW_OUTINIT(base, mask, value) (FTM_WR_OUTINIT(base, (FTM_RD_OUTINIT(base) & ~(mask)) | (value)))
+#define FTM_SET_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) |  (value)))
+#define FTM_CLR_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) & ~(value)))
+#define FTM_TOG_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_OUTINIT bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */
+#define FTM_RD_OUTINIT_CH0OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH0OI_MASK) >> FTM_OUTINIT_CH0OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH0OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH0OI_SHIFT))
+
+/*! @brief Set the CH0OI field to a new value. */
+#define FTM_WR_OUTINIT_CH0OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH0OI_MASK, FTM_OUTINIT_CH0OI(value)))
+#define FTM_BWR_OUTINIT_CH0OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH0OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */
+#define FTM_RD_OUTINIT_CH1OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH1OI_MASK) >> FTM_OUTINIT_CH1OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH1OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH1OI_SHIFT))
+
+/*! @brief Set the CH1OI field to a new value. */
+#define FTM_WR_OUTINIT_CH1OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH1OI_MASK, FTM_OUTINIT_CH1OI(value)))
+#define FTM_BWR_OUTINIT_CH1OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH1OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */
+#define FTM_RD_OUTINIT_CH2OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH2OI_MASK) >> FTM_OUTINIT_CH2OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH2OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH2OI_SHIFT))
+
+/*! @brief Set the CH2OI field to a new value. */
+#define FTM_WR_OUTINIT_CH2OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH2OI_MASK, FTM_OUTINIT_CH2OI(value)))
+#define FTM_BWR_OUTINIT_CH2OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH2OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */
+#define FTM_RD_OUTINIT_CH3OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH3OI_MASK) >> FTM_OUTINIT_CH3OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH3OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH3OI_SHIFT))
+
+/*! @brief Set the CH3OI field to a new value. */
+#define FTM_WR_OUTINIT_CH3OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH3OI_MASK, FTM_OUTINIT_CH3OI(value)))
+#define FTM_BWR_OUTINIT_CH3OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH3OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */
+#define FTM_RD_OUTINIT_CH4OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH4OI_MASK) >> FTM_OUTINIT_CH4OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH4OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH4OI_SHIFT))
+
+/*! @brief Set the CH4OI field to a new value. */
+#define FTM_WR_OUTINIT_CH4OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH4OI_MASK, FTM_OUTINIT_CH4OI(value)))
+#define FTM_BWR_OUTINIT_CH4OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH4OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */
+#define FTM_RD_OUTINIT_CH5OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH5OI_MASK) >> FTM_OUTINIT_CH5OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH5OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH5OI_SHIFT))
+
+/*! @brief Set the CH5OI field to a new value. */
+#define FTM_WR_OUTINIT_CH5OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH5OI_MASK, FTM_OUTINIT_CH5OI(value)))
+#define FTM_BWR_OUTINIT_CH5OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH5OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */
+#define FTM_RD_OUTINIT_CH6OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH6OI_MASK) >> FTM_OUTINIT_CH6OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH6OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH6OI_SHIFT))
+
+/*! @brief Set the CH6OI field to a new value. */
+#define FTM_WR_OUTINIT_CH6OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH6OI_MASK, FTM_OUTINIT_CH6OI(value)))
+#define FTM_BWR_OUTINIT_CH6OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH6OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */
+#define FTM_RD_OUTINIT_CH7OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH7OI_MASK) >> FTM_OUTINIT_CH7OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH7OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH7OI_SHIFT))
+
+/*! @brief Set the CH7OI field to a new value. */
+#define FTM_WR_OUTINIT_CH7OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH7OI_MASK, FTM_OUTINIT_CH7OI(value)))
+#define FTM_BWR_OUTINIT_CH7OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH7OI_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_OUTMASK - Output Mask
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_OUTMASK - Output Mask (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides a mask for each FTM channel. The mask of a channel
+ * determines if its output responds, that is, it is masked or not, when a match
+ * occurs. This feature is used for BLDC control where the PWM signal is presented
+ * to an electric motor at specific times to provide electronic commutation. Any
+ * write to the OUTMASK register, stores the value in its write buffer. The
+ * register is updated with the value of its write buffer according to PWM
+ * synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_OUTMASK register
+ */
+/*@{*/
+#define FTM_RD_OUTMASK(base)     (FTM_OUTMASK_REG(base))
+#define FTM_WR_OUTMASK(base, value) (FTM_OUTMASK_REG(base) = (value))
+#define FTM_RMW_OUTMASK(base, mask, value) (FTM_WR_OUTMASK(base, (FTM_RD_OUTMASK(base) & ~(mask)) | (value)))
+#define FTM_SET_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) |  (value)))
+#define FTM_CLR_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) & ~(value)))
+#define FTM_TOG_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_OUTMASK bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */
+#define FTM_RD_OUTMASK_CH0OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH0OM_MASK) >> FTM_OUTMASK_CH0OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH0OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH0OM_SHIFT))
+
+/*! @brief Set the CH0OM field to a new value. */
+#define FTM_WR_OUTMASK_CH0OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH0OM_MASK, FTM_OUTMASK_CH0OM(value)))
+#define FTM_BWR_OUTMASK_CH0OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH0OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */
+#define FTM_RD_OUTMASK_CH1OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH1OM_MASK) >> FTM_OUTMASK_CH1OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH1OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH1OM_SHIFT))
+
+/*! @brief Set the CH1OM field to a new value. */
+#define FTM_WR_OUTMASK_CH1OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH1OM_MASK, FTM_OUTMASK_CH1OM(value)))
+#define FTM_BWR_OUTMASK_CH1OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH1OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */
+#define FTM_RD_OUTMASK_CH2OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH2OM_MASK) >> FTM_OUTMASK_CH2OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH2OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH2OM_SHIFT))
+
+/*! @brief Set the CH2OM field to a new value. */
+#define FTM_WR_OUTMASK_CH2OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH2OM_MASK, FTM_OUTMASK_CH2OM(value)))
+#define FTM_BWR_OUTMASK_CH2OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH2OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */
+#define FTM_RD_OUTMASK_CH3OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH3OM_MASK) >> FTM_OUTMASK_CH3OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH3OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH3OM_SHIFT))
+
+/*! @brief Set the CH3OM field to a new value. */
+#define FTM_WR_OUTMASK_CH3OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH3OM_MASK, FTM_OUTMASK_CH3OM(value)))
+#define FTM_BWR_OUTMASK_CH3OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH3OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */
+#define FTM_RD_OUTMASK_CH4OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH4OM_MASK) >> FTM_OUTMASK_CH4OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH4OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH4OM_SHIFT))
+
+/*! @brief Set the CH4OM field to a new value. */
+#define FTM_WR_OUTMASK_CH4OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH4OM_MASK, FTM_OUTMASK_CH4OM(value)))
+#define FTM_BWR_OUTMASK_CH4OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH4OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */
+#define FTM_RD_OUTMASK_CH5OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH5OM_MASK) >> FTM_OUTMASK_CH5OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH5OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH5OM_SHIFT))
+
+/*! @brief Set the CH5OM field to a new value. */
+#define FTM_WR_OUTMASK_CH5OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH5OM_MASK, FTM_OUTMASK_CH5OM(value)))
+#define FTM_BWR_OUTMASK_CH5OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH5OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */
+#define FTM_RD_OUTMASK_CH6OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH6OM_MASK) >> FTM_OUTMASK_CH6OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH6OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH6OM_SHIFT))
+
+/*! @brief Set the CH6OM field to a new value. */
+#define FTM_WR_OUTMASK_CH6OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH6OM_MASK, FTM_OUTMASK_CH6OM(value)))
+#define FTM_BWR_OUTMASK_CH6OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH6OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */
+#define FTM_RD_OUTMASK_CH7OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH7OM_MASK) >> FTM_OUTMASK_CH7OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH7OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH7OM_SHIFT))
+
+/*! @brief Set the CH7OM field to a new value. */
+#define FTM_WR_OUTMASK_CH7OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH7OM_MASK, FTM_OUTMASK_CH7OM(value)))
+#define FTM_BWR_OUTMASK_CH7OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH7OM_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_COMBINE - Function For Linked Channels
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_COMBINE - Function For Linked Channels (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the control bits used to configure the fault control,
+ * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
+ * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
+ * 4, and 6.
+ */
+/*!
+ * @name Constants and macros for entire FTM_COMBINE register
+ */
+/*@{*/
+#define FTM_RD_COMBINE(base)     (FTM_COMBINE_REG(base))
+#define FTM_WR_COMBINE(base, value) (FTM_COMBINE_REG(base) = (value))
+#define FTM_RMW_COMBINE(base, mask, value) (FTM_WR_COMBINE(base, (FTM_RD_COMBINE(base) & ~(mask)) | (value)))
+#define FTM_SET_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) |  (value)))
+#define FTM_CLR_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) & ~(value)))
+#define FTM_TOG_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_COMBINE bitfields
+ */
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */
+#define FTM_RD_COMBINE_COMBINE0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE0_MASK) >> FTM_COMBINE_COMBINE0_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE0_SHIFT))
+
+/*! @brief Set the COMBINE0 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE0_MASK, FTM_COMBINE_COMBINE0(value)))
+#define FTM_BWR_COMBINE_COMBINE0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP0[1] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP0 field. */
+#define FTM_RD_COMBINE_COMP0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP0_MASK) >> FTM_COMBINE_COMP0_SHIFT)
+#define FTM_BRD_COMBINE_COMP0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP0_SHIFT))
+
+/*! @brief Set the COMP0 field to a new value. */
+#define FTM_WR_COMBINE_COMP0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP0_MASK, FTM_COMBINE_COMP0(value)))
+#define FTM_BWR_COMBINE_COMP0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */
+#define FTM_RD_COMBINE_DECAPEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN0_MASK) >> FTM_COMBINE_DECAPEN0_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN0_SHIFT))
+
+/*! @brief Set the DECAPEN0 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN0_MASK, FTM_COMBINE_DECAPEN0(value)))
+#define FTM_BWR_COMBINE_DECAPEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP0[3] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */
+#define FTM_RD_COMBINE_DECAP0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP0_MASK) >> FTM_COMBINE_DECAP0_SHIFT)
+#define FTM_BRD_COMBINE_DECAP0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP0_SHIFT))
+
+/*! @brief Set the DECAP0 field to a new value. */
+#define FTM_WR_COMBINE_DECAP0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP0_MASK, FTM_COMBINE_DECAP0(value)))
+#define FTM_BWR_COMBINE_DECAP0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN0[4] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */
+#define FTM_RD_COMBINE_DTEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN0_MASK) >> FTM_COMBINE_DTEN0_SHIFT)
+#define FTM_BRD_COMBINE_DTEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN0_SHIFT))
+
+/*! @brief Set the DTEN0 field to a new value. */
+#define FTM_WR_COMBINE_DTEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN0_MASK, FTM_COMBINE_DTEN0(value)))
+#define FTM_BWR_COMBINE_DTEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */
+#define FTM_RD_COMBINE_SYNCEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN0_MASK) >> FTM_COMBINE_SYNCEN0_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN0_SHIFT))
+
+/*! @brief Set the SYNCEN0 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN0_MASK, FTM_COMBINE_SYNCEN0(value)))
+#define FTM_BWR_COMBINE_SYNCEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */
+#define FTM_RD_COMBINE_FAULTEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN0_MASK) >> FTM_COMBINE_FAULTEN0_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN0_SHIFT))
+
+/*! @brief Set the FAULTEN0 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN0_MASK, FTM_COMBINE_FAULTEN0(value)))
+#define FTM_BWR_COMBINE_FAULTEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */
+#define FTM_RD_COMBINE_COMBINE1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE1_MASK) >> FTM_COMBINE_COMBINE1_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE1_SHIFT))
+
+/*! @brief Set the COMBINE1 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE1_MASK, FTM_COMBINE_COMBINE1(value)))
+#define FTM_BWR_COMBINE_COMBINE1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP1[9] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP1 field. */
+#define FTM_RD_COMBINE_COMP1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP1_MASK) >> FTM_COMBINE_COMP1_SHIFT)
+#define FTM_BRD_COMBINE_COMP1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP1_SHIFT))
+
+/*! @brief Set the COMP1 field to a new value. */
+#define FTM_WR_COMBINE_COMP1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP1_MASK, FTM_COMBINE_COMP1(value)))
+#define FTM_BWR_COMBINE_COMP1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */
+#define FTM_RD_COMBINE_DECAPEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN1_MASK) >> FTM_COMBINE_DECAPEN1_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN1_SHIFT))
+
+/*! @brief Set the DECAPEN1 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN1_MASK, FTM_COMBINE_DECAPEN1(value)))
+#define FTM_BWR_COMBINE_DECAPEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP1[11] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */
+#define FTM_RD_COMBINE_DECAP1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP1_MASK) >> FTM_COMBINE_DECAP1_SHIFT)
+#define FTM_BRD_COMBINE_DECAP1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP1_SHIFT))
+
+/*! @brief Set the DECAP1 field to a new value. */
+#define FTM_WR_COMBINE_DECAP1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP1_MASK, FTM_COMBINE_DECAP1(value)))
+#define FTM_BWR_COMBINE_DECAP1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN1[12] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */
+#define FTM_RD_COMBINE_DTEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN1_MASK) >> FTM_COMBINE_DTEN1_SHIFT)
+#define FTM_BRD_COMBINE_DTEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN1_SHIFT))
+
+/*! @brief Set the DTEN1 field to a new value. */
+#define FTM_WR_COMBINE_DTEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN1_MASK, FTM_COMBINE_DTEN1(value)))
+#define FTM_BWR_COMBINE_DTEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */
+#define FTM_RD_COMBINE_SYNCEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN1_MASK) >> FTM_COMBINE_SYNCEN1_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN1_SHIFT))
+
+/*! @brief Set the SYNCEN1 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN1_MASK, FTM_COMBINE_SYNCEN1(value)))
+#define FTM_BWR_COMBINE_SYNCEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */
+#define FTM_RD_COMBINE_FAULTEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN1_MASK) >> FTM_COMBINE_FAULTEN1_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN1_SHIFT))
+
+/*! @brief Set the FAULTEN1 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN1_MASK, FTM_COMBINE_FAULTEN1(value)))
+#define FTM_BWR_COMBINE_FAULTEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */
+#define FTM_RD_COMBINE_COMBINE2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE2_MASK) >> FTM_COMBINE_COMBINE2_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE2_SHIFT))
+
+/*! @brief Set the COMBINE2 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE2_MASK, FTM_COMBINE_COMBINE2(value)))
+#define FTM_BWR_COMBINE_COMBINE2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP2[17] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP2 field. */
+#define FTM_RD_COMBINE_COMP2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP2_MASK) >> FTM_COMBINE_COMP2_SHIFT)
+#define FTM_BRD_COMBINE_COMP2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP2_SHIFT))
+
+/*! @brief Set the COMP2 field to a new value. */
+#define FTM_WR_COMBINE_COMP2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP2_MASK, FTM_COMBINE_COMP2(value)))
+#define FTM_BWR_COMBINE_COMP2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */
+#define FTM_RD_COMBINE_DECAPEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN2_MASK) >> FTM_COMBINE_DECAPEN2_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN2_SHIFT))
+
+/*! @brief Set the DECAPEN2 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN2_MASK, FTM_COMBINE_DECAPEN2(value)))
+#define FTM_BWR_COMBINE_DECAPEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP2[19] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */
+#define FTM_RD_COMBINE_DECAP2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP2_MASK) >> FTM_COMBINE_DECAP2_SHIFT)
+#define FTM_BRD_COMBINE_DECAP2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP2_SHIFT))
+
+/*! @brief Set the DECAP2 field to a new value. */
+#define FTM_WR_COMBINE_DECAP2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP2_MASK, FTM_COMBINE_DECAP2(value)))
+#define FTM_BWR_COMBINE_DECAP2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN2[20] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */
+#define FTM_RD_COMBINE_DTEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN2_MASK) >> FTM_COMBINE_DTEN2_SHIFT)
+#define FTM_BRD_COMBINE_DTEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN2_SHIFT))
+
+/*! @brief Set the DTEN2 field to a new value. */
+#define FTM_WR_COMBINE_DTEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN2_MASK, FTM_COMBINE_DTEN2(value)))
+#define FTM_BWR_COMBINE_DTEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */
+#define FTM_RD_COMBINE_SYNCEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN2_MASK) >> FTM_COMBINE_SYNCEN2_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN2_SHIFT))
+
+/*! @brief Set the SYNCEN2 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN2_MASK, FTM_COMBINE_SYNCEN2(value)))
+#define FTM_BWR_COMBINE_SYNCEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */
+#define FTM_RD_COMBINE_FAULTEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN2_MASK) >> FTM_COMBINE_FAULTEN2_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN2_SHIFT))
+
+/*! @brief Set the FAULTEN2 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN2_MASK, FTM_COMBINE_FAULTEN2(value)))
+#define FTM_BWR_COMBINE_FAULTEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */
+#define FTM_RD_COMBINE_COMBINE3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE3_MASK) >> FTM_COMBINE_COMBINE3_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE3_SHIFT))
+
+/*! @brief Set the COMBINE3 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE3_MASK, FTM_COMBINE_COMBINE3(value)))
+#define FTM_BWR_COMBINE_COMBINE3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP3[25] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP3 field. */
+#define FTM_RD_COMBINE_COMP3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP3_MASK) >> FTM_COMBINE_COMP3_SHIFT)
+#define FTM_BRD_COMBINE_COMP3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP3_SHIFT))
+
+/*! @brief Set the COMP3 field to a new value. */
+#define FTM_WR_COMBINE_COMP3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP3_MASK, FTM_COMBINE_COMP3(value)))
+#define FTM_BWR_COMBINE_COMP3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */
+#define FTM_RD_COMBINE_DECAPEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN3_MASK) >> FTM_COMBINE_DECAPEN3_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN3_SHIFT))
+
+/*! @brief Set the DECAPEN3 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN3_MASK, FTM_COMBINE_DECAPEN3(value)))
+#define FTM_BWR_COMBINE_DECAPEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP3[27] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */
+#define FTM_RD_COMBINE_DECAP3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP3_MASK) >> FTM_COMBINE_DECAP3_SHIFT)
+#define FTM_BRD_COMBINE_DECAP3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP3_SHIFT))
+
+/*! @brief Set the DECAP3 field to a new value. */
+#define FTM_WR_COMBINE_DECAP3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP3_MASK, FTM_COMBINE_DECAP3(value)))
+#define FTM_BWR_COMBINE_DECAP3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN3[28] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */
+#define FTM_RD_COMBINE_DTEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN3_MASK) >> FTM_COMBINE_DTEN3_SHIFT)
+#define FTM_BRD_COMBINE_DTEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN3_SHIFT))
+
+/*! @brief Set the DTEN3 field to a new value. */
+#define FTM_WR_COMBINE_DTEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN3_MASK, FTM_COMBINE_DTEN3(value)))
+#define FTM_BWR_COMBINE_DTEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */
+#define FTM_RD_COMBINE_SYNCEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN3_MASK) >> FTM_COMBINE_SYNCEN3_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN3_SHIFT))
+
+/*! @brief Set the SYNCEN3 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN3_MASK, FTM_COMBINE_SYNCEN3(value)))
+#define FTM_BWR_COMBINE_SYNCEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */
+#define FTM_RD_COMBINE_FAULTEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN3_MASK) >> FTM_COMBINE_FAULTEN3_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN3_SHIFT))
+
+/*! @brief Set the FAULTEN3 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN3_MASK, FTM_COMBINE_FAULTEN3(value)))
+#define FTM_BWR_COMBINE_FAULTEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN3_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_DEADTIME - Deadtime Insertion Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_DEADTIME - Deadtime Insertion Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the deadtime prescaler factor and deadtime value. All
+ * FTM channels use this clock prescaler and this deadtime value for the deadtime
+ * insertion.
+ */
+/*!
+ * @name Constants and macros for entire FTM_DEADTIME register
+ */
+/*@{*/
+#define FTM_RD_DEADTIME(base)    (FTM_DEADTIME_REG(base))
+#define FTM_WR_DEADTIME(base, value) (FTM_DEADTIME_REG(base) = (value))
+#define FTM_RMW_DEADTIME(base, mask, value) (FTM_WR_DEADTIME(base, (FTM_RD_DEADTIME(base) & ~(mask)) | (value)))
+#define FTM_SET_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) |  (value)))
+#define FTM_CLR_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) & ~(value)))
+#define FTM_TOG_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_DEADTIME bitfields
+ */
+
+/*!
+ * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
+ *
+ * Selects the deadtime insertion value for the deadtime counter. The deadtime
+ * counter is clocked by a scaled version of the system clock. See the description
+ * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
+ * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
+ * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
+ * This pattern continues up to a possible 63 counts. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */
+#define FTM_RD_DEADTIME_DTVAL(base) ((FTM_DEADTIME_REG(base) & FTM_DEADTIME_DTVAL_MASK) >> FTM_DEADTIME_DTVAL_SHIFT)
+#define FTM_BRD_DEADTIME_DTVAL(base) (FTM_RD_DEADTIME_DTVAL(base))
+
+/*! @brief Set the DTVAL field to a new value. */
+#define FTM_WR_DEADTIME_DTVAL(base, value) (FTM_RMW_DEADTIME(base, FTM_DEADTIME_DTVAL_MASK, FTM_DEADTIME_DTVAL(value)))
+#define FTM_BWR_DEADTIME_DTVAL(base, value) (FTM_WR_DEADTIME_DTVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
+ *
+ * Selects the division factor of the system clock. This prescaled clock is used
+ * by the deadtime counter. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0x - Divide the system clock by 1.
+ * - 0b10 - Divide the system clock by 4.
+ * - 0b11 - Divide the system clock by 16.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_DEADTIME_DTPS field. */
+#define FTM_RD_DEADTIME_DTPS(base) ((FTM_DEADTIME_REG(base) & FTM_DEADTIME_DTPS_MASK) >> FTM_DEADTIME_DTPS_SHIFT)
+#define FTM_BRD_DEADTIME_DTPS(base) (FTM_RD_DEADTIME_DTPS(base))
+
+/*! @brief Set the DTPS field to a new value. */
+#define FTM_WR_DEADTIME_DTPS(base, value) (FTM_RMW_DEADTIME(base, FTM_DEADTIME_DTPS_MASK, FTM_DEADTIME_DTPS(value)))
+#define FTM_BWR_DEADTIME_DTPS(base, value) (FTM_WR_DEADTIME_DTPS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_EXTTRIG - FTM External Trigger
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_EXTTRIG - FTM External Trigger (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register: Indicates when a channel trigger was generated Enables the
+ * generation of a trigger when the FTM counter is equal to its initial value
+ * Selects which channels are used in the generation of the channel triggers Several
+ * channels can be selected to generate multiple triggers in one PWM period.
+ * Channels 6 and 7 are not used to generate channel triggers.
+ */
+/*!
+ * @name Constants and macros for entire FTM_EXTTRIG register
+ */
+/*@{*/
+#define FTM_RD_EXTTRIG(base)     (FTM_EXTTRIG_REG(base))
+#define FTM_WR_EXTTRIG(base, value) (FTM_EXTTRIG_REG(base) = (value))
+#define FTM_RMW_EXTTRIG(base, mask, value) (FTM_WR_EXTTRIG(base, (FTM_RD_EXTTRIG(base) & ~(mask)) | (value)))
+#define FTM_SET_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) |  (value)))
+#define FTM_CLR_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) & ~(value)))
+#define FTM_TOG_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_EXTTRIG bitfields
+ */
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */
+#define FTM_RD_EXTTRIG_CH2TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH2TRIG_MASK) >> FTM_EXTTRIG_CH2TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH2TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH2TRIG_SHIFT))
+
+/*! @brief Set the CH2TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH2TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH2TRIG_MASK, FTM_EXTTRIG_CH2TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH2TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH2TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */
+#define FTM_RD_EXTTRIG_CH3TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH3TRIG_MASK) >> FTM_EXTTRIG_CH3TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH3TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH3TRIG_SHIFT))
+
+/*! @brief Set the CH3TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH3TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH3TRIG_MASK, FTM_EXTTRIG_CH3TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH3TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH3TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */
+#define FTM_RD_EXTTRIG_CH4TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH4TRIG_MASK) >> FTM_EXTTRIG_CH4TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH4TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH4TRIG_SHIFT))
+
+/*! @brief Set the CH4TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH4TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH4TRIG_MASK, FTM_EXTTRIG_CH4TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH4TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH4TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */
+#define FTM_RD_EXTTRIG_CH5TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH5TRIG_MASK) >> FTM_EXTTRIG_CH5TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH5TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH5TRIG_SHIFT))
+
+/*! @brief Set the CH5TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH5TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH5TRIG_MASK, FTM_EXTTRIG_CH5TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH5TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH5TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */
+#define FTM_RD_EXTTRIG_CH0TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH0TRIG_MASK) >> FTM_EXTTRIG_CH0TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH0TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH0TRIG_SHIFT))
+
+/*! @brief Set the CH0TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH0TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH0TRIG_MASK, FTM_EXTTRIG_CH0TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH0TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH0TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */
+#define FTM_RD_EXTTRIG_CH1TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH1TRIG_MASK) >> FTM_EXTTRIG_CH1TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH1TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH1TRIG_SHIFT))
+
+/*! @brief Set the CH1TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH1TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH1TRIG_MASK, FTM_EXTTRIG_CH1TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH1TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH1TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
+ *
+ * Enables the generation of the trigger when the FTM counter is equal to the
+ * CNTIN register.
+ *
+ * Values:
+ * - 0b0 - The generation of initialization trigger is disabled.
+ * - 0b1 - The generation of initialization trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */
+#define FTM_RD_EXTTRIG_INITTRIGEN(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_INITTRIGEN_MASK) >> FTM_EXTTRIG_INITTRIGEN_SHIFT)
+#define FTM_BRD_EXTTRIG_INITTRIGEN(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_INITTRIGEN_SHIFT))
+
+/*! @brief Set the INITTRIGEN field to a new value. */
+#define FTM_WR_EXTTRIG_INITTRIGEN(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_INITTRIGEN_MASK, FTM_EXTTRIG_INITTRIGEN(value)))
+#define FTM_BWR_EXTTRIG_INITTRIGEN(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_INITTRIGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
+ *
+ * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
+ * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
+ * has no effect. If another channel trigger is generated before the clearing
+ * sequence is completed, the sequence is reset so TRIGF remains set after the clear
+ * sequence is completed for the earlier TRIGF.
+ *
+ * Values:
+ * - 0b0 - No channel trigger was generated.
+ * - 0b1 - A channel trigger was generated.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */
+#define FTM_RD_EXTTRIG_TRIGF(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_TRIGF_MASK) >> FTM_EXTTRIG_TRIGF_SHIFT)
+#define FTM_BRD_EXTTRIG_TRIGF(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_TRIGF_SHIFT))
+
+/*! @brief Set the TRIGF field to a new value. */
+#define FTM_WR_EXTTRIG_TRIGF(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_TRIGF_MASK, FTM_EXTTRIG_TRIGF(value)))
+#define FTM_BWR_EXTTRIG_TRIGF(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_TRIGF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_POL - Channels Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_POL - Channels Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the output polarity of the FTM channels. The safe value
+ * that is driven in a channel output when the fault control is enabled and a
+ * fault condition is detected is the inactive state of the channel. That is, the
+ * safe value of a channel is the value of its POL bit.
+ */
+/*!
+ * @name Constants and macros for entire FTM_POL register
+ */
+/*@{*/
+#define FTM_RD_POL(base)         (FTM_POL_REG(base))
+#define FTM_WR_POL(base, value)  (FTM_POL_REG(base) = (value))
+#define FTM_RMW_POL(base, mask, value) (FTM_WR_POL(base, (FTM_RD_POL(base) & ~(mask)) | (value)))
+#define FTM_SET_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) |  (value)))
+#define FTM_CLR_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) & ~(value)))
+#define FTM_TOG_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_POL bitfields
+ */
+
+/*!
+ * @name Register FTM_POL, field POL0[0] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL0 field. */
+#define FTM_RD_POL_POL0(base) ((FTM_POL_REG(base) & FTM_POL_POL0_MASK) >> FTM_POL_POL0_SHIFT)
+#define FTM_BRD_POL_POL0(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL0_SHIFT))
+
+/*! @brief Set the POL0 field to a new value. */
+#define FTM_WR_POL_POL0(base, value) (FTM_RMW_POL(base, FTM_POL_POL0_MASK, FTM_POL_POL0(value)))
+#define FTM_BWR_POL_POL0(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL1[1] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL1 field. */
+#define FTM_RD_POL_POL1(base) ((FTM_POL_REG(base) & FTM_POL_POL1_MASK) >> FTM_POL_POL1_SHIFT)
+#define FTM_BRD_POL_POL1(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL1_SHIFT))
+
+/*! @brief Set the POL1 field to a new value. */
+#define FTM_WR_POL_POL1(base, value) (FTM_RMW_POL(base, FTM_POL_POL1_MASK, FTM_POL_POL1(value)))
+#define FTM_BWR_POL_POL1(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL2[2] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL2 field. */
+#define FTM_RD_POL_POL2(base) ((FTM_POL_REG(base) & FTM_POL_POL2_MASK) >> FTM_POL_POL2_SHIFT)
+#define FTM_BRD_POL_POL2(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL2_SHIFT))
+
+/*! @brief Set the POL2 field to a new value. */
+#define FTM_WR_POL_POL2(base, value) (FTM_RMW_POL(base, FTM_POL_POL2_MASK, FTM_POL_POL2(value)))
+#define FTM_BWR_POL_POL2(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL3[3] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL3 field. */
+#define FTM_RD_POL_POL3(base) ((FTM_POL_REG(base) & FTM_POL_POL3_MASK) >> FTM_POL_POL3_SHIFT)
+#define FTM_BRD_POL_POL3(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL3_SHIFT))
+
+/*! @brief Set the POL3 field to a new value. */
+#define FTM_WR_POL_POL3(base, value) (FTM_RMW_POL(base, FTM_POL_POL3_MASK, FTM_POL_POL3(value)))
+#define FTM_BWR_POL_POL3(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL4[4] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL4 field. */
+#define FTM_RD_POL_POL4(base) ((FTM_POL_REG(base) & FTM_POL_POL4_MASK) >> FTM_POL_POL4_SHIFT)
+#define FTM_BRD_POL_POL4(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL4_SHIFT))
+
+/*! @brief Set the POL4 field to a new value. */
+#define FTM_WR_POL_POL4(base, value) (FTM_RMW_POL(base, FTM_POL_POL4_MASK, FTM_POL_POL4(value)))
+#define FTM_BWR_POL_POL4(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL5[5] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL5 field. */
+#define FTM_RD_POL_POL5(base) ((FTM_POL_REG(base) & FTM_POL_POL5_MASK) >> FTM_POL_POL5_SHIFT)
+#define FTM_BRD_POL_POL5(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL5_SHIFT))
+
+/*! @brief Set the POL5 field to a new value. */
+#define FTM_WR_POL_POL5(base, value) (FTM_RMW_POL(base, FTM_POL_POL5_MASK, FTM_POL_POL5(value)))
+#define FTM_BWR_POL_POL5(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL6[6] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL6 field. */
+#define FTM_RD_POL_POL6(base) ((FTM_POL_REG(base) & FTM_POL_POL6_MASK) >> FTM_POL_POL6_SHIFT)
+#define FTM_BRD_POL_POL6(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL6_SHIFT))
+
+/*! @brief Set the POL6 field to a new value. */
+#define FTM_WR_POL_POL6(base, value) (FTM_RMW_POL(base, FTM_POL_POL6_MASK, FTM_POL_POL6(value)))
+#define FTM_BWR_POL_POL6(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL7[7] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL7 field. */
+#define FTM_RD_POL_POL7(base) ((FTM_POL_REG(base) & FTM_POL_POL7_MASK) >> FTM_POL_POL7_SHIFT)
+#define FTM_BRD_POL_POL7(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL7_SHIFT))
+
+/*! @brief Set the POL7 field to a new value. */
+#define FTM_WR_POL_POL7(base, value) (FTM_RMW_POL(base, FTM_POL_POL7_MASK, FTM_POL_POL7(value)))
+#define FTM_BWR_POL_POL7(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FMS - Fault Mode Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FMS - Fault Mode Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the fault detection flags, write protection enable
+ * bit, and the logic OR of the enabled fault inputs.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FMS register
+ */
+/*@{*/
+#define FTM_RD_FMS(base)         (FTM_FMS_REG(base))
+#define FTM_WR_FMS(base, value)  (FTM_FMS_REG(base) = (value))
+#define FTM_RMW_FMS(base, mask, value) (FTM_WR_FMS(base, (FTM_RD_FMS(base) & ~(mask)) | (value)))
+#define FTM_SET_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) |  (value)))
+#define FTM_CLR_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) & ~(value)))
+#define FTM_TOG_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FMS bitfields
+ */
+
+/*!
+ * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
+ * by reading the FMS register while FAULTF0 is set and then writing a 0 to
+ * FAULTF0 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF0 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF0 field. */
+#define FTM_RD_FMS_FAULTF0(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF0_MASK) >> FTM_FMS_FAULTF0_SHIFT)
+#define FTM_BRD_FMS_FAULTF0(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF0_SHIFT))
+
+/*! @brief Set the FAULTF0 field to a new value. */
+#define FTM_WR_FMS_FAULTF0(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF0_MASK, FTM_FMS_FAULTF0(value)))
+#define FTM_BWR_FMS_FAULTF0(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
+ * by reading the FMS register while FAULTF1 is set and then writing a 0 to
+ * FAULTF1 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF1 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF1 field. */
+#define FTM_RD_FMS_FAULTF1(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF1_MASK) >> FTM_FMS_FAULTF1_SHIFT)
+#define FTM_BRD_FMS_FAULTF1(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF1_SHIFT))
+
+/*! @brief Set the FAULTF1 field to a new value. */
+#define FTM_WR_FMS_FAULTF1(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF1_MASK, FTM_FMS_FAULTF1(value)))
+#define FTM_BWR_FMS_FAULTF1(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
+ * by reading the FMS register while FAULTF2 is set and then writing a 0 to
+ * FAULTF2 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF2 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF2 field. */
+#define FTM_RD_FMS_FAULTF2(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF2_MASK) >> FTM_FMS_FAULTF2_SHIFT)
+#define FTM_BRD_FMS_FAULTF2(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF2_SHIFT))
+
+/*! @brief Set the FAULTF2 field to a new value. */
+#define FTM_WR_FMS_FAULTF2(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF2_MASK, FTM_FMS_FAULTF2(value)))
+#define FTM_BWR_FMS_FAULTF2(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
+ * by reading the FMS register while FAULTF3 is set and then writing a 0 to
+ * FAULTF3 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF3 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF3 field. */
+#define FTM_RD_FMS_FAULTF3(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF3_MASK) >> FTM_FMS_FAULTF3_SHIFT)
+#define FTM_BRD_FMS_FAULTF3(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF3_SHIFT))
+
+/*! @brief Set the FAULTF3 field to a new value. */
+#define FTM_WR_FMS_FAULTF3(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF3_MASK, FTM_FMS_FAULTF3(value)))
+#define FTM_BWR_FMS_FAULTF3(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTIN[5] (RO)
+ *
+ * Represents the logic OR of the enabled fault inputs after their filter (if
+ * their filter is enabled) when fault control is enabled.
+ *
+ * Values:
+ * - 0b0 - The logic OR of the enabled fault inputs is 0.
+ * - 0b1 - The logic OR of the enabled fault inputs is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTIN field. */
+#define FTM_RD_FMS_FAULTIN(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTIN_MASK) >> FTM_FMS_FAULTIN_SHIFT)
+#define FTM_BRD_FMS_FAULTIN(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTIN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field WPEN[6] (RW)
+ *
+ * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
+ * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
+ * WPDIS. Writing 0 to WPEN has no effect.
+ *
+ * Values:
+ * - 0b0 - Write protection is disabled. Write protected bits can be written.
+ * - 0b1 - Write protection is enabled. Write protected bits cannot be written.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_WPEN field. */
+#define FTM_RD_FMS_WPEN(base) ((FTM_FMS_REG(base) & FTM_FMS_WPEN_MASK) >> FTM_FMS_WPEN_SHIFT)
+#define FTM_BRD_FMS_WPEN(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_WPEN_SHIFT))
+
+/*! @brief Set the WPEN field to a new value. */
+#define FTM_WR_FMS_WPEN(base, value) (FTM_RMW_FMS(base, FTM_FMS_WPEN_MASK, FTM_FMS_WPEN(value)))
+#define FTM_BWR_FMS_WPEN(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_WPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
+ *
+ * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
+ * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
+ * a 0 to FAULTF while there is no existing fault condition at the enabled fault
+ * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
+ * detected in an enabled fault input before the clearing sequence is completed, the
+ * sequence is reset so FAULTF remains set after the clearing sequence is
+ * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
+ * are cleared individually.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected.
+ * - 0b1 - A fault condition was detected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF field. */
+#define FTM_RD_FMS_FAULTF(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF_MASK) >> FTM_FMS_FAULTF_SHIFT)
+#define FTM_BRD_FMS_FAULTF(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF_SHIFT))
+
+/*! @brief Set the FAULTF field to a new value. */
+#define FTM_WR_FMS_FAULTF(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF_MASK, FTM_FMS_FAULTF(value)))
+#define FTM_BWR_FMS_FAULTF(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FILTER - Input Capture Filter Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FILTER - Input Capture Filter Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the inputs of channels. Channels
+ * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
+ * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
+ * in input modes. Failure to do this could result in a missing valid signal.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FILTER register
+ */
+/*@{*/
+#define FTM_RD_FILTER(base)      (FTM_FILTER_REG(base))
+#define FTM_WR_FILTER(base, value) (FTM_FILTER_REG(base) = (value))
+#define FTM_RMW_FILTER(base, mask, value) (FTM_WR_FILTER(base, (FTM_RD_FILTER(base) & ~(mask)) | (value)))
+#define FTM_SET_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) |  (value)))
+#define FTM_CLR_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) & ~(value)))
+#define FTM_TOG_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FILTER bitfields
+ */
+
+/*!
+ * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */
+#define FTM_RD_FILTER_CH0FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH0FVAL_MASK) >> FTM_FILTER_CH0FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH0FVAL(base) (FTM_RD_FILTER_CH0FVAL(base))
+
+/*! @brief Set the CH0FVAL field to a new value. */
+#define FTM_WR_FILTER_CH0FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH0FVAL_MASK, FTM_FILTER_CH0FVAL(value)))
+#define FTM_BWR_FILTER_CH0FVAL(base, value) (FTM_WR_FILTER_CH0FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */
+#define FTM_RD_FILTER_CH1FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH1FVAL_MASK) >> FTM_FILTER_CH1FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH1FVAL(base) (FTM_RD_FILTER_CH1FVAL(base))
+
+/*! @brief Set the CH1FVAL field to a new value. */
+#define FTM_WR_FILTER_CH1FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH1FVAL_MASK, FTM_FILTER_CH1FVAL(value)))
+#define FTM_BWR_FILTER_CH1FVAL(base, value) (FTM_WR_FILTER_CH1FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */
+#define FTM_RD_FILTER_CH2FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH2FVAL_MASK) >> FTM_FILTER_CH2FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH2FVAL(base) (FTM_RD_FILTER_CH2FVAL(base))
+
+/*! @brief Set the CH2FVAL field to a new value. */
+#define FTM_WR_FILTER_CH2FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH2FVAL_MASK, FTM_FILTER_CH2FVAL(value)))
+#define FTM_BWR_FILTER_CH2FVAL(base, value) (FTM_WR_FILTER_CH2FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */
+#define FTM_RD_FILTER_CH3FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH3FVAL_MASK) >> FTM_FILTER_CH3FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH3FVAL(base) (FTM_RD_FILTER_CH3FVAL(base))
+
+/*! @brief Set the CH3FVAL field to a new value. */
+#define FTM_WR_FILTER_CH3FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH3FVAL_MASK, FTM_FILTER_CH3FVAL(value)))
+#define FTM_BWR_FILTER_CH3FVAL(base, value) (FTM_WR_FILTER_CH3FVAL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FLTCTRL - Fault Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FLTCTRL - Fault Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the fault inputs, enables the
+ * fault inputs and the fault inputs filter.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FLTCTRL register
+ */
+/*@{*/
+#define FTM_RD_FLTCTRL(base)     (FTM_FLTCTRL_REG(base))
+#define FTM_WR_FLTCTRL(base, value) (FTM_FLTCTRL_REG(base) = (value))
+#define FTM_RMW_FLTCTRL(base, mask, value) (FTM_WR_FLTCTRL(base, (FTM_RD_FLTCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) |  (value)))
+#define FTM_CLR_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) & ~(value)))
+#define FTM_TOG_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FLTCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */
+#define FTM_RD_FLTCTRL_FAULT0EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT0EN_MASK) >> FTM_FLTCTRL_FAULT0EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT0EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT0EN_SHIFT))
+
+/*! @brief Set the FAULT0EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT0EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT0EN_MASK, FTM_FLTCTRL_FAULT0EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT0EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */
+#define FTM_RD_FLTCTRL_FAULT1EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT1EN_MASK) >> FTM_FLTCTRL_FAULT1EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT1EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT1EN_SHIFT))
+
+/*! @brief Set the FAULT1EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT1EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT1EN_MASK, FTM_FLTCTRL_FAULT1EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT1EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */
+#define FTM_RD_FLTCTRL_FAULT2EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT2EN_MASK) >> FTM_FLTCTRL_FAULT2EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT2EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT2EN_SHIFT))
+
+/*! @brief Set the FAULT2EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT2EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT2EN_MASK, FTM_FLTCTRL_FAULT2EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT2EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */
+#define FTM_RD_FLTCTRL_FAULT3EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT3EN_MASK) >> FTM_FLTCTRL_FAULT3EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT3EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT3EN_SHIFT))
+
+/*! @brief Set the FAULT3EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT3EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT3EN_MASK, FTM_FLTCTRL_FAULT3EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT3EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT3EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */
+#define FTM_RD_FLTCTRL_FFLTR0EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR0EN_MASK) >> FTM_FLTCTRL_FFLTR0EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR0EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR0EN_SHIFT))
+
+/*! @brief Set the FFLTR0EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR0EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR0EN_MASK, FTM_FLTCTRL_FFLTR0EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR0EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */
+#define FTM_RD_FLTCTRL_FFLTR1EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR1EN_MASK) >> FTM_FLTCTRL_FFLTR1EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR1EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR1EN_SHIFT))
+
+/*! @brief Set the FFLTR1EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR1EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR1EN_MASK, FTM_FLTCTRL_FFLTR1EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR1EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */
+#define FTM_RD_FLTCTRL_FFLTR2EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR2EN_MASK) >> FTM_FLTCTRL_FFLTR2EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR2EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR2EN_SHIFT))
+
+/*! @brief Set the FFLTR2EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR2EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR2EN_MASK, FTM_FLTCTRL_FFLTR2EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR2EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */
+#define FTM_RD_FLTCTRL_FFLTR3EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR3EN_MASK) >> FTM_FLTCTRL_FFLTR3EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR3EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR3EN_SHIFT))
+
+/*! @brief Set the FFLTR3EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR3EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR3EN_MASK, FTM_FLTCTRL_FFLTR3EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR3EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR3EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
+ *
+ * Selects the filter value for the fault inputs. The fault filter is disabled
+ * when the value is zero. Writing to this field has immediate effect and must be
+ * done only when the fault control or all fault inputs are disabled. Failure to
+ * do this could result in a missing fault detection.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */
+#define FTM_RD_FLTCTRL_FFVAL(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFVAL_MASK) >> FTM_FLTCTRL_FFVAL_SHIFT)
+#define FTM_BRD_FLTCTRL_FFVAL(base) (FTM_RD_FLTCTRL_FFVAL(base))
+
+/*! @brief Set the FFVAL field to a new value. */
+#define FTM_WR_FLTCTRL_FFVAL(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFVAL_MASK, FTM_FLTCTRL_FFVAL(value)))
+#define FTM_BWR_FLTCTRL_FFVAL(base, value) (FTM_WR_FLTCTRL_FFVAL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_QDCTRL - Quadrature Decoder Control And Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has the control and status bits for the Quadrature Decoder mode.
+ */
+/*!
+ * @name Constants and macros for entire FTM_QDCTRL register
+ */
+/*@{*/
+#define FTM_RD_QDCTRL(base)      (FTM_QDCTRL_REG(base))
+#define FTM_WR_QDCTRL(base, value) (FTM_QDCTRL_REG(base) = (value))
+#define FTM_RMW_QDCTRL(base, mask, value) (FTM_WR_QDCTRL(base, (FTM_RD_QDCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) |  (value)))
+#define FTM_CLR_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) & ~(value)))
+#define FTM_TOG_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_QDCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
+ *
+ * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
+ * signals control the FTM counter direction. The Quadrature Decoder mode has
+ * precedence over the other modes. See #ModeSel1Table. This field is write protected.
+ * It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Quadrature Decoder mode is disabled.
+ * - 0b1 - Quadrature Decoder mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */
+#define FTM_RD_QDCTRL_QUADEN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADEN_MASK) >> FTM_QDCTRL_QUADEN_SHIFT)
+#define FTM_BRD_QDCTRL_QUADEN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADEN_SHIFT))
+
+/*! @brief Set the QUADEN field to a new value. */
+#define FTM_WR_QDCTRL_QUADEN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_QUADEN_MASK, FTM_QDCTRL_QUADEN(value)))
+#define FTM_BWR_QDCTRL_QUADEN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
+ *
+ * Indicates if the TOF bit was set on the top or the bottom of counting.
+ *
+ * Values:
+ * - 0b0 - TOF bit was set on the bottom of counting. There was an FTM counter
+ *     decrement and FTM counter changes from its minimum value (CNTIN register)
+ *     to its maximum value (MOD register).
+ * - 0b1 - TOF bit was set on the top of counting. There was an FTM counter
+ *     increment and FTM counter changes from its maximum value (MOD register) to its
+ *     minimum value (CNTIN register).
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */
+#define FTM_RD_QDCTRL_TOFDIR(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_TOFDIR_MASK) >> FTM_QDCTRL_TOFDIR_SHIFT)
+#define FTM_BRD_QDCTRL_TOFDIR(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_TOFDIR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
+ *
+ * Indicates the counting direction.
+ *
+ * Values:
+ * - 0b0 - Counting direction is decreasing (FTM counter decrement).
+ * - 0b1 - Counting direction is increasing (FTM counter increment).
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */
+#define FTM_RD_QDCTRL_QUADIR(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADIR_MASK) >> FTM_QDCTRL_QUADIR_SHIFT)
+#define FTM_BRD_QDCTRL_QUADIR(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADIR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
+ *
+ * Selects the encoding mode used in the Quadrature Decoder mode.
+ *
+ * Values:
+ * - 0b0 - Phase A and phase B encoding mode.
+ * - 0b1 - Count and direction encoding mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */
+#define FTM_RD_QDCTRL_QUADMODE(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADMODE_MASK) >> FTM_QDCTRL_QUADMODE_SHIFT)
+#define FTM_BRD_QDCTRL_QUADMODE(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADMODE_SHIFT))
+
+/*! @brief Set the QUADMODE field to a new value. */
+#define FTM_WR_QDCTRL_QUADMODE(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_QUADMODE_MASK, FTM_QDCTRL_QUADMODE(value)))
+#define FTM_BWR_QDCTRL_QUADMODE(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase B input.
+ *
+ * Values:
+ * - 0b0 - Normal polarity. Phase B input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 0b1 - Inverted polarity. Phase B input signal is inverted before
+ *     identifying the rising and falling edges of this signal.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */
+#define FTM_RD_QDCTRL_PHBPOL(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHBPOL_MASK) >> FTM_QDCTRL_PHBPOL_SHIFT)
+#define FTM_BRD_QDCTRL_PHBPOL(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBPOL_SHIFT))
+
+/*! @brief Set the PHBPOL field to a new value. */
+#define FTM_WR_QDCTRL_PHBPOL(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHBPOL_MASK, FTM_QDCTRL_PHBPOL(value)))
+#define FTM_BWR_QDCTRL_PHBPOL(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase A input.
+ *
+ * Values:
+ * - 0b0 - Normal polarity. Phase A input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 0b1 - Inverted polarity. Phase A input signal is inverted before
+ *     identifying the rising and falling edges of this signal.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */
+#define FTM_RD_QDCTRL_PHAPOL(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHAPOL_MASK) >> FTM_QDCTRL_PHAPOL_SHIFT)
+#define FTM_BRD_QDCTRL_PHAPOL(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAPOL_SHIFT))
+
+/*! @brief Set the PHAPOL field to a new value. */
+#define FTM_WR_QDCTRL_PHAPOL(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHAPOL_MASK, FTM_QDCTRL_PHAPOL(value)))
+#define FTM_BWR_QDCTRL_PHAPOL(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase B input. The filter value
+ * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
+ * filter is also disabled when CH1FVAL is zero.
+ *
+ * Values:
+ * - 0b0 - Phase B input filter is disabled.
+ * - 0b1 - Phase B input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */
+#define FTM_RD_QDCTRL_PHBFLTREN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHBFLTREN_MASK) >> FTM_QDCTRL_PHBFLTREN_SHIFT)
+#define FTM_BRD_QDCTRL_PHBFLTREN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBFLTREN_SHIFT))
+
+/*! @brief Set the PHBFLTREN field to a new value. */
+#define FTM_WR_QDCTRL_PHBFLTREN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHBFLTREN_MASK, FTM_QDCTRL_PHBFLTREN(value)))
+#define FTM_BWR_QDCTRL_PHBFLTREN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBFLTREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase A input. The filter value
+ * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
+ * filter is also disabled when CH0FVAL is zero.
+ *
+ * Values:
+ * - 0b0 - Phase A input filter is disabled.
+ * - 0b1 - Phase A input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */
+#define FTM_RD_QDCTRL_PHAFLTREN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHAFLTREN_MASK) >> FTM_QDCTRL_PHAFLTREN_SHIFT)
+#define FTM_BRD_QDCTRL_PHAFLTREN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAFLTREN_SHIFT))
+
+/*! @brief Set the PHAFLTREN field to a new value. */
+#define FTM_WR_QDCTRL_PHAFLTREN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHAFLTREN_MASK, FTM_QDCTRL_PHAFLTREN(value)))
+#define FTM_BWR_QDCTRL_PHAFLTREN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAFLTREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CONF - Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CONF - Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the number of times that the FTM counter overflow
+ * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
+ * of an external global time base, and the global time base signal generation.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CONF register
+ */
+/*@{*/
+#define FTM_RD_CONF(base)        (FTM_CONF_REG(base))
+#define FTM_WR_CONF(base, value) (FTM_CONF_REG(base) = (value))
+#define FTM_RMW_CONF(base, mask, value) (FTM_WR_CONF(base, (FTM_RD_CONF(base) & ~(mask)) | (value)))
+#define FTM_SET_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) |  (value)))
+#define FTM_CLR_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) & ~(value)))
+#define FTM_TOG_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CONF bitfields
+ */
+
+/*!
+ * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
+ *
+ * Selects the ratio between the number of counter overflows to the number of
+ * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
+ * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
+ * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
+ * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
+ * first counter overflow but not for the next 3 overflows. This pattern continues
+ * up to a maximum of 31.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_NUMTOF field. */
+#define FTM_RD_CONF_NUMTOF(base) ((FTM_CONF_REG(base) & FTM_CONF_NUMTOF_MASK) >> FTM_CONF_NUMTOF_SHIFT)
+#define FTM_BRD_CONF_NUMTOF(base) (FTM_RD_CONF_NUMTOF(base))
+
+/*! @brief Set the NUMTOF field to a new value. */
+#define FTM_WR_CONF_NUMTOF(base, value) (FTM_RMW_CONF(base, FTM_CONF_NUMTOF_MASK, FTM_CONF_NUMTOF(value)))
+#define FTM_BWR_CONF_NUMTOF(base, value) (FTM_WR_CONF_NUMTOF(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
+ *
+ * Selects the FTM behavior in BDM mode. See BDM mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_BDMMODE field. */
+#define FTM_RD_CONF_BDMMODE(base) ((FTM_CONF_REG(base) & FTM_CONF_BDMMODE_MASK) >> FTM_CONF_BDMMODE_SHIFT)
+#define FTM_BRD_CONF_BDMMODE(base) (FTM_RD_CONF_BDMMODE(base))
+
+/*! @brief Set the BDMMODE field to a new value. */
+#define FTM_WR_CONF_BDMMODE(base, value) (FTM_RMW_CONF(base, FTM_CONF_BDMMODE_MASK, FTM_CONF_BDMMODE(value)))
+#define FTM_BWR_CONF_BDMMODE(base, value) (FTM_WR_CONF_BDMMODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field GTBEEN[9] (RW)
+ *
+ * Configures the FTM to use an external global time base signal that is
+ * generated by another FTM.
+ *
+ * Values:
+ * - 0b0 - Use of an external global time base is disabled.
+ * - 0b1 - Use of an external global time base is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_GTBEEN field. */
+#define FTM_RD_CONF_GTBEEN(base) ((FTM_CONF_REG(base) & FTM_CONF_GTBEEN_MASK) >> FTM_CONF_GTBEEN_SHIFT)
+#define FTM_BRD_CONF_GTBEEN(base) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEEN_SHIFT))
+
+/*! @brief Set the GTBEEN field to a new value. */
+#define FTM_WR_CONF_GTBEEN(base, value) (FTM_RMW_CONF(base, FTM_CONF_GTBEEN_MASK, FTM_CONF_GTBEEN(value)))
+#define FTM_BWR_CONF_GTBEEN(base, value) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field GTBEOUT[10] (RW)
+ *
+ * Enables the global time base signal generation to other FTMs.
+ *
+ * Values:
+ * - 0b0 - A global time base signal generation is disabled.
+ * - 0b1 - A global time base signal generation is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_GTBEOUT field. */
+#define FTM_RD_CONF_GTBEOUT(base) ((FTM_CONF_REG(base) & FTM_CONF_GTBEOUT_MASK) >> FTM_CONF_GTBEOUT_SHIFT)
+#define FTM_BRD_CONF_GTBEOUT(base) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEOUT_SHIFT))
+
+/*! @brief Set the GTBEOUT field to a new value. */
+#define FTM_WR_CONF_GTBEOUT(base, value) (FTM_RMW_CONF(base, FTM_CONF_GTBEOUT_MASK, FTM_CONF_GTBEOUT(value)))
+#define FTM_BWR_CONF_GTBEOUT(base, value) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEOUT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FLTPOL - FTM Fault Input Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FLTPOL - FTM Fault Input Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the fault inputs polarity.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FLTPOL register
+ */
+/*@{*/
+#define FTM_RD_FLTPOL(base)      (FTM_FLTPOL_REG(base))
+#define FTM_WR_FLTPOL(base, value) (FTM_FLTPOL_REG(base) = (value))
+#define FTM_RMW_FLTPOL(base, mask, value) (FTM_WR_FLTPOL(base, (FTM_RD_FLTPOL(base) & ~(mask)) | (value)))
+#define FTM_SET_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) |  (value)))
+#define FTM_CLR_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) & ~(value)))
+#define FTM_TOG_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FLTPOL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */
+#define FTM_RD_FLTPOL_FLT0POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT0POL_MASK) >> FTM_FLTPOL_FLT0POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT0POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT0POL_SHIFT))
+
+/*! @brief Set the FLT0POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT0POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT0POL_MASK, FTM_FLTPOL_FLT0POL(value)))
+#define FTM_BWR_FLTPOL_FLT0POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT0POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */
+#define FTM_RD_FLTPOL_FLT1POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT1POL_MASK) >> FTM_FLTPOL_FLT1POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT1POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT1POL_SHIFT))
+
+/*! @brief Set the FLT1POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT1POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT1POL_MASK, FTM_FLTPOL_FLT1POL(value)))
+#define FTM_BWR_FLTPOL_FLT1POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT1POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */
+#define FTM_RD_FLTPOL_FLT2POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT2POL_MASK) >> FTM_FLTPOL_FLT2POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT2POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT2POL_SHIFT))
+
+/*! @brief Set the FLT2POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT2POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT2POL_MASK, FTM_FLTPOL_FLT2POL(value)))
+#define FTM_BWR_FLTPOL_FLT2POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT2POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */
+#define FTM_RD_FLTPOL_FLT3POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT3POL_MASK) >> FTM_FLTPOL_FLT3POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT3POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT3POL_SHIFT))
+
+/*! @brief Set the FLT3POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT3POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT3POL_MASK, FTM_FLTPOL_FLT3POL(value)))
+#define FTM_BWR_FLTPOL_FLT3POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT3POL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SYNCONF - Synchronization Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SYNCONF - Synchronization Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
+ * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
+ * 0, 1, 2, when the hardware trigger j is detected.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SYNCONF register
+ */
+/*@{*/
+#define FTM_RD_SYNCONF(base)     (FTM_SYNCONF_REG(base))
+#define FTM_WR_SYNCONF(base, value) (FTM_SYNCONF_REG(base) = (value))
+#define FTM_RMW_SYNCONF(base, mask, value) (FTM_WR_SYNCONF(base, (FTM_RD_SYNCONF(base) & ~(mask)) | (value)))
+#define FTM_SET_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) |  (value)))
+#define FTM_CLR_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) & ~(value)))
+#define FTM_TOG_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SYNCONF bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - FTM clears the TRIGj bit when the hardware trigger j is detected,
+ *     where j = 0, 1,2.
+ * - 0b1 - FTM does not clear the TRIGj bit when the hardware trigger j is
+ *     detected, where j = 0, 1,2.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */
+#define FTM_RD_SYNCONF_HWTRIGMODE(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWTRIGMODE_MASK) >> FTM_SYNCONF_HWTRIGMODE_SHIFT)
+#define FTM_BRD_SYNCONF_HWTRIGMODE(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWTRIGMODE_SHIFT))
+
+/*! @brief Set the HWTRIGMODE field to a new value. */
+#define FTM_WR_SYNCONF_HWTRIGMODE(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWTRIGMODE_MASK, FTM_SYNCONF_HWTRIGMODE(value)))
+#define FTM_BWR_SYNCONF_HWTRIGMODE(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWTRIGMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
+ *
+ * Values:
+ * - 0b0 - CNTIN register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - CNTIN register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */
+#define FTM_RD_SYNCONF_CNTINC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_CNTINC_MASK) >> FTM_SYNCONF_CNTINC_SHIFT)
+#define FTM_BRD_SYNCONF_CNTINC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_CNTINC_SHIFT))
+
+/*! @brief Set the CNTINC field to a new value. */
+#define FTM_WR_SYNCONF_CNTINC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_CNTINC_MASK, FTM_SYNCONF_CNTINC(value)))
+#define FTM_BWR_SYNCONF_CNTINC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_CNTINC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field INVC[4] (RW)
+ *
+ * Values:
+ * - 0b0 - INVCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - INVCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_INVC field. */
+#define FTM_RD_SYNCONF_INVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_INVC_MASK) >> FTM_SYNCONF_INVC_SHIFT)
+#define FTM_BRD_SYNCONF_INVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_INVC_SHIFT))
+
+/*! @brief Set the INVC field to a new value. */
+#define FTM_WR_SYNCONF_INVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_INVC_MASK, FTM_SYNCONF_INVC(value)))
+#define FTM_BWR_SYNCONF_INVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_INVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOC[5] (RW)
+ *
+ * Values:
+ * - 0b0 - SWOCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - SWOCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWOC field. */
+#define FTM_RD_SYNCONF_SWOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWOC_MASK) >> FTM_SYNCONF_SWOC_SHIFT)
+#define FTM_BRD_SYNCONF_SWOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOC_SHIFT))
+
+/*! @brief Set the SWOC field to a new value. */
+#define FTM_WR_SYNCONF_SWOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWOC_MASK, FTM_SYNCONF_SWOC(value)))
+#define FTM_BWR_SYNCONF_SWOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
+ *
+ * Selects the PWM Synchronization mode.
+ *
+ * Values:
+ * - 0b0 - Legacy PWM synchronization is selected.
+ * - 0b1 - Enhanced PWM synchronization is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */
+#define FTM_RD_SYNCONF_SYNCMODE(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SYNCMODE_MASK) >> FTM_SYNCONF_SYNCMODE_SHIFT)
+#define FTM_BRD_SYNCONF_SYNCMODE(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SYNCMODE_SHIFT))
+
+/*! @brief Set the SYNCMODE field to a new value. */
+#define FTM_WR_SYNCONF_SYNCMODE(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SYNCMODE_MASK, FTM_SYNCONF_SYNCMODE(value)))
+#define FTM_BWR_SYNCONF_SYNCMODE(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SYNCMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
+ *
+ * FTM counter synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the FTM counter
+ *     synchronization.
+ * - 0b1 - The software trigger activates the FTM counter synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */
+#define FTM_RD_SYNCONF_SWRSTCNT(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWRSTCNT_MASK) >> FTM_SYNCONF_SWRSTCNT_SHIFT)
+#define FTM_BRD_SYNCONF_SWRSTCNT(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWRSTCNT_SHIFT))
+
+/*! @brief Set the SWRSTCNT field to a new value. */
+#define FTM_WR_SYNCONF_SWRSTCNT(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWRSTCNT_MASK, FTM_SYNCONF_SWRSTCNT(value)))
+#define FTM_BWR_SYNCONF_SWRSTCNT(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWRSTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by the software
+ * trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 0b1 - The software trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */
+#define FTM_RD_SYNCONF_SWWRBUF(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWWRBUF_MASK) >> FTM_SYNCONF_SWWRBUF_SHIFT)
+#define FTM_BRD_SYNCONF_SWWRBUF(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWWRBUF_SHIFT))
+
+/*! @brief Set the SWWRBUF field to a new value. */
+#define FTM_WR_SYNCONF_SWWRBUF(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWWRBUF_MASK, FTM_SYNCONF_SWWRBUF(value)))
+#define FTM_BWR_SYNCONF_SWWRBUF(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWWRBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOM[10] (RW)
+ *
+ * Output mask synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the OUTMASK register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWOM field. */
+#define FTM_RD_SYNCONF_SWOM(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWOM_MASK) >> FTM_SYNCONF_SWOM_SHIFT)
+#define FTM_BRD_SYNCONF_SWOM(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOM_SHIFT))
+
+/*! @brief Set the SWOM field to a new value. */
+#define FTM_WR_SYNCONF_SWOM(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWOM_MASK, FTM_SYNCONF_SWOM(value)))
+#define FTM_BWR_SYNCONF_SWOM(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
+ *
+ * Inverting control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the INVCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */
+#define FTM_RD_SYNCONF_SWINVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWINVC_MASK) >> FTM_SYNCONF_SWINVC_SHIFT)
+#define FTM_BRD_SYNCONF_SWINVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWINVC_SHIFT))
+
+/*! @brief Set the SWINVC field to a new value. */
+#define FTM_WR_SYNCONF_SWINVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWINVC_MASK, FTM_SYNCONF_SWINVC(value)))
+#define FTM_BWR_SYNCONF_SWINVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWINVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
+ *
+ * Software output control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the SWOCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */
+#define FTM_RD_SYNCONF_SWSOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWSOC_MASK) >> FTM_SYNCONF_SWSOC_SHIFT)
+#define FTM_BRD_SYNCONF_SWSOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWSOC_SHIFT))
+
+/*! @brief Set the SWSOC field to a new value. */
+#define FTM_WR_SYNCONF_SWSOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWSOC_MASK, FTM_SYNCONF_SWSOC(value)))
+#define FTM_BWR_SYNCONF_SWSOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWSOC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
+ *
+ * FTM counter synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the FTM counter synchronization.
+ * - 0b1 - A hardware trigger activates the FTM counter synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */
+#define FTM_RD_SYNCONF_HWRSTCNT(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWRSTCNT_MASK) >> FTM_SYNCONF_HWRSTCNT_SHIFT)
+#define FTM_BRD_SYNCONF_HWRSTCNT(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWRSTCNT_SHIFT))
+
+/*! @brief Set the HWRSTCNT field to a new value. */
+#define FTM_WR_SYNCONF_HWRSTCNT(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWRSTCNT_MASK, FTM_SYNCONF_HWRSTCNT(value)))
+#define FTM_BWR_SYNCONF_HWRSTCNT(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWRSTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by a hardware
+ * trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */
+#define FTM_RD_SYNCONF_HWWRBUF(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWWRBUF_MASK) >> FTM_SYNCONF_HWWRBUF_SHIFT)
+#define FTM_BRD_SYNCONF_HWWRBUF(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWWRBUF_SHIFT))
+
+/*! @brief Set the HWWRBUF field to a new value. */
+#define FTM_WR_SYNCONF_HWWRBUF(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWWRBUF_MASK, FTM_SYNCONF_HWWRBUF(value)))
+#define FTM_BWR_SYNCONF_HWWRBUF(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWWRBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWOM[18] (RW)
+ *
+ * Output mask synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the OUTMASK register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWOM field. */
+#define FTM_RD_SYNCONF_HWOM(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWOM_MASK) >> FTM_SYNCONF_HWOM_SHIFT)
+#define FTM_BRD_SYNCONF_HWOM(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWOM_SHIFT))
+
+/*! @brief Set the HWOM field to a new value. */
+#define FTM_WR_SYNCONF_HWOM(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWOM_MASK, FTM_SYNCONF_HWOM(value)))
+#define FTM_BWR_SYNCONF_HWOM(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
+ *
+ * Inverting control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the INVCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */
+#define FTM_RD_SYNCONF_HWINVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWINVC_MASK) >> FTM_SYNCONF_HWINVC_SHIFT)
+#define FTM_BRD_SYNCONF_HWINVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWINVC_SHIFT))
+
+/*! @brief Set the HWINVC field to a new value. */
+#define FTM_WR_SYNCONF_HWINVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWINVC_MASK, FTM_SYNCONF_HWINVC(value)))
+#define FTM_BWR_SYNCONF_HWINVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWINVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
+ *
+ * Software output control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the SWOCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */
+#define FTM_RD_SYNCONF_HWSOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWSOC_MASK) >> FTM_SYNCONF_HWSOC_SHIFT)
+#define FTM_BRD_SYNCONF_HWSOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWSOC_SHIFT))
+
+/*! @brief Set the HWSOC field to a new value. */
+#define FTM_WR_SYNCONF_HWSOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWSOC_MASK, FTM_SYNCONF_HWSOC(value)))
+#define FTM_BWR_SYNCONF_HWSOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWSOC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_INVCTRL - FTM Inverting Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_INVCTRL - FTM Inverting Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls when the channel (n) output becomes the channel (n+1)
+ * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
+ * bit enables the inverting operation for the corresponding pair channels m. This
+ * register has a write buffer. The INVmEN bit is updated by the INVCTRL
+ * register synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_INVCTRL register
+ */
+/*@{*/
+#define FTM_RD_INVCTRL(base)     (FTM_INVCTRL_REG(base))
+#define FTM_WR_INVCTRL(base, value) (FTM_INVCTRL_REG(base) = (value))
+#define FTM_RMW_INVCTRL(base, mask, value) (FTM_WR_INVCTRL(base, (FTM_RD_INVCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) |  (value)))
+#define FTM_CLR_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) & ~(value)))
+#define FTM_TOG_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_INVCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */
+#define FTM_RD_INVCTRL_INV0EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV0EN_MASK) >> FTM_INVCTRL_INV0EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV0EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV0EN_SHIFT))
+
+/*! @brief Set the INV0EN field to a new value. */
+#define FTM_WR_INVCTRL_INV0EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV0EN_MASK, FTM_INVCTRL_INV0EN(value)))
+#define FTM_BWR_INVCTRL_INV0EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */
+#define FTM_RD_INVCTRL_INV1EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV1EN_MASK) >> FTM_INVCTRL_INV1EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV1EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV1EN_SHIFT))
+
+/*! @brief Set the INV1EN field to a new value. */
+#define FTM_WR_INVCTRL_INV1EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV1EN_MASK, FTM_INVCTRL_INV1EN(value)))
+#define FTM_BWR_INVCTRL_INV1EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */
+#define FTM_RD_INVCTRL_INV2EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV2EN_MASK) >> FTM_INVCTRL_INV2EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV2EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV2EN_SHIFT))
+
+/*! @brief Set the INV2EN field to a new value. */
+#define FTM_WR_INVCTRL_INV2EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV2EN_MASK, FTM_INVCTRL_INV2EN(value)))
+#define FTM_BWR_INVCTRL_INV2EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */
+#define FTM_RD_INVCTRL_INV3EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV3EN_MASK) >> FTM_INVCTRL_INV3EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV3EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV3EN_SHIFT))
+
+/*! @brief Set the INV3EN field to a new value. */
+#define FTM_WR_INVCTRL_INV3EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV3EN_MASK, FTM_INVCTRL_INV3EN(value)))
+#define FTM_BWR_INVCTRL_INV3EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV3EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SWOCTRL - FTM Software Output Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SWOCTRL - FTM Software Output Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register enables software control of channel (n) output and defines the
+ * value forced to the channel (n) output: The CHnOC bits enable the control of
+ * the corresponding channel (n) output by software. The CHnOCV bits select the
+ * value that is forced at the corresponding channel (n) output. This register has
+ * a write buffer. The fields are updated by the SWOCTRL register synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SWOCTRL register
+ */
+/*@{*/
+#define FTM_RD_SWOCTRL(base)     (FTM_SWOCTRL_REG(base))
+#define FTM_WR_SWOCTRL(base, value) (FTM_SWOCTRL_REG(base) = (value))
+#define FTM_RMW_SWOCTRL(base, mask, value) (FTM_WR_SWOCTRL(base, (FTM_RD_SWOCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) |  (value)))
+#define FTM_CLR_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) & ~(value)))
+#define FTM_TOG_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SWOCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */
+#define FTM_RD_SWOCTRL_CH0OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH0OC_MASK) >> FTM_SWOCTRL_CH0OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH0OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OC_SHIFT))
+
+/*! @brief Set the CH0OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH0OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH0OC_MASK, FTM_SWOCTRL_CH0OC(value)))
+#define FTM_BWR_SWOCTRL_CH0OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */
+#define FTM_RD_SWOCTRL_CH1OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH1OC_MASK) >> FTM_SWOCTRL_CH1OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH1OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OC_SHIFT))
+
+/*! @brief Set the CH1OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH1OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH1OC_MASK, FTM_SWOCTRL_CH1OC(value)))
+#define FTM_BWR_SWOCTRL_CH1OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */
+#define FTM_RD_SWOCTRL_CH2OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH2OC_MASK) >> FTM_SWOCTRL_CH2OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH2OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OC_SHIFT))
+
+/*! @brief Set the CH2OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH2OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH2OC_MASK, FTM_SWOCTRL_CH2OC(value)))
+#define FTM_BWR_SWOCTRL_CH2OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */
+#define FTM_RD_SWOCTRL_CH3OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH3OC_MASK) >> FTM_SWOCTRL_CH3OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH3OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OC_SHIFT))
+
+/*! @brief Set the CH3OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH3OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH3OC_MASK, FTM_SWOCTRL_CH3OC(value)))
+#define FTM_BWR_SWOCTRL_CH3OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */
+#define FTM_RD_SWOCTRL_CH4OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH4OC_MASK) >> FTM_SWOCTRL_CH4OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH4OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OC_SHIFT))
+
+/*! @brief Set the CH4OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH4OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH4OC_MASK, FTM_SWOCTRL_CH4OC(value)))
+#define FTM_BWR_SWOCTRL_CH4OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */
+#define FTM_RD_SWOCTRL_CH5OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH5OC_MASK) >> FTM_SWOCTRL_CH5OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH5OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OC_SHIFT))
+
+/*! @brief Set the CH5OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH5OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH5OC_MASK, FTM_SWOCTRL_CH5OC(value)))
+#define FTM_BWR_SWOCTRL_CH5OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */
+#define FTM_RD_SWOCTRL_CH6OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH6OC_MASK) >> FTM_SWOCTRL_CH6OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH6OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OC_SHIFT))
+
+/*! @brief Set the CH6OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH6OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH6OC_MASK, FTM_SWOCTRL_CH6OC(value)))
+#define FTM_BWR_SWOCTRL_CH6OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */
+#define FTM_RD_SWOCTRL_CH7OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH7OC_MASK) >> FTM_SWOCTRL_CH7OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH7OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OC_SHIFT))
+
+/*! @brief Set the CH7OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH7OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH7OC_MASK, FTM_SWOCTRL_CH7OC(value)))
+#define FTM_BWR_SWOCTRL_CH7OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */
+#define FTM_RD_SWOCTRL_CH0OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH0OCV_MASK) >> FTM_SWOCTRL_CH0OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH0OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OCV_SHIFT))
+
+/*! @brief Set the CH0OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH0OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH0OCV_MASK, FTM_SWOCTRL_CH0OCV(value)))
+#define FTM_BWR_SWOCTRL_CH0OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */
+#define FTM_RD_SWOCTRL_CH1OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH1OCV_MASK) >> FTM_SWOCTRL_CH1OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH1OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OCV_SHIFT))
+
+/*! @brief Set the CH1OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH1OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH1OCV_MASK, FTM_SWOCTRL_CH1OCV(value)))
+#define FTM_BWR_SWOCTRL_CH1OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */
+#define FTM_RD_SWOCTRL_CH2OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH2OCV_MASK) >> FTM_SWOCTRL_CH2OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH2OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OCV_SHIFT))
+
+/*! @brief Set the CH2OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH2OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH2OCV_MASK, FTM_SWOCTRL_CH2OCV(value)))
+#define FTM_BWR_SWOCTRL_CH2OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */
+#define FTM_RD_SWOCTRL_CH3OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH3OCV_MASK) >> FTM_SWOCTRL_CH3OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH3OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OCV_SHIFT))
+
+/*! @brief Set the CH3OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH3OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH3OCV_MASK, FTM_SWOCTRL_CH3OCV(value)))
+#define FTM_BWR_SWOCTRL_CH3OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */
+#define FTM_RD_SWOCTRL_CH4OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH4OCV_MASK) >> FTM_SWOCTRL_CH4OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH4OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OCV_SHIFT))
+
+/*! @brief Set the CH4OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH4OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH4OCV_MASK, FTM_SWOCTRL_CH4OCV(value)))
+#define FTM_BWR_SWOCTRL_CH4OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */
+#define FTM_RD_SWOCTRL_CH5OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH5OCV_MASK) >> FTM_SWOCTRL_CH5OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH5OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OCV_SHIFT))
+
+/*! @brief Set the CH5OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH5OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH5OCV_MASK, FTM_SWOCTRL_CH5OCV(value)))
+#define FTM_BWR_SWOCTRL_CH5OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */
+#define FTM_RD_SWOCTRL_CH6OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH6OCV_MASK) >> FTM_SWOCTRL_CH6OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH6OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OCV_SHIFT))
+
+/*! @brief Set the CH6OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH6OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH6OCV_MASK, FTM_SWOCTRL_CH6OCV(value)))
+#define FTM_BWR_SWOCTRL_CH6OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */
+#define FTM_RD_SWOCTRL_CH7OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH7OCV_MASK) >> FTM_SWOCTRL_CH7OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH7OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OCV_SHIFT))
+
+/*! @brief Set the CH7OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH7OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH7OCV_MASK, FTM_SWOCTRL_CH7OCV(value)))
+#define FTM_BWR_SWOCTRL_CH7OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OCV_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_PWMLOAD - FTM PWM Load
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_PWMLOAD - FTM PWM Load (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
+ * values of their write buffers when the FTM counter changes from the MOD
+ * register value to its next value or when a channel (j) match occurs. A match occurs
+ * for the channel (j) when FTM counter = C(j)V.
+ */
+/*!
+ * @name Constants and macros for entire FTM_PWMLOAD register
+ */
+/*@{*/
+#define FTM_RD_PWMLOAD(base)     (FTM_PWMLOAD_REG(base))
+#define FTM_WR_PWMLOAD(base, value) (FTM_PWMLOAD_REG(base) = (value))
+#define FTM_RMW_PWMLOAD(base, mask, value) (FTM_WR_PWMLOAD(base, (FTM_RD_PWMLOAD(base) & ~(mask)) | (value)))
+#define FTM_SET_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) |  (value)))
+#define FTM_CLR_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) & ~(value)))
+#define FTM_TOG_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_PWMLOAD bitfields
+ */
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */
+#define FTM_RD_PWMLOAD_CH0SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH0SEL_MASK) >> FTM_PWMLOAD_CH0SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH0SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH0SEL_SHIFT))
+
+/*! @brief Set the CH0SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH0SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH0SEL_MASK, FTM_PWMLOAD_CH0SEL(value)))
+#define FTM_BWR_PWMLOAD_CH0SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH0SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */
+#define FTM_RD_PWMLOAD_CH1SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH1SEL_MASK) >> FTM_PWMLOAD_CH1SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH1SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH1SEL_SHIFT))
+
+/*! @brief Set the CH1SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH1SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH1SEL_MASK, FTM_PWMLOAD_CH1SEL(value)))
+#define FTM_BWR_PWMLOAD_CH1SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH1SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */
+#define FTM_RD_PWMLOAD_CH2SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH2SEL_MASK) >> FTM_PWMLOAD_CH2SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH2SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH2SEL_SHIFT))
+
+/*! @brief Set the CH2SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH2SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH2SEL_MASK, FTM_PWMLOAD_CH2SEL(value)))
+#define FTM_BWR_PWMLOAD_CH2SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH2SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */
+#define FTM_RD_PWMLOAD_CH3SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH3SEL_MASK) >> FTM_PWMLOAD_CH3SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH3SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH3SEL_SHIFT))
+
+/*! @brief Set the CH3SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH3SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH3SEL_MASK, FTM_PWMLOAD_CH3SEL(value)))
+#define FTM_BWR_PWMLOAD_CH3SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH3SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */
+#define FTM_RD_PWMLOAD_CH4SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH4SEL_MASK) >> FTM_PWMLOAD_CH4SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH4SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH4SEL_SHIFT))
+
+/*! @brief Set the CH4SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH4SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH4SEL_MASK, FTM_PWMLOAD_CH4SEL(value)))
+#define FTM_BWR_PWMLOAD_CH4SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH4SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */
+#define FTM_RD_PWMLOAD_CH5SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH5SEL_MASK) >> FTM_PWMLOAD_CH5SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH5SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH5SEL_SHIFT))
+
+/*! @brief Set the CH5SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH5SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH5SEL_MASK, FTM_PWMLOAD_CH5SEL(value)))
+#define FTM_BWR_PWMLOAD_CH5SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH5SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */
+#define FTM_RD_PWMLOAD_CH6SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH6SEL_MASK) >> FTM_PWMLOAD_CH6SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH6SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH6SEL_SHIFT))
+
+/*! @brief Set the CH6SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH6SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH6SEL_MASK, FTM_PWMLOAD_CH6SEL(value)))
+#define FTM_BWR_PWMLOAD_CH6SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH6SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */
+#define FTM_RD_PWMLOAD_CH7SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH7SEL_MASK) >> FTM_PWMLOAD_CH7SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH7SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH7SEL_SHIFT))
+
+/*! @brief Set the CH7SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH7SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH7SEL_MASK, FTM_PWMLOAD_CH7SEL(value)))
+#define FTM_BWR_PWMLOAD_CH7SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH7SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
+ *
+ * Enables the loading of the MOD, CNTIN, and CV registers with the values of
+ * their write buffers.
+ *
+ * Values:
+ * - 0b0 - Loading updated values is disabled.
+ * - 0b1 - Loading updated values is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */
+#define FTM_RD_PWMLOAD_LDOK(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_LDOK_MASK) >> FTM_PWMLOAD_LDOK_SHIFT)
+#define FTM_BRD_PWMLOAD_LDOK(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_LDOK_SHIFT))
+
+/*! @brief Set the LDOK field to a new value. */
+#define FTM_WR_PWMLOAD_LDOK(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_LDOK_MASK, FTM_PWMLOAD_LDOK(value)))
+#define FTM_BWR_PWMLOAD_LDOK(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_LDOK_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 GPIO
+ *
+ * General Purpose Input/Output
+ *
+ * Registers defined in this header file:
+ * - GPIO_PDOR - Port Data Output Register
+ * - GPIO_PSOR - Port Set Output Register
+ * - GPIO_PCOR - Port Clear Output Register
+ * - GPIO_PTOR - Port Toggle Output Register
+ * - GPIO_PDIR - Port Data Input Register
+ * - GPIO_PDDR - Port Data Direction Register
+ */
+
+#define GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
+#define GPIOA_IDX (0U) /*!< Instance number for GPIOA. */
+#define GPIOB_IDX (1U) /*!< Instance number for GPIOB. */
+#define GPIOC_IDX (2U) /*!< Instance number for GPIOC. */
+#define GPIOD_IDX (3U) /*!< Instance number for GPIOD. */
+#define GPIOE_IDX (4U) /*!< Instance number for GPIOE. */
+
+/*******************************************************************************
+ * GPIO_PDOR - Port Data Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDOR - Port Data Output Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the logic levels that are driven on each
+ * general-purpose output pins. Do not modify pin configuration registers associated with
+ * pins not available in your selected package. All unbonded pins not available in
+ * your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDOR register
+ */
+/*@{*/
+#define GPIO_RD_PDOR(base)       (GPIO_PDOR_REG(base))
+#define GPIO_WR_PDOR(base, value) (GPIO_PDOR_REG(base) = (value))
+#define GPIO_RMW_PDOR(base, mask, value) (GPIO_WR_PDOR(base, (GPIO_RD_PDOR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) |  (value)))
+#define GPIO_CLR_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) & ~(value)))
+#define GPIO_TOG_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PSOR - Port Set Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PSOR - Port Set Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to set the fields of the PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PSOR register
+ */
+/*@{*/
+#define GPIO_RD_PSOR(base)       (GPIO_PSOR_REG(base))
+#define GPIO_WR_PSOR(base, value) (GPIO_PSOR_REG(base) = (value))
+#define GPIO_RMW_PSOR(base, mask, value) (GPIO_WR_PSOR(base, (GPIO_RD_PSOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PCOR - Port Clear Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PCOR - Port Clear Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to clear the fields of PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PCOR register
+ */
+/*@{*/
+#define GPIO_RD_PCOR(base)       (GPIO_PCOR_REG(base))
+#define GPIO_WR_PCOR(base, value) (GPIO_PCOR_REG(base) = (value))
+#define GPIO_RMW_PCOR(base, mask, value) (GPIO_WR_PCOR(base, (GPIO_RD_PCOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PTOR - Port Toggle Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PTOR - Port Toggle Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PTOR register
+ */
+/*@{*/
+#define GPIO_RD_PTOR(base)       (GPIO_PTOR_REG(base))
+#define GPIO_WR_PTOR(base, value) (GPIO_PTOR_REG(base) = (value))
+#define GPIO_RMW_PTOR(base, mask, value) (GPIO_WR_PTOR(base, (GPIO_RD_PTOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDIR - Port Data Input Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDIR - Port Data Input Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Do not modify pin configuration registers associated with pins not available
+ * in your selected package. All unbonded pins not available in your package will
+ * default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDIR register
+ */
+/*@{*/
+#define GPIO_RD_PDIR(base)       (GPIO_PDIR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDDR - Port Data Direction Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDDR - Port Data Direction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The PDDR configures the individual port pins for input or output.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDDR register
+ */
+/*@{*/
+#define GPIO_RD_PDDR(base)       (GPIO_PDDR_REG(base))
+#define GPIO_WR_PDDR(base, value) (GPIO_PDDR_REG(base) = (value))
+#define GPIO_RMW_PDDR(base, mask, value) (GPIO_WR_PDDR(base, (GPIO_RD_PDDR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) |  (value)))
+#define GPIO_CLR_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) & ~(value)))
+#define GPIO_TOG_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 I2C
+ *
+ * Inter-Integrated Circuit
+ *
+ * Registers defined in this header file:
+ * - I2C_A1 - I2C Address Register 1
+ * - I2C_F - I2C Frequency Divider register
+ * - I2C_C1 - I2C Control Register 1
+ * - I2C_S - I2C Status register
+ * - I2C_D - I2C Data I/O register
+ * - I2C_C2 - I2C Control Register 2
+ * - I2C_FLT - I2C Programmable Input Glitch Filter register
+ * - I2C_RA - I2C Range Address register
+ * - I2C_SMB - I2C SMBus Control and Status register
+ * - I2C_A2 - I2C Address Register 2
+ * - I2C_SLTH - I2C SCL Low Timeout Register High
+ * - I2C_SLTL - I2C SCL Low Timeout Register Low
+ */
+
+#define I2C_INSTANCE_COUNT (3U) /*!< Number of instances of the I2C module. */
+#define I2C0_IDX (0U) /*!< Instance number for I2C0. */
+#define I2C1_IDX (1U) /*!< Instance number for I2C1. */
+#define I2C2_IDX (2U) /*!< Instance number for I2C2. */
+
+/*******************************************************************************
+ * I2C_A1 - I2C Address Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A1 - I2C Address Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the slave address to be used by the I2C module.
+ */
+/*!
+ * @name Constants and macros for entire I2C_A1 register
+ */
+/*@{*/
+#define I2C_RD_A1(base)          (I2C_A1_REG(base))
+#define I2C_WR_A1(base, value)   (I2C_A1_REG(base) = (value))
+#define I2C_RMW_A1(base, mask, value) (I2C_WR_A1(base, (I2C_RD_A1(base) & ~(mask)) | (value)))
+#define I2C_SET_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) |  (value)))
+#define I2C_CLR_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) & ~(value)))
+#define I2C_TOG_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A1 bitfields
+ */
+
+/*!
+ * @name Register I2C_A1, field AD[7:1] (RW)
+ *
+ * Contains the primary slave address used by the I2C module when it is
+ * addressed as a slave. This field is used in the 7-bit address scheme and the lower
+ * seven bits in the 10-bit address scheme.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A1_AD field. */
+#define I2C_RD_A1_AD(base)   ((I2C_A1_REG(base) & I2C_A1_AD_MASK) >> I2C_A1_AD_SHIFT)
+#define I2C_BRD_A1_AD(base)  (I2C_RD_A1_AD(base))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_A1_AD(base, value) (I2C_RMW_A1(base, I2C_A1_AD_MASK, I2C_A1_AD(value)))
+#define I2C_BWR_A1_AD(base, value) (I2C_WR_A1_AD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_F - I2C Frequency Divider register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_F - I2C Frequency Divider register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_F register
+ */
+/*@{*/
+#define I2C_RD_F(base)           (I2C_F_REG(base))
+#define I2C_WR_F(base, value)    (I2C_F_REG(base) = (value))
+#define I2C_RMW_F(base, mask, value) (I2C_WR_F(base, (I2C_RD_F(base) & ~(mask)) | (value)))
+#define I2C_SET_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) |  (value)))
+#define I2C_CLR_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) & ~(value)))
+#define I2C_TOG_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_F bitfields
+ */
+
+/*!
+ * @name Register I2C_F, field ICR[5:0] (RW)
+ *
+ * Prescales the I2C module clock for bit rate selection. This field and the
+ * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
+ * time, and the SCL stop hold time. For a list of values corresponding to each ICR
+ * setting, see I2C divider and hold values. The SCL divider multiplied by
+ * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
+ * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
+ * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
+ * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
+ * the delay from the falling edge of SDA (I2C data) while SCL is high (start
+ * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
+ * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
+ * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
+ * data) while SCL is high (stop condition). SCL stop hold time = I2C module
+ * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
+ * speed is 8 MHz, the following table shows the possible hold time values with
+ * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
+ * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h
+ * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
+ * 1.125 4.750 5.125
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_ICR field. */
+#define I2C_RD_F_ICR(base)   ((I2C_F_REG(base) & I2C_F_ICR_MASK) >> I2C_F_ICR_SHIFT)
+#define I2C_BRD_F_ICR(base)  (I2C_RD_F_ICR(base))
+
+/*! @brief Set the ICR field to a new value. */
+#define I2C_WR_F_ICR(base, value) (I2C_RMW_F(base, I2C_F_ICR_MASK, I2C_F_ICR(value)))
+#define I2C_BWR_F_ICR(base, value) (I2C_WR_F_ICR(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_F, field MULT[7:6] (RW)
+ *
+ * Defines the multiplier factor (mul). This factor is used along with the SCL
+ * divider to generate the I2C baud rate.
+ *
+ * Values:
+ * - 0b00 - mul = 1
+ * - 0b01 - mul = 2
+ * - 0b10 - mul = 4
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_MULT field. */
+#define I2C_RD_F_MULT(base)  ((I2C_F_REG(base) & I2C_F_MULT_MASK) >> I2C_F_MULT_SHIFT)
+#define I2C_BRD_F_MULT(base) (I2C_RD_F_MULT(base))
+
+/*! @brief Set the MULT field to a new value. */
+#define I2C_WR_F_MULT(base, value) (I2C_RMW_F(base, I2C_F_MULT_MASK, I2C_F_MULT(value)))
+#define I2C_BWR_F_MULT(base, value) (I2C_WR_F_MULT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C1 - I2C Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C1 - I2C Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C1 register
+ */
+/*@{*/
+#define I2C_RD_C1(base)          (I2C_C1_REG(base))
+#define I2C_WR_C1(base, value)   (I2C_C1_REG(base) = (value))
+#define I2C_RMW_C1(base, mask, value) (I2C_WR_C1(base, (I2C_RD_C1(base) & ~(mask)) | (value)))
+#define I2C_SET_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) |  (value)))
+#define I2C_CLR_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) & ~(value)))
+#define I2C_TOG_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C1 bitfields
+ */
+
+/*!
+ * @name Register I2C_C1, field DMAEN[0] (RW)
+ *
+ * Enables or disables the DMA function.
+ *
+ * Values:
+ * - 0b0 - All DMA signalling disabled.
+ * - 0b1 - DMA transfer is enabled. While SMB[FACK] = 0, the following
+ *     conditions trigger the DMA request: a data byte is received, and either address or
+ *     data is transmitted. (ACK/NACK is automatic) the first byte received
+ *     matches the A1 register or is a general call address. If any address matching
+ *     occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
+ *     from master to slave, then it is not required to check S[SRW]. With this
+ *     assumption, DMA can also be used in this case. In other cases, if the master
+ *     reads data from the slave, then it is required to rewrite the C1 register
+ *     operation. With this assumption, DMA cannot be used. When FACK = 1, an
+ *     address or a data byte is transmitted.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_DMAEN field. */
+#define I2C_RD_C1_DMAEN(base) ((I2C_C1_REG(base) & I2C_C1_DMAEN_MASK) >> I2C_C1_DMAEN_SHIFT)
+#define I2C_BRD_C1_DMAEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define I2C_WR_C1_DMAEN(base, value) (I2C_RMW_C1(base, I2C_C1_DMAEN_MASK, I2C_C1_DMAEN(value)))
+#define I2C_BWR_C1_DMAEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field WUEN[1] (RW)
+ *
+ * The I2C module can wake the MCU from low power mode with no peripheral bus
+ * running when slave address matching occurs.
+ *
+ * Values:
+ * - 0b0 - Normal operation. No interrupt generated when address matching in low
+ *     power mode.
+ * - 0b1 - Enables the wakeup function in low power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_WUEN field. */
+#define I2C_RD_C1_WUEN(base) ((I2C_C1_REG(base) & I2C_C1_WUEN_MASK) >> I2C_C1_WUEN_SHIFT)
+#define I2C_BRD_C1_WUEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT))
+
+/*! @brief Set the WUEN field to a new value. */
+#define I2C_WR_C1_WUEN(base, value) (I2C_RMW_C1(base, I2C_C1_WUEN_MASK, I2C_C1_WUEN(value)))
+#define I2C_BWR_C1_WUEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field RSTA[2] (WORZ)
+ *
+ * Writing 1 to this bit generates a repeated START condition provided it is the
+ * current master. This bit will always be read as 0. Attempting a repeat at the
+ * wrong time results in loss of arbitration.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define I2C_WR_C1_RSTA(base, value) (I2C_RMW_C1(base, I2C_C1_RSTA_MASK, I2C_C1_RSTA(value)))
+#define I2C_BWR_C1_RSTA(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_RSTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TXAK[3] (RW)
+ *
+ * Specifies the value driven onto the SDA during data acknowledge cycles for
+ * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
+ * generation. SCL is held low until TXAK is written.
+ *
+ * Values:
+ * - 0b0 - An acknowledge signal is sent to the bus on the following receiving
+ *     byte (if FACK is cleared) or the current receiving byte (if FACK is set).
+ * - 0b1 - No acknowledge signal is sent to the bus on the following receiving
+ *     data byte (if FACK is cleared) or the current receiving data byte (if FACK
+ *     is set).
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TXAK field. */
+#define I2C_RD_C1_TXAK(base) ((I2C_C1_REG(base) & I2C_C1_TXAK_MASK) >> I2C_C1_TXAK_SHIFT)
+#define I2C_BRD_C1_TXAK(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT))
+
+/*! @brief Set the TXAK field to a new value. */
+#define I2C_WR_C1_TXAK(base, value) (I2C_RMW_C1(base, I2C_C1_TXAK_MASK, I2C_C1_TXAK(value)))
+#define I2C_BWR_C1_TXAK(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TX[4] (RW)
+ *
+ * Selects the direction of master and slave transfers. In master mode this bit
+ * must be set according to the type of transfer required. Therefore, for address
+ * cycles, this bit is always set. When addressed as a slave this bit must be
+ * set by software according to the SRW bit in the status register.
+ *
+ * Values:
+ * - 0b0 - Receive
+ * - 0b1 - Transmit
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TX field. */
+#define I2C_RD_C1_TX(base)   ((I2C_C1_REG(base) & I2C_C1_TX_MASK) >> I2C_C1_TX_SHIFT)
+#define I2C_BRD_C1_TX(base)  (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT))
+
+/*! @brief Set the TX field to a new value. */
+#define I2C_WR_C1_TX(base, value) (I2C_RMW_C1(base, I2C_C1_TX_MASK, I2C_C1_TX(value)))
+#define I2C_BWR_C1_TX(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field MST[5] (RW)
+ *
+ * When MST is changed from 0 to 1, a START signal is generated on the bus and
+ * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
+ * generated and the mode of operation changes from master to slave.
+ *
+ * Values:
+ * - 0b0 - Slave mode
+ * - 0b1 - Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_MST field. */
+#define I2C_RD_C1_MST(base)  ((I2C_C1_REG(base) & I2C_C1_MST_MASK) >> I2C_C1_MST_SHIFT)
+#define I2C_BRD_C1_MST(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT))
+
+/*! @brief Set the MST field to a new value. */
+#define I2C_WR_C1_MST(base, value) (I2C_RMW_C1(base, I2C_C1_MST_MASK, I2C_C1_MST(value)))
+#define I2C_BWR_C1_MST(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICIE[6] (RW)
+ *
+ * Enables I2C interrupt requests.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICIE field. */
+#define I2C_RD_C1_IICIE(base) ((I2C_C1_REG(base) & I2C_C1_IICIE_MASK) >> I2C_C1_IICIE_SHIFT)
+#define I2C_BRD_C1_IICIE(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT))
+
+/*! @brief Set the IICIE field to a new value. */
+#define I2C_WR_C1_IICIE(base, value) (I2C_RMW_C1(base, I2C_C1_IICIE_MASK, I2C_C1_IICIE(value)))
+#define I2C_BWR_C1_IICIE(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICEN[7] (RW)
+ *
+ * Enables I2C module operation.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICEN field. */
+#define I2C_RD_C1_IICEN(base) ((I2C_C1_REG(base) & I2C_C1_IICEN_MASK) >> I2C_C1_IICEN_SHIFT)
+#define I2C_BRD_C1_IICEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT))
+
+/*! @brief Set the IICEN field to a new value. */
+#define I2C_WR_C1_IICEN(base, value) (I2C_RMW_C1(base, I2C_C1_IICEN_MASK, I2C_C1_IICEN(value)))
+#define I2C_BWR_C1_IICEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_S - I2C Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_S - I2C Status register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire I2C_S register
+ */
+/*@{*/
+#define I2C_RD_S(base)           (I2C_S_REG(base))
+#define I2C_WR_S(base, value)    (I2C_S_REG(base) = (value))
+#define I2C_RMW_S(base, mask, value) (I2C_WR_S(base, (I2C_RD_S(base) & ~(mask)) | (value)))
+#define I2C_SET_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) |  (value)))
+#define I2C_CLR_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) & ~(value)))
+#define I2C_TOG_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_S bitfields
+ */
+
+/*!
+ * @name Register I2C_S, field RXAK[0] (RO)
+ *
+ * Values:
+ * - 0b0 - Acknowledge signal was received after the completion of one byte of
+ *     data transmission on the bus
+ * - 0b1 - No acknowledge signal detected
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RXAK field. */
+#define I2C_RD_S_RXAK(base)  ((I2C_S_REG(base) & I2C_S_RXAK_MASK) >> I2C_S_RXAK_SHIFT)
+#define I2C_BRD_S_RXAK(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RXAK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IICIF[1] (W1C)
+ *
+ * This bit sets when an interrupt is pending. This bit must be cleared by
+ * software by writing 1 to it, such as in the interrupt routine. One of the following
+ * events can set this bit: One byte transfer, including ACK/NACK bit, completes
+ * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
+ * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
+ * completes if FACK is 1. Match of slave address to calling address including
+ * primary slave address, range slave address , alert response address, second
+ * slave address, or general call address. Arbitration lost In SMBus mode, any
+ * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
+ * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
+ * start detection interrupt: In the interrupt service routine, first clear the
+ * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
+ * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
+ * asserted again.
+ *
+ * Values:
+ * - 0b0 - No interrupt pending
+ * - 0b1 - Interrupt pending
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IICIF field. */
+#define I2C_RD_S_IICIF(base) ((I2C_S_REG(base) & I2C_S_IICIF_MASK) >> I2C_S_IICIF_SHIFT)
+#define I2C_BRD_S_IICIF(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT))
+
+/*! @brief Set the IICIF field to a new value. */
+#define I2C_WR_S_IICIF(base, value) (I2C_RMW_S(base, (I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IICIF(value)))
+#define I2C_BWR_S_IICIF(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field SRW[2] (RO)
+ *
+ * When addressed as a slave, SRW indicates the value of the R/W command bit of
+ * the calling address sent to the master.
+ *
+ * Values:
+ * - 0b0 - Slave receive, master writing to slave
+ * - 0b1 - Slave transmit, master reading from slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_SRW field. */
+#define I2C_RD_S_SRW(base)   ((I2C_S_REG(base) & I2C_S_SRW_MASK) >> I2C_S_SRW_SHIFT)
+#define I2C_BRD_S_SRW(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_SRW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field RAM[3] (RW)
+ *
+ * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
+ * Any nonzero calling address is received that matches the address in the RA
+ * register. The calling address is within the range of values of the A1 and RA
+ * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
+ * Writing the C1 register with any value clears this bit to 0.
+ *
+ * Values:
+ * - 0b0 - Not addressed
+ * - 0b1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RAM field. */
+#define I2C_RD_S_RAM(base)   ((I2C_S_REG(base) & I2C_S_RAM_MASK) >> I2C_S_RAM_SHIFT)
+#define I2C_BRD_S_RAM(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RAM_SHIFT))
+
+/*! @brief Set the RAM field to a new value. */
+#define I2C_WR_S_RAM(base, value) (I2C_RMW_S(base, (I2C_S_RAM_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_RAM(value)))
+#define I2C_BWR_S_RAM(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RAM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field ARBL[4] (W1C)
+ *
+ * This bit is set by hardware when the arbitration procedure is lost. The ARBL
+ * bit must be cleared by software, by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - Standard bus operation.
+ * - 0b1 - Loss of arbitration.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_ARBL field. */
+#define I2C_RD_S_ARBL(base)  ((I2C_S_REG(base) & I2C_S_ARBL_MASK) >> I2C_S_ARBL_SHIFT)
+#define I2C_BRD_S_ARBL(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT))
+
+/*! @brief Set the ARBL field to a new value. */
+#define I2C_WR_S_ARBL(base, value) (I2C_RMW_S(base, (I2C_S_ARBL_MASK | I2C_S_IICIF_MASK), I2C_S_ARBL(value)))
+#define I2C_BWR_S_ARBL(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field BUSY[5] (RO)
+ *
+ * Indicates the status of the bus regardless of slave or master mode. This bit
+ * is set when a START signal is detected and cleared when a STOP signal is
+ * detected.
+ *
+ * Values:
+ * - 0b0 - Bus is idle
+ * - 0b1 - Bus is busy
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_BUSY field. */
+#define I2C_RD_S_BUSY(base)  ((I2C_S_REG(base) & I2C_S_BUSY_MASK) >> I2C_S_BUSY_SHIFT)
+#define I2C_BRD_S_BUSY(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_BUSY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IAAS[6] (RW)
+ *
+ * This bit is set by one of the following conditions: The calling address
+ * matches the programmed primary slave address in the A1 register, or matches the
+ * range address in the RA register (which must be set to a nonzero value and under
+ * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
+ * received. SMB[SIICAEN] is set and the calling address matches the second programmed
+ * slave address. ALERTEN is set and an SMBus alert response address is received
+ * RMEN is set and an address is received that is within the range between the
+ * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
+ * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
+ * value clears this bit.
+ *
+ * Values:
+ * - 0b0 - Not addressed
+ * - 0b1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IAAS field. */
+#define I2C_RD_S_IAAS(base)  ((I2C_S_REG(base) & I2C_S_IAAS_MASK) >> I2C_S_IAAS_SHIFT)
+#define I2C_BRD_S_IAAS(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT))
+
+/*! @brief Set the IAAS field to a new value. */
+#define I2C_WR_S_IAAS(base, value) (I2C_RMW_S(base, (I2C_S_IAAS_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IAAS(value)))
+#define I2C_BWR_S_IAAS(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field TCF[7] (RO)
+ *
+ * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
+ * This bit is valid only during or immediately following a transfer to or from
+ * the I2C module. TCF is cleared by reading the I2C data register in receive mode
+ * or by writing to the I2C data register in transmit mode.
+ *
+ * Values:
+ * - 0b0 - Transfer in progress
+ * - 0b1 - Transfer complete
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_TCF field. */
+#define I2C_RD_S_TCF(base)   ((I2C_S_REG(base) & I2C_S_TCF_MASK) >> I2C_S_TCF_SHIFT)
+#define I2C_BRD_S_TCF(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_TCF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_D - I2C Data I/O register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_D - I2C Data I/O register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_D register
+ */
+/*@{*/
+#define I2C_RD_D(base)           (I2C_D_REG(base))
+#define I2C_WR_D(base, value)    (I2C_D_REG(base) = (value))
+#define I2C_RMW_D(base, mask, value) (I2C_WR_D(base, (I2C_RD_D(base) & ~(mask)) | (value)))
+#define I2C_SET_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) |  (value)))
+#define I2C_CLR_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) & ~(value)))
+#define I2C_TOG_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C2 - I2C Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C2 - I2C Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C2 register
+ */
+/*@{*/
+#define I2C_RD_C2(base)          (I2C_C2_REG(base))
+#define I2C_WR_C2(base, value)   (I2C_C2_REG(base) = (value))
+#define I2C_RMW_C2(base, mask, value) (I2C_WR_C2(base, (I2C_RD_C2(base) & ~(mask)) | (value)))
+#define I2C_SET_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) |  (value)))
+#define I2C_CLR_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) & ~(value)))
+#define I2C_TOG_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C2 bitfields
+ */
+
+/*!
+ * @name Register I2C_C2, field AD[2:0] (RW)
+ *
+ * Contains the upper three bits of the slave address in the 10-bit address
+ * scheme. This field is valid only while the ADEXT bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_AD field. */
+#define I2C_RD_C2_AD(base)   ((I2C_C2_REG(base) & I2C_C2_AD_MASK) >> I2C_C2_AD_SHIFT)
+#define I2C_BRD_C2_AD(base)  (I2C_RD_C2_AD(base))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_C2_AD(base, value) (I2C_RMW_C2(base, I2C_C2_AD_MASK, I2C_C2_AD(value)))
+#define I2C_BWR_C2_AD(base, value) (I2C_WR_C2_AD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field RMEN[3] (RW)
+ *
+ * This bit controls the slave address matching for addresses between the values
+ * of the A1 and RA registers. When this bit is set, a slave address matching
+ * occurs for any address greater than the value of the A1 register and less than
+ * or equal to the value of the RA register.
+ *
+ * Values:
+ * - 0b0 - Range mode disabled. No address matching occurs for an address within
+ *     the range of values of the A1 and RA registers.
+ * - 0b1 - Range mode enabled. Address matching occurs when a slave receives an
+ *     address within the range of values of the A1 and RA registers.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_RMEN field. */
+#define I2C_RD_C2_RMEN(base) ((I2C_C2_REG(base) & I2C_C2_RMEN_MASK) >> I2C_C2_RMEN_SHIFT)
+#define I2C_BRD_C2_RMEN(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT))
+
+/*! @brief Set the RMEN field to a new value. */
+#define I2C_WR_C2_RMEN(base, value) (I2C_RMW_C2(base, I2C_C2_RMEN_MASK, I2C_C2_RMEN(value)))
+#define I2C_BWR_C2_RMEN(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field SBRC[4] (RW)
+ *
+ * Enables independent slave mode baud rate at maximum frequency, which forces
+ * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
+ * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
+ * capture the master's data at only 10 kbit/s.
+ *
+ * Values:
+ * - 0b0 - The slave baud rate follows the master baud rate and clock stretching
+ *     may occur
+ * - 0b1 - Slave baud rate is independent of the master baud rate
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_SBRC field. */
+#define I2C_RD_C2_SBRC(base) ((I2C_C2_REG(base) & I2C_C2_SBRC_MASK) >> I2C_C2_SBRC_SHIFT)
+#define I2C_BRD_C2_SBRC(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT))
+
+/*! @brief Set the SBRC field to a new value. */
+#define I2C_WR_C2_SBRC(base, value) (I2C_RMW_C2(base, I2C_C2_SBRC_MASK, I2C_C2_SBRC(value)))
+#define I2C_BWR_C2_SBRC(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field HDRS[5] (RW)
+ *
+ * Controls the drive capability of the I2C pads.
+ *
+ * Values:
+ * - 0b0 - Normal drive mode
+ * - 0b1 - High drive mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_HDRS field. */
+#define I2C_RD_C2_HDRS(base) ((I2C_C2_REG(base) & I2C_C2_HDRS_MASK) >> I2C_C2_HDRS_SHIFT)
+#define I2C_BRD_C2_HDRS(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT))
+
+/*! @brief Set the HDRS field to a new value. */
+#define I2C_WR_C2_HDRS(base, value) (I2C_RMW_C2(base, I2C_C2_HDRS_MASK, I2C_C2_HDRS(value)))
+#define I2C_BWR_C2_HDRS(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field ADEXT[6] (RW)
+ *
+ * Controls the number of bits used for the slave address.
+ *
+ * Values:
+ * - 0b0 - 7-bit address scheme
+ * - 0b1 - 10-bit address scheme
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_ADEXT field. */
+#define I2C_RD_C2_ADEXT(base) ((I2C_C2_REG(base) & I2C_C2_ADEXT_MASK) >> I2C_C2_ADEXT_SHIFT)
+#define I2C_BRD_C2_ADEXT(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT))
+
+/*! @brief Set the ADEXT field to a new value. */
+#define I2C_WR_C2_ADEXT(base, value) (I2C_RMW_C2(base, I2C_C2_ADEXT_MASK, I2C_C2_ADEXT(value)))
+#define I2C_BWR_C2_ADEXT(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field GCAEN[7] (RW)
+ *
+ * Enables general call address.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_GCAEN field. */
+#define I2C_RD_C2_GCAEN(base) ((I2C_C2_REG(base) & I2C_C2_GCAEN_MASK) >> I2C_C2_GCAEN_SHIFT)
+#define I2C_BRD_C2_GCAEN(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT))
+
+/*! @brief Set the GCAEN field to a new value. */
+#define I2C_WR_C2_GCAEN(base, value) (I2C_RMW_C2(base, I2C_C2_GCAEN_MASK, I2C_C2_GCAEN(value)))
+#define I2C_BWR_C2_GCAEN(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_FLT - I2C Programmable Input Glitch Filter register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_FLT register
+ */
+/*@{*/
+#define I2C_RD_FLT(base)         (I2C_FLT_REG(base))
+#define I2C_WR_FLT(base, value)  (I2C_FLT_REG(base) = (value))
+#define I2C_RMW_FLT(base, mask, value) (I2C_WR_FLT(base, (I2C_RD_FLT(base) & ~(mask)) | (value)))
+#define I2C_SET_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) |  (value)))
+#define I2C_CLR_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) & ~(value)))
+#define I2C_TOG_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_FLT bitfields
+ */
+
+/*!
+ * @name Register I2C_FLT, field FLT[3:0] (RW)
+ *
+ * Controls the width of the glitch, in terms of I2C module clock cycles, that
+ * the filter must absorb. For any glitch whose size is less than or equal to this
+ * width setting, the filter does not allow the glitch to pass.
+ *
+ * Values:
+ * - 0b0000 - No filter/bypass
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_FLT field. */
+#define I2C_RD_FLT_FLT(base) ((I2C_FLT_REG(base) & I2C_FLT_FLT_MASK) >> I2C_FLT_FLT_SHIFT)
+#define I2C_BRD_FLT_FLT(base) (I2C_RD_FLT_FLT(base))
+
+/*! @brief Set the FLT field to a new value. */
+#define I2C_WR_FLT_FLT(base, value) (I2C_RMW_FLT(base, (I2C_FLT_FLT_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_FLT(value)))
+#define I2C_BWR_FLT_FLT(base, value) (I2C_WR_FLT_FLT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STARTF[4] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's start status is detected. The
+ * STARTF bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No start happens on I2C bus
+ * - 0b1 - Start detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STARTF field. */
+#define I2C_RD_FLT_STARTF(base) ((I2C_FLT_REG(base) & I2C_FLT_STARTF_MASK) >> I2C_FLT_STARTF_SHIFT)
+#define I2C_BRD_FLT_STARTF(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT))
+
+/*! @brief Set the STARTF field to a new value. */
+#define I2C_WR_FLT_STARTF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_STARTF(value)))
+#define I2C_BWR_FLT_STARTF(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SSIE[5] (RW)
+ *
+ * This bit enables the interrupt for I2C bus stop or start detection. To clear
+ * the I2C bus stop or start detection interrupt: In the interrupt service
+ * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
+ * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
+ * is asserted again.
+ *
+ * Values:
+ * - 0b0 - Stop or start detection interrupt is disabled
+ * - 0b1 - Stop or start detection interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SSIE field. */
+#define I2C_RD_FLT_SSIE(base) ((I2C_FLT_REG(base) & I2C_FLT_SSIE_MASK) >> I2C_FLT_SSIE_SHIFT)
+#define I2C_BRD_FLT_SSIE(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT))
+
+/*! @brief Set the SSIE field to a new value. */
+#define I2C_WR_FLT_SSIE(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SSIE_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SSIE(value)))
+#define I2C_BWR_FLT_SSIE(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STOPF[6] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
+ * bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No stop happens on I2C bus
+ * - 0b1 - Stop detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STOPF field. */
+#define I2C_RD_FLT_STOPF(base) ((I2C_FLT_REG(base) & I2C_FLT_STOPF_MASK) >> I2C_FLT_STOPF_SHIFT)
+#define I2C_BRD_FLT_STOPF(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT))
+
+/*! @brief Set the STOPF field to a new value. */
+#define I2C_WR_FLT_STOPF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK), I2C_FLT_STOPF(value)))
+#define I2C_BWR_FLT_STOPF(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SHEN[7] (RW)
+ *
+ * Set this bit to hold off entry to stop mode when any data transmission or
+ * reception is occurring. The following scenario explains the holdoff
+ * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
+ * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
+ * byte currently being transferred, including both address and data, completes
+ * its transfer. The I2C slave or master acknowledges that the in-transfer byte
+ * completed its transfer and acknowledges the request to enter stop mode. After
+ * receiving the I2C module's acknowledgment of the request to enter stop mode,
+ * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
+ * is set to 1 and the I2C module is in an idle or disabled state when the MCU
+ * signals to enter stop mode, the module immediately acknowledges the request to
+ * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
+ * reception that was suspended by stop mode entry was incomplete: To resume the
+ * overall transmission or reception after the MCU exits stop mode, software must
+ * reinitialize the transfer by resending the address of the slave. If the I2C
+ * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
+ * system software will receive the interrupt triggered by the I2C Status Register's
+ * TCF bit after the MCU wakes from the stop mode.
+ *
+ * Values:
+ * - 0b0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
+ * - 0b1 - Stop holdoff is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SHEN field. */
+#define I2C_RD_FLT_SHEN(base) ((I2C_FLT_REG(base) & I2C_FLT_SHEN_MASK) >> I2C_FLT_SHEN_SHIFT)
+#define I2C_BRD_FLT_SHEN(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT))
+
+/*! @brief Set the SHEN field to a new value. */
+#define I2C_WR_FLT_SHEN(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SHEN_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SHEN(value)))
+#define I2C_BWR_FLT_SHEN(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_RA - I2C Range Address register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_RA - I2C Range Address register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_RA register
+ */
+/*@{*/
+#define I2C_RD_RA(base)          (I2C_RA_REG(base))
+#define I2C_WR_RA(base, value)   (I2C_RA_REG(base) = (value))
+#define I2C_RMW_RA(base, mask, value) (I2C_WR_RA(base, (I2C_RD_RA(base) & ~(mask)) | (value)))
+#define I2C_SET_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) |  (value)))
+#define I2C_CLR_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) & ~(value)))
+#define I2C_TOG_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_RA bitfields
+ */
+
+/*!
+ * @name Register I2C_RA, field RAD[7:1] (RW)
+ *
+ * This field contains the slave address to be used by the I2C module. The field
+ * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
+ * value write enables this register. This register value can be considered as a
+ * maximum boundary in the range matching mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_RA_RAD field. */
+#define I2C_RD_RA_RAD(base)  ((I2C_RA_REG(base) & I2C_RA_RAD_MASK) >> I2C_RA_RAD_SHIFT)
+#define I2C_BRD_RA_RAD(base) (I2C_RD_RA_RAD(base))
+
+/*! @brief Set the RAD field to a new value. */
+#define I2C_WR_RA_RAD(base, value) (I2C_RMW_RA(base, I2C_RA_RAD_MASK, I2C_RA_RAD(value)))
+#define I2C_BWR_RA_RAD(base, value) (I2C_WR_RA_RAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SMB - I2C SMBus Control and Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SMB - I2C SMBus Control and Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When the SCL and SDA signals are held high for a length of time greater than
+ * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
+ * while the system is detecting how long these signals are being held high, a
+ * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
+ * bus transmission process with the idle bus state. When the TCKSEL bit is set,
+ * there is no need to monitor the SHTF1 bit because the bus speed is too high to
+ * match the protocol of SMBus.
+ */
+/*!
+ * @name Constants and macros for entire I2C_SMB register
+ */
+/*@{*/
+#define I2C_RD_SMB(base)         (I2C_SMB_REG(base))
+#define I2C_WR_SMB(base, value)  (I2C_SMB_REG(base) = (value))
+#define I2C_RMW_SMB(base, mask, value) (I2C_WR_SMB(base, (I2C_RD_SMB(base) & ~(mask)) | (value)))
+#define I2C_SET_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) |  (value)))
+#define I2C_CLR_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) & ~(value)))
+#define I2C_TOG_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_SMB bitfields
+ */
+
+/*!
+ * @name Register I2C_SMB, field SHTF2IE[0] (RW)
+ *
+ * Enables SCL high and SDA low timeout interrupt.
+ *
+ * Values:
+ * - 0b0 - SHTF2 interrupt is disabled
+ * - 0b1 - SHTF2 interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2IE field. */
+#define I2C_RD_SMB_SHTF2IE(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2IE_MASK) >> I2C_SMB_SHTF2IE_SHIFT)
+#define I2C_BRD_SMB_SHTF2IE(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT))
+
+/*! @brief Set the SHTF2IE field to a new value. */
+#define I2C_WR_SMB_SHTF2IE(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2IE_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2IE(value)))
+#define I2C_BWR_SMB_SHTF2IE(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF2[1] (W1C)
+ *
+ * This bit sets when SCL is held high and SDA is held low more than clock *
+ * LoValue / 512. Software clears this bit by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No SCL high and SDA low timeout occurs
+ * - 0b1 - SCL high and SDA low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2 field. */
+#define I2C_RD_SMB_SHTF2(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2_MASK) >> I2C_SMB_SHTF2_SHIFT)
+#define I2C_BRD_SMB_SHTF2(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT))
+
+/*! @brief Set the SHTF2 field to a new value. */
+#define I2C_WR_SMB_SHTF2(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2(value)))
+#define I2C_BWR_SMB_SHTF2(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF1[2] (RO)
+ *
+ * This read-only bit sets when SCL and SDA are held high more than clock *
+ * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
+ *
+ * Values:
+ * - 0b0 - No SCL high and SDA high timeout occurs
+ * - 0b1 - SCL high and SDA high timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF1 field. */
+#define I2C_RD_SMB_SHTF1(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF1_MASK) >> I2C_SMB_SHTF1_SHIFT)
+#define I2C_BRD_SMB_SHTF1(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SLTF[3] (W1C)
+ *
+ * This bit is set when the SLT register (consisting of the SLTH and SLTL
+ * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
+ * Software clears this bit by writing a logic 1 to it. The low timeout function
+ * is disabled when the SLT register's value is 0.
+ *
+ * Values:
+ * - 0b0 - No low timeout occurs
+ * - 0b1 - Low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SLTF field. */
+#define I2C_RD_SMB_SLTF(base) ((I2C_SMB_REG(base) & I2C_SMB_SLTF_MASK) >> I2C_SMB_SLTF_SHIFT)
+#define I2C_BRD_SMB_SLTF(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT))
+
+/*! @brief Set the SLTF field to a new value. */
+#define I2C_WR_SMB_SLTF(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SLTF_MASK | I2C_SMB_SHTF2_MASK), I2C_SMB_SLTF(value)))
+#define I2C_BWR_SMB_SLTF(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field TCKSEL[4] (RW)
+ *
+ * Selects the clock source of the timeout counter.
+ *
+ * Values:
+ * - 0b0 - Timeout counter counts at the frequency of the I2C module clock / 64
+ * - 0b1 - Timeout counter counts at the frequency of the I2C module clock
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_TCKSEL field. */
+#define I2C_RD_SMB_TCKSEL(base) ((I2C_SMB_REG(base) & I2C_SMB_TCKSEL_MASK) >> I2C_SMB_TCKSEL_SHIFT)
+#define I2C_BRD_SMB_TCKSEL(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT))
+
+/*! @brief Set the TCKSEL field to a new value. */
+#define I2C_WR_SMB_TCKSEL(base, value) (I2C_RMW_SMB(base, (I2C_SMB_TCKSEL_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_TCKSEL(value)))
+#define I2C_BWR_SMB_TCKSEL(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SIICAEN[5] (RW)
+ *
+ * Enables or disables SMBus device default address.
+ *
+ * Values:
+ * - 0b0 - I2C address register 2 matching is disabled
+ * - 0b1 - I2C address register 2 matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SIICAEN field. */
+#define I2C_RD_SMB_SIICAEN(base) ((I2C_SMB_REG(base) & I2C_SMB_SIICAEN_MASK) >> I2C_SMB_SIICAEN_SHIFT)
+#define I2C_BRD_SMB_SIICAEN(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT))
+
+/*! @brief Set the SIICAEN field to a new value. */
+#define I2C_WR_SMB_SIICAEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SIICAEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SIICAEN(value)))
+#define I2C_BWR_SMB_SIICAEN(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field ALERTEN[6] (RW)
+ *
+ * Enables or disables SMBus alert response address matching. After the host
+ * responds to a device that used the alert response address, you must use software
+ * to put the device's address on the bus. The alert protocol is described in the
+ * SMBus specification.
+ *
+ * Values:
+ * - 0b0 - SMBus alert response address matching is disabled
+ * - 0b1 - SMBus alert response address matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_ALERTEN field. */
+#define I2C_RD_SMB_ALERTEN(base) ((I2C_SMB_REG(base) & I2C_SMB_ALERTEN_MASK) >> I2C_SMB_ALERTEN_SHIFT)
+#define I2C_BRD_SMB_ALERTEN(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT))
+
+/*! @brief Set the ALERTEN field to a new value. */
+#define I2C_WR_SMB_ALERTEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_ALERTEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_ALERTEN(value)))
+#define I2C_BWR_SMB_ALERTEN(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field FACK[7] (RW)
+ *
+ * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
+ * according to the result of receiving data byte.
+ *
+ * Values:
+ * - 0b0 - An ACK or NACK is sent on the following receiving data byte
+ * - 0b1 - Writing 0 to TXAK after receiving a data byte generates an ACK.
+ *     Writing 1 to TXAK after receiving a data byte generates a NACK.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_FACK field. */
+#define I2C_RD_SMB_FACK(base) ((I2C_SMB_REG(base) & I2C_SMB_FACK_MASK) >> I2C_SMB_FACK_SHIFT)
+#define I2C_BRD_SMB_FACK(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT))
+
+/*! @brief Set the FACK field to a new value. */
+#define I2C_WR_SMB_FACK(base, value) (I2C_RMW_SMB(base, (I2C_SMB_FACK_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_FACK(value)))
+#define I2C_BWR_SMB_FACK(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_A2 - I2C Address Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A2 - I2C Address Register 2 (RW)
+ *
+ * Reset value: 0xC2U
+ */
+/*!
+ * @name Constants and macros for entire I2C_A2 register
+ */
+/*@{*/
+#define I2C_RD_A2(base)          (I2C_A2_REG(base))
+#define I2C_WR_A2(base, value)   (I2C_A2_REG(base) = (value))
+#define I2C_RMW_A2(base, mask, value) (I2C_WR_A2(base, (I2C_RD_A2(base) & ~(mask)) | (value)))
+#define I2C_SET_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) |  (value)))
+#define I2C_CLR_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) & ~(value)))
+#define I2C_TOG_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A2 bitfields
+ */
+
+/*!
+ * @name Register I2C_A2, field SAD[7:1] (RW)
+ *
+ * Contains the slave address used by the SMBus. This field is used on the
+ * device default address or other related addresses.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A2_SAD field. */
+#define I2C_RD_A2_SAD(base)  ((I2C_A2_REG(base) & I2C_A2_SAD_MASK) >> I2C_A2_SAD_SHIFT)
+#define I2C_BRD_A2_SAD(base) (I2C_RD_A2_SAD(base))
+
+/*! @brief Set the SAD field to a new value. */
+#define I2C_WR_A2_SAD(base, value) (I2C_RMW_A2(base, I2C_A2_SAD_MASK, I2C_A2_SAD(value)))
+#define I2C_BWR_A2_SAD(base, value) (I2C_WR_A2_SAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTH - I2C SCL Low Timeout Register High
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTH - I2C SCL Low Timeout Register High (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTH register
+ */
+/*@{*/
+#define I2C_RD_SLTH(base)        (I2C_SLTH_REG(base))
+#define I2C_WR_SLTH(base, value) (I2C_SLTH_REG(base) = (value))
+#define I2C_RMW_SLTH(base, mask, value) (I2C_WR_SLTH(base, (I2C_RD_SLTH(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) |  (value)))
+#define I2C_CLR_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) & ~(value)))
+#define I2C_TOG_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTL - I2C SCL Low Timeout Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTL register
+ */
+/*@{*/
+#define I2C_RD_SLTL(base)        (I2C_SLTL_REG(base))
+#define I2C_WR_SLTL(base, value) (I2C_SLTL_REG(base) = (value))
+#define I2C_RMW_SLTL(base, mask, value) (I2C_WR_SLTL(base, (I2C_RD_SLTL(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) |  (value)))
+#define I2C_CLR_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) & ~(value)))
+#define I2C_TOG_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 I2S
+ *
+ * Inter-IC Sound / Synchronous Audio Interface
+ *
+ * Registers defined in this header file:
+ * - I2S_TCSR - SAI Transmit Control Register
+ * - I2S_TCR1 - SAI Transmit Configuration 1 Register
+ * - I2S_TCR2 - SAI Transmit Configuration 2 Register
+ * - I2S_TCR3 - SAI Transmit Configuration 3 Register
+ * - I2S_TCR4 - SAI Transmit Configuration 4 Register
+ * - I2S_TCR5 - SAI Transmit Configuration 5 Register
+ * - I2S_TDR - SAI Transmit Data Register
+ * - I2S_TFR - SAI Transmit FIFO Register
+ * - I2S_TMR - SAI Transmit Mask Register
+ * - I2S_RCSR - SAI Receive Control Register
+ * - I2S_RCR1 - SAI Receive Configuration 1 Register
+ * - I2S_RCR2 - SAI Receive Configuration 2 Register
+ * - I2S_RCR3 - SAI Receive Configuration 3 Register
+ * - I2S_RCR4 - SAI Receive Configuration 4 Register
+ * - I2S_RCR5 - SAI Receive Configuration 5 Register
+ * - I2S_RDR - SAI Receive Data Register
+ * - I2S_RFR - SAI Receive FIFO Register
+ * - I2S_RMR - SAI Receive Mask Register
+ * - I2S_MCR - SAI MCLK Control Register
+ * - I2S_MDR - SAI MCLK Divide Register
+ */
+
+#define I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */
+#define I2S0_IDX (0U) /*!< Instance number for I2S0. */
+
+/*******************************************************************************
+ * I2S_TCSR - SAI Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCSR - SAI Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCSR register
+ */
+/*@{*/
+#define I2S_RD_TCSR(base)        (I2S_TCSR_REG(base))
+#define I2S_WR_TCSR(base, value) (I2S_TCSR_REG(base) = (value))
+#define I2S_RMW_TCSR(base, mask, value) (I2S_WR_TCSR(base, (I2S_RD_TCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) |  (value)))
+#define I2S_CLR_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) & ~(value)))
+#define I2S_TOG_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_TCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRDE field. */
+#define I2S_RD_TCSR_FRDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRDE_MASK) >> I2S_TCSR_FRDE_SHIFT)
+#define I2S_BRD_TCSR_FRDE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRDE_SHIFT))
+
+/*! @brief Set the FRDE field to a new value. */
+#define I2S_WR_TCSR_FRDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FRDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FRDE(value)))
+#define I2S_BWR_TCSR_FRDE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWDE field. */
+#define I2S_RD_TCSR_FWDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWDE_MASK) >> I2S_TCSR_FWDE_SHIFT)
+#define I2S_BRD_TCSR_FWDE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_TCSR_FWDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWDE(value)))
+#define I2S_BWR_TCSR_FWDE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRIE field. */
+#define I2S_RD_TCSR_FRIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRIE_MASK) >> I2S_TCSR_FRIE_SHIFT)
+#define I2S_BRD_TCSR_FRIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRIE_SHIFT))
+
+/*! @brief Set the FRIE field to a new value. */
+#define I2S_WR_TCSR_FRIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FRIE(value)))
+#define I2S_BWR_TCSR_FRIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWIE field. */
+#define I2S_RD_TCSR_FWIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWIE_MASK) >> I2S_TCSR_FWIE_SHIFT)
+#define I2S_BRD_TCSR_FWIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_TCSR_FWIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWIE(value)))
+#define I2S_BWR_TCSR_FWIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEIE field. */
+#define I2S_RD_TCSR_FEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEIE_MASK) >> I2S_TCSR_FEIE_SHIFT)
+#define I2S_BRD_TCSR_FEIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_TCSR_FEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEIE(value)))
+#define I2S_BWR_TCSR_FEIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEIE field. */
+#define I2S_RD_TCSR_SEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEIE_MASK) >> I2S_TCSR_SEIE_SHIFT)
+#define I2S_BRD_TCSR_SEIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_TCSR_SEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEIE(value)))
+#define I2S_BWR_TCSR_SEIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSIE field. */
+#define I2S_RD_TCSR_WSIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSIE_MASK) >> I2S_TCSR_WSIE_SHIFT)
+#define I2S_BRD_TCSR_WSIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_TCSR_WSIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_WSIE(value)))
+#define I2S_BWR_TCSR_WSIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled transmit channel FIFO is
+ * less than or equal to the transmit FIFO watermark.
+ *
+ * Values:
+ * - 0b0 - Transmit FIFO watermark has not been reached.
+ * - 0b1 - Transmit FIFO watermark has been reached.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRF field. */
+#define I2S_RD_TCSR_FRF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRF_MASK) >> I2S_TCSR_FRF_SHIFT)
+#define I2S_BRD_TCSR_FRF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled transmit FIFO is empty.
+ *
+ * Values:
+ * - 0b0 - No enabled transmit FIFO is empty.
+ * - 0b1 - Enabled transmit FIFO is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWF field. */
+#define I2S_RD_TCSR_FWF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWF_MASK) >> I2S_TCSR_FWF_SHIFT)
+#define I2S_BRD_TCSR_FWF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
+ * field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Transmit underrun not detected.
+ * - 0b1 - Transmit underrun detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEF field. */
+#define I2S_RD_TCSR_FEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEF_MASK) >> I2S_TCSR_FEF_SHIFT)
+#define I2S_BRD_TCSR_FEF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_TCSR_FEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEF(value)))
+#define I2S_BWR_TCSR_FEF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Sync error not detected.
+ * - 0b1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEF field. */
+#define I2S_RD_TCSR_SEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEF_MASK) >> I2S_TCSR_SEF_SHIFT)
+#define I2S_BRD_TCSR_SEF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_TCSR_SEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEF(value)))
+#define I2S_BWR_TCSR_SEF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Start of word not detected.
+ * - 0b1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSF field. */
+#define I2S_RD_TCSR_WSF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSF_MASK) >> I2S_TCSR_WSF_SHIFT)
+#define I2S_BRD_TCSR_WSF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_TCSR_WSF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK), I2S_TCSR_WSF(value)))
+#define I2S_BWR_TCSR_WSF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SR[24] (RW)
+ *
+ * When set, resets the internal transmitter logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SR field. */
+#define I2S_RD_TCSR_SR(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SR_MASK) >> I2S_TCSR_SR_SHIFT)
+#define I2S_BRD_TCSR_SR(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_TCSR_SR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SR(value)))
+#define I2S_BWR_TCSR_SR(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the transmitter is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_TCSR_FR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FR(value)))
+#define I2S_BWR_TCSR_FR(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field BCE[28] (RW)
+ *
+ * Enables the transmit bit clock, separately from the TE. This field is
+ * automatically set whenever TE is set. When software clears this field, the transmit
+ * bit clock remains enabled, and this bit remains set, until the end of the
+ * current frame.
+ *
+ * Values:
+ * - 0b0 - Transmit bit clock is disabled.
+ * - 0b1 - Transmit bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_BCE field. */
+#define I2S_RD_TCSR_BCE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_BCE_MASK) >> I2S_TCSR_BCE_SHIFT)
+#define I2S_BRD_TCSR_BCE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_TCSR_BCE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_BCE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_BCE(value)))
+#define I2S_BWR_TCSR_BCE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables transmitter operation in Debug mode. The transmit bit clock
+ * is not affected by debug mode.
+ *
+ * Values:
+ * - 0b0 - Transmitter is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 0b1 - Transmitter is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_DBGE field. */
+#define I2S_RD_TCSR_DBGE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_DBGE_MASK) >> I2S_TCSR_DBGE_SHIFT)
+#define I2S_BRD_TCSR_DBGE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_TCSR_DBGE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_DBGE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_DBGE(value)))
+#define I2S_BWR_TCSR_DBGE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field STOPE[30] (RW)
+ *
+ * Configures transmitter operation in Stop mode. This field is ignored and the
+ * transmitter is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0b0 - Transmitter disabled in Stop mode.
+ * - 0b1 - Transmitter enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_STOPE field. */
+#define I2S_RD_TCSR_STOPE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_STOPE_MASK) >> I2S_TCSR_STOPE_SHIFT)
+#define I2S_BRD_TCSR_STOPE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_TCSR_STOPE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_STOPE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_STOPE(value)))
+#define I2S_BWR_TCSR_STOPE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field TE[31] (RW)
+ *
+ * Enables/disables the transmitter. When software clears this field, the
+ * transmitter remains enabled, and this bit remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0b0 - Transmitter is disabled.
+ * - 0b1 - Transmitter is enabled, or transmitter has been disabled and has not
+ *     yet reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_TE field. */
+#define I2S_RD_TCSR_TE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_TE_MASK) >> I2S_TCSR_TE_SHIFT)
+#define I2S_BRD_TCSR_TE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT))
+
+/*! @brief Set the TE field to a new value. */
+#define I2S_WR_TCSR_TE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_TE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_TE(value)))
+#define I2S_BWR_TCSR_TE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR1 - SAI Transmit Configuration 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR1 register
+ */
+/*@{*/
+#define I2S_RD_TCR1(base)        (I2S_TCR1_REG(base))
+#define I2S_WR_TCR1(base, value) (I2S_TCR1_REG(base) = (value))
+#define I2S_RMW_TCR1(base, mask, value) (I2S_WR_TCR1(base, (I2S_RD_TCR1(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) |  (value)))
+#define I2S_CLR_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) & ~(value)))
+#define I2S_TOG_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR1, field TFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled transmit channels.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR1_TFW field. */
+#define I2S_RD_TCR1_TFW(base) ((I2S_TCR1_REG(base) & I2S_TCR1_TFW_MASK) >> I2S_TCR1_TFW_SHIFT)
+#define I2S_BRD_TCR1_TFW(base) (I2S_RD_TCR1_TFW(base))
+
+/*! @brief Set the TFW field to a new value. */
+#define I2S_WR_TCR1_TFW(base, value) (I2S_RMW_TCR1(base, I2S_TCR1_TFW_MASK, I2S_TCR1_TFW(value)))
+#define I2S_BWR_TCR1_TFW(base, value) (I2S_WR_TCR1_TFW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR2 - SAI Transmit Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR2 register
+ */
+/*@{*/
+#define I2S_RD_TCR2(base)        (I2S_TCR2_REG(base))
+#define I2S_WR_TCR2(base, value) (I2S_TCR2_REG(base) = (value))
+#define I2S_RMW_TCR2(base, mask, value) (I2S_WR_TCR2(base, (I2S_RD_TCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) |  (value)))
+#define I2S_CLR_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) & ~(value)))
+#define I2S_TOG_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_DIV field. */
+#define I2S_RD_TCR2_DIV(base) ((I2S_TCR2_REG(base) & I2S_TCR2_DIV_MASK) >> I2S_TCR2_DIV_SHIFT)
+#define I2S_BRD_TCR2_DIV(base) (I2S_RD_TCR2_DIV(base))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_TCR2_DIV(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_DIV_MASK, I2S_TCR2_DIV(value)))
+#define I2S_BWR_TCR2_DIV(base, value) (I2S_WR_TCR2_DIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is generated externally in Slave mode.
+ * - 0b1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCD field. */
+#define I2S_RD_TCR2_BCD(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCD_MASK) >> I2S_TCR2_BCD_SHIFT)
+#define I2S_BRD_TCR2_BCD(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_TCR2_BCD(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCD_MASK, I2S_TCR2_BCD(value)))
+#define I2S_BWR_TCR2_BCD(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 0b1 - Bit clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCP field. */
+#define I2S_RD_TCR2_BCP(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCP_MASK) >> I2S_TCR2_BCP_SHIFT)
+#define I2S_BRD_TCR2_BCP(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_TCR2_BCP(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCP_MASK, I2S_TCR2_BCP(value)))
+#define I2S_BWR_TCR2_BCP(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 0b00 - Bus Clock selected.
+ * - 0b01 - Master Clock (MCLK) 1 option selected.
+ * - 0b10 - Master Clock (MCLK) 2 option selected.
+ * - 0b11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_MSEL field. */
+#define I2S_RD_TCR2_MSEL(base) ((I2S_TCR2_REG(base) & I2S_TCR2_MSEL_MASK) >> I2S_TCR2_MSEL_SHIFT)
+#define I2S_BRD_TCR2_MSEL(base) (I2S_RD_TCR2_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_TCR2_MSEL(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_MSEL_MASK, I2S_TCR2_MSEL(value)))
+#define I2S_BWR_TCR2_MSEL(base, value) (I2S_WR_TCR2_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the
+ * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
+ * input as if the clock was externally generated). This has the effect of
+ * decreasing the data input setup time, but increasing the data output valid time. The
+ * slave mode timing from the datasheet should be used for the transmitter when
+ * this bit is set. In synchronous mode, this bit allows the transmitter to use
+ * the slave mode timing from the datasheet, while the receiver uses the master
+ * mode timing. This field has no effect when configured for an externally generated
+ * bit clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCI field. */
+#define I2S_RD_TCR2_BCI(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCI_MASK) >> I2S_TCR2_BCI_SHIFT)
+#define I2S_BRD_TCR2_BCI(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_TCR2_BCI(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCI_MASK, I2S_TCR2_BCI(value)))
+#define I2S_BWR_TCR2_BCI(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the transmitter. When the transmitter
+ * is configured in asynchronous mode and this bit is set, the transmitter is
+ * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the transmitter continues to use the
+ * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
+ * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
+ * the same value. When both are set, the transmitter and receiver are both
+ * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
+ * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
+ * peripheral.
+ *
+ * Values:
+ * - 0b0 - Use the normal bit clock source.
+ * - 0b1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCS field. */
+#define I2S_RD_TCR2_BCS(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCS_MASK) >> I2S_TCR2_BCS_SHIFT)
+#define I2S_BRD_TCR2_BCS(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_TCR2_BCS(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCS_MASK, I2S_TCR2_BCS(value)))
+#define I2S_BWR_TCR2_BCS(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the receiver or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 0b00 - Asynchronous mode.
+ * - 0b01 - Synchronous with receiver.
+ * - 0b10 - Synchronous with another SAI transmitter.
+ * - 0b11 - Synchronous with another SAI receiver.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_SYNC field. */
+#define I2S_RD_TCR2_SYNC(base) ((I2S_TCR2_REG(base) & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT)
+#define I2S_BRD_TCR2_SYNC(base) (I2S_RD_TCR2_SYNC(base))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_TCR2_SYNC(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_SYNC_MASK, I2S_TCR2_SYNC(value)))
+#define I2S_BWR_TCR2_SYNC(base, value) (I2S_WR_TCR2_SYNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR3 - SAI Transmit Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR3 register
+ */
+/*@{*/
+#define I2S_RD_TCR3(base)        (I2S_TCR3_REG(base))
+#define I2S_WR_TCR3(base, value) (I2S_TCR3_REG(base) = (value))
+#define I2S_RMW_TCR3(base, mask, value) (I2S_WR_TCR3(base, (I2S_RD_TCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) |  (value)))
+#define I2S_CLR_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) & ~(value)))
+#define I2S_TOG_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word sets the start of word flag. The value written must be
+ * one less than the word number. For example, writing 0 configures the first
+ * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
+ * start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_WDFL field. */
+#define I2S_RD_TCR3_WDFL(base) ((I2S_TCR3_REG(base) & I2S_TCR3_WDFL_MASK) >> I2S_TCR3_WDFL_SHIFT)
+#define I2S_BRD_TCR3_WDFL(base) (I2S_RD_TCR3_WDFL(base))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_TCR3_WDFL(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_WDFL_MASK, I2S_TCR3_WDFL(value)))
+#define I2S_BWR_TCR3_WDFL(base, value) (I2S_WR_TCR3_WDFL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR3, field TCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for transmit operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0b00 - Transmit data channel N is disabled.
+ * - 0b01 - Transmit data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_TCE field. */
+#define I2S_RD_TCR3_TCE(base) ((I2S_TCR3_REG(base) & I2S_TCR3_TCE_MASK) >> I2S_TCR3_TCE_SHIFT)
+#define I2S_BRD_TCR3_TCE(base) (I2S_RD_TCR3_TCE(base))
+
+/*! @brief Set the TCE field to a new value. */
+#define I2S_WR_TCR3_TCE(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_TCE_MASK, I2S_TCR3_TCE(value)))
+#define I2S_BWR_TCR3_TCE(base, value) (I2S_WR_TCR3_TCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR4 - SAI Transmit Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR4 register
+ */
+/*@{*/
+#define I2S_RD_TCR4(base)        (I2S_TCR4_REG(base))
+#define I2S_WR_TCR4(base, value) (I2S_TCR4_REG(base) = (value))
+#define I2S_RMW_TCR4(base, mask, value) (I2S_WR_TCR4(base, (I2S_RD_TCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) |  (value)))
+#define I2S_CLR_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) & ~(value)))
+#define I2S_TOG_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is generated externally in Slave mode.
+ * - 0b1 - Frame sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSD field. */
+#define I2S_RD_TCR4_FSD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSD_MASK) >> I2S_TCR4_FSD_SHIFT)
+#define I2S_BRD_TCR4_FSD(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_TCR4_FSD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSD_MASK, I2S_TCR4_FSD(value)))
+#define I2S_BWR_TCR4_FSD(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is active high.
+ * - 0b1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSP field. */
+#define I2S_RD_TCR4_FSP(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSP_MASK) >> I2S_TCR4_FSP_SHIFT)
+#define I2S_BRD_TCR4_FSP(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_TCR4_FSP(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSP_MASK, I2S_TCR4_FSP(value)))
+#define I2S_BWR_TCR4_FSP(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Frame sync asserts with the first bit of the frame.
+ * - 0b1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSE field. */
+#define I2S_RD_TCR4_FSE(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSE_MASK) >> I2S_TCR4_FSE_SHIFT)
+#define I2S_BRD_TCR4_FSE(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_TCR4_FSE(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSE_MASK, I2S_TCR4_FSE(value)))
+#define I2S_BWR_TCR4_FSE(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is transmitted first.
+ *
+ * Values:
+ * - 0b0 - LSB is transmitted first.
+ * - 0b1 - MSB is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_MF field. */
+#define I2S_RD_TCR4_MF(base) ((I2S_TCR4_REG(base) & I2S_TCR4_MF_MASK) >> I2S_TCR4_MF_SHIFT)
+#define I2S_BRD_TCR4_MF(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_TCR4_MF(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_MF_MASK, I2S_TCR4_MF(value)))
+#define I2S_BWR_TCR4_MF(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_SYWD field. */
+#define I2S_RD_TCR4_SYWD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_SYWD_MASK) >> I2S_TCR4_SYWD_SHIFT)
+#define I2S_BRD_TCR4_SYWD(base) (I2S_RD_TCR4_SYWD(base))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_TCR4_SYWD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_SYWD_MASK, I2S_TCR4_SYWD(value)))
+#define I2S_BWR_TCR4_SYWD(base, value) (I2S_WR_TCR4_SYWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FRSZ field. */
+#define I2S_RD_TCR4_FRSZ(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FRSZ_MASK) >> I2S_TCR4_FRSZ_SHIFT)
+#define I2S_BRD_TCR4_FRSZ(base) (I2S_RD_TCR4_FRSZ(base))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_TCR4_FRSZ(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FRSZ_MASK, I2S_TCR4_FRSZ(value)))
+#define I2S_BWR_TCR4_FRSZ(base, value) (I2S_WR_TCR4_FRSZ(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR5 - SAI Transmit Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR5 register
+ */
+/*@{*/
+#define I2S_RD_TCR5(base)        (I2S_TCR5_REG(base))
+#define I2S_WR_TCR5(base, value) (I2S_TCR5_REG(base) = (value))
+#define I2S_RMW_TCR5(base, mask, value) (I2S_WR_TCR5(base, (I2S_RD_TCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) |  (value)))
+#define I2S_CLR_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) & ~(value)))
+#define I2S_TOG_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit transmitted for each word in the
+ * frame. If configured for MSB First, the index of the next bit transmitted is
+ * one less than the current bit transmitted. If configured for LSB First, the
+ * index of the next bit transmitted is one more than the current bit transmitted.
+ * The value written must be greater than or equal to the word width when
+ * configured for MSB First. The value written must be less than or equal to 31-word width
+ * when configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_FBT field. */
+#define I2S_RD_TCR5_FBT(base) ((I2S_TCR5_REG(base) & I2S_TCR5_FBT_MASK) >> I2S_TCR5_FBT_SHIFT)
+#define I2S_BRD_TCR5_FBT(base) (I2S_RD_TCR5_FBT(base))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_TCR5_FBT(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_FBT_MASK, I2S_TCR5_FBT(value)))
+#define I2S_BWR_TCR5_FBT(base, value) (I2S_WR_TCR5_FBT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_W0W field. */
+#define I2S_RD_TCR5_W0W(base) ((I2S_TCR5_REG(base) & I2S_TCR5_W0W_MASK) >> I2S_TCR5_W0W_SHIFT)
+#define I2S_BRD_TCR5_W0W(base) (I2S_RD_TCR5_W0W(base))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_TCR5_W0W(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_W0W_MASK, I2S_TCR5_W0W(value)))
+#define I2S_BWR_TCR5_W0W(base, value) (I2S_WR_TCR5_W0W(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_WNW field. */
+#define I2S_RD_TCR5_WNW(base) ((I2S_TCR5_REG(base) & I2S_TCR5_WNW_MASK) >> I2S_TCR5_WNW_SHIFT)
+#define I2S_BRD_TCR5_WNW(base) (I2S_RD_TCR5_WNW(base))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_TCR5_WNW(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_WNW_MASK, I2S_TCR5_WNW(value)))
+#define I2S_BWR_TCR5_WNW(base, value) (I2S_WR_TCR5_WNW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TDR - SAI Transmit Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TDR - SAI Transmit Data Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TDR register
+ */
+/*@{*/
+#define I2S_RD_TDR(base, index)  (I2S_TDR_REG(base, index))
+#define I2S_WR_TDR(base, index, value) (I2S_TDR_REG(base, index) = (value))
+#define I2S_RMW_TDR(base, index, mask, value) (I2S_WR_TDR(base, index, (I2S_RD_TDR(base, index) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TFR - SAI Transmit FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TFR - SAI Transmit FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TFR register
+ */
+/*@{*/
+#define I2S_RD_TFR(base, index)  (I2S_TFR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TFR bitfields
+ */
+
+/*!
+ * @name Register I2S_TFR, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for transmit data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TFR_RFP field. */
+#define I2S_RD_TFR_RFP(base, index) ((I2S_TFR_REG(base, index) & I2S_TFR_RFP_MASK) >> I2S_TFR_RFP_SHIFT)
+#define I2S_BRD_TFR_RFP(base, index) (I2S_RD_TFR_RFP(base, index))
+/*@}*/
+
+/*!
+ * @name Register I2S_TFR, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for transmit data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TFR_WFP field. */
+#define I2S_RD_TFR_WFP(base, index) ((I2S_TFR_REG(base, index) & I2S_TFR_WFP_MASK) >> I2S_TFR_WFP_SHIFT)
+#define I2S_BRD_TFR_WFP(base, index) (I2S_RD_TFR_WFP(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TMR - SAI Transmit Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TMR - SAI Transmit Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When TCSR[TE] is first set At
+ * the end of each frame. This allows the masked words in each frame to change
+ * from frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TMR register
+ */
+/*@{*/
+#define I2S_RD_TMR(base)         (I2S_TMR_REG(base))
+#define I2S_WR_TMR(base, value)  (I2S_TMR_REG(base) = (value))
+#define I2S_RMW_TMR(base, mask, value) (I2S_WR_TMR(base, (I2S_RD_TMR(base) & ~(mask)) | (value)))
+#define I2S_SET_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) |  (value)))
+#define I2S_CLR_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) & ~(value)))
+#define I2S_TOG_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCSR - SAI Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCSR - SAI Receive Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCSR register
+ */
+/*@{*/
+#define I2S_RD_RCSR(base)        (I2S_RCSR_REG(base))
+#define I2S_WR_RCSR(base, value) (I2S_RCSR_REG(base) = (value))
+#define I2S_RMW_RCSR(base, mask, value) (I2S_WR_RCSR(base, (I2S_RD_RCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) |  (value)))
+#define I2S_CLR_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) & ~(value)))
+#define I2S_TOG_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_RCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRDE field. */
+#define I2S_RD_RCSR_FRDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRDE_MASK) >> I2S_RCSR_FRDE_SHIFT)
+#define I2S_BRD_RCSR_FRDE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRDE_SHIFT))
+
+/*! @brief Set the FRDE field to a new value. */
+#define I2S_WR_RCSR_FRDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FRDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FRDE(value)))
+#define I2S_BWR_RCSR_FRDE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWDE field. */
+#define I2S_RD_RCSR_FWDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWDE_MASK) >> I2S_RCSR_FWDE_SHIFT)
+#define I2S_BRD_RCSR_FWDE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_RCSR_FWDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWDE(value)))
+#define I2S_BWR_RCSR_FWDE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRIE field. */
+#define I2S_RD_RCSR_FRIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRIE_MASK) >> I2S_RCSR_FRIE_SHIFT)
+#define I2S_BRD_RCSR_FRIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRIE_SHIFT))
+
+/*! @brief Set the FRIE field to a new value. */
+#define I2S_WR_RCSR_FRIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FRIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FRIE(value)))
+#define I2S_BWR_RCSR_FRIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWIE field. */
+#define I2S_RD_RCSR_FWIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWIE_MASK) >> I2S_RCSR_FWIE_SHIFT)
+#define I2S_BRD_RCSR_FWIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_RCSR_FWIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWIE(value)))
+#define I2S_BWR_RCSR_FWIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEIE field. */
+#define I2S_RD_RCSR_FEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEIE_MASK) >> I2S_RCSR_FEIE_SHIFT)
+#define I2S_BRD_RCSR_FEIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_RCSR_FEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEIE(value)))
+#define I2S_BWR_RCSR_FEIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEIE field. */
+#define I2S_RD_RCSR_SEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEIE_MASK) >> I2S_RCSR_SEIE_SHIFT)
+#define I2S_BRD_RCSR_SEIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_RCSR_SEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEIE(value)))
+#define I2S_BWR_RCSR_SEIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSIE field. */
+#define I2S_RD_RCSR_WSIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSIE_MASK) >> I2S_RCSR_WSIE_SHIFT)
+#define I2S_BRD_RCSR_WSIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_RCSR_WSIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_WSIE(value)))
+#define I2S_BWR_RCSR_WSIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled receive channel FIFO is
+ * greater than the receive FIFO watermark.
+ *
+ * Values:
+ * - 0b0 - Receive FIFO watermark not reached.
+ * - 0b1 - Receive FIFO watermark has been reached.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRF field. */
+#define I2S_RD_RCSR_FRF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRF_MASK) >> I2S_RCSR_FRF_SHIFT)
+#define I2S_BRD_RCSR_FRF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled receive FIFO is full.
+ *
+ * Values:
+ * - 0b0 - No enabled receive FIFO is full.
+ * - 0b1 - Enabled receive FIFO is full.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWF field. */
+#define I2S_RD_RCSR_FWF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWF_MASK) >> I2S_RCSR_FWF_SHIFT)
+#define I2S_BRD_RCSR_FWF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
+ * this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Receive overflow not detected.
+ * - 0b1 - Receive overflow detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEF field. */
+#define I2S_RD_RCSR_FEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEF_MASK) >> I2S_RCSR_FEF_SHIFT)
+#define I2S_BRD_RCSR_FEF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_RCSR_FEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEF(value)))
+#define I2S_BWR_RCSR_FEF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Sync error not detected.
+ * - 0b1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEF field. */
+#define I2S_RD_RCSR_SEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEF_MASK) >> I2S_RCSR_SEF_SHIFT)
+#define I2S_BRD_RCSR_SEF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_RCSR_SEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEF(value)))
+#define I2S_BWR_RCSR_SEF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Start of word not detected.
+ * - 0b1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSF field. */
+#define I2S_RD_RCSR_WSF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSF_MASK) >> I2S_RCSR_WSF_SHIFT)
+#define I2S_BRD_RCSR_WSF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_RCSR_WSF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK), I2S_RCSR_WSF(value)))
+#define I2S_BWR_RCSR_WSF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SR[24] (RW)
+ *
+ * Resets the internal receiver logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SR field. */
+#define I2S_RD_RCSR_SR(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SR_MASK) >> I2S_RCSR_SR_SHIFT)
+#define I2S_BRD_RCSR_SR(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_RCSR_SR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SR(value)))
+#define I2S_BWR_RCSR_SR(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the receiver is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_RCSR_FR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FR(value)))
+#define I2S_BWR_RCSR_FR(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field BCE[28] (RW)
+ *
+ * Enables the receive bit clock, separately from RE. This field is
+ * automatically set whenever RE is set. When software clears this field, the receive bit
+ * clock remains enabled, and this field remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0b0 - Receive bit clock is disabled.
+ * - 0b1 - Receive bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_BCE field. */
+#define I2S_RD_RCSR_BCE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_BCE_MASK) >> I2S_RCSR_BCE_SHIFT)
+#define I2S_BRD_RCSR_BCE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_RCSR_BCE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_BCE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_BCE(value)))
+#define I2S_BWR_RCSR_BCE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables receiver operation in Debug mode. The receive bit clock is
+ * not affected by Debug mode.
+ *
+ * Values:
+ * - 0b0 - Receiver is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 0b1 - Receiver is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_DBGE field. */
+#define I2S_RD_RCSR_DBGE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_DBGE_MASK) >> I2S_RCSR_DBGE_SHIFT)
+#define I2S_BRD_RCSR_DBGE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_RCSR_DBGE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_DBGE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_DBGE(value)))
+#define I2S_BWR_RCSR_DBGE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field STOPE[30] (RW)
+ *
+ * Configures receiver operation in Stop mode. This bit is ignored and the
+ * receiver is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0b0 - Receiver disabled in Stop mode.
+ * - 0b1 - Receiver enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_STOPE field. */
+#define I2S_RD_RCSR_STOPE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_STOPE_MASK) >> I2S_RCSR_STOPE_SHIFT)
+#define I2S_BRD_RCSR_STOPE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_RCSR_STOPE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_STOPE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_STOPE(value)))
+#define I2S_BWR_RCSR_STOPE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field RE[31] (RW)
+ *
+ * Enables/disables the receiver. When software clears this field, the receiver
+ * remains enabled, and this bit remains set, until the end of the current frame.
+ *
+ * Values:
+ * - 0b0 - Receiver is disabled.
+ * - 0b1 - Receiver is enabled, or receiver has been disabled and has not yet
+ *     reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_RE field. */
+#define I2S_RD_RCSR_RE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_RE_MASK) >> I2S_RCSR_RE_SHIFT)
+#define I2S_BRD_RCSR_RE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT))
+
+/*! @brief Set the RE field to a new value. */
+#define I2S_WR_RCSR_RE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_RE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_RE(value)))
+#define I2S_BWR_RCSR_RE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR1 - SAI Receive Configuration 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR1 register
+ */
+/*@{*/
+#define I2S_RD_RCR1(base)        (I2S_RCR1_REG(base))
+#define I2S_WR_RCR1(base, value) (I2S_RCR1_REG(base) = (value))
+#define I2S_RMW_RCR1(base, mask, value) (I2S_WR_RCR1(base, (I2S_RD_RCR1(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) |  (value)))
+#define I2S_CLR_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) & ~(value)))
+#define I2S_TOG_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR1, field RFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled receiver channels.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR1_RFW field. */
+#define I2S_RD_RCR1_RFW(base) ((I2S_RCR1_REG(base) & I2S_RCR1_RFW_MASK) >> I2S_RCR1_RFW_SHIFT)
+#define I2S_BRD_RCR1_RFW(base) (I2S_RD_RCR1_RFW(base))
+
+/*! @brief Set the RFW field to a new value. */
+#define I2S_WR_RCR1_RFW(base, value) (I2S_RMW_RCR1(base, I2S_RCR1_RFW_MASK, I2S_RCR1_RFW(value)))
+#define I2S_BWR_RCR1_RFW(base, value) (I2S_WR_RCR1_RFW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR2 - SAI Receive Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR2 register
+ */
+/*@{*/
+#define I2S_RD_RCR2(base)        (I2S_RCR2_REG(base))
+#define I2S_WR_RCR2(base, value) (I2S_RCR2_REG(base) = (value))
+#define I2S_RMW_RCR2(base, mask, value) (I2S_WR_RCR2(base, (I2S_RD_RCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) |  (value)))
+#define I2S_CLR_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) & ~(value)))
+#define I2S_TOG_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_DIV field. */
+#define I2S_RD_RCR2_DIV(base) ((I2S_RCR2_REG(base) & I2S_RCR2_DIV_MASK) >> I2S_RCR2_DIV_SHIFT)
+#define I2S_BRD_RCR2_DIV(base) (I2S_RD_RCR2_DIV(base))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_RCR2_DIV(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_DIV_MASK, I2S_RCR2_DIV(value)))
+#define I2S_BWR_RCR2_DIV(base, value) (I2S_WR_RCR2_DIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is generated externally in Slave mode.
+ * - 0b1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCD field. */
+#define I2S_RD_RCR2_BCD(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCD_MASK) >> I2S_RCR2_BCD_SHIFT)
+#define I2S_BRD_RCR2_BCD(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_RCR2_BCD(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCD_MASK, I2S_RCR2_BCD(value)))
+#define I2S_BWR_RCR2_BCD(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit Clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 0b1 - Bit Clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCP field. */
+#define I2S_RD_RCR2_BCP(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCP_MASK) >> I2S_RCR2_BCP_SHIFT)
+#define I2S_BRD_RCR2_BCP(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_RCR2_BCP(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCP_MASK, I2S_RCR2_BCP(value)))
+#define I2S_BWR_RCR2_BCP(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 0b00 - Bus Clock selected.
+ * - 0b01 - Master Clock (MCLK) 1 option selected.
+ * - 0b10 - Master Clock (MCLK) 2 option selected.
+ * - 0b11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_MSEL field. */
+#define I2S_RD_RCR2_MSEL(base) ((I2S_RCR2_REG(base) & I2S_RCR2_MSEL_MASK) >> I2S_RCR2_MSEL_SHIFT)
+#define I2S_BRD_RCR2_MSEL(base) (I2S_RD_RCR2_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_RCR2_MSEL(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_MSEL_MASK, I2S_RCR2_MSEL(value)))
+#define I2S_BWR_RCR2_MSEL(base, value) (I2S_WR_RCR2_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the receiver
+ * is delayed by the pad output delay (the receiver is clocked by the pad input
+ * as if the clock was externally generated). This has the effect of decreasing
+ * the data input setup time, but increasing the data output valid time. The slave
+ * mode timing from the datasheet should be used for the receiver when this bit
+ * is set. In synchronous mode, this bit allows the receiver to use the slave mode
+ * timing from the datasheet, while the transmitter uses the master mode timing.
+ * This field has no effect when configured for an externally generated bit
+ * clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCI field. */
+#define I2S_RD_RCR2_BCI(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCI_MASK) >> I2S_RCR2_BCI_SHIFT)
+#define I2S_BRD_RCR2_BCI(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_RCR2_BCI(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCI_MASK, I2S_RCR2_BCI(value)))
+#define I2S_BWR_RCR2_BCI(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the receiver. When the receiver is
+ * configured in asynchronous mode and this bit is set, the receiver is clocked by
+ * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the receiver continues to use the receiver
+ * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
+ * mode, the transmitter BCS field and receiver BCS field must be set to the same
+ * value. When both are set, the transmitter and receiver are both clocked by the
+ * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
+ * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
+ *
+ * Values:
+ * - 0b0 - Use the normal bit clock source.
+ * - 0b1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCS field. */
+#define I2S_RD_RCR2_BCS(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCS_MASK) >> I2S_RCR2_BCS_SHIFT)
+#define I2S_BRD_RCR2_BCS(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_RCR2_BCS(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCS_MASK, I2S_RCR2_BCS(value)))
+#define I2S_BWR_RCR2_BCS(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the transmitter or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 0b00 - Asynchronous mode.
+ * - 0b01 - Synchronous with transmitter.
+ * - 0b10 - Synchronous with another SAI receiver.
+ * - 0b11 - Synchronous with another SAI transmitter.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_SYNC field. */
+#define I2S_RD_RCR2_SYNC(base) ((I2S_RCR2_REG(base) & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT)
+#define I2S_BRD_RCR2_SYNC(base) (I2S_RD_RCR2_SYNC(base))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_RCR2_SYNC(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_SYNC_MASK, I2S_RCR2_SYNC(value)))
+#define I2S_BWR_RCR2_SYNC(base, value) (I2S_WR_RCR2_SYNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR3 - SAI Receive Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR3 register
+ */
+/*@{*/
+#define I2S_RD_RCR3(base)        (I2S_RCR3_REG(base))
+#define I2S_WR_RCR3(base, value) (I2S_RCR3_REG(base) = (value))
+#define I2S_RMW_RCR3(base, mask, value) (I2S_WR_RCR3(base, (I2S_RD_RCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) |  (value)))
+#define I2S_CLR_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) & ~(value)))
+#define I2S_TOG_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word the start of word flag is set. The value written should
+ * be one less than the word number (for example, write zero to configure for
+ * the first word in the frame). When configured to a value greater than the Frame
+ * Size field, then the start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_WDFL field. */
+#define I2S_RD_RCR3_WDFL(base) ((I2S_RCR3_REG(base) & I2S_RCR3_WDFL_MASK) >> I2S_RCR3_WDFL_SHIFT)
+#define I2S_BRD_RCR3_WDFL(base) (I2S_RD_RCR3_WDFL(base))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_RCR3_WDFL(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_WDFL_MASK, I2S_RCR3_WDFL(value)))
+#define I2S_BWR_RCR3_WDFL(base, value) (I2S_WR_RCR3_WDFL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR3, field RCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for receive operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0b00 - Receive data channel N is disabled.
+ * - 0b01 - Receive data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_RCE field. */
+#define I2S_RD_RCR3_RCE(base) ((I2S_RCR3_REG(base) & I2S_RCR3_RCE_MASK) >> I2S_RCR3_RCE_SHIFT)
+#define I2S_BRD_RCR3_RCE(base) (I2S_RD_RCR3_RCE(base))
+
+/*! @brief Set the RCE field to a new value. */
+#define I2S_WR_RCR3_RCE(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_RCE_MASK, I2S_RCR3_RCE(value)))
+#define I2S_BWR_RCR3_RCE(base, value) (I2S_WR_RCR3_RCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR4 - SAI Receive Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR4 register
+ */
+/*@{*/
+#define I2S_RD_RCR4(base)        (I2S_RCR4_REG(base))
+#define I2S_WR_RCR4(base, value) (I2S_RCR4_REG(base) = (value))
+#define I2S_RMW_RCR4(base, mask, value) (I2S_WR_RCR4(base, (I2S_RD_RCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) |  (value)))
+#define I2S_CLR_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) & ~(value)))
+#define I2S_TOG_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame Sync is generated externally in Slave mode.
+ * - 0b1 - Frame Sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSD field. */
+#define I2S_RD_RCR4_FSD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSD_MASK) >> I2S_RCR4_FSD_SHIFT)
+#define I2S_BRD_RCR4_FSD(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_RCR4_FSD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSD_MASK, I2S_RCR4_FSD(value)))
+#define I2S_BWR_RCR4_FSD(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is active high.
+ * - 0b1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSP field. */
+#define I2S_RD_RCR4_FSP(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSP_MASK) >> I2S_RCR4_FSP_SHIFT)
+#define I2S_BRD_RCR4_FSP(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_RCR4_FSP(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSP_MASK, I2S_RCR4_FSP(value)))
+#define I2S_BWR_RCR4_FSP(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Frame sync asserts with the first bit of the frame.
+ * - 0b1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSE field. */
+#define I2S_RD_RCR4_FSE(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSE_MASK) >> I2S_RCR4_FSE_SHIFT)
+#define I2S_BRD_RCR4_FSE(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_RCR4_FSE(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSE_MASK, I2S_RCR4_FSE(value)))
+#define I2S_BWR_RCR4_FSE(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is received first.
+ *
+ * Values:
+ * - 0b0 - LSB is received first.
+ * - 0b1 - MSB is received first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_MF field. */
+#define I2S_RD_RCR4_MF(base) ((I2S_RCR4_REG(base) & I2S_RCR4_MF_MASK) >> I2S_RCR4_MF_SHIFT)
+#define I2S_BRD_RCR4_MF(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_RCR4_MF(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_MF_MASK, I2S_RCR4_MF(value)))
+#define I2S_BWR_RCR4_MF(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_SYWD field. */
+#define I2S_RD_RCR4_SYWD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_SYWD_MASK) >> I2S_RCR4_SYWD_SHIFT)
+#define I2S_BRD_RCR4_SYWD(base) (I2S_RD_RCR4_SYWD(base))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_RCR4_SYWD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_SYWD_MASK, I2S_RCR4_SYWD(value)))
+#define I2S_BWR_RCR4_SYWD(base, value) (I2S_WR_RCR4_SYWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FRSZ field. */
+#define I2S_RD_RCR4_FRSZ(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FRSZ_MASK) >> I2S_RCR4_FRSZ_SHIFT)
+#define I2S_BRD_RCR4_FRSZ(base) (I2S_RD_RCR4_FRSZ(base))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_RCR4_FRSZ(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FRSZ_MASK, I2S_RCR4_FRSZ(value)))
+#define I2S_BWR_RCR4_FRSZ(base, value) (I2S_WR_RCR4_FRSZ(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR5 - SAI Receive Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR5 register
+ */
+/*@{*/
+#define I2S_RD_RCR5(base)        (I2S_RCR5_REG(base))
+#define I2S_WR_RCR5(base, value) (I2S_RCR5_REG(base) = (value))
+#define I2S_RMW_RCR5(base, mask, value) (I2S_WR_RCR5(base, (I2S_RD_RCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) |  (value)))
+#define I2S_CLR_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) & ~(value)))
+#define I2S_TOG_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit received for each word in the
+ * frame. If configured for MSB First, the index of the next bit received is one less
+ * than the current bit received. If configured for LSB First, the index of the
+ * next bit received is one more than the current bit received. The value written
+ * must be greater than or equal to the word width when configured for MSB
+ * First. The value written must be less than or equal to 31-word width when
+ * configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_FBT field. */
+#define I2S_RD_RCR5_FBT(base) ((I2S_RCR5_REG(base) & I2S_RCR5_FBT_MASK) >> I2S_RCR5_FBT_SHIFT)
+#define I2S_BRD_RCR5_FBT(base) (I2S_RD_RCR5_FBT(base))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_RCR5_FBT(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_FBT_MASK, I2S_RCR5_FBT(value)))
+#define I2S_BWR_RCR5_FBT(base, value) (I2S_WR_RCR5_FBT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_W0W field. */
+#define I2S_RD_RCR5_W0W(base) ((I2S_RCR5_REG(base) & I2S_RCR5_W0W_MASK) >> I2S_RCR5_W0W_SHIFT)
+#define I2S_BRD_RCR5_W0W(base) (I2S_RD_RCR5_W0W(base))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_RCR5_W0W(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_W0W_MASK, I2S_RCR5_W0W(value)))
+#define I2S_BWR_RCR5_W0W(base, value) (I2S_WR_RCR5_W0W(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_WNW field. */
+#define I2S_RD_RCR5_WNW(base) ((I2S_RCR5_REG(base) & I2S_RCR5_WNW_MASK) >> I2S_RCR5_WNW_SHIFT)
+#define I2S_BRD_RCR5_WNW(base) (I2S_RD_RCR5_WNW(base))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_RCR5_WNW(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_WNW_MASK, I2S_RCR5_WNW(value)))
+#define I2S_BWR_RCR5_WNW(base, value) (I2S_WR_RCR5_WNW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RDR - SAI Receive Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RDR - SAI Receive Data Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Reading this register introduces one additional peripheral clock wait state
+ * on each read.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RDR register
+ */
+/*@{*/
+#define I2S_RD_RDR(base, index)  (I2S_RDR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RFR - SAI Receive FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RFR - SAI Receive FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RFR register
+ */
+/*@{*/
+#define I2S_RD_RFR(base, index)  (I2S_RFR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RFR bitfields
+ */
+
+/*!
+ * @name Register I2S_RFR, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for receive data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RFR_RFP field. */
+#define I2S_RD_RFR_RFP(base, index) ((I2S_RFR_REG(base, index) & I2S_RFR_RFP_MASK) >> I2S_RFR_RFP_SHIFT)
+#define I2S_BRD_RFR_RFP(base, index) (I2S_RD_RFR_RFP(base, index))
+/*@}*/
+
+/*!
+ * @name Register I2S_RFR, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for receive data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RFR_WFP field. */
+#define I2S_RD_RFR_WFP(base, index) ((I2S_RFR_REG(base, index) & I2S_RFR_WFP_MASK) >> I2S_RFR_WFP_SHIFT)
+#define I2S_BRD_RFR_WFP(base, index) (I2S_RD_RFR_WFP(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RMR - SAI Receive Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RMR - SAI Receive Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When RCSR[RE] is first set At
+ * the end of each frame This allows the masked words in each frame to change from
+ * frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RMR register
+ */
+/*@{*/
+#define I2S_RD_RMR(base)         (I2S_RMR_REG(base))
+#define I2S_WR_RMR(base, value)  (I2S_RMR_REG(base) = (value))
+#define I2S_RMW_RMR(base, mask, value) (I2S_WR_RMR(base, (I2S_RD_RMR(base) & ~(mask)) | (value)))
+#define I2S_SET_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) |  (value)))
+#define I2S_CLR_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) & ~(value)))
+#define I2S_TOG_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MCR - SAI MCLK Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MCR - SAI MCLK Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Control Register (MCR) controls the clock source and direction of
+ * the audio master clock.
+ */
+/*!
+ * @name Constants and macros for entire I2S_MCR register
+ */
+/*@{*/
+#define I2S_RD_MCR(base)         (I2S_MCR_REG(base))
+#define I2S_WR_MCR(base, value)  (I2S_MCR_REG(base) = (value))
+#define I2S_RMW_MCR(base, mask, value) (I2S_WR_MCR(base, (I2S_RD_MCR(base) & ~(mask)) | (value)))
+#define I2S_SET_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) |  (value)))
+#define I2S_CLR_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) & ~(value)))
+#define I2S_TOG_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MCR bitfields
+ */
+
+/*!
+ * @name Register I2S_MCR, field MICS[25:24] (RW)
+ *
+ * Selects the clock input to the MCLK divider. This field cannot be changed
+ * while the MCLK divider is enabled. See the chip configuration details for
+ * information about the connections to these inputs.
+ *
+ * Values:
+ * - 0b00 - MCLK divider input clock 0 selected.
+ * - 0b01 - MCLK divider input clock 1 selected.
+ * - 0b10 - MCLK divider input clock 2 selected.
+ * - 0b11 - MCLK divider input clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MICS field. */
+#define I2S_RD_MCR_MICS(base) ((I2S_MCR_REG(base) & I2S_MCR_MICS_MASK) >> I2S_MCR_MICS_SHIFT)
+#define I2S_BRD_MCR_MICS(base) (I2S_RD_MCR_MICS(base))
+
+/*! @brief Set the MICS field to a new value. */
+#define I2S_WR_MCR_MICS(base, value) (I2S_RMW_MCR(base, I2S_MCR_MICS_MASK, I2S_MCR_MICS(value)))
+#define I2S_BWR_MCR_MICS(base, value) (I2S_WR_MCR_MICS(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field MOE[30] (RW)
+ *
+ * Enables the MCLK divider and configures the MCLK signal pin as an output.
+ * When software clears this field, it remains set until the MCLK divider is fully
+ * disabled.
+ *
+ * Values:
+ * - 0b0 - MCLK signal pin is configured as an input that bypasses the MCLK
+ *     divider.
+ * - 0b1 - MCLK signal pin is configured as an output from the MCLK divider and
+ *     the MCLK divider is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MOE field. */
+#define I2S_RD_MCR_MOE(base) ((I2S_MCR_REG(base) & I2S_MCR_MOE_MASK) >> I2S_MCR_MOE_SHIFT)
+#define I2S_BRD_MCR_MOE(base) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT))
+
+/*! @brief Set the MOE field to a new value. */
+#define I2S_WR_MCR_MOE(base, value) (I2S_RMW_MCR(base, I2S_MCR_MOE_MASK, I2S_MCR_MOE(value)))
+#define I2S_BWR_MCR_MOE(base, value) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field DUF[31] (RO)
+ *
+ * Provides the status of on-the-fly updates to the MCLK divider ratio.
+ *
+ * Values:
+ * - 0b0 - MCLK divider ratio is not being updated currently.
+ * - 0b1 - MCLK divider ratio is updating on-the-fly. Further updates to the
+ *     MCLK divider ratio are blocked while this flag remains set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_DUF field. */
+#define I2S_RD_MCR_DUF(base) ((I2S_MCR_REG(base) & I2S_MCR_DUF_MASK) >> I2S_MCR_DUF_SHIFT)
+#define I2S_BRD_MCR_DUF(base) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_DUF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MDR - SAI MCLK Divide Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MDR - SAI MCLK Divide Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
+ * MDR can be changed when the MCLK divider clock is enabled, additional writes
+ * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
+ * divided clock is disabled do not set MCR[DUF].
+ */
+/*!
+ * @name Constants and macros for entire I2S_MDR register
+ */
+/*@{*/
+#define I2S_RD_MDR(base)         (I2S_MDR_REG(base))
+#define I2S_WR_MDR(base, value)  (I2S_MDR_REG(base) = (value))
+#define I2S_RMW_MDR(base, mask, value) (I2S_WR_MDR(base, (I2S_RD_MDR(base) & ~(mask)) | (value)))
+#define I2S_SET_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) |  (value)))
+#define I2S_CLR_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) & ~(value)))
+#define I2S_TOG_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MDR bitfields
+ */
+
+/*!
+ * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MDR_DIVIDE field. */
+#define I2S_RD_MDR_DIVIDE(base) ((I2S_MDR_REG(base) & I2S_MDR_DIVIDE_MASK) >> I2S_MDR_DIVIDE_SHIFT)
+#define I2S_BRD_MDR_DIVIDE(base) (I2S_RD_MDR_DIVIDE(base))
+
+/*! @brief Set the DIVIDE field to a new value. */
+#define I2S_WR_MDR_DIVIDE(base, value) (I2S_RMW_MDR(base, I2S_MDR_DIVIDE_MASK, I2S_MDR_DIVIDE(value)))
+#define I2S_BWR_MDR_DIVIDE(base, value) (I2S_WR_MDR_DIVIDE(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MDR, field FRACT[19:12] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MDR_FRACT field. */
+#define I2S_RD_MDR_FRACT(base) ((I2S_MDR_REG(base) & I2S_MDR_FRACT_MASK) >> I2S_MDR_FRACT_SHIFT)
+#define I2S_BRD_MDR_FRACT(base) (I2S_RD_MDR_FRACT(base))
+
+/*! @brief Set the FRACT field to a new value. */
+#define I2S_WR_MDR_FRACT(base, value) (I2S_RMW_MDR(base, I2S_MDR_FRACT_MASK, I2S_MDR_FRACT(value)))
+#define I2S_BWR_MDR_FRACT(base, value) (I2S_WR_MDR_FRACT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 LLWU
+ *
+ * Low leakage wakeup unit
+ *
+ * Registers defined in this header file:
+ * - LLWU_PE1 - LLWU Pin Enable 1 register
+ * - LLWU_PE2 - LLWU Pin Enable 2 register
+ * - LLWU_PE3 - LLWU Pin Enable 3 register
+ * - LLWU_PE4 - LLWU Pin Enable 4 register
+ * - LLWU_ME - LLWU Module Enable register
+ * - LLWU_F1 - LLWU Flag 1 register
+ * - LLWU_F2 - LLWU Flag 2 register
+ * - LLWU_F3 - LLWU Flag 3 register
+ * - LLWU_FILT1 - LLWU Pin Filter 1 register
+ * - LLWU_FILT2 - LLWU Pin Filter 2 register
+ * - LLWU_RST - LLWU Reset Enable register
+ */
+
+#define LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
+#define LLWU_IDX (0U) /*!< Instance number for LLWU. */
+
+/*******************************************************************************
+ * LLWU_PE1 - LLWU Pin Enable 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE1 - LLWU Pin Enable 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE1 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE1 register
+ */
+/*@{*/
+#define LLWU_RD_PE1(base)        (LLWU_PE1_REG(base))
+#define LLWU_WR_PE1(base, value) (LLWU_PE1_REG(base) = (value))
+#define LLWU_RMW_PE1(base, mask, value) (LLWU_WR_PE1(base, (LLWU_RD_PE1(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) |  (value)))
+#define LLWU_CLR_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) & ~(value)))
+#define LLWU_TOG_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
+#define LLWU_RD_PE1_WUPE0(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE0_MASK) >> LLWU_PE1_WUPE0_SHIFT)
+#define LLWU_BRD_PE1_WUPE0(base) (LLWU_RD_PE1_WUPE0(base))
+
+/*! @brief Set the WUPE0 field to a new value. */
+#define LLWU_WR_PE1_WUPE0(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE0_MASK, LLWU_PE1_WUPE0(value)))
+#define LLWU_BWR_PE1_WUPE0(base, value) (LLWU_WR_PE1_WUPE0(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
+#define LLWU_RD_PE1_WUPE1(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE1_MASK) >> LLWU_PE1_WUPE1_SHIFT)
+#define LLWU_BRD_PE1_WUPE1(base) (LLWU_RD_PE1_WUPE1(base))
+
+/*! @brief Set the WUPE1 field to a new value. */
+#define LLWU_WR_PE1_WUPE1(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE1_MASK, LLWU_PE1_WUPE1(value)))
+#define LLWU_BWR_PE1_WUPE1(base, value) (LLWU_WR_PE1_WUPE1(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
+#define LLWU_RD_PE1_WUPE2(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE2_MASK) >> LLWU_PE1_WUPE2_SHIFT)
+#define LLWU_BRD_PE1_WUPE2(base) (LLWU_RD_PE1_WUPE2(base))
+
+/*! @brief Set the WUPE2 field to a new value. */
+#define LLWU_WR_PE1_WUPE2(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE2_MASK, LLWU_PE1_WUPE2(value)))
+#define LLWU_BWR_PE1_WUPE2(base, value) (LLWU_WR_PE1_WUPE2(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
+#define LLWU_RD_PE1_WUPE3(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE3_MASK) >> LLWU_PE1_WUPE3_SHIFT)
+#define LLWU_BRD_PE1_WUPE3(base) (LLWU_RD_PE1_WUPE3(base))
+
+/*! @brief Set the WUPE3 field to a new value. */
+#define LLWU_WR_PE1_WUPE3(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE3_MASK, LLWU_PE1_WUPE3(value)))
+#define LLWU_BWR_PE1_WUPE3(base, value) (LLWU_WR_PE1_WUPE3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE2 - LLWU Pin Enable 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE2 - LLWU Pin Enable 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE2 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE2 register
+ */
+/*@{*/
+#define LLWU_RD_PE2(base)        (LLWU_PE2_REG(base))
+#define LLWU_WR_PE2(base, value) (LLWU_PE2_REG(base) = (value))
+#define LLWU_RMW_PE2(base, mask, value) (LLWU_WR_PE2(base, (LLWU_RD_PE2(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) |  (value)))
+#define LLWU_CLR_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) & ~(value)))
+#define LLWU_TOG_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
+#define LLWU_RD_PE2_WUPE4(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE4_MASK) >> LLWU_PE2_WUPE4_SHIFT)
+#define LLWU_BRD_PE2_WUPE4(base) (LLWU_RD_PE2_WUPE4(base))
+
+/*! @brief Set the WUPE4 field to a new value. */
+#define LLWU_WR_PE2_WUPE4(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE4_MASK, LLWU_PE2_WUPE4(value)))
+#define LLWU_BWR_PE2_WUPE4(base, value) (LLWU_WR_PE2_WUPE4(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
+#define LLWU_RD_PE2_WUPE5(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE5_MASK) >> LLWU_PE2_WUPE5_SHIFT)
+#define LLWU_BRD_PE2_WUPE5(base) (LLWU_RD_PE2_WUPE5(base))
+
+/*! @brief Set the WUPE5 field to a new value. */
+#define LLWU_WR_PE2_WUPE5(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE5_MASK, LLWU_PE2_WUPE5(value)))
+#define LLWU_BWR_PE2_WUPE5(base, value) (LLWU_WR_PE2_WUPE5(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
+#define LLWU_RD_PE2_WUPE6(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE6_MASK) >> LLWU_PE2_WUPE6_SHIFT)
+#define LLWU_BRD_PE2_WUPE6(base) (LLWU_RD_PE2_WUPE6(base))
+
+/*! @brief Set the WUPE6 field to a new value. */
+#define LLWU_WR_PE2_WUPE6(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE6_MASK, LLWU_PE2_WUPE6(value)))
+#define LLWU_BWR_PE2_WUPE6(base, value) (LLWU_WR_PE2_WUPE6(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
+#define LLWU_RD_PE2_WUPE7(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE7_MASK) >> LLWU_PE2_WUPE7_SHIFT)
+#define LLWU_BRD_PE2_WUPE7(base) (LLWU_RD_PE2_WUPE7(base))
+
+/*! @brief Set the WUPE7 field to a new value. */
+#define LLWU_WR_PE2_WUPE7(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE7_MASK, LLWU_PE2_WUPE7(value)))
+#define LLWU_BWR_PE2_WUPE7(base, value) (LLWU_WR_PE2_WUPE7(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE3 - LLWU Pin Enable 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE3 - LLWU Pin Enable 3 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE3 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE3 register
+ */
+/*@{*/
+#define LLWU_RD_PE3(base)        (LLWU_PE3_REG(base))
+#define LLWU_WR_PE3(base, value) (LLWU_PE3_REG(base) = (value))
+#define LLWU_RMW_PE3(base, mask, value) (LLWU_WR_PE3(base, (LLWU_RD_PE3(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) |  (value)))
+#define LLWU_CLR_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) & ~(value)))
+#define LLWU_TOG_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
+#define LLWU_RD_PE3_WUPE8(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE8_MASK) >> LLWU_PE3_WUPE8_SHIFT)
+#define LLWU_BRD_PE3_WUPE8(base) (LLWU_RD_PE3_WUPE8(base))
+
+/*! @brief Set the WUPE8 field to a new value. */
+#define LLWU_WR_PE3_WUPE8(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE8_MASK, LLWU_PE3_WUPE8(value)))
+#define LLWU_BWR_PE3_WUPE8(base, value) (LLWU_WR_PE3_WUPE8(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
+#define LLWU_RD_PE3_WUPE9(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE9_MASK) >> LLWU_PE3_WUPE9_SHIFT)
+#define LLWU_BRD_PE3_WUPE9(base) (LLWU_RD_PE3_WUPE9(base))
+
+/*! @brief Set the WUPE9 field to a new value. */
+#define LLWU_WR_PE3_WUPE9(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE9_MASK, LLWU_PE3_WUPE9(value)))
+#define LLWU_BWR_PE3_WUPE9(base, value) (LLWU_WR_PE3_WUPE9(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
+#define LLWU_RD_PE3_WUPE10(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE10_MASK) >> LLWU_PE3_WUPE10_SHIFT)
+#define LLWU_BRD_PE3_WUPE10(base) (LLWU_RD_PE3_WUPE10(base))
+
+/*! @brief Set the WUPE10 field to a new value. */
+#define LLWU_WR_PE3_WUPE10(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE10_MASK, LLWU_PE3_WUPE10(value)))
+#define LLWU_BWR_PE3_WUPE10(base, value) (LLWU_WR_PE3_WUPE10(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
+#define LLWU_RD_PE3_WUPE11(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE11_MASK) >> LLWU_PE3_WUPE11_SHIFT)
+#define LLWU_BRD_PE3_WUPE11(base) (LLWU_RD_PE3_WUPE11(base))
+
+/*! @brief Set the WUPE11 field to a new value. */
+#define LLWU_WR_PE3_WUPE11(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE11_MASK, LLWU_PE3_WUPE11(value)))
+#define LLWU_BWR_PE3_WUPE11(base, value) (LLWU_WR_PE3_WUPE11(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE4 - LLWU Pin Enable 4 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE4 - LLWU Pin Enable 4 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE4 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE4 register
+ */
+/*@{*/
+#define LLWU_RD_PE4(base)        (LLWU_PE4_REG(base))
+#define LLWU_WR_PE4(base, value) (LLWU_PE4_REG(base) = (value))
+#define LLWU_RMW_PE4(base, mask, value) (LLWU_WR_PE4(base, (LLWU_RD_PE4(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) |  (value)))
+#define LLWU_CLR_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) & ~(value)))
+#define LLWU_TOG_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE4 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
+#define LLWU_RD_PE4_WUPE12(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE12_MASK) >> LLWU_PE4_WUPE12_SHIFT)
+#define LLWU_BRD_PE4_WUPE12(base) (LLWU_RD_PE4_WUPE12(base))
+
+/*! @brief Set the WUPE12 field to a new value. */
+#define LLWU_WR_PE4_WUPE12(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE12_MASK, LLWU_PE4_WUPE12(value)))
+#define LLWU_BWR_PE4_WUPE12(base, value) (LLWU_WR_PE4_WUPE12(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
+#define LLWU_RD_PE4_WUPE13(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE13_MASK) >> LLWU_PE4_WUPE13_SHIFT)
+#define LLWU_BRD_PE4_WUPE13(base) (LLWU_RD_PE4_WUPE13(base))
+
+/*! @brief Set the WUPE13 field to a new value. */
+#define LLWU_WR_PE4_WUPE13(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE13_MASK, LLWU_PE4_WUPE13(value)))
+#define LLWU_BWR_PE4_WUPE13(base, value) (LLWU_WR_PE4_WUPE13(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
+#define LLWU_RD_PE4_WUPE14(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE14_MASK) >> LLWU_PE4_WUPE14_SHIFT)
+#define LLWU_BRD_PE4_WUPE14(base) (LLWU_RD_PE4_WUPE14(base))
+
+/*! @brief Set the WUPE14 field to a new value. */
+#define LLWU_WR_PE4_WUPE14(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE14_MASK, LLWU_PE4_WUPE14(value)))
+#define LLWU_BWR_PE4_WUPE14(base, value) (LLWU_WR_PE4_WUPE14(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
+#define LLWU_RD_PE4_WUPE15(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE15_MASK) >> LLWU_PE4_WUPE15_SHIFT)
+#define LLWU_BRD_PE4_WUPE15(base) (LLWU_RD_PE4_WUPE15(base))
+
+/*! @brief Set the WUPE15 field to a new value. */
+#define LLWU_WR_PE4_WUPE15(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE15_MASK, LLWU_PE4_WUPE15(value)))
+#define LLWU_BWR_PE4_WUPE15(base, value) (LLWU_WR_PE4_WUPE15(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_ME - LLWU Module Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_ME - LLWU Module Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_ME contains the bits to enable the internal module flag as a wakeup
+ * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
+ * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
+ * reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
+ * RCM implements many of the reset functions for the chip. See the chip's reset
+ * chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_ME register
+ */
+/*@{*/
+#define LLWU_RD_ME(base)         (LLWU_ME_REG(base))
+#define LLWU_WR_ME(base, value)  (LLWU_ME_REG(base) = (value))
+#define LLWU_RMW_ME(base, mask, value) (LLWU_WR_ME(base, (LLWU_RD_ME(base) & ~(mask)) | (value)))
+#define LLWU_SET_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) |  (value)))
+#define LLWU_CLR_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) & ~(value)))
+#define LLWU_TOG_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_ME bitfields
+ */
+
+/*!
+ * @name Register LLWU_ME, field WUME0[0] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME0 field. */
+#define LLWU_RD_ME_WUME0(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME0_MASK) >> LLWU_ME_WUME0_SHIFT)
+#define LLWU_BRD_ME_WUME0(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT))
+
+/*! @brief Set the WUME0 field to a new value. */
+#define LLWU_WR_ME_WUME0(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME0_MASK, LLWU_ME_WUME0(value)))
+#define LLWU_BWR_ME_WUME0(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME1[1] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME1 field. */
+#define LLWU_RD_ME_WUME1(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME1_MASK) >> LLWU_ME_WUME1_SHIFT)
+#define LLWU_BRD_ME_WUME1(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT))
+
+/*! @brief Set the WUME1 field to a new value. */
+#define LLWU_WR_ME_WUME1(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME1_MASK, LLWU_ME_WUME1(value)))
+#define LLWU_BWR_ME_WUME1(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME2[2] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME2 field. */
+#define LLWU_RD_ME_WUME2(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME2_MASK) >> LLWU_ME_WUME2_SHIFT)
+#define LLWU_BRD_ME_WUME2(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT))
+
+/*! @brief Set the WUME2 field to a new value. */
+#define LLWU_WR_ME_WUME2(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME2_MASK, LLWU_ME_WUME2(value)))
+#define LLWU_BWR_ME_WUME2(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME3[3] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME3 field. */
+#define LLWU_RD_ME_WUME3(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME3_MASK) >> LLWU_ME_WUME3_SHIFT)
+#define LLWU_BRD_ME_WUME3(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT))
+
+/*! @brief Set the WUME3 field to a new value. */
+#define LLWU_WR_ME_WUME3(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME3_MASK, LLWU_ME_WUME3(value)))
+#define LLWU_BWR_ME_WUME3(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME4[4] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME4 field. */
+#define LLWU_RD_ME_WUME4(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME4_MASK) >> LLWU_ME_WUME4_SHIFT)
+#define LLWU_BRD_ME_WUME4(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT))
+
+/*! @brief Set the WUME4 field to a new value. */
+#define LLWU_WR_ME_WUME4(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME4_MASK, LLWU_ME_WUME4(value)))
+#define LLWU_BWR_ME_WUME4(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME5[5] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME5 field. */
+#define LLWU_RD_ME_WUME5(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME5_MASK) >> LLWU_ME_WUME5_SHIFT)
+#define LLWU_BRD_ME_WUME5(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT))
+
+/*! @brief Set the WUME5 field to a new value. */
+#define LLWU_WR_ME_WUME5(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME5_MASK, LLWU_ME_WUME5(value)))
+#define LLWU_BWR_ME_WUME5(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME6[6] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME6 field. */
+#define LLWU_RD_ME_WUME6(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME6_MASK) >> LLWU_ME_WUME6_SHIFT)
+#define LLWU_BRD_ME_WUME6(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT))
+
+/*! @brief Set the WUME6 field to a new value. */
+#define LLWU_WR_ME_WUME6(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME6_MASK, LLWU_ME_WUME6(value)))
+#define LLWU_BWR_ME_WUME6(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME7[7] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME7 field. */
+#define LLWU_RD_ME_WUME7(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME7_MASK) >> LLWU_ME_WUME7_SHIFT)
+#define LLWU_BRD_ME_WUME7(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT))
+
+/*! @brief Set the WUME7 field to a new value. */
+#define LLWU_WR_ME_WUME7(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME7_MASK, LLWU_ME_WUME7(value)))
+#define LLWU_BWR_ME_WUME7(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F1 - LLWU Flag 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F1 - LLWU Flag 1 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F1 register
+ */
+/*@{*/
+#define LLWU_RD_F1(base)         (LLWU_F1_REG(base))
+#define LLWU_WR_F1(base, value)  (LLWU_F1_REG(base) = (value))
+#define LLWU_RMW_F1(base, mask, value) (LLWU_WR_F1(base, (LLWU_RD_F1(base) & ~(mask)) | (value)))
+#define LLWU_SET_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) |  (value)))
+#define LLWU_CLR_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) & ~(value)))
+#define LLWU_TOG_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F1, field WUF0[0] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF0.
+ *
+ * Values:
+ * - 0b0 - LLWU_P0 input was not a wakeup source
+ * - 0b1 - LLWU_P0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF0 field. */
+#define LLWU_RD_F1_WUF0(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF0_MASK) >> LLWU_F1_WUF0_SHIFT)
+#define LLWU_BRD_F1_WUF0(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT))
+
+/*! @brief Set the WUF0 field to a new value. */
+#define LLWU_WR_F1_WUF0(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF0(value)))
+#define LLWU_BWR_F1_WUF0(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF1[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF1.
+ *
+ * Values:
+ * - 0b0 - LLWU_P1 input was not a wakeup source
+ * - 0b1 - LLWU_P1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF1 field. */
+#define LLWU_RD_F1_WUF1(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF1_MASK) >> LLWU_F1_WUF1_SHIFT)
+#define LLWU_BRD_F1_WUF1(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT))
+
+/*! @brief Set the WUF1 field to a new value. */
+#define LLWU_WR_F1_WUF1(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF1_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF1(value)))
+#define LLWU_BWR_F1_WUF1(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF2[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF2.
+ *
+ * Values:
+ * - 0b0 - LLWU_P2 input was not a wakeup source
+ * - 0b1 - LLWU_P2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF2 field. */
+#define LLWU_RD_F1_WUF2(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF2_MASK) >> LLWU_F1_WUF2_SHIFT)
+#define LLWU_BRD_F1_WUF2(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT))
+
+/*! @brief Set the WUF2 field to a new value. */
+#define LLWU_WR_F1_WUF2(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF2_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF2(value)))
+#define LLWU_BWR_F1_WUF2(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF3[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF3.
+ *
+ * Values:
+ * - 0b0 - LLWU_P3 input was not a wake-up source
+ * - 0b1 - LLWU_P3 input was a wake-up source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF3 field. */
+#define LLWU_RD_F1_WUF3(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF3_MASK) >> LLWU_F1_WUF3_SHIFT)
+#define LLWU_BRD_F1_WUF3(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT))
+
+/*! @brief Set the WUF3 field to a new value. */
+#define LLWU_WR_F1_WUF3(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF3_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF3(value)))
+#define LLWU_BWR_F1_WUF3(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF4[4] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF4.
+ *
+ * Values:
+ * - 0b0 - LLWU_P4 input was not a wakeup source
+ * - 0b1 - LLWU_P4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF4 field. */
+#define LLWU_RD_F1_WUF4(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF4_MASK) >> LLWU_F1_WUF4_SHIFT)
+#define LLWU_BRD_F1_WUF4(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT))
+
+/*! @brief Set the WUF4 field to a new value. */
+#define LLWU_WR_F1_WUF4(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF4_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF4(value)))
+#define LLWU_BWR_F1_WUF4(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF5[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF5.
+ *
+ * Values:
+ * - 0b0 - LLWU_P5 input was not a wakeup source
+ * - 0b1 - LLWU_P5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF5 field. */
+#define LLWU_RD_F1_WUF5(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF5_MASK) >> LLWU_F1_WUF5_SHIFT)
+#define LLWU_BRD_F1_WUF5(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT))
+
+/*! @brief Set the WUF5 field to a new value. */
+#define LLWU_WR_F1_WUF5(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF5_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF5(value)))
+#define LLWU_BWR_F1_WUF5(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF6[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF6.
+ *
+ * Values:
+ * - 0b0 - LLWU_P6 input was not a wakeup source
+ * - 0b1 - LLWU_P6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF6 field. */
+#define LLWU_RD_F1_WUF6(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF6_MASK) >> LLWU_F1_WUF6_SHIFT)
+#define LLWU_BRD_F1_WUF6(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT))
+
+/*! @brief Set the WUF6 field to a new value. */
+#define LLWU_WR_F1_WUF6(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF6_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF6(value)))
+#define LLWU_BWR_F1_WUF6(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF7[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF7.
+ *
+ * Values:
+ * - 0b0 - LLWU_P7 input was not a wakeup source
+ * - 0b1 - LLWU_P7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF7 field. */
+#define LLWU_RD_F1_WUF7(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF7_MASK) >> LLWU_F1_WUF7_SHIFT)
+#define LLWU_BRD_F1_WUF7(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT))
+
+/*! @brief Set the WUF7 field to a new value. */
+#define LLWU_WR_F1_WUF7(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF7_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK), LLWU_F1_WUF7(value)))
+#define LLWU_BWR_F1_WUF7(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F2 - LLWU Flag 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F2 - LLWU Flag 2 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F2 register
+ */
+/*@{*/
+#define LLWU_RD_F2(base)         (LLWU_F2_REG(base))
+#define LLWU_WR_F2(base, value)  (LLWU_F2_REG(base) = (value))
+#define LLWU_RMW_F2(base, mask, value) (LLWU_WR_F2(base, (LLWU_RD_F2(base) & ~(mask)) | (value)))
+#define LLWU_SET_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) |  (value)))
+#define LLWU_CLR_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) & ~(value)))
+#define LLWU_TOG_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F2, field WUF8[0] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF8.
+ *
+ * Values:
+ * - 0b0 - LLWU_P8 input was not a wakeup source
+ * - 0b1 - LLWU_P8 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF8 field. */
+#define LLWU_RD_F2_WUF8(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF8_MASK) >> LLWU_F2_WUF8_SHIFT)
+#define LLWU_BRD_F2_WUF8(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT))
+
+/*! @brief Set the WUF8 field to a new value. */
+#define LLWU_WR_F2_WUF8(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF8(value)))
+#define LLWU_BWR_F2_WUF8(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF9[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF9.
+ *
+ * Values:
+ * - 0b0 - LLWU_P9 input was not a wakeup source
+ * - 0b1 - LLWU_P9 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF9 field. */
+#define LLWU_RD_F2_WUF9(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF9_MASK) >> LLWU_F2_WUF9_SHIFT)
+#define LLWU_BRD_F2_WUF9(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT))
+
+/*! @brief Set the WUF9 field to a new value. */
+#define LLWU_WR_F2_WUF9(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF9_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF9(value)))
+#define LLWU_BWR_F2_WUF9(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF10[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF10.
+ *
+ * Values:
+ * - 0b0 - LLWU_P10 input was not a wakeup source
+ * - 0b1 - LLWU_P10 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF10 field. */
+#define LLWU_RD_F2_WUF10(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF10_MASK) >> LLWU_F2_WUF10_SHIFT)
+#define LLWU_BRD_F2_WUF10(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT))
+
+/*! @brief Set the WUF10 field to a new value. */
+#define LLWU_WR_F2_WUF10(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF10_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF10(value)))
+#define LLWU_BWR_F2_WUF10(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF11[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF11.
+ *
+ * Values:
+ * - 0b0 - LLWU_P11 input was not a wakeup source
+ * - 0b1 - LLWU_P11 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF11 field. */
+#define LLWU_RD_F2_WUF11(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF11_MASK) >> LLWU_F2_WUF11_SHIFT)
+#define LLWU_BRD_F2_WUF11(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT))
+
+/*! @brief Set the WUF11 field to a new value. */
+#define LLWU_WR_F2_WUF11(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF11_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF11(value)))
+#define LLWU_BWR_F2_WUF11(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF12[4] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF12.
+ *
+ * Values:
+ * - 0b0 - LLWU_P12 input was not a wakeup source
+ * - 0b1 - LLWU_P12 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF12 field. */
+#define LLWU_RD_F2_WUF12(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF12_MASK) >> LLWU_F2_WUF12_SHIFT)
+#define LLWU_BRD_F2_WUF12(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT))
+
+/*! @brief Set the WUF12 field to a new value. */
+#define LLWU_WR_F2_WUF12(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF12_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF12(value)))
+#define LLWU_BWR_F2_WUF12(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF13[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF13.
+ *
+ * Values:
+ * - 0b0 - LLWU_P13 input was not a wakeup source
+ * - 0b1 - LLWU_P13 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF13 field. */
+#define LLWU_RD_F2_WUF13(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF13_MASK) >> LLWU_F2_WUF13_SHIFT)
+#define LLWU_BRD_F2_WUF13(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT))
+
+/*! @brief Set the WUF13 field to a new value. */
+#define LLWU_WR_F2_WUF13(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF13_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF13(value)))
+#define LLWU_BWR_F2_WUF13(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF14[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF14.
+ *
+ * Values:
+ * - 0b0 - LLWU_P14 input was not a wakeup source
+ * - 0b1 - LLWU_P14 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF14 field. */
+#define LLWU_RD_F2_WUF14(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF14_MASK) >> LLWU_F2_WUF14_SHIFT)
+#define LLWU_BRD_F2_WUF14(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT))
+
+/*! @brief Set the WUF14 field to a new value. */
+#define LLWU_WR_F2_WUF14(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF14_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF14(value)))
+#define LLWU_BWR_F2_WUF14(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF15[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF15.
+ *
+ * Values:
+ * - 0b0 - LLWU_P15 input was not a wakeup source
+ * - 0b1 - LLWU_P15 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF15 field. */
+#define LLWU_RD_F2_WUF15(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF15_MASK) >> LLWU_F2_WUF15_SHIFT)
+#define LLWU_BRD_F2_WUF15(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT))
+
+/*! @brief Set the WUF15 field to a new value. */
+#define LLWU_WR_F2_WUF15(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF15_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK), LLWU_F2_WUF15(value)))
+#define LLWU_BWR_F2_WUF15(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F3 - LLWU Flag 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F3 - LLWU Flag 3 register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
+ * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
+ * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
+ * For internal peripherals that are capable of running in a low-leakage power
+ * mode, such as a real time clock module or CMP module, the flag from the
+ * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
+ * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
+ * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
+ * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
+ * the IntroductionInformation found here describes the registers of the Reset
+ * Control Module (RCM). The RCM implements many of the reset functions for the
+ * chip. See the chip's reset chapter for more information. details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F3 register
+ */
+/*@{*/
+#define LLWU_RD_F3(base)         (LLWU_F3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F3, field MWUF0[0] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 0 input was not a wakeup source
+ * - 0b1 - Module 0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF0 field. */
+#define LLWU_RD_F3_MWUF0(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF0_MASK) >> LLWU_F3_MWUF0_SHIFT)
+#define LLWU_BRD_F3_MWUF0(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF1[1] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 1 input was not a wakeup source
+ * - 0b1 - Module 1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF1 field. */
+#define LLWU_RD_F3_MWUF1(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF1_MASK) >> LLWU_F3_MWUF1_SHIFT)
+#define LLWU_BRD_F3_MWUF1(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF2[2] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 2 input was not a wakeup source
+ * - 0b1 - Module 2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF2 field. */
+#define LLWU_RD_F3_MWUF2(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF2_MASK) >> LLWU_F3_MWUF2_SHIFT)
+#define LLWU_BRD_F3_MWUF2(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF2_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF3[3] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 3 input was not a wakeup source
+ * - 0b1 - Module 3 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF3 field. */
+#define LLWU_RD_F3_MWUF3(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF3_MASK) >> LLWU_F3_MWUF3_SHIFT)
+#define LLWU_BRD_F3_MWUF3(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF3_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF4[4] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 4 input was not a wakeup source
+ * - 0b1 - Module 4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF4 field. */
+#define LLWU_RD_F3_MWUF4(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF4_MASK) >> LLWU_F3_MWUF4_SHIFT)
+#define LLWU_BRD_F3_MWUF4(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF4_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF5[5] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 5 input was not a wakeup source
+ * - 0b1 - Module 5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF5 field. */
+#define LLWU_RD_F3_MWUF5(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF5_MASK) >> LLWU_F3_MWUF5_SHIFT)
+#define LLWU_BRD_F3_MWUF5(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF5_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF6[6] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 6 input was not a wakeup source
+ * - 0b1 - Module 6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF6 field. */
+#define LLWU_RD_F3_MWUF6(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF6_MASK) >> LLWU_F3_MWUF6_SHIFT)
+#define LLWU_BRD_F3_MWUF6(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF6_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF7[7] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 7 input was not a wakeup source
+ * - 0b1 - Module 7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF7 field. */
+#define LLWU_RD_F3_MWUF7(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF7_MASK) >> LLWU_F3_MWUF7_SHIFT)
+#define LLWU_BRD_F3_MWUF7(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF7_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT1 - LLWU Pin Filter 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT1 is a control and status register that is used to enable/disable
+ * the digital filter 1 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT1 register
+ */
+/*@{*/
+#define LLWU_RD_FILT1(base)      (LLWU_FILT1_REG(base))
+#define LLWU_WR_FILT1(base, value) (LLWU_FILT1_REG(base) = (value))
+#define LLWU_RMW_FILT1(base, mask, value) (LLWU_WR_FILT1(base, (LLWU_RD_FILT1(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) |  (value)))
+#define LLWU_CLR_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) & ~(value)))
+#define LLWU_TOG_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0b0000 - Select LLWU_P0 for filter
+ * - 0b1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
+#define LLWU_RD_FILT1_FILTSEL(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTSEL_MASK) >> LLWU_FILT1_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT1_FILTSEL(base) (LLWU_RD_FILT1_FILTSEL(base))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT1_FILTSEL(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTSEL(value)))
+#define LLWU_BWR_FILT1_FILTSEL(base, value) (LLWU_WR_FILT1_FILTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 0b00 - Filter disabled
+ * - 0b01 - Filter posedge detect enabled
+ * - 0b10 - Filter negedge detect enabled
+ * - 0b11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTE field. */
+#define LLWU_RD_FILT1_FILTE(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTE_MASK) >> LLWU_FILT1_FILTE_SHIFT)
+#define LLWU_BRD_FILT1_FILTE(base) (LLWU_RD_FILT1_FILTE(base))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT1_FILTE(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTE_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTE(value)))
+#define LLWU_BWR_FILT1_FILTE(base, value) (LLWU_WR_FILT1_FILTE(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0b0 - Pin Filter 1 was not a wakeup source
+ * - 0b1 - Pin Filter 1 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTF field. */
+#define LLWU_RD_FILT1_FILTF(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTF_MASK) >> LLWU_FILT1_FILTF_SHIFT)
+#define LLWU_BRD_FILT1_FILTF(base) (BITBAND_ACCESS8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT1_FILTF(base, value) (LLWU_RMW_FILT1(base, LLWU_FILT1_FILTF_MASK, LLWU_FILT1_FILTF(value)))
+#define LLWU_BWR_FILT1_FILTF(base, value) (BITBAND_ACCESS8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT2 - LLWU Pin Filter 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT2 is a control and status register that is used to enable/disable
+ * the digital filter 2 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT2 register
+ */
+/*@{*/
+#define LLWU_RD_FILT2(base)      (LLWU_FILT2_REG(base))
+#define LLWU_WR_FILT2(base, value) (LLWU_FILT2_REG(base) = (value))
+#define LLWU_RMW_FILT2(base, mask, value) (LLWU_WR_FILT2(base, (LLWU_RD_FILT2(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) |  (value)))
+#define LLWU_CLR_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) & ~(value)))
+#define LLWU_TOG_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0b0000 - Select LLWU_P0 for filter
+ * - 0b1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
+#define LLWU_RD_FILT2_FILTSEL(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTSEL_MASK) >> LLWU_FILT2_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT2_FILTSEL(base) (LLWU_RD_FILT2_FILTSEL(base))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT2_FILTSEL(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTSEL_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTSEL(value)))
+#define LLWU_BWR_FILT2_FILTSEL(base, value) (LLWU_WR_FILT2_FILTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 0b00 - Filter disabled
+ * - 0b01 - Filter posedge detect enabled
+ * - 0b10 - Filter negedge detect enabled
+ * - 0b11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTE field. */
+#define LLWU_RD_FILT2_FILTE(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTE_MASK) >> LLWU_FILT2_FILTE_SHIFT)
+#define LLWU_BRD_FILT2_FILTE(base) (LLWU_RD_FILT2_FILTE(base))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT2_FILTE(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTE_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTE(value)))
+#define LLWU_BWR_FILT2_FILTE(base, value) (LLWU_WR_FILT2_FILTE(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0b0 - Pin Filter 2 was not a wakeup source
+ * - 0b1 - Pin Filter 2 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTF field. */
+#define LLWU_RD_FILT2_FILTF(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTF_MASK) >> LLWU_FILT2_FILTF_SHIFT)
+#define LLWU_BRD_FILT2_FILTF(base) (BITBAND_ACCESS8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT2_FILTF(base, value) (LLWU_RMW_FILT2(base, LLWU_FILT2_FILTF_MASK, LLWU_FILT2_FILTF(value)))
+#define LLWU_BWR_FILT2_FILTF(base, value) (BITBAND_ACCESS8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_RST - LLWU Reset Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_RST - LLWU Reset Enable register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * LLWU_RST is a control register that is used to enable/disable the digital
+ * filter for the external pin detect and RESET pin. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_RST register
+ */
+/*@{*/
+#define LLWU_RD_RST(base)        (LLWU_RST_REG(base))
+#define LLWU_WR_RST(base, value) (LLWU_RST_REG(base) = (value))
+#define LLWU_RMW_RST(base, mask, value) (LLWU_WR_RST(base, (LLWU_RD_RST(base) & ~(mask)) | (value)))
+#define LLWU_SET_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) |  (value)))
+#define LLWU_CLR_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) & ~(value)))
+#define LLWU_TOG_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_RST bitfields
+ */
+
+/*!
+ * @name Register LLWU_RST, field RSTFILT[0] (RW)
+ *
+ * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
+ * VLLS1 modes.
+ *
+ * Values:
+ * - 0b0 - Filter not enabled
+ * - 0b1 - Filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_RST_RSTFILT field. */
+#define LLWU_RD_RST_RSTFILT(base) ((LLWU_RST_REG(base) & LLWU_RST_RSTFILT_MASK) >> LLWU_RST_RSTFILT_SHIFT)
+#define LLWU_BRD_RST_RSTFILT(base) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_RSTFILT_SHIFT))
+
+/*! @brief Set the RSTFILT field to a new value. */
+#define LLWU_WR_RST_RSTFILT(base, value) (LLWU_RMW_RST(base, LLWU_RST_RSTFILT_MASK, LLWU_RST_RSTFILT(value)))
+#define LLWU_BWR_RST_RSTFILT(base, value) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_RSTFILT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_RST, field LLRSTE[1] (RW)
+ *
+ * This bit must be set to allow the device to be reset while in a low-leakage
+ * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
+ * also be enabled in the explicit port mux control.
+ *
+ * Values:
+ * - 0b0 - RESET pin not enabled as a leakage mode exit source
+ * - 0b1 - RESET pin enabled as a low leakage mode exit source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_RST_LLRSTE field. */
+#define LLWU_RD_RST_LLRSTE(base) ((LLWU_RST_REG(base) & LLWU_RST_LLRSTE_MASK) >> LLWU_RST_LLRSTE_SHIFT)
+#define LLWU_BRD_RST_LLRSTE(base) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_LLRSTE_SHIFT))
+
+/*! @brief Set the LLRSTE field to a new value. */
+#define LLWU_WR_RST_LLRSTE(base, value) (LLWU_RMW_RST(base, LLWU_RST_LLRSTE_MASK, LLWU_RST_LLRSTE(value)))
+#define LLWU_BWR_RST_LLRSTE(base, value) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_LLRSTE_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 LPTMR
+ *
+ * Low Power Timer
+ *
+ * Registers defined in this header file:
+ * - LPTMR_CSR - Low Power Timer Control Status Register
+ * - LPTMR_PSR - Low Power Timer Prescale Register
+ * - LPTMR_CMR - Low Power Timer Compare Register
+ * - LPTMR_CNR - Low Power Timer Counter Register
+ */
+
+#define LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
+#define LPTMR0_IDX (0U) /*!< Instance number for LPTMR0. */
+
+/*******************************************************************************
+ * LPTMR_CSR - Low Power Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CSR - Low Power Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CSR register
+ */
+/*@{*/
+#define LPTMR_RD_CSR(base)       (LPTMR_CSR_REG(base))
+#define LPTMR_WR_CSR(base, value) (LPTMR_CSR_REG(base) = (value))
+#define LPTMR_RMW_CSR(base, mask, value) (LPTMR_WR_CSR(base, (LPTMR_RD_CSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) |  (value)))
+#define LPTMR_CLR_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) & ~(value)))
+#define LPTMR_TOG_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CSR, field TEN[0] (RW)
+ *
+ * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
+ * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
+ * CSR[5:1] must not be altered.
+ *
+ * Values:
+ * - 0b0 - LPTMR is disabled and internal logic is reset.
+ * - 0b1 - LPTMR is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TEN field. */
+#define LPTMR_RD_CSR_TEN(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TEN_MASK) >> LPTMR_CSR_TEN_SHIFT)
+#define LPTMR_BRD_CSR_TEN(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT))
+
+/*! @brief Set the TEN field to a new value. */
+#define LPTMR_WR_CSR_TEN(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TEN_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TEN(value)))
+#define LPTMR_BWR_CSR_TEN(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TMS[1] (RW)
+ *
+ * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
+ * disabled.
+ *
+ * Values:
+ * - 0b0 - Time Counter mode.
+ * - 0b1 - Pulse Counter mode.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TMS field. */
+#define LPTMR_RD_CSR_TMS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TMS_MASK) >> LPTMR_CSR_TMS_SHIFT)
+#define LPTMR_BRD_CSR_TMS(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT))
+
+/*! @brief Set the TMS field to a new value. */
+#define LPTMR_WR_CSR_TMS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TMS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TMS(value)))
+#define LPTMR_BWR_CSR_TMS(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TFC[2] (RW)
+ *
+ * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
+ * TFC configures the CNR to reset on overflow. TFC must be altered only when the
+ * LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - CNR is reset whenever TCF is set.
+ * - 0b1 - CNR is reset on overflow.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TFC field. */
+#define LPTMR_RD_CSR_TFC(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TFC_MASK) >> LPTMR_CSR_TFC_SHIFT)
+#define LPTMR_BRD_CSR_TFC(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT))
+
+/*! @brief Set the TFC field to a new value. */
+#define LPTMR_WR_CSR_TFC(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TFC_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TFC(value)))
+#define LPTMR_BWR_CSR_TFC(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPP[3] (RW)
+ *
+ * Configures the polarity of the input source in Pulse Counter mode. TPP must
+ * be changed only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - Pulse Counter input source is active-high, and the CNR will increment
+ *     on the rising-edge.
+ * - 0b1 - Pulse Counter input source is active-low, and the CNR will increment
+ *     on the falling-edge.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPP field. */
+#define LPTMR_RD_CSR_TPP(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPP_MASK) >> LPTMR_CSR_TPP_SHIFT)
+#define LPTMR_BRD_CSR_TPP(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT))
+
+/*! @brief Set the TPP field to a new value. */
+#define LPTMR_WR_CSR_TPP(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPP_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPP(value)))
+#define LPTMR_BWR_CSR_TPP(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPS[5:4] (RW)
+ *
+ * Configures the input source to be used in Pulse Counter mode. TPS must be
+ * altered only when the LPTMR is disabled. The input connections vary by device.
+ * See the chip configuration details for information on the connections to these
+ * inputs.
+ *
+ * Values:
+ * - 0b00 - Pulse counter input 0 is selected.
+ * - 0b01 - Pulse counter input 1 is selected.
+ * - 0b10 - Pulse counter input 2 is selected.
+ * - 0b11 - Pulse counter input 3 is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPS field. */
+#define LPTMR_RD_CSR_TPS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPS_MASK) >> LPTMR_CSR_TPS_SHIFT)
+#define LPTMR_BRD_CSR_TPS(base) (LPTMR_RD_CSR_TPS(base))
+
+/*! @brief Set the TPS field to a new value. */
+#define LPTMR_WR_CSR_TPS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPS(value)))
+#define LPTMR_BWR_CSR_TPS(base, value) (LPTMR_WR_CSR_TPS(base, value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TIE[6] (RW)
+ *
+ * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
+ *
+ * Values:
+ * - 0b0 - Timer interrupt disabled.
+ * - 0b1 - Timer interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TIE field. */
+#define LPTMR_RD_CSR_TIE(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TIE_MASK) >> LPTMR_CSR_TIE_SHIFT)
+#define LPTMR_BRD_CSR_TIE(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define LPTMR_WR_CSR_TIE(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TIE_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TIE(value)))
+#define LPTMR_BWR_CSR_TIE(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TCF[7] (W1C)
+ *
+ * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
+ * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
+ *
+ * Values:
+ * - 0b0 - The value of CNR is not equal to CMR and increments.
+ * - 0b1 - The value of CNR is equal to CMR and increments.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TCF field. */
+#define LPTMR_RD_CSR_TCF(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TCF_MASK) >> LPTMR_CSR_TCF_SHIFT)
+#define LPTMR_BRD_CSR_TCF(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT))
+
+/*! @brief Set the TCF field to a new value. */
+#define LPTMR_WR_CSR_TCF(base, value) (LPTMR_RMW_CSR(base, LPTMR_CSR_TCF_MASK, LPTMR_CSR_TCF(value)))
+#define LPTMR_BWR_CSR_TCF(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_PSR - Low Power Timer Prescale Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_PSR - Low Power Timer Prescale Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_PSR register
+ */
+/*@{*/
+#define LPTMR_RD_PSR(base)       (LPTMR_PSR_REG(base))
+#define LPTMR_WR_PSR(base, value) (LPTMR_PSR_REG(base) = (value))
+#define LPTMR_RMW_PSR(base, mask, value) (LPTMR_WR_PSR(base, (LPTMR_RD_PSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) |  (value)))
+#define LPTMR_CLR_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) & ~(value)))
+#define LPTMR_TOG_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_PSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_PSR, field PCS[1:0] (RW)
+ *
+ * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
+ * be altered only when the LPTMR is disabled. The clock connections vary by
+ * device. See the chip configuration details for information on the connections to
+ * these inputs.
+ *
+ * Values:
+ * - 0b00 - Prescaler/glitch filter clock 0 selected.
+ * - 0b01 - Prescaler/glitch filter clock 1 selected.
+ * - 0b10 - Prescaler/glitch filter clock 2 selected.
+ * - 0b11 - Prescaler/glitch filter clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PCS field. */
+#define LPTMR_RD_PSR_PCS(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PCS_MASK) >> LPTMR_PSR_PCS_SHIFT)
+#define LPTMR_BRD_PSR_PCS(base) (LPTMR_RD_PSR_PCS(base))
+
+/*! @brief Set the PCS field to a new value. */
+#define LPTMR_WR_PSR_PCS(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PCS_MASK, LPTMR_PSR_PCS(value)))
+#define LPTMR_BWR_PSR_PCS(base, value) (LPTMR_WR_PSR_PCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PBYP[2] (RW)
+ *
+ * When PBYP is set, the selected prescaler clock in Time Counter mode or
+ * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
+ * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
+ * must be altered only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - Prescaler/glitch filter is enabled.
+ * - 0b1 - Prescaler/glitch filter is bypassed.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PBYP field. */
+#define LPTMR_RD_PSR_PBYP(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PBYP_MASK) >> LPTMR_PSR_PBYP_SHIFT)
+#define LPTMR_BRD_PSR_PBYP(base) (BITBAND_ACCESS32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT))
+
+/*! @brief Set the PBYP field to a new value. */
+#define LPTMR_WR_PSR_PBYP(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PBYP_MASK, LPTMR_PSR_PBYP(value)))
+#define LPTMR_BWR_PSR_PBYP(base, value) (BITBAND_ACCESS32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
+ *
+ * Configures the size of the Prescaler in Time Counter mode or width of the
+ * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
+ * is disabled.
+ *
+ * Values:
+ * - 0b0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
+ *     support this configuration.
+ * - 0b0001 - Prescaler divides the prescaler clock by 4; glitch filter
+ *     recognizes change on input pin after 2 rising clock edges.
+ * - 0b0010 - Prescaler divides the prescaler clock by 8; glitch filter
+ *     recognizes change on input pin after 4 rising clock edges.
+ * - 0b0011 - Prescaler divides the prescaler clock by 16; glitch filter
+ *     recognizes change on input pin after 8 rising clock edges.
+ * - 0b0100 - Prescaler divides the prescaler clock by 32; glitch filter
+ *     recognizes change on input pin after 16 rising clock edges.
+ * - 0b0101 - Prescaler divides the prescaler clock by 64; glitch filter
+ *     recognizes change on input pin after 32 rising clock edges.
+ * - 0b0110 - Prescaler divides the prescaler clock by 128; glitch filter
+ *     recognizes change on input pin after 64 rising clock edges.
+ * - 0b0111 - Prescaler divides the prescaler clock by 256; glitch filter
+ *     recognizes change on input pin after 128 rising clock edges.
+ * - 0b1000 - Prescaler divides the prescaler clock by 512; glitch filter
+ *     recognizes change on input pin after 256 rising clock edges.
+ * - 0b1001 - Prescaler divides the prescaler clock by 1024; glitch filter
+ *     recognizes change on input pin after 512 rising clock edges.
+ * - 0b1010 - Prescaler divides the prescaler clock by 2048; glitch filter
+ *     recognizes change on input pin after 1024 rising clock edges.
+ * - 0b1011 - Prescaler divides the prescaler clock by 4096; glitch filter
+ *     recognizes change on input pin after 2048 rising clock edges.
+ * - 0b1100 - Prescaler divides the prescaler clock by 8192; glitch filter
+ *     recognizes change on input pin after 4096 rising clock edges.
+ * - 0b1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
+ *     recognizes change on input pin after 8192 rising clock edges.
+ * - 0b1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
+ *     recognizes change on input pin after 16,384 rising clock edges.
+ * - 0b1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
+ *     recognizes change on input pin after 32,768 rising clock edges.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
+#define LPTMR_RD_PSR_PRESCALE(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PRESCALE_MASK) >> LPTMR_PSR_PRESCALE_SHIFT)
+#define LPTMR_BRD_PSR_PRESCALE(base) (LPTMR_RD_PSR_PRESCALE(base))
+
+/*! @brief Set the PRESCALE field to a new value. */
+#define LPTMR_WR_PSR_PRESCALE(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PRESCALE_MASK, LPTMR_PSR_PRESCALE(value)))
+#define LPTMR_BWR_PSR_PRESCALE(base, value) (LPTMR_WR_PSR_PRESCALE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CMR - Low Power Timer Compare Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CMR - Low Power Timer Compare Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CMR register
+ */
+/*@{*/
+#define LPTMR_RD_CMR(base)       (LPTMR_CMR_REG(base))
+#define LPTMR_WR_CMR(base, value) (LPTMR_CMR_REG(base) = (value))
+#define LPTMR_RMW_CMR(base, mask, value) (LPTMR_WR_CMR(base, (LPTMR_RD_CMR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) |  (value)))
+#define LPTMR_CLR_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) & ~(value)))
+#define LPTMR_TOG_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CMR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
+ *
+ * When the LPTMR is enabled and the CNR equals the value in the CMR and
+ * increments, TCF is set and the hardware trigger asserts until the next time the CNR
+ * increments. If the CMR is 0, the hardware trigger will remain asserted until
+ * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
+ * when TCF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
+#define LPTMR_RD_CMR_COMPARE(base) ((LPTMR_CMR_REG(base) & LPTMR_CMR_COMPARE_MASK) >> LPTMR_CMR_COMPARE_SHIFT)
+#define LPTMR_BRD_CMR_COMPARE(base) (LPTMR_RD_CMR_COMPARE(base))
+
+/*! @brief Set the COMPARE field to a new value. */
+#define LPTMR_WR_CMR_COMPARE(base, value) (LPTMR_RMW_CMR(base, LPTMR_CMR_COMPARE_MASK, LPTMR_CMR_COMPARE(value)))
+#define LPTMR_BWR_CMR_COMPARE(base, value) (LPTMR_WR_CMR_COMPARE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CNR - Low Power Timer Counter Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CNR - Low Power Timer Counter Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CNR register
+ */
+/*@{*/
+#define LPTMR_RD_CNR(base)       (LPTMR_CNR_REG(base))
+#define LPTMR_WR_CNR(base, value) (LPTMR_CNR_REG(base) = (value))
+#define LPTMR_RMW_CNR(base, mask, value) (LPTMR_WR_CNR(base, (LPTMR_RD_CNR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) |  (value)))
+#define LPTMR_CLR_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) & ~(value)))
+#define LPTMR_TOG_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CNR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
+#define LPTMR_RD_CNR_COUNTER(base) ((LPTMR_CNR_REG(base) & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT)
+#define LPTMR_BRD_CNR_COUNTER(base) (LPTMR_RD_CNR_COUNTER(base))
+
+/*! @brief Set the COUNTER field to a new value. */
+#define LPTMR_WR_CNR_COUNTER(base, value) (LPTMR_RMW_CNR(base, LPTMR_CNR_COUNTER_MASK, LPTMR_CNR_COUNTER(value)))
+#define LPTMR_BWR_CNR_COUNTER(base, value) (LPTMR_WR_CNR_COUNTER(base, value))
+/*@}*/
+
+/*
+ * MK64F12 MCG
+ *
+ * Multipurpose Clock Generator module
+ *
+ * Registers defined in this header file:
+ * - MCG_C1 - MCG Control 1 Register
+ * - MCG_C2 - MCG Control 2 Register
+ * - MCG_C3 - MCG Control 3 Register
+ * - MCG_C4 - MCG Control 4 Register
+ * - MCG_C5 - MCG Control 5 Register
+ * - MCG_C6 - MCG Control 6 Register
+ * - MCG_S - MCG Status Register
+ * - MCG_SC - MCG Status and Control Register
+ * - MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ * - MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ * - MCG_C7 - MCG Control 7 Register
+ * - MCG_C8 - MCG Control 8 Register
+ */
+
+#define MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */
+#define MCG_IDX (0U) /*!< Instance number for MCG. */
+
+/*******************************************************************************
+ * MCG_C1 - MCG Control 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C1 - MCG Control 1 Register (RW)
+ *
+ * Reset value: 0x04U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C1 register
+ */
+/*@{*/
+#define MCG_RD_C1(base)          (MCG_C1_REG(base))
+#define MCG_WR_C1(base, value)   (MCG_C1_REG(base) = (value))
+#define MCG_RMW_C1(base, mask, value) (MCG_WR_C1(base, (MCG_RD_C1(base) & ~(mask)) | (value)))
+#define MCG_SET_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) |  (value)))
+#define MCG_CLR_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) & ~(value)))
+#define MCG_TOG_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C1 bitfields
+ */
+
+/*!
+ * @name Register MCG_C1, field IREFSTEN[0] (RW)
+ *
+ * Controls whether or not the internal reference clock remains enabled when the
+ * MCG enters Stop mode.
+ *
+ * Values:
+ * - 0b0 - Internal reference clock is disabled in Stop mode.
+ * - 0b1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
+ *     if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFSTEN field. */
+#define MCG_RD_C1_IREFSTEN(base) ((MCG_C1_REG(base) & MCG_C1_IREFSTEN_MASK) >> MCG_C1_IREFSTEN_SHIFT)
+#define MCG_BRD_C1_IREFSTEN(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT))
+
+/*! @brief Set the IREFSTEN field to a new value. */
+#define MCG_WR_C1_IREFSTEN(base, value) (MCG_RMW_C1(base, MCG_C1_IREFSTEN_MASK, MCG_C1_IREFSTEN(value)))
+#define MCG_BWR_C1_IREFSTEN(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IRCLKEN[1] (RW)
+ *
+ * Enables the internal reference clock for use as MCGIRCLK.
+ *
+ * Values:
+ * - 0b0 - MCGIRCLK inactive.
+ * - 0b1 - MCGIRCLK active.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IRCLKEN field. */
+#define MCG_RD_C1_IRCLKEN(base) ((MCG_C1_REG(base) & MCG_C1_IRCLKEN_MASK) >> MCG_C1_IRCLKEN_SHIFT)
+#define MCG_BRD_C1_IRCLKEN(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT))
+
+/*! @brief Set the IRCLKEN field to a new value. */
+#define MCG_WR_C1_IRCLKEN(base, value) (MCG_RMW_C1(base, MCG_C1_IRCLKEN_MASK, MCG_C1_IRCLKEN(value)))
+#define MCG_BWR_C1_IRCLKEN(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IREFS[2] (RW)
+ *
+ * Selects the reference clock source for the FLL.
+ *
+ * Values:
+ * - 0b0 - External reference clock is selected.
+ * - 0b1 - The slow internal reference clock is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFS field. */
+#define MCG_RD_C1_IREFS(base) ((MCG_C1_REG(base) & MCG_C1_IREFS_MASK) >> MCG_C1_IREFS_SHIFT)
+#define MCG_BRD_C1_IREFS(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT))
+
+/*! @brief Set the IREFS field to a new value. */
+#define MCG_WR_C1_IREFS(base, value) (MCG_RMW_C1(base, MCG_C1_IREFS_MASK, MCG_C1_IREFS(value)))
+#define MCG_BWR_C1_IREFS(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field FRDIV[5:3] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the FLL.
+ * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
+ * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
+ * not required to meet this range, but it is recommended in the cases when trying
+ * to enter a FLL mode from FBE).
+ *
+ * Values:
+ * - 0b000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
+ *     values, Divide Factor is 32.
+ * - 0b001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
+ *     values, Divide Factor is 64.
+ * - 0b010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
+ *     values, Divide Factor is 128.
+ * - 0b011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
+ *     values, Divide Factor is 256.
+ * - 0b100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
+ *     values, Divide Factor is 512.
+ * - 0b101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
+ *     values, Divide Factor is 1024.
+ * - 0b110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
+ *     values, Divide Factor is 1280 .
+ * - 0b111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other
+ *     RANGE values, Divide Factor is 1536 .
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_FRDIV field. */
+#define MCG_RD_C1_FRDIV(base) ((MCG_C1_REG(base) & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
+#define MCG_BRD_C1_FRDIV(base) (MCG_RD_C1_FRDIV(base))
+
+/*! @brief Set the FRDIV field to a new value. */
+#define MCG_WR_C1_FRDIV(base, value) (MCG_RMW_C1(base, MCG_C1_FRDIV_MASK, MCG_C1_FRDIV(value)))
+#define MCG_BWR_C1_FRDIV(base, value) (MCG_WR_C1_FRDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field CLKS[7:6] (RW)
+ *
+ * Selects the clock source for MCGOUTCLK .
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS
+ *     control bit).
+ * - 0b01 - Encoding 1 - Internal reference clock is selected.
+ * - 0b10 - Encoding 2 - External reference clock is selected.
+ * - 0b11 - Encoding 3 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_CLKS field. */
+#define MCG_RD_C1_CLKS(base) ((MCG_C1_REG(base) & MCG_C1_CLKS_MASK) >> MCG_C1_CLKS_SHIFT)
+#define MCG_BRD_C1_CLKS(base) (MCG_RD_C1_CLKS(base))
+
+/*! @brief Set the CLKS field to a new value. */
+#define MCG_WR_C1_CLKS(base, value) (MCG_RMW_C1(base, MCG_C1_CLKS_MASK, MCG_C1_CLKS(value)))
+#define MCG_BWR_C1_CLKS(base, value) (MCG_WR_C1_CLKS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C2 - MCG Control 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C2 - MCG Control 2 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C2 register
+ */
+/*@{*/
+#define MCG_RD_C2(base)          (MCG_C2_REG(base))
+#define MCG_WR_C2(base, value)   (MCG_C2_REG(base) = (value))
+#define MCG_RMW_C2(base, mask, value) (MCG_WR_C2(base, (MCG_RD_C2(base) & ~(mask)) | (value)))
+#define MCG_SET_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) |  (value)))
+#define MCG_CLR_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) & ~(value)))
+#define MCG_TOG_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C2 bitfields
+ */
+
+/*!
+ * @name Register MCG_C2, field IRCS[0] (RW)
+ *
+ * Selects between the fast or slow internal reference clock source.
+ *
+ * Values:
+ * - 0b0 - Slow internal reference clock selected.
+ * - 0b1 - Fast internal reference clock selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_IRCS field. */
+#define MCG_RD_C2_IRCS(base) ((MCG_C2_REG(base) & MCG_C2_IRCS_MASK) >> MCG_C2_IRCS_SHIFT)
+#define MCG_BRD_C2_IRCS(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT))
+
+/*! @brief Set the IRCS field to a new value. */
+#define MCG_WR_C2_IRCS(base, value) (MCG_RMW_C2(base, MCG_C2_IRCS_MASK, MCG_C2_IRCS(value)))
+#define MCG_BWR_C2_IRCS(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field LP[1] (RW)
+ *
+ * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
+ * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
+ * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
+ * other MCG mode, LP bit has no affect.
+ *
+ * Values:
+ * - 0b0 - FLL or PLL is not disabled in bypass modes.
+ * - 0b1 - FLL or PLL is disabled in bypass modes (lower power)
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_LP field. */
+#define MCG_RD_C2_LP(base)   ((MCG_C2_REG(base) & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
+#define MCG_BRD_C2_LP(base)  (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT))
+
+/*! @brief Set the LP field to a new value. */
+#define MCG_WR_C2_LP(base, value) (MCG_RMW_C2(base, MCG_C2_LP_MASK, MCG_C2_LP(value)))
+#define MCG_BWR_C2_LP(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field EREFS[2] (RW)
+ *
+ * Selects the source for the external reference clock. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0b0 - External reference clock requested.
+ * - 0b1 - Oscillator requested.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_EREFS field. */
+#define MCG_RD_C2_EREFS(base) ((MCG_C2_REG(base) & MCG_C2_EREFS_MASK) >> MCG_C2_EREFS_SHIFT)
+#define MCG_BRD_C2_EREFS(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT))
+
+/*! @brief Set the EREFS field to a new value. */
+#define MCG_WR_C2_EREFS(base, value) (MCG_RMW_C2(base, MCG_C2_EREFS_MASK, MCG_C2_EREFS(value)))
+#define MCG_BWR_C2_EREFS(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field HGO[3] (RW)
+ *
+ * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0b0 - Configure crystal oscillator for low-power operation.
+ * - 0b1 - Configure crystal oscillator for high-gain operation.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_HGO field. */
+#define MCG_RD_C2_HGO(base)  ((MCG_C2_REG(base) & MCG_C2_HGO_MASK) >> MCG_C2_HGO_SHIFT)
+#define MCG_BRD_C2_HGO(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT))
+
+/*! @brief Set the HGO field to a new value. */
+#define MCG_WR_C2_HGO(base, value) (MCG_RMW_C2(base, MCG_C2_HGO_MASK, MCG_C2_HGO(value)))
+#define MCG_BWR_C2_HGO(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field RANGE[5:4] (RW)
+ *
+ * Selects the frequency range for the crystal oscillator or external clock
+ * source. See the Oscillator (OSC) chapter for more details and the device data
+ * sheet for the frequency ranges used.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Low frequency range selected for the crystal oscillator
+ *     .
+ * - 0b01 - Encoding 1 - High frequency range selected for the crystal
+ *     oscillator .
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_RANGE field. */
+#define MCG_RD_C2_RANGE(base) ((MCG_C2_REG(base) & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
+#define MCG_BRD_C2_RANGE(base) (MCG_RD_C2_RANGE(base))
+
+/*! @brief Set the RANGE field to a new value. */
+#define MCG_WR_C2_RANGE(base, value) (MCG_RMW_C2(base, MCG_C2_RANGE_MASK, MCG_C2_RANGE(value)))
+#define MCG_BWR_C2_RANGE(base, value) (MCG_WR_C2_RANGE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field FCFTRIM[6] (RW)
+ *
+ * FCFTRIM controls the smallest adjustment of the fast internal reference clock
+ * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
+ * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_FCFTRIM field. */
+#define MCG_RD_C2_FCFTRIM(base) ((MCG_C2_REG(base) & MCG_C2_FCFTRIM_MASK) >> MCG_C2_FCFTRIM_SHIFT)
+#define MCG_BRD_C2_FCFTRIM(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT))
+
+/*! @brief Set the FCFTRIM field to a new value. */
+#define MCG_WR_C2_FCFTRIM(base, value) (MCG_RMW_C2(base, MCG_C2_FCFTRIM_MASK, MCG_C2_FCFTRIM(value)))
+#define MCG_BWR_C2_FCFTRIM(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field LOCRE0[7] (RW)
+ *
+ * Determines whether an interrupt or a reset request is made following a loss
+ * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
+ * set.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a loss of OSC0 external reference
+ *     clock.
+ * - 0b1 - Generate a reset request on a loss of OSC0 external reference clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_LOCRE0 field. */
+#define MCG_RD_C2_LOCRE0(base) ((MCG_C2_REG(base) & MCG_C2_LOCRE0_MASK) >> MCG_C2_LOCRE0_SHIFT)
+#define MCG_BRD_C2_LOCRE0(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT))
+
+/*! @brief Set the LOCRE0 field to a new value. */
+#define MCG_WR_C2_LOCRE0(base, value) (MCG_RMW_C2(base, MCG_C2_LOCRE0_MASK, MCG_C2_LOCRE0(value)))
+#define MCG_BWR_C2_LOCRE0(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C3 - MCG Control 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C3 - MCG Control 3 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C3 register
+ */
+/*@{*/
+#define MCG_RD_C3(base)          (MCG_C3_REG(base))
+#define MCG_WR_C3(base, value)   (MCG_C3_REG(base) = (value))
+#define MCG_RMW_C3(base, mask, value) (MCG_WR_C3(base, (MCG_RD_C3(base) & ~(mask)) | (value)))
+#define MCG_SET_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) |  (value)))
+#define MCG_CLR_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) & ~(value)))
+#define MCG_TOG_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C4 - MCG Control 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C4 - MCG Control 4 Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Reset values for DRST and DMX32 bits are 0.
+ */
+/*!
+ * @name Constants and macros for entire MCG_C4 register
+ */
+/*@{*/
+#define MCG_RD_C4(base)          (MCG_C4_REG(base))
+#define MCG_WR_C4(base, value)   (MCG_C4_REG(base) = (value))
+#define MCG_RMW_C4(base, mask, value) (MCG_WR_C4(base, (MCG_RD_C4(base) & ~(mask)) | (value)))
+#define MCG_SET_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) |  (value)))
+#define MCG_CLR_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) & ~(value)))
+#define MCG_TOG_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C4 bitfields
+ */
+
+/*!
+ * @name Register MCG_C4, field SCFTRIM[0] (RW)
+ *
+ * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
+ * location . controls the smallest adjustment of the slow internal reference
+ * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
+ * decreases the period by the smallest amount possible. If an SCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_SCFTRIM field. */
+#define MCG_RD_C4_SCFTRIM(base) ((MCG_C4_REG(base) & MCG_C4_SCFTRIM_MASK) >> MCG_C4_SCFTRIM_SHIFT)
+#define MCG_BRD_C4_SCFTRIM(base) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT))
+
+/*! @brief Set the SCFTRIM field to a new value. */
+#define MCG_WR_C4_SCFTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_SCFTRIM_MASK, MCG_C4_SCFTRIM(value)))
+#define MCG_BWR_C4_SCFTRIM(base, value) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field FCTRIM[4:1] (RW)
+ *
+ * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
+ * location. controls the fast internal reference clock frequency by controlling
+ * the fast internal reference clock period. The FCTRIM bits are binary weighted,
+ * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
+ * increases the period, and decreasing the value decreases the period. If an
+ * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
+ * responsibility to copy that value from the nonvolatile memory location to this register.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_FCTRIM field. */
+#define MCG_RD_C4_FCTRIM(base) ((MCG_C4_REG(base) & MCG_C4_FCTRIM_MASK) >> MCG_C4_FCTRIM_SHIFT)
+#define MCG_BRD_C4_FCTRIM(base) (MCG_RD_C4_FCTRIM(base))
+
+/*! @brief Set the FCTRIM field to a new value. */
+#define MCG_WR_C4_FCTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_FCTRIM_MASK, MCG_C4_FCTRIM(value)))
+#define MCG_BWR_C4_FCTRIM(base, value) (MCG_WR_C4_FCTRIM(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
+ *
+ * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
+ * LP bit is set, writes to the DRS bits are ignored. The DRST read field
+ * indicates the current frequency range for DCOOUT. The DRST field does not update
+ * immediately after a write to the DRS field due to internal synchronization between
+ * clock domains. See the DCO Frequency Range table for more details.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Low range (reset default).
+ * - 0b01 - Encoding 1 - Mid range.
+ * - 0b10 - Encoding 2 - Mid-high range.
+ * - 0b11 - Encoding 3 - High range.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_DRST_DRS field. */
+#define MCG_RD_C4_DRST_DRS(base) ((MCG_C4_REG(base) & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
+#define MCG_BRD_C4_DRST_DRS(base) (MCG_RD_C4_DRST_DRS(base))
+
+/*! @brief Set the DRST_DRS field to a new value. */
+#define MCG_WR_C4_DRST_DRS(base, value) (MCG_RMW_C4(base, MCG_C4_DRST_DRS_MASK, MCG_C4_DRST_DRS(value)))
+#define MCG_BWR_C4_DRST_DRS(base, value) (MCG_WR_C4_DRST_DRS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field DMX32[7] (RW)
+ *
+ * The DMX32 bit controls whether the DCO frequency range is narrowed to its
+ * maximum frequency with a 32.768 kHz reference. The following table identifies
+ * settings for the DCO frequency range. The system clocks derived from this source
+ * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
+ * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
+ * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
+ * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
+ * 80-100 MHz 1 32.768 kHz 2929 96 MHz
+ *
+ * Values:
+ * - 0b0 - DCO has a default range of 25%.
+ * - 0b1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_DMX32 field. */
+#define MCG_RD_C4_DMX32(base) ((MCG_C4_REG(base) & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
+#define MCG_BRD_C4_DMX32(base) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT))
+
+/*! @brief Set the DMX32 field to a new value. */
+#define MCG_WR_C4_DMX32(base, value) (MCG_RMW_C4(base, MCG_C4_DMX32_MASK, MCG_C4_DMX32(value)))
+#define MCG_BWR_C4_DMX32(base, value) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C5 - MCG Control 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C5 - MCG Control 5 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C5 register
+ */
+/*@{*/
+#define MCG_RD_C5(base)          (MCG_C5_REG(base))
+#define MCG_WR_C5(base, value)   (MCG_C5_REG(base) = (value))
+#define MCG_RMW_C5(base, mask, value) (MCG_WR_C5(base, (MCG_RD_C5(base) & ~(mask)) | (value)))
+#define MCG_SET_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) |  (value)))
+#define MCG_CLR_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) & ~(value)))
+#define MCG_TOG_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C5 bitfields
+ */
+
+/*!
+ * @name Register MCG_C5, field PRDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the PLL.
+ * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
+ * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
+ * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
+ * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
+ * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
+ * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
+ * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
+ * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
+ * Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PRDIV0 field. */
+#define MCG_RD_C5_PRDIV0(base) ((MCG_C5_REG(base) & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
+#define MCG_BRD_C5_PRDIV0(base) (MCG_RD_C5_PRDIV0(base))
+
+/*! @brief Set the PRDIV0 field to a new value. */
+#define MCG_WR_C5_PRDIV0(base, value) (MCG_RMW_C5(base, MCG_C5_PRDIV0_MASK, MCG_C5_PRDIV0(value)))
+#define MCG_BWR_C5_PRDIV0(base, value) (MCG_WR_C5_PRDIV0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C5, field PLLSTEN0[5] (RW)
+ *
+ * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
+ * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
+ * has no affect and does not enable the PLL Clock to run if it is written to 1.
+ *
+ * Values:
+ * - 0b0 - MCGPLLCLK is disabled in any of the Stop modes.
+ * - 0b1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */
+#define MCG_RD_C5_PLLSTEN0(base) ((MCG_C5_REG(base) & MCG_C5_PLLSTEN0_MASK) >> MCG_C5_PLLSTEN0_SHIFT)
+#define MCG_BRD_C5_PLLSTEN0(base) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLSTEN0_SHIFT))
+
+/*! @brief Set the PLLSTEN0 field to a new value. */
+#define MCG_WR_C5_PLLSTEN0(base, value) (MCG_RMW_C5(base, MCG_C5_PLLSTEN0_MASK, MCG_C5_PLLSTEN0(value)))
+#define MCG_BWR_C5_PLLSTEN0(base, value) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLSTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C5, field PLLCLKEN0[6] (RW)
+ *
+ * Enables the PLL independent of PLLS and enables the PLL clock for use as
+ * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
+ * PLL reference clock in the range of 2 - 4 MHz range prior to setting the
+ * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
+ * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
+ * and the external oscillator is being used as the reference clock, the OSCINIT 0
+ * bit should be checked to make sure it is set.
+ *
+ * Values:
+ * - 0b0 - MCGPLLCLK is inactive.
+ * - 0b1 - MCGPLLCLK is active.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */
+#define MCG_RD_C5_PLLCLKEN0(base) ((MCG_C5_REG(base) & MCG_C5_PLLCLKEN0_MASK) >> MCG_C5_PLLCLKEN0_SHIFT)
+#define MCG_BRD_C5_PLLCLKEN0(base) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLCLKEN0_SHIFT))
+
+/*! @brief Set the PLLCLKEN0 field to a new value. */
+#define MCG_WR_C5_PLLCLKEN0(base, value) (MCG_RMW_C5(base, MCG_C5_PLLCLKEN0_MASK, MCG_C5_PLLCLKEN0(value)))
+#define MCG_BWR_C5_PLLCLKEN0(base, value) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLCLKEN0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C6 - MCG Control 6 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C6 - MCG Control 6 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C6 register
+ */
+/*@{*/
+#define MCG_RD_C6(base)          (MCG_C6_REG(base))
+#define MCG_WR_C6(base, value)   (MCG_C6_REG(base) = (value))
+#define MCG_RMW_C6(base, mask, value) (MCG_WR_C6(base, (MCG_RD_C6(base) & ~(mask)) | (value)))
+#define MCG_SET_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) |  (value)))
+#define MCG_CLR_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) & ~(value)))
+#define MCG_TOG_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C6 bitfields
+ */
+
+/*!
+ * @name Register MCG_C6, field VDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
+ * establish the multiplication factor (M) applied to the reference clock frequency.
+ * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
+ * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
+ * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
+ * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
+ * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
+ * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
+ * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_VDIV0 field. */
+#define MCG_RD_C6_VDIV0(base) ((MCG_C6_REG(base) & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
+#define MCG_BRD_C6_VDIV0(base) (MCG_RD_C6_VDIV0(base))
+
+/*! @brief Set the VDIV0 field to a new value. */
+#define MCG_WR_C6_VDIV0(base, value) (MCG_RMW_C6(base, MCG_C6_VDIV0_MASK, MCG_C6_VDIV0(value)))
+#define MCG_BWR_C6_VDIV0(base, value) (MCG_WR_C6_VDIV0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field CME0[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the OSC0 external reference
+ * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
+ * generated following a loss of OSC0 indication. The CME0 bit must only be set
+ * to a logic 1 when the MCG is in an operational mode that uses the external
+ * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
+ * the value of the RANGE0 bits in the C2 register should not be changed. CME0
+ * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur while in Stop mode. CME0 should also be set to a
+ * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
+ *
+ * Values:
+ * - 0b0 - External clock monitor is disabled for OSC0.
+ * - 0b1 - External clock monitor is enabled for OSC0.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_CME0 field. */
+#define MCG_RD_C6_CME0(base) ((MCG_C6_REG(base) & MCG_C6_CME0_MASK) >> MCG_C6_CME0_SHIFT)
+#define MCG_BRD_C6_CME0(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_CME0_SHIFT))
+
+/*! @brief Set the CME0 field to a new value. */
+#define MCG_WR_C6_CME0(base, value) (MCG_RMW_C6(base, MCG_C6_CME0_MASK, MCG_C6_CME0(value)))
+#define MCG_BWR_C6_CME0(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_CME0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field PLLS[6] (RW)
+ *
+ * Controls whether the PLL or FLL output is selected as the MCG source when
+ * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
+ * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
+ *
+ * Values:
+ * - 0b0 - FLL is selected.
+ * - 0b1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
+ *     to generate a PLL reference clock in the range of 2-4 MHz prior to
+ *     setting the PLLS bit).
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_PLLS field. */
+#define MCG_RD_C6_PLLS(base) ((MCG_C6_REG(base) & MCG_C6_PLLS_MASK) >> MCG_C6_PLLS_SHIFT)
+#define MCG_BRD_C6_PLLS(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_PLLS_SHIFT))
+
+/*! @brief Set the PLLS field to a new value. */
+#define MCG_WR_C6_PLLS(base, value) (MCG_RMW_C6(base, MCG_C6_PLLS_MASK, MCG_C6_PLLS(value)))
+#define MCG_BWR_C6_PLLS(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_PLLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field LOLIE0[7] (RW)
+ *
+ * Determines if an interrupt request is made following a loss of lock
+ * indication. This bit only has an effect when LOLS 0 is set.
+ *
+ * Values:
+ * - 0b0 - No interrupt request is generated on loss of lock.
+ * - 0b1 - Generate an interrupt request on loss of lock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_LOLIE0 field. */
+#define MCG_RD_C6_LOLIE0(base) ((MCG_C6_REG(base) & MCG_C6_LOLIE0_MASK) >> MCG_C6_LOLIE0_SHIFT)
+#define MCG_BRD_C6_LOLIE0(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_LOLIE0_SHIFT))
+
+/*! @brief Set the LOLIE0 field to a new value. */
+#define MCG_WR_C6_LOLIE0(base, value) (MCG_RMW_C6(base, MCG_C6_LOLIE0_MASK, MCG_C6_LOLIE0(value)))
+#define MCG_BWR_C6_LOLIE0(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_LOLIE0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_S - MCG Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_S - MCG Status Register (RW)
+ *
+ * Reset value: 0x10U
+ */
+/*!
+ * @name Constants and macros for entire MCG_S register
+ */
+/*@{*/
+#define MCG_RD_S(base)           (MCG_S_REG(base))
+#define MCG_WR_S(base, value)    (MCG_S_REG(base) = (value))
+#define MCG_RMW_S(base, mask, value) (MCG_WR_S(base, (MCG_RD_S(base) & ~(mask)) | (value)))
+#define MCG_SET_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) |  (value)))
+#define MCG_CLR_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) & ~(value)))
+#define MCG_TOG_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_S bitfields
+ */
+
+/*!
+ * @name Register MCG_S, field IRCST[0] (RO)
+ *
+ * The IRCST bit indicates the current source for the internal reference clock
+ * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
+ * to the IRCS bit due to internal synchronization between clock domains. The
+ * IRCST bit will only be updated if the internal reference clock is enabled,
+ * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
+ * bit .
+ *
+ * Values:
+ * - 0b0 - Source of internal reference clock is the slow clock (32 kHz IRC).
+ * - 0b1 - Source of internal reference clock is the fast clock (4 MHz IRC).
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_IRCST field. */
+#define MCG_RD_S_IRCST(base) ((MCG_S_REG(base) & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT)
+#define MCG_BRD_S_IRCST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_IRCST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field OSCINIT0[1] (RO)
+ *
+ * This bit, which resets to 0, is set to 1 after the initialization cycles of
+ * the crystal oscillator clock have completed. After being set, the bit is
+ * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
+ * description for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_OSCINIT0 field. */
+#define MCG_RD_S_OSCINIT0(base) ((MCG_S_REG(base) & MCG_S_OSCINIT0_MASK) >> MCG_S_OSCINIT0_SHIFT)
+#define MCG_BRD_S_OSCINIT0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_OSCINIT0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field CLKST[3:2] (RO)
+ *
+ * These bits indicate the current clock mode. The CLKST bits do not update
+ * immediately after a write to the CLKS bits due to internal synchronization between
+ * clock domains.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Output of the FLL is selected (reset default).
+ * - 0b01 - Encoding 1 - Internal reference clock is selected.
+ * - 0b10 - Encoding 2 - External reference clock is selected.
+ * - 0b11 - Encoding 3 - Output of the PLL is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_CLKST field. */
+#define MCG_RD_S_CLKST(base) ((MCG_S_REG(base) & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
+#define MCG_BRD_S_CLKST(base) (MCG_RD_S_CLKST(base))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field IREFST[4] (RO)
+ *
+ * This bit indicates the current source for the FLL reference clock. The IREFST
+ * bit does not update immediately after a write to the IREFS bit due to
+ * internal synchronization between clock domains.
+ *
+ * Values:
+ * - 0b0 - Source of FLL reference clock is the external reference clock.
+ * - 0b1 - Source of FLL reference clock is the internal reference clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_IREFST field. */
+#define MCG_RD_S_IREFST(base) ((MCG_S_REG(base) & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
+#define MCG_BRD_S_IREFST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_IREFST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field PLLST[5] (RO)
+ *
+ * This bit indicates the clock source selected by PLLS . The PLLST bit does not
+ * update immediately after a write to the PLLS bit due to internal
+ * synchronization between clock domains.
+ *
+ * Values:
+ * - 0b0 - Source of PLLS clock is FLL clock.
+ * - 0b1 - Source of PLLS clock is PLL output clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_PLLST field. */
+#define MCG_RD_S_PLLST(base) ((MCG_S_REG(base) & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT)
+#define MCG_BRD_S_PLLST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_PLLST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field LOCK0[6] (RO)
+ *
+ * This bit indicates whether the PLL has acquired lock. Lock detection is only
+ * enabled when the PLL is enabled (either through clock mode selection or
+ * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
+ * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
+ * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
+ * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
+ * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
+ * reference clock will also cause the LOCK0 bit to clear until the PLL has
+ * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
+ * the lock status bit to clear and stay cleared until the Stop mode is exited
+ * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
+ * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
+ * again.
+ *
+ * Values:
+ * - 0b0 - PLL is currently unlocked.
+ * - 0b1 - PLL is currently locked.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_LOCK0 field. */
+#define MCG_RD_S_LOCK0(base) ((MCG_S_REG(base) & MCG_S_LOCK0_MASK) >> MCG_S_LOCK0_SHIFT)
+#define MCG_BRD_S_LOCK0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOCK0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field LOLS0[7] (W1C)
+ *
+ * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
+ * if after acquiring lock, the PLL output frequency has fallen outside the lock
+ * exit frequency tolerance, D unl . LOLIE determines whether an interrupt
+ * request is made when LOLS is set. LOLRE determines whether a reset request is made
+ * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
+ * when set. Writing a logic 0 to this bit has no effect.
+ *
+ * Values:
+ * - 0b0 - PLL has not lost lock since LOLS 0 was last cleared.
+ * - 0b1 - PLL has lost lock since LOLS 0 was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_LOLS0 field. */
+#define MCG_RD_S_LOLS0(base) ((MCG_S_REG(base) & MCG_S_LOLS0_MASK) >> MCG_S_LOLS0_SHIFT)
+#define MCG_BRD_S_LOLS0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOLS0_SHIFT))
+
+/*! @brief Set the LOLS0 field to a new value. */
+#define MCG_WR_S_LOLS0(base, value) (MCG_RMW_S(base, MCG_S_LOLS0_MASK, MCG_S_LOLS0(value)))
+#define MCG_BWR_S_LOLS0(base, value) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOLS0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_SC - MCG Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_SC - MCG Status and Control Register (RW)
+ *
+ * Reset value: 0x02U
+ */
+/*!
+ * @name Constants and macros for entire MCG_SC register
+ */
+/*@{*/
+#define MCG_RD_SC(base)          (MCG_SC_REG(base))
+#define MCG_WR_SC(base, value)   (MCG_SC_REG(base) = (value))
+#define MCG_RMW_SC(base, mask, value) (MCG_WR_SC(base, (MCG_RD_SC(base) & ~(mask)) | (value)))
+#define MCG_SET_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) |  (value)))
+#define MCG_CLR_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) & ~(value)))
+#define MCG_TOG_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_SC bitfields
+ */
+
+/*!
+ * @name Register MCG_SC, field LOCS0[0] (W1C)
+ *
+ * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
+ * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
+ * logic 1 to it when set.
+ *
+ * Values:
+ * - 0b0 - Loss of OSC0 has not occurred.
+ * - 0b1 - Loss of OSC0 has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_LOCS0 field. */
+#define MCG_RD_SC_LOCS0(base) ((MCG_SC_REG(base) & MCG_SC_LOCS0_MASK) >> MCG_SC_LOCS0_SHIFT)
+#define MCG_BRD_SC_LOCS0(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT))
+
+/*! @brief Set the LOCS0 field to a new value. */
+#define MCG_WR_SC_LOCS0(base, value) (MCG_RMW_SC(base, MCG_SC_LOCS0_MASK, MCG_SC_LOCS0(value)))
+#define MCG_BWR_SC_LOCS0(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field FCRDIV[3:1] (RW)
+ *
+ * Selects the amount to divide down the fast internal reference clock. The
+ * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
+ * divider when the Fast IRC is enabled is not supported).
+ *
+ * Values:
+ * - 0b000 - Divide Factor is 1
+ * - 0b001 - Divide Factor is 2.
+ * - 0b010 - Divide Factor is 4.
+ * - 0b011 - Divide Factor is 8.
+ * - 0b100 - Divide Factor is 16
+ * - 0b101 - Divide Factor is 32
+ * - 0b110 - Divide Factor is 64
+ * - 0b111 - Divide Factor is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FCRDIV field. */
+#define MCG_RD_SC_FCRDIV(base) ((MCG_SC_REG(base) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
+#define MCG_BRD_SC_FCRDIV(base) (MCG_RD_SC_FCRDIV(base))
+
+/*! @brief Set the FCRDIV field to a new value. */
+#define MCG_WR_SC_FCRDIV(base, value) (MCG_RMW_SC(base, (MCG_SC_FCRDIV_MASK | MCG_SC_LOCS0_MASK), MCG_SC_FCRDIV(value)))
+#define MCG_BWR_SC_FCRDIV(base, value) (MCG_WR_SC_FCRDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field FLTPRSRV[4] (RW)
+ *
+ * This bit will prevent the FLL filter values from resetting allowing the FLL
+ * output frequency to remain the same during clock mode changes where the FLL/DCO
+ * output is still valid. (Note: This requires that the FLL reference frequency
+ * to remain the same as what it was prior to the new clock mode switch.
+ * Otherwise FLL filter and frequency values will change.)
+ *
+ * Values:
+ * - 0b0 - FLL filter and FLL frequency will reset on changes to currect clock
+ *     mode.
+ * - 0b1 - Fll filter and FLL frequency retain their previous values during new
+ *     clock mode change.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FLTPRSRV field. */
+#define MCG_RD_SC_FLTPRSRV(base) ((MCG_SC_REG(base) & MCG_SC_FLTPRSRV_MASK) >> MCG_SC_FLTPRSRV_SHIFT)
+#define MCG_BRD_SC_FLTPRSRV(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT))
+
+/*! @brief Set the FLTPRSRV field to a new value. */
+#define MCG_WR_SC_FLTPRSRV(base, value) (MCG_RMW_SC(base, (MCG_SC_FLTPRSRV_MASK | MCG_SC_LOCS0_MASK), MCG_SC_FLTPRSRV(value)))
+#define MCG_BWR_SC_FLTPRSRV(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATMF[5] (RW)
+ *
+ * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
+ * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
+ * registers is detected or the MCG enters into any Stop mode. A write to ATMF
+ * clears the flag.
+ *
+ * Values:
+ * - 0b0 - Automatic Trim Machine completed normally.
+ * - 0b1 - Automatic Trim Machine failed.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATMF field. */
+#define MCG_RD_SC_ATMF(base) ((MCG_SC_REG(base) & MCG_SC_ATMF_MASK) >> MCG_SC_ATMF_SHIFT)
+#define MCG_BRD_SC_ATMF(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT))
+
+/*! @brief Set the ATMF field to a new value. */
+#define MCG_WR_SC_ATMF(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMF(value)))
+#define MCG_BWR_SC_ATMF(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATMS[6] (RW)
+ *
+ * Selects the IRCS clock for Auto Trim Test.
+ *
+ * Values:
+ * - 0b0 - 32 kHz Internal Reference Clock selected.
+ * - 0b1 - 4 MHz Internal Reference Clock selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATMS field. */
+#define MCG_RD_SC_ATMS(base) ((MCG_SC_REG(base) & MCG_SC_ATMS_MASK) >> MCG_SC_ATMS_SHIFT)
+#define MCG_BRD_SC_ATMS(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT))
+
+/*! @brief Set the ATMS field to a new value. */
+#define MCG_WR_SC_ATMS(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMS(value)))
+#define MCG_BWR_SC_ATMS(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATME[7] (RW)
+ *
+ * Enables the Auto Trim Machine to start automatically trimming the selected
+ * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
+ * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
+ * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
+ * operation and clears this bit.
+ *
+ * Values:
+ * - 0b0 - Auto Trim Machine disabled.
+ * - 0b1 - Auto Trim Machine enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATME field. */
+#define MCG_RD_SC_ATME(base) ((MCG_SC_REG(base) & MCG_SC_ATME_MASK) >> MCG_SC_ATME_SHIFT)
+#define MCG_BRD_SC_ATME(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT))
+
+/*! @brief Set the ATME field to a new value. */
+#define MCG_WR_SC_ATME(base, value) (MCG_RMW_SC(base, (MCG_SC_ATME_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATME(value)))
+#define MCG_BWR_SC_ATME(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_ATCVH register
+ */
+/*@{*/
+#define MCG_RD_ATCVH(base)       (MCG_ATCVH_REG(base))
+#define MCG_WR_ATCVH(base, value) (MCG_ATCVH_REG(base) = (value))
+#define MCG_RMW_ATCVH(base, mask, value) (MCG_WR_ATCVH(base, (MCG_RD_ATCVH(base) & ~(mask)) | (value)))
+#define MCG_SET_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) |  (value)))
+#define MCG_CLR_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) & ~(value)))
+#define MCG_TOG_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_ATCVL register
+ */
+/*@{*/
+#define MCG_RD_ATCVL(base)       (MCG_ATCVL_REG(base))
+#define MCG_WR_ATCVL(base, value) (MCG_ATCVL_REG(base) = (value))
+#define MCG_RMW_ATCVL(base, mask, value) (MCG_WR_ATCVL(base, (MCG_RD_ATCVL(base) & ~(mask)) | (value)))
+#define MCG_SET_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) |  (value)))
+#define MCG_CLR_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) & ~(value)))
+#define MCG_TOG_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C7 - MCG Control 7 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C7 - MCG Control 7 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C7 register
+ */
+/*@{*/
+#define MCG_RD_C7(base)          (MCG_C7_REG(base))
+#define MCG_WR_C7(base, value)   (MCG_C7_REG(base) = (value))
+#define MCG_RMW_C7(base, mask, value) (MCG_WR_C7(base, (MCG_RD_C7(base) & ~(mask)) | (value)))
+#define MCG_SET_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) |  (value)))
+#define MCG_CLR_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) & ~(value)))
+#define MCG_TOG_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C7 bitfields
+ */
+
+/*!
+ * @name Register MCG_C7, field OSCSEL[1:0] (RW)
+ *
+ * Selects the MCG FLL external reference clock
+ *
+ * Values:
+ * - 0b00 - Selects Oscillator (OSCCLK0).
+ * - 0b01 - Selects 32 kHz RTC Oscillator.
+ * - 0b10 - Selects Oscillator (OSCCLK1).
+ * - 0b11 - RESERVED
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C7_OSCSEL field. */
+#define MCG_RD_C7_OSCSEL(base) ((MCG_C7_REG(base) & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
+#define MCG_BRD_C7_OSCSEL(base) (MCG_RD_C7_OSCSEL(base))
+
+/*! @brief Set the OSCSEL field to a new value. */
+#define MCG_WR_C7_OSCSEL(base, value) (MCG_RMW_C7(base, MCG_C7_OSCSEL_MASK, MCG_C7_OSCSEL(value)))
+#define MCG_BWR_C7_OSCSEL(base, value) (MCG_WR_C7_OSCSEL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C8 - MCG Control 8 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C8 - MCG Control 8 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C8 register
+ */
+/*@{*/
+#define MCG_RD_C8(base)          (MCG_C8_REG(base))
+#define MCG_WR_C8(base, value)   (MCG_C8_REG(base) = (value))
+#define MCG_RMW_C8(base, mask, value) (MCG_WR_C8(base, (MCG_RD_C8(base) & ~(mask)) | (value)))
+#define MCG_SET_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) |  (value)))
+#define MCG_CLR_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) & ~(value)))
+#define MCG_TOG_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C8 bitfields
+ */
+
+/*!
+ * @name Register MCG_C8, field LOCS1[0] (W1C)
+ *
+ * This bit indicates when a loss of clock has occurred. This bit is cleared by
+ * writing a logic 1 to it when set.
+ *
+ * Values:
+ * - 0b0 - Loss of RTC has not occur.
+ * - 0b1 - Loss of RTC has occur
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOCS1 field. */
+#define MCG_RD_C8_LOCS1(base) ((MCG_C8_REG(base) & MCG_C8_LOCS1_MASK) >> MCG_C8_LOCS1_SHIFT)
+#define MCG_BRD_C8_LOCS1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT))
+
+/*! @brief Set the LOCS1 field to a new value. */
+#define MCG_WR_C8_LOCS1(base, value) (MCG_RMW_C8(base, MCG_C8_LOCS1_MASK, MCG_C8_LOCS1(value)))
+#define MCG_BWR_C8_LOCS1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field CME1[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the output of the RTC
+ * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
+ * reset request is generated following a loss of RTC clock indication. The CME1
+ * bit should be set to a logic 1 when the MCG is in an operational mode that uses
+ * the RTC as its external reference clock or if the RTC is operational. CME1 bit
+ * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
+ * before entering VLPR or VLPW power modes.
+ *
+ * Values:
+ * - 0b0 - External clock monitor is disabled for RTC clock.
+ * - 0b1 - External clock monitor is enabled for RTC clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_CME1 field. */
+#define MCG_RD_C8_CME1(base) ((MCG_C8_REG(base) & MCG_C8_CME1_MASK) >> MCG_C8_CME1_SHIFT)
+#define MCG_BRD_C8_CME1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT))
+
+/*! @brief Set the CME1 field to a new value. */
+#define MCG_WR_C8_CME1(base, value) (MCG_RMW_C8(base, (MCG_C8_CME1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_CME1(value)))
+#define MCG_BWR_C8_CME1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field LOLRE[6] (RW)
+ *
+ * Determines if an interrupt or a reset request is made following a PLL loss of
+ * lock.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a PLL loss of lock indication. The
+ *     PLL loss of lock interrupt enable bit must also be set to generate the
+ *     interrupt request.
+ * - 0b1 - Generate a reset request on a PLL loss of lock indication.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOLRE field. */
+#define MCG_RD_C8_LOLRE(base) ((MCG_C8_REG(base) & MCG_C8_LOLRE_MASK) >> MCG_C8_LOLRE_SHIFT)
+#define MCG_BRD_C8_LOLRE(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOLRE_SHIFT))
+
+/*! @brief Set the LOLRE field to a new value. */
+#define MCG_WR_C8_LOLRE(base, value) (MCG_RMW_C8(base, (MCG_C8_LOLRE_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOLRE(value)))
+#define MCG_BWR_C8_LOLRE(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOLRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field LOCRE1[7] (RW)
+ *
+ * Determines if a interrupt or a reset request is made following a loss of RTC
+ * external reference clock. The LOCRE1 only has an affect when CME1 is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a loss of RTC external reference
+ *     clock.
+ * - 0b1 - Generate a reset request on a loss of RTC external reference clock
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOCRE1 field. */
+#define MCG_RD_C8_LOCRE1(base) ((MCG_C8_REG(base) & MCG_C8_LOCRE1_MASK) >> MCG_C8_LOCRE1_SHIFT)
+#define MCG_BRD_C8_LOCRE1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT))
+
+/*! @brief Set the LOCRE1 field to a new value. */
+#define MCG_WR_C8_LOCRE1(base, value) (MCG_RMW_C8(base, (MCG_C8_LOCRE1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOCRE1(value)))
+#define MCG_BWR_C8_LOCRE1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 MCM
+ *
+ * Core Platform Miscellaneous Control Module
+ *
+ * Registers defined in this header file:
+ * - MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ * - MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ * - MCM_CR - Control Register
+ * - MCM_ISCR - Interrupt Status Register
+ * - MCM_ETBCC - ETB Counter Control register
+ * - MCM_ETBRL - ETB Reload register
+ * - MCM_ETBCNT - ETB Counter Value register
+ * - MCM_PID - Process ID register
+ */
+
+#define MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
+#define MCM_IDX (0U) /*!< Instance number for MCM. */
+
+/*******************************************************************************
+ * MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
+ *
+ * Reset value: 0x001FU
+ *
+ * PLASC is a 16-bit read-only register identifying the presence/absence of bus
+ * slave connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLASC register
+ */
+/*@{*/
+#define MCM_RD_PLASC(base)       (MCM_PLASC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLASC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLASC, field ASC[7:0] (RO)
+ *
+ * Values:
+ * - 0b00000000 - A bus slave connection to AXBS input port n is absent
+ * - 0b00000001 - A bus slave connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLASC_ASC field. */
+#define MCM_RD_PLASC_ASC(base) ((MCM_PLASC_REG(base) & MCM_PLASC_ASC_MASK) >> MCM_PLASC_ASC_SHIFT)
+#define MCM_BRD_PLASC_ASC(base) (MCM_RD_PLASC_ASC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
+ *
+ * Reset value: 0x0037U
+ *
+ * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
+ * master connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLAMC register
+ */
+/*@{*/
+#define MCM_RD_PLAMC(base)       (MCM_PLAMC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLAMC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLAMC, field AMC[7:0] (RO)
+ *
+ * Values:
+ * - 0b00000000 - A bus master connection to AXBS input port n is absent
+ * - 0b00000001 - A bus master connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLAMC_AMC field. */
+#define MCM_RD_PLAMC_AMC(base) ((MCM_PLAMC_REG(base) & MCM_PLAMC_AMC_MASK) >> MCM_PLAMC_AMC_SHIFT)
+#define MCM_BRD_PLAMC_AMC(base) (MCM_RD_PLAMC_AMC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_CR - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CR defines the arbitration and protection schemes for the two system RAM
+ * arrays.
+ */
+/*!
+ * @name Constants and macros for entire MCM_CR register
+ */
+/*@{*/
+#define MCM_RD_CR(base)          (MCM_CR_REG(base))
+#define MCM_WR_CR(base, value)   (MCM_CR_REG(base) = (value))
+#define MCM_RMW_CR(base, mask, value) (MCM_WR_CR(base, (MCM_RD_CR(base) & ~(mask)) | (value)))
+#define MCM_SET_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) |  (value)))
+#define MCM_CLR_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) & ~(value)))
+#define MCM_TOG_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_CR bitfields
+ */
+
+/*!
+ * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_U array.
+ *
+ * Values:
+ * - 0b00 - Round robin
+ * - 0b01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 0b10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 0b11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMUAP field. */
+#define MCM_RD_CR_SRAMUAP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMUAP_MASK) >> MCM_CR_SRAMUAP_SHIFT)
+#define MCM_BRD_CR_SRAMUAP(base) (MCM_RD_CR_SRAMUAP(base))
+
+/*! @brief Set the SRAMUAP field to a new value. */
+#define MCM_WR_CR_SRAMUAP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMUAP_MASK, MCM_CR_SRAMUAP(value)))
+#define MCM_BWR_CR_SRAMUAP(base, value) (MCM_WR_CR_SRAMUAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMUWP[26] (RW)
+ *
+ * When this bit is set, writes to SRAM_U array generates a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMUWP field. */
+#define MCM_RD_CR_SRAMUWP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMUWP_MASK) >> MCM_CR_SRAMUWP_SHIFT)
+#define MCM_BRD_CR_SRAMUWP(base) (MCM_RD_CR_SRAMUWP(base))
+
+/*! @brief Set the SRAMUWP field to a new value. */
+#define MCM_WR_CR_SRAMUWP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMUWP_MASK, MCM_CR_SRAMUWP(value)))
+#define MCM_BWR_CR_SRAMUWP(base, value) (MCM_WR_CR_SRAMUWP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_L array.
+ *
+ * Values:
+ * - 0b00 - Round robin
+ * - 0b01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 0b10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 0b11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMLAP field. */
+#define MCM_RD_CR_SRAMLAP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMLAP_MASK) >> MCM_CR_SRAMLAP_SHIFT)
+#define MCM_BRD_CR_SRAMLAP(base) (MCM_RD_CR_SRAMLAP(base))
+
+/*! @brief Set the SRAMLAP field to a new value. */
+#define MCM_WR_CR_SRAMLAP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMLAP_MASK, MCM_CR_SRAMLAP(value)))
+#define MCM_BWR_CR_SRAMLAP(base, value) (MCM_WR_CR_SRAMLAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMLWP[30] (RW)
+ *
+ * When this bit is set, writes to SRAM_L array generates a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMLWP field. */
+#define MCM_RD_CR_SRAMLWP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMLWP_MASK) >> MCM_CR_SRAMLWP_SHIFT)
+#define MCM_BRD_CR_SRAMLWP(base) (MCM_RD_CR_SRAMLWP(base))
+
+/*! @brief Set the SRAMLWP field to a new value. */
+#define MCM_WR_CR_SRAMLWP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMLWP_MASK, MCM_CR_SRAMLWP(value)))
+#define MCM_BWR_CR_SRAMLWP(base, value) (MCM_WR_CR_SRAMLWP(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ISCR - Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ISCR - Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ISCR register
+ */
+/*@{*/
+#define MCM_RD_ISCR(base)        (MCM_ISCR_REG(base))
+#define MCM_WR_ISCR(base, value) (MCM_ISCR_REG(base) = (value))
+#define MCM_RMW_ISCR(base, mask, value) (MCM_WR_ISCR(base, (MCM_RD_ISCR(base) & ~(mask)) | (value)))
+#define MCM_SET_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) |  (value)))
+#define MCM_CLR_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) & ~(value)))
+#define MCM_TOG_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ISCR bitfields
+ */
+
+/*!
+ * @name Register MCM_ISCR, field IRQ[1] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0b0 - No pending interrupt
+ * - 0b1 - Due to the ETB counter expiring, a normal interrupt is pending
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_IRQ field. */
+#define MCM_RD_ISCR_IRQ(base) ((MCM_ISCR_REG(base) & MCM_ISCR_IRQ_MASK) >> MCM_ISCR_IRQ_SHIFT)
+#define MCM_BRD_ISCR_IRQ(base) (MCM_RD_ISCR_IRQ(base))
+
+/*! @brief Set the IRQ field to a new value. */
+#define MCM_WR_ISCR_IRQ(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_IRQ(value)))
+#define MCM_BWR_ISCR_IRQ(base, value) (MCM_WR_ISCR_IRQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field NMI[2] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0b0 - No pending NMI
+ * - 0b1 - Due to the ETB counter expiring, an NMI is pending
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_NMI field. */
+#define MCM_RD_ISCR_NMI(base) ((MCM_ISCR_REG(base) & MCM_ISCR_NMI_MASK) >> MCM_ISCR_NMI_SHIFT)
+#define MCM_BRD_ISCR_NMI(base) (MCM_RD_ISCR_NMI(base))
+
+/*! @brief Set the NMI field to a new value. */
+#define MCM_WR_ISCR_NMI(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_NMI_MASK | MCM_ISCR_IRQ_MASK), MCM_ISCR_NMI(value)))
+#define MCM_BWR_ISCR_NMI(base, value) (MCM_WR_ISCR_NMI(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field DHREQ[3] (RO)
+ *
+ * Indicates that a debug halt request is initiated due to a ETB counter
+ * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
+ * counter is disabled or when the ETB counter is reloaded.
+ *
+ * Values:
+ * - 0b0 - No debug halt request
+ * - 0b1 - Debug halt request initiated
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_DHREQ field. */
+#define MCM_RD_ISCR_DHREQ(base) ((MCM_ISCR_REG(base) & MCM_ISCR_DHREQ_MASK) >> MCM_ISCR_DHREQ_SHIFT)
+#define MCM_BRD_ISCR_DHREQ(base) (MCM_RD_ISCR_DHREQ(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIOC[8] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
+ * illegal operation has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IOC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIOC field. */
+#define MCM_RD_ISCR_FIOC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIOC_MASK) >> MCM_ISCR_FIOC_SHIFT)
+#define MCM_BRD_ISCR_FIOC(base) (MCM_RD_ISCR_FIOC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FDZC[9] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
+ * divide by zero has been detected in the processor's FPU. Once set, this bit remains
+ * set until software clears the FPSCR[DZC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FDZC field. */
+#define MCM_RD_ISCR_FDZC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FDZC_MASK) >> MCM_ISCR_FDZC_SHIFT)
+#define MCM_BRD_ISCR_FDZC(base) (MCM_RD_ISCR_FDZC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FOFC[10] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
+ * overflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[OFC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FOFC field. */
+#define MCM_RD_ISCR_FOFC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FOFC_MASK) >> MCM_ISCR_FOFC_SHIFT)
+#define MCM_BRD_ISCR_FOFC(base) (MCM_RD_ISCR_FOFC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FUFC[11] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
+ * underflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[UFC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FUFC field. */
+#define MCM_RD_ISCR_FUFC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FUFC_MASK) >> MCM_ISCR_FUFC_SHIFT)
+#define MCM_BRD_ISCR_FUFC(base) (MCM_RD_ISCR_FUFC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIXC[12] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
+ * inexact number has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IXC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIXC field. */
+#define MCM_RD_ISCR_FIXC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIXC_MASK) >> MCM_ISCR_FIXC_SHIFT)
+#define MCM_BRD_ISCR_FIXC(base) (MCM_RD_ISCR_FIXC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIDC[15] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
+ * denormalized number has been detected in the processor's FPU. Once set, this
+ * bit remains set until software clears the FPSCR[IDC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIDC field. */
+#define MCM_RD_ISCR_FIDC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIDC_MASK) >> MCM_ISCR_FIDC_SHIFT)
+#define MCM_BRD_ISCR_FIDC(base) (MCM_RD_ISCR_FIDC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIOCE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIOCE field. */
+#define MCM_RD_ISCR_FIOCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIOCE_MASK) >> MCM_ISCR_FIOCE_SHIFT)
+#define MCM_BRD_ISCR_FIOCE(base) (MCM_RD_ISCR_FIOCE(base))
+
+/*! @brief Set the FIOCE field to a new value. */
+#define MCM_WR_ISCR_FIOCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIOCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIOCE(value)))
+#define MCM_BWR_ISCR_FIOCE(base, value) (MCM_WR_ISCR_FIOCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FDZCE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FDZCE field. */
+#define MCM_RD_ISCR_FDZCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FDZCE_MASK) >> MCM_ISCR_FDZCE_SHIFT)
+#define MCM_BRD_ISCR_FDZCE(base) (MCM_RD_ISCR_FDZCE(base))
+
+/*! @brief Set the FDZCE field to a new value. */
+#define MCM_WR_ISCR_FDZCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FDZCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FDZCE(value)))
+#define MCM_BWR_ISCR_FDZCE(base, value) (MCM_WR_ISCR_FDZCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FOFCE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FOFCE field. */
+#define MCM_RD_ISCR_FOFCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FOFCE_MASK) >> MCM_ISCR_FOFCE_SHIFT)
+#define MCM_BRD_ISCR_FOFCE(base) (MCM_RD_ISCR_FOFCE(base))
+
+/*! @brief Set the FOFCE field to a new value. */
+#define MCM_WR_ISCR_FOFCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FOFCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FOFCE(value)))
+#define MCM_BWR_ISCR_FOFCE(base, value) (MCM_WR_ISCR_FOFCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FUFCE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FUFCE field. */
+#define MCM_RD_ISCR_FUFCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FUFCE_MASK) >> MCM_ISCR_FUFCE_SHIFT)
+#define MCM_BRD_ISCR_FUFCE(base) (MCM_RD_ISCR_FUFCE(base))
+
+/*! @brief Set the FUFCE field to a new value. */
+#define MCM_WR_ISCR_FUFCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FUFCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FUFCE(value)))
+#define MCM_BWR_ISCR_FUFCE(base, value) (MCM_WR_ISCR_FUFCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIXCE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIXCE field. */
+#define MCM_RD_ISCR_FIXCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIXCE_MASK) >> MCM_ISCR_FIXCE_SHIFT)
+#define MCM_BRD_ISCR_FIXCE(base) (MCM_RD_ISCR_FIXCE(base))
+
+/*! @brief Set the FIXCE field to a new value. */
+#define MCM_WR_ISCR_FIXCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIXCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIXCE(value)))
+#define MCM_BWR_ISCR_FIXCE(base, value) (MCM_WR_ISCR_FIXCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIDCE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIDCE field. */
+#define MCM_RD_ISCR_FIDCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIDCE_MASK) >> MCM_ISCR_FIDCE_SHIFT)
+#define MCM_BRD_ISCR_FIDCE(base) (MCM_RD_ISCR_FIDCE(base))
+
+/*! @brief Set the FIDCE field to a new value. */
+#define MCM_WR_ISCR_FIDCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIDCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIDCE(value)))
+#define MCM_BWR_ISCR_FIDCE(base, value) (MCM_WR_ISCR_FIDCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBCC - ETB Counter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBCC - ETB Counter Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBCC register
+ */
+/*@{*/
+#define MCM_RD_ETBCC(base)       (MCM_ETBCC_REG(base))
+#define MCM_WR_ETBCC(base, value) (MCM_ETBCC_REG(base) = (value))
+#define MCM_RMW_ETBCC(base, mask, value) (MCM_WR_ETBCC(base, (MCM_RD_ETBCC(base) & ~(mask)) | (value)))
+#define MCM_SET_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) |  (value)))
+#define MCM_CLR_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) & ~(value)))
+#define MCM_TOG_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBCC bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCC, field CNTEN[0] (RW)
+ *
+ * Enables the ETB counter.
+ *
+ * Values:
+ * - 0b0 - ETB counter disabled
+ * - 0b1 - ETB counter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_CNTEN field. */
+#define MCM_RD_ETBCC_CNTEN(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_CNTEN_MASK) >> MCM_ETBCC_CNTEN_SHIFT)
+#define MCM_BRD_ETBCC_CNTEN(base) (MCM_RD_ETBCC_CNTEN(base))
+
+/*! @brief Set the CNTEN field to a new value. */
+#define MCM_WR_ETBCC_CNTEN(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_CNTEN_MASK, MCM_ETBCC_CNTEN(value)))
+#define MCM_BWR_ETBCC_CNTEN(base, value) (MCM_WR_ETBCC_CNTEN(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
+ *
+ * Values:
+ * - 0b00 - No response when the ETB count expires
+ * - 0b01 - Generate a normal interrupt when the ETB count expires
+ * - 0b10 - Generate an NMI when the ETB count expires
+ * - 0b11 - Generate a debug halt when the ETB count expires
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_RSPT field. */
+#define MCM_RD_ETBCC_RSPT(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_RSPT_MASK) >> MCM_ETBCC_RSPT_SHIFT)
+#define MCM_BRD_ETBCC_RSPT(base) (MCM_RD_ETBCC_RSPT(base))
+
+/*! @brief Set the RSPT field to a new value. */
+#define MCM_WR_ETBCC_RSPT(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_RSPT_MASK, MCM_ETBCC_RSPT(value)))
+#define MCM_BWR_ETBCC_RSPT(base, value) (MCM_WR_ETBCC_RSPT(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field RLRQ[3] (RW)
+ *
+ * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
+ * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
+ * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
+ * If debug halt was enabled and a debug halt request was asserted on counter
+ * expiration, setting this bit clears the debug halt request.
+ *
+ * Values:
+ * - 0b0 - No effect
+ * - 0b1 - Clears pending debug halt, NMI, or IRQ interrupt requests
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_RLRQ field. */
+#define MCM_RD_ETBCC_RLRQ(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_RLRQ_MASK) >> MCM_ETBCC_RLRQ_SHIFT)
+#define MCM_BRD_ETBCC_RLRQ(base) (MCM_RD_ETBCC_RLRQ(base))
+
+/*! @brief Set the RLRQ field to a new value. */
+#define MCM_WR_ETBCC_RLRQ(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_RLRQ_MASK, MCM_ETBCC_RLRQ(value)))
+#define MCM_BWR_ETBCC_RLRQ(base, value) (MCM_WR_ETBCC_RLRQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field ETDIS[4] (RW)
+ *
+ * Disables the trace path from ETM to TPIU.
+ *
+ * Values:
+ * - 0b0 - ETM-to-TPIU trace path enabled
+ * - 0b1 - ETM-to-TPIU trace path disabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_ETDIS field. */
+#define MCM_RD_ETBCC_ETDIS(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_ETDIS_MASK) >> MCM_ETBCC_ETDIS_SHIFT)
+#define MCM_BRD_ETBCC_ETDIS(base) (MCM_RD_ETBCC_ETDIS(base))
+
+/*! @brief Set the ETDIS field to a new value. */
+#define MCM_WR_ETBCC_ETDIS(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_ETDIS_MASK, MCM_ETBCC_ETDIS(value)))
+#define MCM_BWR_ETBCC_ETDIS(base, value) (MCM_WR_ETBCC_ETDIS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field ITDIS[5] (RW)
+ *
+ * Disables the trace path from ITM to TPIU.
+ *
+ * Values:
+ * - 0b0 - ITM-to-TPIU trace path enabled
+ * - 0b1 - ITM-to-TPIU trace path disabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_ITDIS field. */
+#define MCM_RD_ETBCC_ITDIS(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_ITDIS_MASK) >> MCM_ETBCC_ITDIS_SHIFT)
+#define MCM_BRD_ETBCC_ITDIS(base) (MCM_RD_ETBCC_ITDIS(base))
+
+/*! @brief Set the ITDIS field to a new value. */
+#define MCM_WR_ETBCC_ITDIS(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_ITDIS_MASK, MCM_ETBCC_ITDIS(value)))
+#define MCM_BWR_ETBCC_ITDIS(base, value) (MCM_WR_ETBCC_ITDIS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBRL - ETB Reload register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBRL - ETB Reload register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBRL register
+ */
+/*@{*/
+#define MCM_RD_ETBRL(base)       (MCM_ETBRL_REG(base))
+#define MCM_WR_ETBRL(base, value) (MCM_ETBRL_REG(base) = (value))
+#define MCM_RMW_ETBRL(base, mask, value) (MCM_WR_ETBRL(base, (MCM_RD_ETBRL(base) & ~(mask)) | (value)))
+#define MCM_SET_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) |  (value)))
+#define MCM_CLR_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) & ~(value)))
+#define MCM_TOG_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBRL bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
+ *
+ * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
+ * value to this field results in a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBRL_RELOAD field. */
+#define MCM_RD_ETBRL_RELOAD(base) ((MCM_ETBRL_REG(base) & MCM_ETBRL_RELOAD_MASK) >> MCM_ETBRL_RELOAD_SHIFT)
+#define MCM_BRD_ETBRL_RELOAD(base) (MCM_RD_ETBRL_RELOAD(base))
+
+/*! @brief Set the RELOAD field to a new value. */
+#define MCM_WR_ETBRL_RELOAD(base, value) (MCM_RMW_ETBRL(base, MCM_ETBRL_RELOAD_MASK, MCM_ETBRL_RELOAD(value)))
+#define MCM_BWR_ETBRL_RELOAD(base, value) (MCM_WR_ETBRL_RELOAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBCNT - ETB Counter Value register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBCNT - ETB Counter Value register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBCNT register
+ */
+/*@{*/
+#define MCM_RD_ETBCNT(base)      (MCM_ETBCNT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBCNT bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
+ *
+ * Indicates the current 0-mod-4 value of the counter.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCNT_COUNTER field. */
+#define MCM_RD_ETBCNT_COUNTER(base) ((MCM_ETBCNT_REG(base) & MCM_ETBCNT_COUNTER_MASK) >> MCM_ETBCNT_COUNTER_SHIFT)
+#define MCM_BRD_ETBCNT_COUNTER(base) (MCM_RD_ETBCNT_COUNTER(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PID - Process ID register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PID - Process ID register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register drives the M0_PID and M1_PID values in the Memory Protection
+ * Unit(MPU). System software loads this register before passing control to a given
+ * user mode process. If the PID of the process does not match the value in this
+ * register, a bus error occurs. See the MPU chapter for more details.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PID register
+ */
+/*@{*/
+#define MCM_RD_PID(base)         (MCM_PID_REG(base))
+#define MCM_WR_PID(base, value)  (MCM_PID_REG(base) = (value))
+#define MCM_RMW_PID(base, mask, value) (MCM_WR_PID(base, (MCM_RD_PID(base) & ~(mask)) | (value)))
+#define MCM_SET_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) |  (value)))
+#define MCM_CLR_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) & ~(value)))
+#define MCM_TOG_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PID bitfields
+ */
+
+/*!
+ * @name Register MCM_PID, field PID[7:0] (RW)
+ *
+ * Drives the M0_PID and M1_PID values in the MPU.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PID_PID field. */
+#define MCM_RD_PID_PID(base) ((MCM_PID_REG(base) & MCM_PID_PID_MASK) >> MCM_PID_PID_SHIFT)
+#define MCM_BRD_PID_PID(base) (MCM_RD_PID_PID(base))
+
+/*! @brief Set the PID field to a new value. */
+#define MCM_WR_PID_PID(base, value) (MCM_RMW_PID(base, MCM_PID_PID_MASK, MCM_PID_PID(value)))
+#define MCM_BWR_PID_PID(base, value) (MCM_WR_PID_PID(base, value))
+/*@}*/
+
+/*
+ * MK64F12 MPU
+ *
+ * Memory protection unit
+ *
+ * Registers defined in this header file:
+ * - MPU_CESR - Control/Error Status Register
+ * - MPU_EAR - Error Address Register, slave port n
+ * - MPU_EDR - Error Detail Register, slave port n
+ * - MPU_WORD - Region Descriptor n, Word 0
+ * - MPU_RGDAAC - Region Descriptor Alternate Access Control n
+ */
+
+#define MPU_INSTANCE_COUNT (1U) /*!< Number of instances of the MPU module. */
+#define MPU_IDX (0U) /*!< Instance number for MPU. */
+
+/*******************************************************************************
+ * MPU_CESR - Control/Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_CESR - Control/Error Status Register (RW)
+ *
+ * Reset value: 0x00815101U
+ */
+/*!
+ * @name Constants and macros for entire MPU_CESR register
+ */
+/*@{*/
+#define MPU_RD_CESR(base)        (MPU_CESR_REG(base))
+#define MPU_WR_CESR(base, value) (MPU_CESR_REG(base) = (value))
+#define MPU_RMW_CESR(base, mask, value) (MPU_WR_CESR(base, (MPU_RD_CESR(base) & ~(mask)) | (value)))
+#define MPU_SET_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) |  (value)))
+#define MPU_CLR_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) & ~(value)))
+#define MPU_TOG_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_CESR bitfields
+ */
+
+/*!
+ * @name Register MPU_CESR, field VLD[0] (RW)
+ *
+ * Global enable/disable for the MPU.
+ *
+ * Values:
+ * - 0b0 - MPU is disabled. All accesses from all bus masters are allowed.
+ * - 0b1 - MPU is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_VLD field. */
+#define MPU_RD_CESR_VLD(base) ((MPU_CESR_REG(base) & MPU_CESR_VLD_MASK) >> MPU_CESR_VLD_SHIFT)
+#define MPU_BRD_CESR_VLD(base) (BITBAND_ACCESS32(&MPU_CESR_REG(base), MPU_CESR_VLD_SHIFT))
+
+/*! @brief Set the VLD field to a new value. */
+#define MPU_WR_CESR_VLD(base, value) (MPU_RMW_CESR(base, (MPU_CESR_VLD_MASK | MPU_CESR_SPERR_MASK), MPU_CESR_VLD(value)))
+#define MPU_BWR_CESR_VLD(base, value) (BITBAND_ACCESS32(&MPU_CESR_REG(base), MPU_CESR_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field NRGD[11:8] (RO)
+ *
+ * Indicates the number of region descriptors implemented in the MPU.
+ *
+ * Values:
+ * - 0b0000 - 8 region descriptors
+ * - 0b0001 - 12 region descriptors
+ * - 0b0010 - 16 region descriptors
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_NRGD field. */
+#define MPU_RD_CESR_NRGD(base) ((MPU_CESR_REG(base) & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT)
+#define MPU_BRD_CESR_NRGD(base) (MPU_RD_CESR_NRGD(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field NSP[15:12] (RO)
+ *
+ * Specifies the number of slave ports connected to the MPU.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_NSP field. */
+#define MPU_RD_CESR_NSP(base) ((MPU_CESR_REG(base) & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT)
+#define MPU_BRD_CESR_NSP(base) (MPU_RD_CESR_NSP(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field HRL[19:16] (RO)
+ *
+ * Specifies the MPU's hardware and definition revision level. It can be read by
+ * software to determine the functional definition of the module.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_HRL field. */
+#define MPU_RD_CESR_HRL(base) ((MPU_CESR_REG(base) & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT)
+#define MPU_BRD_CESR_HRL(base) (MPU_RD_CESR_HRL(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field SPERR[31:27] (W1C)
+ *
+ * Indicates a captured error in EARn and EDRn. This bit is set when the
+ * hardware detects an error and records the faulting address and attributes. It is
+ * cleared by writing one to it. If another error is captured at the exact same cycle
+ * as the write, the flag remains set. A find-first-one instruction or
+ * equivalent can detect the presence of a captured error. The following shows the
+ * correspondence between the bit number and slave port number: Bit 31 corresponds to
+ * slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
+ * port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
+ *
+ * Values:
+ * - 0b00000 - No error has occurred for slave port n.
+ * - 0b00001 - An error has occurred for slave port n.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_SPERR field. */
+#define MPU_RD_CESR_SPERR(base) ((MPU_CESR_REG(base) & MPU_CESR_SPERR_MASK) >> MPU_CESR_SPERR_SHIFT)
+#define MPU_BRD_CESR_SPERR(base) (MPU_RD_CESR_SPERR(base))
+
+/*! @brief Set the SPERR field to a new value. */
+#define MPU_WR_CESR_SPERR(base, value) (MPU_RMW_CESR(base, MPU_CESR_SPERR_MASK, MPU_CESR_SPERR(value)))
+#define MPU_BWR_CESR_SPERR(base, value) (MPU_WR_CESR_SPERR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_EAR - Error Address Register, slave port n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_EAR - Error Address Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, the 32-bit reference
+ * address is captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] set. Additional information about the faulting access is captured in
+ * the corresponding EDRn at the same time. This register and the corresponding
+ * EDRn contain the most recent access error; there are no hardware interlocks with
+ * CESR[SPERR], as the error registers are always loaded upon the occurrence of
+ * each protection violation.
+ */
+/*!
+ * @name Constants and macros for entire MPU_EAR register
+ */
+/*@{*/
+#define MPU_RD_EAR(base, index)  (MPU_EAR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_EDR - Error Detail Register, slave port n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_EDR - Error Detail Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, 32 bits of error detail
+ * are captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] is set. Information on the faulting address is captured in the
+ * corresponding EARn register at the same time. This register and the corresponding EARn
+ * register contain the most recent access error; there are no hardware interlocks
+ * with CESR[SPERR] as the error registers are always loaded upon the occurrence
+ * of each protection violation.
+ */
+/*!
+ * @name Constants and macros for entire MPU_EDR register
+ */
+/*@{*/
+#define MPU_RD_EDR(base, index)  (MPU_EDR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_EDR bitfields
+ */
+
+/*!
+ * @name Register MPU_EDR, field ERW[0] (RO)
+ *
+ * Indicates the access type of the faulting reference.
+ *
+ * Values:
+ * - 0b0 - Read
+ * - 0b1 - Write
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_ERW field. */
+#define MPU_RD_EDR_ERW(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT)
+#define MPU_BRD_EDR_ERW(base, index) (BITBAND_ACCESS32(&MPU_EDR_REG(base, index), MPU_EDR_ERW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EATTR[3:1] (RO)
+ *
+ * Indicates attribute information about the faulting reference. All other
+ * encodings are reserved.
+ *
+ * Values:
+ * - 0b000 - User mode, instruction access
+ * - 0b001 - User mode, data access
+ * - 0b010 - Supervisor mode, instruction access
+ * - 0b011 - Supervisor mode, data access
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EATTR field. */
+#define MPU_RD_EDR_EATTR(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT)
+#define MPU_BRD_EDR_EATTR(base, index) (MPU_RD_EDR_EATTR(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EMN[7:4] (RO)
+ *
+ * Indicates the bus master that generated the access error.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EMN field. */
+#define MPU_RD_EDR_EMN(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT)
+#define MPU_BRD_EDR_EMN(base, index) (MPU_RD_EDR_EMN(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EPID[15:8] (RO)
+ *
+ * Records the process identifier of the faulting reference. The process
+ * identifier is typically driven only by processor cores; for other bus masters, this
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EPID field. */
+#define MPU_RD_EDR_EPID(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT)
+#define MPU_BRD_EDR_EPID(base, index) (MPU_RD_EDR_EPID(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EACD[31:16] (RO)
+ *
+ * Indicates the region descriptor with the access error. If EDRn contains a
+ * captured error and EACD is cleared, an access did not hit in any region
+ * descriptor. If only a single EACD bit is set, the protection error was caused by a
+ * single non-overlapping region descriptor. If two or more EACD bits are set, the
+ * protection error was caused by an overlapping set of region descriptors.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EACD field. */
+#define MPU_RD_EDR_EACD(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EACD_MASK) >> MPU_EDR_EACD_SHIFT)
+#define MPU_BRD_EDR_EACD(base, index) (MPU_RD_EDR_EACD(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_WORD - Region Descriptor n, Word 0
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_WORD - Region Descriptor n, Word 0 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The first word of the region descriptor defines the 0-modulo-32 byte start
+ * address of the memory region. Writes to this register clear the region
+ * descriptor's valid bit (RGDn_WORD3[VLD]).
+ */
+/*!
+ * @name Constants and macros for entire MPU_WORD register
+ */
+/*@{*/
+#define MPU_RD_WORD(base, index, index2) (MPU_WORD_REG(base, index, index2))
+#define MPU_WR_WORD(base, index, index2, value) (MPU_WORD_REG(base, index, index2) = (value))
+#define MPU_RMW_WORD(base, index, index2, mask, value) (MPU_WR_WORD(base, index, index2, (MPU_RD_WORD(base, index, index2) & ~(mask)) | (value)))
+#define MPU_SET_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) |  (value)))
+#define MPU_CLR_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) & ~(value)))
+#define MPU_TOG_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_WORD bitfields
+ */
+
+/*!
+ * @name Register MPU_WORD, field VLD[0] (RW)
+ *
+ * Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
+ * bit.
+ *
+ * Values:
+ * - 0b0 - Region descriptor is invalid
+ * - 0b1 - Region descriptor is valid
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_VLD field. */
+#define MPU_RD_WORD_VLD(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_VLD_MASK) >> MPU_WORD_VLD_SHIFT)
+#define MPU_BRD_WORD_VLD(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_VLD_SHIFT))
+
+/*! @brief Set the VLD field to a new value. */
+#define MPU_WR_WORD_VLD(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_VLD_MASK, MPU_WORD_VLD(value)))
+#define MPU_BWR_WORD_VLD(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0UM field. */
+#define MPU_RD_WORD_M0UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0UM_MASK) >> MPU_WORD_M0UM_SHIFT)
+#define MPU_BRD_WORD_M0UM(base, index, index2) (MPU_RD_WORD_M0UM(base, index, index2))
+
+/*! @brief Set the M0UM field to a new value. */
+#define MPU_WR_WORD_M0UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0UM_MASK, MPU_WORD_M0UM(value)))
+#define MPU_BWR_WORD_M0UM(base, index, index2, value) (MPU_WR_WORD_M0UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0SM field. */
+#define MPU_RD_WORD_M0SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0SM_MASK) >> MPU_WORD_M0SM_SHIFT)
+#define MPU_BRD_WORD_M0SM(base, index, index2) (MPU_RD_WORD_M0SM(base, index, index2))
+
+/*! @brief Set the M0SM field to a new value. */
+#define MPU_WR_WORD_M0SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0SM_MASK, MPU_WORD_M0SM(value)))
+#define MPU_BWR_WORD_M0SM(base, index, index2, value) (MPU_WR_WORD_M0SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0PE[5] (RW)
+ *
+ * See M0PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0PE field. */
+#define MPU_RD_WORD_M0PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0PE_MASK) >> MPU_WORD_M0PE_SHIFT)
+#define MPU_BRD_WORD_M0PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M0PE_SHIFT))
+
+/*! @brief Set the M0PE field to a new value. */
+#define MPU_WR_WORD_M0PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0PE_MASK, MPU_WORD_M0PE(value)))
+#define MPU_BWR_WORD_M0PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M0PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field ENDADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 31-modulo-32 byte end address of the
+ * memory region. The MPU does not verify that ENDADDR >= SRTADDR.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_ENDADDR field. */
+#define MPU_RD_WORD_ENDADDR(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_ENDADDR_MASK) >> MPU_WORD_ENDADDR_SHIFT)
+#define MPU_BRD_WORD_ENDADDR(base, index, index2) (MPU_RD_WORD_ENDADDR(base, index, index2))
+
+/*! @brief Set the ENDADDR field to a new value. */
+#define MPU_WR_WORD_ENDADDR(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_ENDADDR_MASK, MPU_WORD_ENDADDR(value)))
+#define MPU_BWR_WORD_ENDADDR(base, index, index2, value) (MPU_WR_WORD_ENDADDR(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field SRTADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 0-modulo-32 byte start address of
+ * the memory region.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_SRTADDR field. */
+#define MPU_RD_WORD_SRTADDR(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_SRTADDR_MASK) >> MPU_WORD_SRTADDR_SHIFT)
+#define MPU_BRD_WORD_SRTADDR(base, index, index2) (MPU_RD_WORD_SRTADDR(base, index, index2))
+
+/*! @brief Set the SRTADDR field to a new value. */
+#define MPU_WR_WORD_SRTADDR(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_SRTADDR_MASK, MPU_WORD_SRTADDR(value)))
+#define MPU_BWR_WORD_SRTADDR(base, index, index2, value) (MPU_WR_WORD_SRTADDR(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1UM field. */
+#define MPU_RD_WORD_M1UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1UM_MASK) >> MPU_WORD_M1UM_SHIFT)
+#define MPU_BRD_WORD_M1UM(base, index, index2) (MPU_RD_WORD_M1UM(base, index, index2))
+
+/*! @brief Set the M1UM field to a new value. */
+#define MPU_WR_WORD_M1UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1UM_MASK, MPU_WORD_M1UM(value)))
+#define MPU_BWR_WORD_M1UM(base, index, index2, value) (MPU_WR_WORD_M1UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1SM field. */
+#define MPU_RD_WORD_M1SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1SM_MASK) >> MPU_WORD_M1SM_SHIFT)
+#define MPU_BRD_WORD_M1SM(base, index, index2) (MPU_RD_WORD_M1SM(base, index, index2))
+
+/*! @brief Set the M1SM field to a new value. */
+#define MPU_WR_WORD_M1SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1SM_MASK, MPU_WORD_M1SM(value)))
+#define MPU_BWR_WORD_M1SM(base, index, index2, value) (MPU_WR_WORD_M1SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1PE field. */
+#define MPU_RD_WORD_M1PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1PE_MASK) >> MPU_WORD_M1PE_SHIFT)
+#define MPU_BRD_WORD_M1PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M1PE_SHIFT))
+
+/*! @brief Set the M1PE field to a new value. */
+#define MPU_WR_WORD_M1PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1PE_MASK, MPU_WORD_M1PE(value)))
+#define MPU_BWR_WORD_M1PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M1PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2UM field. */
+#define MPU_RD_WORD_M2UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2UM_MASK) >> MPU_WORD_M2UM_SHIFT)
+#define MPU_BRD_WORD_M2UM(base, index, index2) (MPU_RD_WORD_M2UM(base, index, index2))
+
+/*! @brief Set the M2UM field to a new value. */
+#define MPU_WR_WORD_M2UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2UM_MASK, MPU_WORD_M2UM(value)))
+#define MPU_BWR_WORD_M2UM(base, index, index2, value) (MPU_WR_WORD_M2UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2SM field. */
+#define MPU_RD_WORD_M2SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2SM_MASK) >> MPU_WORD_M2SM_SHIFT)
+#define MPU_BRD_WORD_M2SM(base, index, index2) (MPU_RD_WORD_M2SM(base, index, index2))
+
+/*! @brief Set the M2SM field to a new value. */
+#define MPU_WR_WORD_M2SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2SM_MASK, MPU_WORD_M2SM(value)))
+#define MPU_BWR_WORD_M2SM(base, index, index2, value) (MPU_WR_WORD_M2SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field PIDMASK[23:16] (RW)
+ *
+ * Provides a masking capability so that multiple process identifiers can be
+ * included as part of the region hit determination. If a bit in PIDMASK is set,
+ * then the corresponding PID bit is ignored in the comparison. This field and PID
+ * are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
+ * more information on the handling of the PID and PIDMASK, see "Access Evaluation
+ * - Hit Determination."
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_PIDMASK field. */
+#define MPU_RD_WORD_PIDMASK(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_PIDMASK_MASK) >> MPU_WORD_PIDMASK_SHIFT)
+#define MPU_BRD_WORD_PIDMASK(base, index, index2) (MPU_RD_WORD_PIDMASK(base, index, index2))
+
+/*! @brief Set the PIDMASK field to a new value. */
+#define MPU_WR_WORD_PIDMASK(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_PIDMASK_MASK, MPU_WORD_PIDMASK(value)))
+#define MPU_BWR_WORD_PIDMASK(base, index, index2, value) (MPU_WR_WORD_PIDMASK(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2PE field. */
+#define MPU_RD_WORD_M2PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2PE_MASK) >> MPU_WORD_M2PE_SHIFT)
+#define MPU_BRD_WORD_M2PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M2PE_SHIFT))
+
+/*! @brief Set the M2PE field to a new value. */
+#define MPU_WR_WORD_M2PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2PE_MASK, MPU_WORD_M2PE(value)))
+#define MPU_BWR_WORD_M2PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M2PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in User mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0b000 - An attempted access of that mode may be terminated with an access
+ *     error (if not allowed by another descriptor) and the access not performed.
+ * - 0b001 - Allows the given access type to occur
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3UM field. */
+#define MPU_RD_WORD_M3UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3UM_MASK) >> MPU_WORD_M3UM_SHIFT)
+#define MPU_BRD_WORD_M3UM(base, index, index2) (MPU_RD_WORD_M3UM(base, index, index2))
+
+/*! @brief Set the M3UM field to a new value. */
+#define MPU_WR_WORD_M3UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3UM_MASK, MPU_WORD_M3UM(value)))
+#define MPU_BWR_WORD_M3UM(base, index, index2, value) (MPU_WR_WORD_M3UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 0b00 - r/w/x; read, write and execute allowed
+ * - 0b01 - r/x; read and execute allowed, but no write
+ * - 0b10 - r/w; read and write allowed, but no execute
+ * - 0b11 - Same as User mode defined in M3UM
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3SM field. */
+#define MPU_RD_WORD_M3SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3SM_MASK) >> MPU_WORD_M3SM_SHIFT)
+#define MPU_BRD_WORD_M3SM(base, index, index2) (MPU_RD_WORD_M3SM(base, index, index2))
+
+/*! @brief Set the M3SM field to a new value. */
+#define MPU_WR_WORD_M3SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3SM_MASK, MPU_WORD_M3SM(value)))
+#define MPU_BWR_WORD_M3SM(base, index, index2, value) (MPU_WR_WORD_M3SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the process identifier in the evaluation
+ * - 0b1 - Include the process identifier and mask (RGDn_WORD3) in the region
+ *     hit evaluation
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3PE field. */
+#define MPU_RD_WORD_M3PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3PE_MASK) >> MPU_WORD_M3PE_SHIFT)
+#define MPU_BRD_WORD_M3PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M3PE_SHIFT))
+
+/*! @brief Set the M3PE field to a new value. */
+#define MPU_WR_WORD_M3PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3PE_MASK, MPU_WORD_M3PE(value)))
+#define MPU_BWR_WORD_M3PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M3PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field PID[31:24] (RW)
+ *
+ * Specifies the process identifier that is included in the region hit
+ * determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
+ * field.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_PID field. */
+#define MPU_RD_WORD_PID(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_PID_MASK) >> MPU_WORD_PID_SHIFT)
+#define MPU_BRD_WORD_PID(base, index, index2) (MPU_RD_WORD_PID(base, index, index2))
+
+/*! @brief Set the PID field to a new value. */
+#define MPU_WR_WORD_PID(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_PID_MASK, MPU_WORD_PID(value)))
+#define MPU_BWR_WORD_PID(base, index, index2, value) (MPU_WR_WORD_PID(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 4 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M4WE field. */
+#define MPU_RD_WORD_M4WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M4WE_MASK) >> MPU_WORD_M4WE_SHIFT)
+#define MPU_BRD_WORD_M4WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4WE_SHIFT))
+
+/*! @brief Set the M4WE field to a new value. */
+#define MPU_WR_WORD_M4WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M4WE_MASK, MPU_WORD_M4WE(value)))
+#define MPU_BWR_WORD_M4WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 4 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M4RE field. */
+#define MPU_RD_WORD_M4RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M4RE_MASK) >> MPU_WORD_M4RE_SHIFT)
+#define MPU_BRD_WORD_M4RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4RE_SHIFT))
+
+/*! @brief Set the M4RE field to a new value. */
+#define MPU_WR_WORD_M4RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M4RE_MASK, MPU_WORD_M4RE(value)))
+#define MPU_BWR_WORD_M4RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 5 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M5WE field. */
+#define MPU_RD_WORD_M5WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M5WE_MASK) >> MPU_WORD_M5WE_SHIFT)
+#define MPU_BRD_WORD_M5WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5WE_SHIFT))
+
+/*! @brief Set the M5WE field to a new value. */
+#define MPU_WR_WORD_M5WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M5WE_MASK, MPU_WORD_M5WE(value)))
+#define MPU_BWR_WORD_M5WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 5 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M5RE field. */
+#define MPU_RD_WORD_M5RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M5RE_MASK) >> MPU_WORD_M5RE_SHIFT)
+#define MPU_BRD_WORD_M5RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5RE_SHIFT))
+
+/*! @brief Set the M5RE field to a new value. */
+#define MPU_WR_WORD_M5RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M5RE_MASK, MPU_WORD_M5RE(value)))
+#define MPU_BWR_WORD_M5RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 6 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M6WE field. */
+#define MPU_RD_WORD_M6WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M6WE_MASK) >> MPU_WORD_M6WE_SHIFT)
+#define MPU_BRD_WORD_M6WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6WE_SHIFT))
+
+/*! @brief Set the M6WE field to a new value. */
+#define MPU_WR_WORD_M6WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M6WE_MASK, MPU_WORD_M6WE(value)))
+#define MPU_BWR_WORD_M6WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 6 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M6RE field. */
+#define MPU_RD_WORD_M6RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M6RE_MASK) >> MPU_WORD_M6RE_SHIFT)
+#define MPU_BRD_WORD_M6RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6RE_SHIFT))
+
+/*! @brief Set the M6RE field to a new value. */
+#define MPU_WR_WORD_M6RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M6RE_MASK, MPU_WORD_M6RE(value)))
+#define MPU_BWR_WORD_M6RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 7 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M7WE field. */
+#define MPU_RD_WORD_M7WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M7WE_MASK) >> MPU_WORD_M7WE_SHIFT)
+#define MPU_BRD_WORD_M7WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7WE_SHIFT))
+
+/*! @brief Set the M7WE field to a new value. */
+#define MPU_WR_WORD_M7WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M7WE_MASK, MPU_WORD_M7WE(value)))
+#define MPU_BWR_WORD_M7WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 7 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M7RE field. */
+#define MPU_RD_WORD_M7RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M7RE_MASK) >> MPU_WORD_M7RE_SHIFT)
+#define MPU_BRD_WORD_M7RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7RE_SHIFT))
+
+/*! @brief Set the M7RE field to a new value. */
+#define MPU_WR_WORD_M7RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M7RE_MASK, MPU_WORD_M7RE(value)))
+#define MPU_BWR_WORD_M7RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_RGDAAC - Region Descriptor Alternate Access Control n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_RGDAAC - Region Descriptor Alternate Access Control n (RW)
+ *
+ * Reset value: 0x0061F7DFU
+ *
+ * Because software may adjust only the access controls within a region
+ * descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
+ * this 32-bit entity is available. Writing to this register does not affect the
+ * descriptor's valid bit.
+ */
+/*!
+ * @name Constants and macros for entire MPU_RGDAAC register
+ */
+/*@{*/
+#define MPU_RD_RGDAAC(base, index) (MPU_RGDAAC_REG(base, index))
+#define MPU_WR_RGDAAC(base, index, value) (MPU_RGDAAC_REG(base, index) = (value))
+#define MPU_RMW_RGDAAC(base, index, mask, value) (MPU_WR_RGDAAC(base, index, (MPU_RD_RGDAAC(base, index) & ~(mask)) | (value)))
+#define MPU_SET_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) |  (value)))
+#define MPU_CLR_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) & ~(value)))
+#define MPU_TOG_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_RGDAAC bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDAAC, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0UM field. */
+#define MPU_RD_RGDAAC_M0UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0UM_MASK) >> MPU_RGDAAC_M0UM_SHIFT)
+#define MPU_BRD_RGDAAC_M0UM(base, index) (MPU_RD_RGDAAC_M0UM(base, index))
+
+/*! @brief Set the M0UM field to a new value. */
+#define MPU_WR_RGDAAC_M0UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0UM_MASK, MPU_RGDAAC_M0UM(value)))
+#define MPU_BWR_RGDAAC_M0UM(base, index, value) (MPU_WR_RGDAAC_M0UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0SM field. */
+#define MPU_RD_RGDAAC_M0SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0SM_MASK) >> MPU_RGDAAC_M0SM_SHIFT)
+#define MPU_BRD_RGDAAC_M0SM(base, index) (MPU_RD_RGDAAC_M0SM(base, index))
+
+/*! @brief Set the M0SM field to a new value. */
+#define MPU_WR_RGDAAC_M0SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0SM_MASK, MPU_RGDAAC_M0SM(value)))
+#define MPU_BWR_RGDAAC_M0SM(base, index, value) (MPU_WR_RGDAAC_M0SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M0PE[5] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0PE field. */
+#define MPU_RD_RGDAAC_M0PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0PE_MASK) >> MPU_RGDAAC_M0PE_SHIFT)
+#define MPU_BRD_RGDAAC_M0PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M0PE_SHIFT))
+
+/*! @brief Set the M0PE field to a new value. */
+#define MPU_WR_RGDAAC_M0PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0PE_MASK, MPU_RGDAAC_M0PE(value)))
+#define MPU_BWR_RGDAAC_M0PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M0PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1UM field. */
+#define MPU_RD_RGDAAC_M1UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1UM_MASK) >> MPU_RGDAAC_M1UM_SHIFT)
+#define MPU_BRD_RGDAAC_M1UM(base, index) (MPU_RD_RGDAAC_M1UM(base, index))
+
+/*! @brief Set the M1UM field to a new value. */
+#define MPU_WR_RGDAAC_M1UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1UM_MASK, MPU_RGDAAC_M1UM(value)))
+#define MPU_BWR_RGDAAC_M1UM(base, index, value) (MPU_WR_RGDAAC_M1UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1SM field. */
+#define MPU_RD_RGDAAC_M1SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1SM_MASK) >> MPU_RGDAAC_M1SM_SHIFT)
+#define MPU_BRD_RGDAAC_M1SM(base, index) (MPU_RD_RGDAAC_M1SM(base, index))
+
+/*! @brief Set the M1SM field to a new value. */
+#define MPU_WR_RGDAAC_M1SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1SM_MASK, MPU_RGDAAC_M1SM(value)))
+#define MPU_BWR_RGDAAC_M1SM(base, index, value) (MPU_WR_RGDAAC_M1SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1PE field. */
+#define MPU_RD_RGDAAC_M1PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1PE_MASK) >> MPU_RGDAAC_M1PE_SHIFT)
+#define MPU_BRD_RGDAAC_M1PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M1PE_SHIFT))
+
+/*! @brief Set the M1PE field to a new value. */
+#define MPU_WR_RGDAAC_M1PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1PE_MASK, MPU_RGDAAC_M1PE(value)))
+#define MPU_BWR_RGDAAC_M1PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M1PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2UM field. */
+#define MPU_RD_RGDAAC_M2UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2UM_MASK) >> MPU_RGDAAC_M2UM_SHIFT)
+#define MPU_BRD_RGDAAC_M2UM(base, index) (MPU_RD_RGDAAC_M2UM(base, index))
+
+/*! @brief Set the M2UM field to a new value. */
+#define MPU_WR_RGDAAC_M2UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2UM_MASK, MPU_RGDAAC_M2UM(value)))
+#define MPU_BWR_RGDAAC_M2UM(base, index, value) (MPU_WR_RGDAAC_M2UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2SM field. */
+#define MPU_RD_RGDAAC_M2SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2SM_MASK) >> MPU_RGDAAC_M2SM_SHIFT)
+#define MPU_BRD_RGDAAC_M2SM(base, index) (MPU_RD_RGDAAC_M2SM(base, index))
+
+/*! @brief Set the M2SM field to a new value. */
+#define MPU_WR_RGDAAC_M2SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2SM_MASK, MPU_RGDAAC_M2SM(value)))
+#define MPU_BWR_RGDAAC_M2SM(base, index, value) (MPU_WR_RGDAAC_M2SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2PE field. */
+#define MPU_RD_RGDAAC_M2PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2PE_MASK) >> MPU_RGDAAC_M2PE_SHIFT)
+#define MPU_BRD_RGDAAC_M2PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M2PE_SHIFT))
+
+/*! @brief Set the M2PE field to a new value. */
+#define MPU_WR_RGDAAC_M2PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2PE_MASK, MPU_RGDAAC_M2PE(value)))
+#define MPU_BWR_RGDAAC_M2PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M2PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in user mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0b000 - An attempted access of that mode may be terminated with an access
+ *     error (if not allowed by another descriptor) and the access not performed.
+ * - 0b001 - Allows the given access type to occur
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3UM field. */
+#define MPU_RD_RGDAAC_M3UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3UM_MASK) >> MPU_RGDAAC_M3UM_SHIFT)
+#define MPU_BRD_RGDAAC_M3UM(base, index) (MPU_RD_RGDAAC_M3UM(base, index))
+
+/*! @brief Set the M3UM field to a new value. */
+#define MPU_WR_RGDAAC_M3UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3UM_MASK, MPU_RGDAAC_M3UM(value)))
+#define MPU_BWR_RGDAAC_M3UM(base, index, value) (MPU_WR_RGDAAC_M3UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 0b00 - r/w/x; read, write and execute allowed
+ * - 0b01 - r/x; read and execute allowed, but no write
+ * - 0b10 - r/w; read and write allowed, but no execute
+ * - 0b11 - Same as User mode defined in M3UM
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3SM field. */
+#define MPU_RD_RGDAAC_M3SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3SM_MASK) >> MPU_RGDAAC_M3SM_SHIFT)
+#define MPU_BRD_RGDAAC_M3SM(base, index) (MPU_RD_RGDAAC_M3SM(base, index))
+
+/*! @brief Set the M3SM field to a new value. */
+#define MPU_WR_RGDAAC_M3SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3SM_MASK, MPU_RGDAAC_M3SM(value)))
+#define MPU_BWR_RGDAAC_M3SM(base, index, value) (MPU_WR_RGDAAC_M3SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the process identifier in the evaluation
+ * - 0b1 - Include the process identifier and mask (RGDn.RGDAAC) in the region
+ *     hit evaluation
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3PE field. */
+#define MPU_RD_RGDAAC_M3PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3PE_MASK) >> MPU_RGDAAC_M3PE_SHIFT)
+#define MPU_BRD_RGDAAC_M3PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M3PE_SHIFT))
+
+/*! @brief Set the M3PE field to a new value. */
+#define MPU_WR_RGDAAC_M3PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3PE_MASK, MPU_RGDAAC_M3PE(value)))
+#define MPU_BWR_RGDAAC_M3PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M3PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 4 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M4WE field. */
+#define MPU_RD_RGDAAC_M4WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M4WE_MASK) >> MPU_RGDAAC_M4WE_SHIFT)
+#define MPU_BRD_RGDAAC_M4WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4WE_SHIFT))
+
+/*! @brief Set the M4WE field to a new value. */
+#define MPU_WR_RGDAAC_M4WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M4WE_MASK, MPU_RGDAAC_M4WE(value)))
+#define MPU_BWR_RGDAAC_M4WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 4 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M4RE field. */
+#define MPU_RD_RGDAAC_M4RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M4RE_MASK) >> MPU_RGDAAC_M4RE_SHIFT)
+#define MPU_BRD_RGDAAC_M4RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4RE_SHIFT))
+
+/*! @brief Set the M4RE field to a new value. */
+#define MPU_WR_RGDAAC_M4RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M4RE_MASK, MPU_RGDAAC_M4RE(value)))
+#define MPU_BWR_RGDAAC_M4RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 5 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M5WE field. */
+#define MPU_RD_RGDAAC_M5WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M5WE_MASK) >> MPU_RGDAAC_M5WE_SHIFT)
+#define MPU_BRD_RGDAAC_M5WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5WE_SHIFT))
+
+/*! @brief Set the M5WE field to a new value. */
+#define MPU_WR_RGDAAC_M5WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M5WE_MASK, MPU_RGDAAC_M5WE(value)))
+#define MPU_BWR_RGDAAC_M5WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 5 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M5RE field. */
+#define MPU_RD_RGDAAC_M5RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M5RE_MASK) >> MPU_RGDAAC_M5RE_SHIFT)
+#define MPU_BRD_RGDAAC_M5RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5RE_SHIFT))
+
+/*! @brief Set the M5RE field to a new value. */
+#define MPU_WR_RGDAAC_M5RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M5RE_MASK, MPU_RGDAAC_M5RE(value)))
+#define MPU_BWR_RGDAAC_M5RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 6 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M6WE field. */
+#define MPU_RD_RGDAAC_M6WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M6WE_MASK) >> MPU_RGDAAC_M6WE_SHIFT)
+#define MPU_BRD_RGDAAC_M6WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6WE_SHIFT))
+
+/*! @brief Set the M6WE field to a new value. */
+#define MPU_WR_RGDAAC_M6WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M6WE_MASK, MPU_RGDAAC_M6WE(value)))
+#define MPU_BWR_RGDAAC_M6WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 6 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M6RE field. */
+#define MPU_RD_RGDAAC_M6RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M6RE_MASK) >> MPU_RGDAAC_M6RE_SHIFT)
+#define MPU_BRD_RGDAAC_M6RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6RE_SHIFT))
+
+/*! @brief Set the M6RE field to a new value. */
+#define MPU_WR_RGDAAC_M6RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M6RE_MASK, MPU_RGDAAC_M6RE(value)))
+#define MPU_BWR_RGDAAC_M6RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 7 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M7WE field. */
+#define MPU_RD_RGDAAC_M7WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M7WE_MASK) >> MPU_RGDAAC_M7WE_SHIFT)
+#define MPU_BRD_RGDAAC_M7WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7WE_SHIFT))
+
+/*! @brief Set the M7WE field to a new value. */
+#define MPU_WR_RGDAAC_M7WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M7WE_MASK, MPU_RGDAAC_M7WE(value)))
+#define MPU_BWR_RGDAAC_M7WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 7 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M7RE field. */
+#define MPU_RD_RGDAAC_M7RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M7RE_MASK) >> MPU_RGDAAC_M7RE_SHIFT)
+#define MPU_BRD_RGDAAC_M7RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7RE_SHIFT))
+
+/*! @brief Set the M7RE field to a new value. */
+#define MPU_WR_RGDAAC_M7RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M7RE_MASK, MPU_RGDAAC_M7RE(value)))
+#define MPU_BWR_RGDAAC_M7RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7RE_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 NV
+ *
+ * Flash configuration field
+ *
+ * Registers defined in this header file:
+ * - NV_BACKKEY3 - Backdoor Comparison Key 3.
+ * - NV_BACKKEY2 - Backdoor Comparison Key 2.
+ * - NV_BACKKEY1 - Backdoor Comparison Key 1.
+ * - NV_BACKKEY0 - Backdoor Comparison Key 0.
+ * - NV_BACKKEY7 - Backdoor Comparison Key 7.
+ * - NV_BACKKEY6 - Backdoor Comparison Key 6.
+ * - NV_BACKKEY5 - Backdoor Comparison Key 5.
+ * - NV_BACKKEY4 - Backdoor Comparison Key 4.
+ * - NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ * - NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ * - NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ * - NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ * - NV_FSEC - Non-volatile Flash Security Register
+ * - NV_FOPT - Non-volatile Flash Option Register
+ * - NV_FEPROT - Non-volatile EERAM Protection Register
+ * - NV_FDPROT - Non-volatile D-Flash Protection Register
+ */
+
+#define NV_INSTANCE_COUNT (1U) /*!< Number of instances of the NV module. */
+#define FTFE_FlashConfig_IDX (0U) /*!< Instance number for FTFE_FlashConfig. */
+
+/*******************************************************************************
+ * NV_BACKKEY3 - Backdoor Comparison Key 3.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY3 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY3(base)     (NV_BACKKEY3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY2 - Backdoor Comparison Key 2.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY2 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY2(base)     (NV_BACKKEY2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY1 - Backdoor Comparison Key 1.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY1 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY1(base)     (NV_BACKKEY1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY0 - Backdoor Comparison Key 0.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY0 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY0(base)     (NV_BACKKEY0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY7 - Backdoor Comparison Key 7.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY7 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY7(base)     (NV_BACKKEY7_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY6 - Backdoor Comparison Key 6.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY6 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY6(base)     (NV_BACKKEY6_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY5 - Backdoor Comparison Key 5.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY5 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY5(base)     (NV_BACKKEY5_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY4 - Backdoor Comparison Key 4.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY4 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY4(base)     (NV_BACKKEY4_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT3 register
+ */
+/*@{*/
+#define NV_RD_FPROT3(base)       (NV_FPROT3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT2 register
+ */
+/*@{*/
+#define NV_RD_FPROT2(base)       (NV_FPROT2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT1 register
+ */
+/*@{*/
+#define NV_RD_FPROT1(base)       (NV_FPROT1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT0 register
+ */
+/*@{*/
+#define NV_RD_FPROT0(base)       (NV_FPROT0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FSEC - Non-volatile Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FSEC - Non-volatile Flash Security Register (RO)
+ *
+ * Reset value: 0xFFU
+ *
+ * Allows the user to customize the operation of the MCU at boot time
+ */
+/*!
+ * @name Constants and macros for entire NV_FSEC register
+ */
+/*@{*/
+#define NV_RD_FSEC(base)         (NV_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FSEC bitfields
+ */
+
+/*!
+ * @name Register NV_FSEC, field SEC[1:0] (RO)
+ *
+ * Values:
+ * - 0b10 - MCU security status is unsecure
+ * - 0b11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_SEC field. */
+#define NV_RD_FSEC_SEC(base) ((NV_FSEC_REG(base) & NV_FSEC_SEC_MASK) >> NV_FSEC_SEC_SHIFT)
+#define NV_BRD_FSEC_SEC(base) (NV_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field FSLACC[3:2] (RO)
+ *
+ * Values:
+ * - 0b10 - Freescale factory access denied
+ * - 0b11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_FSLACC field. */
+#define NV_RD_FSEC_FSLACC(base) ((NV_FSEC_REG(base) & NV_FSEC_FSLACC_MASK) >> NV_FSEC_FSLACC_SHIFT)
+#define NV_BRD_FSEC_FSLACC(base) (NV_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field MEEN[5:4] (RO)
+ *
+ * Values:
+ * - 0b10 - Mass erase is disabled
+ * - 0b11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_MEEN field. */
+#define NV_RD_FSEC_MEEN(base) ((NV_FSEC_REG(base) & NV_FSEC_MEEN_MASK) >> NV_FSEC_MEEN_SHIFT)
+#define NV_BRD_FSEC_MEEN(base) (NV_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field KEYEN[7:6] (RO)
+ *
+ * Values:
+ * - 0b10 - Backdoor key access enabled
+ * - 0b11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_KEYEN field. */
+#define NV_RD_FSEC_KEYEN(base) ((NV_FSEC_REG(base) & NV_FSEC_KEYEN_MASK) >> NV_FSEC_KEYEN_SHIFT)
+#define NV_BRD_FSEC_KEYEN(base) (NV_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FOPT - Non-volatile Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FOPT - Non-volatile Flash Option Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FOPT register
+ */
+/*@{*/
+#define NV_RD_FOPT(base)         (NV_FOPT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FOPT bitfields
+ */
+
+/*!
+ * @name Register NV_FOPT, field LPBOOT[0] (RO)
+ *
+ * Values:
+ * - 0b0 - Low-power boot
+ * - 0b1 - Normal boot
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_LPBOOT field. */
+#define NV_RD_FOPT_LPBOOT(base) ((NV_FOPT_REG(base) & NV_FOPT_LPBOOT_MASK) >> NV_FOPT_LPBOOT_SHIFT)
+#define NV_BRD_FOPT_LPBOOT(base) (BITBAND_ACCESS8(&NV_FOPT_REG(base), NV_FOPT_LPBOOT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register NV_FOPT, field EZPORT_DIS[1] (RO)
+ *
+ * Values:
+ * - 0b0 - EzPort operation is disabled
+ * - 0b1 - EzPort operation is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_EZPORT_DIS field. */
+#define NV_RD_FOPT_EZPORT_DIS(base) ((NV_FOPT_REG(base) & NV_FOPT_EZPORT_DIS_MASK) >> NV_FOPT_EZPORT_DIS_SHIFT)
+#define NV_BRD_FOPT_EZPORT_DIS(base) (BITBAND_ACCESS8(&NV_FOPT_REG(base), NV_FOPT_EZPORT_DIS_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FEPROT - Non-volatile EERAM Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FEPROT - Non-volatile EERAM Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FEPROT register
+ */
+/*@{*/
+#define NV_RD_FEPROT(base)       (NV_FEPROT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FDPROT - Non-volatile D-Flash Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FDPROT - Non-volatile D-Flash Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FDPROT register
+ */
+/*@{*/
+#define NV_RD_FDPROT(base)       (NV_FDPROT_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 OSC
+ *
+ * Oscillator
+ *
+ * Registers defined in this header file:
+ * - OSC_CR - OSC Control Register
+ */
+
+#define OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */
+#define OSC_IDX (0U) /*!< Instance number for OSC. */
+
+/*******************************************************************************
+ * OSC_CR - OSC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief OSC_CR - OSC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * After OSC is enabled and starts generating the clocks, the configurations
+ * such as low power and frequency range, must not be changed.
+ */
+/*!
+ * @name Constants and macros for entire OSC_CR register
+ */
+/*@{*/
+#define OSC_RD_CR(base)          (OSC_CR_REG(base))
+#define OSC_WR_CR(base, value)   (OSC_CR_REG(base) = (value))
+#define OSC_RMW_CR(base, mask, value) (OSC_WR_CR(base, (OSC_RD_CR(base) & ~(mask)) | (value)))
+#define OSC_SET_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) |  (value)))
+#define OSC_CLR_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) & ~(value)))
+#define OSC_TOG_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual OSC_CR bitfields
+ */
+
+/*!
+ * @name Register OSC_CR, field SC16P[0] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 16 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC16P field. */
+#define OSC_RD_CR_SC16P(base) ((OSC_CR_REG(base) & OSC_CR_SC16P_MASK) >> OSC_CR_SC16P_SHIFT)
+#define OSC_BRD_CR_SC16P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT))
+
+/*! @brief Set the SC16P field to a new value. */
+#define OSC_WR_CR_SC16P(base, value) (OSC_RMW_CR(base, OSC_CR_SC16P_MASK, OSC_CR_SC16P(value)))
+#define OSC_BWR_CR_SC16P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC8P[1] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 8 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC8P field. */
+#define OSC_RD_CR_SC8P(base) ((OSC_CR_REG(base) & OSC_CR_SC8P_MASK) >> OSC_CR_SC8P_SHIFT)
+#define OSC_BRD_CR_SC8P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT))
+
+/*! @brief Set the SC8P field to a new value. */
+#define OSC_WR_CR_SC8P(base, value) (OSC_RMW_CR(base, OSC_CR_SC8P_MASK, OSC_CR_SC8P(value)))
+#define OSC_BWR_CR_SC8P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC4P[2] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 4 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC4P field. */
+#define OSC_RD_CR_SC4P(base) ((OSC_CR_REG(base) & OSC_CR_SC4P_MASK) >> OSC_CR_SC4P_SHIFT)
+#define OSC_BRD_CR_SC4P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT))
+
+/*! @brief Set the SC4P field to a new value. */
+#define OSC_WR_CR_SC4P(base, value) (OSC_RMW_CR(base, OSC_CR_SC4P_MASK, OSC_CR_SC4P(value)))
+#define OSC_BWR_CR_SC4P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC2P[3] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 2 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC2P field. */
+#define OSC_RD_CR_SC2P(base) ((OSC_CR_REG(base) & OSC_CR_SC2P_MASK) >> OSC_CR_SC2P_SHIFT)
+#define OSC_BRD_CR_SC2P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT))
+
+/*! @brief Set the SC2P field to a new value. */
+#define OSC_WR_CR_SC2P(base, value) (OSC_RMW_CR(base, OSC_CR_SC2P_MASK, OSC_CR_SC2P(value)))
+#define OSC_BWR_CR_SC2P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field EREFSTEN[5] (RW)
+ *
+ * Controls whether or not the external reference clock (OSCERCLK) remains
+ * enabled when MCU enters Stop mode.
+ *
+ * Values:
+ * - 0b0 - External reference clock is disabled in Stop mode.
+ * - 0b1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
+ *     before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_EREFSTEN field. */
+#define OSC_RD_CR_EREFSTEN(base) ((OSC_CR_REG(base) & OSC_CR_EREFSTEN_MASK) >> OSC_CR_EREFSTEN_SHIFT)
+#define OSC_BRD_CR_EREFSTEN(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT))
+
+/*! @brief Set the EREFSTEN field to a new value. */
+#define OSC_WR_CR_EREFSTEN(base, value) (OSC_RMW_CR(base, OSC_CR_EREFSTEN_MASK, OSC_CR_EREFSTEN(value)))
+#define OSC_BWR_CR_EREFSTEN(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field ERCLKEN[7] (RW)
+ *
+ * Enables external reference clock (OSCERCLK).
+ *
+ * Values:
+ * - 0b0 - External reference clock is inactive.
+ * - 0b1 - External reference clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_ERCLKEN field. */
+#define OSC_RD_CR_ERCLKEN(base) ((OSC_CR_REG(base) & OSC_CR_ERCLKEN_MASK) >> OSC_CR_ERCLKEN_SHIFT)
+#define OSC_BRD_CR_ERCLKEN(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT))
+
+/*! @brief Set the ERCLKEN field to a new value. */
+#define OSC_WR_CR_ERCLKEN(base, value) (OSC_RMW_CR(base, OSC_CR_ERCLKEN_MASK, OSC_CR_ERCLKEN(value)))
+#define OSC_BWR_CR_ERCLKEN(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PDB
+ *
+ * Programmable Delay Block
+ *
+ * Registers defined in this header file:
+ * - PDB_SC - Status and Control register
+ * - PDB_MOD - Modulus register
+ * - PDB_CNT - Counter register
+ * - PDB_IDLY - Interrupt Delay register
+ * - PDB_C1 - Channel n Control register 1
+ * - PDB_S - Channel n Status register
+ * - PDB_DLY - Channel n Delay 0 register
+ * - PDB_INTC - DAC Interval Trigger n Control register
+ * - PDB_INT - DAC Interval n register
+ * - PDB_POEN - Pulse-Out n Enable register
+ * - PDB_PODLY - Pulse-Out n Delay register
+ */
+
+#define PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */
+#define PDB0_IDX (0U) /*!< Instance number for PDB0. */
+
+/*******************************************************************************
+ * PDB_SC - Status and Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_SC - Status and Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_SC register
+ */
+/*@{*/
+#define PDB_RD_SC(base)          (PDB_SC_REG(base))
+#define PDB_WR_SC(base, value)   (PDB_SC_REG(base) = (value))
+#define PDB_RMW_SC(base, mask, value) (PDB_WR_SC(base, (PDB_RD_SC(base) & ~(mask)) | (value)))
+#define PDB_SET_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) |  (value)))
+#define PDB_CLR_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) & ~(value)))
+#define PDB_TOG_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_SC bitfields
+ */
+
+/*!
+ * @name Register PDB_SC, field LDOK[0] (RW)
+ *
+ * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
+ * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
+ * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
+ * written to the LDOK field, the values in the buffers of above registers are
+ * not effective and the buffers cannot be written until the values in buffers are
+ * loaded into their internal registers. LDOK can be written only when PDBEN is
+ * set or it can be written at the same time with PDBEN being written to 1. It is
+ * automatically cleared when the values in buffers are loaded into the internal
+ * registers or the PDBEN is cleared. Writing 0 to it has no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_LDOK field. */
+#define PDB_RD_SC_LDOK(base) ((PDB_SC_REG(base) & PDB_SC_LDOK_MASK) >> PDB_SC_LDOK_SHIFT)
+#define PDB_BRD_SC_LDOK(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_LDOK_SHIFT))
+
+/*! @brief Set the LDOK field to a new value. */
+#define PDB_WR_SC_LDOK(base, value) (PDB_RMW_SC(base, PDB_SC_LDOK_MASK, PDB_SC_LDOK(value)))
+#define PDB_BWR_SC_LDOK(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_LDOK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field CONT[1] (RW)
+ *
+ * Enables the PDB operation in Continuous mode.
+ *
+ * Values:
+ * - 0b0 - PDB operation in One-Shot mode
+ * - 0b1 - PDB operation in Continuous mode
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_CONT field. */
+#define PDB_RD_SC_CONT(base) ((PDB_SC_REG(base) & PDB_SC_CONT_MASK) >> PDB_SC_CONT_SHIFT)
+#define PDB_BRD_SC_CONT(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_CONT_SHIFT))
+
+/*! @brief Set the CONT field to a new value. */
+#define PDB_WR_SC_CONT(base, value) (PDB_RMW_SC(base, PDB_SC_CONT_MASK, PDB_SC_CONT(value)))
+#define PDB_BWR_SC_CONT(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_CONT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field MULT[3:2] (RW)
+ *
+ * Selects the multiplication factor of the prescaler divider for the counter
+ * clock.
+ *
+ * Values:
+ * - 0b00 - Multiplication factor is 1.
+ * - 0b01 - Multiplication factor is 10.
+ * - 0b10 - Multiplication factor is 20.
+ * - 0b11 - Multiplication factor is 40.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_MULT field. */
+#define PDB_RD_SC_MULT(base) ((PDB_SC_REG(base) & PDB_SC_MULT_MASK) >> PDB_SC_MULT_SHIFT)
+#define PDB_BRD_SC_MULT(base) (PDB_RD_SC_MULT(base))
+
+/*! @brief Set the MULT field to a new value. */
+#define PDB_WR_SC_MULT(base, value) (PDB_RMW_SC(base, PDB_SC_MULT_MASK, PDB_SC_MULT(value)))
+#define PDB_BWR_SC_MULT(base, value) (PDB_WR_SC_MULT(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBIE[5] (RW)
+ *
+ * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
+ * generates a PDB interrupt.
+ *
+ * Values:
+ * - 0b0 - PDB interrupt disabled.
+ * - 0b1 - PDB interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBIE field. */
+#define PDB_RD_SC_PDBIE(base) ((PDB_SC_REG(base) & PDB_SC_PDBIE_MASK) >> PDB_SC_PDBIE_SHIFT)
+#define PDB_BRD_SC_PDBIE(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIE_SHIFT))
+
+/*! @brief Set the PDBIE field to a new value. */
+#define PDB_WR_SC_PDBIE(base, value) (PDB_RMW_SC(base, PDB_SC_PDBIE_MASK, PDB_SC_PDBIE(value)))
+#define PDB_BWR_SC_PDBIE(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBIF[6] (RW)
+ *
+ * This field is set when the counter value is equal to the IDLY register.
+ * Writing zero clears this field.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBIF field. */
+#define PDB_RD_SC_PDBIF(base) ((PDB_SC_REG(base) & PDB_SC_PDBIF_MASK) >> PDB_SC_PDBIF_SHIFT)
+#define PDB_BRD_SC_PDBIF(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIF_SHIFT))
+
+/*! @brief Set the PDBIF field to a new value. */
+#define PDB_WR_SC_PDBIF(base, value) (PDB_RMW_SC(base, PDB_SC_PDBIF_MASK, PDB_SC_PDBIF(value)))
+#define PDB_BWR_SC_PDBIF(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - PDB disabled. Counter is off.
+ * - 0b1 - PDB enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBEN field. */
+#define PDB_RD_SC_PDBEN(base) ((PDB_SC_REG(base) & PDB_SC_PDBEN_MASK) >> PDB_SC_PDBEN_SHIFT)
+#define PDB_BRD_SC_PDBEN(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEN_SHIFT))
+
+/*! @brief Set the PDBEN field to a new value. */
+#define PDB_WR_SC_PDBEN(base, value) (PDB_RMW_SC(base, PDB_SC_PDBEN_MASK, PDB_SC_PDBEN(value)))
+#define PDB_BWR_SC_PDBEN(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field TRGSEL[11:8] (RW)
+ *
+ * Selects the trigger input source for the PDB. The trigger input source can be
+ * internal or external (EXTRG pin), or the software trigger. Refer to chip
+ * configuration details for the actual PDB input trigger connections.
+ *
+ * Values:
+ * - 0b0000 - Trigger-In 0 is selected.
+ * - 0b0001 - Trigger-In 1 is selected.
+ * - 0b0010 - Trigger-In 2 is selected.
+ * - 0b0011 - Trigger-In 3 is selected.
+ * - 0b0100 - Trigger-In 4 is selected.
+ * - 0b0101 - Trigger-In 5 is selected.
+ * - 0b0110 - Trigger-In 6 is selected.
+ * - 0b0111 - Trigger-In 7 is selected.
+ * - 0b1000 - Trigger-In 8 is selected.
+ * - 0b1001 - Trigger-In 9 is selected.
+ * - 0b1010 - Trigger-In 10 is selected.
+ * - 0b1011 - Trigger-In 11 is selected.
+ * - 0b1100 - Trigger-In 12 is selected.
+ * - 0b1101 - Trigger-In 13 is selected.
+ * - 0b1110 - Trigger-In 14 is selected.
+ * - 0b1111 - Software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_TRGSEL field. */
+#define PDB_RD_SC_TRGSEL(base) ((PDB_SC_REG(base) & PDB_SC_TRGSEL_MASK) >> PDB_SC_TRGSEL_SHIFT)
+#define PDB_BRD_SC_TRGSEL(base) (PDB_RD_SC_TRGSEL(base))
+
+/*! @brief Set the TRGSEL field to a new value. */
+#define PDB_WR_SC_TRGSEL(base, value) (PDB_RMW_SC(base, PDB_SC_TRGSEL_MASK, PDB_SC_TRGSEL(value)))
+#define PDB_BWR_SC_TRGSEL(base, value) (PDB_WR_SC_TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PRESCALER[14:12] (RW)
+ *
+ * Values:
+ * - 0b000 - Counting uses the peripheral clock divided by multiplication factor
+ *     selected by MULT.
+ * - 0b001 - Counting uses the peripheral clock divided by twice of the
+ *     multiplication factor selected by MULT.
+ * - 0b010 - Counting uses the peripheral clock divided by four times of the
+ *     multiplication factor selected by MULT.
+ * - 0b011 - Counting uses the peripheral clock divided by eight times of the
+ *     multiplication factor selected by MULT.
+ * - 0b100 - Counting uses the peripheral clock divided by 16 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b101 - Counting uses the peripheral clock divided by 32 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b110 - Counting uses the peripheral clock divided by 64 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b111 - Counting uses the peripheral clock divided by 128 times of the
+ *     multiplication factor selected by MULT.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PRESCALER field. */
+#define PDB_RD_SC_PRESCALER(base) ((PDB_SC_REG(base) & PDB_SC_PRESCALER_MASK) >> PDB_SC_PRESCALER_SHIFT)
+#define PDB_BRD_SC_PRESCALER(base) (PDB_RD_SC_PRESCALER(base))
+
+/*! @brief Set the PRESCALER field to a new value. */
+#define PDB_WR_SC_PRESCALER(base, value) (PDB_RMW_SC(base, PDB_SC_PRESCALER_MASK, PDB_SC_PRESCALER(value)))
+#define PDB_BWR_SC_PRESCALER(base, value) (PDB_WR_SC_PRESCALER(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field DMAEN[15] (RW)
+ *
+ * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
+ * interrupt.
+ *
+ * Values:
+ * - 0b0 - DMA disabled.
+ * - 0b1 - DMA enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_DMAEN field. */
+#define PDB_RD_SC_DMAEN(base) ((PDB_SC_REG(base) & PDB_SC_DMAEN_MASK) >> PDB_SC_DMAEN_SHIFT)
+#define PDB_BRD_SC_DMAEN(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define PDB_WR_SC_DMAEN(base, value) (PDB_RMW_SC(base, PDB_SC_DMAEN_MASK, PDB_SC_DMAEN(value)))
+#define PDB_BWR_SC_DMAEN(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field SWTRIG[16] (WORZ)
+ *
+ * When PDB is enabled and the software trigger is selected as the trigger input
+ * source, writing 1 to this field resets and restarts the counter. Writing 0 to
+ * this field has no effect. Reading this field results 0.
+ */
+/*@{*/
+/*! @brief Set the SWTRIG field to a new value. */
+#define PDB_WR_SC_SWTRIG(base, value) (PDB_RMW_SC(base, PDB_SC_SWTRIG_MASK, PDB_SC_SWTRIG(value)))
+#define PDB_BWR_SC_SWTRIG(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_SWTRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBEIE[17] (RW)
+ *
+ * Enables the PDB sequence error interrupt. When this field is set, any of the
+ * PDB channel sequence error flags generates a PDB sequence error interrupt.
+ *
+ * Values:
+ * - 0b0 - PDB sequence error interrupt disabled.
+ * - 0b1 - PDB sequence error interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBEIE field. */
+#define PDB_RD_SC_PDBEIE(base) ((PDB_SC_REG(base) & PDB_SC_PDBEIE_MASK) >> PDB_SC_PDBEIE_SHIFT)
+#define PDB_BRD_SC_PDBEIE(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEIE_SHIFT))
+
+/*! @brief Set the PDBEIE field to a new value. */
+#define PDB_WR_SC_PDBEIE(base, value) (PDB_RMW_SC(base, PDB_SC_PDBEIE_MASK, PDB_SC_PDBEIE(value)))
+#define PDB_BWR_SC_PDBEIE(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field LDMOD[19:18] (RW)
+ *
+ * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
+ * after 1 is written to LDOK.
+ *
+ * Values:
+ * - 0b00 - The internal registers are loaded with the values from their buffers
+ *     immediately after 1 is written to LDOK.
+ * - 0b01 - The internal registers are loaded with the values from their buffers
+ *     when the PDB counter reaches the MOD register value after 1 is written to
+ *     LDOK.
+ * - 0b10 - The internal registers are loaded with the values from their buffers
+ *     when a trigger input event is detected after 1 is written to LDOK.
+ * - 0b11 - The internal registers are loaded with the values from their buffers
+ *     when either the PDB counter reaches the MOD register value or a trigger
+ *     input event is detected, after 1 is written to LDOK.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_LDMOD field. */
+#define PDB_RD_SC_LDMOD(base) ((PDB_SC_REG(base) & PDB_SC_LDMOD_MASK) >> PDB_SC_LDMOD_SHIFT)
+#define PDB_BRD_SC_LDMOD(base) (PDB_RD_SC_LDMOD(base))
+
+/*! @brief Set the LDMOD field to a new value. */
+#define PDB_WR_SC_LDMOD(base, value) (PDB_RMW_SC(base, PDB_SC_LDMOD_MASK, PDB_SC_LDMOD(value)))
+#define PDB_BWR_SC_LDMOD(base, value) (PDB_WR_SC_LDMOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_MOD - Modulus register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_MOD - Modulus register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+/*!
+ * @name Constants and macros for entire PDB_MOD register
+ */
+/*@{*/
+#define PDB_RD_MOD(base)         (PDB_MOD_REG(base))
+#define PDB_WR_MOD(base, value)  (PDB_MOD_REG(base) = (value))
+#define PDB_RMW_MOD(base, mask, value) (PDB_WR_MOD(base, (PDB_RD_MOD(base) & ~(mask)) | (value)))
+#define PDB_SET_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) |  (value)))
+#define PDB_CLR_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) & ~(value)))
+#define PDB_TOG_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_MOD bitfields
+ */
+
+/*!
+ * @name Register PDB_MOD, field MOD[15:0] (RW)
+ *
+ * Specifies the period of the counter. When the counter reaches this value, it
+ * will be reset back to zero. If the PDB is in Continuous mode, the count begins
+ * anew. Reading this field returns the value of the internal register that is
+ * effective for the current cycle of PDB.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_MOD_MOD field. */
+#define PDB_RD_MOD_MOD(base) ((PDB_MOD_REG(base) & PDB_MOD_MOD_MASK) >> PDB_MOD_MOD_SHIFT)
+#define PDB_BRD_MOD_MOD(base) (PDB_RD_MOD_MOD(base))
+
+/*! @brief Set the MOD field to a new value. */
+#define PDB_WR_MOD_MOD(base, value) (PDB_RMW_MOD(base, PDB_MOD_MOD_MASK, PDB_MOD_MOD(value)))
+#define PDB_BWR_MOD_MOD(base, value) (PDB_WR_MOD_MOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_CNT - Counter register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_CNT - Counter register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_CNT register
+ */
+/*@{*/
+#define PDB_RD_CNT(base)         (PDB_CNT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_CNT bitfields
+ */
+
+/*!
+ * @name Register PDB_CNT, field CNT[15:0] (RO)
+ *
+ * Contains the current value of the counter.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_CNT_CNT field. */
+#define PDB_RD_CNT_CNT(base) ((PDB_CNT_REG(base) & PDB_CNT_CNT_MASK) >> PDB_CNT_CNT_SHIFT)
+#define PDB_BRD_CNT_CNT(base) (PDB_RD_CNT_CNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_IDLY - Interrupt Delay register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_IDLY - Interrupt Delay register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+/*!
+ * @name Constants and macros for entire PDB_IDLY register
+ */
+/*@{*/
+#define PDB_RD_IDLY(base)        (PDB_IDLY_REG(base))
+#define PDB_WR_IDLY(base, value) (PDB_IDLY_REG(base) = (value))
+#define PDB_RMW_IDLY(base, mask, value) (PDB_WR_IDLY(base, (PDB_RD_IDLY(base) & ~(mask)) | (value)))
+#define PDB_SET_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) |  (value)))
+#define PDB_CLR_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) & ~(value)))
+#define PDB_TOG_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_IDLY bitfields
+ */
+
+/*!
+ * @name Register PDB_IDLY, field IDLY[15:0] (RW)
+ *
+ * Specifies the delay value to schedule the PDB interrupt. It can be used to
+ * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
+ * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
+ * this field returns the value of internal register that is effective for the
+ * current cycle of the PDB.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_IDLY_IDLY field. */
+#define PDB_RD_IDLY_IDLY(base) ((PDB_IDLY_REG(base) & PDB_IDLY_IDLY_MASK) >> PDB_IDLY_IDLY_SHIFT)
+#define PDB_BRD_IDLY_IDLY(base) (PDB_RD_IDLY_IDLY(base))
+
+/*! @brief Set the IDLY field to a new value. */
+#define PDB_WR_IDLY_IDLY(base, value) (PDB_RMW_IDLY(base, PDB_IDLY_IDLY_MASK, PDB_IDLY_IDLY(value)))
+#define PDB_BWR_IDLY_IDLY(base, value) (PDB_WR_IDLY_IDLY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_C1 - Channel n Control register 1
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_C1 - Channel n Control register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PDB channel has one control register, CHnC1. The bits in this register
+ * control the functionality of each PDB channel operation.
+ */
+/*!
+ * @name Constants and macros for entire PDB_C1 register
+ */
+/*@{*/
+#define PDB_RD_C1(base, index)   (PDB_C1_REG(base, index))
+#define PDB_WR_C1(base, index, value) (PDB_C1_REG(base, index) = (value))
+#define PDB_RMW_C1(base, index, mask, value) (PDB_WR_C1(base, index, (PDB_RD_C1(base, index) & ~(mask)) | (value)))
+#define PDB_SET_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) |  (value)))
+#define PDB_CLR_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) & ~(value)))
+#define PDB_TOG_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_C1 bitfields
+ */
+
+/*!
+ * @name Register PDB_C1, field EN[7:0] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
+ * bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger disabled.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_EN field. */
+#define PDB_RD_C1_EN(base, index) ((PDB_C1_REG(base, index) & PDB_C1_EN_MASK) >> PDB_C1_EN_SHIFT)
+#define PDB_BRD_C1_EN(base, index) (PDB_RD_C1_EN(base, index))
+
+/*! @brief Set the EN field to a new value. */
+#define PDB_WR_C1_EN(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_EN_MASK, PDB_C1_EN(value)))
+#define PDB_BWR_C1_EN(base, index, value) (PDB_WR_C1_EN(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_C1, field TOS[15:8] (RW)
+ *
+ * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
+ * implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger is in bypassed mode.
+ *     The pre-trigger asserts one peripheral clock cycle after a rising edge is
+ *     detected on selected trigger input source or software trigger is selected
+ *     and SWTRIG is written with 1.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger asserts when the
+ *     counter reaches the channel delay register and one peripheral clock cycle after
+ *     a rising edge is detected on selected trigger input source or software
+ *     trigger is selected and SETRIG is written with 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_TOS field. */
+#define PDB_RD_C1_TOS(base, index) ((PDB_C1_REG(base, index) & PDB_C1_TOS_MASK) >> PDB_C1_TOS_SHIFT)
+#define PDB_BRD_C1_TOS(base, index) (PDB_RD_C1_TOS(base, index))
+
+/*! @brief Set the TOS field to a new value. */
+#define PDB_WR_C1_TOS(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_TOS_MASK, PDB_C1_TOS(value)))
+#define PDB_BWR_C1_TOS(base, index, value) (PDB_WR_C1_TOS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_C1, field BB[23:16] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
+ * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
+ * enables the ADC conversions complete to trigger the next PDB channel
+ * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
+ * set of configuration and results registers. Application code must only enable
+ * the back-to-back operation of the PDB pre-triggers at the leading of the
+ * back-to-back connection chain.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger back-to-back operation
+ *     disabled.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger back-to-back operation
+ *     enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_BB field. */
+#define PDB_RD_C1_BB(base, index) ((PDB_C1_REG(base, index) & PDB_C1_BB_MASK) >> PDB_C1_BB_SHIFT)
+#define PDB_BRD_C1_BB(base, index) (PDB_RD_C1_BB(base, index))
+
+/*! @brief Set the BB field to a new value. */
+#define PDB_WR_C1_BB(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_BB_MASK, PDB_C1_BB(value)))
+#define PDB_BWR_C1_BB(base, index, value) (PDB_WR_C1_BB(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_S - Channel n Status register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_S - Channel n Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_S register
+ */
+/*@{*/
+#define PDB_RD_S(base, index)    (PDB_S_REG(base, index))
+#define PDB_WR_S(base, index, value) (PDB_S_REG(base, index) = (value))
+#define PDB_RMW_S(base, index, mask, value) (PDB_WR_S(base, index, (PDB_RD_S(base, index) & ~(mask)) | (value)))
+#define PDB_SET_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) |  (value)))
+#define PDB_CLR_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) & ~(value)))
+#define PDB_TOG_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_S bitfields
+ */
+
+/*!
+ * @name Register PDB_S, field ERR[7:0] (RW)
+ *
+ * Only the lower M bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - Sequence error not detected on PDB channel's corresponding
+ *     pre-trigger.
+ * - 0b00000001 - Sequence error detected on PDB channel's corresponding
+ *     pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from
+ *     PDB channel n. When one conversion, which is triggered by one of the
+ *     pre-triggers from PDB channel n, is in progress, new trigger from PDB
+ *     channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is
+ *     set. Writing 0's to clear the sequence error flags.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_S_ERR field. */
+#define PDB_RD_S_ERR(base, index) ((PDB_S_REG(base, index) & PDB_S_ERR_MASK) >> PDB_S_ERR_SHIFT)
+#define PDB_BRD_S_ERR(base, index) (PDB_RD_S_ERR(base, index))
+
+/*! @brief Set the ERR field to a new value. */
+#define PDB_WR_S_ERR(base, index, value) (PDB_RMW_S(base, index, PDB_S_ERR_MASK, PDB_S_ERR(value)))
+#define PDB_BWR_S_ERR(base, index, value) (PDB_WR_S_ERR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_S, field CF[23:16] (RW)
+ *
+ * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
+ * clear these bits.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_S_CF field. */
+#define PDB_RD_S_CF(base, index) ((PDB_S_REG(base, index) & PDB_S_CF_MASK) >> PDB_S_CF_SHIFT)
+#define PDB_BRD_S_CF(base, index) (PDB_RD_S_CF(base, index))
+
+/*! @brief Set the CF field to a new value. */
+#define PDB_WR_S_CF(base, index, value) (PDB_RMW_S(base, index, PDB_S_CF_MASK, PDB_S_CF(value)))
+#define PDB_BWR_S_CF(base, index, value) (PDB_WR_S_CF(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_DLY - Channel n Delay 0 register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_DLY - Channel n Delay 0 register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_DLY register
+ */
+/*@{*/
+#define PDB_RD_DLY(base, index, index2) (PDB_DLY_REG(base, index, index2))
+#define PDB_WR_DLY(base, index, index2, value) (PDB_DLY_REG(base, index, index2) = (value))
+#define PDB_RMW_DLY(base, index, index2, mask, value) (PDB_WR_DLY(base, index, index2, (PDB_RD_DLY(base, index, index2) & ~(mask)) | (value)))
+#define PDB_SET_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) |  (value)))
+#define PDB_CLR_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) & ~(value)))
+#define PDB_TOG_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_DLY bitfields
+ */
+
+/*!
+ * @name Register PDB_DLY, field DLY[15:0] (RW)
+ *
+ * Specifies the delay value for the channel's corresponding pre-trigger. The
+ * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
+ * the value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_DLY_DLY field. */
+#define PDB_RD_DLY_DLY(base, index, index2) ((PDB_DLY_REG(base, index, index2) & PDB_DLY_DLY_MASK) >> PDB_DLY_DLY_SHIFT)
+#define PDB_BRD_DLY_DLY(base, index, index2) (PDB_RD_DLY_DLY(base, index, index2))
+
+/*! @brief Set the DLY field to a new value. */
+#define PDB_WR_DLY_DLY(base, index, index2, value) (PDB_RMW_DLY(base, index, index2, PDB_DLY_DLY_MASK, PDB_DLY_DLY(value)))
+#define PDB_BWR_DLY_DLY(base, index, index2, value) (PDB_WR_DLY_DLY(base, index, index2, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_INTC - DAC Interval Trigger n Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_INTC - DAC Interval Trigger n Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_INTC register
+ */
+/*@{*/
+#define PDB_RD_INTC(base, index) (PDB_INTC_REG(base, index))
+#define PDB_WR_INTC(base, index, value) (PDB_INTC_REG(base, index) = (value))
+#define PDB_RMW_INTC(base, index, mask, value) (PDB_WR_INTC(base, index, (PDB_RD_INTC(base, index) & ~(mask)) | (value)))
+#define PDB_SET_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) |  (value)))
+#define PDB_CLR_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) & ~(value)))
+#define PDB_TOG_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_INTC bitfields
+ */
+
+/*!
+ * @name Register PDB_INTC, field TOE[0] (RW)
+ *
+ * This bit enables the DAC interval trigger.
+ *
+ * Values:
+ * - 0b0 - DAC interval trigger disabled.
+ * - 0b1 - DAC interval trigger enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INTC_TOE field. */
+#define PDB_RD_INTC_TOE(base, index) ((PDB_INTC_REG(base, index) & PDB_INTC_TOE_MASK) >> PDB_INTC_TOE_SHIFT)
+#define PDB_BRD_INTC_TOE(base, index) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_TOE_SHIFT))
+
+/*! @brief Set the TOE field to a new value. */
+#define PDB_WR_INTC_TOE(base, index, value) (PDB_RMW_INTC(base, index, PDB_INTC_TOE_MASK, PDB_INTC_TOE(value)))
+#define PDB_BWR_INTC_TOE(base, index, value) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_TOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_INTC, field EXT[1] (RW)
+ *
+ * Enables the external trigger for DAC interval counter.
+ *
+ * Values:
+ * - 0b0 - DAC external trigger input disabled. DAC interval counter is reset
+ *     and counting starts when a rising edge is detected on selected trigger input
+ *     source or software trigger is selected and SWTRIG is written with 1.
+ * - 0b1 - DAC external trigger input enabled. DAC interval counter is bypassed
+ *     and DAC external trigger input triggers the DAC interval trigger.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INTC_EXT field. */
+#define PDB_RD_INTC_EXT(base, index) ((PDB_INTC_REG(base, index) & PDB_INTC_EXT_MASK) >> PDB_INTC_EXT_SHIFT)
+#define PDB_BRD_INTC_EXT(base, index) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_EXT_SHIFT))
+
+/*! @brief Set the EXT field to a new value. */
+#define PDB_WR_INTC_EXT(base, index, value) (PDB_RMW_INTC(base, index, PDB_INTC_EXT_MASK, PDB_INTC_EXT(value)))
+#define PDB_BWR_INTC_EXT(base, index, value) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_EXT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_INT - DAC Interval n register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_INT - DAC Interval n register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_INT register
+ */
+/*@{*/
+#define PDB_RD_INT(base, index)  (PDB_INT_REG(base, index))
+#define PDB_WR_INT(base, index, value) (PDB_INT_REG(base, index) = (value))
+#define PDB_RMW_INT(base, index, mask, value) (PDB_WR_INT(base, index, (PDB_RD_INT(base, index) & ~(mask)) | (value)))
+#define PDB_SET_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) |  (value)))
+#define PDB_CLR_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) & ~(value)))
+#define PDB_TOG_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_INT bitfields
+ */
+
+/*!
+ * @name Register PDB_INT, field INT[15:0] (RW)
+ *
+ * Specifies the interval value for DAC interval trigger. DAC interval trigger
+ * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
+ * Reading this field returns the value of internal register that is effective
+ * for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INT_INT field. */
+#define PDB_RD_INT_INT(base, index) ((PDB_INT_REG(base, index) & PDB_INT_INT_MASK) >> PDB_INT_INT_SHIFT)
+#define PDB_BRD_INT_INT(base, index) (PDB_RD_INT_INT(base, index))
+
+/*! @brief Set the INT field to a new value. */
+#define PDB_WR_INT_INT(base, index, value) (PDB_RMW_INT(base, index, PDB_INT_INT_MASK, PDB_INT_INT(value)))
+#define PDB_BWR_INT_INT(base, index, value) (PDB_WR_INT_INT(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_POEN - Pulse-Out n Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_POEN - Pulse-Out n Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_POEN register
+ */
+/*@{*/
+#define PDB_RD_POEN(base)        (PDB_POEN_REG(base))
+#define PDB_WR_POEN(base, value) (PDB_POEN_REG(base) = (value))
+#define PDB_RMW_POEN(base, mask, value) (PDB_WR_POEN(base, (PDB_RD_POEN(base) & ~(mask)) | (value)))
+#define PDB_SET_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) |  (value)))
+#define PDB_CLR_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) & ~(value)))
+#define PDB_TOG_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_POEN bitfields
+ */
+
+/*!
+ * @name Register PDB_POEN, field POEN[7:0] (RW)
+ *
+ * Enables the pulse output. Only lower Y bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB Pulse-Out disabled
+ * - 0b00000001 - PDB Pulse-Out enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_POEN_POEN field. */
+#define PDB_RD_POEN_POEN(base) ((PDB_POEN_REG(base) & PDB_POEN_POEN_MASK) >> PDB_POEN_POEN_SHIFT)
+#define PDB_BRD_POEN_POEN(base) (PDB_RD_POEN_POEN(base))
+
+/*! @brief Set the POEN field to a new value. */
+#define PDB_WR_POEN_POEN(base, value) (PDB_RMW_POEN(base, PDB_POEN_POEN_MASK, PDB_POEN_POEN(value)))
+#define PDB_BWR_POEN_POEN(base, value) (PDB_WR_POEN_POEN(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_PODLY - Pulse-Out n Delay register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_PODLY - Pulse-Out n Delay register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_PODLY register
+ */
+/*@{*/
+#define PDB_RD_PODLY(base, index) (PDB_PODLY_REG(base, index))
+#define PDB_WR_PODLY(base, index, value) (PDB_PODLY_REG(base, index) = (value))
+#define PDB_RMW_PODLY(base, index, mask, value) (PDB_WR_PODLY(base, index, (PDB_RD_PODLY(base, index) & ~(mask)) | (value)))
+#define PDB_SET_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) |  (value)))
+#define PDB_CLR_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) & ~(value)))
+#define PDB_TOG_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_PODLY bitfields
+ */
+
+/*!
+ * @name Register PDB_PODLY, field DLY2[15:0] (RW)
+ *
+ * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
+ * low when the PDB counter is equal to the DLY2. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_PODLY_DLY2 field. */
+#define PDB_RD_PODLY_DLY2(base, index) ((PDB_PODLY_REG(base, index) & PDB_PODLY_DLY2_MASK) >> PDB_PODLY_DLY2_SHIFT)
+#define PDB_BRD_PODLY_DLY2(base, index) (PDB_RD_PODLY_DLY2(base, index))
+
+/*! @brief Set the DLY2 field to a new value. */
+#define PDB_WR_PODLY_DLY2(base, index, value) (PDB_RMW_PODLY(base, index, PDB_PODLY_DLY2_MASK, PDB_PODLY_DLY2(value)))
+#define PDB_BWR_PODLY_DLY2(base, index, value) (PDB_WR_PODLY_DLY2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_PODLY, field DLY1[31:16] (RW)
+ *
+ * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
+ * high when the PDB counter is equal to the DLY1. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_PODLY_DLY1 field. */
+#define PDB_RD_PODLY_DLY1(base, index) ((PDB_PODLY_REG(base, index) & PDB_PODLY_DLY1_MASK) >> PDB_PODLY_DLY1_SHIFT)
+#define PDB_BRD_PODLY_DLY1(base, index) (PDB_RD_PODLY_DLY1(base, index))
+
+/*! @brief Set the DLY1 field to a new value. */
+#define PDB_WR_PODLY_DLY1(base, index, value) (PDB_RMW_PODLY(base, index, PDB_PODLY_DLY1_MASK, PDB_PODLY_DLY1(value)))
+#define PDB_BWR_PODLY_DLY1(base, index, value) (PDB_WR_PODLY_DLY1(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 PIT
+ *
+ * Periodic Interrupt Timer
+ *
+ * Registers defined in this header file:
+ * - PIT_MCR - PIT Module Control Register
+ * - PIT_LDVAL - Timer Load Value Register
+ * - PIT_CVAL - Current Timer Value Register
+ * - PIT_TCTRL - Timer Control Register
+ * - PIT_TFLG - Timer Flag Register
+ */
+
+#define PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
+#define PIT_IDX (0U) /*!< Instance number for PIT. */
+
+/*******************************************************************************
+ * PIT_MCR - PIT Module Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_MCR - PIT Module Control Register (RW)
+ *
+ * Reset value: 0x00000006U
+ *
+ * This register enables or disables the PIT timer clocks and controls the
+ * timers when the PIT enters the Debug mode.
+ */
+/*!
+ * @name Constants and macros for entire PIT_MCR register
+ */
+/*@{*/
+#define PIT_RD_MCR(base)         (PIT_MCR_REG(base))
+#define PIT_WR_MCR(base, value)  (PIT_MCR_REG(base) = (value))
+#define PIT_RMW_MCR(base, mask, value) (PIT_WR_MCR(base, (PIT_RD_MCR(base) & ~(mask)) | (value)))
+#define PIT_SET_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) |  (value)))
+#define PIT_CLR_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) & ~(value)))
+#define PIT_TOG_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_MCR bitfields
+ */
+
+/*!
+ * @name Register PIT_MCR, field FRZ[0] (RW)
+ *
+ * Allows the timers to be stopped when the device enters the Debug mode.
+ *
+ * Values:
+ * - 0b0 - Timers continue to run in Debug mode.
+ * - 0b1 - Timers are stopped in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_FRZ field. */
+#define PIT_RD_MCR_FRZ(base) ((PIT_MCR_REG(base) & PIT_MCR_FRZ_MASK) >> PIT_MCR_FRZ_SHIFT)
+#define PIT_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define PIT_WR_MCR_FRZ(base, value) (PIT_RMW_MCR(base, PIT_MCR_FRZ_MASK, PIT_MCR_FRZ(value)))
+#define PIT_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_MCR, field MDIS[1] (RW)
+ *
+ * Disables the standard timers. This field must be enabled before any other
+ * setup is done.
+ *
+ * Values:
+ * - 0b0 - Clock for standard PIT timers is enabled.
+ * - 0b1 - Clock for standard PIT timers is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_MDIS field. */
+#define PIT_RD_MCR_MDIS(base) ((PIT_MCR_REG(base) & PIT_MCR_MDIS_MASK) >> PIT_MCR_MDIS_SHIFT)
+#define PIT_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define PIT_WR_MCR_MDIS(base, value) (PIT_RMW_MCR(base, PIT_MCR_MDIS_MASK, PIT_MCR_MDIS(value)))
+#define PIT_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_LDVAL - Timer Load Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_LDVAL - Timer Load Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers select the timeout period for the timer interrupts.
+ */
+/*!
+ * @name Constants and macros for entire PIT_LDVAL register
+ */
+/*@{*/
+#define PIT_RD_LDVAL(base, index) (PIT_LDVAL_REG(base, index))
+#define PIT_WR_LDVAL(base, index, value) (PIT_LDVAL_REG(base, index) = (value))
+#define PIT_RMW_LDVAL(base, index, mask, value) (PIT_WR_LDVAL(base, index, (PIT_RD_LDVAL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) |  (value)))
+#define PIT_CLR_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) & ~(value)))
+#define PIT_TOG_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_CVAL - Current Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_CVAL - Current Timer Value Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the current timer position.
+ */
+/*!
+ * @name Constants and macros for entire PIT_CVAL register
+ */
+/*@{*/
+#define PIT_RD_CVAL(base, index) (PIT_CVAL_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TCTRL - Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TCTRL - Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the control bits for each timer.
+ */
+/*!
+ * @name Constants and macros for entire PIT_TCTRL register
+ */
+/*@{*/
+#define PIT_RD_TCTRL(base, index) (PIT_TCTRL_REG(base, index))
+#define PIT_WR_TCTRL(base, index, value) (PIT_TCTRL_REG(base, index) = (value))
+#define PIT_RMW_TCTRL(base, index, mask, value) (PIT_WR_TCTRL(base, index, (PIT_RD_TCTRL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) |  (value)))
+#define PIT_CLR_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) & ~(value)))
+#define PIT_TOG_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TCTRL bitfields
+ */
+
+/*!
+ * @name Register PIT_TCTRL, field TEN[0] (RW)
+ *
+ * Enables or disables the timer.
+ *
+ * Values:
+ * - 0b0 - Timer n is disabled.
+ * - 0b1 - Timer n is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TEN field. */
+#define PIT_RD_TCTRL_TEN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TEN_MASK) >> PIT_TCTRL_TEN_SHIFT)
+#define PIT_BRD_TCTRL_TEN(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT))
+
+/*! @brief Set the TEN field to a new value. */
+#define PIT_WR_TCTRL_TEN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TEN_MASK, PIT_TCTRL_TEN(value)))
+#define PIT_BWR_TCTRL_TEN(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field TIE[1] (RW)
+ *
+ * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
+ * will immediately cause an interrupt event. To avoid this, the associated
+ * TFLGn[TIF] must be cleared first.
+ *
+ * Values:
+ * - 0b0 - Interrupt requests from Timer n are disabled.
+ * - 0b1 - Interrupt will be requested whenever TIF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TIE field. */
+#define PIT_RD_TCTRL_TIE(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TIE_MASK) >> PIT_TCTRL_TIE_SHIFT)
+#define PIT_BRD_TCTRL_TIE(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define PIT_WR_TCTRL_TIE(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TIE_MASK, PIT_TCTRL_TIE(value)))
+#define PIT_BWR_TCTRL_TIE(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field CHN[2] (RW)
+ *
+ * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
+ * Timer 0 cannot be chained.
+ *
+ * Values:
+ * - 0b0 - Timer is not chained.
+ * - 0b1 - Timer is chained to previous timer. For example, for Channel 2, if
+ *     this field is set, Timer 2 is chained to Timer 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_CHN field. */
+#define PIT_RD_TCTRL_CHN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_CHN_MASK) >> PIT_TCTRL_CHN_SHIFT)
+#define PIT_BRD_TCTRL_CHN(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT))
+
+/*! @brief Set the CHN field to a new value. */
+#define PIT_WR_TCTRL_CHN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_CHN_MASK, PIT_TCTRL_CHN(value)))
+#define PIT_BWR_TCTRL_CHN(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TFLG - Timer Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TFLG - Timer Flag Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers hold the PIT interrupt flags.
+ */
+/*!
+ * @name Constants and macros for entire PIT_TFLG register
+ */
+/*@{*/
+#define PIT_RD_TFLG(base, index) (PIT_TFLG_REG(base, index))
+#define PIT_WR_TFLG(base, index, value) (PIT_TFLG_REG(base, index) = (value))
+#define PIT_RMW_TFLG(base, index, mask, value) (PIT_WR_TFLG(base, index, (PIT_RD_TFLG(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) |  (value)))
+#define PIT_CLR_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) & ~(value)))
+#define PIT_TOG_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TFLG bitfields
+ */
+
+/*!
+ * @name Register PIT_TFLG, field TIF[0] (W1C)
+ *
+ * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
+ * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
+ * interrupt request.
+ *
+ * Values:
+ * - 0b0 - Timeout has not yet occurred.
+ * - 0b1 - Timeout has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TFLG_TIF field. */
+#define PIT_RD_TFLG_TIF(base, index) ((PIT_TFLG_REG(base, index) & PIT_TFLG_TIF_MASK) >> PIT_TFLG_TIF_SHIFT)
+#define PIT_BRD_TFLG_TIF(base, index) (BITBAND_ACCESS32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT))
+
+/*! @brief Set the TIF field to a new value. */
+#define PIT_WR_TFLG_TIF(base, index, value) (PIT_RMW_TFLG(base, index, PIT_TFLG_TIF_MASK, PIT_TFLG_TIF(value)))
+#define PIT_BWR_TFLG_TIF(base, index, value) (BITBAND_ACCESS32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PMC
+ *
+ * Power Management Controller
+ *
+ * Registers defined in this header file:
+ * - PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ * - PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ * - PMC_REGSC - Regulator Status And Control register
+ */
+
+#define PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
+#define PMC_IDX (0U) /*!< Instance number for PMC. */
+
+/*******************************************************************************
+ * PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
+ *
+ * Reset value: 0x10U
+ *
+ * This register contains status and control bits to support the low voltage
+ * detect function. This register should be written during the reset initialization
+ * program to set the desired controls even if the desired settings are the same
+ * as the reset settings. While the device is in the very low power or low
+ * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
+ * systems that must have LVD always on, configure the Power Mode Protection
+ * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
+ * low leakage modes from being enabled. See the device's data sheet for the
+ * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
+ * register's other bits are reset on Chip Reset Not VLLS. For more information
+ * about these reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC1 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC1(base)      (PMC_LVDSC1_REG(base))
+#define PMC_WR_LVDSC1(base, value) (PMC_LVDSC1_REG(base) = (value))
+#define PMC_RMW_LVDSC1(base, mask, value) (PMC_WR_LVDSC1(base, (PMC_RD_LVDSC1(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) |  (value)))
+#define PMC_CLR_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) & ~(value)))
+#define PMC_TOG_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC1 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
+ *
+ * Selects the LVD trip point voltage (V LVD ).
+ *
+ * Values:
+ * - 0b00 - Low trip point selected (V LVD = V LVDL )
+ * - 0b01 - High trip point selected (V LVD = V LVDH )
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
+#define PMC_RD_LVDSC1_LVDV(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDV_MASK) >> PMC_LVDSC1_LVDV_SHIFT)
+#define PMC_BRD_LVDSC1_LVDV(base) (PMC_RD_LVDSC1_LVDV(base))
+
+/*! @brief Set the LVDV field to a new value. */
+#define PMC_WR_LVDSC1_LVDV(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDV_MASK, PMC_LVDSC1_LVDV(value)))
+#define PMC_BWR_LVDSC1_LVDV(base, value) (PMC_WR_LVDSC1_LVDV(base, value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
+ *
+ * This write-once bit enables LVDF events to generate a hardware reset.
+ * Additional writes are ignored.
+ *
+ * Values:
+ * - 0b0 - LVDF does not generate hardware resets
+ * - 0b1 - Force an MCU reset when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
+#define PMC_RD_LVDSC1_LVDRE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDRE_MASK) >> PMC_LVDSC1_LVDRE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDRE(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT))
+
+/*! @brief Set the LVDRE field to a new value. */
+#define PMC_WR_LVDSC1_LVDRE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDRE_MASK, PMC_LVDSC1_LVDRE(value)))
+#define PMC_BWR_LVDSC1_LVDRE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVDF.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupt disabled (use polling)
+ * - 0b1 - Request a hardware interrupt when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
+#define PMC_RD_LVDSC1_LVDIE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDIE_MASK) >> PMC_LVDSC1_LVDIE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDIE(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT))
+
+/*! @brief Set the LVDIE field to a new value. */
+#define PMC_WR_LVDSC1_LVDIE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDIE_MASK, PMC_LVDSC1_LVDIE(value)))
+#define PMC_BWR_LVDSC1_LVDIE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage detection errors.
+ * Write 1 to clear LVDF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVDACK field to a new value. */
+#define PMC_WR_LVDSC1_LVDACK(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDACK_MASK, PMC_LVDSC1_LVDACK(value)))
+#define PMC_BWR_LVDSC1_LVDACK(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage detect event.
+ *
+ * Values:
+ * - 0b0 - Low-voltage event not detected
+ * - 0b1 - Low-voltage event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
+#define PMC_RD_LVDSC1_LVDF(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDF_MASK) >> PMC_LVDSC1_LVDF_SHIFT)
+#define PMC_BRD_LVDSC1_LVDF(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains status and control bits to support the low voltage
+ * warning function. While the device is in the very low power or low leakage modes,
+ * the LVD system is disabled regardless of LVDSC2 settings. See the device's
+ * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
+ * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
+ * register are reset on Chip Reset Not VLLS. For more information about these
+ * reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC2 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC2(base)      (PMC_LVDSC2_REG(base))
+#define PMC_WR_LVDSC2(base, value) (PMC_LVDSC2_REG(base) = (value))
+#define PMC_RMW_LVDSC2(base, mask, value) (PMC_WR_LVDSC2(base, (PMC_RD_LVDSC2(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) |  (value)))
+#define PMC_CLR_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) & ~(value)))
+#define PMC_TOG_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC2 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
+ *
+ * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
+ * depends on LVDSC1[LVDV].
+ *
+ * Values:
+ * - 0b00 - Low trip point selected (VLVW = VLVW1)
+ * - 0b01 - Mid 1 trip point selected (VLVW = VLVW2)
+ * - 0b10 - Mid 2 trip point selected (VLVW = VLVW3)
+ * - 0b11 - High trip point selected (VLVW = VLVW4)
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
+#define PMC_RD_LVDSC2_LVWV(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWV_MASK) >> PMC_LVDSC2_LVWV_SHIFT)
+#define PMC_BRD_LVDSC2_LVWV(base) (PMC_RD_LVDSC2_LVWV(base))
+
+/*! @brief Set the LVWV field to a new value. */
+#define PMC_WR_LVDSC2_LVWV(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWV_MASK, PMC_LVDSC2_LVWV(value)))
+#define PMC_BWR_LVDSC2_LVWV(base, value) (PMC_WR_LVDSC2_LVWV(base, value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVWF.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupt disabled (use polling)
+ * - 0b1 - Request a hardware interrupt when LVWF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
+#define PMC_RD_LVDSC2_LVWIE(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWIE_MASK) >> PMC_LVDSC2_LVWIE_SHIFT)
+#define PMC_BRD_LVDSC2_LVWIE(base) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT))
+
+/*! @brief Set the LVWIE field to a new value. */
+#define PMC_WR_LVDSC2_LVWIE(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWIE_MASK, PMC_LVDSC2_LVWIE(value)))
+#define PMC_BWR_LVDSC2_LVWIE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage warning errors.
+ * Write 1 to clear LVWF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVWACK field to a new value. */
+#define PMC_WR_LVDSC2_LVWACK(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWACK_MASK, PMC_LVDSC2_LVWACK(value)))
+#define PMC_BWR_LVDSC2_LVWACK(base, value) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage warning event. LVWF is
+ * set when VSupply transitions below the trip point, or after reset and VSupply is
+ * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
+ * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
+ * LVWACK first.
+ *
+ * Values:
+ * - 0b0 - Low-voltage warning event not detected
+ * - 0b1 - Low-voltage warning event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
+#define PMC_RD_LVDSC2_LVWF(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWF_MASK) >> PMC_LVDSC2_LVWF_SHIFT)
+#define PMC_BRD_LVDSC2_LVWF(base) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_REGSC - Regulator Status And Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_REGSC - Regulator Status And Control register (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * The PMC contains an internal voltage regulator. The voltage regulator design
+ * uses a bandgap reference that is also available through a buffer as input to
+ * certain internal peripherals, such as the CMP and ADC. The internal regulator
+ * provides a status bit (REGONS) indicating the regulator is in run regulation.
+ * This register is reset on Chip Reset Not VLLS and by reset types that trigger
+ * Chip Reset not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire PMC_REGSC register
+ */
+/*@{*/
+#define PMC_RD_REGSC(base)       (PMC_REGSC_REG(base))
+#define PMC_WR_REGSC(base, value) (PMC_REGSC_REG(base) = (value))
+#define PMC_RMW_REGSC(base, mask, value) (PMC_WR_REGSC(base, (PMC_RD_REGSC(base) & ~(mask)) | (value)))
+#define PMC_SET_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) |  (value)))
+#define PMC_CLR_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) & ~(value)))
+#define PMC_TOG_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_REGSC bitfields
+ */
+
+/*!
+ * @name Register PMC_REGSC, field BGBE[0] (RW)
+ *
+ * Enables the bandgap buffer.
+ *
+ * Values:
+ * - 0b0 - Bandgap buffer not enabled
+ * - 0b1 - Bandgap buffer enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGBE field. */
+#define PMC_RD_REGSC_BGBE(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGBE_MASK) >> PMC_REGSC_BGBE_SHIFT)
+#define PMC_BRD_REGSC_BGBE(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT))
+
+/*! @brief Set the BGBE field to a new value. */
+#define PMC_WR_REGSC_BGBE(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGBE_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGBE(value)))
+#define PMC_BWR_REGSC_BGBE(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field REGONS[2] (RO)
+ *
+ * This read-only field provides the current status of the internal voltage
+ * regulator.
+ *
+ * Values:
+ * - 0b0 - Regulator is in stop regulation or in transition to/from it
+ * - 0b1 - Regulator is in run regulation
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_REGONS field. */
+#define PMC_RD_REGSC_REGONS(base) ((PMC_REGSC_REG(base) & PMC_REGSC_REGONS_MASK) >> PMC_REGSC_REGONS_SHIFT)
+#define PMC_BRD_REGSC_REGONS(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_REGONS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field ACKISO[3] (W1C)
+ *
+ * Reading this field indicates whether certain peripherals and the I/O pads are
+ * in a latched state as a result of having been in a VLLS mode. Writing 1 to
+ * this field when it is set releases the I/O pads and certain peripherals to their
+ * normal run mode state. After recovering from a VLLS mode, user should restore
+ * chip configuration before clearing ACKISO. In particular, pin configuration
+ * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
+ * being falsely set when ACKISO is cleared.
+ *
+ * Values:
+ * - 0b0 - Peripherals and I/O pads are in normal run state.
+ * - 0b1 - Certain peripherals and I/O pads are in an isolated and latched state.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_ACKISO field. */
+#define PMC_RD_REGSC_ACKISO(base) ((PMC_REGSC_REG(base) & PMC_REGSC_ACKISO_MASK) >> PMC_REGSC_ACKISO_SHIFT)
+#define PMC_BRD_REGSC_ACKISO(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT))
+
+/*! @brief Set the ACKISO field to a new value. */
+#define PMC_WR_REGSC_ACKISO(base, value) (PMC_RMW_REGSC(base, PMC_REGSC_ACKISO_MASK, PMC_REGSC_ACKISO(value)))
+#define PMC_BWR_REGSC_ACKISO(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field BGEN[4] (RW)
+ *
+ * BGEN controls whether the bandgap is enabled in lower power modes of
+ * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
+ * reference in low power modes of operation, set BGEN to continue to enable the
+ * bandgap operation. When the bandgap voltage reference is not needed in low
+ * power modes, clear BGEN to avoid excess power consumption.
+ *
+ * Values:
+ * - 0b0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
+ * - 0b1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGEN field. */
+#define PMC_RD_REGSC_BGEN(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGEN_MASK) >> PMC_REGSC_BGEN_SHIFT)
+#define PMC_BRD_REGSC_BGEN(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT))
+
+/*! @brief Set the BGEN field to a new value. */
+#define PMC_WR_REGSC_BGEN(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGEN_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGEN(value)))
+#define PMC_BWR_REGSC_BGEN(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PORT
+ *
+ * Pin Control and Interrupts
+ *
+ * Registers defined in this header file:
+ * - PORT_PCR - Pin Control Register n
+ * - PORT_GPCLR - Global Pin Control Low Register
+ * - PORT_GPCHR - Global Pin Control High Register
+ * - PORT_ISFR - Interrupt Status Flag Register
+ * - PORT_DFER - Digital Filter Enable Register
+ * - PORT_DFCR - Digital Filter Clock Register
+ * - PORT_DFWR - Digital Filter Width Register
+ */
+
+#define PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
+#define PORTA_IDX (0U) /*!< Instance number for PORTA. */
+#define PORTB_IDX (1U) /*!< Instance number for PORTB. */
+#define PORTC_IDX (2U) /*!< Instance number for PORTC. */
+#define PORTD_IDX (3U) /*!< Instance number for PORTD. */
+#define PORTE_IDX (4U) /*!< Instance number for PORTE. */
+
+/*******************************************************************************
+ * PORT_PCR - Pin Control Register n
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_PCR - Pin Control Register n (RW)
+ *
+ * Reset value: 0x00000746U
+ *
+ * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
+ * this device. See the GPIO Configuration section for details on the available
+ * functions for each pin. Do not modify pin configuration registers associated
+ * with pins not available in your selected package. All unbonded pins not
+ * available in your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire PORT_PCR register
+ */
+/*@{*/
+#define PORT_RD_PCR(base, index) (PORT_PCR_REG(base, index))
+#define PORT_WR_PCR(base, index, value) (PORT_PCR_REG(base, index) = (value))
+#define PORT_RMW_PCR(base, index, mask, value) (PORT_WR_PCR(base, index, (PORT_RD_PCR(base, index) & ~(mask)) | (value)))
+#define PORT_SET_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) |  (value)))
+#define PORT_CLR_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) & ~(value)))
+#define PORT_TOG_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_PCR bitfields
+ */
+
+/*!
+ * @name Register PORT_PCR, field PS[0] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Internal pulldown resistor is enabled on the corresponding pin, if
+ *     the corresponding PE field is set.
+ * - 0b1 - Internal pullup resistor is enabled on the corresponding pin, if the
+ *     corresponding PE field is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PS field. */
+#define PORT_RD_PCR_PS(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PS_MASK) >> PORT_PCR_PS_SHIFT)
+#define PORT_BRD_PCR_PS(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT))
+
+/*! @brief Set the PS field to a new value. */
+#define PORT_WR_PCR_PS(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PS_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PS(value)))
+#define PORT_BWR_PCR_PS(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PE[1] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Internal pullup or pulldown resistor is not enabled on the
+ *     corresponding pin.
+ * - 0b1 - Internal pullup or pulldown resistor is enabled on the corresponding
+ *     pin, if the pin is configured as a digital input.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PE field. */
+#define PORT_RD_PCR_PE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PE_MASK) >> PORT_PCR_PE_SHIFT)
+#define PORT_BRD_PCR_PE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT))
+
+/*! @brief Set the PE field to a new value. */
+#define PORT_WR_PCR_PE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PE(value)))
+#define PORT_BWR_PCR_PE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field SRE[2] (RW)
+ *
+ * Slew rate configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Fast slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ * - 0b1 - Slow slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_SRE field. */
+#define PORT_RD_PCR_SRE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_SRE_MASK) >> PORT_PCR_SRE_SHIFT)
+#define PORT_BRD_PCR_SRE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT))
+
+/*! @brief Set the SRE field to a new value. */
+#define PORT_WR_PCR_SRE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_SRE(value)))
+#define PORT_BWR_PCR_SRE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PFE[4] (RW)
+ *
+ * Passive filter configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Passive input filter is disabled on the corresponding pin.
+ * - 0b1 - Passive input filter is enabled on the corresponding pin, if the pin
+ *     is configured as a digital input. Refer to the device data sheet for
+ *     filter characteristics.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PFE field. */
+#define PORT_RD_PCR_PFE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PFE_MASK) >> PORT_PCR_PFE_SHIFT)
+#define PORT_BRD_PCR_PFE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT))
+
+/*! @brief Set the PFE field to a new value. */
+#define PORT_WR_PCR_PFE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PFE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PFE(value)))
+#define PORT_BWR_PCR_PFE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ODE[5] (RW)
+ *
+ * Open drain configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Open drain output is disabled on the corresponding pin.
+ * - 0b1 - Open drain output is enabled on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ODE field. */
+#define PORT_RD_PCR_ODE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ODE_MASK) >> PORT_PCR_ODE_SHIFT)
+#define PORT_BRD_PCR_ODE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ODE_SHIFT))
+
+/*! @brief Set the ODE field to a new value. */
+#define PORT_WR_PCR_ODE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_ODE(value)))
+#define PORT_BWR_PCR_ODE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field DSE[6] (RW)
+ *
+ * Drive strength configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Low drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ * - 0b1 - High drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_DSE field. */
+#define PORT_RD_PCR_DSE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_DSE_MASK) >> PORT_PCR_DSE_SHIFT)
+#define PORT_BRD_PCR_DSE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT))
+
+/*! @brief Set the DSE field to a new value. */
+#define PORT_WR_PCR_DSE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_DSE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_DSE(value)))
+#define PORT_BWR_PCR_DSE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field MUX[10:8] (RW)
+ *
+ * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
+ * reserved and may result in configuring the pin for a different pin muxing
+ * slot. The corresponding pin is configured in the following pin muxing slot as
+ * follows:
+ *
+ * Values:
+ * - 0b000 - Pin disabled (analog).
+ * - 0b001 - Alternative 1 (GPIO).
+ * - 0b010 - Alternative 2 (chip-specific).
+ * - 0b011 - Alternative 3 (chip-specific).
+ * - 0b100 - Alternative 4 (chip-specific).
+ * - 0b101 - Alternative 5 (chip-specific).
+ * - 0b110 - Alternative 6 (chip-specific).
+ * - 0b111 - Alternative 7 (chip-specific).
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_MUX field. */
+#define PORT_RD_PCR_MUX(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_MUX_MASK) >> PORT_PCR_MUX_SHIFT)
+#define PORT_BRD_PCR_MUX(base, index) (PORT_RD_PCR_MUX(base, index))
+
+/*! @brief Set the MUX field to a new value. */
+#define PORT_WR_PCR_MUX(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_MUX_MASK | PORT_PCR_ISF_MASK), PORT_PCR_MUX(value)))
+#define PORT_BWR_PCR_MUX(base, index, value) (PORT_WR_PCR_MUX(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field LK[15] (RW)
+ *
+ * Values:
+ * - 0b0 - Pin Control Register fields [15:0] are not locked.
+ * - 0b1 - Pin Control Register fields [15:0] are locked and cannot be updated
+ *     until the next system reset.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_LK field. */
+#define PORT_RD_PCR_LK(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_LK_MASK) >> PORT_PCR_LK_SHIFT)
+#define PORT_BRD_PCR_LK(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_LK_SHIFT))
+
+/*! @brief Set the LK field to a new value. */
+#define PORT_WR_PCR_LK(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_LK_MASK | PORT_PCR_ISF_MASK), PORT_PCR_LK(value)))
+#define PORT_BWR_PCR_LK(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_LK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field IRQC[19:16] (RW)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * corresponding pin is configured to generate interrupt/DMA request as follows:
+ *
+ * Values:
+ * - 0b0000 - Interrupt/DMA request disabled.
+ * - 0b0001 - DMA request on rising edge.
+ * - 0b0010 - DMA request on falling edge.
+ * - 0b0011 - DMA request on either edge.
+ * - 0b1000 - Interrupt when logic 0.
+ * - 0b1001 - Interrupt on rising-edge.
+ * - 0b1010 - Interrupt on falling-edge.
+ * - 0b1011 - Interrupt on either edge.
+ * - 0b1100 - Interrupt when logic 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_IRQC field. */
+#define PORT_RD_PCR_IRQC(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_IRQC_MASK) >> PORT_PCR_IRQC_SHIFT)
+#define PORT_BRD_PCR_IRQC(base, index) (PORT_RD_PCR_IRQC(base, index))
+
+/*! @brief Set the IRQC field to a new value. */
+#define PORT_WR_PCR_IRQC(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_IRQC_MASK | PORT_PCR_ISF_MASK), PORT_PCR_IRQC(value)))
+#define PORT_BWR_PCR_IRQC(base, index, value) (PORT_WR_PCR_IRQC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ISF[24] (W1C)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Configured interrupt is not detected.
+ * - 0b1 - Configured interrupt is detected. If the pin is configured to
+ *     generate a DMA request, then the corresponding flag will be cleared automatically
+ *     at the completion of the requested DMA transfer. Otherwise, the flag
+ *     remains set until a logic 1 is written to the flag. If the pin is configured
+ *     for a level sensitive interrupt and the pin remains asserted, then the flag
+ *     is set again immediately after it is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ISF field. */
+#define PORT_RD_PCR_ISF(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ISF_MASK) >> PORT_PCR_ISF_SHIFT)
+#define PORT_BRD_PCR_ISF(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT))
+
+/*! @brief Set the ISF field to a new value. */
+#define PORT_WR_PCR_ISF(base, index, value) (PORT_RMW_PCR(base, index, PORT_PCR_ISF_MASK, PORT_PCR_ISF(value)))
+#define PORT_BWR_PCR_ISF(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCLR - Global Pin Control Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCLR - Global Pin Control Low Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCLR register
+ */
+/*@{*/
+#define PORT_RD_GPCLR(base)      (PORT_GPCLR_REG(base))
+#define PORT_WR_GPCLR(base, value) (PORT_GPCLR_REG(base) = (value))
+#define PORT_RMW_GPCLR(base, mask, value) (PORT_WR_GPCLR(base, (PORT_RD_GPCLR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCLR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCLR_GPWD(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWD_MASK, PORT_GPCLR_GPWD(value)))
+#define PORT_BWR_GPCLR_GPWD(base, value) (PORT_WR_GPCLR_GPWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
+ *     the value in GPWD.
+ * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
+ *     value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCLR_GPWE(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWE_MASK, PORT_GPCLR_GPWE(value)))
+#define PORT_BWR_GPCLR_GPWE(base, value) (PORT_WR_GPCLR_GPWE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCHR - Global Pin Control High Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCHR - Global Pin Control High Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCHR register
+ */
+/*@{*/
+#define PORT_RD_GPCHR(base)      (PORT_GPCHR_REG(base))
+#define PORT_WR_GPCHR(base, value) (PORT_GPCHR_REG(base) = (value))
+#define PORT_RMW_GPCHR(base, mask, value) (PORT_WR_GPCHR(base, (PORT_RD_GPCHR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCHR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCHR_GPWD(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWD_MASK, PORT_GPCHR_GPWD(value)))
+#define PORT_BWR_GPCHR_GPWD(base, value) (PORT_WR_GPCHR_GPWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
+ *     the value in GPWD.
+ * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
+ *     value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCHR_GPWE(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWE_MASK, PORT_GPCHR_GPWE(value)))
+#define PORT_BWR_GPCHR_GPWE(base, value) (PORT_WR_GPCHR_GPWE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_ISFR - Interrupt Status Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_ISFR - Interrupt Status Flag Register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * Interrupt Status Flag for each pin is also visible in the corresponding Pin
+ * Control Register, and each flag can be cleared in either location.
+ */
+/*!
+ * @name Constants and macros for entire PORT_ISFR register
+ */
+/*@{*/
+#define PORT_RD_ISFR(base)       (PORT_ISFR_REG(base))
+#define PORT_WR_ISFR(base, value) (PORT_ISFR_REG(base) = (value))
+#define PORT_RMW_ISFR(base, mask, value) (PORT_WR_ISFR(base, (PORT_RD_ISFR(base) & ~(mask)) | (value)))
+#define PORT_SET_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) |  (value)))
+#define PORT_CLR_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) & ~(value)))
+#define PORT_TOG_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFER - Digital Filter Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFER - Digital Filter Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The corresponding bit is read only for pins that do not support a digital
+ * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
+ * the pins that support digital filter. The digital filter configuration is valid
+ * in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFER register
+ */
+/*@{*/
+#define PORT_RD_DFER(base)       (PORT_DFER_REG(base))
+#define PORT_WR_DFER(base, value) (PORT_DFER_REG(base) = (value))
+#define PORT_RMW_DFER(base, mask, value) (PORT_WR_DFER(base, (PORT_RD_DFER(base) & ~(mask)) | (value)))
+#define PORT_SET_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) |  (value)))
+#define PORT_CLR_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) & ~(value)))
+#define PORT_TOG_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFCR - Digital Filter Clock Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFCR - Digital Filter Clock Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFCR register
+ */
+/*@{*/
+#define PORT_RD_DFCR(base)       (PORT_DFCR_REG(base))
+#define PORT_WR_DFCR(base, value) (PORT_DFCR_REG(base) = (value))
+#define PORT_RMW_DFCR(base, mask, value) (PORT_WR_DFCR(base, (PORT_RD_DFCR(base) & ~(mask)) | (value)))
+#define PORT_SET_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) |  (value)))
+#define PORT_CLR_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) & ~(value)))
+#define PORT_TOG_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_DFCR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFCR, field CS[0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the clock source for the digital input filters. Changing the filter
+ * clock source must be done only when all digital filters are disabled.
+ *
+ * Values:
+ * - 0b0 - Digital filters are clocked by the bus clock.
+ * - 0b1 - Digital filters are clocked by the 1 kHz LPO clock.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_DFCR_CS field. */
+#define PORT_RD_DFCR_CS(base) ((PORT_DFCR_REG(base) & PORT_DFCR_CS_MASK) >> PORT_DFCR_CS_SHIFT)
+#define PORT_BRD_DFCR_CS(base) (BITBAND_ACCESS32(&PORT_DFCR_REG(base), PORT_DFCR_CS_SHIFT))
+
+/*! @brief Set the CS field to a new value. */
+#define PORT_WR_DFCR_CS(base, value) (PORT_RMW_DFCR(base, PORT_DFCR_CS_MASK, PORT_DFCR_CS(value)))
+#define PORT_BWR_DFCR_CS(base, value) (BITBAND_ACCESS32(&PORT_DFCR_REG(base), PORT_DFCR_CS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFWR - Digital Filter Width Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFWR - Digital Filter Width Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFWR register
+ */
+/*@{*/
+#define PORT_RD_DFWR(base)       (PORT_DFWR_REG(base))
+#define PORT_WR_DFWR(base, value) (PORT_DFWR_REG(base) = (value))
+#define PORT_RMW_DFWR(base, mask, value) (PORT_WR_DFWR(base, (PORT_RD_DFWR(base) & ~(mask)) | (value)))
+#define PORT_SET_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) |  (value)))
+#define PORT_CLR_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) & ~(value)))
+#define PORT_TOG_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_DFWR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFWR, field FILT[4:0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the maximum size of the glitches, in clock cycles, that the digital
+ * filter absorbs for the enabled digital filters. Glitches that are longer than
+ * this register setting will pass through the digital filter, and glitches that
+ * are equal to or less than this register setting are filtered. Changing the
+ * filter length must be done only after all filters are disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_DFWR_FILT field. */
+#define PORT_RD_DFWR_FILT(base) ((PORT_DFWR_REG(base) & PORT_DFWR_FILT_MASK) >> PORT_DFWR_FILT_SHIFT)
+#define PORT_BRD_DFWR_FILT(base) (PORT_RD_DFWR_FILT(base))
+
+/*! @brief Set the FILT field to a new value. */
+#define PORT_WR_DFWR_FILT(base, value) (PORT_RMW_DFWR(base, PORT_DFWR_FILT_MASK, PORT_DFWR_FILT(value)))
+#define PORT_BWR_DFWR_FILT(base, value) (PORT_WR_DFWR_FILT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 RCM
+ *
+ * Reset Control Module
+ *
+ * Registers defined in this header file:
+ * - RCM_SRS0 - System Reset Status Register 0
+ * - RCM_SRS1 - System Reset Status Register 1
+ * - RCM_RPFC - Reset Pin Filter Control register
+ * - RCM_RPFW - Reset Pin Filter Width register
+ * - RCM_MR - Mode Register
+ */
+
+#define RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */
+#define RCM_IDX (0U) /*!< Instance number for RCM. */
+
+/*******************************************************************************
+ * RCM_SRS0 - System Reset Status Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS0 - System Reset Status Register 0 (RO)
+ *
+ * Reset value: 0x82U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
+ * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS0 register
+ */
+/*@{*/
+#define RCM_RD_SRS0(base)        (RCM_SRS0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS0 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS0, field WAKEUP[0] (RO)
+ *
+ * Indicates a reset has been caused by an enabled LLWU module wakeup source
+ * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
+ * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
+ * mode causes a reset. This bit is cleared by any reset except WAKEUP.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by LLWU module wakeup source
+ * - 0b1 - Reset caused by LLWU module wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WAKEUP field. */
+#define RCM_RD_SRS0_WAKEUP(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WAKEUP_MASK) >> RCM_SRS0_WAKEUP_SHIFT)
+#define RCM_BRD_SRS0_WAKEUP(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_WAKEUP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LVD[1] (RO)
+ *
+ * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
+ * an LVD reset occurs. This field is also set by POR.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by LVD trip or POR
+ * - 0b1 - Reset caused by LVD trip or POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LVD field. */
+#define RCM_RD_SRS0_LVD(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LVD_MASK) >> RCM_SRS0_LVD_SHIFT)
+#define RCM_BRD_SRS0_LVD(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LVD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LOC[2] (RO)
+ *
+ * Indicates a reset has been caused by a loss of external clock. The MCG clock
+ * monitor must be enabled for a loss of clock to be detected. Refer to the
+ * detailed MCG description for information on enabling the clock monitor.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by a loss of external clock.
+ * - 0b1 - Reset caused by a loss of external clock.
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LOC field. */
+#define RCM_RD_SRS0_LOC(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOC_MASK) >> RCM_SRS0_LOC_SHIFT)
+#define RCM_BRD_SRS0_LOC(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LOC_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LOL[3] (RO)
+ *
+ * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
+ * MCG description for information on the loss-of-clock event.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by a loss of lock in the PLL
+ * - 0b1 - Reset caused by a loss of lock in the PLL
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LOL field. */
+#define RCM_RD_SRS0_LOL(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOL_MASK) >> RCM_SRS0_LOL_SHIFT)
+#define RCM_BRD_SRS0_LOL(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LOL_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field WDOG[5] (RO)
+ *
+ * Indicates a reset has been caused by the watchdog timer Computer Operating
+ * Properly (COP) timing out. This reset source can be blocked by disabling the COP
+ * watchdog: write 00 to SIM_COPCTRL[COPT].
+ *
+ * Values:
+ * - 0b0 - Reset not caused by watchdog timeout
+ * - 0b1 - Reset caused by watchdog timeout
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WDOG field. */
+#define RCM_RD_SRS0_WDOG(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WDOG_MASK) >> RCM_SRS0_WDOG_SHIFT)
+#define RCM_BRD_SRS0_WDOG(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_WDOG_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field PIN[6] (RO)
+ *
+ * Indicates a reset has been caused by an active-low level on the external
+ * RESET pin.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by external reset pin
+ * - 0b1 - Reset caused by external reset pin
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_PIN field. */
+#define RCM_RD_SRS0_PIN(base) ((RCM_SRS0_REG(base) & RCM_SRS0_PIN_MASK) >> RCM_SRS0_PIN_SHIFT)
+#define RCM_BRD_SRS0_PIN(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_PIN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field POR[7] (RO)
+ *
+ * Indicates a reset has been caused by the power-on detection logic. Because
+ * the internal supply voltage was ramping up at the time, the low-voltage reset
+ * (LVD) status bit is also set to indicate that the reset occurred while the
+ * internal supply was below the LVD threshold.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by POR
+ * - 0b1 - Reset caused by POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_POR field. */
+#define RCM_RD_SRS0_POR(base) ((RCM_SRS0_REG(base) & RCM_SRS0_POR_MASK) >> RCM_SRS0_POR_SHIFT)
+#define RCM_BRD_SRS0_POR(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_POR_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_SRS1 - System Reset Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS1 - System Reset Status Register 1 (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS1 register
+ */
+/*@{*/
+#define RCM_RD_SRS1(base)        (RCM_SRS1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS1 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS1, field JTAG[0] (RO)
+ *
+ * Indicates a reset has been caused by JTAG selection of certain IR codes:
+ * EZPORT, EXTEST, HIGHZ, and CLAMP.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by JTAG
+ * - 0b1 - Reset caused by JTAG
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_JTAG field. */
+#define RCM_RD_SRS1_JTAG(base) ((RCM_SRS1_REG(base) & RCM_SRS1_JTAG_MASK) >> RCM_SRS1_JTAG_SHIFT)
+#define RCM_BRD_SRS1_JTAG(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_JTAG_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field LOCKUP[1] (RO)
+ *
+ * Indicates a reset has been caused by the ARM core indication of a LOCKUP
+ * event.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by core LOCKUP event
+ * - 0b1 - Reset caused by core LOCKUP event
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_LOCKUP field. */
+#define RCM_RD_SRS1_LOCKUP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_LOCKUP_MASK) >> RCM_SRS1_LOCKUP_SHIFT)
+#define RCM_BRD_SRS1_LOCKUP(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_LOCKUP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SW[2] (RO)
+ *
+ * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
+ * Application Interrupt and Reset Control Register in the ARM core.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by software setting of SYSRESETREQ bit
+ * - 0b1 - Reset caused by software setting of SYSRESETREQ bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SW field. */
+#define RCM_RD_SRS1_SW(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SW_MASK) >> RCM_SRS1_SW_SHIFT)
+#define RCM_BRD_SRS1_SW(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_SW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field MDM_AP[3] (RO)
+ *
+ * Indicates a reset has been caused by the host debugger system setting of the
+ * System Reset Request bit in the MDM-AP Control Register.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by host debugger system setting of the System Reset
+ *     Request bit
+ * - 0b1 - Reset caused by host debugger system setting of the System Reset
+ *     Request bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_MDM_AP field. */
+#define RCM_RD_SRS1_MDM_AP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_MDM_AP_MASK) >> RCM_SRS1_MDM_AP_SHIFT)
+#define RCM_BRD_SRS1_MDM_AP(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_MDM_AP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field EZPT[4] (RO)
+ *
+ * Indicates a reset has been caused by EzPort receiving the RESET command while
+ * the device is in EzPort mode.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by EzPort receiving the RESET command while the
+ *     device is in EzPort mode
+ * - 0b1 - Reset caused by EzPort receiving the RESET command while the device
+ *     is in EzPort mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_EZPT field. */
+#define RCM_RD_SRS1_EZPT(base) ((RCM_SRS1_REG(base) & RCM_SRS1_EZPT_MASK) >> RCM_SRS1_EZPT_SHIFT)
+#define RCM_BRD_SRS1_EZPT(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_EZPT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SACKERR[5] (RO)
+ *
+ * Indicates that after an attempt to enter Stop mode, a reset has been caused
+ * by a failure of one or more peripherals to acknowledge within approximately one
+ * second to enter stop mode.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by peripheral failure to acknowledge attempt to
+ *     enter stop mode
+ * - 0b1 - Reset caused by peripheral failure to acknowledge attempt to enter
+ *     stop mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SACKERR field. */
+#define RCM_RD_SRS1_SACKERR(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SACKERR_MASK) >> RCM_SRS1_SACKERR_SHIFT)
+#define RCM_BRD_SRS1_SACKERR(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_SACKERR_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFC - Reset Pin Filter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFC - Reset Pin Filter Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
+ * other reset types. The bus clock filter is reset when disabled or when entering
+ * stop mode. The LPO filter is reset when disabled or when entering any low
+ * leakage stop mode .
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFC register
+ */
+/*@{*/
+#define RCM_RD_RPFC(base)        (RCM_RPFC_REG(base))
+#define RCM_WR_RPFC(base, value) (RCM_RPFC_REG(base) = (value))
+#define RCM_RMW_RPFC(base, mask, value) (RCM_WR_RPFC(base, (RCM_RD_RPFC(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) |  (value)))
+#define RCM_CLR_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) & ~(value)))
+#define RCM_TOG_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFC bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
+ *
+ * Selects how the reset pin filter is enabled in run and wait modes.
+ *
+ * Values:
+ * - 0b00 - All filtering disabled
+ * - 0b01 - Bus clock filter enabled for normal operation
+ * - 0b10 - LPO clock filter enabled for normal operation
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */
+#define RCM_RD_RPFC_RSTFLTSRW(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSRW_MASK) >> RCM_RPFC_RSTFLTSRW_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSRW(base) (RCM_RD_RPFC_RSTFLTSRW(base))
+
+/*! @brief Set the RSTFLTSRW field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSRW(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSRW_MASK, RCM_RPFC_RSTFLTSRW(value)))
+#define RCM_BWR_RPFC_RSTFLTSRW(base, value) (RCM_WR_RPFC_RSTFLTSRW(base, value))
+/*@}*/
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
+ *
+ * Selects how the reset pin filter is enabled in Stop and VLPS modes
+ *
+ * Values:
+ * - 0b0 - All filtering disabled
+ * - 0b1 - LPO clock filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */
+#define RCM_RD_RPFC_RSTFLTSS(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSS_MASK) >> RCM_RPFC_RSTFLTSS_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSS(base) (BITBAND_ACCESS8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT))
+
+/*! @brief Set the RSTFLTSS field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSS(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSS_MASK, RCM_RPFC_RSTFLTSS(value)))
+#define RCM_BWR_RPFC_RSTFLTSS(base, value) (BITBAND_ACCESS8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFW - Reset Pin Filter Width register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFW - Reset Pin Filter Width register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
+ * They are unaffected by other reset types.
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFW register
+ */
+/*@{*/
+#define RCM_RD_RPFW(base)        (RCM_RPFW_REG(base))
+#define RCM_WR_RPFW(base, value) (RCM_RPFW_REG(base) = (value))
+#define RCM_RMW_RPFW(base, mask, value) (RCM_WR_RPFW(base, (RCM_RD_RPFW(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) |  (value)))
+#define RCM_CLR_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) & ~(value)))
+#define RCM_TOG_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFW bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
+ *
+ * Selects the reset pin bus clock filter width.
+ *
+ * Values:
+ * - 0b00000 - Bus clock filter count is 1
+ * - 0b00001 - Bus clock filter count is 2
+ * - 0b00010 - Bus clock filter count is 3
+ * - 0b00011 - Bus clock filter count is 4
+ * - 0b00100 - Bus clock filter count is 5
+ * - 0b00101 - Bus clock filter count is 6
+ * - 0b00110 - Bus clock filter count is 7
+ * - 0b00111 - Bus clock filter count is 8
+ * - 0b01000 - Bus clock filter count is 9
+ * - 0b01001 - Bus clock filter count is 10
+ * - 0b01010 - Bus clock filter count is 11
+ * - 0b01011 - Bus clock filter count is 12
+ * - 0b01100 - Bus clock filter count is 13
+ * - 0b01101 - Bus clock filter count is 14
+ * - 0b01110 - Bus clock filter count is 15
+ * - 0b01111 - Bus clock filter count is 16
+ * - 0b10000 - Bus clock filter count is 17
+ * - 0b10001 - Bus clock filter count is 18
+ * - 0b10010 - Bus clock filter count is 19
+ * - 0b10011 - Bus clock filter count is 20
+ * - 0b10100 - Bus clock filter count is 21
+ * - 0b10101 - Bus clock filter count is 22
+ * - 0b10110 - Bus clock filter count is 23
+ * - 0b10111 - Bus clock filter count is 24
+ * - 0b11000 - Bus clock filter count is 25
+ * - 0b11001 - Bus clock filter count is 26
+ * - 0b11010 - Bus clock filter count is 27
+ * - 0b11011 - Bus clock filter count is 28
+ * - 0b11100 - Bus clock filter count is 29
+ * - 0b11101 - Bus clock filter count is 30
+ * - 0b11110 - Bus clock filter count is 31
+ * - 0b11111 - Bus clock filter count is 32
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */
+#define RCM_RD_RPFW_RSTFLTSEL(base) ((RCM_RPFW_REG(base) & RCM_RPFW_RSTFLTSEL_MASK) >> RCM_RPFW_RSTFLTSEL_SHIFT)
+#define RCM_BRD_RPFW_RSTFLTSEL(base) (RCM_RD_RPFW_RSTFLTSEL(base))
+
+/*! @brief Set the RSTFLTSEL field to a new value. */
+#define RCM_WR_RPFW_RSTFLTSEL(base, value) (RCM_RMW_RPFW(base, RCM_RPFW_RSTFLTSEL_MASK, RCM_RPFW_RSTFLTSEL(value)))
+#define RCM_BWR_RPFW_RSTFLTSEL(base, value) (RCM_WR_RPFW_RSTFLTSEL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_MR - Mode Register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_MR - Mode Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the state of the
+ * mode pins during the last Chip Reset.
+ */
+/*!
+ * @name Constants and macros for entire RCM_MR register
+ */
+/*@{*/
+#define RCM_RD_MR(base)          (RCM_MR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_MR bitfields
+ */
+
+/*!
+ * @name Register RCM_MR, field EZP_MS[1] (RO)
+ *
+ * Reflects the state of the EZP_MS pin during the last Chip Reset
+ *
+ * Values:
+ * - 0b0 - Pin deasserted (logic 1)
+ * - 0b1 - Pin asserted (logic 0)
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_MR_EZP_MS field. */
+#define RCM_RD_MR_EZP_MS(base) ((RCM_MR_REG(base) & RCM_MR_EZP_MS_MASK) >> RCM_MR_EZP_MS_SHIFT)
+#define RCM_BRD_MR_EZP_MS(base) (BITBAND_ACCESS8(&RCM_MR_REG(base), RCM_MR_EZP_MS_SHIFT))
+/*@}*/
+
+/*
+ * MK64F12 RFSYS
+ *
+ * System register file
+ *
+ * Registers defined in this header file:
+ * - RFSYS_REG - Register file register
+ */
+
+#define RFSYS_INSTANCE_COUNT (1U) /*!< Number of instances of the RFSYS module. */
+#define RFSYS_IDX (0U) /*!< Instance number for RFSYS. */
+
+/*******************************************************************************
+ * RFSYS_REG - Register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFSYS_REG - Register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFSYS_REG register
+ */
+/*@{*/
+#define RFSYS_RD_REG(base, index) (RFSYS_REG_REG(base, index))
+#define RFSYS_WR_REG(base, index, value) (RFSYS_REG_REG(base, index) = (value))
+#define RFSYS_RMW_REG(base, index, mask, value) (RFSYS_WR_REG(base, index, (RFSYS_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFSYS_SET_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) |  (value)))
+#define RFSYS_CLR_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) & ~(value)))
+#define RFSYS_TOG_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFSYS_REG bitfields
+ */
+
+/*!
+ * @name Register RFSYS_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LL field. */
+#define RFSYS_RD_REG_LL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LL_MASK) >> RFSYS_REG_LL_SHIFT)
+#define RFSYS_BRD_REG_LL(base, index) (RFSYS_RD_REG_LL(base, index))
+
+/*! @brief Set the LL field to a new value. */
+#define RFSYS_WR_REG_LL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LL_MASK, RFSYS_REG_LL(value)))
+#define RFSYS_BWR_REG_LL(base, index, value) (RFSYS_WR_REG_LL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LH field. */
+#define RFSYS_RD_REG_LH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LH_MASK) >> RFSYS_REG_LH_SHIFT)
+#define RFSYS_BRD_REG_LH(base, index) (RFSYS_RD_REG_LH(base, index))
+
+/*! @brief Set the LH field to a new value. */
+#define RFSYS_WR_REG_LH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LH_MASK, RFSYS_REG_LH(value)))
+#define RFSYS_BWR_REG_LH(base, index, value) (RFSYS_WR_REG_LH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HL field. */
+#define RFSYS_RD_REG_HL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HL_MASK) >> RFSYS_REG_HL_SHIFT)
+#define RFSYS_BRD_REG_HL(base, index) (RFSYS_RD_REG_HL(base, index))
+
+/*! @brief Set the HL field to a new value. */
+#define RFSYS_WR_REG_HL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HL_MASK, RFSYS_REG_HL(value)))
+#define RFSYS_BWR_REG_HL(base, index, value) (RFSYS_WR_REG_HL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HH field. */
+#define RFSYS_RD_REG_HH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HH_MASK) >> RFSYS_REG_HH_SHIFT)
+#define RFSYS_BRD_REG_HH(base, index) (RFSYS_RD_REG_HH(base, index))
+
+/*! @brief Set the HH field to a new value. */
+#define RFSYS_WR_REG_HH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HH_MASK, RFSYS_REG_HH(value)))
+#define RFSYS_BWR_REG_HH(base, index, value) (RFSYS_WR_REG_HH(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 RFVBAT
+ *
+ * VBAT register file
+ *
+ * Registers defined in this header file:
+ * - RFVBAT_REG - VBAT register file register
+ */
+
+#define RFVBAT_INSTANCE_COUNT (1U) /*!< Number of instances of the RFVBAT module. */
+#define RFVBAT_IDX (0U) /*!< Instance number for RFVBAT. */
+
+/*******************************************************************************
+ * RFVBAT_REG - VBAT register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFVBAT_REG - VBAT register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFVBAT_REG register
+ */
+/*@{*/
+#define RFVBAT_RD_REG(base, index) (RFVBAT_REG_REG(base, index))
+#define RFVBAT_WR_REG(base, index, value) (RFVBAT_REG_REG(base, index) = (value))
+#define RFVBAT_RMW_REG(base, index, mask, value) (RFVBAT_WR_REG(base, index, (RFVBAT_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFVBAT_SET_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) |  (value)))
+#define RFVBAT_CLR_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) & ~(value)))
+#define RFVBAT_TOG_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFVBAT_REG bitfields
+ */
+
+/*!
+ * @name Register RFVBAT_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_LL field. */
+#define RFVBAT_RD_REG_LL(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_LL_MASK) >> RFVBAT_REG_LL_SHIFT)
+#define RFVBAT_BRD_REG_LL(base, index) (RFVBAT_RD_REG_LL(base, index))
+
+/*! @brief Set the LL field to a new value. */
+#define RFVBAT_WR_REG_LL(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_LL_MASK, RFVBAT_REG_LL(value)))
+#define RFVBAT_BWR_REG_LL(base, index, value) (RFVBAT_WR_REG_LL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_LH field. */
+#define RFVBAT_RD_REG_LH(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_LH_MASK) >> RFVBAT_REG_LH_SHIFT)
+#define RFVBAT_BRD_REG_LH(base, index) (RFVBAT_RD_REG_LH(base, index))
+
+/*! @brief Set the LH field to a new value. */
+#define RFVBAT_WR_REG_LH(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_LH_MASK, RFVBAT_REG_LH(value)))
+#define RFVBAT_BWR_REG_LH(base, index, value) (RFVBAT_WR_REG_LH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_HL field. */
+#define RFVBAT_RD_REG_HL(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_HL_MASK) >> RFVBAT_REG_HL_SHIFT)
+#define RFVBAT_BRD_REG_HL(base, index) (RFVBAT_RD_REG_HL(base, index))
+
+/*! @brief Set the HL field to a new value. */
+#define RFVBAT_WR_REG_HL(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_HL_MASK, RFVBAT_REG_HL(value)))
+#define RFVBAT_BWR_REG_HL(base, index, value) (RFVBAT_WR_REG_HL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_HH field. */
+#define RFVBAT_RD_REG_HH(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_HH_MASK) >> RFVBAT_REG_HH_SHIFT)
+#define RFVBAT_BRD_REG_HH(base, index) (RFVBAT_RD_REG_HH(base, index))
+
+/*! @brief Set the HH field to a new value. */
+#define RFVBAT_WR_REG_HH(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_HH_MASK, RFVBAT_REG_HH(value)))
+#define RFVBAT_BWR_REG_HH(base, index, value) (RFVBAT_WR_REG_HH(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 RNG
+ *
+ * Random Number Generator Accelerator
+ *
+ * Registers defined in this header file:
+ * - RNG_CR - RNGA Control Register
+ * - RNG_SR - RNGA Status Register
+ * - RNG_ER - RNGA Entropy Register
+ * - RNG_OR - RNGA Output Register
+ */
+
+#define RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
+#define RNG_IDX (0U) /*!< Instance number for RNG. */
+
+/*******************************************************************************
+ * RNG_CR - RNGA Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_CR - RNGA Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the operation of RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_CR register
+ */
+/*@{*/
+#define RNG_RD_CR(base)          (RNG_CR_REG(base))
+#define RNG_WR_CR(base, value)   (RNG_CR_REG(base) = (value))
+#define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value)))
+#define RNG_SET_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) |  (value)))
+#define RNG_CLR_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) & ~(value)))
+#define RNG_TOG_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RNG_CR bitfields
+ */
+
+/*!
+ * @name Register RNG_CR, field GO[0] (RW)
+ *
+ * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
+ * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
+ * OR[RANDOUT] with data.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_GO field. */
+#define RNG_RD_CR_GO(base)   ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT)
+#define RNG_BRD_CR_GO(base)  (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_GO_SHIFT))
+
+/*! @brief Set the GO field to a new value. */
+#define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value)))
+#define RNG_BWR_CR_GO(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_GO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field HA[1] (RW)
+ *
+ * Enables notification of security violations (via SR[SECV]). A security
+ * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
+ * After enabling notification of security violations, you must reset RNGA to
+ * disable them again.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_HA field. */
+#define RNG_RD_CR_HA(base)   ((RNG_CR_REG(base) & RNG_CR_HA_MASK) >> RNG_CR_HA_SHIFT)
+#define RNG_BRD_CR_HA(base)  (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_HA_SHIFT))
+
+/*! @brief Set the HA field to a new value. */
+#define RNG_WR_CR_HA(base, value) (RNG_RMW_CR(base, RNG_CR_HA_MASK, RNG_CR_HA(value)))
+#define RNG_BWR_CR_HA(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_HA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field INTM[2] (RW)
+ *
+ * Masks the triggering of an error interrupt to the interrupt controller when
+ * an OR underflow condition occurs. An OR underflow condition occurs when you
+ * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
+ *
+ * Values:
+ * - 0b0 - Not masked
+ * - 0b1 - Masked
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_INTM field. */
+#define RNG_RD_CR_INTM(base) ((RNG_CR_REG(base) & RNG_CR_INTM_MASK) >> RNG_CR_INTM_SHIFT)
+#define RNG_BRD_CR_INTM(base) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_INTM_SHIFT))
+
+/*! @brief Set the INTM field to a new value. */
+#define RNG_WR_CR_INTM(base, value) (RNG_RMW_CR(base, RNG_CR_INTM_MASK, RNG_CR_INTM(value)))
+#define RNG_BWR_CR_INTM(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_INTM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field CLRI[3] (WORZ)
+ *
+ * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
+ *
+ * Values:
+ * - 0b0 - Do not clear the interrupt.
+ * - 0b1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
+ *     the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
+ */
+/*@{*/
+/*! @brief Set the CLRI field to a new value. */
+#define RNG_WR_CR_CLRI(base, value) (RNG_RMW_CR(base, RNG_CR_CLRI_MASK, RNG_CR_CLRI(value)))
+#define RNG_BWR_CR_CLRI(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_CLRI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field SLP[4] (RW)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_SLP field. */
+#define RNG_RD_CR_SLP(base)  ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT)
+#define RNG_BRD_CR_SLP(base) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_SLP_SHIFT))
+
+/*! @brief Set the SLP field to a new value. */
+#define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value)))
+#define RNG_BWR_CR_SLP(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_SLP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_SR - RNGA Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_SR - RNGA Status Register (RO)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Indicates the status of RNGA. This register is read-only.
+ */
+/*!
+ * @name Constants and macros for entire RNG_SR register
+ */
+/*@{*/
+#define RNG_RD_SR(base)          (RNG_SR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RNG_SR bitfields
+ */
+
+/*!
+ * @name Register RNG_SR, field SECV[0] (RO)
+ *
+ * Used only when high assurance is enabled (CR[HA]). Indicates that a security
+ * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
+ * RNGA.
+ *
+ * Values:
+ * - 0b0 - No security violation
+ * - 0b1 - Security violation
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SECV field. */
+#define RNG_RD_SR_SECV(base) ((RNG_SR_REG(base) & RNG_SR_SECV_MASK) >> RNG_SR_SECV_SHIFT)
+#define RNG_BRD_SR_SECV(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_SECV_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field LRS[1] (RO)
+ *
+ * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
+ * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
+ * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
+ * After you read this register, RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_LRS field. */
+#define RNG_RD_SR_LRS(base)  ((RNG_SR_REG(base) & RNG_SR_LRS_MASK) >> RNG_SR_LRS_SHIFT)
+#define RNG_BRD_SR_LRS(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_LRS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field ORU[2] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last read
+ * this register (SR) or RNGA was reset, regardless of whether the error
+ * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
+ * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
+ * field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_ORU field. */
+#define RNG_RD_SR_ORU(base)  ((RNG_SR_REG(base) & RNG_SR_ORU_MASK) >> RNG_SR_ORU_SHIFT)
+#define RNG_BRD_SR_ORU(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_ORU_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field ERRI[3] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last
+ * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
+ * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
+ * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
+ * indicator (via CR[CLRI]), RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_ERRI field. */
+#define RNG_RD_SR_ERRI(base) ((RNG_SR_REG(base) & RNG_SR_ERRI_MASK) >> RNG_SR_ERRI_SHIFT)
+#define RNG_BRD_SR_ERRI(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_ERRI_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field SLP[4] (RO)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SLP field. */
+#define RNG_RD_SR_SLP(base)  ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT)
+#define RNG_BRD_SR_SLP(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_SLP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
+ *
+ * Indicates the number of random-data words that are in OR[RANDOUT], which
+ * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
+ * is not 0, then the contents of a random number contained in OR[RANDOUT] are
+ * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
+ *
+ * Values:
+ * - 0b00000000 - No words (empty)
+ * - 0b00000001 - One word (valid)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_LVL field. */
+#define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT)
+#define RNG_BRD_SR_OREG_LVL(base) (RNG_RD_SR_OREG_LVL(base))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
+ *
+ * Indicates the size of the Output (OR) register in terms of the number of
+ * 32-bit random-data words it can hold.
+ *
+ * Values:
+ * - 0b00000001 - One word (this value is fixed)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
+#define RNG_RD_SR_OREG_SIZE(base) ((RNG_SR_REG(base) & RNG_SR_OREG_SIZE_MASK) >> RNG_SR_OREG_SIZE_SHIFT)
+#define RNG_BRD_SR_OREG_SIZE(base) (RNG_RD_SR_OREG_SIZE(base))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_ER - RNGA Entropy Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_ER - RNGA Entropy Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies an entropy value that RNGA uses in addition to its ring oscillators
+ * to seed its pseudorandom algorithm. This is a write-only register; reads
+ * return all zeros.
+ */
+/*!
+ * @name Constants and macros for entire RNG_ER register
+ */
+/*@{*/
+#define RNG_RD_ER(base)          (RNG_ER_REG(base))
+#define RNG_WR_ER(base, value)   (RNG_ER_REG(base) = (value))
+#define RNG_RMW_ER(base, mask, value) (RNG_WR_ER(base, (RNG_RD_ER(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_OR - RNGA Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_OR - RNGA Output Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Stores a random-data word generated by RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_OR register
+ */
+/*@{*/
+#define RNG_RD_OR(base)          (RNG_OR_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 RTC
+ *
+ * Secure Real Time Clock
+ *
+ * Registers defined in this header file:
+ * - RTC_TSR - RTC Time Seconds Register
+ * - RTC_TPR - RTC Time Prescaler Register
+ * - RTC_TAR - RTC Time Alarm Register
+ * - RTC_TCR - RTC Time Compensation Register
+ * - RTC_CR - RTC Control Register
+ * - RTC_SR - RTC Status Register
+ * - RTC_LR - RTC Lock Register
+ * - RTC_IER - RTC Interrupt Enable Register
+ * - RTC_WAR - RTC Write Access Register
+ * - RTC_RAR - RTC Read Access Register
+ */
+
+#define RTC_INSTANCE_COUNT (1U) /*!< Number of instances of the RTC module. */
+#define RTC_IDX (0U) /*!< Instance number for RTC. */
+
+/*******************************************************************************
+ * RTC_TSR - RTC Time Seconds Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TSR - RTC Time Seconds Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TSR register
+ */
+/*@{*/
+#define RTC_RD_TSR(base)         (RTC_TSR_REG(base))
+#define RTC_WR_TSR(base, value)  (RTC_TSR_REG(base) = (value))
+#define RTC_RMW_TSR(base, mask, value) (RTC_WR_TSR(base, (RTC_RD_TSR(base) & ~(mask)) | (value)))
+#define RTC_SET_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) |  (value)))
+#define RTC_CLR_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) & ~(value)))
+#define RTC_TOG_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TPR - RTC Time Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TPR - RTC Time Prescaler Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TPR register
+ */
+/*@{*/
+#define RTC_RD_TPR(base)         (RTC_TPR_REG(base))
+#define RTC_WR_TPR(base, value)  (RTC_TPR_REG(base) = (value))
+#define RTC_RMW_TPR(base, mask, value) (RTC_WR_TPR(base, (RTC_RD_TPR(base) & ~(mask)) | (value)))
+#define RTC_SET_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) |  (value)))
+#define RTC_CLR_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) & ~(value)))
+#define RTC_TOG_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TPR bitfields
+ */
+
+/*!
+ * @name Register RTC_TPR, field TPR[15:0] (RW)
+ *
+ * When the time counter is enabled, the TPR is read only and increments every
+ * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
+ * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
+ * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
+ * to a logic zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TPR_TPR field. */
+#define RTC_RD_TPR_TPR(base) ((RTC_TPR_REG(base) & RTC_TPR_TPR_MASK) >> RTC_TPR_TPR_SHIFT)
+#define RTC_BRD_TPR_TPR(base) (RTC_RD_TPR_TPR(base))
+
+/*! @brief Set the TPR field to a new value. */
+#define RTC_WR_TPR_TPR(base, value) (RTC_RMW_TPR(base, RTC_TPR_TPR_MASK, RTC_TPR_TPR(value)))
+#define RTC_BWR_TPR_TPR(base, value) (RTC_WR_TPR_TPR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TAR - RTC Time Alarm Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TAR - RTC Time Alarm Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TAR register
+ */
+/*@{*/
+#define RTC_RD_TAR(base)         (RTC_TAR_REG(base))
+#define RTC_WR_TAR(base, value)  (RTC_TAR_REG(base) = (value))
+#define RTC_RMW_TAR(base, mask, value) (RTC_WR_TAR(base, (RTC_RD_TAR(base) & ~(mask)) | (value)))
+#define RTC_SET_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) |  (value)))
+#define RTC_CLR_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) & ~(value)))
+#define RTC_TOG_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TCR - RTC Time Compensation Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TCR - RTC Time Compensation Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TCR register
+ */
+/*@{*/
+#define RTC_RD_TCR(base)         (RTC_TCR_REG(base))
+#define RTC_WR_TCR(base, value)  (RTC_TCR_REG(base) = (value))
+#define RTC_RMW_TCR(base, mask, value) (RTC_WR_TCR(base, (RTC_RD_TCR(base) & ~(mask)) | (value)))
+#define RTC_SET_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) |  (value)))
+#define RTC_CLR_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) & ~(value)))
+#define RTC_TOG_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TCR bitfields
+ */
+
+/*!
+ * @name Register RTC_TCR, field TCR[7:0] (RW)
+ *
+ * Configures the number of 32.768 kHz clock cycles in each second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ *
+ * Values:
+ * - 0b10000000 - Time Prescaler Register overflows every 32896 clock cycles.
+ * - 0b11111111 - Time Prescaler Register overflows every 32769 clock cycles.
+ * - 0b00000000 - Time Prescaler Register overflows every 32768 clock cycles.
+ * - 0b00000001 - Time Prescaler Register overflows every 32767 clock cycles.
+ * - 0b01111111 - Time Prescaler Register overflows every 32641 clock cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCR field. */
+#define RTC_RD_TCR_TCR(base) ((RTC_TCR_REG(base) & RTC_TCR_TCR_MASK) >> RTC_TCR_TCR_SHIFT)
+#define RTC_BRD_TCR_TCR(base) (RTC_RD_TCR_TCR(base))
+
+/*! @brief Set the TCR field to a new value. */
+#define RTC_WR_TCR_TCR(base, value) (RTC_RMW_TCR(base, RTC_TCR_TCR_MASK, RTC_TCR_TCR(value)))
+#define RTC_BWR_TCR_TCR(base, value) (RTC_WR_TCR_TCR(base, value))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIR[15:8] (RW)
+ *
+ * Configures the compensation interval in seconds from 1 to 256 to control how
+ * frequently the TCR should adjust the number of 32.768 kHz cycles in each
+ * second. The value written should be one less than the number of seconds. For
+ * example, write zero to configure for a compensation interval of one second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIR field. */
+#define RTC_RD_TCR_CIR(base) ((RTC_TCR_REG(base) & RTC_TCR_CIR_MASK) >> RTC_TCR_CIR_SHIFT)
+#define RTC_BRD_TCR_CIR(base) (RTC_RD_TCR_CIR(base))
+
+/*! @brief Set the CIR field to a new value. */
+#define RTC_WR_TCR_CIR(base, value) (RTC_RMW_TCR(base, RTC_TCR_CIR_MASK, RTC_TCR_CIR(value)))
+#define RTC_BWR_TCR_CIR(base, value) (RTC_WR_TCR_CIR(base, value))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field TCV[23:16] (RO)
+ *
+ * Current value used by the compensation logic for the present second interval.
+ * Updated once a second if the CIC equals 0 with the contents of the TCR field.
+ * If the CIC does not equal zero then it is loaded with zero (compensation is
+ * not enabled for that second increment).
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCV field. */
+#define RTC_RD_TCR_TCV(base) ((RTC_TCR_REG(base) & RTC_TCR_TCV_MASK) >> RTC_TCR_TCV_SHIFT)
+#define RTC_BRD_TCR_TCV(base) (RTC_RD_TCR_TCV(base))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIC[31:24] (RO)
+ *
+ * Current value of the compensation interval counter. If the compensation
+ * interval counter equals zero then it is loaded with the contents of the CIR. If the
+ * CIC does not equal zero then it is decremented once a second.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIC field. */
+#define RTC_RD_TCR_CIC(base) ((RTC_TCR_REG(base) & RTC_TCR_CIC_MASK) >> RTC_TCR_CIC_SHIFT)
+#define RTC_BRD_TCR_CIC(base) (RTC_RD_TCR_CIC(base))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_CR - RTC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_CR - RTC Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_CR register
+ */
+/*@{*/
+#define RTC_RD_CR(base)          (RTC_CR_REG(base))
+#define RTC_WR_CR(base, value)   (RTC_CR_REG(base) = (value))
+#define RTC_RMW_CR(base, mask, value) (RTC_WR_CR(base, (RTC_RD_CR(base) & ~(mask)) | (value)))
+#define RTC_SET_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) |  (value)))
+#define RTC_CLR_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) & ~(value)))
+#define RTC_TOG_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_CR bitfields
+ */
+
+/*!
+ * @name Register RTC_CR, field SWR[0] (RW)
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
+ *     RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
+ *     explicitly clearing it.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SWR field. */
+#define RTC_RD_CR_SWR(base)  ((RTC_CR_REG(base) & RTC_CR_SWR_MASK) >> RTC_CR_SWR_SHIFT)
+#define RTC_BRD_CR_SWR(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT))
+
+/*! @brief Set the SWR field to a new value. */
+#define RTC_WR_CR_SWR(base, value) (RTC_RMW_CR(base, RTC_CR_SWR_MASK, RTC_CR_SWR(value)))
+#define RTC_BWR_CR_SWR(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPE[1] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0b0 - Wakeup pin is disabled.
+ * - 0b1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPE field. */
+#define RTC_RD_CR_WPE(base)  ((RTC_CR_REG(base) & RTC_CR_WPE_MASK) >> RTC_CR_WPE_SHIFT)
+#define RTC_BRD_CR_WPE(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT))
+
+/*! @brief Set the WPE field to a new value. */
+#define RTC_WR_CR_WPE(base, value) (RTC_RMW_CR(base, RTC_CR_WPE_MASK, RTC_CR_WPE(value)))
+#define RTC_BWR_CR_WPE(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SUP[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Non-supervisor mode write accesses are not supported and generate a
+ *     bus error.
+ * - 0b1 - Non-supervisor mode write accesses are supported.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SUP field. */
+#define RTC_RD_CR_SUP(base)  ((RTC_CR_REG(base) & RTC_CR_SUP_MASK) >> RTC_CR_SUP_SHIFT)
+#define RTC_BRD_CR_SUP(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT))
+
+/*! @brief Set the SUP field to a new value. */
+#define RTC_WR_CR_SUP(base, value) (RTC_RMW_CR(base, RTC_CR_SUP_MASK, RTC_CR_SUP(value)))
+#define RTC_BWR_CR_SUP(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field UM[3] (RW)
+ *
+ * Allows SR[TCE] to be written even when the Status Register is locked. When
+ * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
+ * the SR[TCE] is clear.
+ *
+ * Values:
+ * - 0b0 - Registers cannot be written when locked.
+ * - 0b1 - Registers can be written when locked under limited conditions.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_UM field. */
+#define RTC_RD_CR_UM(base)   ((RTC_CR_REG(base) & RTC_CR_UM_MASK) >> RTC_CR_UM_SHIFT)
+#define RTC_BRD_CR_UM(base)  (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT))
+
+/*! @brief Set the UM field to a new value. */
+#define RTC_WR_CR_UM(base, value) (RTC_RMW_CR(base, RTC_CR_UM_MASK, RTC_CR_UM(value)))
+#define RTC_BWR_CR_UM(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPS[4] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0b0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ * - 0b1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup
+ *     pin is turned on and the 32kHz clock is output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPS field. */
+#define RTC_RD_CR_WPS(base)  ((RTC_CR_REG(base) & RTC_CR_WPS_MASK) >> RTC_CR_WPS_SHIFT)
+#define RTC_BRD_CR_WPS(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT))
+
+/*! @brief Set the WPS field to a new value. */
+#define RTC_WR_CR_WPS(base, value) (RTC_RMW_CR(base, RTC_CR_WPS_MASK, RTC_CR_WPS(value)))
+#define RTC_BWR_CR_WPS(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field OSCE[8] (RW)
+ *
+ * Values:
+ * - 0b0 - 32.768 kHz oscillator is disabled.
+ * - 0b1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
+ *     oscillator startup time before enabling the time counter to allow the 32.768
+ *     kHz clock time to stabilize.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_OSCE field. */
+#define RTC_RD_CR_OSCE(base) ((RTC_CR_REG(base) & RTC_CR_OSCE_MASK) >> RTC_CR_OSCE_SHIFT)
+#define RTC_BRD_CR_OSCE(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT))
+
+/*! @brief Set the OSCE field to a new value. */
+#define RTC_WR_CR_OSCE(base, value) (RTC_RMW_CR(base, RTC_CR_OSCE_MASK, RTC_CR_OSCE(value)))
+#define RTC_BWR_CR_OSCE(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field CLKO[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The 32 kHz clock is output to other peripherals.
+ * - 0b1 - The 32 kHz clock is not output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_CLKO field. */
+#define RTC_RD_CR_CLKO(base) ((RTC_CR_REG(base) & RTC_CR_CLKO_MASK) >> RTC_CR_CLKO_SHIFT)
+#define RTC_BRD_CR_CLKO(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT))
+
+/*! @brief Set the CLKO field to a new value. */
+#define RTC_WR_CR_CLKO(base, value) (RTC_RMW_CR(base, RTC_CR_CLKO_MASK, RTC_CR_CLKO(value)))
+#define RTC_BWR_CR_CLKO(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC16P[10] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC16P field. */
+#define RTC_RD_CR_SC16P(base) ((RTC_CR_REG(base) & RTC_CR_SC16P_MASK) >> RTC_CR_SC16P_SHIFT)
+#define RTC_BRD_CR_SC16P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT))
+
+/*! @brief Set the SC16P field to a new value. */
+#define RTC_WR_CR_SC16P(base, value) (RTC_RMW_CR(base, RTC_CR_SC16P_MASK, RTC_CR_SC16P(value)))
+#define RTC_BWR_CR_SC16P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC8P[11] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC8P field. */
+#define RTC_RD_CR_SC8P(base) ((RTC_CR_REG(base) & RTC_CR_SC8P_MASK) >> RTC_CR_SC8P_SHIFT)
+#define RTC_BRD_CR_SC8P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT))
+
+/*! @brief Set the SC8P field to a new value. */
+#define RTC_WR_CR_SC8P(base, value) (RTC_RMW_CR(base, RTC_CR_SC8P_MASK, RTC_CR_SC8P(value)))
+#define RTC_BWR_CR_SC8P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC4P[12] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC4P field. */
+#define RTC_RD_CR_SC4P(base) ((RTC_CR_REG(base) & RTC_CR_SC4P_MASK) >> RTC_CR_SC4P_SHIFT)
+#define RTC_BRD_CR_SC4P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT))
+
+/*! @brief Set the SC4P field to a new value. */
+#define RTC_WR_CR_SC4P(base, value) (RTC_RMW_CR(base, RTC_CR_SC4P_MASK, RTC_CR_SC4P(value)))
+#define RTC_BWR_CR_SC4P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC2P[13] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC2P field. */
+#define RTC_RD_CR_SC2P(base) ((RTC_CR_REG(base) & RTC_CR_SC2P_MASK) >> RTC_CR_SC2P_SHIFT)
+#define RTC_BRD_CR_SC2P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT))
+
+/*! @brief Set the SC2P field to a new value. */
+#define RTC_WR_CR_SC2P(base, value) (RTC_RMW_CR(base, RTC_CR_SC2P_MASK, RTC_CR_SC2P(value)))
+#define RTC_BWR_CR_SC2P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_SR - RTC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_SR - RTC Status Register (RW)
+ *
+ * Reset value: 0x00000001U
+ */
+/*!
+ * @name Constants and macros for entire RTC_SR register
+ */
+/*@{*/
+#define RTC_RD_SR(base)          (RTC_SR_REG(base))
+#define RTC_WR_SR(base, value)   (RTC_SR_REG(base) = (value))
+#define RTC_RMW_SR(base, mask, value) (RTC_WR_SR(base, (RTC_RD_SR(base) & ~(mask)) | (value)))
+#define RTC_SET_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) |  (value)))
+#define RTC_CLR_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) & ~(value)))
+#define RTC_TOG_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_SR bitfields
+ */
+
+/*!
+ * @name Register RTC_SR, field TIF[0] (RO)
+ *
+ * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
+ * do not increment and read as zero when this bit is set. This bit is cleared by
+ * writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0b0 - Time is valid.
+ * - 0b1 - Time is invalid and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TIF field. */
+#define RTC_RD_SR_TIF(base)  ((RTC_SR_REG(base) & RTC_SR_TIF_MASK) >> RTC_SR_TIF_SHIFT)
+#define RTC_BRD_SR_TIF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TIF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TOF[1] (RO)
+ *
+ * Time overflow flag is set when the time counter is enabled and overflows. The
+ * TSR and TPR do not increment and read as zero when this bit is set. This bit
+ * is cleared by writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0b0 - Time overflow has not occurred.
+ * - 0b1 - Time overflow has occurred and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TOF field. */
+#define RTC_RD_SR_TOF(base)  ((RTC_SR_REG(base) & RTC_SR_TOF_MASK) >> RTC_SR_TOF_SHIFT)
+#define RTC_BRD_SR_TOF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TOF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TAF[2] (RO)
+ *
+ * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
+ * increments. This bit is cleared by writing the TAR register.
+ *
+ * Values:
+ * - 0b0 - Time alarm has not occurred.
+ * - 0b1 - Time alarm has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TAF field. */
+#define RTC_RD_SR_TAF(base)  ((RTC_SR_REG(base) & RTC_SR_TAF_MASK) >> RTC_SR_TAF_SHIFT)
+#define RTC_BRD_SR_TAF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TAF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TCE[4] (RW)
+ *
+ * When time counter is disabled the TSR register and TPR register are
+ * writeable, but do not increment. When time counter is enabled the TSR register and TPR
+ * register are not writeable, but increment.
+ *
+ * Values:
+ * - 0b0 - Time counter is disabled.
+ * - 0b1 - Time counter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TCE field. */
+#define RTC_RD_SR_TCE(base)  ((RTC_SR_REG(base) & RTC_SR_TCE_MASK) >> RTC_SR_TCE_SHIFT)
+#define RTC_BRD_SR_TCE(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT))
+
+/*! @brief Set the TCE field to a new value. */
+#define RTC_WR_SR_TCE(base, value) (RTC_RMW_SR(base, RTC_SR_TCE_MASK, RTC_SR_TCE(value)))
+#define RTC_BWR_SR_TCE(base, value) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_LR - RTC Lock Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_LR - RTC Lock Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_LR register
+ */
+/*@{*/
+#define RTC_RD_LR(base)          (RTC_LR_REG(base))
+#define RTC_WR_LR(base, value)   (RTC_LR_REG(base) = (value))
+#define RTC_RMW_LR(base, mask, value) (RTC_WR_LR(base, (RTC_RD_LR(base) & ~(mask)) | (value)))
+#define RTC_SET_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) |  (value)))
+#define RTC_CLR_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) & ~(value)))
+#define RTC_TOG_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_LR bitfields
+ */
+
+/*!
+ * @name Register RTC_LR, field TCL[3] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Time Compensation Register is locked and writes are ignored.
+ * - 0b1 - Time Compensation Register is not locked and writes complete as
+ *     normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_TCL field. */
+#define RTC_RD_LR_TCL(base)  ((RTC_LR_REG(base) & RTC_LR_TCL_MASK) >> RTC_LR_TCL_SHIFT)
+#define RTC_BRD_LR_TCL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT))
+
+/*! @brief Set the TCL field to a new value. */
+#define RTC_WR_LR_TCL(base, value) (RTC_RMW_LR(base, RTC_LR_TCL_MASK, RTC_LR_TCL(value)))
+#define RTC_BWR_LR_TCL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field CRL[4] (RW)
+ *
+ * After being cleared, this bit can only be set by VBAT POR.
+ *
+ * Values:
+ * - 0b0 - Control Register is locked and writes are ignored.
+ * - 0b1 - Control Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_CRL field. */
+#define RTC_RD_LR_CRL(base)  ((RTC_LR_REG(base) & RTC_LR_CRL_MASK) >> RTC_LR_CRL_SHIFT)
+#define RTC_BRD_LR_CRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT))
+
+/*! @brief Set the CRL field to a new value. */
+#define RTC_WR_LR_CRL(base, value) (RTC_RMW_LR(base, RTC_LR_CRL_MASK, RTC_LR_CRL(value)))
+#define RTC_BWR_LR_CRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field SRL[5] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Status Register is locked and writes are ignored.
+ * - 0b1 - Status Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_SRL field. */
+#define RTC_RD_LR_SRL(base)  ((RTC_LR_REG(base) & RTC_LR_SRL_MASK) >> RTC_LR_SRL_SHIFT)
+#define RTC_BRD_LR_SRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT))
+
+/*! @brief Set the SRL field to a new value. */
+#define RTC_WR_LR_SRL(base, value) (RTC_RMW_LR(base, RTC_LR_SRL_MASK, RTC_LR_SRL(value)))
+#define RTC_BWR_LR_SRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field LRL[6] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Lock Register is locked and writes are ignored.
+ * - 0b1 - Lock Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_LRL field. */
+#define RTC_RD_LR_LRL(base)  ((RTC_LR_REG(base) & RTC_LR_LRL_MASK) >> RTC_LR_LRL_SHIFT)
+#define RTC_BRD_LR_LRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT))
+
+/*! @brief Set the LRL field to a new value. */
+#define RTC_WR_LR_LRL(base, value) (RTC_RMW_LR(base, RTC_LR_LRL_MASK, RTC_LR_LRL(value)))
+#define RTC_BWR_LR_LRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_IER - RTC Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_IER - RTC Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00000007U
+ */
+/*!
+ * @name Constants and macros for entire RTC_IER register
+ */
+/*@{*/
+#define RTC_RD_IER(base)         (RTC_IER_REG(base))
+#define RTC_WR_IER(base, value)  (RTC_IER_REG(base) = (value))
+#define RTC_RMW_IER(base, mask, value) (RTC_WR_IER(base, (RTC_RD_IER(base) & ~(mask)) | (value)))
+#define RTC_SET_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) |  (value)))
+#define RTC_CLR_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) & ~(value)))
+#define RTC_TOG_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_IER bitfields
+ */
+
+/*!
+ * @name Register RTC_IER, field TIIE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Time invalid flag does not generate an interrupt.
+ * - 0b1 - Time invalid flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TIIE field. */
+#define RTC_RD_IER_TIIE(base) ((RTC_IER_REG(base) & RTC_IER_TIIE_MASK) >> RTC_IER_TIIE_SHIFT)
+#define RTC_BRD_IER_TIIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT))
+
+/*! @brief Set the TIIE field to a new value. */
+#define RTC_WR_IER_TIIE(base, value) (RTC_RMW_IER(base, RTC_IER_TIIE_MASK, RTC_IER_TIIE(value)))
+#define RTC_BWR_IER_TIIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TOIE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Time overflow flag does not generate an interrupt.
+ * - 0b1 - Time overflow flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TOIE field. */
+#define RTC_RD_IER_TOIE(base) ((RTC_IER_REG(base) & RTC_IER_TOIE_MASK) >> RTC_IER_TOIE_SHIFT)
+#define RTC_BRD_IER_TOIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT))
+
+/*! @brief Set the TOIE field to a new value. */
+#define RTC_WR_IER_TOIE(base, value) (RTC_RMW_IER(base, RTC_IER_TOIE_MASK, RTC_IER_TOIE(value)))
+#define RTC_BWR_IER_TOIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TAIE[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Time alarm flag does not generate an interrupt.
+ * - 0b1 - Time alarm flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TAIE field. */
+#define RTC_RD_IER_TAIE(base) ((RTC_IER_REG(base) & RTC_IER_TAIE_MASK) >> RTC_IER_TAIE_SHIFT)
+#define RTC_BRD_IER_TAIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT))
+
+/*! @brief Set the TAIE field to a new value. */
+#define RTC_WR_IER_TAIE(base, value) (RTC_RMW_IER(base, RTC_IER_TAIE_MASK, RTC_IER_TAIE(value)))
+#define RTC_BWR_IER_TAIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TSIE[4] (RW)
+ *
+ * The seconds interrupt is an edge-sensitive interrupt with a dedicated
+ * interrupt vector. It is generated once a second and requires no software overhead
+ * (there is no corresponding status flag to clear).
+ *
+ * Values:
+ * - 0b0 - Seconds interrupt is disabled.
+ * - 0b1 - Seconds interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TSIE field. */
+#define RTC_RD_IER_TSIE(base) ((RTC_IER_REG(base) & RTC_IER_TSIE_MASK) >> RTC_IER_TSIE_SHIFT)
+#define RTC_BRD_IER_TSIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT))
+
+/*! @brief Set the TSIE field to a new value. */
+#define RTC_WR_IER_TSIE(base, value) (RTC_RMW_IER(base, RTC_IER_TSIE_MASK, RTC_IER_TSIE(value)))
+#define RTC_BWR_IER_TSIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field WPON[7] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices. Whenever the
+ * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - If the wakeup pin is enabled, then the wakeup pin will assert.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_WPON field. */
+#define RTC_RD_IER_WPON(base) ((RTC_IER_REG(base) & RTC_IER_WPON_MASK) >> RTC_IER_WPON_SHIFT)
+#define RTC_BRD_IER_WPON(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT))
+
+/*! @brief Set the WPON field to a new value. */
+#define RTC_WR_IER_WPON(base, value) (RTC_RMW_IER(base, RTC_IER_WPON_MASK, RTC_IER_WPON(value)))
+#define RTC_BWR_IER_WPON(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_WAR - RTC Write Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_WAR - RTC Write Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_WAR register
+ */
+/*@{*/
+#define RTC_RD_WAR(base)         (RTC_WAR_REG(base))
+#define RTC_WR_WAR(base, value)  (RTC_WAR_REG(base) = (value))
+#define RTC_RMW_WAR(base, mask, value) (RTC_WR_WAR(base, (RTC_RD_WAR(base) & ~(mask)) | (value)))
+#define RTC_SET_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) |  (value)))
+#define RTC_CLR_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) & ~(value)))
+#define RTC_TOG_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_WAR bitfields
+ */
+
+/*!
+ * @name Register RTC_WAR, field TSRW[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Seconds Register are ignored.
+ * - 0b1 - Writes to the Time Seconds Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TSRW field. */
+#define RTC_RD_WAR_TSRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TSRW_MASK) >> RTC_WAR_TSRW_SHIFT)
+#define RTC_BRD_WAR_TSRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TSRW_SHIFT))
+
+/*! @brief Set the TSRW field to a new value. */
+#define RTC_WR_WAR_TSRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TSRW_MASK, RTC_WAR_TSRW(value)))
+#define RTC_BWR_WAR_TSRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TSRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TPRW[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Prescaler Register are ignored.
+ * - 0b1 - Writes to the Time Prescaler Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TPRW field. */
+#define RTC_RD_WAR_TPRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TPRW_MASK) >> RTC_WAR_TPRW_SHIFT)
+#define RTC_BRD_WAR_TPRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TPRW_SHIFT))
+
+/*! @brief Set the TPRW field to a new value. */
+#define RTC_WR_WAR_TPRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TPRW_MASK, RTC_WAR_TPRW(value)))
+#define RTC_BWR_WAR_TPRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TPRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TARW[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Alarm Register are ignored.
+ * - 0b1 - Writes to the Time Alarm Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TARW field. */
+#define RTC_RD_WAR_TARW(base) ((RTC_WAR_REG(base) & RTC_WAR_TARW_MASK) >> RTC_WAR_TARW_SHIFT)
+#define RTC_BRD_WAR_TARW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TARW_SHIFT))
+
+/*! @brief Set the TARW field to a new value. */
+#define RTC_WR_WAR_TARW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TARW_MASK, RTC_WAR_TARW(value)))
+#define RTC_BWR_WAR_TARW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TARW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TCRW[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Compensation Register are ignored.
+ * - 0b1 - Writes to the Time Compensation Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TCRW field. */
+#define RTC_RD_WAR_TCRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TCRW_MASK) >> RTC_WAR_TCRW_SHIFT)
+#define RTC_BRD_WAR_TCRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TCRW_SHIFT))
+
+/*! @brief Set the TCRW field to a new value. */
+#define RTC_WR_WAR_TCRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TCRW_MASK, RTC_WAR_TCRW(value)))
+#define RTC_BWR_WAR_TCRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TCRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field CRW[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Control Register are ignored.
+ * - 0b1 - Writes to the Control Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_CRW field. */
+#define RTC_RD_WAR_CRW(base) ((RTC_WAR_REG(base) & RTC_WAR_CRW_MASK) >> RTC_WAR_CRW_SHIFT)
+#define RTC_BRD_WAR_CRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_CRW_SHIFT))
+
+/*! @brief Set the CRW field to a new value. */
+#define RTC_WR_WAR_CRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_CRW_MASK, RTC_WAR_CRW(value)))
+#define RTC_BWR_WAR_CRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_CRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field SRW[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Status Register are ignored.
+ * - 0b1 - Writes to the Status Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_SRW field. */
+#define RTC_RD_WAR_SRW(base) ((RTC_WAR_REG(base) & RTC_WAR_SRW_MASK) >> RTC_WAR_SRW_SHIFT)
+#define RTC_BRD_WAR_SRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_SRW_SHIFT))
+
+/*! @brief Set the SRW field to a new value. */
+#define RTC_WR_WAR_SRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_SRW_MASK, RTC_WAR_SRW(value)))
+#define RTC_BWR_WAR_SRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_SRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field LRW[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Lock Register are ignored.
+ * - 0b1 - Writes to the Lock Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_LRW field. */
+#define RTC_RD_WAR_LRW(base) ((RTC_WAR_REG(base) & RTC_WAR_LRW_MASK) >> RTC_WAR_LRW_SHIFT)
+#define RTC_BRD_WAR_LRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_LRW_SHIFT))
+
+/*! @brief Set the LRW field to a new value. */
+#define RTC_WR_WAR_LRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_LRW_MASK, RTC_WAR_LRW(value)))
+#define RTC_BWR_WAR_LRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_LRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field IERW[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Interupt Enable Register are ignored.
+ * - 0b1 - Writes to the Interrupt Enable Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_IERW field. */
+#define RTC_RD_WAR_IERW(base) ((RTC_WAR_REG(base) & RTC_WAR_IERW_MASK) >> RTC_WAR_IERW_SHIFT)
+#define RTC_BRD_WAR_IERW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_IERW_SHIFT))
+
+/*! @brief Set the IERW field to a new value. */
+#define RTC_WR_WAR_IERW(base, value) (RTC_RMW_WAR(base, RTC_WAR_IERW_MASK, RTC_WAR_IERW(value)))
+#define RTC_BWR_WAR_IERW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_IERW_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_RAR - RTC Read Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_RAR - RTC Read Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_RAR register
+ */
+/*@{*/
+#define RTC_RD_RAR(base)         (RTC_RAR_REG(base))
+#define RTC_WR_RAR(base, value)  (RTC_RAR_REG(base) = (value))
+#define RTC_RMW_RAR(base, mask, value) (RTC_WR_RAR(base, (RTC_RD_RAR(base) & ~(mask)) | (value)))
+#define RTC_SET_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) |  (value)))
+#define RTC_CLR_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) & ~(value)))
+#define RTC_TOG_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_RAR bitfields
+ */
+
+/*!
+ * @name Register RTC_RAR, field TSRR[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Seconds Register are ignored.
+ * - 0b1 - Reads to the Time Seconds Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TSRR field. */
+#define RTC_RD_RAR_TSRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TSRR_MASK) >> RTC_RAR_TSRR_SHIFT)
+#define RTC_BRD_RAR_TSRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TSRR_SHIFT))
+
+/*! @brief Set the TSRR field to a new value. */
+#define RTC_WR_RAR_TSRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TSRR_MASK, RTC_RAR_TSRR(value)))
+#define RTC_BWR_RAR_TSRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TSRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TPRR[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Pprescaler Register are ignored.
+ * - 0b1 - Reads to the Time Prescaler Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TPRR field. */
+#define RTC_RD_RAR_TPRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TPRR_MASK) >> RTC_RAR_TPRR_SHIFT)
+#define RTC_BRD_RAR_TPRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TPRR_SHIFT))
+
+/*! @brief Set the TPRR field to a new value. */
+#define RTC_WR_RAR_TPRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TPRR_MASK, RTC_RAR_TPRR(value)))
+#define RTC_BWR_RAR_TPRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TPRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TARR[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Alarm Register are ignored.
+ * - 0b1 - Reads to the Time Alarm Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TARR field. */
+#define RTC_RD_RAR_TARR(base) ((RTC_RAR_REG(base) & RTC_RAR_TARR_MASK) >> RTC_RAR_TARR_SHIFT)
+#define RTC_BRD_RAR_TARR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TARR_SHIFT))
+
+/*! @brief Set the TARR field to a new value. */
+#define RTC_WR_RAR_TARR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TARR_MASK, RTC_RAR_TARR(value)))
+#define RTC_BWR_RAR_TARR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TARR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TCRR[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Compensation Register are ignored.
+ * - 0b1 - Reads to the Time Compensation Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TCRR field. */
+#define RTC_RD_RAR_TCRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TCRR_MASK) >> RTC_RAR_TCRR_SHIFT)
+#define RTC_BRD_RAR_TCRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TCRR_SHIFT))
+
+/*! @brief Set the TCRR field to a new value. */
+#define RTC_WR_RAR_TCRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TCRR_MASK, RTC_RAR_TCRR(value)))
+#define RTC_BWR_RAR_TCRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TCRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field CRR[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Control Register are ignored.
+ * - 0b1 - Reads to the Control Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_CRR field. */
+#define RTC_RD_RAR_CRR(base) ((RTC_RAR_REG(base) & RTC_RAR_CRR_MASK) >> RTC_RAR_CRR_SHIFT)
+#define RTC_BRD_RAR_CRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_CRR_SHIFT))
+
+/*! @brief Set the CRR field to a new value. */
+#define RTC_WR_RAR_CRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_CRR_MASK, RTC_RAR_CRR(value)))
+#define RTC_BWR_RAR_CRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_CRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field SRR[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Status Register are ignored.
+ * - 0b1 - Reads to the Status Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_SRR field. */
+#define RTC_RD_RAR_SRR(base) ((RTC_RAR_REG(base) & RTC_RAR_SRR_MASK) >> RTC_RAR_SRR_SHIFT)
+#define RTC_BRD_RAR_SRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_SRR_SHIFT))
+
+/*! @brief Set the SRR field to a new value. */
+#define RTC_WR_RAR_SRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_SRR_MASK, RTC_RAR_SRR(value)))
+#define RTC_BWR_RAR_SRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_SRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field LRR[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Lock Register are ignored.
+ * - 0b1 - Reads to the Lock Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_LRR field. */
+#define RTC_RD_RAR_LRR(base) ((RTC_RAR_REG(base) & RTC_RAR_LRR_MASK) >> RTC_RAR_LRR_SHIFT)
+#define RTC_BRD_RAR_LRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_LRR_SHIFT))
+
+/*! @brief Set the LRR field to a new value. */
+#define RTC_WR_RAR_LRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_LRR_MASK, RTC_RAR_LRR(value)))
+#define RTC_BWR_RAR_LRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_LRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field IERR[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Interrupt Enable Register are ignored.
+ * - 0b1 - Reads to the Interrupt Enable Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_IERR field. */
+#define RTC_RD_RAR_IERR(base) ((RTC_RAR_REG(base) & RTC_RAR_IERR_MASK) >> RTC_RAR_IERR_SHIFT)
+#define RTC_BRD_RAR_IERR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_IERR_SHIFT))
+
+/*! @brief Set the IERR field to a new value. */
+#define RTC_WR_RAR_IERR(base, value) (RTC_RMW_RAR(base, RTC_RAR_IERR_MASK, RTC_RAR_IERR(value)))
+#define RTC_BWR_RAR_IERR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_IERR_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 SDHC
+ *
+ * Secured Digital Host Controller
+ *
+ * Registers defined in this header file:
+ * - SDHC_DSADDR - DMA System Address register
+ * - SDHC_BLKATTR - Block Attributes register
+ * - SDHC_CMDARG - Command Argument register
+ * - SDHC_XFERTYP - Transfer Type register
+ * - SDHC_CMDRSP - Command Response 0
+ * - SDHC_DATPORT - Buffer Data Port register
+ * - SDHC_PRSSTAT - Present State register
+ * - SDHC_PROCTL - Protocol Control register
+ * - SDHC_SYSCTL - System Control register
+ * - SDHC_IRQSTAT - Interrupt Status register
+ * - SDHC_IRQSTATEN - Interrupt Status Enable register
+ * - SDHC_IRQSIGEN - Interrupt Signal Enable register
+ * - SDHC_AC12ERR - Auto CMD12 Error Status Register
+ * - SDHC_HTCAPBLT - Host Controller Capabilities
+ * - SDHC_WML - Watermark Level Register
+ * - SDHC_FEVT - Force Event register
+ * - SDHC_ADMAES - ADMA Error Status register
+ * - SDHC_ADSADDR - ADMA System Addressregister
+ * - SDHC_VENDOR - Vendor Specific register
+ * - SDHC_MMCBOOT - MMC Boot register
+ * - SDHC_HOSTVER - Host Controller Version
+ */
+
+#define SDHC_INSTANCE_COUNT (1U) /*!< Number of instances of the SDHC module. */
+#define SDHC_IDX (0U) /*!< Instance number for SDHC. */
+
+/*******************************************************************************
+ * SDHC_DSADDR - DMA System Address register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_DSADDR - DMA System Address register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for DMA
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_DSADDR register
+ */
+/*@{*/
+#define SDHC_RD_DSADDR(base)     (SDHC_DSADDR_REG(base))
+#define SDHC_WR_DSADDR(base, value) (SDHC_DSADDR_REG(base) = (value))
+#define SDHC_RMW_DSADDR(base, mask, value) (SDHC_WR_DSADDR(base, (SDHC_RD_DSADDR(base) & ~(mask)) | (value)))
+#define SDHC_SET_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) |  (value)))
+#define SDHC_CLR_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) & ~(value)))
+#define SDHC_TOG_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_DSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
+ *
+ * Contains the 32-bit system memory address for a DMA transfer. Because the
+ * address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
+ * When the SDHC stops a DMA transfer, this register points to the system address
+ * of the next contiguous data position. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read operation
+ * during transfers may return an invalid value. The host driver shall initialize
+ * this register before starting a DMA transaction. After DMA has stopped, the
+ * system address of the next contiguous data position can be read from this register.
+ * This register is protected during a data transfer. When data lines are
+ * active, write to this register is ignored. The host driver shall wait, until
+ * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
+ * not support a virtual memory system. It supports only continuous physical
+ * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
+ * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
+ * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
+ * automatically alters the value of internal address counter, so SW cannot
+ * change this register when IRQSTAT[TC] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_DSADDR_DSADDR field. */
+#define SDHC_RD_DSADDR_DSADDR(base) ((SDHC_DSADDR_REG(base) & SDHC_DSADDR_DSADDR_MASK) >> SDHC_DSADDR_DSADDR_SHIFT)
+#define SDHC_BRD_DSADDR_DSADDR(base) (SDHC_RD_DSADDR_DSADDR(base))
+
+/*! @brief Set the DSADDR field to a new value. */
+#define SDHC_WR_DSADDR_DSADDR(base, value) (SDHC_RMW_DSADDR(base, SDHC_DSADDR_DSADDR_MASK, SDHC_DSADDR_DSADDR(value)))
+#define SDHC_BWR_DSADDR_DSADDR(base, value) (SDHC_WR_DSADDR_DSADDR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_BLKATTR - Block Attributes register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_BLKATTR - Block Attributes register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to configure the number of data blocks and the number
+ * of bytes in each block.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_BLKATTR register
+ */
+/*@{*/
+#define SDHC_RD_BLKATTR(base)    (SDHC_BLKATTR_REG(base))
+#define SDHC_WR_BLKATTR(base, value) (SDHC_BLKATTR_REG(base) = (value))
+#define SDHC_RMW_BLKATTR(base, mask, value) (SDHC_WR_BLKATTR(base, (SDHC_RD_BLKATTR(base) & ~(mask)) | (value)))
+#define SDHC_SET_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) |  (value)))
+#define SDHC_CLR_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) & ~(value)))
+#define SDHC_TOG_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_BLKATTR bitfields
+ */
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
+ *
+ * Specifies the block size for block data transfers. Values ranging from 1 byte
+ * up to the maximum buffer size can be set. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read
+ * operations during transfers may return an invalid value, and write operations will be
+ * ignored.
+ *
+ * Values:
+ * - 0b0000000000000 - No data transfer.
+ * - 0b0000000000001 - 1 Byte
+ * - 0b0000000000010 - 2 Bytes
+ * - 0b0000000000011 - 3 Bytes
+ * - 0b0000000000100 - 4 Bytes
+ * - 0b0000111111111 - 511 Bytes
+ * - 0b0001000000000 - 512 Bytes
+ * - 0b0100000000000 - 2048 Bytes
+ * - 0b1000000000000 - 4096 Bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field. */
+#define SDHC_RD_BLKATTR_BLKSIZE(base) ((SDHC_BLKATTR_REG(base) & SDHC_BLKATTR_BLKSIZE_MASK) >> SDHC_BLKATTR_BLKSIZE_SHIFT)
+#define SDHC_BRD_BLKATTR_BLKSIZE(base) (SDHC_RD_BLKATTR_BLKSIZE(base))
+
+/*! @brief Set the BLKSIZE field to a new value. */
+#define SDHC_WR_BLKATTR_BLKSIZE(base, value) (SDHC_RMW_BLKATTR(base, SDHC_BLKATTR_BLKSIZE_MASK, SDHC_BLKATTR_BLKSIZE(value)))
+#define SDHC_BWR_BLKATTR_BLKSIZE(base, value) (SDHC_WR_BLKATTR_BLKSIZE(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
+ *
+ * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
+ * multiple block transfers. For single block transfer, this register will
+ * always read as 1. The host driver shall set this register to a value between 1 and
+ * the maximum block count. The SDHC decrements the block count after each block
+ * transfer and stops when the count reaches zero. Setting the block count to 0
+ * results in no data blocks being transferred. This register must be accessed
+ * only when no transaction is executing, that is, after transactions are stopped.
+ * During data transfer, read operations on this register may return an invalid
+ * value and write operations are ignored. When saving transfer content as a result
+ * of a suspend command, the number of blocks yet to be transferred can be
+ * determined by reading this register. The reading of this register must be applied
+ * after transfer is paused by stop at block gap operation and before sending the
+ * command marked as suspend. This is because when suspend command is sent out,
+ * SDHC will regard the current transfer as aborted and change BLKCNT back to its
+ * original value instead of keeping the dynamical indicator of remained block
+ * count. When restoring transfer content prior to issuing a resume command, the
+ * host driver shall restore the previously saved block count. Although the BLKCNT
+ * field is 0 after reset, the read of reset value is 0x1. This is because when
+ * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
+ * BLKCNT is always 1.
+ *
+ * Values:
+ * - 0b0000000000000000 - Stop count.
+ * - 0b0000000000000001 - 1 block
+ * - 0b0000000000000010 - 2 blocks
+ * - 0b1111111111111111 - 65535 blocks
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_BLKATTR_BLKCNT field. */
+#define SDHC_RD_BLKATTR_BLKCNT(base) ((SDHC_BLKATTR_REG(base) & SDHC_BLKATTR_BLKCNT_MASK) >> SDHC_BLKATTR_BLKCNT_SHIFT)
+#define SDHC_BRD_BLKATTR_BLKCNT(base) (SDHC_RD_BLKATTR_BLKCNT(base))
+
+/*! @brief Set the BLKCNT field to a new value. */
+#define SDHC_WR_BLKATTR_BLKCNT(base, value) (SDHC_RMW_BLKATTR(base, SDHC_BLKATTR_BLKCNT_MASK, SDHC_BLKATTR_BLKCNT(value)))
+#define SDHC_BWR_BLKATTR_BLKCNT(base, value) (SDHC_WR_BLKATTR_BLKCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_CMDARG - Command Argument register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_CMDARG - Command Argument register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the SD/MMC command argument.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_CMDARG register
+ */
+/*@{*/
+#define SDHC_RD_CMDARG(base)     (SDHC_CMDARG_REG(base))
+#define SDHC_WR_CMDARG(base, value) (SDHC_CMDARG_REG(base) = (value))
+#define SDHC_RMW_CMDARG(base, mask, value) (SDHC_WR_CMDARG(base, (SDHC_RD_CMDARG(base) & ~(mask)) | (value)))
+#define SDHC_SET_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) |  (value)))
+#define SDHC_CLR_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) & ~(value)))
+#define SDHC_TOG_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_XFERTYP - Transfer Type register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_XFERTYP - Transfer Type register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to control the operation of data transfers. The host
+ * driver shall set this register before issuing a command followed by a data
+ * transfer, or before issuing a resume command. To prevent data loss, the SDHC
+ * prevents writing to the bits that are involved in the data transfer of this
+ * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
+ * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
+ * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
+ * send a command with data by writing to this register is ignored; when
+ * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
+ * data transfer involved, it is mandatory that the block size is nonzero.
+ * Besides, block count must also be nonzero, or indicated as single block transfer
+ * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
+ * this register is 0 when written), otherwise SDHC will ignore the sending of
+ * this command and do nothing. For write command, with all above restrictions, it
+ * is also mandatory that the write protect switch is not active (WPSPL bit of
+ * Present State Register is 1), otherwise SDHC will also ignore the command. If
+ * the commands with data transfer does not receive the response in 64 clock
+ * cycles, that is, response time-out, SDHC will regard the external device does not
+ * accept the command and abort the data transfer. In this scenario, the driver
+ * must issue the command again to retry the transfer. It is also possible that,
+ * for some reason, the card responds to the command but SDHC does not receive the
+ * response, and if it is internal DMA (either simple DMA or ADMA) read
+ * operation, the external system memory is over-written by the internal DMA with data
+ * sent back from the card. The following table shows the summary of how register
+ * settings determine the type of data transfer. Transfer Type register setting for
+ * various transfer types Multi/Single block select Block count enable Block
+ * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
+ * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
+ * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
+ * in regards to XFERTYP[RSPTYP] as well as the name of the response type.
+ * Relationship between parameters and the name of the response type Response type
+ * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
+ * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
+ * the SDIO specification, response type notation for R5b is not defined. R5
+ * includes R5b in the SDIO specification. But R5b is defined in this specification
+ * to specify that the SDHC will check the busy status after receiving a
+ * response. For example, usually CMD52 is used with R5, but the I/O abort command shall
+ * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
+ * The CRC check shall be disabled for these response types.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_XFERTYP register
+ */
+/*@{*/
+#define SDHC_RD_XFERTYP(base)    (SDHC_XFERTYP_REG(base))
+#define SDHC_WR_XFERTYP(base, value) (SDHC_XFERTYP_REG(base) = (value))
+#define SDHC_RMW_XFERTYP(base, mask, value) (SDHC_WR_XFERTYP(base, (SDHC_RD_XFERTYP(base) & ~(mask)) | (value)))
+#define SDHC_SET_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) |  (value)))
+#define SDHC_CLR_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) & ~(value)))
+#define SDHC_TOG_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_XFERTYP bitfields
+ */
+
+/*!
+ * @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
+ *
+ * Enables DMA functionality. If this bit is set to 1, a DMA operation shall
+ * begin when the host driver sets the DPSEL bit of this register. Whether the
+ * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DMAEN field. */
+#define SDHC_RD_XFERTYP_DMAEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DMAEN_MASK) >> SDHC_XFERTYP_DMAEN_SHIFT)
+#define SDHC_BRD_XFERTYP_DMAEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define SDHC_WR_XFERTYP_DMAEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DMAEN_MASK, SDHC_XFERTYP_DMAEN(value)))
+#define SDHC_BWR_XFERTYP_DMAEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field BCEN[1] (RW)
+ *
+ * Used to enable the Block Count register, which is only relevant for multiple
+ * block transfers. When this bit is 0, the internal counter for block is
+ * disabled, which is useful in executing an infinite transfer.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_BCEN field. */
+#define SDHC_RD_XFERTYP_BCEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_BCEN_MASK) >> SDHC_XFERTYP_BCEN_SHIFT)
+#define SDHC_BRD_XFERTYP_BCEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_BCEN_SHIFT))
+
+/*! @brief Set the BCEN field to a new value. */
+#define SDHC_WR_XFERTYP_BCEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_BCEN_MASK, SDHC_XFERTYP_BCEN(value)))
+#define SDHC_BWR_XFERTYP_BCEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_BCEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
+ *
+ * Multiple block transfers for memory require a CMD12 to stop the transaction.
+ * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
+ * last block transfer has completed. The host driver shall not set this bit to
+ * issue commands that do not require CMD12 to stop a multiple block data
+ * transfer. In particular, secure commands defined in File Security Specification (see
+ * reference list) do not require CMD12. In single block transfer, the SDHC will
+ * ignore this bit whether it is set or not.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_AC12EN field. */
+#define SDHC_RD_XFERTYP_AC12EN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_AC12EN_MASK) >> SDHC_XFERTYP_AC12EN_SHIFT)
+#define SDHC_BRD_XFERTYP_AC12EN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_AC12EN_SHIFT))
+
+/*! @brief Set the AC12EN field to a new value. */
+#define SDHC_WR_XFERTYP_AC12EN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_AC12EN_MASK, SDHC_XFERTYP_AC12EN(value)))
+#define SDHC_BWR_XFERTYP_AC12EN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_AC12EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
+ *
+ * Defines the direction of DAT line data transfers. The bit is set to 1 by the
+ * host driver to transfer data from the SD card to the SDHC and is set to 0 for
+ * all other commands.
+ *
+ * Values:
+ * - 0b0 - Write host to card.
+ * - 0b1 - Read card to host.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DTDSEL field. */
+#define SDHC_RD_XFERTYP_DTDSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DTDSEL_MASK) >> SDHC_XFERTYP_DTDSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_DTDSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DTDSEL_SHIFT))
+
+/*! @brief Set the DTDSEL field to a new value. */
+#define SDHC_WR_XFERTYP_DTDSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DTDSEL_MASK, SDHC_XFERTYP_DTDSEL(value)))
+#define SDHC_BWR_XFERTYP_DTDSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DTDSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
+ *
+ * Enables multiple block DAT line data transfers. For any other commands, this
+ * bit shall be set to 0. If this bit is 0, it is not necessary to set the block
+ * count register.
+ *
+ * Values:
+ * - 0b0 - Single block.
+ * - 0b1 - Multiple blocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_MSBSEL field. */
+#define SDHC_RD_XFERTYP_MSBSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_MSBSEL_MASK) >> SDHC_XFERTYP_MSBSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_MSBSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_MSBSEL_SHIFT))
+
+/*! @brief Set the MSBSEL field to a new value. */
+#define SDHC_WR_XFERTYP_MSBSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_MSBSEL_MASK, SDHC_XFERTYP_MSBSEL(value)))
+#define SDHC_BWR_XFERTYP_MSBSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_MSBSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
+ *
+ * Values:
+ * - 0b00 - No response.
+ * - 0b01 - Response length 136.
+ * - 0b10 - Response length 48.
+ * - 0b11 - Response length 48, check busy after response.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_RSPTYP field. */
+#define SDHC_RD_XFERTYP_RSPTYP(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_RSPTYP_MASK) >> SDHC_XFERTYP_RSPTYP_SHIFT)
+#define SDHC_BRD_XFERTYP_RSPTYP(base) (SDHC_RD_XFERTYP_RSPTYP(base))
+
+/*! @brief Set the RSPTYP field to a new value. */
+#define SDHC_WR_XFERTYP_RSPTYP(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_RSPTYP_MASK, SDHC_XFERTYP_RSPTYP(value)))
+#define SDHC_BWR_XFERTYP_RSPTYP(base, value) (SDHC_WR_XFERTYP_RSPTYP(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
+ *
+ * If this bit is set to 1, the SDHC shall check the CRC field in the response.
+ * If an error is detected, it is reported as a Command CRC Error. If this bit is
+ * set to 0, the CRC field is not checked. The number of bits checked by the CRC
+ * field value changes according to the length of the response.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CCCEN field. */
+#define SDHC_RD_XFERTYP_CCCEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CCCEN_MASK) >> SDHC_XFERTYP_CCCEN_SHIFT)
+#define SDHC_BRD_XFERTYP_CCCEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CCCEN_SHIFT))
+
+/*! @brief Set the CCCEN field to a new value. */
+#define SDHC_WR_XFERTYP_CCCEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CCCEN_MASK, SDHC_XFERTYP_CCCEN(value)))
+#define SDHC_BWR_XFERTYP_CCCEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CCCEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CICEN[20] (RW)
+ *
+ * If this bit is set to 1, the SDHC will check the index field in the response
+ * to see if it has the same value as the command index. If it is not, it is
+ * reported as a command index error. If this bit is set to 0, the index field is not
+ * checked.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CICEN field. */
+#define SDHC_RD_XFERTYP_CICEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CICEN_MASK) >> SDHC_XFERTYP_CICEN_SHIFT)
+#define SDHC_BRD_XFERTYP_CICEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CICEN_SHIFT))
+
+/*! @brief Set the CICEN field to a new value. */
+#define SDHC_WR_XFERTYP_CICEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CICEN_MASK, SDHC_XFERTYP_CICEN(value)))
+#define SDHC_BWR_XFERTYP_CICEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CICEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
+ *
+ * This bit is set to 1 to indicate that data is present and shall be
+ * transferred using the DAT line. It is set to 0 for the following: Commands using only
+ * the CMD line, for example: CMD52. Commands with no data transfer, but using the
+ * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
+ * this bit shall be set, and other bits in this register shall be set the same
+ * as when the transfer was initially launched. When the Write Protect switch is
+ * on, that is, the WPSPL bit is active as 0, any command with a write operation
+ * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
+ * 0, writes to the register Transfer Type are ignored.
+ *
+ * Values:
+ * - 0b0 - No data present.
+ * - 0b1 - Data present.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DPSEL field. */
+#define SDHC_RD_XFERTYP_DPSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DPSEL_MASK) >> SDHC_XFERTYP_DPSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_DPSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DPSEL_SHIFT))
+
+/*! @brief Set the DPSEL field to a new value. */
+#define SDHC_WR_XFERTYP_DPSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DPSEL_MASK, SDHC_XFERTYP_DPSEL(value)))
+#define SDHC_BWR_XFERTYP_DPSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DPSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
+ *
+ * There are three types of special commands: suspend, resume, and abort. These
+ * bits shall be set to 00b for all other commands. Suspend command: If the
+ * suspend command succeeds, the SDHC shall assume that the card bus has been released
+ * and that it is possible to issue the next command which uses the DAT line.
+ * Because the SDHC does not monitor the content of command response, it does not
+ * know if the suspend command succeeded or not. It is the host driver's
+ * responsibility to check the status of the suspend command and send another command
+ * marked as suspend to inform the SDHC that a suspend command was successfully
+ * issued. After the end bit of command is sent, the SDHC deasserts read wait for read
+ * transactions and stops checking busy for write transactions. In 4-bit mode,
+ * the interrupt cycle starts. If the suspend command fails, the SDHC will
+ * maintain its current state, and the host driver shall restart the transfer by setting
+ * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
+ * restoring the registers saved before sending the suspend command and then sends
+ * the resume command. The SDHC will check for a pending busy state before
+ * starting write transfers. Abort command: If this command is set when executing a
+ * read transfer, the SDHC will stop reads to the buffer. If this command is set
+ * when executing a write transfer, the SDHC will stop driving the DAT line. After
+ * issuing the abort command, the host driver must issue a software reset (abort
+ * transaction).
+ *
+ * Values:
+ * - 0b00 - Normal other commands.
+ * - 0b01 - Suspend CMD52 for writing bus suspend in CCCR.
+ * - 0b10 - Resume CMD52 for writing function select in CCCR.
+ * - 0b11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CMDTYP field. */
+#define SDHC_RD_XFERTYP_CMDTYP(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CMDTYP_MASK) >> SDHC_XFERTYP_CMDTYP_SHIFT)
+#define SDHC_BRD_XFERTYP_CMDTYP(base) (SDHC_RD_XFERTYP_CMDTYP(base))
+
+/*! @brief Set the CMDTYP field to a new value. */
+#define SDHC_WR_XFERTYP_CMDTYP(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CMDTYP_MASK, SDHC_XFERTYP_CMDTYP(value)))
+#define SDHC_BWR_XFERTYP_CMDTYP(base, value) (SDHC_WR_XFERTYP_CMDTYP(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
+ *
+ * These bits shall be set to the command number that is specified in bits 45-40
+ * of the command-format in the SD Memory Card Physical Layer Specification and
+ * SDIO Card Specification.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CMDINX field. */
+#define SDHC_RD_XFERTYP_CMDINX(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CMDINX_MASK) >> SDHC_XFERTYP_CMDINX_SHIFT)
+#define SDHC_BRD_XFERTYP_CMDINX(base) (SDHC_RD_XFERTYP_CMDINX(base))
+
+/*! @brief Set the CMDINX field to a new value. */
+#define SDHC_WR_XFERTYP_CMDINX(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CMDINX_MASK, SDHC_XFERTYP_CMDINX(value)))
+#define SDHC_BWR_XFERTYP_CMDINX(base, value) (SDHC_WR_XFERTYP_CMDINX(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_CMDRSP - Command Response 0
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_CMDRSP - Command Response 0 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 0 of the response bits from the card.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP register
+ */
+/*@{*/
+#define SDHC_RD_CMDRSP(base, index) (SDHC_CMDRSP_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_DATPORT - Buffer Data Port register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_DATPORT - Buffer Data Port register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This is a 32-bit data port register used to access the internal buffer and it
+ * cannot be updated in Idle mode.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_DATPORT register
+ */
+/*@{*/
+#define SDHC_RD_DATPORT(base)    (SDHC_DATPORT_REG(base))
+#define SDHC_WR_DATPORT(base, value) (SDHC_DATPORT_REG(base) = (value))
+#define SDHC_RMW_DATPORT(base, mask, value) (SDHC_WR_DATPORT(base, (SDHC_RD_DATPORT(base) & ~(mask)) | (value)))
+#define SDHC_SET_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) |  (value)))
+#define SDHC_CLR_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) & ~(value)))
+#define SDHC_TOG_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_PRSSTAT - Present State register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_PRSSTAT - Present State register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The host driver can get status of the SDHC from this 32-bit read-only
+ * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
+ * SDIO) when the DAT lines are busy during a data transfer. These commands can be
+ * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
+ * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
+ * Physical Specification may add other commands to this list in the future.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_PRSSTAT register
+ */
+/*@{*/
+#define SDHC_RD_PRSSTAT(base)    (SDHC_PRSSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_PRSSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
+ *
+ * If this status bit is 0, it indicates that the CMD line is not in use and the
+ * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
+ * immediately after the Transfer Type register is written. This bit is cleared when
+ * the command response is received. Even if the CDIHB bit is set to 1, Commands
+ * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
+ * generates a command complete interrupt in the interrupt status register. If the
+ * SDHC cannot issue the command because of a command conflict error (see
+ * command CRC error) or because of a command not issued by auto CMD12 error, this bit
+ * will remain 1 and the command complete is not set. The status of issuing an
+ * auto CMD12 does not show on this bit.
+ *
+ * Values:
+ * - 0b0 - Can issue command using only CMD line.
+ * - 0b1 - Cannot issue command.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CIHB field. */
+#define SDHC_RD_PRSSTAT_CIHB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CIHB_MASK) >> SDHC_PRSSTAT_CIHB_SHIFT)
+#define SDHC_BRD_PRSSTAT_CIHB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CIHB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
+ *
+ * This status bit is generated if either the DLA or the RTA is set to 1. If
+ * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
+ * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
+ * the case when the command busy is finished, changing from 1 to 0 generates a
+ * transfer complete interrupt in the Interrupt Status register. The SD host
+ * driver can save registers for a suspend transaction after this bit has changed
+ * from 1 to 0.
+ *
+ * Values:
+ * - 0b0 - Can issue command which uses the DAT line.
+ * - 0b1 - Cannot issue command which uses the DAT line.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CDIHB field. */
+#define SDHC_RD_PRSSTAT_CDIHB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CDIHB_MASK) >> SDHC_PRSSTAT_CDIHB_SHIFT)
+#define SDHC_BRD_PRSSTAT_CDIHB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CDIHB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLA[2] (RO)
+ *
+ * Indicates whether one of the DAT lines on the SD bus is in use. In the case
+ * of read transactions: This status indicates whether a read transfer is
+ * executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
+ * generates a block gap event interrupt in the Interrupt Status register. This bit
+ * will be set in either of the following cases: After the end bit of the read
+ * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
+ * will be cleared in either of the following cases: When the end bit of the last
+ * data block is sent from the SD bus to the SDHC. When the read wait state is
+ * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
+ * the next block gap by driving read wait at the start of the interrupt cycle.
+ * If the read wait signal is already driven (data buffer cannot receive data),
+ * the SDHC can wait for a current block gap by continuing to drive the read wait
+ * signal. It is necessary to support read wait to use the suspend / resume
+ * function. This bit will remain 1 during read wait. In the case of write
+ * transactions: This status indicates that a write transfer is executing on the SD bus.
+ * Changes in this value from 1 to 0 generate a transfer complete interrupt in the
+ * interrupt status register. This bit will be set in either of the following
+ * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
+ * continue a write transfer. This bit will be cleared in either of the
+ * following cases: When the SD card releases write busy of the last data block, the SDHC
+ * will also detect if the output is not busy. If the SD card does not drive the
+ * busy signal after the CRC status is received, the SDHC shall assume the card
+ * drive "Not busy". When the SD card releases write busy, prior to waiting for
+ * write transfer, and as a result of a stop at block gap request. In the case of
+ * command with busy pending: This status indicates that a busy state follows the
+ * command and the data line is in use. This bit will be cleared when the DAT0
+ * line is released.
+ *
+ * Values:
+ * - 0b0 - DAT line inactive.
+ * - 0b1 - DAT line active.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_DLA field. */
+#define SDHC_RD_PRSSTAT_DLA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_DLA_MASK) >> SDHC_PRSSTAT_DLA_SHIFT)
+#define SDHC_BRD_PRSSTAT_DLA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_DLA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
+ *
+ * Indicates that the internal card clock is stable. This bit is for the host
+ * driver to poll clock status when changing the clock frequency. It is recommended
+ * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
+ * frequency is changing.
+ *
+ * Values:
+ * - 0b0 - Clock is changing frequency and not stable.
+ * - 0b1 - Clock is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_SDSTB field. */
+#define SDHC_RD_PRSSTAT_SDSTB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_SDSTB_MASK) >> SDHC_PRSSTAT_SDSTB_SHIFT)
+#define SDHC_BRD_PRSSTAT_SDSTB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_SDSTB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
+ *
+ * Indicates that the bus clock is internally gated off. This bit is for the
+ * host driver to debug.
+ *
+ * Values:
+ * - 0b0 - Bus clock is active.
+ * - 0b1 - Bus clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field. */
+#define SDHC_RD_PRSSTAT_IPGOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_IPGOFF_MASK) >> SDHC_PRSSTAT_IPGOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_IPGOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_IPGOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
+ *
+ * Indicates that the system clock is internally gated off. This bit is for the
+ * host driver to debug during a data transfer.
+ *
+ * Values:
+ * - 0b0 - System clock is active.
+ * - 0b1 - System clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field. */
+#define SDHC_RD_PRSSTAT_HCKOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_HCKOFF_MASK) >> SDHC_PRSSTAT_HCKOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_HCKOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_HCKOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
+ *
+ * Indicates that the is internally gated off. This bit is for the host driver
+ * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
+ * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
+ * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
+ * clock SDHC clock bus clock
+ *
+ * Values:
+ * - 0b0 - SDHC clock is active.
+ * - 0b1 - SDHC clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_PEROFF field. */
+#define SDHC_RD_PRSSTAT_PEROFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_PEROFF_MASK) >> SDHC_PRSSTAT_PEROFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_PEROFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_PEROFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
+ *
+ * Indicates that the SD clock is internally gated off, because of buffer
+ * over/under-run or read pause without read wait assertion, or the driver has cleared
+ * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
+ * data transaction on the SD bus.
+ *
+ * Values:
+ * - 0b0 - SD clock is active.
+ * - 0b1 - SD clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_SDOFF field. */
+#define SDHC_RD_PRSSTAT_SDOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_SDOFF_MASK) >> SDHC_PRSSTAT_SDOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_SDOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_SDOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field WTA[8] (RO)
+ *
+ * Indicates that a write transfer is active. If this bit is 0, it means no
+ * valid write data exists in the SDHC. This bit is set in either of the following
+ * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
+ * restart a write transfer. This bit is cleared in either of the following
+ * cases: After getting the CRC status of the last data block as specified by the
+ * transfer count (single and multiple). After getting the CRC status of any block
+ * where data transmission is about to be stopped by a stop at block gap request.
+ * During a write transaction, a block gap event interrupt is generated when this
+ * bit is changed to 0, as result of the stop at block gap request being set.
+ * This status is useful for the host driver in determining when to issue commands
+ * during write busy state.
+ *
+ * Values:
+ * - 0b0 - No valid data.
+ * - 0b1 - Transferring data.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_WTA field. */
+#define SDHC_RD_PRSSTAT_WTA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_WTA_MASK) >> SDHC_PRSSTAT_WTA_SHIFT)
+#define SDHC_BRD_PRSSTAT_WTA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_WTA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field RTA[9] (RO)
+ *
+ * Used for detecting completion of a read transfer. This bit is set for either
+ * of the following conditions: After the end bit of the read command. When
+ * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
+ * interrupt is generated when this bit changes to 0. This bit is cleared for either of
+ * the following conditions: When the last data block as specified by block
+ * length is transferred to the system, that is, all data are read away from SDHC
+ * internal buffer. When all valid data blocks have been transferred from SDHC
+ * internal buffer to the system and no current block transfers are being sent as a
+ * result of the stop at block gap request being set to 1.
+ *
+ * Values:
+ * - 0b0 - No valid data.
+ * - 0b1 - Transferring data.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_RTA field. */
+#define SDHC_RD_PRSSTAT_RTA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_RTA_MASK) >> SDHC_PRSSTAT_RTA_SHIFT)
+#define SDHC_BRD_PRSSTAT_RTA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_RTA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
+ *
+ * Used for non-DMA write transfers. The SDHC can implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates whether space is
+ * available for write data. If this bit is 1, valid data greater than the watermark
+ * level can be written to the buffer. This read-only flag indicates whether
+ * space is available for write data.
+ *
+ * Values:
+ * - 0b0 - Write disable, the buffer can hold valid data less than the write
+ *     watermark level.
+ * - 0b1 - Write enable, the buffer can hold valid data greater than the write
+ *     watermark level.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_BWEN field. */
+#define SDHC_RD_PRSSTAT_BWEN(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_BWEN_MASK) >> SDHC_PRSSTAT_BWEN_SHIFT)
+#define SDHC_BRD_PRSSTAT_BWEN(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_BWEN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BREN[11] (RO)
+ *
+ * Used for non-DMA read transfers. The SDHC may implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates that valid data exists
+ * in the host side buffer. If this bit is high, valid data greater than the
+ * watermark level exist in the buffer. This read-only flag indicates that valid
+ * data exists in the host side buffer.
+ *
+ * Values:
+ * - 0b0 - Read disable, valid data less than the watermark level exist in the
+ *     buffer.
+ * - 0b1 - Read enable, valid data greater than the watermark level exist in the
+ *     buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_BREN field. */
+#define SDHC_RD_PRSSTAT_BREN(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_BREN_MASK) >> SDHC_PRSSTAT_BREN_SHIFT)
+#define SDHC_BRD_PRSSTAT_BREN(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_BREN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CINS[16] (RO)
+ *
+ * Indicates whether a card has been inserted. The SDHC debounces this signal so
+ * that the host driver will not need to wait for it to stabilize. Changing from
+ * a 0 to 1 generates a card insertion interrupt in the Interrupt Status
+ * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
+ * Status register. A write to the force event register does not effect this bit.
+ * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
+ * bit.
+ *
+ * Values:
+ * - 0b0 - Power on reset or no card.
+ * - 0b1 - Card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CINS field. */
+#define SDHC_RD_PRSSTAT_CINS(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CINS_MASK) >> SDHC_PRSSTAT_CINS_SHIFT)
+#define SDHC_BRD_PRSSTAT_CINS(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CINS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
+ *
+ * Used to check the CMD line level to recover from errors, and for debugging.
+ * The reset value is effected by the external pullup/pulldown resistor, by
+ * default, the read value of this bit after reset is 1b, when the command line is
+ * pulled up.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CLSL field. */
+#define SDHC_RD_PRSSTAT_CLSL(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CLSL_MASK) >> SDHC_PRSSTAT_CLSL_SHIFT)
+#define SDHC_BRD_PRSSTAT_CLSL(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CLSL_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
+ *
+ * Used to check the DAT line level to recover from errors, and for debugging.
+ * This is especially useful in detecting the busy signal level from DAT[0]. The
+ * reset value is effected by the external pullup/pulldown resistors. By default,
+ * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
+ * down and the other lines are pulled up.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_DLSL field. */
+#define SDHC_RD_PRSSTAT_DLSL(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_DLSL_MASK) >> SDHC_PRSSTAT_DLSL_SHIFT)
+#define SDHC_BRD_PRSSTAT_DLSL(base) (SDHC_RD_PRSSTAT_DLSL(base))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_PROCTL - Protocol Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_PROCTL - Protocol Control register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * There are three cases to restart the transfer after stop at the block gap.
+ * Which case is appropriate depends on whether the SDHC issues a suspend command
+ * or the SD card accepts the suspend command: If the host driver does not issue a
+ * suspend command, the continue request shall be used to restart the transfer.
+ * If the host driver issues a suspend command and the SD card accepts it, a
+ * resume command shall be used to restart the transfer. If the host driver issues a
+ * suspend command and the SD card does not accept it, the continue request shall
+ * be used to restart the transfer. Any time stop at block gap request stops the
+ * data transfer, the host driver shall wait for a transfer complete (in the
+ * interrupt status register), before attempting to restart the transfer. When
+ * restarting the data transfer by continue request, the host driver shall clear the
+ * stop at block gap request before or simultaneously.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_PROCTL register
+ */
+/*@{*/
+#define SDHC_RD_PROCTL(base)     (SDHC_PROCTL_REG(base))
+#define SDHC_WR_PROCTL(base, value) (SDHC_PROCTL_REG(base) = (value))
+#define SDHC_RMW_PROCTL(base, mask, value) (SDHC_WR_PROCTL(base, (SDHC_RD_PROCTL(base) & ~(mask)) | (value)))
+#define SDHC_SET_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) |  (value)))
+#define SDHC_CLR_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) & ~(value)))
+#define SDHC_TOG_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_PROCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_PROCTL, field LCTL[0] (RW)
+ *
+ * This bit, fully controlled by the host driver, is used to caution the user
+ * not to remove the card while the card is being accessed. If the software is
+ * going to issue multiple SD commands, this bit can be set during all these
+ * transactions. It is not necessary to change for each transaction. When the software
+ * issues multiple SD commands, setting the bit once before the first command is
+ * sufficient: it is not necessary to reset the bit between commands.
+ *
+ * Values:
+ * - 0b0 - LED off.
+ * - 0b1 - LED on.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_LCTL field. */
+#define SDHC_RD_PROCTL_LCTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_LCTL_MASK) >> SDHC_PROCTL_LCTL_SHIFT)
+#define SDHC_BRD_PROCTL_LCTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_LCTL_SHIFT))
+
+/*! @brief Set the LCTL field to a new value. */
+#define SDHC_WR_PROCTL_LCTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_LCTL_MASK, SDHC_PROCTL_LCTL(value)))
+#define SDHC_BWR_PROCTL_LCTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_LCTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field DTW[2:1] (RW)
+ *
+ * Selects the data width of the SD bus for a data transfer. The host driver
+ * shall set it to match the data width of the card. Possible data transfer width is
+ * 1-bit, 4-bits or 8-bits.
+ *
+ * Values:
+ * - 0b00 - 1-bit mode
+ * - 0b01 - 4-bit mode
+ * - 0b10 - 8-bit mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_DTW field. */
+#define SDHC_RD_PROCTL_DTW(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_DTW_MASK) >> SDHC_PROCTL_DTW_SHIFT)
+#define SDHC_BRD_PROCTL_DTW(base) (SDHC_RD_PROCTL_DTW(base))
+
+/*! @brief Set the DTW field to a new value. */
+#define SDHC_WR_PROCTL_DTW(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_DTW_MASK, SDHC_PROCTL_DTW(value)))
+#define SDHC_BWR_PROCTL_DTW(base, value) (SDHC_WR_PROCTL_DTW(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field D3CD[3] (RW)
+ *
+ * If this bit is set, DAT3 should be pulled down to act as a card detection
+ * pin. Be cautious when using this feature, because DAT3 is also a chip-select for
+ * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
+ * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
+ * is used.
+ *
+ * Values:
+ * - 0b0 - DAT3 does not monitor card Insertion.
+ * - 0b1 - DAT3 as card detection pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_D3CD field. */
+#define SDHC_RD_PROCTL_D3CD(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_D3CD_MASK) >> SDHC_PROCTL_D3CD_SHIFT)
+#define SDHC_BRD_PROCTL_D3CD(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_D3CD_SHIFT))
+
+/*! @brief Set the D3CD field to a new value. */
+#define SDHC_WR_PROCTL_D3CD(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_D3CD_MASK, SDHC_PROCTL_D3CD(value)))
+#define SDHC_BWR_PROCTL_D3CD(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_D3CD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
+ *
+ * The SDHC supports all four endian modes in data transfer.
+ *
+ * Values:
+ * - 0b00 - Big endian mode
+ * - 0b01 - Half word big endian mode
+ * - 0b10 - Little endian mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_EMODE field. */
+#define SDHC_RD_PROCTL_EMODE(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_EMODE_MASK) >> SDHC_PROCTL_EMODE_SHIFT)
+#define SDHC_BRD_PROCTL_EMODE(base) (SDHC_RD_PROCTL_EMODE(base))
+
+/*! @brief Set the EMODE field to a new value. */
+#define SDHC_WR_PROCTL_EMODE(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_EMODE_MASK, SDHC_PROCTL_EMODE(value)))
+#define SDHC_BWR_PROCTL_EMODE(base, value) (SDHC_WR_PROCTL_EMODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CDTL[6] (RW)
+ *
+ * Enabled while the CDSS is set to 1 and it indicates card insertion.
+ *
+ * Values:
+ * - 0b0 - Card detect test level is 0, no card inserted.
+ * - 0b1 - Card detect test level is 1, card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CDTL field. */
+#define SDHC_RD_PROCTL_CDTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CDTL_MASK) >> SDHC_PROCTL_CDTL_SHIFT)
+#define SDHC_BRD_PROCTL_CDTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDTL_SHIFT))
+
+/*! @brief Set the CDTL field to a new value. */
+#define SDHC_WR_PROCTL_CDTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CDTL_MASK, SDHC_PROCTL_CDTL(value)))
+#define SDHC_BWR_PROCTL_CDTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CDSS[7] (RW)
+ *
+ * Selects the source for the card detection.
+ *
+ * Values:
+ * - 0b0 - Card detection level is selected for normal purpose.
+ * - 0b1 - Card detection test level is selected for test purpose.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CDSS field. */
+#define SDHC_RD_PROCTL_CDSS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CDSS_MASK) >> SDHC_PROCTL_CDSS_SHIFT)
+#define SDHC_BRD_PROCTL_CDSS(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDSS_SHIFT))
+
+/*! @brief Set the CDSS field to a new value. */
+#define SDHC_WR_PROCTL_CDSS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CDSS_MASK, SDHC_PROCTL_CDSS(value)))
+#define SDHC_BWR_PROCTL_CDSS(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDSS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
+ *
+ * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
+ * operation.
+ *
+ * Values:
+ * - 0b00 - No DMA or simple DMA is selected.
+ * - 0b01 - ADMA1 is selected.
+ * - 0b10 - ADMA2 is selected.
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_DMAS field. */
+#define SDHC_RD_PROCTL_DMAS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT)
+#define SDHC_BRD_PROCTL_DMAS(base) (SDHC_RD_PROCTL_DMAS(base))
+
+/*! @brief Set the DMAS field to a new value. */
+#define SDHC_WR_PROCTL_DMAS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_DMAS_MASK, SDHC_PROCTL_DMAS(value)))
+#define SDHC_BWR_PROCTL_DMAS(base, value) (SDHC_WR_PROCTL_DMAS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
+ *
+ * Used to stop executing a transaction at the next block gap for both DMA and
+ * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
+ * transfer completion, the host driver shall leave this bit set to 1. Clearing both
+ * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
+ * Wait is used to stop the read transaction at the block gap. The SDHC will
+ * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
+ * that SDIO card support read wait. Therefore, the host driver shall not set
+ * this bit during read transfers unless the SDIO card supports read wait and has
+ * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
+ * the read operation during block gap. In the case of write transfers in which
+ * the host driver writes data to the data port register, the host driver shall set
+ * this bit after all block data is written. If this bit is set to 1, the host
+ * driver shall not write data to the Data Port register after a block is sent.
+ * Once this bit is set, the host driver shall not clear this bit before
+ * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
+ * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
+ *
+ * Values:
+ * - 0b0 - Transfer
+ * - 0b1 - Stop
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_SABGREQ field. */
+#define SDHC_RD_PROCTL_SABGREQ(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_SABGREQ_MASK) >> SDHC_PROCTL_SABGREQ_SHIFT)
+#define SDHC_BRD_PROCTL_SABGREQ(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_SABGREQ_SHIFT))
+
+/*! @brief Set the SABGREQ field to a new value. */
+#define SDHC_WR_PROCTL_SABGREQ(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_SABGREQ_MASK, SDHC_PROCTL_SABGREQ(value)))
+#define SDHC_BWR_PROCTL_SABGREQ(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_SABGREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CREQ[17] (RW)
+ *
+ * Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
+ * When a suspend operation is not accepted by the card, it is also by setting this
+ * bit to restart the paused transfer. To cancel stop at the block gap, set
+ * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
+ * automatically clears this bit, therefore it is not necessary for the host driver to
+ * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
+ * request is ignored.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Restart
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CREQ field. */
+#define SDHC_RD_PROCTL_CREQ(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CREQ_MASK) >> SDHC_PROCTL_CREQ_SHIFT)
+#define SDHC_BRD_PROCTL_CREQ(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CREQ_SHIFT))
+
+/*! @brief Set the CREQ field to a new value. */
+#define SDHC_WR_PROCTL_CREQ(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CREQ_MASK, SDHC_PROCTL_CREQ(value)))
+#define SDHC_BWR_PROCTL_CREQ(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field RWCTL[18] (RW)
+ *
+ * The read wait function is optional for SDIO cards. If the card supports read
+ * wait, set this bit to enable use of the read wait protocol to stop read data
+ * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
+ * read data, which restricts commands generation. When the host driver detects an
+ * SDIO card insertion, it shall set this bit according to the CCCR of the card.
+ * If the card does not support read wait, this bit shall never be set to 1,
+ * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
+ * during read operation is also supported, but the SDHC will stop the SD Clock
+ * to pause reading operation.
+ *
+ * Values:
+ * - 0b0 - Disable read wait control, and stop SD clock at block gap when
+ *     SABGREQ is set.
+ * - 0b1 - Enable read wait control, and assert read wait without stopping SD
+ *     clock at block gap when SABGREQ bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_RWCTL field. */
+#define SDHC_RD_PROCTL_RWCTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_RWCTL_MASK) >> SDHC_PROCTL_RWCTL_SHIFT)
+#define SDHC_BRD_PROCTL_RWCTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_RWCTL_SHIFT))
+
+/*! @brief Set the RWCTL field to a new value. */
+#define SDHC_WR_PROCTL_RWCTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_RWCTL_MASK, SDHC_PROCTL_RWCTL(value)))
+#define SDHC_BWR_PROCTL_RWCTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_RWCTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field IABG[19] (RW)
+ *
+ * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
+ * interrupt cycle. Setting to 1 enables interrupt detection at the block gap
+ * for a multiple block transfer. Setting to 0 disables interrupt detection during
+ * a multiple block transfer. If the SDIO card can't signal an interrupt during a
+ * multiple block transfer, this bit must be set to 0 to avoid an inadvertent
+ * interrupt. When the host driver detects an SDIO card insertion, it shall set
+ * this bit according to the CCCR of the card.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_IABG field. */
+#define SDHC_RD_PROCTL_IABG(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_IABG_MASK) >> SDHC_PROCTL_IABG_SHIFT)
+#define SDHC_BRD_PROCTL_IABG(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_IABG_SHIFT))
+
+/*! @brief Set the IABG field to a new value. */
+#define SDHC_WR_PROCTL_IABG(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_IABG_MASK, SDHC_PROCTL_IABG(value)))
+#define SDHC_BWR_PROCTL_IABG(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_IABG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINT[24] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
+ * (Wake Up Support) in CIS is set to 1. When this bit is set, the card
+ * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
+ * the wakeup feature is not enabled, the SD_CLK must be active to assert the
+ * card interrupt status and the SDHC interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECINT field. */
+#define SDHC_RD_PROCTL_WECINT(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECINT_MASK) >> SDHC_PROCTL_WECINT_SHIFT)
+#define SDHC_BRD_PROCTL_WECINT(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINT_SHIFT))
+
+/*! @brief Set the WECINT field to a new value. */
+#define SDHC_WR_PROCTL_WECINT(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECINT_MASK, SDHC_PROCTL_WECINT(value)))
+#define SDHC_BWR_PROCTL_WECINT(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINS[25] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
+ * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
+ * interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECINS field. */
+#define SDHC_RD_PROCTL_WECINS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECINS_MASK) >> SDHC_PROCTL_WECINS_SHIFT)
+#define SDHC_BRD_PROCTL_WECINS(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINS_SHIFT))
+
+/*! @brief Set the WECINS field to a new value. */
+#define SDHC_WR_PROCTL_WECINS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECINS_MASK, SDHC_PROCTL_WECINS(value)))
+#define SDHC_BWR_PROCTL_WECINS(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECRM[26] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
+ * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECRM field. */
+#define SDHC_RD_PROCTL_WECRM(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECRM_MASK) >> SDHC_PROCTL_WECRM_SHIFT)
+#define SDHC_BRD_PROCTL_WECRM(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECRM_SHIFT))
+
+/*! @brief Set the WECRM field to a new value. */
+#define SDHC_WR_PROCTL_WECRM(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECRM_MASK, SDHC_PROCTL_WECRM(value)))
+#define SDHC_BWR_PROCTL_WECRM(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECRM_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_SYSCTL - System Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_SYSCTL - System Control register (RW)
+ *
+ * Reset value: 0x00008008U
+ */
+/*!
+ * @name Constants and macros for entire SDHC_SYSCTL register
+ */
+/*@{*/
+#define SDHC_RD_SYSCTL(base)     (SDHC_SYSCTL_REG(base))
+#define SDHC_WR_SYSCTL(base, value) (SDHC_SYSCTL_REG(base) = (value))
+#define SDHC_RMW_SYSCTL(base, mask, value) (SDHC_WR_SYSCTL(base, (SDHC_RD_SYSCTL(base) & ~(mask)) | (value)))
+#define SDHC_SET_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) |  (value)))
+#define SDHC_CLR_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) & ~(value)))
+#define SDHC_TOG_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_SYSCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
+ *
+ * If this bit is set, bus clock will always be active and no automatic gating
+ * is applied. The bus clock will be internally gated off, if none of the
+ * following factors are met: The cmd part is reset, or Data part is reset, or Soft
+ * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
+ * request is just set, or This bit is set, or Card insertion is detected, or Card
+ * removal is detected, or Card external interrupt is detected, or The SDHC
+ * clock is not gated off The bus clock will not be auto gated off if the SDHC clock
+ * is not gated off. So clearing only this bit has no effect unless the PEREN bit
+ * is also cleared.
+ *
+ * Values:
+ * - 0b0 - Bus clock will be internally gated off.
+ * - 0b1 - Bus clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_IPGEN field. */
+#define SDHC_RD_SYSCTL_IPGEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_IPGEN_MASK) >> SDHC_SYSCTL_IPGEN_SHIFT)
+#define SDHC_BRD_SYSCTL_IPGEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_IPGEN_SHIFT))
+
+/*! @brief Set the IPGEN field to a new value. */
+#define SDHC_WR_SYSCTL_IPGEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_IPGEN_MASK, SDHC_SYSCTL_IPGEN(value)))
+#define SDHC_BWR_SYSCTL_IPGEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_IPGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
+ *
+ * If this bit is set, system clock will always be active and no automatic
+ * gating is applied. When this bit is cleared, system clock will be automatically off
+ * when no data transfer is on the SD bus.
+ *
+ * Values:
+ * - 0b0 - System clock will be internally gated off.
+ * - 0b1 - System clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_HCKEN field. */
+#define SDHC_RD_SYSCTL_HCKEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_HCKEN_MASK) >> SDHC_SYSCTL_HCKEN_SHIFT)
+#define SDHC_BRD_SYSCTL_HCKEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_HCKEN_SHIFT))
+
+/*! @brief Set the HCKEN field to a new value. */
+#define SDHC_WR_SYSCTL_HCKEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_HCKEN_MASK, SDHC_SYSCTL_HCKEN(value)))
+#define SDHC_BWR_SYSCTL_HCKEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_HCKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field PEREN[2] (RW)
+ *
+ * If this bit is set, SDHC clock will always be active and no automatic gating
+ * is applied. Thus the SDCLK is active except for when auto gating-off during
+ * buffer danger (buffer about to over-run or under-run). When this bit is cleared,
+ * the SDHC clock will be automatically off whenever there is no transaction on
+ * the SD bus. Because this bit is only a feature enabling bit, clearing this bit
+ * does not stop SDCLK immediately. The SDHC clock will be internally gated off,
+ * if none of the following factors are met: The cmd part is reset, or Data part
+ * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
+ * just updated, or Continue request is just set, or This bit is set, or Card
+ * insertion is detected, or Card removal is detected, or Card external interrupt is
+ * detected, or 80 clocks for initialization phase is ongoing
+ *
+ * Values:
+ * - 0b0 - SDHC clock will be internally gated off.
+ * - 0b1 - SDHC clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_PEREN field. */
+#define SDHC_RD_SYSCTL_PEREN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_PEREN_MASK) >> SDHC_SYSCTL_PEREN_SHIFT)
+#define SDHC_BRD_SYSCTL_PEREN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_PEREN_SHIFT))
+
+/*! @brief Set the PEREN field to a new value. */
+#define SDHC_WR_SYSCTL_PEREN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_PEREN_MASK, SDHC_SYSCTL_PEREN(value)))
+#define SDHC_BWR_SYSCTL_PEREN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_PEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
+ *
+ * The host controller shall stop SDCLK when writing this bit to 0. SDCLK
+ * frequency can be changed when this bit is 0. Then, the host controller shall
+ * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
+ * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
+ * power.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field. */
+#define SDHC_RD_SYSCTL_SDCLKEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_SDCLKEN_MASK) >> SDHC_SYSCTL_SDCLKEN_SHIFT)
+#define SDHC_BRD_SYSCTL_SDCLKEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_SDCLKEN_SHIFT))
+
+/*! @brief Set the SDCLKEN field to a new value. */
+#define SDHC_WR_SYSCTL_SDCLKEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_SDCLKEN_MASK, SDHC_SYSCTL_SDCLKEN(value)))
+#define SDHC_BWR_SYSCTL_SDCLKEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_SDCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
+ *
+ * Used to provide a more exact divisor to generate the desired SD clock
+ * frequency. Note the divider can even support odd divisor without deterioration of
+ * duty cycle. The setting are as following:
+ *
+ * Values:
+ * - 0b0000 - Divisor by 1.
+ * - 0b0001 - Divisor by 2.
+ * - 0b1110 - Divisor by 15.
+ * - 0b1111 - Divisor by 16.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_DVS field. */
+#define SDHC_RD_SYSCTL_DVS(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_DVS_MASK) >> SDHC_SYSCTL_DVS_SHIFT)
+#define SDHC_BRD_SYSCTL_DVS(base) (SDHC_RD_SYSCTL_DVS(base))
+
+/*! @brief Set the DVS field to a new value. */
+#define SDHC_WR_SYSCTL_DVS(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_DVS_MASK, SDHC_SYSCTL_DVS(value)))
+#define SDHC_BWR_SYSCTL_DVS(base, value) (SDHC_WR_SYSCTL_DVS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
+ *
+ * Used to select the frequency of the SDCLK pin. The frequency is not
+ * programmed directly. Rather this register holds the prescaler (this register) and
+ * divisor (next register) of the base clock frequency register. Setting 00h bypasses
+ * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
+ * behavior of this prescaler is undefined. The two default divider values can
+ * be calculated by the frequency of SDHC clock and the following divisor bits.
+ * The frequency of SDCLK is set by the following formula: Clock frequency = (Base
+ * clock) / (prescaler x divisor) For example, if the base clock frequency is 96
+ * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
+ * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
+ * less than or equal to the target. Similarly, to approach a clock value of 400
+ * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
+ * value of 400 kHz. The reset value of this field is 80h, so if the input base
+ * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
+ * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
+ * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
+ * never exceed this limit. Only the following settings are allowed:
+ *
+ * Values:
+ * - 0b00000001 - Base clock divided by 2.
+ * - 0b00000010 - Base clock divided by 4.
+ * - 0b00000100 - Base clock divided by 8.
+ * - 0b00001000 - Base clock divided by 16.
+ * - 0b00010000 - Base clock divided by 32.
+ * - 0b00100000 - Base clock divided by 64.
+ * - 0b01000000 - Base clock divided by 128.
+ * - 0b10000000 - Base clock divided by 256.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field. */
+#define SDHC_RD_SYSCTL_SDCLKFS(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_SDCLKFS_MASK) >> SDHC_SYSCTL_SDCLKFS_SHIFT)
+#define SDHC_BRD_SYSCTL_SDCLKFS(base) (SDHC_RD_SYSCTL_SDCLKFS(base))
+
+/*! @brief Set the SDCLKFS field to a new value. */
+#define SDHC_WR_SYSCTL_SDCLKFS(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_SDCLKFS_MASK, SDHC_SYSCTL_SDCLKFS(value)))
+#define SDHC_BWR_SYSCTL_SDCLKFS(base, value) (SDHC_WR_SYSCTL_SDCLKFS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
+ *
+ * Determines the interval by which DAT line timeouts are detected. See
+ * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
+ * clock frequency will be generated by dividing the base clock SDCLK value by this
+ * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
+ * time-out events.
+ *
+ * Values:
+ * - 0b0000 - SDCLK x 2 13
+ * - 0b0001 - SDCLK x 2 14
+ * - 0b1110 - SDCLK x 2 27
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_DTOCV field. */
+#define SDHC_RD_SYSCTL_DTOCV(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_DTOCV_MASK) >> SDHC_SYSCTL_DTOCV_SHIFT)
+#define SDHC_BRD_SYSCTL_DTOCV(base) (SDHC_RD_SYSCTL_DTOCV(base))
+
+/*! @brief Set the DTOCV field to a new value. */
+#define SDHC_WR_SYSCTL_DTOCV(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_DTOCV_MASK, SDHC_SYSCTL_DTOCV(value)))
+#define SDHC_BWR_SYSCTL_DTOCV(base, value) (SDHC_WR_SYSCTL_DTOCV(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
+ *
+ * Effects the entire host controller except for the card detection circuit.
+ * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
+ * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
+ * reset this bit to 0 when the capabilities registers are valid and the host driver
+ * can read them. Additional use of software reset for all does not affect the
+ * value of the capabilities registers. After this bit is set, it is recommended
+ * that the host driver reset the external card and reinitialize it.
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define SDHC_WR_SYSCTL_RSTA(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTA_MASK, SDHC_SYSCTL_RSTA(value)))
+#define SDHC_BWR_SYSCTL_RSTA(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
+ *
+ * Only part of the command circuit is reset. The following registers and bits
+ * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTC field to a new value. */
+#define SDHC_WR_SYSCTL_RSTC(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTC_MASK, SDHC_SYSCTL_RSTC(value)))
+#define SDHC_BWR_SYSCTL_RSTC(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
+ *
+ * Only part of the data circuit is reset. DMA circuit is also reset. The
+ * following registers and bits are cleared by this bit: Data Port register Buffer Is
+ * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
+ * Enable Read Transfer Active Write Transfer Active DAT Line Active Command
+ * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
+ * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
+ * Block Gap Event Transfer Complete
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTD field to a new value. */
+#define SDHC_WR_SYSCTL_RSTD(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTD_MASK, SDHC_SYSCTL_RSTD(value)))
+#define SDHC_BWR_SYSCTL_RSTD(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field INITA[27] (RW)
+ *
+ * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
+ * are sent, this bit is self-cleared. This bit is very useful during the card
+ * power-up period when 74 SD-clocks are needed and the clock auto gating feature
+ * is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
+ * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
+ * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
+ * when command line or data lines are active, write to this bit is not allowed.
+ * On the otherhand, when this bit is set, that is, during intialization active
+ * period, it is allowed to issue command, and the command bit stream will appear
+ * on the CMD pad after all 80 clock cycles are done. So when this command ends,
+ * the driver can make sure the 80 clock cycles are sent out. This is very useful
+ * when the driver needs send 80 cycles to the card and does not want to wait
+ * till this bit is self-cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_INITA field. */
+#define SDHC_RD_SYSCTL_INITA(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_INITA_MASK) >> SDHC_SYSCTL_INITA_SHIFT)
+#define SDHC_BRD_SYSCTL_INITA(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_INITA_SHIFT))
+
+/*! @brief Set the INITA field to a new value. */
+#define SDHC_WR_SYSCTL_INITA(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_INITA_MASK, SDHC_SYSCTL_INITA(value)))
+#define SDHC_BWR_SYSCTL_INITA(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_INITA_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSTAT - Interrupt Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * An interrupt is generated when the Normal Interrupt Signal Enable is enabled
+ * and at least one of the status bits is set to 1. For all bits, writing 1 to a
+ * bit clears it; writing to 0 keeps the bit unchanged. More than one status can
+ * be cleared with a single register write. For Card Interrupt, before writing 1
+ * to clear, it is required that the card stops asserting the interrupt, meaning
+ * that when the Card Driver services the interrupt condition, otherwise the CINT
+ * bit will be asserted again. The table below shows the relationship between
+ * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
+ * complete Command timeout error Meaning of the status 0 0 X X 1 Response not
+ * received within 64 SDCLK cycles 1 0 Response received The table below shows the
+ * relationship between the Transfer Complete and the Data Timeout Error. SDHC status
+ * for data timeout error/transfer complete bit combinations Transfer complete
+ * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
+ * transfer 1 X Data transfer complete The table below shows the relationship between
+ * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
+ * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
+ * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
+ * CMD line conflict
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTAT register
+ */
+/*@{*/
+#define SDHC_RD_IRQSTAT(base)    (SDHC_IRQSTAT_REG(base))
+#define SDHC_WR_IRQSTAT(base, value) (SDHC_IRQSTAT_REG(base) = (value))
+#define SDHC_RMW_IRQSTAT(base, mask, value) (SDHC_WR_IRQSTAT(base, (SDHC_RD_IRQSTAT(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) |  (value)))
+#define SDHC_CLR_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) & ~(value)))
+#define SDHC_TOG_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CC[0] (W1C)
+ *
+ * This bit is set when you receive the end bit of the command response, except
+ * Auto CMD12. See PRSSTAT[CIHB].
+ *
+ * Values:
+ * - 0b0 - Command not complete.
+ * - 0b1 - Command complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CC field. */
+#define SDHC_RD_IRQSTAT_CC(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CC_MASK) >> SDHC_IRQSTAT_CC_SHIFT)
+#define SDHC_BRD_IRQSTAT_CC(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CC_SHIFT))
+
+/*! @brief Set the CC field to a new value. */
+#define SDHC_WR_IRQSTAT_CC(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CC(value)))
+#define SDHC_BWR_IRQSTAT_CC(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field TC[1] (W1C)
+ *
+ * This bit is set when a read or write transfer is completed. In the case of a
+ * read transaction: This bit is set at the falling edge of the read transfer
+ * active status. There are two cases in which this interrupt is generated. The
+ * first is when a data transfer is completed as specified by the data length, after
+ * the last data has been read to the host system. The second is when data has
+ * stopped at the block gap and completed the data transfer by setting
+ * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
+ * transaction: This bit is set at the falling edge of the DAT line active
+ * status. There are two cases in which this interrupt is generated. The first is when
+ * the last data is written to the SD card as specified by the data length and
+ * the busy signal is released. The second is when data transfers are stopped at
+ * the block gap, by setting PROCTL[SABGREQ], and the data transfers are
+ * completed,after valid data is written to the SD card and the busy signal released.
+ *
+ * Values:
+ * - 0b0 - Transfer not complete.
+ * - 0b1 - Transfer complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_TC field. */
+#define SDHC_RD_IRQSTAT_TC(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_TC_MASK) >> SDHC_IRQSTAT_TC_SHIFT)
+#define SDHC_BRD_IRQSTAT_TC(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_TC_SHIFT))
+
+/*! @brief Set the TC field to a new value. */
+#define SDHC_WR_IRQSTAT_TC(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_TC(value)))
+#define SDHC_BWR_IRQSTAT_TC(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_TC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
+ *
+ * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
+ * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
+ * set to 1. In the case of a read transaction: This bit is set at the falling
+ * edge of the DAT line active status, when the transaction is stopped at SD Bus
+ * timing. The read wait must be supported in order to use this function. In the
+ * case of write transaction: This bit is set at the falling edge of write transfer
+ * active status, after getting CRC status at SD bus timing.
+ *
+ * Values:
+ * - 0b0 - No block gap event.
+ * - 0b1 - Transaction stopped at block gap.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BGE field. */
+#define SDHC_RD_IRQSTAT_BGE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BGE_MASK) >> SDHC_IRQSTAT_BGE_SHIFT)
+#define SDHC_BRD_IRQSTAT_BGE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BGE_SHIFT))
+
+/*! @brief Set the BGE field to a new value. */
+#define SDHC_WR_IRQSTAT_BGE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BGE(value)))
+#define SDHC_BWR_IRQSTAT_BGE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
+ *
+ * Occurs only when the internal DMA finishes the data transfer successfully.
+ * Whenever errors occur during data transfer, this bit will not be set. Instead,
+ * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
+ * this bit will be set.
+ *
+ * Values:
+ * - 0b0 - No DMA Interrupt.
+ * - 0b1 - DMA Interrupt is generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DINT field. */
+#define SDHC_RD_IRQSTAT_DINT(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DINT_MASK) >> SDHC_IRQSTAT_DINT_SHIFT)
+#define SDHC_BRD_IRQSTAT_DINT(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DINT_SHIFT))
+
+/*! @brief Set the DINT field to a new value. */
+#define SDHC_WR_IRQSTAT_DINT(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DINT(value)))
+#define SDHC_BWR_IRQSTAT_DINT(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
+ *
+ * This status bit is set if the Buffer Write Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0b0 - Not ready to write buffer.
+ * - 0b1 - Ready to write buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BWR field. */
+#define SDHC_RD_IRQSTAT_BWR(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BWR_MASK) >> SDHC_IRQSTAT_BWR_SHIFT)
+#define SDHC_BRD_IRQSTAT_BWR(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BWR_SHIFT))
+
+/*! @brief Set the BWR field to a new value. */
+#define SDHC_WR_IRQSTAT_BWR(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BWR(value)))
+#define SDHC_BWR_IRQSTAT_BWR(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BWR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
+ *
+ * This status bit is set if the Buffer Read Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0b0 - Not ready to read buffer.
+ * - 0b1 - Ready to read buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BRR field. */
+#define SDHC_RD_IRQSTAT_BRR(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BRR_MASK) >> SDHC_IRQSTAT_BRR_SHIFT)
+#define SDHC_BRD_IRQSTAT_BRR(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BRR_SHIFT))
+
+/*! @brief Set the BRR field to a new value. */
+#define SDHC_WR_IRQSTAT_BRR(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BRR(value)))
+#define SDHC_BWR_IRQSTAT_BRR(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 0 to 1. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if a card is inserted. To leave it cleared,
+ * clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0b0 - Card state unstable or removed.
+ * - 0b1 - Card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CINS field. */
+#define SDHC_RD_IRQSTAT_CINS(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CINS_MASK) >> SDHC_IRQSTAT_CINS_SHIFT)
+#define SDHC_BRD_IRQSTAT_CINS(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINS_SHIFT))
+
+/*! @brief Set the CINS field to a new value. */
+#define SDHC_WR_IRQSTAT_CINS(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CINS(value)))
+#define SDHC_BWR_IRQSTAT_CINS(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 1 to 0. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if no card is inserted. To leave it cleared,
+ * clear the Card Removal Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0b0 - Card state unstable or inserted.
+ * - 0b1 - Card removed.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CRM field. */
+#define SDHC_RD_IRQSTAT_CRM(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CRM_MASK) >> SDHC_IRQSTAT_CRM_SHIFT)
+#define SDHC_BRD_IRQSTAT_CRM(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CRM_SHIFT))
+
+/*! @brief Set the CRM field to a new value. */
+#define SDHC_WR_IRQSTAT_CRM(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CRM(value)))
+#define SDHC_BWR_IRQSTAT_CRM(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CRM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
+ *
+ * This status bit is set when an interrupt signal is detected from the external
+ * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
+ * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
+ * during the interrupt cycle, so the interrupt from card can only be sampled
+ * during interrupt cycle, introducing some delay between the interrupt signal from
+ * the SDIO card and the interrupt to the host system. Writing this bit to 1 can
+ * clear this bit, but as the interrupt factor from the SDIO card does not clear,
+ * this bit is set again. To clear this bit, it is required to reset the interrupt
+ * factor from the external card followed by a writing 1 to this bit. When this
+ * status has been set, and the host driver needs to service this interrupt, the
+ * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
+ * 0 to stop driving the interrupt signal to the host system. After completion
+ * of the card interrupt service (it must reset the interrupt factors in the SDIO
+ * card and the interrupt signal may not be asserted), write 1 to clear this bit,
+ * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
+ * signal again.
+ *
+ * Values:
+ * - 0b0 - No Card Interrupt.
+ * - 0b1 - Generate Card Interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CINT field. */
+#define SDHC_RD_IRQSTAT_CINT(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CINT_MASK) >> SDHC_IRQSTAT_CINT_SHIFT)
+#define SDHC_BRD_IRQSTAT_CINT(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINT_SHIFT))
+
+/*! @brief Set the CINT field to a new value. */
+#define SDHC_WR_IRQSTAT_CINT(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CINT(value)))
+#define SDHC_BWR_IRQSTAT_CINT(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
+ *
+ * Occurs only if no response is returned within 64 SDCLK cycles from the end
+ * bit of the command. If the SDHC detects a CMD line conflict, in which case a
+ * Command CRC Error shall also be set, this bit shall be set without waiting for 64
+ * SDCLK cycles. This is because the command will be aborted by the SDHC.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CTOE field. */
+#define SDHC_RD_IRQSTAT_CTOE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CTOE_MASK) >> SDHC_IRQSTAT_CTOE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CTOE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CTOE_SHIFT))
+
+/*! @brief Set the CTOE field to a new value. */
+#define SDHC_WR_IRQSTAT_CTOE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CTOE(value)))
+#define SDHC_BWR_IRQSTAT_CTOE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
+ *
+ * Command CRC Error is generated in two cases. If a response is returned and
+ * the Command Timeout Error is set to 0, indicating no time-out, this bit is set
+ * when detecting a CRC error in the command response. The SDHC detects a CMD line
+ * conflict by monitoring the CMD line when a command is issued. If the SDHC
+ * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
+ * then the SDHC shall abort the command (Stop driving CMD line) and set this bit
+ * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
+ * conflict.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - CRC Error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CCE field. */
+#define SDHC_RD_IRQSTAT_CCE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CCE_MASK) >> SDHC_IRQSTAT_CCE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CCE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CCE_SHIFT))
+
+/*! @brief Set the CCE field to a new value. */
+#define SDHC_WR_IRQSTAT_CCE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CCE(value)))
+#define SDHC_BWR_IRQSTAT_CCE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
+ *
+ * Occurs when detecting that the end bit of a command response is 0.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - End Bit Error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CEBE field. */
+#define SDHC_RD_IRQSTAT_CEBE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CEBE_MASK) >> SDHC_IRQSTAT_CEBE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CEBE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CEBE_SHIFT))
+
+/*! @brief Set the CEBE field to a new value. */
+#define SDHC_WR_IRQSTAT_CEBE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CEBE(value)))
+#define SDHC_BWR_IRQSTAT_CEBE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
+ *
+ * Occurs if a Command Index error occurs in the command response.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CIE field. */
+#define SDHC_RD_IRQSTAT_CIE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CIE_MASK) >> SDHC_IRQSTAT_CIE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CIE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CIE_SHIFT))
+
+/*! @brief Set the CIE field to a new value. */
+#define SDHC_WR_IRQSTAT_CIE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CIE(value)))
+#define SDHC_BWR_IRQSTAT_CIE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
+ *
+ * Occurs when detecting one of following time-out conditions. Busy time-out for
+ * R1b,R5b type Busy time-out after Write CRC status Read Data time-out
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DTOE field. */
+#define SDHC_RD_IRQSTAT_DTOE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DTOE_MASK) >> SDHC_IRQSTAT_DTOE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DTOE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DTOE_SHIFT))
+
+/*! @brief Set the DTOE field to a new value. */
+#define SDHC_WR_IRQSTAT_DTOE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DTOE(value)))
+#define SDHC_BWR_IRQSTAT_DTOE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
+ *
+ * Occurs when detecting a CRC error when transferring read data, which uses the
+ * DAT line, or when detecting the Write CRC status having a value other than
+ * 010.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DCE field. */
+#define SDHC_RD_IRQSTAT_DCE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DCE_MASK) >> SDHC_IRQSTAT_DCE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DCE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DCE_SHIFT))
+
+/*! @brief Set the DCE field to a new value. */
+#define SDHC_WR_IRQSTAT_DCE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DCE(value)))
+#define SDHC_BWR_IRQSTAT_DCE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
+ *
+ * Occurs either when detecting 0 at the end bit position of read data, which
+ * uses the DAT line, or at the end bit position of the CRC.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DEBE field. */
+#define SDHC_RD_IRQSTAT_DEBE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DEBE_MASK) >> SDHC_IRQSTAT_DEBE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DEBE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DEBE_SHIFT))
+
+/*! @brief Set the DEBE field to a new value. */
+#define SDHC_WR_IRQSTAT_DEBE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DEBE(value)))
+#define SDHC_BWR_IRQSTAT_DEBE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
+ *
+ * Occurs when detecting that one of the bits in the Auto CMD12 Error Status
+ * register has changed from 0 to 1. This bit is set to 1, not only when the errors
+ * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
+ * previous command error.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_AC12E field. */
+#define SDHC_RD_IRQSTAT_AC12E(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_AC12E_MASK) >> SDHC_IRQSTAT_AC12E_SHIFT)
+#define SDHC_BRD_IRQSTAT_AC12E(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_AC12E_SHIFT))
+
+/*! @brief Set the AC12E field to a new value. */
+#define SDHC_WR_IRQSTAT_AC12E(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_AC12E(value)))
+#define SDHC_BWR_IRQSTAT_AC12E(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_AC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
+ *
+ * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
+ * some error occurs in the data transfer. This error can be caused by either
+ * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
+ * Address register is the next fetch address where the error occurs. Because any
+ * error corrupts the whole data block, the host driver shall restart the transfer
+ * from the corrupted block boundary. The address of the block boundary can be
+ * calculated either from the current DSADDR value or from the remaining number of
+ * blocks and the block size.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DMAE field. */
+#define SDHC_RD_IRQSTAT_DMAE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DMAE_MASK) >> SDHC_IRQSTAT_DMAE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DMAE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DMAE_SHIFT))
+
+/*! @brief Set the DMAE field to a new value. */
+#define SDHC_WR_IRQSTAT_DMAE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DMAE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK), SDHC_IRQSTAT_DMAE(value)))
+#define SDHC_BWR_IRQSTAT_DMAE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DMAE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSTATEN - Interrupt Status Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
+ *
+ * Reset value: 0x117F013FU
+ *
+ * Setting the bits in this register to 1 enables the corresponding interrupt
+ * status to be set by the specified event. If any bit is cleared, the
+ * corresponding interrupt status bit is also cleared, that is, when the bit in this register
+ * is cleared, the corresponding bit in interrupt status register is always 0.
+ * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
+ * card interrupt signal during the interrupt period and hold its value in the
+ * flip-flop. There will be some delays on the card interrupt, asserted from the card,
+ * to the time the host system is informed. To detect a CMD line conflict, the
+ * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTATEN register
+ */
+/*@{*/
+#define SDHC_RD_IRQSTATEN(base)  (SDHC_IRQSTATEN_REG(base))
+#define SDHC_WR_IRQSTATEN(base, value) (SDHC_IRQSTATEN_REG(base) = (value))
+#define SDHC_RMW_IRQSTATEN(base, mask, value) (SDHC_WR_IRQSTATEN(base, (SDHC_RD_IRQSTATEN(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) |  (value)))
+#define SDHC_CLR_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) & ~(value)))
+#define SDHC_TOG_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSTATEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field. */
+#define SDHC_RD_IRQSTATEN_CCSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CCSEN_MASK) >> SDHC_IRQSTATEN_CCSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CCSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCSEN_SHIFT))
+
+/*! @brief Set the CCSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CCSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CCSEN_MASK, SDHC_IRQSTATEN_CCSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CCSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field. */
+#define SDHC_RD_IRQSTATEN_TCSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_TCSEN_MASK) >> SDHC_IRQSTATEN_TCSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_TCSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_TCSEN_SHIFT))
+
+/*! @brief Set the TCSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_TCSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_TCSEN_MASK, SDHC_IRQSTATEN_TCSEN(value)))
+#define SDHC_BWR_IRQSTATEN_TCSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_TCSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field. */
+#define SDHC_RD_IRQSTATEN_BGESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BGESEN_MASK) >> SDHC_IRQSTATEN_BGESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BGESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BGESEN_SHIFT))
+
+/*! @brief Set the BGESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BGESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BGESEN_MASK, SDHC_IRQSTATEN_BGESEN(value)))
+#define SDHC_BWR_IRQSTATEN_BGESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BGESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field. */
+#define SDHC_RD_IRQSTATEN_DINTSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DINTSEN_MASK) >> SDHC_IRQSTATEN_DINTSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DINTSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DINTSEN_SHIFT))
+
+/*! @brief Set the DINTSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DINTSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DINTSEN_MASK, SDHC_IRQSTATEN_DINTSEN(value)))
+#define SDHC_BWR_IRQSTATEN_DINTSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DINTSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field. */
+#define SDHC_RD_IRQSTATEN_BWRSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BWRSEN_MASK) >> SDHC_IRQSTATEN_BWRSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BWRSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BWRSEN_SHIFT))
+
+/*! @brief Set the BWRSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BWRSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BWRSEN_MASK, SDHC_IRQSTATEN_BWRSEN(value)))
+#define SDHC_BWR_IRQSTATEN_BWRSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BWRSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field. */
+#define SDHC_RD_IRQSTATEN_BRRSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BRRSEN_MASK) >> SDHC_IRQSTATEN_BRRSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BRRSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BRRSEN_SHIFT))
+
+/*! @brief Set the BRRSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BRRSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BRRSEN_MASK, SDHC_IRQSTATEN_BRRSEN(value)))
+#define SDHC_BWR_IRQSTATEN_BRRSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BRRSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field. */
+#define SDHC_RD_IRQSTATEN_CINSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CINSEN_MASK) >> SDHC_IRQSTATEN_CINSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CINSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINSEN_SHIFT))
+
+/*! @brief Set the CINSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CINSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CINSEN_MASK, SDHC_IRQSTATEN_CINSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CINSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field. */
+#define SDHC_RD_IRQSTATEN_CRMSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CRMSEN_MASK) >> SDHC_IRQSTATEN_CRMSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CRMSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CRMSEN_SHIFT))
+
+/*! @brief Set the CRMSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CRMSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CRMSEN_MASK, SDHC_IRQSTATEN_CRMSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CRMSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CRMSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
+ *
+ * If this bit is set to 0, the SDHC will clear the interrupt request to the
+ * system. The card interrupt detection is stopped when this bit is cleared and
+ * restarted when this bit is set to 1. The host driver must clear the this bit
+ * before servicing the card interrupt and must set this bit again after all interrupt
+ * requests from the card are cleared to prevent inadvertent interrupts.
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field. */
+#define SDHC_RD_IRQSTATEN_CINTSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CINTSEN_MASK) >> SDHC_IRQSTATEN_CINTSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CINTSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINTSEN_SHIFT))
+
+/*! @brief Set the CINTSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CINTSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CINTSEN_MASK, SDHC_IRQSTATEN_CINTSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CINTSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINTSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field. */
+#define SDHC_RD_IRQSTATEN_CTOESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CTOESEN_MASK) >> SDHC_IRQSTATEN_CTOESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CTOESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CTOESEN_SHIFT))
+
+/*! @brief Set the CTOESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CTOESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CTOESEN_MASK, SDHC_IRQSTATEN_CTOESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CTOESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CTOESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field. */
+#define SDHC_RD_IRQSTATEN_CCESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CCESEN_MASK) >> SDHC_IRQSTATEN_CCESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CCESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCESEN_SHIFT))
+
+/*! @brief Set the CCESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CCESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CCESEN_MASK, SDHC_IRQSTATEN_CCESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CCESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field. */
+#define SDHC_RD_IRQSTATEN_CEBESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CEBESEN_MASK) >> SDHC_IRQSTATEN_CEBESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CEBESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CEBESEN_SHIFT))
+
+/*! @brief Set the CEBESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CEBESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CEBESEN_MASK, SDHC_IRQSTATEN_CEBESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CEBESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CEBESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field. */
+#define SDHC_RD_IRQSTATEN_CIESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CIESEN_MASK) >> SDHC_IRQSTATEN_CIESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CIESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CIESEN_SHIFT))
+
+/*! @brief Set the CIESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CIESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CIESEN_MASK, SDHC_IRQSTATEN_CIESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CIESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CIESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field. */
+#define SDHC_RD_IRQSTATEN_DTOESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DTOESEN_MASK) >> SDHC_IRQSTATEN_DTOESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DTOESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DTOESEN_SHIFT))
+
+/*! @brief Set the DTOESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DTOESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DTOESEN_MASK, SDHC_IRQSTATEN_DTOESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DTOESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DTOESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field. */
+#define SDHC_RD_IRQSTATEN_DCESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DCESEN_MASK) >> SDHC_IRQSTATEN_DCESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DCESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DCESEN_SHIFT))
+
+/*! @brief Set the DCESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DCESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DCESEN_MASK, SDHC_IRQSTATEN_DCESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DCESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DCESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field. */
+#define SDHC_RD_IRQSTATEN_DEBESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DEBESEN_MASK) >> SDHC_IRQSTATEN_DEBESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DEBESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DEBESEN_SHIFT))
+
+/*! @brief Set the DEBESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DEBESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DEBESEN_MASK, SDHC_IRQSTATEN_DEBESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DEBESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DEBESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field. */
+#define SDHC_RD_IRQSTATEN_AC12ESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_AC12ESEN_MASK) >> SDHC_IRQSTATEN_AC12ESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_AC12ESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_AC12ESEN_SHIFT))
+
+/*! @brief Set the AC12ESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_AC12ESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_AC12ESEN_MASK, SDHC_IRQSTATEN_AC12ESEN(value)))
+#define SDHC_BWR_IRQSTATEN_AC12ESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_AC12ESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field. */
+#define SDHC_RD_IRQSTATEN_DMAESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DMAESEN_MASK) >> SDHC_IRQSTATEN_DMAESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DMAESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DMAESEN_SHIFT))
+
+/*! @brief Set the DMAESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DMAESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DMAESEN_MASK, SDHC_IRQSTATEN_DMAESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DMAESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DMAESEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSIGEN - Interrupt Signal Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to select which interrupt status is indicated to the
+ * host system as the interrupt. All of these status bits share the same interrupt
+ * line. Setting any of these bits to 1 enables interrupt generation. The
+ * corresponding status register bit will generate an interrupt when the corresponding
+ * interrupt signal enable bit is set.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSIGEN register
+ */
+/*@{*/
+#define SDHC_RD_IRQSIGEN(base)   (SDHC_IRQSIGEN_REG(base))
+#define SDHC_WR_IRQSIGEN(base, value) (SDHC_IRQSIGEN_REG(base) = (value))
+#define SDHC_RMW_IRQSIGEN(base, mask, value) (SDHC_WR_IRQSIGEN(base, (SDHC_RD_IRQSIGEN(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) |  (value)))
+#define SDHC_CLR_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) & ~(value)))
+#define SDHC_TOG_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSIGEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field. */
+#define SDHC_RD_IRQSIGEN_CCIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CCIEN_MASK) >> SDHC_IRQSIGEN_CCIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CCIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCIEN_SHIFT))
+
+/*! @brief Set the CCIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CCIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CCIEN_MASK, SDHC_IRQSIGEN_CCIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CCIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field. */
+#define SDHC_RD_IRQSIGEN_TCIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_TCIEN_MASK) >> SDHC_IRQSIGEN_TCIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_TCIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_TCIEN_SHIFT))
+
+/*! @brief Set the TCIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_TCIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_TCIEN_MASK, SDHC_IRQSIGEN_TCIEN(value)))
+#define SDHC_BWR_IRQSIGEN_TCIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_TCIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field. */
+#define SDHC_RD_IRQSIGEN_BGEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BGEIEN_MASK) >> SDHC_IRQSIGEN_BGEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BGEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BGEIEN_SHIFT))
+
+/*! @brief Set the BGEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BGEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BGEIEN_MASK, SDHC_IRQSIGEN_BGEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BGEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BGEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field. */
+#define SDHC_RD_IRQSIGEN_DINTIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DINTIEN_MASK) >> SDHC_IRQSIGEN_DINTIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DINTIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DINTIEN_SHIFT))
+
+/*! @brief Set the DINTIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DINTIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DINTIEN_MASK, SDHC_IRQSIGEN_DINTIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DINTIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DINTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field. */
+#define SDHC_RD_IRQSIGEN_BWRIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BWRIEN_MASK) >> SDHC_IRQSIGEN_BWRIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BWRIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BWRIEN_SHIFT))
+
+/*! @brief Set the BWRIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BWRIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BWRIEN_MASK, SDHC_IRQSIGEN_BWRIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BWRIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BWRIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field. */
+#define SDHC_RD_IRQSIGEN_BRRIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BRRIEN_MASK) >> SDHC_IRQSIGEN_BRRIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BRRIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BRRIEN_SHIFT))
+
+/*! @brief Set the BRRIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BRRIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BRRIEN_MASK, SDHC_IRQSIGEN_BRRIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BRRIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BRRIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field. */
+#define SDHC_RD_IRQSIGEN_CINSIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CINSIEN_MASK) >> SDHC_IRQSIGEN_CINSIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CINSIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINSIEN_SHIFT))
+
+/*! @brief Set the CINSIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CINSIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CINSIEN_MASK, SDHC_IRQSIGEN_CINSIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CINSIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINSIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field. */
+#define SDHC_RD_IRQSIGEN_CRMIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CRMIEN_MASK) >> SDHC_IRQSIGEN_CRMIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CRMIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CRMIEN_SHIFT))
+
+/*! @brief Set the CRMIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CRMIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CRMIEN_MASK, SDHC_IRQSIGEN_CRMIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CRMIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CRMIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field. */
+#define SDHC_RD_IRQSIGEN_CINTIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CINTIEN_MASK) >> SDHC_IRQSIGEN_CINTIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CINTIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINTIEN_SHIFT))
+
+/*! @brief Set the CINTIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CINTIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CINTIEN_MASK, SDHC_IRQSIGEN_CINTIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CINTIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field. */
+#define SDHC_RD_IRQSIGEN_CTOEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CTOEIEN_MASK) >> SDHC_IRQSIGEN_CTOEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CTOEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CTOEIEN_SHIFT))
+
+/*! @brief Set the CTOEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CTOEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CTOEIEN_MASK, SDHC_IRQSIGEN_CTOEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CTOEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CTOEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field. */
+#define SDHC_RD_IRQSIGEN_CCEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CCEIEN_MASK) >> SDHC_IRQSIGEN_CCEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CCEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCEIEN_SHIFT))
+
+/*! @brief Set the CCEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CCEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CCEIEN_MASK, SDHC_IRQSIGEN_CCEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CCEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field. */
+#define SDHC_RD_IRQSIGEN_CEBEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CEBEIEN_MASK) >> SDHC_IRQSIGEN_CEBEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CEBEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CEBEIEN_SHIFT))
+
+/*! @brief Set the CEBEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CEBEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CEBEIEN_MASK, SDHC_IRQSIGEN_CEBEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CEBEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CEBEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field. */
+#define SDHC_RD_IRQSIGEN_CIEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CIEIEN_MASK) >> SDHC_IRQSIGEN_CIEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CIEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CIEIEN_SHIFT))
+
+/*! @brief Set the CIEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CIEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CIEIEN_MASK, SDHC_IRQSIGEN_CIEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CIEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CIEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field. */
+#define SDHC_RD_IRQSIGEN_DTOEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DTOEIEN_MASK) >> SDHC_IRQSIGEN_DTOEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DTOEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DTOEIEN_SHIFT))
+
+/*! @brief Set the DTOEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DTOEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DTOEIEN_MASK, SDHC_IRQSIGEN_DTOEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DTOEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DTOEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field. */
+#define SDHC_RD_IRQSIGEN_DCEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DCEIEN_MASK) >> SDHC_IRQSIGEN_DCEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DCEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DCEIEN_SHIFT))
+
+/*! @brief Set the DCEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DCEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DCEIEN_MASK, SDHC_IRQSIGEN_DCEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DCEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DCEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field. */
+#define SDHC_RD_IRQSIGEN_DEBEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DEBEIEN_MASK) >> SDHC_IRQSIGEN_DEBEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DEBEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DEBEIEN_SHIFT))
+
+/*! @brief Set the DEBEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DEBEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DEBEIEN_MASK, SDHC_IRQSIGEN_DEBEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DEBEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DEBEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field. */
+#define SDHC_RD_IRQSIGEN_AC12EIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_AC12EIEN_MASK) >> SDHC_IRQSIGEN_AC12EIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_AC12EIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_AC12EIEN_SHIFT))
+
+/*! @brief Set the AC12EIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_AC12EIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_AC12EIEN_MASK, SDHC_IRQSIGEN_AC12EIEN(value)))
+#define SDHC_BWR_IRQSIGEN_AC12EIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_AC12EIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field. */
+#define SDHC_RD_IRQSIGEN_DMAEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DMAEIEN_MASK) >> SDHC_IRQSIGEN_DMAEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DMAEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DMAEIEN_SHIFT))
+
+/*! @brief Set the DMAEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DMAEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DMAEIEN_MASK, SDHC_IRQSIGEN_DMAEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DMAEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DMAEIEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_AC12ERR - Auto CMD12 Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the AC12ESEN bit in the Status register is set, the host driver shall
+ * check this register to identify what kind of error the Auto CMD12 indicated.
+ * This register is valid only when the Auto CMD12 Error status bit is set. The
+ * following table shows the relationship between the Auto CMGD12 CRC error and the
+ * Auto CMD12 command timeout error. Relationship between Command CRC Error and
+ * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
+ * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
+ * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
+ * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
+ * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
+ * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
+ * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
+ * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
+ * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
+ * command that can't be issued. Clear bit 7 if there is no command to issue. The
+ * timing for generating the auto CMD12 error and writing to the command register
+ * are asynchronous. After that, bit 7 shall be sampled when the driver is not
+ * writing to the command register. So it is suggested to read this register only
+ * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
+ * of the error bits (0-4) is set to 1. The command not issued by auto CMD12
+ * error does not generate an interrupt.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_AC12ERR register
+ */
+/*@{*/
+#define SDHC_RD_AC12ERR(base)    (SDHC_AC12ERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_AC12ERR bitfields
+ */
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
+ *
+ * If memory multiple block data transfer is not started, due to a command
+ * error, this bit is not set because it is not necessary to issue an auto CMD12.
+ * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
+ * multiple block data transfer due to some error. If this bit is set to 1, other
+ * error status bits (1-4) have no meaning.
+ *
+ * Values:
+ * - 0b0 - Executed.
+ * - 0b1 - Not executed.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12NE field. */
+#define SDHC_RD_AC12ERR_AC12NE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12NE_MASK) >> SDHC_AC12ERR_AC12NE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12NE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12NE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
+ *
+ * Occurs if no response is returned within 64 SDCLK cycles from the end bit of
+ * the command. If this bit is set to 1, the other error status bits (2-4) have
+ * no meaning.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12TOE field. */
+#define SDHC_RD_AC12ERR_AC12TOE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12TOE_MASK) >> SDHC_AC12ERR_AC12TOE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12TOE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12TOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
+ *
+ * Occurs when detecting that the end bit of command response is 0 which must be
+ * 1.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - End bit error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12EBE field. */
+#define SDHC_RD_AC12ERR_AC12EBE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12EBE_MASK) >> SDHC_AC12ERR_AC12EBE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12EBE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12EBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
+ *
+ * Occurs when detecting a CRC error in the command response.
+ *
+ * Values:
+ * - 0b0 - No CRC error.
+ * - 0b1 - CRC error met in Auto CMD12 response.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12CE field. */
+#define SDHC_RD_AC12ERR_AC12CE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12CE_MASK) >> SDHC_AC12ERR_AC12CE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12CE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12CE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
+ *
+ * Occurs if the command index error occurs in response to a command.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error, the CMD index in response is not CMD12.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12IE field. */
+#define SDHC_RD_AC12ERR_AC12IE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12IE_MASK) >> SDHC_AC12ERR_AC12IE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12IE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12IE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
+ *
+ * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
+ * error (D04-D01) in this register.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Not issued.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field. */
+#define SDHC_RD_AC12ERR_CNIBAC12E(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_CNIBAC12E_MASK) >> SDHC_AC12ERR_CNIBAC12E_SHIFT)
+#define SDHC_BRD_AC12ERR_CNIBAC12E(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_CNIBAC12E_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_HTCAPBLT - Host Controller Capabilities
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_HTCAPBLT - Host Controller Capabilities (RO)
+ *
+ * Reset value: 0x07F30000U
+ *
+ * This register provides the host driver with information specific to the SDHC
+ * implementation. The value in this register is the power-on-reset value, and
+ * does not change with a software reset. Any write to this register is ignored.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_HTCAPBLT register
+ */
+/*@{*/
+#define SDHC_RD_HTCAPBLT(base)   (SDHC_HTCAPBLT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_HTCAPBLT bitfields
+ */
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
+ *
+ * This value indicates the maximum block size that the host driver can read and
+ * write to the buffer in the SDHC. The buffer shall transfer block size without
+ * wait cycles.
+ *
+ * Values:
+ * - 0b000 - 512 bytes
+ * - 0b001 - 1024 bytes
+ * - 0b010 - 2048 bytes
+ * - 0b011 - 4096 bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_MBL field. */
+#define SDHC_RD_HTCAPBLT_MBL(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_MBL_MASK) >> SDHC_HTCAPBLT_MBL_SHIFT)
+#define SDHC_BRD_HTCAPBLT_MBL(base) (SDHC_RD_HTCAPBLT_MBL(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
+ *
+ * This bit indicates whether the SDHC supports the ADMA feature.
+ *
+ * Values:
+ * - 0b0 - Advanced DMA not supported.
+ * - 0b1 - Advanced DMA supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field. */
+#define SDHC_RD_HTCAPBLT_ADMAS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_ADMAS_MASK) >> SDHC_HTCAPBLT_ADMAS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_ADMAS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_ADMAS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
+ *
+ * This bit indicates whether the SDHC supports high speed mode and the host
+ * system can supply a SD Clock frequency from 25 MHz to 50 MHz.
+ *
+ * Values:
+ * - 0b0 - High speed not supported.
+ * - 0b1 - High speed supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_HSS field. */
+#define SDHC_RD_HTCAPBLT_HSS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_HSS_MASK) >> SDHC_HTCAPBLT_HSS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_HSS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_HSS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
+ *
+ * This bit indicates whether the SDHC is capable of using the internal DMA to
+ * transfer data between system memory and the data buffer directly.
+ *
+ * Values:
+ * - 0b0 - DMA not supported.
+ * - 0b1 - DMA supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_DMAS field. */
+#define SDHC_RD_HTCAPBLT_DMAS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_DMAS_MASK) >> SDHC_HTCAPBLT_DMAS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_DMAS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_DMAS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
+ *
+ * This bit indicates whether the SDHC supports suspend / resume functionality.
+ * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
+ * are not supported, and the host driver shall not issue either suspend or
+ * resume commands.
+ *
+ * Values:
+ * - 0b0 - Not supported.
+ * - 0b1 - Supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_SRS field. */
+#define SDHC_RD_HTCAPBLT_SRS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_SRS_MASK) >> SDHC_HTCAPBLT_SRS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_SRS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_SRS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
+ *
+ * This bit shall depend on the host system ability.
+ *
+ * Values:
+ * - 0b0 - 3.3 V not supported.
+ * - 0b1 - 3.3 V supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_VS33 field. */
+#define SDHC_RD_HTCAPBLT_VS33(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_VS33_MASK) >> SDHC_HTCAPBLT_VS33_SHIFT)
+#define SDHC_BRD_HTCAPBLT_VS33(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_VS33_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_WML - Watermark Level Register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_WML - Watermark Level Register (RW)
+ *
+ * Reset value: 0x00100010U
+ *
+ * Both write and read watermark levels (FIFO threshold) are configurable. There
+ * value can range from 1 to 128 words. Both write and read burst lengths are
+ * also configurable. There value can range from 1 to 31 words.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_WML register
+ */
+/*@{*/
+#define SDHC_RD_WML(base)        (SDHC_WML_REG(base))
+#define SDHC_WR_WML(base, value) (SDHC_WML_REG(base) = (value))
+#define SDHC_RMW_WML(base, mask, value) (SDHC_WR_WML(base, (SDHC_RD_WML(base) & ~(mask)) | (value)))
+#define SDHC_SET_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) |  (value)))
+#define SDHC_CLR_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) & ~(value)))
+#define SDHC_TOG_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_WML bitfields
+ */
+
+/*!
+ * @name Register SDHC_WML, field RDWML[7:0] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * read operation. Also the number of words as a sequence of read bursts in
+ * back-to-back mode. The maximum legal value for the read water mark level is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_WML_RDWML field. */
+#define SDHC_RD_WML_RDWML(base) ((SDHC_WML_REG(base) & SDHC_WML_RDWML_MASK) >> SDHC_WML_RDWML_SHIFT)
+#define SDHC_BRD_WML_RDWML(base) (SDHC_RD_WML_RDWML(base))
+
+/*! @brief Set the RDWML field to a new value. */
+#define SDHC_WR_WML_RDWML(base, value) (SDHC_RMW_WML(base, SDHC_WML_RDWML_MASK, SDHC_WML_RDWML(value)))
+#define SDHC_BWR_WML_RDWML(base, value) (SDHC_WR_WML_RDWML(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_WML, field WRWML[23:16] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * write operation. Also the number of words as a sequence of write bursts in
+ * back-to-back mode. The maximum legal value for the write watermark level is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_WML_WRWML field. */
+#define SDHC_RD_WML_WRWML(base) ((SDHC_WML_REG(base) & SDHC_WML_WRWML_MASK) >> SDHC_WML_WRWML_SHIFT)
+#define SDHC_BRD_WML_WRWML(base) (SDHC_RD_WML_WRWML(base))
+
+/*! @brief Set the WRWML field to a new value. */
+#define SDHC_WR_WML_WRWML(base, value) (SDHC_RMW_WML(base, SDHC_WML_WRWML_MASK, SDHC_WML_WRWML(value)))
+#define SDHC_BWR_WML_WRWML(base, value) (SDHC_WR_WML_WRWML(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_FEVT - Force Event register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_FEVT - Force Event register (WO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Force Event (FEVT) register is not a physically implemented register.
+ * Rather, it is an address at which the Interrupt Status register can be written if
+ * the corresponding bit of the Interrupt Status Enable register is set. This
+ * register is a write only register and writing 0 to it has no effect. Writing 1
+ * to this register actually sets the corresponding bit of Interrupt Status
+ * register. A read from this register always results in 0's. To change the
+ * corresponding status bits in the interrupt status register, make sure to set
+ * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
+ * short pulse on the DAT[1] line, and the driver may treat this interrupt as a
+ * normal interrupt. The interrupt service routine may skip polling the card
+ * interrupt factor as the interrupt is selfcleared.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_FEVT register
+ */
+/*@{*/
+#define SDHC_RD_FEVT(base)       (SDHC_FEVT_REG(base))
+#define SDHC_WR_FEVT(base, value) (SDHC_FEVT_REG(base) = (value))
+#define SDHC_RMW_FEVT(base, mask, value) (SDHC_WR_FEVT(base, (SDHC_RD_FEVT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_FEVT bitfields
+ */
+
+/*!
+ * @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
+ *
+ * Forces AC12ERR[AC12NE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12NE field to a new value. */
+#define SDHC_WR_FEVT_AC12NE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12NE_MASK, SDHC_FEVT_AC12NE(value)))
+#define SDHC_BWR_FEVT_AC12NE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12NE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
+ *
+ * Forces AC12ERR[AC12TOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12TOE field to a new value. */
+#define SDHC_WR_FEVT_AC12TOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12TOE_MASK, SDHC_FEVT_AC12TOE(value)))
+#define SDHC_BWR_FEVT_AC12TOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12TOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
+ *
+ * Forces AC12ERR[AC12CE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12CE field to a new value. */
+#define SDHC_WR_FEVT_AC12CE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12CE_MASK, SDHC_FEVT_AC12CE(value)))
+#define SDHC_BWR_FEVT_AC12CE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12CE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
+ *
+ * Forces AC12ERR[AC12EBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12EBE field to a new value. */
+#define SDHC_WR_FEVT_AC12EBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12EBE_MASK, SDHC_FEVT_AC12EBE(value)))
+#define SDHC_BWR_FEVT_AC12EBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12EBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
+ *
+ * Forces AC12ERR[AC12IE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12IE field to a new value. */
+#define SDHC_WR_FEVT_AC12IE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12IE_MASK, SDHC_FEVT_AC12IE(value)))
+#define SDHC_BWR_FEVT_AC12IE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
+ *
+ * Forces AC12ERR[CNIBAC12E] to be set.
+ */
+/*@{*/
+/*! @brief Set the CNIBAC12E field to a new value. */
+#define SDHC_WR_FEVT_CNIBAC12E(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CNIBAC12E_MASK, SDHC_FEVT_CNIBAC12E(value)))
+#define SDHC_BWR_FEVT_CNIBAC12E(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CNIBAC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CTOE[16] (WORZ)
+ *
+ * Forces IRQSTAT[CTOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CTOE field to a new value. */
+#define SDHC_WR_FEVT_CTOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CTOE_MASK, SDHC_FEVT_CTOE(value)))
+#define SDHC_BWR_FEVT_CTOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CCE[17] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CCE field to a new value. */
+#define SDHC_WR_FEVT_CCE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CCE_MASK, SDHC_FEVT_CCE(value)))
+#define SDHC_BWR_FEVT_CCE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CEBE[18] (WORZ)
+ *
+ * Forces IRQSTAT[CEBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CEBE field to a new value. */
+#define SDHC_WR_FEVT_CEBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CEBE_MASK, SDHC_FEVT_CEBE(value)))
+#define SDHC_BWR_FEVT_CEBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CIE[19] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CIE field to a new value. */
+#define SDHC_WR_FEVT_CIE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CIE_MASK, SDHC_FEVT_CIE(value)))
+#define SDHC_BWR_FEVT_CIE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DTOE[20] (WORZ)
+ *
+ * Forces IRQSTAT[DTOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DTOE field to a new value. */
+#define SDHC_WR_FEVT_DTOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DTOE_MASK, SDHC_FEVT_DTOE(value)))
+#define SDHC_BWR_FEVT_DTOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DCE[21] (WORZ)
+ *
+ * Forces IRQSTAT[DCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DCE field to a new value. */
+#define SDHC_WR_FEVT_DCE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DCE_MASK, SDHC_FEVT_DCE(value)))
+#define SDHC_BWR_FEVT_DCE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DEBE[22] (WORZ)
+ *
+ * Forces IRQSTAT[DEBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DEBE field to a new value. */
+#define SDHC_WR_FEVT_DEBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DEBE_MASK, SDHC_FEVT_DEBE(value)))
+#define SDHC_BWR_FEVT_DEBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12E[24] (WORZ)
+ *
+ * Forces IRQSTAT[AC12E] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12E field to a new value. */
+#define SDHC_WR_FEVT_AC12E(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12E_MASK, SDHC_FEVT_AC12E(value)))
+#define SDHC_BWR_FEVT_AC12E(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DMAE[28] (WORZ)
+ *
+ * Forces the DMAE bit of Interrupt Status Register to be set.
+ */
+/*@{*/
+/*! @brief Set the DMAE field to a new value. */
+#define SDHC_WR_FEVT_DMAE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DMAE_MASK, SDHC_FEVT_DMAE(value)))
+#define SDHC_BWR_FEVT_DMAE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DMAE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CINT[31] (WORZ)
+ *
+ * Writing 1 to this bit generates a short low-level pulse on the internal
+ * DAT[1] line, as if a self-clearing interrupt was received from the external card.
+ * If enabled, the CINT bit will be set and the interrupt service routine may
+ * treat this interrupt as a normal interrupt from the external card.
+ */
+/*@{*/
+/*! @brief Set the CINT field to a new value. */
+#define SDHC_WR_FEVT_CINT(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CINT_MASK, SDHC_FEVT_CINT(value)))
+#define SDHC_BWR_FEVT_CINT(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CINT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_ADMAES - ADMA Error Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_ADMAES - ADMA Error Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an ADMA error interrupt has occurred, the ADMA Error States field in
+ * this register holds the ADMA state and the ADMA System Address register holds the
+ * address around the error descriptor. For recovering from this error, the host
+ * driver requires the ADMA state to identify the error descriptor address as
+ * follows: ST_STOP: Previous location set in the ADMA System Address register is
+ * the error descriptor address. ST_FDS: Current location set in the ADMA System
+ * Address register is the error descriptor address. ST_CADR: This state is never
+ * set because it only increments the descriptor pointer and doesn't generate an
+ * ADMA error. ST_TFR: Previous location set in the ADMA System Address register
+ * is the error descriptor address. In case of a write operation, the host driver
+ * must use the ACMD22 to get the number of the written block, rather than using
+ * this information, because unwritten data may exist in the host controller.
+ * The host controller generates the ADMA error interrupt when it detects invalid
+ * descriptor data (valid = 0) in the ST_FDS state. The host driver can
+ * distinguish this error by reading the valid bit of the error descriptor. ADMA Error
+ * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
+ * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
+ * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
+ * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
+ * (Transfer Data) Holds the address of the next executable descriptor command
+ */
+/*!
+ * @name Constants and macros for entire SDHC_ADMAES register
+ */
+/*@{*/
+#define SDHC_RD_ADMAES(base)     (SDHC_ADMAES_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_ADMAES bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
+ *
+ * Indicates the state of the ADMA when an error has occurred during an ADMA
+ * data transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMAES field. */
+#define SDHC_RD_ADMAES_ADMAES(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMAES_MASK) >> SDHC_ADMAES_ADMAES_SHIFT)
+#define SDHC_BRD_ADMAES_ADMAES(base) (SDHC_RD_ADMAES_ADMAES(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMALME[2] (RO)
+ *
+ * This error occurs in the following 2 cases: While the block count enable is
+ * being set, the total data length specified by the descriptor table is different
+ * from that specified by the block count and block length. Total data length
+ * can not be divided by the block length.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMALME field. */
+#define SDHC_RD_ADMAES_ADMALME(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMALME_MASK) >> SDHC_ADMAES_ADMALME_SHIFT)
+#define SDHC_BRD_ADMAES_ADMALME(base) (BITBAND_ACCESS32(&SDHC_ADMAES_REG(base), SDHC_ADMAES_ADMALME_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
+ *
+ * This error occurs when an invalid descriptor is fetched by ADMA.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMADCE field. */
+#define SDHC_RD_ADMAES_ADMADCE(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMADCE_MASK) >> SDHC_ADMAES_ADMADCE_SHIFT)
+#define SDHC_BRD_ADMAES_ADMADCE(base) (BITBAND_ACCESS32(&SDHC_ADMAES_REG(base), SDHC_ADMAES_ADMADCE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_ADSADDR - ADMA System Addressregister
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_ADSADDR - ADMA System Addressregister (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for ADMA
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_ADSADDR register
+ */
+/*@{*/
+#define SDHC_RD_ADSADDR(base)    (SDHC_ADSADDR_REG(base))
+#define SDHC_WR_ADSADDR(base, value) (SDHC_ADSADDR_REG(base) = (value))
+#define SDHC_RMW_ADSADDR(base, mask, value) (SDHC_WR_ADSADDR(base, (SDHC_RD_ADSADDR(base) & ~(mask)) | (value)))
+#define SDHC_SET_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) |  (value)))
+#define SDHC_CLR_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) & ~(value)))
+#define SDHC_TOG_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_ADSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
+ *
+ * Holds the word address of the executing command in the descriptor table. At
+ * the start of ADMA, the host driver shall set the start address of the
+ * Descriptor table. The ADMA engine increments this register address whenever fetching a
+ * descriptor command. When the ADMA is stopped at the block gap, this register
+ * indicates the address of the next executable descriptor command. When the ADMA
+ * error interrupt is generated, this register shall hold the valid descriptor
+ * address depending on the ADMA state. The lower 2 bits of this register is tied
+ * to '0' so the ADMA address is always word-aligned. Because this register
+ * supports dynamic address reflecting, when TC bit is set, it automatically alters the
+ * value of internal address counter, so SW cannot change this register when TC
+ * bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADSADDR_ADSADDR field. */
+#define SDHC_RD_ADSADDR_ADSADDR(base) ((SDHC_ADSADDR_REG(base) & SDHC_ADSADDR_ADSADDR_MASK) >> SDHC_ADSADDR_ADSADDR_SHIFT)
+#define SDHC_BRD_ADSADDR_ADSADDR(base) (SDHC_RD_ADSADDR_ADSADDR(base))
+
+/*! @brief Set the ADSADDR field to a new value. */
+#define SDHC_WR_ADSADDR_ADSADDR(base, value) (SDHC_RMW_ADSADDR(base, SDHC_ADSADDR_ADSADDR_MASK, SDHC_ADSADDR_ADSADDR(value)))
+#define SDHC_BWR_ADSADDR_ADSADDR(base, value) (SDHC_WR_ADSADDR_ADSADDR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_VENDOR - Vendor Specific register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_VENDOR - Vendor Specific register (RW)
+ *
+ * Reset value: 0x00000001U
+ *
+ * This register contains the vendor-specific control/status register.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_VENDOR register
+ */
+/*@{*/
+#define SDHC_RD_VENDOR(base)     (SDHC_VENDOR_REG(base))
+#define SDHC_WR_VENDOR(base, value) (SDHC_VENDOR_REG(base) = (value))
+#define SDHC_RMW_VENDOR(base, mask, value) (SDHC_WR_VENDOR(base, (SDHC_RD_VENDOR(base) & ~(mask)) | (value)))
+#define SDHC_SET_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) |  (value)))
+#define SDHC_CLR_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) & ~(value)))
+#define SDHC_TOG_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_VENDOR bitfields
+ */
+
+/*!
+ * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
+ *
+ * Enables the request to external DMA. When the internal DMA (either simple DMA
+ * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
+ * request when the internal buffer is ready. This bit is particularly useful when
+ * transferring data by CPU polling mode, and it is not allowed to send out the
+ * external DMA request. By default, this bit is set.
+ *
+ * Values:
+ * - 0b0 - In any scenario, SDHC does not send out the external DMA request.
+ * - 0b1 - When internal DMA is not active, the external DMA request will be
+ *     sent out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field. */
+#define SDHC_RD_VENDOR_EXTDMAEN(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_EXTDMAEN_MASK) >> SDHC_VENDOR_EXTDMAEN_SHIFT)
+#define SDHC_BRD_VENDOR_EXTDMAEN(base) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXTDMAEN_SHIFT))
+
+/*! @brief Set the EXTDMAEN field to a new value. */
+#define SDHC_WR_VENDOR_EXTDMAEN(base, value) (SDHC_RMW_VENDOR(base, SDHC_VENDOR_EXTDMAEN_MASK, SDHC_VENDOR_EXTDMAEN(value)))
+#define SDHC_BWR_VENDOR_EXTDMAEN(base, value) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXTDMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
+ *
+ * This bit must be set before S/W issues CMD53 multi-block read with exact
+ * block number. This bit must not be set if the CMD53 multi-block read is not exact
+ * block number.
+ *
+ * Values:
+ * - 0b0 - None exact block read.
+ * - 0b1 - Exact block read for SDIO CMD53.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_EXBLKNU field. */
+#define SDHC_RD_VENDOR_EXBLKNU(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_EXBLKNU_MASK) >> SDHC_VENDOR_EXBLKNU_SHIFT)
+#define SDHC_BRD_VENDOR_EXBLKNU(base) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXBLKNU_SHIFT))
+
+/*! @brief Set the EXBLKNU field to a new value. */
+#define SDHC_WR_VENDOR_EXBLKNU(base, value) (SDHC_RMW_VENDOR(base, SDHC_VENDOR_EXBLKNU_MASK, SDHC_VENDOR_EXBLKNU(value)))
+#define SDHC_BWR_VENDOR_EXBLKNU(base, value) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXBLKNU_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
+ *
+ * Internal state value, reflecting the corresponding state value selected by
+ * Debug Select field. This field is read-only and write to this field does not
+ * have effect.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_INTSTVAL field. */
+#define SDHC_RD_VENDOR_INTSTVAL(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_INTSTVAL_MASK) >> SDHC_VENDOR_INTSTVAL_SHIFT)
+#define SDHC_BRD_VENDOR_INTSTVAL(base) (SDHC_RD_VENDOR_INTSTVAL(base))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_MMCBOOT - MMC Boot register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_MMCBOOT - MMC Boot register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the MMC fast boot control register.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_MMCBOOT register
+ */
+/*@{*/
+#define SDHC_RD_MMCBOOT(base)    (SDHC_MMCBOOT_REG(base))
+#define SDHC_WR_MMCBOOT(base, value) (SDHC_MMCBOOT_REG(base) = (value))
+#define SDHC_RMW_MMCBOOT(base, mask, value) (SDHC_WR_MMCBOOT(base, (SDHC_RD_MMCBOOT(base) & ~(mask)) | (value)))
+#define SDHC_SET_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) |  (value)))
+#define SDHC_CLR_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) & ~(value)))
+#define SDHC_TOG_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_MMCBOOT bitfields
+ */
+
+/*!
+ * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
+ *
+ * Values:
+ * - 0b0000 - SDCLK x 2^8
+ * - 0b0001 - SDCLK x 2^9
+ * - 0b0010 - SDCLK x 2^10
+ * - 0b0011 - SDCLK x 2^11
+ * - 0b0100 - SDCLK x 2^12
+ * - 0b0101 - SDCLK x 2^13
+ * - 0b0110 - SDCLK x 2^14
+ * - 0b0111 - SDCLK x 2^15
+ * - 0b1110 - SDCLK x 2^22
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field. */
+#define SDHC_RD_MMCBOOT_DTOCVACK(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_DTOCVACK_MASK) >> SDHC_MMCBOOT_DTOCVACK_SHIFT)
+#define SDHC_BRD_MMCBOOT_DTOCVACK(base) (SDHC_RD_MMCBOOT_DTOCVACK(base))
+
+/*! @brief Set the DTOCVACK field to a new value. */
+#define SDHC_WR_MMCBOOT_DTOCVACK(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_DTOCVACK_MASK, SDHC_MMCBOOT_DTOCVACK(value)))
+#define SDHC_BWR_MMCBOOT_DTOCVACK(base, value) (SDHC_WR_MMCBOOT_DTOCVACK(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
+ *
+ * Values:
+ * - 0b0 - No ack.
+ * - 0b1 - Ack.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field. */
+#define SDHC_RD_MMCBOOT_BOOTACK(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTACK_MASK) >> SDHC_MMCBOOT_BOOTACK_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTACK(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTACK_SHIFT))
+
+/*! @brief Set the BOOTACK field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTACK(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTACK_MASK, SDHC_MMCBOOT_BOOTACK(value)))
+#define SDHC_BWR_MMCBOOT_BOOTACK(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal boot.
+ * - 0b1 - Alternative boot.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field. */
+#define SDHC_RD_MMCBOOT_BOOTMODE(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTMODE_MASK) >> SDHC_MMCBOOT_BOOTMODE_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTMODE(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTMODE_SHIFT))
+
+/*! @brief Set the BOOTMODE field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTMODE(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTMODE_MASK, SDHC_MMCBOOT_BOOTMODE(value)))
+#define SDHC_BWR_MMCBOOT_BOOTMODE(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Fast boot disable.
+ * - 0b1 - Fast boot enable.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field. */
+#define SDHC_RD_MMCBOOT_BOOTEN(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTEN_MASK) >> SDHC_MMCBOOT_BOOTEN_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTEN(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTEN_SHIFT))
+
+/*! @brief Set the BOOTEN field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTEN(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTEN_MASK, SDHC_MMCBOOT_BOOTEN(value)))
+#define SDHC_BWR_MMCBOOT_BOOTEN(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
+ *
+ * When boot, enable auto stop at block gap function. This function will be
+ * triggered, and host will stop at block gap when received card block cnt is equal
+ * to BOOTBLKCNT.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field. */
+#define SDHC_RD_MMCBOOT_AUTOSABGEN(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_AUTOSABGEN_MASK) >> SDHC_MMCBOOT_AUTOSABGEN_SHIFT)
+#define SDHC_BRD_MMCBOOT_AUTOSABGEN(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_AUTOSABGEN_SHIFT))
+
+/*! @brief Set the AUTOSABGEN field to a new value. */
+#define SDHC_WR_MMCBOOT_AUTOSABGEN(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_AUTOSABGEN_MASK, SDHC_MMCBOOT_AUTOSABGEN(value)))
+#define SDHC_BWR_MMCBOOT_AUTOSABGEN(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_AUTOSABGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
+ *
+ * Defines the stop at block gap value of automatic mode. When received card
+ * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field. */
+#define SDHC_RD_MMCBOOT_BOOTBLKCNT(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTBLKCNT_MASK) >> SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTBLKCNT(base) (SDHC_RD_MMCBOOT_BOOTBLKCNT(base))
+
+/*! @brief Set the BOOTBLKCNT field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTBLKCNT(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTBLKCNT_MASK, SDHC_MMCBOOT_BOOTBLKCNT(value)))
+#define SDHC_BWR_MMCBOOT_BOOTBLKCNT(base, value) (SDHC_WR_MMCBOOT_BOOTBLKCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_HOSTVER - Host Controller Version
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_HOSTVER - Host Controller Version (RO)
+ *
+ * Reset value: 0x00001201U
+ *
+ * This register contains the vendor host controller version information. All
+ * bits are read only and will read the same as the power-reset value.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_HOSTVER register
+ */
+/*@{*/
+#define SDHC_RD_HOSTVER(base)    (SDHC_HOSTVER_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_HOSTVER bitfields
+ */
+
+/*!
+ * @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
+ *
+ * These status bits indicate the host controller specification version.
+ *
+ * Values:
+ * - 0b00000001 - SD host specification version 2.0, supports test event
+ *     register and ADMA.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HOSTVER_SVN field. */
+#define SDHC_RD_HOSTVER_SVN(base) ((SDHC_HOSTVER_REG(base) & SDHC_HOSTVER_SVN_MASK) >> SDHC_HOSTVER_SVN_SHIFT)
+#define SDHC_BRD_HOSTVER_SVN(base) (SDHC_RD_HOSTVER_SVN(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
+ *
+ * These status bits are reserved for the vendor version number. The host driver
+ * shall not use this status.
+ *
+ * Values:
+ * - 0b00000000 - Freescale SDHC version 1.0
+ * - 0b00010000 - Freescale SDHC version 2.0
+ * - 0b00010001 - Freescale SDHC version 2.1
+ * - 0b00010010 - Freescale SDHC version 2.2
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HOSTVER_VVN field. */
+#define SDHC_RD_HOSTVER_VVN(base) ((SDHC_HOSTVER_REG(base) & SDHC_HOSTVER_VVN_MASK) >> SDHC_HOSTVER_VVN_SHIFT)
+#define SDHC_BRD_HOSTVER_VVN(base) (SDHC_RD_HOSTVER_VVN(base))
+/*@}*/
+
+/*
+ * MK64F12 SIM
+ *
+ * System Integration Module
+ *
+ * Registers defined in this header file:
+ * - SIM_SOPT1 - System Options Register 1
+ * - SIM_SOPT1CFG - SOPT1 Configuration Register
+ * - SIM_SOPT2 - System Options Register 2
+ * - SIM_SOPT4 - System Options Register 4
+ * - SIM_SOPT5 - System Options Register 5
+ * - SIM_SOPT7 - System Options Register 7
+ * - SIM_SDID - System Device Identification Register
+ * - SIM_SCGC1 - System Clock Gating Control Register 1
+ * - SIM_SCGC2 - System Clock Gating Control Register 2
+ * - SIM_SCGC3 - System Clock Gating Control Register 3
+ * - SIM_SCGC4 - System Clock Gating Control Register 4
+ * - SIM_SCGC5 - System Clock Gating Control Register 5
+ * - SIM_SCGC6 - System Clock Gating Control Register 6
+ * - SIM_SCGC7 - System Clock Gating Control Register 7
+ * - SIM_CLKDIV1 - System Clock Divider Register 1
+ * - SIM_CLKDIV2 - System Clock Divider Register 2
+ * - SIM_FCFG1 - Flash Configuration Register 1
+ * - SIM_FCFG2 - Flash Configuration Register 2
+ * - SIM_UIDH - Unique Identification Register High
+ * - SIM_UIDMH - Unique Identification Register Mid-High
+ * - SIM_UIDML - Unique Identification Register Mid Low
+ * - SIM_UIDL - Unique Identification Register Low
+ */
+
+#define SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */
+#define SIM_IDX (0U) /*!< Instance number for SIM. */
+
+/*******************************************************************************
+ * SIM_SOPT1 - System Options Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1 - System Options Register 1 (RW)
+ *
+ * Reset value: 0x80000000U
+ *
+ * The SOPT1 register is only reset on POR or LVD.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1 register
+ */
+/*@{*/
+#define SIM_RD_SOPT1(base)       (SIM_SOPT1_REG(base))
+#define SIM_WR_SOPT1(base, value) (SIM_SOPT1_REG(base) = (value))
+#define SIM_RMW_SOPT1(base, mask, value) (SIM_WR_SOPT1(base, (SIM_RD_SOPT1(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) |  (value)))
+#define SIM_CLR_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) & ~(value)))
+#define SIM_TOG_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
+ *
+ * This field specifies the amount of system RAM available on the device.
+ *
+ * Values:
+ * - 0b0001 - 8 KB
+ * - 0b0011 - 16 KB
+ * - 0b0100 - 24 KB
+ * - 0b0101 - 32 KB
+ * - 0b0110 - 48 KB
+ * - 0b0111 - 64 KB
+ * - 0b1000 - 96 KB
+ * - 0b1001 - 128 KB
+ * - 0b1011 - 256 KB
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */
+#define SIM_RD_SOPT1_RAMSIZE(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_RAMSIZE_MASK) >> SIM_SOPT1_RAMSIZE_SHIFT)
+#define SIM_BRD_SOPT1_RAMSIZE(base) (SIM_RD_SOPT1_RAMSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
+ *
+ * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
+ * only on POR/LVD.
+ *
+ * Values:
+ * - 0b00 - System oscillator (OSC32KCLK)
+ * - 0b01 - Reserved
+ * - 0b10 - RTC 32.768kHz oscillator
+ * - 0b11 - LPO 1 kHz
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */
+#define SIM_RD_SOPT1_OSC32KSEL(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
+#define SIM_BRD_SOPT1_OSC32KSEL(base) (SIM_RD_SOPT1_OSC32KSEL(base))
+
+/*! @brief Set the OSC32KSEL field to a new value. */
+#define SIM_WR_SOPT1_OSC32KSEL(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_OSC32KSEL_MASK, SIM_SOPT1_OSC32KSEL(value)))
+#define SIM_BWR_SOPT1_OSC32KSEL(base, value) (SIM_WR_SOPT1_OSC32KSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * VLPR and VLPW modes.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator not in standby during VLPR and VLPW modes.
+ * - 0b1 - USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */
+#define SIM_RD_SOPT1_USBVSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBVSTBY_MASK) >> SIM_SOPT1_USBVSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBVSTBY(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT))
+
+/*! @brief Set the USBVSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBVSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBVSTBY_MASK, SIM_SOPT1_USBVSTBY(value)))
+#define SIM_BWR_SOPT1_USBVSTBY(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * Stop, VLPS, LLS and VLLS modes.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ * - 0b1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */
+#define SIM_RD_SOPT1_USBSSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBSSTBY_MASK) >> SIM_SOPT1_USBSSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBSSTBY(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT))
+
+/*! @brief Set the USBSSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBSSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBSSTBY_MASK, SIM_SOPT1_USBSSTBY(value)))
+#define SIM_BWR_SOPT1_USBSSTBY(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
+ *
+ * Controls whether the USB voltage regulator is enabled.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator is disabled.
+ * - 0b1 - USB voltage regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */
+#define SIM_RD_SOPT1_USBREGEN(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBREGEN_MASK) >> SIM_SOPT1_USBREGEN_SHIFT)
+#define SIM_BRD_SOPT1_USBREGEN(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT))
+
+/*! @brief Set the USBREGEN field to a new value. */
+#define SIM_WR_SOPT1_USBREGEN(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBREGEN_MASK, SIM_SOPT1_USBREGEN(value)))
+#define SIM_BWR_SOPT1_USBREGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT1CFG - SOPT1 Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The SOPT1CFG register is reset on System Reset not VLLS.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1CFG register
+ */
+/*@{*/
+#define SIM_RD_SOPT1CFG(base)    (SIM_SOPT1CFG_REG(base))
+#define SIM_WR_SOPT1CFG(base, value) (SIM_SOPT1CFG_REG(base) = (value))
+#define SIM_RMW_SOPT1CFG(base, mask, value) (SIM_WR_SOPT1CFG(base, (SIM_RD_SOPT1CFG(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) |  (value)))
+#define SIM_CLR_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) & ~(value)))
+#define SIM_TOG_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1CFG bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
+ *
+ * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
+ * register bit clears after a write to USBREGEN.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBREGEN cannot be written.
+ * - 0b1 - SOPT1 USBREGEN can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */
+#define SIM_RD_SOPT1CFG_URWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_URWE_MASK) >> SIM_SOPT1CFG_URWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_URWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT))
+
+/*! @brief Set the URWE field to a new value. */
+#define SIM_WR_SOPT1CFG_URWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_URWE_MASK, SIM_SOPT1CFG_URWE(value)))
+#define SIM_BWR_SOPT1CFG_URWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
+ *
+ * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
+ * This register bit clears after a write to USBVSTBY.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBVSTBY cannot be written.
+ * - 0b1 - SOPT1 USBVSTBY can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */
+#define SIM_RD_SOPT1CFG_UVSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_UVSWE_MASK) >> SIM_SOPT1CFG_UVSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_UVSWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT))
+
+/*! @brief Set the UVSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_UVSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_UVSWE_MASK, SIM_SOPT1CFG_UVSWE(value)))
+#define SIM_BWR_SOPT1CFG_UVSWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
+ *
+ * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
+ * This register bit clears after a write to USBSSTBY.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBSSTBY cannot be written.
+ * - 0b1 - SOPT1 USBSSTBY can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */
+#define SIM_RD_SOPT1CFG_USSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_USSWE_MASK) >> SIM_SOPT1CFG_USSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_USSWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT))
+
+/*! @brief Set the USSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_USSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_USSWE_MASK, SIM_SOPT1CFG_USSWE(value)))
+#define SIM_BWR_SOPT1CFG_USSWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT2 - System Options Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT2 - System Options Register 2 (RW)
+ *
+ * Reset value: 0x00001000U
+ *
+ * SOPT2 contains the controls for selecting many of the module clock source
+ * options on this device. See the Clock Distribution chapter for more information
+ * including clocking diagrams and definitions of device clocks.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT2 register
+ */
+/*@{*/
+#define SIM_RD_SOPT2(base)       (SIM_SOPT2_REG(base))
+#define SIM_WR_SOPT2(base, value) (SIM_SOPT2_REG(base) = (value))
+#define SIM_RMW_SOPT2(base, mask, value) (SIM_WR_SOPT2(base, (SIM_RD_SOPT2(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) |  (value)))
+#define SIM_CLR_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) & ~(value)))
+#define SIM_TOG_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
+ *
+ * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
+ * RTC_CLKOUT pin.
+ *
+ * Values:
+ * - 0b0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
+ * - 0b1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */
+#define SIM_RD_SOPT2_RTCCLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RTCCLKOUTSEL_MASK) >> SIM_SOPT2_RTCCLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_RTCCLKOUTSEL(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT))
+
+/*! @brief Set the RTCCLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_RTCCLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RTCCLKOUTSEL_MASK, SIM_SOPT2_RTCCLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_RTCCLKOUTSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
+ *
+ * Selects the clock to output on the CLKOUT pin.
+ *
+ * Values:
+ * - 0b000 - FlexBus CLKOUT
+ * - 0b001 - Reserved
+ * - 0b010 - Flash clock
+ * - 0b011 - LPO clock (1 kHz)
+ * - 0b100 - MCGIRCLK
+ * - 0b101 - RTC 32.768kHz clock
+ * - 0b110 - OSCERCLK0
+ * - 0b111 - IRC 48 MHz clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */
+#define SIM_RD_SOPT2_CLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_CLKOUTSEL_MASK) >> SIM_SOPT2_CLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_CLKOUTSEL(base) (SIM_RD_SOPT2_CLKOUTSEL(base))
+
+/*! @brief Set the CLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_CLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_CLKOUTSEL_MASK, SIM_SOPT2_CLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_CLKOUTSEL(base, value) (SIM_WR_SOPT2_CLKOUTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
+ *
+ * If flash security is enabled, then this field affects what CPU operations can
+ * access off-chip via the FlexBus interface. This field has no effect if flash
+ * security is not enabled.
+ *
+ * Values:
+ * - 0b00 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 0b01 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 0b10 - Off-chip instruction accesses are disallowed. Data accesses are
+ *     allowed.
+ * - 0b11 - Off-chip instruction accesses and data accesses are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_FBSL field. */
+#define SIM_RD_SOPT2_FBSL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_FBSL_MASK) >> SIM_SOPT2_FBSL_SHIFT)
+#define SIM_BRD_SOPT2_FBSL(base) (SIM_RD_SOPT2_FBSL(base))
+
+/*! @brief Set the FBSL field to a new value. */
+#define SIM_WR_SOPT2_FBSL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_FBSL_MASK, SIM_SOPT2_FBSL(value)))
+#define SIM_BWR_SOPT2_FBSL(base, value) (SIM_WR_SOPT2_FBSL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
+ *
+ * Controls the output drive strength of the PTD7 pin by selecting either one or
+ * two pads to drive it.
+ *
+ * Values:
+ * - 0b0 - Single-pad drive strength for PTD7.
+ * - 0b1 - Double pad drive strength for PTD7.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_PTD7PAD field. */
+#define SIM_RD_SOPT2_PTD7PAD(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_PTD7PAD_MASK) >> SIM_SOPT2_PTD7PAD_SHIFT)
+#define SIM_BRD_SOPT2_PTD7PAD(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_PTD7PAD_SHIFT))
+
+/*! @brief Set the PTD7PAD field to a new value. */
+#define SIM_WR_SOPT2_PTD7PAD(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_PTD7PAD_MASK, SIM_SOPT2_PTD7PAD(value)))
+#define SIM_BWR_SOPT2_PTD7PAD(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_PTD7PAD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
+ *
+ * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
+ * clock source.
+ *
+ * Values:
+ * - 0b0 - MCGOUTCLK
+ * - 0b1 - Core/system clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */
+#define SIM_RD_SOPT2_TRACECLKSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TRACECLKSEL_MASK) >> SIM_SOPT2_TRACECLKSEL_SHIFT)
+#define SIM_BRD_SOPT2_TRACECLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_TRACECLKSEL_SHIFT))
+
+/*! @brief Set the TRACECLKSEL field to a new value. */
+#define SIM_WR_SOPT2_TRACECLKSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TRACECLKSEL_MASK, SIM_SOPT2_TRACECLKSEL(value)))
+#define SIM_BWR_SOPT2_TRACECLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_TRACECLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
+ *
+ * Selects the high frequency clock for various peripheral clocking options.
+ *
+ * Values:
+ * - 0b00 - MCGFLLCLK clock
+ * - 0b01 - MCGPLLCLK clock
+ * - 0b10 - Reserved
+ * - 0b11 - IRC48 MHz clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */
+#define SIM_RD_SOPT2_PLLFLLSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
+#define SIM_BRD_SOPT2_PLLFLLSEL(base) (SIM_RD_SOPT2_PLLFLLSEL(base))
+
+/*! @brief Set the PLLFLLSEL field to a new value. */
+#define SIM_WR_SOPT2_PLLFLLSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_PLLFLLSEL_MASK, SIM_SOPT2_PLLFLLSEL(value)))
+#define SIM_BWR_SOPT2_PLLFLLSEL(base, value) (SIM_WR_SOPT2_PLLFLLSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field USBSRC[18] (RW)
+ *
+ * Selects the clock source for the USB 48 MHz clock.
+ *
+ * Values:
+ * - 0b0 - External bypass clock (USB_CLKIN).
+ * - 0b1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
+ *     SIM_CLKDIV2[USBFRAC, USBDIV].
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_USBSRC field. */
+#define SIM_RD_SOPT2_USBSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_USBSRC_MASK) >> SIM_SOPT2_USBSRC_SHIFT)
+#define SIM_BRD_SOPT2_USBSRC(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT))
+
+/*! @brief Set the USBSRC field to a new value. */
+#define SIM_WR_SOPT2_USBSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_USBSRC_MASK, SIM_SOPT2_USBSRC(value)))
+#define SIM_BWR_SOPT2_USBSRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field RMIISRC[19] (RW)
+ *
+ * Selects the clock source for the Ethernet RMII interface
+ *
+ * Values:
+ * - 0b0 - EXTAL clock
+ * - 0b1 - External bypass clock (ENET_1588_CLKIN).
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RMIISRC field. */
+#define SIM_RD_SOPT2_RMIISRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RMIISRC_MASK) >> SIM_SOPT2_RMIISRC_SHIFT)
+#define SIM_BRD_SOPT2_RMIISRC(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RMIISRC_SHIFT))
+
+/*! @brief Set the RMIISRC field to a new value. */
+#define SIM_WR_SOPT2_RMIISRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RMIISRC_MASK, SIM_SOPT2_RMIISRC(value)))
+#define SIM_BWR_SOPT2_RMIISRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RMIISRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
+ *
+ * Selects the clock source for the Ethernet timestamp clock.
+ *
+ * Values:
+ * - 0b00 - Core/system clock.
+ * - 0b01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 0b10 - OSCERCLK clock
+ * - 0b11 - External bypass clock (ENET_1588_CLKIN).
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TIMESRC field. */
+#define SIM_RD_SOPT2_TIMESRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TIMESRC_MASK) >> SIM_SOPT2_TIMESRC_SHIFT)
+#define SIM_BRD_SOPT2_TIMESRC(base) (SIM_RD_SOPT2_TIMESRC(base))
+
+/*! @brief Set the TIMESRC field to a new value. */
+#define SIM_WR_SOPT2_TIMESRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TIMESRC_MASK, SIM_SOPT2_TIMESRC(value)))
+#define SIM_BWR_SOPT2_TIMESRC(base, value) (SIM_WR_SOPT2_TIMESRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
+ *
+ * Selects the clock source for the SDHC clock .
+ *
+ * Values:
+ * - 0b00 - Core/system clock.
+ * - 0b01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 0b10 - OSCERCLK clock
+ * - 0b11 - External bypass clock (SDHC0_CLKIN)
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_SDHCSRC field. */
+#define SIM_RD_SOPT2_SDHCSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_SDHCSRC_MASK) >> SIM_SOPT2_SDHCSRC_SHIFT)
+#define SIM_BRD_SOPT2_SDHCSRC(base) (SIM_RD_SOPT2_SDHCSRC(base))
+
+/*! @brief Set the SDHCSRC field to a new value. */
+#define SIM_WR_SOPT2_SDHCSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_SDHCSRC_MASK, SIM_SOPT2_SDHCSRC(value)))
+#define SIM_BWR_SOPT2_SDHCSRC(base, value) (SIM_WR_SOPT2_SDHCSRC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT4 - System Options Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT4 - System Options Register 4 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT4 register
+ */
+/*@{*/
+#define SIM_RD_SOPT4(base)       (SIM_SOPT4_REG(base))
+#define SIM_WR_SOPT4(base, value) (SIM_SOPT4_REG(base) = (value))
+#define SIM_RMW_SOPT4(base, mask, value) (SIM_WR_SOPT4(base, (SIM_RD_SOPT4(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) |  (value)))
+#define SIM_CLR_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) & ~(value)))
+#define SIM_TOG_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
+ *
+ * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */
+#define SIM_RD_SOPT4_FTM0FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT0_MASK) >> SIM_SOPT4_FTM0FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT0_SHIFT))
+
+/*! @brief Set the FTM0FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT0_MASK, SIM_SOPT4_FTM0FLT0(value)))
+#define SIM_BWR_SOPT4_FTM0FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
+ *
+ * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT1 pin
+ * - 0b1 - CMP1 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */
+#define SIM_RD_SOPT4_FTM0FLT1(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT1_MASK) >> SIM_SOPT4_FTM0FLT1_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT1(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT1_SHIFT))
+
+/*! @brief Set the FTM0FLT1 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT1(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT1_MASK, SIM_SOPT4_FTM0FLT1(value)))
+#define SIM_BWR_SOPT4_FTM0FLT1(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
+ *
+ * Selects the source of FTM0 fault 2. The pin source for fault 2 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT2 pin
+ * - 0b1 - CMP2 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. */
+#define SIM_RD_SOPT4_FTM0FLT2(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT2_MASK) >> SIM_SOPT4_FTM0FLT2_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT2(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT2_SHIFT))
+
+/*! @brief Set the FTM0FLT2 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT2(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT2_MASK, SIM_SOPT4_FTM0FLT2(value)))
+#define SIM_BWR_SOPT4_FTM0FLT2(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
+ *
+ * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM1_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */
+#define SIM_RD_SOPT4_FTM1FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1FLT0_MASK) >> SIM_SOPT4_FTM1FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM1FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1FLT0_SHIFT))
+
+/*! @brief Set the FTM1FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM1FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1FLT0_MASK, SIM_SOPT4_FTM1FLT0(value)))
+#define SIM_BWR_SOPT4_FTM1FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
+ *
+ * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0b0 - FTM2_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */
+#define SIM_RD_SOPT4_FTM2FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2FLT0_MASK) >> SIM_SOPT4_FTM2FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM2FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2FLT0_SHIFT))
+
+/*! @brief Set the FTM2FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM2FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2FLT0_MASK, SIM_SOPT4_FTM2FLT0(value)))
+#define SIM_BWR_SOPT4_FTM2FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
+ *
+ * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0b0 - FTM3_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */
+#define SIM_RD_SOPT4_FTM3FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3FLT0_MASK) >> SIM_SOPT4_FTM3FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM3FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3FLT0_SHIFT))
+
+/*! @brief Set the FTM3FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM3FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3FLT0_MASK, SIM_SOPT4_FTM3FLT0(value)))
+#define SIM_BWR_SOPT4_FTM3FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
+ *
+ * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0b00 - FTM1_CH0 signal
+ * - 0b01 - CMP0 output
+ * - 0b10 - CMP1 output
+ * - 0b11 - USB start of frame pulse
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */
+#define SIM_RD_SOPT4_FTM1CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1CH0SRC_MASK) >> SIM_SOPT4_FTM1CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM1CH0SRC(base) (SIM_RD_SOPT4_FTM1CH0SRC(base))
+
+/*! @brief Set the FTM1CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM1CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1CH0SRC_MASK, SIM_SOPT4_FTM1CH0SRC(value)))
+#define SIM_BWR_SOPT4_FTM1CH0SRC(base, value) (SIM_WR_SOPT4_FTM1CH0SRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
+ *
+ * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0b00 - FTM2_CH0 signal
+ * - 0b01 - CMP0 output
+ * - 0b10 - CMP1 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */
+#define SIM_RD_SOPT4_FTM2CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2CH0SRC_MASK) >> SIM_SOPT4_FTM2CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM2CH0SRC(base) (SIM_RD_SOPT4_FTM2CH0SRC(base))
+
+/*! @brief Set the FTM2CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM2CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2CH0SRC_MASK, SIM_SOPT4_FTM2CH0SRC(value)))
+#define SIM_BWR_SOPT4_FTM2CH0SRC(base, value) (SIM_WR_SOPT4_FTM2CH0SRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM0 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM_CLK0 pin
+ * - 0b1 - FTM_CLK1 pin
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */
+#define SIM_RD_SOPT4_FTM0CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0CLKSEL_MASK) >> SIM_SOPT4_FTM0CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM0CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0CLKSEL_SHIFT))
+
+/*! @brief Set the FTM0CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM0CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0CLKSEL_MASK, SIM_SOPT4_FTM0CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM0CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM1 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM_CLK0 pin
+ * - 0b1 - FTM_CLK1 pin
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */
+#define SIM_RD_SOPT4_FTM1CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1CLKSEL_MASK) >> SIM_SOPT4_FTM1CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM1CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1CLKSEL_SHIFT))
+
+/*! @brief Set the FTM1CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM1CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1CLKSEL_MASK, SIM_SOPT4_FTM1CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM1CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM2 module. The
+ * selected pin must also be configured for the FTM2 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM2 external clock driven by FTM_CLK0 pin.
+ * - 0b1 - FTM2 external clock driven by FTM_CLK1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */
+#define SIM_RD_SOPT4_FTM2CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2CLKSEL_MASK) >> SIM_SOPT4_FTM2CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM2CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2CLKSEL_SHIFT))
+
+/*! @brief Set the FTM2CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM2CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2CLKSEL_MASK, SIM_SOPT4_FTM2CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM2CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM3 module. The
+ * selected pin must also be configured for the FTM3 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM3 external clock driven by FTM_CLK0 pin.
+ * - 0b1 - FTM3 external clock driven by FTM_CLK1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */
+#define SIM_RD_SOPT4_FTM3CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3CLKSEL_MASK) >> SIM_SOPT4_FTM3CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM3CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3CLKSEL_SHIFT))
+
+/*! @brief Set the FTM3CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM3CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3CLKSEL_MASK, SIM_SOPT4_FTM3CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM3CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 0.
+ *
+ * Values:
+ * - 0b0 - HSCMP0 output drives FTM0 hardware trigger 0
+ * - 0b1 - FTM1 channel match drives FTM0 hardware trigger 0
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */
+#define SIM_RD_SOPT4_FTM0TRG0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0TRG0SRC_MASK) >> SIM_SOPT4_FTM0TRG0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM0TRG0SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG0SRC_SHIFT))
+
+/*! @brief Set the FTM0TRG0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM0TRG0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0TRG0SRC_MASK, SIM_SOPT4_FTM0TRG0SRC(value)))
+#define SIM_BWR_SOPT4_FTM0TRG0SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG0SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 1.
+ *
+ * Values:
+ * - 0b0 - PDB output trigger 1 drives FTM0 hardware trigger 1
+ * - 0b1 - FTM2 channel match drives FTM0 hardware trigger 1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */
+#define SIM_RD_SOPT4_FTM0TRG1SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0TRG1SRC_MASK) >> SIM_SOPT4_FTM0TRG1SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM0TRG1SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG1SRC_SHIFT))
+
+/*! @brief Set the FTM0TRG1SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM0TRG1SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0TRG1SRC_MASK, SIM_SOPT4_FTM0TRG1SRC(value)))
+#define SIM_BWR_SOPT4_FTM0TRG1SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG1SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 0.
+ *
+ * Values:
+ * - 0b0 - Reserved
+ * - 0b1 - FTM1 channel match drives FTM3 hardware trigger 0
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */
+#define SIM_RD_SOPT4_FTM3TRG0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3TRG0SRC_MASK) >> SIM_SOPT4_FTM3TRG0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM3TRG0SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG0SRC_SHIFT))
+
+/*! @brief Set the FTM3TRG0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM3TRG0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3TRG0SRC_MASK, SIM_SOPT4_FTM3TRG0SRC(value)))
+#define SIM_BWR_SOPT4_FTM3TRG0SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG0SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 1.
+ *
+ * Values:
+ * - 0b0 - Reserved
+ * - 0b1 - FTM2 channel match drives FTM3 hardware trigger 1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */
+#define SIM_RD_SOPT4_FTM3TRG1SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3TRG1SRC_MASK) >> SIM_SOPT4_FTM3TRG1SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM3TRG1SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG1SRC_SHIFT))
+
+/*! @brief Set the FTM3TRG1SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM3TRG1SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3TRG1SRC_MASK, SIM_SOPT4_FTM3TRG1SRC(value)))
+#define SIM_BWR_SOPT4_FTM3TRG1SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG1SRC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT5 - System Options Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT5 - System Options Register 5 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT5 register
+ */
+/*@{*/
+#define SIM_RD_SOPT5(base)       (SIM_SOPT5_REG(base))
+#define SIM_WR_SOPT5(base, value) (SIM_SOPT5_REG(base) = (value))
+#define SIM_RMW_SOPT5(base, mask, value) (SIM_WR_SOPT5(base, (SIM_RD_SOPT5(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) |  (value)))
+#define SIM_CLR_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) & ~(value)))
+#define SIM_TOG_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
+ *
+ * Selects the source for the UART 0 transmit data.
+ *
+ * Values:
+ * - 0b00 - UART0_TX pin
+ * - 0b01 - UART0_TX pin modulated with FTM1 channel 0 output
+ * - 0b10 - UART0_TX pin modulated with FTM2 channel 0 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */
+#define SIM_RD_SOPT5_UART0TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART0TXSRC_MASK) >> SIM_SOPT5_UART0TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART0TXSRC(base) (SIM_RD_SOPT5_UART0TXSRC(base))
+
+/*! @brief Set the UART0TXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART0TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART0TXSRC_MASK, SIM_SOPT5_UART0TXSRC(value)))
+#define SIM_BWR_SOPT5_UART0TXSRC(base, value) (SIM_WR_SOPT5_UART0TXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
+ *
+ * Selects the source for the UART 0 receive data.
+ *
+ * Values:
+ * - 0b00 - UART0_RX pin
+ * - 0b01 - CMP0
+ * - 0b10 - CMP1
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */
+#define SIM_RD_SOPT5_UART0RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART0RXSRC_MASK) >> SIM_SOPT5_UART0RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART0RXSRC(base) (SIM_RD_SOPT5_UART0RXSRC(base))
+
+/*! @brief Set the UART0RXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART0RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART0RXSRC_MASK, SIM_SOPT5_UART0RXSRC(value)))
+#define SIM_BWR_SOPT5_UART0RXSRC(base, value) (SIM_WR_SOPT5_UART0RXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
+ *
+ * Selects the source for the UART 1 transmit data.
+ *
+ * Values:
+ * - 0b00 - UART1_TX pin
+ * - 0b01 - UART1_TX pin modulated with FTM1 channel 0 output
+ * - 0b10 - UART1_TX pin modulated with FTM2 channel 0 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */
+#define SIM_RD_SOPT5_UART1TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART1TXSRC_MASK) >> SIM_SOPT5_UART1TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART1TXSRC(base) (SIM_RD_SOPT5_UART1TXSRC(base))
+
+/*! @brief Set the UART1TXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART1TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART1TXSRC_MASK, SIM_SOPT5_UART1TXSRC(value)))
+#define SIM_BWR_SOPT5_UART1TXSRC(base, value) (SIM_WR_SOPT5_UART1TXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
+ *
+ * Selects the source for the UART 1 receive data.
+ *
+ * Values:
+ * - 0b00 - UART1_RX pin
+ * - 0b01 - CMP0
+ * - 0b10 - CMP1
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */
+#define SIM_RD_SOPT5_UART1RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART1RXSRC_MASK) >> SIM_SOPT5_UART1RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART1RXSRC(base) (SIM_RD_SOPT5_UART1RXSRC(base))
+
+/*! @brief Set the UART1RXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART1RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART1RXSRC_MASK, SIM_SOPT5_UART1RXSRC(value)))
+#define SIM_BWR_SOPT5_UART1RXSRC(base, value) (SIM_WR_SOPT5_UART1RXSRC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT7 - System Options Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT7 - System Options Register 7 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT7 register
+ */
+/*@{*/
+#define SIM_RD_SOPT7(base)       (SIM_SOPT7_REG(base))
+#define SIM_WR_SOPT7(base, value) (SIM_SOPT7_REG(base) = (value))
+#define SIM_RMW_SOPT7(base, mask, value) (SIM_WR_SOPT7(base, (SIM_RD_SOPT7(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) |  (value)))
+#define SIM_CLR_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) & ~(value)))
+#define SIM_TOG_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
+ *
+ * Selects the ADC0 trigger source when alternative triggers are functional in
+ * stop and VLPS modes. .
+ *
+ * Values:
+ * - 0b0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0b0001 - High speed comparator 0 output
+ * - 0b0010 - High speed comparator 1 output
+ * - 0b0011 - High speed comparator 2 output
+ * - 0b0100 - PIT trigger 0
+ * - 0b0101 - PIT trigger 1
+ * - 0b0110 - PIT trigger 2
+ * - 0b0111 - PIT trigger 3
+ * - 0b1000 - FTM0 trigger
+ * - 0b1001 - FTM1 trigger
+ * - 0b1010 - FTM2 trigger
+ * - 0b1011 - FTM3 trigger
+ * - 0b1100 - RTC alarm
+ * - 0b1101 - RTC seconds
+ * - 0b1110 - Low-power timer (LPTMR) trigger
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */
+#define SIM_RD_SOPT7_ADC0TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0TRGSEL_MASK) >> SIM_SOPT7_ADC0TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0TRGSEL(base) (SIM_RD_SOPT7_ADC0TRGSEL(base))
+
+/*! @brief Set the ADC0TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0TRGSEL_MASK, SIM_SOPT7_ADC0TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0TRGSEL(base, value) (SIM_WR_SOPT7_ADC0TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
+ *
+ * Selects the ADC0 pre-trigger source when alternative triggers are enabled
+ * through ADC0ALTTRGEN.
+ *
+ * Values:
+ * - 0b0 - Pre-trigger A
+ * - 0b1 - Pre-trigger B
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC0PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0PRETRGSEL_MASK) >> SIM_SOPT7_ADC0PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0PRETRGSEL(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT))
+
+/*! @brief Set the ADC0PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0PRETRGSEL_MASK, SIM_SOPT7_ADC0PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0PRETRGSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
+ *
+ * Enable alternative conversion triggers for ADC0.
+ *
+ * Values:
+ * - 0b0 - PDB trigger selected for ADC0.
+ * - 0b1 - Alternate trigger selected for ADC0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC0ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0ALTTRGEN_MASK) >> SIM_SOPT7_ADC0ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC0ALTTRGEN(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT))
+
+/*! @brief Set the ADC0ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC0ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0ALTTRGEN_MASK, SIM_SOPT7_ADC0ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC0ALTTRGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
+ *
+ * Selects the ADC1 trigger source when alternative triggers are functional in
+ * stop and VLPS modes.
+ *
+ * Values:
+ * - 0b0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0b0001 - High speed comparator 0 output
+ * - 0b0010 - High speed comparator 1 output
+ * - 0b0011 - High speed comparator 2 output
+ * - 0b0100 - PIT trigger 0
+ * - 0b0101 - PIT trigger 1
+ * - 0b0110 - PIT trigger 2
+ * - 0b0111 - PIT trigger 3
+ * - 0b1000 - FTM0 trigger
+ * - 0b1001 - FTM1 trigger
+ * - 0b1010 - FTM2 trigger
+ * - 0b1011 - FTM3 trigger
+ * - 0b1100 - RTC alarm
+ * - 0b1101 - RTC seconds
+ * - 0b1110 - Low-power timer (LPTMR) trigger
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */
+#define SIM_RD_SOPT7_ADC1TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1TRGSEL_MASK) >> SIM_SOPT7_ADC1TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC1TRGSEL(base) (SIM_RD_SOPT7_ADC1TRGSEL(base))
+
+/*! @brief Set the ADC1TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC1TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1TRGSEL_MASK, SIM_SOPT7_ADC1TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC1TRGSEL(base, value) (SIM_WR_SOPT7_ADC1TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
+ *
+ * Selects the ADC1 pre-trigger source when alternative triggers are enabled
+ * through ADC1ALTTRGEN.
+ *
+ * Values:
+ * - 0b0 - Pre-trigger A selected for ADC1.
+ * - 0b1 - Pre-trigger B selected for ADC1.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC1PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1PRETRGSEL_MASK) >> SIM_SOPT7_ADC1PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC1PRETRGSEL(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1PRETRGSEL_SHIFT))
+
+/*! @brief Set the ADC1PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC1PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1PRETRGSEL_MASK, SIM_SOPT7_ADC1PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC1PRETRGSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1PRETRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
+ *
+ * Enable alternative conversion triggers for ADC1.
+ *
+ * Values:
+ * - 0b0 - PDB trigger selected for ADC1
+ * - 0b1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC1ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1ALTTRGEN_MASK) >> SIM_SOPT7_ADC1ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC1ALTTRGEN(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1ALTTRGEN_SHIFT))
+
+/*! @brief Set the ADC1ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC1ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1ALTTRGEN_MASK, SIM_SOPT7_ADC1ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC1ALTTRGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1ALTTRGEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SDID - System Device Identification Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SDID - System Device Identification Register (RO)
+ *
+ * Reset value: 0x00000380U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SDID register
+ */
+/*@{*/
+#define SIM_RD_SDID(base)        (SIM_SDID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SDID bitfields
+ */
+
+/*!
+ * @name Register SIM_SDID, field PINID[3:0] (RO)
+ *
+ * Specifies the pincount of the device.
+ *
+ * Values:
+ * - 0b0000 - Reserved
+ * - 0b0001 - Reserved
+ * - 0b0010 - 32-pin
+ * - 0b0011 - Reserved
+ * - 0b0100 - 48-pin
+ * - 0b0101 - 64-pin
+ * - 0b0110 - 80-pin
+ * - 0b0111 - 81-pin or 121-pin
+ * - 0b1000 - 100-pin
+ * - 0b1001 - 121-pin
+ * - 0b1010 - 144-pin
+ * - 0b1011 - Custom pinout (WLCSP)
+ * - 0b1100 - 169-pin
+ * - 0b1101 - Reserved
+ * - 0b1110 - 256-pin
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_PINID field. */
+#define SIM_RD_SDID_PINID(base) ((SIM_SDID_REG(base) & SIM_SDID_PINID_MASK) >> SIM_SDID_PINID_SHIFT)
+#define SIM_BRD_SDID_PINID(base) (SIM_RD_SDID_PINID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMID[6:4] (RO)
+ *
+ * This field is maintained for compatibility only, but has been superceded by
+ * the SERIESID, FAMILYID and SUBFAMID fields in this register.
+ *
+ * Values:
+ * - 0b000 - K1x Family (without tamper)
+ * - 0b001 - K2x Family (without tamper)
+ * - 0b010 - K3x Family or K1x/K6x Family (with tamper)
+ * - 0b011 - K4x Family or K2x Family (with tamper)
+ * - 0b100 - K6x Family (without tamper)
+ * - 0b101 - K7x Family
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMID field. */
+#define SIM_RD_SDID_FAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMID_MASK) >> SIM_SDID_FAMID_SHIFT)
+#define SIM_BRD_SDID_FAMID(base) (SIM_RD_SDID_FAMID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field DIEID[11:7] (RO)
+ *
+ * Specifies the silicon feature set identication number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_DIEID field. */
+#define SIM_RD_SDID_DIEID(base) ((SIM_SDID_REG(base) & SIM_SDID_DIEID_MASK) >> SIM_SDID_DIEID_SHIFT)
+#define SIM_BRD_SDID_DIEID(base) (SIM_RD_SDID_DIEID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field REVID[15:12] (RO)
+ *
+ * Specifies the silicon implementation number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_REVID field. */
+#define SIM_RD_SDID_REVID(base) ((SIM_SDID_REG(base) & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT)
+#define SIM_BRD_SDID_REVID(base) (SIM_RD_SDID_REVID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SERIESID[23:20] (RO)
+ *
+ * Specifies the Kinetis series of the device.
+ *
+ * Values:
+ * - 0b0000 - Kinetis K series
+ * - 0b0001 - Kinetis L series
+ * - 0b0101 - Kinetis W series
+ * - 0b0110 - Kinetis V series
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SERIESID field. */
+#define SIM_RD_SDID_SERIESID(base) ((SIM_SDID_REG(base) & SIM_SDID_SERIESID_MASK) >> SIM_SDID_SERIESID_SHIFT)
+#define SIM_BRD_SDID_SERIESID(base) (SIM_RD_SDID_SERIESID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
+ *
+ * Specifies the Kinetis sub-family of the device.
+ *
+ * Values:
+ * - 0b0000 - Kx0 Subfamily
+ * - 0b0001 - Kx1 Subfamily (tamper detect)
+ * - 0b0010 - Kx2 Subfamily
+ * - 0b0011 - Kx3 Subfamily (tamper detect)
+ * - 0b0100 - Kx4 Subfamily
+ * - 0b0101 - Kx5 Subfamily (tamper detect)
+ * - 0b0110 - Kx6 Subfamily
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SUBFAMID field. */
+#define SIM_RD_SDID_SUBFAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_SUBFAMID_MASK) >> SIM_SDID_SUBFAMID_SHIFT)
+#define SIM_BRD_SDID_SUBFAMID(base) (SIM_RD_SDID_SUBFAMID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
+ *
+ * Specifies the Kinetis family of the device.
+ *
+ * Values:
+ * - 0b0001 - K1x Family
+ * - 0b0010 - K2x Family
+ * - 0b0011 - K3x Family
+ * - 0b0100 - K4x Family
+ * - 0b0110 - K6x Family
+ * - 0b0111 - K7x Family
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMILYID field. */
+#define SIM_RD_SDID_FAMILYID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMILYID_MASK) >> SIM_SDID_FAMILYID_SHIFT)
+#define SIM_BRD_SDID_FAMILYID(base) (SIM_RD_SDID_FAMILYID(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC1 - System Clock Gating Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC1 register
+ */
+/*@{*/
+#define SIM_RD_SCGC1(base)       (SIM_SCGC1_REG(base))
+#define SIM_WR_SCGC1(base, value) (SIM_SCGC1_REG(base) = (value))
+#define SIM_RMW_SCGC1(base, mask, value) (SIM_WR_SCGC1(base, (SIM_RD_SCGC1(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) |  (value)))
+#define SIM_CLR_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) & ~(value)))
+#define SIM_TOG_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) ^  (value)))
+/*@}*/
+
+/* Unified clock gate bit access macros */
+#define SIM_SCGC_BIT_REG(base, index)        (*((volatile uint32_t *)&SIM_SCGC1_REG(base) + (((uint32_t)(index) >> 5) - 0U)))
+#define SIM_SCGC_BIT_SHIFT(index)            ((uint32_t)(index) & ((1U << 5) - 1U))
+#define SIM_RD_SCGC_BIT(base, index)         (SIM_SCGC_BIT_REG((base), (index)) & (1U << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BRD_SCGC_BIT(base, index)        (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_WR_SCGC_BIT(base, index, value)  (SIM_SCGC_BIT_REG((base), (index)) = (SIM_SCGC_BIT_REG((base), (index)) & ~(1U << SIM_SCGC_BIT_SHIFT(index))) | ((uint32_t)(value) << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BWR_SCGC_BIT(base, index, value) (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)) = (uint32_t)(value))
+
+/*
+ * Constants & macros for individual SIM_SCGC1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC1, field I2C2[6] (RW)
+ *
+ * This bit controls the clock gate to the I2C2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_I2C2 field. */
+#define SIM_RD_SCGC1_I2C2(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_I2C2_MASK) >> SIM_SCGC1_I2C2_SHIFT)
+#define SIM_BRD_SCGC1_I2C2(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_I2C2_SHIFT))
+
+/*! @brief Set the I2C2 field to a new value. */
+#define SIM_WR_SCGC1_I2C2(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_I2C2_MASK, SIM_SCGC1_I2C2(value)))
+#define SIM_BWR_SCGC1_I2C2(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_I2C2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC1, field UART4[10] (RW)
+ *
+ * This bit controls the clock gate to the UART4 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_UART4 field. */
+#define SIM_RD_SCGC1_UART4(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_UART4_MASK) >> SIM_SCGC1_UART4_SHIFT)
+#define SIM_BRD_SCGC1_UART4(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART4_SHIFT))
+
+/*! @brief Set the UART4 field to a new value. */
+#define SIM_WR_SCGC1_UART4(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_UART4_MASK, SIM_SCGC1_UART4(value)))
+#define SIM_BWR_SCGC1_UART4(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC1, field UART5[11] (RW)
+ *
+ * This bit controls the clock gate to the UART5 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_UART5 field. */
+#define SIM_RD_SCGC1_UART5(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_UART5_MASK) >> SIM_SCGC1_UART5_SHIFT)
+#define SIM_BRD_SCGC1_UART5(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART5_SHIFT))
+
+/*! @brief Set the UART5 field to a new value. */
+#define SIM_WR_SCGC1_UART5(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_UART5_MASK, SIM_SCGC1_UART5(value)))
+#define SIM_BWR_SCGC1_UART5(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART5_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC2 - System Clock Gating Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
+ * AIPS1, define the clock gate control bits in the SCGC2. When accessing through
+ * AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC2 register
+ */
+/*@{*/
+#define SIM_RD_SCGC2(base)       (SIM_SCGC2_REG(base))
+#define SIM_WR_SCGC2(base, value) (SIM_SCGC2_REG(base) = (value))
+#define SIM_RMW_SCGC2(base, mask, value) (SIM_WR_SCGC2(base, (SIM_RD_SCGC2(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) |  (value)))
+#define SIM_CLR_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) & ~(value)))
+#define SIM_TOG_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC2, field ENET[0] (RW)
+ *
+ * This bit controls the clock gate to the ENET module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_ENET field. */
+#define SIM_RD_SCGC2_ENET(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_ENET_MASK) >> SIM_SCGC2_ENET_SHIFT)
+#define SIM_BRD_SCGC2_ENET(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_ENET_SHIFT))
+
+/*! @brief Set the ENET field to a new value. */
+#define SIM_WR_SCGC2_ENET(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_ENET_MASK, SIM_SCGC2_ENET(value)))
+#define SIM_BWR_SCGC2_ENET(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_ENET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC2, field DAC0[12] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_DAC0 field. */
+#define SIM_RD_SCGC2_DAC0(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_DAC0_MASK) >> SIM_SCGC2_DAC0_SHIFT)
+#define SIM_BRD_SCGC2_DAC0(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC0_SHIFT))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC2_DAC0(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_DAC0_MASK, SIM_SCGC2_DAC0(value)))
+#define SIM_BWR_SCGC2_DAC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC2, field DAC1[13] (RW)
+ *
+ * This bit controls the clock gate to the DAC1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_DAC1 field. */
+#define SIM_RD_SCGC2_DAC1(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_DAC1_MASK) >> SIM_SCGC2_DAC1_SHIFT)
+#define SIM_BRD_SCGC2_DAC1(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC1_SHIFT))
+
+/*! @brief Set the DAC1 field to a new value. */
+#define SIM_WR_SCGC2_DAC1(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_DAC1_MASK, SIM_SCGC2_DAC1(value)))
+#define SIM_BWR_SCGC2_DAC1(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC3 - System Clock Gating Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
+ * through AIPS1, define the clock gate control bits in the SCGC3. When accessing
+ * through AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC3 register
+ */
+/*@{*/
+#define SIM_RD_SCGC3(base)       (SIM_SCGC3_REG(base))
+#define SIM_WR_SCGC3(base, value) (SIM_SCGC3_REG(base) = (value))
+#define SIM_RMW_SCGC3(base, mask, value) (SIM_WR_SCGC3(base, (SIM_RD_SCGC3(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) |  (value)))
+#define SIM_CLR_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) & ~(value)))
+#define SIM_TOG_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC3 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC3, field RNGA[0] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_RNGA field. */
+#define SIM_RD_SCGC3_RNGA(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_RNGA_MASK) >> SIM_SCGC3_RNGA_SHIFT)
+#define SIM_BRD_SCGC3_RNGA(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_RNGA_SHIFT))
+
+/*! @brief Set the RNGA field to a new value. */
+#define SIM_WR_SCGC3_RNGA(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_RNGA_MASK, SIM_SCGC3_RNGA(value)))
+#define SIM_BWR_SCGC3_RNGA(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_RNGA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field SPI2[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_SPI2 field. */
+#define SIM_RD_SCGC3_SPI2(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_SPI2_MASK) >> SIM_SCGC3_SPI2_SHIFT)
+#define SIM_BRD_SCGC3_SPI2(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SPI2_SHIFT))
+
+/*! @brief Set the SPI2 field to a new value. */
+#define SIM_WR_SCGC3_SPI2(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_SPI2_MASK, SIM_SCGC3_SPI2(value)))
+#define SIM_BWR_SCGC3_SPI2(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SPI2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field SDHC[17] (RW)
+ *
+ * This bit controls the clock gate to the SDHC module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_SDHC field. */
+#define SIM_RD_SCGC3_SDHC(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_SDHC_MASK) >> SIM_SCGC3_SDHC_SHIFT)
+#define SIM_BRD_SCGC3_SDHC(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SDHC_SHIFT))
+
+/*! @brief Set the SDHC field to a new value. */
+#define SIM_WR_SCGC3_SDHC(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_SDHC_MASK, SIM_SCGC3_SDHC(value)))
+#define SIM_BWR_SCGC3_SDHC(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SDHC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field FTM2[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_FTM2 field. */
+#define SIM_RD_SCGC3_FTM2(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_FTM2_MASK) >> SIM_SCGC3_FTM2_SHIFT)
+#define SIM_BRD_SCGC3_FTM2(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM2_SHIFT))
+
+/*! @brief Set the FTM2 field to a new value. */
+#define SIM_WR_SCGC3_FTM2(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_FTM2_MASK, SIM_SCGC3_FTM2(value)))
+#define SIM_BWR_SCGC3_FTM2(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field FTM3[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM3 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_FTM3 field. */
+#define SIM_RD_SCGC3_FTM3(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_FTM3_MASK) >> SIM_SCGC3_FTM3_SHIFT)
+#define SIM_BRD_SCGC3_FTM3(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM3_SHIFT))
+
+/*! @brief Set the FTM3 field to a new value. */
+#define SIM_WR_SCGC3_FTM3(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_FTM3_MASK, SIM_SCGC3_FTM3(value)))
+#define SIM_BWR_SCGC3_FTM3(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field ADC1[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_ADC1 field. */
+#define SIM_RD_SCGC3_ADC1(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_ADC1_MASK) >> SIM_SCGC3_ADC1_SHIFT)
+#define SIM_BRD_SCGC3_ADC1(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_ADC1_SHIFT))
+
+/*! @brief Set the ADC1 field to a new value. */
+#define SIM_WR_SCGC3_ADC1(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_ADC1_MASK, SIM_SCGC3_ADC1(value)))
+#define SIM_BWR_SCGC3_ADC1(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_ADC1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC4 - System Clock Gating Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
+ *
+ * Reset value: 0xF0100030U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC4 register
+ */
+/*@{*/
+#define SIM_RD_SCGC4(base)       (SIM_SCGC4_REG(base))
+#define SIM_WR_SCGC4(base, value) (SIM_SCGC4_REG(base) = (value))
+#define SIM_RMW_SCGC4(base, mask, value) (SIM_WR_SCGC4(base, (SIM_RD_SCGC4(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) |  (value)))
+#define SIM_CLR_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) & ~(value)))
+#define SIM_TOG_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC4, field EWM[1] (RW)
+ *
+ * This bit controls the clock gate to the EWM module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_EWM field. */
+#define SIM_RD_SCGC4_EWM(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_EWM_MASK) >> SIM_SCGC4_EWM_SHIFT)
+#define SIM_BRD_SCGC4_EWM(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_EWM_SHIFT))
+
+/*! @brief Set the EWM field to a new value. */
+#define SIM_WR_SCGC4_EWM(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_EWM_MASK, SIM_SCGC4_EWM(value)))
+#define SIM_BWR_SCGC4_EWM(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_EWM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMT[2] (RW)
+ *
+ * This bit controls the clock gate to the CMT module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMT field. */
+#define SIM_RD_SCGC4_CMT(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMT_MASK) >> SIM_SCGC4_CMT_SHIFT)
+#define SIM_BRD_SCGC4_CMT(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT))
+
+/*! @brief Set the CMT field to a new value. */
+#define SIM_WR_SCGC4_CMT(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMT_MASK, SIM_SCGC4_CMT(value)))
+#define SIM_BWR_SCGC4_CMT(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C0[6] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C0 field. */
+#define SIM_RD_SCGC4_I2C0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C0_MASK) >> SIM_SCGC4_I2C0_SHIFT)
+#define SIM_BRD_SCGC4_I2C0(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT))
+
+/*! @brief Set the I2C0 field to a new value. */
+#define SIM_WR_SCGC4_I2C0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C0_MASK, SIM_SCGC4_I2C0(value)))
+#define SIM_BWR_SCGC4_I2C0(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C1[7] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C1 field. */
+#define SIM_RD_SCGC4_I2C1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C1_MASK) >> SIM_SCGC4_I2C1_SHIFT)
+#define SIM_BRD_SCGC4_I2C1(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT))
+
+/*! @brief Set the I2C1 field to a new value. */
+#define SIM_WR_SCGC4_I2C1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C1_MASK, SIM_SCGC4_I2C1(value)))
+#define SIM_BWR_SCGC4_I2C1(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART0[10] (RW)
+ *
+ * This bit controls the clock gate to the UART0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART0 field. */
+#define SIM_RD_SCGC4_UART0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT)
+#define SIM_BRD_SCGC4_UART0(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART0_SHIFT))
+
+/*! @brief Set the UART0 field to a new value. */
+#define SIM_WR_SCGC4_UART0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART0_MASK, SIM_SCGC4_UART0(value)))
+#define SIM_BWR_SCGC4_UART0(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART1[11] (RW)
+ *
+ * This bit controls the clock gate to the UART1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART1 field. */
+#define SIM_RD_SCGC4_UART1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT)
+#define SIM_BRD_SCGC4_UART1(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART1_SHIFT))
+
+/*! @brief Set the UART1 field to a new value. */
+#define SIM_WR_SCGC4_UART1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART1_MASK, SIM_SCGC4_UART1(value)))
+#define SIM_BWR_SCGC4_UART1(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART2[12] (RW)
+ *
+ * This bit controls the clock gate to the UART2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART2 field. */
+#define SIM_RD_SCGC4_UART2(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT)
+#define SIM_BRD_SCGC4_UART2(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT))
+
+/*! @brief Set the UART2 field to a new value. */
+#define SIM_WR_SCGC4_UART2(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART2_MASK, SIM_SCGC4_UART2(value)))
+#define SIM_BWR_SCGC4_UART2(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART3[13] (RW)
+ *
+ * This bit controls the clock gate to the UART3 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART3 field. */
+#define SIM_RD_SCGC4_UART3(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART3_MASK) >> SIM_SCGC4_UART3_SHIFT)
+#define SIM_BRD_SCGC4_UART3(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART3_SHIFT))
+
+/*! @brief Set the UART3 field to a new value. */
+#define SIM_WR_SCGC4_UART3(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART3_MASK, SIM_SCGC4_UART3(value)))
+#define SIM_BWR_SCGC4_UART3(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field USBOTG[18] (RW)
+ *
+ * This bit controls the clock gate to the USB module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_USBOTG field. */
+#define SIM_RD_SCGC4_USBOTG(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_USBOTG_MASK) >> SIM_SCGC4_USBOTG_SHIFT)
+#define SIM_BRD_SCGC4_USBOTG(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBOTG_SHIFT))
+
+/*! @brief Set the USBOTG field to a new value. */
+#define SIM_WR_SCGC4_USBOTG(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_USBOTG_MASK, SIM_SCGC4_USBOTG(value)))
+#define SIM_BWR_SCGC4_USBOTG(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBOTG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMP[19] (RW)
+ *
+ * This bit controls the clock gate to the comparator module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMP field. */
+#define SIM_RD_SCGC4_CMP(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMP_MASK) >> SIM_SCGC4_CMP_SHIFT)
+#define SIM_BRD_SCGC4_CMP(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT))
+
+/*! @brief Set the CMP field to a new value. */
+#define SIM_WR_SCGC4_CMP(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMP_MASK, SIM_SCGC4_CMP(value)))
+#define SIM_BWR_SCGC4_CMP(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field VREF[20] (RW)
+ *
+ * This bit controls the clock gate to the VREF module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_VREF field. */
+#define SIM_RD_SCGC4_VREF(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_VREF_MASK) >> SIM_SCGC4_VREF_SHIFT)
+#define SIM_BRD_SCGC4_VREF(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT))
+
+/*! @brief Set the VREF field to a new value. */
+#define SIM_WR_SCGC4_VREF(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_VREF_MASK, SIM_SCGC4_VREF(value)))
+#define SIM_BWR_SCGC4_VREF(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC5 - System Clock Gating Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
+ *
+ * Reset value: 0x00040182U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC5 register
+ */
+/*@{*/
+#define SIM_RD_SCGC5(base)       (SIM_SCGC5_REG(base))
+#define SIM_WR_SCGC5(base, value) (SIM_SCGC5_REG(base) = (value))
+#define SIM_RMW_SCGC5(base, mask, value) (SIM_WR_SCGC5(base, (SIM_RD_SCGC5(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) |  (value)))
+#define SIM_CLR_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) & ~(value)))
+#define SIM_TOG_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC5, field LPTMR[0] (RW)
+ *
+ * This bit controls software access to the Low Power Timer module.
+ *
+ * Values:
+ * - 0b0 - Access disabled
+ * - 0b1 - Access enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_LPTMR field. */
+#define SIM_RD_SCGC5_LPTMR(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPTMR_MASK) >> SIM_SCGC5_LPTMR_SHIFT)
+#define SIM_BRD_SCGC5_LPTMR(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT))
+
+/*! @brief Set the LPTMR field to a new value. */
+#define SIM_WR_SCGC5_LPTMR(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPTMR_MASK, SIM_SCGC5_LPTMR(value)))
+#define SIM_BWR_SCGC5_LPTMR(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTA[9] (RW)
+ *
+ * This bit controls the clock gate to the Port A module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTA field. */
+#define SIM_RD_SCGC5_PORTA(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTA_MASK) >> SIM_SCGC5_PORTA_SHIFT)
+#define SIM_BRD_SCGC5_PORTA(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT))
+
+/*! @brief Set the PORTA field to a new value. */
+#define SIM_WR_SCGC5_PORTA(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTA_MASK, SIM_SCGC5_PORTA(value)))
+#define SIM_BWR_SCGC5_PORTA(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTB[10] (RW)
+ *
+ * This bit controls the clock gate to the Port B module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTB field. */
+#define SIM_RD_SCGC5_PORTB(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTB_MASK) >> SIM_SCGC5_PORTB_SHIFT)
+#define SIM_BRD_SCGC5_PORTB(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT))
+
+/*! @brief Set the PORTB field to a new value. */
+#define SIM_WR_SCGC5_PORTB(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTB_MASK, SIM_SCGC5_PORTB(value)))
+#define SIM_BWR_SCGC5_PORTB(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTC[11] (RW)
+ *
+ * This bit controls the clock gate to the Port C module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTC field. */
+#define SIM_RD_SCGC5_PORTC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTC_MASK) >> SIM_SCGC5_PORTC_SHIFT)
+#define SIM_BRD_SCGC5_PORTC(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT))
+
+/*! @brief Set the PORTC field to a new value. */
+#define SIM_WR_SCGC5_PORTC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTC_MASK, SIM_SCGC5_PORTC(value)))
+#define SIM_BWR_SCGC5_PORTC(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTD[12] (RW)
+ *
+ * This bit controls the clock gate to the Port D module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTD field. */
+#define SIM_RD_SCGC5_PORTD(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTD_MASK) >> SIM_SCGC5_PORTD_SHIFT)
+#define SIM_BRD_SCGC5_PORTD(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT))
+
+/*! @brief Set the PORTD field to a new value. */
+#define SIM_WR_SCGC5_PORTD(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTD_MASK, SIM_SCGC5_PORTD(value)))
+#define SIM_BWR_SCGC5_PORTD(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTE[13] (RW)
+ *
+ * This bit controls the clock gate to the Port E module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTE field. */
+#define SIM_RD_SCGC5_PORTE(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTE_MASK) >> SIM_SCGC5_PORTE_SHIFT)
+#define SIM_BRD_SCGC5_PORTE(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT))
+
+/*! @brief Set the PORTE field to a new value. */
+#define SIM_WR_SCGC5_PORTE(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTE_MASK, SIM_SCGC5_PORTE(value)))
+#define SIM_BWR_SCGC5_PORTE(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC6 - System Clock Gating Control Register 6
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
+ *
+ * Reset value: 0x40000001U
+ *
+ * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
+ * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
+ * When accessing through AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC6 register
+ */
+/*@{*/
+#define SIM_RD_SCGC6(base)       (SIM_SCGC6_REG(base))
+#define SIM_WR_SCGC6(base, value) (SIM_SCGC6_REG(base) = (value))
+#define SIM_RMW_SCGC6(base, mask, value) (SIM_WR_SCGC6(base, (SIM_RD_SCGC6(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) |  (value)))
+#define SIM_CLR_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) & ~(value)))
+#define SIM_TOG_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC6 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC6, field FTF[0] (RW)
+ *
+ * This bit controls the clock gate to the flash memory. Flash reads are still
+ * supported while the flash memory is clock gated, but entry into low power modes
+ * is blocked.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTF field. */
+#define SIM_RD_SCGC6_FTF(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTF_MASK) >> SIM_SCGC6_FTF_SHIFT)
+#define SIM_BRD_SCGC6_FTF(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT))
+
+/*! @brief Set the FTF field to a new value. */
+#define SIM_WR_SCGC6_FTF(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTF_MASK, SIM_SCGC6_FTF(value)))
+#define SIM_BWR_SCGC6_FTF(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA Mux module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */
+#define SIM_RD_SCGC6_DMAMUX(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DMAMUX_MASK) >> SIM_SCGC6_DMAMUX_SHIFT)
+#define SIM_BRD_SCGC6_DMAMUX(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT))
+
+/*! @brief Set the DMAMUX field to a new value. */
+#define SIM_WR_SCGC6_DMAMUX(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DMAMUX_MASK, SIM_SCGC6_DMAMUX(value)))
+#define SIM_BWR_SCGC6_DMAMUX(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
+ *
+ * This bit controls the clock gate to the FlexCAN0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. */
+#define SIM_RD_SCGC6_FLEXCAN0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FLEXCAN0_MASK) >> SIM_SCGC6_FLEXCAN0_SHIFT)
+#define SIM_BRD_SCGC6_FLEXCAN0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FLEXCAN0_SHIFT))
+
+/*! @brief Set the FLEXCAN0 field to a new value. */
+#define SIM_WR_SCGC6_FLEXCAN0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FLEXCAN0_MASK, SIM_SCGC6_FLEXCAN0(value)))
+#define SIM_BWR_SCGC6_FLEXCAN0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FLEXCAN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RNGA[9] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RNGA field. */
+#define SIM_RD_SCGC6_RNGA(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RNGA_MASK) >> SIM_SCGC6_RNGA_SHIFT)
+#define SIM_BRD_SCGC6_RNGA(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RNGA_SHIFT))
+
+/*! @brief Set the RNGA field to a new value. */
+#define SIM_WR_SCGC6_RNGA(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RNGA_MASK, SIM_SCGC6_RNGA(value)))
+#define SIM_BWR_SCGC6_RNGA(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RNGA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field SPI0[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_SPI0 field. */
+#define SIM_RD_SCGC6_SPI0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI0_MASK) >> SIM_SCGC6_SPI0_SHIFT)
+#define SIM_BRD_SCGC6_SPI0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT))
+
+/*! @brief Set the SPI0 field to a new value. */
+#define SIM_WR_SCGC6_SPI0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI0_MASK, SIM_SCGC6_SPI0(value)))
+#define SIM_BWR_SCGC6_SPI0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field SPI1[13] (RW)
+ *
+ * This bit controls the clock gate to the SPI1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_SPI1 field. */
+#define SIM_RD_SCGC6_SPI1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI1_MASK) >> SIM_SCGC6_SPI1_SHIFT)
+#define SIM_BRD_SCGC6_SPI1(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT))
+
+/*! @brief Set the SPI1 field to a new value. */
+#define SIM_WR_SCGC6_SPI1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI1_MASK, SIM_SCGC6_SPI1(value)))
+#define SIM_BWR_SCGC6_SPI1(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field I2S[15] (RW)
+ *
+ * This bit controls the clock gate to the I 2 S module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_I2S field. */
+#define SIM_RD_SCGC6_I2S(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_I2S_MASK) >> SIM_SCGC6_I2S_SHIFT)
+#define SIM_BRD_SCGC6_I2S(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT))
+
+/*! @brief Set the I2S field to a new value. */
+#define SIM_WR_SCGC6_I2S(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_I2S_MASK, SIM_SCGC6_I2S(value)))
+#define SIM_BWR_SCGC6_I2S(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field CRC[18] (RW)
+ *
+ * This bit controls the clock gate to the CRC module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_CRC field. */
+#define SIM_RD_SCGC6_CRC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_CRC_MASK) >> SIM_SCGC6_CRC_SHIFT)
+#define SIM_BRD_SCGC6_CRC(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_CRC_SHIFT))
+
+/*! @brief Set the CRC field to a new value. */
+#define SIM_WR_SCGC6_CRC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_CRC_MASK, SIM_SCGC6_CRC(value)))
+#define SIM_BWR_SCGC6_CRC(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_CRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field USBDCD[21] (RW)
+ *
+ * This bit controls the clock gate to the USB DCD module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_USBDCD field. */
+#define SIM_RD_SCGC6_USBDCD(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_USBDCD_MASK) >> SIM_SCGC6_USBDCD_SHIFT)
+#define SIM_BRD_SCGC6_USBDCD(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_USBDCD_SHIFT))
+
+/*! @brief Set the USBDCD field to a new value. */
+#define SIM_WR_SCGC6_USBDCD(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_USBDCD_MASK, SIM_SCGC6_USBDCD(value)))
+#define SIM_BWR_SCGC6_USBDCD(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_USBDCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PDB[22] (RW)
+ *
+ * This bit controls the clock gate to the PDB module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PDB field. */
+#define SIM_RD_SCGC6_PDB(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PDB_MASK) >> SIM_SCGC6_PDB_SHIFT)
+#define SIM_BRD_SCGC6_PDB(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PDB_SHIFT))
+
+/*! @brief Set the PDB field to a new value. */
+#define SIM_WR_SCGC6_PDB(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PDB_MASK, SIM_SCGC6_PDB(value)))
+#define SIM_BWR_SCGC6_PDB(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PDB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PIT[23] (RW)
+ *
+ * This bit controls the clock gate to the PIT module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PIT field. */
+#define SIM_RD_SCGC6_PIT(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PIT_MASK) >> SIM_SCGC6_PIT_SHIFT)
+#define SIM_BRD_SCGC6_PIT(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT))
+
+/*! @brief Set the PIT field to a new value. */
+#define SIM_WR_SCGC6_PIT(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PIT_MASK, SIM_SCGC6_PIT(value)))
+#define SIM_BWR_SCGC6_PIT(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM0[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM0 field. */
+#define SIM_RD_SCGC6_FTM0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM0_MASK) >> SIM_SCGC6_FTM0_SHIFT)
+#define SIM_BRD_SCGC6_FTM0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM0_SHIFT))
+
+/*! @brief Set the FTM0 field to a new value. */
+#define SIM_WR_SCGC6_FTM0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM0_MASK, SIM_SCGC6_FTM0(value)))
+#define SIM_BWR_SCGC6_FTM0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM1[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM1 field. */
+#define SIM_RD_SCGC6_FTM1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM1_MASK) >> SIM_SCGC6_FTM1_SHIFT)
+#define SIM_BRD_SCGC6_FTM1(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM1_SHIFT))
+
+/*! @brief Set the FTM1 field to a new value. */
+#define SIM_WR_SCGC6_FTM1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM1_MASK, SIM_SCGC6_FTM1(value)))
+#define SIM_BWR_SCGC6_FTM1(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM2[26] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM2 field. */
+#define SIM_RD_SCGC6_FTM2(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM2_MASK) >> SIM_SCGC6_FTM2_SHIFT)
+#define SIM_BRD_SCGC6_FTM2(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM2_SHIFT))
+
+/*! @brief Set the FTM2 field to a new value. */
+#define SIM_WR_SCGC6_FTM2(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM2_MASK, SIM_SCGC6_FTM2(value)))
+#define SIM_BWR_SCGC6_FTM2(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field ADC0[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_ADC0 field. */
+#define SIM_RD_SCGC6_ADC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_ADC0_MASK) >> SIM_SCGC6_ADC0_SHIFT)
+#define SIM_BRD_SCGC6_ADC0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT))
+
+/*! @brief Set the ADC0 field to a new value. */
+#define SIM_WR_SCGC6_ADC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_ADC0_MASK, SIM_SCGC6_ADC0(value)))
+#define SIM_BWR_SCGC6_ADC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RTC[29] (RW)
+ *
+ * This bit controls software access and interrupts to the RTC module.
+ *
+ * Values:
+ * - 0b0 - Access and interrupts disabled
+ * - 0b1 - Access and interrupts enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RTC field. */
+#define SIM_RD_SCGC6_RTC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RTC_MASK) >> SIM_SCGC6_RTC_SHIFT)
+#define SIM_BRD_SCGC6_RTC(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT))
+
+/*! @brief Set the RTC field to a new value. */
+#define SIM_WR_SCGC6_RTC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RTC_MASK, SIM_SCGC6_RTC(value)))
+#define SIM_BWR_SCGC6_RTC(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DAC0[31] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DAC0 field. */
+#define SIM_RD_SCGC6_DAC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DAC0_MASK) >> SIM_SCGC6_DAC0_SHIFT)
+#define SIM_BRD_SCGC6_DAC0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC6_DAC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DAC0_MASK, SIM_SCGC6_DAC0(value)))
+#define SIM_BWR_SCGC6_DAC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC7 - System Clock Gating Control Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
+ *
+ * Reset value: 0x00000006U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC7 register
+ */
+/*@{*/
+#define SIM_RD_SCGC7(base)       (SIM_SCGC7_REG(base))
+#define SIM_WR_SCGC7(base, value) (SIM_SCGC7_REG(base) = (value))
+#define SIM_RMW_SCGC7(base, mask, value) (SIM_WR_SCGC7(base, (SIM_RD_SCGC7(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) |  (value)))
+#define SIM_CLR_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) & ~(value)))
+#define SIM_TOG_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
+ *
+ * This bit controls the clock gate to the FlexBus module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */
+#define SIM_RD_SCGC7_FLEXBUS(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_FLEXBUS_MASK) >> SIM_SCGC7_FLEXBUS_SHIFT)
+#define SIM_BRD_SCGC7_FLEXBUS(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_FLEXBUS_SHIFT))
+
+/*! @brief Set the FLEXBUS field to a new value. */
+#define SIM_WR_SCGC7_FLEXBUS(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_FLEXBUS_MASK, SIM_SCGC7_FLEXBUS(value)))
+#define SIM_BWR_SCGC7_FLEXBUS(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_FLEXBUS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC7, field DMA[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_DMA field. */
+#define SIM_RD_SCGC7_DMA(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_DMA_MASK) >> SIM_SCGC7_DMA_SHIFT)
+#define SIM_BRD_SCGC7_DMA(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define SIM_WR_SCGC7_DMA(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_DMA_MASK, SIM_SCGC7_DMA(value)))
+#define SIM_BWR_SCGC7_DMA(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC7, field MPU[2] (RW)
+ *
+ * This bit controls the clock gate to the MPU module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_MPU field. */
+#define SIM_RD_SCGC7_MPU(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_MPU_MASK) >> SIM_SCGC7_MPU_SHIFT)
+#define SIM_BRD_SCGC7_MPU(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_MPU_SHIFT))
+
+/*! @brief Set the MPU field to a new value. */
+#define SIM_WR_SCGC7_MPU(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_MPU_MASK, SIM_SCGC7_MPU(value)))
+#define SIM_BWR_SCGC7_MPU(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_MPU_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV1 - System Clock Divider Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * When updating CLKDIV1, update all fields using the one write command.
+ * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
+ * write to be ignored. The maximum divide ratio that can be programmed between
+ * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
+ * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
+ * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
+ * mode.
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV1 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV1(base)     (SIM_CLKDIV1_REG(base))
+#define SIM_WR_CLKDIV1(base, value) (SIM_CLKDIV1_REG(base) = (value))
+#define SIM_RMW_CLKDIV1(base, mask, value) (SIM_WR_CLKDIV1(base, (SIM_RD_CLKDIV1(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) |  (value)))
+#define SIM_CLR_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) & ~(value)))
+#define SIM_TOG_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV1 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
+ *
+ * This field sets the divide value for the flash clock from MCGOUTCLK. At the
+ * end of reset, it is loaded with either 0001 or 1111 depending on
+ * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
+ * frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */
+#define SIM_RD_CLKDIV1_OUTDIV4(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV4(base) (SIM_RD_CLKDIV1_OUTDIV4(base))
+
+/*! @brief Set the OUTDIV4 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV4(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV4_MASK, SIM_CLKDIV1_OUTDIV4(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV4(base, value) (SIM_WR_CLKDIV1_OUTDIV4(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
+ *
+ * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
+ * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
+ * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
+ * divide of the system clock frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */
+#define SIM_RD_CLKDIV1_OUTDIV3(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV3(base) (SIM_RD_CLKDIV1_OUTDIV3(base))
+
+/*! @brief Set the OUTDIV3 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV3(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV3_MASK, SIM_CLKDIV1_OUTDIV3(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV3(base, value) (SIM_WR_CLKDIV1_OUTDIV3(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
+ *
+ * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
+ * of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
+ * frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */
+#define SIM_RD_CLKDIV1_OUTDIV2(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV2(base) (SIM_RD_CLKDIV1_OUTDIV2(base))
+
+/*! @brief Set the OUTDIV2 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV2(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV2_MASK, SIM_CLKDIV1_OUTDIV2(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV2(base, value) (SIM_WR_CLKDIV1_OUTDIV2(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
+ *
+ * This field sets the divide value for the core/system clock from MCGOUTCLK. At
+ * the end of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT].
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */
+#define SIM_RD_CLKDIV1_OUTDIV1(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV1(base) (SIM_RD_CLKDIV1_OUTDIV1(base))
+
+/*! @brief Set the OUTDIV1 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV1(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV1_MASK, SIM_CLKDIV1_OUTDIV1(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV1(base, value) (SIM_WR_CLKDIV1_OUTDIV1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV2 - System Clock Divider Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV2 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV2(base)     (SIM_CLKDIV2_REG(base))
+#define SIM_WR_CLKDIV2(base, value) (SIM_CLKDIV2_REG(base) = (value))
+#define SIM_RMW_CLKDIV2(base, mask, value) (SIM_WR_CLKDIV2(base, (SIM_RD_CLKDIV2(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) |  (value)))
+#define SIM_CLR_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) & ~(value)))
+#define SIM_TOG_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV2 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
+ *
+ * This field sets the fraction multiply value for the fractional clock divider
+ * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
+ * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. */
+#define SIM_RD_CLKDIV2_USBFRAC(base) ((SIM_CLKDIV2_REG(base) & SIM_CLKDIV2_USBFRAC_MASK) >> SIM_CLKDIV2_USBFRAC_SHIFT)
+#define SIM_BRD_CLKDIV2_USBFRAC(base) (BITBAND_ACCESS32(&SIM_CLKDIV2_REG(base), SIM_CLKDIV2_USBFRAC_SHIFT))
+
+/*! @brief Set the USBFRAC field to a new value. */
+#define SIM_WR_CLKDIV2_USBFRAC(base, value) (SIM_RMW_CLKDIV2(base, SIM_CLKDIV2_USBFRAC_MASK, SIM_CLKDIV2_USBFRAC(value)))
+#define SIM_BWR_CLKDIV2_USBFRAC(base, value) (BITBAND_ACCESS32(&SIM_CLKDIV2_REG(base), SIM_CLKDIV2_USBFRAC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
+ *
+ * This field sets the divide value for the fractional clock divider when the
+ * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
+ * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV2_USBDIV field. */
+#define SIM_RD_CLKDIV2_USBDIV(base) ((SIM_CLKDIV2_REG(base) & SIM_CLKDIV2_USBDIV_MASK) >> SIM_CLKDIV2_USBDIV_SHIFT)
+#define SIM_BRD_CLKDIV2_USBDIV(base) (SIM_RD_CLKDIV2_USBDIV(base))
+
+/*! @brief Set the USBDIV field to a new value. */
+#define SIM_WR_CLKDIV2_USBDIV(base, value) (SIM_RMW_CLKDIV2(base, SIM_CLKDIV2_USBDIV_MASK, SIM_CLKDIV2_USBDIV(value)))
+#define SIM_BWR_CLKDIV2_USBDIV(base, value) (SIM_WR_CLKDIV2_USBDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG1 - Flash Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG1 - Flash Configuration Register 1 (RW)
+ *
+ * Reset value: 0xFF0F0F00U
+ *
+ * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
+ * user programming in user IFR via the PGMPART flash command. For devices with
+ * program flash only:
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG1 register
+ */
+/*@{*/
+#define SIM_RD_FCFG1(base)       (SIM_FCFG1_REG(base))
+#define SIM_WR_FCFG1(base, value) (SIM_FCFG1_REG(base) = (value))
+#define SIM_RMW_FCFG1(base, mask, value) (SIM_WR_FCFG1(base, (SIM_RD_FCFG1(base) & ~(mask)) | (value)))
+#define SIM_SET_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) |  (value)))
+#define SIM_CLR_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) & ~(value)))
+#define SIM_TOG_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG1 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
+ *
+ * Flash accesses are disabled (and generate a bus error) and the Flash memory
+ * is placed in a low power state. This bit should not be changed during VLP
+ * modes. Relocate the interrupt vectors out of Flash memory before disabling the
+ * Flash.
+ *
+ * Values:
+ * - 0b0 - Flash is enabled
+ * - 0b1 - Flash is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */
+#define SIM_RD_FCFG1_FLASHDIS(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDIS_MASK) >> SIM_FCFG1_FLASHDIS_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDIS(base) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT))
+
+/*! @brief Set the FLASHDIS field to a new value. */
+#define SIM_WR_FCFG1_FLASHDIS(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDIS_MASK, SIM_FCFG1_FLASHDIS(value)))
+#define SIM_BWR_FCFG1_FLASHDIS(base, value) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
+ *
+ * When set, Flash memory is disabled for the duration of Wait mode. An attempt
+ * by the DMA or other bus master to access the Flash when the Flash is disabled
+ * will result in a bus error. This bit should be clear during VLP modes. The
+ * Flash will be automatically enabled again at the end of Wait mode so interrupt
+ * vectors do not need to be relocated out of Flash memory. The wakeup time from
+ * Wait mode is extended when this bit is set.
+ *
+ * Values:
+ * - 0b0 - Flash remains enabled during Wait mode
+ * - 0b1 - Flash is disabled for the duration of Wait mode
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */
+#define SIM_RD_FCFG1_FLASHDOZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDOZE_MASK) >> SIM_FCFG1_FLASHDOZE_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDOZE(base) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT))
+
+/*! @brief Set the FLASHDOZE field to a new value. */
+#define SIM_WR_FCFG1_FLASHDOZE(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDOZE_MASK, SIM_FCFG1_FLASHDOZE(value)))
+#define SIM_BWR_FCFG1_FLASHDOZE(base, value) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
+ *
+ * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
+ * description in FTFE chapter. For devices without FlexNVM: Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_DEPART field. */
+#define SIM_RD_FCFG1_DEPART(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT)
+#define SIM_BRD_FCFG1_DEPART(base) (SIM_RD_FCFG1_DEPART(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
+ *
+ * EEPROM data size .
+ *
+ * Values:
+ * - 0b0000 - 16 KB
+ * - 0b0001 - 8 KB
+ * - 0b0010 - 4 KB
+ * - 0b0011 - 2 KB
+ * - 0b0100 - 1 KB
+ * - 0b0101 - 512 Bytes
+ * - 0b0110 - 256 Bytes
+ * - 0b0111 - 128 Bytes
+ * - 0b1000 - 64 Bytes
+ * - 0b1001 - 32 Bytes
+ * - 0b1111 - 0 Bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_EESIZE field. */
+#define SIM_RD_FCFG1_EESIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_EESIZE_MASK) >> SIM_FCFG1_EESIZE_SHIFT)
+#define SIM_BRD_FCFG1_EESIZE(base) (SIM_RD_FCFG1_EESIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
+ *
+ * This field specifies the amount of program flash memory available on the
+ * device . Undefined values are reserved.
+ *
+ * Values:
+ * - 0b0011 - 32 KB of program flash memory
+ * - 0b0101 - 64 KB of program flash memory
+ * - 0b0111 - 128 KB of program flash memory
+ * - 0b1001 - 256 KB of program flash memory
+ * - 0b1011 - 512 KB of program flash memory
+ * - 0b1101 - 1024 KB of program flash memory
+ * - 0b1111 - 1024 KB of program flash memory
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */
+#define SIM_RD_FCFG1_PFSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT)
+#define SIM_BRD_FCFG1_PFSIZE(base) (SIM_RD_FCFG1_PFSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
+ *
+ * This field specifies the amount of FlexNVM memory available on the device .
+ * Undefined values are reserved.
+ *
+ * Values:
+ * - 0b0000 - 0 KB of FlexNVM
+ * - 0b0011 - 32 KB of FlexNVM
+ * - 0b0101 - 64 KB of FlexNVM
+ * - 0b0111 - 128 KB of FlexNVM
+ * - 0b1001 - 256 KB of FlexNVM
+ * - 0b1011 - 512 KB of FlexNVM
+ * - 0b1111 - 512 KB of FlexNVM
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_NVMSIZE field. */
+#define SIM_RD_FCFG1_NVMSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_NVMSIZE_MASK) >> SIM_FCFG1_NVMSIZE_SHIFT)
+#define SIM_BRD_FCFG1_NVMSIZE(base) (SIM_RD_FCFG1_NVMSIZE(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG2 - Flash Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG2 - Flash Configuration Register 2 (RO)
+ *
+ * Reset value: 0x7F7F0000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG2 register
+ */
+/*@{*/
+#define SIM_RD_FCFG2(base)       (SIM_FCFG2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG2 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
+ *
+ * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
+ * the FlexNVM base address indicates the first invalid address of the FlexNVM
+ * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
+ * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
+ * for a device with 256 KB FlexNVM. For devices with program flash only: This
+ * field equals zero if there is only one program flash block, otherwise it equals
+ * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
+ * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
+ * the MAXADDR1 value for a device with 512 KB program flash memory across two
+ * flash blocks and no FlexNVM.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */
+#define SIM_RD_FCFG2_MAXADDR1(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR1_MASK) >> SIM_FCFG2_MAXADDR1_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR1(base) (SIM_RD_FCFG2_MAXADDR1(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field PFLSH[23] (RO)
+ *
+ * For devices with FlexNVM, this bit is always clear. For devices without
+ * FlexNVM, this bit is always set.
+ *
+ * Values:
+ * - 0b0 - Device supports FlexNVM
+ * - 0b1 - Program Flash only, device does not support FlexNVM
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_PFLSH field. */
+#define SIM_RD_FCFG2_PFLSH(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_PFLSH_MASK) >> SIM_FCFG2_PFLSH_SHIFT)
+#define SIM_BRD_FCFG2_PFLSH(base) (BITBAND_ACCESS32(&SIM_FCFG2_REG(base), SIM_FCFG2_PFLSH_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
+ *
+ * This field concatenated with 13 trailing zeros indicates the first invalid
+ * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
+ * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
+ * value for a device with 256 KB program flash in flash block 0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */
+#define SIM_RD_FCFG2_MAXADDR0(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR0_MASK) >> SIM_FCFG2_MAXADDR0_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR0(base) (SIM_RD_FCFG2_MAXADDR0(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDH - Unique Identification Register High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDH - Unique Identification Register High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDH register
+ */
+/*@{*/
+#define SIM_RD_UIDH(base)        (SIM_UIDH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDMH - Unique Identification Register Mid-High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDMH - Unique Identification Register Mid-High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDMH register
+ */
+/*@{*/
+#define SIM_RD_UIDMH(base)       (SIM_UIDMH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDML - Unique Identification Register Mid Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDML - Unique Identification Register Mid Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDML register
+ */
+/*@{*/
+#define SIM_RD_UIDML(base)       (SIM_UIDML_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDL - Unique Identification Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDL - Unique Identification Register Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDL register
+ */
+/*@{*/
+#define SIM_RD_UIDL(base)        (SIM_UIDL_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 SMC
+ *
+ * System Mode Controller
+ *
+ * Registers defined in this header file:
+ * - SMC_PMPROT - Power Mode Protection register
+ * - SMC_PMCTRL - Power Mode Control register
+ * - SMC_VLLSCTRL - VLLS Control register
+ * - SMC_PMSTAT - Power Mode Status register
+ */
+
+#define SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
+#define SMC_IDX (0U) /*!< Instance number for SMC. */
+
+/*******************************************************************************
+ * SMC_PMPROT - Power Mode Protection register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMPROT - Power Mode Protection register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides protection for entry into any low-power run or stop
+ * mode. The enabling of the low-power run or stop mode occurs by configuring the
+ * Power Mode Control register (PMCTRL). The PMPROT register can be written only
+ * once after any system reset. If the MCU is configured for a disallowed or
+ * reserved power mode, the MCU remains in its current power mode. For example, if the
+ * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
+ * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
+ * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
+ * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
+ * that do not trigger Chip Reset not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMPROT register
+ */
+/*@{*/
+#define SMC_RD_PMPROT(base)      (SMC_PMPROT_REG(base))
+#define SMC_WR_PMPROT(base, value) (SMC_PMPROT_REG(base) = (value))
+#define SMC_RMW_PMPROT(base, mask, value) (SMC_WR_PMPROT(base, (SMC_RD_PMPROT(base) & ~(mask)) | (value)))
+#define SMC_SET_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) |  (value)))
+#define SMC_CLR_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) & ~(value)))
+#define SMC_TOG_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMPROT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMPROT, field AVLLS[1] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write once
+ * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
+ *
+ * Values:
+ * - 0b0 - Any VLLSx mode is not allowed
+ * - 0b1 - Any VLLSx mode is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
+#define SMC_RD_PMPROT_AVLLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLLS_MASK) >> SMC_PMPROT_AVLLS_SHIFT)
+#define SMC_BRD_PMPROT_AVLLS(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT))
+
+/*! @brief Set the AVLLS field to a new value. */
+#define SMC_WR_PMPROT_AVLLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLLS_MASK, SMC_PMPROT_AVLLS(value)))
+#define SMC_BWR_PMPROT_AVLLS(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field ALLS[3] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any low-leakage stop mode (LLS).
+ *
+ * Values:
+ * - 0b0 - LLS is not allowed
+ * - 0b1 - LLS is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_ALLS field. */
+#define SMC_RD_PMPROT_ALLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_ALLS_MASK) >> SMC_PMPROT_ALLS_SHIFT)
+#define SMC_BRD_PMPROT_ALLS(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT))
+
+/*! @brief Set the ALLS field to a new value. */
+#define SMC_WR_PMPROT_ALLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_ALLS_MASK, SMC_PMPROT_ALLS(value)))
+#define SMC_BWR_PMPROT_ALLS(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field AVLP[5] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
+ *
+ * Values:
+ * - 0b0 - VLPR, VLPW, and VLPS are not allowed.
+ * - 0b1 - VLPR, VLPW, and VLPS are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLP field. */
+#define SMC_RD_PMPROT_AVLP(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLP_MASK) >> SMC_PMPROT_AVLP_SHIFT)
+#define SMC_BRD_PMPROT_AVLP(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT))
+
+/*! @brief Set the AVLP field to a new value. */
+#define SMC_WR_PMPROT_AVLP(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLP_MASK, SMC_PMPROT_AVLP(value)))
+#define SMC_BWR_PMPROT_AVLP(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMCTRL - Power Mode Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMCTRL - Power Mode Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The PMCTRL register controls entry into low-power Run and Stop modes,
+ * provided that the selected power mode is allowed via an appropriate setting of the
+ * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
+ * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
+ * that do not trigger Chip POR not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMCTRL register
+ */
+/*@{*/
+#define SMC_RD_PMCTRL(base)      (SMC_PMCTRL_REG(base))
+#define SMC_WR_PMCTRL(base, value) (SMC_PMCTRL_REG(base) = (value))
+#define SMC_RMW_PMCTRL(base, mask, value) (SMC_WR_PMCTRL(base, (SMC_RD_PMCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) |  (value)))
+#define SMC_CLR_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) & ~(value)))
+#define SMC_TOG_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
+ *
+ * When written, controls entry into the selected stop mode when Sleep-Now or
+ * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
+ * blocked if the protection level has not been enabled using the PMPROT register.
+ * After any system reset, this field is cleared by hardware on any successful write
+ * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
+ * register is used to further select the particular VLLS submode which will be
+ * entered.
+ *
+ * Values:
+ * - 0b000 - Normal Stop (STOP)
+ * - 0b001 - Reserved
+ * - 0b010 - Very-Low-Power Stop (VLPS)
+ * - 0b011 - Low-Leakage Stop (LLS)
+ * - 0b100 - Very-Low-Leakage Stop (VLLSx)
+ * - 0b101 - Reserved
+ * - 0b110 - Reseved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
+#define SMC_RD_PMCTRL_STOPM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPM_MASK) >> SMC_PMCTRL_STOPM_SHIFT)
+#define SMC_BRD_PMCTRL_STOPM(base) (SMC_RD_PMCTRL_STOPM(base))
+
+/*! @brief Set the STOPM field to a new value. */
+#define SMC_WR_PMCTRL_STOPM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_STOPM_MASK, SMC_PMCTRL_STOPM(value)))
+#define SMC_BWR_PMCTRL_STOPM(base, value) (SMC_WR_PMCTRL_STOPM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPA[3] (RO)
+ *
+ * When set, this read-only status bit indicates an interrupt or reset occured
+ * during the previous stop mode entry sequence, preventing the system from
+ * entering that mode. This field is cleared by hardware at the beginning of any stop
+ * mode entry sequence and is set if the sequence was aborted.
+ *
+ * Values:
+ * - 0b0 - The previous stop mode entry was successsful.
+ * - 0b1 - The previous stop mode entry was aborted.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
+#define SMC_RD_PMCTRL_STOPA(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPA_MASK) >> SMC_PMCTRL_STOPA_SHIFT)
+#define SMC_BRD_PMCTRL_STOPA(base) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_STOPA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
+ *
+ * When written, causes entry into the selected run mode. Writes to this field
+ * are blocked if the protection level has not been enabled using the PMPROT
+ * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
+ * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
+ *
+ * Values:
+ * - 0b00 - Normal Run mode (RUN)
+ * - 0b01 - Reserved
+ * - 0b10 - Very-Low-Power Run mode (VLPR)
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
+#define SMC_RD_PMCTRL_RUNM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_RUNM_MASK) >> SMC_PMCTRL_RUNM_SHIFT)
+#define SMC_BRD_PMCTRL_RUNM(base) (SMC_RD_PMCTRL_RUNM(base))
+
+/*! @brief Set the RUNM field to a new value. */
+#define SMC_WR_PMCTRL_RUNM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_RUNM_MASK, SMC_PMCTRL_RUNM(value)))
+#define SMC_BWR_PMCTRL_RUNM(base, value) (SMC_WR_PMCTRL_RUNM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
+ *
+ * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
+ * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
+ * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
+ * the LPWUI setting. LPWUI must be modified only while the system is in RUN
+ * mode, that is, when PMSTAT=RUN.
+ *
+ * Values:
+ * - 0b0 - The system remains in a VLP mode on an interrupt
+ * - 0b1 - The system exits to Normal RUN mode on an interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_LPWUI field. */
+#define SMC_RD_PMCTRL_LPWUI(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_LPWUI_MASK) >> SMC_PMCTRL_LPWUI_SHIFT)
+#define SMC_BRD_PMCTRL_LPWUI(base) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_LPWUI_SHIFT))
+
+/*! @brief Set the LPWUI field to a new value. */
+#define SMC_WR_PMCTRL_LPWUI(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_LPWUI_MASK, SMC_PMCTRL_LPWUI(value)))
+#define SMC_BWR_PMCTRL_LPWUI(base, value) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_LPWUI_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_VLLSCTRL - VLLS Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_VLLSCTRL - VLLS Control register (RW)
+ *
+ * Reset value: 0x03U
+ *
+ * The VLLSCTRL register controls features related to VLLS modes. This register
+ * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
+ * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
+ * the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_VLLSCTRL register
+ */
+/*@{*/
+#define SMC_RD_VLLSCTRL(base)    (SMC_VLLSCTRL_REG(base))
+#define SMC_WR_VLLSCTRL(base, value) (SMC_VLLSCTRL_REG(base) = (value))
+#define SMC_RMW_VLLSCTRL(base, mask, value) (SMC_WR_VLLSCTRL(base, (SMC_RD_VLLSCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) |  (value)))
+#define SMC_CLR_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) & ~(value)))
+#define SMC_TOG_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_VLLSCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
+ *
+ * Controls which VLLS sub-mode to enter if STOPM=VLLS.
+ *
+ * Values:
+ * - 0b000 - VLLS0
+ * - 0b001 - VLLS1
+ * - 0b010 - VLLS2
+ * - 0b011 - VLLS3
+ * - 0b100 - Reserved
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_VLLSCTRL_VLLSM field. */
+#define SMC_RD_VLLSCTRL_VLLSM(base) ((SMC_VLLSCTRL_REG(base) & SMC_VLLSCTRL_VLLSM_MASK) >> SMC_VLLSCTRL_VLLSM_SHIFT)
+#define SMC_BRD_VLLSCTRL_VLLSM(base) (SMC_RD_VLLSCTRL_VLLSM(base))
+
+/*! @brief Set the VLLSM field to a new value. */
+#define SMC_WR_VLLSCTRL_VLLSM(base, value) (SMC_RMW_VLLSCTRL(base, SMC_VLLSCTRL_VLLSM_MASK, SMC_VLLSCTRL_VLLSM(value)))
+#define SMC_BWR_VLLSCTRL_VLLSM(base, value) (SMC_WR_VLLSCTRL_VLLSM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
+ *
+ * Controls whether the POR detect circuit (for brown-out detection) is enabled
+ * in VLLS0 mode.
+ *
+ * Values:
+ * - 0b0 - POR detect circuit is enabled in VLLS0.
+ * - 0b1 - POR detect circuit is disabled in VLLS0.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_VLLSCTRL_PORPO field. */
+#define SMC_RD_VLLSCTRL_PORPO(base) ((SMC_VLLSCTRL_REG(base) & SMC_VLLSCTRL_PORPO_MASK) >> SMC_VLLSCTRL_PORPO_SHIFT)
+#define SMC_BRD_VLLSCTRL_PORPO(base) (BITBAND_ACCESS8(&SMC_VLLSCTRL_REG(base), SMC_VLLSCTRL_PORPO_SHIFT))
+
+/*! @brief Set the PORPO field to a new value. */
+#define SMC_WR_VLLSCTRL_PORPO(base, value) (SMC_RMW_VLLSCTRL(base, SMC_VLLSCTRL_PORPO_MASK, SMC_VLLSCTRL_PORPO(value)))
+#define SMC_BWR_VLLSCTRL_PORPO(base, value) (BITBAND_ACCESS8(&SMC_VLLSCTRL_REG(base), SMC_VLLSCTRL_PORPO_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMSTAT - Power Mode Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMSTAT - Power Mode Status register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * PMSTAT is a read-only, one-hot register which indicates the current power
+ * mode of the system. This register is reset on Chip POR not VLLS and by reset
+ * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
+ * trigger Chip POR not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMSTAT register
+ */
+/*@{*/
+#define SMC_RD_PMSTAT(base)      (SMC_PMSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMSTAT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
+ *
+ * When debug is enabled, the PMSTAT will not update to STOP or VLPS
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */
+#define SMC_RD_PMSTAT_PMSTAT(base) ((SMC_PMSTAT_REG(base) & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT)
+#define SMC_BRD_PMSTAT_PMSTAT(base) (SMC_RD_PMSTAT_PMSTAT(base))
+/*@}*/
+
+/*
+ * MK64F12 SPI
+ *
+ * Serial Peripheral Interface
+ *
+ * Registers defined in this header file:
+ * - SPI_MCR - Module Configuration Register
+ * - SPI_TCR - Transfer Count Register
+ * - SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
+ * - SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ * - SPI_SR - Status Register
+ * - SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ * - SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ * - SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ * - SPI_POPR - POP RX FIFO Register
+ * - SPI_TXFR0 - Transmit FIFO Registers
+ * - SPI_TXFR1 - Transmit FIFO Registers
+ * - SPI_TXFR2 - Transmit FIFO Registers
+ * - SPI_TXFR3 - Transmit FIFO Registers
+ * - SPI_RXFR0 - Receive FIFO Registers
+ * - SPI_RXFR1 - Receive FIFO Registers
+ * - SPI_RXFR2 - Receive FIFO Registers
+ * - SPI_RXFR3 - Receive FIFO Registers
+ */
+
+#define SPI_INSTANCE_COUNT (3U) /*!< Number of instances of the SPI module. */
+#define SPI0_IDX (0U) /*!< Instance number for SPI0. */
+#define SPI1_IDX (1U) /*!< Instance number for SPI1. */
+#define SPI2_IDX (2U) /*!< Instance number for SPI2. */
+
+/*******************************************************************************
+ * SPI_MCR - Module Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0x00004001U
+ *
+ * Contains bits to configure various attributes associated with the module
+ * operations. The HALT and MDIS bits can be changed at any time, but the effect
+ * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
+ * MCR can be changed, while the module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_MCR register
+ */
+/*@{*/
+#define SPI_RD_MCR(base)         (SPI_MCR_REG(base))
+#define SPI_WR_MCR(base, value)  (SPI_MCR_REG(base) = (value))
+#define SPI_RMW_MCR(base, mask, value) (SPI_WR_MCR(base, (SPI_RD_MCR(base) & ~(mask)) | (value)))
+#define SPI_SET_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) |  (value)))
+#define SPI_CLR_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) & ~(value)))
+#define SPI_TOG_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_MCR bitfields
+ */
+
+/*!
+ * @name Register SPI_MCR, field HALT[0] (RW)
+ *
+ * The HALT bit starts and stops frame transfers. See Start and Stop of Module
+ * transfers
+ *
+ * Values:
+ * - 0b0 - Start transfers.
+ * - 0b1 - Stop transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_HALT field. */
+#define SPI_RD_MCR_HALT(base) ((SPI_MCR_REG(base) & SPI_MCR_HALT_MASK) >> SPI_MCR_HALT_SHIFT)
+#define SPI_BRD_MCR_HALT(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define SPI_WR_MCR_HALT(base, value) (SPI_RMW_MCR(base, SPI_MCR_HALT_MASK, SPI_MCR_HALT(value)))
+#define SPI_BWR_MCR_HALT(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
+ *
+ * Controls when the module master samples SIN in Modified Transfer Format. This
+ * field is valid only when CPHA bit in CTARn[CPHA] is 0.
+ *
+ * Values:
+ * - 0b00 - 0 protocol clock cycles between SCK edge and SIN sample
+ * - 0b01 - 1 protocol clock cycle between SCK edge and SIN sample
+ * - 0b10 - 2 protocol clock cycles between SCK edge and SIN sample
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_SMPL_PT field. */
+#define SPI_RD_MCR_SMPL_PT(base) ((SPI_MCR_REG(base) & SPI_MCR_SMPL_PT_MASK) >> SPI_MCR_SMPL_PT_SHIFT)
+#define SPI_BRD_MCR_SMPL_PT(base) (SPI_RD_MCR_SMPL_PT(base))
+
+/*! @brief Set the SMPL_PT field to a new value. */
+#define SPI_WR_MCR_SMPL_PT(base, value) (SPI_RMW_MCR(base, SPI_MCR_SMPL_PT_MASK, SPI_MCR_SMPL_PT(value)))
+#define SPI_BWR_MCR_SMPL_PT(base, value) (SPI_WR_MCR_SMPL_PT(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
+ *
+ * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
+ * CLR_RXF bit is always read as zero.
+ *
+ * Values:
+ * - 0b0 - Do not clear the RX FIFO counter.
+ * - 0b1 - Clear the RX FIFO counter.
+ */
+/*@{*/
+/*! @brief Set the CLR_RXF field to a new value. */
+#define SPI_WR_MCR_CLR_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_RXF_MASK, SPI_MCR_CLR_RXF(value)))
+#define SPI_BWR_MCR_CLR_RXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CLR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
+ *
+ * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
+ * CLR_TXF bit is always read as zero.
+ *
+ * Values:
+ * - 0b0 - Do not clear the TX FIFO counter.
+ * - 0b1 - Clear the TX FIFO counter.
+ */
+/*@{*/
+/*! @brief Set the CLR_TXF field to a new value. */
+#define SPI_WR_MCR_CLR_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_TXF_MASK, SPI_MCR_CLR_TXF(value)))
+#define SPI_BWR_MCR_CLR_TXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CLR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DIS_RXF[12] (RW)
+ *
+ * When the RX FIFO is disabled, the receive part of the module operates as a
+ * simplified double-buffered SPI. This bit can only be written when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0b0 - RX FIFO is enabled.
+ * - 0b1 - RX FIFO is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DIS_RXF field. */
+#define SPI_RD_MCR_DIS_RXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_RXF_MASK) >> SPI_MCR_DIS_RXF_SHIFT)
+#define SPI_BRD_MCR_DIS_RXF(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT))
+
+/*! @brief Set the DIS_RXF field to a new value. */
+#define SPI_WR_MCR_DIS_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_RXF_MASK, SPI_MCR_DIS_RXF(value)))
+#define SPI_BWR_MCR_DIS_RXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DIS_TXF[13] (RW)
+ *
+ * When the TX FIFO is disabled, the transmit part of the module operates as a
+ * simplified double-buffered SPI. This bit can be written only when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0b0 - TX FIFO is enabled.
+ * - 0b1 - TX FIFO is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DIS_TXF field. */
+#define SPI_RD_MCR_DIS_TXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_TXF_MASK) >> SPI_MCR_DIS_TXF_SHIFT)
+#define SPI_BRD_MCR_DIS_TXF(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT))
+
+/*! @brief Set the DIS_TXF field to a new value. */
+#define SPI_WR_MCR_DIS_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_TXF_MASK, SPI_MCR_DIS_TXF(value)))
+#define SPI_BWR_MCR_DIS_TXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MDIS[14] (RW)
+ *
+ * Allows the clock to be stopped to the non-memory mapped logic in the module
+ * effectively putting it in a software-controlled power-saving state. The reset
+ * value of the MDIS bit is parameterized, with a default reset value of 0. When
+ * the module is used in Slave Mode, we recommend leaving this bit 0, because a
+ * slave doesn't have control over master transactions.
+ *
+ * Values:
+ * - 0b0 - Enables the module clocks.
+ * - 0b1 - Allows external logic to disable the module clocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MDIS field. */
+#define SPI_RD_MCR_MDIS(base) ((SPI_MCR_REG(base) & SPI_MCR_MDIS_MASK) >> SPI_MCR_MDIS_SHIFT)
+#define SPI_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define SPI_WR_MCR_MDIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_MDIS_MASK, SPI_MCR_MDIS(value)))
+#define SPI_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DOZE[15] (RW)
+ *
+ * Provides support for an externally controlled Doze mode power-saving
+ * mechanism.
+ *
+ * Values:
+ * - 0b0 - Doze mode has no effect on the module.
+ * - 0b1 - Doze mode disables the module.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DOZE field. */
+#define SPI_RD_MCR_DOZE(base) ((SPI_MCR_REG(base) & SPI_MCR_DOZE_MASK) >> SPI_MCR_DOZE_SHIFT)
+#define SPI_BRD_MCR_DOZE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT))
+
+/*! @brief Set the DOZE field to a new value. */
+#define SPI_WR_MCR_DOZE(base, value) (SPI_RMW_MCR(base, SPI_MCR_DOZE_MASK, SPI_MCR_DOZE(value)))
+#define SPI_BWR_MCR_DOZE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field PCSIS[21:16] (RW)
+ *
+ * Determines the inactive state of PCSx.
+ *
+ * Values:
+ * - 0b000000 - The inactive state of PCSx is low.
+ * - 0b000001 - The inactive state of PCSx is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_PCSIS field. */
+#define SPI_RD_MCR_PCSIS(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSIS_MASK) >> SPI_MCR_PCSIS_SHIFT)
+#define SPI_BRD_MCR_PCSIS(base) (SPI_RD_MCR_PCSIS(base))
+
+/*! @brief Set the PCSIS field to a new value. */
+#define SPI_WR_MCR_PCSIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSIS_MASK, SPI_MCR_PCSIS(value)))
+#define SPI_BWR_MCR_PCSIS(base, value) (SPI_WR_MCR_PCSIS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field ROOE[24] (RW)
+ *
+ * In the RX FIFO overflow condition, configures the module to ignore the
+ * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
+ * is received, the data from the transfer, generating the overflow, is ignored
+ * or shifted into the shift register.
+ *
+ * Values:
+ * - 0b0 - Incoming data is ignored.
+ * - 0b1 - Incoming data is shifted into the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_ROOE field. */
+#define SPI_RD_MCR_ROOE(base) ((SPI_MCR_REG(base) & SPI_MCR_ROOE_MASK) >> SPI_MCR_ROOE_SHIFT)
+#define SPI_BRD_MCR_ROOE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT))
+
+/*! @brief Set the ROOE field to a new value. */
+#define SPI_WR_MCR_ROOE(base, value) (SPI_RMW_MCR(base, SPI_MCR_ROOE_MASK, SPI_MCR_ROOE(value)))
+#define SPI_BWR_MCR_ROOE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field PCSSE[25] (RW)
+ *
+ * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
+ *
+ * Values:
+ * - 0b0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
+ * - 0b1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_PCSSE field. */
+#define SPI_RD_MCR_PCSSE(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSSE_MASK) >> SPI_MCR_PCSSE_SHIFT)
+#define SPI_BRD_MCR_PCSSE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_PCSSE_SHIFT))
+
+/*! @brief Set the PCSSE field to a new value. */
+#define SPI_WR_MCR_PCSSE(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSSE_MASK, SPI_MCR_PCSSE(value)))
+#define SPI_BWR_MCR_PCSSE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_PCSSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MTFE[26] (RW)
+ *
+ * Enables a modified transfer format to be used.
+ *
+ * Values:
+ * - 0b0 - Modified SPI transfer format disabled.
+ * - 0b1 - Modified SPI transfer format enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MTFE field. */
+#define SPI_RD_MCR_MTFE(base) ((SPI_MCR_REG(base) & SPI_MCR_MTFE_MASK) >> SPI_MCR_MTFE_SHIFT)
+#define SPI_BRD_MCR_MTFE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT))
+
+/*! @brief Set the MTFE field to a new value. */
+#define SPI_WR_MCR_MTFE(base, value) (SPI_RMW_MCR(base, SPI_MCR_MTFE_MASK, SPI_MCR_MTFE(value)))
+#define SPI_BWR_MCR_MTFE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field FRZ[27] (RW)
+ *
+ * Enables transfers to be stopped on the next frame boundary when the device
+ * enters Debug mode.
+ *
+ * Values:
+ * - 0b0 - Do not halt serial transfers in Debug mode.
+ * - 0b1 - Halt serial transfers in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_FRZ field. */
+#define SPI_RD_MCR_FRZ(base) ((SPI_MCR_REG(base) & SPI_MCR_FRZ_MASK) >> SPI_MCR_FRZ_SHIFT)
+#define SPI_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define SPI_WR_MCR_FRZ(base, value) (SPI_RMW_MCR(base, SPI_MCR_FRZ_MASK, SPI_MCR_FRZ(value)))
+#define SPI_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DCONF[29:28] (RO)
+ *
+ * Selects among the different configurations of the module.
+ *
+ * Values:
+ * - 0b00 - SPI
+ * - 0b01 - Reserved
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DCONF field. */
+#define SPI_RD_MCR_DCONF(base) ((SPI_MCR_REG(base) & SPI_MCR_DCONF_MASK) >> SPI_MCR_DCONF_SHIFT)
+#define SPI_BRD_MCR_DCONF(base) (SPI_RD_MCR_DCONF(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
+ *
+ * Enables the Serial Communication Clock (SCK) to run continuously.
+ *
+ * Values:
+ * - 0b0 - Continuous SCK disabled.
+ * - 0b1 - Continuous SCK enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */
+#define SPI_RD_MCR_CONT_SCKE(base) ((SPI_MCR_REG(base) & SPI_MCR_CONT_SCKE_MASK) >> SPI_MCR_CONT_SCKE_SHIFT)
+#define SPI_BRD_MCR_CONT_SCKE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT))
+
+/*! @brief Set the CONT_SCKE field to a new value. */
+#define SPI_WR_MCR_CONT_SCKE(base, value) (SPI_RMW_MCR(base, SPI_MCR_CONT_SCKE_MASK, SPI_MCR_CONT_SCKE(value)))
+#define SPI_BWR_MCR_CONT_SCKE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MSTR[31] (RW)
+ *
+ * Enables either Master mode (if supported) or Slave mode (if supported)
+ * operation.
+ *
+ * Values:
+ * - 0b0 - Enables Slave mode
+ * - 0b1 - Enables Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MSTR field. */
+#define SPI_RD_MCR_MSTR(base) ((SPI_MCR_REG(base) & SPI_MCR_MSTR_MASK) >> SPI_MCR_MSTR_SHIFT)
+#define SPI_BRD_MCR_MSTR(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT))
+
+/*! @brief Set the MSTR field to a new value. */
+#define SPI_WR_MCR_MSTR(base, value) (SPI_RMW_MCR(base, SPI_MCR_MSTR_MASK, SPI_MCR_MSTR(value)))
+#define SPI_BWR_MCR_MSTR(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TCR - Transfer Count Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TCR - Transfer Count Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR contains a counter that indicates the number of SPI transfers made. The
+ * transfer counter is intended to assist in queue management. Do not write the
+ * TCR when the module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TCR register
+ */
+/*@{*/
+#define SPI_RD_TCR(base)         (SPI_TCR_REG(base))
+#define SPI_WR_TCR(base, value)  (SPI_TCR_REG(base) = (value))
+#define SPI_RMW_TCR(base, mask, value) (SPI_WR_TCR(base, (SPI_RD_TCR(base) & ~(mask)) | (value)))
+#define SPI_SET_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) |  (value)))
+#define SPI_CLR_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) & ~(value)))
+#define SPI_TOG_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TCR bitfields
+ */
+
+/*!
+ * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
+ *
+ * Counts the number of SPI transfers the module makes. The SPI_TCNT field
+ * increments every time the last bit of an SPI frame is transmitted. A value written
+ * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
+ * the beginning of the frame when the CTCNT field is set in the executing SPI
+ * command. The Transfer Counter wraps around; incrementing the counter past 65535
+ * resets the counter to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */
+#define SPI_RD_TCR_SPI_TCNT(base) ((SPI_TCR_REG(base) & SPI_TCR_SPI_TCNT_MASK) >> SPI_TCR_SPI_TCNT_SHIFT)
+#define SPI_BRD_TCR_SPI_TCNT(base) (SPI_RD_TCR_SPI_TCNT(base))
+
+/*! @brief Set the SPI_TCNT field to a new value. */
+#define SPI_WR_TCR_SPI_TCNT(base, value) (SPI_RMW_TCR(base, SPI_TCR_SPI_TCNT_MASK, SPI_TCR_SPI_TCNT(value)))
+#define SPI_BWR_TCR_SPI_TCNT(base, value) (SPI_WR_TCR_SPI_TCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * When the module is configured as an SPI bus slave, the CTAR0 register is used.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CTAR_SLAVE register
+ */
+/*@{*/
+#define SPI_RD_CTAR_SLAVE(base, index) (SPI_CTAR_SLAVE_REG(base, index))
+#define SPI_WR_CTAR_SLAVE(base, index, value) (SPI_CTAR_SLAVE_REG(base, index) = (value))
+#define SPI_RMW_CTAR_SLAVE(base, index, mask, value) (SPI_WR_CTAR_SLAVE(base, index, (SPI_RD_CTAR_SLAVE(base, index) & ~(mask)) | (value)))
+#define SPI_SET_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) |  (value)))
+#define SPI_CLR_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) & ~(value)))
+#define SPI_TOG_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CTAR_SLAVE bitfields
+ */
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0b0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 0b1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_CPHA field. */
+#define SPI_RD_CTAR_SLAVE_CPHA(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPHA_MASK) >> SPI_CTAR_SLAVE_CPHA_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_CPHA(base, index) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_CTAR_SLAVE_CPHA(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPHA_MASK, SPI_CTAR_SLAVE_CPHA(value)))
+#define SPI_BWR_CTAR_SLAVE_CPHA(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0b0 - The inactive state value of SCK is low.
+ * - 0b1 - The inactive state value of SCK is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_CPOL field. */
+#define SPI_RD_CTAR_SLAVE_CPOL(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPOL_MASK) >> SPI_CTAR_SLAVE_CPOL_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_CPOL(base, index) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_CTAR_SLAVE_CPOL(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPOL_MASK, SPI_CTAR_SLAVE_CPOL(value)))
+#define SPI_BWR_CTAR_SLAVE_CPOL(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field FMSZ[31:27] (RW)
+ *
+ * The number of bits transfered per frame is equal to the FMSZ field value plus
+ * 1. Note that the minimum valid value of frame size is 4.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_FMSZ field. */
+#define SPI_RD_CTAR_SLAVE_FMSZ(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_FMSZ(base, index) (SPI_RD_CTAR_SLAVE_FMSZ(base, index))
+
+/*! @brief Set the FMSZ field to a new value. */
+#define SPI_WR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_FMSZ_MASK, SPI_CTAR_SLAVE_FMSZ(value)))
+#define SPI_BWR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_WR_CTAR_SLAVE_FMSZ(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * CTAR registers are used to define different transfer attributes. Do not write
+ * to the CTAR registers while the module is in the Running state. In Master
+ * mode, the CTAR registers define combinations of transfer attributes such as frame
+ * size, clock phase and polarity, data bit ordering, baud rate, and various
+ * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
+ * slave transfer attributes. When the module is configured as an SPI master, the
+ * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
+ * registers is used. When the module is configured as an SPI bus slave, it uses
+ * the CTAR0 register.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CTAR register
+ */
+/*@{*/
+#define SPI_RD_CTAR(base, index) (SPI_CTAR_REG(base, index))
+#define SPI_WR_CTAR(base, index, value) (SPI_CTAR_REG(base, index) = (value))
+#define SPI_RMW_CTAR(base, index, mask, value) (SPI_WR_CTAR(base, index, (SPI_RD_CTAR(base, index) & ~(mask)) | (value)))
+#define SPI_SET_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) |  (value)))
+#define SPI_CLR_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) & ~(value)))
+#define SPI_TOG_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CTAR bitfields
+ */
+
+/*!
+ * @name Register SPI_CTAR, field BR[3:0] (RW)
+ *
+ * Selects the scaler value for the baud rate. This field is used only in master
+ * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
+ * generate the frequency of the SCK. The baud rate is computed according to the
+ * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
+ * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
+ * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
+ * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_BR field. */
+#define SPI_RD_CTAR_BR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_BR_MASK) >> SPI_CTAR_BR_SHIFT)
+#define SPI_BRD_CTAR_BR(base, index) (SPI_RD_CTAR_BR(base, index))
+
+/*! @brief Set the BR field to a new value. */
+#define SPI_WR_CTAR_BR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_BR_MASK, SPI_CTAR_BR(value)))
+#define SPI_BWR_CTAR_BR(base, index, value) (SPI_WR_CTAR_BR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field DT[7:4] (RW)
+ *
+ * Selects the Delay after Transfer Scaler. This field is used only in master
+ * mode. The Delay after Transfer is the time between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the next
+ * frame. In the Continuous Serial Communications Clock operation, the DT value
+ * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
+ * protocol clock period, and it is computed according to the following
+ * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
+ * field description for scaler values.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_DT field. */
+#define SPI_RD_CTAR_DT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DT_MASK) >> SPI_CTAR_DT_SHIFT)
+#define SPI_BRD_CTAR_DT(base, index) (SPI_RD_CTAR_DT(base, index))
+
+/*! @brief Set the DT field to a new value. */
+#define SPI_WR_CTAR_DT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DT_MASK, SPI_CTAR_DT(value)))
+#define SPI_BWR_CTAR_DT(base, index, value) (SPI_WR_CTAR_DT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field ASC[11:8] (RW)
+ *
+ * Selects the scaler value for the After SCK Delay. This field is used only in
+ * master mode. The After SCK Delay is the delay between the last edge of SCK and
+ * the negation of PCS. The delay is a multiple of the protocol clock period,
+ * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
+ * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
+ * scaler values. Refer After SCK Delay (tASC ) for more details.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_ASC field. */
+#define SPI_RD_CTAR_ASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_ASC_MASK) >> SPI_CTAR_ASC_SHIFT)
+#define SPI_BRD_CTAR_ASC(base, index) (SPI_RD_CTAR_ASC(base, index))
+
+/*! @brief Set the ASC field to a new value. */
+#define SPI_WR_CTAR_ASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_ASC_MASK, SPI_CTAR_ASC(value)))
+#define SPI_BWR_CTAR_ASC(base, index, value) (SPI_WR_CTAR_ASC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CSSCK[15:12] (RW)
+ *
+ * Selects the scaler value for the PCS to SCK delay. This field is used only in
+ * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
+ * and the first edge of the SCK. The delay is a multiple of the protocol clock
+ * period, and it is computed according to the following equation: t CSC = (1/fP )
+ * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
+ * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
+ * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
+ * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
+ * details.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CSSCK field. */
+#define SPI_RD_CTAR_CSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CSSCK_MASK) >> SPI_CTAR_CSSCK_SHIFT)
+#define SPI_BRD_CTAR_CSSCK(base, index) (SPI_RD_CTAR_CSSCK(base, index))
+
+/*! @brief Set the CSSCK field to a new value. */
+#define SPI_WR_CTAR_CSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CSSCK_MASK, SPI_CTAR_CSSCK(value)))
+#define SPI_BWR_CTAR_CSSCK(base, index, value) (SPI_WR_CTAR_CSSCK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PBR[17:16] (RW)
+ *
+ * Selects the prescaler value for the baud rate. This field is used only in
+ * master mode. The baud rate is the frequency of the SCK. The protocol clock is
+ * divided by the prescaler value before the baud rate selection takes place. See
+ * the BR field description for details on how to compute the baud rate.
+ *
+ * Values:
+ * - 0b00 - Baud Rate Prescaler value is 2.
+ * - 0b01 - Baud Rate Prescaler value is 3.
+ * - 0b10 - Baud Rate Prescaler value is 5.
+ * - 0b11 - Baud Rate Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PBR field. */
+#define SPI_RD_CTAR_PBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PBR_MASK) >> SPI_CTAR_PBR_SHIFT)
+#define SPI_BRD_CTAR_PBR(base, index) (SPI_RD_CTAR_PBR(base, index))
+
+/*! @brief Set the PBR field to a new value. */
+#define SPI_WR_CTAR_PBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PBR_MASK, SPI_CTAR_PBR(value)))
+#define SPI_BWR_CTAR_PBR(base, index, value) (SPI_WR_CTAR_PBR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PDT[19:18] (RW)
+ *
+ * Selects the prescaler value for the delay between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the
+ * next frame. The PDT field is only used in master mode. See the DT field
+ * description for details on how to compute the Delay after Transfer. Refer Delay after
+ * Transfer (tDT ) for more details.
+ *
+ * Values:
+ * - 0b00 - Delay after Transfer Prescaler value is 1.
+ * - 0b01 - Delay after Transfer Prescaler value is 3.
+ * - 0b10 - Delay after Transfer Prescaler value is 5.
+ * - 0b11 - Delay after Transfer Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PDT field. */
+#define SPI_RD_CTAR_PDT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PDT_MASK) >> SPI_CTAR_PDT_SHIFT)
+#define SPI_BRD_CTAR_PDT(base, index) (SPI_RD_CTAR_PDT(base, index))
+
+/*! @brief Set the PDT field to a new value. */
+#define SPI_WR_CTAR_PDT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PDT_MASK, SPI_CTAR_PDT(value)))
+#define SPI_BWR_CTAR_PDT(base, index, value) (SPI_WR_CTAR_PDT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PASC[21:20] (RW)
+ *
+ * Selects the prescaler value for the delay between the last edge of SCK and
+ * the negation of PCS. See the ASC field description for information on how to
+ * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
+ *
+ * Values:
+ * - 0b00 - Delay after Transfer Prescaler value is 1.
+ * - 0b01 - Delay after Transfer Prescaler value is 3.
+ * - 0b10 - Delay after Transfer Prescaler value is 5.
+ * - 0b11 - Delay after Transfer Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PASC field. */
+#define SPI_RD_CTAR_PASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PASC_MASK) >> SPI_CTAR_PASC_SHIFT)
+#define SPI_BRD_CTAR_PASC(base, index) (SPI_RD_CTAR_PASC(base, index))
+
+/*! @brief Set the PASC field to a new value. */
+#define SPI_WR_CTAR_PASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PASC_MASK, SPI_CTAR_PASC(value)))
+#define SPI_BWR_CTAR_PASC(base, index, value) (SPI_WR_CTAR_PASC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PCSSCK[23:22] (RW)
+ *
+ * Selects the prescaler value for the delay between assertion of PCS and the
+ * first edge of the SCK. See the CSSCK field description for information on how to
+ * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
+ *
+ * Values:
+ * - 0b00 - PCS to SCK Prescaler value is 1.
+ * - 0b01 - PCS to SCK Prescaler value is 3.
+ * - 0b10 - PCS to SCK Prescaler value is 5.
+ * - 0b11 - PCS to SCK Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PCSSCK field. */
+#define SPI_RD_CTAR_PCSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PCSSCK_MASK) >> SPI_CTAR_PCSSCK_SHIFT)
+#define SPI_BRD_CTAR_PCSSCK(base, index) (SPI_RD_CTAR_PCSSCK(base, index))
+
+/*! @brief Set the PCSSCK field to a new value. */
+#define SPI_WR_CTAR_PCSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PCSSCK_MASK, SPI_CTAR_PCSSCK(value)))
+#define SPI_BWR_CTAR_PCSSCK(base, index, value) (SPI_WR_CTAR_PCSSCK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field LSBFE[24] (RW)
+ *
+ * Specifies whether the LSB or MSB of the frame is transferred first.
+ *
+ * Values:
+ * - 0b0 - Data is transferred MSB first.
+ * - 0b1 - Data is transferred LSB first.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_LSBFE field. */
+#define SPI_RD_CTAR_LSBFE(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_LSBFE_MASK) >> SPI_CTAR_LSBFE_SHIFT)
+#define SPI_BRD_CTAR_LSBFE(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT))
+
+/*! @brief Set the LSBFE field to a new value. */
+#define SPI_WR_CTAR_LSBFE(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_LSBFE_MASK, SPI_CTAR_LSBFE(value)))
+#define SPI_BWR_CTAR_LSBFE(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0b0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 0b1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CPHA field. */
+#define SPI_RD_CTAR_CPHA(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPHA_MASK) >> SPI_CTAR_CPHA_SHIFT)
+#define SPI_BRD_CTAR_CPHA(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_CTAR_CPHA(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPHA_MASK, SPI_CTAR_CPHA(value)))
+#define SPI_BWR_CTAR_CPHA(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). This bit
+ * is used in both master and slave mode. For successful communication between
+ * serial devices, the devices must have identical clock polarities. When the
+ * Continuous Selection Format is selected, switching between clock polarities
+ * without stopping the module can cause errors in the transfer due to the peripheral
+ * device interpreting the switch of clock polarity as a valid clock edge. In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0b0 - The inactive state value of SCK is low.
+ * - 0b1 - The inactive state value of SCK is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CPOL field. */
+#define SPI_RD_CTAR_CPOL(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPOL_MASK) >> SPI_CTAR_CPOL_SHIFT)
+#define SPI_BRD_CTAR_CPOL(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_CTAR_CPOL(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPOL_MASK, SPI_CTAR_CPOL(value)))
+#define SPI_BWR_CTAR_CPOL(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field FMSZ[30:27] (RW)
+ *
+ * The number of bits transferred per frame is equal to the FMSZ value plus 1.
+ * Regardless of the transmission mode, the minimum valid frame size value is 4.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_FMSZ field. */
+#define SPI_RD_CTAR_FMSZ(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT)
+#define SPI_BRD_CTAR_FMSZ(base, index) (SPI_RD_CTAR_FMSZ(base, index))
+
+/*! @brief Set the FMSZ field to a new value. */
+#define SPI_WR_CTAR_FMSZ(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_FMSZ_MASK, SPI_CTAR_FMSZ(value)))
+#define SPI_BWR_CTAR_FMSZ(base, index, value) (SPI_WR_CTAR_FMSZ(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field DBR[31] (RW)
+ *
+ * Doubles the effective baud rate of the Serial Communications Clock (SCK).
+ * This field is used only in master mode. It effectively halves the Baud Rate
+ * division ratio, supporting faster frequencies, and odd division ratios for the
+ * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
+ * Serial Communications Clock (SCK) depends on the value in the Baud Rate
+ * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
+ * description for details on how to compute the baud rate. SPI SCK Duty Cycle
+ * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
+ * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
+ *
+ * Values:
+ * - 0b0 - The baud rate is computed normally with a 50/50 duty cycle.
+ * - 0b1 - The baud rate is doubled with the duty cycle depending on the Baud
+ *     Rate Prescaler.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_DBR field. */
+#define SPI_RD_CTAR_DBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DBR_MASK) >> SPI_CTAR_DBR_SHIFT)
+#define SPI_BRD_CTAR_DBR(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT))
+
+/*! @brief Set the DBR field to a new value. */
+#define SPI_WR_CTAR_DBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DBR_MASK, SPI_CTAR_DBR(value)))
+#define SPI_BWR_CTAR_DBR(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_SR - Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_SR - Status Register (RW)
+ *
+ * Reset value: 0x02000000U
+ *
+ * SR contains status and flag bits. The bits reflect the status of the module
+ * and indicate the occurrence of events that can generate interrupt or DMA
+ * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
+ * to a flag bit has no effect. This register may not be writable in Module
+ * Disable mode due to the use of power saving mechanisms.
+ */
+/*!
+ * @name Constants and macros for entire SPI_SR register
+ */
+/*@{*/
+#define SPI_RD_SR(base)          (SPI_SR_REG(base))
+#define SPI_WR_SR(base, value)   (SPI_SR_REG(base) = (value))
+#define SPI_RMW_SR(base, mask, value) (SPI_WR_SR(base, (SPI_RD_SR(base) & ~(mask)) | (value)))
+#define SPI_SET_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) |  (value)))
+#define SPI_CLR_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) & ~(value)))
+#define SPI_TOG_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_SR bitfields
+ */
+
+/*!
+ * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
+ *
+ * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
+ * The POPNXTPTR is updated when the POPR is read.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_POPNXTPTR field. */
+#define SPI_RD_SR_POPNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_POPNXTPTR_MASK) >> SPI_SR_POPNXTPTR_SHIFT)
+#define SPI_BRD_SR_POPNXTPTR(base) (SPI_RD_SR_POPNXTPTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RXCTR[7:4] (RO)
+ *
+ * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
+ * every time the POPR is read. The RXCTR is incremented every time data is
+ * transferred from the shift register to the RX FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RXCTR field. */
+#define SPI_RD_SR_RXCTR(base) ((SPI_SR_REG(base) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT)
+#define SPI_BRD_SR_RXCTR(base) (SPI_RD_SR_RXCTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
+ *
+ * Indicates which TX FIFO entry is transmitted during the next transfer. The
+ * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
+ * the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXNXTPTR field. */
+#define SPI_RD_SR_TXNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_TXNXTPTR_MASK) >> SPI_SR_TXNXTPTR_SHIFT)
+#define SPI_BRD_SR_TXNXTPTR(base) (SPI_RD_SR_TXNXTPTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXCTR[15:12] (RO)
+ *
+ * Indicates the number of valid entries in the TX FIFO. The TXCTR is
+ * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
+ * command is executed and the SPI data is transferred to the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXCTR field. */
+#define SPI_RD_SR_TXCTR(base) ((SPI_SR_REG(base) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT)
+#define SPI_BRD_SR_TXCTR(base) (SPI_RD_SR_TXCTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RFDF[17] (W1C)
+ *
+ * Provides a method for the module to request that entries be removed from the
+ * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller when
+ * the RX FIFO is empty.
+ *
+ * Values:
+ * - 0b0 - RX FIFO is empty.
+ * - 0b1 - RX FIFO is not empty.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RFDF field. */
+#define SPI_RD_SR_RFDF(base) ((SPI_SR_REG(base) & SPI_SR_RFDF_MASK) >> SPI_SR_RFDF_SHIFT)
+#define SPI_BRD_SR_RFDF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT))
+
+/*! @brief Set the RFDF field to a new value. */
+#define SPI_WR_SR_RFDF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFDF(value)))
+#define SPI_BWR_SR_RFDF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RFOF[19] (W1C)
+ *
+ * Indicates an overflow condition in the RX FIFO. The field is set when the RX
+ * FIFO and shift register are full and a transfer is initiated. The bit remains
+ * set until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - No Rx FIFO overflow.
+ * - 0b1 - Rx FIFO overflow has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RFOF field. */
+#define SPI_RD_SR_RFOF(base) ((SPI_SR_REG(base) & SPI_SR_RFOF_MASK) >> SPI_SR_RFOF_SHIFT)
+#define SPI_BRD_SR_RFOF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT))
+
+/*! @brief Set the RFOF field to a new value. */
+#define SPI_WR_SR_RFOF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFOF(value)))
+#define SPI_BWR_SR_RFOF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TFFF[25] (W1C)
+ *
+ * Provides a method for the module to request more entries to be added to the
+ * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller to
+ * the TX FIFO full request.
+ *
+ * Values:
+ * - 0b0 - TX FIFO is full.
+ * - 0b1 - TX FIFO is not full.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TFFF field. */
+#define SPI_RD_SR_TFFF(base) ((SPI_SR_REG(base) & SPI_SR_TFFF_MASK) >> SPI_SR_TFFF_SHIFT)
+#define SPI_BRD_SR_TFFF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT))
+
+/*! @brief Set the TFFF field to a new value. */
+#define SPI_WR_SR_TFFF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFFF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFFF(value)))
+#define SPI_BWR_SR_TFFF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TFUF[27] (W1C)
+ *
+ * Indicates an underflow condition in the TX FIFO. The transmit underflow
+ * condition is detected only for SPI blocks operating in Slave mode and SPI
+ * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
+ * is empty and an external SPI master initiates a transfer. The TFUF bit remains
+ * set until cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No TX FIFO underflow.
+ * - 0b1 - TX FIFO underflow has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TFUF field. */
+#define SPI_RD_SR_TFUF(base) ((SPI_SR_REG(base) & SPI_SR_TFUF_MASK) >> SPI_SR_TFUF_SHIFT)
+#define SPI_BRD_SR_TFUF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT))
+
+/*! @brief Set the TFUF field to a new value. */
+#define SPI_WR_SR_TFUF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFUF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFUF(value)))
+#define SPI_BWR_SR_TFUF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field EOQF[28] (W1C)
+ *
+ * Indicates that the last entry in a queue has been transmitted when the module
+ * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
+ * set in the command halfword and the end of the transfer is reached. The EOQF
+ * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
+ * the TXRXS bit is automatically cleared.
+ *
+ * Values:
+ * - 0b0 - EOQ is not set in the executing command.
+ * - 0b1 - EOQ is set in the executing SPI command.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_EOQF field. */
+#define SPI_RD_SR_EOQF(base) ((SPI_SR_REG(base) & SPI_SR_EOQF_MASK) >> SPI_SR_EOQF_SHIFT)
+#define SPI_BRD_SR_EOQF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT))
+
+/*! @brief Set the EOQF field to a new value. */
+#define SPI_WR_SR_EOQF(base, value) (SPI_RMW_SR(base, (SPI_SR_EOQF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_EOQF(value)))
+#define SPI_BWR_SR_EOQF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXRXS[30] (W1C)
+ *
+ * Reflects the run status of the module.
+ *
+ * Values:
+ * - 0b0 - Transmit and receive operations are disabled (The module is in
+ *     Stopped state).
+ * - 0b1 - Transmit and receive operations are enabled (The module is in Running
+ *     state).
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXRXS field. */
+#define SPI_RD_SR_TXRXS(base) ((SPI_SR_REG(base) & SPI_SR_TXRXS_MASK) >> SPI_SR_TXRXS_SHIFT)
+#define SPI_BRD_SR_TXRXS(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT))
+
+/*! @brief Set the TXRXS field to a new value. */
+#define SPI_WR_SR_TXRXS(base, value) (SPI_RMW_SR(base, (SPI_SR_TXRXS_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TCF_MASK), SPI_SR_TXRXS(value)))
+#define SPI_BWR_SR_TXRXS(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TCF[31] (W1C)
+ *
+ * Indicates that all bits in a frame have been shifted out. TCF remains set
+ * until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - Transfer not complete.
+ * - 0b1 - Transfer complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TCF field. */
+#define SPI_RD_SR_TCF(base)  ((SPI_SR_REG(base) & SPI_SR_TCF_MASK) >> SPI_SR_TCF_SHIFT)
+#define SPI_BRD_SR_TCF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT))
+
+/*! @brief Set the TCF field to a new value. */
+#define SPI_WR_SR_TCF(base, value) (SPI_RMW_SR(base, (SPI_SR_TCF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK), SPI_SR_TCF(value)))
+#define SPI_BWR_SR_TCF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RSER controls DMA and interrupt requests. Do not write to the RSER while the
+ * module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RSER register
+ */
+/*@{*/
+#define SPI_RD_RSER(base)        (SPI_RSER_REG(base))
+#define SPI_WR_RSER(base, value) (SPI_RSER_REG(base) = (value))
+#define SPI_RMW_RSER(base, mask, value) (SPI_WR_RSER(base, (SPI_RD_RSER(base) & ~(mask)) | (value)))
+#define SPI_SET_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) |  (value)))
+#define SPI_CLR_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) & ~(value)))
+#define SPI_TOG_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_RSER bitfields
+ */
+
+/*!
+ * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When the
+ * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
+ * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - Interrupt request.
+ * - 0b1 - DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */
+#define SPI_RD_RSER_RFDF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_DIRS_MASK) >> SPI_RSER_RFDF_DIRS_SHIFT)
+#define SPI_BRD_RSER_RFDF_DIRS(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT))
+
+/*! @brief Set the RFDF_DIRS field to a new value. */
+#define SPI_WR_RSER_RFDF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_DIRS_MASK, SPI_RSER_RFDF_DIRS(value)))
+#define SPI_BWR_RSER_RFDF_DIRS(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field RFDF_RE[17] (RW)
+ *
+ * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - RFDF interrupt or DMA requests are disabled.
+ * - 0b1 - RFDF interrupt or DMA requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFDF_RE field. */
+#define SPI_RD_RSER_RFDF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_RE_MASK) >> SPI_RSER_RFDF_RE_SHIFT)
+#define SPI_BRD_RSER_RFDF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT))
+
+/*! @brief Set the RFDF_RE field to a new value. */
+#define SPI_WR_RSER_RFDF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_RE_MASK, SPI_RSER_RFDF_RE(value)))
+#define SPI_BWR_RSER_RFDF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field RFOF_RE[19] (RW)
+ *
+ * Enables the RFOF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - RFOF interrupt requests are disabled.
+ * - 0b1 - RFOF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFOF_RE field. */
+#define SPI_RD_RSER_RFOF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFOF_RE_MASK) >> SPI_RSER_RFOF_RE_SHIFT)
+#define SPI_BRD_RSER_RFOF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT))
+
+/*! @brief Set the RFOF_RE field to a new value. */
+#define SPI_WR_RSER_RFOF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFOF_RE_MASK, SPI_RSER_RFOF_RE(value)))
+#define SPI_BWR_RSER_RFOF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When
+ * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
+ * interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - TFFF flag generates interrupt requests.
+ * - 0b1 - TFFF flag generates DMA requests.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */
+#define SPI_RD_RSER_TFFF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_DIRS_MASK) >> SPI_RSER_TFFF_DIRS_SHIFT)
+#define SPI_BRD_RSER_TFFF_DIRS(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT))
+
+/*! @brief Set the TFFF_DIRS field to a new value. */
+#define SPI_WR_RSER_TFFF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_DIRS_MASK, SPI_RSER_TFFF_DIRS(value)))
+#define SPI_BWR_RSER_TFFF_DIRS(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFFF_RE[25] (RW)
+ *
+ * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - TFFF interrupts or DMA requests are disabled.
+ * - 0b1 - TFFF interrupts or DMA requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFFF_RE field. */
+#define SPI_RD_RSER_TFFF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_RE_MASK) >> SPI_RSER_TFFF_RE_SHIFT)
+#define SPI_BRD_RSER_TFFF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT))
+
+/*! @brief Set the TFFF_RE field to a new value. */
+#define SPI_WR_RSER_TFFF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_RE_MASK, SPI_RSER_TFFF_RE(value)))
+#define SPI_BWR_RSER_TFFF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFUF_RE[27] (RW)
+ *
+ * Enables the TFUF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - TFUF interrupt requests are disabled.
+ * - 0b1 - TFUF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFUF_RE field. */
+#define SPI_RD_RSER_TFUF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFUF_RE_MASK) >> SPI_RSER_TFUF_RE_SHIFT)
+#define SPI_BRD_RSER_TFUF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT))
+
+/*! @brief Set the TFUF_RE field to a new value. */
+#define SPI_WR_RSER_TFUF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFUF_RE_MASK, SPI_RSER_TFUF_RE(value)))
+#define SPI_BWR_RSER_TFUF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field EOQF_RE[28] (RW)
+ *
+ * Enables the EOQF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - EOQF interrupt requests are disabled.
+ * - 0b1 - EOQF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_EOQF_RE field. */
+#define SPI_RD_RSER_EOQF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_EOQF_RE_MASK) >> SPI_RSER_EOQF_RE_SHIFT)
+#define SPI_BRD_RSER_EOQF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT))
+
+/*! @brief Set the EOQF_RE field to a new value. */
+#define SPI_WR_RSER_EOQF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_EOQF_RE_MASK, SPI_RSER_EOQF_RE(value)))
+#define SPI_BWR_RSER_EOQF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TCF_RE[31] (RW)
+ *
+ * Enables TCF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - TCF interrupt requests are disabled.
+ * - 0b1 - TCF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TCF_RE field. */
+#define SPI_RD_RSER_TCF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TCF_RE_MASK) >> SPI_RSER_TCF_RE_SHIFT)
+#define SPI_BRD_RSER_TCF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT))
+
+/*! @brief Set the TCF_RE field to a new value. */
+#define SPI_WR_RSER_TCF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TCF_RE_MASK, SPI_RSER_TCF_RE(value)))
+#define SPI_BWR_RSER_TCF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
+ * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
+ * can be used as data, supporting up to 32-bit frame operation. A read access
+ * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
+ * writing to this register does not update the FIFO. Therefore, any reads performed
+ * while the module is disabled return the last PUSHR write performed while the
+ * module was still enabled.
+ */
+/*!
+ * @name Constants and macros for entire SPI_PUSHR register
+ */
+/*@{*/
+#define SPI_RD_PUSHR(base)       (SPI_PUSHR_REG(base))
+#define SPI_WR_PUSHR(base, value) (SPI_PUSHR_REG(base) = (value))
+#define SPI_RMW_PUSHR(base, mask, value) (SPI_WR_PUSHR(base, (SPI_RD_PUSHR(base) & ~(mask)) | (value)))
+#define SPI_SET_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) |  (value)))
+#define SPI_CLR_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) & ~(value)))
+#define SPI_TOG_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_PUSHR bitfields
+ */
+
+/*!
+ * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
+ *
+ * Holds SPI data to be transferred according to the associated SPI command.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_TXDATA field. */
+#define SPI_RD_PUSHR_TXDATA(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_TXDATA_MASK) >> SPI_PUSHR_TXDATA_SHIFT)
+#define SPI_BRD_PUSHR_TXDATA(base) (SPI_RD_PUSHR_TXDATA(base))
+
+/*! @brief Set the TXDATA field to a new value. */
+#define SPI_WR_PUSHR_TXDATA(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_TXDATA_MASK, SPI_PUSHR_TXDATA(value)))
+#define SPI_BWR_PUSHR_TXDATA(base, value) (SPI_WR_PUSHR_TXDATA(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field PCS[21:16] (RW)
+ *
+ * Select which PCS signals are to be asserted for the transfer. Refer to the
+ * chip configuration details for the number of PCS signals used in this MCU.
+ *
+ * Values:
+ * - 0b000000 - Negate the PCS[x] signal.
+ * - 0b000001 - Assert the PCS[x] signal.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_PCS field. */
+#define SPI_RD_PUSHR_PCS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_PCS_MASK) >> SPI_PUSHR_PCS_SHIFT)
+#define SPI_BRD_PUSHR_PCS(base) (SPI_RD_PUSHR_PCS(base))
+
+/*! @brief Set the PCS field to a new value. */
+#define SPI_WR_PUSHR_PCS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_PCS_MASK, SPI_PUSHR_PCS(value)))
+#define SPI_BWR_PUSHR_PCS(base, value) (SPI_WR_PUSHR_PCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CTCNT[26] (RW)
+ *
+ * Clears the TCNT field in the TCR register. The TCNT field is cleared before
+ * the module starts transmitting the current SPI frame.
+ *
+ * Values:
+ * - 0b0 - Do not clear the TCR[TCNT] field.
+ * - 0b1 - Clear the TCR[TCNT] field.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CTCNT field. */
+#define SPI_RD_PUSHR_CTCNT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTCNT_MASK) >> SPI_PUSHR_CTCNT_SHIFT)
+#define SPI_BRD_PUSHR_CTCNT(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT))
+
+/*! @brief Set the CTCNT field to a new value. */
+#define SPI_WR_PUSHR_CTCNT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTCNT_MASK, SPI_PUSHR_CTCNT(value)))
+#define SPI_BWR_PUSHR_CTCNT(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field EOQ[27] (RW)
+ *
+ * Host software uses this bit to signal to the module that the current SPI
+ * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
+ * SR is set.
+ *
+ * Values:
+ * - 0b0 - The SPI data is not the last data to transfer.
+ * - 0b1 - The SPI data is the last data to transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_EOQ field. */
+#define SPI_RD_PUSHR_EOQ(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_EOQ_MASK) >> SPI_PUSHR_EOQ_SHIFT)
+#define SPI_BRD_PUSHR_EOQ(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT))
+
+/*! @brief Set the EOQ field to a new value. */
+#define SPI_WR_PUSHR_EOQ(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_EOQ_MASK, SPI_PUSHR_EOQ(value)))
+#define SPI_BWR_PUSHR_EOQ(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
+ *
+ * Selects which CTAR to use in master mode to specify the transfer attributes
+ * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
+ * configuration details to determine how many CTARs this device has. You should
+ * not program a value in this field for a register that is not present.
+ *
+ * Values:
+ * - 0b000 - CTAR0
+ * - 0b001 - CTAR1
+ * - 0b010 - Reserved
+ * - 0b011 - Reserved
+ * - 0b100 - Reserved
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CTAS field. */
+#define SPI_RD_PUSHR_CTAS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTAS_MASK) >> SPI_PUSHR_CTAS_SHIFT)
+#define SPI_BRD_PUSHR_CTAS(base) (SPI_RD_PUSHR_CTAS(base))
+
+/*! @brief Set the CTAS field to a new value. */
+#define SPI_WR_PUSHR_CTAS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTAS_MASK, SPI_PUSHR_CTAS(value)))
+#define SPI_BWR_PUSHR_CTAS(base, value) (SPI_WR_PUSHR_CTAS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CONT[31] (RW)
+ *
+ * Selects a continuous selection format. The bit is used in SPI Master mode.
+ * The bit enables the selected PCS signals to remain asserted between transfers.
+ *
+ * Values:
+ * - 0b0 - Return PCSn signals to their inactive state between transfers.
+ * - 0b1 - Keep PCSn signals asserted between transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CONT field. */
+#define SPI_RD_PUSHR_CONT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CONT_MASK) >> SPI_PUSHR_CONT_SHIFT)
+#define SPI_BRD_PUSHR_CONT(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT))
+
+/*! @brief Set the CONT field to a new value. */
+#define SPI_WR_PUSHR_CONT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CONT_MASK, SPI_PUSHR_CONT(value)))
+#define SPI_BWR_PUSHR_CONT(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
+ * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
+ * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
+ * SPI Frame operation.
+ */
+/*!
+ * @name Constants and macros for entire SPI_PUSHR_SLAVE register
+ */
+/*@{*/
+#define SPI_RD_PUSHR_SLAVE(base) (SPI_PUSHR_SLAVE_REG(base))
+#define SPI_WR_PUSHR_SLAVE(base, value) (SPI_PUSHR_SLAVE_REG(base) = (value))
+#define SPI_RMW_PUSHR_SLAVE(base, mask, value) (SPI_WR_PUSHR_SLAVE(base, (SPI_RD_PUSHR_SLAVE(base) & ~(mask)) | (value)))
+#define SPI_SET_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) |  (value)))
+#define SPI_CLR_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) & ~(value)))
+#define SPI_TOG_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_POPR - POP RX FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_POPR - POP RX FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
+ * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
+ * this register will generate a Transfer Error.
+ */
+/*!
+ * @name Constants and macros for entire SPI_POPR register
+ */
+/*@{*/
+#define SPI_RD_POPR(base)        (SPI_POPR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR0 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR0 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR0 register
+ */
+/*@{*/
+#define SPI_RD_TXFR0(base)       (SPI_TXFR0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR0 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR0, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR0_TXDATA field. */
+#define SPI_RD_TXFR0_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXDATA_MASK) >> SPI_TXFR0_TXDATA_SHIFT)
+#define SPI_BRD_TXFR0_TXDATA(base) (SPI_RD_TXFR0_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR0, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR0_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR0_TXCMD_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXCMD_TXDATA_MASK) >> SPI_TXFR0_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR0_TXCMD_TXDATA(base) (SPI_RD_TXFR0_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR1 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR1 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR1 register
+ */
+/*@{*/
+#define SPI_RD_TXFR1(base)       (SPI_TXFR1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR1 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR1, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR1_TXDATA field. */
+#define SPI_RD_TXFR1_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXDATA_MASK) >> SPI_TXFR1_TXDATA_SHIFT)
+#define SPI_BRD_TXFR1_TXDATA(base) (SPI_RD_TXFR1_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR1, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR1_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR1_TXCMD_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXCMD_TXDATA_MASK) >> SPI_TXFR1_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR1_TXCMD_TXDATA(base) (SPI_RD_TXFR1_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR2 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR2 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR2 register
+ */
+/*@{*/
+#define SPI_RD_TXFR2(base)       (SPI_TXFR2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR2 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR2, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR2_TXDATA field. */
+#define SPI_RD_TXFR2_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXDATA_MASK) >> SPI_TXFR2_TXDATA_SHIFT)
+#define SPI_BRD_TXFR2_TXDATA(base) (SPI_RD_TXFR2_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR2, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR2_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR2_TXCMD_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXCMD_TXDATA_MASK) >> SPI_TXFR2_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR2_TXCMD_TXDATA(base) (SPI_RD_TXFR2_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR3 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR3 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR3 register
+ */
+/*@{*/
+#define SPI_RD_TXFR3(base)       (SPI_TXFR3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR3 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR3, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR3_TXDATA field. */
+#define SPI_RD_TXFR3_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXDATA_MASK) >> SPI_TXFR3_TXDATA_SHIFT)
+#define SPI_BRD_TXFR3_TXDATA(base) (SPI_RD_TXFR3_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR3, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR3_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR3_TXCMD_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXCMD_TXDATA_MASK) >> SPI_TXFR3_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR3_TXCMD_TXDATA(base) (SPI_RD_TXFR3_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR0 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR0 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR0 register
+ */
+/*@{*/
+#define SPI_RD_RXFR0(base)       (SPI_RXFR0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR1 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR1 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR1 register
+ */
+/*@{*/
+#define SPI_RD_RXFR1(base)       (SPI_RXFR1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR2 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR2 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR2 register
+ */
+/*@{*/
+#define SPI_RD_RXFR2(base)       (SPI_RXFR2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR3 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR3 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR3 register
+ */
+/*@{*/
+#define SPI_RD_RXFR3(base)       (SPI_RXFR3_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 UART
+ *
+ * Serial Communication Interface
+ *
+ * Registers defined in this header file:
+ * - UART_BDH - UART Baud Rate Registers: High
+ * - UART_BDL - UART Baud Rate Registers: Low
+ * - UART_C1 - UART Control Register 1
+ * - UART_C2 - UART Control Register 2
+ * - UART_S1 - UART Status Register 1
+ * - UART_S2 - UART Status Register 2
+ * - UART_C3 - UART Control Register 3
+ * - UART_D - UART Data Register
+ * - UART_MA1 - UART Match Address Registers 1
+ * - UART_MA2 - UART Match Address Registers 2
+ * - UART_C4 - UART Control Register 4
+ * - UART_C5 - UART Control Register 5
+ * - UART_ED - UART Extended Data Register
+ * - UART_MODEM - UART Modem Register
+ * - UART_IR - UART Infrared Register
+ * - UART_PFIFO - UART FIFO Parameters
+ * - UART_CFIFO - UART FIFO Control Register
+ * - UART_SFIFO - UART FIFO Status Register
+ * - UART_TWFIFO - UART FIFO Transmit Watermark
+ * - UART_TCFIFO - UART FIFO Transmit Count
+ * - UART_RWFIFO - UART FIFO Receive Watermark
+ * - UART_RCFIFO - UART FIFO Receive Count
+ * - UART_C7816 - UART 7816 Control Register
+ * - UART_IE7816 - UART 7816 Interrupt Enable Register
+ * - UART_IS7816 - UART 7816 Interrupt Status Register
+ * - UART_WP7816T0 - UART 7816 Wait Parameter Register
+ * - UART_WP7816T1 - UART 7816 Wait Parameter Register
+ * - UART_WN7816 - UART 7816 Wait N Register
+ * - UART_WF7816 - UART 7816 Wait FD Register
+ * - UART_ET7816 - UART 7816 Error Threshold Register
+ * - UART_TL7816 - UART 7816 Transmit Length Register
+ */
+
+#define UART_INSTANCE_COUNT (6U) /*!< Number of instances of the UART module. */
+#define UART0_IDX (0U) /*!< Instance number for UART0. */
+#define UART1_IDX (1U) /*!< Instance number for UART1. */
+#define UART2_IDX (2U) /*!< Instance number for UART2. */
+#define UART3_IDX (3U) /*!< Instance number for UART3. */
+#define UART4_IDX (4U) /*!< Instance number for UART4. */
+#define UART5_IDX (5U) /*!< Instance number for UART5. */
+
+/*******************************************************************************
+ * UART_BDH - UART Baud Rate Registers: High
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDH - UART Baud Rate Registers: High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register, along with the BDL register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting
+ * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
+ * to BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is,
+ * when C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDH register
+ */
+/*@{*/
+#define UART_RD_BDH(base)        (UART_BDH_REG(base))
+#define UART_WR_BDH(base, value) (UART_BDH_REG(base) = (value))
+#define UART_RMW_BDH(base, mask, value) (UART_WR_BDH(base, (UART_RD_BDH(base) & ~(mask)) | (value)))
+#define UART_SET_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) |  (value)))
+#define UART_CLR_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) & ~(value)))
+#define UART_TOG_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_BDH bitfields
+ */
+
+/*!
+ * @name Register UART_BDH, field SBR[4:0] (RW)
+ *
+ * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
+ * generation for details. The baud rate generator is disabled until C2[TE] or
+ * C2[RE] is set for the first time after reset.The baud rate generator is disabled
+ * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
+ * writing to BDH puts the data in a temporary location until BDL is written.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBR field. */
+#define UART_RD_BDH_SBR(base) ((UART_BDH_REG(base) & UART_BDH_SBR_MASK) >> UART_BDH_SBR_SHIFT)
+#define UART_BRD_BDH_SBR(base) (UART_RD_BDH_SBR(base))
+
+/*! @brief Set the SBR field to a new value. */
+#define UART_WR_BDH_SBR(base, value) (UART_RMW_BDH(base, UART_BDH_SBR_MASK, UART_BDH_SBR(value)))
+#define UART_BWR_BDH_SBR(base, value) (UART_WR_BDH_SBR(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field SBNS[5] (RW)
+ *
+ * SBNS selects the number of stop bits present in a data frame. This field
+ * valid for all 8, 9 and 10 bit data formats available. This field is not valid when
+ * C7816[ISO7816E] is enabled.
+ *
+ * Values:
+ * - 0b0 - Data frame consists of a single stop bit.
+ * - 0b1 - Data frame consists of two stop bits.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBNS field. */
+#define UART_RD_BDH_SBNS(base) ((UART_BDH_REG(base) & UART_BDH_SBNS_MASK) >> UART_BDH_SBNS_SHIFT)
+#define UART_BRD_BDH_SBNS(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_SBNS_SHIFT))
+
+/*! @brief Set the SBNS field to a new value. */
+#define UART_WR_BDH_SBNS(base, value) (UART_RMW_BDH(base, UART_BDH_SBNS_MASK, UART_BDH_SBNS(value)))
+#define UART_BWR_BDH_SBNS(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_SBNS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field RXEDGIE[6] (RW)
+ *
+ * Enables the receive input active edge, RXEDGIF, to generate interrupt
+ * requests.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupts from RXEDGIF disabled using polling.
+ * - 0b1 - RXEDGIF interrupt request enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_RXEDGIE field. */
+#define UART_RD_BDH_RXEDGIE(base) ((UART_BDH_REG(base) & UART_BDH_RXEDGIE_MASK) >> UART_BDH_RXEDGIE_SHIFT)
+#define UART_BRD_BDH_RXEDGIE(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT))
+
+/*! @brief Set the RXEDGIE field to a new value. */
+#define UART_WR_BDH_RXEDGIE(base, value) (UART_RMW_BDH(base, UART_BDH_RXEDGIE_MASK, UART_BDH_RXEDGIE(value)))
+#define UART_BWR_BDH_RXEDGIE(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field LBKDIE[7] (RW)
+ *
+ * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
+ * based on the state of LBKDDMAS. or DMA transfer requests,
+ *
+ * Values:
+ * - 0b0 - LBKDIF interrupt and DMA transfer requests disabled.
+ * - 0b1 - LBKDIF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_LBKDIE field. */
+#define UART_RD_BDH_LBKDIE(base) ((UART_BDH_REG(base) & UART_BDH_LBKDIE_MASK) >> UART_BDH_LBKDIE_SHIFT)
+#define UART_BRD_BDH_LBKDIE(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_LBKDIE_SHIFT))
+
+/*! @brief Set the LBKDIE field to a new value. */
+#define UART_WR_BDH_LBKDIE(base, value) (UART_RMW_BDH(base, UART_BDH_LBKDIE_MASK, UART_BDH_LBKDIE(value)))
+#define UART_BWR_BDH_LBKDIE(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_LBKDIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_BDL - UART Baud Rate Registers: Low
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDL - UART Baud Rate Registers: Low (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * This register, along with the BDH register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
+ * first write to BDH to buffer the high half of the new value and then write to
+ * BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is, when
+ * C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDL register
+ */
+/*@{*/
+#define UART_RD_BDL(base)        (UART_BDL_REG(base))
+#define UART_WR_BDL(base, value) (UART_BDL_REG(base) = (value))
+#define UART_RMW_BDL(base, mask, value) (UART_WR_BDL(base, (UART_RD_BDL(base) & ~(mask)) | (value)))
+#define UART_SET_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) |  (value)))
+#define UART_CLR_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) & ~(value)))
+#define UART_TOG_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C1 - UART Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C1 - UART Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This read/write register controls various optional features of the UART
+ * system.
+ */
+/*!
+ * @name Constants and macros for entire UART_C1 register
+ */
+/*@{*/
+#define UART_RD_C1(base)         (UART_C1_REG(base))
+#define UART_WR_C1(base, value)  (UART_C1_REG(base) = (value))
+#define UART_RMW_C1(base, mask, value) (UART_WR_C1(base, (UART_RD_C1(base) & ~(mask)) | (value)))
+#define UART_SET_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) |  (value)))
+#define UART_CLR_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) & ~(value)))
+#define UART_TOG_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C1 bitfields
+ */
+
+/*!
+ * @name Register UART_C1, field PT[0] (RW)
+ *
+ * Determines whether the UART generates and checks for even parity or odd
+ * parity. With even parity, an even number of 1s clears the parity bit and an odd
+ * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
+ * parity bit and an even number of 1s sets the parity bit. This field must be
+ * cleared when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Even parity.
+ * - 0b1 - Odd parity.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PT field. */
+#define UART_RD_C1_PT(base)  ((UART_C1_REG(base) & UART_C1_PT_MASK) >> UART_C1_PT_SHIFT)
+#define UART_BRD_C1_PT(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PT_SHIFT))
+
+/*! @brief Set the PT field to a new value. */
+#define UART_WR_C1_PT(base, value) (UART_RMW_C1(base, UART_C1_PT_MASK, UART_C1_PT(value)))
+#define UART_BWR_C1_PT(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field PE[1] (RW)
+ *
+ * Enables the parity function. When parity is enabled, parity function inserts
+ * a parity bit in the bit position immediately preceding the stop bit. This
+ * field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Parity function disabled.
+ * - 0b1 - Parity function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PE field. */
+#define UART_RD_C1_PE(base)  ((UART_C1_REG(base) & UART_C1_PE_MASK) >> UART_C1_PE_SHIFT)
+#define UART_BRD_C1_PE(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PE_SHIFT))
+
+/*! @brief Set the PE field to a new value. */
+#define UART_WR_C1_PE(base, value) (UART_RMW_C1(base, UART_C1_PE_MASK, UART_C1_PE(value)))
+#define UART_BWR_C1_PE(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field ILT[2] (RW)
+ *
+ * Determines when the receiver starts counting logic 1s as idle character bits.
+ * The count begins either after a valid start bit or after the stop bit. If the
+ * count begins after the start bit, then a string of logic 1s preceding the
+ * stop bit can cause false recognition of an idle character. Beginning the count
+ * after the stop bit avoids false idle character recognition, but requires
+ * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
+ * logic of 1'b0 is automatically shifted after a received stop bit, therefore
+ * resetting the idle count. In case the UART is programmed for IDLE line wakeup
+ * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
+ * logic 1s as idle character bits. In idle line wakeup, an idle character is
+ * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
+ * and C4[M10] fields.
+ *
+ * Values:
+ * - 0b0 - Idle character bit count starts after start bit.
+ * - 0b1 - Idle character bit count starts after stop bit.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_ILT field. */
+#define UART_RD_C1_ILT(base) ((UART_C1_REG(base) & UART_C1_ILT_MASK) >> UART_C1_ILT_SHIFT)
+#define UART_BRD_C1_ILT(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_ILT_SHIFT))
+
+/*! @brief Set the ILT field to a new value. */
+#define UART_WR_C1_ILT(base, value) (UART_RMW_C1(base, UART_C1_ILT_MASK, UART_C1_ILT(value)))
+#define UART_BWR_C1_ILT(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_ILT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field WAKE[3] (RW)
+ *
+ * Determines which condition wakes the UART: Address mark in the most
+ * significant bit position of a received data character, or An idle condition on the
+ * receive pin input signal.
+ *
+ * Values:
+ * - 0b0 - Idle line wakeup.
+ * - 0b1 - Address mark wakeup.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_WAKE field. */
+#define UART_RD_C1_WAKE(base) ((UART_C1_REG(base) & UART_C1_WAKE_MASK) >> UART_C1_WAKE_SHIFT)
+#define UART_BRD_C1_WAKE(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT))
+
+/*! @brief Set the WAKE field to a new value. */
+#define UART_WR_C1_WAKE(base, value) (UART_RMW_C1(base, UART_C1_WAKE_MASK, UART_C1_WAKE(value)))
+#define UART_BWR_C1_WAKE(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field M[4] (RW)
+ *
+ * This field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) +
+ *     stop.
+ * - 0b1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_M field. */
+#define UART_RD_C1_M(base)   ((UART_C1_REG(base) & UART_C1_M_MASK) >> UART_C1_M_SHIFT)
+#define UART_BRD_C1_M(base)  (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_M_SHIFT))
+
+/*! @brief Set the M field to a new value. */
+#define UART_WR_C1_M(base, value) (UART_RMW_C1(base, UART_C1_M_MASK, UART_C1_M(value)))
+#define UART_BWR_C1_M(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_M_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field RSRC[5] (RW)
+ *
+ * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
+ * is set, the RSRC field determines the source for the receiver shift register
+ * input.
+ *
+ * Values:
+ * - 0b0 - Selects internal loop back mode. The receiver input is internally
+ *     connected to transmitter output.
+ * - 0b1 - Single wire UART mode where the receiver input is connected to the
+ *     transmit pin input signal.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_RSRC field. */
+#define UART_RD_C1_RSRC(base) ((UART_C1_REG(base) & UART_C1_RSRC_MASK) >> UART_C1_RSRC_SHIFT)
+#define UART_BRD_C1_RSRC(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT))
+
+/*! @brief Set the RSRC field to a new value. */
+#define UART_WR_C1_RSRC(base, value) (UART_RMW_C1(base, UART_C1_RSRC_MASK, UART_C1_RSRC(value)))
+#define UART_BWR_C1_RSRC(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field UARTSWAI[6] (RW)
+ *
+ * Values:
+ * - 0b0 - UART clock continues to run in Wait mode.
+ * - 0b1 - UART clock freezes while CPU is in Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_UARTSWAI field. */
+#define UART_RD_C1_UARTSWAI(base) ((UART_C1_REG(base) & UART_C1_UARTSWAI_MASK) >> UART_C1_UARTSWAI_SHIFT)
+#define UART_BRD_C1_UARTSWAI(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_UARTSWAI_SHIFT))
+
+/*! @brief Set the UARTSWAI field to a new value. */
+#define UART_WR_C1_UARTSWAI(base, value) (UART_RMW_C1(base, UART_C1_UARTSWAI_MASK, UART_C1_UARTSWAI(value)))
+#define UART_BWR_C1_UARTSWAI(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_UARTSWAI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field LOOPS[7] (RW)
+ *
+ * When LOOPS is set, the RxD pin is disconnected from the UART and the
+ * transmitter output is internally connected to the receiver input. The transmitter and
+ * the receiver must be enabled to use the loop function.
+ *
+ * Values:
+ * - 0b0 - Normal operation.
+ * - 0b1 - Loop mode where transmitter output is internally connected to
+ *     receiver input. The receiver input is determined by RSRC.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_LOOPS field. */
+#define UART_RD_C1_LOOPS(base) ((UART_C1_REG(base) & UART_C1_LOOPS_MASK) >> UART_C1_LOOPS_SHIFT)
+#define UART_BRD_C1_LOOPS(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT))
+
+/*! @brief Set the LOOPS field to a new value. */
+#define UART_WR_C1_LOOPS(base, value) (UART_RMW_C1(base, UART_C1_LOOPS_MASK, UART_C1_LOOPS(value)))
+#define UART_BWR_C1_LOOPS(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C2 - UART Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C2 - UART Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register can be read or written at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_C2 register
+ */
+/*@{*/
+#define UART_RD_C2(base)         (UART_C2_REG(base))
+#define UART_WR_C2(base, value)  (UART_C2_REG(base) = (value))
+#define UART_RMW_C2(base, mask, value) (UART_WR_C2(base, (UART_RD_C2(base) & ~(mask)) | (value)))
+#define UART_SET_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) |  (value)))
+#define UART_CLR_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) & ~(value)))
+#define UART_TOG_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C2 bitfields
+ */
+
+/*!
+ * @name Register UART_C2, field SBK[0] (RW)
+ *
+ * Toggling SBK sends one break character from the following: See Transmitting
+ * break characters for the number of logic 0s for the different configurations.
+ * Toggling implies clearing the SBK field before the break character has finished
+ * transmitting. As long as SBK is set, the transmitter continues to send
+ * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
+ * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
+ * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
+ * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
+ * C7816[ISO_7816E] is set.
+ *
+ * Values:
+ * - 0b0 - Normal transmitter operation.
+ * - 0b1 - Queue break characters to be sent.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_SBK field. */
+#define UART_RD_C2_SBK(base) ((UART_C2_REG(base) & UART_C2_SBK_MASK) >> UART_C2_SBK_SHIFT)
+#define UART_BRD_C2_SBK(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_SBK_SHIFT))
+
+/*! @brief Set the SBK field to a new value. */
+#define UART_WR_C2_SBK(base, value) (UART_RMW_C2(base, UART_C2_SBK_MASK, UART_C2_SBK(value)))
+#define UART_BWR_C2_SBK(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_SBK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RWU[1] (RW)
+ *
+ * This field can be set to place the UART receiver in a standby state. RWU
+ * automatically clears when an RWU event occurs, that is, an IDLE event when
+ * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
+ * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
+ * on idle) if the channel is currently not idle. This can be determined by
+ * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
+ * idle, it is possible that the UART will discard data. This is because the data
+ * must be received or a LIN break detected after an IDLE is detected before IDLE
+ * is allowed to reasserted.
+ *
+ * Values:
+ * - 0b0 - Normal operation.
+ * - 0b1 - RWU enables the wakeup function and inhibits further receiver
+ *     interrupt requests. Normally, hardware wakes the receiver by automatically
+ *     clearing RWU.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RWU field. */
+#define UART_RD_C2_RWU(base) ((UART_C2_REG(base) & UART_C2_RWU_MASK) >> UART_C2_RWU_SHIFT)
+#define UART_BRD_C2_RWU(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RWU_SHIFT))
+
+/*! @brief Set the RWU field to a new value. */
+#define UART_WR_C2_RWU(base, value) (UART_RMW_C2(base, UART_C2_RWU_MASK, UART_C2_RWU(value)))
+#define UART_BWR_C2_RWU(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RWU_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RE[2] (RW)
+ *
+ * Enables the UART receiver.
+ *
+ * Values:
+ * - 0b0 - Receiver off.
+ * - 0b1 - Receiver on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RE field. */
+#define UART_RD_C2_RE(base)  ((UART_C2_REG(base) & UART_C2_RE_MASK) >> UART_C2_RE_SHIFT)
+#define UART_BRD_C2_RE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RE_SHIFT))
+
+/*! @brief Set the RE field to a new value. */
+#define UART_WR_C2_RE(base, value) (UART_RMW_C2(base, UART_C2_RE_MASK, UART_C2_RE(value)))
+#define UART_BWR_C2_RE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TE[3] (RW)
+ *
+ * Enables the UART transmitter. TE can be used to queue an idle preamble by
+ * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
+ * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
+ * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
+ * additional characters are transmitted.
+ *
+ * Values:
+ * - 0b0 - Transmitter off.
+ * - 0b1 - Transmitter on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TE field. */
+#define UART_RD_C2_TE(base)  ((UART_C2_REG(base) & UART_C2_TE_MASK) >> UART_C2_TE_SHIFT)
+#define UART_BRD_C2_TE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TE_SHIFT))
+
+/*! @brief Set the TE field to a new value. */
+#define UART_WR_C2_TE(base, value) (UART_RMW_C2(base, UART_C2_TE_MASK, UART_C2_TE(value)))
+#define UART_BWR_C2_TE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field ILIE[4] (RW)
+ *
+ * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
+ * transfer requests based on the state of C5[ILDMAS].
+ *
+ * Values:
+ * - 0b0 - IDLE interrupt requests disabled. and DMA transfer
+ * - 0b1 - IDLE interrupt requests enabled. or DMA transfer
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_ILIE field. */
+#define UART_RD_C2_ILIE(base) ((UART_C2_REG(base) & UART_C2_ILIE_MASK) >> UART_C2_ILIE_SHIFT)
+#define UART_BRD_C2_ILIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT))
+
+/*! @brief Set the ILIE field to a new value. */
+#define UART_WR_C2_ILIE(base, value) (UART_RMW_C2(base, UART_C2_ILIE_MASK, UART_C2_ILIE(value)))
+#define UART_BWR_C2_ILIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RIE[5] (RW)
+ *
+ * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[RDMAS].
+ *
+ * Values:
+ * - 0b0 - RDRF interrupt and DMA transfer requests disabled.
+ * - 0b1 - RDRF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RIE field. */
+#define UART_RD_C2_RIE(base) ((UART_C2_REG(base) & UART_C2_RIE_MASK) >> UART_C2_RIE_SHIFT)
+#define UART_BRD_C2_RIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RIE_SHIFT))
+
+/*! @brief Set the RIE field to a new value. */
+#define UART_WR_C2_RIE(base, value) (UART_RMW_C2(base, UART_C2_RIE_MASK, UART_C2_RIE(value)))
+#define UART_BWR_C2_RIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TCIE[6] (RW)
+ *
+ * Enables the transmission complete flag, S1[TC], to generate interrupt
+ * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
+ * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
+ * written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0b0 - TC interrupt and DMA transfer requests disabled.
+ * - 0b1 - TC interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TCIE field. */
+#define UART_RD_C2_TCIE(base) ((UART_C2_REG(base) & UART_C2_TCIE_MASK) >> UART_C2_TCIE_SHIFT)
+#define UART_BRD_C2_TCIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT))
+
+/*! @brief Set the TCIE field to a new value. */
+#define UART_WR_C2_TCIE(base, value) (UART_RMW_C2(base, UART_C2_TCIE_MASK, UART_C2_TCIE(value)))
+#define UART_BWR_C2_TCIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TIE[7] (RW)
+ *
+ * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
+ * must be cleared, and D[D] must not be written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0b0 - TDRE interrupt and DMA transfer requests disabled.
+ * - 0b1 - TDRE interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TIE field. */
+#define UART_RD_C2_TIE(base) ((UART_C2_REG(base) & UART_C2_TIE_MASK) >> UART_C2_TIE_SHIFT)
+#define UART_BRD_C2_TIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define UART_WR_C2_TIE(base, value) (UART_RMW_C2(base, UART_C2_TIE_MASK, UART_C2_TIE(value)))
+#define UART_BWR_C2_TIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S1 - UART Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S1 - UART Status Register 1 (RO)
+ *
+ * Reset value: 0xC0U
+ *
+ * The S1 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. This register can also be polled by the MCU to check the
+ * status of its fields. To clear a flag, the status register should be read followed
+ * by a read or write to D register, depending on the interrupt flag type. Other
+ * instructions can be executed between the two steps as long the handling of
+ * I/O is not compromised, but the order of operations is important for flag
+ * clearing. When a flag is configured to trigger a DMA request, assertion of the
+ * associated DMA done signal from the DMA controller clears the flag. If the
+ * condition that results in the assertion of the flag, interrupt, or DMA request is not
+ * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
+ * reasserts. For example, if the DMA or interrupt service routine fails to write
+ * sufficient data to the transmit buffer to raise it above the watermark level, the
+ * flag reasserts and generates another interrupt or DMA request. Reading an
+ * empty data register to clear one of the flags of the S1 register causes the FIFO
+ * pointers to become misaligned. A receive FIFO flush reinitializes the
+ * pointers. A better way to prevent this situation is to always leave one byte in FIFO
+ * and this byte will be read eventually in clearing the flag bit.
+ */
+/*!
+ * @name Constants and macros for entire UART_S1 register
+ */
+/*@{*/
+#define UART_RD_S1(base)         (UART_S1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S1 bitfields
+ */
+
+/*!
+ * @name Register UART_S1, field PF[0] (RO)
+ *
+ * PF is set when PE is set and the parity of the received data does not match
+ * its parity bit. The PF is not set in the case of an overrun condition. When PF
+ * is set, it indicates only that a dataword was received with parity error since
+ * the last time it was cleared. There is no guarantee that the first dataword
+ * read from the receive buffer has a parity error or that there is only one
+ * dataword in the buffer that was received with a parity error, unless the receive
+ * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
+ * disabled, Within the receive buffer structure the received dataword is tagged
+ * if it is received with a parity error. This information is available by reading
+ * the ED register prior to reading the D register.
+ *
+ * Values:
+ * - 0b0 - No parity error detected since the last time this flag was cleared.
+ *     If the receive buffer has a depth greater than 1, then there may be data in
+ *     the receive buffer what was received with a parity error.
+ * - 0b1 - At least one dataword was received with a parity error since the last
+ *     time this flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_PF field. */
+#define UART_RD_S1_PF(base)  ((UART_S1_REG(base) & UART_S1_PF_MASK) >> UART_S1_PF_SHIFT)
+#define UART_BRD_S1_PF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_PF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field FE[1] (RO)
+ *
+ * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
+ * then FE will set when a logic 0 is accepted for either of the two stop bits.
+ * FE does not set in the case of an overrun or while the LIN break detect feature
+ * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
+ * cleared. To clear FE, read S1 with FE set and then read D. The last data in the
+ * receive buffer represents the data that was received with the frame error
+ * enabled. Framing errors are not supported when 7816E is set/enabled. However, if
+ * this flag is set, data is still not received in 7816 mode.
+ *
+ * Values:
+ * - 0b0 - No framing error detected.
+ * - 0b1 - Framing error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_FE field. */
+#define UART_RD_S1_FE(base)  ((UART_S1_REG(base) & UART_S1_FE_MASK) >> UART_S1_FE_SHIFT)
+#define UART_BRD_S1_FE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_FE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field NF[2] (RO)
+ *
+ * NF is set when the UART detects noise on the receiver input. NF does not
+ * become set in the case of an overrun or while the LIN break detect feature is
+ * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
+ * been received with noise since the last time it was cleared. There is no
+ * guarantee that the first dataword read from the receive buffer has noise or that there
+ * is only one dataword in the buffer that was received with noise unless the
+ * receive buffer has a depth of one. To clear NF, read S1 and then read D.
+ *
+ * Values:
+ * - 0b0 - No noise detected since the last time this flag was cleared. If the
+ *     receive buffer has a depth greater than 1 then there may be data in the
+ *     receiver buffer that was received with noise.
+ * - 0b1 - At least one dataword was received with noise detected since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_NF field. */
+#define UART_RD_S1_NF(base)  ((UART_S1_REG(base) & UART_S1_NF_MASK) >> UART_S1_NF_SHIFT)
+#define UART_BRD_S1_NF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_NF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field OR[3] (RO)
+ *
+ * OR is set when software fails to prevent the receive data register from
+ * overflowing with data. The OR bit is set immediately after the stop bit has been
+ * completely received for the dataword that overflows the buffer and all the other
+ * error flags (FE, NF, and PF) are prevented from setting. The data in the
+ * shift register is lost, but the data already in the UART data registers is not
+ * affected. If the OR flag is set, no data is stored in the data buffer even if
+ * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
+ * flags are blocked from asserting, that is, transition from an inactive to an
+ * active state. To clear OR, read S1 when OR is set and then read D. See
+ * functional description for more details regarding the operation of the OR bit.If
+ * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
+ * is not cleared before the next data character is received. In 7816 mode, it is
+ * possible to configure a NACK to be returned by programing C7816[ONACK].
+ *
+ * Values:
+ * - 0b0 - No overrun has occurred since the last time the flag was cleared.
+ * - 0b1 - Overrun has occurred or the overrun flag has not been cleared since
+ *     the last overrun occured.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_OR field. */
+#define UART_RD_S1_OR(base)  ((UART_S1_REG(base) & UART_S1_OR_MASK) >> UART_S1_OR_SHIFT)
+#define UART_BRD_S1_OR(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_OR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field IDLE[4] (RO)
+ *
+ * After the IDLE flag is cleared, a frame must be received (although not
+ * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
+ * break character must set the S2[LBKDIF] flag before an idle condition can set the
+ * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
+ * IDLE is set when either of the following appear on the receiver input: 10
+ * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
+ * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
+ * detection is not supported when 7816E is set/enabled and hence this flag is
+ * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
+ * flag if RWUID is set, else the IDLE flag does not become set.
+ *
+ * Values:
+ * - 0b0 - Receiver input is either active now or has never become active since
+ *     the IDLE flag was last cleared.
+ * - 0b1 - Receiver input has become idle or the flag has not been cleared since
+ *     it last asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_IDLE field. */
+#define UART_RD_S1_IDLE(base) ((UART_S1_REG(base) & UART_S1_IDLE_MASK) >> UART_S1_IDLE_SHIFT)
+#define UART_BRD_S1_IDLE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field RDRF[5] (RO)
+ *
+ * RDRF is set when the number of datawords in the receive buffer is equal to or
+ * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
+ * process of being received is not included in the count. To clear RDRF, read S1
+ * when RDRF is set and then read D. For more efficient interrupt and DMA
+ * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
+ * Then read S1 and the final data value, resulting in the clearing of the RDRF
+ * flag. Even if RDRF is set, data will continue to be received until an overrun
+ * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
+ * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
+ * buffer but over-write each other.
+ *
+ * Values:
+ * - 0b0 - The number of datawords in the receive buffer is less than the number
+ *     indicated by RXWATER.
+ * - 0b1 - The number of datawords in the receive buffer is equal to or greater
+ *     than the number indicated by RXWATER at some point in time since this flag
+ *     was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_RDRF field. */
+#define UART_RD_S1_RDRF(base) ((UART_S1_REG(base) & UART_S1_RDRF_MASK) >> UART_S1_RDRF_SHIFT)
+#define UART_BRD_S1_RDRF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_RDRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TC[6] (RO)
+ *
+ * TC is set when the transmit buffer is empty and no data, preamble, or break
+ * character is being transmitted. When TC is set, the transmit data output signal
+ * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
+ * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
+ * set after any NACK signal has been received, but prior to any corresponding
+ * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
+ * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
+ * in C2.
+ *
+ * Values:
+ * - 0b0 - Transmitter active (sending data, a preamble, or a break).
+ * - 0b1 - Transmitter idle (transmission activity complete).
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TC field. */
+#define UART_RD_S1_TC(base)  ((UART_S1_REG(base) & UART_S1_TC_MASK) >> UART_S1_TC_SHIFT)
+#define UART_BRD_S1_TC(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_TC_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TDRE[7] (RO)
+ *
+ * TDRE will set when the number of datawords in the transmit buffer (D and
+ * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
+ * character that is in the process of being transmitted is not included in the count.
+ * To clear TDRE, read S1 when TDRE is set and then write to the UART data
+ * register (D). For more efficient interrupt servicing, all data except the final value
+ * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
+ * before writing the final data value, resulting in the clearing of the TRDE
+ * flag. This is more efficient because the TDRE reasserts until the watermark has
+ * been exceeded. So, attempting to clear the TDRE with every write will be
+ * ineffective until sufficient data has been written.
+ *
+ * Values:
+ * - 0b0 - The amount of data in the transmit buffer is greater than the value
+ *     indicated by TWFIFO[TXWATER].
+ * - 0b1 - The amount of data in the transmit buffer is less than or equal to
+ *     the value indicated by TWFIFO[TXWATER] at some point in time since the flag
+ *     has been cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TDRE field. */
+#define UART_RD_S1_TDRE(base) ((UART_S1_REG(base) & UART_S1_TDRE_MASK) >> UART_S1_TDRE_SHIFT)
+#define UART_BRD_S1_TDRE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_TDRE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S2 - UART Status Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S2 - UART Status Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The S2 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. Also, this register can be polled by the MCU to check the
+ * status of these bits. This register can be read or written at any time, with the
+ * exception of the MSBF and RXINV bits, which should be changed by the user only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_S2 register
+ */
+/*@{*/
+#define UART_RD_S2(base)         (UART_S2_REG(base))
+#define UART_WR_S2(base, value)  (UART_S2_REG(base) = (value))
+#define UART_RMW_S2(base, mask, value) (UART_WR_S2(base, (UART_RD_S2(base) & ~(mask)) | (value)))
+#define UART_SET_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) |  (value)))
+#define UART_CLR_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) & ~(value)))
+#define UART_TOG_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S2 bitfields
+ */
+
+/*!
+ * @name Register UART_S2, field RAF[0] (RO)
+ *
+ * RAF is set when the UART receiver detects a logic 0 during the RT1 time
+ * period of the start bit search. RAF is cleared when the receiver detects an idle
+ * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
+ * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
+ * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
+ * to configure the guard time to 12. However, if a NACK is required to be
+ * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
+ * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
+ * prior to actually being inactive.
+ *
+ * Values:
+ * - 0b0 - UART receiver idle/inactive waiting for a start bit.
+ * - 0b1 - UART receiver active, RxD input not idle.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RAF field. */
+#define UART_RD_S2_RAF(base) ((UART_S2_REG(base) & UART_S2_RAF_MASK) >> UART_S2_RAF_SHIFT)
+#define UART_BRD_S2_RAF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RAF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field LBKDE[1] (RW)
+ *
+ * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
+ * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
+ * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
+ *
+ * Values:
+ * - 0b0 - Break character detection is disabled.
+ * - 0b1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
+ *     12 bits time if C1[M] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_LBKDE field. */
+#define UART_RD_S2_LBKDE(base) ((UART_S2_REG(base) & UART_S2_LBKDE_MASK) >> UART_S2_LBKDE_SHIFT)
+#define UART_BRD_S2_LBKDE(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDE_SHIFT))
+
+/*! @brief Set the LBKDE field to a new value. */
+#define UART_WR_S2_LBKDE(base, value) (UART_RMW_S2(base, (UART_S2_LBKDE_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_LBKDE(value)))
+#define UART_BWR_S2_LBKDE(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field BRK13[2] (RW)
+ *
+ * Determines whether the transmit break character is 10, 11, or 12 bits long,
+ * or 13 or 14 bits long. See for the length of the break character for the
+ * different configurations. The detection of a framing error is not affected by this
+ * field. Transmitting break characters
+ *
+ * Values:
+ * - 0b0 - Break character is 10, 11, or 12 bits long.
+ * - 0b1 - Break character is 13 or 14 bits long.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_BRK13 field. */
+#define UART_RD_S2_BRK13(base) ((UART_S2_REG(base) & UART_S2_BRK13_MASK) >> UART_S2_BRK13_SHIFT)
+#define UART_BRD_S2_BRK13(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT))
+
+/*! @brief Set the BRK13 field to a new value. */
+#define UART_WR_S2_BRK13(base, value) (UART_RMW_S2(base, (UART_S2_BRK13_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_BRK13(value)))
+#define UART_BWR_S2_BRK13(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RWUID[3] (RW)
+ *
+ * When RWU is set and WAKE is cleared, this field controls whether the idle
+ * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - S1[IDLE] is not set upon detection of an idle character.
+ * - 0b1 - S1[IDLE] is set upon detection of an idle character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RWUID field. */
+#define UART_RD_S2_RWUID(base) ((UART_S2_REG(base) & UART_S2_RWUID_MASK) >> UART_S2_RWUID_SHIFT)
+#define UART_BRD_S2_RWUID(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT))
+
+/*! @brief Set the RWUID field to a new value. */
+#define UART_WR_S2_RWUID(base, value) (UART_RMW_S2(base, (UART_S2_RWUID_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RWUID(value)))
+#define UART_BWR_S2_RWUID(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the received data input. In NRZ
+ * format, a one is represented by a mark and a zero is represented by a space for
+ * normal polarity, and the opposite for inverted polarity. In IrDA format, a
+ * zero is represented by short high pulse in the middle of a bit time remaining
+ * idle low for a one for normal polarity. A zero is represented by a short low
+ * pulse in the middle of a bit time remaining idle high for a one for inverted
+ * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
+ * enabled and an initial character is detected in T = 0 protocol mode. Setting
+ * RXINV inverts the RxD input for data bits, start and stop bits, break, and
+ * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
+ * are inverted.
+ *
+ * Values:
+ * - 0b0 - Receive data is not inverted.
+ * - 0b1 - Receive data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXINV field. */
+#define UART_RD_S2_RXINV(base) ((UART_S2_REG(base) & UART_S2_RXINV_MASK) >> UART_S2_RXINV_SHIFT)
+#define UART_BRD_S2_RXINV(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT))
+
+/*! @brief Set the RXINV field to a new value. */
+#define UART_WR_S2_RXINV(base, value) (UART_RMW_S2(base, (UART_S2_RXINV_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RXINV(value)))
+#define UART_BWR_S2_RXINV(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field MSBF[5] (RW)
+ *
+ * Setting this field reverses the order of the bits that are transmitted and
+ * received on the wire. This field does not affect the polarity of the bits, the
+ * location of the parity bit, or the location of the start or stop bits. This
+ * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
+ * an initial character is detected in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0b0 - LSB (bit0) is the first bit that is transmitted following the start
+ *     bit. Further, the first bit received after the start bit is identified as
+ *     bit0.
+ * - 0b1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted
+ *     following the start bit, depending on the setting of C1[M] and C1[PE]. Further,
+ *     the first bit received after the start bit is identified as bit8, bit7, or
+ *     bit6, depending on the setting of C1[M] and C1[PE].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_MSBF field. */
+#define UART_RD_S2_MSBF(base) ((UART_S2_REG(base) & UART_S2_MSBF_MASK) >> UART_S2_MSBF_SHIFT)
+#define UART_BRD_S2_MSBF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT))
+
+/*! @brief Set the MSBF field to a new value. */
+#define UART_WR_S2_MSBF(base, value) (UART_RMW_S2(base, (UART_S2_MSBF_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_MSBF(value)))
+#define UART_BWR_S2_MSBF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXEDGIF[6] (W1C)
+ *
+ * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
+ * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
+ * to it. See for additional details. RXEDGIF description The active edge is
+ * detected only in two wire mode and on receiving data coming from the RxD pin.
+ *
+ * Values:
+ * - 0b0 - No active edge on the receive pin has occurred.
+ * - 0b1 - An active edge on the receive pin has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXEDGIF field. */
+#define UART_RD_S2_RXEDGIF(base) ((UART_S2_REG(base) & UART_S2_RXEDGIF_MASK) >> UART_S2_RXEDGIF_SHIFT)
+#define UART_BRD_S2_RXEDGIF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT))
+
+/*! @brief Set the RXEDGIF field to a new value. */
+#define UART_WR_S2_RXEDGIF(base, value) (UART_RMW_S2(base, (UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RXEDGIF(value)))
+#define UART_BWR_S2_RXEDGIF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field LBKDIF[7] (W1C)
+ *
+ * LBKDIF is set when LBKDE is set and a LIN break character is detected on the
+ * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
+ * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
+ * last LIN break character. LBKDIF is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - No LIN break character detected.
+ * - 0b1 - LIN break character detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_LBKDIF field. */
+#define UART_RD_S2_LBKDIF(base) ((UART_S2_REG(base) & UART_S2_LBKDIF_MASK) >> UART_S2_LBKDIF_SHIFT)
+#define UART_BRD_S2_LBKDIF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDIF_SHIFT))
+
+/*! @brief Set the LBKDIF field to a new value. */
+#define UART_WR_S2_LBKDIF(base, value) (UART_RMW_S2(base, (UART_S2_LBKDIF_MASK | UART_S2_RXEDGIF_MASK), UART_S2_LBKDIF(value)))
+#define UART_BWR_S2_LBKDIF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDIF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C3 - UART Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C3 - UART Control Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_C3 register
+ */
+/*@{*/
+#define UART_RD_C3(base)         (UART_C3_REG(base))
+#define UART_WR_C3(base, value)  (UART_C3_REG(base) = (value))
+#define UART_RMW_C3(base, mask, value) (UART_WR_C3(base, (UART_RD_C3(base) & ~(mask)) | (value)))
+#define UART_SET_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) |  (value)))
+#define UART_CLR_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) & ~(value)))
+#define UART_TOG_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C3 bitfields
+ */
+
+/*!
+ * @name Register UART_C3, field PEIE[0] (RW)
+ *
+ * Enables the parity error flag, S1[PF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - PF interrupt requests are disabled.
+ * - 0b1 - PF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_PEIE field. */
+#define UART_RD_C3_PEIE(base) ((UART_C3_REG(base) & UART_C3_PEIE_MASK) >> UART_C3_PEIE_SHIFT)
+#define UART_BRD_C3_PEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT))
+
+/*! @brief Set the PEIE field to a new value. */
+#define UART_WR_C3_PEIE(base, value) (UART_RMW_C3(base, UART_C3_PEIE_MASK, UART_C3_PEIE(value)))
+#define UART_BWR_C3_PEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field FEIE[1] (RW)
+ *
+ * Enables the framing error flag, S1[FE], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - FE interrupt requests are disabled.
+ * - 0b1 - FE interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_FEIE field. */
+#define UART_RD_C3_FEIE(base) ((UART_C3_REG(base) & UART_C3_FEIE_MASK) >> UART_C3_FEIE_SHIFT)
+#define UART_BRD_C3_FEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define UART_WR_C3_FEIE(base, value) (UART_RMW_C3(base, UART_C3_FEIE_MASK, UART_C3_FEIE(value)))
+#define UART_BWR_C3_FEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field NEIE[2] (RW)
+ *
+ * Enables the noise flag, S1[NF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - NF interrupt requests are disabled.
+ * - 0b1 - NF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_NEIE field. */
+#define UART_RD_C3_NEIE(base) ((UART_C3_REG(base) & UART_C3_NEIE_MASK) >> UART_C3_NEIE_SHIFT)
+#define UART_BRD_C3_NEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT))
+
+/*! @brief Set the NEIE field to a new value. */
+#define UART_WR_C3_NEIE(base, value) (UART_RMW_C3(base, UART_C3_NEIE_MASK, UART_C3_NEIE(value)))
+#define UART_BWR_C3_NEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field ORIE[3] (RW)
+ *
+ * Enables the overrun error flag, S1[OR], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - OR interrupts are disabled.
+ * - 0b1 - OR interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_ORIE field. */
+#define UART_RD_C3_ORIE(base) ((UART_C3_REG(base) & UART_C3_ORIE_MASK) >> UART_C3_ORIE_SHIFT)
+#define UART_BRD_C3_ORIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT))
+
+/*! @brief Set the ORIE field to a new value. */
+#define UART_WR_C3_ORIE(base, value) (UART_RMW_C3(base, UART_C3_ORIE_MASK, UART_C3_ORIE(value)))
+#define UART_BWR_C3_ORIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the transmitted data output. In
+ * NRZ format, a one is represented by a mark and a zero is represented by a space
+ * for normal polarity, and the opposite for inverted polarity. In IrDA format,
+ * a zero is represented by short high pulse in the middle of a bit time
+ * remaining idle low for a one for normal polarity, and a zero is represented by short
+ * low pulse in the middle of a bit time remaining idle high for a one for
+ * inverted polarity. This field is automatically set when C7816[INIT] and
+ * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
+ * Setting TXINV inverts all transmitted values, including idle, break, start, and
+ * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
+ * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
+ * the transmitted data bits and parity bit are inverted.
+ *
+ * Values:
+ * - 0b0 - Transmit data is not inverted.
+ * - 0b1 - Transmit data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXINV field. */
+#define UART_RD_C3_TXINV(base) ((UART_C3_REG(base) & UART_C3_TXINV_MASK) >> UART_C3_TXINV_SHIFT)
+#define UART_BRD_C3_TXINV(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT))
+
+/*! @brief Set the TXINV field to a new value. */
+#define UART_WR_C3_TXINV(base, value) (UART_RMW_C3(base, UART_C3_TXINV_MASK, UART_C3_TXINV(value)))
+#define UART_BWR_C3_TXINV(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXDIR[5] (RW)
+ *
+ * Determines whether the TXD pin is used as an input or output in the
+ * single-wire mode of operation. This field is relevant only to the single wire mode.
+ * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
+ * automatically cleared after the requested block is transmitted. This condition is
+ * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
+ * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
+ * being transmitted, the hardware automatically overrides this field as needed. In
+ * this situation, TXDIR does not reflect the temporary state associated with
+ * the NACK.
+ *
+ * Values:
+ * - 0b0 - TXD pin is an input in single wire mode.
+ * - 0b1 - TXD pin is an output in single wire mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXDIR field. */
+#define UART_RD_C3_TXDIR(base) ((UART_C3_REG(base) & UART_C3_TXDIR_MASK) >> UART_C3_TXDIR_SHIFT)
+#define UART_BRD_C3_TXDIR(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT))
+
+/*! @brief Set the TXDIR field to a new value. */
+#define UART_WR_C3_TXDIR(base, value) (UART_RMW_C3(base, UART_C3_TXDIR_MASK, UART_C3_TXDIR(value)))
+#define UART_BWR_C3_TXDIR(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field T8[6] (RW)
+ *
+ * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
+ * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
+ * same as in the previous transmission, T8 does not have to be rewritten. The same
+ * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
+ * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
+ * the remaining data.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_T8 field. */
+#define UART_RD_C3_T8(base)  ((UART_C3_REG(base) & UART_C3_T8_MASK) >> UART_C3_T8_SHIFT)
+#define UART_BRD_C3_T8(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_T8_SHIFT))
+
+/*! @brief Set the T8 field to a new value. */
+#define UART_WR_C3_T8(base, value) (UART_RMW_C3(base, UART_C3_T8_MASK, UART_C3_T8(value)))
+#define UART_BWR_C3_T8(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_T8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field R8[7] (RO)
+ *
+ * R8 is the ninth data bit received when the UART is configured for 9-bit data
+ * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
+ * current data value in the UARTx_D register. To read the 9th bit, read the
+ * value of UARTx_C3[R8], then read the UARTx_D register.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_R8 field. */
+#define UART_RD_C3_R8(base)  ((UART_C3_REG(base) & UART_C3_R8_MASK) >> UART_C3_R8_SHIFT)
+#define UART_BRD_C3_R8(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_R8_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_D - UART Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_D - UART Data Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is actually two separate registers. Reads return the contents
+ * of the read-only receive data register and writes go to the write-only transmit
+ * data register. In 8-bit or 9-bit data format, only UART data register (D)
+ * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
+ * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
+ * register, only if the ninth bit of data needs to be captured. Similarly, the
+ * ED register needs to be read, prior to the D register, only if the additional
+ * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
+ * bit cleared) if the parity is enabled, you get seven data bits and one parity
+ * bit. That one parity bit is loaded into the D register. So, for the data bits,
+ * mask off the parity bit from the value you read out of this register. When
+ * transmitting in 9-bit data format and using 8-bit write instructions, write first
+ * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
+ * C3[T8] stores the data in a temporary register. If D register is written first,
+ * and then the new data on data bus is stored in D, the temporary value written by
+ * the last write to C3[T8] gets stored in the C3[T8] register.
+ */
+/*!
+ * @name Constants and macros for entire UART_D register
+ */
+/*@{*/
+#define UART_RD_D(base)          (UART_D_REG(base))
+#define UART_WR_D(base, value)   (UART_D_REG(base) = (value))
+#define UART_RMW_D(base, mask, value) (UART_WR_D(base, (UART_RD_D(base) & ~(mask)) | (value)))
+#define UART_SET_D(base, value)  (UART_WR_D(base, UART_RD_D(base) |  (value)))
+#define UART_CLR_D(base, value)  (UART_WR_D(base, UART_RD_D(base) & ~(value)))
+#define UART_TOG_D(base, value)  (UART_WR_D(base, UART_RD_D(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA1 - UART Match Address Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA1 - UART Match Address Registers 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MA1 and MA2 registers are compared to input data addresses when the most
+ * significant bit is set and the associated C4[MAEN] field is set. If a match
+ * occurs, the following data is transferred to the data register. If a match
+ * fails, the following data is discarded. These registers can be read and written at
+ * anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA1 register
+ */
+/*@{*/
+#define UART_RD_MA1(base)        (UART_MA1_REG(base))
+#define UART_WR_MA1(base, value) (UART_MA1_REG(base) = (value))
+#define UART_RMW_MA1(base, mask, value) (UART_WR_MA1(base, (UART_RD_MA1(base) & ~(mask)) | (value)))
+#define UART_SET_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) |  (value)))
+#define UART_CLR_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) & ~(value)))
+#define UART_TOG_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA2 - UART Match Address Registers 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA2 - UART Match Address Registers 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * These registers can be read and written at anytime. The MA1 and MA2 registers
+ * are compared to input data addresses when the most significant bit is set and
+ * the associated C4[MAEN] field is set. If a match occurs, the following data
+ * is transferred to the data register. If a match fails, the following data is
+ * discarded.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA2 register
+ */
+/*@{*/
+#define UART_RD_MA2(base)        (UART_MA2_REG(base))
+#define UART_WR_MA2(base, value) (UART_MA2_REG(base) = (value))
+#define UART_RMW_MA2(base, mask, value) (UART_WR_MA2(base, (UART_RD_MA2(base) & ~(mask)) | (value)))
+#define UART_SET_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) |  (value)))
+#define UART_CLR_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) & ~(value)))
+#define UART_TOG_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C4 - UART Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C4 - UART Control Register 4 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C4 register
+ */
+/*@{*/
+#define UART_RD_C4(base)         (UART_C4_REG(base))
+#define UART_WR_C4(base, value)  (UART_C4_REG(base) = (value))
+#define UART_RMW_C4(base, mask, value) (UART_WR_C4(base, (UART_RD_C4(base) & ~(mask)) | (value)))
+#define UART_SET_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) |  (value)))
+#define UART_CLR_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) & ~(value)))
+#define UART_TOG_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C4 bitfields
+ */
+
+/*!
+ * @name Register UART_C4, field BRFA[4:0] (RW)
+ *
+ * This bit field is used to add more timing resolution to the average baud
+ * frequency, in increments of 1/32. See Baud rate generation for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_BRFA field. */
+#define UART_RD_C4_BRFA(base) ((UART_C4_REG(base) & UART_C4_BRFA_MASK) >> UART_C4_BRFA_SHIFT)
+#define UART_BRD_C4_BRFA(base) (UART_RD_C4_BRFA(base))
+
+/*! @brief Set the BRFA field to a new value. */
+#define UART_WR_C4_BRFA(base, value) (UART_RMW_C4(base, UART_C4_BRFA_MASK, UART_C4_BRFA(value)))
+#define UART_BWR_C4_BRFA(base, value) (UART_WR_C4_BRFA(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field M10[5] (RW)
+ *
+ * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
+ * This tenth bit is generated and interpreted as a parity bit. The M10 field
+ * does not affect the LIN send or detect break behavior. If M10 is set, then both
+ * C1[M] and C1[PE] must also be set. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
+ *
+ * Values:
+ * - 0b0 - The parity bit is the ninth bit in the serial transmission.
+ * - 0b1 - The parity bit is the tenth bit in the serial transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_M10 field. */
+#define UART_RD_C4_M10(base) ((UART_C4_REG(base) & UART_C4_M10_MASK) >> UART_C4_M10_SHIFT)
+#define UART_BRD_C4_M10(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_M10_SHIFT))
+
+/*! @brief Set the M10 field to a new value. */
+#define UART_WR_C4_M10(base, value) (UART_RMW_C4(base, UART_C4_M10_MASK, UART_C4_M10(value)))
+#define UART_BWR_C4_M10(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_M10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN2[6] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0b0 - All data received is transferred to the data buffer if MAEN1 is
+ *     cleared.
+ * - 0b1 - All data received with the most significant bit cleared, is
+ *     discarded. All data received with the most significant bit set, is compared with
+ *     contents of MA2 register. If no match occurs, the data is discarded. If a
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN2 field. */
+#define UART_RD_C4_MAEN2(base) ((UART_C4_REG(base) & UART_C4_MAEN2_MASK) >> UART_C4_MAEN2_SHIFT)
+#define UART_BRD_C4_MAEN2(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT))
+
+/*! @brief Set the MAEN2 field to a new value. */
+#define UART_WR_C4_MAEN2(base, value) (UART_RMW_C4(base, UART_C4_MAEN2_MASK, UART_C4_MAEN2(value)))
+#define UART_BWR_C4_MAEN2(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN1[7] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0b0 - All data received is transferred to the data buffer if MAEN2 is
+ *     cleared.
+ * - 0b1 - All data received with the most significant bit cleared, is
+ *     discarded. All data received with the most significant bit set, is compared with
+ *     contents of MA1 register. If no match occurs, the data is discarded. If
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN1 field. */
+#define UART_RD_C4_MAEN1(base) ((UART_C4_REG(base) & UART_C4_MAEN1_MASK) >> UART_C4_MAEN1_SHIFT)
+#define UART_BRD_C4_MAEN1(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT))
+
+/*! @brief Set the MAEN1 field to a new value. */
+#define UART_WR_C4_MAEN1(base, value) (UART_RMW_C4(base, UART_C4_MAEN1_MASK, UART_C4_MAEN1(value)))
+#define UART_BWR_C4_MAEN1(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C5 - UART Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C5 - UART Control Register 5 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C5 register
+ */
+/*@{*/
+#define UART_RD_C5(base)         (UART_C5_REG(base))
+#define UART_WR_C5(base, value)  (UART_C5_REG(base) = (value))
+#define UART_RMW_C5(base, mask, value) (UART_WR_C5(base, (UART_RD_C5(base) & ~(mask)) | (value)))
+#define UART_SET_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) |  (value)))
+#define UART_CLR_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) & ~(value)))
+#define UART_TOG_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C5 bitfields
+ */
+
+/*!
+ * @name Register UART_C5, field LBKDDMAS[3] (RW)
+ *
+ * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
+ * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
+ * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
+ * of the state of LBKDDMAS.
+ *
+ * Values:
+ * - 0b0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
+ *     asserted to request an interrupt service.
+ * - 0b1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal
+ *     is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_LBKDDMAS field. */
+#define UART_RD_C5_LBKDDMAS(base) ((UART_C5_REG(base) & UART_C5_LBKDDMAS_MASK) >> UART_C5_LBKDDMAS_SHIFT)
+#define UART_BRD_C5_LBKDDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_LBKDDMAS_SHIFT))
+
+/*! @brief Set the LBKDDMAS field to a new value. */
+#define UART_WR_C5_LBKDDMAS(base, value) (UART_RMW_C5(base, UART_C5_LBKDDMAS_MASK, UART_C5_LBKDDMAS(value)))
+#define UART_BWR_C5_LBKDDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_LBKDDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field ILDMAS[4] (RW)
+ *
+ * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
+ * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
+ * DMA and IDLE interrupt request signals are not asserted, regardless of the state
+ * of ILDMAS.
+ *
+ * Values:
+ * - 0b0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal
+ *     is asserted to request an interrupt service.
+ * - 0b1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_ILDMAS field. */
+#define UART_RD_C5_ILDMAS(base) ((UART_C5_REG(base) & UART_C5_ILDMAS_MASK) >> UART_C5_ILDMAS_SHIFT)
+#define UART_BRD_C5_ILDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_ILDMAS_SHIFT))
+
+/*! @brief Set the ILDMAS field to a new value. */
+#define UART_WR_C5_ILDMAS(base, value) (UART_RMW_C5(base, UART_C5_ILDMAS_MASK, UART_C5_ILDMAS(value)))
+#define UART_BWR_C5_ILDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_ILDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field RDMAS[5] (RW)
+ *
+ * Configures the receiver data register full flag, S1[RDRF], to generate
+ * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
+ * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
+ * regardless of the state of RDMAS.
+ *
+ * Values:
+ * - 0b0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
+ *     asserted to request an interrupt service.
+ * - 0b1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_RDMAS field. */
+#define UART_RD_C5_RDMAS(base) ((UART_C5_REG(base) & UART_C5_RDMAS_MASK) >> UART_C5_RDMAS_SHIFT)
+#define UART_BRD_C5_RDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT))
+
+/*! @brief Set the RDMAS field to a new value. */
+#define UART_WR_C5_RDMAS(base, value) (UART_RMW_C5(base, UART_C5_RDMAS_MASK, UART_C5_RDMAS(value)))
+#define UART_BWR_C5_RDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TCDMAS[6] (RW)
+ *
+ * Configures the transmission complete flag, S1[TC], to generate interrupt or
+ * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
+ * interrupt request signals are not asserted when the S1[TC] flag is set, regardless
+ * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
+ * must be cleared, and D must not be written unless a DMA request is being serviced.
+ *
+ * Values:
+ * - 0b0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt
+ *     request signal is asserted to request an interrupt service.
+ * - 0b1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TCDMAS field. */
+#define UART_RD_C5_TCDMAS(base) ((UART_C5_REG(base) & UART_C5_TCDMAS_MASK) >> UART_C5_TCDMAS_SHIFT)
+#define UART_BRD_C5_TCDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TCDMAS_SHIFT))
+
+/*! @brief Set the TCDMAS field to a new value. */
+#define UART_WR_C5_TCDMAS(base, value) (UART_RMW_C5(base, UART_C5_TCDMAS_MASK, UART_C5_TCDMAS(value)))
+#define UART_BWR_C5_TCDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TCDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TDMAS[7] (RW)
+ *
+ * Configures the transmit data register empty flag, S1[TDRE], to generate
+ * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
+ * TDRE interrupt request signals are not asserted when the TDRE flag is set,
+ * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
+ * must be cleared, and D must not be written unless a DMA request is being
+ * serviced.
+ *
+ * Values:
+ * - 0b0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
+ *     request signal is asserted to request interrupt service.
+ * - 0b1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TDMAS field. */
+#define UART_RD_C5_TDMAS(base) ((UART_C5_REG(base) & UART_C5_TDMAS_MASK) >> UART_C5_TDMAS_SHIFT)
+#define UART_BRD_C5_TDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT))
+
+/*! @brief Set the TDMAS field to a new value. */
+#define UART_WR_C5_TDMAS(base, value) (UART_RMW_C5(base, UART_C5_TDMAS_MASK, UART_C5_TDMAS(value)))
+#define UART_BWR_C5_TDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ED - UART Extended Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ED - UART Extended Data Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains additional information flags that are stored with a
+ * received dataword. This register may be read at any time but contains valid data
+ * only if there is a dataword in the receive FIFO. The data contained in this
+ * register represents additional information regarding the conditions on which a
+ * dataword was received. The importance of this data varies with the
+ * application, and in some cases maybe completely optional. These fields automatically
+ * update to reflect the conditions of the next dataword whenever D is read. If
+ * S1[NF] and S1[PF] have not been set since the last time the receive buffer was
+ * empty, the NOISY and PARITYE fields will be zero.
+ */
+/*!
+ * @name Constants and macros for entire UART_ED register
+ */
+/*@{*/
+#define UART_RD_ED(base)         (UART_ED_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ED bitfields
+ */
+
+/*!
+ * @name Register UART_ED, field PARITYE[6] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with a
+ * parity error.
+ *
+ * Values:
+ * - 0b0 - The dataword was received without a parity error.
+ * - 0b1 - The dataword was received with a parity error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ED_PARITYE field. */
+#define UART_RD_ED_PARITYE(base) ((UART_ED_REG(base) & UART_ED_PARITYE_MASK) >> UART_ED_PARITYE_SHIFT)
+#define UART_BRD_ED_PARITYE(base) (BITBAND_ACCESS8(&UART_ED_REG(base), UART_ED_PARITYE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_ED, field NOISY[7] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with
+ * noise.
+ *
+ * Values:
+ * - 0b0 - The dataword was received without noise.
+ * - 0b1 - The data was received with noise.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ED_NOISY field. */
+#define UART_RD_ED_NOISY(base) ((UART_ED_REG(base) & UART_ED_NOISY_MASK) >> UART_ED_NOISY_SHIFT)
+#define UART_BRD_ED_NOISY(base) (BITBAND_ACCESS8(&UART_ED_REG(base), UART_ED_NOISY_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MODEM - UART Modem Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MODEM - UART Modem Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MODEM register controls options for setting the modem configuration.
+ * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
+ * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
+ * ISO-7816 protocol does not use the RTS and CTS signals.
+ */
+/*!
+ * @name Constants and macros for entire UART_MODEM register
+ */
+/*@{*/
+#define UART_RD_MODEM(base)      (UART_MODEM_REG(base))
+#define UART_WR_MODEM(base, value) (UART_MODEM_REG(base) = (value))
+#define UART_RMW_MODEM(base, mask, value) (UART_WR_MODEM(base, (UART_RD_MODEM(base) & ~(mask)) | (value)))
+#define UART_SET_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) |  (value)))
+#define UART_CLR_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) & ~(value)))
+#define UART_TOG_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_MODEM bitfields
+ */
+
+/*!
+ * @name Register UART_MODEM, field TXCTSE[0] (RW)
+ *
+ * TXCTSE controls the operation of the transmitter. TXCTSE can be set
+ * independently from the state of TXRTSE and RXRTSE.
+ *
+ * Values:
+ * - 0b0 - CTS has no effect on the transmitter.
+ * - 0b1 - Enables clear-to-send operation. The transmitter checks the state of
+ *     CTS each time it is ready to send a character. If CTS is asserted, the
+ *     character is sent. If CTS is deasserted, the signal TXD remains in the mark
+ *     state and transmission is delayed until CTS is asserted. Changes in CTS as
+ *     a character is being sent do not affect its transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXCTSE field. */
+#define UART_RD_MODEM_TXCTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_TXCTSE_MASK) >> UART_MODEM_TXCTSE_SHIFT)
+#define UART_BRD_MODEM_TXCTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXCTSE_SHIFT))
+
+/*! @brief Set the TXCTSE field to a new value. */
+#define UART_WR_MODEM_TXCTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXCTSE_MASK, UART_MODEM_TXCTSE(value)))
+#define UART_BWR_MODEM_TXCTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXCTSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field TXRTSE[1] (RW)
+ *
+ * Controls RTS before and after a transmission.
+ *
+ * Values:
+ * - 0b0 - The transmitter has no effect on RTS.
+ * - 0b1 - When a character is placed into an empty transmitter data buffer ,
+ *     RTS asserts one bit time before the start bit is transmitted. RTS deasserts
+ *     one bit time after all characters in the transmitter data buffer and shift
+ *     register are completely sent, including the last stop bit. (FIFO) (FIFO)
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXRTSE field. */
+#define UART_RD_MODEM_TXRTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_TXRTSE_MASK) >> UART_MODEM_TXRTSE_SHIFT)
+#define UART_BRD_MODEM_TXRTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSE_SHIFT))
+
+/*! @brief Set the TXRTSE field to a new value. */
+#define UART_WR_MODEM_TXRTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXRTSE_MASK, UART_MODEM_TXRTSE(value)))
+#define UART_BWR_MODEM_TXRTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field TXRTSPOL[2] (RW)
+ *
+ * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
+ * polarity of the receiver RTS. RTS will remain negated in the active low state
+ * unless TXRTSE is set.
+ *
+ * Values:
+ * - 0b0 - Transmitter RTS is active low.
+ * - 0b1 - Transmitter RTS is active high.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXRTSPOL field. */
+#define UART_RD_MODEM_TXRTSPOL(base) ((UART_MODEM_REG(base) & UART_MODEM_TXRTSPOL_MASK) >> UART_MODEM_TXRTSPOL_SHIFT)
+#define UART_BRD_MODEM_TXRTSPOL(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSPOL_SHIFT))
+
+/*! @brief Set the TXRTSPOL field to a new value. */
+#define UART_WR_MODEM_TXRTSPOL(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXRTSPOL_MASK, UART_MODEM_TXRTSPOL(value)))
+#define UART_BWR_MODEM_TXRTSPOL(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field RXRTSE[3] (RW)
+ *
+ * Allows the RTS output to control the CTS input of the transmitting device to
+ * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
+ *
+ * Values:
+ * - 0b0 - The receiver has no effect on RTS.
+ * - 0b1 - RTS is deasserted if the number of characters in the receiver data
+ *     register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
+ *     when the number of characters in the receiver data register (FIFO) is
+ *     less than RWFIFO[RXWATER].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_RXRTSE field. */
+#define UART_RD_MODEM_RXRTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_RXRTSE_MASK) >> UART_MODEM_RXRTSE_SHIFT)
+#define UART_BRD_MODEM_RXRTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_RXRTSE_SHIFT))
+
+/*! @brief Set the RXRTSE field to a new value. */
+#define UART_WR_MODEM_RXRTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_RXRTSE_MASK, UART_MODEM_RXRTSE(value)))
+#define UART_BWR_MODEM_RXRTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_RXRTSE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IR - UART Infrared Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IR - UART Infrared Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IR register controls options for setting the infrared configuration.
+ */
+/*!
+ * @name Constants and macros for entire UART_IR register
+ */
+/*@{*/
+#define UART_RD_IR(base)         (UART_IR_REG(base))
+#define UART_WR_IR(base, value)  (UART_IR_REG(base) = (value))
+#define UART_RMW_IR(base, mask, value) (UART_WR_IR(base, (UART_RD_IR(base) & ~(mask)) | (value)))
+#define UART_SET_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) |  (value)))
+#define UART_CLR_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) & ~(value)))
+#define UART_TOG_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IR bitfields
+ */
+
+/*!
+ * @name Register UART_IR, field TNP[1:0] (RW)
+ *
+ * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
+ *
+ * Values:
+ * - 0b00 - 3/16.
+ * - 0b01 - 1/16.
+ * - 0b10 - 1/32.
+ * - 0b11 - 1/4.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IR_TNP field. */
+#define UART_RD_IR_TNP(base) ((UART_IR_REG(base) & UART_IR_TNP_MASK) >> UART_IR_TNP_SHIFT)
+#define UART_BRD_IR_TNP(base) (UART_RD_IR_TNP(base))
+
+/*! @brief Set the TNP field to a new value. */
+#define UART_WR_IR_TNP(base, value) (UART_RMW_IR(base, UART_IR_TNP_MASK, UART_IR_TNP(value)))
+#define UART_BWR_IR_TNP(base, value) (UART_WR_IR_TNP(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_IR, field IREN[2] (RW)
+ *
+ * Enables/disables the infrared modulation/demodulation.
+ *
+ * Values:
+ * - 0b0 - IR disabled.
+ * - 0b1 - IR enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IR_IREN field. */
+#define UART_RD_IR_IREN(base) ((UART_IR_REG(base) & UART_IR_IREN_MASK) >> UART_IR_IREN_SHIFT)
+#define UART_BRD_IR_IREN(base) (BITBAND_ACCESS8(&UART_IR_REG(base), UART_IR_IREN_SHIFT))
+
+/*! @brief Set the IREN field to a new value. */
+#define UART_WR_IR_IREN(base, value) (UART_RMW_IR(base, UART_IR_IREN_MASK, UART_IR_IREN(value)))
+#define UART_BWR_IR_IREN(base, value) (BITBAND_ACCESS8(&UART_IR_REG(base), UART_IR_IREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_PFIFO - UART FIFO Parameters
+ ******************************************************************************/
+
+/*!
+ * @brief UART_PFIFO - UART FIFO Parameters (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability for the programmer to turn on and off FIFO
+ * functionality. It also provides the size of the FIFO that has been
+ * implemented. This register may be read at any time. This register must be written only
+ * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
+ * empty.
+ */
+/*!
+ * @name Constants and macros for entire UART_PFIFO register
+ */
+/*@{*/
+#define UART_RD_PFIFO(base)      (UART_PFIFO_REG(base))
+#define UART_WR_PFIFO(base, value) (UART_PFIFO_REG(base) = (value))
+#define UART_RMW_PFIFO(base, mask, value) (UART_WR_PFIFO(base, (UART_RD_PFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) |  (value)))
+#define UART_CLR_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) & ~(value)))
+#define UART_TOG_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_PFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
+ *
+ * The maximum number of receive datawords that can be stored in the receive
+ * buffer before an overrun occurs. This field is read only.
+ *
+ * Values:
+ * - 0b000 - Receive FIFO/Buffer depth = 1 dataword.
+ * - 0b001 - Receive FIFO/Buffer depth = 4 datawords.
+ * - 0b010 - Receive FIFO/Buffer depth = 8 datawords.
+ * - 0b011 - Receive FIFO/Buffer depth = 16 datawords.
+ * - 0b100 - Receive FIFO/Buffer depth = 32 datawords.
+ * - 0b101 - Receive FIFO/Buffer depth = 64 datawords.
+ * - 0b110 - Receive FIFO/Buffer depth = 128 datawords.
+ * - 0b111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. */
+#define UART_RD_PFIFO_RXFIFOSIZE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_RXFIFOSIZE_MASK) >> UART_PFIFO_RXFIFOSIZE_SHIFT)
+#define UART_BRD_PFIFO_RXFIFOSIZE(base) (UART_RD_PFIFO_RXFIFOSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field RXFE[3] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the receive buffer is
+ * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
+ * If this field is not set, the receive buffer operates as a FIFO of depth one
+ * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
+ * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
+ * commands must be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0b0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
+ * - 0b1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_RXFE field. */
+#define UART_RD_PFIFO_RXFE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_RXFE_MASK) >> UART_PFIFO_RXFE_SHIFT)
+#define UART_BRD_PFIFO_RXFE(base) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_RXFE_SHIFT))
+
+/*! @brief Set the RXFE field to a new value. */
+#define UART_WR_PFIFO_RXFE(base, value) (UART_RMW_PFIFO(base, UART_PFIFO_RXFE_MASK, UART_PFIFO_RXFE(value)))
+#define UART_BWR_PFIFO_RXFE(base, value) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_RXFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
+ *
+ * The maximum number of transmit datawords that can be stored in the transmit
+ * buffer. This field is read only.
+ *
+ * Values:
+ * - 0b000 - Transmit FIFO/Buffer depth = 1 dataword.
+ * - 0b001 - Transmit FIFO/Buffer depth = 4 datawords.
+ * - 0b010 - Transmit FIFO/Buffer depth = 8 datawords.
+ * - 0b011 - Transmit FIFO/Buffer depth = 16 datawords.
+ * - 0b100 - Transmit FIFO/Buffer depth = 32 datawords.
+ * - 0b101 - Transmit FIFO/Buffer depth = 64 datawords.
+ * - 0b110 - Transmit FIFO/Buffer depth = 128 datawords.
+ * - 0b111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. */
+#define UART_RD_PFIFO_TXFIFOSIZE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_TXFIFOSIZE_MASK) >> UART_PFIFO_TXFIFOSIZE_SHIFT)
+#define UART_BRD_PFIFO_TXFIFOSIZE(base) (UART_RD_PFIFO_TXFIFOSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field TXFE[7] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the transmit buffer
+ * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
+ * field is not set, the transmit buffer operates as a FIFO of depth one dataword
+ * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
+ * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
+ * be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0b0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
+ * - 0b1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_TXFE field. */
+#define UART_RD_PFIFO_TXFE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_TXFE_MASK) >> UART_PFIFO_TXFE_SHIFT)
+#define UART_BRD_PFIFO_TXFE(base) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_TXFE_SHIFT))
+
+/*! @brief Set the TXFE field to a new value. */
+#define UART_WR_PFIFO_TXFE(base, value) (UART_RMW_PFIFO(base, UART_PFIFO_TXFE_MASK, UART_PFIFO_TXFE(value)))
+#define UART_BWR_PFIFO_TXFE(base, value) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_TXFE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_CFIFO - UART FIFO Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_CFIFO - UART FIFO Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to program various control fields for FIFO
+ * operation. This register may be read or written at any time. Note that
+ * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
+ * to prevent unintended/unpredictable behavior. Therefore, it is recommended that
+ * TE and RE be cleared prior to flushing the corresponding FIFO.
+ */
+/*!
+ * @name Constants and macros for entire UART_CFIFO register
+ */
+/*@{*/
+#define UART_RD_CFIFO(base)      (UART_CFIFO_REG(base))
+#define UART_WR_CFIFO(base, value) (UART_CFIFO_REG(base) = (value))
+#define UART_RMW_CFIFO(base, mask, value) (UART_WR_CFIFO(base, (UART_RD_CFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) |  (value)))
+#define UART_CLR_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) & ~(value)))
+#define UART_TOG_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_CFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_CFIFO, field RXUFE[0] (RW)
+ *
+ * When this field is set, the RXUF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - RXUF flag does not generate an interrupt to the host.
+ * - 0b1 - RXUF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_RXUFE field. */
+#define UART_RD_CFIFO_RXUFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_RXUFE_MASK) >> UART_CFIFO_RXUFE_SHIFT)
+#define UART_BRD_CFIFO_RXUFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXUFE_SHIFT))
+
+/*! @brief Set the RXUFE field to a new value. */
+#define UART_WR_CFIFO_RXUFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXUFE_MASK, UART_CFIFO_RXUFE(value)))
+#define UART_BWR_CFIFO_RXUFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXUFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field TXOFE[1] (RW)
+ *
+ * When this field is set, the TXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - TXOF flag does not generate an interrupt to the host.
+ * - 0b1 - TXOF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_TXOFE field. */
+#define UART_RD_CFIFO_TXOFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_TXOFE_MASK) >> UART_CFIFO_TXOFE_SHIFT)
+#define UART_BRD_CFIFO_TXOFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXOFE_SHIFT))
+
+/*! @brief Set the TXOFE field to a new value. */
+#define UART_WR_CFIFO_TXOFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_TXOFE_MASK, UART_CFIFO_TXOFE(value)))
+#define UART_BWR_CFIFO_TXOFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXOFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field RXOFE[2] (RW)
+ *
+ * When this field is set, the RXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - RXOF flag does not generate an interrupt to the host.
+ * - 0b1 - RXOF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_RXOFE field. */
+#define UART_RD_CFIFO_RXOFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_RXOFE_MASK) >> UART_CFIFO_RXOFE_SHIFT)
+#define UART_BRD_CFIFO_RXOFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXOFE_SHIFT))
+
+/*! @brief Set the RXOFE field to a new value. */
+#define UART_WR_CFIFO_RXOFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXOFE_MASK, UART_CFIFO_RXOFE(value)))
+#define UART_BWR_CFIFO_RXOFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXOFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the receive
+ * FIFO/buffer to be flushed. This does not affect data that is in the receive shift
+ * register.
+ *
+ * Values:
+ * - 0b0 - No flush operation occurs.
+ * - 0b1 - All data in the receive FIFO/buffer is cleared out.
+ */
+/*@{*/
+/*! @brief Set the RXFLUSH field to a new value. */
+#define UART_WR_CFIFO_RXFLUSH(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXFLUSH_MASK, UART_CFIFO_RXFLUSH(value)))
+#define UART_BWR_CFIFO_RXFLUSH(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXFLUSH_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the transmit
+ * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
+ * register.
+ *
+ * Values:
+ * - 0b0 - No flush operation occurs.
+ * - 0b1 - All data in the transmit FIFO/Buffer is cleared out.
+ */
+/*@{*/
+/*! @brief Set the TXFLUSH field to a new value. */
+#define UART_WR_CFIFO_TXFLUSH(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_TXFLUSH_MASK, UART_CFIFO_TXFLUSH(value)))
+#define UART_BWR_CFIFO_TXFLUSH(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXFLUSH_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_SFIFO - UART FIFO Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_SFIFO - UART FIFO Status Register (RW)
+ *
+ * Reset value: 0xC0U
+ *
+ * This register provides status information regarding the transmit and receiver
+ * buffers/FIFOs, including interrupt information. This register may be written
+ * to or read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_SFIFO register
+ */
+/*@{*/
+#define UART_RD_SFIFO(base)      (UART_SFIFO_REG(base))
+#define UART_WR_SFIFO(base, value) (UART_SFIFO_REG(base) = (value))
+#define UART_RMW_SFIFO(base, mask, value) (UART_WR_SFIFO(base, (UART_RD_SFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) |  (value)))
+#define UART_CLR_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) & ~(value)))
+#define UART_TOG_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_SFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_SFIFO, field RXUF[0] (W1C)
+ *
+ * Indicates that more data has been read from the receive buffer than was
+ * present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No receive buffer underflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one receive buffer underflow has occurred since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXUF field. */
+#define UART_RD_SFIFO_RXUF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXUF_MASK) >> UART_SFIFO_RXUF_SHIFT)
+#define UART_BRD_SFIFO_RXUF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXUF_SHIFT))
+
+/*! @brief Set the RXUF field to a new value. */
+#define UART_WR_SFIFO_RXUF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_RXUF_MASK | UART_SFIFO_TXOF_MASK | UART_SFIFO_RXOF_MASK), UART_SFIFO_RXUF(value)))
+#define UART_BWR_SFIFO_RXUF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field TXOF[1] (W1C)
+ *
+ * Indicates that more data has been written to the transmit buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
+ * flag is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No transmit buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one transmit buffer overflow has occurred since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_TXOF field. */
+#define UART_RD_SFIFO_TXOF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_TXOF_MASK) >> UART_SFIFO_TXOF_SHIFT)
+#define UART_BRD_SFIFO_TXOF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXOF_SHIFT))
+
+/*! @brief Set the TXOF field to a new value. */
+#define UART_WR_SFIFO_TXOF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_TXOF_MASK | UART_SFIFO_RXUF_MASK | UART_SFIFO_RXOF_MASK), UART_SFIFO_TXOF(value)))
+#define UART_BWR_SFIFO_TXOF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field RXOF[2] (W1C)
+ *
+ * Indicates that more data has been written to the receive buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No receive buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one receive buffer overflow has occurred since the last time
+ *     the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXOF field. */
+#define UART_RD_SFIFO_RXOF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXOF_MASK) >> UART_SFIFO_RXOF_SHIFT)
+#define UART_BRD_SFIFO_RXOF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXOF_SHIFT))
+
+/*! @brief Set the RXOF field to a new value. */
+#define UART_WR_SFIFO_RXOF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_RXOF_MASK | UART_SFIFO_RXUF_MASK | UART_SFIFO_TXOF_MASK), UART_SFIFO_RXOF(value)))
+#define UART_BWR_SFIFO_RXOF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field RXEMPT[6] (RO)
+ *
+ * Asserts when there is no data in the receive FIFO/Buffer. This field does not
+ * take into account data that is in the receive shift register.
+ *
+ * Values:
+ * - 0b0 - Receive buffer is not empty.
+ * - 0b1 - Receive buffer is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXEMPT field. */
+#define UART_RD_SFIFO_RXEMPT(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXEMPT_MASK) >> UART_SFIFO_RXEMPT_SHIFT)
+#define UART_BRD_SFIFO_RXEMPT(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXEMPT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field TXEMPT[7] (RO)
+ *
+ * Asserts when there is no data in the Transmit FIFO/buffer. This field does
+ * not take into account data that is in the transmit shift register.
+ *
+ * Values:
+ * - 0b0 - Transmit buffer is not empty.
+ * - 0b1 - Transmit buffer is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_TXEMPT field. */
+#define UART_RD_SFIFO_TXEMPT(base) ((UART_SFIFO_REG(base) & UART_SFIFO_TXEMPT_MASK) >> UART_SFIFO_TXEMPT_SHIFT)
+#define UART_BRD_SFIFO_TXEMPT(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXEMPT_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TWFIFO - UART FIFO Transmit Watermark
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TWFIFO - UART FIFO Transmit Watermark (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of needing additional transmit data. This register may be read at any
+ * time but must be written only when C2[TE] is not set. Changing the value of the
+ * watermark will not clear the S1[TDRE] flag.
+ */
+/*!
+ * @name Constants and macros for entire UART_TWFIFO register
+ */
+/*@{*/
+#define UART_RD_TWFIFO(base)     (UART_TWFIFO_REG(base))
+#define UART_WR_TWFIFO(base, value) (UART_TWFIFO_REG(base) = (value))
+#define UART_RMW_TWFIFO(base, mask, value) (UART_WR_TWFIFO(base, (UART_RD_TWFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) |  (value)))
+#define UART_CLR_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) & ~(value)))
+#define UART_TOG_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TCFIFO - UART FIFO Transmit Count
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TCFIFO - UART FIFO Transmit Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the transmit buffer/FIFO. It may be read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_TCFIFO register
+ */
+/*@{*/
+#define UART_RD_TCFIFO(base)     (UART_TCFIFO_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * UART_RWFIFO - UART FIFO Receive Watermark
+ ******************************************************************************/
+
+/*!
+ * @brief UART_RWFIFO - UART FIFO Receive Watermark (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of the need to remove data from the receiver FIFO/buffer. This register
+ * may be read at any time but must be written only when C2[RE] is not asserted.
+ * Changing the value in this register will not clear S1[RDRF].
+ */
+/*!
+ * @name Constants and macros for entire UART_RWFIFO register
+ */
+/*@{*/
+#define UART_RD_RWFIFO(base)     (UART_RWFIFO_REG(base))
+#define UART_WR_RWFIFO(base, value) (UART_RWFIFO_REG(base) = (value))
+#define UART_RMW_RWFIFO(base, mask, value) (UART_WR_RWFIFO(base, (UART_RD_RWFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) |  (value)))
+#define UART_CLR_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) & ~(value)))
+#define UART_TOG_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_RCFIFO - UART FIFO Receive Count
+ ******************************************************************************/
+
+/*!
+ * @brief UART_RCFIFO - UART FIFO Receive Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the receive FIFO/buffer. It may be read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_RCFIFO register
+ */
+/*@{*/
+#define UART_RD_RCFIFO(base)     (UART_RCFIFO_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C7816 - UART 7816 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C7816 - UART 7816 Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The C7816 register is the primary control register for ISO-7816 specific
+ * functionality. This register is specific to 7816 functionality and the values in
+ * this register have no effect on UART operation and should be ignored if
+ * ISO_7816E is not set/enabled. This register may be read at any time but values must
+ * be changed only when ISO_7816E is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_C7816 register
+ */
+/*@{*/
+#define UART_RD_C7816(base)      (UART_C7816_REG(base))
+#define UART_WR_C7816(base, value) (UART_C7816_REG(base) = (value))
+#define UART_RMW_C7816(base, mask, value) (UART_WR_C7816(base, (UART_RD_C7816(base) & ~(mask)) | (value)))
+#define UART_SET_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) |  (value)))
+#define UART_CLR_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) & ~(value)))
+#define UART_TOG_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C7816 bitfields
+ */
+
+/*!
+ * @name Register UART_C7816, field ISO_7816E[0] (RW)
+ *
+ * Indicates that the UART is operating according to the ISO-7816 protocol. This
+ * field must be modified only when no transmit or receive is occurring. If this
+ * field is changed during a data transfer, the data being transmitted or
+ * received may be transferred incorrectly.
+ *
+ * Values:
+ * - 0b0 - ISO-7816 functionality is turned off/not enabled.
+ * - 0b1 - ISO-7816 functionality is turned on/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ISO_7816E field. */
+#define UART_RD_C7816_ISO_7816E(base) ((UART_C7816_REG(base) & UART_C7816_ISO_7816E_MASK) >> UART_C7816_ISO_7816E_SHIFT)
+#define UART_BRD_C7816_ISO_7816E(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT))
+
+/*! @brief Set the ISO_7816E field to a new value. */
+#define UART_WR_C7816_ISO_7816E(base, value) (UART_RMW_C7816(base, UART_C7816_ISO_7816E_MASK, UART_C7816_ISO_7816E(value)))
+#define UART_BWR_C7816_ISO_7816E(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field TTYPE[1] (RW)
+ *
+ * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
+ * for more details.
+ *
+ * Values:
+ * - 0b0 - T = 0 per the ISO-7816 specification.
+ * - 0b1 - T = 1 per the ISO-7816 specification.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_TTYPE field. */
+#define UART_RD_C7816_TTYPE(base) ((UART_C7816_REG(base) & UART_C7816_TTYPE_MASK) >> UART_C7816_TTYPE_SHIFT)
+#define UART_BRD_C7816_TTYPE(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT))
+
+/*! @brief Set the TTYPE field to a new value. */
+#define UART_WR_C7816_TTYPE(base, value) (UART_RMW_C7816(base, UART_C7816_TTYPE_MASK, UART_C7816_TTYPE(value)))
+#define UART_BWR_C7816_TTYPE(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field INIT[2] (RW)
+ *
+ * When this field is set, all received characters are searched for a valid
+ * initial character. If an invalid initial character is identified, and ANACK is
+ * set, a NACK is sent. All received data is discarded and error flags blocked
+ * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
+ * until a valid initial character is detected. Upon detecting a valid initial
+ * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
+ * automatically updated to reflect the initial character that was received. The
+ * actual INIT data value is not stored in the receive buffer. Additionally, upon
+ * detection of a valid initial character, IS7816[INITD] is set and an interrupt
+ * issued as programmed by IE7816[INITDE]. When a valid initial character is
+ * detected, INIT is automatically cleared. This Initial Character Detect feature is
+ * supported only in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0b0 - Normal operating mode. Receiver does not seek to identify initial
+ *     character.
+ * - 0b1 - Receiver searches for initial character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_INIT field. */
+#define UART_RD_C7816_INIT(base) ((UART_C7816_REG(base) & UART_C7816_INIT_MASK) >> UART_C7816_INIT_SHIFT)
+#define UART_BRD_C7816_INIT(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT))
+
+/*! @brief Set the INIT field to a new value. */
+#define UART_WR_C7816_INIT(base, value) (UART_RMW_C7816(base, UART_C7816_INIT_MASK, UART_C7816_INIT(value)))
+#define UART_BWR_C7816_INIT(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ANACK[3] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a parity error occurs or if INIT is set and an invalid initial character is
+ * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
+ * attempts to retransmit the data indefinitely. To stop retransmission attempts,
+ * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
+ *
+ * Values:
+ * - 0b0 - No NACK is automatically generated.
+ * - 0b1 - A NACK is automatically generated if a parity error is detected or if
+ *     an invalid initial character is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ANACK field. */
+#define UART_RD_C7816_ANACK(base) ((UART_C7816_REG(base) & UART_C7816_ANACK_MASK) >> UART_C7816_ANACK_SHIFT)
+#define UART_BRD_C7816_ANACK(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT))
+
+/*! @brief Set the ANACK field to a new value. */
+#define UART_WR_C7816_ANACK(base, value) (UART_RMW_C7816(base, UART_C7816_ANACK_MASK, UART_C7816_ANACK(value)))
+#define UART_BWR_C7816_ANACK(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ONACK[4] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
+ * this results in the transmitter resending the packet that overflowed until the
+ * retransmit threshold for that transmitter is reached. A NACK is generated only
+ * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
+ * considerations
+ *
+ * Values:
+ * - 0b0 - The received data does not generate a NACK when the receipt of the
+ *     data results in an overflow event.
+ * - 0b1 - If the receiver buffer overflows, a NACK is automatically sent on a
+ *     received character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ONACK field. */
+#define UART_RD_C7816_ONACK(base) ((UART_C7816_REG(base) & UART_C7816_ONACK_MASK) >> UART_C7816_ONACK_SHIFT)
+#define UART_BRD_C7816_ONACK(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT))
+
+/*! @brief Set the ONACK field to a new value. */
+#define UART_WR_C7816_ONACK(base, value) (UART_RMW_C7816(base, UART_C7816_ONACK_MASK, UART_C7816_ONACK(value)))
+#define UART_BWR_C7816_ONACK(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IE7816 - UART 7816 Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IE7816 register controls which flags result in an interrupt being issued.
+ * This register is specific to 7816 functionality, the corresponding flags that
+ * drive the interrupts are not asserted when 7816E is not set/enabled. However,
+ * these flags may remain set if they are asserted while 7816E was set and not
+ * subsequently cleared. This register may be read or written to at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_IE7816 register
+ */
+/*@{*/
+#define UART_RD_IE7816(base)     (UART_IE7816_REG(base))
+#define UART_WR_IE7816(base, value) (UART_IE7816_REG(base) = (value))
+#define UART_RMW_IE7816(base, mask, value) (UART_WR_IE7816(base, (UART_RD_IE7816(base) & ~(mask)) | (value)))
+#define UART_SET_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) |  (value)))
+#define UART_CLR_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) & ~(value)))
+#define UART_TOG_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IE7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IE7816, field RXTE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[RXT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[RXT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_RXTE field. */
+#define UART_RD_IE7816_RXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_RXTE_MASK) >> UART_IE7816_RXTE_SHIFT)
+#define UART_BRD_IE7816_RXTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT))
+
+/*! @brief Set the RXTE field to a new value. */
+#define UART_WR_IE7816_RXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_RXTE_MASK, UART_IE7816_RXTE(value)))
+#define UART_BWR_IE7816_RXTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field TXTE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[TXT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[TXT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_TXTE field. */
+#define UART_RD_IE7816_TXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_TXTE_MASK) >> UART_IE7816_TXTE_SHIFT)
+#define UART_BRD_IE7816_TXTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT))
+
+/*! @brief Set the TXTE field to a new value. */
+#define UART_WR_IE7816_TXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_TXTE_MASK, UART_IE7816_TXTE(value)))
+#define UART_BWR_IE7816_TXTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field GTVE[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[GTV] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[GTV] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_GTVE field. */
+#define UART_RD_IE7816_GTVE(base) ((UART_IE7816_REG(base) & UART_IE7816_GTVE_MASK) >> UART_IE7816_GTVE_SHIFT)
+#define UART_BRD_IE7816_GTVE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT))
+
+/*! @brief Set the GTVE field to a new value. */
+#define UART_WR_IE7816_GTVE(base, value) (UART_RMW_IE7816(base, UART_IE7816_GTVE_MASK, UART_IE7816_GTVE(value)))
+#define UART_BWR_IE7816_GTVE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field INITDE[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[INITD] does not result in the generation of
+ *     an interrupt.
+ * - 0b1 - The assertion of IS7816[INITD] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_INITDE field. */
+#define UART_RD_IE7816_INITDE(base) ((UART_IE7816_REG(base) & UART_IE7816_INITDE_MASK) >> UART_IE7816_INITDE_SHIFT)
+#define UART_BRD_IE7816_INITDE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT))
+
+/*! @brief Set the INITDE field to a new value. */
+#define UART_WR_IE7816_INITDE(base, value) (UART_RMW_IE7816(base, UART_IE7816_INITDE_MASK, UART_IE7816_INITDE(value)))
+#define UART_BWR_IE7816_INITDE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field BWTE[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[BWT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[BWT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_BWTE field. */
+#define UART_RD_IE7816_BWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_BWTE_MASK) >> UART_IE7816_BWTE_SHIFT)
+#define UART_BRD_IE7816_BWTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT))
+
+/*! @brief Set the BWTE field to a new value. */
+#define UART_WR_IE7816_BWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_BWTE_MASK, UART_IE7816_BWTE(value)))
+#define UART_BWR_IE7816_BWTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field CWTE[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[CWT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[CWT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_CWTE field. */
+#define UART_RD_IE7816_CWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_CWTE_MASK) >> UART_IE7816_CWTE_SHIFT)
+#define UART_BRD_IE7816_CWTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT))
+
+/*! @brief Set the CWTE field to a new value. */
+#define UART_WR_IE7816_CWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_CWTE_MASK, UART_IE7816_CWTE(value)))
+#define UART_BWR_IE7816_CWTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field WTE[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[WT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[WT] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_WTE field. */
+#define UART_RD_IE7816_WTE(base) ((UART_IE7816_REG(base) & UART_IE7816_WTE_MASK) >> UART_IE7816_WTE_SHIFT)
+#define UART_BRD_IE7816_WTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT))
+
+/*! @brief Set the WTE field to a new value. */
+#define UART_WR_IE7816_WTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_WTE_MASK, UART_IE7816_WTE(value)))
+#define UART_BWR_IE7816_WTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IS7816 - UART 7816 Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IS7816 - UART 7816 Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IS7816 register provides a mechanism to read and clear the interrupt
+ * flags. All flags/interrupts are cleared by writing a 1 to the field location.
+ * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
+ * the flag condition that occurred since the last time the bit was cleared, not
+ * that the condition currently exists. The status flags are set regardless of
+ * whether the corresponding field in the IE7816 is set or cleared. The IE7816
+ * controls only if an interrupt is issued to the host processor. This register is
+ * specific to 7816 functionality and the values in this register have no affect on
+ * UART operation and should be ignored if 7816E is not set/enabled. This
+ * register may be read or written at anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_IS7816 register
+ */
+/*@{*/
+#define UART_RD_IS7816(base)     (UART_IS7816_REG(base))
+#define UART_WR_IS7816(base, value) (UART_IS7816_REG(base) = (value))
+#define UART_RMW_IS7816(base, mask, value) (UART_WR_IS7816(base, (UART_RD_IS7816(base) & ~(mask)) | (value)))
+#define UART_SET_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) |  (value)))
+#define UART_CLR_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) & ~(value)))
+#define UART_TOG_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IS7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IS7816, field RXT[0] (W1C)
+ *
+ * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
+ * generated in response to parity errors on received data. This flag requires ANACK
+ * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
+ * Clearing this field also resets the counter keeping track of consecutive NACKS. The
+ * UART will continue to attempt to receive data regardless of whether this flag
+ * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
+ * or packet is received without needing to issue a NACK, the internal NACK
+ * detection counter is cleared and the count restarts from zero on the next
+ * transmitted NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - The number of consecutive NACKS generated as a result of parity
+ *     errors and buffer overruns is less than or equal to the value in
+ *     ET7816[RXTHRESHOLD].
+ * - 0b1 - The number of consecutive NACKS generated as a result of parity
+ *     errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_RXT field. */
+#define UART_RD_IS7816_RXT(base) ((UART_IS7816_REG(base) & UART_IS7816_RXT_MASK) >> UART_IS7816_RXT_SHIFT)
+#define UART_BRD_IS7816_RXT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT))
+
+/*! @brief Set the RXT field to a new value. */
+#define UART_WR_IS7816_RXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_RXT(value)))
+#define UART_BWR_IS7816_RXT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field TXT[1] (W1C)
+ *
+ * Indicates that the transmit NACK threshold has been exceeded as indicated by
+ * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
+ * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
+ * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
+ * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
+ * internal NACK detection counter is cleared and the count restarts from zero on
+ * the next received NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - The number of retries and corresponding NACKS does not exceed the
+ *     value in ET7816[TXTHRESHOLD].
+ * - 0b1 - The number of retries and corresponding NACKS exceeds the value in
+ *     ET7816[TXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_TXT field. */
+#define UART_RD_IS7816_TXT(base) ((UART_IS7816_REG(base) & UART_IS7816_TXT_MASK) >> UART_IS7816_TXT_SHIFT)
+#define UART_BRD_IS7816_TXT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT))
+
+/*! @brief Set the TXT field to a new value. */
+#define UART_WR_IS7816_TXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_TXT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_TXT(value)))
+#define UART_BWR_IS7816_TXT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field GTV[2] (W1C)
+ *
+ * Indicates that one or more of the character guard time, block guard time, or
+ * guard time are violated. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - A guard time (GT, CGT, or BGT) has not been violated.
+ * - 0b1 - A guard time (GT, CGT, or BGT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_GTV field. */
+#define UART_RD_IS7816_GTV(base) ((UART_IS7816_REG(base) & UART_IS7816_GTV_MASK) >> UART_IS7816_GTV_SHIFT)
+#define UART_BRD_IS7816_GTV(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT))
+
+/*! @brief Set the GTV field to a new value. */
+#define UART_WR_IS7816_GTV(base, value) (UART_RMW_IS7816(base, (UART_IS7816_GTV_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_GTV(value)))
+#define UART_BWR_IS7816_GTV(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field INITD[4] (W1C)
+ *
+ * Indicates that a valid initial character is received. This interrupt is
+ * cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - A valid initial character has not been received.
+ * - 0b1 - A valid initial character has been received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_INITD field. */
+#define UART_RD_IS7816_INITD(base) ((UART_IS7816_REG(base) & UART_IS7816_INITD_MASK) >> UART_IS7816_INITD_SHIFT)
+#define UART_BRD_IS7816_INITD(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT))
+
+/*! @brief Set the INITD field to a new value. */
+#define UART_WR_IS7816_INITD(base, value) (UART_RMW_IS7816(base, (UART_IS7816_INITD_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_INITD(value)))
+#define UART_BWR_IS7816_INITD(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field BWT[5] (W1C)
+ *
+ * Indicates that the block wait time, the time between the leading edge of
+ * first received character of a block and the leading edge of the last character the
+ * previously transmitted block, has exceeded the programmed value. This flag
+ * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - Block wait time (BWT) has not been violated.
+ * - 0b1 - Block wait time (BWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_BWT field. */
+#define UART_RD_IS7816_BWT(base) ((UART_IS7816_REG(base) & UART_IS7816_BWT_MASK) >> UART_IS7816_BWT_SHIFT)
+#define UART_BRD_IS7816_BWT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT))
+
+/*! @brief Set the BWT field to a new value. */
+#define UART_WR_IS7816_BWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_BWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_BWT(value)))
+#define UART_BWR_IS7816_BWT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field CWT[6] (W1C)
+ *
+ * Indicates that the character wait time, the time between the leading edges of
+ * two consecutive characters in a block, has exceeded the programmed value.
+ * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
+ * writing 1.
+ *
+ * Values:
+ * - 0b0 - Character wait time (CWT) has not been violated.
+ * - 0b1 - Character wait time (CWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_CWT field. */
+#define UART_RD_IS7816_CWT(base) ((UART_IS7816_REG(base) & UART_IS7816_CWT_MASK) >> UART_IS7816_CWT_SHIFT)
+#define UART_BRD_IS7816_CWT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT))
+
+/*! @brief Set the CWT field to a new value. */
+#define UART_WR_IS7816_CWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_CWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_CWT(value)))
+#define UART_BWR_IS7816_CWT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field WT[7] (W1C)
+ *
+ * Indicates that the wait time, the time between the leading edge of a
+ * character being transmitted and the leading edge of the next response character, has
+ * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
+ * This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - Wait time (WT) has not been violated.
+ * - 0b1 - Wait time (WT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_WT field. */
+#define UART_RD_IS7816_WT(base) ((UART_IS7816_REG(base) & UART_IS7816_WT_MASK) >> UART_IS7816_WT_SHIFT)
+#define UART_BRD_IS7816_WT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT))
+
+/*! @brief Set the WT field to a new value. */
+#define UART_WR_IS7816_WT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_WT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK), UART_IS7816_WT(value)))
+#define UART_BWR_IS7816_WT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816T0 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816T0 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816T0 register
+ */
+/*@{*/
+#define UART_RD_WP7816T0(base)   (UART_WP7816T0_REG(base))
+#define UART_WR_WP7816T0(base, value) (UART_WP7816T0_REG(base) = (value))
+#define UART_RMW_WP7816T0(base, mask, value) (UART_WR_WP7816T0(base, (UART_RD_WP7816T0(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) |  (value)))
+#define UART_CLR_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) & ~(value)))
+#define UART_TOG_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816T1 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816T1 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816T1 register
+ */
+/*@{*/
+#define UART_RD_WP7816T1(base)   (UART_WP7816T1_REG(base))
+#define UART_WR_WP7816T1(base, value) (UART_WP7816T1_REG(base) = (value))
+#define UART_RMW_WP7816T1(base, mask, value) (UART_WR_WP7816T1(base, (UART_RD_WP7816T1(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) |  (value)))
+#define UART_CLR_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) & ~(value)))
+#define UART_TOG_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_WP7816T1 bitfields
+ */
+
+/*!
+ * @name Register UART_WP7816T1, field BWI[3:0] (RW)
+ *
+ * Used to calculate the value used for the BWT counter. It represent a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816T1_BWI field. */
+#define UART_RD_WP7816T1_BWI(base) ((UART_WP7816T1_REG(base) & UART_WP7816T1_BWI_MASK) >> UART_WP7816T1_BWI_SHIFT)
+#define UART_BRD_WP7816T1_BWI(base) (UART_RD_WP7816T1_BWI(base))
+
+/*! @brief Set the BWI field to a new value. */
+#define UART_WR_WP7816T1_BWI(base, value) (UART_RMW_WP7816T1(base, UART_WP7816T1_BWI_MASK, UART_WP7816T1_BWI(value)))
+#define UART_BWR_WP7816T1_BWI(base, value) (UART_WR_WP7816T1_BWI(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_WP7816T1, field CWI[7:4] (RW)
+ *
+ * Used to calculate the value used for the CWT counter. It represents a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816T1_CWI field. */
+#define UART_RD_WP7816T1_CWI(base) ((UART_WP7816T1_REG(base) & UART_WP7816T1_CWI_MASK) >> UART_WP7816T1_CWI_SHIFT)
+#define UART_BRD_WP7816T1_CWI(base) (UART_RD_WP7816T1_CWI(base))
+
+/*! @brief Set the CWI field to a new value. */
+#define UART_WR_WP7816T1_CWI(base, value) (UART_RMW_WP7816T1(base, UART_WP7816T1_CWI_MASK, UART_WP7816T1_CWI(value)))
+#define UART_BWR_WP7816T1_CWI(base, value) (UART_WR_WP7816T1_CWI(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WN7816 - UART 7816 Wait N Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WN7816 - UART 7816 Wait N Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The WN7816 register contains a parameter that is used in the calculation of
+ * the guard time counter. This register may be read at any time. This register
+ * must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WN7816 register
+ */
+/*@{*/
+#define UART_RD_WN7816(base)     (UART_WN7816_REG(base))
+#define UART_WR_WN7816(base, value) (UART_WN7816_REG(base) = (value))
+#define UART_RMW_WN7816(base, mask, value) (UART_WR_WN7816(base, (UART_RD_WN7816(base) & ~(mask)) | (value)))
+#define UART_SET_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) |  (value)))
+#define UART_CLR_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) & ~(value)))
+#define UART_TOG_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WF7816 - UART 7816 Wait FD Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WF7816 - UART 7816 Wait FD Register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * The WF7816 contains parameters that are used in the generation of various
+ * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WF7816 register
+ */
+/*@{*/
+#define UART_RD_WF7816(base)     (UART_WF7816_REG(base))
+#define UART_WR_WF7816(base, value) (UART_WF7816_REG(base) = (value))
+#define UART_RMW_WF7816(base, mask, value) (UART_WR_WF7816(base, (UART_RD_WF7816(base) & ~(mask)) | (value)))
+#define UART_SET_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) |  (value)))
+#define UART_CLR_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) & ~(value)))
+#define UART_TOG_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ET7816 - UART 7816 Error Threshold Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ET7816 - UART 7816 Error Threshold Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The ET7816 register contains fields that determine the number of NACKs that
+ * must be received or transmitted before the host processor is notified. This
+ * register may be read at anytime. This register must be written to only when
+ * C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_ET7816 register
+ */
+/*@{*/
+#define UART_RD_ET7816(base)     (UART_ET7816_REG(base))
+#define UART_WR_ET7816(base, value) (UART_ET7816_REG(base) = (value))
+#define UART_RMW_ET7816(base, mask, value) (UART_WR_ET7816(base, (UART_RD_ET7816(base) & ~(mask)) | (value)))
+#define UART_SET_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) |  (value)))
+#define UART_CLR_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) & ~(value)))
+#define UART_TOG_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ET7816 bitfields
+ */
+
+/*!
+ * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
+ *
+ * The value written to this field indicates the maximum number of consecutive
+ * NACKs generated as a result of a parity error or receiver buffer overruns
+ * before the host processor is notified. After the counter exceeds that value in the
+ * field, the IS7816[RXT] is asserted. This field is meaningful only when
+ * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
+ * NACKs that have been transmitted since the last successful reception. This
+ * counter saturates at 4'hF and does not wrap around. Regardless of the number of
+ * NACKs sent, the UART continues to receive valid packets indefinitely. For
+ * additional information, see IS7816[RXT] field description.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */
+#define UART_RD_ET7816_RXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_RXTHRESHOLD_MASK) >> UART_ET7816_RXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_RXTHRESHOLD(base) (UART_RD_ET7816_RXTHRESHOLD(base))
+
+/*! @brief Set the RXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_RXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_RXTHRESHOLD_MASK, UART_ET7816_RXTHRESHOLD(value)))
+#define UART_BWR_ET7816_RXTHRESHOLD(base, value) (UART_WR_ET7816_RXTHRESHOLD(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
+ *
+ * The value written to this field indicates the maximum number of failed
+ * attempts (NACKs) a transmitted character can have before the host processor is
+ * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
+ * The value read from this field represents the number of consecutive NACKs
+ * that have been received since the last successful transmission. This counter
+ * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
+ * received, the UART continues to retransmit indefinitely. This flag only
+ * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
+ * description.
+ *
+ * Values:
+ * - 0b0000 - TXT asserts on the first NACK that is received.
+ * - 0b0001 - TXT asserts on the second NACK that is received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */
+#define UART_RD_ET7816_TXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_TXTHRESHOLD_MASK) >> UART_ET7816_TXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_TXTHRESHOLD(base) (UART_RD_ET7816_TXTHRESHOLD(base))
+
+/*! @brief Set the TXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_TXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_TXTHRESHOLD_MASK, UART_ET7816_TXTHRESHOLD(value)))
+#define UART_BWR_ET7816_TXTHRESHOLD(base, value) (UART_WR_ET7816_TXTHRESHOLD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TL7816 - UART 7816 Transmit Length Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TL7816 - UART 7816 Transmit Length Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The TL7816 register is used to indicate the number of characters contained in
+ * the block being transmitted. This register is used only when C7816[TTYPE] =
+ * 1. This register may be read at anytime. This register must be written only
+ * when C2[TE] is not enabled.
+ */
+/*!
+ * @name Constants and macros for entire UART_TL7816 register
+ */
+/*@{*/
+#define UART_RD_TL7816(base)     (UART_TL7816_REG(base))
+#define UART_WR_TL7816(base, value) (UART_TL7816_REG(base) = (value))
+#define UART_RMW_TL7816(base, mask, value) (UART_WR_TL7816(base, (UART_RD_TL7816(base) & ~(mask)) | (value)))
+#define UART_SET_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) |  (value)))
+#define UART_CLR_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) & ~(value)))
+#define UART_TOG_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 USB
+ *
+ * Universal Serial Bus, OTG Capable Controller
+ *
+ * Registers defined in this header file:
+ * - USB_PERID - Peripheral ID register
+ * - USB_IDCOMP - Peripheral ID Complement register
+ * - USB_REV - Peripheral Revision register
+ * - USB_ADDINFO - Peripheral Additional Info register
+ * - USB_OTGISTAT - OTG Interrupt Status register
+ * - USB_OTGICR - OTG Interrupt Control register
+ * - USB_OTGSTAT - OTG Status register
+ * - USB_OTGCTL - OTG Control register
+ * - USB_ISTAT - Interrupt Status register
+ * - USB_INTEN - Interrupt Enable register
+ * - USB_ERRSTAT - Error Interrupt Status register
+ * - USB_ERREN - Error Interrupt Enable register
+ * - USB_STAT - Status register
+ * - USB_CTL - Control register
+ * - USB_ADDR - Address register
+ * - USB_BDTPAGE1 - BDT Page register 1
+ * - USB_FRMNUML - Frame Number register Low
+ * - USB_FRMNUMH - Frame Number register High
+ * - USB_TOKEN - Token register
+ * - USB_SOFTHLD - SOF Threshold register
+ * - USB_BDTPAGE2 - BDT Page Register 2
+ * - USB_BDTPAGE3 - BDT Page Register 3
+ * - USB_ENDPT - Endpoint Control register
+ * - USB_USBCTRL - USB Control register
+ * - USB_OBSERVE - USB OTG Observe register
+ * - USB_CONTROL - USB OTG Control register
+ * - USB_USBTRC0 - USB Transceiver Control register 0
+ * - USB_USBFRMADJUST - Frame Adjust Register
+ * - USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ * - USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ * - USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ */
+
+#define USB_INSTANCE_COUNT (1U) /*!< Number of instances of the USB module. */
+#define USB0_IDX (0U) /*!< Instance number for USB0. */
+
+/*******************************************************************************
+ * USB_PERID - Peripheral ID register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_PERID - Peripheral ID register (RO)
+ *
+ * Reset value: 0x04U
+ *
+ * Reads back the value of 0x04. This value is defined for the USB peripheral.
+ */
+/*!
+ * @name Constants and macros for entire USB_PERID register
+ */
+/*@{*/
+#define USB_RD_PERID(base)       (USB_PERID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_PERID bitfields
+ */
+
+/*!
+ * @name Register USB_PERID, field ID[5:0] (RO)
+ *
+ * This field always reads 0x4h.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_PERID_ID field. */
+#define USB_RD_PERID_ID(base) ((USB_PERID_REG(base) & USB_PERID_ID_MASK) >> USB_PERID_ID_SHIFT)
+#define USB_BRD_PERID_ID(base) (USB_RD_PERID_ID(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_IDCOMP - Peripheral ID Complement register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_IDCOMP - Peripheral ID Complement register (RO)
+ *
+ * Reset value: 0xFBU
+ *
+ * Reads back the complement of the Peripheral ID register. For the USB
+ * peripheral, the value is 0xFB.
+ */
+/*!
+ * @name Constants and macros for entire USB_IDCOMP register
+ */
+/*@{*/
+#define USB_RD_IDCOMP(base)      (USB_IDCOMP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_IDCOMP bitfields
+ */
+
+/*!
+ * @name Register USB_IDCOMP, field NID[5:0] (RO)
+ *
+ * Ones' complement of PERID[ID]. bits.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_IDCOMP_NID field. */
+#define USB_RD_IDCOMP_NID(base) ((USB_IDCOMP_REG(base) & USB_IDCOMP_NID_MASK) >> USB_IDCOMP_NID_SHIFT)
+#define USB_BRD_IDCOMP_NID(base) (USB_RD_IDCOMP_NID(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_REV - Peripheral Revision register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_REV - Peripheral Revision register (RO)
+ *
+ * Reset value: 0x33U
+ *
+ * Contains the revision number of the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_REV register
+ */
+/*@{*/
+#define USB_RD_REV(base)         (USB_REV_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDINFO - Peripheral Additional Info register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDINFO - Peripheral Additional Info register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with
+ * the Host Enable bit.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDINFO register
+ */
+/*@{*/
+#define USB_RD_ADDINFO(base)     (USB_ADDINFO_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDINFO bitfields
+ */
+
+/*!
+ * @name Register USB_ADDINFO, field IEHOST[0] (RO)
+ *
+ * This bit is set if host mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IEHOST field. */
+#define USB_RD_ADDINFO_IEHOST(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IEHOST_MASK) >> USB_ADDINFO_IEHOST_SHIFT)
+#define USB_BRD_ADDINFO_IEHOST(base) (BITBAND_ACCESS8(&USB_ADDINFO_REG(base), USB_ADDINFO_IEHOST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_ADDINFO, field IRQNUM[7:3] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IRQNUM field. */
+#define USB_RD_ADDINFO_IRQNUM(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IRQNUM_MASK) >> USB_ADDINFO_IRQNUM_SHIFT)
+#define USB_BRD_ADDINFO_IRQNUM(base) (USB_RD_ADDINFO_IRQNUM(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGISTAT - OTG Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGISTAT - OTG Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Records changes of the ID sense and VBUS signals. Software can read this
+ * register to determine the event that triggers an interrupt. Only bits that have
+ * changed since the last software read are set. Writing a one to a bit clears the
+ * associated interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGISTAT register
+ */
+/*@{*/
+#define USB_RD_OTGISTAT(base)    (USB_OTGISTAT_REG(base))
+#define USB_WR_OTGISTAT(base, value) (USB_OTGISTAT_REG(base) = (value))
+#define USB_RMW_OTGISTAT(base, mask, value) (USB_WR_OTGISTAT(base, (USB_RD_OTGISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) |  (value)))
+#define USB_CLR_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) & ~(value)))
+#define USB_TOG_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on an A device.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field. */
+#define USB_RD_OTGISTAT_AVBUSCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_AVBUSCHG_MASK) >> USB_OTGISTAT_AVBUSCHG_SHIFT)
+#define USB_BRD_OTGISTAT_AVBUSCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_AVBUSCHG_SHIFT))
+
+/*! @brief Set the AVBUSCHG field to a new value. */
+#define USB_WR_OTGISTAT_AVBUSCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_AVBUSCHG_MASK, USB_OTGISTAT_AVBUSCHG(value)))
+#define USB_BWR_OTGISTAT_AVBUSCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_AVBUSCHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on a B device.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field. */
+#define USB_RD_OTGISTAT_B_SESS_CHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_B_SESS_CHG_MASK) >> USB_OTGISTAT_B_SESS_CHG_SHIFT)
+#define USB_BRD_OTGISTAT_B_SESS_CHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_B_SESS_CHG_SHIFT))
+
+/*! @brief Set the B_SESS_CHG field to a new value. */
+#define USB_WR_OTGISTAT_B_SESS_CHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_B_SESS_CHG_MASK, USB_OTGISTAT_B_SESS_CHG(value)))
+#define USB_BWR_OTGISTAT_B_SESS_CHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_B_SESS_CHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW)
+ *
+ * This bit is set when a change in VBUS is detected indicating a session valid
+ * or a session no longer valid.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field. */
+#define USB_RD_OTGISTAT_SESSVLDCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_SESSVLDCHG_MASK) >> USB_OTGISTAT_SESSVLDCHG_SHIFT)
+#define USB_BRD_OTGISTAT_SESSVLDCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_SESSVLDCHG_SHIFT))
+
+/*! @brief Set the SESSVLDCHG field to a new value. */
+#define USB_WR_OTGISTAT_SESSVLDCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_SESSVLDCHG_MASK, USB_OTGISTAT_SESSVLDCHG(value)))
+#define USB_BWR_OTGISTAT_SESSVLDCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_SESSVLDCHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW)
+ *
+ * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits)
+ * are stable without change for 1 millisecond, and the value of the line state
+ * is different from the last time when the line state was stable. It is set on
+ * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
+ * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt
+ * can be used in detecting Reset, Resume, Connect, and Data Line Pulse
+ * signaling.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field. */
+#define USB_RD_OTGISTAT_LINE_STATE_CHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_LINE_STATE_CHG_MASK) >> USB_OTGISTAT_LINE_STATE_CHG_SHIFT)
+#define USB_BRD_OTGISTAT_LINE_STATE_CHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_LINE_STATE_CHG_SHIFT))
+
+/*! @brief Set the LINE_STATE_CHG field to a new value. */
+#define USB_WR_OTGISTAT_LINE_STATE_CHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_LINE_STATE_CHG_MASK, USB_OTGISTAT_LINE_STATE_CHG(value)))
+#define USB_BWR_OTGISTAT_LINE_STATE_CHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_LINE_STATE_CHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW)
+ *
+ * This bit is set when the 1 millisecond timer expires. This bit stays asserted
+ * until cleared by software. The interrupt must be serviced every millisecond
+ * to avoid losing 1msec counts.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_ONEMSEC field. */
+#define USB_RD_OTGISTAT_ONEMSEC(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_ONEMSEC_MASK) >> USB_OTGISTAT_ONEMSEC_SHIFT)
+#define USB_BRD_OTGISTAT_ONEMSEC(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_ONEMSEC_SHIFT))
+
+/*! @brief Set the ONEMSEC field to a new value. */
+#define USB_WR_OTGISTAT_ONEMSEC(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_ONEMSEC_MASK, USB_OTGISTAT_ONEMSEC(value)))
+#define USB_BWR_OTGISTAT_ONEMSEC(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_ONEMSEC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field IDCHG[7] (RW)
+ *
+ * This bit is set when a change in the ID Signal from the USB connector is
+ * sensed.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_IDCHG field. */
+#define USB_RD_OTGISTAT_IDCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_IDCHG_MASK) >> USB_OTGISTAT_IDCHG_SHIFT)
+#define USB_BRD_OTGISTAT_IDCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_IDCHG_SHIFT))
+
+/*! @brief Set the IDCHG field to a new value. */
+#define USB_WR_OTGISTAT_IDCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_IDCHG_MASK, USB_OTGISTAT_IDCHG(value)))
+#define USB_BWR_OTGISTAT_IDCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_IDCHG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGICR - OTG Interrupt Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGICR - OTG Interrupt Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Enables the corresponding interrupt status bits defined in the OTG Interrupt
+ * Status Register.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGICR register
+ */
+/*@{*/
+#define USB_RD_OTGICR(base)      (USB_OTGICR_REG(base))
+#define USB_WR_OTGICR(base, value) (USB_OTGICR_REG(base) = (value))
+#define USB_RMW_OTGICR(base, mask, value) (USB_WR_OTGICR(base, (USB_RD_OTGICR(base) & ~(mask)) | (value)))
+#define USB_SET_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) |  (value)))
+#define USB_CLR_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) & ~(value)))
+#define USB_TOG_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGICR bitfields
+ */
+
+/*!
+ * @name Register USB_OTGICR, field AVBUSEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the AVBUSCHG interrupt.
+ * - 0b1 - Enables the AVBUSCHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_AVBUSEN field. */
+#define USB_RD_OTGICR_AVBUSEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_AVBUSEN_MASK) >> USB_OTGICR_AVBUSEN_SHIFT)
+#define USB_BRD_OTGICR_AVBUSEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_AVBUSEN_SHIFT))
+
+/*! @brief Set the AVBUSEN field to a new value. */
+#define USB_WR_OTGICR_AVBUSEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_AVBUSEN_MASK, USB_OTGICR_AVBUSEN(value)))
+#define USB_BWR_OTGICR_AVBUSEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_AVBUSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field BSESSEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the B_SESS_CHG interrupt.
+ * - 0b1 - Enables the B_SESS_CHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_BSESSEN field. */
+#define USB_RD_OTGICR_BSESSEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_BSESSEN_MASK) >> USB_OTGICR_BSESSEN_SHIFT)
+#define USB_BRD_OTGICR_BSESSEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_BSESSEN_SHIFT))
+
+/*! @brief Set the BSESSEN field to a new value. */
+#define USB_WR_OTGICR_BSESSEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_BSESSEN_MASK, USB_OTGICR_BSESSEN(value)))
+#define USB_BWR_OTGICR_BSESSEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_BSESSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field SESSVLDEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the SESSVLDCHG interrupt.
+ * - 0b1 - Enables the SESSVLDCHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_SESSVLDEN field. */
+#define USB_RD_OTGICR_SESSVLDEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_SESSVLDEN_MASK) >> USB_OTGICR_SESSVLDEN_SHIFT)
+#define USB_BRD_OTGICR_SESSVLDEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_SESSVLDEN_SHIFT))
+
+/*! @brief Set the SESSVLDEN field to a new value. */
+#define USB_WR_OTGICR_SESSVLDEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_SESSVLDEN_MASK, USB_OTGICR_SESSVLDEN(value)))
+#define USB_BWR_OTGICR_SESSVLDEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_SESSVLDEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field LINESTATEEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the LINE_STAT_CHG interrupt.
+ * - 0b1 - Enables the LINE_STAT_CHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_LINESTATEEN field. */
+#define USB_RD_OTGICR_LINESTATEEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_LINESTATEEN_MASK) >> USB_OTGICR_LINESTATEEN_SHIFT)
+#define USB_BRD_OTGICR_LINESTATEEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_LINESTATEEN_SHIFT))
+
+/*! @brief Set the LINESTATEEN field to a new value. */
+#define USB_WR_OTGICR_LINESTATEEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_LINESTATEEN_MASK, USB_OTGICR_LINESTATEEN(value)))
+#define USB_BWR_OTGICR_LINESTATEEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_LINESTATEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field ONEMSECEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Diables the 1ms timer interrupt.
+ * - 0b1 - Enables the 1ms timer interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_ONEMSECEN field. */
+#define USB_RD_OTGICR_ONEMSECEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_ONEMSECEN_MASK) >> USB_OTGICR_ONEMSECEN_SHIFT)
+#define USB_BRD_OTGICR_ONEMSECEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_ONEMSECEN_SHIFT))
+
+/*! @brief Set the ONEMSECEN field to a new value. */
+#define USB_WR_OTGICR_ONEMSECEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_ONEMSECEN_MASK, USB_OTGICR_ONEMSECEN(value)))
+#define USB_BWR_OTGICR_ONEMSECEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_ONEMSECEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field IDEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The ID interrupt is disabled
+ * - 0b1 - The ID interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_IDEN field. */
+#define USB_RD_OTGICR_IDEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_IDEN_MASK) >> USB_OTGICR_IDEN_SHIFT)
+#define USB_BRD_OTGICR_IDEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_IDEN_SHIFT))
+
+/*! @brief Set the IDEN field to a new value. */
+#define USB_WR_OTGICR_IDEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_IDEN_MASK, USB_OTGICR_IDEN(value)))
+#define USB_BWR_OTGICR_IDEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_IDEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGSTAT - OTG Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGSTAT - OTG Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Displays the actual value from the external comparator outputs of the ID pin
+ * and VBUS.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGSTAT register
+ */
+/*@{*/
+#define USB_RD_OTGSTAT(base)     (USB_OTGSTAT_REG(base))
+#define USB_WR_OTGSTAT(base, value) (USB_OTGSTAT_REG(base) = (value))
+#define USB_RMW_OTGSTAT(base, mask, value) (USB_WR_OTGSTAT(base, (USB_RD_OTGSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) |  (value)))
+#define USB_CLR_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) & ~(value)))
+#define USB_TOG_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is below the A VBUS Valid threshold.
+ * - 0b1 - The VBUS voltage is above the A VBUS Valid threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field. */
+#define USB_RD_OTGSTAT_AVBUSVLD(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_AVBUSVLD_MASK) >> USB_OTGSTAT_AVBUSVLD_SHIFT)
+#define USB_BRD_OTGSTAT_AVBUSVLD(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_AVBUSVLD_SHIFT))
+
+/*! @brief Set the AVBUSVLD field to a new value. */
+#define USB_WR_OTGSTAT_AVBUSVLD(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_AVBUSVLD_MASK, USB_OTGSTAT_AVBUSVLD(value)))
+#define USB_BWR_OTGSTAT_AVBUSVLD(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_AVBUSVLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field BSESSEND[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is above the B session end threshold.
+ * - 0b1 - The VBUS voltage is below the B session end threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_BSESSEND field. */
+#define USB_RD_OTGSTAT_BSESSEND(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_BSESSEND_MASK) >> USB_OTGSTAT_BSESSEND_SHIFT)
+#define USB_BRD_OTGSTAT_BSESSEND(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_BSESSEND_SHIFT))
+
+/*! @brief Set the BSESSEND field to a new value. */
+#define USB_WR_OTGSTAT_BSESSEND(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_BSESSEND_MASK, USB_OTGSTAT_BSESSEND(value)))
+#define USB_BWR_OTGSTAT_BSESSEND(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_BSESSEND_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is below the B session valid threshold
+ * - 0b1 - The VBUS voltage is above the B session valid threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_SESS_VLD field. */
+#define USB_RD_OTGSTAT_SESS_VLD(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_SESS_VLD_MASK) >> USB_OTGSTAT_SESS_VLD_SHIFT)
+#define USB_BRD_OTGSTAT_SESS_VLD(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_SESS_VLD_SHIFT))
+
+/*! @brief Set the SESS_VLD field to a new value. */
+#define USB_WR_OTGSTAT_SESS_VLD(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_SESS_VLD_MASK, USB_OTGSTAT_SESS_VLD(value)))
+#define USB_BWR_OTGSTAT_SESS_VLD(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_SESS_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
+ *
+ * Indicates that the internal signals that control the LINE_STATE_CHG field of
+ * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG
+ * field and then read this field. If this field reads as 1, then the value of
+ * LINE_STATE_CHG can be considered stable.
+ *
+ * Values:
+ * - 0b0 - The LINE_STAT_CHG bit is not yet stable.
+ * - 0b1 - The LINE_STAT_CHG bit has been debounced and is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field. */
+#define USB_RD_OTGSTAT_LINESTATESTABLE(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_LINESTATESTABLE_MASK) >> USB_OTGSTAT_LINESTATESTABLE_SHIFT)
+#define USB_BRD_OTGSTAT_LINESTATESTABLE(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_LINESTATESTABLE_SHIFT))
+
+/*! @brief Set the LINESTATESTABLE field to a new value. */
+#define USB_WR_OTGSTAT_LINESTATESTABLE(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_LINESTATESTABLE_MASK, USB_OTGSTAT_LINESTATESTABLE(value)))
+#define USB_BWR_OTGSTAT_LINESTATESTABLE(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_LINESTATESTABLE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW)
+ *
+ * This bit is reserved for the 1ms count, but it is not useful to software.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field. */
+#define USB_RD_OTGSTAT_ONEMSECEN(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_ONEMSECEN_MASK) >> USB_OTGSTAT_ONEMSECEN_SHIFT)
+#define USB_BRD_OTGSTAT_ONEMSECEN(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ONEMSECEN_SHIFT))
+
+/*! @brief Set the ONEMSECEN field to a new value. */
+#define USB_WR_OTGSTAT_ONEMSECEN(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_ONEMSECEN_MASK, USB_OTGSTAT_ONEMSECEN(value)))
+#define USB_BWR_OTGSTAT_ONEMSECEN(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ONEMSECEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field ID[7] (RW)
+ *
+ * Indicates the current state of the ID pin on the USB connector
+ *
+ * Values:
+ * - 0b0 - Indicates a Type A cable is plugged into the USB connector.
+ * - 0b1 - Indicates no cable is attached or a Type B cable is plugged into the
+ *     USB connector.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_ID field. */
+#define USB_RD_OTGSTAT_ID(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_ID_MASK) >> USB_OTGSTAT_ID_SHIFT)
+#define USB_BRD_OTGSTAT_ID(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ID_SHIFT))
+
+/*! @brief Set the ID field to a new value. */
+#define USB_WR_OTGSTAT_ID(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_ID_MASK, USB_OTGSTAT_ID(value)))
+#define USB_BWR_OTGSTAT_ID(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ID_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGCTL - OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGCTL - OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Controls the operation of VBUS and Data Line termination resistors.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGCTL register
+ */
+/*@{*/
+#define USB_RD_OTGCTL(base)      (USB_OTGCTL_REG(base))
+#define USB_WR_OTGCTL(base, value) (USB_OTGCTL_REG(base) = (value))
+#define USB_RMW_OTGCTL(base, mask, value) (USB_WR_OTGCTL(base, (USB_RD_OTGCTL(base) & ~(mask)) | (value)))
+#define USB_SET_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) |  (value)))
+#define USB_CLR_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) & ~(value)))
+#define USB_TOG_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGCTL bitfields
+ */
+
+/*!
+ * @name Register USB_OTGCTL, field OTGEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then
+ *     the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+
+ *     and D- Data Line pull-down resistors are engaged.
+ * - 0b1 - The pull-up and pull-down controls in this register are used.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_OTGEN field. */
+#define USB_RD_OTGCTL_OTGEN(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_OTGEN_MASK) >> USB_OTGCTL_OTGEN_SHIFT)
+#define USB_BRD_OTGCTL_OTGEN(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_OTGEN_SHIFT))
+
+/*! @brief Set the OTGEN field to a new value. */
+#define USB_WR_OTGCTL_OTGEN(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_OTGEN_MASK, USB_OTGCTL_OTGEN(value)))
+#define USB_BWR_OTGCTL_OTGEN(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_OTGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DMLOW[4] (RW)
+ *
+ * Values:
+ * - 0b0 - D- pulldown resistor is not enabled.
+ * - 0b1 - D- pulldown resistor is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DMLOW field. */
+#define USB_RD_OTGCTL_DMLOW(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DMLOW_MASK) >> USB_OTGCTL_DMLOW_SHIFT)
+#define USB_BRD_OTGCTL_DMLOW(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DMLOW_SHIFT))
+
+/*! @brief Set the DMLOW field to a new value. */
+#define USB_WR_OTGCTL_DMLOW(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DMLOW_MASK, USB_OTGCTL_DMLOW(value)))
+#define USB_BWR_OTGCTL_DMLOW(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DMLOW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DPLOW[5] (RW)
+ *
+ * This bit should always be enabled together with bit 4 (DMLOW)
+ *
+ * Values:
+ * - 0b0 - D+ pulldown resistor is not enabled.
+ * - 0b1 - D+ pulldown resistor is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPLOW field. */
+#define USB_RD_OTGCTL_DPLOW(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPLOW_MASK) >> USB_OTGCTL_DPLOW_SHIFT)
+#define USB_BRD_OTGCTL_DPLOW(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPLOW_SHIFT))
+
+/*! @brief Set the DPLOW field to a new value. */
+#define USB_WR_OTGCTL_DPLOW(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPLOW_MASK, USB_OTGCTL_DPLOW(value)))
+#define USB_BWR_OTGCTL_DPLOW(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPLOW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DPHIGH[7] (RW)
+ *
+ * Values:
+ * - 0b0 - D+ pullup resistor is not enabled
+ * - 0b1 - D+ pullup resistor is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPHIGH field. */
+#define USB_RD_OTGCTL_DPHIGH(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPHIGH_MASK) >> USB_OTGCTL_DPHIGH_SHIFT)
+#define USB_BRD_OTGCTL_DPHIGH(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT))
+
+/*! @brief Set the DPHIGH field to a new value. */
+#define USB_WR_OTGCTL_DPHIGH(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPHIGH_MASK, USB_OTGCTL_DPHIGH(value)))
+#define USB_BWR_OTGCTL_DPHIGH(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ISTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ISTAT - Interrupt Status register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains fields for each of the interrupt sources within the USB Module. Each
+ * of these fields are qualified with their respective interrupt enable bits.
+ * All fields of this register are logically OR'd together along with the OTG
+ * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the
+ * processor's interrupt controller. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ISTAT register
+ */
+/*@{*/
+#define USB_RD_ISTAT(base)       (USB_ISTAT_REG(base))
+#define USB_WR_ISTAT(base, value) (USB_ISTAT_REG(base) = (value))
+#define USB_RMW_ISTAT(base, mask, value) (USB_WR_ISTAT(base, (USB_RD_ISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) |  (value)))
+#define USB_CLR_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) & ~(value)))
+#define USB_TOG_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ISTAT, field USBRST[0] (W1C)
+ *
+ * This bit is set when the USB Module has decoded a valid USB reset. This
+ * informs the processor that it should write 0x00 into the address register and
+ * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5
+ * microseconds. It is not asserted again until the USB reset condition has been
+ * removed and then reasserted.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_USBRST field. */
+#define USB_RD_ISTAT_USBRST(base) ((USB_ISTAT_REG(base) & USB_ISTAT_USBRST_MASK) >> USB_ISTAT_USBRST_SHIFT)
+#define USB_BRD_ISTAT_USBRST(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT))
+
+/*! @brief Set the USBRST field to a new value. */
+#define USB_WR_ISTAT_USBRST(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_USBRST(value)))
+#define USB_BWR_ISTAT_USBRST(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ERROR[1] (W1C)
+ *
+ * This bit is set when any of the error conditions within Error Interrupt
+ * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register
+ * to determine the source of the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ERROR field. */
+#define USB_RD_ISTAT_ERROR(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ERROR_MASK) >> USB_ISTAT_ERROR_SHIFT)
+#define USB_BRD_ISTAT_ERROR(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT))
+
+/*! @brief Set the ERROR field to a new value. */
+#define USB_WR_ISTAT_ERROR(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ERROR_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ERROR(value)))
+#define USB_BWR_ISTAT_ERROR(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SOFTOK[2] (W1C)
+ *
+ * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In
+ * Host mode this field is set when the SOF threshold is reached, so that
+ * software can prepare for the next SOF.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SOFTOK field. */
+#define USB_RD_ISTAT_SOFTOK(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SOFTOK_MASK) >> USB_ISTAT_SOFTOK_SHIFT)
+#define USB_BRD_ISTAT_SOFTOK(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT))
+
+/*! @brief Set the SOFTOK field to a new value. */
+#define USB_WR_ISTAT_SOFTOK(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SOFTOK_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SOFTOK(value)))
+#define USB_BWR_ISTAT_SOFTOK(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field TOKDNE[3] (W1C)
+ *
+ * This bit is set when the current token being processed has completed. The
+ * processor must immediately read the STATUS (STAT) register to determine the
+ * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes
+ * STAT to be cleared or the STAT holding register to be loaded into the STAT
+ * register.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_TOKDNE field. */
+#define USB_RD_ISTAT_TOKDNE(base) ((USB_ISTAT_REG(base) & USB_ISTAT_TOKDNE_MASK) >> USB_ISTAT_TOKDNE_SHIFT)
+#define USB_BRD_ISTAT_TOKDNE(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT))
+
+/*! @brief Set the TOKDNE field to a new value. */
+#define USB_WR_ISTAT_TOKDNE(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_TOKDNE_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_TOKDNE(value)))
+#define USB_BWR_ISTAT_TOKDNE(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SLEEP[4] (W1C)
+ *
+ * This bit is set when the USB Module detects a constant idle on the USB bus
+ * for 3 ms. The sleep timer is reset by activity on the USB bus.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SLEEP field. */
+#define USB_RD_ISTAT_SLEEP(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SLEEP_MASK) >> USB_ISTAT_SLEEP_SHIFT)
+#define USB_BRD_ISTAT_SLEEP(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define USB_WR_ISTAT_SLEEP(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SLEEP_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SLEEP(value)))
+#define USB_BWR_ISTAT_SLEEP(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field RESUME[5] (W1C)
+ *
+ * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us.
+ * When not in suspend mode this interrupt must be disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_RESUME field. */
+#define USB_RD_ISTAT_RESUME(base) ((USB_ISTAT_REG(base) & USB_ISTAT_RESUME_MASK) >> USB_ISTAT_RESUME_SHIFT)
+#define USB_BRD_ISTAT_RESUME(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_ISTAT_RESUME(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_RESUME_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_RESUME(value)))
+#define USB_BWR_ISTAT_RESUME(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ATTACH[6] (W1C)
+ *
+ * This bit is set when the USB Module detects an attach of a USB device. This
+ * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a
+ * peripheral is now present and must be configured; it is asserted if there have
+ * been no transitions on the USB for 2.5 us and the current bus state is not SE0."
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ATTACH field. */
+#define USB_RD_ISTAT_ATTACH(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ATTACH_MASK) >> USB_ISTAT_ATTACH_SHIFT)
+#define USB_BRD_ISTAT_ATTACH(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ATTACH_SHIFT))
+
+/*! @brief Set the ATTACH field to a new value. */
+#define USB_WR_ISTAT_ATTACH(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ATTACH_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ATTACH(value)))
+#define USB_BWR_ISTAT_ATTACH(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ATTACH_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field STALL[7] (W1C)
+ *
+ * In Target mode this bit is asserted when a STALL handshake is sent by the
+ * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge
+ * during the handshake phase of a USB transaction.This interrupt can be used to
+ * determine whether the last USB transaction was completed successfully or
+ * stalled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_STALL field. */
+#define USB_RD_ISTAT_STALL(base) ((USB_ISTAT_REG(base) & USB_ISTAT_STALL_MASK) >> USB_ISTAT_STALL_SHIFT)
+#define USB_BRD_ISTAT_STALL(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT))
+
+/*! @brief Set the STALL field to a new value. */
+#define USB_WR_ISTAT_STALL(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_STALL_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK), USB_ISTAT_STALL(value)))
+#define USB_BWR_ISTAT_STALL(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_INTEN - Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_INTEN - Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable fields for each of the interrupt sources within the USB
+ * Module. Setting any of these bits enables the respective interrupt source in the
+ * ISTAT register. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_INTEN register
+ */
+/*@{*/
+#define USB_RD_INTEN(base)       (USB_INTEN_REG(base))
+#define USB_WR_INTEN(base, value) (USB_INTEN_REG(base) = (value))
+#define USB_RMW_INTEN(base, mask, value) (USB_WR_INTEN(base, (USB_RD_INTEN(base) & ~(mask)) | (value)))
+#define USB_SET_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) |  (value)))
+#define USB_CLR_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) & ~(value)))
+#define USB_TOG_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_INTEN bitfields
+ */
+
+/*!
+ * @name Register USB_INTEN, field USBRSTEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the USBRST interrupt.
+ * - 0b1 - Enables the USBRST interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_USBRSTEN field. */
+#define USB_RD_INTEN_USBRSTEN(base) ((USB_INTEN_REG(base) & USB_INTEN_USBRSTEN_MASK) >> USB_INTEN_USBRSTEN_SHIFT)
+#define USB_BRD_INTEN_USBRSTEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT))
+
+/*! @brief Set the USBRSTEN field to a new value. */
+#define USB_WR_INTEN_USBRSTEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_USBRSTEN_MASK, USB_INTEN_USBRSTEN(value)))
+#define USB_BWR_INTEN_USBRSTEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ERROREN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the ERROR interrupt.
+ * - 0b1 - Enables the ERROR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ERROREN field. */
+#define USB_RD_INTEN_ERROREN(base) ((USB_INTEN_REG(base) & USB_INTEN_ERROREN_MASK) >> USB_INTEN_ERROREN_SHIFT)
+#define USB_BRD_INTEN_ERROREN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT))
+
+/*! @brief Set the ERROREN field to a new value. */
+#define USB_WR_INTEN_ERROREN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ERROREN_MASK, USB_INTEN_ERROREN(value)))
+#define USB_BWR_INTEN_ERROREN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SOFTOKEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disbles the SOFTOK interrupt.
+ * - 0b1 - Enables the SOFTOK interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SOFTOKEN field. */
+#define USB_RD_INTEN_SOFTOKEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SOFTOKEN_MASK) >> USB_INTEN_SOFTOKEN_SHIFT)
+#define USB_BRD_INTEN_SOFTOKEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT))
+
+/*! @brief Set the SOFTOKEN field to a new value. */
+#define USB_WR_INTEN_SOFTOKEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SOFTOKEN_MASK, USB_INTEN_SOFTOKEN(value)))
+#define USB_BWR_INTEN_SOFTOKEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field TOKDNEEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the TOKDNE interrupt.
+ * - 0b1 - Enables the TOKDNE interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_TOKDNEEN field. */
+#define USB_RD_INTEN_TOKDNEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_TOKDNEEN_MASK) >> USB_INTEN_TOKDNEEN_SHIFT)
+#define USB_BRD_INTEN_TOKDNEEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT))
+
+/*! @brief Set the TOKDNEEN field to a new value. */
+#define USB_WR_INTEN_TOKDNEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_TOKDNEEN_MASK, USB_INTEN_TOKDNEEN(value)))
+#define USB_BWR_INTEN_TOKDNEEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SLEEPEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the SLEEP interrupt.
+ * - 0b1 - Enables the SLEEP interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SLEEPEN field. */
+#define USB_RD_INTEN_SLEEPEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SLEEPEN_MASK) >> USB_INTEN_SLEEPEN_SHIFT)
+#define USB_BRD_INTEN_SLEEPEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT))
+
+/*! @brief Set the SLEEPEN field to a new value. */
+#define USB_WR_INTEN_SLEEPEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SLEEPEN_MASK, USB_INTEN_SLEEPEN(value)))
+#define USB_BWR_INTEN_SLEEPEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field RESUMEEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the RESUME interrupt.
+ * - 0b1 - Enables the RESUME interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_RESUMEEN field. */
+#define USB_RD_INTEN_RESUMEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_RESUMEEN_MASK) >> USB_INTEN_RESUMEEN_SHIFT)
+#define USB_BRD_INTEN_RESUMEEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT))
+
+/*! @brief Set the RESUMEEN field to a new value. */
+#define USB_WR_INTEN_RESUMEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_RESUMEEN_MASK, USB_INTEN_RESUMEEN(value)))
+#define USB_BWR_INTEN_RESUMEEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ATTACHEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the ATTACH interrupt.
+ * - 0b1 - Enables the ATTACH interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ATTACHEN field. */
+#define USB_RD_INTEN_ATTACHEN(base) ((USB_INTEN_REG(base) & USB_INTEN_ATTACHEN_MASK) >> USB_INTEN_ATTACHEN_SHIFT)
+#define USB_BRD_INTEN_ATTACHEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ATTACHEN_SHIFT))
+
+/*! @brief Set the ATTACHEN field to a new value. */
+#define USB_WR_INTEN_ATTACHEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ATTACHEN_MASK, USB_INTEN_ATTACHEN(value)))
+#define USB_BWR_INTEN_ATTACHEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ATTACHEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field STALLEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Diasbles the STALL interrupt.
+ * - 0b1 - Enables the STALL interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_STALLEN field. */
+#define USB_RD_INTEN_STALLEN(base) ((USB_INTEN_REG(base) & USB_INTEN_STALLEN_MASK) >> USB_INTEN_STALLEN_SHIFT)
+#define USB_BRD_INTEN_STALLEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT))
+
+/*! @brief Set the STALLEN field to a new value. */
+#define USB_WR_INTEN_STALLEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_STALLEN_MASK, USB_INTEN_STALLEN(value)))
+#define USB_BWR_INTEN_STALLEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERRSTAT - Error Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERRSTAT - Error Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error sources within the USB Module.
+ * Each of these bits are qualified with their respective error enable bits. All
+ * bits of this register are logically OR'd together and the result placed in the
+ * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. Each bit is set
+ * as soon as the error condition is detected. Therefore, the interrupt does not
+ * typically correspond with the end of a token being processed. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERRSTAT register
+ */
+/*@{*/
+#define USB_RD_ERRSTAT(base)     (USB_ERRSTAT_REG(base))
+#define USB_WR_ERRSTAT(base, value) (USB_ERRSTAT_REG(base) = (value))
+#define USB_RMW_ERRSTAT(base, mask, value) (USB_WR_ERRSTAT(base, (USB_RD_ERRSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) |  (value)))
+#define USB_CLR_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) & ~(value)))
+#define USB_TOG_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERRSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ERRSTAT, field PIDERR[0] (W1C)
+ *
+ * This bit is set when the PID check field fails.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_PIDERR field. */
+#define USB_RD_ERRSTAT_PIDERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_PIDERR_MASK) >> USB_ERRSTAT_PIDERR_SHIFT)
+#define USB_BRD_ERRSTAT_PIDERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT))
+
+/*! @brief Set the PIDERR field to a new value. */
+#define USB_WR_ERRSTAT_PIDERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_PIDERR(value)))
+#define USB_BWR_ERRSTAT_PIDERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C)
+ *
+ * This error interrupt has two functions. When the USB Module is operating in
+ * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token
+ * packets generated by the host. If set the token packet was rejected due to a
+ * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this
+ * interrupt detects End Of Frame (EOF) error conditions. This occurs when the
+ * USB Module is transmitting or receiving data and the SOF counter reaches zero.
+ * This interrupt is useful when developing USB packet scheduling software to
+ * ensure that no USB transactions cross the start of the next frame.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC5EOF field. */
+#define USB_RD_ERRSTAT_CRC5EOF(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC5EOF_MASK) >> USB_ERRSTAT_CRC5EOF_SHIFT)
+#define USB_BRD_ERRSTAT_CRC5EOF(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5EOF_SHIFT))
+
+/*! @brief Set the CRC5EOF field to a new value. */
+#define USB_WR_ERRSTAT_CRC5EOF(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC5EOF(value)))
+#define USB_BWR_ERRSTAT_CRC5EOF(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5EOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC16[2] (W1C)
+ *
+ * This bit is set when a data packet is rejected due to a CRC16 error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC16 field. */
+#define USB_RD_ERRSTAT_CRC16(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC16_MASK) >> USB_ERRSTAT_CRC16_SHIFT)
+#define USB_BRD_ERRSTAT_CRC16(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT))
+
+/*! @brief Set the CRC16 field to a new value. */
+#define USB_WR_ERRSTAT_CRC16(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC16(value)))
+#define USB_BWR_ERRSTAT_CRC16(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DFN8[3] (W1C)
+ *
+ * This bit is set if the data field received was not 8 bits in length. USB
+ * Specification 1.0 requires that data fields be an integral number of bytes. If the
+ * data field was not an integral number of bytes, this bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DFN8 field. */
+#define USB_RD_ERRSTAT_DFN8(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DFN8_MASK) >> USB_ERRSTAT_DFN8_SHIFT)
+#define USB_BRD_ERRSTAT_DFN8(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT))
+
+/*! @brief Set the DFN8 field to a new value. */
+#define USB_WR_ERRSTAT_DFN8(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DFN8(value)))
+#define USB_BWR_ERRSTAT_DFN8(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTOERR[4] (W1C)
+ *
+ * This bit is set when a bus turnaround timeout error occurs. The USB module
+ * contains a bus turnaround timer that keeps track of the amount of time elapsed
+ * between the token and data phases of a SETUP or OUT TOKEN or the data and
+ * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the
+ * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTOERR field. */
+#define USB_RD_ERRSTAT_BTOERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTOERR_MASK) >> USB_ERRSTAT_BTOERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTOERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT))
+
+/*! @brief Set the BTOERR field to a new value. */
+#define USB_WR_ERRSTAT_BTOERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_BTOERR(value)))
+#define USB_BWR_ERRSTAT_BTOERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DMAERR[5] (W1C)
+ *
+ * This bit is set if the USB Module has requested a DMA access to read a new
+ * BDT but has not been given the bus before it needs to receive or transmit data.
+ * If processing a TX transfer this would cause a transmit data underflow
+ * condition. If processing a RX transfer this would cause a receive data overflow
+ * condition. This interrupt is useful when developing device arbitration hardware for
+ * the microprocessor and the USB module to minimize bus request and bus grant
+ * latency. This bit is also set if a data packet to or from the host is larger
+ * than the buffer size allocated in the BDT. In this case the data packet is
+ * truncated as it is put in buffer memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DMAERR field. */
+#define USB_RD_ERRSTAT_DMAERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DMAERR_MASK) >> USB_ERRSTAT_DMAERR_SHIFT)
+#define USB_BRD_ERRSTAT_DMAERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT))
+
+/*! @brief Set the DMAERR field to a new value. */
+#define USB_WR_ERRSTAT_DMAERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DMAERR(value)))
+#define USB_BWR_ERRSTAT_DMAERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTSERR[7] (W1C)
+ *
+ * This bit is set when a bit stuff error is detected. If set, the corresponding
+ * packet is rejected due to the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTSERR field. */
+#define USB_RD_ERRSTAT_BTSERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTSERR_MASK) >> USB_ERRSTAT_BTSERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTSERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT))
+
+/*! @brief Set the BTSERR field to a new value. */
+#define USB_WR_ERRSTAT_BTSERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTSERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK), USB_ERRSTAT_BTSERR(value)))
+#define USB_BWR_ERRSTAT_BTSERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERREN - Error Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERREN - Error Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error interrupt sources within the USB
+ * module. Setting any of these bits enables the respective interrupt source in
+ * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore,
+ * the interrupt does not typically correspond with the end of a token being
+ * processed. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERREN register
+ */
+/*@{*/
+#define USB_RD_ERREN(base)       (USB_ERREN_REG(base))
+#define USB_WR_ERREN(base, value) (USB_ERREN_REG(base) = (value))
+#define USB_RMW_ERREN(base, mask, value) (USB_WR_ERREN(base, (USB_RD_ERREN(base) & ~(mask)) | (value)))
+#define USB_SET_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) |  (value)))
+#define USB_CLR_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) & ~(value)))
+#define USB_TOG_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERREN bitfields
+ */
+
+/*!
+ * @name Register USB_ERREN, field PIDERREN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the PIDERR interrupt.
+ * - 0b1 - Enters the PIDERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_PIDERREN field. */
+#define USB_RD_ERREN_PIDERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_PIDERREN_MASK) >> USB_ERREN_PIDERREN_SHIFT)
+#define USB_BRD_ERREN_PIDERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT))
+
+/*! @brief Set the PIDERREN field to a new value. */
+#define USB_WR_ERREN_PIDERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_PIDERREN_MASK, USB_ERREN_PIDERREN(value)))
+#define USB_BWR_ERREN_PIDERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC5EOFEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the CRC5/EOF interrupt.
+ * - 0b1 - Enables the CRC5/EOF interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC5EOFEN field. */
+#define USB_RD_ERREN_CRC5EOFEN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC5EOFEN_MASK) >> USB_ERREN_CRC5EOFEN_SHIFT)
+#define USB_BRD_ERREN_CRC5EOFEN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT))
+
+/*! @brief Set the CRC5EOFEN field to a new value. */
+#define USB_WR_ERREN_CRC5EOFEN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC5EOFEN_MASK, USB_ERREN_CRC5EOFEN(value)))
+#define USB_BWR_ERREN_CRC5EOFEN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC16EN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the CRC16 interrupt.
+ * - 0b1 - Enables the CRC16 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC16EN field. */
+#define USB_RD_ERREN_CRC16EN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC16EN_MASK) >> USB_ERREN_CRC16EN_SHIFT)
+#define USB_BRD_ERREN_CRC16EN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT))
+
+/*! @brief Set the CRC16EN field to a new value. */
+#define USB_WR_ERREN_CRC16EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC16EN_MASK, USB_ERREN_CRC16EN(value)))
+#define USB_BWR_ERREN_CRC16EN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DFN8EN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the DFN8 interrupt.
+ * - 0b1 - Enables the DFN8 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DFN8EN field. */
+#define USB_RD_ERREN_DFN8EN(base) ((USB_ERREN_REG(base) & USB_ERREN_DFN8EN_MASK) >> USB_ERREN_DFN8EN_SHIFT)
+#define USB_BRD_ERREN_DFN8EN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT))
+
+/*! @brief Set the DFN8EN field to a new value. */
+#define USB_WR_ERREN_DFN8EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DFN8EN_MASK, USB_ERREN_DFN8EN(value)))
+#define USB_BWR_ERREN_DFN8EN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTOERREN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the BTOERR interrupt.
+ * - 0b1 - Enables the BTOERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTOERREN field. */
+#define USB_RD_ERREN_BTOERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTOERREN_MASK) >> USB_ERREN_BTOERREN_SHIFT)
+#define USB_BRD_ERREN_BTOERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT))
+
+/*! @brief Set the BTOERREN field to a new value. */
+#define USB_WR_ERREN_BTOERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTOERREN_MASK, USB_ERREN_BTOERREN(value)))
+#define USB_BWR_ERREN_BTOERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DMAERREN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the DMAERR interrupt.
+ * - 0b1 - Enables the DMAERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DMAERREN field. */
+#define USB_RD_ERREN_DMAERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_DMAERREN_MASK) >> USB_ERREN_DMAERREN_SHIFT)
+#define USB_BRD_ERREN_DMAERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT))
+
+/*! @brief Set the DMAERREN field to a new value. */
+#define USB_WR_ERREN_DMAERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DMAERREN_MASK, USB_ERREN_DMAERREN(value)))
+#define USB_BWR_ERREN_DMAERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTSERREN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the BTSERR interrupt.
+ * - 0b1 - Enables the BTSERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTSERREN field. */
+#define USB_RD_ERREN_BTSERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTSERREN_MASK) >> USB_ERREN_BTSERREN_SHIFT)
+#define USB_BRD_ERREN_BTSERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT))
+
+/*! @brief Set the BTSERREN field to a new value. */
+#define USB_WR_ERREN_BTSERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTSERREN_MASK, USB_ERREN_BTSERREN(value)))
+#define USB_BWR_ERREN_BTSERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_STAT - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_STAT - Status register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * Reports the transaction status within the USB module. When the processor's
+ * interrupt controller has received a TOKDNE, interrupt the Status Register must
+ * be read to determine the status of the previous endpoint communication. The
+ * data in the status register is valid when TOKDNE interrupt is asserted. The
+ * Status register is actually a read window into a status FIFO maintained by the USB
+ * module. When the USB module uses a BD, it updates the Status register. If
+ * another USB transaction is performed before the TOKDNE interrupt is serviced, the
+ * USB module stores the status of the next transaction in the STAT FIFO. Thus
+ * STAT is actually a four byte FIFO that allows the processor core to process one
+ * transaction while the SIE is processing the next transaction. Clearing the
+ * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents
+ * of the next STAT value. If the data in the STAT holding register is valid, the
+ * SIE immediately reasserts to TOKDNE interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_STAT register
+ */
+/*@{*/
+#define USB_RD_STAT(base)        (USB_STAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_STAT bitfields
+ */
+
+/*!
+ * @name Register USB_STAT, field ODD[2] (RO)
+ *
+ * This bit is set if the last buffer descriptor updated was in the odd bank of
+ * the BDT.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ODD field. */
+#define USB_RD_STAT_ODD(base) ((USB_STAT_REG(base) & USB_STAT_ODD_MASK) >> USB_STAT_ODD_SHIFT)
+#define USB_BRD_STAT_ODD(base) (BITBAND_ACCESS8(&USB_STAT_REG(base), USB_STAT_ODD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field TX[3] (RO)
+ *
+ * Values:
+ * - 0b0 - The most recent transaction was a receive operation.
+ * - 0b1 - The most recent transaction was a transmit operation.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_TX field. */
+#define USB_RD_STAT_TX(base) ((USB_STAT_REG(base) & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT)
+#define USB_BRD_STAT_TX(base) (BITBAND_ACCESS8(&USB_STAT_REG(base), USB_STAT_TX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field ENDP[7:4] (RO)
+ *
+ * This four-bit field encodes the endpoint address that received or transmitted
+ * the previous token. This allows the processor core to determine the BDT entry
+ * that was updated by the last USB transaction.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ENDP field. */
+#define USB_RD_STAT_ENDP(base) ((USB_STAT_REG(base) & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT)
+#define USB_BRD_STAT_ENDP(base) (USB_RD_STAT_ENDP(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CTL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CTL - Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides various control and configuration information for the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_CTL register
+ */
+/*@{*/
+#define USB_RD_CTL(base)         (USB_CTL_REG(base))
+#define USB_WR_CTL(base, value)  (USB_CTL_REG(base) = (value))
+#define USB_RMW_CTL(base, mask, value) (USB_WR_CTL(base, (USB_RD_CTL(base) & ~(mask)) | (value)))
+#define USB_SET_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) |  (value)))
+#define USB_CLR_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) & ~(value)))
+#define USB_TOG_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CTL bitfields
+ */
+
+/*!
+ * @name Register USB_CTL, field USBENSOFEN[0] (RW)
+ *
+ * Setting this bit enables the USB-FS to operate; clearing it disables the
+ * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs.
+ * Therefore, setting this bit resets much of the logic in the SIE. When host mode
+ * is enabled, clearing this bit causes the SIE to stop sending SOF tokens.
+ *
+ * Values:
+ * - 0b0 - Disables the USB Module.
+ * - 0b1 - Enables the USB Module.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_USBENSOFEN field. */
+#define USB_RD_CTL_USBENSOFEN(base) ((USB_CTL_REG(base) & USB_CTL_USBENSOFEN_MASK) >> USB_CTL_USBENSOFEN_SHIFT)
+#define USB_BRD_CTL_USBENSOFEN(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT))
+
+/*! @brief Set the USBENSOFEN field to a new value. */
+#define USB_WR_CTL_USBENSOFEN(base, value) (USB_RMW_CTL(base, USB_CTL_USBENSOFEN_MASK, USB_CTL_USBENSOFEN(value)))
+#define USB_BWR_CTL_USBENSOFEN(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field ODDRST[1] (RW)
+ *
+ * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which
+ * then specifies the EVEN BDT bank.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_ODDRST field. */
+#define USB_RD_CTL_ODDRST(base) ((USB_CTL_REG(base) & USB_CTL_ODDRST_MASK) >> USB_CTL_ODDRST_SHIFT)
+#define USB_BRD_CTL_ODDRST(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT))
+
+/*! @brief Set the ODDRST field to a new value. */
+#define USB_WR_CTL_ODDRST(base, value) (USB_RMW_CTL(base, USB_CTL_ODDRST_MASK, USB_CTL_ODDRST(value)))
+#define USB_BWR_CTL_ODDRST(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field RESUME[2] (RW)
+ *
+ * When set to 1 this bit enables the USB Module to execute resume signaling.
+ * This allows the USB Module to perform remote wake-up. Software must set RESUME
+ * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN
+ * bit is set, the USB module appends a Low Speed End of Packet to the Resume
+ * signaling when the RESUME bit is cleared. For more information on RESUME
+ * signaling see Section 7.1.4.5 of the USB specification version 1.0.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_RESUME field. */
+#define USB_RD_CTL_RESUME(base) ((USB_CTL_REG(base) & USB_CTL_RESUME_MASK) >> USB_CTL_RESUME_SHIFT)
+#define USB_BRD_CTL_RESUME(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESUME_SHIFT))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_CTL_RESUME(base, value) (USB_RMW_CTL(base, USB_CTL_RESUME_MASK, USB_CTL_RESUME(value)))
+#define USB_BWR_CTL_RESUME(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESUME_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field HOSTMODEEN[3] (RW)
+ *
+ * When set to 1, this bit enables the USB Module to operate in Host mode. In
+ * host mode, the USB module performs USB transactions under the programmed control
+ * of the host processor.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_HOSTMODEEN field. */
+#define USB_RD_CTL_HOSTMODEEN(base) ((USB_CTL_REG(base) & USB_CTL_HOSTMODEEN_MASK) >> USB_CTL_HOSTMODEEN_SHIFT)
+#define USB_BRD_CTL_HOSTMODEEN(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_HOSTMODEEN_SHIFT))
+
+/*! @brief Set the HOSTMODEEN field to a new value. */
+#define USB_WR_CTL_HOSTMODEEN(base, value) (USB_RMW_CTL(base, USB_CTL_HOSTMODEEN_MASK, USB_CTL_HOSTMODEEN(value)))
+#define USB_BWR_CTL_HOSTMODEEN(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_HOSTMODEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field RESET[4] (RW)
+ *
+ * Setting this bit enables the USB Module to generate USB reset signaling. This
+ * allows the USB Module to reset USB peripherals. This control signal is only
+ * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the
+ * required amount of time and then clear it to 0 to end reset signaling. For more
+ * information on reset signaling see Section 7.1.4.3 of the USB specification version
+ * 1.0.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_RESET field. */
+#define USB_RD_CTL_RESET(base) ((USB_CTL_REG(base) & USB_CTL_RESET_MASK) >> USB_CTL_RESET_SHIFT)
+#define USB_BRD_CTL_RESET(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESET_SHIFT))
+
+/*! @brief Set the RESET field to a new value. */
+#define USB_WR_CTL_RESET(base, value) (USB_RMW_CTL(base, USB_CTL_RESET_MASK, USB_CTL_RESET(value)))
+#define USB_BWR_CTL_RESET(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW)
+ *
+ * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB
+ * token. Software must not write more token commands to the Token Register when
+ * TOKEN_BUSY is set. Software should check this field before writing any tokens
+ * to the Token Register to ensure that token commands are not lost. In Target
+ * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and
+ * reception. Clearing this bit allows the SIE to continue token processing. This bit
+ * is set by the SIE when a SETUP Token is received allowing software to dequeue
+ * any pending packet transactions in the BDT before resuming token processing.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field. */
+#define USB_RD_CTL_TXSUSPENDTOKENBUSY(base) ((USB_CTL_REG(base) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) >> USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)
+#define USB_BRD_CTL_TXSUSPENDTOKENBUSY(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))
+
+/*! @brief Set the TXSUSPENDTOKENBUSY field to a new value. */
+#define USB_WR_CTL_TXSUSPENDTOKENBUSY(base, value) (USB_RMW_CTL(base, USB_CTL_TXSUSPENDTOKENBUSY_MASK, USB_CTL_TXSUSPENDTOKENBUSY(value)))
+#define USB_BWR_CTL_TXSUSPENDTOKENBUSY(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field SE0[6] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_SE0 field. */
+#define USB_RD_CTL_SE0(base) ((USB_CTL_REG(base) & USB_CTL_SE0_MASK) >> USB_CTL_SE0_SHIFT)
+#define USB_BRD_CTL_SE0(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT))
+
+/*! @brief Set the SE0 field to a new value. */
+#define USB_WR_CTL_SE0(base, value) (USB_RMW_CTL(base, USB_CTL_SE0_MASK, USB_CTL_SE0(value)))
+#define USB_BWR_CTL_SE0(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field JSTATE[7] (RW)
+ *
+ * The polarity of this signal is affected by the current state of LSEN .
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_JSTATE field. */
+#define USB_RD_CTL_JSTATE(base) ((USB_CTL_REG(base) & USB_CTL_JSTATE_MASK) >> USB_CTL_JSTATE_SHIFT)
+#define USB_BRD_CTL_JSTATE(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT))
+
+/*! @brief Set the JSTATE field to a new value. */
+#define USB_WR_CTL_JSTATE(base, value) (USB_RMW_CTL(base, USB_CTL_JSTATE_MASK, USB_CTL_JSTATE(value)))
+#define USB_BWR_CTL_JSTATE(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDR - Address register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDR - Address register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Holds the unique USB address that the USB module decodes when in Peripheral
+ * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module
+ * transmits this address with a TOKEN packet. This enables the USB module to
+ * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1.
+ * The Address register is reset to 0x00 after the reset input becomes active or
+ * the USB module decodes a USB reset signal. This action initializes the Address
+ * register to decode address 0x00 as required by the USB specification.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDR register
+ */
+/*@{*/
+#define USB_RD_ADDR(base)        (USB_ADDR_REG(base))
+#define USB_WR_ADDR(base, value) (USB_ADDR_REG(base) = (value))
+#define USB_RMW_ADDR(base, mask, value) (USB_WR_ADDR(base, (USB_RD_ADDR(base) & ~(mask)) | (value)))
+#define USB_SET_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) |  (value)))
+#define USB_CLR_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) & ~(value)))
+#define USB_TOG_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDR bitfields
+ */
+
+/*!
+ * @name Register USB_ADDR, field ADDR[6:0] (RW)
+ *
+ * Defines the USB address that the USB module decodes in peripheral mode, or
+ * transmits when in host mode.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_ADDR field. */
+#define USB_RD_ADDR_ADDR(base) ((USB_ADDR_REG(base) & USB_ADDR_ADDR_MASK) >> USB_ADDR_ADDR_SHIFT)
+#define USB_BRD_ADDR_ADDR(base) (USB_RD_ADDR_ADDR(base))
+
+/*! @brief Set the ADDR field to a new value. */
+#define USB_WR_ADDR_ADDR(base, value) (USB_RMW_ADDR(base, USB_ADDR_ADDR_MASK, USB_ADDR_ADDR(value)))
+#define USB_BWR_ADDR_ADDR(base, value) (USB_WR_ADDR_ADDR(base, value))
+/*@}*/
+
+/*!
+ * @name Register USB_ADDR, field LSEN[7] (RW)
+ *
+ * Informs the USB module that the next token command written to the token
+ * register must be performed at low speed. This enables the USB module to perform the
+ * necessary preamble required for low-speed data transmissions.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_LSEN field. */
+#define USB_RD_ADDR_LSEN(base) ((USB_ADDR_REG(base) & USB_ADDR_LSEN_MASK) >> USB_ADDR_LSEN_SHIFT)
+#define USB_BRD_ADDR_LSEN(base) (BITBAND_ACCESS8(&USB_ADDR_REG(base), USB_ADDR_LSEN_SHIFT))
+
+/*! @brief Set the LSEN field to a new value. */
+#define USB_WR_ADDR_LSEN(base, value) (USB_RMW_ADDR(base, USB_ADDR_LSEN_MASK, USB_ADDR_LSEN(value)))
+#define USB_BWR_ADDR_LSEN(base, value) (BITBAND_ACCESS8(&USB_ADDR_REG(base), USB_ADDR_LSEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE1 - BDT Page register 1
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE1 - BDT Page register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides address bits 15 through 9 of the base address where the current
+ * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor
+ * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so
+ * bits 8 through 0 of the base address are always zero.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE1 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE1(base)    (USB_BDTPAGE1_REG(base))
+#define USB_WR_BDTPAGE1(base, value) (USB_BDTPAGE1_REG(base) = (value))
+#define USB_RMW_BDTPAGE1(base, mask, value) (USB_WR_BDTPAGE1(base, (USB_RD_BDTPAGE1(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) |  (value)))
+#define USB_CLR_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) & ~(value)))
+#define USB_TOG_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_BDTPAGE1 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW)
+ *
+ * Provides address bits 15 through 9 of the BDT base address.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_BDTPAGE1_BDTBA field. */
+#define USB_RD_BDTPAGE1_BDTBA(base) ((USB_BDTPAGE1_REG(base) & USB_BDTPAGE1_BDTBA_MASK) >> USB_BDTPAGE1_BDTBA_SHIFT)
+#define USB_BRD_BDTPAGE1_BDTBA(base) (USB_RD_BDTPAGE1_BDTBA(base))
+
+/*! @brief Set the BDTBA field to a new value. */
+#define USB_WR_BDTPAGE1_BDTBA(base, value) (USB_RMW_BDTPAGE1(base, USB_BDTPAGE1_BDTBA_MASK, USB_BDTPAGE1_BDTBA(value)))
+#define USB_BWR_BDTPAGE1_BDTBA(base, value) (USB_WR_BDTPAGE1_BDTBA(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUML - Frame Number register Low
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUML - Frame Number register Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUML register
+ */
+/*@{*/
+#define USB_RD_FRMNUML(base)     (USB_FRMNUML_REG(base))
+#define USB_WR_FRMNUML(base, value) (USB_FRMNUML_REG(base) = (value))
+#define USB_RMW_FRMNUML(base, mask, value) (USB_WR_FRMNUML(base, (USB_RD_FRMNUML(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) |  (value)))
+#define USB_CLR_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) & ~(value)))
+#define USB_TOG_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUMH - Frame Number register High
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUMH - Frame Number register High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUMH register
+ */
+/*@{*/
+#define USB_RD_FRMNUMH(base)     (USB_FRMNUMH_REG(base))
+#define USB_WR_FRMNUMH(base, value) (USB_FRMNUMH_REG(base) = (value))
+#define USB_RMW_FRMNUMH(base, mask, value) (USB_WR_FRMNUMH(base, (USB_RD_FRMNUMH(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) |  (value)))
+#define USB_CLR_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) & ~(value)))
+#define USB_TOG_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_FRMNUMH bitfields
+ */
+
+/*!
+ * @name Register USB_FRMNUMH, field FRM[2:0] (RW)
+ *
+ * This 3-bit field and the 8-bit field in the Frame Number Register Low are
+ * used to compute the address where the current Buffer Descriptor Table (BDT)
+ * resides in system memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_FRMNUMH_FRM field. */
+#define USB_RD_FRMNUMH_FRM(base) ((USB_FRMNUMH_REG(base) & USB_FRMNUMH_FRM_MASK) >> USB_FRMNUMH_FRM_SHIFT)
+#define USB_BRD_FRMNUMH_FRM(base) (USB_RD_FRMNUMH_FRM(base))
+
+/*! @brief Set the FRM field to a new value. */
+#define USB_WR_FRMNUMH_FRM(base, value) (USB_RMW_FRMNUMH(base, USB_FRMNUMH_FRM_MASK, USB_FRMNUMH_FRM(value)))
+#define USB_BWR_FRMNUMH_FRM(base, value) (USB_WR_FRMNUMH_FRM(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_TOKEN - Token register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_TOKEN - Token register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the
+ * software needs to execute a USB transaction to a peripheral, it writes the
+ * TOKEN type and endpoint to this register. After this register has been written,
+ * the USB module begins the specified USB transaction to the address contained in
+ * the address register. The processor core must always check that the
+ * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register.
+ * This ensures that the token commands are not overwritten before they can be
+ * executed. The address register and endpoint control register 0 are also used when
+ * performing a token command and therefore must also be written before the
+ * Token Register. The address register is used to select the USB peripheral address
+ * transmitted by the token command. The endpoint control register determines the
+ * handshake and retry policies used during the transfer.
+ */
+/*!
+ * @name Constants and macros for entire USB_TOKEN register
+ */
+/*@{*/
+#define USB_RD_TOKEN(base)       (USB_TOKEN_REG(base))
+#define USB_WR_TOKEN(base, value) (USB_TOKEN_REG(base) = (value))
+#define USB_RMW_TOKEN(base, mask, value) (USB_WR_TOKEN(base, (USB_RD_TOKEN(base) & ~(mask)) | (value)))
+#define USB_SET_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) |  (value)))
+#define USB_CLR_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) & ~(value)))
+#define USB_TOG_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_TOKEN bitfields
+ */
+
+/*!
+ * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW)
+ *
+ * Holds the Endpoint address for the token command. The four bit value written
+ * must be a valid endpoint.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_TOKEN_TOKENENDPT field. */
+#define USB_RD_TOKEN_TOKENENDPT(base) ((USB_TOKEN_REG(base) & USB_TOKEN_TOKENENDPT_MASK) >> USB_TOKEN_TOKENENDPT_SHIFT)
+#define USB_BRD_TOKEN_TOKENENDPT(base) (USB_RD_TOKEN_TOKENENDPT(base))
+
+/*! @brief Set the TOKENENDPT field to a new value. */
+#define USB_WR_TOKEN_TOKENENDPT(base, value) (USB_RMW_TOKEN(base, USB_TOKEN_TOKENENDPT_MASK, USB_TOKEN_TOKENENDPT(value)))
+#define USB_BWR_TOKEN_TOKENENDPT(base, value) (USB_WR_TOKEN_TOKENENDPT(base, value))
+/*@}*/
+
+/*!
+ * @name Register USB_TOKEN, field TOKENPID[7:4] (RW)
+ *
+ * Contains the token type executed by the USB module.
+ *
+ * Values:
+ * - 0b0001 - OUT Token. USB Module performs an OUT (TX) transaction.
+ * - 0b1001 - IN Token. USB Module performs an In (RX) transaction.
+ * - 0b1101 - SETUP Token. USB Module performs a SETUP (TX) transaction
+ */
+/*@{*/
+/*! @brief Read current value of the USB_TOKEN_TOKENPID field. */
+#define USB_RD_TOKEN_TOKENPID(base) ((USB_TOKEN_REG(base) & USB_TOKEN_TOKENPID_MASK) >> USB_TOKEN_TOKENPID_SHIFT)
+#define USB_BRD_TOKEN_TOKENPID(base) (USB_RD_TOKEN_TOKENPID(base))
+
+/*! @brief Set the TOKENPID field to a new value. */
+#define USB_WR_TOKEN_TOKENPID(base, value) (USB_RMW_TOKEN(base, USB_TOKEN_TOKENPID_MASK, USB_TOKEN_TOKENPID(value)))
+#define USB_BWR_TOKEN_TOKENPID(base, value) (USB_WR_TOKEN_TOKENPID(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_SOFTHLD - SOF Threshold register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_SOFTHLD - SOF Threshold register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in
+ * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The
+ * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with
+ * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF)
+ * token is transmitted. The SOF threshold register is used to program the number
+ * of USB byte times before the SOF to stop initiating token packet transactions.
+ * This register must be set to a value that ensures that other packets are not
+ * actively being transmitted when the SOF time counts to zero. When the SOF
+ * counter reaches the threshold value, no more tokens are transmitted until after the
+ * SOF has been transmitted. The value programmed into the threshold register
+ * must reserve enough time to ensure the worst case transaction completes. In
+ * general the worst case transaction is an IN token followed by a data packet from
+ * the target followed by the response from the host. The actual time required is
+ * a function of the maximum packet size on the bus. Typical values for the SOF
+ * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26;
+ * 8-byte packets=18.
+ */
+/*!
+ * @name Constants and macros for entire USB_SOFTHLD register
+ */
+/*@{*/
+#define USB_RD_SOFTHLD(base)     (USB_SOFTHLD_REG(base))
+#define USB_WR_SOFTHLD(base, value) (USB_SOFTHLD_REG(base) = (value))
+#define USB_RMW_SOFTHLD(base, mask, value) (USB_WR_SOFTHLD(base, (USB_RD_SOFTHLD(base) & ~(mask)) | (value)))
+#define USB_SET_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) |  (value)))
+#define USB_CLR_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) & ~(value)))
+#define USB_TOG_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE2 - BDT Page Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE2 - BDT Page Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE2 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE2(base)    (USB_BDTPAGE2_REG(base))
+#define USB_WR_BDTPAGE2(base, value) (USB_BDTPAGE2_REG(base) = (value))
+#define USB_RMW_BDTPAGE2(base, mask, value) (USB_WR_BDTPAGE2(base, (USB_RD_BDTPAGE2(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) |  (value)))
+#define USB_CLR_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) & ~(value)))
+#define USB_TOG_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE3 - BDT Page Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE3 - BDT Page Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE3 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE3(base)    (USB_BDTPAGE3_REG(base))
+#define USB_WR_BDTPAGE3(base, value) (USB_BDTPAGE3_REG(base) = (value))
+#define USB_RMW_BDTPAGE3(base, mask, value) (USB_WR_BDTPAGE3(base, (USB_RD_BDTPAGE3(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) |  (value)))
+#define USB_CLR_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) & ~(value)))
+#define USB_TOG_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ENDPT - Endpoint Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ENDPT - Endpoint Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains the endpoint control bits for each of the 16 endpoints available
+ * within the USB module for a decoded address. The format for these registers is
+ * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control
+ * pipe 0, which is required for all USB functions. Therefore, after a USBRST
+ * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode
+ * ENDPT0 is used to determine the handshake, retry and low speed
+ * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
+ * bit should be 1. For Isochronous transfers it should be 0. Common values to
+ * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
+ * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and
+ * EPTXEN define if an endpoint is enabled and define the direction of the endpoint.
+ * The endpoint enable/direction control is defined in the following table.
+ * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint
+ * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only
+ * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and
+ * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP)
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire USB_ENDPT register
+ */
+/*@{*/
+#define USB_RD_ENDPT(base, index) (USB_ENDPT_REG(base, index))
+#define USB_WR_ENDPT(base, index, value) (USB_ENDPT_REG(base, index) = (value))
+#define USB_RMW_ENDPT(base, index, mask, value) (USB_WR_ENDPT(base, index, (USB_RD_ENDPT(base, index) & ~(mask)) | (value)))
+#define USB_SET_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) |  (value)))
+#define USB_CLR_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) & ~(value)))
+#define USB_TOG_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ENDPT bitfields
+ */
+
+/*!
+ * @name Register USB_ENDPT, field EPHSHK[0] (RW)
+ *
+ * When set this bit enables an endpoint to perform handshaking during a
+ * transaction to this endpoint. This bit is generally 1 unless the endpoint is
+ * Isochronous.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPHSHK field. */
+#define USB_RD_ENDPT_EPHSHK(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPHSHK_MASK) >> USB_ENDPT_EPHSHK_SHIFT)
+#define USB_BRD_ENDPT_EPHSHK(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT))
+
+/*! @brief Set the EPHSHK field to a new value. */
+#define USB_WR_ENDPT_EPHSHK(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPHSHK_MASK, USB_ENDPT_EPHSHK(value)))
+#define USB_BWR_ENDPT_EPHSHK(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPSTALL[1] (RW)
+ *
+ * When set this bit indicates that the endpoint is called. This bit has
+ * priority over all other control bits in the EndPoint Enable Register, but it is only
+ * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB
+ * Module to return a STALL handshake. After an endpoint is stalled it requires
+ * intervention from the Host Controller.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPSTALL field. */
+#define USB_RD_ENDPT_EPSTALL(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPSTALL_MASK) >> USB_ENDPT_EPSTALL_SHIFT)
+#define USB_BRD_ENDPT_EPSTALL(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT))
+
+/*! @brief Set the EPSTALL field to a new value. */
+#define USB_WR_ENDPT_EPSTALL(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPSTALL_MASK, USB_ENDPT_EPSTALL(value)))
+#define USB_BWR_ENDPT_EPSTALL(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPTXEN[2] (RW)
+ *
+ * This bit, when set, enables the endpoint for TX transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPTXEN field. */
+#define USB_RD_ENDPT_EPTXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPTXEN_MASK) >> USB_ENDPT_EPTXEN_SHIFT)
+#define USB_BRD_ENDPT_EPTXEN(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT))
+
+/*! @brief Set the EPTXEN field to a new value. */
+#define USB_WR_ENDPT_EPTXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPTXEN_MASK, USB_ENDPT_EPTXEN(value)))
+#define USB_BWR_ENDPT_EPTXEN(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPRXEN[3] (RW)
+ *
+ * This bit, when set, enables the endpoint for RX transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPRXEN field. */
+#define USB_RD_ENDPT_EPRXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPRXEN_MASK) >> USB_ENDPT_EPRXEN_SHIFT)
+#define USB_BRD_ENDPT_EPRXEN(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT))
+
+/*! @brief Set the EPRXEN field to a new value. */
+#define USB_WR_ENDPT_EPRXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPRXEN_MASK, USB_ENDPT_EPRXEN(value)))
+#define USB_BWR_ENDPT_EPRXEN(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPCTLDIS[4] (RW)
+ *
+ * This bit, when set, disables control (SETUP) transfers. When cleared, control
+ * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
+ * are also set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPCTLDIS field. */
+#define USB_RD_ENDPT_EPCTLDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPCTLDIS_MASK) >> USB_ENDPT_EPCTLDIS_SHIFT)
+#define USB_BRD_ENDPT_EPCTLDIS(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT))
+
+/*! @brief Set the EPCTLDIS field to a new value. */
+#define USB_WR_ENDPT_EPCTLDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPCTLDIS_MASK, USB_ENDPT_EPCTLDIS(value)))
+#define USB_BWR_ENDPT_EPCTLDIS(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field RETRYDIS[6] (RW)
+ *
+ * This is a Host mode only bit and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed
+ * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID
+ * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When
+ * this bit is cleared, NAKed transactions are retried in hardware. This bit must
+ * be set when the host is attempting to poll an interrupt endpoint.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_RETRYDIS field. */
+#define USB_RD_ENDPT_RETRYDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_RETRYDIS_MASK) >> USB_ENDPT_RETRYDIS_SHIFT)
+#define USB_BRD_ENDPT_RETRYDIS(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_RETRYDIS_SHIFT))
+
+/*! @brief Set the RETRYDIS field to a new value. */
+#define USB_WR_ENDPT_RETRYDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_RETRYDIS_MASK, USB_ENDPT_RETRYDIS(value)))
+#define USB_BWR_ENDPT_RETRYDIS(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_RETRYDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field HOSTWOHUB[7] (RW)
+ *
+ * This is a Host mode only field and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a
+ * directly connected low speed device. When cleared, the host produces the
+ * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed
+ * device as required to communicate with a low speed device through a hub.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_HOSTWOHUB field. */
+#define USB_RD_ENDPT_HOSTWOHUB(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_HOSTWOHUB_MASK) >> USB_ENDPT_HOSTWOHUB_SHIFT)
+#define USB_BRD_ENDPT_HOSTWOHUB(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_HOSTWOHUB_SHIFT))
+
+/*! @brief Set the HOSTWOHUB field to a new value. */
+#define USB_WR_ENDPT_HOSTWOHUB(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_HOSTWOHUB_MASK, USB_ENDPT_HOSTWOHUB(value)))
+#define USB_BWR_ENDPT_HOSTWOHUB(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_HOSTWOHUB_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBCTRL - USB Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBCTRL - USB Control register (RW)
+ *
+ * Reset value: 0xC0U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBCTRL register
+ */
+/*@{*/
+#define USB_RD_USBCTRL(base)     (USB_USBCTRL_REG(base))
+#define USB_WR_USBCTRL(base, value) (USB_USBCTRL_REG(base) = (value))
+#define USB_RMW_USBCTRL(base, mask, value) (USB_WR_USBCTRL(base, (USB_RD_USBCTRL(base) & ~(mask)) | (value)))
+#define USB_SET_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) |  (value)))
+#define USB_CLR_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) & ~(value)))
+#define USB_TOG_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBCTRL bitfields
+ */
+
+/*!
+ * @name Register USB_USBCTRL, field PDE[6] (RW)
+ *
+ * Enables the weak pulldowns on the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - Weak pulldowns are disabled on D+ and D-.
+ * - 0b1 - Weak pulldowns are enabled on D+ and D-.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_PDE field. */
+#define USB_RD_USBCTRL_PDE(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_PDE_MASK) >> USB_USBCTRL_PDE_SHIFT)
+#define USB_BRD_USBCTRL_PDE(base) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT))
+
+/*! @brief Set the PDE field to a new value. */
+#define USB_WR_USBCTRL_PDE(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_PDE_MASK, USB_USBCTRL_PDE(value)))
+#define USB_BWR_USBCTRL_PDE(base, value) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_USBCTRL, field SUSP[7] (RW)
+ *
+ * Places the USB transceiver into the suspend state.
+ *
+ * Values:
+ * - 0b0 - USB transceiver is not in suspend state.
+ * - 0b1 - USB transceiver is in suspend state.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_SUSP field. */
+#define USB_RD_USBCTRL_SUSP(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_SUSP_MASK) >> USB_USBCTRL_SUSP_SHIFT)
+#define USB_BRD_USBCTRL_SUSP(base) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT))
+
+/*! @brief Set the SUSP field to a new value. */
+#define USB_WR_USBCTRL_SUSP(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_SUSP_MASK, USB_USBCTRL_SUSP(value)))
+#define USB_BWR_USBCTRL_SUSP(base, value) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OBSERVE - USB OTG Observe register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OBSERVE - USB OTG Observe register (RO)
+ *
+ * Reset value: 0x50U
+ *
+ * Provides visibility on the state of the pull-ups and pull-downs at the
+ * transceiver. Useful when interfacing to an external OTG control module via a serial
+ * interface.
+ */
+/*!
+ * @name Constants and macros for entire USB_OBSERVE register
+ */
+/*@{*/
+#define USB_RD_OBSERVE(base)     (USB_OBSERVE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OBSERVE bitfields
+ */
+
+/*!
+ * @name Register USB_OBSERVE, field DMPD[4] (RO)
+ *
+ * Provides observability of the D- Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D- pulldown disabled.
+ * - 0b1 - D- pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DMPD field. */
+#define USB_RD_OBSERVE_DMPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DMPD_MASK) >> USB_OBSERVE_DMPD_SHIFT)
+#define USB_BRD_OBSERVE_DMPD(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DMPD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPD[6] (RO)
+ *
+ * Provides observability of the D+ Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D+ pulldown disabled.
+ * - 0b1 - D+ pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPD field. */
+#define USB_RD_OBSERVE_DPPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPD_MASK) >> USB_OBSERVE_DPPD_SHIFT)
+#define USB_BRD_OBSERVE_DPPD(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPU[7] (RO)
+ *
+ * Provides observability of the D+ Pullup enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D+ pullup disabled.
+ * - 0b1 - D+ pullup enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPU field. */
+#define USB_RD_OBSERVE_DPPU(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPU_MASK) >> USB_OBSERVE_DPPU_SHIFT)
+#define USB_BRD_OBSERVE_DPPU(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPU_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CONTROL - USB OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CONTROL - USB OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_CONTROL register
+ */
+/*@{*/
+#define USB_RD_CONTROL(base)     (USB_CONTROL_REG(base))
+#define USB_WR_CONTROL(base, value) (USB_CONTROL_REG(base) = (value))
+#define USB_RMW_CONTROL(base, mask, value) (USB_WR_CONTROL(base, (USB_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USB_SET_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) |  (value)))
+#define USB_CLR_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) & ~(value)))
+#define USB_TOG_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW)
+ *
+ * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG
+ * device mode.
+ *
+ * Values:
+ * - 0b0 - DP Pullup in non-OTG device mode is not enabled.
+ * - 0b1 - DP Pullup in non-OTG device mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field. */
+#define USB_RD_CONTROL_DPPULLUPNONOTG(base) ((USB_CONTROL_REG(base) & USB_CONTROL_DPPULLUPNONOTG_MASK) >> USB_CONTROL_DPPULLUPNONOTG_SHIFT)
+#define USB_BRD_CONTROL_DPPULLUPNONOTG(base) (BITBAND_ACCESS8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT))
+
+/*! @brief Set the DPPULLUPNONOTG field to a new value. */
+#define USB_WR_CONTROL_DPPULLUPNONOTG(base, value) (USB_RMW_CONTROL(base, USB_CONTROL_DPPULLUPNONOTG_MASK, USB_CONTROL_DPPULLUPNONOTG(value)))
+#define USB_BWR_CONTROL_DPPULLUPNONOTG(base, value) (BITBAND_ACCESS8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBTRC0 - USB Transceiver Control register 0
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBTRC0 - USB Transceiver Control register 0 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Includes signals for basic operation of the on-chip USB Full Speed
+ * transceiver and configuration of the USB data connection that are not otherwise included
+ * in the USB Full Speed controller registers.
+ */
+/*!
+ * @name Constants and macros for entire USB_USBTRC0 register
+ */
+/*@{*/
+#define USB_RD_USBTRC0(base)     (USB_USBTRC0_REG(base))
+#define USB_WR_USBTRC0(base, value) (USB_USBTRC0_REG(base) = (value))
+#define USB_RMW_USBTRC0(base, mask, value) (USB_WR_USBTRC0(base, (USB_RD_USBTRC0(base) & ~(mask)) | (value)))
+#define USB_SET_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) |  (value)))
+#define USB_CLR_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) & ~(value)))
+#define USB_TOG_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBTRC0 bitfields
+ */
+
+/*!
+ * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No interrupt was generated.
+ * - 0b1 - Interrupt was generated because of the USB asynchronous interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field. */
+#define USB_RD_USBTRC0_USB_RESUME_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_RESUME_INT_MASK) >> USB_USBTRC0_USB_RESUME_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_RESUME_INT(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_RESUME_INT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field SYNC_DET[1] (RO)
+ *
+ * Values:
+ * - 0b0 - Synchronous interrupt has not been detected.
+ * - 0b1 - Synchronous interrupt has been detected.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_SYNC_DET field. */
+#define USB_RD_USBTRC0_SYNC_DET(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_SYNC_DET_MASK) >> USB_USBTRC0_SYNC_DET_SHIFT)
+#define USB_BRD_USBTRC0_SYNC_DET(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_SYNC_DET_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO)
+ *
+ * This read-only field will be set to value high at 1'b1 when any of USB clock
+ * recovery interrupt conditions are detected and those interrupts are unmasked.
+ * For customer use the only unmasked USB clock recovery interrupt condition
+ * results from an overflow of the frequency trim setting values indicating that the
+ * frequency trim calculated is out of the adjustment range of the IRC48M output
+ * clock. To clear this bit after it has been set, Write 0xFF to register
+ * USB_CLK_RECOVER_INT_STATUS.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field. */
+#define USB_RD_USBTRC0_USB_CLK_RECOVERY_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) >> USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_CLK_RECOVERY_INT(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESMEN[5] (RW)
+ *
+ * This bit, when set, allows the USB module to send an asynchronous wakeup
+ * event to the MCU upon detection of resume signaling on the USB bus. The MCU then
+ * re-enables clocks to the USB module. It is used for low-power suspend mode when
+ * USB module clocks are stopped or the USB transceiver is in Suspend mode.
+ * Async wakeup only works in device mode.
+ *
+ * Values:
+ * - 0b0 - USB asynchronous wakeup from suspend mode disabled.
+ * - 0b1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous
+ *     resume interrupt differs from the synchronous resume interrupt in that it
+ *     asynchronously detects K-state using the unfiltered state of the D+ and D-
+ *     pins. This interrupt should only be enabled when the Transceiver is
+ *     suspended.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USBRESMEN field. */
+#define USB_RD_USBTRC0_USBRESMEN(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USBRESMEN_MASK) >> USB_USBTRC0_USBRESMEN_SHIFT)
+#define USB_BRD_USBTRC0_USBRESMEN(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT))
+
+/*! @brief Set the USBRESMEN field to a new value. */
+#define USB_WR_USBTRC0_USBRESMEN(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESMEN_MASK, USB_USBTRC0_USBRESMEN(value)))
+#define USB_BWR_USBTRC0_USBRESMEN(base, value) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESET[7] (WO)
+ *
+ * Generates a hard reset to USBOTG. After this bit is set and the reset occurs,
+ * this bit is automatically cleared. This bit is always read as zero. Wait two
+ * USB clock cycles after setting this bit.
+ *
+ * Values:
+ * - 0b0 - Normal USB module operation.
+ * - 0b1 - Returns the USB module to its reset state.
+ */
+/*@{*/
+/*! @brief Set the USBRESET field to a new value. */
+#define USB_WR_USBTRC0_USBRESET(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESET_MASK, USB_USBTRC0_USBRESET(value)))
+#define USB_BWR_USBTRC0_USBRESET(base, value) (USB_WR_USBTRC0_USBRESET(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBFRMADJUST - Frame Adjust Register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBFRMADJUST - Frame Adjust Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBFRMADJUST register
+ */
+/*@{*/
+#define USB_RD_USBFRMADJUST(base) (USB_USBFRMADJUST_REG(base))
+#define USB_WR_USBFRMADJUST(base, value) (USB_USBFRMADJUST_REG(base) = (value))
+#define USB_RMW_USBFRMADJUST(base, mask, value) (USB_WR_USBFRMADJUST(base, (USB_RD_USBFRMADJUST(base) & ~(mask)) | (value)))
+#define USB_SET_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) |  (value)))
+#define USB_CLR_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) & ~(value)))
+#define USB_TOG_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Signals in this register control the crystal-less USB clock mode in which the
+ * internal IRC48M oscillator is tuned to match the clock extracted from the
+ * incoming USB data stream. The IRC48M internal oscillator module must be enabled
+ * in register USB_CLK_RECOVER_IRC_EN for this mode.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_CTRL(base) (USB_CLK_RECOVER_CTRL_REG(base))
+#define USB_WR_CLK_RECOVER_CTRL(base, value) (USB_CLK_RECOVER_CTRL_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_CTRL(base, mask, value) (USB_WR_CLK_RECOVER_CTRL(base, (USB_RD_CLK_RECOVER_CTRL(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW)
+ *
+ * IRC48 has a default trim fine value whose default value is factory trimmed
+ * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz
+ * and keeps updating the trim fine value accordingly
+ *
+ * Values:
+ * - 0b0 - Trim fine adjustment always works based on the previous updated trim
+ *     fine value (default)
+ * - 0b1 - Trim fine restarts from the IFR trim value whenever
+ *     bus_reset/bus_resume is detected or module enable is desasserted
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))
+
+/*! @brief Set the RESTART_IFRTRIM_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW)
+ *
+ * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock.
+ * It has two phases after user enables clock_recover_en bit, rough phase and
+ * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine
+ * value is different during these two phases. The step in rough phase is larger
+ * than that in tracking phase. Switch back to rough stage whenever USB bus reset
+ * or bus resume occurs.
+ *
+ * Values:
+ * - 0b0 - Always works in tracking phase after the 1st time rough to track
+ *     transition (default)
+ * - 0b1 - Go back to rough stage whenever bus reset or bus resume occurs
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))
+
+/*! @brief Set the RESET_RESUME_ROUGH_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW)
+ *
+ * This bit must be enabled if user wants to use the crystal-less USB mode for
+ * the Full Speed USB controller and transceiver. This bit should not be set for
+ * USB host mode or OTG.
+ *
+ * Values:
+ * - 0b0 - Disable clock recovery block (default)
+ * - 0b1 - Enable clock recovery block
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) >> USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))
+
+/*! @brief Set the CLOCK_RECOVER_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * Controls basic operation of the on-chip IRC48M module used to produce nominal
+ * 48MHz clocks for USB crystal-less operation and other functions. See
+ * additional information about the IRC48M operation in the Clock Distribution chapter.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_IRC_EN(base) (USB_CLK_RECOVER_IRC_EN_REG(base))
+#define USB_WR_CLK_RECOVER_IRC_EN(base, value) (USB_CLK_RECOVER_IRC_EN_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_IRC_EN(base, mask, value) (USB_WR_CLK_RECOVER_IRC_EN(base, (USB_RD_CLK_RECOVER_IRC_EN(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW)
+ *
+ * This bit is used to enable the local analog regulator for IRC48Mhz module.
+ * This bit must be set if user wants to use the crystal-less USB clock
+ * configuration.
+ *
+ * Values:
+ * - 0b0 - IRC48M local regulator is disabled
+ * - 0b1 - IRC48M local regulator is enabled (default)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_REG_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_REG_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))
+
+/*! @brief Set the REG_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_REG_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_REG_EN_MASK, USB_CLK_RECOVER_IRC_EN_REG_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_REG_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
+ *
+ * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
+ * crystal-less USB. It can only be used for FS USB device mode operation. This
+ * bit must be set before using the crystal-less USB clock configuration.
+ *
+ * Values:
+ * - 0b0 - Disable the IRC48M module (default)
+ * - 0b1 - Enable the IRC48M module
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_IRC_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_IRC_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))
+
+/*! @brief Set the IRC_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK, USB_CLK_RECOVER_IRC_EN_IRC_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * A Write operation with value high at 1'b1 on any combination of individual
+ * bits will clear those bits.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_INT_STATUS(base) (USB_CLK_RECOVER_INT_STATUS_REG(base))
+#define USB_WR_CLK_RECOVER_INT_STATUS(base, value) (USB_CLK_RECOVER_INT_STATUS_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_INT_STATUS(base, mask, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, (USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C)
+ *
+ * Indicates that the USB clock recovery algorithm has detected that the
+ * frequency trim adjustment needed for the IRC48M output clock is outside the available
+ * TRIM_FINE adjustment range for the IRC48M module.
+ *
+ * Values:
+ * - 0b0 - No interrupt is reported
+ * - 0b1 - Unmasked interrupt has been generated
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field. */
+#define USB_RD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) ((USB_CLK_RECOVER_INT_STATUS_REG(base) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) >> USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)
+#define USB_BRD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))
+
+/*! @brief Set the OVF_ERROR field to a new value. */
+#define USB_WR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (USB_RMW_CLK_RECOVER_INT_STATUS(base, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(value)))
+#define USB_BWR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 USBDCD
+ *
+ * USB Device Charger Detection module
+ *
+ * Registers defined in this header file:
+ * - USBDCD_CONTROL - Control register
+ * - USBDCD_CLOCK - Clock register
+ * - USBDCD_STATUS - Status register
+ * - USBDCD_TIMER0 - TIMER0 register
+ * - USBDCD_TIMER1 - TIMER1 register
+ * - USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ * - USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ */
+
+#define USBDCD_INSTANCE_COUNT (1U) /*!< Number of instances of the USBDCD module. */
+#define USBDCD_IDX (0U) /*!< Instance number for USBDCD. */
+
+/*******************************************************************************
+ * USBDCD_CONTROL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_CONTROL - Control register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Contains the control and interrupt bit fields.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_CONTROL register
+ */
+/*@{*/
+#define USBDCD_RD_CONTROL(base)  (USBDCD_CONTROL_REG(base))
+#define USBDCD_WR_CONTROL(base, value) (USBDCD_CONTROL_REG(base) = (value))
+#define USBDCD_RMW_CONTROL(base, mask, value) (USBDCD_WR_CONTROL(base, (USBDCD_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USBDCD_SET_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) |  (value)))
+#define USBDCD_CLR_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) & ~(value)))
+#define USBDCD_TOG_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CONTROL, field IACK[0] (WORZ)
+ *
+ * Determines whether the interrupt is cleared.
+ *
+ * Values:
+ * - 0b0 - Do not clear the interrupt.
+ * - 0b1 - Clear the IF bit (interrupt flag).
+ */
+/*@{*/
+/*! @brief Set the IACK field to a new value. */
+#define USBDCD_WR_CONTROL_IACK(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_IACK_MASK, USBDCD_CONTROL_IACK(value)))
+#define USBDCD_BWR_CONTROL_IACK(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field IF[8] (RO)
+ *
+ * Determines whether an interrupt is pending.
+ *
+ * Values:
+ * - 0b0 - No interrupt is pending.
+ * - 0b1 - An interrupt is pending.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_IF field. */
+#define USBDCD_RD_CONTROL_IF(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_IF_MASK) >> USBDCD_CONTROL_IF_SHIFT)
+#define USBDCD_BRD_CONTROL_IF(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field IE[16] (RW)
+ *
+ * Enables/disables interrupts to the system.
+ *
+ * Values:
+ * - 0b0 - Disable interrupts to the system.
+ * - 0b1 - Enable interrupts to the system.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_IE field. */
+#define USBDCD_RD_CONTROL_IE(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_IE_MASK) >> USBDCD_CONTROL_IE_SHIFT)
+#define USBDCD_BRD_CONTROL_IE(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IE_SHIFT))
+
+/*! @brief Set the IE field to a new value. */
+#define USBDCD_WR_CONTROL_IE(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_IE_MASK, USBDCD_CONTROL_IE(value)))
+#define USBDCD_BWR_CONTROL_IE(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field BC12[17] (RW)
+ *
+ * BC1.2 compatibility. This bit cannot be changed after start detection.
+ *
+ * Values:
+ * - 0b0 - Compatible with BC1.1 (default)
+ * - 0b1 - Compatible with BC1.2
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_BC12 field. */
+#define USBDCD_RD_CONTROL_BC12(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_BC12_MASK) >> USBDCD_CONTROL_BC12_SHIFT)
+#define USBDCD_BRD_CONTROL_BC12(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_BC12_SHIFT))
+
+/*! @brief Set the BC12 field to a new value. */
+#define USBDCD_WR_CONTROL_BC12(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_BC12_MASK, USBDCD_CONTROL_BC12(value)))
+#define USBDCD_BWR_CONTROL_BC12(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_BC12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field START[24] (WORZ)
+ *
+ * Determines whether the charger detection sequence is initiated.
+ *
+ * Values:
+ * - 0b0 - Do not start the sequence. Writes of this value have no effect.
+ * - 0b1 - Initiate the charger detection sequence. If the sequence is already
+ *     running, writes of this value have no effect.
+ */
+/*@{*/
+/*! @brief Set the START field to a new value. */
+#define USBDCD_WR_CONTROL_START(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_START_MASK, USBDCD_CONTROL_START(value)))
+#define USBDCD_BWR_CONTROL_START(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_START_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field SR[25] (WORZ)
+ *
+ * Determines whether a software reset is performed.
+ *
+ * Values:
+ * - 0b0 - Do not perform a software reset.
+ * - 0b1 - Perform a software reset.
+ */
+/*@{*/
+/*! @brief Set the SR field to a new value. */
+#define USBDCD_WR_CONTROL_SR(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_SR_MASK, USBDCD_CONTROL_SR(value)))
+#define USBDCD_BWR_CONTROL_SR(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_SR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_CLOCK - Clock register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_CLOCK - Clock register (RW)
+ *
+ * Reset value: 0x000000C1U
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_CLOCK register
+ */
+/*@{*/
+#define USBDCD_RD_CLOCK(base)    (USBDCD_CLOCK_REG(base))
+#define USBDCD_WR_CLOCK(base, value) (USBDCD_CLOCK_REG(base) = (value))
+#define USBDCD_RMW_CLOCK(base, mask, value) (USBDCD_WR_CLOCK(base, (USBDCD_RD_CLOCK(base) & ~(mask)) | (value)))
+#define USBDCD_SET_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) |  (value)))
+#define USBDCD_CLR_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) & ~(value)))
+#define USBDCD_TOG_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_CLOCK bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW)
+ *
+ * Specifies the unit of measure for the clock speed.
+ *
+ * Values:
+ * - 0b0 - kHz Speed (between 1 kHz and 1023 kHz)
+ * - 0b1 - MHz Speed (between 1 MHz and 1023 MHz)
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field. */
+#define USBDCD_RD_CLOCK_CLOCK_UNIT(base) ((USBDCD_CLOCK_REG(base) & USBDCD_CLOCK_CLOCK_UNIT_MASK) >> USBDCD_CLOCK_CLOCK_UNIT_SHIFT)
+#define USBDCD_BRD_CLOCK_CLOCK_UNIT(base) (BITBAND_ACCESS32(&USBDCD_CLOCK_REG(base), USBDCD_CLOCK_CLOCK_UNIT_SHIFT))
+
+/*! @brief Set the CLOCK_UNIT field to a new value. */
+#define USBDCD_WR_CLOCK_CLOCK_UNIT(base, value) (USBDCD_RMW_CLOCK(base, USBDCD_CLOCK_CLOCK_UNIT_MASK, USBDCD_CLOCK_CLOCK_UNIT(value)))
+#define USBDCD_BWR_CLOCK_CLOCK_UNIT(base, value) (BITBAND_ACCESS32(&USBDCD_CLOCK_REG(base), USBDCD_CLOCK_CLOCK_UNIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW)
+ *
+ * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to
+ * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples
+ * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz:
+ * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100)
+ * For 500 kHz: 0b01_1111_0100 (500)
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field. */
+#define USBDCD_RD_CLOCK_CLOCK_SPEED(base) ((USBDCD_CLOCK_REG(base) & USBDCD_CLOCK_CLOCK_SPEED_MASK) >> USBDCD_CLOCK_CLOCK_SPEED_SHIFT)
+#define USBDCD_BRD_CLOCK_CLOCK_SPEED(base) (USBDCD_RD_CLOCK_CLOCK_SPEED(base))
+
+/*! @brief Set the CLOCK_SPEED field to a new value. */
+#define USBDCD_WR_CLOCK_CLOCK_SPEED(base, value) (USBDCD_RMW_CLOCK(base, USBDCD_CLOCK_CLOCK_SPEED_MASK, USBDCD_CLOCK_CLOCK_SPEED(value)))
+#define USBDCD_BWR_CLOCK_CLOCK_SPEED(base, value) (USBDCD_WR_CLOCK_CLOCK_SPEED(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_STATUS - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_STATUS - Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Provides the current state of the module for system software monitoring.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_STATUS register
+ */
+/*@{*/
+#define USBDCD_RD_STATUS(base)   (USBDCD_STATUS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_STATUS bitfields
+ */
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO)
+ *
+ * Reports how the charger detection is attached.
+ *
+ * Values:
+ * - 0b00 - No results to report.
+ * - 0b01 - Attached to a standard host. Must comply with USB 2.0 by drawing
+ *     only 2.5 mA (max) until connected.
+ * - 0b10 - Attached to a charging port. The exact meaning depends on bit 18: 0:
+ *     Attached to either a charging host or a dedicated charger. The charger
+ *     type detection has not completed. 1: Attached to a charging host. The
+ *     charger type detection has completed.
+ * - 0b11 - Attached to a dedicated charger.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_SEQ_RES field. */
+#define USBDCD_RD_STATUS_SEQ_RES(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_SEQ_RES_MASK) >> USBDCD_STATUS_SEQ_RES_SHIFT)
+#define USBDCD_BRD_STATUS_SEQ_RES(base) (USBDCD_RD_STATUS_SEQ_RES(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO)
+ *
+ * Indicates the status of the charger detection sequence.
+ *
+ * Values:
+ * - 0b00 - The module is either not enabled, or the module is enabled but the
+ *     data pins have not yet been detected.
+ * - 0b01 - Data pin contact detection is complete.
+ * - 0b10 - Charging port detection is complete.
+ * - 0b11 - Charger type detection is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field. */
+#define USBDCD_RD_STATUS_SEQ_STAT(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_SEQ_STAT_MASK) >> USBDCD_STATUS_SEQ_STAT_SHIFT)
+#define USBDCD_BRD_STATUS_SEQ_STAT(base) (USBDCD_RD_STATUS_SEQ_STAT(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field ERR[20] (RO)
+ *
+ * Indicates whether there is an error in the detection sequence.
+ *
+ * Values:
+ * - 0b0 - No sequence errors.
+ * - 0b1 - Error in the detection sequence. See the SEQ_STAT field to determine
+ *     the phase in which the error occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_ERR field. */
+#define USBDCD_RD_STATUS_ERR(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_ERR_MASK) >> USBDCD_STATUS_ERR_SHIFT)
+#define USBDCD_BRD_STATUS_ERR(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field TO[21] (RO)
+ *
+ * Indicates whether the detection sequence has passed the timeout threshhold.
+ *
+ * Values:
+ * - 0b0 - The detection sequence has not been running for over 1 s.
+ * - 0b1 - It has been over 1 s since the data pin contact was detected and
+ *     debounced.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_TO field. */
+#define USBDCD_RD_STATUS_TO(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_TO_MASK) >> USBDCD_STATUS_TO_SHIFT)
+#define USBDCD_BRD_STATUS_TO(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_TO_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field ACTIVE[22] (RO)
+ *
+ * Indicates whether the sequence is running.
+ *
+ * Values:
+ * - 0b0 - The sequence is not running.
+ * - 0b1 - The sequence is running.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_ACTIVE field. */
+#define USBDCD_RD_STATUS_ACTIVE(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_ACTIVE_MASK) >> USBDCD_STATUS_ACTIVE_SHIFT)
+#define USBDCD_BRD_STATUS_ACTIVE(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_ACTIVE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER0 - TIMER0 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER0 - TIMER0 register (RW)
+ *
+ * Reset value: 0x00100000U
+ *
+ * TIMER0 has an TSEQ_INIT field that represents the system latency in ms.
+ * Latency is measured from the time when VBUS goes active until the time system
+ * software initiates charger detection sequence in USBDCD module. When software sets
+ * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized
+ * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery
+ * Charging Specification requires the entire sequence, including TSEQ_INIT, to be
+ * completed in 1s or less.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER0 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER0(base)   (USBDCD_TIMER0_REG(base))
+#define USBDCD_WR_TIMER0(base, value) (USBDCD_TIMER0_REG(base) = (value))
+#define USBDCD_RMW_TIMER0(base, mask, value) (USBDCD_WR_TIMER0(base, (USBDCD_RD_TIMER0(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) |  (value)))
+#define USBDCD_CLR_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) & ~(value)))
+#define USBDCD_TOG_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER0 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO)
+ *
+ * Displays the amount of elapsed time since the event of setting the START bit
+ * plus the value of TSEQ_INIT. The timer is automatically initialized with the
+ * value of TSEQ_INIT before starting to count. This timer enables compliance with
+ * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging
+ * Specification. If the timer reaches the one second limit, the module triggers
+ * an interrupt and sets the error flag STATUS[ERR]. The timer continues
+ * counting throughout the charger detection sequence, even when control has been passed
+ * to software. As long as the module is active, the timer continues to count
+ * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not
+ * rollover to zero. A software reset clears the timer.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER0_TUNITCON field. */
+#define USBDCD_RD_TIMER0_TUNITCON(base) ((USBDCD_TIMER0_REG(base) & USBDCD_TIMER0_TUNITCON_MASK) >> USBDCD_TIMER0_TUNITCON_SHIFT)
+#define USBDCD_BRD_TIMER0_TUNITCON(base) (USBDCD_RD_TIMER0_TUNITCON(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW)
+ *
+ * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS
+ * goes active to the time system software initiates the charger detection
+ * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit
+ * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid
+ * values are 0-1023, but the USB Battery Charging Specification requires the
+ * entire sequence, including TSEQ_INIT, to be completed in 1s or less.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field. */
+#define USBDCD_RD_TIMER0_TSEQ_INIT(base) ((USBDCD_TIMER0_REG(base) & USBDCD_TIMER0_TSEQ_INIT_MASK) >> USBDCD_TIMER0_TSEQ_INIT_SHIFT)
+#define USBDCD_BRD_TIMER0_TSEQ_INIT(base) (USBDCD_RD_TIMER0_TSEQ_INIT(base))
+
+/*! @brief Set the TSEQ_INIT field to a new value. */
+#define USBDCD_WR_TIMER0_TSEQ_INIT(base, value) (USBDCD_RMW_TIMER0(base, USBDCD_TIMER0_TSEQ_INIT_MASK, USBDCD_TIMER0_TSEQ_INIT(value)))
+#define USBDCD_BWR_TIMER0_TSEQ_INIT(base, value) (USBDCD_WR_TIMER0_TSEQ_INIT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER1 - TIMER1 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER1 - TIMER1 register (RW)
+ *
+ * Reset value: 0x000A0028U
+ *
+ * TIMER1 contains timing parameters. Note that register values can be written
+ * that are not compliant with the USB Battery Charging Specification, so care
+ * should be taken when overwriting the default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER1 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER1(base)   (USBDCD_TIMER1_REG(base))
+#define USBDCD_WR_TIMER1(base, value) (USBDCD_TIMER1_REG(base) = (value))
+#define USBDCD_RMW_TIMER1(base, mask, value) (USBDCD_WR_TIMER1(base, (USBDCD_RD_TIMER1(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) |  (value)))
+#define USBDCD_CLR_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) & ~(value)))
+#define USBDCD_TOG_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER1 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW)
+ *
+ * This timing parameter is used after detection of the data pin. See "Charging
+ * Port Detection". Valid values are 1-1023, but the USB Battery Charging
+ * Specification requires a minimum value of 40 ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field. */
+#define USBDCD_RD_TIMER1_TVDPSRC_ON(base) ((USBDCD_TIMER1_REG(base) & USBDCD_TIMER1_TVDPSRC_ON_MASK) >> USBDCD_TIMER1_TVDPSRC_ON_SHIFT)
+#define USBDCD_BRD_TIMER1_TVDPSRC_ON(base) (USBDCD_RD_TIMER1_TVDPSRC_ON(base))
+
+/*! @brief Set the TVDPSRC_ON field to a new value. */
+#define USBDCD_WR_TIMER1_TVDPSRC_ON(base, value) (USBDCD_RMW_TIMER1(base, USBDCD_TIMER1_TVDPSRC_ON_MASK, USBDCD_TIMER1_TVDPSRC_ON(value)))
+#define USBDCD_BWR_TIMER1_TVDPSRC_ON(base, value) (USBDCD_WR_TIMER1_TVDPSRC_ON(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW)
+ *
+ * Sets the time period (ms) to debounce the D+ signal during the data pin
+ * contact detection phase. See "Debouncing the data pin contact" Valid values are
+ * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10
+ * ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field. */
+#define USBDCD_RD_TIMER1_TDCD_DBNC(base) ((USBDCD_TIMER1_REG(base) & USBDCD_TIMER1_TDCD_DBNC_MASK) >> USBDCD_TIMER1_TDCD_DBNC_SHIFT)
+#define USBDCD_BRD_TIMER1_TDCD_DBNC(base) (USBDCD_RD_TIMER1_TDCD_DBNC(base))
+
+/*! @brief Set the TDCD_DBNC field to a new value. */
+#define USBDCD_WR_TIMER1_TDCD_DBNC(base, value) (USBDCD_RMW_TIMER1(base, USBDCD_TIMER1_TDCD_DBNC_MASK, USBDCD_TIMER1_TDCD_DBNC(value)))
+#define USBDCD_BWR_TIMER1_TDCD_DBNC(base, value) (USBDCD_WR_TIMER1_TDCD_DBNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW)
+ *
+ * Reset value: 0x00280001U
+ *
+ * TIMER2_BC11 contains timing parameters for USB Battery Charging
+ * Specification, v1.1. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC11 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER2_BC11(base) (USBDCD_TIMER2_BC11_REG(base))
+#define USBDCD_WR_TIMER2_BC11(base, value) (USBDCD_TIMER2_BC11_REG(base) = (value))
+#define USBDCD_RMW_TIMER2_BC11(base, mask, value) (USBDCD_WR_TIMER2_BC11(base, (USBDCD_RD_TIMER2_BC11(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) |  (value)))
+#define USBDCD_CLR_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) & ~(value)))
+#define USBDCD_TOG_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after the device
+ * connects to the USB bus until checking the state of the D- line to determine the
+ * type of charging port. See "Charger Type Detection." Valid values are 1-15ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field. */
+#define USBDCD_RD_TIMER2_BC11_CHECK_DM(base) ((USBDCD_TIMER2_BC11_REG(base) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) >> USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)
+#define USBDCD_BRD_TIMER2_BC11_CHECK_DM(base) (USBDCD_RD_TIMER2_BC11_CHECK_DM(base))
+
+/*! @brief Set the CHECK_DM field to a new value. */
+#define USBDCD_WR_TIMER2_BC11_CHECK_DM(base, value) (USBDCD_RMW_TIMER2_BC11(base, USBDCD_TIMER2_BC11_CHECK_DM_MASK, USBDCD_TIMER2_BC11_CHECK_DM(value)))
+#define USBDCD_BWR_TIMER2_BC11_CHECK_DM(base, value) (USBDCD_WR_TIMER2_BC11_CHECK_DM(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW)
+ *
+ * Sets the time period (ms) that the module waits after charging port detection
+ * before system software must enable the D+ pullup to connect to the USB host.
+ * Valid values are 1-1023, but the USB Battery Charging Specification requires a
+ * minimum value of 40 ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field. */
+#define USBDCD_RD_TIMER2_BC11_TVDPSRC_CON(base) ((USBDCD_TIMER2_BC11_REG(base) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) >> USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)
+#define USBDCD_BRD_TIMER2_BC11_TVDPSRC_CON(base) (USBDCD_RD_TIMER2_BC11_TVDPSRC_CON(base))
+
+/*! @brief Set the TVDPSRC_CON field to a new value. */
+#define USBDCD_WR_TIMER2_BC11_TVDPSRC_CON(base, value) (USBDCD_RMW_TIMER2_BC11(base, USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK, USBDCD_TIMER2_BC11_TVDPSRC_CON(value)))
+#define USBDCD_BWR_TIMER2_BC11_TVDPSRC_CON(base, value) (USBDCD_WR_TIMER2_BC11_TVDPSRC_CON(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW)
+ *
+ * Reset value: 0x00010028U
+ *
+ * TIMER2_BC12 contains timing parameters for USB Battery Charging
+ * Specification, v1.2. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC12 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER2_BC12(base) (USBDCD_TIMER2_BC12_REG(base))
+#define USBDCD_WR_TIMER2_BC12(base, value) (USBDCD_TIMER2_BC12_REG(base) = (value))
+#define USBDCD_RMW_TIMER2_BC12(base, mask, value) (USBDCD_WR_TIMER2_BC12(base, (USBDCD_RD_TIMER2_BC12(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) |  (value)))
+#define USBDCD_CLR_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) & ~(value)))
+#define USBDCD_TOG_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid
+ * values are 0-40ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field. */
+#define USBDCD_RD_TIMER2_BC12_TVDMSRC_ON(base) ((USBDCD_TIMER2_BC12_REG(base) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) >> USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)
+#define USBDCD_BRD_TIMER2_BC12_TVDMSRC_ON(base) (USBDCD_RD_TIMER2_BC12_TVDMSRC_ON(base))
+
+/*! @brief Set the TVDMSRC_ON field to a new value. */
+#define USBDCD_WR_TIMER2_BC12_TVDMSRC_ON(base, value) (USBDCD_RMW_TIMER2_BC12(base, USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK, USBDCD_TIMER2_BC12_TVDMSRC_ON(value)))
+#define USBDCD_BWR_TIMER2_BC12_TVDMSRC_ON(base, value) (USBDCD_WR_TIMER2_BC12_TVDMSRC_ON(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after primary detection
+ * before start to secondary detection. Valid values are 1-1023ms. Default is
+ * 1ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field. */
+#define USBDCD_RD_TIMER2_BC12_TWAIT_AFTER_PRD(base) ((USBDCD_TIMER2_BC12_REG(base) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) >> USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)
+#define USBDCD_BRD_TIMER2_BC12_TWAIT_AFTER_PRD(base) (USBDCD_RD_TIMER2_BC12_TWAIT_AFTER_PRD(base))
+
+/*! @brief Set the TWAIT_AFTER_PRD field to a new value. */
+#define USBDCD_WR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value) (USBDCD_RMW_TIMER2_BC12(base, USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK, USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(value)))
+#define USBDCD_BWR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value) (USBDCD_WR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value))
+/*@}*/
+
+/*
+ * MK64F12 VREF
+ *
+ * Voltage Reference
+ *
+ * Registers defined in this header file:
+ * - VREF_TRM - VREF Trim Register
+ * - VREF_SC - VREF Status and Control Register
+ */
+
+#define VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
+#define VREF_IDX (0U) /*!< Instance number for VREF. */
+
+/*******************************************************************************
+ * VREF_TRM - VREF Trim Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_TRM - VREF Trim Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains bits that contain the trim data for the Voltage
+ * Reference.
+ */
+/*!
+ * @name Constants and macros for entire VREF_TRM register
+ */
+/*@{*/
+#define VREF_RD_TRM(base)        (VREF_TRM_REG(base))
+#define VREF_WR_TRM(base, value) (VREF_TRM_REG(base) = (value))
+#define VREF_RMW_TRM(base, mask, value) (VREF_WR_TRM(base, (VREF_RD_TRM(base) & ~(mask)) | (value)))
+#define VREF_SET_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) |  (value)))
+#define VREF_CLR_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) & ~(value)))
+#define VREF_TOG_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_TRM bitfields
+ */
+
+/*!
+ * @name Register VREF_TRM, field TRIM[5:0] (RW)
+ *
+ * These bits change the resulting VREF by approximately +/- 0.5 mV for each
+ * step. Min = minimum and max = maximum voltage reference output. For minimum and
+ * maximum voltage reference output values, refer to the Data Sheet for this chip.
+ *
+ * Values:
+ * - 0b000000 - Min
+ * - 0b111111 - Max
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_TRIM field. */
+#define VREF_RD_TRM_TRIM(base) ((VREF_TRM_REG(base) & VREF_TRM_TRIM_MASK) >> VREF_TRM_TRIM_SHIFT)
+#define VREF_BRD_TRM_TRIM(base) (VREF_RD_TRM_TRIM(base))
+
+/*! @brief Set the TRIM field to a new value. */
+#define VREF_WR_TRM_TRIM(base, value) (VREF_RMW_TRM(base, VREF_TRM_TRIM_MASK, VREF_TRM_TRIM(value)))
+#define VREF_BWR_TRM_TRIM(base, value) (VREF_WR_TRM_TRIM(base, value))
+/*@}*/
+
+/*!
+ * @name Register VREF_TRM, field CHOPEN[6] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0b0 - Chop oscillator is disabled.
+ * - 0b1 - Chop oscillator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_CHOPEN field. */
+#define VREF_RD_TRM_CHOPEN(base) ((VREF_TRM_REG(base) & VREF_TRM_CHOPEN_MASK) >> VREF_TRM_CHOPEN_SHIFT)
+#define VREF_BRD_TRM_CHOPEN(base) (BITBAND_ACCESS8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT))
+
+/*! @brief Set the CHOPEN field to a new value. */
+#define VREF_WR_TRM_CHOPEN(base, value) (VREF_RMW_TRM(base, VREF_TRM_CHOPEN_MASK, VREF_TRM_CHOPEN(value)))
+#define VREF_BWR_TRM_CHOPEN(base, value) (BITBAND_ACCESS8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * VREF_SC - VREF Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_SC - VREF Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the control bits used to enable the internal voltage
+ * reference and to select the buffer mode to be used.
+ */
+/*!
+ * @name Constants and macros for entire VREF_SC register
+ */
+/*@{*/
+#define VREF_RD_SC(base)         (VREF_SC_REG(base))
+#define VREF_WR_SC(base, value)  (VREF_SC_REG(base) = (value))
+#define VREF_RMW_SC(base, mask, value) (VREF_WR_SC(base, (VREF_RD_SC(base) & ~(mask)) | (value)))
+#define VREF_SET_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) |  (value)))
+#define VREF_CLR_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) & ~(value)))
+#define VREF_TOG_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_SC bitfields
+ */
+
+/*!
+ * @name Register VREF_SC, field MODE_LV[1:0] (RW)
+ *
+ * These bits select the buffer modes for the Voltage Reference module.
+ *
+ * Values:
+ * - 0b00 - Bandgap on only, for stabilization and startup
+ * - 0b01 - High power buffer mode enabled
+ * - 0b10 - Low-power buffer mode enabled
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_MODE_LV field. */
+#define VREF_RD_SC_MODE_LV(base) ((VREF_SC_REG(base) & VREF_SC_MODE_LV_MASK) >> VREF_SC_MODE_LV_SHIFT)
+#define VREF_BRD_SC_MODE_LV(base) (VREF_RD_SC_MODE_LV(base))
+
+/*! @brief Set the MODE_LV field to a new value. */
+#define VREF_WR_SC_MODE_LV(base, value) (VREF_RMW_SC(base, VREF_SC_MODE_LV_MASK, VREF_SC_MODE_LV(value)))
+#define VREF_BWR_SC_MODE_LV(base, value) (VREF_WR_SC_MODE_LV(base, value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFST[2] (RO)
+ *
+ * This bit indicates that the bandgap reference within the Voltage Reference
+ * module has completed its startup and stabilization.
+ *
+ * Values:
+ * - 0b0 - The module is disabled or not stable.
+ * - 0b1 - The module is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFST field. */
+#define VREF_RD_SC_VREFST(base) ((VREF_SC_REG(base) & VREF_SC_VREFST_MASK) >> VREF_SC_VREFST_SHIFT)
+#define VREF_BRD_SC_VREFST(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field ICOMPEN[5] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_ICOMPEN field. */
+#define VREF_RD_SC_ICOMPEN(base) ((VREF_SC_REG(base) & VREF_SC_ICOMPEN_MASK) >> VREF_SC_ICOMPEN_SHIFT)
+#define VREF_BRD_SC_ICOMPEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT))
+
+/*! @brief Set the ICOMPEN field to a new value. */
+#define VREF_WR_SC_ICOMPEN(base, value) (VREF_RMW_SC(base, VREF_SC_ICOMPEN_MASK, VREF_SC_ICOMPEN(value)))
+#define VREF_BWR_SC_ICOMPEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field REGEN[6] (RW)
+ *
+ * This bit is used to enable the internal 1.75 V regulator to produce a
+ * constant internal voltage supply in order to reduce the sensitivity to external
+ * supply noise and variation. If it is desired to keep the regulator enabled in very
+ * low power modes, refer to the Chip Configuration details for a description on
+ * how this can be achieved. This bit is set during factory trimming of the VREF
+ * voltage. This bit should be written to 1 to achieve the performance stated in
+ * the data sheet.
+ *
+ * Values:
+ * - 0b0 - Internal 1.75 V regulator is disabled.
+ * - 0b1 - Internal 1.75 V regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_REGEN field. */
+#define VREF_RD_SC_REGEN(base) ((VREF_SC_REG(base) & VREF_SC_REGEN_MASK) >> VREF_SC_REGEN_SHIFT)
+#define VREF_BRD_SC_REGEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT))
+
+/*! @brief Set the REGEN field to a new value. */
+#define VREF_WR_SC_REGEN(base, value) (VREF_RMW_SC(base, VREF_SC_REGEN_MASK, VREF_SC_REGEN(value)))
+#define VREF_BWR_SC_REGEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFEN[7] (RW)
+ *
+ * This bit is used to enable the bandgap reference within the Voltage Reference
+ * module. After the VREF is enabled, turning off the clock to the VREF module
+ * via the corresponding clock gate register will not disable the VREF. VREF must
+ * be disabled via this VREFEN bit.
+ *
+ * Values:
+ * - 0b0 - The module is disabled.
+ * - 0b1 - The module is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFEN field. */
+#define VREF_RD_SC_VREFEN(base) ((VREF_SC_REG(base) & VREF_SC_VREFEN_MASK) >> VREF_SC_VREFEN_SHIFT)
+#define VREF_BRD_SC_VREFEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT))
+
+/*! @brief Set the VREFEN field to a new value. */
+#define VREF_WR_SC_VREFEN(base, value) (VREF_RMW_SC(base, VREF_SC_VREFEN_MASK, VREF_SC_VREFEN(value)))
+#define VREF_BWR_SC_VREFEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 WDOG
+ *
+ * Generation 2008 Watchdog Timer
+ *
+ * Registers defined in this header file:
+ * - WDOG_STCTRLH - Watchdog Status and Control Register High
+ * - WDOG_STCTRLL - Watchdog Status and Control Register Low
+ * - WDOG_TOVALH - Watchdog Time-out Value Register High
+ * - WDOG_TOVALL - Watchdog Time-out Value Register Low
+ * - WDOG_WINH - Watchdog Window Register High
+ * - WDOG_WINL - Watchdog Window Register Low
+ * - WDOG_REFRESH - Watchdog Refresh register
+ * - WDOG_UNLOCK - Watchdog Unlock register
+ * - WDOG_TMROUTH - Watchdog Timer Output Register High
+ * - WDOG_TMROUTL - Watchdog Timer Output Register Low
+ * - WDOG_RSTCNT - Watchdog Reset Count register
+ * - WDOG_PRESC - Watchdog Prescaler register
+ */
+
+#define WDOG_INSTANCE_COUNT (1U) /*!< Number of instances of the WDOG module. */
+#define WDOG_IDX (0U) /*!< Instance number for WDOG. */
+
+/*******************************************************************************
+ * WDOG_STCTRLH - Watchdog Status and Control Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
+ *
+ * Reset value: 0x01D3U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLH register
+ */
+/*@{*/
+#define WDOG_RD_STCTRLH(base)    (WDOG_STCTRLH_REG(base))
+#define WDOG_WR_STCTRLH(base, value) (WDOG_STCTRLH_REG(base) = (value))
+#define WDOG_RMW_STCTRLH(base, mask, value) (WDOG_WR_STCTRLH(base, (WDOG_RD_STCTRLH(base) & ~(mask)) | (value)))
+#define WDOG_SET_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) |  (value)))
+#define WDOG_CLR_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) & ~(value)))
+#define WDOG_TOG_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_STCTRLH bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
+ *
+ * Enables or disables the WDOG's operation. In the disabled state, the watchdog
+ * timer is kept in the reset state, but the other exception conditions can
+ * still trigger a reset/interrupt. A change in the value of this bit must be held
+ * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled.
+ * - 0b1 - WDOG is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. */
+#define WDOG_RD_STCTRLH_WDOGEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WDOGEN_MASK) >> WDOG_STCTRLH_WDOGEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WDOGEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WDOGEN_SHIFT))
+
+/*! @brief Set the WDOGEN field to a new value. */
+#define WDOG_WR_STCTRLH_WDOGEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WDOGEN_MASK, WDOG_STCTRLH_WDOGEN(value)))
+#define WDOG_BWR_STCTRLH_WDOGEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WDOGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
+ *
+ * Selects clock source for the WDOG timer and other internal timing operations.
+ *
+ * Values:
+ * - 0b0 - WDOG clock sourced from LPO .
+ * - 0b1 - WDOG clock sourced from alternate clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. */
+#define WDOG_RD_STCTRLH_CLKSRC(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_CLKSRC_MASK) >> WDOG_STCTRLH_CLKSRC_SHIFT)
+#define WDOG_BRD_STCTRLH_CLKSRC(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_CLKSRC_SHIFT))
+
+/*! @brief Set the CLKSRC field to a new value. */
+#define WDOG_WR_STCTRLH_CLKSRC(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_CLKSRC_MASK, WDOG_STCTRLH_CLKSRC(value)))
+#define WDOG_BWR_STCTRLH_CLKSRC(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_CLKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
+ *
+ * Used to enable the debug breadcrumbs feature. A change in this bit is updated
+ * immediately, as opposed to updating after WCT.
+ *
+ * Values:
+ * - 0b0 - WDOG time-out generates reset only.
+ * - 0b1 - WDOG time-out initially generates an interrupt. After WCT, it
+ *     generates a reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. */
+#define WDOG_RD_STCTRLH_IRQRSTEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_IRQRSTEN_MASK) >> WDOG_STCTRLH_IRQRSTEN_SHIFT)
+#define WDOG_BRD_STCTRLH_IRQRSTEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_IRQRSTEN_SHIFT))
+
+/*! @brief Set the IRQRSTEN field to a new value. */
+#define WDOG_WR_STCTRLH_IRQRSTEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_IRQRSTEN_MASK, WDOG_STCTRLH_IRQRSTEN(value)))
+#define WDOG_BWR_STCTRLH_IRQRSTEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_IRQRSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
+ *
+ * Enables Windowing mode.
+ *
+ * Values:
+ * - 0b0 - Windowing mode is disabled.
+ * - 0b1 - Windowing mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WINEN field. */
+#define WDOG_RD_STCTRLH_WINEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WINEN_MASK) >> WDOG_STCTRLH_WINEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WINEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WINEN_SHIFT))
+
+/*! @brief Set the WINEN field to a new value. */
+#define WDOG_WR_STCTRLH_WINEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WINEN_MASK, WDOG_STCTRLH_WINEN(value)))
+#define WDOG_BWR_STCTRLH_WINEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WINEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
+ *
+ * Enables updates to watchdog write-once registers, after the reset-triggered
+ * initial configuration window (WCT) closes, through unlock sequence.
+ *
+ * Values:
+ * - 0b0 - No further updates allowed to WDOG write-once registers.
+ * - 0b1 - WDOG write-once registers can be unlocked for updating.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. */
+#define WDOG_RD_STCTRLH_ALLOWUPDATE(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_ALLOWUPDATE_MASK) >> WDOG_STCTRLH_ALLOWUPDATE_SHIFT)
+#define WDOG_BRD_STCTRLH_ALLOWUPDATE(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_ALLOWUPDATE_SHIFT))
+
+/*! @brief Set the ALLOWUPDATE field to a new value. */
+#define WDOG_WR_STCTRLH_ALLOWUPDATE(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_ALLOWUPDATE_MASK, WDOG_STCTRLH_ALLOWUPDATE(value)))
+#define WDOG_BWR_STCTRLH_ALLOWUPDATE(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_ALLOWUPDATE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
+ *
+ * Enables or disables WDOG in Debug mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Debug mode.
+ * - 0b1 - WDOG is enabled in CPU Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_DBGEN field. */
+#define WDOG_RD_STCTRLH_DBGEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_DBGEN_MASK) >> WDOG_STCTRLH_DBGEN_SHIFT)
+#define WDOG_BRD_STCTRLH_DBGEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DBGEN_SHIFT))
+
+/*! @brief Set the DBGEN field to a new value. */
+#define WDOG_WR_STCTRLH_DBGEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_DBGEN_MASK, WDOG_STCTRLH_DBGEN(value)))
+#define WDOG_BWR_STCTRLH_DBGEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DBGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
+ *
+ * Enables or disables WDOG in Stop mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Stop mode.
+ * - 0b1 - WDOG is enabled in CPU Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_STOPEN field. */
+#define WDOG_RD_STCTRLH_STOPEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_STOPEN_MASK) >> WDOG_STCTRLH_STOPEN_SHIFT)
+#define WDOG_BRD_STCTRLH_STOPEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_STOPEN_SHIFT))
+
+/*! @brief Set the STOPEN field to a new value. */
+#define WDOG_WR_STCTRLH_STOPEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_STOPEN_MASK, WDOG_STCTRLH_STOPEN(value)))
+#define WDOG_BWR_STCTRLH_STOPEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_STOPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
+ *
+ * Enables or disables WDOG in Wait mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Wait mode.
+ * - 0b1 - WDOG is enabled in CPU Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WAITEN field. */
+#define WDOG_RD_STCTRLH_WAITEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WAITEN_MASK) >> WDOG_STCTRLH_WAITEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WAITEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WAITEN_SHIFT))
+
+/*! @brief Set the WAITEN field to a new value. */
+#define WDOG_WR_STCTRLH_WAITEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WAITEN_MASK, WDOG_STCTRLH_WAITEN(value)))
+#define WDOG_BWR_STCTRLH_WAITEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WAITEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
+ *
+ * Puts the watchdog in the functional test mode. In this mode, the watchdog
+ * timer and the associated compare and reset generation logic is tested for correct
+ * operation. The clock for the timer is switched from the main watchdog clock
+ * to the fast clock input for watchdog functional test. The TESTSEL bit selects
+ * the test to be run.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. */
+#define WDOG_RD_STCTRLH_TESTWDOG(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_TESTWDOG_MASK) >> WDOG_STCTRLH_TESTWDOG_SHIFT)
+#define WDOG_BRD_STCTRLH_TESTWDOG(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTWDOG_SHIFT))
+
+/*! @brief Set the TESTWDOG field to a new value. */
+#define WDOG_WR_STCTRLH_TESTWDOG(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_TESTWDOG_MASK, WDOG_STCTRLH_TESTWDOG(value)))
+#define WDOG_BWR_STCTRLH_TESTWDOG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTWDOG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
+ *
+ * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
+ * timer.
+ *
+ * Values:
+ * - 0b0 - Quick test. The timer runs in normal operation. You can load a small
+ *     time-out value to do a quick test.
+ * - 0b1 - Byte test. Puts the timer in the byte test mode where individual
+ *     bytes of the timer are enabled for operation and are compared for time-out
+ *     against the corresponding byte of the programmed time-out value. Select the
+ *     byte through BYTESEL[1:0] for testing.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. */
+#define WDOG_RD_STCTRLH_TESTSEL(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_TESTSEL_MASK) >> WDOG_STCTRLH_TESTSEL_SHIFT)
+#define WDOG_BRD_STCTRLH_TESTSEL(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTSEL_SHIFT))
+
+/*! @brief Set the TESTSEL field to a new value. */
+#define WDOG_WR_STCTRLH_TESTSEL(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_TESTSEL_MASK, WDOG_STCTRLH_TESTSEL(value)))
+#define WDOG_BWR_STCTRLH_TESTSEL(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
+ *
+ * This 2-bit field selects the byte to be tested when the watchdog is in the
+ * byte test mode.
+ *
+ * Values:
+ * - 0b00 - Byte 0 selected
+ * - 0b01 - Byte 1 selected
+ * - 0b10 - Byte 2 selected
+ * - 0b11 - Byte 3 selected
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. */
+#define WDOG_RD_STCTRLH_BYTESEL(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_BYTESEL_MASK) >> WDOG_STCTRLH_BYTESEL_SHIFT)
+#define WDOG_BRD_STCTRLH_BYTESEL(base) (WDOG_RD_STCTRLH_BYTESEL(base))
+
+/*! @brief Set the BYTESEL field to a new value. */
+#define WDOG_WR_STCTRLH_BYTESEL(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_BYTESEL_MASK, WDOG_STCTRLH_BYTESEL(value)))
+#define WDOG_BWR_STCTRLH_BYTESEL(base, value) (WDOG_WR_STCTRLH_BYTESEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
+ *
+ * Allows the WDOG's functional test mode to be disabled permanently. After it
+ * is set, it can only be cleared by a reset. It cannot be unlocked for editing
+ * after it is set.
+ *
+ * Values:
+ * - 0b0 - WDOG functional test mode is not disabled.
+ * - 0b1 - WDOG functional test mode is disabled permanently until reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. */
+#define WDOG_RD_STCTRLH_DISTESTWDOG(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_DISTESTWDOG_MASK) >> WDOG_STCTRLH_DISTESTWDOG_SHIFT)
+#define WDOG_BRD_STCTRLH_DISTESTWDOG(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DISTESTWDOG_SHIFT))
+
+/*! @brief Set the DISTESTWDOG field to a new value. */
+#define WDOG_WR_STCTRLH_DISTESTWDOG(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_DISTESTWDOG_MASK, WDOG_STCTRLH_DISTESTWDOG(value)))
+#define WDOG_BWR_STCTRLH_DISTESTWDOG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DISTESTWDOG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_STCTRLL - Watchdog Status and Control Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
+ *
+ * Reset value: 0x0001U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLL register
+ */
+/*@{*/
+#define WDOG_RD_STCTRLL(base)    (WDOG_STCTRLL_REG(base))
+#define WDOG_WR_STCTRLL(base, value) (WDOG_STCTRLL_REG(base) = (value))
+#define WDOG_RMW_STCTRLL(base, mask, value) (WDOG_WR_STCTRLL(base, (WDOG_RD_STCTRLL(base) & ~(mask)) | (value)))
+#define WDOG_SET_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) |  (value)))
+#define WDOG_CLR_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) & ~(value)))
+#define WDOG_TOG_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_STCTRLL bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
+ *
+ * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
+ * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
+ * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
+ * bit. It also gets cleared on a system reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLL_INTFLG field. */
+#define WDOG_RD_STCTRLL_INTFLG(base) ((WDOG_STCTRLL_REG(base) & WDOG_STCTRLL_INTFLG_MASK) >> WDOG_STCTRLL_INTFLG_SHIFT)
+#define WDOG_BRD_STCTRLL_INTFLG(base) (BITBAND_ACCESS16(&WDOG_STCTRLL_REG(base), WDOG_STCTRLL_INTFLG_SHIFT))
+
+/*! @brief Set the INTFLG field to a new value. */
+#define WDOG_WR_STCTRLL_INTFLG(base, value) (WDOG_RMW_STCTRLL(base, WDOG_STCTRLL_INTFLG_MASK, WDOG_STCTRLL_INTFLG(value)))
+#define WDOG_BWR_STCTRLL_INTFLG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLL_REG(base), WDOG_STCTRLL_INTFLG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TOVALH - Watchdog Time-out Value Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
+ *
+ * Reset value: 0x004CU
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TOVALH register
+ */
+/*@{*/
+#define WDOG_RD_TOVALH(base)     (WDOG_TOVALH_REG(base))
+#define WDOG_WR_TOVALH(base, value) (WDOG_TOVALH_REG(base) = (value))
+#define WDOG_RMW_TOVALH(base, mask, value) (WDOG_WR_TOVALH(base, (WDOG_RD_TOVALH(base) & ~(mask)) | (value)))
+#define WDOG_SET_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) |  (value)))
+#define WDOG_CLR_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) & ~(value)))
+#define WDOG_TOG_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TOVALL - Watchdog Time-out Value Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
+ *
+ * Reset value: 0x4B4CU
+ *
+ * The time-out value of the watchdog must be set to a minimum of four watchdog
+ * clock cycles. This is to take into account the delay in new settings taking
+ * effect in the watchdog clock domain.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TOVALL register
+ */
+/*@{*/
+#define WDOG_RD_TOVALL(base)     (WDOG_TOVALL_REG(base))
+#define WDOG_WR_TOVALL(base, value) (WDOG_TOVALL_REG(base) = (value))
+#define WDOG_RMW_TOVALL(base, mask, value) (WDOG_WR_TOVALL(base, (WDOG_RD_TOVALL(base) & ~(mask)) | (value)))
+#define WDOG_SET_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) |  (value)))
+#define WDOG_CLR_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) & ~(value)))
+#define WDOG_TOG_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_WINH - Watchdog Window Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_WINH - Watchdog Window Register High (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_WINH register
+ */
+/*@{*/
+#define WDOG_RD_WINH(base)       (WDOG_WINH_REG(base))
+#define WDOG_WR_WINH(base, value) (WDOG_WINH_REG(base) = (value))
+#define WDOG_RMW_WINH(base, mask, value) (WDOG_WR_WINH(base, (WDOG_RD_WINH(base) & ~(mask)) | (value)))
+#define WDOG_SET_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) |  (value)))
+#define WDOG_CLR_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) & ~(value)))
+#define WDOG_TOG_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_WINL - Watchdog Window Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_WINL - Watchdog Window Register Low (RW)
+ *
+ * Reset value: 0x0010U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_WINL register
+ */
+/*@{*/
+#define WDOG_RD_WINL(base)       (WDOG_WINL_REG(base))
+#define WDOG_WR_WINL(base, value) (WDOG_WINL_REG(base) = (value))
+#define WDOG_RMW_WINL(base, mask, value) (WDOG_WR_WINL(base, (WDOG_RD_WINL(base) & ~(mask)) | (value)))
+#define WDOG_SET_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) |  (value)))
+#define WDOG_CLR_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) & ~(value)))
+#define WDOG_TOG_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_REFRESH - Watchdog Refresh register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_REFRESH - Watchdog Refresh register (RW)
+ *
+ * Reset value: 0xB480U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_REFRESH register
+ */
+/*@{*/
+#define WDOG_RD_REFRESH(base)    (WDOG_REFRESH_REG(base))
+#define WDOG_WR_REFRESH(base, value) (WDOG_REFRESH_REG(base) = (value))
+#define WDOG_RMW_REFRESH(base, mask, value) (WDOG_WR_REFRESH(base, (WDOG_RD_REFRESH(base) & ~(mask)) | (value)))
+#define WDOG_SET_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) |  (value)))
+#define WDOG_CLR_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) & ~(value)))
+#define WDOG_TOG_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_UNLOCK - Watchdog Unlock register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_UNLOCK - Watchdog Unlock register (RW)
+ *
+ * Reset value: 0xD928U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_UNLOCK register
+ */
+/*@{*/
+#define WDOG_RD_UNLOCK(base)     (WDOG_UNLOCK_REG(base))
+#define WDOG_WR_UNLOCK(base, value) (WDOG_UNLOCK_REG(base) = (value))
+#define WDOG_RMW_UNLOCK(base, mask, value) (WDOG_WR_UNLOCK(base, (WDOG_RD_UNLOCK(base) & ~(mask)) | (value)))
+#define WDOG_SET_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) |  (value)))
+#define WDOG_CLR_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) & ~(value)))
+#define WDOG_TOG_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TMROUTH - Watchdog Timer Output Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTH register
+ */
+/*@{*/
+#define WDOG_RD_TMROUTH(base)    (WDOG_TMROUTH_REG(base))
+#define WDOG_WR_TMROUTH(base, value) (WDOG_TMROUTH_REG(base) = (value))
+#define WDOG_RMW_TMROUTH(base, mask, value) (WDOG_WR_TMROUTH(base, (WDOG_RD_TMROUTH(base) & ~(mask)) | (value)))
+#define WDOG_SET_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) |  (value)))
+#define WDOG_CLR_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) & ~(value)))
+#define WDOG_TOG_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TMROUTL - Watchdog Timer Output Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
+ * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
+ * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
+ * the watchdog timer.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTL register
+ */
+/*@{*/
+#define WDOG_RD_TMROUTL(base)    (WDOG_TMROUTL_REG(base))
+#define WDOG_WR_TMROUTL(base, value) (WDOG_TMROUTL_REG(base) = (value))
+#define WDOG_RMW_TMROUTL(base, mask, value) (WDOG_WR_TMROUTL(base, (WDOG_RD_TMROUTL(base) & ~(mask)) | (value)))
+#define WDOG_SET_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) |  (value)))
+#define WDOG_CLR_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) & ~(value)))
+#define WDOG_TOG_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_RSTCNT - Watchdog Reset Count register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_RSTCNT - Watchdog Reset Count register (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_RSTCNT register
+ */
+/*@{*/
+#define WDOG_RD_RSTCNT(base)     (WDOG_RSTCNT_REG(base))
+#define WDOG_WR_RSTCNT(base, value) (WDOG_RSTCNT_REG(base) = (value))
+#define WDOG_RMW_RSTCNT(base, mask, value) (WDOG_WR_RSTCNT(base, (WDOG_RD_RSTCNT(base) & ~(mask)) | (value)))
+#define WDOG_SET_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) |  (value)))
+#define WDOG_CLR_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) & ~(value)))
+#define WDOG_TOG_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_PRESC - Watchdog Prescaler register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_PRESC - Watchdog Prescaler register (RW)
+ *
+ * Reset value: 0x0400U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_PRESC register
+ */
+/*@{*/
+#define WDOG_RD_PRESC(base)      (WDOG_PRESC_REG(base))
+#define WDOG_WR_PRESC(base, value) (WDOG_PRESC_REG(base) = (value))
+#define WDOG_RMW_PRESC(base, mask, value) (WDOG_WR_PRESC(base, (WDOG_RD_PRESC(base) & ~(mask)) | (value)))
+#define WDOG_SET_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) |  (value)))
+#define WDOG_CLR_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) & ~(value)))
+#define WDOG_TOG_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_PRESC bitfields
+ */
+
+/*!
+ * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
+ *
+ * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
+ * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
+ * 1) to provide the prescaled WDOG_CLK.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_PRESC_PRESCVAL field. */
+#define WDOG_RD_PRESC_PRESCVAL(base) ((WDOG_PRESC_REG(base) & WDOG_PRESC_PRESCVAL_MASK) >> WDOG_PRESC_PRESCVAL_SHIFT)
+#define WDOG_BRD_PRESC_PRESCVAL(base) (WDOG_RD_PRESC_PRESCVAL(base))
+
+/*! @brief Set the PRESCVAL field to a new value. */
+#define WDOG_WR_PRESC_PRESCVAL(base, value) (WDOG_RMW_PRESC(base, WDOG_PRESC_PRESCVAL_MASK, WDOG_PRESC_PRESCVAL(value)))
+#define WDOG_BWR_PRESC_PRESCVAL(base, value) (WDOG_WR_PRESC_PRESCVAL(base, value))
+/*@}*/
+
+/* Instance numbers for core modules */
+#define JTAG_IDX (0) /*!< Instance number for JTAG. */
+#define TPIU_IDX (0) /*!< Instance number for TPIU. */
+#define SCB_IDX (0) /*!< Instance number for SCB. */
+#define CoreDebug_IDX (0) /*!< Instance number for CoreDebug. */
+
+#if defined(__IAR_SYSTEMS_ICC__)
+  /* Restore checking of "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)" */
+  #pragma diag_default=pm008
+#endif
+
+#endif /* __MK64F12_EXTENSION_H__ */
+/* EOF */
diff --git a/Workspace/ADC/SDK/platform/devices/MK64F12/include/MK64F12_features.h b/Workspace/ADC/SDK/platform/devices/MK64F12/include/MK64F12_features.h
new file mode 100644
index 0000000..9c826df
--- /dev/null
+++ b/Workspace/ADC/SDK/platform/devices/MK64F12/include/MK64F12_features.h
@@ -0,0 +1,1901 @@
+/*
+** ###################################################################
+**     Version:             rev. 2.14, 2015-06-08
+**     Build:               b150715
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-01-30)
+**         Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.6 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.7 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.8 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.9 (2015-01-21)
+**         Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
+**     - rev. 2.10 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**     - rev. 2.11 (2015-05-19)
+**         FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
+**         Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
+**         Added features for PDB and PORT.
+**     - rev. 2.12 (2015-05-25)
+**         Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
+**     - rev. 2.13 (2015-05-27)
+**         Several USB features added.
+**     - rev. 2.14 (2015-06-08)
+**         FTM features BUS_CLOCK and FAST_CLOCK removed.
+**
+** ###################################################################
+*/
+
+#if !defined(__FSL_MK64F12_FEATURES_H__)
+#define __FSL_MK64F12_FEATURES_H__
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* FLEXCAN module features */
+
+/* @brief Message buffer size */
+#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
+/* @brief Has doze mode support (register bit field MCR[DOZE]). */
+#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
+/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
+#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
+/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
+/* @brief Has extended bit timing register (register CBT). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
+/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
+#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
+/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
+#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
+/* @brief Number of interrupt vectors. */
+#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* SOC module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief ACMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_ACMP_COUNT (0)
+    /* @brief ADC16 availability on the SoC. */
+    #define FSL_FEATURE_SOC_ADC16_COUNT (2)
+    /* @brief AFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_AFE_COUNT (0)
+    /* @brief AIPS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AIPS_COUNT (2)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (0)
+    /* @brief AXBS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AXBS_COUNT (1)
+    /* @brief CADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CADC_COUNT (0)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief MMCAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
+    /* @brief CMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMP_COUNT (3)
+    /* @brief CMT availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMT_COUNT (1)
+    /* @brief CNC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CNC_COUNT (0)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief DAC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DAC_COUNT (2)
+    /* @brief DCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DCDC_COUNT (0)
+    /* @brief DDR availability on the SoC. */
+    #define FSL_FEATURE_SOC_DDR_COUNT (0)
+    /* @brief DMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMA_COUNT (0)
+    /* @brief DMAMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+    /* @brief DRY availability on the SoC. */
+    #define FSL_FEATURE_SOC_DRY_COUNT (0)
+    /* @brief DSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_DSPI_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EMVSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+    /* @brief ENC availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENC_COUNT (0)
+    /* @brief ENET availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENET_COUNT (1)
+    /* @brief EWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EWM_COUNT (1)
+    /* @brief FB availability on the SoC. */
+    #define FSL_FEATURE_SOC_FB_COUNT (1)
+    /* @brief FGPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+    /* @brief FLEXIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FSKDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+    /* @brief FTFA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFA_COUNT (0)
+    /* @brief FTFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFE_COUNT (1)
+    /* @brief FTFL availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFL_COUNT (0)
+    /* @brief FTM availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTM_COUNT (4)
+    /* @brief FTMRA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+    /* @brief FTMRE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+    /* @brief FTMRH availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief HSADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_HSADC_COUNT (0)
+    /* @brief I2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2C_COUNT (3)
+    /* @brief I2S availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2S_COUNT (1)
+    /* @brief ICS availability on the SoC. */
+    #define FSL_FEATURE_SOC_ICS_COUNT (0)
+    /* @brief IRQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_IRQ_COUNT (0)
+    /* @brief KBI availability on the SoC. */
+    #define FSL_FEATURE_SOC_KBI_COUNT (0)
+    /* @brief SLCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_SLCD_COUNT (0)
+    /* @brief LCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LCDC_COUNT (0)
+    /* @brief LDO availability on the SoC. */
+    #define FSL_FEATURE_SOC_LDO_COUNT (0)
+    /* @brief LLWU availability on the SoC. */
+    #define FSL_FEATURE_SOC_LLWU_COUNT (1)
+    /* @brief LMEM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LMEM_COUNT (0)
+    /* @brief LPSCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPTPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (0)
+    /* @brief LTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LTC_COUNT (0)
+    /* @brief MC availability on the SoC. */
+    #define FSL_FEATURE_SOC_MC_COUNT (0)
+    /* @brief MCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCG_COUNT (1)
+    /* @brief MCGLITE availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+    /* @brief MCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCM_COUNT (1)
+    /* @brief MMAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMAU_COUNT (0)
+    /* @brief MMDVSQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+    /* @brief MPU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MPU_COUNT (1)
+    /* @brief MSCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+    /* @brief MTB availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTB_COUNT (0)
+    /* @brief MTBDWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
+    /* @brief NFC availability on the SoC. */
+    #define FSL_FEATURE_SOC_NFC_COUNT (0)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+    /* @brief OSC availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSC_COUNT (1)
+    /* @brief OTFAD availability on the SoC. */
+    #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+    /* @brief PDB availability on the SoC. */
+    #define FSL_FEATURE_SOC_PDB_COUNT (1)
+    /* @brief PGA availability on the SoC. */
+    #define FSL_FEATURE_SOC_PGA_COUNT (0)
+    /* @brief PIT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PIT_COUNT (1)
+    /* @brief PMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_PMC_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (0)
+    /* @brief PWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWT_COUNT (0)
+    /* @brief QuadSPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+    /* @brief RCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RCM_COUNT (1)
+    /* @brief RFSYS availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+    /* @brief RFVBAT availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+    /* @brief RNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNG_COUNT (1)
+    /* @brief RNGB availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNGB_COUNT (0)
+    /* @brief ROM availability on the SoC. */
+    #define FSL_FEATURE_SOC_ROM_COUNT (0)
+    /* @brief RSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RSIM_COUNT (0)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCI_COUNT (0)
+    /* @brief SDHC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDHC_COUNT (1)
+    /* @brief SDRAM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+    /* @brief SIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SIM_COUNT (1)
+    /* @brief SMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMC_COUNT (1)
+    /* @brief SPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPI_COUNT (0)
+    /* @brief TMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_TMR_COUNT (0)
+    /* @brief TPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_TPM_COUNT (0)
+    /* @brief TRIAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+    /* @brief TRNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRNG_COUNT (0)
+    /* @brief TSI availability on the SoC. */
+    #define FSL_FEATURE_SOC_TSI_COUNT (0)
+    /* @brief UART availability on the SoC. */
+    #define FSL_FEATURE_SOC_UART_COUNT (6)
+    /* @brief USB availability on the SoC. */
+    #define FSL_FEATURE_SOC_USB_COUNT (1)
+    /* @brief USBDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+    /* @brief USBHSDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+    /* @brief USBPHY availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+    /* @brief VREF availability on the SoC. */
+    #define FSL_FEATURE_SOC_VREF_COUNT (1)
+    /* @brief WDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_WDOG_COUNT (1)
+    /* @brief XBAR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XBAR_COUNT (0)
+    /* @brief XCVR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XCVR_COUNT (0)
+    /* @brief ZLL availability on the SoC. */
+    #define FSL_FEATURE_SOC_ZLL_COUNT (0)
+#elif defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12)
+    /* @brief ACMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_ACMP_COUNT (0)
+    /* @brief ADC16 availability on the SoC. */
+    #define FSL_FEATURE_SOC_ADC16_COUNT (2)
+    /* @brief AFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_AFE_COUNT (0)
+    /* @brief AIPS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AIPS_COUNT (2)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (0)
+    /* @brief AXBS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AXBS_COUNT (1)
+    /* @brief CADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CADC_COUNT (0)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief MMCAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
+    /* @brief CMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMP_COUNT (3)
+    /* @brief CMT availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMT_COUNT (1)
+    /* @brief CNC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CNC_COUNT (0)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief DAC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DAC_COUNT (1)
+    /* @brief DCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DCDC_COUNT (0)
+    /* @brief DDR availability on the SoC. */
+    #define FSL_FEATURE_SOC_DDR_COUNT (0)
+    /* @brief DMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMA_COUNT (0)
+    /* @brief DMAMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+    /* @brief DRY availability on the SoC. */
+    #define FSL_FEATURE_SOC_DRY_COUNT (0)
+    /* @brief DSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_DSPI_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EMVSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+    /* @brief ENC availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENC_COUNT (0)
+    /* @brief ENET availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENET_COUNT (1)
+    /* @brief EWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EWM_COUNT (1)
+    /* @brief FB availability on the SoC. */
+    #define FSL_FEATURE_SOC_FB_COUNT (1)
+    /* @brief FGPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+    /* @brief FLEXIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FSKDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+    /* @brief FTFA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFA_COUNT (0)
+    /* @brief FTFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFE_COUNT (1)
+    /* @brief FTFL availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFL_COUNT (0)
+    /* @brief FTM availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTM_COUNT (4)
+    /* @brief FTMRA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+    /* @brief FTMRE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+    /* @brief FTMRH availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief HSADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_HSADC_COUNT (0)
+    /* @brief I2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2C_COUNT (3)
+    /* @brief I2S availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2S_COUNT (1)
+    /* @brief ICS availability on the SoC. */
+    #define FSL_FEATURE_SOC_ICS_COUNT (0)
+    /* @brief IRQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_IRQ_COUNT (0)
+    /* @brief KBI availability on the SoC. */
+    #define FSL_FEATURE_SOC_KBI_COUNT (0)
+    /* @brief SLCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_SLCD_COUNT (0)
+    /* @brief LCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LCDC_COUNT (0)
+    /* @brief LDO availability on the SoC. */
+    #define FSL_FEATURE_SOC_LDO_COUNT (0)
+    /* @brief LLWU availability on the SoC. */
+    #define FSL_FEATURE_SOC_LLWU_COUNT (1)
+    /* @brief LMEM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LMEM_COUNT (0)
+    /* @brief LPSCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPTPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (0)
+    /* @brief LTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LTC_COUNT (0)
+    /* @brief MC availability on the SoC. */
+    #define FSL_FEATURE_SOC_MC_COUNT (0)
+    /* @brief MCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCG_COUNT (1)
+    /* @brief MCGLITE availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+    /* @brief MCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCM_COUNT (1)
+    /* @brief MMAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMAU_COUNT (0)
+    /* @brief MMDVSQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+    /* @brief MPU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MPU_COUNT (1)
+    /* @brief MSCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+    /* @brief MTB availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTB_COUNT (0)
+    /* @brief MTBDWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
+    /* @brief NFC availability on the SoC. */
+    #define FSL_FEATURE_SOC_NFC_COUNT (0)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+    /* @brief OSC availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSC_COUNT (1)
+    /* @brief OTFAD availability on the SoC. */
+    #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+    /* @brief PDB availability on the SoC. */
+    #define FSL_FEATURE_SOC_PDB_COUNT (1)
+    /* @brief PGA availability on the SoC. */
+    #define FSL_FEATURE_SOC_PGA_COUNT (0)
+    /* @brief PIT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PIT_COUNT (1)
+    /* @brief PMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_PMC_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (0)
+    /* @brief PWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWT_COUNT (0)
+    /* @brief QuadSPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+    /* @brief RCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RCM_COUNT (1)
+    /* @brief RFSYS availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+    /* @brief RFVBAT availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+    /* @brief RNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNG_COUNT (1)
+    /* @brief RNGB availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNGB_COUNT (0)
+    /* @brief ROM availability on the SoC. */
+    #define FSL_FEATURE_SOC_ROM_COUNT (0)
+    /* @brief RSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RSIM_COUNT (0)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCI_COUNT (0)
+    /* @brief SDHC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDHC_COUNT (1)
+    /* @brief SDRAM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+    /* @brief SIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SIM_COUNT (1)
+    /* @brief SMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMC_COUNT (1)
+    /* @brief SPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPI_COUNT (0)
+    /* @brief TMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_TMR_COUNT (0)
+    /* @brief TPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_TPM_COUNT (0)
+    /* @brief TRIAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+    /* @brief TRNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRNG_COUNT (0)
+    /* @brief TSI availability on the SoC. */
+    #define FSL_FEATURE_SOC_TSI_COUNT (0)
+    /* @brief UART availability on the SoC. */
+    #define FSL_FEATURE_SOC_UART_COUNT (6)
+    /* @brief USB availability on the SoC. */
+    #define FSL_FEATURE_SOC_USB_COUNT (1)
+    /* @brief USBDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+    /* @brief USBHSDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+    /* @brief USBPHY availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+    /* @brief VREF availability on the SoC. */
+    #define FSL_FEATURE_SOC_VREF_COUNT (1)
+    /* @brief WDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_WDOG_COUNT (1)
+    /* @brief XBAR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XBAR_COUNT (0)
+    /* @brief XCVR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XCVR_COUNT (0)
+    /* @brief ZLL availability on the SoC. */
+    #define FSL_FEATURE_SOC_ZLL_COUNT (0)
+#endif
+
+/* CRC module features */
+
+/* @brief Has data register with name CRC */
+#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (DMA_INSTANCE_COUNT * 16)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (DMAMUX_INSTANCE_COUNT * 16)
+/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+
+/* ENET module features */
+
+/* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */
+#define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0)
+/* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */
+#define FSL_FEATURE_ENET_SUPPORT_PTP (1)
+/* @brief Number of associated interrupt vectors. */
+#define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
+/* @brief Errata 2597: No support for IEEE 1588 timestamp timer overflow interrupt. */
+#define FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT_ERRATA_2579 (0)
+/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
+#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
+
+/* EWM module features */
+
+/* @brief Has clock prescaler (register CLKPRESCALER). */
+#define FSL_FEATURE_EWM_HAS_PRESCALER  (0)
+
+/* FLEXBUS module features */
+
+/* No feature definitions */
+
+/* FLASH module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (0)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (1)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (131072)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00020000)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0001C000)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00018000)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00010000)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00000000)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00020000)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+#elif defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (0)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (1)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+#endif
+
+/* FTM module features */
+
+/* @brief Number of channels. */
+#define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
+#define FSL_FEATURE_FTM_CHANNEL_COUNTx { 8, 2, 2, 8 }
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
+
+/* SAI module features */
+
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+#define FSL_FEATURE_SAI_FIFO_COUNT (8)
+/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
+#define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
+#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
+/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
+#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
+/* @brief Ihe interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
+
+/* LLWU module features */
+
+/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+/* @brief Has pins 8-15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+/* @brief Maximum number of internal modules connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+/* @brief Number of digital filters. */
+#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+/* @brief Has MF5 register. */
+#define FSL_FEATURE_LLWU_HAS_MF (0)
+/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1)
+/* @brief Has external pin 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
+/* @brief Has external pin 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
+/* @brief Has external pin 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
+/* @brief Has external pin 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
+/* @brief Has external pin 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
+/* @brief Has external pin 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
+/* @brief Has external pin 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
+/* @brief Has external pin 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
+/* @brief Has external pin 8 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
+/* @brief Has external pin 9 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
+/* @brief Has external pin 10 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
+/* @brief Has external pin 11 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
+/* @brief Has external pin 12 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
+/* @brief Has external pin 13 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
+/* @brief Has external pin 14 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
+/* @brief Has external pin 15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
+/* @brief Has external pin 16 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+/* @brief Has external pin 17 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+/* @brief Has external pin 18 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+/* @brief Has external pin 19 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+/* @brief Has external pin 20 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+/* @brief Has external pin 21 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+/* @brief Has external pin 22 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+/* @brief Has external pin 23 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+/* @brief Has external pin 24 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+/* @brief Has external pin 25 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+/* @brief Has external pin 26 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+/* @brief Has external pin 27 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+/* @brief Has external pin 28 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+/* @brief Has external pin 29 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+/* @brief Has external pin 30 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+/* @brief Has external pin 31 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+/* @brief Has internal module 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+/* @brief Has internal module 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+/* @brief Has internal module 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+/* @brief Has internal module 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+/* @brief Has internal module 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
+/* @brief Has internal module 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+/* @brief Has internal module 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+/* @brief Has internal module 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+
+/* MCG module features */
+
+/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
+/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
+/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
+/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
+/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
+/* @brief The PLL clock is divided by 2 before VCO divider. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
+/* @brief FRDIV supports 1280. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
+/* @brief FRDIV supports 1536. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
+#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
+/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
+#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
+/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_PLL1 (0)
+/* @brief Has 48MHz internal oscillator. */
+#define FSL_FEATURE_MCG_HAS_IRC_48M (1)
+/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_OSC1 (0)
+/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
+#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
+/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
+#define FSL_FEATURE_MCG_HAS_LOLRE (1)
+/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
+#define FSL_FEATURE_MCG_USE_OSCSEL (1)
+/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
+#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
+/* @brief TBD */
+#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL (1)
+/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
+/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
+/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
+#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
+/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
+#define FSL_FEATURE_MCG_HAS_FLL (1)
+/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
+/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
+#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
+/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
+/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
+/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
+#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
+/* @brief Has external clock monitor (register bit C6[CME]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
+/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
+#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
+/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
+#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
+/* @brief Has PEI mode or PBI mode. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
+/* @brief Reset clock mode is BLPI. */
+#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
+
+/* MPU module features */
+
+/* @brief Specifies number of descriptors available. */
+#define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12)
+/* @brief Has process identifier support. */
+#define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1)
+/* @brief Has master 0. */
+#define FSL_FEATURE_MPU_HAS_MASTER0 (1)
+/* @brief Has master 1. */
+#define FSL_FEATURE_MPU_HAS_MASTER1 (1)
+/* @brief Has master 2. */
+#define FSL_FEATURE_MPU_HAS_MASTER2 (1)
+/* @brief Has master 3. */
+#define FSL_FEATURE_MPU_HAS_MASTER3 (1)
+/* @brief Has master 4. */
+#define FSL_FEATURE_MPU_HAS_MASTER4 (1)
+/* @brief Has master 5. */
+#define FSL_FEATURE_MPU_HAS_MASTER5 (1)
+/* @brief Has master 6. */
+#define FSL_FEATURE_MPU_HAS_MASTER6 (0)
+/* @brief Has master 7. */
+#define FSL_FEATURE_MPU_HAS_MASTER7 (0)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
+
+/* OSC module features */
+
+/* @brief Has OSC1 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC1 (0)
+/* @brief Has OSC0 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC0 (0)
+/* @brief Has OSC external oscillator (without index). */
+#define FSL_FEATURE_OSC_HAS_OSC (1)
+/* @brief Number of OSC external oscillators. */
+#define FSL_FEATURE_OSC_OSC_COUNT (1)
+/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
+#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
+
+/* PDB module features */
+
+/* @brief Define the count of supporting ADC pre-trigger for each channel. */
+#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2)
+/* @brief Has DAC support. */
+#define FSL_FEATURE_PDB_HAS_DAC (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (4)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (1)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (1)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (1)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (1)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (1)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (0)
+
+/* RTC module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \
+    defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12)
+    /* @brief Has wakeup pin (bit field CR[WPS]). */
+    #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+    /* @brief Has low power features (registers MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+    /* @brief Has read/write access control (registers WAR and RAR). */
+    #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+    /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_SECURITY (1)
+#elif defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief Has wakeup pin (bit field CR[WPS]). */
+    #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+    /* @brief Has low power features (registers MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+    /* @brief Has read/write access control (registers WAR and RAR). */
+    #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+    /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_SECURITY (0)
+#endif
+
+/* SDHC module features */
+
+/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
+#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1)
+/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
+#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0)
+/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
+#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (1)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
+
+/* DSPI module features */
+
+/* @brief Receive/transmit FIFO size in number of items. */
+#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
+#define FSL_FEATURE_DSPI_FIFO_SIZEx { 4, 1, 1 }
+/* @brief Maximum transfer data width in bits. */
+#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
+/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
+#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
+/* @brief Number of chip select pins. */
+#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
+/* @brief Has chip select strobe capability on the PCS5 pin. */
+#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
+/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+/* @brief Has 16-bit data transfer support. */
+#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (0) : \
+    ((x) == 2 ? (0) : (-1))))
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
+
+/* UART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_HAS_FIFO (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_UART_IS_SCI (0)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_FIFO_SIZE (8)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
+/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
+#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (1) : \
+    ((x) == 2 ? (1) : \
+    ((x) == 3 ? (1) : \
+    ((x) == 4 ? (0) : \
+    ((x) == 5 ? (0) : (-1)))))))
+
+/* USB module features */
+
+/* @brief HOST mode enabled */
+#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
+/* @brief OTG mode enabled */
+#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
+/* @brief Has KEEP_ALIVE_CTRL register */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
+/* @brief Has the Dynamic SOF threshold compare support */
+#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
+/* @brief Has the VBUS detect support */
+#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
+/* @brief Has the IRC48M module clock support */
+#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief Describes the set of SC[MODE_LV] bitfield values */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+
+/* WDOG module features */
+
+/* @brief Watchdog is available. */
+#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
+/* @brief Has Wait mode support. */
+#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
+
+#endif /* __FSL_MK64F12_FEATURES_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/Workspace/ADC/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h b/Workspace/ADC/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
new file mode 100644
index 0000000..0044bbf
--- /dev/null
+++ b/Workspace/ADC/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
@@ -0,0 +1,111 @@
+/*
+** ###################################################################
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Register bit field access macros.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+#ifndef _FSL_BITACCESS_H
+#define _FSL_BITACCESS_H  1
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/**
+ * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+#endif /* _FSL_BITACCESS_H */
+
+/******************************************************************************/
diff --git a/Workspace/ADC/SDK/platform/devices/fsl_device_registers.h b/Workspace/ADC/SDK/platform/devices/fsl_device_registers.h
new file mode 100644
index 0000000..abeb4ac
--- /dev/null
+++ b/Workspace/ADC/SDK/platform/devices/fsl_device_registers.h
@@ -0,0 +1,1083 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2014-05-15
+**     Build:               b141209
+**
+**     Abstract:
+**         Common include file for CMSIS register access layer headers.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-05-15)
+**         Customer release.
+**
+** ###################################################################
+*/
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \
+    defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10))
+
+    #define K02F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK02F12810/include/MK02F12810.h"
+    /* Extension register definitions */
+    #include "MK02F12810/include/MK02F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK02F12810/include/MK02F12810_features.h"
+
+#elif (defined(CPU_MK10DN512VLK10) || defined(CPU_MK10DN512VLL10) || defined(CPU_MK10DX128VLQ10) || \
+    defined(CPU_MK10DX256VLQ10) || defined(CPU_MK10DN512VLQ10) || defined(CPU_MK10DN512VMC10) || \
+    defined(CPU_MK10DX128VMD10) || defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10))
+
+    #define K10D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK10D10/include/MK10D10.h"
+    /* Extension register definitions */
+    #include "MK10D10/include/MK10D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK10D10/include/MK10D10_features.h"
+
+#elif (defined(CPU_MK11DX128AVLK5) || defined(CPU_MK11DX256AVLK5) || defined(CPU_MK11DN512AVLK5) || \
+    defined(CPU_MK11DX128AVMC5) || defined(CPU_MK11DX256AVMC5) || defined(CPU_MK11DN512AVMC5))
+
+    #define K11DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK11DA5/include/MK11DA5.h"
+    /* Extension register definitions */
+    #include "MK11DA5/include/MK11DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK11DA5/include/MK11DA5_features.h"
+
+#elif (defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DX256VLK10) || defined(CPU_MK20DN512VLL10) || \
+    defined(CPU_MK20DX256VLL10) || defined(CPU_MK20DX128VLQ10) || defined(CPU_MK20DX256VLQ10) || \
+    defined(CPU_MK20DN512VLQ10) || defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || \
+    defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || defined(CPU_MK20DN512VMD10))
+
+    #define K20D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D10/include/MK20D10.h"
+    /* Extension register definitions */
+    #include "MK20D10/include/MK20D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D10/include/MK20D10_features.h"
+
+#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \
+    defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
+    defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
+    defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
+    defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \
+    defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
+    defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \
+    defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
+    defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
+    defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5))
+
+    #define K20D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D5/include/MK20D5.h"
+    /* Extension register definitions */
+    #include "MK20D5/include/MK20D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D5/include/MK20D5_features.h"
+
+#elif (defined(CPU_MK21DX128AVLK5) || defined(CPU_MK21DX256AVLK5) || defined(CPU_MK21DN512AVLK5) || \
+    defined(CPU_MK21DX128AVMC5) || defined(CPU_MK21DX256AVMC5) || defined(CPU_MK21DN512AVMC5))
+
+    #define K21DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21DA5/include/MK21DA5.h"
+    /* Extension register definitions */
+    #include "MK21DA5/include/MK21DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21DA5/include/MK21DA5_features.h"
+
+#elif (defined(CPU_MK21FX512AVLQ12) || defined(CPU_MK21FN1M0AVLQ12) || defined(CPU_MK21FX512AVMC12) || \
+    defined(CPU_MK21FN1M0AVMC12) || defined(CPU_MK21FX512AVMD12) || defined(CPU_MK21FN1M0AVMD12))
+
+    #define K21FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21FA12/include/MK21FA12.h"
+    /* Extension register definitions */
+    #include "MK21FA12/include/MK21FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21FA12/include/MK21FA12_features.h"
+
+#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \
+    defined(CPU_MK22FN128VMP10))
+
+    #define K22F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F12810/include/MK22F12810.h"
+    /* Extension register definitions */
+    #include "MK22F12810/include/MK22F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F12810/include/MK22F12810_features.h"
+
+#elif (defined(CPU_MK22FX512AVLH12) || defined(CPU_MK22FN1M0AVLH12) || defined(CPU_MK22FX512AVLK12) || \
+    defined(CPU_MK22FN1M0AVLK12) || defined(CPU_MK22FX512AVLL12) || defined(CPU_MK22FN1M0AVLL12) || \
+    defined(CPU_MK22FX512AVLQ12) || defined(CPU_MK22FN1M0AVLQ12) || defined(CPU_MK22FX512AVMC12) || \
+    defined(CPU_MK22FN1M0AVMC12) || defined(CPU_MK22FX512AVMD12) || defined(CPU_MK22FN1M0AVMD12))
+
+    #define K22FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22FA12/include/MK22FA12.h"
+    /* Extension register definitions */
+    #include "MK22FA12/include/MK22FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22FA12/include/MK22FA12_features.h"
+
+#elif (defined(CPU_MK22FN256CAH12) || defined(CPU_MK22FN128CAH12) || defined(CPU_MK22FN256VDC12) || \
+    defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12))
+
+    #define K22F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F25612/include/MK22F25612.h"
+    /* Extension register definitions */
+    #include "MK22F25612/include/MK22F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F25612/include/MK22F25612_features.h"
+
+#elif (defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
+    defined(CPU_MK22FN512VLL12) || defined(CPU_MK22FN512VMP12))
+
+    #define K22F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F51212/include/MK22F51212.h"
+    /* Extension register definitions */
+    #include "MK22F51212/include/MK22F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F51212/include/MK22F51212_features.h"
+
+#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12))
+
+    #define K24F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F12/include/MK24F12.h"
+    /* Extension register definitions */
+    #include "MK24F12/include/MK24F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F12/include/MK24F12_features.h"
+
+#elif (defined(CPU_MK24FN256VDC12))
+
+    #define K24F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F25612/include/MK24F25612.h"
+    /* Extension register definitions */
+    #include "MK24F25612/include/MK24F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F25612/include/MK24F25612_features.h"
+
+#elif (defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VLQ18) || defined(CPU_MK26FN2M0VMD18) || \
+    defined(CPU_MK26FN2M0VMI18))
+
+    #define K26F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK26F18/include/MK26F18.h"
+    /* Extension register definitions */
+    #include "MK26F18/include/MK26F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK26F18/include/MK26F18_features.h"
+
+#elif (defined(CPU_MK30DN512VLK10) || defined(CPU_MK30DN512VLL10) || defined(CPU_MK30DX128VLQ10) || \
+    defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMC10) || \
+    defined(CPU_MK30DX128VMD10) || defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10))
+
+    #define K30D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK30D10/include/MK30D10.h"
+    /* Extension register definitions */
+    #include "MK30D10/include/MK30D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK30D10/include/MK30D10_features.h"
+
+#elif (defined(CPU_MK40DN512VLK10) || defined(CPU_MK40DN512VLL10) || defined(CPU_MK40DX128VLQ10) || \
+    defined(CPU_MK40DX256VLQ10) || defined(CPU_MK40DN512VLQ10) || defined(CPU_MK40DN512VMC10) || \
+    defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || defined(CPU_MK40DN512VMD10))
+
+    #define K40D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK40D10/include/MK40D10.h"
+    /* Extension register definitions */
+    #include "MK40D10/include/MK40D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK40D10/include/MK40D10_features.h"
+
+#elif (defined(CPU_MK50DX256CLL10) || defined(CPU_MK50DN512CLL10) || defined(CPU_MK50DN512CLQ10) || \
+    defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || defined(CPU_MK50DN512CMD10) || \
+    defined(CPU_MK50DX256CMD10) || defined(CPU_MK50DX256CLK10))
+
+    #define K50D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK50D10/include/MK50D10.h"
+    /* Extension register definitions */
+    #include "MK50D10/include/MK50D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK50D10/include/MK50D10_features.h"
+
+#elif (defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10) || defined(CPU_MK51DN256CLQ10) || \
+    defined(CPU_MK51DN512CLQ10) || defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || \
+    defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10) || defined(CPU_MK51DX256CLK10))
+
+    #define K51D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK51D10/include/MK51D10.h"
+    /* Extension register definitions */
+    #include "MK51D10/include/MK51D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK51D10/include/MK51D10_features.h"
+
+#elif (defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10))
+
+    #define K52D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK52D10/include/MK52D10.h"
+    /* Extension register definitions */
+    #include "MK52D10/include/MK52D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK52D10/include/MK52D10_features.h"
+
+#elif (defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || defined(CPU_MK53DN512CMD10) || \
+    defined(CPU_MK53DX256CMD10))
+
+    #define K53D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK53D10/include/MK53D10.h"
+    /* Extension register definitions */
+    #include "MK53D10/include/MK53D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK53D10/include/MK53D10_features.h"
+
+#elif (defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DN512VLL10) || \
+    defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DN512VLQ10) || \
+    defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || defined(CPU_MK60DN512VMC10) || \
+    defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10))
+
+    #define K60D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK60D10/include/MK60D10.h"
+    /* Extension register definitions */
+    #include "MK60D10/include/MK60D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK60D10/include/MK60D10_features.h"
+
+#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12))
+
+    #define K63F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK63F12/include/MK63F12.h"
+    /* Extension register definitions */
+    #include "MK63F12/include/MK63F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK63F12/include/MK63F12_features.h"
+
+#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
+    defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12))
+
+
+    #define K64F12_SERIES
+    /* CMSIS-style register definitions */
+    #include "MK64F12/include/MK64F12.h"
+    /* Extension register definitions */
+    #include "MK64F12/include/MK64F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK64F12/include/MK64F12_features.h"
+
+#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
+    defined(CPU_MK65FX1M0VMI18))
+
+    #define K65F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK65F18/include/MK65F18.h"
+    /* Extension register definitions */
+    #include "MK65F18/include/MK65F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK65F18/include/MK65F18_features.h"
+
+#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
+    defined(CPU_MK66FX1M0VMD18))
+
+    #define K66F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK66F18/include/MK66F18.h"
+    /* Extension register definitions */
+    #include "MK66F18/include/MK66F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK66F18/include/MK66F18_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12))
+
+    #define K70F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F12/include/MK70F12.h"
+    /* Extension register definitions */
+    #include "MK70F12/include/MK70F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F12/include/MK70F12_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+
+    #define K70F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F15/include/MK70F15.h"
+    /* Extension register definitions */
+    #include "MK70F15/include/MK70F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F15/include/MK70F15_features.h"
+
+#elif (defined(CPU_MK80FN256CAx15) || defined(CPU_MK80FN256VDC15) || defined(CPU_MK80FN256VLL15) || \
+    defined(CPU_MK80FN256VLQ15))
+
+    #define K80F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK80F25615/include/MK80F25615.h"
+    /* Extension register definitions */
+    #include "MK80F25615/include/MK80F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK80F25615/include/MK80F25615_features.h"
+
+#elif (defined(CPU_MK81FN256CAx15) || defined(CPU_MK81FN256VDC15) || defined(CPU_MK81FN256VLL15) || \
+    defined(CPU_MK81FN256VLQ15))
+
+    #define K81F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK81F25615/include/MK81F25615.h"
+    /* Extension register definitions */
+    #include "MK81F25615/include/MK81F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK81F25615/include/MK81F25615_features.h"
+
+#elif (defined(CPU_MK82FN256CAx15) || defined(CPU_MK82FN256VDC15) || defined(CPU_MK82FN256VLL15) || \
+    defined(CPU_MK82FN256VLQ15))
+
+    #define K82F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK82F25615/include/MK82F25615.h"
+    /* Extension register definitions */
+    #include "MK82F25615/include/MK82F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK82F25615/include/MK82F25615_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC2) || defined(CPU_MKE02Z32VLC2) || defined(CPU_MKE02Z16VLC2) || \
+    defined(CPU_MKE02Z64VLD2) || defined(CPU_MKE02Z32VLD2) || defined(CPU_MKE02Z16VLD2) || \
+    defined(CPU_MKE02Z64VLH2) || defined(CPU_MKE02Z64VQH2) || defined(CPU_MKE02Z32VLH2) || \
+    defined(CPU_MKE02Z32VQH2))
+
+    #define KE02Z2_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z2/include/MKE02Z2.h"
+    /* Extension register definitions */
+    #include "MKE02Z2/include/MKE02Z2_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z2/include/MKE02Z2_features.h"
+
+#elif (defined(CPU_SKEAZN64MLC2) || defined(CPU_SKEAZN32MLC2) || defined(CPU_SKEAZN16MLC2) || \
+    defined(CPU_SKEAZN64MLD2) || defined(CPU_SKEAZN32MLD2) || defined(CPU_SKEAZN16MLD2) || \
+    defined(CPU_SKEAZN64MLH2) || defined(CPU_SKEAZN32MLH2))
+
+    #define SKEAZN642_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN642/include/SKEAZN642.h"
+    /* Extension register definitions */
+    #include "SKEAZN642/include/SKEAZN642_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN642/include/SKEAZN642_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC4) || defined(CPU_MKE02Z32VLC4) || defined(CPU_MKE02Z16VLC4) || \
+    defined(CPU_MKE02Z64VLD4) || defined(CPU_MKE02Z32VLD4) || defined(CPU_MKE02Z16VLD4) || \
+    defined(CPU_MKE02Z64VLH4) || defined(CPU_MKE02Z64VQH4) || defined(CPU_MKE02Z32VLH4) || \
+    defined(CPU_MKE02Z32VQH4))
+
+    #define KE02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z4/include/MKE02Z4.h"
+    /* Extension register definitions */
+    #include "MKE02Z4/include/MKE02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z4/include/MKE02Z4_features.h"
+
+#elif (defined(CPU_MKE04Z128VLD4) || defined(CPU_MKE04Z64VLD4) || defined(CPU_MKE04Z128VLK4) || \
+    defined(CPU_MKE04Z64VLK4) || defined(CPU_MKE04Z128VQH4) || defined(CPU_MKE04Z64VQH4) || \
+    defined(CPU_MKE04Z128VLH4) || defined(CPU_MKE04Z64VLH4))
+
+    #define KE04Z1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284.h"
+    /* Extension register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_features.h"
+
+#elif (defined(CPU_MKE04Z8VFK4) || defined(CPU_MKE04Z8VTG4) || defined(CPU_MKE04Z8VWJ4))
+
+    #define KE04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z4/include/MKE04Z4.h"
+    /* Extension register definitions */
+    #include "MKE04Z4/include/MKE04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z4/include/MKE04Z4_features.h"
+
+#elif (defined(CPU_SKEAZN8MFK) || defined(CPU_SKEAZN8MTG))
+
+    #define SKEAZN84_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN84/include/SKEAZN84.h"
+    /* Extension register definitions */
+    #include "SKEAZN84/include/SKEAZN84_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN84/include/SKEAZN84_features.h"
+
+#elif (defined(CPU_MKE06Z128VLD4) || defined(CPU_MKE06Z64VLD4) || defined(CPU_MKE06Z128VLK4) || \
+    defined(CPU_MKE06Z64VLK4) || defined(CPU_MKE06Z128VQH4) || defined(CPU_MKE06Z64VQH4) || \
+    defined(CPU_MKE06Z128VLH4) || defined(CPU_MKE06Z64VLH4))
+
+    #define KE06Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE06Z4/include/MKE06Z4.h"
+    /* Extension register definitions */
+    #include "MKE06Z4/include/MKE06Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE06Z4/include/MKE06Z4_features.h"
+
+#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
+    defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \
+    defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4))
+
+    #define KL02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL02Z4/include/MKL02Z4.h"
+    /* Extension register definitions */
+    #include "MKL02Z4/include/MKL02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL02Z4/include/MKL02Z4_features.h"
+
+#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \
+    defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \
+    defined(CPU_MKL03Z32VFK4))
+
+    #define KL03Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL03Z4/include/MKL03Z4.h"
+    /* Extension register definitions */
+    #include "MKL03Z4/include/MKL03Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL03Z4/include/MKL03Z4_features.h"
+
+#elif (defined(CPU_MKL04Z8VFK4) || defined(CPU_MKL04Z16VFK4) || defined(CPU_MKL04Z32VFK4) || \
+    defined(CPU_MKL04Z8VLC4) || defined(CPU_MKL04Z16VLC4) || defined(CPU_MKL04Z32VLC4) || \
+    defined(CPU_MKL04Z8VFM4) || defined(CPU_MKL04Z16VFM4) || defined(CPU_MKL04Z32VFM4) || \
+    defined(CPU_MKL04Z16VLF4) || defined(CPU_MKL04Z32VLF4))
+
+    #define KL04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL04Z4/include/MKL04Z4.h"
+    /* Extension register definitions */
+    #include "MKL04Z4/include/MKL04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL04Z4/include/MKL04Z4_features.h"
+
+#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \
+    defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
+    defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
+    defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4))
+
+    #define KL05Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL05Z4/include/MKL05Z4.h"
+    /* Extension register definitions */
+    #include "MKL05Z4/include/MKL05Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL05Z4/include/MKL05Z4_features.h"
+
+#elif (defined(CPU_MKL13Z32VFM4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z32VFT4) || \
+    defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z32VLH4) || defined(CPU_MKL13Z64VLH4) || \
+    defined(CPU_MKL13Z32VLK4) || defined(CPU_MKL13Z64VLK4) || defined(CPU_MKL13Z32VMP4) || \
+    defined(CPU_MKL13Z64VMP4))
+
+    #define KL13Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL13Z644/include/MKL13Z644.h"
+    /* Extension register definitions */
+    #include "MKL13Z644/include/MKL13Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL13Z644/include/MKL13Z644_features.h"
+
+#elif (defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || defined(CPU_MKL14Z32VFT4) || \
+    defined(CPU_MKL14Z64VFT4) || defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || \
+    defined(CPU_MKL14Z32VLK4) || defined(CPU_MKL14Z64VLK4))
+
+    #define KL14Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL14Z4/include/MKL14Z4.h"
+    /* Extension register definitions */
+    #include "MKL14Z4/include/MKL14Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL14Z4/include/MKL14Z4_features.h"
+
+#elif (defined(CPU_MKL15Z128CAD4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || \
+    defined(CPU_MKL15Z128VFM4) || defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || \
+    defined(CPU_MKL15Z128VFT4) || defined(CPU_MKL15Z32VLH4) || defined(CPU_MKL15Z64VLH4) || \
+    defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || defined(CPU_MKL15Z64VLK4) || \
+    defined(CPU_MKL15Z128VLK4))
+
+    #define KL15Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL15Z4/include/MKL15Z4.h"
+    /* Extension register definitions */
+    #include "MKL15Z4/include/MKL15Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL15Z4/include/MKL15Z4_features.h"
+
+#elif (defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || \
+    defined(CPU_MKL16Z32VFT4) || defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || \
+    defined(CPU_MKL16Z32VLH4) || defined(CPU_MKL16Z64VLH4) || defined(CPU_MKL16Z128VLH4) || \
+    defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VMP4))
+
+    #define KL16Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL16Z4/include/MKL16Z4.h"
+    /* Extension register definitions */
+    #include "MKL16Z4/include/MKL16Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL16Z4/include/MKL16Z4_features.h"
+
+#elif (defined(CPU_MKL17Z128VFM4) || defined(CPU_MKL17Z256VFM4) || defined(CPU_MKL17Z128VFT4) || \
+    defined(CPU_MKL17Z256VFT4) || defined(CPU_MKL17Z128VLH4) || defined(CPU_MKL17Z256VLH4) || \
+    defined(CPU_MKL17Z128VMP4) || defined(CPU_MKL17Z256VMP4))
+
+    #define KL17Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z4/include/MKL17Z4.h"
+    /* Extension register definitions */
+    #include "MKL17Z4/include/MKL17Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z4/include/MKL17Z4_features.h"
+
+#elif (defined(CPU_MKL17Z32VDA4) || defined(CPU_MKL17Z64VDA4) || defined(CPU_MKL17Z32VFM4) || \
+    defined(CPU_MKL17Z64VFM4) || defined(CPU_MKL17Z32VFT4) || defined(CPU_MKL17Z64VFT4) || \
+    defined(CPU_MKL17Z32VLH4) || defined(CPU_MKL17Z64VLH4) || defined(CPU_MKL17Z32VMP4) || \
+    defined(CPU_MKL17Z64VMP4))
+
+    #define KL17Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z644/include/MKL17Z644.h"
+    /* Extension register definitions */
+    #include "MKL17Z644/include/MKL17Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z644/include/MKL17Z644_features.h"
+
+#elif (defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || defined(CPU_MKL24Z32VFT4) || \
+    defined(CPU_MKL24Z64VFT4) || defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || \
+    defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4))
+
+    #define KL24Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL24Z4/include/MKL24Z4.h"
+    /* Extension register definitions */
+    #include "MKL24Z4/include/MKL24Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL24Z4/include/MKL24Z4_features.h"
+
+#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
+    defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
+    defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
+    defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
+
+    #define KL25Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL25Z4/include/MKL25Z4.h"
+    /* Extension register definitions */
+    #include "MKL25Z4/include/MKL25Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL25Z4/include/MKL25Z4_features.h"
+
+
+#elif (defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || \
+    defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || \
+    defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || \
+    defined(CPU_MKL26Z128VLH4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z128VLL4) || \
+    defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
+    defined(CPU_MKL26Z256VMP4))
+
+    #define KL26Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL26Z4/include/MKL26Z4.h"
+    /* Extension register definitions */
+    #include "MKL26Z4/include/MKL26Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL26Z4/include/MKL26Z4_features.h"
+
+#elif (defined(CPU_MKL27Z128VFM4) || defined(CPU_MKL27Z256VFM4) || defined(CPU_MKL27Z128VFT4) || \
+    defined(CPU_MKL27Z256VFT4) || defined(CPU_MKL27Z128VLH4) || defined(CPU_MKL27Z256VLH4) || \
+    defined(CPU_MKL27Z128VMP4) || defined(CPU_MKL27Z256VMP4))
+
+    #define KL27Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z4/include/MKL27Z4.h"
+    /* Extension register definitions */
+    #include "MKL27Z4/include/MKL27Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z4/include/MKL27Z4_features.h"
+
+#elif (defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z64VDA4) || defined(CPU_MKL27Z32VFM4) || \
+    defined(CPU_MKL27Z64VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z64VFT4) || \
+    defined(CPU_MKL27Z32VLH4) || defined(CPU_MKL27Z64VLH4) || defined(CPU_MKL27Z32VMP4) || \
+    defined(CPU_MKL27Z64VMP4))
+
+    #define KL27Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z644/include/MKL27Z644.h"
+    /* Extension register definitions */
+    #include "MKL27Z644/include/MKL27Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z644/include/MKL27Z644_features.h"
+
+#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \
+    defined(CPU_MKL33Z256VMP4))
+
+    #define KL33Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z4/include/MKL33Z4.h"
+    /* Extension register definitions */
+    #include "MKL33Z4/include/MKL33Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z4/include/MKL33Z4_features.h"
+
+#elif (defined(CPU_MKL33Z32VFT4) || defined(CPU_MKL33Z64VFT4) || defined(CPU_MKL33Z32VLH4) || \
+    defined(CPU_MKL33Z64VLH4) || defined(CPU_MKL33Z32VLK4) || defined(CPU_MKL33Z64VLK4) || \
+    defined(CPU_MKL33Z32VMP4) || defined(CPU_MKL33Z64VMP4))
+
+    #define KL33Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z644/include/MKL33Z644.h"
+    /* Extension register definitions */
+    #include "MKL33Z644/include/MKL33Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z644/include/MKL33Z644_features.h"
+
+#elif (defined(CPU_MKL34Z64VLH4) || defined(CPU_MKL34Z64VLL4))
+
+    #define KL34Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL34Z4/include/MKL34Z4.h"
+    /* Extension register definitions */
+    #include "MKL34Z4/include/MKL34Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL34Z4/include/MKL34Z4_features.h"
+
+#elif (defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || \
+    defined(CPU_MKL36Z64VLL4) || defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || \
+    defined(CPU_MKL36Z128VMC4) || defined(CPU_MKL36Z256VMC4) || defined(CPU_MKL36Z256VMP4))
+
+    #define KL36Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL36Z4/include/MKL36Z4.h"
+    /* Extension register definitions */
+    #include "MKL36Z4/include/MKL36Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL36Z4/include/MKL36Z4_features.h"
+
+#elif (defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z128VMP4) || \
+    defined(CPU_MKL43Z256VMP4))
+
+    #define KL43Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL43Z4/include/MKL43Z4.h"
+    /* Extension register definitions */
+    #include "MKL43Z4/include/MKL43Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL43Z4/include/MKL43Z4_features.h"
+
+#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
+    defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \
+    defined(CPU_MKL46Z256VMP4))
+
+    #define KL46Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL46Z4/include/MKL46Z4.h"
+    /* Extension register definitions */
+    #include "MKL46Z4/include/MKL46Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL46Z4/include/MKL46Z4_features.h"
+
+#elif (defined(CPU_MKM14Z128AHH5) || defined(CPU_MKM14Z64AHH5))
+
+    #define KM14ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5.h"
+    /* Extension register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_features.h"
+
+#elif (defined(CPU_MKM33Z128ALH5) || defined(CPU_MKM33Z64ALH5) || defined(CPU_MKM33Z128ALL5) || \
+    defined(CPU_MKM33Z64ALL5))
+
+    #define KM33ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5.h"
+    /* Extension register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z128ALL5))
+
+    #define KM34ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5.h"
+    /* Extension register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z256VLL7) || defined(CPU_MKM34Z256VLQ7))
+
+    #define KM34Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34Z7/include/MKM34Z7.h"
+    /* Extension register definitions */
+    #include "MKM34Z7/include/MKM34Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34Z7/include/MKM34Z7_features.h"
+
+#elif (defined(CPU_MKV10Z16VFM7) || defined(CPU_MKV10Z16VLC7) || defined(CPU_MKV10Z16VLF7) || \
+    defined(CPU_MKV10Z32VFM7) || defined(CPU_MKV10Z32VLC7) || defined(CPU_MKV10Z32VLF7))
+
+    #define KV10Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z7/include/MKV10Z7.h"
+    /* Extension register definitions */
+    #include "MKV10Z7/include/MKV10Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z7/include/MKV10Z7_features.h"
+
+#elif (defined(CPU_MKV10Z128VFM7) || defined(CPU_MKV10Z128VLC7) || defined(CPU_MKV10Z128VLF7) || \
+    defined(CPU_MKV10Z128VLH7) || defined(CPU_MKV10Z64VFM7) || defined(CPU_MKV10Z64VLC7) || \
+    defined(CPU_MKV10Z64VLF7) || defined(CPU_MKV10Z64VLH7))
+
+    #define KV10Z1287_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z1287/include/MKV10Z1287.h"
+    /* Extension register definitions */
+    #include "MKV10Z1287/include/MKV10Z1287_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z1287/include/MKV10Z1287_features.h"
+
+#elif (defined(CPU_MKV11Z128VFM7) || defined(CPU_MKV11Z128VLC7) || defined(CPU_MKV11Z128VLF7) || \
+    defined(CPU_MKV11Z128VLH7) || defined(CPU_MKV11Z64VFM7) || defined(CPU_MKV11Z64VLC7) || \
+    defined(CPU_MKV11Z64VLF7) || defined(CPU_MKV11Z64VLH7))
+
+    #define KV11Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV11Z7/include/MKV11Z7.h"
+    /* Extension register definitions */
+    #include "MKV11Z7/include/MKV11Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV11Z7/include/MKV11Z7_features.h"
+
+#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
+    defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10))
+
+    #define KV30F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV30F12810/include/MKV30F12810.h"
+    /* Extension register definitions */
+    #include "MKV30F12810/include/MKV30F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV30F12810/include/MKV30F12810_features.h"
+
+#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10))
+
+    #define KV31F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F12810/include/MKV31F12810.h"
+    /* Extension register definitions */
+    #include "MKV31F12810/include/MKV31F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F12810/include/MKV31F12810_features.h"
+
+#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12))
+
+    #define KV31F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F25612/include/MKV31F25612.h"
+    /* Extension register definitions */
+    #include "MKV31F25612/include/MKV31F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F25612/include/MKV31F25612_features.h"
+
+#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12))
+
+    #define KV31F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F51212/include/MKV31F51212.h"
+    /* Extension register definitions */
+    #include "MKV31F51212/include/MKV31F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F51212/include/MKV31F51212_features.h"
+
+#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
+    defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15))
+
+    #define KV40F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV40F15/include/MKV40F15.h"
+    /* Extension register definitions */
+    #include "MKV40F15/include/MKV40F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV40F15/include/MKV40F15_features.h"
+
+#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15))
+
+    #define KV43F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV43F15/include/MKV43F15.h"
+    /* Extension register definitions */
+    #include "MKV43F15/include/MKV43F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV43F15/include/MKV43F15_features.h"
+
+#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15))
+
+    #define KV44F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV44F15/include/MKV44F15.h"
+    /* Extension register definitions */
+    #include "MKV44F15/include/MKV44F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV44F15/include/MKV44F15_features.h"
+
+#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \
+    defined(CPU_MKV45F256VLL15))
+
+    #define KV45F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV45F15/include/MKV45F15.h"
+    /* Extension register definitions */
+    #include "MKV45F15/include/MKV45F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV45F15/include/MKV45F15_features.h"
+
+#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \
+    defined(CPU_MKV46F256VLL15))
+
+    #define KV46F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV46F15/include/MKV46F15.h"
+    /* Extension register definitions */
+    #include "MKV46F15/include/MKV46F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV46F15/include/MKV46F15_features.h"
+
+#elif (defined(CPU_MKW01Z128CHN4))
+
+    #define KW01Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW01Z4/include/MKW01Z4.h"
+    /* Extension register definitions */
+    #include "MKW01Z4/include/MKW01Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW01Z4/include/MKW01Z4_features.h"
+
+#elif (defined(CPU_MKW20Z160VHT4))
+
+    #define KW20Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW20Z4/include/MKW20Z4.h"
+    /* Extension register definitions */
+    #include "MKW20Z4/include/MKW20Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW20Z4/include/MKW20Z4_features.h"
+
+#elif (defined(CPU_MKW21D256VHA5) || defined(CPU_MKW21D512VHA5))
+
+    #define KW21D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW21D5/include/MKW21D5.h"
+    /* Extension register definitions */
+    #include "MKW21D5/include/MKW21D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW21D5/include/MKW21D5_features.h"
+
+#elif (defined(CPU_MKW22D512VHA5))
+
+    #define KW22D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW22D5/include/MKW22D5.h"
+    /* Extension register definitions */
+    #include "MKW22D5/include/MKW22D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW22D5/include/MKW22D5_features.h"
+
+#elif (defined(CPU_MKW24D512VHA5))
+
+    #define KW24D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW24D5/include/MKW24D5.h"
+    /* Extension register definitions */
+    #include "MKW24D5/include/MKW24D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW24D5/include/MKW24D5_features.h"
+
+#elif (defined(CPU_MKW30Z160VHM4))
+
+    #define KW30Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW30Z4/include/MKW30Z4.h"
+    /* Extension register definitions */
+    #include "MKW30Z4/include/MKW30Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW30Z4/include/MKW30Z4_features.h"
+
+#elif (defined(CPU_MKW40Z160VHT4))
+
+    #define KW40Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW40Z4/include/MKW40Z4.h"
+    /* Extension register definitions */
+    #include "MKW40Z4/include/MKW40Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW40Z4/include/MKW40Z4_features.h"
+
+#elif (defined(CPU_SKEAZ128MLH) || defined(CPU_SKEAZ64MLH) || defined(CPU_SKEAZ128MLK) || \
+    defined(CPU_SKEAZ64MLK))
+
+    #define SKEAZ1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284.h"
+    /* Extension register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/Workspace/ADC/Sources/main.c b/Workspace/ADC/Sources/main.c
new file mode 100644
index 0000000..530e685
--- /dev/null
+++ b/Workspace/ADC/Sources/main.c
@@ -0,0 +1,66 @@
+#include "MK64F12.h"
+
+void uart_putchar(char ch);
+unsigned short ADC_read16b(void);
+void put(char *ptr_str);
+void DelayFunction(void);
+
+int main(void)
+{
+    SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;/*Enable the ADC0 Clock*/
+    ADC0_CFG1 |= ADC_CFG1_MODE(3);/*16bits ADC*/
+    ADC0_SC1A |= ADC_SC1_ADCH(31);/*Disable the module, ADCH = 11111 */
+    uint16_t ubd;/*Variable to save the baud rate*/
+    uint8_t temp;
+    SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; /*Enable the UART clock*/
+    SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;/*Enable the PORTB clock*/
+    PORTB_PCR16 |= PORT_PCR_MUX(3);
+    PORTB_PCR17 |= PORT_PCR_MUX(3);
+    UART0_C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK ); /*Disable Tx and Rx*/
+    UART0_C1 = 0; /*Dafaultsettings of the register*/
+    ubd= (uint16_t)((21000*1000)/(9600 * 16)); /* Calculate baud settings */
+    temp = UART0_BDH & ~(UART_BDH_SBR(0x1F)); /*Save the value of UART0_BDH except SBR*/
+    UART0_BDH = temp | (((ubd& 0x1F00) >> 8));
+    UART0_BDL = (uint8_t)(ubd& UART_BDL_SBR_MASK);
+    UART0_C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK ); /* Enable receiver and transmitter */
+    uint8_t ch;
+    unsigned short bADCData;
+    put("\r\n ADC code example\r\n");
+    for (;;)
+    {
+        bADCData = ADC_read16b();
+        DelayFunction();
+    }
+    return 0;
+}
+
+unsigned short ADC_read16b(void)
+{
+    ADC0_SC1A = 26 & ADC_SC1_ADCH_MASK; //Write to SC1A to start conversion
+    while(ADC0_SC2 & ADC_SC2_ADACT_MASK); //Conversion in progress
+    while(!(ADC0_SC1A & ADC_SC1_COCO_MASK));//Until conversion complete
+    return ADC0_RA;
+}
+
+void uart_putchar(char ch)
+{
+    /* Wait until space is available in the FIFO */
+    while(!(UART0_S1 & UART_S1_TDRE_MASK));
+    /* Send the character */
+    UART0_D = (uint8_t)ch;
+}
+
+void put(char *ptr_str)
+{
+    while(*ptr_str)
+    uart_putchar(*ptr_str++);
+}
+
+void DelayFunction(void)
+{
+    unsigned long Counter = 0xFFFFF;
+    do
+    {
+        Counter--;
+    } while(Counter);
+}
diff --git a/Workspace/FTM_AND_PWM/.cproject b/Workspace/FTM_AND_PWM/.cproject
new file mode 100644
index 0000000..d009e49
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/.cproject
@@ -0,0 +1,129 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<macros>
+					<stringMacro name="PROJECT_KSDK_PATH" type="VALUE_TEXT" value="${KSDK_PATH}"/>
+				</macros>
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="FTM_AND_PWM" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.138424891" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.671934056" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1175035411" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1895319972" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.983170211" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.161883849" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1925652539" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.max" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.11219160" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.67316860" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.12133355" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.hard" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.295274606" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.fpv4spd16" valueType="enumerated"/>
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+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.446926023" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.611553597" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.1316335364" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
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+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.996371827" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.312855577" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.790468637" name="Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" value="ar" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.1774832244" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1114519651" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.584099008" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder buildPath="${workspace_loc:/GPIO}/Debug" id="ilg.gnuarmeclipse.managedbuild.cross.builder.2018125917" keepEnvironmentInBuildfile="false" name="Gnu Make Builder" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.2120002892" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.538999987" name="Use preprocessor" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.1145931798" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
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+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1102412416" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.154764793" name="Language standard" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.c99" valueType="enumerated"/>
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+									<listOptionValue builtIn="false" value="&quot;../Sources&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../Project_Settings/Startup_Code&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/CMSIS/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices/MK64F12/include&quot;"/>
+								</option>
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+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.1971374264" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;../Sources&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../Project_Settings/Startup_Code&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/CMSIS/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices/MK64F12/include&quot;"/>
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+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.613993163" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.462759647" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.1291283292" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.416132893" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.2026894627" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="-specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs" valueType="string"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.1394898970" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="&quot;MK64FN1M0xxx12_flash.ld&quot;"/>
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+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
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+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1276352763" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.830299569" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.282145612" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.2110003551" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.1898028372" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.338169926" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1783546987" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1190073944" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.805423770" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.1404268138" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
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+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
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+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1102412416;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.13072522">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1648336251;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.1060554805">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
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+	<storageModule moduleId="refreshScope"/>
+</cproject>
diff --git a/Workspace/FTM_AND_PWM/.cwGeneratedFileSetLog b/Workspace/FTM_AND_PWM/.cwGeneratedFileSetLog
new file mode 100644
index 0000000..da94cd8
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/.cwGeneratedFileSetLog
@@ -0,0 +1,19 @@
+Sources/main.c
+Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
+SDK/platform/devices/MK64F12/include/MK64F12_extension.h
+SDK/platform/CMSIS/Include/arm_math.h
+SDK/platform/CMSIS/Include/core_cmSimd.h
+SDK/platform/devices/MK64F12/include/MK64F12.h
+SDK/platform/CMSIS/Include/core_cm4.h
+SDK/platform/CMSIS/Include/arm_common_tables.h
+SDK/platform/devices/MK64F12/include/MK64F12_features.h
+SDK/platform/devices/fsl_device_registers.h
+SDK/platform/CMSIS/Include/arm_const_structs.h
+SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
+SDK/platform/CMSIS/Include/core_cmFunc.h
+SDK/platform/CMSIS/Include/core_cmInstr.h
+Project_Settings/Startup_Code/system_MK64F12.h
+Project_Settings/Startup_Code/startup.c
+Project_Settings/Startup_Code/startup_MK64F12.S
+Project_Settings/Startup_Code/startup.h
+Project_Settings/Startup_Code/system_MK64F12.c
\ No newline at end of file
diff --git a/Workspace/FTM_AND_PWM/.project b/Workspace/FTM_AND_PWM/.project
new file mode 100644
index 0000000..3955bea
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/.project
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>FTM_AND_PWM</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<variableList>
+		<variable>
+			<name>PROJECT_KSDK_PATH</name>
+			<value>file:/C:/Freescale/KSDK_1.3.0</value>
+		</variable>
+	</variableList>
+</projectDescription>
diff --git a/Workspace/FTM_AND_PWM/.settings/com.freescale.processorexpert.derivative.prefs b/Workspace/FTM_AND_PWM/.settings/com.freescale.processorexpert.derivative.prefs
new file mode 100644
index 0000000..60d5016
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/.settings/com.freescale.processorexpert.derivative.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+versionGenerated/versionGenerated=1.0.0.RT7_b1550-0615
diff --git a/Workspace/FTM_AND_PWM/.settings/language.settings.xml b/Workspace/FTM_AND_PWM/.settings/language.settings.xml
new file mode 100644
index 0000000..964859d
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/.settings/language.settings.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1868151765049822542" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings Cross ARM" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/Workspace/FTM_AND_PWM/Debug/FTM_AND_PWM.elf b/Workspace/FTM_AND_PWM/Debug/FTM_AND_PWM.elf
new file mode 100644
index 0000000..e7718f8
Binary files /dev/null and b/Workspace/FTM_AND_PWM/Debug/FTM_AND_PWM.elf differ
diff --git a/Workspace/FTM_AND_PWM/Debug/FTM_AND_PWM.map b/Workspace/FTM_AND_PWM/Debug/FTM_AND_PWM.map
new file mode 100644
index 0000000..ecfe2ac
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Debug/FTM_AND_PWM.map
@@ -0,0 +1,614 @@
+Archive member included because of file (symbol)
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+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (exit)
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+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_global_impure_ptr)
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+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (__libc_init_array)
+c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
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+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data._impure_ptr
+                0x00000000        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .eh_frame      0x00000000        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+m_interrupts     0x00000000         0x00000400         xr
+m_flash_config   0x00000400         0x00000010         xr
+m_text           0x00000410         0x000ffbf0         xr
+m_data           0x1fff0000         0x00010000         rw
+m_data_2         0x20000000         0x00030000         rw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+LOAD ./Sources/main.o
+LOAD ./Project_Settings/Startup_Code/startup.o
+LOAD ./Project_Settings/Startup_Code/startup_MK64F12.o
+LOAD ./Project_Settings/Startup_Code/system_MK64F12.o
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libstdc++_s.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libm.a
+START GROUP
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000400                HEAP_SIZE = DEFINED (__heap_size__)?__heap_size__:0x400
+                0x00000400                STACK_SIZE = DEFINED (__stack_size__)?__stack_size__:0x400
+                0x00000000                M_VECTOR_RAM_SIZE = DEFINED (__ram_vector_table__)?0x400:0x0
+
+.interrupts     0x00000000      0x400
+                0x00000000                __VECTOR_TABLE = .
+                0x00000000                . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector    0x00000000      0x400 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000000                __isr_vector
+                0x00000400                . = ALIGN (0x4)
+
+.flash_config   0x00000400       0x10
+                0x00000400                . = ALIGN (0x4)
+ *(.FlashConfig)
+ .FlashConfig   0x00000400       0x10 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000410                . = ALIGN (0x4)
+
+.text           0x00000410      0x384
+                0x00000410                . = ALIGN (0x4)
+ *(.text)
+ .text          0x00000410       0x54 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .text          0x00000464       0x74 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00000464                _start
+                0x00000464                _mainCRTStartup
+ .text          0x000004d8       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x000004d8                Reset_Handler
+                0x000004e8                DebugMon_Handler
+                0x000004e8                I2C0_IRQHandler
+                0x000004e8                HardFault_Handler
+                0x000004e8                SysTick_Handler
+                0x000004e8                UART3_RX_TX_IRQHandler
+                0x000004e8                PendSV_Handler
+                0x000004e8                NMI_Handler
+                0x000004e8                UART0_RX_TX_IRQHandler
+                0x000004e8                I2C1_IRQHandler
+                0x000004e8                DMA2_IRQHandler
+                0x000004e8                ENET_Error_IRQHandler
+                0x000004e8                CAN0_Tx_Warning_IRQHandler
+                0x000004e8                PIT0_IRQHandler
+                0x000004e8                CAN0_ORed_Message_buffer_IRQHandler
+                0x000004e8                CMP2_IRQHandler
+                0x000004e8                LLWU_IRQHandler
+                0x000004e8                ENET_Receive_IRQHandler
+                0x000004e8                ENET_1588_Timer_IRQHandler
+                0x000004e8                UART2_RX_TX_IRQHandler
+                0x000004e8                SWI_IRQHandler
+                0x000004e8                ADC0_IRQHandler
+                0x000004e8                UsageFault_Handler
+                0x000004e8                I2S0_Tx_IRQHandler
+                0x000004e8                CMT_IRQHandler
+                0x000004e8                UART4_RX_TX_IRQHandler
+                0x000004e8                SPI1_IRQHandler
+                0x000004e8                DefaultISR
+                0x000004e8                DMA9_IRQHandler
+                0x000004e8                DMA14_IRQHandler
+                0x000004e8                CMP1_IRQHandler
+                0x000004e8                Reserved71_IRQHandler
+                0x000004e8                PORTD_IRQHandler
+                0x000004e8                PORTB_IRQHandler
+                0x000004e8                UART4_ERR_IRQHandler
+                0x000004e8                ADC1_IRQHandler
+                0x000004e8                I2C2_IRQHandler
+                0x000004e8                PIT2_IRQHandler
+                0x000004e8                I2S0_Rx_IRQHandler
+                0x000004e8                DMA5_IRQHandler
+                0x000004e8                RTC_IRQHandler
+                0x000004e8                PDB0_IRQHandler
+                0x000004e8                CAN0_Rx_Warning_IRQHandler
+                0x000004e8                FTM1_IRQHandler
+                0x000004e8                UART5_RX_TX_IRQHandler
+                0x000004e8                UART3_ERR_IRQHandler
+                0x000004e8                PIT3_IRQHandler
+                0x000004e8                SDHC_IRQHandler
+                0x000004e8                RTC_Seconds_IRQHandler
+                0x000004e8                MCG_IRQHandler
+                0x000004e8                FTFE_IRQHandler
+                0x000004e8                UART2_ERR_IRQHandler
+                0x000004e8                DMA11_IRQHandler
+                0x000004e8                UART5_ERR_IRQHandler
+                0x000004e8                Read_Collision_IRQHandler
+                0x000004e8                DMA7_IRQHandler
+                0x000004e8                ENET_Transmit_IRQHandler
+                0x000004e8                USBDCD_IRQHandler
+                0x000004e8                USB0_IRQHandler
+                0x000004e8                SPI2_IRQHandler
+                0x000004e8                WDOG_EWM_IRQHandler
+                0x000004e8                MemManage_Handler
+                0x000004e8                SVC_Handler
+                0x000004e8                DMA13_IRQHandler
+                0x000004e8                DMA3_IRQHandler
+                0x000004e8                UART0_LON_IRQHandler
+                0x000004e8                RNG_IRQHandler
+                0x000004e8                DMA0_IRQHandler
+                0x000004e8                DMA15_IRQHandler
+                0x000004e8                DAC0_IRQHandler
+                0x000004e8                CAN0_Error_IRQHandler
+                0x000004e8                DMA4_IRQHandler
+                0x000004e8                PIT1_IRQHandler
+                0x000004e8                UART0_ERR_IRQHandler
+                0x000004e8                DMA_Error_IRQHandler
+                0x000004e8                LVD_LVW_IRQHandler
+                0x000004e8                SPI0_IRQHandler
+                0x000004e8                PORTA_IRQHandler
+                0x000004e8                DAC1_IRQHandler
+                0x000004e8                MCM_IRQHandler
+                0x000004e8                DMA12_IRQHandler
+                0x000004e8                CAN0_Bus_Off_IRQHandler
+                0x000004e8                FTM3_IRQHandler
+                0x000004e8                PORTE_IRQHandler
+                0x000004e8                FTM2_IRQHandler
+                0x000004e8                LPTMR0_IRQHandler
+                0x000004e8                BusFault_Handler
+                0x000004e8                DMA8_IRQHandler
+                0x000004e8                DMA10_IRQHandler
+                0x000004e8                CAN0_Wake_Up_IRQHandler
+                0x000004e8                UART1_ERR_IRQHandler
+                0x000004e8                UART1_RX_TX_IRQHandler
+                0x000004e8                CMP0_IRQHandler
+                0x000004e8                PORTC_IRQHandler
+                0x000004e8                DMA6_IRQHandler
+                0x000004e8                DMA1_IRQHandler
+ *(.text*)
+ .text.NVIC_EnableIRQ
+                0x000004ec       0x30 ./Sources/main.o
+ .text.main     0x0000051c       0x80 ./Sources/main.o
+                0x0000051c                main
+ .text.FTM0_IRQHandler
+                0x0000059c       0x48 ./Sources/main.o
+                0x0000059c                FTM0_IRQHandler
+ .text.init_data_bss
+                0x000005e4       0xcc ./Project_Settings/Startup_Code/startup.o
+                0x000005e4                init_data_bss
+ .text.SystemInit
+                0x000006b0       0x3c ./Project_Settings/Startup_Code/system_MK64F12.o
+                0x000006b0                SystemInit
+ .text.exit     0x000006ec       0x28 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+                0x000006ec                exit
+ .text.__libc_init_array
+                0x00000714       0x4c c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                0x00000714                __libc_init_array
+ .text.memset   0x00000760       0x10 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                0x00000760                memset
+ .text._exit    0x00000770        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                0x00000770                _exit
+ *(.rodata)
+ *(.rodata*)
+ .rodata.str1.1
+                0x00000774        0x2 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *fill*         0x00000776        0x2 
+ .rodata._global_impure_ptr
+                0x00000778        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                0x00000778                _global_impure_ptr
+ *(.glue_7)
+ .glue_7        0x00000000        0x0 linker stubs
+ *(.glue_7t)
+ .glue_7t       0x00000000        0x0 linker stubs
+ *(.eh_frame)
+ .eh_frame      0x0000077c        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.init)
+ .init          0x0000077c        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x0000077c                _init
+ .init          0x00000780        0x8 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ *(.fini)
+ .fini          0x00000788        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x00000788                _fini
+ .fini          0x0000078c        0x8 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000794                . = ALIGN (0x4)
+
+.vfp11_veneer   0x00000794        0x0
+ .vfp11_veneer  0x00000000        0x0 linker stubs
+
+.v4_bx          0x00000794        0x0
+ .v4_bx         0x00000000        0x0 linker stubs
+
+.iplt           0x00000794        0x0
+ .iplt          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM            0x00000794        0x8
+                0x00000794                __exidx_start = .
+ *(.ARM.exidx*)
+ .ARM.exidx     0x00000794        0x8 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x0000079c                __exidx_end = .
+
+.rel.dyn        0x0000079c        0x0
+ .rel.iplt      0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ctors          0x0000079c        0x0
+                0x0000079c                __CTOR_LIST__ = .
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+                0x0000079c                __CTOR_END__ = .
+
+.dtors          0x0000079c        0x0
+                0x0000079c                __DTOR_LIST__ = .
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+                0x0000079c                __DTOR_END__ = .
+
+.preinit_array  0x0000079c        0x0
+                0x0000079c                PROVIDE (__preinit_array_start, .)
+ *(.preinit_array*)
+                0x0000079c                PROVIDE (__preinit_array_end, .)
+
+.init_array     0x0000079c        0x4
+                0x0000079c                PROVIDE (__init_array_start, .)
+ *(SORT(.init_array.*))
+ *(.init_array*)
+ .init_array    0x0000079c        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x000007a0                PROVIDE (__init_array_end, .)
+
+.fini_array     0x000007a0        0x4
+                0x000007a0                PROVIDE (__fini_array_start, .)
+ *(SORT(.fini_array.*))
+ *(.fini_array*)
+ .fini_array    0x000007a0        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x000007a4                PROVIDE (__fini_array_end, .)
+                0x000007a4                __etext = .
+                0x000007a4                __DATA_ROM = .
+
+.interrupts_ram
+                0x1fff0000        0x0
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __VECTOR_RAM__ = .
+                0x1fff0000                __interrupts_ram_start__ = .
+ *(.m_interrupts_ram)
+                0x1fff0000                . = (. + M_VECTOR_RAM_SIZE)
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __interrupts_ram_end__ = .
+                0x00000000                __VECTOR_RAM = DEFINED (__ram_vector_table__)?__VECTOR_RAM__:ORIGIN (m_interrupts)
+                0x00000000                __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED (__ram_vector_table__)?(__interrupts_ram_end__ - __interrupts_ram_start__):0x0
+
+.data           0x1fff0000       0x64 load address 0x000007a4
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __DATA_RAM = .
+                0x1fff0000                __data_start__ = .
+ *(.data)
+ *(.data*)
+ .data.impure_data
+                0x1fff0000       0x60 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *(.jcr*)
+ .jcr           0x1fff0060        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .jcr           0x1fff0060        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __data_end__ = .
+                0x00000808                __DATA_END = (__DATA_ROM + (__data_end__ - __data_start__))
+                0x00100000                text_end = (ORIGIN (m_text) + 0xffbf0)
+                0x00000001                ASSERT ((__DATA_END <= text_end), region m_text overflowed with text and data)
+
+.igot.plt       0x1fff0064        0x0 load address 0x00000808
+ .igot.plt      0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.bss            0x1fff0064       0x1c load address 0x00000808
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __START_BSS = .
+                0x1fff0064                __bss_start__ = .
+ *(.bss)
+ .bss           0x1fff0064       0x1c c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.bss*)
+ *(COMMON)
+                0x1fff0080                . = ALIGN (0x4)
+                0x1fff0080                __bss_end__ = .
+                0x1fff0080                __END_BSS = .
+
+.heap           0x20000000      0x400
+                0x20000000                . = ALIGN (0x8)
+                0x20000000                __end__ = .
+                0x20000000                PROVIDE (end, .)
+                0x20000000                __HeapBase = .
+                0x20000400                . = (. + HEAP_SIZE)
+ *fill*         0x20000000      0x400 
+                0x20000400                __HeapLimit = .
+
+.stack          0x20000400      0x400
+                0x20000400                . = ALIGN (0x8)
+                0x20000800                . = (. + STACK_SIZE)
+ *fill*         0x20000400      0x400 
+                0x20030000                __StackTop = (ORIGIN (m_data_2) + 0x30000)
+                0x2002fc00                __StackLimit = (__StackTop - STACK_SIZE)
+                0x20030000                PROVIDE (__stack, __StackTop)
+
+.ARM.attributes
+                0x00000000       0x30
+ *(.ARM.attributes)
+ .ARM.attributes
+                0x00000000       0x22 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .ARM.attributes
+                0x00000022       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .ARM.attributes
+                0x00000056       0x20 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.attributes
+                0x00000076       0x39 ./Sources/main.o
+ .ARM.attributes
+                0x000000af       0x39 ./Project_Settings/Startup_Code/startup.o
+ .ARM.attributes
+                0x000000e8       0x1f ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .ARM.attributes
+                0x00000107       0x39 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .ARM.attributes
+                0x00000140       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .ARM.attributes
+                0x00000174       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .ARM.attributes
+                0x000001a8       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .ARM.attributes
+                0x000001dc       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .ARM.attributes
+                0x00000210       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .ARM.attributes
+                0x00000244       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .ARM.attributes
+                0x00000278       0x22 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000001                ASSERT ((__StackLimit >= __HeapLimit), region m_data_2 overflowed with stack and heap)
+OUTPUT(FTM_AND_PWM.elf elf32-littlearm)
+
+.debug_info     0x00000000     0x1327
+ .debug_info    0x00000000      0x8dd ./Sources/main.o
+ .debug_info    0x000008dd      0x3a7 ./Project_Settings/Startup_Code/startup.o
+ .debug_info    0x00000c84       0x93 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_info    0x00000d17      0x610 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_abbrev   0x00000000      0x392
+ .debug_abbrev  0x00000000      0x16a ./Sources/main.o
+ .debug_abbrev  0x0000016a       0xfa ./Project_Settings/Startup_Code/startup.o
+ .debug_abbrev  0x00000264       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_abbrev  0x00000278      0x11a ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_aranges  0x00000000       0x98
+ .debug_aranges
+                0x00000000       0x30 ./Sources/main.o
+ .debug_aranges
+                0x00000030       0x20 ./Project_Settings/Startup_Code/startup.o
+ .debug_aranges
+                0x00000050       0x20 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_aranges
+                0x00000070       0x28 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_ranges   0x00000000       0x48
+ .debug_ranges  0x00000000       0x20 ./Sources/main.o
+ .debug_ranges  0x00000020       0x10 ./Project_Settings/Startup_Code/startup.o
+ .debug_ranges  0x00000030       0x18 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_macro    0x00000000    0x30d8e
+ .debug_macro   0x00000000       0x8d ./Sources/main.o
+ .debug_macro   0x0000008d      0x856 ./Sources/main.o
+ .debug_macro   0x000008e3       0x16 ./Sources/main.o
+ .debug_macro   0x000008f9       0x16 ./Sources/main.o
+ .debug_macro   0x0000090f       0x44 ./Sources/main.o
+ .debug_macro   0x00000953      0x209 ./Sources/main.o
+ .debug_macro   0x00000b5c       0x56 ./Sources/main.o
+ .debug_macro   0x00000bb2       0x3b ./Sources/main.o
+ .debug_macro   0x00000bed       0x34 ./Sources/main.o
+ .debug_macro   0x00000c21       0x26 ./Sources/main.o
+ .debug_macro   0x00000c47      0xd1d ./Sources/main.o
+ .debug_macro   0x00001964       0x78 ./Sources/main.o
+ .debug_macro   0x000019dc    0x1773b ./Sources/main.o
+ .debug_macro   0x00019117      0x171 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019288       0x11 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019299       0x58 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000192f1       0x35 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019326       0xa3 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193c9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193df      0x10e ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000194ed       0x7f ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0001956c       0x52 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195be       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195d4       0x43 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019617      0x180 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019797       0x22 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197b9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197cf    0x16273 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0002fa42     0x1182 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00030bc4      0x162 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00030d26       0x68 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_line     0x00000000      0x9dc
+ .debug_line    0x00000000      0x277 ./Sources/main.o
+ .debug_line    0x00000277      0x364 ./Project_Settings/Startup_Code/startup.o
+ .debug_line    0x000005db       0x6a ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_line    0x00000645      0x397 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_str      0x00000000   0x19d099
+ .debug_str     0x00000000    0x900b5 ./Sources/main.o
+                              0x90256 (size before relaxing)
+ .debug_str     0x000900b5   0x10ceef ./Project_Settings/Startup_Code/startup.o
+                             0x19ca81 (size before relaxing)
+ .debug_str     0x0019cfa4       0xf5 ./Project_Settings/Startup_Code/system_MK64F12.o
+                             0x19cb3c (size before relaxing)
+
+.comment        0x00000000       0x70
+ .comment       0x00000000       0x70 ./Sources/main.o
+                                 0x71 (size before relaxing)
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/startup.o
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_frame    0x00000000      0x16c
+ .debug_frame   0x00000000       0x68 ./Sources/main.o
+ .debug_frame   0x00000068       0x2c ./Project_Settings/Startup_Code/startup.o
+ .debug_frame   0x00000094       0x44 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_frame   0x000000d8       0x28 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .debug_frame   0x00000100       0x2c c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .debug_frame   0x0000012c       0x20 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .debug_frame   0x0000014c       0x20 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
diff --git a/Workspace/FTM_AND_PWM/Debug/GPIO.map b/Workspace/FTM_AND_PWM/Debug/GPIO.map
new file mode 100644
index 0000000..14ab067
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Debug/GPIO.map
@@ -0,0 +1,610 @@
+Archive member included because of file (symbol)
+
+c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (exit)
+c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_global_impure_ptr)
+c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (__libc_init_array)
+c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (memset)
+c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                              c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_exit)
+
+Discarded input sections
+
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .data          0x00000000        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.extab     0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
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+ .data          0x00000000        0x0 ./Project_Settings/Startup_Code/startup.o
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+ .debug_macro   0x00000000    0x1773b ./Project_Settings/Startup_Code/startup.o
+ .data          0x00000000        0x0 ./Project_Settings/Startup_Code/startup_MK64F12.o
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+ .data.SystemCoreClock
+                0x00000000        0x4 ./Project_Settings/Startup_Code/system_MK64F12.o
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+ .debug_macro   0x00000000       0x3b ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x34 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x26 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000      0xd1d ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x78 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000    0x1773b ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x58 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x35 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0xa3 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x16 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000      0x10e ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x7f ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x52 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x16 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x43 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000      0x180 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x22 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x16 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000    0x16273 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000     0x1182 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data._impure_ptr
+                0x00000000        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .eh_frame      0x00000000        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .text          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .data          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .bss           0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+m_interrupts     0x00000000         0x00000400         xr
+m_flash_config   0x00000400         0x00000010         xr
+m_text           0x00000410         0x000ffbf0         xr
+m_data           0x1fff0000         0x00010000         rw
+m_data_2         0x20000000         0x00030000         rw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+LOAD ./Sources/main.o
+LOAD ./Project_Settings/Startup_Code/startup.o
+LOAD ./Project_Settings/Startup_Code/startup_MK64F12.o
+LOAD ./Project_Settings/Startup_Code/system_MK64F12.o
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libstdc++_s.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libm.a
+START GROUP
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+LOAD c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000400                HEAP_SIZE = DEFINED (__heap_size__)?__heap_size__:0x400
+                0x00000400                STACK_SIZE = DEFINED (__stack_size__)?__stack_size__:0x400
+                0x00000000                M_VECTOR_RAM_SIZE = DEFINED (__ram_vector_table__)?0x400:0x0
+
+.interrupts     0x00000000      0x400
+                0x00000000                __VECTOR_TABLE = .
+                0x00000000                . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector    0x00000000      0x400 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000000                __isr_vector
+                0x00000400                . = ALIGN (0x4)
+
+.flash_config   0x00000400       0x10
+                0x00000400                . = ALIGN (0x4)
+ *(.FlashConfig)
+ .FlashConfig   0x00000400       0x10 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000410                . = ALIGN (0x4)
+
+.text           0x00000410      0x444
+                0x00000410                . = ALIGN (0x4)
+ *(.text)
+ .text          0x00000410       0x54 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .text          0x00000464       0x74 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00000464                _start
+                0x00000464                _mainCRTStartup
+ .text          0x000004d8       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x000004d8                Reset_Handler
+                0x000004e8                DebugMon_Handler
+                0x000004e8                I2C0_IRQHandler
+                0x000004e8                HardFault_Handler
+                0x000004e8                SysTick_Handler
+                0x000004e8                UART3_RX_TX_IRQHandler
+                0x000004e8                PendSV_Handler
+                0x000004e8                NMI_Handler
+                0x000004e8                UART0_RX_TX_IRQHandler
+                0x000004e8                I2C1_IRQHandler
+                0x000004e8                DMA2_IRQHandler
+                0x000004e8                ENET_Error_IRQHandler
+                0x000004e8                CAN0_Tx_Warning_IRQHandler
+                0x000004e8                PIT0_IRQHandler
+                0x000004e8                CAN0_ORed_Message_buffer_IRQHandler
+                0x000004e8                CMP2_IRQHandler
+                0x000004e8                LLWU_IRQHandler
+                0x000004e8                ENET_Receive_IRQHandler
+                0x000004e8                ENET_1588_Timer_IRQHandler
+                0x000004e8                UART2_RX_TX_IRQHandler
+                0x000004e8                SWI_IRQHandler
+                0x000004e8                ADC0_IRQHandler
+                0x000004e8                UsageFault_Handler
+                0x000004e8                I2S0_Tx_IRQHandler
+                0x000004e8                CMT_IRQHandler
+                0x000004e8                UART4_RX_TX_IRQHandler
+                0x000004e8                SPI1_IRQHandler
+                0x000004e8                DefaultISR
+                0x000004e8                DMA9_IRQHandler
+                0x000004e8                DMA14_IRQHandler
+                0x000004e8                CMP1_IRQHandler
+                0x000004e8                Reserved71_IRQHandler
+                0x000004e8                PORTD_IRQHandler
+                0x000004e8                PORTB_IRQHandler
+                0x000004e8                UART4_ERR_IRQHandler
+                0x000004e8                ADC1_IRQHandler
+                0x000004e8                I2C2_IRQHandler
+                0x000004e8                PIT2_IRQHandler
+                0x000004e8                I2S0_Rx_IRQHandler
+                0x000004e8                DMA5_IRQHandler
+                0x000004e8                RTC_IRQHandler
+                0x000004e8                PDB0_IRQHandler
+                0x000004e8                CAN0_Rx_Warning_IRQHandler
+                0x000004e8                FTM1_IRQHandler
+                0x000004e8                UART5_RX_TX_IRQHandler
+                0x000004e8                UART3_ERR_IRQHandler
+                0x000004e8                PIT3_IRQHandler
+                0x000004e8                SDHC_IRQHandler
+                0x000004e8                RTC_Seconds_IRQHandler
+                0x000004e8                MCG_IRQHandler
+                0x000004e8                FTFE_IRQHandler
+                0x000004e8                UART2_ERR_IRQHandler
+                0x000004e8                DMA11_IRQHandler
+                0x000004e8                UART5_ERR_IRQHandler
+                0x000004e8                Read_Collision_IRQHandler
+                0x000004e8                DMA7_IRQHandler
+                0x000004e8                ENET_Transmit_IRQHandler
+                0x000004e8                USBDCD_IRQHandler
+                0x000004e8                USB0_IRQHandler
+                0x000004e8                SPI2_IRQHandler
+                0x000004e8                WDOG_EWM_IRQHandler
+                0x000004e8                MemManage_Handler
+                0x000004e8                SVC_Handler
+                0x000004e8                DMA13_IRQHandler
+                0x000004e8                DMA3_IRQHandler
+                0x000004e8                UART0_LON_IRQHandler
+                0x000004e8                RNG_IRQHandler
+                0x000004e8                DMA0_IRQHandler
+                0x000004e8                DMA15_IRQHandler
+                0x000004e8                DAC0_IRQHandler
+                0x000004e8                CAN0_Error_IRQHandler
+                0x000004e8                DMA4_IRQHandler
+                0x000004e8                PIT1_IRQHandler
+                0x000004e8                UART0_ERR_IRQHandler
+                0x000004e8                DMA_Error_IRQHandler
+                0x000004e8                LVD_LVW_IRQHandler
+                0x000004e8                SPI0_IRQHandler
+                0x000004e8                FTM0_IRQHandler
+                0x000004e8                PORTA_IRQHandler
+                0x000004e8                DAC1_IRQHandler
+                0x000004e8                MCM_IRQHandler
+                0x000004e8                DMA12_IRQHandler
+                0x000004e8                CAN0_Bus_Off_IRQHandler
+                0x000004e8                FTM3_IRQHandler
+                0x000004e8                PORTE_IRQHandler
+                0x000004e8                FTM2_IRQHandler
+                0x000004e8                LPTMR0_IRQHandler
+                0x000004e8                BusFault_Handler
+                0x000004e8                DMA8_IRQHandler
+                0x000004e8                DMA10_IRQHandler
+                0x000004e8                CAN0_Wake_Up_IRQHandler
+                0x000004e8                UART1_ERR_IRQHandler
+                0x000004e8                UART1_RX_TX_IRQHandler
+                0x000004e8                CMP0_IRQHandler
+                0x000004e8                PORTC_IRQHandler
+                0x000004e8                DMA6_IRQHandler
+                0x000004e8                DMA1_IRQHandler
+ *(.text*)
+ .text.main     0x000004ec      0x1b8 ./Sources/main.o
+                0x000004ec                main
+ .text.init_data_bss
+                0x000006a4       0xcc ./Project_Settings/Startup_Code/startup.o
+                0x000006a4                init_data_bss
+ .text.SystemInit
+                0x00000770       0x3c ./Project_Settings/Startup_Code/system_MK64F12.o
+                0x00000770                SystemInit
+ .text.exit     0x000007ac       0x28 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+                0x000007ac                exit
+ .text.__libc_init_array
+                0x000007d4       0x4c c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                0x000007d4                __libc_init_array
+ .text.memset   0x00000820       0x10 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                0x00000820                memset
+ .text._exit    0x00000830        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                0x00000830                _exit
+ *(.rodata)
+ *(.rodata*)
+ .rodata.str1.1
+                0x00000834        0x2 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *fill*         0x00000836        0x2 
+ .rodata._global_impure_ptr
+                0x00000838        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                0x00000838                _global_impure_ptr
+ *(.glue_7)
+ .glue_7        0x00000000        0x0 linker stubs
+ *(.glue_7t)
+ .glue_7t       0x00000000        0x0 linker stubs
+ *(.eh_frame)
+ .eh_frame      0x0000083c        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.init)
+ .init          0x0000083c        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x0000083c                _init
+ .init          0x00000840        0x8 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ *(.fini)
+ .fini          0x00000848        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x00000848                _fini
+ .fini          0x0000084c        0x8 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000854                . = ALIGN (0x4)
+
+.vfp11_veneer   0x00000854        0x0
+ .vfp11_veneer  0x00000000        0x0 linker stubs
+
+.v4_bx          0x00000854        0x0
+ .v4_bx         0x00000000        0x0 linker stubs
+
+.iplt           0x00000854        0x0
+ .iplt          0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM            0x00000854        0x8
+                0x00000854                __exidx_start = .
+ *(.ARM.exidx*)
+ .ARM.exidx     0x00000854        0x8 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x0000085c                __exidx_end = .
+
+.rel.dyn        0x0000085c        0x0
+ .rel.iplt      0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ctors          0x0000085c        0x0
+                0x0000085c                __CTOR_LIST__ = .
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+                0x0000085c                __CTOR_END__ = .
+
+.dtors          0x0000085c        0x0
+                0x0000085c                __DTOR_LIST__ = .
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+                0x0000085c                __DTOR_END__ = .
+
+.preinit_array  0x0000085c        0x0
+                0x0000085c                PROVIDE (__preinit_array_start, .)
+ *(.preinit_array*)
+                0x0000085c                PROVIDE (__preinit_array_end, .)
+
+.init_array     0x0000085c        0x4
+                0x0000085c                PROVIDE (__init_array_start, .)
+ *(SORT(.init_array.*))
+ *(.init_array*)
+ .init_array    0x0000085c        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x00000860                PROVIDE (__init_array_end, .)
+
+.fini_array     0x00000860        0x4
+                0x00000860                PROVIDE (__fini_array_start, .)
+ *(SORT(.fini_array.*))
+ *(.fini_array*)
+ .fini_array    0x00000860        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x00000864                PROVIDE (__fini_array_end, .)
+                0x00000864                __etext = .
+                0x00000864                __DATA_ROM = .
+
+.interrupts_ram
+                0x1fff0000        0x0
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __VECTOR_RAM__ = .
+                0x1fff0000                __interrupts_ram_start__ = .
+ *(.m_interrupts_ram)
+                0x1fff0000                . = (. + M_VECTOR_RAM_SIZE)
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __interrupts_ram_end__ = .
+                0x00000000                __VECTOR_RAM = DEFINED (__ram_vector_table__)?__VECTOR_RAM__:ORIGIN (m_interrupts)
+                0x00000000                __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED (__ram_vector_table__)?(__interrupts_ram_end__ - __interrupts_ram_start__):0x0
+
+.data           0x1fff0000       0x64 load address 0x00000864
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __DATA_RAM = .
+                0x1fff0000                __data_start__ = .
+ *(.data)
+ *(.data*)
+ .data.impure_data
+                0x1fff0000       0x60 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *(.jcr*)
+ .jcr           0x1fff0060        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .jcr           0x1fff0060        0x4 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __data_end__ = .
+                0x000008c8                __DATA_END = (__DATA_ROM + (__data_end__ - __data_start__))
+                0x00100000                text_end = (ORIGIN (m_text) + 0xffbf0)
+                0x00000001                ASSERT ((__DATA_END <= text_end), region m_text overflowed with text and data)
+
+.igot.plt       0x1fff0064        0x0 load address 0x000008c8
+ .igot.plt      0x00000000        0x0 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.bss            0x1fff0064       0x1c load address 0x000008c8
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __START_BSS = .
+                0x1fff0064                __bss_start__ = .
+ *(.bss)
+ .bss           0x1fff0064       0x1c c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.bss*)
+ *(COMMON)
+                0x1fff0080                . = ALIGN (0x4)
+                0x1fff0080                __bss_end__ = .
+                0x1fff0080                __END_BSS = .
+
+.heap           0x20000000      0x400
+                0x20000000                . = ALIGN (0x8)
+                0x20000000                __end__ = .
+                0x20000000                PROVIDE (end, .)
+                0x20000000                __HeapBase = .
+                0x20000400                . = (. + HEAP_SIZE)
+ *fill*         0x20000000      0x400 
+                0x20000400                __HeapLimit = .
+
+.stack          0x20000400      0x400
+                0x20000400                . = ALIGN (0x8)
+                0x20000800                . = (. + STACK_SIZE)
+ *fill*         0x20000400      0x400 
+                0x20030000                __StackTop = (ORIGIN (m_data_2) + 0x30000)
+                0x2002fc00                __StackLimit = (__StackTop - STACK_SIZE)
+                0x20030000                PROVIDE (__stack, __StackTop)
+
+.ARM.attributes
+                0x00000000       0x30
+ *(.ARM.attributes)
+ .ARM.attributes
+                0x00000000       0x22 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .ARM.attributes
+                0x00000022       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .ARM.attributes
+                0x00000056       0x20 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.attributes
+                0x00000076       0x39 ./Sources/main.o
+ .ARM.attributes
+                0x000000af       0x39 ./Project_Settings/Startup_Code/startup.o
+ .ARM.attributes
+                0x000000e8       0x1f ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .ARM.attributes
+                0x00000107       0x39 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .ARM.attributes
+                0x00000140       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .ARM.attributes
+                0x00000174       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .ARM.attributes
+                0x000001a8       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .ARM.attributes
+                0x000001dc       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .ARM.attributes
+                0x00000210       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .ARM.attributes
+                0x00000244       0x34 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .ARM.attributes
+                0x00000278       0x22 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000001                ASSERT ((__StackLimit >= __HeapLimit), region m_data_2 overflowed with stack and heap)
+OUTPUT(GPIO.elf elf32-littlearm)
+
+.debug_info     0x00000000      0xe1b
+ .debug_info    0x00000000      0x3d1 ./Sources/main.o
+ .debug_info    0x000003d1      0x3a7 ./Project_Settings/Startup_Code/startup.o
+ .debug_info    0x00000778       0x93 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_info    0x0000080b      0x610 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_abbrev   0x00000000      0x31b
+ .debug_abbrev  0x00000000       0xf3 ./Sources/main.o
+ .debug_abbrev  0x000000f3       0xfa ./Project_Settings/Startup_Code/startup.o
+ .debug_abbrev  0x000001ed       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_abbrev  0x00000201      0x11a ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_aranges  0x00000000       0x88
+ .debug_aranges
+                0x00000000       0x20 ./Sources/main.o
+ .debug_aranges
+                0x00000020       0x20 ./Project_Settings/Startup_Code/startup.o
+ .debug_aranges
+                0x00000040       0x20 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_aranges
+                0x00000060       0x28 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_ranges   0x00000000       0x38
+ .debug_ranges  0x00000000       0x10 ./Sources/main.o
+ .debug_ranges  0x00000010       0x10 ./Project_Settings/Startup_Code/startup.o
+ .debug_ranges  0x00000020       0x18 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_macro    0x00000000    0x30d8e
+ .debug_macro   0x00000000       0x8d ./Sources/main.o
+ .debug_macro   0x0000008d      0x856 ./Sources/main.o
+ .debug_macro   0x000008e3       0x16 ./Sources/main.o
+ .debug_macro   0x000008f9       0x16 ./Sources/main.o
+ .debug_macro   0x0000090f       0x44 ./Sources/main.o
+ .debug_macro   0x00000953      0x209 ./Sources/main.o
+ .debug_macro   0x00000b5c       0x56 ./Sources/main.o
+ .debug_macro   0x00000bb2       0x3b ./Sources/main.o
+ .debug_macro   0x00000bed       0x34 ./Sources/main.o
+ .debug_macro   0x00000c21       0x26 ./Sources/main.o
+ .debug_macro   0x00000c47      0xd1d ./Sources/main.o
+ .debug_macro   0x00001964       0x78 ./Sources/main.o
+ .debug_macro   0x000019dc    0x1773b ./Sources/main.o
+ .debug_macro   0x00019117      0x171 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019288       0x11 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019299       0x58 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000192f1       0x35 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019326       0xa3 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193c9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193df      0x10e ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000194ed       0x7f ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0001956c       0x52 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195be       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195d4       0x43 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019617      0x180 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019797       0x22 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197b9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197cf    0x16273 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0002fa42     0x1182 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00030bc4      0x162 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00030d26       0x68 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_line     0x00000000      0x9e7
+ .debug_line    0x00000000      0x282 ./Sources/main.o
+ .debug_line    0x00000282      0x364 ./Project_Settings/Startup_Code/startup.o
+ .debug_line    0x000005e6       0x6a ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_line    0x00000650      0x397 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_str      0x00000000   0x19cabb
+ .debug_str     0x00000000    0x8fb05 ./Sources/main.o
+                              0x8fc6f (size before relaxing)
+ .debug_str     0x0008fb05   0x10cec1 ./Project_Settings/Startup_Code/startup.o
+                             0x19ca81 (size before relaxing)
+ .debug_str     0x0019c9c6       0xf5 ./Project_Settings/Startup_Code/system_MK64F12.o
+                             0x19cb3c (size before relaxing)
+
+.comment        0x00000000       0x70
+ .comment       0x00000000       0x70 ./Sources/main.o
+                                 0x71 (size before relaxing)
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/startup.o
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_frame    0x00000000      0x130
+ .debug_frame   0x00000000       0x2c ./Sources/main.o
+ .debug_frame   0x0000002c       0x2c ./Project_Settings/Startup_Code/startup.o
+ .debug_frame   0x00000058       0x44 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_frame   0x0000009c       0x28 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .debug_frame   0x000000c4       0x2c c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .debug_frame   0x000000f0       0x20 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .debug_frame   0x00000110       0x20 c:/freescale/kds_3.0.0/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
diff --git a/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/startup.d b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/startup.d
new file mode 100644
index 0000000..09df623
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/startup.d
@@ -0,0 +1,38 @@
+Project_Settings/Startup_Code/startup.o: \
+ ../Project_Settings/Startup_Code/startup.c \
+ ../Project_Settings/Startup_Code/startup.h \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h
+
+../Project_Settings/Startup_Code/startup.h:
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
diff --git a/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/startup.o b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/startup.o
new file mode 100644
index 0000000..1ad9a63
Binary files /dev/null and b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/startup.o differ
diff --git a/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/startup_MK64F12.d b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/startup_MK64F12.d
new file mode 100644
index 0000000..15e90f1
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/startup_MK64F12.d
@@ -0,0 +1,2 @@
+Project_Settings/Startup_Code/startup_MK64F12.o: \
+ ../Project_Settings/Startup_Code/startup_MK64F12.S
diff --git a/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/startup_MK64F12.o b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/startup_MK64F12.o
new file mode 100644
index 0000000..335db47
Binary files /dev/null and b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/startup_MK64F12.o differ
diff --git a/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/subdir.mk b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/subdir.mk
new file mode 100644
index 0000000..1e5a1fb
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/subdir.mk
@@ -0,0 +1,41 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Project_Settings/Startup_Code/startup.c \
+../Project_Settings/Startup_Code/system_MK64F12.c 
+
+S_UPPER_SRCS += \
+../Project_Settings/Startup_Code/startup_MK64F12.S 
+
+OBJS += \
+./Project_Settings/Startup_Code/startup.o \
+./Project_Settings/Startup_Code/startup_MK64F12.o \
+./Project_Settings/Startup_Code/system_MK64F12.o 
+
+C_DEPS += \
+./Project_Settings/Startup_Code/startup.d \
+./Project_Settings/Startup_Code/system_MK64F12.d 
+
+S_UPPER_DEPS += \
+./Project_Settings/Startup_Code/startup_MK64F12.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Project_Settings/Startup_Code/%.o: ../Project_Settings/Startup_Code/%.c
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM C Compiler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+Project_Settings/Startup_Code/%.o: ../Project_Settings/Startup_Code/%.S
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM GNU Assembler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+
diff --git a/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/system_MK64F12.d b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/system_MK64F12.d
new file mode 100644
index 0000000..d0e2961
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/system_MK64F12.d
@@ -0,0 +1,35 @@
+Project_Settings/Startup_Code/system_MK64F12.o: \
+ ../Project_Settings/Startup_Code/system_MK64F12.c \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
diff --git a/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/system_MK64F12.o b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/system_MK64F12.o
new file mode 100644
index 0000000..cd86214
Binary files /dev/null and b/Workspace/FTM_AND_PWM/Debug/Project_Settings/Startup_Code/system_MK64F12.o differ
diff --git a/Workspace/FTM_AND_PWM/Debug/Sources/main.d b/Workspace/FTM_AND_PWM/Debug/Sources/main.d
new file mode 100644
index 0000000..6984a8b
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Debug/Sources/main.d
@@ -0,0 +1,19 @@
+Sources/main.o: ../Sources/main.c \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
diff --git a/Workspace/FTM_AND_PWM/Debug/Sources/main.o b/Workspace/FTM_AND_PWM/Debug/Sources/main.o
new file mode 100644
index 0000000..53d5734
Binary files /dev/null and b/Workspace/FTM_AND_PWM/Debug/Sources/main.o differ
diff --git a/Workspace/FTM_AND_PWM/Debug/Sources/subdir.mk b/Workspace/FTM_AND_PWM/Debug/Sources/subdir.mk
new file mode 100644
index 0000000..95aa41f
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Debug/Sources/subdir.mk
@@ -0,0 +1,24 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Sources/main.c 
+
+OBJS += \
+./Sources/main.o 
+
+C_DEPS += \
+./Sources/main.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Sources/%.o: ../Sources/%.c
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM C Compiler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+
diff --git a/Workspace/FTM_AND_PWM/Debug/makefile b/Workspace/FTM_AND_PWM/Debug/makefile
new file mode 100644
index 0000000..62c1daa
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Debug/makefile
@@ -0,0 +1,77 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include Sources/subdir.mk
+-include Project_Settings/Startup_Code/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C++_DEPS)),)
+-include $(C++_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+ifneq ($(strip $(ASM_DEPS)),)
+-include $(ASM_DEPS)
+endif
+ifneq ($(strip $(CC_DEPS)),)
+-include $(CC_DEPS)
+endif
+ifneq ($(strip $(CPP_DEPS)),)
+-include $(CPP_DEPS)
+endif
+ifneq ($(strip $(CXX_DEPS)),)
+-include $(CXX_DEPS)
+endif
+ifneq ($(strip $(C_UPPER_DEPS)),)
+-include $(C_UPPER_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables 
+SECONDARY_SIZE += \
+FTM_AND_PWM.siz \
+
+
+# All Target
+all: FTM_AND_PWM.elf secondary-outputs
+
+# Tool invocations
+FTM_AND_PWM.elf: $(OBJS) $(USER_OBJS)
+	@echo 'Building target: $@'
+	@echo 'Invoking: Cross ARM C++ Linker'
+	arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -T "MK64FN1M0xxx12_flash.ld" -Xlinker --gc-sections -L"C:/Downloads/Workspaces/KDS/Lab/wksp5_lab4 B/wksp5/FTM_AND_PWM/Project_Settings/Linker_Files" -Wl,-Map,"FTM_AND_PWM.map" -specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs -o "FTM_AND_PWM.elf" $(OBJS) $(USER_OBJS) $(LIBS)
+	@echo 'Finished building target: $@'
+	@echo ' '
+
+FTM_AND_PWM.siz: FTM_AND_PWM.elf
+	@echo 'Invoking: Cross ARM GNU Print Size'
+	arm-none-eabi-size --format=berkeley "FTM_AND_PWM.elf"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+# Other Targets
+clean:
+	-$(RM) $(SECONDARY_SIZE)$(C++_DEPS)$(OBJS)$(C_DEPS)$(ASM_DEPS)$(CC_DEPS)$(CPP_DEPS)$(CXX_DEPS)$(C_UPPER_DEPS)$(S_UPPER_DEPS) FTM_AND_PWM.elf
+	-@echo ' '
+
+secondary-outputs: $(SECONDARY_SIZE)
+
+.PHONY: all clean dependents
+.SECONDARY:
+
+-include ../makefile.targets
diff --git a/Workspace/FTM_AND_PWM/Debug/objects.mk b/Workspace/FTM_AND_PWM/Debug/objects.mk
new file mode 100644
index 0000000..742c2da
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/Workspace/FTM_AND_PWM/Debug/sources.mk b/Workspace/FTM_AND_PWM/Debug/sources.mk
new file mode 100644
index 0000000..80f8a41
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Debug/sources.mk
@@ -0,0 +1,31 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ELF_SRCS := 
+O_SRCS := 
+CPP_SRCS := 
+C_UPPER_SRCS := 
+C_SRCS := 
+S_UPPER_SRCS := 
+OBJ_SRCS := 
+ASM_SRCS := 
+CXX_SRCS := 
+C++_SRCS := 
+CC_SRCS := 
+SECONDARY_SIZE := 
+C++_DEPS := 
+OBJS := 
+C_DEPS := 
+ASM_DEPS := 
+CC_DEPS := 
+CPP_DEPS := 
+CXX_DEPS := 
+C_UPPER_DEPS := 
+S_UPPER_DEPS := 
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Sources \
+Project_Settings/Startup_Code \
+
diff --git a/Workspace/FTM_AND_PWM/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch b/Workspace/FTM_AND_PWM/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch
new file mode 100644
index 0000000..cae21a4
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doConnectToRunning" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f kinetis.cfg"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/GPIO.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="GPIO"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/GPIO"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/FTM_AND_PWM/Project_Settings/Debugger/GPIO_Debug_Segger.launch b/Workspace/FTM_AND_PWM/Project_Settings/Debugger/GPIO_Debug_Segger.launch
new file mode 100644
index 0000000..68923d5
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Project_Settings/Debugger/GPIO_Debug_Segger.launch
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.jlink.launchConfigurationType">
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="MK64FN1M0xxx12"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="1000"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM J-Link"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/GPIO.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="GPIO"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/GPIO"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/FTM_AND_PWM/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld b/Workspace/FTM_AND_PWM/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
new file mode 100644
index 0000000..506082b
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
@@ -0,0 +1,245 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150624
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
+  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0
+  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
+  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+  } > m_data_2
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data_2
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
+}
+
diff --git a/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/startup.c b/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/startup.c
new file mode 100644
index 0000000..b89e7fc
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/startup.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "startup.h"
+#include "fsl_device_registers.h"
+
+#if (defined(__ICCARM__))
+    #pragma section = ".data"
+    #pragma section = ".data_init"
+    #pragma section = ".bss"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : init_data_bss
+ * Description   : Make necessary initializations for RAM.
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ *
+ * Tool Chians:
+ *   __GNUC__   : GCC
+ *   __CC_ARM   : KEIL
+ *   __ICCARM__ : IAR
+ *
+ *END**************************************************************************/
+void init_data_bss(void)
+{
+    uint32_t n; 
+    
+    /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+    #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base  
+    #define __VECTOR_RAM Image$$VECTOR_RAM$$Base  
+    #define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];  
+    extern uint32_t __VECTOR_RAM[];  
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif
+
+    if (__VECTOR_RAM != __VECTOR_TABLE)
+    {   
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+    else
+    {
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_TABLE;
+    }
+
+#if !defined(__CC_ARM) && !defined(__ICCARM__)
+    
+    /* Declare pointers for various data sections. These pointers
+     * are initialized using values pulled in from the linker file */
+    uint8_t * data_ram, * data_rom, * data_rom_end;
+    uint8_t * bss_start, * bss_end;
+
+    /* Get the addresses for the .data section (initialized data section) */
+#if defined(__GNUC__)
+    extern uint32_t __DATA_ROM[];
+    extern uint32_t __DATA_RAM[];
+    extern char __DATA_END[];
+    data_ram = (uint8_t *)__DATA_RAM;
+    data_rom = (uint8_t *)__DATA_ROM;
+    data_rom_end  = (uint8_t *)__DATA_END;
+    n = data_rom_end - data_rom;
+#endif
+
+    /* Copy initialized data from ROM to RAM */
+    while (n--)
+    {
+        *data_ram++ = *data_rom++;
+    }   
+    
+    /* Get the addresses for the .bss section (zero-initialized data) */
+#if defined(__GNUC__)
+    extern char __START_BSS[];
+    extern char __END_BSS[];
+    bss_start = (uint8_t *)__START_BSS;
+    bss_end = (uint8_t *)__END_BSS;
+#endif
+		
+    /* Clear the zero-initialized data section */
+    n = bss_end - bss_start;
+    while(n--)
+    {
+        *bss_start++ = 0;
+    }
+#endif /* !__CC_ARM && !__ICCARM__*/
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/startup.h b/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/startup.h
new file mode 100644
index 0000000..17ad55f
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/startup.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _STARTUP_H_
+#define _STARTUP_H_
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Make necessary initializations for RAM.
+ *
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ */
+void init_data_bss(void);
+
+#endif /* _STARTUP_H_*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/startup_MK64F12.S b/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/startup_MK64F12.S
new file mode 100644
index 0000000..aebe2e6
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/startup_MK64F12.S
@@ -0,0 +1,457 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK64F12.s                                                           */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK64F12                                                                     */
+/*  @version: 2.8                                                                         */
+/*  @date:    2015-2-19                                                                   */
+/*  @build:   b150225                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_IRQHandler                                 /* DMA Channel 0 Transfer Complete*/
+    .long   DMA1_IRQHandler                                 /* DMA Channel 1 Transfer Complete*/
+    .long   DMA2_IRQHandler                                 /* DMA Channel 2 Transfer Complete*/
+    .long   DMA3_IRQHandler                                 /* DMA Channel 3 Transfer Complete*/
+    .long   DMA4_IRQHandler                                 /* DMA Channel 4 Transfer Complete*/
+    .long   DMA5_IRQHandler                                 /* DMA Channel 5 Transfer Complete*/
+    .long   DMA6_IRQHandler                                 /* DMA Channel 6 Transfer Complete*/
+    .long   DMA7_IRQHandler                                 /* DMA Channel 7 Transfer Complete*/
+    .long   DMA8_IRQHandler                                 /* DMA Channel 8 Transfer Complete*/
+    .long   DMA9_IRQHandler                                 /* DMA Channel 9 Transfer Complete*/
+    .long   DMA10_IRQHandler                                /* DMA Channel 10 Transfer Complete*/
+    .long   DMA11_IRQHandler                                /* DMA Channel 11 Transfer Complete*/
+    .long   DMA12_IRQHandler                                /* DMA Channel 12 Transfer Complete*/
+    .long   DMA13_IRQHandler                                /* DMA Channel 13 Transfer Complete*/
+    .long   DMA14_IRQHandler                                /* DMA Channel 14 Transfer Complete*/
+    .long   DMA15_IRQHandler                                /* DMA Channel 15 Transfer Complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA Error Interrupt*/
+    .long   MCM_IRQHandler                                  /* Normal Interrupt*/
+    .long   FTFE_IRQHandler                                 /* FTFE Command complete interrupt*/
+    .long   Read_Collision_IRQHandler                       /* Read Collision Interrupt*/
+    .long   LVD_LVW_IRQHandler                              /* Low Voltage Detect, Low Voltage Warning*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup Unit*/
+    .long   WDOG_EWM_IRQHandler                             /* WDOG Interrupt*/
+    .long   RNG_IRQHandler                                  /* RNG Interrupt*/
+    .long   I2C0_IRQHandler                                 /* I2C0 interrupt*/
+    .long   I2C1_IRQHandler                                 /* I2C1 interrupt*/
+    .long   SPI0_IRQHandler                                 /* SPI0 Interrupt*/
+    .long   SPI1_IRQHandler                                 /* SPI1 Interrupt*/
+    .long   I2S0_Tx_IRQHandler                              /* I2S0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* I2S0 receive interrupt*/
+    .long   UART0_LON_IRQHandler                            /* UART0 LON interrupt*/
+    .long   UART0_RX_TX_IRQHandler                          /* UART0 Receive/Transmit interrupt*/
+    .long   UART0_ERR_IRQHandler                            /* UART0 Error interrupt*/
+    .long   UART1_RX_TX_IRQHandler                          /* UART1 Receive/Transmit interrupt*/
+    .long   UART1_ERR_IRQHandler                            /* UART1 Error interrupt*/
+    .long   UART2_RX_TX_IRQHandler                          /* UART2 Receive/Transmit interrupt*/
+    .long   UART2_ERR_IRQHandler                            /* UART2 Error interrupt*/
+    .long   UART3_RX_TX_IRQHandler                          /* UART3 Receive/Transmit interrupt*/
+    .long   UART3_ERR_IRQHandler                            /* UART3 Error interrupt*/
+    .long   ADC0_IRQHandler                                 /* ADC0 interrupt*/
+    .long   CMP0_IRQHandler                                 /* CMP0 interrupt*/
+    .long   CMP1_IRQHandler                                 /* CMP1 interrupt*/
+    .long   FTM0_IRQHandler                                 /* FTM0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FTM1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FTM2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* CMT interrupt*/
+    .long   RTC_IRQHandler                                  /* RTC interrupt*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds interrupt*/
+    .long   PIT0_IRQHandler                                 /* PIT timer channel 0 interrupt*/
+    .long   PIT1_IRQHandler                                 /* PIT timer channel 1 interrupt*/
+    .long   PIT2_IRQHandler                                 /* PIT timer channel 2 interrupt*/
+    .long   PIT3_IRQHandler                                 /* PIT timer channel 3 interrupt*/
+    .long   PDB0_IRQHandler                                 /* PDB0 Interrupt*/
+    .long   USB0_IRQHandler                                 /* USB0 interrupt*/
+    .long   USBDCD_IRQHandler                               /* USBDCD Interrupt*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt 71*/
+    .long   DAC0_IRQHandler                                 /* DAC0 interrupt*/
+    .long   MCG_IRQHandler                                  /* MCG Interrupt*/
+    .long   LPTMR0_IRQHandler                               /* LPTimer interrupt*/
+    .long   PORTA_IRQHandler                                /* Port A interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* SPI2 Interrupt*/
+    .long   UART4_RX_TX_IRQHandler                          /* UART4 Receive/Transmit interrupt*/
+    .long   UART4_ERR_IRQHandler                            /* UART4 Error interrupt*/
+    .long   UART5_RX_TX_IRQHandler                          /* UART5 Receive/Transmit interrupt*/
+    .long   UART5_ERR_IRQHandler                            /* UART5 Error interrupt*/
+    .long   CMP2_IRQHandler                                 /* CMP2 interrupt*/
+    .long   FTM3_IRQHandler                                 /* FTM3 fault, overflow and channels interrupt*/
+    .long   DAC1_IRQHandler                                 /* DAC1 interrupt*/
+    .long   ADC1_IRQHandler                                 /* ADC1 interrupt*/
+    .long   I2C2_IRQHandler                                 /* I2C2 interrupt*/
+    .long   CAN0_ORed_Message_buffer_IRQHandler             /* CAN0 OR'd message buffers interrupt*/
+    .long   CAN0_Bus_Off_IRQHandler                         /* CAN0 bus off interrupt*/
+    .long   CAN0_Error_IRQHandler                           /* CAN0 error interrupt*/
+    .long   CAN0_Tx_Warning_IRQHandler                      /* CAN0 Tx warning interrupt*/
+    .long   CAN0_Rx_Warning_IRQHandler                      /* CAN0 Rx warning interrupt*/
+    .long   CAN0_Wake_Up_IRQHandler                         /* CAN0 wake up interrupt*/
+    .long   SDHC_IRQHandler                                 /* SDHC interrupt*/
+    .long   ENET_1588_Timer_IRQHandler                      /* Ethernet MAC IEEE 1588 Timer Interrupt*/
+    .long   ENET_Transmit_IRQHandler                        /* Ethernet MAC Transmit Interrupt*/
+    .long   ENET_Receive_IRQHandler                         /* Ethernet MAC Receive Interrupt*/
+    .long   ENET_Error_IRQHandler                           /* Ethernet MAC Error and miscelaneous Interrupt*/
+    .long   DefaultISR                                      /* 102*/
+    .long   DefaultISR                                      /* 103*/
+    .long   DefaultISR                                      /* 104*/
+    .long   DefaultISR                                      /* 105*/
+    .long   DefaultISR                                      /* 106*/
+    .long   DefaultISR                                      /* 107*/
+    .long   DefaultISR                                      /* 108*/
+    .long   DefaultISR                                      /* 109*/
+    .long   DefaultISR                                      /* 110*/
+    .long   DefaultISR                                      /* 111*/
+    .long   DefaultISR                                      /* 112*/
+    .long   DefaultISR                                      /* 113*/
+    .long   DefaultISR                                      /* 114*/
+    .long   DefaultISR                                      /* 115*/
+    .long   DefaultISR                                      /* 116*/
+    .long   DefaultISR                                      /* 117*/
+    .long   DefaultISR                                      /* 118*/
+    .long   DefaultISR                                      /* 119*/
+    .long   DefaultISR                                      /* 120*/
+    .long   DefaultISR                                      /* 121*/
+    .long   DefaultISR                                      /* 122*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+    .long   DefaultISR                                      /* 240*/
+    .long   DefaultISR                                      /* 241*/
+    .long   DefaultISR                                      /* 242*/
+    .long   DefaultISR                                      /* 243*/
+    .long   DefaultISR                                      /* 244*/
+    .long   DefaultISR                                      /* 245*/
+    .long   DefaultISR                                      /* 246*/
+    .long   DefaultISR                                      /* 247*/
+    .long   DefaultISR                                      /* 248*/
+    .long   DefaultISR                                      /* 249*/
+    .long   DefaultISR                                      /* 250*/
+    .long   DefaultISR                                      /* 251*/
+    .long   DefaultISR                                      /* 252*/
+    .long   DefaultISR                                      /* 253*/
+    .long   DefaultISR                                      /* 254*/
+    .long   0xFFFFFFFF                                      /*  Reserved for user TRIM value*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_IRQHandler
+    def_irq_handler    DMA1_IRQHandler
+    def_irq_handler    DMA2_IRQHandler
+    def_irq_handler    DMA3_IRQHandler
+    def_irq_handler    DMA4_IRQHandler
+    def_irq_handler    DMA5_IRQHandler
+    def_irq_handler    DMA6_IRQHandler
+    def_irq_handler    DMA7_IRQHandler
+    def_irq_handler    DMA8_IRQHandler
+    def_irq_handler    DMA9_IRQHandler
+    def_irq_handler    DMA10_IRQHandler
+    def_irq_handler    DMA11_IRQHandler
+    def_irq_handler    DMA12_IRQHandler
+    def_irq_handler    DMA13_IRQHandler
+    def_irq_handler    DMA14_IRQHandler
+    def_irq_handler    DMA15_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFE_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    RNG_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    UART0_LON_IRQHandler
+    def_irq_handler    UART0_RX_TX_IRQHandler
+    def_irq_handler    UART0_ERR_IRQHandler
+    def_irq_handler    UART1_RX_TX_IRQHandler
+    def_irq_handler    UART1_ERR_IRQHandler
+    def_irq_handler    UART2_RX_TX_IRQHandler
+    def_irq_handler    UART2_ERR_IRQHandler
+    def_irq_handler    UART3_RX_TX_IRQHandler
+    def_irq_handler    UART3_ERR_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    PIT1_IRQHandler
+    def_irq_handler    PIT2_IRQHandler
+    def_irq_handler    PIT3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    UART4_RX_TX_IRQHandler
+    def_irq_handler    UART4_ERR_IRQHandler
+    def_irq_handler    UART5_RX_TX_IRQHandler
+    def_irq_handler    UART5_ERR_IRQHandler
+    def_irq_handler    CMP2_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    DAC1_IRQHandler
+    def_irq_handler    ADC1_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    CAN0_ORed_Message_buffer_IRQHandler
+    def_irq_handler    CAN0_Bus_Off_IRQHandler
+    def_irq_handler    CAN0_Error_IRQHandler
+    def_irq_handler    CAN0_Tx_Warning_IRQHandler
+    def_irq_handler    CAN0_Rx_Warning_IRQHandler
+    def_irq_handler    CAN0_Wake_Up_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    ENET_1588_Timer_IRQHandler
+    def_irq_handler    ENET_Transmit_IRQHandler
+    def_irq_handler    ENET_Receive_IRQHandler
+    def_irq_handler    ENET_Error_IRQHandler
+
+    .end
diff --git a/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/system_MK64F12.c b/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/system_MK64F12.c
new file mode 100644
index 0000000..e3c1376
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/system_MK64F12.c
@@ -0,0 +1,414 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief Device specific configuration file for MK64F12 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+#if (DISABLE_WDOG)
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+  /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+  WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+                 WDOG_STCTRLH_WAITEN_MASK |
+                 WDOG_STCTRLH_STOPEN_MASK |
+                 WDOG_STCTRLH_ALLOWUPDATE_MASK |
+                 WDOG_STCTRLH_CLKSRC_MASK |
+                 0x0100U;
+#endif /* (DISABLE_WDOG) */
+#ifdef CLOCK_SETUP
+  if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
+  {
+    if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
+    {
+       PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO:  Only has an effect if recovering from VLLSx.*/
+    }
+  } else {
+#ifdef SYSTEM_RTC_CR_VALUE
+    SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
+    if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
+      RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
+      RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
+      RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
+    }
+#endif
+  }
+
+  /* Power mode protection initialization */
+#ifdef SYSTEM_SMC_PMPROT_VALUE
+  SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
+#endif
+
+  /* System clock initialization */
+  /* Internal reference clock trim initialization */
+#if defined(SLOW_TRIM_ADDRESS)
+  if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) {                              /* Skip if non-volatile flash memory is erased */
+    MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
+  #endif /* defined(SLOW_TRIM_ADDRESS) */
+  #if defined(SLOW_FINE_TRIM_ADDRESS)
+    MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
+  #endif
+  #if defined(FAST_TRIM_ADDRESS)
+    MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
+  #endif
+  #if defined(FAST_FINE_TRIM_ADDRESS)
+    MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
+  #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
+#if defined(SLOW_TRIM_ADDRESS)
+  }
+  #endif /* defined(SLOW_TRIM_ADDRESS) */
+
+  /* Set system prescalers and clock sources */
+  SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
+  SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
+  SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+  /* Set MCG and OSC */
+#if  ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+  /* PORTA_PCR19: ISF=0,MUX=0 */
+  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
+  MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+  /* Check that the source of the FLL reference clock is the requested one. */
+  if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+    }
+  } else {
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+    }
+  }
+  MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+  MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+  OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
+  #if (MCG_MODE == MCG_MODE_BLPI)
+  /* BLPI specific */
+  MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
+  #endif
+
+#else /* MCG_MODE */
+  /* Set MCG and OSC */
+#if  (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+  /* PORTA_PCR19: ISF=0,MUX=0 */
+  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
+  MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+  OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
+  #if (MCG_MODE == MCG_MODE_PEE)
+  MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
+  #else
+  MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+  #endif
+  if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
+    while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
+    }
+  }
+  /* Check that the source of the FLL reference clock is the requested one. */
+  if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+    }
+  } else {
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+    }
+  }
+  MCG->C4 = ((SYSTEM_MCG_C4_VALUE)  & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+#endif /* MCG_MODE */
+
+  /* Common for all MCG modes */
+
+  /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
+  MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
+  MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+  if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
+    MCG->C5 |= MCG_C5_PLLCLKEN0_MASK;  /* PLL clock enable in mode other than PEE or PBE */
+  }
+  /* BLPE, PEE and PBE MCG mode specific */
+
+#if (MCG_MODE == MCG_MODE_BLPE)
+  MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
+#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
+  MCG->C6 |= (MCG_C6_PLLS_MASK);       /* Set C6 (PLL select, VCO divider etc.) */
+  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
+  }
+  #if (MCG_MODE == MCG_MODE_PEE)
+  MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
+  #endif
+#endif
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
+  }
+  /* Use LPTMR to wait for 1ms dor FLL clock stabilization */
+  SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;   /* Alow software control of LPMTR */
+  LPTMR0->CMR = LPTMR_CMR_COMPARE(0);  /* Default 1 LPO tick */
+  LPTMR0->CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00));
+  LPTMR0->PSR = (LPTMR_PSR_PCS(0x01) | LPTMR_PSR_PBYP_MASK); /* Clock source: LPO, Prescaler bypass enable */
+  LPTMR0->CSR = LPTMR_CSR_TEN_MASK;    /* LPMTR enable */
+  while((LPTMR0_CSR & LPTMR_CSR_TCF_MASK) == 0u) {
+  }
+  LPTMR0_CSR = 0x00;                   /* Disable LPTMR */
+  SIM_SCGC5 &= (uint32_t)~(uint32_t)SIM_SCGC5_LPTMR_MASK;
+#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
+  }
+#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+  }
+#elif (MCG_MODE == MCG_MODE_PEE)
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
+  }
+#endif
+#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
+  SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
+  while(SMC->PMSTAT != 0x04U) {        /* Wait until the system is in VLPR mode */
+  }
+#endif
+
+#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
+  SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
+#endif
+
+  /* PLL loss of lock interrupt request initialization */
+  if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
+    NVIC_EnableIRQ(MCG_IRQn);          /* Enable PLL loss of lock interrupt request */
+  }
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+  uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
+  uint16_t Divider;
+
+  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
+    /* Output of FLL or PLL is selected */
+    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
+      /* FLL is selected */
+      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+        case 0x00U:
+          MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+          break;
+        case 0x01U:
+          MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+          break;
+        case 0x02U:
+        default:
+          MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+          break;
+        }
+        if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
+          switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
+          case 0x38U:
+            Divider = 1536U;
+            break;
+          case 0x30U:
+            Divider = 1280U;
+            break;
+          default:
+            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+            break;
+          }
+        } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+          Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+        }
+        MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+        MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+      /* Select correct multiplier to calculate the MCG output clock  */
+      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+        case 0x00U:
+          MCGOUTClock *= 640U;
+          break;
+        case 0x20U:
+          MCGOUTClock *= 1280U;
+          break;
+        case 0x40U:
+          MCGOUTClock *= 1920U;
+          break;
+        case 0x60U:
+          MCGOUTClock *= 2560U;
+          break;
+        case 0x80U:
+          MCGOUTClock *= 732U;
+          break;
+        case 0xA0U:
+          MCGOUTClock *= 1464U;
+          break;
+        case 0xC0U:
+          MCGOUTClock *= 2197U;
+          break;
+        case 0xE0U:
+          MCGOUTClock *= 2929U;
+          break;
+        default:
+          break;
+      }
+    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+      /* PLL is selected */
+      Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
+      MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+      Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
+      MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
+    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
+    /* Internal reference clock is selected */
+    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+      Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+      MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
+    /* External reference clock is selected */
+    switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+    case 0x00U:
+      MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
+      break;
+    case 0x01U:
+      MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+      break;
+    case 0x02U:
+    default:
+      MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+      break;
+    }
+  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    /* Reserved value */
+    return;
+  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+  SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/system_MK64F12.h b/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/system_MK64F12.h
new file mode 100644
index 0000000..d6a5f05
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Project_Settings/Startup_Code/system_MK64F12.h
@@ -0,0 +1,352 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief Device specific configuration file for MK64F12 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK64F12_H_
+#define SYSTEM_MK64F12_H_                        /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG                 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI                   0U
+#define MCG_MODE_FBI                   1U
+#define MCG_MODE_BLPI                  2U
+#define MCG_MODE_FEE                   3U
+#define MCG_MODE_FBE                   4U
+#define MCG_MODE_BLPE                  5U
+#define MCG_MODE_PBE                   6U
+#define MCG_MODE_PEE                   7U
+
+/* Predefined clock setups
+   0 ... Default  part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock = 20.97152MHz
+         Bus clock  = 20.97152MHz
+   1 ... Maximum achievable clock frequency configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+   2 ... Chip internaly clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   3 ... Chip externally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: RTC oscillator reference clock
+         Core clock = 0.032768MHz
+         Bus clock  = 0.032768MHz
+   4 ... USB clock setup
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+ */
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ                50000000u           /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_XTAL32k_CLK_HZ             32768u              /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+#define CPU_INT_SLOW_CLK_HZ            32768u              /* Value of the slow internal oscillator clock frequency in Hz  */
+#define CPU_INT_FAST_CLK_HZ            4000000u            /* Value of the fast internal oscillator clock frequency in Hz  */
+#define CPU_INT_IRC_CLK_HZ             48000000u           /* Value of the 48M internal oscillator clock frequency in Hz  */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE            0x0300U             /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE        0x2AU               /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */                             /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */                        /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */                             /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */                        /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_FEI /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x06U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00110000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00U               /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 1)
+  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 2)
+  #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_BLPI /* Clock generator mode */
+  /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x46U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00040000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 3)
+  #define DEFAULT_SYSTEM_CLOCK         32768u              /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_BLPE /* Clock generator mode */
+  /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x82U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x02U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=1 */
+  #define SYSTEM_MCG_C7_VALUE          0x01U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00U               /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 4)
+  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
+  #define SYSTEM_SIM_CLKDIV2_VALUE     0x09U               /* SIM_CLKDIV2 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
+#endif
+#else
+  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* #if !defined(SYSTEM_MK64F12_H_) */
diff --git a/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/arm_common_tables.h b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000..039cc3d
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/arm_const_structs.h b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 0000000..726d06e
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/arm_math.h b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000..e4b2f62
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/arm_math.h
@@ -0,0 +1,7556 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_math.h
+*
+* Description:	Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   * 
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   * 
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+  #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31	   0x400000
+#define TABLE_SPACING_Q15	   0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+#elif defined __GNUC__
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__			/* Cosmic */
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+#elif defined __TASKING__
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+//#define __CLZ __clz
+//#endif
+
+//note: function can be removed when all toolchain support __CLZ for Cortex-M0
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+      ((q15_t) x * (q15_t) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		 *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15( 
+    const arm_cfft_instance_q15 * S, 
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31( 
+    const arm_cfft_instance_q31 * S, 
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+  
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in >= 0.0f)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+   
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("push")         \
+         _Pragma ("O1")
+    #else
+      #define LOW_OPTIMIZATION_ENTER 
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_EXIT \
+         _Pragma ("pop")
+    #else
+      #define LOW_OPTIMIZATION_EXIT  
+    #endif
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)		// Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)		// TASKING
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/core_cm4.h b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000..9749c27
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1858 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)IRQn < 0) {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)IRQn < 0) {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                             /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/core_cmFunc.h b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000..b6ad0a4
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,664 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+    or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+	or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/core_cmInstr.h b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000..fca425c
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,916 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+  return(result);
+}
+#endif
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+#endif
+  return(result);
+}
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/core_cmSimd.h b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/core_cmSimd.h
new file mode 100644
index 0000000..7b8e37f
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/SDK/platform/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/Workspace/FTM_AND_PWM/SDK/platform/devices/MK64F12/include/MK64F12.h b/Workspace/FTM_AND_PWM/SDK/platform/devices/MK64F12/include/MK64F12.h
new file mode 100644
index 0000000..3114ad7
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/SDK/platform/devices/MK64F12/include/MK64F12.h
@@ -0,0 +1,18767 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MK64F12
+**
+**     Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12.h
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief CMSIS Peripheral Access Layer for MK64F12
+ *
+ * CMSIS Peripheral Access Layer for MK64F12
+ */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCU activation
+   ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MK64F12_H_)  /* Check if memory map has not been already included */
+#define MK64F12_H_
+#define MCU_MK64F12
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+  #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0008u
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ *        bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ *        0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return  Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 102                /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_IRQn                    = 0,                /**< DMA Channel 0 Transfer Complete */
+  DMA1_IRQn                    = 1,                /**< DMA Channel 1 Transfer Complete */
+  DMA2_IRQn                    = 2,                /**< DMA Channel 2 Transfer Complete */
+  DMA3_IRQn                    = 3,                /**< DMA Channel 3 Transfer Complete */
+  DMA4_IRQn                    = 4,                /**< DMA Channel 4 Transfer Complete */
+  DMA5_IRQn                    = 5,                /**< DMA Channel 5 Transfer Complete */
+  DMA6_IRQn                    = 6,                /**< DMA Channel 6 Transfer Complete */
+  DMA7_IRQn                    = 7,                /**< DMA Channel 7 Transfer Complete */
+  DMA8_IRQn                    = 8,                /**< DMA Channel 8 Transfer Complete */
+  DMA9_IRQn                    = 9,                /**< DMA Channel 9 Transfer Complete */
+  DMA10_IRQn                   = 10,               /**< DMA Channel 10 Transfer Complete */
+  DMA11_IRQn                   = 11,               /**< DMA Channel 11 Transfer Complete */
+  DMA12_IRQn                   = 12,               /**< DMA Channel 12 Transfer Complete */
+  DMA13_IRQn                   = 13,               /**< DMA Channel 13 Transfer Complete */
+  DMA14_IRQn                   = 14,               /**< DMA Channel 14 Transfer Complete */
+  DMA15_IRQn                   = 15,               /**< DMA Channel 15 Transfer Complete */
+  DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
+  MCM_IRQn                     = 17,               /**< Normal Interrupt */
+  FTFE_IRQn                    = 18,               /**< FTFE Command complete interrupt */
+  Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
+  LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
+  LLWU_IRQn                    = 21,               /**< Low Leakage Wakeup Unit */
+  WDOG_EWM_IRQn                = 22,               /**< WDOG Interrupt */
+  RNG_IRQn                     = 23,               /**< RNG Interrupt */
+  I2C0_IRQn                    = 24,               /**< I2C0 interrupt */
+  I2C1_IRQn                    = 25,               /**< I2C1 interrupt */
+  SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
+  SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
+  I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
+  I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
+  UART0_LON_IRQn               = 30,               /**< UART0 LON interrupt */
+  UART0_RX_TX_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
+  UART0_ERR_IRQn               = 32,               /**< UART0 Error interrupt */
+  UART1_RX_TX_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
+  UART1_ERR_IRQn               = 34,               /**< UART1 Error interrupt */
+  UART2_RX_TX_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
+  UART2_ERR_IRQn               = 36,               /**< UART2 Error interrupt */
+  UART3_RX_TX_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
+  UART3_ERR_IRQn               = 38,               /**< UART3 Error interrupt */
+  ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
+  CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
+  FTM0_IRQn                    = 42,               /**< FTM0 fault, overflow and channels interrupt */
+  FTM1_IRQn                    = 43,               /**< FTM1 fault, overflow and channels interrupt */
+  FTM2_IRQn                    = 44,               /**< FTM2 fault, overflow and channels interrupt */
+  CMT_IRQn                     = 45,               /**< CMT interrupt */
+  RTC_IRQn                     = 46,               /**< RTC interrupt */
+  RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
+  PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
+  PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
+  PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
+  PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
+  PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
+  USB0_IRQn                    = 53,               /**< USB0 interrupt */
+  USBDCD_IRQn                  = 54,               /**< USBDCD Interrupt */
+  Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
+  DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
+  MCG_IRQn                     = 57,               /**< MCG Interrupt */
+  LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
+  PORTA_IRQn                   = 59,               /**< Port A interrupt */
+  PORTB_IRQn                   = 60,               /**< Port B interrupt */
+  PORTC_IRQn                   = 61,               /**< Port C interrupt */
+  PORTD_IRQn                   = 62,               /**< Port D interrupt */
+  PORTE_IRQn                   = 63,               /**< Port E interrupt */
+  SWI_IRQn                     = 64,               /**< Software interrupt */
+  SPI2_IRQn                    = 65,               /**< SPI2 Interrupt */
+  UART4_RX_TX_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
+  UART4_ERR_IRQn               = 67,               /**< UART4 Error interrupt */
+  UART5_RX_TX_IRQn             = 68,               /**< UART5 Receive/Transmit interrupt */
+  UART5_ERR_IRQn               = 69,               /**< UART5 Error interrupt */
+  CMP2_IRQn                    = 70,               /**< CMP2 interrupt */
+  FTM3_IRQn                    = 71,               /**< FTM3 fault, overflow and channels interrupt */
+  DAC1_IRQn                    = 72,               /**< DAC1 interrupt */
+  ADC1_IRQn                    = 73,               /**< ADC1 interrupt */
+  I2C2_IRQn                    = 74,               /**< I2C2 interrupt */
+  CAN0_ORed_Message_buffer_IRQn = 75,              /**< CAN0 OR'd message buffers interrupt */
+  CAN0_Bus_Off_IRQn            = 76,               /**< CAN0 bus off interrupt */
+  CAN0_Error_IRQn              = 77,               /**< CAN0 error interrupt */
+  CAN0_Tx_Warning_IRQn         = 78,               /**< CAN0 Tx warning interrupt */
+  CAN0_Rx_Warning_IRQn         = 79,               /**< CAN0 Rx warning interrupt */
+  CAN0_Wake_Up_IRQn            = 80,               /**< CAN0 wake up interrupt */
+  SDHC_IRQn                    = 81,               /**< SDHC interrupt */
+  ENET_1588_Timer_IRQn         = 82,               /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+  ENET_Transmit_IRQn           = 83,               /**< Ethernet MAC Transmit Interrupt */
+  ENET_Receive_IRQn            = 84,               /**< Ethernet MAC Receive Interrupt */
+  ENET_Error_IRQn              = 85                /**< Ethernet MAC Error and miscelaneous Interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_MK64F12.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index)                  ((base)->SC1[index])
+#define ADC_SC1_COUNT                            2
+#define ADC_CFG1_REG(base)                       ((base)->CFG1)
+#define ADC_CFG2_REG(base)                       ((base)->CFG2)
+#define ADC_R_REG(base,index)                    ((base)->R[index])
+#define ADC_R_COUNT                              2
+#define ADC_CV1_REG(base)                        ((base)->CV1)
+#define ADC_CV2_REG(base)                        ((base)->CV2)
+#define ADC_SC2_REG(base)                        ((base)->SC2)
+#define ADC_SC3_REG(base)                        ((base)->SC3)
+#define ADC_OFS_REG(base)                        ((base)->OFS)
+#define ADC_PG_REG(base)                         ((base)->PG)
+#define ADC_MG_REG(base)                         ((base)->MG)
+#define ADC_CLPD_REG(base)                       ((base)->CLPD)
+#define ADC_CLPS_REG(base)                       ((base)->CLPS)
+#define ADC_CLP4_REG(base)                       ((base)->CLP4)
+#define ADC_CLP3_REG(base)                       ((base)->CLP3)
+#define ADC_CLP2_REG(base)                       ((base)->CLP2)
+#define ADC_CLP1_REG(base)                       ((base)->CLP1)
+#define ADC_CLP0_REG(base)                       ((base)->CLP0)
+#define ADC_CLMD_REG(base)                       ((base)->CLMD)
+#define ADC_CLMS_REG(base)                       ((base)->CLMS)
+#define ADC_CLM4_REG(base)                       ((base)->CLM4)
+#define ADC_CLM3_REG(base)                       ((base)->CLM3)
+#define ADC_CLM2_REG(base)                       ((base)->CLM2)
+#define ADC_CLM1_REG(base)                       ((base)->CLM1)
+#define ADC_CLM0_REG(base)                       ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK                        0x1Fu
+#define ADC_SC1_ADCH_SHIFT                       0
+#define ADC_SC1_ADCH_WIDTH                       5
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        0x20u
+#define ADC_SC1_DIFF_SHIFT                       5
+#define ADC_SC1_DIFF_WIDTH                       1
+#define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK                        0x40u
+#define ADC_SC1_AIEN_SHIFT                       6
+#define ADC_SC1_AIEN_WIDTH                       1
+#define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK                        0x80u
+#define ADC_SC1_COCO_SHIFT                       7
+#define ADC_SC1_COCO_WIDTH                       1
+#define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK                     0x3u
+#define ADC_CFG1_ADICLK_SHIFT                    0
+#define ADC_CFG1_ADICLK_WIDTH                    2
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       0xCu
+#define ADC_CFG1_MODE_SHIFT                      2
+#define ADC_CFG1_MODE_WIDTH                      2
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     0x10u
+#define ADC_CFG1_ADLSMP_SHIFT                    4
+#define ADC_CFG1_ADLSMP_WIDTH                    1
+#define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK                       0x60u
+#define ADC_CFG1_ADIV_SHIFT                      5
+#define ADC_CFG1_ADIV_WIDTH                      2
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      0x80u
+#define ADC_CFG1_ADLPC_SHIFT                     7
+#define ADC_CFG1_ADLPC_WIDTH                     1
+#define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK                     0x3u
+#define ADC_CFG2_ADLSTS_SHIFT                    0
+#define ADC_CFG2_ADLSTS_WIDTH                    2
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      0x4u
+#define ADC_CFG2_ADHSC_SHIFT                     2
+#define ADC_CFG2_ADHSC_WIDTH                     1
+#define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK                    0x8u
+#define ADC_CFG2_ADACKEN_SHIFT                   3
+#define ADC_CFG2_ADACKEN_WIDTH                   1
+#define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK                     0x10u
+#define ADC_CFG2_MUXSEL_SHIFT                    4
+#define ADC_CFG2_MUXSEL_WIDTH                    1
+#define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
+/* R Bit Fields */
+#define ADC_R_D_MASK                             0xFFFFu
+#define ADC_R_D_SHIFT                            0
+#define ADC_R_D_WIDTH                            16
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK                          0xFFFFu
+#define ADC_CV1_CV_SHIFT                         0
+#define ADC_CV1_CV_WIDTH                         16
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK                          0xFFFFu
+#define ADC_CV2_CV_SHIFT                         0
+#define ADC_CV2_CV_WIDTH                         16
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK                      0x3u
+#define ADC_SC2_REFSEL_SHIFT                     0
+#define ADC_SC2_REFSEL_WIDTH                     2
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       0x4u
+#define ADC_SC2_DMAEN_SHIFT                      2
+#define ADC_SC2_DMAEN_WIDTH                      1
+#define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK                       0x8u
+#define ADC_SC2_ACREN_SHIFT                      3
+#define ADC_SC2_ACREN_WIDTH                      1
+#define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK                       0x10u
+#define ADC_SC2_ACFGT_SHIFT                      4
+#define ADC_SC2_ACFGT_WIDTH                      1
+#define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK                        0x20u
+#define ADC_SC2_ACFE_SHIFT                       5
+#define ADC_SC2_ACFE_WIDTH                       1
+#define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK                       0x40u
+#define ADC_SC2_ADTRG_SHIFT                      6
+#define ADC_SC2_ADTRG_WIDTH                      1
+#define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK                       0x80u
+#define ADC_SC2_ADACT_SHIFT                      7
+#define ADC_SC2_ADACT_WIDTH                      1
+#define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK                        0x3u
+#define ADC_SC3_AVGS_SHIFT                       0
+#define ADC_SC3_AVGS_WIDTH                       2
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        0x4u
+#define ADC_SC3_AVGE_SHIFT                       2
+#define ADC_SC3_AVGE_WIDTH                       1
+#define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK                        0x8u
+#define ADC_SC3_ADCO_SHIFT                       3
+#define ADC_SC3_ADCO_WIDTH                       1
+#define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK                        0x40u
+#define ADC_SC3_CALF_SHIFT                       6
+#define ADC_SC3_CALF_WIDTH                       1
+#define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK                         0x80u
+#define ADC_SC3_CAL_SHIFT                        7
+#define ADC_SC3_CAL_WIDTH                        1
+#define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK                         0xFFFFu
+#define ADC_OFS_OFS_SHIFT                        0
+#define ADC_OFS_OFS_WIDTH                        16
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK                           0xFFFFu
+#define ADC_PG_PG_SHIFT                          0
+#define ADC_PG_PG_WIDTH                          16
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK                           0xFFFFu
+#define ADC_MG_MG_SHIFT                          0
+#define ADC_MG_MG_WIDTH                          16
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK                       0x3Fu
+#define ADC_CLPD_CLPD_SHIFT                      0
+#define ADC_CLPD_CLPD_WIDTH                      6
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK                       0x3Fu
+#define ADC_CLPS_CLPS_SHIFT                      0
+#define ADC_CLPS_CLPS_WIDTH                      6
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK                       0x3FFu
+#define ADC_CLP4_CLP4_SHIFT                      0
+#define ADC_CLP4_CLP4_WIDTH                      10
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK                       0x1FFu
+#define ADC_CLP3_CLP3_SHIFT                      0
+#define ADC_CLP3_CLP3_WIDTH                      9
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK                       0xFFu
+#define ADC_CLP2_CLP2_SHIFT                      0
+#define ADC_CLP2_CLP2_WIDTH                      8
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK                       0x7Fu
+#define ADC_CLP1_CLP1_SHIFT                      0
+#define ADC_CLP1_CLP1_WIDTH                      7
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK                       0x3Fu
+#define ADC_CLP0_CLP0_SHIFT                      0
+#define ADC_CLP0_CLP0_WIDTH                      6
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK                       0x3Fu
+#define ADC_CLMD_CLMD_SHIFT                      0
+#define ADC_CLMD_CLMD_WIDTH                      6
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK                       0x3Fu
+#define ADC_CLMS_CLMS_SHIFT                      0
+#define ADC_CLMS_CLMS_WIDTH                      6
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK                       0x3FFu
+#define ADC_CLM4_CLM4_SHIFT                      0
+#define ADC_CLM4_CLM4_WIDTH                      10
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK                       0x1FFu
+#define ADC_CLM3_CLM3_SHIFT                      0
+#define ADC_CLM3_CLM3_WIDTH                      9
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK                       0xFFu
+#define ADC_CLM2_CLM2_SHIFT                      0
+#define ADC_CLM2_CLM2_WIDTH                      8
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK                       0x7Fu
+#define ADC_CLM1_CLM1_SHIFT                      0
+#define ADC_CLM1_CLM1_WIDTH                      7
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK                       0x3Fu
+#define ADC_CLM0_CLM0_SHIFT                      0
+#define ADC_CLM0_CLM0_WIDTH                      6
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR                            (ADC0)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_Type *)ADC1_BASE)
+#define ADC1_BASE_PTR                            (ADC1)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A                                ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B                                ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1                                ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2                                ADC_CFG2_REG(ADC0)
+#define ADC0_RA                                  ADC_R_REG(ADC0,0)
+#define ADC0_RB                                  ADC_R_REG(ADC0,1)
+#define ADC0_CV1                                 ADC_CV1_REG(ADC0)
+#define ADC0_CV2                                 ADC_CV2_REG(ADC0)
+#define ADC0_SC2                                 ADC_SC2_REG(ADC0)
+#define ADC0_SC3                                 ADC_SC3_REG(ADC0)
+#define ADC0_OFS                                 ADC_OFS_REG(ADC0)
+#define ADC0_PG                                  ADC_PG_REG(ADC0)
+#define ADC0_MG                                  ADC_MG_REG(ADC0)
+#define ADC0_CLPD                                ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS                                ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4                                ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3                                ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2                                ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1                                ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0                                ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD                                ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS                                ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4                                ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3                                ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2                                ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1                                ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0                                ADC_CLM0_REG(ADC0)
+/* ADC1 */
+#define ADC1_SC1A                                ADC_SC1_REG(ADC1,0)
+#define ADC1_SC1B                                ADC_SC1_REG(ADC1,1)
+#define ADC1_CFG1                                ADC_CFG1_REG(ADC1)
+#define ADC1_CFG2                                ADC_CFG2_REG(ADC1)
+#define ADC1_RA                                  ADC_R_REG(ADC1,0)
+#define ADC1_RB                                  ADC_R_REG(ADC1,1)
+#define ADC1_CV1                                 ADC_CV1_REG(ADC1)
+#define ADC1_CV2                                 ADC_CV2_REG(ADC1)
+#define ADC1_SC2                                 ADC_SC2_REG(ADC1)
+#define ADC1_SC3                                 ADC_SC3_REG(ADC1)
+#define ADC1_OFS                                 ADC_OFS_REG(ADC1)
+#define ADC1_PG                                  ADC_PG_REG(ADC1)
+#define ADC1_MG                                  ADC_MG_REG(ADC1)
+#define ADC1_CLPD                                ADC_CLPD_REG(ADC1)
+#define ADC1_CLPS                                ADC_CLPS_REG(ADC1)
+#define ADC1_CLP4                                ADC_CLP4_REG(ADC1)
+#define ADC1_CLP3                                ADC_CLP3_REG(ADC1)
+#define ADC1_CLP2                                ADC_CLP2_REG(ADC1)
+#define ADC1_CLP1                                ADC_CLP1_REG(ADC1)
+#define ADC1_CLP0                                ADC_CLP0_REG(ADC1)
+#define ADC1_CLMD                                ADC_CLMD_REG(ADC1)
+#define ADC1_CLMS                                ADC_CLMS_REG(ADC1)
+#define ADC1_CLM4                                ADC_CLM4_REG(ADC1)
+#define ADC1_CLM3                                ADC_CLM3_REG(ADC1)
+#define ADC1_CLM2                                ADC_CLM2_REG(ADC1)
+#define ADC1_CLM1                                ADC_CLM1_REG(ADC1)
+#define ADC1_CLM0                                ADC_CLM0_REG(ADC1)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index)                          ADC_SC1_REG(ADC0,index)
+#define ADC1_SC1(index)                          ADC_SC1_REG(ADC1,index)
+#define ADC0_R(index)                            ADC_R_REG(ADC0,index)
+#define ADC1_R(index)                            ADC_R_REG(ADC1,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPRA;                              /**< Master Privilege Register A, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PACRA;                             /**< Peripheral Access Control Register, offset: 0x20 */
+  __IO uint32_t PACRB;                             /**< Peripheral Access Control Register, offset: 0x24 */
+  __IO uint32_t PACRC;                             /**< Peripheral Access Control Register, offset: 0x28 */
+  __IO uint32_t PACRD;                             /**< Peripheral Access Control Register, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PACRE;                             /**< Peripheral Access Control Register, offset: 0x40 */
+  __IO uint32_t PACRF;                             /**< Peripheral Access Control Register, offset: 0x44 */
+  __IO uint32_t PACRG;                             /**< Peripheral Access Control Register, offset: 0x48 */
+  __IO uint32_t PACRH;                             /**< Peripheral Access Control Register, offset: 0x4C */
+  __IO uint32_t PACRI;                             /**< Peripheral Access Control Register, offset: 0x50 */
+  __IO uint32_t PACRJ;                             /**< Peripheral Access Control Register, offset: 0x54 */
+  __IO uint32_t PACRK;                             /**< Peripheral Access Control Register, offset: 0x58 */
+  __IO uint32_t PACRL;                             /**< Peripheral Access Control Register, offset: 0x5C */
+  __IO uint32_t PACRM;                             /**< Peripheral Access Control Register, offset: 0x60 */
+  __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
+  __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
+  __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t PACRU;                             /**< Peripheral Access Control Register, offset: 0x80 */
+} AIPS_Type, *AIPS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register accessors */
+#define AIPS_MPRA_REG(base)                      ((base)->MPRA)
+#define AIPS_PACRA_REG(base)                     ((base)->PACRA)
+#define AIPS_PACRB_REG(base)                     ((base)->PACRB)
+#define AIPS_PACRC_REG(base)                     ((base)->PACRC)
+#define AIPS_PACRD_REG(base)                     ((base)->PACRD)
+#define AIPS_PACRE_REG(base)                     ((base)->PACRE)
+#define AIPS_PACRF_REG(base)                     ((base)->PACRF)
+#define AIPS_PACRG_REG(base)                     ((base)->PACRG)
+#define AIPS_PACRH_REG(base)                     ((base)->PACRH)
+#define AIPS_PACRI_REG(base)                     ((base)->PACRI)
+#define AIPS_PACRJ_REG(base)                     ((base)->PACRJ)
+#define AIPS_PACRK_REG(base)                     ((base)->PACRK)
+#define AIPS_PACRL_REG(base)                     ((base)->PACRL)
+#define AIPS_PACRM_REG(base)                     ((base)->PACRM)
+#define AIPS_PACRN_REG(base)                     ((base)->PACRN)
+#define AIPS_PACRO_REG(base)                     ((base)->PACRO)
+#define AIPS_PACRP_REG(base)                     ((base)->PACRP)
+#define AIPS_PACRU_REG(base)                     ((base)->PACRU)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/* MPRA Bit Fields */
+#define AIPS_MPRA_MPL5_MASK                      0x100u
+#define AIPS_MPRA_MPL5_SHIFT                     8
+#define AIPS_MPRA_MPL5_WIDTH                     1
+#define AIPS_MPRA_MPL5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL5_SHIFT))&AIPS_MPRA_MPL5_MASK)
+#define AIPS_MPRA_MTW5_MASK                      0x200u
+#define AIPS_MPRA_MTW5_SHIFT                     9
+#define AIPS_MPRA_MTW5_WIDTH                     1
+#define AIPS_MPRA_MTW5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW5_SHIFT))&AIPS_MPRA_MTW5_MASK)
+#define AIPS_MPRA_MTR5_MASK                      0x400u
+#define AIPS_MPRA_MTR5_SHIFT                     10
+#define AIPS_MPRA_MTR5_WIDTH                     1
+#define AIPS_MPRA_MTR5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR5_SHIFT))&AIPS_MPRA_MTR5_MASK)
+#define AIPS_MPRA_MPL4_MASK                      0x1000u
+#define AIPS_MPRA_MPL4_SHIFT                     12
+#define AIPS_MPRA_MPL4_WIDTH                     1
+#define AIPS_MPRA_MPL4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL4_SHIFT))&AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MTW4_MASK                      0x2000u
+#define AIPS_MPRA_MTW4_SHIFT                     13
+#define AIPS_MPRA_MTW4_WIDTH                     1
+#define AIPS_MPRA_MTW4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW4_SHIFT))&AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTR4_MASK                      0x4000u
+#define AIPS_MPRA_MTR4_SHIFT                     14
+#define AIPS_MPRA_MTR4_WIDTH                     1
+#define AIPS_MPRA_MTR4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR4_SHIFT))&AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MPL3_MASK                      0x10000u
+#define AIPS_MPRA_MPL3_SHIFT                     16
+#define AIPS_MPRA_MPL3_WIDTH                     1
+#define AIPS_MPRA_MPL3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL3_SHIFT))&AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MTW3_MASK                      0x20000u
+#define AIPS_MPRA_MTW3_SHIFT                     17
+#define AIPS_MPRA_MTW3_WIDTH                     1
+#define AIPS_MPRA_MTW3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW3_SHIFT))&AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTR3_MASK                      0x40000u
+#define AIPS_MPRA_MTR3_SHIFT                     18
+#define AIPS_MPRA_MTR3_WIDTH                     1
+#define AIPS_MPRA_MTR3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR3_SHIFT))&AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MPL2_MASK                      0x100000u
+#define AIPS_MPRA_MPL2_SHIFT                     20
+#define AIPS_MPRA_MPL2_WIDTH                     1
+#define AIPS_MPRA_MPL2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL2_SHIFT))&AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MTW2_MASK                      0x200000u
+#define AIPS_MPRA_MTW2_SHIFT                     21
+#define AIPS_MPRA_MTW2_WIDTH                     1
+#define AIPS_MPRA_MTW2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW2_SHIFT))&AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTR2_MASK                      0x400000u
+#define AIPS_MPRA_MTR2_SHIFT                     22
+#define AIPS_MPRA_MTR2_WIDTH                     1
+#define AIPS_MPRA_MTR2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR2_SHIFT))&AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MPL1_MASK                      0x1000000u
+#define AIPS_MPRA_MPL1_SHIFT                     24
+#define AIPS_MPRA_MPL1_WIDTH                     1
+#define AIPS_MPRA_MPL1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL1_SHIFT))&AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MTW1_MASK                      0x2000000u
+#define AIPS_MPRA_MTW1_SHIFT                     25
+#define AIPS_MPRA_MTW1_WIDTH                     1
+#define AIPS_MPRA_MTW1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW1_SHIFT))&AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTR1_MASK                      0x4000000u
+#define AIPS_MPRA_MTR1_SHIFT                     26
+#define AIPS_MPRA_MTR1_WIDTH                     1
+#define AIPS_MPRA_MTR1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR1_SHIFT))&AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MPL0_MASK                      0x10000000u
+#define AIPS_MPRA_MPL0_SHIFT                     28
+#define AIPS_MPRA_MPL0_WIDTH                     1
+#define AIPS_MPRA_MPL0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL0_SHIFT))&AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MTW0_MASK                      0x20000000u
+#define AIPS_MPRA_MTW0_SHIFT                     29
+#define AIPS_MPRA_MTW0_WIDTH                     1
+#define AIPS_MPRA_MTW0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW0_SHIFT))&AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTR0_MASK                      0x40000000u
+#define AIPS_MPRA_MTR0_SHIFT                     30
+#define AIPS_MPRA_MTR0_WIDTH                     1
+#define AIPS_MPRA_MTR0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR0_SHIFT))&AIPS_MPRA_MTR0_MASK)
+/* PACRA Bit Fields */
+#define AIPS_PACRA_TP7_MASK                      0x1u
+#define AIPS_PACRA_TP7_SHIFT                     0
+#define AIPS_PACRA_TP7_WIDTH                     1
+#define AIPS_PACRA_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP7_SHIFT))&AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_WP7_MASK                      0x2u
+#define AIPS_PACRA_WP7_SHIFT                     1
+#define AIPS_PACRA_WP7_WIDTH                     1
+#define AIPS_PACRA_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP7_SHIFT))&AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_SP7_MASK                      0x4u
+#define AIPS_PACRA_SP7_SHIFT                     2
+#define AIPS_PACRA_SP7_WIDTH                     1
+#define AIPS_PACRA_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP7_SHIFT))&AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_TP6_MASK                      0x10u
+#define AIPS_PACRA_TP6_SHIFT                     4
+#define AIPS_PACRA_TP6_WIDTH                     1
+#define AIPS_PACRA_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP6_SHIFT))&AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_WP6_MASK                      0x20u
+#define AIPS_PACRA_WP6_SHIFT                     5
+#define AIPS_PACRA_WP6_WIDTH                     1
+#define AIPS_PACRA_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP6_SHIFT))&AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_SP6_MASK                      0x40u
+#define AIPS_PACRA_SP6_SHIFT                     6
+#define AIPS_PACRA_SP6_WIDTH                     1
+#define AIPS_PACRA_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP6_SHIFT))&AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_TP5_MASK                      0x100u
+#define AIPS_PACRA_TP5_SHIFT                     8
+#define AIPS_PACRA_TP5_WIDTH                     1
+#define AIPS_PACRA_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP5_SHIFT))&AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_WP5_MASK                      0x200u
+#define AIPS_PACRA_WP5_SHIFT                     9
+#define AIPS_PACRA_WP5_WIDTH                     1
+#define AIPS_PACRA_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP5_SHIFT))&AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_SP5_MASK                      0x400u
+#define AIPS_PACRA_SP5_SHIFT                     10
+#define AIPS_PACRA_SP5_WIDTH                     1
+#define AIPS_PACRA_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP5_SHIFT))&AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_TP4_MASK                      0x1000u
+#define AIPS_PACRA_TP4_SHIFT                     12
+#define AIPS_PACRA_TP4_WIDTH                     1
+#define AIPS_PACRA_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP4_SHIFT))&AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_WP4_MASK                      0x2000u
+#define AIPS_PACRA_WP4_SHIFT                     13
+#define AIPS_PACRA_WP4_WIDTH                     1
+#define AIPS_PACRA_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP4_SHIFT))&AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_SP4_MASK                      0x4000u
+#define AIPS_PACRA_SP4_SHIFT                     14
+#define AIPS_PACRA_SP4_WIDTH                     1
+#define AIPS_PACRA_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP4_SHIFT))&AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_TP3_MASK                      0x10000u
+#define AIPS_PACRA_TP3_SHIFT                     16
+#define AIPS_PACRA_TP3_WIDTH                     1
+#define AIPS_PACRA_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP3_SHIFT))&AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_WP3_MASK                      0x20000u
+#define AIPS_PACRA_WP3_SHIFT                     17
+#define AIPS_PACRA_WP3_WIDTH                     1
+#define AIPS_PACRA_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP3_SHIFT))&AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_SP3_MASK                      0x40000u
+#define AIPS_PACRA_SP3_SHIFT                     18
+#define AIPS_PACRA_SP3_WIDTH                     1
+#define AIPS_PACRA_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP3_SHIFT))&AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_TP2_MASK                      0x100000u
+#define AIPS_PACRA_TP2_SHIFT                     20
+#define AIPS_PACRA_TP2_WIDTH                     1
+#define AIPS_PACRA_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP2_SHIFT))&AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_WP2_MASK                      0x200000u
+#define AIPS_PACRA_WP2_SHIFT                     21
+#define AIPS_PACRA_WP2_WIDTH                     1
+#define AIPS_PACRA_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP2_SHIFT))&AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_SP2_MASK                      0x400000u
+#define AIPS_PACRA_SP2_SHIFT                     22
+#define AIPS_PACRA_SP2_WIDTH                     1
+#define AIPS_PACRA_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP2_SHIFT))&AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_TP1_MASK                      0x1000000u
+#define AIPS_PACRA_TP1_SHIFT                     24
+#define AIPS_PACRA_TP1_WIDTH                     1
+#define AIPS_PACRA_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP1_SHIFT))&AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_WP1_MASK                      0x2000000u
+#define AIPS_PACRA_WP1_SHIFT                     25
+#define AIPS_PACRA_WP1_WIDTH                     1
+#define AIPS_PACRA_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP1_SHIFT))&AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_SP1_MASK                      0x4000000u
+#define AIPS_PACRA_SP1_SHIFT                     26
+#define AIPS_PACRA_SP1_WIDTH                     1
+#define AIPS_PACRA_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP1_SHIFT))&AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_TP0_MASK                      0x10000000u
+#define AIPS_PACRA_TP0_SHIFT                     28
+#define AIPS_PACRA_TP0_WIDTH                     1
+#define AIPS_PACRA_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP0_SHIFT))&AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_WP0_MASK                      0x20000000u
+#define AIPS_PACRA_WP0_SHIFT                     29
+#define AIPS_PACRA_WP0_WIDTH                     1
+#define AIPS_PACRA_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP0_SHIFT))&AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_SP0_MASK                      0x40000000u
+#define AIPS_PACRA_SP0_SHIFT                     30
+#define AIPS_PACRA_SP0_WIDTH                     1
+#define AIPS_PACRA_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP0_SHIFT))&AIPS_PACRA_SP0_MASK)
+/* PACRB Bit Fields */
+#define AIPS_PACRB_TP7_MASK                      0x1u
+#define AIPS_PACRB_TP7_SHIFT                     0
+#define AIPS_PACRB_TP7_WIDTH                     1
+#define AIPS_PACRB_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP7_SHIFT))&AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_WP7_MASK                      0x2u
+#define AIPS_PACRB_WP7_SHIFT                     1
+#define AIPS_PACRB_WP7_WIDTH                     1
+#define AIPS_PACRB_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP7_SHIFT))&AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_SP7_MASK                      0x4u
+#define AIPS_PACRB_SP7_SHIFT                     2
+#define AIPS_PACRB_SP7_WIDTH                     1
+#define AIPS_PACRB_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP7_SHIFT))&AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_TP6_MASK                      0x10u
+#define AIPS_PACRB_TP6_SHIFT                     4
+#define AIPS_PACRB_TP6_WIDTH                     1
+#define AIPS_PACRB_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP6_SHIFT))&AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_WP6_MASK                      0x20u
+#define AIPS_PACRB_WP6_SHIFT                     5
+#define AIPS_PACRB_WP6_WIDTH                     1
+#define AIPS_PACRB_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP6_SHIFT))&AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_SP6_MASK                      0x40u
+#define AIPS_PACRB_SP6_SHIFT                     6
+#define AIPS_PACRB_SP6_WIDTH                     1
+#define AIPS_PACRB_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP6_SHIFT))&AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_TP5_MASK                      0x100u
+#define AIPS_PACRB_TP5_SHIFT                     8
+#define AIPS_PACRB_TP5_WIDTH                     1
+#define AIPS_PACRB_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP5_SHIFT))&AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_WP5_MASK                      0x200u
+#define AIPS_PACRB_WP5_SHIFT                     9
+#define AIPS_PACRB_WP5_WIDTH                     1
+#define AIPS_PACRB_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP5_SHIFT))&AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_SP5_MASK                      0x400u
+#define AIPS_PACRB_SP5_SHIFT                     10
+#define AIPS_PACRB_SP5_WIDTH                     1
+#define AIPS_PACRB_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP5_SHIFT))&AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_TP4_MASK                      0x1000u
+#define AIPS_PACRB_TP4_SHIFT                     12
+#define AIPS_PACRB_TP4_WIDTH                     1
+#define AIPS_PACRB_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP4_SHIFT))&AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_WP4_MASK                      0x2000u
+#define AIPS_PACRB_WP4_SHIFT                     13
+#define AIPS_PACRB_WP4_WIDTH                     1
+#define AIPS_PACRB_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP4_SHIFT))&AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_SP4_MASK                      0x4000u
+#define AIPS_PACRB_SP4_SHIFT                     14
+#define AIPS_PACRB_SP4_WIDTH                     1
+#define AIPS_PACRB_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP4_SHIFT))&AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_TP3_MASK                      0x10000u
+#define AIPS_PACRB_TP3_SHIFT                     16
+#define AIPS_PACRB_TP3_WIDTH                     1
+#define AIPS_PACRB_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP3_SHIFT))&AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_WP3_MASK                      0x20000u
+#define AIPS_PACRB_WP3_SHIFT                     17
+#define AIPS_PACRB_WP3_WIDTH                     1
+#define AIPS_PACRB_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP3_SHIFT))&AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_SP3_MASK                      0x40000u
+#define AIPS_PACRB_SP3_SHIFT                     18
+#define AIPS_PACRB_SP3_WIDTH                     1
+#define AIPS_PACRB_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP3_SHIFT))&AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_TP2_MASK                      0x100000u
+#define AIPS_PACRB_TP2_SHIFT                     20
+#define AIPS_PACRB_TP2_WIDTH                     1
+#define AIPS_PACRB_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP2_SHIFT))&AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_WP2_MASK                      0x200000u
+#define AIPS_PACRB_WP2_SHIFT                     21
+#define AIPS_PACRB_WP2_WIDTH                     1
+#define AIPS_PACRB_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP2_SHIFT))&AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_SP2_MASK                      0x400000u
+#define AIPS_PACRB_SP2_SHIFT                     22
+#define AIPS_PACRB_SP2_WIDTH                     1
+#define AIPS_PACRB_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP2_SHIFT))&AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_TP1_MASK                      0x1000000u
+#define AIPS_PACRB_TP1_SHIFT                     24
+#define AIPS_PACRB_TP1_WIDTH                     1
+#define AIPS_PACRB_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP1_SHIFT))&AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_WP1_MASK                      0x2000000u
+#define AIPS_PACRB_WP1_SHIFT                     25
+#define AIPS_PACRB_WP1_WIDTH                     1
+#define AIPS_PACRB_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP1_SHIFT))&AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_SP1_MASK                      0x4000000u
+#define AIPS_PACRB_SP1_SHIFT                     26
+#define AIPS_PACRB_SP1_WIDTH                     1
+#define AIPS_PACRB_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP1_SHIFT))&AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_TP0_MASK                      0x10000000u
+#define AIPS_PACRB_TP0_SHIFT                     28
+#define AIPS_PACRB_TP0_WIDTH                     1
+#define AIPS_PACRB_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP0_SHIFT))&AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_WP0_MASK                      0x20000000u
+#define AIPS_PACRB_WP0_SHIFT                     29
+#define AIPS_PACRB_WP0_WIDTH                     1
+#define AIPS_PACRB_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP0_SHIFT))&AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_SP0_MASK                      0x40000000u
+#define AIPS_PACRB_SP0_SHIFT                     30
+#define AIPS_PACRB_SP0_WIDTH                     1
+#define AIPS_PACRB_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP0_SHIFT))&AIPS_PACRB_SP0_MASK)
+/* PACRC Bit Fields */
+#define AIPS_PACRC_TP7_MASK                      0x1u
+#define AIPS_PACRC_TP7_SHIFT                     0
+#define AIPS_PACRC_TP7_WIDTH                     1
+#define AIPS_PACRC_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP7_SHIFT))&AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_WP7_MASK                      0x2u
+#define AIPS_PACRC_WP7_SHIFT                     1
+#define AIPS_PACRC_WP7_WIDTH                     1
+#define AIPS_PACRC_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP7_SHIFT))&AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_SP7_MASK                      0x4u
+#define AIPS_PACRC_SP7_SHIFT                     2
+#define AIPS_PACRC_SP7_WIDTH                     1
+#define AIPS_PACRC_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP7_SHIFT))&AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_TP6_MASK                      0x10u
+#define AIPS_PACRC_TP6_SHIFT                     4
+#define AIPS_PACRC_TP6_WIDTH                     1
+#define AIPS_PACRC_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP6_SHIFT))&AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_WP6_MASK                      0x20u
+#define AIPS_PACRC_WP6_SHIFT                     5
+#define AIPS_PACRC_WP6_WIDTH                     1
+#define AIPS_PACRC_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP6_SHIFT))&AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_SP6_MASK                      0x40u
+#define AIPS_PACRC_SP6_SHIFT                     6
+#define AIPS_PACRC_SP6_WIDTH                     1
+#define AIPS_PACRC_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP6_SHIFT))&AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_TP5_MASK                      0x100u
+#define AIPS_PACRC_TP5_SHIFT                     8
+#define AIPS_PACRC_TP5_WIDTH                     1
+#define AIPS_PACRC_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP5_SHIFT))&AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_WP5_MASK                      0x200u
+#define AIPS_PACRC_WP5_SHIFT                     9
+#define AIPS_PACRC_WP5_WIDTH                     1
+#define AIPS_PACRC_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP5_SHIFT))&AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_SP5_MASK                      0x400u
+#define AIPS_PACRC_SP5_SHIFT                     10
+#define AIPS_PACRC_SP5_WIDTH                     1
+#define AIPS_PACRC_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP5_SHIFT))&AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_TP4_MASK                      0x1000u
+#define AIPS_PACRC_TP4_SHIFT                     12
+#define AIPS_PACRC_TP4_WIDTH                     1
+#define AIPS_PACRC_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP4_SHIFT))&AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_WP4_MASK                      0x2000u
+#define AIPS_PACRC_WP4_SHIFT                     13
+#define AIPS_PACRC_WP4_WIDTH                     1
+#define AIPS_PACRC_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP4_SHIFT))&AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_SP4_MASK                      0x4000u
+#define AIPS_PACRC_SP4_SHIFT                     14
+#define AIPS_PACRC_SP4_WIDTH                     1
+#define AIPS_PACRC_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP4_SHIFT))&AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_TP3_MASK                      0x10000u
+#define AIPS_PACRC_TP3_SHIFT                     16
+#define AIPS_PACRC_TP3_WIDTH                     1
+#define AIPS_PACRC_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP3_SHIFT))&AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_WP3_MASK                      0x20000u
+#define AIPS_PACRC_WP3_SHIFT                     17
+#define AIPS_PACRC_WP3_WIDTH                     1
+#define AIPS_PACRC_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP3_SHIFT))&AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_SP3_MASK                      0x40000u
+#define AIPS_PACRC_SP3_SHIFT                     18
+#define AIPS_PACRC_SP3_WIDTH                     1
+#define AIPS_PACRC_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP3_SHIFT))&AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_TP2_MASK                      0x100000u
+#define AIPS_PACRC_TP2_SHIFT                     20
+#define AIPS_PACRC_TP2_WIDTH                     1
+#define AIPS_PACRC_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP2_SHIFT))&AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_WP2_MASK                      0x200000u
+#define AIPS_PACRC_WP2_SHIFT                     21
+#define AIPS_PACRC_WP2_WIDTH                     1
+#define AIPS_PACRC_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP2_SHIFT))&AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_SP2_MASK                      0x400000u
+#define AIPS_PACRC_SP2_SHIFT                     22
+#define AIPS_PACRC_SP2_WIDTH                     1
+#define AIPS_PACRC_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP2_SHIFT))&AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_TP1_MASK                      0x1000000u
+#define AIPS_PACRC_TP1_SHIFT                     24
+#define AIPS_PACRC_TP1_WIDTH                     1
+#define AIPS_PACRC_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP1_SHIFT))&AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_WP1_MASK                      0x2000000u
+#define AIPS_PACRC_WP1_SHIFT                     25
+#define AIPS_PACRC_WP1_WIDTH                     1
+#define AIPS_PACRC_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP1_SHIFT))&AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_SP1_MASK                      0x4000000u
+#define AIPS_PACRC_SP1_SHIFT                     26
+#define AIPS_PACRC_SP1_WIDTH                     1
+#define AIPS_PACRC_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP1_SHIFT))&AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_TP0_MASK                      0x10000000u
+#define AIPS_PACRC_TP0_SHIFT                     28
+#define AIPS_PACRC_TP0_WIDTH                     1
+#define AIPS_PACRC_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP0_SHIFT))&AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_WP0_MASK                      0x20000000u
+#define AIPS_PACRC_WP0_SHIFT                     29
+#define AIPS_PACRC_WP0_WIDTH                     1
+#define AIPS_PACRC_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP0_SHIFT))&AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_SP0_MASK                      0x40000000u
+#define AIPS_PACRC_SP0_SHIFT                     30
+#define AIPS_PACRC_SP0_WIDTH                     1
+#define AIPS_PACRC_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP0_SHIFT))&AIPS_PACRC_SP0_MASK)
+/* PACRD Bit Fields */
+#define AIPS_PACRD_TP7_MASK                      0x1u
+#define AIPS_PACRD_TP7_SHIFT                     0
+#define AIPS_PACRD_TP7_WIDTH                     1
+#define AIPS_PACRD_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP7_SHIFT))&AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_WP7_MASK                      0x2u
+#define AIPS_PACRD_WP7_SHIFT                     1
+#define AIPS_PACRD_WP7_WIDTH                     1
+#define AIPS_PACRD_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP7_SHIFT))&AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_SP7_MASK                      0x4u
+#define AIPS_PACRD_SP7_SHIFT                     2
+#define AIPS_PACRD_SP7_WIDTH                     1
+#define AIPS_PACRD_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP7_SHIFT))&AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_TP6_MASK                      0x10u
+#define AIPS_PACRD_TP6_SHIFT                     4
+#define AIPS_PACRD_TP6_WIDTH                     1
+#define AIPS_PACRD_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP6_SHIFT))&AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_WP6_MASK                      0x20u
+#define AIPS_PACRD_WP6_SHIFT                     5
+#define AIPS_PACRD_WP6_WIDTH                     1
+#define AIPS_PACRD_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP6_SHIFT))&AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_SP6_MASK                      0x40u
+#define AIPS_PACRD_SP6_SHIFT                     6
+#define AIPS_PACRD_SP6_WIDTH                     1
+#define AIPS_PACRD_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP6_SHIFT))&AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_TP5_MASK                      0x100u
+#define AIPS_PACRD_TP5_SHIFT                     8
+#define AIPS_PACRD_TP5_WIDTH                     1
+#define AIPS_PACRD_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP5_SHIFT))&AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_WP5_MASK                      0x200u
+#define AIPS_PACRD_WP5_SHIFT                     9
+#define AIPS_PACRD_WP5_WIDTH                     1
+#define AIPS_PACRD_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP5_SHIFT))&AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_SP5_MASK                      0x400u
+#define AIPS_PACRD_SP5_SHIFT                     10
+#define AIPS_PACRD_SP5_WIDTH                     1
+#define AIPS_PACRD_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP5_SHIFT))&AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_TP4_MASK                      0x1000u
+#define AIPS_PACRD_TP4_SHIFT                     12
+#define AIPS_PACRD_TP4_WIDTH                     1
+#define AIPS_PACRD_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP4_SHIFT))&AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_WP4_MASK                      0x2000u
+#define AIPS_PACRD_WP4_SHIFT                     13
+#define AIPS_PACRD_WP4_WIDTH                     1
+#define AIPS_PACRD_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP4_SHIFT))&AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_SP4_MASK                      0x4000u
+#define AIPS_PACRD_SP4_SHIFT                     14
+#define AIPS_PACRD_SP4_WIDTH                     1
+#define AIPS_PACRD_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP4_SHIFT))&AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_TP3_MASK                      0x10000u
+#define AIPS_PACRD_TP3_SHIFT                     16
+#define AIPS_PACRD_TP3_WIDTH                     1
+#define AIPS_PACRD_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP3_SHIFT))&AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_WP3_MASK                      0x20000u
+#define AIPS_PACRD_WP3_SHIFT                     17
+#define AIPS_PACRD_WP3_WIDTH                     1
+#define AIPS_PACRD_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP3_SHIFT))&AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_SP3_MASK                      0x40000u
+#define AIPS_PACRD_SP3_SHIFT                     18
+#define AIPS_PACRD_SP3_WIDTH                     1
+#define AIPS_PACRD_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP3_SHIFT))&AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_TP2_MASK                      0x100000u
+#define AIPS_PACRD_TP2_SHIFT                     20
+#define AIPS_PACRD_TP2_WIDTH                     1
+#define AIPS_PACRD_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP2_SHIFT))&AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_WP2_MASK                      0x200000u
+#define AIPS_PACRD_WP2_SHIFT                     21
+#define AIPS_PACRD_WP2_WIDTH                     1
+#define AIPS_PACRD_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP2_SHIFT))&AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_SP2_MASK                      0x400000u
+#define AIPS_PACRD_SP2_SHIFT                     22
+#define AIPS_PACRD_SP2_WIDTH                     1
+#define AIPS_PACRD_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP2_SHIFT))&AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_TP1_MASK                      0x1000000u
+#define AIPS_PACRD_TP1_SHIFT                     24
+#define AIPS_PACRD_TP1_WIDTH                     1
+#define AIPS_PACRD_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP1_SHIFT))&AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_WP1_MASK                      0x2000000u
+#define AIPS_PACRD_WP1_SHIFT                     25
+#define AIPS_PACRD_WP1_WIDTH                     1
+#define AIPS_PACRD_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP1_SHIFT))&AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_SP1_MASK                      0x4000000u
+#define AIPS_PACRD_SP1_SHIFT                     26
+#define AIPS_PACRD_SP1_WIDTH                     1
+#define AIPS_PACRD_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP1_SHIFT))&AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_TP0_MASK                      0x10000000u
+#define AIPS_PACRD_TP0_SHIFT                     28
+#define AIPS_PACRD_TP0_WIDTH                     1
+#define AIPS_PACRD_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP0_SHIFT))&AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_WP0_MASK                      0x20000000u
+#define AIPS_PACRD_WP0_SHIFT                     29
+#define AIPS_PACRD_WP0_WIDTH                     1
+#define AIPS_PACRD_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP0_SHIFT))&AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_SP0_MASK                      0x40000000u
+#define AIPS_PACRD_SP0_SHIFT                     30
+#define AIPS_PACRD_SP0_WIDTH                     1
+#define AIPS_PACRD_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP0_SHIFT))&AIPS_PACRD_SP0_MASK)
+/* PACRE Bit Fields */
+#define AIPS_PACRE_TP7_MASK                      0x1u
+#define AIPS_PACRE_TP7_SHIFT                     0
+#define AIPS_PACRE_TP7_WIDTH                     1
+#define AIPS_PACRE_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP7_SHIFT))&AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_WP7_MASK                      0x2u
+#define AIPS_PACRE_WP7_SHIFT                     1
+#define AIPS_PACRE_WP7_WIDTH                     1
+#define AIPS_PACRE_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP7_SHIFT))&AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_SP7_MASK                      0x4u
+#define AIPS_PACRE_SP7_SHIFT                     2
+#define AIPS_PACRE_SP7_WIDTH                     1
+#define AIPS_PACRE_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP7_SHIFT))&AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_TP6_MASK                      0x10u
+#define AIPS_PACRE_TP6_SHIFT                     4
+#define AIPS_PACRE_TP6_WIDTH                     1
+#define AIPS_PACRE_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP6_SHIFT))&AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_WP6_MASK                      0x20u
+#define AIPS_PACRE_WP6_SHIFT                     5
+#define AIPS_PACRE_WP6_WIDTH                     1
+#define AIPS_PACRE_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP6_SHIFT))&AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_SP6_MASK                      0x40u
+#define AIPS_PACRE_SP6_SHIFT                     6
+#define AIPS_PACRE_SP6_WIDTH                     1
+#define AIPS_PACRE_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP6_SHIFT))&AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_TP5_MASK                      0x100u
+#define AIPS_PACRE_TP5_SHIFT                     8
+#define AIPS_PACRE_TP5_WIDTH                     1
+#define AIPS_PACRE_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP5_SHIFT))&AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_WP5_MASK                      0x200u
+#define AIPS_PACRE_WP5_SHIFT                     9
+#define AIPS_PACRE_WP5_WIDTH                     1
+#define AIPS_PACRE_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP5_SHIFT))&AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_SP5_MASK                      0x400u
+#define AIPS_PACRE_SP5_SHIFT                     10
+#define AIPS_PACRE_SP5_WIDTH                     1
+#define AIPS_PACRE_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP5_SHIFT))&AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_TP4_MASK                      0x1000u
+#define AIPS_PACRE_TP4_SHIFT                     12
+#define AIPS_PACRE_TP4_WIDTH                     1
+#define AIPS_PACRE_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP4_SHIFT))&AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_WP4_MASK                      0x2000u
+#define AIPS_PACRE_WP4_SHIFT                     13
+#define AIPS_PACRE_WP4_WIDTH                     1
+#define AIPS_PACRE_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP4_SHIFT))&AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_SP4_MASK                      0x4000u
+#define AIPS_PACRE_SP4_SHIFT                     14
+#define AIPS_PACRE_SP4_WIDTH                     1
+#define AIPS_PACRE_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP4_SHIFT))&AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_TP3_MASK                      0x10000u
+#define AIPS_PACRE_TP3_SHIFT                     16
+#define AIPS_PACRE_TP3_WIDTH                     1
+#define AIPS_PACRE_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP3_SHIFT))&AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_WP3_MASK                      0x20000u
+#define AIPS_PACRE_WP3_SHIFT                     17
+#define AIPS_PACRE_WP3_WIDTH                     1
+#define AIPS_PACRE_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP3_SHIFT))&AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_SP3_MASK                      0x40000u
+#define AIPS_PACRE_SP3_SHIFT                     18
+#define AIPS_PACRE_SP3_WIDTH                     1
+#define AIPS_PACRE_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP3_SHIFT))&AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_TP2_MASK                      0x100000u
+#define AIPS_PACRE_TP2_SHIFT                     20
+#define AIPS_PACRE_TP2_WIDTH                     1
+#define AIPS_PACRE_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP2_SHIFT))&AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_WP2_MASK                      0x200000u
+#define AIPS_PACRE_WP2_SHIFT                     21
+#define AIPS_PACRE_WP2_WIDTH                     1
+#define AIPS_PACRE_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP2_SHIFT))&AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_SP2_MASK                      0x400000u
+#define AIPS_PACRE_SP2_SHIFT                     22
+#define AIPS_PACRE_SP2_WIDTH                     1
+#define AIPS_PACRE_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP2_SHIFT))&AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_TP1_MASK                      0x1000000u
+#define AIPS_PACRE_TP1_SHIFT                     24
+#define AIPS_PACRE_TP1_WIDTH                     1
+#define AIPS_PACRE_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP1_SHIFT))&AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_WP1_MASK                      0x2000000u
+#define AIPS_PACRE_WP1_SHIFT                     25
+#define AIPS_PACRE_WP1_WIDTH                     1
+#define AIPS_PACRE_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP1_SHIFT))&AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_SP1_MASK                      0x4000000u
+#define AIPS_PACRE_SP1_SHIFT                     26
+#define AIPS_PACRE_SP1_WIDTH                     1
+#define AIPS_PACRE_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP1_SHIFT))&AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_TP0_MASK                      0x10000000u
+#define AIPS_PACRE_TP0_SHIFT                     28
+#define AIPS_PACRE_TP0_WIDTH                     1
+#define AIPS_PACRE_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP0_SHIFT))&AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_WP0_MASK                      0x20000000u
+#define AIPS_PACRE_WP0_SHIFT                     29
+#define AIPS_PACRE_WP0_WIDTH                     1
+#define AIPS_PACRE_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP0_SHIFT))&AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_SP0_MASK                      0x40000000u
+#define AIPS_PACRE_SP0_SHIFT                     30
+#define AIPS_PACRE_SP0_WIDTH                     1
+#define AIPS_PACRE_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP0_SHIFT))&AIPS_PACRE_SP0_MASK)
+/* PACRF Bit Fields */
+#define AIPS_PACRF_TP7_MASK                      0x1u
+#define AIPS_PACRF_TP7_SHIFT                     0
+#define AIPS_PACRF_TP7_WIDTH                     1
+#define AIPS_PACRF_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP7_SHIFT))&AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_WP7_MASK                      0x2u
+#define AIPS_PACRF_WP7_SHIFT                     1
+#define AIPS_PACRF_WP7_WIDTH                     1
+#define AIPS_PACRF_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP7_SHIFT))&AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_SP7_MASK                      0x4u
+#define AIPS_PACRF_SP7_SHIFT                     2
+#define AIPS_PACRF_SP7_WIDTH                     1
+#define AIPS_PACRF_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP7_SHIFT))&AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_TP6_MASK                      0x10u
+#define AIPS_PACRF_TP6_SHIFT                     4
+#define AIPS_PACRF_TP6_WIDTH                     1
+#define AIPS_PACRF_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP6_SHIFT))&AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_WP6_MASK                      0x20u
+#define AIPS_PACRF_WP6_SHIFT                     5
+#define AIPS_PACRF_WP6_WIDTH                     1
+#define AIPS_PACRF_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP6_SHIFT))&AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_SP6_MASK                      0x40u
+#define AIPS_PACRF_SP6_SHIFT                     6
+#define AIPS_PACRF_SP6_WIDTH                     1
+#define AIPS_PACRF_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP6_SHIFT))&AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_TP5_MASK                      0x100u
+#define AIPS_PACRF_TP5_SHIFT                     8
+#define AIPS_PACRF_TP5_WIDTH                     1
+#define AIPS_PACRF_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP5_SHIFT))&AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_WP5_MASK                      0x200u
+#define AIPS_PACRF_WP5_SHIFT                     9
+#define AIPS_PACRF_WP5_WIDTH                     1
+#define AIPS_PACRF_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP5_SHIFT))&AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_SP5_MASK                      0x400u
+#define AIPS_PACRF_SP5_SHIFT                     10
+#define AIPS_PACRF_SP5_WIDTH                     1
+#define AIPS_PACRF_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP5_SHIFT))&AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_TP4_MASK                      0x1000u
+#define AIPS_PACRF_TP4_SHIFT                     12
+#define AIPS_PACRF_TP4_WIDTH                     1
+#define AIPS_PACRF_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP4_SHIFT))&AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_WP4_MASK                      0x2000u
+#define AIPS_PACRF_WP4_SHIFT                     13
+#define AIPS_PACRF_WP4_WIDTH                     1
+#define AIPS_PACRF_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP4_SHIFT))&AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_SP4_MASK                      0x4000u
+#define AIPS_PACRF_SP4_SHIFT                     14
+#define AIPS_PACRF_SP4_WIDTH                     1
+#define AIPS_PACRF_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP4_SHIFT))&AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_TP3_MASK                      0x10000u
+#define AIPS_PACRF_TP3_SHIFT                     16
+#define AIPS_PACRF_TP3_WIDTH                     1
+#define AIPS_PACRF_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP3_SHIFT))&AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_WP3_MASK                      0x20000u
+#define AIPS_PACRF_WP3_SHIFT                     17
+#define AIPS_PACRF_WP3_WIDTH                     1
+#define AIPS_PACRF_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP3_SHIFT))&AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_SP3_MASK                      0x40000u
+#define AIPS_PACRF_SP3_SHIFT                     18
+#define AIPS_PACRF_SP3_WIDTH                     1
+#define AIPS_PACRF_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP3_SHIFT))&AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_TP2_MASK                      0x100000u
+#define AIPS_PACRF_TP2_SHIFT                     20
+#define AIPS_PACRF_TP2_WIDTH                     1
+#define AIPS_PACRF_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP2_SHIFT))&AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_WP2_MASK                      0x200000u
+#define AIPS_PACRF_WP2_SHIFT                     21
+#define AIPS_PACRF_WP2_WIDTH                     1
+#define AIPS_PACRF_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP2_SHIFT))&AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_SP2_MASK                      0x400000u
+#define AIPS_PACRF_SP2_SHIFT                     22
+#define AIPS_PACRF_SP2_WIDTH                     1
+#define AIPS_PACRF_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP2_SHIFT))&AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_TP1_MASK                      0x1000000u
+#define AIPS_PACRF_TP1_SHIFT                     24
+#define AIPS_PACRF_TP1_WIDTH                     1
+#define AIPS_PACRF_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP1_SHIFT))&AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_WP1_MASK                      0x2000000u
+#define AIPS_PACRF_WP1_SHIFT                     25
+#define AIPS_PACRF_WP1_WIDTH                     1
+#define AIPS_PACRF_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP1_SHIFT))&AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_SP1_MASK                      0x4000000u
+#define AIPS_PACRF_SP1_SHIFT                     26
+#define AIPS_PACRF_SP1_WIDTH                     1
+#define AIPS_PACRF_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP1_SHIFT))&AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_TP0_MASK                      0x10000000u
+#define AIPS_PACRF_TP0_SHIFT                     28
+#define AIPS_PACRF_TP0_WIDTH                     1
+#define AIPS_PACRF_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP0_SHIFT))&AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_WP0_MASK                      0x20000000u
+#define AIPS_PACRF_WP0_SHIFT                     29
+#define AIPS_PACRF_WP0_WIDTH                     1
+#define AIPS_PACRF_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP0_SHIFT))&AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_SP0_MASK                      0x40000000u
+#define AIPS_PACRF_SP0_SHIFT                     30
+#define AIPS_PACRF_SP0_WIDTH                     1
+#define AIPS_PACRF_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP0_SHIFT))&AIPS_PACRF_SP0_MASK)
+/* PACRG Bit Fields */
+#define AIPS_PACRG_TP7_MASK                      0x1u
+#define AIPS_PACRG_TP7_SHIFT                     0
+#define AIPS_PACRG_TP7_WIDTH                     1
+#define AIPS_PACRG_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP7_SHIFT))&AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_WP7_MASK                      0x2u
+#define AIPS_PACRG_WP7_SHIFT                     1
+#define AIPS_PACRG_WP7_WIDTH                     1
+#define AIPS_PACRG_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP7_SHIFT))&AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_SP7_MASK                      0x4u
+#define AIPS_PACRG_SP7_SHIFT                     2
+#define AIPS_PACRG_SP7_WIDTH                     1
+#define AIPS_PACRG_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP7_SHIFT))&AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_TP6_MASK                      0x10u
+#define AIPS_PACRG_TP6_SHIFT                     4
+#define AIPS_PACRG_TP6_WIDTH                     1
+#define AIPS_PACRG_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP6_SHIFT))&AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_WP6_MASK                      0x20u
+#define AIPS_PACRG_WP6_SHIFT                     5
+#define AIPS_PACRG_WP6_WIDTH                     1
+#define AIPS_PACRG_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP6_SHIFT))&AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_SP6_MASK                      0x40u
+#define AIPS_PACRG_SP6_SHIFT                     6
+#define AIPS_PACRG_SP6_WIDTH                     1
+#define AIPS_PACRG_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP6_SHIFT))&AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_TP5_MASK                      0x100u
+#define AIPS_PACRG_TP5_SHIFT                     8
+#define AIPS_PACRG_TP5_WIDTH                     1
+#define AIPS_PACRG_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP5_SHIFT))&AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_WP5_MASK                      0x200u
+#define AIPS_PACRG_WP5_SHIFT                     9
+#define AIPS_PACRG_WP5_WIDTH                     1
+#define AIPS_PACRG_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP5_SHIFT))&AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_SP5_MASK                      0x400u
+#define AIPS_PACRG_SP5_SHIFT                     10
+#define AIPS_PACRG_SP5_WIDTH                     1
+#define AIPS_PACRG_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP5_SHIFT))&AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_TP4_MASK                      0x1000u
+#define AIPS_PACRG_TP4_SHIFT                     12
+#define AIPS_PACRG_TP4_WIDTH                     1
+#define AIPS_PACRG_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP4_SHIFT))&AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_WP4_MASK                      0x2000u
+#define AIPS_PACRG_WP4_SHIFT                     13
+#define AIPS_PACRG_WP4_WIDTH                     1
+#define AIPS_PACRG_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP4_SHIFT))&AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_SP4_MASK                      0x4000u
+#define AIPS_PACRG_SP4_SHIFT                     14
+#define AIPS_PACRG_SP4_WIDTH                     1
+#define AIPS_PACRG_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP4_SHIFT))&AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_TP3_MASK                      0x10000u
+#define AIPS_PACRG_TP3_SHIFT                     16
+#define AIPS_PACRG_TP3_WIDTH                     1
+#define AIPS_PACRG_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP3_SHIFT))&AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_WP3_MASK                      0x20000u
+#define AIPS_PACRG_WP3_SHIFT                     17
+#define AIPS_PACRG_WP3_WIDTH                     1
+#define AIPS_PACRG_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP3_SHIFT))&AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_SP3_MASK                      0x40000u
+#define AIPS_PACRG_SP3_SHIFT                     18
+#define AIPS_PACRG_SP3_WIDTH                     1
+#define AIPS_PACRG_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP3_SHIFT))&AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_TP2_MASK                      0x100000u
+#define AIPS_PACRG_TP2_SHIFT                     20
+#define AIPS_PACRG_TP2_WIDTH                     1
+#define AIPS_PACRG_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP2_SHIFT))&AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_WP2_MASK                      0x200000u
+#define AIPS_PACRG_WP2_SHIFT                     21
+#define AIPS_PACRG_WP2_WIDTH                     1
+#define AIPS_PACRG_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP2_SHIFT))&AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_SP2_MASK                      0x400000u
+#define AIPS_PACRG_SP2_SHIFT                     22
+#define AIPS_PACRG_SP2_WIDTH                     1
+#define AIPS_PACRG_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP2_SHIFT))&AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_TP1_MASK                      0x1000000u
+#define AIPS_PACRG_TP1_SHIFT                     24
+#define AIPS_PACRG_TP1_WIDTH                     1
+#define AIPS_PACRG_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP1_SHIFT))&AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_WP1_MASK                      0x2000000u
+#define AIPS_PACRG_WP1_SHIFT                     25
+#define AIPS_PACRG_WP1_WIDTH                     1
+#define AIPS_PACRG_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP1_SHIFT))&AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_SP1_MASK                      0x4000000u
+#define AIPS_PACRG_SP1_SHIFT                     26
+#define AIPS_PACRG_SP1_WIDTH                     1
+#define AIPS_PACRG_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP1_SHIFT))&AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_TP0_MASK                      0x10000000u
+#define AIPS_PACRG_TP0_SHIFT                     28
+#define AIPS_PACRG_TP0_WIDTH                     1
+#define AIPS_PACRG_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP0_SHIFT))&AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_WP0_MASK                      0x20000000u
+#define AIPS_PACRG_WP0_SHIFT                     29
+#define AIPS_PACRG_WP0_WIDTH                     1
+#define AIPS_PACRG_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP0_SHIFT))&AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_SP0_MASK                      0x40000000u
+#define AIPS_PACRG_SP0_SHIFT                     30
+#define AIPS_PACRG_SP0_WIDTH                     1
+#define AIPS_PACRG_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP0_SHIFT))&AIPS_PACRG_SP0_MASK)
+/* PACRH Bit Fields */
+#define AIPS_PACRH_TP7_MASK                      0x1u
+#define AIPS_PACRH_TP7_SHIFT                     0
+#define AIPS_PACRH_TP7_WIDTH                     1
+#define AIPS_PACRH_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP7_SHIFT))&AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_WP7_MASK                      0x2u
+#define AIPS_PACRH_WP7_SHIFT                     1
+#define AIPS_PACRH_WP7_WIDTH                     1
+#define AIPS_PACRH_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP7_SHIFT))&AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_SP7_MASK                      0x4u
+#define AIPS_PACRH_SP7_SHIFT                     2
+#define AIPS_PACRH_SP7_WIDTH                     1
+#define AIPS_PACRH_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP7_SHIFT))&AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_TP6_MASK                      0x10u
+#define AIPS_PACRH_TP6_SHIFT                     4
+#define AIPS_PACRH_TP6_WIDTH                     1
+#define AIPS_PACRH_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP6_SHIFT))&AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_WP6_MASK                      0x20u
+#define AIPS_PACRH_WP6_SHIFT                     5
+#define AIPS_PACRH_WP6_WIDTH                     1
+#define AIPS_PACRH_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP6_SHIFT))&AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_SP6_MASK                      0x40u
+#define AIPS_PACRH_SP6_SHIFT                     6
+#define AIPS_PACRH_SP6_WIDTH                     1
+#define AIPS_PACRH_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP6_SHIFT))&AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_TP5_MASK                      0x100u
+#define AIPS_PACRH_TP5_SHIFT                     8
+#define AIPS_PACRH_TP5_WIDTH                     1
+#define AIPS_PACRH_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP5_SHIFT))&AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_WP5_MASK                      0x200u
+#define AIPS_PACRH_WP5_SHIFT                     9
+#define AIPS_PACRH_WP5_WIDTH                     1
+#define AIPS_PACRH_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP5_SHIFT))&AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_SP5_MASK                      0x400u
+#define AIPS_PACRH_SP5_SHIFT                     10
+#define AIPS_PACRH_SP5_WIDTH                     1
+#define AIPS_PACRH_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP5_SHIFT))&AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_TP4_MASK                      0x1000u
+#define AIPS_PACRH_TP4_SHIFT                     12
+#define AIPS_PACRH_TP4_WIDTH                     1
+#define AIPS_PACRH_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP4_SHIFT))&AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_WP4_MASK                      0x2000u
+#define AIPS_PACRH_WP4_SHIFT                     13
+#define AIPS_PACRH_WP4_WIDTH                     1
+#define AIPS_PACRH_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP4_SHIFT))&AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_SP4_MASK                      0x4000u
+#define AIPS_PACRH_SP4_SHIFT                     14
+#define AIPS_PACRH_SP4_WIDTH                     1
+#define AIPS_PACRH_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP4_SHIFT))&AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_TP3_MASK                      0x10000u
+#define AIPS_PACRH_TP3_SHIFT                     16
+#define AIPS_PACRH_TP3_WIDTH                     1
+#define AIPS_PACRH_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP3_SHIFT))&AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_WP3_MASK                      0x20000u
+#define AIPS_PACRH_WP3_SHIFT                     17
+#define AIPS_PACRH_WP3_WIDTH                     1
+#define AIPS_PACRH_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP3_SHIFT))&AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_SP3_MASK                      0x40000u
+#define AIPS_PACRH_SP3_SHIFT                     18
+#define AIPS_PACRH_SP3_WIDTH                     1
+#define AIPS_PACRH_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP3_SHIFT))&AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_TP2_MASK                      0x100000u
+#define AIPS_PACRH_TP2_SHIFT                     20
+#define AIPS_PACRH_TP2_WIDTH                     1
+#define AIPS_PACRH_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP2_SHIFT))&AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_WP2_MASK                      0x200000u
+#define AIPS_PACRH_WP2_SHIFT                     21
+#define AIPS_PACRH_WP2_WIDTH                     1
+#define AIPS_PACRH_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP2_SHIFT))&AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_SP2_MASK                      0x400000u
+#define AIPS_PACRH_SP2_SHIFT                     22
+#define AIPS_PACRH_SP2_WIDTH                     1
+#define AIPS_PACRH_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP2_SHIFT))&AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_TP1_MASK                      0x1000000u
+#define AIPS_PACRH_TP1_SHIFT                     24
+#define AIPS_PACRH_TP1_WIDTH                     1
+#define AIPS_PACRH_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP1_SHIFT))&AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_WP1_MASK                      0x2000000u
+#define AIPS_PACRH_WP1_SHIFT                     25
+#define AIPS_PACRH_WP1_WIDTH                     1
+#define AIPS_PACRH_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP1_SHIFT))&AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_SP1_MASK                      0x4000000u
+#define AIPS_PACRH_SP1_SHIFT                     26
+#define AIPS_PACRH_SP1_WIDTH                     1
+#define AIPS_PACRH_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP1_SHIFT))&AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_TP0_MASK                      0x10000000u
+#define AIPS_PACRH_TP0_SHIFT                     28
+#define AIPS_PACRH_TP0_WIDTH                     1
+#define AIPS_PACRH_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP0_SHIFT))&AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_WP0_MASK                      0x20000000u
+#define AIPS_PACRH_WP0_SHIFT                     29
+#define AIPS_PACRH_WP0_WIDTH                     1
+#define AIPS_PACRH_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP0_SHIFT))&AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_SP0_MASK                      0x40000000u
+#define AIPS_PACRH_SP0_SHIFT                     30
+#define AIPS_PACRH_SP0_WIDTH                     1
+#define AIPS_PACRH_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP0_SHIFT))&AIPS_PACRH_SP0_MASK)
+/* PACRI Bit Fields */
+#define AIPS_PACRI_TP7_MASK                      0x1u
+#define AIPS_PACRI_TP7_SHIFT                     0
+#define AIPS_PACRI_TP7_WIDTH                     1
+#define AIPS_PACRI_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP7_SHIFT))&AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_WP7_MASK                      0x2u
+#define AIPS_PACRI_WP7_SHIFT                     1
+#define AIPS_PACRI_WP7_WIDTH                     1
+#define AIPS_PACRI_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP7_SHIFT))&AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_SP7_MASK                      0x4u
+#define AIPS_PACRI_SP7_SHIFT                     2
+#define AIPS_PACRI_SP7_WIDTH                     1
+#define AIPS_PACRI_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP7_SHIFT))&AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_TP6_MASK                      0x10u
+#define AIPS_PACRI_TP6_SHIFT                     4
+#define AIPS_PACRI_TP6_WIDTH                     1
+#define AIPS_PACRI_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP6_SHIFT))&AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_WP6_MASK                      0x20u
+#define AIPS_PACRI_WP6_SHIFT                     5
+#define AIPS_PACRI_WP6_WIDTH                     1
+#define AIPS_PACRI_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP6_SHIFT))&AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_SP6_MASK                      0x40u
+#define AIPS_PACRI_SP6_SHIFT                     6
+#define AIPS_PACRI_SP6_WIDTH                     1
+#define AIPS_PACRI_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP6_SHIFT))&AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_TP5_MASK                      0x100u
+#define AIPS_PACRI_TP5_SHIFT                     8
+#define AIPS_PACRI_TP5_WIDTH                     1
+#define AIPS_PACRI_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP5_SHIFT))&AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_WP5_MASK                      0x200u
+#define AIPS_PACRI_WP5_SHIFT                     9
+#define AIPS_PACRI_WP5_WIDTH                     1
+#define AIPS_PACRI_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP5_SHIFT))&AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_SP5_MASK                      0x400u
+#define AIPS_PACRI_SP5_SHIFT                     10
+#define AIPS_PACRI_SP5_WIDTH                     1
+#define AIPS_PACRI_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP5_SHIFT))&AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_TP4_MASK                      0x1000u
+#define AIPS_PACRI_TP4_SHIFT                     12
+#define AIPS_PACRI_TP4_WIDTH                     1
+#define AIPS_PACRI_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP4_SHIFT))&AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_WP4_MASK                      0x2000u
+#define AIPS_PACRI_WP4_SHIFT                     13
+#define AIPS_PACRI_WP4_WIDTH                     1
+#define AIPS_PACRI_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP4_SHIFT))&AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_SP4_MASK                      0x4000u
+#define AIPS_PACRI_SP4_SHIFT                     14
+#define AIPS_PACRI_SP4_WIDTH                     1
+#define AIPS_PACRI_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP4_SHIFT))&AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_TP3_MASK                      0x10000u
+#define AIPS_PACRI_TP3_SHIFT                     16
+#define AIPS_PACRI_TP3_WIDTH                     1
+#define AIPS_PACRI_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP3_SHIFT))&AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_WP3_MASK                      0x20000u
+#define AIPS_PACRI_WP3_SHIFT                     17
+#define AIPS_PACRI_WP3_WIDTH                     1
+#define AIPS_PACRI_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP3_SHIFT))&AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_SP3_MASK                      0x40000u
+#define AIPS_PACRI_SP3_SHIFT                     18
+#define AIPS_PACRI_SP3_WIDTH                     1
+#define AIPS_PACRI_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP3_SHIFT))&AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_TP2_MASK                      0x100000u
+#define AIPS_PACRI_TP2_SHIFT                     20
+#define AIPS_PACRI_TP2_WIDTH                     1
+#define AIPS_PACRI_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP2_SHIFT))&AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_WP2_MASK                      0x200000u
+#define AIPS_PACRI_WP2_SHIFT                     21
+#define AIPS_PACRI_WP2_WIDTH                     1
+#define AIPS_PACRI_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP2_SHIFT))&AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_SP2_MASK                      0x400000u
+#define AIPS_PACRI_SP2_SHIFT                     22
+#define AIPS_PACRI_SP2_WIDTH                     1
+#define AIPS_PACRI_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP2_SHIFT))&AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_TP1_MASK                      0x1000000u
+#define AIPS_PACRI_TP1_SHIFT                     24
+#define AIPS_PACRI_TP1_WIDTH                     1
+#define AIPS_PACRI_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP1_SHIFT))&AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_WP1_MASK                      0x2000000u
+#define AIPS_PACRI_WP1_SHIFT                     25
+#define AIPS_PACRI_WP1_WIDTH                     1
+#define AIPS_PACRI_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP1_SHIFT))&AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_SP1_MASK                      0x4000000u
+#define AIPS_PACRI_SP1_SHIFT                     26
+#define AIPS_PACRI_SP1_WIDTH                     1
+#define AIPS_PACRI_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP1_SHIFT))&AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_TP0_MASK                      0x10000000u
+#define AIPS_PACRI_TP0_SHIFT                     28
+#define AIPS_PACRI_TP0_WIDTH                     1
+#define AIPS_PACRI_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP0_SHIFT))&AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_WP0_MASK                      0x20000000u
+#define AIPS_PACRI_WP0_SHIFT                     29
+#define AIPS_PACRI_WP0_WIDTH                     1
+#define AIPS_PACRI_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP0_SHIFT))&AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_SP0_MASK                      0x40000000u
+#define AIPS_PACRI_SP0_SHIFT                     30
+#define AIPS_PACRI_SP0_WIDTH                     1
+#define AIPS_PACRI_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP0_SHIFT))&AIPS_PACRI_SP0_MASK)
+/* PACRJ Bit Fields */
+#define AIPS_PACRJ_TP7_MASK                      0x1u
+#define AIPS_PACRJ_TP7_SHIFT                     0
+#define AIPS_PACRJ_TP7_WIDTH                     1
+#define AIPS_PACRJ_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP7_SHIFT))&AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_WP7_MASK                      0x2u
+#define AIPS_PACRJ_WP7_SHIFT                     1
+#define AIPS_PACRJ_WP7_WIDTH                     1
+#define AIPS_PACRJ_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP7_SHIFT))&AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_SP7_MASK                      0x4u
+#define AIPS_PACRJ_SP7_SHIFT                     2
+#define AIPS_PACRJ_SP7_WIDTH                     1
+#define AIPS_PACRJ_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP7_SHIFT))&AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_TP6_MASK                      0x10u
+#define AIPS_PACRJ_TP6_SHIFT                     4
+#define AIPS_PACRJ_TP6_WIDTH                     1
+#define AIPS_PACRJ_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP6_SHIFT))&AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_WP6_MASK                      0x20u
+#define AIPS_PACRJ_WP6_SHIFT                     5
+#define AIPS_PACRJ_WP6_WIDTH                     1
+#define AIPS_PACRJ_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP6_SHIFT))&AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_SP6_MASK                      0x40u
+#define AIPS_PACRJ_SP6_SHIFT                     6
+#define AIPS_PACRJ_SP6_WIDTH                     1
+#define AIPS_PACRJ_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP6_SHIFT))&AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_TP5_MASK                      0x100u
+#define AIPS_PACRJ_TP5_SHIFT                     8
+#define AIPS_PACRJ_TP5_WIDTH                     1
+#define AIPS_PACRJ_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP5_SHIFT))&AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_WP5_MASK                      0x200u
+#define AIPS_PACRJ_WP5_SHIFT                     9
+#define AIPS_PACRJ_WP5_WIDTH                     1
+#define AIPS_PACRJ_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP5_SHIFT))&AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_SP5_MASK                      0x400u
+#define AIPS_PACRJ_SP5_SHIFT                     10
+#define AIPS_PACRJ_SP5_WIDTH                     1
+#define AIPS_PACRJ_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP5_SHIFT))&AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_TP4_MASK                      0x1000u
+#define AIPS_PACRJ_TP4_SHIFT                     12
+#define AIPS_PACRJ_TP4_WIDTH                     1
+#define AIPS_PACRJ_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP4_SHIFT))&AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_WP4_MASK                      0x2000u
+#define AIPS_PACRJ_WP4_SHIFT                     13
+#define AIPS_PACRJ_WP4_WIDTH                     1
+#define AIPS_PACRJ_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP4_SHIFT))&AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_SP4_MASK                      0x4000u
+#define AIPS_PACRJ_SP4_SHIFT                     14
+#define AIPS_PACRJ_SP4_WIDTH                     1
+#define AIPS_PACRJ_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP4_SHIFT))&AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_TP3_MASK                      0x10000u
+#define AIPS_PACRJ_TP3_SHIFT                     16
+#define AIPS_PACRJ_TP3_WIDTH                     1
+#define AIPS_PACRJ_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP3_SHIFT))&AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_WP3_MASK                      0x20000u
+#define AIPS_PACRJ_WP3_SHIFT                     17
+#define AIPS_PACRJ_WP3_WIDTH                     1
+#define AIPS_PACRJ_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP3_SHIFT))&AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_SP3_MASK                      0x40000u
+#define AIPS_PACRJ_SP3_SHIFT                     18
+#define AIPS_PACRJ_SP3_WIDTH                     1
+#define AIPS_PACRJ_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP3_SHIFT))&AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_TP2_MASK                      0x100000u
+#define AIPS_PACRJ_TP2_SHIFT                     20
+#define AIPS_PACRJ_TP2_WIDTH                     1
+#define AIPS_PACRJ_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP2_SHIFT))&AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_WP2_MASK                      0x200000u
+#define AIPS_PACRJ_WP2_SHIFT                     21
+#define AIPS_PACRJ_WP2_WIDTH                     1
+#define AIPS_PACRJ_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP2_SHIFT))&AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_SP2_MASK                      0x400000u
+#define AIPS_PACRJ_SP2_SHIFT                     22
+#define AIPS_PACRJ_SP2_WIDTH                     1
+#define AIPS_PACRJ_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP2_SHIFT))&AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_TP1_MASK                      0x1000000u
+#define AIPS_PACRJ_TP1_SHIFT                     24
+#define AIPS_PACRJ_TP1_WIDTH                     1
+#define AIPS_PACRJ_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP1_SHIFT))&AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_WP1_MASK                      0x2000000u
+#define AIPS_PACRJ_WP1_SHIFT                     25
+#define AIPS_PACRJ_WP1_WIDTH                     1
+#define AIPS_PACRJ_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP1_SHIFT))&AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_SP1_MASK                      0x4000000u
+#define AIPS_PACRJ_SP1_SHIFT                     26
+#define AIPS_PACRJ_SP1_WIDTH                     1
+#define AIPS_PACRJ_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP1_SHIFT))&AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_TP0_MASK                      0x10000000u
+#define AIPS_PACRJ_TP0_SHIFT                     28
+#define AIPS_PACRJ_TP0_WIDTH                     1
+#define AIPS_PACRJ_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP0_SHIFT))&AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_WP0_MASK                      0x20000000u
+#define AIPS_PACRJ_WP0_SHIFT                     29
+#define AIPS_PACRJ_WP0_WIDTH                     1
+#define AIPS_PACRJ_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP0_SHIFT))&AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_SP0_MASK                      0x40000000u
+#define AIPS_PACRJ_SP0_SHIFT                     30
+#define AIPS_PACRJ_SP0_WIDTH                     1
+#define AIPS_PACRJ_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP0_SHIFT))&AIPS_PACRJ_SP0_MASK)
+/* PACRK Bit Fields */
+#define AIPS_PACRK_TP7_MASK                      0x1u
+#define AIPS_PACRK_TP7_SHIFT                     0
+#define AIPS_PACRK_TP7_WIDTH                     1
+#define AIPS_PACRK_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP7_SHIFT))&AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_WP7_MASK                      0x2u
+#define AIPS_PACRK_WP7_SHIFT                     1
+#define AIPS_PACRK_WP7_WIDTH                     1
+#define AIPS_PACRK_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP7_SHIFT))&AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_SP7_MASK                      0x4u
+#define AIPS_PACRK_SP7_SHIFT                     2
+#define AIPS_PACRK_SP7_WIDTH                     1
+#define AIPS_PACRK_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP7_SHIFT))&AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_TP6_MASK                      0x10u
+#define AIPS_PACRK_TP6_SHIFT                     4
+#define AIPS_PACRK_TP6_WIDTH                     1
+#define AIPS_PACRK_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP6_SHIFT))&AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_WP6_MASK                      0x20u
+#define AIPS_PACRK_WP6_SHIFT                     5
+#define AIPS_PACRK_WP6_WIDTH                     1
+#define AIPS_PACRK_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP6_SHIFT))&AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_SP6_MASK                      0x40u
+#define AIPS_PACRK_SP6_SHIFT                     6
+#define AIPS_PACRK_SP6_WIDTH                     1
+#define AIPS_PACRK_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP6_SHIFT))&AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_TP5_MASK                      0x100u
+#define AIPS_PACRK_TP5_SHIFT                     8
+#define AIPS_PACRK_TP5_WIDTH                     1
+#define AIPS_PACRK_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP5_SHIFT))&AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_WP5_MASK                      0x200u
+#define AIPS_PACRK_WP5_SHIFT                     9
+#define AIPS_PACRK_WP5_WIDTH                     1
+#define AIPS_PACRK_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP5_SHIFT))&AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_SP5_MASK                      0x400u
+#define AIPS_PACRK_SP5_SHIFT                     10
+#define AIPS_PACRK_SP5_WIDTH                     1
+#define AIPS_PACRK_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP5_SHIFT))&AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_TP4_MASK                      0x1000u
+#define AIPS_PACRK_TP4_SHIFT                     12
+#define AIPS_PACRK_TP4_WIDTH                     1
+#define AIPS_PACRK_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP4_SHIFT))&AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_WP4_MASK                      0x2000u
+#define AIPS_PACRK_WP4_SHIFT                     13
+#define AIPS_PACRK_WP4_WIDTH                     1
+#define AIPS_PACRK_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP4_SHIFT))&AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_SP4_MASK                      0x4000u
+#define AIPS_PACRK_SP4_SHIFT                     14
+#define AIPS_PACRK_SP4_WIDTH                     1
+#define AIPS_PACRK_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP4_SHIFT))&AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_TP3_MASK                      0x10000u
+#define AIPS_PACRK_TP3_SHIFT                     16
+#define AIPS_PACRK_TP3_WIDTH                     1
+#define AIPS_PACRK_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP3_SHIFT))&AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_WP3_MASK                      0x20000u
+#define AIPS_PACRK_WP3_SHIFT                     17
+#define AIPS_PACRK_WP3_WIDTH                     1
+#define AIPS_PACRK_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP3_SHIFT))&AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_SP3_MASK                      0x40000u
+#define AIPS_PACRK_SP3_SHIFT                     18
+#define AIPS_PACRK_SP3_WIDTH                     1
+#define AIPS_PACRK_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP3_SHIFT))&AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_TP2_MASK                      0x100000u
+#define AIPS_PACRK_TP2_SHIFT                     20
+#define AIPS_PACRK_TP2_WIDTH                     1
+#define AIPS_PACRK_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP2_SHIFT))&AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_WP2_MASK                      0x200000u
+#define AIPS_PACRK_WP2_SHIFT                     21
+#define AIPS_PACRK_WP2_WIDTH                     1
+#define AIPS_PACRK_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP2_SHIFT))&AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_SP2_MASK                      0x400000u
+#define AIPS_PACRK_SP2_SHIFT                     22
+#define AIPS_PACRK_SP2_WIDTH                     1
+#define AIPS_PACRK_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP2_SHIFT))&AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_TP1_MASK                      0x1000000u
+#define AIPS_PACRK_TP1_SHIFT                     24
+#define AIPS_PACRK_TP1_WIDTH                     1
+#define AIPS_PACRK_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP1_SHIFT))&AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_WP1_MASK                      0x2000000u
+#define AIPS_PACRK_WP1_SHIFT                     25
+#define AIPS_PACRK_WP1_WIDTH                     1
+#define AIPS_PACRK_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP1_SHIFT))&AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_SP1_MASK                      0x4000000u
+#define AIPS_PACRK_SP1_SHIFT                     26
+#define AIPS_PACRK_SP1_WIDTH                     1
+#define AIPS_PACRK_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP1_SHIFT))&AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_TP0_MASK                      0x10000000u
+#define AIPS_PACRK_TP0_SHIFT                     28
+#define AIPS_PACRK_TP0_WIDTH                     1
+#define AIPS_PACRK_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP0_SHIFT))&AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_WP0_MASK                      0x20000000u
+#define AIPS_PACRK_WP0_SHIFT                     29
+#define AIPS_PACRK_WP0_WIDTH                     1
+#define AIPS_PACRK_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP0_SHIFT))&AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_SP0_MASK                      0x40000000u
+#define AIPS_PACRK_SP0_SHIFT                     30
+#define AIPS_PACRK_SP0_WIDTH                     1
+#define AIPS_PACRK_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP0_SHIFT))&AIPS_PACRK_SP0_MASK)
+/* PACRL Bit Fields */
+#define AIPS_PACRL_TP7_MASK                      0x1u
+#define AIPS_PACRL_TP7_SHIFT                     0
+#define AIPS_PACRL_TP7_WIDTH                     1
+#define AIPS_PACRL_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP7_SHIFT))&AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_WP7_MASK                      0x2u
+#define AIPS_PACRL_WP7_SHIFT                     1
+#define AIPS_PACRL_WP7_WIDTH                     1
+#define AIPS_PACRL_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP7_SHIFT))&AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_SP7_MASK                      0x4u
+#define AIPS_PACRL_SP7_SHIFT                     2
+#define AIPS_PACRL_SP7_WIDTH                     1
+#define AIPS_PACRL_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP7_SHIFT))&AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_TP6_MASK                      0x10u
+#define AIPS_PACRL_TP6_SHIFT                     4
+#define AIPS_PACRL_TP6_WIDTH                     1
+#define AIPS_PACRL_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP6_SHIFT))&AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_WP6_MASK                      0x20u
+#define AIPS_PACRL_WP6_SHIFT                     5
+#define AIPS_PACRL_WP6_WIDTH                     1
+#define AIPS_PACRL_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP6_SHIFT))&AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_SP6_MASK                      0x40u
+#define AIPS_PACRL_SP6_SHIFT                     6
+#define AIPS_PACRL_SP6_WIDTH                     1
+#define AIPS_PACRL_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP6_SHIFT))&AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_TP5_MASK                      0x100u
+#define AIPS_PACRL_TP5_SHIFT                     8
+#define AIPS_PACRL_TP5_WIDTH                     1
+#define AIPS_PACRL_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP5_SHIFT))&AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_WP5_MASK                      0x200u
+#define AIPS_PACRL_WP5_SHIFT                     9
+#define AIPS_PACRL_WP5_WIDTH                     1
+#define AIPS_PACRL_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP5_SHIFT))&AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_SP5_MASK                      0x400u
+#define AIPS_PACRL_SP5_SHIFT                     10
+#define AIPS_PACRL_SP5_WIDTH                     1
+#define AIPS_PACRL_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP5_SHIFT))&AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_TP4_MASK                      0x1000u
+#define AIPS_PACRL_TP4_SHIFT                     12
+#define AIPS_PACRL_TP4_WIDTH                     1
+#define AIPS_PACRL_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP4_SHIFT))&AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_WP4_MASK                      0x2000u
+#define AIPS_PACRL_WP4_SHIFT                     13
+#define AIPS_PACRL_WP4_WIDTH                     1
+#define AIPS_PACRL_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP4_SHIFT))&AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_SP4_MASK                      0x4000u
+#define AIPS_PACRL_SP4_SHIFT                     14
+#define AIPS_PACRL_SP4_WIDTH                     1
+#define AIPS_PACRL_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP4_SHIFT))&AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_TP3_MASK                      0x10000u
+#define AIPS_PACRL_TP3_SHIFT                     16
+#define AIPS_PACRL_TP3_WIDTH                     1
+#define AIPS_PACRL_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP3_SHIFT))&AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_WP3_MASK                      0x20000u
+#define AIPS_PACRL_WP3_SHIFT                     17
+#define AIPS_PACRL_WP3_WIDTH                     1
+#define AIPS_PACRL_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP3_SHIFT))&AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_SP3_MASK                      0x40000u
+#define AIPS_PACRL_SP3_SHIFT                     18
+#define AIPS_PACRL_SP3_WIDTH                     1
+#define AIPS_PACRL_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP3_SHIFT))&AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_TP2_MASK                      0x100000u
+#define AIPS_PACRL_TP2_SHIFT                     20
+#define AIPS_PACRL_TP2_WIDTH                     1
+#define AIPS_PACRL_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP2_SHIFT))&AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_WP2_MASK                      0x200000u
+#define AIPS_PACRL_WP2_SHIFT                     21
+#define AIPS_PACRL_WP2_WIDTH                     1
+#define AIPS_PACRL_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP2_SHIFT))&AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_SP2_MASK                      0x400000u
+#define AIPS_PACRL_SP2_SHIFT                     22
+#define AIPS_PACRL_SP2_WIDTH                     1
+#define AIPS_PACRL_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP2_SHIFT))&AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_TP1_MASK                      0x1000000u
+#define AIPS_PACRL_TP1_SHIFT                     24
+#define AIPS_PACRL_TP1_WIDTH                     1
+#define AIPS_PACRL_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP1_SHIFT))&AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_WP1_MASK                      0x2000000u
+#define AIPS_PACRL_WP1_SHIFT                     25
+#define AIPS_PACRL_WP1_WIDTH                     1
+#define AIPS_PACRL_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP1_SHIFT))&AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_SP1_MASK                      0x4000000u
+#define AIPS_PACRL_SP1_SHIFT                     26
+#define AIPS_PACRL_SP1_WIDTH                     1
+#define AIPS_PACRL_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP1_SHIFT))&AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_TP0_MASK                      0x10000000u
+#define AIPS_PACRL_TP0_SHIFT                     28
+#define AIPS_PACRL_TP0_WIDTH                     1
+#define AIPS_PACRL_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP0_SHIFT))&AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_WP0_MASK                      0x20000000u
+#define AIPS_PACRL_WP0_SHIFT                     29
+#define AIPS_PACRL_WP0_WIDTH                     1
+#define AIPS_PACRL_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP0_SHIFT))&AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_SP0_MASK                      0x40000000u
+#define AIPS_PACRL_SP0_SHIFT                     30
+#define AIPS_PACRL_SP0_WIDTH                     1
+#define AIPS_PACRL_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP0_SHIFT))&AIPS_PACRL_SP0_MASK)
+/* PACRM Bit Fields */
+#define AIPS_PACRM_TP7_MASK                      0x1u
+#define AIPS_PACRM_TP7_SHIFT                     0
+#define AIPS_PACRM_TP7_WIDTH                     1
+#define AIPS_PACRM_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP7_SHIFT))&AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_WP7_MASK                      0x2u
+#define AIPS_PACRM_WP7_SHIFT                     1
+#define AIPS_PACRM_WP7_WIDTH                     1
+#define AIPS_PACRM_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP7_SHIFT))&AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_SP7_MASK                      0x4u
+#define AIPS_PACRM_SP7_SHIFT                     2
+#define AIPS_PACRM_SP7_WIDTH                     1
+#define AIPS_PACRM_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP7_SHIFT))&AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_TP6_MASK                      0x10u
+#define AIPS_PACRM_TP6_SHIFT                     4
+#define AIPS_PACRM_TP6_WIDTH                     1
+#define AIPS_PACRM_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP6_SHIFT))&AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_WP6_MASK                      0x20u
+#define AIPS_PACRM_WP6_SHIFT                     5
+#define AIPS_PACRM_WP6_WIDTH                     1
+#define AIPS_PACRM_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP6_SHIFT))&AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_SP6_MASK                      0x40u
+#define AIPS_PACRM_SP6_SHIFT                     6
+#define AIPS_PACRM_SP6_WIDTH                     1
+#define AIPS_PACRM_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP6_SHIFT))&AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_TP5_MASK                      0x100u
+#define AIPS_PACRM_TP5_SHIFT                     8
+#define AIPS_PACRM_TP5_WIDTH                     1
+#define AIPS_PACRM_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP5_SHIFT))&AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_WP5_MASK                      0x200u
+#define AIPS_PACRM_WP5_SHIFT                     9
+#define AIPS_PACRM_WP5_WIDTH                     1
+#define AIPS_PACRM_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP5_SHIFT))&AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_SP5_MASK                      0x400u
+#define AIPS_PACRM_SP5_SHIFT                     10
+#define AIPS_PACRM_SP5_WIDTH                     1
+#define AIPS_PACRM_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP5_SHIFT))&AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_TP4_MASK                      0x1000u
+#define AIPS_PACRM_TP4_SHIFT                     12
+#define AIPS_PACRM_TP4_WIDTH                     1
+#define AIPS_PACRM_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP4_SHIFT))&AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_WP4_MASK                      0x2000u
+#define AIPS_PACRM_WP4_SHIFT                     13
+#define AIPS_PACRM_WP4_WIDTH                     1
+#define AIPS_PACRM_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP4_SHIFT))&AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_SP4_MASK                      0x4000u
+#define AIPS_PACRM_SP4_SHIFT                     14
+#define AIPS_PACRM_SP4_WIDTH                     1
+#define AIPS_PACRM_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP4_SHIFT))&AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_TP3_MASK                      0x10000u
+#define AIPS_PACRM_TP3_SHIFT                     16
+#define AIPS_PACRM_TP3_WIDTH                     1
+#define AIPS_PACRM_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP3_SHIFT))&AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_WP3_MASK                      0x20000u
+#define AIPS_PACRM_WP3_SHIFT                     17
+#define AIPS_PACRM_WP3_WIDTH                     1
+#define AIPS_PACRM_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP3_SHIFT))&AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_SP3_MASK                      0x40000u
+#define AIPS_PACRM_SP3_SHIFT                     18
+#define AIPS_PACRM_SP3_WIDTH                     1
+#define AIPS_PACRM_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP3_SHIFT))&AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_TP2_MASK                      0x100000u
+#define AIPS_PACRM_TP2_SHIFT                     20
+#define AIPS_PACRM_TP2_WIDTH                     1
+#define AIPS_PACRM_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP2_SHIFT))&AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_WP2_MASK                      0x200000u
+#define AIPS_PACRM_WP2_SHIFT                     21
+#define AIPS_PACRM_WP2_WIDTH                     1
+#define AIPS_PACRM_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP2_SHIFT))&AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_SP2_MASK                      0x400000u
+#define AIPS_PACRM_SP2_SHIFT                     22
+#define AIPS_PACRM_SP2_WIDTH                     1
+#define AIPS_PACRM_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP2_SHIFT))&AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_TP1_MASK                      0x1000000u
+#define AIPS_PACRM_TP1_SHIFT                     24
+#define AIPS_PACRM_TP1_WIDTH                     1
+#define AIPS_PACRM_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP1_SHIFT))&AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_WP1_MASK                      0x2000000u
+#define AIPS_PACRM_WP1_SHIFT                     25
+#define AIPS_PACRM_WP1_WIDTH                     1
+#define AIPS_PACRM_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP1_SHIFT))&AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_SP1_MASK                      0x4000000u
+#define AIPS_PACRM_SP1_SHIFT                     26
+#define AIPS_PACRM_SP1_WIDTH                     1
+#define AIPS_PACRM_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP1_SHIFT))&AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_TP0_MASK                      0x10000000u
+#define AIPS_PACRM_TP0_SHIFT                     28
+#define AIPS_PACRM_TP0_WIDTH                     1
+#define AIPS_PACRM_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP0_SHIFT))&AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_WP0_MASK                      0x20000000u
+#define AIPS_PACRM_WP0_SHIFT                     29
+#define AIPS_PACRM_WP0_WIDTH                     1
+#define AIPS_PACRM_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP0_SHIFT))&AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_SP0_MASK                      0x40000000u
+#define AIPS_PACRM_SP0_SHIFT                     30
+#define AIPS_PACRM_SP0_WIDTH                     1
+#define AIPS_PACRM_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP0_SHIFT))&AIPS_PACRM_SP0_MASK)
+/* PACRN Bit Fields */
+#define AIPS_PACRN_TP7_MASK                      0x1u
+#define AIPS_PACRN_TP7_SHIFT                     0
+#define AIPS_PACRN_TP7_WIDTH                     1
+#define AIPS_PACRN_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP7_SHIFT))&AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_WP7_MASK                      0x2u
+#define AIPS_PACRN_WP7_SHIFT                     1
+#define AIPS_PACRN_WP7_WIDTH                     1
+#define AIPS_PACRN_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP7_SHIFT))&AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_SP7_MASK                      0x4u
+#define AIPS_PACRN_SP7_SHIFT                     2
+#define AIPS_PACRN_SP7_WIDTH                     1
+#define AIPS_PACRN_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP7_SHIFT))&AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_TP6_MASK                      0x10u
+#define AIPS_PACRN_TP6_SHIFT                     4
+#define AIPS_PACRN_TP6_WIDTH                     1
+#define AIPS_PACRN_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP6_SHIFT))&AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_WP6_MASK                      0x20u
+#define AIPS_PACRN_WP6_SHIFT                     5
+#define AIPS_PACRN_WP6_WIDTH                     1
+#define AIPS_PACRN_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP6_SHIFT))&AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_SP6_MASK                      0x40u
+#define AIPS_PACRN_SP6_SHIFT                     6
+#define AIPS_PACRN_SP6_WIDTH                     1
+#define AIPS_PACRN_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP6_SHIFT))&AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_TP5_MASK                      0x100u
+#define AIPS_PACRN_TP5_SHIFT                     8
+#define AIPS_PACRN_TP5_WIDTH                     1
+#define AIPS_PACRN_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP5_SHIFT))&AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_WP5_MASK                      0x200u
+#define AIPS_PACRN_WP5_SHIFT                     9
+#define AIPS_PACRN_WP5_WIDTH                     1
+#define AIPS_PACRN_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP5_SHIFT))&AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_SP5_MASK                      0x400u
+#define AIPS_PACRN_SP5_SHIFT                     10
+#define AIPS_PACRN_SP5_WIDTH                     1
+#define AIPS_PACRN_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP5_SHIFT))&AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_TP4_MASK                      0x1000u
+#define AIPS_PACRN_TP4_SHIFT                     12
+#define AIPS_PACRN_TP4_WIDTH                     1
+#define AIPS_PACRN_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP4_SHIFT))&AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_WP4_MASK                      0x2000u
+#define AIPS_PACRN_WP4_SHIFT                     13
+#define AIPS_PACRN_WP4_WIDTH                     1
+#define AIPS_PACRN_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP4_SHIFT))&AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_SP4_MASK                      0x4000u
+#define AIPS_PACRN_SP4_SHIFT                     14
+#define AIPS_PACRN_SP4_WIDTH                     1
+#define AIPS_PACRN_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP4_SHIFT))&AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_TP3_MASK                      0x10000u
+#define AIPS_PACRN_TP3_SHIFT                     16
+#define AIPS_PACRN_TP3_WIDTH                     1
+#define AIPS_PACRN_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP3_SHIFT))&AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_WP3_MASK                      0x20000u
+#define AIPS_PACRN_WP3_SHIFT                     17
+#define AIPS_PACRN_WP3_WIDTH                     1
+#define AIPS_PACRN_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP3_SHIFT))&AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_SP3_MASK                      0x40000u
+#define AIPS_PACRN_SP3_SHIFT                     18
+#define AIPS_PACRN_SP3_WIDTH                     1
+#define AIPS_PACRN_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP3_SHIFT))&AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_TP2_MASK                      0x100000u
+#define AIPS_PACRN_TP2_SHIFT                     20
+#define AIPS_PACRN_TP2_WIDTH                     1
+#define AIPS_PACRN_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP2_SHIFT))&AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_WP2_MASK                      0x200000u
+#define AIPS_PACRN_WP2_SHIFT                     21
+#define AIPS_PACRN_WP2_WIDTH                     1
+#define AIPS_PACRN_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP2_SHIFT))&AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_SP2_MASK                      0x400000u
+#define AIPS_PACRN_SP2_SHIFT                     22
+#define AIPS_PACRN_SP2_WIDTH                     1
+#define AIPS_PACRN_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP2_SHIFT))&AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_TP1_MASK                      0x1000000u
+#define AIPS_PACRN_TP1_SHIFT                     24
+#define AIPS_PACRN_TP1_WIDTH                     1
+#define AIPS_PACRN_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP1_SHIFT))&AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_WP1_MASK                      0x2000000u
+#define AIPS_PACRN_WP1_SHIFT                     25
+#define AIPS_PACRN_WP1_WIDTH                     1
+#define AIPS_PACRN_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP1_SHIFT))&AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_SP1_MASK                      0x4000000u
+#define AIPS_PACRN_SP1_SHIFT                     26
+#define AIPS_PACRN_SP1_WIDTH                     1
+#define AIPS_PACRN_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP1_SHIFT))&AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_TP0_MASK                      0x10000000u
+#define AIPS_PACRN_TP0_SHIFT                     28
+#define AIPS_PACRN_TP0_WIDTH                     1
+#define AIPS_PACRN_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP0_SHIFT))&AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_WP0_MASK                      0x20000000u
+#define AIPS_PACRN_WP0_SHIFT                     29
+#define AIPS_PACRN_WP0_WIDTH                     1
+#define AIPS_PACRN_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP0_SHIFT))&AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_SP0_MASK                      0x40000000u
+#define AIPS_PACRN_SP0_SHIFT                     30
+#define AIPS_PACRN_SP0_WIDTH                     1
+#define AIPS_PACRN_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP0_SHIFT))&AIPS_PACRN_SP0_MASK)
+/* PACRO Bit Fields */
+#define AIPS_PACRO_TP7_MASK                      0x1u
+#define AIPS_PACRO_TP7_SHIFT                     0
+#define AIPS_PACRO_TP7_WIDTH                     1
+#define AIPS_PACRO_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP7_SHIFT))&AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_WP7_MASK                      0x2u
+#define AIPS_PACRO_WP7_SHIFT                     1
+#define AIPS_PACRO_WP7_WIDTH                     1
+#define AIPS_PACRO_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP7_SHIFT))&AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_SP7_MASK                      0x4u
+#define AIPS_PACRO_SP7_SHIFT                     2
+#define AIPS_PACRO_SP7_WIDTH                     1
+#define AIPS_PACRO_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP7_SHIFT))&AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_TP6_MASK                      0x10u
+#define AIPS_PACRO_TP6_SHIFT                     4
+#define AIPS_PACRO_TP6_WIDTH                     1
+#define AIPS_PACRO_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP6_SHIFT))&AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_WP6_MASK                      0x20u
+#define AIPS_PACRO_WP6_SHIFT                     5
+#define AIPS_PACRO_WP6_WIDTH                     1
+#define AIPS_PACRO_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP6_SHIFT))&AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_SP6_MASK                      0x40u
+#define AIPS_PACRO_SP6_SHIFT                     6
+#define AIPS_PACRO_SP6_WIDTH                     1
+#define AIPS_PACRO_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP6_SHIFT))&AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_TP5_MASK                      0x100u
+#define AIPS_PACRO_TP5_SHIFT                     8
+#define AIPS_PACRO_TP5_WIDTH                     1
+#define AIPS_PACRO_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP5_SHIFT))&AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_WP5_MASK                      0x200u
+#define AIPS_PACRO_WP5_SHIFT                     9
+#define AIPS_PACRO_WP5_WIDTH                     1
+#define AIPS_PACRO_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP5_SHIFT))&AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_SP5_MASK                      0x400u
+#define AIPS_PACRO_SP5_SHIFT                     10
+#define AIPS_PACRO_SP5_WIDTH                     1
+#define AIPS_PACRO_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP5_SHIFT))&AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_TP4_MASK                      0x1000u
+#define AIPS_PACRO_TP4_SHIFT                     12
+#define AIPS_PACRO_TP4_WIDTH                     1
+#define AIPS_PACRO_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP4_SHIFT))&AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_WP4_MASK                      0x2000u
+#define AIPS_PACRO_WP4_SHIFT                     13
+#define AIPS_PACRO_WP4_WIDTH                     1
+#define AIPS_PACRO_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP4_SHIFT))&AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_SP4_MASK                      0x4000u
+#define AIPS_PACRO_SP4_SHIFT                     14
+#define AIPS_PACRO_SP4_WIDTH                     1
+#define AIPS_PACRO_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP4_SHIFT))&AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_TP3_MASK                      0x10000u
+#define AIPS_PACRO_TP3_SHIFT                     16
+#define AIPS_PACRO_TP3_WIDTH                     1
+#define AIPS_PACRO_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP3_SHIFT))&AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_WP3_MASK                      0x20000u
+#define AIPS_PACRO_WP3_SHIFT                     17
+#define AIPS_PACRO_WP3_WIDTH                     1
+#define AIPS_PACRO_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP3_SHIFT))&AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_SP3_MASK                      0x40000u
+#define AIPS_PACRO_SP3_SHIFT                     18
+#define AIPS_PACRO_SP3_WIDTH                     1
+#define AIPS_PACRO_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP3_SHIFT))&AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_TP2_MASK                      0x100000u
+#define AIPS_PACRO_TP2_SHIFT                     20
+#define AIPS_PACRO_TP2_WIDTH                     1
+#define AIPS_PACRO_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP2_SHIFT))&AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_WP2_MASK                      0x200000u
+#define AIPS_PACRO_WP2_SHIFT                     21
+#define AIPS_PACRO_WP2_WIDTH                     1
+#define AIPS_PACRO_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP2_SHIFT))&AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_SP2_MASK                      0x400000u
+#define AIPS_PACRO_SP2_SHIFT                     22
+#define AIPS_PACRO_SP2_WIDTH                     1
+#define AIPS_PACRO_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP2_SHIFT))&AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_TP1_MASK                      0x1000000u
+#define AIPS_PACRO_TP1_SHIFT                     24
+#define AIPS_PACRO_TP1_WIDTH                     1
+#define AIPS_PACRO_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP1_SHIFT))&AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_WP1_MASK                      0x2000000u
+#define AIPS_PACRO_WP1_SHIFT                     25
+#define AIPS_PACRO_WP1_WIDTH                     1
+#define AIPS_PACRO_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP1_SHIFT))&AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_SP1_MASK                      0x4000000u
+#define AIPS_PACRO_SP1_SHIFT                     26
+#define AIPS_PACRO_SP1_WIDTH                     1
+#define AIPS_PACRO_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP1_SHIFT))&AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_TP0_MASK                      0x10000000u
+#define AIPS_PACRO_TP0_SHIFT                     28
+#define AIPS_PACRO_TP0_WIDTH                     1
+#define AIPS_PACRO_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP0_SHIFT))&AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_WP0_MASK                      0x20000000u
+#define AIPS_PACRO_WP0_SHIFT                     29
+#define AIPS_PACRO_WP0_WIDTH                     1
+#define AIPS_PACRO_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP0_SHIFT))&AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_SP0_MASK                      0x40000000u
+#define AIPS_PACRO_SP0_SHIFT                     30
+#define AIPS_PACRO_SP0_WIDTH                     1
+#define AIPS_PACRO_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP0_SHIFT))&AIPS_PACRO_SP0_MASK)
+/* PACRP Bit Fields */
+#define AIPS_PACRP_TP7_MASK                      0x1u
+#define AIPS_PACRP_TP7_SHIFT                     0
+#define AIPS_PACRP_TP7_WIDTH                     1
+#define AIPS_PACRP_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP7_SHIFT))&AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_WP7_MASK                      0x2u
+#define AIPS_PACRP_WP7_SHIFT                     1
+#define AIPS_PACRP_WP7_WIDTH                     1
+#define AIPS_PACRP_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP7_SHIFT))&AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_SP7_MASK                      0x4u
+#define AIPS_PACRP_SP7_SHIFT                     2
+#define AIPS_PACRP_SP7_WIDTH                     1
+#define AIPS_PACRP_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP7_SHIFT))&AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_TP6_MASK                      0x10u
+#define AIPS_PACRP_TP6_SHIFT                     4
+#define AIPS_PACRP_TP6_WIDTH                     1
+#define AIPS_PACRP_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP6_SHIFT))&AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_WP6_MASK                      0x20u
+#define AIPS_PACRP_WP6_SHIFT                     5
+#define AIPS_PACRP_WP6_WIDTH                     1
+#define AIPS_PACRP_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP6_SHIFT))&AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_SP6_MASK                      0x40u
+#define AIPS_PACRP_SP6_SHIFT                     6
+#define AIPS_PACRP_SP6_WIDTH                     1
+#define AIPS_PACRP_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP6_SHIFT))&AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_TP5_MASK                      0x100u
+#define AIPS_PACRP_TP5_SHIFT                     8
+#define AIPS_PACRP_TP5_WIDTH                     1
+#define AIPS_PACRP_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP5_SHIFT))&AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_WP5_MASK                      0x200u
+#define AIPS_PACRP_WP5_SHIFT                     9
+#define AIPS_PACRP_WP5_WIDTH                     1
+#define AIPS_PACRP_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP5_SHIFT))&AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_SP5_MASK                      0x400u
+#define AIPS_PACRP_SP5_SHIFT                     10
+#define AIPS_PACRP_SP5_WIDTH                     1
+#define AIPS_PACRP_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP5_SHIFT))&AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_TP4_MASK                      0x1000u
+#define AIPS_PACRP_TP4_SHIFT                     12
+#define AIPS_PACRP_TP4_WIDTH                     1
+#define AIPS_PACRP_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP4_SHIFT))&AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_WP4_MASK                      0x2000u
+#define AIPS_PACRP_WP4_SHIFT                     13
+#define AIPS_PACRP_WP4_WIDTH                     1
+#define AIPS_PACRP_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP4_SHIFT))&AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_SP4_MASK                      0x4000u
+#define AIPS_PACRP_SP4_SHIFT                     14
+#define AIPS_PACRP_SP4_WIDTH                     1
+#define AIPS_PACRP_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP4_SHIFT))&AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_TP3_MASK                      0x10000u
+#define AIPS_PACRP_TP3_SHIFT                     16
+#define AIPS_PACRP_TP3_WIDTH                     1
+#define AIPS_PACRP_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP3_SHIFT))&AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_WP3_MASK                      0x20000u
+#define AIPS_PACRP_WP3_SHIFT                     17
+#define AIPS_PACRP_WP3_WIDTH                     1
+#define AIPS_PACRP_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP3_SHIFT))&AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_SP3_MASK                      0x40000u
+#define AIPS_PACRP_SP3_SHIFT                     18
+#define AIPS_PACRP_SP3_WIDTH                     1
+#define AIPS_PACRP_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP3_SHIFT))&AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_TP2_MASK                      0x100000u
+#define AIPS_PACRP_TP2_SHIFT                     20
+#define AIPS_PACRP_TP2_WIDTH                     1
+#define AIPS_PACRP_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP2_SHIFT))&AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_WP2_MASK                      0x200000u
+#define AIPS_PACRP_WP2_SHIFT                     21
+#define AIPS_PACRP_WP2_WIDTH                     1
+#define AIPS_PACRP_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP2_SHIFT))&AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_SP2_MASK                      0x400000u
+#define AIPS_PACRP_SP2_SHIFT                     22
+#define AIPS_PACRP_SP2_WIDTH                     1
+#define AIPS_PACRP_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP2_SHIFT))&AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_TP1_MASK                      0x1000000u
+#define AIPS_PACRP_TP1_SHIFT                     24
+#define AIPS_PACRP_TP1_WIDTH                     1
+#define AIPS_PACRP_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP1_SHIFT))&AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_WP1_MASK                      0x2000000u
+#define AIPS_PACRP_WP1_SHIFT                     25
+#define AIPS_PACRP_WP1_WIDTH                     1
+#define AIPS_PACRP_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP1_SHIFT))&AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_SP1_MASK                      0x4000000u
+#define AIPS_PACRP_SP1_SHIFT                     26
+#define AIPS_PACRP_SP1_WIDTH                     1
+#define AIPS_PACRP_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP1_SHIFT))&AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_TP0_MASK                      0x10000000u
+#define AIPS_PACRP_TP0_SHIFT                     28
+#define AIPS_PACRP_TP0_WIDTH                     1
+#define AIPS_PACRP_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP0_SHIFT))&AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_WP0_MASK                      0x20000000u
+#define AIPS_PACRP_WP0_SHIFT                     29
+#define AIPS_PACRP_WP0_WIDTH                     1
+#define AIPS_PACRP_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP0_SHIFT))&AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_SP0_MASK                      0x40000000u
+#define AIPS_PACRP_SP0_SHIFT                     30
+#define AIPS_PACRP_SP0_WIDTH                     1
+#define AIPS_PACRP_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP0_SHIFT))&AIPS_PACRP_SP0_MASK)
+/* PACRU Bit Fields */
+#define AIPS_PACRU_TP1_MASK                      0x1000000u
+#define AIPS_PACRU_TP1_SHIFT                     24
+#define AIPS_PACRU_TP1_WIDTH                     1
+#define AIPS_PACRU_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_TP1_SHIFT))&AIPS_PACRU_TP1_MASK)
+#define AIPS_PACRU_WP1_MASK                      0x2000000u
+#define AIPS_PACRU_WP1_SHIFT                     25
+#define AIPS_PACRU_WP1_WIDTH                     1
+#define AIPS_PACRU_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_WP1_SHIFT))&AIPS_PACRU_WP1_MASK)
+#define AIPS_PACRU_SP1_MASK                      0x4000000u
+#define AIPS_PACRU_SP1_SHIFT                     26
+#define AIPS_PACRU_SP1_WIDTH                     1
+#define AIPS_PACRU_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_SP1_SHIFT))&AIPS_PACRU_SP1_MASK)
+#define AIPS_PACRU_TP0_MASK                      0x10000000u
+#define AIPS_PACRU_TP0_SHIFT                     28
+#define AIPS_PACRU_TP0_WIDTH                     1
+#define AIPS_PACRU_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_TP0_SHIFT))&AIPS_PACRU_TP0_MASK)
+#define AIPS_PACRU_WP0_MASK                      0x20000000u
+#define AIPS_PACRU_WP0_SHIFT                     29
+#define AIPS_PACRU_WP0_WIDTH                     1
+#define AIPS_PACRU_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_WP0_SHIFT))&AIPS_PACRU_WP0_MASK)
+#define AIPS_PACRU_SP0_MASK                      0x40000000u
+#define AIPS_PACRU_SP0_SHIFT                     30
+#define AIPS_PACRU_SP0_WIDTH                     1
+#define AIPS_PACRU_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_SP0_SHIFT))&AIPS_PACRU_SP0_MASK)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base address */
+#define AIPS0_BASE                               (0x40000000u)
+/** Peripheral AIPS0 base pointer */
+#define AIPS0                                    ((AIPS_Type *)AIPS0_BASE)
+#define AIPS0_BASE_PTR                           (AIPS0)
+/** Peripheral AIPS1 base address */
+#define AIPS1_BASE                               (0x40080000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1                                    ((AIPS_Type *)AIPS1_BASE)
+#define AIPS1_BASE_PTR                           (AIPS1)
+/** Array initializer of AIPS peripheral base addresses */
+#define AIPS_BASE_ADDRS                          { AIPS0_BASE, AIPS1_BASE }
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS                           { AIPS0, AIPS1 }
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register instance definitions */
+/* AIPS0 */
+#define AIPS0_MPRA                               AIPS_MPRA_REG(AIPS0)
+#define AIPS0_PACRA                              AIPS_PACRA_REG(AIPS0)
+#define AIPS0_PACRB                              AIPS_PACRB_REG(AIPS0)
+#define AIPS0_PACRC                              AIPS_PACRC_REG(AIPS0)
+#define AIPS0_PACRD                              AIPS_PACRD_REG(AIPS0)
+#define AIPS0_PACRE                              AIPS_PACRE_REG(AIPS0)
+#define AIPS0_PACRF                              AIPS_PACRF_REG(AIPS0)
+#define AIPS0_PACRG                              AIPS_PACRG_REG(AIPS0)
+#define AIPS0_PACRH                              AIPS_PACRH_REG(AIPS0)
+#define AIPS0_PACRI                              AIPS_PACRI_REG(AIPS0)
+#define AIPS0_PACRJ                              AIPS_PACRJ_REG(AIPS0)
+#define AIPS0_PACRK                              AIPS_PACRK_REG(AIPS0)
+#define AIPS0_PACRL                              AIPS_PACRL_REG(AIPS0)
+#define AIPS0_PACRM                              AIPS_PACRM_REG(AIPS0)
+#define AIPS0_PACRN                              AIPS_PACRN_REG(AIPS0)
+#define AIPS0_PACRO                              AIPS_PACRO_REG(AIPS0)
+#define AIPS0_PACRP                              AIPS_PACRP_REG(AIPS0)
+#define AIPS0_PACRU                              AIPS_PACRU_REG(AIPS0)
+/* AIPS1 */
+#define AIPS1_MPRA                               AIPS_MPRA_REG(AIPS1)
+#define AIPS1_PACRA                              AIPS_PACRA_REG(AIPS1)
+#define AIPS1_PACRB                              AIPS_PACRB_REG(AIPS1)
+#define AIPS1_PACRC                              AIPS_PACRC_REG(AIPS1)
+#define AIPS1_PACRD                              AIPS_PACRD_REG(AIPS1)
+#define AIPS1_PACRE                              AIPS_PACRE_REG(AIPS1)
+#define AIPS1_PACRF                              AIPS_PACRF_REG(AIPS1)
+#define AIPS1_PACRG                              AIPS_PACRG_REG(AIPS1)
+#define AIPS1_PACRH                              AIPS_PACRH_REG(AIPS1)
+#define AIPS1_PACRI                              AIPS_PACRI_REG(AIPS1)
+#define AIPS1_PACRJ                              AIPS_PACRJ_REG(AIPS1)
+#define AIPS1_PACRK                              AIPS_PACRK_REG(AIPS1)
+#define AIPS1_PACRL                              AIPS_PACRL_REG(AIPS1)
+#define AIPS1_PACRM                              AIPS_PACRM_REG(AIPS1)
+#define AIPS1_PACRN                              AIPS_PACRN_REG(AIPS1)
+#define AIPS1_PACRO                              AIPS_PACRO_REG(AIPS1)
+#define AIPS1_PACRP                              AIPS_PACRP_REG(AIPS1)
+#define AIPS1_PACRU                              AIPS_PACRU_REG(AIPS1)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t PRS;                               /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CRS;                               /**< Control Register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_1[236];
+  } SLAVE[5];
+       uint8_t RESERVED_0[768];
+  __IO uint32_t MGPCR0;                            /**< Master General Purpose Control Register, offset: 0x800 */
+       uint8_t RESERVED_1[252];
+  __IO uint32_t MGPCR1;                            /**< Master General Purpose Control Register, offset: 0x900 */
+       uint8_t RESERVED_2[252];
+  __IO uint32_t MGPCR2;                            /**< Master General Purpose Control Register, offset: 0xA00 */
+       uint8_t RESERVED_3[252];
+  __IO uint32_t MGPCR3;                            /**< Master General Purpose Control Register, offset: 0xB00 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t MGPCR4;                            /**< Master General Purpose Control Register, offset: 0xC00 */
+       uint8_t RESERVED_5[252];
+  __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
+} AXBS_Type, *AXBS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register accessors */
+#define AXBS_PRS_REG(base,index)                 ((base)->SLAVE[index].PRS)
+#define AXBS_PRS_COUNT                           5
+#define AXBS_CRS_REG(base,index)                 ((base)->SLAVE[index].CRS)
+#define AXBS_CRS_COUNT                           5
+#define AXBS_MGPCR0_REG(base)                    ((base)->MGPCR0)
+#define AXBS_MGPCR1_REG(base)                    ((base)->MGPCR1)
+#define AXBS_MGPCR2_REG(base)                    ((base)->MGPCR2)
+#define AXBS_MGPCR3_REG(base)                    ((base)->MGPCR3)
+#define AXBS_MGPCR4_REG(base)                    ((base)->MGPCR4)
+#define AXBS_MGPCR5_REG(base)                    ((base)->MGPCR5)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/* PRS Bit Fields */
+#define AXBS_PRS_M0_MASK                         0x7u
+#define AXBS_PRS_M0_SHIFT                        0
+#define AXBS_PRS_M0_WIDTH                        3
+#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK                         0x70u
+#define AXBS_PRS_M1_SHIFT                        4
+#define AXBS_PRS_M1_WIDTH                        3
+#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK                         0x700u
+#define AXBS_PRS_M2_SHIFT                        8
+#define AXBS_PRS_M2_WIDTH                        3
+#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK                         0x7000u
+#define AXBS_PRS_M3_SHIFT                        12
+#define AXBS_PRS_M3_WIDTH                        3
+#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK                         0x70000u
+#define AXBS_PRS_M4_SHIFT                        16
+#define AXBS_PRS_M4_WIDTH                        3
+#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK                         0x700000u
+#define AXBS_PRS_M5_SHIFT                        20
+#define AXBS_PRS_M5_WIDTH                        3
+#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
+/* CRS Bit Fields */
+#define AXBS_CRS_PARK_MASK                       0x7u
+#define AXBS_CRS_PARK_SHIFT                      0
+#define AXBS_CRS_PARK_WIDTH                      3
+#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK                       0x30u
+#define AXBS_CRS_PCTL_SHIFT                      4
+#define AXBS_CRS_PCTL_WIDTH                      2
+#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK                        0x300u
+#define AXBS_CRS_ARB_SHIFT                       8
+#define AXBS_CRS_ARB_WIDTH                       2
+#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK                        0x40000000u
+#define AXBS_CRS_HLP_SHIFT                       30
+#define AXBS_CRS_HLP_WIDTH                       1
+#define AXBS_CRS_HLP(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_HLP_SHIFT))&AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_RO_MASK                         0x80000000u
+#define AXBS_CRS_RO_SHIFT                        31
+#define AXBS_CRS_RO_WIDTH                        1
+#define AXBS_CRS_RO(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_RO_SHIFT))&AXBS_CRS_RO_MASK)
+/* MGPCR0 Bit Fields */
+#define AXBS_MGPCR0_AULB_MASK                    0x7u
+#define AXBS_MGPCR0_AULB_SHIFT                   0
+#define AXBS_MGPCR0_AULB_WIDTH                   3
+#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
+/* MGPCR1 Bit Fields */
+#define AXBS_MGPCR1_AULB_MASK                    0x7u
+#define AXBS_MGPCR1_AULB_SHIFT                   0
+#define AXBS_MGPCR1_AULB_WIDTH                   3
+#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
+/* MGPCR2 Bit Fields */
+#define AXBS_MGPCR2_AULB_MASK                    0x7u
+#define AXBS_MGPCR2_AULB_SHIFT                   0
+#define AXBS_MGPCR2_AULB_WIDTH                   3
+#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
+/* MGPCR3 Bit Fields */
+#define AXBS_MGPCR3_AULB_MASK                    0x7u
+#define AXBS_MGPCR3_AULB_SHIFT                   0
+#define AXBS_MGPCR3_AULB_WIDTH                   3
+#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
+/* MGPCR4 Bit Fields */
+#define AXBS_MGPCR4_AULB_MASK                    0x7u
+#define AXBS_MGPCR4_AULB_SHIFT                   0
+#define AXBS_MGPCR4_AULB_WIDTH                   3
+#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
+/* MGPCR5 Bit Fields */
+#define AXBS_MGPCR5_AULB_MASK                    0x7u
+#define AXBS_MGPCR5_AULB_SHIFT                   0
+#define AXBS_MGPCR5_AULB_WIDTH                   3
+#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS base address */
+#define AXBS_BASE                                (0x40004000u)
+/** Peripheral AXBS base pointer */
+#define AXBS                                     ((AXBS_Type *)AXBS_BASE)
+#define AXBS_BASE_PTR                            (AXBS)
+/** Array initializer of AXBS peripheral base addresses */
+#define AXBS_BASE_ADDRS                          { AXBS_BASE }
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASE_PTRS                           { AXBS }
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register instance definitions */
+/* AXBS */
+#define AXBS_PRS0                                AXBS_PRS_REG(AXBS,0)
+#define AXBS_CRS0                                AXBS_CRS_REG(AXBS,0)
+#define AXBS_PRS1                                AXBS_PRS_REG(AXBS,1)
+#define AXBS_CRS1                                AXBS_CRS_REG(AXBS,1)
+#define AXBS_PRS2                                AXBS_PRS_REG(AXBS,2)
+#define AXBS_CRS2                                AXBS_CRS_REG(AXBS,2)
+#define AXBS_PRS3                                AXBS_PRS_REG(AXBS,3)
+#define AXBS_CRS3                                AXBS_CRS_REG(AXBS,3)
+#define AXBS_PRS4                                AXBS_PRS_REG(AXBS,4)
+#define AXBS_CRS4                                AXBS_CRS_REG(AXBS,4)
+#define AXBS_MGPCR0                              AXBS_MGPCR0_REG(AXBS)
+#define AXBS_MGPCR1                              AXBS_MGPCR1_REG(AXBS)
+#define AXBS_MGPCR2                              AXBS_MGPCR2_REG(AXBS)
+#define AXBS_MGPCR3                              AXBS_MGPCR3_REG(AXBS)
+#define AXBS_MGPCR4                              AXBS_MGPCR4_REG(AXBS)
+#define AXBS_MGPCR5                              AXBS_MGPCR5_REG(AXBS)
+
+/* AXBS - Register array accessors */
+#define AXBS_PRS(index)                          AXBS_PRS_REG(AXBS,index)
+#define AXBS_CRS(index)                          AXBS_CRS_REG(AXBS,index)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
+  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
+  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
+  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
+  __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
+  __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
+  __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
+  __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
+  __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
+       uint8_t RESERVED_4[48];
+  struct {                                         /* offset: 0x80, array step: 0x10 */
+    __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+    __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+    __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+    __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+  } MB[16];
+       uint8_t RESERVED_5[1792];
+  __IO uint32_t RXIMR[16];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_Type, *CAN_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register accessors */
+#define CAN_MCR_REG(base)                        ((base)->MCR)
+#define CAN_CTRL1_REG(base)                      ((base)->CTRL1)
+#define CAN_TIMER_REG(base)                      ((base)->TIMER)
+#define CAN_RXMGMASK_REG(base)                   ((base)->RXMGMASK)
+#define CAN_RX14MASK_REG(base)                   ((base)->RX14MASK)
+#define CAN_RX15MASK_REG(base)                   ((base)->RX15MASK)
+#define CAN_ECR_REG(base)                        ((base)->ECR)
+#define CAN_ESR1_REG(base)                       ((base)->ESR1)
+#define CAN_IMASK1_REG(base)                     ((base)->IMASK1)
+#define CAN_IFLAG1_REG(base)                     ((base)->IFLAG1)
+#define CAN_CTRL2_REG(base)                      ((base)->CTRL2)
+#define CAN_ESR2_REG(base)                       ((base)->ESR2)
+#define CAN_CRCR_REG(base)                       ((base)->CRCR)
+#define CAN_RXFGMASK_REG(base)                   ((base)->RXFGMASK)
+#define CAN_RXFIR_REG(base)                      ((base)->RXFIR)
+#define CAN_CS_REG(base,index)                   ((base)->MB[index].CS)
+#define CAN_CS_COUNT                             16
+#define CAN_ID_REG(base,index)                   ((base)->MB[index].ID)
+#define CAN_ID_COUNT                             16
+#define CAN_WORD0_REG(base,index)                ((base)->MB[index].WORD0)
+#define CAN_WORD0_COUNT                          16
+#define CAN_WORD1_REG(base,index)                ((base)->MB[index].WORD1)
+#define CAN_WORD1_COUNT                          16
+#define CAN_RXIMR_REG(base,index)                ((base)->RXIMR[index])
+#define CAN_RXIMR_COUNT                          16
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define CAN_MCR_MAXMB_MASK                       0x7Fu
+#define CAN_MCR_MAXMB_SHIFT                      0
+#define CAN_MCR_MAXMB_WIDTH                      7
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK                        0x300u
+#define CAN_MCR_IDAM_SHIFT                       8
+#define CAN_MCR_IDAM_WIDTH                       2
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK                         0x1000u
+#define CAN_MCR_AEN_SHIFT                        12
+#define CAN_MCR_AEN_WIDTH                        1
+#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK                     0x2000u
+#define CAN_MCR_LPRIOEN_SHIFT                    13
+#define CAN_MCR_LPRIOEN_WIDTH                    1
+#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_IRMQ_MASK                        0x10000u
+#define CAN_MCR_IRMQ_SHIFT                       16
+#define CAN_MCR_IRMQ_WIDTH                       1
+#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK                      0x20000u
+#define CAN_MCR_SRXDIS_SHIFT                     17
+#define CAN_MCR_SRXDIS_WIDTH                     1
+#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_WAKSRC_MASK                      0x80000u
+#define CAN_MCR_WAKSRC_SHIFT                     19
+#define CAN_MCR_WAKSRC_WIDTH                     1
+#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKSRC_SHIFT))&CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_LPMACK_MASK                      0x100000u
+#define CAN_MCR_LPMACK_SHIFT                     20
+#define CAN_MCR_LPMACK_WIDTH                     1
+#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK                       0x200000u
+#define CAN_MCR_WRNEN_SHIFT                      21
+#define CAN_MCR_WRNEN_WIDTH                      1
+#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SLFWAK_MASK                      0x400000u
+#define CAN_MCR_SLFWAK_SHIFT                     22
+#define CAN_MCR_SLFWAK_WIDTH                     1
+#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SLFWAK_SHIFT))&CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SUPV_MASK                        0x800000u
+#define CAN_MCR_SUPV_SHIFT                       23
+#define CAN_MCR_SUPV_WIDTH                       1
+#define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
+#define CAN_MCR_FRZACK_MASK                      0x1000000u
+#define CAN_MCR_FRZACK_SHIFT                     24
+#define CAN_MCR_FRZACK_WIDTH                     1
+#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK                     0x2000000u
+#define CAN_MCR_SOFTRST_SHIFT                    25
+#define CAN_MCR_SOFTRST_WIDTH                    1
+#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_WAKMSK_MASK                      0x4000000u
+#define CAN_MCR_WAKMSK_SHIFT                     26
+#define CAN_MCR_WAKMSK_WIDTH                     1
+#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKMSK_SHIFT))&CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_NOTRDY_MASK                      0x8000000u
+#define CAN_MCR_NOTRDY_SHIFT                     27
+#define CAN_MCR_NOTRDY_WIDTH                     1
+#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK                        0x10000000u
+#define CAN_MCR_HALT_SHIFT                       28
+#define CAN_MCR_HALT_WIDTH                       1
+#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK                        0x20000000u
+#define CAN_MCR_RFEN_SHIFT                       29
+#define CAN_MCR_RFEN_WIDTH                       1
+#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK                         0x40000000u
+#define CAN_MCR_FRZ_SHIFT                        30
+#define CAN_MCR_FRZ_WIDTH                        1
+#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK                        0x80000000u
+#define CAN_MCR_MDIS_SHIFT                       31
+#define CAN_MCR_MDIS_WIDTH                       1
+#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
+/* CTRL1 Bit Fields */
+#define CAN_CTRL1_PROPSEG_MASK                   0x7u
+#define CAN_CTRL1_PROPSEG_SHIFT                  0
+#define CAN_CTRL1_PROPSEG_WIDTH                  3
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK                       0x8u
+#define CAN_CTRL1_LOM_SHIFT                      3
+#define CAN_CTRL1_LOM_WIDTH                      1
+#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK                      0x10u
+#define CAN_CTRL1_LBUF_SHIFT                     4
+#define CAN_CTRL1_LBUF_WIDTH                     1
+#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK                      0x20u
+#define CAN_CTRL1_TSYN_SHIFT                     5
+#define CAN_CTRL1_TSYN_WIDTH                     1
+#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK                   0x40u
+#define CAN_CTRL1_BOFFREC_SHIFT                  6
+#define CAN_CTRL1_BOFFREC_WIDTH                  1
+#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK                       0x80u
+#define CAN_CTRL1_SMP_SHIFT                      7
+#define CAN_CTRL1_SMP_WIDTH                      1
+#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK                   0x400u
+#define CAN_CTRL1_RWRNMSK_SHIFT                  10
+#define CAN_CTRL1_RWRNMSK_WIDTH                  1
+#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK                   0x800u
+#define CAN_CTRL1_TWRNMSK_SHIFT                  11
+#define CAN_CTRL1_TWRNMSK_WIDTH                  1
+#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK                       0x1000u
+#define CAN_CTRL1_LPB_SHIFT                      12
+#define CAN_CTRL1_LPB_WIDTH                      1
+#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_CLKSRC_MASK                    0x2000u
+#define CAN_CTRL1_CLKSRC_SHIFT                   13
+#define CAN_CTRL1_CLKSRC_WIDTH                   1
+#define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_ERRMSK_MASK                    0x4000u
+#define CAN_CTRL1_ERRMSK_SHIFT                   14
+#define CAN_CTRL1_ERRMSK_WIDTH                   1
+#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK                   0x8000u
+#define CAN_CTRL1_BOFFMSK_SHIFT                  15
+#define CAN_CTRL1_BOFFMSK_WIDTH                  1
+#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK                     0x70000u
+#define CAN_CTRL1_PSEG2_SHIFT                    16
+#define CAN_CTRL1_PSEG2_WIDTH                    3
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK                     0x380000u
+#define CAN_CTRL1_PSEG1_SHIFT                    19
+#define CAN_CTRL1_PSEG1_WIDTH                    3
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK                       0xC00000u
+#define CAN_CTRL1_RJW_SHIFT                      22
+#define CAN_CTRL1_RJW_WIDTH                      2
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
+#define CAN_CTRL1_PRESDIV_SHIFT                  24
+#define CAN_CTRL1_PRESDIV_WIDTH                  8
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
+/* TIMER Bit Fields */
+#define CAN_TIMER_TIMER_MASK                     0xFFFFu
+#define CAN_TIMER_TIMER_SHIFT                    0
+#define CAN_TIMER_TIMER_WIDTH                    16
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
+/* RXMGMASK Bit Fields */
+#define CAN_RXMGMASK_MG_MASK                     0xFFFFFFFFu
+#define CAN_RXMGMASK_MG_SHIFT                    0
+#define CAN_RXMGMASK_MG_WIDTH                    32
+#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
+/* RX14MASK Bit Fields */
+#define CAN_RX14MASK_RX14M_MASK                  0xFFFFFFFFu
+#define CAN_RX14MASK_RX14M_SHIFT                 0
+#define CAN_RX14MASK_RX14M_WIDTH                 32
+#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
+/* RX15MASK Bit Fields */
+#define CAN_RX15MASK_RX15M_MASK                  0xFFFFFFFFu
+#define CAN_RX15MASK_RX15M_SHIFT                 0
+#define CAN_RX15MASK_RX15M_WIDTH                 32
+#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
+/* ECR Bit Fields */
+#define CAN_ECR_TXERRCNT_MASK                    0xFFu
+#define CAN_ECR_TXERRCNT_SHIFT                   0
+#define CAN_ECR_TXERRCNT_WIDTH                   8
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK                    0xFF00u
+#define CAN_ECR_RXERRCNT_SHIFT                   8
+#define CAN_ECR_RXERRCNT_WIDTH                   8
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
+/* ESR1 Bit Fields */
+#define CAN_ESR1_WAKINT_MASK                     0x1u
+#define CAN_ESR1_WAKINT_SHIFT                    0
+#define CAN_ESR1_WAKINT_WIDTH                    1
+#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_WAKINT_SHIFT))&CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_ERRINT_MASK                     0x2u
+#define CAN_ESR1_ERRINT_SHIFT                    1
+#define CAN_ESR1_ERRINT_WIDTH                    1
+#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK                    0x4u
+#define CAN_ESR1_BOFFINT_SHIFT                   2
+#define CAN_ESR1_BOFFINT_WIDTH                   1
+#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK                         0x8u
+#define CAN_ESR1_RX_SHIFT                        3
+#define CAN_ESR1_RX_WIDTH                        1
+#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK                    0x30u
+#define CAN_ESR1_FLTCONF_SHIFT                   4
+#define CAN_ESR1_FLTCONF_WIDTH                   2
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK                         0x40u
+#define CAN_ESR1_TX_SHIFT                        6
+#define CAN_ESR1_TX_WIDTH                        1
+#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK                       0x80u
+#define CAN_ESR1_IDLE_SHIFT                      7
+#define CAN_ESR1_IDLE_WIDTH                      1
+#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK                      0x100u
+#define CAN_ESR1_RXWRN_SHIFT                     8
+#define CAN_ESR1_RXWRN_WIDTH                     1
+#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK                      0x200u
+#define CAN_ESR1_TXWRN_SHIFT                     9
+#define CAN_ESR1_TXWRN_WIDTH                     1
+#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK                     0x400u
+#define CAN_ESR1_STFERR_SHIFT                    10
+#define CAN_ESR1_STFERR_WIDTH                    1
+#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK                     0x800u
+#define CAN_ESR1_FRMERR_SHIFT                    11
+#define CAN_ESR1_FRMERR_WIDTH                    1
+#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK                     0x1000u
+#define CAN_ESR1_CRCERR_SHIFT                    12
+#define CAN_ESR1_CRCERR_WIDTH                    1
+#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK                     0x2000u
+#define CAN_ESR1_ACKERR_SHIFT                    13
+#define CAN_ESR1_ACKERR_WIDTH                    1
+#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK                    0x4000u
+#define CAN_ESR1_BIT0ERR_SHIFT                   14
+#define CAN_ESR1_BIT0ERR_WIDTH                   1
+#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK                    0x8000u
+#define CAN_ESR1_BIT1ERR_SHIFT                   15
+#define CAN_ESR1_BIT1ERR_WIDTH                   1
+#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK                    0x10000u
+#define CAN_ESR1_RWRNINT_SHIFT                   16
+#define CAN_ESR1_RWRNINT_WIDTH                   1
+#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK                    0x20000u
+#define CAN_ESR1_TWRNINT_SHIFT                   17
+#define CAN_ESR1_TWRNINT_WIDTH                   1
+#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK                      0x40000u
+#define CAN_ESR1_SYNCH_SHIFT                     18
+#define CAN_ESR1_SYNCH_WIDTH                     1
+#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
+/* IMASK1 Bit Fields */
+#define CAN_IMASK1_BUFLM_MASK                    0xFFFFFFFFu
+#define CAN_IMASK1_BUFLM_SHIFT                   0
+#define CAN_IMASK1_BUFLM_WIDTH                   32
+#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
+/* IFLAG1 Bit Fields */
+#define CAN_IFLAG1_BUF0I_MASK                    0x1u
+#define CAN_IFLAG1_BUF0I_SHIFT                   0
+#define CAN_IFLAG1_BUF0I_WIDTH                   1
+#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF4TO1I_MASK                 0x1Eu
+#define CAN_IFLAG1_BUF4TO1I_SHIFT                1
+#define CAN_IFLAG1_BUF4TO1I_WIDTH                4
+#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK                    0x20u
+#define CAN_IFLAG1_BUF5I_SHIFT                   5
+#define CAN_IFLAG1_BUF5I_WIDTH                   1
+#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK                    0x40u
+#define CAN_IFLAG1_BUF6I_SHIFT                   6
+#define CAN_IFLAG1_BUF6I_WIDTH                   1
+#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK                    0x80u
+#define CAN_IFLAG1_BUF7I_SHIFT                   7
+#define CAN_IFLAG1_BUF7I_WIDTH                   1
+#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK                0xFFFFFF00u
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               8
+#define CAN_IFLAG1_BUF31TO8I_WIDTH               24
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
+/* CTRL2 Bit Fields */
+#define CAN_CTRL2_EACEN_MASK                     0x10000u
+#define CAN_CTRL2_EACEN_SHIFT                    16
+#define CAN_CTRL2_EACEN_WIDTH                    1
+#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK                       0x20000u
+#define CAN_CTRL2_RRS_SHIFT                      17
+#define CAN_CTRL2_RRS_WIDTH                      1
+#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK                       0x40000u
+#define CAN_CTRL2_MRP_SHIFT                      18
+#define CAN_CTRL2_MRP_WIDTH                      1
+#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK                      0xF80000u
+#define CAN_CTRL2_TASD_SHIFT                     19
+#define CAN_CTRL2_TASD_WIDTH                     5
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK                      0xF000000u
+#define CAN_CTRL2_RFFN_SHIFT                     24
+#define CAN_CTRL2_RFFN_WIDTH                     4
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK                    0x10000000u
+#define CAN_CTRL2_WRMFRZ_SHIFT                   28
+#define CAN_CTRL2_WRMFRZ_WIDTH                   1
+#define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_WRMFRZ_SHIFT))&CAN_CTRL2_WRMFRZ_MASK)
+/* ESR2 Bit Fields */
+#define CAN_ESR2_IMB_MASK                        0x2000u
+#define CAN_ESR2_IMB_SHIFT                       13
+#define CAN_ESR2_IMB_WIDTH                       1
+#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK                        0x4000u
+#define CAN_ESR2_VPS_SHIFT                       14
+#define CAN_ESR2_VPS_WIDTH                       1
+#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK                       0x7F0000u
+#define CAN_ESR2_LPTM_SHIFT                      16
+#define CAN_ESR2_LPTM_WIDTH                      7
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
+/* CRCR Bit Fields */
+#define CAN_CRCR_TXCRC_MASK                      0x7FFFu
+#define CAN_CRCR_TXCRC_SHIFT                     0
+#define CAN_CRCR_TXCRC_WIDTH                     15
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK                      0x7F0000u
+#define CAN_CRCR_MBCRC_SHIFT                     16
+#define CAN_CRCR_MBCRC_WIDTH                     7
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
+/* RXFGMASK Bit Fields */
+#define CAN_RXFGMASK_FGM_MASK                    0xFFFFFFFFu
+#define CAN_RXFGMASK_FGM_SHIFT                   0
+#define CAN_RXFGMASK_FGM_WIDTH                   32
+#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
+/* RXFIR Bit Fields */
+#define CAN_RXFIR_IDHIT_MASK                     0x1FFu
+#define CAN_RXFIR_IDHIT_SHIFT                    0
+#define CAN_RXFIR_IDHIT_WIDTH                    9
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
+/* CS Bit Fields */
+#define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
+#define CAN_CS_TIME_STAMP_SHIFT                  0
+#define CAN_CS_TIME_STAMP_WIDTH                  16
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK                          0xF0000u
+#define CAN_CS_DLC_SHIFT                         16
+#define CAN_CS_DLC_WIDTH                         4
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK                          0x100000u
+#define CAN_CS_RTR_SHIFT                         20
+#define CAN_CS_RTR_WIDTH                         1
+#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_RTR_SHIFT))&CAN_CS_RTR_MASK)
+#define CAN_CS_IDE_MASK                          0x200000u
+#define CAN_CS_IDE_SHIFT                         21
+#define CAN_CS_IDE_WIDTH                         1
+#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_IDE_SHIFT))&CAN_CS_IDE_MASK)
+#define CAN_CS_SRR_MASK                          0x400000u
+#define CAN_CS_SRR_SHIFT                         22
+#define CAN_CS_SRR_WIDTH                         1
+#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_SRR_SHIFT))&CAN_CS_SRR_MASK)
+#define CAN_CS_CODE_MASK                         0xF000000u
+#define CAN_CS_CODE_SHIFT                        24
+#define CAN_CS_CODE_WIDTH                        4
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
+/* ID Bit Fields */
+#define CAN_ID_EXT_MASK                          0x3FFFFu
+#define CAN_ID_EXT_SHIFT                         0
+#define CAN_ID_EXT_WIDTH                         18
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK                          0x1FFC0000u
+#define CAN_ID_STD_SHIFT                         18
+#define CAN_ID_STD_WIDTH                         11
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK                         0xE0000000u
+#define CAN_ID_PRIO_SHIFT                        29
+#define CAN_ID_PRIO_WIDTH                        3
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
+/* WORD0 Bit Fields */
+#define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              0
+#define CAN_WORD0_DATA_BYTE_3_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              8
+#define CAN_WORD0_DATA_BYTE_2_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              16
+#define CAN_WORD0_DATA_BYTE_1_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              24
+#define CAN_WORD0_DATA_BYTE_0_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
+/* WORD1 Bit Fields */
+#define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              0
+#define CAN_WORD1_DATA_BYTE_7_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              8
+#define CAN_WORD1_DATA_BYTE_6_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              16
+#define CAN_WORD1_DATA_BYTE_5_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              24
+#define CAN_WORD1_DATA_BYTE_4_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
+/* RXIMR Bit Fields */
+#define CAN_RXIMR_MI_MASK                        0xFFFFFFFFu
+#define CAN_RXIMR_MI_SHIFT                       0
+#define CAN_RXIMR_MI_WIDTH                       32
+#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+#define CAN0_BASE_PTR                            (CAN0)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS                      { CAN0_Rx_Warning_IRQn }
+#define CAN_Tx_Warning_IRQS                      { CAN0_Tx_Warning_IRQn }
+#define CAN_Wake_Up_IRQS                         { CAN0_Wake_Up_IRQn }
+#define CAN_Error_IRQS                           { CAN0_Error_IRQn }
+#define CAN_Bus_Off_IRQS                         { CAN0_Bus_Off_IRQn }
+#define CAN_ORed_Message_buffer_IRQS             { CAN0_ORed_Message_buffer_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register instance definitions */
+/* CAN0 */
+#define CAN0_MCR                                 CAN_MCR_REG(CAN0)
+#define CAN0_CTRL1                               CAN_CTRL1_REG(CAN0)
+#define CAN0_TIMER                               CAN_TIMER_REG(CAN0)
+#define CAN0_RXMGMASK                            CAN_RXMGMASK_REG(CAN0)
+#define CAN0_RX14MASK                            CAN_RX14MASK_REG(CAN0)
+#define CAN0_RX15MASK                            CAN_RX15MASK_REG(CAN0)
+#define CAN0_ECR                                 CAN_ECR_REG(CAN0)
+#define CAN0_ESR1                                CAN_ESR1_REG(CAN0)
+#define CAN0_IMASK1                              CAN_IMASK1_REG(CAN0)
+#define CAN0_IFLAG1                              CAN_IFLAG1_REG(CAN0)
+#define CAN0_CTRL2                               CAN_CTRL2_REG(CAN0)
+#define CAN0_ESR2                                CAN_ESR2_REG(CAN0)
+#define CAN0_CRCR                                CAN_CRCR_REG(CAN0)
+#define CAN0_RXFGMASK                            CAN_RXFGMASK_REG(CAN0)
+#define CAN0_RXFIR                               CAN_RXFIR_REG(CAN0)
+#define CAN0_CS0                                 CAN_CS_REG(CAN0,0)
+#define CAN0_ID0                                 CAN_ID_REG(CAN0,0)
+#define CAN0_WORD00                              CAN_WORD0_REG(CAN0,0)
+#define CAN0_WORD10                              CAN_WORD1_REG(CAN0,0)
+#define CAN0_CS1                                 CAN_CS_REG(CAN0,1)
+#define CAN0_ID1                                 CAN_ID_REG(CAN0,1)
+#define CAN0_WORD01                              CAN_WORD0_REG(CAN0,1)
+#define CAN0_WORD11                              CAN_WORD1_REG(CAN0,1)
+#define CAN0_CS2                                 CAN_CS_REG(CAN0,2)
+#define CAN0_ID2                                 CAN_ID_REG(CAN0,2)
+#define CAN0_WORD02                              CAN_WORD0_REG(CAN0,2)
+#define CAN0_WORD12                              CAN_WORD1_REG(CAN0,2)
+#define CAN0_CS3                                 CAN_CS_REG(CAN0,3)
+#define CAN0_ID3                                 CAN_ID_REG(CAN0,3)
+#define CAN0_WORD03                              CAN_WORD0_REG(CAN0,3)
+#define CAN0_WORD13                              CAN_WORD1_REG(CAN0,3)
+#define CAN0_CS4                                 CAN_CS_REG(CAN0,4)
+#define CAN0_ID4                                 CAN_ID_REG(CAN0,4)
+#define CAN0_WORD04                              CAN_WORD0_REG(CAN0,4)
+#define CAN0_WORD14                              CAN_WORD1_REG(CAN0,4)
+#define CAN0_CS5                                 CAN_CS_REG(CAN0,5)
+#define CAN0_ID5                                 CAN_ID_REG(CAN0,5)
+#define CAN0_WORD05                              CAN_WORD0_REG(CAN0,5)
+#define CAN0_WORD15                              CAN_WORD1_REG(CAN0,5)
+#define CAN0_CS6                                 CAN_CS_REG(CAN0,6)
+#define CAN0_ID6                                 CAN_ID_REG(CAN0,6)
+#define CAN0_WORD06                              CAN_WORD0_REG(CAN0,6)
+#define CAN0_WORD16                              CAN_WORD1_REG(CAN0,6)
+#define CAN0_CS7                                 CAN_CS_REG(CAN0,7)
+#define CAN0_ID7                                 CAN_ID_REG(CAN0,7)
+#define CAN0_WORD07                              CAN_WORD0_REG(CAN0,7)
+#define CAN0_WORD17                              CAN_WORD1_REG(CAN0,7)
+#define CAN0_CS8                                 CAN_CS_REG(CAN0,8)
+#define CAN0_ID8                                 CAN_ID_REG(CAN0,8)
+#define CAN0_WORD08                              CAN_WORD0_REG(CAN0,8)
+#define CAN0_WORD18                              CAN_WORD1_REG(CAN0,8)
+#define CAN0_CS9                                 CAN_CS_REG(CAN0,9)
+#define CAN0_ID9                                 CAN_ID_REG(CAN0,9)
+#define CAN0_WORD09                              CAN_WORD0_REG(CAN0,9)
+#define CAN0_WORD19                              CAN_WORD1_REG(CAN0,9)
+#define CAN0_CS10                                CAN_CS_REG(CAN0,10)
+#define CAN0_ID10                                CAN_ID_REG(CAN0,10)
+#define CAN0_WORD010                             CAN_WORD0_REG(CAN0,10)
+#define CAN0_WORD110                             CAN_WORD1_REG(CAN0,10)
+#define CAN0_CS11                                CAN_CS_REG(CAN0,11)
+#define CAN0_ID11                                CAN_ID_REG(CAN0,11)
+#define CAN0_WORD011                             CAN_WORD0_REG(CAN0,11)
+#define CAN0_WORD111                             CAN_WORD1_REG(CAN0,11)
+#define CAN0_CS12                                CAN_CS_REG(CAN0,12)
+#define CAN0_ID12                                CAN_ID_REG(CAN0,12)
+#define CAN0_WORD012                             CAN_WORD0_REG(CAN0,12)
+#define CAN0_WORD112                             CAN_WORD1_REG(CAN0,12)
+#define CAN0_CS13                                CAN_CS_REG(CAN0,13)
+#define CAN0_ID13                                CAN_ID_REG(CAN0,13)
+#define CAN0_WORD013                             CAN_WORD0_REG(CAN0,13)
+#define CAN0_WORD113                             CAN_WORD1_REG(CAN0,13)
+#define CAN0_CS14                                CAN_CS_REG(CAN0,14)
+#define CAN0_ID14                                CAN_ID_REG(CAN0,14)
+#define CAN0_WORD014                             CAN_WORD0_REG(CAN0,14)
+#define CAN0_WORD114                             CAN_WORD1_REG(CAN0,14)
+#define CAN0_CS15                                CAN_CS_REG(CAN0,15)
+#define CAN0_ID15                                CAN_ID_REG(CAN0,15)
+#define CAN0_WORD015                             CAN_WORD0_REG(CAN0,15)
+#define CAN0_WORD115                             CAN_WORD1_REG(CAN0,15)
+#define CAN0_RXIMR0                              CAN_RXIMR_REG(CAN0,0)
+#define CAN0_RXIMR1                              CAN_RXIMR_REG(CAN0,1)
+#define CAN0_RXIMR2                              CAN_RXIMR_REG(CAN0,2)
+#define CAN0_RXIMR3                              CAN_RXIMR_REG(CAN0,3)
+#define CAN0_RXIMR4                              CAN_RXIMR_REG(CAN0,4)
+#define CAN0_RXIMR5                              CAN_RXIMR_REG(CAN0,5)
+#define CAN0_RXIMR6                              CAN_RXIMR_REG(CAN0,6)
+#define CAN0_RXIMR7                              CAN_RXIMR_REG(CAN0,7)
+#define CAN0_RXIMR8                              CAN_RXIMR_REG(CAN0,8)
+#define CAN0_RXIMR9                              CAN_RXIMR_REG(CAN0,9)
+#define CAN0_RXIMR10                             CAN_RXIMR_REG(CAN0,10)
+#define CAN0_RXIMR11                             CAN_RXIMR_REG(CAN0,11)
+#define CAN0_RXIMR12                             CAN_RXIMR_REG(CAN0,12)
+#define CAN0_RXIMR13                             CAN_RXIMR_REG(CAN0,13)
+#define CAN0_RXIMR14                             CAN_RXIMR_REG(CAN0,14)
+#define CAN0_RXIMR15                             CAN_RXIMR_REG(CAN0,15)
+
+/* CAN - Register array accessors */
+#define CAN0_CS(index)                           CAN_CS_REG(CAN0,index)
+#define CAN0_ID(index)                           CAN_ID_REG(CAN0,index)
+#define CAN0_WORD0(index)                        CAN_WORD0_REG(CAN0,index)
+#define CAN0_WORD1(index)                        CAN_WORD1_REG(CAN0,index)
+#define CAN0_RXIMR(index)                        CAN_RXIMR_REG(CAN0,index)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+  __O  uint32_t DIRECT[16];                        /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[2048];
+  __O  uint32_t LDR_CASR;                          /**< Status register - Load Register command, offset: 0x840 */
+  __O  uint32_t LDR_CAA;                           /**< Accumulator register - Load Register command, offset: 0x844 */
+  __O  uint32_t LDR_CA[9];                         /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
+       uint8_t RESERVED_1[20];
+  __I  uint32_t STR_CASR;                          /**< Status register - Store Register command, offset: 0x880 */
+  __I  uint32_t STR_CAA;                           /**< Accumulator register - Store Register command, offset: 0x884 */
+  __I  uint32_t STR_CA[9];                         /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
+       uint8_t RESERVED_2[20];
+  __O  uint32_t ADR_CASR;                          /**< Status register - Add Register command, offset: 0x8C0 */
+  __O  uint32_t ADR_CAA;                           /**< Accumulator register - Add to register command, offset: 0x8C4 */
+  __O  uint32_t ADR_CA[9];                         /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
+       uint8_t RESERVED_3[20];
+  __O  uint32_t RADR_CASR;                         /**< Status register - Reverse and Add to Register command, offset: 0x900 */
+  __O  uint32_t RADR_CAA;                          /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
+  __O  uint32_t RADR_CA[9];                        /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
+       uint8_t RESERVED_4[84];
+  __O  uint32_t XOR_CASR;                          /**< Status register - Exclusive Or command, offset: 0x980 */
+  __O  uint32_t XOR_CAA;                           /**< Accumulator register - Exclusive Or command, offset: 0x984 */
+  __O  uint32_t XOR_CA[9];                         /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
+       uint8_t RESERVED_5[20];
+  __O  uint32_t ROTL_CASR;                         /**< Status register - Rotate Left command, offset: 0x9C0 */
+  __O  uint32_t ROTL_CAA;                          /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
+  __O  uint32_t ROTL_CA[9];                        /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
+       uint8_t RESERVED_6[276];
+  __O  uint32_t AESC_CASR;                         /**< Status register - AES Column Operation command, offset: 0xB00 */
+  __O  uint32_t AESC_CAA;                          /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
+  __O  uint32_t AESC_CA[9];                        /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
+       uint8_t RESERVED_7[20];
+  __O  uint32_t AESIC_CASR;                        /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
+  __O  uint32_t AESIC_CAA;                         /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
+  __O  uint32_t AESIC_CA[9];                       /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
+} CAU_Type, *CAU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register accessors */
+#define CAU_DIRECT_REG(base,index)               ((base)->DIRECT[index])
+#define CAU_DIRECT_COUNT                         16
+#define CAU_LDR_CASR_REG(base)                   ((base)->LDR_CASR)
+#define CAU_LDR_CAA_REG(base)                    ((base)->LDR_CAA)
+#define CAU_LDR_CA_REG(base,index)               ((base)->LDR_CA[index])
+#define CAU_LDR_CA_COUNT                         9
+#define CAU_STR_CASR_REG(base)                   ((base)->STR_CASR)
+#define CAU_STR_CAA_REG(base)                    ((base)->STR_CAA)
+#define CAU_STR_CA_REG(base,index)               ((base)->STR_CA[index])
+#define CAU_STR_CA_COUNT                         9
+#define CAU_ADR_CASR_REG(base)                   ((base)->ADR_CASR)
+#define CAU_ADR_CAA_REG(base)                    ((base)->ADR_CAA)
+#define CAU_ADR_CA_REG(base,index)               ((base)->ADR_CA[index])
+#define CAU_ADR_CA_COUNT                         9
+#define CAU_RADR_CASR_REG(base)                  ((base)->RADR_CASR)
+#define CAU_RADR_CAA_REG(base)                   ((base)->RADR_CAA)
+#define CAU_RADR_CA_REG(base,index)              ((base)->RADR_CA[index])
+#define CAU_RADR_CA_COUNT                        9
+#define CAU_XOR_CASR_REG(base)                   ((base)->XOR_CASR)
+#define CAU_XOR_CAA_REG(base)                    ((base)->XOR_CAA)
+#define CAU_XOR_CA_REG(base,index)               ((base)->XOR_CA[index])
+#define CAU_XOR_CA_COUNT                         9
+#define CAU_ROTL_CASR_REG(base)                  ((base)->ROTL_CASR)
+#define CAU_ROTL_CAA_REG(base)                   ((base)->ROTL_CAA)
+#define CAU_ROTL_CA_REG(base,index)              ((base)->ROTL_CA[index])
+#define CAU_ROTL_CA_COUNT                        9
+#define CAU_AESC_CASR_REG(base)                  ((base)->AESC_CASR)
+#define CAU_AESC_CAA_REG(base)                   ((base)->AESC_CAA)
+#define CAU_AESC_CA_REG(base,index)              ((base)->AESC_CA[index])
+#define CAU_AESC_CA_COUNT                        9
+#define CAU_AESIC_CASR_REG(base)                 ((base)->AESIC_CASR)
+#define CAU_AESIC_CAA_REG(base)                  ((base)->AESIC_CAA)
+#define CAU_AESIC_CA_REG(base,index)             ((base)->AESIC_CA[index])
+#define CAU_AESIC_CA_COUNT                       9
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/* DIRECT Bit Fields */
+#define CAU_DIRECT_CAU_DIRECT0_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT0_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT0_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT0(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
+#define CAU_DIRECT_CAU_DIRECT1_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT1_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT1_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT1(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
+#define CAU_DIRECT_CAU_DIRECT2_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT2_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT2_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT2(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
+#define CAU_DIRECT_CAU_DIRECT3_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT3_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT3_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT3(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
+#define CAU_DIRECT_CAU_DIRECT4_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT4_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT4_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT4(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
+#define CAU_DIRECT_CAU_DIRECT5_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT5_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT5_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT5(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
+#define CAU_DIRECT_CAU_DIRECT6_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT6_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT6_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT6(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
+#define CAU_DIRECT_CAU_DIRECT7_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT7_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT7_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT7(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
+#define CAU_DIRECT_CAU_DIRECT8_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT8_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT8_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT8(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
+#define CAU_DIRECT_CAU_DIRECT9_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT9_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT9_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT9(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
+#define CAU_DIRECT_CAU_DIRECT10_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT10_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT10_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT10(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
+#define CAU_DIRECT_CAU_DIRECT11_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT11_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT11_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT11(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
+#define CAU_DIRECT_CAU_DIRECT12_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT12_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT12_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT12(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
+#define CAU_DIRECT_CAU_DIRECT13_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT13_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT13_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT13(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
+#define CAU_DIRECT_CAU_DIRECT14_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT14_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT14_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT14(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
+#define CAU_DIRECT_CAU_DIRECT15_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT15_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT15_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT15(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
+/* LDR_CASR Bit Fields */
+#define CAU_LDR_CASR_IC_MASK                     0x1u
+#define CAU_LDR_CASR_IC_SHIFT                    0
+#define CAU_LDR_CASR_IC_WIDTH                    1
+#define CAU_LDR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_IC_SHIFT))&CAU_LDR_CASR_IC_MASK)
+#define CAU_LDR_CASR_DPE_MASK                    0x2u
+#define CAU_LDR_CASR_DPE_SHIFT                   1
+#define CAU_LDR_CASR_DPE_WIDTH                   1
+#define CAU_LDR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_DPE_SHIFT))&CAU_LDR_CASR_DPE_MASK)
+#define CAU_LDR_CASR_VER_MASK                    0xF0000000u
+#define CAU_LDR_CASR_VER_SHIFT                   28
+#define CAU_LDR_CASR_VER_WIDTH                   4
+#define CAU_LDR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
+/* LDR_CAA Bit Fields */
+#define CAU_LDR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_LDR_CAA_ACC_SHIFT                    0
+#define CAU_LDR_CAA_ACC_WIDTH                    32
+#define CAU_LDR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
+/* LDR_CA Bit Fields */
+#define CAU_LDR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA0_SHIFT                     0
+#define CAU_LDR_CA_CA0_WIDTH                     32
+#define CAU_LDR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
+#define CAU_LDR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA1_SHIFT                     0
+#define CAU_LDR_CA_CA1_WIDTH                     32
+#define CAU_LDR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
+#define CAU_LDR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA2_SHIFT                     0
+#define CAU_LDR_CA_CA2_WIDTH                     32
+#define CAU_LDR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
+#define CAU_LDR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA3_SHIFT                     0
+#define CAU_LDR_CA_CA3_WIDTH                     32
+#define CAU_LDR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
+#define CAU_LDR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA4_SHIFT                     0
+#define CAU_LDR_CA_CA4_WIDTH                     32
+#define CAU_LDR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
+#define CAU_LDR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA5_SHIFT                     0
+#define CAU_LDR_CA_CA5_WIDTH                     32
+#define CAU_LDR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
+#define CAU_LDR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA6_SHIFT                     0
+#define CAU_LDR_CA_CA6_WIDTH                     32
+#define CAU_LDR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
+#define CAU_LDR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA7_SHIFT                     0
+#define CAU_LDR_CA_CA7_WIDTH                     32
+#define CAU_LDR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
+#define CAU_LDR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA8_SHIFT                     0
+#define CAU_LDR_CA_CA8_WIDTH                     32
+#define CAU_LDR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
+/* STR_CASR Bit Fields */
+#define CAU_STR_CASR_IC_MASK                     0x1u
+#define CAU_STR_CASR_IC_SHIFT                    0
+#define CAU_STR_CASR_IC_WIDTH                    1
+#define CAU_STR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_IC_SHIFT))&CAU_STR_CASR_IC_MASK)
+#define CAU_STR_CASR_DPE_MASK                    0x2u
+#define CAU_STR_CASR_DPE_SHIFT                   1
+#define CAU_STR_CASR_DPE_WIDTH                   1
+#define CAU_STR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_DPE_SHIFT))&CAU_STR_CASR_DPE_MASK)
+#define CAU_STR_CASR_VER_MASK                    0xF0000000u
+#define CAU_STR_CASR_VER_SHIFT                   28
+#define CAU_STR_CASR_VER_WIDTH                   4
+#define CAU_STR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
+/* STR_CAA Bit Fields */
+#define CAU_STR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_STR_CAA_ACC_SHIFT                    0
+#define CAU_STR_CAA_ACC_WIDTH                    32
+#define CAU_STR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
+/* STR_CA Bit Fields */
+#define CAU_STR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA0_SHIFT                     0
+#define CAU_STR_CA_CA0_WIDTH                     32
+#define CAU_STR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
+#define CAU_STR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA1_SHIFT                     0
+#define CAU_STR_CA_CA1_WIDTH                     32
+#define CAU_STR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
+#define CAU_STR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA2_SHIFT                     0
+#define CAU_STR_CA_CA2_WIDTH                     32
+#define CAU_STR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
+#define CAU_STR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA3_SHIFT                     0
+#define CAU_STR_CA_CA3_WIDTH                     32
+#define CAU_STR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
+#define CAU_STR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA4_SHIFT                     0
+#define CAU_STR_CA_CA4_WIDTH                     32
+#define CAU_STR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
+#define CAU_STR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA5_SHIFT                     0
+#define CAU_STR_CA_CA5_WIDTH                     32
+#define CAU_STR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
+#define CAU_STR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA6_SHIFT                     0
+#define CAU_STR_CA_CA6_WIDTH                     32
+#define CAU_STR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
+#define CAU_STR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA7_SHIFT                     0
+#define CAU_STR_CA_CA7_WIDTH                     32
+#define CAU_STR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
+#define CAU_STR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA8_SHIFT                     0
+#define CAU_STR_CA_CA8_WIDTH                     32
+#define CAU_STR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
+/* ADR_CASR Bit Fields */
+#define CAU_ADR_CASR_IC_MASK                     0x1u
+#define CAU_ADR_CASR_IC_SHIFT                    0
+#define CAU_ADR_CASR_IC_WIDTH                    1
+#define CAU_ADR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_IC_SHIFT))&CAU_ADR_CASR_IC_MASK)
+#define CAU_ADR_CASR_DPE_MASK                    0x2u
+#define CAU_ADR_CASR_DPE_SHIFT                   1
+#define CAU_ADR_CASR_DPE_WIDTH                   1
+#define CAU_ADR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_DPE_SHIFT))&CAU_ADR_CASR_DPE_MASK)
+#define CAU_ADR_CASR_VER_MASK                    0xF0000000u
+#define CAU_ADR_CASR_VER_SHIFT                   28
+#define CAU_ADR_CASR_VER_WIDTH                   4
+#define CAU_ADR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
+/* ADR_CAA Bit Fields */
+#define CAU_ADR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_ADR_CAA_ACC_SHIFT                    0
+#define CAU_ADR_CAA_ACC_WIDTH                    32
+#define CAU_ADR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
+/* ADR_CA Bit Fields */
+#define CAU_ADR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA0_SHIFT                     0
+#define CAU_ADR_CA_CA0_WIDTH                     32
+#define CAU_ADR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
+#define CAU_ADR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA1_SHIFT                     0
+#define CAU_ADR_CA_CA1_WIDTH                     32
+#define CAU_ADR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
+#define CAU_ADR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA2_SHIFT                     0
+#define CAU_ADR_CA_CA2_WIDTH                     32
+#define CAU_ADR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
+#define CAU_ADR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA3_SHIFT                     0
+#define CAU_ADR_CA_CA3_WIDTH                     32
+#define CAU_ADR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
+#define CAU_ADR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA4_SHIFT                     0
+#define CAU_ADR_CA_CA4_WIDTH                     32
+#define CAU_ADR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
+#define CAU_ADR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA5_SHIFT                     0
+#define CAU_ADR_CA_CA5_WIDTH                     32
+#define CAU_ADR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
+#define CAU_ADR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA6_SHIFT                     0
+#define CAU_ADR_CA_CA6_WIDTH                     32
+#define CAU_ADR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
+#define CAU_ADR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA7_SHIFT                     0
+#define CAU_ADR_CA_CA7_WIDTH                     32
+#define CAU_ADR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
+#define CAU_ADR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA8_SHIFT                     0
+#define CAU_ADR_CA_CA8_WIDTH                     32
+#define CAU_ADR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
+/* RADR_CASR Bit Fields */
+#define CAU_RADR_CASR_IC_MASK                    0x1u
+#define CAU_RADR_CASR_IC_SHIFT                   0
+#define CAU_RADR_CASR_IC_WIDTH                   1
+#define CAU_RADR_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_IC_SHIFT))&CAU_RADR_CASR_IC_MASK)
+#define CAU_RADR_CASR_DPE_MASK                   0x2u
+#define CAU_RADR_CASR_DPE_SHIFT                  1
+#define CAU_RADR_CASR_DPE_WIDTH                  1
+#define CAU_RADR_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_DPE_SHIFT))&CAU_RADR_CASR_DPE_MASK)
+#define CAU_RADR_CASR_VER_MASK                   0xF0000000u
+#define CAU_RADR_CASR_VER_SHIFT                  28
+#define CAU_RADR_CASR_VER_WIDTH                  4
+#define CAU_RADR_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
+/* RADR_CAA Bit Fields */
+#define CAU_RADR_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_RADR_CAA_ACC_SHIFT                   0
+#define CAU_RADR_CAA_ACC_WIDTH                   32
+#define CAU_RADR_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
+/* RADR_CA Bit Fields */
+#define CAU_RADR_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA0_SHIFT                    0
+#define CAU_RADR_CA_CA0_WIDTH                    32
+#define CAU_RADR_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
+#define CAU_RADR_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA1_SHIFT                    0
+#define CAU_RADR_CA_CA1_WIDTH                    32
+#define CAU_RADR_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
+#define CAU_RADR_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA2_SHIFT                    0
+#define CAU_RADR_CA_CA2_WIDTH                    32
+#define CAU_RADR_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
+#define CAU_RADR_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA3_SHIFT                    0
+#define CAU_RADR_CA_CA3_WIDTH                    32
+#define CAU_RADR_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
+#define CAU_RADR_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA4_SHIFT                    0
+#define CAU_RADR_CA_CA4_WIDTH                    32
+#define CAU_RADR_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
+#define CAU_RADR_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA5_SHIFT                    0
+#define CAU_RADR_CA_CA5_WIDTH                    32
+#define CAU_RADR_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
+#define CAU_RADR_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA6_SHIFT                    0
+#define CAU_RADR_CA_CA6_WIDTH                    32
+#define CAU_RADR_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
+#define CAU_RADR_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA7_SHIFT                    0
+#define CAU_RADR_CA_CA7_WIDTH                    32
+#define CAU_RADR_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
+#define CAU_RADR_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA8_SHIFT                    0
+#define CAU_RADR_CA_CA8_WIDTH                    32
+#define CAU_RADR_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
+/* XOR_CASR Bit Fields */
+#define CAU_XOR_CASR_IC_MASK                     0x1u
+#define CAU_XOR_CASR_IC_SHIFT                    0
+#define CAU_XOR_CASR_IC_WIDTH                    1
+#define CAU_XOR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_IC_SHIFT))&CAU_XOR_CASR_IC_MASK)
+#define CAU_XOR_CASR_DPE_MASK                    0x2u
+#define CAU_XOR_CASR_DPE_SHIFT                   1
+#define CAU_XOR_CASR_DPE_WIDTH                   1
+#define CAU_XOR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_DPE_SHIFT))&CAU_XOR_CASR_DPE_MASK)
+#define CAU_XOR_CASR_VER_MASK                    0xF0000000u
+#define CAU_XOR_CASR_VER_SHIFT                   28
+#define CAU_XOR_CASR_VER_WIDTH                   4
+#define CAU_XOR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
+/* XOR_CAA Bit Fields */
+#define CAU_XOR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_XOR_CAA_ACC_SHIFT                    0
+#define CAU_XOR_CAA_ACC_WIDTH                    32
+#define CAU_XOR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
+/* XOR_CA Bit Fields */
+#define CAU_XOR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA0_SHIFT                     0
+#define CAU_XOR_CA_CA0_WIDTH                     32
+#define CAU_XOR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
+#define CAU_XOR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA1_SHIFT                     0
+#define CAU_XOR_CA_CA1_WIDTH                     32
+#define CAU_XOR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
+#define CAU_XOR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA2_SHIFT                     0
+#define CAU_XOR_CA_CA2_WIDTH                     32
+#define CAU_XOR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
+#define CAU_XOR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA3_SHIFT                     0
+#define CAU_XOR_CA_CA3_WIDTH                     32
+#define CAU_XOR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
+#define CAU_XOR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA4_SHIFT                     0
+#define CAU_XOR_CA_CA4_WIDTH                     32
+#define CAU_XOR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
+#define CAU_XOR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA5_SHIFT                     0
+#define CAU_XOR_CA_CA5_WIDTH                     32
+#define CAU_XOR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
+#define CAU_XOR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA6_SHIFT                     0
+#define CAU_XOR_CA_CA6_WIDTH                     32
+#define CAU_XOR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
+#define CAU_XOR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA7_SHIFT                     0
+#define CAU_XOR_CA_CA7_WIDTH                     32
+#define CAU_XOR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
+#define CAU_XOR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA8_SHIFT                     0
+#define CAU_XOR_CA_CA8_WIDTH                     32
+#define CAU_XOR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
+/* ROTL_CASR Bit Fields */
+#define CAU_ROTL_CASR_IC_MASK                    0x1u
+#define CAU_ROTL_CASR_IC_SHIFT                   0
+#define CAU_ROTL_CASR_IC_WIDTH                   1
+#define CAU_ROTL_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_IC_SHIFT))&CAU_ROTL_CASR_IC_MASK)
+#define CAU_ROTL_CASR_DPE_MASK                   0x2u
+#define CAU_ROTL_CASR_DPE_SHIFT                  1
+#define CAU_ROTL_CASR_DPE_WIDTH                  1
+#define CAU_ROTL_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_DPE_SHIFT))&CAU_ROTL_CASR_DPE_MASK)
+#define CAU_ROTL_CASR_VER_MASK                   0xF0000000u
+#define CAU_ROTL_CASR_VER_SHIFT                  28
+#define CAU_ROTL_CASR_VER_WIDTH                  4
+#define CAU_ROTL_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
+/* ROTL_CAA Bit Fields */
+#define CAU_ROTL_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_ROTL_CAA_ACC_SHIFT                   0
+#define CAU_ROTL_CAA_ACC_WIDTH                   32
+#define CAU_ROTL_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
+/* ROTL_CA Bit Fields */
+#define CAU_ROTL_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA0_SHIFT                    0
+#define CAU_ROTL_CA_CA0_WIDTH                    32
+#define CAU_ROTL_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
+#define CAU_ROTL_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA1_SHIFT                    0
+#define CAU_ROTL_CA_CA1_WIDTH                    32
+#define CAU_ROTL_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
+#define CAU_ROTL_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA2_SHIFT                    0
+#define CAU_ROTL_CA_CA2_WIDTH                    32
+#define CAU_ROTL_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
+#define CAU_ROTL_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA3_SHIFT                    0
+#define CAU_ROTL_CA_CA3_WIDTH                    32
+#define CAU_ROTL_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
+#define CAU_ROTL_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA4_SHIFT                    0
+#define CAU_ROTL_CA_CA4_WIDTH                    32
+#define CAU_ROTL_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
+#define CAU_ROTL_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA5_SHIFT                    0
+#define CAU_ROTL_CA_CA5_WIDTH                    32
+#define CAU_ROTL_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
+#define CAU_ROTL_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA6_SHIFT                    0
+#define CAU_ROTL_CA_CA6_WIDTH                    32
+#define CAU_ROTL_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
+#define CAU_ROTL_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA7_SHIFT                    0
+#define CAU_ROTL_CA_CA7_WIDTH                    32
+#define CAU_ROTL_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
+#define CAU_ROTL_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA8_SHIFT                    0
+#define CAU_ROTL_CA_CA8_WIDTH                    32
+#define CAU_ROTL_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
+/* AESC_CASR Bit Fields */
+#define CAU_AESC_CASR_IC_MASK                    0x1u
+#define CAU_AESC_CASR_IC_SHIFT                   0
+#define CAU_AESC_CASR_IC_WIDTH                   1
+#define CAU_AESC_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_IC_SHIFT))&CAU_AESC_CASR_IC_MASK)
+#define CAU_AESC_CASR_DPE_MASK                   0x2u
+#define CAU_AESC_CASR_DPE_SHIFT                  1
+#define CAU_AESC_CASR_DPE_WIDTH                  1
+#define CAU_AESC_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_DPE_SHIFT))&CAU_AESC_CASR_DPE_MASK)
+#define CAU_AESC_CASR_VER_MASK                   0xF0000000u
+#define CAU_AESC_CASR_VER_SHIFT                  28
+#define CAU_AESC_CASR_VER_WIDTH                  4
+#define CAU_AESC_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
+/* AESC_CAA Bit Fields */
+#define CAU_AESC_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_AESC_CAA_ACC_SHIFT                   0
+#define CAU_AESC_CAA_ACC_WIDTH                   32
+#define CAU_AESC_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
+/* AESC_CA Bit Fields */
+#define CAU_AESC_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA0_SHIFT                    0
+#define CAU_AESC_CA_CA0_WIDTH                    32
+#define CAU_AESC_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
+#define CAU_AESC_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA1_SHIFT                    0
+#define CAU_AESC_CA_CA1_WIDTH                    32
+#define CAU_AESC_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
+#define CAU_AESC_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA2_SHIFT                    0
+#define CAU_AESC_CA_CA2_WIDTH                    32
+#define CAU_AESC_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
+#define CAU_AESC_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA3_SHIFT                    0
+#define CAU_AESC_CA_CA3_WIDTH                    32
+#define CAU_AESC_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
+#define CAU_AESC_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA4_SHIFT                    0
+#define CAU_AESC_CA_CA4_WIDTH                    32
+#define CAU_AESC_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
+#define CAU_AESC_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA5_SHIFT                    0
+#define CAU_AESC_CA_CA5_WIDTH                    32
+#define CAU_AESC_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
+#define CAU_AESC_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA6_SHIFT                    0
+#define CAU_AESC_CA_CA6_WIDTH                    32
+#define CAU_AESC_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
+#define CAU_AESC_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA7_SHIFT                    0
+#define CAU_AESC_CA_CA7_WIDTH                    32
+#define CAU_AESC_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
+#define CAU_AESC_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA8_SHIFT                    0
+#define CAU_AESC_CA_CA8_WIDTH                    32
+#define CAU_AESC_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
+/* AESIC_CASR Bit Fields */
+#define CAU_AESIC_CASR_IC_MASK                   0x1u
+#define CAU_AESIC_CASR_IC_SHIFT                  0
+#define CAU_AESIC_CASR_IC_WIDTH                  1
+#define CAU_AESIC_CASR_IC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_IC_SHIFT))&CAU_AESIC_CASR_IC_MASK)
+#define CAU_AESIC_CASR_DPE_MASK                  0x2u
+#define CAU_AESIC_CASR_DPE_SHIFT                 1
+#define CAU_AESIC_CASR_DPE_WIDTH                 1
+#define CAU_AESIC_CASR_DPE(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_DPE_SHIFT))&CAU_AESIC_CASR_DPE_MASK)
+#define CAU_AESIC_CASR_VER_MASK                  0xF0000000u
+#define CAU_AESIC_CASR_VER_SHIFT                 28
+#define CAU_AESIC_CASR_VER_WIDTH                 4
+#define CAU_AESIC_CASR_VER(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
+/* AESIC_CAA Bit Fields */
+#define CAU_AESIC_CAA_ACC_MASK                   0xFFFFFFFFu
+#define CAU_AESIC_CAA_ACC_SHIFT                  0
+#define CAU_AESIC_CAA_ACC_WIDTH                  32
+#define CAU_AESIC_CAA_ACC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
+/* AESIC_CA Bit Fields */
+#define CAU_AESIC_CA_CA0_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA0_SHIFT                   0
+#define CAU_AESIC_CA_CA0_WIDTH                   32
+#define CAU_AESIC_CA_CA0(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
+#define CAU_AESIC_CA_CA1_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA1_SHIFT                   0
+#define CAU_AESIC_CA_CA1_WIDTH                   32
+#define CAU_AESIC_CA_CA1(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
+#define CAU_AESIC_CA_CA2_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA2_SHIFT                   0
+#define CAU_AESIC_CA_CA2_WIDTH                   32
+#define CAU_AESIC_CA_CA2(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
+#define CAU_AESIC_CA_CA3_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA3_SHIFT                   0
+#define CAU_AESIC_CA_CA3_WIDTH                   32
+#define CAU_AESIC_CA_CA3(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
+#define CAU_AESIC_CA_CA4_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA4_SHIFT                   0
+#define CAU_AESIC_CA_CA4_WIDTH                   32
+#define CAU_AESIC_CA_CA4(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
+#define CAU_AESIC_CA_CA5_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA5_SHIFT                   0
+#define CAU_AESIC_CA_CA5_WIDTH                   32
+#define CAU_AESIC_CA_CA5(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
+#define CAU_AESIC_CA_CA6_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA6_SHIFT                   0
+#define CAU_AESIC_CA_CA6_WIDTH                   32
+#define CAU_AESIC_CA_CA6(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
+#define CAU_AESIC_CA_CA7_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA7_SHIFT                   0
+#define CAU_AESIC_CA_CA7_WIDTH                   32
+#define CAU_AESIC_CA_CA7(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
+#define CAU_AESIC_CA_CA8_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA8_SHIFT                   0
+#define CAU_AESIC_CA_CA8_WIDTH                   32
+#define CAU_AESIC_CA_CA8(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+/** Peripheral CAU base address */
+#define CAU_BASE                                 (0xE0081000u)
+/** Peripheral CAU base pointer */
+#define CAU                                      ((CAU_Type *)CAU_BASE)
+#define CAU_BASE_PTR                             (CAU)
+/** Array initializer of CAU peripheral base addresses */
+#define CAU_BASE_ADDRS                           { CAU_BASE }
+/** Array initializer of CAU peripheral base pointers */
+#define CAU_BASE_PTRS                            { CAU }
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register instance definitions */
+/* CAU */
+#define CAU_DIRECT0                              CAU_DIRECT_REG(CAU,0)
+#define CAU_DIRECT1                              CAU_DIRECT_REG(CAU,1)
+#define CAU_DIRECT2                              CAU_DIRECT_REG(CAU,2)
+#define CAU_DIRECT3                              CAU_DIRECT_REG(CAU,3)
+#define CAU_DIRECT4                              CAU_DIRECT_REG(CAU,4)
+#define CAU_DIRECT5                              CAU_DIRECT_REG(CAU,5)
+#define CAU_DIRECT6                              CAU_DIRECT_REG(CAU,6)
+#define CAU_DIRECT7                              CAU_DIRECT_REG(CAU,7)
+#define CAU_DIRECT8                              CAU_DIRECT_REG(CAU,8)
+#define CAU_DIRECT9                              CAU_DIRECT_REG(CAU,9)
+#define CAU_DIRECT10                             CAU_DIRECT_REG(CAU,10)
+#define CAU_DIRECT11                             CAU_DIRECT_REG(CAU,11)
+#define CAU_DIRECT12                             CAU_DIRECT_REG(CAU,12)
+#define CAU_DIRECT13                             CAU_DIRECT_REG(CAU,13)
+#define CAU_DIRECT14                             CAU_DIRECT_REG(CAU,14)
+#define CAU_DIRECT15                             CAU_DIRECT_REG(CAU,15)
+#define CAU_LDR_CASR                             CAU_LDR_CASR_REG(CAU)
+#define CAU_LDR_CAA                              CAU_LDR_CAA_REG(CAU)
+#define CAU_LDR_CA0                              CAU_LDR_CA_REG(CAU,0)
+#define CAU_LDR_CA1                              CAU_LDR_CA_REG(CAU,1)
+#define CAU_LDR_CA2                              CAU_LDR_CA_REG(CAU,2)
+#define CAU_LDR_CA3                              CAU_LDR_CA_REG(CAU,3)
+#define CAU_LDR_CA4                              CAU_LDR_CA_REG(CAU,4)
+#define CAU_LDR_CA5                              CAU_LDR_CA_REG(CAU,5)
+#define CAU_LDR_CA6                              CAU_LDR_CA_REG(CAU,6)
+#define CAU_LDR_CA7                              CAU_LDR_CA_REG(CAU,7)
+#define CAU_LDR_CA8                              CAU_LDR_CA_REG(CAU,8)
+#define CAU_STR_CASR                             CAU_STR_CASR_REG(CAU)
+#define CAU_STR_CAA                              CAU_STR_CAA_REG(CAU)
+#define CAU_STR_CA0                              CAU_STR_CA_REG(CAU,0)
+#define CAU_STR_CA1                              CAU_STR_CA_REG(CAU,1)
+#define CAU_STR_CA2                              CAU_STR_CA_REG(CAU,2)
+#define CAU_STR_CA3                              CAU_STR_CA_REG(CAU,3)
+#define CAU_STR_CA4                              CAU_STR_CA_REG(CAU,4)
+#define CAU_STR_CA5                              CAU_STR_CA_REG(CAU,5)
+#define CAU_STR_CA6                              CAU_STR_CA_REG(CAU,6)
+#define CAU_STR_CA7                              CAU_STR_CA_REG(CAU,7)
+#define CAU_STR_CA8                              CAU_STR_CA_REG(CAU,8)
+#define CAU_ADR_CASR                             CAU_ADR_CASR_REG(CAU)
+#define CAU_ADR_CAA                              CAU_ADR_CAA_REG(CAU)
+#define CAU_ADR_CA0                              CAU_ADR_CA_REG(CAU,0)
+#define CAU_ADR_CA1                              CAU_ADR_CA_REG(CAU,1)
+#define CAU_ADR_CA2                              CAU_ADR_CA_REG(CAU,2)
+#define CAU_ADR_CA3                              CAU_ADR_CA_REG(CAU,3)
+#define CAU_ADR_CA4                              CAU_ADR_CA_REG(CAU,4)
+#define CAU_ADR_CA5                              CAU_ADR_CA_REG(CAU,5)
+#define CAU_ADR_CA6                              CAU_ADR_CA_REG(CAU,6)
+#define CAU_ADR_CA7                              CAU_ADR_CA_REG(CAU,7)
+#define CAU_ADR_CA8                              CAU_ADR_CA_REG(CAU,8)
+#define CAU_RADR_CASR                            CAU_RADR_CASR_REG(CAU)
+#define CAU_RADR_CAA                             CAU_RADR_CAA_REG(CAU)
+#define CAU_RADR_CA0                             CAU_RADR_CA_REG(CAU,0)
+#define CAU_RADR_CA1                             CAU_RADR_CA_REG(CAU,1)
+#define CAU_RADR_CA2                             CAU_RADR_CA_REG(CAU,2)
+#define CAU_RADR_CA3                             CAU_RADR_CA_REG(CAU,3)
+#define CAU_RADR_CA4                             CAU_RADR_CA_REG(CAU,4)
+#define CAU_RADR_CA5                             CAU_RADR_CA_REG(CAU,5)
+#define CAU_RADR_CA6                             CAU_RADR_CA_REG(CAU,6)
+#define CAU_RADR_CA7                             CAU_RADR_CA_REG(CAU,7)
+#define CAU_RADR_CA8                             CAU_RADR_CA_REG(CAU,8)
+#define CAU_XOR_CASR                             CAU_XOR_CASR_REG(CAU)
+#define CAU_XOR_CAA                              CAU_XOR_CAA_REG(CAU)
+#define CAU_XOR_CA0                              CAU_XOR_CA_REG(CAU,0)
+#define CAU_XOR_CA1                              CAU_XOR_CA_REG(CAU,1)
+#define CAU_XOR_CA2                              CAU_XOR_CA_REG(CAU,2)
+#define CAU_XOR_CA3                              CAU_XOR_CA_REG(CAU,3)
+#define CAU_XOR_CA4                              CAU_XOR_CA_REG(CAU,4)
+#define CAU_XOR_CA5                              CAU_XOR_CA_REG(CAU,5)
+#define CAU_XOR_CA6                              CAU_XOR_CA_REG(CAU,6)
+#define CAU_XOR_CA7                              CAU_XOR_CA_REG(CAU,7)
+#define CAU_XOR_CA8                              CAU_XOR_CA_REG(CAU,8)
+#define CAU_ROTL_CASR                            CAU_ROTL_CASR_REG(CAU)
+#define CAU_ROTL_CAA                             CAU_ROTL_CAA_REG(CAU)
+#define CAU_ROTL_CA0                             CAU_ROTL_CA_REG(CAU,0)
+#define CAU_ROTL_CA1                             CAU_ROTL_CA_REG(CAU,1)
+#define CAU_ROTL_CA2                             CAU_ROTL_CA_REG(CAU,2)
+#define CAU_ROTL_CA3                             CAU_ROTL_CA_REG(CAU,3)
+#define CAU_ROTL_CA4                             CAU_ROTL_CA_REG(CAU,4)
+#define CAU_ROTL_CA5                             CAU_ROTL_CA_REG(CAU,5)
+#define CAU_ROTL_CA6                             CAU_ROTL_CA_REG(CAU,6)
+#define CAU_ROTL_CA7                             CAU_ROTL_CA_REG(CAU,7)
+#define CAU_ROTL_CA8                             CAU_ROTL_CA_REG(CAU,8)
+#define CAU_AESC_CASR                            CAU_AESC_CASR_REG(CAU)
+#define CAU_AESC_CAA                             CAU_AESC_CAA_REG(CAU)
+#define CAU_AESC_CA0                             CAU_AESC_CA_REG(CAU,0)
+#define CAU_AESC_CA1                             CAU_AESC_CA_REG(CAU,1)
+#define CAU_AESC_CA2                             CAU_AESC_CA_REG(CAU,2)
+#define CAU_AESC_CA3                             CAU_AESC_CA_REG(CAU,3)
+#define CAU_AESC_CA4                             CAU_AESC_CA_REG(CAU,4)
+#define CAU_AESC_CA5                             CAU_AESC_CA_REG(CAU,5)
+#define CAU_AESC_CA6                             CAU_AESC_CA_REG(CAU,6)
+#define CAU_AESC_CA7                             CAU_AESC_CA_REG(CAU,7)
+#define CAU_AESC_CA8                             CAU_AESC_CA_REG(CAU,8)
+#define CAU_AESIC_CASR                           CAU_AESIC_CASR_REG(CAU)
+#define CAU_AESIC_CAA                            CAU_AESIC_CAA_REG(CAU)
+#define CAU_AESIC_CA0                            CAU_AESIC_CA_REG(CAU,0)
+#define CAU_AESIC_CA1                            CAU_AESIC_CA_REG(CAU,1)
+#define CAU_AESIC_CA2                            CAU_AESIC_CA_REG(CAU,2)
+#define CAU_AESIC_CA3                            CAU_AESIC_CA_REG(CAU,3)
+#define CAU_AESIC_CA4                            CAU_AESIC_CA_REG(CAU,4)
+#define CAU_AESIC_CA5                            CAU_AESIC_CA_REG(CAU,5)
+#define CAU_AESIC_CA6                            CAU_AESIC_CA_REG(CAU,6)
+#define CAU_AESIC_CA7                            CAU_AESIC_CA_REG(CAU,7)
+#define CAU_AESIC_CA8                            CAU_AESIC_CA_REG(CAU,8)
+
+/* CAU - Register array accessors */
+#define CAU_DIRECT(index)                        CAU_DIRECT_REG(CAU,index)
+#define CAU_LDR_CA(index)                        CAU_LDR_CA_REG(CAU,index)
+#define CAU_STR_CA(index)                        CAU_STR_CA_REG(CAU,index)
+#define CAU_ADR_CA(index)                        CAU_ADR_CA_REG(CAU,index)
+#define CAU_RADR_CA(index)                       CAU_RADR_CA_REG(CAU,index)
+#define CAU_XOR_CA(index)                        CAU_XOR_CA_REG(CAU,index)
+#define CAU_ROTL_CA(index)                       CAU_ROTL_CA_REG(CAU,index)
+#define CAU_AESC_CA(index)                       CAU_AESC_CA_REG(CAU,index)
+#define CAU_AESIC_CA(index)                      CAU_AESIC_CA_REG(CAU,index)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base)                        ((base)->CR0)
+#define CMP_CR1_REG(base)                        ((base)->CR1)
+#define CMP_FPR_REG(base)                        ((base)->FPR)
+#define CMP_SCR_REG(base)                        ((base)->SCR)
+#define CMP_DACCR_REG(base)                      ((base)->DACCR)
+#define CMP_MUXCR_REG(base)                      ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK                     0x3u
+#define CMP_CR0_HYSTCTR_SHIFT                    0
+#define CMP_CR0_HYSTCTR_WIDTH                    2
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT                 4
+#define CMP_CR0_FILTER_CNT_WIDTH                 3
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK                          0x1u
+#define CMP_CR1_EN_SHIFT                         0
+#define CMP_CR1_EN_WIDTH                         1
+#define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK                         0x2u
+#define CMP_CR1_OPE_SHIFT                        1
+#define CMP_CR1_OPE_WIDTH                        1
+#define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK                         0x4u
+#define CMP_CR1_COS_SHIFT                        2
+#define CMP_CR1_COS_WIDTH                        1
+#define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK                         0x8u
+#define CMP_CR1_INV_SHIFT                        3
+#define CMP_CR1_INV_WIDTH                        1
+#define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK                       0x10u
+#define CMP_CR1_PMODE_SHIFT                      4
+#define CMP_CR1_PMODE_WIDTH                      1
+#define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
+#define CMP_CR1_WE_MASK                          0x40u
+#define CMP_CR1_WE_SHIFT                         6
+#define CMP_CR1_WE_WIDTH                         1
+#define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK                          0x80u
+#define CMP_CR1_SE_SHIFT                         7
+#define CMP_CR1_SE_WIDTH                         1
+#define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK                    0xFFu
+#define CMP_FPR_FILT_PER_SHIFT                   0
+#define CMP_FPR_FILT_PER_WIDTH                   8
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK                        0x1u
+#define CMP_SCR_COUT_SHIFT                       0
+#define CMP_SCR_COUT_WIDTH                       1
+#define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK                         0x2u
+#define CMP_SCR_CFF_SHIFT                        1
+#define CMP_SCR_CFF_WIDTH                        1
+#define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK                         0x4u
+#define CMP_SCR_CFR_SHIFT                        2
+#define CMP_SCR_CFR_WIDTH                        1
+#define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK                         0x8u
+#define CMP_SCR_IEF_SHIFT                        3
+#define CMP_SCR_IEF_WIDTH                        1
+#define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK                         0x10u
+#define CMP_SCR_IER_SHIFT                        4
+#define CMP_SCR_IER_WIDTH                        1
+#define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK                       0x40u
+#define CMP_SCR_DMAEN_SHIFT                      6
+#define CMP_SCR_DMAEN_WIDTH                      1
+#define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK                     0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT                    0
+#define CMP_DACCR_VOSEL_WIDTH                    6
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     0x40u
+#define CMP_DACCR_VRSEL_SHIFT                    6
+#define CMP_DACCR_VRSEL_WIDTH                    1
+#define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK                     0x80u
+#define CMP_DACCR_DACEN_SHIFT                    7
+#define CMP_DACCR_DACEN_WIDTH                    1
+#define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK                      0x7u
+#define CMP_MUXCR_MSEL_SHIFT                     0
+#define CMP_MUXCR_MSEL_WIDTH                     3
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      0x38u
+#define CMP_MUXCR_PSEL_SHIFT                     3
+#define CMP_MUXCR_PSEL_WIDTH                     3
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK                      0x80u
+#define CMP_MUXCR_PSTM_SHIFT                     7
+#define CMP_MUXCR_PSTM_WIDTH                     1
+#define CMP_MUXCR_PSTM(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSTM_SHIFT))&CMP_MUXCR_PSTM_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR                            (CMP0)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE                                (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1                                     ((CMP_Type *)CMP1_BASE)
+#define CMP1_BASE_PTR                            (CMP1)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE                                (0x40073010u)
+/** Peripheral CMP2 base pointer */
+#define CMP2                                     ((CMP_Type *)CMP2_BASE)
+#define CMP2_BASE_PTR                            (CMP2)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS                           { CMP0_BASE, CMP1_BASE, CMP2_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS                            { CMP0, CMP1, CMP2 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0                                 CMP_CR0_REG(CMP0)
+#define CMP0_CR1                                 CMP_CR1_REG(CMP0)
+#define CMP0_FPR                                 CMP_FPR_REG(CMP0)
+#define CMP0_SCR                                 CMP_SCR_REG(CMP0)
+#define CMP0_DACCR                               CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR                               CMP_MUXCR_REG(CMP0)
+/* CMP1 */
+#define CMP1_CR0                                 CMP_CR0_REG(CMP1)
+#define CMP1_CR1                                 CMP_CR1_REG(CMP1)
+#define CMP1_FPR                                 CMP_FPR_REG(CMP1)
+#define CMP1_SCR                                 CMP_SCR_REG(CMP1)
+#define CMP1_DACCR                               CMP_DACCR_REG(CMP1)
+#define CMP1_MUXCR                               CMP_MUXCR_REG(CMP1)
+/* CMP2 */
+#define CMP2_CR0                                 CMP_CR0_REG(CMP2)
+#define CMP2_CR1                                 CMP_CR1_REG(CMP2)
+#define CMP2_FPR                                 CMP_FPR_REG(CMP2)
+#define CMP2_SCR                                 CMP_SCR_REG(CMP2)
+#define CMP2_DACCR                               CMP_DACCR_REG(CMP2)
+#define CMP2_MUXCR                               CMP_MUXCR_REG(CMP2)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CGH1;                               /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+  __IO uint8_t CGL1;                               /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+  __IO uint8_t CGH2;                               /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+  __IO uint8_t CGL2;                               /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+  __IO uint8_t OC;                                 /**< CMT Output Control Register, offset: 0x4 */
+  __IO uint8_t MSC;                                /**< CMT Modulator Status and Control Register, offset: 0x5 */
+  __IO uint8_t CMD1;                               /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+  __IO uint8_t CMD2;                               /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+  __IO uint8_t CMD3;                               /**< CMT Modulator Data Register Space High, offset: 0x8 */
+  __IO uint8_t CMD4;                               /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+  __IO uint8_t PPS;                                /**< CMT Primary Prescaler Register, offset: 0xA */
+  __IO uint8_t DMA;                                /**< CMT Direct Memory Access Register, offset: 0xB */
+} CMT_Type, *CMT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register accessors */
+#define CMT_CGH1_REG(base)                       ((base)->CGH1)
+#define CMT_CGL1_REG(base)                       ((base)->CGL1)
+#define CMT_CGH2_REG(base)                       ((base)->CGH2)
+#define CMT_CGL2_REG(base)                       ((base)->CGL2)
+#define CMT_OC_REG(base)                         ((base)->OC)
+#define CMT_MSC_REG(base)                        ((base)->MSC)
+#define CMT_CMD1_REG(base)                       ((base)->CMD1)
+#define CMT_CMD2_REG(base)                       ((base)->CMD2)
+#define CMT_CMD3_REG(base)                       ((base)->CMD3)
+#define CMT_CMD4_REG(base)                       ((base)->CMD4)
+#define CMT_PPS_REG(base)                        ((base)->PPS)
+#define CMT_DMA_REG(base)                        ((base)->DMA)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK                         0xFFu
+#define CMT_CGH1_PH_SHIFT                        0
+#define CMT_CGH1_PH_WIDTH                        8
+#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK                         0xFFu
+#define CMT_CGL1_PL_SHIFT                        0
+#define CMT_CGL1_PL_WIDTH                        8
+#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK                         0xFFu
+#define CMT_CGH2_SH_SHIFT                        0
+#define CMT_CGH2_SH_WIDTH                        8
+#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK                         0xFFu
+#define CMT_CGL2_SL_SHIFT                        0
+#define CMT_CGL2_SL_WIDTH                        8
+#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK                       0x20u
+#define CMT_OC_IROPEN_SHIFT                      5
+#define CMT_OC_IROPEN_WIDTH                      1
+#define CMT_OC_IROPEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROPEN_SHIFT))&CMT_OC_IROPEN_MASK)
+#define CMT_OC_CMTPOL_MASK                       0x40u
+#define CMT_OC_CMTPOL_SHIFT                      6
+#define CMT_OC_CMTPOL_WIDTH                      1
+#define CMT_OC_CMTPOL(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_OC_CMTPOL_SHIFT))&CMT_OC_CMTPOL_MASK)
+#define CMT_OC_IROL_MASK                         0x80u
+#define CMT_OC_IROL_SHIFT                        7
+#define CMT_OC_IROL_WIDTH                        1
+#define CMT_OC_IROL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROL_SHIFT))&CMT_OC_IROL_MASK)
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK                       0x1u
+#define CMT_MSC_MCGEN_SHIFT                      0
+#define CMT_MSC_MCGEN_WIDTH                      1
+#define CMT_MSC_MCGEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_MCGEN_SHIFT))&CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_EOCIE_MASK                       0x2u
+#define CMT_MSC_EOCIE_SHIFT                      1
+#define CMT_MSC_EOCIE_WIDTH                      1
+#define CMT_MSC_EOCIE(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCIE_SHIFT))&CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_FSK_MASK                         0x4u
+#define CMT_MSC_FSK_SHIFT                        2
+#define CMT_MSC_FSK_WIDTH                        1
+#define CMT_MSC_FSK(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_MSC_FSK_SHIFT))&CMT_MSC_FSK_MASK)
+#define CMT_MSC_BASE_MASK                        0x8u
+#define CMT_MSC_BASE_SHIFT                       3
+#define CMT_MSC_BASE_WIDTH                       1
+#define CMT_MSC_BASE(x)                          (((uint8_t)(((uint8_t)(x))<<CMT_MSC_BASE_SHIFT))&CMT_MSC_BASE_MASK)
+#define CMT_MSC_EXSPC_MASK                       0x10u
+#define CMT_MSC_EXSPC_SHIFT                      4
+#define CMT_MSC_EXSPC_WIDTH                      1
+#define CMT_MSC_EXSPC(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EXSPC_SHIFT))&CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_CMTDIV_MASK                      0x60u
+#define CMT_MSC_CMTDIV_SHIFT                     5
+#define CMT_MSC_CMTDIV_WIDTH                     2
+#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK                        0x80u
+#define CMT_MSC_EOCF_SHIFT                       7
+#define CMT_MSC_EOCF_WIDTH                       1
+#define CMT_MSC_EOCF(x)                          (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCF_SHIFT))&CMT_MSC_EOCF_MASK)
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK                         0xFFu
+#define CMT_CMD1_MB_SHIFT                        0
+#define CMT_CMD1_MB_WIDTH                        8
+#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK                         0xFFu
+#define CMT_CMD2_MB_SHIFT                        0
+#define CMT_CMD2_MB_WIDTH                        8
+#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK                         0xFFu
+#define CMT_CMD3_SB_SHIFT                        0
+#define CMT_CMD3_SB_WIDTH                        8
+#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK                         0xFFu
+#define CMT_CMD4_SB_SHIFT                        0
+#define CMT_CMD4_SB_WIDTH                        8
+#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK                      0xFu
+#define CMT_PPS_PPSDIV_SHIFT                     0
+#define CMT_PPS_PPSDIV_WIDTH                     4
+#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK                         0x1u
+#define CMT_DMA_DMA_SHIFT                        0
+#define CMT_DMA_DMA_WIDTH                        1
+#define CMT_DMA_DMA(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_DMA_DMA_SHIFT))&CMT_DMA_DMA_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE                                 (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT                                      ((CMT_Type *)CMT_BASE)
+#define CMT_BASE_PTR                             (CMT)
+/** Array initializer of CMT peripheral base addresses */
+#define CMT_BASE_ADDRS                           { CMT_BASE }
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASE_PTRS                            { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS                                 { CMT_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register instance definitions */
+/* CMT */
+#define CMT_CGH1                                 CMT_CGH1_REG(CMT)
+#define CMT_CGL1                                 CMT_CGL1_REG(CMT)
+#define CMT_CGH2                                 CMT_CGH2_REG(CMT)
+#define CMT_CGL2                                 CMT_CGL2_REG(CMT)
+#define CMT_OC                                   CMT_OC_REG(CMT)
+#define CMT_MSC                                  CMT_MSC_REG(CMT)
+#define CMT_CMD1                                 CMT_CMD1_REG(CMT)
+#define CMT_CMD2                                 CMT_CMD2_REG(CMT)
+#define CMT_CMD3                                 CMT_CMD3_REG(CMT)
+#define CMT_CMD4                                 CMT_CMD4_REG(CMT)
+#define CMT_PPS                                  CMT_PPS_REG(CMT)
+#define CMT_DMA                                  CMT_DMA_REG(CMT)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type, *CRC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register accessors */
+#define CRC_DATAL_REG(base)                      ((base)->ACCESS16BIT.DATAL)
+#define CRC_DATAH_REG(base)                      ((base)->ACCESS16BIT.DATAH)
+#define CRC_DATA_REG(base)                       ((base)->DATA)
+#define CRC_DATALL_REG(base)                     ((base)->ACCESS8BIT.DATALL)
+#define CRC_DATALU_REG(base)                     ((base)->ACCESS8BIT.DATALU)
+#define CRC_DATAHL_REG(base)                     ((base)->ACCESS8BIT.DATAHL)
+#define CRC_DATAHU_REG(base)                     ((base)->ACCESS8BIT.DATAHU)
+#define CRC_GPOLYL_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYL)
+#define CRC_GPOLYH_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYH)
+#define CRC_GPOLY_REG(base)                      ((base)->GPOLY)
+#define CRC_GPOLYLL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
+#define CRC_GPOLYLU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
+#define CRC_GPOLYHL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
+#define CRC_GPOLYHU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
+#define CRC_CTRL_REG(base)                       ((base)->CTRL)
+#define CRC_CTRLHU_REG(base)                     ((base)->CTRL_ACCESS8BIT.CTRLHU)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK                     0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT                    0
+#define CRC_DATAL_DATAL_WIDTH                    16
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK                     0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT                    0
+#define CRC_DATAH_DATAH_WIDTH                    16
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK                         0xFFu
+#define CRC_DATA_LL_SHIFT                        0
+#define CRC_DATA_LL_WIDTH                        8
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         0xFF00u
+#define CRC_DATA_LU_SHIFT                        8
+#define CRC_DATA_LU_WIDTH                        8
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         0xFF0000u
+#define CRC_DATA_HL_SHIFT                        16
+#define CRC_DATA_HL_WIDTH                        8
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         0xFF000000u
+#define CRC_DATA_HU_SHIFT                        24
+#define CRC_DATA_HU_WIDTH                        8
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK                   0xFFu
+#define CRC_DATALL_DATALL_SHIFT                  0
+#define CRC_DATALL_DATALL_WIDTH                  8
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK                   0xFFu
+#define CRC_DATALU_DATALU_SHIFT                  0
+#define CRC_DATALU_DATALU_WIDTH                  8
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK                   0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT                  0
+#define CRC_DATAHL_DATAHL_WIDTH                  8
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK                   0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT                  0
+#define CRC_DATAHU_DATAHU_WIDTH                  8
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT                  0
+#define CRC_GPOLYL_GPOLYL_WIDTH                  16
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT                  0
+#define CRC_GPOLYH_GPOLYH_WIDTH                  16
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK                       0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT                      0
+#define CRC_GPOLY_LOW_WIDTH                      16
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT                     16
+#define CRC_GPOLY_HIGH_WIDTH                     16
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                0
+#define CRC_GPOLYLL_GPOLYLL_WIDTH                8
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                0
+#define CRC_GPOLYLU_GPOLYLU_WIDTH                8
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                0
+#define CRC_GPOLYHL_GPOLYHL_WIDTH                8
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                0
+#define CRC_GPOLYHU_GPOLYHU_WIDTH                8
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK                       0x1000000u
+#define CRC_CTRL_TCRC_SHIFT                      24
+#define CRC_CTRL_TCRC_WIDTH                      1
+#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK                        0x2000000u
+#define CRC_CTRL_WAS_SHIFT                       25
+#define CRC_CTRL_WAS_WIDTH                       1
+#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK                       0x4000000u
+#define CRC_CTRL_FXOR_SHIFT                      26
+#define CRC_CTRL_FXOR_WIDTH                      1
+#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK                       0x30000000u
+#define CRC_CTRL_TOTR_SHIFT                      28
+#define CRC_CTRL_TOTR_WIDTH                      2
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        0xC0000000u
+#define CRC_CTRL_TOT_SHIFT                       30
+#define CRC_CTRL_TOT_WIDTH                       2
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK                     0x1u
+#define CRC_CTRLHU_TCRC_SHIFT                    0
+#define CRC_CTRLHU_TCRC_WIDTH                    1
+#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TCRC_SHIFT))&CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK                      0x2u
+#define CRC_CTRLHU_WAS_SHIFT                     1
+#define CRC_CTRLHU_WAS_WIDTH                     1
+#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_WAS_SHIFT))&CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK                     0x4u
+#define CRC_CTRLHU_FXOR_SHIFT                    2
+#define CRC_CTRLHU_FXOR_WIDTH                    1
+#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_FXOR_SHIFT))&CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK                     0x30u
+#define CRC_CTRLHU_TOTR_SHIFT                    4
+#define CRC_CTRLHU_TOTR_WIDTH                    2
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      0xC0u
+#define CRC_CTRLHU_TOT_SHIFT                     6
+#define CRC_CTRLHU_TOT_WIDTH                     2
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+#define CRC_BASE_PTR                             (CRC0)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register instance definitions */
+/* CRC */
+#define CRC_DATA                                 CRC_DATA_REG(CRC0)
+#define CRC_DATAL                                CRC_DATAL_REG(CRC0)
+#define CRC_DATALL                               CRC_DATALL_REG(CRC0)
+#define CRC_DATALU                               CRC_DATALU_REG(CRC0)
+#define CRC_DATAH                                CRC_DATAH_REG(CRC0)
+#define CRC_DATAHL                               CRC_DATAHL_REG(CRC0)
+#define CRC_DATAHU                               CRC_DATAHU_REG(CRC0)
+#define CRC_GPOLY                                CRC_GPOLY_REG(CRC0)
+#define CRC_GPOLYL                               CRC_GPOLYL_REG(CRC0)
+#define CRC_GPOLYLL                              CRC_GPOLYLL_REG(CRC0)
+#define CRC_GPOLYLU                              CRC_GPOLYLU_REG(CRC0)
+#define CRC_GPOLYH                               CRC_GPOLYH_REG(CRC0)
+#define CRC_GPOLYHL                              CRC_GPOLYHL_REG(CRC0)
+#define CRC_GPOLYHU                              CRC_GPOLYHU_REG(CRC0)
+#define CRC_CTRL                                 CRC_CTRL_REG(CRC0)
+#define CRC_CTRLHU                               CRC_CTRLHU_REG(CRC0)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[16];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index)                 ((base)->DAT[index].DATL)
+#define DAC_DATL_COUNT                           16
+#define DAC_DATH_REG(base,index)                 ((base)->DAT[index].DATH)
+#define DAC_DATH_COUNT                           16
+#define DAC_SR_REG(base)                         ((base)->SR)
+#define DAC_C0_REG(base)                         ((base)->C0)
+#define DAC_C1_REG(base)                         ((base)->C1)
+#define DAC_C2_REG(base)                         ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK                      0xFFu
+#define DAC_DATL_DATA0_SHIFT                     0
+#define DAC_DATL_DATA0_WIDTH                     8
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK                      0xFu
+#define DAC_DATH_DATA1_SHIFT                     0
+#define DAC_DATH_DATA1_WIDTH                     4
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK                    0x1u
+#define DAC_SR_DACBFRPBF_SHIFT                   0
+#define DAC_SR_DACBFRPBF_WIDTH                   1
+#define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK                    0x2u
+#define DAC_SR_DACBFRPTF_SHIFT                   1
+#define DAC_SR_DACBFRPTF_WIDTH                   1
+#define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK                     0x4u
+#define DAC_SR_DACBFWMF_SHIFT                    2
+#define DAC_SR_DACBFWMF_WIDTH                    1
+#define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFWMF_SHIFT))&DAC_SR_DACBFWMF_MASK)
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK                     0x1u
+#define DAC_C0_DACBBIEN_SHIFT                    0
+#define DAC_C0_DACBBIEN_WIDTH                    1
+#define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK                     0x2u
+#define DAC_C0_DACBTIEN_SHIFT                    1
+#define DAC_C0_DACBTIEN_WIDTH                    1
+#define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK                     0x4u
+#define DAC_C0_DACBWIEN_SHIFT                    2
+#define DAC_C0_DACBWIEN_WIDTH                    1
+#define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBWIEN_SHIFT))&DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK                         0x8u
+#define DAC_C0_LPEN_SHIFT                        3
+#define DAC_C0_LPEN_WIDTH                        1
+#define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK                     0x10u
+#define DAC_C0_DACSWTRG_SHIFT                    4
+#define DAC_C0_DACSWTRG_WIDTH                    1
+#define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK                    0x20u
+#define DAC_C0_DACTRGSEL_SHIFT                   5
+#define DAC_C0_DACTRGSEL_WIDTH                   1
+#define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK                       0x40u
+#define DAC_C0_DACRFS_SHIFT                      6
+#define DAC_C0_DACRFS_WIDTH                      1
+#define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK                        0x80u
+#define DAC_C0_DACEN_SHIFT                       7
+#define DAC_C0_DACEN_WIDTH                       1
+#define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK                      0x1u
+#define DAC_C1_DACBFEN_SHIFT                     0
+#define DAC_C1_DACBFEN_WIDTH                     1
+#define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK                      0x6u
+#define DAC_C1_DACBFMD_SHIFT                     1
+#define DAC_C1_DACBFMD_WIDTH                     2
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK                      0x18u
+#define DAC_C1_DACBFWM_SHIFT                     3
+#define DAC_C1_DACBFWM_WIDTH                     2
+#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK                        0x80u
+#define DAC_C1_DMAEN_SHIFT                       7
+#define DAC_C1_DMAEN_WIDTH                       1
+#define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK                      0xFu
+#define DAC_C2_DACBFUP_SHIFT                     0
+#define DAC_C2_DACBFUP_WIDTH                     4
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      0xF0u
+#define DAC_C2_DACBFRP_SHIFT                     4
+#define DAC_C2_DACBFRP_WIDTH                     4
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR                            (DAC0)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE                                (0x400CD000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1                                     ((DAC_Type *)DAC1_BASE)
+#define DAC1_BASE_PTR                            (DAC1)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS                           { DAC0_BASE, DAC1_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS                            { DAC0, DAC1 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn, DAC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L                               DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H                               DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L                               DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H                               DAC_DATH_REG(DAC0,1)
+#define DAC0_DAT2L                               DAC_DATL_REG(DAC0,2)
+#define DAC0_DAT2H                               DAC_DATH_REG(DAC0,2)
+#define DAC0_DAT3L                               DAC_DATL_REG(DAC0,3)
+#define DAC0_DAT3H                               DAC_DATH_REG(DAC0,3)
+#define DAC0_DAT4L                               DAC_DATL_REG(DAC0,4)
+#define DAC0_DAT4H                               DAC_DATH_REG(DAC0,4)
+#define DAC0_DAT5L                               DAC_DATL_REG(DAC0,5)
+#define DAC0_DAT5H                               DAC_DATH_REG(DAC0,5)
+#define DAC0_DAT6L                               DAC_DATL_REG(DAC0,6)
+#define DAC0_DAT6H                               DAC_DATH_REG(DAC0,6)
+#define DAC0_DAT7L                               DAC_DATL_REG(DAC0,7)
+#define DAC0_DAT7H                               DAC_DATH_REG(DAC0,7)
+#define DAC0_DAT8L                               DAC_DATL_REG(DAC0,8)
+#define DAC0_DAT8H                               DAC_DATH_REG(DAC0,8)
+#define DAC0_DAT9L                               DAC_DATL_REG(DAC0,9)
+#define DAC0_DAT9H                               DAC_DATH_REG(DAC0,9)
+#define DAC0_DAT10L                              DAC_DATL_REG(DAC0,10)
+#define DAC0_DAT10H                              DAC_DATH_REG(DAC0,10)
+#define DAC0_DAT11L                              DAC_DATL_REG(DAC0,11)
+#define DAC0_DAT11H                              DAC_DATH_REG(DAC0,11)
+#define DAC0_DAT12L                              DAC_DATL_REG(DAC0,12)
+#define DAC0_DAT12H                              DAC_DATH_REG(DAC0,12)
+#define DAC0_DAT13L                              DAC_DATL_REG(DAC0,13)
+#define DAC0_DAT13H                              DAC_DATH_REG(DAC0,13)
+#define DAC0_DAT14L                              DAC_DATL_REG(DAC0,14)
+#define DAC0_DAT14H                              DAC_DATH_REG(DAC0,14)
+#define DAC0_DAT15L                              DAC_DATL_REG(DAC0,15)
+#define DAC0_DAT15H                              DAC_DATH_REG(DAC0,15)
+#define DAC0_SR                                  DAC_SR_REG(DAC0)
+#define DAC0_C0                                  DAC_C0_REG(DAC0)
+#define DAC0_C1                                  DAC_C1_REG(DAC0)
+#define DAC0_C2                                  DAC_C2_REG(DAC0)
+/* DAC1 */
+#define DAC1_DAT0L                               DAC_DATL_REG(DAC1,0)
+#define DAC1_DAT0H                               DAC_DATH_REG(DAC1,0)
+#define DAC1_DAT1L                               DAC_DATL_REG(DAC1,1)
+#define DAC1_DAT1H                               DAC_DATH_REG(DAC1,1)
+#define DAC1_DAT2L                               DAC_DATL_REG(DAC1,2)
+#define DAC1_DAT2H                               DAC_DATH_REG(DAC1,2)
+#define DAC1_DAT3L                               DAC_DATL_REG(DAC1,3)
+#define DAC1_DAT3H                               DAC_DATH_REG(DAC1,3)
+#define DAC1_DAT4L                               DAC_DATL_REG(DAC1,4)
+#define DAC1_DAT4H                               DAC_DATH_REG(DAC1,4)
+#define DAC1_DAT5L                               DAC_DATL_REG(DAC1,5)
+#define DAC1_DAT5H                               DAC_DATH_REG(DAC1,5)
+#define DAC1_DAT6L                               DAC_DATL_REG(DAC1,6)
+#define DAC1_DAT6H                               DAC_DATH_REG(DAC1,6)
+#define DAC1_DAT7L                               DAC_DATL_REG(DAC1,7)
+#define DAC1_DAT7H                               DAC_DATH_REG(DAC1,7)
+#define DAC1_DAT8L                               DAC_DATL_REG(DAC1,8)
+#define DAC1_DAT8H                               DAC_DATH_REG(DAC1,8)
+#define DAC1_DAT9L                               DAC_DATL_REG(DAC1,9)
+#define DAC1_DAT9H                               DAC_DATH_REG(DAC1,9)
+#define DAC1_DAT10L                              DAC_DATL_REG(DAC1,10)
+#define DAC1_DAT10H                              DAC_DATH_REG(DAC1,10)
+#define DAC1_DAT11L                              DAC_DATL_REG(DAC1,11)
+#define DAC1_DAT11H                              DAC_DATH_REG(DAC1,11)
+#define DAC1_DAT12L                              DAC_DATL_REG(DAC1,12)
+#define DAC1_DAT12H                              DAC_DATH_REG(DAC1,12)
+#define DAC1_DAT13L                              DAC_DATL_REG(DAC1,13)
+#define DAC1_DAT13H                              DAC_DATH_REG(DAC1,13)
+#define DAC1_DAT14L                              DAC_DATL_REG(DAC1,14)
+#define DAC1_DAT14H                              DAC_DATH_REG(DAC1,14)
+#define DAC1_DAT15L                              DAC_DATL_REG(DAC1,15)
+#define DAC1_DAT15H                              DAC_DATH_REG(DAC1,15)
+#define DAC1_SR                                  DAC_SR_REG(DAC1)
+#define DAC1_C0                                  DAC_C0_REG(DAC1)
+#define DAC1_C1                                  DAC_C1_REG(DAC1)
+#define DAC1_C2                                  DAC_C2_REG(DAC1)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index)                         DAC_DATL_REG(DAC0,index)
+#define DAC1_DATL(index)                         DAC_DATL_REG(DAC1,index)
+#define DAC0_DATH(index)                         DAC_DATH_REG(DAC0,index)
+#define DAC1_DATH(index)                         DAC_DATH_REG(DAC1,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[200];
+  __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /**< Channel n Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /**< Channel n Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /**< Channel n Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /**< Channel n Priority Register, offset: 0x107 */
+  __IO uint8_t DCHPRI11;                           /**< Channel n Priority Register, offset: 0x108 */
+  __IO uint8_t DCHPRI10;                           /**< Channel n Priority Register, offset: 0x109 */
+  __IO uint8_t DCHPRI9;                            /**< Channel n Priority Register, offset: 0x10A */
+  __IO uint8_t DCHPRI8;                            /**< Channel n Priority Register, offset: 0x10B */
+  __IO uint8_t DCHPRI15;                           /**< Channel n Priority Register, offset: 0x10C */
+  __IO uint8_t DCHPRI14;                           /**< Channel n Priority Register, offset: 0x10D */
+  __IO uint8_t DCHPRI13;                           /**< Channel n Priority Register, offset: 0x10E */
+  __IO uint8_t DCHPRI12;                           /**< Channel n Priority Register, offset: 0x10F */
+       uint8_t RESERVED_6[3824];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[16];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_CR_REG(base)                         ((base)->CR)
+#define DMA_ES_REG(base)                         ((base)->ES)
+#define DMA_ERQ_REG(base)                        ((base)->ERQ)
+#define DMA_EEI_REG(base)                        ((base)->EEI)
+#define DMA_CEEI_REG(base)                       ((base)->CEEI)
+#define DMA_SEEI_REG(base)                       ((base)->SEEI)
+#define DMA_CERQ_REG(base)                       ((base)->CERQ)
+#define DMA_SERQ_REG(base)                       ((base)->SERQ)
+#define DMA_CDNE_REG(base)                       ((base)->CDNE)
+#define DMA_SSRT_REG(base)                       ((base)->SSRT)
+#define DMA_CERR_REG(base)                       ((base)->CERR)
+#define DMA_CINT_REG(base)                       ((base)->CINT)
+#define DMA_INT_REG(base)                        ((base)->INT)
+#define DMA_ERR_REG(base)                        ((base)->ERR)
+#define DMA_HRS_REG(base)                        ((base)->HRS)
+#define DMA_DCHPRI3_REG(base)                    ((base)->DCHPRI3)
+#define DMA_DCHPRI2_REG(base)                    ((base)->DCHPRI2)
+#define DMA_DCHPRI1_REG(base)                    ((base)->DCHPRI1)
+#define DMA_DCHPRI0_REG(base)                    ((base)->DCHPRI0)
+#define DMA_DCHPRI7_REG(base)                    ((base)->DCHPRI7)
+#define DMA_DCHPRI6_REG(base)                    ((base)->DCHPRI6)
+#define DMA_DCHPRI5_REG(base)                    ((base)->DCHPRI5)
+#define DMA_DCHPRI4_REG(base)                    ((base)->DCHPRI4)
+#define DMA_DCHPRI11_REG(base)                   ((base)->DCHPRI11)
+#define DMA_DCHPRI10_REG(base)                   ((base)->DCHPRI10)
+#define DMA_DCHPRI9_REG(base)                    ((base)->DCHPRI9)
+#define DMA_DCHPRI8_REG(base)                    ((base)->DCHPRI8)
+#define DMA_DCHPRI15_REG(base)                   ((base)->DCHPRI15)
+#define DMA_DCHPRI14_REG(base)                   ((base)->DCHPRI14)
+#define DMA_DCHPRI13_REG(base)                   ((base)->DCHPRI13)
+#define DMA_DCHPRI12_REG(base)                   ((base)->DCHPRI12)
+#define DMA_SADDR_REG(base,index)                ((base)->TCD[index].SADDR)
+#define DMA_SADDR_COUNT                          16
+#define DMA_SOFF_REG(base,index)                 ((base)->TCD[index].SOFF)
+#define DMA_SOFF_COUNT                           16
+#define DMA_ATTR_REG(base,index)                 ((base)->TCD[index].ATTR)
+#define DMA_ATTR_COUNT                           16
+#define DMA_NBYTES_MLNO_REG(base,index)          ((base)->TCD[index].NBYTES_MLNO)
+#define DMA_NBYTES_MLNO_COUNT                    16
+#define DMA_NBYTES_MLOFFNO_REG(base,index)       ((base)->TCD[index].NBYTES_MLOFFNO)
+#define DMA_NBYTES_MLOFFNO_COUNT                 16
+#define DMA_NBYTES_MLOFFYES_REG(base,index)      ((base)->TCD[index].NBYTES_MLOFFYES)
+#define DMA_NBYTES_MLOFFYES_COUNT                16
+#define DMA_SLAST_REG(base,index)                ((base)->TCD[index].SLAST)
+#define DMA_SLAST_COUNT                          16
+#define DMA_DADDR_REG(base,index)                ((base)->TCD[index].DADDR)
+#define DMA_DADDR_COUNT                          16
+#define DMA_DOFF_REG(base,index)                 ((base)->TCD[index].DOFF)
+#define DMA_DOFF_COUNT                           16
+#define DMA_CITER_ELINKNO_REG(base,index)        ((base)->TCD[index].CITER_ELINKNO)
+#define DMA_CITER_ELINKNO_COUNT                  16
+#define DMA_CITER_ELINKYES_REG(base,index)       ((base)->TCD[index].CITER_ELINKYES)
+#define DMA_CITER_ELINKYES_COUNT                 16
+#define DMA_DLAST_SGA_REG(base,index)            ((base)->TCD[index].DLAST_SGA)
+#define DMA_DLAST_SGA_COUNT                      16
+#define DMA_CSR_REG(base,index)                  ((base)->TCD[index].CSR)
+#define DMA_CSR_COUNT                            16
+#define DMA_BITER_ELINKNO_REG(base,index)        ((base)->TCD[index].BITER_ELINKNO)
+#define DMA_BITER_ELINKNO_COUNT                  16
+#define DMA_BITER_ELINKYES_REG(base,index)       ((base)->TCD[index].BITER_ELINKYES)
+#define DMA_BITER_ELINKYES_COUNT                 16
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK                         0x2u
+#define DMA_CR_EDBG_SHIFT                        1
+#define DMA_CR_EDBG_WIDTH                        1
+#define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK                         0x4u
+#define DMA_CR_ERCA_SHIFT                        2
+#define DMA_CR_ERCA_WIDTH                        1
+#define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK                          0x10u
+#define DMA_CR_HOE_SHIFT                         4
+#define DMA_CR_HOE_WIDTH                         1
+#define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK                         0x20u
+#define DMA_CR_HALT_SHIFT                        5
+#define DMA_CR_HALT_WIDTH                        1
+#define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK                          0x40u
+#define DMA_CR_CLM_SHIFT                         6
+#define DMA_CR_CLM_WIDTH                         1
+#define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK                         0x80u
+#define DMA_CR_EMLM_SHIFT                        7
+#define DMA_CR_EMLM_WIDTH                        1
+#define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK                          0x10000u
+#define DMA_CR_ECX_SHIFT                         16
+#define DMA_CR_ECX_WIDTH                         1
+#define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK                           0x20000u
+#define DMA_CR_CX_SHIFT                          17
+#define DMA_CR_CX_WIDTH                          1
+#define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK                          0x1u
+#define DMA_ES_DBE_SHIFT                         0
+#define DMA_ES_DBE_WIDTH                         1
+#define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK                          0x2u
+#define DMA_ES_SBE_SHIFT                         1
+#define DMA_ES_SBE_WIDTH                         1
+#define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK                          0x4u
+#define DMA_ES_SGE_SHIFT                         2
+#define DMA_ES_SGE_WIDTH                         1
+#define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK                          0x8u
+#define DMA_ES_NCE_SHIFT                         3
+#define DMA_ES_NCE_WIDTH                         1
+#define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK                          0x10u
+#define DMA_ES_DOE_SHIFT                         4
+#define DMA_ES_DOE_WIDTH                         1
+#define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK                          0x20u
+#define DMA_ES_DAE_SHIFT                         5
+#define DMA_ES_DAE_WIDTH                         1
+#define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK                          0x40u
+#define DMA_ES_SOE_SHIFT                         6
+#define DMA_ES_SOE_WIDTH                         1
+#define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK                          0x80u
+#define DMA_ES_SAE_SHIFT                         7
+#define DMA_ES_SAE_WIDTH                         1
+#define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK                       0xF00u
+#define DMA_ES_ERRCHN_SHIFT                      8
+#define DMA_ES_ERRCHN_WIDTH                      4
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          0x4000u
+#define DMA_ES_CPE_SHIFT                         14
+#define DMA_ES_CPE_WIDTH                         1
+#define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK                          0x10000u
+#define DMA_ES_ECX_SHIFT                         16
+#define DMA_ES_ECX_WIDTH                         1
+#define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK                          0x80000000u
+#define DMA_ES_VLD_SHIFT                         31
+#define DMA_ES_VLD_WIDTH                         1
+#define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK                        0x1u
+#define DMA_ERQ_ERQ0_SHIFT                       0
+#define DMA_ERQ_ERQ0_WIDTH                       1
+#define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK                        0x2u
+#define DMA_ERQ_ERQ1_SHIFT                       1
+#define DMA_ERQ_ERQ1_WIDTH                       1
+#define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK                        0x4u
+#define DMA_ERQ_ERQ2_SHIFT                       2
+#define DMA_ERQ_ERQ2_WIDTH                       1
+#define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK                        0x8u
+#define DMA_ERQ_ERQ3_SHIFT                       3
+#define DMA_ERQ_ERQ3_WIDTH                       1
+#define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK                        0x10u
+#define DMA_ERQ_ERQ4_SHIFT                       4
+#define DMA_ERQ_ERQ4_WIDTH                       1
+#define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK                        0x20u
+#define DMA_ERQ_ERQ5_SHIFT                       5
+#define DMA_ERQ_ERQ5_WIDTH                       1
+#define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK                        0x40u
+#define DMA_ERQ_ERQ6_SHIFT                       6
+#define DMA_ERQ_ERQ6_WIDTH                       1
+#define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK                        0x80u
+#define DMA_ERQ_ERQ7_SHIFT                       7
+#define DMA_ERQ_ERQ7_WIDTH                       1
+#define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK                        0x100u
+#define DMA_ERQ_ERQ8_SHIFT                       8
+#define DMA_ERQ_ERQ8_WIDTH                       1
+#define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK                        0x200u
+#define DMA_ERQ_ERQ9_SHIFT                       9
+#define DMA_ERQ_ERQ9_WIDTH                       1
+#define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK                       0x400u
+#define DMA_ERQ_ERQ10_SHIFT                      10
+#define DMA_ERQ_ERQ10_WIDTH                      1
+#define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK                       0x800u
+#define DMA_ERQ_ERQ11_SHIFT                      11
+#define DMA_ERQ_ERQ11_WIDTH                      1
+#define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK                       0x1000u
+#define DMA_ERQ_ERQ12_SHIFT                      12
+#define DMA_ERQ_ERQ12_WIDTH                      1
+#define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK                       0x2000u
+#define DMA_ERQ_ERQ13_SHIFT                      13
+#define DMA_ERQ_ERQ13_WIDTH                      1
+#define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK                       0x4000u
+#define DMA_ERQ_ERQ14_SHIFT                      14
+#define DMA_ERQ_ERQ14_WIDTH                      1
+#define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK                       0x8000u
+#define DMA_ERQ_ERQ15_SHIFT                      15
+#define DMA_ERQ_ERQ15_WIDTH                      1
+#define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK                        0x1u
+#define DMA_EEI_EEI0_SHIFT                       0
+#define DMA_EEI_EEI0_WIDTH                       1
+#define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK                        0x2u
+#define DMA_EEI_EEI1_SHIFT                       1
+#define DMA_EEI_EEI1_WIDTH                       1
+#define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK                        0x4u
+#define DMA_EEI_EEI2_SHIFT                       2
+#define DMA_EEI_EEI2_WIDTH                       1
+#define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK                        0x8u
+#define DMA_EEI_EEI3_SHIFT                       3
+#define DMA_EEI_EEI3_WIDTH                       1
+#define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK                        0x10u
+#define DMA_EEI_EEI4_SHIFT                       4
+#define DMA_EEI_EEI4_WIDTH                       1
+#define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK                        0x20u
+#define DMA_EEI_EEI5_SHIFT                       5
+#define DMA_EEI_EEI5_WIDTH                       1
+#define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK                        0x40u
+#define DMA_EEI_EEI6_SHIFT                       6
+#define DMA_EEI_EEI6_WIDTH                       1
+#define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK                        0x80u
+#define DMA_EEI_EEI7_SHIFT                       7
+#define DMA_EEI_EEI7_WIDTH                       1
+#define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK                        0x100u
+#define DMA_EEI_EEI8_SHIFT                       8
+#define DMA_EEI_EEI8_WIDTH                       1
+#define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK                        0x200u
+#define DMA_EEI_EEI9_SHIFT                       9
+#define DMA_EEI_EEI9_WIDTH                       1
+#define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK                       0x400u
+#define DMA_EEI_EEI10_SHIFT                      10
+#define DMA_EEI_EEI10_WIDTH                      1
+#define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK                       0x800u
+#define DMA_EEI_EEI11_SHIFT                      11
+#define DMA_EEI_EEI11_WIDTH                      1
+#define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK                       0x1000u
+#define DMA_EEI_EEI12_SHIFT                      12
+#define DMA_EEI_EEI12_WIDTH                      1
+#define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK                       0x2000u
+#define DMA_EEI_EEI13_SHIFT                      13
+#define DMA_EEI_EEI13_WIDTH                      1
+#define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK                       0x4000u
+#define DMA_EEI_EEI14_SHIFT                      14
+#define DMA_EEI_EEI14_WIDTH                      1
+#define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK                       0x8000u
+#define DMA_EEI_EEI15_SHIFT                      15
+#define DMA_EEI_EEI15_WIDTH                      1
+#define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK                       0xFu
+#define DMA_CEEI_CEEI_SHIFT                      0
+#define DMA_CEEI_CEEI_WIDTH                      4
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       0x40u
+#define DMA_CEEI_CAEE_SHIFT                      6
+#define DMA_CEEI_CAEE_WIDTH                      1
+#define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK                        0x80u
+#define DMA_CEEI_NOP_SHIFT                       7
+#define DMA_CEEI_NOP_WIDTH                       1
+#define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK                       0xFu
+#define DMA_SEEI_SEEI_SHIFT                      0
+#define DMA_SEEI_SEEI_WIDTH                      4
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       0x40u
+#define DMA_SEEI_SAEE_SHIFT                      6
+#define DMA_SEEI_SAEE_WIDTH                      1
+#define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK                        0x80u
+#define DMA_SEEI_NOP_SHIFT                       7
+#define DMA_SEEI_NOP_WIDTH                       1
+#define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK                       0xFu
+#define DMA_CERQ_CERQ_SHIFT                      0
+#define DMA_CERQ_CERQ_WIDTH                      4
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       0x40u
+#define DMA_CERQ_CAER_SHIFT                      6
+#define DMA_CERQ_CAER_WIDTH                      1
+#define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK                        0x80u
+#define DMA_CERQ_NOP_SHIFT                       7
+#define DMA_CERQ_NOP_WIDTH                       1
+#define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK                       0xFu
+#define DMA_SERQ_SERQ_SHIFT                      0
+#define DMA_SERQ_SERQ_WIDTH                      4
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       0x40u
+#define DMA_SERQ_SAER_SHIFT                      6
+#define DMA_SERQ_SAER_WIDTH                      1
+#define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK                        0x80u
+#define DMA_SERQ_NOP_SHIFT                       7
+#define DMA_SERQ_NOP_WIDTH                       1
+#define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK                       0xFu
+#define DMA_CDNE_CDNE_SHIFT                      0
+#define DMA_CDNE_CDNE_WIDTH                      4
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       0x40u
+#define DMA_CDNE_CADN_SHIFT                      6
+#define DMA_CDNE_CADN_WIDTH                      1
+#define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK                        0x80u
+#define DMA_CDNE_NOP_SHIFT                       7
+#define DMA_CDNE_NOP_WIDTH                       1
+#define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK                       0xFu
+#define DMA_SSRT_SSRT_SHIFT                      0
+#define DMA_SSRT_SSRT_WIDTH                      4
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       0x40u
+#define DMA_SSRT_SAST_SHIFT                      6
+#define DMA_SSRT_SAST_WIDTH                      1
+#define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK                        0x80u
+#define DMA_SSRT_NOP_SHIFT                       7
+#define DMA_SSRT_NOP_WIDTH                       1
+#define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK                       0xFu
+#define DMA_CERR_CERR_SHIFT                      0
+#define DMA_CERR_CERR_WIDTH                      4
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       0x40u
+#define DMA_CERR_CAEI_SHIFT                      6
+#define DMA_CERR_CAEI_WIDTH                      1
+#define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK                        0x80u
+#define DMA_CERR_NOP_SHIFT                       7
+#define DMA_CERR_NOP_WIDTH                       1
+#define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK                       0xFu
+#define DMA_CINT_CINT_SHIFT                      0
+#define DMA_CINT_CINT_WIDTH                      4
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       0x40u
+#define DMA_CINT_CAIR_SHIFT                      6
+#define DMA_CINT_CAIR_WIDTH                      1
+#define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK                        0x80u
+#define DMA_CINT_NOP_SHIFT                       7
+#define DMA_CINT_NOP_WIDTH                       1
+#define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK                        0x1u
+#define DMA_INT_INT0_SHIFT                       0
+#define DMA_INT_INT0_WIDTH                       1
+#define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK                        0x2u
+#define DMA_INT_INT1_SHIFT                       1
+#define DMA_INT_INT1_WIDTH                       1
+#define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK                        0x4u
+#define DMA_INT_INT2_SHIFT                       2
+#define DMA_INT_INT2_WIDTH                       1
+#define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK                        0x8u
+#define DMA_INT_INT3_SHIFT                       3
+#define DMA_INT_INT3_WIDTH                       1
+#define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK                        0x10u
+#define DMA_INT_INT4_SHIFT                       4
+#define DMA_INT_INT4_WIDTH                       1
+#define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK                        0x20u
+#define DMA_INT_INT5_SHIFT                       5
+#define DMA_INT_INT5_WIDTH                       1
+#define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK                        0x40u
+#define DMA_INT_INT6_SHIFT                       6
+#define DMA_INT_INT6_WIDTH                       1
+#define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK                        0x80u
+#define DMA_INT_INT7_SHIFT                       7
+#define DMA_INT_INT7_WIDTH                       1
+#define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK                        0x100u
+#define DMA_INT_INT8_SHIFT                       8
+#define DMA_INT_INT8_WIDTH                       1
+#define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK                        0x200u
+#define DMA_INT_INT9_SHIFT                       9
+#define DMA_INT_INT9_WIDTH                       1
+#define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK                       0x400u
+#define DMA_INT_INT10_SHIFT                      10
+#define DMA_INT_INT10_WIDTH                      1
+#define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK                       0x800u
+#define DMA_INT_INT11_SHIFT                      11
+#define DMA_INT_INT11_WIDTH                      1
+#define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK                       0x1000u
+#define DMA_INT_INT12_SHIFT                      12
+#define DMA_INT_INT12_WIDTH                      1
+#define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK                       0x2000u
+#define DMA_INT_INT13_SHIFT                      13
+#define DMA_INT_INT13_WIDTH                      1
+#define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK                       0x4000u
+#define DMA_INT_INT14_SHIFT                      14
+#define DMA_INT_INT14_WIDTH                      1
+#define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK                       0x8000u
+#define DMA_INT_INT15_SHIFT                      15
+#define DMA_INT_INT15_WIDTH                      1
+#define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK                        0x1u
+#define DMA_ERR_ERR0_SHIFT                       0
+#define DMA_ERR_ERR0_WIDTH                       1
+#define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK                        0x2u
+#define DMA_ERR_ERR1_SHIFT                       1
+#define DMA_ERR_ERR1_WIDTH                       1
+#define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK                        0x4u
+#define DMA_ERR_ERR2_SHIFT                       2
+#define DMA_ERR_ERR2_WIDTH                       1
+#define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK                        0x8u
+#define DMA_ERR_ERR3_SHIFT                       3
+#define DMA_ERR_ERR3_WIDTH                       1
+#define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK                        0x10u
+#define DMA_ERR_ERR4_SHIFT                       4
+#define DMA_ERR_ERR4_WIDTH                       1
+#define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK                        0x20u
+#define DMA_ERR_ERR5_SHIFT                       5
+#define DMA_ERR_ERR5_WIDTH                       1
+#define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK                        0x40u
+#define DMA_ERR_ERR6_SHIFT                       6
+#define DMA_ERR_ERR6_WIDTH                       1
+#define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK                        0x80u
+#define DMA_ERR_ERR7_SHIFT                       7
+#define DMA_ERR_ERR7_WIDTH                       1
+#define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK                        0x100u
+#define DMA_ERR_ERR8_SHIFT                       8
+#define DMA_ERR_ERR8_WIDTH                       1
+#define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK                        0x200u
+#define DMA_ERR_ERR9_SHIFT                       9
+#define DMA_ERR_ERR9_WIDTH                       1
+#define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK                       0x400u
+#define DMA_ERR_ERR10_SHIFT                      10
+#define DMA_ERR_ERR10_WIDTH                      1
+#define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK                       0x800u
+#define DMA_ERR_ERR11_SHIFT                      11
+#define DMA_ERR_ERR11_WIDTH                      1
+#define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK                       0x1000u
+#define DMA_ERR_ERR12_SHIFT                      12
+#define DMA_ERR_ERR12_WIDTH                      1
+#define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK                       0x2000u
+#define DMA_ERR_ERR13_SHIFT                      13
+#define DMA_ERR_ERR13_WIDTH                      1
+#define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK                       0x4000u
+#define DMA_ERR_ERR14_SHIFT                      14
+#define DMA_ERR_ERR14_WIDTH                      1
+#define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK                       0x8000u
+#define DMA_ERR_ERR15_SHIFT                      15
+#define DMA_ERR_ERR15_WIDTH                      1
+#define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK                        0x1u
+#define DMA_HRS_HRS0_SHIFT                       0
+#define DMA_HRS_HRS0_WIDTH                       1
+#define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK                        0x2u
+#define DMA_HRS_HRS1_SHIFT                       1
+#define DMA_HRS_HRS1_WIDTH                       1
+#define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK                        0x4u
+#define DMA_HRS_HRS2_SHIFT                       2
+#define DMA_HRS_HRS2_WIDTH                       1
+#define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK                        0x8u
+#define DMA_HRS_HRS3_SHIFT                       3
+#define DMA_HRS_HRS3_WIDTH                       1
+#define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK                        0x10u
+#define DMA_HRS_HRS4_SHIFT                       4
+#define DMA_HRS_HRS4_WIDTH                       1
+#define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK                        0x20u
+#define DMA_HRS_HRS5_SHIFT                       5
+#define DMA_HRS_HRS5_WIDTH                       1
+#define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK                        0x40u
+#define DMA_HRS_HRS6_SHIFT                       6
+#define DMA_HRS_HRS6_WIDTH                       1
+#define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK                        0x80u
+#define DMA_HRS_HRS7_SHIFT                       7
+#define DMA_HRS_HRS7_WIDTH                       1
+#define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK                        0x100u
+#define DMA_HRS_HRS8_SHIFT                       8
+#define DMA_HRS_HRS8_WIDTH                       1
+#define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK                        0x200u
+#define DMA_HRS_HRS9_SHIFT                       9
+#define DMA_HRS_HRS9_WIDTH                       1
+#define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK                       0x400u
+#define DMA_HRS_HRS10_SHIFT                      10
+#define DMA_HRS_HRS10_WIDTH                      1
+#define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK                       0x800u
+#define DMA_HRS_HRS11_SHIFT                      11
+#define DMA_HRS_HRS11_WIDTH                      1
+#define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK                       0x1000u
+#define DMA_HRS_HRS12_SHIFT                      12
+#define DMA_HRS_HRS12_WIDTH                      1
+#define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK                       0x2000u
+#define DMA_HRS_HRS13_SHIFT                      13
+#define DMA_HRS_HRS13_WIDTH                      1
+#define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK                       0x4000u
+#define DMA_HRS_HRS14_SHIFT                      14
+#define DMA_HRS_HRS14_WIDTH                      1
+#define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK                       0x8000u
+#define DMA_HRS_HRS15_SHIFT                      15
+#define DMA_HRS_HRS15_WIDTH                      1
+#define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT                  0
+#define DMA_DCHPRI3_CHPRI_WIDTH                  4
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     0x40u
+#define DMA_DCHPRI3_DPA_SHIFT                    6
+#define DMA_DCHPRI3_DPA_WIDTH                    1
+#define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_DPA_SHIFT))&DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK                     0x80u
+#define DMA_DCHPRI3_ECP_SHIFT                    7
+#define DMA_DCHPRI3_ECP_WIDTH                    1
+#define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_ECP_SHIFT))&DMA_DCHPRI3_ECP_MASK)
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT                  0
+#define DMA_DCHPRI2_CHPRI_WIDTH                  4
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     0x40u
+#define DMA_DCHPRI2_DPA_SHIFT                    6
+#define DMA_DCHPRI2_DPA_WIDTH                    1
+#define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_DPA_SHIFT))&DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK                     0x80u
+#define DMA_DCHPRI2_ECP_SHIFT                    7
+#define DMA_DCHPRI2_ECP_WIDTH                    1
+#define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_ECP_SHIFT))&DMA_DCHPRI2_ECP_MASK)
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT                  0
+#define DMA_DCHPRI1_CHPRI_WIDTH                  4
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     0x40u
+#define DMA_DCHPRI1_DPA_SHIFT                    6
+#define DMA_DCHPRI1_DPA_WIDTH                    1
+#define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_DPA_SHIFT))&DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK                     0x80u
+#define DMA_DCHPRI1_ECP_SHIFT                    7
+#define DMA_DCHPRI1_ECP_WIDTH                    1
+#define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_ECP_SHIFT))&DMA_DCHPRI1_ECP_MASK)
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT                  0
+#define DMA_DCHPRI0_CHPRI_WIDTH                  4
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     0x40u
+#define DMA_DCHPRI0_DPA_SHIFT                    6
+#define DMA_DCHPRI0_DPA_WIDTH                    1
+#define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_DPA_SHIFT))&DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK                     0x80u
+#define DMA_DCHPRI0_ECP_SHIFT                    7
+#define DMA_DCHPRI0_ECP_WIDTH                    1
+#define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_ECP_SHIFT))&DMA_DCHPRI0_ECP_MASK)
+/* DCHPRI7 Bit Fields */
+#define DMA_DCHPRI7_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI7_CHPRI_SHIFT                  0
+#define DMA_DCHPRI7_CHPRI_WIDTH                  4
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     0x40u
+#define DMA_DCHPRI7_DPA_SHIFT                    6
+#define DMA_DCHPRI7_DPA_WIDTH                    1
+#define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_DPA_SHIFT))&DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK                     0x80u
+#define DMA_DCHPRI7_ECP_SHIFT                    7
+#define DMA_DCHPRI7_ECP_WIDTH                    1
+#define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_ECP_SHIFT))&DMA_DCHPRI7_ECP_MASK)
+/* DCHPRI6 Bit Fields */
+#define DMA_DCHPRI6_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI6_CHPRI_SHIFT                  0
+#define DMA_DCHPRI6_CHPRI_WIDTH                  4
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     0x40u
+#define DMA_DCHPRI6_DPA_SHIFT                    6
+#define DMA_DCHPRI6_DPA_WIDTH                    1
+#define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_DPA_SHIFT))&DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK                     0x80u
+#define DMA_DCHPRI6_ECP_SHIFT                    7
+#define DMA_DCHPRI6_ECP_WIDTH                    1
+#define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_ECP_SHIFT))&DMA_DCHPRI6_ECP_MASK)
+/* DCHPRI5 Bit Fields */
+#define DMA_DCHPRI5_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI5_CHPRI_SHIFT                  0
+#define DMA_DCHPRI5_CHPRI_WIDTH                  4
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     0x40u
+#define DMA_DCHPRI5_DPA_SHIFT                    6
+#define DMA_DCHPRI5_DPA_WIDTH                    1
+#define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_DPA_SHIFT))&DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK                     0x80u
+#define DMA_DCHPRI5_ECP_SHIFT                    7
+#define DMA_DCHPRI5_ECP_WIDTH                    1
+#define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_ECP_SHIFT))&DMA_DCHPRI5_ECP_MASK)
+/* DCHPRI4 Bit Fields */
+#define DMA_DCHPRI4_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI4_CHPRI_SHIFT                  0
+#define DMA_DCHPRI4_CHPRI_WIDTH                  4
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     0x40u
+#define DMA_DCHPRI4_DPA_SHIFT                    6
+#define DMA_DCHPRI4_DPA_WIDTH                    1
+#define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_DPA_SHIFT))&DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK                     0x80u
+#define DMA_DCHPRI4_ECP_SHIFT                    7
+#define DMA_DCHPRI4_ECP_WIDTH                    1
+#define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_ECP_SHIFT))&DMA_DCHPRI4_ECP_MASK)
+/* DCHPRI11 Bit Fields */
+#define DMA_DCHPRI11_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI11_CHPRI_SHIFT                 0
+#define DMA_DCHPRI11_CHPRI_WIDTH                 4
+#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK                    0x40u
+#define DMA_DCHPRI11_DPA_SHIFT                   6
+#define DMA_DCHPRI11_DPA_WIDTH                   1
+#define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_DPA_SHIFT))&DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_ECP_MASK                    0x80u
+#define DMA_DCHPRI11_ECP_SHIFT                   7
+#define DMA_DCHPRI11_ECP_WIDTH                   1
+#define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_ECP_SHIFT))&DMA_DCHPRI11_ECP_MASK)
+/* DCHPRI10 Bit Fields */
+#define DMA_DCHPRI10_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI10_CHPRI_SHIFT                 0
+#define DMA_DCHPRI10_CHPRI_WIDTH                 4
+#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK                    0x40u
+#define DMA_DCHPRI10_DPA_SHIFT                   6
+#define DMA_DCHPRI10_DPA_WIDTH                   1
+#define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_DPA_SHIFT))&DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_ECP_MASK                    0x80u
+#define DMA_DCHPRI10_ECP_SHIFT                   7
+#define DMA_DCHPRI10_ECP_WIDTH                   1
+#define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_ECP_SHIFT))&DMA_DCHPRI10_ECP_MASK)
+/* DCHPRI9 Bit Fields */
+#define DMA_DCHPRI9_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI9_CHPRI_SHIFT                  0
+#define DMA_DCHPRI9_CHPRI_WIDTH                  4
+#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK                     0x40u
+#define DMA_DCHPRI9_DPA_SHIFT                    6
+#define DMA_DCHPRI9_DPA_WIDTH                    1
+#define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_DPA_SHIFT))&DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_ECP_MASK                     0x80u
+#define DMA_DCHPRI9_ECP_SHIFT                    7
+#define DMA_DCHPRI9_ECP_WIDTH                    1
+#define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_ECP_SHIFT))&DMA_DCHPRI9_ECP_MASK)
+/* DCHPRI8 Bit Fields */
+#define DMA_DCHPRI8_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI8_CHPRI_SHIFT                  0
+#define DMA_DCHPRI8_CHPRI_WIDTH                  4
+#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK                     0x40u
+#define DMA_DCHPRI8_DPA_SHIFT                    6
+#define DMA_DCHPRI8_DPA_WIDTH                    1
+#define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_DPA_SHIFT))&DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_ECP_MASK                     0x80u
+#define DMA_DCHPRI8_ECP_SHIFT                    7
+#define DMA_DCHPRI8_ECP_WIDTH                    1
+#define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_ECP_SHIFT))&DMA_DCHPRI8_ECP_MASK)
+/* DCHPRI15 Bit Fields */
+#define DMA_DCHPRI15_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI15_CHPRI_SHIFT                 0
+#define DMA_DCHPRI15_CHPRI_WIDTH                 4
+#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK                    0x40u
+#define DMA_DCHPRI15_DPA_SHIFT                   6
+#define DMA_DCHPRI15_DPA_WIDTH                   1
+#define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_DPA_SHIFT))&DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_ECP_MASK                    0x80u
+#define DMA_DCHPRI15_ECP_SHIFT                   7
+#define DMA_DCHPRI15_ECP_WIDTH                   1
+#define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_ECP_SHIFT))&DMA_DCHPRI15_ECP_MASK)
+/* DCHPRI14 Bit Fields */
+#define DMA_DCHPRI14_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI14_CHPRI_SHIFT                 0
+#define DMA_DCHPRI14_CHPRI_WIDTH                 4
+#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK                    0x40u
+#define DMA_DCHPRI14_DPA_SHIFT                   6
+#define DMA_DCHPRI14_DPA_WIDTH                   1
+#define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_DPA_SHIFT))&DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_ECP_MASK                    0x80u
+#define DMA_DCHPRI14_ECP_SHIFT                   7
+#define DMA_DCHPRI14_ECP_WIDTH                   1
+#define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_ECP_SHIFT))&DMA_DCHPRI14_ECP_MASK)
+/* DCHPRI13 Bit Fields */
+#define DMA_DCHPRI13_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI13_CHPRI_SHIFT                 0
+#define DMA_DCHPRI13_CHPRI_WIDTH                 4
+#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK                    0x40u
+#define DMA_DCHPRI13_DPA_SHIFT                   6
+#define DMA_DCHPRI13_DPA_WIDTH                   1
+#define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_DPA_SHIFT))&DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_ECP_MASK                    0x80u
+#define DMA_DCHPRI13_ECP_SHIFT                   7
+#define DMA_DCHPRI13_ECP_WIDTH                   1
+#define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_ECP_SHIFT))&DMA_DCHPRI13_ECP_MASK)
+/* DCHPRI12 Bit Fields */
+#define DMA_DCHPRI12_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI12_CHPRI_SHIFT                 0
+#define DMA_DCHPRI12_CHPRI_WIDTH                 4
+#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK                    0x40u
+#define DMA_DCHPRI12_DPA_SHIFT                   6
+#define DMA_DCHPRI12_DPA_WIDTH                   1
+#define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_DPA_SHIFT))&DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_ECP_MASK                    0x80u
+#define DMA_DCHPRI12_ECP_SHIFT                   7
+#define DMA_DCHPRI12_ECP_WIDTH                   1
+#define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_ECP_SHIFT))&DMA_DCHPRI12_ECP_MASK)
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK                     0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT                    0
+#define DMA_SADDR_SADDR_WIDTH                    32
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK                       0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT                      0
+#define DMA_SOFF_SOFF_WIDTH                      16
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK                      0x7u
+#define DMA_ATTR_DSIZE_SHIFT                     0
+#define DMA_ATTR_DSIZE_WIDTH                     3
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       0xF8u
+#define DMA_ATTR_DMOD_SHIFT                      3
+#define DMA_ATTR_DMOD_WIDTH                      5
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      0x700u
+#define DMA_ATTR_SSIZE_SHIFT                     8
+#define DMA_ATTR_SSIZE_WIDTH                     3
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       0xF800u
+#define DMA_ATTR_SMOD_SHIFT                      11
+#define DMA_ATTR_SMOD_WIDTH                      5
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             0
+#define DMA_NBYTES_MLNO_NBYTES_WIDTH             32
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          0
+#define DMA_NBYTES_MLOFFNO_NBYTES_WIDTH          30
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           30
+#define DMA_NBYTES_MLOFFNO_DMLOE_WIDTH           1
+#define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           31
+#define DMA_NBYTES_MLOFFNO_SMLOE_WIDTH           1
+#define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         0
+#define DMA_NBYTES_MLOFFYES_NBYTES_WIDTH         10
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          10
+#define DMA_NBYTES_MLOFFYES_MLOFF_WIDTH          20
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          30
+#define DMA_NBYTES_MLOFFYES_DMLOE_WIDTH          1
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          31
+#define DMA_NBYTES_MLOFFYES_SMLOE_WIDTH          1
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK                     0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT                    0
+#define DMA_SLAST_SLAST_WIDTH                    32
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK                     0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT                    0
+#define DMA_DADDR_DADDR_WIDTH                    32
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK                       0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT                      0
+#define DMA_DOFF_DOFF_WIDTH                      16
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK             0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT            0
+#define DMA_CITER_ELINKNO_CITER_WIDTH            15
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            15
+#define DMA_CITER_ELINKNO_ELINK_WIDTH            1
+#define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_ELINK_SHIFT))&DMA_CITER_ELINKNO_ELINK_MASK)
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK            0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT           0
+#define DMA_CITER_ELINKYES_CITER_WIDTH           9
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_CITER_ELINKYES_LINKCH_WIDTH          4
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           15
+#define DMA_CITER_ELINKYES_ELINK_WIDTH           1
+#define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_ELINK_SHIFT))&DMA_CITER_ELINKYES_ELINK_MASK)
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             0
+#define DMA_DLAST_SGA_DLASTSGA_WIDTH             32
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK                       0x1u
+#define DMA_CSR_START_SHIFT                      0
+#define DMA_CSR_START_WIDTH                      1
+#define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_CSR_START_SHIFT))&DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK                    0x2u
+#define DMA_CSR_INTMAJOR_SHIFT                   1
+#define DMA_CSR_INTMAJOR_WIDTH                   1
+#define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTMAJOR_SHIFT))&DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK                     0x4u
+#define DMA_CSR_INTHALF_SHIFT                    2
+#define DMA_CSR_INTHALF_WIDTH                    1
+#define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTHALF_SHIFT))&DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK                        0x8u
+#define DMA_CSR_DREQ_SHIFT                       3
+#define DMA_CSR_DREQ_WIDTH                       1
+#define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DREQ_SHIFT))&DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK                         0x10u
+#define DMA_CSR_ESG_SHIFT                        4
+#define DMA_CSR_ESG_WIDTH                        1
+#define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ESG_SHIFT))&DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK                  0x20u
+#define DMA_CSR_MAJORELINK_SHIFT                 5
+#define DMA_CSR_MAJORELINK_WIDTH                 1
+#define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORELINK_SHIFT))&DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK                      0x40u
+#define DMA_CSR_ACTIVE_SHIFT                     6
+#define DMA_CSR_ACTIVE_WIDTH                     1
+#define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ACTIVE_SHIFT))&DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK                        0x80u
+#define DMA_CSR_DONE_SHIFT                       7
+#define DMA_CSR_DONE_WIDTH                       1
+#define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DONE_SHIFT))&DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK                 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT                8
+#define DMA_CSR_MAJORLINKCH_WIDTH                4
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         0xC000u
+#define DMA_CSR_BWC_SHIFT                        14
+#define DMA_CSR_BWC_WIDTH                        2
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK             0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT            0
+#define DMA_BITER_ELINKNO_BITER_WIDTH            15
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            15
+#define DMA_BITER_ELINKNO_ELINK_WIDTH            1
+#define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_ELINK_SHIFT))&DMA_BITER_ELINKNO_ELINK_MASK)
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK            0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT           0
+#define DMA_BITER_ELINKYES_BITER_WIDTH           9
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_BITER_ELINKYES_LINKCH_WIDTH          4
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           15
+#define DMA_BITER_ELINKYES_ELINK_WIDTH           1
+#define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_ELINK_SHIFT))&DMA_BITER_ELINKYES_ELINK_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR                             (DMA0)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_CR                                   DMA_CR_REG(DMA0)
+#define DMA_ES                                   DMA_ES_REG(DMA0)
+#define DMA_ERQ                                  DMA_ERQ_REG(DMA0)
+#define DMA_EEI                                  DMA_EEI_REG(DMA0)
+#define DMA_CEEI                                 DMA_CEEI_REG(DMA0)
+#define DMA_SEEI                                 DMA_SEEI_REG(DMA0)
+#define DMA_CERQ                                 DMA_CERQ_REG(DMA0)
+#define DMA_SERQ                                 DMA_SERQ_REG(DMA0)
+#define DMA_CDNE                                 DMA_CDNE_REG(DMA0)
+#define DMA_SSRT                                 DMA_SSRT_REG(DMA0)
+#define DMA_CERR                                 DMA_CERR_REG(DMA0)
+#define DMA_CINT                                 DMA_CINT_REG(DMA0)
+#define DMA_INT                                  DMA_INT_REG(DMA0)
+#define DMA_ERR                                  DMA_ERR_REG(DMA0)
+#define DMA_HRS                                  DMA_HRS_REG(DMA0)
+#define DMA_DCHPRI3                              DMA_DCHPRI3_REG(DMA0)
+#define DMA_DCHPRI2                              DMA_DCHPRI2_REG(DMA0)
+#define DMA_DCHPRI1                              DMA_DCHPRI1_REG(DMA0)
+#define DMA_DCHPRI0                              DMA_DCHPRI0_REG(DMA0)
+#define DMA_DCHPRI7                              DMA_DCHPRI7_REG(DMA0)
+#define DMA_DCHPRI6                              DMA_DCHPRI6_REG(DMA0)
+#define DMA_DCHPRI5                              DMA_DCHPRI5_REG(DMA0)
+#define DMA_DCHPRI4                              DMA_DCHPRI4_REG(DMA0)
+#define DMA_DCHPRI11                             DMA_DCHPRI11_REG(DMA0)
+#define DMA_DCHPRI10                             DMA_DCHPRI10_REG(DMA0)
+#define DMA_DCHPRI9                              DMA_DCHPRI9_REG(DMA0)
+#define DMA_DCHPRI8                              DMA_DCHPRI8_REG(DMA0)
+#define DMA_DCHPRI15                             DMA_DCHPRI15_REG(DMA0)
+#define DMA_DCHPRI14                             DMA_DCHPRI14_REG(DMA0)
+#define DMA_DCHPRI13                             DMA_DCHPRI13_REG(DMA0)
+#define DMA_DCHPRI12                             DMA_DCHPRI12_REG(DMA0)
+#define DMA_TCD0_SADDR                           DMA_SADDR_REG(DMA0,0)
+#define DMA_TCD0_SOFF                            DMA_SOFF_REG(DMA0,0)
+#define DMA_TCD0_ATTR                            DMA_ATTR_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,0)
+#define DMA_TCD0_SLAST                           DMA_SLAST_REG(DMA0,0)
+#define DMA_TCD0_DADDR                           DMA_DADDR_REG(DMA0,0)
+#define DMA_TCD0_DOFF                            DMA_DOFF_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD0_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,0)
+#define DMA_TCD0_CSR                             DMA_CSR_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD1_SADDR                           DMA_SADDR_REG(DMA0,1)
+#define DMA_TCD1_SOFF                            DMA_SOFF_REG(DMA0,1)
+#define DMA_TCD1_ATTR                            DMA_ATTR_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,1)
+#define DMA_TCD1_SLAST                           DMA_SLAST_REG(DMA0,1)
+#define DMA_TCD1_DADDR                           DMA_DADDR_REG(DMA0,1)
+#define DMA_TCD1_DOFF                            DMA_DOFF_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD1_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,1)
+#define DMA_TCD1_CSR                             DMA_CSR_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD2_SADDR                           DMA_SADDR_REG(DMA0,2)
+#define DMA_TCD2_SOFF                            DMA_SOFF_REG(DMA0,2)
+#define DMA_TCD2_ATTR                            DMA_ATTR_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,2)
+#define DMA_TCD2_SLAST                           DMA_SLAST_REG(DMA0,2)
+#define DMA_TCD2_DADDR                           DMA_DADDR_REG(DMA0,2)
+#define DMA_TCD2_DOFF                            DMA_DOFF_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD2_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,2)
+#define DMA_TCD2_CSR                             DMA_CSR_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD3_SADDR                           DMA_SADDR_REG(DMA0,3)
+#define DMA_TCD3_SOFF                            DMA_SOFF_REG(DMA0,3)
+#define DMA_TCD3_ATTR                            DMA_ATTR_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,3)
+#define DMA_TCD3_SLAST                           DMA_SLAST_REG(DMA0,3)
+#define DMA_TCD3_DADDR                           DMA_DADDR_REG(DMA0,3)
+#define DMA_TCD3_DOFF                            DMA_DOFF_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD3_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,3)
+#define DMA_TCD3_CSR                             DMA_CSR_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD4_SADDR                           DMA_SADDR_REG(DMA0,4)
+#define DMA_TCD4_SOFF                            DMA_SOFF_REG(DMA0,4)
+#define DMA_TCD4_ATTR                            DMA_ATTR_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,4)
+#define DMA_TCD4_SLAST                           DMA_SLAST_REG(DMA0,4)
+#define DMA_TCD4_DADDR                           DMA_DADDR_REG(DMA0,4)
+#define DMA_TCD4_DOFF                            DMA_DOFF_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD4_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,4)
+#define DMA_TCD4_CSR                             DMA_CSR_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD5_SADDR                           DMA_SADDR_REG(DMA0,5)
+#define DMA_TCD5_SOFF                            DMA_SOFF_REG(DMA0,5)
+#define DMA_TCD5_ATTR                            DMA_ATTR_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,5)
+#define DMA_TCD5_SLAST                           DMA_SLAST_REG(DMA0,5)
+#define DMA_TCD5_DADDR                           DMA_DADDR_REG(DMA0,5)
+#define DMA_TCD5_DOFF                            DMA_DOFF_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD5_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,5)
+#define DMA_TCD5_CSR                             DMA_CSR_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD6_SADDR                           DMA_SADDR_REG(DMA0,6)
+#define DMA_TCD6_SOFF                            DMA_SOFF_REG(DMA0,6)
+#define DMA_TCD6_ATTR                            DMA_ATTR_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,6)
+#define DMA_TCD6_SLAST                           DMA_SLAST_REG(DMA0,6)
+#define DMA_TCD6_DADDR                           DMA_DADDR_REG(DMA0,6)
+#define DMA_TCD6_DOFF                            DMA_DOFF_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD6_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,6)
+#define DMA_TCD6_CSR                             DMA_CSR_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD7_SADDR                           DMA_SADDR_REG(DMA0,7)
+#define DMA_TCD7_SOFF                            DMA_SOFF_REG(DMA0,7)
+#define DMA_TCD7_ATTR                            DMA_ATTR_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,7)
+#define DMA_TCD7_SLAST                           DMA_SLAST_REG(DMA0,7)
+#define DMA_TCD7_DADDR                           DMA_DADDR_REG(DMA0,7)
+#define DMA_TCD7_DOFF                            DMA_DOFF_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD7_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,7)
+#define DMA_TCD7_CSR                             DMA_CSR_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD8_SADDR                           DMA_SADDR_REG(DMA0,8)
+#define DMA_TCD8_SOFF                            DMA_SOFF_REG(DMA0,8)
+#define DMA_TCD8_ATTR                            DMA_ATTR_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,8)
+#define DMA_TCD8_SLAST                           DMA_SLAST_REG(DMA0,8)
+#define DMA_TCD8_DADDR                           DMA_DADDR_REG(DMA0,8)
+#define DMA_TCD8_DOFF                            DMA_DOFF_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD8_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,8)
+#define DMA_TCD8_CSR                             DMA_CSR_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD9_SADDR                           DMA_SADDR_REG(DMA0,9)
+#define DMA_TCD9_SOFF                            DMA_SOFF_REG(DMA0,9)
+#define DMA_TCD9_ATTR                            DMA_ATTR_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,9)
+#define DMA_TCD9_SLAST                           DMA_SLAST_REG(DMA0,9)
+#define DMA_TCD9_DADDR                           DMA_DADDR_REG(DMA0,9)
+#define DMA_TCD9_DOFF                            DMA_DOFF_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD9_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,9)
+#define DMA_TCD9_CSR                             DMA_CSR_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD10_SADDR                          DMA_SADDR_REG(DMA0,10)
+#define DMA_TCD10_SOFF                           DMA_SOFF_REG(DMA0,10)
+#define DMA_TCD10_ATTR                           DMA_ATTR_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,10)
+#define DMA_TCD10_SLAST                          DMA_SLAST_REG(DMA0,10)
+#define DMA_TCD10_DADDR                          DMA_DADDR_REG(DMA0,10)
+#define DMA_TCD10_DOFF                           DMA_DOFF_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD10_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,10)
+#define DMA_TCD10_CSR                            DMA_CSR_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD11_SADDR                          DMA_SADDR_REG(DMA0,11)
+#define DMA_TCD11_SOFF                           DMA_SOFF_REG(DMA0,11)
+#define DMA_TCD11_ATTR                           DMA_ATTR_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,11)
+#define DMA_TCD11_SLAST                          DMA_SLAST_REG(DMA0,11)
+#define DMA_TCD11_DADDR                          DMA_DADDR_REG(DMA0,11)
+#define DMA_TCD11_DOFF                           DMA_DOFF_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD11_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,11)
+#define DMA_TCD11_CSR                            DMA_CSR_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD12_SADDR                          DMA_SADDR_REG(DMA0,12)
+#define DMA_TCD12_SOFF                           DMA_SOFF_REG(DMA0,12)
+#define DMA_TCD12_ATTR                           DMA_ATTR_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,12)
+#define DMA_TCD12_SLAST                          DMA_SLAST_REG(DMA0,12)
+#define DMA_TCD12_DADDR                          DMA_DADDR_REG(DMA0,12)
+#define DMA_TCD12_DOFF                           DMA_DOFF_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD12_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,12)
+#define DMA_TCD12_CSR                            DMA_CSR_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD13_SADDR                          DMA_SADDR_REG(DMA0,13)
+#define DMA_TCD13_SOFF                           DMA_SOFF_REG(DMA0,13)
+#define DMA_TCD13_ATTR                           DMA_ATTR_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,13)
+#define DMA_TCD13_SLAST                          DMA_SLAST_REG(DMA0,13)
+#define DMA_TCD13_DADDR                          DMA_DADDR_REG(DMA0,13)
+#define DMA_TCD13_DOFF                           DMA_DOFF_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD13_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,13)
+#define DMA_TCD13_CSR                            DMA_CSR_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD14_SADDR                          DMA_SADDR_REG(DMA0,14)
+#define DMA_TCD14_SOFF                           DMA_SOFF_REG(DMA0,14)
+#define DMA_TCD14_ATTR                           DMA_ATTR_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,14)
+#define DMA_TCD14_SLAST                          DMA_SLAST_REG(DMA0,14)
+#define DMA_TCD14_DADDR                          DMA_DADDR_REG(DMA0,14)
+#define DMA_TCD14_DOFF                           DMA_DOFF_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD14_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,14)
+#define DMA_TCD14_CSR                            DMA_CSR_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD15_SADDR                          DMA_SADDR_REG(DMA0,15)
+#define DMA_TCD15_SOFF                           DMA_SOFF_REG(DMA0,15)
+#define DMA_TCD15_ATTR                           DMA_ATTR_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,15)
+#define DMA_TCD15_SLAST                          DMA_SLAST_REG(DMA0,15)
+#define DMA_TCD15_DADDR                          DMA_DADDR_REG(DMA0,15)
+#define DMA_TCD15_DOFF                           DMA_DOFF_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,15)
+#define DMA_TCD15_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,15)
+#define DMA_TCD15_CSR                            DMA_CSR_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,15)
+
+/* DMA - Register array accessors */
+#define DMA_SADDR(index)                         DMA_SADDR_REG(DMA0,index)
+#define DMA_SOFF(index)                          DMA_SOFF_REG(DMA0,index)
+#define DMA_ATTR(index)                          DMA_ATTR_REG(DMA0,index)
+#define DMA_NBYTES_MLNO(index)                   DMA_NBYTES_MLNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFNO(index)                DMA_NBYTES_MLOFFNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFYES(index)               DMA_NBYTES_MLOFFYES_REG(DMA0,index)
+#define DMA_SLAST(index)                         DMA_SLAST_REG(DMA0,index)
+#define DMA_DADDR(index)                         DMA_DADDR_REG(DMA0,index)
+#define DMA_DOFF(index)                          DMA_DOFF_REG(DMA0,index)
+#define DMA_CITER_ELINKNO(index)                 DMA_CITER_ELINKNO_REG(DMA0,index)
+#define DMA_CITER_ELINKYES(index)                DMA_CITER_ELINKYES_REG(DMA0,index)
+#define DMA_DLAST_SGA(index)                     DMA_DLAST_SGA_REG(DMA0,index)
+#define DMA_CSR(index)                           DMA_CSR_REG(DMA0,index)
+#define DMA_BITER_ELINKNO(index)                 DMA_BITER_ELINKNO_REG(DMA0,index)
+#define DMA_BITER_ELINKYES(index)                DMA_BITER_ELINKYES_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[16];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index)             ((base)->CHCFG[index])
+#define DMAMUX_CHCFG_COUNT                       16
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT                0
+#define DMAMUX_CHCFG_SOURCE_WIDTH                6
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT                  6
+#define DMAMUX_CHCFG_TRIG_WIDTH                  1
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT                  7
+#define DMAMUX_CHCFG_ENBL_WIDTH                  1
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE                              (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
+#define DMAMUX_BASE_PTR                          (DMAMUX)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { DMAMUX }
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX */
+#define DMAMUX_CHCFG0                            DMAMUX_CHCFG_REG(DMAMUX,0)
+#define DMAMUX_CHCFG1                            DMAMUX_CHCFG_REG(DMAMUX,1)
+#define DMAMUX_CHCFG2                            DMAMUX_CHCFG_REG(DMAMUX,2)
+#define DMAMUX_CHCFG3                            DMAMUX_CHCFG_REG(DMAMUX,3)
+#define DMAMUX_CHCFG4                            DMAMUX_CHCFG_REG(DMAMUX,4)
+#define DMAMUX_CHCFG5                            DMAMUX_CHCFG_REG(DMAMUX,5)
+#define DMAMUX_CHCFG6                            DMAMUX_CHCFG_REG(DMAMUX,6)
+#define DMAMUX_CHCFG7                            DMAMUX_CHCFG_REG(DMAMUX,7)
+#define DMAMUX_CHCFG8                            DMAMUX_CHCFG_REG(DMAMUX,8)
+#define DMAMUX_CHCFG9                            DMAMUX_CHCFG_REG(DMAMUX,9)
+#define DMAMUX_CHCFG10                           DMAMUX_CHCFG_REG(DMAMUX,10)
+#define DMAMUX_CHCFG11                           DMAMUX_CHCFG_REG(DMAMUX,11)
+#define DMAMUX_CHCFG12                           DMAMUX_CHCFG_REG(DMAMUX,12)
+#define DMAMUX_CHCFG13                           DMAMUX_CHCFG_REG(DMAMUX,13)
+#define DMAMUX_CHCFG14                           DMAMUX_CHCFG_REG(DMAMUX,14)
+#define DMAMUX_CHCFG15                           DMAMUX_CHCFG_REG(DMAMUX,15)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX_CHCFG(index)                      DMAMUX_CHCFG_REG(DMAMUX,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4];
+  __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
+  __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register, offset: 0x10 */
+  __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register, offset: 0x14 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
+  __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
+       uint8_t RESERVED_4[28];
+  __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
+       uint8_t RESERVED_5[28];
+  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
+  __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
+  __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
+       uint8_t RESERVED_8[40];
+  __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+  __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+  __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
+  __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
+       uint8_t RESERVED_9[28];
+  __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
+       uint8_t RESERVED_10[56];
+  __IO uint32_t RDSR;                              /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+  __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+  __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+  __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+  __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+  __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+  __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+  __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+  __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+  __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+  __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
+       uint8_t RESERVED_12[12];
+  __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+  __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+       uint8_t RESERVED_13[60];
+  __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
+  __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
+  __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
+  __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
+  __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
+  __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
+  __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
+  __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
+  __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
+  __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
+  __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
+  __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
+  __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
+  __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
+  __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
+  __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
+  __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
+       uint8_t RESERVED_14[4];
+  __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
+  __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
+  __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
+  __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
+  __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
+  __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
+  __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
+  __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
+       uint8_t RESERVED_15[4];
+  __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
+  __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
+       uint8_t RESERVED_16[12];
+  __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
+  __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
+  __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
+  __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
+  __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
+  __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
+  __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
+  __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
+       uint8_t RESERVED_17[4];
+  __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
+  __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
+  __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
+  __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
+  __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
+  __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
+  __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
+  __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
+  __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
+  __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
+  __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
+  __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
+  __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
+  __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
+  __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
+       uint8_t RESERVED_18[284];
+  __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
+  __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
+  __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
+  __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
+  __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
+  __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
+  __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+       uint8_t RESERVED_19[488];
+  __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
+  struct {                                         /* offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+  } CHANNEL[4];
+} ENET_Type, *ENET_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register accessors */
+#define ENET_EIR_REG(base)                       ((base)->EIR)
+#define ENET_EIMR_REG(base)                      ((base)->EIMR)
+#define ENET_RDAR_REG(base)                      ((base)->RDAR)
+#define ENET_TDAR_REG(base)                      ((base)->TDAR)
+#define ENET_ECR_REG(base)                       ((base)->ECR)
+#define ENET_MMFR_REG(base)                      ((base)->MMFR)
+#define ENET_MSCR_REG(base)                      ((base)->MSCR)
+#define ENET_MIBC_REG(base)                      ((base)->MIBC)
+#define ENET_RCR_REG(base)                       ((base)->RCR)
+#define ENET_TCR_REG(base)                       ((base)->TCR)
+#define ENET_PALR_REG(base)                      ((base)->PALR)
+#define ENET_PAUR_REG(base)                      ((base)->PAUR)
+#define ENET_OPD_REG(base)                       ((base)->OPD)
+#define ENET_IAUR_REG(base)                      ((base)->IAUR)
+#define ENET_IALR_REG(base)                      ((base)->IALR)
+#define ENET_GAUR_REG(base)                      ((base)->GAUR)
+#define ENET_GALR_REG(base)                      ((base)->GALR)
+#define ENET_TFWR_REG(base)                      ((base)->TFWR)
+#define ENET_RDSR_REG(base)                      ((base)->RDSR)
+#define ENET_TDSR_REG(base)                      ((base)->TDSR)
+#define ENET_MRBR_REG(base)                      ((base)->MRBR)
+#define ENET_RSFL_REG(base)                      ((base)->RSFL)
+#define ENET_RSEM_REG(base)                      ((base)->RSEM)
+#define ENET_RAEM_REG(base)                      ((base)->RAEM)
+#define ENET_RAFL_REG(base)                      ((base)->RAFL)
+#define ENET_TSEM_REG(base)                      ((base)->TSEM)
+#define ENET_TAEM_REG(base)                      ((base)->TAEM)
+#define ENET_TAFL_REG(base)                      ((base)->TAFL)
+#define ENET_TIPG_REG(base)                      ((base)->TIPG)
+#define ENET_FTRL_REG(base)                      ((base)->FTRL)
+#define ENET_TACC_REG(base)                      ((base)->TACC)
+#define ENET_RACC_REG(base)                      ((base)->RACC)
+#define ENET_RMON_T_PACKETS_REG(base)            ((base)->RMON_T_PACKETS)
+#define ENET_RMON_T_BC_PKT_REG(base)             ((base)->RMON_T_BC_PKT)
+#define ENET_RMON_T_MC_PKT_REG(base)             ((base)->RMON_T_MC_PKT)
+#define ENET_RMON_T_CRC_ALIGN_REG(base)          ((base)->RMON_T_CRC_ALIGN)
+#define ENET_RMON_T_UNDERSIZE_REG(base)          ((base)->RMON_T_UNDERSIZE)
+#define ENET_RMON_T_OVERSIZE_REG(base)           ((base)->RMON_T_OVERSIZE)
+#define ENET_RMON_T_FRAG_REG(base)               ((base)->RMON_T_FRAG)
+#define ENET_RMON_T_JAB_REG(base)                ((base)->RMON_T_JAB)
+#define ENET_RMON_T_COL_REG(base)                ((base)->RMON_T_COL)
+#define ENET_RMON_T_P64_REG(base)                ((base)->RMON_T_P64)
+#define ENET_RMON_T_P65TO127_REG(base)           ((base)->RMON_T_P65TO127)
+#define ENET_RMON_T_P128TO255_REG(base)          ((base)->RMON_T_P128TO255)
+#define ENET_RMON_T_P256TO511_REG(base)          ((base)->RMON_T_P256TO511)
+#define ENET_RMON_T_P512TO1023_REG(base)         ((base)->RMON_T_P512TO1023)
+#define ENET_RMON_T_P1024TO2047_REG(base)        ((base)->RMON_T_P1024TO2047)
+#define ENET_RMON_T_P_GTE2048_REG(base)          ((base)->RMON_T_P_GTE2048)
+#define ENET_RMON_T_OCTETS_REG(base)             ((base)->RMON_T_OCTETS)
+#define ENET_IEEE_T_FRAME_OK_REG(base)           ((base)->IEEE_T_FRAME_OK)
+#define ENET_IEEE_T_1COL_REG(base)               ((base)->IEEE_T_1COL)
+#define ENET_IEEE_T_MCOL_REG(base)               ((base)->IEEE_T_MCOL)
+#define ENET_IEEE_T_DEF_REG(base)                ((base)->IEEE_T_DEF)
+#define ENET_IEEE_T_LCOL_REG(base)               ((base)->IEEE_T_LCOL)
+#define ENET_IEEE_T_EXCOL_REG(base)              ((base)->IEEE_T_EXCOL)
+#define ENET_IEEE_T_MACERR_REG(base)             ((base)->IEEE_T_MACERR)
+#define ENET_IEEE_T_CSERR_REG(base)              ((base)->IEEE_T_CSERR)
+#define ENET_IEEE_T_FDXFC_REG(base)              ((base)->IEEE_T_FDXFC)
+#define ENET_IEEE_T_OCTETS_OK_REG(base)          ((base)->IEEE_T_OCTETS_OK)
+#define ENET_RMON_R_PACKETS_REG(base)            ((base)->RMON_R_PACKETS)
+#define ENET_RMON_R_BC_PKT_REG(base)             ((base)->RMON_R_BC_PKT)
+#define ENET_RMON_R_MC_PKT_REG(base)             ((base)->RMON_R_MC_PKT)
+#define ENET_RMON_R_CRC_ALIGN_REG(base)          ((base)->RMON_R_CRC_ALIGN)
+#define ENET_RMON_R_UNDERSIZE_REG(base)          ((base)->RMON_R_UNDERSIZE)
+#define ENET_RMON_R_OVERSIZE_REG(base)           ((base)->RMON_R_OVERSIZE)
+#define ENET_RMON_R_FRAG_REG(base)               ((base)->RMON_R_FRAG)
+#define ENET_RMON_R_JAB_REG(base)                ((base)->RMON_R_JAB)
+#define ENET_RMON_R_P64_REG(base)                ((base)->RMON_R_P64)
+#define ENET_RMON_R_P65TO127_REG(base)           ((base)->RMON_R_P65TO127)
+#define ENET_RMON_R_P128TO255_REG(base)          ((base)->RMON_R_P128TO255)
+#define ENET_RMON_R_P256TO511_REG(base)          ((base)->RMON_R_P256TO511)
+#define ENET_RMON_R_P512TO1023_REG(base)         ((base)->RMON_R_P512TO1023)
+#define ENET_RMON_R_P1024TO2047_REG(base)        ((base)->RMON_R_P1024TO2047)
+#define ENET_RMON_R_P_GTE2048_REG(base)          ((base)->RMON_R_P_GTE2048)
+#define ENET_RMON_R_OCTETS_REG(base)             ((base)->RMON_R_OCTETS)
+#define ENET_IEEE_R_DROP_REG(base)               ((base)->IEEE_R_DROP)
+#define ENET_IEEE_R_FRAME_OK_REG(base)           ((base)->IEEE_R_FRAME_OK)
+#define ENET_IEEE_R_CRC_REG(base)                ((base)->IEEE_R_CRC)
+#define ENET_IEEE_R_ALIGN_REG(base)              ((base)->IEEE_R_ALIGN)
+#define ENET_IEEE_R_MACERR_REG(base)             ((base)->IEEE_R_MACERR)
+#define ENET_IEEE_R_FDXFC_REG(base)              ((base)->IEEE_R_FDXFC)
+#define ENET_IEEE_R_OCTETS_OK_REG(base)          ((base)->IEEE_R_OCTETS_OK)
+#define ENET_ATCR_REG(base)                      ((base)->ATCR)
+#define ENET_ATVR_REG(base)                      ((base)->ATVR)
+#define ENET_ATOFF_REG(base)                     ((base)->ATOFF)
+#define ENET_ATPER_REG(base)                     ((base)->ATPER)
+#define ENET_ATCOR_REG(base)                     ((base)->ATCOR)
+#define ENET_ATINC_REG(base)                     ((base)->ATINC)
+#define ENET_ATSTMP_REG(base)                    ((base)->ATSTMP)
+#define ENET_TGSR_REG(base)                      ((base)->TGSR)
+#define ENET_TCSR_REG(base,index)                ((base)->CHANNEL[index].TCSR)
+#define ENET_TCSR_COUNT                          4
+#define ENET_TCCR_REG(base,index)                ((base)->CHANNEL[index].TCCR)
+#define ENET_TCCR_COUNT                          4
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/* EIR Bit Fields */
+#define ENET_EIR_TS_TIMER_MASK                   0x8000u
+#define ENET_EIR_TS_TIMER_SHIFT                  15
+#define ENET_EIR_TS_TIMER_WIDTH                  1
+#define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_TIMER_SHIFT))&ENET_EIR_TS_TIMER_MASK)
+#define ENET_EIR_TS_AVAIL_MASK                   0x10000u
+#define ENET_EIR_TS_AVAIL_SHIFT                  16
+#define ENET_EIR_TS_AVAIL_WIDTH                  1
+#define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_AVAIL_SHIFT))&ENET_EIR_TS_AVAIL_MASK)
+#define ENET_EIR_WAKEUP_MASK                     0x20000u
+#define ENET_EIR_WAKEUP_SHIFT                    17
+#define ENET_EIR_WAKEUP_WIDTH                    1
+#define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_EIR_WAKEUP_SHIFT))&ENET_EIR_WAKEUP_MASK)
+#define ENET_EIR_PLR_MASK                        0x40000u
+#define ENET_EIR_PLR_SHIFT                       18
+#define ENET_EIR_PLR_WIDTH                       1
+#define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_PLR_SHIFT))&ENET_EIR_PLR_MASK)
+#define ENET_EIR_UN_MASK                         0x80000u
+#define ENET_EIR_UN_SHIFT                        19
+#define ENET_EIR_UN_WIDTH                        1
+#define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_UN_SHIFT))&ENET_EIR_UN_MASK)
+#define ENET_EIR_RL_MASK                         0x100000u
+#define ENET_EIR_RL_SHIFT                        20
+#define ENET_EIR_RL_WIDTH                        1
+#define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RL_SHIFT))&ENET_EIR_RL_MASK)
+#define ENET_EIR_LC_MASK                         0x200000u
+#define ENET_EIR_LC_SHIFT                        21
+#define ENET_EIR_LC_WIDTH                        1
+#define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_LC_SHIFT))&ENET_EIR_LC_MASK)
+#define ENET_EIR_EBERR_MASK                      0x400000u
+#define ENET_EIR_EBERR_SHIFT                     22
+#define ENET_EIR_EBERR_WIDTH                     1
+#define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIR_EBERR_SHIFT))&ENET_EIR_EBERR_MASK)
+#define ENET_EIR_MII_MASK                        0x800000u
+#define ENET_EIR_MII_SHIFT                       23
+#define ENET_EIR_MII_WIDTH                       1
+#define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_MII_SHIFT))&ENET_EIR_MII_MASK)
+#define ENET_EIR_RXB_MASK                        0x1000000u
+#define ENET_EIR_RXB_SHIFT                       24
+#define ENET_EIR_RXB_WIDTH                       1
+#define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXB_SHIFT))&ENET_EIR_RXB_MASK)
+#define ENET_EIR_RXF_MASK                        0x2000000u
+#define ENET_EIR_RXF_SHIFT                       25
+#define ENET_EIR_RXF_WIDTH                       1
+#define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXF_SHIFT))&ENET_EIR_RXF_MASK)
+#define ENET_EIR_TXB_MASK                        0x4000000u
+#define ENET_EIR_TXB_SHIFT                       26
+#define ENET_EIR_TXB_WIDTH                       1
+#define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXB_SHIFT))&ENET_EIR_TXB_MASK)
+#define ENET_EIR_TXF_MASK                        0x8000000u
+#define ENET_EIR_TXF_SHIFT                       27
+#define ENET_EIR_TXF_WIDTH                       1
+#define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXF_SHIFT))&ENET_EIR_TXF_MASK)
+#define ENET_EIR_GRA_MASK                        0x10000000u
+#define ENET_EIR_GRA_SHIFT                       28
+#define ENET_EIR_GRA_WIDTH                       1
+#define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_GRA_SHIFT))&ENET_EIR_GRA_MASK)
+#define ENET_EIR_BABT_MASK                       0x20000000u
+#define ENET_EIR_BABT_SHIFT                      29
+#define ENET_EIR_BABT_WIDTH                      1
+#define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABT_SHIFT))&ENET_EIR_BABT_MASK)
+#define ENET_EIR_BABR_MASK                       0x40000000u
+#define ENET_EIR_BABR_SHIFT                      30
+#define ENET_EIR_BABR_WIDTH                      1
+#define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABR_SHIFT))&ENET_EIR_BABR_MASK)
+/* EIMR Bit Fields */
+#define ENET_EIMR_TS_TIMER_MASK                  0x8000u
+#define ENET_EIMR_TS_TIMER_SHIFT                 15
+#define ENET_EIMR_TS_TIMER_WIDTH                 1
+#define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_TIMER_SHIFT))&ENET_EIMR_TS_TIMER_MASK)
+#define ENET_EIMR_TS_AVAIL_MASK                  0x10000u
+#define ENET_EIMR_TS_AVAIL_SHIFT                 16
+#define ENET_EIMR_TS_AVAIL_WIDTH                 1
+#define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_AVAIL_SHIFT))&ENET_EIMR_TS_AVAIL_MASK)
+#define ENET_EIMR_WAKEUP_MASK                    0x20000u
+#define ENET_EIMR_WAKEUP_SHIFT                   17
+#define ENET_EIMR_WAKEUP_WIDTH                   1
+#define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_WAKEUP_SHIFT))&ENET_EIMR_WAKEUP_MASK)
+#define ENET_EIMR_PLR_MASK                       0x40000u
+#define ENET_EIMR_PLR_SHIFT                      18
+#define ENET_EIMR_PLR_WIDTH                      1
+#define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_PLR_SHIFT))&ENET_EIMR_PLR_MASK)
+#define ENET_EIMR_UN_MASK                        0x80000u
+#define ENET_EIMR_UN_SHIFT                       19
+#define ENET_EIMR_UN_WIDTH                       1
+#define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_UN_SHIFT))&ENET_EIMR_UN_MASK)
+#define ENET_EIMR_RL_MASK                        0x100000u
+#define ENET_EIMR_RL_SHIFT                       20
+#define ENET_EIMR_RL_WIDTH                       1
+#define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RL_SHIFT))&ENET_EIMR_RL_MASK)
+#define ENET_EIMR_LC_MASK                        0x200000u
+#define ENET_EIMR_LC_SHIFT                       21
+#define ENET_EIMR_LC_WIDTH                       1
+#define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_LC_SHIFT))&ENET_EIMR_LC_MASK)
+#define ENET_EIMR_EBERR_MASK                     0x400000u
+#define ENET_EIMR_EBERR_SHIFT                    22
+#define ENET_EIMR_EBERR_WIDTH                    1
+#define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_EBERR_SHIFT))&ENET_EIMR_EBERR_MASK)
+#define ENET_EIMR_MII_MASK                       0x800000u
+#define ENET_EIMR_MII_SHIFT                      23
+#define ENET_EIMR_MII_WIDTH                      1
+#define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_MII_SHIFT))&ENET_EIMR_MII_MASK)
+#define ENET_EIMR_RXB_MASK                       0x1000000u
+#define ENET_EIMR_RXB_SHIFT                      24
+#define ENET_EIMR_RXB_WIDTH                      1
+#define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXB_SHIFT))&ENET_EIMR_RXB_MASK)
+#define ENET_EIMR_RXF_MASK                       0x2000000u
+#define ENET_EIMR_RXF_SHIFT                      25
+#define ENET_EIMR_RXF_WIDTH                      1
+#define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXF_SHIFT))&ENET_EIMR_RXF_MASK)
+#define ENET_EIMR_TXB_MASK                       0x4000000u
+#define ENET_EIMR_TXB_SHIFT                      26
+#define ENET_EIMR_TXB_WIDTH                      1
+#define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXB_SHIFT))&ENET_EIMR_TXB_MASK)
+#define ENET_EIMR_TXF_MASK                       0x8000000u
+#define ENET_EIMR_TXF_SHIFT                      27
+#define ENET_EIMR_TXF_WIDTH                      1
+#define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXF_SHIFT))&ENET_EIMR_TXF_MASK)
+#define ENET_EIMR_GRA_MASK                       0x10000000u
+#define ENET_EIMR_GRA_SHIFT                      28
+#define ENET_EIMR_GRA_WIDTH                      1
+#define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_GRA_SHIFT))&ENET_EIMR_GRA_MASK)
+#define ENET_EIMR_BABT_MASK                      0x20000000u
+#define ENET_EIMR_BABT_SHIFT                     29
+#define ENET_EIMR_BABT_WIDTH                     1
+#define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABT_SHIFT))&ENET_EIMR_BABT_MASK)
+#define ENET_EIMR_BABR_MASK                      0x40000000u
+#define ENET_EIMR_BABR_SHIFT                     30
+#define ENET_EIMR_BABR_WIDTH                     1
+#define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABR_SHIFT))&ENET_EIMR_BABR_MASK)
+/* RDAR Bit Fields */
+#define ENET_RDAR_RDAR_MASK                      0x1000000u
+#define ENET_RDAR_RDAR_SHIFT                     24
+#define ENET_RDAR_RDAR_WIDTH                     1
+#define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RDAR_RDAR_SHIFT))&ENET_RDAR_RDAR_MASK)
+/* TDAR Bit Fields */
+#define ENET_TDAR_TDAR_MASK                      0x1000000u
+#define ENET_TDAR_TDAR_SHIFT                     24
+#define ENET_TDAR_TDAR_WIDTH                     1
+#define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TDAR_TDAR_SHIFT))&ENET_TDAR_TDAR_MASK)
+/* ECR Bit Fields */
+#define ENET_ECR_RESET_MASK                      0x1u
+#define ENET_ECR_RESET_SHIFT                     0
+#define ENET_ECR_RESET_WIDTH                     1
+#define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_RESET_SHIFT))&ENET_ECR_RESET_MASK)
+#define ENET_ECR_ETHEREN_MASK                    0x2u
+#define ENET_ECR_ETHEREN_SHIFT                   1
+#define ENET_ECR_ETHEREN_WIDTH                   1
+#define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ECR_ETHEREN_SHIFT))&ENET_ECR_ETHEREN_MASK)
+#define ENET_ECR_MAGICEN_MASK                    0x4u
+#define ENET_ECR_MAGICEN_SHIFT                   2
+#define ENET_ECR_MAGICEN_WIDTH                   1
+#define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ECR_MAGICEN_SHIFT))&ENET_ECR_MAGICEN_MASK)
+#define ENET_ECR_SLEEP_MASK                      0x8u
+#define ENET_ECR_SLEEP_SHIFT                     3
+#define ENET_ECR_SLEEP_WIDTH                     1
+#define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_SLEEP_SHIFT))&ENET_ECR_SLEEP_MASK)
+#define ENET_ECR_EN1588_MASK                     0x10u
+#define ENET_ECR_EN1588_SHIFT                    4
+#define ENET_ECR_EN1588_WIDTH                    1
+#define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ECR_EN1588_SHIFT))&ENET_ECR_EN1588_MASK)
+#define ENET_ECR_DBGEN_MASK                      0x40u
+#define ENET_ECR_DBGEN_SHIFT                     6
+#define ENET_ECR_DBGEN_WIDTH                     1
+#define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBGEN_SHIFT))&ENET_ECR_DBGEN_MASK)
+#define ENET_ECR_STOPEN_MASK                     0x80u
+#define ENET_ECR_STOPEN_SHIFT                    7
+#define ENET_ECR_STOPEN_WIDTH                    1
+#define ENET_ECR_STOPEN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ECR_STOPEN_SHIFT))&ENET_ECR_STOPEN_MASK)
+#define ENET_ECR_DBSWP_MASK                      0x100u
+#define ENET_ECR_DBSWP_SHIFT                     8
+#define ENET_ECR_DBSWP_WIDTH                     1
+#define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBSWP_SHIFT))&ENET_ECR_DBSWP_MASK)
+/* MMFR Bit Fields */
+#define ENET_MMFR_DATA_MASK                      0xFFFFu
+#define ENET_MMFR_DATA_SHIFT                     0
+#define ENET_MMFR_DATA_WIDTH                     16
+#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK                        0x30000u
+#define ENET_MMFR_TA_SHIFT                       16
+#define ENET_MMFR_TA_WIDTH                       2
+#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK                        0x7C0000u
+#define ENET_MMFR_RA_SHIFT                       18
+#define ENET_MMFR_RA_WIDTH                       5
+#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK                        0xF800000u
+#define ENET_MMFR_PA_SHIFT                       23
+#define ENET_MMFR_PA_WIDTH                       5
+#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK                        0x30000000u
+#define ENET_MMFR_OP_SHIFT                       28
+#define ENET_MMFR_OP_WIDTH                       2
+#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK                        0xC0000000u
+#define ENET_MMFR_ST_SHIFT                       30
+#define ENET_MMFR_ST_WIDTH                       2
+#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
+/* MSCR Bit Fields */
+#define ENET_MSCR_MII_SPEED_MASK                 0x7Eu
+#define ENET_MSCR_MII_SPEED_SHIFT                1
+#define ENET_MSCR_MII_SPEED_WIDTH                6
+#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE_MASK                   0x80u
+#define ENET_MSCR_DIS_PRE_SHIFT                  7
+#define ENET_MSCR_DIS_PRE_WIDTH                  1
+#define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_DIS_PRE_SHIFT))&ENET_MSCR_DIS_PRE_MASK)
+#define ENET_MSCR_HOLDTIME_MASK                  0x700u
+#define ENET_MSCR_HOLDTIME_SHIFT                 8
+#define ENET_MSCR_HOLDTIME_WIDTH                 3
+#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
+/* MIBC Bit Fields */
+#define ENET_MIBC_MIB_CLEAR_MASK                 0x20000000u
+#define ENET_MIBC_MIB_CLEAR_SHIFT                29
+#define ENET_MIBC_MIB_CLEAR_WIDTH                1
+#define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_CLEAR_SHIFT))&ENET_MIBC_MIB_CLEAR_MASK)
+#define ENET_MIBC_MIB_IDLE_MASK                  0x40000000u
+#define ENET_MIBC_MIB_IDLE_SHIFT                 30
+#define ENET_MIBC_MIB_IDLE_WIDTH                 1
+#define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_IDLE_SHIFT))&ENET_MIBC_MIB_IDLE_MASK)
+#define ENET_MIBC_MIB_DIS_MASK                   0x80000000u
+#define ENET_MIBC_MIB_DIS_SHIFT                  31
+#define ENET_MIBC_MIB_DIS_WIDTH                  1
+#define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_DIS_SHIFT))&ENET_MIBC_MIB_DIS_MASK)
+/* RCR Bit Fields */
+#define ENET_RCR_LOOP_MASK                       0x1u
+#define ENET_RCR_LOOP_SHIFT                      0
+#define ENET_RCR_LOOP_WIDTH                      1
+#define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_LOOP_SHIFT))&ENET_RCR_LOOP_MASK)
+#define ENET_RCR_DRT_MASK                        0x2u
+#define ENET_RCR_DRT_SHIFT                       1
+#define ENET_RCR_DRT_WIDTH                       1
+#define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_DRT_SHIFT))&ENET_RCR_DRT_MASK)
+#define ENET_RCR_MII_MODE_MASK                   0x4u
+#define ENET_RCR_MII_MODE_SHIFT                  2
+#define ENET_RCR_MII_MODE_WIDTH                  1
+#define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MII_MODE_SHIFT))&ENET_RCR_MII_MODE_MASK)
+#define ENET_RCR_PROM_MASK                       0x8u
+#define ENET_RCR_PROM_SHIFT                      3
+#define ENET_RCR_PROM_WIDTH                      1
+#define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PROM_SHIFT))&ENET_RCR_PROM_MASK)
+#define ENET_RCR_BC_REJ_MASK                     0x10u
+#define ENET_RCR_BC_REJ_SHIFT                    4
+#define ENET_RCR_BC_REJ_WIDTH                    1
+#define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_BC_REJ_SHIFT))&ENET_RCR_BC_REJ_MASK)
+#define ENET_RCR_FCE_MASK                        0x20u
+#define ENET_RCR_FCE_SHIFT                       5
+#define ENET_RCR_FCE_WIDTH                       1
+#define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_FCE_SHIFT))&ENET_RCR_FCE_MASK)
+#define ENET_RCR_RMII_MODE_MASK                  0x100u
+#define ENET_RCR_RMII_MODE_SHIFT                 8
+#define ENET_RCR_RMII_MODE_WIDTH                 1
+#define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_MODE_SHIFT))&ENET_RCR_RMII_MODE_MASK)
+#define ENET_RCR_RMII_10T_MASK                   0x200u
+#define ENET_RCR_RMII_10T_SHIFT                  9
+#define ENET_RCR_RMII_10T_WIDTH                  1
+#define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_10T_SHIFT))&ENET_RCR_RMII_10T_MASK)
+#define ENET_RCR_PADEN_MASK                      0x1000u
+#define ENET_RCR_PADEN_SHIFT                     12
+#define ENET_RCR_PADEN_WIDTH                     1
+#define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PADEN_SHIFT))&ENET_RCR_PADEN_MASK)
+#define ENET_RCR_PAUFWD_MASK                     0x2000u
+#define ENET_RCR_PAUFWD_SHIFT                    13
+#define ENET_RCR_PAUFWD_WIDTH                    1
+#define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PAUFWD_SHIFT))&ENET_RCR_PAUFWD_MASK)
+#define ENET_RCR_CRCFWD_MASK                     0x4000u
+#define ENET_RCR_CRCFWD_SHIFT                    14
+#define ENET_RCR_CRCFWD_WIDTH                    1
+#define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CRCFWD_SHIFT))&ENET_RCR_CRCFWD_MASK)
+#define ENET_RCR_CFEN_MASK                       0x8000u
+#define ENET_RCR_CFEN_SHIFT                      15
+#define ENET_RCR_CFEN_WIDTH                      1
+#define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CFEN_SHIFT))&ENET_RCR_CFEN_MASK)
+#define ENET_RCR_MAX_FL_MASK                     0x3FFF0000u
+#define ENET_RCR_MAX_FL_SHIFT                    16
+#define ENET_RCR_MAX_FL_WIDTH                    14
+#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC_MASK                        0x40000000u
+#define ENET_RCR_NLC_SHIFT                       30
+#define ENET_RCR_NLC_WIDTH                       1
+#define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_NLC_SHIFT))&ENET_RCR_NLC_MASK)
+#define ENET_RCR_GRS_MASK                        0x80000000u
+#define ENET_RCR_GRS_SHIFT                       31
+#define ENET_RCR_GRS_WIDTH                       1
+#define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_GRS_SHIFT))&ENET_RCR_GRS_MASK)
+/* TCR Bit Fields */
+#define ENET_TCR_GTS_MASK                        0x1u
+#define ENET_TCR_GTS_SHIFT                       0
+#define ENET_TCR_GTS_WIDTH                       1
+#define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_TCR_GTS_SHIFT))&ENET_TCR_GTS_MASK)
+#define ENET_TCR_FDEN_MASK                       0x4u
+#define ENET_TCR_FDEN_SHIFT                      2
+#define ENET_TCR_FDEN_WIDTH                      1
+#define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCR_FDEN_SHIFT))&ENET_TCR_FDEN_MASK)
+#define ENET_TCR_TFC_PAUSE_MASK                  0x8u
+#define ENET_TCR_TFC_PAUSE_SHIFT                 3
+#define ENET_TCR_TFC_PAUSE_WIDTH                 1
+#define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_TCR_TFC_PAUSE_SHIFT))&ENET_TCR_TFC_PAUSE_MASK)
+#define ENET_TCR_RFC_PAUSE_MASK                  0x10u
+#define ENET_TCR_RFC_PAUSE_SHIFT                 4
+#define ENET_TCR_RFC_PAUSE_WIDTH                 1
+#define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_TCR_RFC_PAUSE_SHIFT))&ENET_TCR_RFC_PAUSE_MASK)
+#define ENET_TCR_ADDSEL_MASK                     0xE0u
+#define ENET_TCR_ADDSEL_SHIFT                    5
+#define ENET_TCR_ADDSEL_WIDTH                    3
+#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS_MASK                     0x100u
+#define ENET_TCR_ADDINS_SHIFT                    8
+#define ENET_TCR_ADDINS_WIDTH                    1
+#define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDINS_SHIFT))&ENET_TCR_ADDINS_MASK)
+#define ENET_TCR_CRCFWD_MASK                     0x200u
+#define ENET_TCR_CRCFWD_SHIFT                    9
+#define ENET_TCR_CRCFWD_WIDTH                    1
+#define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_CRCFWD_SHIFT))&ENET_TCR_CRCFWD_MASK)
+/* PALR Bit Fields */
+#define ENET_PALR_PADDR1_MASK                    0xFFFFFFFFu
+#define ENET_PALR_PADDR1_SHIFT                   0
+#define ENET_PALR_PADDR1_WIDTH                   32
+#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
+/* PAUR Bit Fields */
+#define ENET_PAUR_TYPE_MASK                      0xFFFFu
+#define ENET_PAUR_TYPE_SHIFT                     0
+#define ENET_PAUR_TYPE_WIDTH                     16
+#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK                    0xFFFF0000u
+#define ENET_PAUR_PADDR2_SHIFT                   16
+#define ENET_PAUR_PADDR2_WIDTH                   16
+#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
+/* OPD Bit Fields */
+#define ENET_OPD_PAUSE_DUR_MASK                  0xFFFFu
+#define ENET_OPD_PAUSE_DUR_SHIFT                 0
+#define ENET_OPD_PAUSE_DUR_WIDTH                 16
+#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK                     0xFFFF0000u
+#define ENET_OPD_OPCODE_SHIFT                    16
+#define ENET_OPD_OPCODE_WIDTH                    16
+#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
+/* IAUR Bit Fields */
+#define ENET_IAUR_IADDR1_MASK                    0xFFFFFFFFu
+#define ENET_IAUR_IADDR1_SHIFT                   0
+#define ENET_IAUR_IADDR1_WIDTH                   32
+#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
+/* IALR Bit Fields */
+#define ENET_IALR_IADDR2_MASK                    0xFFFFFFFFu
+#define ENET_IALR_IADDR2_SHIFT                   0
+#define ENET_IALR_IADDR2_WIDTH                   32
+#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
+/* GAUR Bit Fields */
+#define ENET_GAUR_GADDR1_MASK                    0xFFFFFFFFu
+#define ENET_GAUR_GADDR1_SHIFT                   0
+#define ENET_GAUR_GADDR1_WIDTH                   32
+#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
+/* GALR Bit Fields */
+#define ENET_GALR_GADDR2_MASK                    0xFFFFFFFFu
+#define ENET_GALR_GADDR2_SHIFT                   0
+#define ENET_GALR_GADDR2_WIDTH                   32
+#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
+/* TFWR Bit Fields */
+#define ENET_TFWR_TFWR_MASK                      0x3Fu
+#define ENET_TFWR_TFWR_SHIFT                     0
+#define ENET_TFWR_TFWR_WIDTH                     6
+#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD_MASK                    0x100u
+#define ENET_TFWR_STRFWD_SHIFT                   8
+#define ENET_TFWR_STRFWD_WIDTH                   1
+#define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_STRFWD_SHIFT))&ENET_TFWR_STRFWD_MASK)
+/* RDSR Bit Fields */
+#define ENET_RDSR_R_DES_START_MASK               0xFFFFFFF8u
+#define ENET_RDSR_R_DES_START_SHIFT              3
+#define ENET_RDSR_R_DES_START_WIDTH              29
+#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
+/* TDSR Bit Fields */
+#define ENET_TDSR_X_DES_START_MASK               0xFFFFFFF8u
+#define ENET_TDSR_X_DES_START_SHIFT              3
+#define ENET_TDSR_X_DES_START_WIDTH              29
+#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
+/* MRBR Bit Fields */
+#define ENET_MRBR_R_BUF_SIZE_MASK                0x3FF0u
+#define ENET_MRBR_R_BUF_SIZE_SHIFT               4
+#define ENET_MRBR_R_BUF_SIZE_WIDTH               10
+#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
+/* RSFL Bit Fields */
+#define ENET_RSFL_RX_SECTION_FULL_MASK           0xFFu
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT          0
+#define ENET_RSFL_RX_SECTION_FULL_WIDTH          8
+#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
+/* RSEM Bit Fields */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         0
+#define ENET_RSEM_RX_SECTION_EMPTY_WIDTH         8
+#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK        0x1F0000u
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       16
+#define ENET_RSEM_STAT_SECTION_EMPTY_WIDTH       5
+#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+/* RAEM Bit Fields */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          0
+#define ENET_RAEM_RX_ALMOST_EMPTY_WIDTH          8
+#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+/* RAFL Bit Fields */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK            0xFFu
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           0
+#define ENET_RAFL_RX_ALMOST_FULL_WIDTH           8
+#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
+/* TSEM Bit Fields */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         0
+#define ENET_TSEM_TX_SECTION_EMPTY_WIDTH         8
+#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
+/* TAEM Bit Fields */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          0
+#define ENET_TAEM_TX_ALMOST_EMPTY_WIDTH          8
+#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+/* TAFL Bit Fields */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK            0xFFu
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           0
+#define ENET_TAFL_TX_ALMOST_FULL_WIDTH           8
+#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
+/* TIPG Bit Fields */
+#define ENET_TIPG_IPG_MASK                       0x1Fu
+#define ENET_TIPG_IPG_SHIFT                      0
+#define ENET_TIPG_IPG_WIDTH                      5
+#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
+/* FTRL Bit Fields */
+#define ENET_FTRL_TRUNC_FL_MASK                  0x3FFFu
+#define ENET_FTRL_TRUNC_FL_SHIFT                 0
+#define ENET_FTRL_TRUNC_FL_WIDTH                 14
+#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
+/* TACC Bit Fields */
+#define ENET_TACC_SHIFT16_MASK                   0x1u
+#define ENET_TACC_SHIFT16_SHIFT                  0
+#define ENET_TACC_SHIFT16_WIDTH                  1
+#define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_TACC_SHIFT16_SHIFT))&ENET_TACC_SHIFT16_MASK)
+#define ENET_TACC_IPCHK_MASK                     0x8u
+#define ENET_TACC_IPCHK_SHIFT                    3
+#define ENET_TACC_IPCHK_WIDTH                    1
+#define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TACC_IPCHK_SHIFT))&ENET_TACC_IPCHK_MASK)
+#define ENET_TACC_PROCHK_MASK                    0x10u
+#define ENET_TACC_PROCHK_SHIFT                   4
+#define ENET_TACC_PROCHK_WIDTH                   1
+#define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_TACC_PROCHK_SHIFT))&ENET_TACC_PROCHK_MASK)
+/* RACC Bit Fields */
+#define ENET_RACC_PADREM_MASK                    0x1u
+#define ENET_RACC_PADREM_SHIFT                   0
+#define ENET_RACC_PADREM_WIDTH                   1
+#define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PADREM_SHIFT))&ENET_RACC_PADREM_MASK)
+#define ENET_RACC_IPDIS_MASK                     0x2u
+#define ENET_RACC_IPDIS_SHIFT                    1
+#define ENET_RACC_IPDIS_WIDTH                    1
+#define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RACC_IPDIS_SHIFT))&ENET_RACC_IPDIS_MASK)
+#define ENET_RACC_PRODIS_MASK                    0x4u
+#define ENET_RACC_PRODIS_SHIFT                   2
+#define ENET_RACC_PRODIS_WIDTH                   1
+#define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PRODIS_SHIFT))&ENET_RACC_PRODIS_MASK)
+#define ENET_RACC_LINEDIS_MASK                   0x40u
+#define ENET_RACC_LINEDIS_SHIFT                  6
+#define ENET_RACC_LINEDIS_WIDTH                  1
+#define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RACC_LINEDIS_SHIFT))&ENET_RACC_LINEDIS_MASK)
+#define ENET_RACC_SHIFT16_MASK                   0x80u
+#define ENET_RACC_SHIFT16_SHIFT                  7
+#define ENET_RACC_SHIFT16_WIDTH                  1
+#define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RACC_SHIFT16_SHIFT))&ENET_RACC_SHIFT16_MASK)
+/* RMON_T_PACKETS Bit Fields */
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK          0xFFFFu
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         0
+#define ENET_RMON_T_PACKETS_TXPKTS_WIDTH         16
+#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
+/* RMON_T_BC_PKT Bit Fields */
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           0xFFFFu
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          0
+#define ENET_RMON_T_BC_PKT_TXPKTS_WIDTH          16
+#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+/* RMON_T_MC_PKT Bit Fields */
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           0xFFFFu
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          0
+#define ENET_RMON_T_MC_PKT_TXPKTS_WIDTH          16
+#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+/* RMON_T_CRC_ALIGN Bit Fields */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       0
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_WIDTH       16
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+/* RMON_T_UNDERSIZE Bit Fields */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       0
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_WIDTH       16
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+/* RMON_T_OVERSIZE Bit Fields */
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         0xFFFFu
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        0
+#define ENET_RMON_T_OVERSIZE_TXPKTS_WIDTH        16
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+/* RMON_T_FRAG Bit Fields */
+#define ENET_RMON_T_FRAG_TXPKTS_MASK             0xFFFFu
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            0
+#define ENET_RMON_T_FRAG_TXPKTS_WIDTH            16
+#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
+/* RMON_T_JAB Bit Fields */
+#define ENET_RMON_T_JAB_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT             0
+#define ENET_RMON_T_JAB_TXPKTS_WIDTH             16
+#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
+/* RMON_T_COL Bit Fields */
+#define ENET_RMON_T_COL_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_COL_TXPKTS_SHIFT             0
+#define ENET_RMON_T_COL_TXPKTS_WIDTH             16
+#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
+/* RMON_T_P64 Bit Fields */
+#define ENET_RMON_T_P64_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_P64_TXPKTS_SHIFT             0
+#define ENET_RMON_T_P64_TXPKTS_WIDTH             16
+#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
+/* RMON_T_P65TO127 Bit Fields */
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK         0xFFFFu
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        0
+#define ENET_RMON_T_P65TO127_TXPKTS_WIDTH        16
+#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
+/* RMON_T_P128TO255 Bit Fields */
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P128TO255_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
+/* RMON_T_P256TO511 Bit Fields */
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P256TO511_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
+/* RMON_T_P512TO1023 Bit Fields */
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       0xFFFFu
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      0
+#define ENET_RMON_T_P512TO1023_TXPKTS_WIDTH      16
+#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+/* RMON_T_P1024TO2047 Bit Fields */
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      0xFFFFu
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     0
+#define ENET_RMON_T_P1024TO2047_TXPKTS_WIDTH     16
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+/* RMON_T_P_GTE2048 Bit Fields */
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P_GTE2048_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+/* RMON_T_OCTETS Bit Fields */
+#define ENET_RMON_T_OCTETS_TXOCTS_MASK           0xFFFFFFFFu
+#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          0
+#define ENET_RMON_T_OCTETS_TXOCTS_WIDTH          32
+#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
+/* IEEE_T_FRAME_OK Bit Fields */
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          0xFFFFu
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         0
+#define ENET_IEEE_T_FRAME_OK_COUNT_WIDTH         16
+#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+/* IEEE_T_1COL Bit Fields */
+#define ENET_IEEE_T_1COL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_1COL_COUNT_SHIFT             0
+#define ENET_IEEE_T_1COL_COUNT_WIDTH             16
+#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
+/* IEEE_T_MCOL Bit Fields */
+#define ENET_IEEE_T_MCOL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT             0
+#define ENET_IEEE_T_MCOL_COUNT_WIDTH             16
+#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
+/* IEEE_T_DEF Bit Fields */
+#define ENET_IEEE_T_DEF_COUNT_MASK               0xFFFFu
+#define ENET_IEEE_T_DEF_COUNT_SHIFT              0
+#define ENET_IEEE_T_DEF_COUNT_WIDTH              16
+#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
+/* IEEE_T_LCOL Bit Fields */
+#define ENET_IEEE_T_LCOL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT             0
+#define ENET_IEEE_T_LCOL_COUNT_WIDTH             16
+#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
+/* IEEE_T_EXCOL Bit Fields */
+#define ENET_IEEE_T_EXCOL_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            0
+#define ENET_IEEE_T_EXCOL_COUNT_WIDTH            16
+#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
+/* IEEE_T_MACERR Bit Fields */
+#define ENET_IEEE_T_MACERR_COUNT_MASK            0xFFFFu
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT           0
+#define ENET_IEEE_T_MACERR_COUNT_WIDTH           16
+#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
+/* IEEE_T_CSERR Bit Fields */
+#define ENET_IEEE_T_CSERR_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT            0
+#define ENET_IEEE_T_CSERR_COUNT_WIDTH            16
+#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
+/* IEEE_T_FDXFC Bit Fields */
+#define ENET_IEEE_T_FDXFC_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            0
+#define ENET_IEEE_T_FDXFC_COUNT_WIDTH            16
+#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
+/* IEEE_T_OCTETS_OK Bit Fields */
+#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        0
+#define ENET_IEEE_T_OCTETS_OK_COUNT_WIDTH        32
+#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+/* RMON_R_PACKETS Bit Fields */
+#define ENET_RMON_R_PACKETS_COUNT_MASK           0xFFFFu
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT          0
+#define ENET_RMON_R_PACKETS_COUNT_WIDTH          16
+#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
+/* RMON_R_BC_PKT Bit Fields */
+#define ENET_RMON_R_BC_PKT_COUNT_MASK            0xFFFFu
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           0
+#define ENET_RMON_R_BC_PKT_COUNT_WIDTH           16
+#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
+/* RMON_R_MC_PKT Bit Fields */
+#define ENET_RMON_R_MC_PKT_COUNT_MASK            0xFFFFu
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           0
+#define ENET_RMON_R_MC_PKT_COUNT_WIDTH           16
+#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
+/* RMON_R_CRC_ALIGN Bit Fields */
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        0
+#define ENET_RMON_R_CRC_ALIGN_COUNT_WIDTH        16
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+/* RMON_R_UNDERSIZE Bit Fields */
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        0
+#define ENET_RMON_R_UNDERSIZE_COUNT_WIDTH        16
+#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+/* RMON_R_OVERSIZE Bit Fields */
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK          0xFFFFu
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         0
+#define ENET_RMON_R_OVERSIZE_COUNT_WIDTH         16
+#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
+/* RMON_R_FRAG Bit Fields */
+#define ENET_RMON_R_FRAG_COUNT_MASK              0xFFFFu
+#define ENET_RMON_R_FRAG_COUNT_SHIFT             0
+#define ENET_RMON_R_FRAG_COUNT_WIDTH             16
+#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
+/* RMON_R_JAB Bit Fields */
+#define ENET_RMON_R_JAB_COUNT_MASK               0xFFFFu
+#define ENET_RMON_R_JAB_COUNT_SHIFT              0
+#define ENET_RMON_R_JAB_COUNT_WIDTH              16
+#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
+/* RMON_R_P64 Bit Fields */
+#define ENET_RMON_R_P64_COUNT_MASK               0xFFFFu
+#define ENET_RMON_R_P64_COUNT_SHIFT              0
+#define ENET_RMON_R_P64_COUNT_WIDTH              16
+#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
+/* RMON_R_P65TO127 Bit Fields */
+#define ENET_RMON_R_P65TO127_COUNT_MASK          0xFFFFu
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT         0
+#define ENET_RMON_R_P65TO127_COUNT_WIDTH         16
+#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
+/* RMON_R_P128TO255 Bit Fields */
+#define ENET_RMON_R_P128TO255_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT        0
+#define ENET_RMON_R_P128TO255_COUNT_WIDTH        16
+#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
+/* RMON_R_P256TO511 Bit Fields */
+#define ENET_RMON_R_P256TO511_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT        0
+#define ENET_RMON_R_P256TO511_COUNT_WIDTH        16
+#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
+/* RMON_R_P512TO1023 Bit Fields */
+#define ENET_RMON_R_P512TO1023_COUNT_MASK        0xFFFFu
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       0
+#define ENET_RMON_R_P512TO1023_COUNT_WIDTH       16
+#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
+/* RMON_R_P1024TO2047 Bit Fields */
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK       0xFFFFu
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      0
+#define ENET_RMON_R_P1024TO2047_COUNT_WIDTH      16
+#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
+/* RMON_R_P_GTE2048 Bit Fields */
+#define ENET_RMON_R_P_GTE2048_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        0
+#define ENET_RMON_R_P_GTE2048_COUNT_WIDTH        16
+#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
+/* RMON_R_OCTETS Bit Fields */
+#define ENET_RMON_R_OCTETS_COUNT_MASK            0xFFFFFFFFu
+#define ENET_RMON_R_OCTETS_COUNT_SHIFT           0
+#define ENET_RMON_R_OCTETS_COUNT_WIDTH           32
+#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
+/* IEEE_R_DROP Bit Fields */
+#define ENET_IEEE_R_DROP_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_R_DROP_COUNT_SHIFT             0
+#define ENET_IEEE_R_DROP_COUNT_WIDTH             16
+#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
+/* IEEE_R_FRAME_OK Bit Fields */
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          0xFFFFu
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         0
+#define ENET_IEEE_R_FRAME_OK_COUNT_WIDTH         16
+#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+/* IEEE_R_CRC Bit Fields */
+#define ENET_IEEE_R_CRC_COUNT_MASK               0xFFFFu
+#define ENET_IEEE_R_CRC_COUNT_SHIFT              0
+#define ENET_IEEE_R_CRC_COUNT_WIDTH              16
+#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
+/* IEEE_R_ALIGN Bit Fields */
+#define ENET_IEEE_R_ALIGN_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            0
+#define ENET_IEEE_R_ALIGN_COUNT_WIDTH            16
+#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
+/* IEEE_R_MACERR Bit Fields */
+#define ENET_IEEE_R_MACERR_COUNT_MASK            0xFFFFu
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT           0
+#define ENET_IEEE_R_MACERR_COUNT_WIDTH           16
+#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
+/* IEEE_R_FDXFC Bit Fields */
+#define ENET_IEEE_R_FDXFC_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            0
+#define ENET_IEEE_R_FDXFC_COUNT_WIDTH            16
+#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
+/* IEEE_R_OCTETS_OK Bit Fields */
+#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        0
+#define ENET_IEEE_R_OCTETS_OK_COUNT_WIDTH        32
+#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+/* ATCR Bit Fields */
+#define ENET_ATCR_EN_MASK                        0x1u
+#define ENET_ATCR_EN_SHIFT                       0
+#define ENET_ATCR_EN_WIDTH                       1
+#define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_EN_SHIFT))&ENET_ATCR_EN_MASK)
+#define ENET_ATCR_OFFEN_MASK                     0x4u
+#define ENET_ATCR_OFFEN_SHIFT                    2
+#define ENET_ATCR_OFFEN_WIDTH                    1
+#define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFEN_SHIFT))&ENET_ATCR_OFFEN_MASK)
+#define ENET_ATCR_OFFRST_MASK                    0x8u
+#define ENET_ATCR_OFFRST_SHIFT                   3
+#define ENET_ATCR_OFFRST_WIDTH                   1
+#define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFRST_SHIFT))&ENET_ATCR_OFFRST_MASK)
+#define ENET_ATCR_PEREN_MASK                     0x10u
+#define ENET_ATCR_PEREN_SHIFT                    4
+#define ENET_ATCR_PEREN_WIDTH                    1
+#define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PEREN_SHIFT))&ENET_ATCR_PEREN_MASK)
+#define ENET_ATCR_PINPER_MASK                    0x80u
+#define ENET_ATCR_PINPER_SHIFT                   7
+#define ENET_ATCR_PINPER_WIDTH                   1
+#define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PINPER_SHIFT))&ENET_ATCR_PINPER_MASK)
+#define ENET_ATCR_RESTART_MASK                   0x200u
+#define ENET_ATCR_RESTART_SHIFT                  9
+#define ENET_ATCR_RESTART_WIDTH                  1
+#define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_RESTART_SHIFT))&ENET_ATCR_RESTART_MASK)
+#define ENET_ATCR_CAPTURE_MASK                   0x800u
+#define ENET_ATCR_CAPTURE_SHIFT                  11
+#define ENET_ATCR_CAPTURE_WIDTH                  1
+#define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_CAPTURE_SHIFT))&ENET_ATCR_CAPTURE_MASK)
+#define ENET_ATCR_SLAVE_MASK                     0x2000u
+#define ENET_ATCR_SLAVE_SHIFT                    13
+#define ENET_ATCR_SLAVE_WIDTH                    1
+#define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_SLAVE_SHIFT))&ENET_ATCR_SLAVE_MASK)
+/* ATVR Bit Fields */
+#define ENET_ATVR_ATIME_MASK                     0xFFFFFFFFu
+#define ENET_ATVR_ATIME_SHIFT                    0
+#define ENET_ATVR_ATIME_WIDTH                    32
+#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
+/* ATOFF Bit Fields */
+#define ENET_ATOFF_OFFSET_MASK                   0xFFFFFFFFu
+#define ENET_ATOFF_OFFSET_SHIFT                  0
+#define ENET_ATOFF_OFFSET_WIDTH                  32
+#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
+/* ATPER Bit Fields */
+#define ENET_ATPER_PERIOD_MASK                   0xFFFFFFFFu
+#define ENET_ATPER_PERIOD_SHIFT                  0
+#define ENET_ATPER_PERIOD_WIDTH                  32
+#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
+/* ATCOR Bit Fields */
+#define ENET_ATCOR_COR_MASK                      0x7FFFFFFFu
+#define ENET_ATCOR_COR_SHIFT                     0
+#define ENET_ATCOR_COR_WIDTH                     31
+#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
+/* ATINC Bit Fields */
+#define ENET_ATINC_INC_MASK                      0x7Fu
+#define ENET_ATINC_INC_SHIFT                     0
+#define ENET_ATINC_INC_WIDTH                     7
+#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK                 0x7F00u
+#define ENET_ATINC_INC_CORR_SHIFT                8
+#define ENET_ATINC_INC_CORR_WIDTH                7
+#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
+/* ATSTMP Bit Fields */
+#define ENET_ATSTMP_TIMESTAMP_MASK               0xFFFFFFFFu
+#define ENET_ATSTMP_TIMESTAMP_SHIFT              0
+#define ENET_ATSTMP_TIMESTAMP_WIDTH              32
+#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
+/* TGSR Bit Fields */
+#define ENET_TGSR_TF0_MASK                       0x1u
+#define ENET_TGSR_TF0_SHIFT                      0
+#define ENET_TGSR_TF0_WIDTH                      1
+#define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF0_SHIFT))&ENET_TGSR_TF0_MASK)
+#define ENET_TGSR_TF1_MASK                       0x2u
+#define ENET_TGSR_TF1_SHIFT                      1
+#define ENET_TGSR_TF1_WIDTH                      1
+#define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF1_SHIFT))&ENET_TGSR_TF1_MASK)
+#define ENET_TGSR_TF2_MASK                       0x4u
+#define ENET_TGSR_TF2_SHIFT                      2
+#define ENET_TGSR_TF2_WIDTH                      1
+#define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF2_SHIFT))&ENET_TGSR_TF2_MASK)
+#define ENET_TGSR_TF3_MASK                       0x8u
+#define ENET_TGSR_TF3_SHIFT                      3
+#define ENET_TGSR_TF3_WIDTH                      1
+#define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF3_SHIFT))&ENET_TGSR_TF3_MASK)
+/* TCSR Bit Fields */
+#define ENET_TCSR_TDRE_MASK                      0x1u
+#define ENET_TCSR_TDRE_SHIFT                     0
+#define ENET_TCSR_TDRE_WIDTH                     1
+#define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TDRE_SHIFT))&ENET_TCSR_TDRE_MASK)
+#define ENET_TCSR_TMODE_MASK                     0x3Cu
+#define ENET_TCSR_TMODE_SHIFT                    2
+#define ENET_TCSR_TMODE_WIDTH                    4
+#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE_MASK                       0x40u
+#define ENET_TCSR_TIE_SHIFT                      6
+#define ENET_TCSR_TIE_WIDTH                      1
+#define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TIE_SHIFT))&ENET_TCSR_TIE_MASK)
+#define ENET_TCSR_TF_MASK                        0x80u
+#define ENET_TCSR_TF_SHIFT                       7
+#define ENET_TCSR_TF_WIDTH                       1
+#define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TF_SHIFT))&ENET_TCSR_TF_MASK)
+/* TCCR Bit Fields */
+#define ENET_TCCR_TCC_MASK                       0xFFFFFFFFu
+#define ENET_TCCR_TCC_SHIFT                      0
+#define ENET_TCCR_TCC_WIDTH                      32
+#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE                                (0x400C0000u)
+/** Peripheral ENET base pointer */
+#define ENET                                     ((ENET_Type *)ENET_BASE)
+#define ENET_BASE_PTR                            (ENET)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS                          { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS                           { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_Transmit_IRQS                       { ENET_Transmit_IRQn }
+#define ENET_Receive_IRQS                        { ENET_Receive_IRQn }
+#define ENET_Error_IRQS                          { ENET_Error_IRQn }
+#define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register instance definitions */
+/* ENET */
+#define ENET_EIR                                 ENET_EIR_REG(ENET)
+#define ENET_EIMR                                ENET_EIMR_REG(ENET)
+#define ENET_RDAR                                ENET_RDAR_REG(ENET)
+#define ENET_TDAR                                ENET_TDAR_REG(ENET)
+#define ENET_ECR                                 ENET_ECR_REG(ENET)
+#define ENET_MMFR                                ENET_MMFR_REG(ENET)
+#define ENET_MSCR                                ENET_MSCR_REG(ENET)
+#define ENET_MIBC                                ENET_MIBC_REG(ENET)
+#define ENET_RCR                                 ENET_RCR_REG(ENET)
+#define ENET_TCR                                 ENET_TCR_REG(ENET)
+#define ENET_PALR                                ENET_PALR_REG(ENET)
+#define ENET_PAUR                                ENET_PAUR_REG(ENET)
+#define ENET_OPD                                 ENET_OPD_REG(ENET)
+#define ENET_IAUR                                ENET_IAUR_REG(ENET)
+#define ENET_IALR                                ENET_IALR_REG(ENET)
+#define ENET_GAUR                                ENET_GAUR_REG(ENET)
+#define ENET_GALR                                ENET_GALR_REG(ENET)
+#define ENET_TFWR                                ENET_TFWR_REG(ENET)
+#define ENET_RDSR                                ENET_RDSR_REG(ENET)
+#define ENET_TDSR                                ENET_TDSR_REG(ENET)
+#define ENET_MRBR                                ENET_MRBR_REG(ENET)
+#define ENET_RSFL                                ENET_RSFL_REG(ENET)
+#define ENET_RSEM                                ENET_RSEM_REG(ENET)
+#define ENET_RAEM                                ENET_RAEM_REG(ENET)
+#define ENET_RAFL                                ENET_RAFL_REG(ENET)
+#define ENET_TSEM                                ENET_TSEM_REG(ENET)
+#define ENET_TAEM                                ENET_TAEM_REG(ENET)
+#define ENET_TAFL                                ENET_TAFL_REG(ENET)
+#define ENET_TIPG                                ENET_TIPG_REG(ENET)
+#define ENET_FTRL                                ENET_FTRL_REG(ENET)
+#define ENET_TACC                                ENET_TACC_REG(ENET)
+#define ENET_RACC                                ENET_RACC_REG(ENET)
+#define ENET_RMON_T_PACKETS                      ENET_RMON_T_PACKETS_REG(ENET)
+#define ENET_RMON_T_BC_PKT                       ENET_RMON_T_BC_PKT_REG(ENET)
+#define ENET_RMON_T_MC_PKT                       ENET_RMON_T_MC_PKT_REG(ENET)
+#define ENET_RMON_T_CRC_ALIGN                    ENET_RMON_T_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_T_UNDERSIZE                    ENET_RMON_T_UNDERSIZE_REG(ENET)
+#define ENET_RMON_T_OVERSIZE                     ENET_RMON_T_OVERSIZE_REG(ENET)
+#define ENET_RMON_T_FRAG                         ENET_RMON_T_FRAG_REG(ENET)
+#define ENET_RMON_T_JAB                          ENET_RMON_T_JAB_REG(ENET)
+#define ENET_RMON_T_COL                          ENET_RMON_T_COL_REG(ENET)
+#define ENET_RMON_T_P64                          ENET_RMON_T_P64_REG(ENET)
+#define ENET_RMON_T_P65TO127                     ENET_RMON_T_P65TO127_REG(ENET)
+#define ENET_RMON_T_P128TO255                    ENET_RMON_T_P128TO255_REG(ENET)
+#define ENET_RMON_T_P256TO511                    ENET_RMON_T_P256TO511_REG(ENET)
+#define ENET_RMON_T_P512TO1023                   ENET_RMON_T_P512TO1023_REG(ENET)
+#define ENET_RMON_T_P1024TO2047                  ENET_RMON_T_P1024TO2047_REG(ENET)
+#define ENET_RMON_T_P_GTE2048                    ENET_RMON_T_P_GTE2048_REG(ENET)
+#define ENET_RMON_T_OCTETS                       ENET_RMON_T_OCTETS_REG(ENET)
+#define ENET_IEEE_T_FRAME_OK                     ENET_IEEE_T_FRAME_OK_REG(ENET)
+#define ENET_IEEE_T_1COL                         ENET_IEEE_T_1COL_REG(ENET)
+#define ENET_IEEE_T_MCOL                         ENET_IEEE_T_MCOL_REG(ENET)
+#define ENET_IEEE_T_DEF                          ENET_IEEE_T_DEF_REG(ENET)
+#define ENET_IEEE_T_LCOL                         ENET_IEEE_T_LCOL_REG(ENET)
+#define ENET_IEEE_T_EXCOL                        ENET_IEEE_T_EXCOL_REG(ENET)
+#define ENET_IEEE_T_MACERR                       ENET_IEEE_T_MACERR_REG(ENET)
+#define ENET_IEEE_T_CSERR                        ENET_IEEE_T_CSERR_REG(ENET)
+#define ENET_IEEE_T_FDXFC                        ENET_IEEE_T_FDXFC_REG(ENET)
+#define ENET_IEEE_T_OCTETS_OK                    ENET_IEEE_T_OCTETS_OK_REG(ENET)
+#define ENET_RMON_R_PACKETS                      ENET_RMON_R_PACKETS_REG(ENET)
+#define ENET_RMON_R_BC_PKT                       ENET_RMON_R_BC_PKT_REG(ENET)
+#define ENET_RMON_R_MC_PKT                       ENET_RMON_R_MC_PKT_REG(ENET)
+#define ENET_RMON_R_CRC_ALIGN                    ENET_RMON_R_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_R_UNDERSIZE                    ENET_RMON_R_UNDERSIZE_REG(ENET)
+#define ENET_RMON_R_OVERSIZE                     ENET_RMON_R_OVERSIZE_REG(ENET)
+#define ENET_RMON_R_FRAG                         ENET_RMON_R_FRAG_REG(ENET)
+#define ENET_RMON_R_JAB                          ENET_RMON_R_JAB_REG(ENET)
+#define ENET_RMON_R_P64                          ENET_RMON_R_P64_REG(ENET)
+#define ENET_RMON_R_P65TO127                     ENET_RMON_R_P65TO127_REG(ENET)
+#define ENET_RMON_R_P128TO255                    ENET_RMON_R_P128TO255_REG(ENET)
+#define ENET_RMON_R_P256TO511                    ENET_RMON_R_P256TO511_REG(ENET)
+#define ENET_RMON_R_P512TO1023                   ENET_RMON_R_P512TO1023_REG(ENET)
+#define ENET_RMON_R_P1024TO2047                  ENET_RMON_R_P1024TO2047_REG(ENET)
+#define ENET_RMON_R_P_GTE2048                    ENET_RMON_R_P_GTE2048_REG(ENET)
+#define ENET_RMON_R_OCTETS                       ENET_RMON_R_OCTETS_REG(ENET)
+#define ENET_IEEE_R_DROP                         ENET_IEEE_R_DROP_REG(ENET)
+#define ENET_IEEE_R_FRAME_OK                     ENET_IEEE_R_FRAME_OK_REG(ENET)
+#define ENET_IEEE_R_CRC                          ENET_IEEE_R_CRC_REG(ENET)
+#define ENET_IEEE_R_ALIGN                        ENET_IEEE_R_ALIGN_REG(ENET)
+#define ENET_IEEE_R_MACERR                       ENET_IEEE_R_MACERR_REG(ENET)
+#define ENET_IEEE_R_FDXFC                        ENET_IEEE_R_FDXFC_REG(ENET)
+#define ENET_IEEE_R_OCTETS_OK                    ENET_IEEE_R_OCTETS_OK_REG(ENET)
+#define ENET_ATCR                                ENET_ATCR_REG(ENET)
+#define ENET_ATVR                                ENET_ATVR_REG(ENET)
+#define ENET_ATOFF                               ENET_ATOFF_REG(ENET)
+#define ENET_ATPER                               ENET_ATPER_REG(ENET)
+#define ENET_ATCOR                               ENET_ATCOR_REG(ENET)
+#define ENET_ATINC                               ENET_ATINC_REG(ENET)
+#define ENET_ATSTMP                              ENET_ATSTMP_REG(ENET)
+#define ENET_TGSR                                ENET_TGSR_REG(ENET)
+#define ENET_TCSR0                               ENET_TCSR_REG(ENET,0)
+#define ENET_TCCR0                               ENET_TCCR_REG(ENET,0)
+#define ENET_TCSR1                               ENET_TCSR_REG(ENET,1)
+#define ENET_TCCR1                               ENET_TCCR_REG(ENET,1)
+#define ENET_TCSR2                               ENET_TCSR_REG(ENET,2)
+#define ENET_TCCR2                               ENET_TCCR_REG(ENET,2)
+#define ENET_TCSR3                               ENET_TCSR_REG(ENET,3)
+#define ENET_TCCR3                               ENET_TCCR_REG(ENET,3)
+
+/* ENET - Register array accessors */
+#define ENET_TCSR(index)                         ENET_TCSR_REG(ENET,index)
+#define ENET_TCCR(index)                         ENET_TCCR_REG(ENET,index)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
+} EWM_Type, *EWM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register accessors */
+#define EWM_CTRL_REG(base)                       ((base)->CTRL)
+#define EWM_SERV_REG(base)                       ((base)->SERV)
+#define EWM_CMPL_REG(base)                       ((base)->CMPL)
+#define EWM_CMPH_REG(base)                       ((base)->CMPH)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK                      0x1u
+#define EWM_CTRL_EWMEN_SHIFT                     0
+#define EWM_CTRL_EWMEN_WIDTH                     1
+#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK                      0x2u
+#define EWM_CTRL_ASSIN_SHIFT                     1
+#define EWM_CTRL_ASSIN_WIDTH                     1
+#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK                       0x4u
+#define EWM_CTRL_INEN_SHIFT                      2
+#define EWM_CTRL_INEN_WIDTH                      1
+#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK                      0x8u
+#define EWM_CTRL_INTEN_SHIFT                     3
+#define EWM_CTRL_INTEN_WIDTH                     1
+#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK                    0xFFu
+#define EWM_SERV_SERVICE_SHIFT                   0
+#define EWM_SERV_SERVICE_WIDTH                   8
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK                   0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT                  0
+#define EWM_CMPL_COMPAREL_WIDTH                  8
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK                   0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT                  0
+#define EWM_CMPH_COMPAREH_WIDTH                  8
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE                                 (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM                                      ((EWM_Type *)EWM_BASE)
+#define EWM_BASE_PTR                             (EWM)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS                           { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS                            { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS                                 { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register instance definitions */
+/* EWM */
+#define EWM_CTRL                                 EWM_CTRL_REG(EWM)
+#define EWM_SERV                                 EWM_SERV_REG(EWM)
+#define EWM_CMPL                                 EWM_CMPL_REG(EWM)
+#define EWM_CMPH                                 EWM_CMPH_REG(EWM)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0xC */
+    __IO uint32_t CSAR;                              /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+    __IO uint32_t CSMR;                              /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+    __IO uint32_t CSCR;                              /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+  } CS[6];
+       uint8_t RESERVED_0[24];
+  __IO uint32_t CSPMCR;                            /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type, *FB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register accessors */
+#define FB_CSAR_REG(base,index)                  ((base)->CS[index].CSAR)
+#define FB_CSAR_COUNT                            6
+#define FB_CSMR_REG(base,index)                  ((base)->CS[index].CSMR)
+#define FB_CSMR_COUNT                            6
+#define FB_CSCR_REG(base,index)                  ((base)->CS[index].CSCR)
+#define FB_CSCR_COUNT                            6
+#define FB_CSPMCR_REG(base)                      ((base)->CSPMCR)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK                          0xFFFF0000u
+#define FB_CSAR_BA_SHIFT                         16
+#define FB_CSAR_BA_WIDTH                         16
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
+/* CSMR Bit Fields */
+#define FB_CSMR_V_MASK                           0x1u
+#define FB_CSMR_V_SHIFT                          0
+#define FB_CSMR_V_WIDTH                          1
+#define FB_CSMR_V(x)                             (((uint32_t)(((uint32_t)(x))<<FB_CSMR_V_SHIFT))&FB_CSMR_V_MASK)
+#define FB_CSMR_WP_MASK                          0x100u
+#define FB_CSMR_WP_SHIFT                         8
+#define FB_CSMR_WP_WIDTH                         1
+#define FB_CSMR_WP(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSMR_WP_SHIFT))&FB_CSMR_WP_MASK)
+#define FB_CSMR_BAM_MASK                         0xFFFF0000u
+#define FB_CSMR_BAM_SHIFT                        16
+#define FB_CSMR_BAM_WIDTH                        16
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
+/* CSCR Bit Fields */
+#define FB_CSCR_BSTW_MASK                        0x8u
+#define FB_CSCR_BSTW_SHIFT                       3
+#define FB_CSCR_BSTW_WIDTH                       1
+#define FB_CSCR_BSTW(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTW_SHIFT))&FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTR_MASK                        0x10u
+#define FB_CSCR_BSTR_SHIFT                       4
+#define FB_CSCR_BSTR_WIDTH                       1
+#define FB_CSCR_BSTR(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTR_SHIFT))&FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BEM_MASK                         0x20u
+#define FB_CSCR_BEM_SHIFT                        5
+#define FB_CSCR_BEM_WIDTH                        1
+#define FB_CSCR_BEM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BEM_SHIFT))&FB_CSCR_BEM_MASK)
+#define FB_CSCR_PS_MASK                          0xC0u
+#define FB_CSCR_PS_SHIFT                         6
+#define FB_CSCR_PS_WIDTH                         2
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK                          0x100u
+#define FB_CSCR_AA_SHIFT                         8
+#define FB_CSCR_AA_WIDTH                         1
+#define FB_CSCR_AA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_AA_SHIFT))&FB_CSCR_AA_MASK)
+#define FB_CSCR_BLS_MASK                         0x200u
+#define FB_CSCR_BLS_SHIFT                        9
+#define FB_CSCR_BLS_WIDTH                        1
+#define FB_CSCR_BLS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BLS_SHIFT))&FB_CSCR_BLS_MASK)
+#define FB_CSCR_WS_MASK                          0xFC00u
+#define FB_CSCR_WS_SHIFT                         10
+#define FB_CSCR_WS_WIDTH                         6
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        0x30000u
+#define FB_CSCR_WRAH_SHIFT                       16
+#define FB_CSCR_WRAH_WIDTH                       2
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        0xC0000u
+#define FB_CSCR_RDAH_SHIFT                       18
+#define FB_CSCR_RDAH_WIDTH                       2
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        0x300000u
+#define FB_CSCR_ASET_SHIFT                       20
+#define FB_CSCR_ASET_WIDTH                       2
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK                        0x400000u
+#define FB_CSCR_EXTS_SHIFT                       22
+#define FB_CSCR_EXTS_WIDTH                       1
+#define FB_CSCR_EXTS(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_EXTS_SHIFT))&FB_CSCR_EXTS_MASK)
+#define FB_CSCR_SWSEN_MASK                       0x800000u
+#define FB_CSCR_SWSEN_SHIFT                      23
+#define FB_CSCR_SWSEN_WIDTH                      1
+#define FB_CSCR_SWSEN(x)                         (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWSEN_SHIFT))&FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWS_MASK                         0xFC000000u
+#define FB_CSCR_SWS_SHIFT                        26
+#define FB_CSCR_SWS_WIDTH                        6
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
+/* CSPMCR Bit Fields */
+#define FB_CSPMCR_GROUP5_MASK                    0xF000u
+#define FB_CSPMCR_GROUP5_SHIFT                   12
+#define FB_CSPMCR_GROUP5_WIDTH                   4
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    0xF0000u
+#define FB_CSPMCR_GROUP4_SHIFT                   16
+#define FB_CSPMCR_GROUP4_WIDTH                   4
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    0xF00000u
+#define FB_CSPMCR_GROUP3_SHIFT                   20
+#define FB_CSPMCR_GROUP3_WIDTH                   4
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    0xF000000u
+#define FB_CSPMCR_GROUP2_SHIFT                   24
+#define FB_CSPMCR_GROUP2_WIDTH                   4
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    0xF0000000u
+#define FB_CSPMCR_GROUP1_SHIFT                   28
+#define FB_CSPMCR_GROUP1_WIDTH                   4
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE                                  (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB                                       ((FB_Type *)FB_BASE)
+#define FB_BASE_PTR                              (FB)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS                            { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS                             { FB }
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register instance definitions */
+/* FB */
+#define FB_CSAR0                                 FB_CSAR_REG(FB,0)
+#define FB_CSMR0                                 FB_CSMR_REG(FB,0)
+#define FB_CSCR0                                 FB_CSCR_REG(FB,0)
+#define FB_CSAR1                                 FB_CSAR_REG(FB,1)
+#define FB_CSMR1                                 FB_CSMR_REG(FB,1)
+#define FB_CSCR1                                 FB_CSCR_REG(FB,1)
+#define FB_CSAR2                                 FB_CSAR_REG(FB,2)
+#define FB_CSMR2                                 FB_CSMR_REG(FB,2)
+#define FB_CSCR2                                 FB_CSCR_REG(FB,2)
+#define FB_CSAR3                                 FB_CSAR_REG(FB,3)
+#define FB_CSMR3                                 FB_CSMR_REG(FB,3)
+#define FB_CSCR3                                 FB_CSCR_REG(FB,3)
+#define FB_CSAR4                                 FB_CSAR_REG(FB,4)
+#define FB_CSMR4                                 FB_CSMR_REG(FB,4)
+#define FB_CSCR4                                 FB_CSCR_REG(FB,4)
+#define FB_CSAR5                                 FB_CSAR_REG(FB,5)
+#define FB_CSMR5                                 FB_CSMR_REG(FB,5)
+#define FB_CSCR5                                 FB_CSCR_REG(FB,5)
+#define FB_CSPMCR                                FB_CSPMCR_REG(FB)
+
+/* FB - Register array accessors */
+#define FB_CSAR(index)                           FB_CSAR_REG(FB,index)
+#define FB_CSMR(index)                           FB_CSMR_REG(FB,index)
+#define FB_CSCR(index)                           FB_CSCR_REG(FB,index)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PFAPR;                             /**< Flash Access Protection Register, offset: 0x0 */
+  __IO uint32_t PFB0CR;                            /**< Flash Bank 0 Control Register, offset: 0x4 */
+  __IO uint32_t PFB1CR;                            /**< Flash Bank 1 Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[244];
+  __IO uint32_t TAGVDW0S[4];                       /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+  __IO uint32_t TAGVDW1S[4];                       /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
+  __IO uint32_t TAGVDW2S[4];                       /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+  __IO uint32_t TAGVDW3S[4];                       /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
+       uint8_t RESERVED_1[192];
+  struct {                                         /* offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_U;                            /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_L;                            /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
+  } SET[4][4];
+} FMC_Type, *FMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register accessors */
+#define FMC_PFAPR_REG(base)                      ((base)->PFAPR)
+#define FMC_PFB0CR_REG(base)                     ((base)->PFB0CR)
+#define FMC_PFB1CR_REG(base)                     ((base)->PFB1CR)
+#define FMC_TAGVDW0S_REG(base,index)             ((base)->TAGVDW0S[index])
+#define FMC_TAGVDW0S_COUNT                       4
+#define FMC_TAGVDW1S_REG(base,index)             ((base)->TAGVDW1S[index])
+#define FMC_TAGVDW1S_COUNT                       4
+#define FMC_TAGVDW2S_REG(base,index)             ((base)->TAGVDW2S[index])
+#define FMC_TAGVDW2S_COUNT                       4
+#define FMC_TAGVDW3S_REG(base,index)             ((base)->TAGVDW3S[index])
+#define FMC_TAGVDW3S_COUNT                       4
+#define FMC_DATA_U_REG(base,index,index2)        ((base)->SET[index][index2].DATA_U)
+#define FMC_DATA_U_COUNT                         4
+#define FMC_DATA_U_COUNT2                        4
+#define FMC_DATA_L_REG(base,index,index2)        ((base)->SET[index][index2].DATA_L)
+#define FMC_DATA_L_COUNT                         4
+#define FMC_DATA_L_COUNT2                        4
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK                      0x3u
+#define FMC_PFAPR_M0AP_SHIFT                     0
+#define FMC_PFAPR_M0AP_WIDTH                     2
+#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK                      0xCu
+#define FMC_PFAPR_M1AP_SHIFT                     2
+#define FMC_PFAPR_M1AP_WIDTH                     2
+#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK                      0x30u
+#define FMC_PFAPR_M2AP_SHIFT                     4
+#define FMC_PFAPR_M2AP_WIDTH                     2
+#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK                      0xC0u
+#define FMC_PFAPR_M3AP_SHIFT                     6
+#define FMC_PFAPR_M3AP_WIDTH                     2
+#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK                      0x300u
+#define FMC_PFAPR_M4AP_SHIFT                     8
+#define FMC_PFAPR_M4AP_WIDTH                     2
+#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK                      0xC00u
+#define FMC_PFAPR_M5AP_SHIFT                     10
+#define FMC_PFAPR_M5AP_WIDTH                     2
+#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK                      0x3000u
+#define FMC_PFAPR_M6AP_SHIFT                     12
+#define FMC_PFAPR_M6AP_WIDTH                     2
+#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK                      0xC000u
+#define FMC_PFAPR_M7AP_SHIFT                     14
+#define FMC_PFAPR_M7AP_WIDTH                     2
+#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK                     0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT                    16
+#define FMC_PFAPR_M0PFD_WIDTH                    1
+#define FMC_PFAPR_M0PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0PFD_SHIFT))&FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK                     0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT                    17
+#define FMC_PFAPR_M1PFD_WIDTH                    1
+#define FMC_PFAPR_M1PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1PFD_SHIFT))&FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK                     0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT                    18
+#define FMC_PFAPR_M2PFD_WIDTH                    1
+#define FMC_PFAPR_M2PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2PFD_SHIFT))&FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK                     0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT                    19
+#define FMC_PFAPR_M3PFD_WIDTH                    1
+#define FMC_PFAPR_M3PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3PFD_SHIFT))&FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M4PFD_MASK                     0x100000u
+#define FMC_PFAPR_M4PFD_SHIFT                    20
+#define FMC_PFAPR_M4PFD_WIDTH                    1
+#define FMC_PFAPR_M4PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4PFD_SHIFT))&FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M5PFD_MASK                     0x200000u
+#define FMC_PFAPR_M5PFD_SHIFT                    21
+#define FMC_PFAPR_M5PFD_WIDTH                    1
+#define FMC_PFAPR_M5PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5PFD_SHIFT))&FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M6PFD_MASK                     0x400000u
+#define FMC_PFAPR_M6PFD_SHIFT                    22
+#define FMC_PFAPR_M6PFD_WIDTH                    1
+#define FMC_PFAPR_M6PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6PFD_SHIFT))&FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M7PFD_MASK                     0x800000u
+#define FMC_PFAPR_M7PFD_SHIFT                    23
+#define FMC_PFAPR_M7PFD_WIDTH                    1
+#define FMC_PFAPR_M7PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7PFD_SHIFT))&FMC_PFAPR_M7PFD_MASK)
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK                   0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT                  0
+#define FMC_PFB0CR_B0SEBE_WIDTH                  1
+#define FMC_PFB0CR_B0SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0SEBE_SHIFT))&FMC_PFB0CR_B0SEBE_MASK)
+#define FMC_PFB0CR_B0IPE_MASK                    0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT                   1
+#define FMC_PFB0CR_B0IPE_WIDTH                   1
+#define FMC_PFB0CR_B0IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0IPE_SHIFT))&FMC_PFB0CR_B0IPE_MASK)
+#define FMC_PFB0CR_B0DPE_MASK                    0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT                   2
+#define FMC_PFB0CR_B0DPE_WIDTH                   1
+#define FMC_PFB0CR_B0DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DPE_SHIFT))&FMC_PFB0CR_B0DPE_MASK)
+#define FMC_PFB0CR_B0ICE_MASK                    0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT                   3
+#define FMC_PFB0CR_B0ICE_WIDTH                   1
+#define FMC_PFB0CR_B0ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0ICE_SHIFT))&FMC_PFB0CR_B0ICE_MASK)
+#define FMC_PFB0CR_B0DCE_MASK                    0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT                   4
+#define FMC_PFB0CR_B0DCE_WIDTH                   1
+#define FMC_PFB0CR_B0DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DCE_SHIFT))&FMC_PFB0CR_B0DCE_MASK)
+#define FMC_PFB0CR_CRC_MASK                      0xE0u
+#define FMC_PFB0CR_CRC_SHIFT                     5
+#define FMC_PFB0CR_CRC_WIDTH                     3
+#define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK                     0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT                    17
+#define FMC_PFB0CR_B0MW_WIDTH                    2
+#define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK                  0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT                 19
+#define FMC_PFB0CR_S_B_INV_WIDTH                 1
+#define FMC_PFB0CR_S_B_INV(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_S_B_INV_SHIFT))&FMC_PFB0CR_S_B_INV_MASK)
+#define FMC_PFB0CR_CINV_WAY_MASK                 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT                20
+#define FMC_PFB0CR_CINV_WAY_WIDTH                4
+#define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK                 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT                24
+#define FMC_PFB0CR_CLCK_WAY_WIDTH                4
+#define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK                   0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT                  28
+#define FMC_PFB0CR_B0RWSC_WIDTH                  4
+#define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* PFB1CR Bit Fields */
+#define FMC_PFB1CR_B1SEBE_MASK                   0x1u
+#define FMC_PFB1CR_B1SEBE_SHIFT                  0
+#define FMC_PFB1CR_B1SEBE_WIDTH                  1
+#define FMC_PFB1CR_B1SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1SEBE_SHIFT))&FMC_PFB1CR_B1SEBE_MASK)
+#define FMC_PFB1CR_B1IPE_MASK                    0x2u
+#define FMC_PFB1CR_B1IPE_SHIFT                   1
+#define FMC_PFB1CR_B1IPE_WIDTH                   1
+#define FMC_PFB1CR_B1IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1IPE_SHIFT))&FMC_PFB1CR_B1IPE_MASK)
+#define FMC_PFB1CR_B1DPE_MASK                    0x4u
+#define FMC_PFB1CR_B1DPE_SHIFT                   2
+#define FMC_PFB1CR_B1DPE_WIDTH                   1
+#define FMC_PFB1CR_B1DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DPE_SHIFT))&FMC_PFB1CR_B1DPE_MASK)
+#define FMC_PFB1CR_B1ICE_MASK                    0x8u
+#define FMC_PFB1CR_B1ICE_SHIFT                   3
+#define FMC_PFB1CR_B1ICE_WIDTH                   1
+#define FMC_PFB1CR_B1ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1ICE_SHIFT))&FMC_PFB1CR_B1ICE_MASK)
+#define FMC_PFB1CR_B1DCE_MASK                    0x10u
+#define FMC_PFB1CR_B1DCE_SHIFT                   4
+#define FMC_PFB1CR_B1DCE_WIDTH                   1
+#define FMC_PFB1CR_B1DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DCE_SHIFT))&FMC_PFB1CR_B1DCE_MASK)
+#define FMC_PFB1CR_B1MW_MASK                     0x60000u
+#define FMC_PFB1CR_B1MW_SHIFT                    17
+#define FMC_PFB1CR_B1MW_WIDTH                    2
+#define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK                   0xF0000000u
+#define FMC_PFB1CR_B1RWSC_SHIFT                  28
+#define FMC_PFB1CR_B1RWSC_WIDTH                  4
+#define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
+/* TAGVDW0S Bit Fields */
+#define FMC_TAGVDW0S_valid_MASK                  0x1u
+#define FMC_TAGVDW0S_valid_SHIFT                 0
+#define FMC_TAGVDW0S_valid_WIDTH                 1
+#define FMC_TAGVDW0S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_valid_SHIFT))&FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW0S_tag_SHIFT                   5
+#define FMC_TAGVDW0S_tag_WIDTH                   14
+#define FMC_TAGVDW0S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
+/* TAGVDW1S Bit Fields */
+#define FMC_TAGVDW1S_valid_MASK                  0x1u
+#define FMC_TAGVDW1S_valid_SHIFT                 0
+#define FMC_TAGVDW1S_valid_WIDTH                 1
+#define FMC_TAGVDW1S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_valid_SHIFT))&FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW1S_tag_SHIFT                   5
+#define FMC_TAGVDW1S_tag_WIDTH                   14
+#define FMC_TAGVDW1S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
+/* TAGVDW2S Bit Fields */
+#define FMC_TAGVDW2S_valid_MASK                  0x1u
+#define FMC_TAGVDW2S_valid_SHIFT                 0
+#define FMC_TAGVDW2S_valid_WIDTH                 1
+#define FMC_TAGVDW2S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_valid_SHIFT))&FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW2S_tag_SHIFT                   5
+#define FMC_TAGVDW2S_tag_WIDTH                   14
+#define FMC_TAGVDW2S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
+/* TAGVDW3S Bit Fields */
+#define FMC_TAGVDW3S_valid_MASK                  0x1u
+#define FMC_TAGVDW3S_valid_SHIFT                 0
+#define FMC_TAGVDW3S_valid_WIDTH                 1
+#define FMC_TAGVDW3S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_valid_SHIFT))&FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW3S_tag_SHIFT                   5
+#define FMC_TAGVDW3S_tag_WIDTH                   14
+#define FMC_TAGVDW3S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
+/* DATA_U Bit Fields */
+#define FMC_DATA_U_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_U_data_SHIFT                    0
+#define FMC_DATA_U_data_WIDTH                    32
+#define FMC_DATA_U_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
+/* DATA_L Bit Fields */
+#define FMC_DATA_L_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_L_data_SHIFT                    0
+#define FMC_DATA_L_data_WIDTH                    32
+#define FMC_DATA_L_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE                                 (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC                                      ((FMC_Type *)FMC_BASE)
+#define FMC_BASE_PTR                             (FMC)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS                           { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS                            { FMC }
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register instance definitions */
+/* FMC */
+#define FMC_PFAPR                                FMC_PFAPR_REG(FMC)
+#define FMC_PFB0CR                               FMC_PFB0CR_REG(FMC)
+#define FMC_PFB1CR                               FMC_PFB1CR_REG(FMC)
+#define FMC_TAGVDW0S0                            FMC_TAGVDW0S_REG(FMC,0)
+#define FMC_TAGVDW0S1                            FMC_TAGVDW0S_REG(FMC,1)
+#define FMC_TAGVDW0S2                            FMC_TAGVDW0S_REG(FMC,2)
+#define FMC_TAGVDW0S3                            FMC_TAGVDW0S_REG(FMC,3)
+#define FMC_TAGVDW1S0                            FMC_TAGVDW1S_REG(FMC,0)
+#define FMC_TAGVDW1S1                            FMC_TAGVDW1S_REG(FMC,1)
+#define FMC_TAGVDW1S2                            FMC_TAGVDW1S_REG(FMC,2)
+#define FMC_TAGVDW1S3                            FMC_TAGVDW1S_REG(FMC,3)
+#define FMC_TAGVDW2S0                            FMC_TAGVDW2S_REG(FMC,0)
+#define FMC_TAGVDW2S1                            FMC_TAGVDW2S_REG(FMC,1)
+#define FMC_TAGVDW2S2                            FMC_TAGVDW2S_REG(FMC,2)
+#define FMC_TAGVDW2S3                            FMC_TAGVDW2S_REG(FMC,3)
+#define FMC_TAGVDW3S0                            FMC_TAGVDW3S_REG(FMC,0)
+#define FMC_TAGVDW3S1                            FMC_TAGVDW3S_REG(FMC,1)
+#define FMC_TAGVDW3S2                            FMC_TAGVDW3S_REG(FMC,2)
+#define FMC_TAGVDW3S3                            FMC_TAGVDW3S_REG(FMC,3)
+#define FMC_DATAW0S0U                            FMC_DATA_U_REG(FMC,0,0)
+#define FMC_DATAW0S0L                            FMC_DATA_L_REG(FMC,0,0)
+#define FMC_DATAW0S1U                            FMC_DATA_U_REG(FMC,0,1)
+#define FMC_DATAW0S1L                            FMC_DATA_L_REG(FMC,0,1)
+#define FMC_DATAW0S2U                            FMC_DATA_U_REG(FMC,0,2)
+#define FMC_DATAW0S2L                            FMC_DATA_L_REG(FMC,0,2)
+#define FMC_DATAW0S3U                            FMC_DATA_U_REG(FMC,0,3)
+#define FMC_DATAW0S3L                            FMC_DATA_L_REG(FMC,0,3)
+#define FMC_DATAW1S0U                            FMC_DATA_U_REG(FMC,1,0)
+#define FMC_DATAW1S0L                            FMC_DATA_L_REG(FMC,1,0)
+#define FMC_DATAW1S1U                            FMC_DATA_U_REG(FMC,1,1)
+#define FMC_DATAW1S1L                            FMC_DATA_L_REG(FMC,1,1)
+#define FMC_DATAW1S2U                            FMC_DATA_U_REG(FMC,1,2)
+#define FMC_DATAW1S2L                            FMC_DATA_L_REG(FMC,1,2)
+#define FMC_DATAW1S3U                            FMC_DATA_U_REG(FMC,1,3)
+#define FMC_DATAW1S3L                            FMC_DATA_L_REG(FMC,1,3)
+#define FMC_DATAW2S0U                            FMC_DATA_U_REG(FMC,2,0)
+#define FMC_DATAW2S0L                            FMC_DATA_L_REG(FMC,2,0)
+#define FMC_DATAW2S1U                            FMC_DATA_U_REG(FMC,2,1)
+#define FMC_DATAW2S1L                            FMC_DATA_L_REG(FMC,2,1)
+#define FMC_DATAW2S2U                            FMC_DATA_U_REG(FMC,2,2)
+#define FMC_DATAW2S2L                            FMC_DATA_L_REG(FMC,2,2)
+#define FMC_DATAW2S3U                            FMC_DATA_U_REG(FMC,2,3)
+#define FMC_DATAW2S3L                            FMC_DATA_L_REG(FMC,2,3)
+#define FMC_DATAW3S0U                            FMC_DATA_U_REG(FMC,3,0)
+#define FMC_DATAW3S0L                            FMC_DATA_L_REG(FMC,3,0)
+#define FMC_DATAW3S1U                            FMC_DATA_U_REG(FMC,3,1)
+#define FMC_DATAW3S1L                            FMC_DATA_L_REG(FMC,3,1)
+#define FMC_DATAW3S2U                            FMC_DATA_U_REG(FMC,3,2)
+#define FMC_DATAW3S2L                            FMC_DATA_L_REG(FMC,3,2)
+#define FMC_DATAW3S3U                            FMC_DATA_U_REG(FMC,3,3)
+#define FMC_DATAW3S3L                            FMC_DATA_L_REG(FMC,3,3)
+
+/* FMC - Register array accessors */
+#define FMC_TAGVDW0S(index)                      FMC_TAGVDW0S_REG(FMC,index)
+#define FMC_TAGVDW1S(index)                      FMC_TAGVDW1S_REG(FMC,index)
+#define FMC_TAGVDW2S(index)                      FMC_TAGVDW2S_REG(FMC,index)
+#define FMC_TAGVDW3S(index)                      FMC_TAGVDW3S_REG(FMC,index)
+#define FMC_DATA_U(index,index2)                 FMC_DATA_U_REG(FMC,index,index2)
+#define FMC_DATA_L(index,index2)                 FMC_DATA_L_REG(FMC,index,index2)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t FEPROT;                             /**< EEPROM Protection Register, offset: 0x16 */
+  __IO uint8_t FDPROT;                             /**< Data Flash Protection Register, offset: 0x17 */
+} FTFE_Type, *FTFE_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register accessors */
+#define FTFE_FSTAT_REG(base)                     ((base)->FSTAT)
+#define FTFE_FCNFG_REG(base)                     ((base)->FCNFG)
+#define FTFE_FSEC_REG(base)                      ((base)->FSEC)
+#define FTFE_FOPT_REG(base)                      ((base)->FOPT)
+#define FTFE_FCCOB3_REG(base)                    ((base)->FCCOB3)
+#define FTFE_FCCOB2_REG(base)                    ((base)->FCCOB2)
+#define FTFE_FCCOB1_REG(base)                    ((base)->FCCOB1)
+#define FTFE_FCCOB0_REG(base)                    ((base)->FCCOB0)
+#define FTFE_FCCOB7_REG(base)                    ((base)->FCCOB7)
+#define FTFE_FCCOB6_REG(base)                    ((base)->FCCOB6)
+#define FTFE_FCCOB5_REG(base)                    ((base)->FCCOB5)
+#define FTFE_FCCOB4_REG(base)                    ((base)->FCCOB4)
+#define FTFE_FCCOBB_REG(base)                    ((base)->FCCOBB)
+#define FTFE_FCCOBA_REG(base)                    ((base)->FCCOBA)
+#define FTFE_FCCOB9_REG(base)                    ((base)->FCCOB9)
+#define FTFE_FCCOB8_REG(base)                    ((base)->FCCOB8)
+#define FTFE_FPROT3_REG(base)                    ((base)->FPROT3)
+#define FTFE_FPROT2_REG(base)                    ((base)->FPROT2)
+#define FTFE_FPROT1_REG(base)                    ((base)->FPROT1)
+#define FTFE_FPROT0_REG(base)                    ((base)->FPROT0)
+#define FTFE_FEPROT_REG(base)                    ((base)->FEPROT)
+#define FTFE_FDPROT_REG(base)                    ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFE_FSTAT_MGSTAT0_MASK                  0x1u
+#define FTFE_FSTAT_MGSTAT0_SHIFT                 0
+#define FTFE_FSTAT_MGSTAT0_WIDTH                 1
+#define FTFE_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_MGSTAT0_SHIFT))&FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_FPVIOL_MASK                   0x10u
+#define FTFE_FSTAT_FPVIOL_SHIFT                  4
+#define FTFE_FSTAT_FPVIOL_WIDTH                  1
+#define FTFE_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_FPVIOL_SHIFT))&FTFE_FSTAT_FPVIOL_MASK)
+#define FTFE_FSTAT_ACCERR_MASK                   0x20u
+#define FTFE_FSTAT_ACCERR_SHIFT                  5
+#define FTFE_FSTAT_ACCERR_WIDTH                  1
+#define FTFE_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_ACCERR_SHIFT))&FTFE_FSTAT_ACCERR_MASK)
+#define FTFE_FSTAT_RDCOLERR_MASK                 0x40u
+#define FTFE_FSTAT_RDCOLERR_SHIFT                6
+#define FTFE_FSTAT_RDCOLERR_WIDTH                1
+#define FTFE_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_RDCOLERR_SHIFT))&FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFE_FSTAT_CCIF_MASK                     0x80u
+#define FTFE_FSTAT_CCIF_SHIFT                    7
+#define FTFE_FSTAT_CCIF_WIDTH                    1
+#define FTFE_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_CCIF_SHIFT))&FTFE_FSTAT_CCIF_MASK)
+/* FCNFG Bit Fields */
+#define FTFE_FCNFG_EEERDY_MASK                   0x1u
+#define FTFE_FCNFG_EEERDY_SHIFT                  0
+#define FTFE_FCNFG_EEERDY_WIDTH                  1
+#define FTFE_FCNFG_EEERDY(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_EEERDY_SHIFT))&FTFE_FCNFG_EEERDY_MASK)
+#define FTFE_FCNFG_RAMRDY_MASK                   0x2u
+#define FTFE_FCNFG_RAMRDY_SHIFT                  1
+#define FTFE_FCNFG_RAMRDY_WIDTH                  1
+#define FTFE_FCNFG_RAMRDY(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RAMRDY_SHIFT))&FTFE_FCNFG_RAMRDY_MASK)
+#define FTFE_FCNFG_PFLSH_MASK                    0x4u
+#define FTFE_FCNFG_PFLSH_SHIFT                   2
+#define FTFE_FCNFG_PFLSH_WIDTH                   1
+#define FTFE_FCNFG_PFLSH(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_PFLSH_SHIFT))&FTFE_FCNFG_PFLSH_MASK)
+#define FTFE_FCNFG_SWAP_MASK                     0x8u
+#define FTFE_FCNFG_SWAP_SHIFT                    3
+#define FTFE_FCNFG_SWAP_WIDTH                    1
+#define FTFE_FCNFG_SWAP(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_SWAP_SHIFT))&FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_ERSSUSP_MASK                  0x10u
+#define FTFE_FCNFG_ERSSUSP_SHIFT                 4
+#define FTFE_FCNFG_ERSSUSP_WIDTH                 1
+#define FTFE_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSSUSP_SHIFT))&FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSAREQ_MASK                  0x20u
+#define FTFE_FCNFG_ERSAREQ_SHIFT                 5
+#define FTFE_FCNFG_ERSAREQ_WIDTH                 1
+#define FTFE_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSAREQ_SHIFT))&FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_RDCOLLIE_MASK                 0x40u
+#define FTFE_FCNFG_RDCOLLIE_SHIFT                6
+#define FTFE_FCNFG_RDCOLLIE_WIDTH                1
+#define FTFE_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RDCOLLIE_SHIFT))&FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_CCIE_MASK                     0x80u
+#define FTFE_FCNFG_CCIE_SHIFT                    7
+#define FTFE_FCNFG_CCIE_WIDTH                    1
+#define FTFE_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_CCIE_SHIFT))&FTFE_FCNFG_CCIE_MASK)
+/* FSEC Bit Fields */
+#define FTFE_FSEC_SEC_MASK                       0x3u
+#define FTFE_FSEC_SEC_SHIFT                      0
+#define FTFE_FSEC_SEC_WIDTH                      2
+#define FTFE_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK                    0xCu
+#define FTFE_FSEC_FSLACC_SHIFT                   2
+#define FTFE_FSEC_FSLACC_WIDTH                   2
+#define FTFE_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK                      0x30u
+#define FTFE_FSEC_MEEN_SHIFT                     4
+#define FTFE_FSEC_MEEN_WIDTH                     2
+#define FTFE_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK                     0xC0u
+#define FTFE_FSEC_KEYEN_SHIFT                    6
+#define FTFE_FSEC_KEYEN_WIDTH                    2
+#define FTFE_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFE_FOPT_OPT_MASK                       0xFFu
+#define FTFE_FOPT_OPT_SHIFT                      0
+#define FTFE_FOPT_OPT_WIDTH                      8
+#define FTFE_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFE_FCCOB3_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB3_CCOBn_SHIFT                  0
+#define FTFE_FCCOB3_CCOBn_WIDTH                  8
+#define FTFE_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFE_FCCOB2_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB2_CCOBn_SHIFT                  0
+#define FTFE_FCCOB2_CCOBn_WIDTH                  8
+#define FTFE_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFE_FCCOB1_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB1_CCOBn_SHIFT                  0
+#define FTFE_FCCOB1_CCOBn_WIDTH                  8
+#define FTFE_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFE_FCCOB0_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB0_CCOBn_SHIFT                  0
+#define FTFE_FCCOB0_CCOBn_WIDTH                  8
+#define FTFE_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFE_FCCOB7_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB7_CCOBn_SHIFT                  0
+#define FTFE_FCCOB7_CCOBn_WIDTH                  8
+#define FTFE_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFE_FCCOB6_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB6_CCOBn_SHIFT                  0
+#define FTFE_FCCOB6_CCOBn_WIDTH                  8
+#define FTFE_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFE_FCCOB5_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB5_CCOBn_SHIFT                  0
+#define FTFE_FCCOB5_CCOBn_WIDTH                  8
+#define FTFE_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFE_FCCOB4_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB4_CCOBn_SHIFT                  0
+#define FTFE_FCCOB4_CCOBn_WIDTH                  8
+#define FTFE_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFE_FCCOBB_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBB_CCOBn_SHIFT                  0
+#define FTFE_FCCOBB_CCOBn_WIDTH                  8
+#define FTFE_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFE_FCCOBA_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBA_CCOBn_SHIFT                  0
+#define FTFE_FCCOBA_CCOBn_WIDTH                  8
+#define FTFE_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFE_FCCOB9_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB9_CCOBn_SHIFT                  0
+#define FTFE_FCCOB9_CCOBn_WIDTH                  8
+#define FTFE_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFE_FCCOB8_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB8_CCOBn_SHIFT                  0
+#define FTFE_FCCOB8_CCOBn_WIDTH                  8
+#define FTFE_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFE_FPROT3_PROT_MASK                    0xFFu
+#define FTFE_FPROT3_PROT_SHIFT                   0
+#define FTFE_FPROT3_PROT_WIDTH                   8
+#define FTFE_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFE_FPROT2_PROT_MASK                    0xFFu
+#define FTFE_FPROT2_PROT_SHIFT                   0
+#define FTFE_FPROT2_PROT_WIDTH                   8
+#define FTFE_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFE_FPROT1_PROT_MASK                    0xFFu
+#define FTFE_FPROT1_PROT_SHIFT                   0
+#define FTFE_FPROT1_PROT_WIDTH                   8
+#define FTFE_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFE_FPROT0_PROT_MASK                    0xFFu
+#define FTFE_FPROT0_PROT_SHIFT                   0
+#define FTFE_FPROT0_PROT_WIDTH                   8
+#define FTFE_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFE_FEPROT_EPROT_MASK                   0xFFu
+#define FTFE_FEPROT_EPROT_SHIFT                  0
+#define FTFE_FEPROT_EPROT_WIDTH                  8
+#define FTFE_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFE_FDPROT_DPROT_MASK                   0xFFu
+#define FTFE_FDPROT_DPROT_SHIFT                  0
+#define FTFE_FDPROT_DPROT_WIDTH                  8
+#define FTFE_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE                                (0x40020000u)
+/** Peripheral FTFE base pointer */
+#define FTFE                                     ((FTFE_Type *)FTFE_BASE)
+#define FTFE_BASE_PTR                            (FTFE)
+/** Array initializer of FTFE peripheral base addresses */
+#define FTFE_BASE_ADDRS                          { FTFE_BASE }
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASE_PTRS                           { FTFE }
+/** Interrupt vectors for the FTFE peripheral type */
+#define FTFE_COMMAND_COMPLETE_IRQS               { FTFE_IRQn }
+#define FTFE_READ_COLLISION_IRQS                 { Read_Collision_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register instance definitions */
+/* FTFE */
+#define FTFE_FSTAT                               FTFE_FSTAT_REG(FTFE)
+#define FTFE_FCNFG                               FTFE_FCNFG_REG(FTFE)
+#define FTFE_FSEC                                FTFE_FSEC_REG(FTFE)
+#define FTFE_FOPT                                FTFE_FOPT_REG(FTFE)
+#define FTFE_FCCOB3                              FTFE_FCCOB3_REG(FTFE)
+#define FTFE_FCCOB2                              FTFE_FCCOB2_REG(FTFE)
+#define FTFE_FCCOB1                              FTFE_FCCOB1_REG(FTFE)
+#define FTFE_FCCOB0                              FTFE_FCCOB0_REG(FTFE)
+#define FTFE_FCCOB7                              FTFE_FCCOB7_REG(FTFE)
+#define FTFE_FCCOB6                              FTFE_FCCOB6_REG(FTFE)
+#define FTFE_FCCOB5                              FTFE_FCCOB5_REG(FTFE)
+#define FTFE_FCCOB4                              FTFE_FCCOB4_REG(FTFE)
+#define FTFE_FCCOBB                              FTFE_FCCOBB_REG(FTFE)
+#define FTFE_FCCOBA                              FTFE_FCCOBA_REG(FTFE)
+#define FTFE_FCCOB9                              FTFE_FCCOB9_REG(FTFE)
+#define FTFE_FCCOB8                              FTFE_FCCOB8_REG(FTFE)
+#define FTFE_FPROT3                              FTFE_FPROT3_REG(FTFE)
+#define FTFE_FPROT2                              FTFE_FPROT2_REG(FTFE)
+#define FTFE_FPROT1                              FTFE_FPROT1_REG(FTFE)
+#define FTFE_FPROT0                              FTFE_FPROT0_REG(FTFE)
+#define FTFE_FEPROT                              FTFE_FEPROT_REG(FTFE)
+#define FTFE_FDPROT                              FTFE_FDPROT_REG(FTFE)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[8];
+  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
+  __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
+  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
+  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
+  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
+  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
+  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
+  __IO uint32_t DEADTIME;                          /**< Deadtime Insertion Control, offset: 0x68 */
+  __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
+  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
+  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
+  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
+  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+  __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
+  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
+  __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
+  __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
+  __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type, *FTM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register accessors */
+#define FTM_SC_REG(base)                         ((base)->SC)
+#define FTM_CNT_REG(base)                        ((base)->CNT)
+#define FTM_MOD_REG(base)                        ((base)->MOD)
+#define FTM_CnSC_REG(base,index)                 ((base)->CONTROLS[index].CnSC)
+#define FTM_CnSC_COUNT                           8
+#define FTM_CnV_REG(base,index)                  ((base)->CONTROLS[index].CnV)
+#define FTM_CnV_COUNT                            8
+#define FTM_CNTIN_REG(base)                      ((base)->CNTIN)
+#define FTM_STATUS_REG(base)                     ((base)->STATUS)
+#define FTM_MODE_REG(base)                       ((base)->MODE)
+#define FTM_SYNC_REG(base)                       ((base)->SYNC)
+#define FTM_OUTINIT_REG(base)                    ((base)->OUTINIT)
+#define FTM_OUTMASK_REG(base)                    ((base)->OUTMASK)
+#define FTM_COMBINE_REG(base)                    ((base)->COMBINE)
+#define FTM_DEADTIME_REG(base)                   ((base)->DEADTIME)
+#define FTM_EXTTRIG_REG(base)                    ((base)->EXTTRIG)
+#define FTM_POL_REG(base)                        ((base)->POL)
+#define FTM_FMS_REG(base)                        ((base)->FMS)
+#define FTM_FILTER_REG(base)                     ((base)->FILTER)
+#define FTM_FLTCTRL_REG(base)                    ((base)->FLTCTRL)
+#define FTM_QDCTRL_REG(base)                     ((base)->QDCTRL)
+#define FTM_CONF_REG(base)                       ((base)->CONF)
+#define FTM_FLTPOL_REG(base)                     ((base)->FLTPOL)
+#define FTM_SYNCONF_REG(base)                    ((base)->SYNCONF)
+#define FTM_INVCTRL_REG(base)                    ((base)->INVCTRL)
+#define FTM_SWOCTRL_REG(base)                    ((base)->SWOCTRL)
+#define FTM_PWMLOAD_REG(base)                    ((base)->PWMLOAD)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK                           0x7u
+#define FTM_SC_PS_SHIFT                          0
+#define FTM_SC_PS_WIDTH                          3
+#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK                         0x18u
+#define FTM_SC_CLKS_SHIFT                        3
+#define FTM_SC_CLKS_WIDTH                        2
+#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK                        0x20u
+#define FTM_SC_CPWMS_SHIFT                       5
+#define FTM_SC_CPWMS_WIDTH                       1
+#define FTM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK                         0x40u
+#define FTM_SC_TOIE_SHIFT                        6
+#define FTM_SC_TOIE_WIDTH                        1
+#define FTM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK                          0x80u
+#define FTM_SC_TOF_SHIFT                         7
+#define FTM_SC_TOF_WIDTH                         1
+#define FTM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK                       0xFFFFu
+#define FTM_CNT_COUNT_SHIFT                      0
+#define FTM_CNT_COUNT_WIDTH                      16
+#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK                         0xFFFFu
+#define FTM_MOD_MOD_SHIFT                        0
+#define FTM_MOD_MOD_WIDTH                        16
+#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK                        0x1u
+#define FTM_CnSC_DMA_SHIFT                       0
+#define FTM_CnSC_DMA_WIDTH                       1
+#define FTM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ELSA_MASK                       0x4u
+#define FTM_CnSC_ELSA_SHIFT                      2
+#define FTM_CnSC_ELSA_WIDTH                      1
+#define FTM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK                       0x8u
+#define FTM_CnSC_ELSB_SHIFT                      3
+#define FTM_CnSC_ELSB_WIDTH                      1
+#define FTM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK                        0x10u
+#define FTM_CnSC_MSA_SHIFT                       4
+#define FTM_CnSC_MSA_WIDTH                       1
+#define FTM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK                        0x20u
+#define FTM_CnSC_MSB_SHIFT                       5
+#define FTM_CnSC_MSB_WIDTH                       1
+#define FTM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK                       0x40u
+#define FTM_CnSC_CHIE_SHIFT                      6
+#define FTM_CnSC_CHIE_WIDTH                      1
+#define FTM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK                        0x80u
+#define FTM_CnSC_CHF_SHIFT                       7
+#define FTM_CnSC_CHF_WIDTH                       1
+#define FTM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK                         0xFFFFu
+#define FTM_CnV_VAL_SHIFT                        0
+#define FTM_CnV_VAL_WIDTH                        16
+#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK                      0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT                     0
+#define FTM_CNTIN_INIT_WIDTH                     16
+#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK                     0x1u
+#define FTM_STATUS_CH0F_SHIFT                    0
+#define FTM_STATUS_CH0F_WIDTH                    1
+#define FTM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK                     0x2u
+#define FTM_STATUS_CH1F_SHIFT                    1
+#define FTM_STATUS_CH1F_WIDTH                    1
+#define FTM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK                     0x4u
+#define FTM_STATUS_CH2F_SHIFT                    2
+#define FTM_STATUS_CH2F_WIDTH                    1
+#define FTM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK                     0x8u
+#define FTM_STATUS_CH3F_SHIFT                    3
+#define FTM_STATUS_CH3F_WIDTH                    1
+#define FTM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK                     0x10u
+#define FTM_STATUS_CH4F_SHIFT                    4
+#define FTM_STATUS_CH4F_WIDTH                    1
+#define FTM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK                     0x20u
+#define FTM_STATUS_CH5F_SHIFT                    5
+#define FTM_STATUS_CH5F_WIDTH                    1
+#define FTM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK                     0x40u
+#define FTM_STATUS_CH6F_SHIFT                    6
+#define FTM_STATUS_CH6F_WIDTH                    1
+#define FTM_STATUS_CH6F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK                     0x80u
+#define FTM_STATUS_CH7F_SHIFT                    7
+#define FTM_STATUS_CH7F_WIDTH                    1
+#define FTM_STATUS_CH7F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK                      0x1u
+#define FTM_MODE_FTMEN_SHIFT                     0
+#define FTM_MODE_FTMEN_WIDTH                     1
+#define FTM_MODE_FTMEN(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK                       0x2u
+#define FTM_MODE_INIT_SHIFT                      1
+#define FTM_MODE_INIT_WIDTH                      1
+#define FTM_MODE_INIT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK                      0x4u
+#define FTM_MODE_WPDIS_SHIFT                     2
+#define FTM_MODE_WPDIS_WIDTH                     1
+#define FTM_MODE_WPDIS(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK                    0x8u
+#define FTM_MODE_PWMSYNC_SHIFT                   3
+#define FTM_MODE_PWMSYNC_WIDTH                   1
+#define FTM_MODE_PWMSYNC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK                    0x10u
+#define FTM_MODE_CAPTEST_SHIFT                   4
+#define FTM_MODE_CAPTEST_WIDTH                   1
+#define FTM_MODE_CAPTEST(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK                     0x60u
+#define FTM_MODE_FAULTM_SHIFT                    5
+#define FTM_MODE_FAULTM_WIDTH                    2
+#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK                    0x80u
+#define FTM_MODE_FAULTIE_SHIFT                   7
+#define FTM_MODE_FAULTIE_WIDTH                   1
+#define FTM_MODE_FAULTIE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK                     0x1u
+#define FTM_SYNC_CNTMIN_SHIFT                    0
+#define FTM_SYNC_CNTMIN_WIDTH                    1
+#define FTM_SYNC_CNTMIN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK                     0x2u
+#define FTM_SYNC_CNTMAX_SHIFT                    1
+#define FTM_SYNC_CNTMAX_WIDTH                    1
+#define FTM_SYNC_CNTMAX(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK                     0x4u
+#define FTM_SYNC_REINIT_SHIFT                    2
+#define FTM_SYNC_REINIT_WIDTH                    1
+#define FTM_SYNC_REINIT(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK                    0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT                   3
+#define FTM_SYNC_SYNCHOM_WIDTH                   1
+#define FTM_SYNC_SYNCHOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK                      0x10u
+#define FTM_SYNC_TRIG0_SHIFT                     4
+#define FTM_SYNC_TRIG0_WIDTH                     1
+#define FTM_SYNC_TRIG0(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK                      0x20u
+#define FTM_SYNC_TRIG1_SHIFT                     5
+#define FTM_SYNC_TRIG1_WIDTH                     1
+#define FTM_SYNC_TRIG1(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK                      0x40u
+#define FTM_SYNC_TRIG2_SHIFT                     6
+#define FTM_SYNC_TRIG2_WIDTH                     1
+#define FTM_SYNC_TRIG2(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK                     0x80u
+#define FTM_SYNC_SWSYNC_SHIFT                    7
+#define FTM_SYNC_SWSYNC_WIDTH                    1
+#define FTM_SYNC_SWSYNC(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK                   0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT                  0
+#define FTM_OUTINIT_CH0OI_WIDTH                  1
+#define FTM_OUTINIT_CH0OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK                   0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT                  1
+#define FTM_OUTINIT_CH1OI_WIDTH                  1
+#define FTM_OUTINIT_CH1OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK                   0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT                  2
+#define FTM_OUTINIT_CH2OI_WIDTH                  1
+#define FTM_OUTINIT_CH2OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK                   0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT                  3
+#define FTM_OUTINIT_CH3OI_WIDTH                  1
+#define FTM_OUTINIT_CH3OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK                   0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT                  4
+#define FTM_OUTINIT_CH4OI_WIDTH                  1
+#define FTM_OUTINIT_CH4OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK                   0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT                  5
+#define FTM_OUTINIT_CH5OI_WIDTH                  1
+#define FTM_OUTINIT_CH5OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK                   0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT                  6
+#define FTM_OUTINIT_CH6OI_WIDTH                  1
+#define FTM_OUTINIT_CH6OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK                   0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT                  7
+#define FTM_OUTINIT_CH7OI_WIDTH                  1
+#define FTM_OUTINIT_CH7OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK                   0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT                  0
+#define FTM_OUTMASK_CH0OM_WIDTH                  1
+#define FTM_OUTMASK_CH0OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK                   0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT                  1
+#define FTM_OUTMASK_CH1OM_WIDTH                  1
+#define FTM_OUTMASK_CH1OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK                   0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT                  2
+#define FTM_OUTMASK_CH2OM_WIDTH                  1
+#define FTM_OUTMASK_CH2OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK                   0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT                  3
+#define FTM_OUTMASK_CH3OM_WIDTH                  1
+#define FTM_OUTMASK_CH3OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK                   0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT                  4
+#define FTM_OUTMASK_CH4OM_WIDTH                  1
+#define FTM_OUTMASK_CH4OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK                   0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT                  5
+#define FTM_OUTMASK_CH5OM_WIDTH                  1
+#define FTM_OUTMASK_CH5OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK                   0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT                  6
+#define FTM_OUTMASK_CH6OM_WIDTH                  1
+#define FTM_OUTMASK_CH6OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK                   0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT                  7
+#define FTM_OUTMASK_CH7OM_WIDTH                  1
+#define FTM_OUTMASK_CH7OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK                0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT               0
+#define FTM_COMBINE_COMBINE0_WIDTH               1
+#define FTM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK                   0x2u
+#define FTM_COMBINE_COMP0_SHIFT                  1
+#define FTM_COMBINE_COMP0_WIDTH                  1
+#define FTM_COMBINE_COMP0(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK                0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT               2
+#define FTM_COMBINE_DECAPEN0_WIDTH               1
+#define FTM_COMBINE_DECAPEN0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK                  0x8u
+#define FTM_COMBINE_DECAP0_SHIFT                 3
+#define FTM_COMBINE_DECAP0_WIDTH                 1
+#define FTM_COMBINE_DECAP0(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK                   0x10u
+#define FTM_COMBINE_DTEN0_SHIFT                  4
+#define FTM_COMBINE_DTEN0_WIDTH                  1
+#define FTM_COMBINE_DTEN0(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK                 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT                5
+#define FTM_COMBINE_SYNCEN0_WIDTH                1
+#define FTM_COMBINE_SYNCEN0(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK                0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT               6
+#define FTM_COMBINE_FAULTEN0_WIDTH               1
+#define FTM_COMBINE_FAULTEN0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK                0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT               8
+#define FTM_COMBINE_COMBINE1_WIDTH               1
+#define FTM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK                   0x200u
+#define FTM_COMBINE_COMP1_SHIFT                  9
+#define FTM_COMBINE_COMP1_WIDTH                  1
+#define FTM_COMBINE_COMP1(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK                0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT               10
+#define FTM_COMBINE_DECAPEN1_WIDTH               1
+#define FTM_COMBINE_DECAPEN1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK                  0x800u
+#define FTM_COMBINE_DECAP1_SHIFT                 11
+#define FTM_COMBINE_DECAP1_WIDTH                 1
+#define FTM_COMBINE_DECAP1(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK                   0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT                  12
+#define FTM_COMBINE_DTEN1_WIDTH                  1
+#define FTM_COMBINE_DTEN1(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK                 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT                13
+#define FTM_COMBINE_SYNCEN1_WIDTH                1
+#define FTM_COMBINE_SYNCEN1(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK                0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT               14
+#define FTM_COMBINE_FAULTEN1_WIDTH               1
+#define FTM_COMBINE_FAULTEN1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK                0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT               16
+#define FTM_COMBINE_COMBINE2_WIDTH               1
+#define FTM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK                   0x20000u
+#define FTM_COMBINE_COMP2_SHIFT                  17
+#define FTM_COMBINE_COMP2_WIDTH                  1
+#define FTM_COMBINE_COMP2(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK                0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT               18
+#define FTM_COMBINE_DECAPEN2_WIDTH               1
+#define FTM_COMBINE_DECAPEN2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK                  0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT                 19
+#define FTM_COMBINE_DECAP2_WIDTH                 1
+#define FTM_COMBINE_DECAP2(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK                   0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT                  20
+#define FTM_COMBINE_DTEN2_WIDTH                  1
+#define FTM_COMBINE_DTEN2(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK                 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT                21
+#define FTM_COMBINE_SYNCEN2_WIDTH                1
+#define FTM_COMBINE_SYNCEN2(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK                0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT               22
+#define FTM_COMBINE_FAULTEN2_WIDTH               1
+#define FTM_COMBINE_FAULTEN2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK                0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT               24
+#define FTM_COMBINE_COMBINE3_WIDTH               1
+#define FTM_COMBINE_COMBINE3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK                   0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT                  25
+#define FTM_COMBINE_COMP3_WIDTH                  1
+#define FTM_COMBINE_COMP3(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK                0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT               26
+#define FTM_COMBINE_DECAPEN3_WIDTH               1
+#define FTM_COMBINE_DECAPEN3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK                  0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT                 27
+#define FTM_COMBINE_DECAP3_WIDTH                 1
+#define FTM_COMBINE_DECAP3(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK                   0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT                  28
+#define FTM_COMBINE_DTEN3_WIDTH                  1
+#define FTM_COMBINE_DTEN3(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK                 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT                29
+#define FTM_COMBINE_SYNCEN3_WIDTH                1
+#define FTM_COMBINE_SYNCEN3(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK                0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT               30
+#define FTM_COMBINE_FAULTEN3_WIDTH               1
+#define FTM_COMBINE_FAULTEN3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK                  0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT                 0
+#define FTM_DEADTIME_DTVAL_WIDTH                 6
+#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK                   0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT                  6
+#define FTM_DEADTIME_DTPS_WIDTH                  2
+#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK                 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT                0
+#define FTM_EXTTRIG_CH2TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH2TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK                 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT                1
+#define FTM_EXTTRIG_CH3TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH3TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK                 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT                2
+#define FTM_EXTTRIG_CH4TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH4TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK                 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT                3
+#define FTM_EXTTRIG_CH5TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH5TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK                 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT                4
+#define FTM_EXTTRIG_CH0TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH0TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK                 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT                5
+#define FTM_EXTTRIG_CH1TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH1TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK              0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT             6
+#define FTM_EXTTRIG_INITTRIGEN_WIDTH             1
+#define FTM_EXTTRIG_INITTRIGEN(x)                (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK                   0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT                  7
+#define FTM_EXTTRIG_TRIGF_WIDTH                  1
+#define FTM_EXTTRIG_TRIGF(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK                        0x1u
+#define FTM_POL_POL0_SHIFT                       0
+#define FTM_POL_POL0_WIDTH                       1
+#define FTM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK                        0x2u
+#define FTM_POL_POL1_SHIFT                       1
+#define FTM_POL_POL1_WIDTH                       1
+#define FTM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK                        0x4u
+#define FTM_POL_POL2_SHIFT                       2
+#define FTM_POL_POL2_WIDTH                       1
+#define FTM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK                        0x8u
+#define FTM_POL_POL3_SHIFT                       3
+#define FTM_POL_POL3_WIDTH                       1
+#define FTM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK                        0x10u
+#define FTM_POL_POL4_SHIFT                       4
+#define FTM_POL_POL4_WIDTH                       1
+#define FTM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK                        0x20u
+#define FTM_POL_POL5_SHIFT                       5
+#define FTM_POL_POL5_WIDTH                       1
+#define FTM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK                        0x40u
+#define FTM_POL_POL6_SHIFT                       6
+#define FTM_POL_POL6_WIDTH                       1
+#define FTM_POL_POL6(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK                        0x80u
+#define FTM_POL_POL7_SHIFT                       7
+#define FTM_POL_POL7_WIDTH                       1
+#define FTM_POL_POL7(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK                     0x1u
+#define FTM_FMS_FAULTF0_SHIFT                    0
+#define FTM_FMS_FAULTF0_WIDTH                    1
+#define FTM_FMS_FAULTF0(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK                     0x2u
+#define FTM_FMS_FAULTF1_SHIFT                    1
+#define FTM_FMS_FAULTF1_WIDTH                    1
+#define FTM_FMS_FAULTF1(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK                     0x4u
+#define FTM_FMS_FAULTF2_SHIFT                    2
+#define FTM_FMS_FAULTF2_WIDTH                    1
+#define FTM_FMS_FAULTF2(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK                     0x8u
+#define FTM_FMS_FAULTF3_SHIFT                    3
+#define FTM_FMS_FAULTF3_WIDTH                    1
+#define FTM_FMS_FAULTF3(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK                     0x20u
+#define FTM_FMS_FAULTIN_SHIFT                    5
+#define FTM_FMS_FAULTIN_WIDTH                    1
+#define FTM_FMS_FAULTIN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK                        0x40u
+#define FTM_FMS_WPEN_SHIFT                       6
+#define FTM_FMS_WPEN_WIDTH                       1
+#define FTM_FMS_WPEN(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK                      0x80u
+#define FTM_FMS_FAULTF_SHIFT                     7
+#define FTM_FMS_FAULTF_WIDTH                     1
+#define FTM_FMS_FAULTF(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK                  0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT                 0
+#define FTM_FILTER_CH0FVAL_WIDTH                 4
+#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK                  0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT                 4
+#define FTM_FILTER_CH1FVAL_WIDTH                 4
+#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK                  0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT                 8
+#define FTM_FILTER_CH2FVAL_WIDTH                 4
+#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK                  0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT                 12
+#define FTM_FILTER_CH3FVAL_WIDTH                 4
+#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK                0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT               0
+#define FTM_FLTCTRL_FAULT0EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT0EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK                0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT               1
+#define FTM_FLTCTRL_FAULT1EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT1EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK                0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT               2
+#define FTM_FLTCTRL_FAULT2EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT2EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK                0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT               3
+#define FTM_FLTCTRL_FAULT3EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT3EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK                0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT               4
+#define FTM_FLTCTRL_FFLTR0EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR0EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK                0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT               5
+#define FTM_FLTCTRL_FFLTR1EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR1EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK                0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT               6
+#define FTM_FLTCTRL_FFLTR2EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR2EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK                0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT               7
+#define FTM_FLTCTRL_FFLTR3EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR3EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK                   0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT                  8
+#define FTM_FLTCTRL_FFVAL_WIDTH                  4
+#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK                   0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT                  0
+#define FTM_QDCTRL_QUADEN_WIDTH                  1
+#define FTM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK                   0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT                  1
+#define FTM_QDCTRL_TOFDIR_WIDTH                  1
+#define FTM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK                   0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT                  2
+#define FTM_QDCTRL_QUADIR_WIDTH                  1
+#define FTM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK                 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT                3
+#define FTM_QDCTRL_QUADMODE_WIDTH                1
+#define FTM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK                   0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT                  4
+#define FTM_QDCTRL_PHBPOL_WIDTH                  1
+#define FTM_QDCTRL_PHBPOL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK                   0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT                  5
+#define FTM_QDCTRL_PHAPOL_WIDTH                  1
+#define FTM_QDCTRL_PHAPOL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK                0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT               6
+#define FTM_QDCTRL_PHBFLTREN_WIDTH               1
+#define FTM_QDCTRL_PHBFLTREN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK                0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT               7
+#define FTM_QDCTRL_PHAFLTREN_WIDTH               1
+#define FTM_QDCTRL_PHAFLTREN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK                     0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT                    0
+#define FTM_CONF_NUMTOF_WIDTH                    5
+#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK                    0xC0u
+#define FTM_CONF_BDMMODE_SHIFT                   6
+#define FTM_CONF_BDMMODE_WIDTH                   2
+#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK                     0x200u
+#define FTM_CONF_GTBEEN_SHIFT                    9
+#define FTM_CONF_GTBEEN_WIDTH                    1
+#define FTM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK                    0x400u
+#define FTM_CONF_GTBEOUT_SHIFT                   10
+#define FTM_CONF_GTBEOUT_WIDTH                   1
+#define FTM_CONF_GTBEOUT(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK                  0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT                 0
+#define FTM_FLTPOL_FLT0POL_WIDTH                 1
+#define FTM_FLTPOL_FLT0POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK                  0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT                 1
+#define FTM_FLTPOL_FLT1POL_WIDTH                 1
+#define FTM_FLTPOL_FLT1POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK                  0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT                 2
+#define FTM_FLTPOL_FLT2POL_WIDTH                 1
+#define FTM_FLTPOL_FLT2POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK                  0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT                 3
+#define FTM_FLTPOL_FLT3POL_WIDTH                 1
+#define FTM_FLTPOL_FLT3POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK              0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT             0
+#define FTM_SYNCONF_HWTRIGMODE_WIDTH             1
+#define FTM_SYNCONF_HWTRIGMODE(x)                (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK                  0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT                 2
+#define FTM_SYNCONF_CNTINC_WIDTH                 1
+#define FTM_SYNCONF_CNTINC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK                    0x10u
+#define FTM_SYNCONF_INVC_SHIFT                   4
+#define FTM_SYNCONF_INVC_WIDTH                   1
+#define FTM_SYNCONF_INVC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK                    0x20u
+#define FTM_SYNCONF_SWOC_SHIFT                   5
+#define FTM_SYNCONF_SWOC_WIDTH                   1
+#define FTM_SYNCONF_SWOC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK                0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT               7
+#define FTM_SYNCONF_SYNCMODE_WIDTH               1
+#define FTM_SYNCONF_SYNCMODE(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK                0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT               8
+#define FTM_SYNCONF_SWRSTCNT_WIDTH               1
+#define FTM_SYNCONF_SWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK                 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT                9
+#define FTM_SYNCONF_SWWRBUF_WIDTH                1
+#define FTM_SYNCONF_SWWRBUF(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK                    0x400u
+#define FTM_SYNCONF_SWOM_SHIFT                   10
+#define FTM_SYNCONF_SWOM_WIDTH                   1
+#define FTM_SYNCONF_SWOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK                  0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT                 11
+#define FTM_SYNCONF_SWINVC_WIDTH                 1
+#define FTM_SYNCONF_SWINVC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK                   0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT                  12
+#define FTM_SYNCONF_SWSOC_WIDTH                  1
+#define FTM_SYNCONF_SWSOC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK                0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT               16
+#define FTM_SYNCONF_HWRSTCNT_WIDTH               1
+#define FTM_SYNCONF_HWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK                 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT                17
+#define FTM_SYNCONF_HWWRBUF_WIDTH                1
+#define FTM_SYNCONF_HWWRBUF(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK                    0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT                   18
+#define FTM_SYNCONF_HWOM_WIDTH                   1
+#define FTM_SYNCONF_HWOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK                  0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT                 19
+#define FTM_SYNCONF_HWINVC_WIDTH                 1
+#define FTM_SYNCONF_HWINVC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK                   0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT                  20
+#define FTM_SYNCONF_HWSOC_WIDTH                  1
+#define FTM_SYNCONF_HWSOC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK                  0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT                 0
+#define FTM_INVCTRL_INV0EN_WIDTH                 1
+#define FTM_INVCTRL_INV0EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK                  0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT                 1
+#define FTM_INVCTRL_INV1EN_WIDTH                 1
+#define FTM_INVCTRL_INV1EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK                  0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT                 2
+#define FTM_INVCTRL_INV2EN_WIDTH                 1
+#define FTM_INVCTRL_INV2EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK                  0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT                 3
+#define FTM_INVCTRL_INV3EN_WIDTH                 1
+#define FTM_INVCTRL_INV3EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK                   0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT                  0
+#define FTM_SWOCTRL_CH0OC_WIDTH                  1
+#define FTM_SWOCTRL_CH0OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK                   0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT                  1
+#define FTM_SWOCTRL_CH1OC_WIDTH                  1
+#define FTM_SWOCTRL_CH1OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK                   0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT                  2
+#define FTM_SWOCTRL_CH2OC_WIDTH                  1
+#define FTM_SWOCTRL_CH2OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK                   0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT                  3
+#define FTM_SWOCTRL_CH3OC_WIDTH                  1
+#define FTM_SWOCTRL_CH3OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK                   0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT                  4
+#define FTM_SWOCTRL_CH4OC_WIDTH                  1
+#define FTM_SWOCTRL_CH4OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK                   0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT                  5
+#define FTM_SWOCTRL_CH5OC_WIDTH                  1
+#define FTM_SWOCTRL_CH5OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK                   0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT                  6
+#define FTM_SWOCTRL_CH6OC_WIDTH                  1
+#define FTM_SWOCTRL_CH6OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK                   0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT                  7
+#define FTM_SWOCTRL_CH7OC_WIDTH                  1
+#define FTM_SWOCTRL_CH7OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK                  0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT                 8
+#define FTM_SWOCTRL_CH0OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH0OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK                  0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT                 9
+#define FTM_SWOCTRL_CH1OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH1OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK                  0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT                 10
+#define FTM_SWOCTRL_CH2OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH2OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK                  0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT                 11
+#define FTM_SWOCTRL_CH3OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH3OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK                  0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT                 12
+#define FTM_SWOCTRL_CH4OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH4OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK                  0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT                 13
+#define FTM_SWOCTRL_CH5OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH5OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK                  0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT                 14
+#define FTM_SWOCTRL_CH6OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH6OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK                  0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT                 15
+#define FTM_SWOCTRL_CH7OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH7OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK                  0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT                 0
+#define FTM_PWMLOAD_CH0SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH0SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK                  0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT                 1
+#define FTM_PWMLOAD_CH1SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH1SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK                  0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT                 2
+#define FTM_PWMLOAD_CH2SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH2SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK                  0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT                 3
+#define FTM_PWMLOAD_CH3SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH3SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK                  0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT                 4
+#define FTM_PWMLOAD_CH4SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH4SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK                  0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT                 5
+#define FTM_PWMLOAD_CH5SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH5SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK                  0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT                 6
+#define FTM_PWMLOAD_CH6SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH6SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK                  0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT                 7
+#define FTM_PWMLOAD_CH7SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH7SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK                    0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT                   9
+#define FTM_PWMLOAD_LDOK_WIDTH                   1
+#define FTM_PWMLOAD_LDOK(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE                                (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0                                     ((FTM_Type *)FTM0_BASE)
+#define FTM0_BASE_PTR                            (FTM0)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE                                (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1                                     ((FTM_Type *)FTM1_BASE)
+#define FTM1_BASE_PTR                            (FTM1)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE                                (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2                                     ((FTM_Type *)FTM2_BASE)
+#define FTM2_BASE_PTR                            (FTM2)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE                                (0x400B9000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3                                     ((FTM_Type *)FTM3_BASE)
+#define FTM3_BASE_PTR                            (FTM3)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS                           { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS                            { FTM0, FTM1, FTM2, FTM3 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS                                 { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register instance definitions */
+/* FTM0 */
+#define FTM0_SC                                  FTM_SC_REG(FTM0)
+#define FTM0_CNT                                 FTM_CNT_REG(FTM0)
+#define FTM0_MOD                                 FTM_MOD_REG(FTM0)
+#define FTM0_C0SC                                FTM_CnSC_REG(FTM0,0)
+#define FTM0_C0V                                 FTM_CnV_REG(FTM0,0)
+#define FTM0_C1SC                                FTM_CnSC_REG(FTM0,1)
+#define FTM0_C1V                                 FTM_CnV_REG(FTM0,1)
+#define FTM0_C2SC                                FTM_CnSC_REG(FTM0,2)
+#define FTM0_C2V                                 FTM_CnV_REG(FTM0,2)
+#define FTM0_C3SC                                FTM_CnSC_REG(FTM0,3)
+#define FTM0_C3V                                 FTM_CnV_REG(FTM0,3)
+#define FTM0_C4SC                                FTM_CnSC_REG(FTM0,4)
+#define FTM0_C4V                                 FTM_CnV_REG(FTM0,4)
+#define FTM0_C5SC                                FTM_CnSC_REG(FTM0,5)
+#define FTM0_C5V                                 FTM_CnV_REG(FTM0,5)
+#define FTM0_C6SC                                FTM_CnSC_REG(FTM0,6)
+#define FTM0_C6V                                 FTM_CnV_REG(FTM0,6)
+#define FTM0_C7SC                                FTM_CnSC_REG(FTM0,7)
+#define FTM0_C7V                                 FTM_CnV_REG(FTM0,7)
+#define FTM0_CNTIN                               FTM_CNTIN_REG(FTM0)
+#define FTM0_STATUS                              FTM_STATUS_REG(FTM0)
+#define FTM0_MODE                                FTM_MODE_REG(FTM0)
+#define FTM0_SYNC                                FTM_SYNC_REG(FTM0)
+#define FTM0_OUTINIT                             FTM_OUTINIT_REG(FTM0)
+#define FTM0_OUTMASK                             FTM_OUTMASK_REG(FTM0)
+#define FTM0_COMBINE                             FTM_COMBINE_REG(FTM0)
+#define FTM0_DEADTIME                            FTM_DEADTIME_REG(FTM0)
+#define FTM0_EXTTRIG                             FTM_EXTTRIG_REG(FTM0)
+#define FTM0_POL                                 FTM_POL_REG(FTM0)
+#define FTM0_FMS                                 FTM_FMS_REG(FTM0)
+#define FTM0_FILTER                              FTM_FILTER_REG(FTM0)
+#define FTM0_FLTCTRL                             FTM_FLTCTRL_REG(FTM0)
+#define FTM0_QDCTRL                              FTM_QDCTRL_REG(FTM0)
+#define FTM0_CONF                                FTM_CONF_REG(FTM0)
+#define FTM0_FLTPOL                              FTM_FLTPOL_REG(FTM0)
+#define FTM0_SYNCONF                             FTM_SYNCONF_REG(FTM0)
+#define FTM0_INVCTRL                             FTM_INVCTRL_REG(FTM0)
+#define FTM0_SWOCTRL                             FTM_SWOCTRL_REG(FTM0)
+#define FTM0_PWMLOAD                             FTM_PWMLOAD_REG(FTM0)
+/* FTM1 */
+#define FTM1_SC                                  FTM_SC_REG(FTM1)
+#define FTM1_CNT                                 FTM_CNT_REG(FTM1)
+#define FTM1_MOD                                 FTM_MOD_REG(FTM1)
+#define FTM1_C0SC                                FTM_CnSC_REG(FTM1,0)
+#define FTM1_C0V                                 FTM_CnV_REG(FTM1,0)
+#define FTM1_C1SC                                FTM_CnSC_REG(FTM1,1)
+#define FTM1_C1V                                 FTM_CnV_REG(FTM1,1)
+#define FTM1_CNTIN                               FTM_CNTIN_REG(FTM1)
+#define FTM1_STATUS                              FTM_STATUS_REG(FTM1)
+#define FTM1_MODE                                FTM_MODE_REG(FTM1)
+#define FTM1_SYNC                                FTM_SYNC_REG(FTM1)
+#define FTM1_OUTINIT                             FTM_OUTINIT_REG(FTM1)
+#define FTM1_OUTMASK                             FTM_OUTMASK_REG(FTM1)
+#define FTM1_COMBINE                             FTM_COMBINE_REG(FTM1)
+#define FTM1_DEADTIME                            FTM_DEADTIME_REG(FTM1)
+#define FTM1_EXTTRIG                             FTM_EXTTRIG_REG(FTM1)
+#define FTM1_POL                                 FTM_POL_REG(FTM1)
+#define FTM1_FMS                                 FTM_FMS_REG(FTM1)
+#define FTM1_FILTER                              FTM_FILTER_REG(FTM1)
+#define FTM1_FLTCTRL                             FTM_FLTCTRL_REG(FTM1)
+#define FTM1_QDCTRL                              FTM_QDCTRL_REG(FTM1)
+#define FTM1_CONF                                FTM_CONF_REG(FTM1)
+#define FTM1_FLTPOL                              FTM_FLTPOL_REG(FTM1)
+#define FTM1_SYNCONF                             FTM_SYNCONF_REG(FTM1)
+#define FTM1_INVCTRL                             FTM_INVCTRL_REG(FTM1)
+#define FTM1_SWOCTRL                             FTM_SWOCTRL_REG(FTM1)
+#define FTM1_PWMLOAD                             FTM_PWMLOAD_REG(FTM1)
+/* FTM2 */
+#define FTM2_SC                                  FTM_SC_REG(FTM2)
+#define FTM2_CNT                                 FTM_CNT_REG(FTM2)
+#define FTM2_MOD                                 FTM_MOD_REG(FTM2)
+#define FTM2_C0SC                                FTM_CnSC_REG(FTM2,0)
+#define FTM2_C0V                                 FTM_CnV_REG(FTM2,0)
+#define FTM2_C1SC                                FTM_CnSC_REG(FTM2,1)
+#define FTM2_C1V                                 FTM_CnV_REG(FTM2,1)
+#define FTM2_CNTIN                               FTM_CNTIN_REG(FTM2)
+#define FTM2_STATUS                              FTM_STATUS_REG(FTM2)
+#define FTM2_MODE                                FTM_MODE_REG(FTM2)
+#define FTM2_SYNC                                FTM_SYNC_REG(FTM2)
+#define FTM2_OUTINIT                             FTM_OUTINIT_REG(FTM2)
+#define FTM2_OUTMASK                             FTM_OUTMASK_REG(FTM2)
+#define FTM2_COMBINE                             FTM_COMBINE_REG(FTM2)
+#define FTM2_DEADTIME                            FTM_DEADTIME_REG(FTM2)
+#define FTM2_EXTTRIG                             FTM_EXTTRIG_REG(FTM2)
+#define FTM2_POL                                 FTM_POL_REG(FTM2)
+#define FTM2_FMS                                 FTM_FMS_REG(FTM2)
+#define FTM2_FILTER                              FTM_FILTER_REG(FTM2)
+#define FTM2_FLTCTRL                             FTM_FLTCTRL_REG(FTM2)
+#define FTM2_QDCTRL                              FTM_QDCTRL_REG(FTM2)
+#define FTM2_CONF                                FTM_CONF_REG(FTM2)
+#define FTM2_FLTPOL                              FTM_FLTPOL_REG(FTM2)
+#define FTM2_SYNCONF                             FTM_SYNCONF_REG(FTM2)
+#define FTM2_INVCTRL                             FTM_INVCTRL_REG(FTM2)
+#define FTM2_SWOCTRL                             FTM_SWOCTRL_REG(FTM2)
+#define FTM2_PWMLOAD                             FTM_PWMLOAD_REG(FTM2)
+/* FTM3 */
+#define FTM3_SC                                  FTM_SC_REG(FTM3)
+#define FTM3_CNT                                 FTM_CNT_REG(FTM3)
+#define FTM3_MOD                                 FTM_MOD_REG(FTM3)
+#define FTM3_C0SC                                FTM_CnSC_REG(FTM3,0)
+#define FTM3_C0V                                 FTM_CnV_REG(FTM3,0)
+#define FTM3_C1SC                                FTM_CnSC_REG(FTM3,1)
+#define FTM3_C1V                                 FTM_CnV_REG(FTM3,1)
+#define FTM3_C2SC                                FTM_CnSC_REG(FTM3,2)
+#define FTM3_C2V                                 FTM_CnV_REG(FTM3,2)
+#define FTM3_C3SC                                FTM_CnSC_REG(FTM3,3)
+#define FTM3_C3V                                 FTM_CnV_REG(FTM3,3)
+#define FTM3_C4SC                                FTM_CnSC_REG(FTM3,4)
+#define FTM3_C4V                                 FTM_CnV_REG(FTM3,4)
+#define FTM3_C5SC                                FTM_CnSC_REG(FTM3,5)
+#define FTM3_C5V                                 FTM_CnV_REG(FTM3,5)
+#define FTM3_C6SC                                FTM_CnSC_REG(FTM3,6)
+#define FTM3_C6V                                 FTM_CnV_REG(FTM3,6)
+#define FTM3_C7SC                                FTM_CnSC_REG(FTM3,7)
+#define FTM3_C7V                                 FTM_CnV_REG(FTM3,7)
+#define FTM3_CNTIN                               FTM_CNTIN_REG(FTM3)
+#define FTM3_STATUS                              FTM_STATUS_REG(FTM3)
+#define FTM3_MODE                                FTM_MODE_REG(FTM3)
+#define FTM3_SYNC                                FTM_SYNC_REG(FTM3)
+#define FTM3_OUTINIT                             FTM_OUTINIT_REG(FTM3)
+#define FTM3_OUTMASK                             FTM_OUTMASK_REG(FTM3)
+#define FTM3_COMBINE                             FTM_COMBINE_REG(FTM3)
+#define FTM3_DEADTIME                            FTM_DEADTIME_REG(FTM3)
+#define FTM3_EXTTRIG                             FTM_EXTTRIG_REG(FTM3)
+#define FTM3_POL                                 FTM_POL_REG(FTM3)
+#define FTM3_FMS                                 FTM_FMS_REG(FTM3)
+#define FTM3_FILTER                              FTM_FILTER_REG(FTM3)
+#define FTM3_FLTCTRL                             FTM_FLTCTRL_REG(FTM3)
+#define FTM3_QDCTRL                              FTM_QDCTRL_REG(FTM3)
+#define FTM3_CONF                                FTM_CONF_REG(FTM3)
+#define FTM3_FLTPOL                              FTM_FLTPOL_REG(FTM3)
+#define FTM3_SYNCONF                             FTM_SYNCONF_REG(FTM3)
+#define FTM3_INVCTRL                             FTM_INVCTRL_REG(FTM3)
+#define FTM3_SWOCTRL                             FTM_SWOCTRL_REG(FTM3)
+#define FTM3_PWMLOAD                             FTM_PWMLOAD_REG(FTM3)
+
+/* FTM - Register array accessors */
+#define FTM0_CnSC(index)                         FTM_CnSC_REG(FTM0,index)
+#define FTM1_CnSC(index)                         FTM_CnSC_REG(FTM1,index)
+#define FTM2_CnSC(index)                         FTM_CnSC_REG(FTM2,index)
+#define FTM3_CnSC(index)                         FTM_CnSC_REG(FTM3,index)
+#define FTM0_CnV(index)                          FTM_CnV_REG(FTM0,index)
+#define FTM1_CnV(index)                          FTM_CnV_REG(FTM1,index)
+#define FTM2_CnV(index)                          FTM_CnV_REG(FTM2,index)
+#define FTM3_CnV(index)                          FTM_CnV_REG(FTM3,index)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base)                      ((base)->PDOR)
+#define GPIO_PSOR_REG(base)                      ((base)->PSOR)
+#define GPIO_PCOR_REG(base)                      ((base)->PCOR)
+#define GPIO_PTOR_REG(base)                      ((base)->PTOR)
+#define GPIO_PDIR_REG(base)                      ((base)->PDIR)
+#define GPIO_PDDR_REG(base)                      ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT                      0
+#define GPIO_PDOR_PDO_WIDTH                      32
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT                     0
+#define GPIO_PSOR_PTSO_WIDTH                     32
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT                     0
+#define GPIO_PCOR_PTCO_WIDTH                     32
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT                     0
+#define GPIO_PTOR_PTTO_WIDTH                     32
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT                      0
+#define GPIO_PDIR_PDI_WIDTH                      32
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT                      0
+#define GPIO_PDDR_PDD_WIDTH                      32
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE                                 (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA                                      ((GPIO_Type *)PTA_BASE)
+#define PTA_BASE_PTR                             (PTA)
+/** Peripheral PTB base address */
+#define PTB_BASE                                 (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB                                      ((GPIO_Type *)PTB_BASE)
+#define PTB_BASE_PTR                             (PTB)
+/** Peripheral PTC base address */
+#define PTC_BASE                                 (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC                                      ((GPIO_Type *)PTC_BASE)
+#define PTC_BASE_PTR                             (PTC)
+/** Peripheral PTD base address */
+#define PTD_BASE                                 (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD                                      ((GPIO_Type *)PTD_BASE)
+#define PTD_BASE_PTR                             (PTD)
+/** Peripheral PTE base address */
+#define PTE_BASE                                 (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE                                      ((GPIO_Type *)PTE_BASE)
+#define PTE_BASE_PTR                             (PTE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { PTA, PTB, PTC, PTD, PTE }
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* PTA */
+#define GPIOA_PDOR                               GPIO_PDOR_REG(PTA)
+#define GPIOA_PSOR                               GPIO_PSOR_REG(PTA)
+#define GPIOA_PCOR                               GPIO_PCOR_REG(PTA)
+#define GPIOA_PTOR                               GPIO_PTOR_REG(PTA)
+#define GPIOA_PDIR                               GPIO_PDIR_REG(PTA)
+#define GPIOA_PDDR                               GPIO_PDDR_REG(PTA)
+/* PTB */
+#define GPIOB_PDOR                               GPIO_PDOR_REG(PTB)
+#define GPIOB_PSOR                               GPIO_PSOR_REG(PTB)
+#define GPIOB_PCOR                               GPIO_PCOR_REG(PTB)
+#define GPIOB_PTOR                               GPIO_PTOR_REG(PTB)
+#define GPIOB_PDIR                               GPIO_PDIR_REG(PTB)
+#define GPIOB_PDDR                               GPIO_PDDR_REG(PTB)
+/* PTC */
+#define GPIOC_PDOR                               GPIO_PDOR_REG(PTC)
+#define GPIOC_PSOR                               GPIO_PSOR_REG(PTC)
+#define GPIOC_PCOR                               GPIO_PCOR_REG(PTC)
+#define GPIOC_PTOR                               GPIO_PTOR_REG(PTC)
+#define GPIOC_PDIR                               GPIO_PDIR_REG(PTC)
+#define GPIOC_PDDR                               GPIO_PDDR_REG(PTC)
+/* PTD */
+#define GPIOD_PDOR                               GPIO_PDOR_REG(PTD)
+#define GPIOD_PSOR                               GPIO_PSOR_REG(PTD)
+#define GPIOD_PCOR                               GPIO_PCOR_REG(PTD)
+#define GPIOD_PTOR                               GPIO_PTOR_REG(PTD)
+#define GPIOD_PDIR                               GPIO_PDIR_REG(PTD)
+#define GPIOD_PDDR                               GPIO_PDDR_REG(PTD)
+/* PTE */
+#define GPIOE_PDOR                               GPIO_PDOR_REG(PTE)
+#define GPIOE_PSOR                               GPIO_PSOR_REG(PTE)
+#define GPIOE_PCOR                               GPIO_PCOR_REG(PTE)
+#define GPIOE_PTOR                               GPIO_PTOR_REG(PTE)
+#define GPIOE_PDIR                               GPIO_PDIR_REG(PTE)
+#define GPIOE_PDDR                               GPIO_PDDR_REG(PTE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base)                         ((base)->A1)
+#define I2C_F_REG(base)                          ((base)->F)
+#define I2C_C1_REG(base)                         ((base)->C1)
+#define I2C_S_REG(base)                          ((base)->S)
+#define I2C_D_REG(base)                          ((base)->D)
+#define I2C_C2_REG(base)                         ((base)->C2)
+#define I2C_FLT_REG(base)                        ((base)->FLT)
+#define I2C_RA_REG(base)                         ((base)->RA)
+#define I2C_SMB_REG(base)                        ((base)->SMB)
+#define I2C_A2_REG(base)                         ((base)->A2)
+#define I2C_SLTH_REG(base)                       ((base)->SLTH)
+#define I2C_SLTL_REG(base)                       ((base)->SLTL)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK                           0xFEu
+#define I2C_A1_AD_SHIFT                          1
+#define I2C_A1_AD_WIDTH                          7
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK                           0x3Fu
+#define I2C_F_ICR_SHIFT                          0
+#define I2C_F_ICR_WIDTH                          6
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          0xC0u
+#define I2C_F_MULT_SHIFT                         6
+#define I2C_F_MULT_WIDTH                         2
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK                        0x1u
+#define I2C_C1_DMAEN_SHIFT                       0
+#define I2C_C1_DMAEN_WIDTH                       1
+#define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_DMAEN_SHIFT))&I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK                         0x2u
+#define I2C_C1_WUEN_SHIFT                        1
+#define I2C_C1_WUEN_WIDTH                        1
+#define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_WUEN_SHIFT))&I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK                         0x4u
+#define I2C_C1_RSTA_SHIFT                        2
+#define I2C_C1_RSTA_WIDTH                        1
+#define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_RSTA_SHIFT))&I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK                         0x8u
+#define I2C_C1_TXAK_SHIFT                        3
+#define I2C_C1_TXAK_WIDTH                        1
+#define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_TXAK_SHIFT))&I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK                           0x10u
+#define I2C_C1_TX_SHIFT                          4
+#define I2C_C1_TX_WIDTH                          1
+#define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C1_TX_SHIFT))&I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK                          0x20u
+#define I2C_C1_MST_SHIFT                         5
+#define I2C_C1_MST_WIDTH                         1
+#define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_C1_MST_SHIFT))&I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK                        0x40u
+#define I2C_C1_IICIE_SHIFT                       6
+#define I2C_C1_IICIE_WIDTH                       1
+#define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICIE_SHIFT))&I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK                        0x80u
+#define I2C_C1_IICEN_SHIFT                       7
+#define I2C_C1_IICEN_WIDTH                       1
+#define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICEN_SHIFT))&I2C_C1_IICEN_MASK)
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK                          0x1u
+#define I2C_S_RXAK_SHIFT                         0
+#define I2C_S_RXAK_WIDTH                         1
+#define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_RXAK_SHIFT))&I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK                         0x2u
+#define I2C_S_IICIF_SHIFT                        1
+#define I2C_S_IICIF_WIDTH                        1
+#define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_S_IICIF_SHIFT))&I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK                           0x4u
+#define I2C_S_SRW_SHIFT                          2
+#define I2C_S_SRW_WIDTH                          1
+#define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_SRW_SHIFT))&I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK                           0x8u
+#define I2C_S_RAM_SHIFT                          3
+#define I2C_S_RAM_WIDTH                          1
+#define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_RAM_SHIFT))&I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK                          0x10u
+#define I2C_S_ARBL_SHIFT                         4
+#define I2C_S_ARBL_WIDTH                         1
+#define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_ARBL_SHIFT))&I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK                          0x20u
+#define I2C_S_BUSY_SHIFT                         5
+#define I2C_S_BUSY_WIDTH                         1
+#define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_BUSY_SHIFT))&I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK                          0x40u
+#define I2C_S_IAAS_SHIFT                         6
+#define I2C_S_IAAS_WIDTH                         1
+#define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_IAAS_SHIFT))&I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK                           0x80u
+#define I2C_S_TCF_SHIFT                          7
+#define I2C_S_TCF_WIDTH                          1
+#define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_TCF_SHIFT))&I2C_S_TCF_MASK)
+/* D Bit Fields */
+#define I2C_D_DATA_MASK                          0xFFu
+#define I2C_D_DATA_SHIFT                         0
+#define I2C_D_DATA_WIDTH                         8
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK                           0x7u
+#define I2C_C2_AD_SHIFT                          0
+#define I2C_C2_AD_WIDTH                          3
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         0x8u
+#define I2C_C2_RMEN_SHIFT                        3
+#define I2C_C2_RMEN_WIDTH                        1
+#define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_RMEN_SHIFT))&I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK                         0x10u
+#define I2C_C2_SBRC_SHIFT                        4
+#define I2C_C2_SBRC_WIDTH                        1
+#define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_SBRC_SHIFT))&I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK                         0x20u
+#define I2C_C2_HDRS_SHIFT                        5
+#define I2C_C2_HDRS_WIDTH                        1
+#define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_HDRS_SHIFT))&I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK                        0x40u
+#define I2C_C2_ADEXT_SHIFT                       6
+#define I2C_C2_ADEXT_WIDTH                       1
+#define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_ADEXT_SHIFT))&I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK                        0x80u
+#define I2C_C2_GCAEN_SHIFT                       7
+#define I2C_C2_GCAEN_WIDTH                       1
+#define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_GCAEN_SHIFT))&I2C_C2_GCAEN_MASK)
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK                         0xFu
+#define I2C_FLT_FLT_SHIFT                        0
+#define I2C_FLT_FLT_WIDTH                        4
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK                      0x10u
+#define I2C_FLT_STARTF_SHIFT                     4
+#define I2C_FLT_STARTF_WIDTH                     1
+#define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STARTF_SHIFT))&I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK                        0x20u
+#define I2C_FLT_SSIE_SHIFT                       5
+#define I2C_FLT_SSIE_WIDTH                       1
+#define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SSIE_SHIFT))&I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK                       0x40u
+#define I2C_FLT_STOPF_SHIFT                      6
+#define I2C_FLT_STOPF_WIDTH                      1
+#define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STOPF_SHIFT))&I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK                        0x80u
+#define I2C_FLT_SHEN_SHIFT                       7
+#define I2C_FLT_SHEN_WIDTH                       1
+#define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SHEN_SHIFT))&I2C_FLT_SHEN_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK                          0xFEu
+#define I2C_RA_RAD_SHIFT                         1
+#define I2C_RA_RAD_WIDTH                         7
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK                     0x1u
+#define I2C_SMB_SHTF2IE_SHIFT                    0
+#define I2C_SMB_SHTF2IE_WIDTH                    1
+#define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2IE_SHIFT))&I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK                       0x2u
+#define I2C_SMB_SHTF2_SHIFT                      1
+#define I2C_SMB_SHTF2_WIDTH                      1
+#define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2_SHIFT))&I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK                       0x4u
+#define I2C_SMB_SHTF1_SHIFT                      2
+#define I2C_SMB_SHTF1_WIDTH                      1
+#define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF1_SHIFT))&I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK                        0x8u
+#define I2C_SMB_SLTF_SHIFT                       3
+#define I2C_SMB_SLTF_WIDTH                       1
+#define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SLTF_SHIFT))&I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK                      0x10u
+#define I2C_SMB_TCKSEL_SHIFT                     4
+#define I2C_SMB_TCKSEL_WIDTH                     1
+#define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_SMB_TCKSEL_SHIFT))&I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK                     0x20u
+#define I2C_SMB_SIICAEN_SHIFT                    5
+#define I2C_SMB_SIICAEN_WIDTH                    1
+#define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SIICAEN_SHIFT))&I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK                     0x40u
+#define I2C_SMB_ALERTEN_SHIFT                    6
+#define I2C_SMB_ALERTEN_WIDTH                    1
+#define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_ALERTEN_SHIFT))&I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK                        0x80u
+#define I2C_SMB_FACK_SHIFT                       7
+#define I2C_SMB_FACK_WIDTH                       1
+#define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_FACK_SHIFT))&I2C_SMB_FACK_MASK)
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK                          0xFEu
+#define I2C_A2_SAD_SHIFT                         1
+#define I2C_A2_SAD_WIDTH                         7
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK                       0xFFu
+#define I2C_SLTH_SSLT_SHIFT                      0
+#define I2C_SLTH_SSLT_WIDTH                      8
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK                       0xFFu
+#define I2C_SLTL_SSLT_SHIFT                      0
+#define I2C_SLTL_SSLT_WIDTH                      8
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR                            (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR                            (I2C1)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x400E6000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+#define I2C2_BASE_PTR                            (I2C2)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1                                  I2C_A1_REG(I2C0)
+#define I2C0_F                                   I2C_F_REG(I2C0)
+#define I2C0_C1                                  I2C_C1_REG(I2C0)
+#define I2C0_S                                   I2C_S_REG(I2C0)
+#define I2C0_D                                   I2C_D_REG(I2C0)
+#define I2C0_C2                                  I2C_C2_REG(I2C0)
+#define I2C0_FLT                                 I2C_FLT_REG(I2C0)
+#define I2C0_RA                                  I2C_RA_REG(I2C0)
+#define I2C0_SMB                                 I2C_SMB_REG(I2C0)
+#define I2C0_A2                                  I2C_A2_REG(I2C0)
+#define I2C0_SLTH                                I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL                                I2C_SLTL_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1                                  I2C_A1_REG(I2C1)
+#define I2C1_F                                   I2C_F_REG(I2C1)
+#define I2C1_C1                                  I2C_C1_REG(I2C1)
+#define I2C1_S                                   I2C_S_REG(I2C1)
+#define I2C1_D                                   I2C_D_REG(I2C1)
+#define I2C1_C2                                  I2C_C2_REG(I2C1)
+#define I2C1_FLT                                 I2C_FLT_REG(I2C1)
+#define I2C1_RA                                  I2C_RA_REG(I2C1)
+#define I2C1_SMB                                 I2C_SMB_REG(I2C1)
+#define I2C1_A2                                  I2C_A2_REG(I2C1)
+#define I2C1_SLTH                                I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL                                I2C_SLTL_REG(I2C1)
+/* I2C2 */
+#define I2C2_A1                                  I2C_A1_REG(I2C2)
+#define I2C2_F                                   I2C_F_REG(I2C2)
+#define I2C2_C1                                  I2C_C1_REG(I2C2)
+#define I2C2_S                                   I2C_S_REG(I2C2)
+#define I2C2_D                                   I2C_D_REG(I2C2)
+#define I2C2_C2                                  I2C_C2_REG(I2C2)
+#define I2C2_FLT                                 I2C_FLT_REG(I2C2)
+#define I2C2_RA                                  I2C_RA_REG(I2C2)
+#define I2C2_SMB                                 I2C_SMB_REG(I2C2)
+#define I2C2_A2                                  I2C_A2_REG(I2C2)
+#define I2C2_SLTH                                I2C_SLTH_REG(I2C2)
+#define I2C2_SLTL                                I2C_SLTL_REG(I2C2)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
+  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t TDR[2];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __I  uint32_t TFR[2];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_3[28];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
+  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t RDR[2];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[24];
+  __I  uint32_t RFR[2];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_6[24];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
+  __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base)                       ((base)->TCSR)
+#define I2S_TCR1_REG(base)                       ((base)->TCR1)
+#define I2S_TCR2_REG(base)                       ((base)->TCR2)
+#define I2S_TCR3_REG(base)                       ((base)->TCR3)
+#define I2S_TCR4_REG(base)                       ((base)->TCR4)
+#define I2S_TCR5_REG(base)                       ((base)->TCR5)
+#define I2S_TDR_REG(base,index)                  ((base)->TDR[index])
+#define I2S_TDR_COUNT                            2
+#define I2S_TFR_REG(base,index)                  ((base)->TFR[index])
+#define I2S_TFR_COUNT                            2
+#define I2S_TMR_REG(base)                        ((base)->TMR)
+#define I2S_RCSR_REG(base)                       ((base)->RCSR)
+#define I2S_RCR1_REG(base)                       ((base)->RCR1)
+#define I2S_RCR2_REG(base)                       ((base)->RCR2)
+#define I2S_RCR3_REG(base)                       ((base)->RCR3)
+#define I2S_RCR4_REG(base)                       ((base)->RCR4)
+#define I2S_RCR5_REG(base)                       ((base)->RCR5)
+#define I2S_RDR_REG(base,index)                  ((base)->RDR[index])
+#define I2S_RDR_COUNT                            2
+#define I2S_RFR_REG(base,index)                  ((base)->RFR[index])
+#define I2S_RFR_COUNT                            2
+#define I2S_RMR_REG(base)                        ((base)->RMR)
+#define I2S_MCR_REG(base)                        ((base)->MCR)
+#define I2S_MDR_REG(base)                        ((base)->MDR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK                       0x1u
+#define I2S_TCSR_FRDE_SHIFT                      0
+#define I2S_TCSR_FRDE_WIDTH                      1
+#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRDE_SHIFT))&I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK                       0x2u
+#define I2S_TCSR_FWDE_SHIFT                      1
+#define I2S_TCSR_FWDE_WIDTH                      1
+#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK                       0x100u
+#define I2S_TCSR_FRIE_SHIFT                      8
+#define I2S_TCSR_FRIE_WIDTH                      1
+#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRIE_SHIFT))&I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK                       0x200u
+#define I2S_TCSR_FWIE_SHIFT                      9
+#define I2S_TCSR_FWIE_WIDTH                      1
+#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK                       0x400u
+#define I2S_TCSR_FEIE_SHIFT                      10
+#define I2S_TCSR_FEIE_WIDTH                      1
+#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK                       0x800u
+#define I2S_TCSR_SEIE_SHIFT                      11
+#define I2S_TCSR_SEIE_WIDTH                      1
+#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK                       0x1000u
+#define I2S_TCSR_WSIE_SHIFT                      12
+#define I2S_TCSR_WSIE_WIDTH                      1
+#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK                        0x10000u
+#define I2S_TCSR_FRF_SHIFT                       16
+#define I2S_TCSR_FRF_WIDTH                       1
+#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRF_SHIFT))&I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK                        0x20000u
+#define I2S_TCSR_FWF_SHIFT                       17
+#define I2S_TCSR_FWF_WIDTH                       1
+#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK                        0x40000u
+#define I2S_TCSR_FEF_SHIFT                       18
+#define I2S_TCSR_FEF_WIDTH                       1
+#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK                        0x80000u
+#define I2S_TCSR_SEF_SHIFT                       19
+#define I2S_TCSR_SEF_WIDTH                       1
+#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK                        0x100000u
+#define I2S_TCSR_WSF_SHIFT                       20
+#define I2S_TCSR_WSF_WIDTH                       1
+#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK                         0x1000000u
+#define I2S_TCSR_SR_SHIFT                        24
+#define I2S_TCSR_SR_WIDTH                        1
+#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK                         0x2000000u
+#define I2S_TCSR_FR_SHIFT                        25
+#define I2S_TCSR_FR_WIDTH                        1
+#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK                        0x10000000u
+#define I2S_TCSR_BCE_SHIFT                       28
+#define I2S_TCSR_BCE_WIDTH                       1
+#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK                       0x20000000u
+#define I2S_TCSR_DBGE_SHIFT                      29
+#define I2S_TCSR_DBGE_WIDTH                      1
+#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK                      0x40000000u
+#define I2S_TCSR_STOPE_SHIFT                     30
+#define I2S_TCSR_STOPE_WIDTH                     1
+#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK                         0x80000000u
+#define I2S_TCSR_TE_SHIFT                        31
+#define I2S_TCSR_TE_WIDTH                        1
+#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK                        0x7u
+#define I2S_TCR1_TFW_SHIFT                       0
+#define I2S_TCR1_TFW_WIDTH                       3
+#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK                        0xFFu
+#define I2S_TCR2_DIV_SHIFT                       0
+#define I2S_TCR2_DIV_WIDTH                       8
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        0x1000000u
+#define I2S_TCR2_BCD_SHIFT                       24
+#define I2S_TCR2_BCD_WIDTH                       1
+#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK                        0x2000000u
+#define I2S_TCR2_BCP_SHIFT                       25
+#define I2S_TCR2_BCP_WIDTH                       1
+#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK                       0xC000000u
+#define I2S_TCR2_MSEL_SHIFT                      26
+#define I2S_TCR2_MSEL_WIDTH                      2
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK                        0x10000000u
+#define I2S_TCR2_BCI_SHIFT                       28
+#define I2S_TCR2_BCI_WIDTH                       1
+#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK                        0x20000000u
+#define I2S_TCR2_BCS_SHIFT                       29
+#define I2S_TCR2_BCS_WIDTH                       1
+#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK                       0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT                      30
+#define I2S_TCR2_SYNC_WIDTH                      2
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK                       0x1Fu
+#define I2S_TCR3_WDFL_SHIFT                      0
+#define I2S_TCR3_WDFL_WIDTH                      5
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        0x30000u
+#define I2S_TCR3_TCE_SHIFT                       16
+#define I2S_TCR3_TCE_WIDTH                       2
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK                        0x1u
+#define I2S_TCR4_FSD_SHIFT                       0
+#define I2S_TCR4_FSD_WIDTH                       1
+#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK                        0x2u
+#define I2S_TCR4_FSP_SHIFT                       1
+#define I2S_TCR4_FSP_WIDTH                       1
+#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSE_MASK                        0x8u
+#define I2S_TCR4_FSE_SHIFT                       3
+#define I2S_TCR4_FSE_WIDTH                       1
+#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK                         0x10u
+#define I2S_TCR4_MF_SHIFT                        4
+#define I2S_TCR4_MF_WIDTH                        1
+#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK                       0x1F00u
+#define I2S_TCR4_SYWD_SHIFT                      8
+#define I2S_TCR4_SYWD_WIDTH                      5
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT                      16
+#define I2S_TCR4_FRSZ_WIDTH                      5
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK                        0x1F00u
+#define I2S_TCR5_FBT_SHIFT                       8
+#define I2S_TCR5_FBT_WIDTH                       5
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        0x1F0000u
+#define I2S_TCR5_W0W_SHIFT                       16
+#define I2S_TCR5_W0W_WIDTH                       5
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        0x1F000000u
+#define I2S_TCR5_WNW_SHIFT                       24
+#define I2S_TCR5_WNW_WIDTH                       5
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT                        0
+#define I2S_TDR_TDR_WIDTH                        32
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK                         0xFu
+#define I2S_TFR_RFP_SHIFT                        0
+#define I2S_TFR_RFP_WIDTH                        4
+#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK                         0xF0000u
+#define I2S_TFR_WFP_SHIFT                        16
+#define I2S_TFR_WFP_WIDTH                        4
+#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK                         0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT                        0
+#define I2S_TMR_TWM_WIDTH                        32
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK                       0x1u
+#define I2S_RCSR_FRDE_SHIFT                      0
+#define I2S_RCSR_FRDE_WIDTH                      1
+#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRDE_SHIFT))&I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK                       0x2u
+#define I2S_RCSR_FWDE_SHIFT                      1
+#define I2S_RCSR_FWDE_WIDTH                      1
+#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK                       0x100u
+#define I2S_RCSR_FRIE_SHIFT                      8
+#define I2S_RCSR_FRIE_WIDTH                      1
+#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRIE_SHIFT))&I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK                       0x200u
+#define I2S_RCSR_FWIE_SHIFT                      9
+#define I2S_RCSR_FWIE_WIDTH                      1
+#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK                       0x400u
+#define I2S_RCSR_FEIE_SHIFT                      10
+#define I2S_RCSR_FEIE_WIDTH                      1
+#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK                       0x800u
+#define I2S_RCSR_SEIE_SHIFT                      11
+#define I2S_RCSR_SEIE_WIDTH                      1
+#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK                       0x1000u
+#define I2S_RCSR_WSIE_SHIFT                      12
+#define I2S_RCSR_WSIE_WIDTH                      1
+#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK                        0x10000u
+#define I2S_RCSR_FRF_SHIFT                       16
+#define I2S_RCSR_FRF_WIDTH                       1
+#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRF_SHIFT))&I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK                        0x20000u
+#define I2S_RCSR_FWF_SHIFT                       17
+#define I2S_RCSR_FWF_WIDTH                       1
+#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK                        0x40000u
+#define I2S_RCSR_FEF_SHIFT                       18
+#define I2S_RCSR_FEF_WIDTH                       1
+#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK                        0x80000u
+#define I2S_RCSR_SEF_SHIFT                       19
+#define I2S_RCSR_SEF_WIDTH                       1
+#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK                        0x100000u
+#define I2S_RCSR_WSF_SHIFT                       20
+#define I2S_RCSR_WSF_WIDTH                       1
+#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK                         0x1000000u
+#define I2S_RCSR_SR_SHIFT                        24
+#define I2S_RCSR_SR_WIDTH                        1
+#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK                         0x2000000u
+#define I2S_RCSR_FR_SHIFT                        25
+#define I2S_RCSR_FR_WIDTH                        1
+#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK                        0x10000000u
+#define I2S_RCSR_BCE_SHIFT                       28
+#define I2S_RCSR_BCE_WIDTH                       1
+#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK                       0x20000000u
+#define I2S_RCSR_DBGE_SHIFT                      29
+#define I2S_RCSR_DBGE_WIDTH                      1
+#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK                      0x40000000u
+#define I2S_RCSR_STOPE_SHIFT                     30
+#define I2S_RCSR_STOPE_WIDTH                     1
+#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK                         0x80000000u
+#define I2S_RCSR_RE_SHIFT                        31
+#define I2S_RCSR_RE_WIDTH                        1
+#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK                        0x7u
+#define I2S_RCR1_RFW_SHIFT                       0
+#define I2S_RCR1_RFW_WIDTH                       3
+#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK                        0xFFu
+#define I2S_RCR2_DIV_SHIFT                       0
+#define I2S_RCR2_DIV_WIDTH                       8
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        0x1000000u
+#define I2S_RCR2_BCD_SHIFT                       24
+#define I2S_RCR2_BCD_WIDTH                       1
+#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK                        0x2000000u
+#define I2S_RCR2_BCP_SHIFT                       25
+#define I2S_RCR2_BCP_WIDTH                       1
+#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK                       0xC000000u
+#define I2S_RCR2_MSEL_SHIFT                      26
+#define I2S_RCR2_MSEL_WIDTH                      2
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK                        0x10000000u
+#define I2S_RCR2_BCI_SHIFT                       28
+#define I2S_RCR2_BCI_WIDTH                       1
+#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK                        0x20000000u
+#define I2S_RCR2_BCS_SHIFT                       29
+#define I2S_RCR2_BCS_WIDTH                       1
+#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK                       0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT                      30
+#define I2S_RCR2_SYNC_WIDTH                      2
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK                       0x1Fu
+#define I2S_RCR3_WDFL_SHIFT                      0
+#define I2S_RCR3_WDFL_WIDTH                      5
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        0x30000u
+#define I2S_RCR3_RCE_SHIFT                       16
+#define I2S_RCR3_RCE_WIDTH                       2
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK                        0x1u
+#define I2S_RCR4_FSD_SHIFT                       0
+#define I2S_RCR4_FSD_WIDTH                       1
+#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK                        0x2u
+#define I2S_RCR4_FSP_SHIFT                       1
+#define I2S_RCR4_FSP_WIDTH                       1
+#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSE_MASK                        0x8u
+#define I2S_RCR4_FSE_SHIFT                       3
+#define I2S_RCR4_FSE_WIDTH                       1
+#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK                         0x10u
+#define I2S_RCR4_MF_SHIFT                        4
+#define I2S_RCR4_MF_WIDTH                        1
+#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK                       0x1F00u
+#define I2S_RCR4_SYWD_SHIFT                      8
+#define I2S_RCR4_SYWD_WIDTH                      5
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT                      16
+#define I2S_RCR4_FRSZ_WIDTH                      5
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK                        0x1F00u
+#define I2S_RCR5_FBT_SHIFT                       8
+#define I2S_RCR5_FBT_WIDTH                       5
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        0x1F0000u
+#define I2S_RCR5_W0W_SHIFT                       16
+#define I2S_RCR5_W0W_WIDTH                       5
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        0x1F000000u
+#define I2S_RCR5_WNW_SHIFT                       24
+#define I2S_RCR5_WNW_WIDTH                       5
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT                        0
+#define I2S_RDR_RDR_WIDTH                        32
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK                         0xFu
+#define I2S_RFR_RFP_SHIFT                        0
+#define I2S_RFR_RFP_WIDTH                        4
+#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK                         0xF0000u
+#define I2S_RFR_WFP_SHIFT                        16
+#define I2S_RFR_WFP_WIDTH                        4
+#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK                         0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT                        0
+#define I2S_RMR_RWM_WIDTH                        32
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK                        0x3000000u
+#define I2S_MCR_MICS_SHIFT                       24
+#define I2S_MCR_MICS_WIDTH                       2
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK                         0x40000000u
+#define I2S_MCR_MOE_SHIFT                        30
+#define I2S_MCR_MOE_WIDTH                        1
+#define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MOE_SHIFT))&I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK                         0x80000000u
+#define I2S_MCR_DUF_SHIFT                        31
+#define I2S_MCR_DUF_WIDTH                        1
+#define I2S_MCR_DUF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_DUF_SHIFT))&I2S_MCR_DUF_MASK)
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK                      0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT                     0
+#define I2S_MDR_DIVIDE_WIDTH                     12
+#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK                       0xFF000u
+#define I2S_MDR_FRACT_SHIFT                      12
+#define I2S_MDR_FRACT_WIDTH                      8
+#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR                            (I2S0)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS                              { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS                              { I2S0_Tx_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR                                I2S_TCSR_REG(I2S0)
+#define I2S0_TCR1                                I2S_TCR1_REG(I2S0)
+#define I2S0_TCR2                                I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3                                I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4                                I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5                                I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0                                I2S_TDR_REG(I2S0,0)
+#define I2S0_TDR1                                I2S_TDR_REG(I2S0,1)
+#define I2S0_TFR0                                I2S_TFR_REG(I2S0,0)
+#define I2S0_TFR1                                I2S_TFR_REG(I2S0,1)
+#define I2S0_TMR                                 I2S_TMR_REG(I2S0)
+#define I2S0_RCSR                                I2S_RCSR_REG(I2S0)
+#define I2S0_RCR1                                I2S_RCR1_REG(I2S0)
+#define I2S0_RCR2                                I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3                                I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4                                I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5                                I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0                                I2S_RDR_REG(I2S0,0)
+#define I2S0_RDR1                                I2S_RDR_REG(I2S0,1)
+#define I2S0_RFR0                                I2S_RFR_REG(I2S0,0)
+#define I2S0_RFR1                                I2S_RFR_REG(I2S0,1)
+#define I2S0_RMR                                 I2S_RMR_REG(I2S0)
+#define I2S0_MCR                                 I2S_MCR_REG(I2S0)
+#define I2S0_MDR                                 I2S_MDR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index)                          I2S_TDR_REG(I2S0,index)
+#define I2S0_TFR(index)                          I2S_TFR_REG(I2S0,index)
+#define I2S0_RDR(index)                          I2S_RDR_REG(I2S0,index)
+#define I2S0_RFR(index)                          I2S_RFR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
+  __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
+  __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
+  __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
+  __IO uint8_t RST;                                /**< LLWU Reset Enable register, offset: 0xA */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base)                       ((base)->PE1)
+#define LLWU_PE2_REG(base)                       ((base)->PE2)
+#define LLWU_PE3_REG(base)                       ((base)->PE3)
+#define LLWU_PE4_REG(base)                       ((base)->PE4)
+#define LLWU_ME_REG(base)                        ((base)->ME)
+#define LLWU_F1_REG(base)                        ((base)->F1)
+#define LLWU_F2_REG(base)                        ((base)->F2)
+#define LLWU_F3_REG(base)                        ((base)->F3)
+#define LLWU_FILT1_REG(base)                     ((base)->FILT1)
+#define LLWU_FILT2_REG(base)                     ((base)->FILT2)
+#define LLWU_RST_REG(base)                       ((base)->RST)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK                      0x3u
+#define LLWU_PE1_WUPE0_SHIFT                     0
+#define LLWU_PE1_WUPE0_WIDTH                     2
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      0xCu
+#define LLWU_PE1_WUPE1_SHIFT                     2
+#define LLWU_PE1_WUPE1_WIDTH                     2
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      0x30u
+#define LLWU_PE1_WUPE2_SHIFT                     4
+#define LLWU_PE1_WUPE2_WIDTH                     2
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      0xC0u
+#define LLWU_PE1_WUPE3_SHIFT                     6
+#define LLWU_PE1_WUPE3_WIDTH                     2
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK                      0x3u
+#define LLWU_PE2_WUPE4_SHIFT                     0
+#define LLWU_PE2_WUPE4_WIDTH                     2
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      0xCu
+#define LLWU_PE2_WUPE5_SHIFT                     2
+#define LLWU_PE2_WUPE5_WIDTH                     2
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      0x30u
+#define LLWU_PE2_WUPE6_SHIFT                     4
+#define LLWU_PE2_WUPE6_WIDTH                     2
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      0xC0u
+#define LLWU_PE2_WUPE7_SHIFT                     6
+#define LLWU_PE2_WUPE7_WIDTH                     2
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK                      0x3u
+#define LLWU_PE3_WUPE8_SHIFT                     0
+#define LLWU_PE3_WUPE8_WIDTH                     2
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      0xCu
+#define LLWU_PE3_WUPE9_SHIFT                     2
+#define LLWU_PE3_WUPE9_WIDTH                     2
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     0x30u
+#define LLWU_PE3_WUPE10_SHIFT                    4
+#define LLWU_PE3_WUPE10_WIDTH                    2
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     0xC0u
+#define LLWU_PE3_WUPE11_SHIFT                    6
+#define LLWU_PE3_WUPE11_WIDTH                    2
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK                     0x3u
+#define LLWU_PE4_WUPE12_SHIFT                    0
+#define LLWU_PE4_WUPE12_WIDTH                    2
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     0xCu
+#define LLWU_PE4_WUPE13_SHIFT                    2
+#define LLWU_PE4_WUPE13_WIDTH                    2
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     0x30u
+#define LLWU_PE4_WUPE14_SHIFT                    4
+#define LLWU_PE4_WUPE14_WIDTH                    2
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     0xC0u
+#define LLWU_PE4_WUPE15_SHIFT                    6
+#define LLWU_PE4_WUPE15_WIDTH                    2
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK                       0x1u
+#define LLWU_ME_WUME0_SHIFT                      0
+#define LLWU_ME_WUME0_WIDTH                      1
+#define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK                       0x2u
+#define LLWU_ME_WUME1_SHIFT                      1
+#define LLWU_ME_WUME1_WIDTH                      1
+#define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK                       0x4u
+#define LLWU_ME_WUME2_SHIFT                      2
+#define LLWU_ME_WUME2_WIDTH                      1
+#define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK                       0x8u
+#define LLWU_ME_WUME3_SHIFT                      3
+#define LLWU_ME_WUME3_WIDTH                      1
+#define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK                       0x10u
+#define LLWU_ME_WUME4_SHIFT                      4
+#define LLWU_ME_WUME4_WIDTH                      1
+#define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK                       0x20u
+#define LLWU_ME_WUME5_SHIFT                      5
+#define LLWU_ME_WUME5_WIDTH                      1
+#define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK                       0x40u
+#define LLWU_ME_WUME6_SHIFT                      6
+#define LLWU_ME_WUME6_WIDTH                      1
+#define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK                       0x80u
+#define LLWU_ME_WUME7_SHIFT                      7
+#define LLWU_ME_WUME7_WIDTH                      1
+#define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK                        0x1u
+#define LLWU_F1_WUF0_SHIFT                       0
+#define LLWU_F1_WUF0_WIDTH                       1
+#define LLWU_F1_WUF0(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF0_SHIFT))&LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK                        0x2u
+#define LLWU_F1_WUF1_SHIFT                       1
+#define LLWU_F1_WUF1_WIDTH                       1
+#define LLWU_F1_WUF1(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF1_SHIFT))&LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK                        0x4u
+#define LLWU_F1_WUF2_SHIFT                       2
+#define LLWU_F1_WUF2_WIDTH                       1
+#define LLWU_F1_WUF2(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF2_SHIFT))&LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK                        0x8u
+#define LLWU_F1_WUF3_SHIFT                       3
+#define LLWU_F1_WUF3_WIDTH                       1
+#define LLWU_F1_WUF3(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF3_SHIFT))&LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK                        0x10u
+#define LLWU_F1_WUF4_SHIFT                       4
+#define LLWU_F1_WUF4_WIDTH                       1
+#define LLWU_F1_WUF4(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF4_SHIFT))&LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK                        0x20u
+#define LLWU_F1_WUF5_SHIFT                       5
+#define LLWU_F1_WUF5_WIDTH                       1
+#define LLWU_F1_WUF5(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF5_SHIFT))&LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK                        0x40u
+#define LLWU_F1_WUF6_SHIFT                       6
+#define LLWU_F1_WUF6_WIDTH                       1
+#define LLWU_F1_WUF6(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF6_SHIFT))&LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK                        0x80u
+#define LLWU_F1_WUF7_SHIFT                       7
+#define LLWU_F1_WUF7_WIDTH                       1
+#define LLWU_F1_WUF7(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF7_SHIFT))&LLWU_F1_WUF7_MASK)
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK                        0x1u
+#define LLWU_F2_WUF8_SHIFT                       0
+#define LLWU_F2_WUF8_WIDTH                       1
+#define LLWU_F2_WUF8(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF8_SHIFT))&LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK                        0x2u
+#define LLWU_F2_WUF9_SHIFT                       1
+#define LLWU_F2_WUF9_WIDTH                       1
+#define LLWU_F2_WUF9(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF9_SHIFT))&LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK                       0x4u
+#define LLWU_F2_WUF10_SHIFT                      2
+#define LLWU_F2_WUF10_WIDTH                      1
+#define LLWU_F2_WUF10(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF10_SHIFT))&LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK                       0x8u
+#define LLWU_F2_WUF11_SHIFT                      3
+#define LLWU_F2_WUF11_WIDTH                      1
+#define LLWU_F2_WUF11(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF11_SHIFT))&LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK                       0x10u
+#define LLWU_F2_WUF12_SHIFT                      4
+#define LLWU_F2_WUF12_WIDTH                      1
+#define LLWU_F2_WUF12(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF12_SHIFT))&LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK                       0x20u
+#define LLWU_F2_WUF13_SHIFT                      5
+#define LLWU_F2_WUF13_WIDTH                      1
+#define LLWU_F2_WUF13(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF13_SHIFT))&LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK                       0x40u
+#define LLWU_F2_WUF14_SHIFT                      6
+#define LLWU_F2_WUF14_WIDTH                      1
+#define LLWU_F2_WUF14(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF14_SHIFT))&LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK                       0x80u
+#define LLWU_F2_WUF15_SHIFT                      7
+#define LLWU_F2_WUF15_WIDTH                      1
+#define LLWU_F2_WUF15(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF15_SHIFT))&LLWU_F2_WUF15_MASK)
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK                       0x1u
+#define LLWU_F3_MWUF0_SHIFT                      0
+#define LLWU_F3_MWUF0_WIDTH                      1
+#define LLWU_F3_MWUF0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF0_SHIFT))&LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK                       0x2u
+#define LLWU_F3_MWUF1_SHIFT                      1
+#define LLWU_F3_MWUF1_WIDTH                      1
+#define LLWU_F3_MWUF1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF1_SHIFT))&LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK                       0x4u
+#define LLWU_F3_MWUF2_SHIFT                      2
+#define LLWU_F3_MWUF2_WIDTH                      1
+#define LLWU_F3_MWUF2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF2_SHIFT))&LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK                       0x8u
+#define LLWU_F3_MWUF3_SHIFT                      3
+#define LLWU_F3_MWUF3_WIDTH                      1
+#define LLWU_F3_MWUF3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF3_SHIFT))&LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK                       0x10u
+#define LLWU_F3_MWUF4_SHIFT                      4
+#define LLWU_F3_MWUF4_WIDTH                      1
+#define LLWU_F3_MWUF4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF4_SHIFT))&LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK                       0x20u
+#define LLWU_F3_MWUF5_SHIFT                      5
+#define LLWU_F3_MWUF5_WIDTH                      1
+#define LLWU_F3_MWUF5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF5_SHIFT))&LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK                       0x40u
+#define LLWU_F3_MWUF6_SHIFT                      6
+#define LLWU_F3_MWUF6_WIDTH                      1
+#define LLWU_F3_MWUF6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF6_SHIFT))&LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK                       0x80u
+#define LLWU_F3_MWUF7_SHIFT                      7
+#define LLWU_F3_MWUF7_WIDTH                      1
+#define LLWU_F3_MWUF7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF7_SHIFT))&LLWU_F3_MWUF7_MASK)
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK                  0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT                 0
+#define LLWU_FILT1_FILTSEL_WIDTH                 4
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    0x60u
+#define LLWU_FILT1_FILTE_SHIFT                   5
+#define LLWU_FILT1_FILTE_WIDTH                   2
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK                    0x80u
+#define LLWU_FILT1_FILTF_SHIFT                   7
+#define LLWU_FILT1_FILTF_WIDTH                   1
+#define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK                  0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT                 0
+#define LLWU_FILT2_FILTSEL_WIDTH                 4
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    0x60u
+#define LLWU_FILT2_FILTE_SHIFT                   5
+#define LLWU_FILT2_FILTE_WIDTH                   2
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK                    0x80u
+#define LLWU_FILT2_FILTF_SHIFT                   7
+#define LLWU_FILT2_FILTF_WIDTH                   1
+#define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK                    0x1u
+#define LLWU_RST_RSTFILT_SHIFT                   0
+#define LLWU_RST_RSTFILT_WIDTH                   1
+#define LLWU_RST_RSTFILT(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_RST_RSTFILT_SHIFT))&LLWU_RST_RSTFILT_MASK)
+#define LLWU_RST_LLRSTE_MASK                     0x2u
+#define LLWU_RST_LLRSTE_SHIFT                    1
+#define LLWU_RST_LLRSTE_WIDTH                    1
+#define LLWU_RST_LLRSTE(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_RST_LLRSTE_SHIFT))&LLWU_RST_LLRSTE_MASK)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR                            (LLWU)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1                                 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2                                 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3                                 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4                                 LLWU_PE4_REG(LLWU)
+#define LLWU_ME                                  LLWU_ME_REG(LLWU)
+#define LLWU_F1                                  LLWU_F1_REG(LLWU)
+#define LLWU_F2                                  LLWU_F2_REG(LLWU)
+#define LLWU_F3                                  LLWU_F3_REG(LLWU)
+#define LLWU_FILT1                               LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2                               LLWU_FILT2_REG(LLWU)
+#define LLWU_RST                                 LLWU_RST_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base)                      ((base)->CSR)
+#define LPTMR_PSR_REG(base)                      ((base)->PSR)
+#define LPTMR_CMR_REG(base)                      ((base)->CMR)
+#define LPTMR_CNR_REG(base)                      ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK                       0x1u
+#define LPTMR_CSR_TEN_SHIFT                      0
+#define LPTMR_CSR_TEN_WIDTH                      1
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK                       0x2u
+#define LPTMR_CSR_TMS_SHIFT                      1
+#define LPTMR_CSR_TMS_WIDTH                      1
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK                       0x4u
+#define LPTMR_CSR_TFC_SHIFT                      2
+#define LPTMR_CSR_TFC_WIDTH                      1
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK                       0x8u
+#define LPTMR_CSR_TPP_SHIFT                      3
+#define LPTMR_CSR_TPP_WIDTH                      1
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK                       0x30u
+#define LPTMR_CSR_TPS_SHIFT                      4
+#define LPTMR_CSR_TPS_WIDTH                      2
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       0x40u
+#define LPTMR_CSR_TIE_SHIFT                      6
+#define LPTMR_CSR_TIE_WIDTH                      1
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK                       0x80u
+#define LPTMR_CSR_TCF_SHIFT                      7
+#define LPTMR_CSR_TCF_WIDTH                      1
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK                       0x3u
+#define LPTMR_PSR_PCS_SHIFT                      0
+#define LPTMR_PSR_PCS_WIDTH                      2
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      0x4u
+#define LPTMR_PSR_PBYP_SHIFT                     2
+#define LPTMR_PSR_PBYP_WIDTH                     1
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK                  0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT                 3
+#define LPTMR_PSR_PRESCALE_WIDTH                 4
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT                  0
+#define LPTMR_CMR_COMPARE_WIDTH                  16
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT                  0
+#define LPTMR_CNR_COUNTER_WIDTH                  16
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR                          (LPTMR0)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR                               LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR                               LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR                               LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR                               LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
+  __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
+  __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
+  __IO uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+  __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+  __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
+  __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base)                         ((base)->C1)
+#define MCG_C2_REG(base)                         ((base)->C2)
+#define MCG_C3_REG(base)                         ((base)->C3)
+#define MCG_C4_REG(base)                         ((base)->C4)
+#define MCG_C5_REG(base)                         ((base)->C5)
+#define MCG_C6_REG(base)                         ((base)->C6)
+#define MCG_S_REG(base)                          ((base)->S)
+#define MCG_SC_REG(base)                         ((base)->SC)
+#define MCG_ATCVH_REG(base)                      ((base)->ATCVH)
+#define MCG_ATCVL_REG(base)                      ((base)->ATCVL)
+#define MCG_C7_REG(base)                         ((base)->C7)
+#define MCG_C8_REG(base)                         ((base)->C8)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK                     0x1u
+#define MCG_C1_IREFSTEN_SHIFT                    0
+#define MCG_C1_IREFSTEN_WIDTH                    1
+#define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK                      0x2u
+#define MCG_C1_IRCLKEN_SHIFT                     1
+#define MCG_C1_IRCLKEN_WIDTH                     1
+#define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK                        0x4u
+#define MCG_C1_IREFS_SHIFT                       2
+#define MCG_C1_IREFS_WIDTH                       1
+#define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFS_SHIFT))&MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK                        0x38u
+#define MCG_C1_FRDIV_SHIFT                       3
+#define MCG_C1_FRDIV_WIDTH                       3
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         0xC0u
+#define MCG_C1_CLKS_SHIFT                        6
+#define MCG_C1_CLKS_WIDTH                        2
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK                         0x1u
+#define MCG_C2_IRCS_SHIFT                        0
+#define MCG_C2_IRCS_WIDTH                        1
+#define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK                           0x2u
+#define MCG_C2_LP_SHIFT                          1
+#define MCG_C2_LP_WIDTH                          1
+#define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x))<<MCG_C2_LP_SHIFT))&MCG_C2_LP_MASK)
+#define MCG_C2_EREFS_MASK                        0x4u
+#define MCG_C2_EREFS_SHIFT                       2
+#define MCG_C2_EREFS_WIDTH                       1
+#define MCG_C2_EREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS_SHIFT))&MCG_C2_EREFS_MASK)
+#define MCG_C2_HGO_MASK                          0x8u
+#define MCG_C2_HGO_SHIFT                         3
+#define MCG_C2_HGO_WIDTH                         1
+#define MCG_C2_HGO(x)                            (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO_SHIFT))&MCG_C2_HGO_MASK)
+#define MCG_C2_RANGE_MASK                        0x30u
+#define MCG_C2_RANGE_SHIFT                       4
+#define MCG_C2_RANGE_WIDTH                       2
+#define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK                      0x40u
+#define MCG_C2_FCFTRIM_SHIFT                     6
+#define MCG_C2_FCFTRIM_WIDTH                     1
+#define MCG_C2_FCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C2_FCFTRIM_SHIFT))&MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK                       0x80u
+#define MCG_C2_LOCRE0_SHIFT                      7
+#define MCG_C2_LOCRE0_WIDTH                      1
+#define MCG_C2_LOCRE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_LOCRE0_SHIFT))&MCG_C2_LOCRE0_MASK)
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK                       0xFFu
+#define MCG_C3_SCTRIM_SHIFT                      0
+#define MCG_C3_SCTRIM_WIDTH                      8
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK                      0x1u
+#define MCG_C4_SCFTRIM_SHIFT                     0
+#define MCG_C4_SCFTRIM_WIDTH                     1
+#define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C4_SCFTRIM_SHIFT))&MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK                       0x1Eu
+#define MCG_C4_FCTRIM_SHIFT                      1
+#define MCG_C4_FCTRIM_WIDTH                      4
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     0x60u
+#define MCG_C4_DRST_DRS_SHIFT                    5
+#define MCG_C4_DRST_DRS_WIDTH                    2
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK                        0x80u
+#define MCG_C4_DMX32_SHIFT                       7
+#define MCG_C4_DMX32_WIDTH                       1
+#define MCG_C4_DMX32(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C4_DMX32_SHIFT))&MCG_C4_DMX32_MASK)
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK                       0x1Fu
+#define MCG_C5_PRDIV0_SHIFT                      0
+#define MCG_C5_PRDIV0_WIDTH                      5
+#define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK                     0x20u
+#define MCG_C5_PLLSTEN0_SHIFT                    5
+#define MCG_C5_PLLSTEN0_WIDTH                    1
+#define MCG_C5_PLLSTEN0(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLSTEN0_SHIFT))&MCG_C5_PLLSTEN0_MASK)
+#define MCG_C5_PLLCLKEN0_MASK                    0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT                   6
+#define MCG_C5_PLLCLKEN0_WIDTH                   1
+#define MCG_C5_PLLCLKEN0(x)                      (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLCLKEN0_SHIFT))&MCG_C5_PLLCLKEN0_MASK)
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK                        0x1Fu
+#define MCG_C6_VDIV0_SHIFT                       0
+#define MCG_C6_VDIV0_WIDTH                       5
+#define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK                         0x20u
+#define MCG_C6_CME0_SHIFT                        5
+#define MCG_C6_CME0_WIDTH                        1
+#define MCG_C6_CME0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_CME0_SHIFT))&MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK                         0x40u
+#define MCG_C6_PLLS_SHIFT                        6
+#define MCG_C6_PLLS_WIDTH                        1
+#define MCG_C6_PLLS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_PLLS_SHIFT))&MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK                       0x80u
+#define MCG_C6_LOLIE0_SHIFT                      7
+#define MCG_C6_LOLIE0_WIDTH                      1
+#define MCG_C6_LOLIE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C6_LOLIE0_SHIFT))&MCG_C6_LOLIE0_MASK)
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK                         0x1u
+#define MCG_S_IRCST_SHIFT                        0
+#define MCG_S_IRCST_WIDTH                        1
+#define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_IRCST_SHIFT))&MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK                      0x2u
+#define MCG_S_OSCINIT0_SHIFT                     1
+#define MCG_S_OSCINIT0_WIDTH                     1
+#define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK                         0xCu
+#define MCG_S_CLKST_SHIFT                        2
+#define MCG_S_CLKST_WIDTH                        2
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK                        0x10u
+#define MCG_S_IREFST_SHIFT                       4
+#define MCG_S_IREFST_WIDTH                       1
+#define MCG_S_IREFST(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_S_IREFST_SHIFT))&MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK                         0x20u
+#define MCG_S_PLLST_SHIFT                        5
+#define MCG_S_PLLST_WIDTH                        1
+#define MCG_S_PLLST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_PLLST_SHIFT))&MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK                         0x40u
+#define MCG_S_LOCK0_SHIFT                        6
+#define MCG_S_LOCK0_WIDTH                        1
+#define MCG_S_LOCK0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOCK0_SHIFT))&MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK                         0x80u
+#define MCG_S_LOLS0_SHIFT                        7
+#define MCG_S_LOLS0_WIDTH                        1
+#define MCG_S_LOLS0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOLS0_SHIFT))&MCG_S_LOLS0_MASK)
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK                        0x1u
+#define MCG_SC_LOCS0_SHIFT                       0
+#define MCG_SC_LOCS0_WIDTH                       1
+#define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_SC_LOCS0_SHIFT))&MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK                       0xEu
+#define MCG_SC_FCRDIV_SHIFT                      1
+#define MCG_SC_FCRDIV_WIDTH                      3
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK                     0x10u
+#define MCG_SC_FLTPRSRV_SHIFT                    4
+#define MCG_SC_FLTPRSRV_WIDTH                    1
+#define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_SC_FLTPRSRV_SHIFT))&MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK                         0x20u
+#define MCG_SC_ATMF_SHIFT                        5
+#define MCG_SC_ATMF_WIDTH                        1
+#define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMF_SHIFT))&MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK                         0x40u
+#define MCG_SC_ATMS_SHIFT                        6
+#define MCG_SC_ATMS_WIDTH                        1
+#define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMS_SHIFT))&MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK                         0x80u
+#define MCG_SC_ATME_SHIFT                        7
+#define MCG_SC_ATME_WIDTH                        1
+#define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATME_SHIFT))&MCG_SC_ATME_MASK)
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK                     0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT                    0
+#define MCG_ATCVH_ATCVH_WIDTH                    8
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK                     0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT                    0
+#define MCG_ATCVL_ATCVL_WIDTH                    8
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK                       0x3u
+#define MCG_C7_OSCSEL_SHIFT                      0
+#define MCG_C7_OSCSEL_WIDTH                      2
+#define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK                        0x1u
+#define MCG_C8_LOCS1_SHIFT                       0
+#define MCG_C8_LOCS1_WIDTH                       1
+#define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCS1_SHIFT))&MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK                         0x20u
+#define MCG_C8_CME1_SHIFT                        5
+#define MCG_C8_CME1_WIDTH                        1
+#define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C8_CME1_SHIFT))&MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK                        0x40u
+#define MCG_C8_LOLRE_SHIFT                       6
+#define MCG_C8_LOLRE_WIDTH                       1
+#define MCG_C8_LOLRE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOLRE_SHIFT))&MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK                       0x80u
+#define MCG_C8_LOCRE1_SHIFT                      7
+#define MCG_C8_LOCRE1_WIDTH                      1
+#define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCRE1_SHIFT))&MCG_C8_LOCRE1_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR                             (MCG)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS                           { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS                            { MCG }
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1                                   MCG_C1_REG(MCG)
+#define MCG_C2                                   MCG_C2_REG(MCG)
+#define MCG_C3                                   MCG_C3_REG(MCG)
+#define MCG_C4                                   MCG_C4_REG(MCG)
+#define MCG_C5                                   MCG_C5_REG(MCG)
+#define MCG_C6                                   MCG_C6_REG(MCG)
+#define MCG_S                                    MCG_S_REG(MCG)
+#define MCG_SC                                   MCG_SC_REG(MCG)
+#define MCG_ATCVH                                MCG_ATCVH_REG(MCG)
+#define MCG_ATCVL                                MCG_ATCVL_REG(MCG)
+#define MCG_C7                                   MCG_C7_REG(MCG)
+#define MCG_C8                                   MCG_C8_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t CR;                                /**< Control Register, offset: 0xC */
+  __IO uint32_t ISCR;                              /**< Interrupt Status Register, offset: 0x10 */
+  __IO uint32_t ETBCC;                             /**< ETB Counter Control register, offset: 0x14 */
+  __IO uint32_t ETBRL;                             /**< ETB Reload register, offset: 0x18 */
+  __I  uint32_t ETBCNT;                            /**< ETB Counter Value register, offset: 0x1C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PID;                               /**< Process ID register, offset: 0x30 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base)                      ((base)->PLASC)
+#define MCM_PLAMC_REG(base)                      ((base)->PLAMC)
+#define MCM_CR_REG(base)                         ((base)->CR)
+#define MCM_ISCR_REG(base)                       ((base)->ISCR)
+#define MCM_ETBCC_REG(base)                      ((base)->ETBCC)
+#define MCM_ETBRL_REG(base)                      ((base)->ETBRL)
+#define MCM_ETBCNT_REG(base)                     ((base)->ETBCNT)
+#define MCM_PID_REG(base)                        ((base)->PID)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK                       0xFFu
+#define MCM_PLASC_ASC_SHIFT                      0
+#define MCM_PLASC_ASC_WIDTH                      8
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK                       0xFFu
+#define MCM_PLAMC_AMC_SHIFT                      0
+#define MCM_PLAMC_AMC_WIDTH                      8
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* CR Bit Fields */
+#define MCM_CR_SRAMUAP_MASK                      0x3000000u
+#define MCM_CR_SRAMUAP_SHIFT                     24
+#define MCM_CR_SRAMUAP_WIDTH                     2
+#define MCM_CR_SRAMUAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP_MASK                      0x4000000u
+#define MCM_CR_SRAMUWP_SHIFT                     26
+#define MCM_CR_SRAMUWP_WIDTH                     1
+#define MCM_CR_SRAMUWP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUWP_SHIFT))&MCM_CR_SRAMUWP_MASK)
+#define MCM_CR_SRAMLAP_MASK                      0x30000000u
+#define MCM_CR_SRAMLAP_SHIFT                     28
+#define MCM_CR_SRAMLAP_WIDTH                     2
+#define MCM_CR_SRAMLAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP_MASK                      0x40000000u
+#define MCM_CR_SRAMLWP_SHIFT                     30
+#define MCM_CR_SRAMLWP_WIDTH                     1
+#define MCM_CR_SRAMLWP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLWP_SHIFT))&MCM_CR_SRAMLWP_MASK)
+/* ISCR Bit Fields */
+#define MCM_ISCR_IRQ_MASK                        0x2u
+#define MCM_ISCR_IRQ_SHIFT                       1
+#define MCM_ISCR_IRQ_WIDTH                       1
+#define MCM_ISCR_IRQ(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_IRQ_SHIFT))&MCM_ISCR_IRQ_MASK)
+#define MCM_ISCR_NMI_MASK                        0x4u
+#define MCM_ISCR_NMI_SHIFT                       2
+#define MCM_ISCR_NMI_WIDTH                       1
+#define MCM_ISCR_NMI(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_NMI_SHIFT))&MCM_ISCR_NMI_MASK)
+#define MCM_ISCR_DHREQ_MASK                      0x8u
+#define MCM_ISCR_DHREQ_SHIFT                     3
+#define MCM_ISCR_DHREQ_WIDTH                     1
+#define MCM_ISCR_DHREQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_DHREQ_SHIFT))&MCM_ISCR_DHREQ_MASK)
+#define MCM_ISCR_FIOC_MASK                       0x100u
+#define MCM_ISCR_FIOC_SHIFT                      8
+#define MCM_ISCR_FIOC_WIDTH                      1
+#define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FDZC_MASK                       0x200u
+#define MCM_ISCR_FDZC_SHIFT                      9
+#define MCM_ISCR_FDZC_WIDTH                      1
+#define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FOFC_MASK                       0x400u
+#define MCM_ISCR_FOFC_SHIFT                      10
+#define MCM_ISCR_FOFC_WIDTH                      1
+#define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FUFC_MASK                       0x800u
+#define MCM_ISCR_FUFC_SHIFT                      11
+#define MCM_ISCR_FUFC_WIDTH                      1
+#define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FIXC_MASK                       0x1000u
+#define MCM_ISCR_FIXC_SHIFT                      12
+#define MCM_ISCR_FIXC_WIDTH                      1
+#define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIDC_MASK                       0x8000u
+#define MCM_ISCR_FIDC_SHIFT                      15
+#define MCM_ISCR_FIDC_WIDTH                      1
+#define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIOCE_MASK                      0x1000000u
+#define MCM_ISCR_FIOCE_SHIFT                     24
+#define MCM_ISCR_FIOCE_WIDTH                     1
+#define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FDZCE_MASK                      0x2000000u
+#define MCM_ISCR_FDZCE_SHIFT                     25
+#define MCM_ISCR_FDZCE_WIDTH                     1
+#define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FOFCE_MASK                      0x4000000u
+#define MCM_ISCR_FOFCE_SHIFT                     26
+#define MCM_ISCR_FOFCE_WIDTH                     1
+#define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FUFCE_MASK                      0x8000000u
+#define MCM_ISCR_FUFCE_SHIFT                     27
+#define MCM_ISCR_FUFCE_WIDTH                     1
+#define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FIXCE_MASK                      0x10000000u
+#define MCM_ISCR_FIXCE_SHIFT                     28
+#define MCM_ISCR_FIXCE_WIDTH                     1
+#define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIDCE_MASK                      0x80000000u
+#define MCM_ISCR_FIDCE_SHIFT                     31
+#define MCM_ISCR_FIDCE_WIDTH                     1
+#define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
+/* ETBCC Bit Fields */
+#define MCM_ETBCC_CNTEN_MASK                     0x1u
+#define MCM_ETBCC_CNTEN_SHIFT                    0
+#define MCM_ETBCC_CNTEN_WIDTH                    1
+#define MCM_ETBCC_CNTEN(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_CNTEN_SHIFT))&MCM_ETBCC_CNTEN_MASK)
+#define MCM_ETBCC_RSPT_MASK                      0x6u
+#define MCM_ETBCC_RSPT_SHIFT                     1
+#define MCM_ETBCC_RSPT_WIDTH                     2
+#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK                      0x8u
+#define MCM_ETBCC_RLRQ_SHIFT                     3
+#define MCM_ETBCC_RLRQ_WIDTH                     1
+#define MCM_ETBCC_RLRQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RLRQ_SHIFT))&MCM_ETBCC_RLRQ_MASK)
+#define MCM_ETBCC_ETDIS_MASK                     0x10u
+#define MCM_ETBCC_ETDIS_SHIFT                    4
+#define MCM_ETBCC_ETDIS_WIDTH                    1
+#define MCM_ETBCC_ETDIS(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ETDIS_SHIFT))&MCM_ETBCC_ETDIS_MASK)
+#define MCM_ETBCC_ITDIS_MASK                     0x20u
+#define MCM_ETBCC_ITDIS_SHIFT                    5
+#define MCM_ETBCC_ITDIS_WIDTH                    1
+#define MCM_ETBCC_ITDIS(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ITDIS_SHIFT))&MCM_ETBCC_ITDIS_MASK)
+/* ETBRL Bit Fields */
+#define MCM_ETBRL_RELOAD_MASK                    0x7FFu
+#define MCM_ETBRL_RELOAD_SHIFT                   0
+#define MCM_ETBRL_RELOAD_WIDTH                   11
+#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
+/* ETBCNT Bit Fields */
+#define MCM_ETBCNT_COUNTER_MASK                  0x7FFu
+#define MCM_ETBCNT_COUNTER_SHIFT                 0
+#define MCM_ETBCNT_COUNTER_WIDTH                 11
+#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
+/* PID Bit Fields */
+#define MCM_PID_PID_MASK                         0xFFu
+#define MCM_PID_PID_SHIFT                        0
+#define MCM_PID_PID_WIDTH                        8
+#define MCM_PID_PID(x)                           (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR                             (MCM)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { MCM }
+/** Interrupt vectors for the MCM peripheral type */
+#define MCM_IRQS                                 { MCM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC                                MCM_PLASC_REG(MCM)
+#define MCM_PLAMC                                MCM_PLAMC_REG(MCM)
+#define MCM_CR                                   MCM_CR_REG(MCM)
+#define MCM_ISCR                                 MCM_ISCR_REG(MCM)
+#define MCM_ETBCC                                MCM_ETBCC_REG(MCM)
+#define MCM_ETBRL                                MCM_ETBRL_REG(MCM)
+#define MCM_ETBCNT                               MCM_ETBCNT_REG(MCM)
+#define MCM_PID                                  MCM_PID_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
+ * @{
+ */
+
+/** MPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} MPU_Type, *MPU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register accessors */
+#define MPU_CESR_REG(base)                       ((base)->CESR)
+#define MPU_EAR_REG(base,index)                  ((base)->SP[index].EAR)
+#define MPU_EAR_COUNT                            5
+#define MPU_EDR_REG(base,index)                  ((base)->SP[index].EDR)
+#define MPU_EDR_COUNT                            5
+#define MPU_WORD_REG(base,index,index2)          ((base)->WORD[index][index2])
+#define MPU_WORD_COUNT                           12
+#define MPU_WORD_COUNT2                          4
+#define MPU_RGDAAC_REG(base,index)               ((base)->RGDAAC[index])
+#define MPU_RGDAAC_COUNT                         12
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Masks MPU Register Masks
+ * @{
+ */
+
+/* CESR Bit Fields */
+#define MPU_CESR_VLD_MASK                        0x1u
+#define MPU_CESR_VLD_SHIFT                       0
+#define MPU_CESR_VLD_WIDTH                       1
+#define MPU_CESR_VLD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_VLD_SHIFT))&MPU_CESR_VLD_MASK)
+#define MPU_CESR_NRGD_MASK                       0xF00u
+#define MPU_CESR_NRGD_SHIFT                      8
+#define MPU_CESR_NRGD_WIDTH                      4
+#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
+#define MPU_CESR_NSP_MASK                        0xF000u
+#define MPU_CESR_NSP_SHIFT                       12
+#define MPU_CESR_NSP_WIDTH                       4
+#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
+#define MPU_CESR_HRL_MASK                        0xF0000u
+#define MPU_CESR_HRL_SHIFT                       16
+#define MPU_CESR_HRL_WIDTH                       4
+#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
+#define MPU_CESR_SPERR_MASK                      0xF8000000u
+#define MPU_CESR_SPERR_SHIFT                     27
+#define MPU_CESR_SPERR_WIDTH                     5
+#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
+/* EAR Bit Fields */
+#define MPU_EAR_EADDR_MASK                       0xFFFFFFFFu
+#define MPU_EAR_EADDR_SHIFT                      0
+#define MPU_EAR_EADDR_WIDTH                      32
+#define MPU_EAR_EADDR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
+/* EDR Bit Fields */
+#define MPU_EDR_ERW_MASK                         0x1u
+#define MPU_EDR_ERW_SHIFT                        0
+#define MPU_EDR_ERW_WIDTH                        1
+#define MPU_EDR_ERW(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_ERW_SHIFT))&MPU_EDR_ERW_MASK)
+#define MPU_EDR_EATTR_MASK                       0xEu
+#define MPU_EDR_EATTR_SHIFT                      1
+#define MPU_EDR_EATTR_WIDTH                      3
+#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
+#define MPU_EDR_EMN_MASK                         0xF0u
+#define MPU_EDR_EMN_SHIFT                        4
+#define MPU_EDR_EMN_WIDTH                        4
+#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
+#define MPU_EDR_EPID_MASK                        0xFF00u
+#define MPU_EDR_EPID_SHIFT                       8
+#define MPU_EDR_EPID_WIDTH                       8
+#define MPU_EDR_EPID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
+#define MPU_EDR_EACD_MASK                        0xFFFF0000u
+#define MPU_EDR_EACD_SHIFT                       16
+#define MPU_EDR_EACD_WIDTH                       16
+#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
+/* WORD Bit Fields */
+#define MPU_WORD_VLD_MASK                        0x1u
+#define MPU_WORD_VLD_SHIFT                       0
+#define MPU_WORD_VLD_WIDTH                       1
+#define MPU_WORD_VLD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_VLD_SHIFT))&MPU_WORD_VLD_MASK)
+#define MPU_WORD_M0UM_MASK                       0x7u
+#define MPU_WORD_M0UM_SHIFT                      0
+#define MPU_WORD_M0UM_WIDTH                      3
+#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
+#define MPU_WORD_M0SM_MASK                       0x18u
+#define MPU_WORD_M0SM_SHIFT                      3
+#define MPU_WORD_M0SM_WIDTH                      2
+#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
+#define MPU_WORD_M0PE_MASK                       0x20u
+#define MPU_WORD_M0PE_SHIFT                      5
+#define MPU_WORD_M0PE_WIDTH                      1
+#define MPU_WORD_M0PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0PE_SHIFT))&MPU_WORD_M0PE_MASK)
+#define MPU_WORD_ENDADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_ENDADDR_SHIFT                   5
+#define MPU_WORD_ENDADDR_WIDTH                   27
+#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
+#define MPU_WORD_SRTADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_SRTADDR_SHIFT                   5
+#define MPU_WORD_SRTADDR_WIDTH                   27
+#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
+#define MPU_WORD_M1UM_MASK                       0x1C0u
+#define MPU_WORD_M1UM_SHIFT                      6
+#define MPU_WORD_M1UM_WIDTH                      3
+#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
+#define MPU_WORD_M1SM_MASK                       0x600u
+#define MPU_WORD_M1SM_SHIFT                      9
+#define MPU_WORD_M1SM_WIDTH                      2
+#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
+#define MPU_WORD_M1PE_MASK                       0x800u
+#define MPU_WORD_M1PE_SHIFT                      11
+#define MPU_WORD_M1PE_WIDTH                      1
+#define MPU_WORD_M1PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1PE_SHIFT))&MPU_WORD_M1PE_MASK)
+#define MPU_WORD_M2UM_MASK                       0x7000u
+#define MPU_WORD_M2UM_SHIFT                      12
+#define MPU_WORD_M2UM_WIDTH                      3
+#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
+#define MPU_WORD_M2SM_MASK                       0x18000u
+#define MPU_WORD_M2SM_SHIFT                      15
+#define MPU_WORD_M2SM_WIDTH                      2
+#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
+#define MPU_WORD_PIDMASK_MASK                    0xFF0000u
+#define MPU_WORD_PIDMASK_SHIFT                   16
+#define MPU_WORD_PIDMASK_WIDTH                   8
+#define MPU_WORD_PIDMASK(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
+#define MPU_WORD_M2PE_MASK                       0x20000u
+#define MPU_WORD_M2PE_SHIFT                      17
+#define MPU_WORD_M2PE_WIDTH                      1
+#define MPU_WORD_M2PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2PE_SHIFT))&MPU_WORD_M2PE_MASK)
+#define MPU_WORD_M3UM_MASK                       0x1C0000u
+#define MPU_WORD_M3UM_SHIFT                      18
+#define MPU_WORD_M3UM_WIDTH                      3
+#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
+#define MPU_WORD_M3SM_MASK                       0x600000u
+#define MPU_WORD_M3SM_SHIFT                      21
+#define MPU_WORD_M3SM_WIDTH                      2
+#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
+#define MPU_WORD_M3PE_MASK                       0x800000u
+#define MPU_WORD_M3PE_SHIFT                      23
+#define MPU_WORD_M3PE_WIDTH                      1
+#define MPU_WORD_M3PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3PE_SHIFT))&MPU_WORD_M3PE_MASK)
+#define MPU_WORD_PID_MASK                        0xFF000000u
+#define MPU_WORD_PID_SHIFT                       24
+#define MPU_WORD_PID_WIDTH                       8
+#define MPU_WORD_PID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
+#define MPU_WORD_M4WE_MASK                       0x1000000u
+#define MPU_WORD_M4WE_SHIFT                      24
+#define MPU_WORD_M4WE_WIDTH                      1
+#define MPU_WORD_M4WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4WE_SHIFT))&MPU_WORD_M4WE_MASK)
+#define MPU_WORD_M4RE_MASK                       0x2000000u
+#define MPU_WORD_M4RE_SHIFT                      25
+#define MPU_WORD_M4RE_WIDTH                      1
+#define MPU_WORD_M4RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4RE_SHIFT))&MPU_WORD_M4RE_MASK)
+#define MPU_WORD_M5WE_MASK                       0x4000000u
+#define MPU_WORD_M5WE_SHIFT                      26
+#define MPU_WORD_M5WE_WIDTH                      1
+#define MPU_WORD_M5WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5WE_SHIFT))&MPU_WORD_M5WE_MASK)
+#define MPU_WORD_M5RE_MASK                       0x8000000u
+#define MPU_WORD_M5RE_SHIFT                      27
+#define MPU_WORD_M5RE_WIDTH                      1
+#define MPU_WORD_M5RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5RE_SHIFT))&MPU_WORD_M5RE_MASK)
+#define MPU_WORD_M6WE_MASK                       0x10000000u
+#define MPU_WORD_M6WE_SHIFT                      28
+#define MPU_WORD_M6WE_WIDTH                      1
+#define MPU_WORD_M6WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6WE_SHIFT))&MPU_WORD_M6WE_MASK)
+#define MPU_WORD_M6RE_MASK                       0x20000000u
+#define MPU_WORD_M6RE_SHIFT                      29
+#define MPU_WORD_M6RE_WIDTH                      1
+#define MPU_WORD_M6RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6RE_SHIFT))&MPU_WORD_M6RE_MASK)
+#define MPU_WORD_M7WE_MASK                       0x40000000u
+#define MPU_WORD_M7WE_SHIFT                      30
+#define MPU_WORD_M7WE_WIDTH                      1
+#define MPU_WORD_M7WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7WE_SHIFT))&MPU_WORD_M7WE_MASK)
+#define MPU_WORD_M7RE_MASK                       0x80000000u
+#define MPU_WORD_M7RE_SHIFT                      31
+#define MPU_WORD_M7RE_WIDTH                      1
+#define MPU_WORD_M7RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7RE_SHIFT))&MPU_WORD_M7RE_MASK)
+/* RGDAAC Bit Fields */
+#define MPU_RGDAAC_M0UM_MASK                     0x7u
+#define MPU_RGDAAC_M0UM_SHIFT                    0
+#define MPU_RGDAAC_M0UM_WIDTH                    3
+#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
+#define MPU_RGDAAC_M0SM_MASK                     0x18u
+#define MPU_RGDAAC_M0SM_SHIFT                    3
+#define MPU_RGDAAC_M0SM_WIDTH                    2
+#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
+#define MPU_RGDAAC_M0PE_MASK                     0x20u
+#define MPU_RGDAAC_M0PE_SHIFT                    5
+#define MPU_RGDAAC_M0PE_WIDTH                    1
+#define MPU_RGDAAC_M0PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0PE_SHIFT))&MPU_RGDAAC_M0PE_MASK)
+#define MPU_RGDAAC_M1UM_MASK                     0x1C0u
+#define MPU_RGDAAC_M1UM_SHIFT                    6
+#define MPU_RGDAAC_M1UM_WIDTH                    3
+#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
+#define MPU_RGDAAC_M1SM_MASK                     0x600u
+#define MPU_RGDAAC_M1SM_SHIFT                    9
+#define MPU_RGDAAC_M1SM_WIDTH                    2
+#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
+#define MPU_RGDAAC_M1PE_MASK                     0x800u
+#define MPU_RGDAAC_M1PE_SHIFT                    11
+#define MPU_RGDAAC_M1PE_WIDTH                    1
+#define MPU_RGDAAC_M1PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1PE_SHIFT))&MPU_RGDAAC_M1PE_MASK)
+#define MPU_RGDAAC_M2UM_MASK                     0x7000u
+#define MPU_RGDAAC_M2UM_SHIFT                    12
+#define MPU_RGDAAC_M2UM_WIDTH                    3
+#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
+#define MPU_RGDAAC_M2SM_MASK                     0x18000u
+#define MPU_RGDAAC_M2SM_SHIFT                    15
+#define MPU_RGDAAC_M2SM_WIDTH                    2
+#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
+#define MPU_RGDAAC_M2PE_MASK                     0x20000u
+#define MPU_RGDAAC_M2PE_SHIFT                    17
+#define MPU_RGDAAC_M2PE_WIDTH                    1
+#define MPU_RGDAAC_M2PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2PE_SHIFT))&MPU_RGDAAC_M2PE_MASK)
+#define MPU_RGDAAC_M3UM_MASK                     0x1C0000u
+#define MPU_RGDAAC_M3UM_SHIFT                    18
+#define MPU_RGDAAC_M3UM_WIDTH                    3
+#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
+#define MPU_RGDAAC_M3SM_MASK                     0x600000u
+#define MPU_RGDAAC_M3SM_SHIFT                    21
+#define MPU_RGDAAC_M3SM_WIDTH                    2
+#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
+#define MPU_RGDAAC_M3PE_MASK                     0x800000u
+#define MPU_RGDAAC_M3PE_SHIFT                    23
+#define MPU_RGDAAC_M3PE_WIDTH                    1
+#define MPU_RGDAAC_M3PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3PE_SHIFT))&MPU_RGDAAC_M3PE_MASK)
+#define MPU_RGDAAC_M4WE_MASK                     0x1000000u
+#define MPU_RGDAAC_M4WE_SHIFT                    24
+#define MPU_RGDAAC_M4WE_WIDTH                    1
+#define MPU_RGDAAC_M4WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4WE_SHIFT))&MPU_RGDAAC_M4WE_MASK)
+#define MPU_RGDAAC_M4RE_MASK                     0x2000000u
+#define MPU_RGDAAC_M4RE_SHIFT                    25
+#define MPU_RGDAAC_M4RE_WIDTH                    1
+#define MPU_RGDAAC_M4RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4RE_SHIFT))&MPU_RGDAAC_M4RE_MASK)
+#define MPU_RGDAAC_M5WE_MASK                     0x4000000u
+#define MPU_RGDAAC_M5WE_SHIFT                    26
+#define MPU_RGDAAC_M5WE_WIDTH                    1
+#define MPU_RGDAAC_M5WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5WE_SHIFT))&MPU_RGDAAC_M5WE_MASK)
+#define MPU_RGDAAC_M5RE_MASK                     0x8000000u
+#define MPU_RGDAAC_M5RE_SHIFT                    27
+#define MPU_RGDAAC_M5RE_WIDTH                    1
+#define MPU_RGDAAC_M5RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5RE_SHIFT))&MPU_RGDAAC_M5RE_MASK)
+#define MPU_RGDAAC_M6WE_MASK                     0x10000000u
+#define MPU_RGDAAC_M6WE_SHIFT                    28
+#define MPU_RGDAAC_M6WE_WIDTH                    1
+#define MPU_RGDAAC_M6WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6WE_SHIFT))&MPU_RGDAAC_M6WE_MASK)
+#define MPU_RGDAAC_M6RE_MASK                     0x20000000u
+#define MPU_RGDAAC_M6RE_SHIFT                    29
+#define MPU_RGDAAC_M6RE_WIDTH                    1
+#define MPU_RGDAAC_M6RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6RE_SHIFT))&MPU_RGDAAC_M6RE_MASK)
+#define MPU_RGDAAC_M7WE_MASK                     0x40000000u
+#define MPU_RGDAAC_M7WE_SHIFT                    30
+#define MPU_RGDAAC_M7WE_WIDTH                    1
+#define MPU_RGDAAC_M7WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7WE_SHIFT))&MPU_RGDAAC_M7WE_MASK)
+#define MPU_RGDAAC_M7RE_MASK                     0x80000000u
+#define MPU_RGDAAC_M7RE_SHIFT                    31
+#define MPU_RGDAAC_M7RE_WIDTH                    1
+#define MPU_RGDAAC_M7RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7RE_SHIFT))&MPU_RGDAAC_M7RE_MASK)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Masks */
+
+
+/* MPU - Peripheral instance base addresses */
+/** Peripheral MPU base address */
+#define MPU_BASE                                 (0x4000D000u)
+/** Peripheral MPU base pointer */
+#define MPU                                      ((MPU_Type *)MPU_BASE)
+#define MPU_BASE_PTR                             (MPU)
+/** Array initializer of MPU peripheral base addresses */
+#define MPU_BASE_ADDRS                           { MPU_BASE }
+/** Array initializer of MPU peripheral base pointers */
+#define MPU_BASE_PTRS                            { MPU }
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register instance definitions */
+/* MPU */
+#define MPU_CESR                                 MPU_CESR_REG(MPU)
+#define MPU_EAR0                                 MPU_EAR_REG(MPU,0)
+#define MPU_EDR0                                 MPU_EDR_REG(MPU,0)
+#define MPU_EAR1                                 MPU_EAR_REG(MPU,1)
+#define MPU_EDR1                                 MPU_EDR_REG(MPU,1)
+#define MPU_EAR2                                 MPU_EAR_REG(MPU,2)
+#define MPU_EDR2                                 MPU_EDR_REG(MPU,2)
+#define MPU_EAR3                                 MPU_EAR_REG(MPU,3)
+#define MPU_EDR3                                 MPU_EDR_REG(MPU,3)
+#define MPU_EAR4                                 MPU_EAR_REG(MPU,4)
+#define MPU_EDR4                                 MPU_EDR_REG(MPU,4)
+#define MPU_RGD0_WORD0                           MPU_WORD_REG(MPU,0,0)
+#define MPU_RGD0_WORD1                           MPU_WORD_REG(MPU,0,1)
+#define MPU_RGD0_WORD2                           MPU_WORD_REG(MPU,0,2)
+#define MPU_RGD0_WORD3                           MPU_WORD_REG(MPU,0,3)
+#define MPU_RGD1_WORD0                           MPU_WORD_REG(MPU,1,0)
+#define MPU_RGD1_WORD1                           MPU_WORD_REG(MPU,1,1)
+#define MPU_RGD1_WORD2                           MPU_WORD_REG(MPU,1,2)
+#define MPU_RGD1_WORD3                           MPU_WORD_REG(MPU,1,3)
+#define MPU_RGD2_WORD0                           MPU_WORD_REG(MPU,2,0)
+#define MPU_RGD2_WORD1                           MPU_WORD_REG(MPU,2,1)
+#define MPU_RGD2_WORD2                           MPU_WORD_REG(MPU,2,2)
+#define MPU_RGD2_WORD3                           MPU_WORD_REG(MPU,2,3)
+#define MPU_RGD3_WORD0                           MPU_WORD_REG(MPU,3,0)
+#define MPU_RGD3_WORD1                           MPU_WORD_REG(MPU,3,1)
+#define MPU_RGD3_WORD2                           MPU_WORD_REG(MPU,3,2)
+#define MPU_RGD3_WORD3                           MPU_WORD_REG(MPU,3,3)
+#define MPU_RGD4_WORD0                           MPU_WORD_REG(MPU,4,0)
+#define MPU_RGD4_WORD1                           MPU_WORD_REG(MPU,4,1)
+#define MPU_RGD4_WORD2                           MPU_WORD_REG(MPU,4,2)
+#define MPU_RGD4_WORD3                           MPU_WORD_REG(MPU,4,3)
+#define MPU_RGD5_WORD0                           MPU_WORD_REG(MPU,5,0)
+#define MPU_RGD5_WORD1                           MPU_WORD_REG(MPU,5,1)
+#define MPU_RGD5_WORD2                           MPU_WORD_REG(MPU,5,2)
+#define MPU_RGD5_WORD3                           MPU_WORD_REG(MPU,5,3)
+#define MPU_RGD6_WORD0                           MPU_WORD_REG(MPU,6,0)
+#define MPU_RGD6_WORD1                           MPU_WORD_REG(MPU,6,1)
+#define MPU_RGD6_WORD2                           MPU_WORD_REG(MPU,6,2)
+#define MPU_RGD6_WORD3                           MPU_WORD_REG(MPU,6,3)
+#define MPU_RGD7_WORD0                           MPU_WORD_REG(MPU,7,0)
+#define MPU_RGD7_WORD1                           MPU_WORD_REG(MPU,7,1)
+#define MPU_RGD7_WORD2                           MPU_WORD_REG(MPU,7,2)
+#define MPU_RGD7_WORD3                           MPU_WORD_REG(MPU,7,3)
+#define MPU_RGD8_WORD0                           MPU_WORD_REG(MPU,8,0)
+#define MPU_RGD8_WORD1                           MPU_WORD_REG(MPU,8,1)
+#define MPU_RGD8_WORD2                           MPU_WORD_REG(MPU,8,2)
+#define MPU_RGD8_WORD3                           MPU_WORD_REG(MPU,8,3)
+#define MPU_RGD9_WORD0                           MPU_WORD_REG(MPU,9,0)
+#define MPU_RGD9_WORD1                           MPU_WORD_REG(MPU,9,1)
+#define MPU_RGD9_WORD2                           MPU_WORD_REG(MPU,9,2)
+#define MPU_RGD9_WORD3                           MPU_WORD_REG(MPU,9,3)
+#define MPU_RGD10_WORD0                          MPU_WORD_REG(MPU,10,0)
+#define MPU_RGD10_WORD1                          MPU_WORD_REG(MPU,10,1)
+#define MPU_RGD10_WORD2                          MPU_WORD_REG(MPU,10,2)
+#define MPU_RGD10_WORD3                          MPU_WORD_REG(MPU,10,3)
+#define MPU_RGD11_WORD0                          MPU_WORD_REG(MPU,11,0)
+#define MPU_RGD11_WORD1                          MPU_WORD_REG(MPU,11,1)
+#define MPU_RGD11_WORD2                          MPU_WORD_REG(MPU,11,2)
+#define MPU_RGD11_WORD3                          MPU_WORD_REG(MPU,11,3)
+#define MPU_RGDAAC0                              MPU_RGDAAC_REG(MPU,0)
+#define MPU_RGDAAC1                              MPU_RGDAAC_REG(MPU,1)
+#define MPU_RGDAAC2                              MPU_RGDAAC_REG(MPU,2)
+#define MPU_RGDAAC3                              MPU_RGDAAC_REG(MPU,3)
+#define MPU_RGDAAC4                              MPU_RGDAAC_REG(MPU,4)
+#define MPU_RGDAAC5                              MPU_RGDAAC_REG(MPU,5)
+#define MPU_RGDAAC6                              MPU_RGDAAC_REG(MPU,6)
+#define MPU_RGDAAC7                              MPU_RGDAAC_REG(MPU,7)
+#define MPU_RGDAAC8                              MPU_RGDAAC_REG(MPU,8)
+#define MPU_RGDAAC9                              MPU_RGDAAC_REG(MPU,9)
+#define MPU_RGDAAC10                             MPU_RGDAAC_REG(MPU,10)
+#define MPU_RGDAAC11                             MPU_RGDAAC_REG(MPU,11)
+
+/* MPU - Register array accessors */
+#define MPU_EAR(index)                           MPU_EAR_REG(MPU,index)
+#define MPU_EDR(index)                           MPU_EDR_REG(MPU,index)
+#define MPU_WORD(index,index2)                   MPU_WORD_REG(MPU,index,index2)
+#define MPU_RGDAAC(index)                        MPU_RGDAAC_REG(MPU,index)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+  __I  uint8_t FEPROT;                             /**< Non-volatile EERAM Protection Register, offset: 0xE */
+  __I  uint8_t FDPROT;                             /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base)                    ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base)                    ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base)                    ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base)                    ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base)                    ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base)                    ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base)                    ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base)                    ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base)                      ((base)->FPROT3)
+#define NV_FPROT2_REG(base)                      ((base)->FPROT2)
+#define NV_FPROT1_REG(base)                      ((base)->FPROT1)
+#define NV_FPROT0_REG(base)                      ((base)->FPROT0)
+#define NV_FSEC_REG(base)                        ((base)->FSEC)
+#define NV_FOPT_REG(base)                        ((base)->FOPT)
+#define NV_FEPROT_REG(base)                      ((base)->FEPROT)
+#define NV_FDPROT_REG(base)                      ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK                     0xFFu
+#define NV_BACKKEY3_KEY_SHIFT                    0
+#define NV_BACKKEY3_KEY_WIDTH                    8
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK                     0xFFu
+#define NV_BACKKEY2_KEY_SHIFT                    0
+#define NV_BACKKEY2_KEY_WIDTH                    8
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK                     0xFFu
+#define NV_BACKKEY1_KEY_SHIFT                    0
+#define NV_BACKKEY1_KEY_WIDTH                    8
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK                     0xFFu
+#define NV_BACKKEY0_KEY_SHIFT                    0
+#define NV_BACKKEY0_KEY_WIDTH                    8
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK                     0xFFu
+#define NV_BACKKEY7_KEY_SHIFT                    0
+#define NV_BACKKEY7_KEY_WIDTH                    8
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK                     0xFFu
+#define NV_BACKKEY6_KEY_SHIFT                    0
+#define NV_BACKKEY6_KEY_WIDTH                    8
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK                     0xFFu
+#define NV_BACKKEY5_KEY_SHIFT                    0
+#define NV_BACKKEY5_KEY_WIDTH                    8
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK                     0xFFu
+#define NV_BACKKEY4_KEY_SHIFT                    0
+#define NV_BACKKEY4_KEY_WIDTH                    8
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK                      0xFFu
+#define NV_FPROT3_PROT_SHIFT                     0
+#define NV_FPROT3_PROT_WIDTH                     8
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK                      0xFFu
+#define NV_FPROT2_PROT_SHIFT                     0
+#define NV_FPROT2_PROT_WIDTH                     8
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK                      0xFFu
+#define NV_FPROT1_PROT_SHIFT                     0
+#define NV_FPROT1_PROT_WIDTH                     8
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK                      0xFFu
+#define NV_FPROT0_PROT_SHIFT                     0
+#define NV_FPROT0_PROT_WIDTH                     8
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK                         0x3u
+#define NV_FSEC_SEC_SHIFT                        0
+#define NV_FSEC_SEC_WIDTH                        2
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      0xCu
+#define NV_FSEC_FSLACC_SHIFT                     2
+#define NV_FSEC_FSLACC_WIDTH                     2
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        0x30u
+#define NV_FSEC_MEEN_SHIFT                       4
+#define NV_FSEC_MEEN_WIDTH                       2
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       0xC0u
+#define NV_FSEC_KEYEN_SHIFT                      6
+#define NV_FSEC_KEYEN_WIDTH                      2
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK                      0x1u
+#define NV_FOPT_LPBOOT_SHIFT                     0
+#define NV_FOPT_LPBOOT_WIDTH                     1
+#define NV_FOPT_LPBOOT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT_SHIFT))&NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK                  0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT                 1
+#define NV_FOPT_EZPORT_DIS_WIDTH                 1
+#define NV_FOPT_EZPORT_DIS(x)                    (((uint8_t)(((uint8_t)(x))<<NV_FOPT_EZPORT_DIS_SHIFT))&NV_FOPT_EZPORT_DIS_MASK)
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK                     0xFFu
+#define NV_FEPROT_EPROT_SHIFT                    0
+#define NV_FEPROT_EPROT_WIDTH                    8
+#define NV_FEPROT_EPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK                     0xFFu
+#define NV_FDPROT_DPROT_SHIFT                    0
+#define NV_FDPROT_DPROT_WIDTH                    8
+#define NV_FDPROT_DPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFE_FlashConfig base address */
+#define FTFE_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFE_FlashConfig base pointer */
+#define FTFE_FlashConfig                         ((NV_Type *)FTFE_FlashConfig_BASE)
+#define FTFE_FlashConfig_BASE_PTR                (FTFE_FlashConfig)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS                            { FTFE_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS                             { FTFE_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFE_FlashConfig */
+#define NV_BACKKEY3                              NV_BACKKEY3_REG(FTFE_FlashConfig)
+#define NV_BACKKEY2                              NV_BACKKEY2_REG(FTFE_FlashConfig)
+#define NV_BACKKEY1                              NV_BACKKEY1_REG(FTFE_FlashConfig)
+#define NV_BACKKEY0                              NV_BACKKEY0_REG(FTFE_FlashConfig)
+#define NV_BACKKEY7                              NV_BACKKEY7_REG(FTFE_FlashConfig)
+#define NV_BACKKEY6                              NV_BACKKEY6_REG(FTFE_FlashConfig)
+#define NV_BACKKEY5                              NV_BACKKEY5_REG(FTFE_FlashConfig)
+#define NV_BACKKEY4                              NV_BACKKEY4_REG(FTFE_FlashConfig)
+#define NV_FPROT3                                NV_FPROT3_REG(FTFE_FlashConfig)
+#define NV_FPROT2                                NV_FPROT2_REG(FTFE_FlashConfig)
+#define NV_FPROT1                                NV_FPROT1_REG(FTFE_FlashConfig)
+#define NV_FPROT0                                NV_FPROT0_REG(FTFE_FlashConfig)
+#define NV_FSEC                                  NV_FSEC_REG(FTFE_FlashConfig)
+#define NV_FOPT                                  NV_FOPT_REG(FTFE_FlashConfig)
+#define NV_FEPROT                                NV_FEPROT_REG(FTFE_FlashConfig)
+#define NV_FDPROT                                NV_FDPROT_REG(FTFE_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base)                         ((base)->CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK                        0x1u
+#define OSC_CR_SC16P_SHIFT                       0
+#define OSC_CR_SC16P_WIDTH                       1
+#define OSC_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK                         0x2u
+#define OSC_CR_SC8P_SHIFT                        1
+#define OSC_CR_SC8P_WIDTH                        1
+#define OSC_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK                         0x4u
+#define OSC_CR_SC4P_SHIFT                        2
+#define OSC_CR_SC4P_WIDTH                        1
+#define OSC_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK                         0x8u
+#define OSC_CR_SC2P_SHIFT                        3
+#define OSC_CR_SC2P_WIDTH                        1
+#define OSC_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK                     0x20u
+#define OSC_CR_EREFSTEN_SHIFT                    5
+#define OSC_CR_EREFSTEN_WIDTH                    1
+#define OSC_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK                      0x80u
+#define OSC_CR_ERCLKEN_SHIFT                     7
+#define OSC_CR_ERCLKEN_WIDTH                     1
+#define OSC_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE                                 (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC                                      ((OSC_Type *)OSC_BASE)
+#define OSC_BASE_PTR                             (OSC)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS                           { OSC_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS                            { OSC }
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC */
+#define OSC_CR                                   OSC_CR_REG(OSC)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control register, offset: 0x0 */
+  __IO uint32_t MOD;                               /**< Modulus register, offset: 0x4 */
+  __I  uint32_t CNT;                               /**< Counter register, offset: 0x8 */
+  __IO uint32_t IDLY;                              /**< Interrupt Delay register, offset: 0xC */
+  struct {                                         /* offset: 0x10, array step: 0x28 */
+    __IO uint32_t C1;                                /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+    __IO uint32_t S;                                 /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+    __IO uint32_t DLY[2];                            /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+         uint8_t RESERVED_0[24];
+  } CH[2];
+       uint8_t RESERVED_0[240];
+  struct {                                         /* offset: 0x150, array step: 0x8 */
+    __IO uint32_t INTC;                              /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+    __IO uint32_t INT;                               /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+  } DAC[2];
+       uint8_t RESERVED_1[48];
+  __IO uint32_t POEN;                              /**< Pulse-Out n Enable register, offset: 0x190 */
+  __IO uint32_t PODLY[3];                          /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type, *PDB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register accessors */
+#define PDB_SC_REG(base)                         ((base)->SC)
+#define PDB_MOD_REG(base)                        ((base)->MOD)
+#define PDB_CNT_REG(base)                        ((base)->CNT)
+#define PDB_IDLY_REG(base)                       ((base)->IDLY)
+#define PDB_C1_REG(base,index)                   ((base)->CH[index].C1)
+#define PDB_C1_COUNT                             2
+#define PDB_S_REG(base,index)                    ((base)->CH[index].S)
+#define PDB_S_COUNT                              2
+#define PDB_DLY_REG(base,index,index2)           ((base)->CH[index].DLY[index2])
+#define PDB_DLY_COUNT                            2
+#define PDB_DLY_COUNT2                           2
+#define PDB_INTC_REG(base,index)                 ((base)->DAC[index].INTC)
+#define PDB_INTC_COUNT                           2
+#define PDB_INT_REG(base,index)                  ((base)->DAC[index].INT)
+#define PDB_INT_COUNT                            2
+#define PDB_POEN_REG(base)                       ((base)->POEN)
+#define PDB_PODLY_REG(base,index)                ((base)->PODLY[index])
+#define PDB_PODLY_COUNT                          3
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK                         0x1u
+#define PDB_SC_LDOK_SHIFT                        0
+#define PDB_SC_LDOK_WIDTH                        1
+#define PDB_SC_LDOK(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK                         0x2u
+#define PDB_SC_CONT_SHIFT                        1
+#define PDB_SC_CONT_WIDTH                        1
+#define PDB_SC_CONT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK                         0xCu
+#define PDB_SC_MULT_SHIFT                        2
+#define PDB_SC_MULT_WIDTH                        2
+#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK                        0x20u
+#define PDB_SC_PDBIE_SHIFT                       5
+#define PDB_SC_PDBIE_WIDTH                       1
+#define PDB_SC_PDBIE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK                        0x40u
+#define PDB_SC_PDBIF_SHIFT                       6
+#define PDB_SC_PDBIF_WIDTH                       1
+#define PDB_SC_PDBIF(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK                        0x80u
+#define PDB_SC_PDBEN_SHIFT                       7
+#define PDB_SC_PDBEN_WIDTH                       1
+#define PDB_SC_PDBEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK                       0xF00u
+#define PDB_SC_TRGSEL_SHIFT                      8
+#define PDB_SC_TRGSEL_WIDTH                      4
+#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK                    0x7000u
+#define PDB_SC_PRESCALER_SHIFT                   12
+#define PDB_SC_PRESCALER_WIDTH                   3
+#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK                        0x8000u
+#define PDB_SC_DMAEN_SHIFT                       15
+#define PDB_SC_DMAEN_WIDTH                       1
+#define PDB_SC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK                       0x10000u
+#define PDB_SC_SWTRIG_SHIFT                      16
+#define PDB_SC_SWTRIG_WIDTH                      1
+#define PDB_SC_SWTRIG(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK                       0x20000u
+#define PDB_SC_PDBEIE_SHIFT                      17
+#define PDB_SC_PDBEIE_WIDTH                      1
+#define PDB_SC_PDBEIE(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK                        0xC0000u
+#define PDB_SC_LDMOD_SHIFT                       18
+#define PDB_SC_LDMOD_WIDTH                       2
+#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK                         0xFFFFu
+#define PDB_MOD_MOD_SHIFT                        0
+#define PDB_MOD_MOD_WIDTH                        16
+#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK                         0xFFFFu
+#define PDB_CNT_CNT_SHIFT                        0
+#define PDB_CNT_CNT_WIDTH                        16
+#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK                       0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT                      0
+#define PDB_IDLY_IDLY_WIDTH                      16
+#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK                           0xFFu
+#define PDB_C1_EN_SHIFT                          0
+#define PDB_C1_EN_WIDTH                          8
+#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK                          0xFF00u
+#define PDB_C1_TOS_SHIFT                         8
+#define PDB_C1_TOS_WIDTH                         8
+#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK                           0xFF0000u
+#define PDB_C1_BB_SHIFT                          16
+#define PDB_C1_BB_WIDTH                          8
+#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK                           0xFFu
+#define PDB_S_ERR_SHIFT                          0
+#define PDB_S_ERR_WIDTH                          8
+#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK                            0xFF0000u
+#define PDB_S_CF_SHIFT                           16
+#define PDB_S_CF_WIDTH                           8
+#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK                         0xFFFFu
+#define PDB_DLY_DLY_SHIFT                        0
+#define PDB_DLY_DLY_WIDTH                        16
+#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* INTC Bit Fields */
+#define PDB_INTC_TOE_MASK                        0x1u
+#define PDB_INTC_TOE_SHIFT                       0
+#define PDB_INTC_TOE_WIDTH                       1
+#define PDB_INTC_TOE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_TOE_SHIFT))&PDB_INTC_TOE_MASK)
+#define PDB_INTC_EXT_MASK                        0x2u
+#define PDB_INTC_EXT_SHIFT                       1
+#define PDB_INTC_EXT_WIDTH                       1
+#define PDB_INTC_EXT(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_EXT_SHIFT))&PDB_INTC_EXT_MASK)
+/* INT Bit Fields */
+#define PDB_INT_INT_MASK                         0xFFFFu
+#define PDB_INT_INT_SHIFT                        0
+#define PDB_INT_INT_WIDTH                        16
+#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK                       0xFFu
+#define PDB_POEN_POEN_SHIFT                      0
+#define PDB_POEN_POEN_WIDTH                      8
+#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK                      0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT                     0
+#define PDB_PODLY_DLY2_WIDTH                     16
+#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK                      0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT                     16
+#define PDB_PODLY_DLY1_WIDTH                     16
+#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE                                (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0                                     ((PDB_Type *)PDB0_BASE)
+#define PDB0_BASE_PTR                            (PDB0)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS                           { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS                            { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS                                 { PDB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register instance definitions */
+/* PDB0 */
+#define PDB0_SC                                  PDB_SC_REG(PDB0)
+#define PDB0_MOD                                 PDB_MOD_REG(PDB0)
+#define PDB0_CNT                                 PDB_CNT_REG(PDB0)
+#define PDB0_IDLY                                PDB_IDLY_REG(PDB0)
+#define PDB0_CH0C1                               PDB_C1_REG(PDB0,0)
+#define PDB0_CH0S                                PDB_S_REG(PDB0,0)
+#define PDB0_CH0DLY0                             PDB_DLY_REG(PDB0,0,0)
+#define PDB0_CH0DLY1                             PDB_DLY_REG(PDB0,0,1)
+#define PDB0_CH1C1                               PDB_C1_REG(PDB0,1)
+#define PDB0_CH1S                                PDB_S_REG(PDB0,1)
+#define PDB0_CH1DLY0                             PDB_DLY_REG(PDB0,1,0)
+#define PDB0_CH1DLY1                             PDB_DLY_REG(PDB0,1,1)
+#define PDB0_DACINTC0                            PDB_INTC_REG(PDB0,0)
+#define PDB0_DACINT0                             PDB_INT_REG(PDB0,0)
+#define PDB0_DACINTC1                            PDB_INTC_REG(PDB0,1)
+#define PDB0_DACINT1                             PDB_INT_REG(PDB0,1)
+#define PDB0_POEN                                PDB_POEN_REG(PDB0)
+#define PDB0_PO0DLY                              PDB_PODLY_REG(PDB0,0)
+#define PDB0_PO1DLY                              PDB_PODLY_REG(PDB0,1)
+#define PDB0_PO2DLY                              PDB_PODLY_REG(PDB0,2)
+
+/* PDB - Register array accessors */
+#define PDB0_C1(index)                           PDB_C1_REG(PDB0,index)
+#define PDB0_S(index)                            PDB_S_REG(PDB0,index)
+#define PDB0_DLY(index,index2)                   PDB_DLY_REG(PDB0,index,index2)
+#define PDB0_INTC(index)                         PDB_INTC_REG(PDB0,index)
+#define PDB0_INT(index)                          PDB_INT_REG(PDB0,index)
+#define PDB0_PODLY(index)                        PDB_PODLY_REG(PDB0,index)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[252];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[4];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base)                        ((base)->MCR)
+#define PIT_LDVAL_REG(base,index)                ((base)->CHANNEL[index].LDVAL)
+#define PIT_LDVAL_COUNT                          4
+#define PIT_CVAL_REG(base,index)                 ((base)->CHANNEL[index].CVAL)
+#define PIT_CVAL_COUNT                           4
+#define PIT_TCTRL_REG(base,index)                ((base)->CHANNEL[index].TCTRL)
+#define PIT_TCTRL_COUNT                          4
+#define PIT_TFLG_REG(base,index)                 ((base)->CHANNEL[index].TFLG)
+#define PIT_TFLG_COUNT                           4
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK                         0x1u
+#define PIT_MCR_FRZ_SHIFT                        0
+#define PIT_MCR_FRZ_WIDTH                        1
+#define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK                        0x2u
+#define PIT_MCR_MDIS_SHIFT                       1
+#define PIT_MCR_MDIS_WIDTH                       1
+#define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT                      0
+#define PIT_LDVAL_TSV_WIDTH                      32
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT                       0
+#define PIT_CVAL_TVL_WIDTH                       32
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK                       0x1u
+#define PIT_TCTRL_TEN_SHIFT                      0
+#define PIT_TCTRL_TEN_WIDTH                      1
+#define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK                       0x2u
+#define PIT_TCTRL_TIE_SHIFT                      1
+#define PIT_TCTRL_TIE_WIDTH                      1
+#define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK                       0x4u
+#define PIT_TCTRL_CHN_SHIFT                      2
+#define PIT_TCTRL_CHN_WIDTH                      1
+#define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK                        0x1u
+#define PIT_TFLG_TIF_SHIFT                       0
+#define PIT_TFLG_TIF_WIDTH                       1
+#define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR                             (PIT)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS                           { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR                                  PIT_MCR_REG(PIT)
+#define PIT_LDVAL0                               PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0                                PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0                               PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0                                PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1                               PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1                                PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1                               PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1                                PIT_TFLG_REG(PIT,1)
+#define PIT_LDVAL2                               PIT_LDVAL_REG(PIT,2)
+#define PIT_CVAL2                                PIT_CVAL_REG(PIT,2)
+#define PIT_TCTRL2                               PIT_TCTRL_REG(PIT,2)
+#define PIT_TFLG2                                PIT_TFLG_REG(PIT,2)
+#define PIT_LDVAL3                               PIT_LDVAL_REG(PIT,3)
+#define PIT_CVAL3                                PIT_CVAL_REG(PIT,3)
+#define PIT_TCTRL3                               PIT_TCTRL_REG(PIT,3)
+#define PIT_TFLG3                                PIT_TFLG_REG(PIT,3)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index)                         PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index)                          PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index)                         PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index)                          PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base)                     ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base)                     ((base)->LVDSC2)
+#define PMC_REGSC_REG(base)                      ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK                     0x3u
+#define PMC_LVDSC1_LVDV_SHIFT                    0
+#define PMC_LVDSC1_LVDV_WIDTH                    2
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT                   4
+#define PMC_LVDSC1_LVDRE_WIDTH                   1
+#define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK                    0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT                   5
+#define PMC_LVDSC1_LVDIE_WIDTH                   1
+#define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK                   0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT                  6
+#define PMC_LVDSC1_LVDACK_WIDTH                  1
+#define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK                     0x80u
+#define PMC_LVDSC1_LVDF_SHIFT                    7
+#define PMC_LVDSC1_LVDF_WIDTH                    1
+#define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK                     0x3u
+#define PMC_LVDSC2_LVWV_SHIFT                    0
+#define PMC_LVDSC2_LVWV_WIDTH                    2
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT                   5
+#define PMC_LVDSC2_LVWIE_WIDTH                   1
+#define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK                   0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT                  6
+#define PMC_LVDSC2_LVWACK_WIDTH                  1
+#define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK                     0x80u
+#define PMC_LVDSC2_LVWF_SHIFT                    7
+#define PMC_LVDSC2_LVWF_WIDTH                    1
+#define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK                      0x1u
+#define PMC_REGSC_BGBE_SHIFT                     0
+#define PMC_REGSC_BGBE_WIDTH                     1
+#define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK                    0x4u
+#define PMC_REGSC_REGONS_SHIFT                   2
+#define PMC_REGSC_REGONS_WIDTH                   1
+#define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK                    0x8u
+#define PMC_REGSC_ACKISO_SHIFT                   3
+#define PMC_REGSC_ACKISO_WIDTH                   1
+#define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK                      0x10u
+#define PMC_REGSC_BGEN_SHIFT                     4
+#define PMC_REGSC_BGEN_WIDTH                     1
+#define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR                             (PMC)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS                           { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { LVD_LVW_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1                               PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2                               PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC                                PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
+  __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
+  __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index)                 ((base)->PCR[index])
+#define PORT_PCR_COUNT                           32
+#define PORT_GPCLR_REG(base)                     ((base)->GPCLR)
+#define PORT_GPCHR_REG(base)                     ((base)->GPCHR)
+#define PORT_ISFR_REG(base)                      ((base)->ISFR)
+#define PORT_DFER_REG(base)                      ((base)->DFER)
+#define PORT_DFCR_REG(base)                      ((base)->DFCR)
+#define PORT_DFWR_REG(base)                      ((base)->DFWR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK                         0x1u
+#define PORT_PCR_PS_SHIFT                        0
+#define PORT_PCR_PS_WIDTH                        1
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK                         0x2u
+#define PORT_PCR_PE_SHIFT                        1
+#define PORT_PCR_PE_WIDTH                        1
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK                        0x4u
+#define PORT_PCR_SRE_SHIFT                       2
+#define PORT_PCR_SRE_WIDTH                       1
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK                        0x10u
+#define PORT_PCR_PFE_SHIFT                       4
+#define PORT_PCR_PFE_WIDTH                       1
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK                        0x20u
+#define PORT_PCR_ODE_SHIFT                       5
+#define PORT_PCR_ODE_WIDTH                       1
+#define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK                        0x40u
+#define PORT_PCR_DSE_SHIFT                       6
+#define PORT_PCR_DSE_WIDTH                       1
+#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK                        0x700u
+#define PORT_PCR_MUX_SHIFT                       8
+#define PORT_PCR_MUX_WIDTH                       3
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK                         0x8000u
+#define PORT_PCR_LK_SHIFT                        15
+#define PORT_PCR_LK_WIDTH                        1
+#define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK                       0xF0000u
+#define PORT_PCR_IRQC_SHIFT                      16
+#define PORT_PCR_IRQC_WIDTH                      4
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        0x1000000u
+#define PORT_PCR_ISF_SHIFT                       24
+#define PORT_PCR_ISF_WIDTH                       1
+#define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT                    0
+#define PORT_GPCLR_GPWD_WIDTH                    16
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT                    16
+#define PORT_GPCLR_GPWE_WIDTH                    16
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT                    0
+#define PORT_GPCHR_GPWD_WIDTH                    16
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT                    16
+#define PORT_GPCHR_GPWE_WIDTH                    16
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT                      0
+#define PORT_ISFR_ISF_WIDTH                      32
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK                       0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT                      0
+#define PORT_DFER_DFE_WIDTH                      32
+#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK                        0x1u
+#define PORT_DFCR_CS_SHIFT                       0
+#define PORT_DFCR_CS_WIDTH                       1
+#define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK                      0x1Fu
+#define PORT_DFWR_FILT_SHIFT                     0
+#define PORT_DFWR_FILT_WIDTH                     5
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR                           (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR                           (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR                           (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR                           (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR                           (PORTE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0                               PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1                               PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2                               PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3                               PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4                               PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5                               PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6                               PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7                               PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8                               PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9                               PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10                              PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11                              PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12                              PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13                              PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14                              PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15                              PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16                              PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17                              PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18                              PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19                              PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20                              PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21                              PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22                              PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23                              PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24                              PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25                              PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26                              PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27                              PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28                              PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29                              PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30                              PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31                              PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR                              PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR                              PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR                               PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0                               PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1                               PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2                               PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3                               PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4                               PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5                               PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6                               PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7                               PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8                               PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9                               PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10                              PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11                              PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12                              PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13                              PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14                              PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15                              PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16                              PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17                              PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18                              PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19                              PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20                              PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21                              PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22                              PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23                              PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24                              PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25                              PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26                              PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27                              PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28                              PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29                              PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30                              PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31                              PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR                              PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR                              PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR                               PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0                               PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1                               PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2                               PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3                               PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4                               PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5                               PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6                               PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7                               PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8                               PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9                               PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10                              PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11                              PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12                              PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13                              PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14                              PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15                              PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16                              PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17                              PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18                              PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19                              PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20                              PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21                              PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22                              PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23                              PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24                              PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25                              PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26                              PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27                              PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28                              PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29                              PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30                              PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31                              PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR                              PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR                              PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR                               PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0                               PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1                               PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2                               PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3                               PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4                               PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5                               PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6                               PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7                               PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8                               PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9                               PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10                              PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11                              PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12                              PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13                              PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14                              PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15                              PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16                              PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17                              PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18                              PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19                              PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20                              PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21                              PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22                              PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23                              PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24                              PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25                              PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26                              PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27                              PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28                              PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29                              PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30                              PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31                              PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR                              PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR                              PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR                               PORT_ISFR_REG(PORTD)
+#define PORTD_DFER                               PORT_DFER_REG(PORTD)
+#define PORTD_DFCR                               PORT_DFCR_REG(PORTD)
+#define PORTD_DFWR                               PORT_DFWR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0                               PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1                               PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2                               PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3                               PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4                               PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5                               PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6                               PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7                               PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8                               PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9                               PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10                              PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11                              PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12                              PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13                              PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14                              PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15                              PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16                              PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17                              PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18                              PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19                              PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20                              PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21                              PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22                              PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23                              PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24                              PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25                              PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26                              PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27                              PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28                              PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29                              PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30                              PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31                              PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR                              PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR                              PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR                               PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index)                         PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index)                         PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index)                         PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index)                         PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index)                         PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+       uint8_t RESERVED_1[1];
+  __I  uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base)                       ((base)->SRS0)
+#define RCM_SRS1_REG(base)                       ((base)->SRS1)
+#define RCM_RPFC_REG(base)                       ((base)->RPFC)
+#define RCM_RPFW_REG(base)                       ((base)->RPFW)
+#define RCM_MR_REG(base)                         ((base)->MR)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK                     0x1u
+#define RCM_SRS0_WAKEUP_SHIFT                    0
+#define RCM_SRS0_WAKEUP_WIDTH                    1
+#define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK                        0x2u
+#define RCM_SRS0_LVD_SHIFT                       1
+#define RCM_SRS0_LVD_WIDTH                       1
+#define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK                        0x4u
+#define RCM_SRS0_LOC_SHIFT                       2
+#define RCM_SRS0_LOC_WIDTH                       1
+#define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOC_SHIFT))&RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK                        0x8u
+#define RCM_SRS0_LOL_SHIFT                       3
+#define RCM_SRS0_LOL_WIDTH                       1
+#define RCM_SRS0_LOL(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOL_SHIFT))&RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK                       0x20u
+#define RCM_SRS0_WDOG_SHIFT                      5
+#define RCM_SRS0_WDOG_WIDTH                      1
+#define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK                        0x40u
+#define RCM_SRS0_PIN_SHIFT                       6
+#define RCM_SRS0_PIN_WIDTH                       1
+#define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK                        0x80u
+#define RCM_SRS0_POR_SHIFT                       7
+#define RCM_SRS0_POR_WIDTH                       1
+#define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK                       0x1u
+#define RCM_SRS1_JTAG_SHIFT                      0
+#define RCM_SRS1_JTAG_WIDTH                      1
+#define RCM_SRS1_JTAG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_JTAG_SHIFT))&RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK                     0x2u
+#define RCM_SRS1_LOCKUP_SHIFT                    1
+#define RCM_SRS1_LOCKUP_WIDTH                    1
+#define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK                         0x4u
+#define RCM_SRS1_SW_SHIFT                        2
+#define RCM_SRS1_SW_WIDTH                        1
+#define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK                     0x8u
+#define RCM_SRS1_MDM_AP_SHIFT                    3
+#define RCM_SRS1_MDM_AP_WIDTH                    1
+#define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK                       0x10u
+#define RCM_SRS1_EZPT_SHIFT                      4
+#define RCM_SRS1_EZPT_WIDTH                      1
+#define RCM_SRS1_EZPT(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_EZPT_SHIFT))&RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK                    0x20u
+#define RCM_SRS1_SACKERR_SHIFT                   5
+#define RCM_SRS1_SACKERR_WIDTH                   1
+#define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 0
+#define RCM_RPFC_RSTFLTSRW_WIDTH                 2
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK                   0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT                  2
+#define RCM_RPFC_RSTFLTSS_WIDTH                  1
+#define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 0
+#define RCM_RPFW_RSTFLTSEL_WIDTH                 5
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK                       0x2u
+#define RCM_MR_EZP_MS_SHIFT                      1
+#define RCM_MR_EZP_MS_WIDTH                      1
+#define RCM_MR_EZP_MS(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_MR_EZP_MS_SHIFT))&RCM_MR_EZP_MS_MASK)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR                             (RCM)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS                           { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS                            { RCM }
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0                                 RCM_SRS0_REG(RCM)
+#define RCM_SRS1                                 RCM_SRS1_REG(RCM)
+#define RCM_RPFC                                 RCM_RPFC_REG(RCM)
+#define RCM_RPFW                                 RCM_RPFW_REG(RCM)
+#define RCM_MR                                   RCM_MR_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index)                ((base)->REG[index])
+#define RFSYS_REG_COUNT                          8
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK                        0xFFu
+#define RFSYS_REG_LL_SHIFT                       0
+#define RFSYS_REG_LL_WIDTH                       8
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        0xFF00u
+#define RFSYS_REG_LH_SHIFT                       8
+#define RFSYS_REG_LH_WIDTH                       8
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        0xFF0000u
+#define RFSYS_REG_HL_SHIFT                       16
+#define RFSYS_REG_HL_WIDTH                       8
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        0xFF000000u
+#define RFSYS_REG_HH_SHIFT                       24
+#define RFSYS_REG_HH_WIDTH                       8
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR                           (RFSYS)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS                          { RFSYS }
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0                               RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1                               RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2                               RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3                               RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4                               RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5                               RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6                               RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7                               RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index)                         RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type, *RFVBAT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register accessors */
+#define RFVBAT_REG_REG(base,index)               ((base)->REG[index])
+#define RFVBAT_REG_COUNT                         8
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK                       0xFFu
+#define RFVBAT_REG_LL_SHIFT                      0
+#define RFVBAT_REG_LL_WIDTH                      8
+#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK                       0xFF00u
+#define RFVBAT_REG_LH_SHIFT                      8
+#define RFVBAT_REG_LH_WIDTH                      8
+#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK                       0xFF0000u
+#define RFVBAT_REG_HL_SHIFT                      16
+#define RFVBAT_REG_HL_WIDTH                      8
+#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK                       0xFF000000u
+#define RFVBAT_REG_HH_SHIFT                      24
+#define RFVBAT_REG_HH_WIDTH                      8
+#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE                              (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
+#define RFVBAT_BASE_PTR                          (RFVBAT)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS                        { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS                         { RFVBAT }
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register instance definitions */
+/* RFVBAT */
+#define RFVBAT_REG0                              RFVBAT_REG_REG(RFVBAT,0)
+#define RFVBAT_REG1                              RFVBAT_REG_REG(RFVBAT,1)
+#define RFVBAT_REG2                              RFVBAT_REG_REG(RFVBAT,2)
+#define RFVBAT_REG3                              RFVBAT_REG_REG(RFVBAT,3)
+#define RFVBAT_REG4                              RFVBAT_REG_REG(RFVBAT,4)
+#define RFVBAT_REG5                              RFVBAT_REG_REG(RFVBAT,5)
+#define RFVBAT_REG6                              RFVBAT_REG_REG(RFVBAT,6)
+#define RFVBAT_REG7                              RFVBAT_REG_REG(RFVBAT,7)
+
+/* RFVBAT - Register array accessors */
+#define RFVBAT_REG(index)                        RFVBAT_REG_REG(RFVBAT,index)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< RNGA Control Register, offset: 0x0 */
+  __I  uint32_t SR;                                /**< RNGA Status Register, offset: 0x4 */
+  __O  uint32_t ER;                                /**< RNGA Entropy Register, offset: 0x8 */
+  __I  uint32_t OR;                                /**< RNGA Output Register, offset: 0xC */
+} RNG_Type, *RNG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register accessors */
+#define RNG_CR_REG(base)                         ((base)->CR)
+#define RNG_SR_REG(base)                         ((base)->SR)
+#define RNG_ER_REG(base)                         ((base)->ER)
+#define RNG_OR_REG(base)                         ((base)->OR)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define RNG_CR_GO_MASK                           0x1u
+#define RNG_CR_GO_SHIFT                          0
+#define RNG_CR_GO_WIDTH                          1
+#define RNG_CR_GO(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_GO_SHIFT))&RNG_CR_GO_MASK)
+#define RNG_CR_HA_MASK                           0x2u
+#define RNG_CR_HA_SHIFT                          1
+#define RNG_CR_HA_WIDTH                          1
+#define RNG_CR_HA(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_HA_SHIFT))&RNG_CR_HA_MASK)
+#define RNG_CR_INTM_MASK                         0x4u
+#define RNG_CR_INTM_SHIFT                        2
+#define RNG_CR_INTM_WIDTH                        1
+#define RNG_CR_INTM(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_INTM_SHIFT))&RNG_CR_INTM_MASK)
+#define RNG_CR_CLRI_MASK                         0x8u
+#define RNG_CR_CLRI_SHIFT                        3
+#define RNG_CR_CLRI_WIDTH                        1
+#define RNG_CR_CLRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_CLRI_SHIFT))&RNG_CR_CLRI_MASK)
+#define RNG_CR_SLP_MASK                          0x10u
+#define RNG_CR_SLP_SHIFT                         4
+#define RNG_CR_SLP_WIDTH                         1
+#define RNG_CR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_CR_SLP_SHIFT))&RNG_CR_SLP_MASK)
+/* SR Bit Fields */
+#define RNG_SR_SECV_MASK                         0x1u
+#define RNG_SR_SECV_SHIFT                        0
+#define RNG_SR_SECV_WIDTH                        1
+#define RNG_SR_SECV(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_SECV_SHIFT))&RNG_SR_SECV_MASK)
+#define RNG_SR_LRS_MASK                          0x2u
+#define RNG_SR_LRS_SHIFT                         1
+#define RNG_SR_LRS_WIDTH                         1
+#define RNG_SR_LRS(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_LRS_SHIFT))&RNG_SR_LRS_MASK)
+#define RNG_SR_ORU_MASK                          0x4u
+#define RNG_SR_ORU_SHIFT                         2
+#define RNG_SR_ORU_WIDTH                         1
+#define RNG_SR_ORU(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_ORU_SHIFT))&RNG_SR_ORU_MASK)
+#define RNG_SR_ERRI_MASK                         0x8u
+#define RNG_SR_ERRI_SHIFT                        3
+#define RNG_SR_ERRI_WIDTH                        1
+#define RNG_SR_ERRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_ERRI_SHIFT))&RNG_SR_ERRI_MASK)
+#define RNG_SR_SLP_MASK                          0x10u
+#define RNG_SR_SLP_SHIFT                         4
+#define RNG_SR_SLP_WIDTH                         1
+#define RNG_SR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_SLP_SHIFT))&RNG_SR_SLP_MASK)
+#define RNG_SR_OREG_LVL_MASK                     0xFF00u
+#define RNG_SR_OREG_LVL_SHIFT                    8
+#define RNG_SR_OREG_LVL_WIDTH                    8
+#define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK                    0xFF0000u
+#define RNG_SR_OREG_SIZE_SHIFT                   16
+#define RNG_SR_OREG_SIZE_WIDTH                   8
+#define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
+/* ER Bit Fields */
+#define RNG_ER_EXT_ENT_MASK                      0xFFFFFFFFu
+#define RNG_ER_EXT_ENT_SHIFT                     0
+#define RNG_ER_EXT_ENT_WIDTH                     32
+#define RNG_ER_EXT_ENT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
+/* OR Bit Fields */
+#define RNG_OR_RANDOUT_MASK                      0xFFFFFFFFu
+#define RNG_OR_RANDOUT_SHIFT                     0
+#define RNG_OR_RANDOUT_WIDTH                     32
+#define RNG_OR_RANDOUT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE                                 (0x40029000u)
+/** Peripheral RNG base pointer */
+#define RNG                                      ((RNG_Type *)RNG_BASE)
+#define RNG_BASE_PTR                             (RNG)
+/** Array initializer of RNG peripheral base addresses */
+#define RNG_BASE_ADDRS                           { RNG_BASE }
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASE_PTRS                            { RNG }
+/** Interrupt vectors for the RNG peripheral type */
+#define RNG_IRQS                                 { RNG_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register instance definitions */
+/* RNG */
+#define RNG_CR                                   RNG_CR_REG(RNG)
+#define RNG_SR                                   RNG_SR_REG(RNG)
+#define RNG_ER                                   RNG_ER_REG(RNG)
+#define RNG_OR                                   RNG_OR_REG(RNG)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+       uint8_t RESERVED_0[2016];
+  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base)                        ((base)->TSR)
+#define RTC_TPR_REG(base)                        ((base)->TPR)
+#define RTC_TAR_REG(base)                        ((base)->TAR)
+#define RTC_TCR_REG(base)                        ((base)->TCR)
+#define RTC_CR_REG(base)                         ((base)->CR)
+#define RTC_SR_REG(base)                         ((base)->SR)
+#define RTC_LR_REG(base)                         ((base)->LR)
+#define RTC_IER_REG(base)                        ((base)->IER)
+#define RTC_WAR_REG(base)                        ((base)->WAR)
+#define RTC_RAR_REG(base)                        ((base)->RAR)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT                        0
+#define RTC_TSR_TSR_WIDTH                        32
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK                         0xFFFFu
+#define RTC_TPR_TPR_SHIFT                        0
+#define RTC_TPR_TPR_WIDTH                        16
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT                        0
+#define RTC_TAR_TAR_WIDTH                        32
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK                         0xFFu
+#define RTC_TCR_TCR_SHIFT                        0
+#define RTC_TCR_TCR_WIDTH                        8
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         0xFF00u
+#define RTC_TCR_CIR_SHIFT                        8
+#define RTC_TCR_CIR_WIDTH                        8
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         0xFF0000u
+#define RTC_TCR_TCV_SHIFT                        16
+#define RTC_TCR_TCV_WIDTH                        8
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         0xFF000000u
+#define RTC_TCR_CIC_SHIFT                        24
+#define RTC_TCR_CIC_WIDTH                        8
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK                          0x1u
+#define RTC_CR_SWR_SHIFT                         0
+#define RTC_CR_SWR_WIDTH                         1
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK                          0x2u
+#define RTC_CR_WPE_SHIFT                         1
+#define RTC_CR_WPE_WIDTH                         1
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK                          0x4u
+#define RTC_CR_SUP_SHIFT                         2
+#define RTC_CR_SUP_WIDTH                         1
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK                           0x8u
+#define RTC_CR_UM_SHIFT                          3
+#define RTC_CR_UM_WIDTH                          1
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK                          0x10u
+#define RTC_CR_WPS_SHIFT                         4
+#define RTC_CR_WPS_WIDTH                         1
+#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK                         0x100u
+#define RTC_CR_OSCE_SHIFT                        8
+#define RTC_CR_OSCE_WIDTH                        1
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK                         0x200u
+#define RTC_CR_CLKO_SHIFT                        9
+#define RTC_CR_CLKO_WIDTH                        1
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK                        0x400u
+#define RTC_CR_SC16P_SHIFT                       10
+#define RTC_CR_SC16P_WIDTH                       1
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK                         0x800u
+#define RTC_CR_SC8P_SHIFT                        11
+#define RTC_CR_SC8P_WIDTH                        1
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK                         0x1000u
+#define RTC_CR_SC4P_SHIFT                        12
+#define RTC_CR_SC4P_WIDTH                        1
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK                         0x2000u
+#define RTC_CR_SC2P_SHIFT                        13
+#define RTC_CR_SC2P_WIDTH                        1
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK                          0x1u
+#define RTC_SR_TIF_SHIFT                         0
+#define RTC_SR_TIF_WIDTH                         1
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK                          0x2u
+#define RTC_SR_TOF_SHIFT                         1
+#define RTC_SR_TOF_WIDTH                         1
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK                          0x4u
+#define RTC_SR_TAF_SHIFT                         2
+#define RTC_SR_TAF_WIDTH                         1
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK                          0x10u
+#define RTC_SR_TCE_SHIFT                         4
+#define RTC_SR_TCE_WIDTH                         1
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK                          0x8u
+#define RTC_LR_TCL_SHIFT                         3
+#define RTC_LR_TCL_WIDTH                         1
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK                          0x10u
+#define RTC_LR_CRL_SHIFT                         4
+#define RTC_LR_CRL_WIDTH                         1
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK                          0x20u
+#define RTC_LR_SRL_SHIFT                         5
+#define RTC_LR_SRL_WIDTH                         1
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK                          0x40u
+#define RTC_LR_LRL_SHIFT                         6
+#define RTC_LR_LRL_WIDTH                         1
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK                        0x1u
+#define RTC_IER_TIIE_SHIFT                       0
+#define RTC_IER_TIIE_WIDTH                       1
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK                        0x2u
+#define RTC_IER_TOIE_SHIFT                       1
+#define RTC_IER_TOIE_WIDTH                       1
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK                        0x4u
+#define RTC_IER_TAIE_SHIFT                       2
+#define RTC_IER_TAIE_WIDTH                       1
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK                        0x10u
+#define RTC_IER_TSIE_SHIFT                       4
+#define RTC_IER_TSIE_WIDTH                       1
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK                        0x80u
+#define RTC_IER_WPON_SHIFT                       7
+#define RTC_IER_WPON_WIDTH                       1
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK                        0x1u
+#define RTC_WAR_TSRW_SHIFT                       0
+#define RTC_WAR_TSRW_WIDTH                       1
+#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TSRW_SHIFT))&RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK                        0x2u
+#define RTC_WAR_TPRW_SHIFT                       1
+#define RTC_WAR_TPRW_WIDTH                       1
+#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TPRW_SHIFT))&RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK                        0x4u
+#define RTC_WAR_TARW_SHIFT                       2
+#define RTC_WAR_TARW_WIDTH                       1
+#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TARW_SHIFT))&RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK                        0x8u
+#define RTC_WAR_TCRW_SHIFT                       3
+#define RTC_WAR_TCRW_WIDTH                       1
+#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TCRW_SHIFT))&RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK                         0x10u
+#define RTC_WAR_CRW_SHIFT                        4
+#define RTC_WAR_CRW_WIDTH                        1
+#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_CRW_SHIFT))&RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK                         0x20u
+#define RTC_WAR_SRW_SHIFT                        5
+#define RTC_WAR_SRW_WIDTH                        1
+#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_SRW_SHIFT))&RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK                         0x40u
+#define RTC_WAR_LRW_SHIFT                        6
+#define RTC_WAR_LRW_WIDTH                        1
+#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_LRW_SHIFT))&RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK                        0x80u
+#define RTC_WAR_IERW_SHIFT                       7
+#define RTC_WAR_IERW_WIDTH                       1
+#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_IERW_SHIFT))&RTC_WAR_IERW_MASK)
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK                        0x1u
+#define RTC_RAR_TSRR_SHIFT                       0
+#define RTC_RAR_TSRR_WIDTH                       1
+#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TSRR_SHIFT))&RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK                        0x2u
+#define RTC_RAR_TPRR_SHIFT                       1
+#define RTC_RAR_TPRR_WIDTH                       1
+#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TPRR_SHIFT))&RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK                        0x4u
+#define RTC_RAR_TARR_SHIFT                       2
+#define RTC_RAR_TARR_WIDTH                       1
+#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TARR_SHIFT))&RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK                        0x8u
+#define RTC_RAR_TCRR_SHIFT                       3
+#define RTC_RAR_TCRR_WIDTH                       1
+#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TCRR_SHIFT))&RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK                         0x10u
+#define RTC_RAR_CRR_SHIFT                        4
+#define RTC_RAR_CRR_WIDTH                        1
+#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_CRR_SHIFT))&RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK                         0x20u
+#define RTC_RAR_SRR_SHIFT                        5
+#define RTC_RAR_SRR_WIDTH                        1
+#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_SRR_SHIFT))&RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK                         0x40u
+#define RTC_RAR_LRR_SHIFT                        6
+#define RTC_RAR_LRR_WIDTH                        1
+#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_LRR_SHIFT))&RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK                        0x80u
+#define RTC_RAR_IERR_SHIFT                       7
+#define RTC_RAR_IERR_WIDTH                       1
+#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_IERR_SHIFT))&RTC_RAR_IERR_MASK)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR                             (RTC)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR                                  RTC_TSR_REG(RTC)
+#define RTC_TPR                                  RTC_TPR_REG(RTC)
+#define RTC_TAR                                  RTC_TAR_REG(RTC)
+#define RTC_TCR                                  RTC_TCR_REG(RTC)
+#define RTC_CR                                   RTC_CR_REG(RTC)
+#define RTC_SR                                   RTC_SR_REG(RTC)
+#define RTC_LR                                   RTC_LR_REG(RTC)
+#define RTC_IER                                  RTC_IER_REG(RTC)
+#define RTC_WAR                                  RTC_WAR_REG(RTC)
+#define RTC_RAR                                  RTC_RAR_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
+ * @{
+ */
+
+/** SDHC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DSADDR;                            /**< DMA System Address register, offset: 0x0 */
+  __IO uint32_t BLKATTR;                           /**< Block Attributes register, offset: 0x4 */
+  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x8 */
+  __IO uint32_t XFERTYP;                           /**< Transfer Type register, offset: 0xC */
+  __I  uint32_t CMDRSP[4];                         /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t DATPORT;                           /**< Buffer Data Port register, offset: 0x20 */
+  __I  uint32_t PRSSTAT;                           /**< Present State register, offset: 0x24 */
+  __IO uint32_t PROCTL;                            /**< Protocol Control register, offset: 0x28 */
+  __IO uint32_t SYSCTL;                            /**< System Control register, offset: 0x2C */
+  __IO uint32_t IRQSTAT;                           /**< Interrupt Status register, offset: 0x30 */
+  __IO uint32_t IRQSTATEN;                         /**< Interrupt Status Enable register, offset: 0x34 */
+  __IO uint32_t IRQSIGEN;                          /**< Interrupt Signal Enable register, offset: 0x38 */
+  __I  uint32_t AC12ERR;                           /**< Auto CMD12 Error Status Register, offset: 0x3C */
+  __I  uint32_t HTCAPBLT;                          /**< Host Controller Capabilities, offset: 0x40 */
+  __IO uint32_t WML;                               /**< Watermark Level Register, offset: 0x44 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t FEVT;                              /**< Force Event register, offset: 0x50 */
+  __I  uint32_t ADMAES;                            /**< ADMA Error Status register, offset: 0x54 */
+  __IO uint32_t ADSADDR;                           /**< ADMA System Addressregister, offset: 0x58 */
+       uint8_t RESERVED_1[100];
+  __IO uint32_t VENDOR;                            /**< Vendor Specific register, offset: 0xC0 */
+  __IO uint32_t MMCBOOT;                           /**< MMC Boot register, offset: 0xC4 */
+       uint8_t RESERVED_2[52];
+  __I  uint32_t HOSTVER;                           /**< Host Controller Version, offset: 0xFC */
+} SDHC_Type, *SDHC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register accessors */
+#define SDHC_DSADDR_REG(base)                    ((base)->DSADDR)
+#define SDHC_BLKATTR_REG(base)                   ((base)->BLKATTR)
+#define SDHC_CMDARG_REG(base)                    ((base)->CMDARG)
+#define SDHC_XFERTYP_REG(base)                   ((base)->XFERTYP)
+#define SDHC_CMDRSP_REG(base,index)              ((base)->CMDRSP[index])
+#define SDHC_CMDRSP_COUNT                        4
+#define SDHC_DATPORT_REG(base)                   ((base)->DATPORT)
+#define SDHC_PRSSTAT_REG(base)                   ((base)->PRSSTAT)
+#define SDHC_PROCTL_REG(base)                    ((base)->PROCTL)
+#define SDHC_SYSCTL_REG(base)                    ((base)->SYSCTL)
+#define SDHC_IRQSTAT_REG(base)                   ((base)->IRQSTAT)
+#define SDHC_IRQSTATEN_REG(base)                 ((base)->IRQSTATEN)
+#define SDHC_IRQSIGEN_REG(base)                  ((base)->IRQSIGEN)
+#define SDHC_AC12ERR_REG(base)                   ((base)->AC12ERR)
+#define SDHC_HTCAPBLT_REG(base)                  ((base)->HTCAPBLT)
+#define SDHC_WML_REG(base)                       ((base)->WML)
+#define SDHC_FEVT_REG(base)                      ((base)->FEVT)
+#define SDHC_ADMAES_REG(base)                    ((base)->ADMAES)
+#define SDHC_ADSADDR_REG(base)                   ((base)->ADSADDR)
+#define SDHC_VENDOR_REG(base)                    ((base)->VENDOR)
+#define SDHC_MMCBOOT_REG(base)                   ((base)->MMCBOOT)
+#define SDHC_HOSTVER_REG(base)                   ((base)->HOSTVER)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/* DSADDR Bit Fields */
+#define SDHC_DSADDR_DSADDR_MASK                  0xFFFFFFFCu
+#define SDHC_DSADDR_DSADDR_SHIFT                 2
+#define SDHC_DSADDR_DSADDR_WIDTH                 30
+#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
+/* BLKATTR Bit Fields */
+#define SDHC_BLKATTR_BLKSIZE_MASK                0x1FFFu
+#define SDHC_BLKATTR_BLKSIZE_SHIFT               0
+#define SDHC_BLKATTR_BLKSIZE_WIDTH               13
+#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK                 0xFFFF0000u
+#define SDHC_BLKATTR_BLKCNT_SHIFT                16
+#define SDHC_BLKATTR_BLKCNT_WIDTH                16
+#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
+/* CMDARG Bit Fields */
+#define SDHC_CMDARG_CMDARG_MASK                  0xFFFFFFFFu
+#define SDHC_CMDARG_CMDARG_SHIFT                 0
+#define SDHC_CMDARG_CMDARG_WIDTH                 32
+#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
+/* XFERTYP Bit Fields */
+#define SDHC_XFERTYP_DMAEN_MASK                  0x1u
+#define SDHC_XFERTYP_DMAEN_SHIFT                 0
+#define SDHC_XFERTYP_DMAEN_WIDTH                 1
+#define SDHC_XFERTYP_DMAEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DMAEN_SHIFT))&SDHC_XFERTYP_DMAEN_MASK)
+#define SDHC_XFERTYP_BCEN_MASK                   0x2u
+#define SDHC_XFERTYP_BCEN_SHIFT                  1
+#define SDHC_XFERTYP_BCEN_WIDTH                  1
+#define SDHC_XFERTYP_BCEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_BCEN_SHIFT))&SDHC_XFERTYP_BCEN_MASK)
+#define SDHC_XFERTYP_AC12EN_MASK                 0x4u
+#define SDHC_XFERTYP_AC12EN_SHIFT                2
+#define SDHC_XFERTYP_AC12EN_WIDTH                1
+#define SDHC_XFERTYP_AC12EN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_AC12EN_SHIFT))&SDHC_XFERTYP_AC12EN_MASK)
+#define SDHC_XFERTYP_DTDSEL_MASK                 0x10u
+#define SDHC_XFERTYP_DTDSEL_SHIFT                4
+#define SDHC_XFERTYP_DTDSEL_WIDTH                1
+#define SDHC_XFERTYP_DTDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DTDSEL_SHIFT))&SDHC_XFERTYP_DTDSEL_MASK)
+#define SDHC_XFERTYP_MSBSEL_MASK                 0x20u
+#define SDHC_XFERTYP_MSBSEL_SHIFT                5
+#define SDHC_XFERTYP_MSBSEL_WIDTH                1
+#define SDHC_XFERTYP_MSBSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_MSBSEL_SHIFT))&SDHC_XFERTYP_MSBSEL_MASK)
+#define SDHC_XFERTYP_RSPTYP_MASK                 0x30000u
+#define SDHC_XFERTYP_RSPTYP_SHIFT                16
+#define SDHC_XFERTYP_RSPTYP_WIDTH                2
+#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK                  0x80000u
+#define SDHC_XFERTYP_CCCEN_SHIFT                 19
+#define SDHC_XFERTYP_CCCEN_WIDTH                 1
+#define SDHC_XFERTYP_CCCEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CCCEN_SHIFT))&SDHC_XFERTYP_CCCEN_MASK)
+#define SDHC_XFERTYP_CICEN_MASK                  0x100000u
+#define SDHC_XFERTYP_CICEN_SHIFT                 20
+#define SDHC_XFERTYP_CICEN_WIDTH                 1
+#define SDHC_XFERTYP_CICEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CICEN_SHIFT))&SDHC_XFERTYP_CICEN_MASK)
+#define SDHC_XFERTYP_DPSEL_MASK                  0x200000u
+#define SDHC_XFERTYP_DPSEL_SHIFT                 21
+#define SDHC_XFERTYP_DPSEL_WIDTH                 1
+#define SDHC_XFERTYP_DPSEL(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DPSEL_SHIFT))&SDHC_XFERTYP_DPSEL_MASK)
+#define SDHC_XFERTYP_CMDTYP_MASK                 0xC00000u
+#define SDHC_XFERTYP_CMDTYP_SHIFT                22
+#define SDHC_XFERTYP_CMDTYP_WIDTH                2
+#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK                 0x3F000000u
+#define SDHC_XFERTYP_CMDINX_SHIFT                24
+#define SDHC_XFERTYP_CMDINX_WIDTH                6
+#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
+/* CMDRSP Bit Fields */
+#define SDHC_CMDRSP_CMDRSP0_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP0_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP0_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP1_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP1_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP2_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP2_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP3_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP3_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
+/* DATPORT Bit Fields */
+#define SDHC_DATPORT_DATCONT_MASK                0xFFFFFFFFu
+#define SDHC_DATPORT_DATCONT_SHIFT               0
+#define SDHC_DATPORT_DATCONT_WIDTH               32
+#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
+/* PRSSTAT Bit Fields */
+#define SDHC_PRSSTAT_CIHB_MASK                   0x1u
+#define SDHC_PRSSTAT_CIHB_SHIFT                  0
+#define SDHC_PRSSTAT_CIHB_WIDTH                  1
+#define SDHC_PRSSTAT_CIHB(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CIHB_SHIFT))&SDHC_PRSSTAT_CIHB_MASK)
+#define SDHC_PRSSTAT_CDIHB_MASK                  0x2u
+#define SDHC_PRSSTAT_CDIHB_SHIFT                 1
+#define SDHC_PRSSTAT_CDIHB_WIDTH                 1
+#define SDHC_PRSSTAT_CDIHB(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CDIHB_SHIFT))&SDHC_PRSSTAT_CDIHB_MASK)
+#define SDHC_PRSSTAT_DLA_MASK                    0x4u
+#define SDHC_PRSSTAT_DLA_SHIFT                   2
+#define SDHC_PRSSTAT_DLA_WIDTH                   1
+#define SDHC_PRSSTAT_DLA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLA_SHIFT))&SDHC_PRSSTAT_DLA_MASK)
+#define SDHC_PRSSTAT_SDSTB_MASK                  0x8u
+#define SDHC_PRSSTAT_SDSTB_SHIFT                 3
+#define SDHC_PRSSTAT_SDSTB_WIDTH                 1
+#define SDHC_PRSSTAT_SDSTB(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDSTB_SHIFT))&SDHC_PRSSTAT_SDSTB_MASK)
+#define SDHC_PRSSTAT_IPGOFF_MASK                 0x10u
+#define SDHC_PRSSTAT_IPGOFF_SHIFT                4
+#define SDHC_PRSSTAT_IPGOFF_WIDTH                1
+#define SDHC_PRSSTAT_IPGOFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_IPGOFF_SHIFT))&SDHC_PRSSTAT_IPGOFF_MASK)
+#define SDHC_PRSSTAT_HCKOFF_MASK                 0x20u
+#define SDHC_PRSSTAT_HCKOFF_SHIFT                5
+#define SDHC_PRSSTAT_HCKOFF_WIDTH                1
+#define SDHC_PRSSTAT_HCKOFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_HCKOFF_SHIFT))&SDHC_PRSSTAT_HCKOFF_MASK)
+#define SDHC_PRSSTAT_PEROFF_MASK                 0x40u
+#define SDHC_PRSSTAT_PEROFF_SHIFT                6
+#define SDHC_PRSSTAT_PEROFF_WIDTH                1
+#define SDHC_PRSSTAT_PEROFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_PEROFF_SHIFT))&SDHC_PRSSTAT_PEROFF_MASK)
+#define SDHC_PRSSTAT_SDOFF_MASK                  0x80u
+#define SDHC_PRSSTAT_SDOFF_SHIFT                 7
+#define SDHC_PRSSTAT_SDOFF_WIDTH                 1
+#define SDHC_PRSSTAT_SDOFF(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDOFF_SHIFT))&SDHC_PRSSTAT_SDOFF_MASK)
+#define SDHC_PRSSTAT_WTA_MASK                    0x100u
+#define SDHC_PRSSTAT_WTA_SHIFT                   8
+#define SDHC_PRSSTAT_WTA_WIDTH                   1
+#define SDHC_PRSSTAT_WTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_WTA_SHIFT))&SDHC_PRSSTAT_WTA_MASK)
+#define SDHC_PRSSTAT_RTA_MASK                    0x200u
+#define SDHC_PRSSTAT_RTA_SHIFT                   9
+#define SDHC_PRSSTAT_RTA_WIDTH                   1
+#define SDHC_PRSSTAT_RTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_RTA_SHIFT))&SDHC_PRSSTAT_RTA_MASK)
+#define SDHC_PRSSTAT_BWEN_MASK                   0x400u
+#define SDHC_PRSSTAT_BWEN_SHIFT                  10
+#define SDHC_PRSSTAT_BWEN_WIDTH                  1
+#define SDHC_PRSSTAT_BWEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BWEN_SHIFT))&SDHC_PRSSTAT_BWEN_MASK)
+#define SDHC_PRSSTAT_BREN_MASK                   0x800u
+#define SDHC_PRSSTAT_BREN_SHIFT                  11
+#define SDHC_PRSSTAT_BREN_WIDTH                  1
+#define SDHC_PRSSTAT_BREN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BREN_SHIFT))&SDHC_PRSSTAT_BREN_MASK)
+#define SDHC_PRSSTAT_CINS_MASK                   0x10000u
+#define SDHC_PRSSTAT_CINS_SHIFT                  16
+#define SDHC_PRSSTAT_CINS_WIDTH                  1
+#define SDHC_PRSSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CINS_SHIFT))&SDHC_PRSSTAT_CINS_MASK)
+#define SDHC_PRSSTAT_CLSL_MASK                   0x800000u
+#define SDHC_PRSSTAT_CLSL_SHIFT                  23
+#define SDHC_PRSSTAT_CLSL_WIDTH                  1
+#define SDHC_PRSSTAT_CLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CLSL_SHIFT))&SDHC_PRSSTAT_CLSL_MASK)
+#define SDHC_PRSSTAT_DLSL_MASK                   0xFF000000u
+#define SDHC_PRSSTAT_DLSL_SHIFT                  24
+#define SDHC_PRSSTAT_DLSL_WIDTH                  8
+#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
+/* PROCTL Bit Fields */
+#define SDHC_PROCTL_LCTL_MASK                    0x1u
+#define SDHC_PROCTL_LCTL_SHIFT                   0
+#define SDHC_PROCTL_LCTL_WIDTH                   1
+#define SDHC_PROCTL_LCTL(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_LCTL_SHIFT))&SDHC_PROCTL_LCTL_MASK)
+#define SDHC_PROCTL_DTW_MASK                     0x6u
+#define SDHC_PROCTL_DTW_SHIFT                    1
+#define SDHC_PROCTL_DTW_WIDTH                    2
+#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK                    0x8u
+#define SDHC_PROCTL_D3CD_SHIFT                   3
+#define SDHC_PROCTL_D3CD_WIDTH                   1
+#define SDHC_PROCTL_D3CD(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_D3CD_SHIFT))&SDHC_PROCTL_D3CD_MASK)
+#define SDHC_PROCTL_EMODE_MASK                   0x30u
+#define SDHC_PROCTL_EMODE_SHIFT                  4
+#define SDHC_PROCTL_EMODE_WIDTH                  2
+#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK                    0x40u
+#define SDHC_PROCTL_CDTL_SHIFT                   6
+#define SDHC_PROCTL_CDTL_WIDTH                   1
+#define SDHC_PROCTL_CDTL(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDTL_SHIFT))&SDHC_PROCTL_CDTL_MASK)
+#define SDHC_PROCTL_CDSS_MASK                    0x80u
+#define SDHC_PROCTL_CDSS_SHIFT                   7
+#define SDHC_PROCTL_CDSS_WIDTH                   1
+#define SDHC_PROCTL_CDSS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDSS_SHIFT))&SDHC_PROCTL_CDSS_MASK)
+#define SDHC_PROCTL_DMAS_MASK                    0x300u
+#define SDHC_PROCTL_DMAS_SHIFT                   8
+#define SDHC_PROCTL_DMAS_WIDTH                   2
+#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK                 0x10000u
+#define SDHC_PROCTL_SABGREQ_SHIFT                16
+#define SDHC_PROCTL_SABGREQ_WIDTH                1
+#define SDHC_PROCTL_SABGREQ(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_SABGREQ_SHIFT))&SDHC_PROCTL_SABGREQ_MASK)
+#define SDHC_PROCTL_CREQ_MASK                    0x20000u
+#define SDHC_PROCTL_CREQ_SHIFT                   17
+#define SDHC_PROCTL_CREQ_WIDTH                   1
+#define SDHC_PROCTL_CREQ(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CREQ_SHIFT))&SDHC_PROCTL_CREQ_MASK)
+#define SDHC_PROCTL_RWCTL_MASK                   0x40000u
+#define SDHC_PROCTL_RWCTL_SHIFT                  18
+#define SDHC_PROCTL_RWCTL_WIDTH                  1
+#define SDHC_PROCTL_RWCTL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_RWCTL_SHIFT))&SDHC_PROCTL_RWCTL_MASK)
+#define SDHC_PROCTL_IABG_MASK                    0x80000u
+#define SDHC_PROCTL_IABG_SHIFT                   19
+#define SDHC_PROCTL_IABG_WIDTH                   1
+#define SDHC_PROCTL_IABG(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_IABG_SHIFT))&SDHC_PROCTL_IABG_MASK)
+#define SDHC_PROCTL_WECINT_MASK                  0x1000000u
+#define SDHC_PROCTL_WECINT_SHIFT                 24
+#define SDHC_PROCTL_WECINT_WIDTH                 1
+#define SDHC_PROCTL_WECINT(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINT_SHIFT))&SDHC_PROCTL_WECINT_MASK)
+#define SDHC_PROCTL_WECINS_MASK                  0x2000000u
+#define SDHC_PROCTL_WECINS_SHIFT                 25
+#define SDHC_PROCTL_WECINS_WIDTH                 1
+#define SDHC_PROCTL_WECINS(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINS_SHIFT))&SDHC_PROCTL_WECINS_MASK)
+#define SDHC_PROCTL_WECRM_MASK                   0x4000000u
+#define SDHC_PROCTL_WECRM_SHIFT                  26
+#define SDHC_PROCTL_WECRM_WIDTH                  1
+#define SDHC_PROCTL_WECRM(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECRM_SHIFT))&SDHC_PROCTL_WECRM_MASK)
+/* SYSCTL Bit Fields */
+#define SDHC_SYSCTL_IPGEN_MASK                   0x1u
+#define SDHC_SYSCTL_IPGEN_SHIFT                  0
+#define SDHC_SYSCTL_IPGEN_WIDTH                  1
+#define SDHC_SYSCTL_IPGEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_IPGEN_SHIFT))&SDHC_SYSCTL_IPGEN_MASK)
+#define SDHC_SYSCTL_HCKEN_MASK                   0x2u
+#define SDHC_SYSCTL_HCKEN_SHIFT                  1
+#define SDHC_SYSCTL_HCKEN_WIDTH                  1
+#define SDHC_SYSCTL_HCKEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_HCKEN_SHIFT))&SDHC_SYSCTL_HCKEN_MASK)
+#define SDHC_SYSCTL_PEREN_MASK                   0x4u
+#define SDHC_SYSCTL_PEREN_SHIFT                  2
+#define SDHC_SYSCTL_PEREN_WIDTH                  1
+#define SDHC_SYSCTL_PEREN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_PEREN_SHIFT))&SDHC_SYSCTL_PEREN_MASK)
+#define SDHC_SYSCTL_SDCLKEN_MASK                 0x8u
+#define SDHC_SYSCTL_SDCLKEN_SHIFT                3
+#define SDHC_SYSCTL_SDCLKEN_WIDTH                1
+#define SDHC_SYSCTL_SDCLKEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKEN_SHIFT))&SDHC_SYSCTL_SDCLKEN_MASK)
+#define SDHC_SYSCTL_DVS_MASK                     0xF0u
+#define SDHC_SYSCTL_DVS_SHIFT                    4
+#define SDHC_SYSCTL_DVS_WIDTH                    4
+#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK                 0xFF00u
+#define SDHC_SYSCTL_SDCLKFS_SHIFT                8
+#define SDHC_SYSCTL_SDCLKFS_WIDTH                8
+#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK                   0xF0000u
+#define SDHC_SYSCTL_DTOCV_SHIFT                  16
+#define SDHC_SYSCTL_DTOCV_WIDTH                  4
+#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK                    0x1000000u
+#define SDHC_SYSCTL_RSTA_SHIFT                   24
+#define SDHC_SYSCTL_RSTA_WIDTH                   1
+#define SDHC_SYSCTL_RSTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTA_SHIFT))&SDHC_SYSCTL_RSTA_MASK)
+#define SDHC_SYSCTL_RSTC_MASK                    0x2000000u
+#define SDHC_SYSCTL_RSTC_SHIFT                   25
+#define SDHC_SYSCTL_RSTC_WIDTH                   1
+#define SDHC_SYSCTL_RSTC(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTC_SHIFT))&SDHC_SYSCTL_RSTC_MASK)
+#define SDHC_SYSCTL_RSTD_MASK                    0x4000000u
+#define SDHC_SYSCTL_RSTD_SHIFT                   26
+#define SDHC_SYSCTL_RSTD_WIDTH                   1
+#define SDHC_SYSCTL_RSTD(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTD_SHIFT))&SDHC_SYSCTL_RSTD_MASK)
+#define SDHC_SYSCTL_INITA_MASK                   0x8000000u
+#define SDHC_SYSCTL_INITA_SHIFT                  27
+#define SDHC_SYSCTL_INITA_WIDTH                  1
+#define SDHC_SYSCTL_INITA(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_INITA_SHIFT))&SDHC_SYSCTL_INITA_MASK)
+/* IRQSTAT Bit Fields */
+#define SDHC_IRQSTAT_CC_MASK                     0x1u
+#define SDHC_IRQSTAT_CC_SHIFT                    0
+#define SDHC_IRQSTAT_CC_WIDTH                    1
+#define SDHC_IRQSTAT_CC(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CC_SHIFT))&SDHC_IRQSTAT_CC_MASK)
+#define SDHC_IRQSTAT_TC_MASK                     0x2u
+#define SDHC_IRQSTAT_TC_SHIFT                    1
+#define SDHC_IRQSTAT_TC_WIDTH                    1
+#define SDHC_IRQSTAT_TC(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_TC_SHIFT))&SDHC_IRQSTAT_TC_MASK)
+#define SDHC_IRQSTAT_BGE_MASK                    0x4u
+#define SDHC_IRQSTAT_BGE_SHIFT                   2
+#define SDHC_IRQSTAT_BGE_WIDTH                   1
+#define SDHC_IRQSTAT_BGE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BGE_SHIFT))&SDHC_IRQSTAT_BGE_MASK)
+#define SDHC_IRQSTAT_DINT_MASK                   0x8u
+#define SDHC_IRQSTAT_DINT_SHIFT                  3
+#define SDHC_IRQSTAT_DINT_WIDTH                  1
+#define SDHC_IRQSTAT_DINT(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DINT_SHIFT))&SDHC_IRQSTAT_DINT_MASK)
+#define SDHC_IRQSTAT_BWR_MASK                    0x10u
+#define SDHC_IRQSTAT_BWR_SHIFT                   4
+#define SDHC_IRQSTAT_BWR_WIDTH                   1
+#define SDHC_IRQSTAT_BWR(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BWR_SHIFT))&SDHC_IRQSTAT_BWR_MASK)
+#define SDHC_IRQSTAT_BRR_MASK                    0x20u
+#define SDHC_IRQSTAT_BRR_SHIFT                   5
+#define SDHC_IRQSTAT_BRR_WIDTH                   1
+#define SDHC_IRQSTAT_BRR(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BRR_SHIFT))&SDHC_IRQSTAT_BRR_MASK)
+#define SDHC_IRQSTAT_CINS_MASK                   0x40u
+#define SDHC_IRQSTAT_CINS_SHIFT                  6
+#define SDHC_IRQSTAT_CINS_WIDTH                  1
+#define SDHC_IRQSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINS_SHIFT))&SDHC_IRQSTAT_CINS_MASK)
+#define SDHC_IRQSTAT_CRM_MASK                    0x80u
+#define SDHC_IRQSTAT_CRM_SHIFT                   7
+#define SDHC_IRQSTAT_CRM_WIDTH                   1
+#define SDHC_IRQSTAT_CRM(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CRM_SHIFT))&SDHC_IRQSTAT_CRM_MASK)
+#define SDHC_IRQSTAT_CINT_MASK                   0x100u
+#define SDHC_IRQSTAT_CINT_SHIFT                  8
+#define SDHC_IRQSTAT_CINT_WIDTH                  1
+#define SDHC_IRQSTAT_CINT(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINT_SHIFT))&SDHC_IRQSTAT_CINT_MASK)
+#define SDHC_IRQSTAT_CTOE_MASK                   0x10000u
+#define SDHC_IRQSTAT_CTOE_SHIFT                  16
+#define SDHC_IRQSTAT_CTOE_WIDTH                  1
+#define SDHC_IRQSTAT_CTOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CTOE_SHIFT))&SDHC_IRQSTAT_CTOE_MASK)
+#define SDHC_IRQSTAT_CCE_MASK                    0x20000u
+#define SDHC_IRQSTAT_CCE_SHIFT                   17
+#define SDHC_IRQSTAT_CCE_WIDTH                   1
+#define SDHC_IRQSTAT_CCE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CCE_SHIFT))&SDHC_IRQSTAT_CCE_MASK)
+#define SDHC_IRQSTAT_CEBE_MASK                   0x40000u
+#define SDHC_IRQSTAT_CEBE_SHIFT                  18
+#define SDHC_IRQSTAT_CEBE_WIDTH                  1
+#define SDHC_IRQSTAT_CEBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CEBE_SHIFT))&SDHC_IRQSTAT_CEBE_MASK)
+#define SDHC_IRQSTAT_CIE_MASK                    0x80000u
+#define SDHC_IRQSTAT_CIE_SHIFT                   19
+#define SDHC_IRQSTAT_CIE_WIDTH                   1
+#define SDHC_IRQSTAT_CIE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CIE_SHIFT))&SDHC_IRQSTAT_CIE_MASK)
+#define SDHC_IRQSTAT_DTOE_MASK                   0x100000u
+#define SDHC_IRQSTAT_DTOE_SHIFT                  20
+#define SDHC_IRQSTAT_DTOE_WIDTH                  1
+#define SDHC_IRQSTAT_DTOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DTOE_SHIFT))&SDHC_IRQSTAT_DTOE_MASK)
+#define SDHC_IRQSTAT_DCE_MASK                    0x200000u
+#define SDHC_IRQSTAT_DCE_SHIFT                   21
+#define SDHC_IRQSTAT_DCE_WIDTH                   1
+#define SDHC_IRQSTAT_DCE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DCE_SHIFT))&SDHC_IRQSTAT_DCE_MASK)
+#define SDHC_IRQSTAT_DEBE_MASK                   0x400000u
+#define SDHC_IRQSTAT_DEBE_SHIFT                  22
+#define SDHC_IRQSTAT_DEBE_WIDTH                  1
+#define SDHC_IRQSTAT_DEBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DEBE_SHIFT))&SDHC_IRQSTAT_DEBE_MASK)
+#define SDHC_IRQSTAT_AC12E_MASK                  0x1000000u
+#define SDHC_IRQSTAT_AC12E_SHIFT                 24
+#define SDHC_IRQSTAT_AC12E_WIDTH                 1
+#define SDHC_IRQSTAT_AC12E(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_AC12E_SHIFT))&SDHC_IRQSTAT_AC12E_MASK)
+#define SDHC_IRQSTAT_DMAE_MASK                   0x10000000u
+#define SDHC_IRQSTAT_DMAE_SHIFT                  28
+#define SDHC_IRQSTAT_DMAE_WIDTH                  1
+#define SDHC_IRQSTAT_DMAE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DMAE_SHIFT))&SDHC_IRQSTAT_DMAE_MASK)
+/* IRQSTATEN Bit Fields */
+#define SDHC_IRQSTATEN_CCSEN_MASK                0x1u
+#define SDHC_IRQSTATEN_CCSEN_SHIFT               0
+#define SDHC_IRQSTATEN_CCSEN_WIDTH               1
+#define SDHC_IRQSTATEN_CCSEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCSEN_SHIFT))&SDHC_IRQSTATEN_CCSEN_MASK)
+#define SDHC_IRQSTATEN_TCSEN_MASK                0x2u
+#define SDHC_IRQSTATEN_TCSEN_SHIFT               1
+#define SDHC_IRQSTATEN_TCSEN_WIDTH               1
+#define SDHC_IRQSTATEN_TCSEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_TCSEN_SHIFT))&SDHC_IRQSTATEN_TCSEN_MASK)
+#define SDHC_IRQSTATEN_BGESEN_MASK               0x4u
+#define SDHC_IRQSTATEN_BGESEN_SHIFT              2
+#define SDHC_IRQSTATEN_BGESEN_WIDTH              1
+#define SDHC_IRQSTATEN_BGESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BGESEN_SHIFT))&SDHC_IRQSTATEN_BGESEN_MASK)
+#define SDHC_IRQSTATEN_DINTSEN_MASK              0x8u
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT             3
+#define SDHC_IRQSTATEN_DINTSEN_WIDTH             1
+#define SDHC_IRQSTATEN_DINTSEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DINTSEN_SHIFT))&SDHC_IRQSTATEN_DINTSEN_MASK)
+#define SDHC_IRQSTATEN_BWRSEN_MASK               0x10u
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT              4
+#define SDHC_IRQSTATEN_BWRSEN_WIDTH              1
+#define SDHC_IRQSTATEN_BWRSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BWRSEN_SHIFT))&SDHC_IRQSTATEN_BWRSEN_MASK)
+#define SDHC_IRQSTATEN_BRRSEN_MASK               0x20u
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT              5
+#define SDHC_IRQSTATEN_BRRSEN_WIDTH              1
+#define SDHC_IRQSTATEN_BRRSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BRRSEN_SHIFT))&SDHC_IRQSTATEN_BRRSEN_MASK)
+#define SDHC_IRQSTATEN_CINSEN_MASK               0x40u
+#define SDHC_IRQSTATEN_CINSEN_SHIFT              6
+#define SDHC_IRQSTATEN_CINSEN_WIDTH              1
+#define SDHC_IRQSTATEN_CINSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINSEN_SHIFT))&SDHC_IRQSTATEN_CINSEN_MASK)
+#define SDHC_IRQSTATEN_CRMSEN_MASK               0x80u
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT              7
+#define SDHC_IRQSTATEN_CRMSEN_WIDTH              1
+#define SDHC_IRQSTATEN_CRMSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CRMSEN_SHIFT))&SDHC_IRQSTATEN_CRMSEN_MASK)
+#define SDHC_IRQSTATEN_CINTSEN_MASK              0x100u
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT             8
+#define SDHC_IRQSTATEN_CINTSEN_WIDTH             1
+#define SDHC_IRQSTATEN_CINTSEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINTSEN_SHIFT))&SDHC_IRQSTATEN_CINTSEN_MASK)
+#define SDHC_IRQSTATEN_CTOESEN_MASK              0x10000u
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT             16
+#define SDHC_IRQSTATEN_CTOESEN_WIDTH             1
+#define SDHC_IRQSTATEN_CTOESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CTOESEN_SHIFT))&SDHC_IRQSTATEN_CTOESEN_MASK)
+#define SDHC_IRQSTATEN_CCESEN_MASK               0x20000u
+#define SDHC_IRQSTATEN_CCESEN_SHIFT              17
+#define SDHC_IRQSTATEN_CCESEN_WIDTH              1
+#define SDHC_IRQSTATEN_CCESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCESEN_SHIFT))&SDHC_IRQSTATEN_CCESEN_MASK)
+#define SDHC_IRQSTATEN_CEBESEN_MASK              0x40000u
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT             18
+#define SDHC_IRQSTATEN_CEBESEN_WIDTH             1
+#define SDHC_IRQSTATEN_CEBESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CEBESEN_SHIFT))&SDHC_IRQSTATEN_CEBESEN_MASK)
+#define SDHC_IRQSTATEN_CIESEN_MASK               0x80000u
+#define SDHC_IRQSTATEN_CIESEN_SHIFT              19
+#define SDHC_IRQSTATEN_CIESEN_WIDTH              1
+#define SDHC_IRQSTATEN_CIESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CIESEN_SHIFT))&SDHC_IRQSTATEN_CIESEN_MASK)
+#define SDHC_IRQSTATEN_DTOESEN_MASK              0x100000u
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT             20
+#define SDHC_IRQSTATEN_DTOESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DTOESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DTOESEN_SHIFT))&SDHC_IRQSTATEN_DTOESEN_MASK)
+#define SDHC_IRQSTATEN_DCESEN_MASK               0x200000u
+#define SDHC_IRQSTATEN_DCESEN_SHIFT              21
+#define SDHC_IRQSTATEN_DCESEN_WIDTH              1
+#define SDHC_IRQSTATEN_DCESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DCESEN_SHIFT))&SDHC_IRQSTATEN_DCESEN_MASK)
+#define SDHC_IRQSTATEN_DEBESEN_MASK              0x400000u
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT             22
+#define SDHC_IRQSTATEN_DEBESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DEBESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DEBESEN_SHIFT))&SDHC_IRQSTATEN_DEBESEN_MASK)
+#define SDHC_IRQSTATEN_AC12ESEN_MASK             0x1000000u
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT            24
+#define SDHC_IRQSTATEN_AC12ESEN_WIDTH            1
+#define SDHC_IRQSTATEN_AC12ESEN(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_AC12ESEN_SHIFT))&SDHC_IRQSTATEN_AC12ESEN_MASK)
+#define SDHC_IRQSTATEN_DMAESEN_MASK              0x10000000u
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT             28
+#define SDHC_IRQSTATEN_DMAESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DMAESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DMAESEN_SHIFT))&SDHC_IRQSTATEN_DMAESEN_MASK)
+/* IRQSIGEN Bit Fields */
+#define SDHC_IRQSIGEN_CCIEN_MASK                 0x1u
+#define SDHC_IRQSIGEN_CCIEN_SHIFT                0
+#define SDHC_IRQSIGEN_CCIEN_WIDTH                1
+#define SDHC_IRQSIGEN_CCIEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCIEN_SHIFT))&SDHC_IRQSIGEN_CCIEN_MASK)
+#define SDHC_IRQSIGEN_TCIEN_MASK                 0x2u
+#define SDHC_IRQSIGEN_TCIEN_SHIFT                1
+#define SDHC_IRQSIGEN_TCIEN_WIDTH                1
+#define SDHC_IRQSIGEN_TCIEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_TCIEN_SHIFT))&SDHC_IRQSIGEN_TCIEN_MASK)
+#define SDHC_IRQSIGEN_BGEIEN_MASK                0x4u
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT               2
+#define SDHC_IRQSIGEN_BGEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BGEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BGEIEN_SHIFT))&SDHC_IRQSIGEN_BGEIEN_MASK)
+#define SDHC_IRQSIGEN_DINTIEN_MASK               0x8u
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT              3
+#define SDHC_IRQSIGEN_DINTIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DINTIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DINTIEN_SHIFT))&SDHC_IRQSIGEN_DINTIEN_MASK)
+#define SDHC_IRQSIGEN_BWRIEN_MASK                0x10u
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT               4
+#define SDHC_IRQSIGEN_BWRIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BWRIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BWRIEN_SHIFT))&SDHC_IRQSIGEN_BWRIEN_MASK)
+#define SDHC_IRQSIGEN_BRRIEN_MASK                0x20u
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT               5
+#define SDHC_IRQSIGEN_BRRIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BRRIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BRRIEN_SHIFT))&SDHC_IRQSIGEN_BRRIEN_MASK)
+#define SDHC_IRQSIGEN_CINSIEN_MASK               0x40u
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT              6
+#define SDHC_IRQSIGEN_CINSIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CINSIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINSIEN_SHIFT))&SDHC_IRQSIGEN_CINSIEN_MASK)
+#define SDHC_IRQSIGEN_CRMIEN_MASK                0x80u
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT               7
+#define SDHC_IRQSIGEN_CRMIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CRMIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CRMIEN_SHIFT))&SDHC_IRQSIGEN_CRMIEN_MASK)
+#define SDHC_IRQSIGEN_CINTIEN_MASK               0x100u
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT              8
+#define SDHC_IRQSIGEN_CINTIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CINTIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINTIEN_SHIFT))&SDHC_IRQSIGEN_CINTIEN_MASK)
+#define SDHC_IRQSIGEN_CTOEIEN_MASK               0x10000u
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT              16
+#define SDHC_IRQSIGEN_CTOEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CTOEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CTOEIEN_SHIFT))&SDHC_IRQSIGEN_CTOEIEN_MASK)
+#define SDHC_IRQSIGEN_CCEIEN_MASK                0x20000u
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT               17
+#define SDHC_IRQSIGEN_CCEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CCEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCEIEN_SHIFT))&SDHC_IRQSIGEN_CCEIEN_MASK)
+#define SDHC_IRQSIGEN_CEBEIEN_MASK               0x40000u
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT              18
+#define SDHC_IRQSIGEN_CEBEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CEBEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CEBEIEN_SHIFT))&SDHC_IRQSIGEN_CEBEIEN_MASK)
+#define SDHC_IRQSIGEN_CIEIEN_MASK                0x80000u
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT               19
+#define SDHC_IRQSIGEN_CIEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CIEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CIEIEN_SHIFT))&SDHC_IRQSIGEN_CIEIEN_MASK)
+#define SDHC_IRQSIGEN_DTOEIEN_MASK               0x100000u
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT              20
+#define SDHC_IRQSIGEN_DTOEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DTOEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DTOEIEN_SHIFT))&SDHC_IRQSIGEN_DTOEIEN_MASK)
+#define SDHC_IRQSIGEN_DCEIEN_MASK                0x200000u
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT               21
+#define SDHC_IRQSIGEN_DCEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_DCEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DCEIEN_SHIFT))&SDHC_IRQSIGEN_DCEIEN_MASK)
+#define SDHC_IRQSIGEN_DEBEIEN_MASK               0x400000u
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT              22
+#define SDHC_IRQSIGEN_DEBEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DEBEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DEBEIEN_SHIFT))&SDHC_IRQSIGEN_DEBEIEN_MASK)
+#define SDHC_IRQSIGEN_AC12EIEN_MASK              0x1000000u
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT             24
+#define SDHC_IRQSIGEN_AC12EIEN_WIDTH             1
+#define SDHC_IRQSIGEN_AC12EIEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_AC12EIEN_SHIFT))&SDHC_IRQSIGEN_AC12EIEN_MASK)
+#define SDHC_IRQSIGEN_DMAEIEN_MASK               0x10000000u
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT              28
+#define SDHC_IRQSIGEN_DMAEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DMAEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DMAEIEN_SHIFT))&SDHC_IRQSIGEN_DMAEIEN_MASK)
+/* AC12ERR Bit Fields */
+#define SDHC_AC12ERR_AC12NE_MASK                 0x1u
+#define SDHC_AC12ERR_AC12NE_SHIFT                0
+#define SDHC_AC12ERR_AC12NE_WIDTH                1
+#define SDHC_AC12ERR_AC12NE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12NE_SHIFT))&SDHC_AC12ERR_AC12NE_MASK)
+#define SDHC_AC12ERR_AC12TOE_MASK                0x2u
+#define SDHC_AC12ERR_AC12TOE_SHIFT               1
+#define SDHC_AC12ERR_AC12TOE_WIDTH               1
+#define SDHC_AC12ERR_AC12TOE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12TOE_SHIFT))&SDHC_AC12ERR_AC12TOE_MASK)
+#define SDHC_AC12ERR_AC12EBE_MASK                0x4u
+#define SDHC_AC12ERR_AC12EBE_SHIFT               2
+#define SDHC_AC12ERR_AC12EBE_WIDTH               1
+#define SDHC_AC12ERR_AC12EBE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12EBE_SHIFT))&SDHC_AC12ERR_AC12EBE_MASK)
+#define SDHC_AC12ERR_AC12CE_MASK                 0x8u
+#define SDHC_AC12ERR_AC12CE_SHIFT                3
+#define SDHC_AC12ERR_AC12CE_WIDTH                1
+#define SDHC_AC12ERR_AC12CE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12CE_SHIFT))&SDHC_AC12ERR_AC12CE_MASK)
+#define SDHC_AC12ERR_AC12IE_MASK                 0x10u
+#define SDHC_AC12ERR_AC12IE_SHIFT                4
+#define SDHC_AC12ERR_AC12IE_WIDTH                1
+#define SDHC_AC12ERR_AC12IE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12IE_SHIFT))&SDHC_AC12ERR_AC12IE_MASK)
+#define SDHC_AC12ERR_CNIBAC12E_MASK              0x80u
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT             7
+#define SDHC_AC12ERR_CNIBAC12E_WIDTH             1
+#define SDHC_AC12ERR_CNIBAC12E(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_CNIBAC12E_SHIFT))&SDHC_AC12ERR_CNIBAC12E_MASK)
+/* HTCAPBLT Bit Fields */
+#define SDHC_HTCAPBLT_MBL_MASK                   0x70000u
+#define SDHC_HTCAPBLT_MBL_SHIFT                  16
+#define SDHC_HTCAPBLT_MBL_WIDTH                  3
+#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK                 0x100000u
+#define SDHC_HTCAPBLT_ADMAS_SHIFT                20
+#define SDHC_HTCAPBLT_ADMAS_WIDTH                1
+#define SDHC_HTCAPBLT_ADMAS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_ADMAS_SHIFT))&SDHC_HTCAPBLT_ADMAS_MASK)
+#define SDHC_HTCAPBLT_HSS_MASK                   0x200000u
+#define SDHC_HTCAPBLT_HSS_SHIFT                  21
+#define SDHC_HTCAPBLT_HSS_WIDTH                  1
+#define SDHC_HTCAPBLT_HSS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_HSS_SHIFT))&SDHC_HTCAPBLT_HSS_MASK)
+#define SDHC_HTCAPBLT_DMAS_MASK                  0x400000u
+#define SDHC_HTCAPBLT_DMAS_SHIFT                 22
+#define SDHC_HTCAPBLT_DMAS_WIDTH                 1
+#define SDHC_HTCAPBLT_DMAS(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_DMAS_SHIFT))&SDHC_HTCAPBLT_DMAS_MASK)
+#define SDHC_HTCAPBLT_SRS_MASK                   0x800000u
+#define SDHC_HTCAPBLT_SRS_SHIFT                  23
+#define SDHC_HTCAPBLT_SRS_WIDTH                  1
+#define SDHC_HTCAPBLT_SRS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_SRS_SHIFT))&SDHC_HTCAPBLT_SRS_MASK)
+#define SDHC_HTCAPBLT_VS33_MASK                  0x1000000u
+#define SDHC_HTCAPBLT_VS33_SHIFT                 24
+#define SDHC_HTCAPBLT_VS33_WIDTH                 1
+#define SDHC_HTCAPBLT_VS33(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_VS33_SHIFT))&SDHC_HTCAPBLT_VS33_MASK)
+/* WML Bit Fields */
+#define SDHC_WML_RDWML_MASK                      0xFFu
+#define SDHC_WML_RDWML_SHIFT                     0
+#define SDHC_WML_RDWML_WIDTH                     8
+#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK                      0xFF0000u
+#define SDHC_WML_WRWML_SHIFT                     16
+#define SDHC_WML_WRWML_WIDTH                     8
+#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
+/* FEVT Bit Fields */
+#define SDHC_FEVT_AC12NE_MASK                    0x1u
+#define SDHC_FEVT_AC12NE_SHIFT                   0
+#define SDHC_FEVT_AC12NE_WIDTH                   1
+#define SDHC_FEVT_AC12NE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12NE_SHIFT))&SDHC_FEVT_AC12NE_MASK)
+#define SDHC_FEVT_AC12TOE_MASK                   0x2u
+#define SDHC_FEVT_AC12TOE_SHIFT                  1
+#define SDHC_FEVT_AC12TOE_WIDTH                  1
+#define SDHC_FEVT_AC12TOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12TOE_SHIFT))&SDHC_FEVT_AC12TOE_MASK)
+#define SDHC_FEVT_AC12CE_MASK                    0x4u
+#define SDHC_FEVT_AC12CE_SHIFT                   2
+#define SDHC_FEVT_AC12CE_WIDTH                   1
+#define SDHC_FEVT_AC12CE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12CE_SHIFT))&SDHC_FEVT_AC12CE_MASK)
+#define SDHC_FEVT_AC12EBE_MASK                   0x8u
+#define SDHC_FEVT_AC12EBE_SHIFT                  3
+#define SDHC_FEVT_AC12EBE_WIDTH                  1
+#define SDHC_FEVT_AC12EBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12EBE_SHIFT))&SDHC_FEVT_AC12EBE_MASK)
+#define SDHC_FEVT_AC12IE_MASK                    0x10u
+#define SDHC_FEVT_AC12IE_SHIFT                   4
+#define SDHC_FEVT_AC12IE_WIDTH                   1
+#define SDHC_FEVT_AC12IE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12IE_SHIFT))&SDHC_FEVT_AC12IE_MASK)
+#define SDHC_FEVT_CNIBAC12E_MASK                 0x80u
+#define SDHC_FEVT_CNIBAC12E_SHIFT                7
+#define SDHC_FEVT_CNIBAC12E_WIDTH                1
+#define SDHC_FEVT_CNIBAC12E(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CNIBAC12E_SHIFT))&SDHC_FEVT_CNIBAC12E_MASK)
+#define SDHC_FEVT_CTOE_MASK                      0x10000u
+#define SDHC_FEVT_CTOE_SHIFT                     16
+#define SDHC_FEVT_CTOE_WIDTH                     1
+#define SDHC_FEVT_CTOE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CTOE_SHIFT))&SDHC_FEVT_CTOE_MASK)
+#define SDHC_FEVT_CCE_MASK                       0x20000u
+#define SDHC_FEVT_CCE_SHIFT                      17
+#define SDHC_FEVT_CCE_WIDTH                      1
+#define SDHC_FEVT_CCE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CCE_SHIFT))&SDHC_FEVT_CCE_MASK)
+#define SDHC_FEVT_CEBE_MASK                      0x40000u
+#define SDHC_FEVT_CEBE_SHIFT                     18
+#define SDHC_FEVT_CEBE_WIDTH                     1
+#define SDHC_FEVT_CEBE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CEBE_SHIFT))&SDHC_FEVT_CEBE_MASK)
+#define SDHC_FEVT_CIE_MASK                       0x80000u
+#define SDHC_FEVT_CIE_SHIFT                      19
+#define SDHC_FEVT_CIE_WIDTH                      1
+#define SDHC_FEVT_CIE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CIE_SHIFT))&SDHC_FEVT_CIE_MASK)
+#define SDHC_FEVT_DTOE_MASK                      0x100000u
+#define SDHC_FEVT_DTOE_SHIFT                     20
+#define SDHC_FEVT_DTOE_WIDTH                     1
+#define SDHC_FEVT_DTOE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DTOE_SHIFT))&SDHC_FEVT_DTOE_MASK)
+#define SDHC_FEVT_DCE_MASK                       0x200000u
+#define SDHC_FEVT_DCE_SHIFT                      21
+#define SDHC_FEVT_DCE_WIDTH                      1
+#define SDHC_FEVT_DCE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DCE_SHIFT))&SDHC_FEVT_DCE_MASK)
+#define SDHC_FEVT_DEBE_MASK                      0x400000u
+#define SDHC_FEVT_DEBE_SHIFT                     22
+#define SDHC_FEVT_DEBE_WIDTH                     1
+#define SDHC_FEVT_DEBE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DEBE_SHIFT))&SDHC_FEVT_DEBE_MASK)
+#define SDHC_FEVT_AC12E_MASK                     0x1000000u
+#define SDHC_FEVT_AC12E_SHIFT                    24
+#define SDHC_FEVT_AC12E_WIDTH                    1
+#define SDHC_FEVT_AC12E(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12E_SHIFT))&SDHC_FEVT_AC12E_MASK)
+#define SDHC_FEVT_DMAE_MASK                      0x10000000u
+#define SDHC_FEVT_DMAE_SHIFT                     28
+#define SDHC_FEVT_DMAE_WIDTH                     1
+#define SDHC_FEVT_DMAE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DMAE_SHIFT))&SDHC_FEVT_DMAE_MASK)
+#define SDHC_FEVT_CINT_MASK                      0x80000000u
+#define SDHC_FEVT_CINT_SHIFT                     31
+#define SDHC_FEVT_CINT_WIDTH                     1
+#define SDHC_FEVT_CINT(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CINT_SHIFT))&SDHC_FEVT_CINT_MASK)
+/* ADMAES Bit Fields */
+#define SDHC_ADMAES_ADMAES_MASK                  0x3u
+#define SDHC_ADMAES_ADMAES_SHIFT                 0
+#define SDHC_ADMAES_ADMAES_WIDTH                 2
+#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK                 0x4u
+#define SDHC_ADMAES_ADMALME_SHIFT                2
+#define SDHC_ADMAES_ADMALME_WIDTH                1
+#define SDHC_ADMAES_ADMALME(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMALME_SHIFT))&SDHC_ADMAES_ADMALME_MASK)
+#define SDHC_ADMAES_ADMADCE_MASK                 0x8u
+#define SDHC_ADMAES_ADMADCE_SHIFT                3
+#define SDHC_ADMAES_ADMADCE_WIDTH                1
+#define SDHC_ADMAES_ADMADCE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMADCE_SHIFT))&SDHC_ADMAES_ADMADCE_MASK)
+/* ADSADDR Bit Fields */
+#define SDHC_ADSADDR_ADSADDR_MASK                0xFFFFFFFCu
+#define SDHC_ADSADDR_ADSADDR_SHIFT               2
+#define SDHC_ADSADDR_ADSADDR_WIDTH               30
+#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
+/* VENDOR Bit Fields */
+#define SDHC_VENDOR_EXTDMAEN_MASK                0x1u
+#define SDHC_VENDOR_EXTDMAEN_SHIFT               0
+#define SDHC_VENDOR_EXTDMAEN_WIDTH               1
+#define SDHC_VENDOR_EXTDMAEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXTDMAEN_SHIFT))&SDHC_VENDOR_EXTDMAEN_MASK)
+#define SDHC_VENDOR_EXBLKNU_MASK                 0x2u
+#define SDHC_VENDOR_EXBLKNU_SHIFT                1
+#define SDHC_VENDOR_EXBLKNU_WIDTH                1
+#define SDHC_VENDOR_EXBLKNU(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXBLKNU_SHIFT))&SDHC_VENDOR_EXBLKNU_MASK)
+#define SDHC_VENDOR_INTSTVAL_MASK                0xFF0000u
+#define SDHC_VENDOR_INTSTVAL_SHIFT               16
+#define SDHC_VENDOR_INTSTVAL_WIDTH               8
+#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
+/* MMCBOOT Bit Fields */
+#define SDHC_MMCBOOT_DTOCVACK_MASK               0xFu
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT              0
+#define SDHC_MMCBOOT_DTOCVACK_WIDTH              4
+#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK                0x10u
+#define SDHC_MMCBOOT_BOOTACK_SHIFT               4
+#define SDHC_MMCBOOT_BOOTACK_WIDTH               1
+#define SDHC_MMCBOOT_BOOTACK(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTACK_SHIFT))&SDHC_MMCBOOT_BOOTACK_MASK)
+#define SDHC_MMCBOOT_BOOTMODE_MASK               0x20u
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT              5
+#define SDHC_MMCBOOT_BOOTMODE_WIDTH              1
+#define SDHC_MMCBOOT_BOOTMODE(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTMODE_SHIFT))&SDHC_MMCBOOT_BOOTMODE_MASK)
+#define SDHC_MMCBOOT_BOOTEN_MASK                 0x40u
+#define SDHC_MMCBOOT_BOOTEN_SHIFT                6
+#define SDHC_MMCBOOT_BOOTEN_WIDTH                1
+#define SDHC_MMCBOOT_BOOTEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTEN_SHIFT))&SDHC_MMCBOOT_BOOTEN_MASK)
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK             0x80u
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            7
+#define SDHC_MMCBOOT_AUTOSABGEN_WIDTH            1
+#define SDHC_MMCBOOT_AUTOSABGEN(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_AUTOSABGEN_SHIFT))&SDHC_MMCBOOT_AUTOSABGEN_MASK)
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             0xFFFF0000u
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            16
+#define SDHC_MMCBOOT_BOOTBLKCNT_WIDTH            16
+#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+/* HOSTVER Bit Fields */
+#define SDHC_HOSTVER_SVN_MASK                    0xFFu
+#define SDHC_HOSTVER_SVN_SHIFT                   0
+#define SDHC_HOSTVER_SVN_WIDTH                   8
+#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK                    0xFF00u
+#define SDHC_HOSTVER_VVN_SHIFT                   8
+#define SDHC_HOSTVER_VVN_WIDTH                   8
+#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/** Peripheral SDHC base address */
+#define SDHC_BASE                                (0x400B1000u)
+/** Peripheral SDHC base pointer */
+#define SDHC                                     ((SDHC_Type *)SDHC_BASE)
+#define SDHC_BASE_PTR                            (SDHC)
+/** Array initializer of SDHC peripheral base addresses */
+#define SDHC_BASE_ADDRS                          { SDHC_BASE }
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASE_PTRS                           { SDHC }
+/** Interrupt vectors for the SDHC peripheral type */
+#define SDHC_IRQS                                { SDHC_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register instance definitions */
+/* SDHC */
+#define SDHC_DSADDR                              SDHC_DSADDR_REG(SDHC)
+#define SDHC_BLKATTR                             SDHC_BLKATTR_REG(SDHC)
+#define SDHC_CMDARG                              SDHC_CMDARG_REG(SDHC)
+#define SDHC_XFERTYP                             SDHC_XFERTYP_REG(SDHC)
+#define SDHC_CMDRSP0                             SDHC_CMDRSP_REG(SDHC,0)
+#define SDHC_CMDRSP1                             SDHC_CMDRSP_REG(SDHC,1)
+#define SDHC_CMDRSP2                             SDHC_CMDRSP_REG(SDHC,2)
+#define SDHC_CMDRSP3                             SDHC_CMDRSP_REG(SDHC,3)
+#define SDHC_DATPORT                             SDHC_DATPORT_REG(SDHC)
+#define SDHC_PRSSTAT                             SDHC_PRSSTAT_REG(SDHC)
+#define SDHC_PROCTL                              SDHC_PROCTL_REG(SDHC)
+#define SDHC_SYSCTL                              SDHC_SYSCTL_REG(SDHC)
+#define SDHC_IRQSTAT                             SDHC_IRQSTAT_REG(SDHC)
+#define SDHC_IRQSTATEN                           SDHC_IRQSTATEN_REG(SDHC)
+#define SDHC_IRQSIGEN                            SDHC_IRQSIGEN_REG(SDHC)
+#define SDHC_AC12ERR                             SDHC_AC12ERR_REG(SDHC)
+#define SDHC_HTCAPBLT                            SDHC_HTCAPBLT_REG(SDHC)
+#define SDHC_WML                                 SDHC_WML_REG(SDHC)
+#define SDHC_FEVT                                SDHC_FEVT_REG(SDHC)
+#define SDHC_ADMAES                              SDHC_ADMAES_REG(SDHC)
+#define SDHC_ADSADDR                             SDHC_ADSADDR_REG(SDHC)
+#define SDHC_VENDOR                              SDHC_VENDOR_REG(SDHC)
+#define SDHC_MMCBOOT                             SDHC_MMCBOOT_REG(SDHC)
+#define SDHC_HOSTVER                             SDHC_HOSTVER_REG(SDHC)
+
+/* SDHC - Register array accessors */
+#define SDHC_CMDRSP(index)                       SDHC_CMDRSP_REG(SDHC,index)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
+       uint8_t RESERVED_0[4092];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+  __IO uint32_t SCGC1;                             /**< System Clock Gating Control Register 1, offset: 0x1028 */
+  __IO uint32_t SCGC2;                             /**< System Clock Gating Control Register 2, offset: 0x102C */
+  __IO uint32_t SCGC3;                             /**< System Clock Gating Control Register 3, offset: 0x1030 */
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+  __IO uint32_t CLKDIV2;                           /**< System Clock Divider Register 2, offset: 0x1048 */
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+  __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base)                      ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base)                   ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base)                      ((base)->SOPT2)
+#define SIM_SOPT4_REG(base)                      ((base)->SOPT4)
+#define SIM_SOPT5_REG(base)                      ((base)->SOPT5)
+#define SIM_SOPT7_REG(base)                      ((base)->SOPT7)
+#define SIM_SDID_REG(base)                       ((base)->SDID)
+#define SIM_SCGC1_REG(base)                      ((base)->SCGC1)
+#define SIM_SCGC2_REG(base)                      ((base)->SCGC2)
+#define SIM_SCGC3_REG(base)                      ((base)->SCGC3)
+#define SIM_SCGC4_REG(base)                      ((base)->SCGC4)
+#define SIM_SCGC5_REG(base)                      ((base)->SCGC5)
+#define SIM_SCGC6_REG(base)                      ((base)->SCGC6)
+#define SIM_SCGC7_REG(base)                      ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base)                    ((base)->CLKDIV1)
+#define SIM_CLKDIV2_REG(base)                    ((base)->CLKDIV2)
+#define SIM_FCFG1_REG(base)                      ((base)->FCFG1)
+#define SIM_FCFG2_REG(base)                      ((base)->FCFG2)
+#define SIM_UIDH_REG(base)                       ((base)->UIDH)
+#define SIM_UIDMH_REG(base)                      ((base)->UIDMH)
+#define SIM_UIDML_REG(base)                      ((base)->UIDML)
+#define SIM_UIDL_REG(base)                       ((base)->UIDL)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK                   0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT                  12
+#define SIM_SOPT1_RAMSIZE_WIDTH                  4
+#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT                18
+#define SIM_SOPT1_OSC32KSEL_WIDTH                2
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK                  0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT                 29
+#define SIM_SOPT1_USBVSTBY_WIDTH                 1
+#define SIM_SOPT1_USBVSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBVSTBY_SHIFT))&SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK                  0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT                 30
+#define SIM_SOPT1_USBSSTBY_WIDTH                 1
+#define SIM_SOPT1_USBSSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBSSTBY_SHIFT))&SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK                  0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT                 31
+#define SIM_SOPT1_USBREGEN_WIDTH                 1
+#define SIM_SOPT1_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBREGEN_SHIFT))&SIM_SOPT1_USBREGEN_MASK)
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK                   0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT                  24
+#define SIM_SOPT1CFG_URWE_WIDTH                  1
+#define SIM_SOPT1CFG_URWE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_URWE_SHIFT))&SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK                  0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT                 25
+#define SIM_SOPT1CFG_UVSWE_WIDTH                 1
+#define SIM_SOPT1CFG_UVSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_UVSWE_SHIFT))&SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK                  0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT                 26
+#define SIM_SOPT1CFG_USSWE_WIDTH                 1
+#define SIM_SOPT1CFG_USSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_USSWE_SHIFT))&SIM_SOPT1CFG_USSWE_MASK)
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
+#define SIM_SOPT2_RTCCLKOUTSEL_WIDTH             1
+#define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                5
+#define SIM_SOPT2_CLKOUTSEL_WIDTH                3
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK                      0x300u
+#define SIM_SOPT2_FBSL_SHIFT                     8
+#define SIM_SOPT2_FBSL_WIDTH                     2
+#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK                   0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT                  11
+#define SIM_SOPT2_PTD7PAD_WIDTH                  1
+#define SIM_SOPT2_PTD7PAD(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PTD7PAD_SHIFT))&SIM_SOPT2_PTD7PAD_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK               0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT              12
+#define SIM_SOPT2_TRACECLKSEL_WIDTH              1
+#define SIM_SOPT2_TRACECLKSEL(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TRACECLKSEL_SHIFT))&SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK                 0x30000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                16
+#define SIM_SOPT2_PLLFLLSEL_WIDTH                2
+#define SIM_SOPT2_PLLFLLSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK                    0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT                   18
+#define SIM_SOPT2_USBSRC_WIDTH                   1
+#define SIM_SOPT2_USBSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_RMIISRC_MASK                   0x80000u
+#define SIM_SOPT2_RMIISRC_SHIFT                  19
+#define SIM_SOPT2_RMIISRC_WIDTH                  1
+#define SIM_SOPT2_RMIISRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RMIISRC_SHIFT))&SIM_SOPT2_RMIISRC_MASK)
+#define SIM_SOPT2_TIMESRC_MASK                   0x300000u
+#define SIM_SOPT2_TIMESRC_SHIFT                  20
+#define SIM_SOPT2_TIMESRC_WIDTH                  2
+#define SIM_SOPT2_TIMESRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK                   0x30000000u
+#define SIM_SOPT2_SDHCSRC_SHIFT                  28
+#define SIM_SOPT2_SDHCSRC_WIDTH                  2
+#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK                  0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT                 0
+#define SIM_SOPT4_FTM0FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT0_SHIFT))&SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK                  0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT                 1
+#define SIM_SOPT4_FTM0FLT1_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT1_SHIFT))&SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM0FLT2_MASK                  0x4u
+#define SIM_SOPT4_FTM0FLT2_SHIFT                 2
+#define SIM_SOPT4_FTM0FLT2_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT2(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT2_SHIFT))&SIM_SOPT4_FTM0FLT2_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK                  0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT                 4
+#define SIM_SOPT4_FTM1FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM1FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1FLT0_SHIFT))&SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_MASK                  0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT                 8
+#define SIM_SOPT4_FTM2FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM2FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2FLT0_SHIFT))&SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM3FLT0_MASK                  0x1000u
+#define SIM_SOPT4_FTM3FLT0_SHIFT                 12
+#define SIM_SOPT4_FTM3FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM3FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3FLT0_SHIFT))&SIM_SOPT4_FTM3FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK                0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT               18
+#define SIM_SOPT4_FTM1CH0SRC_WIDTH               2
+#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK                0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT               20
+#define SIM_SOPT4_FTM2CH0SRC_WIDTH               2
+#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK                0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT               24
+#define SIM_SOPT4_FTM0CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0CLKSEL_SHIFT))&SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK                0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT               25
+#define SIM_SOPT4_FTM1CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CLKSEL_SHIFT))&SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_MASK                0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT               26
+#define SIM_SOPT4_FTM2CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CLKSEL_SHIFT))&SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM3CLKSEL_MASK                0x8000000u
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT               27
+#define SIM_SOPT4_FTM3CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM3CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3CLKSEL_SHIFT))&SIM_SOPT4_FTM3CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK               0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT              28
+#define SIM_SOPT4_FTM0TRG0SRC_WIDTH              1
+#define SIM_SOPT4_FTM0TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG0SRC_SHIFT))&SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_MASK               0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT              29
+#define SIM_SOPT4_FTM0TRG1SRC_WIDTH              1
+#define SIM_SOPT4_FTM0TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG1SRC_SHIFT))&SIM_SOPT4_FTM0TRG1SRC_MASK)
+#define SIM_SOPT4_FTM3TRG0SRC_MASK               0x40000000u
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT              30
+#define SIM_SOPT4_FTM3TRG0SRC_WIDTH              1
+#define SIM_SOPT4_FTM3TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG0SRC_SHIFT))&SIM_SOPT4_FTM3TRG0SRC_MASK)
+#define SIM_SOPT4_FTM3TRG1SRC_MASK               0x80000000u
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT              31
+#define SIM_SOPT4_FTM3TRG1SRC_WIDTH              1
+#define SIM_SOPT4_FTM3TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG1SRC_SHIFT))&SIM_SOPT4_FTM3TRG1SRC_MASK)
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK                0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT               0
+#define SIM_SOPT5_UART0TXSRC_WIDTH               2
+#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK                0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT               2
+#define SIM_SOPT5_UART0RXSRC_WIDTH               2
+#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK                0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT               4
+#define SIM_SOPT5_UART1TXSRC_WIDTH               2
+#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK                0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT               6
+#define SIM_SOPT5_UART1RXSRC_WIDTH               2
+#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
+#define SIM_SOPT7_ADC0TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
+#define SIM_SOPT7_ADC0PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
+#define SIM_SOPT7_ADC0ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_MASK                0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT               8
+#define SIM_SOPT7_ADC1TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK             0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            12
+#define SIM_SOPT7_ADC1PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC1PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1PRETRGSEL_SHIFT))&SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK              0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             15
+#define SIM_SOPT7_ADC1ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC1ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1ALTTRGEN_SHIFT))&SIM_SOPT7_ADC1ALTTRGEN_MASK)
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK                      0xFu
+#define SIM_SDID_PINID_SHIFT                     0
+#define SIM_SDID_PINID_WIDTH                     4
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK                      0x70u
+#define SIM_SDID_FAMID_SHIFT                     4
+#define SIM_SDID_FAMID_WIDTH                     3
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK                      0xF80u
+#define SIM_SDID_DIEID_SHIFT                     7
+#define SIM_SDID_DIEID_WIDTH                     5
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      0xF000u
+#define SIM_SDID_REVID_SHIFT                     12
+#define SIM_SDID_REVID_WIDTH                     4
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK                   0xF00000u
+#define SIM_SDID_SERIESID_SHIFT                  20
+#define SIM_SDID_SERIESID_WIDTH                  4
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT                  24
+#define SIM_SDID_SUBFAMID_WIDTH                  4
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK                   0xF0000000u
+#define SIM_SDID_FAMILYID_SHIFT                  28
+#define SIM_SDID_FAMILYID_WIDTH                  4
+#define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
+/* SCGC1 Bit Fields */
+#define SIM_SCGC1_I2C2_MASK                      0x40u
+#define SIM_SCGC1_I2C2_SHIFT                     6
+#define SIM_SCGC1_I2C2_WIDTH                     1
+#define SIM_SCGC1_I2C2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_I2C2_SHIFT))&SIM_SCGC1_I2C2_MASK)
+#define SIM_SCGC1_UART4_MASK                     0x400u
+#define SIM_SCGC1_UART4_SHIFT                    10
+#define SIM_SCGC1_UART4_WIDTH                    1
+#define SIM_SCGC1_UART4(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART4_SHIFT))&SIM_SCGC1_UART4_MASK)
+#define SIM_SCGC1_UART5_MASK                     0x800u
+#define SIM_SCGC1_UART5_SHIFT                    11
+#define SIM_SCGC1_UART5_WIDTH                    1
+#define SIM_SCGC1_UART5(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART5_SHIFT))&SIM_SCGC1_UART5_MASK)
+/* SCGC2 Bit Fields */
+#define SIM_SCGC2_ENET_MASK                      0x1u
+#define SIM_SCGC2_ENET_SHIFT                     0
+#define SIM_SCGC2_ENET_WIDTH                     1
+#define SIM_SCGC2_ENET(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_ENET_SHIFT))&SIM_SCGC2_ENET_MASK)
+#define SIM_SCGC2_DAC0_MASK                      0x1000u
+#define SIM_SCGC2_DAC0_SHIFT                     12
+#define SIM_SCGC2_DAC0_WIDTH                     1
+#define SIM_SCGC2_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC0_SHIFT))&SIM_SCGC2_DAC0_MASK)
+#define SIM_SCGC2_DAC1_MASK                      0x2000u
+#define SIM_SCGC2_DAC1_SHIFT                     13
+#define SIM_SCGC2_DAC1_WIDTH                     1
+#define SIM_SCGC2_DAC1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC1_SHIFT))&SIM_SCGC2_DAC1_MASK)
+/* SCGC3 Bit Fields */
+#define SIM_SCGC3_RNGA_MASK                      0x1u
+#define SIM_SCGC3_RNGA_SHIFT                     0
+#define SIM_SCGC3_RNGA_WIDTH                     1
+#define SIM_SCGC3_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_RNGA_SHIFT))&SIM_SCGC3_RNGA_MASK)
+#define SIM_SCGC3_SPI2_MASK                      0x1000u
+#define SIM_SCGC3_SPI2_SHIFT                     12
+#define SIM_SCGC3_SPI2_WIDTH                     1
+#define SIM_SCGC3_SPI2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SPI2_SHIFT))&SIM_SCGC3_SPI2_MASK)
+#define SIM_SCGC3_SDHC_MASK                      0x20000u
+#define SIM_SCGC3_SDHC_SHIFT                     17
+#define SIM_SCGC3_SDHC_WIDTH                     1
+#define SIM_SCGC3_SDHC(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SDHC_SHIFT))&SIM_SCGC3_SDHC_MASK)
+#define SIM_SCGC3_FTM2_MASK                      0x1000000u
+#define SIM_SCGC3_FTM2_SHIFT                     24
+#define SIM_SCGC3_FTM2_WIDTH                     1
+#define SIM_SCGC3_FTM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM2_SHIFT))&SIM_SCGC3_FTM2_MASK)
+#define SIM_SCGC3_FTM3_MASK                      0x2000000u
+#define SIM_SCGC3_FTM3_SHIFT                     25
+#define SIM_SCGC3_FTM3_WIDTH                     1
+#define SIM_SCGC3_FTM3(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM3_SHIFT))&SIM_SCGC3_FTM3_MASK)
+#define SIM_SCGC3_ADC1_MASK                      0x8000000u
+#define SIM_SCGC3_ADC1_SHIFT                     27
+#define SIM_SCGC3_ADC1_WIDTH                     1
+#define SIM_SCGC3_ADC1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_ADC1_SHIFT))&SIM_SCGC3_ADC1_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK                       0x2u
+#define SIM_SCGC4_EWM_SHIFT                      1
+#define SIM_SCGC4_EWM_WIDTH                      1
+#define SIM_SCGC4_EWM(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_EWM_SHIFT))&SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_CMT_MASK                       0x4u
+#define SIM_SCGC4_CMT_SHIFT                      2
+#define SIM_SCGC4_CMT_WIDTH                      1
+#define SIM_SCGC4_CMT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMT_SHIFT))&SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_I2C0_MASK                      0x40u
+#define SIM_SCGC4_I2C0_SHIFT                     6
+#define SIM_SCGC4_I2C0_WIDTH                     1
+#define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C0_SHIFT))&SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK                      0x80u
+#define SIM_SCGC4_I2C1_SHIFT                     7
+#define SIM_SCGC4_I2C1_WIDTH                     1
+#define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C1_SHIFT))&SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK                     0x400u
+#define SIM_SCGC4_UART0_SHIFT                    10
+#define SIM_SCGC4_UART0_WIDTH                    1
+#define SIM_SCGC4_UART0(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART0_SHIFT))&SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK                     0x800u
+#define SIM_SCGC4_UART1_SHIFT                    11
+#define SIM_SCGC4_UART1_WIDTH                    1
+#define SIM_SCGC4_UART1(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART1_SHIFT))&SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK                     0x1000u
+#define SIM_SCGC4_UART2_SHIFT                    12
+#define SIM_SCGC4_UART2_WIDTH                    1
+#define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_UART3_MASK                     0x2000u
+#define SIM_SCGC4_UART3_SHIFT                    13
+#define SIM_SCGC4_UART3_WIDTH                    1
+#define SIM_SCGC4_UART3(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART3_SHIFT))&SIM_SCGC4_UART3_MASK)
+#define SIM_SCGC4_USBOTG_MASK                    0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT                   18
+#define SIM_SCGC4_USBOTG_WIDTH                   1
+#define SIM_SCGC4_USBOTG(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBOTG_SHIFT))&SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK                       0x80000u
+#define SIM_SCGC4_CMP_SHIFT                      19
+#define SIM_SCGC4_CMP_WIDTH                      1
+#define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK                      0x100000u
+#define SIM_SCGC4_VREF_SHIFT                     20
+#define SIM_SCGC4_VREF_WIDTH                     1
+#define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_VREF_SHIFT))&SIM_SCGC4_VREF_MASK)
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK                     0x1u
+#define SIM_SCGC5_LPTMR_SHIFT                    0
+#define SIM_SCGC5_LPTMR_WIDTH                    1
+#define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_PORTA_MASK                     0x200u
+#define SIM_SCGC5_PORTA_SHIFT                    9
+#define SIM_SCGC5_PORTA_WIDTH                    1
+#define SIM_SCGC5_PORTA(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK                     0x400u
+#define SIM_SCGC5_PORTB_SHIFT                    10
+#define SIM_SCGC5_PORTB_WIDTH                    1
+#define SIM_SCGC5_PORTB(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK                     0x800u
+#define SIM_SCGC5_PORTC_SHIFT                    11
+#define SIM_SCGC5_PORTC_WIDTH                    1
+#define SIM_SCGC5_PORTC(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK                     0x1000u
+#define SIM_SCGC5_PORTD_SHIFT                    12
+#define SIM_SCGC5_PORTD_WIDTH                    1
+#define SIM_SCGC5_PORTD(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK                     0x2000u
+#define SIM_SCGC5_PORTE_SHIFT                    13
+#define SIM_SCGC5_PORTE_WIDTH                    1
+#define SIM_SCGC5_PORTE(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK                       0x1u
+#define SIM_SCGC6_FTF_SHIFT                      0
+#define SIM_SCGC6_FTF_WIDTH                      1
+#define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK                    0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT                   1
+#define SIM_SCGC6_DMAMUX_WIDTH                   1
+#define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_FLEXCAN0_MASK                  0x10u
+#define SIM_SCGC6_FLEXCAN0_SHIFT                 4
+#define SIM_SCGC6_FLEXCAN0_WIDTH                 1
+#define SIM_SCGC6_FLEXCAN0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FLEXCAN0_SHIFT))&SIM_SCGC6_FLEXCAN0_MASK)
+#define SIM_SCGC6_RNGA_MASK                      0x200u
+#define SIM_SCGC6_RNGA_SHIFT                     9
+#define SIM_SCGC6_RNGA_WIDTH                     1
+#define SIM_SCGC6_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RNGA_SHIFT))&SIM_SCGC6_RNGA_MASK)
+#define SIM_SCGC6_SPI0_MASK                      0x1000u
+#define SIM_SCGC6_SPI0_SHIFT                     12
+#define SIM_SCGC6_SPI0_WIDTH                     1
+#define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI0_SHIFT))&SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK                      0x2000u
+#define SIM_SCGC6_SPI1_SHIFT                     13
+#define SIM_SCGC6_SPI1_WIDTH                     1
+#define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI1_SHIFT))&SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_I2S_MASK                       0x8000u
+#define SIM_SCGC6_I2S_SHIFT                      15
+#define SIM_SCGC6_I2S_WIDTH                      1
+#define SIM_SCGC6_I2S(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S_SHIFT))&SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK                       0x40000u
+#define SIM_SCGC6_CRC_SHIFT                      18
+#define SIM_SCGC6_CRC_WIDTH                      1
+#define SIM_SCGC6_CRC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_CRC_SHIFT))&SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_USBDCD_MASK                    0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT                   21
+#define SIM_SCGC6_USBDCD_WIDTH                   1
+#define SIM_SCGC6_USBDCD(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_USBDCD_SHIFT))&SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_PDB_MASK                       0x400000u
+#define SIM_SCGC6_PDB_SHIFT                      22
+#define SIM_SCGC6_PDB_WIDTH                      1
+#define SIM_SCGC6_PDB(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PDB_SHIFT))&SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK                       0x800000u
+#define SIM_SCGC6_PIT_SHIFT                      23
+#define SIM_SCGC6_PIT_WIDTH                      1
+#define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK                      0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT                     24
+#define SIM_SCGC6_FTM0_WIDTH                     1
+#define SIM_SCGC6_FTM0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM0_SHIFT))&SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK                      0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT                     25
+#define SIM_SCGC6_FTM1_WIDTH                     1
+#define SIM_SCGC6_FTM1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM1_SHIFT))&SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM2_MASK                      0x4000000u
+#define SIM_SCGC6_FTM2_SHIFT                     26
+#define SIM_SCGC6_FTM2_WIDTH                     1
+#define SIM_SCGC6_FTM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM2_SHIFT))&SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_ADC0_MASK                      0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT                     27
+#define SIM_SCGC6_ADC0_WIDTH                     1
+#define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK                       0x20000000u
+#define SIM_SCGC6_RTC_SHIFT                      29
+#define SIM_SCGC6_RTC_WIDTH                      1
+#define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK                      0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT                     31
+#define SIM_SCGC6_DAC0_WIDTH                     1
+#define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_FLEXBUS_MASK                   0x1u
+#define SIM_SCGC7_FLEXBUS_SHIFT                  0
+#define SIM_SCGC7_FLEXBUS_WIDTH                  1
+#define SIM_SCGC7_FLEXBUS(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_FLEXBUS_SHIFT))&SIM_SCGC7_FLEXBUS_MASK)
+#define SIM_SCGC7_DMA_MASK                       0x2u
+#define SIM_SCGC7_DMA_SHIFT                      1
+#define SIM_SCGC7_DMA_WIDTH                      1
+#define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_MPU_MASK                       0x4u
+#define SIM_SCGC7_MPU_SHIFT                      2
+#define SIM_SCGC7_MPU_WIDTH                      1
+#define SIM_SCGC7_MPU(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_MPU_SHIFT))&SIM_SCGC7_MPU_MASK)
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
+#define SIM_CLKDIV1_OUTDIV4_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK                 0xF00000u
+#define SIM_CLKDIV1_OUTDIV3_SHIFT                20
+#define SIM_CLKDIV1_OUTDIV3_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV3(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK                 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT                24
+#define SIM_CLKDIV1_OUTDIV2_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
+#define SIM_CLKDIV1_OUTDIV1_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK                 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT                0
+#define SIM_CLKDIV2_USBFRAC_WIDTH                1
+#define SIM_CLKDIV2_USBFRAC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBFRAC_SHIFT))&SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK                  0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT                 1
+#define SIM_CLKDIV2_USBDIV_WIDTH                 3
+#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK                  0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT                 0
+#define SIM_FCFG1_FLASHDIS_WIDTH                 1
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT                1
+#define SIM_FCFG1_FLASHDOZE_WIDTH                1
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_DEPART_MASK                    0xF00u
+#define SIM_FCFG1_DEPART_SHIFT                   8
+#define SIM_FCFG1_DEPART_WIDTH                   4
+#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK                    0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT                   16
+#define SIM_FCFG1_EESIZE_WIDTH                   4
+#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT                   24
+#define SIM_FCFG1_PFSIZE_WIDTH                   4
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK                   0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT                  28
+#define SIM_FCFG1_NVMSIZE_WIDTH                  4
+#define SIM_FCFG1_NVMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK                  0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT                 16
+#define SIM_FCFG2_MAXADDR1_WIDTH                 7
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK                     0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT                    23
+#define SIM_FCFG2_PFLSH_WIDTH                    1
+#define SIM_FCFG2_PFLSH(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_PFLSH_SHIFT))&SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK                  0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT                 24
+#define SIM_FCFG2_MAXADDR0_WIDTH                 7
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT                       0
+#define SIM_UIDH_UID_WIDTH                       32
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT                      0
+#define SIM_UIDMH_UID_WIDTH                      32
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT                      0
+#define SIM_UIDML_UID_WIDTH                      32
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT                       0
+#define SIM_UIDL_UID_WIDTH                       32
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR                             (SIM)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1                                SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG                             SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2                                SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4                                SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5                                SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7                                SIM_SOPT7_REG(SIM)
+#define SIM_SDID                                 SIM_SDID_REG(SIM)
+#define SIM_SCGC1                                SIM_SCGC1_REG(SIM)
+#define SIM_SCGC2                                SIM_SCGC2_REG(SIM)
+#define SIM_SCGC3                                SIM_SCGC3_REG(SIM)
+#define SIM_SCGC4                                SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5                                SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6                                SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7                                SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1                              SIM_CLKDIV1_REG(SIM)
+#define SIM_CLKDIV2                              SIM_CLKDIV2_REG(SIM)
+#define SIM_FCFG1                                SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2                                SIM_FCFG2_REG(SIM)
+#define SIM_UIDH                                 SIM_UIDH_REG(SIM)
+#define SIM_UIDMH                                SIM_UIDMH_REG(SIM)
+#define SIM_UIDML                                SIM_UIDML_REG(SIM)
+#define SIM_UIDL                                 SIM_UIDL_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t VLLSCTRL;                           /**< VLLS Control register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base)                     ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base)                     ((base)->PMCTRL)
+#define SMC_VLLSCTRL_REG(base)                   ((base)->VLLSCTRL)
+#define SMC_PMSTAT_REG(base)                     ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK                    0x2u
+#define SMC_PMPROT_AVLLS_SHIFT                   1
+#define SMC_PMPROT_AVLLS_WIDTH                   1
+#define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK                     0x8u
+#define SMC_PMPROT_ALLS_SHIFT                    3
+#define SMC_PMPROT_ALLS_WIDTH                    1
+#define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK                     0x20u
+#define SMC_PMPROT_AVLP_SHIFT                    5
+#define SMC_PMPROT_AVLP_WIDTH                    1
+#define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK                    0x7u
+#define SMC_PMCTRL_STOPM_SHIFT                   0
+#define SMC_PMCTRL_STOPM_WIDTH                   3
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK                    0x8u
+#define SMC_PMCTRL_STOPA_SHIFT                   3
+#define SMC_PMCTRL_STOPA_WIDTH                   1
+#define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK                     0x60u
+#define SMC_PMCTRL_RUNM_SHIFT                    5
+#define SMC_PMCTRL_RUNM_WIDTH                    2
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK                    0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT                   7
+#define SMC_PMCTRL_LPWUI_WIDTH                   1
+#define SMC_PMCTRL_LPWUI(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_LPWUI_SHIFT))&SMC_PMCTRL_LPWUI_MASK)
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK                  0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT                 0
+#define SMC_VLLSCTRL_VLLSM_WIDTH                 3
+#define SMC_VLLSCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK                  0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT                 5
+#define SMC_VLLSCTRL_PORPO_WIDTH                 1
+#define SMC_VLLSCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_PORPO_SHIFT))&SMC_VLLSCTRL_PORPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK                   0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT                  0
+#define SMC_PMSTAT_PMSTAT_WIDTH                  7
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR                             (SMC)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC }
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT                               SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL                               SMC_PMCTRL_REG(SMC)
+#define SMC_VLLSCTRL                             SMC_VLLSCTRL_REG(SMC)
+#define SMC_PMSTAT                               SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+    __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+  };
+       uint8_t RESERVED_1[24];
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
+  __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+  union {                                          /* offset: 0x34 */
+    __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+    __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+  };
+  __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
+  __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
+  __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
+  __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
+  __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
+       uint8_t RESERVED_2[48];
+  __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
+  __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
+  __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
+  __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_MCR_REG(base)                        ((base)->MCR)
+#define SPI_TCR_REG(base)                        ((base)->TCR)
+#define SPI_CTAR_REG(base,index2)                ((base)->CTAR[index2])
+#define SPI_CTAR_COUNT                           2
+#define SPI_CTAR_SLAVE_REG(base,index2)          ((base)->CTAR_SLAVE[index2])
+#define SPI_CTAR_SLAVE_COUNT                     1
+#define SPI_SR_REG(base)                         ((base)->SR)
+#define SPI_RSER_REG(base)                       ((base)->RSER)
+#define SPI_PUSHR_REG(base)                      ((base)->PUSHR)
+#define SPI_PUSHR_SLAVE_REG(base)                ((base)->PUSHR_SLAVE)
+#define SPI_POPR_REG(base)                       ((base)->POPR)
+#define SPI_TXFR0_REG(base)                      ((base)->TXFR0)
+#define SPI_TXFR1_REG(base)                      ((base)->TXFR1)
+#define SPI_TXFR2_REG(base)                      ((base)->TXFR2)
+#define SPI_TXFR3_REG(base)                      ((base)->TXFR3)
+#define SPI_RXFR0_REG(base)                      ((base)->RXFR0)
+#define SPI_RXFR1_REG(base)                      ((base)->RXFR1)
+#define SPI_RXFR2_REG(base)                      ((base)->RXFR2)
+#define SPI_RXFR3_REG(base)                      ((base)->RXFR3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK                        0x1u
+#define SPI_MCR_HALT_SHIFT                       0
+#define SPI_MCR_HALT_WIDTH                       1
+#define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_HALT_SHIFT))&SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK                     0x300u
+#define SPI_MCR_SMPL_PT_SHIFT                    8
+#define SPI_MCR_SMPL_PT_WIDTH                    2
+#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK                     0x400u
+#define SPI_MCR_CLR_RXF_SHIFT                    10
+#define SPI_MCR_CLR_RXF_WIDTH                    1
+#define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_RXF_SHIFT))&SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK                     0x800u
+#define SPI_MCR_CLR_TXF_SHIFT                    11
+#define SPI_MCR_CLR_TXF_WIDTH                    1
+#define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_TXF_SHIFT))&SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK                     0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT                    12
+#define SPI_MCR_DIS_RXF_WIDTH                    1
+#define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_RXF_SHIFT))&SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK                     0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT                    13
+#define SPI_MCR_DIS_TXF_WIDTH                    1
+#define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_TXF_SHIFT))&SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK                        0x4000u
+#define SPI_MCR_MDIS_SHIFT                       14
+#define SPI_MCR_MDIS_WIDTH                       1
+#define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MDIS_SHIFT))&SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK                        0x8000u
+#define SPI_MCR_DOZE_SHIFT                       15
+#define SPI_MCR_DOZE_WIDTH                       1
+#define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DOZE_SHIFT))&SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK                       0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT                      16
+#define SPI_MCR_PCSIS_WIDTH                      6
+#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK                        0x1000000u
+#define SPI_MCR_ROOE_SHIFT                       24
+#define SPI_MCR_ROOE_WIDTH                       1
+#define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_ROOE_SHIFT))&SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK                       0x2000000u
+#define SPI_MCR_PCSSE_SHIFT                      25
+#define SPI_MCR_PCSSE_WIDTH                      1
+#define SPI_MCR_PCSSE(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSSE_SHIFT))&SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK                        0x4000000u
+#define SPI_MCR_MTFE_SHIFT                       26
+#define SPI_MCR_MTFE_WIDTH                       1
+#define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MTFE_SHIFT))&SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK                         0x8000000u
+#define SPI_MCR_FRZ_SHIFT                        27
+#define SPI_MCR_FRZ_WIDTH                        1
+#define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_MCR_FRZ_SHIFT))&SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK                       0x30000000u
+#define SPI_MCR_DCONF_SHIFT                      28
+#define SPI_MCR_DCONF_WIDTH                      2
+#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK                   0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT                  30
+#define SPI_MCR_CONT_SCKE_WIDTH                  1
+#define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CONT_SCKE_SHIFT))&SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK                        0x80000000u
+#define SPI_MCR_MSTR_SHIFT                       31
+#define SPI_MCR_MSTR_WIDTH                       1
+#define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MSTR_SHIFT))&SPI_MCR_MSTR_MASK)
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK                    0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT                   16
+#define SPI_TCR_SPI_TCNT_WIDTH                   16
+#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK                         0xFu
+#define SPI_CTAR_BR_SHIFT                        0
+#define SPI_CTAR_BR_WIDTH                        4
+#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK                         0xF0u
+#define SPI_CTAR_DT_SHIFT                        4
+#define SPI_CTAR_DT_WIDTH                        4
+#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK                        0xF00u
+#define SPI_CTAR_ASC_SHIFT                       8
+#define SPI_CTAR_ASC_WIDTH                       4
+#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK                      0xF000u
+#define SPI_CTAR_CSSCK_SHIFT                     12
+#define SPI_CTAR_CSSCK_WIDTH                     4
+#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK                        0x30000u
+#define SPI_CTAR_PBR_SHIFT                       16
+#define SPI_CTAR_PBR_WIDTH                       2
+#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK                        0xC0000u
+#define SPI_CTAR_PDT_SHIFT                       18
+#define SPI_CTAR_PDT_WIDTH                       2
+#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK                       0x300000u
+#define SPI_CTAR_PASC_SHIFT                      20
+#define SPI_CTAR_PASC_WIDTH                      2
+#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK                     0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT                    22
+#define SPI_CTAR_PCSSCK_WIDTH                    2
+#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK                      0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT                     24
+#define SPI_CTAR_LSBFE_WIDTH                     1
+#define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_LSBFE_SHIFT))&SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK                       0x2000000u
+#define SPI_CTAR_CPHA_SHIFT                      25
+#define SPI_CTAR_CPHA_WIDTH                      1
+#define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPHA_SHIFT))&SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK                       0x4000000u
+#define SPI_CTAR_CPOL_SHIFT                      26
+#define SPI_CTAR_CPOL_WIDTH                      1
+#define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPOL_SHIFT))&SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK                       0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT                      27
+#define SPI_CTAR_FMSZ_WIDTH                      4
+#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK                        0x80000000u
+#define SPI_CTAR_DBR_SHIFT                       31
+#define SPI_CTAR_DBR_WIDTH                       1
+#define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DBR_SHIFT))&SPI_CTAR_DBR_MASK)
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK                 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT                25
+#define SPI_CTAR_SLAVE_CPHA_WIDTH                1
+#define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPHA_SHIFT))&SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK                 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT                26
+#define SPI_CTAR_SLAVE_CPOL_WIDTH                1
+#define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPOL_SHIFT))&SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK                 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT                27
+#define SPI_CTAR_SLAVE_FMSZ_WIDTH                5
+#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK                    0xFu
+#define SPI_SR_POPNXTPTR_SHIFT                   0
+#define SPI_SR_POPNXTPTR_WIDTH                   4
+#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK                        0xF0u
+#define SPI_SR_RXCTR_SHIFT                       4
+#define SPI_SR_RXCTR_WIDTH                       4
+#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK                     0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT                    8
+#define SPI_SR_TXNXTPTR_WIDTH                    4
+#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK                        0xF000u
+#define SPI_SR_TXCTR_SHIFT                       12
+#define SPI_SR_TXCTR_WIDTH                       4
+#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK                         0x20000u
+#define SPI_SR_RFDF_SHIFT                        17
+#define SPI_SR_RFDF_WIDTH                        1
+#define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFDF_SHIFT))&SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK                         0x80000u
+#define SPI_SR_RFOF_SHIFT                        19
+#define SPI_SR_RFOF_WIDTH                        1
+#define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFOF_SHIFT))&SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK                         0x2000000u
+#define SPI_SR_TFFF_SHIFT                        25
+#define SPI_SR_TFFF_WIDTH                        1
+#define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK                         0x8000000u
+#define SPI_SR_TFUF_SHIFT                        27
+#define SPI_SR_TFUF_WIDTH                        1
+#define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFUF_SHIFT))&SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK                         0x10000000u
+#define SPI_SR_EOQF_SHIFT                        28
+#define SPI_SR_EOQF_WIDTH                        1
+#define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_EOQF_SHIFT))&SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK                        0x40000000u
+#define SPI_SR_TXRXS_SHIFT                       30
+#define SPI_SR_TXRXS_WIDTH                       1
+#define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXRXS_SHIFT))&SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK                          0x80000000u
+#define SPI_SR_TCF_SHIFT                         31
+#define SPI_SR_TCF_WIDTH                         1
+#define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x))<<SPI_SR_TCF_SHIFT))&SPI_SR_TCF_MASK)
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK                  0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT                 16
+#define SPI_RSER_RFDF_DIRS_WIDTH                 1
+#define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_DIRS_SHIFT))&SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK                    0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT                   17
+#define SPI_RSER_RFDF_RE_WIDTH                   1
+#define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_RE_SHIFT))&SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK                    0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT                   19
+#define SPI_RSER_RFOF_RE_WIDTH                   1
+#define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFOF_RE_SHIFT))&SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK                  0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT                 24
+#define SPI_RSER_TFFF_DIRS_WIDTH                 1
+#define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_DIRS_SHIFT))&SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK                    0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT                   25
+#define SPI_RSER_TFFF_RE_WIDTH                   1
+#define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK                    0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT                   27
+#define SPI_RSER_TFUF_RE_WIDTH                   1
+#define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFUF_RE_SHIFT))&SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK                    0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT                   28
+#define SPI_RSER_EOQF_RE_WIDTH                   1
+#define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_EOQF_RE_SHIFT))&SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK                     0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT                    31
+#define SPI_RSER_TCF_RE_WIDTH                    1
+#define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TCF_RE_SHIFT))&SPI_RSER_TCF_RE_MASK)
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK                    0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT                   0
+#define SPI_PUSHR_TXDATA_WIDTH                   16
+#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK                       0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT                      16
+#define SPI_PUSHR_PCS_WIDTH                      6
+#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK                     0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT                    26
+#define SPI_PUSHR_CTCNT_WIDTH                    1
+#define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTCNT_SHIFT))&SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK                       0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT                      27
+#define SPI_PUSHR_EOQ_WIDTH                      1
+#define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_EOQ_SHIFT))&SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK                      0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT                     28
+#define SPI_PUSHR_CTAS_WIDTH                     3
+#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK                      0x80000000u
+#define SPI_PUSHR_CONT_SHIFT                     31
+#define SPI_PUSHR_CONT_WIDTH                     1
+#define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CONT_SHIFT))&SPI_PUSHR_CONT_MASK)
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK              0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             0
+#define SPI_PUSHR_SLAVE_TXDATA_WIDTH             32
+#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK                     0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT                    0
+#define SPI_POPR_RXDATA_WIDTH                    32
+#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT                   0
+#define SPI_TXFR0_TXDATA_WIDTH                   16
+#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR0_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT                   0
+#define SPI_TXFR1_TXDATA_WIDTH                   16
+#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR1_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT                   0
+#define SPI_TXFR2_TXDATA_WIDTH                   16
+#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR2_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT                   0
+#define SPI_TXFR3_TXDATA_WIDTH                   16
+#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR3_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT                   0
+#define SPI_RXFR0_RXDATA_WIDTH                   32
+#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT                   0
+#define SPI_RXFR1_RXDATA_WIDTH                   32
+#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT                   0
+#define SPI_RXFR2_RXDATA_WIDTH                   32
+#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT                   0
+#define SPI_RXFR3_RXDATA_WIDTH                   32
+#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR                            (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR                            (SPI1)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x400AC000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+#define SPI2_BASE_PTR                            (SPI2)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_MCR                                 SPI_MCR_REG(SPI0)
+#define SPI0_TCR                                 SPI_TCR_REG(SPI0)
+#define SPI0_CTAR0                               SPI_CTAR_REG(SPI0,0)
+#define SPI0_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI0,0)
+#define SPI0_CTAR1                               SPI_CTAR_REG(SPI0,1)
+#define SPI0_SR                                  SPI_SR_REG(SPI0)
+#define SPI0_RSER                                SPI_RSER_REG(SPI0)
+#define SPI0_PUSHR                               SPI_PUSHR_REG(SPI0)
+#define SPI0_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI0)
+#define SPI0_POPR                                SPI_POPR_REG(SPI0)
+#define SPI0_TXFR0                               SPI_TXFR0_REG(SPI0)
+#define SPI0_TXFR1                               SPI_TXFR1_REG(SPI0)
+#define SPI0_TXFR2                               SPI_TXFR2_REG(SPI0)
+#define SPI0_TXFR3                               SPI_TXFR3_REG(SPI0)
+#define SPI0_RXFR0                               SPI_RXFR0_REG(SPI0)
+#define SPI0_RXFR1                               SPI_RXFR1_REG(SPI0)
+#define SPI0_RXFR2                               SPI_RXFR2_REG(SPI0)
+#define SPI0_RXFR3                               SPI_RXFR3_REG(SPI0)
+/* SPI1 */
+#define SPI1_MCR                                 SPI_MCR_REG(SPI1)
+#define SPI1_TCR                                 SPI_TCR_REG(SPI1)
+#define SPI1_CTAR0                               SPI_CTAR_REG(SPI1,0)
+#define SPI1_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI1,0)
+#define SPI1_CTAR1                               SPI_CTAR_REG(SPI1,1)
+#define SPI1_SR                                  SPI_SR_REG(SPI1)
+#define SPI1_RSER                                SPI_RSER_REG(SPI1)
+#define SPI1_PUSHR                               SPI_PUSHR_REG(SPI1)
+#define SPI1_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI1)
+#define SPI1_POPR                                SPI_POPR_REG(SPI1)
+#define SPI1_TXFR0                               SPI_TXFR0_REG(SPI1)
+#define SPI1_TXFR1                               SPI_TXFR1_REG(SPI1)
+#define SPI1_TXFR2                               SPI_TXFR2_REG(SPI1)
+#define SPI1_TXFR3                               SPI_TXFR3_REG(SPI1)
+#define SPI1_RXFR0                               SPI_RXFR0_REG(SPI1)
+#define SPI1_RXFR1                               SPI_RXFR1_REG(SPI1)
+#define SPI1_RXFR2                               SPI_RXFR2_REG(SPI1)
+#define SPI1_RXFR3                               SPI_RXFR3_REG(SPI1)
+/* SPI2 */
+#define SPI2_MCR                                 SPI_MCR_REG(SPI2)
+#define SPI2_TCR                                 SPI_TCR_REG(SPI2)
+#define SPI2_CTAR0                               SPI_CTAR_REG(SPI2,0)
+#define SPI2_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI2,0)
+#define SPI2_CTAR1                               SPI_CTAR_REG(SPI2,1)
+#define SPI2_SR                                  SPI_SR_REG(SPI2)
+#define SPI2_RSER                                SPI_RSER_REG(SPI2)
+#define SPI2_PUSHR                               SPI_PUSHR_REG(SPI2)
+#define SPI2_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI2)
+#define SPI2_POPR                                SPI_POPR_REG(SPI2)
+#define SPI2_TXFR0                               SPI_TXFR0_REG(SPI2)
+#define SPI2_TXFR1                               SPI_TXFR1_REG(SPI2)
+#define SPI2_TXFR2                               SPI_TXFR2_REG(SPI2)
+#define SPI2_TXFR3                               SPI_TXFR3_REG(SPI2)
+#define SPI2_RXFR0                               SPI_RXFR0_REG(SPI2)
+#define SPI2_RXFR1                               SPI_RXFR1_REG(SPI2)
+#define SPI2_RXFR2                               SPI_RXFR2_REG(SPI2)
+#define SPI2_RXFR3                               SPI_RXFR3_REG(SPI2)
+
+/* SPI - Register array accessors */
+#define SPI0_CTAR(index2)                        SPI_CTAR_REG(SPI0,index2)
+#define SPI1_CTAR(index2)                        SPI_CTAR_REG(SPI1,index2)
+#define SPI2_CTAR(index2)                        SPI_CTAR_REG(SPI2,index2)
+#define SPI0_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI0,index2)
+#define SPI1_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI1,index2)
+#define SPI2_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI2,index2)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
+  __I  uint8_t ED;                                 /**< UART Extended Data Register, offset: 0xC */
+  __IO uint8_t MODEM;                              /**< UART Modem Register, offset: 0xD */
+  __IO uint8_t IR;                                 /**< UART Infrared Register, offset: 0xE */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t PFIFO;                              /**< UART FIFO Parameters, offset: 0x10 */
+  __IO uint8_t CFIFO;                              /**< UART FIFO Control Register, offset: 0x11 */
+  __IO uint8_t SFIFO;                              /**< UART FIFO Status Register, offset: 0x12 */
+  __IO uint8_t TWFIFO;                             /**< UART FIFO Transmit Watermark, offset: 0x13 */
+  __I  uint8_t TCFIFO;                             /**< UART FIFO Transmit Count, offset: 0x14 */
+  __IO uint8_t RWFIFO;                             /**< UART FIFO Receive Watermark, offset: 0x15 */
+  __I  uint8_t RCFIFO;                             /**< UART FIFO Receive Count, offset: 0x16 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
+  __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+  __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+  union {                                          /* offset: 0x1B */
+    __IO uint8_t WP7816T0;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+    __IO uint8_t WP7816T1;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+  };
+  __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
+  __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
+  __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
+  __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base)                       ((base)->BDH)
+#define UART_BDL_REG(base)                       ((base)->BDL)
+#define UART_C1_REG(base)                        ((base)->C1)
+#define UART_C2_REG(base)                        ((base)->C2)
+#define UART_S1_REG(base)                        ((base)->S1)
+#define UART_S2_REG(base)                        ((base)->S2)
+#define UART_C3_REG(base)                        ((base)->C3)
+#define UART_D_REG(base)                         ((base)->D)
+#define UART_MA1_REG(base)                       ((base)->MA1)
+#define UART_MA2_REG(base)                       ((base)->MA2)
+#define UART_C4_REG(base)                        ((base)->C4)
+#define UART_C5_REG(base)                        ((base)->C5)
+#define UART_ED_REG(base)                        ((base)->ED)
+#define UART_MODEM_REG(base)                     ((base)->MODEM)
+#define UART_IR_REG(base)                        ((base)->IR)
+#define UART_PFIFO_REG(base)                     ((base)->PFIFO)
+#define UART_CFIFO_REG(base)                     ((base)->CFIFO)
+#define UART_SFIFO_REG(base)                     ((base)->SFIFO)
+#define UART_TWFIFO_REG(base)                    ((base)->TWFIFO)
+#define UART_TCFIFO_REG(base)                    ((base)->TCFIFO)
+#define UART_RWFIFO_REG(base)                    ((base)->RWFIFO)
+#define UART_RCFIFO_REG(base)                    ((base)->RCFIFO)
+#define UART_C7816_REG(base)                     ((base)->C7816)
+#define UART_IE7816_REG(base)                    ((base)->IE7816)
+#define UART_IS7816_REG(base)                    ((base)->IS7816)
+#define UART_WP7816T0_REG(base)                  ((base)->WP7816T0)
+#define UART_WP7816T1_REG(base)                  ((base)->WP7816T1)
+#define UART_WN7816_REG(base)                    ((base)->WN7816)
+#define UART_WF7816_REG(base)                    ((base)->WF7816)
+#define UART_ET7816_REG(base)                    ((base)->ET7816)
+#define UART_TL7816_REG(base)                    ((base)->TL7816)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK                        0x1Fu
+#define UART_BDH_SBR_SHIFT                       0
+#define UART_BDH_SBR_WIDTH                       5
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK                       0x20u
+#define UART_BDH_SBNS_SHIFT                      5
+#define UART_BDH_SBNS_WIDTH                      1
+#define UART_BDH_SBNS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBNS_SHIFT))&UART_BDH_SBNS_MASK)
+#define UART_BDH_RXEDGIE_MASK                    0x40u
+#define UART_BDH_RXEDGIE_SHIFT                   6
+#define UART_BDH_RXEDGIE_WIDTH                   1
+#define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK                     0x80u
+#define UART_BDH_LBKDIE_SHIFT                    7
+#define UART_BDH_LBKDIE_WIDTH                    1
+#define UART_BDH_LBKDIE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_BDH_LBKDIE_SHIFT))&UART_BDH_LBKDIE_MASK)
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK                        0xFFu
+#define UART_BDL_SBR_SHIFT                       0
+#define UART_BDL_SBR_WIDTH                       8
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK                          0x1u
+#define UART_C1_PT_SHIFT                         0
+#define UART_C1_PT_WIDTH                         1
+#define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
+#define UART_C1_PE_MASK                          0x2u
+#define UART_C1_PE_SHIFT                         1
+#define UART_C1_PE_WIDTH                         1
+#define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK                         0x4u
+#define UART_C1_ILT_SHIFT                        2
+#define UART_C1_ILT_WIDTH                        1
+#define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK                        0x8u
+#define UART_C1_WAKE_SHIFT                       3
+#define UART_C1_WAKE_WIDTH                       1
+#define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK                           0x10u
+#define UART_C1_M_SHIFT                          4
+#define UART_C1_M_WIDTH                          1
+#define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK                        0x20u
+#define UART_C1_RSRC_SHIFT                       5
+#define UART_C1_RSRC_WIDTH                       1
+#define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK                    0x40u
+#define UART_C1_UARTSWAI_SHIFT                   6
+#define UART_C1_UARTSWAI_WIDTH                   1
+#define UART_C1_UARTSWAI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C1_UARTSWAI_SHIFT))&UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK                       0x80u
+#define UART_C1_LOOPS_SHIFT                      7
+#define UART_C1_LOOPS_WIDTH                      1
+#define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK                         0x1u
+#define UART_C2_SBK_SHIFT                        0
+#define UART_C2_SBK_WIDTH                        1
+#define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK                         0x2u
+#define UART_C2_RWU_SHIFT                        1
+#define UART_C2_RWU_WIDTH                        1
+#define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK                          0x4u
+#define UART_C2_RE_SHIFT                         2
+#define UART_C2_RE_WIDTH                         1
+#define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
+#define UART_C2_TE_MASK                          0x8u
+#define UART_C2_TE_SHIFT                         3
+#define UART_C2_TE_WIDTH                         1
+#define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK                        0x10u
+#define UART_C2_ILIE_SHIFT                       4
+#define UART_C2_ILIE_WIDTH                       1
+#define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK                         0x20u
+#define UART_C2_RIE_SHIFT                        5
+#define UART_C2_RIE_WIDTH                        1
+#define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK                        0x40u
+#define UART_C2_TCIE_SHIFT                       6
+#define UART_C2_TCIE_WIDTH                       1
+#define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK                         0x80u
+#define UART_C2_TIE_SHIFT                        7
+#define UART_C2_TIE_WIDTH                        1
+#define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK                          0x1u
+#define UART_S1_PF_SHIFT                         0
+#define UART_S1_PF_WIDTH                         1
+#define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
+#define UART_S1_FE_MASK                          0x2u
+#define UART_S1_FE_SHIFT                         1
+#define UART_S1_FE_WIDTH                         1
+#define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
+#define UART_S1_NF_MASK                          0x4u
+#define UART_S1_NF_SHIFT                         2
+#define UART_S1_NF_WIDTH                         1
+#define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
+#define UART_S1_OR_MASK                          0x8u
+#define UART_S1_OR_SHIFT                         3
+#define UART_S1_OR_WIDTH                         1
+#define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK                        0x10u
+#define UART_S1_IDLE_SHIFT                       4
+#define UART_S1_IDLE_WIDTH                       1
+#define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK                        0x20u
+#define UART_S1_RDRF_SHIFT                       5
+#define UART_S1_RDRF_WIDTH                       1
+#define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK                          0x40u
+#define UART_S1_TC_SHIFT                         6
+#define UART_S1_TC_WIDTH                         1
+#define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK                        0x80u
+#define UART_S1_TDRE_SHIFT                       7
+#define UART_S1_TDRE_WIDTH                       1
+#define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK                         0x1u
+#define UART_S2_RAF_SHIFT                        0
+#define UART_S2_RAF_WIDTH                        1
+#define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK                       0x2u
+#define UART_S2_LBKDE_SHIFT                      1
+#define UART_S2_LBKDE_WIDTH                      1
+#define UART_S2_LBKDE(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDE_SHIFT))&UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK                       0x4u
+#define UART_S2_BRK13_SHIFT                      2
+#define UART_S2_BRK13_WIDTH                      1
+#define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK                       0x8u
+#define UART_S2_RWUID_SHIFT                      3
+#define UART_S2_RWUID_WIDTH                      1
+#define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK                       0x10u
+#define UART_S2_RXINV_SHIFT                      4
+#define UART_S2_RXINV_WIDTH                      1
+#define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK                        0x20u
+#define UART_S2_MSBF_SHIFT                       5
+#define UART_S2_MSBF_WIDTH                       1
+#define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S2_MSBF_SHIFT))&UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK                     0x40u
+#define UART_S2_RXEDGIF_SHIFT                    6
+#define UART_S2_RXEDGIF_WIDTH                    1
+#define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK                      0x80u
+#define UART_S2_LBKDIF_SHIFT                     7
+#define UART_S2_LBKDIF_WIDTH                     1
+#define UART_S2_LBKDIF(x)                        (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDIF_SHIFT))&UART_S2_LBKDIF_MASK)
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK                        0x1u
+#define UART_C3_PEIE_SHIFT                       0
+#define UART_C3_PEIE_WIDTH                       1
+#define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK                        0x2u
+#define UART_C3_FEIE_SHIFT                       1
+#define UART_C3_FEIE_WIDTH                       1
+#define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK                        0x4u
+#define UART_C3_NEIE_SHIFT                       2
+#define UART_C3_NEIE_WIDTH                       1
+#define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK                        0x8u
+#define UART_C3_ORIE_SHIFT                       3
+#define UART_C3_ORIE_WIDTH                       1
+#define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK                       0x10u
+#define UART_C3_TXINV_SHIFT                      4
+#define UART_C3_TXINV_WIDTH                      1
+#define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK                       0x20u
+#define UART_C3_TXDIR_SHIFT                      5
+#define UART_C3_TXDIR_WIDTH                      1
+#define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK                          0x40u
+#define UART_C3_T8_SHIFT                         6
+#define UART_C3_T8_WIDTH                         1
+#define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
+#define UART_C3_R8_MASK                          0x80u
+#define UART_C3_R8_SHIFT                         7
+#define UART_C3_R8_WIDTH                         1
+#define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
+/* D Bit Fields */
+#define UART_D_RT_MASK                           0xFFu
+#define UART_D_RT_SHIFT                          0
+#define UART_D_RT_WIDTH                          8
+#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK                         0xFFu
+#define UART_MA1_MA_SHIFT                        0
+#define UART_MA1_MA_WIDTH                        8
+#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK                         0xFFu
+#define UART_MA2_MA_SHIFT                        0
+#define UART_MA2_MA_WIDTH                        8
+#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK                        0x1Fu
+#define UART_C4_BRFA_SHIFT                       0
+#define UART_C4_BRFA_WIDTH                       5
+#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK                         0x20u
+#define UART_C4_M10_SHIFT                        5
+#define UART_C4_M10_WIDTH                        1
+#define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C4_M10_SHIFT))&UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK                       0x40u
+#define UART_C4_MAEN2_SHIFT                      6
+#define UART_C4_MAEN2_WIDTH                      1
+#define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN2_SHIFT))&UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK                       0x80u
+#define UART_C4_MAEN1_SHIFT                      7
+#define UART_C4_MAEN1_WIDTH                      1
+#define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN1_SHIFT))&UART_C4_MAEN1_MASK)
+/* C5 Bit Fields */
+#define UART_C5_LBKDDMAS_MASK                    0x8u
+#define UART_C5_LBKDDMAS_SHIFT                   3
+#define UART_C5_LBKDDMAS_WIDTH                   1
+#define UART_C5_LBKDDMAS(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C5_LBKDDMAS_SHIFT))&UART_C5_LBKDDMAS_MASK)
+#define UART_C5_ILDMAS_MASK                      0x10u
+#define UART_C5_ILDMAS_SHIFT                     4
+#define UART_C5_ILDMAS_WIDTH                     1
+#define UART_C5_ILDMAS(x)                        (((uint8_t)(((uint8_t)(x))<<UART_C5_ILDMAS_SHIFT))&UART_C5_ILDMAS_MASK)
+#define UART_C5_RDMAS_MASK                       0x20u
+#define UART_C5_RDMAS_SHIFT                      5
+#define UART_C5_RDMAS_WIDTH                      1
+#define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_RDMAS_SHIFT))&UART_C5_RDMAS_MASK)
+#define UART_C5_TCDMAS_MASK                      0x40u
+#define UART_C5_TCDMAS_SHIFT                     6
+#define UART_C5_TCDMAS_WIDTH                     1
+#define UART_C5_TCDMAS(x)                        (((uint8_t)(((uint8_t)(x))<<UART_C5_TCDMAS_SHIFT))&UART_C5_TCDMAS_MASK)
+#define UART_C5_TDMAS_MASK                       0x80u
+#define UART_C5_TDMAS_SHIFT                      7
+#define UART_C5_TDMAS_WIDTH                      1
+#define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_TDMAS_SHIFT))&UART_C5_TDMAS_MASK)
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK                     0x40u
+#define UART_ED_PARITYE_SHIFT                    6
+#define UART_ED_PARITYE_WIDTH                    1
+#define UART_ED_PARITYE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_ED_PARITYE_SHIFT))&UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK                       0x80u
+#define UART_ED_NOISY_SHIFT                      7
+#define UART_ED_NOISY_WIDTH                      1
+#define UART_ED_NOISY(x)                         (((uint8_t)(((uint8_t)(x))<<UART_ED_NOISY_SHIFT))&UART_ED_NOISY_MASK)
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK                   0x1u
+#define UART_MODEM_TXCTSE_SHIFT                  0
+#define UART_MODEM_TXCTSE_WIDTH                  1
+#define UART_MODEM_TXCTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXCTSE_SHIFT))&UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK                   0x2u
+#define UART_MODEM_TXRTSE_SHIFT                  1
+#define UART_MODEM_TXRTSE_WIDTH                  1
+#define UART_MODEM_TXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSE_SHIFT))&UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK                 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT                2
+#define UART_MODEM_TXRTSPOL_WIDTH                1
+#define UART_MODEM_TXRTSPOL(x)                   (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSPOL_SHIFT))&UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK                   0x8u
+#define UART_MODEM_RXRTSE_SHIFT                  3
+#define UART_MODEM_RXRTSE_WIDTH                  1
+#define UART_MODEM_RXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_RXRTSE_SHIFT))&UART_MODEM_RXRTSE_MASK)
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK                         0x3u
+#define UART_IR_TNP_SHIFT                        0
+#define UART_IR_TNP_WIDTH                        2
+#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK                        0x4u
+#define UART_IR_IREN_SHIFT                       2
+#define UART_IR_IREN_WIDTH                       1
+#define UART_IR_IREN(x)                          (((uint8_t)(((uint8_t)(x))<<UART_IR_IREN_SHIFT))&UART_IR_IREN_MASK)
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK               0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT              0
+#define UART_PFIFO_RXFIFOSIZE_WIDTH              3
+#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK                     0x8u
+#define UART_PFIFO_RXFE_SHIFT                    3
+#define UART_PFIFO_RXFE_WIDTH                    1
+#define UART_PFIFO_RXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFE_SHIFT))&UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK               0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT              4
+#define UART_PFIFO_TXFIFOSIZE_WIDTH              3
+#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK                     0x80u
+#define UART_PFIFO_TXFE_SHIFT                    7
+#define UART_PFIFO_TXFE_WIDTH                    1
+#define UART_PFIFO_TXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFE_SHIFT))&UART_PFIFO_TXFE_MASK)
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK                    0x1u
+#define UART_CFIFO_RXUFE_SHIFT                   0
+#define UART_CFIFO_RXUFE_WIDTH                   1
+#define UART_CFIFO_RXUFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXUFE_SHIFT))&UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK                    0x2u
+#define UART_CFIFO_TXOFE_SHIFT                   1
+#define UART_CFIFO_TXOFE_WIDTH                   1
+#define UART_CFIFO_TXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXOFE_SHIFT))&UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXOFE_MASK                    0x4u
+#define UART_CFIFO_RXOFE_SHIFT                   2
+#define UART_CFIFO_RXOFE_WIDTH                   1
+#define UART_CFIFO_RXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXOFE_SHIFT))&UART_CFIFO_RXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK                  0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT                 6
+#define UART_CFIFO_RXFLUSH_WIDTH                 1
+#define UART_CFIFO_RXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXFLUSH_SHIFT))&UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK                  0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT                 7
+#define UART_CFIFO_TXFLUSH_WIDTH                 1
+#define UART_CFIFO_TXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXFLUSH_SHIFT))&UART_CFIFO_TXFLUSH_MASK)
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK                     0x1u
+#define UART_SFIFO_RXUF_SHIFT                    0
+#define UART_SFIFO_RXUF_WIDTH                    1
+#define UART_SFIFO_RXUF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXUF_SHIFT))&UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK                     0x2u
+#define UART_SFIFO_TXOF_SHIFT                    1
+#define UART_SFIFO_TXOF_WIDTH                    1
+#define UART_SFIFO_TXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXOF_SHIFT))&UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXOF_MASK                     0x4u
+#define UART_SFIFO_RXOF_SHIFT                    2
+#define UART_SFIFO_RXOF_WIDTH                    1
+#define UART_SFIFO_RXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXOF_SHIFT))&UART_SFIFO_RXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK                   0x40u
+#define UART_SFIFO_RXEMPT_SHIFT                  6
+#define UART_SFIFO_RXEMPT_WIDTH                  1
+#define UART_SFIFO_RXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXEMPT_SHIFT))&UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK                   0x80u
+#define UART_SFIFO_TXEMPT_SHIFT                  7
+#define UART_SFIFO_TXEMPT_WIDTH                  1
+#define UART_SFIFO_TXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXEMPT_SHIFT))&UART_SFIFO_TXEMPT_MASK)
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK                 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT                0
+#define UART_TWFIFO_TXWATER_WIDTH                8
+#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK                 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT                0
+#define UART_TCFIFO_TXCOUNT_WIDTH                8
+#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK                 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT                0
+#define UART_RWFIFO_RXWATER_WIDTH                8
+#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK                 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT                0
+#define UART_RCFIFO_RXCOUNT_WIDTH                8
+#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK                0x1u
+#define UART_C7816_ISO_7816E_SHIFT               0
+#define UART_C7816_ISO_7816E_WIDTH               1
+#define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x))<<UART_C7816_ISO_7816E_SHIFT))&UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK                    0x2u
+#define UART_C7816_TTYPE_SHIFT                   1
+#define UART_C7816_TTYPE_WIDTH                   1
+#define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_TTYPE_SHIFT))&UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK                     0x4u
+#define UART_C7816_INIT_SHIFT                    2
+#define UART_C7816_INIT_WIDTH                    1
+#define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_C7816_INIT_SHIFT))&UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK                    0x8u
+#define UART_C7816_ANACK_SHIFT                   3
+#define UART_C7816_ANACK_WIDTH                   1
+#define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ANACK_SHIFT))&UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK                    0x10u
+#define UART_C7816_ONACK_SHIFT                   4
+#define UART_C7816_ONACK_WIDTH                   1
+#define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ONACK_SHIFT))&UART_C7816_ONACK_MASK)
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK                    0x1u
+#define UART_IE7816_RXTE_SHIFT                   0
+#define UART_IE7816_RXTE_WIDTH                   1
+#define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_RXTE_SHIFT))&UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK                    0x2u
+#define UART_IE7816_TXTE_SHIFT                   1
+#define UART_IE7816_TXTE_WIDTH                   1
+#define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_TXTE_SHIFT))&UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK                    0x4u
+#define UART_IE7816_GTVE_SHIFT                   2
+#define UART_IE7816_GTVE_WIDTH                   1
+#define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_GTVE_SHIFT))&UART_IE7816_GTVE_MASK)
+#define UART_IE7816_INITDE_MASK                  0x10u
+#define UART_IE7816_INITDE_SHIFT                 4
+#define UART_IE7816_INITDE_WIDTH                 1
+#define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x))<<UART_IE7816_INITDE_SHIFT))&UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK                    0x20u
+#define UART_IE7816_BWTE_SHIFT                   5
+#define UART_IE7816_BWTE_WIDTH                   1
+#define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_BWTE_SHIFT))&UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK                    0x40u
+#define UART_IE7816_CWTE_SHIFT                   6
+#define UART_IE7816_CWTE_WIDTH                   1
+#define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_CWTE_SHIFT))&UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK                     0x80u
+#define UART_IE7816_WTE_SHIFT                    7
+#define UART_IE7816_WTE_WIDTH                    1
+#define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IE7816_WTE_SHIFT))&UART_IE7816_WTE_MASK)
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK                     0x1u
+#define UART_IS7816_RXT_SHIFT                    0
+#define UART_IS7816_RXT_WIDTH                    1
+#define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_RXT_SHIFT))&UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK                     0x2u
+#define UART_IS7816_TXT_SHIFT                    1
+#define UART_IS7816_TXT_WIDTH                    1
+#define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_TXT_SHIFT))&UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK                     0x4u
+#define UART_IS7816_GTV_SHIFT                    2
+#define UART_IS7816_GTV_WIDTH                    1
+#define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_GTV_SHIFT))&UART_IS7816_GTV_MASK)
+#define UART_IS7816_INITD_MASK                   0x10u
+#define UART_IS7816_INITD_SHIFT                  4
+#define UART_IS7816_INITD_WIDTH                  1
+#define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x))<<UART_IS7816_INITD_SHIFT))&UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK                     0x20u
+#define UART_IS7816_BWT_SHIFT                    5
+#define UART_IS7816_BWT_WIDTH                    1
+#define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_BWT_SHIFT))&UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK                     0x40u
+#define UART_IS7816_CWT_SHIFT                    6
+#define UART_IS7816_CWT_WIDTH                    1
+#define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_CWT_SHIFT))&UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK                      0x80u
+#define UART_IS7816_WT_SHIFT                     7
+#define UART_IS7816_WT_WIDTH                     1
+#define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x))<<UART_IS7816_WT_SHIFT))&UART_IS7816_WT_MASK)
+/* WP7816T0 Bit Fields */
+#define UART_WP7816T0_WI_MASK                    0xFFu
+#define UART_WP7816T0_WI_SHIFT                   0
+#define UART_WP7816T0_WI_WIDTH                   8
+#define UART_WP7816T0_WI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
+/* WP7816T1 Bit Fields */
+#define UART_WP7816T1_BWI_MASK                   0xFu
+#define UART_WP7816T1_BWI_SHIFT                  0
+#define UART_WP7816T1_BWI_WIDTH                  4
+#define UART_WP7816T1_BWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
+#define UART_WP7816T1_CWI_MASK                   0xF0u
+#define UART_WP7816T1_CWI_SHIFT                  4
+#define UART_WP7816T1_CWI_WIDTH                  4
+#define UART_WP7816T1_CWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK                     0xFFu
+#define UART_WN7816_GTN_SHIFT                    0
+#define UART_WN7816_GTN_WIDTH                    8
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK                    0xFFu
+#define UART_WF7816_GTFD_SHIFT                   0
+#define UART_WF7816_GTFD_WIDTH                   8
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK             0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT            0
+#define UART_ET7816_RXTHRESHOLD_WIDTH            4
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK             0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT            4
+#define UART_ET7816_TXTHRESHOLD_WIDTH            4
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK                    0xFFu
+#define UART_TL7816_TLEN_SHIFT                   0
+#define UART_TL7816_TLEN_WIDTH                   8
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0                                    ((UART_Type *)UART0_BASE)
+#define UART0_BASE_PTR                           (UART0)
+/** Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1                                    ((UART_Type *)UART1_BASE)
+#define UART1_BASE_PTR                           (UART1)
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR                           (UART2)
+/** Peripheral UART3 base address */
+#define UART3_BASE                               (0x4006D000u)
+/** Peripheral UART3 base pointer */
+#define UART3                                    ((UART_Type *)UART3_BASE)
+#define UART3_BASE_PTR                           (UART3)
+/** Peripheral UART4 base address */
+#define UART4_BASE                               (0x400EA000u)
+/** Peripheral UART4 base pointer */
+#define UART4                                    ((UART_Type *)UART4_BASE)
+#define UART4_BASE_PTR                           (UART4)
+/** Peripheral UART5 base address */
+#define UART5_BASE                               (0x400EB000u)
+/** Peripheral UART5 base pointer */
+#define UART5                                    ((UART_Type *)UART5_BASE)
+#define UART5_BASE_PTR                           (UART5)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS                           { UART0, UART1, UART2, UART3, UART4, UART5 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS                          { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
+#define UART_ERR_IRQS                            { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
+#define UART_LON_IRQS                            { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART0 */
+#define UART0_BDH                                UART_BDH_REG(UART0)
+#define UART0_BDL                                UART_BDL_REG(UART0)
+#define UART0_C1                                 UART_C1_REG(UART0)
+#define UART0_C2                                 UART_C2_REG(UART0)
+#define UART0_S1                                 UART_S1_REG(UART0)
+#define UART0_S2                                 UART_S2_REG(UART0)
+#define UART0_C3                                 UART_C3_REG(UART0)
+#define UART0_D                                  UART_D_REG(UART0)
+#define UART0_MA1                                UART_MA1_REG(UART0)
+#define UART0_MA2                                UART_MA2_REG(UART0)
+#define UART0_C4                                 UART_C4_REG(UART0)
+#define UART0_C5                                 UART_C5_REG(UART0)
+#define UART0_ED                                 UART_ED_REG(UART0)
+#define UART0_MODEM                              UART_MODEM_REG(UART0)
+#define UART0_IR                                 UART_IR_REG(UART0)
+#define UART0_PFIFO                              UART_PFIFO_REG(UART0)
+#define UART0_CFIFO                              UART_CFIFO_REG(UART0)
+#define UART0_SFIFO                              UART_SFIFO_REG(UART0)
+#define UART0_TWFIFO                             UART_TWFIFO_REG(UART0)
+#define UART0_TCFIFO                             UART_TCFIFO_REG(UART0)
+#define UART0_RWFIFO                             UART_RWFIFO_REG(UART0)
+#define UART0_RCFIFO                             UART_RCFIFO_REG(UART0)
+#define UART0_C7816                              UART_C7816_REG(UART0)
+#define UART0_IE7816                             UART_IE7816_REG(UART0)
+#define UART0_IS7816                             UART_IS7816_REG(UART0)
+#define UART0_WP7816T0                           UART_WP7816T0_REG(UART0)
+#define UART0_WP7816T1                           UART_WP7816T1_REG(UART0)
+#define UART0_WN7816                             UART_WN7816_REG(UART0)
+#define UART0_WF7816                             UART_WF7816_REG(UART0)
+#define UART0_ET7816                             UART_ET7816_REG(UART0)
+#define UART0_TL7816                             UART_TL7816_REG(UART0)
+/* UART1 */
+#define UART1_BDH                                UART_BDH_REG(UART1)
+#define UART1_BDL                                UART_BDL_REG(UART1)
+#define UART1_C1                                 UART_C1_REG(UART1)
+#define UART1_C2                                 UART_C2_REG(UART1)
+#define UART1_S1                                 UART_S1_REG(UART1)
+#define UART1_S2                                 UART_S2_REG(UART1)
+#define UART1_C3                                 UART_C3_REG(UART1)
+#define UART1_D                                  UART_D_REG(UART1)
+#define UART1_MA1                                UART_MA1_REG(UART1)
+#define UART1_MA2                                UART_MA2_REG(UART1)
+#define UART1_C4                                 UART_C4_REG(UART1)
+#define UART1_C5                                 UART_C5_REG(UART1)
+#define UART1_ED                                 UART_ED_REG(UART1)
+#define UART1_MODEM                              UART_MODEM_REG(UART1)
+#define UART1_IR                                 UART_IR_REG(UART1)
+#define UART1_PFIFO                              UART_PFIFO_REG(UART1)
+#define UART1_CFIFO                              UART_CFIFO_REG(UART1)
+#define UART1_SFIFO                              UART_SFIFO_REG(UART1)
+#define UART1_TWFIFO                             UART_TWFIFO_REG(UART1)
+#define UART1_TCFIFO                             UART_TCFIFO_REG(UART1)
+#define UART1_RWFIFO                             UART_RWFIFO_REG(UART1)
+#define UART1_RCFIFO                             UART_RCFIFO_REG(UART1)
+/* UART2 */
+#define UART2_BDH                                UART_BDH_REG(UART2)
+#define UART2_BDL                                UART_BDL_REG(UART2)
+#define UART2_C1                                 UART_C1_REG(UART2)
+#define UART2_C2                                 UART_C2_REG(UART2)
+#define UART2_S1                                 UART_S1_REG(UART2)
+#define UART2_S2                                 UART_S2_REG(UART2)
+#define UART2_C3                                 UART_C3_REG(UART2)
+#define UART2_D                                  UART_D_REG(UART2)
+#define UART2_MA1                                UART_MA1_REG(UART2)
+#define UART2_MA2                                UART_MA2_REG(UART2)
+#define UART2_C4                                 UART_C4_REG(UART2)
+#define UART2_C5                                 UART_C5_REG(UART2)
+#define UART2_ED                                 UART_ED_REG(UART2)
+#define UART2_MODEM                              UART_MODEM_REG(UART2)
+#define UART2_IR                                 UART_IR_REG(UART2)
+#define UART2_PFIFO                              UART_PFIFO_REG(UART2)
+#define UART2_CFIFO                              UART_CFIFO_REG(UART2)
+#define UART2_SFIFO                              UART_SFIFO_REG(UART2)
+#define UART2_TWFIFO                             UART_TWFIFO_REG(UART2)
+#define UART2_TCFIFO                             UART_TCFIFO_REG(UART2)
+#define UART2_RWFIFO                             UART_RWFIFO_REG(UART2)
+#define UART2_RCFIFO                             UART_RCFIFO_REG(UART2)
+/* UART3 */
+#define UART3_BDH                                UART_BDH_REG(UART3)
+#define UART3_BDL                                UART_BDL_REG(UART3)
+#define UART3_C1                                 UART_C1_REG(UART3)
+#define UART3_C2                                 UART_C2_REG(UART3)
+#define UART3_S1                                 UART_S1_REG(UART3)
+#define UART3_S2                                 UART_S2_REG(UART3)
+#define UART3_C3                                 UART_C3_REG(UART3)
+#define UART3_D                                  UART_D_REG(UART3)
+#define UART3_MA1                                UART_MA1_REG(UART3)
+#define UART3_MA2                                UART_MA2_REG(UART3)
+#define UART3_C4                                 UART_C4_REG(UART3)
+#define UART3_C5                                 UART_C5_REG(UART3)
+#define UART3_ED                                 UART_ED_REG(UART3)
+#define UART3_MODEM                              UART_MODEM_REG(UART3)
+#define UART3_IR                                 UART_IR_REG(UART3)
+#define UART3_PFIFO                              UART_PFIFO_REG(UART3)
+#define UART3_CFIFO                              UART_CFIFO_REG(UART3)
+#define UART3_SFIFO                              UART_SFIFO_REG(UART3)
+#define UART3_TWFIFO                             UART_TWFIFO_REG(UART3)
+#define UART3_TCFIFO                             UART_TCFIFO_REG(UART3)
+#define UART3_RWFIFO                             UART_RWFIFO_REG(UART3)
+#define UART3_RCFIFO                             UART_RCFIFO_REG(UART3)
+/* UART4 */
+#define UART4_BDH                                UART_BDH_REG(UART4)
+#define UART4_BDL                                UART_BDL_REG(UART4)
+#define UART4_C1                                 UART_C1_REG(UART4)
+#define UART4_C2                                 UART_C2_REG(UART4)
+#define UART4_S1                                 UART_S1_REG(UART4)
+#define UART4_S2                                 UART_S2_REG(UART4)
+#define UART4_C3                                 UART_C3_REG(UART4)
+#define UART4_D                                  UART_D_REG(UART4)
+#define UART4_MA1                                UART_MA1_REG(UART4)
+#define UART4_MA2                                UART_MA2_REG(UART4)
+#define UART4_C4                                 UART_C4_REG(UART4)
+#define UART4_C5                                 UART_C5_REG(UART4)
+#define UART4_ED                                 UART_ED_REG(UART4)
+#define UART4_MODEM                              UART_MODEM_REG(UART4)
+#define UART4_IR                                 UART_IR_REG(UART4)
+#define UART4_PFIFO                              UART_PFIFO_REG(UART4)
+#define UART4_CFIFO                              UART_CFIFO_REG(UART4)
+#define UART4_SFIFO                              UART_SFIFO_REG(UART4)
+#define UART4_TWFIFO                             UART_TWFIFO_REG(UART4)
+#define UART4_TCFIFO                             UART_TCFIFO_REG(UART4)
+#define UART4_RWFIFO                             UART_RWFIFO_REG(UART4)
+#define UART4_RCFIFO                             UART_RCFIFO_REG(UART4)
+/* UART5 */
+#define UART5_BDH                                UART_BDH_REG(UART5)
+#define UART5_BDL                                UART_BDL_REG(UART5)
+#define UART5_C1                                 UART_C1_REG(UART5)
+#define UART5_C2                                 UART_C2_REG(UART5)
+#define UART5_S1                                 UART_S1_REG(UART5)
+#define UART5_S2                                 UART_S2_REG(UART5)
+#define UART5_C3                                 UART_C3_REG(UART5)
+#define UART5_D                                  UART_D_REG(UART5)
+#define UART5_MA1                                UART_MA1_REG(UART5)
+#define UART5_MA2                                UART_MA2_REG(UART5)
+#define UART5_C4                                 UART_C4_REG(UART5)
+#define UART5_C5                                 UART_C5_REG(UART5)
+#define UART5_ED                                 UART_ED_REG(UART5)
+#define UART5_MODEM                              UART_MODEM_REG(UART5)
+#define UART5_IR                                 UART_IR_REG(UART5)
+#define UART5_PFIFO                              UART_PFIFO_REG(UART5)
+#define UART5_CFIFO                              UART_CFIFO_REG(UART5)
+#define UART5_SFIFO                              UART_SFIFO_REG(UART5)
+#define UART5_TWFIFO                             UART_TWFIFO_REG(UART5)
+#define UART5_TCFIFO                             UART_TCFIFO_REG(UART5)
+#define UART5_RWFIFO                             UART_RWFIFO_REG(UART5)
+#define UART5_RCFIFO                             UART_RCFIFO_REG(UART5)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[3];
+  __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t OTGICR;                             /**< OTG Interrupt Control register, offset: 0x14 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_7[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_11[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_16[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t SOFTHLD;                            /**< SOF Threshold register, offset: 0xAC */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_20[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_21[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_22[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_25[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
+       uint8_t RESERVED_26[43];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_27[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48M oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_28[23];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base)                      ((base)->PERID)
+#define USB_IDCOMP_REG(base)                     ((base)->IDCOMP)
+#define USB_REV_REG(base)                        ((base)->REV)
+#define USB_ADDINFO_REG(base)                    ((base)->ADDINFO)
+#define USB_OTGISTAT_REG(base)                   ((base)->OTGISTAT)
+#define USB_OTGICR_REG(base)                     ((base)->OTGICR)
+#define USB_OTGSTAT_REG(base)                    ((base)->OTGSTAT)
+#define USB_OTGCTL_REG(base)                     ((base)->OTGCTL)
+#define USB_ISTAT_REG(base)                      ((base)->ISTAT)
+#define USB_INTEN_REG(base)                      ((base)->INTEN)
+#define USB_ERRSTAT_REG(base)                    ((base)->ERRSTAT)
+#define USB_ERREN_REG(base)                      ((base)->ERREN)
+#define USB_STAT_REG(base)                       ((base)->STAT)
+#define USB_CTL_REG(base)                        ((base)->CTL)
+#define USB_ADDR_REG(base)                       ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base)                   ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base)                    ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base)                    ((base)->FRMNUMH)
+#define USB_TOKEN_REG(base)                      ((base)->TOKEN)
+#define USB_SOFTHLD_REG(base)                    ((base)->SOFTHLD)
+#define USB_BDTPAGE2_REG(base)                   ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base)                   ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index)                ((base)->ENDPOINT[index].ENDPT)
+#define USB_ENDPT_COUNT                          16
+#define USB_USBCTRL_REG(base)                    ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base)                    ((base)->OBSERVE)
+#define USB_CONTROL_REG(base)                    ((base)->CONTROL)
+#define USB_USBTRC0_REG(base)                    ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base)               ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base)           ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base)         ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base)     ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK                        0x3Fu
+#define USB_PERID_ID_SHIFT                       0
+#define USB_PERID_ID_WIDTH                       6
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK                      0x3Fu
+#define USB_IDCOMP_NID_SHIFT                     0
+#define USB_IDCOMP_NID_WIDTH                     6
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK                         0xFFu
+#define USB_REV_REV_SHIFT                        0
+#define USB_REV_REV_WIDTH                        8
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK                  0x1u
+#define USB_ADDINFO_IEHOST_SHIFT                 0
+#define USB_ADDINFO_IEHOST_WIDTH                 1
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
+#define USB_ADDINFO_IRQNUM_MASK                  0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT                 3
+#define USB_ADDINFO_IRQNUM_WIDTH                 5
+#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK               0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT              0
+#define USB_OTGISTAT_AVBUSCHG_WIDTH              1
+#define USB_OTGISTAT_AVBUSCHG(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_AVBUSCHG_SHIFT))&USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK             0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT            2
+#define USB_OTGISTAT_B_SESS_CHG_WIDTH            1
+#define USB_OTGISTAT_B_SESS_CHG(x)               (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_B_SESS_CHG_SHIFT))&USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK             0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT            3
+#define USB_OTGISTAT_SESSVLDCHG_WIDTH            1
+#define USB_OTGISTAT_SESSVLDCHG(x)               (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_SESSVLDCHG_SHIFT))&USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK         0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        5
+#define USB_OTGISTAT_LINE_STATE_CHG_WIDTH        1
+#define USB_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK                0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT               6
+#define USB_OTGISTAT_ONEMSEC_WIDTH               1
+#define USB_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK                  0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT                 7
+#define USB_OTGISTAT_IDCHG_WIDTH                 1
+#define USB_OTGISTAT_IDCHG(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_IDCHG_SHIFT))&USB_OTGISTAT_IDCHG_MASK)
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK                  0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT                 0
+#define USB_OTGICR_AVBUSEN_WIDTH                 1
+#define USB_OTGICR_AVBUSEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_AVBUSEN_SHIFT))&USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK                  0x4u
+#define USB_OTGICR_BSESSEN_SHIFT                 2
+#define USB_OTGICR_BSESSEN_WIDTH                 1
+#define USB_OTGICR_BSESSEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_BSESSEN_SHIFT))&USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK                0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT               3
+#define USB_OTGICR_SESSVLDEN_WIDTH               1
+#define USB_OTGICR_SESSVLDEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_SESSVLDEN_SHIFT))&USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK              0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT             5
+#define USB_OTGICR_LINESTATEEN_WIDTH             1
+#define USB_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK                0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT               6
+#define USB_OTGICR_ONEMSECEN_WIDTH               1
+#define USB_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK                     0x80u
+#define USB_OTGICR_IDEN_SHIFT                    7
+#define USB_OTGICR_IDEN_WIDTH                    1
+#define USB_OTGICR_IDEN(x)                       (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_IDEN_SHIFT))&USB_OTGICR_IDEN_MASK)
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK                0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT               0
+#define USB_OTGSTAT_AVBUSVLD_WIDTH               1
+#define USB_OTGSTAT_AVBUSVLD(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_AVBUSVLD_SHIFT))&USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK                0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT               2
+#define USB_OTGSTAT_BSESSEND_WIDTH               1
+#define USB_OTGSTAT_BSESSEND(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_BSESSEND_SHIFT))&USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK                0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT               3
+#define USB_OTGSTAT_SESS_VLD_WIDTH               1
+#define USB_OTGSTAT_SESS_VLD(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_SESS_VLD_SHIFT))&USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK         0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        5
+#define USB_OTGSTAT_LINESTATESTABLE_WIDTH        1
+#define USB_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK               0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT              6
+#define USB_OTGSTAT_ONEMSECEN_WIDTH              1
+#define USB_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK                      0x80u
+#define USB_OTGSTAT_ID_SHIFT                     7
+#define USB_OTGSTAT_ID_WIDTH                     1
+#define USB_OTGSTAT_ID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ID_SHIFT))&USB_OTGSTAT_ID_MASK)
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK                    0x4u
+#define USB_OTGCTL_OTGEN_SHIFT                   2
+#define USB_OTGCTL_OTGEN_WIDTH                   1
+#define USB_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK                    0x10u
+#define USB_OTGCTL_DMLOW_SHIFT                   4
+#define USB_OTGCTL_DMLOW_WIDTH                   1
+#define USB_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK                    0x20u
+#define USB_OTGCTL_DPLOW_SHIFT                   5
+#define USB_OTGCTL_DPLOW_WIDTH                   1
+#define USB_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK                   0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT                  7
+#define USB_OTGCTL_DPHIGH_WIDTH                  1
+#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK                    0x1u
+#define USB_ISTAT_USBRST_SHIFT                   0
+#define USB_ISTAT_USBRST_WIDTH                   1
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK                     0x2u
+#define USB_ISTAT_ERROR_SHIFT                    1
+#define USB_ISTAT_ERROR_WIDTH                    1
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK                    0x4u
+#define USB_ISTAT_SOFTOK_SHIFT                   2
+#define USB_ISTAT_SOFTOK_WIDTH                   1
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK                    0x8u
+#define USB_ISTAT_TOKDNE_SHIFT                   3
+#define USB_ISTAT_TOKDNE_WIDTH                   1
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK                     0x10u
+#define USB_ISTAT_SLEEP_SHIFT                    4
+#define USB_ISTAT_SLEEP_WIDTH                    1
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK                    0x20u
+#define USB_ISTAT_RESUME_SHIFT                   5
+#define USB_ISTAT_RESUME_WIDTH                   1
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK                    0x40u
+#define USB_ISTAT_ATTACH_SHIFT                   6
+#define USB_ISTAT_ATTACH_WIDTH                   1
+#define USB_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK                     0x80u
+#define USB_ISTAT_STALL_SHIFT                    7
+#define USB_ISTAT_STALL_WIDTH                    1
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK                  0x1u
+#define USB_INTEN_USBRSTEN_SHIFT                 0
+#define USB_INTEN_USBRSTEN_WIDTH                 1
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK                   0x2u
+#define USB_INTEN_ERROREN_SHIFT                  1
+#define USB_INTEN_ERROREN_WIDTH                  1
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK                  0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT                 2
+#define USB_INTEN_SOFTOKEN_WIDTH                 1
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK                  0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT                 3
+#define USB_INTEN_TOKDNEEN_WIDTH                 1
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK                   0x10u
+#define USB_INTEN_SLEEPEN_SHIFT                  4
+#define USB_INTEN_SLEEPEN_WIDTH                  1
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK                  0x20u
+#define USB_INTEN_RESUMEEN_SHIFT                 5
+#define USB_INTEN_RESUMEEN_WIDTH                 1
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK                  0x40u
+#define USB_INTEN_ATTACHEN_SHIFT                 6
+#define USB_INTEN_ATTACHEN_WIDTH                 1
+#define USB_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK                   0x80u
+#define USB_INTEN_STALLEN_SHIFT                  7
+#define USB_INTEN_STALLEN_WIDTH                  1
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK                  0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT                 0
+#define USB_ERRSTAT_PIDERR_WIDTH                 1
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK                 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT                1
+#define USB_ERRSTAT_CRC5EOF_WIDTH                1
+#define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK                   0x4u
+#define USB_ERRSTAT_CRC16_SHIFT                  2
+#define USB_ERRSTAT_CRC16_WIDTH                  1
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK                    0x8u
+#define USB_ERRSTAT_DFN8_SHIFT                   3
+#define USB_ERRSTAT_DFN8_WIDTH                   1
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK                  0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT                 4
+#define USB_ERRSTAT_BTOERR_WIDTH                 1
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK                  0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT                 5
+#define USB_ERRSTAT_DMAERR_WIDTH                 1
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK                  0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT                 7
+#define USB_ERRSTAT_BTSERR_WIDTH                 1
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK                  0x1u
+#define USB_ERREN_PIDERREN_SHIFT                 0
+#define USB_ERREN_PIDERREN_WIDTH                 1
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK                 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT                1
+#define USB_ERREN_CRC5EOFEN_WIDTH                1
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK                   0x4u
+#define USB_ERREN_CRC16EN_SHIFT                  2
+#define USB_ERREN_CRC16EN_WIDTH                  1
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK                    0x8u
+#define USB_ERREN_DFN8EN_SHIFT                   3
+#define USB_ERREN_DFN8EN_WIDTH                   1
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK                  0x10u
+#define USB_ERREN_BTOERREN_SHIFT                 4
+#define USB_ERREN_BTOERREN_WIDTH                 1
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK                  0x20u
+#define USB_ERREN_DMAERREN_SHIFT                 5
+#define USB_ERREN_DMAERREN_WIDTH                 1
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK                  0x80u
+#define USB_ERREN_BTSERREN_SHIFT                 7
+#define USB_ERREN_BTSERREN_WIDTH                 1
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK                        0x4u
+#define USB_STAT_ODD_SHIFT                       2
+#define USB_STAT_ODD_WIDTH                       1
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK                         0x8u
+#define USB_STAT_TX_SHIFT                        3
+#define USB_STAT_TX_WIDTH                        1
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK                       0xF0u
+#define USB_STAT_ENDP_SHIFT                      4
+#define USB_STAT_ENDP_WIDTH                      4
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK                  0x1u
+#define USB_CTL_USBENSOFEN_SHIFT                 0
+#define USB_CTL_USBENSOFEN_WIDTH                 1
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK                      0x2u
+#define USB_CTL_ODDRST_SHIFT                     1
+#define USB_CTL_ODDRST_WIDTH                     1
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK                      0x4u
+#define USB_CTL_RESUME_SHIFT                     2
+#define USB_CTL_RESUME_WIDTH                     1
+#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK                  0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT                 3
+#define USB_CTL_HOSTMODEEN_WIDTH                 1
+#define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK                       0x10u
+#define USB_CTL_RESET_SHIFT                      4
+#define USB_CTL_RESET_WIDTH                      1
+#define USB_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
+#define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH         1
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK                         0x40u
+#define USB_CTL_SE0_SHIFT                        6
+#define USB_CTL_SE0_WIDTH                        1
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK                      0x80u
+#define USB_CTL_JSTATE_SHIFT                     7
+#define USB_CTL_JSTATE_WIDTH                     1
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK                       0x7Fu
+#define USB_ADDR_ADDR_SHIFT                      0
+#define USB_ADDR_ADDR_WIDTH                      7
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK                       0x80u
+#define USB_ADDR_LSEN_SHIFT                      7
+#define USB_ADDR_LSEN_WIDTH                      1
+#define USB_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT                 1
+#define USB_BDTPAGE1_BDTBA_WIDTH                 7
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK                     0xFFu
+#define USB_FRMNUML_FRM_SHIFT                    0
+#define USB_FRMNUML_FRM_WIDTH                    8
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK                     0x7u
+#define USB_FRMNUMH_FRM_SHIFT                    0
+#define USB_FRMNUMH_FRM_WIDTH                    3
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK                0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT               0
+#define USB_TOKEN_TOKENENDPT_WIDTH               4
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT                 4
+#define USB_TOKEN_TOKENPID_WIDTH                 4
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK                     0xFFu
+#define USB_SOFTHLD_CNT_SHIFT                    0
+#define USB_SOFTHLD_CNT_WIDTH                    8
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT                 0
+#define USB_BDTPAGE2_BDTBA_WIDTH                 8
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT                 0
+#define USB_BDTPAGE3_BDTBA_WIDTH                 8
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK                    0x1u
+#define USB_ENDPT_EPHSHK_SHIFT                   0
+#define USB_ENDPT_EPHSHK_WIDTH                   1
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK                   0x2u
+#define USB_ENDPT_EPSTALL_SHIFT                  1
+#define USB_ENDPT_EPSTALL_WIDTH                  1
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK                    0x4u
+#define USB_ENDPT_EPTXEN_SHIFT                   2
+#define USB_ENDPT_EPTXEN_WIDTH                   1
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK                    0x8u
+#define USB_ENDPT_EPRXEN_SHIFT                   3
+#define USB_ENDPT_EPRXEN_WIDTH                   1
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK                  0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT                 4
+#define USB_ENDPT_EPCTLDIS_WIDTH                 1
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK                  0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT                 6
+#define USB_ENDPT_RETRYDIS_WIDTH                 1
+#define USB_ENDPT_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK                 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT                7
+#define USB_ENDPT_HOSTWOHUB_WIDTH                1
+#define USB_ENDPT_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK                     0x40u
+#define USB_USBCTRL_PDE_SHIFT                    6
+#define USB_USBCTRL_PDE_WIDTH                    1
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK                    0x80u
+#define USB_USBCTRL_SUSP_SHIFT                   7
+#define USB_USBCTRL_SUSP_WIDTH                   1
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK                    0x10u
+#define USB_OBSERVE_DMPD_SHIFT                   4
+#define USB_OBSERVE_DMPD_WIDTH                   1
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK                    0x40u
+#define USB_OBSERVE_DPPD_SHIFT                   6
+#define USB_OBSERVE_DPPD_WIDTH                   1
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK                    0x80u
+#define USB_OBSERVE_DPPU_SHIFT                   7
+#define USB_OBSERVE_DPPU_WIDTH                   1
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
+#define USB_CONTROL_DPPULLUPNONOTG_WIDTH         1
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
+#define USB_USBTRC0_USB_RESUME_INT_WIDTH         1
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK                0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT               1
+#define USB_USBTRC0_SYNC_DET_WIDTH               1
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   2
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH   1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))&USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK               0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT              5
+#define USB_USBTRC0_USBRESMEN_WIDTH              1
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK                0x80u
+#define USB_USBTRC0_USBRESET_SHIFT               7
+#define USB_USBTRC0_USBRESET_WIDTH               1
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK                0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT               0
+#define USB_USBFRMADJUST_ADJ_WIDTH               8
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))&USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK       0x1u
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      0
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH 1
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))&USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR                            (USB0)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID                               USB_PERID_REG(USB0)
+#define USB0_IDCOMP                              USB_IDCOMP_REG(USB0)
+#define USB0_REV                                 USB_REV_REG(USB0)
+#define USB0_ADDINFO                             USB_ADDINFO_REG(USB0)
+#define USB0_OTGISTAT                            USB_OTGISTAT_REG(USB0)
+#define USB0_OTGICR                              USB_OTGICR_REG(USB0)
+#define USB0_OTGSTAT                             USB_OTGSTAT_REG(USB0)
+#define USB0_OTGCTL                              USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT                               USB_ISTAT_REG(USB0)
+#define USB0_INTEN                               USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT                             USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN                               USB_ERREN_REG(USB0)
+#define USB0_STAT                                USB_STAT_REG(USB0)
+#define USB0_CTL                                 USB_CTL_REG(USB0)
+#define USB0_ADDR                                USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1                            USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML                             USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH                             USB_FRMNUMH_REG(USB0)
+#define USB0_TOKEN                               USB_TOKEN_REG(USB0)
+#define USB0_SOFTHLD                             USB_SOFTHLD_REG(USB0)
+#define USB0_BDTPAGE2                            USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3                            USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0                              USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1                              USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2                              USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3                              USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4                              USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5                              USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6                              USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7                              USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8                              USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9                              USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10                             USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11                             USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12                             USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13                             USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14                             USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15                             USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL                             USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE                             USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL                             USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0                             USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST                        USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL                    USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN                  USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS              USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index)                        USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
+  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
+  __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
+  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
+  union {                                          /* offset: 0x18 */
+    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
+    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
+  };
+} USBDCD_Type, *USBDCD_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register accessors */
+#define USBDCD_CONTROL_REG(base)                 ((base)->CONTROL)
+#define USBDCD_CLOCK_REG(base)                   ((base)->CLOCK)
+#define USBDCD_STATUS_REG(base)                  ((base)->STATUS)
+#define USBDCD_TIMER0_REG(base)                  ((base)->TIMER0)
+#define USBDCD_TIMER1_REG(base)                  ((base)->TIMER1)
+#define USBDCD_TIMER2_BC11_REG(base)             ((base)->TIMER2_BC11)
+#define USBDCD_TIMER2_BC12_REG(base)             ((base)->TIMER2_BC12)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK                 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT                0
+#define USBDCD_CONTROL_IACK_WIDTH                1
+#define USBDCD_CONTROL_IACK(x)                   (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IACK_SHIFT))&USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IF_MASK                   0x100u
+#define USBDCD_CONTROL_IF_SHIFT                  8
+#define USBDCD_CONTROL_IF_WIDTH                  1
+#define USBDCD_CONTROL_IF(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IF_SHIFT))&USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IE_MASK                   0x10000u
+#define USBDCD_CONTROL_IE_SHIFT                  16
+#define USBDCD_CONTROL_IE_WIDTH                  1
+#define USBDCD_CONTROL_IE(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IE_SHIFT))&USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_BC12_MASK                 0x20000u
+#define USBDCD_CONTROL_BC12_SHIFT                17
+#define USBDCD_CONTROL_BC12_WIDTH                1
+#define USBDCD_CONTROL_BC12(x)                   (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_BC12_SHIFT))&USBDCD_CONTROL_BC12_MASK)
+#define USBDCD_CONTROL_START_MASK                0x1000000u
+#define USBDCD_CONTROL_START_SHIFT               24
+#define USBDCD_CONTROL_START_WIDTH               1
+#define USBDCD_CONTROL_START(x)                  (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_START_SHIFT))&USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_SR_MASK                   0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT                  25
+#define USBDCD_CONTROL_SR_WIDTH                  1
+#define USBDCD_CONTROL_SR(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_SR_SHIFT))&USBDCD_CONTROL_SR_MASK)
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK             0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            0
+#define USBDCD_CLOCK_CLOCK_UNIT_WIDTH            1
+#define USBDCD_CLOCK_CLOCK_UNIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_UNIT_SHIFT))&USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK            0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           2
+#define USBDCD_CLOCK_CLOCK_SPEED_WIDTH           10
+#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK               0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT              16
+#define USBDCD_STATUS_SEQ_RES_WIDTH              2
+#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK              0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT             18
+#define USBDCD_STATUS_SEQ_STAT_WIDTH             2
+#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK                   0x100000u
+#define USBDCD_STATUS_ERR_SHIFT                  20
+#define USBDCD_STATUS_ERR_WIDTH                  1
+#define USBDCD_STATUS_ERR(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ERR_SHIFT))&USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_TO_MASK                    0x200000u
+#define USBDCD_STATUS_TO_SHIFT                   21
+#define USBDCD_STATUS_TO_WIDTH                   1
+#define USBDCD_STATUS_TO(x)                      (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_TO_SHIFT))&USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_ACTIVE_MASK                0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT               22
+#define USBDCD_STATUS_ACTIVE_WIDTH               1
+#define USBDCD_STATUS_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ACTIVE_SHIFT))&USBDCD_STATUS_ACTIVE_MASK)
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK              0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT             0
+#define USBDCD_TIMER0_TUNITCON_WIDTH             12
+#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK             0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            16
+#define USBDCD_TIMER0_TSEQ_INIT_WIDTH            10
+#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK            0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           0
+#define USBDCD_TIMER1_TVDPSRC_ON_WIDTH           10
+#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK             0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            16
+#define USBDCD_TIMER1_TDCD_DBNC_WIDTH            10
+#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2_BC11 Bit Fields */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK         0xFu
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        0
+#define USBDCD_TIMER2_BC11_CHECK_DM_WIDTH        4
+#define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      0x3FF0000u
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     16
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_WIDTH     10
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+/* TIMER2_BC12 Bit Fields */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       0x3FFu
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      0
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_WIDTH      10
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  0x3FF0000u
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_WIDTH 10
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE                              (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD                                   ((USBDCD_Type *)USBDCD_BASE)
+#define USBDCD_BASE_PTR                          (USBDCD)
+/** Array initializer of USBDCD peripheral base addresses */
+#define USBDCD_BASE_ADDRS                        { USBDCD_BASE }
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASE_PTRS                         { USBDCD }
+/** Interrupt vectors for the USBDCD peripheral type */
+#define USBDCD_IRQS                              { USBDCD_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register instance definitions */
+/* USBDCD */
+#define USBDCD_CONTROL                           USBDCD_CONTROL_REG(USBDCD)
+#define USBDCD_CLOCK                             USBDCD_CLOCK_REG(USBDCD)
+#define USBDCD_STATUS                            USBDCD_STATUS_REG(USBDCD)
+#define USBDCD_TIMER0                            USBDCD_TIMER0_REG(USBDCD)
+#define USBDCD_TIMER1                            USBDCD_TIMER1_REG(USBDCD)
+#define USBDCD_TIMER2_BC11                       USBDCD_TIMER2_BC11_REG(USBDCD)
+#define USBDCD_TIMER2_BC12                       USBDCD_TIMER2_BC12_REG(USBDCD)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base)                       ((base)->TRM)
+#define VREF_SC_REG(base)                        ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK                       0x3Fu
+#define VREF_TRM_TRIM_SHIFT                      0
+#define VREF_TRM_TRIM_WIDTH                      6
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     0x40u
+#define VREF_TRM_CHOPEN_SHIFT                    6
+#define VREF_TRM_CHOPEN_WIDTH                    1
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_TRM_CHOPEN_SHIFT))&VREF_TRM_CHOPEN_MASK)
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK                     0x3u
+#define VREF_SC_MODE_LV_SHIFT                    0
+#define VREF_SC_MODE_LV_WIDTH                    2
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      0x4u
+#define VREF_SC_VREFST_SHIFT                     2
+#define VREF_SC_VREFST_WIDTH                     1
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFST_SHIFT))&VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK                     0x20u
+#define VREF_SC_ICOMPEN_SHIFT                    5
+#define VREF_SC_ICOMPEN_WIDTH                    1
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_ICOMPEN_SHIFT))&VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK                       0x40u
+#define VREF_SC_REGEN_SHIFT                      6
+#define VREF_SC_REGEN_WIDTH                      1
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_SC_REGEN_SHIFT))&VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK                      0x80u
+#define VREF_SC_VREFEN_SHIFT                     7
+#define VREF_SC_VREFEN_WIDTH                     1
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFEN_SHIFT))&VREF_SC_VREFEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR                            (VREF)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM                                 VREF_TRM_REG(VREF)
+#define VREF_SC                                  VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t STCTRLH;                           /**< Watchdog Status and Control Register High, offset: 0x0 */
+  __IO uint16_t STCTRLL;                           /**< Watchdog Status and Control Register Low, offset: 0x2 */
+  __IO uint16_t TOVALH;                            /**< Watchdog Time-out Value Register High, offset: 0x4 */
+  __IO uint16_t TOVALL;                            /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+  __IO uint16_t WINH;                              /**< Watchdog Window Register High, offset: 0x8 */
+  __IO uint16_t WINL;                              /**< Watchdog Window Register Low, offset: 0xA */
+  __IO uint16_t REFRESH;                           /**< Watchdog Refresh register, offset: 0xC */
+  __IO uint16_t UNLOCK;                            /**< Watchdog Unlock register, offset: 0xE */
+  __IO uint16_t TMROUTH;                           /**< Watchdog Timer Output Register High, offset: 0x10 */
+  __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
+  __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
+  __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type, *WDOG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register accessors */
+#define WDOG_STCTRLH_REG(base)                   ((base)->STCTRLH)
+#define WDOG_STCTRLL_REG(base)                   ((base)->STCTRLL)
+#define WDOG_TOVALH_REG(base)                    ((base)->TOVALH)
+#define WDOG_TOVALL_REG(base)                    ((base)->TOVALL)
+#define WDOG_WINH_REG(base)                      ((base)->WINH)
+#define WDOG_WINL_REG(base)                      ((base)->WINL)
+#define WDOG_REFRESH_REG(base)                   ((base)->REFRESH)
+#define WDOG_UNLOCK_REG(base)                    ((base)->UNLOCK)
+#define WDOG_TMROUTH_REG(base)                   ((base)->TMROUTH)
+#define WDOG_TMROUTL_REG(base)                   ((base)->TMROUTL)
+#define WDOG_RSTCNT_REG(base)                    ((base)->RSTCNT)
+#define WDOG_PRESC_REG(base)                     ((base)->PRESC)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK                 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT                0
+#define WDOG_STCTRLH_WDOGEN_WIDTH                1
+#define WDOG_STCTRLH_WDOGEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WDOGEN_SHIFT))&WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK                 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT                1
+#define WDOG_STCTRLH_CLKSRC_WIDTH                1
+#define WDOG_STCTRLH_CLKSRC(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_CLKSRC_SHIFT))&WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK               0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT              2
+#define WDOG_STCTRLH_IRQRSTEN_WIDTH              1
+#define WDOG_STCTRLH_IRQRSTEN(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_IRQRSTEN_SHIFT))&WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK                  0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT                 3
+#define WDOG_STCTRLH_WINEN_WIDTH                 1
+#define WDOG_STCTRLH_WINEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WINEN_SHIFT))&WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK            0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           4
+#define WDOG_STCTRLH_ALLOWUPDATE_WIDTH           1
+#define WDOG_STCTRLH_ALLOWUPDATE(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_ALLOWUPDATE_SHIFT))&WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK                  0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT                 5
+#define WDOG_STCTRLH_DBGEN_WIDTH                 1
+#define WDOG_STCTRLH_DBGEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DBGEN_SHIFT))&WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK                 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT                6
+#define WDOG_STCTRLH_STOPEN_WIDTH                1
+#define WDOG_STCTRLH_STOPEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_STOPEN_SHIFT))&WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK                 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT                7
+#define WDOG_STCTRLH_WAITEN_WIDTH                1
+#define WDOG_STCTRLH_WAITEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WAITEN_SHIFT))&WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK               0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT              10
+#define WDOG_STCTRLH_TESTWDOG_WIDTH              1
+#define WDOG_STCTRLH_TESTWDOG(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTWDOG_SHIFT))&WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK                0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT               11
+#define WDOG_STCTRLH_TESTSEL_WIDTH               1
+#define WDOG_STCTRLH_TESTSEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTSEL_SHIFT))&WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK                0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT               12
+#define WDOG_STCTRLH_BYTESEL_WIDTH               2
+#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK            0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT           14
+#define WDOG_STCTRLH_DISTESTWDOG_WIDTH           1
+#define WDOG_STCTRLH_DISTESTWDOG(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DISTESTWDOG_SHIFT))&WDOG_STCTRLH_DISTESTWDOG_MASK)
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK                 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT                15
+#define WDOG_STCTRLL_INTFLG_WIDTH                1
+#define WDOG_STCTRLL_INTFLG(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLL_INTFLG_SHIFT))&WDOG_STCTRLL_INTFLG_MASK)
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK               0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              0
+#define WDOG_TOVALH_TOVALHIGH_WIDTH              16
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK                0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT               0
+#define WDOG_TOVALL_TOVALLOW_WIDTH               16
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK                   0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT                  0
+#define WDOG_WINH_WINHIGH_WIDTH                  16
+#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK                    0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT                   0
+#define WDOG_WINL_WINLOW_WIDTH                   16
+#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK            0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT           0
+#define WDOG_REFRESH_WDOGREFRESH_WIDTH           16
+#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK              0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             0
+#define WDOG_UNLOCK_WDOGUNLOCK_WIDTH             16
+#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK           0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          0
+#define WDOG_TMROUTH_TIMEROUTHIGH_WIDTH          16
+#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK            0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           0
+#define WDOG_TMROUTL_TIMEROUTLOW_WIDTH           16
+#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK                  0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT                 0
+#define WDOG_RSTCNT_RSTCNT_WIDTH                 16
+#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK                 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT                8
+#define WDOG_PRESC_PRESCVAL_WIDTH                3
+#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+#define WDOG_BASE_PTR                            (WDOG)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS                          { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS                           { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS                                { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register instance definitions */
+/* WDOG */
+#define WDOG_STCTRLH                             WDOG_STCTRLH_REG(WDOG)
+#define WDOG_STCTRLL                             WDOG_STCTRLL_REG(WDOG)
+#define WDOG_TOVALH                              WDOG_TOVALH_REG(WDOG)
+#define WDOG_TOVALL                              WDOG_TOVALL_REG(WDOG)
+#define WDOG_WINH                                WDOG_WINH_REG(WDOG)
+#define WDOG_WINL                                WDOG_WINL_REG(WDOG)
+#define WDOG_REFRESH                             WDOG_REFRESH_REG(WDOG)
+#define WDOG_UNLOCK                              WDOG_UNLOCK_REG(WDOG)
+#define WDOG_TMROUTH                             WDOG_TMROUTH_REG(WDOG)
+#define WDOG_TMROUTL                             WDOG_TMROUTL_REG(WDOG)
+#define WDOG_RSTCNT                              WDOG_RSTCNT_REG(WDOG)
+#define WDOG_PRESC                               WDOG_PRESC_REG(WDOG)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Backward Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define DMA_EARS_REG(base)                       This_symbol_has_been_deprecated
+#define DMA_EARS                                 This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_SHIFT                  This_symbol_has_been_deprecated
+#define ENET_RMON_T_DROP_REG(base)               This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP_REG(base)               This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE_REG(base)                This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0_REG(base)            This_symbol_has_been_deprecated
+#define ENET_RMON_R_DROP_REG(base)               ENET_IEEE_R_DROP_REG(base)
+#define ENET_RMON_R_FRAME_OK_REG(base)           ENET_IEEE_R_FRAME_OK_REG(base)
+#define ENET_RMON_T_DROP                         This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP                         This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE                          This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0                      This_symbol_has_been_deprecated
+#define MCG_C9_REG(base)                         This_symbol_has_been_deprecated
+#define MCG_C2_EREFS0_MASK                       MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT                      MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK                         MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT                        MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK                       MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT                      MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x)                         MCG_C2_RANGE(x)
+#define MCG_C9                                   This_symbol_has_been_deprecated
+#define MCM_PLACR_REG(base)                      This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_MASK                       This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_SHIFT                      This_symbol_has_been_deprecated
+#define MCM_PLACR                                This_symbol_has_been_deprecated
+#define ADC_BASES                    ADC_BASE_PTRS
+#define AIPS_BASES                   AIPS_BASE_PTRS
+#define AXBS_BASES                   AXBS_BASE_PTRS
+#define CAN_BASES                    CAN_BASE_PTRS
+#define CAU_BASES                    CAU_BASE_PTRS
+#define CMP_BASES                    CMP_BASE_PTRS
+#define CMT_BASES                    CMT_BASE_PTRS
+#define CRC_BASES                    CRC_BASE_PTRS
+#define DAC_BASES                    DAC_BASE_PTRS
+#define DMA_BASES                    DMA_BASE_PTRS
+#define DMAMUX_BASES                 DMAMUX_BASE_PTRS
+#define ENET_BASES                   ENET_BASE_PTRS
+#define EWM_BASES                    EWM_BASE_PTRS
+#define FB_BASES                     FB_BASE_PTRS
+#define FMC_BASES                    FMC_BASE_PTRS
+#define FTFE_BASES                   FTFE_BASE_PTRS
+#define FTM_BASES                    FTM_BASE_PTRS
+#define GPIO_BASES                   GPIO_BASE_PTRS
+#define I2C_BASES                    I2C_BASE_PTRS
+#define I2S_BASES                    I2S_BASE_PTRS
+#define LLWU_BASES                   LLWU_BASE_PTRS
+#define LPTMR_BASES                  LPTMR_BASE_PTRS
+#define MCG_BASES                    MCG_BASE_PTRS
+#define MCM_ISR_REG(base)            MCM_ISCR_REG(base)
+#define MCM_ISR_FIOC_MASK            MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT           MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK            MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT           MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK            MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT           MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK            MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT           MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK            MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT           MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK            MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT           MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK           MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT          MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK           MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT          MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK           MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT          MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK           MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT          MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK           MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT          MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK           MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT          MCM_ISCR_FIDCE_SHIFT
+#define MCM_BASES                    MCM_BASE_PTRS
+#define MPU_BASES                    MPU_BASE_PTRS
+#define NV_BASES                     NV_BASE_PTRS
+#define OSC_BASES                    OSC_BASE_PTRS
+#define PDB_BASES                    PDB_BASE_PTRS
+#define PIT_BASES                    PIT_BASE_PTRS
+#define PMC_BASES                    PMC_BASE_PTRS
+#define PORT_BASES                   PORT_BASE_PTRS
+#define RCM_BASES                    RCM_BASE_PTRS
+#define RFSYS_BASES                  RFSYS_BASE_PTRS
+#define RFVBAT_BASES                 RFVBAT_BASE_PTRS
+#define RNG_BASES                    RNG_BASE_PTRS
+#define RTC_BASES                    RTC_BASE_PTRS
+#define SDHC_BASES                   SDHC_BASE_PTRS
+#define SIM_BASES                    SIM_BASE_PTRS
+#define SMC_BASES                    SMC_BASE_PTRS
+#define SPI_BASES                    SPI_BASE_PTRS
+#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
+#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
+#define UART_WP7816_T_TYPE0_WI_MASK  UART_WP7816T0_WI_MASK
+#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
+#define UART_WP7816_T_TYPE0_WI(x)    UART_WP7816T0_WI(x)
+#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
+#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
+#define UART_WP7816_T_TYPE1_BWI(x)   UART_WP7816T1_BWI(x)
+#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
+#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
+#define UART_WP7816_T_TYPE1_CWI(x)   UART_WP7816T1_CWI(x)
+#define UART_BASES                   UART_BASE_PTRS
+#define USB_BASES                    USB_BASE_PTRS
+#define USBDCD_BASES                 USBDCD_BASE_PTRS
+#define VREF_BASES                   VREF_BASE_PTRS
+#define WDOG_BASES                   WDOG_BASE_PTRS
+#define Watchdog_IRQn                WDOG_EWM_IRQn
+#define Watchdog_IRQHandler          WDOG_EWM_IRQHandler
+#define LPTimer_IRQn                 LPTMR0_IRQn
+#define LPTimer_IRQHandler           LPTMR0_IRQHandler
+#define LLW_IRQn                     LLWU_IRQn
+#define LLW_IRQHandler               LLWU_IRQHandler
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MK64F12_H_) */
+  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+  #if (MCU_MEM_MAP_VERSION != 0x0200u)
+    #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+      #warning There are included two not compatible versions of memory maps. Please check possible differences.
+    #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+  #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
+#endif  /* #if !defined(MK64F12_H_) */
+
+/* MK64F12.h, eof. */
diff --git a/Workspace/FTM_AND_PWM/SDK/platform/devices/MK64F12/include/MK64F12_extension.h b/Workspace/FTM_AND_PWM/SDK/platform/devices/MK64F12/include/MK64F12_extension.h
new file mode 100644
index 0000000..c47b6c4
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/SDK/platform/devices/MK64F12/include/MK64F12_extension.h
@@ -0,0 +1,63846 @@
+/*
+** ###################################################################
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150612
+**
+**     Abstract:
+**         Extension to the CMSIS register access layer header.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __MK64F12_EXTENSION_H__
+#define __MK64F12_EXTENSION_H__
+
+#include "MK64F12.h"
+#include "fsl_bitaccess.h"
+
+#if defined(__IAR_SYSTEMS_ICC__)
+  /*
+   * Suppress "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)"
+   * as some register descriptions contain code examples
+   */
+  #pragma diag_suppress=pm008
+#endif
+
+/*
+ * MK64F12 ADC
+ *
+ * Analog-to-Digital Converter
+ *
+ * Registers defined in this header file:
+ * - ADC_SC1 - ADC Status and Control Registers 1
+ * - ADC_CFG1 - ADC Configuration Register 1
+ * - ADC_CFG2 - ADC Configuration Register 2
+ * - ADC_R - ADC Data Result Register
+ * - ADC_CV1 - Compare Value Registers
+ * - ADC_CV2 - Compare Value Registers
+ * - ADC_SC2 - Status and Control Register 2
+ * - ADC_SC3 - Status and Control Register 3
+ * - ADC_OFS - ADC Offset Correction Register
+ * - ADC_PG - ADC Plus-Side Gain Register
+ * - ADC_MG - ADC Minus-Side Gain Register
+ * - ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ */
+
+#define ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
+#define ADC0_IDX (0U) /*!< Instance number for ADC0. */
+#define ADC1_IDX (1U) /*!< Instance number for ADC1. */
+
+/*******************************************************************************
+ * ADC_SC1 - ADC Status and Control Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC1 - ADC Status and Control Registers 1 (RW)
+ *
+ * Reset value: 0x0000001FU
+ *
+ * SC1A is used for both software and hardware trigger modes of operation. To
+ * allow sequential conversions of the ADC to be triggered by internal peripherals,
+ * the ADC can have more than one status and control register: one for each
+ * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
+ * for use only in hardware trigger mode. See the chip configuration information
+ * about the number of SC1n registers specific to this device. The SC1n registers
+ * have identical fields, and are used in a "ping-pong" approach to control ADC
+ * operation. At any one point in time, only one of the SC1n registers is actively
+ * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
+ * a conversion is allowed, and vice-versa for any of the SC1n registers specific
+ * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
+ * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
+ * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
+ * value other than all 1s. Writing any of the SC1n registers while that specific
+ * SC1n register is actively controlling a conversion aborts the current conversion.
+ * None of the SC1B-SC1n registers are used for software trigger operation and
+ * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC1 register
+ */
+/*@{*/
+#define ADC_RD_SC1(base, index)  (ADC_SC1_REG(base, index))
+#define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value))
+#define ADC_RMW_SC1(base, index, mask, value) (ADC_WR_SC1(base, index, (ADC_RD_SC1(base, index) & ~(mask)) | (value)))
+#define ADC_SET_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) |  (value)))
+#define ADC_CLR_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) & ~(value)))
+#define ADC_TOG_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC1 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC1, field ADCH[4:0] (RW)
+ *
+ * Selects one of the input channels. The input channel decode depends on the
+ * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
+ * DADMx. Some of the input channel options in the bitfield-setting descriptions might
+ * not be available for your device. For the actual ADC channel assignments for
+ * your device, see the Chip Configuration details. The successive approximation
+ * converter subsystem is turned off when the channel select bits are all set,
+ * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
+ * isolation of the input channel from all sources. Terminating continuous
+ * conversions this way prevents an additional single conversion from being performed. It
+ * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
+ * when continuous conversions are not enabled because the module automatically
+ * enters a low-power state when a conversion completes.
+ *
+ * Values:
+ * - 0b00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
+ *     selected as input.
+ * - 0b00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
+ *     selected as input.
+ * - 0b00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
+ *     selected as input.
+ * - 0b00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
+ *     selected as input.
+ * - 0b00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b11000 - Reserved.
+ * - 0b11001 - Reserved.
+ * - 0b11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input;
+ *     when DIFF=1, Temp Sensor (differential) is selected as input.
+ * - 0b11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
+ *     DIFF=1, Bandgap (differential) is selected as input.
+ * - 0b11100 - Reserved.
+ * - 0b11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
+ *     (differential) is selected as input. Voltage reference selected is determined
+ *     by SC2[REFSEL].
+ * - 0b11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
+ *     reserved. Voltage reference selected is determined by SC2[REFSEL].
+ * - 0b11111 - Module is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_ADCH field. */
+#define ADC_RD_SC1_ADCH(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_ADCH_MASK) >> ADC_SC1_ADCH_SHIFT)
+#define ADC_BRD_SC1_ADCH(base, index) (ADC_RD_SC1_ADCH(base, index))
+
+/*! @brief Set the ADCH field to a new value. */
+#define ADC_WR_SC1_ADCH(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_ADCH_MASK, ADC_SC1_ADCH(value)))
+#define ADC_BWR_SC1_ADCH(base, index, value) (ADC_WR_SC1_ADCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field DIFF[5] (RW)
+ *
+ * Configures the ADC to operate in differential mode. When enabled, this mode
+ * automatically selects from the differential channels, and changes the
+ * conversion algorithm and the number of cycles to complete a conversion.
+ *
+ * Values:
+ * - 0b0 - Single-ended conversions and input channels are selected.
+ * - 0b1 - Differential conversions and input channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_DIFF field. */
+#define ADC_RD_SC1_DIFF(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_DIFF_MASK) >> ADC_SC1_DIFF_SHIFT)
+#define ADC_BRD_SC1_DIFF(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT))
+
+/*! @brief Set the DIFF field to a new value. */
+#define ADC_WR_SC1_DIFF(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_DIFF_MASK, ADC_SC1_DIFF(value)))
+#define ADC_BWR_SC1_DIFF(base, index, value) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field AIEN[6] (RW)
+ *
+ * Enables conversion complete interrupts. When COCO becomes set while the
+ * respective AIEN is high, an interrupt is asserted.
+ *
+ * Values:
+ * - 0b0 - Conversion complete interrupt is disabled.
+ * - 0b1 - Conversion complete interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_AIEN field. */
+#define ADC_RD_SC1_AIEN(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIEN_SHIFT)
+#define ADC_BRD_SC1_AIEN(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT))
+
+/*! @brief Set the AIEN field to a new value. */
+#define ADC_WR_SC1_AIEN(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_AIEN_MASK, ADC_SC1_AIEN(value)))
+#define ADC_BWR_SC1_AIEN(base, index, value) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field COCO[7] (RO)
+ *
+ * This is a read-only field that is set each time a conversion is completed
+ * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
+ * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
+ * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
+ * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
+ * COCO is set upon completion of the selected number of conversions (determined
+ * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
+ * COCO is cleared when the respective SC1n register is written or when the
+ * respective Rn register is read.
+ *
+ * Values:
+ * - 0b0 - Conversion is not completed.
+ * - 0b1 - Conversion is completed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_COCO field. */
+#define ADC_RD_SC1_COCO(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_COCO_MASK) >> ADC_SC1_COCO_SHIFT)
+#define ADC_BRD_SC1_COCO(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG1 - ADC Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG1 - ADC Configuration Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The configuration Register 1 (CFG1) selects the mode of operation, clock
+ * source, clock divide, and configuration for low power or long sample time.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG1 register
+ */
+/*@{*/
+#define ADC_RD_CFG1(base)        (ADC_CFG1_REG(base))
+#define ADC_WR_CFG1(base, value) (ADC_CFG1_REG(base) = (value))
+#define ADC_RMW_CFG1(base, mask, value) (ADC_WR_CFG1(base, (ADC_RD_CFG1(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) |  (value)))
+#define ADC_CLR_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) & ~(value)))
+#define ADC_TOG_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
+ *
+ * Selects the input clock source to generate the internal clock, ADCK. Note
+ * that when the ADACK clock source is selected, it is not required to be active
+ * prior to conversion start. When it is selected and it is not active prior to a
+ * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
+ * the start of a conversion and deactivated when conversions are terminated. In
+ * this case, there is an associated clock startup delay each time the clock
+ * source is re-activated.
+ *
+ * Values:
+ * - 0b00 - Bus clock
+ * - 0b01 - Alternate clock 2 (ALTCLK2)
+ * - 0b10 - Alternate clock (ALTCLK)
+ * - 0b11 - Asynchronous clock (ADACK)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADICLK field. */
+#define ADC_RD_CFG1_ADICLK(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADICLK_MASK) >> ADC_CFG1_ADICLK_SHIFT)
+#define ADC_BRD_CFG1_ADICLK(base) (ADC_RD_CFG1_ADICLK(base))
+
+/*! @brief Set the ADICLK field to a new value. */
+#define ADC_WR_CFG1_ADICLK(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADICLK_MASK, ADC_CFG1_ADICLK(value)))
+#define ADC_BWR_CFG1_ADICLK(base, value) (ADC_WR_CFG1_ADICLK(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field MODE[3:2] (RW)
+ *
+ * Selects the ADC resolution mode.
+ *
+ * Values:
+ * - 0b00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
+ *     differential 9-bit conversion with 2's complement output.
+ * - 0b01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it
+ *     is differential 13-bit conversion with 2's complement output.
+ * - 0b10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it
+ *     is differential 11-bit conversion with 2's complement output
+ * - 0b11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it
+ *     is differential 16-bit conversion with 2's complement output
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_MODE field. */
+#define ADC_RD_CFG1_MODE(base) ((ADC_CFG1_REG(base) & ADC_CFG1_MODE_MASK) >> ADC_CFG1_MODE_SHIFT)
+#define ADC_BRD_CFG1_MODE(base) (ADC_RD_CFG1_MODE(base))
+
+/*! @brief Set the MODE field to a new value. */
+#define ADC_WR_CFG1_MODE(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_MODE_MASK, ADC_CFG1_MODE(value)))
+#define ADC_BWR_CFG1_MODE(base, value) (ADC_WR_CFG1_MODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLSMP[4] (RW)
+ *
+ * Selects between different sample times based on the conversion mode selected.
+ * This field adjusts the sample period to allow higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption if
+ * continuous conversions are enabled and high conversion rates are not required.
+ * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
+ * extent of the long sample time.
+ *
+ * Values:
+ * - 0b0 - Short sample time.
+ * - 0b1 - Long sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
+#define ADC_RD_CFG1_ADLSMP(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLSMP_MASK) >> ADC_CFG1_ADLSMP_SHIFT)
+#define ADC_BRD_CFG1_ADLSMP(base) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT))
+
+/*! @brief Set the ADLSMP field to a new value. */
+#define ADC_WR_CFG1_ADLSMP(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLSMP_MASK, ADC_CFG1_ADLSMP(value)))
+#define ADC_BWR_CFG1_ADLSMP(base, value) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADIV[6:5] (RW)
+ *
+ * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
+ *
+ * Values:
+ * - 0b00 - The divide ratio is 1 and the clock rate is input clock.
+ * - 0b01 - The divide ratio is 2 and the clock rate is (input clock)/2.
+ * - 0b10 - The divide ratio is 4 and the clock rate is (input clock)/4.
+ * - 0b11 - The divide ratio is 8 and the clock rate is (input clock)/8.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADIV field. */
+#define ADC_RD_CFG1_ADIV(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT)
+#define ADC_BRD_CFG1_ADIV(base) (ADC_RD_CFG1_ADIV(base))
+
+/*! @brief Set the ADIV field to a new value. */
+#define ADC_WR_CFG1_ADIV(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADIV_MASK, ADC_CFG1_ADIV(value)))
+#define ADC_BWR_CFG1_ADIV(base, value) (ADC_WR_CFG1_ADIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLPC[7] (RW)
+ *
+ * Controls the power configuration of the successive approximation converter.
+ * This optimizes power consumption when higher sample rates are not required.
+ *
+ * Values:
+ * - 0b0 - Normal power configuration.
+ * - 0b1 - Low-power configuration. The power is reduced at the expense of
+ *     maximum clock speed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLPC field. */
+#define ADC_RD_CFG1_ADLPC(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLPC_MASK) >> ADC_CFG1_ADLPC_SHIFT)
+#define ADC_BRD_CFG1_ADLPC(base) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT))
+
+/*! @brief Set the ADLPC field to a new value. */
+#define ADC_WR_CFG1_ADLPC(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLPC_MASK, ADC_CFG1_ADLPC(value)))
+#define ADC_BWR_CFG1_ADLPC(base, value) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG2 - ADC Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG2 - ADC Configuration Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Configuration Register 2 (CFG2) selects the special high-speed configuration
+ * for very high speed conversions and selects the long sample time duration
+ * during long sample mode.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG2 register
+ */
+/*@{*/
+#define ADC_RD_CFG2(base)        (ADC_CFG2_REG(base))
+#define ADC_WR_CFG2(base, value) (ADC_CFG2_REG(base) = (value))
+#define ADC_RMW_CFG2(base, mask, value) (ADC_WR_CFG2(base, (ADC_RD_CFG2(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) |  (value)))
+#define ADC_CLR_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) & ~(value)))
+#define ADC_TOG_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
+ *
+ * Selects between the extended sample times when long sample time is selected,
+ * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption when
+ * continuous conversions are enabled if high conversion rates are not required.
+ *
+ * Values:
+ * - 0b00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
+ *     total.
+ * - 0b01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
+ * - 0b10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
+ * - 0b11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
+#define ADC_RD_CFG2_ADLSTS(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADLSTS_MASK) >> ADC_CFG2_ADLSTS_SHIFT)
+#define ADC_BRD_CFG2_ADLSTS(base) (ADC_RD_CFG2_ADLSTS(base))
+
+/*! @brief Set the ADLSTS field to a new value. */
+#define ADC_WR_CFG2_ADLSTS(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADLSTS_MASK, ADC_CFG2_ADLSTS(value)))
+#define ADC_BWR_CFG2_ADLSTS(base, value) (ADC_WR_CFG2_ADLSTS(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADHSC[2] (RW)
+ *
+ * Configures the ADC for very high-speed operation. The conversion sequence is
+ * altered with 2 ADCK cycles added to the conversion time to allow higher speed
+ * conversion clocks.
+ *
+ * Values:
+ * - 0b0 - Normal conversion sequence selected.
+ * - 0b1 - High-speed conversion sequence selected with 2 additional ADCK cycles
+ *     to total conversion time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADHSC field. */
+#define ADC_RD_CFG2_ADHSC(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADHSC_MASK) >> ADC_CFG2_ADHSC_SHIFT)
+#define ADC_BRD_CFG2_ADHSC(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT))
+
+/*! @brief Set the ADHSC field to a new value. */
+#define ADC_WR_CFG2_ADHSC(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADHSC_MASK, ADC_CFG2_ADHSC(value)))
+#define ADC_BWR_CFG2_ADHSC(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADACKEN[3] (RW)
+ *
+ * Enables the asynchronous clock source and the clock source output regardless
+ * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
+ * asynchronous clock may be used by other modules. See chip configuration
+ * information. Setting this field allows the clock to be used even while the ADC is
+ * idle or operating from a different clock source. Also, latency of initiating a
+ * single or first-continuous conversion with the asynchronous clock selected is
+ * reduced because the ADACK clock is already operational.
+ *
+ * Values:
+ * - 0b0 - Asynchronous clock output disabled; Asynchronous clock is enabled
+ *     only if selected by ADICLK and a conversion is active.
+ * - 0b1 - Asynchronous clock and clock output is enabled regardless of the
+ *     state of the ADC.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
+#define ADC_RD_CFG2_ADACKEN(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADACKEN_MASK) >> ADC_CFG2_ADACKEN_SHIFT)
+#define ADC_BRD_CFG2_ADACKEN(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT))
+
+/*! @brief Set the ADACKEN field to a new value. */
+#define ADC_WR_CFG2_ADACKEN(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADACKEN_MASK, ADC_CFG2_ADACKEN(value)))
+#define ADC_BWR_CFG2_ADACKEN(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field MUXSEL[4] (RW)
+ *
+ * Changes the ADC mux setting to select between alternate sets of ADC channels.
+ *
+ * Values:
+ * - 0b0 - ADxxa channels are selected.
+ * - 0b1 - ADxxb channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
+#define ADC_RD_CFG2_MUXSEL(base) ((ADC_CFG2_REG(base) & ADC_CFG2_MUXSEL_MASK) >> ADC_CFG2_MUXSEL_SHIFT)
+#define ADC_BRD_CFG2_MUXSEL(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT))
+
+/*! @brief Set the MUXSEL field to a new value. */
+#define ADC_WR_CFG2_MUXSEL(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_MUXSEL_MASK, ADC_CFG2_MUXSEL(value)))
+#define ADC_BWR_CFG2_MUXSEL(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_R - ADC Data Result Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_R - ADC Data Result Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The data result registers (Rn) contain the result of an ADC conversion of the
+ * channel selected by the corresponding status and channel control register
+ * (SC1A:SC1n). For every status and channel control register, there is a
+ * corresponding data result register. Unused bits in R n are cleared in unsigned
+ * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
+ * For example, when configured for 10-bit single-ended mode, D[15:10] are
+ * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
+ * that is, bit 10 extended through bit 15. The following table describes the
+ * behavior of the data result registers in the different modes of operation. Data
+ * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
+ * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
+ * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
+ * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
+ * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
+ * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
+ * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
+ * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
+ * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
+ * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
+ * 2's complement data if indicated
+ */
+/*!
+ * @name Constants and macros for entire ADC_R register
+ */
+/*@{*/
+#define ADC_RD_R(base, index)    (ADC_R_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_R bitfields
+ */
+
+/*!
+ * @name Register ADC_R, field D[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_R_D field. */
+#define ADC_RD_R_D(base, index) ((ADC_R_REG(base, index) & ADC_R_D_MASK) >> ADC_R_D_SHIFT)
+#define ADC_BRD_R_D(base, index) (ADC_RD_R_D(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV1 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV1 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV1 register
+ */
+/*@{*/
+#define ADC_RD_CV1(base)         (ADC_CV1_REG(base))
+#define ADC_WR_CV1(base, value)  (ADC_CV1_REG(base) = (value))
+#define ADC_RMW_CV1(base, mask, value) (ADC_WR_CV1(base, (ADC_RD_CV1(base) & ~(mask)) | (value)))
+#define ADC_SET_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) |  (value)))
+#define ADC_CLR_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) & ~(value)))
+#define ADC_TOG_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV1, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV1_CV field. */
+#define ADC_RD_CV1_CV(base)  ((ADC_CV1_REG(base) & ADC_CV1_CV_MASK) >> ADC_CV1_CV_SHIFT)
+#define ADC_BRD_CV1_CV(base) (ADC_RD_CV1_CV(base))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV1_CV(base, value) (ADC_RMW_CV1(base, ADC_CV1_CV_MASK, ADC_CV1_CV(value)))
+#define ADC_BWR_CV1_CV(base, value) (ADC_WR_CV1_CV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV2 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV2 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV2 register
+ */
+/*@{*/
+#define ADC_RD_CV2(base)         (ADC_CV2_REG(base))
+#define ADC_WR_CV2(base, value)  (ADC_CV2_REG(base) = (value))
+#define ADC_RMW_CV2(base, mask, value) (ADC_WR_CV2(base, (ADC_RD_CV2(base) & ~(mask)) | (value)))
+#define ADC_SET_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) |  (value)))
+#define ADC_CLR_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) & ~(value)))
+#define ADC_TOG_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV2, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV2_CV field. */
+#define ADC_RD_CV2_CV(base)  ((ADC_CV2_REG(base) & ADC_CV2_CV_MASK) >> ADC_CV2_CV_SHIFT)
+#define ADC_BRD_CV2_CV(base) (ADC_RD_CV2_CV(base))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV2_CV(base, value) (ADC_RMW_CV2(base, ADC_CV2_CV_MASK, ADC_CV2_CV(value)))
+#define ADC_BWR_CV2_CV(base, value) (ADC_WR_CV2_CV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC2 - Status and Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC2 - Status and Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The status and control register 2 (SC2) contains the conversion active,
+ * hardware/software trigger select, compare function, and voltage reference select of
+ * the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC2 register
+ */
+/*@{*/
+#define ADC_RD_SC2(base)         (ADC_SC2_REG(base))
+#define ADC_WR_SC2(base, value)  (ADC_SC2_REG(base) = (value))
+#define ADC_RMW_SC2(base, mask, value) (ADC_WR_SC2(base, (ADC_RD_SC2(base) & ~(mask)) | (value)))
+#define ADC_SET_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) |  (value)))
+#define ADC_CLR_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) & ~(value)))
+#define ADC_TOG_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC2 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC2, field REFSEL[1:0] (RW)
+ *
+ * Selects the voltage reference source used for conversions.
+ *
+ * Values:
+ * - 0b00 - Default voltage reference pin pair, that is, external pins VREFH and
+ *     VREFL
+ * - 0b01 - Alternate reference pair, that is, VALTH and VALTL . This pair may
+ *     be additional external pins or internal sources depending on the MCU
+ *     configuration. See the chip configuration information for details specific to
+ *     this MCU
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_REFSEL field. */
+#define ADC_RD_SC2_REFSEL(base) ((ADC_SC2_REG(base) & ADC_SC2_REFSEL_MASK) >> ADC_SC2_REFSEL_SHIFT)
+#define ADC_BRD_SC2_REFSEL(base) (ADC_RD_SC2_REFSEL(base))
+
+/*! @brief Set the REFSEL field to a new value. */
+#define ADC_WR_SC2_REFSEL(base, value) (ADC_RMW_SC2(base, ADC_SC2_REFSEL_MASK, ADC_SC2_REFSEL(value)))
+#define ADC_BWR_SC2_REFSEL(base, value) (ADC_WR_SC2_REFSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field DMAEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled and will assert the ADC DMA request during an ADC
+ *     conversion complete event noted when any of the SC1n[COCO] flags is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_DMAEN field. */
+#define ADC_RD_SC2_DMAEN(base) ((ADC_SC2_REG(base) & ADC_SC2_DMAEN_MASK) >> ADC_SC2_DMAEN_SHIFT)
+#define ADC_BRD_SC2_DMAEN(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define ADC_WR_SC2_DMAEN(base, value) (ADC_RMW_SC2(base, ADC_SC2_DMAEN_MASK, ADC_SC2_DMAEN(value)))
+#define ADC_BWR_SC2_DMAEN(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACREN[3] (RW)
+ *
+ * Configures the compare function to check if the conversion result of the
+ * input being monitored is either between or outside the range formed by CV1 and CV2
+ * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
+ * effect.
+ *
+ * Values:
+ * - 0b0 - Range function disabled. Only CV1 is compared.
+ * - 0b1 - Range function enabled. Both CV1 and CV2 are compared.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACREN field. */
+#define ADC_RD_SC2_ACREN(base) ((ADC_SC2_REG(base) & ADC_SC2_ACREN_MASK) >> ADC_SC2_ACREN_SHIFT)
+#define ADC_BRD_SC2_ACREN(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT))
+
+/*! @brief Set the ACREN field to a new value. */
+#define ADC_WR_SC2_ACREN(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACREN_MASK, ADC_SC2_ACREN(value)))
+#define ADC_BWR_SC2_ACREN(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFGT[4] (RW)
+ *
+ * Configures the compare function to check the conversion result relative to
+ * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
+ * have any effect.
+ *
+ * Values:
+ * - 0b0 - Configures less than threshold, outside range not inclusive and
+ *     inside range not inclusive; functionality based on the values placed in CV1 and
+ *     CV2.
+ * - 0b1 - Configures greater than or equal to threshold, outside and inside
+ *     ranges inclusive; functionality based on the values placed in CV1 and CV2.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFGT field. */
+#define ADC_RD_SC2_ACFGT(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFGT_MASK) >> ADC_SC2_ACFGT_SHIFT)
+#define ADC_BRD_SC2_ACFGT(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT))
+
+/*! @brief Set the ACFGT field to a new value. */
+#define ADC_WR_SC2_ACFGT(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFGT_MASK, ADC_SC2_ACFGT(value)))
+#define ADC_BWR_SC2_ACFGT(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFE[5] (RW)
+ *
+ * Enables the compare function.
+ *
+ * Values:
+ * - 0b0 - Compare function disabled.
+ * - 0b1 - Compare function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFE field. */
+#define ADC_RD_SC2_ACFE(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFE_MASK) >> ADC_SC2_ACFE_SHIFT)
+#define ADC_BRD_SC2_ACFE(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT))
+
+/*! @brief Set the ACFE field to a new value. */
+#define ADC_WR_SC2_ACFE(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFE_MASK, ADC_SC2_ACFE(value)))
+#define ADC_BWR_SC2_ACFE(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADTRG[6] (RW)
+ *
+ * Selects the type of trigger used for initiating a conversion. Two types of
+ * trigger are selectable: Software trigger: When software trigger is selected, a
+ * conversion is initiated following a write to SC1A. Hardware trigger: When
+ * hardware trigger is selected, a conversion is initiated following the assertion of
+ * the ADHWT input after a pulse of the ADHWTSn input.
+ *
+ * Values:
+ * - 0b0 - Software trigger selected.
+ * - 0b1 - Hardware trigger selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADTRG field. */
+#define ADC_RD_SC2_ADTRG(base) ((ADC_SC2_REG(base) & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT)
+#define ADC_BRD_SC2_ADTRG(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT))
+
+/*! @brief Set the ADTRG field to a new value. */
+#define ADC_WR_SC2_ADTRG(base, value) (ADC_RMW_SC2(base, ADC_SC2_ADTRG_MASK, ADC_SC2_ADTRG(value)))
+#define ADC_BWR_SC2_ADTRG(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADACT[7] (RO)
+ *
+ * Indicates that a conversion or hardware averaging is in progress. ADACT is
+ * set when a conversion is initiated and cleared when a conversion is completed or
+ * aborted.
+ *
+ * Values:
+ * - 0b0 - Conversion not in progress.
+ * - 0b1 - Conversion in progress.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADACT field. */
+#define ADC_RD_SC2_ADACT(base) ((ADC_SC2_REG(base) & ADC_SC2_ADACT_MASK) >> ADC_SC2_ADACT_SHIFT)
+#define ADC_BRD_SC2_ADACT(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADACT_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC3 - Status and Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC3 - Status and Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Status and Control Register 3 (SC3) controls the calibration, continuous
+ * convert, and hardware averaging functions of the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC3 register
+ */
+/*@{*/
+#define ADC_RD_SC3(base)         (ADC_SC3_REG(base))
+#define ADC_WR_SC3(base, value)  (ADC_SC3_REG(base) = (value))
+#define ADC_RMW_SC3(base, mask, value) (ADC_WR_SC3(base, (ADC_RD_SC3(base) & ~(mask)) | (value)))
+#define ADC_SET_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) |  (value)))
+#define ADC_CLR_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) & ~(value)))
+#define ADC_TOG_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC3 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC3, field AVGS[1:0] (RW)
+ *
+ * Determines how many ADC conversions will be averaged to create the ADC
+ * average result.
+ *
+ * Values:
+ * - 0b00 - 4 samples averaged.
+ * - 0b01 - 8 samples averaged.
+ * - 0b10 - 16 samples averaged.
+ * - 0b11 - 32 samples averaged.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGS field. */
+#define ADC_RD_SC3_AVGS(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGS_MASK) >> ADC_SC3_AVGS_SHIFT)
+#define ADC_BRD_SC3_AVGS(base) (ADC_RD_SC3_AVGS(base))
+
+/*! @brief Set the AVGS field to a new value. */
+#define ADC_WR_SC3_AVGS(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGS_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGS(value)))
+#define ADC_BWR_SC3_AVGS(base, value) (ADC_WR_SC3_AVGS(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field AVGE[2] (RW)
+ *
+ * Enables the hardware average function of the ADC.
+ *
+ * Values:
+ * - 0b0 - Hardware average function disabled.
+ * - 0b1 - Hardware average function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGE field. */
+#define ADC_RD_SC3_AVGE(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGE_MASK) >> ADC_SC3_AVGE_SHIFT)
+#define ADC_BRD_SC3_AVGE(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT))
+
+/*! @brief Set the AVGE field to a new value. */
+#define ADC_WR_SC3_AVGE(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGE_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGE(value)))
+#define ADC_BWR_SC3_AVGE(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field ADCO[3] (RW)
+ *
+ * Enables continuous conversions.
+ *
+ * Values:
+ * - 0b0 - One conversion or one set of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ * - 0b1 - Continuous conversions or sets of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_ADCO field. */
+#define ADC_RD_SC3_ADCO(base) ((ADC_SC3_REG(base) & ADC_SC3_ADCO_MASK) >> ADC_SC3_ADCO_SHIFT)
+#define ADC_BRD_SC3_ADCO(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT))
+
+/*! @brief Set the ADCO field to a new value. */
+#define ADC_WR_SC3_ADCO(base, value) (ADC_RMW_SC3(base, (ADC_SC3_ADCO_MASK | ADC_SC3_CALF_MASK), ADC_SC3_ADCO(value)))
+#define ADC_BWR_SC3_ADCO(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CALF[6] (W1C)
+ *
+ * Displays the result of the calibration sequence. The calibration sequence
+ * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
+ * entered before the calibration sequence completes. Writing 1 to CALF clears it.
+ *
+ * Values:
+ * - 0b0 - Calibration completed normally.
+ * - 0b1 - Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CALF field. */
+#define ADC_RD_SC3_CALF(base) ((ADC_SC3_REG(base) & ADC_SC3_CALF_MASK) >> ADC_SC3_CALF_SHIFT)
+#define ADC_BRD_SC3_CALF(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT))
+
+/*! @brief Set the CALF field to a new value. */
+#define ADC_WR_SC3_CALF(base, value) (ADC_RMW_SC3(base, ADC_SC3_CALF_MASK, ADC_SC3_CALF(value)))
+#define ADC_BWR_SC3_CALF(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CAL[7] (RW)
+ *
+ * Begins the calibration sequence when set. This field stays set while the
+ * calibration is in progress and is cleared when the calibration sequence is
+ * completed. CALF must be checked to determine the result of the calibration sequence.
+ * Once started, the calibration routine cannot be interrupted by writes to the
+ * ADC registers or the results will be invalid and CALF will set. Setting CAL
+ * will abort any current conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CAL field. */
+#define ADC_RD_SC3_CAL(base) ((ADC_SC3_REG(base) & ADC_SC3_CAL_MASK) >> ADC_SC3_CAL_SHIFT)
+#define ADC_BRD_SC3_CAL(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT))
+
+/*! @brief Set the CAL field to a new value. */
+#define ADC_WR_SC3_CAL(base, value) (ADC_RMW_SC3(base, (ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK), ADC_SC3_CAL(value)))
+#define ADC_BWR_SC3_CAL(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_OFS - ADC Offset Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_OFS - ADC Offset Correction Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * The ADC Offset Correction Register (OFS) contains the user-selected or
+ * calibration-generated offset error correction value. This register is a 2's
+ * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
+ * conversion and the result is transferred into the result registers, Rn. If the
+ * result is greater than the maximum or less than the minimum result value, it is
+ * forced to the appropriate limit for the current mode of operation.
+ */
+/*!
+ * @name Constants and macros for entire ADC_OFS register
+ */
+/*@{*/
+#define ADC_RD_OFS(base)         (ADC_OFS_REG(base))
+#define ADC_WR_OFS(base, value)  (ADC_OFS_REG(base) = (value))
+#define ADC_RMW_OFS(base, mask, value) (ADC_WR_OFS(base, (ADC_RD_OFS(base) & ~(mask)) | (value)))
+#define ADC_SET_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) |  (value)))
+#define ADC_CLR_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) & ~(value)))
+#define ADC_TOG_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_OFS bitfields
+ */
+
+/*!
+ * @name Register ADC_OFS, field OFS[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_OFS_OFS field. */
+#define ADC_RD_OFS_OFS(base) ((ADC_OFS_REG(base) & ADC_OFS_OFS_MASK) >> ADC_OFS_OFS_SHIFT)
+#define ADC_BRD_OFS_OFS(base) (ADC_RD_OFS_OFS(base))
+
+/*! @brief Set the OFS field to a new value. */
+#define ADC_WR_OFS_OFS(base, value) (ADC_RMW_OFS(base, ADC_OFS_OFS_MASK, ADC_OFS_OFS(value)))
+#define ADC_BWR_OFS_OFS(base, value) (ADC_WR_OFS_OFS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_PG - ADC Plus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_PG - ADC Plus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Plus-Side Gain Register (PG) contains the gain error correction for the
+ * plus-side input in differential mode or the overall conversion in single-ended
+ * mode. PG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
+ * written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_PG register
+ */
+/*@{*/
+#define ADC_RD_PG(base)          (ADC_PG_REG(base))
+#define ADC_WR_PG(base, value)   (ADC_PG_REG(base) = (value))
+#define ADC_RMW_PG(base, mask, value) (ADC_WR_PG(base, (ADC_RD_PG(base) & ~(mask)) | (value)))
+#define ADC_SET_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) |  (value)))
+#define ADC_CLR_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) & ~(value)))
+#define ADC_TOG_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_PG bitfields
+ */
+
+/*!
+ * @name Register ADC_PG, field PG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_PG_PG field. */
+#define ADC_RD_PG_PG(base)   ((ADC_PG_REG(base) & ADC_PG_PG_MASK) >> ADC_PG_PG_SHIFT)
+#define ADC_BRD_PG_PG(base)  (ADC_RD_PG_PG(base))
+
+/*! @brief Set the PG field to a new value. */
+#define ADC_WR_PG_PG(base, value) (ADC_RMW_PG(base, ADC_PG_PG_MASK, ADC_PG_PG(value)))
+#define ADC_BWR_PG_PG(base, value) (ADC_WR_PG_PG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_MG - ADC Minus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_MG - ADC Minus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Minus-Side Gain Register (MG) contains the gain error correction for the
+ * minus-side input in differential mode. This register is ignored in
+ * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
+ * be written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_MG register
+ */
+/*@{*/
+#define ADC_RD_MG(base)          (ADC_MG_REG(base))
+#define ADC_WR_MG(base, value)   (ADC_MG_REG(base) = (value))
+#define ADC_RMW_MG(base, mask, value) (ADC_WR_MG(base, (ADC_RD_MG(base) & ~(mask)) | (value)))
+#define ADC_SET_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) |  (value)))
+#define ADC_CLR_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) & ~(value)))
+#define ADC_TOG_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_MG bitfields
+ */
+
+/*!
+ * @name Register ADC_MG, field MG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_MG_MG field. */
+#define ADC_RD_MG_MG(base)   ((ADC_MG_REG(base) & ADC_MG_MG_MASK) >> ADC_MG_MG_SHIFT)
+#define ADC_BRD_MG_MG(base)  (ADC_RD_MG_MG(base))
+
+/*! @brief Set the MG field to a new value. */
+#define ADC_WR_MG_MG(base, value) (ADC_RMW_MG(base, ADC_MG_MG_MASK, ADC_MG_MG(value)))
+#define ADC_BWR_MG_MG(base, value) (ADC_WR_MG_MG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
+ * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
+ * when the self-calibration sequence is done, that is, CAL is cleared. If these
+ * registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPD register
+ */
+/*@{*/
+#define ADC_RD_CLPD(base)        (ADC_CLPD_REG(base))
+#define ADC_WR_CLPD(base, value) (ADC_CLPD_REG(base) = (value))
+#define ADC_RMW_CLPD(base, mask, value) (ADC_WR_CLPD(base, (ADC_RD_CLPD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) |  (value)))
+#define ADC_CLR_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) & ~(value)))
+#define ADC_TOG_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPD, field CLPD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPD_CLPD field. */
+#define ADC_RD_CLPD_CLPD(base) ((ADC_CLPD_REG(base) & ADC_CLPD_CLPD_MASK) >> ADC_CLPD_CLPD_SHIFT)
+#define ADC_BRD_CLPD_CLPD(base) (ADC_RD_CLPD_CLPD(base))
+
+/*! @brief Set the CLPD field to a new value. */
+#define ADC_WR_CLPD_CLPD(base, value) (ADC_RMW_CLPD(base, ADC_CLPD_CLPD_MASK, ADC_CLPD_CLPD(value)))
+#define ADC_BWR_CLPD_CLPD(base, value) (ADC_WR_CLPD_CLPD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPS register
+ */
+/*@{*/
+#define ADC_RD_CLPS(base)        (ADC_CLPS_REG(base))
+#define ADC_WR_CLPS(base, value) (ADC_CLPS_REG(base) = (value))
+#define ADC_RMW_CLPS(base, mask, value) (ADC_WR_CLPS(base, (ADC_RD_CLPS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) |  (value)))
+#define ADC_CLR_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) & ~(value)))
+#define ADC_TOG_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPS, field CLPS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPS_CLPS field. */
+#define ADC_RD_CLPS_CLPS(base) ((ADC_CLPS_REG(base) & ADC_CLPS_CLPS_MASK) >> ADC_CLPS_CLPS_SHIFT)
+#define ADC_BRD_CLPS_CLPS(base) (ADC_RD_CLPS_CLPS(base))
+
+/*! @brief Set the CLPS field to a new value. */
+#define ADC_WR_CLPS_CLPS(base, value) (ADC_RMW_CLPS(base, ADC_CLPS_CLPS_MASK, ADC_CLPS_CLPS(value)))
+#define ADC_BWR_CLPS_CLPS(base, value) (ADC_WR_CLPS_CLPS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP4 register
+ */
+/*@{*/
+#define ADC_RD_CLP4(base)        (ADC_CLP4_REG(base))
+#define ADC_WR_CLP4(base, value) (ADC_CLP4_REG(base) = (value))
+#define ADC_RMW_CLP4(base, mask, value) (ADC_WR_CLP4(base, (ADC_RD_CLP4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) |  (value)))
+#define ADC_CLR_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) & ~(value)))
+#define ADC_TOG_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP4, field CLP4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP4_CLP4 field. */
+#define ADC_RD_CLP4_CLP4(base) ((ADC_CLP4_REG(base) & ADC_CLP4_CLP4_MASK) >> ADC_CLP4_CLP4_SHIFT)
+#define ADC_BRD_CLP4_CLP4(base) (ADC_RD_CLP4_CLP4(base))
+
+/*! @brief Set the CLP4 field to a new value. */
+#define ADC_WR_CLP4_CLP4(base, value) (ADC_RMW_CLP4(base, ADC_CLP4_CLP4_MASK, ADC_CLP4_CLP4(value)))
+#define ADC_BWR_CLP4_CLP4(base, value) (ADC_WR_CLP4_CLP4(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP3 register
+ */
+/*@{*/
+#define ADC_RD_CLP3(base)        (ADC_CLP3_REG(base))
+#define ADC_WR_CLP3(base, value) (ADC_CLP3_REG(base) = (value))
+#define ADC_RMW_CLP3(base, mask, value) (ADC_WR_CLP3(base, (ADC_RD_CLP3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) |  (value)))
+#define ADC_CLR_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) & ~(value)))
+#define ADC_TOG_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP3, field CLP3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP3_CLP3 field. */
+#define ADC_RD_CLP3_CLP3(base) ((ADC_CLP3_REG(base) & ADC_CLP3_CLP3_MASK) >> ADC_CLP3_CLP3_SHIFT)
+#define ADC_BRD_CLP3_CLP3(base) (ADC_RD_CLP3_CLP3(base))
+
+/*! @brief Set the CLP3 field to a new value. */
+#define ADC_WR_CLP3_CLP3(base, value) (ADC_RMW_CLP3(base, ADC_CLP3_CLP3_MASK, ADC_CLP3_CLP3(value)))
+#define ADC_BWR_CLP3_CLP3(base, value) (ADC_WR_CLP3_CLP3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP2 register
+ */
+/*@{*/
+#define ADC_RD_CLP2(base)        (ADC_CLP2_REG(base))
+#define ADC_WR_CLP2(base, value) (ADC_CLP2_REG(base) = (value))
+#define ADC_RMW_CLP2(base, mask, value) (ADC_WR_CLP2(base, (ADC_RD_CLP2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) |  (value)))
+#define ADC_CLR_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) & ~(value)))
+#define ADC_TOG_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP2, field CLP2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP2_CLP2 field. */
+#define ADC_RD_CLP2_CLP2(base) ((ADC_CLP2_REG(base) & ADC_CLP2_CLP2_MASK) >> ADC_CLP2_CLP2_SHIFT)
+#define ADC_BRD_CLP2_CLP2(base) (ADC_RD_CLP2_CLP2(base))
+
+/*! @brief Set the CLP2 field to a new value. */
+#define ADC_WR_CLP2_CLP2(base, value) (ADC_RMW_CLP2(base, ADC_CLP2_CLP2_MASK, ADC_CLP2_CLP2(value)))
+#define ADC_BWR_CLP2_CLP2(base, value) (ADC_WR_CLP2_CLP2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP1 register
+ */
+/*@{*/
+#define ADC_RD_CLP1(base)        (ADC_CLP1_REG(base))
+#define ADC_WR_CLP1(base, value) (ADC_CLP1_REG(base) = (value))
+#define ADC_RMW_CLP1(base, mask, value) (ADC_WR_CLP1(base, (ADC_RD_CLP1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) |  (value)))
+#define ADC_CLR_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) & ~(value)))
+#define ADC_TOG_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP1, field CLP1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP1_CLP1 field. */
+#define ADC_RD_CLP1_CLP1(base) ((ADC_CLP1_REG(base) & ADC_CLP1_CLP1_MASK) >> ADC_CLP1_CLP1_SHIFT)
+#define ADC_BRD_CLP1_CLP1(base) (ADC_RD_CLP1_CLP1(base))
+
+/*! @brief Set the CLP1 field to a new value. */
+#define ADC_WR_CLP1_CLP1(base, value) (ADC_RMW_CLP1(base, ADC_CLP1_CLP1_MASK, ADC_CLP1_CLP1(value)))
+#define ADC_BWR_CLP1_CLP1(base, value) (ADC_WR_CLP1_CLP1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP0 register
+ */
+/*@{*/
+#define ADC_RD_CLP0(base)        (ADC_CLP0_REG(base))
+#define ADC_WR_CLP0(base, value) (ADC_CLP0_REG(base) = (value))
+#define ADC_RMW_CLP0(base, mask, value) (ADC_WR_CLP0(base, (ADC_RD_CLP0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) |  (value)))
+#define ADC_CLR_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) & ~(value)))
+#define ADC_TOG_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP0, field CLP0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP0_CLP0 field. */
+#define ADC_RD_CLP0_CLP0(base) ((ADC_CLP0_REG(base) & ADC_CLP0_CLP0_MASK) >> ADC_CLP0_CLP0_SHIFT)
+#define ADC_BRD_CLP0_CLP0(base) (ADC_RD_CLP0_CLP0(base))
+
+/*! @brief Set the CLP0 field to a new value. */
+#define ADC_WR_CLP0_CLP0(base, value) (ADC_RMW_CLP0(base, ADC_CLP0_CLP0_MASK, ADC_CLP0_CLP0(value)))
+#define ADC_BWR_CLP0_CLP0(base, value) (ADC_WR_CLP0_CLP0(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Minus-Side General Calibration Value (CLMx) registers contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
+ * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
+ * set when the self-calibration sequence is done, that is, CAL is cleared. If
+ * these registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMD register
+ */
+/*@{*/
+#define ADC_RD_CLMD(base)        (ADC_CLMD_REG(base))
+#define ADC_WR_CLMD(base, value) (ADC_CLMD_REG(base) = (value))
+#define ADC_RMW_CLMD(base, mask, value) (ADC_WR_CLMD(base, (ADC_RD_CLMD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) |  (value)))
+#define ADC_CLR_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) & ~(value)))
+#define ADC_TOG_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMD, field CLMD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMD_CLMD field. */
+#define ADC_RD_CLMD_CLMD(base) ((ADC_CLMD_REG(base) & ADC_CLMD_CLMD_MASK) >> ADC_CLMD_CLMD_SHIFT)
+#define ADC_BRD_CLMD_CLMD(base) (ADC_RD_CLMD_CLMD(base))
+
+/*! @brief Set the CLMD field to a new value. */
+#define ADC_WR_CLMD_CLMD(base, value) (ADC_RMW_CLMD(base, ADC_CLMD_CLMD_MASK, ADC_CLMD_CLMD(value)))
+#define ADC_BWR_CLMD_CLMD(base, value) (ADC_WR_CLMD_CLMD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMS register
+ */
+/*@{*/
+#define ADC_RD_CLMS(base)        (ADC_CLMS_REG(base))
+#define ADC_WR_CLMS(base, value) (ADC_CLMS_REG(base) = (value))
+#define ADC_RMW_CLMS(base, mask, value) (ADC_WR_CLMS(base, (ADC_RD_CLMS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) |  (value)))
+#define ADC_CLR_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) & ~(value)))
+#define ADC_TOG_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMS, field CLMS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMS_CLMS field. */
+#define ADC_RD_CLMS_CLMS(base) ((ADC_CLMS_REG(base) & ADC_CLMS_CLMS_MASK) >> ADC_CLMS_CLMS_SHIFT)
+#define ADC_BRD_CLMS_CLMS(base) (ADC_RD_CLMS_CLMS(base))
+
+/*! @brief Set the CLMS field to a new value. */
+#define ADC_WR_CLMS_CLMS(base, value) (ADC_RMW_CLMS(base, ADC_CLMS_CLMS_MASK, ADC_CLMS_CLMS(value)))
+#define ADC_BWR_CLMS_CLMS(base, value) (ADC_WR_CLMS_CLMS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM4 register
+ */
+/*@{*/
+#define ADC_RD_CLM4(base)        (ADC_CLM4_REG(base))
+#define ADC_WR_CLM4(base, value) (ADC_CLM4_REG(base) = (value))
+#define ADC_RMW_CLM4(base, mask, value) (ADC_WR_CLM4(base, (ADC_RD_CLM4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) |  (value)))
+#define ADC_CLR_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) & ~(value)))
+#define ADC_TOG_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM4, field CLM4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM4_CLM4 field. */
+#define ADC_RD_CLM4_CLM4(base) ((ADC_CLM4_REG(base) & ADC_CLM4_CLM4_MASK) >> ADC_CLM4_CLM4_SHIFT)
+#define ADC_BRD_CLM4_CLM4(base) (ADC_RD_CLM4_CLM4(base))
+
+/*! @brief Set the CLM4 field to a new value. */
+#define ADC_WR_CLM4_CLM4(base, value) (ADC_RMW_CLM4(base, ADC_CLM4_CLM4_MASK, ADC_CLM4_CLM4(value)))
+#define ADC_BWR_CLM4_CLM4(base, value) (ADC_WR_CLM4_CLM4(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM3 register
+ */
+/*@{*/
+#define ADC_RD_CLM3(base)        (ADC_CLM3_REG(base))
+#define ADC_WR_CLM3(base, value) (ADC_CLM3_REG(base) = (value))
+#define ADC_RMW_CLM3(base, mask, value) (ADC_WR_CLM3(base, (ADC_RD_CLM3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) |  (value)))
+#define ADC_CLR_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) & ~(value)))
+#define ADC_TOG_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM3, field CLM3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM3_CLM3 field. */
+#define ADC_RD_CLM3_CLM3(base) ((ADC_CLM3_REG(base) & ADC_CLM3_CLM3_MASK) >> ADC_CLM3_CLM3_SHIFT)
+#define ADC_BRD_CLM3_CLM3(base) (ADC_RD_CLM3_CLM3(base))
+
+/*! @brief Set the CLM3 field to a new value. */
+#define ADC_WR_CLM3_CLM3(base, value) (ADC_RMW_CLM3(base, ADC_CLM3_CLM3_MASK, ADC_CLM3_CLM3(value)))
+#define ADC_BWR_CLM3_CLM3(base, value) (ADC_WR_CLM3_CLM3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM2 register
+ */
+/*@{*/
+#define ADC_RD_CLM2(base)        (ADC_CLM2_REG(base))
+#define ADC_WR_CLM2(base, value) (ADC_CLM2_REG(base) = (value))
+#define ADC_RMW_CLM2(base, mask, value) (ADC_WR_CLM2(base, (ADC_RD_CLM2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) |  (value)))
+#define ADC_CLR_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) & ~(value)))
+#define ADC_TOG_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM2, field CLM2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM2_CLM2 field. */
+#define ADC_RD_CLM2_CLM2(base) ((ADC_CLM2_REG(base) & ADC_CLM2_CLM2_MASK) >> ADC_CLM2_CLM2_SHIFT)
+#define ADC_BRD_CLM2_CLM2(base) (ADC_RD_CLM2_CLM2(base))
+
+/*! @brief Set the CLM2 field to a new value. */
+#define ADC_WR_CLM2_CLM2(base, value) (ADC_RMW_CLM2(base, ADC_CLM2_CLM2_MASK, ADC_CLM2_CLM2(value)))
+#define ADC_BWR_CLM2_CLM2(base, value) (ADC_WR_CLM2_CLM2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM1 register
+ */
+/*@{*/
+#define ADC_RD_CLM1(base)        (ADC_CLM1_REG(base))
+#define ADC_WR_CLM1(base, value) (ADC_CLM1_REG(base) = (value))
+#define ADC_RMW_CLM1(base, mask, value) (ADC_WR_CLM1(base, (ADC_RD_CLM1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) |  (value)))
+#define ADC_CLR_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) & ~(value)))
+#define ADC_TOG_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM1, field CLM1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM1_CLM1 field. */
+#define ADC_RD_CLM1_CLM1(base) ((ADC_CLM1_REG(base) & ADC_CLM1_CLM1_MASK) >> ADC_CLM1_CLM1_SHIFT)
+#define ADC_BRD_CLM1_CLM1(base) (ADC_RD_CLM1_CLM1(base))
+
+/*! @brief Set the CLM1 field to a new value. */
+#define ADC_WR_CLM1_CLM1(base, value) (ADC_RMW_CLM1(base, ADC_CLM1_CLM1_MASK, ADC_CLM1_CLM1(value)))
+#define ADC_BWR_CLM1_CLM1(base, value) (ADC_WR_CLM1_CLM1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM0 register
+ */
+/*@{*/
+#define ADC_RD_CLM0(base)        (ADC_CLM0_REG(base))
+#define ADC_WR_CLM0(base, value) (ADC_CLM0_REG(base) = (value))
+#define ADC_RMW_CLM0(base, mask, value) (ADC_WR_CLM0(base, (ADC_RD_CLM0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) |  (value)))
+#define ADC_CLR_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) & ~(value)))
+#define ADC_TOG_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM0, field CLM0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM0_CLM0 field. */
+#define ADC_RD_CLM0_CLM0(base) ((ADC_CLM0_REG(base) & ADC_CLM0_CLM0_MASK) >> ADC_CLM0_CLM0_SHIFT)
+#define ADC_BRD_CLM0_CLM0(base) (ADC_RD_CLM0_CLM0(base))
+
+/*! @brief Set the CLM0 field to a new value. */
+#define ADC_WR_CLM0_CLM0(base, value) (ADC_RMW_CLM0(base, ADC_CLM0_CLM0_MASK, ADC_CLM0_CLM0(value)))
+#define ADC_BWR_CLM0_CLM0(base, value) (ADC_WR_CLM0_CLM0(base, value))
+/*@}*/
+
+/*
+ * MK64F12 AIPS
+ *
+ * AIPS-Lite Bridge
+ *
+ * Registers defined in this header file:
+ * - AIPS_MPRA - Master Privilege Register A
+ * - AIPS_PACRA - Peripheral Access Control Register
+ * - AIPS_PACRB - Peripheral Access Control Register
+ * - AIPS_PACRC - Peripheral Access Control Register
+ * - AIPS_PACRD - Peripheral Access Control Register
+ * - AIPS_PACRE - Peripheral Access Control Register
+ * - AIPS_PACRF - Peripheral Access Control Register
+ * - AIPS_PACRG - Peripheral Access Control Register
+ * - AIPS_PACRH - Peripheral Access Control Register
+ * - AIPS_PACRI - Peripheral Access Control Register
+ * - AIPS_PACRJ - Peripheral Access Control Register
+ * - AIPS_PACRK - Peripheral Access Control Register
+ * - AIPS_PACRL - Peripheral Access Control Register
+ * - AIPS_PACRM - Peripheral Access Control Register
+ * - AIPS_PACRN - Peripheral Access Control Register
+ * - AIPS_PACRO - Peripheral Access Control Register
+ * - AIPS_PACRP - Peripheral Access Control Register
+ * - AIPS_PACRU - Peripheral Access Control Register
+ */
+
+#define AIPS_INSTANCE_COUNT (2U) /*!< Number of instances of the AIPS module. */
+#define AIPS0_IDX (0U) /*!< Instance number for AIPS0. */
+#define AIPS1_IDX (1U) /*!< Instance number for AIPS1. */
+
+/*******************************************************************************
+ * AIPS_MPRA - Master Privilege Register A
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_MPRA - Master Privilege Register A (RW)
+ *
+ * Reset value: 0x77700000U
+ *
+ * The MPRA specifies identical 4-bit fields defining the access-privilege level
+ * associated with a bus master to various peripherals on the chip. The register
+ * provides one field per bus master. At reset, the default value loaded into
+ * the MPRA fields is chip-specific. See the chip configuration details for the
+ * value of a particular device. A register field that maps to an unimplemented
+ * master or peripheral behaves as read-only-zero. Each master is assigned a logical
+ * ID from 0 to 15. See the master logical ID assignment table in the
+ * chip-specific AIPS information.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_MPRA register
+ */
+/*@{*/
+#define AIPS_RD_MPRA(base)       (AIPS_MPRA_REG(base))
+#define AIPS_WR_MPRA(base, value) (AIPS_MPRA_REG(base) = (value))
+#define AIPS_RMW_MPRA(base, mask, value) (AIPS_WR_MPRA(base, (AIPS_RD_MPRA(base) & ~(mask)) | (value)))
+#define AIPS_SET_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) |  (value)))
+#define AIPS_CLR_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) & ~(value)))
+#define AIPS_TOG_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_MPRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_MPRA, field MPL5[8] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL5 field. */
+#define AIPS_RD_MPRA_MPL5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL5_MASK) >> AIPS_MPRA_MPL5_SHIFT)
+#define AIPS_BRD_MPRA_MPL5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL5_SHIFT))
+
+/*! @brief Set the MPL5 field to a new value. */
+#define AIPS_WR_MPRA_MPL5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL5_MASK, AIPS_MPRA_MPL5(value)))
+#define AIPS_BWR_MPRA_MPL5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW5[9] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW5 field. */
+#define AIPS_RD_MPRA_MTW5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW5_MASK) >> AIPS_MPRA_MTW5_SHIFT)
+#define AIPS_BRD_MPRA_MTW5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW5_SHIFT))
+
+/*! @brief Set the MTW5 field to a new value. */
+#define AIPS_WR_MPRA_MTW5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW5_MASK, AIPS_MPRA_MTW5(value)))
+#define AIPS_BWR_MPRA_MTW5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR5[10] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR5 field. */
+#define AIPS_RD_MPRA_MTR5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR5_MASK) >> AIPS_MPRA_MTR5_SHIFT)
+#define AIPS_BRD_MPRA_MTR5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR5_SHIFT))
+
+/*! @brief Set the MTR5 field to a new value. */
+#define AIPS_WR_MPRA_MTR5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR5_MASK, AIPS_MPRA_MTR5(value)))
+#define AIPS_BWR_MPRA_MTR5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL4[12] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL4 field. */
+#define AIPS_RD_MPRA_MPL4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL4_MASK) >> AIPS_MPRA_MPL4_SHIFT)
+#define AIPS_BRD_MPRA_MPL4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL4_SHIFT))
+
+/*! @brief Set the MPL4 field to a new value. */
+#define AIPS_WR_MPRA_MPL4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL4_MASK, AIPS_MPRA_MPL4(value)))
+#define AIPS_BWR_MPRA_MPL4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW4[13] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW4 field. */
+#define AIPS_RD_MPRA_MTW4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW4_MASK) >> AIPS_MPRA_MTW4_SHIFT)
+#define AIPS_BRD_MPRA_MTW4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW4_SHIFT))
+
+/*! @brief Set the MTW4 field to a new value. */
+#define AIPS_WR_MPRA_MTW4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW4_MASK, AIPS_MPRA_MTW4(value)))
+#define AIPS_BWR_MPRA_MTW4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR4[14] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR4 field. */
+#define AIPS_RD_MPRA_MTR4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR4_MASK) >> AIPS_MPRA_MTR4_SHIFT)
+#define AIPS_BRD_MPRA_MTR4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR4_SHIFT))
+
+/*! @brief Set the MTR4 field to a new value. */
+#define AIPS_WR_MPRA_MTR4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR4_MASK, AIPS_MPRA_MTR4(value)))
+#define AIPS_BWR_MPRA_MTR4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL3[16] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL3 field. */
+#define AIPS_RD_MPRA_MPL3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL3_MASK) >> AIPS_MPRA_MPL3_SHIFT)
+#define AIPS_BRD_MPRA_MPL3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL3_SHIFT))
+
+/*! @brief Set the MPL3 field to a new value. */
+#define AIPS_WR_MPRA_MPL3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL3_MASK, AIPS_MPRA_MPL3(value)))
+#define AIPS_BWR_MPRA_MPL3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW3[17] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW3 field. */
+#define AIPS_RD_MPRA_MTW3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW3_MASK) >> AIPS_MPRA_MTW3_SHIFT)
+#define AIPS_BRD_MPRA_MTW3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW3_SHIFT))
+
+/*! @brief Set the MTW3 field to a new value. */
+#define AIPS_WR_MPRA_MTW3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW3_MASK, AIPS_MPRA_MTW3(value)))
+#define AIPS_BWR_MPRA_MTW3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR3[18] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR3 field. */
+#define AIPS_RD_MPRA_MTR3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR3_MASK) >> AIPS_MPRA_MTR3_SHIFT)
+#define AIPS_BRD_MPRA_MTR3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR3_SHIFT))
+
+/*! @brief Set the MTR3 field to a new value. */
+#define AIPS_WR_MPRA_MTR3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR3_MASK, AIPS_MPRA_MTR3(value)))
+#define AIPS_BWR_MPRA_MTR3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL2[20] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL2 field. */
+#define AIPS_RD_MPRA_MPL2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL2_MASK) >> AIPS_MPRA_MPL2_SHIFT)
+#define AIPS_BRD_MPRA_MPL2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL2_SHIFT))
+
+/*! @brief Set the MPL2 field to a new value. */
+#define AIPS_WR_MPRA_MPL2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL2_MASK, AIPS_MPRA_MPL2(value)))
+#define AIPS_BWR_MPRA_MPL2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW2[21] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW2 field. */
+#define AIPS_RD_MPRA_MTW2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW2_MASK) >> AIPS_MPRA_MTW2_SHIFT)
+#define AIPS_BRD_MPRA_MTW2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW2_SHIFT))
+
+/*! @brief Set the MTW2 field to a new value. */
+#define AIPS_WR_MPRA_MTW2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW2_MASK, AIPS_MPRA_MTW2(value)))
+#define AIPS_BWR_MPRA_MTW2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR2[22] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR2 field. */
+#define AIPS_RD_MPRA_MTR2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR2_MASK) >> AIPS_MPRA_MTR2_SHIFT)
+#define AIPS_BRD_MPRA_MTR2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR2_SHIFT))
+
+/*! @brief Set the MTR2 field to a new value. */
+#define AIPS_WR_MPRA_MTR2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR2_MASK, AIPS_MPRA_MTR2(value)))
+#define AIPS_BWR_MPRA_MTR2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL1[24] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL1 field. */
+#define AIPS_RD_MPRA_MPL1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL1_MASK) >> AIPS_MPRA_MPL1_SHIFT)
+#define AIPS_BRD_MPRA_MPL1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL1_SHIFT))
+
+/*! @brief Set the MPL1 field to a new value. */
+#define AIPS_WR_MPRA_MPL1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL1_MASK, AIPS_MPRA_MPL1(value)))
+#define AIPS_BWR_MPRA_MPL1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW1[25] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW1 field. */
+#define AIPS_RD_MPRA_MTW1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW1_MASK) >> AIPS_MPRA_MTW1_SHIFT)
+#define AIPS_BRD_MPRA_MTW1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW1_SHIFT))
+
+/*! @brief Set the MTW1 field to a new value. */
+#define AIPS_WR_MPRA_MTW1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW1_MASK, AIPS_MPRA_MTW1(value)))
+#define AIPS_BWR_MPRA_MTW1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR1[26] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR1 field. */
+#define AIPS_RD_MPRA_MTR1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR1_MASK) >> AIPS_MPRA_MTR1_SHIFT)
+#define AIPS_BRD_MPRA_MTR1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR1_SHIFT))
+
+/*! @brief Set the MTR1 field to a new value. */
+#define AIPS_WR_MPRA_MTR1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR1_MASK, AIPS_MPRA_MTR1(value)))
+#define AIPS_BWR_MPRA_MTR1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL0[28] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL0 field. */
+#define AIPS_RD_MPRA_MPL0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL0_MASK) >> AIPS_MPRA_MPL0_SHIFT)
+#define AIPS_BRD_MPRA_MPL0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL0_SHIFT))
+
+/*! @brief Set the MPL0 field to a new value. */
+#define AIPS_WR_MPRA_MPL0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL0_MASK, AIPS_MPRA_MPL0(value)))
+#define AIPS_BWR_MPRA_MPL0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW0[29] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW0 field. */
+#define AIPS_RD_MPRA_MTW0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW0_MASK) >> AIPS_MPRA_MTW0_SHIFT)
+#define AIPS_BRD_MPRA_MTW0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW0_SHIFT))
+
+/*! @brief Set the MTW0 field to a new value. */
+#define AIPS_WR_MPRA_MTW0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW0_MASK, AIPS_MPRA_MTW0(value)))
+#define AIPS_BWR_MPRA_MTW0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR0[30] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR0 field. */
+#define AIPS_RD_MPRA_MTR0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR0_MASK) >> AIPS_MPRA_MTR0_SHIFT)
+#define AIPS_BRD_MPRA_MTR0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR0_SHIFT))
+
+/*! @brief Set the MTR0 field to a new value. */
+#define AIPS_WR_MPRA_MTR0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR0_MASK, AIPS_MPRA_MTR0(value)))
+#define AIPS_BWR_MPRA_MTR0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRA - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRA - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x50004000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRA register
+ */
+/*@{*/
+#define AIPS_RD_PACRA(base)      (AIPS_PACRA_REG(base))
+#define AIPS_WR_PACRA(base, value) (AIPS_PACRA_REG(base) = (value))
+#define AIPS_RMW_PACRA(base, mask, value) (AIPS_WR_PACRA(base, (AIPS_RD_PACRA(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) |  (value)))
+#define AIPS_CLR_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) & ~(value)))
+#define AIPS_TOG_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRA, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP7 field. */
+#define AIPS_RD_PACRA_TP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP7_MASK) >> AIPS_PACRA_TP7_SHIFT)
+#define AIPS_BRD_PACRA_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRA_TP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP7_MASK, AIPS_PACRA_TP7(value)))
+#define AIPS_BWR_PACRA_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP7 field. */
+#define AIPS_RD_PACRA_WP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP7_MASK) >> AIPS_PACRA_WP7_SHIFT)
+#define AIPS_BRD_PACRA_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRA_WP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP7_MASK, AIPS_PACRA_WP7(value)))
+#define AIPS_BWR_PACRA_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP7 field. */
+#define AIPS_RD_PACRA_SP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP7_MASK) >> AIPS_PACRA_SP7_SHIFT)
+#define AIPS_BRD_PACRA_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRA_SP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP7_MASK, AIPS_PACRA_SP7(value)))
+#define AIPS_BWR_PACRA_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP6 field. */
+#define AIPS_RD_PACRA_TP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP6_MASK) >> AIPS_PACRA_TP6_SHIFT)
+#define AIPS_BRD_PACRA_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRA_TP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP6_MASK, AIPS_PACRA_TP6(value)))
+#define AIPS_BWR_PACRA_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP6 field. */
+#define AIPS_RD_PACRA_WP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP6_MASK) >> AIPS_PACRA_WP6_SHIFT)
+#define AIPS_BRD_PACRA_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRA_WP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP6_MASK, AIPS_PACRA_WP6(value)))
+#define AIPS_BWR_PACRA_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP6 field. */
+#define AIPS_RD_PACRA_SP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP6_MASK) >> AIPS_PACRA_SP6_SHIFT)
+#define AIPS_BRD_PACRA_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRA_SP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP6_MASK, AIPS_PACRA_SP6(value)))
+#define AIPS_BWR_PACRA_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP5 field. */
+#define AIPS_RD_PACRA_TP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP5_MASK) >> AIPS_PACRA_TP5_SHIFT)
+#define AIPS_BRD_PACRA_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRA_TP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP5_MASK, AIPS_PACRA_TP5(value)))
+#define AIPS_BWR_PACRA_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP5 field. */
+#define AIPS_RD_PACRA_WP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP5_MASK) >> AIPS_PACRA_WP5_SHIFT)
+#define AIPS_BRD_PACRA_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRA_WP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP5_MASK, AIPS_PACRA_WP5(value)))
+#define AIPS_BWR_PACRA_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP5 field. */
+#define AIPS_RD_PACRA_SP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP5_MASK) >> AIPS_PACRA_SP5_SHIFT)
+#define AIPS_BRD_PACRA_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRA_SP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP5_MASK, AIPS_PACRA_SP5(value)))
+#define AIPS_BWR_PACRA_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP4 field. */
+#define AIPS_RD_PACRA_TP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP4_MASK) >> AIPS_PACRA_TP4_SHIFT)
+#define AIPS_BRD_PACRA_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRA_TP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP4_MASK, AIPS_PACRA_TP4(value)))
+#define AIPS_BWR_PACRA_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP4 field. */
+#define AIPS_RD_PACRA_WP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP4_MASK) >> AIPS_PACRA_WP4_SHIFT)
+#define AIPS_BRD_PACRA_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRA_WP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP4_MASK, AIPS_PACRA_WP4(value)))
+#define AIPS_BWR_PACRA_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP4 field. */
+#define AIPS_RD_PACRA_SP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP4_MASK) >> AIPS_PACRA_SP4_SHIFT)
+#define AIPS_BRD_PACRA_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRA_SP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP4_MASK, AIPS_PACRA_SP4(value)))
+#define AIPS_BWR_PACRA_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP3 field. */
+#define AIPS_RD_PACRA_TP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP3_MASK) >> AIPS_PACRA_TP3_SHIFT)
+#define AIPS_BRD_PACRA_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRA_TP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP3_MASK, AIPS_PACRA_TP3(value)))
+#define AIPS_BWR_PACRA_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP3 field. */
+#define AIPS_RD_PACRA_WP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP3_MASK) >> AIPS_PACRA_WP3_SHIFT)
+#define AIPS_BRD_PACRA_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRA_WP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP3_MASK, AIPS_PACRA_WP3(value)))
+#define AIPS_BWR_PACRA_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP3 field. */
+#define AIPS_RD_PACRA_SP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP3_MASK) >> AIPS_PACRA_SP3_SHIFT)
+#define AIPS_BRD_PACRA_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRA_SP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP3_MASK, AIPS_PACRA_SP3(value)))
+#define AIPS_BWR_PACRA_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP2 field. */
+#define AIPS_RD_PACRA_TP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP2_MASK) >> AIPS_PACRA_TP2_SHIFT)
+#define AIPS_BRD_PACRA_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRA_TP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP2_MASK, AIPS_PACRA_TP2(value)))
+#define AIPS_BWR_PACRA_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP2 field. */
+#define AIPS_RD_PACRA_WP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP2_MASK) >> AIPS_PACRA_WP2_SHIFT)
+#define AIPS_BRD_PACRA_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRA_WP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP2_MASK, AIPS_PACRA_WP2(value)))
+#define AIPS_BWR_PACRA_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP2 field. */
+#define AIPS_RD_PACRA_SP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP2_MASK) >> AIPS_PACRA_SP2_SHIFT)
+#define AIPS_BRD_PACRA_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRA_SP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP2_MASK, AIPS_PACRA_SP2(value)))
+#define AIPS_BWR_PACRA_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP1 field. */
+#define AIPS_RD_PACRA_TP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP1_MASK) >> AIPS_PACRA_TP1_SHIFT)
+#define AIPS_BRD_PACRA_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRA_TP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP1_MASK, AIPS_PACRA_TP1(value)))
+#define AIPS_BWR_PACRA_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP1 field. */
+#define AIPS_RD_PACRA_WP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP1_MASK) >> AIPS_PACRA_WP1_SHIFT)
+#define AIPS_BRD_PACRA_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRA_WP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP1_MASK, AIPS_PACRA_WP1(value)))
+#define AIPS_BWR_PACRA_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP1 field. */
+#define AIPS_RD_PACRA_SP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP1_MASK) >> AIPS_PACRA_SP1_SHIFT)
+#define AIPS_BRD_PACRA_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRA_SP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP1_MASK, AIPS_PACRA_SP1(value)))
+#define AIPS_BWR_PACRA_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP0 field. */
+#define AIPS_RD_PACRA_TP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP0_MASK) >> AIPS_PACRA_TP0_SHIFT)
+#define AIPS_BRD_PACRA_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRA_TP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP0_MASK, AIPS_PACRA_TP0(value)))
+#define AIPS_BWR_PACRA_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP0 field. */
+#define AIPS_RD_PACRA_WP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP0_MASK) >> AIPS_PACRA_WP0_SHIFT)
+#define AIPS_BRD_PACRA_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRA_WP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP0_MASK, AIPS_PACRA_WP0(value)))
+#define AIPS_BWR_PACRA_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP0 field. */
+#define AIPS_RD_PACRA_SP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP0_MASK) >> AIPS_PACRA_SP0_SHIFT)
+#define AIPS_BRD_PACRA_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRA_SP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP0_MASK, AIPS_PACRA_SP0(value)))
+#define AIPS_BWR_PACRA_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRB - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRB - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44004400U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRB register
+ */
+/*@{*/
+#define AIPS_RD_PACRB(base)      (AIPS_PACRB_REG(base))
+#define AIPS_WR_PACRB(base, value) (AIPS_PACRB_REG(base) = (value))
+#define AIPS_RMW_PACRB(base, mask, value) (AIPS_WR_PACRB(base, (AIPS_RD_PACRB(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) |  (value)))
+#define AIPS_CLR_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) & ~(value)))
+#define AIPS_TOG_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRB bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRB, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP7 field. */
+#define AIPS_RD_PACRB_TP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP7_MASK) >> AIPS_PACRB_TP7_SHIFT)
+#define AIPS_BRD_PACRB_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRB_TP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP7_MASK, AIPS_PACRB_TP7(value)))
+#define AIPS_BWR_PACRB_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP7 field. */
+#define AIPS_RD_PACRB_WP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP7_MASK) >> AIPS_PACRB_WP7_SHIFT)
+#define AIPS_BRD_PACRB_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRB_WP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP7_MASK, AIPS_PACRB_WP7(value)))
+#define AIPS_BWR_PACRB_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP7 field. */
+#define AIPS_RD_PACRB_SP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP7_MASK) >> AIPS_PACRB_SP7_SHIFT)
+#define AIPS_BRD_PACRB_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRB_SP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP7_MASK, AIPS_PACRB_SP7(value)))
+#define AIPS_BWR_PACRB_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP6 field. */
+#define AIPS_RD_PACRB_TP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP6_MASK) >> AIPS_PACRB_TP6_SHIFT)
+#define AIPS_BRD_PACRB_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRB_TP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP6_MASK, AIPS_PACRB_TP6(value)))
+#define AIPS_BWR_PACRB_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP6 field. */
+#define AIPS_RD_PACRB_WP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP6_MASK) >> AIPS_PACRB_WP6_SHIFT)
+#define AIPS_BRD_PACRB_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRB_WP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP6_MASK, AIPS_PACRB_WP6(value)))
+#define AIPS_BWR_PACRB_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP6 field. */
+#define AIPS_RD_PACRB_SP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP6_MASK) >> AIPS_PACRB_SP6_SHIFT)
+#define AIPS_BRD_PACRB_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRB_SP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP6_MASK, AIPS_PACRB_SP6(value)))
+#define AIPS_BWR_PACRB_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP5 field. */
+#define AIPS_RD_PACRB_TP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP5_MASK) >> AIPS_PACRB_TP5_SHIFT)
+#define AIPS_BRD_PACRB_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRB_TP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP5_MASK, AIPS_PACRB_TP5(value)))
+#define AIPS_BWR_PACRB_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP5 field. */
+#define AIPS_RD_PACRB_WP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP5_MASK) >> AIPS_PACRB_WP5_SHIFT)
+#define AIPS_BRD_PACRB_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRB_WP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP5_MASK, AIPS_PACRB_WP5(value)))
+#define AIPS_BWR_PACRB_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP5 field. */
+#define AIPS_RD_PACRB_SP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP5_MASK) >> AIPS_PACRB_SP5_SHIFT)
+#define AIPS_BRD_PACRB_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRB_SP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP5_MASK, AIPS_PACRB_SP5(value)))
+#define AIPS_BWR_PACRB_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP4 field. */
+#define AIPS_RD_PACRB_TP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP4_MASK) >> AIPS_PACRB_TP4_SHIFT)
+#define AIPS_BRD_PACRB_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRB_TP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP4_MASK, AIPS_PACRB_TP4(value)))
+#define AIPS_BWR_PACRB_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP4 field. */
+#define AIPS_RD_PACRB_WP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP4_MASK) >> AIPS_PACRB_WP4_SHIFT)
+#define AIPS_BRD_PACRB_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRB_WP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP4_MASK, AIPS_PACRB_WP4(value)))
+#define AIPS_BWR_PACRB_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP4 field. */
+#define AIPS_RD_PACRB_SP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP4_MASK) >> AIPS_PACRB_SP4_SHIFT)
+#define AIPS_BRD_PACRB_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRB_SP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP4_MASK, AIPS_PACRB_SP4(value)))
+#define AIPS_BWR_PACRB_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP3 field. */
+#define AIPS_RD_PACRB_TP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP3_MASK) >> AIPS_PACRB_TP3_SHIFT)
+#define AIPS_BRD_PACRB_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRB_TP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP3_MASK, AIPS_PACRB_TP3(value)))
+#define AIPS_BWR_PACRB_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP3 field. */
+#define AIPS_RD_PACRB_WP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP3_MASK) >> AIPS_PACRB_WP3_SHIFT)
+#define AIPS_BRD_PACRB_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRB_WP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP3_MASK, AIPS_PACRB_WP3(value)))
+#define AIPS_BWR_PACRB_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP3 field. */
+#define AIPS_RD_PACRB_SP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP3_MASK) >> AIPS_PACRB_SP3_SHIFT)
+#define AIPS_BRD_PACRB_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRB_SP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP3_MASK, AIPS_PACRB_SP3(value)))
+#define AIPS_BWR_PACRB_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP2 field. */
+#define AIPS_RD_PACRB_TP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP2_MASK) >> AIPS_PACRB_TP2_SHIFT)
+#define AIPS_BRD_PACRB_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRB_TP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP2_MASK, AIPS_PACRB_TP2(value)))
+#define AIPS_BWR_PACRB_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP2 field. */
+#define AIPS_RD_PACRB_WP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP2_MASK) >> AIPS_PACRB_WP2_SHIFT)
+#define AIPS_BRD_PACRB_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRB_WP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP2_MASK, AIPS_PACRB_WP2(value)))
+#define AIPS_BWR_PACRB_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP2 field. */
+#define AIPS_RD_PACRB_SP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP2_MASK) >> AIPS_PACRB_SP2_SHIFT)
+#define AIPS_BRD_PACRB_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRB_SP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP2_MASK, AIPS_PACRB_SP2(value)))
+#define AIPS_BWR_PACRB_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP1 field. */
+#define AIPS_RD_PACRB_TP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP1_MASK) >> AIPS_PACRB_TP1_SHIFT)
+#define AIPS_BRD_PACRB_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRB_TP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP1_MASK, AIPS_PACRB_TP1(value)))
+#define AIPS_BWR_PACRB_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP1 field. */
+#define AIPS_RD_PACRB_WP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP1_MASK) >> AIPS_PACRB_WP1_SHIFT)
+#define AIPS_BRD_PACRB_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRB_WP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP1_MASK, AIPS_PACRB_WP1(value)))
+#define AIPS_BWR_PACRB_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP1 field. */
+#define AIPS_RD_PACRB_SP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP1_MASK) >> AIPS_PACRB_SP1_SHIFT)
+#define AIPS_BRD_PACRB_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRB_SP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP1_MASK, AIPS_PACRB_SP1(value)))
+#define AIPS_BWR_PACRB_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP0 field. */
+#define AIPS_RD_PACRB_TP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP0_MASK) >> AIPS_PACRB_TP0_SHIFT)
+#define AIPS_BRD_PACRB_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRB_TP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP0_MASK, AIPS_PACRB_TP0(value)))
+#define AIPS_BWR_PACRB_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP0 field. */
+#define AIPS_RD_PACRB_WP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP0_MASK) >> AIPS_PACRB_WP0_SHIFT)
+#define AIPS_BRD_PACRB_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRB_WP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP0_MASK, AIPS_PACRB_WP0(value)))
+#define AIPS_BWR_PACRB_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP0 field. */
+#define AIPS_RD_PACRB_SP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP0_MASK) >> AIPS_PACRB_SP0_SHIFT)
+#define AIPS_BRD_PACRB_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRB_SP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP0_MASK, AIPS_PACRB_SP0(value)))
+#define AIPS_BWR_PACRB_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRC - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRC - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRC register
+ */
+/*@{*/
+#define AIPS_RD_PACRC(base)      (AIPS_PACRC_REG(base))
+#define AIPS_WR_PACRC(base, value) (AIPS_PACRC_REG(base) = (value))
+#define AIPS_RMW_PACRC(base, mask, value) (AIPS_WR_PACRC(base, (AIPS_RD_PACRC(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) |  (value)))
+#define AIPS_CLR_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) & ~(value)))
+#define AIPS_TOG_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRC bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRC, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP7 field. */
+#define AIPS_RD_PACRC_TP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP7_MASK) >> AIPS_PACRC_TP7_SHIFT)
+#define AIPS_BRD_PACRC_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRC_TP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP7_MASK, AIPS_PACRC_TP7(value)))
+#define AIPS_BWR_PACRC_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP7 field. */
+#define AIPS_RD_PACRC_WP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP7_MASK) >> AIPS_PACRC_WP7_SHIFT)
+#define AIPS_BRD_PACRC_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRC_WP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP7_MASK, AIPS_PACRC_WP7(value)))
+#define AIPS_BWR_PACRC_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP7 field. */
+#define AIPS_RD_PACRC_SP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP7_MASK) >> AIPS_PACRC_SP7_SHIFT)
+#define AIPS_BRD_PACRC_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRC_SP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP7_MASK, AIPS_PACRC_SP7(value)))
+#define AIPS_BWR_PACRC_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP6 field. */
+#define AIPS_RD_PACRC_TP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP6_MASK) >> AIPS_PACRC_TP6_SHIFT)
+#define AIPS_BRD_PACRC_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRC_TP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP6_MASK, AIPS_PACRC_TP6(value)))
+#define AIPS_BWR_PACRC_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP6 field. */
+#define AIPS_RD_PACRC_WP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP6_MASK) >> AIPS_PACRC_WP6_SHIFT)
+#define AIPS_BRD_PACRC_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRC_WP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP6_MASK, AIPS_PACRC_WP6(value)))
+#define AIPS_BWR_PACRC_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP6 field. */
+#define AIPS_RD_PACRC_SP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP6_MASK) >> AIPS_PACRC_SP6_SHIFT)
+#define AIPS_BRD_PACRC_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRC_SP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP6_MASK, AIPS_PACRC_SP6(value)))
+#define AIPS_BWR_PACRC_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP5 field. */
+#define AIPS_RD_PACRC_TP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP5_MASK) >> AIPS_PACRC_TP5_SHIFT)
+#define AIPS_BRD_PACRC_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRC_TP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP5_MASK, AIPS_PACRC_TP5(value)))
+#define AIPS_BWR_PACRC_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP5 field. */
+#define AIPS_RD_PACRC_WP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP5_MASK) >> AIPS_PACRC_WP5_SHIFT)
+#define AIPS_BRD_PACRC_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRC_WP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP5_MASK, AIPS_PACRC_WP5(value)))
+#define AIPS_BWR_PACRC_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP5 field. */
+#define AIPS_RD_PACRC_SP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP5_MASK) >> AIPS_PACRC_SP5_SHIFT)
+#define AIPS_BRD_PACRC_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRC_SP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP5_MASK, AIPS_PACRC_SP5(value)))
+#define AIPS_BWR_PACRC_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP4 field. */
+#define AIPS_RD_PACRC_TP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP4_MASK) >> AIPS_PACRC_TP4_SHIFT)
+#define AIPS_BRD_PACRC_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRC_TP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP4_MASK, AIPS_PACRC_TP4(value)))
+#define AIPS_BWR_PACRC_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP4 field. */
+#define AIPS_RD_PACRC_WP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP4_MASK) >> AIPS_PACRC_WP4_SHIFT)
+#define AIPS_BRD_PACRC_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRC_WP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP4_MASK, AIPS_PACRC_WP4(value)))
+#define AIPS_BWR_PACRC_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP4 field. */
+#define AIPS_RD_PACRC_SP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP4_MASK) >> AIPS_PACRC_SP4_SHIFT)
+#define AIPS_BRD_PACRC_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRC_SP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP4_MASK, AIPS_PACRC_SP4(value)))
+#define AIPS_BWR_PACRC_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP3 field. */
+#define AIPS_RD_PACRC_TP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP3_MASK) >> AIPS_PACRC_TP3_SHIFT)
+#define AIPS_BRD_PACRC_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRC_TP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP3_MASK, AIPS_PACRC_TP3(value)))
+#define AIPS_BWR_PACRC_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP3 field. */
+#define AIPS_RD_PACRC_WP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP3_MASK) >> AIPS_PACRC_WP3_SHIFT)
+#define AIPS_BRD_PACRC_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRC_WP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP3_MASK, AIPS_PACRC_WP3(value)))
+#define AIPS_BWR_PACRC_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP3 field. */
+#define AIPS_RD_PACRC_SP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP3_MASK) >> AIPS_PACRC_SP3_SHIFT)
+#define AIPS_BRD_PACRC_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRC_SP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP3_MASK, AIPS_PACRC_SP3(value)))
+#define AIPS_BWR_PACRC_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP2 field. */
+#define AIPS_RD_PACRC_TP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP2_MASK) >> AIPS_PACRC_TP2_SHIFT)
+#define AIPS_BRD_PACRC_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRC_TP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP2_MASK, AIPS_PACRC_TP2(value)))
+#define AIPS_BWR_PACRC_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP2 field. */
+#define AIPS_RD_PACRC_WP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP2_MASK) >> AIPS_PACRC_WP2_SHIFT)
+#define AIPS_BRD_PACRC_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRC_WP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP2_MASK, AIPS_PACRC_WP2(value)))
+#define AIPS_BWR_PACRC_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP2 field. */
+#define AIPS_RD_PACRC_SP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP2_MASK) >> AIPS_PACRC_SP2_SHIFT)
+#define AIPS_BRD_PACRC_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRC_SP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP2_MASK, AIPS_PACRC_SP2(value)))
+#define AIPS_BWR_PACRC_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP1 field. */
+#define AIPS_RD_PACRC_TP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP1_MASK) >> AIPS_PACRC_TP1_SHIFT)
+#define AIPS_BRD_PACRC_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRC_TP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP1_MASK, AIPS_PACRC_TP1(value)))
+#define AIPS_BWR_PACRC_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP1 field. */
+#define AIPS_RD_PACRC_WP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP1_MASK) >> AIPS_PACRC_WP1_SHIFT)
+#define AIPS_BRD_PACRC_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRC_WP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP1_MASK, AIPS_PACRC_WP1(value)))
+#define AIPS_BWR_PACRC_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP1 field. */
+#define AIPS_RD_PACRC_SP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP1_MASK) >> AIPS_PACRC_SP1_SHIFT)
+#define AIPS_BRD_PACRC_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRC_SP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP1_MASK, AIPS_PACRC_SP1(value)))
+#define AIPS_BWR_PACRC_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP0 field. */
+#define AIPS_RD_PACRC_TP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP0_MASK) >> AIPS_PACRC_TP0_SHIFT)
+#define AIPS_BRD_PACRC_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRC_TP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP0_MASK, AIPS_PACRC_TP0(value)))
+#define AIPS_BWR_PACRC_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP0 field. */
+#define AIPS_RD_PACRC_WP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP0_MASK) >> AIPS_PACRC_WP0_SHIFT)
+#define AIPS_BRD_PACRC_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRC_WP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP0_MASK, AIPS_PACRC_WP0(value)))
+#define AIPS_BWR_PACRC_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP0 field. */
+#define AIPS_RD_PACRC_SP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP0_MASK) >> AIPS_PACRC_SP0_SHIFT)
+#define AIPS_BRD_PACRC_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRC_SP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP0_MASK, AIPS_PACRC_SP0(value)))
+#define AIPS_BWR_PACRC_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRD - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRD - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRD register
+ */
+/*@{*/
+#define AIPS_RD_PACRD(base)      (AIPS_PACRD_REG(base))
+#define AIPS_WR_PACRD(base, value) (AIPS_PACRD_REG(base) = (value))
+#define AIPS_RMW_PACRD(base, mask, value) (AIPS_WR_PACRD(base, (AIPS_RD_PACRD(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) |  (value)))
+#define AIPS_CLR_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) & ~(value)))
+#define AIPS_TOG_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRD bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRD, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP7 field. */
+#define AIPS_RD_PACRD_TP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP7_MASK) >> AIPS_PACRD_TP7_SHIFT)
+#define AIPS_BRD_PACRD_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRD_TP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP7_MASK, AIPS_PACRD_TP7(value)))
+#define AIPS_BWR_PACRD_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP7 field. */
+#define AIPS_RD_PACRD_WP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP7_MASK) >> AIPS_PACRD_WP7_SHIFT)
+#define AIPS_BRD_PACRD_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRD_WP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP7_MASK, AIPS_PACRD_WP7(value)))
+#define AIPS_BWR_PACRD_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP7 field. */
+#define AIPS_RD_PACRD_SP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP7_MASK) >> AIPS_PACRD_SP7_SHIFT)
+#define AIPS_BRD_PACRD_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRD_SP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP7_MASK, AIPS_PACRD_SP7(value)))
+#define AIPS_BWR_PACRD_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP6 field. */
+#define AIPS_RD_PACRD_TP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP6_MASK) >> AIPS_PACRD_TP6_SHIFT)
+#define AIPS_BRD_PACRD_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRD_TP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP6_MASK, AIPS_PACRD_TP6(value)))
+#define AIPS_BWR_PACRD_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP6 field. */
+#define AIPS_RD_PACRD_WP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP6_MASK) >> AIPS_PACRD_WP6_SHIFT)
+#define AIPS_BRD_PACRD_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRD_WP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP6_MASK, AIPS_PACRD_WP6(value)))
+#define AIPS_BWR_PACRD_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP6 field. */
+#define AIPS_RD_PACRD_SP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP6_MASK) >> AIPS_PACRD_SP6_SHIFT)
+#define AIPS_BRD_PACRD_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRD_SP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP6_MASK, AIPS_PACRD_SP6(value)))
+#define AIPS_BWR_PACRD_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP5 field. */
+#define AIPS_RD_PACRD_TP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP5_MASK) >> AIPS_PACRD_TP5_SHIFT)
+#define AIPS_BRD_PACRD_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRD_TP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP5_MASK, AIPS_PACRD_TP5(value)))
+#define AIPS_BWR_PACRD_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP5 field. */
+#define AIPS_RD_PACRD_WP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP5_MASK) >> AIPS_PACRD_WP5_SHIFT)
+#define AIPS_BRD_PACRD_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRD_WP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP5_MASK, AIPS_PACRD_WP5(value)))
+#define AIPS_BWR_PACRD_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP5 field. */
+#define AIPS_RD_PACRD_SP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP5_MASK) >> AIPS_PACRD_SP5_SHIFT)
+#define AIPS_BRD_PACRD_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRD_SP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP5_MASK, AIPS_PACRD_SP5(value)))
+#define AIPS_BWR_PACRD_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP4 field. */
+#define AIPS_RD_PACRD_TP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP4_MASK) >> AIPS_PACRD_TP4_SHIFT)
+#define AIPS_BRD_PACRD_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRD_TP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP4_MASK, AIPS_PACRD_TP4(value)))
+#define AIPS_BWR_PACRD_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP4 field. */
+#define AIPS_RD_PACRD_WP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP4_MASK) >> AIPS_PACRD_WP4_SHIFT)
+#define AIPS_BRD_PACRD_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRD_WP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP4_MASK, AIPS_PACRD_WP4(value)))
+#define AIPS_BWR_PACRD_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP4 field. */
+#define AIPS_RD_PACRD_SP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP4_MASK) >> AIPS_PACRD_SP4_SHIFT)
+#define AIPS_BRD_PACRD_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRD_SP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP4_MASK, AIPS_PACRD_SP4(value)))
+#define AIPS_BWR_PACRD_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP3 field. */
+#define AIPS_RD_PACRD_TP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP3_MASK) >> AIPS_PACRD_TP3_SHIFT)
+#define AIPS_BRD_PACRD_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRD_TP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP3_MASK, AIPS_PACRD_TP3(value)))
+#define AIPS_BWR_PACRD_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP3 field. */
+#define AIPS_RD_PACRD_WP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP3_MASK) >> AIPS_PACRD_WP3_SHIFT)
+#define AIPS_BRD_PACRD_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRD_WP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP3_MASK, AIPS_PACRD_WP3(value)))
+#define AIPS_BWR_PACRD_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP3 field. */
+#define AIPS_RD_PACRD_SP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP3_MASK) >> AIPS_PACRD_SP3_SHIFT)
+#define AIPS_BRD_PACRD_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRD_SP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP3_MASK, AIPS_PACRD_SP3(value)))
+#define AIPS_BWR_PACRD_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP2 field. */
+#define AIPS_RD_PACRD_TP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP2_MASK) >> AIPS_PACRD_TP2_SHIFT)
+#define AIPS_BRD_PACRD_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRD_TP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP2_MASK, AIPS_PACRD_TP2(value)))
+#define AIPS_BWR_PACRD_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP2 field. */
+#define AIPS_RD_PACRD_WP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP2_MASK) >> AIPS_PACRD_WP2_SHIFT)
+#define AIPS_BRD_PACRD_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRD_WP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP2_MASK, AIPS_PACRD_WP2(value)))
+#define AIPS_BWR_PACRD_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP2 field. */
+#define AIPS_RD_PACRD_SP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP2_MASK) >> AIPS_PACRD_SP2_SHIFT)
+#define AIPS_BRD_PACRD_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRD_SP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP2_MASK, AIPS_PACRD_SP2(value)))
+#define AIPS_BWR_PACRD_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP1 field. */
+#define AIPS_RD_PACRD_TP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP1_MASK) >> AIPS_PACRD_TP1_SHIFT)
+#define AIPS_BRD_PACRD_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRD_TP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP1_MASK, AIPS_PACRD_TP1(value)))
+#define AIPS_BWR_PACRD_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP1 field. */
+#define AIPS_RD_PACRD_WP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP1_MASK) >> AIPS_PACRD_WP1_SHIFT)
+#define AIPS_BRD_PACRD_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRD_WP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP1_MASK, AIPS_PACRD_WP1(value)))
+#define AIPS_BWR_PACRD_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP1 field. */
+#define AIPS_RD_PACRD_SP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP1_MASK) >> AIPS_PACRD_SP1_SHIFT)
+#define AIPS_BRD_PACRD_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRD_SP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP1_MASK, AIPS_PACRD_SP1(value)))
+#define AIPS_BWR_PACRD_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP0 field. */
+#define AIPS_RD_PACRD_TP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP0_MASK) >> AIPS_PACRD_TP0_SHIFT)
+#define AIPS_BRD_PACRD_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRD_TP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP0_MASK, AIPS_PACRD_TP0(value)))
+#define AIPS_BWR_PACRD_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP0 field. */
+#define AIPS_RD_PACRD_WP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP0_MASK) >> AIPS_PACRD_WP0_SHIFT)
+#define AIPS_BRD_PACRD_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRD_WP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP0_MASK, AIPS_PACRD_WP0(value)))
+#define AIPS_BWR_PACRD_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP0 field. */
+#define AIPS_RD_PACRD_SP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP0_MASK) >> AIPS_PACRD_SP0_SHIFT)
+#define AIPS_BRD_PACRD_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRD_SP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP0_MASK, AIPS_PACRD_SP0(value)))
+#define AIPS_BWR_PACRD_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRE - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRE - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRE register
+ */
+/*@{*/
+#define AIPS_RD_PACRE(base)      (AIPS_PACRE_REG(base))
+#define AIPS_WR_PACRE(base, value) (AIPS_PACRE_REG(base) = (value))
+#define AIPS_RMW_PACRE(base, mask, value) (AIPS_WR_PACRE(base, (AIPS_RD_PACRE(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) |  (value)))
+#define AIPS_CLR_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) & ~(value)))
+#define AIPS_TOG_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRE bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRE, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP7 field. */
+#define AIPS_RD_PACRE_TP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP7_MASK) >> AIPS_PACRE_TP7_SHIFT)
+#define AIPS_BRD_PACRE_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRE_TP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP7_MASK, AIPS_PACRE_TP7(value)))
+#define AIPS_BWR_PACRE_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP7 field. */
+#define AIPS_RD_PACRE_WP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP7_MASK) >> AIPS_PACRE_WP7_SHIFT)
+#define AIPS_BRD_PACRE_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRE_WP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP7_MASK, AIPS_PACRE_WP7(value)))
+#define AIPS_BWR_PACRE_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP7 field. */
+#define AIPS_RD_PACRE_SP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP7_MASK) >> AIPS_PACRE_SP7_SHIFT)
+#define AIPS_BRD_PACRE_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRE_SP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP7_MASK, AIPS_PACRE_SP7(value)))
+#define AIPS_BWR_PACRE_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP6 field. */
+#define AIPS_RD_PACRE_TP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP6_MASK) >> AIPS_PACRE_TP6_SHIFT)
+#define AIPS_BRD_PACRE_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRE_TP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP6_MASK, AIPS_PACRE_TP6(value)))
+#define AIPS_BWR_PACRE_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP6 field. */
+#define AIPS_RD_PACRE_WP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP6_MASK) >> AIPS_PACRE_WP6_SHIFT)
+#define AIPS_BRD_PACRE_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRE_WP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP6_MASK, AIPS_PACRE_WP6(value)))
+#define AIPS_BWR_PACRE_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP6 field. */
+#define AIPS_RD_PACRE_SP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP6_MASK) >> AIPS_PACRE_SP6_SHIFT)
+#define AIPS_BRD_PACRE_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRE_SP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP6_MASK, AIPS_PACRE_SP6(value)))
+#define AIPS_BWR_PACRE_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP5 field. */
+#define AIPS_RD_PACRE_TP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP5_MASK) >> AIPS_PACRE_TP5_SHIFT)
+#define AIPS_BRD_PACRE_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRE_TP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP5_MASK, AIPS_PACRE_TP5(value)))
+#define AIPS_BWR_PACRE_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP5 field. */
+#define AIPS_RD_PACRE_WP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP5_MASK) >> AIPS_PACRE_WP5_SHIFT)
+#define AIPS_BRD_PACRE_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRE_WP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP5_MASK, AIPS_PACRE_WP5(value)))
+#define AIPS_BWR_PACRE_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP5 field. */
+#define AIPS_RD_PACRE_SP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP5_MASK) >> AIPS_PACRE_SP5_SHIFT)
+#define AIPS_BRD_PACRE_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRE_SP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP5_MASK, AIPS_PACRE_SP5(value)))
+#define AIPS_BWR_PACRE_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP4 field. */
+#define AIPS_RD_PACRE_TP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP4_MASK) >> AIPS_PACRE_TP4_SHIFT)
+#define AIPS_BRD_PACRE_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRE_TP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP4_MASK, AIPS_PACRE_TP4(value)))
+#define AIPS_BWR_PACRE_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP4 field. */
+#define AIPS_RD_PACRE_WP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP4_MASK) >> AIPS_PACRE_WP4_SHIFT)
+#define AIPS_BRD_PACRE_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRE_WP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP4_MASK, AIPS_PACRE_WP4(value)))
+#define AIPS_BWR_PACRE_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP4 field. */
+#define AIPS_RD_PACRE_SP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP4_MASK) >> AIPS_PACRE_SP4_SHIFT)
+#define AIPS_BRD_PACRE_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRE_SP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP4_MASK, AIPS_PACRE_SP4(value)))
+#define AIPS_BWR_PACRE_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP3 field. */
+#define AIPS_RD_PACRE_TP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP3_MASK) >> AIPS_PACRE_TP3_SHIFT)
+#define AIPS_BRD_PACRE_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRE_TP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP3_MASK, AIPS_PACRE_TP3(value)))
+#define AIPS_BWR_PACRE_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP3 field. */
+#define AIPS_RD_PACRE_WP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP3_MASK) >> AIPS_PACRE_WP3_SHIFT)
+#define AIPS_BRD_PACRE_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRE_WP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP3_MASK, AIPS_PACRE_WP3(value)))
+#define AIPS_BWR_PACRE_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP3 field. */
+#define AIPS_RD_PACRE_SP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP3_MASK) >> AIPS_PACRE_SP3_SHIFT)
+#define AIPS_BRD_PACRE_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRE_SP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP3_MASK, AIPS_PACRE_SP3(value)))
+#define AIPS_BWR_PACRE_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP2 field. */
+#define AIPS_RD_PACRE_TP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP2_MASK) >> AIPS_PACRE_TP2_SHIFT)
+#define AIPS_BRD_PACRE_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRE_TP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP2_MASK, AIPS_PACRE_TP2(value)))
+#define AIPS_BWR_PACRE_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP2 field. */
+#define AIPS_RD_PACRE_WP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP2_MASK) >> AIPS_PACRE_WP2_SHIFT)
+#define AIPS_BRD_PACRE_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRE_WP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP2_MASK, AIPS_PACRE_WP2(value)))
+#define AIPS_BWR_PACRE_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP2 field. */
+#define AIPS_RD_PACRE_SP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP2_MASK) >> AIPS_PACRE_SP2_SHIFT)
+#define AIPS_BRD_PACRE_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRE_SP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP2_MASK, AIPS_PACRE_SP2(value)))
+#define AIPS_BWR_PACRE_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP1 field. */
+#define AIPS_RD_PACRE_TP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP1_MASK) >> AIPS_PACRE_TP1_SHIFT)
+#define AIPS_BRD_PACRE_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRE_TP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP1_MASK, AIPS_PACRE_TP1(value)))
+#define AIPS_BWR_PACRE_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP1 field. */
+#define AIPS_RD_PACRE_WP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP1_MASK) >> AIPS_PACRE_WP1_SHIFT)
+#define AIPS_BRD_PACRE_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRE_WP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP1_MASK, AIPS_PACRE_WP1(value)))
+#define AIPS_BWR_PACRE_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP1 field. */
+#define AIPS_RD_PACRE_SP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP1_MASK) >> AIPS_PACRE_SP1_SHIFT)
+#define AIPS_BRD_PACRE_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRE_SP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP1_MASK, AIPS_PACRE_SP1(value)))
+#define AIPS_BWR_PACRE_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP0 field. */
+#define AIPS_RD_PACRE_TP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP0_MASK) >> AIPS_PACRE_TP0_SHIFT)
+#define AIPS_BRD_PACRE_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRE_TP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP0_MASK, AIPS_PACRE_TP0(value)))
+#define AIPS_BWR_PACRE_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP0 field. */
+#define AIPS_RD_PACRE_WP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP0_MASK) >> AIPS_PACRE_WP0_SHIFT)
+#define AIPS_BRD_PACRE_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRE_WP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP0_MASK, AIPS_PACRE_WP0(value)))
+#define AIPS_BWR_PACRE_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP0 field. */
+#define AIPS_RD_PACRE_SP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP0_MASK) >> AIPS_PACRE_SP0_SHIFT)
+#define AIPS_BRD_PACRE_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRE_SP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP0_MASK, AIPS_PACRE_SP0(value)))
+#define AIPS_BWR_PACRE_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRF - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRF - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRF register
+ */
+/*@{*/
+#define AIPS_RD_PACRF(base)      (AIPS_PACRF_REG(base))
+#define AIPS_WR_PACRF(base, value) (AIPS_PACRF_REG(base) = (value))
+#define AIPS_RMW_PACRF(base, mask, value) (AIPS_WR_PACRF(base, (AIPS_RD_PACRF(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) |  (value)))
+#define AIPS_CLR_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) & ~(value)))
+#define AIPS_TOG_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRF bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRF, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP7 field. */
+#define AIPS_RD_PACRF_TP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP7_MASK) >> AIPS_PACRF_TP7_SHIFT)
+#define AIPS_BRD_PACRF_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRF_TP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP7_MASK, AIPS_PACRF_TP7(value)))
+#define AIPS_BWR_PACRF_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP7 field. */
+#define AIPS_RD_PACRF_WP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP7_MASK) >> AIPS_PACRF_WP7_SHIFT)
+#define AIPS_BRD_PACRF_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRF_WP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP7_MASK, AIPS_PACRF_WP7(value)))
+#define AIPS_BWR_PACRF_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP7 field. */
+#define AIPS_RD_PACRF_SP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP7_MASK) >> AIPS_PACRF_SP7_SHIFT)
+#define AIPS_BRD_PACRF_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRF_SP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP7_MASK, AIPS_PACRF_SP7(value)))
+#define AIPS_BWR_PACRF_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP6 field. */
+#define AIPS_RD_PACRF_TP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP6_MASK) >> AIPS_PACRF_TP6_SHIFT)
+#define AIPS_BRD_PACRF_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRF_TP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP6_MASK, AIPS_PACRF_TP6(value)))
+#define AIPS_BWR_PACRF_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP6 field. */
+#define AIPS_RD_PACRF_WP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP6_MASK) >> AIPS_PACRF_WP6_SHIFT)
+#define AIPS_BRD_PACRF_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRF_WP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP6_MASK, AIPS_PACRF_WP6(value)))
+#define AIPS_BWR_PACRF_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP6 field. */
+#define AIPS_RD_PACRF_SP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP6_MASK) >> AIPS_PACRF_SP6_SHIFT)
+#define AIPS_BRD_PACRF_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRF_SP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP6_MASK, AIPS_PACRF_SP6(value)))
+#define AIPS_BWR_PACRF_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP5 field. */
+#define AIPS_RD_PACRF_TP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP5_MASK) >> AIPS_PACRF_TP5_SHIFT)
+#define AIPS_BRD_PACRF_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRF_TP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP5_MASK, AIPS_PACRF_TP5(value)))
+#define AIPS_BWR_PACRF_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP5 field. */
+#define AIPS_RD_PACRF_WP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP5_MASK) >> AIPS_PACRF_WP5_SHIFT)
+#define AIPS_BRD_PACRF_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRF_WP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP5_MASK, AIPS_PACRF_WP5(value)))
+#define AIPS_BWR_PACRF_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP5 field. */
+#define AIPS_RD_PACRF_SP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP5_MASK) >> AIPS_PACRF_SP5_SHIFT)
+#define AIPS_BRD_PACRF_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRF_SP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP5_MASK, AIPS_PACRF_SP5(value)))
+#define AIPS_BWR_PACRF_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP4 field. */
+#define AIPS_RD_PACRF_TP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP4_MASK) >> AIPS_PACRF_TP4_SHIFT)
+#define AIPS_BRD_PACRF_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRF_TP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP4_MASK, AIPS_PACRF_TP4(value)))
+#define AIPS_BWR_PACRF_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP4 field. */
+#define AIPS_RD_PACRF_WP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP4_MASK) >> AIPS_PACRF_WP4_SHIFT)
+#define AIPS_BRD_PACRF_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRF_WP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP4_MASK, AIPS_PACRF_WP4(value)))
+#define AIPS_BWR_PACRF_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP4 field. */
+#define AIPS_RD_PACRF_SP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP4_MASK) >> AIPS_PACRF_SP4_SHIFT)
+#define AIPS_BRD_PACRF_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRF_SP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP4_MASK, AIPS_PACRF_SP4(value)))
+#define AIPS_BWR_PACRF_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP3 field. */
+#define AIPS_RD_PACRF_TP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP3_MASK) >> AIPS_PACRF_TP3_SHIFT)
+#define AIPS_BRD_PACRF_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRF_TP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP3_MASK, AIPS_PACRF_TP3(value)))
+#define AIPS_BWR_PACRF_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP3 field. */
+#define AIPS_RD_PACRF_WP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP3_MASK) >> AIPS_PACRF_WP3_SHIFT)
+#define AIPS_BRD_PACRF_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRF_WP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP3_MASK, AIPS_PACRF_WP3(value)))
+#define AIPS_BWR_PACRF_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP3 field. */
+#define AIPS_RD_PACRF_SP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP3_MASK) >> AIPS_PACRF_SP3_SHIFT)
+#define AIPS_BRD_PACRF_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRF_SP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP3_MASK, AIPS_PACRF_SP3(value)))
+#define AIPS_BWR_PACRF_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP2 field. */
+#define AIPS_RD_PACRF_TP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP2_MASK) >> AIPS_PACRF_TP2_SHIFT)
+#define AIPS_BRD_PACRF_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRF_TP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP2_MASK, AIPS_PACRF_TP2(value)))
+#define AIPS_BWR_PACRF_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP2 field. */
+#define AIPS_RD_PACRF_WP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP2_MASK) >> AIPS_PACRF_WP2_SHIFT)
+#define AIPS_BRD_PACRF_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRF_WP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP2_MASK, AIPS_PACRF_WP2(value)))
+#define AIPS_BWR_PACRF_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP2 field. */
+#define AIPS_RD_PACRF_SP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP2_MASK) >> AIPS_PACRF_SP2_SHIFT)
+#define AIPS_BRD_PACRF_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRF_SP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP2_MASK, AIPS_PACRF_SP2(value)))
+#define AIPS_BWR_PACRF_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP1 field. */
+#define AIPS_RD_PACRF_TP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP1_MASK) >> AIPS_PACRF_TP1_SHIFT)
+#define AIPS_BRD_PACRF_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRF_TP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP1_MASK, AIPS_PACRF_TP1(value)))
+#define AIPS_BWR_PACRF_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP1 field. */
+#define AIPS_RD_PACRF_WP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP1_MASK) >> AIPS_PACRF_WP1_SHIFT)
+#define AIPS_BRD_PACRF_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRF_WP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP1_MASK, AIPS_PACRF_WP1(value)))
+#define AIPS_BWR_PACRF_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP1 field. */
+#define AIPS_RD_PACRF_SP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP1_MASK) >> AIPS_PACRF_SP1_SHIFT)
+#define AIPS_BRD_PACRF_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRF_SP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP1_MASK, AIPS_PACRF_SP1(value)))
+#define AIPS_BWR_PACRF_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP0 field. */
+#define AIPS_RD_PACRF_TP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP0_MASK) >> AIPS_PACRF_TP0_SHIFT)
+#define AIPS_BRD_PACRF_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRF_TP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP0_MASK, AIPS_PACRF_TP0(value)))
+#define AIPS_BWR_PACRF_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP0 field. */
+#define AIPS_RD_PACRF_WP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP0_MASK) >> AIPS_PACRF_WP0_SHIFT)
+#define AIPS_BRD_PACRF_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRF_WP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP0_MASK, AIPS_PACRF_WP0(value)))
+#define AIPS_BWR_PACRF_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP0 field. */
+#define AIPS_RD_PACRF_SP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP0_MASK) >> AIPS_PACRF_SP0_SHIFT)
+#define AIPS_BRD_PACRF_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRF_SP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP0_MASK, AIPS_PACRF_SP0(value)))
+#define AIPS_BWR_PACRF_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRG - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRG - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRG register
+ */
+/*@{*/
+#define AIPS_RD_PACRG(base)      (AIPS_PACRG_REG(base))
+#define AIPS_WR_PACRG(base, value) (AIPS_PACRG_REG(base) = (value))
+#define AIPS_RMW_PACRG(base, mask, value) (AIPS_WR_PACRG(base, (AIPS_RD_PACRG(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) |  (value)))
+#define AIPS_CLR_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) & ~(value)))
+#define AIPS_TOG_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRG bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRG, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP7 field. */
+#define AIPS_RD_PACRG_TP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP7_MASK) >> AIPS_PACRG_TP7_SHIFT)
+#define AIPS_BRD_PACRG_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRG_TP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP7_MASK, AIPS_PACRG_TP7(value)))
+#define AIPS_BWR_PACRG_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP7 field. */
+#define AIPS_RD_PACRG_WP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP7_MASK) >> AIPS_PACRG_WP7_SHIFT)
+#define AIPS_BRD_PACRG_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRG_WP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP7_MASK, AIPS_PACRG_WP7(value)))
+#define AIPS_BWR_PACRG_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP7 field. */
+#define AIPS_RD_PACRG_SP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP7_MASK) >> AIPS_PACRG_SP7_SHIFT)
+#define AIPS_BRD_PACRG_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRG_SP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP7_MASK, AIPS_PACRG_SP7(value)))
+#define AIPS_BWR_PACRG_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP6 field. */
+#define AIPS_RD_PACRG_TP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP6_MASK) >> AIPS_PACRG_TP6_SHIFT)
+#define AIPS_BRD_PACRG_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRG_TP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP6_MASK, AIPS_PACRG_TP6(value)))
+#define AIPS_BWR_PACRG_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP6 field. */
+#define AIPS_RD_PACRG_WP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP6_MASK) >> AIPS_PACRG_WP6_SHIFT)
+#define AIPS_BRD_PACRG_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRG_WP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP6_MASK, AIPS_PACRG_WP6(value)))
+#define AIPS_BWR_PACRG_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP6 field. */
+#define AIPS_RD_PACRG_SP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP6_MASK) >> AIPS_PACRG_SP6_SHIFT)
+#define AIPS_BRD_PACRG_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRG_SP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP6_MASK, AIPS_PACRG_SP6(value)))
+#define AIPS_BWR_PACRG_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP5 field. */
+#define AIPS_RD_PACRG_TP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP5_MASK) >> AIPS_PACRG_TP5_SHIFT)
+#define AIPS_BRD_PACRG_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRG_TP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP5_MASK, AIPS_PACRG_TP5(value)))
+#define AIPS_BWR_PACRG_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP5 field. */
+#define AIPS_RD_PACRG_WP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP5_MASK) >> AIPS_PACRG_WP5_SHIFT)
+#define AIPS_BRD_PACRG_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRG_WP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP5_MASK, AIPS_PACRG_WP5(value)))
+#define AIPS_BWR_PACRG_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP5 field. */
+#define AIPS_RD_PACRG_SP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP5_MASK) >> AIPS_PACRG_SP5_SHIFT)
+#define AIPS_BRD_PACRG_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRG_SP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP5_MASK, AIPS_PACRG_SP5(value)))
+#define AIPS_BWR_PACRG_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP4 field. */
+#define AIPS_RD_PACRG_TP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP4_MASK) >> AIPS_PACRG_TP4_SHIFT)
+#define AIPS_BRD_PACRG_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRG_TP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP4_MASK, AIPS_PACRG_TP4(value)))
+#define AIPS_BWR_PACRG_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP4 field. */
+#define AIPS_RD_PACRG_WP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP4_MASK) >> AIPS_PACRG_WP4_SHIFT)
+#define AIPS_BRD_PACRG_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRG_WP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP4_MASK, AIPS_PACRG_WP4(value)))
+#define AIPS_BWR_PACRG_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP4 field. */
+#define AIPS_RD_PACRG_SP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP4_MASK) >> AIPS_PACRG_SP4_SHIFT)
+#define AIPS_BRD_PACRG_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRG_SP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP4_MASK, AIPS_PACRG_SP4(value)))
+#define AIPS_BWR_PACRG_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP3 field. */
+#define AIPS_RD_PACRG_TP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP3_MASK) >> AIPS_PACRG_TP3_SHIFT)
+#define AIPS_BRD_PACRG_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRG_TP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP3_MASK, AIPS_PACRG_TP3(value)))
+#define AIPS_BWR_PACRG_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP3 field. */
+#define AIPS_RD_PACRG_WP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP3_MASK) >> AIPS_PACRG_WP3_SHIFT)
+#define AIPS_BRD_PACRG_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRG_WP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP3_MASK, AIPS_PACRG_WP3(value)))
+#define AIPS_BWR_PACRG_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP3 field. */
+#define AIPS_RD_PACRG_SP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP3_MASK) >> AIPS_PACRG_SP3_SHIFT)
+#define AIPS_BRD_PACRG_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRG_SP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP3_MASK, AIPS_PACRG_SP3(value)))
+#define AIPS_BWR_PACRG_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP2 field. */
+#define AIPS_RD_PACRG_TP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP2_MASK) >> AIPS_PACRG_TP2_SHIFT)
+#define AIPS_BRD_PACRG_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRG_TP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP2_MASK, AIPS_PACRG_TP2(value)))
+#define AIPS_BWR_PACRG_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP2 field. */
+#define AIPS_RD_PACRG_WP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP2_MASK) >> AIPS_PACRG_WP2_SHIFT)
+#define AIPS_BRD_PACRG_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRG_WP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP2_MASK, AIPS_PACRG_WP2(value)))
+#define AIPS_BWR_PACRG_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP2 field. */
+#define AIPS_RD_PACRG_SP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP2_MASK) >> AIPS_PACRG_SP2_SHIFT)
+#define AIPS_BRD_PACRG_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRG_SP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP2_MASK, AIPS_PACRG_SP2(value)))
+#define AIPS_BWR_PACRG_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP1 field. */
+#define AIPS_RD_PACRG_TP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP1_MASK) >> AIPS_PACRG_TP1_SHIFT)
+#define AIPS_BRD_PACRG_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRG_TP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP1_MASK, AIPS_PACRG_TP1(value)))
+#define AIPS_BWR_PACRG_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP1 field. */
+#define AIPS_RD_PACRG_WP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP1_MASK) >> AIPS_PACRG_WP1_SHIFT)
+#define AIPS_BRD_PACRG_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRG_WP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP1_MASK, AIPS_PACRG_WP1(value)))
+#define AIPS_BWR_PACRG_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP1 field. */
+#define AIPS_RD_PACRG_SP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP1_MASK) >> AIPS_PACRG_SP1_SHIFT)
+#define AIPS_BRD_PACRG_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRG_SP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP1_MASK, AIPS_PACRG_SP1(value)))
+#define AIPS_BWR_PACRG_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP0 field. */
+#define AIPS_RD_PACRG_TP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP0_MASK) >> AIPS_PACRG_TP0_SHIFT)
+#define AIPS_BRD_PACRG_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRG_TP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP0_MASK, AIPS_PACRG_TP0(value)))
+#define AIPS_BWR_PACRG_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP0 field. */
+#define AIPS_RD_PACRG_WP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP0_MASK) >> AIPS_PACRG_WP0_SHIFT)
+#define AIPS_BRD_PACRG_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRG_WP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP0_MASK, AIPS_PACRG_WP0(value)))
+#define AIPS_BWR_PACRG_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP0 field. */
+#define AIPS_RD_PACRG_SP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP0_MASK) >> AIPS_PACRG_SP0_SHIFT)
+#define AIPS_BRD_PACRG_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRG_SP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP0_MASK, AIPS_PACRG_SP0(value)))
+#define AIPS_BWR_PACRG_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRH - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRH - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRH register
+ */
+/*@{*/
+#define AIPS_RD_PACRH(base)      (AIPS_PACRH_REG(base))
+#define AIPS_WR_PACRH(base, value) (AIPS_PACRH_REG(base) = (value))
+#define AIPS_RMW_PACRH(base, mask, value) (AIPS_WR_PACRH(base, (AIPS_RD_PACRH(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) |  (value)))
+#define AIPS_CLR_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) & ~(value)))
+#define AIPS_TOG_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRH bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRH, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP7 field. */
+#define AIPS_RD_PACRH_TP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP7_MASK) >> AIPS_PACRH_TP7_SHIFT)
+#define AIPS_BRD_PACRH_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRH_TP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP7_MASK, AIPS_PACRH_TP7(value)))
+#define AIPS_BWR_PACRH_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP7 field. */
+#define AIPS_RD_PACRH_WP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP7_MASK) >> AIPS_PACRH_WP7_SHIFT)
+#define AIPS_BRD_PACRH_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRH_WP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP7_MASK, AIPS_PACRH_WP7(value)))
+#define AIPS_BWR_PACRH_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP7 field. */
+#define AIPS_RD_PACRH_SP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP7_MASK) >> AIPS_PACRH_SP7_SHIFT)
+#define AIPS_BRD_PACRH_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRH_SP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP7_MASK, AIPS_PACRH_SP7(value)))
+#define AIPS_BWR_PACRH_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP6 field. */
+#define AIPS_RD_PACRH_TP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP6_MASK) >> AIPS_PACRH_TP6_SHIFT)
+#define AIPS_BRD_PACRH_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRH_TP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP6_MASK, AIPS_PACRH_TP6(value)))
+#define AIPS_BWR_PACRH_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP6 field. */
+#define AIPS_RD_PACRH_WP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP6_MASK) >> AIPS_PACRH_WP6_SHIFT)
+#define AIPS_BRD_PACRH_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRH_WP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP6_MASK, AIPS_PACRH_WP6(value)))
+#define AIPS_BWR_PACRH_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP6 field. */
+#define AIPS_RD_PACRH_SP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP6_MASK) >> AIPS_PACRH_SP6_SHIFT)
+#define AIPS_BRD_PACRH_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRH_SP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP6_MASK, AIPS_PACRH_SP6(value)))
+#define AIPS_BWR_PACRH_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP5 field. */
+#define AIPS_RD_PACRH_TP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP5_MASK) >> AIPS_PACRH_TP5_SHIFT)
+#define AIPS_BRD_PACRH_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRH_TP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP5_MASK, AIPS_PACRH_TP5(value)))
+#define AIPS_BWR_PACRH_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP5 field. */
+#define AIPS_RD_PACRH_WP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP5_MASK) >> AIPS_PACRH_WP5_SHIFT)
+#define AIPS_BRD_PACRH_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRH_WP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP5_MASK, AIPS_PACRH_WP5(value)))
+#define AIPS_BWR_PACRH_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP5 field. */
+#define AIPS_RD_PACRH_SP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP5_MASK) >> AIPS_PACRH_SP5_SHIFT)
+#define AIPS_BRD_PACRH_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRH_SP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP5_MASK, AIPS_PACRH_SP5(value)))
+#define AIPS_BWR_PACRH_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP4 field. */
+#define AIPS_RD_PACRH_TP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP4_MASK) >> AIPS_PACRH_TP4_SHIFT)
+#define AIPS_BRD_PACRH_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRH_TP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP4_MASK, AIPS_PACRH_TP4(value)))
+#define AIPS_BWR_PACRH_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP4 field. */
+#define AIPS_RD_PACRH_WP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP4_MASK) >> AIPS_PACRH_WP4_SHIFT)
+#define AIPS_BRD_PACRH_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRH_WP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP4_MASK, AIPS_PACRH_WP4(value)))
+#define AIPS_BWR_PACRH_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP4 field. */
+#define AIPS_RD_PACRH_SP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP4_MASK) >> AIPS_PACRH_SP4_SHIFT)
+#define AIPS_BRD_PACRH_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRH_SP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP4_MASK, AIPS_PACRH_SP4(value)))
+#define AIPS_BWR_PACRH_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP3 field. */
+#define AIPS_RD_PACRH_TP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP3_MASK) >> AIPS_PACRH_TP3_SHIFT)
+#define AIPS_BRD_PACRH_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRH_TP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP3_MASK, AIPS_PACRH_TP3(value)))
+#define AIPS_BWR_PACRH_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP3 field. */
+#define AIPS_RD_PACRH_WP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP3_MASK) >> AIPS_PACRH_WP3_SHIFT)
+#define AIPS_BRD_PACRH_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRH_WP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP3_MASK, AIPS_PACRH_WP3(value)))
+#define AIPS_BWR_PACRH_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP3 field. */
+#define AIPS_RD_PACRH_SP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP3_MASK) >> AIPS_PACRH_SP3_SHIFT)
+#define AIPS_BRD_PACRH_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRH_SP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP3_MASK, AIPS_PACRH_SP3(value)))
+#define AIPS_BWR_PACRH_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP2 field. */
+#define AIPS_RD_PACRH_TP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP2_MASK) >> AIPS_PACRH_TP2_SHIFT)
+#define AIPS_BRD_PACRH_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRH_TP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP2_MASK, AIPS_PACRH_TP2(value)))
+#define AIPS_BWR_PACRH_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP2 field. */
+#define AIPS_RD_PACRH_WP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP2_MASK) >> AIPS_PACRH_WP2_SHIFT)
+#define AIPS_BRD_PACRH_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRH_WP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP2_MASK, AIPS_PACRH_WP2(value)))
+#define AIPS_BWR_PACRH_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP2 field. */
+#define AIPS_RD_PACRH_SP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP2_MASK) >> AIPS_PACRH_SP2_SHIFT)
+#define AIPS_BRD_PACRH_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRH_SP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP2_MASK, AIPS_PACRH_SP2(value)))
+#define AIPS_BWR_PACRH_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP1 field. */
+#define AIPS_RD_PACRH_TP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP1_MASK) >> AIPS_PACRH_TP1_SHIFT)
+#define AIPS_BRD_PACRH_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRH_TP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP1_MASK, AIPS_PACRH_TP1(value)))
+#define AIPS_BWR_PACRH_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP1 field. */
+#define AIPS_RD_PACRH_WP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP1_MASK) >> AIPS_PACRH_WP1_SHIFT)
+#define AIPS_BRD_PACRH_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRH_WP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP1_MASK, AIPS_PACRH_WP1(value)))
+#define AIPS_BWR_PACRH_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP1 field. */
+#define AIPS_RD_PACRH_SP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP1_MASK) >> AIPS_PACRH_SP1_SHIFT)
+#define AIPS_BRD_PACRH_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRH_SP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP1_MASK, AIPS_PACRH_SP1(value)))
+#define AIPS_BWR_PACRH_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP0 field. */
+#define AIPS_RD_PACRH_TP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP0_MASK) >> AIPS_PACRH_TP0_SHIFT)
+#define AIPS_BRD_PACRH_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRH_TP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP0_MASK, AIPS_PACRH_TP0(value)))
+#define AIPS_BWR_PACRH_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP0 field. */
+#define AIPS_RD_PACRH_WP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP0_MASK) >> AIPS_PACRH_WP0_SHIFT)
+#define AIPS_BRD_PACRH_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRH_WP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP0_MASK, AIPS_PACRH_WP0(value)))
+#define AIPS_BWR_PACRH_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP0 field. */
+#define AIPS_RD_PACRH_SP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP0_MASK) >> AIPS_PACRH_SP0_SHIFT)
+#define AIPS_BRD_PACRH_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRH_SP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP0_MASK, AIPS_PACRH_SP0(value)))
+#define AIPS_BWR_PACRH_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRI - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRI - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRI register
+ */
+/*@{*/
+#define AIPS_RD_PACRI(base)      (AIPS_PACRI_REG(base))
+#define AIPS_WR_PACRI(base, value) (AIPS_PACRI_REG(base) = (value))
+#define AIPS_RMW_PACRI(base, mask, value) (AIPS_WR_PACRI(base, (AIPS_RD_PACRI(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) |  (value)))
+#define AIPS_CLR_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) & ~(value)))
+#define AIPS_TOG_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRI bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRI, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP7 field. */
+#define AIPS_RD_PACRI_TP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP7_MASK) >> AIPS_PACRI_TP7_SHIFT)
+#define AIPS_BRD_PACRI_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRI_TP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP7_MASK, AIPS_PACRI_TP7(value)))
+#define AIPS_BWR_PACRI_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP7 field. */
+#define AIPS_RD_PACRI_WP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP7_MASK) >> AIPS_PACRI_WP7_SHIFT)
+#define AIPS_BRD_PACRI_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRI_WP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP7_MASK, AIPS_PACRI_WP7(value)))
+#define AIPS_BWR_PACRI_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP7 field. */
+#define AIPS_RD_PACRI_SP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP7_MASK) >> AIPS_PACRI_SP7_SHIFT)
+#define AIPS_BRD_PACRI_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRI_SP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP7_MASK, AIPS_PACRI_SP7(value)))
+#define AIPS_BWR_PACRI_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP6 field. */
+#define AIPS_RD_PACRI_TP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP6_MASK) >> AIPS_PACRI_TP6_SHIFT)
+#define AIPS_BRD_PACRI_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRI_TP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP6_MASK, AIPS_PACRI_TP6(value)))
+#define AIPS_BWR_PACRI_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP6 field. */
+#define AIPS_RD_PACRI_WP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP6_MASK) >> AIPS_PACRI_WP6_SHIFT)
+#define AIPS_BRD_PACRI_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRI_WP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP6_MASK, AIPS_PACRI_WP6(value)))
+#define AIPS_BWR_PACRI_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP6 field. */
+#define AIPS_RD_PACRI_SP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP6_MASK) >> AIPS_PACRI_SP6_SHIFT)
+#define AIPS_BRD_PACRI_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRI_SP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP6_MASK, AIPS_PACRI_SP6(value)))
+#define AIPS_BWR_PACRI_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP5 field. */
+#define AIPS_RD_PACRI_TP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP5_MASK) >> AIPS_PACRI_TP5_SHIFT)
+#define AIPS_BRD_PACRI_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRI_TP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP5_MASK, AIPS_PACRI_TP5(value)))
+#define AIPS_BWR_PACRI_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP5 field. */
+#define AIPS_RD_PACRI_WP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP5_MASK) >> AIPS_PACRI_WP5_SHIFT)
+#define AIPS_BRD_PACRI_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRI_WP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP5_MASK, AIPS_PACRI_WP5(value)))
+#define AIPS_BWR_PACRI_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP5 field. */
+#define AIPS_RD_PACRI_SP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP5_MASK) >> AIPS_PACRI_SP5_SHIFT)
+#define AIPS_BRD_PACRI_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRI_SP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP5_MASK, AIPS_PACRI_SP5(value)))
+#define AIPS_BWR_PACRI_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP4 field. */
+#define AIPS_RD_PACRI_TP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP4_MASK) >> AIPS_PACRI_TP4_SHIFT)
+#define AIPS_BRD_PACRI_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRI_TP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP4_MASK, AIPS_PACRI_TP4(value)))
+#define AIPS_BWR_PACRI_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP4 field. */
+#define AIPS_RD_PACRI_WP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP4_MASK) >> AIPS_PACRI_WP4_SHIFT)
+#define AIPS_BRD_PACRI_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRI_WP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP4_MASK, AIPS_PACRI_WP4(value)))
+#define AIPS_BWR_PACRI_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP4 field. */
+#define AIPS_RD_PACRI_SP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP4_MASK) >> AIPS_PACRI_SP4_SHIFT)
+#define AIPS_BRD_PACRI_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRI_SP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP4_MASK, AIPS_PACRI_SP4(value)))
+#define AIPS_BWR_PACRI_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP3 field. */
+#define AIPS_RD_PACRI_TP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP3_MASK) >> AIPS_PACRI_TP3_SHIFT)
+#define AIPS_BRD_PACRI_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRI_TP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP3_MASK, AIPS_PACRI_TP3(value)))
+#define AIPS_BWR_PACRI_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP3 field. */
+#define AIPS_RD_PACRI_WP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP3_MASK) >> AIPS_PACRI_WP3_SHIFT)
+#define AIPS_BRD_PACRI_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRI_WP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP3_MASK, AIPS_PACRI_WP3(value)))
+#define AIPS_BWR_PACRI_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP3 field. */
+#define AIPS_RD_PACRI_SP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP3_MASK) >> AIPS_PACRI_SP3_SHIFT)
+#define AIPS_BRD_PACRI_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRI_SP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP3_MASK, AIPS_PACRI_SP3(value)))
+#define AIPS_BWR_PACRI_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP2 field. */
+#define AIPS_RD_PACRI_TP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP2_MASK) >> AIPS_PACRI_TP2_SHIFT)
+#define AIPS_BRD_PACRI_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRI_TP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP2_MASK, AIPS_PACRI_TP2(value)))
+#define AIPS_BWR_PACRI_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP2 field. */
+#define AIPS_RD_PACRI_WP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP2_MASK) >> AIPS_PACRI_WP2_SHIFT)
+#define AIPS_BRD_PACRI_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRI_WP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP2_MASK, AIPS_PACRI_WP2(value)))
+#define AIPS_BWR_PACRI_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP2 field. */
+#define AIPS_RD_PACRI_SP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP2_MASK) >> AIPS_PACRI_SP2_SHIFT)
+#define AIPS_BRD_PACRI_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRI_SP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP2_MASK, AIPS_PACRI_SP2(value)))
+#define AIPS_BWR_PACRI_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP1 field. */
+#define AIPS_RD_PACRI_TP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP1_MASK) >> AIPS_PACRI_TP1_SHIFT)
+#define AIPS_BRD_PACRI_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRI_TP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP1_MASK, AIPS_PACRI_TP1(value)))
+#define AIPS_BWR_PACRI_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP1 field. */
+#define AIPS_RD_PACRI_WP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP1_MASK) >> AIPS_PACRI_WP1_SHIFT)
+#define AIPS_BRD_PACRI_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRI_WP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP1_MASK, AIPS_PACRI_WP1(value)))
+#define AIPS_BWR_PACRI_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP1 field. */
+#define AIPS_RD_PACRI_SP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP1_MASK) >> AIPS_PACRI_SP1_SHIFT)
+#define AIPS_BRD_PACRI_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRI_SP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP1_MASK, AIPS_PACRI_SP1(value)))
+#define AIPS_BWR_PACRI_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP0 field. */
+#define AIPS_RD_PACRI_TP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP0_MASK) >> AIPS_PACRI_TP0_SHIFT)
+#define AIPS_BRD_PACRI_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRI_TP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP0_MASK, AIPS_PACRI_TP0(value)))
+#define AIPS_BWR_PACRI_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP0 field. */
+#define AIPS_RD_PACRI_WP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP0_MASK) >> AIPS_PACRI_WP0_SHIFT)
+#define AIPS_BRD_PACRI_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRI_WP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP0_MASK, AIPS_PACRI_WP0(value)))
+#define AIPS_BWR_PACRI_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP0 field. */
+#define AIPS_RD_PACRI_SP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP0_MASK) >> AIPS_PACRI_SP0_SHIFT)
+#define AIPS_BRD_PACRI_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRI_SP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP0_MASK, AIPS_PACRI_SP0(value)))
+#define AIPS_BWR_PACRI_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRJ - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRJ - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRJ register
+ */
+/*@{*/
+#define AIPS_RD_PACRJ(base)      (AIPS_PACRJ_REG(base))
+#define AIPS_WR_PACRJ(base, value) (AIPS_PACRJ_REG(base) = (value))
+#define AIPS_RMW_PACRJ(base, mask, value) (AIPS_WR_PACRJ(base, (AIPS_RD_PACRJ(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) |  (value)))
+#define AIPS_CLR_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) & ~(value)))
+#define AIPS_TOG_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRJ bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRJ, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP7 field. */
+#define AIPS_RD_PACRJ_TP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP7_MASK) >> AIPS_PACRJ_TP7_SHIFT)
+#define AIPS_BRD_PACRJ_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRJ_TP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP7_MASK, AIPS_PACRJ_TP7(value)))
+#define AIPS_BWR_PACRJ_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP7 field. */
+#define AIPS_RD_PACRJ_WP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP7_MASK) >> AIPS_PACRJ_WP7_SHIFT)
+#define AIPS_BRD_PACRJ_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRJ_WP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP7_MASK, AIPS_PACRJ_WP7(value)))
+#define AIPS_BWR_PACRJ_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP7 field. */
+#define AIPS_RD_PACRJ_SP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP7_MASK) >> AIPS_PACRJ_SP7_SHIFT)
+#define AIPS_BRD_PACRJ_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRJ_SP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP7_MASK, AIPS_PACRJ_SP7(value)))
+#define AIPS_BWR_PACRJ_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP6 field. */
+#define AIPS_RD_PACRJ_TP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP6_MASK) >> AIPS_PACRJ_TP6_SHIFT)
+#define AIPS_BRD_PACRJ_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRJ_TP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP6_MASK, AIPS_PACRJ_TP6(value)))
+#define AIPS_BWR_PACRJ_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP6 field. */
+#define AIPS_RD_PACRJ_WP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP6_MASK) >> AIPS_PACRJ_WP6_SHIFT)
+#define AIPS_BRD_PACRJ_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRJ_WP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP6_MASK, AIPS_PACRJ_WP6(value)))
+#define AIPS_BWR_PACRJ_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP6 field. */
+#define AIPS_RD_PACRJ_SP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP6_MASK) >> AIPS_PACRJ_SP6_SHIFT)
+#define AIPS_BRD_PACRJ_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRJ_SP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP6_MASK, AIPS_PACRJ_SP6(value)))
+#define AIPS_BWR_PACRJ_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP5 field. */
+#define AIPS_RD_PACRJ_TP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP5_MASK) >> AIPS_PACRJ_TP5_SHIFT)
+#define AIPS_BRD_PACRJ_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRJ_TP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP5_MASK, AIPS_PACRJ_TP5(value)))
+#define AIPS_BWR_PACRJ_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP5 field. */
+#define AIPS_RD_PACRJ_WP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP5_MASK) >> AIPS_PACRJ_WP5_SHIFT)
+#define AIPS_BRD_PACRJ_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRJ_WP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP5_MASK, AIPS_PACRJ_WP5(value)))
+#define AIPS_BWR_PACRJ_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP5 field. */
+#define AIPS_RD_PACRJ_SP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP5_MASK) >> AIPS_PACRJ_SP5_SHIFT)
+#define AIPS_BRD_PACRJ_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRJ_SP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP5_MASK, AIPS_PACRJ_SP5(value)))
+#define AIPS_BWR_PACRJ_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP4 field. */
+#define AIPS_RD_PACRJ_TP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP4_MASK) >> AIPS_PACRJ_TP4_SHIFT)
+#define AIPS_BRD_PACRJ_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRJ_TP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP4_MASK, AIPS_PACRJ_TP4(value)))
+#define AIPS_BWR_PACRJ_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP4 field. */
+#define AIPS_RD_PACRJ_WP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP4_MASK) >> AIPS_PACRJ_WP4_SHIFT)
+#define AIPS_BRD_PACRJ_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRJ_WP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP4_MASK, AIPS_PACRJ_WP4(value)))
+#define AIPS_BWR_PACRJ_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP4 field. */
+#define AIPS_RD_PACRJ_SP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP4_MASK) >> AIPS_PACRJ_SP4_SHIFT)
+#define AIPS_BRD_PACRJ_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRJ_SP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP4_MASK, AIPS_PACRJ_SP4(value)))
+#define AIPS_BWR_PACRJ_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP3 field. */
+#define AIPS_RD_PACRJ_TP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP3_MASK) >> AIPS_PACRJ_TP3_SHIFT)
+#define AIPS_BRD_PACRJ_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRJ_TP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP3_MASK, AIPS_PACRJ_TP3(value)))
+#define AIPS_BWR_PACRJ_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP3 field. */
+#define AIPS_RD_PACRJ_WP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP3_MASK) >> AIPS_PACRJ_WP3_SHIFT)
+#define AIPS_BRD_PACRJ_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRJ_WP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP3_MASK, AIPS_PACRJ_WP3(value)))
+#define AIPS_BWR_PACRJ_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP3 field. */
+#define AIPS_RD_PACRJ_SP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP3_MASK) >> AIPS_PACRJ_SP3_SHIFT)
+#define AIPS_BRD_PACRJ_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRJ_SP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP3_MASK, AIPS_PACRJ_SP3(value)))
+#define AIPS_BWR_PACRJ_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP2 field. */
+#define AIPS_RD_PACRJ_TP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP2_MASK) >> AIPS_PACRJ_TP2_SHIFT)
+#define AIPS_BRD_PACRJ_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRJ_TP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP2_MASK, AIPS_PACRJ_TP2(value)))
+#define AIPS_BWR_PACRJ_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP2 field. */
+#define AIPS_RD_PACRJ_WP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP2_MASK) >> AIPS_PACRJ_WP2_SHIFT)
+#define AIPS_BRD_PACRJ_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRJ_WP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP2_MASK, AIPS_PACRJ_WP2(value)))
+#define AIPS_BWR_PACRJ_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP2 field. */
+#define AIPS_RD_PACRJ_SP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP2_MASK) >> AIPS_PACRJ_SP2_SHIFT)
+#define AIPS_BRD_PACRJ_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRJ_SP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP2_MASK, AIPS_PACRJ_SP2(value)))
+#define AIPS_BWR_PACRJ_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP1 field. */
+#define AIPS_RD_PACRJ_TP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP1_MASK) >> AIPS_PACRJ_TP1_SHIFT)
+#define AIPS_BRD_PACRJ_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRJ_TP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP1_MASK, AIPS_PACRJ_TP1(value)))
+#define AIPS_BWR_PACRJ_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP1 field. */
+#define AIPS_RD_PACRJ_WP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP1_MASK) >> AIPS_PACRJ_WP1_SHIFT)
+#define AIPS_BRD_PACRJ_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRJ_WP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP1_MASK, AIPS_PACRJ_WP1(value)))
+#define AIPS_BWR_PACRJ_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP1 field. */
+#define AIPS_RD_PACRJ_SP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP1_MASK) >> AIPS_PACRJ_SP1_SHIFT)
+#define AIPS_BRD_PACRJ_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRJ_SP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP1_MASK, AIPS_PACRJ_SP1(value)))
+#define AIPS_BWR_PACRJ_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP0 field. */
+#define AIPS_RD_PACRJ_TP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP0_MASK) >> AIPS_PACRJ_TP0_SHIFT)
+#define AIPS_BRD_PACRJ_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRJ_TP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP0_MASK, AIPS_PACRJ_TP0(value)))
+#define AIPS_BWR_PACRJ_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP0 field. */
+#define AIPS_RD_PACRJ_WP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP0_MASK) >> AIPS_PACRJ_WP0_SHIFT)
+#define AIPS_BRD_PACRJ_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRJ_WP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP0_MASK, AIPS_PACRJ_WP0(value)))
+#define AIPS_BWR_PACRJ_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP0 field. */
+#define AIPS_RD_PACRJ_SP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP0_MASK) >> AIPS_PACRJ_SP0_SHIFT)
+#define AIPS_BRD_PACRJ_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRJ_SP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP0_MASK, AIPS_PACRJ_SP0(value)))
+#define AIPS_BWR_PACRJ_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRK - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRK - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRK register
+ */
+/*@{*/
+#define AIPS_RD_PACRK(base)      (AIPS_PACRK_REG(base))
+#define AIPS_WR_PACRK(base, value) (AIPS_PACRK_REG(base) = (value))
+#define AIPS_RMW_PACRK(base, mask, value) (AIPS_WR_PACRK(base, (AIPS_RD_PACRK(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) |  (value)))
+#define AIPS_CLR_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) & ~(value)))
+#define AIPS_TOG_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRK bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRK, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP7 field. */
+#define AIPS_RD_PACRK_TP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP7_MASK) >> AIPS_PACRK_TP7_SHIFT)
+#define AIPS_BRD_PACRK_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRK_TP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP7_MASK, AIPS_PACRK_TP7(value)))
+#define AIPS_BWR_PACRK_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP7 field. */
+#define AIPS_RD_PACRK_WP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP7_MASK) >> AIPS_PACRK_WP7_SHIFT)
+#define AIPS_BRD_PACRK_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRK_WP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP7_MASK, AIPS_PACRK_WP7(value)))
+#define AIPS_BWR_PACRK_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP7 field. */
+#define AIPS_RD_PACRK_SP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP7_MASK) >> AIPS_PACRK_SP7_SHIFT)
+#define AIPS_BRD_PACRK_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRK_SP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP7_MASK, AIPS_PACRK_SP7(value)))
+#define AIPS_BWR_PACRK_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP6 field. */
+#define AIPS_RD_PACRK_TP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP6_MASK) >> AIPS_PACRK_TP6_SHIFT)
+#define AIPS_BRD_PACRK_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRK_TP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP6_MASK, AIPS_PACRK_TP6(value)))
+#define AIPS_BWR_PACRK_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP6 field. */
+#define AIPS_RD_PACRK_WP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP6_MASK) >> AIPS_PACRK_WP6_SHIFT)
+#define AIPS_BRD_PACRK_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRK_WP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP6_MASK, AIPS_PACRK_WP6(value)))
+#define AIPS_BWR_PACRK_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP6 field. */
+#define AIPS_RD_PACRK_SP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP6_MASK) >> AIPS_PACRK_SP6_SHIFT)
+#define AIPS_BRD_PACRK_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRK_SP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP6_MASK, AIPS_PACRK_SP6(value)))
+#define AIPS_BWR_PACRK_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP5 field. */
+#define AIPS_RD_PACRK_TP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP5_MASK) >> AIPS_PACRK_TP5_SHIFT)
+#define AIPS_BRD_PACRK_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRK_TP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP5_MASK, AIPS_PACRK_TP5(value)))
+#define AIPS_BWR_PACRK_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP5 field. */
+#define AIPS_RD_PACRK_WP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP5_MASK) >> AIPS_PACRK_WP5_SHIFT)
+#define AIPS_BRD_PACRK_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRK_WP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP5_MASK, AIPS_PACRK_WP5(value)))
+#define AIPS_BWR_PACRK_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP5 field. */
+#define AIPS_RD_PACRK_SP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP5_MASK) >> AIPS_PACRK_SP5_SHIFT)
+#define AIPS_BRD_PACRK_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRK_SP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP5_MASK, AIPS_PACRK_SP5(value)))
+#define AIPS_BWR_PACRK_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP4 field. */
+#define AIPS_RD_PACRK_TP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP4_MASK) >> AIPS_PACRK_TP4_SHIFT)
+#define AIPS_BRD_PACRK_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRK_TP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP4_MASK, AIPS_PACRK_TP4(value)))
+#define AIPS_BWR_PACRK_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP4 field. */
+#define AIPS_RD_PACRK_WP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP4_MASK) >> AIPS_PACRK_WP4_SHIFT)
+#define AIPS_BRD_PACRK_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRK_WP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP4_MASK, AIPS_PACRK_WP4(value)))
+#define AIPS_BWR_PACRK_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP4 field. */
+#define AIPS_RD_PACRK_SP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP4_MASK) >> AIPS_PACRK_SP4_SHIFT)
+#define AIPS_BRD_PACRK_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRK_SP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP4_MASK, AIPS_PACRK_SP4(value)))
+#define AIPS_BWR_PACRK_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP3 field. */
+#define AIPS_RD_PACRK_TP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP3_MASK) >> AIPS_PACRK_TP3_SHIFT)
+#define AIPS_BRD_PACRK_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRK_TP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP3_MASK, AIPS_PACRK_TP3(value)))
+#define AIPS_BWR_PACRK_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP3 field. */
+#define AIPS_RD_PACRK_WP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP3_MASK) >> AIPS_PACRK_WP3_SHIFT)
+#define AIPS_BRD_PACRK_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRK_WP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP3_MASK, AIPS_PACRK_WP3(value)))
+#define AIPS_BWR_PACRK_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP3 field. */
+#define AIPS_RD_PACRK_SP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP3_MASK) >> AIPS_PACRK_SP3_SHIFT)
+#define AIPS_BRD_PACRK_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRK_SP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP3_MASK, AIPS_PACRK_SP3(value)))
+#define AIPS_BWR_PACRK_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP2 field. */
+#define AIPS_RD_PACRK_TP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP2_MASK) >> AIPS_PACRK_TP2_SHIFT)
+#define AIPS_BRD_PACRK_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRK_TP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP2_MASK, AIPS_PACRK_TP2(value)))
+#define AIPS_BWR_PACRK_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP2 field. */
+#define AIPS_RD_PACRK_WP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP2_MASK) >> AIPS_PACRK_WP2_SHIFT)
+#define AIPS_BRD_PACRK_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRK_WP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP2_MASK, AIPS_PACRK_WP2(value)))
+#define AIPS_BWR_PACRK_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP2 field. */
+#define AIPS_RD_PACRK_SP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP2_MASK) >> AIPS_PACRK_SP2_SHIFT)
+#define AIPS_BRD_PACRK_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRK_SP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP2_MASK, AIPS_PACRK_SP2(value)))
+#define AIPS_BWR_PACRK_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP1 field. */
+#define AIPS_RD_PACRK_TP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP1_MASK) >> AIPS_PACRK_TP1_SHIFT)
+#define AIPS_BRD_PACRK_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRK_TP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP1_MASK, AIPS_PACRK_TP1(value)))
+#define AIPS_BWR_PACRK_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP1 field. */
+#define AIPS_RD_PACRK_WP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP1_MASK) >> AIPS_PACRK_WP1_SHIFT)
+#define AIPS_BRD_PACRK_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRK_WP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP1_MASK, AIPS_PACRK_WP1(value)))
+#define AIPS_BWR_PACRK_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP1 field. */
+#define AIPS_RD_PACRK_SP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP1_MASK) >> AIPS_PACRK_SP1_SHIFT)
+#define AIPS_BRD_PACRK_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRK_SP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP1_MASK, AIPS_PACRK_SP1(value)))
+#define AIPS_BWR_PACRK_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP0 field. */
+#define AIPS_RD_PACRK_TP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP0_MASK) >> AIPS_PACRK_TP0_SHIFT)
+#define AIPS_BRD_PACRK_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRK_TP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP0_MASK, AIPS_PACRK_TP0(value)))
+#define AIPS_BWR_PACRK_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP0 field. */
+#define AIPS_RD_PACRK_WP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP0_MASK) >> AIPS_PACRK_WP0_SHIFT)
+#define AIPS_BRD_PACRK_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRK_WP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP0_MASK, AIPS_PACRK_WP0(value)))
+#define AIPS_BWR_PACRK_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP0 field. */
+#define AIPS_RD_PACRK_SP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP0_MASK) >> AIPS_PACRK_SP0_SHIFT)
+#define AIPS_BRD_PACRK_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRK_SP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP0_MASK, AIPS_PACRK_SP0(value)))
+#define AIPS_BWR_PACRK_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRL - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRL - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRL register
+ */
+/*@{*/
+#define AIPS_RD_PACRL(base)      (AIPS_PACRL_REG(base))
+#define AIPS_WR_PACRL(base, value) (AIPS_PACRL_REG(base) = (value))
+#define AIPS_RMW_PACRL(base, mask, value) (AIPS_WR_PACRL(base, (AIPS_RD_PACRL(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) |  (value)))
+#define AIPS_CLR_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) & ~(value)))
+#define AIPS_TOG_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRL bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRL, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP7 field. */
+#define AIPS_RD_PACRL_TP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP7_MASK) >> AIPS_PACRL_TP7_SHIFT)
+#define AIPS_BRD_PACRL_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRL_TP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP7_MASK, AIPS_PACRL_TP7(value)))
+#define AIPS_BWR_PACRL_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP7 field. */
+#define AIPS_RD_PACRL_WP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP7_MASK) >> AIPS_PACRL_WP7_SHIFT)
+#define AIPS_BRD_PACRL_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRL_WP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP7_MASK, AIPS_PACRL_WP7(value)))
+#define AIPS_BWR_PACRL_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP7 field. */
+#define AIPS_RD_PACRL_SP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP7_MASK) >> AIPS_PACRL_SP7_SHIFT)
+#define AIPS_BRD_PACRL_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRL_SP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP7_MASK, AIPS_PACRL_SP7(value)))
+#define AIPS_BWR_PACRL_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP6 field. */
+#define AIPS_RD_PACRL_TP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP6_MASK) >> AIPS_PACRL_TP6_SHIFT)
+#define AIPS_BRD_PACRL_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRL_TP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP6_MASK, AIPS_PACRL_TP6(value)))
+#define AIPS_BWR_PACRL_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP6 field. */
+#define AIPS_RD_PACRL_WP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP6_MASK) >> AIPS_PACRL_WP6_SHIFT)
+#define AIPS_BRD_PACRL_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRL_WP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP6_MASK, AIPS_PACRL_WP6(value)))
+#define AIPS_BWR_PACRL_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP6 field. */
+#define AIPS_RD_PACRL_SP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP6_MASK) >> AIPS_PACRL_SP6_SHIFT)
+#define AIPS_BRD_PACRL_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRL_SP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP6_MASK, AIPS_PACRL_SP6(value)))
+#define AIPS_BWR_PACRL_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP5 field. */
+#define AIPS_RD_PACRL_TP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP5_MASK) >> AIPS_PACRL_TP5_SHIFT)
+#define AIPS_BRD_PACRL_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRL_TP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP5_MASK, AIPS_PACRL_TP5(value)))
+#define AIPS_BWR_PACRL_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP5 field. */
+#define AIPS_RD_PACRL_WP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP5_MASK) >> AIPS_PACRL_WP5_SHIFT)
+#define AIPS_BRD_PACRL_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRL_WP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP5_MASK, AIPS_PACRL_WP5(value)))
+#define AIPS_BWR_PACRL_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP5 field. */
+#define AIPS_RD_PACRL_SP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP5_MASK) >> AIPS_PACRL_SP5_SHIFT)
+#define AIPS_BRD_PACRL_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRL_SP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP5_MASK, AIPS_PACRL_SP5(value)))
+#define AIPS_BWR_PACRL_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP4 field. */
+#define AIPS_RD_PACRL_TP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP4_MASK) >> AIPS_PACRL_TP4_SHIFT)
+#define AIPS_BRD_PACRL_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRL_TP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP4_MASK, AIPS_PACRL_TP4(value)))
+#define AIPS_BWR_PACRL_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP4 field. */
+#define AIPS_RD_PACRL_WP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP4_MASK) >> AIPS_PACRL_WP4_SHIFT)
+#define AIPS_BRD_PACRL_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRL_WP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP4_MASK, AIPS_PACRL_WP4(value)))
+#define AIPS_BWR_PACRL_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP4 field. */
+#define AIPS_RD_PACRL_SP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP4_MASK) >> AIPS_PACRL_SP4_SHIFT)
+#define AIPS_BRD_PACRL_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRL_SP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP4_MASK, AIPS_PACRL_SP4(value)))
+#define AIPS_BWR_PACRL_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP3 field. */
+#define AIPS_RD_PACRL_TP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP3_MASK) >> AIPS_PACRL_TP3_SHIFT)
+#define AIPS_BRD_PACRL_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRL_TP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP3_MASK, AIPS_PACRL_TP3(value)))
+#define AIPS_BWR_PACRL_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP3 field. */
+#define AIPS_RD_PACRL_WP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP3_MASK) >> AIPS_PACRL_WP3_SHIFT)
+#define AIPS_BRD_PACRL_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRL_WP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP3_MASK, AIPS_PACRL_WP3(value)))
+#define AIPS_BWR_PACRL_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP3 field. */
+#define AIPS_RD_PACRL_SP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP3_MASK) >> AIPS_PACRL_SP3_SHIFT)
+#define AIPS_BRD_PACRL_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRL_SP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP3_MASK, AIPS_PACRL_SP3(value)))
+#define AIPS_BWR_PACRL_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP2 field. */
+#define AIPS_RD_PACRL_TP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP2_MASK) >> AIPS_PACRL_TP2_SHIFT)
+#define AIPS_BRD_PACRL_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRL_TP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP2_MASK, AIPS_PACRL_TP2(value)))
+#define AIPS_BWR_PACRL_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP2 field. */
+#define AIPS_RD_PACRL_WP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP2_MASK) >> AIPS_PACRL_WP2_SHIFT)
+#define AIPS_BRD_PACRL_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRL_WP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP2_MASK, AIPS_PACRL_WP2(value)))
+#define AIPS_BWR_PACRL_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP2 field. */
+#define AIPS_RD_PACRL_SP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP2_MASK) >> AIPS_PACRL_SP2_SHIFT)
+#define AIPS_BRD_PACRL_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRL_SP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP2_MASK, AIPS_PACRL_SP2(value)))
+#define AIPS_BWR_PACRL_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP1 field. */
+#define AIPS_RD_PACRL_TP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP1_MASK) >> AIPS_PACRL_TP1_SHIFT)
+#define AIPS_BRD_PACRL_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRL_TP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP1_MASK, AIPS_PACRL_TP1(value)))
+#define AIPS_BWR_PACRL_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP1 field. */
+#define AIPS_RD_PACRL_WP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP1_MASK) >> AIPS_PACRL_WP1_SHIFT)
+#define AIPS_BRD_PACRL_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRL_WP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP1_MASK, AIPS_PACRL_WP1(value)))
+#define AIPS_BWR_PACRL_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP1 field. */
+#define AIPS_RD_PACRL_SP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP1_MASK) >> AIPS_PACRL_SP1_SHIFT)
+#define AIPS_BRD_PACRL_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRL_SP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP1_MASK, AIPS_PACRL_SP1(value)))
+#define AIPS_BWR_PACRL_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP0 field. */
+#define AIPS_RD_PACRL_TP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP0_MASK) >> AIPS_PACRL_TP0_SHIFT)
+#define AIPS_BRD_PACRL_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRL_TP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP0_MASK, AIPS_PACRL_TP0(value)))
+#define AIPS_BWR_PACRL_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP0 field. */
+#define AIPS_RD_PACRL_WP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP0_MASK) >> AIPS_PACRL_WP0_SHIFT)
+#define AIPS_BRD_PACRL_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRL_WP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP0_MASK, AIPS_PACRL_WP0(value)))
+#define AIPS_BWR_PACRL_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP0 field. */
+#define AIPS_RD_PACRL_SP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP0_MASK) >> AIPS_PACRL_SP0_SHIFT)
+#define AIPS_BRD_PACRL_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRL_SP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP0_MASK, AIPS_PACRL_SP0(value)))
+#define AIPS_BWR_PACRL_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRM - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRM - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRM register
+ */
+/*@{*/
+#define AIPS_RD_PACRM(base)      (AIPS_PACRM_REG(base))
+#define AIPS_WR_PACRM(base, value) (AIPS_PACRM_REG(base) = (value))
+#define AIPS_RMW_PACRM(base, mask, value) (AIPS_WR_PACRM(base, (AIPS_RD_PACRM(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) |  (value)))
+#define AIPS_CLR_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) & ~(value)))
+#define AIPS_TOG_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRM bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRM, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP7 field. */
+#define AIPS_RD_PACRM_TP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP7_MASK) >> AIPS_PACRM_TP7_SHIFT)
+#define AIPS_BRD_PACRM_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRM_TP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP7_MASK, AIPS_PACRM_TP7(value)))
+#define AIPS_BWR_PACRM_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP7 field. */
+#define AIPS_RD_PACRM_WP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP7_MASK) >> AIPS_PACRM_WP7_SHIFT)
+#define AIPS_BRD_PACRM_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRM_WP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP7_MASK, AIPS_PACRM_WP7(value)))
+#define AIPS_BWR_PACRM_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP7 field. */
+#define AIPS_RD_PACRM_SP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP7_MASK) >> AIPS_PACRM_SP7_SHIFT)
+#define AIPS_BRD_PACRM_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRM_SP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP7_MASK, AIPS_PACRM_SP7(value)))
+#define AIPS_BWR_PACRM_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP6 field. */
+#define AIPS_RD_PACRM_TP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP6_MASK) >> AIPS_PACRM_TP6_SHIFT)
+#define AIPS_BRD_PACRM_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRM_TP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP6_MASK, AIPS_PACRM_TP6(value)))
+#define AIPS_BWR_PACRM_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP6 field. */
+#define AIPS_RD_PACRM_WP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP6_MASK) >> AIPS_PACRM_WP6_SHIFT)
+#define AIPS_BRD_PACRM_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRM_WP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP6_MASK, AIPS_PACRM_WP6(value)))
+#define AIPS_BWR_PACRM_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP6 field. */
+#define AIPS_RD_PACRM_SP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP6_MASK) >> AIPS_PACRM_SP6_SHIFT)
+#define AIPS_BRD_PACRM_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRM_SP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP6_MASK, AIPS_PACRM_SP6(value)))
+#define AIPS_BWR_PACRM_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP5 field. */
+#define AIPS_RD_PACRM_TP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP5_MASK) >> AIPS_PACRM_TP5_SHIFT)
+#define AIPS_BRD_PACRM_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRM_TP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP5_MASK, AIPS_PACRM_TP5(value)))
+#define AIPS_BWR_PACRM_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP5 field. */
+#define AIPS_RD_PACRM_WP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP5_MASK) >> AIPS_PACRM_WP5_SHIFT)
+#define AIPS_BRD_PACRM_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRM_WP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP5_MASK, AIPS_PACRM_WP5(value)))
+#define AIPS_BWR_PACRM_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP5 field. */
+#define AIPS_RD_PACRM_SP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP5_MASK) >> AIPS_PACRM_SP5_SHIFT)
+#define AIPS_BRD_PACRM_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRM_SP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP5_MASK, AIPS_PACRM_SP5(value)))
+#define AIPS_BWR_PACRM_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP4 field. */
+#define AIPS_RD_PACRM_TP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP4_MASK) >> AIPS_PACRM_TP4_SHIFT)
+#define AIPS_BRD_PACRM_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRM_TP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP4_MASK, AIPS_PACRM_TP4(value)))
+#define AIPS_BWR_PACRM_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP4 field. */
+#define AIPS_RD_PACRM_WP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP4_MASK) >> AIPS_PACRM_WP4_SHIFT)
+#define AIPS_BRD_PACRM_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRM_WP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP4_MASK, AIPS_PACRM_WP4(value)))
+#define AIPS_BWR_PACRM_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP4 field. */
+#define AIPS_RD_PACRM_SP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP4_MASK) >> AIPS_PACRM_SP4_SHIFT)
+#define AIPS_BRD_PACRM_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRM_SP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP4_MASK, AIPS_PACRM_SP4(value)))
+#define AIPS_BWR_PACRM_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP3 field. */
+#define AIPS_RD_PACRM_TP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP3_MASK) >> AIPS_PACRM_TP3_SHIFT)
+#define AIPS_BRD_PACRM_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRM_TP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP3_MASK, AIPS_PACRM_TP3(value)))
+#define AIPS_BWR_PACRM_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP3 field. */
+#define AIPS_RD_PACRM_WP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP3_MASK) >> AIPS_PACRM_WP3_SHIFT)
+#define AIPS_BRD_PACRM_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRM_WP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP3_MASK, AIPS_PACRM_WP3(value)))
+#define AIPS_BWR_PACRM_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP3 field. */
+#define AIPS_RD_PACRM_SP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP3_MASK) >> AIPS_PACRM_SP3_SHIFT)
+#define AIPS_BRD_PACRM_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRM_SP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP3_MASK, AIPS_PACRM_SP3(value)))
+#define AIPS_BWR_PACRM_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP2 field. */
+#define AIPS_RD_PACRM_TP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP2_MASK) >> AIPS_PACRM_TP2_SHIFT)
+#define AIPS_BRD_PACRM_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRM_TP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP2_MASK, AIPS_PACRM_TP2(value)))
+#define AIPS_BWR_PACRM_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP2 field. */
+#define AIPS_RD_PACRM_WP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP2_MASK) >> AIPS_PACRM_WP2_SHIFT)
+#define AIPS_BRD_PACRM_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRM_WP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP2_MASK, AIPS_PACRM_WP2(value)))
+#define AIPS_BWR_PACRM_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP2 field. */
+#define AIPS_RD_PACRM_SP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP2_MASK) >> AIPS_PACRM_SP2_SHIFT)
+#define AIPS_BRD_PACRM_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRM_SP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP2_MASK, AIPS_PACRM_SP2(value)))
+#define AIPS_BWR_PACRM_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP1 field. */
+#define AIPS_RD_PACRM_TP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP1_MASK) >> AIPS_PACRM_TP1_SHIFT)
+#define AIPS_BRD_PACRM_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRM_TP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP1_MASK, AIPS_PACRM_TP1(value)))
+#define AIPS_BWR_PACRM_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP1 field. */
+#define AIPS_RD_PACRM_WP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP1_MASK) >> AIPS_PACRM_WP1_SHIFT)
+#define AIPS_BRD_PACRM_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRM_WP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP1_MASK, AIPS_PACRM_WP1(value)))
+#define AIPS_BWR_PACRM_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP1 field. */
+#define AIPS_RD_PACRM_SP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP1_MASK) >> AIPS_PACRM_SP1_SHIFT)
+#define AIPS_BRD_PACRM_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRM_SP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP1_MASK, AIPS_PACRM_SP1(value)))
+#define AIPS_BWR_PACRM_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP0 field. */
+#define AIPS_RD_PACRM_TP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP0_MASK) >> AIPS_PACRM_TP0_SHIFT)
+#define AIPS_BRD_PACRM_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRM_TP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP0_MASK, AIPS_PACRM_TP0(value)))
+#define AIPS_BWR_PACRM_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP0 field. */
+#define AIPS_RD_PACRM_WP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP0_MASK) >> AIPS_PACRM_WP0_SHIFT)
+#define AIPS_BRD_PACRM_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRM_WP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP0_MASK, AIPS_PACRM_WP0(value)))
+#define AIPS_BWR_PACRM_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP0 field. */
+#define AIPS_RD_PACRM_SP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP0_MASK) >> AIPS_PACRM_SP0_SHIFT)
+#define AIPS_BRD_PACRM_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRM_SP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP0_MASK, AIPS_PACRM_SP0(value)))
+#define AIPS_BWR_PACRM_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRN - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRN - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRN register
+ */
+/*@{*/
+#define AIPS_RD_PACRN(base)      (AIPS_PACRN_REG(base))
+#define AIPS_WR_PACRN(base, value) (AIPS_PACRN_REG(base) = (value))
+#define AIPS_RMW_PACRN(base, mask, value) (AIPS_WR_PACRN(base, (AIPS_RD_PACRN(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) |  (value)))
+#define AIPS_CLR_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) & ~(value)))
+#define AIPS_TOG_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRN bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRN, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP7 field. */
+#define AIPS_RD_PACRN_TP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP7_MASK) >> AIPS_PACRN_TP7_SHIFT)
+#define AIPS_BRD_PACRN_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRN_TP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP7_MASK, AIPS_PACRN_TP7(value)))
+#define AIPS_BWR_PACRN_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP7 field. */
+#define AIPS_RD_PACRN_WP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP7_MASK) >> AIPS_PACRN_WP7_SHIFT)
+#define AIPS_BRD_PACRN_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRN_WP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP7_MASK, AIPS_PACRN_WP7(value)))
+#define AIPS_BWR_PACRN_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP7 field. */
+#define AIPS_RD_PACRN_SP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP7_MASK) >> AIPS_PACRN_SP7_SHIFT)
+#define AIPS_BRD_PACRN_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRN_SP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP7_MASK, AIPS_PACRN_SP7(value)))
+#define AIPS_BWR_PACRN_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP6 field. */
+#define AIPS_RD_PACRN_TP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP6_MASK) >> AIPS_PACRN_TP6_SHIFT)
+#define AIPS_BRD_PACRN_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRN_TP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP6_MASK, AIPS_PACRN_TP6(value)))
+#define AIPS_BWR_PACRN_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP6 field. */
+#define AIPS_RD_PACRN_WP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP6_MASK) >> AIPS_PACRN_WP6_SHIFT)
+#define AIPS_BRD_PACRN_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRN_WP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP6_MASK, AIPS_PACRN_WP6(value)))
+#define AIPS_BWR_PACRN_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP6 field. */
+#define AIPS_RD_PACRN_SP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP6_MASK) >> AIPS_PACRN_SP6_SHIFT)
+#define AIPS_BRD_PACRN_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRN_SP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP6_MASK, AIPS_PACRN_SP6(value)))
+#define AIPS_BWR_PACRN_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP5 field. */
+#define AIPS_RD_PACRN_TP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP5_MASK) >> AIPS_PACRN_TP5_SHIFT)
+#define AIPS_BRD_PACRN_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRN_TP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP5_MASK, AIPS_PACRN_TP5(value)))
+#define AIPS_BWR_PACRN_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP5 field. */
+#define AIPS_RD_PACRN_WP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP5_MASK) >> AIPS_PACRN_WP5_SHIFT)
+#define AIPS_BRD_PACRN_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRN_WP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP5_MASK, AIPS_PACRN_WP5(value)))
+#define AIPS_BWR_PACRN_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP5 field. */
+#define AIPS_RD_PACRN_SP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP5_MASK) >> AIPS_PACRN_SP5_SHIFT)
+#define AIPS_BRD_PACRN_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRN_SP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP5_MASK, AIPS_PACRN_SP5(value)))
+#define AIPS_BWR_PACRN_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP4 field. */
+#define AIPS_RD_PACRN_TP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP4_MASK) >> AIPS_PACRN_TP4_SHIFT)
+#define AIPS_BRD_PACRN_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRN_TP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP4_MASK, AIPS_PACRN_TP4(value)))
+#define AIPS_BWR_PACRN_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP4 field. */
+#define AIPS_RD_PACRN_WP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP4_MASK) >> AIPS_PACRN_WP4_SHIFT)
+#define AIPS_BRD_PACRN_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRN_WP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP4_MASK, AIPS_PACRN_WP4(value)))
+#define AIPS_BWR_PACRN_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP4 field. */
+#define AIPS_RD_PACRN_SP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP4_MASK) >> AIPS_PACRN_SP4_SHIFT)
+#define AIPS_BRD_PACRN_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRN_SP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP4_MASK, AIPS_PACRN_SP4(value)))
+#define AIPS_BWR_PACRN_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP3 field. */
+#define AIPS_RD_PACRN_TP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP3_MASK) >> AIPS_PACRN_TP3_SHIFT)
+#define AIPS_BRD_PACRN_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRN_TP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP3_MASK, AIPS_PACRN_TP3(value)))
+#define AIPS_BWR_PACRN_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP3 field. */
+#define AIPS_RD_PACRN_WP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP3_MASK) >> AIPS_PACRN_WP3_SHIFT)
+#define AIPS_BRD_PACRN_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRN_WP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP3_MASK, AIPS_PACRN_WP3(value)))
+#define AIPS_BWR_PACRN_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP3 field. */
+#define AIPS_RD_PACRN_SP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP3_MASK) >> AIPS_PACRN_SP3_SHIFT)
+#define AIPS_BRD_PACRN_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRN_SP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP3_MASK, AIPS_PACRN_SP3(value)))
+#define AIPS_BWR_PACRN_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP2 field. */
+#define AIPS_RD_PACRN_TP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP2_MASK) >> AIPS_PACRN_TP2_SHIFT)
+#define AIPS_BRD_PACRN_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRN_TP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP2_MASK, AIPS_PACRN_TP2(value)))
+#define AIPS_BWR_PACRN_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP2 field. */
+#define AIPS_RD_PACRN_WP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP2_MASK) >> AIPS_PACRN_WP2_SHIFT)
+#define AIPS_BRD_PACRN_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRN_WP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP2_MASK, AIPS_PACRN_WP2(value)))
+#define AIPS_BWR_PACRN_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP2 field. */
+#define AIPS_RD_PACRN_SP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP2_MASK) >> AIPS_PACRN_SP2_SHIFT)
+#define AIPS_BRD_PACRN_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRN_SP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP2_MASK, AIPS_PACRN_SP2(value)))
+#define AIPS_BWR_PACRN_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP1 field. */
+#define AIPS_RD_PACRN_TP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP1_MASK) >> AIPS_PACRN_TP1_SHIFT)
+#define AIPS_BRD_PACRN_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRN_TP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP1_MASK, AIPS_PACRN_TP1(value)))
+#define AIPS_BWR_PACRN_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP1 field. */
+#define AIPS_RD_PACRN_WP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP1_MASK) >> AIPS_PACRN_WP1_SHIFT)
+#define AIPS_BRD_PACRN_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRN_WP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP1_MASK, AIPS_PACRN_WP1(value)))
+#define AIPS_BWR_PACRN_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP1 field. */
+#define AIPS_RD_PACRN_SP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP1_MASK) >> AIPS_PACRN_SP1_SHIFT)
+#define AIPS_BRD_PACRN_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRN_SP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP1_MASK, AIPS_PACRN_SP1(value)))
+#define AIPS_BWR_PACRN_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP0 field. */
+#define AIPS_RD_PACRN_TP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP0_MASK) >> AIPS_PACRN_TP0_SHIFT)
+#define AIPS_BRD_PACRN_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRN_TP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP0_MASK, AIPS_PACRN_TP0(value)))
+#define AIPS_BWR_PACRN_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP0 field. */
+#define AIPS_RD_PACRN_WP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP0_MASK) >> AIPS_PACRN_WP0_SHIFT)
+#define AIPS_BRD_PACRN_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRN_WP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP0_MASK, AIPS_PACRN_WP0(value)))
+#define AIPS_BWR_PACRN_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP0 field. */
+#define AIPS_RD_PACRN_SP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP0_MASK) >> AIPS_PACRN_SP0_SHIFT)
+#define AIPS_BRD_PACRN_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRN_SP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP0_MASK, AIPS_PACRN_SP0(value)))
+#define AIPS_BWR_PACRN_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRO - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRO - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRO register
+ */
+/*@{*/
+#define AIPS_RD_PACRO(base)      (AIPS_PACRO_REG(base))
+#define AIPS_WR_PACRO(base, value) (AIPS_PACRO_REG(base) = (value))
+#define AIPS_RMW_PACRO(base, mask, value) (AIPS_WR_PACRO(base, (AIPS_RD_PACRO(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) |  (value)))
+#define AIPS_CLR_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) & ~(value)))
+#define AIPS_TOG_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRO bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRO, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP7 field. */
+#define AIPS_RD_PACRO_TP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP7_MASK) >> AIPS_PACRO_TP7_SHIFT)
+#define AIPS_BRD_PACRO_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRO_TP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP7_MASK, AIPS_PACRO_TP7(value)))
+#define AIPS_BWR_PACRO_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP7 field. */
+#define AIPS_RD_PACRO_WP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP7_MASK) >> AIPS_PACRO_WP7_SHIFT)
+#define AIPS_BRD_PACRO_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRO_WP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP7_MASK, AIPS_PACRO_WP7(value)))
+#define AIPS_BWR_PACRO_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP7 field. */
+#define AIPS_RD_PACRO_SP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP7_MASK) >> AIPS_PACRO_SP7_SHIFT)
+#define AIPS_BRD_PACRO_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRO_SP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP7_MASK, AIPS_PACRO_SP7(value)))
+#define AIPS_BWR_PACRO_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP6 field. */
+#define AIPS_RD_PACRO_TP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP6_MASK) >> AIPS_PACRO_TP6_SHIFT)
+#define AIPS_BRD_PACRO_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRO_TP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP6_MASK, AIPS_PACRO_TP6(value)))
+#define AIPS_BWR_PACRO_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP6 field. */
+#define AIPS_RD_PACRO_WP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP6_MASK) >> AIPS_PACRO_WP6_SHIFT)
+#define AIPS_BRD_PACRO_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRO_WP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP6_MASK, AIPS_PACRO_WP6(value)))
+#define AIPS_BWR_PACRO_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP6 field. */
+#define AIPS_RD_PACRO_SP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP6_MASK) >> AIPS_PACRO_SP6_SHIFT)
+#define AIPS_BRD_PACRO_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRO_SP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP6_MASK, AIPS_PACRO_SP6(value)))
+#define AIPS_BWR_PACRO_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP5 field. */
+#define AIPS_RD_PACRO_TP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP5_MASK) >> AIPS_PACRO_TP5_SHIFT)
+#define AIPS_BRD_PACRO_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRO_TP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP5_MASK, AIPS_PACRO_TP5(value)))
+#define AIPS_BWR_PACRO_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP5 field. */
+#define AIPS_RD_PACRO_WP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP5_MASK) >> AIPS_PACRO_WP5_SHIFT)
+#define AIPS_BRD_PACRO_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRO_WP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP5_MASK, AIPS_PACRO_WP5(value)))
+#define AIPS_BWR_PACRO_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP5 field. */
+#define AIPS_RD_PACRO_SP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP5_MASK) >> AIPS_PACRO_SP5_SHIFT)
+#define AIPS_BRD_PACRO_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRO_SP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP5_MASK, AIPS_PACRO_SP5(value)))
+#define AIPS_BWR_PACRO_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP4 field. */
+#define AIPS_RD_PACRO_TP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP4_MASK) >> AIPS_PACRO_TP4_SHIFT)
+#define AIPS_BRD_PACRO_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRO_TP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP4_MASK, AIPS_PACRO_TP4(value)))
+#define AIPS_BWR_PACRO_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP4 field. */
+#define AIPS_RD_PACRO_WP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP4_MASK) >> AIPS_PACRO_WP4_SHIFT)
+#define AIPS_BRD_PACRO_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRO_WP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP4_MASK, AIPS_PACRO_WP4(value)))
+#define AIPS_BWR_PACRO_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP4 field. */
+#define AIPS_RD_PACRO_SP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP4_MASK) >> AIPS_PACRO_SP4_SHIFT)
+#define AIPS_BRD_PACRO_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRO_SP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP4_MASK, AIPS_PACRO_SP4(value)))
+#define AIPS_BWR_PACRO_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP3 field. */
+#define AIPS_RD_PACRO_TP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP3_MASK) >> AIPS_PACRO_TP3_SHIFT)
+#define AIPS_BRD_PACRO_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRO_TP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP3_MASK, AIPS_PACRO_TP3(value)))
+#define AIPS_BWR_PACRO_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP3 field. */
+#define AIPS_RD_PACRO_WP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP3_MASK) >> AIPS_PACRO_WP3_SHIFT)
+#define AIPS_BRD_PACRO_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRO_WP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP3_MASK, AIPS_PACRO_WP3(value)))
+#define AIPS_BWR_PACRO_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP3 field. */
+#define AIPS_RD_PACRO_SP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP3_MASK) >> AIPS_PACRO_SP3_SHIFT)
+#define AIPS_BRD_PACRO_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRO_SP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP3_MASK, AIPS_PACRO_SP3(value)))
+#define AIPS_BWR_PACRO_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP2 field. */
+#define AIPS_RD_PACRO_TP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP2_MASK) >> AIPS_PACRO_TP2_SHIFT)
+#define AIPS_BRD_PACRO_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRO_TP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP2_MASK, AIPS_PACRO_TP2(value)))
+#define AIPS_BWR_PACRO_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP2 field. */
+#define AIPS_RD_PACRO_WP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP2_MASK) >> AIPS_PACRO_WP2_SHIFT)
+#define AIPS_BRD_PACRO_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRO_WP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP2_MASK, AIPS_PACRO_WP2(value)))
+#define AIPS_BWR_PACRO_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP2 field. */
+#define AIPS_RD_PACRO_SP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP2_MASK) >> AIPS_PACRO_SP2_SHIFT)
+#define AIPS_BRD_PACRO_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRO_SP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP2_MASK, AIPS_PACRO_SP2(value)))
+#define AIPS_BWR_PACRO_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP1 field. */
+#define AIPS_RD_PACRO_TP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP1_MASK) >> AIPS_PACRO_TP1_SHIFT)
+#define AIPS_BRD_PACRO_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRO_TP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP1_MASK, AIPS_PACRO_TP1(value)))
+#define AIPS_BWR_PACRO_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP1 field. */
+#define AIPS_RD_PACRO_WP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP1_MASK) >> AIPS_PACRO_WP1_SHIFT)
+#define AIPS_BRD_PACRO_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRO_WP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP1_MASK, AIPS_PACRO_WP1(value)))
+#define AIPS_BWR_PACRO_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP1 field. */
+#define AIPS_RD_PACRO_SP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP1_MASK) >> AIPS_PACRO_SP1_SHIFT)
+#define AIPS_BRD_PACRO_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRO_SP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP1_MASK, AIPS_PACRO_SP1(value)))
+#define AIPS_BWR_PACRO_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP0 field. */
+#define AIPS_RD_PACRO_TP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP0_MASK) >> AIPS_PACRO_TP0_SHIFT)
+#define AIPS_BRD_PACRO_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRO_TP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP0_MASK, AIPS_PACRO_TP0(value)))
+#define AIPS_BWR_PACRO_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP0 field. */
+#define AIPS_RD_PACRO_WP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP0_MASK) >> AIPS_PACRO_WP0_SHIFT)
+#define AIPS_BRD_PACRO_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRO_WP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP0_MASK, AIPS_PACRO_WP0(value)))
+#define AIPS_BWR_PACRO_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP0 field. */
+#define AIPS_RD_PACRO_SP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP0_MASK) >> AIPS_PACRO_SP0_SHIFT)
+#define AIPS_BRD_PACRO_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRO_SP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP0_MASK, AIPS_PACRO_SP0(value)))
+#define AIPS_BWR_PACRO_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRP - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRP - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRP register
+ */
+/*@{*/
+#define AIPS_RD_PACRP(base)      (AIPS_PACRP_REG(base))
+#define AIPS_WR_PACRP(base, value) (AIPS_PACRP_REG(base) = (value))
+#define AIPS_RMW_PACRP(base, mask, value) (AIPS_WR_PACRP(base, (AIPS_RD_PACRP(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) |  (value)))
+#define AIPS_CLR_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) & ~(value)))
+#define AIPS_TOG_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRP bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRP, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP7 field. */
+#define AIPS_RD_PACRP_TP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP7_MASK) >> AIPS_PACRP_TP7_SHIFT)
+#define AIPS_BRD_PACRP_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRP_TP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP7_MASK, AIPS_PACRP_TP7(value)))
+#define AIPS_BWR_PACRP_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP7 field. */
+#define AIPS_RD_PACRP_WP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP7_MASK) >> AIPS_PACRP_WP7_SHIFT)
+#define AIPS_BRD_PACRP_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRP_WP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP7_MASK, AIPS_PACRP_WP7(value)))
+#define AIPS_BWR_PACRP_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP7 field. */
+#define AIPS_RD_PACRP_SP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP7_MASK) >> AIPS_PACRP_SP7_SHIFT)
+#define AIPS_BRD_PACRP_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRP_SP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP7_MASK, AIPS_PACRP_SP7(value)))
+#define AIPS_BWR_PACRP_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP6 field. */
+#define AIPS_RD_PACRP_TP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP6_MASK) >> AIPS_PACRP_TP6_SHIFT)
+#define AIPS_BRD_PACRP_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRP_TP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP6_MASK, AIPS_PACRP_TP6(value)))
+#define AIPS_BWR_PACRP_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP6 field. */
+#define AIPS_RD_PACRP_WP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP6_MASK) >> AIPS_PACRP_WP6_SHIFT)
+#define AIPS_BRD_PACRP_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRP_WP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP6_MASK, AIPS_PACRP_WP6(value)))
+#define AIPS_BWR_PACRP_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP6 field. */
+#define AIPS_RD_PACRP_SP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP6_MASK) >> AIPS_PACRP_SP6_SHIFT)
+#define AIPS_BRD_PACRP_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRP_SP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP6_MASK, AIPS_PACRP_SP6(value)))
+#define AIPS_BWR_PACRP_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP5 field. */
+#define AIPS_RD_PACRP_TP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP5_MASK) >> AIPS_PACRP_TP5_SHIFT)
+#define AIPS_BRD_PACRP_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRP_TP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP5_MASK, AIPS_PACRP_TP5(value)))
+#define AIPS_BWR_PACRP_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP5 field. */
+#define AIPS_RD_PACRP_WP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP5_MASK) >> AIPS_PACRP_WP5_SHIFT)
+#define AIPS_BRD_PACRP_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRP_WP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP5_MASK, AIPS_PACRP_WP5(value)))
+#define AIPS_BWR_PACRP_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP5 field. */
+#define AIPS_RD_PACRP_SP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP5_MASK) >> AIPS_PACRP_SP5_SHIFT)
+#define AIPS_BRD_PACRP_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRP_SP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP5_MASK, AIPS_PACRP_SP5(value)))
+#define AIPS_BWR_PACRP_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP4 field. */
+#define AIPS_RD_PACRP_TP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP4_MASK) >> AIPS_PACRP_TP4_SHIFT)
+#define AIPS_BRD_PACRP_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRP_TP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP4_MASK, AIPS_PACRP_TP4(value)))
+#define AIPS_BWR_PACRP_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP4 field. */
+#define AIPS_RD_PACRP_WP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP4_MASK) >> AIPS_PACRP_WP4_SHIFT)
+#define AIPS_BRD_PACRP_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRP_WP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP4_MASK, AIPS_PACRP_WP4(value)))
+#define AIPS_BWR_PACRP_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP4 field. */
+#define AIPS_RD_PACRP_SP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP4_MASK) >> AIPS_PACRP_SP4_SHIFT)
+#define AIPS_BRD_PACRP_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRP_SP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP4_MASK, AIPS_PACRP_SP4(value)))
+#define AIPS_BWR_PACRP_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP3 field. */
+#define AIPS_RD_PACRP_TP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP3_MASK) >> AIPS_PACRP_TP3_SHIFT)
+#define AIPS_BRD_PACRP_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRP_TP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP3_MASK, AIPS_PACRP_TP3(value)))
+#define AIPS_BWR_PACRP_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP3 field. */
+#define AIPS_RD_PACRP_WP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP3_MASK) >> AIPS_PACRP_WP3_SHIFT)
+#define AIPS_BRD_PACRP_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRP_WP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP3_MASK, AIPS_PACRP_WP3(value)))
+#define AIPS_BWR_PACRP_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP3 field. */
+#define AIPS_RD_PACRP_SP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP3_MASK) >> AIPS_PACRP_SP3_SHIFT)
+#define AIPS_BRD_PACRP_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRP_SP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP3_MASK, AIPS_PACRP_SP3(value)))
+#define AIPS_BWR_PACRP_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP2 field. */
+#define AIPS_RD_PACRP_TP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP2_MASK) >> AIPS_PACRP_TP2_SHIFT)
+#define AIPS_BRD_PACRP_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRP_TP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP2_MASK, AIPS_PACRP_TP2(value)))
+#define AIPS_BWR_PACRP_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP2 field. */
+#define AIPS_RD_PACRP_WP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP2_MASK) >> AIPS_PACRP_WP2_SHIFT)
+#define AIPS_BRD_PACRP_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRP_WP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP2_MASK, AIPS_PACRP_WP2(value)))
+#define AIPS_BWR_PACRP_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP2 field. */
+#define AIPS_RD_PACRP_SP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP2_MASK) >> AIPS_PACRP_SP2_SHIFT)
+#define AIPS_BRD_PACRP_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRP_SP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP2_MASK, AIPS_PACRP_SP2(value)))
+#define AIPS_BWR_PACRP_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP1 field. */
+#define AIPS_RD_PACRP_TP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP1_MASK) >> AIPS_PACRP_TP1_SHIFT)
+#define AIPS_BRD_PACRP_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRP_TP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP1_MASK, AIPS_PACRP_TP1(value)))
+#define AIPS_BWR_PACRP_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP1 field. */
+#define AIPS_RD_PACRP_WP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP1_MASK) >> AIPS_PACRP_WP1_SHIFT)
+#define AIPS_BRD_PACRP_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRP_WP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP1_MASK, AIPS_PACRP_WP1(value)))
+#define AIPS_BWR_PACRP_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP1 field. */
+#define AIPS_RD_PACRP_SP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP1_MASK) >> AIPS_PACRP_SP1_SHIFT)
+#define AIPS_BRD_PACRP_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRP_SP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP1_MASK, AIPS_PACRP_SP1(value)))
+#define AIPS_BWR_PACRP_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP0 field. */
+#define AIPS_RD_PACRP_TP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP0_MASK) >> AIPS_PACRP_TP0_SHIFT)
+#define AIPS_BRD_PACRP_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRP_TP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP0_MASK, AIPS_PACRP_TP0(value)))
+#define AIPS_BWR_PACRP_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP0 field. */
+#define AIPS_RD_PACRP_WP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP0_MASK) >> AIPS_PACRP_WP0_SHIFT)
+#define AIPS_BRD_PACRP_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRP_WP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP0_MASK, AIPS_PACRP_WP0(value)))
+#define AIPS_BWR_PACRP_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP0 field. */
+#define AIPS_RD_PACRP_SP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP0_MASK) >> AIPS_PACRP_SP0_SHIFT)
+#define AIPS_BRD_PACRP_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRP_SP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP0_MASK, AIPS_PACRP_SP0(value)))
+#define AIPS_BWR_PACRP_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRU - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRU - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44000000U
+ *
+ * PACRU defines the access levels for the two global spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRU register
+ */
+/*@{*/
+#define AIPS_RD_PACRU(base)      (AIPS_PACRU_REG(base))
+#define AIPS_WR_PACRU(base, value) (AIPS_PACRU_REG(base) = (value))
+#define AIPS_RMW_PACRU(base, mask, value) (AIPS_WR_PACRU(base, (AIPS_RD_PACRU(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) |  (value)))
+#define AIPS_CLR_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) & ~(value)))
+#define AIPS_TOG_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRU bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRU, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_TP1 field. */
+#define AIPS_RD_PACRU_TP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_TP1_MASK) >> AIPS_PACRU_TP1_SHIFT)
+#define AIPS_BRD_PACRU_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRU_TP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_TP1_MASK, AIPS_PACRU_TP1(value)))
+#define AIPS_BWR_PACRU_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_WP1 field. */
+#define AIPS_RD_PACRU_WP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_WP1_MASK) >> AIPS_PACRU_WP1_SHIFT)
+#define AIPS_BRD_PACRU_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRU_WP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_WP1_MASK, AIPS_PACRU_WP1(value)))
+#define AIPS_BWR_PACRU_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_SP1 field. */
+#define AIPS_RD_PACRU_SP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_SP1_MASK) >> AIPS_PACRU_SP1_SHIFT)
+#define AIPS_BRD_PACRU_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRU_SP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_SP1_MASK, AIPS_PACRU_SP1(value)))
+#define AIPS_BWR_PACRU_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_TP0 field. */
+#define AIPS_RD_PACRU_TP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_TP0_MASK) >> AIPS_PACRU_TP0_SHIFT)
+#define AIPS_BRD_PACRU_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRU_TP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_TP0_MASK, AIPS_PACRU_TP0(value)))
+#define AIPS_BWR_PACRU_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_WP0 field. */
+#define AIPS_RD_PACRU_WP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_WP0_MASK) >> AIPS_PACRU_WP0_SHIFT)
+#define AIPS_BRD_PACRU_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRU_WP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_WP0_MASK, AIPS_PACRU_WP0(value)))
+#define AIPS_BWR_PACRU_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_SP0 field. */
+#define AIPS_RD_PACRU_SP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_SP0_MASK) >> AIPS_PACRU_SP0_SHIFT)
+#define AIPS_BRD_PACRU_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRU_SP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_SP0_MASK, AIPS_PACRU_SP0(value)))
+#define AIPS_BWR_PACRU_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP0_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 AXBS
+ *
+ * Crossbar switch
+ *
+ * Registers defined in this header file:
+ * - AXBS_PRS - Priority Registers Slave
+ * - AXBS_CRS - Control Register
+ * - AXBS_MGPCR0 - Master General Purpose Control Register
+ * - AXBS_MGPCR1 - Master General Purpose Control Register
+ * - AXBS_MGPCR2 - Master General Purpose Control Register
+ * - AXBS_MGPCR3 - Master General Purpose Control Register
+ * - AXBS_MGPCR4 - Master General Purpose Control Register
+ * - AXBS_MGPCR5 - Master General Purpose Control Register
+ */
+
+#define AXBS_INSTANCE_COUNT (1U) /*!< Number of instances of the AXBS module. */
+#define AXBS_IDX (0U) /*!< Instance number for AXBS. */
+
+/*******************************************************************************
+ * AXBS_PRS - Priority Registers Slave
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_PRS - Priority Registers Slave (RW)
+ *
+ * Reset value: 0x00543210U
+ *
+ * The priority registers (PRSn) set the priority of each master port on a per
+ * slave port basis and reside in each slave port. The priority register can be
+ * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
+ * register can only be read; attempts to write to it have no effect on PRSn and
+ * result in a bus-error response to the master initiating the write. Two available
+ * masters must not be programmed with the same priority level. Attempts to
+ * program two or more masters with the same priority level result in a bus-error
+ * response and the PRSn is not updated. Valid values for the Mn priority fields
+ * depend on which masters are available on the chip. This information can be found in
+ * the chip-specific information for the crossbar. If the chip contains less
+ * than five masters, values 0 to 3 are valid. Writing other values will result in
+ * an error. If the chip contains five or more masters, valid values are 0 to n-1,
+ * where n is the number of masters attached to the AXBS module. Other values
+ * will result in an error.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_PRS register
+ */
+/*@{*/
+#define AXBS_RD_PRS(base, index) (AXBS_PRS_REG(base, index))
+#define AXBS_WR_PRS(base, index, value) (AXBS_PRS_REG(base, index) = (value))
+#define AXBS_RMW_PRS(base, index, mask, value) (AXBS_WR_PRS(base, index, (AXBS_RD_PRS(base, index) & ~(mask)) | (value)))
+#define AXBS_SET_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) |  (value)))
+#define AXBS_CLR_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) & ~(value)))
+#define AXBS_TOG_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_PRS bitfields
+ */
+
+/*!
+ * @name Register AXBS_PRS, field M0[2:0] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M0 field. */
+#define AXBS_RD_PRS_M0(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M0_MASK) >> AXBS_PRS_M0_SHIFT)
+#define AXBS_BRD_PRS_M0(base, index) (AXBS_RD_PRS_M0(base, index))
+
+/*! @brief Set the M0 field to a new value. */
+#define AXBS_WR_PRS_M0(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M0_MASK, AXBS_PRS_M0(value)))
+#define AXBS_BWR_PRS_M0(base, index, value) (AXBS_WR_PRS_M0(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M1[6:4] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M1 field. */
+#define AXBS_RD_PRS_M1(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M1_MASK) >> AXBS_PRS_M1_SHIFT)
+#define AXBS_BRD_PRS_M1(base, index) (AXBS_RD_PRS_M1(base, index))
+
+/*! @brief Set the M1 field to a new value. */
+#define AXBS_WR_PRS_M1(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M1_MASK, AXBS_PRS_M1(value)))
+#define AXBS_BWR_PRS_M1(base, index, value) (AXBS_WR_PRS_M1(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M2[10:8] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M2 field. */
+#define AXBS_RD_PRS_M2(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M2_MASK) >> AXBS_PRS_M2_SHIFT)
+#define AXBS_BRD_PRS_M2(base, index) (AXBS_RD_PRS_M2(base, index))
+
+/*! @brief Set the M2 field to a new value. */
+#define AXBS_WR_PRS_M2(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M2_MASK, AXBS_PRS_M2(value)))
+#define AXBS_BWR_PRS_M2(base, index, value) (AXBS_WR_PRS_M2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M3[14:12] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M3 field. */
+#define AXBS_RD_PRS_M3(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M3_MASK) >> AXBS_PRS_M3_SHIFT)
+#define AXBS_BRD_PRS_M3(base, index) (AXBS_RD_PRS_M3(base, index))
+
+/*! @brief Set the M3 field to a new value. */
+#define AXBS_WR_PRS_M3(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M3_MASK, AXBS_PRS_M3(value)))
+#define AXBS_BWR_PRS_M3(base, index, value) (AXBS_WR_PRS_M3(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M4[18:16] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M4 field. */
+#define AXBS_RD_PRS_M4(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M4_MASK) >> AXBS_PRS_M4_SHIFT)
+#define AXBS_BRD_PRS_M4(base, index) (AXBS_RD_PRS_M4(base, index))
+
+/*! @brief Set the M4 field to a new value. */
+#define AXBS_WR_PRS_M4(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M4_MASK, AXBS_PRS_M4(value)))
+#define AXBS_BWR_PRS_M4(base, index, value) (AXBS_WR_PRS_M4(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M5[22:20] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M5 field. */
+#define AXBS_RD_PRS_M5(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M5_MASK) >> AXBS_PRS_M5_SHIFT)
+#define AXBS_BRD_PRS_M5(base, index) (AXBS_RD_PRS_M5(base, index))
+
+/*! @brief Set the M5 field to a new value. */
+#define AXBS_WR_PRS_M5(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M5_MASK, AXBS_PRS_M5(value)))
+#define AXBS_BWR_PRS_M5(base, index, value) (AXBS_WR_PRS_M5(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_CRS - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_CRS - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers control several features of each slave port and must be
+ * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
+ * attempts to write to it have no effect and result in an error response.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_CRS register
+ */
+/*@{*/
+#define AXBS_RD_CRS(base, index) (AXBS_CRS_REG(base, index))
+#define AXBS_WR_CRS(base, index, value) (AXBS_CRS_REG(base, index) = (value))
+#define AXBS_RMW_CRS(base, index, mask, value) (AXBS_WR_CRS(base, index, (AXBS_RD_CRS(base, index) & ~(mask)) | (value)))
+#define AXBS_SET_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) |  (value)))
+#define AXBS_CLR_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) & ~(value)))
+#define AXBS_TOG_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_CRS bitfields
+ */
+
+/*!
+ * @name Register AXBS_CRS, field PARK[2:0] (RW)
+ *
+ * Determines which master port the current slave port parks on when no masters
+ * are actively making requests and the PCTL bits are cleared. Select only master
+ * ports that are present on the chip. Otherwise, undefined behavior might occur.
+ *
+ * Values:
+ * - 0b000 - Park on master port M0
+ * - 0b001 - Park on master port M1
+ * - 0b010 - Park on master port M2
+ * - 0b011 - Park on master port M3
+ * - 0b100 - Park on master port M4
+ * - 0b101 - Park on master port M5
+ * - 0b110 - Park on master port M6
+ * - 0b111 - Park on master port M7
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_PARK field. */
+#define AXBS_RD_CRS_PARK(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_PARK_MASK) >> AXBS_CRS_PARK_SHIFT)
+#define AXBS_BRD_CRS_PARK(base, index) (AXBS_RD_CRS_PARK(base, index))
+
+/*! @brief Set the PARK field to a new value. */
+#define AXBS_WR_CRS_PARK(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_PARK_MASK, AXBS_CRS_PARK(value)))
+#define AXBS_BWR_CRS_PARK(base, index, value) (AXBS_WR_CRS_PARK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field PCTL[5:4] (RW)
+ *
+ * Determines the slave port's parking control. The low-power park feature
+ * results in an overall power savings if the slave port is not saturated. However,
+ * this forces an extra latency clock when any master tries to access the slave
+ * port while not in use because it is not parked on any master.
+ *
+ * Values:
+ * - 0b00 - When no master makes a request, the arbiter parks the slave port on
+ *     the master port defined by the PARK field
+ * - 0b01 - When no master makes a request, the arbiter parks the slave port on
+ *     the last master to be in control of the slave port
+ * - 0b10 - When no master makes a request, the slave port is not parked on a
+ *     master and the arbiter drives all outputs to a constant safe state
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_PCTL field. */
+#define AXBS_RD_CRS_PCTL(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_PCTL_MASK) >> AXBS_CRS_PCTL_SHIFT)
+#define AXBS_BRD_CRS_PCTL(base, index) (AXBS_RD_CRS_PCTL(base, index))
+
+/*! @brief Set the PCTL field to a new value. */
+#define AXBS_WR_CRS_PCTL(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_PCTL_MASK, AXBS_CRS_PCTL(value)))
+#define AXBS_BWR_CRS_PCTL(base, index, value) (AXBS_WR_CRS_PCTL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field ARB[9:8] (RW)
+ *
+ * Selects the arbitration policy for the slave port.
+ *
+ * Values:
+ * - 0b00 - Fixed priority
+ * - 0b01 - Round-robin, or rotating, priority
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_ARB field. */
+#define AXBS_RD_CRS_ARB(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_ARB_MASK) >> AXBS_CRS_ARB_SHIFT)
+#define AXBS_BRD_CRS_ARB(base, index) (AXBS_RD_CRS_ARB(base, index))
+
+/*! @brief Set the ARB field to a new value. */
+#define AXBS_WR_CRS_ARB(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_ARB_MASK, AXBS_CRS_ARB(value)))
+#define AXBS_BWR_CRS_ARB(base, index, value) (AXBS_WR_CRS_ARB(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field HLP[30] (RW)
+ *
+ * Sets the initial arbitration priority for low power mode requests . Setting
+ * this bit will not affect the request for low power mode from attaining highest
+ * priority once it has control of the slave ports.
+ *
+ * Values:
+ * - 0b0 - The low power mode request has the highest priority for arbitration
+ *     on this slave port
+ * - 0b1 - The low power mode request has the lowest initial priority for
+ *     arbitration on this slave port
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_HLP field. */
+#define AXBS_RD_CRS_HLP(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_HLP_MASK) >> AXBS_CRS_HLP_SHIFT)
+#define AXBS_BRD_CRS_HLP(base, index) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_HLP_SHIFT))
+
+/*! @brief Set the HLP field to a new value. */
+#define AXBS_WR_CRS_HLP(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_HLP_MASK, AXBS_CRS_HLP(value)))
+#define AXBS_BWR_CRS_HLP(base, index, value) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_HLP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field RO[31] (RW)
+ *
+ * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
+ * only a hardware reset clears it.
+ *
+ * Values:
+ * - 0b0 - The slave port's registers are writeable
+ * - 0b1 - The slave port's registers are read-only and cannot be written.
+ *     Attempted writes have no effect on the registers and result in a bus error
+ *     response.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_RO field. */
+#define AXBS_RD_CRS_RO(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_RO_MASK) >> AXBS_CRS_RO_SHIFT)
+#define AXBS_BRD_CRS_RO(base, index) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_RO_SHIFT))
+
+/*! @brief Set the RO field to a new value. */
+#define AXBS_WR_CRS_RO(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_RO_MASK, AXBS_CRS_RO(value)))
+#define AXBS_BWR_CRS_RO(base, index, value) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_RO_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR0 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR0 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR0 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR0(base)     (AXBS_MGPCR0_REG(base))
+#define AXBS_WR_MGPCR0(base, value) (AXBS_MGPCR0_REG(base) = (value))
+#define AXBS_RMW_MGPCR0(base, mask, value) (AXBS_WR_MGPCR0(base, (AXBS_RD_MGPCR0(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) |  (value)))
+#define AXBS_CLR_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) & ~(value)))
+#define AXBS_TOG_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR0 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR0_AULB field. */
+#define AXBS_RD_MGPCR0_AULB(base) ((AXBS_MGPCR0_REG(base) & AXBS_MGPCR0_AULB_MASK) >> AXBS_MGPCR0_AULB_SHIFT)
+#define AXBS_BRD_MGPCR0_AULB(base) (AXBS_RD_MGPCR0_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR0_AULB(base, value) (AXBS_RMW_MGPCR0(base, AXBS_MGPCR0_AULB_MASK, AXBS_MGPCR0_AULB(value)))
+#define AXBS_BWR_MGPCR0_AULB(base, value) (AXBS_WR_MGPCR0_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR1 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR1 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR1 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR1(base)     (AXBS_MGPCR1_REG(base))
+#define AXBS_WR_MGPCR1(base, value) (AXBS_MGPCR1_REG(base) = (value))
+#define AXBS_RMW_MGPCR1(base, mask, value) (AXBS_WR_MGPCR1(base, (AXBS_RD_MGPCR1(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) |  (value)))
+#define AXBS_CLR_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) & ~(value)))
+#define AXBS_TOG_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR1 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR1_AULB field. */
+#define AXBS_RD_MGPCR1_AULB(base) ((AXBS_MGPCR1_REG(base) & AXBS_MGPCR1_AULB_MASK) >> AXBS_MGPCR1_AULB_SHIFT)
+#define AXBS_BRD_MGPCR1_AULB(base) (AXBS_RD_MGPCR1_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR1_AULB(base, value) (AXBS_RMW_MGPCR1(base, AXBS_MGPCR1_AULB_MASK, AXBS_MGPCR1_AULB(value)))
+#define AXBS_BWR_MGPCR1_AULB(base, value) (AXBS_WR_MGPCR1_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR2 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR2 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR2 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR2(base)     (AXBS_MGPCR2_REG(base))
+#define AXBS_WR_MGPCR2(base, value) (AXBS_MGPCR2_REG(base) = (value))
+#define AXBS_RMW_MGPCR2(base, mask, value) (AXBS_WR_MGPCR2(base, (AXBS_RD_MGPCR2(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) |  (value)))
+#define AXBS_CLR_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) & ~(value)))
+#define AXBS_TOG_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR2 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR2_AULB field. */
+#define AXBS_RD_MGPCR2_AULB(base) ((AXBS_MGPCR2_REG(base) & AXBS_MGPCR2_AULB_MASK) >> AXBS_MGPCR2_AULB_SHIFT)
+#define AXBS_BRD_MGPCR2_AULB(base) (AXBS_RD_MGPCR2_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR2_AULB(base, value) (AXBS_RMW_MGPCR2(base, AXBS_MGPCR2_AULB_MASK, AXBS_MGPCR2_AULB(value)))
+#define AXBS_BWR_MGPCR2_AULB(base, value) (AXBS_WR_MGPCR2_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR3 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR3 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR3 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR3(base)     (AXBS_MGPCR3_REG(base))
+#define AXBS_WR_MGPCR3(base, value) (AXBS_MGPCR3_REG(base) = (value))
+#define AXBS_RMW_MGPCR3(base, mask, value) (AXBS_WR_MGPCR3(base, (AXBS_RD_MGPCR3(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) |  (value)))
+#define AXBS_CLR_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) & ~(value)))
+#define AXBS_TOG_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR3 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR3_AULB field. */
+#define AXBS_RD_MGPCR3_AULB(base) ((AXBS_MGPCR3_REG(base) & AXBS_MGPCR3_AULB_MASK) >> AXBS_MGPCR3_AULB_SHIFT)
+#define AXBS_BRD_MGPCR3_AULB(base) (AXBS_RD_MGPCR3_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR3_AULB(base, value) (AXBS_RMW_MGPCR3(base, AXBS_MGPCR3_AULB_MASK, AXBS_MGPCR3_AULB(value)))
+#define AXBS_BWR_MGPCR3_AULB(base, value) (AXBS_WR_MGPCR3_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR4 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR4 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR4 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR4(base)     (AXBS_MGPCR4_REG(base))
+#define AXBS_WR_MGPCR4(base, value) (AXBS_MGPCR4_REG(base) = (value))
+#define AXBS_RMW_MGPCR4(base, mask, value) (AXBS_WR_MGPCR4(base, (AXBS_RD_MGPCR4(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) |  (value)))
+#define AXBS_CLR_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) & ~(value)))
+#define AXBS_TOG_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR4 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR4_AULB field. */
+#define AXBS_RD_MGPCR4_AULB(base) ((AXBS_MGPCR4_REG(base) & AXBS_MGPCR4_AULB_MASK) >> AXBS_MGPCR4_AULB_SHIFT)
+#define AXBS_BRD_MGPCR4_AULB(base) (AXBS_RD_MGPCR4_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR4_AULB(base, value) (AXBS_RMW_MGPCR4(base, AXBS_MGPCR4_AULB_MASK, AXBS_MGPCR4_AULB(value)))
+#define AXBS_BWR_MGPCR4_AULB(base, value) (AXBS_WR_MGPCR4_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR5 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR5 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR5 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR5(base)     (AXBS_MGPCR5_REG(base))
+#define AXBS_WR_MGPCR5(base, value) (AXBS_MGPCR5_REG(base) = (value))
+#define AXBS_RMW_MGPCR5(base, mask, value) (AXBS_WR_MGPCR5(base, (AXBS_RD_MGPCR5(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) |  (value)))
+#define AXBS_CLR_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) & ~(value)))
+#define AXBS_TOG_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR5 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR5_AULB field. */
+#define AXBS_RD_MGPCR5_AULB(base) ((AXBS_MGPCR5_REG(base) & AXBS_MGPCR5_AULB_MASK) >> AXBS_MGPCR5_AULB_SHIFT)
+#define AXBS_BRD_MGPCR5_AULB(base) (AXBS_RD_MGPCR5_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR5_AULB(base, value) (AXBS_RMW_MGPCR5(base, AXBS_MGPCR5_AULB_MASK, AXBS_MGPCR5_AULB(value)))
+#define AXBS_BWR_MGPCR5_AULB(base, value) (AXBS_WR_MGPCR5_AULB(base, value))
+/*@}*/
+
+/*
+ * MK64F12 CAN
+ *
+ * Flex Controller Area Network module
+ *
+ * Registers defined in this header file:
+ * - CAN_MCR - Module Configuration Register
+ * - CAN_CTRL1 - Control 1 register
+ * - CAN_TIMER - Free Running Timer
+ * - CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ * - CAN_RX14MASK - Rx 14 Mask register
+ * - CAN_RX15MASK - Rx 15 Mask register
+ * - CAN_ECR - Error Counter
+ * - CAN_ESR1 - Error and Status 1 register
+ * - CAN_IMASK1 - Interrupt Masks 1 register
+ * - CAN_IFLAG1 - Interrupt Flags 1 register
+ * - CAN_CTRL2 - Control 2 register
+ * - CAN_ESR2 - Error and Status 2 register
+ * - CAN_CRCR - CRC Register
+ * - CAN_RXFGMASK - Rx FIFO Global Mask register
+ * - CAN_RXFIR - Rx FIFO Information Register
+ * - CAN_CS - Message Buffer 0 CS Register
+ * - CAN_ID - Message Buffer 0 ID Register
+ * - CAN_WORD0 - Message Buffer 0 WORD0 Register
+ * - CAN_WORD1 - Message Buffer 0 WORD1 Register
+ * - CAN_RXIMR - Rx Individual Mask Registers
+ */
+
+#define CAN_INSTANCE_COUNT (1U) /*!< Number of instances of the CAN module. */
+#define CAN0_IDX (0U) /*!< Instance number for CAN0. */
+
+/*******************************************************************************
+ * CAN_MCR - Module Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0xD890000FU
+ *
+ * This register defines global system configurations, such as the module
+ * operation modes and the maximum message buffer configuration.
+ */
+/*!
+ * @name Constants and macros for entire CAN_MCR register
+ */
+/*@{*/
+#define CAN_RD_MCR(base)         (CAN_MCR_REG(base))
+#define CAN_WR_MCR(base, value)  (CAN_MCR_REG(base) = (value))
+#define CAN_RMW_MCR(base, mask, value) (CAN_WR_MCR(base, (CAN_RD_MCR(base) & ~(mask)) | (value)))
+#define CAN_SET_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) |  (value)))
+#define CAN_CLR_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) & ~(value)))
+#define CAN_TOG_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_MCR bitfields
+ */
+
+/*!
+ * @name Register CAN_MCR, field MAXMB[6:0] (RW)
+ *
+ * This 7-bit field defines the number of the last Message Buffers that will
+ * take part in the matching and arbitration processes. The reset value (0x0F) is
+ * equivalent to a 16 MB configuration. This field can be written only in Freeze
+ * mode because it is blocked by hardware in other modes. Number of the last MB =
+ * MAXMB MAXMB must be programmed with a value smaller than the parameter
+ * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
+ * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
+ * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
+ * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
+ * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
+ * Matching Timing").
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_MAXMB field. */
+#define CAN_RD_MCR_MAXMB(base) ((CAN_MCR_REG(base) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT)
+#define CAN_BRD_MCR_MAXMB(base) (CAN_RD_MCR_MAXMB(base))
+
+/*! @brief Set the MAXMB field to a new value. */
+#define CAN_WR_MCR_MAXMB(base, value) (CAN_RMW_MCR(base, CAN_MCR_MAXMB_MASK, CAN_MCR_MAXMB(value)))
+#define CAN_BWR_MCR_MAXMB(base, value) (CAN_WR_MCR_MAXMB(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field IDAM[9:8] (RW)
+ *
+ * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
+ * elements. Note that all elements of the table are configured at the same time by this
+ * field (they are all the same format). See Section "Rx FIFO Structure". This
+ * field can be written only in Freeze mode because it is blocked by hardware in
+ * other modes.
+ *
+ * Values:
+ * - 0b00 - Format A: One full ID (standard and extended) per ID Filter Table
+ *     element.
+ * - 0b01 - Format B: Two full standard IDs or two partial 14-bit (standard and
+ *     extended) IDs per ID Filter Table element.
+ * - 0b10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table
+ *     element.
+ * - 0b11 - Format D: All frames rejected.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_IDAM field. */
+#define CAN_RD_MCR_IDAM(base) ((CAN_MCR_REG(base) & CAN_MCR_IDAM_MASK) >> CAN_MCR_IDAM_SHIFT)
+#define CAN_BRD_MCR_IDAM(base) (CAN_RD_MCR_IDAM(base))
+
+/*! @brief Set the IDAM field to a new value. */
+#define CAN_WR_MCR_IDAM(base, value) (CAN_RMW_MCR(base, CAN_MCR_IDAM_MASK, CAN_MCR_IDAM(value)))
+#define CAN_BWR_MCR_IDAM(base, value) (CAN_WR_MCR_IDAM(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field AEN[12] (RW)
+ *
+ * This bit is supplied for backwards compatibility with legacy applications.
+ * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
+ * safe procedure for aborting a pending transmission, so that no frame is sent in
+ * the CAN bus without notification. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
+ * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
+ * used for updating Mailboxes configured for transmission. Writing the Abort code
+ * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Abort disabled.
+ * - 0b1 - Abort enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_AEN field. */
+#define CAN_RD_MCR_AEN(base) ((CAN_MCR_REG(base) & CAN_MCR_AEN_MASK) >> CAN_MCR_AEN_SHIFT)
+#define CAN_BRD_MCR_AEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_AEN_SHIFT))
+
+/*! @brief Set the AEN field to a new value. */
+#define CAN_WR_MCR_AEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_AEN_MASK, CAN_MCR_AEN(value)))
+#define CAN_BWR_MCR_AEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_AEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field LPRIOEN[13] (RW)
+ *
+ * This bit is provided for backwards compatibility with legacy applications. It
+ * controls whether the local priority feature is enabled or not. It is used to
+ * expand the ID used during the arbitration process. With this expanded ID
+ * concept, the arbitration process is done based on the full 32-bit word, but the
+ * actual transmitted ID still has 11-bit for standard frames and 29-bit for
+ * extended frames. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Local Priority disabled.
+ * - 0b1 - Local Priority enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_LPRIOEN field. */
+#define CAN_RD_MCR_LPRIOEN(base) ((CAN_MCR_REG(base) & CAN_MCR_LPRIOEN_MASK) >> CAN_MCR_LPRIOEN_SHIFT)
+#define CAN_BRD_MCR_LPRIOEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPRIOEN_SHIFT))
+
+/*! @brief Set the LPRIOEN field to a new value. */
+#define CAN_WR_MCR_LPRIOEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_LPRIOEN_MASK, CAN_MCR_LPRIOEN(value)))
+#define CAN_BWR_MCR_LPRIOEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPRIOEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field IRMQ[16] (RW)
+ *
+ * This bit indicates whether Rx matching process will be based either on
+ * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
+ * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Individual Rx masking and queue feature are disabled. For backward
+ *     compatibility with legacy applications, the reading of C/S word locks the MB
+ *     even if it is EMPTY.
+ * - 0b1 - Individual Rx masking and queue feature are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_IRMQ field. */
+#define CAN_RD_MCR_IRMQ(base) ((CAN_MCR_REG(base) & CAN_MCR_IRMQ_MASK) >> CAN_MCR_IRMQ_SHIFT)
+#define CAN_BRD_MCR_IRMQ(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_IRMQ_SHIFT))
+
+/*! @brief Set the IRMQ field to a new value. */
+#define CAN_WR_MCR_IRMQ(base, value) (CAN_RMW_MCR(base, CAN_MCR_IRMQ_MASK, CAN_MCR_IRMQ(value)))
+#define CAN_BWR_MCR_IRMQ(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_IRMQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SRXDIS[17] (RW)
+ *
+ * This bit defines whether FlexCAN is allowed to receive frames transmitted by
+ * itself. If this bit is asserted, frames transmitted by the module will not be
+ * stored in any MB, regardless if the MB is programmed with an ID that matches
+ * the transmitted frame, and no interrupt flag or interrupt signal will be
+ * generated due to the frame reception. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Self reception enabled.
+ * - 0b1 - Self reception disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SRXDIS field. */
+#define CAN_RD_MCR_SRXDIS(base) ((CAN_MCR_REG(base) & CAN_MCR_SRXDIS_MASK) >> CAN_MCR_SRXDIS_SHIFT)
+#define CAN_BRD_MCR_SRXDIS(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SRXDIS_SHIFT))
+
+/*! @brief Set the SRXDIS field to a new value. */
+#define CAN_WR_MCR_SRXDIS(base, value) (CAN_RMW_MCR(base, CAN_MCR_SRXDIS_MASK, CAN_MCR_SRXDIS(value)))
+#define CAN_BWR_MCR_SRXDIS(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SRXDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WAKSRC[19] (RW)
+ *
+ * This bit defines whether the integrated low-pass filter is applied to protect
+ * the Rx CAN input from spurious wake up. This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ * - 0b1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WAKSRC field. */
+#define CAN_RD_MCR_WAKSRC(base) ((CAN_MCR_REG(base) & CAN_MCR_WAKSRC_MASK) >> CAN_MCR_WAKSRC_SHIFT)
+#define CAN_BRD_MCR_WAKSRC(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKSRC_SHIFT))
+
+/*! @brief Set the WAKSRC field to a new value. */
+#define CAN_WR_MCR_WAKSRC(base, value) (CAN_RMW_MCR(base, CAN_MCR_WAKSRC_MASK, CAN_MCR_WAKSRC(value)))
+#define CAN_BWR_MCR_WAKSRC(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field LPMACK[20] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
+ * mode , Stop mode ). A low-power mode cannot be entered until all current
+ * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
+ * to know when FlexCAN has actually entered low power mode. LPMACK will be
+ * asserted within 180 CAN bits from the low-power mode request by the CPU, and
+ * negated within 2 CAN bits after the low-power mode request removal (see Section
+ * "Protocol Timing").
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not in a low-power mode.
+ * - 0b1 - FlexCAN is in a low-power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_LPMACK field. */
+#define CAN_RD_MCR_LPMACK(base) ((CAN_MCR_REG(base) & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT)
+#define CAN_BRD_MCR_LPMACK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPMACK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WRNEN[21] (RW)
+ *
+ * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
+ * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
+ * RWRNINT flags will always be zero, independent of the values of the error
+ * counters, and no warning interrupt will ever be generated. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
+ *     error counters.
+ * - 0b1 - TWRNINT and RWRNINT bits are set when the respective error counter
+ *     transitions from less than 96 to greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WRNEN field. */
+#define CAN_RD_MCR_WRNEN(base) ((CAN_MCR_REG(base) & CAN_MCR_WRNEN_MASK) >> CAN_MCR_WRNEN_SHIFT)
+#define CAN_BRD_MCR_WRNEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WRNEN_SHIFT))
+
+/*! @brief Set the WRNEN field to a new value. */
+#define CAN_WR_MCR_WRNEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_WRNEN_MASK, CAN_MCR_WRNEN(value)))
+#define CAN_BWR_MCR_WRNEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WRNEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SLFWAK[22] (RW)
+ *
+ * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
+ * other than Disable mode. When this feature is enabled, the FlexCAN module
+ * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
+ * If a wake up event is detected during Stop mode, then FlexCAN generates, if
+ * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
+ * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
+ * low-power mode other than Disable mode, this bit cannot be written as it is
+ * blocked by hardware.
+ *
+ * Values:
+ * - 0b0 - FlexCAN Self Wake Up feature is disabled.
+ * - 0b1 - FlexCAN Self Wake Up feature is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SLFWAK field. */
+#define CAN_RD_MCR_SLFWAK(base) ((CAN_MCR_REG(base) & CAN_MCR_SLFWAK_MASK) >> CAN_MCR_SLFWAK_SHIFT)
+#define CAN_BRD_MCR_SLFWAK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SLFWAK_SHIFT))
+
+/*! @brief Set the SLFWAK field to a new value. */
+#define CAN_WR_MCR_SLFWAK(base, value) (CAN_RMW_MCR(base, CAN_MCR_SLFWAK_MASK, CAN_MCR_SLFWAK(value)))
+#define CAN_BWR_MCR_SLFWAK(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SLFWAK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SUPV[23] (RW)
+ *
+ * This bit configures the FlexCAN to be either in Supervisor or User mode. The
+ * registers affected by this bit are marked as S/U in the Access Type column of
+ * the module memory map. Reset value of this bit is 1, so the affected registers
+ * start with Supervisor access allowance only . This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
+ *     Unrestricted accesses .
+ * - 0b1 - FlexCAN is in Supervisor mode. Affected registers allow only
+ *     Supervisor access. Unrestricted access behaves as though the access was done to an
+ *     unimplemented register location .
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SUPV field. */
+#define CAN_RD_MCR_SUPV(base) ((CAN_MCR_REG(base) & CAN_MCR_SUPV_MASK) >> CAN_MCR_SUPV_SHIFT)
+#define CAN_BRD_MCR_SUPV(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SUPV_SHIFT))
+
+/*! @brief Set the SUPV field to a new value. */
+#define CAN_WR_MCR_SUPV(base, value) (CAN_RMW_MCR(base, CAN_MCR_SUPV_MASK, CAN_MCR_SUPV(value)))
+#define CAN_BWR_MCR_SUPV(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SUPV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field FRZACK[24] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
+ * is stopped. The Freeze mode request cannot be granted until current
+ * transmission or reception processes have finished. Therefore the software can poll the
+ * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
+ * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
+ * running again. If Freeze mode is requested while FlexCAN is in a low power
+ * mode, then the FRZACK bit will be set only when the low-power mode is exited.
+ * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
+ * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
+ * mode request removal (see Section "Protocol Timing").
+ *
+ * Values:
+ * - 0b0 - FlexCAN not in Freeze mode, prescaler running.
+ * - 0b1 - FlexCAN in Freeze mode, prescaler stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_FRZACK field. */
+#define CAN_RD_MCR_FRZACK(base) ((CAN_MCR_REG(base) & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)
+#define CAN_BRD_MCR_FRZACK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZACK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SOFTRST[25] (RW)
+ *
+ * When this bit is asserted, FlexCAN resets its internal state machines and
+ * some of the memory mapped registers. The following registers are reset: MCR
+ * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
+ * CRCR. Configuration registers that control the interface to the CAN bus are
+ * not affected by soft reset. The following registers are unaffected: CTRL1,
+ * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
+ * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
+ * writes to the MCR Register, but it is also asserted when global soft reset is
+ * requested at MCU level . Because soft reset is synchronous and has to follow a
+ * request/acknowledge procedure across clock domains, it may take some time to
+ * fully propagate its effect. The SOFTRST bit remains asserted while reset is
+ * pending, and is automatically negated when reset completes. Therefore, software can
+ * poll this bit to know when the soft reset has completed. Soft reset cannot be
+ * applied while clocks are shut down in a low power mode. The module should be
+ * first removed from low power mode, and then soft reset can be applied.
+ *
+ * Values:
+ * - 0b0 - No reset request.
+ * - 0b1 - Resets the registers affected by soft reset.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SOFTRST field. */
+#define CAN_RD_MCR_SOFTRST(base) ((CAN_MCR_REG(base) & CAN_MCR_SOFTRST_MASK) >> CAN_MCR_SOFTRST_SHIFT)
+#define CAN_BRD_MCR_SOFTRST(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SOFTRST_SHIFT))
+
+/*! @brief Set the SOFTRST field to a new value. */
+#define CAN_WR_MCR_SOFTRST(base, value) (CAN_RMW_MCR(base, CAN_MCR_SOFTRST_MASK, CAN_MCR_SOFTRST(value)))
+#define CAN_BWR_MCR_SOFTRST(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SOFTRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WAKMSK[26] (RW)
+ *
+ * This bit enables the Wake Up Interrupt generation under Self Wake Up
+ * mechanism.
+ *
+ * Values:
+ * - 0b0 - Wake Up Interrupt is disabled.
+ * - 0b1 - Wake Up Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WAKMSK field. */
+#define CAN_RD_MCR_WAKMSK(base) ((CAN_MCR_REG(base) & CAN_MCR_WAKMSK_MASK) >> CAN_MCR_WAKMSK_SHIFT)
+#define CAN_BRD_MCR_WAKMSK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKMSK_SHIFT))
+
+/*! @brief Set the WAKMSK field to a new value. */
+#define CAN_WR_MCR_WAKMSK(base, value) (CAN_RMW_MCR(base, CAN_MCR_WAKMSK_MASK, CAN_MCR_WAKMSK(value)))
+#define CAN_BWR_MCR_WAKMSK(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field NOTRDY[27] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
+ * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN module is either in Normal mode, Listen-Only mode or
+ *     Loop-Back mode.
+ * - 0b1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_NOTRDY field. */
+#define CAN_RD_MCR_NOTRDY(base) ((CAN_MCR_REG(base) & CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT)
+#define CAN_BRD_MCR_NOTRDY(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_NOTRDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field HALT[28] (RW)
+ *
+ * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
+ * should clear it after initializing the Message Buffers and Control Register. No
+ * reception or transmission is performed by FlexCAN before this bit is cleared.
+ * Freeze mode cannot be entered while FlexCAN is in a low power mode.
+ *
+ * Values:
+ * - 0b0 - No Freeze mode request.
+ * - 0b1 - Enters Freeze mode if the FRZ bit is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_HALT field. */
+#define CAN_RD_MCR_HALT(base) ((CAN_MCR_REG(base) & CAN_MCR_HALT_MASK) >> CAN_MCR_HALT_SHIFT)
+#define CAN_BRD_MCR_HALT(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define CAN_WR_MCR_HALT(base, value) (CAN_RMW_MCR(base, CAN_MCR_HALT_MASK, CAN_MCR_HALT(value)))
+#define CAN_BWR_MCR_HALT(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field RFEN[29] (RW)
+ *
+ * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
+ * set, MBs 0 to 5 cannot be used for normal reception and transmission because
+ * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
+ * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
+ * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
+ * minimum number of peripheral clocks per CAN bit as described in the table
+ * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
+ * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Rx FIFO not enabled.
+ * - 0b1 - Rx FIFO enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_RFEN field. */
+#define CAN_RD_MCR_RFEN(base) ((CAN_MCR_REG(base) & CAN_MCR_RFEN_MASK) >> CAN_MCR_RFEN_SHIFT)
+#define CAN_BRD_MCR_RFEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_RFEN_SHIFT))
+
+/*! @brief Set the RFEN field to a new value. */
+#define CAN_WR_MCR_RFEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_RFEN_MASK, CAN_MCR_RFEN(value)))
+#define CAN_BWR_MCR_RFEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_RFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field FRZ[30] (RW)
+ *
+ * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
+ * Register is set or when Debug mode is requested at MCU level . When FRZ is
+ * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
+ * FlexCAN to exit from Freeze mode.
+ *
+ * Values:
+ * - 0b0 - Not enabled to enter Freeze mode.
+ * - 0b1 - Enabled to enter Freeze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_FRZ field. */
+#define CAN_RD_MCR_FRZ(base) ((CAN_MCR_REG(base) & CAN_MCR_FRZ_MASK) >> CAN_MCR_FRZ_SHIFT)
+#define CAN_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define CAN_WR_MCR_FRZ(base, value) (CAN_RMW_MCR(base, CAN_MCR_FRZ_MASK, CAN_MCR_FRZ(value)))
+#define CAN_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field MDIS[31] (RW)
+ *
+ * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
+ * disables the clocks to the CAN Protocol Engine and Controller Host Interface
+ * sub-modules. This is the only bit within this register not affected by soft
+ * reset.
+ *
+ * Values:
+ * - 0b0 - Enable the FlexCAN module.
+ * - 0b1 - Disable the FlexCAN module.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_MDIS field. */
+#define CAN_RD_MCR_MDIS(base) ((CAN_MCR_REG(base) & CAN_MCR_MDIS_MASK) >> CAN_MCR_MDIS_SHIFT)
+#define CAN_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define CAN_WR_MCR_MDIS(base, value) (CAN_RMW_MCR(base, CAN_MCR_MDIS_MASK, CAN_MCR_MDIS(value)))
+#define CAN_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CTRL1 - Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CTRL1 - Control 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is defined for specific FlexCAN control features related to the
+ * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
+ * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
+ * (Bus-Off, Error, Warning). It also determines the Division Factor for the
+ * clock prescaler.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CTRL1 register
+ */
+/*@{*/
+#define CAN_RD_CTRL1(base)       (CAN_CTRL1_REG(base))
+#define CAN_WR_CTRL1(base, value) (CAN_CTRL1_REG(base) = (value))
+#define CAN_RMW_CTRL1(base, mask, value) (CAN_WR_CTRL1(base, (CAN_RD_CTRL1(base) & ~(mask)) | (value)))
+#define CAN_SET_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) |  (value)))
+#define CAN_CLR_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) & ~(value)))
+#define CAN_TOG_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CTRL1 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
+ *
+ * This 3-bit field defines the length of the Propagation Segment in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Propagation
+ * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PROPSEG field. */
+#define CAN_RD_CTRL1_PROPSEG(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PROPSEG_MASK) >> CAN_CTRL1_PROPSEG_SHIFT)
+#define CAN_BRD_CTRL1_PROPSEG(base) (CAN_RD_CTRL1_PROPSEG(base))
+
+/*! @brief Set the PROPSEG field to a new value. */
+#define CAN_WR_CTRL1_PROPSEG(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PROPSEG_MASK, CAN_CTRL1_PROPSEG(value)))
+#define CAN_BWR_CTRL1_PROPSEG(base, value) (CAN_WR_CTRL1_PROPSEG(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LOM[3] (RW)
+ *
+ * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
+ * transmission is disabled, all error counters are frozen and the module operates
+ * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
+ * will be received. If FlexCAN detects a message that has not been acknowledged,
+ * it will flag a BIT0 error without changing the REC, as if it was trying to
+ * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
+ * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
+ * entered. There can be some delay between the Listen-Only mode request and
+ * acknowledge. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Listen-Only mode is deactivated.
+ * - 0b1 - FlexCAN module operates in Listen-Only mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LOM field. */
+#define CAN_RD_CTRL1_LOM(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LOM_MASK) >> CAN_CTRL1_LOM_SHIFT)
+#define CAN_BRD_CTRL1_LOM(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LOM_SHIFT))
+
+/*! @brief Set the LOM field to a new value. */
+#define CAN_WR_CTRL1_LOM(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LOM_MASK, CAN_CTRL1_LOM(value)))
+#define CAN_BWR_CTRL1_LOM(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LBUF[4] (RW)
+ *
+ * This bit defines the ordering mechanism for Message Buffer transmission. When
+ * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0b0 - Buffer with highest priority is transmitted first.
+ * - 0b1 - Lowest number buffer is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LBUF field. */
+#define CAN_RD_CTRL1_LBUF(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LBUF_MASK) >> CAN_CTRL1_LBUF_SHIFT)
+#define CAN_BRD_CTRL1_LBUF(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LBUF_SHIFT))
+
+/*! @brief Set the LBUF field to a new value. */
+#define CAN_WR_CTRL1_LBUF(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LBUF_MASK, CAN_CTRL1_LBUF(value)))
+#define CAN_BWR_CTRL1_LBUF(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field TSYN[5] (RW)
+ *
+ * This bit enables a mechanism that resets the free-running timer each time a
+ * message is received in Message Buffer 0. This feature provides means to
+ * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
+ * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
+ * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
+ * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Timer Sync feature disabled
+ * - 0b1 - Timer Sync feature enabled
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_TSYN field. */
+#define CAN_RD_CTRL1_TSYN(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_TSYN_MASK) >> CAN_CTRL1_TSYN_SHIFT)
+#define CAN_BRD_CTRL1_TSYN(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TSYN_SHIFT))
+
+/*! @brief Set the TSYN field to a new value. */
+#define CAN_WR_CTRL1_TSYN(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_TSYN_MASK, CAN_CTRL1_TSYN(value)))
+#define CAN_BWR_CTRL1_TSYN(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TSYN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
+ *
+ * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
+ * negated, automatic recovering from Bus Off state occurs according to the CAN
+ * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
+ * disabled and the module remains in Bus Off state until the bit is negated by the
+ * user. If the negation occurs before 128 sequences of 11 recessive bits are
+ * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
+ * never been asserted. If the negation occurs after 128 sequences of 11
+ * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
+ * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
+ * be re-asserted again during Bus Off, but it will be effective only the next
+ * time the module enters Bus Off. If BOFFREC was negated when the module entered
+ * Bus Off, asserting it during Bus Off will not be effective for the current Bus
+ * Off recovery.
+ *
+ * Values:
+ * - 0b0 - Automatic recovering from Bus Off state enabled, according to CAN
+ *     Spec 2.0 part B.
+ * - 0b1 - Automatic recovering from Bus Off state disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_BOFFREC field. */
+#define CAN_RD_CTRL1_BOFFREC(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_BOFFREC_MASK) >> CAN_CTRL1_BOFFREC_SHIFT)
+#define CAN_BRD_CTRL1_BOFFREC(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFREC_SHIFT))
+
+/*! @brief Set the BOFFREC field to a new value. */
+#define CAN_WR_CTRL1_BOFFREC(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_BOFFREC_MASK, CAN_CTRL1_BOFFREC(value)))
+#define CAN_BWR_CTRL1_BOFFREC(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFREC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field SMP[7] (RW)
+ *
+ * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
+ * be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0b0 - Just one sample is used to determine the bit value.
+ * - 0b1 - Three samples are used to determine the value of the received bit:
+ *     the regular one (sample point) and 2 preceding samples; a majority rule is
+ *     used.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_SMP field. */
+#define CAN_RD_CTRL1_SMP(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_SMP_MASK) >> CAN_CTRL1_SMP_SHIFT)
+#define CAN_BRD_CTRL1_SMP(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_SMP_SHIFT))
+
+/*! @brief Set the SMP field to a new value. */
+#define CAN_WR_CTRL1_SMP(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_SMP_MASK, CAN_CTRL1_SMP(value)))
+#define CAN_BWR_CTRL1_SMP(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_SMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
+ *
+ * This bit provides a mask for the Rx Warning Interrupt associated with the
+ * RWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Rx Warning Interrupt disabled.
+ * - 0b1 - Rx Warning Interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_RWRNMSK field. */
+#define CAN_RD_CTRL1_RWRNMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_RWRNMSK_MASK) >> CAN_CTRL1_RWRNMSK_SHIFT)
+#define CAN_BRD_CTRL1_RWRNMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_RWRNMSK_SHIFT))
+
+/*! @brief Set the RWRNMSK field to a new value. */
+#define CAN_WR_CTRL1_RWRNMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_RWRNMSK_MASK, CAN_CTRL1_RWRNMSK(value)))
+#define CAN_BWR_CTRL1_RWRNMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_RWRNMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
+ *
+ * This bit provides a mask for the Tx Warning Interrupt associated with the
+ * TWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Tx Warning Interrupt disabled.
+ * - 0b1 - Tx Warning Interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_TWRNMSK field. */
+#define CAN_RD_CTRL1_TWRNMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_TWRNMSK_MASK) >> CAN_CTRL1_TWRNMSK_SHIFT)
+#define CAN_BRD_CTRL1_TWRNMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TWRNMSK_SHIFT))
+
+/*! @brief Set the TWRNMSK field to a new value. */
+#define CAN_WR_CTRL1_TWRNMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_TWRNMSK_MASK, CAN_CTRL1_TWRNMSK(value)))
+#define CAN_BWR_CTRL1_TWRNMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TWRNMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LPB[12] (RW)
+ *
+ * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
+ * FlexCAN performs an internal loop back that can be used for self test operation.
+ * The bit stream output of the transmitter is fed back internally to the receiver
+ * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
+ * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
+ * and treats its own transmitted message as a message received from a remote
+ * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
+ * frame acknowledge field, generating an internal acknowledge bit to ensure proper
+ * reception of its own message. Both transmit and receive interrupts are
+ * generated. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
+ * this will impede the self reception of a transmitted message.
+ *
+ * Values:
+ * - 0b0 - Loop Back disabled.
+ * - 0b1 - Loop Back enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LPB field. */
+#define CAN_RD_CTRL1_LPB(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LPB_MASK) >> CAN_CTRL1_LPB_SHIFT)
+#define CAN_BRD_CTRL1_LPB(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LPB_SHIFT))
+
+/*! @brief Set the LPB field to a new value. */
+#define CAN_WR_CTRL1_LPB(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LPB_MASK, CAN_CTRL1_LPB(value)))
+#define CAN_BWR_CTRL1_LPB(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LPB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
+ *
+ * This bit selects the clock source to the CAN Protocol Engine (PE) to be
+ * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
+ * The selected clock is the one fed to the prescaler to generate the Serial Clock
+ * (Sclock). In order to guarantee reliable operation, this bit can be written
+ * only in Disable mode because it is blocked by hardware in other modes. See
+ * Section "Protocol Timing".
+ *
+ * Values:
+ * - 0b0 - The CAN engine clock source is the oscillator clock. Under this
+ *     condition, the oscillator clock frequency must be lower than the bus clock.
+ * - 0b1 - The CAN engine clock source is the peripheral clock.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_CLKSRC field. */
+#define CAN_RD_CTRL1_CLKSRC(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_CLKSRC_MASK) >> CAN_CTRL1_CLKSRC_SHIFT)
+#define CAN_BRD_CTRL1_CLKSRC(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_CLKSRC_SHIFT))
+
+/*! @brief Set the CLKSRC field to a new value. */
+#define CAN_WR_CTRL1_CLKSRC(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_CLKSRC_MASK, CAN_CTRL1_CLKSRC(value)))
+#define CAN_BWR_CTRL1_CLKSRC(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_CLKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
+ *
+ * This bit provides a mask for the Error Interrupt.
+ *
+ * Values:
+ * - 0b0 - Error interrupt disabled.
+ * - 0b1 - Error interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_ERRMSK field. */
+#define CAN_RD_CTRL1_ERRMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_ERRMSK_MASK) >> CAN_CTRL1_ERRMSK_SHIFT)
+#define CAN_BRD_CTRL1_ERRMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_ERRMSK_SHIFT))
+
+/*! @brief Set the ERRMSK field to a new value. */
+#define CAN_WR_CTRL1_ERRMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_ERRMSK_MASK, CAN_CTRL1_ERRMSK(value)))
+#define CAN_BWR_CTRL1_ERRMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_ERRMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
+ *
+ * This bit provides a mask for the Bus Off Interrupt.
+ *
+ * Values:
+ * - 0b0 - Bus Off interrupt disabled.
+ * - 0b1 - Bus Off interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_BOFFMSK field. */
+#define CAN_RD_CTRL1_BOFFMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_BOFFMSK_MASK) >> CAN_CTRL1_BOFFMSK_SHIFT)
+#define CAN_BRD_CTRL1_BOFFMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFMSK_SHIFT))
+
+/*! @brief Set the BOFFMSK field to a new value. */
+#define CAN_WR_CTRL1_BOFFMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_BOFFMSK_MASK, CAN_CTRL1_BOFFMSK(value)))
+#define CAN_BWR_CTRL1_BOFFMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
+ * time. The valid programmable values are 1-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 2 = (PSEG2 + 1) * Time-Quanta.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PSEG2 field. */
+#define CAN_RD_CTRL1_PSEG2(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PSEG2_MASK) >> CAN_CTRL1_PSEG2_SHIFT)
+#define CAN_BRD_CTRL1_PSEG2(base) (CAN_RD_CTRL1_PSEG2(base))
+
+/*! @brief Set the PSEG2 field to a new value. */
+#define CAN_WR_CTRL1_PSEG2(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PSEG2_MASK, CAN_CTRL1_PSEG2(value)))
+#define CAN_BWR_CTRL1_PSEG2(base, value) (CAN_WR_CTRL1_PSEG2(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 1 = (PSEG1 + 1) * Time-Quanta.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PSEG1 field. */
+#define CAN_RD_CTRL1_PSEG1(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PSEG1_MASK) >> CAN_CTRL1_PSEG1_SHIFT)
+#define CAN_BRD_CTRL1_PSEG1(base) (CAN_RD_CTRL1_PSEG1(base))
+
+/*! @brief Set the PSEG1 field to a new value. */
+#define CAN_WR_CTRL1_PSEG1(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PSEG1_MASK, CAN_CTRL1_PSEG1(value)))
+#define CAN_BWR_CTRL1_PSEG1(base, value) (CAN_WR_CTRL1_PSEG1(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field RJW[23:22] (RW)
+ *
+ * This 2-bit field defines the maximum number of time quanta that a bit time
+ * can be changed by one re-synchronization. One time quantum is equal to the
+ * Sclock period. The valid programmable values are 0-3. This field can be written
+ * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
+ * Width = RJW + 1.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_RJW field. */
+#define CAN_RD_CTRL1_RJW(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_RJW_MASK) >> CAN_CTRL1_RJW_SHIFT)
+#define CAN_BRD_CTRL1_RJW(base) (CAN_RD_CTRL1_RJW(base))
+
+/*! @brief Set the RJW field to a new value. */
+#define CAN_WR_CTRL1_RJW(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_RJW_MASK, CAN_CTRL1_RJW(value)))
+#define CAN_BWR_CTRL1_RJW(base, value) (CAN_WR_CTRL1_RJW(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
+ *
+ * This 8-bit field defines the ratio between the PE clock frequency and the
+ * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
+ * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
+ * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
+ * Sclock frequency equal to the PE clock frequency divided by 256. See Section
+ * "Protocol Timing". This field can be written only in Freeze mode because it is
+ * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
+ * (PRESDIV + 1)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PRESDIV field. */
+#define CAN_RD_CTRL1_PRESDIV(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PRESDIV_MASK) >> CAN_CTRL1_PRESDIV_SHIFT)
+#define CAN_BRD_CTRL1_PRESDIV(base) (CAN_RD_CTRL1_PRESDIV(base))
+
+/*! @brief Set the PRESDIV field to a new value. */
+#define CAN_WR_CTRL1_PRESDIV(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PRESDIV_MASK, CAN_CTRL1_PRESDIV(value)))
+#define CAN_BWR_CTRL1_PRESDIV(base, value) (CAN_WR_CTRL1_PRESDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_TIMER - Free Running Timer
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_TIMER - Free Running Timer (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register represents a 16-bit free running counter that can be read and
+ * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
+ * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
+ * defines the baud rate on the CAN bus. During a message transmission/reception,
+ * it increments by one for each bit that is received or transmitted. When there
+ * is no message on the bus, it counts using the previously programmed baud
+ * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
+ * timer value is captured when the second bit of the identifier field of any frame
+ * is on the CAN bus. This captured value is written into the Time Stamp entry
+ * in a message buffer after a successful reception or transmission of a message.
+ * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
+ * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
+ * can write to this register anytime. However, if the write occurs at the same
+ * time that the Timer is being reset by a reception in the first Mailbox, then
+ * the write value is discarded. Reading this register affects the Mailbox
+ * Unlocking procedure; see Section "Mailbox Lock Mechanism".
+ */
+/*!
+ * @name Constants and macros for entire CAN_TIMER register
+ */
+/*@{*/
+#define CAN_RD_TIMER(base)       (CAN_TIMER_REG(base))
+#define CAN_WR_TIMER(base, value) (CAN_TIMER_REG(base) = (value))
+#define CAN_RMW_TIMER(base, mask, value) (CAN_WR_TIMER(base, (CAN_RD_TIMER(base) & ~(mask)) | (value)))
+#define CAN_SET_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) |  (value)))
+#define CAN_CLR_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) & ~(value)))
+#define CAN_TOG_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_TIMER bitfields
+ */
+
+/*!
+ * @name Register CAN_TIMER, field TIMER[15:0] (RW)
+ *
+ * Contains the free-running counter value.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_TIMER_TIMER field. */
+#define CAN_RD_TIMER_TIMER(base) ((CAN_TIMER_REG(base) & CAN_TIMER_TIMER_MASK) >> CAN_TIMER_TIMER_SHIFT)
+#define CAN_BRD_TIMER_TIMER(base) (CAN_RD_TIMER_TIMER(base))
+
+/*! @brief Set the TIMER field to a new value. */
+#define CAN_WR_TIMER_TIMER(base, value) (CAN_RMW_TIMER(base, CAN_TIMER_TIMER_MASK, CAN_TIMER_TIMER(value)))
+#define CAN_BWR_TIMER_TIMER(base, value) (CAN_WR_TIMER_TIMER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RXMGMASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
+ * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
+ * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
+ * mask registers. This register can only be written in Freeze mode as it is
+ * blocked by hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXMGMASK register
+ */
+/*@{*/
+#define CAN_RD_RXMGMASK(base)    (CAN_RXMGMASK_REG(base))
+#define CAN_WR_RXMGMASK(base, value) (CAN_RXMGMASK_REG(base) = (value))
+#define CAN_RMW_RXMGMASK(base, mask, value) (CAN_WR_RXMGMASK(base, (CAN_RD_RXMGMASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) |  (value)))
+#define CAN_CLR_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) & ~(value)))
+#define CAN_TOG_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RX14MASK - Rx 14 Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RX14MASK - Rx 14 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX14MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
+ * is used to mask the filter fields of Message Buffer 14. This register can only
+ * be programmed while the module is in Freeze mode as it is blocked by hardware
+ * in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RX14MASK register
+ */
+/*@{*/
+#define CAN_RD_RX14MASK(base)    (CAN_RX14MASK_REG(base))
+#define CAN_WR_RX14MASK(base, value) (CAN_RX14MASK_REG(base) = (value))
+#define CAN_RMW_RX14MASK(base, mask, value) (CAN_WR_RX14MASK(base, (CAN_RD_RX14MASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) |  (value)))
+#define CAN_CLR_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) & ~(value)))
+#define CAN_TOG_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RX15MASK - Rx 15 Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RX15MASK - Rx 15 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX15MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
+ * is used to mask the filter fields of Message Buffer 15. This register can be
+ * programmed only while the module is in Freeze mode because it is blocked by
+ * hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RX15MASK register
+ */
+/*@{*/
+#define CAN_RD_RX15MASK(base)    (CAN_RX15MASK_REG(base))
+#define CAN_WR_RX15MASK(base, value) (CAN_RX15MASK_REG(base) = (value))
+#define CAN_RMW_RX15MASK(base, mask, value) (CAN_WR_RX15MASK(base, (CAN_RD_RX15MASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) |  (value)))
+#define CAN_CLR_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) & ~(value)))
+#define CAN_TOG_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ECR - Error Counter
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ECR - Error Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has two 8-bit fields reflecting the value of two FlexCAN error
+ * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
+ * (RXERRCNT field). The rules for increasing and decreasing these counters are
+ * described in the CAN protocol and are completely implemented in the FlexCAN
+ * module. Both counters are read-only except in Freeze mode, where they can be
+ * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
+ * for example, transmit Error Active or Error Passive flag, delay its
+ * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
+ * Off state. The following are the basic rules for FlexCAN bus state transitions:
+ * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
+ * 128, the FLTCONF field in the Error and Status Register is updated to reflect
+ * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
+ * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
+ * other already satisfies this condition, the FLTCONF field in the Error and
+ * Status Register is updated to reflect 'Error Active' state. If the value of
+ * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
+ * Register is updated to reflect 'Bus Off' state, and an interrupt may be
+ * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
+ * state, then TXERRCNT is cascaded together with another internal counter to count
+ * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
+ * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
+ * 11 such bits and then wraps around while incrementing the TXERRCNT. When
+ * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
+ * Register is updated to be 'Error Active' and both error counters are reset to zero.
+ * At any instance of dominant bit following a stream of less than 11
+ * consecutive recessive bits, the internal counter resets itself to zero without affecting
+ * the TXERRCNT value. If during system start-up, only one node is operating,
+ * then its TXERRCNT increases in each message it is trying to transmit, as a
+ * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
+ * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
+ * increment anymore by acknowledge errors. Therefore the device never goes to
+ * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
+ * is not incremented further, even if more errors are detected while being a
+ * receiver. At the next successful message reception, the counter is set to a value
+ * between 119 and 127 to resume to 'Error Active' state.
+ */
+/*!
+ * @name Constants and macros for entire CAN_ECR register
+ */
+/*@{*/
+#define CAN_RD_ECR(base)         (CAN_ECR_REG(base))
+#define CAN_WR_ECR(base, value)  (CAN_ECR_REG(base) = (value))
+#define CAN_RMW_ECR(base, mask, value) (CAN_WR_ECR(base, (CAN_RD_ECR(base) & ~(mask)) | (value)))
+#define CAN_SET_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) |  (value)))
+#define CAN_CLR_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) & ~(value)))
+#define CAN_TOG_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ECR bitfields
+ */
+
+/*!
+ * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ECR_TXERRCNT field. */
+#define CAN_RD_ECR_TXERRCNT(base) ((CAN_ECR_REG(base) & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT)
+#define CAN_BRD_ECR_TXERRCNT(base) (CAN_RD_ECR_TXERRCNT(base))
+
+/*! @brief Set the TXERRCNT field to a new value. */
+#define CAN_WR_ECR_TXERRCNT(base, value) (CAN_RMW_ECR(base, CAN_ECR_TXERRCNT_MASK, CAN_ECR_TXERRCNT(value)))
+#define CAN_BWR_ECR_TXERRCNT(base, value) (CAN_WR_ECR_TXERRCNT(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ECR_RXERRCNT field. */
+#define CAN_RD_ECR_RXERRCNT(base) ((CAN_ECR_REG(base) & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT)
+#define CAN_BRD_ECR_RXERRCNT(base) (CAN_RD_ECR_RXERRCNT(base))
+
+/*! @brief Set the RXERRCNT field to a new value. */
+#define CAN_WR_ECR_RXERRCNT(base, value) (CAN_RMW_ECR(base, CAN_ECR_RXERRCNT_MASK, CAN_ECR_RXERRCNT(value)))
+#define CAN_BWR_ECR_RXERRCNT(base, value) (CAN_WR_ECR_RXERRCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ESR1 - Error and Status 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ESR1 - Error and Status 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various error conditions, some general status of the
+ * device and it is the source of interrupts to the CPU. The CPU read action
+ * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
+ * that occurred since the last time the CPU read this register. Bits 9-3 are
+ * status bits. The following table shows the FlexCAN state variables and their
+ * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
+ * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
+ * Transmitting 1 0 0 1 Receiving
+ */
+/*!
+ * @name Constants and macros for entire CAN_ESR1 register
+ */
+/*@{*/
+#define CAN_RD_ESR1(base)        (CAN_ESR1_REG(base))
+#define CAN_WR_ESR1(base, value) (CAN_ESR1_REG(base) = (value))
+#define CAN_RMW_ESR1(base, mask, value) (CAN_WR_ESR1(base, (CAN_RD_ESR1(base) & ~(mask)) | (value)))
+#define CAN_SET_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) |  (value)))
+#define CAN_CLR_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) & ~(value)))
+#define CAN_TOG_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ESR1 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR1, field WAKINT[0] (W1C)
+ *
+ * This field applies when FlexCAN is in low-power mode under Self Wake Up
+ * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
+ * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
+ * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
+ * is masked. The CPU must clear this flag before disabling the bit. Otherwise
+ * it will be set when the SLFWAK is set again. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - Indicates a recessive to dominant transition was received on the CAN
+ *     bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_WAKINT field. */
+#define CAN_RD_ESR1_WAKINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_WAKINT_MASK) >> CAN_ESR1_WAKINT_SHIFT)
+#define CAN_BRD_ESR1_WAKINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_WAKINT_SHIFT))
+
+/*! @brief Set the WAKINT field to a new value. */
+#define CAN_WR_ESR1_WAKINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_WAKINT(value)))
+#define CAN_BWR_ESR1_WAKINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_WAKINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field ERRINT[1] (W1C)
+ *
+ * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
+ * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
+ * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - Indicates setting of any Error Bit in the Error and Status Register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_ERRINT field. */
+#define CAN_RD_ESR1_ERRINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_ERRINT_MASK) >> CAN_ESR1_ERRINT_SHIFT)
+#define CAN_BRD_ESR1_ERRINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ERRINT_SHIFT))
+
+/*! @brief Set the ERRINT field to a new value. */
+#define CAN_WR_ESR1_ERRINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_ERRINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_ERRINT(value)))
+#define CAN_BWR_ESR1_ERRINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ERRINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
+ *
+ * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
+ * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
+ * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - FlexCAN module entered Bus Off state.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BOFFINT field. */
+#define CAN_RD_ESR1_BOFFINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BOFFINT_MASK) >> CAN_ESR1_BOFFINT_SHIFT)
+#define CAN_BRD_ESR1_BOFFINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BOFFINT_SHIFT))
+
+/*! @brief Set the BOFFINT field to a new value. */
+#define CAN_WR_ESR1_BOFFINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_BOFFINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_BOFFINT(value)))
+#define CAN_BWR_ESR1_BOFFINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BOFFINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RX[3] (RO)
+ *
+ * This bit indicates if FlexCAN is receiving a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not receiving a message.
+ * - 0b1 - FlexCAN is receiving a message.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RX field. */
+#define CAN_RD_ESR1_RX(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RX_MASK) >> CAN_ESR1_RX_SHIFT)
+#define CAN_BRD_ESR1_RX(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
+ *
+ * This 2-bit field indicates the Confinement State of the FlexCAN module. If
+ * the LOM bit in the Control Register is asserted, after some delay that depends
+ * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
+ * same delay affects the way how FLTCONF reflects an update to ECR register by
+ * the CPU. It may be necessary up to one CAN bit time to get them coherent
+ * again. Because the Control Register is not affected by soft reset, the FLTCONF
+ * field will not be affected by soft reset if the LOM bit is asserted.
+ *
+ * Values:
+ * - 0b00 - Error Active
+ * - 0b01 - Error Passive
+ * - 0b1x - Bus Off
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_FLTCONF field. */
+#define CAN_RD_ESR1_FLTCONF(base) ((CAN_ESR1_REG(base) & CAN_ESR1_FLTCONF_MASK) >> CAN_ESR1_FLTCONF_SHIFT)
+#define CAN_BRD_ESR1_FLTCONF(base) (CAN_RD_ESR1_FLTCONF(base))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TX[6] (RO)
+ *
+ * This bit indicates if FlexCAN is transmitting a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not transmitting a message.
+ * - 0b1 - FlexCAN is transmitting a message.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TX field. */
+#define CAN_RD_ESR1_TX(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TX_MASK) >> CAN_ESR1_TX_SHIFT)
+#define CAN_BRD_ESR1_TX(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field IDLE[7] (RO)
+ *
+ * This bit indicates when CAN bus is in IDLE state. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - CAN bus is now IDLE.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_IDLE field. */
+#define CAN_RD_ESR1_IDLE(base) ((CAN_ESR1_REG(base) & CAN_ESR1_IDLE_MASK) >> CAN_ESR1_IDLE_SHIFT)
+#define CAN_BRD_ESR1_IDLE(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RXWRN[8] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * reception. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - RXERRCNT is greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RXWRN field. */
+#define CAN_RD_ESR1_RXWRN(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RXWRN_MASK) >> CAN_ESR1_RXWRN_SHIFT)
+#define CAN_BRD_ESR1_RXWRN(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RXWRN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TXWRN[9] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * transmission. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - TXERRCNT is greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TXWRN field. */
+#define CAN_RD_ESR1_TXWRN(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TXWRN_MASK) >> CAN_ESR1_TXWRN_SHIFT)
+#define CAN_BRD_ESR1_TXWRN(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TXWRN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field STFERR[10] (RO)
+ *
+ * This bit indicates that a Stuffing Error has been etected.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A Stuffing Error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_STFERR field. */
+#define CAN_RD_ESR1_STFERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_STFERR_MASK) >> CAN_ESR1_STFERR_SHIFT)
+#define CAN_BRD_ESR1_STFERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_STFERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field FRMERR[11] (RO)
+ *
+ * This bit indicates that a Form Error has been detected by the receiver node,
+ * that is, a fixed-form bit field contains at least one illegal bit.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A Form Error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_FRMERR field. */
+#define CAN_RD_ESR1_FRMERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_FRMERR_MASK) >> CAN_ESR1_FRMERR_SHIFT)
+#define CAN_BRD_ESR1_FRMERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_FRMERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field CRCERR[12] (RO)
+ *
+ * This bit indicates that a CRC Error has been detected by the receiver node,
+ * that is, the calculated CRC is different from the received.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A CRC error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_CRCERR field. */
+#define CAN_RD_ESR1_CRCERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_CRCERR_MASK) >> CAN_ESR1_CRCERR_SHIFT)
+#define CAN_BRD_ESR1_CRCERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_CRCERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field ACKERR[13] (RO)
+ *
+ * This bit indicates that an Acknowledge Error has been detected by the
+ * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - An ACK error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_ACKERR field. */
+#define CAN_RD_ESR1_ACKERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_ACKERR_MASK) >> CAN_ESR1_ACKERR_SHIFT)
+#define CAN_BRD_ESR1_ACKERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ACKERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - At least one bit sent as dominant is received as recessive.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BIT0ERR field. */
+#define CAN_RD_ESR1_BIT0ERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BIT0ERR_MASK) >> CAN_ESR1_BIT0ERR_SHIFT)
+#define CAN_BRD_ESR1_BIT0ERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BIT0ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message. This bit is not set by a transmitter in case of
+ * arbitration field or ACK slot, or in case of a node sending a passive error
+ * flag that detects dominant bits.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - At least one bit sent as recessive is received as dominant.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BIT1ERR field. */
+#define CAN_RD_ESR1_BIT1ERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BIT1ERR_MASK) >> CAN_ESR1_BIT1ERR_SHIFT)
+#define CAN_BRD_ESR1_BIT1ERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BIT1ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
+ * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
+ * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
+ * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - The Rx error counter transitioned from less than 96 to greater than
+ *     or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RWRNINT field. */
+#define CAN_RD_ESR1_RWRNINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RWRNINT_MASK) >> CAN_ESR1_RWRNINT_SHIFT)
+#define CAN_BRD_ESR1_RWRNINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RWRNINT_SHIFT))
+
+/*! @brief Set the RWRNINT field to a new value. */
+#define CAN_WR_ESR1_RWRNINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_RWRNINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_RWRNINT(value)))
+#define CAN_BWR_ESR1_RWRNINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RWRNINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
+ * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
+ * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
+ * is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This flag is not generated during Bus Off state. This bit is not
+ * updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - The Tx error counter transitioned from less than 96 to greater than
+ *     or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TWRNINT field. */
+#define CAN_RD_ESR1_TWRNINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TWRNINT_MASK) >> CAN_ESR1_TWRNINT_SHIFT)
+#define CAN_BRD_ESR1_TWRNINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TWRNINT_SHIFT))
+
+/*! @brief Set the TWRNINT field to a new value. */
+#define CAN_WR_ESR1_TWRNINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_TWRNINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK), CAN_ESR1_TWRNINT(value)))
+#define CAN_BWR_ESR1_TWRNINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TWRNINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field SYNCH[18] (RO)
+ *
+ * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
+ * bus and able to participate in the communication process. It is set and
+ * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not synchronized to the CAN bus.
+ * - 0b1 - FlexCAN is synchronized to the CAN bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_SYNCH field. */
+#define CAN_RD_ESR1_SYNCH(base) ((CAN_ESR1_REG(base) & CAN_ESR1_SYNCH_MASK) >> CAN_ESR1_SYNCH_SHIFT)
+#define CAN_BRD_ESR1_SYNCH(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_SYNCH_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_IMASK1 - Interrupt Masks 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_IMASK1 - Interrupt Masks 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register allows any number of a range of the 32 Message Buffer
+ * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
+ * bit per buffer, enabling the CPU to determine which buffer generates an
+ * interrupt after a successful transmission or reception, that is, when the
+ * corresponding IFLAG1 bit is set.
+ */
+/*!
+ * @name Constants and macros for entire CAN_IMASK1 register
+ */
+/*@{*/
+#define CAN_RD_IMASK1(base)      (CAN_IMASK1_REG(base))
+#define CAN_WR_IMASK1(base, value) (CAN_IMASK1_REG(base) = (value))
+#define CAN_RMW_IMASK1(base, mask, value) (CAN_WR_IMASK1(base, (CAN_RD_IMASK1(base) & ~(mask)) | (value)))
+#define CAN_SET_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) |  (value)))
+#define CAN_CLR_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) & ~(value)))
+#define CAN_TOG_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_IFLAG1 - Interrupt Flags 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the flags for the 32 Message Buffer interrupts for MB31
+ * to MB0. It contains one interrupt flag bit per buffer. Each successful
+ * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
+ * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
+ * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
+ * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
+ * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
+ * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
+ * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
+ * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
+ * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
+ * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
+ * the FIFO flags must be cleared. The same care must be taken when an RFFN
+ * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
+ * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
+ * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
+ * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
+ * they will remain set and be inconsistent with the number of MBs available.
+ */
+/*!
+ * @name Constants and macros for entire CAN_IFLAG1 register
+ */
+/*@{*/
+#define CAN_RD_IFLAG1(base)      (CAN_IFLAG1_REG(base))
+#define CAN_WR_IFLAG1(base, value) (CAN_IFLAG1_REG(base) = (value))
+#define CAN_RMW_IFLAG1(base, mask, value) (CAN_WR_IFLAG1(base, (CAN_RD_IFLAG1(base) & ~(mask)) | (value)))
+#define CAN_SET_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) |  (value)))
+#define CAN_CLR_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) & ~(value)))
+#define CAN_TOG_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_IFLAG1 bitfields
+ */
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
+ * set.
+ *
+ * Values:
+ * - 0b0 - The corresponding buffer has no occurrence of successfully completed
+ *     transmission or reception when MCR[RFEN]=0.
+ * - 0b1 - The corresponding buffer has successfully completed transmission or
+ *     reception when MCR[RFEN]=0.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF0I field. */
+#define CAN_RD_IFLAG1_BUF0I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF0I_MASK) >> CAN_IFLAG1_BUF0I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF0I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF0I_SHIFT))
+
+/*! @brief Set the BUF0I field to a new value. */
+#define CAN_WR_IFLAG1_BUF0I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF0I(value)))
+#define CAN_BWR_IFLAG1_BUF0I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF0I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
+ * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
+ * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
+ * when MCR[RFEN] is set.
+ *
+ * Values:
+ * - 0b0000 - The corresponding buffer has no occurrence of successfully
+ *     completed transmission or reception when MCR[RFEN]=0.
+ * - 0b0001 - The corresponding buffer has successfully completed transmission
+ *     or reception when MCR[RFEN]=0.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field. */
+#define CAN_RD_IFLAG1_BUF4TO1I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF4TO1I_MASK) >> CAN_IFLAG1_BUF4TO1I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF4TO1I(base) (CAN_RD_IFLAG1_BUF4TO1I(base))
+
+/*! @brief Set the BUF4TO1I field to a new value. */
+#define CAN_WR_IFLAG1_BUF4TO1I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF4TO1I(value)))
+#define CAN_BWR_IFLAG1_BUF4TO1I(base, value) (CAN_WR_IFLAG1_BUF4TO1I(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
+ * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
+ * least one frame is available to be read from the Rx FIFO.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB5 completing transmission/reception when
+ *     MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
+ * - 0b1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
+ *     available in the Rx FIFO when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF5I field. */
+#define CAN_RD_IFLAG1_BUF5I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF5I_MASK) >> CAN_IFLAG1_BUF5I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF5I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF5I_SHIFT))
+
+/*! @brief Set the BUF5I field to a new value. */
+#define CAN_WR_IFLAG1_BUF5I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF5I(value)))
+#define CAN_BWR_IFLAG1_BUF5I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF5I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
+ * when MCR[RFEN] is set. In this case, the flag indicates when the number of
+ * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
+ * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
+ * cleared while the number of unread messages is greater than 4, it does not
+ * assert again until the number of unread messages within the Rx FIFO is decreased
+ * to be equal to or less than 4.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB6 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
+ * - 0b1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     almost full when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF6I field. */
+#define CAN_RD_IFLAG1_BUF6I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF6I_MASK) >> CAN_IFLAG1_BUF6I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF6I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF6I_SHIFT))
+
+/*! @brief Set the BUF6I field to a new value. */
+#define CAN_WR_IFLAG1_BUF6I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF6I(value)))
+#define CAN_BWR_IFLAG1_BUF6I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF6I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
+ * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
+ * because the Rx FIFO is full. Note that the flag will not be asserted when the
+ * Rx FIFO is full and the message was captured by a Mailbox.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB7 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
+ * - 0b1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     overflow when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF7I field. */
+#define CAN_RD_IFLAG1_BUF7I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF7I_MASK) >> CAN_IFLAG1_BUF7I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF7I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF7I_SHIFT))
+
+/*! @brief Set the BUF7I field to a new value. */
+#define CAN_WR_IFLAG1_BUF7I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF7I(value)))
+#define CAN_BWR_IFLAG1_BUF7I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF7I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
+ *
+ * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
+ * MB8.
+ *
+ * Values:
+ * - 0b000000000000000000000000 - The corresponding buffer has no occurrence of
+ *     successfully completed transmission or reception.
+ * - 0b000000000000000000000001 - The corresponding buffer has successfully
+ *     completed transmission or reception.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field. */
+#define CAN_RD_IFLAG1_BUF31TO8I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF31TO8I_MASK) >> CAN_IFLAG1_BUF31TO8I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF31TO8I(base) (CAN_RD_IFLAG1_BUF31TO8I(base))
+
+/*! @brief Set the BUF31TO8I field to a new value. */
+#define CAN_WR_IFLAG1_BUF31TO8I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF31TO8I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK), CAN_IFLAG1_BUF31TO8I(value)))
+#define CAN_BWR_IFLAG1_BUF31TO8I(base, value) (CAN_WR_IFLAG1_BUF31TO8I(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CTRL2 - Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CTRL2 - Control 2 register (RW)
+ *
+ * Reset value: 0x00B00000U
+ *
+ * This register contains control bits for CAN errors, FIFO features, and mode
+ * selection.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CTRL2 register
+ */
+/*@{*/
+#define CAN_RD_CTRL2(base)       (CAN_CTRL2_REG(base))
+#define CAN_WR_CTRL2(base, value) (CAN_CTRL2_REG(base) = (value))
+#define CAN_RMW_CTRL2(base, mask, value) (CAN_WR_CTRL2(base, (CAN_RD_CTRL2(base) & ~(mask)) | (value)))
+#define CAN_SET_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) |  (value)))
+#define CAN_CLR_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) & ~(value)))
+#define CAN_TOG_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CTRL2 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL2, field EACEN[16] (RW)
+ *
+ * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
+ * filters with their corresponding bits in the incoming frame by the matching
+ * process. This bit does not affect matching for Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
+ *     compared despite mask bits.
+ * - 0b1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit
+ *     with their corresponding bits within the incoming frame. Mask bits do apply.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_EACEN field. */
+#define CAN_RD_CTRL2_EACEN(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_EACEN_MASK) >> CAN_CTRL2_EACEN_SHIFT)
+#define CAN_BRD_CTRL2_EACEN(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_EACEN_SHIFT))
+
+/*! @brief Set the EACEN field to a new value. */
+#define CAN_WR_CTRL2_EACEN(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_EACEN_MASK, CAN_CTRL2_EACEN(value)))
+#define CAN_BWR_CTRL2_EACEN(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_EACEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field RRS[17] (RW)
+ *
+ * If this bit is asserted Remote Request Frame is submitted to a matching
+ * process and stored in the corresponding Message Buffer in the same fashion of a
+ * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
+ * negated the Remote Request Frame is submitted to a matching process and an
+ * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
+ * is found with the same ID. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Remote Response Frame is generated.
+ * - 0b1 - Remote Request Frame is stored.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_RRS field. */
+#define CAN_RD_CTRL2_RRS(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_RRS_MASK) >> CAN_CTRL2_RRS_SHIFT)
+#define CAN_BRD_CTRL2_RRS(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_RRS_SHIFT))
+
+/*! @brief Set the RRS field to a new value. */
+#define CAN_WR_CTRL2_RRS(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_RRS_MASK, CAN_CTRL2_RRS(value)))
+#define CAN_BWR_CTRL2_RRS(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_RRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field MRP[18] (RW)
+ *
+ * If this bit is set the matching process starts from the Mailboxes and if no
+ * match occurs the matching continues on the Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Matching starts from Rx FIFO and continues on Mailboxes.
+ * - 0b1 - Matching starts from Mailboxes and continues on Rx FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_MRP field. */
+#define CAN_RD_CTRL2_MRP(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_MRP_MASK) >> CAN_CTRL2_MRP_SHIFT)
+#define CAN_BRD_CTRL2_MRP(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_MRP_SHIFT))
+
+/*! @brief Set the MRP field to a new value. */
+#define CAN_WR_CTRL2_MRP(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_MRP_MASK, CAN_CTRL2_MRP(value)))
+#define CAN_BWR_CTRL2_MRP(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_MRP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field TASD[23:19] (RW)
+ *
+ * This 5-bit field indicates how many CAN bits the Tx arbitration process start
+ * point can be delayed from the first bit of CRC field on CAN bus. This field
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes. This field is useful to optimize the transmit performance based on
+ * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
+ * The duration of an arbitration process, in terms of CAN bits, is directly
+ * proportional to the number of available MBs and CAN baud rate and inversely
+ * proportional to the peripheral clock frequency. The optimal arbitration timing is
+ * that in which the last MB is scanned right before the first bit of the
+ * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
+ * clock ratio is high and the CAN baud rate is low then the arbitration can be
+ * delayed and vice-versa. If TASD is 0 then the arbitration start is not
+ * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
+ * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
+ * the CPU can configure a Tx MB later and less time is reserved for
+ * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
+ * to find winner MBs in time to compete with other nodes for the CAN bus. If the
+ * arbitration ends too much time before the first bit of Intermission field then
+ * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
+ * not the best to be transmitted. The optimal configuration for TASD can be
+ * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
+ * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
+ * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
+ * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
+ * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
+ * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
+ * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
+ * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
+ * Timing" for more details.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_TASD field. */
+#define CAN_RD_CTRL2_TASD(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_TASD_MASK) >> CAN_CTRL2_TASD_SHIFT)
+#define CAN_BRD_CTRL2_TASD(base) (CAN_RD_CTRL2_TASD(base))
+
+/*! @brief Set the TASD field to a new value. */
+#define CAN_WR_CTRL2_TASD(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_TASD_MASK, CAN_CTRL2_TASD(value)))
+#define CAN_BWR_CTRL2_TASD(base, value) (CAN_WR_CTRL2_TASD(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
+ *
+ * This 4-bit field defines the number of Rx FIFO filters, as shown in the
+ * following table. The maximum selectable number of filters is determined by the MCU.
+ * This field can only be written in Freeze mode as it is blocked by hardware in
+ * other modes. This field must not be programmed with values that make the
+ * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
+ * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
+ * a memory space equivalent to two Message Buffers which means that the more
+ * filters are implemented the less Mailboxes will be available. Considering that
+ * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
+ * be programmed with a value correponding to a number of filters not greater
+ * than the number of available memory words which can be calculated as follows:
+ * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
+ * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
+ * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
+ * SETUP_MB value (memory space available) the exceeding ones will not be functional.
+ * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
+ * Filter Table Remaining Available MailboxesThe number of the last remaining
+ * available mailboxes is defined by the least value between the parameter
+ * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
+ * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
+ * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
+ * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
+ * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
+ * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
+ * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
+ * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
+ * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
+ * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
+ * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
+ * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
+ * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
+ * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
+ * 0-37 MB 38-63 Elements 0-31 Elements 32-127
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_RFFN field. */
+#define CAN_RD_CTRL2_RFFN(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT)
+#define CAN_BRD_CTRL2_RFFN(base) (CAN_RD_CTRL2_RFFN(base))
+
+/*! @brief Set the RFFN field to a new value. */
+#define CAN_WR_CTRL2_RFFN(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_RFFN_MASK, CAN_CTRL2_RFFN(value)))
+#define CAN_BWR_CTRL2_RFFN(base, value) (CAN_WR_CTRL2_RFFN(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
+ *
+ * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
+ * can only be written in Freeze mode and has no effect out of Freeze mode.
+ *
+ * Values:
+ * - 0b0 - Maintain the write access restrictions.
+ * - 0b1 - Enable unrestricted write access to FlexCAN memory.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_WRMFRZ field. */
+#define CAN_RD_CTRL2_WRMFRZ(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_WRMFRZ_MASK) >> CAN_CTRL2_WRMFRZ_SHIFT)
+#define CAN_BRD_CTRL2_WRMFRZ(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_WRMFRZ_SHIFT))
+
+/*! @brief Set the WRMFRZ field to a new value. */
+#define CAN_WR_CTRL2_WRMFRZ(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_WRMFRZ_MASK, CAN_CTRL2_WRMFRZ(value)))
+#define CAN_BWR_CTRL2_WRMFRZ(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_WRMFRZ_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ESR2 - Error and Status 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ESR2 - Error and Status 2 register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various interrupt flags and some general status.
+ */
+/*!
+ * @name Constants and macros for entire CAN_ESR2 register
+ */
+/*@{*/
+#define CAN_RD_ESR2(base)        (CAN_ESR2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ESR2 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR2, field IMB[13] (RO)
+ *
+ * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
+ * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
+ * following cases: During arbitration, if an LPTM is found and it is inactive. If
+ * IMB is not asserted and a frame is transmitted successfully. This bit is
+ * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
+ * mechanism have the following behavior: if an MB is successfully transmitted and
+ * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
+ * the index related to the MB just transmitted is loaded into ESR2[LPTM].
+ *
+ * Values:
+ * - 0b0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
+ * - 0b1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox.
+ *     LPTM content is the number of the first one.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_IMB field. */
+#define CAN_RD_ESR2_IMB(base) ((CAN_ESR2_REG(base) & CAN_ESR2_IMB_MASK) >> CAN_ESR2_IMB_SHIFT)
+#define CAN_BRD_ESR2_IMB(base) (BITBAND_ACCESS32(&CAN_ESR2_REG(base), CAN_ESR2_IMB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR2, field VPS[14] (RO)
+ *
+ * This bit indicates whether IMB and LPTM contents are currently valid or not.
+ * VPS is asserted upon every complete Tx arbitration process unless the CPU
+ * writes to Control and Status word of a Mailbox that has already been scanned, that
+ * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
+ * If there is no inactive Mailbox and only one Tx Mailbox that is being
+ * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
+ * arbitration process or upon a write to Control and Status word of any Mailbox.
+ * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
+ * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
+ * in C/S of a MB that is being transmitted (pending abort), or any write attempt
+ * into a Tx MB with IFLAG set is blocked.
+ *
+ * Values:
+ * - 0b0 - Contents of IMB and LPTM are invalid.
+ * - 0b1 - Contents of IMB and LPTM are valid.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_VPS field. */
+#define CAN_RD_ESR2_VPS(base) ((CAN_ESR2_REG(base) & CAN_ESR2_VPS_MASK) >> CAN_ESR2_VPS_SHIFT)
+#define CAN_BRD_ESR2_VPS(base) (BITBAND_ACCESS32(&CAN_ESR2_REG(base), CAN_ESR2_VPS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR2, field LPTM[22:16] (RO)
+ *
+ * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
+ * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
+ * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
+ * negated then the Mailbox indicated is the one that has the greatest arbitration
+ * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
+ * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
+ * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
+ * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
+ * updated with its Mailbox number.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_LPTM field. */
+#define CAN_RD_ESR2_LPTM(base) ((CAN_ESR2_REG(base) & CAN_ESR2_LPTM_MASK) >> CAN_ESR2_LPTM_SHIFT)
+#define CAN_BRD_ESR2_LPTM(base) (CAN_RD_ESR2_LPTM(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CRCR - CRC Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CRCR - CRC Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides information about the CRC of transmitted messages.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CRCR register
+ */
+/*@{*/
+#define CAN_RD_CRCR(base)        (CAN_CRCR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CRCR bitfields
+ */
+
+/*!
+ * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
+ *
+ * This field indicates the CRC value of the last message transmitted. This
+ * field is updated at the same time the Tx Interrupt Flag is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CRCR_TXCRC field. */
+#define CAN_RD_CRCR_TXCRC(base) ((CAN_CRCR_REG(base) & CAN_CRCR_TXCRC_MASK) >> CAN_CRCR_TXCRC_SHIFT)
+#define CAN_BRD_CRCR_TXCRC(base) (CAN_RD_CRCR_TXCRC(base))
+/*@}*/
+
+/*!
+ * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
+ *
+ * This field indicates the number of the Mailbox corresponding to the value in
+ * TXCRC field.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CRCR_MBCRC field. */
+#define CAN_RD_CRCR_MBCRC(base) ((CAN_CRCR_REG(base) & CAN_CRCR_MBCRC_MASK) >> CAN_CRCR_MBCRC_SHIFT)
+#define CAN_BRD_CRCR_MBCRC(base) (CAN_RD_CRCR_MBCRC(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXFGMASK - Rx FIFO Global Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
+ * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
+ * according to CTRL2[RFFN] field setting. This register can only be written in
+ * Freeze mode as it is blocked by hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXFGMASK register
+ */
+/*@{*/
+#define CAN_RD_RXFGMASK(base)    (CAN_RXFGMASK_REG(base))
+#define CAN_WR_RXFGMASK(base, value) (CAN_RXFGMASK_REG(base) = (value))
+#define CAN_RMW_RXFGMASK(base, mask, value) (CAN_WR_RXFGMASK(base, (CAN_RD_RXFGMASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) |  (value)))
+#define CAN_CLR_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) & ~(value)))
+#define CAN_TOG_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXFIR - Rx FIFO Information Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXFIR - Rx FIFO Information Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFIR provides information on Rx FIFO. This register is the port through
+ * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
+ * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
+ * well as its output is updated whenever the output of the Rx FIFO is updated
+ * with the next message. See Section "Rx FIFO" for instructions on reading this
+ * register.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXFIR register
+ */
+/*@{*/
+#define CAN_RD_RXFIR(base)       (CAN_RXFIR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_RXFIR bitfields
+ */
+
+/*!
+ * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
+ *
+ * This field indicates which Identifier Acceptance Filter was hit by the
+ * received message that is in the output of the Rx FIFO. If multiple filters match the
+ * incoming message ID then the first matching IDAF found (lowest number) by the
+ * matching process is indicated. This field is valid only while the
+ * IFLAG[BUF5I] is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_RXFIR_IDHIT field. */
+#define CAN_RD_RXFIR_IDHIT(base) ((CAN_RXFIR_REG(base) & CAN_RXFIR_IDHIT_MASK) >> CAN_RXFIR_IDHIT_SHIFT)
+#define CAN_BRD_RXFIR_IDHIT(base) (CAN_RD_RXFIR_IDHIT(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CS - Message Buffer 0 CS Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CS - Message Buffer 0 CS Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_CS register
+ */
+/*@{*/
+#define CAN_RD_CS(base, index)   (CAN_CS_REG(base, index))
+#define CAN_WR_CS(base, index, value) (CAN_CS_REG(base, index) = (value))
+#define CAN_RMW_CS(base, index, mask, value) (CAN_WR_CS(base, index, (CAN_RD_CS(base, index) & ~(mask)) | (value)))
+#define CAN_SET_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) |  (value)))
+#define CAN_CLR_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) & ~(value)))
+#define CAN_TOG_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CS bitfields
+ */
+
+/*!
+ * @name Register CAN_CS, field TIME_STAMP[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_TIME_STAMP field. */
+#define CAN_RD_CS_TIME_STAMP(base, index) ((CAN_CS_REG(base, index) & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT)
+#define CAN_BRD_CS_TIME_STAMP(base, index) (CAN_RD_CS_TIME_STAMP(base, index))
+
+/*! @brief Set the TIME_STAMP field to a new value. */
+#define CAN_WR_CS_TIME_STAMP(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_TIME_STAMP_MASK, CAN_CS_TIME_STAMP(value)))
+#define CAN_BWR_CS_TIME_STAMP(base, index, value) (CAN_WR_CS_TIME_STAMP(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field DLC[19:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_DLC field. */
+#define CAN_RD_CS_DLC(base, index) ((CAN_CS_REG(base, index) & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT)
+#define CAN_BRD_CS_DLC(base, index) (CAN_RD_CS_DLC(base, index))
+
+/*! @brief Set the DLC field to a new value. */
+#define CAN_WR_CS_DLC(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_DLC_MASK, CAN_CS_DLC(value)))
+#define CAN_BWR_CS_DLC(base, index, value) (CAN_WR_CS_DLC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field RTR[20] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_RTR field. */
+#define CAN_RD_CS_RTR(base, index) ((CAN_CS_REG(base, index) & CAN_CS_RTR_MASK) >> CAN_CS_RTR_SHIFT)
+#define CAN_BRD_CS_RTR(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_RTR_SHIFT))
+
+/*! @brief Set the RTR field to a new value. */
+#define CAN_WR_CS_RTR(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_RTR_MASK, CAN_CS_RTR(value)))
+#define CAN_BWR_CS_RTR(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_RTR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field IDE[21] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_IDE field. */
+#define CAN_RD_CS_IDE(base, index) ((CAN_CS_REG(base, index) & CAN_CS_IDE_MASK) >> CAN_CS_IDE_SHIFT)
+#define CAN_BRD_CS_IDE(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_IDE_SHIFT))
+
+/*! @brief Set the IDE field to a new value. */
+#define CAN_WR_CS_IDE(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_IDE_MASK, CAN_CS_IDE(value)))
+#define CAN_BWR_CS_IDE(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_IDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field SRR[22] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_SRR field. */
+#define CAN_RD_CS_SRR(base, index) ((CAN_CS_REG(base, index) & CAN_CS_SRR_MASK) >> CAN_CS_SRR_SHIFT)
+#define CAN_BRD_CS_SRR(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_SRR_SHIFT))
+
+/*! @brief Set the SRR field to a new value. */
+#define CAN_WR_CS_SRR(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_SRR_MASK, CAN_CS_SRR(value)))
+#define CAN_BWR_CS_SRR(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_SRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field CODE[27:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_CODE field. */
+#define CAN_RD_CS_CODE(base, index) ((CAN_CS_REG(base, index) & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT)
+#define CAN_BRD_CS_CODE(base, index) (CAN_RD_CS_CODE(base, index))
+
+/*! @brief Set the CODE field to a new value. */
+#define CAN_WR_CS_CODE(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_CODE_MASK, CAN_CS_CODE(value)))
+#define CAN_BWR_CS_CODE(base, index, value) (CAN_WR_CS_CODE(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ID - Message Buffer 0 ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ID - Message Buffer 0 ID Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_ID register
+ */
+/*@{*/
+#define CAN_RD_ID(base, index)   (CAN_ID_REG(base, index))
+#define CAN_WR_ID(base, index, value) (CAN_ID_REG(base, index) = (value))
+#define CAN_RMW_ID(base, index, mask, value) (CAN_WR_ID(base, index, (CAN_RD_ID(base, index) & ~(mask)) | (value)))
+#define CAN_SET_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) |  (value)))
+#define CAN_CLR_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) & ~(value)))
+#define CAN_TOG_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ID bitfields
+ */
+
+/*!
+ * @name Register CAN_ID, field EXT[17:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_EXT field. */
+#define CAN_RD_ID_EXT(base, index) ((CAN_ID_REG(base, index) & CAN_ID_EXT_MASK) >> CAN_ID_EXT_SHIFT)
+#define CAN_BRD_ID_EXT(base, index) (CAN_RD_ID_EXT(base, index))
+
+/*! @brief Set the EXT field to a new value. */
+#define CAN_WR_ID_EXT(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_EXT_MASK, CAN_ID_EXT(value)))
+#define CAN_BWR_ID_EXT(base, index, value) (CAN_WR_ID_EXT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ID, field STD[28:18] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_STD field. */
+#define CAN_RD_ID_STD(base, index) ((CAN_ID_REG(base, index) & CAN_ID_STD_MASK) >> CAN_ID_STD_SHIFT)
+#define CAN_BRD_ID_STD(base, index) (CAN_RD_ID_STD(base, index))
+
+/*! @brief Set the STD field to a new value. */
+#define CAN_WR_ID_STD(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_STD_MASK, CAN_ID_STD(value)))
+#define CAN_BWR_ID_STD(base, index, value) (CAN_WR_ID_STD(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ID, field PRIO[31:29] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_PRIO field. */
+#define CAN_RD_ID_PRIO(base, index) ((CAN_ID_REG(base, index) & CAN_ID_PRIO_MASK) >> CAN_ID_PRIO_SHIFT)
+#define CAN_BRD_ID_PRIO(base, index) (CAN_RD_ID_PRIO(base, index))
+
+/*! @brief Set the PRIO field to a new value. */
+#define CAN_WR_ID_PRIO(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_PRIO_MASK, CAN_ID_PRIO(value)))
+#define CAN_BWR_ID_PRIO(base, index, value) (CAN_WR_ID_PRIO(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_WORD0 - Message Buffer 0 WORD0 Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_WORD0 - Message Buffer 0 WORD0 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_WORD0 register
+ */
+/*@{*/
+#define CAN_RD_WORD0(base, index) (CAN_WORD0_REG(base, index))
+#define CAN_WR_WORD0(base, index, value) (CAN_WORD0_REG(base, index) = (value))
+#define CAN_RMW_WORD0(base, index, mask, value) (CAN_WR_WORD0(base, index, (CAN_RD_WORD0(base, index) & ~(mask)) | (value)))
+#define CAN_SET_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) |  (value)))
+#define CAN_CLR_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) & ~(value)))
+#define CAN_TOG_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_WORD0 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_3[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_3 field. */
+#define CAN_RD_WORD0_DATA_BYTE_3(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_3_MASK) >> CAN_WORD0_DATA_BYTE_3_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_3(base, index) (CAN_RD_WORD0_DATA_BYTE_3(base, index))
+
+/*! @brief Set the DATA_BYTE_3 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_3(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_3_MASK, CAN_WORD0_DATA_BYTE_3(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_3(base, index, value) (CAN_WR_WORD0_DATA_BYTE_3(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_2[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_2 field. */
+#define CAN_RD_WORD0_DATA_BYTE_2(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_2_MASK) >> CAN_WORD0_DATA_BYTE_2_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_2(base, index) (CAN_RD_WORD0_DATA_BYTE_2(base, index))
+
+/*! @brief Set the DATA_BYTE_2 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_2(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_2_MASK, CAN_WORD0_DATA_BYTE_2(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_2(base, index, value) (CAN_WR_WORD0_DATA_BYTE_2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_1[23:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_1 field. */
+#define CAN_RD_WORD0_DATA_BYTE_1(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_1_MASK) >> CAN_WORD0_DATA_BYTE_1_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_1(base, index) (CAN_RD_WORD0_DATA_BYTE_1(base, index))
+
+/*! @brief Set the DATA_BYTE_1 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_1(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_1_MASK, CAN_WORD0_DATA_BYTE_1(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_1(base, index, value) (CAN_WR_WORD0_DATA_BYTE_1(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_0[31:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_0 field. */
+#define CAN_RD_WORD0_DATA_BYTE_0(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_0_MASK) >> CAN_WORD0_DATA_BYTE_0_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_0(base, index) (CAN_RD_WORD0_DATA_BYTE_0(base, index))
+
+/*! @brief Set the DATA_BYTE_0 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_0(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_0_MASK, CAN_WORD0_DATA_BYTE_0(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_0(base, index, value) (CAN_WR_WORD0_DATA_BYTE_0(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_WORD1 - Message Buffer 0 WORD1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_WORD1 - Message Buffer 0 WORD1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_WORD1 register
+ */
+/*@{*/
+#define CAN_RD_WORD1(base, index) (CAN_WORD1_REG(base, index))
+#define CAN_WR_WORD1(base, index, value) (CAN_WORD1_REG(base, index) = (value))
+#define CAN_RMW_WORD1(base, index, mask, value) (CAN_WR_WORD1(base, index, (CAN_RD_WORD1(base, index) & ~(mask)) | (value)))
+#define CAN_SET_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) |  (value)))
+#define CAN_CLR_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) & ~(value)))
+#define CAN_TOG_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_WORD1 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_7[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_7 field. */
+#define CAN_RD_WORD1_DATA_BYTE_7(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_7_MASK) >> CAN_WORD1_DATA_BYTE_7_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_7(base, index) (CAN_RD_WORD1_DATA_BYTE_7(base, index))
+
+/*! @brief Set the DATA_BYTE_7 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_7(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_7_MASK, CAN_WORD1_DATA_BYTE_7(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_7(base, index, value) (CAN_WR_WORD1_DATA_BYTE_7(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_6[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_6 field. */
+#define CAN_RD_WORD1_DATA_BYTE_6(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_6_MASK) >> CAN_WORD1_DATA_BYTE_6_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_6(base, index) (CAN_RD_WORD1_DATA_BYTE_6(base, index))
+
+/*! @brief Set the DATA_BYTE_6 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_6(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_6_MASK, CAN_WORD1_DATA_BYTE_6(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_6(base, index, value) (CAN_WR_WORD1_DATA_BYTE_6(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_5[23:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_5 field. */
+#define CAN_RD_WORD1_DATA_BYTE_5(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_5_MASK) >> CAN_WORD1_DATA_BYTE_5_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_5(base, index) (CAN_RD_WORD1_DATA_BYTE_5(base, index))
+
+/*! @brief Set the DATA_BYTE_5 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_5(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_5_MASK, CAN_WORD1_DATA_BYTE_5(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_5(base, index, value) (CAN_WR_WORD1_DATA_BYTE_5(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_4[31:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_4 field. */
+#define CAN_RD_WORD1_DATA_BYTE_4(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_4_MASK) >> CAN_WORD1_DATA_BYTE_4_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_4(base, index) (CAN_RD_WORD1_DATA_BYTE_4(base, index))
+
+/*! @brief Set the DATA_BYTE_4 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_4(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_4_MASK, CAN_WORD1_DATA_BYTE_4(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_4(base, index, value) (CAN_WR_WORD1_DATA_BYTE_4(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXIMR - Rx Individual Mask Registers
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXIMR - Rx Individual Mask Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers are located in RAM. RXIMR are used as acceptance masks for ID
+ * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
+ * register is provided for each available Mailbox, providing ID masking
+ * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
+ * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
+ * Table elements on a one-to-one correspondence depending on the setting of
+ * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
+ * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
+ * are not affected by reset and must be explicitly initialized prior to any
+ * reception.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXIMR register
+ */
+/*@{*/
+#define CAN_RD_RXIMR(base, index) (CAN_RXIMR_REG(base, index))
+#define CAN_WR_RXIMR(base, index, value) (CAN_RXIMR_REG(base, index) = (value))
+#define CAN_RMW_RXIMR(base, index, mask, value) (CAN_WR_RXIMR(base, index, (CAN_RD_RXIMR(base, index) & ~(mask)) | (value)))
+#define CAN_SET_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) |  (value)))
+#define CAN_CLR_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) & ~(value)))
+#define CAN_TOG_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 CAU
+ *
+ * Memory Mapped Cryptographic Acceleration Unit (MMCAU)
+ *
+ * Registers defined in this header file:
+ * - CAU_DIRECT - Direct access register 0
+ * - CAU_LDR_CASR - Status register - Load Register command
+ * - CAU_LDR_CAA - Accumulator register - Load Register command
+ * - CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ * - CAU_STR_CASR - Status register - Store Register command
+ * - CAU_STR_CAA - Accumulator register - Store Register command
+ * - CAU_STR_CA - General Purpose Register 0 - Store Register command
+ * - CAU_ADR_CASR - Status register - Add Register command
+ * - CAU_ADR_CAA - Accumulator register - Add to register command
+ * - CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ * - CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ * - CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ * - CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ * - CAU_XOR_CASR - Status register - Exclusive Or command
+ * - CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ * - CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ * - CAU_ROTL_CASR - Status register - Rotate Left command
+ * - CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ * - CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ * - CAU_AESC_CASR - Status register - AES Column Operation command
+ * - CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ * - CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ * - CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ * - CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ * - CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ */
+
+#define CAU_INSTANCE_COUNT (1U) /*!< Number of instances of the CAU module. */
+#define CAU_IDX (0U) /*!< Instance number for CAU. */
+
+/*******************************************************************************
+ * CAU_DIRECT - Direct access register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_DIRECT - Direct access register 0 (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_DIRECT register
+ */
+/*@{*/
+#define CAU_WR_DIRECT(base, index, value) (CAU_DIRECT_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CASR - Status register - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CASR - Status register - Load Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CASR register
+ */
+/*@{*/
+#define CAU_WR_LDR_CASR(base, value) (CAU_LDR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_LDR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_LDR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_LDR_CASR_IC(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_IC(value)))
+#define CAU_BWR_LDR_CASR_IC(base, value) (CAU_WR_LDR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_LDR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_LDR_CASR_DPE(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_DPE(value)))
+#define CAU_BWR_LDR_CASR_DPE(base, value) (CAU_WR_LDR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_LDR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_LDR_CASR_VER(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_VER(value)))
+#define CAU_BWR_LDR_CASR_VER(base, value) (CAU_WR_LDR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CAA - Accumulator register - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CAA - Accumulator register - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CAA register
+ */
+/*@{*/
+#define CAU_WR_LDR_CAA(base, value) (CAU_LDR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CA - General Purpose Register 0 - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CA register
+ */
+/*@{*/
+#define CAU_WR_LDR_CA(base, index, value) (CAU_LDR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CASR - Status register - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CASR - Status register - Store Register command (RO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CASR register
+ */
+/*@{*/
+#define CAU_RD_STR_CASR(base)    (CAU_STR_CASR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_STR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_STR_CASR, field IC[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_IC field. */
+#define CAU_RD_STR_CASR_IC(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_IC_MASK) >> CAU_STR_CASR_IC_SHIFT)
+#define CAU_BRD_STR_CASR_IC(base) (CAU_RD_STR_CASR_IC(base))
+/*@}*/
+
+/*!
+ * @name Register CAU_STR_CASR, field DPE[1] (RO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_DPE field. */
+#define CAU_RD_STR_CASR_DPE(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_DPE_MASK) >> CAU_STR_CASR_DPE_SHIFT)
+#define CAU_BRD_STR_CASR_DPE(base) (CAU_RD_STR_CASR_DPE(base))
+/*@}*/
+
+/*!
+ * @name Register CAU_STR_CASR, field VER[31:28] (RO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_VER field. */
+#define CAU_RD_STR_CASR_VER(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_VER_MASK) >> CAU_STR_CASR_VER_SHIFT)
+#define CAU_BRD_STR_CASR_VER(base) (CAU_RD_STR_CASR_VER(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CAA - Accumulator register - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CAA - Accumulator register - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CAA register
+ */
+/*@{*/
+#define CAU_RD_STR_CAA(base)     (CAU_STR_CAA_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CA - General Purpose Register 0 - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CA - General Purpose Register 0 - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CA register
+ */
+/*@{*/
+#define CAU_RD_STR_CA(base, index) (CAU_STR_CA_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CASR - Status register - Add Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CASR - Status register - Add Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CASR register
+ */
+/*@{*/
+#define CAU_WR_ADR_CASR(base, value) (CAU_ADR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_ADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_ADR_CASR_IC(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_IC(value)))
+#define CAU_BWR_ADR_CASR_IC(base, value) (CAU_WR_ADR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_ADR_CASR_DPE(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_DPE(value)))
+#define CAU_BWR_ADR_CASR_DPE(base, value) (CAU_WR_ADR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_ADR_CASR_VER(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_VER(value)))
+#define CAU_BWR_ADR_CASR_VER(base, value) (CAU_WR_ADR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CAA - Accumulator register - Add to register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CAA - Accumulator register - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CAA register
+ */
+/*@{*/
+#define CAU_WR_ADR_CAA(base, value) (CAU_ADR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CA - General Purpose Register 0 - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CA register
+ */
+/*@{*/
+#define CAU_WR_ADR_CA(base, index, value) (CAU_ADR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CASR - Status register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CASR register
+ */
+/*@{*/
+#define CAU_WR_RADR_CASR(base, value) (CAU_RADR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_RADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_RADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_RADR_CASR_IC(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_IC(value)))
+#define CAU_BWR_RADR_CASR_IC(base, value) (CAU_WR_RADR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_RADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_RADR_CASR_DPE(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_DPE(value)))
+#define CAU_BWR_RADR_CASR_DPE(base, value) (CAU_WR_RADR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_RADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_RADR_CASR_VER(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_VER(value)))
+#define CAU_BWR_RADR_CASR_VER(base, value) (CAU_WR_RADR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CAA register
+ */
+/*@{*/
+#define CAU_WR_RADR_CAA(base, value) (CAU_RADR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CA register
+ */
+/*@{*/
+#define CAU_WR_RADR_CA(base, index, value) (CAU_RADR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CASR - Status register - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CASR - Status register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CASR register
+ */
+/*@{*/
+#define CAU_WR_XOR_CASR(base, value) (CAU_XOR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_XOR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_XOR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_XOR_CASR_IC(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_IC(value)))
+#define CAU_BWR_XOR_CASR_IC(base, value) (CAU_WR_XOR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_XOR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_XOR_CASR_DPE(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_DPE(value)))
+#define CAU_BWR_XOR_CASR_DPE(base, value) (CAU_WR_XOR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_XOR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_XOR_CASR_VER(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_VER(value)))
+#define CAU_BWR_XOR_CASR_VER(base, value) (CAU_WR_XOR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CAA register
+ */
+/*@{*/
+#define CAU_WR_XOR_CAA(base, value) (CAU_XOR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CA register
+ */
+/*@{*/
+#define CAU_WR_XOR_CA(base, index, value) (CAU_XOR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CASR - Status register - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CASR - Status register - Rotate Left command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CASR register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CASR(base, value) (CAU_ROTL_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_ROTL_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ROTL_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_ROTL_CASR_IC(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_IC(value)))
+#define CAU_BWR_ROTL_CASR_IC(base, value) (CAU_WR_ROTL_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ROTL_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_ROTL_CASR_DPE(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_DPE(value)))
+#define CAU_BWR_ROTL_CASR_DPE(base, value) (CAU_WR_ROTL_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_ROTL_CASR_VER(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_VER(value)))
+#define CAU_BWR_ROTL_CASR_VER(base, value) (CAU_WR_ROTL_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CAA register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CAA(base, value) (CAU_ROTL_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CA register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CA(base, index, value) (CAU_ROTL_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CASR - Status register - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CASR - Status register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CASR register
+ */
+/*@{*/
+#define CAU_WR_AESC_CASR(base, value) (CAU_AESC_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_AESC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_AESC_CASR_IC(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_IC(value)))
+#define CAU_BWR_AESC_CASR_IC(base, value) (CAU_WR_AESC_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_AESC_CASR_DPE(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_DPE(value)))
+#define CAU_BWR_AESC_CASR_DPE(base, value) (CAU_WR_AESC_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_AESC_CASR_VER(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_VER(value)))
+#define CAU_BWR_AESC_CASR_VER(base, value) (CAU_WR_AESC_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CAA register
+ */
+/*@{*/
+#define CAU_WR_AESC_CAA(base, value) (CAU_AESC_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CA register
+ */
+/*@{*/
+#define CAU_WR_AESC_CA(base, index, value) (CAU_AESC_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CASR - Status register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CASR register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CASR(base, value) (CAU_AESIC_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_AESIC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESIC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_AESIC_CASR_IC(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_IC(value)))
+#define CAU_BWR_AESIC_CASR_IC(base, value) (CAU_WR_AESIC_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESIC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_AESIC_CASR_DPE(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_DPE(value)))
+#define CAU_BWR_AESIC_CASR_DPE(base, value) (CAU_WR_AESIC_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_AESIC_CASR_VER(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_VER(value)))
+#define CAU_BWR_AESIC_CASR_VER(base, value) (CAU_WR_AESIC_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CAA register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CAA(base, value) (CAU_AESIC_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CA register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CA(base, index, value) (CAU_AESIC_CA_REG(base, index) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CMP
+ *
+ * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
+ *
+ * Registers defined in this header file:
+ * - CMP_CR0 - CMP Control Register 0
+ * - CMP_CR1 - CMP Control Register 1
+ * - CMP_FPR - CMP Filter Period Register
+ * - CMP_SCR - CMP Status and Control Register
+ * - CMP_DACCR - DAC Control Register
+ * - CMP_MUXCR - MUX Control Register
+ */
+
+#define CMP_INSTANCE_COUNT (3U) /*!< Number of instances of the CMP module. */
+#define CMP0_IDX (0U) /*!< Instance number for CMP0. */
+#define CMP1_IDX (1U) /*!< Instance number for CMP1. */
+#define CMP2_IDX (2U) /*!< Instance number for CMP2. */
+
+/*******************************************************************************
+ * CMP_CR0 - CMP Control Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR0 - CMP Control Register 0 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR0 register
+ */
+/*@{*/
+#define CMP_RD_CR0(base)         (CMP_CR0_REG(base))
+#define CMP_WR_CR0(base, value)  (CMP_CR0_REG(base) = (value))
+#define CMP_RMW_CR0(base, mask, value) (CMP_WR_CR0(base, (CMP_RD_CR0(base) & ~(mask)) | (value)))
+#define CMP_SET_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) |  (value)))
+#define CMP_CLR_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) & ~(value)))
+#define CMP_TOG_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR0 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
+ *
+ * Defines the programmable hysteresis level. The hysteresis values associated
+ * with each level are device-specific. See the Data Sheet of the device for the
+ * exact values.
+ *
+ * Values:
+ * - 0b00 - Level 0
+ * - 0b01 - Level 1
+ * - 0b10 - Level 2
+ * - 0b11 - Level 3
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
+#define CMP_RD_CR0_HYSTCTR(base) ((CMP_CR0_REG(base) & CMP_CR0_HYSTCTR_MASK) >> CMP_CR0_HYSTCTR_SHIFT)
+#define CMP_BRD_CR0_HYSTCTR(base) (CMP_RD_CR0_HYSTCTR(base))
+
+/*! @brief Set the HYSTCTR field to a new value. */
+#define CMP_WR_CR0_HYSTCTR(base, value) (CMP_RMW_CR0(base, CMP_CR0_HYSTCTR_MASK, CMP_CR0_HYSTCTR(value)))
+#define CMP_BWR_CR0_HYSTCTR(base, value) (CMP_WR_CR0_HYSTCTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
+ *
+ * Represents the number of consecutive samples that must agree prior to the
+ * comparator ouput filter accepting a new output state. For information regarding
+ * filter programming and latency, see the Functional descriptionThe CMP module
+ * can be used to compare two analog input voltages applied to INP and INM. .
+ *
+ * Values:
+ * - 0b000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not
+ *     a legal state, and is not recommended. If SE = 0, COUT = COUTA.
+ * - 0b001 - One sample must agree. The comparator output is simply sampled.
+ * - 0b010 - 2 consecutive samples must agree.
+ * - 0b011 - 3 consecutive samples must agree.
+ * - 0b100 - 4 consecutive samples must agree.
+ * - 0b101 - 5 consecutive samples must agree.
+ * - 0b110 - 6 consecutive samples must agree.
+ * - 0b111 - 7 consecutive samples must agree.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
+#define CMP_RD_CR0_FILTER_CNT(base) ((CMP_CR0_REG(base) & CMP_CR0_FILTER_CNT_MASK) >> CMP_CR0_FILTER_CNT_SHIFT)
+#define CMP_BRD_CR0_FILTER_CNT(base) (CMP_RD_CR0_FILTER_CNT(base))
+
+/*! @brief Set the FILTER_CNT field to a new value. */
+#define CMP_WR_CR0_FILTER_CNT(base, value) (CMP_RMW_CR0(base, CMP_CR0_FILTER_CNT_MASK, CMP_CR0_FILTER_CNT(value)))
+#define CMP_BWR_CR0_FILTER_CNT(base, value) (CMP_WR_CR0_FILTER_CNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_CR1 - CMP Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR1 - CMP Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR1 register
+ */
+/*@{*/
+#define CMP_RD_CR1(base)         (CMP_CR1_REG(base))
+#define CMP_WR_CR1(base, value)  (CMP_CR1_REG(base) = (value))
+#define CMP_RMW_CR1(base, mask, value) (CMP_WR_CR1(base, (CMP_RD_CR1(base) & ~(mask)) | (value)))
+#define CMP_SET_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) |  (value)))
+#define CMP_CLR_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) & ~(value)))
+#define CMP_TOG_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR1 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR1, field EN[0] (RW)
+ *
+ * Enables the Analog Comparator module. When the module is not enabled, it
+ * remains in the off state, and consumes no power. When the user selects the same
+ * input from analog mux to the positive and negative port, the comparator is
+ * disabled automatically.
+ *
+ * Values:
+ * - 0b0 - Analog Comparator is disabled.
+ * - 0b1 - Analog Comparator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_EN field. */
+#define CMP_RD_CR1_EN(base)  ((CMP_CR1_REG(base) & CMP_CR1_EN_MASK) >> CMP_CR1_EN_SHIFT)
+#define CMP_BRD_CR1_EN(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT))
+
+/*! @brief Set the EN field to a new value. */
+#define CMP_WR_CR1_EN(base, value) (CMP_RMW_CR1(base, CMP_CR1_EN_MASK, CMP_CR1_EN(value)))
+#define CMP_BWR_CR1_EN(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field OPE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - CMPO is not available on the associated CMPO output pin. If the
+ *     comparator does not own the pin, this field has no effect.
+ * - 0b1 - CMPO is available on the associated CMPO output pin. The comparator
+ *     output (CMPO) is driven out on the associated CMPO output pin if the
+ *     comparator owns the pin. If the comparator does not own the field, this bit has
+ *     no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_OPE field. */
+#define CMP_RD_CR1_OPE(base) ((CMP_CR1_REG(base) & CMP_CR1_OPE_MASK) >> CMP_CR1_OPE_SHIFT)
+#define CMP_BRD_CR1_OPE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT))
+
+/*! @brief Set the OPE field to a new value. */
+#define CMP_WR_CR1_OPE(base, value) (CMP_RMW_CR1(base, CMP_CR1_OPE_MASK, CMP_CR1_OPE(value)))
+#define CMP_BWR_CR1_OPE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field COS[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Set the filtered comparator output (CMPO) to equal COUT.
+ * - 0b1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_COS field. */
+#define CMP_RD_CR1_COS(base) ((CMP_CR1_REG(base) & CMP_CR1_COS_MASK) >> CMP_CR1_COS_SHIFT)
+#define CMP_BRD_CR1_COS(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT))
+
+/*! @brief Set the COS field to a new value. */
+#define CMP_WR_CR1_COS(base, value) (CMP_RMW_CR1(base, CMP_CR1_COS_MASK, CMP_CR1_COS(value)))
+#define CMP_BWR_CR1_COS(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field INV[3] (RW)
+ *
+ * Allows selection of the polarity of the analog comparator function. It is
+ * also driven to the COUT output, on both the device pin and as SCR[COUT], when
+ * OPE=0.
+ *
+ * Values:
+ * - 0b0 - Does not invert the comparator output.
+ * - 0b1 - Inverts the comparator output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_INV field. */
+#define CMP_RD_CR1_INV(base) ((CMP_CR1_REG(base) & CMP_CR1_INV_MASK) >> CMP_CR1_INV_SHIFT)
+#define CMP_BRD_CR1_INV(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT))
+
+/*! @brief Set the INV field to a new value. */
+#define CMP_WR_CR1_INV(base, value) (CMP_RMW_CR1(base, CMP_CR1_INV_MASK, CMP_CR1_INV(value)))
+#define CMP_BWR_CR1_INV(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field PMODE[4] (RW)
+ *
+ * See the electrical specifications table in the device Data Sheet for details.
+ *
+ * Values:
+ * - 0b0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
+ *     output propagation delay and lower current consumption.
+ * - 0b1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has
+ *     faster output propagation delay and higher current consumption.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_PMODE field. */
+#define CMP_RD_CR1_PMODE(base) ((CMP_CR1_REG(base) & CMP_CR1_PMODE_MASK) >> CMP_CR1_PMODE_SHIFT)
+#define CMP_BRD_CR1_PMODE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT))
+
+/*! @brief Set the PMODE field to a new value. */
+#define CMP_WR_CR1_PMODE(base, value) (CMP_RMW_CR1(base, CMP_CR1_PMODE_MASK, CMP_CR1_PMODE(value)))
+#define CMP_BWR_CR1_PMODE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field WE[6] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0b0 - Windowing mode is not selected.
+ * - 0b1 - Windowing mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_WE field. */
+#define CMP_RD_CR1_WE(base)  ((CMP_CR1_REG(base) & CMP_CR1_WE_MASK) >> CMP_CR1_WE_SHIFT)
+#define CMP_BRD_CR1_WE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT))
+
+/*! @brief Set the WE field to a new value. */
+#define CMP_WR_CR1_WE(base, value) (CMP_RMW_CR1(base, CMP_CR1_WE_MASK, CMP_CR1_WE(value)))
+#define CMP_BWR_CR1_WE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field SE[7] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0b0 - Sampling mode is not selected.
+ * - 0b1 - Sampling mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_SE field. */
+#define CMP_RD_CR1_SE(base)  ((CMP_CR1_REG(base) & CMP_CR1_SE_MASK) >> CMP_CR1_SE_SHIFT)
+#define CMP_BRD_CR1_SE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT))
+
+/*! @brief Set the SE field to a new value. */
+#define CMP_WR_CR1_SE(base, value) (CMP_RMW_CR1(base, CMP_CR1_SE_MASK, CMP_CR1_SE(value)))
+#define CMP_BWR_CR1_SE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_FPR - CMP Filter Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_FPR - CMP Filter Period Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_FPR register
+ */
+/*@{*/
+#define CMP_RD_FPR(base)         (CMP_FPR_REG(base))
+#define CMP_WR_FPR(base, value)  (CMP_FPR_REG(base) = (value))
+#define CMP_RMW_FPR(base, mask, value) (CMP_WR_FPR(base, (CMP_RD_FPR(base) & ~(mask)) | (value)))
+#define CMP_SET_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) |  (value)))
+#define CMP_CLR_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) & ~(value)))
+#define CMP_TOG_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_SCR - CMP Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_SCR - CMP Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_SCR register
+ */
+/*@{*/
+#define CMP_RD_SCR(base)         (CMP_SCR_REG(base))
+#define CMP_WR_SCR(base, value)  (CMP_SCR_REG(base) = (value))
+#define CMP_RMW_SCR(base, mask, value) (CMP_WR_SCR(base, (CMP_RD_SCR(base) & ~(mask)) | (value)))
+#define CMP_SET_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) |  (value)))
+#define CMP_CLR_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) & ~(value)))
+#define CMP_TOG_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_SCR bitfields
+ */
+
+/*!
+ * @name Register CMP_SCR, field COUT[0] (RO)
+ *
+ * Returns the current value of the Analog Comparator output, when read. The
+ * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
+ * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_COUT field. */
+#define CMP_RD_SCR_COUT(base) ((CMP_SCR_REG(base) & CMP_SCR_COUT_MASK) >> CMP_SCR_COUT_SHIFT)
+#define CMP_BRD_SCR_COUT(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_COUT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFF[1] (W1C)
+ *
+ * Detects a falling-edge on COUT, when set, during normal operation. CFF is
+ * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0b0 - Falling-edge on COUT has not been detected.
+ * - 0b1 - Falling-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFF field. */
+#define CMP_RD_SCR_CFF(base) ((CMP_SCR_REG(base) & CMP_SCR_CFF_MASK) >> CMP_SCR_CFF_SHIFT)
+#define CMP_BRD_SCR_CFF(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT))
+
+/*! @brief Set the CFF field to a new value. */
+#define CMP_WR_SCR_CFF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_CFF(value)))
+#define CMP_BWR_SCR_CFF(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFR[2] (W1C)
+ *
+ * Detects a rising-edge on COUT, when set, during normal operation. CFR is
+ * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0b0 - Rising-edge on COUT has not been detected.
+ * - 0b1 - Rising-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFR field. */
+#define CMP_RD_SCR_CFR(base) ((CMP_SCR_REG(base) & CMP_SCR_CFR_MASK) >> CMP_SCR_CFR_SHIFT)
+#define CMP_BRD_SCR_CFR(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT))
+
+/*! @brief Set the CFR field to a new value. */
+#define CMP_WR_SCR_CFR(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK), CMP_SCR_CFR(value)))
+#define CMP_BWR_SCR_CFR(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IEF[3] (RW)
+ *
+ * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFF is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled.
+ * - 0b1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IEF field. */
+#define CMP_RD_SCR_IEF(base) ((CMP_SCR_REG(base) & CMP_SCR_IEF_MASK) >> CMP_SCR_IEF_SHIFT)
+#define CMP_BRD_SCR_IEF(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT))
+
+/*! @brief Set the IEF field to a new value. */
+#define CMP_WR_SCR_IEF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IEF_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IEF(value)))
+#define CMP_BWR_SCR_IEF(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IER[4] (RW)
+ *
+ * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFR is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled.
+ * - 0b1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IER field. */
+#define CMP_RD_SCR_IER(base) ((CMP_SCR_REG(base) & CMP_SCR_IER_MASK) >> CMP_SCR_IER_SHIFT)
+#define CMP_BRD_SCR_IER(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT))
+
+/*! @brief Set the IER field to a new value. */
+#define CMP_WR_SCR_IER(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IER_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IER(value)))
+#define CMP_BWR_SCR_IER(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field DMAEN[6] (RW)
+ *
+ * Enables the DMA transfer triggered from the CMP module. When this field is
+ * set, a DMA request is asserted when CFR or CFF is set.
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_DMAEN field. */
+#define CMP_RD_SCR_DMAEN(base) ((CMP_SCR_REG(base) & CMP_SCR_DMAEN_MASK) >> CMP_SCR_DMAEN_SHIFT)
+#define CMP_BRD_SCR_DMAEN(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define CMP_WR_SCR_DMAEN(base, value) (CMP_RMW_SCR(base, (CMP_SCR_DMAEN_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_DMAEN(value)))
+#define CMP_BWR_SCR_DMAEN(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_DACCR - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_DACCR - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_DACCR register
+ */
+/*@{*/
+#define CMP_RD_DACCR(base)       (CMP_DACCR_REG(base))
+#define CMP_WR_DACCR(base, value) (CMP_DACCR_REG(base) = (value))
+#define CMP_RMW_DACCR(base, mask, value) (CMP_WR_DACCR(base, (CMP_RD_DACCR(base) & ~(mask)) | (value)))
+#define CMP_SET_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) |  (value)))
+#define CMP_CLR_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) & ~(value)))
+#define CMP_TOG_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_DACCR bitfields
+ */
+
+/*!
+ * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
+ *
+ * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
+ * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VOSEL field. */
+#define CMP_RD_DACCR_VOSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VOSEL_MASK) >> CMP_DACCR_VOSEL_SHIFT)
+#define CMP_BRD_DACCR_VOSEL(base) (CMP_RD_DACCR_VOSEL(base))
+
+/*! @brief Set the VOSEL field to a new value. */
+#define CMP_WR_DACCR_VOSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VOSEL_MASK, CMP_DACCR_VOSEL(value)))
+#define CMP_BWR_DACCR_VOSEL(base, value) (CMP_WR_DACCR_VOSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field VRSEL[6] (RW)
+ *
+ * Values:
+ * - 0b0 - V is selected as resistor ladder network supply reference V. in1 in
+ * - 0b1 - V is selected as resistor ladder network supply reference V. in2 in
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VRSEL field. */
+#define CMP_RD_DACCR_VRSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VRSEL_MASK) >> CMP_DACCR_VRSEL_SHIFT)
+#define CMP_BRD_DACCR_VRSEL(base) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT))
+
+/*! @brief Set the VRSEL field to a new value. */
+#define CMP_WR_DACCR_VRSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VRSEL_MASK, CMP_DACCR_VRSEL(value)))
+#define CMP_BWR_DACCR_VRSEL(base, value) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field DACEN[7] (RW)
+ *
+ * Enables the DAC. When the DAC is disabled, it is powered down to conserve
+ * power.
+ *
+ * Values:
+ * - 0b0 - DAC is disabled.
+ * - 0b1 - DAC is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_DACEN field. */
+#define CMP_RD_DACCR_DACEN(base) ((CMP_DACCR_REG(base) & CMP_DACCR_DACEN_MASK) >> CMP_DACCR_DACEN_SHIFT)
+#define CMP_BRD_DACCR_DACEN(base) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT))
+
+/*! @brief Set the DACEN field to a new value. */
+#define CMP_WR_DACCR_DACEN(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_DACEN_MASK, CMP_DACCR_DACEN(value)))
+#define CMP_BWR_DACCR_DACEN(base, value) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_MUXCR - MUX Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_MUXCR - MUX Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_MUXCR register
+ */
+/*@{*/
+#define CMP_RD_MUXCR(base)       (CMP_MUXCR_REG(base))
+#define CMP_WR_MUXCR(base, value) (CMP_MUXCR_REG(base) = (value))
+#define CMP_RMW_MUXCR(base, mask, value) (CMP_WR_MUXCR(base, (CMP_RD_MUXCR(base) & ~(mask)) | (value)))
+#define CMP_SET_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) |  (value)))
+#define CMP_CLR_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) & ~(value)))
+#define CMP_TOG_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_MUXCR bitfields
+ */
+
+/*!
+ * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
+ *
+ * Determines which input is selected for the minus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 0b000 - IN0
+ * - 0b001 - IN1
+ * - 0b010 - IN2
+ * - 0b011 - IN3
+ * - 0b100 - IN4
+ * - 0b101 - IN5
+ * - 0b110 - IN6
+ * - 0b111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_MSEL field. */
+#define CMP_RD_MUXCR_MSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_MSEL_MASK) >> CMP_MUXCR_MSEL_SHIFT)
+#define CMP_BRD_MUXCR_MSEL(base) (CMP_RD_MUXCR_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define CMP_WR_MUXCR_MSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_MSEL_MASK, CMP_MUXCR_MSEL(value)))
+#define CMP_BWR_MUXCR_MSEL(base, value) (CMP_WR_MUXCR_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
+ *
+ * Determines which input is selected for the plus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 0b000 - IN0
+ * - 0b001 - IN1
+ * - 0b010 - IN2
+ * - 0b011 - IN3
+ * - 0b100 - IN4
+ * - 0b101 - IN5
+ * - 0b110 - IN6
+ * - 0b111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSEL field. */
+#define CMP_RD_MUXCR_PSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSEL_MASK) >> CMP_MUXCR_PSEL_SHIFT)
+#define CMP_BRD_MUXCR_PSEL(base) (CMP_RD_MUXCR_PSEL(base))
+
+/*! @brief Set the PSEL field to a new value. */
+#define CMP_WR_MUXCR_PSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSEL_MASK, CMP_MUXCR_PSEL(value)))
+#define CMP_BWR_MUXCR_PSEL(base, value) (CMP_WR_MUXCR_PSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSTM[7] (RW)
+ *
+ * This bit is used to enable to MUX pass through mode. Pass through mode is
+ * always available but for some devices this feature must be always disabled due to
+ * the lack of package pins.
+ *
+ * Values:
+ * - 0b0 - Pass Through Mode is disabled.
+ * - 0b1 - Pass Through Mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSTM field. */
+#define CMP_RD_MUXCR_PSTM(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSTM_MASK) >> CMP_MUXCR_PSTM_SHIFT)
+#define CMP_BRD_MUXCR_PSTM(base) (BITBAND_ACCESS8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT))
+
+/*! @brief Set the PSTM field to a new value. */
+#define CMP_WR_MUXCR_PSTM(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSTM_MASK, CMP_MUXCR_PSTM(value)))
+#define CMP_BWR_MUXCR_PSTM(base, value) (BITBAND_ACCESS8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CMT
+ *
+ * Carrier Modulator Transmitter
+ *
+ * Registers defined in this header file:
+ * - CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ * - CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ * - CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ * - CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ * - CMT_OC - CMT Output Control Register
+ * - CMT_MSC - CMT Modulator Status and Control Register
+ * - CMT_CMD1 - CMT Modulator Data Register Mark High
+ * - CMT_CMD2 - CMT Modulator Data Register Mark Low
+ * - CMT_CMD3 - CMT Modulator Data Register Space High
+ * - CMT_CMD4 - CMT Modulator Data Register Space Low
+ * - CMT_PPS - CMT Primary Prescaler Register
+ * - CMT_DMA - CMT Direct Memory Access Register
+ */
+
+#define CMT_INSTANCE_COUNT (1U) /*!< Number of instances of the CMT module. */
+#define CMT_IDX (0U) /*!< Instance number for CMT. */
+
+/*******************************************************************************
+ * CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary high value for generating the carrier
+ * output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGH1 register
+ */
+/*@{*/
+#define CMT_RD_CGH1(base)        (CMT_CGH1_REG(base))
+#define CMT_WR_CGH1(base, value) (CMT_CGH1_REG(base) = (value))
+#define CMT_RMW_CGH1(base, mask, value) (CMT_WR_CGH1(base, (CMT_RD_CGH1(base) & ~(mask)) | (value)))
+#define CMT_SET_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) |  (value)))
+#define CMT_CLR_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) & ~(value)))
+#define CMT_TOG_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary low value for generating the carrier
+ * output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGL1 register
+ */
+/*@{*/
+#define CMT_RD_CGL1(base)        (CMT_CGL1_REG(base))
+#define CMT_WR_CGL1(base, value) (CMT_CGL1_REG(base) = (value))
+#define CMT_RMW_CGL1(base, mask, value) (CMT_WR_CGL1(base, (CMT_RD_CGL1(base) & ~(mask)) | (value)))
+#define CMT_SET_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) |  (value)))
+#define CMT_CLR_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) & ~(value)))
+#define CMT_TOG_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary high value for generating the
+ * carrier output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGH2 register
+ */
+/*@{*/
+#define CMT_RD_CGH2(base)        (CMT_CGH2_REG(base))
+#define CMT_WR_CGH2(base, value) (CMT_CGH2_REG(base) = (value))
+#define CMT_RMW_CGH2(base, mask, value) (CMT_WR_CGH2(base, (CMT_RD_CGH2(base) & ~(mask)) | (value)))
+#define CMT_SET_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) |  (value)))
+#define CMT_CLR_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) & ~(value)))
+#define CMT_TOG_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary low value for generating the
+ * carrier output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGL2 register
+ */
+/*@{*/
+#define CMT_RD_CGL2(base)        (CMT_CGL2_REG(base))
+#define CMT_WR_CGL2(base, value) (CMT_CGL2_REG(base) = (value))
+#define CMT_RMW_CGL2(base, mask, value) (CMT_WR_CGL2(base, (CMT_RD_CGL2(base) & ~(mask)) | (value)))
+#define CMT_SET_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) |  (value)))
+#define CMT_CLR_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) & ~(value)))
+#define CMT_TOG_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_OC - CMT Output Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_OC - CMT Output Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to control the IRO signal of the CMT module.
+ */
+/*!
+ * @name Constants and macros for entire CMT_OC register
+ */
+/*@{*/
+#define CMT_RD_OC(base)          (CMT_OC_REG(base))
+#define CMT_WR_OC(base, value)   (CMT_OC_REG(base) = (value))
+#define CMT_RMW_OC(base, mask, value) (CMT_WR_OC(base, (CMT_RD_OC(base) & ~(mask)) | (value)))
+#define CMT_SET_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) |  (value)))
+#define CMT_CLR_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) & ~(value)))
+#define CMT_TOG_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_OC bitfields
+ */
+
+/*!
+ * @name Register CMT_OC, field IROPEN[5] (RW)
+ *
+ * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
+ * output that drives out either the CMT transmitter output or the state of IROL
+ * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
+ * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
+ * signal is disabled, it is in a high-impedance state and is unable to draw any
+ * current. This signal is disabled during reset.
+ *
+ * Values:
+ * - 0b0 - The IRO signal is disabled.
+ * - 0b1 - The IRO signal is enabled as output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_IROPEN field. */
+#define CMT_RD_OC_IROPEN(base) ((CMT_OC_REG(base) & CMT_OC_IROPEN_MASK) >> CMT_OC_IROPEN_SHIFT)
+#define CMT_BRD_OC_IROPEN(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT))
+
+/*! @brief Set the IROPEN field to a new value. */
+#define CMT_WR_OC_IROPEN(base, value) (CMT_RMW_OC(base, CMT_OC_IROPEN_MASK, CMT_OC_IROPEN(value)))
+#define CMT_BWR_OC_IROPEN(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_OC, field CMTPOL[6] (RW)
+ *
+ * Controls the polarity of the IRO signal.
+ *
+ * Values:
+ * - 0b0 - The IRO signal is active-low.
+ * - 0b1 - The IRO signal is active-high.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_CMTPOL field. */
+#define CMT_RD_OC_CMTPOL(base) ((CMT_OC_REG(base) & CMT_OC_CMTPOL_MASK) >> CMT_OC_CMTPOL_SHIFT)
+#define CMT_BRD_OC_CMTPOL(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT))
+
+/*! @brief Set the CMTPOL field to a new value. */
+#define CMT_WR_OC_CMTPOL(base, value) (CMT_RMW_OC(base, CMT_OC_CMTPOL_MASK, CMT_OC_CMTPOL(value)))
+#define CMT_BWR_OC_CMTPOL(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_OC, field IROL[7] (RW)
+ *
+ * Reads the state of the IRO latch. Writing to IROL changes the state of the
+ * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_IROL field. */
+#define CMT_RD_OC_IROL(base) ((CMT_OC_REG(base) & CMT_OC_IROL_MASK) >> CMT_OC_IROL_SHIFT)
+#define CMT_BRD_OC_IROL(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT))
+
+/*! @brief Set the IROL field to a new value. */
+#define CMT_WR_OC_IROL(base, value) (CMT_RMW_OC(base, CMT_OC_IROL_MASK, CMT_OC_IROL(value)))
+#define CMT_BWR_OC_IROL(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_MSC - CMT Modulator Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_MSC - CMT Modulator Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the modulator and carrier generator enable (MCGEN),
+ * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
+ * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
+ * (EOCF) status bit.
+ */
+/*!
+ * @name Constants and macros for entire CMT_MSC register
+ */
+/*@{*/
+#define CMT_RD_MSC(base)         (CMT_MSC_REG(base))
+#define CMT_WR_MSC(base, value)  (CMT_MSC_REG(base) = (value))
+#define CMT_RMW_MSC(base, mask, value) (CMT_WR_MSC(base, (CMT_RD_MSC(base) & ~(mask)) | (value)))
+#define CMT_SET_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) |  (value)))
+#define CMT_CLR_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) & ~(value)))
+#define CMT_TOG_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_MSC bitfields
+ */
+
+/*!
+ * @name Register CMT_MSC, field MCGEN[0] (RW)
+ *
+ * Setting MCGEN will initialize the carrier generator and modulator and will
+ * enable all clocks. When enabled, the carrier generator and modulator will
+ * function continuously. When MCGEN is cleared, the current modulator cycle will be
+ * allowed to expire before all carrier and modulator clocks are disabled to save
+ * power and the modulator output is forced low. To prevent spurious operation,
+ * the user should initialize all data and control registers before enabling the
+ * system.
+ *
+ * Values:
+ * - 0b0 - Modulator and carrier generator disabled
+ * - 0b1 - Modulator and carrier generator enabled
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_MCGEN field. */
+#define CMT_RD_MSC_MCGEN(base) ((CMT_MSC_REG(base) & CMT_MSC_MCGEN_MASK) >> CMT_MSC_MCGEN_SHIFT)
+#define CMT_BRD_MSC_MCGEN(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT))
+
+/*! @brief Set the MCGEN field to a new value. */
+#define CMT_WR_MSC_MCGEN(base, value) (CMT_RMW_MSC(base, CMT_MSC_MCGEN_MASK, CMT_MSC_MCGEN(value)))
+#define CMT_BWR_MSC_MCGEN(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EOCIE[1] (RW)
+ *
+ * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
+ *
+ * Values:
+ * - 0b0 - CPU interrupt is disabled.
+ * - 0b1 - CPU interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EOCIE field. */
+#define CMT_RD_MSC_EOCIE(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCIE_MASK) >> CMT_MSC_EOCIE_SHIFT)
+#define CMT_BRD_MSC_EOCIE(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT))
+
+/*! @brief Set the EOCIE field to a new value. */
+#define CMT_WR_MSC_EOCIE(base, value) (CMT_RMW_MSC(base, CMT_MSC_EOCIE_MASK, CMT_MSC_EOCIE(value)))
+#define CMT_BWR_MSC_EOCIE(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field FSK[2] (RW)
+ *
+ * Enables FSK operation.
+ *
+ * Values:
+ * - 0b0 - The CMT operates in Time or Baseband mode.
+ * - 0b1 - The CMT operates in FSK mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_FSK field. */
+#define CMT_RD_MSC_FSK(base) ((CMT_MSC_REG(base) & CMT_MSC_FSK_MASK) >> CMT_MSC_FSK_SHIFT)
+#define CMT_BRD_MSC_FSK(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT))
+
+/*! @brief Set the FSK field to a new value. */
+#define CMT_WR_MSC_FSK(base, value) (CMT_RMW_MSC(base, CMT_MSC_FSK_MASK, CMT_MSC_FSK(value)))
+#define CMT_BWR_MSC_FSK(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field BASE[3] (RW)
+ *
+ * When set, BASE disables the carrier generator and forces the carrier output
+ * high for generation of baseband protocols. When BASE is cleared, the carrier
+ * generator is enabled and the carrier output toggles at the frequency determined
+ * by values stored in the carrier data registers. This field is cleared by
+ * reset. This field is not double-buffered and must not be written to during a
+ * transmission.
+ *
+ * Values:
+ * - 0b0 - Baseband mode is disabled.
+ * - 0b1 - Baseband mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_BASE field. */
+#define CMT_RD_MSC_BASE(base) ((CMT_MSC_REG(base) & CMT_MSC_BASE_MASK) >> CMT_MSC_BASE_SHIFT)
+#define CMT_BRD_MSC_BASE(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT))
+
+/*! @brief Set the BASE field to a new value. */
+#define CMT_WR_MSC_BASE(base, value) (CMT_RMW_MSC(base, CMT_MSC_BASE_MASK, CMT_MSC_BASE(value)))
+#define CMT_BWR_MSC_BASE(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EXSPC[4] (RW)
+ *
+ * Enables the extended space operation.
+ *
+ * Values:
+ * - 0b0 - Extended space is disabled.
+ * - 0b1 - Extended space is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EXSPC field. */
+#define CMT_RD_MSC_EXSPC(base) ((CMT_MSC_REG(base) & CMT_MSC_EXSPC_MASK) >> CMT_MSC_EXSPC_SHIFT)
+#define CMT_BRD_MSC_EXSPC(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT))
+
+/*! @brief Set the EXSPC field to a new value. */
+#define CMT_WR_MSC_EXSPC(base, value) (CMT_RMW_MSC(base, CMT_MSC_EXSPC_MASK, CMT_MSC_EXSPC(value)))
+#define CMT_BWR_MSC_EXSPC(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
+ *
+ * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
+ * divided by 2 ,4, or 8 . This field must not be changed during a transmission
+ * because it is not double-buffered.
+ *
+ * Values:
+ * - 0b00 - IF * 1
+ * - 0b01 - IF * 2
+ * - 0b10 - IF * 4
+ * - 0b11 - IF * 8
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_CMTDIV field. */
+#define CMT_RD_MSC_CMTDIV(base) ((CMT_MSC_REG(base) & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT)
+#define CMT_BRD_MSC_CMTDIV(base) (CMT_RD_MSC_CMTDIV(base))
+
+/*! @brief Set the CMTDIV field to a new value. */
+#define CMT_WR_MSC_CMTDIV(base, value) (CMT_RMW_MSC(base, CMT_MSC_CMTDIV_MASK, CMT_MSC_CMTDIV(value)))
+#define CMT_BWR_MSC_CMTDIV(base, value) (CMT_WR_MSC_CMTDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EOCF[7] (RO)
+ *
+ * Sets when: The modulator is not currently active and MCGEN is set to begin
+ * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
+ * set. This is recognized when a match occurs between the contents of the space
+ * period register and the down counter. At this time, the counter is
+ * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
+ * the space period register is loaded with, possibly new contents of the space
+ * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
+ * access of CMD2 or CMD4, or by the DMA transfer.
+ *
+ * Values:
+ * - 0b0 - End of modulation cycle has not occured since the flag last cleared.
+ * - 0b1 - End of modulator cycle has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EOCF field. */
+#define CMT_RD_MSC_EOCF(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCF_MASK) >> CMT_MSC_EOCF_SHIFT)
+#define CMT_BRD_MSC_EOCF(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD1 - CMT Modulator Data Register Mark High
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD1 register
+ */
+/*@{*/
+#define CMT_RD_CMD1(base)        (CMT_CMD1_REG(base))
+#define CMT_WR_CMD1(base, value) (CMT_CMD1_REG(base) = (value))
+#define CMT_RMW_CMD1(base, mask, value) (CMT_WR_CMD1(base, (CMT_RD_CMD1(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) |  (value)))
+#define CMT_CLR_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) & ~(value)))
+#define CMT_TOG_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD2 - CMT Modulator Data Register Mark Low
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD2 register
+ */
+/*@{*/
+#define CMT_RD_CMD2(base)        (CMT_CMD2_REG(base))
+#define CMT_WR_CMD2(base, value) (CMT_CMD2_REG(base) = (value))
+#define CMT_RMW_CMD2(base, mask, value) (CMT_WR_CMD2(base, (CMT_RD_CMD2(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) |  (value)))
+#define CMT_CLR_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) & ~(value)))
+#define CMT_TOG_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD3 - CMT Modulator Data Register Space High
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD3 - CMT Modulator Data Register Space High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD3 register
+ */
+/*@{*/
+#define CMT_RD_CMD3(base)        (CMT_CMD3_REG(base))
+#define CMT_WR_CMD3(base, value) (CMT_CMD3_REG(base) = (value))
+#define CMT_RMW_CMD3(base, mask, value) (CMT_WR_CMD3(base, (CMT_RD_CMD3(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) |  (value)))
+#define CMT_CLR_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) & ~(value)))
+#define CMT_TOG_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD4 - CMT Modulator Data Register Space Low
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD4 register
+ */
+/*@{*/
+#define CMT_RD_CMD4(base)        (CMT_CMD4_REG(base))
+#define CMT_WR_CMD4(base, value) (CMT_CMD4_REG(base) = (value))
+#define CMT_RMW_CMD4(base, mask, value) (CMT_WR_CMD4(base, (CMT_RD_CMD4(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) |  (value)))
+#define CMT_CLR_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) & ~(value)))
+#define CMT_TOG_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_PPS - CMT Primary Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_PPS - CMT Primary Prescaler Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to set the Primary Prescaler Divider field (PPSDIV).
+ */
+/*!
+ * @name Constants and macros for entire CMT_PPS register
+ */
+/*@{*/
+#define CMT_RD_PPS(base)         (CMT_PPS_REG(base))
+#define CMT_WR_PPS(base, value)  (CMT_PPS_REG(base) = (value))
+#define CMT_RMW_PPS(base, mask, value) (CMT_WR_PPS(base, (CMT_RD_PPS(base) & ~(mask)) | (value)))
+#define CMT_SET_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) |  (value)))
+#define CMT_CLR_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) & ~(value)))
+#define CMT_TOG_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_PPS bitfields
+ */
+
+/*!
+ * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
+ *
+ * Divides the CMT clock to generate the Intermediate Frequency clock enable to
+ * the secondary prescaler.
+ *
+ * Values:
+ * - 0b0000 - Bus clock * 1
+ * - 0b0001 - Bus clock * 2
+ * - 0b0010 - Bus clock * 3
+ * - 0b0011 - Bus clock * 4
+ * - 0b0100 - Bus clock * 5
+ * - 0b0101 - Bus clock * 6
+ * - 0b0110 - Bus clock * 7
+ * - 0b0111 - Bus clock * 8
+ * - 0b1000 - Bus clock * 9
+ * - 0b1001 - Bus clock * 10
+ * - 0b1010 - Bus clock * 11
+ * - 0b1011 - Bus clock * 12
+ * - 0b1100 - Bus clock * 13
+ * - 0b1101 - Bus clock * 14
+ * - 0b1110 - Bus clock * 15
+ * - 0b1111 - Bus clock * 16
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_PPS_PPSDIV field. */
+#define CMT_RD_PPS_PPSDIV(base) ((CMT_PPS_REG(base) & CMT_PPS_PPSDIV_MASK) >> CMT_PPS_PPSDIV_SHIFT)
+#define CMT_BRD_PPS_PPSDIV(base) (CMT_RD_PPS_PPSDIV(base))
+
+/*! @brief Set the PPSDIV field to a new value. */
+#define CMT_WR_PPS_PPSDIV(base, value) (CMT_RMW_PPS(base, CMT_PPS_PPSDIV_MASK, CMT_PPS_PPSDIV(value)))
+#define CMT_BWR_PPS_PPSDIV(base, value) (CMT_WR_PPS_PPSDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_DMA - CMT Direct Memory Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_DMA - CMT Direct Memory Access Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to enable/disable direct memory access (DMA).
+ */
+/*!
+ * @name Constants and macros for entire CMT_DMA register
+ */
+/*@{*/
+#define CMT_RD_DMA(base)         (CMT_DMA_REG(base))
+#define CMT_WR_DMA(base, value)  (CMT_DMA_REG(base) = (value))
+#define CMT_RMW_DMA(base, mask, value) (CMT_WR_DMA(base, (CMT_RD_DMA(base) & ~(mask)) | (value)))
+#define CMT_SET_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) |  (value)))
+#define CMT_CLR_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) & ~(value)))
+#define CMT_TOG_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_DMA bitfields
+ */
+
+/*!
+ * @name Register CMT_DMA, field DMA[0] (RW)
+ *
+ * Enables the DMA protocol.
+ *
+ * Values:
+ * - 0b0 - DMA transfer request and done are disabled.
+ * - 0b1 - DMA transfer request and done are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_DMA_DMA field. */
+#define CMT_RD_DMA_DMA(base) ((CMT_DMA_REG(base) & CMT_DMA_DMA_MASK) >> CMT_DMA_DMA_SHIFT)
+#define CMT_BRD_DMA_DMA(base) (BITBAND_ACCESS8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define CMT_WR_DMA_DMA(base, value) (CMT_RMW_DMA(base, CMT_DMA_DMA_MASK, CMT_DMA_DMA(value)))
+#define CMT_BWR_DMA_DMA(base, value) (BITBAND_ACCESS8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CRC
+ *
+ * Cyclic Redundancy Check
+ *
+ * Registers defined in this header file:
+ * - CRC_DATAL - CRC_DATAL register.
+ * - CRC_DATAH - CRC_DATAH register.
+ * - CRC_DATALL - CRC_DATALL register.
+ * - CRC_DATALU - CRC_DATALU register.
+ * - CRC_DATAHL - CRC_DATAHL register.
+ * - CRC_DATAHU - CRC_DATAHU register.
+ * - CRC_DATA - CRC Data register
+ * - CRC_GPOLY - CRC Polynomial register
+ * - CRC_GPOLYL - CRC_GPOLYL register.
+ * - CRC_GPOLYH - CRC_GPOLYH register.
+ * - CRC_GPOLYLL - CRC_GPOLYLL register.
+ * - CRC_GPOLYLU - CRC_GPOLYLU register.
+ * - CRC_GPOLYHL - CRC_GPOLYHL register.
+ * - CRC_GPOLYHU - CRC_GPOLYHU register.
+ * - CRC_CTRL - CRC Control register
+ * - CRC_CTRLHU - CRC_CTRLHU register.
+ */
+
+#define CRC_INSTANCE_COUNT (1U) /*!< Number of instances of the CRC module. */
+#define CRC_IDX (0U) /*!< Instance number for CRC. */
+
+/*******************************************************************************
+ * CRC_DATALL - CRC_DATALL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATALL - CRC_DATALL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATALL register
+ */
+/*@{*/
+#define CRC_RD_DATALL(base)      (CRC_DATALL_REG(base))
+#define CRC_WR_DATALL(base, value) (CRC_DATALL_REG(base) = (value))
+#define CRC_RMW_DATALL(base, mask, value) (CRC_WR_DATALL(base, (CRC_RD_DATALL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) |  (value)))
+#define CRC_CLR_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) & ~(value)))
+#define CRC_TOG_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAL - CRC_DATAL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAL - CRC_DATAL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAL register
+ */
+/*@{*/
+#define CRC_RD_DATAL(base)       (CRC_DATAL_REG(base))
+#define CRC_WR_DATAL(base, value) (CRC_DATAL_REG(base) = (value))
+#define CRC_RMW_DATAL(base, mask, value) (CRC_WR_DATAL(base, (CRC_RD_DATAL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) |  (value)))
+#define CRC_CLR_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) & ~(value)))
+#define CRC_TOG_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATA - CRC Data register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATA - CRC Data register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * The CRC Data register contains the value of the seed, data, and checksum.
+ * When CTRL[WAS] is set, any write to the data register is regarded as the seed
+ * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
+ * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
+ * not used for programming the seed value, and reads of these fields return an
+ * indeterminate value. In 32-bit CRC mode, all fields are used for programming
+ * the seed value. When programming data values, the values can be written 8 bits,
+ * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
+ * data value written first. After all data values are written, the CRC result
+ * can be read from this data register. In 16-bit CRC mode, the CRC result is
+ * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
+ * result. Reads of this register at any time return the intermediate CRC value,
+ * provided the CRC module is configured.
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATA register
+ */
+/*@{*/
+#define CRC_RD_DATA(base)        (CRC_DATA_REG(base))
+#define CRC_WR_DATA(base, value) (CRC_DATA_REG(base) = (value))
+#define CRC_RMW_DATA(base, mask, value) (CRC_WR_DATA(base, (CRC_RD_DATA(base) & ~(mask)) | (value)))
+#define CRC_SET_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) |  (value)))
+#define CRC_CLR_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) & ~(value)))
+#define CRC_TOG_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_DATA bitfields
+ */
+
+/*!
+ * @name Register CRC_DATA, field LL[7:0] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_LL field. */
+#define CRC_RD_DATA_LL(base) ((CRC_DATA_REG(base) & CRC_DATA_LL_MASK) >> CRC_DATA_LL_SHIFT)
+#define CRC_BRD_DATA_LL(base) (CRC_RD_DATA_LL(base))
+
+/*! @brief Set the LL field to a new value. */
+#define CRC_WR_DATA_LL(base, value) (CRC_RMW_DATA(base, CRC_DATA_LL_MASK, CRC_DATA_LL(value)))
+#define CRC_BWR_DATA_LL(base, value) (CRC_WR_DATA_LL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field LU[15:8] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_LU field. */
+#define CRC_RD_DATA_LU(base) ((CRC_DATA_REG(base) & CRC_DATA_LU_MASK) >> CRC_DATA_LU_SHIFT)
+#define CRC_BRD_DATA_LU(base) (CRC_RD_DATA_LU(base))
+
+/*! @brief Set the LU field to a new value. */
+#define CRC_WR_DATA_LU(base, value) (CRC_RMW_DATA(base, CRC_DATA_LU_MASK, CRC_DATA_LU(value)))
+#define CRC_BWR_DATA_LU(base, value) (CRC_WR_DATA_LU(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field HL[23:16] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_HL field. */
+#define CRC_RD_DATA_HL(base) ((CRC_DATA_REG(base) & CRC_DATA_HL_MASK) >> CRC_DATA_HL_SHIFT)
+#define CRC_BRD_DATA_HL(base) (CRC_RD_DATA_HL(base))
+
+/*! @brief Set the HL field to a new value. */
+#define CRC_WR_DATA_HL(base, value) (CRC_RMW_DATA(base, CRC_DATA_HL_MASK, CRC_DATA_HL(value)))
+#define CRC_BWR_DATA_HL(base, value) (CRC_WR_DATA_HL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field HU[31:24] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_HU field. */
+#define CRC_RD_DATA_HU(base) ((CRC_DATA_REG(base) & CRC_DATA_HU_MASK) >> CRC_DATA_HU_SHIFT)
+#define CRC_BRD_DATA_HU(base) (CRC_RD_DATA_HU(base))
+
+/*! @brief Set the HU field to a new value. */
+#define CRC_WR_DATA_HU(base, value) (CRC_RMW_DATA(base, CRC_DATA_HU_MASK, CRC_DATA_HU(value)))
+#define CRC_BWR_DATA_HU(base, value) (CRC_WR_DATA_HU(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATALU - CRC_DATALU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATALU - CRC_DATALU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATALU register
+ */
+/*@{*/
+#define CRC_RD_DATALU(base)      (CRC_DATALU_REG(base))
+#define CRC_WR_DATALU(base, value) (CRC_DATALU_REG(base) = (value))
+#define CRC_RMW_DATALU(base, mask, value) (CRC_WR_DATALU(base, (CRC_RD_DATALU(base) & ~(mask)) | (value)))
+#define CRC_SET_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) |  (value)))
+#define CRC_CLR_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) & ~(value)))
+#define CRC_TOG_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAHL - CRC_DATAHL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAHL - CRC_DATAHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAHL register
+ */
+/*@{*/
+#define CRC_RD_DATAHL(base)      (CRC_DATAHL_REG(base))
+#define CRC_WR_DATAHL(base, value) (CRC_DATAHL_REG(base) = (value))
+#define CRC_RMW_DATAHL(base, mask, value) (CRC_WR_DATAHL(base, (CRC_RD_DATAHL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) |  (value)))
+#define CRC_CLR_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) & ~(value)))
+#define CRC_TOG_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAH - CRC_DATAH register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAH - CRC_DATAH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAH register
+ */
+/*@{*/
+#define CRC_RD_DATAH(base)       (CRC_DATAH_REG(base))
+#define CRC_WR_DATAH(base, value) (CRC_DATAH_REG(base) = (value))
+#define CRC_RMW_DATAH(base, mask, value) (CRC_WR_DATAH(base, (CRC_RD_DATAH(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) |  (value)))
+#define CRC_CLR_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) & ~(value)))
+#define CRC_TOG_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAHU - CRC_DATAHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAHU - CRC_DATAHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAHU register
+ */
+/*@{*/
+#define CRC_RD_DATAHU(base)      (CRC_DATAHU_REG(base))
+#define CRC_WR_DATAHU(base, value) (CRC_DATAHU_REG(base) = (value))
+#define CRC_RMW_DATAHU(base, mask, value) (CRC_WR_DATAHU(base, (CRC_RD_DATAHU(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) |  (value)))
+#define CRC_CLR_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) & ~(value)))
+#define CRC_TOG_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYLL - CRC_GPOLYLL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYLL(base)     (CRC_GPOLYLL_REG(base))
+#define CRC_WR_GPOLYLL(base, value) (CRC_GPOLYLL_REG(base) = (value))
+#define CRC_RMW_GPOLYLL(base, mask, value) (CRC_WR_GPOLYLL(base, (CRC_RD_GPOLYLL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) |  (value)))
+#define CRC_CLR_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) & ~(value)))
+#define CRC_TOG_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLY - CRC Polynomial register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLY - CRC Polynomial register (RW)
+ *
+ * Reset value: 0x00001021U
+ *
+ * This register contains the value of the polynomial for the CRC calculation.
+ * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
+ * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
+ * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
+ * used in both 16- and 32-bit CRC modes.
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLY register
+ */
+/*@{*/
+#define CRC_RD_GPOLY(base)       (CRC_GPOLY_REG(base))
+#define CRC_WR_GPOLY(base, value) (CRC_GPOLY_REG(base) = (value))
+#define CRC_RMW_GPOLY(base, mask, value) (CRC_WR_GPOLY(base, (CRC_RD_GPOLY(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) |  (value)))
+#define CRC_CLR_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) & ~(value)))
+#define CRC_TOG_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_GPOLY bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLY, field LOW[15:0] (RW)
+ *
+ * Writable and readable in both 32-bit and 16-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_GPOLY_LOW field. */
+#define CRC_RD_GPOLY_LOW(base) ((CRC_GPOLY_REG(base) & CRC_GPOLY_LOW_MASK) >> CRC_GPOLY_LOW_SHIFT)
+#define CRC_BRD_GPOLY_LOW(base) (CRC_RD_GPOLY_LOW(base))
+
+/*! @brief Set the LOW field to a new value. */
+#define CRC_WR_GPOLY_LOW(base, value) (CRC_RMW_GPOLY(base, CRC_GPOLY_LOW_MASK, CRC_GPOLY_LOW(value)))
+#define CRC_BWR_GPOLY_LOW(base, value) (CRC_WR_GPOLY_LOW(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
+ *
+ * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
+ * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_GPOLY_HIGH field. */
+#define CRC_RD_GPOLY_HIGH(base) ((CRC_GPOLY_REG(base) & CRC_GPOLY_HIGH_MASK) >> CRC_GPOLY_HIGH_SHIFT)
+#define CRC_BRD_GPOLY_HIGH(base) (CRC_RD_GPOLY_HIGH(base))
+
+/*! @brief Set the HIGH field to a new value. */
+#define CRC_WR_GPOLY_HIGH(base, value) (CRC_RMW_GPOLY(base, CRC_GPOLY_HIGH_MASK, CRC_GPOLY_HIGH(value)))
+#define CRC_BWR_GPOLY_HIGH(base, value) (CRC_WR_GPOLY_HIGH(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYL - CRC_GPOLYL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYL - CRC_GPOLYL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYL(base)      (CRC_GPOLYL_REG(base))
+#define CRC_WR_GPOLYL(base, value) (CRC_GPOLYL_REG(base) = (value))
+#define CRC_RMW_GPOLYL(base, mask, value) (CRC_WR_GPOLYL(base, (CRC_RD_GPOLYL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) |  (value)))
+#define CRC_CLR_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) & ~(value)))
+#define CRC_TOG_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYLU - CRC_GPOLYLU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLU register
+ */
+/*@{*/
+#define CRC_RD_GPOLYLU(base)     (CRC_GPOLYLU_REG(base))
+#define CRC_WR_GPOLYLU(base, value) (CRC_GPOLYLU_REG(base) = (value))
+#define CRC_RMW_GPOLYLU(base, mask, value) (CRC_WR_GPOLYLU(base, (CRC_RD_GPOLYLU(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) |  (value)))
+#define CRC_CLR_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) & ~(value)))
+#define CRC_TOG_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYH - CRC_GPOLYH register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYH - CRC_GPOLYH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYH register
+ */
+/*@{*/
+#define CRC_RD_GPOLYH(base)      (CRC_GPOLYH_REG(base))
+#define CRC_WR_GPOLYH(base, value) (CRC_GPOLYH_REG(base) = (value))
+#define CRC_RMW_GPOLYH(base, mask, value) (CRC_WR_GPOLYH(base, (CRC_RD_GPOLYH(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) |  (value)))
+#define CRC_CLR_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) & ~(value)))
+#define CRC_TOG_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYHL - CRC_GPOLYHL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYHL(base)     (CRC_GPOLYHL_REG(base))
+#define CRC_WR_GPOLYHL(base, value) (CRC_GPOLYHL_REG(base) = (value))
+#define CRC_RMW_GPOLYHL(base, mask, value) (CRC_WR_GPOLYHL(base, (CRC_RD_GPOLYHL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) |  (value)))
+#define CRC_CLR_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) & ~(value)))
+#define CRC_TOG_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYHU - CRC_GPOLYHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHU register
+ */
+/*@{*/
+#define CRC_RD_GPOLYHU(base)     (CRC_GPOLYHU_REG(base))
+#define CRC_WR_GPOLYHU(base, value) (CRC_GPOLYHU_REG(base) = (value))
+#define CRC_RMW_GPOLYHU(base, mask, value) (CRC_WR_GPOLYHU(base, (CRC_RD_GPOLYHU(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) |  (value)))
+#define CRC_CLR_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) & ~(value)))
+#define CRC_TOG_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_CTRL - CRC Control register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_CTRL - CRC Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls the configuration and working of the CRC module.
+ * Appropriate bits must be set before starting a new CRC calculation. A new CRC
+ * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
+ * the CRC data register.
+ */
+/*!
+ * @name Constants and macros for entire CRC_CTRL register
+ */
+/*@{*/
+#define CRC_RD_CTRL(base)        (CRC_CTRL_REG(base))
+#define CRC_WR_CTRL(base, value) (CRC_CTRL_REG(base) = (value))
+#define CRC_RMW_CTRL(base, mask, value) (CRC_WR_CTRL(base, (CRC_RD_CTRL(base) & ~(mask)) | (value)))
+#define CRC_SET_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) |  (value)))
+#define CRC_CLR_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) & ~(value)))
+#define CRC_TOG_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_CTRL bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRL, field TCRC[24] (RW)
+ *
+ * Width of CRC protocol.
+ *
+ * Values:
+ * - 0b0 - 16-bit CRC protocol.
+ * - 0b1 - 32-bit CRC protocol.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TCRC field. */
+#define CRC_RD_CTRL_TCRC(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TCRC_MASK) >> CRC_CTRL_TCRC_SHIFT)
+#define CRC_BRD_CTRL_TCRC(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_TCRC_SHIFT))
+
+/*! @brief Set the TCRC field to a new value. */
+#define CRC_WR_CTRL_TCRC(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TCRC_MASK, CRC_CTRL_TCRC(value)))
+#define CRC_BWR_CTRL_TCRC(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_TCRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field WAS[25] (RW)
+ *
+ * When asserted, a value written to the CRC data register is considered a seed
+ * value. When deasserted, a value written to the CRC data register is taken as
+ * data for CRC computation.
+ *
+ * Values:
+ * - 0b0 - Writes to the CRC data register are data values.
+ * - 0b1 - Writes to the CRC data register are seed values.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_WAS field. */
+#define CRC_RD_CTRL_WAS(base) ((CRC_CTRL_REG(base) & CRC_CTRL_WAS_MASK) >> CRC_CTRL_WAS_SHIFT)
+#define CRC_BRD_CTRL_WAS(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_WAS_SHIFT))
+
+/*! @brief Set the WAS field to a new value. */
+#define CRC_WR_CTRL_WAS(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_WAS_MASK, CRC_CTRL_WAS(value)))
+#define CRC_BWR_CTRL_WAS(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_WAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field FXOR[26] (RW)
+ *
+ * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
+ * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
+ *
+ * Values:
+ * - 0b0 - No XOR on reading.
+ * - 0b1 - Invert or complement the read value of the CRC Data register.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_FXOR field. */
+#define CRC_RD_CTRL_FXOR(base) ((CRC_CTRL_REG(base) & CRC_CTRL_FXOR_MASK) >> CRC_CTRL_FXOR_SHIFT)
+#define CRC_BRD_CTRL_FXOR(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_FXOR_SHIFT))
+
+/*! @brief Set the FXOR field to a new value. */
+#define CRC_WR_CTRL_FXOR(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_FXOR_MASK, CRC_CTRL_FXOR(value)))
+#define CRC_BWR_CTRL_FXOR(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_FXOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field TOTR[29:28] (RW)
+ *
+ * Identifies the transpose configuration of the value read from the CRC Data
+ * register. See the description of the transpose feature for the available
+ * transpose options.
+ *
+ * Values:
+ * - 0b00 - No transposition.
+ * - 0b01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TOTR field. */
+#define CRC_RD_CTRL_TOTR(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT)
+#define CRC_BRD_CTRL_TOTR(base) (CRC_RD_CTRL_TOTR(base))
+
+/*! @brief Set the TOTR field to a new value. */
+#define CRC_WR_CTRL_TOTR(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TOTR_MASK, CRC_CTRL_TOTR(value)))
+#define CRC_BWR_CTRL_TOTR(base, value) (CRC_WR_CTRL_TOTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field TOT[31:30] (RW)
+ *
+ * Defines the transpose configuration of the data written to the CRC data
+ * register. See the description of the transpose feature for the available transpose
+ * options.
+ *
+ * Values:
+ * - 0b00 - No transposition.
+ * - 0b01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TOT field. */
+#define CRC_RD_CTRL_TOT(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TOT_MASK) >> CRC_CTRL_TOT_SHIFT)
+#define CRC_BRD_CTRL_TOT(base) (CRC_RD_CTRL_TOT(base))
+
+/*! @brief Set the TOT field to a new value. */
+#define CRC_WR_CTRL_TOT(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TOT_MASK, CRC_CTRL_TOT(value)))
+#define CRC_BWR_CTRL_TOT(base, value) (CRC_WR_CTRL_TOT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_CTRLHU - CRC_CTRLHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_CTRLHU - CRC_CTRLHU register. (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CRC_CTRLHU register
+ */
+/*@{*/
+#define CRC_RD_CTRLHU(base)      (CRC_CTRLHU_REG(base))
+#define CRC_WR_CTRLHU(base, value) (CRC_CTRLHU_REG(base) = (value))
+#define CRC_RMW_CTRLHU(base, mask, value) (CRC_WR_CTRLHU(base, (CRC_RD_CTRLHU(base) & ~(mask)) | (value)))
+#define CRC_SET_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) |  (value)))
+#define CRC_CLR_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) & ~(value)))
+#define CRC_TOG_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_CTRLHU bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRLHU, field TCRC[0] (RW)
+ *
+ * Values:
+ * - 0b0 - 16-bit CRC protocol.
+ * - 0b1 - 32-bit CRC protocol.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TCRC field. */
+#define CRC_RD_CTRLHU_TCRC(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TCRC_MASK) >> CRC_CTRLHU_TCRC_SHIFT)
+#define CRC_BRD_CTRLHU_TCRC(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_TCRC_SHIFT))
+
+/*! @brief Set the TCRC field to a new value. */
+#define CRC_WR_CTRLHU_TCRC(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TCRC_MASK, CRC_CTRLHU_TCRC(value)))
+#define CRC_BWR_CTRLHU_TCRC(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_TCRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field WAS[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Writes to CRC data register are data values.
+ * - 0b1 - Writes to CRC data reguster are seed values.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_WAS field. */
+#define CRC_RD_CTRLHU_WAS(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_WAS_MASK) >> CRC_CTRLHU_WAS_SHIFT)
+#define CRC_BRD_CTRLHU_WAS(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_WAS_SHIFT))
+
+/*! @brief Set the WAS field to a new value. */
+#define CRC_WR_CTRLHU_WAS(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_WAS_MASK, CRC_CTRLHU_WAS(value)))
+#define CRC_BWR_CTRLHU_WAS(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_WAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field FXOR[2] (RW)
+ *
+ * Values:
+ * - 0b0 - No XOR on reading.
+ * - 0b1 - Invert or complement the read value of CRC data register.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_FXOR field. */
+#define CRC_RD_CTRLHU_FXOR(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_FXOR_MASK) >> CRC_CTRLHU_FXOR_SHIFT)
+#define CRC_BRD_CTRLHU_FXOR(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_FXOR_SHIFT))
+
+/*! @brief Set the FXOR field to a new value. */
+#define CRC_WR_CTRLHU_FXOR(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_FXOR_MASK, CRC_CTRLHU_FXOR(value)))
+#define CRC_BWR_CTRLHU_FXOR(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_FXOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
+ *
+ * Values:
+ * - 0b00 - No Transposition.
+ * - 0b01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TOTR field. */
+#define CRC_RD_CTRLHU_TOTR(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TOTR_MASK) >> CRC_CTRLHU_TOTR_SHIFT)
+#define CRC_BRD_CTRLHU_TOTR(base) (CRC_RD_CTRLHU_TOTR(base))
+
+/*! @brief Set the TOTR field to a new value. */
+#define CRC_WR_CTRLHU_TOTR(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TOTR_MASK, CRC_CTRLHU_TOTR(value)))
+#define CRC_BWR_CTRLHU_TOTR(base, value) (CRC_WR_CTRLHU_TOTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
+ *
+ * Values:
+ * - 0b00 - No Transposition.
+ * - 0b01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TOT field. */
+#define CRC_RD_CTRLHU_TOT(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TOT_MASK) >> CRC_CTRLHU_TOT_SHIFT)
+#define CRC_BRD_CTRLHU_TOT(base) (CRC_RD_CTRLHU_TOT(base))
+
+/*! @brief Set the TOT field to a new value. */
+#define CRC_WR_CTRLHU_TOT(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TOT_MASK, CRC_CTRLHU_TOT(value)))
+#define CRC_BWR_CTRLHU_TOT(base, value) (CRC_WR_CTRLHU_TOT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 DAC
+ *
+ * 12-Bit Digital-to-Analog Converter
+ *
+ * Registers defined in this header file:
+ * - DAC_DATL - DAC Data Low Register
+ * - DAC_DATH - DAC Data High Register
+ * - DAC_SR - DAC Status Register
+ * - DAC_C0 - DAC Control Register
+ * - DAC_C1 - DAC Control Register 1
+ * - DAC_C2 - DAC Control Register 2
+ */
+
+#define DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
+#define DAC0_IDX (0U) /*!< Instance number for DAC0. */
+#define DAC1_IDX (1U) /*!< Instance number for DAC1. */
+
+/*******************************************************************************
+ * DAC_DATL - DAC Data Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATL - DAC Data Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATL register
+ */
+/*@{*/
+#define DAC_RD_DATL(base, index) (DAC_DATL_REG(base, index))
+#define DAC_WR_DATL(base, index, value) (DAC_DATL_REG(base, index) = (value))
+#define DAC_RMW_DATL(base, index, mask, value) (DAC_WR_DATL(base, index, (DAC_RD_DATL(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) |  (value)))
+#define DAC_CLR_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) & ~(value)))
+#define DAC_TOG_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_DATH - DAC Data High Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATH - DAC Data High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATH register
+ */
+/*@{*/
+#define DAC_RD_DATH(base, index) (DAC_DATH_REG(base, index))
+#define DAC_WR_DATH(base, index, value) (DAC_DATH_REG(base, index) = (value))
+#define DAC_RMW_DATH(base, index, mask, value) (DAC_WR_DATH(base, index, (DAC_RD_DATH(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) |  (value)))
+#define DAC_CLR_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) & ~(value)))
+#define DAC_TOG_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_DATH bitfields
+ */
+
+/*!
+ * @name Register DAC_DATH, field DATA1[3:0] (RW)
+ *
+ * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
+ * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
+ * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_DATH_DATA1 field. */
+#define DAC_RD_DATH_DATA1(base, index) ((DAC_DATH_REG(base, index) & DAC_DATH_DATA1_MASK) >> DAC_DATH_DATA1_SHIFT)
+#define DAC_BRD_DATH_DATA1(base, index) (DAC_RD_DATH_DATA1(base, index))
+
+/*! @brief Set the DATA1 field to a new value. */
+#define DAC_WR_DATH_DATA1(base, index, value) (DAC_RMW_DATH(base, index, DAC_DATH_DATA1_MASK, DAC_DATH_DATA1(value)))
+#define DAC_BWR_DATH_DATA1(base, index, value) (DAC_WR_DATH_DATA1(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_SR - DAC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_SR - DAC Status Register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
+ * request is done. Writing 0 to a field clears it whereas writing 1 has no
+ * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
+ * The flags are set only when the data buffer status is changed. Do not use
+ * 32/16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_SR register
+ */
+/*@{*/
+#define DAC_RD_SR(base)          (DAC_SR_REG(base))
+#define DAC_WR_SR(base, value)   (DAC_SR_REG(base) = (value))
+#define DAC_RMW_SR(base, mask, value) (DAC_WR_SR(base, (DAC_RD_SR(base) & ~(mask)) | (value)))
+#define DAC_SET_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) |  (value)))
+#define DAC_CLR_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) & ~(value)))
+#define DAC_TOG_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_SR bitfields
+ */
+
+/*!
+ * @name Register DAC_SR, field DACBFRPBF[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
+ * - 0b1 - The DAC buffer read pointer is equal to C2[DACBFUP].
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
+#define DAC_RD_SR_DACBFRPBF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPBF_MASK) >> DAC_SR_DACBFRPBF_SHIFT)
+#define DAC_BRD_SR_DACBFRPBF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT))
+
+/*! @brief Set the DACBFRPBF field to a new value. */
+#define DAC_WR_SR_DACBFRPBF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPBF_MASK, DAC_SR_DACBFRPBF(value)))
+#define DAC_BWR_SR_DACBFRPBF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFRPTF[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer is not zero.
+ * - 0b1 - The DAC buffer read pointer is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
+#define DAC_RD_SR_DACBFRPTF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPTF_MASK) >> DAC_SR_DACBFRPTF_SHIFT)
+#define DAC_BRD_SR_DACBFRPTF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT))
+
+/*! @brief Set the DACBFRPTF field to a new value. */
+#define DAC_WR_SR_DACBFRPTF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPTF_MASK, DAC_SR_DACBFRPTF(value)))
+#define DAC_BWR_SR_DACBFRPTF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFWMF[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer has not reached the watermark level.
+ * - 0b1 - The DAC buffer read pointer has reached the watermark level.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFWMF field. */
+#define DAC_RD_SR_DACBFWMF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFWMF_MASK) >> DAC_SR_DACBFWMF_SHIFT)
+#define DAC_BRD_SR_DACBFWMF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFWMF_SHIFT))
+
+/*! @brief Set the DACBFWMF field to a new value. */
+#define DAC_WR_SR_DACBFWMF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFWMF_MASK, DAC_SR_DACBFWMF(value)))
+#define DAC_BWR_SR_DACBFWMF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFWMF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C0 - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C0 - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_C0 register
+ */
+/*@{*/
+#define DAC_RD_C0(base)          (DAC_C0_REG(base))
+#define DAC_WR_C0(base, value)   (DAC_C0_REG(base) = (value))
+#define DAC_RMW_C0(base, mask, value) (DAC_WR_C0(base, (DAC_RD_C0(base) & ~(mask)) | (value)))
+#define DAC_SET_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) |  (value)))
+#define DAC_CLR_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) & ~(value)))
+#define DAC_TOG_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C0 bitfields
+ */
+
+/*!
+ * @name Register DAC_C0, field DACBBIEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer bottom flag interrupt is disabled.
+ * - 0b1 - The DAC buffer read pointer bottom flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBBIEN field. */
+#define DAC_RD_C0_DACBBIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBBIEN_MASK) >> DAC_C0_DACBBIEN_SHIFT)
+#define DAC_BRD_C0_DACBBIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT))
+
+/*! @brief Set the DACBBIEN field to a new value. */
+#define DAC_WR_C0_DACBBIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBBIEN_MASK, DAC_C0_DACBBIEN(value)))
+#define DAC_BWR_C0_DACBBIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBTIEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer top flag interrupt is disabled.
+ * - 0b1 - The DAC buffer read pointer top flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBTIEN field. */
+#define DAC_RD_C0_DACBTIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBTIEN_MASK) >> DAC_C0_DACBTIEN_SHIFT)
+#define DAC_BRD_C0_DACBTIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT))
+
+/*! @brief Set the DACBTIEN field to a new value. */
+#define DAC_WR_C0_DACBTIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBTIEN_MASK, DAC_C0_DACBTIEN(value)))
+#define DAC_BWR_C0_DACBTIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBWIEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer watermark interrupt is disabled.
+ * - 0b1 - The DAC buffer watermark interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBWIEN field. */
+#define DAC_RD_C0_DACBWIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBWIEN_MASK) >> DAC_C0_DACBWIEN_SHIFT)
+#define DAC_BRD_C0_DACBWIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBWIEN_SHIFT))
+
+/*! @brief Set the DACBWIEN field to a new value. */
+#define DAC_WR_C0_DACBWIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBWIEN_MASK, DAC_C0_DACBWIEN(value)))
+#define DAC_BWR_C0_DACBWIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBWIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field LPEN[3] (RW)
+ *
+ * See the 12-bit DAC electrical characteristics of the device data sheet for
+ * details on the impact of the modes below.
+ *
+ * Values:
+ * - 0b0 - High-Power mode
+ * - 0b1 - Low-Power mode
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_LPEN field. */
+#define DAC_RD_C0_LPEN(base) ((DAC_C0_REG(base) & DAC_C0_LPEN_MASK) >> DAC_C0_LPEN_SHIFT)
+#define DAC_BRD_C0_LPEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT))
+
+/*! @brief Set the LPEN field to a new value. */
+#define DAC_WR_C0_LPEN(base, value) (DAC_RMW_C0(base, DAC_C0_LPEN_MASK, DAC_C0_LPEN(value)))
+#define DAC_BWR_C0_LPEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
+ *
+ * Active high. This is a write-only field, which always reads 0. If DAC
+ * software trigger is selected and buffer is enabled, writing 1 to this field will
+ * advance the buffer read pointer once.
+ *
+ * Values:
+ * - 0b0 - The DAC soft trigger is not valid.
+ * - 0b1 - The DAC soft trigger is valid.
+ */
+/*@{*/
+/*! @brief Set the DACSWTRG field to a new value. */
+#define DAC_WR_C0_DACSWTRG(base, value) (DAC_RMW_C0(base, DAC_C0_DACSWTRG_MASK, DAC_C0_DACSWTRG(value)))
+#define DAC_BWR_C0_DACSWTRG(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACSWTRG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACTRGSEL[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC hardware trigger is selected.
+ * - 0b1 - The DAC software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
+#define DAC_RD_C0_DACTRGSEL(base) ((DAC_C0_REG(base) & DAC_C0_DACTRGSEL_MASK) >> DAC_C0_DACTRGSEL_SHIFT)
+#define DAC_BRD_C0_DACTRGSEL(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT))
+
+/*! @brief Set the DACTRGSEL field to a new value. */
+#define DAC_WR_C0_DACTRGSEL(base, value) (DAC_RMW_C0(base, DAC_C0_DACTRGSEL_MASK, DAC_C0_DACTRGSEL(value)))
+#define DAC_BWR_C0_DACTRGSEL(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACRFS[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC selects DACREF_1 as the reference voltage.
+ * - 0b1 - The DAC selects DACREF_2 as the reference voltage.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACRFS field. */
+#define DAC_RD_C0_DACRFS(base) ((DAC_C0_REG(base) & DAC_C0_DACRFS_MASK) >> DAC_C0_DACRFS_SHIFT)
+#define DAC_BRD_C0_DACRFS(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT))
+
+/*! @brief Set the DACRFS field to a new value. */
+#define DAC_WR_C0_DACRFS(base, value) (DAC_RMW_C0(base, DAC_C0_DACRFS_MASK, DAC_C0_DACRFS(value)))
+#define DAC_BWR_C0_DACRFS(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACEN[7] (RW)
+ *
+ * Starts the Programmable Reference Generator operation.
+ *
+ * Values:
+ * - 0b0 - The DAC system is disabled.
+ * - 0b1 - The DAC system is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACEN field. */
+#define DAC_RD_C0_DACEN(base) ((DAC_C0_REG(base) & DAC_C0_DACEN_MASK) >> DAC_C0_DACEN_SHIFT)
+#define DAC_BRD_C0_DACEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT))
+
+/*! @brief Set the DACEN field to a new value. */
+#define DAC_WR_C0_DACEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACEN_MASK, DAC_C0_DACEN(value)))
+#define DAC_BWR_C0_DACEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C1 - DAC Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C1 - DAC Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_C1 register
+ */
+/*@{*/
+#define DAC_RD_C1(base)          (DAC_C1_REG(base))
+#define DAC_WR_C1(base, value)   (DAC_C1_REG(base) = (value))
+#define DAC_RMW_C1(base, mask, value) (DAC_WR_C1(base, (DAC_RD_C1(base) & ~(mask)) | (value)))
+#define DAC_SET_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) |  (value)))
+#define DAC_CLR_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) & ~(value)))
+#define DAC_TOG_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C1 bitfields
+ */
+
+/*!
+ * @name Register DAC_C1, field DACBFEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Buffer read pointer is disabled. The converted data is always the
+ *     first word of the buffer.
+ * - 0b1 - Buffer read pointer is enabled. The converted data is the word that
+ *     the read pointer points to. It means converted data can be from any word of
+ *     the buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFEN field. */
+#define DAC_RD_C1_DACBFEN(base) ((DAC_C1_REG(base) & DAC_C1_DACBFEN_MASK) >> DAC_C1_DACBFEN_SHIFT)
+#define DAC_BRD_C1_DACBFEN(base) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT))
+
+/*! @brief Set the DACBFEN field to a new value. */
+#define DAC_WR_C1_DACBFEN(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFEN_MASK, DAC_C1_DACBFEN(value)))
+#define DAC_BWR_C1_DACBFEN(base, value) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFMD[2:1] (RW)
+ *
+ * Values:
+ * - 0b00 - Normal mode
+ * - 0b01 - Swing mode
+ * - 0b10 - One-Time Scan mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFMD field. */
+#define DAC_RD_C1_DACBFMD(base) ((DAC_C1_REG(base) & DAC_C1_DACBFMD_MASK) >> DAC_C1_DACBFMD_SHIFT)
+#define DAC_BRD_C1_DACBFMD(base) (DAC_RD_C1_DACBFMD(base))
+
+/*! @brief Set the DACBFMD field to a new value. */
+#define DAC_WR_C1_DACBFMD(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFMD_MASK, DAC_C1_DACBFMD(value)))
+#define DAC_BWR_C1_DACBFMD(base, value) (DAC_WR_C1_DACBFMD(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFWM[4:3] (RW)
+ *
+ * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
+ * the word defined by this field, which is 1-4 words away from the upper limit
+ * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
+ * watermark interrupt.
+ *
+ * Values:
+ * - 0b00 - 1 word
+ * - 0b01 - 2 words
+ * - 0b10 - 3 words
+ * - 0b11 - 4 words
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFWM field. */
+#define DAC_RD_C1_DACBFWM(base) ((DAC_C1_REG(base) & DAC_C1_DACBFWM_MASK) >> DAC_C1_DACBFWM_SHIFT)
+#define DAC_BRD_C1_DACBFWM(base) (DAC_RD_C1_DACBFWM(base))
+
+/*! @brief Set the DACBFWM field to a new value. */
+#define DAC_WR_C1_DACBFWM(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFWM_MASK, DAC_C1_DACBFWM(value)))
+#define DAC_BWR_C1_DACBFWM(base, value) (DAC_WR_C1_DACBFWM(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DMAEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled. When DMA is enabled, the DMA request will be
+ *     generated by original interrupts. The interrupts will not be presented on this
+ *     module at the same time.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DMAEN field. */
+#define DAC_RD_C1_DMAEN(base) ((DAC_C1_REG(base) & DAC_C1_DMAEN_MASK) >> DAC_C1_DMAEN_SHIFT)
+#define DAC_BRD_C1_DMAEN(base) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define DAC_WR_C1_DMAEN(base, value) (DAC_RMW_C1(base, DAC_C1_DMAEN_MASK, DAC_C1_DMAEN(value)))
+#define DAC_BWR_C1_DMAEN(base, value) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C2 - DAC Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C2 - DAC Control Register 2 (RW)
+ *
+ * Reset value: 0x0FU
+ */
+/*!
+ * @name Constants and macros for entire DAC_C2 register
+ */
+/*@{*/
+#define DAC_RD_C2(base)          (DAC_C2_REG(base))
+#define DAC_WR_C2(base, value)   (DAC_C2_REG(base) = (value))
+#define DAC_RMW_C2(base, mask, value) (DAC_WR_C2(base, (DAC_RD_C2(base) & ~(mask)) | (value)))
+#define DAC_SET_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) |  (value)))
+#define DAC_CLR_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) & ~(value)))
+#define DAC_TOG_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C2 bitfields
+ */
+
+/*!
+ * @name Register DAC_C2, field DACBFUP[3:0] (RW)
+ *
+ * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
+ * exceed it.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFUP field. */
+#define DAC_RD_C2_DACBFUP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFUP_MASK) >> DAC_C2_DACBFUP_SHIFT)
+#define DAC_BRD_C2_DACBFUP(base) (DAC_RD_C2_DACBFUP(base))
+
+/*! @brief Set the DACBFUP field to a new value. */
+#define DAC_WR_C2_DACBFUP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFUP_MASK, DAC_C2_DACBFUP(value)))
+#define DAC_BWR_C2_DACBFUP(base, value) (DAC_WR_C2_DACBFUP(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C2, field DACBFRP[7:4] (RW)
+ *
+ * Keeps the current value of the buffer read pointer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFRP field. */
+#define DAC_RD_C2_DACBFRP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT)
+#define DAC_BRD_C2_DACBFRP(base) (DAC_RD_C2_DACBFRP(base))
+
+/*! @brief Set the DACBFRP field to a new value. */
+#define DAC_WR_C2_DACBFRP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFRP_MASK, DAC_C2_DACBFRP(value)))
+#define DAC_BWR_C2_DACBFRP(base, value) (DAC_WR_C2_DACBFRP(base, value))
+/*@}*/
+
+/*
+ * MK64F12 DMA
+ *
+ * Enhanced direct memory access controller
+ *
+ * Registers defined in this header file:
+ * - DMA_CR - Control Register
+ * - DMA_ES - Error Status Register
+ * - DMA_ERQ - Enable Request Register
+ * - DMA_EEI - Enable Error Interrupt Register
+ * - DMA_CEEI - Clear Enable Error Interrupt Register
+ * - DMA_SEEI - Set Enable Error Interrupt Register
+ * - DMA_CERQ - Clear Enable Request Register
+ * - DMA_SERQ - Set Enable Request Register
+ * - DMA_CDNE - Clear DONE Status Bit Register
+ * - DMA_SSRT - Set START Bit Register
+ * - DMA_CERR - Clear Error Register
+ * - DMA_CINT - Clear Interrupt Request Register
+ * - DMA_INT - Interrupt Request Register
+ * - DMA_ERR - Error Register
+ * - DMA_HRS - Hardware Request Status Register
+ * - DMA_DCHPRI3 - Channel n Priority Register
+ * - DMA_DCHPRI2 - Channel n Priority Register
+ * - DMA_DCHPRI1 - Channel n Priority Register
+ * - DMA_DCHPRI0 - Channel n Priority Register
+ * - DMA_DCHPRI7 - Channel n Priority Register
+ * - DMA_DCHPRI6 - Channel n Priority Register
+ * - DMA_DCHPRI5 - Channel n Priority Register
+ * - DMA_DCHPRI4 - Channel n Priority Register
+ * - DMA_DCHPRI11 - Channel n Priority Register
+ * - DMA_DCHPRI10 - Channel n Priority Register
+ * - DMA_DCHPRI9 - Channel n Priority Register
+ * - DMA_DCHPRI8 - Channel n Priority Register
+ * - DMA_DCHPRI15 - Channel n Priority Register
+ * - DMA_DCHPRI14 - Channel n Priority Register
+ * - DMA_DCHPRI13 - Channel n Priority Register
+ * - DMA_DCHPRI12 - Channel n Priority Register
+ * - DMA_SADDR - TCD Source Address
+ * - DMA_SOFF - TCD Signed Source Address Offset
+ * - DMA_ATTR - TCD Transfer Attributes
+ * - DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ * - DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ * - DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ * - DMA_SLAST - TCD Last Source Address Adjustment
+ * - DMA_DADDR - TCD Destination Address
+ * - DMA_DOFF - TCD Signed Destination Address Offset
+ * - DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ * - DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ * - DMA_CSR - TCD Control and Status
+ * - DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ */
+
+#define DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
+#define DMA_IDX (0U) /*!< Instance number for DMA. */
+
+/*******************************************************************************
+ * DMA_CR - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CR defines the basic operating configuration of the DMA. Arbitration can
+ * be configured to use either a fixed-priority or a round-robin scheme. For
+ * fixed-priority arbitration, the highest priority channel requesting service is
+ * selected to execute. The channel priority registers assign the priorities; see
+ * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
+ * ignored and channels are cycled through (from high to low channel number)
+ * without regard to priority. For correct operation, writes to the CR register must
+ * be performed only when the DMA channels are inactive; that is, when
+ * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
+ * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
+ * minor loop completion. When minor loop offsets are enabled, the minor loop
+ * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
+ * destination address (TCDn_DADDR), or to both prior to the addresses being
+ * written back into the TCD. If the major loop is complete, the minor loop offset is
+ * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
+ * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
+ * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
+ * is used to specify multiple fields: a source enable bit (SMLOE) to specify
+ * the minor loop offset should be applied to the source address (TCDn_SADDR) upon
+ * minor loop completion, a destination enable bit (DMLOE) to specify the minor
+ * loop offset should be applied to the destination address (TCDn_DADDR) upon
+ * minor loop completion, and the sign extended minor loop offset value (MLOFF). The
+ * same offset value (MLOFF) is used for both source and destination minor loop
+ * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
+ * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
+ * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
+ * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
+ * assigned to the NBYTES field.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CR register
+ */
+/*@{*/
+#define DMA_RD_CR(base)          (DMA_CR_REG(base))
+#define DMA_WR_CR(base, value)   (DMA_CR_REG(base) = (value))
+#define DMA_RMW_CR(base, mask, value) (DMA_WR_CR(base, (DMA_RD_CR(base) & ~(mask)) | (value)))
+#define DMA_SET_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) |  (value)))
+#define DMA_CLR_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) & ~(value)))
+#define DMA_TOG_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CR bitfields
+ */
+
+/*!
+ * @name Register DMA_CR, field EDBG[1] (RW)
+ *
+ * Values:
+ * - 0b0 - When in debug mode, the DMA continues to operate.
+ * - 0b1 - When in debug mode, the DMA stalls the start of a new channel.
+ *     Executing channels are allowed to complete. Channel execution resumes when the
+ *     system exits debug mode or the EDBG bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_EDBG field. */
+#define DMA_RD_CR_EDBG(base) ((DMA_CR_REG(base) & DMA_CR_EDBG_MASK) >> DMA_CR_EDBG_SHIFT)
+#define DMA_BRD_CR_EDBG(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EDBG_SHIFT))
+
+/*! @brief Set the EDBG field to a new value. */
+#define DMA_WR_CR_EDBG(base, value) (DMA_RMW_CR(base, DMA_CR_EDBG_MASK, DMA_CR_EDBG(value)))
+#define DMA_BWR_CR_EDBG(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EDBG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field ERCA[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Fixed priority arbitration is used for channel selection .
+ * - 0b1 - Round robin arbitration is used for channel selection .
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_ERCA field. */
+#define DMA_RD_CR_ERCA(base) ((DMA_CR_REG(base) & DMA_CR_ERCA_MASK) >> DMA_CR_ERCA_SHIFT)
+#define DMA_BRD_CR_ERCA(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ERCA_SHIFT))
+
+/*! @brief Set the ERCA field to a new value. */
+#define DMA_WR_CR_ERCA(base, value) (DMA_RMW_CR(base, DMA_CR_ERCA_MASK, DMA_CR_ERCA(value)))
+#define DMA_BWR_CR_ERCA(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ERCA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field HOE[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Any error causes the HALT bit to set. Subsequently, all service
+ *     requests are ignored until the HALT bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_HOE field. */
+#define DMA_RD_CR_HOE(base)  ((DMA_CR_REG(base) & DMA_CR_HOE_MASK) >> DMA_CR_HOE_SHIFT)
+#define DMA_BRD_CR_HOE(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HOE_SHIFT))
+
+/*! @brief Set the HOE field to a new value. */
+#define DMA_WR_CR_HOE(base, value) (DMA_RMW_CR(base, DMA_CR_HOE_MASK, DMA_CR_HOE(value)))
+#define DMA_BWR_CR_HOE(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field HALT[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Stall the start of any new channels. Executing channels are allowed
+ *     to complete. Channel execution resumes when this bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_HALT field. */
+#define DMA_RD_CR_HALT(base) ((DMA_CR_REG(base) & DMA_CR_HALT_MASK) >> DMA_CR_HALT_SHIFT)
+#define DMA_BRD_CR_HALT(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define DMA_WR_CR_HALT(base, value) (DMA_RMW_CR(base, DMA_CR_HALT_MASK, DMA_CR_HALT(value)))
+#define DMA_BWR_CR_HALT(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field CLM[6] (RW)
+ *
+ * Values:
+ * - 0b0 - A minor loop channel link made to itself goes through channel
+ *     arbitration before being activated again.
+ * - 0b1 - A minor loop channel link made to itself does not go through channel
+ *     arbitration before being activated again. Upon minor loop completion, the
+ *     channel activates again if that channel has a minor loop channel link
+ *     enabled and the link channel is itself. This effectively applies the minor
+ *     loop offsets and restarts the next minor loop.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_CLM field. */
+#define DMA_RD_CR_CLM(base)  ((DMA_CR_REG(base) & DMA_CR_CLM_MASK) >> DMA_CR_CLM_SHIFT)
+#define DMA_BRD_CR_CLM(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CLM_SHIFT))
+
+/*! @brief Set the CLM field to a new value. */
+#define DMA_WR_CR_CLM(base, value) (DMA_RMW_CR(base, DMA_CR_CLM_MASK, DMA_CR_CLM(value)))
+#define DMA_BWR_CR_CLM(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CLM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field EMLM[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
+ * - 0b1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
+ *     an offset field, and the NBYTES field. The individual enable fields allow
+ *     the minor loop offset to be applied to the source address, the
+ *     destination address, or both. The NBYTES field is reduced when either offset is
+ *     enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_EMLM field. */
+#define DMA_RD_CR_EMLM(base) ((DMA_CR_REG(base) & DMA_CR_EMLM_MASK) >> DMA_CR_EMLM_SHIFT)
+#define DMA_BRD_CR_EMLM(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EMLM_SHIFT))
+
+/*! @brief Set the EMLM field to a new value. */
+#define DMA_WR_CR_EMLM(base, value) (DMA_RMW_CR(base, DMA_CR_EMLM_MASK, DMA_CR_EMLM(value)))
+#define DMA_BWR_CR_EMLM(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EMLM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field ECX[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Cancel the remaining data transfer in the same fashion as the CX bit.
+ *     Stop the executing channel and force the minor loop to finish. The cancel
+ *     takes effect after the last write of the current read/write sequence. The
+ *     ECX bit clears itself after the cancel is honored. In addition to
+ *     cancelling the transfer, ECX treats the cancel as an error condition, thus
+ *     updating the Error Status register (DMAx_ES) and generating an optional error
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_ECX field. */
+#define DMA_RD_CR_ECX(base)  ((DMA_CR_REG(base) & DMA_CR_ECX_MASK) >> DMA_CR_ECX_SHIFT)
+#define DMA_BRD_CR_ECX(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ECX_SHIFT))
+
+/*! @brief Set the ECX field to a new value. */
+#define DMA_WR_CR_ECX(base, value) (DMA_RMW_CR(base, DMA_CR_ECX_MASK, DMA_CR_ECX(value)))
+#define DMA_BWR_CR_ECX(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ECX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field CX[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Cancel the remaining data transfer. Stop the executing channel and
+ *     force the minor loop to finish. The cancel takes effect after the last write
+ *     of the current read/write sequence. The CX bit clears itself after the
+ *     cancel has been honored. This cancel retires the channel normally as if the
+ *     minor loop was completed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_CX field. */
+#define DMA_RD_CR_CX(base)   ((DMA_CR_REG(base) & DMA_CR_CX_MASK) >> DMA_CR_CX_SHIFT)
+#define DMA_BRD_CR_CX(base)  (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CX_SHIFT))
+
+/*! @brief Set the CX field to a new value. */
+#define DMA_WR_CR_CX(base, value) (DMA_RMW_CR(base, DMA_CR_CX_MASK, DMA_CR_CX(value)))
+#define DMA_BWR_CR_CX(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CX_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ES - Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ES - Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ES provides information concerning the last recorded channel error.
+ * Channel errors can be caused by: A configuration error, that is: An illegal setting
+ * in the transfer-control descriptor, or An illegal priority register setting
+ * in fixed-arbitration An error termination to a bus master read or write cycle
+ * See the Error Reporting and Handling section for more details.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ES register
+ */
+/*@{*/
+#define DMA_RD_ES(base)          (DMA_ES_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ES bitfields
+ */
+
+/*!
+ * @name Register DMA_ES, field DBE[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination bus error
+ * - 0b1 - The last recorded error was a bus error on a destination write
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DBE field. */
+#define DMA_RD_ES_DBE(base)  ((DMA_ES_REG(base) & DMA_ES_DBE_MASK) >> DMA_ES_DBE_SHIFT)
+#define DMA_BRD_ES_DBE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SBE[1] (RO)
+ *
+ * Values:
+ * - 0b0 - No source bus error
+ * - 0b1 - The last recorded error was a bus error on a source read
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SBE field. */
+#define DMA_RD_ES_SBE(base)  ((DMA_ES_REG(base) & DMA_ES_SBE_MASK) >> DMA_ES_SBE_SHIFT)
+#define DMA_BRD_ES_SBE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SGE[2] (RO)
+ *
+ * Values:
+ * - 0b0 - No scatter/gather configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DLASTSGA field. This field is checked at the beginning of a
+ *     scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled.
+ *     TCDn_DLASTSGA is not on a 32 byte boundary.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SGE field. */
+#define DMA_RD_ES_SGE(base)  ((DMA_ES_REG(base) & DMA_ES_SGE_MASK) >> DMA_ES_SGE_SHIFT)
+#define DMA_BRD_ES_SGE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SGE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field NCE[3] (RO)
+ *
+ * Values:
+ * - 0b0 - No NBYTES/CITER configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
+ *     TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
+ *     TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_NCE field. */
+#define DMA_RD_ES_NCE(base)  ((DMA_ES_REG(base) & DMA_ES_NCE_MASK) >> DMA_ES_NCE_SHIFT)
+#define DMA_BRD_ES_NCE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_NCE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field DOE[4] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination offset configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DOE field. */
+#define DMA_RD_ES_DOE(base)  ((DMA_ES_REG(base) & DMA_ES_DOE_MASK) >> DMA_ES_DOE_SHIFT)
+#define DMA_BRD_ES_DOE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field DAE[5] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination address configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DAE field. */
+#define DMA_RD_ES_DAE(base)  ((DMA_ES_REG(base) & DMA_ES_DAE_MASK) >> DMA_ES_DAE_SHIFT)
+#define DMA_BRD_ES_DAE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DAE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SOE[6] (RO)
+ *
+ * Values:
+ * - 0b0 - No source offset configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SOE field. */
+#define DMA_RD_ES_SOE(base)  ((DMA_ES_REG(base) & DMA_ES_SOE_MASK) >> DMA_ES_SOE_SHIFT)
+#define DMA_BRD_ES_SOE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SAE[7] (RO)
+ *
+ * Values:
+ * - 0b0 - No source address configuration error.
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SAE field. */
+#define DMA_RD_ES_SAE(base)  ((DMA_ES_REG(base) & DMA_ES_SAE_MASK) >> DMA_ES_SAE_SHIFT)
+#define DMA_BRD_ES_SAE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SAE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field ERRCHN[11:8] (RO)
+ *
+ * The channel number of the last recorded error (excluding CPE errors) or last
+ * recorded error canceled transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_ERRCHN field. */
+#define DMA_RD_ES_ERRCHN(base) ((DMA_ES_REG(base) & DMA_ES_ERRCHN_MASK) >> DMA_ES_ERRCHN_SHIFT)
+#define DMA_BRD_ES_ERRCHN(base) (DMA_RD_ES_ERRCHN(base))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field CPE[14] (RO)
+ *
+ * Values:
+ * - 0b0 - No channel priority error
+ * - 0b1 - The last recorded error was a configuration error in the channel
+ *     priorities . Channel priorities are not unique.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_CPE field. */
+#define DMA_RD_ES_CPE(base)  ((DMA_ES_REG(base) & DMA_ES_CPE_MASK) >> DMA_ES_CPE_SHIFT)
+#define DMA_BRD_ES_CPE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_CPE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field ECX[16] (RO)
+ *
+ * Values:
+ * - 0b0 - No canceled transfers
+ * - 0b1 - The last recorded entry was a canceled transfer by the error cancel
+ *     transfer input
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_ECX field. */
+#define DMA_RD_ES_ECX(base)  ((DMA_ES_REG(base) & DMA_ES_ECX_MASK) >> DMA_ES_ECX_SHIFT)
+#define DMA_BRD_ES_ECX(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_ECX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field VLD[31] (RO)
+ *
+ * Logical OR of all ERR status bits
+ *
+ * Values:
+ * - 0b0 - No ERR bits are set
+ * - 0b1 - At least one ERR bit is set indicating a valid error exists that has
+ *     not been cleared
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_VLD field. */
+#define DMA_RD_ES_VLD(base)  ((DMA_ES_REG(base) & DMA_ES_VLD_MASK) >> DMA_ES_VLD_SHIFT)
+#define DMA_BRD_ES_VLD(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_VLD_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ERQ - Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ERQ - Enable Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERQ register provides a bit map for the 16 implemented channels to enable
+ * the request signal for each channel. The state of any given channel enable is
+ * directly affected by writes to this register; it is also affected by writes
+ * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
+ * for a single channel can easily be modified without needing to perform a
+ * read-modify-write sequence to the ERQ. DMA request input signals and this enable
+ * request flag must be asserted before a channel's hardware service request is
+ * accepted. The state of the DMA enable request flag does not affect a channel
+ * service request made explicitly through software or a linked channel request.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ERQ register
+ */
+/*@{*/
+#define DMA_RD_ERQ(base)         (DMA_ERQ_REG(base))
+#define DMA_WR_ERQ(base, value)  (DMA_ERQ_REG(base) = (value))
+#define DMA_RMW_ERQ(base, mask, value) (DMA_WR_ERQ(base, (DMA_RD_ERQ(base) & ~(mask)) | (value)))
+#define DMA_SET_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) |  (value)))
+#define DMA_CLR_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) & ~(value)))
+#define DMA_TOG_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_ERQ, field ERQ0[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ0 field. */
+#define DMA_RD_ERQ_ERQ0(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ0_MASK) >> DMA_ERQ_ERQ0_SHIFT)
+#define DMA_BRD_ERQ_ERQ0(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ0_SHIFT))
+
+/*! @brief Set the ERQ0 field to a new value. */
+#define DMA_WR_ERQ_ERQ0(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ0_MASK, DMA_ERQ_ERQ0(value)))
+#define DMA_BWR_ERQ_ERQ0(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ1[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ1 field. */
+#define DMA_RD_ERQ_ERQ1(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ1_MASK) >> DMA_ERQ_ERQ1_SHIFT)
+#define DMA_BRD_ERQ_ERQ1(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ1_SHIFT))
+
+/*! @brief Set the ERQ1 field to a new value. */
+#define DMA_WR_ERQ_ERQ1(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ1_MASK, DMA_ERQ_ERQ1(value)))
+#define DMA_BWR_ERQ_ERQ1(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ2[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ2 field. */
+#define DMA_RD_ERQ_ERQ2(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ2_MASK) >> DMA_ERQ_ERQ2_SHIFT)
+#define DMA_BRD_ERQ_ERQ2(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ2_SHIFT))
+
+/*! @brief Set the ERQ2 field to a new value. */
+#define DMA_WR_ERQ_ERQ2(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ2_MASK, DMA_ERQ_ERQ2(value)))
+#define DMA_BWR_ERQ_ERQ2(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ3[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ3 field. */
+#define DMA_RD_ERQ_ERQ3(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ3_MASK) >> DMA_ERQ_ERQ3_SHIFT)
+#define DMA_BRD_ERQ_ERQ3(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ3_SHIFT))
+
+/*! @brief Set the ERQ3 field to a new value. */
+#define DMA_WR_ERQ_ERQ3(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ3_MASK, DMA_ERQ_ERQ3(value)))
+#define DMA_BWR_ERQ_ERQ3(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ4[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ4 field. */
+#define DMA_RD_ERQ_ERQ4(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ4_MASK) >> DMA_ERQ_ERQ4_SHIFT)
+#define DMA_BRD_ERQ_ERQ4(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ4_SHIFT))
+
+/*! @brief Set the ERQ4 field to a new value. */
+#define DMA_WR_ERQ_ERQ4(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ4_MASK, DMA_ERQ_ERQ4(value)))
+#define DMA_BWR_ERQ_ERQ4(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ5[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ5 field. */
+#define DMA_RD_ERQ_ERQ5(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ5_MASK) >> DMA_ERQ_ERQ5_SHIFT)
+#define DMA_BRD_ERQ_ERQ5(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ5_SHIFT))
+
+/*! @brief Set the ERQ5 field to a new value. */
+#define DMA_WR_ERQ_ERQ5(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ5_MASK, DMA_ERQ_ERQ5(value)))
+#define DMA_BWR_ERQ_ERQ5(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ6[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ6 field. */
+#define DMA_RD_ERQ_ERQ6(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ6_MASK) >> DMA_ERQ_ERQ6_SHIFT)
+#define DMA_BRD_ERQ_ERQ6(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ6_SHIFT))
+
+/*! @brief Set the ERQ6 field to a new value. */
+#define DMA_WR_ERQ_ERQ6(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ6_MASK, DMA_ERQ_ERQ6(value)))
+#define DMA_BWR_ERQ_ERQ6(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ7[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ7 field. */
+#define DMA_RD_ERQ_ERQ7(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ7_MASK) >> DMA_ERQ_ERQ7_SHIFT)
+#define DMA_BRD_ERQ_ERQ7(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ7_SHIFT))
+
+/*! @brief Set the ERQ7 field to a new value. */
+#define DMA_WR_ERQ_ERQ7(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ7_MASK, DMA_ERQ_ERQ7(value)))
+#define DMA_BWR_ERQ_ERQ7(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ8[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ8 field. */
+#define DMA_RD_ERQ_ERQ8(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ8_MASK) >> DMA_ERQ_ERQ8_SHIFT)
+#define DMA_BRD_ERQ_ERQ8(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ8_SHIFT))
+
+/*! @brief Set the ERQ8 field to a new value. */
+#define DMA_WR_ERQ_ERQ8(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ8_MASK, DMA_ERQ_ERQ8(value)))
+#define DMA_BWR_ERQ_ERQ8(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ9[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ9 field. */
+#define DMA_RD_ERQ_ERQ9(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ9_MASK) >> DMA_ERQ_ERQ9_SHIFT)
+#define DMA_BRD_ERQ_ERQ9(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ9_SHIFT))
+
+/*! @brief Set the ERQ9 field to a new value. */
+#define DMA_WR_ERQ_ERQ9(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ9_MASK, DMA_ERQ_ERQ9(value)))
+#define DMA_BWR_ERQ_ERQ9(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ10[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ10 field. */
+#define DMA_RD_ERQ_ERQ10(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ10_MASK) >> DMA_ERQ_ERQ10_SHIFT)
+#define DMA_BRD_ERQ_ERQ10(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ10_SHIFT))
+
+/*! @brief Set the ERQ10 field to a new value. */
+#define DMA_WR_ERQ_ERQ10(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ10_MASK, DMA_ERQ_ERQ10(value)))
+#define DMA_BWR_ERQ_ERQ10(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ11[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ11 field. */
+#define DMA_RD_ERQ_ERQ11(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ11_MASK) >> DMA_ERQ_ERQ11_SHIFT)
+#define DMA_BRD_ERQ_ERQ11(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ11_SHIFT))
+
+/*! @brief Set the ERQ11 field to a new value. */
+#define DMA_WR_ERQ_ERQ11(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ11_MASK, DMA_ERQ_ERQ11(value)))
+#define DMA_BWR_ERQ_ERQ11(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ12[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ12 field. */
+#define DMA_RD_ERQ_ERQ12(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ12_MASK) >> DMA_ERQ_ERQ12_SHIFT)
+#define DMA_BRD_ERQ_ERQ12(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ12_SHIFT))
+
+/*! @brief Set the ERQ12 field to a new value. */
+#define DMA_WR_ERQ_ERQ12(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ12_MASK, DMA_ERQ_ERQ12(value)))
+#define DMA_BWR_ERQ_ERQ12(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ13[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ13 field. */
+#define DMA_RD_ERQ_ERQ13(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ13_MASK) >> DMA_ERQ_ERQ13_SHIFT)
+#define DMA_BRD_ERQ_ERQ13(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ13_SHIFT))
+
+/*! @brief Set the ERQ13 field to a new value. */
+#define DMA_WR_ERQ_ERQ13(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ13_MASK, DMA_ERQ_ERQ13(value)))
+#define DMA_BWR_ERQ_ERQ13(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ14[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ14 field. */
+#define DMA_RD_ERQ_ERQ14(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ14_MASK) >> DMA_ERQ_ERQ14_SHIFT)
+#define DMA_BRD_ERQ_ERQ14(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ14_SHIFT))
+
+/*! @brief Set the ERQ14 field to a new value. */
+#define DMA_WR_ERQ_ERQ14(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ14_MASK, DMA_ERQ_ERQ14(value)))
+#define DMA_BWR_ERQ_ERQ14(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ15[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ15 field. */
+#define DMA_RD_ERQ_ERQ15(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ15_MASK) >> DMA_ERQ_ERQ15_SHIFT)
+#define DMA_BRD_ERQ_ERQ15(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ15_SHIFT))
+
+/*! @brief Set the ERQ15 field to a new value. */
+#define DMA_WR_ERQ_ERQ15(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ15_MASK, DMA_ERQ_ERQ15(value)))
+#define DMA_BWR_ERQ_ERQ15(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_EEI - Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_EEI - Enable Error Interrupt Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The EEI register provides a bit map for the 16 channels to enable the error
+ * interrupt signal for each channel. The state of any given channel's error
+ * interrupt enable is directly affected by writes to this register; it is also
+ * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
+ * interrupt enable for a single channel can easily be modified without the need to
+ * perform a read-modify-write sequence to the EEI register. The DMA error
+ * indicator and the error interrupt enable flag must be asserted before an error
+ * interrupt request for a given channel is asserted to the interrupt controller.
+ */
+/*!
+ * @name Constants and macros for entire DMA_EEI register
+ */
+/*@{*/
+#define DMA_RD_EEI(base)         (DMA_EEI_REG(base))
+#define DMA_WR_EEI(base, value)  (DMA_EEI_REG(base) = (value))
+#define DMA_RMW_EEI(base, mask, value) (DMA_WR_EEI(base, (DMA_RD_EEI(base) & ~(mask)) | (value)))
+#define DMA_SET_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) |  (value)))
+#define DMA_CLR_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) & ~(value)))
+#define DMA_TOG_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_EEI bitfields
+ */
+
+/*!
+ * @name Register DMA_EEI, field EEI0[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI0 field. */
+#define DMA_RD_EEI_EEI0(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI0_MASK) >> DMA_EEI_EEI0_SHIFT)
+#define DMA_BRD_EEI_EEI0(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI0_SHIFT))
+
+/*! @brief Set the EEI0 field to a new value. */
+#define DMA_WR_EEI_EEI0(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI0_MASK, DMA_EEI_EEI0(value)))
+#define DMA_BWR_EEI_EEI0(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI1[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI1 field. */
+#define DMA_RD_EEI_EEI1(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI1_MASK) >> DMA_EEI_EEI1_SHIFT)
+#define DMA_BRD_EEI_EEI1(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI1_SHIFT))
+
+/*! @brief Set the EEI1 field to a new value. */
+#define DMA_WR_EEI_EEI1(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI1_MASK, DMA_EEI_EEI1(value)))
+#define DMA_BWR_EEI_EEI1(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI2[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI2 field. */
+#define DMA_RD_EEI_EEI2(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI2_MASK) >> DMA_EEI_EEI2_SHIFT)
+#define DMA_BRD_EEI_EEI2(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI2_SHIFT))
+
+/*! @brief Set the EEI2 field to a new value. */
+#define DMA_WR_EEI_EEI2(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI2_MASK, DMA_EEI_EEI2(value)))
+#define DMA_BWR_EEI_EEI2(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI3[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI3 field. */
+#define DMA_RD_EEI_EEI3(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI3_MASK) >> DMA_EEI_EEI3_SHIFT)
+#define DMA_BRD_EEI_EEI3(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI3_SHIFT))
+
+/*! @brief Set the EEI3 field to a new value. */
+#define DMA_WR_EEI_EEI3(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI3_MASK, DMA_EEI_EEI3(value)))
+#define DMA_BWR_EEI_EEI3(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI4[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI4 field. */
+#define DMA_RD_EEI_EEI4(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI4_MASK) >> DMA_EEI_EEI4_SHIFT)
+#define DMA_BRD_EEI_EEI4(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI4_SHIFT))
+
+/*! @brief Set the EEI4 field to a new value. */
+#define DMA_WR_EEI_EEI4(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI4_MASK, DMA_EEI_EEI4(value)))
+#define DMA_BWR_EEI_EEI4(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI5[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI5 field. */
+#define DMA_RD_EEI_EEI5(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI5_MASK) >> DMA_EEI_EEI5_SHIFT)
+#define DMA_BRD_EEI_EEI5(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI5_SHIFT))
+
+/*! @brief Set the EEI5 field to a new value. */
+#define DMA_WR_EEI_EEI5(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI5_MASK, DMA_EEI_EEI5(value)))
+#define DMA_BWR_EEI_EEI5(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI6[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI6 field. */
+#define DMA_RD_EEI_EEI6(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI6_MASK) >> DMA_EEI_EEI6_SHIFT)
+#define DMA_BRD_EEI_EEI6(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI6_SHIFT))
+
+/*! @brief Set the EEI6 field to a new value. */
+#define DMA_WR_EEI_EEI6(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI6_MASK, DMA_EEI_EEI6(value)))
+#define DMA_BWR_EEI_EEI6(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI7[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI7 field. */
+#define DMA_RD_EEI_EEI7(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI7_MASK) >> DMA_EEI_EEI7_SHIFT)
+#define DMA_BRD_EEI_EEI7(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI7_SHIFT))
+
+/*! @brief Set the EEI7 field to a new value. */
+#define DMA_WR_EEI_EEI7(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI7_MASK, DMA_EEI_EEI7(value)))
+#define DMA_BWR_EEI_EEI7(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI8[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI8 field. */
+#define DMA_RD_EEI_EEI8(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI8_MASK) >> DMA_EEI_EEI8_SHIFT)
+#define DMA_BRD_EEI_EEI8(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI8_SHIFT))
+
+/*! @brief Set the EEI8 field to a new value. */
+#define DMA_WR_EEI_EEI8(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI8_MASK, DMA_EEI_EEI8(value)))
+#define DMA_BWR_EEI_EEI8(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI9[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI9 field. */
+#define DMA_RD_EEI_EEI9(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI9_MASK) >> DMA_EEI_EEI9_SHIFT)
+#define DMA_BRD_EEI_EEI9(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI9_SHIFT))
+
+/*! @brief Set the EEI9 field to a new value. */
+#define DMA_WR_EEI_EEI9(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI9_MASK, DMA_EEI_EEI9(value)))
+#define DMA_BWR_EEI_EEI9(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI10[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI10 field. */
+#define DMA_RD_EEI_EEI10(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI10_MASK) >> DMA_EEI_EEI10_SHIFT)
+#define DMA_BRD_EEI_EEI10(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI10_SHIFT))
+
+/*! @brief Set the EEI10 field to a new value. */
+#define DMA_WR_EEI_EEI10(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI10_MASK, DMA_EEI_EEI10(value)))
+#define DMA_BWR_EEI_EEI10(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI11[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI11 field. */
+#define DMA_RD_EEI_EEI11(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI11_MASK) >> DMA_EEI_EEI11_SHIFT)
+#define DMA_BRD_EEI_EEI11(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI11_SHIFT))
+
+/*! @brief Set the EEI11 field to a new value. */
+#define DMA_WR_EEI_EEI11(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI11_MASK, DMA_EEI_EEI11(value)))
+#define DMA_BWR_EEI_EEI11(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI12[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI12 field. */
+#define DMA_RD_EEI_EEI12(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI12_MASK) >> DMA_EEI_EEI12_SHIFT)
+#define DMA_BRD_EEI_EEI12(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI12_SHIFT))
+
+/*! @brief Set the EEI12 field to a new value. */
+#define DMA_WR_EEI_EEI12(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI12_MASK, DMA_EEI_EEI12(value)))
+#define DMA_BWR_EEI_EEI12(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI13[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI13 field. */
+#define DMA_RD_EEI_EEI13(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI13_MASK) >> DMA_EEI_EEI13_SHIFT)
+#define DMA_BRD_EEI_EEI13(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI13_SHIFT))
+
+/*! @brief Set the EEI13 field to a new value. */
+#define DMA_WR_EEI_EEI13(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI13_MASK, DMA_EEI_EEI13(value)))
+#define DMA_BWR_EEI_EEI13(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI14[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI14 field. */
+#define DMA_RD_EEI_EEI14(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI14_MASK) >> DMA_EEI_EEI14_SHIFT)
+#define DMA_BRD_EEI_EEI14(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI14_SHIFT))
+
+/*! @brief Set the EEI14 field to a new value. */
+#define DMA_WR_EEI_EEI14(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI14_MASK, DMA_EEI_EEI14(value)))
+#define DMA_BWR_EEI_EEI14(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI15[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI15 field. */
+#define DMA_RD_EEI_EEI15(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI15_MASK) >> DMA_EEI_EEI15_SHIFT)
+#define DMA_BRD_EEI_EEI15(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI15_SHIFT))
+
+/*! @brief Set the EEI15 field to a new value. */
+#define DMA_WR_EEI_EEI15(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI15_MASK, DMA_EEI_EEI15(value)))
+#define DMA_BWR_EEI_EEI15(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CEEI - Clear Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CEEI - Clear Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
+ * the EEI to disable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be cleared. Setting
+ * the CAEE bit provides a global clear function, forcing the EEI contents to be
+ * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
+ * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
+ * Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CEEI register
+ */
+/*@{*/
+#define DMA_RD_CEEI(base)        (DMA_CEEI_REG(base))
+#define DMA_WR_CEEI(base, value) (DMA_CEEI_REG(base) = (value))
+#define DMA_RMW_CEEI(base, mask, value) (DMA_WR_CEEI(base, (DMA_RD_CEEI(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in EEI
+ */
+/*@{*/
+/*! @brief Set the CEEI field to a new value. */
+#define DMA_WR_CEEI_CEEI(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_CEEI_MASK, DMA_CEEI_CEEI(value)))
+#define DMA_BWR_CEEI_CEEI(base, value) (DMA_WR_CEEI_CEEI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CEEI, field CAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the EEI bit specified in the CEEI field
+ * - 0b1 - Clear all bits in EEI
+ */
+/*@{*/
+/*! @brief Set the CAEE field to a new value. */
+#define DMA_WR_CEEI_CAEE(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_CAEE_MASK, DMA_CEEI_CAEE(value)))
+#define DMA_BWR_CEEI_CAEE(base, value) (BITBAND_ACCESS8(&DMA_CEEI_REG(base), DMA_CEEI_CAEE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CEEI_NOP(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_NOP_MASK, DMA_CEEI_NOP(value)))
+#define DMA_BWR_CEEI_NOP(base, value) (BITBAND_ACCESS8(&DMA_CEEI_REG(base), DMA_CEEI_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SEEI - Set Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SEEI - Set Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
+ * EEI to enable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be set. Setting the
+ * SAEE bit provides a global set function, forcing the entire EEI contents to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SEEI register
+ */
+/*@{*/
+#define DMA_RD_SEEI(base)        (DMA_SEEI_REG(base))
+#define DMA_WR_SEEI(base, value) (DMA_SEEI_REG(base) = (value))
+#define DMA_RMW_SEEI(base, mask, value) (DMA_WR_SEEI(base, (DMA_RD_SEEI(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in EEI
+ */
+/*@{*/
+/*! @brief Set the SEEI field to a new value. */
+#define DMA_WR_SEEI_SEEI(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_SEEI_MASK, DMA_SEEI_SEEI(value)))
+#define DMA_BWR_SEEI_SEEI(base, value) (DMA_WR_SEEI_SEEI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SEEI, field SAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the EEI bit specified in the SEEI field.
+ * - 0b1 - Sets all bits in EEI
+ */
+/*@{*/
+/*! @brief Set the SAEE field to a new value. */
+#define DMA_WR_SEEI_SAEE(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_SAEE_MASK, DMA_SEEI_SAEE(value)))
+#define DMA_BWR_SEEI_SAEE(base, value) (BITBAND_ACCESS8(&DMA_SEEI_REG(base), DMA_SEEI_SAEE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SEEI_NOP(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_NOP_MASK, DMA_SEEI_NOP(value)))
+#define DMA_BWR_SEEI_NOP(base, value) (BITBAND_ACCESS8(&DMA_SEEI_REG(base), DMA_SEEI_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CERQ - Clear Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CERQ - Clear Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERQ to disable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be cleared. Setting the
+ * CAER bit provides a global clear function, forcing the entire contents of the
+ * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
+ * command is ignored. This allows you to write multiple-byte registers as a 32-bit
+ * word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CERQ register
+ */
+/*@{*/
+#define DMA_RD_CERQ(base)        (DMA_CERQ_REG(base))
+#define DMA_WR_CERQ(base, value) (DMA_CERQ_REG(base) = (value))
+#define DMA_RMW_CERQ(base, mask, value) (DMA_WR_CERQ(base, (DMA_RD_CERQ(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERQ
+ */
+/*@{*/
+/*! @brief Set the CERQ field to a new value. */
+#define DMA_WR_CERQ_CERQ(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_CERQ_MASK, DMA_CERQ_CERQ(value)))
+#define DMA_BWR_CERQ_CERQ(base, value) (DMA_WR_CERQ_CERQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERQ, field CAER[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the ERQ bit specified in the CERQ field
+ * - 0b1 - Clear all bits in ERQ
+ */
+/*@{*/
+/*! @brief Set the CAER field to a new value. */
+#define DMA_WR_CERQ_CAER(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_CAER_MASK, DMA_CERQ_CAER(value)))
+#define DMA_BWR_CERQ_CAER(base, value) (BITBAND_ACCESS8(&DMA_CERQ_REG(base), DMA_CERQ_CAER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CERQ_NOP(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_NOP_MASK, DMA_CERQ_NOP(value)))
+#define DMA_BWR_CERQ_NOP(base, value) (BITBAND_ACCESS8(&DMA_CERQ_REG(base), DMA_CERQ_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SERQ - Set Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SERQ - Set Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
+ * ERQ to enable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
+ * bit provides a global set function, forcing the entire contents of ERQ to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SERQ register
+ */
+/*@{*/
+#define DMA_RD_SERQ(base)        (DMA_SERQ_REG(base))
+#define DMA_WR_SERQ(base, value) (DMA_SERQ_REG(base) = (value))
+#define DMA_RMW_SERQ(base, mask, value) (DMA_WR_SERQ(base, (DMA_RD_SERQ(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in ERQ
+ */
+/*@{*/
+/*! @brief Set the SERQ field to a new value. */
+#define DMA_WR_SERQ_SERQ(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_SERQ_MASK, DMA_SERQ_SERQ(value)))
+#define DMA_BWR_SERQ_SERQ(base, value) (DMA_WR_SERQ_SERQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SERQ, field SAER[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the ERQ bit specified in the SERQ field
+ * - 0b1 - Set all bits in ERQ
+ */
+/*@{*/
+/*! @brief Set the SAER field to a new value. */
+#define DMA_WR_SERQ_SAER(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_SAER_MASK, DMA_SERQ_SAER(value)))
+#define DMA_BWR_SERQ_SAER(base, value) (BITBAND_ACCESS8(&DMA_SERQ_REG(base), DMA_SERQ_SAER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SERQ_NOP(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_NOP_MASK, DMA_SERQ_NOP(value)))
+#define DMA_BWR_SERQ_NOP(base, value) (BITBAND_ACCESS8(&DMA_SERQ_REG(base), DMA_SERQ_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CDNE - Clear DONE Status Bit Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CDNE - Clear DONE Status Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
+ * the CADN bit provides a global clear function, forcing all DONE bits to be
+ * cleared. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CDNE register
+ */
+/*@{*/
+#define DMA_RD_CDNE(base)        (DMA_CDNE_REG(base))
+#define DMA_WR_CDNE(base, value) (DMA_CDNE_REG(base) = (value))
+#define DMA_RMW_CDNE(base, mask, value) (DMA_WR_CDNE(base, (DMA_RD_CDNE(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CDNE bitfields
+ */
+
+/*!
+ * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in TCDn_CSR[DONE]
+ */
+/*@{*/
+/*! @brief Set the CDNE field to a new value. */
+#define DMA_WR_CDNE_CDNE(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_CDNE_MASK, DMA_CDNE_CDNE(value)))
+#define DMA_BWR_CDNE_CDNE(base, value) (DMA_WR_CDNE_CDNE(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CDNE, field CADN[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
+ * - 0b1 - Clears all bits in TCDn_CSR[DONE]
+ */
+/*@{*/
+/*! @brief Set the CADN field to a new value. */
+#define DMA_WR_CDNE_CADN(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_CADN_MASK, DMA_CDNE_CADN(value)))
+#define DMA_BWR_CDNE_CADN(base, value) (BITBAND_ACCESS8(&DMA_CDNE_REG(base), DMA_CDNE_CADN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CDNE, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CDNE_NOP(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_NOP_MASK, DMA_CDNE_NOP(value)))
+#define DMA_BWR_CDNE_NOP(base, value) (BITBAND_ACCESS8(&DMA_CDNE_REG(base), DMA_CDNE_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SSRT - Set START Bit Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SSRT - Set START Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SSRT provides a simple memory-mapped mechanism to set the START bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * START bit in the corresponding transfer control descriptor to be set. Setting the
+ * SAST bit provides a global set function, forcing all START bits to be set. If
+ * the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SSRT register
+ */
+/*@{*/
+#define DMA_RD_SSRT(base)        (DMA_SSRT_REG(base))
+#define DMA_WR_SSRT(base, value) (DMA_SSRT_REG(base) = (value))
+#define DMA_RMW_SSRT(base, mask, value) (DMA_WR_SSRT(base, (DMA_RD_SSRT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SSRT bitfields
+ */
+
+/*!
+ * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in TCDn_CSR[START]
+ */
+/*@{*/
+/*! @brief Set the SSRT field to a new value. */
+#define DMA_WR_SSRT_SSRT(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_SSRT_MASK, DMA_SSRT_SSRT(value)))
+#define DMA_BWR_SSRT_SSRT(base, value) (DMA_WR_SSRT_SSRT(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SSRT, field SAST[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
+ * - 0b1 - Set all bits in TCDn_CSR[START]
+ */
+/*@{*/
+/*! @brief Set the SAST field to a new value. */
+#define DMA_WR_SSRT_SAST(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_SAST_MASK, DMA_SSRT_SAST(value)))
+#define DMA_BWR_SSRT_SAST(base, value) (BITBAND_ACCESS8(&DMA_SSRT_REG(base), DMA_SSRT_SAST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SSRT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SSRT_NOP(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_NOP_MASK, DMA_SSRT_NOP(value)))
+#define DMA_BWR_SSRT_NOP(base, value) (BITBAND_ACCESS8(&DMA_SSRT_REG(base), DMA_SSRT_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CERR - Clear Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CERR - Clear Error Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERR provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERR to disable the error condition flag for a given channel. The given value
+ * on a register write causes the corresponding bit in the ERR to be cleared.
+ * Setting the CAEI bit provides a global clear function, forcing the ERR contents
+ * to be cleared, clearing all channel error indicators. If the NOP bit is set,
+ * the command is ignored. This allows you to write multiple-byte registers as a
+ * 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CERR register
+ */
+/*@{*/
+#define DMA_RD_CERR(base)        (DMA_CERR_REG(base))
+#define DMA_WR_CERR(base, value) (DMA_CERR_REG(base) = (value))
+#define DMA_RMW_CERR(base, mask, value) (DMA_WR_CERR(base, (DMA_RD_CERR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CERR bitfields
+ */
+
+/*!
+ * @name Register DMA_CERR, field CERR[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERR
+ */
+/*@{*/
+/*! @brief Set the CERR field to a new value. */
+#define DMA_WR_CERR_CERR(base, value) (DMA_RMW_CERR(base, DMA_CERR_CERR_MASK, DMA_CERR_CERR(value)))
+#define DMA_BWR_CERR_CERR(base, value) (DMA_WR_CERR_CERR(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERR, field CAEI[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the ERR bit specified in the CERR field
+ * - 0b1 - Clear all bits in ERR
+ */
+/*@{*/
+/*! @brief Set the CAEI field to a new value. */
+#define DMA_WR_CERR_CAEI(base, value) (DMA_RMW_CERR(base, DMA_CERR_CAEI_MASK, DMA_CERR_CAEI(value)))
+#define DMA_BWR_CERR_CAEI(base, value) (BITBAND_ACCESS8(&DMA_CERR_REG(base), DMA_CERR_CAEI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERR, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CERR_NOP(base, value) (DMA_RMW_CERR(base, DMA_CERR_NOP_MASK, DMA_CERR_NOP(value)))
+#define DMA_BWR_CERR_NOP(base, value) (BITBAND_ACCESS8(&DMA_CERR_REG(base), DMA_CERR_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CINT - Clear Interrupt Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CINT - Clear Interrupt Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
+ * the INT to disable the interrupt request for a given channel. The given value
+ * on a register write causes the corresponding bit in the INT to be cleared.
+ * Setting the CAIR bit provides a global clear function, forcing the entire contents
+ * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
+ * bit is set, the command is ignored. This allows you to write multiple-byte
+ * registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CINT register
+ */
+/*@{*/
+#define DMA_RD_CINT(base)        (DMA_CINT_REG(base))
+#define DMA_WR_CINT(base, value) (DMA_CINT_REG(base) = (value))
+#define DMA_RMW_CINT(base, mask, value) (DMA_WR_CINT(base, (DMA_RD_CINT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CINT bitfields
+ */
+
+/*!
+ * @name Register DMA_CINT, field CINT[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in INT
+ */
+/*@{*/
+/*! @brief Set the CINT field to a new value. */
+#define DMA_WR_CINT_CINT(base, value) (DMA_RMW_CINT(base, DMA_CINT_CINT_MASK, DMA_CINT_CINT(value)))
+#define DMA_BWR_CINT_CINT(base, value) (DMA_WR_CINT_CINT(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CINT, field CAIR[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the INT bit specified in the CINT field
+ * - 0b1 - Clear all bits in INT
+ */
+/*@{*/
+/*! @brief Set the CAIR field to a new value. */
+#define DMA_WR_CINT_CAIR(base, value) (DMA_RMW_CINT(base, DMA_CINT_CAIR_MASK, DMA_CINT_CAIR(value)))
+#define DMA_BWR_CINT_CAIR(base, value) (BITBAND_ACCESS8(&DMA_CINT_REG(base), DMA_CINT_CAIR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CINT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CINT_NOP(base, value) (DMA_RMW_CINT(base, DMA_CINT_NOP_MASK, DMA_CINT_NOP(value)))
+#define DMA_BWR_CINT_NOP(base, value) (BITBAND_ACCESS8(&DMA_CINT_REG(base), DMA_CINT_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_INT - Interrupt Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_INT - Interrupt Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The INT register provides a bit map for the 16 channels signaling the
+ * presence of an interrupt request for each channel. Depending on the appropriate bit
+ * setting in the transfer-control descriptors, the eDMA engine generates an
+ * interrupt on data transfer completion. The outputs of this register are directly
+ * routed to the interrupt controller (INTC). During the interrupt-service routine
+ * associated with any given channel, it is the software's responsibility to
+ * clear the appropriate bit, negating the interrupt request. Typically, a write to
+ * the CINT register in the interrupt service routine is used for this purpose.
+ * The state of any given channel's interrupt request is directly affected by
+ * writes to this register; it is also affected by writes to the CINT register. On
+ * writes to INT, a 1 in any bit position clears the corresponding channel's
+ * interrupt request. A zero in any bit position has no affect on the corresponding
+ * channel's current interrupt status. The CINT register is provided so the interrupt
+ * request for a single channel can easily be cleared without the need to
+ * perform a read-modify-write sequence to the INT register.
+ */
+/*!
+ * @name Constants and macros for entire DMA_INT register
+ */
+/*@{*/
+#define DMA_RD_INT(base)         (DMA_INT_REG(base))
+#define DMA_WR_INT(base, value)  (DMA_INT_REG(base) = (value))
+#define DMA_RMW_INT(base, mask, value) (DMA_WR_INT(base, (DMA_RD_INT(base) & ~(mask)) | (value)))
+#define DMA_SET_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) |  (value)))
+#define DMA_CLR_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) & ~(value)))
+#define DMA_TOG_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_INT bitfields
+ */
+
+/*!
+ * @name Register DMA_INT, field INT0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT0 field. */
+#define DMA_RD_INT_INT0(base) ((DMA_INT_REG(base) & DMA_INT_INT0_MASK) >> DMA_INT_INT0_SHIFT)
+#define DMA_BRD_INT_INT0(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT0_SHIFT))
+
+/*! @brief Set the INT0 field to a new value. */
+#define DMA_WR_INT_INT0(base, value) (DMA_RMW_INT(base, (DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT0(value)))
+#define DMA_BWR_INT_INT0(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT1 field. */
+#define DMA_RD_INT_INT1(base) ((DMA_INT_REG(base) & DMA_INT_INT1_MASK) >> DMA_INT_INT1_SHIFT)
+#define DMA_BRD_INT_INT1(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT1_SHIFT))
+
+/*! @brief Set the INT1 field to a new value. */
+#define DMA_WR_INT_INT1(base, value) (DMA_RMW_INT(base, (DMA_INT_INT1_MASK | DMA_INT_INT0_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT1(value)))
+#define DMA_BWR_INT_INT1(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT2 field. */
+#define DMA_RD_INT_INT2(base) ((DMA_INT_REG(base) & DMA_INT_INT2_MASK) >> DMA_INT_INT2_SHIFT)
+#define DMA_BRD_INT_INT2(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT2_SHIFT))
+
+/*! @brief Set the INT2 field to a new value. */
+#define DMA_WR_INT_INT2(base, value) (DMA_RMW_INT(base, (DMA_INT_INT2_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT2(value)))
+#define DMA_BWR_INT_INT2(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT3 field. */
+#define DMA_RD_INT_INT3(base) ((DMA_INT_REG(base) & DMA_INT_INT3_MASK) >> DMA_INT_INT3_SHIFT)
+#define DMA_BRD_INT_INT3(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT3_SHIFT))
+
+/*! @brief Set the INT3 field to a new value. */
+#define DMA_WR_INT_INT3(base, value) (DMA_RMW_INT(base, (DMA_INT_INT3_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT3(value)))
+#define DMA_BWR_INT_INT3(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT4[4] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT4 field. */
+#define DMA_RD_INT_INT4(base) ((DMA_INT_REG(base) & DMA_INT_INT4_MASK) >> DMA_INT_INT4_SHIFT)
+#define DMA_BRD_INT_INT4(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT4_SHIFT))
+
+/*! @brief Set the INT4 field to a new value. */
+#define DMA_WR_INT_INT4(base, value) (DMA_RMW_INT(base, (DMA_INT_INT4_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT4(value)))
+#define DMA_BWR_INT_INT4(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT5[5] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT5 field. */
+#define DMA_RD_INT_INT5(base) ((DMA_INT_REG(base) & DMA_INT_INT5_MASK) >> DMA_INT_INT5_SHIFT)
+#define DMA_BRD_INT_INT5(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT5_SHIFT))
+
+/*! @brief Set the INT5 field to a new value. */
+#define DMA_WR_INT_INT5(base, value) (DMA_RMW_INT(base, (DMA_INT_INT5_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT5(value)))
+#define DMA_BWR_INT_INT5(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT6[6] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT6 field. */
+#define DMA_RD_INT_INT6(base) ((DMA_INT_REG(base) & DMA_INT_INT6_MASK) >> DMA_INT_INT6_SHIFT)
+#define DMA_BRD_INT_INT6(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT6_SHIFT))
+
+/*! @brief Set the INT6 field to a new value. */
+#define DMA_WR_INT_INT6(base, value) (DMA_RMW_INT(base, (DMA_INT_INT6_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT6(value)))
+#define DMA_BWR_INT_INT6(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT7[7] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT7 field. */
+#define DMA_RD_INT_INT7(base) ((DMA_INT_REG(base) & DMA_INT_INT7_MASK) >> DMA_INT_INT7_SHIFT)
+#define DMA_BRD_INT_INT7(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT7_SHIFT))
+
+/*! @brief Set the INT7 field to a new value. */
+#define DMA_WR_INT_INT7(base, value) (DMA_RMW_INT(base, (DMA_INT_INT7_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT7(value)))
+#define DMA_BWR_INT_INT7(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT8[8] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT8 field. */
+#define DMA_RD_INT_INT8(base) ((DMA_INT_REG(base) & DMA_INT_INT8_MASK) >> DMA_INT_INT8_SHIFT)
+#define DMA_BRD_INT_INT8(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT8_SHIFT))
+
+/*! @brief Set the INT8 field to a new value. */
+#define DMA_WR_INT_INT8(base, value) (DMA_RMW_INT(base, (DMA_INT_INT8_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT8(value)))
+#define DMA_BWR_INT_INT8(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT9[9] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT9 field. */
+#define DMA_RD_INT_INT9(base) ((DMA_INT_REG(base) & DMA_INT_INT9_MASK) >> DMA_INT_INT9_SHIFT)
+#define DMA_BRD_INT_INT9(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT9_SHIFT))
+
+/*! @brief Set the INT9 field to a new value. */
+#define DMA_WR_INT_INT9(base, value) (DMA_RMW_INT(base, (DMA_INT_INT9_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT9(value)))
+#define DMA_BWR_INT_INT9(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT10[10] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT10 field. */
+#define DMA_RD_INT_INT10(base) ((DMA_INT_REG(base) & DMA_INT_INT10_MASK) >> DMA_INT_INT10_SHIFT)
+#define DMA_BRD_INT_INT10(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT10_SHIFT))
+
+/*! @brief Set the INT10 field to a new value. */
+#define DMA_WR_INT_INT10(base, value) (DMA_RMW_INT(base, (DMA_INT_INT10_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT10(value)))
+#define DMA_BWR_INT_INT10(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT11[11] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT11 field. */
+#define DMA_RD_INT_INT11(base) ((DMA_INT_REG(base) & DMA_INT_INT11_MASK) >> DMA_INT_INT11_SHIFT)
+#define DMA_BRD_INT_INT11(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT11_SHIFT))
+
+/*! @brief Set the INT11 field to a new value. */
+#define DMA_WR_INT_INT11(base, value) (DMA_RMW_INT(base, (DMA_INT_INT11_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT11(value)))
+#define DMA_BWR_INT_INT11(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT12[12] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT12 field. */
+#define DMA_RD_INT_INT12(base) ((DMA_INT_REG(base) & DMA_INT_INT12_MASK) >> DMA_INT_INT12_SHIFT)
+#define DMA_BRD_INT_INT12(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT12_SHIFT))
+
+/*! @brief Set the INT12 field to a new value. */
+#define DMA_WR_INT_INT12(base, value) (DMA_RMW_INT(base, (DMA_INT_INT12_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT12(value)))
+#define DMA_BWR_INT_INT12(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT13[13] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT13 field. */
+#define DMA_RD_INT_INT13(base) ((DMA_INT_REG(base) & DMA_INT_INT13_MASK) >> DMA_INT_INT13_SHIFT)
+#define DMA_BRD_INT_INT13(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT13_SHIFT))
+
+/*! @brief Set the INT13 field to a new value. */
+#define DMA_WR_INT_INT13(base, value) (DMA_RMW_INT(base, (DMA_INT_INT13_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT13(value)))
+#define DMA_BWR_INT_INT13(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT14[14] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT14 field. */
+#define DMA_RD_INT_INT14(base) ((DMA_INT_REG(base) & DMA_INT_INT14_MASK) >> DMA_INT_INT14_SHIFT)
+#define DMA_BRD_INT_INT14(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT14_SHIFT))
+
+/*! @brief Set the INT14 field to a new value. */
+#define DMA_WR_INT_INT14(base, value) (DMA_RMW_INT(base, (DMA_INT_INT14_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT15_MASK), DMA_INT_INT14(value)))
+#define DMA_BWR_INT_INT14(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT15[15] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT15 field. */
+#define DMA_RD_INT_INT15(base) ((DMA_INT_REG(base) & DMA_INT_INT15_MASK) >> DMA_INT_INT15_SHIFT)
+#define DMA_BRD_INT_INT15(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT15_SHIFT))
+
+/*! @brief Set the INT15 field to a new value. */
+#define DMA_WR_INT_INT15(base, value) (DMA_RMW_INT(base, (DMA_INT_INT15_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK), DMA_INT_INT15(value)))
+#define DMA_BWR_INT_INT15(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ERR - Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ERR - Error Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERR provides a bit map for the 16 channels, signaling the presence of an
+ * error for each channel. The eDMA engine signals the occurrence of an error
+ * condition by setting the appropriate bit in this register. The outputs of this
+ * register are enabled by the contents of the EEI, and then routed to the
+ * interrupt controller. During the execution of the interrupt-service routine associated
+ * with any DMA errors, it is software's responsibility to clear the appropriate
+ * bit, negating the error-interrupt request. Typically, a write to the CERR in
+ * the interrupt-service routine is used for this purpose. The normal DMA channel
+ * completion indicators (setting the transfer control descriptor DONE flag and
+ * the possible assertion of an interrupt request) are not affected when an error
+ * is detected. The contents of this register can also be polled because a
+ * non-zero value indicates the presence of a channel error regardless of the state of
+ * the EEI. The state of any given channel's error indicators is affected by
+ * writes to this register; it is also affected by writes to the CERR. On writes to
+ * the ERR, a one in any bit position clears the corresponding channel's error
+ * status. A zero in any bit position has no affect on the corresponding channel's
+ * current error status. The CERR is provided so the error indicator for a single
+ * channel can easily be cleared.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ERR register
+ */
+/*@{*/
+#define DMA_RD_ERR(base)         (DMA_ERR_REG(base))
+#define DMA_WR_ERR(base, value)  (DMA_ERR_REG(base) = (value))
+#define DMA_RMW_ERR(base, mask, value) (DMA_WR_ERR(base, (DMA_RD_ERR(base) & ~(mask)) | (value)))
+#define DMA_SET_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) |  (value)))
+#define DMA_CLR_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) & ~(value)))
+#define DMA_TOG_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ERR bitfields
+ */
+
+/*!
+ * @name Register DMA_ERR, field ERR0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR0 field. */
+#define DMA_RD_ERR_ERR0(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR0_MASK) >> DMA_ERR_ERR0_SHIFT)
+#define DMA_BRD_ERR_ERR0(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR0_SHIFT))
+
+/*! @brief Set the ERR0 field to a new value. */
+#define DMA_WR_ERR_ERR0(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR0(value)))
+#define DMA_BWR_ERR_ERR0(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR1 field. */
+#define DMA_RD_ERR_ERR1(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR1_MASK) >> DMA_ERR_ERR1_SHIFT)
+#define DMA_BRD_ERR_ERR1(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR1_SHIFT))
+
+/*! @brief Set the ERR1 field to a new value. */
+#define DMA_WR_ERR_ERR1(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR1_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR1(value)))
+#define DMA_BWR_ERR_ERR1(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR2 field. */
+#define DMA_RD_ERR_ERR2(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR2_MASK) >> DMA_ERR_ERR2_SHIFT)
+#define DMA_BRD_ERR_ERR2(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR2_SHIFT))
+
+/*! @brief Set the ERR2 field to a new value. */
+#define DMA_WR_ERR_ERR2(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR2_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR2(value)))
+#define DMA_BWR_ERR_ERR2(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR3 field. */
+#define DMA_RD_ERR_ERR3(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR3_MASK) >> DMA_ERR_ERR3_SHIFT)
+#define DMA_BRD_ERR_ERR3(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR3_SHIFT))
+
+/*! @brief Set the ERR3 field to a new value. */
+#define DMA_WR_ERR_ERR3(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR3_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR3(value)))
+#define DMA_BWR_ERR_ERR3(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR4[4] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR4 field. */
+#define DMA_RD_ERR_ERR4(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR4_MASK) >> DMA_ERR_ERR4_SHIFT)
+#define DMA_BRD_ERR_ERR4(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR4_SHIFT))
+
+/*! @brief Set the ERR4 field to a new value. */
+#define DMA_WR_ERR_ERR4(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR4_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR4(value)))
+#define DMA_BWR_ERR_ERR4(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR5[5] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR5 field. */
+#define DMA_RD_ERR_ERR5(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR5_MASK) >> DMA_ERR_ERR5_SHIFT)
+#define DMA_BRD_ERR_ERR5(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR5_SHIFT))
+
+/*! @brief Set the ERR5 field to a new value. */
+#define DMA_WR_ERR_ERR5(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR5_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR5(value)))
+#define DMA_BWR_ERR_ERR5(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR6[6] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR6 field. */
+#define DMA_RD_ERR_ERR6(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR6_MASK) >> DMA_ERR_ERR6_SHIFT)
+#define DMA_BRD_ERR_ERR6(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR6_SHIFT))
+
+/*! @brief Set the ERR6 field to a new value. */
+#define DMA_WR_ERR_ERR6(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR6_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR6(value)))
+#define DMA_BWR_ERR_ERR6(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR7[7] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR7 field. */
+#define DMA_RD_ERR_ERR7(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR7_MASK) >> DMA_ERR_ERR7_SHIFT)
+#define DMA_BRD_ERR_ERR7(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR7_SHIFT))
+
+/*! @brief Set the ERR7 field to a new value. */
+#define DMA_WR_ERR_ERR7(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR7_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR7(value)))
+#define DMA_BWR_ERR_ERR7(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR8[8] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR8 field. */
+#define DMA_RD_ERR_ERR8(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR8_MASK) >> DMA_ERR_ERR8_SHIFT)
+#define DMA_BRD_ERR_ERR8(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR8_SHIFT))
+
+/*! @brief Set the ERR8 field to a new value. */
+#define DMA_WR_ERR_ERR8(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR8_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR8(value)))
+#define DMA_BWR_ERR_ERR8(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR9[9] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR9 field. */
+#define DMA_RD_ERR_ERR9(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR9_MASK) >> DMA_ERR_ERR9_SHIFT)
+#define DMA_BRD_ERR_ERR9(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR9_SHIFT))
+
+/*! @brief Set the ERR9 field to a new value. */
+#define DMA_WR_ERR_ERR9(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR9_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR9(value)))
+#define DMA_BWR_ERR_ERR9(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR10[10] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR10 field. */
+#define DMA_RD_ERR_ERR10(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR10_MASK) >> DMA_ERR_ERR10_SHIFT)
+#define DMA_BRD_ERR_ERR10(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR10_SHIFT))
+
+/*! @brief Set the ERR10 field to a new value. */
+#define DMA_WR_ERR_ERR10(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR10_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR10(value)))
+#define DMA_BWR_ERR_ERR10(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR11[11] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR11 field. */
+#define DMA_RD_ERR_ERR11(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR11_MASK) >> DMA_ERR_ERR11_SHIFT)
+#define DMA_BRD_ERR_ERR11(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR11_SHIFT))
+
+/*! @brief Set the ERR11 field to a new value. */
+#define DMA_WR_ERR_ERR11(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR11_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR11(value)))
+#define DMA_BWR_ERR_ERR11(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR12[12] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR12 field. */
+#define DMA_RD_ERR_ERR12(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR12_MASK) >> DMA_ERR_ERR12_SHIFT)
+#define DMA_BRD_ERR_ERR12(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR12_SHIFT))
+
+/*! @brief Set the ERR12 field to a new value. */
+#define DMA_WR_ERR_ERR12(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR12_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR12(value)))
+#define DMA_BWR_ERR_ERR12(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR13[13] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR13 field. */
+#define DMA_RD_ERR_ERR13(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR13_MASK) >> DMA_ERR_ERR13_SHIFT)
+#define DMA_BRD_ERR_ERR13(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR13_SHIFT))
+
+/*! @brief Set the ERR13 field to a new value. */
+#define DMA_WR_ERR_ERR13(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR13_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR13(value)))
+#define DMA_BWR_ERR_ERR13(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR14[14] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR14 field. */
+#define DMA_RD_ERR_ERR14(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR14_MASK) >> DMA_ERR_ERR14_SHIFT)
+#define DMA_BRD_ERR_ERR14(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR14_SHIFT))
+
+/*! @brief Set the ERR14 field to a new value. */
+#define DMA_WR_ERR_ERR14(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR14_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR14(value)))
+#define DMA_BWR_ERR_ERR14(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR15[15] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR15 field. */
+#define DMA_RD_ERR_ERR15(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR15_MASK) >> DMA_ERR_ERR15_SHIFT)
+#define DMA_BRD_ERR_ERR15(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR15_SHIFT))
+
+/*! @brief Set the ERR15 field to a new value. */
+#define DMA_WR_ERR_ERR15(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR15_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK), DMA_ERR_ERR15(value)))
+#define DMA_BWR_ERR_ERR15(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_HRS - Hardware Request Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_HRS - Hardware Request Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The HRS register provides a bit map for the DMA channels, signaling the
+ * presence of a hardware request for each channel. The hardware request status bits
+ * reflect the current state of the register and qualified (via the ERQ fields)
+ * DMA request signals as seen by the DMA's arbitration logic. This view into the
+ * hardware request signals may be used for debug purposes. These bits reflect the
+ * state of the request as seen by the arbitration logic. Therefore, this status
+ * is affected by the ERQ bits.
+ */
+/*!
+ * @name Constants and macros for entire DMA_HRS register
+ */
+/*@{*/
+#define DMA_RD_HRS(base)         (DMA_HRS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_HRS bitfields
+ */
+
+/*!
+ * @name Register DMA_HRS, field HRS0[0] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 0 is not present
+ * - 0b1 - A hardware service request for channel 0 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS0 field. */
+#define DMA_RD_HRS_HRS0(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS0_MASK) >> DMA_HRS_HRS0_SHIFT)
+#define DMA_BRD_HRS_HRS0(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS1[1] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 1 is not present
+ * - 0b1 - A hardware service request for channel 1 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS1 field. */
+#define DMA_RD_HRS_HRS1(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS1_MASK) >> DMA_HRS_HRS1_SHIFT)
+#define DMA_BRD_HRS_HRS1(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS2[2] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 2 is not present
+ * - 0b1 - A hardware service request for channel 2 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS2 field. */
+#define DMA_RD_HRS_HRS2(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS2_MASK) >> DMA_HRS_HRS2_SHIFT)
+#define DMA_BRD_HRS_HRS2(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS2_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS3[3] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 3 is not present
+ * - 0b1 - A hardware service request for channel 3 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS3 field. */
+#define DMA_RD_HRS_HRS3(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS3_MASK) >> DMA_HRS_HRS3_SHIFT)
+#define DMA_BRD_HRS_HRS3(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS3_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS4[4] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 4 is not present
+ * - 0b1 - A hardware service request for channel 4 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS4 field. */
+#define DMA_RD_HRS_HRS4(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS4_MASK) >> DMA_HRS_HRS4_SHIFT)
+#define DMA_BRD_HRS_HRS4(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS4_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS5[5] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 5 is not present
+ * - 0b1 - A hardware service request for channel 5 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS5 field. */
+#define DMA_RD_HRS_HRS5(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS5_MASK) >> DMA_HRS_HRS5_SHIFT)
+#define DMA_BRD_HRS_HRS5(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS5_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS6[6] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 6 is not present
+ * - 0b1 - A hardware service request for channel 6 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS6 field. */
+#define DMA_RD_HRS_HRS6(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS6_MASK) >> DMA_HRS_HRS6_SHIFT)
+#define DMA_BRD_HRS_HRS6(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS6_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS7[7] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 7 is not present
+ * - 0b1 - A hardware service request for channel 7 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS7 field. */
+#define DMA_RD_HRS_HRS7(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS7_MASK) >> DMA_HRS_HRS7_SHIFT)
+#define DMA_BRD_HRS_HRS7(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS7_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS8[8] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 8 is not present
+ * - 0b1 - A hardware service request for channel 8 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS8 field. */
+#define DMA_RD_HRS_HRS8(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS8_MASK) >> DMA_HRS_HRS8_SHIFT)
+#define DMA_BRD_HRS_HRS8(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS8_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS9[9] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 9 is not present
+ * - 0b1 - A hardware service request for channel 9 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS9 field. */
+#define DMA_RD_HRS_HRS9(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS9_MASK) >> DMA_HRS_HRS9_SHIFT)
+#define DMA_BRD_HRS_HRS9(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS9_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS10[10] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 10 is not present
+ * - 0b1 - A hardware service request for channel 10 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS10 field. */
+#define DMA_RD_HRS_HRS10(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS10_MASK) >> DMA_HRS_HRS10_SHIFT)
+#define DMA_BRD_HRS_HRS10(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS10_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS11[11] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 11 is not present
+ * - 0b1 - A hardware service request for channel 11 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS11 field. */
+#define DMA_RD_HRS_HRS11(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS11_MASK) >> DMA_HRS_HRS11_SHIFT)
+#define DMA_BRD_HRS_HRS11(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS11_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS12[12] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 12 is not present
+ * - 0b1 - A hardware service request for channel 12 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS12 field. */
+#define DMA_RD_HRS_HRS12(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS12_MASK) >> DMA_HRS_HRS12_SHIFT)
+#define DMA_BRD_HRS_HRS12(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS12_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS13[13] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 13 is not present
+ * - 0b1 - A hardware service request for channel 13 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS13 field. */
+#define DMA_RD_HRS_HRS13(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS13_MASK) >> DMA_HRS_HRS13_SHIFT)
+#define DMA_BRD_HRS_HRS13(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS13_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS14[14] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 14 is not present
+ * - 0b1 - A hardware service request for channel 14 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS14 field. */
+#define DMA_RD_HRS_HRS14(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS14_MASK) >> DMA_HRS_HRS14_SHIFT)
+#define DMA_BRD_HRS_HRS14(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS14_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS15[15] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 15 is not present
+ * - 0b1 - A hardware service request for channel 15 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS15 field. */
+#define DMA_RD_HRS_HRS15(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS15_MASK) >> DMA_HRS_HRS15_SHIFT)
+#define DMA_BRD_HRS_HRS15(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS15_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI3 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI3 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI3 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI3(base)     (DMA_DCHPRI3_REG(base))
+#define DMA_WR_DCHPRI3(base, value) (DMA_DCHPRI3_REG(base) = (value))
+#define DMA_RMW_DCHPRI3(base, mask, value) (DMA_WR_DCHPRI3(base, (DMA_RD_DCHPRI3(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) |  (value)))
+#define DMA_CLR_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) & ~(value)))
+#define DMA_TOG_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI3 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI3, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_CHPRI field. */
+#define DMA_RD_DCHPRI3_CHPRI(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_CHPRI_MASK) >> DMA_DCHPRI3_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI3_CHPRI(base) (DMA_RD_DCHPRI3_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI3_CHPRI(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_CHPRI_MASK, DMA_DCHPRI3_CHPRI(value)))
+#define DMA_BWR_DCHPRI3_CHPRI(base, value) (DMA_WR_DCHPRI3_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI3, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_DPA field. */
+#define DMA_RD_DCHPRI3_DPA(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_DPA_MASK) >> DMA_DCHPRI3_DPA_SHIFT)
+#define DMA_BRD_DCHPRI3_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI3_DPA(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_DPA_MASK, DMA_DCHPRI3_DPA(value)))
+#define DMA_BWR_DCHPRI3_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI3, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_ECP field. */
+#define DMA_RD_DCHPRI3_ECP(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_ECP_MASK) >> DMA_DCHPRI3_ECP_SHIFT)
+#define DMA_BRD_DCHPRI3_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI3_ECP(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_ECP_MASK, DMA_DCHPRI3_ECP(value)))
+#define DMA_BWR_DCHPRI3_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI2 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI2 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI2 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI2(base)     (DMA_DCHPRI2_REG(base))
+#define DMA_WR_DCHPRI2(base, value) (DMA_DCHPRI2_REG(base) = (value))
+#define DMA_RMW_DCHPRI2(base, mask, value) (DMA_WR_DCHPRI2(base, (DMA_RD_DCHPRI2(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) |  (value)))
+#define DMA_CLR_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) & ~(value)))
+#define DMA_TOG_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI2 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI2, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_CHPRI field. */
+#define DMA_RD_DCHPRI2_CHPRI(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_CHPRI_MASK) >> DMA_DCHPRI2_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI2_CHPRI(base) (DMA_RD_DCHPRI2_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI2_CHPRI(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_CHPRI_MASK, DMA_DCHPRI2_CHPRI(value)))
+#define DMA_BWR_DCHPRI2_CHPRI(base, value) (DMA_WR_DCHPRI2_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI2, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_DPA field. */
+#define DMA_RD_DCHPRI2_DPA(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_DPA_MASK) >> DMA_DCHPRI2_DPA_SHIFT)
+#define DMA_BRD_DCHPRI2_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI2_DPA(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_DPA_MASK, DMA_DCHPRI2_DPA(value)))
+#define DMA_BWR_DCHPRI2_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI2, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_ECP field. */
+#define DMA_RD_DCHPRI2_ECP(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_ECP_MASK) >> DMA_DCHPRI2_ECP_SHIFT)
+#define DMA_BRD_DCHPRI2_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI2_ECP(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_ECP_MASK, DMA_DCHPRI2_ECP(value)))
+#define DMA_BWR_DCHPRI2_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI1 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI1 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI1 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI1(base)     (DMA_DCHPRI1_REG(base))
+#define DMA_WR_DCHPRI1(base, value) (DMA_DCHPRI1_REG(base) = (value))
+#define DMA_RMW_DCHPRI1(base, mask, value) (DMA_WR_DCHPRI1(base, (DMA_RD_DCHPRI1(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) |  (value)))
+#define DMA_CLR_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) & ~(value)))
+#define DMA_TOG_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI1 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI1, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_CHPRI field. */
+#define DMA_RD_DCHPRI1_CHPRI(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_CHPRI_MASK) >> DMA_DCHPRI1_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI1_CHPRI(base) (DMA_RD_DCHPRI1_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI1_CHPRI(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_CHPRI_MASK, DMA_DCHPRI1_CHPRI(value)))
+#define DMA_BWR_DCHPRI1_CHPRI(base, value) (DMA_WR_DCHPRI1_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI1, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_DPA field. */
+#define DMA_RD_DCHPRI1_DPA(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_DPA_MASK) >> DMA_DCHPRI1_DPA_SHIFT)
+#define DMA_BRD_DCHPRI1_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI1_DPA(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_DPA_MASK, DMA_DCHPRI1_DPA(value)))
+#define DMA_BWR_DCHPRI1_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI1, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_ECP field. */
+#define DMA_RD_DCHPRI1_ECP(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_ECP_MASK) >> DMA_DCHPRI1_ECP_SHIFT)
+#define DMA_BRD_DCHPRI1_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI1_ECP(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_ECP_MASK, DMA_DCHPRI1_ECP(value)))
+#define DMA_BWR_DCHPRI1_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI0 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI0 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI0 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI0(base)     (DMA_DCHPRI0_REG(base))
+#define DMA_WR_DCHPRI0(base, value) (DMA_DCHPRI0_REG(base) = (value))
+#define DMA_RMW_DCHPRI0(base, mask, value) (DMA_WR_DCHPRI0(base, (DMA_RD_DCHPRI0(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) |  (value)))
+#define DMA_CLR_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) & ~(value)))
+#define DMA_TOG_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI0 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI0, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_CHPRI field. */
+#define DMA_RD_DCHPRI0_CHPRI(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_CHPRI_MASK) >> DMA_DCHPRI0_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI0_CHPRI(base) (DMA_RD_DCHPRI0_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI0_CHPRI(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_CHPRI_MASK, DMA_DCHPRI0_CHPRI(value)))
+#define DMA_BWR_DCHPRI0_CHPRI(base, value) (DMA_WR_DCHPRI0_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI0, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_DPA field. */
+#define DMA_RD_DCHPRI0_DPA(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_DPA_MASK) >> DMA_DCHPRI0_DPA_SHIFT)
+#define DMA_BRD_DCHPRI0_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI0_DPA(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_DPA_MASK, DMA_DCHPRI0_DPA(value)))
+#define DMA_BWR_DCHPRI0_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI0, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_ECP field. */
+#define DMA_RD_DCHPRI0_ECP(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_ECP_MASK) >> DMA_DCHPRI0_ECP_SHIFT)
+#define DMA_BRD_DCHPRI0_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI0_ECP(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_ECP_MASK, DMA_DCHPRI0_ECP(value)))
+#define DMA_BWR_DCHPRI0_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI7 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI7 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI7 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI7(base)     (DMA_DCHPRI7_REG(base))
+#define DMA_WR_DCHPRI7(base, value) (DMA_DCHPRI7_REG(base) = (value))
+#define DMA_RMW_DCHPRI7(base, mask, value) (DMA_WR_DCHPRI7(base, (DMA_RD_DCHPRI7(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) |  (value)))
+#define DMA_CLR_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) & ~(value)))
+#define DMA_TOG_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI7 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI7, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_CHPRI field. */
+#define DMA_RD_DCHPRI7_CHPRI(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_CHPRI_MASK) >> DMA_DCHPRI7_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI7_CHPRI(base) (DMA_RD_DCHPRI7_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI7_CHPRI(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_CHPRI_MASK, DMA_DCHPRI7_CHPRI(value)))
+#define DMA_BWR_DCHPRI7_CHPRI(base, value) (DMA_WR_DCHPRI7_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI7, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_DPA field. */
+#define DMA_RD_DCHPRI7_DPA(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_DPA_MASK) >> DMA_DCHPRI7_DPA_SHIFT)
+#define DMA_BRD_DCHPRI7_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI7_DPA(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_DPA_MASK, DMA_DCHPRI7_DPA(value)))
+#define DMA_BWR_DCHPRI7_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI7, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_ECP field. */
+#define DMA_RD_DCHPRI7_ECP(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_ECP_MASK) >> DMA_DCHPRI7_ECP_SHIFT)
+#define DMA_BRD_DCHPRI7_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI7_ECP(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_ECP_MASK, DMA_DCHPRI7_ECP(value)))
+#define DMA_BWR_DCHPRI7_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI6 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI6 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI6 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI6(base)     (DMA_DCHPRI6_REG(base))
+#define DMA_WR_DCHPRI6(base, value) (DMA_DCHPRI6_REG(base) = (value))
+#define DMA_RMW_DCHPRI6(base, mask, value) (DMA_WR_DCHPRI6(base, (DMA_RD_DCHPRI6(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) |  (value)))
+#define DMA_CLR_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) & ~(value)))
+#define DMA_TOG_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI6 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI6, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_CHPRI field. */
+#define DMA_RD_DCHPRI6_CHPRI(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_CHPRI_MASK) >> DMA_DCHPRI6_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI6_CHPRI(base) (DMA_RD_DCHPRI6_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI6_CHPRI(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_CHPRI_MASK, DMA_DCHPRI6_CHPRI(value)))
+#define DMA_BWR_DCHPRI6_CHPRI(base, value) (DMA_WR_DCHPRI6_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI6, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_DPA field. */
+#define DMA_RD_DCHPRI6_DPA(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_DPA_MASK) >> DMA_DCHPRI6_DPA_SHIFT)
+#define DMA_BRD_DCHPRI6_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI6_DPA(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_DPA_MASK, DMA_DCHPRI6_DPA(value)))
+#define DMA_BWR_DCHPRI6_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI6, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_ECP field. */
+#define DMA_RD_DCHPRI6_ECP(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_ECP_MASK) >> DMA_DCHPRI6_ECP_SHIFT)
+#define DMA_BRD_DCHPRI6_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI6_ECP(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_ECP_MASK, DMA_DCHPRI6_ECP(value)))
+#define DMA_BWR_DCHPRI6_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI5 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI5 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI5 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI5(base)     (DMA_DCHPRI5_REG(base))
+#define DMA_WR_DCHPRI5(base, value) (DMA_DCHPRI5_REG(base) = (value))
+#define DMA_RMW_DCHPRI5(base, mask, value) (DMA_WR_DCHPRI5(base, (DMA_RD_DCHPRI5(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) |  (value)))
+#define DMA_CLR_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) & ~(value)))
+#define DMA_TOG_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI5 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI5, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_CHPRI field. */
+#define DMA_RD_DCHPRI5_CHPRI(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_CHPRI_MASK) >> DMA_DCHPRI5_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI5_CHPRI(base) (DMA_RD_DCHPRI5_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI5_CHPRI(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_CHPRI_MASK, DMA_DCHPRI5_CHPRI(value)))
+#define DMA_BWR_DCHPRI5_CHPRI(base, value) (DMA_WR_DCHPRI5_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI5, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_DPA field. */
+#define DMA_RD_DCHPRI5_DPA(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_DPA_MASK) >> DMA_DCHPRI5_DPA_SHIFT)
+#define DMA_BRD_DCHPRI5_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI5_DPA(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_DPA_MASK, DMA_DCHPRI5_DPA(value)))
+#define DMA_BWR_DCHPRI5_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI5, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_ECP field. */
+#define DMA_RD_DCHPRI5_ECP(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_ECP_MASK) >> DMA_DCHPRI5_ECP_SHIFT)
+#define DMA_BRD_DCHPRI5_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI5_ECP(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_ECP_MASK, DMA_DCHPRI5_ECP(value)))
+#define DMA_BWR_DCHPRI5_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI4 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI4 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI4 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI4(base)     (DMA_DCHPRI4_REG(base))
+#define DMA_WR_DCHPRI4(base, value) (DMA_DCHPRI4_REG(base) = (value))
+#define DMA_RMW_DCHPRI4(base, mask, value) (DMA_WR_DCHPRI4(base, (DMA_RD_DCHPRI4(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) |  (value)))
+#define DMA_CLR_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) & ~(value)))
+#define DMA_TOG_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI4 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI4, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_CHPRI field. */
+#define DMA_RD_DCHPRI4_CHPRI(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_CHPRI_MASK) >> DMA_DCHPRI4_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI4_CHPRI(base) (DMA_RD_DCHPRI4_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI4_CHPRI(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_CHPRI_MASK, DMA_DCHPRI4_CHPRI(value)))
+#define DMA_BWR_DCHPRI4_CHPRI(base, value) (DMA_WR_DCHPRI4_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI4, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_DPA field. */
+#define DMA_RD_DCHPRI4_DPA(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_DPA_MASK) >> DMA_DCHPRI4_DPA_SHIFT)
+#define DMA_BRD_DCHPRI4_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI4_DPA(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_DPA_MASK, DMA_DCHPRI4_DPA(value)))
+#define DMA_BWR_DCHPRI4_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI4, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_ECP field. */
+#define DMA_RD_DCHPRI4_ECP(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_ECP_MASK) >> DMA_DCHPRI4_ECP_SHIFT)
+#define DMA_BRD_DCHPRI4_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI4_ECP(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_ECP_MASK, DMA_DCHPRI4_ECP(value)))
+#define DMA_BWR_DCHPRI4_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI11 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI11 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI11 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI11(base)    (DMA_DCHPRI11_REG(base))
+#define DMA_WR_DCHPRI11(base, value) (DMA_DCHPRI11_REG(base) = (value))
+#define DMA_RMW_DCHPRI11(base, mask, value) (DMA_WR_DCHPRI11(base, (DMA_RD_DCHPRI11(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) |  (value)))
+#define DMA_CLR_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) & ~(value)))
+#define DMA_TOG_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI11 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI11, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_CHPRI field. */
+#define DMA_RD_DCHPRI11_CHPRI(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_CHPRI_MASK) >> DMA_DCHPRI11_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI11_CHPRI(base) (DMA_RD_DCHPRI11_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI11_CHPRI(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_CHPRI_MASK, DMA_DCHPRI11_CHPRI(value)))
+#define DMA_BWR_DCHPRI11_CHPRI(base, value) (DMA_WR_DCHPRI11_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI11, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_DPA field. */
+#define DMA_RD_DCHPRI11_DPA(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_DPA_MASK) >> DMA_DCHPRI11_DPA_SHIFT)
+#define DMA_BRD_DCHPRI11_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI11_DPA(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_DPA_MASK, DMA_DCHPRI11_DPA(value)))
+#define DMA_BWR_DCHPRI11_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI11, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_ECP field. */
+#define DMA_RD_DCHPRI11_ECP(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_ECP_MASK) >> DMA_DCHPRI11_ECP_SHIFT)
+#define DMA_BRD_DCHPRI11_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI11_ECP(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_ECP_MASK, DMA_DCHPRI11_ECP(value)))
+#define DMA_BWR_DCHPRI11_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI10 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI10 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI10 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI10(base)    (DMA_DCHPRI10_REG(base))
+#define DMA_WR_DCHPRI10(base, value) (DMA_DCHPRI10_REG(base) = (value))
+#define DMA_RMW_DCHPRI10(base, mask, value) (DMA_WR_DCHPRI10(base, (DMA_RD_DCHPRI10(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) |  (value)))
+#define DMA_CLR_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) & ~(value)))
+#define DMA_TOG_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI10 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI10, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_CHPRI field. */
+#define DMA_RD_DCHPRI10_CHPRI(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_CHPRI_MASK) >> DMA_DCHPRI10_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI10_CHPRI(base) (DMA_RD_DCHPRI10_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI10_CHPRI(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_CHPRI_MASK, DMA_DCHPRI10_CHPRI(value)))
+#define DMA_BWR_DCHPRI10_CHPRI(base, value) (DMA_WR_DCHPRI10_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI10, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_DPA field. */
+#define DMA_RD_DCHPRI10_DPA(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_DPA_MASK) >> DMA_DCHPRI10_DPA_SHIFT)
+#define DMA_BRD_DCHPRI10_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI10_DPA(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_DPA_MASK, DMA_DCHPRI10_DPA(value)))
+#define DMA_BWR_DCHPRI10_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI10, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_ECP field. */
+#define DMA_RD_DCHPRI10_ECP(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_ECP_MASK) >> DMA_DCHPRI10_ECP_SHIFT)
+#define DMA_BRD_DCHPRI10_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI10_ECP(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_ECP_MASK, DMA_DCHPRI10_ECP(value)))
+#define DMA_BWR_DCHPRI10_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI9 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI9 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI9 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI9(base)     (DMA_DCHPRI9_REG(base))
+#define DMA_WR_DCHPRI9(base, value) (DMA_DCHPRI9_REG(base) = (value))
+#define DMA_RMW_DCHPRI9(base, mask, value) (DMA_WR_DCHPRI9(base, (DMA_RD_DCHPRI9(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) |  (value)))
+#define DMA_CLR_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) & ~(value)))
+#define DMA_TOG_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI9 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI9, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_CHPRI field. */
+#define DMA_RD_DCHPRI9_CHPRI(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_CHPRI_MASK) >> DMA_DCHPRI9_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI9_CHPRI(base) (DMA_RD_DCHPRI9_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI9_CHPRI(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_CHPRI_MASK, DMA_DCHPRI9_CHPRI(value)))
+#define DMA_BWR_DCHPRI9_CHPRI(base, value) (DMA_WR_DCHPRI9_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI9, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_DPA field. */
+#define DMA_RD_DCHPRI9_DPA(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_DPA_MASK) >> DMA_DCHPRI9_DPA_SHIFT)
+#define DMA_BRD_DCHPRI9_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI9_DPA(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_DPA_MASK, DMA_DCHPRI9_DPA(value)))
+#define DMA_BWR_DCHPRI9_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI9, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_ECP field. */
+#define DMA_RD_DCHPRI9_ECP(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_ECP_MASK) >> DMA_DCHPRI9_ECP_SHIFT)
+#define DMA_BRD_DCHPRI9_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI9_ECP(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_ECP_MASK, DMA_DCHPRI9_ECP(value)))
+#define DMA_BWR_DCHPRI9_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI8 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI8 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI8 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI8(base)     (DMA_DCHPRI8_REG(base))
+#define DMA_WR_DCHPRI8(base, value) (DMA_DCHPRI8_REG(base) = (value))
+#define DMA_RMW_DCHPRI8(base, mask, value) (DMA_WR_DCHPRI8(base, (DMA_RD_DCHPRI8(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) |  (value)))
+#define DMA_CLR_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) & ~(value)))
+#define DMA_TOG_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI8 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI8, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_CHPRI field. */
+#define DMA_RD_DCHPRI8_CHPRI(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_CHPRI_MASK) >> DMA_DCHPRI8_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI8_CHPRI(base) (DMA_RD_DCHPRI8_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI8_CHPRI(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_CHPRI_MASK, DMA_DCHPRI8_CHPRI(value)))
+#define DMA_BWR_DCHPRI8_CHPRI(base, value) (DMA_WR_DCHPRI8_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI8, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_DPA field. */
+#define DMA_RD_DCHPRI8_DPA(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_DPA_MASK) >> DMA_DCHPRI8_DPA_SHIFT)
+#define DMA_BRD_DCHPRI8_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI8_DPA(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_DPA_MASK, DMA_DCHPRI8_DPA(value)))
+#define DMA_BWR_DCHPRI8_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI8, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_ECP field. */
+#define DMA_RD_DCHPRI8_ECP(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_ECP_MASK) >> DMA_DCHPRI8_ECP_SHIFT)
+#define DMA_BRD_DCHPRI8_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI8_ECP(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_ECP_MASK, DMA_DCHPRI8_ECP(value)))
+#define DMA_BWR_DCHPRI8_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI15 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI15 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI15 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI15(base)    (DMA_DCHPRI15_REG(base))
+#define DMA_WR_DCHPRI15(base, value) (DMA_DCHPRI15_REG(base) = (value))
+#define DMA_RMW_DCHPRI15(base, mask, value) (DMA_WR_DCHPRI15(base, (DMA_RD_DCHPRI15(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) |  (value)))
+#define DMA_CLR_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) & ~(value)))
+#define DMA_TOG_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI15 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI15, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_CHPRI field. */
+#define DMA_RD_DCHPRI15_CHPRI(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_CHPRI_MASK) >> DMA_DCHPRI15_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI15_CHPRI(base) (DMA_RD_DCHPRI15_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI15_CHPRI(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_CHPRI_MASK, DMA_DCHPRI15_CHPRI(value)))
+#define DMA_BWR_DCHPRI15_CHPRI(base, value) (DMA_WR_DCHPRI15_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI15, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_DPA field. */
+#define DMA_RD_DCHPRI15_DPA(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_DPA_MASK) >> DMA_DCHPRI15_DPA_SHIFT)
+#define DMA_BRD_DCHPRI15_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI15_DPA(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_DPA_MASK, DMA_DCHPRI15_DPA(value)))
+#define DMA_BWR_DCHPRI15_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI15, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_ECP field. */
+#define DMA_RD_DCHPRI15_ECP(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_ECP_MASK) >> DMA_DCHPRI15_ECP_SHIFT)
+#define DMA_BRD_DCHPRI15_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI15_ECP(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_ECP_MASK, DMA_DCHPRI15_ECP(value)))
+#define DMA_BWR_DCHPRI15_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI14 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI14 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI14 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI14(base)    (DMA_DCHPRI14_REG(base))
+#define DMA_WR_DCHPRI14(base, value) (DMA_DCHPRI14_REG(base) = (value))
+#define DMA_RMW_DCHPRI14(base, mask, value) (DMA_WR_DCHPRI14(base, (DMA_RD_DCHPRI14(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) |  (value)))
+#define DMA_CLR_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) & ~(value)))
+#define DMA_TOG_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI14 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI14, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_CHPRI field. */
+#define DMA_RD_DCHPRI14_CHPRI(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_CHPRI_MASK) >> DMA_DCHPRI14_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI14_CHPRI(base) (DMA_RD_DCHPRI14_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI14_CHPRI(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_CHPRI_MASK, DMA_DCHPRI14_CHPRI(value)))
+#define DMA_BWR_DCHPRI14_CHPRI(base, value) (DMA_WR_DCHPRI14_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI14, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_DPA field. */
+#define DMA_RD_DCHPRI14_DPA(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_DPA_MASK) >> DMA_DCHPRI14_DPA_SHIFT)
+#define DMA_BRD_DCHPRI14_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI14_DPA(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_DPA_MASK, DMA_DCHPRI14_DPA(value)))
+#define DMA_BWR_DCHPRI14_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI14, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_ECP field. */
+#define DMA_RD_DCHPRI14_ECP(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_ECP_MASK) >> DMA_DCHPRI14_ECP_SHIFT)
+#define DMA_BRD_DCHPRI14_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI14_ECP(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_ECP_MASK, DMA_DCHPRI14_ECP(value)))
+#define DMA_BWR_DCHPRI14_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI13 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI13 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI13 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI13(base)    (DMA_DCHPRI13_REG(base))
+#define DMA_WR_DCHPRI13(base, value) (DMA_DCHPRI13_REG(base) = (value))
+#define DMA_RMW_DCHPRI13(base, mask, value) (DMA_WR_DCHPRI13(base, (DMA_RD_DCHPRI13(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) |  (value)))
+#define DMA_CLR_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) & ~(value)))
+#define DMA_TOG_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI13 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI13, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_CHPRI field. */
+#define DMA_RD_DCHPRI13_CHPRI(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_CHPRI_MASK) >> DMA_DCHPRI13_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI13_CHPRI(base) (DMA_RD_DCHPRI13_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI13_CHPRI(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_CHPRI_MASK, DMA_DCHPRI13_CHPRI(value)))
+#define DMA_BWR_DCHPRI13_CHPRI(base, value) (DMA_WR_DCHPRI13_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI13, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_DPA field. */
+#define DMA_RD_DCHPRI13_DPA(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_DPA_MASK) >> DMA_DCHPRI13_DPA_SHIFT)
+#define DMA_BRD_DCHPRI13_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI13_DPA(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_DPA_MASK, DMA_DCHPRI13_DPA(value)))
+#define DMA_BWR_DCHPRI13_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI13, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_ECP field. */
+#define DMA_RD_DCHPRI13_ECP(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_ECP_MASK) >> DMA_DCHPRI13_ECP_SHIFT)
+#define DMA_BRD_DCHPRI13_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI13_ECP(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_ECP_MASK, DMA_DCHPRI13_ECP(value)))
+#define DMA_BWR_DCHPRI13_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI12 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI12 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI12 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI12(base)    (DMA_DCHPRI12_REG(base))
+#define DMA_WR_DCHPRI12(base, value) (DMA_DCHPRI12_REG(base) = (value))
+#define DMA_RMW_DCHPRI12(base, mask, value) (DMA_WR_DCHPRI12(base, (DMA_RD_DCHPRI12(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) |  (value)))
+#define DMA_CLR_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) & ~(value)))
+#define DMA_TOG_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI12 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI12, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_CHPRI field. */
+#define DMA_RD_DCHPRI12_CHPRI(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_CHPRI_MASK) >> DMA_DCHPRI12_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI12_CHPRI(base) (DMA_RD_DCHPRI12_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI12_CHPRI(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_CHPRI_MASK, DMA_DCHPRI12_CHPRI(value)))
+#define DMA_BWR_DCHPRI12_CHPRI(base, value) (DMA_WR_DCHPRI12_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI12, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_DPA field. */
+#define DMA_RD_DCHPRI12_DPA(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_DPA_MASK) >> DMA_DCHPRI12_DPA_SHIFT)
+#define DMA_BRD_DCHPRI12_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI12_DPA(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_DPA_MASK, DMA_DCHPRI12_DPA(value)))
+#define DMA_BWR_DCHPRI12_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI12, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_ECP field. */
+#define DMA_RD_DCHPRI12_ECP(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_ECP_MASK) >> DMA_DCHPRI12_ECP_SHIFT)
+#define DMA_BRD_DCHPRI12_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI12_ECP(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_ECP_MASK, DMA_DCHPRI12_ECP(value)))
+#define DMA_BWR_DCHPRI12_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SADDR - TCD Source Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SADDR - TCD Source Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SADDR register
+ */
+/*@{*/
+#define DMA_RD_SADDR(base, index) (DMA_SADDR_REG(base, index))
+#define DMA_WR_SADDR(base, index, value) (DMA_SADDR_REG(base, index) = (value))
+#define DMA_RMW_SADDR(base, index, mask, value) (DMA_WR_SADDR(base, index, (DMA_RD_SADDR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) |  (value)))
+#define DMA_CLR_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) & ~(value)))
+#define DMA_TOG_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SOFF - TCD Signed Source Address Offset
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SOFF - TCD Signed Source Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SOFF register
+ */
+/*@{*/
+#define DMA_RD_SOFF(base, index) (DMA_SOFF_REG(base, index))
+#define DMA_WR_SOFF(base, index, value) (DMA_SOFF_REG(base, index) = (value))
+#define DMA_RMW_SOFF(base, index, mask, value) (DMA_WR_SOFF(base, index, (DMA_RD_SOFF(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) |  (value)))
+#define DMA_CLR_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) & ~(value)))
+#define DMA_TOG_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ATTR - TCD Transfer Attributes
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ATTR - TCD Transfer Attributes (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_ATTR register
+ */
+/*@{*/
+#define DMA_RD_ATTR(base, index) (DMA_ATTR_REG(base, index))
+#define DMA_WR_ATTR(base, index, value) (DMA_ATTR_REG(base, index) = (value))
+#define DMA_RMW_ATTR(base, index, mask, value) (DMA_WR_ATTR(base, index, (DMA_RD_ATTR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) |  (value)))
+#define DMA_CLR_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) & ~(value)))
+#define DMA_TOG_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ATTR bitfields
+ */
+
+/*!
+ * @name Register DMA_ATTR, field DSIZE[2:0] (RW)
+ *
+ * See the SSIZE definition
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_DSIZE field. */
+#define DMA_RD_ATTR_DSIZE(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_DSIZE_MASK) >> DMA_ATTR_DSIZE_SHIFT)
+#define DMA_BRD_ATTR_DSIZE(base, index) (DMA_RD_ATTR_DSIZE(base, index))
+
+/*! @brief Set the DSIZE field to a new value. */
+#define DMA_WR_ATTR_DSIZE(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_DSIZE_MASK, DMA_ATTR_DSIZE(value)))
+#define DMA_BWR_ATTR_DSIZE(base, index, value) (DMA_WR_ATTR_DSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field DMOD[7:3] (RW)
+ *
+ * See the SMOD definition
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_DMOD field. */
+#define DMA_RD_ATTR_DMOD(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_DMOD_MASK) >> DMA_ATTR_DMOD_SHIFT)
+#define DMA_BRD_ATTR_DMOD(base, index) (DMA_RD_ATTR_DMOD(base, index))
+
+/*! @brief Set the DMOD field to a new value. */
+#define DMA_WR_ATTR_DMOD(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_DMOD_MASK, DMA_ATTR_DMOD(value)))
+#define DMA_BWR_ATTR_DMOD(base, index, value) (DMA_WR_ATTR_DMOD(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field SSIZE[10:8] (RW)
+ *
+ * The attempted use of a Reserved encoding causes a configuration error.
+ *
+ * Values:
+ * - 0b000 - 8-bit
+ * - 0b001 - 16-bit
+ * - 0b010 - 32-bit
+ * - 0b011 - Reserved
+ * - 0b100 - 16-byte
+ * - 0b101 - 32-byte
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_SSIZE field. */
+#define DMA_RD_ATTR_SSIZE(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_SSIZE_MASK) >> DMA_ATTR_SSIZE_SHIFT)
+#define DMA_BRD_ATTR_SSIZE(base, index) (DMA_RD_ATTR_SSIZE(base, index))
+
+/*! @brief Set the SSIZE field to a new value. */
+#define DMA_WR_ATTR_SSIZE(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_SSIZE_MASK, DMA_ATTR_SSIZE(value)))
+#define DMA_BWR_ATTR_SSIZE(base, index, value) (DMA_WR_ATTR_SSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field SMOD[15:11] (RW)
+ *
+ * Values:
+ * - 0b00000 - Source address modulo feature is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_SMOD field. */
+#define DMA_RD_ATTR_SMOD(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_SMOD_MASK) >> DMA_ATTR_SMOD_SHIFT)
+#define DMA_BRD_ATTR_SMOD(base, index) (DMA_RD_ATTR_SMOD(base, index))
+
+/*! @brief Set the SMOD field to a new value. */
+#define DMA_WR_ATTR_SMOD(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_SMOD_MASK, DMA_ATTR_SMOD(value)))
+#define DMA_BWR_ATTR_SMOD(base, index, value) (DMA_WR_ATTR_SMOD(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
+ * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
+ * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
+ * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLOFFYES register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLOFFYES(base, index) (DMA_NBYTES_MLOFFYES_REG(base, index))
+#define DMA_WR_NBYTES_MLOFFYES(base, index, value) (DMA_NBYTES_MLOFFYES_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLOFFYES(base, index, mask, value) (DMA_WR_NBYTES_MLOFFYES(base, index, (DMA_RD_NBYTES_MLOFFYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_NBYTES_MLOFFYES bitfields
+ */
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted.
+ * (Although, it may be stalled by using the bandwidth control field, or via
+ * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
+ * written back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_NBYTES field. */
+#define DMA_RD_NBYTES_MLOFFYES_NBYTES(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) >> DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_NBYTES(base, index) (DMA_RD_NBYTES_MLOFFYES_NBYTES(base, index))
+
+/*! @brief Set the NBYTES field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_NBYTES(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_NBYTES_MASK, DMA_NBYTES_MLOFFYES_NBYTES(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_NBYTES(base, index, value) (DMA_WR_NBYTES_MLOFFYES_NBYTES(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_MLOFF field. */
+#define DMA_RD_NBYTES_MLOFFYES_MLOFF(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) >> DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_MLOFF(base, index) (DMA_RD_NBYTES_MLOFFYES_MLOFF(base, index))
+
+/*! @brief Set the MLOFF field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_MLOFF(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_MLOFF_MASK, DMA_NBYTES_MLOFFYES_MLOFF(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_MLOFF(base, index, value) (DMA_WR_NBYTES_MLOFFYES_MLOFF(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the DADDR
+ * - 0b1 - The minor loop offset is applied to the DADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_DMLOE field. */
+#define DMA_RD_NBYTES_MLOFFYES_DMLOE(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) >> DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_DMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))
+
+/*! @brief Set the DMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_DMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_DMLOE_MASK, DMA_NBYTES_MLOFFYES_DMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_DMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_DMLOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the SADDR
+ * - 0b1 - The minor loop offset is applied to the SADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_SMLOE field. */
+#define DMA_RD_NBYTES_MLOFFYES_SMLOE(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) >> DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_SMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))
+
+/*! @brief Set the SMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_SMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_SMLOE_MASK, DMA_NBYTES_MLOFFYES_SMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_SMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_SMLOE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
+ * register to use depends on whether minor loop mapping is disabled, enabled but not
+ * used for this channel, or enabled and used. TCD word 2 is defined as follows
+ * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
+ * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
+ * for TCD word 2's definition.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLNO register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLNO(base, index) (DMA_NBYTES_MLNO_REG(base, index))
+#define DMA_WR_NBYTES_MLNO(base, index, value) (DMA_NBYTES_MLNO_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLNO(base, index, mask, value) (DMA_WR_NBYTES_MLNO(base, index, (DMA_RD_NBYTES_MLNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
+ * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
+ * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
+ * the TCD_NBYTES_MLNO register description.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLOFFNO register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLOFFNO(base, index) (DMA_NBYTES_MLOFFNO_REG(base, index))
+#define DMA_WR_NBYTES_MLOFFNO(base, index, value) (DMA_NBYTES_MLOFFNO_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLOFFNO(base, index, mask, value) (DMA_WR_NBYTES_MLOFFNO(base, index, (DMA_RD_NBYTES_MLOFFNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_NBYTES_MLOFFNO bitfields
+ */
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted;
+ * although, it may be stalled by using the bandwidth control field, or via
+ * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
+ * back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_NBYTES field. */
+#define DMA_RD_NBYTES_MLOFFNO_NBYTES(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) >> DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_NBYTES(base, index) (DMA_RD_NBYTES_MLOFFNO_NBYTES(base, index))
+
+/*! @brief Set the NBYTES field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_NBYTES(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_NBYTES_MASK, DMA_NBYTES_MLOFFNO_NBYTES(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_NBYTES(base, index, value) (DMA_WR_NBYTES_MLOFFNO_NBYTES(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the DADDR
+ * - 0b1 - The minor loop offset is applied to the DADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_DMLOE field. */
+#define DMA_RD_NBYTES_MLOFFNO_DMLOE(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) >> DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_DMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))
+
+/*! @brief Set the DMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_DMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_DMLOE_MASK, DMA_NBYTES_MLOFFNO_DMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_DMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_DMLOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the SADDR
+ * - 0b1 - The minor loop offset is applied to the SADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_SMLOE field. */
+#define DMA_RD_NBYTES_MLOFFNO_SMLOE(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) >> DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_SMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))
+
+/*! @brief Set the SMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_SMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_SMLOE_MASK, DMA_NBYTES_MLOFFNO_SMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_SMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_SMLOE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SLAST - TCD Last Source Address Adjustment
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SLAST - TCD Last Source Address Adjustment (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SLAST register
+ */
+/*@{*/
+#define DMA_RD_SLAST(base, index) (DMA_SLAST_REG(base, index))
+#define DMA_WR_SLAST(base, index, value) (DMA_SLAST_REG(base, index) = (value))
+#define DMA_RMW_SLAST(base, index, mask, value) (DMA_WR_SLAST(base, index, (DMA_RD_SLAST(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) |  (value)))
+#define DMA_CLR_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) & ~(value)))
+#define DMA_TOG_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DADDR - TCD Destination Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DADDR - TCD Destination Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DADDR register
+ */
+/*@{*/
+#define DMA_RD_DADDR(base, index) (DMA_DADDR_REG(base, index))
+#define DMA_WR_DADDR(base, index, value) (DMA_DADDR_REG(base, index) = (value))
+#define DMA_RMW_DADDR(base, index, mask, value) (DMA_WR_DADDR(base, index, (DMA_RD_DADDR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) |  (value)))
+#define DMA_CLR_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) & ~(value)))
+#define DMA_TOG_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DOFF - TCD Signed Destination Address Offset
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DOFF - TCD Signed Destination Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DOFF register
+ */
+/*@{*/
+#define DMA_RD_DOFF(base, index) (DMA_DOFF_REG(base, index))
+#define DMA_WR_DOFF(base, index, value) (DMA_DOFF_REG(base, index) = (value))
+#define DMA_RMW_DOFF(base, index, mask, value) (DMA_WR_DOFF(base, index, (DMA_RD_DOFF(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) |  (value)))
+#define DMA_CLR_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) & ~(value)))
+#define DMA_TOG_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
+ * follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CITER_ELINKNO register
+ */
+/*@{*/
+#define DMA_RD_CITER_ELINKNO(base, index) (DMA_CITER_ELINKNO_REG(base, index))
+#define DMA_WR_CITER_ELINKNO(base, index, value) (DMA_CITER_ELINKNO_REG(base, index) = (value))
+#define DMA_RMW_CITER_ELINKNO(base, index, mask, value) (DMA_WR_CITER_ELINKNO(base, index, (DMA_RD_CITER_ELINKNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) |  (value)))
+#define DMA_CLR_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) & ~(value)))
+#define DMA_TOG_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_CITER_ELINKNO, field CITER[14:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKNO_CITER field. */
+#define DMA_RD_CITER_ELINKNO_CITER(base, index) ((DMA_CITER_ELINKNO_REG(base, index) & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT)
+#define DMA_BRD_CITER_ELINKNO_CITER(base, index) (DMA_RD_CITER_ELINKNO_CITER(base, index))
+
+/*! @brief Set the CITER field to a new value. */
+#define DMA_WR_CITER_ELINKNO_CITER(base, index, value) (DMA_RMW_CITER_ELINKNO(base, index, DMA_CITER_ELINKNO_CITER_MASK, DMA_CITER_ELINKNO_CITER(value)))
+#define DMA_BWR_CITER_ELINKNO_CITER(base, index, value) (DMA_WR_CITER_ELINKNO_CITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKNO_ELINK field. */
+#define DMA_RD_CITER_ELINKNO_ELINK(base, index) ((DMA_CITER_ELINKNO_REG(base, index) & DMA_CITER_ELINKNO_ELINK_MASK) >> DMA_CITER_ELINKNO_ELINK_SHIFT)
+#define DMA_BRD_CITER_ELINKNO_ELINK(base, index) (BITBAND_ACCESS16(&DMA_CITER_ELINKNO_REG(base, index), DMA_CITER_ELINKNO_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_CITER_ELINKNO_ELINK(base, index, value) (DMA_RMW_CITER_ELINKNO(base, index, DMA_CITER_ELINKNO_ELINK_MASK, DMA_CITER_ELINKNO_ELINK(value)))
+#define DMA_BWR_CITER_ELINKNO_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CITER_ELINKNO_REG(base, index), DMA_CITER_ELINKNO_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CITER_ELINKYES register
+ */
+/*@{*/
+#define DMA_RD_CITER_ELINKYES(base, index) (DMA_CITER_ELINKYES_REG(base, index))
+#define DMA_WR_CITER_ELINKYES(base, index, value) (DMA_CITER_ELINKYES_REG(base, index) = (value))
+#define DMA_RMW_CITER_ELINKYES(base, index, mask, value) (DMA_WR_CITER_ELINKYES(base, index, (DMA_RD_CITER_ELINKYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) |  (value)))
+#define DMA_CLR_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) & ~(value)))
+#define DMA_TOG_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field CITER[8:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_CITER field. */
+#define DMA_RD_CITER_ELINKYES_CITER(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_CITER(base, index) (DMA_RD_CITER_ELINKYES_CITER(base, index))
+
+/*! @brief Set the CITER field to a new value. */
+#define DMA_WR_CITER_ELINKYES_CITER(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_CITER_MASK, DMA_CITER_ELINKYES_CITER(value)))
+#define DMA_BWR_CITER_ELINKYES_CITER(base, index, value) (DMA_WR_CITER_ELINKYES_CITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request to the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_LINKCH field. */
+#define DMA_RD_CITER_ELINKYES_LINKCH(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_LINKCH_MASK) >> DMA_CITER_ELINKYES_LINKCH_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_LINKCH(base, index) (DMA_RD_CITER_ELINKYES_LINKCH(base, index))
+
+/*! @brief Set the LINKCH field to a new value. */
+#define DMA_WR_CITER_ELINKYES_LINKCH(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_LINKCH_MASK, DMA_CITER_ELINKYES_LINKCH(value)))
+#define DMA_BWR_CITER_ELINKYES_LINKCH(base, index, value) (DMA_WR_CITER_ELINKYES_LINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_ELINK field. */
+#define DMA_RD_CITER_ELINKYES_ELINK(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_ELINK_MASK) >> DMA_CITER_ELINKYES_ELINK_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_ELINK(base, index) (BITBAND_ACCESS16(&DMA_CITER_ELINKYES_REG(base, index), DMA_CITER_ELINKYES_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_CITER_ELINKYES_ELINK(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_ELINK_MASK, DMA_CITER_ELINKYES_ELINK(value)))
+#define DMA_BWR_CITER_ELINKYES_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CITER_ELINKYES_REG(base, index), DMA_CITER_ELINKYES_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DLAST_SGA register
+ */
+/*@{*/
+#define DMA_RD_DLAST_SGA(base, index) (DMA_DLAST_SGA_REG(base, index))
+#define DMA_WR_DLAST_SGA(base, index, value) (DMA_DLAST_SGA_REG(base, index) = (value))
+#define DMA_RMW_DLAST_SGA(base, index, mask, value) (DMA_WR_DLAST_SGA(base, index, (DMA_RD_DLAST_SGA(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) |  (value)))
+#define DMA_CLR_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) & ~(value)))
+#define DMA_TOG_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CSR - TCD Control and Status
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CSR - TCD Control and Status (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_CSR register
+ */
+/*@{*/
+#define DMA_RD_CSR(base, index)  (DMA_CSR_REG(base, index))
+#define DMA_WR_CSR(base, index, value) (DMA_CSR_REG(base, index) = (value))
+#define DMA_RMW_CSR(base, index, mask, value) (DMA_WR_CSR(base, index, (DMA_RD_CSR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) |  (value)))
+#define DMA_CLR_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) & ~(value)))
+#define DMA_TOG_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CSR bitfields
+ */
+
+/*!
+ * @name Register DMA_CSR, field START[0] (RW)
+ *
+ * If this flag is set, the channel is requesting service. The eDMA hardware
+ * automatically clears this flag after the channel begins execution.
+ *
+ * Values:
+ * - 0b0 - The channel is not explicitly started
+ * - 0b1 - The channel is explicitly started via a software initiated service
+ *     request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_START field. */
+#define DMA_RD_CSR_START(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_START_MASK) >> DMA_CSR_START_SHIFT)
+#define DMA_BRD_CSR_START(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_START_SHIFT))
+
+/*! @brief Set the START field to a new value. */
+#define DMA_WR_CSR_START(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_START_MASK, DMA_CSR_START(value)))
+#define DMA_BWR_CSR_START(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_START_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field INTMAJOR[1] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT when the current major iteration count reaches
+ * zero.
+ *
+ * Values:
+ * - 0b0 - The end-of-major loop interrupt is disabled
+ * - 0b1 - The end-of-major loop interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_INTMAJOR field. */
+#define DMA_RD_CSR_INTMAJOR(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_INTMAJOR_MASK) >> DMA_CSR_INTMAJOR_SHIFT)
+#define DMA_BRD_CSR_INTMAJOR(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTMAJOR_SHIFT))
+
+/*! @brief Set the INTMAJOR field to a new value. */
+#define DMA_WR_CSR_INTMAJOR(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_INTMAJOR_MASK, DMA_CSR_INTMAJOR(value)))
+#define DMA_BWR_CSR_INTMAJOR(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTMAJOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field INTHALF[2] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT register when the current major iteration count
+ * reaches the halfway point. Specifically, the comparison performed by the eDMA
+ * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
+ * provided to support double-buffered (aka ping-pong) schemes or other types of data
+ * movement where the processor needs an early indication of the transfer's
+ * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
+ *
+ * Values:
+ * - 0b0 - The half-point interrupt is disabled
+ * - 0b1 - The half-point interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_INTHALF field. */
+#define DMA_RD_CSR_INTHALF(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_INTHALF_MASK) >> DMA_CSR_INTHALF_SHIFT)
+#define DMA_BRD_CSR_INTHALF(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTHALF_SHIFT))
+
+/*! @brief Set the INTHALF field to a new value. */
+#define DMA_WR_CSR_INTHALF(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_INTHALF_MASK, DMA_CSR_INTHALF(value)))
+#define DMA_BWR_CSR_INTHALF(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTHALF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field DREQ[3] (RW)
+ *
+ * If this flag is set, the eDMA hardware automatically clears the corresponding
+ * ERQ bit when the current major iteration count reaches zero.
+ *
+ * Values:
+ * - 0b0 - The channel's ERQ bit is not affected
+ * - 0b1 - The channel's ERQ bit is cleared when the major loop is complete
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_DREQ field. */
+#define DMA_RD_CSR_DREQ(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_DREQ_MASK) >> DMA_CSR_DREQ_SHIFT)
+#define DMA_BRD_CSR_DREQ(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DREQ_SHIFT))
+
+/*! @brief Set the DREQ field to a new value. */
+#define DMA_WR_CSR_DREQ(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_DREQ_MASK, DMA_CSR_DREQ(value)))
+#define DMA_BWR_CSR_DREQ(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field ESG[4] (RW)
+ *
+ * As the channel completes the major loop, this flag enables scatter/gather
+ * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
+ * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
+ * loaded as the transfer control descriptor into the local memory. To support the
+ * dynamic scatter/gather coherency model, this field is forced to zero when
+ * written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0b0 - The current channel's TCD is normal format.
+ * - 0b1 - The current channel's TCD specifies a scatter gather format. The
+ *     DLASTSGA field provides a memory pointer to the next TCD to be loaded into
+ *     this channel after the major loop completes its execution.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_ESG field. */
+#define DMA_RD_CSR_ESG(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_ESG_MASK) >> DMA_CSR_ESG_SHIFT)
+#define DMA_BRD_CSR_ESG(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ESG_SHIFT))
+
+/*! @brief Set the ESG field to a new value. */
+#define DMA_WR_CSR_ESG(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_ESG_MASK, DMA_CSR_ESG(value)))
+#define DMA_BWR_CSR_ESG(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ESG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field MAJORELINK[5] (RW)
+ *
+ * As the channel completes the major loop, this flag enables the linking to
+ * another channel, defined by MAJORLINKCH. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. To support the dynamic linking coherency model,
+ * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_MAJORELINK field. */
+#define DMA_RD_CSR_MAJORELINK(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_MAJORELINK_MASK) >> DMA_CSR_MAJORELINK_SHIFT)
+#define DMA_BRD_CSR_MAJORELINK(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_MAJORELINK_SHIFT))
+
+/*! @brief Set the MAJORELINK field to a new value. */
+#define DMA_WR_CSR_MAJORELINK(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_MAJORELINK_MASK, DMA_CSR_MAJORELINK(value)))
+#define DMA_BWR_CSR_MAJORELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_MAJORELINK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field ACTIVE[6] (RW)
+ *
+ * This flag signals the channel is currently in execution. It is set when
+ * channel service begins, and the eDMA clears it as the minor loop completes or if
+ * any error condition is detected. This bit resets to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_ACTIVE field. */
+#define DMA_RD_CSR_ACTIVE(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_ACTIVE_MASK) >> DMA_CSR_ACTIVE_SHIFT)
+#define DMA_BRD_CSR_ACTIVE(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ACTIVE_SHIFT))
+
+/*! @brief Set the ACTIVE field to a new value. */
+#define DMA_WR_CSR_ACTIVE(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_ACTIVE_MASK, DMA_CSR_ACTIVE(value)))
+#define DMA_BWR_CSR_ACTIVE(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ACTIVE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field DONE[7] (RW)
+ *
+ * This flag indicates the eDMA has completed the major loop. The eDMA engine
+ * sets it as the CITER count reaches zero; The software clears it, or the hardware
+ * when the channel is activated. This bit must be cleared to write the
+ * MAJORELINK or ESG bits.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_DONE field. */
+#define DMA_RD_CSR_DONE(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT)
+#define DMA_BRD_CSR_DONE(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DONE_SHIFT))
+
+/*! @brief Set the DONE field to a new value. */
+#define DMA_WR_CSR_DONE(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_DONE_MASK, DMA_CSR_DONE(value)))
+#define DMA_BWR_CSR_DONE(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DONE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field MAJORLINKCH[11:8] (RW)
+ *
+ * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
+ * performed after the major loop counter is exhausted. else After the major loop
+ * counter is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_MAJORLINKCH field. */
+#define DMA_RD_CSR_MAJORLINKCH(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_MAJORLINKCH_MASK) >> DMA_CSR_MAJORLINKCH_SHIFT)
+#define DMA_BRD_CSR_MAJORLINKCH(base, index) (DMA_RD_CSR_MAJORLINKCH(base, index))
+
+/*! @brief Set the MAJORLINKCH field to a new value. */
+#define DMA_WR_CSR_MAJORLINKCH(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_MAJORLINKCH_MASK, DMA_CSR_MAJORLINKCH(value)))
+#define DMA_BWR_CSR_MAJORLINKCH(base, index, value) (DMA_WR_CSR_MAJORLINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field BWC[15:14] (RW)
+ *
+ * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
+ * the eDMA processes the minor loop, it continuously generates read/write
+ * sequences until the minor count is exhausted. This field forces the eDMA to stall
+ * after the completion of each read/write access to control the bus request
+ * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
+ * this field is ignored between the first and second transfers and after the
+ * last write of each minor loop. This behavior is a side effect of reducing
+ * start-up latency.
+ *
+ * Values:
+ * - 0b00 - No eDMA engine stalls
+ * - 0b01 - Reserved
+ * - 0b10 - eDMA engine stalls for 4 cycles after each r/w
+ * - 0b11 - eDMA engine stalls for 8 cycles after each r/w
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_BWC field. */
+#define DMA_RD_CSR_BWC(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_BWC_MASK) >> DMA_CSR_BWC_SHIFT)
+#define DMA_BRD_CSR_BWC(base, index) (DMA_RD_CSR_BWC(base, index))
+
+/*! @brief Set the BWC field to a new value. */
+#define DMA_WR_CSR_BWC(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_BWC_MASK, DMA_CSR_BWC(value)))
+#define DMA_BWR_CSR_BWC(base, index, value) (DMA_WR_CSR_BWC(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
+ * follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_BITER_ELINKYES register
+ */
+/*@{*/
+#define DMA_RD_BITER_ELINKYES(base, index) (DMA_BITER_ELINKYES_REG(base, index))
+#define DMA_WR_BITER_ELINKYES(base, index, value) (DMA_BITER_ELINKYES_REG(base, index) = (value))
+#define DMA_RMW_BITER_ELINKYES(base, index, mask, value) (DMA_WR_BITER_ELINKYES(base, index, (DMA_RD_BITER_ELINKYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) |  (value)))
+#define DMA_CLR_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) & ~(value)))
+#define DMA_TOG_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_BITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field BITER[8:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_BITER field. */
+#define DMA_RD_BITER_ELINKYES_BITER(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_BITER_MASK) >> DMA_BITER_ELINKYES_BITER_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_BITER(base, index) (DMA_RD_BITER_ELINKYES_BITER(base, index))
+
+/*! @brief Set the BITER field to a new value. */
+#define DMA_WR_BITER_ELINKYES_BITER(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_BITER_MASK, DMA_BITER_ELINKYES_BITER(value)))
+#define DMA_BWR_BITER_ELINKYES_BITER(base, index, value) (DMA_WR_BITER_ELINKYES_BITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START]
+ * bit. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the major
+ * iteration count is exhausted, the contents of this field is reloaded into the
+ * CITER field.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_LINKCH field. */
+#define DMA_RD_BITER_ELINKYES_LINKCH(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_LINKCH_MASK) >> DMA_BITER_ELINKYES_LINKCH_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_LINKCH(base, index) (DMA_RD_BITER_ELINKYES_LINKCH(base, index))
+
+/*! @brief Set the LINKCH field to a new value. */
+#define DMA_WR_BITER_ELINKYES_LINKCH(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_LINKCH_MASK, DMA_BITER_ELINKYES_LINKCH(value)))
+#define DMA_BWR_BITER_ELINKYES_LINKCH(base, index, value) (DMA_WR_BITER_ELINKYES_LINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking disables, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded into
+ * the CITER field.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_ELINK field. */
+#define DMA_RD_BITER_ELINKYES_ELINK(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_ELINK_MASK) >> DMA_BITER_ELINKYES_ELINK_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_ELINK(base, index) (BITBAND_ACCESS16(&DMA_BITER_ELINKYES_REG(base, index), DMA_BITER_ELINKYES_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_BITER_ELINKYES_ELINK(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_ELINK_MASK, DMA_BITER_ELINKYES_ELINK(value)))
+#define DMA_BWR_BITER_ELINKYES_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_BITER_ELINKYES_REG(base, index), DMA_BITER_ELINKYES_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
+ * as follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_BITER_ELINKNO register
+ */
+/*@{*/
+#define DMA_RD_BITER_ELINKNO(base, index) (DMA_BITER_ELINKNO_REG(base, index))
+#define DMA_WR_BITER_ELINKNO(base, index, value) (DMA_BITER_ELINKNO_REG(base, index) = (value))
+#define DMA_RMW_BITER_ELINKNO(base, index, mask, value) (DMA_WR_BITER_ELINKNO(base, index, (DMA_RD_BITER_ELINKNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) |  (value)))
+#define DMA_CLR_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) & ~(value)))
+#define DMA_TOG_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_BITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_BITER_ELINKNO, field BITER[14:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKNO_BITER field. */
+#define DMA_RD_BITER_ELINKNO_BITER(base, index) ((DMA_BITER_ELINKNO_REG(base, index) & DMA_BITER_ELINKNO_BITER_MASK) >> DMA_BITER_ELINKNO_BITER_SHIFT)
+#define DMA_BRD_BITER_ELINKNO_BITER(base, index) (DMA_RD_BITER_ELINKNO_BITER(base, index))
+
+/*! @brief Set the BITER field to a new value. */
+#define DMA_WR_BITER_ELINKNO_BITER(base, index, value) (DMA_RMW_BITER_ELINKNO(base, index, DMA_BITER_ELINKNO_BITER_MASK, DMA_BITER_ELINKNO_BITER(value)))
+#define DMA_BWR_BITER_ELINKNO_BITER(base, index, value) (DMA_WR_BITER_ELINKNO_BITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded
+ * into the CITER field.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKNO_ELINK field. */
+#define DMA_RD_BITER_ELINKNO_ELINK(base, index) ((DMA_BITER_ELINKNO_REG(base, index) & DMA_BITER_ELINKNO_ELINK_MASK) >> DMA_BITER_ELINKNO_ELINK_SHIFT)
+#define DMA_BRD_BITER_ELINKNO_ELINK(base, index) (BITBAND_ACCESS16(&DMA_BITER_ELINKNO_REG(base, index), DMA_BITER_ELINKNO_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_BITER_ELINKNO_ELINK(base, index, value) (DMA_RMW_BITER_ELINKNO(base, index, DMA_BITER_ELINKNO_ELINK_MASK, DMA_BITER_ELINKNO_ELINK(value)))
+#define DMA_BWR_BITER_ELINKNO_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_BITER_ELINKNO_REG(base, index), DMA_BITER_ELINKNO_ELINK_SHIFT) = (value))
+/*@}*/
+
+/* Register macros for indexed access to DMA channel priority registers */
+/*
+ * Constants and macros for entire DMA_DCHPRIn register
+ */
+#define DMA_DCHPRIn_INDEX(channel)          (((channel) & ~0x03U) | (3 - ((channel) & 0x03U)))
+#define DMA_DCHPRIn_REG(base, index)        (((volatile uint8_t *)&DMA_DCHPRI3_REG(base))[DMA_DCHPRIn_INDEX(index)])
+#define DMA_RD_DCHPRIn(base, index)         (DMA_DCHPRIn_REG((base), (index)))
+#define DMA_WR_DCHPRIn(base, index, value)  (DMA_DCHPRIn_REG((base), (index)) = (value))
+#define DMA_SET_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) |  (value)))
+#define DMA_CLR_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) & ~(value)))
+#define DMA_TOG_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) ^  (value)))
+
+/*
+ * Register DMA_DCHPRIn, bit field CHPRI
+ */
+/* Read current value of the CHPRI bit field. */
+#define DMA_RD_DCHPRIn_CHPRI(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_CHPRI_MASK) >> DMA_DCHPRI0_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRIn_CHPRI(base, index) (DMA_RD_DCHPRIn_CHPRI((base), (index)))
+
+/* Set the CHPRI bit field to a new value. */
+#define DMA_WR_DCHPRIn_CHPRI(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_CHPRI_MASK) | DMA_DCHPRI0_CHPRI(value)))
+#define DMA_BWR_DCHPRIn_CHPRI(base, index, value) (DMA_WR_DCHPRIn_CHPRI((base), (index), (value)))
+
+/*
+ * Register DMA_DCHPRIn, bit field DPA
+ */
+/* Read current value of the DPA bit field. */
+#define DMA_RD_DCHPRIn_DPA(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_DPA_MASK) >> DMA_DCHPRI0_DPA_SHIFT)
+#define DMA_BRD_DCHPRIn_DPA(base, index) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_DPA_SHIFT))
+
+/* Set the DPA bit field to a new value. */
+#define DMA_WR_DCHPRIn_DPA(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_DPA_MASK) | DMA_DCHPRI0_DPA(value)))
+#define DMA_BWR_DCHPRIn_DPA(base, index, value) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_DPA_SHIFT) = (value))
+
+/*
+ * Register DMA_DCHPRIn, bit field ECP
+ */
+/* Read current value of the ECP bit field. */
+#define DMA_RD_DCHPRIn_ECP(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_ECP_MASK) >> DMA_DCHPRI0_ECP_SHIFT)
+#define DMA_BRD_DCHPRIn_ECP(base, index) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_ECP_SHIFT))
+
+/* Set the ECP bit field to a new value. */
+#define DMA_WR_DCHPRIn_ECP(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_ECP_MASK) | DMA_DCHPRI0_ECP(value)))
+#define DMA_BWR_DCHPRIn_ECP(base, index, value) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_ECP_SHIFT) = (value))
+
+/*
+ * MK64F12 DMAMUX
+ *
+ * DMA channel multiplexor
+ *
+ * Registers defined in this header file:
+ * - DMAMUX_CHCFG - Channel Configuration register
+ */
+
+#define DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
+#define DMAMUX_IDX (0U) /*!< Instance number for DMAMUX. */
+
+/*******************************************************************************
+ * DMAMUX_CHCFG - Channel Configuration register
+ ******************************************************************************/
+
+/*!
+ * @brief DMAMUX_CHCFG - Channel Configuration register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Each of the DMA channels can be independently enabled/disabled and associated
+ * with one of the DMA slots (peripheral slots or always-on slots) in the
+ * system. Setting multiple CHCFG registers with the same source value will result in
+ * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
+ * Before changing the trigger or source settings, a DMA channel must be disabled
+ * via CHCFGn[ENBL].
+ */
+/*!
+ * @name Constants and macros for entire DMAMUX_CHCFG register
+ */
+/*@{*/
+#define DMAMUX_RD_CHCFG(base, index) (DMAMUX_CHCFG_REG(base, index))
+#define DMAMUX_WR_CHCFG(base, index, value) (DMAMUX_CHCFG_REG(base, index) = (value))
+#define DMAMUX_RMW_CHCFG(base, index, mask, value) (DMAMUX_WR_CHCFG(base, index, (DMAMUX_RD_CHCFG(base, index) & ~(mask)) | (value)))
+#define DMAMUX_SET_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) |  (value)))
+#define DMAMUX_CLR_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) & ~(value)))
+#define DMAMUX_TOG_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMAMUX_CHCFG bitfields
+ */
+
+/*!
+ * @name Register DMAMUX_CHCFG, field SOURCE[5:0] (RW)
+ *
+ * Specifies which DMA source, if any, is routed to a particular DMA channel.
+ * See your device's chip configuration details for information about the
+ * peripherals and their slot numbers.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_SOURCE field. */
+#define DMAMUX_RD_CHCFG_SOURCE(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT)
+#define DMAMUX_BRD_CHCFG_SOURCE(base, index) (DMAMUX_RD_CHCFG_SOURCE(base, index))
+
+/*! @brief Set the SOURCE field to a new value. */
+#define DMAMUX_WR_CHCFG_SOURCE(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_SOURCE_MASK, DMAMUX_CHCFG_SOURCE(value)))
+#define DMAMUX_BWR_CHCFG_SOURCE(base, index, value) (DMAMUX_WR_CHCFG_SOURCE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field TRIG[6] (RW)
+ *
+ * Enables the periodic trigger capability for the triggered DMA channel.
+ *
+ * Values:
+ * - 0b0 - Triggering is disabled. If triggering is disabled and ENBL is set,
+ *     the DMA Channel will simply route the specified source to the DMA channel.
+ *     (Normal mode)
+ * - 0b1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
+ *     DMAMUX is in Periodic Trigger mode.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_TRIG field. */
+#define DMAMUX_RD_CHCFG_TRIG(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_TRIG_MASK) >> DMAMUX_CHCFG_TRIG_SHIFT)
+#define DMAMUX_BRD_CHCFG_TRIG(base, index) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT))
+
+/*! @brief Set the TRIG field to a new value. */
+#define DMAMUX_WR_CHCFG_TRIG(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_TRIG_MASK, DMAMUX_CHCFG_TRIG(value)))
+#define DMAMUX_BWR_CHCFG_TRIG(base, index, value) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field ENBL[7] (RW)
+ *
+ * Enables the DMA channel.
+ *
+ * Values:
+ * - 0b0 - DMA channel is disabled. This mode is primarily used during
+ *     configuration of the DMAMux. The DMA has separate channel enables/disables, which
+ *     should be used to disable or reconfigure a DMA channel.
+ * - 0b1 - DMA channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_ENBL field. */
+#define DMAMUX_RD_CHCFG_ENBL(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT)
+#define DMAMUX_BRD_CHCFG_ENBL(base, index) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT))
+
+/*! @brief Set the ENBL field to a new value. */
+#define DMAMUX_WR_CHCFG_ENBL(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_ENBL_MASK, DMAMUX_CHCFG_ENBL(value)))
+#define DMAMUX_BWR_CHCFG_ENBL(base, index, value) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 ENET
+ *
+ * Ethernet MAC-NET Core
+ *
+ * Registers defined in this header file:
+ * - ENET_EIR - Interrupt Event Register
+ * - ENET_EIMR - Interrupt Mask Register
+ * - ENET_RDAR - Receive Descriptor Active Register
+ * - ENET_TDAR - Transmit Descriptor Active Register
+ * - ENET_ECR - Ethernet Control Register
+ * - ENET_MMFR - MII Management Frame Register
+ * - ENET_MSCR - MII Speed Control Register
+ * - ENET_MIBC - MIB Control Register
+ * - ENET_RCR - Receive Control Register
+ * - ENET_TCR - Transmit Control Register
+ * - ENET_PALR - Physical Address Lower Register
+ * - ENET_PAUR - Physical Address Upper Register
+ * - ENET_OPD - Opcode/Pause Duration Register
+ * - ENET_IAUR - Descriptor Individual Upper Address Register
+ * - ENET_IALR - Descriptor Individual Lower Address Register
+ * - ENET_GAUR - Descriptor Group Upper Address Register
+ * - ENET_GALR - Descriptor Group Lower Address Register
+ * - ENET_TFWR - Transmit FIFO Watermark Register
+ * - ENET_RDSR - Receive Descriptor Ring Start Register
+ * - ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ * - ENET_MRBR - Maximum Receive Buffer Size Register
+ * - ENET_RSFL - Receive FIFO Section Full Threshold
+ * - ENET_RSEM - Receive FIFO Section Empty Threshold
+ * - ENET_RAEM - Receive FIFO Almost Empty Threshold
+ * - ENET_RAFL - Receive FIFO Almost Full Threshold
+ * - ENET_TSEM - Transmit FIFO Section Empty Threshold
+ * - ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ * - ENET_TAFL - Transmit FIFO Almost Full Threshold
+ * - ENET_TIPG - Transmit Inter-Packet Gap
+ * - ENET_FTRL - Frame Truncation Length
+ * - ENET_TACC - Transmit Accelerator Function Configuration
+ * - ENET_RACC - Receive Accelerator Function Configuration
+ * - ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ * - ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ * - ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ * - ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ * - ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ * - ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ * - ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ * - ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ * - ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ * - ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ * - ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ * - ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ * - ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ * - ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ * - ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ * - ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ * - ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ * - ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ * - ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ * - ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ * - ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ * - ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ * - ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ * - ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ * - ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ * - ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ * - ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ * - ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ * - ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ * - ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ * - ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ * - ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ * - ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ * - ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ * - ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ * - ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ * - ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ * - ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ * - ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ * - ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ * - ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ * - ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ * - ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ * - ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ * - ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ * - ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ * - ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ * - ENET_ATCR - Adjustable Timer Control Register
+ * - ENET_ATVR - Timer Value Register
+ * - ENET_ATOFF - Timer Offset Register
+ * - ENET_ATPER - Timer Period Register
+ * - ENET_ATCOR - Timer Correction Register
+ * - ENET_ATINC - Time-Stamping Clock Period Register
+ * - ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ * - ENET_TGSR - Timer Global Status Register
+ * - ENET_TCSR - Timer Control Status Register
+ * - ENET_TCCR - Timer Compare Capture Register
+ */
+
+#define ENET_INSTANCE_COUNT (1U) /*!< Number of instances of the ENET module. */
+#define ENET_IDX (0U) /*!< Instance number for ENET. */
+
+/*******************************************************************************
+ * ENET_EIR - Interrupt Event Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_EIR - Interrupt Event Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an event occurs that sets a bit in EIR, an interrupt occurs if the
+ * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
+ * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
+ * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
+ * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
+ * Legacy mode does not require these flags to be enabled.
+ */
+/*!
+ * @name Constants and macros for entire ENET_EIR register
+ */
+/*@{*/
+#define ENET_RD_EIR(base)        (ENET_EIR_REG(base))
+#define ENET_WR_EIR(base, value) (ENET_EIR_REG(base) = (value))
+#define ENET_RMW_EIR(base, mask, value) (ENET_WR_EIR(base, (ENET_RD_EIR(base) & ~(mask)) | (value)))
+#define ENET_SET_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) |  (value)))
+#define ENET_CLR_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) & ~(value)))
+#define ENET_TOG_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_EIR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
+ *
+ * The adjustable timer reached the period event. A period event interrupt can
+ * be generated if ATCR[PEREN] is set and the timer wraps according to the
+ * periodic setting in the ATPER register. Set the timer period value before setting
+ * ATCR[PEREN].
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TS_TIMER field. */
+#define ENET_RD_EIR_TS_TIMER(base) ((ENET_EIR_REG(base) & ENET_EIR_TS_TIMER_MASK) >> ENET_EIR_TS_TIMER_SHIFT)
+#define ENET_BRD_EIR_TS_TIMER(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_TIMER_SHIFT))
+
+/*! @brief Set the TS_TIMER field to a new value. */
+#define ENET_WR_EIR_TS_TIMER(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TS_TIMER(value)))
+#define ENET_BWR_EIR_TS_TIMER(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_TIMER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
+ *
+ * Indicates that the timestamp of the last transmitted timing frame is
+ * available in the ATSTMP register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TS_AVAIL field. */
+#define ENET_RD_EIR_TS_AVAIL(base) ((ENET_EIR_REG(base) & ENET_EIR_TS_AVAIL_MASK) >> ENET_EIR_TS_AVAIL_SHIFT)
+#define ENET_BRD_EIR_TS_AVAIL(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_AVAIL_SHIFT))
+
+/*! @brief Set the TS_AVAIL field to a new value. */
+#define ENET_WR_EIR_TS_AVAIL(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TS_AVAIL_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TS_AVAIL(value)))
+#define ENET_BWR_EIR_TS_AVAIL(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_AVAIL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field WAKEUP[17] (W1C)
+ *
+ * Read-only status bit to indicate that a magic packet has been detected. Will
+ * act only if ECR[MAGICEN] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_WAKEUP field. */
+#define ENET_RD_EIR_WAKEUP(base) ((ENET_EIR_REG(base) & ENET_EIR_WAKEUP_MASK) >> ENET_EIR_WAKEUP_SHIFT)
+#define ENET_BRD_EIR_WAKEUP(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_WAKEUP_SHIFT))
+
+/*! @brief Set the WAKEUP field to a new value. */
+#define ENET_WR_EIR_WAKEUP(base, value) (ENET_RMW_EIR(base, (ENET_EIR_WAKEUP_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_WAKEUP(value)))
+#define ENET_BWR_EIR_WAKEUP(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_WAKEUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field PLR[18] (W1C)
+ *
+ * Indicates a frame was received with a payload length error. See Frame
+ * Length/Type Verification: Payload Length Check for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_PLR field. */
+#define ENET_RD_EIR_PLR(base) ((ENET_EIR_REG(base) & ENET_EIR_PLR_MASK) >> ENET_EIR_PLR_SHIFT)
+#define ENET_BRD_EIR_PLR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_PLR_SHIFT))
+
+/*! @brief Set the PLR field to a new value. */
+#define ENET_WR_EIR_PLR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_PLR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_PLR(value)))
+#define ENET_BWR_EIR_PLR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_PLR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field UN[19] (W1C)
+ *
+ * Indicates the transmit FIFO became empty before the complete frame was
+ * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
+ * frame is discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_UN field. */
+#define ENET_RD_EIR_UN(base) ((ENET_EIR_REG(base) & ENET_EIR_UN_MASK) >> ENET_EIR_UN_SHIFT)
+#define ENET_BRD_EIR_UN(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_UN_SHIFT))
+
+/*! @brief Set the UN field to a new value. */
+#define ENET_WR_EIR_UN(base, value) (ENET_RMW_EIR(base, (ENET_EIR_UN_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_UN(value)))
+#define ENET_BWR_EIR_UN(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_UN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RL[20] (W1C)
+ *
+ * Indicates a collision occurred on each of 16 successive attempts to transmit
+ * the frame. The frame is discarded without being transmitted and transmission
+ * of the next frame commences. This error can only occur in half-duplex mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RL field. */
+#define ENET_RD_EIR_RL(base) ((ENET_EIR_REG(base) & ENET_EIR_RL_MASK) >> ENET_EIR_RL_SHIFT)
+#define ENET_BRD_EIR_RL(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RL_SHIFT))
+
+/*! @brief Set the RL field to a new value. */
+#define ENET_WR_EIR_RL(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RL_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RL(value)))
+#define ENET_BWR_EIR_RL(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field LC[21] (W1C)
+ *
+ * Indicates a collision occurred beyond the collision window (slot time) in
+ * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
+ * frame is discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_LC field. */
+#define ENET_RD_EIR_LC(base) ((ENET_EIR_REG(base) & ENET_EIR_LC_MASK) >> ENET_EIR_LC_SHIFT)
+#define ENET_BRD_EIR_LC(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_LC_SHIFT))
+
+/*! @brief Set the LC field to a new value. */
+#define ENET_WR_EIR_LC(base, value) (ENET_RMW_EIR(base, (ENET_EIR_LC_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_LC(value)))
+#define ENET_BWR_EIR_LC(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_LC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field EBERR[22] (W1C)
+ *
+ * Indicates a system bus error occurred when a uDMA transaction is underway.
+ * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
+ * MAC. When this occurs, software must ensure proper actions, possibly resetting
+ * the system, to resume normal operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_EBERR field. */
+#define ENET_RD_EIR_EBERR(base) ((ENET_EIR_REG(base) & ENET_EIR_EBERR_MASK) >> ENET_EIR_EBERR_SHIFT)
+#define ENET_BRD_EIR_EBERR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_EBERR_SHIFT))
+
+/*! @brief Set the EBERR field to a new value. */
+#define ENET_WR_EIR_EBERR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_EBERR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_EBERR(value)))
+#define ENET_BWR_EIR_EBERR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_EBERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field MII[23] (W1C)
+ *
+ * Indicates that the MII has completed the data transfer requested.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_MII field. */
+#define ENET_RD_EIR_MII(base) ((ENET_EIR_REG(base) & ENET_EIR_MII_MASK) >> ENET_EIR_MII_SHIFT)
+#define ENET_BRD_EIR_MII(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_MII_SHIFT))
+
+/*! @brief Set the MII field to a new value. */
+#define ENET_WR_EIR_MII(base, value) (ENET_RMW_EIR(base, (ENET_EIR_MII_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_MII(value)))
+#define ENET_BWR_EIR_MII(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_MII_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RXB[24] (W1C)
+ *
+ * Indicates a receive buffer descriptor is not the last in the frame has been
+ * updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RXB field. */
+#define ENET_RD_EIR_RXB(base) ((ENET_EIR_REG(base) & ENET_EIR_RXB_MASK) >> ENET_EIR_RXB_SHIFT)
+#define ENET_BRD_EIR_RXB(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXB_SHIFT))
+
+/*! @brief Set the RXB field to a new value. */
+#define ENET_WR_EIR_RXB(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RXB_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RXB(value)))
+#define ENET_BWR_EIR_RXB(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RXF[25] (W1C)
+ *
+ * Indicates a frame has been received and the last corresponding buffer
+ * descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RXF field. */
+#define ENET_RD_EIR_RXF(base) ((ENET_EIR_REG(base) & ENET_EIR_RXF_MASK) >> ENET_EIR_RXF_SHIFT)
+#define ENET_BRD_EIR_RXF(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXF_SHIFT))
+
+/*! @brief Set the RXF field to a new value. */
+#define ENET_WR_EIR_RXF(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RXF_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RXF(value)))
+#define ENET_BWR_EIR_RXF(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TXB[26] (W1C)
+ *
+ * Indicates a transmit buffer descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TXB field. */
+#define ENET_RD_EIR_TXB(base) ((ENET_EIR_REG(base) & ENET_EIR_TXB_MASK) >> ENET_EIR_TXB_SHIFT)
+#define ENET_BRD_EIR_TXB(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXB_SHIFT))
+
+/*! @brief Set the TXB field to a new value. */
+#define ENET_WR_EIR_TXB(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TXB_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TXB(value)))
+#define ENET_BWR_EIR_TXB(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TXF[27] (W1C)
+ *
+ * Indicates a frame has been transmitted and the last corresponding buffer
+ * descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TXF field. */
+#define ENET_RD_EIR_TXF(base) ((ENET_EIR_REG(base) & ENET_EIR_TXF_MASK) >> ENET_EIR_TXF_SHIFT)
+#define ENET_BRD_EIR_TXF(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXF_SHIFT))
+
+/*! @brief Set the TXF field to a new value. */
+#define ENET_WR_EIR_TXF(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TXF_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TXF(value)))
+#define ENET_BWR_EIR_TXF(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field GRA[28] (W1C)
+ *
+ * This interrupt is asserted after the transmitter is put into a pause state
+ * after completion of the frame currently being transmitted. See Graceful Transmit
+ * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
+ * asserted only when the TX transitions into the stopped state. If this bit is
+ * cleared by writing 1 and the TX is still stopped, the bit is not set again.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_GRA field. */
+#define ENET_RD_EIR_GRA(base) ((ENET_EIR_REG(base) & ENET_EIR_GRA_MASK) >> ENET_EIR_GRA_SHIFT)
+#define ENET_BRD_EIR_GRA(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_GRA_SHIFT))
+
+/*! @brief Set the GRA field to a new value. */
+#define ENET_WR_EIR_GRA(base, value) (ENET_RMW_EIR(base, (ENET_EIR_GRA_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_GRA(value)))
+#define ENET_BWR_EIR_GRA(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_GRA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field BABT[29] (W1C)
+ *
+ * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
+ * this condition is caused when a frame that is too long is placed into the
+ * transmit data buffer(s). Truncation does not occur.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_BABT field. */
+#define ENET_RD_EIR_BABT(base) ((ENET_EIR_REG(base) & ENET_EIR_BABT_MASK) >> ENET_EIR_BABT_SHIFT)
+#define ENET_BRD_EIR_BABT(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABT_SHIFT))
+
+/*! @brief Set the BABT field to a new value. */
+#define ENET_WR_EIR_BABT(base, value) (ENET_RMW_EIR(base, (ENET_EIR_BABT_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABR_MASK), ENET_EIR_BABT(value)))
+#define ENET_BWR_EIR_BABT(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field BABR[30] (W1C)
+ *
+ * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_BABR field. */
+#define ENET_RD_EIR_BABR(base) ((ENET_EIR_REG(base) & ENET_EIR_BABR_MASK) >> ENET_EIR_BABR_SHIFT)
+#define ENET_BRD_EIR_BABR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABR_SHIFT))
+
+/*! @brief Set the BABR field to a new value. */
+#define ENET_WR_EIR_BABR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_BABR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK), ENET_EIR_BABR(value)))
+#define ENET_BWR_EIR_BABR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_EIMR - Interrupt Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_EIMR - Interrupt Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * EIMR controls which interrupt events are allowed to generate actual
+ * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
+ * and EIMR registers are set, an interrupt is generated. The interrupt signal
+ * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
+ * 0 is written to the EIMR field.
+ */
+/*!
+ * @name Constants and macros for entire ENET_EIMR register
+ */
+/*@{*/
+#define ENET_RD_EIMR(base)       (ENET_EIMR_REG(base))
+#define ENET_WR_EIMR(base, value) (ENET_EIMR_REG(base) = (value))
+#define ENET_RMW_EIMR(base, mask, value) (ENET_WR_EIMR(base, (ENET_RD_EIMR(base) & ~(mask)) | (value)))
+#define ENET_SET_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) |  (value)))
+#define ENET_CLR_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) & ~(value)))
+#define ENET_TOG_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_EIMR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_TIMER field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TS_TIMER field. */
+#define ENET_RD_EIMR_TS_TIMER(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TS_TIMER_MASK) >> ENET_EIMR_TS_TIMER_SHIFT)
+#define ENET_BRD_EIMR_TS_TIMER(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_TIMER_SHIFT))
+
+/*! @brief Set the TS_TIMER field to a new value. */
+#define ENET_WR_EIMR_TS_TIMER(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TS_TIMER_MASK, ENET_EIMR_TS_TIMER(value)))
+#define ENET_BWR_EIMR_TS_TIMER(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_TIMER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TS_AVAIL field. */
+#define ENET_RD_EIMR_TS_AVAIL(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TS_AVAIL_MASK) >> ENET_EIMR_TS_AVAIL_SHIFT)
+#define ENET_BRD_EIMR_TS_AVAIL(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_AVAIL_SHIFT))
+
+/*! @brief Set the TS_AVAIL field to a new value. */
+#define ENET_WR_EIMR_TS_AVAIL(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TS_AVAIL_MASK, ENET_EIMR_TS_AVAIL(value)))
+#define ENET_BWR_EIMR_TS_AVAIL(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_AVAIL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field WAKEUP[17] (RW)
+ *
+ * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR WAKEUP field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_WAKEUP field. */
+#define ENET_RD_EIMR_WAKEUP(base) ((ENET_EIMR_REG(base) & ENET_EIMR_WAKEUP_MASK) >> ENET_EIMR_WAKEUP_SHIFT)
+#define ENET_BRD_EIMR_WAKEUP(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_WAKEUP_SHIFT))
+
+/*! @brief Set the WAKEUP field to a new value. */
+#define ENET_WR_EIMR_WAKEUP(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_WAKEUP_MASK, ENET_EIMR_WAKEUP(value)))
+#define ENET_BWR_EIMR_WAKEUP(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_WAKEUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field PLR[18] (RW)
+ *
+ * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR PLR field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_PLR field. */
+#define ENET_RD_EIMR_PLR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_PLR_MASK) >> ENET_EIMR_PLR_SHIFT)
+#define ENET_BRD_EIMR_PLR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_PLR_SHIFT))
+
+/*! @brief Set the PLR field to a new value. */
+#define ENET_WR_EIMR_PLR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_PLR_MASK, ENET_EIMR_PLR(value)))
+#define ENET_BWR_EIMR_PLR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_PLR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field UN[19] (RW)
+ *
+ * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR UN field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_UN field. */
+#define ENET_RD_EIMR_UN(base) ((ENET_EIMR_REG(base) & ENET_EIMR_UN_MASK) >> ENET_EIMR_UN_SHIFT)
+#define ENET_BRD_EIMR_UN(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_UN_SHIFT))
+
+/*! @brief Set the UN field to a new value. */
+#define ENET_WR_EIMR_UN(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_UN_MASK, ENET_EIMR_UN(value)))
+#define ENET_BWR_EIMR_UN(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_UN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RL[20] (RW)
+ *
+ * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR RL field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RL field. */
+#define ENET_RD_EIMR_RL(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RL_MASK) >> ENET_EIMR_RL_SHIFT)
+#define ENET_BRD_EIMR_RL(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RL_SHIFT))
+
+/*! @brief Set the RL field to a new value. */
+#define ENET_WR_EIMR_RL(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RL_MASK, ENET_EIMR_RL(value)))
+#define ENET_BWR_EIMR_RL(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field LC[21] (RW)
+ *
+ * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR LC field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_LC field. */
+#define ENET_RD_EIMR_LC(base) ((ENET_EIMR_REG(base) & ENET_EIMR_LC_MASK) >> ENET_EIMR_LC_SHIFT)
+#define ENET_BRD_EIMR_LC(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_LC_SHIFT))
+
+/*! @brief Set the LC field to a new value. */
+#define ENET_WR_EIMR_LC(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_LC_MASK, ENET_EIMR_LC(value)))
+#define ENET_BWR_EIMR_LC(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_LC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field EBERR[22] (RW)
+ *
+ * Corresponds to interrupt source EIR[EBERR] and determines whether an
+ * interrupt condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR EBERR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_EBERR field. */
+#define ENET_RD_EIMR_EBERR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_EBERR_MASK) >> ENET_EIMR_EBERR_SHIFT)
+#define ENET_BRD_EIMR_EBERR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_EBERR_SHIFT))
+
+/*! @brief Set the EBERR field to a new value. */
+#define ENET_WR_EIMR_EBERR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_EBERR_MASK, ENET_EIMR_EBERR(value)))
+#define ENET_BWR_EIMR_EBERR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_EBERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field MII[23] (RW)
+ *
+ * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR MII field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_MII field. */
+#define ENET_RD_EIMR_MII(base) ((ENET_EIMR_REG(base) & ENET_EIMR_MII_MASK) >> ENET_EIMR_MII_SHIFT)
+#define ENET_BRD_EIMR_MII(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_MII_SHIFT))
+
+/*! @brief Set the MII field to a new value. */
+#define ENET_WR_EIMR_MII(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_MII_MASK, ENET_EIMR_MII(value)))
+#define ENET_BWR_EIMR_MII(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_MII_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RXB[24] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXB field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RXB field. */
+#define ENET_RD_EIMR_RXB(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RXB_MASK) >> ENET_EIMR_RXB_SHIFT)
+#define ENET_BRD_EIMR_RXB(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXB_SHIFT))
+
+/*! @brief Set the RXB field to a new value. */
+#define ENET_WR_EIMR_RXB(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RXB_MASK, ENET_EIMR_RXB(value)))
+#define ENET_BWR_EIMR_RXB(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RXF[25] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RXF field. */
+#define ENET_RD_EIMR_RXF(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RXF_MASK) >> ENET_EIMR_RXF_SHIFT)
+#define ENET_BRD_EIMR_RXF(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXF_SHIFT))
+
+/*! @brief Set the RXF field to a new value. */
+#define ENET_WR_EIMR_RXF(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RXF_MASK, ENET_EIMR_RXF(value)))
+#define ENET_BWR_EIMR_RXF(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TXB[26] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TXB field. */
+#define ENET_RD_EIMR_TXB(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TXB_MASK) >> ENET_EIMR_TXB_SHIFT)
+#define ENET_BRD_EIMR_TXB(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXB_SHIFT))
+
+/*! @brief Set the TXB field to a new value. */
+#define ENET_WR_EIMR_TXB(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TXB_MASK, ENET_EIMR_TXB(value)))
+#define ENET_BWR_EIMR_TXB(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TXF[27] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TXF field. */
+#define ENET_RD_EIMR_TXF(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TXF_MASK) >> ENET_EIMR_TXF_SHIFT)
+#define ENET_BRD_EIMR_TXF(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXF_SHIFT))
+
+/*! @brief Set the TXF field to a new value. */
+#define ENET_WR_EIMR_TXF(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TXF_MASK, ENET_EIMR_TXF(value)))
+#define ENET_BWR_EIMR_TXF(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field GRA[28] (RW)
+ *
+ * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR GRA field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_GRA field. */
+#define ENET_RD_EIMR_GRA(base) ((ENET_EIMR_REG(base) & ENET_EIMR_GRA_MASK) >> ENET_EIMR_GRA_SHIFT)
+#define ENET_BRD_EIMR_GRA(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_GRA_SHIFT))
+
+/*! @brief Set the GRA field to a new value. */
+#define ENET_WR_EIMR_GRA(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_GRA_MASK, ENET_EIMR_GRA(value)))
+#define ENET_BWR_EIMR_GRA(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_GRA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field BABT[29] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABT
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_BABT field. */
+#define ENET_RD_EIMR_BABT(base) ((ENET_EIMR_REG(base) & ENET_EIMR_BABT_MASK) >> ENET_EIMR_BABT_SHIFT)
+#define ENET_BRD_EIMR_BABT(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABT_SHIFT))
+
+/*! @brief Set the BABT field to a new value. */
+#define ENET_WR_EIMR_BABT(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_BABT_MASK, ENET_EIMR_BABT(value)))
+#define ENET_BWR_EIMR_BABT(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field BABR[30] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_BABR field. */
+#define ENET_RD_EIMR_BABR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_BABR_MASK) >> ENET_EIMR_BABR_SHIFT)
+#define ENET_BRD_EIMR_BABR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABR_SHIFT))
+
+/*! @brief Set the BABR field to a new value. */
+#define ENET_WR_EIMR_BABR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_BABR_MASK, ENET_EIMR_BABR(value)))
+#define ENET_BWR_EIMR_BABR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RDAR - Receive Descriptor Active Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RDAR - Receive Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDAR is a command register, written by the user, to indicate that the receive
+ * descriptor ring has been updated, that is, that the driver produced empty
+ * receive buffers with the empty bit set.
+ */
+/*!
+ * @name Constants and macros for entire ENET_RDAR register
+ */
+/*@{*/
+#define ENET_RD_RDAR(base)       (ENET_RDAR_REG(base))
+#define ENET_WR_RDAR(base, value) (ENET_RDAR_REG(base) = (value))
+#define ENET_RMW_RDAR(base, mask, value) (ENET_WR_RDAR(base, (ENET_RD_RDAR(base) & ~(mask)) | (value)))
+#define ENET_SET_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) |  (value)))
+#define ENET_CLR_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) & ~(value)))
+#define ENET_TOG_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDAR, field RDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This field is cleared by the MAC device when no additional empty
+ * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
+ * from set to cleared or when ECR[RESET] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RDAR_RDAR field. */
+#define ENET_RD_RDAR_RDAR(base) ((ENET_RDAR_REG(base) & ENET_RDAR_RDAR_MASK) >> ENET_RDAR_RDAR_SHIFT)
+#define ENET_BRD_RDAR_RDAR(base) (BITBAND_ACCESS32(&ENET_RDAR_REG(base), ENET_RDAR_RDAR_SHIFT))
+
+/*! @brief Set the RDAR field to a new value. */
+#define ENET_WR_RDAR_RDAR(base, value) (ENET_RMW_RDAR(base, ENET_RDAR_RDAR_MASK, ENET_RDAR_RDAR(value)))
+#define ENET_BWR_RDAR_RDAR(base, value) (BITBAND_ACCESS32(&ENET_RDAR_REG(base), ENET_RDAR_RDAR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TDAR - Transmit Descriptor Active Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TDAR - Transmit Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The TDAR is a command register that the user writes to indicate that the
+ * transmit descriptor ring has been updated, that is, that transmit buffers have
+ * been produced by the driver with the ready bit set in the buffer descriptor. The
+ * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
+ * cleared, or when ECR[RESET] is set.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TDAR register
+ */
+/*@{*/
+#define ENET_RD_TDAR(base)       (ENET_TDAR_REG(base))
+#define ENET_WR_TDAR(base, value) (ENET_TDAR_REG(base) = (value))
+#define ENET_RMW_TDAR(base, mask, value) (ENET_WR_TDAR(base, (ENET_RD_TDAR(base) & ~(mask)) | (value)))
+#define ENET_SET_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) |  (value)))
+#define ENET_CLR_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) & ~(value)))
+#define ENET_TOG_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDAR, field TDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This bit is cleared by the MAC device when no additional ready descriptors
+ * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
+ * set to cleared or when ECR[RESET] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TDAR_TDAR field. */
+#define ENET_RD_TDAR_TDAR(base) ((ENET_TDAR_REG(base) & ENET_TDAR_TDAR_MASK) >> ENET_TDAR_TDAR_SHIFT)
+#define ENET_BRD_TDAR_TDAR(base) (BITBAND_ACCESS32(&ENET_TDAR_REG(base), ENET_TDAR_TDAR_SHIFT))
+
+/*! @brief Set the TDAR field to a new value. */
+#define ENET_WR_TDAR_TDAR(base, value) (ENET_RMW_TDAR(base, ENET_TDAR_TDAR_MASK, ENET_TDAR_TDAR(value)))
+#define ENET_BWR_TDAR_TDAR(base, value) (BITBAND_ACCESS32(&ENET_TDAR_REG(base), ENET_TDAR_TDAR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ECR - Ethernet Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ECR - Ethernet Control Register (RW)
+ *
+ * Reset value: 0xF0000000U
+ *
+ * ECR is a read/write user register, though hardware may also alter fields in
+ * this register. It controls many of the high level features of the Ethernet MAC,
+ * including legacy FEC support through the EN1588 field.
+ */
+/*!
+ * @name Constants and macros for entire ENET_ECR register
+ */
+/*@{*/
+#define ENET_RD_ECR(base)        (ENET_ECR_REG(base))
+#define ENET_WR_ECR(base, value) (ENET_ECR_REG(base) = (value))
+#define ENET_RMW_ECR(base, mask, value) (ENET_WR_ECR(base, (ENET_RD_ECR(base) & ~(mask)) | (value)))
+#define ENET_SET_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) |  (value)))
+#define ENET_CLR_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) & ~(value)))
+#define ENET_TOG_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ECR bitfields
+ */
+
+/*!
+ * @name Register ENET_ECR, field RESET[0] (RW)
+ *
+ * When this field is set, it clears the ETHEREN field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_RESET field. */
+#define ENET_RD_ECR_RESET(base) ((ENET_ECR_REG(base) & ENET_ECR_RESET_MASK) >> ENET_ECR_RESET_SHIFT)
+#define ENET_BRD_ECR_RESET(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_RESET_SHIFT))
+
+/*! @brief Set the RESET field to a new value. */
+#define ENET_WR_ECR_RESET(base, value) (ENET_RMW_ECR(base, ENET_ECR_RESET_MASK, ENET_ECR_RESET(value)))
+#define ENET_BWR_ECR_RESET(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_RESET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field ETHEREN[1] (RW)
+ *
+ * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
+ * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
+ * descriptor, and FIFO control logic are reset, including the buffer descriptor and
+ * FIFO pointers. Hardware clears this field under the following conditions: RESET
+ * is set by software An error condition causes the EBERR field to set. ETHEREN
+ * must be set at the very last step during ENET
+ * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
+ * is cleared to 0 by software then then next time ETHEREN is set, the EIR
+ * interrupts must cleared to 0 due to previous pending interrupts.
+ *
+ * Values:
+ * - 0b0 - Reception immediately stops and transmission stops after a bad CRC is
+ *     appended to any currently transmitted frame.
+ * - 0b1 - MAC is enabled, and reception and transmission are possible.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_ETHEREN field. */
+#define ENET_RD_ECR_ETHEREN(base) ((ENET_ECR_REG(base) & ENET_ECR_ETHEREN_MASK) >> ENET_ECR_ETHEREN_SHIFT)
+#define ENET_BRD_ECR_ETHEREN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_ETHEREN_SHIFT))
+
+/*! @brief Set the ETHEREN field to a new value. */
+#define ENET_WR_ECR_ETHEREN(base, value) (ENET_RMW_ECR(base, ENET_ECR_ETHEREN_MASK, ENET_ECR_ETHEREN(value)))
+#define ENET_BWR_ECR_ETHEREN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_ETHEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field MAGICEN[2] (RW)
+ *
+ * Enables/disables magic packet detection. MAGICEN is relevant only if the
+ * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
+ * sleep mode and magic packet detection.
+ *
+ * Values:
+ * - 0b0 - Magic detection logic disabled.
+ * - 0b1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a
+ *     frame is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_MAGICEN field. */
+#define ENET_RD_ECR_MAGICEN(base) ((ENET_ECR_REG(base) & ENET_ECR_MAGICEN_MASK) >> ENET_ECR_MAGICEN_SHIFT)
+#define ENET_BRD_ECR_MAGICEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_MAGICEN_SHIFT))
+
+/*! @brief Set the MAGICEN field to a new value. */
+#define ENET_WR_ECR_MAGICEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_MAGICEN_MASK, ENET_ECR_MAGICEN(value)))
+#define ENET_BWR_ECR_MAGICEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_MAGICEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field SLEEP[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operating mode.
+ * - 0b1 - Sleep mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_SLEEP field. */
+#define ENET_RD_ECR_SLEEP(base) ((ENET_ECR_REG(base) & ENET_ECR_SLEEP_MASK) >> ENET_ECR_SLEEP_SHIFT)
+#define ENET_BRD_ECR_SLEEP(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_SLEEP_SHIFT))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define ENET_WR_ECR_SLEEP(base, value) (ENET_RMW_ECR(base, ENET_ECR_SLEEP_MASK, ENET_ECR_SLEEP(value)))
+#define ENET_BWR_ECR_SLEEP(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_SLEEP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field EN1588[4] (RW)
+ *
+ * Enables enhanced functionality of the MAC.
+ *
+ * Values:
+ * - 0b0 - Legacy FEC buffer descriptors and functions enabled.
+ * - 0b1 - Enhanced frame time-stamping functions enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_EN1588 field. */
+#define ENET_RD_ECR_EN1588(base) ((ENET_ECR_REG(base) & ENET_ECR_EN1588_MASK) >> ENET_ECR_EN1588_SHIFT)
+#define ENET_BRD_ECR_EN1588(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_EN1588_SHIFT))
+
+/*! @brief Set the EN1588 field to a new value. */
+#define ENET_WR_ECR_EN1588(base, value) (ENET_RMW_ECR(base, ENET_ECR_EN1588_MASK, ENET_ECR_EN1588(value)))
+#define ENET_BWR_ECR_EN1588(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_EN1588_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field DBGEN[6] (RW)
+ *
+ * Enables the MAC to enter hardware freeze mode when the device enters debug
+ * mode.
+ *
+ * Values:
+ * - 0b0 - MAC continues operation in debug mode.
+ * - 0b1 - MAC enters hardware freeze mode when the processor is in debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_DBGEN field. */
+#define ENET_RD_ECR_DBGEN(base) ((ENET_ECR_REG(base) & ENET_ECR_DBGEN_MASK) >> ENET_ECR_DBGEN_SHIFT)
+#define ENET_BRD_ECR_DBGEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBGEN_SHIFT))
+
+/*! @brief Set the DBGEN field to a new value. */
+#define ENET_WR_ECR_DBGEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_DBGEN_MASK, ENET_ECR_DBGEN(value)))
+#define ENET_BWR_ECR_DBGEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field STOPEN[7] (RW)
+ *
+ * Controls device behavior in doze mode. In doze mode, if this field is set
+ * then all the clocks of the ENET assembly are disabled, except the RMII /MII
+ * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
+ * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
+ * can still wake the system after receiving a magic packet in stop mode. MAGICEN
+ * must be set prior to entering sleep/stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_STOPEN field. */
+#define ENET_RD_ECR_STOPEN(base) ((ENET_ECR_REG(base) & ENET_ECR_STOPEN_MASK) >> ENET_ECR_STOPEN_SHIFT)
+#define ENET_BRD_ECR_STOPEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_STOPEN_SHIFT))
+
+/*! @brief Set the STOPEN field to a new value. */
+#define ENET_WR_ECR_STOPEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_STOPEN_MASK, ENET_ECR_STOPEN(value)))
+#define ENET_BWR_ECR_STOPEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_STOPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field DBSWP[8] (RW)
+ *
+ * Swaps the byte locations of the buffer descriptors. This field must be
+ * written to 1 after reset.
+ *
+ * Values:
+ * - 0b0 - The buffer descriptor bytes are not swapped to support big-endian
+ *     devices.
+ * - 0b1 - The buffer descriptor bytes are swapped to support little-endian
+ *     devices.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_DBSWP field. */
+#define ENET_RD_ECR_DBSWP(base) ((ENET_ECR_REG(base) & ENET_ECR_DBSWP_MASK) >> ENET_ECR_DBSWP_SHIFT)
+#define ENET_BRD_ECR_DBSWP(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBSWP_SHIFT))
+
+/*! @brief Set the DBSWP field to a new value. */
+#define ENET_WR_ECR_DBSWP(base, value) (ENET_RMW_ECR(base, ENET_ECR_DBSWP_MASK, ENET_ECR_DBSWP(value)))
+#define ENET_BWR_ECR_DBSWP(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBSWP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MMFR - MII Management Frame Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MMFR - MII Management Frame Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Writing to MMFR triggers a management frame transaction to the PHY device
+ * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
+ * during a write to MMFR, an MII frame is generated with the data previously written
+ * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
+ * MSCR is currently zero. If the MMFR register is written while frame generation is
+ * in progress, the frame contents are altered. Software must use the EIR[MII]
+ * interrupt indication to avoid writing to the MMFR register while frame
+ * generation is in progress.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MMFR register
+ */
+/*@{*/
+#define ENET_RD_MMFR(base)       (ENET_MMFR_REG(base))
+#define ENET_WR_MMFR(base, value) (ENET_MMFR_REG(base) = (value))
+#define ENET_RMW_MMFR(base, mask, value) (ENET_WR_MMFR(base, (ENET_RD_MMFR(base) & ~(mask)) | (value)))
+#define ENET_SET_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) |  (value)))
+#define ENET_CLR_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) & ~(value)))
+#define ENET_TOG_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MMFR bitfields
+ */
+
+/*!
+ * @name Register ENET_MMFR, field DATA[15:0] (RW)
+ *
+ * This is the field for data to be written to or read from the PHY register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_DATA field. */
+#define ENET_RD_MMFR_DATA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT)
+#define ENET_BRD_MMFR_DATA(base) (ENET_RD_MMFR_DATA(base))
+
+/*! @brief Set the DATA field to a new value. */
+#define ENET_WR_MMFR_DATA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_DATA_MASK, ENET_MMFR_DATA(value)))
+#define ENET_BWR_MMFR_DATA(base, value) (ENET_WR_MMFR_DATA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field TA[17:16] (RW)
+ *
+ * This field must be programmed to 10 to generate a valid MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_TA field. */
+#define ENET_RD_MMFR_TA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_TA_MASK) >> ENET_MMFR_TA_SHIFT)
+#define ENET_BRD_MMFR_TA(base) (ENET_RD_MMFR_TA(base))
+
+/*! @brief Set the TA field to a new value. */
+#define ENET_WR_MMFR_TA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_TA_MASK, ENET_MMFR_TA(value)))
+#define ENET_BWR_MMFR_TA(base, value) (ENET_WR_MMFR_TA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field RA[22:18] (RW)
+ *
+ * Specifies one of up to 32 registers within the specified PHY device.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_RA field. */
+#define ENET_RD_MMFR_RA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_RA_MASK) >> ENET_MMFR_RA_SHIFT)
+#define ENET_BRD_MMFR_RA(base) (ENET_RD_MMFR_RA(base))
+
+/*! @brief Set the RA field to a new value. */
+#define ENET_WR_MMFR_RA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_RA_MASK, ENET_MMFR_RA(value)))
+#define ENET_BWR_MMFR_RA(base, value) (ENET_WR_MMFR_RA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field PA[27:23] (RW)
+ *
+ * Specifies one of up to 32 attached PHY devices.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_PA field. */
+#define ENET_RD_MMFR_PA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_PA_MASK) >> ENET_MMFR_PA_SHIFT)
+#define ENET_BRD_MMFR_PA(base) (ENET_RD_MMFR_PA(base))
+
+/*! @brief Set the PA field to a new value. */
+#define ENET_WR_MMFR_PA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_PA_MASK, ENET_MMFR_PA(value)))
+#define ENET_BWR_MMFR_PA(base, value) (ENET_WR_MMFR_PA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field OP[29:28] (RW)
+ *
+ * Determines the frame operation.
+ *
+ * Values:
+ * - 0b00 - Write frame operation, but not MII compliant.
+ * - 0b01 - Write frame operation for a valid MII management frame.
+ * - 0b10 - Read frame operation for a valid MII management frame.
+ * - 0b11 - Read frame operation, but not MII compliant.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_OP field. */
+#define ENET_RD_MMFR_OP(base) ((ENET_MMFR_REG(base) & ENET_MMFR_OP_MASK) >> ENET_MMFR_OP_SHIFT)
+#define ENET_BRD_MMFR_OP(base) (ENET_RD_MMFR_OP(base))
+
+/*! @brief Set the OP field to a new value. */
+#define ENET_WR_MMFR_OP(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_OP_MASK, ENET_MMFR_OP(value)))
+#define ENET_BWR_MMFR_OP(base, value) (ENET_WR_MMFR_OP(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field ST[31:30] (RW)
+ *
+ * These fields must be programmed to 01 for a valid MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_ST field. */
+#define ENET_RD_MMFR_ST(base) ((ENET_MMFR_REG(base) & ENET_MMFR_ST_MASK) >> ENET_MMFR_ST_SHIFT)
+#define ENET_BRD_MMFR_ST(base) (ENET_RD_MMFR_ST(base))
+
+/*! @brief Set the ST field to a new value. */
+#define ENET_WR_MMFR_ST(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_ST_MASK, ENET_MMFR_ST(value)))
+#define ENET_BWR_MMFR_ST(base, value) (ENET_WR_MMFR_ST(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MSCR - MII Speed Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MSCR - MII Speed Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * MSCR provides control of the MII clock (MDC pin) frequency and allows a
+ * preamble drop on the MII management frame. The MII_SPEED field must be programmed
+ * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
+ * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
+ * a non-zero value to source a read or write management frame. After the
+ * management frame is complete, the MSCR register may optionally be cleared to turn
+ * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
+ * changes during operation. This change takes effect following a rising or falling
+ * edge of MDC. If the internal module clock is 25 MHz, programming this register
+ * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
+ * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
+ * MII_SPEED as a function of internal module clock frequency. Programming Examples
+ * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
+ * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
+ * 0xD 2.36 MHz
+ */
+/*!
+ * @name Constants and macros for entire ENET_MSCR register
+ */
+/*@{*/
+#define ENET_RD_MSCR(base)       (ENET_MSCR_REG(base))
+#define ENET_WR_MSCR(base, value) (ENET_MSCR_REG(base) = (value))
+#define ENET_RMW_MSCR(base, mask, value) (ENET_WR_MSCR(base, (ENET_RD_MSCR(base) & ~(mask)) | (value)))
+#define ENET_SET_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) |  (value)))
+#define ENET_CLR_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) & ~(value)))
+#define ENET_TOG_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MSCR bitfields
+ */
+
+/*!
+ * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
+ *
+ * Controls the frequency of the MII management interface clock (MDC) relative
+ * to the internal module clock. A value of 0 in this field turns off MDC and
+ * leaves it in low voltage state. Any non-zero value results in the MDC frequency
+ * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_MII_SPEED field. */
+#define ENET_RD_MSCR_MII_SPEED(base) ((ENET_MSCR_REG(base) & ENET_MSCR_MII_SPEED_MASK) >> ENET_MSCR_MII_SPEED_SHIFT)
+#define ENET_BRD_MSCR_MII_SPEED(base) (ENET_RD_MSCR_MII_SPEED(base))
+
+/*! @brief Set the MII_SPEED field to a new value. */
+#define ENET_WR_MSCR_MII_SPEED(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_MII_SPEED_MASK, ENET_MSCR_MII_SPEED(value)))
+#define ENET_BWR_MSCR_MII_SPEED(base, value) (ENET_WR_MSCR_MII_SPEED(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
+ *
+ * Enables/disables prepending a preamble to the MII management frame. The MII
+ * standard allows the preamble to be dropped if the attached PHY devices do not
+ * require it.
+ *
+ * Values:
+ * - 0b0 - Preamble enabled.
+ * - 0b1 - Preamble (32 ones) is not prepended to the MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_DIS_PRE field. */
+#define ENET_RD_MSCR_DIS_PRE(base) ((ENET_MSCR_REG(base) & ENET_MSCR_DIS_PRE_MASK) >> ENET_MSCR_DIS_PRE_SHIFT)
+#define ENET_BRD_MSCR_DIS_PRE(base) (BITBAND_ACCESS32(&ENET_MSCR_REG(base), ENET_MSCR_DIS_PRE_SHIFT))
+
+/*! @brief Set the DIS_PRE field to a new value. */
+#define ENET_WR_MSCR_DIS_PRE(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_DIS_PRE_MASK, ENET_MSCR_DIS_PRE(value)))
+#define ENET_BWR_MSCR_DIS_PRE(base, value) (BITBAND_ACCESS32(&ENET_MSCR_REG(base), ENET_MSCR_DIS_PRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
+ *
+ * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
+ * output. Depending on the host bus frequency, the setting may need to be
+ * increased.
+ *
+ * Values:
+ * - 0b000 - 1 internal module clock cycle
+ * - 0b001 - 2 internal module clock cycles
+ * - 0b010 - 3 internal module clock cycles
+ * - 0b111 - 8 internal module clock cycles
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_HOLDTIME field. */
+#define ENET_RD_MSCR_HOLDTIME(base) ((ENET_MSCR_REG(base) & ENET_MSCR_HOLDTIME_MASK) >> ENET_MSCR_HOLDTIME_SHIFT)
+#define ENET_BRD_MSCR_HOLDTIME(base) (ENET_RD_MSCR_HOLDTIME(base))
+
+/*! @brief Set the HOLDTIME field to a new value. */
+#define ENET_WR_MSCR_HOLDTIME(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_HOLDTIME_MASK, ENET_MSCR_HOLDTIME(value)))
+#define ENET_BWR_MSCR_HOLDTIME(base, value) (ENET_WR_MSCR_HOLDTIME(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MIBC - MIB Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MIBC - MIB Control Register (RW)
+ *
+ * Reset value: 0xC0000000U
+ *
+ * MIBC is a read/write register controlling and observing the state of the MIB
+ * block. Access this register to disable the MIB block operation or clear the
+ * MIB counters. The MIB_DIS field resets to 1.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MIBC register
+ */
+/*@{*/
+#define ENET_RD_MIBC(base)       (ENET_MIBC_REG(base))
+#define ENET_WR_MIBC(base, value) (ENET_MIBC_REG(base) = (value))
+#define ENET_RMW_MIBC(base, mask, value) (ENET_WR_MIBC(base, (ENET_RD_MIBC(base) & ~(mask)) | (value)))
+#define ENET_SET_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) |  (value)))
+#define ENET_CLR_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) & ~(value)))
+#define ENET_TOG_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MIBC bitfields
+ */
+
+/*!
+ * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
+ *
+ * If set, all statistics counters are reset to 0. This field is not
+ * self-clearing. To clear the MIB counters set and then clear the field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_CLEAR field. */
+#define ENET_RD_MIBC_MIB_CLEAR(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_CLEAR_MASK) >> ENET_MIBC_MIB_CLEAR_SHIFT)
+#define ENET_BRD_MIBC_MIB_CLEAR(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_CLEAR_SHIFT))
+
+/*! @brief Set the MIB_CLEAR field to a new value. */
+#define ENET_WR_MIBC_MIB_CLEAR(base, value) (ENET_RMW_MIBC(base, ENET_MIBC_MIB_CLEAR_MASK, ENET_MIBC_MIB_CLEAR(value)))
+#define ENET_BWR_MIBC_MIB_CLEAR(base, value) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_CLEAR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
+ *
+ * If this status field is set, the MIB block is not currently updating any MIB
+ * counters.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_IDLE field. */
+#define ENET_RD_MIBC_MIB_IDLE(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_IDLE_MASK) >> ENET_MIBC_MIB_IDLE_SHIFT)
+#define ENET_BRD_MIBC_MIB_IDLE(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
+ *
+ * If this control field is set, the MIB logic halts and does not update any MIB
+ * counters.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_DIS field. */
+#define ENET_RD_MIBC_MIB_DIS(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_DIS_MASK) >> ENET_MIBC_MIB_DIS_SHIFT)
+#define ENET_BRD_MIBC_MIB_DIS(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_DIS_SHIFT))
+
+/*! @brief Set the MIB_DIS field to a new value. */
+#define ENET_WR_MIBC_MIB_DIS(base, value) (ENET_RMW_MIBC(base, ENET_MIBC_MIB_DIS_MASK, ENET_MIBC_MIB_DIS(value)))
+#define ENET_BWR_MIBC_MIB_DIS(base, value) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_DIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RCR - Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RCR - Receive Control Register (RW)
+ *
+ * Reset value: 0x05EE0001U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RCR register
+ */
+/*@{*/
+#define ENET_RD_RCR(base)        (ENET_RCR_REG(base))
+#define ENET_WR_RCR(base, value) (ENET_RCR_REG(base) = (value))
+#define ENET_RMW_RCR(base, mask, value) (ENET_WR_RCR(base, (ENET_RD_RCR(base) & ~(mask)) | (value)))
+#define ENET_SET_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) |  (value)))
+#define ENET_CLR_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) & ~(value)))
+#define ENET_TOG_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RCR bitfields
+ */
+
+/*!
+ * @name Register ENET_RCR, field LOOP[0] (RW)
+ *
+ * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
+ * RMII_MODE must be written to 0.
+ *
+ * Values:
+ * - 0b0 - Loopback disabled.
+ * - 0b1 - Transmitted frames are looped back internal to the device and
+ *     transmit MII output signals are not asserted. DRT must be cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_LOOP field. */
+#define ENET_RD_RCR_LOOP(base) ((ENET_RCR_REG(base) & ENET_RCR_LOOP_MASK) >> ENET_RCR_LOOP_SHIFT)
+#define ENET_BRD_RCR_LOOP(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_LOOP_SHIFT))
+
+/*! @brief Set the LOOP field to a new value. */
+#define ENET_WR_RCR_LOOP(base, value) (ENET_RMW_RCR(base, ENET_RCR_LOOP_MASK, ENET_RCR_LOOP(value)))
+#define ENET_BWR_RCR_LOOP(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_LOOP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field DRT[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Receive path operates independently of transmit. Used for full-duplex
+ *     or to monitor transmit activity in half-duplex mode.
+ * - 0b1 - Disable reception of frames while transmitting. Normally used for
+ *     half-duplex mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_DRT field. */
+#define ENET_RD_RCR_DRT(base) ((ENET_RCR_REG(base) & ENET_RCR_DRT_MASK) >> ENET_RCR_DRT_SHIFT)
+#define ENET_BRD_RCR_DRT(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_DRT_SHIFT))
+
+/*! @brief Set the DRT field to a new value. */
+#define ENET_WR_RCR_DRT(base, value) (ENET_RMW_RCR(base, ENET_RCR_DRT_MASK, ENET_RCR_DRT(value)))
+#define ENET_BWR_RCR_DRT(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_DRT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field MII_MODE[2] (RW)
+ *
+ * This field must always be set.
+ *
+ * Values:
+ * - 0b0 - Reserved.
+ * - 0b1 - MII or RMII mode, as indicated by the RMII_MODE field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_MII_MODE field. */
+#define ENET_RD_RCR_MII_MODE(base) ((ENET_RCR_REG(base) & ENET_RCR_MII_MODE_MASK) >> ENET_RCR_MII_MODE_SHIFT)
+#define ENET_BRD_RCR_MII_MODE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_MII_MODE_SHIFT))
+
+/*! @brief Set the MII_MODE field to a new value. */
+#define ENET_WR_RCR_MII_MODE(base, value) (ENET_RMW_RCR(base, ENET_RCR_MII_MODE_MASK, ENET_RCR_MII_MODE(value)))
+#define ENET_BWR_RCR_MII_MODE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_MII_MODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PROM[3] (RW)
+ *
+ * All frames are accepted regardless of address matching.
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PROM field. */
+#define ENET_RD_RCR_PROM(base) ((ENET_RCR_REG(base) & ENET_RCR_PROM_MASK) >> ENET_RCR_PROM_SHIFT)
+#define ENET_BRD_RCR_PROM(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PROM_SHIFT))
+
+/*! @brief Set the PROM field to a new value. */
+#define ENET_WR_RCR_PROM(base, value) (ENET_RMW_RCR(base, ENET_RCR_PROM_MASK, ENET_RCR_PROM(value)))
+#define ENET_BWR_RCR_PROM(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PROM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field BC_REJ[4] (RW)
+ *
+ * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
+ * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
+ * broadcast DA are accepted and the MISS (M) is set in the receive buffer
+ * descriptor.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_BC_REJ field. */
+#define ENET_RD_RCR_BC_REJ(base) ((ENET_RCR_REG(base) & ENET_RCR_BC_REJ_MASK) >> ENET_RCR_BC_REJ_SHIFT)
+#define ENET_BRD_RCR_BC_REJ(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_BC_REJ_SHIFT))
+
+/*! @brief Set the BC_REJ field to a new value. */
+#define ENET_WR_RCR_BC_REJ(base, value) (ENET_RMW_RCR(base, ENET_RCR_BC_REJ_MASK, ENET_RCR_BC_REJ(value)))
+#define ENET_BWR_RCR_BC_REJ(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_BC_REJ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field FCE[5] (RW)
+ *
+ * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
+ * transmitter stops transmitting data frames for a given duration.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_FCE field. */
+#define ENET_RD_RCR_FCE(base) ((ENET_RCR_REG(base) & ENET_RCR_FCE_MASK) >> ENET_RCR_FCE_SHIFT)
+#define ENET_BRD_RCR_FCE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_FCE_SHIFT))
+
+/*! @brief Set the FCE field to a new value. */
+#define ENET_WR_RCR_FCE(base, value) (ENET_RMW_RCR(base, ENET_RCR_FCE_MASK, ENET_RCR_FCE(value)))
+#define ENET_BWR_RCR_FCE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_FCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field RMII_MODE[8] (RW)
+ *
+ * Specifies whether the MAC is configured for MII mode or RMII operation .
+ *
+ * Values:
+ * - 0b0 - MAC configured for MII mode.
+ * - 0b1 - MAC configured for RMII operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_RMII_MODE field. */
+#define ENET_RD_RCR_RMII_MODE(base) ((ENET_RCR_REG(base) & ENET_RCR_RMII_MODE_MASK) >> ENET_RCR_RMII_MODE_SHIFT)
+#define ENET_BRD_RCR_RMII_MODE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_MODE_SHIFT))
+
+/*! @brief Set the RMII_MODE field to a new value. */
+#define ENET_WR_RCR_RMII_MODE(base, value) (ENET_RMW_RCR(base, ENET_RCR_RMII_MODE_MASK, ENET_RCR_RMII_MODE(value)))
+#define ENET_BWR_RCR_RMII_MODE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_MODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field RMII_10T[9] (RW)
+ *
+ * Enables 10-Mbps mode of the RMII .
+ *
+ * Values:
+ * - 0b0 - 100 Mbps operation.
+ * - 0b1 - 10 Mbps operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_RMII_10T field. */
+#define ENET_RD_RCR_RMII_10T(base) ((ENET_RCR_REG(base) & ENET_RCR_RMII_10T_MASK) >> ENET_RCR_RMII_10T_SHIFT)
+#define ENET_BRD_RCR_RMII_10T(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_10T_SHIFT))
+
+/*! @brief Set the RMII_10T field to a new value. */
+#define ENET_WR_RCR_RMII_10T(base, value) (ENET_RMW_RCR(base, ENET_RCR_RMII_10T_MASK, ENET_RCR_RMII_10T(value)))
+#define ENET_BWR_RCR_RMII_10T(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_10T_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PADEN[12] (RW)
+ *
+ * Specifies whether the MAC removes padding from received frames.
+ *
+ * Values:
+ * - 0b0 - No padding is removed on receive by the MAC.
+ * - 0b1 - Padding is removed from received frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PADEN field. */
+#define ENET_RD_RCR_PADEN(base) ((ENET_RCR_REG(base) & ENET_RCR_PADEN_MASK) >> ENET_RCR_PADEN_SHIFT)
+#define ENET_BRD_RCR_PADEN(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PADEN_SHIFT))
+
+/*! @brief Set the PADEN field to a new value. */
+#define ENET_WR_RCR_PADEN(base, value) (ENET_RMW_RCR(base, ENET_RCR_PADEN_MASK, ENET_RCR_PADEN(value)))
+#define ENET_BWR_RCR_PADEN(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PADEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PAUFWD[13] (RW)
+ *
+ * Specifies whether pause frames are terminated or forwarded.
+ *
+ * Values:
+ * - 0b0 - Pause frames are terminated and discarded in the MAC.
+ * - 0b1 - Pause frames are forwarded to the user application.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PAUFWD field. */
+#define ENET_RD_RCR_PAUFWD(base) ((ENET_RCR_REG(base) & ENET_RCR_PAUFWD_MASK) >> ENET_RCR_PAUFWD_SHIFT)
+#define ENET_BRD_RCR_PAUFWD(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PAUFWD_SHIFT))
+
+/*! @brief Set the PAUFWD field to a new value. */
+#define ENET_WR_RCR_PAUFWD(base, value) (ENET_RMW_RCR(base, ENET_RCR_PAUFWD_MASK, ENET_RCR_PAUFWD(value)))
+#define ENET_BWR_RCR_PAUFWD(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PAUFWD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field CRCFWD[14] (RW)
+ *
+ * Specifies whether the CRC field of received frames is transmitted or
+ * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
+ * field is checked and always terminated and removed.
+ *
+ * Values:
+ * - 0b0 - The CRC field of received frames is transmitted to the user
+ *     application.
+ * - 0b1 - The CRC field is stripped from the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_CRCFWD field. */
+#define ENET_RD_RCR_CRCFWD(base) ((ENET_RCR_REG(base) & ENET_RCR_CRCFWD_MASK) >> ENET_RCR_CRCFWD_SHIFT)
+#define ENET_BRD_RCR_CRCFWD(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CRCFWD_SHIFT))
+
+/*! @brief Set the CRCFWD field to a new value. */
+#define ENET_WR_RCR_CRCFWD(base, value) (ENET_RMW_RCR(base, ENET_RCR_CRCFWD_MASK, ENET_RCR_CRCFWD(value)))
+#define ENET_BWR_RCR_CRCFWD(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CRCFWD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field CFEN[15] (RW)
+ *
+ * Enables/disables the MAC control frame.
+ *
+ * Values:
+ * - 0b0 - MAC control frames with any opcode other than 0x0001 (pause frame)
+ *     are accepted and forwarded to the client interface.
+ * - 0b1 - MAC control frames with any opcode other than 0x0001 (pause frame)
+ *     are silently discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_CFEN field. */
+#define ENET_RD_RCR_CFEN(base) ((ENET_RCR_REG(base) & ENET_RCR_CFEN_MASK) >> ENET_RCR_CFEN_SHIFT)
+#define ENET_BRD_RCR_CFEN(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CFEN_SHIFT))
+
+/*! @brief Set the CFEN field to a new value. */
+#define ENET_WR_RCR_CFEN(base, value) (ENET_RMW_RCR(base, ENET_RCR_CFEN_MASK, ENET_RCR_CFEN(value)))
+#define ENET_BWR_RCR_CFEN(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
+ *
+ * Resets to decimal 1518. Length is measured starting at DA and includes the
+ * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
+ * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
+ * to occur and set the LG field in the end of frame receive buffer descriptor.
+ * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
+ * supported.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_MAX_FL field. */
+#define ENET_RD_RCR_MAX_FL(base) ((ENET_RCR_REG(base) & ENET_RCR_MAX_FL_MASK) >> ENET_RCR_MAX_FL_SHIFT)
+#define ENET_BRD_RCR_MAX_FL(base) (ENET_RD_RCR_MAX_FL(base))
+
+/*! @brief Set the MAX_FL field to a new value. */
+#define ENET_WR_RCR_MAX_FL(base, value) (ENET_RMW_RCR(base, ENET_RCR_MAX_FL_MASK, ENET_RCR_MAX_FL(value)))
+#define ENET_BWR_RCR_MAX_FL(base, value) (ENET_WR_RCR_MAX_FL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field NLC[30] (RW)
+ *
+ * Enables/disables a payload length check.
+ *
+ * Values:
+ * - 0b0 - The payload length check is disabled.
+ * - 0b1 - The core checks the frame's payload length with the frame length/type
+ *     field. Errors are indicated in the EIR[PLC] field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_NLC field. */
+#define ENET_RD_RCR_NLC(base) ((ENET_RCR_REG(base) & ENET_RCR_NLC_MASK) >> ENET_RCR_NLC_SHIFT)
+#define ENET_BRD_RCR_NLC(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_NLC_SHIFT))
+
+/*! @brief Set the NLC field to a new value. */
+#define ENET_WR_RCR_NLC(base, value) (ENET_RMW_RCR(base, ENET_RCR_NLC_MASK, ENET_RCR_NLC(value)))
+#define ENET_BWR_RCR_NLC(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_NLC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field GRS[31] (RO)
+ *
+ * Read-only status indicating that the MAC receive datapath is stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_GRS field. */
+#define ENET_RD_RCR_GRS(base) ((ENET_RCR_REG(base) & ENET_RCR_GRS_MASK) >> ENET_RCR_GRS_SHIFT)
+#define ENET_BRD_RCR_GRS(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_GRS_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCR - Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCR - Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR is read/write and configures the transmit block. This register is cleared
+ * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCR register
+ */
+/*@{*/
+#define ENET_RD_TCR(base)        (ENET_TCR_REG(base))
+#define ENET_WR_TCR(base, value) (ENET_TCR_REG(base) = (value))
+#define ENET_RMW_TCR(base, mask, value) (ENET_WR_TCR(base, (ENET_RD_TCR(base) & ~(mask)) | (value)))
+#define ENET_SET_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) |  (value)))
+#define ENET_CLR_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) & ~(value)))
+#define ENET_TOG_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TCR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCR, field GTS[0] (RW)
+ *
+ * When this field is set, MAC stops transmission after any frame currently
+ * transmitted is complete and EIR[GRA] is set. If frame transmission is not
+ * currently underway, the GRA interrupt is asserted immediately. After transmission
+ * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
+ * transmitted. If an early collision occurs during transmission when GTS is set,
+ * transmission stops after the collision. The frame is transmitted again after GTS is
+ * cleared. There may be old frames in the transmit FIFO that transmit when GTS
+ * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_GTS field. */
+#define ENET_RD_TCR_GTS(base) ((ENET_TCR_REG(base) & ENET_TCR_GTS_MASK) >> ENET_TCR_GTS_SHIFT)
+#define ENET_BRD_TCR_GTS(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_GTS_SHIFT))
+
+/*! @brief Set the GTS field to a new value. */
+#define ENET_WR_TCR_GTS(base, value) (ENET_RMW_TCR(base, ENET_TCR_GTS_MASK, ENET_TCR_GTS(value)))
+#define ENET_BWR_TCR_GTS(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_GTS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field FDEN[2] (RW)
+ *
+ * If this field is set, frames transmit independent of carrier sense and
+ * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_FDEN field. */
+#define ENET_RD_TCR_FDEN(base) ((ENET_TCR_REG(base) & ENET_TCR_FDEN_MASK) >> ENET_TCR_FDEN_SHIFT)
+#define ENET_BRD_TCR_FDEN(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_FDEN_SHIFT))
+
+/*! @brief Set the FDEN field to a new value. */
+#define ENET_WR_TCR_FDEN(base, value) (ENET_RMW_TCR(base, ENET_TCR_FDEN_MASK, ENET_TCR_FDEN(value)))
+#define ENET_BWR_TCR_FDEN(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_FDEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
+ *
+ * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
+ * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
+ * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
+ * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
+ * the MAC may continue transmitting a MAC control PAUSE frame.
+ *
+ * Values:
+ * - 0b0 - No PAUSE frame transmitted.
+ * - 0b1 - The MAC stops transmission of data frames after the current
+ *     transmission is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_TFC_PAUSE field. */
+#define ENET_RD_TCR_TFC_PAUSE(base) ((ENET_TCR_REG(base) & ENET_TCR_TFC_PAUSE_MASK) >> ENET_TCR_TFC_PAUSE_SHIFT)
+#define ENET_BRD_TCR_TFC_PAUSE(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_TFC_PAUSE_SHIFT))
+
+/*! @brief Set the TFC_PAUSE field to a new value. */
+#define ENET_WR_TCR_TFC_PAUSE(base, value) (ENET_RMW_TCR(base, ENET_TCR_TFC_PAUSE_MASK, ENET_TCR_TFC_PAUSE(value)))
+#define ENET_BWR_TCR_TFC_PAUSE(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_TFC_PAUSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
+ *
+ * This status field is set when a full-duplex flow control pause frame is
+ * received and the transmitter pauses for the duration defined in this pause frame.
+ * This field automatically clears when the pause duration is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_RFC_PAUSE field. */
+#define ENET_RD_TCR_RFC_PAUSE(base) ((ENET_TCR_REG(base) & ENET_TCR_RFC_PAUSE_MASK) >> ENET_TCR_RFC_PAUSE_SHIFT)
+#define ENET_BRD_TCR_RFC_PAUSE(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_RFC_PAUSE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
+ *
+ * If ADDINS is set, indicates the MAC address that overwrites the source MAC
+ * address.
+ *
+ * Values:
+ * - 0b000 - Node MAC address programmed on PADDR1/2 registers.
+ * - 0b100 - Reserved.
+ * - 0b101 - Reserved.
+ * - 0b110 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_ADDSEL field. */
+#define ENET_RD_TCR_ADDSEL(base) ((ENET_TCR_REG(base) & ENET_TCR_ADDSEL_MASK) >> ENET_TCR_ADDSEL_SHIFT)
+#define ENET_BRD_TCR_ADDSEL(base) (ENET_RD_TCR_ADDSEL(base))
+
+/*! @brief Set the ADDSEL field to a new value. */
+#define ENET_WR_TCR_ADDSEL(base, value) (ENET_RMW_TCR(base, ENET_TCR_ADDSEL_MASK, ENET_TCR_ADDSEL(value)))
+#define ENET_BWR_TCR_ADDSEL(base, value) (ENET_WR_TCR_ADDSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field ADDINS[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The source MAC address is not modified by the MAC.
+ * - 0b1 - The MAC overwrites the source MAC address with the programmed MAC
+ *     address according to ADDSEL.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_ADDINS field. */
+#define ENET_RD_TCR_ADDINS(base) ((ENET_TCR_REG(base) & ENET_TCR_ADDINS_MASK) >> ENET_TCR_ADDINS_SHIFT)
+#define ENET_BRD_TCR_ADDINS(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_ADDINS_SHIFT))
+
+/*! @brief Set the ADDINS field to a new value. */
+#define ENET_WR_TCR_ADDINS(base, value) (ENET_RMW_TCR(base, ENET_TCR_ADDINS_MASK, ENET_TCR_ADDINS(value)))
+#define ENET_BWR_TCR_ADDINS(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_ADDINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field CRCFWD[9] (RW)
+ *
+ * Values:
+ * - 0b0 - TxBD[TC] controls whether the frame has a CRC from the application.
+ * - 0b1 - The transmitter does not append any CRC to transmitted frames, as it
+ *     is expecting a frame with CRC from the application.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_CRCFWD field. */
+#define ENET_RD_TCR_CRCFWD(base) ((ENET_TCR_REG(base) & ENET_TCR_CRCFWD_MASK) >> ENET_TCR_CRCFWD_SHIFT)
+#define ENET_BRD_TCR_CRCFWD(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_CRCFWD_SHIFT))
+
+/*! @brief Set the CRCFWD field to a new value. */
+#define ENET_WR_TCR_CRCFWD(base, value) (ENET_RMW_TCR(base, ENET_TCR_CRCFWD_MASK, ENET_TCR_CRCFWD(value)))
+#define ENET_BWR_TCR_CRCFWD(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_CRCFWD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_PALR - Physical Address Lower Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_PALR - Physical Address Lower Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
+ * in the address recognition process to compare with the destination address
+ * (DA) field of receive frames with an individual DA. In addition, this register
+ * is used in bytes 0 through 3 of the six-byte source address field when
+ * transmitting PAUSE frames. This register is not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_PALR register
+ */
+/*@{*/
+#define ENET_RD_PALR(base)       (ENET_PALR_REG(base))
+#define ENET_WR_PALR(base, value) (ENET_PALR_REG(base) = (value))
+#define ENET_RMW_PALR(base, mask, value) (ENET_WR_PALR(base, (ENET_RD_PALR(base) & ~(mask)) | (value)))
+#define ENET_SET_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) |  (value)))
+#define ENET_CLR_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) & ~(value)))
+#define ENET_TOG_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_PAUR - Physical Address Upper Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_PAUR - Physical Address Upper Register (RW)
+ *
+ * Reset value: 0x00008808U
+ *
+ * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
+ * the address recognition process to compare with the destination address (DA)
+ * field of receive frames with an individual DA. In addition, this register is
+ * used in bytes 4 and 5 of the six-byte source address field when transmitting
+ * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
+ * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
+ * you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_PAUR register
+ */
+/*@{*/
+#define ENET_RD_PAUR(base)       (ENET_PAUR_REG(base))
+#define ENET_WR_PAUR(base, value) (ENET_PAUR_REG(base) = (value))
+#define ENET_RMW_PAUR(base, mask, value) (ENET_WR_PAUR(base, (ENET_RD_PAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) |  (value)))
+#define ENET_CLR_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) & ~(value)))
+#define ENET_TOG_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_PAUR bitfields
+ */
+
+/*!
+ * @name Register ENET_PAUR, field TYPE[15:0] (RO)
+ *
+ * These fields have a constant value of 0x8808.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_PAUR_TYPE field. */
+#define ENET_RD_PAUR_TYPE(base) ((ENET_PAUR_REG(base) & ENET_PAUR_TYPE_MASK) >> ENET_PAUR_TYPE_SHIFT)
+#define ENET_BRD_PAUR_TYPE(base) (ENET_RD_PAUR_TYPE(base))
+/*@}*/
+
+/*!
+ * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
+ *
+ * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
+ * for exact match, and the source address field in PAUSE frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_PAUR_PADDR2 field. */
+#define ENET_RD_PAUR_PADDR2(base) ((ENET_PAUR_REG(base) & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT)
+#define ENET_BRD_PAUR_PADDR2(base) (ENET_RD_PAUR_PADDR2(base))
+
+/*! @brief Set the PADDR2 field to a new value. */
+#define ENET_WR_PAUR_PADDR2(base, value) (ENET_RMW_PAUR(base, ENET_PAUR_PADDR2_MASK, ENET_PAUR_PADDR2(value)))
+#define ENET_BWR_PAUR_PADDR2(base, value) (ENET_WR_PAUR_PADDR2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_OPD - Opcode/Pause Duration Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_OPD - Opcode/Pause Duration Register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * OPD is read/write accessible. This register contains the 16-bit opcode and
+ * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
+ * field is a constant value, 0x0001. When another node detects a PAUSE frame,
+ * that node pauses transmission for the duration specified in the pause duration
+ * field. The lower 16 bits of this register are not reset and you must initialize
+ * it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_OPD register
+ */
+/*@{*/
+#define ENET_RD_OPD(base)        (ENET_OPD_REG(base))
+#define ENET_WR_OPD(base, value) (ENET_OPD_REG(base) = (value))
+#define ENET_RMW_OPD(base, mask, value) (ENET_WR_OPD(base, (ENET_RD_OPD(base) & ~(mask)) | (value)))
+#define ENET_SET_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) |  (value)))
+#define ENET_CLR_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) & ~(value)))
+#define ENET_TOG_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_OPD bitfields
+ */
+
+/*!
+ * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
+ *
+ * Pause duration field used in PAUSE frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_OPD_PAUSE_DUR field. */
+#define ENET_RD_OPD_PAUSE_DUR(base) ((ENET_OPD_REG(base) & ENET_OPD_PAUSE_DUR_MASK) >> ENET_OPD_PAUSE_DUR_SHIFT)
+#define ENET_BRD_OPD_PAUSE_DUR(base) (ENET_RD_OPD_PAUSE_DUR(base))
+
+/*! @brief Set the PAUSE_DUR field to a new value. */
+#define ENET_WR_OPD_PAUSE_DUR(base, value) (ENET_RMW_OPD(base, ENET_OPD_PAUSE_DUR_MASK, ENET_OPD_PAUSE_DUR(value)))
+#define ENET_BWR_OPD_PAUSE_DUR(base, value) (ENET_WR_OPD_PAUSE_DUR(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_OPD, field OPCODE[31:16] (RO)
+ *
+ * These fields have a constant value of 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_OPD_OPCODE field. */
+#define ENET_RD_OPD_OPCODE(base) ((ENET_OPD_REG(base) & ENET_OPD_OPCODE_MASK) >> ENET_OPD_OPCODE_SHIFT)
+#define ENET_BRD_OPD_OPCODE(base) (ENET_RD_OPD_OPCODE(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IAUR - Descriptor Individual Upper Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IAUR - Descriptor Individual Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the destination address (DA) field of receive frames with an individual
+ * DA. This register is not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IAUR register
+ */
+/*@{*/
+#define ENET_RD_IAUR(base)       (ENET_IAUR_REG(base))
+#define ENET_WR_IAUR(base, value) (ENET_IAUR_REG(base) = (value))
+#define ENET_RMW_IAUR(base, mask, value) (ENET_WR_IAUR(base, (ENET_RD_IAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) |  (value)))
+#define ENET_CLR_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) & ~(value)))
+#define ENET_TOG_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IALR - Descriptor Individual Lower Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IALR - Descriptor Individual Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IALR contains the lower 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the DA field of receive frames with an individual DA. This register is
+ * not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IALR register
+ */
+/*@{*/
+#define ENET_RD_IALR(base)       (ENET_IALR_REG(base))
+#define ENET_WR_IALR(base, value) (ENET_IALR_REG(base) = (value))
+#define ENET_RMW_IALR(base, mask, value) (ENET_WR_IALR(base, (ENET_RD_IALR(base) & ~(mask)) | (value)))
+#define ENET_SET_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) |  (value)))
+#define ENET_CLR_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) & ~(value)))
+#define ENET_TOG_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_GAUR - Descriptor Group Upper Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_GAUR - Descriptor Group Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+/*!
+ * @name Constants and macros for entire ENET_GAUR register
+ */
+/*@{*/
+#define ENET_RD_GAUR(base)       (ENET_GAUR_REG(base))
+#define ENET_WR_GAUR(base, value) (ENET_GAUR_REG(base) = (value))
+#define ENET_RMW_GAUR(base, mask, value) (ENET_WR_GAUR(base, (ENET_RD_GAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) |  (value)))
+#define ENET_CLR_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) & ~(value)))
+#define ENET_TOG_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_GALR - Descriptor Group Lower Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_GALR - Descriptor Group Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GALR contains the lower 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+/*!
+ * @name Constants and macros for entire ENET_GALR register
+ */
+/*@{*/
+#define ENET_RD_GALR(base)       (ENET_GALR_REG(base))
+#define ENET_WR_GALR(base, value) (ENET_GALR_REG(base) = (value))
+#define ENET_RMW_GALR(base, mask, value) (ENET_WR_GALR(base, (ENET_RD_GALR(base) & ~(mask)) | (value)))
+#define ENET_SET_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) |  (value)))
+#define ENET_CLR_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) & ~(value)))
+#define ENET_TOG_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TFWR - Transmit FIFO Watermark Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TFWR - Transmit FIFO Watermark Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
+ * in the transmit FIFO before transmission of a frame can begin. This allows you
+ * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
+ * latency (TFWR = 11) due to contention for the system bus. Setting the
+ * watermark to a high value minimizes the risk of transmit FIFO underrun due to
+ * contention for the system bus. The byte counts associated with the TFWR field may need
+ * to be modified to match a given system requirement. For example, worst case
+ * bus access latency by the transmit data DMA channel. When the FIFO level
+ * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
+ * transmit control logic starts frame transmission even before the end-of-frame is
+ * available in the FIFO (cut-through operation). If a complete frame has a size
+ * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
+ * to the line. To enable store and forward on the Transmit path, set STR_FWD to
+ * '1'. In this case, the MAC starts to transmit data only when a complete frame
+ * is stored in the Transmit FIFO.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TFWR register
+ */
+/*@{*/
+#define ENET_RD_TFWR(base)       (ENET_TFWR_REG(base))
+#define ENET_WR_TFWR(base, value) (ENET_TFWR_REG(base) = (value))
+#define ENET_RMW_TFWR(base, mask, value) (ENET_WR_TFWR(base, (ENET_RD_TFWR(base) & ~(mask)) | (value)))
+#define ENET_SET_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) |  (value)))
+#define ENET_CLR_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) & ~(value)))
+#define ENET_TOG_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TFWR bitfields
+ */
+
+/*!
+ * @name Register ENET_TFWR, field TFWR[5:0] (RW)
+ *
+ * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
+ * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
+ * begins. If a frame with less than the threshold is written, it is still sent
+ * independently of this threshold setting. The threshold is relevant only if the
+ * frame is larger than the threshold given. This chip may not support the maximum
+ * number of bytes written shown below. See the chip-specific information for the
+ * ENET module for this value.
+ *
+ * Values:
+ * - 0b000000 - 64 bytes written.
+ * - 0b000001 - 64 bytes written.
+ * - 0b000010 - 128 bytes written.
+ * - 0b000011 - 192 bytes written.
+ * - 0b111110 - 3968 bytes written.
+ * - 0b111111 - 4032 bytes written.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TFWR_TFWR field. */
+#define ENET_RD_TFWR_TFWR(base) ((ENET_TFWR_REG(base) & ENET_TFWR_TFWR_MASK) >> ENET_TFWR_TFWR_SHIFT)
+#define ENET_BRD_TFWR_TFWR(base) (ENET_RD_TFWR_TFWR(base))
+
+/*! @brief Set the TFWR field to a new value. */
+#define ENET_WR_TFWR_TFWR(base, value) (ENET_RMW_TFWR(base, ENET_TFWR_TFWR_MASK, ENET_TFWR_TFWR(value)))
+#define ENET_BWR_TFWR_TFWR(base, value) (ENET_WR_TFWR_TFWR(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TFWR, field STRFWD[8] (RW)
+ *
+ * Values:
+ * - 0b0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
+ * - 0b1 - Enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TFWR_STRFWD field. */
+#define ENET_RD_TFWR_STRFWD(base) ((ENET_TFWR_REG(base) & ENET_TFWR_STRFWD_MASK) >> ENET_TFWR_STRFWD_SHIFT)
+#define ENET_BRD_TFWR_STRFWD(base) (BITBAND_ACCESS32(&ENET_TFWR_REG(base), ENET_TFWR_STRFWD_SHIFT))
+
+/*! @brief Set the STRFWD field to a new value. */
+#define ENET_WR_TFWR_STRFWD(base, value) (ENET_RMW_TFWR(base, ENET_TFWR_STRFWD_MASK, ENET_TFWR_STRFWD(value)))
+#define ENET_BWR_TFWR_STRFWD(base, value) (BITBAND_ACCESS32(&ENET_TFWR_REG(base), ENET_TFWR_STRFWD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RDSR - Receive Descriptor Ring Start Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RDSR - Receive Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDSR points to the beginning of the circular receive buffer descriptor queue
+ * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
+ * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
+ * by 16. This register must be initialized prior to operation
+ */
+/*!
+ * @name Constants and macros for entire ENET_RDSR register
+ */
+/*@{*/
+#define ENET_RD_RDSR(base)       (ENET_RDSR_REG(base))
+#define ENET_WR_RDSR(base, value) (ENET_RDSR_REG(base) = (value))
+#define ENET_RMW_RDSR(base, mask, value) (ENET_WR_RDSR(base, (ENET_RD_RDSR(base) & ~(mask)) | (value)))
+#define ENET_SET_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) |  (value)))
+#define ENET_CLR_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) & ~(value)))
+#define ENET_TOG_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the receive buffer descriptor queue.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RDSR_R_DES_START field. */
+#define ENET_RD_RDSR_R_DES_START(base) ((ENET_RDSR_REG(base) & ENET_RDSR_R_DES_START_MASK) >> ENET_RDSR_R_DES_START_SHIFT)
+#define ENET_BRD_RDSR_R_DES_START(base) (ENET_RD_RDSR_R_DES_START(base))
+
+/*! @brief Set the R_DES_START field to a new value. */
+#define ENET_WR_RDSR_R_DES_START(base, value) (ENET_RMW_RDSR(base, ENET_RDSR_R_DES_START_MASK, ENET_RDSR_R_DES_START(value)))
+#define ENET_BWR_RDSR_R_DES_START(base, value) (ENET_WR_RDSR_R_DES_START(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TDSR provides a pointer to the beginning of the circular transmit buffer
+ * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
+ * must be zero); however, it is recommended to be 128-bit aligned, that is,
+ * evenly divisible by 16. This register must be initialized prior to operation.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TDSR register
+ */
+/*@{*/
+#define ENET_RD_TDSR(base)       (ENET_TDSR_REG(base))
+#define ENET_WR_TDSR(base, value) (ENET_TDSR_REG(base) = (value))
+#define ENET_RMW_TDSR(base, mask, value) (ENET_WR_TDSR(base, (ENET_RD_TDSR(base) & ~(mask)) | (value)))
+#define ENET_SET_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) |  (value)))
+#define ENET_CLR_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) & ~(value)))
+#define ENET_TOG_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the transmit buffer descriptor queue.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TDSR_X_DES_START field. */
+#define ENET_RD_TDSR_X_DES_START(base) ((ENET_TDSR_REG(base) & ENET_TDSR_X_DES_START_MASK) >> ENET_TDSR_X_DES_START_SHIFT)
+#define ENET_BRD_TDSR_X_DES_START(base) (ENET_RD_TDSR_X_DES_START(base))
+
+/*! @brief Set the X_DES_START field to a new value. */
+#define ENET_WR_TDSR_X_DES_START(base, value) (ENET_RMW_TDSR(base, ENET_TDSR_X_DES_START_MASK, ENET_TDSR_X_DES_START(value)))
+#define ENET_BWR_TDSR_X_DES_START(base, value) (ENET_WR_TDSR_X_DES_START(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MRBR - Maximum Receive Buffer Size Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MRBR - Maximum Receive Buffer Size Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MRBR is a user-programmable register that dictates the maximum size of
+ * all receive buffers. This value should take into consideration that the receive
+ * CRC is always written into the last receive buffer. To allow one maximum size
+ * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
+ * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
+ * set to zero by the device. To minimize bus usage (descriptor fetches), set
+ * MRBR greater than or equal to 256 bytes. This register must be initialized
+ * before operation.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MRBR register
+ */
+/*@{*/
+#define ENET_RD_MRBR(base)       (ENET_MRBR_REG(base))
+#define ENET_WR_MRBR(base, value) (ENET_MRBR_REG(base) = (value))
+#define ENET_RMW_MRBR(base, mask, value) (ENET_WR_MRBR(base, (ENET_RD_MRBR(base) & ~(mask)) | (value)))
+#define ENET_SET_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) |  (value)))
+#define ENET_CLR_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) & ~(value)))
+#define ENET_TOG_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MRBR bitfields
+ */
+
+/*!
+ * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
+ *
+ * Receive buffer size in bytes.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field. */
+#define ENET_RD_MRBR_R_BUF_SIZE(base) ((ENET_MRBR_REG(base) & ENET_MRBR_R_BUF_SIZE_MASK) >> ENET_MRBR_R_BUF_SIZE_SHIFT)
+#define ENET_BRD_MRBR_R_BUF_SIZE(base) (ENET_RD_MRBR_R_BUF_SIZE(base))
+
+/*! @brief Set the R_BUF_SIZE field to a new value. */
+#define ENET_WR_MRBR_R_BUF_SIZE(base, value) (ENET_RMW_MRBR(base, ENET_MRBR_R_BUF_SIZE_MASK, ENET_MRBR_R_BUF_SIZE(value)))
+#define ENET_BWR_MRBR_R_BUF_SIZE(base, value) (ENET_WR_MRBR_R_BUF_SIZE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RSFL - Receive FIFO Section Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RSFL - Receive FIFO Section Full Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RSFL register
+ */
+/*@{*/
+#define ENET_RD_RSFL(base)       (ENET_RSFL_REG(base))
+#define ENET_WR_RSFL(base, value) (ENET_RSFL_REG(base) = (value))
+#define ENET_RMW_RSFL(base, mask, value) (ENET_WR_RSFL(base, (ENET_RD_RSFL(base) & ~(mask)) | (value)))
+#define ENET_SET_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) |  (value)))
+#define ENET_CLR_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) & ~(value)))
+#define ENET_TOG_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RSFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
+ * this field to enable store and forward on the RX FIFO. When programming a value
+ * greater than 0 (cut-through operation), it must be greater than
+ * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
+ * in the Receive FIFO (cut-through operation).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field. */
+#define ENET_RD_RSFL_RX_SECTION_FULL(base) ((ENET_RSFL_REG(base) & ENET_RSFL_RX_SECTION_FULL_MASK) >> ENET_RSFL_RX_SECTION_FULL_SHIFT)
+#define ENET_BRD_RSFL_RX_SECTION_FULL(base) (ENET_RD_RSFL_RX_SECTION_FULL(base))
+
+/*! @brief Set the RX_SECTION_FULL field to a new value. */
+#define ENET_WR_RSFL_RX_SECTION_FULL(base, value) (ENET_RMW_RSFL(base, ENET_RSFL_RX_SECTION_FULL_MASK, ENET_RSFL_RX_SECTION_FULL(value)))
+#define ENET_BWR_RSFL_RX_SECTION_FULL(base, value) (ENET_WR_RSFL_RX_SECTION_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RSEM - Receive FIFO Section Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RSEM register
+ */
+/*@{*/
+#define ENET_RD_RSEM(base)       (ENET_RSEM_REG(base))
+#define ENET_WR_RSEM(base, value) (ENET_RSEM_REG(base) = (value))
+#define ENET_RMW_RSEM(base, mask, value) (ENET_WR_RSEM(base, (ENET_RD_RSEM(base) & ~(mask)) | (value)))
+#define ENET_SET_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) |  (value)))
+#define ENET_CLR_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) & ~(value)))
+#define ENET_TOG_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
+ * FIFO has reached this level, a pause frame will be issued. A value of 0
+ * disables automatic pause frame generation. When the FIFO level goes below the value
+ * programmed in this field, an XON pause frame is issued to indicate the FIFO
+ * congestion is cleared to the remote Ethernet client. The section-empty
+ * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field. */
+#define ENET_RD_RSEM_RX_SECTION_EMPTY(base) ((ENET_RSEM_REG(base) & ENET_RSEM_RX_SECTION_EMPTY_MASK) >> ENET_RSEM_RX_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_RSEM_RX_SECTION_EMPTY(base) (ENET_RD_RSEM_RX_SECTION_EMPTY(base))
+
+/*! @brief Set the RX_SECTION_EMPTY field to a new value. */
+#define ENET_WR_RSEM_RX_SECTION_EMPTY(base, value) (ENET_RMW_RSEM(base, ENET_RSEM_RX_SECTION_EMPTY_MASK, ENET_RSEM_RX_SECTION_EMPTY(value)))
+#define ENET_BWR_RSEM_RX_SECTION_EMPTY(base, value) (ENET_WR_RSEM_RX_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
+ *
+ * Defines number of frames in the receive FIFO, independent of its size, that
+ * can be accepted. If the limit is reached, reception will continue normally,
+ * however a pause frame will be triggered to indicate a possible congestion to the
+ * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
+ * frame generation
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field. */
+#define ENET_RD_RSEM_STAT_SECTION_EMPTY(base) ((ENET_RSEM_REG(base) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) >> ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_RSEM_STAT_SECTION_EMPTY(base) (ENET_RD_RSEM_STAT_SECTION_EMPTY(base))
+
+/*! @brief Set the STAT_SECTION_EMPTY field to a new value. */
+#define ENET_WR_RSEM_STAT_SECTION_EMPTY(base, value) (ENET_RMW_RSEM(base, ENET_RSEM_STAT_SECTION_EMPTY_MASK, ENET_RSEM_STAT_SECTION_EMPTY(value)))
+#define ENET_BWR_RSEM_STAT_SECTION_EMPTY(base, value) (ENET_WR_RSEM_STAT_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RAEM - Receive FIFO Almost Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RAEM register
+ */
+/*@{*/
+#define ENET_RD_RAEM(base)       (ENET_RAEM_REG(base))
+#define ENET_WR_RAEM(base, value) (ENET_RAEM_REG(base) = (value))
+#define ENET_RMW_RAEM(base, mask, value) (ENET_WR_RAEM(base, (ENET_RD_RAEM(base) & ~(mask)) | (value)))
+#define ENET_SET_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) |  (value)))
+#define ENET_CLR_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) & ~(value)))
+#define ENET_TOG_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field and the end-of-frame has
+ * not been received for the frame yet, the core receive read control stops FIFO
+ * read (and subsequently stops transferring data to the MAC client
+ * application). It continues to deliver the frame, if again more data than the threshold or
+ * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field. */
+#define ENET_RD_RAEM_RX_ALMOST_EMPTY(base) ((ENET_RAEM_REG(base) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) >> ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)
+#define ENET_BRD_RAEM_RX_ALMOST_EMPTY(base) (ENET_RD_RAEM_RX_ALMOST_EMPTY(base))
+
+/*! @brief Set the RX_ALMOST_EMPTY field to a new value. */
+#define ENET_WR_RAEM_RX_ALMOST_EMPTY(base, value) (ENET_RMW_RAEM(base, ENET_RAEM_RX_ALMOST_EMPTY_MASK, ENET_RAEM_RX_ALMOST_EMPTY(value)))
+#define ENET_BWR_RAEM_RX_ALMOST_EMPTY(base, value) (ENET_WR_RAEM_RX_ALMOST_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RAFL - Receive FIFO Almost Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RAFL register
+ */
+/*@{*/
+#define ENET_RD_RAFL(base)       (ENET_RAFL_REG(base))
+#define ENET_WR_RAFL(base, value) (ENET_RAFL_REG(base) = (value))
+#define ENET_RMW_RAFL(base, mask, value) (ENET_WR_RAFL(base, (ENET_RD_RAFL(base) & ~(mask)) | (value)))
+#define ENET_SET_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) |  (value)))
+#define ENET_CLR_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) & ~(value)))
+#define ENET_TOG_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
+ * truncates the received frame to avoid FIFO overflow. The corresponding error
+ * status will be set when the frame is delivered to the application. A minimum
+ * value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field. */
+#define ENET_RD_RAFL_RX_ALMOST_FULL(base) ((ENET_RAFL_REG(base) & ENET_RAFL_RX_ALMOST_FULL_MASK) >> ENET_RAFL_RX_ALMOST_FULL_SHIFT)
+#define ENET_BRD_RAFL_RX_ALMOST_FULL(base) (ENET_RD_RAFL_RX_ALMOST_FULL(base))
+
+/*! @brief Set the RX_ALMOST_FULL field to a new value. */
+#define ENET_WR_RAFL_RX_ALMOST_FULL(base, value) (ENET_RMW_RAFL(base, ENET_RAFL_RX_ALMOST_FULL_MASK, ENET_RAFL_RX_ALMOST_FULL(value)))
+#define ENET_BWR_RAFL_RX_ALMOST_FULL(base, value) (ENET_WR_RAFL_RX_ALMOST_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TSEM - Transmit FIFO Section Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TSEM register
+ */
+/*@{*/
+#define ENET_RD_TSEM(base)       (ENET_TSEM_REG(base))
+#define ENET_WR_TSEM(base, value) (ENET_TSEM_REG(base) = (value))
+#define ENET_RMW_TSEM(base, mask, value) (ENET_WR_TSEM(base, (ENET_RD_TSEM(base) & ~(mask)) | (value)))
+#define ENET_SET_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) |  (value)))
+#define ENET_CLR_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) & ~(value)))
+#define ENET_TOG_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field. */
+#define ENET_RD_TSEM_TX_SECTION_EMPTY(base) ((ENET_TSEM_REG(base) & ENET_TSEM_TX_SECTION_EMPTY_MASK) >> ENET_TSEM_TX_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_TSEM_TX_SECTION_EMPTY(base) (ENET_RD_TSEM_TX_SECTION_EMPTY(base))
+
+/*! @brief Set the TX_SECTION_EMPTY field to a new value. */
+#define ENET_WR_TSEM_TX_SECTION_EMPTY(base, value) (ENET_RMW_TSEM(base, ENET_TSEM_TX_SECTION_EMPTY_MASK, ENET_TSEM_TX_SECTION_EMPTY(value)))
+#define ENET_BWR_TSEM_TX_SECTION_EMPTY(base, value) (ENET_WR_TSEM_TX_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TAEM register
+ */
+/*@{*/
+#define ENET_RD_TAEM(base)       (ENET_TAEM_REG(base))
+#define ENET_WR_TAEM(base, value) (ENET_TAEM_REG(base) = (value))
+#define ENET_RMW_TAEM(base, mask, value) (ENET_WR_TAEM(base, (ENET_RD_TAEM(base) & ~(mask)) | (value)))
+#define ENET_SET_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) |  (value)))
+#define ENET_CLR_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) & ~(value)))
+#define ENET_TOG_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field, and no end-of-frame is
+ * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
+ * stops reading the FIFO and transmits a frame with an MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A minimum value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field. */
+#define ENET_RD_TAEM_TX_ALMOST_EMPTY(base) ((ENET_TAEM_REG(base) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) >> ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)
+#define ENET_BRD_TAEM_TX_ALMOST_EMPTY(base) (ENET_RD_TAEM_TX_ALMOST_EMPTY(base))
+
+/*! @brief Set the TX_ALMOST_EMPTY field to a new value. */
+#define ENET_WR_TAEM_TX_ALMOST_EMPTY(base, value) (ENET_RMW_TAEM(base, ENET_TAEM_TX_ALMOST_EMPTY_MASK, ENET_TAEM_TX_ALMOST_EMPTY(value)))
+#define ENET_BWR_TAEM_TX_ALMOST_EMPTY(base, value) (ENET_WR_TAEM_TX_ALMOST_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TAFL - Transmit FIFO Almost Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000008U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TAFL register
+ */
+/*@{*/
+#define ENET_RD_TAFL(base)       (ENET_TAFL_REG(base))
+#define ENET_WR_TAFL(base, value) (ENET_TAFL_REG(base) = (value))
+#define ENET_RMW_TAFL(base, mask, value) (ENET_WR_TAFL(base, (ENET_RD_TAFL(base) & ~(mask)) | (value)))
+#define ENET_SET_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) |  (value)))
+#define ENET_CLR_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) & ~(value)))
+#define ENET_TOG_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
+ * value of six is required . A recommended value of at least 8 should be set
+ * allowing a latency of two clock cycles to the application. If more latency is
+ * required the value can be increased as necessary (latency = TAFL - 5). When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
+ * application does not react on this signal, the FIFO write control logic, to
+ * avoid FIFO overflow, truncates the current frame and sets the error status. As a
+ * result, the frame will be transmitted with an GMII/MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A FIFO overflow is a fatal error and requires
+ * a global reset on the transmit datapath or at least deassertion of ETHEREN.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field. */
+#define ENET_RD_TAFL_TX_ALMOST_FULL(base) ((ENET_TAFL_REG(base) & ENET_TAFL_TX_ALMOST_FULL_MASK) >> ENET_TAFL_TX_ALMOST_FULL_SHIFT)
+#define ENET_BRD_TAFL_TX_ALMOST_FULL(base) (ENET_RD_TAFL_TX_ALMOST_FULL(base))
+
+/*! @brief Set the TX_ALMOST_FULL field to a new value. */
+#define ENET_WR_TAFL_TX_ALMOST_FULL(base, value) (ENET_RMW_TAFL(base, ENET_TAFL_TX_ALMOST_FULL_MASK, ENET_TAFL_TX_ALMOST_FULL(value)))
+#define ENET_BWR_TAFL_TX_ALMOST_FULL(base, value) (ENET_WR_TAFL_TX_ALMOST_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TIPG - Transmit Inter-Packet Gap
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TIPG - Transmit Inter-Packet Gap (RW)
+ *
+ * Reset value: 0x0000000CU
+ */
+/*!
+ * @name Constants and macros for entire ENET_TIPG register
+ */
+/*@{*/
+#define ENET_RD_TIPG(base)       (ENET_TIPG_REG(base))
+#define ENET_WR_TIPG(base, value) (ENET_TIPG_REG(base) = (value))
+#define ENET_RMW_TIPG(base, mask, value) (ENET_WR_TIPG(base, (ENET_RD_TIPG(base) & ~(mask)) | (value)))
+#define ENET_SET_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) |  (value)))
+#define ENET_CLR_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) & ~(value)))
+#define ENET_TOG_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TIPG bitfields
+ */
+
+/*!
+ * @name Register ENET_TIPG, field IPG[4:0] (RW)
+ *
+ * Indicates the IPG, in bytes, between transmitted frames. Valid values range
+ * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
+ * 27, the IPG is 27.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TIPG_IPG field. */
+#define ENET_RD_TIPG_IPG(base) ((ENET_TIPG_REG(base) & ENET_TIPG_IPG_MASK) >> ENET_TIPG_IPG_SHIFT)
+#define ENET_BRD_TIPG_IPG(base) (ENET_RD_TIPG_IPG(base))
+
+/*! @brief Set the IPG field to a new value. */
+#define ENET_WR_TIPG_IPG(base, value) (ENET_RMW_TIPG(base, ENET_TIPG_IPG_MASK, ENET_TIPG_IPG(value)))
+#define ENET_BWR_TIPG_IPG(base, value) (ENET_WR_TIPG_IPG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_FTRL - Frame Truncation Length
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_FTRL - Frame Truncation Length (RW)
+ *
+ * Reset value: 0x000007FFU
+ */
+/*!
+ * @name Constants and macros for entire ENET_FTRL register
+ */
+/*@{*/
+#define ENET_RD_FTRL(base)       (ENET_FTRL_REG(base))
+#define ENET_WR_FTRL(base, value) (ENET_FTRL_REG(base) = (value))
+#define ENET_RMW_FTRL(base, mask, value) (ENET_WR_FTRL(base, (ENET_RD_FTRL(base) & ~(mask)) | (value)))
+#define ENET_SET_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) |  (value)))
+#define ENET_CLR_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) & ~(value)))
+#define ENET_TOG_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_FTRL bitfields
+ */
+
+/*!
+ * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
+ *
+ * Indicates the value a receive frame is truncated, if it is greater than this
+ * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
+ * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
+ * less data, guaranteeing that it never receives more than the set limit.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_FTRL_TRUNC_FL field. */
+#define ENET_RD_FTRL_TRUNC_FL(base) ((ENET_FTRL_REG(base) & ENET_FTRL_TRUNC_FL_MASK) >> ENET_FTRL_TRUNC_FL_SHIFT)
+#define ENET_BRD_FTRL_TRUNC_FL(base) (ENET_RD_FTRL_TRUNC_FL(base))
+
+/*! @brief Set the TRUNC_FL field to a new value. */
+#define ENET_WR_FTRL_TRUNC_FL(base, value) (ENET_RMW_FTRL(base, ENET_FTRL_TRUNC_FL_MASK, ENET_FTRL_TRUNC_FL(value)))
+#define ENET_BWR_FTRL_TRUNC_FL(base, value) (ENET_WR_FTRL_TRUNC_FL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TACC - Transmit Accelerator Function Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TACC - Transmit Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TACC controls accelerator actions when sending frames. The register can be
+ * changed before or after each frame, but it must remain unmodified during frame
+ * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
+ * checksum feature.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TACC register
+ */
+/*@{*/
+#define ENET_RD_TACC(base)       (ENET_TACC_REG(base))
+#define ENET_WR_TACC(base, value) (ENET_TACC_REG(base) = (value))
+#define ENET_RMW_TACC(base, mask, value) (ENET_WR_TACC(base, (ENET_RD_TACC(base) & ~(mask)) | (value)))
+#define ENET_SET_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) |  (value)))
+#define ENET_CLR_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) & ~(value)))
+#define ENET_TOG_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TACC bitfields
+ */
+
+/*!
+ * @name Register ENET_TACC, field SHIFT16[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Indicates to the transmit data FIFO that the written frames contain
+ *     two additional octets before the frame data. This means the actual frame
+ *     begins at bit 16 of the first word written into the FIFO. This function
+ *     allows putting the frame payload on a 32-bit boundary in memory, as the
+ *     14-byte Ethernet header is extended to a 16-byte header.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_SHIFT16 field. */
+#define ENET_RD_TACC_SHIFT16(base) ((ENET_TACC_REG(base) & ENET_TACC_SHIFT16_MASK) >> ENET_TACC_SHIFT16_SHIFT)
+#define ENET_BRD_TACC_SHIFT16(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_SHIFT16_SHIFT))
+
+/*! @brief Set the SHIFT16 field to a new value. */
+#define ENET_WR_TACC_SHIFT16(base, value) (ENET_RMW_TACC(base, ENET_TACC_SHIFT16_MASK, ENET_TACC_SHIFT16(value)))
+#define ENET_BWR_TACC_SHIFT16(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_SHIFT16_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TACC, field IPCHK[3] (RW)
+ *
+ * Enables insertion of IP header checksum.
+ *
+ * Values:
+ * - 0b0 - Checksum is not inserted.
+ * - 0b1 - If an IP frame is transmitted, the checksum is inserted
+ *     automatically. The IP header checksum field must be cleared. If a non-IP frame is
+ *     transmitted the frame is not modified.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_IPCHK field. */
+#define ENET_RD_TACC_IPCHK(base) ((ENET_TACC_REG(base) & ENET_TACC_IPCHK_MASK) >> ENET_TACC_IPCHK_SHIFT)
+#define ENET_BRD_TACC_IPCHK(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_IPCHK_SHIFT))
+
+/*! @brief Set the IPCHK field to a new value. */
+#define ENET_WR_TACC_IPCHK(base, value) (ENET_RMW_TACC(base, ENET_TACC_IPCHK_MASK, ENET_TACC_IPCHK(value)))
+#define ENET_BWR_TACC_IPCHK(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_IPCHK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TACC, field PROCHK[4] (RW)
+ *
+ * Enables insertion of protocol checksum.
+ *
+ * Values:
+ * - 0b0 - Checksum not inserted.
+ * - 0b1 - If an IP frame with a known protocol is transmitted, the checksum is
+ *     inserted automatically into the frame. The checksum field must be cleared.
+ *     The other frames are not modified.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_PROCHK field. */
+#define ENET_RD_TACC_PROCHK(base) ((ENET_TACC_REG(base) & ENET_TACC_PROCHK_MASK) >> ENET_TACC_PROCHK_SHIFT)
+#define ENET_BRD_TACC_PROCHK(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_PROCHK_SHIFT))
+
+/*! @brief Set the PROCHK field to a new value. */
+#define ENET_WR_TACC_PROCHK(base, value) (ENET_RMW_TACC(base, ENET_TACC_PROCHK_MASK, ENET_TACC_PROCHK(value)))
+#define ENET_BWR_TACC_PROCHK(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_PROCHK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RACC - Receive Accelerator Function Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RACC - Receive Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RACC register
+ */
+/*@{*/
+#define ENET_RD_RACC(base)       (ENET_RACC_REG(base))
+#define ENET_WR_RACC(base, value) (ENET_RACC_REG(base) = (value))
+#define ENET_RMW_RACC(base, mask, value) (ENET_WR_RACC(base, (ENET_RD_RACC(base) & ~(mask)) | (value)))
+#define ENET_SET_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) |  (value)))
+#define ENET_CLR_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) & ~(value)))
+#define ENET_TOG_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RACC bitfields
+ */
+
+/*!
+ * @name Register ENET_RACC, field PADREM[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Padding not removed.
+ * - 0b1 - Any bytes following the IP payload section of the frame are removed
+ *     from the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_PADREM field. */
+#define ENET_RD_RACC_PADREM(base) ((ENET_RACC_REG(base) & ENET_RACC_PADREM_MASK) >> ENET_RACC_PADREM_SHIFT)
+#define ENET_BRD_RACC_PADREM(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PADREM_SHIFT))
+
+/*! @brief Set the PADREM field to a new value. */
+#define ENET_WR_RACC_PADREM(base, value) (ENET_RMW_RACC(base, ENET_RACC_PADREM_MASK, ENET_RACC_PADREM(value)))
+#define ENET_BWR_RACC_PADREM(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PADREM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field IPDIS[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with wrong IPv4 header checksum are not discarded.
+ * - 0b1 - If an IPv4 frame is received with a mismatching header checksum, the
+ *     frame is discarded. IPv6 has no header checksum and is not affected by
+ *     this setting. Discarding is only available when the RX FIFO operates in store
+ *     and forward mode (RSFL cleared).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_IPDIS field. */
+#define ENET_RD_RACC_IPDIS(base) ((ENET_RACC_REG(base) & ENET_RACC_IPDIS_MASK) >> ENET_RACC_IPDIS_SHIFT)
+#define ENET_BRD_RACC_IPDIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_IPDIS_SHIFT))
+
+/*! @brief Set the IPDIS field to a new value. */
+#define ENET_WR_RACC_IPDIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_IPDIS_MASK, ENET_RACC_IPDIS(value)))
+#define ENET_BWR_RACC_IPDIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_IPDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field PRODIS[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with wrong checksum are not discarded.
+ * - 0b1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong
+ *     TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only
+ *     available when the RX FIFO operates in store and forward mode (RSFL cleared).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_PRODIS field. */
+#define ENET_RD_RACC_PRODIS(base) ((ENET_RACC_REG(base) & ENET_RACC_PRODIS_MASK) >> ENET_RACC_PRODIS_SHIFT)
+#define ENET_BRD_RACC_PRODIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PRODIS_SHIFT))
+
+/*! @brief Set the PRODIS field to a new value. */
+#define ENET_WR_RACC_PRODIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_PRODIS_MASK, ENET_RACC_PRODIS(value)))
+#define ENET_BWR_RACC_PRODIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PRODIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field LINEDIS[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with errors are not discarded.
+ * - 0b1 - Any frame received with a CRC, length, or PHY error is automatically
+ *     discarded and not forwarded to the user application interface.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_LINEDIS field. */
+#define ENET_RD_RACC_LINEDIS(base) ((ENET_RACC_REG(base) & ENET_RACC_LINEDIS_MASK) >> ENET_RACC_LINEDIS_SHIFT)
+#define ENET_BRD_RACC_LINEDIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_LINEDIS_SHIFT))
+
+/*! @brief Set the LINEDIS field to a new value. */
+#define ENET_WR_RACC_LINEDIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_LINEDIS_MASK, ENET_RACC_LINEDIS(value)))
+#define ENET_BWR_RACC_LINEDIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_LINEDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field SHIFT16[7] (RW)
+ *
+ * When this field is set, the actual frame data starts at bit 16 of the first
+ * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
+ * This function only affects the FIFO storage and has no influence on the
+ * statistics, which use the actual length of the frame received.
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Instructs the MAC to write two additional bytes in front of each
+ *     frame received into the RX FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_SHIFT16 field. */
+#define ENET_RD_RACC_SHIFT16(base) ((ENET_RACC_REG(base) & ENET_RACC_SHIFT16_MASK) >> ENET_RACC_SHIFT16_SHIFT)
+#define ENET_BRD_RACC_SHIFT16(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_SHIFT16_SHIFT))
+
+/*! @brief Set the SHIFT16 field to a new value. */
+#define ENET_WR_RACC_SHIFT16(base, value) (ENET_RMW_RACC(base, ENET_RACC_SHIFT16_MASK, ENET_RACC_SHIFT16(value)))
+#define ENET_BWR_RACC_SHIFT16(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_SHIFT16_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_PACKETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_PACKETS(base) (ENET_RMON_T_PACKETS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field. */
+#define ENET_RD_RMON_T_PACKETS_TXPKTS(base) ((ENET_RMON_T_PACKETS_REG(base) & ENET_RMON_T_PACKETS_TXPKTS_MASK) >> ENET_RMON_T_PACKETS_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_PACKETS_TXPKTS(base) (ENET_RD_RMON_T_PACKETS_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RMON Tx Broadcast Packets
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_BC_PKT(base) (ENET_RMON_T_BC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field. */
+#define ENET_RD_RMON_T_BC_PKT_TXPKTS(base) ((ENET_RMON_T_BC_PKT_REG(base) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) >> ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_BC_PKT_TXPKTS(base) (ENET_RD_RMON_T_BC_PKT_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_MC_PKT(base) (ENET_RMON_T_MC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field. */
+#define ENET_RD_RMON_T_MC_PKT_TXPKTS(base) ((ENET_RMON_T_MC_PKT_REG(base) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) >> ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_MC_PKT_TXPKTS(base) (ENET_RD_RMON_T_MC_PKT_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_CRC_ALIGN(base) (ENET_RMON_T_CRC_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field. */
+#define ENET_RD_RMON_T_CRC_ALIGN_TXPKTS(base) ((ENET_RMON_T_CRC_ALIGN_REG(base) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) >> ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_CRC_ALIGN_TXPKTS(base) (ENET_RD_RMON_T_CRC_ALIGN_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_UNDERSIZE(base) (ENET_RMON_T_UNDERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field. */
+#define ENET_RD_RMON_T_UNDERSIZE_TXPKTS(base) ((ENET_RMON_T_UNDERSIZE_REG(base) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) >> ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_UNDERSIZE_TXPKTS(base) (ENET_RD_RMON_T_UNDERSIZE_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_OVERSIZE(base) (ENET_RMON_T_OVERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field. */
+#define ENET_RD_RMON_T_OVERSIZE_TXPKTS(base) ((ENET_RMON_T_OVERSIZE_REG(base) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) >> ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_OVERSIZE_TXPKTS(base) (ENET_RD_RMON_T_OVERSIZE_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_FRAG register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_FRAG(base) (ENET_RMON_T_FRAG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field. */
+#define ENET_RD_RMON_T_FRAG_TXPKTS(base) ((ENET_RMON_T_FRAG_REG(base) & ENET_RMON_T_FRAG_TXPKTS_MASK) >> ENET_RMON_T_FRAG_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_FRAG_TXPKTS(base) (ENET_RD_RMON_T_FRAG_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_JAB register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_JAB(base) (ENET_RMON_T_JAB_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field. */
+#define ENET_RD_RMON_T_JAB_TXPKTS(base) ((ENET_RMON_T_JAB_REG(base) & ENET_RMON_T_JAB_TXPKTS_MASK) >> ENET_RMON_T_JAB_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_JAB_TXPKTS(base) (ENET_RD_RMON_T_JAB_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_COL register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_COL(base) (ENET_RMON_T_COL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_COL bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field. */
+#define ENET_RD_RMON_T_COL_TXPKTS(base) ((ENET_RMON_T_COL_REG(base) & ENET_RMON_T_COL_TXPKTS_MASK) >> ENET_RMON_T_COL_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_COL_TXPKTS(base) (ENET_RD_RMON_T_COL_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P64 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P64(base) (ENET_RMON_T_P64_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field. */
+#define ENET_RD_RMON_T_P64_TXPKTS(base) ((ENET_RMON_T_P64_REG(base) & ENET_RMON_T_P64_TXPKTS_MASK) >> ENET_RMON_T_P64_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P64_TXPKTS(base) (ENET_RD_RMON_T_P64_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P65TO127(base) (ENET_RMON_T_P65TO127_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field. */
+#define ENET_RD_RMON_T_P65TO127_TXPKTS(base) ((ENET_RMON_T_P65TO127_REG(base) & ENET_RMON_T_P65TO127_TXPKTS_MASK) >> ENET_RMON_T_P65TO127_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P65TO127_TXPKTS(base) (ENET_RD_RMON_T_P65TO127_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P128TO255(base) (ENET_RMON_T_P128TO255_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field. */
+#define ENET_RD_RMON_T_P128TO255_TXPKTS(base) ((ENET_RMON_T_P128TO255_REG(base) & ENET_RMON_T_P128TO255_TXPKTS_MASK) >> ENET_RMON_T_P128TO255_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P128TO255_TXPKTS(base) (ENET_RD_RMON_T_P128TO255_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P256TO511(base) (ENET_RMON_T_P256TO511_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field. */
+#define ENET_RD_RMON_T_P256TO511_TXPKTS(base) ((ENET_RMON_T_P256TO511_REG(base) & ENET_RMON_T_P256TO511_TXPKTS_MASK) >> ENET_RMON_T_P256TO511_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P256TO511_TXPKTS(base) (ENET_RD_RMON_T_P256TO511_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P512TO1023(base) (ENET_RMON_T_P512TO1023_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field. */
+#define ENET_RD_RMON_T_P512TO1023_TXPKTS(base) ((ENET_RMON_T_P512TO1023_REG(base) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) >> ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P512TO1023_TXPKTS(base) (ENET_RD_RMON_T_P512TO1023_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P1024TO2047(base) (ENET_RMON_T_P1024TO2047_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field. */
+#define ENET_RD_RMON_T_P1024TO2047_TXPKTS(base) ((ENET_RMON_T_P1024TO2047_REG(base) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) >> ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P1024TO2047_TXPKTS(base) (ENET_RD_RMON_T_P1024TO2047_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P_GTE2048(base) (ENET_RMON_T_P_GTE2048_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field. */
+#define ENET_RD_RMON_T_P_GTE2048_TXPKTS(base) ((ENET_RMON_T_P_GTE2048_REG(base) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) >> ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P_GTE2048_TXPKTS(base) (ENET_RD_RMON_T_P_GTE2048_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OCTETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_OCTETS(base) (ENET_RMON_T_OCTETS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_FRAME_OK(base) (ENET_IEEE_T_FRAME_OK_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field. */
+#define ENET_RD_IEEE_T_FRAME_OK_COUNT(base) ((ENET_IEEE_T_FRAME_OK_REG(base) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) >> ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_FRAME_OK_COUNT(base) (ENET_RD_IEEE_T_FRAME_OK_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_1COL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_1COL(base) (ENET_IEEE_T_1COL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_1COL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field. */
+#define ENET_RD_IEEE_T_1COL_COUNT(base) ((ENET_IEEE_T_1COL_REG(base) & ENET_IEEE_T_1COL_COUNT_MASK) >> ENET_IEEE_T_1COL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_1COL_COUNT(base) (ENET_RD_IEEE_T_1COL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_MCOL(base) (ENET_IEEE_T_MCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field. */
+#define ENET_RD_IEEE_T_MCOL_COUNT(base) ((ENET_IEEE_T_MCOL_REG(base) & ENET_IEEE_T_MCOL_COUNT_MASK) >> ENET_IEEE_T_MCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_MCOL_COUNT(base) (ENET_RD_IEEE_T_MCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_DEF register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_DEF(base) (ENET_IEEE_T_DEF_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_DEF bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field. */
+#define ENET_RD_IEEE_T_DEF_COUNT(base) ((ENET_IEEE_T_DEF_REG(base) & ENET_IEEE_T_DEF_COUNT_MASK) >> ENET_IEEE_T_DEF_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_DEF_COUNT(base) (ENET_RD_IEEE_T_DEF_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_LCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_LCOL(base) (ENET_IEEE_T_LCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field. */
+#define ENET_RD_IEEE_T_LCOL_COUNT(base) ((ENET_IEEE_T_LCOL_REG(base) & ENET_IEEE_T_LCOL_COUNT_MASK) >> ENET_IEEE_T_LCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_LCOL_COUNT(base) (ENET_RD_IEEE_T_LCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_EXCOL(base) (ENET_IEEE_T_EXCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field. */
+#define ENET_RD_IEEE_T_EXCOL_COUNT(base) ((ENET_IEEE_T_EXCOL_REG(base) & ENET_IEEE_T_EXCOL_COUNT_MASK) >> ENET_IEEE_T_EXCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_EXCOL_COUNT(base) (ENET_RD_IEEE_T_EXCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MACERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_MACERR(base) (ENET_IEEE_T_MACERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field. */
+#define ENET_RD_IEEE_T_MACERR_COUNT(base) ((ENET_IEEE_T_MACERR_REG(base) & ENET_IEEE_T_MACERR_COUNT_MASK) >> ENET_IEEE_T_MACERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_MACERR_COUNT(base) (ENET_RD_IEEE_T_MACERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_CSERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_CSERR(base) (ENET_IEEE_T_CSERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field. */
+#define ENET_RD_IEEE_T_CSERR_COUNT(base) ((ENET_IEEE_T_CSERR_REG(base) & ENET_IEEE_T_CSERR_COUNT_MASK) >> ENET_IEEE_T_CSERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_CSERR_COUNT(base) (ENET_RD_IEEE_T_CSERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_FDXFC(base) (ENET_IEEE_T_FDXFC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field. */
+#define ENET_RD_IEEE_T_FDXFC_COUNT(base) ((ENET_IEEE_T_FDXFC_REG(base) & ENET_IEEE_T_FDXFC_COUNT_MASK) >> ENET_IEEE_T_FDXFC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_FDXFC_COUNT(base) (ENET_RD_IEEE_T_FDXFC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counts total octets (includes header and FCS fields).
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_OCTETS_OK(base) (ENET_IEEE_T_OCTETS_OK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_PACKETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_PACKETS(base) (ENET_RMON_R_PACKETS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field. */
+#define ENET_RD_RMON_R_PACKETS_COUNT(base) ((ENET_RMON_R_PACKETS_REG(base) & ENET_RMON_R_PACKETS_COUNT_MASK) >> ENET_RMON_R_PACKETS_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_PACKETS_COUNT(base) (ENET_RD_RMON_R_PACKETS_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_BC_PKT(base) (ENET_RMON_R_BC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field. */
+#define ENET_RD_RMON_R_BC_PKT_COUNT(base) ((ENET_RMON_R_BC_PKT_REG(base) & ENET_RMON_R_BC_PKT_COUNT_MASK) >> ENET_RMON_R_BC_PKT_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_BC_PKT_COUNT(base) (ENET_RD_RMON_R_BC_PKT_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_MC_PKT(base) (ENET_RMON_R_MC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field. */
+#define ENET_RD_RMON_R_MC_PKT_COUNT(base) ((ENET_RMON_R_MC_PKT_REG(base) & ENET_RMON_R_MC_PKT_COUNT_MASK) >> ENET_RMON_R_MC_PKT_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_MC_PKT_COUNT(base) (ENET_RD_RMON_R_MC_PKT_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_CRC_ALIGN(base) (ENET_RMON_R_CRC_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field. */
+#define ENET_RD_RMON_R_CRC_ALIGN_COUNT(base) ((ENET_RMON_R_CRC_ALIGN_REG(base) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) >> ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_CRC_ALIGN_COUNT(base) (ENET_RD_RMON_R_CRC_ALIGN_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_UNDERSIZE(base) (ENET_RMON_R_UNDERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field. */
+#define ENET_RD_RMON_R_UNDERSIZE_COUNT(base) ((ENET_RMON_R_UNDERSIZE_REG(base) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) >> ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_UNDERSIZE_COUNT(base) (ENET_RD_RMON_R_UNDERSIZE_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_OVERSIZE(base) (ENET_RMON_R_OVERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field. */
+#define ENET_RD_RMON_R_OVERSIZE_COUNT(base) ((ENET_RMON_R_OVERSIZE_REG(base) & ENET_RMON_R_OVERSIZE_COUNT_MASK) >> ENET_RMON_R_OVERSIZE_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_OVERSIZE_COUNT(base) (ENET_RD_RMON_R_OVERSIZE_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_FRAG register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_FRAG(base) (ENET_RMON_R_FRAG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field. */
+#define ENET_RD_RMON_R_FRAG_COUNT(base) ((ENET_RMON_R_FRAG_REG(base) & ENET_RMON_R_FRAG_COUNT_MASK) >> ENET_RMON_R_FRAG_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_FRAG_COUNT(base) (ENET_RD_RMON_R_FRAG_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_JAB register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_JAB(base) (ENET_RMON_R_JAB_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_JAB_COUNT field. */
+#define ENET_RD_RMON_R_JAB_COUNT(base) ((ENET_RMON_R_JAB_REG(base) & ENET_RMON_R_JAB_COUNT_MASK) >> ENET_RMON_R_JAB_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_JAB_COUNT(base) (ENET_RD_RMON_R_JAB_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P64 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P64(base) (ENET_RMON_R_P64_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P64_COUNT field. */
+#define ENET_RD_RMON_R_P64_COUNT(base) ((ENET_RMON_R_P64_REG(base) & ENET_RMON_R_P64_COUNT_MASK) >> ENET_RMON_R_P64_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P64_COUNT(base) (ENET_RD_RMON_R_P64_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P65TO127(base) (ENET_RMON_R_P65TO127_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field. */
+#define ENET_RD_RMON_R_P65TO127_COUNT(base) ((ENET_RMON_R_P65TO127_REG(base) & ENET_RMON_R_P65TO127_COUNT_MASK) >> ENET_RMON_R_P65TO127_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P65TO127_COUNT(base) (ENET_RD_RMON_R_P65TO127_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P128TO255(base) (ENET_RMON_R_P128TO255_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field. */
+#define ENET_RD_RMON_R_P128TO255_COUNT(base) ((ENET_RMON_R_P128TO255_REG(base) & ENET_RMON_R_P128TO255_COUNT_MASK) >> ENET_RMON_R_P128TO255_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P128TO255_COUNT(base) (ENET_RD_RMON_R_P128TO255_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P256TO511(base) (ENET_RMON_R_P256TO511_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field. */
+#define ENET_RD_RMON_R_P256TO511_COUNT(base) ((ENET_RMON_R_P256TO511_REG(base) & ENET_RMON_R_P256TO511_COUNT_MASK) >> ENET_RMON_R_P256TO511_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P256TO511_COUNT(base) (ENET_RD_RMON_R_P256TO511_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P512TO1023(base) (ENET_RMON_R_P512TO1023_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field. */
+#define ENET_RD_RMON_R_P512TO1023_COUNT(base) ((ENET_RMON_R_P512TO1023_REG(base) & ENET_RMON_R_P512TO1023_COUNT_MASK) >> ENET_RMON_R_P512TO1023_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P512TO1023_COUNT(base) (ENET_RD_RMON_R_P512TO1023_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P1024TO2047(base) (ENET_RMON_R_P1024TO2047_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field. */
+#define ENET_RD_RMON_R_P1024TO2047_COUNT(base) ((ENET_RMON_R_P1024TO2047_REG(base) & ENET_RMON_R_P1024TO2047_COUNT_MASK) >> ENET_RMON_R_P1024TO2047_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P1024TO2047_COUNT(base) (ENET_RD_RMON_R_P1024TO2047_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P_GTE2048 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P_GTE2048(base) (ENET_RMON_R_P_GTE2048_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P_GTE2048, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P_GTE2048_COUNT field. */
+#define ENET_RD_RMON_R_P_GTE2048_COUNT(base) ((ENET_RMON_R_P_GTE2048_REG(base) & ENET_RMON_R_P_GTE2048_COUNT_MASK) >> ENET_RMON_R_P_GTE2048_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P_GTE2048_COUNT(base) (ENET_RD_RMON_R_P_GTE2048_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OCTETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_OCTETS(base) (ENET_RMON_R_OCTETS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counter increments if a frame with invalid or missing SFD character is
+ * detected and has been dropped. None of the other counters increments if this counter
+ * increments.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_DROP register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_DROP(base) (ENET_IEEE_R_DROP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_DROP bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field. */
+#define ENET_RD_IEEE_R_DROP_COUNT(base) ((ENET_IEEE_R_DROP_REG(base) & ENET_IEEE_R_DROP_COUNT_MASK) >> ENET_IEEE_R_DROP_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_DROP_COUNT(base) (ENET_RD_IEEE_R_DROP_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_FRAME_OK(base) (ENET_IEEE_R_FRAME_OK_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field. */
+#define ENET_RD_IEEE_R_FRAME_OK_COUNT(base) ((ENET_IEEE_R_FRAME_OK_REG(base) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) >> ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_FRAME_OK_COUNT(base) (ENET_RD_IEEE_R_FRAME_OK_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_CRC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_CRC(base) (ENET_IEEE_R_CRC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_CRC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field. */
+#define ENET_RD_IEEE_R_CRC_COUNT(base) ((ENET_IEEE_R_CRC_REG(base) & ENET_IEEE_R_CRC_COUNT_MASK) >> ENET_IEEE_R_CRC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_CRC_COUNT(base) (ENET_RD_IEEE_R_CRC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_ALIGN(base) (ENET_IEEE_R_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field. */
+#define ENET_RD_IEEE_R_ALIGN_COUNT(base) ((ENET_IEEE_R_ALIGN_REG(base) & ENET_IEEE_R_ALIGN_COUNT_MASK) >> ENET_IEEE_R_ALIGN_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_ALIGN_COUNT(base) (ENET_RD_IEEE_R_ALIGN_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_MACERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_MACERR(base) (ENET_IEEE_R_MACERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field. */
+#define ENET_RD_IEEE_R_MACERR_COUNT(base) ((ENET_IEEE_R_MACERR_REG(base) & ENET_IEEE_R_MACERR_COUNT_MASK) >> ENET_IEEE_R_MACERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_MACERR_COUNT(base) (ENET_RD_IEEE_R_MACERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_FDXFC(base) (ENET_IEEE_R_FDXFC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field. */
+#define ENET_RD_IEEE_R_FDXFC_COUNT(base) ((ENET_IEEE_R_FDXFC_REG(base) & ENET_IEEE_R_FDXFC_COUNT_MASK) >> ENET_IEEE_R_FDXFC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_FDXFC_COUNT(base) (ENET_RD_IEEE_R_FDXFC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_OCTETS_OK(base) (ENET_IEEE_R_OCTETS_OK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATCR - Adjustable Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATCR - Adjustable Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * ATCR command fields can trigger the corresponding events directly. It is not
+ * necessary to preserve any of the configuration fields when a command field is
+ * set in the register, that is, no read-modify-write is required. The fields are
+ * automatically cleared after the command completes.
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATCR register
+ */
+/*@{*/
+#define ENET_RD_ATCR(base)       (ENET_ATCR_REG(base))
+#define ENET_WR_ATCR(base, value) (ENET_ATCR_REG(base) = (value))
+#define ENET_RMW_ATCR(base, mask, value) (ENET_WR_ATCR(base, (ENET_RD_ATCR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) |  (value)))
+#define ENET_CLR_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) & ~(value)))
+#define ENET_TOG_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATCR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCR, field EN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer stops at the current value.
+ * - 0b1 - The timer starts incrementing.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_EN field. */
+#define ENET_RD_ATCR_EN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_EN_MASK) >> ENET_ATCR_EN_SHIFT)
+#define ENET_BRD_ATCR_EN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_EN_SHIFT))
+
+/*! @brief Set the EN field to a new value. */
+#define ENET_WR_ATCR_EN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_EN_MASK, ENET_ATCR_EN(value)))
+#define ENET_BWR_ATCR_EN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field OFFEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - The timer can be reset to zero when the given offset time is reached
+ *     (offset event). The field is cleared when the offset event is reached, so
+ *     no further event occurs until the field is set again. The timer offset
+ *     value must be set before setting this field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_OFFEN field. */
+#define ENET_RD_ATCR_OFFEN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_OFFEN_MASK) >> ENET_ATCR_OFFEN_SHIFT)
+#define ENET_BRD_ATCR_OFFEN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFEN_SHIFT))
+
+/*! @brief Set the OFFEN field to a new value. */
+#define ENET_WR_ATCR_OFFEN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_OFFEN_MASK, ENET_ATCR_OFFEN(value)))
+#define ENET_BWR_ATCR_OFFEN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field OFFRST[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer is not affected and no action occurs, besides clearing
+ *     OFFEN, when the offset is reached.
+ * - 0b1 - If OFFEN is set, the timer resets to zero when the offset setting is
+ *     reached. The offset event does not cause a timer interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_OFFRST field. */
+#define ENET_RD_ATCR_OFFRST(base) ((ENET_ATCR_REG(base) & ENET_ATCR_OFFRST_MASK) >> ENET_ATCR_OFFRST_SHIFT)
+#define ENET_BRD_ATCR_OFFRST(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFRST_SHIFT))
+
+/*! @brief Set the OFFRST field to a new value. */
+#define ENET_WR_ATCR_OFFRST(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_OFFRST_MASK, ENET_ATCR_OFFRST(value)))
+#define ENET_BWR_ATCR_OFFRST(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field PEREN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the
+ *     event signal output is asserted when the timer wraps around according to the
+ *     periodic setting ATPER. The timer period value must be set before setting
+ *     this bit. Not all devices contain the event signal output. See the chip
+ *     configuration details.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_PEREN field. */
+#define ENET_RD_ATCR_PEREN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_PEREN_MASK) >> ENET_ATCR_PEREN_SHIFT)
+#define ENET_BRD_ATCR_PEREN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PEREN_SHIFT))
+
+/*! @brief Set the PEREN field to a new value. */
+#define ENET_WR_ATCR_PEREN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_PEREN_MASK, ENET_ATCR_PEREN(value)))
+#define ENET_BWR_ATCR_PEREN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field PINPER[7] (RW)
+ *
+ * Enables event signal output assertion on period event. Not all devices
+ * contain the event signal output. See the chip configuration details.
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - Enable.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_PINPER field. */
+#define ENET_RD_ATCR_PINPER(base) ((ENET_ATCR_REG(base) & ENET_ATCR_PINPER_MASK) >> ENET_ATCR_PINPER_SHIFT)
+#define ENET_BRD_ATCR_PINPER(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PINPER_SHIFT))
+
+/*! @brief Set the PINPER field to a new value. */
+#define ENET_WR_ATCR_PINPER(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_PINPER_MASK, ENET_ATCR_PINPER(value)))
+#define ENET_BWR_ATCR_PINPER(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PINPER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field RESTART[9] (RW)
+ *
+ * Resets the timer to zero. This has no effect on the counter enable. If the
+ * counter is enabled when this field is set, the timer is reset to zero and starts
+ * counting from there. When set, all other fields are ignored during a write.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_RESTART field. */
+#define ENET_RD_ATCR_RESTART(base) ((ENET_ATCR_REG(base) & ENET_ATCR_RESTART_MASK) >> ENET_ATCR_RESTART_SHIFT)
+#define ENET_BRD_ATCR_RESTART(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_RESTART_SHIFT))
+
+/*! @brief Set the RESTART field to a new value. */
+#define ENET_WR_ATCR_RESTART(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_RESTART_MASK, ENET_ATCR_RESTART(value)))
+#define ENET_BWR_ATCR_RESTART(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_RESTART_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field CAPTURE[11] (RW)
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - The current time is captured and can be read from the ATVR register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_CAPTURE field. */
+#define ENET_RD_ATCR_CAPTURE(base) ((ENET_ATCR_REG(base) & ENET_ATCR_CAPTURE_MASK) >> ENET_ATCR_CAPTURE_SHIFT)
+#define ENET_BRD_ATCR_CAPTURE(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_CAPTURE_SHIFT))
+
+/*! @brief Set the CAPTURE field to a new value. */
+#define ENET_WR_ATCR_CAPTURE(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_CAPTURE_MASK, ENET_ATCR_CAPTURE(value)))
+#define ENET_BWR_ATCR_CAPTURE(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_CAPTURE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field SLAVE[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer is active and all configuration fields in this register are
+ *     relevant.
+ * - 0b1 - The internal timer is disabled and the externally provided timer
+ *     value is used. All other fields, except CAPTURE, in this register have no
+ *     effect. CAPTURE can still be used to capture the current timer value.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_SLAVE field. */
+#define ENET_RD_ATCR_SLAVE(base) ((ENET_ATCR_REG(base) & ENET_ATCR_SLAVE_MASK) >> ENET_ATCR_SLAVE_SHIFT)
+#define ENET_BRD_ATCR_SLAVE(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_SLAVE_SHIFT))
+
+/*! @brief Set the SLAVE field to a new value. */
+#define ENET_WR_ATCR_SLAVE(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_SLAVE_MASK, ENET_ATCR_SLAVE(value)))
+#define ENET_BWR_ATCR_SLAVE(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_SLAVE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATVR - Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATVR - Timer Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATVR register
+ */
+/*@{*/
+#define ENET_RD_ATVR(base)       (ENET_ATVR_REG(base))
+#define ENET_WR_ATVR(base, value) (ENET_ATVR_REG(base) = (value))
+#define ENET_RMW_ATVR(base, mask, value) (ENET_WR_ATVR(base, (ENET_RD_ATVR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) |  (value)))
+#define ENET_CLR_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) & ~(value)))
+#define ENET_TOG_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATOFF - Timer Offset Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATOFF - Timer Offset Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATOFF register
+ */
+/*@{*/
+#define ENET_RD_ATOFF(base)      (ENET_ATOFF_REG(base))
+#define ENET_WR_ATOFF(base, value) (ENET_ATOFF_REG(base) = (value))
+#define ENET_RMW_ATOFF(base, mask, value) (ENET_WR_ATOFF(base, (ENET_RD_ATOFF(base) & ~(mask)) | (value)))
+#define ENET_SET_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) |  (value)))
+#define ENET_CLR_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) & ~(value)))
+#define ENET_TOG_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATPER - Timer Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATPER - Timer Period Register (RW)
+ *
+ * Reset value: 0x3B9ACA00U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATPER register
+ */
+/*@{*/
+#define ENET_RD_ATPER(base)      (ENET_ATPER_REG(base))
+#define ENET_WR_ATPER(base, value) (ENET_ATPER_REG(base) = (value))
+#define ENET_RMW_ATPER(base, mask, value) (ENET_WR_ATPER(base, (ENET_RD_ATPER(base) & ~(mask)) | (value)))
+#define ENET_SET_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) |  (value)))
+#define ENET_CLR_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) & ~(value)))
+#define ENET_TOG_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATCOR - Timer Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATCOR - Timer Correction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATCOR register
+ */
+/*@{*/
+#define ENET_RD_ATCOR(base)      (ENET_ATCOR_REG(base))
+#define ENET_WR_ATCOR(base, value) (ENET_ATCOR_REG(base) = (value))
+#define ENET_RMW_ATCOR(base, mask, value) (ENET_WR_ATCOR(base, (ENET_RD_ATCOR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) |  (value)))
+#define ENET_CLR_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) & ~(value)))
+#define ENET_TOG_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATCOR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCOR, field COR[30:0] (RW)
+ *
+ * Defines after how many timer clock cycles (ts_clk) the correction counter
+ * should be reset and trigger a correction increment on the timer. The amount of
+ * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
+ * counter and no corrections occur. This value is given in clock cycles, not in
+ * nanoseconds as all other values.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCOR_COR field. */
+#define ENET_RD_ATCOR_COR(base) ((ENET_ATCOR_REG(base) & ENET_ATCOR_COR_MASK) >> ENET_ATCOR_COR_SHIFT)
+#define ENET_BRD_ATCOR_COR(base) (ENET_RD_ATCOR_COR(base))
+
+/*! @brief Set the COR field to a new value. */
+#define ENET_WR_ATCOR_COR(base, value) (ENET_RMW_ATCOR(base, ENET_ATCOR_COR_MASK, ENET_ATCOR_COR(value)))
+#define ENET_BWR_ATCOR_COR(base, value) (ENET_WR_ATCOR_COR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATINC - Time-Stamping Clock Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATINC - Time-Stamping Clock Period Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATINC register
+ */
+/*@{*/
+#define ENET_RD_ATINC(base)      (ENET_ATINC_REG(base))
+#define ENET_WR_ATINC(base, value) (ENET_ATINC_REG(base) = (value))
+#define ENET_RMW_ATINC(base, mask, value) (ENET_WR_ATINC(base, (ENET_RD_ATINC(base) & ~(mask)) | (value)))
+#define ENET_SET_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) |  (value)))
+#define ENET_CLR_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) & ~(value)))
+#define ENET_TOG_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATINC bitfields
+ */
+
+/*!
+ * @name Register ENET_ATINC, field INC[6:0] (RW)
+ *
+ * The timer increments by this amount each clock cycle. For example, set to 10
+ * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
+ * that is an integer fraction of the period set in ATPER.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATINC_INC field. */
+#define ENET_RD_ATINC_INC(base) ((ENET_ATINC_REG(base) & ENET_ATINC_INC_MASK) >> ENET_ATINC_INC_SHIFT)
+#define ENET_BRD_ATINC_INC(base) (ENET_RD_ATINC_INC(base))
+
+/*! @brief Set the INC field to a new value. */
+#define ENET_WR_ATINC_INC(base, value) (ENET_RMW_ATINC(base, ENET_ATINC_INC_MASK, ENET_ATINC_INC(value)))
+#define ENET_BWR_ATINC_INC(base, value) (ENET_WR_ATINC_INC(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
+ *
+ * This value is added every time the correction timer expires (every clock
+ * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
+ * than INC speeds up the timer.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATINC_INC_CORR field. */
+#define ENET_RD_ATINC_INC_CORR(base) ((ENET_ATINC_REG(base) & ENET_ATINC_INC_CORR_MASK) >> ENET_ATINC_INC_CORR_SHIFT)
+#define ENET_BRD_ATINC_INC_CORR(base) (ENET_RD_ATINC_INC_CORR(base))
+
+/*! @brief Set the INC_CORR field to a new value. */
+#define ENET_WR_ATINC_INC_CORR(base, value) (ENET_RMW_ATINC(base, ENET_ATINC_INC_CORR_MASK, ENET_ATINC_INC_CORR(value)))
+#define ENET_BWR_ATINC_INC_CORR(base, value) (ENET_WR_ATINC_INC_CORR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATSTMP register
+ */
+/*@{*/
+#define ENET_RD_ATSTMP(base)     (ENET_ATSTMP_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TGSR - Timer Global Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TGSR - Timer Global Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TGSR register
+ */
+/*@{*/
+#define ENET_RD_TGSR(base)       (ENET_TGSR_REG(base))
+#define ENET_WR_TGSR(base, value) (ENET_TGSR_REG(base) = (value))
+#define ENET_RMW_TGSR(base, mask, value) (ENET_WR_TGSR(base, (ENET_RD_TGSR(base) & ~(mask)) | (value)))
+#define ENET_SET_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) |  (value)))
+#define ENET_CLR_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) & ~(value)))
+#define ENET_TOG_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TGSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TGSR, field TF0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 0 is clear
+ * - 0b1 - Timer Flag for Channel 0 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF0 field. */
+#define ENET_RD_TGSR_TF0(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF0_MASK) >> ENET_TGSR_TF0_SHIFT)
+#define ENET_BRD_TGSR_TF0(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF0_SHIFT))
+
+/*! @brief Set the TF0 field to a new value. */
+#define ENET_WR_TGSR_TF0(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF2_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF0(value)))
+#define ENET_BWR_TGSR_TF0(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 1 is clear
+ * - 0b1 - Timer Flag for Channel 1 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF1 field. */
+#define ENET_RD_TGSR_TF1(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF1_MASK) >> ENET_TGSR_TF1_SHIFT)
+#define ENET_BRD_TGSR_TF1(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF1_SHIFT))
+
+/*! @brief Set the TF1 field to a new value. */
+#define ENET_WR_TGSR_TF1(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF1_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF2_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF1(value)))
+#define ENET_BWR_TGSR_TF1(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 2 is clear
+ * - 0b1 - Timer Flag for Channel 2 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF2 field. */
+#define ENET_RD_TGSR_TF2(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF2_MASK) >> ENET_TGSR_TF2_SHIFT)
+#define ENET_BRD_TGSR_TF2(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF2_SHIFT))
+
+/*! @brief Set the TF2 field to a new value. */
+#define ENET_WR_TGSR_TF2(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF2_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF2(value)))
+#define ENET_BWR_TGSR_TF2(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 3 is clear
+ * - 0b1 - Timer Flag for Channel 3 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF3 field. */
+#define ENET_RD_TGSR_TF3(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF3_MASK) >> ENET_TGSR_TF3_SHIFT)
+#define ENET_BRD_TGSR_TF3(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF3_SHIFT))
+
+/*! @brief Set the TF3 field to a new value. */
+#define ENET_WR_TGSR_TF3(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF3_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF2_MASK), ENET_TGSR_TF3(value)))
+#define ENET_BWR_TGSR_TF3(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF3_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCSR - Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCSR - Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCSR register
+ */
+/*@{*/
+#define ENET_RD_TCSR(base, index) (ENET_TCSR_REG(base, index))
+#define ENET_WR_TCSR(base, index, value) (ENET_TCSR_REG(base, index) = (value))
+#define ENET_RMW_TCSR(base, index, mask, value) (ENET_WR_TCSR(base, index, (ENET_RD_TCSR(base, index) & ~(mask)) | (value)))
+#define ENET_SET_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) |  (value)))
+#define ENET_CLR_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) & ~(value)))
+#define ENET_TOG_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TCSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCSR, field TDRE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA request is disabled
+ * - 0b1 - DMA request is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TDRE field. */
+#define ENET_RD_TCSR_TDRE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TDRE_MASK) >> ENET_TCSR_TDRE_SHIFT)
+#define ENET_BRD_TCSR_TDRE(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TDRE_SHIFT))
+
+/*! @brief Set the TDRE field to a new value. */
+#define ENET_WR_TCSR_TDRE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TDRE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TDRE(value)))
+#define ENET_BWR_TCSR_TDRE(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TDRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TMODE[5:2] (RW)
+ *
+ * Updating the Timer Mode field takes a few cycles to register because it is
+ * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
+ * from the 1588 clock domain. When changing Timer Mode, always disable the
+ * channel and read this register to verify the channel is disabled first.
+ *
+ * Values:
+ * - 0b0000 - Timer Channel is disabled.
+ * - 0b0001 - Timer Channel is configured for Input Capture on rising edge
+ * - 0b0010 - Timer Channel is configured for Input Capture on falling edge
+ * - 0b0011 - Timer Channel is configured for Input Capture on both edges
+ * - 0b0100 - Timer Channel is configured for Output Compare - software only
+ * - 0b0101 - Timer Channel is configured for Output Compare - toggle output on
+ *     compare
+ * - 0b0110 - Timer Channel is configured for Output Compare - clear output on
+ *     compare
+ * - 0b0111 - Timer Channel is configured for Output Compare - set output on
+ *     compare
+ * - 0b1000 - Reserved
+ * - 0b1010 - Timer Channel is configured for Output Compare - clear output on
+ *     compare, set output on overflow
+ * - 0b10x1 - Timer Channel is configured for Output Compare - set output on
+ *     compare, clear output on overflow
+ * - 0b1100 - Reserved
+ * - 0b1110 - Timer Channel is configured for Output Compare - pulse output low
+ *     on compare for one 1588 clock cycle
+ * - 0b1111 - Timer Channel is configured for Output Compare - pulse output high
+ *     on compare for one 1588 clock cycle
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TMODE field. */
+#define ENET_RD_TCSR_TMODE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TMODE_MASK) >> ENET_TCSR_TMODE_SHIFT)
+#define ENET_BRD_TCSR_TMODE(base, index) (ENET_RD_TCSR_TMODE(base, index))
+
+/*! @brief Set the TMODE field to a new value. */
+#define ENET_WR_TCSR_TMODE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TMODE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TMODE(value)))
+#define ENET_BWR_TCSR_TMODE(base, index, value) (ENET_WR_TCSR_TMODE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TIE[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled
+ * - 0b1 - Interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TIE field. */
+#define ENET_RD_TCSR_TIE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TIE_MASK) >> ENET_TCSR_TIE_SHIFT)
+#define ENET_BRD_TCSR_TIE(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define ENET_WR_TCSR_TIE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TIE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TIE(value)))
+#define ENET_BWR_TCSR_TIE(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TF[7] (W1C)
+ *
+ * Sets when input capture or output compare occurs. This flag is double
+ * buffered between the module clock and 1588 clock domains. When this field is 1, it
+ * can be cleared to 0 by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - Input Capture or Output Compare has not occurred
+ * - 0b1 - Input Capture or Output Compare has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TF field. */
+#define ENET_RD_TCSR_TF(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TF_MASK) >> ENET_TCSR_TF_SHIFT)
+#define ENET_BRD_TCSR_TF(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TF_SHIFT))
+
+/*! @brief Set the TF field to a new value. */
+#define ENET_WR_TCSR_TF(base, index, value) (ENET_RMW_TCSR(base, index, ENET_TCSR_TF_MASK, ENET_TCSR_TF(value)))
+#define ENET_BWR_TCSR_TF(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCCR - Timer Compare Capture Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCCR - Timer Compare Capture Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCCR register
+ */
+/*@{*/
+#define ENET_RD_TCCR(base, index) (ENET_TCCR_REG(base, index))
+#define ENET_WR_TCCR(base, index, value) (ENET_TCCR_REG(base, index) = (value))
+#define ENET_RMW_TCCR(base, index, mask, value) (ENET_WR_TCCR(base, index, (ENET_RD_TCCR(base, index) & ~(mask)) | (value)))
+#define ENET_SET_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) |  (value)))
+#define ENET_CLR_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) & ~(value)))
+#define ENET_TOG_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 EWM
+ *
+ * External Watchdog Monitor
+ *
+ * Registers defined in this header file:
+ * - EWM_CTRL - Control Register
+ * - EWM_SERV - Service Register
+ * - EWM_CMPL - Compare Low Register
+ * - EWM_CMPH - Compare High Register
+ */
+
+#define EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
+#define EWM_IDX (0U) /*!< Instance number for EWM. */
+
+/*******************************************************************************
+ * EWM_CTRL - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CTRL - Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
+ * written once after a CPU reset. Modifying these bits more than once, generates
+ * a bus transfer error.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CTRL register
+ */
+/*@{*/
+#define EWM_RD_CTRL(base)        (EWM_CTRL_REG(base))
+#define EWM_WR_CTRL(base, value) (EWM_CTRL_REG(base) = (value))
+#define EWM_RMW_CTRL(base, mask, value) (EWM_WR_CTRL(base, (EWM_RD_CTRL(base) & ~(mask)) | (value)))
+#define EWM_SET_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) |  (value)))
+#define EWM_CLR_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) & ~(value)))
+#define EWM_TOG_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual EWM_CTRL bitfields
+ */
+
+/*!
+ * @name Register EWM_CTRL, field EWMEN[0] (RW)
+ *
+ * This bit when set, enables the EWM module. This resets the EWM counter to
+ * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
+ * therefore it cannot be enabled until a reset occurs, due to the write-once
+ * nature of this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_EWMEN field. */
+#define EWM_RD_CTRL_EWMEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_EWMEN_MASK) >> EWM_CTRL_EWMEN_SHIFT)
+#define EWM_BRD_CTRL_EWMEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_EWMEN_SHIFT))
+
+/*! @brief Set the EWMEN field to a new value. */
+#define EWM_WR_CTRL_EWMEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_EWMEN_MASK, EWM_CTRL_EWMEN(value)))
+#define EWM_BWR_CTRL_EWMEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_EWMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field ASSIN[1] (RW)
+ *
+ * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
+ * inverts the assert state to a logic one.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_ASSIN field. */
+#define EWM_RD_CTRL_ASSIN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_ASSIN_MASK) >> EWM_CTRL_ASSIN_SHIFT)
+#define EWM_BRD_CTRL_ASSIN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_ASSIN_SHIFT))
+
+/*! @brief Set the ASSIN field to a new value. */
+#define EWM_WR_CTRL_ASSIN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_ASSIN_MASK, EWM_CTRL_ASSIN(value)))
+#define EWM_BWR_CTRL_ASSIN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_ASSIN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field INEN[2] (RW)
+ *
+ * This bit when set, enables the EWM_in port.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_INEN field. */
+#define EWM_RD_CTRL_INEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_INEN_MASK) >> EWM_CTRL_INEN_SHIFT)
+#define EWM_BRD_CTRL_INEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INEN_SHIFT))
+
+/*! @brief Set the INEN field to a new value. */
+#define EWM_WR_CTRL_INEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_INEN_MASK, EWM_CTRL_INEN(value)))
+#define EWM_BWR_CTRL_INEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field INTEN[3] (RW)
+ *
+ * This bit when set and EWM_out is asserted, an interrupt request is generated.
+ * To de-assert interrupt request, user should clear this bit by writing 0.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_INTEN field. */
+#define EWM_RD_CTRL_INTEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_INTEN_MASK) >> EWM_CTRL_INTEN_SHIFT)
+#define EWM_BRD_CTRL_INTEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INTEN_SHIFT))
+
+/*! @brief Set the INTEN field to a new value. */
+#define EWM_WR_CTRL_INTEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_INTEN_MASK, EWM_CTRL_INTEN(value)))
+#define EWM_BWR_CTRL_INTEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INTEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_SERV - Service Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_SERV - Service Register (WORZ)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERV register provides the interface from the CPU to the EWM module. It
+ * is write-only and reads of this register return zero.
+ */
+/*!
+ * @name Constants and macros for entire EWM_SERV register
+ */
+/*@{*/
+#define EWM_RD_SERV(base)        (EWM_SERV_REG(base))
+#define EWM_WR_SERV(base, value) (EWM_SERV_REG(base) = (value))
+#define EWM_RMW_SERV(base, mask, value) (EWM_WR_SERV(base, (EWM_RD_SERV(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_CMPL - Compare Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CMPL - Compare Low Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CMPL register is reset to zero after a CPU reset. This provides no
+ * minimum time for the CPU to service the EWM counter. This register can be written
+ * only once after a CPU reset. Writing this register more than once generates a
+ * bus transfer error.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CMPL register
+ */
+/*@{*/
+#define EWM_RD_CMPL(base)        (EWM_CMPL_REG(base))
+#define EWM_WR_CMPL(base, value) (EWM_CMPL_REG(base) = (value))
+#define EWM_RMW_CMPL(base, mask, value) (EWM_WR_CMPL(base, (EWM_RD_CMPL(base) & ~(mask)) | (value)))
+#define EWM_SET_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) |  (value)))
+#define EWM_CLR_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) & ~(value)))
+#define EWM_TOG_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_CMPH - Compare High Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CMPH - Compare High Register (RW)
+ *
+ * Reset value: 0xFFU
+ *
+ * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
+ * of 256 clocks time, for the CPU to service the EWM counter. This register can
+ * be written only once after a CPU reset. Writing this register more than once
+ * generates a bus transfer error. The valid values for CMPH are up to 0xFE
+ * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
+ * if EWM counter is greater than CMPH.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CMPH register
+ */
+/*@{*/
+#define EWM_RD_CMPH(base)        (EWM_CMPH_REG(base))
+#define EWM_WR_CMPH(base, value) (EWM_CMPH_REG(base) = (value))
+#define EWM_RMW_CMPH(base, mask, value) (EWM_WR_CMPH(base, (EWM_RD_CMPH(base) & ~(mask)) | (value)))
+#define EWM_SET_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) |  (value)))
+#define EWM_CLR_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) & ~(value)))
+#define EWM_TOG_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FB
+ *
+ * FlexBus external bus interface
+ *
+ * Registers defined in this header file:
+ * - FB_CSAR - Chip Select Address Register
+ * - FB_CSMR - Chip Select Mask Register
+ * - FB_CSCR - Chip Select Control Register
+ * - FB_CSPMCR - Chip Select port Multiplexing Control Register
+ */
+
+#define FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
+#define FB_IDX (0U) /*!< Instance number for FB. */
+
+/*******************************************************************************
+ * FB_CSAR - Chip Select Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSAR - Chip Select Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the associated chip-select's base address.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSAR register
+ */
+/*@{*/
+#define FB_RD_CSAR(base, index)  (FB_CSAR_REG(base, index))
+#define FB_WR_CSAR(base, index, value) (FB_CSAR_REG(base, index) = (value))
+#define FB_RMW_CSAR(base, index, mask, value) (FB_WR_CSAR(base, index, (FB_RD_CSAR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) |  (value)))
+#define FB_CLR_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) & ~(value)))
+#define FB_TOG_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSAR bitfields
+ */
+
+/*!
+ * @name Register FB_CSAR, field BA[31:16] (RW)
+ *
+ * Defines the base address for memory dedicated to the associated chip-select.
+ * BA is compared to bits 31-16 on the internal address bus to determine if the
+ * associated chip-select's memory is being accessed. Because the FlexBus module
+ * is one of the slaves connected to the crossbar switch, it is only accessible
+ * within a certain memory range. See the chip memory map for the applicable
+ * FlexBus "expansion" address range for which the chip-selects can be active. Set the
+ * CSARn and CSMRn registers appropriately before accessing this region.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSAR_BA field. */
+#define FB_RD_CSAR_BA(base, index) ((FB_CSAR_REG(base, index) & FB_CSAR_BA_MASK) >> FB_CSAR_BA_SHIFT)
+#define FB_BRD_CSAR_BA(base, index) (FB_RD_CSAR_BA(base, index))
+
+/*! @brief Set the BA field to a new value. */
+#define FB_WR_CSAR_BA(base, index, value) (FB_RMW_CSAR(base, index, FB_CSAR_BA_MASK, FB_CSAR_BA(value)))
+#define FB_BWR_CSAR_BA(base, index, value) (FB_WR_CSAR_BA(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSMR - Chip Select Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSMR - Chip Select Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the address mask and allowable access types for the associated
+ * chip-select.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSMR register
+ */
+/*@{*/
+#define FB_RD_CSMR(base, index)  (FB_CSMR_REG(base, index))
+#define FB_WR_CSMR(base, index, value) (FB_CSMR_REG(base, index) = (value))
+#define FB_RMW_CSMR(base, index, mask, value) (FB_WR_CSMR(base, index, (FB_RD_CSMR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) |  (value)))
+#define FB_CLR_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) & ~(value)))
+#define FB_TOG_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSMR bitfields
+ */
+
+/*!
+ * @name Register FB_CSMR, field V[0] (RW)
+ *
+ * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
+ * Programmed chip-selects do not assert until the V bit is 1b (except for
+ * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
+ * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
+ * select initialization sequence to allow other chip selects to function as
+ * programmed.
+ *
+ * Values:
+ * - 0b0 - Chip-select is invalid.
+ * - 0b1 - Chip-select is valid.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_V field. */
+#define FB_RD_CSMR_V(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_V_MASK) >> FB_CSMR_V_SHIFT)
+#define FB_BRD_CSMR_V(base, index) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_V_SHIFT))
+
+/*! @brief Set the V field to a new value. */
+#define FB_WR_CSMR_V(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_V_MASK, FB_CSMR_V(value)))
+#define FB_BWR_CSMR_V(base, index, value) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_V_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSMR, field WP[8] (RW)
+ *
+ * Controls write accesses to the address range in the corresponding CSAR.
+ *
+ * Values:
+ * - 0b0 - Write accesses are allowed.
+ * - 0b1 - Write accesses are not allowed. Attempting to write to the range of
+ *     addresses for which the WP bit is set results in a bus error termination of
+ *     the internal cycle and no external cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_WP field. */
+#define FB_RD_CSMR_WP(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_WP_MASK) >> FB_CSMR_WP_SHIFT)
+#define FB_BRD_CSMR_WP(base, index) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_WP_SHIFT))
+
+/*! @brief Set the WP field to a new value. */
+#define FB_WR_CSMR_WP(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_WP_MASK, FB_CSMR_WP(value)))
+#define FB_BWR_CSMR_WP(base, index, value) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_WP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSMR, field BAM[31:16] (RW)
+ *
+ * Defines the associated chip-select's block size by masking address bits.
+ *
+ * Values:
+ * - 0b0000000000000000 - The corresponding address bit in CSAR is used in the
+ *     chip-select decode.
+ * - 0b0000000000000001 - The corresponding address bit in CSAR is a don't care
+ *     in the chip-select decode.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_BAM field. */
+#define FB_RD_CSMR_BAM(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_BAM_MASK) >> FB_CSMR_BAM_SHIFT)
+#define FB_BRD_CSMR_BAM(base, index) (FB_RD_CSMR_BAM(base, index))
+
+/*! @brief Set the BAM field to a new value. */
+#define FB_WR_CSMR_BAM(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_BAM_MASK, FB_CSMR_BAM(value)))
+#define FB_BWR_CSMR_BAM(base, index, value) (FB_WR_CSMR_BAM(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSCR - Chip Select Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSCR - Chip Select Control Register (RW)
+ *
+ * Reset value: 0x003FFC00U
+ *
+ * Controls the auto-acknowledge, address setup and hold times, port size, burst
+ * capability, and number of wait states for the associated chip select. To
+ * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
+ * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
+ * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
+ * particular chip for information on the exact CSCR0 reset value.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSCR register
+ */
+/*@{*/
+#define FB_RD_CSCR(base, index)  (FB_CSCR_REG(base, index))
+#define FB_WR_CSCR(base, index, value) (FB_CSCR_REG(base, index) = (value))
+#define FB_RMW_CSCR(base, index, mask, value) (FB_WR_CSCR(base, index, (FB_RD_CSCR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) |  (value)))
+#define FB_CLR_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) & ~(value)))
+#define FB_TOG_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSCR, field BSTW[3] (RW)
+ *
+ * Specifies whether burst writes are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0b0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst writes. For example, a 32-bit write to an
+ *     8-bit port takes four byte writes.
+ * - 0b1 - Enabled. Enables burst write of data larger than the specified port
+ *     size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to
+ *     8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BSTW field. */
+#define FB_RD_CSCR_BSTW(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BSTW_MASK) >> FB_CSCR_BSTW_SHIFT)
+#define FB_BRD_CSCR_BSTW(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTW_SHIFT))
+
+/*! @brief Set the BSTW field to a new value. */
+#define FB_WR_CSCR_BSTW(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BSTW_MASK, FB_CSCR_BSTW(value)))
+#define FB_BWR_CSCR_BSTW(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BSTR[4] (RW)
+ *
+ * Specifies whether burst reads are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0b0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst reads. For example, a 32-bit read from an
+ *     8-bit port is broken into four 8-bit reads.
+ * - 0b1 - Enabled. Enables data burst reads larger than the specified port
+ *     size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
+ *     ports, and line reads from 8-, 16-, and 32-bit ports.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BSTR field. */
+#define FB_RD_CSCR_BSTR(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BSTR_MASK) >> FB_CSCR_BSTR_SHIFT)
+#define FB_BRD_CSCR_BSTR(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTR_SHIFT))
+
+/*! @brief Set the BSTR field to a new value. */
+#define FB_WR_CSCR_BSTR(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BSTR_MASK, FB_CSCR_BSTR(value)))
+#define FB_BWR_CSCR_BSTR(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BEM[5] (RW)
+ *
+ * Specifies whether the corresponding FB_BE is asserted for read accesses.
+ * Certain memories have byte enables that must be asserted during reads and writes.
+ * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
+ * of byte enable support for these SRAMs.
+ *
+ * Values:
+ * - 0b0 - FB_BE is asserted for data write only.
+ * - 0b1 - FB_BE is asserted for data read and write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BEM field. */
+#define FB_RD_CSCR_BEM(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BEM_MASK) >> FB_CSCR_BEM_SHIFT)
+#define FB_BRD_CSCR_BEM(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BEM_SHIFT))
+
+/*! @brief Set the BEM field to a new value. */
+#define FB_WR_CSCR_BEM(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BEM_MASK, FB_CSCR_BEM(value)))
+#define FB_BWR_CSCR_BEM(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BEM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field PS[7:6] (RW)
+ *
+ * Specifies the data port width of the associated chip-select, and determines
+ * where data is driven during write cycles and where data is sampled during read
+ * cycles.
+ *
+ * Values:
+ * - 0b00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
+ * - 0b01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24]
+ *     when BLS is 0b, or FB_D[7:0] when BLS is 1b.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_PS field. */
+#define FB_RD_CSCR_PS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_PS_MASK) >> FB_CSCR_PS_SHIFT)
+#define FB_BRD_CSCR_PS(base, index) (FB_RD_CSCR_PS(base, index))
+
+/*! @brief Set the PS field to a new value. */
+#define FB_WR_CSCR_PS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_PS_MASK, FB_CSCR_PS(value)))
+#define FB_BWR_CSCR_PS(base, index, value) (FB_WR_CSCR_PS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field AA[8] (RW)
+ *
+ * Asserts the internal transfer acknowledge for accesses specified by the
+ * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
+ * asserts an external FB_TA before the wait-state countdown asserts the
+ * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
+ * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
+ *
+ * Values:
+ * - 0b0 - Disabled. No internal transfer acknowledge is asserted and the cycle
+ *     is terminated externally.
+ * - 0b1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_AA field. */
+#define FB_RD_CSCR_AA(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_AA_MASK) >> FB_CSCR_AA_SHIFT)
+#define FB_BRD_CSCR_AA(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_AA_SHIFT))
+
+/*! @brief Set the AA field to a new value. */
+#define FB_WR_CSCR_AA(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_AA_MASK, FB_CSCR_AA(value)))
+#define FB_BWR_CSCR_AA(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_AA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BLS[9] (RW)
+ *
+ * Specifies if data on FB_AD appears left-aligned or right-aligned during the
+ * data phase of a FlexBus access.
+ *
+ * Values:
+ * - 0b0 - Not shifted. Data is left-aligned on FB_AD.
+ * - 0b1 - Shifted. Data is right-aligned on FB_AD.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BLS field. */
+#define FB_RD_CSCR_BLS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BLS_MASK) >> FB_CSCR_BLS_SHIFT)
+#define FB_BRD_CSCR_BLS(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BLS_SHIFT))
+
+/*! @brief Set the BLS field to a new value. */
+#define FB_WR_CSCR_BLS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BLS_MASK, FB_CSCR_BLS(value)))
+#define FB_BWR_CSCR_BLS(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field WS[15:10] (RW)
+ *
+ * Specifies the number of wait states inserted after FlexBus asserts the
+ * associated chip-select and before an internal transfer acknowledge is generated (WS
+ * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_WS field. */
+#define FB_RD_CSCR_WS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_WS_MASK) >> FB_CSCR_WS_SHIFT)
+#define FB_BRD_CSCR_WS(base, index) (FB_RD_CSCR_WS(base, index))
+
+/*! @brief Set the WS field to a new value. */
+#define FB_WR_CSCR_WS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_WS_MASK, FB_CSCR_WS(value)))
+#define FB_BWR_CSCR_WS(base, index, value) (FB_WR_CSCR_WS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field WRAH[17:16] (RW)
+ *
+ * Controls the address, data, and attribute hold time after the termination of
+ * a write cycle that hits in the associated chip-select's address space. The
+ * hold time applies only at the end of a transfer. Therefore, during a burst
+ * transfer or a transfer to a port size smaller than the transfer size, the hold time
+ * is only added after the last bus cycle.
+ *
+ * Values:
+ * - 0b00 - 1 cycle (default for all but FB_CS0 )
+ * - 0b01 - 2 cycles
+ * - 0b10 - 3 cycles
+ * - 0b11 - 4 cycles (default for FB_CS0 )
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_WRAH field. */
+#define FB_RD_CSCR_WRAH(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_WRAH_MASK) >> FB_CSCR_WRAH_SHIFT)
+#define FB_BRD_CSCR_WRAH(base, index) (FB_RD_CSCR_WRAH(base, index))
+
+/*! @brief Set the WRAH field to a new value. */
+#define FB_WR_CSCR_WRAH(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_WRAH_MASK, FB_CSCR_WRAH(value)))
+#define FB_BWR_CSCR_WRAH(base, index, value) (FB_WR_CSCR_WRAH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field RDAH[19:18] (RW)
+ *
+ * Controls the address and attribute hold time after the termination during a
+ * read cycle that hits in the associated chip-select's address space. The hold
+ * time applies only at the end of a transfer. Therefore, during a burst transfer
+ * or a transfer to a port size smaller than the transfer size, the hold time is
+ * only added after the last bus cycle. The number of cycles the address and
+ * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
+ *
+ * Values:
+ * - 0b00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
+ * - 0b01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
+ * - 0b10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
+ * - 0b11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_RDAH field. */
+#define FB_RD_CSCR_RDAH(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_RDAH_MASK) >> FB_CSCR_RDAH_SHIFT)
+#define FB_BRD_CSCR_RDAH(base, index) (FB_RD_CSCR_RDAH(base, index))
+
+/*! @brief Set the RDAH field to a new value. */
+#define FB_WR_CSCR_RDAH(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_RDAH_MASK, FB_CSCR_RDAH(value)))
+#define FB_BWR_CSCR_RDAH(base, index, value) (FB_WR_CSCR_RDAH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field ASET[21:20] (RW)
+ *
+ * Controls when the chip-select is asserted with respect to assertion of a
+ * valid address and attributes.
+ *
+ * Values:
+ * - 0b00 - Assert FB_CSn on the first rising clock edge after the address is
+ *     asserted (default for all but FB_CS0 ).
+ * - 0b01 - Assert FB_CSn on the second rising clock edge after the address is
+ *     asserted.
+ * - 0b10 - Assert FB_CSn on the third rising clock edge after the address is
+ *     asserted.
+ * - 0b11 - Assert FB_CSn on the fourth rising clock edge after the address is
+ *     asserted (default for FB_CS0 ).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_ASET field. */
+#define FB_RD_CSCR_ASET(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_ASET_MASK) >> FB_CSCR_ASET_SHIFT)
+#define FB_BRD_CSCR_ASET(base, index) (FB_RD_CSCR_ASET(base, index))
+
+/*! @brief Set the ASET field to a new value. */
+#define FB_WR_CSCR_ASET(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_ASET_MASK, FB_CSCR_ASET(value)))
+#define FB_BWR_CSCR_ASET(base, index, value) (FB_WR_CSCR_ASET(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field EXTS[22] (RW)
+ *
+ * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
+ * /FB_ALE is asserted.
+ *
+ * Values:
+ * - 0b0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
+ * - 0b1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive
+ *     clock edge after FB_CSn asserts.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_EXTS field. */
+#define FB_RD_CSCR_EXTS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_EXTS_MASK) >> FB_CSCR_EXTS_SHIFT)
+#define FB_BRD_CSCR_EXTS(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_EXTS_SHIFT))
+
+/*! @brief Set the EXTS field to a new value. */
+#define FB_WR_CSCR_EXTS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_EXTS_MASK, FB_CSCR_EXTS(value)))
+#define FB_BWR_CSCR_EXTS(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_EXTS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field SWSEN[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled. A number of wait states (specified by WS) are inserted
+ *     before an internal transfer acknowledge is generated for all transfers.
+ * - 0b1 - Enabled. A number of wait states (specified by SWS) are inserted
+ *     before an internal transfer acknowledge is generated for burst transfer
+ *     secondary terminations.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_SWSEN field. */
+#define FB_RD_CSCR_SWSEN(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_SWSEN_MASK) >> FB_CSCR_SWSEN_SHIFT)
+#define FB_BRD_CSCR_SWSEN(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_SWSEN_SHIFT))
+
+/*! @brief Set the SWSEN field to a new value. */
+#define FB_WR_CSCR_SWSEN(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_SWSEN_MASK, FB_CSCR_SWSEN(value)))
+#define FB_BWR_CSCR_SWSEN(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_SWSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field SWS[31:26] (RW)
+ *
+ * Used only when the SWSEN bit is 1b. Specifies the number of wait states
+ * inserted before an internal transfer acknowledge is generated for a burst transfer
+ * (except for the first termination, which is controlled by WS).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_SWS field. */
+#define FB_RD_CSCR_SWS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_SWS_MASK) >> FB_CSCR_SWS_SHIFT)
+#define FB_BRD_CSCR_SWS(base, index) (FB_RD_CSCR_SWS(base, index))
+
+/*! @brief Set the SWS field to a new value. */
+#define FB_WR_CSCR_SWS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_SWS_MASK, FB_CSCR_SWS(value)))
+#define FB_BWR_CSCR_SWS(base, index, value) (FB_WR_CSCR_SWS(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSPMCR - Chip Select port Multiplexing Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
+ * do any of the following: Write to a reserved address Write to a reserved
+ * field in this register, or Access this register using a size other than 32 bits.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSPMCR register
+ */
+/*@{*/
+#define FB_RD_CSPMCR(base)       (FB_CSPMCR_REG(base))
+#define FB_WR_CSPMCR(base, value) (FB_CSPMCR_REG(base) = (value))
+#define FB_RMW_CSPMCR(base, mask, value) (FB_WR_CSPMCR(base, (FB_RD_CSPMCR(base) & ~(mask)) | (value)))
+#define FB_SET_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) |  (value)))
+#define FB_CLR_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) & ~(value)))
+#define FB_TOG_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSPMCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
+ *
+ * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
+ * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
+ * bus hangs during a transfer.
+ *
+ * Values:
+ * - 0b0000 - FB_TA
+ * - 0b0001 - FB_CS3 . You must also write 1b to CSCR[AA].
+ * - 0b0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
+#define FB_RD_CSPMCR_GROUP5(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP5_MASK) >> FB_CSPMCR_GROUP5_SHIFT)
+#define FB_BRD_CSPMCR_GROUP5(base) (FB_RD_CSPMCR_GROUP5(base))
+
+/*! @brief Set the GROUP5 field to a new value. */
+#define FB_WR_CSPMCR_GROUP5(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP5_MASK, FB_CSPMCR_GROUP5(value)))
+#define FB_BWR_CSPMCR_GROUP5(base, value) (FB_WR_CSPMCR_GROUP5(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
+ *
+ * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_TBST
+ * - 0b0001 - FB_CS2
+ * - 0b0010 - FB_BE_15_8
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
+#define FB_RD_CSPMCR_GROUP4(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP4_MASK) >> FB_CSPMCR_GROUP4_SHIFT)
+#define FB_BRD_CSPMCR_GROUP4(base) (FB_RD_CSPMCR_GROUP4(base))
+
+/*! @brief Set the GROUP4 field to a new value. */
+#define FB_WR_CSPMCR_GROUP4(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP4_MASK, FB_CSPMCR_GROUP4(value)))
+#define FB_BWR_CSPMCR_GROUP4(base, value) (FB_WR_CSPMCR_GROUP4(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
+ *
+ * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_CS5
+ * - 0b0001 - FB_TSIZ1
+ * - 0b0010 - FB_BE_23_16
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
+#define FB_RD_CSPMCR_GROUP3(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP3_MASK) >> FB_CSPMCR_GROUP3_SHIFT)
+#define FB_BRD_CSPMCR_GROUP3(base) (FB_RD_CSPMCR_GROUP3(base))
+
+/*! @brief Set the GROUP3 field to a new value. */
+#define FB_WR_CSPMCR_GROUP3(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP3_MASK, FB_CSPMCR_GROUP3(value)))
+#define FB_BWR_CSPMCR_GROUP3(base, value) (FB_WR_CSPMCR_GROUP3(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
+ *
+ * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_CS4
+ * - 0b0001 - FB_TSIZ0
+ * - 0b0010 - FB_BE_31_24
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
+#define FB_RD_CSPMCR_GROUP2(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP2_MASK) >> FB_CSPMCR_GROUP2_SHIFT)
+#define FB_BRD_CSPMCR_GROUP2(base) (FB_RD_CSPMCR_GROUP2(base))
+
+/*! @brief Set the GROUP2 field to a new value. */
+#define FB_WR_CSPMCR_GROUP2(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP2_MASK, FB_CSPMCR_GROUP2(value)))
+#define FB_BWR_CSPMCR_GROUP2(base, value) (FB_WR_CSPMCR_GROUP2(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
+ *
+ * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
+ *
+ * Values:
+ * - 0b0000 - FB_ALE
+ * - 0b0001 - FB_CS1
+ * - 0b0010 - FB_TS
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
+#define FB_RD_CSPMCR_GROUP1(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP1_MASK) >> FB_CSPMCR_GROUP1_SHIFT)
+#define FB_BRD_CSPMCR_GROUP1(base) (FB_RD_CSPMCR_GROUP1(base))
+
+/*! @brief Set the GROUP1 field to a new value. */
+#define FB_WR_CSPMCR_GROUP1(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP1_MASK, FB_CSPMCR_GROUP1(value)))
+#define FB_BWR_CSPMCR_GROUP1(base, value) (FB_WR_CSPMCR_GROUP1(base, value))
+/*@}*/
+
+/*
+ * MK64F12 FMC
+ *
+ * Flash Memory Controller
+ *
+ * Registers defined in this header file:
+ * - FMC_PFAPR - Flash Access Protection Register
+ * - FMC_PFB0CR - Flash Bank 0 Control Register
+ * - FMC_PFB1CR - Flash Bank 1 Control Register
+ * - FMC_TAGVDW0S - Cache Tag Storage
+ * - FMC_TAGVDW1S - Cache Tag Storage
+ * - FMC_TAGVDW2S - Cache Tag Storage
+ * - FMC_TAGVDW3S - Cache Tag Storage
+ * - FMC_DATA_U - Cache Data Storage (upper word)
+ * - FMC_DATA_L - Cache Data Storage (lower word)
+ */
+
+#define FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */
+#define FMC_IDX (0U) /*!< Instance number for FMC. */
+
+/*******************************************************************************
+ * FMC_PFAPR - Flash Access Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFAPR - Flash Access Protection Register (RW)
+ *
+ * Reset value: 0x00F8003FU
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFAPR register
+ */
+/*@{*/
+#define FMC_RD_PFAPR(base)       (FMC_PFAPR_REG(base))
+#define FMC_WR_PFAPR(base, value) (FMC_PFAPR_REG(base) = (value))
+#define FMC_RMW_PFAPR(base, mask, value) (FMC_WR_PFAPR(base, (FMC_RD_PFAPR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) |  (value)))
+#define FMC_CLR_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) & ~(value)))
+#define FMC_TOG_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFAPR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M0AP field. */
+#define FMC_RD_PFAPR_M0AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M0AP_MASK) >> FMC_PFAPR_M0AP_SHIFT)
+#define FMC_BRD_PFAPR_M0AP(base) (FMC_RD_PFAPR_M0AP(base))
+
+/*! @brief Set the M0AP field to a new value. */
+#define FMC_WR_PFAPR_M0AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M0AP_MASK, FMC_PFAPR_M0AP(value)))
+#define FMC_BWR_PFAPR_M0AP(base, value) (FMC_WR_PFAPR_M0AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M1AP field. */
+#define FMC_RD_PFAPR_M1AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M1AP_MASK) >> FMC_PFAPR_M1AP_SHIFT)
+#define FMC_BRD_PFAPR_M1AP(base) (FMC_RD_PFAPR_M1AP(base))
+
+/*! @brief Set the M1AP field to a new value. */
+#define FMC_WR_PFAPR_M1AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M1AP_MASK, FMC_PFAPR_M1AP(value)))
+#define FMC_BWR_PFAPR_M1AP(base, value) (FMC_WR_PFAPR_M1AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M2AP field. */
+#define FMC_RD_PFAPR_M2AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M2AP_MASK) >> FMC_PFAPR_M2AP_SHIFT)
+#define FMC_BRD_PFAPR_M2AP(base) (FMC_RD_PFAPR_M2AP(base))
+
+/*! @brief Set the M2AP field to a new value. */
+#define FMC_WR_PFAPR_M2AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M2AP_MASK, FMC_PFAPR_M2AP(value)))
+#define FMC_BWR_PFAPR_M2AP(base, value) (FMC_WR_PFAPR_M2AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M3AP field. */
+#define FMC_RD_PFAPR_M3AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M3AP_MASK) >> FMC_PFAPR_M3AP_SHIFT)
+#define FMC_BRD_PFAPR_M3AP(base) (FMC_RD_PFAPR_M3AP(base))
+
+/*! @brief Set the M3AP field to a new value. */
+#define FMC_WR_PFAPR_M3AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M3AP_MASK, FMC_PFAPR_M3AP(value)))
+#define FMC_BWR_PFAPR_M3AP(base, value) (FMC_WR_PFAPR_M3AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M4AP field. */
+#define FMC_RD_PFAPR_M4AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M4AP_MASK) >> FMC_PFAPR_M4AP_SHIFT)
+#define FMC_BRD_PFAPR_M4AP(base) (FMC_RD_PFAPR_M4AP(base))
+
+/*! @brief Set the M4AP field to a new value. */
+#define FMC_WR_PFAPR_M4AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M4AP_MASK, FMC_PFAPR_M4AP(value)))
+#define FMC_BWR_PFAPR_M4AP(base, value) (FMC_WR_PFAPR_M4AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M5AP field. */
+#define FMC_RD_PFAPR_M5AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M5AP_MASK) >> FMC_PFAPR_M5AP_SHIFT)
+#define FMC_BRD_PFAPR_M5AP(base) (FMC_RD_PFAPR_M5AP(base))
+
+/*! @brief Set the M5AP field to a new value. */
+#define FMC_WR_PFAPR_M5AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M5AP_MASK, FMC_PFAPR_M5AP(value)))
+#define FMC_BWR_PFAPR_M5AP(base, value) (FMC_WR_PFAPR_M5AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M6AP field. */
+#define FMC_RD_PFAPR_M6AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M6AP_MASK) >> FMC_PFAPR_M6AP_SHIFT)
+#define FMC_BRD_PFAPR_M6AP(base) (FMC_RD_PFAPR_M6AP(base))
+
+/*! @brief Set the M6AP field to a new value. */
+#define FMC_WR_PFAPR_M6AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M6AP_MASK, FMC_PFAPR_M6AP(value)))
+#define FMC_BWR_PFAPR_M6AP(base, value) (FMC_WR_PFAPR_M6AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master.
+ * - 0b01 - Only read accesses may be performed by this master.
+ * - 0b10 - Only write accesses may be performed by this master.
+ * - 0b11 - Both read and write accesses may be performed by this master.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M7AP field. */
+#define FMC_RD_PFAPR_M7AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M7AP_MASK) >> FMC_PFAPR_M7AP_SHIFT)
+#define FMC_BRD_PFAPR_M7AP(base) (FMC_RD_PFAPR_M7AP(base))
+
+/*! @brief Set the M7AP field to a new value. */
+#define FMC_WR_PFAPR_M7AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M7AP_MASK, FMC_PFAPR_M7AP(value)))
+#define FMC_BWR_PFAPR_M7AP(base, value) (FMC_WR_PFAPR_M7AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M0PFD[16] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M0PFD field. */
+#define FMC_RD_PFAPR_M0PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M0PFD_MASK) >> FMC_PFAPR_M0PFD_SHIFT)
+#define FMC_BRD_PFAPR_M0PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M0PFD_SHIFT))
+
+/*! @brief Set the M0PFD field to a new value. */
+#define FMC_WR_PFAPR_M0PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M0PFD_MASK, FMC_PFAPR_M0PFD(value)))
+#define FMC_BWR_PFAPR_M0PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M0PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M1PFD[17] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M1PFD field. */
+#define FMC_RD_PFAPR_M1PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M1PFD_MASK) >> FMC_PFAPR_M1PFD_SHIFT)
+#define FMC_BRD_PFAPR_M1PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M1PFD_SHIFT))
+
+/*! @brief Set the M1PFD field to a new value. */
+#define FMC_WR_PFAPR_M1PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M1PFD_MASK, FMC_PFAPR_M1PFD(value)))
+#define FMC_BWR_PFAPR_M1PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M1PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M2PFD[18] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M2PFD field. */
+#define FMC_RD_PFAPR_M2PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M2PFD_MASK) >> FMC_PFAPR_M2PFD_SHIFT)
+#define FMC_BRD_PFAPR_M2PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M2PFD_SHIFT))
+
+/*! @brief Set the M2PFD field to a new value. */
+#define FMC_WR_PFAPR_M2PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M2PFD_MASK, FMC_PFAPR_M2PFD(value)))
+#define FMC_BWR_PFAPR_M2PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M2PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M3PFD[19] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M3PFD field. */
+#define FMC_RD_PFAPR_M3PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M3PFD_MASK) >> FMC_PFAPR_M3PFD_SHIFT)
+#define FMC_BRD_PFAPR_M3PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M3PFD_SHIFT))
+
+/*! @brief Set the M3PFD field to a new value. */
+#define FMC_WR_PFAPR_M3PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M3PFD_MASK, FMC_PFAPR_M3PFD(value)))
+#define FMC_BWR_PFAPR_M3PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M3PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M4PFD[20] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M4PFD field. */
+#define FMC_RD_PFAPR_M4PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M4PFD_MASK) >> FMC_PFAPR_M4PFD_SHIFT)
+#define FMC_BRD_PFAPR_M4PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M4PFD_SHIFT))
+
+/*! @brief Set the M4PFD field to a new value. */
+#define FMC_WR_PFAPR_M4PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M4PFD_MASK, FMC_PFAPR_M4PFD(value)))
+#define FMC_BWR_PFAPR_M4PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M4PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M5PFD[21] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M5PFD field. */
+#define FMC_RD_PFAPR_M5PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M5PFD_MASK) >> FMC_PFAPR_M5PFD_SHIFT)
+#define FMC_BRD_PFAPR_M5PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M5PFD_SHIFT))
+
+/*! @brief Set the M5PFD field to a new value. */
+#define FMC_WR_PFAPR_M5PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M5PFD_MASK, FMC_PFAPR_M5PFD(value)))
+#define FMC_BWR_PFAPR_M5PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M5PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M6PFD[22] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M6PFD field. */
+#define FMC_RD_PFAPR_M6PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M6PFD_MASK) >> FMC_PFAPR_M6PFD_SHIFT)
+#define FMC_BRD_PFAPR_M6PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M6PFD_SHIFT))
+
+/*! @brief Set the M6PFD field to a new value. */
+#define FMC_WR_PFAPR_M6PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M6PFD_MASK, FMC_PFAPR_M6PFD(value)))
+#define FMC_BWR_PFAPR_M6PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M6PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M7PFD[23] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M7PFD field. */
+#define FMC_RD_PFAPR_M7PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M7PFD_MASK) >> FMC_PFAPR_M7PFD_SHIFT)
+#define FMC_BRD_PFAPR_M7PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M7PFD_SHIFT))
+
+/*! @brief Set the M7PFD field to a new value. */
+#define FMC_WR_PFAPR_M7PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M7PFD_MASK, FMC_PFAPR_M7PFD(value)))
+#define FMC_BWR_PFAPR_M7PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M7PFD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_PFB0CR - Flash Bank 0 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFB0CR - Flash Bank 0 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFB0CR register
+ */
+/*@{*/
+#define FMC_RD_PFB0CR(base)      (FMC_PFB0CR_REG(base))
+#define FMC_WR_PFB0CR(base, value) (FMC_PFB0CR_REG(base) = (value))
+#define FMC_RMW_PFB0CR(base, mask, value) (FMC_WR_PFB0CR(base, (FMC_RD_PFB0CR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) |  (value)))
+#define FMC_CLR_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) & ~(value)))
+#define FMC_TOG_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFB0CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry page buffer is enabled in response
+ * to flash read accesses. Its operation is independent from bank 1's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0b0 - Single entry buffer is disabled.
+ * - 0b1 - Single entry buffer is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */
+#define FMC_RD_PFB0CR_B0SEBE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0SEBE_MASK) >> FMC_PFB0CR_B0SEBE_SHIFT)
+#define FMC_BRD_PFB0CR_B0SEBE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0SEBE_SHIFT))
+
+/*! @brief Set the B0SEBE field to a new value. */
+#define FMC_WR_PFB0CR_B0SEBE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0SEBE_MASK, FMC_PFB0CR_B0SEBE(value)))
+#define FMC_BWR_PFB0CR_B0SEBE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0SEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to instruction fetches.
+ * - 0b1 - Enable prefetches in response to instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */
+#define FMC_RD_PFB0CR_B0IPE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0IPE_MASK) >> FMC_PFB0CR_B0IPE_SHIFT)
+#define FMC_BRD_PFB0CR_B0IPE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0IPE_SHIFT))
+
+/*! @brief Set the B0IPE field to a new value. */
+#define FMC_WR_PFB0CR_B0IPE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0IPE_MASK, FMC_PFB0CR_B0IPE(value)))
+#define FMC_BWR_PFB0CR_B0IPE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0IPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to data references.
+ * - 0b1 - Enable prefetches in response to data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */
+#define FMC_RD_PFB0CR_B0DPE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0DPE_MASK) >> FMC_PFB0CR_B0DPE_SHIFT)
+#define FMC_BRD_PFB0CR_B0DPE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DPE_SHIFT))
+
+/*! @brief Set the B0DPE field to a new value. */
+#define FMC_WR_PFB0CR_B0DPE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0DPE_MASK, FMC_PFB0CR_B0DPE(value)))
+#define FMC_BWR_PFB0CR_B0DPE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache instruction fetches.
+ * - 0b1 - Cache instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */
+#define FMC_RD_PFB0CR_B0ICE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0ICE_MASK) >> FMC_PFB0CR_B0ICE_SHIFT)
+#define FMC_BRD_PFB0CR_B0ICE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0ICE_SHIFT))
+
+/*! @brief Set the B0ICE field to a new value. */
+#define FMC_WR_PFB0CR_B0ICE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0ICE_MASK, FMC_PFB0CR_B0ICE(value)))
+#define FMC_BWR_PFB0CR_B0ICE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0ICE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache data references.
+ * - 0b1 - Cache data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */
+#define FMC_RD_PFB0CR_B0DCE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0DCE_MASK) >> FMC_PFB0CR_B0DCE_SHIFT)
+#define FMC_BRD_PFB0CR_B0DCE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DCE_SHIFT))
+
+/*! @brief Set the B0DCE field to a new value. */
+#define FMC_WR_PFB0CR_B0DCE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0DCE_MASK, FMC_PFB0CR_B0DCE(value)))
+#define FMC_BWR_PFB0CR_B0DCE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
+ *
+ * This 3-bit field defines the replacement algorithm for accesses that are
+ * cached.
+ *
+ * Values:
+ * - 0b000 - LRU replacement algorithm per set across all four ways
+ * - 0b001 - Reserved
+ * - 0b010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
+ * - 0b011 - Independent LRU with ways [0-2] for ifetches, [3] for data
+ * - 0b1xx - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_CRC field. */
+#define FMC_RD_PFB0CR_CRC(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_CRC_MASK) >> FMC_PFB0CR_CRC_SHIFT)
+#define FMC_BRD_PFB0CR_CRC(base) (FMC_RD_PFB0CR_CRC(base))
+
+/*! @brief Set the CRC field to a new value. */
+#define FMC_WR_PFB0CR_CRC(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CRC_MASK, FMC_PFB0CR_CRC(value)))
+#define FMC_BWR_PFB0CR_CRC(base, value) (FMC_WR_PFB0CR_CRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 0 memory.
+ *
+ * Values:
+ * - 0b00 - 32 bits
+ * - 0b01 - 64 bits
+ * - 0b10 - 128 bits
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0MW field. */
+#define FMC_RD_PFB0CR_B0MW(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0MW_MASK) >> FMC_PFB0CR_B0MW_SHIFT)
+#define FMC_BRD_PFB0CR_B0MW(base) (FMC_RD_PFB0CR_B0MW(base))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
+ *
+ * This bit determines if the FMC's prefetch speculation buffer and the single
+ * entry page buffer are to be invalidated (cleared). When this bit is written,
+ * the speculation buffer and single entry buffer are immediately cleared. This bit
+ * always reads as zero.
+ *
+ * Values:
+ * - 0b0 - Speculation buffer and single entry buffer are not affected.
+ * - 0b1 - Invalidate (clear) speculation buffer and single entry buffer.
+ */
+/*@{*/
+/*! @brief Set the S_B_INV field to a new value. */
+#define FMC_WR_PFB0CR_S_B_INV(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_S_B_INV_MASK, FMC_PFB0CR_S_B_INV(value)))
+#define FMC_BWR_PFB0CR_S_B_INV(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_S_B_INV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
+ *
+ * These bits determine if the given cache way is to be invalidated (cleared).
+ * When a bit within this field is written, the corresponding cache way is
+ * immediately invalidated: the way's tag, data, and valid contents are cleared. This
+ * field always reads as zero. Cache invalidation takes precedence over locking.
+ * The cache is invalidated by system reset. System software is required to
+ * maintain memory coherency when any segment of the flash memory is programmed or
+ * erased. Accordingly, cache invalidations must occur after a programming or erase
+ * event is completed and before the new memory image is accessed. The bit setting
+ * definitions are for each bit in the field.
+ *
+ * Values:
+ * - 0b0000 - No cache way invalidation for the corresponding cache
+ * - 0b0001 - Invalidate cache way for the corresponding cache: clear the tag,
+ *     data, and vld bits of ways selected
+ */
+/*@{*/
+/*! @brief Set the CINV_WAY field to a new value. */
+#define FMC_WR_PFB0CR_CINV_WAY(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY(value)))
+#define FMC_BWR_PFB0CR_CINV_WAY(base, value) (FMC_WR_PFB0CR_CINV_WAY(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
+ *
+ * These bits determine if the given cache way is locked such that its contents
+ * will not be displaced by future misses. The bit setting definitions are for
+ * each bit in the field.
+ *
+ * Values:
+ * - 0b0000 - Cache way is unlocked and may be displaced
+ * - 0b0001 - Cache way is locked and its contents are not displaced
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */
+#define FMC_RD_PFB0CR_CLCK_WAY(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_CLCK_WAY_MASK) >> FMC_PFB0CR_CLCK_WAY_SHIFT)
+#define FMC_BRD_PFB0CR_CLCK_WAY(base) (FMC_RD_PFB0CR_CLCK_WAY(base))
+
+/*! @brief Set the CLCK_WAY field to a new value. */
+#define FMC_WR_PFB0CR_CLCK_WAY(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CLCK_WAY_MASK, FMC_PFB0CR_CLCK_WAY(value)))
+#define FMC_BWR_PFB0CR_CLCK_WAY(base, value) (FMC_WR_PFB0CR_CLCK_WAY(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 0 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */
+#define FMC_RD_PFB0CR_B0RWSC(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0RWSC_MASK) >> FMC_PFB0CR_B0RWSC_SHIFT)
+#define FMC_BRD_PFB0CR_B0RWSC(base) (FMC_RD_PFB0CR_B0RWSC(base))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_PFB1CR - Flash Bank 1 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFB1CR - Flash Bank 1 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ *
+ * This register has a format similar to that for PFB0CR, except it controls the
+ * operation of flash bank 1, and the "global" cache control fields are empty.
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFB1CR register
+ */
+/*@{*/
+#define FMC_RD_PFB1CR(base)      (FMC_PFB1CR_REG(base))
+#define FMC_WR_PFB1CR(base, value) (FMC_PFB1CR_REG(base) = (value))
+#define FMC_RMW_PFB1CR(base, mask, value) (FMC_WR_PFB1CR(base, (FMC_RD_PFB1CR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) |  (value)))
+#define FMC_CLR_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) & ~(value)))
+#define FMC_TOG_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFB1CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry buffer is enabled in response to
+ * flash read accesses. Its operation is independent from bank 0's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0b0 - Single entry buffer is disabled.
+ * - 0b1 - Single entry buffer is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */
+#define FMC_RD_PFB1CR_B1SEBE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1SEBE_MASK) >> FMC_PFB1CR_B1SEBE_SHIFT)
+#define FMC_BRD_PFB1CR_B1SEBE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1SEBE_SHIFT))
+
+/*! @brief Set the B1SEBE field to a new value. */
+#define FMC_WR_PFB1CR_B1SEBE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1SEBE_MASK, FMC_PFB1CR_B1SEBE(value)))
+#define FMC_BWR_PFB1CR_B1SEBE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1SEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to instruction fetches.
+ * - 0b1 - Enable prefetches in response to instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */
+#define FMC_RD_PFB1CR_B1IPE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1IPE_MASK) >> FMC_PFB1CR_B1IPE_SHIFT)
+#define FMC_BRD_PFB1CR_B1IPE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1IPE_SHIFT))
+
+/*! @brief Set the B1IPE field to a new value. */
+#define FMC_WR_PFB1CR_B1IPE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1IPE_MASK, FMC_PFB1CR_B1IPE(value)))
+#define FMC_BWR_PFB1CR_B1IPE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1IPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to data references.
+ * - 0b1 - Enable prefetches in response to data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */
+#define FMC_RD_PFB1CR_B1DPE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1DPE_MASK) >> FMC_PFB1CR_B1DPE_SHIFT)
+#define FMC_BRD_PFB1CR_B1DPE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DPE_SHIFT))
+
+/*! @brief Set the B1DPE field to a new value. */
+#define FMC_WR_PFB1CR_B1DPE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1DPE_MASK, FMC_PFB1CR_B1DPE(value)))
+#define FMC_BWR_PFB1CR_B1DPE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache instruction fetches.
+ * - 0b1 - Cache instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */
+#define FMC_RD_PFB1CR_B1ICE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1ICE_MASK) >> FMC_PFB1CR_B1ICE_SHIFT)
+#define FMC_BRD_PFB1CR_B1ICE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1ICE_SHIFT))
+
+/*! @brief Set the B1ICE field to a new value. */
+#define FMC_WR_PFB1CR_B1ICE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1ICE_MASK, FMC_PFB1CR_B1ICE(value)))
+#define FMC_BWR_PFB1CR_B1ICE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1ICE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache data references.
+ * - 0b1 - Cache data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */
+#define FMC_RD_PFB1CR_B1DCE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1DCE_MASK) >> FMC_PFB1CR_B1DCE_SHIFT)
+#define FMC_BRD_PFB1CR_B1DCE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DCE_SHIFT))
+
+/*! @brief Set the B1DCE field to a new value. */
+#define FMC_WR_PFB1CR_B1DCE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1DCE_MASK, FMC_PFB1CR_B1DCE(value)))
+#define FMC_BWR_PFB1CR_B1DCE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 1 memory.
+ *
+ * Values:
+ * - 0b00 - 32 bits
+ * - 0b01 - 64 bits
+ * - 0b10 - 128 bits
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1MW field. */
+#define FMC_RD_PFB1CR_B1MW(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1MW_MASK) >> FMC_PFB1CR_B1MW_SHIFT)
+#define FMC_BRD_PFB1CR_B1MW(base) (FMC_RD_PFB1CR_B1MW(base))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 1 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */
+#define FMC_RD_PFB1CR_B1RWSC(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1RWSC_MASK) >> FMC_PFB1CR_B1RWSC_SHIFT)
+#define FMC_BRD_PFB1CR_B1RWSC(base) (FMC_RD_PFB1CR_B1RWSC(base))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW0S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW0S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW0S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW0S(base, index) (FMC_TAGVDW0S_REG(base, index))
+#define FMC_WR_TAGVDW0S(base, index, value) (FMC_TAGVDW0S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW0S(base, index, mask, value) (FMC_WR_TAGVDW0S(base, index, (FMC_RD_TAGVDW0S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW0S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW0S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW0S_valid field. */
+#define FMC_RD_TAGVDW0S_valid(base, index) ((FMC_TAGVDW0S_REG(base, index) & FMC_TAGVDW0S_valid_MASK) >> FMC_TAGVDW0S_valid_SHIFT)
+#define FMC_BRD_TAGVDW0S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW0S_REG(base, index), FMC_TAGVDW0S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW0S_valid(base, index, value) (FMC_RMW_TAGVDW0S(base, index, FMC_TAGVDW0S_valid_MASK, FMC_TAGVDW0S_valid(value)))
+#define FMC_BWR_TAGVDW0S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW0S_REG(base, index), FMC_TAGVDW0S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW0S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW0S_tag field. */
+#define FMC_RD_TAGVDW0S_tag(base, index) ((FMC_TAGVDW0S_REG(base, index) & FMC_TAGVDW0S_tag_MASK) >> FMC_TAGVDW0S_tag_SHIFT)
+#define FMC_BRD_TAGVDW0S_tag(base, index) (FMC_RD_TAGVDW0S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW0S_tag(base, index, value) (FMC_RMW_TAGVDW0S(base, index, FMC_TAGVDW0S_tag_MASK, FMC_TAGVDW0S_tag(value)))
+#define FMC_BWR_TAGVDW0S_tag(base, index, value) (FMC_WR_TAGVDW0S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW1S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW1S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW1S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW1S(base, index) (FMC_TAGVDW1S_REG(base, index))
+#define FMC_WR_TAGVDW1S(base, index, value) (FMC_TAGVDW1S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW1S(base, index, mask, value) (FMC_WR_TAGVDW1S(base, index, (FMC_RD_TAGVDW1S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW1S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW1S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW1S_valid field. */
+#define FMC_RD_TAGVDW1S_valid(base, index) ((FMC_TAGVDW1S_REG(base, index) & FMC_TAGVDW1S_valid_MASK) >> FMC_TAGVDW1S_valid_SHIFT)
+#define FMC_BRD_TAGVDW1S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW1S_REG(base, index), FMC_TAGVDW1S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW1S_valid(base, index, value) (FMC_RMW_TAGVDW1S(base, index, FMC_TAGVDW1S_valid_MASK, FMC_TAGVDW1S_valid(value)))
+#define FMC_BWR_TAGVDW1S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW1S_REG(base, index), FMC_TAGVDW1S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW1S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW1S_tag field. */
+#define FMC_RD_TAGVDW1S_tag(base, index) ((FMC_TAGVDW1S_REG(base, index) & FMC_TAGVDW1S_tag_MASK) >> FMC_TAGVDW1S_tag_SHIFT)
+#define FMC_BRD_TAGVDW1S_tag(base, index) (FMC_RD_TAGVDW1S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW1S_tag(base, index, value) (FMC_RMW_TAGVDW1S(base, index, FMC_TAGVDW1S_tag_MASK, FMC_TAGVDW1S_tag(value)))
+#define FMC_BWR_TAGVDW1S_tag(base, index, value) (FMC_WR_TAGVDW1S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW2S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW2S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW2S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW2S(base, index) (FMC_TAGVDW2S_REG(base, index))
+#define FMC_WR_TAGVDW2S(base, index, value) (FMC_TAGVDW2S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW2S(base, index, mask, value) (FMC_WR_TAGVDW2S(base, index, (FMC_RD_TAGVDW2S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW2S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW2S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW2S_valid field. */
+#define FMC_RD_TAGVDW2S_valid(base, index) ((FMC_TAGVDW2S_REG(base, index) & FMC_TAGVDW2S_valid_MASK) >> FMC_TAGVDW2S_valid_SHIFT)
+#define FMC_BRD_TAGVDW2S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW2S_REG(base, index), FMC_TAGVDW2S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW2S_valid(base, index, value) (FMC_RMW_TAGVDW2S(base, index, FMC_TAGVDW2S_valid_MASK, FMC_TAGVDW2S_valid(value)))
+#define FMC_BWR_TAGVDW2S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW2S_REG(base, index), FMC_TAGVDW2S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW2S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW2S_tag field. */
+#define FMC_RD_TAGVDW2S_tag(base, index) ((FMC_TAGVDW2S_REG(base, index) & FMC_TAGVDW2S_tag_MASK) >> FMC_TAGVDW2S_tag_SHIFT)
+#define FMC_BRD_TAGVDW2S_tag(base, index) (FMC_RD_TAGVDW2S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW2S_tag(base, index, value) (FMC_RMW_TAGVDW2S(base, index, FMC_TAGVDW2S_tag_MASK, FMC_TAGVDW2S_tag(value)))
+#define FMC_BWR_TAGVDW2S_tag(base, index, value) (FMC_WR_TAGVDW2S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW3S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW3S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW3S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW3S(base, index) (FMC_TAGVDW3S_REG(base, index))
+#define FMC_WR_TAGVDW3S(base, index, value) (FMC_TAGVDW3S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW3S(base, index, mask, value) (FMC_WR_TAGVDW3S(base, index, (FMC_RD_TAGVDW3S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW3S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW3S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW3S_valid field. */
+#define FMC_RD_TAGVDW3S_valid(base, index) ((FMC_TAGVDW3S_REG(base, index) & FMC_TAGVDW3S_valid_MASK) >> FMC_TAGVDW3S_valid_SHIFT)
+#define FMC_BRD_TAGVDW3S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW3S_REG(base, index), FMC_TAGVDW3S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW3S_valid(base, index, value) (FMC_RMW_TAGVDW3S(base, index, FMC_TAGVDW3S_valid_MASK, FMC_TAGVDW3S_valid(value)))
+#define FMC_BWR_TAGVDW3S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW3S_REG(base, index), FMC_TAGVDW3S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW3S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW3S_tag field. */
+#define FMC_RD_TAGVDW3S_tag(base, index) ((FMC_TAGVDW3S_REG(base, index) & FMC_TAGVDW3S_tag_MASK) >> FMC_TAGVDW3S_tag_SHIFT)
+#define FMC_BRD_TAGVDW3S_tag(base, index) (FMC_RD_TAGVDW3S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW3S_tag(base, index, value) (FMC_RMW_TAGVDW3S(base, index, FMC_TAGVDW3S_tag_MASK, FMC_TAGVDW3S_tag(value)))
+#define FMC_BWR_TAGVDW3S_tag(base, index, value) (FMC_WR_TAGVDW3S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_DATA_U - Cache Data Storage (upper word)
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_DATA_U - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_DATA_U register
+ */
+/*@{*/
+#define FMC_RD_DATA_U(base, index, index2) (FMC_DATA_U_REG(base, index, index2))
+#define FMC_WR_DATA_U(base, index, index2, value) (FMC_DATA_U_REG(base, index, index2) = (value))
+#define FMC_RMW_DATA_U(base, index, index2, mask, value) (FMC_WR_DATA_U(base, index, index2, (FMC_RD_DATA_U(base, index, index2) & ~(mask)) | (value)))
+#define FMC_SET_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) |  (value)))
+#define FMC_CLR_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) & ~(value)))
+#define FMC_TOG_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_DATA_L - Cache Data Storage (lower word)
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_DATA_L - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_DATA_L register
+ */
+/*@{*/
+#define FMC_RD_DATA_L(base, index, index2) (FMC_DATA_L_REG(base, index, index2))
+#define FMC_WR_DATA_L(base, index, index2, value) (FMC_DATA_L_REG(base, index, index2) = (value))
+#define FMC_RMW_DATA_L(base, index, index2, mask, value) (FMC_WR_DATA_L(base, index, index2, (FMC_RD_DATA_L(base, index, index2) & ~(mask)) | (value)))
+#define FMC_SET_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) |  (value)))
+#define FMC_CLR_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) & ~(value)))
+#define FMC_TOG_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FTFE
+ *
+ * Flash Memory Interface
+ *
+ * Registers defined in this header file:
+ * - FTFE_FSTAT - Flash Status Register
+ * - FTFE_FCNFG - Flash Configuration Register
+ * - FTFE_FSEC - Flash Security Register
+ * - FTFE_FOPT - Flash Option Register
+ * - FTFE_FCCOB3 - Flash Common Command Object Registers
+ * - FTFE_FCCOB2 - Flash Common Command Object Registers
+ * - FTFE_FCCOB1 - Flash Common Command Object Registers
+ * - FTFE_FCCOB0 - Flash Common Command Object Registers
+ * - FTFE_FCCOB7 - Flash Common Command Object Registers
+ * - FTFE_FCCOB6 - Flash Common Command Object Registers
+ * - FTFE_FCCOB5 - Flash Common Command Object Registers
+ * - FTFE_FCCOB4 - Flash Common Command Object Registers
+ * - FTFE_FCCOBB - Flash Common Command Object Registers
+ * - FTFE_FCCOBA - Flash Common Command Object Registers
+ * - FTFE_FCCOB9 - Flash Common Command Object Registers
+ * - FTFE_FCCOB8 - Flash Common Command Object Registers
+ * - FTFE_FPROT3 - Program Flash Protection Registers
+ * - FTFE_FPROT2 - Program Flash Protection Registers
+ * - FTFE_FPROT1 - Program Flash Protection Registers
+ * - FTFE_FPROT0 - Program Flash Protection Registers
+ * - FTFE_FEPROT - EEPROM Protection Register
+ * - FTFE_FDPROT - Data Flash Protection Register
+ */
+
+#define FTFE_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFE module. */
+#define FTFE_IDX (0U) /*!< Instance number for FTFE. */
+
+/*******************************************************************************
+ * FTFE_FSTAT - Flash Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FSTAT - Flash Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FSTAT register reports the operational status of the FTFE module. The
+ * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0
+ * bit is read only. The unassigned bits read 0 and are not writable. When set, the
+ * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this
+ * register prevent the launch of any more commands or writes to the FlexRAM (when
+ * EEERDY is set) until the flag is cleared (by writing a one to it).
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FSTAT register
+ */
+/*@{*/
+#define FTFE_RD_FSTAT(base)      (FTFE_FSTAT_REG(base))
+#define FTFE_WR_FSTAT(base, value) (FTFE_FSTAT_REG(base) = (value))
+#define FTFE_RMW_FSTAT(base, mask, value) (FTFE_WR_FSTAT(base, (FTFE_RD_FSTAT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) |  (value)))
+#define FTFE_CLR_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) & ~(value)))
+#define FTFE_TOG_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FSTAT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO)
+ *
+ * The MGSTAT0 status flag is set if an error is detected during execution of an
+ * FTFE command or during the flash reset sequence. As a status flag, this bit
+ * cannot (and need not) be cleared by the user like the other error flags in this
+ * register. The value of the MGSTAT0 bit for "command-N" is valid only at the
+ * end of the "command-N" execution when CCIF=1 and before the next command has
+ * been launched. At some point during the execution of "command-N+1," the previous
+ * result is discarded and any previous error is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field. */
+#define FTFE_RD_FSTAT_MGSTAT0(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_MGSTAT0_MASK) >> FTFE_FSTAT_MGSTAT0_SHIFT)
+#define FTFE_BRD_FSTAT_MGSTAT0(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_MGSTAT0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C)
+ *
+ * The FPVIOL error bit indicates an attempt was made to program or erase an
+ * address in a protected area of program flash or data flash memory during a
+ * command write sequence or a write was attempted to a protected area of the FlexRAM
+ * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared
+ * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a
+ * 0 to the FPVIOL bit has no effect.
+ *
+ * Values:
+ * - 0b0 - No protection violation detected
+ * - 0b1 - Protection violation detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_FPVIOL field. */
+#define FTFE_RD_FSTAT_FPVIOL(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_FPVIOL_MASK) >> FTFE_FSTAT_FPVIOL_SHIFT)
+#define FTFE_BRD_FSTAT_FPVIOL(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_FPVIOL_SHIFT))
+
+/*! @brief Set the FPVIOL field to a new value. */
+#define FTFE_WR_FSTAT_FPVIOL(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_FPVIOL(value)))
+#define FTFE_BWR_FSTAT_FPVIOL(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_FPVIOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field ACCERR[5] (W1C)
+ *
+ * The ACCERR error bit indicates an illegal access has occurred to an FTFE
+ * resource caused by a violation of the command write sequence or issuing an illegal
+ * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch
+ * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
+ * ACCERR bit has no effect.
+ *
+ * Values:
+ * - 0b0 - No access error detected
+ * - 0b1 - Access error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_ACCERR field. */
+#define FTFE_RD_FSTAT_ACCERR(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_ACCERR_MASK) >> FTFE_FSTAT_ACCERR_SHIFT)
+#define FTFE_BRD_FSTAT_ACCERR(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_ACCERR_SHIFT))
+
+/*! @brief Set the ACCERR field to a new value. */
+#define FTFE_WR_FSTAT_ACCERR(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_ACCERR(value)))
+#define FTFE_BWR_FSTAT_ACCERR(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_ACCERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C)
+ *
+ * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE
+ * resource that was being manipulated by an FTFE command (CCIF=0). Any
+ * simultaneous access is detected as a collision error by the block arbitration logic. The
+ * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by
+ * writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
+ *
+ * Values:
+ * - 0b0 - No collision error detected
+ * - 0b1 - Collision error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_RDCOLERR field. */
+#define FTFE_RD_FSTAT_RDCOLERR(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_RDCOLERR_MASK) >> FTFE_FSTAT_RDCOLERR_SHIFT)
+#define FTFE_BRD_FSTAT_RDCOLERR(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_RDCOLERR_SHIFT))
+
+/*! @brief Set the RDCOLERR field to a new value. */
+#define FTFE_WR_FSTAT_RDCOLERR(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_RDCOLERR(value)))
+#define FTFE_BWR_FSTAT_RDCOLERR(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_RDCOLERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field CCIF[7] (W1C)
+ *
+ * The CCIF flag indicates that a FTFE command or EEPROM file system operation
+ * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a
+ * command, and CCIF stays low until command completion or command violation. The
+ * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE,
+ * and CCIF stays low until the EEPROM file system has created the associated
+ * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory
+ * controller at the end of the reset initialization sequence. Depending on how
+ * quickly the read occurs after reset release, the user may or may not see the 0
+ * hardware reset value.
+ *
+ * Values:
+ * - 0b0 - FTFE command or EEPROM file system operation in progress
+ * - 0b1 - FTFE command or EEPROM file system operation has completed
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_CCIF field. */
+#define FTFE_RD_FSTAT_CCIF(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_CCIF_MASK) >> FTFE_FSTAT_CCIF_SHIFT)
+#define FTFE_BRD_FSTAT_CCIF(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_CCIF_SHIFT))
+
+/*! @brief Set the CCIF field to a new value. */
+#define FTFE_WR_FSTAT_CCIF(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_CCIF_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_RDCOLERR_MASK), FTFE_FSTAT_CCIF(value)))
+#define FTFE_BWR_FSTAT_CCIF(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_CCIF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCNFG - Flash Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCNFG - Flash Configuration Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides information on the current functional state of the
+ * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write
+ * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned
+ * bits read as noted and are not writable. The reset values for the SWAP, PFLSH,
+ * RAMRDY, and EEERDY bits are determined during the reset sequence.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCNFG register
+ */
+/*@{*/
+#define FTFE_RD_FCNFG(base)      (FTFE_FCNFG_REG(base))
+#define FTFE_WR_FCNFG(base, value) (FTFE_FCNFG_REG(base) = (value))
+#define FTFE_RMW_FCNFG(base, mask, value) (FTFE_WR_FCNFG(base, (FTFE_RD_FCNFG(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) |  (value)))
+#define FTFE_CLR_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) & ~(value)))
+#define FTFE_TOG_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FCNFG bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCNFG, field EEERDY[0] (RO)
+ *
+ * For devices with FlexNVM: This flag indicates if the EEPROM backup data has
+ * been copied to the FlexRAM and is therefore available for read access. During
+ * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if
+ * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM:
+ * This bit is reserved.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FlexRAM is not available for EEPROM
+ *     operation.
+ * - 0b1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations
+ *     where: reads from the FlexRAM return data previously written to the
+ *     FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the
+ *     written data in the FlexRAM and EEPROM backup.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_EEERDY field. */
+#define FTFE_RD_FCNFG_EEERDY(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_EEERDY_MASK) >> FTFE_FCNFG_EEERDY_SHIFT)
+#define FTFE_BRD_FCNFG_EEERDY(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_EEERDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field RAMRDY[1] (RO)
+ *
+ * This flag indicates the current status of the FlexRAM/ programming
+ * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally
+ * controlled by the Set FlexRAM Function command. During the reset sequence, the
+ * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will
+ * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is
+ * cleared if the Program Partition command is run to partition the FlexNVM block
+ * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks
+ * command or execution of the erase-all operation triggered external to the FTFE.
+ * For devices without FlexNVM: This bit should always be set.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FlexRAM is not available for traditional
+ *     RAM access. For devices without FlexNVM: Programming acceleration RAM is not
+ *     available.
+ * - 0b1 - For devices with FlexNVM: FlexRAM is available as traditional RAM
+ *     only; writes to the FlexRAM do not trigger EEPROM operations. For devices
+ *     without FlexNVM: Programming acceleration RAM is available.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_RAMRDY field. */
+#define FTFE_RD_FCNFG_RAMRDY(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_RAMRDY_MASK) >> FTFE_FCNFG_RAMRDY_SHIFT)
+#define FTFE_BRD_FCNFG_RAMRDY(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RAMRDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field PFLSH[2] (RO)
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FTFE configuration supports two program
+ *     flash blocks and two FlexNVM blocks For devices with program flash only:
+ *     Reserved
+ * - 0b1 - For devices with FlexNVM: Reserved For devices with program flash
+ *     only: FTFE configuration supports four program flash blocks
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_PFLSH field. */
+#define FTFE_RD_FCNFG_PFLSH(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_PFLSH_MASK) >> FTFE_FCNFG_PFLSH_SHIFT)
+#define FTFE_BRD_FCNFG_PFLSH(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_PFLSH_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field SWAP[3] (RO)
+ *
+ * The SWAP flag indicates which half of the program flash space is located at
+ * relative address 0x0000. The state of the SWAP flag is set by the FTFE during
+ * the reset sequence. See for information on swap management.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: Program flash 0 block is located at
+ *     relative address 0x0000 For devices with program flash only: Program flash 0
+ *     block is located at relative address 0x0000
+ * - 0b1 - For devices with FlexNVM: Reserved For devices with program flash
+ *     only: Program flash 1 block is located at relative address 0x0000
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_SWAP field. */
+#define FTFE_RD_FCNFG_SWAP(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_SWAP_MASK) >> FTFE_FCNFG_SWAP_SHIFT)
+#define FTFE_BRD_FCNFG_SWAP(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_SWAP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW)
+ *
+ * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector
+ * command while it is executing.
+ *
+ * Values:
+ * - 0b0 - No suspend requested
+ * - 0b1 - Suspend the current Erase Flash Sector command execution.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_ERSSUSP field. */
+#define FTFE_RD_FCNFG_ERSSUSP(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_ERSSUSP_MASK) >> FTFE_FCNFG_ERSSUSP_SHIFT)
+#define FTFE_BRD_FCNFG_ERSSUSP(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSSUSP_SHIFT))
+
+/*! @brief Set the ERSSUSP field to a new value. */
+#define FTFE_WR_FCNFG_ERSSUSP(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_ERSSUSP_MASK, FTFE_FCNFG_ERSSUSP(value)))
+#define FTFE_BWR_FCNFG_ERSSUSP(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSSUSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO)
+ *
+ * This bit issues a request to the memory controller to execute the Erase All
+ * Blocks command and release security. ERSAREQ is not directly writable but is
+ * under indirect user control. Refer to the device's Chip Configuration details on
+ * how to request this command. The ERSAREQ bit sets when an erase all request
+ * is triggered external to the FTFE and CCIF is set (no command is currently
+ * being executed). ERSAREQ is cleared by the FTFE when the operation completes.
+ *
+ * Values:
+ * - 0b0 - No request or request complete
+ * - 0b1 - Request to: run the Erase All Blocks command, verify the erased
+ *     state, program the security byte in the Flash Configuration Field to the
+ *     unsecure state, and release MCU security by setting the FSEC[SEC] field to the
+ *     unsecure state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_ERSAREQ field. */
+#define FTFE_RD_FCNFG_ERSAREQ(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_ERSAREQ_MASK) >> FTFE_FCNFG_ERSAREQ_SHIFT)
+#define FTFE_BRD_FCNFG_ERSAREQ(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSAREQ_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW)
+ *
+ * The RDCOLLIE bit controls interrupt generation when an FTFE read collision
+ * error occurs.
+ *
+ * Values:
+ * - 0b0 - Read collision error interrupt disabled
+ * - 0b1 - Read collision error interrupt enabled. An interrupt request is
+ *     generated whenever an FTFE read collision error is detected (see the
+ *     description of FSTAT[RDCOLERR]).
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field. */
+#define FTFE_RD_FCNFG_RDCOLLIE(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_RDCOLLIE_MASK) >> FTFE_FCNFG_RDCOLLIE_SHIFT)
+#define FTFE_BRD_FCNFG_RDCOLLIE(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RDCOLLIE_SHIFT))
+
+/*! @brief Set the RDCOLLIE field to a new value. */
+#define FTFE_WR_FCNFG_RDCOLLIE(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_RDCOLLIE_MASK, FTFE_FCNFG_RDCOLLIE(value)))
+#define FTFE_BWR_FCNFG_RDCOLLIE(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RDCOLLIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field CCIE[7] (RW)
+ *
+ * The CCIE bit controls interrupt generation when an FTFE command completes.
+ *
+ * Values:
+ * - 0b0 - Command complete interrupt disabled
+ * - 0b1 - Command complete interrupt enabled. An interrupt request is generated
+ *     whenever the FSTAT[CCIF] flag is set.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_CCIE field. */
+#define FTFE_RD_FCNFG_CCIE(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_CCIE_MASK) >> FTFE_FCNFG_CCIE_SHIFT)
+#define FTFE_BRD_FCNFG_CCIE(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_CCIE_SHIFT))
+
+/*! @brief Set the CCIE field to a new value. */
+#define FTFE_WR_FCNFG_CCIE(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_CCIE_MASK, FTFE_FCNFG_CCIE(value)))
+#define FTFE_BWR_FCNFG_CCIE(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_CCIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FSEC - Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FSEC - Flash Security Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This read-only register holds all bits associated with the security of the
+ * MCU and FTFE module. During the reset sequence, the register is loaded with the
+ * contents of the flash security byte in the Flash Configuration Field located
+ * in program flash memory. The Flash basis for the values is signified by X in
+ * the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FSEC register
+ */
+/*@{*/
+#define FTFE_RD_FSEC(base)       (FTFE_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FSEC bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSEC, field SEC[1:0] (RO)
+ *
+ * These bits define the security state of the MCU. In the secure state, the MCU
+ * limits access to FTFE module resources. The limitations are defined per
+ * device and are detailed in the Chip Configuration details. If the FTFE module is
+ * unsecured using backdoor key access, the SEC bits are forced to 10b.
+ *
+ * Values:
+ * - 0b00 - MCU security status is secure
+ * - 0b01 - MCU security status is secure
+ * - 0b10 - MCU security status is unsecure (The standard shipping condition of
+ *     the FTFE is unsecure.)
+ * - 0b11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_SEC field. */
+#define FTFE_RD_FSEC_SEC(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_SEC_MASK) >> FTFE_FSEC_SEC_SHIFT)
+#define FTFE_BRD_FSEC_SEC(base) (FTFE_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field FSLACC[3:2] (RO)
+ *
+ * These bits enable or disable access to the flash memory contents during
+ * returned part failure analysis at Freescale. When SEC is secure and FSLACC is
+ * denied, access to the program flash contents is denied and any failure analysis
+ * performed by Freescale factory test must begin with a full erase to unsecure the
+ * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is
+ * granted), Freescale factory testing has visibility of the current flash
+ * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to
+ * secure. When the SEC field is set to unsecure, the FSLACC setting does not
+ * matter.
+ *
+ * Values:
+ * - 0b00 - Freescale factory access granted
+ * - 0b01 - Freescale factory access denied
+ * - 0b10 - Freescale factory access denied
+ * - 0b11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_FSLACC field. */
+#define FTFE_RD_FSEC_FSLACC(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_FSLACC_MASK) >> FTFE_FSEC_FSLACC_SHIFT)
+#define FTFE_BRD_FSEC_FSLACC(base) (FTFE_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field MEEN[5:4] (RO)
+ *
+ * Enables and disables mass erase capability of the FTFE module. The state of
+ * the MEEN bits is only relevant when the SEC bits are set to secure outside of
+ * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does
+ * not matter.
+ *
+ * Values:
+ * - 0b00 - Mass erase is enabled
+ * - 0b01 - Mass erase is enabled
+ * - 0b10 - Mass erase is disabled
+ * - 0b11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_MEEN field. */
+#define FTFE_RD_FSEC_MEEN(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_MEEN_MASK) >> FTFE_FSEC_MEEN_SHIFT)
+#define FTFE_BRD_FSEC_MEEN(base) (FTFE_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field KEYEN[7:6] (RO)
+ *
+ * These bits enable and disable backdoor key access to the FTFE module.
+ *
+ * Values:
+ * - 0b00 - Backdoor key access disabled
+ * - 0b01 - Backdoor key access disabled (preferred KEYEN state to disable
+ *     backdoor key access)
+ * - 0b10 - Backdoor key access enabled
+ * - 0b11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_KEYEN field. */
+#define FTFE_RD_FSEC_KEYEN(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_KEYEN_MASK) >> FTFE_FSEC_KEYEN_SHIFT)
+#define FTFE_BRD_FSEC_KEYEN(base) (FTFE_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FOPT - Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FOPT - Flash Option Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * The flash option register allows the MCU to customize its operations by
+ * examining the state of these read-only bits, which are loaded from NVM at reset.
+ * The function of the bits is defined in the device's Chip Configuration details.
+ * All bits in the register are read-only. During the reset sequence, the
+ * register is loaded from the flash nonvolatile option byte in the Flash Configuration
+ * Field located in program flash memory. The flash basis for the values is
+ * signified by X in the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FOPT register
+ */
+/*@{*/
+#define FTFE_RD_FOPT(base)       (FTFE_FOPT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB3 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB3 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB3 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB3(base)     (FTFE_FCCOB3_REG(base))
+#define FTFE_WR_FCCOB3(base, value) (FTFE_FCCOB3_REG(base) = (value))
+#define FTFE_RMW_FCCOB3(base, mask, value) (FTFE_WR_FCCOB3(base, (FTFE_RD_FCCOB3(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) |  (value)))
+#define FTFE_CLR_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) & ~(value)))
+#define FTFE_TOG_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB2 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB2 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB2 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB2(base)     (FTFE_FCCOB2_REG(base))
+#define FTFE_WR_FCCOB2(base, value) (FTFE_FCCOB2_REG(base) = (value))
+#define FTFE_RMW_FCCOB2(base, mask, value) (FTFE_WR_FCCOB2(base, (FTFE_RD_FCCOB2(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) |  (value)))
+#define FTFE_CLR_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) & ~(value)))
+#define FTFE_TOG_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB1 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB1 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB1 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB1(base)     (FTFE_FCCOB1_REG(base))
+#define FTFE_WR_FCCOB1(base, value) (FTFE_FCCOB1_REG(base) = (value))
+#define FTFE_RMW_FCCOB1(base, mask, value) (FTFE_WR_FCCOB1(base, (FTFE_RD_FCCOB1(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) |  (value)))
+#define FTFE_CLR_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) & ~(value)))
+#define FTFE_TOG_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB0 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB0 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB0 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB0(base)     (FTFE_FCCOB0_REG(base))
+#define FTFE_WR_FCCOB0(base, value) (FTFE_FCCOB0_REG(base) = (value))
+#define FTFE_RMW_FCCOB0(base, mask, value) (FTFE_WR_FCCOB0(base, (FTFE_RD_FCCOB0(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) |  (value)))
+#define FTFE_CLR_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) & ~(value)))
+#define FTFE_TOG_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB7 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB7 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB7 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB7(base)     (FTFE_FCCOB7_REG(base))
+#define FTFE_WR_FCCOB7(base, value) (FTFE_FCCOB7_REG(base) = (value))
+#define FTFE_RMW_FCCOB7(base, mask, value) (FTFE_WR_FCCOB7(base, (FTFE_RD_FCCOB7(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) |  (value)))
+#define FTFE_CLR_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) & ~(value)))
+#define FTFE_TOG_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB6 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB6 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB6 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB6(base)     (FTFE_FCCOB6_REG(base))
+#define FTFE_WR_FCCOB6(base, value) (FTFE_FCCOB6_REG(base) = (value))
+#define FTFE_RMW_FCCOB6(base, mask, value) (FTFE_WR_FCCOB6(base, (FTFE_RD_FCCOB6(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) |  (value)))
+#define FTFE_CLR_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) & ~(value)))
+#define FTFE_TOG_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB5 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB5 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB5 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB5(base)     (FTFE_FCCOB5_REG(base))
+#define FTFE_WR_FCCOB5(base, value) (FTFE_FCCOB5_REG(base) = (value))
+#define FTFE_RMW_FCCOB5(base, mask, value) (FTFE_WR_FCCOB5(base, (FTFE_RD_FCCOB5(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) |  (value)))
+#define FTFE_CLR_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) & ~(value)))
+#define FTFE_TOG_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB4 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB4 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB4 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB4(base)     (FTFE_FCCOB4_REG(base))
+#define FTFE_WR_FCCOB4(base, value) (FTFE_FCCOB4_REG(base) = (value))
+#define FTFE_RMW_FCCOB4(base, mask, value) (FTFE_WR_FCCOB4(base, (FTFE_RD_FCCOB4(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) |  (value)))
+#define FTFE_CLR_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) & ~(value)))
+#define FTFE_TOG_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOBB - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOBB - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBB register
+ */
+/*@{*/
+#define FTFE_RD_FCCOBB(base)     (FTFE_FCCOBB_REG(base))
+#define FTFE_WR_FCCOBB(base, value) (FTFE_FCCOBB_REG(base) = (value))
+#define FTFE_RMW_FCCOBB(base, mask, value) (FTFE_WR_FCCOBB(base, (FTFE_RD_FCCOBB(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) |  (value)))
+#define FTFE_CLR_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) & ~(value)))
+#define FTFE_TOG_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOBA - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOBA - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBA register
+ */
+/*@{*/
+#define FTFE_RD_FCCOBA(base)     (FTFE_FCCOBA_REG(base))
+#define FTFE_WR_FCCOBA(base, value) (FTFE_FCCOBA_REG(base) = (value))
+#define FTFE_RMW_FCCOBA(base, mask, value) (FTFE_WR_FCCOBA(base, (FTFE_RD_FCCOBA(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) |  (value)))
+#define FTFE_CLR_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) & ~(value)))
+#define FTFE_TOG_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB9 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB9 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB9 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB9(base)     (FTFE_FCCOB9_REG(base))
+#define FTFE_WR_FCCOB9(base, value) (FTFE_FCCOB9_REG(base) = (value))
+#define FTFE_RMW_FCCOB9(base, mask, value) (FTFE_WR_FCCOB9(base, (FTFE_RD_FCCOB9(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) |  (value)))
+#define FTFE_CLR_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) & ~(value)))
+#define FTFE_TOG_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB8 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB8 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB8 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB8(base)     (FTFE_FCCOB8_REG(base))
+#define FTFE_WR_FCCOB8(base, value) (FTFE_FCCOB8_REG(base) = (value))
+#define FTFE_RMW_FCCOB8(base, mask, value) (FTFE_WR_FCCOB8(base, (FTFE_RD_FCCOB8(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) |  (value)))
+#define FTFE_CLR_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) & ~(value)))
+#define FTFE_TOG_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT3 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT3 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT3 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT3(base)     (FTFE_FPROT3_REG(base))
+#define FTFE_WR_FPROT3(base, value) (FTFE_FPROT3_REG(base) = (value))
+#define FTFE_RMW_FPROT3(base, mask, value) (FTFE_WR_FPROT3(base, (FTFE_RD_FPROT3(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) |  (value)))
+#define FTFE_CLR_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) & ~(value)))
+#define FTFE_TOG_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT2 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT2 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT2 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT2(base)     (FTFE_FPROT2_REG(base))
+#define FTFE_WR_FPROT2(base, value) (FTFE_FPROT2_REG(base) = (value))
+#define FTFE_RMW_FPROT2(base, mask, value) (FTFE_WR_FPROT2(base, (FTFE_RD_FPROT2(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) |  (value)))
+#define FTFE_CLR_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) & ~(value)))
+#define FTFE_TOG_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT1 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT1 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT1 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT1(base)     (FTFE_FPROT1_REG(base))
+#define FTFE_WR_FPROT1(base, value) (FTFE_FPROT1_REG(base) = (value))
+#define FTFE_RMW_FPROT1(base, mask, value) (FTFE_WR_FPROT1(base, (FTFE_RD_FPROT1(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) |  (value)))
+#define FTFE_CLR_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) & ~(value)))
+#define FTFE_TOG_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT0 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT0 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT0 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT0(base)     (FTFE_FPROT0_REG(base))
+#define FTFE_WR_FPROT0(base, value) (FTFE_FPROT0_REG(base) = (value))
+#define FTFE_RMW_FPROT0(base, mask, value) (FTFE_WR_FPROT0(base, (FTFE_RD_FPROT0(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) |  (value)))
+#define FTFE_CLR_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) & ~(value)))
+#define FTFE_TOG_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FEPROT - EEPROM Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FEPROT - EEPROM Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of
+ * the FlexRAM are protected against program and erase operations. Protected
+ * EEPROM regions cannot have their content changed by writing to it. Unprotected
+ * regions can be changed by writing to the FlexRAM. For devices with program flash
+ * only: This register is reserved and not used.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FEPROT register
+ */
+/*@{*/
+#define FTFE_RD_FEPROT(base)     (FTFE_FEPROT_REG(base))
+#define FTFE_WR_FEPROT(base, value) (FTFE_FEPROT_REG(base) = (value))
+#define FTFE_RMW_FEPROT(base, mask, value) (FTFE_WR_FEPROT(base, (FTFE_RD_FEPROT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) |  (value)))
+#define FTFE_CLR_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) & ~(value)))
+#define FTFE_TOG_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FDPROT - Data Flash Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FDPROT - Data Flash Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FDPROT register defines which data flash regions are protected against
+ * program and erase operations. Protected Flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by both program and erase
+ * operations.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FDPROT register
+ */
+/*@{*/
+#define FTFE_RD_FDPROT(base)     (FTFE_FDPROT_REG(base))
+#define FTFE_WR_FDPROT(base, value) (FTFE_FDPROT_REG(base) = (value))
+#define FTFE_RMW_FDPROT(base, mask, value) (FTFE_WR_FDPROT(base, (FTFE_RD_FDPROT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) |  (value)))
+#define FTFE_CLR_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) & ~(value)))
+#define FTFE_TOG_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FTM
+ *
+ * FlexTimer Module
+ *
+ * Registers defined in this header file:
+ * - FTM_SC - Status And Control
+ * - FTM_CNT - Counter
+ * - FTM_MOD - Modulo
+ * - FTM_CnSC - Channel (n) Status And Control
+ * - FTM_CnV - Channel (n) Value
+ * - FTM_CNTIN - Counter Initial Value
+ * - FTM_STATUS - Capture And Compare Status
+ * - FTM_MODE - Features Mode Selection
+ * - FTM_SYNC - Synchronization
+ * - FTM_OUTINIT - Initial State For Channels Output
+ * - FTM_OUTMASK - Output Mask
+ * - FTM_COMBINE - Function For Linked Channels
+ * - FTM_DEADTIME - Deadtime Insertion Control
+ * - FTM_EXTTRIG - FTM External Trigger
+ * - FTM_POL - Channels Polarity
+ * - FTM_FMS - Fault Mode Status
+ * - FTM_FILTER - Input Capture Filter Control
+ * - FTM_FLTCTRL - Fault Control
+ * - FTM_QDCTRL - Quadrature Decoder Control And Status
+ * - FTM_CONF - Configuration
+ * - FTM_FLTPOL - FTM Fault Input Polarity
+ * - FTM_SYNCONF - Synchronization Configuration
+ * - FTM_INVCTRL - FTM Inverting Control
+ * - FTM_SWOCTRL - FTM Software Output Control
+ * - FTM_PWMLOAD - FTM PWM Load
+ */
+
+#define FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
+#define FTM0_IDX (0U) /*!< Instance number for FTM0. */
+#define FTM1_IDX (1U) /*!< Instance number for FTM1. */
+#define FTM2_IDX (2U) /*!< Instance number for FTM2. */
+#define FTM3_IDX (3U) /*!< Instance number for FTM3. */
+
+/*******************************************************************************
+ * FTM_SC - Status And Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SC - Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * SC contains the overflow status flag and control bits used to configure the
+ * interrupt enable, FTM configuration, clock source, and prescaler factor. These
+ * controls relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SC register
+ */
+/*@{*/
+#define FTM_RD_SC(base)          (FTM_SC_REG(base))
+#define FTM_WR_SC(base, value)   (FTM_SC_REG(base) = (value))
+#define FTM_RMW_SC(base, mask, value) (FTM_WR_SC(base, (FTM_RD_SC(base) & ~(mask)) | (value)))
+#define FTM_SET_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) |  (value)))
+#define FTM_CLR_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) & ~(value)))
+#define FTM_TOG_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SC bitfields
+ */
+
+/*!
+ * @name Register FTM_SC, field PS[2:0] (RW)
+ *
+ * Selects one of 8 division factors for the clock source selected by CLKS. The
+ * new prescaler factor affects the clock source on the next system clock cycle
+ * after the new value is updated into the register bits. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b000 - Divide by 1
+ * - 0b001 - Divide by 2
+ * - 0b010 - Divide by 4
+ * - 0b011 - Divide by 8
+ * - 0b100 - Divide by 16
+ * - 0b101 - Divide by 32
+ * - 0b110 - Divide by 64
+ * - 0b111 - Divide by 128
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_PS field. */
+#define FTM_RD_SC_PS(base)   ((FTM_SC_REG(base) & FTM_SC_PS_MASK) >> FTM_SC_PS_SHIFT)
+#define FTM_BRD_SC_PS(base)  (FTM_RD_SC_PS(base))
+
+/*! @brief Set the PS field to a new value. */
+#define FTM_WR_SC_PS(base, value) (FTM_RMW_SC(base, FTM_SC_PS_MASK, FTM_SC_PS(value)))
+#define FTM_BWR_SC_PS(base, value) (FTM_WR_SC_PS(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field CLKS[4:3] (RW)
+ *
+ * Selects one of the three FTM counter clock sources. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b00 - No clock selected. This in effect disables the FTM counter.
+ * - 0b01 - System clock
+ * - 0b10 - Fixed frequency clock
+ * - 0b11 - External clock
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_CLKS field. */
+#define FTM_RD_SC_CLKS(base) ((FTM_SC_REG(base) & FTM_SC_CLKS_MASK) >> FTM_SC_CLKS_SHIFT)
+#define FTM_BRD_SC_CLKS(base) (FTM_RD_SC_CLKS(base))
+
+/*! @brief Set the CLKS field to a new value. */
+#define FTM_WR_SC_CLKS(base, value) (FTM_RMW_SC(base, FTM_SC_CLKS_MASK, FTM_SC_CLKS(value)))
+#define FTM_BWR_SC_CLKS(base, value) (FTM_WR_SC_CLKS(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field CPWMS[5] (RW)
+ *
+ * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
+ * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ *
+ * Values:
+ * - 0b0 - FTM counter operates in Up Counting mode.
+ * - 0b1 - FTM counter operates in Up-Down Counting mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_CPWMS field. */
+#define FTM_RD_SC_CPWMS(base) ((FTM_SC_REG(base) & FTM_SC_CPWMS_MASK) >> FTM_SC_CPWMS_SHIFT)
+#define FTM_BRD_SC_CPWMS(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_CPWMS_SHIFT))
+
+/*! @brief Set the CPWMS field to a new value. */
+#define FTM_WR_SC_CPWMS(base, value) (FTM_RMW_SC(base, FTM_SC_CPWMS_MASK, FTM_SC_CPWMS(value)))
+#define FTM_BWR_SC_CPWMS(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_CPWMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field TOIE[6] (RW)
+ *
+ * Enables FTM overflow interrupts.
+ *
+ * Values:
+ * - 0b0 - Disable TOF interrupts. Use software polling.
+ * - 0b1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_TOIE field. */
+#define FTM_RD_SC_TOIE(base) ((FTM_SC_REG(base) & FTM_SC_TOIE_MASK) >> FTM_SC_TOIE_SHIFT)
+#define FTM_BRD_SC_TOIE(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOIE_SHIFT))
+
+/*! @brief Set the TOIE field to a new value. */
+#define FTM_WR_SC_TOIE(base, value) (FTM_RMW_SC(base, FTM_SC_TOIE_MASK, FTM_SC_TOIE(value)))
+#define FTM_BWR_SC_TOIE(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field TOF[7] (ROWZ)
+ *
+ * Set by hardware when the FTM counter passes the value in the MOD register.
+ * The TOF bit is cleared by reading the SC register while TOF is set and then
+ * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
+ * occurs between the read and write operations, the write operation has no
+ * effect; therefore, TOF remains set indicating an overflow has occurred. In this
+ * case, a TOF interrupt request is not lost due to the clearing sequence for a
+ * previous TOF.
+ *
+ * Values:
+ * - 0b0 - FTM counter has not overflowed.
+ * - 0b1 - FTM counter has overflowed.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_TOF field. */
+#define FTM_RD_SC_TOF(base)  ((FTM_SC_REG(base) & FTM_SC_TOF_MASK) >> FTM_SC_TOF_SHIFT)
+#define FTM_BRD_SC_TOF(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOF_SHIFT))
+
+/*! @brief Set the TOF field to a new value. */
+#define FTM_WR_SC_TOF(base, value) (FTM_RMW_SC(base, FTM_SC_TOF_MASK, FTM_SC_TOF(value)))
+#define FTM_BWR_SC_TOF(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CNT - Counter
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CNT - Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CNT register contains the FTM counter value. Reset clears the CNT
+ * register. Writing any value to COUNT updates the counter with its initial value,
+ * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
+ * may read.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CNT register
+ */
+/*@{*/
+#define FTM_RD_CNT(base)         (FTM_CNT_REG(base))
+#define FTM_WR_CNT(base, value)  (FTM_CNT_REG(base) = (value))
+#define FTM_RMW_CNT(base, mask, value) (FTM_WR_CNT(base, (FTM_RD_CNT(base) & ~(mask)) | (value)))
+#define FTM_SET_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) |  (value)))
+#define FTM_CLR_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) & ~(value)))
+#define FTM_TOG_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CNT bitfields
+ */
+
+/*!
+ * @name Register FTM_CNT, field COUNT[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CNT_COUNT field. */
+#define FTM_RD_CNT_COUNT(base) ((FTM_CNT_REG(base) & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT)
+#define FTM_BRD_CNT_COUNT(base) (FTM_RD_CNT_COUNT(base))
+
+/*! @brief Set the COUNT field to a new value. */
+#define FTM_WR_CNT_COUNT(base, value) (FTM_RMW_CNT(base, FTM_CNT_COUNT_MASK, FTM_CNT_COUNT(value)))
+#define FTM_BWR_CNT_COUNT(base, value) (FTM_WR_CNT_COUNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_MOD - Modulo
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_MOD - Modulo (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Modulo register contains the modulo value for the FTM counter. After the
+ * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
+ * the next clock, and the next value of FTM counter depends on the selected
+ * counting method; see Counter. Writing to the MOD register latches the value into a
+ * buffer. The MOD register is updated with the value of its write buffer
+ * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
+ * mechanism may be manually reset by writing to the SC register whether BDM is
+ * active or not. Initialize the FTM counter, by writing to CNT, before writing
+ * to the MOD register to avoid confusion about when the first counter overflow
+ * will occur.
+ */
+/*!
+ * @name Constants and macros for entire FTM_MOD register
+ */
+/*@{*/
+#define FTM_RD_MOD(base)         (FTM_MOD_REG(base))
+#define FTM_WR_MOD(base, value)  (FTM_MOD_REG(base) = (value))
+#define FTM_RMW_MOD(base, mask, value) (FTM_WR_MOD(base, (FTM_RD_MOD(base) & ~(mask)) | (value)))
+#define FTM_SET_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) |  (value)))
+#define FTM_CLR_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) & ~(value)))
+#define FTM_TOG_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_MOD bitfields
+ */
+
+/*!
+ * @name Register FTM_MOD, field MOD[15:0] (RW)
+ *
+ * Modulo Value
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MOD_MOD field. */
+#define FTM_RD_MOD_MOD(base) ((FTM_MOD_REG(base) & FTM_MOD_MOD_MASK) >> FTM_MOD_MOD_SHIFT)
+#define FTM_BRD_MOD_MOD(base) (FTM_RD_MOD_MOD(base))
+
+/*! @brief Set the MOD field to a new value. */
+#define FTM_WR_MOD_MOD(base, value) (FTM_RMW_MOD(base, FTM_MOD_MOD_MASK, FTM_MOD_MOD(value)))
+#define FTM_BWR_MOD_MOD(base, value) (FTM_WR_MOD_MOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CnSC - Channel (n) Status And Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CnSC - Channel (n) Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CnSC contains the channel-interrupt-status flag and control bits used to
+ * configure the interrupt enable, channel configuration, and pin function. Mode,
+ * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
+ * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
+ * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
+ * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
+ * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
+ * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
+ * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
+ * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
+ * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
+ * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
+ * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
+ * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
+ * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
+ * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
+ * Enabled Rising and falling edges
+ */
+/*!
+ * @name Constants and macros for entire FTM_CnSC register
+ */
+/*@{*/
+#define FTM_RD_CnSC(base, index) (FTM_CnSC_REG(base, index))
+#define FTM_WR_CnSC(base, index, value) (FTM_CnSC_REG(base, index) = (value))
+#define FTM_RMW_CnSC(base, index, mask, value) (FTM_WR_CnSC(base, index, (FTM_RD_CnSC(base, index) & ~(mask)) | (value)))
+#define FTM_SET_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) |  (value)))
+#define FTM_CLR_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) & ~(value)))
+#define FTM_TOG_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CnSC bitfields
+ */
+
+/*!
+ * @name Register FTM_CnSC, field DMA[0] (RW)
+ *
+ * Enables DMA transfers for the channel.
+ *
+ * Values:
+ * - 0b0 - Disable DMA transfers.
+ * - 0b1 - Enable DMA transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_DMA field. */
+#define FTM_RD_CnSC_DMA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_DMA_MASK) >> FTM_CnSC_DMA_SHIFT)
+#define FTM_BRD_CnSC_DMA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define FTM_WR_CnSC_DMA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_DMA_MASK, FTM_CnSC_DMA(value)))
+#define FTM_BWR_CnSC_DMA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_DMA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field ELSA[2] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_ELSA field. */
+#define FTM_RD_CnSC_ELSA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_ELSA_MASK) >> FTM_CnSC_ELSA_SHIFT)
+#define FTM_BRD_CnSC_ELSA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSA_SHIFT))
+
+/*! @brief Set the ELSA field to a new value. */
+#define FTM_WR_CnSC_ELSA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_ELSA_MASK, FTM_CnSC_ELSA(value)))
+#define FTM_BWR_CnSC_ELSA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field ELSB[3] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_ELSB field. */
+#define FTM_RD_CnSC_ELSB(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_ELSB_MASK) >> FTM_CnSC_ELSB_SHIFT)
+#define FTM_BRD_CnSC_ELSB(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSB_SHIFT))
+
+/*! @brief Set the ELSB field to a new value. */
+#define FTM_WR_CnSC_ELSB(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_ELSB_MASK, FTM_CnSC_ELSB(value)))
+#define FTM_BWR_CnSC_ELSB(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field MSA[4] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_MSA field. */
+#define FTM_RD_CnSC_MSA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_MSA_MASK) >> FTM_CnSC_MSA_SHIFT)
+#define FTM_BRD_CnSC_MSA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSA_SHIFT))
+
+/*! @brief Set the MSA field to a new value. */
+#define FTM_WR_CnSC_MSA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_MSA_MASK, FTM_CnSC_MSA(value)))
+#define FTM_BWR_CnSC_MSA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field MSB[5] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_MSB field. */
+#define FTM_RD_CnSC_MSB(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_MSB_MASK) >> FTM_CnSC_MSB_SHIFT)
+#define FTM_BRD_CnSC_MSB(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSB_SHIFT))
+
+/*! @brief Set the MSB field to a new value. */
+#define FTM_WR_CnSC_MSB(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_MSB_MASK, FTM_CnSC_MSB(value)))
+#define FTM_BWR_CnSC_MSB(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field CHIE[6] (RW)
+ *
+ * Enables channel interrupts.
+ *
+ * Values:
+ * - 0b0 - Disable channel interrupts. Use software polling.
+ * - 0b1 - Enable channel interrupts.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_CHIE field. */
+#define FTM_RD_CnSC_CHIE(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_CHIE_MASK) >> FTM_CnSC_CHIE_SHIFT)
+#define FTM_BRD_CnSC_CHIE(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHIE_SHIFT))
+
+/*! @brief Set the CHIE field to a new value. */
+#define FTM_WR_CnSC_CHIE(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_CHIE_MASK, FTM_CnSC_CHIE(value)))
+#define FTM_BWR_CnSC_CHIE(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field CHF[7] (ROWZ)
+ *
+ * Set by hardware when an event occurs on the channel. CHF is cleared by
+ * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
+ * Writing a 1 to CHF has no effect. If another event occurs between the read and
+ * write operations, the write operation has no effect; therefore, CHF remains set
+ * indicating an event has occurred. In this case a CHF interrupt request is not
+ * lost due to the clearing sequence for a previous CHF.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_CHF field. */
+#define FTM_RD_CnSC_CHF(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_CHF_MASK) >> FTM_CnSC_CHF_SHIFT)
+#define FTM_BRD_CnSC_CHF(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHF_SHIFT))
+
+/*! @brief Set the CHF field to a new value. */
+#define FTM_WR_CnSC_CHF(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_CHF_MASK, FTM_CnSC_CHF(value)))
+#define FTM_BWR_CnSC_CHF(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CnV - Channel (n) Value
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CnV - Channel (n) Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the captured FTM counter value for the input modes or
+ * the match value for the output modes. In Input Capture, Capture Test, and
+ * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
+ * writing to a CnV register latches the value into a buffer. A CnV register is
+ * updated with the value of its write buffer according to Registers updated from
+ * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
+ * reset by writing to the CnSC register whether BDM mode is active or not.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CnV register
+ */
+/*@{*/
+#define FTM_RD_CnV(base, index)  (FTM_CnV_REG(base, index))
+#define FTM_WR_CnV(base, index, value) (FTM_CnV_REG(base, index) = (value))
+#define FTM_RMW_CnV(base, index, mask, value) (FTM_WR_CnV(base, index, (FTM_RD_CnV(base, index) & ~(mask)) | (value)))
+#define FTM_SET_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) |  (value)))
+#define FTM_CLR_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) & ~(value)))
+#define FTM_TOG_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CnV bitfields
+ */
+
+/*!
+ * @name Register FTM_CnV, field VAL[15:0] (RW)
+ *
+ * Captured FTM counter value of the input modes or the match value for the
+ * output modes
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnV_VAL field. */
+#define FTM_RD_CnV_VAL(base, index) ((FTM_CnV_REG(base, index) & FTM_CnV_VAL_MASK) >> FTM_CnV_VAL_SHIFT)
+#define FTM_BRD_CnV_VAL(base, index) (FTM_RD_CnV_VAL(base, index))
+
+/*! @brief Set the VAL field to a new value. */
+#define FTM_WR_CnV_VAL(base, index, value) (FTM_RMW_CnV(base, index, FTM_CnV_VAL_MASK, FTM_CnV_VAL(value)))
+#define FTM_BWR_CnV_VAL(base, index, value) (FTM_WR_CnV_VAL(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CNTIN - Counter Initial Value
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CNTIN - Counter Initial Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Counter Initial Value register contains the initial value for the FTM
+ * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
+ * register is updated with the value of its write buffer according to Registers
+ * updated from write buffers. When the FTM clock is initially selected, by
+ * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
+ * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
+ * write the new value to the the CNTIN register and then initialize the FTM
+ * counter by writing any value to the CNT register.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CNTIN register
+ */
+/*@{*/
+#define FTM_RD_CNTIN(base)       (FTM_CNTIN_REG(base))
+#define FTM_WR_CNTIN(base, value) (FTM_CNTIN_REG(base) = (value))
+#define FTM_RMW_CNTIN(base, mask, value) (FTM_WR_CNTIN(base, (FTM_RD_CNTIN(base) & ~(mask)) | (value)))
+#define FTM_SET_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) |  (value)))
+#define FTM_CLR_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) & ~(value)))
+#define FTM_TOG_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CNTIN bitfields
+ */
+
+/*!
+ * @name Register FTM_CNTIN, field INIT[15:0] (RW)
+ *
+ * Initial Value Of The FTM Counter
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CNTIN_INIT field. */
+#define FTM_RD_CNTIN_INIT(base) ((FTM_CNTIN_REG(base) & FTM_CNTIN_INIT_MASK) >> FTM_CNTIN_INIT_SHIFT)
+#define FTM_BRD_CNTIN_INIT(base) (FTM_RD_CNTIN_INIT(base))
+
+/*! @brief Set the INIT field to a new value. */
+#define FTM_WR_CNTIN_INIT(base, value) (FTM_RMW_CNTIN(base, FTM_CNTIN_INIT_MASK, FTM_CNTIN_INIT(value)))
+#define FTM_BWR_CNTIN_INIT(base, value) (FTM_WR_CNTIN_INIT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_STATUS - Capture And Compare Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_STATUS - Capture And Compare Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
+ * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
+ * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
+ * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
+ * STATUS. Hardware sets the individual channel flags when an event occurs on the
+ * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
+ * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
+ * occurs between the read and write operations, the write operation has no effect;
+ * therefore, CHnF remains set indicating an event has occurred. In this case, a
+ * CHnF interrupt request is not lost due to the clearing sequence for a previous
+ * CHnF. The STATUS register should be used only in Combine mode.
+ */
+/*!
+ * @name Constants and macros for entire FTM_STATUS register
+ */
+/*@{*/
+#define FTM_RD_STATUS(base)      (FTM_STATUS_REG(base))
+#define FTM_WR_STATUS(base, value) (FTM_STATUS_REG(base) = (value))
+#define FTM_RMW_STATUS(base, mask, value) (FTM_WR_STATUS(base, (FTM_RD_STATUS(base) & ~(mask)) | (value)))
+#define FTM_SET_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) |  (value)))
+#define FTM_CLR_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) & ~(value)))
+#define FTM_TOG_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_STATUS bitfields
+ */
+
+/*!
+ * @name Register FTM_STATUS, field CH0F[0] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH0F field. */
+#define FTM_RD_STATUS_CH0F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH0F_MASK) >> FTM_STATUS_CH0F_SHIFT)
+#define FTM_BRD_STATUS_CH0F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH0F_SHIFT))
+
+/*! @brief Set the CH0F field to a new value. */
+#define FTM_WR_STATUS_CH0F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH0F(value)))
+#define FTM_BWR_STATUS_CH0F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH0F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH1F[1] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH1F field. */
+#define FTM_RD_STATUS_CH1F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH1F_MASK) >> FTM_STATUS_CH1F_SHIFT)
+#define FTM_BRD_STATUS_CH1F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH1F_SHIFT))
+
+/*! @brief Set the CH1F field to a new value. */
+#define FTM_WR_STATUS_CH1F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH1F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH1F(value)))
+#define FTM_BWR_STATUS_CH1F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH1F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH2F[2] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH2F field. */
+#define FTM_RD_STATUS_CH2F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH2F_MASK) >> FTM_STATUS_CH2F_SHIFT)
+#define FTM_BRD_STATUS_CH2F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH2F_SHIFT))
+
+/*! @brief Set the CH2F field to a new value. */
+#define FTM_WR_STATUS_CH2F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH2F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH2F(value)))
+#define FTM_BWR_STATUS_CH2F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH2F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH3F[3] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH3F field. */
+#define FTM_RD_STATUS_CH3F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH3F_MASK) >> FTM_STATUS_CH3F_SHIFT)
+#define FTM_BRD_STATUS_CH3F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH3F_SHIFT))
+
+/*! @brief Set the CH3F field to a new value. */
+#define FTM_WR_STATUS_CH3F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH3F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH3F(value)))
+#define FTM_BWR_STATUS_CH3F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH3F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH4F[4] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH4F field. */
+#define FTM_RD_STATUS_CH4F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH4F_MASK) >> FTM_STATUS_CH4F_SHIFT)
+#define FTM_BRD_STATUS_CH4F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH4F_SHIFT))
+
+/*! @brief Set the CH4F field to a new value. */
+#define FTM_WR_STATUS_CH4F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH4F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH4F(value)))
+#define FTM_BWR_STATUS_CH4F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH4F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH5F[5] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH5F field. */
+#define FTM_RD_STATUS_CH5F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH5F_MASK) >> FTM_STATUS_CH5F_SHIFT)
+#define FTM_BRD_STATUS_CH5F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH5F_SHIFT))
+
+/*! @brief Set the CH5F field to a new value. */
+#define FTM_WR_STATUS_CH5F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH5F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH5F(value)))
+#define FTM_BWR_STATUS_CH5F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH5F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH6F[6] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH6F field. */
+#define FTM_RD_STATUS_CH6F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH6F_MASK) >> FTM_STATUS_CH6F_SHIFT)
+#define FTM_BRD_STATUS_CH6F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH6F_SHIFT))
+
+/*! @brief Set the CH6F field to a new value. */
+#define FTM_WR_STATUS_CH6F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH6F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH6F(value)))
+#define FTM_BWR_STATUS_CH6F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH6F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH7F[7] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH7F field. */
+#define FTM_RD_STATUS_CH7F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH7F_MASK) >> FTM_STATUS_CH7F_SHIFT)
+#define FTM_BRD_STATUS_CH7F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH7F_SHIFT))
+
+/*! @brief Set the CH7F field to a new value. */
+#define FTM_WR_STATUS_CH7F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH7F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK), FTM_STATUS_CH7F(value)))
+#define FTM_BWR_STATUS_CH7F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH7F_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_MODE - Features Mode Selection
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_MODE - Features Mode Selection (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * This register contains the global enable bit for FTM-specific features and
+ * the control bits used to configure: Fault control mode and interrupt Capture
+ * Test mode PWM synchronization Write protection Channel output initialization
+ * These controls relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire FTM_MODE register
+ */
+/*@{*/
+#define FTM_RD_MODE(base)        (FTM_MODE_REG(base))
+#define FTM_WR_MODE(base, value) (FTM_MODE_REG(base) = (value))
+#define FTM_RMW_MODE(base, mask, value) (FTM_WR_MODE(base, (FTM_RD_MODE(base) & ~(mask)) | (value)))
+#define FTM_SET_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) |  (value)))
+#define FTM_CLR_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) & ~(value)))
+#define FTM_TOG_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_MODE bitfields
+ */
+
+/*!
+ * @name Register FTM_MODE, field FTMEN[0] (RW)
+ *
+ * This field is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Only the TPM-compatible registers (first set of registers) can be
+ *     used without any restriction. Do not use the FTM-specific registers.
+ * - 0b1 - All registers including the FTM-specific registers (second set of
+ *     registers) are available for use with no restrictions.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FTMEN field. */
+#define FTM_RD_MODE_FTMEN(base) ((FTM_MODE_REG(base) & FTM_MODE_FTMEN_MASK) >> FTM_MODE_FTMEN_SHIFT)
+#define FTM_BRD_MODE_FTMEN(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FTMEN_SHIFT))
+
+/*! @brief Set the FTMEN field to a new value. */
+#define FTM_WR_MODE_FTMEN(base, value) (FTM_RMW_MODE(base, FTM_MODE_FTMEN_MASK, FTM_MODE_FTMEN(value)))
+#define FTM_BWR_MODE_FTMEN(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FTMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field INIT[1] (RW)
+ *
+ * When a 1 is written to INIT bit the channels output is initialized according
+ * to the state of their corresponding bit in the OUTINIT register. Writing a 0
+ * to INIT bit has no effect. The INIT bit is always read as 0.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_INIT field. */
+#define FTM_RD_MODE_INIT(base) ((FTM_MODE_REG(base) & FTM_MODE_INIT_MASK) >> FTM_MODE_INIT_SHIFT)
+#define FTM_BRD_MODE_INIT(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_INIT_SHIFT))
+
+/*! @brief Set the INIT field to a new value. */
+#define FTM_WR_MODE_INIT(base, value) (FTM_RMW_MODE(base, FTM_MODE_INIT_MASK, FTM_MODE_INIT(value)))
+#define FTM_BWR_MODE_INIT(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_INIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field WPDIS[2] (RW)
+ *
+ * When write protection is enabled (WPDIS = 0), write protected bits cannot be
+ * written. When write protection is disabled (WPDIS = 1), write protected bits
+ * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
+ * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
+ * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
+ *
+ * Values:
+ * - 0b0 - Write protection is enabled.
+ * - 0b1 - Write protection is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_WPDIS field. */
+#define FTM_RD_MODE_WPDIS(base) ((FTM_MODE_REG(base) & FTM_MODE_WPDIS_MASK) >> FTM_MODE_WPDIS_SHIFT)
+#define FTM_BRD_MODE_WPDIS(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_WPDIS_SHIFT))
+
+/*! @brief Set the WPDIS field to a new value. */
+#define FTM_WR_MODE_WPDIS(base, value) (FTM_RMW_MODE(base, FTM_MODE_WPDIS_MASK, FTM_MODE_WPDIS(value)))
+#define FTM_BWR_MODE_WPDIS(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_WPDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field PWMSYNC[3] (RW)
+ *
+ * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
+ * synchronization. See PWM synchronization. The PWMSYNC bit configures the
+ * synchronization when SYNCMODE is 0.
+ *
+ * Values:
+ * - 0b0 - No restrictions. Software and hardware triggers can be used by MOD,
+ *     CnV, OUTMASK, and FTM counter synchronization.
+ * - 0b1 - Software trigger can only be used by MOD and CnV synchronization, and
+ *     hardware triggers can only be used by OUTMASK and FTM counter
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_PWMSYNC field. */
+#define FTM_RD_MODE_PWMSYNC(base) ((FTM_MODE_REG(base) & FTM_MODE_PWMSYNC_MASK) >> FTM_MODE_PWMSYNC_SHIFT)
+#define FTM_BRD_MODE_PWMSYNC(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_PWMSYNC_SHIFT))
+
+/*! @brief Set the PWMSYNC field to a new value. */
+#define FTM_WR_MODE_PWMSYNC(base, value) (FTM_RMW_MODE(base, FTM_MODE_PWMSYNC_MASK, FTM_MODE_PWMSYNC(value)))
+#define FTM_BWR_MODE_PWMSYNC(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_PWMSYNC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field CAPTEST[4] (RW)
+ *
+ * Enables the capture test mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Capture test mode is disabled.
+ * - 0b1 - Capture test mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_CAPTEST field. */
+#define FTM_RD_MODE_CAPTEST(base) ((FTM_MODE_REG(base) & FTM_MODE_CAPTEST_MASK) >> FTM_MODE_CAPTEST_SHIFT)
+#define FTM_BRD_MODE_CAPTEST(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_CAPTEST_SHIFT))
+
+/*! @brief Set the CAPTEST field to a new value. */
+#define FTM_WR_MODE_CAPTEST(base, value) (FTM_RMW_MODE(base, FTM_MODE_CAPTEST_MASK, FTM_MODE_CAPTEST(value)))
+#define FTM_BWR_MODE_CAPTEST(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_CAPTEST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field FAULTM[6:5] (RW)
+ *
+ * Defines the FTM fault control mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b00 - Fault control is disabled for all channels.
+ * - 0b01 - Fault control is enabled for even channels only (channels 0, 2, 4,
+ *     and 6), and the selected mode is the manual fault clearing.
+ * - 0b10 - Fault control is enabled for all channels, and the selected mode is
+ *     the manual fault clearing.
+ * - 0b11 - Fault control is enabled for all channels, and the selected mode is
+ *     the automatic fault clearing.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FAULTM field. */
+#define FTM_RD_MODE_FAULTM(base) ((FTM_MODE_REG(base) & FTM_MODE_FAULTM_MASK) >> FTM_MODE_FAULTM_SHIFT)
+#define FTM_BRD_MODE_FAULTM(base) (FTM_RD_MODE_FAULTM(base))
+
+/*! @brief Set the FAULTM field to a new value. */
+#define FTM_WR_MODE_FAULTM(base, value) (FTM_RMW_MODE(base, FTM_MODE_FAULTM_MASK, FTM_MODE_FAULTM(value)))
+#define FTM_BWR_MODE_FAULTM(base, value) (FTM_WR_MODE_FAULTM(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field FAULTIE[7] (RW)
+ *
+ * Enables the generation of an interrupt when a fault is detected by FTM and
+ * the FTM fault control is enabled.
+ *
+ * Values:
+ * - 0b0 - Fault control interrupt is disabled.
+ * - 0b1 - Fault control interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FAULTIE field. */
+#define FTM_RD_MODE_FAULTIE(base) ((FTM_MODE_REG(base) & FTM_MODE_FAULTIE_MASK) >> FTM_MODE_FAULTIE_SHIFT)
+#define FTM_BRD_MODE_FAULTIE(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FAULTIE_SHIFT))
+
+/*! @brief Set the FAULTIE field to a new value. */
+#define FTM_WR_MODE_FAULTIE(base, value) (FTM_RMW_MODE(base, FTM_MODE_FAULTIE_MASK, FTM_MODE_FAULTIE(value)))
+#define FTM_BWR_MODE_FAULTIE(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FAULTIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SYNC - Synchronization
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SYNC - Synchronization (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the PWM synchronization. A synchronization event can
+ * perform the synchronized update of MOD, CV, and OUTMASK registers with the
+ * value of their write buffer and the FTM counter initialization. The software
+ * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
+ * potential conflict if used together when SYNCMODE = 0. Use only hardware or
+ * software triggers but not both at the same time, otherwise unpredictable behavior
+ * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
+ * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
+ * all enabled channels simultaneously. The use of the loading point selection
+ * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
+ * bits, is likely to result in unpredictable behavior. The synchronization
+ * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
+ * register) bits. See PWM synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SYNC register
+ */
+/*@{*/
+#define FTM_RD_SYNC(base)        (FTM_SYNC_REG(base))
+#define FTM_WR_SYNC(base, value) (FTM_SYNC_REG(base) = (value))
+#define FTM_RMW_SYNC(base, mask, value) (FTM_WR_SYNC(base, (FTM_RD_SYNC(base) & ~(mask)) | (value)))
+#define FTM_SET_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) |  (value)))
+#define FTM_CLR_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) & ~(value)))
+#define FTM_TOG_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SYNC bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNC, field CNTMIN[0] (RW)
+ *
+ * Selects the minimum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMIN is one, the selected loading point is when the
+ * FTM counter reaches its minimum value (CNTIN register).
+ *
+ * Values:
+ * - 0b0 - The minimum loading point is disabled.
+ * - 0b1 - The minimum loading point is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_CNTMIN field. */
+#define FTM_RD_SYNC_CNTMIN(base) ((FTM_SYNC_REG(base) & FTM_SYNC_CNTMIN_MASK) >> FTM_SYNC_CNTMIN_SHIFT)
+#define FTM_BRD_SYNC_CNTMIN(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMIN_SHIFT))
+
+/*! @brief Set the CNTMIN field to a new value. */
+#define FTM_WR_SYNC_CNTMIN(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_CNTMIN_MASK, FTM_SYNC_CNTMIN(value)))
+#define FTM_BWR_SYNC_CNTMIN(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMIN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field CNTMAX[1] (RW)
+ *
+ * Selects the maximum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
+ * counter reaches its maximum value (MOD register).
+ *
+ * Values:
+ * - 0b0 - The maximum loading point is disabled.
+ * - 0b1 - The maximum loading point is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_CNTMAX field. */
+#define FTM_RD_SYNC_CNTMAX(base) ((FTM_SYNC_REG(base) & FTM_SYNC_CNTMAX_MASK) >> FTM_SYNC_CNTMAX_SHIFT)
+#define FTM_BRD_SYNC_CNTMAX(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMAX_SHIFT))
+
+/*! @brief Set the CNTMAX field to a new value. */
+#define FTM_WR_SYNC_CNTMAX(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_CNTMAX_MASK, FTM_SYNC_CNTMAX(value)))
+#define FTM_BWR_SYNC_CNTMAX(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMAX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field REINIT[2] (RW)
+ *
+ * Determines if the FTM counter is reinitialized when the selected trigger for
+ * the synchronization is detected. The REINIT bit configures the synchronization
+ * when SYNCMODE is zero.
+ *
+ * Values:
+ * - 0b0 - FTM counter continues to count normally.
+ * - 0b1 - FTM counter is updated with its initial value when the selected
+ *     trigger is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_REINIT field. */
+#define FTM_RD_SYNC_REINIT(base) ((FTM_SYNC_REG(base) & FTM_SYNC_REINIT_MASK) >> FTM_SYNC_REINIT_SHIFT)
+#define FTM_BRD_SYNC_REINIT(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_REINIT_SHIFT))
+
+/*! @brief Set the REINIT field to a new value. */
+#define FTM_WR_SYNC_REINIT(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_REINIT_MASK, FTM_SYNC_REINIT(value)))
+#define FTM_BWR_SYNC_REINIT(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_REINIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
+ *
+ * Selects when the OUTMASK register is updated with the value of its buffer.
+ *
+ * Values:
+ * - 0b0 - OUTMASK register is updated with the value of its buffer in all
+ *     rising edges of the system clock.
+ * - 0b1 - OUTMASK register is updated with the value of its buffer only by the
+ *     PWM synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */
+#define FTM_RD_SYNC_SYNCHOM(base) ((FTM_SYNC_REG(base) & FTM_SYNC_SYNCHOM_MASK) >> FTM_SYNC_SYNCHOM_SHIFT)
+#define FTM_BRD_SYNC_SYNCHOM(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SYNCHOM_SHIFT))
+
+/*! @brief Set the SYNCHOM field to a new value. */
+#define FTM_WR_SYNC_SYNCHOM(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_SYNCHOM_MASK, FTM_SYNC_SYNCHOM(value)))
+#define FTM_BWR_SYNC_SYNCHOM(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SYNCHOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG0[4] (RW)
+ *
+ * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
+ * occurs when a rising edge is detected at the trigger 0 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG0 field. */
+#define FTM_RD_SYNC_TRIG0(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG0_MASK) >> FTM_SYNC_TRIG0_SHIFT)
+#define FTM_BRD_SYNC_TRIG0(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG0_SHIFT))
+
+/*! @brief Set the TRIG0 field to a new value. */
+#define FTM_WR_SYNC_TRIG0(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG0_MASK, FTM_SYNC_TRIG0(value)))
+#define FTM_BWR_SYNC_TRIG0(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG1[5] (RW)
+ *
+ * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
+ * happens when a rising edge is detected at the trigger 1 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG1 field. */
+#define FTM_RD_SYNC_TRIG1(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG1_MASK) >> FTM_SYNC_TRIG1_SHIFT)
+#define FTM_BRD_SYNC_TRIG1(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG1_SHIFT))
+
+/*! @brief Set the TRIG1 field to a new value. */
+#define FTM_WR_SYNC_TRIG1(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG1_MASK, FTM_SYNC_TRIG1(value)))
+#define FTM_BWR_SYNC_TRIG1(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG2[6] (RW)
+ *
+ * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
+ * happens when a rising edge is detected at the trigger 2 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG2 field. */
+#define FTM_RD_SYNC_TRIG2(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG2_MASK) >> FTM_SYNC_TRIG2_SHIFT)
+#define FTM_BRD_SYNC_TRIG2(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG2_SHIFT))
+
+/*! @brief Set the TRIG2 field to a new value. */
+#define FTM_WR_SYNC_TRIG2(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG2_MASK, FTM_SYNC_TRIG2(value)))
+#define FTM_BWR_SYNC_TRIG2(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field SWSYNC[7] (RW)
+ *
+ * Selects the software trigger as the PWM synchronization trigger. The software
+ * trigger happens when a 1 is written to SWSYNC bit.
+ *
+ * Values:
+ * - 0b0 - Software trigger is not selected.
+ * - 0b1 - Software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_SWSYNC field. */
+#define FTM_RD_SYNC_SWSYNC(base) ((FTM_SYNC_REG(base) & FTM_SYNC_SWSYNC_MASK) >> FTM_SYNC_SWSYNC_SHIFT)
+#define FTM_BRD_SYNC_SWSYNC(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SWSYNC_SHIFT))
+
+/*! @brief Set the SWSYNC field to a new value. */
+#define FTM_WR_SYNC_SWSYNC(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_SWSYNC_MASK, FTM_SYNC_SWSYNC(value)))
+#define FTM_BWR_SYNC_SWSYNC(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SWSYNC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_OUTINIT - Initial State For Channels Output
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_OUTINIT - Initial State For Channels Output (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire FTM_OUTINIT register
+ */
+/*@{*/
+#define FTM_RD_OUTINIT(base)     (FTM_OUTINIT_REG(base))
+#define FTM_WR_OUTINIT(base, value) (FTM_OUTINIT_REG(base) = (value))
+#define FTM_RMW_OUTINIT(base, mask, value) (FTM_WR_OUTINIT(base, (FTM_RD_OUTINIT(base) & ~(mask)) | (value)))
+#define FTM_SET_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) |  (value)))
+#define FTM_CLR_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) & ~(value)))
+#define FTM_TOG_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_OUTINIT bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */
+#define FTM_RD_OUTINIT_CH0OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH0OI_MASK) >> FTM_OUTINIT_CH0OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH0OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH0OI_SHIFT))
+
+/*! @brief Set the CH0OI field to a new value. */
+#define FTM_WR_OUTINIT_CH0OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH0OI_MASK, FTM_OUTINIT_CH0OI(value)))
+#define FTM_BWR_OUTINIT_CH0OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH0OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */
+#define FTM_RD_OUTINIT_CH1OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH1OI_MASK) >> FTM_OUTINIT_CH1OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH1OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH1OI_SHIFT))
+
+/*! @brief Set the CH1OI field to a new value. */
+#define FTM_WR_OUTINIT_CH1OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH1OI_MASK, FTM_OUTINIT_CH1OI(value)))
+#define FTM_BWR_OUTINIT_CH1OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH1OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */
+#define FTM_RD_OUTINIT_CH2OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH2OI_MASK) >> FTM_OUTINIT_CH2OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH2OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH2OI_SHIFT))
+
+/*! @brief Set the CH2OI field to a new value. */
+#define FTM_WR_OUTINIT_CH2OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH2OI_MASK, FTM_OUTINIT_CH2OI(value)))
+#define FTM_BWR_OUTINIT_CH2OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH2OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */
+#define FTM_RD_OUTINIT_CH3OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH3OI_MASK) >> FTM_OUTINIT_CH3OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH3OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH3OI_SHIFT))
+
+/*! @brief Set the CH3OI field to a new value. */
+#define FTM_WR_OUTINIT_CH3OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH3OI_MASK, FTM_OUTINIT_CH3OI(value)))
+#define FTM_BWR_OUTINIT_CH3OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH3OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */
+#define FTM_RD_OUTINIT_CH4OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH4OI_MASK) >> FTM_OUTINIT_CH4OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH4OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH4OI_SHIFT))
+
+/*! @brief Set the CH4OI field to a new value. */
+#define FTM_WR_OUTINIT_CH4OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH4OI_MASK, FTM_OUTINIT_CH4OI(value)))
+#define FTM_BWR_OUTINIT_CH4OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH4OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */
+#define FTM_RD_OUTINIT_CH5OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH5OI_MASK) >> FTM_OUTINIT_CH5OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH5OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH5OI_SHIFT))
+
+/*! @brief Set the CH5OI field to a new value. */
+#define FTM_WR_OUTINIT_CH5OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH5OI_MASK, FTM_OUTINIT_CH5OI(value)))
+#define FTM_BWR_OUTINIT_CH5OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH5OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */
+#define FTM_RD_OUTINIT_CH6OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH6OI_MASK) >> FTM_OUTINIT_CH6OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH6OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH6OI_SHIFT))
+
+/*! @brief Set the CH6OI field to a new value. */
+#define FTM_WR_OUTINIT_CH6OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH6OI_MASK, FTM_OUTINIT_CH6OI(value)))
+#define FTM_BWR_OUTINIT_CH6OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH6OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */
+#define FTM_RD_OUTINIT_CH7OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH7OI_MASK) >> FTM_OUTINIT_CH7OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH7OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH7OI_SHIFT))
+
+/*! @brief Set the CH7OI field to a new value. */
+#define FTM_WR_OUTINIT_CH7OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH7OI_MASK, FTM_OUTINIT_CH7OI(value)))
+#define FTM_BWR_OUTINIT_CH7OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH7OI_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_OUTMASK - Output Mask
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_OUTMASK - Output Mask (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides a mask for each FTM channel. The mask of a channel
+ * determines if its output responds, that is, it is masked or not, when a match
+ * occurs. This feature is used for BLDC control where the PWM signal is presented
+ * to an electric motor at specific times to provide electronic commutation. Any
+ * write to the OUTMASK register, stores the value in its write buffer. The
+ * register is updated with the value of its write buffer according to PWM
+ * synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_OUTMASK register
+ */
+/*@{*/
+#define FTM_RD_OUTMASK(base)     (FTM_OUTMASK_REG(base))
+#define FTM_WR_OUTMASK(base, value) (FTM_OUTMASK_REG(base) = (value))
+#define FTM_RMW_OUTMASK(base, mask, value) (FTM_WR_OUTMASK(base, (FTM_RD_OUTMASK(base) & ~(mask)) | (value)))
+#define FTM_SET_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) |  (value)))
+#define FTM_CLR_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) & ~(value)))
+#define FTM_TOG_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_OUTMASK bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */
+#define FTM_RD_OUTMASK_CH0OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH0OM_MASK) >> FTM_OUTMASK_CH0OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH0OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH0OM_SHIFT))
+
+/*! @brief Set the CH0OM field to a new value. */
+#define FTM_WR_OUTMASK_CH0OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH0OM_MASK, FTM_OUTMASK_CH0OM(value)))
+#define FTM_BWR_OUTMASK_CH0OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH0OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */
+#define FTM_RD_OUTMASK_CH1OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH1OM_MASK) >> FTM_OUTMASK_CH1OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH1OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH1OM_SHIFT))
+
+/*! @brief Set the CH1OM field to a new value. */
+#define FTM_WR_OUTMASK_CH1OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH1OM_MASK, FTM_OUTMASK_CH1OM(value)))
+#define FTM_BWR_OUTMASK_CH1OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH1OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */
+#define FTM_RD_OUTMASK_CH2OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH2OM_MASK) >> FTM_OUTMASK_CH2OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH2OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH2OM_SHIFT))
+
+/*! @brief Set the CH2OM field to a new value. */
+#define FTM_WR_OUTMASK_CH2OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH2OM_MASK, FTM_OUTMASK_CH2OM(value)))
+#define FTM_BWR_OUTMASK_CH2OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH2OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */
+#define FTM_RD_OUTMASK_CH3OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH3OM_MASK) >> FTM_OUTMASK_CH3OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH3OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH3OM_SHIFT))
+
+/*! @brief Set the CH3OM field to a new value. */
+#define FTM_WR_OUTMASK_CH3OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH3OM_MASK, FTM_OUTMASK_CH3OM(value)))
+#define FTM_BWR_OUTMASK_CH3OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH3OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */
+#define FTM_RD_OUTMASK_CH4OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH4OM_MASK) >> FTM_OUTMASK_CH4OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH4OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH4OM_SHIFT))
+
+/*! @brief Set the CH4OM field to a new value. */
+#define FTM_WR_OUTMASK_CH4OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH4OM_MASK, FTM_OUTMASK_CH4OM(value)))
+#define FTM_BWR_OUTMASK_CH4OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH4OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */
+#define FTM_RD_OUTMASK_CH5OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH5OM_MASK) >> FTM_OUTMASK_CH5OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH5OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH5OM_SHIFT))
+
+/*! @brief Set the CH5OM field to a new value. */
+#define FTM_WR_OUTMASK_CH5OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH5OM_MASK, FTM_OUTMASK_CH5OM(value)))
+#define FTM_BWR_OUTMASK_CH5OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH5OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */
+#define FTM_RD_OUTMASK_CH6OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH6OM_MASK) >> FTM_OUTMASK_CH6OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH6OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH6OM_SHIFT))
+
+/*! @brief Set the CH6OM field to a new value. */
+#define FTM_WR_OUTMASK_CH6OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH6OM_MASK, FTM_OUTMASK_CH6OM(value)))
+#define FTM_BWR_OUTMASK_CH6OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH6OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */
+#define FTM_RD_OUTMASK_CH7OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH7OM_MASK) >> FTM_OUTMASK_CH7OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH7OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH7OM_SHIFT))
+
+/*! @brief Set the CH7OM field to a new value. */
+#define FTM_WR_OUTMASK_CH7OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH7OM_MASK, FTM_OUTMASK_CH7OM(value)))
+#define FTM_BWR_OUTMASK_CH7OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH7OM_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_COMBINE - Function For Linked Channels
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_COMBINE - Function For Linked Channels (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the control bits used to configure the fault control,
+ * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
+ * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
+ * 4, and 6.
+ */
+/*!
+ * @name Constants and macros for entire FTM_COMBINE register
+ */
+/*@{*/
+#define FTM_RD_COMBINE(base)     (FTM_COMBINE_REG(base))
+#define FTM_WR_COMBINE(base, value) (FTM_COMBINE_REG(base) = (value))
+#define FTM_RMW_COMBINE(base, mask, value) (FTM_WR_COMBINE(base, (FTM_RD_COMBINE(base) & ~(mask)) | (value)))
+#define FTM_SET_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) |  (value)))
+#define FTM_CLR_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) & ~(value)))
+#define FTM_TOG_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_COMBINE bitfields
+ */
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */
+#define FTM_RD_COMBINE_COMBINE0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE0_MASK) >> FTM_COMBINE_COMBINE0_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE0_SHIFT))
+
+/*! @brief Set the COMBINE0 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE0_MASK, FTM_COMBINE_COMBINE0(value)))
+#define FTM_BWR_COMBINE_COMBINE0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP0[1] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP0 field. */
+#define FTM_RD_COMBINE_COMP0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP0_MASK) >> FTM_COMBINE_COMP0_SHIFT)
+#define FTM_BRD_COMBINE_COMP0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP0_SHIFT))
+
+/*! @brief Set the COMP0 field to a new value. */
+#define FTM_WR_COMBINE_COMP0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP0_MASK, FTM_COMBINE_COMP0(value)))
+#define FTM_BWR_COMBINE_COMP0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */
+#define FTM_RD_COMBINE_DECAPEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN0_MASK) >> FTM_COMBINE_DECAPEN0_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN0_SHIFT))
+
+/*! @brief Set the DECAPEN0 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN0_MASK, FTM_COMBINE_DECAPEN0(value)))
+#define FTM_BWR_COMBINE_DECAPEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP0[3] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */
+#define FTM_RD_COMBINE_DECAP0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP0_MASK) >> FTM_COMBINE_DECAP0_SHIFT)
+#define FTM_BRD_COMBINE_DECAP0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP0_SHIFT))
+
+/*! @brief Set the DECAP0 field to a new value. */
+#define FTM_WR_COMBINE_DECAP0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP0_MASK, FTM_COMBINE_DECAP0(value)))
+#define FTM_BWR_COMBINE_DECAP0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN0[4] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */
+#define FTM_RD_COMBINE_DTEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN0_MASK) >> FTM_COMBINE_DTEN0_SHIFT)
+#define FTM_BRD_COMBINE_DTEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN0_SHIFT))
+
+/*! @brief Set the DTEN0 field to a new value. */
+#define FTM_WR_COMBINE_DTEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN0_MASK, FTM_COMBINE_DTEN0(value)))
+#define FTM_BWR_COMBINE_DTEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */
+#define FTM_RD_COMBINE_SYNCEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN0_MASK) >> FTM_COMBINE_SYNCEN0_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN0_SHIFT))
+
+/*! @brief Set the SYNCEN0 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN0_MASK, FTM_COMBINE_SYNCEN0(value)))
+#define FTM_BWR_COMBINE_SYNCEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */
+#define FTM_RD_COMBINE_FAULTEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN0_MASK) >> FTM_COMBINE_FAULTEN0_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN0_SHIFT))
+
+/*! @brief Set the FAULTEN0 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN0_MASK, FTM_COMBINE_FAULTEN0(value)))
+#define FTM_BWR_COMBINE_FAULTEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */
+#define FTM_RD_COMBINE_COMBINE1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE1_MASK) >> FTM_COMBINE_COMBINE1_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE1_SHIFT))
+
+/*! @brief Set the COMBINE1 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE1_MASK, FTM_COMBINE_COMBINE1(value)))
+#define FTM_BWR_COMBINE_COMBINE1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP1[9] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP1 field. */
+#define FTM_RD_COMBINE_COMP1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP1_MASK) >> FTM_COMBINE_COMP1_SHIFT)
+#define FTM_BRD_COMBINE_COMP1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP1_SHIFT))
+
+/*! @brief Set the COMP1 field to a new value. */
+#define FTM_WR_COMBINE_COMP1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP1_MASK, FTM_COMBINE_COMP1(value)))
+#define FTM_BWR_COMBINE_COMP1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */
+#define FTM_RD_COMBINE_DECAPEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN1_MASK) >> FTM_COMBINE_DECAPEN1_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN1_SHIFT))
+
+/*! @brief Set the DECAPEN1 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN1_MASK, FTM_COMBINE_DECAPEN1(value)))
+#define FTM_BWR_COMBINE_DECAPEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP1[11] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */
+#define FTM_RD_COMBINE_DECAP1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP1_MASK) >> FTM_COMBINE_DECAP1_SHIFT)
+#define FTM_BRD_COMBINE_DECAP1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP1_SHIFT))
+
+/*! @brief Set the DECAP1 field to a new value. */
+#define FTM_WR_COMBINE_DECAP1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP1_MASK, FTM_COMBINE_DECAP1(value)))
+#define FTM_BWR_COMBINE_DECAP1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN1[12] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */
+#define FTM_RD_COMBINE_DTEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN1_MASK) >> FTM_COMBINE_DTEN1_SHIFT)
+#define FTM_BRD_COMBINE_DTEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN1_SHIFT))
+
+/*! @brief Set the DTEN1 field to a new value. */
+#define FTM_WR_COMBINE_DTEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN1_MASK, FTM_COMBINE_DTEN1(value)))
+#define FTM_BWR_COMBINE_DTEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */
+#define FTM_RD_COMBINE_SYNCEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN1_MASK) >> FTM_COMBINE_SYNCEN1_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN1_SHIFT))
+
+/*! @brief Set the SYNCEN1 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN1_MASK, FTM_COMBINE_SYNCEN1(value)))
+#define FTM_BWR_COMBINE_SYNCEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */
+#define FTM_RD_COMBINE_FAULTEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN1_MASK) >> FTM_COMBINE_FAULTEN1_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN1_SHIFT))
+
+/*! @brief Set the FAULTEN1 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN1_MASK, FTM_COMBINE_FAULTEN1(value)))
+#define FTM_BWR_COMBINE_FAULTEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */
+#define FTM_RD_COMBINE_COMBINE2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE2_MASK) >> FTM_COMBINE_COMBINE2_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE2_SHIFT))
+
+/*! @brief Set the COMBINE2 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE2_MASK, FTM_COMBINE_COMBINE2(value)))
+#define FTM_BWR_COMBINE_COMBINE2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP2[17] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP2 field. */
+#define FTM_RD_COMBINE_COMP2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP2_MASK) >> FTM_COMBINE_COMP2_SHIFT)
+#define FTM_BRD_COMBINE_COMP2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP2_SHIFT))
+
+/*! @brief Set the COMP2 field to a new value. */
+#define FTM_WR_COMBINE_COMP2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP2_MASK, FTM_COMBINE_COMP2(value)))
+#define FTM_BWR_COMBINE_COMP2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */
+#define FTM_RD_COMBINE_DECAPEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN2_MASK) >> FTM_COMBINE_DECAPEN2_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN2_SHIFT))
+
+/*! @brief Set the DECAPEN2 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN2_MASK, FTM_COMBINE_DECAPEN2(value)))
+#define FTM_BWR_COMBINE_DECAPEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP2[19] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */
+#define FTM_RD_COMBINE_DECAP2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP2_MASK) >> FTM_COMBINE_DECAP2_SHIFT)
+#define FTM_BRD_COMBINE_DECAP2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP2_SHIFT))
+
+/*! @brief Set the DECAP2 field to a new value. */
+#define FTM_WR_COMBINE_DECAP2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP2_MASK, FTM_COMBINE_DECAP2(value)))
+#define FTM_BWR_COMBINE_DECAP2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN2[20] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */
+#define FTM_RD_COMBINE_DTEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN2_MASK) >> FTM_COMBINE_DTEN2_SHIFT)
+#define FTM_BRD_COMBINE_DTEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN2_SHIFT))
+
+/*! @brief Set the DTEN2 field to a new value. */
+#define FTM_WR_COMBINE_DTEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN2_MASK, FTM_COMBINE_DTEN2(value)))
+#define FTM_BWR_COMBINE_DTEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */
+#define FTM_RD_COMBINE_SYNCEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN2_MASK) >> FTM_COMBINE_SYNCEN2_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN2_SHIFT))
+
+/*! @brief Set the SYNCEN2 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN2_MASK, FTM_COMBINE_SYNCEN2(value)))
+#define FTM_BWR_COMBINE_SYNCEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */
+#define FTM_RD_COMBINE_FAULTEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN2_MASK) >> FTM_COMBINE_FAULTEN2_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN2_SHIFT))
+
+/*! @brief Set the FAULTEN2 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN2_MASK, FTM_COMBINE_FAULTEN2(value)))
+#define FTM_BWR_COMBINE_FAULTEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */
+#define FTM_RD_COMBINE_COMBINE3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE3_MASK) >> FTM_COMBINE_COMBINE3_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE3_SHIFT))
+
+/*! @brief Set the COMBINE3 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE3_MASK, FTM_COMBINE_COMBINE3(value)))
+#define FTM_BWR_COMBINE_COMBINE3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP3[25] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP3 field. */
+#define FTM_RD_COMBINE_COMP3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP3_MASK) >> FTM_COMBINE_COMP3_SHIFT)
+#define FTM_BRD_COMBINE_COMP3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP3_SHIFT))
+
+/*! @brief Set the COMP3 field to a new value. */
+#define FTM_WR_COMBINE_COMP3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP3_MASK, FTM_COMBINE_COMP3(value)))
+#define FTM_BWR_COMBINE_COMP3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */
+#define FTM_RD_COMBINE_DECAPEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN3_MASK) >> FTM_COMBINE_DECAPEN3_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN3_SHIFT))
+
+/*! @brief Set the DECAPEN3 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN3_MASK, FTM_COMBINE_DECAPEN3(value)))
+#define FTM_BWR_COMBINE_DECAPEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP3[27] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */
+#define FTM_RD_COMBINE_DECAP3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP3_MASK) >> FTM_COMBINE_DECAP3_SHIFT)
+#define FTM_BRD_COMBINE_DECAP3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP3_SHIFT))
+
+/*! @brief Set the DECAP3 field to a new value. */
+#define FTM_WR_COMBINE_DECAP3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP3_MASK, FTM_COMBINE_DECAP3(value)))
+#define FTM_BWR_COMBINE_DECAP3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN3[28] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */
+#define FTM_RD_COMBINE_DTEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN3_MASK) >> FTM_COMBINE_DTEN3_SHIFT)
+#define FTM_BRD_COMBINE_DTEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN3_SHIFT))
+
+/*! @brief Set the DTEN3 field to a new value. */
+#define FTM_WR_COMBINE_DTEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN3_MASK, FTM_COMBINE_DTEN3(value)))
+#define FTM_BWR_COMBINE_DTEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */
+#define FTM_RD_COMBINE_SYNCEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN3_MASK) >> FTM_COMBINE_SYNCEN3_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN3_SHIFT))
+
+/*! @brief Set the SYNCEN3 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN3_MASK, FTM_COMBINE_SYNCEN3(value)))
+#define FTM_BWR_COMBINE_SYNCEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */
+#define FTM_RD_COMBINE_FAULTEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN3_MASK) >> FTM_COMBINE_FAULTEN3_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN3_SHIFT))
+
+/*! @brief Set the FAULTEN3 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN3_MASK, FTM_COMBINE_FAULTEN3(value)))
+#define FTM_BWR_COMBINE_FAULTEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN3_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_DEADTIME - Deadtime Insertion Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_DEADTIME - Deadtime Insertion Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the deadtime prescaler factor and deadtime value. All
+ * FTM channels use this clock prescaler and this deadtime value for the deadtime
+ * insertion.
+ */
+/*!
+ * @name Constants and macros for entire FTM_DEADTIME register
+ */
+/*@{*/
+#define FTM_RD_DEADTIME(base)    (FTM_DEADTIME_REG(base))
+#define FTM_WR_DEADTIME(base, value) (FTM_DEADTIME_REG(base) = (value))
+#define FTM_RMW_DEADTIME(base, mask, value) (FTM_WR_DEADTIME(base, (FTM_RD_DEADTIME(base) & ~(mask)) | (value)))
+#define FTM_SET_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) |  (value)))
+#define FTM_CLR_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) & ~(value)))
+#define FTM_TOG_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_DEADTIME bitfields
+ */
+
+/*!
+ * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
+ *
+ * Selects the deadtime insertion value for the deadtime counter. The deadtime
+ * counter is clocked by a scaled version of the system clock. See the description
+ * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
+ * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
+ * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
+ * This pattern continues up to a possible 63 counts. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */
+#define FTM_RD_DEADTIME_DTVAL(base) ((FTM_DEADTIME_REG(base) & FTM_DEADTIME_DTVAL_MASK) >> FTM_DEADTIME_DTVAL_SHIFT)
+#define FTM_BRD_DEADTIME_DTVAL(base) (FTM_RD_DEADTIME_DTVAL(base))
+
+/*! @brief Set the DTVAL field to a new value. */
+#define FTM_WR_DEADTIME_DTVAL(base, value) (FTM_RMW_DEADTIME(base, FTM_DEADTIME_DTVAL_MASK, FTM_DEADTIME_DTVAL(value)))
+#define FTM_BWR_DEADTIME_DTVAL(base, value) (FTM_WR_DEADTIME_DTVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
+ *
+ * Selects the division factor of the system clock. This prescaled clock is used
+ * by the deadtime counter. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0x - Divide the system clock by 1.
+ * - 0b10 - Divide the system clock by 4.
+ * - 0b11 - Divide the system clock by 16.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_DEADTIME_DTPS field. */
+#define FTM_RD_DEADTIME_DTPS(base) ((FTM_DEADTIME_REG(base) & FTM_DEADTIME_DTPS_MASK) >> FTM_DEADTIME_DTPS_SHIFT)
+#define FTM_BRD_DEADTIME_DTPS(base) (FTM_RD_DEADTIME_DTPS(base))
+
+/*! @brief Set the DTPS field to a new value. */
+#define FTM_WR_DEADTIME_DTPS(base, value) (FTM_RMW_DEADTIME(base, FTM_DEADTIME_DTPS_MASK, FTM_DEADTIME_DTPS(value)))
+#define FTM_BWR_DEADTIME_DTPS(base, value) (FTM_WR_DEADTIME_DTPS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_EXTTRIG - FTM External Trigger
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_EXTTRIG - FTM External Trigger (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register: Indicates when a channel trigger was generated Enables the
+ * generation of a trigger when the FTM counter is equal to its initial value
+ * Selects which channels are used in the generation of the channel triggers Several
+ * channels can be selected to generate multiple triggers in one PWM period.
+ * Channels 6 and 7 are not used to generate channel triggers.
+ */
+/*!
+ * @name Constants and macros for entire FTM_EXTTRIG register
+ */
+/*@{*/
+#define FTM_RD_EXTTRIG(base)     (FTM_EXTTRIG_REG(base))
+#define FTM_WR_EXTTRIG(base, value) (FTM_EXTTRIG_REG(base) = (value))
+#define FTM_RMW_EXTTRIG(base, mask, value) (FTM_WR_EXTTRIG(base, (FTM_RD_EXTTRIG(base) & ~(mask)) | (value)))
+#define FTM_SET_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) |  (value)))
+#define FTM_CLR_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) & ~(value)))
+#define FTM_TOG_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_EXTTRIG bitfields
+ */
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */
+#define FTM_RD_EXTTRIG_CH2TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH2TRIG_MASK) >> FTM_EXTTRIG_CH2TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH2TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH2TRIG_SHIFT))
+
+/*! @brief Set the CH2TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH2TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH2TRIG_MASK, FTM_EXTTRIG_CH2TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH2TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH2TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */
+#define FTM_RD_EXTTRIG_CH3TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH3TRIG_MASK) >> FTM_EXTTRIG_CH3TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH3TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH3TRIG_SHIFT))
+
+/*! @brief Set the CH3TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH3TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH3TRIG_MASK, FTM_EXTTRIG_CH3TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH3TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH3TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */
+#define FTM_RD_EXTTRIG_CH4TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH4TRIG_MASK) >> FTM_EXTTRIG_CH4TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH4TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH4TRIG_SHIFT))
+
+/*! @brief Set the CH4TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH4TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH4TRIG_MASK, FTM_EXTTRIG_CH4TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH4TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH4TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */
+#define FTM_RD_EXTTRIG_CH5TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH5TRIG_MASK) >> FTM_EXTTRIG_CH5TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH5TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH5TRIG_SHIFT))
+
+/*! @brief Set the CH5TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH5TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH5TRIG_MASK, FTM_EXTTRIG_CH5TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH5TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH5TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */
+#define FTM_RD_EXTTRIG_CH0TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH0TRIG_MASK) >> FTM_EXTTRIG_CH0TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH0TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH0TRIG_SHIFT))
+
+/*! @brief Set the CH0TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH0TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH0TRIG_MASK, FTM_EXTTRIG_CH0TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH0TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH0TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */
+#define FTM_RD_EXTTRIG_CH1TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH1TRIG_MASK) >> FTM_EXTTRIG_CH1TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH1TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH1TRIG_SHIFT))
+
+/*! @brief Set the CH1TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH1TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH1TRIG_MASK, FTM_EXTTRIG_CH1TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH1TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH1TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
+ *
+ * Enables the generation of the trigger when the FTM counter is equal to the
+ * CNTIN register.
+ *
+ * Values:
+ * - 0b0 - The generation of initialization trigger is disabled.
+ * - 0b1 - The generation of initialization trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */
+#define FTM_RD_EXTTRIG_INITTRIGEN(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_INITTRIGEN_MASK) >> FTM_EXTTRIG_INITTRIGEN_SHIFT)
+#define FTM_BRD_EXTTRIG_INITTRIGEN(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_INITTRIGEN_SHIFT))
+
+/*! @brief Set the INITTRIGEN field to a new value. */
+#define FTM_WR_EXTTRIG_INITTRIGEN(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_INITTRIGEN_MASK, FTM_EXTTRIG_INITTRIGEN(value)))
+#define FTM_BWR_EXTTRIG_INITTRIGEN(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_INITTRIGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
+ *
+ * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
+ * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
+ * has no effect. If another channel trigger is generated before the clearing
+ * sequence is completed, the sequence is reset so TRIGF remains set after the clear
+ * sequence is completed for the earlier TRIGF.
+ *
+ * Values:
+ * - 0b0 - No channel trigger was generated.
+ * - 0b1 - A channel trigger was generated.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */
+#define FTM_RD_EXTTRIG_TRIGF(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_TRIGF_MASK) >> FTM_EXTTRIG_TRIGF_SHIFT)
+#define FTM_BRD_EXTTRIG_TRIGF(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_TRIGF_SHIFT))
+
+/*! @brief Set the TRIGF field to a new value. */
+#define FTM_WR_EXTTRIG_TRIGF(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_TRIGF_MASK, FTM_EXTTRIG_TRIGF(value)))
+#define FTM_BWR_EXTTRIG_TRIGF(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_TRIGF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_POL - Channels Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_POL - Channels Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the output polarity of the FTM channels. The safe value
+ * that is driven in a channel output when the fault control is enabled and a
+ * fault condition is detected is the inactive state of the channel. That is, the
+ * safe value of a channel is the value of its POL bit.
+ */
+/*!
+ * @name Constants and macros for entire FTM_POL register
+ */
+/*@{*/
+#define FTM_RD_POL(base)         (FTM_POL_REG(base))
+#define FTM_WR_POL(base, value)  (FTM_POL_REG(base) = (value))
+#define FTM_RMW_POL(base, mask, value) (FTM_WR_POL(base, (FTM_RD_POL(base) & ~(mask)) | (value)))
+#define FTM_SET_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) |  (value)))
+#define FTM_CLR_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) & ~(value)))
+#define FTM_TOG_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_POL bitfields
+ */
+
+/*!
+ * @name Register FTM_POL, field POL0[0] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL0 field. */
+#define FTM_RD_POL_POL0(base) ((FTM_POL_REG(base) & FTM_POL_POL0_MASK) >> FTM_POL_POL0_SHIFT)
+#define FTM_BRD_POL_POL0(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL0_SHIFT))
+
+/*! @brief Set the POL0 field to a new value. */
+#define FTM_WR_POL_POL0(base, value) (FTM_RMW_POL(base, FTM_POL_POL0_MASK, FTM_POL_POL0(value)))
+#define FTM_BWR_POL_POL0(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL1[1] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL1 field. */
+#define FTM_RD_POL_POL1(base) ((FTM_POL_REG(base) & FTM_POL_POL1_MASK) >> FTM_POL_POL1_SHIFT)
+#define FTM_BRD_POL_POL1(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL1_SHIFT))
+
+/*! @brief Set the POL1 field to a new value. */
+#define FTM_WR_POL_POL1(base, value) (FTM_RMW_POL(base, FTM_POL_POL1_MASK, FTM_POL_POL1(value)))
+#define FTM_BWR_POL_POL1(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL2[2] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL2 field. */
+#define FTM_RD_POL_POL2(base) ((FTM_POL_REG(base) & FTM_POL_POL2_MASK) >> FTM_POL_POL2_SHIFT)
+#define FTM_BRD_POL_POL2(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL2_SHIFT))
+
+/*! @brief Set the POL2 field to a new value. */
+#define FTM_WR_POL_POL2(base, value) (FTM_RMW_POL(base, FTM_POL_POL2_MASK, FTM_POL_POL2(value)))
+#define FTM_BWR_POL_POL2(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL3[3] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL3 field. */
+#define FTM_RD_POL_POL3(base) ((FTM_POL_REG(base) & FTM_POL_POL3_MASK) >> FTM_POL_POL3_SHIFT)
+#define FTM_BRD_POL_POL3(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL3_SHIFT))
+
+/*! @brief Set the POL3 field to a new value. */
+#define FTM_WR_POL_POL3(base, value) (FTM_RMW_POL(base, FTM_POL_POL3_MASK, FTM_POL_POL3(value)))
+#define FTM_BWR_POL_POL3(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL4[4] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL4 field. */
+#define FTM_RD_POL_POL4(base) ((FTM_POL_REG(base) & FTM_POL_POL4_MASK) >> FTM_POL_POL4_SHIFT)
+#define FTM_BRD_POL_POL4(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL4_SHIFT))
+
+/*! @brief Set the POL4 field to a new value. */
+#define FTM_WR_POL_POL4(base, value) (FTM_RMW_POL(base, FTM_POL_POL4_MASK, FTM_POL_POL4(value)))
+#define FTM_BWR_POL_POL4(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL5[5] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL5 field. */
+#define FTM_RD_POL_POL5(base) ((FTM_POL_REG(base) & FTM_POL_POL5_MASK) >> FTM_POL_POL5_SHIFT)
+#define FTM_BRD_POL_POL5(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL5_SHIFT))
+
+/*! @brief Set the POL5 field to a new value. */
+#define FTM_WR_POL_POL5(base, value) (FTM_RMW_POL(base, FTM_POL_POL5_MASK, FTM_POL_POL5(value)))
+#define FTM_BWR_POL_POL5(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL6[6] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL6 field. */
+#define FTM_RD_POL_POL6(base) ((FTM_POL_REG(base) & FTM_POL_POL6_MASK) >> FTM_POL_POL6_SHIFT)
+#define FTM_BRD_POL_POL6(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL6_SHIFT))
+
+/*! @brief Set the POL6 field to a new value. */
+#define FTM_WR_POL_POL6(base, value) (FTM_RMW_POL(base, FTM_POL_POL6_MASK, FTM_POL_POL6(value)))
+#define FTM_BWR_POL_POL6(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL7[7] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL7 field. */
+#define FTM_RD_POL_POL7(base) ((FTM_POL_REG(base) & FTM_POL_POL7_MASK) >> FTM_POL_POL7_SHIFT)
+#define FTM_BRD_POL_POL7(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL7_SHIFT))
+
+/*! @brief Set the POL7 field to a new value. */
+#define FTM_WR_POL_POL7(base, value) (FTM_RMW_POL(base, FTM_POL_POL7_MASK, FTM_POL_POL7(value)))
+#define FTM_BWR_POL_POL7(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FMS - Fault Mode Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FMS - Fault Mode Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the fault detection flags, write protection enable
+ * bit, and the logic OR of the enabled fault inputs.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FMS register
+ */
+/*@{*/
+#define FTM_RD_FMS(base)         (FTM_FMS_REG(base))
+#define FTM_WR_FMS(base, value)  (FTM_FMS_REG(base) = (value))
+#define FTM_RMW_FMS(base, mask, value) (FTM_WR_FMS(base, (FTM_RD_FMS(base) & ~(mask)) | (value)))
+#define FTM_SET_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) |  (value)))
+#define FTM_CLR_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) & ~(value)))
+#define FTM_TOG_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FMS bitfields
+ */
+
+/*!
+ * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
+ * by reading the FMS register while FAULTF0 is set and then writing a 0 to
+ * FAULTF0 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF0 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF0 field. */
+#define FTM_RD_FMS_FAULTF0(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF0_MASK) >> FTM_FMS_FAULTF0_SHIFT)
+#define FTM_BRD_FMS_FAULTF0(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF0_SHIFT))
+
+/*! @brief Set the FAULTF0 field to a new value. */
+#define FTM_WR_FMS_FAULTF0(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF0_MASK, FTM_FMS_FAULTF0(value)))
+#define FTM_BWR_FMS_FAULTF0(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
+ * by reading the FMS register while FAULTF1 is set and then writing a 0 to
+ * FAULTF1 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF1 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF1 field. */
+#define FTM_RD_FMS_FAULTF1(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF1_MASK) >> FTM_FMS_FAULTF1_SHIFT)
+#define FTM_BRD_FMS_FAULTF1(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF1_SHIFT))
+
+/*! @brief Set the FAULTF1 field to a new value. */
+#define FTM_WR_FMS_FAULTF1(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF1_MASK, FTM_FMS_FAULTF1(value)))
+#define FTM_BWR_FMS_FAULTF1(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
+ * by reading the FMS register while FAULTF2 is set and then writing a 0 to
+ * FAULTF2 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF2 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF2 field. */
+#define FTM_RD_FMS_FAULTF2(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF2_MASK) >> FTM_FMS_FAULTF2_SHIFT)
+#define FTM_BRD_FMS_FAULTF2(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF2_SHIFT))
+
+/*! @brief Set the FAULTF2 field to a new value. */
+#define FTM_WR_FMS_FAULTF2(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF2_MASK, FTM_FMS_FAULTF2(value)))
+#define FTM_BWR_FMS_FAULTF2(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
+ * by reading the FMS register while FAULTF3 is set and then writing a 0 to
+ * FAULTF3 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF3 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF3 field. */
+#define FTM_RD_FMS_FAULTF3(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF3_MASK) >> FTM_FMS_FAULTF3_SHIFT)
+#define FTM_BRD_FMS_FAULTF3(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF3_SHIFT))
+
+/*! @brief Set the FAULTF3 field to a new value. */
+#define FTM_WR_FMS_FAULTF3(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF3_MASK, FTM_FMS_FAULTF3(value)))
+#define FTM_BWR_FMS_FAULTF3(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTIN[5] (RO)
+ *
+ * Represents the logic OR of the enabled fault inputs after their filter (if
+ * their filter is enabled) when fault control is enabled.
+ *
+ * Values:
+ * - 0b0 - The logic OR of the enabled fault inputs is 0.
+ * - 0b1 - The logic OR of the enabled fault inputs is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTIN field. */
+#define FTM_RD_FMS_FAULTIN(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTIN_MASK) >> FTM_FMS_FAULTIN_SHIFT)
+#define FTM_BRD_FMS_FAULTIN(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTIN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field WPEN[6] (RW)
+ *
+ * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
+ * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
+ * WPDIS. Writing 0 to WPEN has no effect.
+ *
+ * Values:
+ * - 0b0 - Write protection is disabled. Write protected bits can be written.
+ * - 0b1 - Write protection is enabled. Write protected bits cannot be written.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_WPEN field. */
+#define FTM_RD_FMS_WPEN(base) ((FTM_FMS_REG(base) & FTM_FMS_WPEN_MASK) >> FTM_FMS_WPEN_SHIFT)
+#define FTM_BRD_FMS_WPEN(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_WPEN_SHIFT))
+
+/*! @brief Set the WPEN field to a new value. */
+#define FTM_WR_FMS_WPEN(base, value) (FTM_RMW_FMS(base, FTM_FMS_WPEN_MASK, FTM_FMS_WPEN(value)))
+#define FTM_BWR_FMS_WPEN(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_WPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
+ *
+ * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
+ * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
+ * a 0 to FAULTF while there is no existing fault condition at the enabled fault
+ * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
+ * detected in an enabled fault input before the clearing sequence is completed, the
+ * sequence is reset so FAULTF remains set after the clearing sequence is
+ * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
+ * are cleared individually.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected.
+ * - 0b1 - A fault condition was detected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF field. */
+#define FTM_RD_FMS_FAULTF(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF_MASK) >> FTM_FMS_FAULTF_SHIFT)
+#define FTM_BRD_FMS_FAULTF(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF_SHIFT))
+
+/*! @brief Set the FAULTF field to a new value. */
+#define FTM_WR_FMS_FAULTF(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF_MASK, FTM_FMS_FAULTF(value)))
+#define FTM_BWR_FMS_FAULTF(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FILTER - Input Capture Filter Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FILTER - Input Capture Filter Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the inputs of channels. Channels
+ * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
+ * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
+ * in input modes. Failure to do this could result in a missing valid signal.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FILTER register
+ */
+/*@{*/
+#define FTM_RD_FILTER(base)      (FTM_FILTER_REG(base))
+#define FTM_WR_FILTER(base, value) (FTM_FILTER_REG(base) = (value))
+#define FTM_RMW_FILTER(base, mask, value) (FTM_WR_FILTER(base, (FTM_RD_FILTER(base) & ~(mask)) | (value)))
+#define FTM_SET_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) |  (value)))
+#define FTM_CLR_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) & ~(value)))
+#define FTM_TOG_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FILTER bitfields
+ */
+
+/*!
+ * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */
+#define FTM_RD_FILTER_CH0FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH0FVAL_MASK) >> FTM_FILTER_CH0FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH0FVAL(base) (FTM_RD_FILTER_CH0FVAL(base))
+
+/*! @brief Set the CH0FVAL field to a new value. */
+#define FTM_WR_FILTER_CH0FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH0FVAL_MASK, FTM_FILTER_CH0FVAL(value)))
+#define FTM_BWR_FILTER_CH0FVAL(base, value) (FTM_WR_FILTER_CH0FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */
+#define FTM_RD_FILTER_CH1FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH1FVAL_MASK) >> FTM_FILTER_CH1FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH1FVAL(base) (FTM_RD_FILTER_CH1FVAL(base))
+
+/*! @brief Set the CH1FVAL field to a new value. */
+#define FTM_WR_FILTER_CH1FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH1FVAL_MASK, FTM_FILTER_CH1FVAL(value)))
+#define FTM_BWR_FILTER_CH1FVAL(base, value) (FTM_WR_FILTER_CH1FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */
+#define FTM_RD_FILTER_CH2FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH2FVAL_MASK) >> FTM_FILTER_CH2FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH2FVAL(base) (FTM_RD_FILTER_CH2FVAL(base))
+
+/*! @brief Set the CH2FVAL field to a new value. */
+#define FTM_WR_FILTER_CH2FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH2FVAL_MASK, FTM_FILTER_CH2FVAL(value)))
+#define FTM_BWR_FILTER_CH2FVAL(base, value) (FTM_WR_FILTER_CH2FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */
+#define FTM_RD_FILTER_CH3FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH3FVAL_MASK) >> FTM_FILTER_CH3FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH3FVAL(base) (FTM_RD_FILTER_CH3FVAL(base))
+
+/*! @brief Set the CH3FVAL field to a new value. */
+#define FTM_WR_FILTER_CH3FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH3FVAL_MASK, FTM_FILTER_CH3FVAL(value)))
+#define FTM_BWR_FILTER_CH3FVAL(base, value) (FTM_WR_FILTER_CH3FVAL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FLTCTRL - Fault Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FLTCTRL - Fault Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the fault inputs, enables the
+ * fault inputs and the fault inputs filter.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FLTCTRL register
+ */
+/*@{*/
+#define FTM_RD_FLTCTRL(base)     (FTM_FLTCTRL_REG(base))
+#define FTM_WR_FLTCTRL(base, value) (FTM_FLTCTRL_REG(base) = (value))
+#define FTM_RMW_FLTCTRL(base, mask, value) (FTM_WR_FLTCTRL(base, (FTM_RD_FLTCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) |  (value)))
+#define FTM_CLR_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) & ~(value)))
+#define FTM_TOG_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FLTCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */
+#define FTM_RD_FLTCTRL_FAULT0EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT0EN_MASK) >> FTM_FLTCTRL_FAULT0EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT0EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT0EN_SHIFT))
+
+/*! @brief Set the FAULT0EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT0EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT0EN_MASK, FTM_FLTCTRL_FAULT0EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT0EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */
+#define FTM_RD_FLTCTRL_FAULT1EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT1EN_MASK) >> FTM_FLTCTRL_FAULT1EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT1EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT1EN_SHIFT))
+
+/*! @brief Set the FAULT1EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT1EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT1EN_MASK, FTM_FLTCTRL_FAULT1EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT1EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */
+#define FTM_RD_FLTCTRL_FAULT2EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT2EN_MASK) >> FTM_FLTCTRL_FAULT2EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT2EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT2EN_SHIFT))
+
+/*! @brief Set the FAULT2EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT2EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT2EN_MASK, FTM_FLTCTRL_FAULT2EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT2EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */
+#define FTM_RD_FLTCTRL_FAULT3EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT3EN_MASK) >> FTM_FLTCTRL_FAULT3EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT3EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT3EN_SHIFT))
+
+/*! @brief Set the FAULT3EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT3EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT3EN_MASK, FTM_FLTCTRL_FAULT3EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT3EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT3EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */
+#define FTM_RD_FLTCTRL_FFLTR0EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR0EN_MASK) >> FTM_FLTCTRL_FFLTR0EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR0EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR0EN_SHIFT))
+
+/*! @brief Set the FFLTR0EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR0EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR0EN_MASK, FTM_FLTCTRL_FFLTR0EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR0EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */
+#define FTM_RD_FLTCTRL_FFLTR1EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR1EN_MASK) >> FTM_FLTCTRL_FFLTR1EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR1EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR1EN_SHIFT))
+
+/*! @brief Set the FFLTR1EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR1EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR1EN_MASK, FTM_FLTCTRL_FFLTR1EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR1EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */
+#define FTM_RD_FLTCTRL_FFLTR2EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR2EN_MASK) >> FTM_FLTCTRL_FFLTR2EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR2EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR2EN_SHIFT))
+
+/*! @brief Set the FFLTR2EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR2EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR2EN_MASK, FTM_FLTCTRL_FFLTR2EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR2EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */
+#define FTM_RD_FLTCTRL_FFLTR3EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR3EN_MASK) >> FTM_FLTCTRL_FFLTR3EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR3EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR3EN_SHIFT))
+
+/*! @brief Set the FFLTR3EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR3EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR3EN_MASK, FTM_FLTCTRL_FFLTR3EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR3EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR3EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
+ *
+ * Selects the filter value for the fault inputs. The fault filter is disabled
+ * when the value is zero. Writing to this field has immediate effect and must be
+ * done only when the fault control or all fault inputs are disabled. Failure to
+ * do this could result in a missing fault detection.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */
+#define FTM_RD_FLTCTRL_FFVAL(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFVAL_MASK) >> FTM_FLTCTRL_FFVAL_SHIFT)
+#define FTM_BRD_FLTCTRL_FFVAL(base) (FTM_RD_FLTCTRL_FFVAL(base))
+
+/*! @brief Set the FFVAL field to a new value. */
+#define FTM_WR_FLTCTRL_FFVAL(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFVAL_MASK, FTM_FLTCTRL_FFVAL(value)))
+#define FTM_BWR_FLTCTRL_FFVAL(base, value) (FTM_WR_FLTCTRL_FFVAL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_QDCTRL - Quadrature Decoder Control And Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has the control and status bits for the Quadrature Decoder mode.
+ */
+/*!
+ * @name Constants and macros for entire FTM_QDCTRL register
+ */
+/*@{*/
+#define FTM_RD_QDCTRL(base)      (FTM_QDCTRL_REG(base))
+#define FTM_WR_QDCTRL(base, value) (FTM_QDCTRL_REG(base) = (value))
+#define FTM_RMW_QDCTRL(base, mask, value) (FTM_WR_QDCTRL(base, (FTM_RD_QDCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) |  (value)))
+#define FTM_CLR_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) & ~(value)))
+#define FTM_TOG_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_QDCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
+ *
+ * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
+ * signals control the FTM counter direction. The Quadrature Decoder mode has
+ * precedence over the other modes. See #ModeSel1Table. This field is write protected.
+ * It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Quadrature Decoder mode is disabled.
+ * - 0b1 - Quadrature Decoder mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */
+#define FTM_RD_QDCTRL_QUADEN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADEN_MASK) >> FTM_QDCTRL_QUADEN_SHIFT)
+#define FTM_BRD_QDCTRL_QUADEN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADEN_SHIFT))
+
+/*! @brief Set the QUADEN field to a new value. */
+#define FTM_WR_QDCTRL_QUADEN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_QUADEN_MASK, FTM_QDCTRL_QUADEN(value)))
+#define FTM_BWR_QDCTRL_QUADEN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
+ *
+ * Indicates if the TOF bit was set on the top or the bottom of counting.
+ *
+ * Values:
+ * - 0b0 - TOF bit was set on the bottom of counting. There was an FTM counter
+ *     decrement and FTM counter changes from its minimum value (CNTIN register)
+ *     to its maximum value (MOD register).
+ * - 0b1 - TOF bit was set on the top of counting. There was an FTM counter
+ *     increment and FTM counter changes from its maximum value (MOD register) to its
+ *     minimum value (CNTIN register).
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */
+#define FTM_RD_QDCTRL_TOFDIR(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_TOFDIR_MASK) >> FTM_QDCTRL_TOFDIR_SHIFT)
+#define FTM_BRD_QDCTRL_TOFDIR(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_TOFDIR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
+ *
+ * Indicates the counting direction.
+ *
+ * Values:
+ * - 0b0 - Counting direction is decreasing (FTM counter decrement).
+ * - 0b1 - Counting direction is increasing (FTM counter increment).
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */
+#define FTM_RD_QDCTRL_QUADIR(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADIR_MASK) >> FTM_QDCTRL_QUADIR_SHIFT)
+#define FTM_BRD_QDCTRL_QUADIR(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADIR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
+ *
+ * Selects the encoding mode used in the Quadrature Decoder mode.
+ *
+ * Values:
+ * - 0b0 - Phase A and phase B encoding mode.
+ * - 0b1 - Count and direction encoding mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */
+#define FTM_RD_QDCTRL_QUADMODE(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADMODE_MASK) >> FTM_QDCTRL_QUADMODE_SHIFT)
+#define FTM_BRD_QDCTRL_QUADMODE(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADMODE_SHIFT))
+
+/*! @brief Set the QUADMODE field to a new value. */
+#define FTM_WR_QDCTRL_QUADMODE(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_QUADMODE_MASK, FTM_QDCTRL_QUADMODE(value)))
+#define FTM_BWR_QDCTRL_QUADMODE(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase B input.
+ *
+ * Values:
+ * - 0b0 - Normal polarity. Phase B input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 0b1 - Inverted polarity. Phase B input signal is inverted before
+ *     identifying the rising and falling edges of this signal.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */
+#define FTM_RD_QDCTRL_PHBPOL(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHBPOL_MASK) >> FTM_QDCTRL_PHBPOL_SHIFT)
+#define FTM_BRD_QDCTRL_PHBPOL(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBPOL_SHIFT))
+
+/*! @brief Set the PHBPOL field to a new value. */
+#define FTM_WR_QDCTRL_PHBPOL(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHBPOL_MASK, FTM_QDCTRL_PHBPOL(value)))
+#define FTM_BWR_QDCTRL_PHBPOL(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase A input.
+ *
+ * Values:
+ * - 0b0 - Normal polarity. Phase A input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 0b1 - Inverted polarity. Phase A input signal is inverted before
+ *     identifying the rising and falling edges of this signal.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */
+#define FTM_RD_QDCTRL_PHAPOL(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHAPOL_MASK) >> FTM_QDCTRL_PHAPOL_SHIFT)
+#define FTM_BRD_QDCTRL_PHAPOL(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAPOL_SHIFT))
+
+/*! @brief Set the PHAPOL field to a new value. */
+#define FTM_WR_QDCTRL_PHAPOL(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHAPOL_MASK, FTM_QDCTRL_PHAPOL(value)))
+#define FTM_BWR_QDCTRL_PHAPOL(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase B input. The filter value
+ * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
+ * filter is also disabled when CH1FVAL is zero.
+ *
+ * Values:
+ * - 0b0 - Phase B input filter is disabled.
+ * - 0b1 - Phase B input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */
+#define FTM_RD_QDCTRL_PHBFLTREN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHBFLTREN_MASK) >> FTM_QDCTRL_PHBFLTREN_SHIFT)
+#define FTM_BRD_QDCTRL_PHBFLTREN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBFLTREN_SHIFT))
+
+/*! @brief Set the PHBFLTREN field to a new value. */
+#define FTM_WR_QDCTRL_PHBFLTREN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHBFLTREN_MASK, FTM_QDCTRL_PHBFLTREN(value)))
+#define FTM_BWR_QDCTRL_PHBFLTREN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBFLTREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase A input. The filter value
+ * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
+ * filter is also disabled when CH0FVAL is zero.
+ *
+ * Values:
+ * - 0b0 - Phase A input filter is disabled.
+ * - 0b1 - Phase A input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */
+#define FTM_RD_QDCTRL_PHAFLTREN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHAFLTREN_MASK) >> FTM_QDCTRL_PHAFLTREN_SHIFT)
+#define FTM_BRD_QDCTRL_PHAFLTREN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAFLTREN_SHIFT))
+
+/*! @brief Set the PHAFLTREN field to a new value. */
+#define FTM_WR_QDCTRL_PHAFLTREN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHAFLTREN_MASK, FTM_QDCTRL_PHAFLTREN(value)))
+#define FTM_BWR_QDCTRL_PHAFLTREN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAFLTREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CONF - Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CONF - Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the number of times that the FTM counter overflow
+ * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
+ * of an external global time base, and the global time base signal generation.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CONF register
+ */
+/*@{*/
+#define FTM_RD_CONF(base)        (FTM_CONF_REG(base))
+#define FTM_WR_CONF(base, value) (FTM_CONF_REG(base) = (value))
+#define FTM_RMW_CONF(base, mask, value) (FTM_WR_CONF(base, (FTM_RD_CONF(base) & ~(mask)) | (value)))
+#define FTM_SET_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) |  (value)))
+#define FTM_CLR_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) & ~(value)))
+#define FTM_TOG_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CONF bitfields
+ */
+
+/*!
+ * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
+ *
+ * Selects the ratio between the number of counter overflows to the number of
+ * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
+ * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
+ * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
+ * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
+ * first counter overflow but not for the next 3 overflows. This pattern continues
+ * up to a maximum of 31.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_NUMTOF field. */
+#define FTM_RD_CONF_NUMTOF(base) ((FTM_CONF_REG(base) & FTM_CONF_NUMTOF_MASK) >> FTM_CONF_NUMTOF_SHIFT)
+#define FTM_BRD_CONF_NUMTOF(base) (FTM_RD_CONF_NUMTOF(base))
+
+/*! @brief Set the NUMTOF field to a new value. */
+#define FTM_WR_CONF_NUMTOF(base, value) (FTM_RMW_CONF(base, FTM_CONF_NUMTOF_MASK, FTM_CONF_NUMTOF(value)))
+#define FTM_BWR_CONF_NUMTOF(base, value) (FTM_WR_CONF_NUMTOF(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
+ *
+ * Selects the FTM behavior in BDM mode. See BDM mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_BDMMODE field. */
+#define FTM_RD_CONF_BDMMODE(base) ((FTM_CONF_REG(base) & FTM_CONF_BDMMODE_MASK) >> FTM_CONF_BDMMODE_SHIFT)
+#define FTM_BRD_CONF_BDMMODE(base) (FTM_RD_CONF_BDMMODE(base))
+
+/*! @brief Set the BDMMODE field to a new value. */
+#define FTM_WR_CONF_BDMMODE(base, value) (FTM_RMW_CONF(base, FTM_CONF_BDMMODE_MASK, FTM_CONF_BDMMODE(value)))
+#define FTM_BWR_CONF_BDMMODE(base, value) (FTM_WR_CONF_BDMMODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field GTBEEN[9] (RW)
+ *
+ * Configures the FTM to use an external global time base signal that is
+ * generated by another FTM.
+ *
+ * Values:
+ * - 0b0 - Use of an external global time base is disabled.
+ * - 0b1 - Use of an external global time base is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_GTBEEN field. */
+#define FTM_RD_CONF_GTBEEN(base) ((FTM_CONF_REG(base) & FTM_CONF_GTBEEN_MASK) >> FTM_CONF_GTBEEN_SHIFT)
+#define FTM_BRD_CONF_GTBEEN(base) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEEN_SHIFT))
+
+/*! @brief Set the GTBEEN field to a new value. */
+#define FTM_WR_CONF_GTBEEN(base, value) (FTM_RMW_CONF(base, FTM_CONF_GTBEEN_MASK, FTM_CONF_GTBEEN(value)))
+#define FTM_BWR_CONF_GTBEEN(base, value) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field GTBEOUT[10] (RW)
+ *
+ * Enables the global time base signal generation to other FTMs.
+ *
+ * Values:
+ * - 0b0 - A global time base signal generation is disabled.
+ * - 0b1 - A global time base signal generation is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_GTBEOUT field. */
+#define FTM_RD_CONF_GTBEOUT(base) ((FTM_CONF_REG(base) & FTM_CONF_GTBEOUT_MASK) >> FTM_CONF_GTBEOUT_SHIFT)
+#define FTM_BRD_CONF_GTBEOUT(base) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEOUT_SHIFT))
+
+/*! @brief Set the GTBEOUT field to a new value. */
+#define FTM_WR_CONF_GTBEOUT(base, value) (FTM_RMW_CONF(base, FTM_CONF_GTBEOUT_MASK, FTM_CONF_GTBEOUT(value)))
+#define FTM_BWR_CONF_GTBEOUT(base, value) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEOUT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FLTPOL - FTM Fault Input Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FLTPOL - FTM Fault Input Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the fault inputs polarity.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FLTPOL register
+ */
+/*@{*/
+#define FTM_RD_FLTPOL(base)      (FTM_FLTPOL_REG(base))
+#define FTM_WR_FLTPOL(base, value) (FTM_FLTPOL_REG(base) = (value))
+#define FTM_RMW_FLTPOL(base, mask, value) (FTM_WR_FLTPOL(base, (FTM_RD_FLTPOL(base) & ~(mask)) | (value)))
+#define FTM_SET_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) |  (value)))
+#define FTM_CLR_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) & ~(value)))
+#define FTM_TOG_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FLTPOL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */
+#define FTM_RD_FLTPOL_FLT0POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT0POL_MASK) >> FTM_FLTPOL_FLT0POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT0POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT0POL_SHIFT))
+
+/*! @brief Set the FLT0POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT0POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT0POL_MASK, FTM_FLTPOL_FLT0POL(value)))
+#define FTM_BWR_FLTPOL_FLT0POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT0POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */
+#define FTM_RD_FLTPOL_FLT1POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT1POL_MASK) >> FTM_FLTPOL_FLT1POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT1POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT1POL_SHIFT))
+
+/*! @brief Set the FLT1POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT1POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT1POL_MASK, FTM_FLTPOL_FLT1POL(value)))
+#define FTM_BWR_FLTPOL_FLT1POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT1POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */
+#define FTM_RD_FLTPOL_FLT2POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT2POL_MASK) >> FTM_FLTPOL_FLT2POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT2POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT2POL_SHIFT))
+
+/*! @brief Set the FLT2POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT2POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT2POL_MASK, FTM_FLTPOL_FLT2POL(value)))
+#define FTM_BWR_FLTPOL_FLT2POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT2POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */
+#define FTM_RD_FLTPOL_FLT3POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT3POL_MASK) >> FTM_FLTPOL_FLT3POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT3POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT3POL_SHIFT))
+
+/*! @brief Set the FLT3POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT3POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT3POL_MASK, FTM_FLTPOL_FLT3POL(value)))
+#define FTM_BWR_FLTPOL_FLT3POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT3POL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SYNCONF - Synchronization Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SYNCONF - Synchronization Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
+ * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
+ * 0, 1, 2, when the hardware trigger j is detected.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SYNCONF register
+ */
+/*@{*/
+#define FTM_RD_SYNCONF(base)     (FTM_SYNCONF_REG(base))
+#define FTM_WR_SYNCONF(base, value) (FTM_SYNCONF_REG(base) = (value))
+#define FTM_RMW_SYNCONF(base, mask, value) (FTM_WR_SYNCONF(base, (FTM_RD_SYNCONF(base) & ~(mask)) | (value)))
+#define FTM_SET_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) |  (value)))
+#define FTM_CLR_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) & ~(value)))
+#define FTM_TOG_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SYNCONF bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - FTM clears the TRIGj bit when the hardware trigger j is detected,
+ *     where j = 0, 1,2.
+ * - 0b1 - FTM does not clear the TRIGj bit when the hardware trigger j is
+ *     detected, where j = 0, 1,2.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */
+#define FTM_RD_SYNCONF_HWTRIGMODE(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWTRIGMODE_MASK) >> FTM_SYNCONF_HWTRIGMODE_SHIFT)
+#define FTM_BRD_SYNCONF_HWTRIGMODE(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWTRIGMODE_SHIFT))
+
+/*! @brief Set the HWTRIGMODE field to a new value. */
+#define FTM_WR_SYNCONF_HWTRIGMODE(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWTRIGMODE_MASK, FTM_SYNCONF_HWTRIGMODE(value)))
+#define FTM_BWR_SYNCONF_HWTRIGMODE(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWTRIGMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
+ *
+ * Values:
+ * - 0b0 - CNTIN register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - CNTIN register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */
+#define FTM_RD_SYNCONF_CNTINC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_CNTINC_MASK) >> FTM_SYNCONF_CNTINC_SHIFT)
+#define FTM_BRD_SYNCONF_CNTINC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_CNTINC_SHIFT))
+
+/*! @brief Set the CNTINC field to a new value. */
+#define FTM_WR_SYNCONF_CNTINC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_CNTINC_MASK, FTM_SYNCONF_CNTINC(value)))
+#define FTM_BWR_SYNCONF_CNTINC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_CNTINC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field INVC[4] (RW)
+ *
+ * Values:
+ * - 0b0 - INVCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - INVCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_INVC field. */
+#define FTM_RD_SYNCONF_INVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_INVC_MASK) >> FTM_SYNCONF_INVC_SHIFT)
+#define FTM_BRD_SYNCONF_INVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_INVC_SHIFT))
+
+/*! @brief Set the INVC field to a new value. */
+#define FTM_WR_SYNCONF_INVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_INVC_MASK, FTM_SYNCONF_INVC(value)))
+#define FTM_BWR_SYNCONF_INVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_INVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOC[5] (RW)
+ *
+ * Values:
+ * - 0b0 - SWOCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - SWOCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWOC field. */
+#define FTM_RD_SYNCONF_SWOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWOC_MASK) >> FTM_SYNCONF_SWOC_SHIFT)
+#define FTM_BRD_SYNCONF_SWOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOC_SHIFT))
+
+/*! @brief Set the SWOC field to a new value. */
+#define FTM_WR_SYNCONF_SWOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWOC_MASK, FTM_SYNCONF_SWOC(value)))
+#define FTM_BWR_SYNCONF_SWOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
+ *
+ * Selects the PWM Synchronization mode.
+ *
+ * Values:
+ * - 0b0 - Legacy PWM synchronization is selected.
+ * - 0b1 - Enhanced PWM synchronization is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */
+#define FTM_RD_SYNCONF_SYNCMODE(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SYNCMODE_MASK) >> FTM_SYNCONF_SYNCMODE_SHIFT)
+#define FTM_BRD_SYNCONF_SYNCMODE(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SYNCMODE_SHIFT))
+
+/*! @brief Set the SYNCMODE field to a new value. */
+#define FTM_WR_SYNCONF_SYNCMODE(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SYNCMODE_MASK, FTM_SYNCONF_SYNCMODE(value)))
+#define FTM_BWR_SYNCONF_SYNCMODE(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SYNCMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
+ *
+ * FTM counter synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the FTM counter
+ *     synchronization.
+ * - 0b1 - The software trigger activates the FTM counter synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */
+#define FTM_RD_SYNCONF_SWRSTCNT(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWRSTCNT_MASK) >> FTM_SYNCONF_SWRSTCNT_SHIFT)
+#define FTM_BRD_SYNCONF_SWRSTCNT(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWRSTCNT_SHIFT))
+
+/*! @brief Set the SWRSTCNT field to a new value. */
+#define FTM_WR_SYNCONF_SWRSTCNT(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWRSTCNT_MASK, FTM_SYNCONF_SWRSTCNT(value)))
+#define FTM_BWR_SYNCONF_SWRSTCNT(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWRSTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by the software
+ * trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 0b1 - The software trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */
+#define FTM_RD_SYNCONF_SWWRBUF(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWWRBUF_MASK) >> FTM_SYNCONF_SWWRBUF_SHIFT)
+#define FTM_BRD_SYNCONF_SWWRBUF(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWWRBUF_SHIFT))
+
+/*! @brief Set the SWWRBUF field to a new value. */
+#define FTM_WR_SYNCONF_SWWRBUF(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWWRBUF_MASK, FTM_SYNCONF_SWWRBUF(value)))
+#define FTM_BWR_SYNCONF_SWWRBUF(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWWRBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOM[10] (RW)
+ *
+ * Output mask synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the OUTMASK register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWOM field. */
+#define FTM_RD_SYNCONF_SWOM(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWOM_MASK) >> FTM_SYNCONF_SWOM_SHIFT)
+#define FTM_BRD_SYNCONF_SWOM(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOM_SHIFT))
+
+/*! @brief Set the SWOM field to a new value. */
+#define FTM_WR_SYNCONF_SWOM(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWOM_MASK, FTM_SYNCONF_SWOM(value)))
+#define FTM_BWR_SYNCONF_SWOM(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
+ *
+ * Inverting control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the INVCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */
+#define FTM_RD_SYNCONF_SWINVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWINVC_MASK) >> FTM_SYNCONF_SWINVC_SHIFT)
+#define FTM_BRD_SYNCONF_SWINVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWINVC_SHIFT))
+
+/*! @brief Set the SWINVC field to a new value. */
+#define FTM_WR_SYNCONF_SWINVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWINVC_MASK, FTM_SYNCONF_SWINVC(value)))
+#define FTM_BWR_SYNCONF_SWINVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWINVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
+ *
+ * Software output control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the SWOCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */
+#define FTM_RD_SYNCONF_SWSOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWSOC_MASK) >> FTM_SYNCONF_SWSOC_SHIFT)
+#define FTM_BRD_SYNCONF_SWSOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWSOC_SHIFT))
+
+/*! @brief Set the SWSOC field to a new value. */
+#define FTM_WR_SYNCONF_SWSOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWSOC_MASK, FTM_SYNCONF_SWSOC(value)))
+#define FTM_BWR_SYNCONF_SWSOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWSOC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
+ *
+ * FTM counter synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the FTM counter synchronization.
+ * - 0b1 - A hardware trigger activates the FTM counter synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */
+#define FTM_RD_SYNCONF_HWRSTCNT(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWRSTCNT_MASK) >> FTM_SYNCONF_HWRSTCNT_SHIFT)
+#define FTM_BRD_SYNCONF_HWRSTCNT(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWRSTCNT_SHIFT))
+
+/*! @brief Set the HWRSTCNT field to a new value. */
+#define FTM_WR_SYNCONF_HWRSTCNT(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWRSTCNT_MASK, FTM_SYNCONF_HWRSTCNT(value)))
+#define FTM_BWR_SYNCONF_HWRSTCNT(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWRSTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by a hardware
+ * trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */
+#define FTM_RD_SYNCONF_HWWRBUF(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWWRBUF_MASK) >> FTM_SYNCONF_HWWRBUF_SHIFT)
+#define FTM_BRD_SYNCONF_HWWRBUF(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWWRBUF_SHIFT))
+
+/*! @brief Set the HWWRBUF field to a new value. */
+#define FTM_WR_SYNCONF_HWWRBUF(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWWRBUF_MASK, FTM_SYNCONF_HWWRBUF(value)))
+#define FTM_BWR_SYNCONF_HWWRBUF(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWWRBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWOM[18] (RW)
+ *
+ * Output mask synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the OUTMASK register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWOM field. */
+#define FTM_RD_SYNCONF_HWOM(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWOM_MASK) >> FTM_SYNCONF_HWOM_SHIFT)
+#define FTM_BRD_SYNCONF_HWOM(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWOM_SHIFT))
+
+/*! @brief Set the HWOM field to a new value. */
+#define FTM_WR_SYNCONF_HWOM(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWOM_MASK, FTM_SYNCONF_HWOM(value)))
+#define FTM_BWR_SYNCONF_HWOM(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
+ *
+ * Inverting control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the INVCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */
+#define FTM_RD_SYNCONF_HWINVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWINVC_MASK) >> FTM_SYNCONF_HWINVC_SHIFT)
+#define FTM_BRD_SYNCONF_HWINVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWINVC_SHIFT))
+
+/*! @brief Set the HWINVC field to a new value. */
+#define FTM_WR_SYNCONF_HWINVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWINVC_MASK, FTM_SYNCONF_HWINVC(value)))
+#define FTM_BWR_SYNCONF_HWINVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWINVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
+ *
+ * Software output control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the SWOCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */
+#define FTM_RD_SYNCONF_HWSOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWSOC_MASK) >> FTM_SYNCONF_HWSOC_SHIFT)
+#define FTM_BRD_SYNCONF_HWSOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWSOC_SHIFT))
+
+/*! @brief Set the HWSOC field to a new value. */
+#define FTM_WR_SYNCONF_HWSOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWSOC_MASK, FTM_SYNCONF_HWSOC(value)))
+#define FTM_BWR_SYNCONF_HWSOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWSOC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_INVCTRL - FTM Inverting Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_INVCTRL - FTM Inverting Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls when the channel (n) output becomes the channel (n+1)
+ * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
+ * bit enables the inverting operation for the corresponding pair channels m. This
+ * register has a write buffer. The INVmEN bit is updated by the INVCTRL
+ * register synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_INVCTRL register
+ */
+/*@{*/
+#define FTM_RD_INVCTRL(base)     (FTM_INVCTRL_REG(base))
+#define FTM_WR_INVCTRL(base, value) (FTM_INVCTRL_REG(base) = (value))
+#define FTM_RMW_INVCTRL(base, mask, value) (FTM_WR_INVCTRL(base, (FTM_RD_INVCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) |  (value)))
+#define FTM_CLR_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) & ~(value)))
+#define FTM_TOG_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_INVCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */
+#define FTM_RD_INVCTRL_INV0EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV0EN_MASK) >> FTM_INVCTRL_INV0EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV0EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV0EN_SHIFT))
+
+/*! @brief Set the INV0EN field to a new value. */
+#define FTM_WR_INVCTRL_INV0EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV0EN_MASK, FTM_INVCTRL_INV0EN(value)))
+#define FTM_BWR_INVCTRL_INV0EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */
+#define FTM_RD_INVCTRL_INV1EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV1EN_MASK) >> FTM_INVCTRL_INV1EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV1EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV1EN_SHIFT))
+
+/*! @brief Set the INV1EN field to a new value. */
+#define FTM_WR_INVCTRL_INV1EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV1EN_MASK, FTM_INVCTRL_INV1EN(value)))
+#define FTM_BWR_INVCTRL_INV1EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */
+#define FTM_RD_INVCTRL_INV2EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV2EN_MASK) >> FTM_INVCTRL_INV2EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV2EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV2EN_SHIFT))
+
+/*! @brief Set the INV2EN field to a new value. */
+#define FTM_WR_INVCTRL_INV2EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV2EN_MASK, FTM_INVCTRL_INV2EN(value)))
+#define FTM_BWR_INVCTRL_INV2EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */
+#define FTM_RD_INVCTRL_INV3EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV3EN_MASK) >> FTM_INVCTRL_INV3EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV3EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV3EN_SHIFT))
+
+/*! @brief Set the INV3EN field to a new value. */
+#define FTM_WR_INVCTRL_INV3EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV3EN_MASK, FTM_INVCTRL_INV3EN(value)))
+#define FTM_BWR_INVCTRL_INV3EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV3EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SWOCTRL - FTM Software Output Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SWOCTRL - FTM Software Output Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register enables software control of channel (n) output and defines the
+ * value forced to the channel (n) output: The CHnOC bits enable the control of
+ * the corresponding channel (n) output by software. The CHnOCV bits select the
+ * value that is forced at the corresponding channel (n) output. This register has
+ * a write buffer. The fields are updated by the SWOCTRL register synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SWOCTRL register
+ */
+/*@{*/
+#define FTM_RD_SWOCTRL(base)     (FTM_SWOCTRL_REG(base))
+#define FTM_WR_SWOCTRL(base, value) (FTM_SWOCTRL_REG(base) = (value))
+#define FTM_RMW_SWOCTRL(base, mask, value) (FTM_WR_SWOCTRL(base, (FTM_RD_SWOCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) |  (value)))
+#define FTM_CLR_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) & ~(value)))
+#define FTM_TOG_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SWOCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */
+#define FTM_RD_SWOCTRL_CH0OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH0OC_MASK) >> FTM_SWOCTRL_CH0OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH0OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OC_SHIFT))
+
+/*! @brief Set the CH0OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH0OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH0OC_MASK, FTM_SWOCTRL_CH0OC(value)))
+#define FTM_BWR_SWOCTRL_CH0OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */
+#define FTM_RD_SWOCTRL_CH1OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH1OC_MASK) >> FTM_SWOCTRL_CH1OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH1OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OC_SHIFT))
+
+/*! @brief Set the CH1OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH1OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH1OC_MASK, FTM_SWOCTRL_CH1OC(value)))
+#define FTM_BWR_SWOCTRL_CH1OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */
+#define FTM_RD_SWOCTRL_CH2OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH2OC_MASK) >> FTM_SWOCTRL_CH2OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH2OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OC_SHIFT))
+
+/*! @brief Set the CH2OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH2OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH2OC_MASK, FTM_SWOCTRL_CH2OC(value)))
+#define FTM_BWR_SWOCTRL_CH2OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */
+#define FTM_RD_SWOCTRL_CH3OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH3OC_MASK) >> FTM_SWOCTRL_CH3OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH3OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OC_SHIFT))
+
+/*! @brief Set the CH3OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH3OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH3OC_MASK, FTM_SWOCTRL_CH3OC(value)))
+#define FTM_BWR_SWOCTRL_CH3OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */
+#define FTM_RD_SWOCTRL_CH4OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH4OC_MASK) >> FTM_SWOCTRL_CH4OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH4OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OC_SHIFT))
+
+/*! @brief Set the CH4OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH4OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH4OC_MASK, FTM_SWOCTRL_CH4OC(value)))
+#define FTM_BWR_SWOCTRL_CH4OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */
+#define FTM_RD_SWOCTRL_CH5OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH5OC_MASK) >> FTM_SWOCTRL_CH5OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH5OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OC_SHIFT))
+
+/*! @brief Set the CH5OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH5OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH5OC_MASK, FTM_SWOCTRL_CH5OC(value)))
+#define FTM_BWR_SWOCTRL_CH5OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */
+#define FTM_RD_SWOCTRL_CH6OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH6OC_MASK) >> FTM_SWOCTRL_CH6OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH6OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OC_SHIFT))
+
+/*! @brief Set the CH6OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH6OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH6OC_MASK, FTM_SWOCTRL_CH6OC(value)))
+#define FTM_BWR_SWOCTRL_CH6OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */
+#define FTM_RD_SWOCTRL_CH7OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH7OC_MASK) >> FTM_SWOCTRL_CH7OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH7OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OC_SHIFT))
+
+/*! @brief Set the CH7OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH7OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH7OC_MASK, FTM_SWOCTRL_CH7OC(value)))
+#define FTM_BWR_SWOCTRL_CH7OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */
+#define FTM_RD_SWOCTRL_CH0OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH0OCV_MASK) >> FTM_SWOCTRL_CH0OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH0OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OCV_SHIFT))
+
+/*! @brief Set the CH0OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH0OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH0OCV_MASK, FTM_SWOCTRL_CH0OCV(value)))
+#define FTM_BWR_SWOCTRL_CH0OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */
+#define FTM_RD_SWOCTRL_CH1OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH1OCV_MASK) >> FTM_SWOCTRL_CH1OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH1OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OCV_SHIFT))
+
+/*! @brief Set the CH1OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH1OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH1OCV_MASK, FTM_SWOCTRL_CH1OCV(value)))
+#define FTM_BWR_SWOCTRL_CH1OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */
+#define FTM_RD_SWOCTRL_CH2OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH2OCV_MASK) >> FTM_SWOCTRL_CH2OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH2OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OCV_SHIFT))
+
+/*! @brief Set the CH2OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH2OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH2OCV_MASK, FTM_SWOCTRL_CH2OCV(value)))
+#define FTM_BWR_SWOCTRL_CH2OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */
+#define FTM_RD_SWOCTRL_CH3OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH3OCV_MASK) >> FTM_SWOCTRL_CH3OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH3OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OCV_SHIFT))
+
+/*! @brief Set the CH3OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH3OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH3OCV_MASK, FTM_SWOCTRL_CH3OCV(value)))
+#define FTM_BWR_SWOCTRL_CH3OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */
+#define FTM_RD_SWOCTRL_CH4OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH4OCV_MASK) >> FTM_SWOCTRL_CH4OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH4OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OCV_SHIFT))
+
+/*! @brief Set the CH4OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH4OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH4OCV_MASK, FTM_SWOCTRL_CH4OCV(value)))
+#define FTM_BWR_SWOCTRL_CH4OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */
+#define FTM_RD_SWOCTRL_CH5OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH5OCV_MASK) >> FTM_SWOCTRL_CH5OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH5OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OCV_SHIFT))
+
+/*! @brief Set the CH5OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH5OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH5OCV_MASK, FTM_SWOCTRL_CH5OCV(value)))
+#define FTM_BWR_SWOCTRL_CH5OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */
+#define FTM_RD_SWOCTRL_CH6OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH6OCV_MASK) >> FTM_SWOCTRL_CH6OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH6OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OCV_SHIFT))
+
+/*! @brief Set the CH6OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH6OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH6OCV_MASK, FTM_SWOCTRL_CH6OCV(value)))
+#define FTM_BWR_SWOCTRL_CH6OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */
+#define FTM_RD_SWOCTRL_CH7OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH7OCV_MASK) >> FTM_SWOCTRL_CH7OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH7OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OCV_SHIFT))
+
+/*! @brief Set the CH7OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH7OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH7OCV_MASK, FTM_SWOCTRL_CH7OCV(value)))
+#define FTM_BWR_SWOCTRL_CH7OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OCV_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_PWMLOAD - FTM PWM Load
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_PWMLOAD - FTM PWM Load (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
+ * values of their write buffers when the FTM counter changes from the MOD
+ * register value to its next value or when a channel (j) match occurs. A match occurs
+ * for the channel (j) when FTM counter = C(j)V.
+ */
+/*!
+ * @name Constants and macros for entire FTM_PWMLOAD register
+ */
+/*@{*/
+#define FTM_RD_PWMLOAD(base)     (FTM_PWMLOAD_REG(base))
+#define FTM_WR_PWMLOAD(base, value) (FTM_PWMLOAD_REG(base) = (value))
+#define FTM_RMW_PWMLOAD(base, mask, value) (FTM_WR_PWMLOAD(base, (FTM_RD_PWMLOAD(base) & ~(mask)) | (value)))
+#define FTM_SET_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) |  (value)))
+#define FTM_CLR_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) & ~(value)))
+#define FTM_TOG_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_PWMLOAD bitfields
+ */
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */
+#define FTM_RD_PWMLOAD_CH0SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH0SEL_MASK) >> FTM_PWMLOAD_CH0SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH0SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH0SEL_SHIFT))
+
+/*! @brief Set the CH0SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH0SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH0SEL_MASK, FTM_PWMLOAD_CH0SEL(value)))
+#define FTM_BWR_PWMLOAD_CH0SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH0SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */
+#define FTM_RD_PWMLOAD_CH1SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH1SEL_MASK) >> FTM_PWMLOAD_CH1SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH1SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH1SEL_SHIFT))
+
+/*! @brief Set the CH1SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH1SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH1SEL_MASK, FTM_PWMLOAD_CH1SEL(value)))
+#define FTM_BWR_PWMLOAD_CH1SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH1SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */
+#define FTM_RD_PWMLOAD_CH2SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH2SEL_MASK) >> FTM_PWMLOAD_CH2SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH2SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH2SEL_SHIFT))
+
+/*! @brief Set the CH2SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH2SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH2SEL_MASK, FTM_PWMLOAD_CH2SEL(value)))
+#define FTM_BWR_PWMLOAD_CH2SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH2SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */
+#define FTM_RD_PWMLOAD_CH3SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH3SEL_MASK) >> FTM_PWMLOAD_CH3SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH3SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH3SEL_SHIFT))
+
+/*! @brief Set the CH3SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH3SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH3SEL_MASK, FTM_PWMLOAD_CH3SEL(value)))
+#define FTM_BWR_PWMLOAD_CH3SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH3SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */
+#define FTM_RD_PWMLOAD_CH4SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH4SEL_MASK) >> FTM_PWMLOAD_CH4SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH4SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH4SEL_SHIFT))
+
+/*! @brief Set the CH4SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH4SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH4SEL_MASK, FTM_PWMLOAD_CH4SEL(value)))
+#define FTM_BWR_PWMLOAD_CH4SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH4SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */
+#define FTM_RD_PWMLOAD_CH5SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH5SEL_MASK) >> FTM_PWMLOAD_CH5SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH5SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH5SEL_SHIFT))
+
+/*! @brief Set the CH5SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH5SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH5SEL_MASK, FTM_PWMLOAD_CH5SEL(value)))
+#define FTM_BWR_PWMLOAD_CH5SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH5SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */
+#define FTM_RD_PWMLOAD_CH6SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH6SEL_MASK) >> FTM_PWMLOAD_CH6SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH6SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH6SEL_SHIFT))
+
+/*! @brief Set the CH6SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH6SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH6SEL_MASK, FTM_PWMLOAD_CH6SEL(value)))
+#define FTM_BWR_PWMLOAD_CH6SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH6SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */
+#define FTM_RD_PWMLOAD_CH7SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH7SEL_MASK) >> FTM_PWMLOAD_CH7SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH7SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH7SEL_SHIFT))
+
+/*! @brief Set the CH7SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH7SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH7SEL_MASK, FTM_PWMLOAD_CH7SEL(value)))
+#define FTM_BWR_PWMLOAD_CH7SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH7SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
+ *
+ * Enables the loading of the MOD, CNTIN, and CV registers with the values of
+ * their write buffers.
+ *
+ * Values:
+ * - 0b0 - Loading updated values is disabled.
+ * - 0b1 - Loading updated values is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */
+#define FTM_RD_PWMLOAD_LDOK(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_LDOK_MASK) >> FTM_PWMLOAD_LDOK_SHIFT)
+#define FTM_BRD_PWMLOAD_LDOK(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_LDOK_SHIFT))
+
+/*! @brief Set the LDOK field to a new value. */
+#define FTM_WR_PWMLOAD_LDOK(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_LDOK_MASK, FTM_PWMLOAD_LDOK(value)))
+#define FTM_BWR_PWMLOAD_LDOK(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_LDOK_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 GPIO
+ *
+ * General Purpose Input/Output
+ *
+ * Registers defined in this header file:
+ * - GPIO_PDOR - Port Data Output Register
+ * - GPIO_PSOR - Port Set Output Register
+ * - GPIO_PCOR - Port Clear Output Register
+ * - GPIO_PTOR - Port Toggle Output Register
+ * - GPIO_PDIR - Port Data Input Register
+ * - GPIO_PDDR - Port Data Direction Register
+ */
+
+#define GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
+#define GPIOA_IDX (0U) /*!< Instance number for GPIOA. */
+#define GPIOB_IDX (1U) /*!< Instance number for GPIOB. */
+#define GPIOC_IDX (2U) /*!< Instance number for GPIOC. */
+#define GPIOD_IDX (3U) /*!< Instance number for GPIOD. */
+#define GPIOE_IDX (4U) /*!< Instance number for GPIOE. */
+
+/*******************************************************************************
+ * GPIO_PDOR - Port Data Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDOR - Port Data Output Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the logic levels that are driven on each
+ * general-purpose output pins. Do not modify pin configuration registers associated with
+ * pins not available in your selected package. All unbonded pins not available in
+ * your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDOR register
+ */
+/*@{*/
+#define GPIO_RD_PDOR(base)       (GPIO_PDOR_REG(base))
+#define GPIO_WR_PDOR(base, value) (GPIO_PDOR_REG(base) = (value))
+#define GPIO_RMW_PDOR(base, mask, value) (GPIO_WR_PDOR(base, (GPIO_RD_PDOR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) |  (value)))
+#define GPIO_CLR_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) & ~(value)))
+#define GPIO_TOG_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PSOR - Port Set Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PSOR - Port Set Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to set the fields of the PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PSOR register
+ */
+/*@{*/
+#define GPIO_RD_PSOR(base)       (GPIO_PSOR_REG(base))
+#define GPIO_WR_PSOR(base, value) (GPIO_PSOR_REG(base) = (value))
+#define GPIO_RMW_PSOR(base, mask, value) (GPIO_WR_PSOR(base, (GPIO_RD_PSOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PCOR - Port Clear Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PCOR - Port Clear Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to clear the fields of PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PCOR register
+ */
+/*@{*/
+#define GPIO_RD_PCOR(base)       (GPIO_PCOR_REG(base))
+#define GPIO_WR_PCOR(base, value) (GPIO_PCOR_REG(base) = (value))
+#define GPIO_RMW_PCOR(base, mask, value) (GPIO_WR_PCOR(base, (GPIO_RD_PCOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PTOR - Port Toggle Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PTOR - Port Toggle Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PTOR register
+ */
+/*@{*/
+#define GPIO_RD_PTOR(base)       (GPIO_PTOR_REG(base))
+#define GPIO_WR_PTOR(base, value) (GPIO_PTOR_REG(base) = (value))
+#define GPIO_RMW_PTOR(base, mask, value) (GPIO_WR_PTOR(base, (GPIO_RD_PTOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDIR - Port Data Input Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDIR - Port Data Input Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Do not modify pin configuration registers associated with pins not available
+ * in your selected package. All unbonded pins not available in your package will
+ * default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDIR register
+ */
+/*@{*/
+#define GPIO_RD_PDIR(base)       (GPIO_PDIR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDDR - Port Data Direction Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDDR - Port Data Direction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The PDDR configures the individual port pins for input or output.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDDR register
+ */
+/*@{*/
+#define GPIO_RD_PDDR(base)       (GPIO_PDDR_REG(base))
+#define GPIO_WR_PDDR(base, value) (GPIO_PDDR_REG(base) = (value))
+#define GPIO_RMW_PDDR(base, mask, value) (GPIO_WR_PDDR(base, (GPIO_RD_PDDR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) |  (value)))
+#define GPIO_CLR_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) & ~(value)))
+#define GPIO_TOG_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 I2C
+ *
+ * Inter-Integrated Circuit
+ *
+ * Registers defined in this header file:
+ * - I2C_A1 - I2C Address Register 1
+ * - I2C_F - I2C Frequency Divider register
+ * - I2C_C1 - I2C Control Register 1
+ * - I2C_S - I2C Status register
+ * - I2C_D - I2C Data I/O register
+ * - I2C_C2 - I2C Control Register 2
+ * - I2C_FLT - I2C Programmable Input Glitch Filter register
+ * - I2C_RA - I2C Range Address register
+ * - I2C_SMB - I2C SMBus Control and Status register
+ * - I2C_A2 - I2C Address Register 2
+ * - I2C_SLTH - I2C SCL Low Timeout Register High
+ * - I2C_SLTL - I2C SCL Low Timeout Register Low
+ */
+
+#define I2C_INSTANCE_COUNT (3U) /*!< Number of instances of the I2C module. */
+#define I2C0_IDX (0U) /*!< Instance number for I2C0. */
+#define I2C1_IDX (1U) /*!< Instance number for I2C1. */
+#define I2C2_IDX (2U) /*!< Instance number for I2C2. */
+
+/*******************************************************************************
+ * I2C_A1 - I2C Address Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A1 - I2C Address Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the slave address to be used by the I2C module.
+ */
+/*!
+ * @name Constants and macros for entire I2C_A1 register
+ */
+/*@{*/
+#define I2C_RD_A1(base)          (I2C_A1_REG(base))
+#define I2C_WR_A1(base, value)   (I2C_A1_REG(base) = (value))
+#define I2C_RMW_A1(base, mask, value) (I2C_WR_A1(base, (I2C_RD_A1(base) & ~(mask)) | (value)))
+#define I2C_SET_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) |  (value)))
+#define I2C_CLR_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) & ~(value)))
+#define I2C_TOG_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A1 bitfields
+ */
+
+/*!
+ * @name Register I2C_A1, field AD[7:1] (RW)
+ *
+ * Contains the primary slave address used by the I2C module when it is
+ * addressed as a slave. This field is used in the 7-bit address scheme and the lower
+ * seven bits in the 10-bit address scheme.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A1_AD field. */
+#define I2C_RD_A1_AD(base)   ((I2C_A1_REG(base) & I2C_A1_AD_MASK) >> I2C_A1_AD_SHIFT)
+#define I2C_BRD_A1_AD(base)  (I2C_RD_A1_AD(base))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_A1_AD(base, value) (I2C_RMW_A1(base, I2C_A1_AD_MASK, I2C_A1_AD(value)))
+#define I2C_BWR_A1_AD(base, value) (I2C_WR_A1_AD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_F - I2C Frequency Divider register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_F - I2C Frequency Divider register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_F register
+ */
+/*@{*/
+#define I2C_RD_F(base)           (I2C_F_REG(base))
+#define I2C_WR_F(base, value)    (I2C_F_REG(base) = (value))
+#define I2C_RMW_F(base, mask, value) (I2C_WR_F(base, (I2C_RD_F(base) & ~(mask)) | (value)))
+#define I2C_SET_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) |  (value)))
+#define I2C_CLR_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) & ~(value)))
+#define I2C_TOG_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_F bitfields
+ */
+
+/*!
+ * @name Register I2C_F, field ICR[5:0] (RW)
+ *
+ * Prescales the I2C module clock for bit rate selection. This field and the
+ * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
+ * time, and the SCL stop hold time. For a list of values corresponding to each ICR
+ * setting, see I2C divider and hold values. The SCL divider multiplied by
+ * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
+ * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
+ * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
+ * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
+ * the delay from the falling edge of SDA (I2C data) while SCL is high (start
+ * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
+ * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
+ * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
+ * data) while SCL is high (stop condition). SCL stop hold time = I2C module
+ * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
+ * speed is 8 MHz, the following table shows the possible hold time values with
+ * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
+ * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h
+ * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
+ * 1.125 4.750 5.125
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_ICR field. */
+#define I2C_RD_F_ICR(base)   ((I2C_F_REG(base) & I2C_F_ICR_MASK) >> I2C_F_ICR_SHIFT)
+#define I2C_BRD_F_ICR(base)  (I2C_RD_F_ICR(base))
+
+/*! @brief Set the ICR field to a new value. */
+#define I2C_WR_F_ICR(base, value) (I2C_RMW_F(base, I2C_F_ICR_MASK, I2C_F_ICR(value)))
+#define I2C_BWR_F_ICR(base, value) (I2C_WR_F_ICR(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_F, field MULT[7:6] (RW)
+ *
+ * Defines the multiplier factor (mul). This factor is used along with the SCL
+ * divider to generate the I2C baud rate.
+ *
+ * Values:
+ * - 0b00 - mul = 1
+ * - 0b01 - mul = 2
+ * - 0b10 - mul = 4
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_MULT field. */
+#define I2C_RD_F_MULT(base)  ((I2C_F_REG(base) & I2C_F_MULT_MASK) >> I2C_F_MULT_SHIFT)
+#define I2C_BRD_F_MULT(base) (I2C_RD_F_MULT(base))
+
+/*! @brief Set the MULT field to a new value. */
+#define I2C_WR_F_MULT(base, value) (I2C_RMW_F(base, I2C_F_MULT_MASK, I2C_F_MULT(value)))
+#define I2C_BWR_F_MULT(base, value) (I2C_WR_F_MULT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C1 - I2C Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C1 - I2C Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C1 register
+ */
+/*@{*/
+#define I2C_RD_C1(base)          (I2C_C1_REG(base))
+#define I2C_WR_C1(base, value)   (I2C_C1_REG(base) = (value))
+#define I2C_RMW_C1(base, mask, value) (I2C_WR_C1(base, (I2C_RD_C1(base) & ~(mask)) | (value)))
+#define I2C_SET_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) |  (value)))
+#define I2C_CLR_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) & ~(value)))
+#define I2C_TOG_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C1 bitfields
+ */
+
+/*!
+ * @name Register I2C_C1, field DMAEN[0] (RW)
+ *
+ * Enables or disables the DMA function.
+ *
+ * Values:
+ * - 0b0 - All DMA signalling disabled.
+ * - 0b1 - DMA transfer is enabled. While SMB[FACK] = 0, the following
+ *     conditions trigger the DMA request: a data byte is received, and either address or
+ *     data is transmitted. (ACK/NACK is automatic) the first byte received
+ *     matches the A1 register or is a general call address. If any address matching
+ *     occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
+ *     from master to slave, then it is not required to check S[SRW]. With this
+ *     assumption, DMA can also be used in this case. In other cases, if the master
+ *     reads data from the slave, then it is required to rewrite the C1 register
+ *     operation. With this assumption, DMA cannot be used. When FACK = 1, an
+ *     address or a data byte is transmitted.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_DMAEN field. */
+#define I2C_RD_C1_DMAEN(base) ((I2C_C1_REG(base) & I2C_C1_DMAEN_MASK) >> I2C_C1_DMAEN_SHIFT)
+#define I2C_BRD_C1_DMAEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define I2C_WR_C1_DMAEN(base, value) (I2C_RMW_C1(base, I2C_C1_DMAEN_MASK, I2C_C1_DMAEN(value)))
+#define I2C_BWR_C1_DMAEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field WUEN[1] (RW)
+ *
+ * The I2C module can wake the MCU from low power mode with no peripheral bus
+ * running when slave address matching occurs.
+ *
+ * Values:
+ * - 0b0 - Normal operation. No interrupt generated when address matching in low
+ *     power mode.
+ * - 0b1 - Enables the wakeup function in low power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_WUEN field. */
+#define I2C_RD_C1_WUEN(base) ((I2C_C1_REG(base) & I2C_C1_WUEN_MASK) >> I2C_C1_WUEN_SHIFT)
+#define I2C_BRD_C1_WUEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT))
+
+/*! @brief Set the WUEN field to a new value. */
+#define I2C_WR_C1_WUEN(base, value) (I2C_RMW_C1(base, I2C_C1_WUEN_MASK, I2C_C1_WUEN(value)))
+#define I2C_BWR_C1_WUEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field RSTA[2] (WORZ)
+ *
+ * Writing 1 to this bit generates a repeated START condition provided it is the
+ * current master. This bit will always be read as 0. Attempting a repeat at the
+ * wrong time results in loss of arbitration.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define I2C_WR_C1_RSTA(base, value) (I2C_RMW_C1(base, I2C_C1_RSTA_MASK, I2C_C1_RSTA(value)))
+#define I2C_BWR_C1_RSTA(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_RSTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TXAK[3] (RW)
+ *
+ * Specifies the value driven onto the SDA during data acknowledge cycles for
+ * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
+ * generation. SCL is held low until TXAK is written.
+ *
+ * Values:
+ * - 0b0 - An acknowledge signal is sent to the bus on the following receiving
+ *     byte (if FACK is cleared) or the current receiving byte (if FACK is set).
+ * - 0b1 - No acknowledge signal is sent to the bus on the following receiving
+ *     data byte (if FACK is cleared) or the current receiving data byte (if FACK
+ *     is set).
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TXAK field. */
+#define I2C_RD_C1_TXAK(base) ((I2C_C1_REG(base) & I2C_C1_TXAK_MASK) >> I2C_C1_TXAK_SHIFT)
+#define I2C_BRD_C1_TXAK(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT))
+
+/*! @brief Set the TXAK field to a new value. */
+#define I2C_WR_C1_TXAK(base, value) (I2C_RMW_C1(base, I2C_C1_TXAK_MASK, I2C_C1_TXAK(value)))
+#define I2C_BWR_C1_TXAK(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TX[4] (RW)
+ *
+ * Selects the direction of master and slave transfers. In master mode this bit
+ * must be set according to the type of transfer required. Therefore, for address
+ * cycles, this bit is always set. When addressed as a slave this bit must be
+ * set by software according to the SRW bit in the status register.
+ *
+ * Values:
+ * - 0b0 - Receive
+ * - 0b1 - Transmit
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TX field. */
+#define I2C_RD_C1_TX(base)   ((I2C_C1_REG(base) & I2C_C1_TX_MASK) >> I2C_C1_TX_SHIFT)
+#define I2C_BRD_C1_TX(base)  (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT))
+
+/*! @brief Set the TX field to a new value. */
+#define I2C_WR_C1_TX(base, value) (I2C_RMW_C1(base, I2C_C1_TX_MASK, I2C_C1_TX(value)))
+#define I2C_BWR_C1_TX(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field MST[5] (RW)
+ *
+ * When MST is changed from 0 to 1, a START signal is generated on the bus and
+ * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
+ * generated and the mode of operation changes from master to slave.
+ *
+ * Values:
+ * - 0b0 - Slave mode
+ * - 0b1 - Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_MST field. */
+#define I2C_RD_C1_MST(base)  ((I2C_C1_REG(base) & I2C_C1_MST_MASK) >> I2C_C1_MST_SHIFT)
+#define I2C_BRD_C1_MST(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT))
+
+/*! @brief Set the MST field to a new value. */
+#define I2C_WR_C1_MST(base, value) (I2C_RMW_C1(base, I2C_C1_MST_MASK, I2C_C1_MST(value)))
+#define I2C_BWR_C1_MST(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICIE[6] (RW)
+ *
+ * Enables I2C interrupt requests.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICIE field. */
+#define I2C_RD_C1_IICIE(base) ((I2C_C1_REG(base) & I2C_C1_IICIE_MASK) >> I2C_C1_IICIE_SHIFT)
+#define I2C_BRD_C1_IICIE(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT))
+
+/*! @brief Set the IICIE field to a new value. */
+#define I2C_WR_C1_IICIE(base, value) (I2C_RMW_C1(base, I2C_C1_IICIE_MASK, I2C_C1_IICIE(value)))
+#define I2C_BWR_C1_IICIE(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICEN[7] (RW)
+ *
+ * Enables I2C module operation.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICEN field. */
+#define I2C_RD_C1_IICEN(base) ((I2C_C1_REG(base) & I2C_C1_IICEN_MASK) >> I2C_C1_IICEN_SHIFT)
+#define I2C_BRD_C1_IICEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT))
+
+/*! @brief Set the IICEN field to a new value. */
+#define I2C_WR_C1_IICEN(base, value) (I2C_RMW_C1(base, I2C_C1_IICEN_MASK, I2C_C1_IICEN(value)))
+#define I2C_BWR_C1_IICEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_S - I2C Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_S - I2C Status register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire I2C_S register
+ */
+/*@{*/
+#define I2C_RD_S(base)           (I2C_S_REG(base))
+#define I2C_WR_S(base, value)    (I2C_S_REG(base) = (value))
+#define I2C_RMW_S(base, mask, value) (I2C_WR_S(base, (I2C_RD_S(base) & ~(mask)) | (value)))
+#define I2C_SET_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) |  (value)))
+#define I2C_CLR_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) & ~(value)))
+#define I2C_TOG_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_S bitfields
+ */
+
+/*!
+ * @name Register I2C_S, field RXAK[0] (RO)
+ *
+ * Values:
+ * - 0b0 - Acknowledge signal was received after the completion of one byte of
+ *     data transmission on the bus
+ * - 0b1 - No acknowledge signal detected
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RXAK field. */
+#define I2C_RD_S_RXAK(base)  ((I2C_S_REG(base) & I2C_S_RXAK_MASK) >> I2C_S_RXAK_SHIFT)
+#define I2C_BRD_S_RXAK(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RXAK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IICIF[1] (W1C)
+ *
+ * This bit sets when an interrupt is pending. This bit must be cleared by
+ * software by writing 1 to it, such as in the interrupt routine. One of the following
+ * events can set this bit: One byte transfer, including ACK/NACK bit, completes
+ * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
+ * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
+ * completes if FACK is 1. Match of slave address to calling address including
+ * primary slave address, range slave address , alert response address, second
+ * slave address, or general call address. Arbitration lost In SMBus mode, any
+ * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
+ * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
+ * start detection interrupt: In the interrupt service routine, first clear the
+ * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
+ * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
+ * asserted again.
+ *
+ * Values:
+ * - 0b0 - No interrupt pending
+ * - 0b1 - Interrupt pending
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IICIF field. */
+#define I2C_RD_S_IICIF(base) ((I2C_S_REG(base) & I2C_S_IICIF_MASK) >> I2C_S_IICIF_SHIFT)
+#define I2C_BRD_S_IICIF(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT))
+
+/*! @brief Set the IICIF field to a new value. */
+#define I2C_WR_S_IICIF(base, value) (I2C_RMW_S(base, (I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IICIF(value)))
+#define I2C_BWR_S_IICIF(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field SRW[2] (RO)
+ *
+ * When addressed as a slave, SRW indicates the value of the R/W command bit of
+ * the calling address sent to the master.
+ *
+ * Values:
+ * - 0b0 - Slave receive, master writing to slave
+ * - 0b1 - Slave transmit, master reading from slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_SRW field. */
+#define I2C_RD_S_SRW(base)   ((I2C_S_REG(base) & I2C_S_SRW_MASK) >> I2C_S_SRW_SHIFT)
+#define I2C_BRD_S_SRW(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_SRW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field RAM[3] (RW)
+ *
+ * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
+ * Any nonzero calling address is received that matches the address in the RA
+ * register. The calling address is within the range of values of the A1 and RA
+ * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
+ * Writing the C1 register with any value clears this bit to 0.
+ *
+ * Values:
+ * - 0b0 - Not addressed
+ * - 0b1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RAM field. */
+#define I2C_RD_S_RAM(base)   ((I2C_S_REG(base) & I2C_S_RAM_MASK) >> I2C_S_RAM_SHIFT)
+#define I2C_BRD_S_RAM(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RAM_SHIFT))
+
+/*! @brief Set the RAM field to a new value. */
+#define I2C_WR_S_RAM(base, value) (I2C_RMW_S(base, (I2C_S_RAM_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_RAM(value)))
+#define I2C_BWR_S_RAM(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RAM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field ARBL[4] (W1C)
+ *
+ * This bit is set by hardware when the arbitration procedure is lost. The ARBL
+ * bit must be cleared by software, by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - Standard bus operation.
+ * - 0b1 - Loss of arbitration.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_ARBL field. */
+#define I2C_RD_S_ARBL(base)  ((I2C_S_REG(base) & I2C_S_ARBL_MASK) >> I2C_S_ARBL_SHIFT)
+#define I2C_BRD_S_ARBL(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT))
+
+/*! @brief Set the ARBL field to a new value. */
+#define I2C_WR_S_ARBL(base, value) (I2C_RMW_S(base, (I2C_S_ARBL_MASK | I2C_S_IICIF_MASK), I2C_S_ARBL(value)))
+#define I2C_BWR_S_ARBL(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field BUSY[5] (RO)
+ *
+ * Indicates the status of the bus regardless of slave or master mode. This bit
+ * is set when a START signal is detected and cleared when a STOP signal is
+ * detected.
+ *
+ * Values:
+ * - 0b0 - Bus is idle
+ * - 0b1 - Bus is busy
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_BUSY field. */
+#define I2C_RD_S_BUSY(base)  ((I2C_S_REG(base) & I2C_S_BUSY_MASK) >> I2C_S_BUSY_SHIFT)
+#define I2C_BRD_S_BUSY(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_BUSY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IAAS[6] (RW)
+ *
+ * This bit is set by one of the following conditions: The calling address
+ * matches the programmed primary slave address in the A1 register, or matches the
+ * range address in the RA register (which must be set to a nonzero value and under
+ * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
+ * received. SMB[SIICAEN] is set and the calling address matches the second programmed
+ * slave address. ALERTEN is set and an SMBus alert response address is received
+ * RMEN is set and an address is received that is within the range between the
+ * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
+ * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
+ * value clears this bit.
+ *
+ * Values:
+ * - 0b0 - Not addressed
+ * - 0b1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IAAS field. */
+#define I2C_RD_S_IAAS(base)  ((I2C_S_REG(base) & I2C_S_IAAS_MASK) >> I2C_S_IAAS_SHIFT)
+#define I2C_BRD_S_IAAS(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT))
+
+/*! @brief Set the IAAS field to a new value. */
+#define I2C_WR_S_IAAS(base, value) (I2C_RMW_S(base, (I2C_S_IAAS_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IAAS(value)))
+#define I2C_BWR_S_IAAS(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field TCF[7] (RO)
+ *
+ * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
+ * This bit is valid only during or immediately following a transfer to or from
+ * the I2C module. TCF is cleared by reading the I2C data register in receive mode
+ * or by writing to the I2C data register in transmit mode.
+ *
+ * Values:
+ * - 0b0 - Transfer in progress
+ * - 0b1 - Transfer complete
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_TCF field. */
+#define I2C_RD_S_TCF(base)   ((I2C_S_REG(base) & I2C_S_TCF_MASK) >> I2C_S_TCF_SHIFT)
+#define I2C_BRD_S_TCF(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_TCF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_D - I2C Data I/O register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_D - I2C Data I/O register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_D register
+ */
+/*@{*/
+#define I2C_RD_D(base)           (I2C_D_REG(base))
+#define I2C_WR_D(base, value)    (I2C_D_REG(base) = (value))
+#define I2C_RMW_D(base, mask, value) (I2C_WR_D(base, (I2C_RD_D(base) & ~(mask)) | (value)))
+#define I2C_SET_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) |  (value)))
+#define I2C_CLR_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) & ~(value)))
+#define I2C_TOG_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C2 - I2C Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C2 - I2C Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C2 register
+ */
+/*@{*/
+#define I2C_RD_C2(base)          (I2C_C2_REG(base))
+#define I2C_WR_C2(base, value)   (I2C_C2_REG(base) = (value))
+#define I2C_RMW_C2(base, mask, value) (I2C_WR_C2(base, (I2C_RD_C2(base) & ~(mask)) | (value)))
+#define I2C_SET_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) |  (value)))
+#define I2C_CLR_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) & ~(value)))
+#define I2C_TOG_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C2 bitfields
+ */
+
+/*!
+ * @name Register I2C_C2, field AD[2:0] (RW)
+ *
+ * Contains the upper three bits of the slave address in the 10-bit address
+ * scheme. This field is valid only while the ADEXT bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_AD field. */
+#define I2C_RD_C2_AD(base)   ((I2C_C2_REG(base) & I2C_C2_AD_MASK) >> I2C_C2_AD_SHIFT)
+#define I2C_BRD_C2_AD(base)  (I2C_RD_C2_AD(base))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_C2_AD(base, value) (I2C_RMW_C2(base, I2C_C2_AD_MASK, I2C_C2_AD(value)))
+#define I2C_BWR_C2_AD(base, value) (I2C_WR_C2_AD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field RMEN[3] (RW)
+ *
+ * This bit controls the slave address matching for addresses between the values
+ * of the A1 and RA registers. When this bit is set, a slave address matching
+ * occurs for any address greater than the value of the A1 register and less than
+ * or equal to the value of the RA register.
+ *
+ * Values:
+ * - 0b0 - Range mode disabled. No address matching occurs for an address within
+ *     the range of values of the A1 and RA registers.
+ * - 0b1 - Range mode enabled. Address matching occurs when a slave receives an
+ *     address within the range of values of the A1 and RA registers.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_RMEN field. */
+#define I2C_RD_C2_RMEN(base) ((I2C_C2_REG(base) & I2C_C2_RMEN_MASK) >> I2C_C2_RMEN_SHIFT)
+#define I2C_BRD_C2_RMEN(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT))
+
+/*! @brief Set the RMEN field to a new value. */
+#define I2C_WR_C2_RMEN(base, value) (I2C_RMW_C2(base, I2C_C2_RMEN_MASK, I2C_C2_RMEN(value)))
+#define I2C_BWR_C2_RMEN(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field SBRC[4] (RW)
+ *
+ * Enables independent slave mode baud rate at maximum frequency, which forces
+ * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
+ * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
+ * capture the master's data at only 10 kbit/s.
+ *
+ * Values:
+ * - 0b0 - The slave baud rate follows the master baud rate and clock stretching
+ *     may occur
+ * - 0b1 - Slave baud rate is independent of the master baud rate
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_SBRC field. */
+#define I2C_RD_C2_SBRC(base) ((I2C_C2_REG(base) & I2C_C2_SBRC_MASK) >> I2C_C2_SBRC_SHIFT)
+#define I2C_BRD_C2_SBRC(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT))
+
+/*! @brief Set the SBRC field to a new value. */
+#define I2C_WR_C2_SBRC(base, value) (I2C_RMW_C2(base, I2C_C2_SBRC_MASK, I2C_C2_SBRC(value)))
+#define I2C_BWR_C2_SBRC(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field HDRS[5] (RW)
+ *
+ * Controls the drive capability of the I2C pads.
+ *
+ * Values:
+ * - 0b0 - Normal drive mode
+ * - 0b1 - High drive mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_HDRS field. */
+#define I2C_RD_C2_HDRS(base) ((I2C_C2_REG(base) & I2C_C2_HDRS_MASK) >> I2C_C2_HDRS_SHIFT)
+#define I2C_BRD_C2_HDRS(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT))
+
+/*! @brief Set the HDRS field to a new value. */
+#define I2C_WR_C2_HDRS(base, value) (I2C_RMW_C2(base, I2C_C2_HDRS_MASK, I2C_C2_HDRS(value)))
+#define I2C_BWR_C2_HDRS(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field ADEXT[6] (RW)
+ *
+ * Controls the number of bits used for the slave address.
+ *
+ * Values:
+ * - 0b0 - 7-bit address scheme
+ * - 0b1 - 10-bit address scheme
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_ADEXT field. */
+#define I2C_RD_C2_ADEXT(base) ((I2C_C2_REG(base) & I2C_C2_ADEXT_MASK) >> I2C_C2_ADEXT_SHIFT)
+#define I2C_BRD_C2_ADEXT(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT))
+
+/*! @brief Set the ADEXT field to a new value. */
+#define I2C_WR_C2_ADEXT(base, value) (I2C_RMW_C2(base, I2C_C2_ADEXT_MASK, I2C_C2_ADEXT(value)))
+#define I2C_BWR_C2_ADEXT(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field GCAEN[7] (RW)
+ *
+ * Enables general call address.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_GCAEN field. */
+#define I2C_RD_C2_GCAEN(base) ((I2C_C2_REG(base) & I2C_C2_GCAEN_MASK) >> I2C_C2_GCAEN_SHIFT)
+#define I2C_BRD_C2_GCAEN(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT))
+
+/*! @brief Set the GCAEN field to a new value. */
+#define I2C_WR_C2_GCAEN(base, value) (I2C_RMW_C2(base, I2C_C2_GCAEN_MASK, I2C_C2_GCAEN(value)))
+#define I2C_BWR_C2_GCAEN(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_FLT - I2C Programmable Input Glitch Filter register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_FLT register
+ */
+/*@{*/
+#define I2C_RD_FLT(base)         (I2C_FLT_REG(base))
+#define I2C_WR_FLT(base, value)  (I2C_FLT_REG(base) = (value))
+#define I2C_RMW_FLT(base, mask, value) (I2C_WR_FLT(base, (I2C_RD_FLT(base) & ~(mask)) | (value)))
+#define I2C_SET_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) |  (value)))
+#define I2C_CLR_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) & ~(value)))
+#define I2C_TOG_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_FLT bitfields
+ */
+
+/*!
+ * @name Register I2C_FLT, field FLT[3:0] (RW)
+ *
+ * Controls the width of the glitch, in terms of I2C module clock cycles, that
+ * the filter must absorb. For any glitch whose size is less than or equal to this
+ * width setting, the filter does not allow the glitch to pass.
+ *
+ * Values:
+ * - 0b0000 - No filter/bypass
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_FLT field. */
+#define I2C_RD_FLT_FLT(base) ((I2C_FLT_REG(base) & I2C_FLT_FLT_MASK) >> I2C_FLT_FLT_SHIFT)
+#define I2C_BRD_FLT_FLT(base) (I2C_RD_FLT_FLT(base))
+
+/*! @brief Set the FLT field to a new value. */
+#define I2C_WR_FLT_FLT(base, value) (I2C_RMW_FLT(base, (I2C_FLT_FLT_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_FLT(value)))
+#define I2C_BWR_FLT_FLT(base, value) (I2C_WR_FLT_FLT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STARTF[4] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's start status is detected. The
+ * STARTF bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No start happens on I2C bus
+ * - 0b1 - Start detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STARTF field. */
+#define I2C_RD_FLT_STARTF(base) ((I2C_FLT_REG(base) & I2C_FLT_STARTF_MASK) >> I2C_FLT_STARTF_SHIFT)
+#define I2C_BRD_FLT_STARTF(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT))
+
+/*! @brief Set the STARTF field to a new value. */
+#define I2C_WR_FLT_STARTF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_STARTF(value)))
+#define I2C_BWR_FLT_STARTF(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SSIE[5] (RW)
+ *
+ * This bit enables the interrupt for I2C bus stop or start detection. To clear
+ * the I2C bus stop or start detection interrupt: In the interrupt service
+ * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
+ * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
+ * is asserted again.
+ *
+ * Values:
+ * - 0b0 - Stop or start detection interrupt is disabled
+ * - 0b1 - Stop or start detection interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SSIE field. */
+#define I2C_RD_FLT_SSIE(base) ((I2C_FLT_REG(base) & I2C_FLT_SSIE_MASK) >> I2C_FLT_SSIE_SHIFT)
+#define I2C_BRD_FLT_SSIE(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT))
+
+/*! @brief Set the SSIE field to a new value. */
+#define I2C_WR_FLT_SSIE(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SSIE_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SSIE(value)))
+#define I2C_BWR_FLT_SSIE(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STOPF[6] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
+ * bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No stop happens on I2C bus
+ * - 0b1 - Stop detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STOPF field. */
+#define I2C_RD_FLT_STOPF(base) ((I2C_FLT_REG(base) & I2C_FLT_STOPF_MASK) >> I2C_FLT_STOPF_SHIFT)
+#define I2C_BRD_FLT_STOPF(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT))
+
+/*! @brief Set the STOPF field to a new value. */
+#define I2C_WR_FLT_STOPF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK), I2C_FLT_STOPF(value)))
+#define I2C_BWR_FLT_STOPF(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SHEN[7] (RW)
+ *
+ * Set this bit to hold off entry to stop mode when any data transmission or
+ * reception is occurring. The following scenario explains the holdoff
+ * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
+ * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
+ * byte currently being transferred, including both address and data, completes
+ * its transfer. The I2C slave or master acknowledges that the in-transfer byte
+ * completed its transfer and acknowledges the request to enter stop mode. After
+ * receiving the I2C module's acknowledgment of the request to enter stop mode,
+ * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
+ * is set to 1 and the I2C module is in an idle or disabled state when the MCU
+ * signals to enter stop mode, the module immediately acknowledges the request to
+ * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
+ * reception that was suspended by stop mode entry was incomplete: To resume the
+ * overall transmission or reception after the MCU exits stop mode, software must
+ * reinitialize the transfer by resending the address of the slave. If the I2C
+ * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
+ * system software will receive the interrupt triggered by the I2C Status Register's
+ * TCF bit after the MCU wakes from the stop mode.
+ *
+ * Values:
+ * - 0b0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
+ * - 0b1 - Stop holdoff is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SHEN field. */
+#define I2C_RD_FLT_SHEN(base) ((I2C_FLT_REG(base) & I2C_FLT_SHEN_MASK) >> I2C_FLT_SHEN_SHIFT)
+#define I2C_BRD_FLT_SHEN(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT))
+
+/*! @brief Set the SHEN field to a new value. */
+#define I2C_WR_FLT_SHEN(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SHEN_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SHEN(value)))
+#define I2C_BWR_FLT_SHEN(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_RA - I2C Range Address register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_RA - I2C Range Address register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_RA register
+ */
+/*@{*/
+#define I2C_RD_RA(base)          (I2C_RA_REG(base))
+#define I2C_WR_RA(base, value)   (I2C_RA_REG(base) = (value))
+#define I2C_RMW_RA(base, mask, value) (I2C_WR_RA(base, (I2C_RD_RA(base) & ~(mask)) | (value)))
+#define I2C_SET_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) |  (value)))
+#define I2C_CLR_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) & ~(value)))
+#define I2C_TOG_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_RA bitfields
+ */
+
+/*!
+ * @name Register I2C_RA, field RAD[7:1] (RW)
+ *
+ * This field contains the slave address to be used by the I2C module. The field
+ * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
+ * value write enables this register. This register value can be considered as a
+ * maximum boundary in the range matching mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_RA_RAD field. */
+#define I2C_RD_RA_RAD(base)  ((I2C_RA_REG(base) & I2C_RA_RAD_MASK) >> I2C_RA_RAD_SHIFT)
+#define I2C_BRD_RA_RAD(base) (I2C_RD_RA_RAD(base))
+
+/*! @brief Set the RAD field to a new value. */
+#define I2C_WR_RA_RAD(base, value) (I2C_RMW_RA(base, I2C_RA_RAD_MASK, I2C_RA_RAD(value)))
+#define I2C_BWR_RA_RAD(base, value) (I2C_WR_RA_RAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SMB - I2C SMBus Control and Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SMB - I2C SMBus Control and Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When the SCL and SDA signals are held high for a length of time greater than
+ * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
+ * while the system is detecting how long these signals are being held high, a
+ * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
+ * bus transmission process with the idle bus state. When the TCKSEL bit is set,
+ * there is no need to monitor the SHTF1 bit because the bus speed is too high to
+ * match the protocol of SMBus.
+ */
+/*!
+ * @name Constants and macros for entire I2C_SMB register
+ */
+/*@{*/
+#define I2C_RD_SMB(base)         (I2C_SMB_REG(base))
+#define I2C_WR_SMB(base, value)  (I2C_SMB_REG(base) = (value))
+#define I2C_RMW_SMB(base, mask, value) (I2C_WR_SMB(base, (I2C_RD_SMB(base) & ~(mask)) | (value)))
+#define I2C_SET_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) |  (value)))
+#define I2C_CLR_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) & ~(value)))
+#define I2C_TOG_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_SMB bitfields
+ */
+
+/*!
+ * @name Register I2C_SMB, field SHTF2IE[0] (RW)
+ *
+ * Enables SCL high and SDA low timeout interrupt.
+ *
+ * Values:
+ * - 0b0 - SHTF2 interrupt is disabled
+ * - 0b1 - SHTF2 interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2IE field. */
+#define I2C_RD_SMB_SHTF2IE(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2IE_MASK) >> I2C_SMB_SHTF2IE_SHIFT)
+#define I2C_BRD_SMB_SHTF2IE(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT))
+
+/*! @brief Set the SHTF2IE field to a new value. */
+#define I2C_WR_SMB_SHTF2IE(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2IE_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2IE(value)))
+#define I2C_BWR_SMB_SHTF2IE(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF2[1] (W1C)
+ *
+ * This bit sets when SCL is held high and SDA is held low more than clock *
+ * LoValue / 512. Software clears this bit by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No SCL high and SDA low timeout occurs
+ * - 0b1 - SCL high and SDA low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2 field. */
+#define I2C_RD_SMB_SHTF2(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2_MASK) >> I2C_SMB_SHTF2_SHIFT)
+#define I2C_BRD_SMB_SHTF2(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT))
+
+/*! @brief Set the SHTF2 field to a new value. */
+#define I2C_WR_SMB_SHTF2(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2(value)))
+#define I2C_BWR_SMB_SHTF2(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF1[2] (RO)
+ *
+ * This read-only bit sets when SCL and SDA are held high more than clock *
+ * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
+ *
+ * Values:
+ * - 0b0 - No SCL high and SDA high timeout occurs
+ * - 0b1 - SCL high and SDA high timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF1 field. */
+#define I2C_RD_SMB_SHTF1(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF1_MASK) >> I2C_SMB_SHTF1_SHIFT)
+#define I2C_BRD_SMB_SHTF1(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SLTF[3] (W1C)
+ *
+ * This bit is set when the SLT register (consisting of the SLTH and SLTL
+ * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
+ * Software clears this bit by writing a logic 1 to it. The low timeout function
+ * is disabled when the SLT register's value is 0.
+ *
+ * Values:
+ * - 0b0 - No low timeout occurs
+ * - 0b1 - Low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SLTF field. */
+#define I2C_RD_SMB_SLTF(base) ((I2C_SMB_REG(base) & I2C_SMB_SLTF_MASK) >> I2C_SMB_SLTF_SHIFT)
+#define I2C_BRD_SMB_SLTF(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT))
+
+/*! @brief Set the SLTF field to a new value. */
+#define I2C_WR_SMB_SLTF(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SLTF_MASK | I2C_SMB_SHTF2_MASK), I2C_SMB_SLTF(value)))
+#define I2C_BWR_SMB_SLTF(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field TCKSEL[4] (RW)
+ *
+ * Selects the clock source of the timeout counter.
+ *
+ * Values:
+ * - 0b0 - Timeout counter counts at the frequency of the I2C module clock / 64
+ * - 0b1 - Timeout counter counts at the frequency of the I2C module clock
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_TCKSEL field. */
+#define I2C_RD_SMB_TCKSEL(base) ((I2C_SMB_REG(base) & I2C_SMB_TCKSEL_MASK) >> I2C_SMB_TCKSEL_SHIFT)
+#define I2C_BRD_SMB_TCKSEL(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT))
+
+/*! @brief Set the TCKSEL field to a new value. */
+#define I2C_WR_SMB_TCKSEL(base, value) (I2C_RMW_SMB(base, (I2C_SMB_TCKSEL_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_TCKSEL(value)))
+#define I2C_BWR_SMB_TCKSEL(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SIICAEN[5] (RW)
+ *
+ * Enables or disables SMBus device default address.
+ *
+ * Values:
+ * - 0b0 - I2C address register 2 matching is disabled
+ * - 0b1 - I2C address register 2 matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SIICAEN field. */
+#define I2C_RD_SMB_SIICAEN(base) ((I2C_SMB_REG(base) & I2C_SMB_SIICAEN_MASK) >> I2C_SMB_SIICAEN_SHIFT)
+#define I2C_BRD_SMB_SIICAEN(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT))
+
+/*! @brief Set the SIICAEN field to a new value. */
+#define I2C_WR_SMB_SIICAEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SIICAEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SIICAEN(value)))
+#define I2C_BWR_SMB_SIICAEN(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field ALERTEN[6] (RW)
+ *
+ * Enables or disables SMBus alert response address matching. After the host
+ * responds to a device that used the alert response address, you must use software
+ * to put the device's address on the bus. The alert protocol is described in the
+ * SMBus specification.
+ *
+ * Values:
+ * - 0b0 - SMBus alert response address matching is disabled
+ * - 0b1 - SMBus alert response address matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_ALERTEN field. */
+#define I2C_RD_SMB_ALERTEN(base) ((I2C_SMB_REG(base) & I2C_SMB_ALERTEN_MASK) >> I2C_SMB_ALERTEN_SHIFT)
+#define I2C_BRD_SMB_ALERTEN(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT))
+
+/*! @brief Set the ALERTEN field to a new value. */
+#define I2C_WR_SMB_ALERTEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_ALERTEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_ALERTEN(value)))
+#define I2C_BWR_SMB_ALERTEN(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field FACK[7] (RW)
+ *
+ * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
+ * according to the result of receiving data byte.
+ *
+ * Values:
+ * - 0b0 - An ACK or NACK is sent on the following receiving data byte
+ * - 0b1 - Writing 0 to TXAK after receiving a data byte generates an ACK.
+ *     Writing 1 to TXAK after receiving a data byte generates a NACK.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_FACK field. */
+#define I2C_RD_SMB_FACK(base) ((I2C_SMB_REG(base) & I2C_SMB_FACK_MASK) >> I2C_SMB_FACK_SHIFT)
+#define I2C_BRD_SMB_FACK(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT))
+
+/*! @brief Set the FACK field to a new value. */
+#define I2C_WR_SMB_FACK(base, value) (I2C_RMW_SMB(base, (I2C_SMB_FACK_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_FACK(value)))
+#define I2C_BWR_SMB_FACK(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_A2 - I2C Address Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A2 - I2C Address Register 2 (RW)
+ *
+ * Reset value: 0xC2U
+ */
+/*!
+ * @name Constants and macros for entire I2C_A2 register
+ */
+/*@{*/
+#define I2C_RD_A2(base)          (I2C_A2_REG(base))
+#define I2C_WR_A2(base, value)   (I2C_A2_REG(base) = (value))
+#define I2C_RMW_A2(base, mask, value) (I2C_WR_A2(base, (I2C_RD_A2(base) & ~(mask)) | (value)))
+#define I2C_SET_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) |  (value)))
+#define I2C_CLR_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) & ~(value)))
+#define I2C_TOG_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A2 bitfields
+ */
+
+/*!
+ * @name Register I2C_A2, field SAD[7:1] (RW)
+ *
+ * Contains the slave address used by the SMBus. This field is used on the
+ * device default address or other related addresses.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A2_SAD field. */
+#define I2C_RD_A2_SAD(base)  ((I2C_A2_REG(base) & I2C_A2_SAD_MASK) >> I2C_A2_SAD_SHIFT)
+#define I2C_BRD_A2_SAD(base) (I2C_RD_A2_SAD(base))
+
+/*! @brief Set the SAD field to a new value. */
+#define I2C_WR_A2_SAD(base, value) (I2C_RMW_A2(base, I2C_A2_SAD_MASK, I2C_A2_SAD(value)))
+#define I2C_BWR_A2_SAD(base, value) (I2C_WR_A2_SAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTH - I2C SCL Low Timeout Register High
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTH - I2C SCL Low Timeout Register High (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTH register
+ */
+/*@{*/
+#define I2C_RD_SLTH(base)        (I2C_SLTH_REG(base))
+#define I2C_WR_SLTH(base, value) (I2C_SLTH_REG(base) = (value))
+#define I2C_RMW_SLTH(base, mask, value) (I2C_WR_SLTH(base, (I2C_RD_SLTH(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) |  (value)))
+#define I2C_CLR_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) & ~(value)))
+#define I2C_TOG_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTL - I2C SCL Low Timeout Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTL register
+ */
+/*@{*/
+#define I2C_RD_SLTL(base)        (I2C_SLTL_REG(base))
+#define I2C_WR_SLTL(base, value) (I2C_SLTL_REG(base) = (value))
+#define I2C_RMW_SLTL(base, mask, value) (I2C_WR_SLTL(base, (I2C_RD_SLTL(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) |  (value)))
+#define I2C_CLR_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) & ~(value)))
+#define I2C_TOG_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 I2S
+ *
+ * Inter-IC Sound / Synchronous Audio Interface
+ *
+ * Registers defined in this header file:
+ * - I2S_TCSR - SAI Transmit Control Register
+ * - I2S_TCR1 - SAI Transmit Configuration 1 Register
+ * - I2S_TCR2 - SAI Transmit Configuration 2 Register
+ * - I2S_TCR3 - SAI Transmit Configuration 3 Register
+ * - I2S_TCR4 - SAI Transmit Configuration 4 Register
+ * - I2S_TCR5 - SAI Transmit Configuration 5 Register
+ * - I2S_TDR - SAI Transmit Data Register
+ * - I2S_TFR - SAI Transmit FIFO Register
+ * - I2S_TMR - SAI Transmit Mask Register
+ * - I2S_RCSR - SAI Receive Control Register
+ * - I2S_RCR1 - SAI Receive Configuration 1 Register
+ * - I2S_RCR2 - SAI Receive Configuration 2 Register
+ * - I2S_RCR3 - SAI Receive Configuration 3 Register
+ * - I2S_RCR4 - SAI Receive Configuration 4 Register
+ * - I2S_RCR5 - SAI Receive Configuration 5 Register
+ * - I2S_RDR - SAI Receive Data Register
+ * - I2S_RFR - SAI Receive FIFO Register
+ * - I2S_RMR - SAI Receive Mask Register
+ * - I2S_MCR - SAI MCLK Control Register
+ * - I2S_MDR - SAI MCLK Divide Register
+ */
+
+#define I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */
+#define I2S0_IDX (0U) /*!< Instance number for I2S0. */
+
+/*******************************************************************************
+ * I2S_TCSR - SAI Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCSR - SAI Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCSR register
+ */
+/*@{*/
+#define I2S_RD_TCSR(base)        (I2S_TCSR_REG(base))
+#define I2S_WR_TCSR(base, value) (I2S_TCSR_REG(base) = (value))
+#define I2S_RMW_TCSR(base, mask, value) (I2S_WR_TCSR(base, (I2S_RD_TCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) |  (value)))
+#define I2S_CLR_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) & ~(value)))
+#define I2S_TOG_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_TCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRDE field. */
+#define I2S_RD_TCSR_FRDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRDE_MASK) >> I2S_TCSR_FRDE_SHIFT)
+#define I2S_BRD_TCSR_FRDE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRDE_SHIFT))
+
+/*! @brief Set the FRDE field to a new value. */
+#define I2S_WR_TCSR_FRDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FRDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FRDE(value)))
+#define I2S_BWR_TCSR_FRDE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWDE field. */
+#define I2S_RD_TCSR_FWDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWDE_MASK) >> I2S_TCSR_FWDE_SHIFT)
+#define I2S_BRD_TCSR_FWDE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_TCSR_FWDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWDE(value)))
+#define I2S_BWR_TCSR_FWDE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRIE field. */
+#define I2S_RD_TCSR_FRIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRIE_MASK) >> I2S_TCSR_FRIE_SHIFT)
+#define I2S_BRD_TCSR_FRIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRIE_SHIFT))
+
+/*! @brief Set the FRIE field to a new value. */
+#define I2S_WR_TCSR_FRIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FRIE(value)))
+#define I2S_BWR_TCSR_FRIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWIE field. */
+#define I2S_RD_TCSR_FWIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWIE_MASK) >> I2S_TCSR_FWIE_SHIFT)
+#define I2S_BRD_TCSR_FWIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_TCSR_FWIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWIE(value)))
+#define I2S_BWR_TCSR_FWIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEIE field. */
+#define I2S_RD_TCSR_FEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEIE_MASK) >> I2S_TCSR_FEIE_SHIFT)
+#define I2S_BRD_TCSR_FEIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_TCSR_FEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEIE(value)))
+#define I2S_BWR_TCSR_FEIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEIE field. */
+#define I2S_RD_TCSR_SEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEIE_MASK) >> I2S_TCSR_SEIE_SHIFT)
+#define I2S_BRD_TCSR_SEIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_TCSR_SEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEIE(value)))
+#define I2S_BWR_TCSR_SEIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSIE field. */
+#define I2S_RD_TCSR_WSIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSIE_MASK) >> I2S_TCSR_WSIE_SHIFT)
+#define I2S_BRD_TCSR_WSIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_TCSR_WSIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_WSIE(value)))
+#define I2S_BWR_TCSR_WSIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled transmit channel FIFO is
+ * less than or equal to the transmit FIFO watermark.
+ *
+ * Values:
+ * - 0b0 - Transmit FIFO watermark has not been reached.
+ * - 0b1 - Transmit FIFO watermark has been reached.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRF field. */
+#define I2S_RD_TCSR_FRF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRF_MASK) >> I2S_TCSR_FRF_SHIFT)
+#define I2S_BRD_TCSR_FRF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled transmit FIFO is empty.
+ *
+ * Values:
+ * - 0b0 - No enabled transmit FIFO is empty.
+ * - 0b1 - Enabled transmit FIFO is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWF field. */
+#define I2S_RD_TCSR_FWF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWF_MASK) >> I2S_TCSR_FWF_SHIFT)
+#define I2S_BRD_TCSR_FWF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
+ * field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Transmit underrun not detected.
+ * - 0b1 - Transmit underrun detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEF field. */
+#define I2S_RD_TCSR_FEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEF_MASK) >> I2S_TCSR_FEF_SHIFT)
+#define I2S_BRD_TCSR_FEF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_TCSR_FEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEF(value)))
+#define I2S_BWR_TCSR_FEF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Sync error not detected.
+ * - 0b1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEF field. */
+#define I2S_RD_TCSR_SEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEF_MASK) >> I2S_TCSR_SEF_SHIFT)
+#define I2S_BRD_TCSR_SEF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_TCSR_SEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEF(value)))
+#define I2S_BWR_TCSR_SEF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Start of word not detected.
+ * - 0b1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSF field. */
+#define I2S_RD_TCSR_WSF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSF_MASK) >> I2S_TCSR_WSF_SHIFT)
+#define I2S_BRD_TCSR_WSF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_TCSR_WSF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK), I2S_TCSR_WSF(value)))
+#define I2S_BWR_TCSR_WSF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SR[24] (RW)
+ *
+ * When set, resets the internal transmitter logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SR field. */
+#define I2S_RD_TCSR_SR(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SR_MASK) >> I2S_TCSR_SR_SHIFT)
+#define I2S_BRD_TCSR_SR(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_TCSR_SR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SR(value)))
+#define I2S_BWR_TCSR_SR(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the transmitter is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_TCSR_FR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FR(value)))
+#define I2S_BWR_TCSR_FR(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field BCE[28] (RW)
+ *
+ * Enables the transmit bit clock, separately from the TE. This field is
+ * automatically set whenever TE is set. When software clears this field, the transmit
+ * bit clock remains enabled, and this bit remains set, until the end of the
+ * current frame.
+ *
+ * Values:
+ * - 0b0 - Transmit bit clock is disabled.
+ * - 0b1 - Transmit bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_BCE field. */
+#define I2S_RD_TCSR_BCE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_BCE_MASK) >> I2S_TCSR_BCE_SHIFT)
+#define I2S_BRD_TCSR_BCE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_TCSR_BCE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_BCE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_BCE(value)))
+#define I2S_BWR_TCSR_BCE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables transmitter operation in Debug mode. The transmit bit clock
+ * is not affected by debug mode.
+ *
+ * Values:
+ * - 0b0 - Transmitter is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 0b1 - Transmitter is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_DBGE field. */
+#define I2S_RD_TCSR_DBGE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_DBGE_MASK) >> I2S_TCSR_DBGE_SHIFT)
+#define I2S_BRD_TCSR_DBGE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_TCSR_DBGE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_DBGE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_DBGE(value)))
+#define I2S_BWR_TCSR_DBGE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field STOPE[30] (RW)
+ *
+ * Configures transmitter operation in Stop mode. This field is ignored and the
+ * transmitter is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0b0 - Transmitter disabled in Stop mode.
+ * - 0b1 - Transmitter enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_STOPE field. */
+#define I2S_RD_TCSR_STOPE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_STOPE_MASK) >> I2S_TCSR_STOPE_SHIFT)
+#define I2S_BRD_TCSR_STOPE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_TCSR_STOPE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_STOPE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_STOPE(value)))
+#define I2S_BWR_TCSR_STOPE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field TE[31] (RW)
+ *
+ * Enables/disables the transmitter. When software clears this field, the
+ * transmitter remains enabled, and this bit remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0b0 - Transmitter is disabled.
+ * - 0b1 - Transmitter is enabled, or transmitter has been disabled and has not
+ *     yet reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_TE field. */
+#define I2S_RD_TCSR_TE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_TE_MASK) >> I2S_TCSR_TE_SHIFT)
+#define I2S_BRD_TCSR_TE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT))
+
+/*! @brief Set the TE field to a new value. */
+#define I2S_WR_TCSR_TE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_TE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_TE(value)))
+#define I2S_BWR_TCSR_TE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR1 - SAI Transmit Configuration 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR1 register
+ */
+/*@{*/
+#define I2S_RD_TCR1(base)        (I2S_TCR1_REG(base))
+#define I2S_WR_TCR1(base, value) (I2S_TCR1_REG(base) = (value))
+#define I2S_RMW_TCR1(base, mask, value) (I2S_WR_TCR1(base, (I2S_RD_TCR1(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) |  (value)))
+#define I2S_CLR_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) & ~(value)))
+#define I2S_TOG_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR1, field TFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled transmit channels.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR1_TFW field. */
+#define I2S_RD_TCR1_TFW(base) ((I2S_TCR1_REG(base) & I2S_TCR1_TFW_MASK) >> I2S_TCR1_TFW_SHIFT)
+#define I2S_BRD_TCR1_TFW(base) (I2S_RD_TCR1_TFW(base))
+
+/*! @brief Set the TFW field to a new value. */
+#define I2S_WR_TCR1_TFW(base, value) (I2S_RMW_TCR1(base, I2S_TCR1_TFW_MASK, I2S_TCR1_TFW(value)))
+#define I2S_BWR_TCR1_TFW(base, value) (I2S_WR_TCR1_TFW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR2 - SAI Transmit Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR2 register
+ */
+/*@{*/
+#define I2S_RD_TCR2(base)        (I2S_TCR2_REG(base))
+#define I2S_WR_TCR2(base, value) (I2S_TCR2_REG(base) = (value))
+#define I2S_RMW_TCR2(base, mask, value) (I2S_WR_TCR2(base, (I2S_RD_TCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) |  (value)))
+#define I2S_CLR_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) & ~(value)))
+#define I2S_TOG_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_DIV field. */
+#define I2S_RD_TCR2_DIV(base) ((I2S_TCR2_REG(base) & I2S_TCR2_DIV_MASK) >> I2S_TCR2_DIV_SHIFT)
+#define I2S_BRD_TCR2_DIV(base) (I2S_RD_TCR2_DIV(base))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_TCR2_DIV(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_DIV_MASK, I2S_TCR2_DIV(value)))
+#define I2S_BWR_TCR2_DIV(base, value) (I2S_WR_TCR2_DIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is generated externally in Slave mode.
+ * - 0b1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCD field. */
+#define I2S_RD_TCR2_BCD(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCD_MASK) >> I2S_TCR2_BCD_SHIFT)
+#define I2S_BRD_TCR2_BCD(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_TCR2_BCD(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCD_MASK, I2S_TCR2_BCD(value)))
+#define I2S_BWR_TCR2_BCD(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 0b1 - Bit clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCP field. */
+#define I2S_RD_TCR2_BCP(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCP_MASK) >> I2S_TCR2_BCP_SHIFT)
+#define I2S_BRD_TCR2_BCP(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_TCR2_BCP(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCP_MASK, I2S_TCR2_BCP(value)))
+#define I2S_BWR_TCR2_BCP(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 0b00 - Bus Clock selected.
+ * - 0b01 - Master Clock (MCLK) 1 option selected.
+ * - 0b10 - Master Clock (MCLK) 2 option selected.
+ * - 0b11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_MSEL field. */
+#define I2S_RD_TCR2_MSEL(base) ((I2S_TCR2_REG(base) & I2S_TCR2_MSEL_MASK) >> I2S_TCR2_MSEL_SHIFT)
+#define I2S_BRD_TCR2_MSEL(base) (I2S_RD_TCR2_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_TCR2_MSEL(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_MSEL_MASK, I2S_TCR2_MSEL(value)))
+#define I2S_BWR_TCR2_MSEL(base, value) (I2S_WR_TCR2_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the
+ * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
+ * input as if the clock was externally generated). This has the effect of
+ * decreasing the data input setup time, but increasing the data output valid time. The
+ * slave mode timing from the datasheet should be used for the transmitter when
+ * this bit is set. In synchronous mode, this bit allows the transmitter to use
+ * the slave mode timing from the datasheet, while the receiver uses the master
+ * mode timing. This field has no effect when configured for an externally generated
+ * bit clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCI field. */
+#define I2S_RD_TCR2_BCI(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCI_MASK) >> I2S_TCR2_BCI_SHIFT)
+#define I2S_BRD_TCR2_BCI(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_TCR2_BCI(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCI_MASK, I2S_TCR2_BCI(value)))
+#define I2S_BWR_TCR2_BCI(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the transmitter. When the transmitter
+ * is configured in asynchronous mode and this bit is set, the transmitter is
+ * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the transmitter continues to use the
+ * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
+ * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
+ * the same value. When both are set, the transmitter and receiver are both
+ * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
+ * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
+ * peripheral.
+ *
+ * Values:
+ * - 0b0 - Use the normal bit clock source.
+ * - 0b1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCS field. */
+#define I2S_RD_TCR2_BCS(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCS_MASK) >> I2S_TCR2_BCS_SHIFT)
+#define I2S_BRD_TCR2_BCS(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_TCR2_BCS(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCS_MASK, I2S_TCR2_BCS(value)))
+#define I2S_BWR_TCR2_BCS(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the receiver or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 0b00 - Asynchronous mode.
+ * - 0b01 - Synchronous with receiver.
+ * - 0b10 - Synchronous with another SAI transmitter.
+ * - 0b11 - Synchronous with another SAI receiver.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_SYNC field. */
+#define I2S_RD_TCR2_SYNC(base) ((I2S_TCR2_REG(base) & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT)
+#define I2S_BRD_TCR2_SYNC(base) (I2S_RD_TCR2_SYNC(base))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_TCR2_SYNC(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_SYNC_MASK, I2S_TCR2_SYNC(value)))
+#define I2S_BWR_TCR2_SYNC(base, value) (I2S_WR_TCR2_SYNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR3 - SAI Transmit Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR3 register
+ */
+/*@{*/
+#define I2S_RD_TCR3(base)        (I2S_TCR3_REG(base))
+#define I2S_WR_TCR3(base, value) (I2S_TCR3_REG(base) = (value))
+#define I2S_RMW_TCR3(base, mask, value) (I2S_WR_TCR3(base, (I2S_RD_TCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) |  (value)))
+#define I2S_CLR_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) & ~(value)))
+#define I2S_TOG_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word sets the start of word flag. The value written must be
+ * one less than the word number. For example, writing 0 configures the first
+ * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
+ * start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_WDFL field. */
+#define I2S_RD_TCR3_WDFL(base) ((I2S_TCR3_REG(base) & I2S_TCR3_WDFL_MASK) >> I2S_TCR3_WDFL_SHIFT)
+#define I2S_BRD_TCR3_WDFL(base) (I2S_RD_TCR3_WDFL(base))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_TCR3_WDFL(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_WDFL_MASK, I2S_TCR3_WDFL(value)))
+#define I2S_BWR_TCR3_WDFL(base, value) (I2S_WR_TCR3_WDFL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR3, field TCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for transmit operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0b00 - Transmit data channel N is disabled.
+ * - 0b01 - Transmit data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_TCE field. */
+#define I2S_RD_TCR3_TCE(base) ((I2S_TCR3_REG(base) & I2S_TCR3_TCE_MASK) >> I2S_TCR3_TCE_SHIFT)
+#define I2S_BRD_TCR3_TCE(base) (I2S_RD_TCR3_TCE(base))
+
+/*! @brief Set the TCE field to a new value. */
+#define I2S_WR_TCR3_TCE(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_TCE_MASK, I2S_TCR3_TCE(value)))
+#define I2S_BWR_TCR3_TCE(base, value) (I2S_WR_TCR3_TCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR4 - SAI Transmit Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR4 register
+ */
+/*@{*/
+#define I2S_RD_TCR4(base)        (I2S_TCR4_REG(base))
+#define I2S_WR_TCR4(base, value) (I2S_TCR4_REG(base) = (value))
+#define I2S_RMW_TCR4(base, mask, value) (I2S_WR_TCR4(base, (I2S_RD_TCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) |  (value)))
+#define I2S_CLR_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) & ~(value)))
+#define I2S_TOG_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is generated externally in Slave mode.
+ * - 0b1 - Frame sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSD field. */
+#define I2S_RD_TCR4_FSD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSD_MASK) >> I2S_TCR4_FSD_SHIFT)
+#define I2S_BRD_TCR4_FSD(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_TCR4_FSD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSD_MASK, I2S_TCR4_FSD(value)))
+#define I2S_BWR_TCR4_FSD(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is active high.
+ * - 0b1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSP field. */
+#define I2S_RD_TCR4_FSP(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSP_MASK) >> I2S_TCR4_FSP_SHIFT)
+#define I2S_BRD_TCR4_FSP(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_TCR4_FSP(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSP_MASK, I2S_TCR4_FSP(value)))
+#define I2S_BWR_TCR4_FSP(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Frame sync asserts with the first bit of the frame.
+ * - 0b1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSE field. */
+#define I2S_RD_TCR4_FSE(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSE_MASK) >> I2S_TCR4_FSE_SHIFT)
+#define I2S_BRD_TCR4_FSE(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_TCR4_FSE(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSE_MASK, I2S_TCR4_FSE(value)))
+#define I2S_BWR_TCR4_FSE(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is transmitted first.
+ *
+ * Values:
+ * - 0b0 - LSB is transmitted first.
+ * - 0b1 - MSB is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_MF field. */
+#define I2S_RD_TCR4_MF(base) ((I2S_TCR4_REG(base) & I2S_TCR4_MF_MASK) >> I2S_TCR4_MF_SHIFT)
+#define I2S_BRD_TCR4_MF(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_TCR4_MF(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_MF_MASK, I2S_TCR4_MF(value)))
+#define I2S_BWR_TCR4_MF(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_SYWD field. */
+#define I2S_RD_TCR4_SYWD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_SYWD_MASK) >> I2S_TCR4_SYWD_SHIFT)
+#define I2S_BRD_TCR4_SYWD(base) (I2S_RD_TCR4_SYWD(base))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_TCR4_SYWD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_SYWD_MASK, I2S_TCR4_SYWD(value)))
+#define I2S_BWR_TCR4_SYWD(base, value) (I2S_WR_TCR4_SYWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FRSZ field. */
+#define I2S_RD_TCR4_FRSZ(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FRSZ_MASK) >> I2S_TCR4_FRSZ_SHIFT)
+#define I2S_BRD_TCR4_FRSZ(base) (I2S_RD_TCR4_FRSZ(base))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_TCR4_FRSZ(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FRSZ_MASK, I2S_TCR4_FRSZ(value)))
+#define I2S_BWR_TCR4_FRSZ(base, value) (I2S_WR_TCR4_FRSZ(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR5 - SAI Transmit Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR5 register
+ */
+/*@{*/
+#define I2S_RD_TCR5(base)        (I2S_TCR5_REG(base))
+#define I2S_WR_TCR5(base, value) (I2S_TCR5_REG(base) = (value))
+#define I2S_RMW_TCR5(base, mask, value) (I2S_WR_TCR5(base, (I2S_RD_TCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) |  (value)))
+#define I2S_CLR_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) & ~(value)))
+#define I2S_TOG_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit transmitted for each word in the
+ * frame. If configured for MSB First, the index of the next bit transmitted is
+ * one less than the current bit transmitted. If configured for LSB First, the
+ * index of the next bit transmitted is one more than the current bit transmitted.
+ * The value written must be greater than or equal to the word width when
+ * configured for MSB First. The value written must be less than or equal to 31-word width
+ * when configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_FBT field. */
+#define I2S_RD_TCR5_FBT(base) ((I2S_TCR5_REG(base) & I2S_TCR5_FBT_MASK) >> I2S_TCR5_FBT_SHIFT)
+#define I2S_BRD_TCR5_FBT(base) (I2S_RD_TCR5_FBT(base))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_TCR5_FBT(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_FBT_MASK, I2S_TCR5_FBT(value)))
+#define I2S_BWR_TCR5_FBT(base, value) (I2S_WR_TCR5_FBT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_W0W field. */
+#define I2S_RD_TCR5_W0W(base) ((I2S_TCR5_REG(base) & I2S_TCR5_W0W_MASK) >> I2S_TCR5_W0W_SHIFT)
+#define I2S_BRD_TCR5_W0W(base) (I2S_RD_TCR5_W0W(base))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_TCR5_W0W(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_W0W_MASK, I2S_TCR5_W0W(value)))
+#define I2S_BWR_TCR5_W0W(base, value) (I2S_WR_TCR5_W0W(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_WNW field. */
+#define I2S_RD_TCR5_WNW(base) ((I2S_TCR5_REG(base) & I2S_TCR5_WNW_MASK) >> I2S_TCR5_WNW_SHIFT)
+#define I2S_BRD_TCR5_WNW(base) (I2S_RD_TCR5_WNW(base))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_TCR5_WNW(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_WNW_MASK, I2S_TCR5_WNW(value)))
+#define I2S_BWR_TCR5_WNW(base, value) (I2S_WR_TCR5_WNW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TDR - SAI Transmit Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TDR - SAI Transmit Data Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TDR register
+ */
+/*@{*/
+#define I2S_RD_TDR(base, index)  (I2S_TDR_REG(base, index))
+#define I2S_WR_TDR(base, index, value) (I2S_TDR_REG(base, index) = (value))
+#define I2S_RMW_TDR(base, index, mask, value) (I2S_WR_TDR(base, index, (I2S_RD_TDR(base, index) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TFR - SAI Transmit FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TFR - SAI Transmit FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TFR register
+ */
+/*@{*/
+#define I2S_RD_TFR(base, index)  (I2S_TFR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TFR bitfields
+ */
+
+/*!
+ * @name Register I2S_TFR, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for transmit data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TFR_RFP field. */
+#define I2S_RD_TFR_RFP(base, index) ((I2S_TFR_REG(base, index) & I2S_TFR_RFP_MASK) >> I2S_TFR_RFP_SHIFT)
+#define I2S_BRD_TFR_RFP(base, index) (I2S_RD_TFR_RFP(base, index))
+/*@}*/
+
+/*!
+ * @name Register I2S_TFR, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for transmit data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TFR_WFP field. */
+#define I2S_RD_TFR_WFP(base, index) ((I2S_TFR_REG(base, index) & I2S_TFR_WFP_MASK) >> I2S_TFR_WFP_SHIFT)
+#define I2S_BRD_TFR_WFP(base, index) (I2S_RD_TFR_WFP(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TMR - SAI Transmit Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TMR - SAI Transmit Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When TCSR[TE] is first set At
+ * the end of each frame. This allows the masked words in each frame to change
+ * from frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TMR register
+ */
+/*@{*/
+#define I2S_RD_TMR(base)         (I2S_TMR_REG(base))
+#define I2S_WR_TMR(base, value)  (I2S_TMR_REG(base) = (value))
+#define I2S_RMW_TMR(base, mask, value) (I2S_WR_TMR(base, (I2S_RD_TMR(base) & ~(mask)) | (value)))
+#define I2S_SET_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) |  (value)))
+#define I2S_CLR_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) & ~(value)))
+#define I2S_TOG_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCSR - SAI Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCSR - SAI Receive Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCSR register
+ */
+/*@{*/
+#define I2S_RD_RCSR(base)        (I2S_RCSR_REG(base))
+#define I2S_WR_RCSR(base, value) (I2S_RCSR_REG(base) = (value))
+#define I2S_RMW_RCSR(base, mask, value) (I2S_WR_RCSR(base, (I2S_RD_RCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) |  (value)))
+#define I2S_CLR_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) & ~(value)))
+#define I2S_TOG_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_RCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRDE field. */
+#define I2S_RD_RCSR_FRDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRDE_MASK) >> I2S_RCSR_FRDE_SHIFT)
+#define I2S_BRD_RCSR_FRDE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRDE_SHIFT))
+
+/*! @brief Set the FRDE field to a new value. */
+#define I2S_WR_RCSR_FRDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FRDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FRDE(value)))
+#define I2S_BWR_RCSR_FRDE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWDE field. */
+#define I2S_RD_RCSR_FWDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWDE_MASK) >> I2S_RCSR_FWDE_SHIFT)
+#define I2S_BRD_RCSR_FWDE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_RCSR_FWDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWDE(value)))
+#define I2S_BWR_RCSR_FWDE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRIE field. */
+#define I2S_RD_RCSR_FRIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRIE_MASK) >> I2S_RCSR_FRIE_SHIFT)
+#define I2S_BRD_RCSR_FRIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRIE_SHIFT))
+
+/*! @brief Set the FRIE field to a new value. */
+#define I2S_WR_RCSR_FRIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FRIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FRIE(value)))
+#define I2S_BWR_RCSR_FRIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWIE field. */
+#define I2S_RD_RCSR_FWIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWIE_MASK) >> I2S_RCSR_FWIE_SHIFT)
+#define I2S_BRD_RCSR_FWIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_RCSR_FWIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWIE(value)))
+#define I2S_BWR_RCSR_FWIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEIE field. */
+#define I2S_RD_RCSR_FEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEIE_MASK) >> I2S_RCSR_FEIE_SHIFT)
+#define I2S_BRD_RCSR_FEIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_RCSR_FEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEIE(value)))
+#define I2S_BWR_RCSR_FEIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEIE field. */
+#define I2S_RD_RCSR_SEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEIE_MASK) >> I2S_RCSR_SEIE_SHIFT)
+#define I2S_BRD_RCSR_SEIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_RCSR_SEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEIE(value)))
+#define I2S_BWR_RCSR_SEIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSIE field. */
+#define I2S_RD_RCSR_WSIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSIE_MASK) >> I2S_RCSR_WSIE_SHIFT)
+#define I2S_BRD_RCSR_WSIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_RCSR_WSIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_WSIE(value)))
+#define I2S_BWR_RCSR_WSIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled receive channel FIFO is
+ * greater than the receive FIFO watermark.
+ *
+ * Values:
+ * - 0b0 - Receive FIFO watermark not reached.
+ * - 0b1 - Receive FIFO watermark has been reached.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRF field. */
+#define I2S_RD_RCSR_FRF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRF_MASK) >> I2S_RCSR_FRF_SHIFT)
+#define I2S_BRD_RCSR_FRF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled receive FIFO is full.
+ *
+ * Values:
+ * - 0b0 - No enabled receive FIFO is full.
+ * - 0b1 - Enabled receive FIFO is full.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWF field. */
+#define I2S_RD_RCSR_FWF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWF_MASK) >> I2S_RCSR_FWF_SHIFT)
+#define I2S_BRD_RCSR_FWF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
+ * this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Receive overflow not detected.
+ * - 0b1 - Receive overflow detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEF field. */
+#define I2S_RD_RCSR_FEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEF_MASK) >> I2S_RCSR_FEF_SHIFT)
+#define I2S_BRD_RCSR_FEF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_RCSR_FEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEF(value)))
+#define I2S_BWR_RCSR_FEF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Sync error not detected.
+ * - 0b1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEF field. */
+#define I2S_RD_RCSR_SEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEF_MASK) >> I2S_RCSR_SEF_SHIFT)
+#define I2S_BRD_RCSR_SEF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_RCSR_SEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEF(value)))
+#define I2S_BWR_RCSR_SEF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Start of word not detected.
+ * - 0b1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSF field. */
+#define I2S_RD_RCSR_WSF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSF_MASK) >> I2S_RCSR_WSF_SHIFT)
+#define I2S_BRD_RCSR_WSF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_RCSR_WSF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK), I2S_RCSR_WSF(value)))
+#define I2S_BWR_RCSR_WSF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SR[24] (RW)
+ *
+ * Resets the internal receiver logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SR field. */
+#define I2S_RD_RCSR_SR(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SR_MASK) >> I2S_RCSR_SR_SHIFT)
+#define I2S_BRD_RCSR_SR(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_RCSR_SR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SR(value)))
+#define I2S_BWR_RCSR_SR(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the receiver is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_RCSR_FR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FR(value)))
+#define I2S_BWR_RCSR_FR(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field BCE[28] (RW)
+ *
+ * Enables the receive bit clock, separately from RE. This field is
+ * automatically set whenever RE is set. When software clears this field, the receive bit
+ * clock remains enabled, and this field remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0b0 - Receive bit clock is disabled.
+ * - 0b1 - Receive bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_BCE field. */
+#define I2S_RD_RCSR_BCE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_BCE_MASK) >> I2S_RCSR_BCE_SHIFT)
+#define I2S_BRD_RCSR_BCE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_RCSR_BCE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_BCE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_BCE(value)))
+#define I2S_BWR_RCSR_BCE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables receiver operation in Debug mode. The receive bit clock is
+ * not affected by Debug mode.
+ *
+ * Values:
+ * - 0b0 - Receiver is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 0b1 - Receiver is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_DBGE field. */
+#define I2S_RD_RCSR_DBGE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_DBGE_MASK) >> I2S_RCSR_DBGE_SHIFT)
+#define I2S_BRD_RCSR_DBGE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_RCSR_DBGE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_DBGE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_DBGE(value)))
+#define I2S_BWR_RCSR_DBGE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field STOPE[30] (RW)
+ *
+ * Configures receiver operation in Stop mode. This bit is ignored and the
+ * receiver is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0b0 - Receiver disabled in Stop mode.
+ * - 0b1 - Receiver enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_STOPE field. */
+#define I2S_RD_RCSR_STOPE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_STOPE_MASK) >> I2S_RCSR_STOPE_SHIFT)
+#define I2S_BRD_RCSR_STOPE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_RCSR_STOPE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_STOPE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_STOPE(value)))
+#define I2S_BWR_RCSR_STOPE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field RE[31] (RW)
+ *
+ * Enables/disables the receiver. When software clears this field, the receiver
+ * remains enabled, and this bit remains set, until the end of the current frame.
+ *
+ * Values:
+ * - 0b0 - Receiver is disabled.
+ * - 0b1 - Receiver is enabled, or receiver has been disabled and has not yet
+ *     reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_RE field. */
+#define I2S_RD_RCSR_RE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_RE_MASK) >> I2S_RCSR_RE_SHIFT)
+#define I2S_BRD_RCSR_RE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT))
+
+/*! @brief Set the RE field to a new value. */
+#define I2S_WR_RCSR_RE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_RE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_RE(value)))
+#define I2S_BWR_RCSR_RE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR1 - SAI Receive Configuration 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR1 register
+ */
+/*@{*/
+#define I2S_RD_RCR1(base)        (I2S_RCR1_REG(base))
+#define I2S_WR_RCR1(base, value) (I2S_RCR1_REG(base) = (value))
+#define I2S_RMW_RCR1(base, mask, value) (I2S_WR_RCR1(base, (I2S_RD_RCR1(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) |  (value)))
+#define I2S_CLR_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) & ~(value)))
+#define I2S_TOG_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR1, field RFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled receiver channels.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR1_RFW field. */
+#define I2S_RD_RCR1_RFW(base) ((I2S_RCR1_REG(base) & I2S_RCR1_RFW_MASK) >> I2S_RCR1_RFW_SHIFT)
+#define I2S_BRD_RCR1_RFW(base) (I2S_RD_RCR1_RFW(base))
+
+/*! @brief Set the RFW field to a new value. */
+#define I2S_WR_RCR1_RFW(base, value) (I2S_RMW_RCR1(base, I2S_RCR1_RFW_MASK, I2S_RCR1_RFW(value)))
+#define I2S_BWR_RCR1_RFW(base, value) (I2S_WR_RCR1_RFW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR2 - SAI Receive Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR2 register
+ */
+/*@{*/
+#define I2S_RD_RCR2(base)        (I2S_RCR2_REG(base))
+#define I2S_WR_RCR2(base, value) (I2S_RCR2_REG(base) = (value))
+#define I2S_RMW_RCR2(base, mask, value) (I2S_WR_RCR2(base, (I2S_RD_RCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) |  (value)))
+#define I2S_CLR_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) & ~(value)))
+#define I2S_TOG_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_DIV field. */
+#define I2S_RD_RCR2_DIV(base) ((I2S_RCR2_REG(base) & I2S_RCR2_DIV_MASK) >> I2S_RCR2_DIV_SHIFT)
+#define I2S_BRD_RCR2_DIV(base) (I2S_RD_RCR2_DIV(base))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_RCR2_DIV(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_DIV_MASK, I2S_RCR2_DIV(value)))
+#define I2S_BWR_RCR2_DIV(base, value) (I2S_WR_RCR2_DIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is generated externally in Slave mode.
+ * - 0b1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCD field. */
+#define I2S_RD_RCR2_BCD(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCD_MASK) >> I2S_RCR2_BCD_SHIFT)
+#define I2S_BRD_RCR2_BCD(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_RCR2_BCD(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCD_MASK, I2S_RCR2_BCD(value)))
+#define I2S_BWR_RCR2_BCD(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit Clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 0b1 - Bit Clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCP field. */
+#define I2S_RD_RCR2_BCP(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCP_MASK) >> I2S_RCR2_BCP_SHIFT)
+#define I2S_BRD_RCR2_BCP(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_RCR2_BCP(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCP_MASK, I2S_RCR2_BCP(value)))
+#define I2S_BWR_RCR2_BCP(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 0b00 - Bus Clock selected.
+ * - 0b01 - Master Clock (MCLK) 1 option selected.
+ * - 0b10 - Master Clock (MCLK) 2 option selected.
+ * - 0b11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_MSEL field. */
+#define I2S_RD_RCR2_MSEL(base) ((I2S_RCR2_REG(base) & I2S_RCR2_MSEL_MASK) >> I2S_RCR2_MSEL_SHIFT)
+#define I2S_BRD_RCR2_MSEL(base) (I2S_RD_RCR2_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_RCR2_MSEL(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_MSEL_MASK, I2S_RCR2_MSEL(value)))
+#define I2S_BWR_RCR2_MSEL(base, value) (I2S_WR_RCR2_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the receiver
+ * is delayed by the pad output delay (the receiver is clocked by the pad input
+ * as if the clock was externally generated). This has the effect of decreasing
+ * the data input setup time, but increasing the data output valid time. The slave
+ * mode timing from the datasheet should be used for the receiver when this bit
+ * is set. In synchronous mode, this bit allows the receiver to use the slave mode
+ * timing from the datasheet, while the transmitter uses the master mode timing.
+ * This field has no effect when configured for an externally generated bit
+ * clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCI field. */
+#define I2S_RD_RCR2_BCI(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCI_MASK) >> I2S_RCR2_BCI_SHIFT)
+#define I2S_BRD_RCR2_BCI(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_RCR2_BCI(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCI_MASK, I2S_RCR2_BCI(value)))
+#define I2S_BWR_RCR2_BCI(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the receiver. When the receiver is
+ * configured in asynchronous mode and this bit is set, the receiver is clocked by
+ * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the receiver continues to use the receiver
+ * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
+ * mode, the transmitter BCS field and receiver BCS field must be set to the same
+ * value. When both are set, the transmitter and receiver are both clocked by the
+ * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
+ * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
+ *
+ * Values:
+ * - 0b0 - Use the normal bit clock source.
+ * - 0b1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCS field. */
+#define I2S_RD_RCR2_BCS(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCS_MASK) >> I2S_RCR2_BCS_SHIFT)
+#define I2S_BRD_RCR2_BCS(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_RCR2_BCS(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCS_MASK, I2S_RCR2_BCS(value)))
+#define I2S_BWR_RCR2_BCS(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the transmitter or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 0b00 - Asynchronous mode.
+ * - 0b01 - Synchronous with transmitter.
+ * - 0b10 - Synchronous with another SAI receiver.
+ * - 0b11 - Synchronous with another SAI transmitter.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_SYNC field. */
+#define I2S_RD_RCR2_SYNC(base) ((I2S_RCR2_REG(base) & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT)
+#define I2S_BRD_RCR2_SYNC(base) (I2S_RD_RCR2_SYNC(base))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_RCR2_SYNC(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_SYNC_MASK, I2S_RCR2_SYNC(value)))
+#define I2S_BWR_RCR2_SYNC(base, value) (I2S_WR_RCR2_SYNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR3 - SAI Receive Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR3 register
+ */
+/*@{*/
+#define I2S_RD_RCR3(base)        (I2S_RCR3_REG(base))
+#define I2S_WR_RCR3(base, value) (I2S_RCR3_REG(base) = (value))
+#define I2S_RMW_RCR3(base, mask, value) (I2S_WR_RCR3(base, (I2S_RD_RCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) |  (value)))
+#define I2S_CLR_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) & ~(value)))
+#define I2S_TOG_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word the start of word flag is set. The value written should
+ * be one less than the word number (for example, write zero to configure for
+ * the first word in the frame). When configured to a value greater than the Frame
+ * Size field, then the start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_WDFL field. */
+#define I2S_RD_RCR3_WDFL(base) ((I2S_RCR3_REG(base) & I2S_RCR3_WDFL_MASK) >> I2S_RCR3_WDFL_SHIFT)
+#define I2S_BRD_RCR3_WDFL(base) (I2S_RD_RCR3_WDFL(base))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_RCR3_WDFL(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_WDFL_MASK, I2S_RCR3_WDFL(value)))
+#define I2S_BWR_RCR3_WDFL(base, value) (I2S_WR_RCR3_WDFL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR3, field RCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for receive operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0b00 - Receive data channel N is disabled.
+ * - 0b01 - Receive data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_RCE field. */
+#define I2S_RD_RCR3_RCE(base) ((I2S_RCR3_REG(base) & I2S_RCR3_RCE_MASK) >> I2S_RCR3_RCE_SHIFT)
+#define I2S_BRD_RCR3_RCE(base) (I2S_RD_RCR3_RCE(base))
+
+/*! @brief Set the RCE field to a new value. */
+#define I2S_WR_RCR3_RCE(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_RCE_MASK, I2S_RCR3_RCE(value)))
+#define I2S_BWR_RCR3_RCE(base, value) (I2S_WR_RCR3_RCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR4 - SAI Receive Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR4 register
+ */
+/*@{*/
+#define I2S_RD_RCR4(base)        (I2S_RCR4_REG(base))
+#define I2S_WR_RCR4(base, value) (I2S_RCR4_REG(base) = (value))
+#define I2S_RMW_RCR4(base, mask, value) (I2S_WR_RCR4(base, (I2S_RD_RCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) |  (value)))
+#define I2S_CLR_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) & ~(value)))
+#define I2S_TOG_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame Sync is generated externally in Slave mode.
+ * - 0b1 - Frame Sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSD field. */
+#define I2S_RD_RCR4_FSD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSD_MASK) >> I2S_RCR4_FSD_SHIFT)
+#define I2S_BRD_RCR4_FSD(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_RCR4_FSD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSD_MASK, I2S_RCR4_FSD(value)))
+#define I2S_BWR_RCR4_FSD(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is active high.
+ * - 0b1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSP field. */
+#define I2S_RD_RCR4_FSP(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSP_MASK) >> I2S_RCR4_FSP_SHIFT)
+#define I2S_BRD_RCR4_FSP(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_RCR4_FSP(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSP_MASK, I2S_RCR4_FSP(value)))
+#define I2S_BWR_RCR4_FSP(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Frame sync asserts with the first bit of the frame.
+ * - 0b1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSE field. */
+#define I2S_RD_RCR4_FSE(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSE_MASK) >> I2S_RCR4_FSE_SHIFT)
+#define I2S_BRD_RCR4_FSE(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_RCR4_FSE(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSE_MASK, I2S_RCR4_FSE(value)))
+#define I2S_BWR_RCR4_FSE(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is received first.
+ *
+ * Values:
+ * - 0b0 - LSB is received first.
+ * - 0b1 - MSB is received first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_MF field. */
+#define I2S_RD_RCR4_MF(base) ((I2S_RCR4_REG(base) & I2S_RCR4_MF_MASK) >> I2S_RCR4_MF_SHIFT)
+#define I2S_BRD_RCR4_MF(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_RCR4_MF(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_MF_MASK, I2S_RCR4_MF(value)))
+#define I2S_BWR_RCR4_MF(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_SYWD field. */
+#define I2S_RD_RCR4_SYWD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_SYWD_MASK) >> I2S_RCR4_SYWD_SHIFT)
+#define I2S_BRD_RCR4_SYWD(base) (I2S_RD_RCR4_SYWD(base))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_RCR4_SYWD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_SYWD_MASK, I2S_RCR4_SYWD(value)))
+#define I2S_BWR_RCR4_SYWD(base, value) (I2S_WR_RCR4_SYWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FRSZ field. */
+#define I2S_RD_RCR4_FRSZ(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FRSZ_MASK) >> I2S_RCR4_FRSZ_SHIFT)
+#define I2S_BRD_RCR4_FRSZ(base) (I2S_RD_RCR4_FRSZ(base))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_RCR4_FRSZ(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FRSZ_MASK, I2S_RCR4_FRSZ(value)))
+#define I2S_BWR_RCR4_FRSZ(base, value) (I2S_WR_RCR4_FRSZ(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR5 - SAI Receive Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR5 register
+ */
+/*@{*/
+#define I2S_RD_RCR5(base)        (I2S_RCR5_REG(base))
+#define I2S_WR_RCR5(base, value) (I2S_RCR5_REG(base) = (value))
+#define I2S_RMW_RCR5(base, mask, value) (I2S_WR_RCR5(base, (I2S_RD_RCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) |  (value)))
+#define I2S_CLR_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) & ~(value)))
+#define I2S_TOG_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit received for each word in the
+ * frame. If configured for MSB First, the index of the next bit received is one less
+ * than the current bit received. If configured for LSB First, the index of the
+ * next bit received is one more than the current bit received. The value written
+ * must be greater than or equal to the word width when configured for MSB
+ * First. The value written must be less than or equal to 31-word width when
+ * configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_FBT field. */
+#define I2S_RD_RCR5_FBT(base) ((I2S_RCR5_REG(base) & I2S_RCR5_FBT_MASK) >> I2S_RCR5_FBT_SHIFT)
+#define I2S_BRD_RCR5_FBT(base) (I2S_RD_RCR5_FBT(base))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_RCR5_FBT(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_FBT_MASK, I2S_RCR5_FBT(value)))
+#define I2S_BWR_RCR5_FBT(base, value) (I2S_WR_RCR5_FBT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_W0W field. */
+#define I2S_RD_RCR5_W0W(base) ((I2S_RCR5_REG(base) & I2S_RCR5_W0W_MASK) >> I2S_RCR5_W0W_SHIFT)
+#define I2S_BRD_RCR5_W0W(base) (I2S_RD_RCR5_W0W(base))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_RCR5_W0W(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_W0W_MASK, I2S_RCR5_W0W(value)))
+#define I2S_BWR_RCR5_W0W(base, value) (I2S_WR_RCR5_W0W(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_WNW field. */
+#define I2S_RD_RCR5_WNW(base) ((I2S_RCR5_REG(base) & I2S_RCR5_WNW_MASK) >> I2S_RCR5_WNW_SHIFT)
+#define I2S_BRD_RCR5_WNW(base) (I2S_RD_RCR5_WNW(base))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_RCR5_WNW(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_WNW_MASK, I2S_RCR5_WNW(value)))
+#define I2S_BWR_RCR5_WNW(base, value) (I2S_WR_RCR5_WNW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RDR - SAI Receive Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RDR - SAI Receive Data Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Reading this register introduces one additional peripheral clock wait state
+ * on each read.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RDR register
+ */
+/*@{*/
+#define I2S_RD_RDR(base, index)  (I2S_RDR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RFR - SAI Receive FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RFR - SAI Receive FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RFR register
+ */
+/*@{*/
+#define I2S_RD_RFR(base, index)  (I2S_RFR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RFR bitfields
+ */
+
+/*!
+ * @name Register I2S_RFR, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for receive data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RFR_RFP field. */
+#define I2S_RD_RFR_RFP(base, index) ((I2S_RFR_REG(base, index) & I2S_RFR_RFP_MASK) >> I2S_RFR_RFP_SHIFT)
+#define I2S_BRD_RFR_RFP(base, index) (I2S_RD_RFR_RFP(base, index))
+/*@}*/
+
+/*!
+ * @name Register I2S_RFR, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for receive data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RFR_WFP field. */
+#define I2S_RD_RFR_WFP(base, index) ((I2S_RFR_REG(base, index) & I2S_RFR_WFP_MASK) >> I2S_RFR_WFP_SHIFT)
+#define I2S_BRD_RFR_WFP(base, index) (I2S_RD_RFR_WFP(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RMR - SAI Receive Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RMR - SAI Receive Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When RCSR[RE] is first set At
+ * the end of each frame This allows the masked words in each frame to change from
+ * frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RMR register
+ */
+/*@{*/
+#define I2S_RD_RMR(base)         (I2S_RMR_REG(base))
+#define I2S_WR_RMR(base, value)  (I2S_RMR_REG(base) = (value))
+#define I2S_RMW_RMR(base, mask, value) (I2S_WR_RMR(base, (I2S_RD_RMR(base) & ~(mask)) | (value)))
+#define I2S_SET_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) |  (value)))
+#define I2S_CLR_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) & ~(value)))
+#define I2S_TOG_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MCR - SAI MCLK Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MCR - SAI MCLK Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Control Register (MCR) controls the clock source and direction of
+ * the audio master clock.
+ */
+/*!
+ * @name Constants and macros for entire I2S_MCR register
+ */
+/*@{*/
+#define I2S_RD_MCR(base)         (I2S_MCR_REG(base))
+#define I2S_WR_MCR(base, value)  (I2S_MCR_REG(base) = (value))
+#define I2S_RMW_MCR(base, mask, value) (I2S_WR_MCR(base, (I2S_RD_MCR(base) & ~(mask)) | (value)))
+#define I2S_SET_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) |  (value)))
+#define I2S_CLR_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) & ~(value)))
+#define I2S_TOG_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MCR bitfields
+ */
+
+/*!
+ * @name Register I2S_MCR, field MICS[25:24] (RW)
+ *
+ * Selects the clock input to the MCLK divider. This field cannot be changed
+ * while the MCLK divider is enabled. See the chip configuration details for
+ * information about the connections to these inputs.
+ *
+ * Values:
+ * - 0b00 - MCLK divider input clock 0 selected.
+ * - 0b01 - MCLK divider input clock 1 selected.
+ * - 0b10 - MCLK divider input clock 2 selected.
+ * - 0b11 - MCLK divider input clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MICS field. */
+#define I2S_RD_MCR_MICS(base) ((I2S_MCR_REG(base) & I2S_MCR_MICS_MASK) >> I2S_MCR_MICS_SHIFT)
+#define I2S_BRD_MCR_MICS(base) (I2S_RD_MCR_MICS(base))
+
+/*! @brief Set the MICS field to a new value. */
+#define I2S_WR_MCR_MICS(base, value) (I2S_RMW_MCR(base, I2S_MCR_MICS_MASK, I2S_MCR_MICS(value)))
+#define I2S_BWR_MCR_MICS(base, value) (I2S_WR_MCR_MICS(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field MOE[30] (RW)
+ *
+ * Enables the MCLK divider and configures the MCLK signal pin as an output.
+ * When software clears this field, it remains set until the MCLK divider is fully
+ * disabled.
+ *
+ * Values:
+ * - 0b0 - MCLK signal pin is configured as an input that bypasses the MCLK
+ *     divider.
+ * - 0b1 - MCLK signal pin is configured as an output from the MCLK divider and
+ *     the MCLK divider is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MOE field. */
+#define I2S_RD_MCR_MOE(base) ((I2S_MCR_REG(base) & I2S_MCR_MOE_MASK) >> I2S_MCR_MOE_SHIFT)
+#define I2S_BRD_MCR_MOE(base) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT))
+
+/*! @brief Set the MOE field to a new value. */
+#define I2S_WR_MCR_MOE(base, value) (I2S_RMW_MCR(base, I2S_MCR_MOE_MASK, I2S_MCR_MOE(value)))
+#define I2S_BWR_MCR_MOE(base, value) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field DUF[31] (RO)
+ *
+ * Provides the status of on-the-fly updates to the MCLK divider ratio.
+ *
+ * Values:
+ * - 0b0 - MCLK divider ratio is not being updated currently.
+ * - 0b1 - MCLK divider ratio is updating on-the-fly. Further updates to the
+ *     MCLK divider ratio are blocked while this flag remains set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_DUF field. */
+#define I2S_RD_MCR_DUF(base) ((I2S_MCR_REG(base) & I2S_MCR_DUF_MASK) >> I2S_MCR_DUF_SHIFT)
+#define I2S_BRD_MCR_DUF(base) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_DUF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MDR - SAI MCLK Divide Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MDR - SAI MCLK Divide Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
+ * MDR can be changed when the MCLK divider clock is enabled, additional writes
+ * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
+ * divided clock is disabled do not set MCR[DUF].
+ */
+/*!
+ * @name Constants and macros for entire I2S_MDR register
+ */
+/*@{*/
+#define I2S_RD_MDR(base)         (I2S_MDR_REG(base))
+#define I2S_WR_MDR(base, value)  (I2S_MDR_REG(base) = (value))
+#define I2S_RMW_MDR(base, mask, value) (I2S_WR_MDR(base, (I2S_RD_MDR(base) & ~(mask)) | (value)))
+#define I2S_SET_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) |  (value)))
+#define I2S_CLR_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) & ~(value)))
+#define I2S_TOG_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MDR bitfields
+ */
+
+/*!
+ * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MDR_DIVIDE field. */
+#define I2S_RD_MDR_DIVIDE(base) ((I2S_MDR_REG(base) & I2S_MDR_DIVIDE_MASK) >> I2S_MDR_DIVIDE_SHIFT)
+#define I2S_BRD_MDR_DIVIDE(base) (I2S_RD_MDR_DIVIDE(base))
+
+/*! @brief Set the DIVIDE field to a new value. */
+#define I2S_WR_MDR_DIVIDE(base, value) (I2S_RMW_MDR(base, I2S_MDR_DIVIDE_MASK, I2S_MDR_DIVIDE(value)))
+#define I2S_BWR_MDR_DIVIDE(base, value) (I2S_WR_MDR_DIVIDE(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MDR, field FRACT[19:12] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MDR_FRACT field. */
+#define I2S_RD_MDR_FRACT(base) ((I2S_MDR_REG(base) & I2S_MDR_FRACT_MASK) >> I2S_MDR_FRACT_SHIFT)
+#define I2S_BRD_MDR_FRACT(base) (I2S_RD_MDR_FRACT(base))
+
+/*! @brief Set the FRACT field to a new value. */
+#define I2S_WR_MDR_FRACT(base, value) (I2S_RMW_MDR(base, I2S_MDR_FRACT_MASK, I2S_MDR_FRACT(value)))
+#define I2S_BWR_MDR_FRACT(base, value) (I2S_WR_MDR_FRACT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 LLWU
+ *
+ * Low leakage wakeup unit
+ *
+ * Registers defined in this header file:
+ * - LLWU_PE1 - LLWU Pin Enable 1 register
+ * - LLWU_PE2 - LLWU Pin Enable 2 register
+ * - LLWU_PE3 - LLWU Pin Enable 3 register
+ * - LLWU_PE4 - LLWU Pin Enable 4 register
+ * - LLWU_ME - LLWU Module Enable register
+ * - LLWU_F1 - LLWU Flag 1 register
+ * - LLWU_F2 - LLWU Flag 2 register
+ * - LLWU_F3 - LLWU Flag 3 register
+ * - LLWU_FILT1 - LLWU Pin Filter 1 register
+ * - LLWU_FILT2 - LLWU Pin Filter 2 register
+ * - LLWU_RST - LLWU Reset Enable register
+ */
+
+#define LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
+#define LLWU_IDX (0U) /*!< Instance number for LLWU. */
+
+/*******************************************************************************
+ * LLWU_PE1 - LLWU Pin Enable 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE1 - LLWU Pin Enable 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE1 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE1 register
+ */
+/*@{*/
+#define LLWU_RD_PE1(base)        (LLWU_PE1_REG(base))
+#define LLWU_WR_PE1(base, value) (LLWU_PE1_REG(base) = (value))
+#define LLWU_RMW_PE1(base, mask, value) (LLWU_WR_PE1(base, (LLWU_RD_PE1(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) |  (value)))
+#define LLWU_CLR_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) & ~(value)))
+#define LLWU_TOG_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
+#define LLWU_RD_PE1_WUPE0(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE0_MASK) >> LLWU_PE1_WUPE0_SHIFT)
+#define LLWU_BRD_PE1_WUPE0(base) (LLWU_RD_PE1_WUPE0(base))
+
+/*! @brief Set the WUPE0 field to a new value. */
+#define LLWU_WR_PE1_WUPE0(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE0_MASK, LLWU_PE1_WUPE0(value)))
+#define LLWU_BWR_PE1_WUPE0(base, value) (LLWU_WR_PE1_WUPE0(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
+#define LLWU_RD_PE1_WUPE1(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE1_MASK) >> LLWU_PE1_WUPE1_SHIFT)
+#define LLWU_BRD_PE1_WUPE1(base) (LLWU_RD_PE1_WUPE1(base))
+
+/*! @brief Set the WUPE1 field to a new value. */
+#define LLWU_WR_PE1_WUPE1(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE1_MASK, LLWU_PE1_WUPE1(value)))
+#define LLWU_BWR_PE1_WUPE1(base, value) (LLWU_WR_PE1_WUPE1(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
+#define LLWU_RD_PE1_WUPE2(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE2_MASK) >> LLWU_PE1_WUPE2_SHIFT)
+#define LLWU_BRD_PE1_WUPE2(base) (LLWU_RD_PE1_WUPE2(base))
+
+/*! @brief Set the WUPE2 field to a new value. */
+#define LLWU_WR_PE1_WUPE2(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE2_MASK, LLWU_PE1_WUPE2(value)))
+#define LLWU_BWR_PE1_WUPE2(base, value) (LLWU_WR_PE1_WUPE2(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
+#define LLWU_RD_PE1_WUPE3(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE3_MASK) >> LLWU_PE1_WUPE3_SHIFT)
+#define LLWU_BRD_PE1_WUPE3(base) (LLWU_RD_PE1_WUPE3(base))
+
+/*! @brief Set the WUPE3 field to a new value. */
+#define LLWU_WR_PE1_WUPE3(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE3_MASK, LLWU_PE1_WUPE3(value)))
+#define LLWU_BWR_PE1_WUPE3(base, value) (LLWU_WR_PE1_WUPE3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE2 - LLWU Pin Enable 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE2 - LLWU Pin Enable 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE2 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE2 register
+ */
+/*@{*/
+#define LLWU_RD_PE2(base)        (LLWU_PE2_REG(base))
+#define LLWU_WR_PE2(base, value) (LLWU_PE2_REG(base) = (value))
+#define LLWU_RMW_PE2(base, mask, value) (LLWU_WR_PE2(base, (LLWU_RD_PE2(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) |  (value)))
+#define LLWU_CLR_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) & ~(value)))
+#define LLWU_TOG_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
+#define LLWU_RD_PE2_WUPE4(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE4_MASK) >> LLWU_PE2_WUPE4_SHIFT)
+#define LLWU_BRD_PE2_WUPE4(base) (LLWU_RD_PE2_WUPE4(base))
+
+/*! @brief Set the WUPE4 field to a new value. */
+#define LLWU_WR_PE2_WUPE4(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE4_MASK, LLWU_PE2_WUPE4(value)))
+#define LLWU_BWR_PE2_WUPE4(base, value) (LLWU_WR_PE2_WUPE4(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
+#define LLWU_RD_PE2_WUPE5(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE5_MASK) >> LLWU_PE2_WUPE5_SHIFT)
+#define LLWU_BRD_PE2_WUPE5(base) (LLWU_RD_PE2_WUPE5(base))
+
+/*! @brief Set the WUPE5 field to a new value. */
+#define LLWU_WR_PE2_WUPE5(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE5_MASK, LLWU_PE2_WUPE5(value)))
+#define LLWU_BWR_PE2_WUPE5(base, value) (LLWU_WR_PE2_WUPE5(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
+#define LLWU_RD_PE2_WUPE6(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE6_MASK) >> LLWU_PE2_WUPE6_SHIFT)
+#define LLWU_BRD_PE2_WUPE6(base) (LLWU_RD_PE2_WUPE6(base))
+
+/*! @brief Set the WUPE6 field to a new value. */
+#define LLWU_WR_PE2_WUPE6(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE6_MASK, LLWU_PE2_WUPE6(value)))
+#define LLWU_BWR_PE2_WUPE6(base, value) (LLWU_WR_PE2_WUPE6(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
+#define LLWU_RD_PE2_WUPE7(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE7_MASK) >> LLWU_PE2_WUPE7_SHIFT)
+#define LLWU_BRD_PE2_WUPE7(base) (LLWU_RD_PE2_WUPE7(base))
+
+/*! @brief Set the WUPE7 field to a new value. */
+#define LLWU_WR_PE2_WUPE7(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE7_MASK, LLWU_PE2_WUPE7(value)))
+#define LLWU_BWR_PE2_WUPE7(base, value) (LLWU_WR_PE2_WUPE7(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE3 - LLWU Pin Enable 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE3 - LLWU Pin Enable 3 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE3 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE3 register
+ */
+/*@{*/
+#define LLWU_RD_PE3(base)        (LLWU_PE3_REG(base))
+#define LLWU_WR_PE3(base, value) (LLWU_PE3_REG(base) = (value))
+#define LLWU_RMW_PE3(base, mask, value) (LLWU_WR_PE3(base, (LLWU_RD_PE3(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) |  (value)))
+#define LLWU_CLR_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) & ~(value)))
+#define LLWU_TOG_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
+#define LLWU_RD_PE3_WUPE8(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE8_MASK) >> LLWU_PE3_WUPE8_SHIFT)
+#define LLWU_BRD_PE3_WUPE8(base) (LLWU_RD_PE3_WUPE8(base))
+
+/*! @brief Set the WUPE8 field to a new value. */
+#define LLWU_WR_PE3_WUPE8(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE8_MASK, LLWU_PE3_WUPE8(value)))
+#define LLWU_BWR_PE3_WUPE8(base, value) (LLWU_WR_PE3_WUPE8(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
+#define LLWU_RD_PE3_WUPE9(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE9_MASK) >> LLWU_PE3_WUPE9_SHIFT)
+#define LLWU_BRD_PE3_WUPE9(base) (LLWU_RD_PE3_WUPE9(base))
+
+/*! @brief Set the WUPE9 field to a new value. */
+#define LLWU_WR_PE3_WUPE9(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE9_MASK, LLWU_PE3_WUPE9(value)))
+#define LLWU_BWR_PE3_WUPE9(base, value) (LLWU_WR_PE3_WUPE9(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
+#define LLWU_RD_PE3_WUPE10(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE10_MASK) >> LLWU_PE3_WUPE10_SHIFT)
+#define LLWU_BRD_PE3_WUPE10(base) (LLWU_RD_PE3_WUPE10(base))
+
+/*! @brief Set the WUPE10 field to a new value. */
+#define LLWU_WR_PE3_WUPE10(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE10_MASK, LLWU_PE3_WUPE10(value)))
+#define LLWU_BWR_PE3_WUPE10(base, value) (LLWU_WR_PE3_WUPE10(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
+#define LLWU_RD_PE3_WUPE11(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE11_MASK) >> LLWU_PE3_WUPE11_SHIFT)
+#define LLWU_BRD_PE3_WUPE11(base) (LLWU_RD_PE3_WUPE11(base))
+
+/*! @brief Set the WUPE11 field to a new value. */
+#define LLWU_WR_PE3_WUPE11(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE11_MASK, LLWU_PE3_WUPE11(value)))
+#define LLWU_BWR_PE3_WUPE11(base, value) (LLWU_WR_PE3_WUPE11(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE4 - LLWU Pin Enable 4 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE4 - LLWU Pin Enable 4 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE4 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE4 register
+ */
+/*@{*/
+#define LLWU_RD_PE4(base)        (LLWU_PE4_REG(base))
+#define LLWU_WR_PE4(base, value) (LLWU_PE4_REG(base) = (value))
+#define LLWU_RMW_PE4(base, mask, value) (LLWU_WR_PE4(base, (LLWU_RD_PE4(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) |  (value)))
+#define LLWU_CLR_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) & ~(value)))
+#define LLWU_TOG_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE4 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
+#define LLWU_RD_PE4_WUPE12(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE12_MASK) >> LLWU_PE4_WUPE12_SHIFT)
+#define LLWU_BRD_PE4_WUPE12(base) (LLWU_RD_PE4_WUPE12(base))
+
+/*! @brief Set the WUPE12 field to a new value. */
+#define LLWU_WR_PE4_WUPE12(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE12_MASK, LLWU_PE4_WUPE12(value)))
+#define LLWU_BWR_PE4_WUPE12(base, value) (LLWU_WR_PE4_WUPE12(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
+#define LLWU_RD_PE4_WUPE13(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE13_MASK) >> LLWU_PE4_WUPE13_SHIFT)
+#define LLWU_BRD_PE4_WUPE13(base) (LLWU_RD_PE4_WUPE13(base))
+
+/*! @brief Set the WUPE13 field to a new value. */
+#define LLWU_WR_PE4_WUPE13(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE13_MASK, LLWU_PE4_WUPE13(value)))
+#define LLWU_BWR_PE4_WUPE13(base, value) (LLWU_WR_PE4_WUPE13(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
+#define LLWU_RD_PE4_WUPE14(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE14_MASK) >> LLWU_PE4_WUPE14_SHIFT)
+#define LLWU_BRD_PE4_WUPE14(base) (LLWU_RD_PE4_WUPE14(base))
+
+/*! @brief Set the WUPE14 field to a new value. */
+#define LLWU_WR_PE4_WUPE14(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE14_MASK, LLWU_PE4_WUPE14(value)))
+#define LLWU_BWR_PE4_WUPE14(base, value) (LLWU_WR_PE4_WUPE14(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
+#define LLWU_RD_PE4_WUPE15(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE15_MASK) >> LLWU_PE4_WUPE15_SHIFT)
+#define LLWU_BRD_PE4_WUPE15(base) (LLWU_RD_PE4_WUPE15(base))
+
+/*! @brief Set the WUPE15 field to a new value. */
+#define LLWU_WR_PE4_WUPE15(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE15_MASK, LLWU_PE4_WUPE15(value)))
+#define LLWU_BWR_PE4_WUPE15(base, value) (LLWU_WR_PE4_WUPE15(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_ME - LLWU Module Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_ME - LLWU Module Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_ME contains the bits to enable the internal module flag as a wakeup
+ * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
+ * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
+ * reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
+ * RCM implements many of the reset functions for the chip. See the chip's reset
+ * chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_ME register
+ */
+/*@{*/
+#define LLWU_RD_ME(base)         (LLWU_ME_REG(base))
+#define LLWU_WR_ME(base, value)  (LLWU_ME_REG(base) = (value))
+#define LLWU_RMW_ME(base, mask, value) (LLWU_WR_ME(base, (LLWU_RD_ME(base) & ~(mask)) | (value)))
+#define LLWU_SET_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) |  (value)))
+#define LLWU_CLR_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) & ~(value)))
+#define LLWU_TOG_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_ME bitfields
+ */
+
+/*!
+ * @name Register LLWU_ME, field WUME0[0] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME0 field. */
+#define LLWU_RD_ME_WUME0(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME0_MASK) >> LLWU_ME_WUME0_SHIFT)
+#define LLWU_BRD_ME_WUME0(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT))
+
+/*! @brief Set the WUME0 field to a new value. */
+#define LLWU_WR_ME_WUME0(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME0_MASK, LLWU_ME_WUME0(value)))
+#define LLWU_BWR_ME_WUME0(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME1[1] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME1 field. */
+#define LLWU_RD_ME_WUME1(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME1_MASK) >> LLWU_ME_WUME1_SHIFT)
+#define LLWU_BRD_ME_WUME1(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT))
+
+/*! @brief Set the WUME1 field to a new value. */
+#define LLWU_WR_ME_WUME1(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME1_MASK, LLWU_ME_WUME1(value)))
+#define LLWU_BWR_ME_WUME1(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME2[2] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME2 field. */
+#define LLWU_RD_ME_WUME2(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME2_MASK) >> LLWU_ME_WUME2_SHIFT)
+#define LLWU_BRD_ME_WUME2(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT))
+
+/*! @brief Set the WUME2 field to a new value. */
+#define LLWU_WR_ME_WUME2(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME2_MASK, LLWU_ME_WUME2(value)))
+#define LLWU_BWR_ME_WUME2(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME3[3] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME3 field. */
+#define LLWU_RD_ME_WUME3(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME3_MASK) >> LLWU_ME_WUME3_SHIFT)
+#define LLWU_BRD_ME_WUME3(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT))
+
+/*! @brief Set the WUME3 field to a new value. */
+#define LLWU_WR_ME_WUME3(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME3_MASK, LLWU_ME_WUME3(value)))
+#define LLWU_BWR_ME_WUME3(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME4[4] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME4 field. */
+#define LLWU_RD_ME_WUME4(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME4_MASK) >> LLWU_ME_WUME4_SHIFT)
+#define LLWU_BRD_ME_WUME4(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT))
+
+/*! @brief Set the WUME4 field to a new value. */
+#define LLWU_WR_ME_WUME4(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME4_MASK, LLWU_ME_WUME4(value)))
+#define LLWU_BWR_ME_WUME4(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME5[5] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME5 field. */
+#define LLWU_RD_ME_WUME5(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME5_MASK) >> LLWU_ME_WUME5_SHIFT)
+#define LLWU_BRD_ME_WUME5(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT))
+
+/*! @brief Set the WUME5 field to a new value. */
+#define LLWU_WR_ME_WUME5(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME5_MASK, LLWU_ME_WUME5(value)))
+#define LLWU_BWR_ME_WUME5(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME6[6] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME6 field. */
+#define LLWU_RD_ME_WUME6(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME6_MASK) >> LLWU_ME_WUME6_SHIFT)
+#define LLWU_BRD_ME_WUME6(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT))
+
+/*! @brief Set the WUME6 field to a new value. */
+#define LLWU_WR_ME_WUME6(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME6_MASK, LLWU_ME_WUME6(value)))
+#define LLWU_BWR_ME_WUME6(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME7[7] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME7 field. */
+#define LLWU_RD_ME_WUME7(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME7_MASK) >> LLWU_ME_WUME7_SHIFT)
+#define LLWU_BRD_ME_WUME7(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT))
+
+/*! @brief Set the WUME7 field to a new value. */
+#define LLWU_WR_ME_WUME7(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME7_MASK, LLWU_ME_WUME7(value)))
+#define LLWU_BWR_ME_WUME7(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F1 - LLWU Flag 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F1 - LLWU Flag 1 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F1 register
+ */
+/*@{*/
+#define LLWU_RD_F1(base)         (LLWU_F1_REG(base))
+#define LLWU_WR_F1(base, value)  (LLWU_F1_REG(base) = (value))
+#define LLWU_RMW_F1(base, mask, value) (LLWU_WR_F1(base, (LLWU_RD_F1(base) & ~(mask)) | (value)))
+#define LLWU_SET_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) |  (value)))
+#define LLWU_CLR_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) & ~(value)))
+#define LLWU_TOG_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F1, field WUF0[0] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF0.
+ *
+ * Values:
+ * - 0b0 - LLWU_P0 input was not a wakeup source
+ * - 0b1 - LLWU_P0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF0 field. */
+#define LLWU_RD_F1_WUF0(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF0_MASK) >> LLWU_F1_WUF0_SHIFT)
+#define LLWU_BRD_F1_WUF0(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT))
+
+/*! @brief Set the WUF0 field to a new value. */
+#define LLWU_WR_F1_WUF0(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF0(value)))
+#define LLWU_BWR_F1_WUF0(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF1[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF1.
+ *
+ * Values:
+ * - 0b0 - LLWU_P1 input was not a wakeup source
+ * - 0b1 - LLWU_P1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF1 field. */
+#define LLWU_RD_F1_WUF1(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF1_MASK) >> LLWU_F1_WUF1_SHIFT)
+#define LLWU_BRD_F1_WUF1(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT))
+
+/*! @brief Set the WUF1 field to a new value. */
+#define LLWU_WR_F1_WUF1(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF1_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF1(value)))
+#define LLWU_BWR_F1_WUF1(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF2[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF2.
+ *
+ * Values:
+ * - 0b0 - LLWU_P2 input was not a wakeup source
+ * - 0b1 - LLWU_P2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF2 field. */
+#define LLWU_RD_F1_WUF2(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF2_MASK) >> LLWU_F1_WUF2_SHIFT)
+#define LLWU_BRD_F1_WUF2(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT))
+
+/*! @brief Set the WUF2 field to a new value. */
+#define LLWU_WR_F1_WUF2(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF2_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF2(value)))
+#define LLWU_BWR_F1_WUF2(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF3[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF3.
+ *
+ * Values:
+ * - 0b0 - LLWU_P3 input was not a wake-up source
+ * - 0b1 - LLWU_P3 input was a wake-up source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF3 field. */
+#define LLWU_RD_F1_WUF3(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF3_MASK) >> LLWU_F1_WUF3_SHIFT)
+#define LLWU_BRD_F1_WUF3(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT))
+
+/*! @brief Set the WUF3 field to a new value. */
+#define LLWU_WR_F1_WUF3(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF3_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF3(value)))
+#define LLWU_BWR_F1_WUF3(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF4[4] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF4.
+ *
+ * Values:
+ * - 0b0 - LLWU_P4 input was not a wakeup source
+ * - 0b1 - LLWU_P4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF4 field. */
+#define LLWU_RD_F1_WUF4(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF4_MASK) >> LLWU_F1_WUF4_SHIFT)
+#define LLWU_BRD_F1_WUF4(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT))
+
+/*! @brief Set the WUF4 field to a new value. */
+#define LLWU_WR_F1_WUF4(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF4_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF4(value)))
+#define LLWU_BWR_F1_WUF4(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF5[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF5.
+ *
+ * Values:
+ * - 0b0 - LLWU_P5 input was not a wakeup source
+ * - 0b1 - LLWU_P5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF5 field. */
+#define LLWU_RD_F1_WUF5(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF5_MASK) >> LLWU_F1_WUF5_SHIFT)
+#define LLWU_BRD_F1_WUF5(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT))
+
+/*! @brief Set the WUF5 field to a new value. */
+#define LLWU_WR_F1_WUF5(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF5_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF5(value)))
+#define LLWU_BWR_F1_WUF5(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF6[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF6.
+ *
+ * Values:
+ * - 0b0 - LLWU_P6 input was not a wakeup source
+ * - 0b1 - LLWU_P6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF6 field. */
+#define LLWU_RD_F1_WUF6(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF6_MASK) >> LLWU_F1_WUF6_SHIFT)
+#define LLWU_BRD_F1_WUF6(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT))
+
+/*! @brief Set the WUF6 field to a new value. */
+#define LLWU_WR_F1_WUF6(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF6_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF6(value)))
+#define LLWU_BWR_F1_WUF6(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF7[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF7.
+ *
+ * Values:
+ * - 0b0 - LLWU_P7 input was not a wakeup source
+ * - 0b1 - LLWU_P7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF7 field. */
+#define LLWU_RD_F1_WUF7(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF7_MASK) >> LLWU_F1_WUF7_SHIFT)
+#define LLWU_BRD_F1_WUF7(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT))
+
+/*! @brief Set the WUF7 field to a new value. */
+#define LLWU_WR_F1_WUF7(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF7_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK), LLWU_F1_WUF7(value)))
+#define LLWU_BWR_F1_WUF7(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F2 - LLWU Flag 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F2 - LLWU Flag 2 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F2 register
+ */
+/*@{*/
+#define LLWU_RD_F2(base)         (LLWU_F2_REG(base))
+#define LLWU_WR_F2(base, value)  (LLWU_F2_REG(base) = (value))
+#define LLWU_RMW_F2(base, mask, value) (LLWU_WR_F2(base, (LLWU_RD_F2(base) & ~(mask)) | (value)))
+#define LLWU_SET_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) |  (value)))
+#define LLWU_CLR_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) & ~(value)))
+#define LLWU_TOG_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F2, field WUF8[0] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF8.
+ *
+ * Values:
+ * - 0b0 - LLWU_P8 input was not a wakeup source
+ * - 0b1 - LLWU_P8 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF8 field. */
+#define LLWU_RD_F2_WUF8(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF8_MASK) >> LLWU_F2_WUF8_SHIFT)
+#define LLWU_BRD_F2_WUF8(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT))
+
+/*! @brief Set the WUF8 field to a new value. */
+#define LLWU_WR_F2_WUF8(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF8(value)))
+#define LLWU_BWR_F2_WUF8(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF9[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF9.
+ *
+ * Values:
+ * - 0b0 - LLWU_P9 input was not a wakeup source
+ * - 0b1 - LLWU_P9 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF9 field. */
+#define LLWU_RD_F2_WUF9(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF9_MASK) >> LLWU_F2_WUF9_SHIFT)
+#define LLWU_BRD_F2_WUF9(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT))
+
+/*! @brief Set the WUF9 field to a new value. */
+#define LLWU_WR_F2_WUF9(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF9_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF9(value)))
+#define LLWU_BWR_F2_WUF9(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF10[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF10.
+ *
+ * Values:
+ * - 0b0 - LLWU_P10 input was not a wakeup source
+ * - 0b1 - LLWU_P10 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF10 field. */
+#define LLWU_RD_F2_WUF10(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF10_MASK) >> LLWU_F2_WUF10_SHIFT)
+#define LLWU_BRD_F2_WUF10(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT))
+
+/*! @brief Set the WUF10 field to a new value. */
+#define LLWU_WR_F2_WUF10(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF10_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF10(value)))
+#define LLWU_BWR_F2_WUF10(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF11[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF11.
+ *
+ * Values:
+ * - 0b0 - LLWU_P11 input was not a wakeup source
+ * - 0b1 - LLWU_P11 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF11 field. */
+#define LLWU_RD_F2_WUF11(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF11_MASK) >> LLWU_F2_WUF11_SHIFT)
+#define LLWU_BRD_F2_WUF11(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT))
+
+/*! @brief Set the WUF11 field to a new value. */
+#define LLWU_WR_F2_WUF11(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF11_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF11(value)))
+#define LLWU_BWR_F2_WUF11(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF12[4] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF12.
+ *
+ * Values:
+ * - 0b0 - LLWU_P12 input was not a wakeup source
+ * - 0b1 - LLWU_P12 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF12 field. */
+#define LLWU_RD_F2_WUF12(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF12_MASK) >> LLWU_F2_WUF12_SHIFT)
+#define LLWU_BRD_F2_WUF12(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT))
+
+/*! @brief Set the WUF12 field to a new value. */
+#define LLWU_WR_F2_WUF12(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF12_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF12(value)))
+#define LLWU_BWR_F2_WUF12(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF13[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF13.
+ *
+ * Values:
+ * - 0b0 - LLWU_P13 input was not a wakeup source
+ * - 0b1 - LLWU_P13 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF13 field. */
+#define LLWU_RD_F2_WUF13(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF13_MASK) >> LLWU_F2_WUF13_SHIFT)
+#define LLWU_BRD_F2_WUF13(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT))
+
+/*! @brief Set the WUF13 field to a new value. */
+#define LLWU_WR_F2_WUF13(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF13_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF13(value)))
+#define LLWU_BWR_F2_WUF13(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF14[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF14.
+ *
+ * Values:
+ * - 0b0 - LLWU_P14 input was not a wakeup source
+ * - 0b1 - LLWU_P14 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF14 field. */
+#define LLWU_RD_F2_WUF14(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF14_MASK) >> LLWU_F2_WUF14_SHIFT)
+#define LLWU_BRD_F2_WUF14(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT))
+
+/*! @brief Set the WUF14 field to a new value. */
+#define LLWU_WR_F2_WUF14(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF14_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF14(value)))
+#define LLWU_BWR_F2_WUF14(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF15[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF15.
+ *
+ * Values:
+ * - 0b0 - LLWU_P15 input was not a wakeup source
+ * - 0b1 - LLWU_P15 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF15 field. */
+#define LLWU_RD_F2_WUF15(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF15_MASK) >> LLWU_F2_WUF15_SHIFT)
+#define LLWU_BRD_F2_WUF15(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT))
+
+/*! @brief Set the WUF15 field to a new value. */
+#define LLWU_WR_F2_WUF15(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF15_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK), LLWU_F2_WUF15(value)))
+#define LLWU_BWR_F2_WUF15(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F3 - LLWU Flag 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F3 - LLWU Flag 3 register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
+ * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
+ * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
+ * For internal peripherals that are capable of running in a low-leakage power
+ * mode, such as a real time clock module or CMP module, the flag from the
+ * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
+ * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
+ * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
+ * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
+ * the IntroductionInformation found here describes the registers of the Reset
+ * Control Module (RCM). The RCM implements many of the reset functions for the
+ * chip. See the chip's reset chapter for more information. details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F3 register
+ */
+/*@{*/
+#define LLWU_RD_F3(base)         (LLWU_F3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F3, field MWUF0[0] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 0 input was not a wakeup source
+ * - 0b1 - Module 0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF0 field. */
+#define LLWU_RD_F3_MWUF0(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF0_MASK) >> LLWU_F3_MWUF0_SHIFT)
+#define LLWU_BRD_F3_MWUF0(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF1[1] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 1 input was not a wakeup source
+ * - 0b1 - Module 1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF1 field. */
+#define LLWU_RD_F3_MWUF1(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF1_MASK) >> LLWU_F3_MWUF1_SHIFT)
+#define LLWU_BRD_F3_MWUF1(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF2[2] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 2 input was not a wakeup source
+ * - 0b1 - Module 2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF2 field. */
+#define LLWU_RD_F3_MWUF2(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF2_MASK) >> LLWU_F3_MWUF2_SHIFT)
+#define LLWU_BRD_F3_MWUF2(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF2_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF3[3] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 3 input was not a wakeup source
+ * - 0b1 - Module 3 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF3 field. */
+#define LLWU_RD_F3_MWUF3(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF3_MASK) >> LLWU_F3_MWUF3_SHIFT)
+#define LLWU_BRD_F3_MWUF3(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF3_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF4[4] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 4 input was not a wakeup source
+ * - 0b1 - Module 4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF4 field. */
+#define LLWU_RD_F3_MWUF4(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF4_MASK) >> LLWU_F3_MWUF4_SHIFT)
+#define LLWU_BRD_F3_MWUF4(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF4_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF5[5] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 5 input was not a wakeup source
+ * - 0b1 - Module 5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF5 field. */
+#define LLWU_RD_F3_MWUF5(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF5_MASK) >> LLWU_F3_MWUF5_SHIFT)
+#define LLWU_BRD_F3_MWUF5(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF5_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF6[6] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 6 input was not a wakeup source
+ * - 0b1 - Module 6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF6 field. */
+#define LLWU_RD_F3_MWUF6(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF6_MASK) >> LLWU_F3_MWUF6_SHIFT)
+#define LLWU_BRD_F3_MWUF6(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF6_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF7[7] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 7 input was not a wakeup source
+ * - 0b1 - Module 7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF7 field. */
+#define LLWU_RD_F3_MWUF7(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF7_MASK) >> LLWU_F3_MWUF7_SHIFT)
+#define LLWU_BRD_F3_MWUF7(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF7_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT1 - LLWU Pin Filter 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT1 is a control and status register that is used to enable/disable
+ * the digital filter 1 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT1 register
+ */
+/*@{*/
+#define LLWU_RD_FILT1(base)      (LLWU_FILT1_REG(base))
+#define LLWU_WR_FILT1(base, value) (LLWU_FILT1_REG(base) = (value))
+#define LLWU_RMW_FILT1(base, mask, value) (LLWU_WR_FILT1(base, (LLWU_RD_FILT1(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) |  (value)))
+#define LLWU_CLR_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) & ~(value)))
+#define LLWU_TOG_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0b0000 - Select LLWU_P0 for filter
+ * - 0b1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
+#define LLWU_RD_FILT1_FILTSEL(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTSEL_MASK) >> LLWU_FILT1_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT1_FILTSEL(base) (LLWU_RD_FILT1_FILTSEL(base))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT1_FILTSEL(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTSEL(value)))
+#define LLWU_BWR_FILT1_FILTSEL(base, value) (LLWU_WR_FILT1_FILTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 0b00 - Filter disabled
+ * - 0b01 - Filter posedge detect enabled
+ * - 0b10 - Filter negedge detect enabled
+ * - 0b11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTE field. */
+#define LLWU_RD_FILT1_FILTE(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTE_MASK) >> LLWU_FILT1_FILTE_SHIFT)
+#define LLWU_BRD_FILT1_FILTE(base) (LLWU_RD_FILT1_FILTE(base))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT1_FILTE(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTE_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTE(value)))
+#define LLWU_BWR_FILT1_FILTE(base, value) (LLWU_WR_FILT1_FILTE(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0b0 - Pin Filter 1 was not a wakeup source
+ * - 0b1 - Pin Filter 1 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTF field. */
+#define LLWU_RD_FILT1_FILTF(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTF_MASK) >> LLWU_FILT1_FILTF_SHIFT)
+#define LLWU_BRD_FILT1_FILTF(base) (BITBAND_ACCESS8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT1_FILTF(base, value) (LLWU_RMW_FILT1(base, LLWU_FILT1_FILTF_MASK, LLWU_FILT1_FILTF(value)))
+#define LLWU_BWR_FILT1_FILTF(base, value) (BITBAND_ACCESS8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT2 - LLWU Pin Filter 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT2 is a control and status register that is used to enable/disable
+ * the digital filter 2 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT2 register
+ */
+/*@{*/
+#define LLWU_RD_FILT2(base)      (LLWU_FILT2_REG(base))
+#define LLWU_WR_FILT2(base, value) (LLWU_FILT2_REG(base) = (value))
+#define LLWU_RMW_FILT2(base, mask, value) (LLWU_WR_FILT2(base, (LLWU_RD_FILT2(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) |  (value)))
+#define LLWU_CLR_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) & ~(value)))
+#define LLWU_TOG_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0b0000 - Select LLWU_P0 for filter
+ * - 0b1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
+#define LLWU_RD_FILT2_FILTSEL(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTSEL_MASK) >> LLWU_FILT2_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT2_FILTSEL(base) (LLWU_RD_FILT2_FILTSEL(base))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT2_FILTSEL(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTSEL_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTSEL(value)))
+#define LLWU_BWR_FILT2_FILTSEL(base, value) (LLWU_WR_FILT2_FILTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 0b00 - Filter disabled
+ * - 0b01 - Filter posedge detect enabled
+ * - 0b10 - Filter negedge detect enabled
+ * - 0b11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTE field. */
+#define LLWU_RD_FILT2_FILTE(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTE_MASK) >> LLWU_FILT2_FILTE_SHIFT)
+#define LLWU_BRD_FILT2_FILTE(base) (LLWU_RD_FILT2_FILTE(base))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT2_FILTE(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTE_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTE(value)))
+#define LLWU_BWR_FILT2_FILTE(base, value) (LLWU_WR_FILT2_FILTE(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0b0 - Pin Filter 2 was not a wakeup source
+ * - 0b1 - Pin Filter 2 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTF field. */
+#define LLWU_RD_FILT2_FILTF(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTF_MASK) >> LLWU_FILT2_FILTF_SHIFT)
+#define LLWU_BRD_FILT2_FILTF(base) (BITBAND_ACCESS8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT2_FILTF(base, value) (LLWU_RMW_FILT2(base, LLWU_FILT2_FILTF_MASK, LLWU_FILT2_FILTF(value)))
+#define LLWU_BWR_FILT2_FILTF(base, value) (BITBAND_ACCESS8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_RST - LLWU Reset Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_RST - LLWU Reset Enable register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * LLWU_RST is a control register that is used to enable/disable the digital
+ * filter for the external pin detect and RESET pin. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_RST register
+ */
+/*@{*/
+#define LLWU_RD_RST(base)        (LLWU_RST_REG(base))
+#define LLWU_WR_RST(base, value) (LLWU_RST_REG(base) = (value))
+#define LLWU_RMW_RST(base, mask, value) (LLWU_WR_RST(base, (LLWU_RD_RST(base) & ~(mask)) | (value)))
+#define LLWU_SET_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) |  (value)))
+#define LLWU_CLR_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) & ~(value)))
+#define LLWU_TOG_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_RST bitfields
+ */
+
+/*!
+ * @name Register LLWU_RST, field RSTFILT[0] (RW)
+ *
+ * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
+ * VLLS1 modes.
+ *
+ * Values:
+ * - 0b0 - Filter not enabled
+ * - 0b1 - Filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_RST_RSTFILT field. */
+#define LLWU_RD_RST_RSTFILT(base) ((LLWU_RST_REG(base) & LLWU_RST_RSTFILT_MASK) >> LLWU_RST_RSTFILT_SHIFT)
+#define LLWU_BRD_RST_RSTFILT(base) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_RSTFILT_SHIFT))
+
+/*! @brief Set the RSTFILT field to a new value. */
+#define LLWU_WR_RST_RSTFILT(base, value) (LLWU_RMW_RST(base, LLWU_RST_RSTFILT_MASK, LLWU_RST_RSTFILT(value)))
+#define LLWU_BWR_RST_RSTFILT(base, value) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_RSTFILT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_RST, field LLRSTE[1] (RW)
+ *
+ * This bit must be set to allow the device to be reset while in a low-leakage
+ * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
+ * also be enabled in the explicit port mux control.
+ *
+ * Values:
+ * - 0b0 - RESET pin not enabled as a leakage mode exit source
+ * - 0b1 - RESET pin enabled as a low leakage mode exit source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_RST_LLRSTE field. */
+#define LLWU_RD_RST_LLRSTE(base) ((LLWU_RST_REG(base) & LLWU_RST_LLRSTE_MASK) >> LLWU_RST_LLRSTE_SHIFT)
+#define LLWU_BRD_RST_LLRSTE(base) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_LLRSTE_SHIFT))
+
+/*! @brief Set the LLRSTE field to a new value. */
+#define LLWU_WR_RST_LLRSTE(base, value) (LLWU_RMW_RST(base, LLWU_RST_LLRSTE_MASK, LLWU_RST_LLRSTE(value)))
+#define LLWU_BWR_RST_LLRSTE(base, value) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_LLRSTE_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 LPTMR
+ *
+ * Low Power Timer
+ *
+ * Registers defined in this header file:
+ * - LPTMR_CSR - Low Power Timer Control Status Register
+ * - LPTMR_PSR - Low Power Timer Prescale Register
+ * - LPTMR_CMR - Low Power Timer Compare Register
+ * - LPTMR_CNR - Low Power Timer Counter Register
+ */
+
+#define LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
+#define LPTMR0_IDX (0U) /*!< Instance number for LPTMR0. */
+
+/*******************************************************************************
+ * LPTMR_CSR - Low Power Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CSR - Low Power Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CSR register
+ */
+/*@{*/
+#define LPTMR_RD_CSR(base)       (LPTMR_CSR_REG(base))
+#define LPTMR_WR_CSR(base, value) (LPTMR_CSR_REG(base) = (value))
+#define LPTMR_RMW_CSR(base, mask, value) (LPTMR_WR_CSR(base, (LPTMR_RD_CSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) |  (value)))
+#define LPTMR_CLR_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) & ~(value)))
+#define LPTMR_TOG_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CSR, field TEN[0] (RW)
+ *
+ * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
+ * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
+ * CSR[5:1] must not be altered.
+ *
+ * Values:
+ * - 0b0 - LPTMR is disabled and internal logic is reset.
+ * - 0b1 - LPTMR is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TEN field. */
+#define LPTMR_RD_CSR_TEN(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TEN_MASK) >> LPTMR_CSR_TEN_SHIFT)
+#define LPTMR_BRD_CSR_TEN(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT))
+
+/*! @brief Set the TEN field to a new value. */
+#define LPTMR_WR_CSR_TEN(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TEN_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TEN(value)))
+#define LPTMR_BWR_CSR_TEN(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TMS[1] (RW)
+ *
+ * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
+ * disabled.
+ *
+ * Values:
+ * - 0b0 - Time Counter mode.
+ * - 0b1 - Pulse Counter mode.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TMS field. */
+#define LPTMR_RD_CSR_TMS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TMS_MASK) >> LPTMR_CSR_TMS_SHIFT)
+#define LPTMR_BRD_CSR_TMS(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT))
+
+/*! @brief Set the TMS field to a new value. */
+#define LPTMR_WR_CSR_TMS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TMS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TMS(value)))
+#define LPTMR_BWR_CSR_TMS(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TFC[2] (RW)
+ *
+ * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
+ * TFC configures the CNR to reset on overflow. TFC must be altered only when the
+ * LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - CNR is reset whenever TCF is set.
+ * - 0b1 - CNR is reset on overflow.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TFC field. */
+#define LPTMR_RD_CSR_TFC(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TFC_MASK) >> LPTMR_CSR_TFC_SHIFT)
+#define LPTMR_BRD_CSR_TFC(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT))
+
+/*! @brief Set the TFC field to a new value. */
+#define LPTMR_WR_CSR_TFC(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TFC_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TFC(value)))
+#define LPTMR_BWR_CSR_TFC(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPP[3] (RW)
+ *
+ * Configures the polarity of the input source in Pulse Counter mode. TPP must
+ * be changed only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - Pulse Counter input source is active-high, and the CNR will increment
+ *     on the rising-edge.
+ * - 0b1 - Pulse Counter input source is active-low, and the CNR will increment
+ *     on the falling-edge.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPP field. */
+#define LPTMR_RD_CSR_TPP(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPP_MASK) >> LPTMR_CSR_TPP_SHIFT)
+#define LPTMR_BRD_CSR_TPP(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT))
+
+/*! @brief Set the TPP field to a new value. */
+#define LPTMR_WR_CSR_TPP(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPP_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPP(value)))
+#define LPTMR_BWR_CSR_TPP(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPS[5:4] (RW)
+ *
+ * Configures the input source to be used in Pulse Counter mode. TPS must be
+ * altered only when the LPTMR is disabled. The input connections vary by device.
+ * See the chip configuration details for information on the connections to these
+ * inputs.
+ *
+ * Values:
+ * - 0b00 - Pulse counter input 0 is selected.
+ * - 0b01 - Pulse counter input 1 is selected.
+ * - 0b10 - Pulse counter input 2 is selected.
+ * - 0b11 - Pulse counter input 3 is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPS field. */
+#define LPTMR_RD_CSR_TPS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPS_MASK) >> LPTMR_CSR_TPS_SHIFT)
+#define LPTMR_BRD_CSR_TPS(base) (LPTMR_RD_CSR_TPS(base))
+
+/*! @brief Set the TPS field to a new value. */
+#define LPTMR_WR_CSR_TPS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPS(value)))
+#define LPTMR_BWR_CSR_TPS(base, value) (LPTMR_WR_CSR_TPS(base, value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TIE[6] (RW)
+ *
+ * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
+ *
+ * Values:
+ * - 0b0 - Timer interrupt disabled.
+ * - 0b1 - Timer interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TIE field. */
+#define LPTMR_RD_CSR_TIE(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TIE_MASK) >> LPTMR_CSR_TIE_SHIFT)
+#define LPTMR_BRD_CSR_TIE(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define LPTMR_WR_CSR_TIE(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TIE_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TIE(value)))
+#define LPTMR_BWR_CSR_TIE(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TCF[7] (W1C)
+ *
+ * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
+ * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
+ *
+ * Values:
+ * - 0b0 - The value of CNR is not equal to CMR and increments.
+ * - 0b1 - The value of CNR is equal to CMR and increments.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TCF field. */
+#define LPTMR_RD_CSR_TCF(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TCF_MASK) >> LPTMR_CSR_TCF_SHIFT)
+#define LPTMR_BRD_CSR_TCF(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT))
+
+/*! @brief Set the TCF field to a new value. */
+#define LPTMR_WR_CSR_TCF(base, value) (LPTMR_RMW_CSR(base, LPTMR_CSR_TCF_MASK, LPTMR_CSR_TCF(value)))
+#define LPTMR_BWR_CSR_TCF(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_PSR - Low Power Timer Prescale Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_PSR - Low Power Timer Prescale Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_PSR register
+ */
+/*@{*/
+#define LPTMR_RD_PSR(base)       (LPTMR_PSR_REG(base))
+#define LPTMR_WR_PSR(base, value) (LPTMR_PSR_REG(base) = (value))
+#define LPTMR_RMW_PSR(base, mask, value) (LPTMR_WR_PSR(base, (LPTMR_RD_PSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) |  (value)))
+#define LPTMR_CLR_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) & ~(value)))
+#define LPTMR_TOG_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_PSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_PSR, field PCS[1:0] (RW)
+ *
+ * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
+ * be altered only when the LPTMR is disabled. The clock connections vary by
+ * device. See the chip configuration details for information on the connections to
+ * these inputs.
+ *
+ * Values:
+ * - 0b00 - Prescaler/glitch filter clock 0 selected.
+ * - 0b01 - Prescaler/glitch filter clock 1 selected.
+ * - 0b10 - Prescaler/glitch filter clock 2 selected.
+ * - 0b11 - Prescaler/glitch filter clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PCS field. */
+#define LPTMR_RD_PSR_PCS(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PCS_MASK) >> LPTMR_PSR_PCS_SHIFT)
+#define LPTMR_BRD_PSR_PCS(base) (LPTMR_RD_PSR_PCS(base))
+
+/*! @brief Set the PCS field to a new value. */
+#define LPTMR_WR_PSR_PCS(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PCS_MASK, LPTMR_PSR_PCS(value)))
+#define LPTMR_BWR_PSR_PCS(base, value) (LPTMR_WR_PSR_PCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PBYP[2] (RW)
+ *
+ * When PBYP is set, the selected prescaler clock in Time Counter mode or
+ * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
+ * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
+ * must be altered only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - Prescaler/glitch filter is enabled.
+ * - 0b1 - Prescaler/glitch filter is bypassed.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PBYP field. */
+#define LPTMR_RD_PSR_PBYP(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PBYP_MASK) >> LPTMR_PSR_PBYP_SHIFT)
+#define LPTMR_BRD_PSR_PBYP(base) (BITBAND_ACCESS32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT))
+
+/*! @brief Set the PBYP field to a new value. */
+#define LPTMR_WR_PSR_PBYP(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PBYP_MASK, LPTMR_PSR_PBYP(value)))
+#define LPTMR_BWR_PSR_PBYP(base, value) (BITBAND_ACCESS32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
+ *
+ * Configures the size of the Prescaler in Time Counter mode or width of the
+ * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
+ * is disabled.
+ *
+ * Values:
+ * - 0b0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
+ *     support this configuration.
+ * - 0b0001 - Prescaler divides the prescaler clock by 4; glitch filter
+ *     recognizes change on input pin after 2 rising clock edges.
+ * - 0b0010 - Prescaler divides the prescaler clock by 8; glitch filter
+ *     recognizes change on input pin after 4 rising clock edges.
+ * - 0b0011 - Prescaler divides the prescaler clock by 16; glitch filter
+ *     recognizes change on input pin after 8 rising clock edges.
+ * - 0b0100 - Prescaler divides the prescaler clock by 32; glitch filter
+ *     recognizes change on input pin after 16 rising clock edges.
+ * - 0b0101 - Prescaler divides the prescaler clock by 64; glitch filter
+ *     recognizes change on input pin after 32 rising clock edges.
+ * - 0b0110 - Prescaler divides the prescaler clock by 128; glitch filter
+ *     recognizes change on input pin after 64 rising clock edges.
+ * - 0b0111 - Prescaler divides the prescaler clock by 256; glitch filter
+ *     recognizes change on input pin after 128 rising clock edges.
+ * - 0b1000 - Prescaler divides the prescaler clock by 512; glitch filter
+ *     recognizes change on input pin after 256 rising clock edges.
+ * - 0b1001 - Prescaler divides the prescaler clock by 1024; glitch filter
+ *     recognizes change on input pin after 512 rising clock edges.
+ * - 0b1010 - Prescaler divides the prescaler clock by 2048; glitch filter
+ *     recognizes change on input pin after 1024 rising clock edges.
+ * - 0b1011 - Prescaler divides the prescaler clock by 4096; glitch filter
+ *     recognizes change on input pin after 2048 rising clock edges.
+ * - 0b1100 - Prescaler divides the prescaler clock by 8192; glitch filter
+ *     recognizes change on input pin after 4096 rising clock edges.
+ * - 0b1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
+ *     recognizes change on input pin after 8192 rising clock edges.
+ * - 0b1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
+ *     recognizes change on input pin after 16,384 rising clock edges.
+ * - 0b1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
+ *     recognizes change on input pin after 32,768 rising clock edges.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
+#define LPTMR_RD_PSR_PRESCALE(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PRESCALE_MASK) >> LPTMR_PSR_PRESCALE_SHIFT)
+#define LPTMR_BRD_PSR_PRESCALE(base) (LPTMR_RD_PSR_PRESCALE(base))
+
+/*! @brief Set the PRESCALE field to a new value. */
+#define LPTMR_WR_PSR_PRESCALE(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PRESCALE_MASK, LPTMR_PSR_PRESCALE(value)))
+#define LPTMR_BWR_PSR_PRESCALE(base, value) (LPTMR_WR_PSR_PRESCALE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CMR - Low Power Timer Compare Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CMR - Low Power Timer Compare Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CMR register
+ */
+/*@{*/
+#define LPTMR_RD_CMR(base)       (LPTMR_CMR_REG(base))
+#define LPTMR_WR_CMR(base, value) (LPTMR_CMR_REG(base) = (value))
+#define LPTMR_RMW_CMR(base, mask, value) (LPTMR_WR_CMR(base, (LPTMR_RD_CMR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) |  (value)))
+#define LPTMR_CLR_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) & ~(value)))
+#define LPTMR_TOG_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CMR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
+ *
+ * When the LPTMR is enabled and the CNR equals the value in the CMR and
+ * increments, TCF is set and the hardware trigger asserts until the next time the CNR
+ * increments. If the CMR is 0, the hardware trigger will remain asserted until
+ * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
+ * when TCF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
+#define LPTMR_RD_CMR_COMPARE(base) ((LPTMR_CMR_REG(base) & LPTMR_CMR_COMPARE_MASK) >> LPTMR_CMR_COMPARE_SHIFT)
+#define LPTMR_BRD_CMR_COMPARE(base) (LPTMR_RD_CMR_COMPARE(base))
+
+/*! @brief Set the COMPARE field to a new value. */
+#define LPTMR_WR_CMR_COMPARE(base, value) (LPTMR_RMW_CMR(base, LPTMR_CMR_COMPARE_MASK, LPTMR_CMR_COMPARE(value)))
+#define LPTMR_BWR_CMR_COMPARE(base, value) (LPTMR_WR_CMR_COMPARE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CNR - Low Power Timer Counter Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CNR - Low Power Timer Counter Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CNR register
+ */
+/*@{*/
+#define LPTMR_RD_CNR(base)       (LPTMR_CNR_REG(base))
+#define LPTMR_WR_CNR(base, value) (LPTMR_CNR_REG(base) = (value))
+#define LPTMR_RMW_CNR(base, mask, value) (LPTMR_WR_CNR(base, (LPTMR_RD_CNR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) |  (value)))
+#define LPTMR_CLR_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) & ~(value)))
+#define LPTMR_TOG_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CNR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
+#define LPTMR_RD_CNR_COUNTER(base) ((LPTMR_CNR_REG(base) & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT)
+#define LPTMR_BRD_CNR_COUNTER(base) (LPTMR_RD_CNR_COUNTER(base))
+
+/*! @brief Set the COUNTER field to a new value. */
+#define LPTMR_WR_CNR_COUNTER(base, value) (LPTMR_RMW_CNR(base, LPTMR_CNR_COUNTER_MASK, LPTMR_CNR_COUNTER(value)))
+#define LPTMR_BWR_CNR_COUNTER(base, value) (LPTMR_WR_CNR_COUNTER(base, value))
+/*@}*/
+
+/*
+ * MK64F12 MCG
+ *
+ * Multipurpose Clock Generator module
+ *
+ * Registers defined in this header file:
+ * - MCG_C1 - MCG Control 1 Register
+ * - MCG_C2 - MCG Control 2 Register
+ * - MCG_C3 - MCG Control 3 Register
+ * - MCG_C4 - MCG Control 4 Register
+ * - MCG_C5 - MCG Control 5 Register
+ * - MCG_C6 - MCG Control 6 Register
+ * - MCG_S - MCG Status Register
+ * - MCG_SC - MCG Status and Control Register
+ * - MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ * - MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ * - MCG_C7 - MCG Control 7 Register
+ * - MCG_C8 - MCG Control 8 Register
+ */
+
+#define MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */
+#define MCG_IDX (0U) /*!< Instance number for MCG. */
+
+/*******************************************************************************
+ * MCG_C1 - MCG Control 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C1 - MCG Control 1 Register (RW)
+ *
+ * Reset value: 0x04U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C1 register
+ */
+/*@{*/
+#define MCG_RD_C1(base)          (MCG_C1_REG(base))
+#define MCG_WR_C1(base, value)   (MCG_C1_REG(base) = (value))
+#define MCG_RMW_C1(base, mask, value) (MCG_WR_C1(base, (MCG_RD_C1(base) & ~(mask)) | (value)))
+#define MCG_SET_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) |  (value)))
+#define MCG_CLR_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) & ~(value)))
+#define MCG_TOG_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C1 bitfields
+ */
+
+/*!
+ * @name Register MCG_C1, field IREFSTEN[0] (RW)
+ *
+ * Controls whether or not the internal reference clock remains enabled when the
+ * MCG enters Stop mode.
+ *
+ * Values:
+ * - 0b0 - Internal reference clock is disabled in Stop mode.
+ * - 0b1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
+ *     if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFSTEN field. */
+#define MCG_RD_C1_IREFSTEN(base) ((MCG_C1_REG(base) & MCG_C1_IREFSTEN_MASK) >> MCG_C1_IREFSTEN_SHIFT)
+#define MCG_BRD_C1_IREFSTEN(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT))
+
+/*! @brief Set the IREFSTEN field to a new value. */
+#define MCG_WR_C1_IREFSTEN(base, value) (MCG_RMW_C1(base, MCG_C1_IREFSTEN_MASK, MCG_C1_IREFSTEN(value)))
+#define MCG_BWR_C1_IREFSTEN(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IRCLKEN[1] (RW)
+ *
+ * Enables the internal reference clock for use as MCGIRCLK.
+ *
+ * Values:
+ * - 0b0 - MCGIRCLK inactive.
+ * - 0b1 - MCGIRCLK active.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IRCLKEN field. */
+#define MCG_RD_C1_IRCLKEN(base) ((MCG_C1_REG(base) & MCG_C1_IRCLKEN_MASK) >> MCG_C1_IRCLKEN_SHIFT)
+#define MCG_BRD_C1_IRCLKEN(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT))
+
+/*! @brief Set the IRCLKEN field to a new value. */
+#define MCG_WR_C1_IRCLKEN(base, value) (MCG_RMW_C1(base, MCG_C1_IRCLKEN_MASK, MCG_C1_IRCLKEN(value)))
+#define MCG_BWR_C1_IRCLKEN(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IREFS[2] (RW)
+ *
+ * Selects the reference clock source for the FLL.
+ *
+ * Values:
+ * - 0b0 - External reference clock is selected.
+ * - 0b1 - The slow internal reference clock is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFS field. */
+#define MCG_RD_C1_IREFS(base) ((MCG_C1_REG(base) & MCG_C1_IREFS_MASK) >> MCG_C1_IREFS_SHIFT)
+#define MCG_BRD_C1_IREFS(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT))
+
+/*! @brief Set the IREFS field to a new value. */
+#define MCG_WR_C1_IREFS(base, value) (MCG_RMW_C1(base, MCG_C1_IREFS_MASK, MCG_C1_IREFS(value)))
+#define MCG_BWR_C1_IREFS(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field FRDIV[5:3] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the FLL.
+ * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
+ * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
+ * not required to meet this range, but it is recommended in the cases when trying
+ * to enter a FLL mode from FBE).
+ *
+ * Values:
+ * - 0b000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
+ *     values, Divide Factor is 32.
+ * - 0b001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
+ *     values, Divide Factor is 64.
+ * - 0b010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
+ *     values, Divide Factor is 128.
+ * - 0b011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
+ *     values, Divide Factor is 256.
+ * - 0b100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
+ *     values, Divide Factor is 512.
+ * - 0b101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
+ *     values, Divide Factor is 1024.
+ * - 0b110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
+ *     values, Divide Factor is 1280 .
+ * - 0b111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other
+ *     RANGE values, Divide Factor is 1536 .
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_FRDIV field. */
+#define MCG_RD_C1_FRDIV(base) ((MCG_C1_REG(base) & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
+#define MCG_BRD_C1_FRDIV(base) (MCG_RD_C1_FRDIV(base))
+
+/*! @brief Set the FRDIV field to a new value. */
+#define MCG_WR_C1_FRDIV(base, value) (MCG_RMW_C1(base, MCG_C1_FRDIV_MASK, MCG_C1_FRDIV(value)))
+#define MCG_BWR_C1_FRDIV(base, value) (MCG_WR_C1_FRDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field CLKS[7:6] (RW)
+ *
+ * Selects the clock source for MCGOUTCLK .
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS
+ *     control bit).
+ * - 0b01 - Encoding 1 - Internal reference clock is selected.
+ * - 0b10 - Encoding 2 - External reference clock is selected.
+ * - 0b11 - Encoding 3 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_CLKS field. */
+#define MCG_RD_C1_CLKS(base) ((MCG_C1_REG(base) & MCG_C1_CLKS_MASK) >> MCG_C1_CLKS_SHIFT)
+#define MCG_BRD_C1_CLKS(base) (MCG_RD_C1_CLKS(base))
+
+/*! @brief Set the CLKS field to a new value. */
+#define MCG_WR_C1_CLKS(base, value) (MCG_RMW_C1(base, MCG_C1_CLKS_MASK, MCG_C1_CLKS(value)))
+#define MCG_BWR_C1_CLKS(base, value) (MCG_WR_C1_CLKS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C2 - MCG Control 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C2 - MCG Control 2 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C2 register
+ */
+/*@{*/
+#define MCG_RD_C2(base)          (MCG_C2_REG(base))
+#define MCG_WR_C2(base, value)   (MCG_C2_REG(base) = (value))
+#define MCG_RMW_C2(base, mask, value) (MCG_WR_C2(base, (MCG_RD_C2(base) & ~(mask)) | (value)))
+#define MCG_SET_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) |  (value)))
+#define MCG_CLR_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) & ~(value)))
+#define MCG_TOG_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C2 bitfields
+ */
+
+/*!
+ * @name Register MCG_C2, field IRCS[0] (RW)
+ *
+ * Selects between the fast or slow internal reference clock source.
+ *
+ * Values:
+ * - 0b0 - Slow internal reference clock selected.
+ * - 0b1 - Fast internal reference clock selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_IRCS field. */
+#define MCG_RD_C2_IRCS(base) ((MCG_C2_REG(base) & MCG_C2_IRCS_MASK) >> MCG_C2_IRCS_SHIFT)
+#define MCG_BRD_C2_IRCS(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT))
+
+/*! @brief Set the IRCS field to a new value. */
+#define MCG_WR_C2_IRCS(base, value) (MCG_RMW_C2(base, MCG_C2_IRCS_MASK, MCG_C2_IRCS(value)))
+#define MCG_BWR_C2_IRCS(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field LP[1] (RW)
+ *
+ * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
+ * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
+ * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
+ * other MCG mode, LP bit has no affect.
+ *
+ * Values:
+ * - 0b0 - FLL or PLL is not disabled in bypass modes.
+ * - 0b1 - FLL or PLL is disabled in bypass modes (lower power)
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_LP field. */
+#define MCG_RD_C2_LP(base)   ((MCG_C2_REG(base) & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
+#define MCG_BRD_C2_LP(base)  (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT))
+
+/*! @brief Set the LP field to a new value. */
+#define MCG_WR_C2_LP(base, value) (MCG_RMW_C2(base, MCG_C2_LP_MASK, MCG_C2_LP(value)))
+#define MCG_BWR_C2_LP(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field EREFS[2] (RW)
+ *
+ * Selects the source for the external reference clock. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0b0 - External reference clock requested.
+ * - 0b1 - Oscillator requested.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_EREFS field. */
+#define MCG_RD_C2_EREFS(base) ((MCG_C2_REG(base) & MCG_C2_EREFS_MASK) >> MCG_C2_EREFS_SHIFT)
+#define MCG_BRD_C2_EREFS(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT))
+
+/*! @brief Set the EREFS field to a new value. */
+#define MCG_WR_C2_EREFS(base, value) (MCG_RMW_C2(base, MCG_C2_EREFS_MASK, MCG_C2_EREFS(value)))
+#define MCG_BWR_C2_EREFS(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field HGO[3] (RW)
+ *
+ * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0b0 - Configure crystal oscillator for low-power operation.
+ * - 0b1 - Configure crystal oscillator for high-gain operation.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_HGO field. */
+#define MCG_RD_C2_HGO(base)  ((MCG_C2_REG(base) & MCG_C2_HGO_MASK) >> MCG_C2_HGO_SHIFT)
+#define MCG_BRD_C2_HGO(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT))
+
+/*! @brief Set the HGO field to a new value. */
+#define MCG_WR_C2_HGO(base, value) (MCG_RMW_C2(base, MCG_C2_HGO_MASK, MCG_C2_HGO(value)))
+#define MCG_BWR_C2_HGO(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field RANGE[5:4] (RW)
+ *
+ * Selects the frequency range for the crystal oscillator or external clock
+ * source. See the Oscillator (OSC) chapter for more details and the device data
+ * sheet for the frequency ranges used.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Low frequency range selected for the crystal oscillator
+ *     .
+ * - 0b01 - Encoding 1 - High frequency range selected for the crystal
+ *     oscillator .
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_RANGE field. */
+#define MCG_RD_C2_RANGE(base) ((MCG_C2_REG(base) & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
+#define MCG_BRD_C2_RANGE(base) (MCG_RD_C2_RANGE(base))
+
+/*! @brief Set the RANGE field to a new value. */
+#define MCG_WR_C2_RANGE(base, value) (MCG_RMW_C2(base, MCG_C2_RANGE_MASK, MCG_C2_RANGE(value)))
+#define MCG_BWR_C2_RANGE(base, value) (MCG_WR_C2_RANGE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field FCFTRIM[6] (RW)
+ *
+ * FCFTRIM controls the smallest adjustment of the fast internal reference clock
+ * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
+ * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_FCFTRIM field. */
+#define MCG_RD_C2_FCFTRIM(base) ((MCG_C2_REG(base) & MCG_C2_FCFTRIM_MASK) >> MCG_C2_FCFTRIM_SHIFT)
+#define MCG_BRD_C2_FCFTRIM(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT))
+
+/*! @brief Set the FCFTRIM field to a new value. */
+#define MCG_WR_C2_FCFTRIM(base, value) (MCG_RMW_C2(base, MCG_C2_FCFTRIM_MASK, MCG_C2_FCFTRIM(value)))
+#define MCG_BWR_C2_FCFTRIM(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field LOCRE0[7] (RW)
+ *
+ * Determines whether an interrupt or a reset request is made following a loss
+ * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
+ * set.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a loss of OSC0 external reference
+ *     clock.
+ * - 0b1 - Generate a reset request on a loss of OSC0 external reference clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_LOCRE0 field. */
+#define MCG_RD_C2_LOCRE0(base) ((MCG_C2_REG(base) & MCG_C2_LOCRE0_MASK) >> MCG_C2_LOCRE0_SHIFT)
+#define MCG_BRD_C2_LOCRE0(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT))
+
+/*! @brief Set the LOCRE0 field to a new value. */
+#define MCG_WR_C2_LOCRE0(base, value) (MCG_RMW_C2(base, MCG_C2_LOCRE0_MASK, MCG_C2_LOCRE0(value)))
+#define MCG_BWR_C2_LOCRE0(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C3 - MCG Control 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C3 - MCG Control 3 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C3 register
+ */
+/*@{*/
+#define MCG_RD_C3(base)          (MCG_C3_REG(base))
+#define MCG_WR_C3(base, value)   (MCG_C3_REG(base) = (value))
+#define MCG_RMW_C3(base, mask, value) (MCG_WR_C3(base, (MCG_RD_C3(base) & ~(mask)) | (value)))
+#define MCG_SET_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) |  (value)))
+#define MCG_CLR_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) & ~(value)))
+#define MCG_TOG_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C4 - MCG Control 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C4 - MCG Control 4 Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Reset values for DRST and DMX32 bits are 0.
+ */
+/*!
+ * @name Constants and macros for entire MCG_C4 register
+ */
+/*@{*/
+#define MCG_RD_C4(base)          (MCG_C4_REG(base))
+#define MCG_WR_C4(base, value)   (MCG_C4_REG(base) = (value))
+#define MCG_RMW_C4(base, mask, value) (MCG_WR_C4(base, (MCG_RD_C4(base) & ~(mask)) | (value)))
+#define MCG_SET_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) |  (value)))
+#define MCG_CLR_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) & ~(value)))
+#define MCG_TOG_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C4 bitfields
+ */
+
+/*!
+ * @name Register MCG_C4, field SCFTRIM[0] (RW)
+ *
+ * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
+ * location . controls the smallest adjustment of the slow internal reference
+ * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
+ * decreases the period by the smallest amount possible. If an SCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_SCFTRIM field. */
+#define MCG_RD_C4_SCFTRIM(base) ((MCG_C4_REG(base) & MCG_C4_SCFTRIM_MASK) >> MCG_C4_SCFTRIM_SHIFT)
+#define MCG_BRD_C4_SCFTRIM(base) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT))
+
+/*! @brief Set the SCFTRIM field to a new value. */
+#define MCG_WR_C4_SCFTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_SCFTRIM_MASK, MCG_C4_SCFTRIM(value)))
+#define MCG_BWR_C4_SCFTRIM(base, value) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field FCTRIM[4:1] (RW)
+ *
+ * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
+ * location. controls the fast internal reference clock frequency by controlling
+ * the fast internal reference clock period. The FCTRIM bits are binary weighted,
+ * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
+ * increases the period, and decreasing the value decreases the period. If an
+ * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
+ * responsibility to copy that value from the nonvolatile memory location to this register.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_FCTRIM field. */
+#define MCG_RD_C4_FCTRIM(base) ((MCG_C4_REG(base) & MCG_C4_FCTRIM_MASK) >> MCG_C4_FCTRIM_SHIFT)
+#define MCG_BRD_C4_FCTRIM(base) (MCG_RD_C4_FCTRIM(base))
+
+/*! @brief Set the FCTRIM field to a new value. */
+#define MCG_WR_C4_FCTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_FCTRIM_MASK, MCG_C4_FCTRIM(value)))
+#define MCG_BWR_C4_FCTRIM(base, value) (MCG_WR_C4_FCTRIM(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
+ *
+ * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
+ * LP bit is set, writes to the DRS bits are ignored. The DRST read field
+ * indicates the current frequency range for DCOOUT. The DRST field does not update
+ * immediately after a write to the DRS field due to internal synchronization between
+ * clock domains. See the DCO Frequency Range table for more details.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Low range (reset default).
+ * - 0b01 - Encoding 1 - Mid range.
+ * - 0b10 - Encoding 2 - Mid-high range.
+ * - 0b11 - Encoding 3 - High range.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_DRST_DRS field. */
+#define MCG_RD_C4_DRST_DRS(base) ((MCG_C4_REG(base) & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
+#define MCG_BRD_C4_DRST_DRS(base) (MCG_RD_C4_DRST_DRS(base))
+
+/*! @brief Set the DRST_DRS field to a new value. */
+#define MCG_WR_C4_DRST_DRS(base, value) (MCG_RMW_C4(base, MCG_C4_DRST_DRS_MASK, MCG_C4_DRST_DRS(value)))
+#define MCG_BWR_C4_DRST_DRS(base, value) (MCG_WR_C4_DRST_DRS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field DMX32[7] (RW)
+ *
+ * The DMX32 bit controls whether the DCO frequency range is narrowed to its
+ * maximum frequency with a 32.768 kHz reference. The following table identifies
+ * settings for the DCO frequency range. The system clocks derived from this source
+ * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
+ * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
+ * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
+ * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
+ * 80-100 MHz 1 32.768 kHz 2929 96 MHz
+ *
+ * Values:
+ * - 0b0 - DCO has a default range of 25%.
+ * - 0b1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_DMX32 field. */
+#define MCG_RD_C4_DMX32(base) ((MCG_C4_REG(base) & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
+#define MCG_BRD_C4_DMX32(base) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT))
+
+/*! @brief Set the DMX32 field to a new value. */
+#define MCG_WR_C4_DMX32(base, value) (MCG_RMW_C4(base, MCG_C4_DMX32_MASK, MCG_C4_DMX32(value)))
+#define MCG_BWR_C4_DMX32(base, value) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C5 - MCG Control 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C5 - MCG Control 5 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C5 register
+ */
+/*@{*/
+#define MCG_RD_C5(base)          (MCG_C5_REG(base))
+#define MCG_WR_C5(base, value)   (MCG_C5_REG(base) = (value))
+#define MCG_RMW_C5(base, mask, value) (MCG_WR_C5(base, (MCG_RD_C5(base) & ~(mask)) | (value)))
+#define MCG_SET_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) |  (value)))
+#define MCG_CLR_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) & ~(value)))
+#define MCG_TOG_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C5 bitfields
+ */
+
+/*!
+ * @name Register MCG_C5, field PRDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the PLL.
+ * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
+ * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
+ * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
+ * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
+ * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
+ * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
+ * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
+ * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
+ * Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PRDIV0 field. */
+#define MCG_RD_C5_PRDIV0(base) ((MCG_C5_REG(base) & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
+#define MCG_BRD_C5_PRDIV0(base) (MCG_RD_C5_PRDIV0(base))
+
+/*! @brief Set the PRDIV0 field to a new value. */
+#define MCG_WR_C5_PRDIV0(base, value) (MCG_RMW_C5(base, MCG_C5_PRDIV0_MASK, MCG_C5_PRDIV0(value)))
+#define MCG_BWR_C5_PRDIV0(base, value) (MCG_WR_C5_PRDIV0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C5, field PLLSTEN0[5] (RW)
+ *
+ * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
+ * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
+ * has no affect and does not enable the PLL Clock to run if it is written to 1.
+ *
+ * Values:
+ * - 0b0 - MCGPLLCLK is disabled in any of the Stop modes.
+ * - 0b1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */
+#define MCG_RD_C5_PLLSTEN0(base) ((MCG_C5_REG(base) & MCG_C5_PLLSTEN0_MASK) >> MCG_C5_PLLSTEN0_SHIFT)
+#define MCG_BRD_C5_PLLSTEN0(base) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLSTEN0_SHIFT))
+
+/*! @brief Set the PLLSTEN0 field to a new value. */
+#define MCG_WR_C5_PLLSTEN0(base, value) (MCG_RMW_C5(base, MCG_C5_PLLSTEN0_MASK, MCG_C5_PLLSTEN0(value)))
+#define MCG_BWR_C5_PLLSTEN0(base, value) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLSTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C5, field PLLCLKEN0[6] (RW)
+ *
+ * Enables the PLL independent of PLLS and enables the PLL clock for use as
+ * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
+ * PLL reference clock in the range of 2 - 4 MHz range prior to setting the
+ * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
+ * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
+ * and the external oscillator is being used as the reference clock, the OSCINIT 0
+ * bit should be checked to make sure it is set.
+ *
+ * Values:
+ * - 0b0 - MCGPLLCLK is inactive.
+ * - 0b1 - MCGPLLCLK is active.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */
+#define MCG_RD_C5_PLLCLKEN0(base) ((MCG_C5_REG(base) & MCG_C5_PLLCLKEN0_MASK) >> MCG_C5_PLLCLKEN0_SHIFT)
+#define MCG_BRD_C5_PLLCLKEN0(base) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLCLKEN0_SHIFT))
+
+/*! @brief Set the PLLCLKEN0 field to a new value. */
+#define MCG_WR_C5_PLLCLKEN0(base, value) (MCG_RMW_C5(base, MCG_C5_PLLCLKEN0_MASK, MCG_C5_PLLCLKEN0(value)))
+#define MCG_BWR_C5_PLLCLKEN0(base, value) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLCLKEN0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C6 - MCG Control 6 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C6 - MCG Control 6 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C6 register
+ */
+/*@{*/
+#define MCG_RD_C6(base)          (MCG_C6_REG(base))
+#define MCG_WR_C6(base, value)   (MCG_C6_REG(base) = (value))
+#define MCG_RMW_C6(base, mask, value) (MCG_WR_C6(base, (MCG_RD_C6(base) & ~(mask)) | (value)))
+#define MCG_SET_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) |  (value)))
+#define MCG_CLR_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) & ~(value)))
+#define MCG_TOG_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C6 bitfields
+ */
+
+/*!
+ * @name Register MCG_C6, field VDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
+ * establish the multiplication factor (M) applied to the reference clock frequency.
+ * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
+ * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
+ * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
+ * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
+ * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
+ * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
+ * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_VDIV0 field. */
+#define MCG_RD_C6_VDIV0(base) ((MCG_C6_REG(base) & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
+#define MCG_BRD_C6_VDIV0(base) (MCG_RD_C6_VDIV0(base))
+
+/*! @brief Set the VDIV0 field to a new value. */
+#define MCG_WR_C6_VDIV0(base, value) (MCG_RMW_C6(base, MCG_C6_VDIV0_MASK, MCG_C6_VDIV0(value)))
+#define MCG_BWR_C6_VDIV0(base, value) (MCG_WR_C6_VDIV0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field CME0[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the OSC0 external reference
+ * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
+ * generated following a loss of OSC0 indication. The CME0 bit must only be set
+ * to a logic 1 when the MCG is in an operational mode that uses the external
+ * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
+ * the value of the RANGE0 bits in the C2 register should not be changed. CME0
+ * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur while in Stop mode. CME0 should also be set to a
+ * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
+ *
+ * Values:
+ * - 0b0 - External clock monitor is disabled for OSC0.
+ * - 0b1 - External clock monitor is enabled for OSC0.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_CME0 field. */
+#define MCG_RD_C6_CME0(base) ((MCG_C6_REG(base) & MCG_C6_CME0_MASK) >> MCG_C6_CME0_SHIFT)
+#define MCG_BRD_C6_CME0(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_CME0_SHIFT))
+
+/*! @brief Set the CME0 field to a new value. */
+#define MCG_WR_C6_CME0(base, value) (MCG_RMW_C6(base, MCG_C6_CME0_MASK, MCG_C6_CME0(value)))
+#define MCG_BWR_C6_CME0(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_CME0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field PLLS[6] (RW)
+ *
+ * Controls whether the PLL or FLL output is selected as the MCG source when
+ * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
+ * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
+ *
+ * Values:
+ * - 0b0 - FLL is selected.
+ * - 0b1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
+ *     to generate a PLL reference clock in the range of 2-4 MHz prior to
+ *     setting the PLLS bit).
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_PLLS field. */
+#define MCG_RD_C6_PLLS(base) ((MCG_C6_REG(base) & MCG_C6_PLLS_MASK) >> MCG_C6_PLLS_SHIFT)
+#define MCG_BRD_C6_PLLS(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_PLLS_SHIFT))
+
+/*! @brief Set the PLLS field to a new value. */
+#define MCG_WR_C6_PLLS(base, value) (MCG_RMW_C6(base, MCG_C6_PLLS_MASK, MCG_C6_PLLS(value)))
+#define MCG_BWR_C6_PLLS(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_PLLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field LOLIE0[7] (RW)
+ *
+ * Determines if an interrupt request is made following a loss of lock
+ * indication. This bit only has an effect when LOLS 0 is set.
+ *
+ * Values:
+ * - 0b0 - No interrupt request is generated on loss of lock.
+ * - 0b1 - Generate an interrupt request on loss of lock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_LOLIE0 field. */
+#define MCG_RD_C6_LOLIE0(base) ((MCG_C6_REG(base) & MCG_C6_LOLIE0_MASK) >> MCG_C6_LOLIE0_SHIFT)
+#define MCG_BRD_C6_LOLIE0(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_LOLIE0_SHIFT))
+
+/*! @brief Set the LOLIE0 field to a new value. */
+#define MCG_WR_C6_LOLIE0(base, value) (MCG_RMW_C6(base, MCG_C6_LOLIE0_MASK, MCG_C6_LOLIE0(value)))
+#define MCG_BWR_C6_LOLIE0(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_LOLIE0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_S - MCG Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_S - MCG Status Register (RW)
+ *
+ * Reset value: 0x10U
+ */
+/*!
+ * @name Constants and macros for entire MCG_S register
+ */
+/*@{*/
+#define MCG_RD_S(base)           (MCG_S_REG(base))
+#define MCG_WR_S(base, value)    (MCG_S_REG(base) = (value))
+#define MCG_RMW_S(base, mask, value) (MCG_WR_S(base, (MCG_RD_S(base) & ~(mask)) | (value)))
+#define MCG_SET_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) |  (value)))
+#define MCG_CLR_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) & ~(value)))
+#define MCG_TOG_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_S bitfields
+ */
+
+/*!
+ * @name Register MCG_S, field IRCST[0] (RO)
+ *
+ * The IRCST bit indicates the current source for the internal reference clock
+ * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
+ * to the IRCS bit due to internal synchronization between clock domains. The
+ * IRCST bit will only be updated if the internal reference clock is enabled,
+ * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
+ * bit .
+ *
+ * Values:
+ * - 0b0 - Source of internal reference clock is the slow clock (32 kHz IRC).
+ * - 0b1 - Source of internal reference clock is the fast clock (4 MHz IRC).
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_IRCST field. */
+#define MCG_RD_S_IRCST(base) ((MCG_S_REG(base) & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT)
+#define MCG_BRD_S_IRCST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_IRCST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field OSCINIT0[1] (RO)
+ *
+ * This bit, which resets to 0, is set to 1 after the initialization cycles of
+ * the crystal oscillator clock have completed. After being set, the bit is
+ * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
+ * description for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_OSCINIT0 field. */
+#define MCG_RD_S_OSCINIT0(base) ((MCG_S_REG(base) & MCG_S_OSCINIT0_MASK) >> MCG_S_OSCINIT0_SHIFT)
+#define MCG_BRD_S_OSCINIT0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_OSCINIT0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field CLKST[3:2] (RO)
+ *
+ * These bits indicate the current clock mode. The CLKST bits do not update
+ * immediately after a write to the CLKS bits due to internal synchronization between
+ * clock domains.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Output of the FLL is selected (reset default).
+ * - 0b01 - Encoding 1 - Internal reference clock is selected.
+ * - 0b10 - Encoding 2 - External reference clock is selected.
+ * - 0b11 - Encoding 3 - Output of the PLL is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_CLKST field. */
+#define MCG_RD_S_CLKST(base) ((MCG_S_REG(base) & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
+#define MCG_BRD_S_CLKST(base) (MCG_RD_S_CLKST(base))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field IREFST[4] (RO)
+ *
+ * This bit indicates the current source for the FLL reference clock. The IREFST
+ * bit does not update immediately after a write to the IREFS bit due to
+ * internal synchronization between clock domains.
+ *
+ * Values:
+ * - 0b0 - Source of FLL reference clock is the external reference clock.
+ * - 0b1 - Source of FLL reference clock is the internal reference clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_IREFST field. */
+#define MCG_RD_S_IREFST(base) ((MCG_S_REG(base) & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
+#define MCG_BRD_S_IREFST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_IREFST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field PLLST[5] (RO)
+ *
+ * This bit indicates the clock source selected by PLLS . The PLLST bit does not
+ * update immediately after a write to the PLLS bit due to internal
+ * synchronization between clock domains.
+ *
+ * Values:
+ * - 0b0 - Source of PLLS clock is FLL clock.
+ * - 0b1 - Source of PLLS clock is PLL output clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_PLLST field. */
+#define MCG_RD_S_PLLST(base) ((MCG_S_REG(base) & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT)
+#define MCG_BRD_S_PLLST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_PLLST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field LOCK0[6] (RO)
+ *
+ * This bit indicates whether the PLL has acquired lock. Lock detection is only
+ * enabled when the PLL is enabled (either through clock mode selection or
+ * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
+ * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
+ * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
+ * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
+ * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
+ * reference clock will also cause the LOCK0 bit to clear until the PLL has
+ * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
+ * the lock status bit to clear and stay cleared until the Stop mode is exited
+ * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
+ * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
+ * again.
+ *
+ * Values:
+ * - 0b0 - PLL is currently unlocked.
+ * - 0b1 - PLL is currently locked.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_LOCK0 field. */
+#define MCG_RD_S_LOCK0(base) ((MCG_S_REG(base) & MCG_S_LOCK0_MASK) >> MCG_S_LOCK0_SHIFT)
+#define MCG_BRD_S_LOCK0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOCK0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field LOLS0[7] (W1C)
+ *
+ * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
+ * if after acquiring lock, the PLL output frequency has fallen outside the lock
+ * exit frequency tolerance, D unl . LOLIE determines whether an interrupt
+ * request is made when LOLS is set. LOLRE determines whether a reset request is made
+ * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
+ * when set. Writing a logic 0 to this bit has no effect.
+ *
+ * Values:
+ * - 0b0 - PLL has not lost lock since LOLS 0 was last cleared.
+ * - 0b1 - PLL has lost lock since LOLS 0 was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_LOLS0 field. */
+#define MCG_RD_S_LOLS0(base) ((MCG_S_REG(base) & MCG_S_LOLS0_MASK) >> MCG_S_LOLS0_SHIFT)
+#define MCG_BRD_S_LOLS0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOLS0_SHIFT))
+
+/*! @brief Set the LOLS0 field to a new value. */
+#define MCG_WR_S_LOLS0(base, value) (MCG_RMW_S(base, MCG_S_LOLS0_MASK, MCG_S_LOLS0(value)))
+#define MCG_BWR_S_LOLS0(base, value) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOLS0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_SC - MCG Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_SC - MCG Status and Control Register (RW)
+ *
+ * Reset value: 0x02U
+ */
+/*!
+ * @name Constants and macros for entire MCG_SC register
+ */
+/*@{*/
+#define MCG_RD_SC(base)          (MCG_SC_REG(base))
+#define MCG_WR_SC(base, value)   (MCG_SC_REG(base) = (value))
+#define MCG_RMW_SC(base, mask, value) (MCG_WR_SC(base, (MCG_RD_SC(base) & ~(mask)) | (value)))
+#define MCG_SET_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) |  (value)))
+#define MCG_CLR_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) & ~(value)))
+#define MCG_TOG_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_SC bitfields
+ */
+
+/*!
+ * @name Register MCG_SC, field LOCS0[0] (W1C)
+ *
+ * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
+ * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
+ * logic 1 to it when set.
+ *
+ * Values:
+ * - 0b0 - Loss of OSC0 has not occurred.
+ * - 0b1 - Loss of OSC0 has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_LOCS0 field. */
+#define MCG_RD_SC_LOCS0(base) ((MCG_SC_REG(base) & MCG_SC_LOCS0_MASK) >> MCG_SC_LOCS0_SHIFT)
+#define MCG_BRD_SC_LOCS0(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT))
+
+/*! @brief Set the LOCS0 field to a new value. */
+#define MCG_WR_SC_LOCS0(base, value) (MCG_RMW_SC(base, MCG_SC_LOCS0_MASK, MCG_SC_LOCS0(value)))
+#define MCG_BWR_SC_LOCS0(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field FCRDIV[3:1] (RW)
+ *
+ * Selects the amount to divide down the fast internal reference clock. The
+ * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
+ * divider when the Fast IRC is enabled is not supported).
+ *
+ * Values:
+ * - 0b000 - Divide Factor is 1
+ * - 0b001 - Divide Factor is 2.
+ * - 0b010 - Divide Factor is 4.
+ * - 0b011 - Divide Factor is 8.
+ * - 0b100 - Divide Factor is 16
+ * - 0b101 - Divide Factor is 32
+ * - 0b110 - Divide Factor is 64
+ * - 0b111 - Divide Factor is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FCRDIV field. */
+#define MCG_RD_SC_FCRDIV(base) ((MCG_SC_REG(base) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
+#define MCG_BRD_SC_FCRDIV(base) (MCG_RD_SC_FCRDIV(base))
+
+/*! @brief Set the FCRDIV field to a new value. */
+#define MCG_WR_SC_FCRDIV(base, value) (MCG_RMW_SC(base, (MCG_SC_FCRDIV_MASK | MCG_SC_LOCS0_MASK), MCG_SC_FCRDIV(value)))
+#define MCG_BWR_SC_FCRDIV(base, value) (MCG_WR_SC_FCRDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field FLTPRSRV[4] (RW)
+ *
+ * This bit will prevent the FLL filter values from resetting allowing the FLL
+ * output frequency to remain the same during clock mode changes where the FLL/DCO
+ * output is still valid. (Note: This requires that the FLL reference frequency
+ * to remain the same as what it was prior to the new clock mode switch.
+ * Otherwise FLL filter and frequency values will change.)
+ *
+ * Values:
+ * - 0b0 - FLL filter and FLL frequency will reset on changes to currect clock
+ *     mode.
+ * - 0b1 - Fll filter and FLL frequency retain their previous values during new
+ *     clock mode change.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FLTPRSRV field. */
+#define MCG_RD_SC_FLTPRSRV(base) ((MCG_SC_REG(base) & MCG_SC_FLTPRSRV_MASK) >> MCG_SC_FLTPRSRV_SHIFT)
+#define MCG_BRD_SC_FLTPRSRV(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT))
+
+/*! @brief Set the FLTPRSRV field to a new value. */
+#define MCG_WR_SC_FLTPRSRV(base, value) (MCG_RMW_SC(base, (MCG_SC_FLTPRSRV_MASK | MCG_SC_LOCS0_MASK), MCG_SC_FLTPRSRV(value)))
+#define MCG_BWR_SC_FLTPRSRV(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATMF[5] (RW)
+ *
+ * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
+ * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
+ * registers is detected or the MCG enters into any Stop mode. A write to ATMF
+ * clears the flag.
+ *
+ * Values:
+ * - 0b0 - Automatic Trim Machine completed normally.
+ * - 0b1 - Automatic Trim Machine failed.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATMF field. */
+#define MCG_RD_SC_ATMF(base) ((MCG_SC_REG(base) & MCG_SC_ATMF_MASK) >> MCG_SC_ATMF_SHIFT)
+#define MCG_BRD_SC_ATMF(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT))
+
+/*! @brief Set the ATMF field to a new value. */
+#define MCG_WR_SC_ATMF(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMF(value)))
+#define MCG_BWR_SC_ATMF(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATMS[6] (RW)
+ *
+ * Selects the IRCS clock for Auto Trim Test.
+ *
+ * Values:
+ * - 0b0 - 32 kHz Internal Reference Clock selected.
+ * - 0b1 - 4 MHz Internal Reference Clock selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATMS field. */
+#define MCG_RD_SC_ATMS(base) ((MCG_SC_REG(base) & MCG_SC_ATMS_MASK) >> MCG_SC_ATMS_SHIFT)
+#define MCG_BRD_SC_ATMS(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT))
+
+/*! @brief Set the ATMS field to a new value. */
+#define MCG_WR_SC_ATMS(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMS(value)))
+#define MCG_BWR_SC_ATMS(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATME[7] (RW)
+ *
+ * Enables the Auto Trim Machine to start automatically trimming the selected
+ * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
+ * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
+ * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
+ * operation and clears this bit.
+ *
+ * Values:
+ * - 0b0 - Auto Trim Machine disabled.
+ * - 0b1 - Auto Trim Machine enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATME field. */
+#define MCG_RD_SC_ATME(base) ((MCG_SC_REG(base) & MCG_SC_ATME_MASK) >> MCG_SC_ATME_SHIFT)
+#define MCG_BRD_SC_ATME(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT))
+
+/*! @brief Set the ATME field to a new value. */
+#define MCG_WR_SC_ATME(base, value) (MCG_RMW_SC(base, (MCG_SC_ATME_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATME(value)))
+#define MCG_BWR_SC_ATME(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_ATCVH register
+ */
+/*@{*/
+#define MCG_RD_ATCVH(base)       (MCG_ATCVH_REG(base))
+#define MCG_WR_ATCVH(base, value) (MCG_ATCVH_REG(base) = (value))
+#define MCG_RMW_ATCVH(base, mask, value) (MCG_WR_ATCVH(base, (MCG_RD_ATCVH(base) & ~(mask)) | (value)))
+#define MCG_SET_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) |  (value)))
+#define MCG_CLR_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) & ~(value)))
+#define MCG_TOG_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_ATCVL register
+ */
+/*@{*/
+#define MCG_RD_ATCVL(base)       (MCG_ATCVL_REG(base))
+#define MCG_WR_ATCVL(base, value) (MCG_ATCVL_REG(base) = (value))
+#define MCG_RMW_ATCVL(base, mask, value) (MCG_WR_ATCVL(base, (MCG_RD_ATCVL(base) & ~(mask)) | (value)))
+#define MCG_SET_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) |  (value)))
+#define MCG_CLR_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) & ~(value)))
+#define MCG_TOG_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C7 - MCG Control 7 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C7 - MCG Control 7 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C7 register
+ */
+/*@{*/
+#define MCG_RD_C7(base)          (MCG_C7_REG(base))
+#define MCG_WR_C7(base, value)   (MCG_C7_REG(base) = (value))
+#define MCG_RMW_C7(base, mask, value) (MCG_WR_C7(base, (MCG_RD_C7(base) & ~(mask)) | (value)))
+#define MCG_SET_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) |  (value)))
+#define MCG_CLR_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) & ~(value)))
+#define MCG_TOG_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C7 bitfields
+ */
+
+/*!
+ * @name Register MCG_C7, field OSCSEL[1:0] (RW)
+ *
+ * Selects the MCG FLL external reference clock
+ *
+ * Values:
+ * - 0b00 - Selects Oscillator (OSCCLK0).
+ * - 0b01 - Selects 32 kHz RTC Oscillator.
+ * - 0b10 - Selects Oscillator (OSCCLK1).
+ * - 0b11 - RESERVED
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C7_OSCSEL field. */
+#define MCG_RD_C7_OSCSEL(base) ((MCG_C7_REG(base) & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
+#define MCG_BRD_C7_OSCSEL(base) (MCG_RD_C7_OSCSEL(base))
+
+/*! @brief Set the OSCSEL field to a new value. */
+#define MCG_WR_C7_OSCSEL(base, value) (MCG_RMW_C7(base, MCG_C7_OSCSEL_MASK, MCG_C7_OSCSEL(value)))
+#define MCG_BWR_C7_OSCSEL(base, value) (MCG_WR_C7_OSCSEL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C8 - MCG Control 8 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C8 - MCG Control 8 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C8 register
+ */
+/*@{*/
+#define MCG_RD_C8(base)          (MCG_C8_REG(base))
+#define MCG_WR_C8(base, value)   (MCG_C8_REG(base) = (value))
+#define MCG_RMW_C8(base, mask, value) (MCG_WR_C8(base, (MCG_RD_C8(base) & ~(mask)) | (value)))
+#define MCG_SET_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) |  (value)))
+#define MCG_CLR_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) & ~(value)))
+#define MCG_TOG_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C8 bitfields
+ */
+
+/*!
+ * @name Register MCG_C8, field LOCS1[0] (W1C)
+ *
+ * This bit indicates when a loss of clock has occurred. This bit is cleared by
+ * writing a logic 1 to it when set.
+ *
+ * Values:
+ * - 0b0 - Loss of RTC has not occur.
+ * - 0b1 - Loss of RTC has occur
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOCS1 field. */
+#define MCG_RD_C8_LOCS1(base) ((MCG_C8_REG(base) & MCG_C8_LOCS1_MASK) >> MCG_C8_LOCS1_SHIFT)
+#define MCG_BRD_C8_LOCS1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT))
+
+/*! @brief Set the LOCS1 field to a new value. */
+#define MCG_WR_C8_LOCS1(base, value) (MCG_RMW_C8(base, MCG_C8_LOCS1_MASK, MCG_C8_LOCS1(value)))
+#define MCG_BWR_C8_LOCS1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field CME1[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the output of the RTC
+ * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
+ * reset request is generated following a loss of RTC clock indication. The CME1
+ * bit should be set to a logic 1 when the MCG is in an operational mode that uses
+ * the RTC as its external reference clock or if the RTC is operational. CME1 bit
+ * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
+ * before entering VLPR or VLPW power modes.
+ *
+ * Values:
+ * - 0b0 - External clock monitor is disabled for RTC clock.
+ * - 0b1 - External clock monitor is enabled for RTC clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_CME1 field. */
+#define MCG_RD_C8_CME1(base) ((MCG_C8_REG(base) & MCG_C8_CME1_MASK) >> MCG_C8_CME1_SHIFT)
+#define MCG_BRD_C8_CME1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT))
+
+/*! @brief Set the CME1 field to a new value. */
+#define MCG_WR_C8_CME1(base, value) (MCG_RMW_C8(base, (MCG_C8_CME1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_CME1(value)))
+#define MCG_BWR_C8_CME1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field LOLRE[6] (RW)
+ *
+ * Determines if an interrupt or a reset request is made following a PLL loss of
+ * lock.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a PLL loss of lock indication. The
+ *     PLL loss of lock interrupt enable bit must also be set to generate the
+ *     interrupt request.
+ * - 0b1 - Generate a reset request on a PLL loss of lock indication.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOLRE field. */
+#define MCG_RD_C8_LOLRE(base) ((MCG_C8_REG(base) & MCG_C8_LOLRE_MASK) >> MCG_C8_LOLRE_SHIFT)
+#define MCG_BRD_C8_LOLRE(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOLRE_SHIFT))
+
+/*! @brief Set the LOLRE field to a new value. */
+#define MCG_WR_C8_LOLRE(base, value) (MCG_RMW_C8(base, (MCG_C8_LOLRE_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOLRE(value)))
+#define MCG_BWR_C8_LOLRE(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOLRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field LOCRE1[7] (RW)
+ *
+ * Determines if a interrupt or a reset request is made following a loss of RTC
+ * external reference clock. The LOCRE1 only has an affect when CME1 is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a loss of RTC external reference
+ *     clock.
+ * - 0b1 - Generate a reset request on a loss of RTC external reference clock
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOCRE1 field. */
+#define MCG_RD_C8_LOCRE1(base) ((MCG_C8_REG(base) & MCG_C8_LOCRE1_MASK) >> MCG_C8_LOCRE1_SHIFT)
+#define MCG_BRD_C8_LOCRE1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT))
+
+/*! @brief Set the LOCRE1 field to a new value. */
+#define MCG_WR_C8_LOCRE1(base, value) (MCG_RMW_C8(base, (MCG_C8_LOCRE1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOCRE1(value)))
+#define MCG_BWR_C8_LOCRE1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 MCM
+ *
+ * Core Platform Miscellaneous Control Module
+ *
+ * Registers defined in this header file:
+ * - MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ * - MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ * - MCM_CR - Control Register
+ * - MCM_ISCR - Interrupt Status Register
+ * - MCM_ETBCC - ETB Counter Control register
+ * - MCM_ETBRL - ETB Reload register
+ * - MCM_ETBCNT - ETB Counter Value register
+ * - MCM_PID - Process ID register
+ */
+
+#define MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
+#define MCM_IDX (0U) /*!< Instance number for MCM. */
+
+/*******************************************************************************
+ * MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
+ *
+ * Reset value: 0x001FU
+ *
+ * PLASC is a 16-bit read-only register identifying the presence/absence of bus
+ * slave connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLASC register
+ */
+/*@{*/
+#define MCM_RD_PLASC(base)       (MCM_PLASC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLASC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLASC, field ASC[7:0] (RO)
+ *
+ * Values:
+ * - 0b00000000 - A bus slave connection to AXBS input port n is absent
+ * - 0b00000001 - A bus slave connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLASC_ASC field. */
+#define MCM_RD_PLASC_ASC(base) ((MCM_PLASC_REG(base) & MCM_PLASC_ASC_MASK) >> MCM_PLASC_ASC_SHIFT)
+#define MCM_BRD_PLASC_ASC(base) (MCM_RD_PLASC_ASC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
+ *
+ * Reset value: 0x0037U
+ *
+ * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
+ * master connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLAMC register
+ */
+/*@{*/
+#define MCM_RD_PLAMC(base)       (MCM_PLAMC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLAMC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLAMC, field AMC[7:0] (RO)
+ *
+ * Values:
+ * - 0b00000000 - A bus master connection to AXBS input port n is absent
+ * - 0b00000001 - A bus master connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLAMC_AMC field. */
+#define MCM_RD_PLAMC_AMC(base) ((MCM_PLAMC_REG(base) & MCM_PLAMC_AMC_MASK) >> MCM_PLAMC_AMC_SHIFT)
+#define MCM_BRD_PLAMC_AMC(base) (MCM_RD_PLAMC_AMC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_CR - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CR defines the arbitration and protection schemes for the two system RAM
+ * arrays.
+ */
+/*!
+ * @name Constants and macros for entire MCM_CR register
+ */
+/*@{*/
+#define MCM_RD_CR(base)          (MCM_CR_REG(base))
+#define MCM_WR_CR(base, value)   (MCM_CR_REG(base) = (value))
+#define MCM_RMW_CR(base, mask, value) (MCM_WR_CR(base, (MCM_RD_CR(base) & ~(mask)) | (value)))
+#define MCM_SET_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) |  (value)))
+#define MCM_CLR_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) & ~(value)))
+#define MCM_TOG_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_CR bitfields
+ */
+
+/*!
+ * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_U array.
+ *
+ * Values:
+ * - 0b00 - Round robin
+ * - 0b01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 0b10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 0b11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMUAP field. */
+#define MCM_RD_CR_SRAMUAP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMUAP_MASK) >> MCM_CR_SRAMUAP_SHIFT)
+#define MCM_BRD_CR_SRAMUAP(base) (MCM_RD_CR_SRAMUAP(base))
+
+/*! @brief Set the SRAMUAP field to a new value. */
+#define MCM_WR_CR_SRAMUAP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMUAP_MASK, MCM_CR_SRAMUAP(value)))
+#define MCM_BWR_CR_SRAMUAP(base, value) (MCM_WR_CR_SRAMUAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMUWP[26] (RW)
+ *
+ * When this bit is set, writes to SRAM_U array generates a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMUWP field. */
+#define MCM_RD_CR_SRAMUWP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMUWP_MASK) >> MCM_CR_SRAMUWP_SHIFT)
+#define MCM_BRD_CR_SRAMUWP(base) (MCM_RD_CR_SRAMUWP(base))
+
+/*! @brief Set the SRAMUWP field to a new value. */
+#define MCM_WR_CR_SRAMUWP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMUWP_MASK, MCM_CR_SRAMUWP(value)))
+#define MCM_BWR_CR_SRAMUWP(base, value) (MCM_WR_CR_SRAMUWP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_L array.
+ *
+ * Values:
+ * - 0b00 - Round robin
+ * - 0b01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 0b10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 0b11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMLAP field. */
+#define MCM_RD_CR_SRAMLAP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMLAP_MASK) >> MCM_CR_SRAMLAP_SHIFT)
+#define MCM_BRD_CR_SRAMLAP(base) (MCM_RD_CR_SRAMLAP(base))
+
+/*! @brief Set the SRAMLAP field to a new value. */
+#define MCM_WR_CR_SRAMLAP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMLAP_MASK, MCM_CR_SRAMLAP(value)))
+#define MCM_BWR_CR_SRAMLAP(base, value) (MCM_WR_CR_SRAMLAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMLWP[30] (RW)
+ *
+ * When this bit is set, writes to SRAM_L array generates a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMLWP field. */
+#define MCM_RD_CR_SRAMLWP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMLWP_MASK) >> MCM_CR_SRAMLWP_SHIFT)
+#define MCM_BRD_CR_SRAMLWP(base) (MCM_RD_CR_SRAMLWP(base))
+
+/*! @brief Set the SRAMLWP field to a new value. */
+#define MCM_WR_CR_SRAMLWP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMLWP_MASK, MCM_CR_SRAMLWP(value)))
+#define MCM_BWR_CR_SRAMLWP(base, value) (MCM_WR_CR_SRAMLWP(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ISCR - Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ISCR - Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ISCR register
+ */
+/*@{*/
+#define MCM_RD_ISCR(base)        (MCM_ISCR_REG(base))
+#define MCM_WR_ISCR(base, value) (MCM_ISCR_REG(base) = (value))
+#define MCM_RMW_ISCR(base, mask, value) (MCM_WR_ISCR(base, (MCM_RD_ISCR(base) & ~(mask)) | (value)))
+#define MCM_SET_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) |  (value)))
+#define MCM_CLR_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) & ~(value)))
+#define MCM_TOG_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ISCR bitfields
+ */
+
+/*!
+ * @name Register MCM_ISCR, field IRQ[1] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0b0 - No pending interrupt
+ * - 0b1 - Due to the ETB counter expiring, a normal interrupt is pending
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_IRQ field. */
+#define MCM_RD_ISCR_IRQ(base) ((MCM_ISCR_REG(base) & MCM_ISCR_IRQ_MASK) >> MCM_ISCR_IRQ_SHIFT)
+#define MCM_BRD_ISCR_IRQ(base) (MCM_RD_ISCR_IRQ(base))
+
+/*! @brief Set the IRQ field to a new value. */
+#define MCM_WR_ISCR_IRQ(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_IRQ(value)))
+#define MCM_BWR_ISCR_IRQ(base, value) (MCM_WR_ISCR_IRQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field NMI[2] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0b0 - No pending NMI
+ * - 0b1 - Due to the ETB counter expiring, an NMI is pending
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_NMI field. */
+#define MCM_RD_ISCR_NMI(base) ((MCM_ISCR_REG(base) & MCM_ISCR_NMI_MASK) >> MCM_ISCR_NMI_SHIFT)
+#define MCM_BRD_ISCR_NMI(base) (MCM_RD_ISCR_NMI(base))
+
+/*! @brief Set the NMI field to a new value. */
+#define MCM_WR_ISCR_NMI(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_NMI_MASK | MCM_ISCR_IRQ_MASK), MCM_ISCR_NMI(value)))
+#define MCM_BWR_ISCR_NMI(base, value) (MCM_WR_ISCR_NMI(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field DHREQ[3] (RO)
+ *
+ * Indicates that a debug halt request is initiated due to a ETB counter
+ * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
+ * counter is disabled or when the ETB counter is reloaded.
+ *
+ * Values:
+ * - 0b0 - No debug halt request
+ * - 0b1 - Debug halt request initiated
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_DHREQ field. */
+#define MCM_RD_ISCR_DHREQ(base) ((MCM_ISCR_REG(base) & MCM_ISCR_DHREQ_MASK) >> MCM_ISCR_DHREQ_SHIFT)
+#define MCM_BRD_ISCR_DHREQ(base) (MCM_RD_ISCR_DHREQ(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIOC[8] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
+ * illegal operation has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IOC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIOC field. */
+#define MCM_RD_ISCR_FIOC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIOC_MASK) >> MCM_ISCR_FIOC_SHIFT)
+#define MCM_BRD_ISCR_FIOC(base) (MCM_RD_ISCR_FIOC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FDZC[9] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
+ * divide by zero has been detected in the processor's FPU. Once set, this bit remains
+ * set until software clears the FPSCR[DZC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FDZC field. */
+#define MCM_RD_ISCR_FDZC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FDZC_MASK) >> MCM_ISCR_FDZC_SHIFT)
+#define MCM_BRD_ISCR_FDZC(base) (MCM_RD_ISCR_FDZC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FOFC[10] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
+ * overflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[OFC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FOFC field. */
+#define MCM_RD_ISCR_FOFC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FOFC_MASK) >> MCM_ISCR_FOFC_SHIFT)
+#define MCM_BRD_ISCR_FOFC(base) (MCM_RD_ISCR_FOFC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FUFC[11] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
+ * underflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[UFC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FUFC field. */
+#define MCM_RD_ISCR_FUFC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FUFC_MASK) >> MCM_ISCR_FUFC_SHIFT)
+#define MCM_BRD_ISCR_FUFC(base) (MCM_RD_ISCR_FUFC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIXC[12] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
+ * inexact number has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IXC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIXC field. */
+#define MCM_RD_ISCR_FIXC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIXC_MASK) >> MCM_ISCR_FIXC_SHIFT)
+#define MCM_BRD_ISCR_FIXC(base) (MCM_RD_ISCR_FIXC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIDC[15] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
+ * denormalized number has been detected in the processor's FPU. Once set, this
+ * bit remains set until software clears the FPSCR[IDC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIDC field. */
+#define MCM_RD_ISCR_FIDC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIDC_MASK) >> MCM_ISCR_FIDC_SHIFT)
+#define MCM_BRD_ISCR_FIDC(base) (MCM_RD_ISCR_FIDC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIOCE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIOCE field. */
+#define MCM_RD_ISCR_FIOCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIOCE_MASK) >> MCM_ISCR_FIOCE_SHIFT)
+#define MCM_BRD_ISCR_FIOCE(base) (MCM_RD_ISCR_FIOCE(base))
+
+/*! @brief Set the FIOCE field to a new value. */
+#define MCM_WR_ISCR_FIOCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIOCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIOCE(value)))
+#define MCM_BWR_ISCR_FIOCE(base, value) (MCM_WR_ISCR_FIOCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FDZCE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FDZCE field. */
+#define MCM_RD_ISCR_FDZCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FDZCE_MASK) >> MCM_ISCR_FDZCE_SHIFT)
+#define MCM_BRD_ISCR_FDZCE(base) (MCM_RD_ISCR_FDZCE(base))
+
+/*! @brief Set the FDZCE field to a new value. */
+#define MCM_WR_ISCR_FDZCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FDZCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FDZCE(value)))
+#define MCM_BWR_ISCR_FDZCE(base, value) (MCM_WR_ISCR_FDZCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FOFCE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FOFCE field. */
+#define MCM_RD_ISCR_FOFCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FOFCE_MASK) >> MCM_ISCR_FOFCE_SHIFT)
+#define MCM_BRD_ISCR_FOFCE(base) (MCM_RD_ISCR_FOFCE(base))
+
+/*! @brief Set the FOFCE field to a new value. */
+#define MCM_WR_ISCR_FOFCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FOFCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FOFCE(value)))
+#define MCM_BWR_ISCR_FOFCE(base, value) (MCM_WR_ISCR_FOFCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FUFCE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FUFCE field. */
+#define MCM_RD_ISCR_FUFCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FUFCE_MASK) >> MCM_ISCR_FUFCE_SHIFT)
+#define MCM_BRD_ISCR_FUFCE(base) (MCM_RD_ISCR_FUFCE(base))
+
+/*! @brief Set the FUFCE field to a new value. */
+#define MCM_WR_ISCR_FUFCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FUFCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FUFCE(value)))
+#define MCM_BWR_ISCR_FUFCE(base, value) (MCM_WR_ISCR_FUFCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIXCE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIXCE field. */
+#define MCM_RD_ISCR_FIXCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIXCE_MASK) >> MCM_ISCR_FIXCE_SHIFT)
+#define MCM_BRD_ISCR_FIXCE(base) (MCM_RD_ISCR_FIXCE(base))
+
+/*! @brief Set the FIXCE field to a new value. */
+#define MCM_WR_ISCR_FIXCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIXCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIXCE(value)))
+#define MCM_BWR_ISCR_FIXCE(base, value) (MCM_WR_ISCR_FIXCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIDCE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIDCE field. */
+#define MCM_RD_ISCR_FIDCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIDCE_MASK) >> MCM_ISCR_FIDCE_SHIFT)
+#define MCM_BRD_ISCR_FIDCE(base) (MCM_RD_ISCR_FIDCE(base))
+
+/*! @brief Set the FIDCE field to a new value. */
+#define MCM_WR_ISCR_FIDCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIDCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIDCE(value)))
+#define MCM_BWR_ISCR_FIDCE(base, value) (MCM_WR_ISCR_FIDCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBCC - ETB Counter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBCC - ETB Counter Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBCC register
+ */
+/*@{*/
+#define MCM_RD_ETBCC(base)       (MCM_ETBCC_REG(base))
+#define MCM_WR_ETBCC(base, value) (MCM_ETBCC_REG(base) = (value))
+#define MCM_RMW_ETBCC(base, mask, value) (MCM_WR_ETBCC(base, (MCM_RD_ETBCC(base) & ~(mask)) | (value)))
+#define MCM_SET_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) |  (value)))
+#define MCM_CLR_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) & ~(value)))
+#define MCM_TOG_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBCC bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCC, field CNTEN[0] (RW)
+ *
+ * Enables the ETB counter.
+ *
+ * Values:
+ * - 0b0 - ETB counter disabled
+ * - 0b1 - ETB counter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_CNTEN field. */
+#define MCM_RD_ETBCC_CNTEN(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_CNTEN_MASK) >> MCM_ETBCC_CNTEN_SHIFT)
+#define MCM_BRD_ETBCC_CNTEN(base) (MCM_RD_ETBCC_CNTEN(base))
+
+/*! @brief Set the CNTEN field to a new value. */
+#define MCM_WR_ETBCC_CNTEN(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_CNTEN_MASK, MCM_ETBCC_CNTEN(value)))
+#define MCM_BWR_ETBCC_CNTEN(base, value) (MCM_WR_ETBCC_CNTEN(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
+ *
+ * Values:
+ * - 0b00 - No response when the ETB count expires
+ * - 0b01 - Generate a normal interrupt when the ETB count expires
+ * - 0b10 - Generate an NMI when the ETB count expires
+ * - 0b11 - Generate a debug halt when the ETB count expires
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_RSPT field. */
+#define MCM_RD_ETBCC_RSPT(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_RSPT_MASK) >> MCM_ETBCC_RSPT_SHIFT)
+#define MCM_BRD_ETBCC_RSPT(base) (MCM_RD_ETBCC_RSPT(base))
+
+/*! @brief Set the RSPT field to a new value. */
+#define MCM_WR_ETBCC_RSPT(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_RSPT_MASK, MCM_ETBCC_RSPT(value)))
+#define MCM_BWR_ETBCC_RSPT(base, value) (MCM_WR_ETBCC_RSPT(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field RLRQ[3] (RW)
+ *
+ * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
+ * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
+ * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
+ * If debug halt was enabled and a debug halt request was asserted on counter
+ * expiration, setting this bit clears the debug halt request.
+ *
+ * Values:
+ * - 0b0 - No effect
+ * - 0b1 - Clears pending debug halt, NMI, or IRQ interrupt requests
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_RLRQ field. */
+#define MCM_RD_ETBCC_RLRQ(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_RLRQ_MASK) >> MCM_ETBCC_RLRQ_SHIFT)
+#define MCM_BRD_ETBCC_RLRQ(base) (MCM_RD_ETBCC_RLRQ(base))
+
+/*! @brief Set the RLRQ field to a new value. */
+#define MCM_WR_ETBCC_RLRQ(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_RLRQ_MASK, MCM_ETBCC_RLRQ(value)))
+#define MCM_BWR_ETBCC_RLRQ(base, value) (MCM_WR_ETBCC_RLRQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field ETDIS[4] (RW)
+ *
+ * Disables the trace path from ETM to TPIU.
+ *
+ * Values:
+ * - 0b0 - ETM-to-TPIU trace path enabled
+ * - 0b1 - ETM-to-TPIU trace path disabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_ETDIS field. */
+#define MCM_RD_ETBCC_ETDIS(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_ETDIS_MASK) >> MCM_ETBCC_ETDIS_SHIFT)
+#define MCM_BRD_ETBCC_ETDIS(base) (MCM_RD_ETBCC_ETDIS(base))
+
+/*! @brief Set the ETDIS field to a new value. */
+#define MCM_WR_ETBCC_ETDIS(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_ETDIS_MASK, MCM_ETBCC_ETDIS(value)))
+#define MCM_BWR_ETBCC_ETDIS(base, value) (MCM_WR_ETBCC_ETDIS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field ITDIS[5] (RW)
+ *
+ * Disables the trace path from ITM to TPIU.
+ *
+ * Values:
+ * - 0b0 - ITM-to-TPIU trace path enabled
+ * - 0b1 - ITM-to-TPIU trace path disabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_ITDIS field. */
+#define MCM_RD_ETBCC_ITDIS(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_ITDIS_MASK) >> MCM_ETBCC_ITDIS_SHIFT)
+#define MCM_BRD_ETBCC_ITDIS(base) (MCM_RD_ETBCC_ITDIS(base))
+
+/*! @brief Set the ITDIS field to a new value. */
+#define MCM_WR_ETBCC_ITDIS(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_ITDIS_MASK, MCM_ETBCC_ITDIS(value)))
+#define MCM_BWR_ETBCC_ITDIS(base, value) (MCM_WR_ETBCC_ITDIS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBRL - ETB Reload register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBRL - ETB Reload register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBRL register
+ */
+/*@{*/
+#define MCM_RD_ETBRL(base)       (MCM_ETBRL_REG(base))
+#define MCM_WR_ETBRL(base, value) (MCM_ETBRL_REG(base) = (value))
+#define MCM_RMW_ETBRL(base, mask, value) (MCM_WR_ETBRL(base, (MCM_RD_ETBRL(base) & ~(mask)) | (value)))
+#define MCM_SET_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) |  (value)))
+#define MCM_CLR_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) & ~(value)))
+#define MCM_TOG_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBRL bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
+ *
+ * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
+ * value to this field results in a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBRL_RELOAD field. */
+#define MCM_RD_ETBRL_RELOAD(base) ((MCM_ETBRL_REG(base) & MCM_ETBRL_RELOAD_MASK) >> MCM_ETBRL_RELOAD_SHIFT)
+#define MCM_BRD_ETBRL_RELOAD(base) (MCM_RD_ETBRL_RELOAD(base))
+
+/*! @brief Set the RELOAD field to a new value. */
+#define MCM_WR_ETBRL_RELOAD(base, value) (MCM_RMW_ETBRL(base, MCM_ETBRL_RELOAD_MASK, MCM_ETBRL_RELOAD(value)))
+#define MCM_BWR_ETBRL_RELOAD(base, value) (MCM_WR_ETBRL_RELOAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBCNT - ETB Counter Value register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBCNT - ETB Counter Value register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBCNT register
+ */
+/*@{*/
+#define MCM_RD_ETBCNT(base)      (MCM_ETBCNT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBCNT bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
+ *
+ * Indicates the current 0-mod-4 value of the counter.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCNT_COUNTER field. */
+#define MCM_RD_ETBCNT_COUNTER(base) ((MCM_ETBCNT_REG(base) & MCM_ETBCNT_COUNTER_MASK) >> MCM_ETBCNT_COUNTER_SHIFT)
+#define MCM_BRD_ETBCNT_COUNTER(base) (MCM_RD_ETBCNT_COUNTER(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PID - Process ID register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PID - Process ID register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register drives the M0_PID and M1_PID values in the Memory Protection
+ * Unit(MPU). System software loads this register before passing control to a given
+ * user mode process. If the PID of the process does not match the value in this
+ * register, a bus error occurs. See the MPU chapter for more details.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PID register
+ */
+/*@{*/
+#define MCM_RD_PID(base)         (MCM_PID_REG(base))
+#define MCM_WR_PID(base, value)  (MCM_PID_REG(base) = (value))
+#define MCM_RMW_PID(base, mask, value) (MCM_WR_PID(base, (MCM_RD_PID(base) & ~(mask)) | (value)))
+#define MCM_SET_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) |  (value)))
+#define MCM_CLR_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) & ~(value)))
+#define MCM_TOG_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PID bitfields
+ */
+
+/*!
+ * @name Register MCM_PID, field PID[7:0] (RW)
+ *
+ * Drives the M0_PID and M1_PID values in the MPU.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PID_PID field. */
+#define MCM_RD_PID_PID(base) ((MCM_PID_REG(base) & MCM_PID_PID_MASK) >> MCM_PID_PID_SHIFT)
+#define MCM_BRD_PID_PID(base) (MCM_RD_PID_PID(base))
+
+/*! @brief Set the PID field to a new value. */
+#define MCM_WR_PID_PID(base, value) (MCM_RMW_PID(base, MCM_PID_PID_MASK, MCM_PID_PID(value)))
+#define MCM_BWR_PID_PID(base, value) (MCM_WR_PID_PID(base, value))
+/*@}*/
+
+/*
+ * MK64F12 MPU
+ *
+ * Memory protection unit
+ *
+ * Registers defined in this header file:
+ * - MPU_CESR - Control/Error Status Register
+ * - MPU_EAR - Error Address Register, slave port n
+ * - MPU_EDR - Error Detail Register, slave port n
+ * - MPU_WORD - Region Descriptor n, Word 0
+ * - MPU_RGDAAC - Region Descriptor Alternate Access Control n
+ */
+
+#define MPU_INSTANCE_COUNT (1U) /*!< Number of instances of the MPU module. */
+#define MPU_IDX (0U) /*!< Instance number for MPU. */
+
+/*******************************************************************************
+ * MPU_CESR - Control/Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_CESR - Control/Error Status Register (RW)
+ *
+ * Reset value: 0x00815101U
+ */
+/*!
+ * @name Constants and macros for entire MPU_CESR register
+ */
+/*@{*/
+#define MPU_RD_CESR(base)        (MPU_CESR_REG(base))
+#define MPU_WR_CESR(base, value) (MPU_CESR_REG(base) = (value))
+#define MPU_RMW_CESR(base, mask, value) (MPU_WR_CESR(base, (MPU_RD_CESR(base) & ~(mask)) | (value)))
+#define MPU_SET_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) |  (value)))
+#define MPU_CLR_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) & ~(value)))
+#define MPU_TOG_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_CESR bitfields
+ */
+
+/*!
+ * @name Register MPU_CESR, field VLD[0] (RW)
+ *
+ * Global enable/disable for the MPU.
+ *
+ * Values:
+ * - 0b0 - MPU is disabled. All accesses from all bus masters are allowed.
+ * - 0b1 - MPU is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_VLD field. */
+#define MPU_RD_CESR_VLD(base) ((MPU_CESR_REG(base) & MPU_CESR_VLD_MASK) >> MPU_CESR_VLD_SHIFT)
+#define MPU_BRD_CESR_VLD(base) (BITBAND_ACCESS32(&MPU_CESR_REG(base), MPU_CESR_VLD_SHIFT))
+
+/*! @brief Set the VLD field to a new value. */
+#define MPU_WR_CESR_VLD(base, value) (MPU_RMW_CESR(base, (MPU_CESR_VLD_MASK | MPU_CESR_SPERR_MASK), MPU_CESR_VLD(value)))
+#define MPU_BWR_CESR_VLD(base, value) (BITBAND_ACCESS32(&MPU_CESR_REG(base), MPU_CESR_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field NRGD[11:8] (RO)
+ *
+ * Indicates the number of region descriptors implemented in the MPU.
+ *
+ * Values:
+ * - 0b0000 - 8 region descriptors
+ * - 0b0001 - 12 region descriptors
+ * - 0b0010 - 16 region descriptors
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_NRGD field. */
+#define MPU_RD_CESR_NRGD(base) ((MPU_CESR_REG(base) & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT)
+#define MPU_BRD_CESR_NRGD(base) (MPU_RD_CESR_NRGD(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field NSP[15:12] (RO)
+ *
+ * Specifies the number of slave ports connected to the MPU.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_NSP field. */
+#define MPU_RD_CESR_NSP(base) ((MPU_CESR_REG(base) & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT)
+#define MPU_BRD_CESR_NSP(base) (MPU_RD_CESR_NSP(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field HRL[19:16] (RO)
+ *
+ * Specifies the MPU's hardware and definition revision level. It can be read by
+ * software to determine the functional definition of the module.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_HRL field. */
+#define MPU_RD_CESR_HRL(base) ((MPU_CESR_REG(base) & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT)
+#define MPU_BRD_CESR_HRL(base) (MPU_RD_CESR_HRL(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field SPERR[31:27] (W1C)
+ *
+ * Indicates a captured error in EARn and EDRn. This bit is set when the
+ * hardware detects an error and records the faulting address and attributes. It is
+ * cleared by writing one to it. If another error is captured at the exact same cycle
+ * as the write, the flag remains set. A find-first-one instruction or
+ * equivalent can detect the presence of a captured error. The following shows the
+ * correspondence between the bit number and slave port number: Bit 31 corresponds to
+ * slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
+ * port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
+ *
+ * Values:
+ * - 0b00000 - No error has occurred for slave port n.
+ * - 0b00001 - An error has occurred for slave port n.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_SPERR field. */
+#define MPU_RD_CESR_SPERR(base) ((MPU_CESR_REG(base) & MPU_CESR_SPERR_MASK) >> MPU_CESR_SPERR_SHIFT)
+#define MPU_BRD_CESR_SPERR(base) (MPU_RD_CESR_SPERR(base))
+
+/*! @brief Set the SPERR field to a new value. */
+#define MPU_WR_CESR_SPERR(base, value) (MPU_RMW_CESR(base, MPU_CESR_SPERR_MASK, MPU_CESR_SPERR(value)))
+#define MPU_BWR_CESR_SPERR(base, value) (MPU_WR_CESR_SPERR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_EAR - Error Address Register, slave port n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_EAR - Error Address Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, the 32-bit reference
+ * address is captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] set. Additional information about the faulting access is captured in
+ * the corresponding EDRn at the same time. This register and the corresponding
+ * EDRn contain the most recent access error; there are no hardware interlocks with
+ * CESR[SPERR], as the error registers are always loaded upon the occurrence of
+ * each protection violation.
+ */
+/*!
+ * @name Constants and macros for entire MPU_EAR register
+ */
+/*@{*/
+#define MPU_RD_EAR(base, index)  (MPU_EAR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_EDR - Error Detail Register, slave port n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_EDR - Error Detail Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, 32 bits of error detail
+ * are captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] is set. Information on the faulting address is captured in the
+ * corresponding EARn register at the same time. This register and the corresponding EARn
+ * register contain the most recent access error; there are no hardware interlocks
+ * with CESR[SPERR] as the error registers are always loaded upon the occurrence
+ * of each protection violation.
+ */
+/*!
+ * @name Constants and macros for entire MPU_EDR register
+ */
+/*@{*/
+#define MPU_RD_EDR(base, index)  (MPU_EDR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_EDR bitfields
+ */
+
+/*!
+ * @name Register MPU_EDR, field ERW[0] (RO)
+ *
+ * Indicates the access type of the faulting reference.
+ *
+ * Values:
+ * - 0b0 - Read
+ * - 0b1 - Write
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_ERW field. */
+#define MPU_RD_EDR_ERW(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT)
+#define MPU_BRD_EDR_ERW(base, index) (BITBAND_ACCESS32(&MPU_EDR_REG(base, index), MPU_EDR_ERW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EATTR[3:1] (RO)
+ *
+ * Indicates attribute information about the faulting reference. All other
+ * encodings are reserved.
+ *
+ * Values:
+ * - 0b000 - User mode, instruction access
+ * - 0b001 - User mode, data access
+ * - 0b010 - Supervisor mode, instruction access
+ * - 0b011 - Supervisor mode, data access
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EATTR field. */
+#define MPU_RD_EDR_EATTR(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT)
+#define MPU_BRD_EDR_EATTR(base, index) (MPU_RD_EDR_EATTR(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EMN[7:4] (RO)
+ *
+ * Indicates the bus master that generated the access error.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EMN field. */
+#define MPU_RD_EDR_EMN(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT)
+#define MPU_BRD_EDR_EMN(base, index) (MPU_RD_EDR_EMN(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EPID[15:8] (RO)
+ *
+ * Records the process identifier of the faulting reference. The process
+ * identifier is typically driven only by processor cores; for other bus masters, this
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EPID field. */
+#define MPU_RD_EDR_EPID(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT)
+#define MPU_BRD_EDR_EPID(base, index) (MPU_RD_EDR_EPID(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EACD[31:16] (RO)
+ *
+ * Indicates the region descriptor with the access error. If EDRn contains a
+ * captured error and EACD is cleared, an access did not hit in any region
+ * descriptor. If only a single EACD bit is set, the protection error was caused by a
+ * single non-overlapping region descriptor. If two or more EACD bits are set, the
+ * protection error was caused by an overlapping set of region descriptors.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EACD field. */
+#define MPU_RD_EDR_EACD(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EACD_MASK) >> MPU_EDR_EACD_SHIFT)
+#define MPU_BRD_EDR_EACD(base, index) (MPU_RD_EDR_EACD(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_WORD - Region Descriptor n, Word 0
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_WORD - Region Descriptor n, Word 0 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The first word of the region descriptor defines the 0-modulo-32 byte start
+ * address of the memory region. Writes to this register clear the region
+ * descriptor's valid bit (RGDn_WORD3[VLD]).
+ */
+/*!
+ * @name Constants and macros for entire MPU_WORD register
+ */
+/*@{*/
+#define MPU_RD_WORD(base, index, index2) (MPU_WORD_REG(base, index, index2))
+#define MPU_WR_WORD(base, index, index2, value) (MPU_WORD_REG(base, index, index2) = (value))
+#define MPU_RMW_WORD(base, index, index2, mask, value) (MPU_WR_WORD(base, index, index2, (MPU_RD_WORD(base, index, index2) & ~(mask)) | (value)))
+#define MPU_SET_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) |  (value)))
+#define MPU_CLR_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) & ~(value)))
+#define MPU_TOG_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_WORD bitfields
+ */
+
+/*!
+ * @name Register MPU_WORD, field VLD[0] (RW)
+ *
+ * Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
+ * bit.
+ *
+ * Values:
+ * - 0b0 - Region descriptor is invalid
+ * - 0b1 - Region descriptor is valid
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_VLD field. */
+#define MPU_RD_WORD_VLD(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_VLD_MASK) >> MPU_WORD_VLD_SHIFT)
+#define MPU_BRD_WORD_VLD(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_VLD_SHIFT))
+
+/*! @brief Set the VLD field to a new value. */
+#define MPU_WR_WORD_VLD(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_VLD_MASK, MPU_WORD_VLD(value)))
+#define MPU_BWR_WORD_VLD(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0UM field. */
+#define MPU_RD_WORD_M0UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0UM_MASK) >> MPU_WORD_M0UM_SHIFT)
+#define MPU_BRD_WORD_M0UM(base, index, index2) (MPU_RD_WORD_M0UM(base, index, index2))
+
+/*! @brief Set the M0UM field to a new value. */
+#define MPU_WR_WORD_M0UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0UM_MASK, MPU_WORD_M0UM(value)))
+#define MPU_BWR_WORD_M0UM(base, index, index2, value) (MPU_WR_WORD_M0UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0SM field. */
+#define MPU_RD_WORD_M0SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0SM_MASK) >> MPU_WORD_M0SM_SHIFT)
+#define MPU_BRD_WORD_M0SM(base, index, index2) (MPU_RD_WORD_M0SM(base, index, index2))
+
+/*! @brief Set the M0SM field to a new value. */
+#define MPU_WR_WORD_M0SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0SM_MASK, MPU_WORD_M0SM(value)))
+#define MPU_BWR_WORD_M0SM(base, index, index2, value) (MPU_WR_WORD_M0SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0PE[5] (RW)
+ *
+ * See M0PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0PE field. */
+#define MPU_RD_WORD_M0PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0PE_MASK) >> MPU_WORD_M0PE_SHIFT)
+#define MPU_BRD_WORD_M0PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M0PE_SHIFT))
+
+/*! @brief Set the M0PE field to a new value. */
+#define MPU_WR_WORD_M0PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0PE_MASK, MPU_WORD_M0PE(value)))
+#define MPU_BWR_WORD_M0PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M0PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field ENDADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 31-modulo-32 byte end address of the
+ * memory region. The MPU does not verify that ENDADDR >= SRTADDR.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_ENDADDR field. */
+#define MPU_RD_WORD_ENDADDR(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_ENDADDR_MASK) >> MPU_WORD_ENDADDR_SHIFT)
+#define MPU_BRD_WORD_ENDADDR(base, index, index2) (MPU_RD_WORD_ENDADDR(base, index, index2))
+
+/*! @brief Set the ENDADDR field to a new value. */
+#define MPU_WR_WORD_ENDADDR(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_ENDADDR_MASK, MPU_WORD_ENDADDR(value)))
+#define MPU_BWR_WORD_ENDADDR(base, index, index2, value) (MPU_WR_WORD_ENDADDR(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field SRTADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 0-modulo-32 byte start address of
+ * the memory region.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_SRTADDR field. */
+#define MPU_RD_WORD_SRTADDR(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_SRTADDR_MASK) >> MPU_WORD_SRTADDR_SHIFT)
+#define MPU_BRD_WORD_SRTADDR(base, index, index2) (MPU_RD_WORD_SRTADDR(base, index, index2))
+
+/*! @brief Set the SRTADDR field to a new value. */
+#define MPU_WR_WORD_SRTADDR(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_SRTADDR_MASK, MPU_WORD_SRTADDR(value)))
+#define MPU_BWR_WORD_SRTADDR(base, index, index2, value) (MPU_WR_WORD_SRTADDR(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1UM field. */
+#define MPU_RD_WORD_M1UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1UM_MASK) >> MPU_WORD_M1UM_SHIFT)
+#define MPU_BRD_WORD_M1UM(base, index, index2) (MPU_RD_WORD_M1UM(base, index, index2))
+
+/*! @brief Set the M1UM field to a new value. */
+#define MPU_WR_WORD_M1UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1UM_MASK, MPU_WORD_M1UM(value)))
+#define MPU_BWR_WORD_M1UM(base, index, index2, value) (MPU_WR_WORD_M1UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1SM field. */
+#define MPU_RD_WORD_M1SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1SM_MASK) >> MPU_WORD_M1SM_SHIFT)
+#define MPU_BRD_WORD_M1SM(base, index, index2) (MPU_RD_WORD_M1SM(base, index, index2))
+
+/*! @brief Set the M1SM field to a new value. */
+#define MPU_WR_WORD_M1SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1SM_MASK, MPU_WORD_M1SM(value)))
+#define MPU_BWR_WORD_M1SM(base, index, index2, value) (MPU_WR_WORD_M1SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1PE field. */
+#define MPU_RD_WORD_M1PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1PE_MASK) >> MPU_WORD_M1PE_SHIFT)
+#define MPU_BRD_WORD_M1PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M1PE_SHIFT))
+
+/*! @brief Set the M1PE field to a new value. */
+#define MPU_WR_WORD_M1PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1PE_MASK, MPU_WORD_M1PE(value)))
+#define MPU_BWR_WORD_M1PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M1PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2UM field. */
+#define MPU_RD_WORD_M2UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2UM_MASK) >> MPU_WORD_M2UM_SHIFT)
+#define MPU_BRD_WORD_M2UM(base, index, index2) (MPU_RD_WORD_M2UM(base, index, index2))
+
+/*! @brief Set the M2UM field to a new value. */
+#define MPU_WR_WORD_M2UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2UM_MASK, MPU_WORD_M2UM(value)))
+#define MPU_BWR_WORD_M2UM(base, index, index2, value) (MPU_WR_WORD_M2UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2SM field. */
+#define MPU_RD_WORD_M2SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2SM_MASK) >> MPU_WORD_M2SM_SHIFT)
+#define MPU_BRD_WORD_M2SM(base, index, index2) (MPU_RD_WORD_M2SM(base, index, index2))
+
+/*! @brief Set the M2SM field to a new value. */
+#define MPU_WR_WORD_M2SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2SM_MASK, MPU_WORD_M2SM(value)))
+#define MPU_BWR_WORD_M2SM(base, index, index2, value) (MPU_WR_WORD_M2SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field PIDMASK[23:16] (RW)
+ *
+ * Provides a masking capability so that multiple process identifiers can be
+ * included as part of the region hit determination. If a bit in PIDMASK is set,
+ * then the corresponding PID bit is ignored in the comparison. This field and PID
+ * are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
+ * more information on the handling of the PID and PIDMASK, see "Access Evaluation
+ * - Hit Determination."
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_PIDMASK field. */
+#define MPU_RD_WORD_PIDMASK(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_PIDMASK_MASK) >> MPU_WORD_PIDMASK_SHIFT)
+#define MPU_BRD_WORD_PIDMASK(base, index, index2) (MPU_RD_WORD_PIDMASK(base, index, index2))
+
+/*! @brief Set the PIDMASK field to a new value. */
+#define MPU_WR_WORD_PIDMASK(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_PIDMASK_MASK, MPU_WORD_PIDMASK(value)))
+#define MPU_BWR_WORD_PIDMASK(base, index, index2, value) (MPU_WR_WORD_PIDMASK(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2PE field. */
+#define MPU_RD_WORD_M2PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2PE_MASK) >> MPU_WORD_M2PE_SHIFT)
+#define MPU_BRD_WORD_M2PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M2PE_SHIFT))
+
+/*! @brief Set the M2PE field to a new value. */
+#define MPU_WR_WORD_M2PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2PE_MASK, MPU_WORD_M2PE(value)))
+#define MPU_BWR_WORD_M2PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M2PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in User mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0b000 - An attempted access of that mode may be terminated with an access
+ *     error (if not allowed by another descriptor) and the access not performed.
+ * - 0b001 - Allows the given access type to occur
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3UM field. */
+#define MPU_RD_WORD_M3UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3UM_MASK) >> MPU_WORD_M3UM_SHIFT)
+#define MPU_BRD_WORD_M3UM(base, index, index2) (MPU_RD_WORD_M3UM(base, index, index2))
+
+/*! @brief Set the M3UM field to a new value. */
+#define MPU_WR_WORD_M3UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3UM_MASK, MPU_WORD_M3UM(value)))
+#define MPU_BWR_WORD_M3UM(base, index, index2, value) (MPU_WR_WORD_M3UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 0b00 - r/w/x; read, write and execute allowed
+ * - 0b01 - r/x; read and execute allowed, but no write
+ * - 0b10 - r/w; read and write allowed, but no execute
+ * - 0b11 - Same as User mode defined in M3UM
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3SM field. */
+#define MPU_RD_WORD_M3SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3SM_MASK) >> MPU_WORD_M3SM_SHIFT)
+#define MPU_BRD_WORD_M3SM(base, index, index2) (MPU_RD_WORD_M3SM(base, index, index2))
+
+/*! @brief Set the M3SM field to a new value. */
+#define MPU_WR_WORD_M3SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3SM_MASK, MPU_WORD_M3SM(value)))
+#define MPU_BWR_WORD_M3SM(base, index, index2, value) (MPU_WR_WORD_M3SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the process identifier in the evaluation
+ * - 0b1 - Include the process identifier and mask (RGDn_WORD3) in the region
+ *     hit evaluation
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3PE field. */
+#define MPU_RD_WORD_M3PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3PE_MASK) >> MPU_WORD_M3PE_SHIFT)
+#define MPU_BRD_WORD_M3PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M3PE_SHIFT))
+
+/*! @brief Set the M3PE field to a new value. */
+#define MPU_WR_WORD_M3PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3PE_MASK, MPU_WORD_M3PE(value)))
+#define MPU_BWR_WORD_M3PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M3PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field PID[31:24] (RW)
+ *
+ * Specifies the process identifier that is included in the region hit
+ * determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
+ * field.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_PID field. */
+#define MPU_RD_WORD_PID(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_PID_MASK) >> MPU_WORD_PID_SHIFT)
+#define MPU_BRD_WORD_PID(base, index, index2) (MPU_RD_WORD_PID(base, index, index2))
+
+/*! @brief Set the PID field to a new value. */
+#define MPU_WR_WORD_PID(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_PID_MASK, MPU_WORD_PID(value)))
+#define MPU_BWR_WORD_PID(base, index, index2, value) (MPU_WR_WORD_PID(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 4 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M4WE field. */
+#define MPU_RD_WORD_M4WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M4WE_MASK) >> MPU_WORD_M4WE_SHIFT)
+#define MPU_BRD_WORD_M4WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4WE_SHIFT))
+
+/*! @brief Set the M4WE field to a new value. */
+#define MPU_WR_WORD_M4WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M4WE_MASK, MPU_WORD_M4WE(value)))
+#define MPU_BWR_WORD_M4WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 4 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M4RE field. */
+#define MPU_RD_WORD_M4RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M4RE_MASK) >> MPU_WORD_M4RE_SHIFT)
+#define MPU_BRD_WORD_M4RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4RE_SHIFT))
+
+/*! @brief Set the M4RE field to a new value. */
+#define MPU_WR_WORD_M4RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M4RE_MASK, MPU_WORD_M4RE(value)))
+#define MPU_BWR_WORD_M4RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 5 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M5WE field. */
+#define MPU_RD_WORD_M5WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M5WE_MASK) >> MPU_WORD_M5WE_SHIFT)
+#define MPU_BRD_WORD_M5WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5WE_SHIFT))
+
+/*! @brief Set the M5WE field to a new value. */
+#define MPU_WR_WORD_M5WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M5WE_MASK, MPU_WORD_M5WE(value)))
+#define MPU_BWR_WORD_M5WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 5 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M5RE field. */
+#define MPU_RD_WORD_M5RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M5RE_MASK) >> MPU_WORD_M5RE_SHIFT)
+#define MPU_BRD_WORD_M5RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5RE_SHIFT))
+
+/*! @brief Set the M5RE field to a new value. */
+#define MPU_WR_WORD_M5RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M5RE_MASK, MPU_WORD_M5RE(value)))
+#define MPU_BWR_WORD_M5RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 6 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M6WE field. */
+#define MPU_RD_WORD_M6WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M6WE_MASK) >> MPU_WORD_M6WE_SHIFT)
+#define MPU_BRD_WORD_M6WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6WE_SHIFT))
+
+/*! @brief Set the M6WE field to a new value. */
+#define MPU_WR_WORD_M6WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M6WE_MASK, MPU_WORD_M6WE(value)))
+#define MPU_BWR_WORD_M6WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 6 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M6RE field. */
+#define MPU_RD_WORD_M6RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M6RE_MASK) >> MPU_WORD_M6RE_SHIFT)
+#define MPU_BRD_WORD_M6RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6RE_SHIFT))
+
+/*! @brief Set the M6RE field to a new value. */
+#define MPU_WR_WORD_M6RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M6RE_MASK, MPU_WORD_M6RE(value)))
+#define MPU_BWR_WORD_M6RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 7 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M7WE field. */
+#define MPU_RD_WORD_M7WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M7WE_MASK) >> MPU_WORD_M7WE_SHIFT)
+#define MPU_BRD_WORD_M7WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7WE_SHIFT))
+
+/*! @brief Set the M7WE field to a new value. */
+#define MPU_WR_WORD_M7WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M7WE_MASK, MPU_WORD_M7WE(value)))
+#define MPU_BWR_WORD_M7WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 7 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M7RE field. */
+#define MPU_RD_WORD_M7RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M7RE_MASK) >> MPU_WORD_M7RE_SHIFT)
+#define MPU_BRD_WORD_M7RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7RE_SHIFT))
+
+/*! @brief Set the M7RE field to a new value. */
+#define MPU_WR_WORD_M7RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M7RE_MASK, MPU_WORD_M7RE(value)))
+#define MPU_BWR_WORD_M7RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_RGDAAC - Region Descriptor Alternate Access Control n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_RGDAAC - Region Descriptor Alternate Access Control n (RW)
+ *
+ * Reset value: 0x0061F7DFU
+ *
+ * Because software may adjust only the access controls within a region
+ * descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
+ * this 32-bit entity is available. Writing to this register does not affect the
+ * descriptor's valid bit.
+ */
+/*!
+ * @name Constants and macros for entire MPU_RGDAAC register
+ */
+/*@{*/
+#define MPU_RD_RGDAAC(base, index) (MPU_RGDAAC_REG(base, index))
+#define MPU_WR_RGDAAC(base, index, value) (MPU_RGDAAC_REG(base, index) = (value))
+#define MPU_RMW_RGDAAC(base, index, mask, value) (MPU_WR_RGDAAC(base, index, (MPU_RD_RGDAAC(base, index) & ~(mask)) | (value)))
+#define MPU_SET_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) |  (value)))
+#define MPU_CLR_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) & ~(value)))
+#define MPU_TOG_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_RGDAAC bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDAAC, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0UM field. */
+#define MPU_RD_RGDAAC_M0UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0UM_MASK) >> MPU_RGDAAC_M0UM_SHIFT)
+#define MPU_BRD_RGDAAC_M0UM(base, index) (MPU_RD_RGDAAC_M0UM(base, index))
+
+/*! @brief Set the M0UM field to a new value. */
+#define MPU_WR_RGDAAC_M0UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0UM_MASK, MPU_RGDAAC_M0UM(value)))
+#define MPU_BWR_RGDAAC_M0UM(base, index, value) (MPU_WR_RGDAAC_M0UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0SM field. */
+#define MPU_RD_RGDAAC_M0SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0SM_MASK) >> MPU_RGDAAC_M0SM_SHIFT)
+#define MPU_BRD_RGDAAC_M0SM(base, index) (MPU_RD_RGDAAC_M0SM(base, index))
+
+/*! @brief Set the M0SM field to a new value. */
+#define MPU_WR_RGDAAC_M0SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0SM_MASK, MPU_RGDAAC_M0SM(value)))
+#define MPU_BWR_RGDAAC_M0SM(base, index, value) (MPU_WR_RGDAAC_M0SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M0PE[5] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0PE field. */
+#define MPU_RD_RGDAAC_M0PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0PE_MASK) >> MPU_RGDAAC_M0PE_SHIFT)
+#define MPU_BRD_RGDAAC_M0PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M0PE_SHIFT))
+
+/*! @brief Set the M0PE field to a new value. */
+#define MPU_WR_RGDAAC_M0PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0PE_MASK, MPU_RGDAAC_M0PE(value)))
+#define MPU_BWR_RGDAAC_M0PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M0PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1UM field. */
+#define MPU_RD_RGDAAC_M1UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1UM_MASK) >> MPU_RGDAAC_M1UM_SHIFT)
+#define MPU_BRD_RGDAAC_M1UM(base, index) (MPU_RD_RGDAAC_M1UM(base, index))
+
+/*! @brief Set the M1UM field to a new value. */
+#define MPU_WR_RGDAAC_M1UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1UM_MASK, MPU_RGDAAC_M1UM(value)))
+#define MPU_BWR_RGDAAC_M1UM(base, index, value) (MPU_WR_RGDAAC_M1UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1SM field. */
+#define MPU_RD_RGDAAC_M1SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1SM_MASK) >> MPU_RGDAAC_M1SM_SHIFT)
+#define MPU_BRD_RGDAAC_M1SM(base, index) (MPU_RD_RGDAAC_M1SM(base, index))
+
+/*! @brief Set the M1SM field to a new value. */
+#define MPU_WR_RGDAAC_M1SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1SM_MASK, MPU_RGDAAC_M1SM(value)))
+#define MPU_BWR_RGDAAC_M1SM(base, index, value) (MPU_WR_RGDAAC_M1SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1PE field. */
+#define MPU_RD_RGDAAC_M1PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1PE_MASK) >> MPU_RGDAAC_M1PE_SHIFT)
+#define MPU_BRD_RGDAAC_M1PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M1PE_SHIFT))
+
+/*! @brief Set the M1PE field to a new value. */
+#define MPU_WR_RGDAAC_M1PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1PE_MASK, MPU_RGDAAC_M1PE(value)))
+#define MPU_BWR_RGDAAC_M1PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M1PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2UM field. */
+#define MPU_RD_RGDAAC_M2UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2UM_MASK) >> MPU_RGDAAC_M2UM_SHIFT)
+#define MPU_BRD_RGDAAC_M2UM(base, index) (MPU_RD_RGDAAC_M2UM(base, index))
+
+/*! @brief Set the M2UM field to a new value. */
+#define MPU_WR_RGDAAC_M2UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2UM_MASK, MPU_RGDAAC_M2UM(value)))
+#define MPU_BWR_RGDAAC_M2UM(base, index, value) (MPU_WR_RGDAAC_M2UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2SM field. */
+#define MPU_RD_RGDAAC_M2SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2SM_MASK) >> MPU_RGDAAC_M2SM_SHIFT)
+#define MPU_BRD_RGDAAC_M2SM(base, index) (MPU_RD_RGDAAC_M2SM(base, index))
+
+/*! @brief Set the M2SM field to a new value. */
+#define MPU_WR_RGDAAC_M2SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2SM_MASK, MPU_RGDAAC_M2SM(value)))
+#define MPU_BWR_RGDAAC_M2SM(base, index, value) (MPU_WR_RGDAAC_M2SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2PE field. */
+#define MPU_RD_RGDAAC_M2PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2PE_MASK) >> MPU_RGDAAC_M2PE_SHIFT)
+#define MPU_BRD_RGDAAC_M2PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M2PE_SHIFT))
+
+/*! @brief Set the M2PE field to a new value. */
+#define MPU_WR_RGDAAC_M2PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2PE_MASK, MPU_RGDAAC_M2PE(value)))
+#define MPU_BWR_RGDAAC_M2PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M2PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in user mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0b000 - An attempted access of that mode may be terminated with an access
+ *     error (if not allowed by another descriptor) and the access not performed.
+ * - 0b001 - Allows the given access type to occur
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3UM field. */
+#define MPU_RD_RGDAAC_M3UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3UM_MASK) >> MPU_RGDAAC_M3UM_SHIFT)
+#define MPU_BRD_RGDAAC_M3UM(base, index) (MPU_RD_RGDAAC_M3UM(base, index))
+
+/*! @brief Set the M3UM field to a new value. */
+#define MPU_WR_RGDAAC_M3UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3UM_MASK, MPU_RGDAAC_M3UM(value)))
+#define MPU_BWR_RGDAAC_M3UM(base, index, value) (MPU_WR_RGDAAC_M3UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 0b00 - r/w/x; read, write and execute allowed
+ * - 0b01 - r/x; read and execute allowed, but no write
+ * - 0b10 - r/w; read and write allowed, but no execute
+ * - 0b11 - Same as User mode defined in M3UM
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3SM field. */
+#define MPU_RD_RGDAAC_M3SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3SM_MASK) >> MPU_RGDAAC_M3SM_SHIFT)
+#define MPU_BRD_RGDAAC_M3SM(base, index) (MPU_RD_RGDAAC_M3SM(base, index))
+
+/*! @brief Set the M3SM field to a new value. */
+#define MPU_WR_RGDAAC_M3SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3SM_MASK, MPU_RGDAAC_M3SM(value)))
+#define MPU_BWR_RGDAAC_M3SM(base, index, value) (MPU_WR_RGDAAC_M3SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the process identifier in the evaluation
+ * - 0b1 - Include the process identifier and mask (RGDn.RGDAAC) in the region
+ *     hit evaluation
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3PE field. */
+#define MPU_RD_RGDAAC_M3PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3PE_MASK) >> MPU_RGDAAC_M3PE_SHIFT)
+#define MPU_BRD_RGDAAC_M3PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M3PE_SHIFT))
+
+/*! @brief Set the M3PE field to a new value. */
+#define MPU_WR_RGDAAC_M3PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3PE_MASK, MPU_RGDAAC_M3PE(value)))
+#define MPU_BWR_RGDAAC_M3PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M3PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 4 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M4WE field. */
+#define MPU_RD_RGDAAC_M4WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M4WE_MASK) >> MPU_RGDAAC_M4WE_SHIFT)
+#define MPU_BRD_RGDAAC_M4WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4WE_SHIFT))
+
+/*! @brief Set the M4WE field to a new value. */
+#define MPU_WR_RGDAAC_M4WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M4WE_MASK, MPU_RGDAAC_M4WE(value)))
+#define MPU_BWR_RGDAAC_M4WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 4 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M4RE field. */
+#define MPU_RD_RGDAAC_M4RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M4RE_MASK) >> MPU_RGDAAC_M4RE_SHIFT)
+#define MPU_BRD_RGDAAC_M4RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4RE_SHIFT))
+
+/*! @brief Set the M4RE field to a new value. */
+#define MPU_WR_RGDAAC_M4RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M4RE_MASK, MPU_RGDAAC_M4RE(value)))
+#define MPU_BWR_RGDAAC_M4RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 5 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M5WE field. */
+#define MPU_RD_RGDAAC_M5WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M5WE_MASK) >> MPU_RGDAAC_M5WE_SHIFT)
+#define MPU_BRD_RGDAAC_M5WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5WE_SHIFT))
+
+/*! @brief Set the M5WE field to a new value. */
+#define MPU_WR_RGDAAC_M5WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M5WE_MASK, MPU_RGDAAC_M5WE(value)))
+#define MPU_BWR_RGDAAC_M5WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 5 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M5RE field. */
+#define MPU_RD_RGDAAC_M5RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M5RE_MASK) >> MPU_RGDAAC_M5RE_SHIFT)
+#define MPU_BRD_RGDAAC_M5RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5RE_SHIFT))
+
+/*! @brief Set the M5RE field to a new value. */
+#define MPU_WR_RGDAAC_M5RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M5RE_MASK, MPU_RGDAAC_M5RE(value)))
+#define MPU_BWR_RGDAAC_M5RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 6 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M6WE field. */
+#define MPU_RD_RGDAAC_M6WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M6WE_MASK) >> MPU_RGDAAC_M6WE_SHIFT)
+#define MPU_BRD_RGDAAC_M6WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6WE_SHIFT))
+
+/*! @brief Set the M6WE field to a new value. */
+#define MPU_WR_RGDAAC_M6WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M6WE_MASK, MPU_RGDAAC_M6WE(value)))
+#define MPU_BWR_RGDAAC_M6WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 6 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M6RE field. */
+#define MPU_RD_RGDAAC_M6RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M6RE_MASK) >> MPU_RGDAAC_M6RE_SHIFT)
+#define MPU_BRD_RGDAAC_M6RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6RE_SHIFT))
+
+/*! @brief Set the M6RE field to a new value. */
+#define MPU_WR_RGDAAC_M6RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M6RE_MASK, MPU_RGDAAC_M6RE(value)))
+#define MPU_BWR_RGDAAC_M6RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 7 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M7WE field. */
+#define MPU_RD_RGDAAC_M7WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M7WE_MASK) >> MPU_RGDAAC_M7WE_SHIFT)
+#define MPU_BRD_RGDAAC_M7WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7WE_SHIFT))
+
+/*! @brief Set the M7WE field to a new value. */
+#define MPU_WR_RGDAAC_M7WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M7WE_MASK, MPU_RGDAAC_M7WE(value)))
+#define MPU_BWR_RGDAAC_M7WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 7 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M7RE field. */
+#define MPU_RD_RGDAAC_M7RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M7RE_MASK) >> MPU_RGDAAC_M7RE_SHIFT)
+#define MPU_BRD_RGDAAC_M7RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7RE_SHIFT))
+
+/*! @brief Set the M7RE field to a new value. */
+#define MPU_WR_RGDAAC_M7RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M7RE_MASK, MPU_RGDAAC_M7RE(value)))
+#define MPU_BWR_RGDAAC_M7RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7RE_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 NV
+ *
+ * Flash configuration field
+ *
+ * Registers defined in this header file:
+ * - NV_BACKKEY3 - Backdoor Comparison Key 3.
+ * - NV_BACKKEY2 - Backdoor Comparison Key 2.
+ * - NV_BACKKEY1 - Backdoor Comparison Key 1.
+ * - NV_BACKKEY0 - Backdoor Comparison Key 0.
+ * - NV_BACKKEY7 - Backdoor Comparison Key 7.
+ * - NV_BACKKEY6 - Backdoor Comparison Key 6.
+ * - NV_BACKKEY5 - Backdoor Comparison Key 5.
+ * - NV_BACKKEY4 - Backdoor Comparison Key 4.
+ * - NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ * - NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ * - NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ * - NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ * - NV_FSEC - Non-volatile Flash Security Register
+ * - NV_FOPT - Non-volatile Flash Option Register
+ * - NV_FEPROT - Non-volatile EERAM Protection Register
+ * - NV_FDPROT - Non-volatile D-Flash Protection Register
+ */
+
+#define NV_INSTANCE_COUNT (1U) /*!< Number of instances of the NV module. */
+#define FTFE_FlashConfig_IDX (0U) /*!< Instance number for FTFE_FlashConfig. */
+
+/*******************************************************************************
+ * NV_BACKKEY3 - Backdoor Comparison Key 3.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY3 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY3(base)     (NV_BACKKEY3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY2 - Backdoor Comparison Key 2.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY2 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY2(base)     (NV_BACKKEY2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY1 - Backdoor Comparison Key 1.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY1 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY1(base)     (NV_BACKKEY1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY0 - Backdoor Comparison Key 0.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY0 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY0(base)     (NV_BACKKEY0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY7 - Backdoor Comparison Key 7.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY7 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY7(base)     (NV_BACKKEY7_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY6 - Backdoor Comparison Key 6.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY6 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY6(base)     (NV_BACKKEY6_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY5 - Backdoor Comparison Key 5.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY5 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY5(base)     (NV_BACKKEY5_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY4 - Backdoor Comparison Key 4.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY4 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY4(base)     (NV_BACKKEY4_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT3 register
+ */
+/*@{*/
+#define NV_RD_FPROT3(base)       (NV_FPROT3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT2 register
+ */
+/*@{*/
+#define NV_RD_FPROT2(base)       (NV_FPROT2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT1 register
+ */
+/*@{*/
+#define NV_RD_FPROT1(base)       (NV_FPROT1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT0 register
+ */
+/*@{*/
+#define NV_RD_FPROT0(base)       (NV_FPROT0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FSEC - Non-volatile Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FSEC - Non-volatile Flash Security Register (RO)
+ *
+ * Reset value: 0xFFU
+ *
+ * Allows the user to customize the operation of the MCU at boot time
+ */
+/*!
+ * @name Constants and macros for entire NV_FSEC register
+ */
+/*@{*/
+#define NV_RD_FSEC(base)         (NV_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FSEC bitfields
+ */
+
+/*!
+ * @name Register NV_FSEC, field SEC[1:0] (RO)
+ *
+ * Values:
+ * - 0b10 - MCU security status is unsecure
+ * - 0b11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_SEC field. */
+#define NV_RD_FSEC_SEC(base) ((NV_FSEC_REG(base) & NV_FSEC_SEC_MASK) >> NV_FSEC_SEC_SHIFT)
+#define NV_BRD_FSEC_SEC(base) (NV_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field FSLACC[3:2] (RO)
+ *
+ * Values:
+ * - 0b10 - Freescale factory access denied
+ * - 0b11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_FSLACC field. */
+#define NV_RD_FSEC_FSLACC(base) ((NV_FSEC_REG(base) & NV_FSEC_FSLACC_MASK) >> NV_FSEC_FSLACC_SHIFT)
+#define NV_BRD_FSEC_FSLACC(base) (NV_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field MEEN[5:4] (RO)
+ *
+ * Values:
+ * - 0b10 - Mass erase is disabled
+ * - 0b11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_MEEN field. */
+#define NV_RD_FSEC_MEEN(base) ((NV_FSEC_REG(base) & NV_FSEC_MEEN_MASK) >> NV_FSEC_MEEN_SHIFT)
+#define NV_BRD_FSEC_MEEN(base) (NV_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field KEYEN[7:6] (RO)
+ *
+ * Values:
+ * - 0b10 - Backdoor key access enabled
+ * - 0b11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_KEYEN field. */
+#define NV_RD_FSEC_KEYEN(base) ((NV_FSEC_REG(base) & NV_FSEC_KEYEN_MASK) >> NV_FSEC_KEYEN_SHIFT)
+#define NV_BRD_FSEC_KEYEN(base) (NV_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FOPT - Non-volatile Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FOPT - Non-volatile Flash Option Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FOPT register
+ */
+/*@{*/
+#define NV_RD_FOPT(base)         (NV_FOPT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FOPT bitfields
+ */
+
+/*!
+ * @name Register NV_FOPT, field LPBOOT[0] (RO)
+ *
+ * Values:
+ * - 0b0 - Low-power boot
+ * - 0b1 - Normal boot
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_LPBOOT field. */
+#define NV_RD_FOPT_LPBOOT(base) ((NV_FOPT_REG(base) & NV_FOPT_LPBOOT_MASK) >> NV_FOPT_LPBOOT_SHIFT)
+#define NV_BRD_FOPT_LPBOOT(base) (BITBAND_ACCESS8(&NV_FOPT_REG(base), NV_FOPT_LPBOOT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register NV_FOPT, field EZPORT_DIS[1] (RO)
+ *
+ * Values:
+ * - 0b0 - EzPort operation is disabled
+ * - 0b1 - EzPort operation is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_EZPORT_DIS field. */
+#define NV_RD_FOPT_EZPORT_DIS(base) ((NV_FOPT_REG(base) & NV_FOPT_EZPORT_DIS_MASK) >> NV_FOPT_EZPORT_DIS_SHIFT)
+#define NV_BRD_FOPT_EZPORT_DIS(base) (BITBAND_ACCESS8(&NV_FOPT_REG(base), NV_FOPT_EZPORT_DIS_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FEPROT - Non-volatile EERAM Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FEPROT - Non-volatile EERAM Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FEPROT register
+ */
+/*@{*/
+#define NV_RD_FEPROT(base)       (NV_FEPROT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FDPROT - Non-volatile D-Flash Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FDPROT - Non-volatile D-Flash Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FDPROT register
+ */
+/*@{*/
+#define NV_RD_FDPROT(base)       (NV_FDPROT_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 OSC
+ *
+ * Oscillator
+ *
+ * Registers defined in this header file:
+ * - OSC_CR - OSC Control Register
+ */
+
+#define OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */
+#define OSC_IDX (0U) /*!< Instance number for OSC. */
+
+/*******************************************************************************
+ * OSC_CR - OSC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief OSC_CR - OSC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * After OSC is enabled and starts generating the clocks, the configurations
+ * such as low power and frequency range, must not be changed.
+ */
+/*!
+ * @name Constants and macros for entire OSC_CR register
+ */
+/*@{*/
+#define OSC_RD_CR(base)          (OSC_CR_REG(base))
+#define OSC_WR_CR(base, value)   (OSC_CR_REG(base) = (value))
+#define OSC_RMW_CR(base, mask, value) (OSC_WR_CR(base, (OSC_RD_CR(base) & ~(mask)) | (value)))
+#define OSC_SET_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) |  (value)))
+#define OSC_CLR_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) & ~(value)))
+#define OSC_TOG_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual OSC_CR bitfields
+ */
+
+/*!
+ * @name Register OSC_CR, field SC16P[0] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 16 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC16P field. */
+#define OSC_RD_CR_SC16P(base) ((OSC_CR_REG(base) & OSC_CR_SC16P_MASK) >> OSC_CR_SC16P_SHIFT)
+#define OSC_BRD_CR_SC16P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT))
+
+/*! @brief Set the SC16P field to a new value. */
+#define OSC_WR_CR_SC16P(base, value) (OSC_RMW_CR(base, OSC_CR_SC16P_MASK, OSC_CR_SC16P(value)))
+#define OSC_BWR_CR_SC16P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC8P[1] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 8 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC8P field. */
+#define OSC_RD_CR_SC8P(base) ((OSC_CR_REG(base) & OSC_CR_SC8P_MASK) >> OSC_CR_SC8P_SHIFT)
+#define OSC_BRD_CR_SC8P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT))
+
+/*! @brief Set the SC8P field to a new value. */
+#define OSC_WR_CR_SC8P(base, value) (OSC_RMW_CR(base, OSC_CR_SC8P_MASK, OSC_CR_SC8P(value)))
+#define OSC_BWR_CR_SC8P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC4P[2] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 4 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC4P field. */
+#define OSC_RD_CR_SC4P(base) ((OSC_CR_REG(base) & OSC_CR_SC4P_MASK) >> OSC_CR_SC4P_SHIFT)
+#define OSC_BRD_CR_SC4P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT))
+
+/*! @brief Set the SC4P field to a new value. */
+#define OSC_WR_CR_SC4P(base, value) (OSC_RMW_CR(base, OSC_CR_SC4P_MASK, OSC_CR_SC4P(value)))
+#define OSC_BWR_CR_SC4P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC2P[3] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 2 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC2P field. */
+#define OSC_RD_CR_SC2P(base) ((OSC_CR_REG(base) & OSC_CR_SC2P_MASK) >> OSC_CR_SC2P_SHIFT)
+#define OSC_BRD_CR_SC2P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT))
+
+/*! @brief Set the SC2P field to a new value. */
+#define OSC_WR_CR_SC2P(base, value) (OSC_RMW_CR(base, OSC_CR_SC2P_MASK, OSC_CR_SC2P(value)))
+#define OSC_BWR_CR_SC2P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field EREFSTEN[5] (RW)
+ *
+ * Controls whether or not the external reference clock (OSCERCLK) remains
+ * enabled when MCU enters Stop mode.
+ *
+ * Values:
+ * - 0b0 - External reference clock is disabled in Stop mode.
+ * - 0b1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
+ *     before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_EREFSTEN field. */
+#define OSC_RD_CR_EREFSTEN(base) ((OSC_CR_REG(base) & OSC_CR_EREFSTEN_MASK) >> OSC_CR_EREFSTEN_SHIFT)
+#define OSC_BRD_CR_EREFSTEN(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT))
+
+/*! @brief Set the EREFSTEN field to a new value. */
+#define OSC_WR_CR_EREFSTEN(base, value) (OSC_RMW_CR(base, OSC_CR_EREFSTEN_MASK, OSC_CR_EREFSTEN(value)))
+#define OSC_BWR_CR_EREFSTEN(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field ERCLKEN[7] (RW)
+ *
+ * Enables external reference clock (OSCERCLK).
+ *
+ * Values:
+ * - 0b0 - External reference clock is inactive.
+ * - 0b1 - External reference clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_ERCLKEN field. */
+#define OSC_RD_CR_ERCLKEN(base) ((OSC_CR_REG(base) & OSC_CR_ERCLKEN_MASK) >> OSC_CR_ERCLKEN_SHIFT)
+#define OSC_BRD_CR_ERCLKEN(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT))
+
+/*! @brief Set the ERCLKEN field to a new value. */
+#define OSC_WR_CR_ERCLKEN(base, value) (OSC_RMW_CR(base, OSC_CR_ERCLKEN_MASK, OSC_CR_ERCLKEN(value)))
+#define OSC_BWR_CR_ERCLKEN(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PDB
+ *
+ * Programmable Delay Block
+ *
+ * Registers defined in this header file:
+ * - PDB_SC - Status and Control register
+ * - PDB_MOD - Modulus register
+ * - PDB_CNT - Counter register
+ * - PDB_IDLY - Interrupt Delay register
+ * - PDB_C1 - Channel n Control register 1
+ * - PDB_S - Channel n Status register
+ * - PDB_DLY - Channel n Delay 0 register
+ * - PDB_INTC - DAC Interval Trigger n Control register
+ * - PDB_INT - DAC Interval n register
+ * - PDB_POEN - Pulse-Out n Enable register
+ * - PDB_PODLY - Pulse-Out n Delay register
+ */
+
+#define PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */
+#define PDB0_IDX (0U) /*!< Instance number for PDB0. */
+
+/*******************************************************************************
+ * PDB_SC - Status and Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_SC - Status and Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_SC register
+ */
+/*@{*/
+#define PDB_RD_SC(base)          (PDB_SC_REG(base))
+#define PDB_WR_SC(base, value)   (PDB_SC_REG(base) = (value))
+#define PDB_RMW_SC(base, mask, value) (PDB_WR_SC(base, (PDB_RD_SC(base) & ~(mask)) | (value)))
+#define PDB_SET_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) |  (value)))
+#define PDB_CLR_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) & ~(value)))
+#define PDB_TOG_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_SC bitfields
+ */
+
+/*!
+ * @name Register PDB_SC, field LDOK[0] (RW)
+ *
+ * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
+ * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
+ * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
+ * written to the LDOK field, the values in the buffers of above registers are
+ * not effective and the buffers cannot be written until the values in buffers are
+ * loaded into their internal registers. LDOK can be written only when PDBEN is
+ * set or it can be written at the same time with PDBEN being written to 1. It is
+ * automatically cleared when the values in buffers are loaded into the internal
+ * registers or the PDBEN is cleared. Writing 0 to it has no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_LDOK field. */
+#define PDB_RD_SC_LDOK(base) ((PDB_SC_REG(base) & PDB_SC_LDOK_MASK) >> PDB_SC_LDOK_SHIFT)
+#define PDB_BRD_SC_LDOK(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_LDOK_SHIFT))
+
+/*! @brief Set the LDOK field to a new value. */
+#define PDB_WR_SC_LDOK(base, value) (PDB_RMW_SC(base, PDB_SC_LDOK_MASK, PDB_SC_LDOK(value)))
+#define PDB_BWR_SC_LDOK(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_LDOK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field CONT[1] (RW)
+ *
+ * Enables the PDB operation in Continuous mode.
+ *
+ * Values:
+ * - 0b0 - PDB operation in One-Shot mode
+ * - 0b1 - PDB operation in Continuous mode
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_CONT field. */
+#define PDB_RD_SC_CONT(base) ((PDB_SC_REG(base) & PDB_SC_CONT_MASK) >> PDB_SC_CONT_SHIFT)
+#define PDB_BRD_SC_CONT(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_CONT_SHIFT))
+
+/*! @brief Set the CONT field to a new value. */
+#define PDB_WR_SC_CONT(base, value) (PDB_RMW_SC(base, PDB_SC_CONT_MASK, PDB_SC_CONT(value)))
+#define PDB_BWR_SC_CONT(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_CONT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field MULT[3:2] (RW)
+ *
+ * Selects the multiplication factor of the prescaler divider for the counter
+ * clock.
+ *
+ * Values:
+ * - 0b00 - Multiplication factor is 1.
+ * - 0b01 - Multiplication factor is 10.
+ * - 0b10 - Multiplication factor is 20.
+ * - 0b11 - Multiplication factor is 40.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_MULT field. */
+#define PDB_RD_SC_MULT(base) ((PDB_SC_REG(base) & PDB_SC_MULT_MASK) >> PDB_SC_MULT_SHIFT)
+#define PDB_BRD_SC_MULT(base) (PDB_RD_SC_MULT(base))
+
+/*! @brief Set the MULT field to a new value. */
+#define PDB_WR_SC_MULT(base, value) (PDB_RMW_SC(base, PDB_SC_MULT_MASK, PDB_SC_MULT(value)))
+#define PDB_BWR_SC_MULT(base, value) (PDB_WR_SC_MULT(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBIE[5] (RW)
+ *
+ * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
+ * generates a PDB interrupt.
+ *
+ * Values:
+ * - 0b0 - PDB interrupt disabled.
+ * - 0b1 - PDB interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBIE field. */
+#define PDB_RD_SC_PDBIE(base) ((PDB_SC_REG(base) & PDB_SC_PDBIE_MASK) >> PDB_SC_PDBIE_SHIFT)
+#define PDB_BRD_SC_PDBIE(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIE_SHIFT))
+
+/*! @brief Set the PDBIE field to a new value. */
+#define PDB_WR_SC_PDBIE(base, value) (PDB_RMW_SC(base, PDB_SC_PDBIE_MASK, PDB_SC_PDBIE(value)))
+#define PDB_BWR_SC_PDBIE(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBIF[6] (RW)
+ *
+ * This field is set when the counter value is equal to the IDLY register.
+ * Writing zero clears this field.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBIF field. */
+#define PDB_RD_SC_PDBIF(base) ((PDB_SC_REG(base) & PDB_SC_PDBIF_MASK) >> PDB_SC_PDBIF_SHIFT)
+#define PDB_BRD_SC_PDBIF(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIF_SHIFT))
+
+/*! @brief Set the PDBIF field to a new value. */
+#define PDB_WR_SC_PDBIF(base, value) (PDB_RMW_SC(base, PDB_SC_PDBIF_MASK, PDB_SC_PDBIF(value)))
+#define PDB_BWR_SC_PDBIF(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - PDB disabled. Counter is off.
+ * - 0b1 - PDB enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBEN field. */
+#define PDB_RD_SC_PDBEN(base) ((PDB_SC_REG(base) & PDB_SC_PDBEN_MASK) >> PDB_SC_PDBEN_SHIFT)
+#define PDB_BRD_SC_PDBEN(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEN_SHIFT))
+
+/*! @brief Set the PDBEN field to a new value. */
+#define PDB_WR_SC_PDBEN(base, value) (PDB_RMW_SC(base, PDB_SC_PDBEN_MASK, PDB_SC_PDBEN(value)))
+#define PDB_BWR_SC_PDBEN(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field TRGSEL[11:8] (RW)
+ *
+ * Selects the trigger input source for the PDB. The trigger input source can be
+ * internal or external (EXTRG pin), or the software trigger. Refer to chip
+ * configuration details for the actual PDB input trigger connections.
+ *
+ * Values:
+ * - 0b0000 - Trigger-In 0 is selected.
+ * - 0b0001 - Trigger-In 1 is selected.
+ * - 0b0010 - Trigger-In 2 is selected.
+ * - 0b0011 - Trigger-In 3 is selected.
+ * - 0b0100 - Trigger-In 4 is selected.
+ * - 0b0101 - Trigger-In 5 is selected.
+ * - 0b0110 - Trigger-In 6 is selected.
+ * - 0b0111 - Trigger-In 7 is selected.
+ * - 0b1000 - Trigger-In 8 is selected.
+ * - 0b1001 - Trigger-In 9 is selected.
+ * - 0b1010 - Trigger-In 10 is selected.
+ * - 0b1011 - Trigger-In 11 is selected.
+ * - 0b1100 - Trigger-In 12 is selected.
+ * - 0b1101 - Trigger-In 13 is selected.
+ * - 0b1110 - Trigger-In 14 is selected.
+ * - 0b1111 - Software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_TRGSEL field. */
+#define PDB_RD_SC_TRGSEL(base) ((PDB_SC_REG(base) & PDB_SC_TRGSEL_MASK) >> PDB_SC_TRGSEL_SHIFT)
+#define PDB_BRD_SC_TRGSEL(base) (PDB_RD_SC_TRGSEL(base))
+
+/*! @brief Set the TRGSEL field to a new value. */
+#define PDB_WR_SC_TRGSEL(base, value) (PDB_RMW_SC(base, PDB_SC_TRGSEL_MASK, PDB_SC_TRGSEL(value)))
+#define PDB_BWR_SC_TRGSEL(base, value) (PDB_WR_SC_TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PRESCALER[14:12] (RW)
+ *
+ * Values:
+ * - 0b000 - Counting uses the peripheral clock divided by multiplication factor
+ *     selected by MULT.
+ * - 0b001 - Counting uses the peripheral clock divided by twice of the
+ *     multiplication factor selected by MULT.
+ * - 0b010 - Counting uses the peripheral clock divided by four times of the
+ *     multiplication factor selected by MULT.
+ * - 0b011 - Counting uses the peripheral clock divided by eight times of the
+ *     multiplication factor selected by MULT.
+ * - 0b100 - Counting uses the peripheral clock divided by 16 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b101 - Counting uses the peripheral clock divided by 32 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b110 - Counting uses the peripheral clock divided by 64 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b111 - Counting uses the peripheral clock divided by 128 times of the
+ *     multiplication factor selected by MULT.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PRESCALER field. */
+#define PDB_RD_SC_PRESCALER(base) ((PDB_SC_REG(base) & PDB_SC_PRESCALER_MASK) >> PDB_SC_PRESCALER_SHIFT)
+#define PDB_BRD_SC_PRESCALER(base) (PDB_RD_SC_PRESCALER(base))
+
+/*! @brief Set the PRESCALER field to a new value. */
+#define PDB_WR_SC_PRESCALER(base, value) (PDB_RMW_SC(base, PDB_SC_PRESCALER_MASK, PDB_SC_PRESCALER(value)))
+#define PDB_BWR_SC_PRESCALER(base, value) (PDB_WR_SC_PRESCALER(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field DMAEN[15] (RW)
+ *
+ * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
+ * interrupt.
+ *
+ * Values:
+ * - 0b0 - DMA disabled.
+ * - 0b1 - DMA enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_DMAEN field. */
+#define PDB_RD_SC_DMAEN(base) ((PDB_SC_REG(base) & PDB_SC_DMAEN_MASK) >> PDB_SC_DMAEN_SHIFT)
+#define PDB_BRD_SC_DMAEN(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define PDB_WR_SC_DMAEN(base, value) (PDB_RMW_SC(base, PDB_SC_DMAEN_MASK, PDB_SC_DMAEN(value)))
+#define PDB_BWR_SC_DMAEN(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field SWTRIG[16] (WORZ)
+ *
+ * When PDB is enabled and the software trigger is selected as the trigger input
+ * source, writing 1 to this field resets and restarts the counter. Writing 0 to
+ * this field has no effect. Reading this field results 0.
+ */
+/*@{*/
+/*! @brief Set the SWTRIG field to a new value. */
+#define PDB_WR_SC_SWTRIG(base, value) (PDB_RMW_SC(base, PDB_SC_SWTRIG_MASK, PDB_SC_SWTRIG(value)))
+#define PDB_BWR_SC_SWTRIG(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_SWTRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBEIE[17] (RW)
+ *
+ * Enables the PDB sequence error interrupt. When this field is set, any of the
+ * PDB channel sequence error flags generates a PDB sequence error interrupt.
+ *
+ * Values:
+ * - 0b0 - PDB sequence error interrupt disabled.
+ * - 0b1 - PDB sequence error interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBEIE field. */
+#define PDB_RD_SC_PDBEIE(base) ((PDB_SC_REG(base) & PDB_SC_PDBEIE_MASK) >> PDB_SC_PDBEIE_SHIFT)
+#define PDB_BRD_SC_PDBEIE(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEIE_SHIFT))
+
+/*! @brief Set the PDBEIE field to a new value. */
+#define PDB_WR_SC_PDBEIE(base, value) (PDB_RMW_SC(base, PDB_SC_PDBEIE_MASK, PDB_SC_PDBEIE(value)))
+#define PDB_BWR_SC_PDBEIE(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field LDMOD[19:18] (RW)
+ *
+ * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
+ * after 1 is written to LDOK.
+ *
+ * Values:
+ * - 0b00 - The internal registers are loaded with the values from their buffers
+ *     immediately after 1 is written to LDOK.
+ * - 0b01 - The internal registers are loaded with the values from their buffers
+ *     when the PDB counter reaches the MOD register value after 1 is written to
+ *     LDOK.
+ * - 0b10 - The internal registers are loaded with the values from their buffers
+ *     when a trigger input event is detected after 1 is written to LDOK.
+ * - 0b11 - The internal registers are loaded with the values from their buffers
+ *     when either the PDB counter reaches the MOD register value or a trigger
+ *     input event is detected, after 1 is written to LDOK.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_LDMOD field. */
+#define PDB_RD_SC_LDMOD(base) ((PDB_SC_REG(base) & PDB_SC_LDMOD_MASK) >> PDB_SC_LDMOD_SHIFT)
+#define PDB_BRD_SC_LDMOD(base) (PDB_RD_SC_LDMOD(base))
+
+/*! @brief Set the LDMOD field to a new value. */
+#define PDB_WR_SC_LDMOD(base, value) (PDB_RMW_SC(base, PDB_SC_LDMOD_MASK, PDB_SC_LDMOD(value)))
+#define PDB_BWR_SC_LDMOD(base, value) (PDB_WR_SC_LDMOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_MOD - Modulus register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_MOD - Modulus register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+/*!
+ * @name Constants and macros for entire PDB_MOD register
+ */
+/*@{*/
+#define PDB_RD_MOD(base)         (PDB_MOD_REG(base))
+#define PDB_WR_MOD(base, value)  (PDB_MOD_REG(base) = (value))
+#define PDB_RMW_MOD(base, mask, value) (PDB_WR_MOD(base, (PDB_RD_MOD(base) & ~(mask)) | (value)))
+#define PDB_SET_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) |  (value)))
+#define PDB_CLR_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) & ~(value)))
+#define PDB_TOG_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_MOD bitfields
+ */
+
+/*!
+ * @name Register PDB_MOD, field MOD[15:0] (RW)
+ *
+ * Specifies the period of the counter. When the counter reaches this value, it
+ * will be reset back to zero. If the PDB is in Continuous mode, the count begins
+ * anew. Reading this field returns the value of the internal register that is
+ * effective for the current cycle of PDB.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_MOD_MOD field. */
+#define PDB_RD_MOD_MOD(base) ((PDB_MOD_REG(base) & PDB_MOD_MOD_MASK) >> PDB_MOD_MOD_SHIFT)
+#define PDB_BRD_MOD_MOD(base) (PDB_RD_MOD_MOD(base))
+
+/*! @brief Set the MOD field to a new value. */
+#define PDB_WR_MOD_MOD(base, value) (PDB_RMW_MOD(base, PDB_MOD_MOD_MASK, PDB_MOD_MOD(value)))
+#define PDB_BWR_MOD_MOD(base, value) (PDB_WR_MOD_MOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_CNT - Counter register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_CNT - Counter register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_CNT register
+ */
+/*@{*/
+#define PDB_RD_CNT(base)         (PDB_CNT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_CNT bitfields
+ */
+
+/*!
+ * @name Register PDB_CNT, field CNT[15:0] (RO)
+ *
+ * Contains the current value of the counter.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_CNT_CNT field. */
+#define PDB_RD_CNT_CNT(base) ((PDB_CNT_REG(base) & PDB_CNT_CNT_MASK) >> PDB_CNT_CNT_SHIFT)
+#define PDB_BRD_CNT_CNT(base) (PDB_RD_CNT_CNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_IDLY - Interrupt Delay register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_IDLY - Interrupt Delay register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+/*!
+ * @name Constants and macros for entire PDB_IDLY register
+ */
+/*@{*/
+#define PDB_RD_IDLY(base)        (PDB_IDLY_REG(base))
+#define PDB_WR_IDLY(base, value) (PDB_IDLY_REG(base) = (value))
+#define PDB_RMW_IDLY(base, mask, value) (PDB_WR_IDLY(base, (PDB_RD_IDLY(base) & ~(mask)) | (value)))
+#define PDB_SET_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) |  (value)))
+#define PDB_CLR_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) & ~(value)))
+#define PDB_TOG_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_IDLY bitfields
+ */
+
+/*!
+ * @name Register PDB_IDLY, field IDLY[15:0] (RW)
+ *
+ * Specifies the delay value to schedule the PDB interrupt. It can be used to
+ * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
+ * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
+ * this field returns the value of internal register that is effective for the
+ * current cycle of the PDB.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_IDLY_IDLY field. */
+#define PDB_RD_IDLY_IDLY(base) ((PDB_IDLY_REG(base) & PDB_IDLY_IDLY_MASK) >> PDB_IDLY_IDLY_SHIFT)
+#define PDB_BRD_IDLY_IDLY(base) (PDB_RD_IDLY_IDLY(base))
+
+/*! @brief Set the IDLY field to a new value. */
+#define PDB_WR_IDLY_IDLY(base, value) (PDB_RMW_IDLY(base, PDB_IDLY_IDLY_MASK, PDB_IDLY_IDLY(value)))
+#define PDB_BWR_IDLY_IDLY(base, value) (PDB_WR_IDLY_IDLY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_C1 - Channel n Control register 1
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_C1 - Channel n Control register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PDB channel has one control register, CHnC1. The bits in this register
+ * control the functionality of each PDB channel operation.
+ */
+/*!
+ * @name Constants and macros for entire PDB_C1 register
+ */
+/*@{*/
+#define PDB_RD_C1(base, index)   (PDB_C1_REG(base, index))
+#define PDB_WR_C1(base, index, value) (PDB_C1_REG(base, index) = (value))
+#define PDB_RMW_C1(base, index, mask, value) (PDB_WR_C1(base, index, (PDB_RD_C1(base, index) & ~(mask)) | (value)))
+#define PDB_SET_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) |  (value)))
+#define PDB_CLR_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) & ~(value)))
+#define PDB_TOG_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_C1 bitfields
+ */
+
+/*!
+ * @name Register PDB_C1, field EN[7:0] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
+ * bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger disabled.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_EN field. */
+#define PDB_RD_C1_EN(base, index) ((PDB_C1_REG(base, index) & PDB_C1_EN_MASK) >> PDB_C1_EN_SHIFT)
+#define PDB_BRD_C1_EN(base, index) (PDB_RD_C1_EN(base, index))
+
+/*! @brief Set the EN field to a new value. */
+#define PDB_WR_C1_EN(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_EN_MASK, PDB_C1_EN(value)))
+#define PDB_BWR_C1_EN(base, index, value) (PDB_WR_C1_EN(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_C1, field TOS[15:8] (RW)
+ *
+ * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
+ * implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger is in bypassed mode.
+ *     The pre-trigger asserts one peripheral clock cycle after a rising edge is
+ *     detected on selected trigger input source or software trigger is selected
+ *     and SWTRIG is written with 1.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger asserts when the
+ *     counter reaches the channel delay register and one peripheral clock cycle after
+ *     a rising edge is detected on selected trigger input source or software
+ *     trigger is selected and SETRIG is written with 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_TOS field. */
+#define PDB_RD_C1_TOS(base, index) ((PDB_C1_REG(base, index) & PDB_C1_TOS_MASK) >> PDB_C1_TOS_SHIFT)
+#define PDB_BRD_C1_TOS(base, index) (PDB_RD_C1_TOS(base, index))
+
+/*! @brief Set the TOS field to a new value. */
+#define PDB_WR_C1_TOS(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_TOS_MASK, PDB_C1_TOS(value)))
+#define PDB_BWR_C1_TOS(base, index, value) (PDB_WR_C1_TOS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_C1, field BB[23:16] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
+ * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
+ * enables the ADC conversions complete to trigger the next PDB channel
+ * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
+ * set of configuration and results registers. Application code must only enable
+ * the back-to-back operation of the PDB pre-triggers at the leading of the
+ * back-to-back connection chain.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger back-to-back operation
+ *     disabled.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger back-to-back operation
+ *     enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_BB field. */
+#define PDB_RD_C1_BB(base, index) ((PDB_C1_REG(base, index) & PDB_C1_BB_MASK) >> PDB_C1_BB_SHIFT)
+#define PDB_BRD_C1_BB(base, index) (PDB_RD_C1_BB(base, index))
+
+/*! @brief Set the BB field to a new value. */
+#define PDB_WR_C1_BB(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_BB_MASK, PDB_C1_BB(value)))
+#define PDB_BWR_C1_BB(base, index, value) (PDB_WR_C1_BB(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_S - Channel n Status register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_S - Channel n Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_S register
+ */
+/*@{*/
+#define PDB_RD_S(base, index)    (PDB_S_REG(base, index))
+#define PDB_WR_S(base, index, value) (PDB_S_REG(base, index) = (value))
+#define PDB_RMW_S(base, index, mask, value) (PDB_WR_S(base, index, (PDB_RD_S(base, index) & ~(mask)) | (value)))
+#define PDB_SET_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) |  (value)))
+#define PDB_CLR_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) & ~(value)))
+#define PDB_TOG_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_S bitfields
+ */
+
+/*!
+ * @name Register PDB_S, field ERR[7:0] (RW)
+ *
+ * Only the lower M bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - Sequence error not detected on PDB channel's corresponding
+ *     pre-trigger.
+ * - 0b00000001 - Sequence error detected on PDB channel's corresponding
+ *     pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from
+ *     PDB channel n. When one conversion, which is triggered by one of the
+ *     pre-triggers from PDB channel n, is in progress, new trigger from PDB
+ *     channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is
+ *     set. Writing 0's to clear the sequence error flags.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_S_ERR field. */
+#define PDB_RD_S_ERR(base, index) ((PDB_S_REG(base, index) & PDB_S_ERR_MASK) >> PDB_S_ERR_SHIFT)
+#define PDB_BRD_S_ERR(base, index) (PDB_RD_S_ERR(base, index))
+
+/*! @brief Set the ERR field to a new value. */
+#define PDB_WR_S_ERR(base, index, value) (PDB_RMW_S(base, index, PDB_S_ERR_MASK, PDB_S_ERR(value)))
+#define PDB_BWR_S_ERR(base, index, value) (PDB_WR_S_ERR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_S, field CF[23:16] (RW)
+ *
+ * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
+ * clear these bits.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_S_CF field. */
+#define PDB_RD_S_CF(base, index) ((PDB_S_REG(base, index) & PDB_S_CF_MASK) >> PDB_S_CF_SHIFT)
+#define PDB_BRD_S_CF(base, index) (PDB_RD_S_CF(base, index))
+
+/*! @brief Set the CF field to a new value. */
+#define PDB_WR_S_CF(base, index, value) (PDB_RMW_S(base, index, PDB_S_CF_MASK, PDB_S_CF(value)))
+#define PDB_BWR_S_CF(base, index, value) (PDB_WR_S_CF(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_DLY - Channel n Delay 0 register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_DLY - Channel n Delay 0 register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_DLY register
+ */
+/*@{*/
+#define PDB_RD_DLY(base, index, index2) (PDB_DLY_REG(base, index, index2))
+#define PDB_WR_DLY(base, index, index2, value) (PDB_DLY_REG(base, index, index2) = (value))
+#define PDB_RMW_DLY(base, index, index2, mask, value) (PDB_WR_DLY(base, index, index2, (PDB_RD_DLY(base, index, index2) & ~(mask)) | (value)))
+#define PDB_SET_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) |  (value)))
+#define PDB_CLR_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) & ~(value)))
+#define PDB_TOG_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_DLY bitfields
+ */
+
+/*!
+ * @name Register PDB_DLY, field DLY[15:0] (RW)
+ *
+ * Specifies the delay value for the channel's corresponding pre-trigger. The
+ * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
+ * the value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_DLY_DLY field. */
+#define PDB_RD_DLY_DLY(base, index, index2) ((PDB_DLY_REG(base, index, index2) & PDB_DLY_DLY_MASK) >> PDB_DLY_DLY_SHIFT)
+#define PDB_BRD_DLY_DLY(base, index, index2) (PDB_RD_DLY_DLY(base, index, index2))
+
+/*! @brief Set the DLY field to a new value. */
+#define PDB_WR_DLY_DLY(base, index, index2, value) (PDB_RMW_DLY(base, index, index2, PDB_DLY_DLY_MASK, PDB_DLY_DLY(value)))
+#define PDB_BWR_DLY_DLY(base, index, index2, value) (PDB_WR_DLY_DLY(base, index, index2, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_INTC - DAC Interval Trigger n Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_INTC - DAC Interval Trigger n Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_INTC register
+ */
+/*@{*/
+#define PDB_RD_INTC(base, index) (PDB_INTC_REG(base, index))
+#define PDB_WR_INTC(base, index, value) (PDB_INTC_REG(base, index) = (value))
+#define PDB_RMW_INTC(base, index, mask, value) (PDB_WR_INTC(base, index, (PDB_RD_INTC(base, index) & ~(mask)) | (value)))
+#define PDB_SET_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) |  (value)))
+#define PDB_CLR_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) & ~(value)))
+#define PDB_TOG_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_INTC bitfields
+ */
+
+/*!
+ * @name Register PDB_INTC, field TOE[0] (RW)
+ *
+ * This bit enables the DAC interval trigger.
+ *
+ * Values:
+ * - 0b0 - DAC interval trigger disabled.
+ * - 0b1 - DAC interval trigger enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INTC_TOE field. */
+#define PDB_RD_INTC_TOE(base, index) ((PDB_INTC_REG(base, index) & PDB_INTC_TOE_MASK) >> PDB_INTC_TOE_SHIFT)
+#define PDB_BRD_INTC_TOE(base, index) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_TOE_SHIFT))
+
+/*! @brief Set the TOE field to a new value. */
+#define PDB_WR_INTC_TOE(base, index, value) (PDB_RMW_INTC(base, index, PDB_INTC_TOE_MASK, PDB_INTC_TOE(value)))
+#define PDB_BWR_INTC_TOE(base, index, value) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_TOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_INTC, field EXT[1] (RW)
+ *
+ * Enables the external trigger for DAC interval counter.
+ *
+ * Values:
+ * - 0b0 - DAC external trigger input disabled. DAC interval counter is reset
+ *     and counting starts when a rising edge is detected on selected trigger input
+ *     source or software trigger is selected and SWTRIG is written with 1.
+ * - 0b1 - DAC external trigger input enabled. DAC interval counter is bypassed
+ *     and DAC external trigger input triggers the DAC interval trigger.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INTC_EXT field. */
+#define PDB_RD_INTC_EXT(base, index) ((PDB_INTC_REG(base, index) & PDB_INTC_EXT_MASK) >> PDB_INTC_EXT_SHIFT)
+#define PDB_BRD_INTC_EXT(base, index) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_EXT_SHIFT))
+
+/*! @brief Set the EXT field to a new value. */
+#define PDB_WR_INTC_EXT(base, index, value) (PDB_RMW_INTC(base, index, PDB_INTC_EXT_MASK, PDB_INTC_EXT(value)))
+#define PDB_BWR_INTC_EXT(base, index, value) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_EXT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_INT - DAC Interval n register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_INT - DAC Interval n register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_INT register
+ */
+/*@{*/
+#define PDB_RD_INT(base, index)  (PDB_INT_REG(base, index))
+#define PDB_WR_INT(base, index, value) (PDB_INT_REG(base, index) = (value))
+#define PDB_RMW_INT(base, index, mask, value) (PDB_WR_INT(base, index, (PDB_RD_INT(base, index) & ~(mask)) | (value)))
+#define PDB_SET_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) |  (value)))
+#define PDB_CLR_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) & ~(value)))
+#define PDB_TOG_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_INT bitfields
+ */
+
+/*!
+ * @name Register PDB_INT, field INT[15:0] (RW)
+ *
+ * Specifies the interval value for DAC interval trigger. DAC interval trigger
+ * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
+ * Reading this field returns the value of internal register that is effective
+ * for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INT_INT field. */
+#define PDB_RD_INT_INT(base, index) ((PDB_INT_REG(base, index) & PDB_INT_INT_MASK) >> PDB_INT_INT_SHIFT)
+#define PDB_BRD_INT_INT(base, index) (PDB_RD_INT_INT(base, index))
+
+/*! @brief Set the INT field to a new value. */
+#define PDB_WR_INT_INT(base, index, value) (PDB_RMW_INT(base, index, PDB_INT_INT_MASK, PDB_INT_INT(value)))
+#define PDB_BWR_INT_INT(base, index, value) (PDB_WR_INT_INT(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_POEN - Pulse-Out n Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_POEN - Pulse-Out n Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_POEN register
+ */
+/*@{*/
+#define PDB_RD_POEN(base)        (PDB_POEN_REG(base))
+#define PDB_WR_POEN(base, value) (PDB_POEN_REG(base) = (value))
+#define PDB_RMW_POEN(base, mask, value) (PDB_WR_POEN(base, (PDB_RD_POEN(base) & ~(mask)) | (value)))
+#define PDB_SET_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) |  (value)))
+#define PDB_CLR_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) & ~(value)))
+#define PDB_TOG_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_POEN bitfields
+ */
+
+/*!
+ * @name Register PDB_POEN, field POEN[7:0] (RW)
+ *
+ * Enables the pulse output. Only lower Y bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB Pulse-Out disabled
+ * - 0b00000001 - PDB Pulse-Out enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_POEN_POEN field. */
+#define PDB_RD_POEN_POEN(base) ((PDB_POEN_REG(base) & PDB_POEN_POEN_MASK) >> PDB_POEN_POEN_SHIFT)
+#define PDB_BRD_POEN_POEN(base) (PDB_RD_POEN_POEN(base))
+
+/*! @brief Set the POEN field to a new value. */
+#define PDB_WR_POEN_POEN(base, value) (PDB_RMW_POEN(base, PDB_POEN_POEN_MASK, PDB_POEN_POEN(value)))
+#define PDB_BWR_POEN_POEN(base, value) (PDB_WR_POEN_POEN(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_PODLY - Pulse-Out n Delay register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_PODLY - Pulse-Out n Delay register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_PODLY register
+ */
+/*@{*/
+#define PDB_RD_PODLY(base, index) (PDB_PODLY_REG(base, index))
+#define PDB_WR_PODLY(base, index, value) (PDB_PODLY_REG(base, index) = (value))
+#define PDB_RMW_PODLY(base, index, mask, value) (PDB_WR_PODLY(base, index, (PDB_RD_PODLY(base, index) & ~(mask)) | (value)))
+#define PDB_SET_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) |  (value)))
+#define PDB_CLR_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) & ~(value)))
+#define PDB_TOG_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_PODLY bitfields
+ */
+
+/*!
+ * @name Register PDB_PODLY, field DLY2[15:0] (RW)
+ *
+ * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
+ * low when the PDB counter is equal to the DLY2. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_PODLY_DLY2 field. */
+#define PDB_RD_PODLY_DLY2(base, index) ((PDB_PODLY_REG(base, index) & PDB_PODLY_DLY2_MASK) >> PDB_PODLY_DLY2_SHIFT)
+#define PDB_BRD_PODLY_DLY2(base, index) (PDB_RD_PODLY_DLY2(base, index))
+
+/*! @brief Set the DLY2 field to a new value. */
+#define PDB_WR_PODLY_DLY2(base, index, value) (PDB_RMW_PODLY(base, index, PDB_PODLY_DLY2_MASK, PDB_PODLY_DLY2(value)))
+#define PDB_BWR_PODLY_DLY2(base, index, value) (PDB_WR_PODLY_DLY2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_PODLY, field DLY1[31:16] (RW)
+ *
+ * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
+ * high when the PDB counter is equal to the DLY1. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_PODLY_DLY1 field. */
+#define PDB_RD_PODLY_DLY1(base, index) ((PDB_PODLY_REG(base, index) & PDB_PODLY_DLY1_MASK) >> PDB_PODLY_DLY1_SHIFT)
+#define PDB_BRD_PODLY_DLY1(base, index) (PDB_RD_PODLY_DLY1(base, index))
+
+/*! @brief Set the DLY1 field to a new value. */
+#define PDB_WR_PODLY_DLY1(base, index, value) (PDB_RMW_PODLY(base, index, PDB_PODLY_DLY1_MASK, PDB_PODLY_DLY1(value)))
+#define PDB_BWR_PODLY_DLY1(base, index, value) (PDB_WR_PODLY_DLY1(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 PIT
+ *
+ * Periodic Interrupt Timer
+ *
+ * Registers defined in this header file:
+ * - PIT_MCR - PIT Module Control Register
+ * - PIT_LDVAL - Timer Load Value Register
+ * - PIT_CVAL - Current Timer Value Register
+ * - PIT_TCTRL - Timer Control Register
+ * - PIT_TFLG - Timer Flag Register
+ */
+
+#define PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
+#define PIT_IDX (0U) /*!< Instance number for PIT. */
+
+/*******************************************************************************
+ * PIT_MCR - PIT Module Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_MCR - PIT Module Control Register (RW)
+ *
+ * Reset value: 0x00000006U
+ *
+ * This register enables or disables the PIT timer clocks and controls the
+ * timers when the PIT enters the Debug mode.
+ */
+/*!
+ * @name Constants and macros for entire PIT_MCR register
+ */
+/*@{*/
+#define PIT_RD_MCR(base)         (PIT_MCR_REG(base))
+#define PIT_WR_MCR(base, value)  (PIT_MCR_REG(base) = (value))
+#define PIT_RMW_MCR(base, mask, value) (PIT_WR_MCR(base, (PIT_RD_MCR(base) & ~(mask)) | (value)))
+#define PIT_SET_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) |  (value)))
+#define PIT_CLR_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) & ~(value)))
+#define PIT_TOG_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_MCR bitfields
+ */
+
+/*!
+ * @name Register PIT_MCR, field FRZ[0] (RW)
+ *
+ * Allows the timers to be stopped when the device enters the Debug mode.
+ *
+ * Values:
+ * - 0b0 - Timers continue to run in Debug mode.
+ * - 0b1 - Timers are stopped in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_FRZ field. */
+#define PIT_RD_MCR_FRZ(base) ((PIT_MCR_REG(base) & PIT_MCR_FRZ_MASK) >> PIT_MCR_FRZ_SHIFT)
+#define PIT_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define PIT_WR_MCR_FRZ(base, value) (PIT_RMW_MCR(base, PIT_MCR_FRZ_MASK, PIT_MCR_FRZ(value)))
+#define PIT_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_MCR, field MDIS[1] (RW)
+ *
+ * Disables the standard timers. This field must be enabled before any other
+ * setup is done.
+ *
+ * Values:
+ * - 0b0 - Clock for standard PIT timers is enabled.
+ * - 0b1 - Clock for standard PIT timers is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_MDIS field. */
+#define PIT_RD_MCR_MDIS(base) ((PIT_MCR_REG(base) & PIT_MCR_MDIS_MASK) >> PIT_MCR_MDIS_SHIFT)
+#define PIT_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define PIT_WR_MCR_MDIS(base, value) (PIT_RMW_MCR(base, PIT_MCR_MDIS_MASK, PIT_MCR_MDIS(value)))
+#define PIT_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_LDVAL - Timer Load Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_LDVAL - Timer Load Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers select the timeout period for the timer interrupts.
+ */
+/*!
+ * @name Constants and macros for entire PIT_LDVAL register
+ */
+/*@{*/
+#define PIT_RD_LDVAL(base, index) (PIT_LDVAL_REG(base, index))
+#define PIT_WR_LDVAL(base, index, value) (PIT_LDVAL_REG(base, index) = (value))
+#define PIT_RMW_LDVAL(base, index, mask, value) (PIT_WR_LDVAL(base, index, (PIT_RD_LDVAL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) |  (value)))
+#define PIT_CLR_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) & ~(value)))
+#define PIT_TOG_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_CVAL - Current Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_CVAL - Current Timer Value Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the current timer position.
+ */
+/*!
+ * @name Constants and macros for entire PIT_CVAL register
+ */
+/*@{*/
+#define PIT_RD_CVAL(base, index) (PIT_CVAL_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TCTRL - Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TCTRL - Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the control bits for each timer.
+ */
+/*!
+ * @name Constants and macros for entire PIT_TCTRL register
+ */
+/*@{*/
+#define PIT_RD_TCTRL(base, index) (PIT_TCTRL_REG(base, index))
+#define PIT_WR_TCTRL(base, index, value) (PIT_TCTRL_REG(base, index) = (value))
+#define PIT_RMW_TCTRL(base, index, mask, value) (PIT_WR_TCTRL(base, index, (PIT_RD_TCTRL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) |  (value)))
+#define PIT_CLR_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) & ~(value)))
+#define PIT_TOG_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TCTRL bitfields
+ */
+
+/*!
+ * @name Register PIT_TCTRL, field TEN[0] (RW)
+ *
+ * Enables or disables the timer.
+ *
+ * Values:
+ * - 0b0 - Timer n is disabled.
+ * - 0b1 - Timer n is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TEN field. */
+#define PIT_RD_TCTRL_TEN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TEN_MASK) >> PIT_TCTRL_TEN_SHIFT)
+#define PIT_BRD_TCTRL_TEN(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT))
+
+/*! @brief Set the TEN field to a new value. */
+#define PIT_WR_TCTRL_TEN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TEN_MASK, PIT_TCTRL_TEN(value)))
+#define PIT_BWR_TCTRL_TEN(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field TIE[1] (RW)
+ *
+ * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
+ * will immediately cause an interrupt event. To avoid this, the associated
+ * TFLGn[TIF] must be cleared first.
+ *
+ * Values:
+ * - 0b0 - Interrupt requests from Timer n are disabled.
+ * - 0b1 - Interrupt will be requested whenever TIF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TIE field. */
+#define PIT_RD_TCTRL_TIE(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TIE_MASK) >> PIT_TCTRL_TIE_SHIFT)
+#define PIT_BRD_TCTRL_TIE(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define PIT_WR_TCTRL_TIE(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TIE_MASK, PIT_TCTRL_TIE(value)))
+#define PIT_BWR_TCTRL_TIE(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field CHN[2] (RW)
+ *
+ * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
+ * Timer 0 cannot be chained.
+ *
+ * Values:
+ * - 0b0 - Timer is not chained.
+ * - 0b1 - Timer is chained to previous timer. For example, for Channel 2, if
+ *     this field is set, Timer 2 is chained to Timer 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_CHN field. */
+#define PIT_RD_TCTRL_CHN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_CHN_MASK) >> PIT_TCTRL_CHN_SHIFT)
+#define PIT_BRD_TCTRL_CHN(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT))
+
+/*! @brief Set the CHN field to a new value. */
+#define PIT_WR_TCTRL_CHN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_CHN_MASK, PIT_TCTRL_CHN(value)))
+#define PIT_BWR_TCTRL_CHN(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TFLG - Timer Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TFLG - Timer Flag Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers hold the PIT interrupt flags.
+ */
+/*!
+ * @name Constants and macros for entire PIT_TFLG register
+ */
+/*@{*/
+#define PIT_RD_TFLG(base, index) (PIT_TFLG_REG(base, index))
+#define PIT_WR_TFLG(base, index, value) (PIT_TFLG_REG(base, index) = (value))
+#define PIT_RMW_TFLG(base, index, mask, value) (PIT_WR_TFLG(base, index, (PIT_RD_TFLG(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) |  (value)))
+#define PIT_CLR_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) & ~(value)))
+#define PIT_TOG_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TFLG bitfields
+ */
+
+/*!
+ * @name Register PIT_TFLG, field TIF[0] (W1C)
+ *
+ * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
+ * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
+ * interrupt request.
+ *
+ * Values:
+ * - 0b0 - Timeout has not yet occurred.
+ * - 0b1 - Timeout has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TFLG_TIF field. */
+#define PIT_RD_TFLG_TIF(base, index) ((PIT_TFLG_REG(base, index) & PIT_TFLG_TIF_MASK) >> PIT_TFLG_TIF_SHIFT)
+#define PIT_BRD_TFLG_TIF(base, index) (BITBAND_ACCESS32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT))
+
+/*! @brief Set the TIF field to a new value. */
+#define PIT_WR_TFLG_TIF(base, index, value) (PIT_RMW_TFLG(base, index, PIT_TFLG_TIF_MASK, PIT_TFLG_TIF(value)))
+#define PIT_BWR_TFLG_TIF(base, index, value) (BITBAND_ACCESS32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PMC
+ *
+ * Power Management Controller
+ *
+ * Registers defined in this header file:
+ * - PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ * - PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ * - PMC_REGSC - Regulator Status And Control register
+ */
+
+#define PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
+#define PMC_IDX (0U) /*!< Instance number for PMC. */
+
+/*******************************************************************************
+ * PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
+ *
+ * Reset value: 0x10U
+ *
+ * This register contains status and control bits to support the low voltage
+ * detect function. This register should be written during the reset initialization
+ * program to set the desired controls even if the desired settings are the same
+ * as the reset settings. While the device is in the very low power or low
+ * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
+ * systems that must have LVD always on, configure the Power Mode Protection
+ * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
+ * low leakage modes from being enabled. See the device's data sheet for the
+ * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
+ * register's other bits are reset on Chip Reset Not VLLS. For more information
+ * about these reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC1 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC1(base)      (PMC_LVDSC1_REG(base))
+#define PMC_WR_LVDSC1(base, value) (PMC_LVDSC1_REG(base) = (value))
+#define PMC_RMW_LVDSC1(base, mask, value) (PMC_WR_LVDSC1(base, (PMC_RD_LVDSC1(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) |  (value)))
+#define PMC_CLR_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) & ~(value)))
+#define PMC_TOG_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC1 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
+ *
+ * Selects the LVD trip point voltage (V LVD ).
+ *
+ * Values:
+ * - 0b00 - Low trip point selected (V LVD = V LVDL )
+ * - 0b01 - High trip point selected (V LVD = V LVDH )
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
+#define PMC_RD_LVDSC1_LVDV(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDV_MASK) >> PMC_LVDSC1_LVDV_SHIFT)
+#define PMC_BRD_LVDSC1_LVDV(base) (PMC_RD_LVDSC1_LVDV(base))
+
+/*! @brief Set the LVDV field to a new value. */
+#define PMC_WR_LVDSC1_LVDV(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDV_MASK, PMC_LVDSC1_LVDV(value)))
+#define PMC_BWR_LVDSC1_LVDV(base, value) (PMC_WR_LVDSC1_LVDV(base, value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
+ *
+ * This write-once bit enables LVDF events to generate a hardware reset.
+ * Additional writes are ignored.
+ *
+ * Values:
+ * - 0b0 - LVDF does not generate hardware resets
+ * - 0b1 - Force an MCU reset when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
+#define PMC_RD_LVDSC1_LVDRE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDRE_MASK) >> PMC_LVDSC1_LVDRE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDRE(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT))
+
+/*! @brief Set the LVDRE field to a new value. */
+#define PMC_WR_LVDSC1_LVDRE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDRE_MASK, PMC_LVDSC1_LVDRE(value)))
+#define PMC_BWR_LVDSC1_LVDRE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVDF.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupt disabled (use polling)
+ * - 0b1 - Request a hardware interrupt when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
+#define PMC_RD_LVDSC1_LVDIE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDIE_MASK) >> PMC_LVDSC1_LVDIE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDIE(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT))
+
+/*! @brief Set the LVDIE field to a new value. */
+#define PMC_WR_LVDSC1_LVDIE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDIE_MASK, PMC_LVDSC1_LVDIE(value)))
+#define PMC_BWR_LVDSC1_LVDIE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage detection errors.
+ * Write 1 to clear LVDF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVDACK field to a new value. */
+#define PMC_WR_LVDSC1_LVDACK(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDACK_MASK, PMC_LVDSC1_LVDACK(value)))
+#define PMC_BWR_LVDSC1_LVDACK(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage detect event.
+ *
+ * Values:
+ * - 0b0 - Low-voltage event not detected
+ * - 0b1 - Low-voltage event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
+#define PMC_RD_LVDSC1_LVDF(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDF_MASK) >> PMC_LVDSC1_LVDF_SHIFT)
+#define PMC_BRD_LVDSC1_LVDF(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains status and control bits to support the low voltage
+ * warning function. While the device is in the very low power or low leakage modes,
+ * the LVD system is disabled regardless of LVDSC2 settings. See the device's
+ * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
+ * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
+ * register are reset on Chip Reset Not VLLS. For more information about these
+ * reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC2 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC2(base)      (PMC_LVDSC2_REG(base))
+#define PMC_WR_LVDSC2(base, value) (PMC_LVDSC2_REG(base) = (value))
+#define PMC_RMW_LVDSC2(base, mask, value) (PMC_WR_LVDSC2(base, (PMC_RD_LVDSC2(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) |  (value)))
+#define PMC_CLR_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) & ~(value)))
+#define PMC_TOG_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC2 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
+ *
+ * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
+ * depends on LVDSC1[LVDV].
+ *
+ * Values:
+ * - 0b00 - Low trip point selected (VLVW = VLVW1)
+ * - 0b01 - Mid 1 trip point selected (VLVW = VLVW2)
+ * - 0b10 - Mid 2 trip point selected (VLVW = VLVW3)
+ * - 0b11 - High trip point selected (VLVW = VLVW4)
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
+#define PMC_RD_LVDSC2_LVWV(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWV_MASK) >> PMC_LVDSC2_LVWV_SHIFT)
+#define PMC_BRD_LVDSC2_LVWV(base) (PMC_RD_LVDSC2_LVWV(base))
+
+/*! @brief Set the LVWV field to a new value. */
+#define PMC_WR_LVDSC2_LVWV(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWV_MASK, PMC_LVDSC2_LVWV(value)))
+#define PMC_BWR_LVDSC2_LVWV(base, value) (PMC_WR_LVDSC2_LVWV(base, value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVWF.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupt disabled (use polling)
+ * - 0b1 - Request a hardware interrupt when LVWF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
+#define PMC_RD_LVDSC2_LVWIE(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWIE_MASK) >> PMC_LVDSC2_LVWIE_SHIFT)
+#define PMC_BRD_LVDSC2_LVWIE(base) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT))
+
+/*! @brief Set the LVWIE field to a new value. */
+#define PMC_WR_LVDSC2_LVWIE(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWIE_MASK, PMC_LVDSC2_LVWIE(value)))
+#define PMC_BWR_LVDSC2_LVWIE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage warning errors.
+ * Write 1 to clear LVWF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVWACK field to a new value. */
+#define PMC_WR_LVDSC2_LVWACK(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWACK_MASK, PMC_LVDSC2_LVWACK(value)))
+#define PMC_BWR_LVDSC2_LVWACK(base, value) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage warning event. LVWF is
+ * set when VSupply transitions below the trip point, or after reset and VSupply is
+ * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
+ * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
+ * LVWACK first.
+ *
+ * Values:
+ * - 0b0 - Low-voltage warning event not detected
+ * - 0b1 - Low-voltage warning event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
+#define PMC_RD_LVDSC2_LVWF(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWF_MASK) >> PMC_LVDSC2_LVWF_SHIFT)
+#define PMC_BRD_LVDSC2_LVWF(base) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_REGSC - Regulator Status And Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_REGSC - Regulator Status And Control register (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * The PMC contains an internal voltage regulator. The voltage regulator design
+ * uses a bandgap reference that is also available through a buffer as input to
+ * certain internal peripherals, such as the CMP and ADC. The internal regulator
+ * provides a status bit (REGONS) indicating the regulator is in run regulation.
+ * This register is reset on Chip Reset Not VLLS and by reset types that trigger
+ * Chip Reset not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire PMC_REGSC register
+ */
+/*@{*/
+#define PMC_RD_REGSC(base)       (PMC_REGSC_REG(base))
+#define PMC_WR_REGSC(base, value) (PMC_REGSC_REG(base) = (value))
+#define PMC_RMW_REGSC(base, mask, value) (PMC_WR_REGSC(base, (PMC_RD_REGSC(base) & ~(mask)) | (value)))
+#define PMC_SET_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) |  (value)))
+#define PMC_CLR_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) & ~(value)))
+#define PMC_TOG_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_REGSC bitfields
+ */
+
+/*!
+ * @name Register PMC_REGSC, field BGBE[0] (RW)
+ *
+ * Enables the bandgap buffer.
+ *
+ * Values:
+ * - 0b0 - Bandgap buffer not enabled
+ * - 0b1 - Bandgap buffer enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGBE field. */
+#define PMC_RD_REGSC_BGBE(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGBE_MASK) >> PMC_REGSC_BGBE_SHIFT)
+#define PMC_BRD_REGSC_BGBE(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT))
+
+/*! @brief Set the BGBE field to a new value. */
+#define PMC_WR_REGSC_BGBE(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGBE_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGBE(value)))
+#define PMC_BWR_REGSC_BGBE(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field REGONS[2] (RO)
+ *
+ * This read-only field provides the current status of the internal voltage
+ * regulator.
+ *
+ * Values:
+ * - 0b0 - Regulator is in stop regulation or in transition to/from it
+ * - 0b1 - Regulator is in run regulation
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_REGONS field. */
+#define PMC_RD_REGSC_REGONS(base) ((PMC_REGSC_REG(base) & PMC_REGSC_REGONS_MASK) >> PMC_REGSC_REGONS_SHIFT)
+#define PMC_BRD_REGSC_REGONS(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_REGONS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field ACKISO[3] (W1C)
+ *
+ * Reading this field indicates whether certain peripherals and the I/O pads are
+ * in a latched state as a result of having been in a VLLS mode. Writing 1 to
+ * this field when it is set releases the I/O pads and certain peripherals to their
+ * normal run mode state. After recovering from a VLLS mode, user should restore
+ * chip configuration before clearing ACKISO. In particular, pin configuration
+ * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
+ * being falsely set when ACKISO is cleared.
+ *
+ * Values:
+ * - 0b0 - Peripherals and I/O pads are in normal run state.
+ * - 0b1 - Certain peripherals and I/O pads are in an isolated and latched state.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_ACKISO field. */
+#define PMC_RD_REGSC_ACKISO(base) ((PMC_REGSC_REG(base) & PMC_REGSC_ACKISO_MASK) >> PMC_REGSC_ACKISO_SHIFT)
+#define PMC_BRD_REGSC_ACKISO(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT))
+
+/*! @brief Set the ACKISO field to a new value. */
+#define PMC_WR_REGSC_ACKISO(base, value) (PMC_RMW_REGSC(base, PMC_REGSC_ACKISO_MASK, PMC_REGSC_ACKISO(value)))
+#define PMC_BWR_REGSC_ACKISO(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field BGEN[4] (RW)
+ *
+ * BGEN controls whether the bandgap is enabled in lower power modes of
+ * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
+ * reference in low power modes of operation, set BGEN to continue to enable the
+ * bandgap operation. When the bandgap voltage reference is not needed in low
+ * power modes, clear BGEN to avoid excess power consumption.
+ *
+ * Values:
+ * - 0b0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
+ * - 0b1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGEN field. */
+#define PMC_RD_REGSC_BGEN(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGEN_MASK) >> PMC_REGSC_BGEN_SHIFT)
+#define PMC_BRD_REGSC_BGEN(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT))
+
+/*! @brief Set the BGEN field to a new value. */
+#define PMC_WR_REGSC_BGEN(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGEN_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGEN(value)))
+#define PMC_BWR_REGSC_BGEN(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PORT
+ *
+ * Pin Control and Interrupts
+ *
+ * Registers defined in this header file:
+ * - PORT_PCR - Pin Control Register n
+ * - PORT_GPCLR - Global Pin Control Low Register
+ * - PORT_GPCHR - Global Pin Control High Register
+ * - PORT_ISFR - Interrupt Status Flag Register
+ * - PORT_DFER - Digital Filter Enable Register
+ * - PORT_DFCR - Digital Filter Clock Register
+ * - PORT_DFWR - Digital Filter Width Register
+ */
+
+#define PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
+#define PORTA_IDX (0U) /*!< Instance number for PORTA. */
+#define PORTB_IDX (1U) /*!< Instance number for PORTB. */
+#define PORTC_IDX (2U) /*!< Instance number for PORTC. */
+#define PORTD_IDX (3U) /*!< Instance number for PORTD. */
+#define PORTE_IDX (4U) /*!< Instance number for PORTE. */
+
+/*******************************************************************************
+ * PORT_PCR - Pin Control Register n
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_PCR - Pin Control Register n (RW)
+ *
+ * Reset value: 0x00000746U
+ *
+ * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
+ * this device. See the GPIO Configuration section for details on the available
+ * functions for each pin. Do not modify pin configuration registers associated
+ * with pins not available in your selected package. All unbonded pins not
+ * available in your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire PORT_PCR register
+ */
+/*@{*/
+#define PORT_RD_PCR(base, index) (PORT_PCR_REG(base, index))
+#define PORT_WR_PCR(base, index, value) (PORT_PCR_REG(base, index) = (value))
+#define PORT_RMW_PCR(base, index, mask, value) (PORT_WR_PCR(base, index, (PORT_RD_PCR(base, index) & ~(mask)) | (value)))
+#define PORT_SET_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) |  (value)))
+#define PORT_CLR_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) & ~(value)))
+#define PORT_TOG_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_PCR bitfields
+ */
+
+/*!
+ * @name Register PORT_PCR, field PS[0] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Internal pulldown resistor is enabled on the corresponding pin, if
+ *     the corresponding PE field is set.
+ * - 0b1 - Internal pullup resistor is enabled on the corresponding pin, if the
+ *     corresponding PE field is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PS field. */
+#define PORT_RD_PCR_PS(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PS_MASK) >> PORT_PCR_PS_SHIFT)
+#define PORT_BRD_PCR_PS(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT))
+
+/*! @brief Set the PS field to a new value. */
+#define PORT_WR_PCR_PS(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PS_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PS(value)))
+#define PORT_BWR_PCR_PS(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PE[1] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Internal pullup or pulldown resistor is not enabled on the
+ *     corresponding pin.
+ * - 0b1 - Internal pullup or pulldown resistor is enabled on the corresponding
+ *     pin, if the pin is configured as a digital input.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PE field. */
+#define PORT_RD_PCR_PE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PE_MASK) >> PORT_PCR_PE_SHIFT)
+#define PORT_BRD_PCR_PE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT))
+
+/*! @brief Set the PE field to a new value. */
+#define PORT_WR_PCR_PE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PE(value)))
+#define PORT_BWR_PCR_PE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field SRE[2] (RW)
+ *
+ * Slew rate configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Fast slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ * - 0b1 - Slow slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_SRE field. */
+#define PORT_RD_PCR_SRE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_SRE_MASK) >> PORT_PCR_SRE_SHIFT)
+#define PORT_BRD_PCR_SRE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT))
+
+/*! @brief Set the SRE field to a new value. */
+#define PORT_WR_PCR_SRE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_SRE(value)))
+#define PORT_BWR_PCR_SRE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PFE[4] (RW)
+ *
+ * Passive filter configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Passive input filter is disabled on the corresponding pin.
+ * - 0b1 - Passive input filter is enabled on the corresponding pin, if the pin
+ *     is configured as a digital input. Refer to the device data sheet for
+ *     filter characteristics.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PFE field. */
+#define PORT_RD_PCR_PFE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PFE_MASK) >> PORT_PCR_PFE_SHIFT)
+#define PORT_BRD_PCR_PFE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT))
+
+/*! @brief Set the PFE field to a new value. */
+#define PORT_WR_PCR_PFE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PFE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PFE(value)))
+#define PORT_BWR_PCR_PFE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ODE[5] (RW)
+ *
+ * Open drain configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Open drain output is disabled on the corresponding pin.
+ * - 0b1 - Open drain output is enabled on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ODE field. */
+#define PORT_RD_PCR_ODE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ODE_MASK) >> PORT_PCR_ODE_SHIFT)
+#define PORT_BRD_PCR_ODE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ODE_SHIFT))
+
+/*! @brief Set the ODE field to a new value. */
+#define PORT_WR_PCR_ODE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_ODE(value)))
+#define PORT_BWR_PCR_ODE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field DSE[6] (RW)
+ *
+ * Drive strength configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Low drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ * - 0b1 - High drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_DSE field. */
+#define PORT_RD_PCR_DSE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_DSE_MASK) >> PORT_PCR_DSE_SHIFT)
+#define PORT_BRD_PCR_DSE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT))
+
+/*! @brief Set the DSE field to a new value. */
+#define PORT_WR_PCR_DSE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_DSE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_DSE(value)))
+#define PORT_BWR_PCR_DSE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field MUX[10:8] (RW)
+ *
+ * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
+ * reserved and may result in configuring the pin for a different pin muxing
+ * slot. The corresponding pin is configured in the following pin muxing slot as
+ * follows:
+ *
+ * Values:
+ * - 0b000 - Pin disabled (analog).
+ * - 0b001 - Alternative 1 (GPIO).
+ * - 0b010 - Alternative 2 (chip-specific).
+ * - 0b011 - Alternative 3 (chip-specific).
+ * - 0b100 - Alternative 4 (chip-specific).
+ * - 0b101 - Alternative 5 (chip-specific).
+ * - 0b110 - Alternative 6 (chip-specific).
+ * - 0b111 - Alternative 7 (chip-specific).
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_MUX field. */
+#define PORT_RD_PCR_MUX(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_MUX_MASK) >> PORT_PCR_MUX_SHIFT)
+#define PORT_BRD_PCR_MUX(base, index) (PORT_RD_PCR_MUX(base, index))
+
+/*! @brief Set the MUX field to a new value. */
+#define PORT_WR_PCR_MUX(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_MUX_MASK | PORT_PCR_ISF_MASK), PORT_PCR_MUX(value)))
+#define PORT_BWR_PCR_MUX(base, index, value) (PORT_WR_PCR_MUX(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field LK[15] (RW)
+ *
+ * Values:
+ * - 0b0 - Pin Control Register fields [15:0] are not locked.
+ * - 0b1 - Pin Control Register fields [15:0] are locked and cannot be updated
+ *     until the next system reset.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_LK field. */
+#define PORT_RD_PCR_LK(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_LK_MASK) >> PORT_PCR_LK_SHIFT)
+#define PORT_BRD_PCR_LK(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_LK_SHIFT))
+
+/*! @brief Set the LK field to a new value. */
+#define PORT_WR_PCR_LK(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_LK_MASK | PORT_PCR_ISF_MASK), PORT_PCR_LK(value)))
+#define PORT_BWR_PCR_LK(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_LK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field IRQC[19:16] (RW)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * corresponding pin is configured to generate interrupt/DMA request as follows:
+ *
+ * Values:
+ * - 0b0000 - Interrupt/DMA request disabled.
+ * - 0b0001 - DMA request on rising edge.
+ * - 0b0010 - DMA request on falling edge.
+ * - 0b0011 - DMA request on either edge.
+ * - 0b1000 - Interrupt when logic 0.
+ * - 0b1001 - Interrupt on rising-edge.
+ * - 0b1010 - Interrupt on falling-edge.
+ * - 0b1011 - Interrupt on either edge.
+ * - 0b1100 - Interrupt when logic 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_IRQC field. */
+#define PORT_RD_PCR_IRQC(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_IRQC_MASK) >> PORT_PCR_IRQC_SHIFT)
+#define PORT_BRD_PCR_IRQC(base, index) (PORT_RD_PCR_IRQC(base, index))
+
+/*! @brief Set the IRQC field to a new value. */
+#define PORT_WR_PCR_IRQC(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_IRQC_MASK | PORT_PCR_ISF_MASK), PORT_PCR_IRQC(value)))
+#define PORT_BWR_PCR_IRQC(base, index, value) (PORT_WR_PCR_IRQC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ISF[24] (W1C)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Configured interrupt is not detected.
+ * - 0b1 - Configured interrupt is detected. If the pin is configured to
+ *     generate a DMA request, then the corresponding flag will be cleared automatically
+ *     at the completion of the requested DMA transfer. Otherwise, the flag
+ *     remains set until a logic 1 is written to the flag. If the pin is configured
+ *     for a level sensitive interrupt and the pin remains asserted, then the flag
+ *     is set again immediately after it is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ISF field. */
+#define PORT_RD_PCR_ISF(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ISF_MASK) >> PORT_PCR_ISF_SHIFT)
+#define PORT_BRD_PCR_ISF(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT))
+
+/*! @brief Set the ISF field to a new value. */
+#define PORT_WR_PCR_ISF(base, index, value) (PORT_RMW_PCR(base, index, PORT_PCR_ISF_MASK, PORT_PCR_ISF(value)))
+#define PORT_BWR_PCR_ISF(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCLR - Global Pin Control Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCLR - Global Pin Control Low Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCLR register
+ */
+/*@{*/
+#define PORT_RD_GPCLR(base)      (PORT_GPCLR_REG(base))
+#define PORT_WR_GPCLR(base, value) (PORT_GPCLR_REG(base) = (value))
+#define PORT_RMW_GPCLR(base, mask, value) (PORT_WR_GPCLR(base, (PORT_RD_GPCLR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCLR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCLR_GPWD(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWD_MASK, PORT_GPCLR_GPWD(value)))
+#define PORT_BWR_GPCLR_GPWD(base, value) (PORT_WR_GPCLR_GPWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
+ *     the value in GPWD.
+ * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
+ *     value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCLR_GPWE(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWE_MASK, PORT_GPCLR_GPWE(value)))
+#define PORT_BWR_GPCLR_GPWE(base, value) (PORT_WR_GPCLR_GPWE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCHR - Global Pin Control High Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCHR - Global Pin Control High Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCHR register
+ */
+/*@{*/
+#define PORT_RD_GPCHR(base)      (PORT_GPCHR_REG(base))
+#define PORT_WR_GPCHR(base, value) (PORT_GPCHR_REG(base) = (value))
+#define PORT_RMW_GPCHR(base, mask, value) (PORT_WR_GPCHR(base, (PORT_RD_GPCHR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCHR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCHR_GPWD(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWD_MASK, PORT_GPCHR_GPWD(value)))
+#define PORT_BWR_GPCHR_GPWD(base, value) (PORT_WR_GPCHR_GPWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
+ *     the value in GPWD.
+ * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
+ *     value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCHR_GPWE(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWE_MASK, PORT_GPCHR_GPWE(value)))
+#define PORT_BWR_GPCHR_GPWE(base, value) (PORT_WR_GPCHR_GPWE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_ISFR - Interrupt Status Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_ISFR - Interrupt Status Flag Register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * Interrupt Status Flag for each pin is also visible in the corresponding Pin
+ * Control Register, and each flag can be cleared in either location.
+ */
+/*!
+ * @name Constants and macros for entire PORT_ISFR register
+ */
+/*@{*/
+#define PORT_RD_ISFR(base)       (PORT_ISFR_REG(base))
+#define PORT_WR_ISFR(base, value) (PORT_ISFR_REG(base) = (value))
+#define PORT_RMW_ISFR(base, mask, value) (PORT_WR_ISFR(base, (PORT_RD_ISFR(base) & ~(mask)) | (value)))
+#define PORT_SET_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) |  (value)))
+#define PORT_CLR_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) & ~(value)))
+#define PORT_TOG_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFER - Digital Filter Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFER - Digital Filter Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The corresponding bit is read only for pins that do not support a digital
+ * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
+ * the pins that support digital filter. The digital filter configuration is valid
+ * in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFER register
+ */
+/*@{*/
+#define PORT_RD_DFER(base)       (PORT_DFER_REG(base))
+#define PORT_WR_DFER(base, value) (PORT_DFER_REG(base) = (value))
+#define PORT_RMW_DFER(base, mask, value) (PORT_WR_DFER(base, (PORT_RD_DFER(base) & ~(mask)) | (value)))
+#define PORT_SET_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) |  (value)))
+#define PORT_CLR_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) & ~(value)))
+#define PORT_TOG_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFCR - Digital Filter Clock Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFCR - Digital Filter Clock Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFCR register
+ */
+/*@{*/
+#define PORT_RD_DFCR(base)       (PORT_DFCR_REG(base))
+#define PORT_WR_DFCR(base, value) (PORT_DFCR_REG(base) = (value))
+#define PORT_RMW_DFCR(base, mask, value) (PORT_WR_DFCR(base, (PORT_RD_DFCR(base) & ~(mask)) | (value)))
+#define PORT_SET_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) |  (value)))
+#define PORT_CLR_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) & ~(value)))
+#define PORT_TOG_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_DFCR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFCR, field CS[0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the clock source for the digital input filters. Changing the filter
+ * clock source must be done only when all digital filters are disabled.
+ *
+ * Values:
+ * - 0b0 - Digital filters are clocked by the bus clock.
+ * - 0b1 - Digital filters are clocked by the 1 kHz LPO clock.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_DFCR_CS field. */
+#define PORT_RD_DFCR_CS(base) ((PORT_DFCR_REG(base) & PORT_DFCR_CS_MASK) >> PORT_DFCR_CS_SHIFT)
+#define PORT_BRD_DFCR_CS(base) (BITBAND_ACCESS32(&PORT_DFCR_REG(base), PORT_DFCR_CS_SHIFT))
+
+/*! @brief Set the CS field to a new value. */
+#define PORT_WR_DFCR_CS(base, value) (PORT_RMW_DFCR(base, PORT_DFCR_CS_MASK, PORT_DFCR_CS(value)))
+#define PORT_BWR_DFCR_CS(base, value) (BITBAND_ACCESS32(&PORT_DFCR_REG(base), PORT_DFCR_CS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFWR - Digital Filter Width Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFWR - Digital Filter Width Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFWR register
+ */
+/*@{*/
+#define PORT_RD_DFWR(base)       (PORT_DFWR_REG(base))
+#define PORT_WR_DFWR(base, value) (PORT_DFWR_REG(base) = (value))
+#define PORT_RMW_DFWR(base, mask, value) (PORT_WR_DFWR(base, (PORT_RD_DFWR(base) & ~(mask)) | (value)))
+#define PORT_SET_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) |  (value)))
+#define PORT_CLR_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) & ~(value)))
+#define PORT_TOG_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_DFWR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFWR, field FILT[4:0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the maximum size of the glitches, in clock cycles, that the digital
+ * filter absorbs for the enabled digital filters. Glitches that are longer than
+ * this register setting will pass through the digital filter, and glitches that
+ * are equal to or less than this register setting are filtered. Changing the
+ * filter length must be done only after all filters are disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_DFWR_FILT field. */
+#define PORT_RD_DFWR_FILT(base) ((PORT_DFWR_REG(base) & PORT_DFWR_FILT_MASK) >> PORT_DFWR_FILT_SHIFT)
+#define PORT_BRD_DFWR_FILT(base) (PORT_RD_DFWR_FILT(base))
+
+/*! @brief Set the FILT field to a new value. */
+#define PORT_WR_DFWR_FILT(base, value) (PORT_RMW_DFWR(base, PORT_DFWR_FILT_MASK, PORT_DFWR_FILT(value)))
+#define PORT_BWR_DFWR_FILT(base, value) (PORT_WR_DFWR_FILT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 RCM
+ *
+ * Reset Control Module
+ *
+ * Registers defined in this header file:
+ * - RCM_SRS0 - System Reset Status Register 0
+ * - RCM_SRS1 - System Reset Status Register 1
+ * - RCM_RPFC - Reset Pin Filter Control register
+ * - RCM_RPFW - Reset Pin Filter Width register
+ * - RCM_MR - Mode Register
+ */
+
+#define RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */
+#define RCM_IDX (0U) /*!< Instance number for RCM. */
+
+/*******************************************************************************
+ * RCM_SRS0 - System Reset Status Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS0 - System Reset Status Register 0 (RO)
+ *
+ * Reset value: 0x82U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
+ * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS0 register
+ */
+/*@{*/
+#define RCM_RD_SRS0(base)        (RCM_SRS0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS0 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS0, field WAKEUP[0] (RO)
+ *
+ * Indicates a reset has been caused by an enabled LLWU module wakeup source
+ * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
+ * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
+ * mode causes a reset. This bit is cleared by any reset except WAKEUP.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by LLWU module wakeup source
+ * - 0b1 - Reset caused by LLWU module wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WAKEUP field. */
+#define RCM_RD_SRS0_WAKEUP(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WAKEUP_MASK) >> RCM_SRS0_WAKEUP_SHIFT)
+#define RCM_BRD_SRS0_WAKEUP(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_WAKEUP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LVD[1] (RO)
+ *
+ * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
+ * an LVD reset occurs. This field is also set by POR.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by LVD trip or POR
+ * - 0b1 - Reset caused by LVD trip or POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LVD field. */
+#define RCM_RD_SRS0_LVD(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LVD_MASK) >> RCM_SRS0_LVD_SHIFT)
+#define RCM_BRD_SRS0_LVD(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LVD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LOC[2] (RO)
+ *
+ * Indicates a reset has been caused by a loss of external clock. The MCG clock
+ * monitor must be enabled for a loss of clock to be detected. Refer to the
+ * detailed MCG description for information on enabling the clock monitor.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by a loss of external clock.
+ * - 0b1 - Reset caused by a loss of external clock.
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LOC field. */
+#define RCM_RD_SRS0_LOC(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOC_MASK) >> RCM_SRS0_LOC_SHIFT)
+#define RCM_BRD_SRS0_LOC(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LOC_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LOL[3] (RO)
+ *
+ * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
+ * MCG description for information on the loss-of-clock event.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by a loss of lock in the PLL
+ * - 0b1 - Reset caused by a loss of lock in the PLL
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LOL field. */
+#define RCM_RD_SRS0_LOL(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOL_MASK) >> RCM_SRS0_LOL_SHIFT)
+#define RCM_BRD_SRS0_LOL(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LOL_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field WDOG[5] (RO)
+ *
+ * Indicates a reset has been caused by the watchdog timer Computer Operating
+ * Properly (COP) timing out. This reset source can be blocked by disabling the COP
+ * watchdog: write 00 to SIM_COPCTRL[COPT].
+ *
+ * Values:
+ * - 0b0 - Reset not caused by watchdog timeout
+ * - 0b1 - Reset caused by watchdog timeout
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WDOG field. */
+#define RCM_RD_SRS0_WDOG(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WDOG_MASK) >> RCM_SRS0_WDOG_SHIFT)
+#define RCM_BRD_SRS0_WDOG(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_WDOG_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field PIN[6] (RO)
+ *
+ * Indicates a reset has been caused by an active-low level on the external
+ * RESET pin.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by external reset pin
+ * - 0b1 - Reset caused by external reset pin
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_PIN field. */
+#define RCM_RD_SRS0_PIN(base) ((RCM_SRS0_REG(base) & RCM_SRS0_PIN_MASK) >> RCM_SRS0_PIN_SHIFT)
+#define RCM_BRD_SRS0_PIN(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_PIN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field POR[7] (RO)
+ *
+ * Indicates a reset has been caused by the power-on detection logic. Because
+ * the internal supply voltage was ramping up at the time, the low-voltage reset
+ * (LVD) status bit is also set to indicate that the reset occurred while the
+ * internal supply was below the LVD threshold.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by POR
+ * - 0b1 - Reset caused by POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_POR field. */
+#define RCM_RD_SRS0_POR(base) ((RCM_SRS0_REG(base) & RCM_SRS0_POR_MASK) >> RCM_SRS0_POR_SHIFT)
+#define RCM_BRD_SRS0_POR(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_POR_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_SRS1 - System Reset Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS1 - System Reset Status Register 1 (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS1 register
+ */
+/*@{*/
+#define RCM_RD_SRS1(base)        (RCM_SRS1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS1 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS1, field JTAG[0] (RO)
+ *
+ * Indicates a reset has been caused by JTAG selection of certain IR codes:
+ * EZPORT, EXTEST, HIGHZ, and CLAMP.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by JTAG
+ * - 0b1 - Reset caused by JTAG
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_JTAG field. */
+#define RCM_RD_SRS1_JTAG(base) ((RCM_SRS1_REG(base) & RCM_SRS1_JTAG_MASK) >> RCM_SRS1_JTAG_SHIFT)
+#define RCM_BRD_SRS1_JTAG(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_JTAG_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field LOCKUP[1] (RO)
+ *
+ * Indicates a reset has been caused by the ARM core indication of a LOCKUP
+ * event.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by core LOCKUP event
+ * - 0b1 - Reset caused by core LOCKUP event
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_LOCKUP field. */
+#define RCM_RD_SRS1_LOCKUP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_LOCKUP_MASK) >> RCM_SRS1_LOCKUP_SHIFT)
+#define RCM_BRD_SRS1_LOCKUP(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_LOCKUP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SW[2] (RO)
+ *
+ * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
+ * Application Interrupt and Reset Control Register in the ARM core.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by software setting of SYSRESETREQ bit
+ * - 0b1 - Reset caused by software setting of SYSRESETREQ bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SW field. */
+#define RCM_RD_SRS1_SW(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SW_MASK) >> RCM_SRS1_SW_SHIFT)
+#define RCM_BRD_SRS1_SW(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_SW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field MDM_AP[3] (RO)
+ *
+ * Indicates a reset has been caused by the host debugger system setting of the
+ * System Reset Request bit in the MDM-AP Control Register.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by host debugger system setting of the System Reset
+ *     Request bit
+ * - 0b1 - Reset caused by host debugger system setting of the System Reset
+ *     Request bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_MDM_AP field. */
+#define RCM_RD_SRS1_MDM_AP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_MDM_AP_MASK) >> RCM_SRS1_MDM_AP_SHIFT)
+#define RCM_BRD_SRS1_MDM_AP(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_MDM_AP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field EZPT[4] (RO)
+ *
+ * Indicates a reset has been caused by EzPort receiving the RESET command while
+ * the device is in EzPort mode.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by EzPort receiving the RESET command while the
+ *     device is in EzPort mode
+ * - 0b1 - Reset caused by EzPort receiving the RESET command while the device
+ *     is in EzPort mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_EZPT field. */
+#define RCM_RD_SRS1_EZPT(base) ((RCM_SRS1_REG(base) & RCM_SRS1_EZPT_MASK) >> RCM_SRS1_EZPT_SHIFT)
+#define RCM_BRD_SRS1_EZPT(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_EZPT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SACKERR[5] (RO)
+ *
+ * Indicates that after an attempt to enter Stop mode, a reset has been caused
+ * by a failure of one or more peripherals to acknowledge within approximately one
+ * second to enter stop mode.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by peripheral failure to acknowledge attempt to
+ *     enter stop mode
+ * - 0b1 - Reset caused by peripheral failure to acknowledge attempt to enter
+ *     stop mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SACKERR field. */
+#define RCM_RD_SRS1_SACKERR(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SACKERR_MASK) >> RCM_SRS1_SACKERR_SHIFT)
+#define RCM_BRD_SRS1_SACKERR(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_SACKERR_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFC - Reset Pin Filter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFC - Reset Pin Filter Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
+ * other reset types. The bus clock filter is reset when disabled or when entering
+ * stop mode. The LPO filter is reset when disabled or when entering any low
+ * leakage stop mode .
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFC register
+ */
+/*@{*/
+#define RCM_RD_RPFC(base)        (RCM_RPFC_REG(base))
+#define RCM_WR_RPFC(base, value) (RCM_RPFC_REG(base) = (value))
+#define RCM_RMW_RPFC(base, mask, value) (RCM_WR_RPFC(base, (RCM_RD_RPFC(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) |  (value)))
+#define RCM_CLR_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) & ~(value)))
+#define RCM_TOG_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFC bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
+ *
+ * Selects how the reset pin filter is enabled in run and wait modes.
+ *
+ * Values:
+ * - 0b00 - All filtering disabled
+ * - 0b01 - Bus clock filter enabled for normal operation
+ * - 0b10 - LPO clock filter enabled for normal operation
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */
+#define RCM_RD_RPFC_RSTFLTSRW(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSRW_MASK) >> RCM_RPFC_RSTFLTSRW_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSRW(base) (RCM_RD_RPFC_RSTFLTSRW(base))
+
+/*! @brief Set the RSTFLTSRW field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSRW(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSRW_MASK, RCM_RPFC_RSTFLTSRW(value)))
+#define RCM_BWR_RPFC_RSTFLTSRW(base, value) (RCM_WR_RPFC_RSTFLTSRW(base, value))
+/*@}*/
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
+ *
+ * Selects how the reset pin filter is enabled in Stop and VLPS modes
+ *
+ * Values:
+ * - 0b0 - All filtering disabled
+ * - 0b1 - LPO clock filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */
+#define RCM_RD_RPFC_RSTFLTSS(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSS_MASK) >> RCM_RPFC_RSTFLTSS_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSS(base) (BITBAND_ACCESS8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT))
+
+/*! @brief Set the RSTFLTSS field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSS(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSS_MASK, RCM_RPFC_RSTFLTSS(value)))
+#define RCM_BWR_RPFC_RSTFLTSS(base, value) (BITBAND_ACCESS8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFW - Reset Pin Filter Width register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFW - Reset Pin Filter Width register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
+ * They are unaffected by other reset types.
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFW register
+ */
+/*@{*/
+#define RCM_RD_RPFW(base)        (RCM_RPFW_REG(base))
+#define RCM_WR_RPFW(base, value) (RCM_RPFW_REG(base) = (value))
+#define RCM_RMW_RPFW(base, mask, value) (RCM_WR_RPFW(base, (RCM_RD_RPFW(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) |  (value)))
+#define RCM_CLR_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) & ~(value)))
+#define RCM_TOG_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFW bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
+ *
+ * Selects the reset pin bus clock filter width.
+ *
+ * Values:
+ * - 0b00000 - Bus clock filter count is 1
+ * - 0b00001 - Bus clock filter count is 2
+ * - 0b00010 - Bus clock filter count is 3
+ * - 0b00011 - Bus clock filter count is 4
+ * - 0b00100 - Bus clock filter count is 5
+ * - 0b00101 - Bus clock filter count is 6
+ * - 0b00110 - Bus clock filter count is 7
+ * - 0b00111 - Bus clock filter count is 8
+ * - 0b01000 - Bus clock filter count is 9
+ * - 0b01001 - Bus clock filter count is 10
+ * - 0b01010 - Bus clock filter count is 11
+ * - 0b01011 - Bus clock filter count is 12
+ * - 0b01100 - Bus clock filter count is 13
+ * - 0b01101 - Bus clock filter count is 14
+ * - 0b01110 - Bus clock filter count is 15
+ * - 0b01111 - Bus clock filter count is 16
+ * - 0b10000 - Bus clock filter count is 17
+ * - 0b10001 - Bus clock filter count is 18
+ * - 0b10010 - Bus clock filter count is 19
+ * - 0b10011 - Bus clock filter count is 20
+ * - 0b10100 - Bus clock filter count is 21
+ * - 0b10101 - Bus clock filter count is 22
+ * - 0b10110 - Bus clock filter count is 23
+ * - 0b10111 - Bus clock filter count is 24
+ * - 0b11000 - Bus clock filter count is 25
+ * - 0b11001 - Bus clock filter count is 26
+ * - 0b11010 - Bus clock filter count is 27
+ * - 0b11011 - Bus clock filter count is 28
+ * - 0b11100 - Bus clock filter count is 29
+ * - 0b11101 - Bus clock filter count is 30
+ * - 0b11110 - Bus clock filter count is 31
+ * - 0b11111 - Bus clock filter count is 32
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */
+#define RCM_RD_RPFW_RSTFLTSEL(base) ((RCM_RPFW_REG(base) & RCM_RPFW_RSTFLTSEL_MASK) >> RCM_RPFW_RSTFLTSEL_SHIFT)
+#define RCM_BRD_RPFW_RSTFLTSEL(base) (RCM_RD_RPFW_RSTFLTSEL(base))
+
+/*! @brief Set the RSTFLTSEL field to a new value. */
+#define RCM_WR_RPFW_RSTFLTSEL(base, value) (RCM_RMW_RPFW(base, RCM_RPFW_RSTFLTSEL_MASK, RCM_RPFW_RSTFLTSEL(value)))
+#define RCM_BWR_RPFW_RSTFLTSEL(base, value) (RCM_WR_RPFW_RSTFLTSEL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_MR - Mode Register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_MR - Mode Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the state of the
+ * mode pins during the last Chip Reset.
+ */
+/*!
+ * @name Constants and macros for entire RCM_MR register
+ */
+/*@{*/
+#define RCM_RD_MR(base)          (RCM_MR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_MR bitfields
+ */
+
+/*!
+ * @name Register RCM_MR, field EZP_MS[1] (RO)
+ *
+ * Reflects the state of the EZP_MS pin during the last Chip Reset
+ *
+ * Values:
+ * - 0b0 - Pin deasserted (logic 1)
+ * - 0b1 - Pin asserted (logic 0)
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_MR_EZP_MS field. */
+#define RCM_RD_MR_EZP_MS(base) ((RCM_MR_REG(base) & RCM_MR_EZP_MS_MASK) >> RCM_MR_EZP_MS_SHIFT)
+#define RCM_BRD_MR_EZP_MS(base) (BITBAND_ACCESS8(&RCM_MR_REG(base), RCM_MR_EZP_MS_SHIFT))
+/*@}*/
+
+/*
+ * MK64F12 RFSYS
+ *
+ * System register file
+ *
+ * Registers defined in this header file:
+ * - RFSYS_REG - Register file register
+ */
+
+#define RFSYS_INSTANCE_COUNT (1U) /*!< Number of instances of the RFSYS module. */
+#define RFSYS_IDX (0U) /*!< Instance number for RFSYS. */
+
+/*******************************************************************************
+ * RFSYS_REG - Register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFSYS_REG - Register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFSYS_REG register
+ */
+/*@{*/
+#define RFSYS_RD_REG(base, index) (RFSYS_REG_REG(base, index))
+#define RFSYS_WR_REG(base, index, value) (RFSYS_REG_REG(base, index) = (value))
+#define RFSYS_RMW_REG(base, index, mask, value) (RFSYS_WR_REG(base, index, (RFSYS_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFSYS_SET_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) |  (value)))
+#define RFSYS_CLR_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) & ~(value)))
+#define RFSYS_TOG_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFSYS_REG bitfields
+ */
+
+/*!
+ * @name Register RFSYS_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LL field. */
+#define RFSYS_RD_REG_LL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LL_MASK) >> RFSYS_REG_LL_SHIFT)
+#define RFSYS_BRD_REG_LL(base, index) (RFSYS_RD_REG_LL(base, index))
+
+/*! @brief Set the LL field to a new value. */
+#define RFSYS_WR_REG_LL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LL_MASK, RFSYS_REG_LL(value)))
+#define RFSYS_BWR_REG_LL(base, index, value) (RFSYS_WR_REG_LL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LH field. */
+#define RFSYS_RD_REG_LH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LH_MASK) >> RFSYS_REG_LH_SHIFT)
+#define RFSYS_BRD_REG_LH(base, index) (RFSYS_RD_REG_LH(base, index))
+
+/*! @brief Set the LH field to a new value. */
+#define RFSYS_WR_REG_LH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LH_MASK, RFSYS_REG_LH(value)))
+#define RFSYS_BWR_REG_LH(base, index, value) (RFSYS_WR_REG_LH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HL field. */
+#define RFSYS_RD_REG_HL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HL_MASK) >> RFSYS_REG_HL_SHIFT)
+#define RFSYS_BRD_REG_HL(base, index) (RFSYS_RD_REG_HL(base, index))
+
+/*! @brief Set the HL field to a new value. */
+#define RFSYS_WR_REG_HL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HL_MASK, RFSYS_REG_HL(value)))
+#define RFSYS_BWR_REG_HL(base, index, value) (RFSYS_WR_REG_HL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HH field. */
+#define RFSYS_RD_REG_HH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HH_MASK) >> RFSYS_REG_HH_SHIFT)
+#define RFSYS_BRD_REG_HH(base, index) (RFSYS_RD_REG_HH(base, index))
+
+/*! @brief Set the HH field to a new value. */
+#define RFSYS_WR_REG_HH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HH_MASK, RFSYS_REG_HH(value)))
+#define RFSYS_BWR_REG_HH(base, index, value) (RFSYS_WR_REG_HH(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 RFVBAT
+ *
+ * VBAT register file
+ *
+ * Registers defined in this header file:
+ * - RFVBAT_REG - VBAT register file register
+ */
+
+#define RFVBAT_INSTANCE_COUNT (1U) /*!< Number of instances of the RFVBAT module. */
+#define RFVBAT_IDX (0U) /*!< Instance number for RFVBAT. */
+
+/*******************************************************************************
+ * RFVBAT_REG - VBAT register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFVBAT_REG - VBAT register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFVBAT_REG register
+ */
+/*@{*/
+#define RFVBAT_RD_REG(base, index) (RFVBAT_REG_REG(base, index))
+#define RFVBAT_WR_REG(base, index, value) (RFVBAT_REG_REG(base, index) = (value))
+#define RFVBAT_RMW_REG(base, index, mask, value) (RFVBAT_WR_REG(base, index, (RFVBAT_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFVBAT_SET_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) |  (value)))
+#define RFVBAT_CLR_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) & ~(value)))
+#define RFVBAT_TOG_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFVBAT_REG bitfields
+ */
+
+/*!
+ * @name Register RFVBAT_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_LL field. */
+#define RFVBAT_RD_REG_LL(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_LL_MASK) >> RFVBAT_REG_LL_SHIFT)
+#define RFVBAT_BRD_REG_LL(base, index) (RFVBAT_RD_REG_LL(base, index))
+
+/*! @brief Set the LL field to a new value. */
+#define RFVBAT_WR_REG_LL(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_LL_MASK, RFVBAT_REG_LL(value)))
+#define RFVBAT_BWR_REG_LL(base, index, value) (RFVBAT_WR_REG_LL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_LH field. */
+#define RFVBAT_RD_REG_LH(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_LH_MASK) >> RFVBAT_REG_LH_SHIFT)
+#define RFVBAT_BRD_REG_LH(base, index) (RFVBAT_RD_REG_LH(base, index))
+
+/*! @brief Set the LH field to a new value. */
+#define RFVBAT_WR_REG_LH(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_LH_MASK, RFVBAT_REG_LH(value)))
+#define RFVBAT_BWR_REG_LH(base, index, value) (RFVBAT_WR_REG_LH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_HL field. */
+#define RFVBAT_RD_REG_HL(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_HL_MASK) >> RFVBAT_REG_HL_SHIFT)
+#define RFVBAT_BRD_REG_HL(base, index) (RFVBAT_RD_REG_HL(base, index))
+
+/*! @brief Set the HL field to a new value. */
+#define RFVBAT_WR_REG_HL(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_HL_MASK, RFVBAT_REG_HL(value)))
+#define RFVBAT_BWR_REG_HL(base, index, value) (RFVBAT_WR_REG_HL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_HH field. */
+#define RFVBAT_RD_REG_HH(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_HH_MASK) >> RFVBAT_REG_HH_SHIFT)
+#define RFVBAT_BRD_REG_HH(base, index) (RFVBAT_RD_REG_HH(base, index))
+
+/*! @brief Set the HH field to a new value. */
+#define RFVBAT_WR_REG_HH(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_HH_MASK, RFVBAT_REG_HH(value)))
+#define RFVBAT_BWR_REG_HH(base, index, value) (RFVBAT_WR_REG_HH(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 RNG
+ *
+ * Random Number Generator Accelerator
+ *
+ * Registers defined in this header file:
+ * - RNG_CR - RNGA Control Register
+ * - RNG_SR - RNGA Status Register
+ * - RNG_ER - RNGA Entropy Register
+ * - RNG_OR - RNGA Output Register
+ */
+
+#define RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
+#define RNG_IDX (0U) /*!< Instance number for RNG. */
+
+/*******************************************************************************
+ * RNG_CR - RNGA Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_CR - RNGA Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the operation of RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_CR register
+ */
+/*@{*/
+#define RNG_RD_CR(base)          (RNG_CR_REG(base))
+#define RNG_WR_CR(base, value)   (RNG_CR_REG(base) = (value))
+#define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value)))
+#define RNG_SET_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) |  (value)))
+#define RNG_CLR_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) & ~(value)))
+#define RNG_TOG_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RNG_CR bitfields
+ */
+
+/*!
+ * @name Register RNG_CR, field GO[0] (RW)
+ *
+ * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
+ * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
+ * OR[RANDOUT] with data.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_GO field. */
+#define RNG_RD_CR_GO(base)   ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT)
+#define RNG_BRD_CR_GO(base)  (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_GO_SHIFT))
+
+/*! @brief Set the GO field to a new value. */
+#define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value)))
+#define RNG_BWR_CR_GO(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_GO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field HA[1] (RW)
+ *
+ * Enables notification of security violations (via SR[SECV]). A security
+ * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
+ * After enabling notification of security violations, you must reset RNGA to
+ * disable them again.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_HA field. */
+#define RNG_RD_CR_HA(base)   ((RNG_CR_REG(base) & RNG_CR_HA_MASK) >> RNG_CR_HA_SHIFT)
+#define RNG_BRD_CR_HA(base)  (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_HA_SHIFT))
+
+/*! @brief Set the HA field to a new value. */
+#define RNG_WR_CR_HA(base, value) (RNG_RMW_CR(base, RNG_CR_HA_MASK, RNG_CR_HA(value)))
+#define RNG_BWR_CR_HA(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_HA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field INTM[2] (RW)
+ *
+ * Masks the triggering of an error interrupt to the interrupt controller when
+ * an OR underflow condition occurs. An OR underflow condition occurs when you
+ * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
+ *
+ * Values:
+ * - 0b0 - Not masked
+ * - 0b1 - Masked
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_INTM field. */
+#define RNG_RD_CR_INTM(base) ((RNG_CR_REG(base) & RNG_CR_INTM_MASK) >> RNG_CR_INTM_SHIFT)
+#define RNG_BRD_CR_INTM(base) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_INTM_SHIFT))
+
+/*! @brief Set the INTM field to a new value. */
+#define RNG_WR_CR_INTM(base, value) (RNG_RMW_CR(base, RNG_CR_INTM_MASK, RNG_CR_INTM(value)))
+#define RNG_BWR_CR_INTM(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_INTM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field CLRI[3] (WORZ)
+ *
+ * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
+ *
+ * Values:
+ * - 0b0 - Do not clear the interrupt.
+ * - 0b1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
+ *     the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
+ */
+/*@{*/
+/*! @brief Set the CLRI field to a new value. */
+#define RNG_WR_CR_CLRI(base, value) (RNG_RMW_CR(base, RNG_CR_CLRI_MASK, RNG_CR_CLRI(value)))
+#define RNG_BWR_CR_CLRI(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_CLRI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field SLP[4] (RW)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_SLP field. */
+#define RNG_RD_CR_SLP(base)  ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT)
+#define RNG_BRD_CR_SLP(base) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_SLP_SHIFT))
+
+/*! @brief Set the SLP field to a new value. */
+#define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value)))
+#define RNG_BWR_CR_SLP(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_SLP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_SR - RNGA Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_SR - RNGA Status Register (RO)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Indicates the status of RNGA. This register is read-only.
+ */
+/*!
+ * @name Constants and macros for entire RNG_SR register
+ */
+/*@{*/
+#define RNG_RD_SR(base)          (RNG_SR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RNG_SR bitfields
+ */
+
+/*!
+ * @name Register RNG_SR, field SECV[0] (RO)
+ *
+ * Used only when high assurance is enabled (CR[HA]). Indicates that a security
+ * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
+ * RNGA.
+ *
+ * Values:
+ * - 0b0 - No security violation
+ * - 0b1 - Security violation
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SECV field. */
+#define RNG_RD_SR_SECV(base) ((RNG_SR_REG(base) & RNG_SR_SECV_MASK) >> RNG_SR_SECV_SHIFT)
+#define RNG_BRD_SR_SECV(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_SECV_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field LRS[1] (RO)
+ *
+ * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
+ * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
+ * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
+ * After you read this register, RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_LRS field. */
+#define RNG_RD_SR_LRS(base)  ((RNG_SR_REG(base) & RNG_SR_LRS_MASK) >> RNG_SR_LRS_SHIFT)
+#define RNG_BRD_SR_LRS(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_LRS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field ORU[2] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last read
+ * this register (SR) or RNGA was reset, regardless of whether the error
+ * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
+ * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
+ * field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_ORU field. */
+#define RNG_RD_SR_ORU(base)  ((RNG_SR_REG(base) & RNG_SR_ORU_MASK) >> RNG_SR_ORU_SHIFT)
+#define RNG_BRD_SR_ORU(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_ORU_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field ERRI[3] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last
+ * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
+ * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
+ * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
+ * indicator (via CR[CLRI]), RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_ERRI field. */
+#define RNG_RD_SR_ERRI(base) ((RNG_SR_REG(base) & RNG_SR_ERRI_MASK) >> RNG_SR_ERRI_SHIFT)
+#define RNG_BRD_SR_ERRI(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_ERRI_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field SLP[4] (RO)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SLP field. */
+#define RNG_RD_SR_SLP(base)  ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT)
+#define RNG_BRD_SR_SLP(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_SLP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
+ *
+ * Indicates the number of random-data words that are in OR[RANDOUT], which
+ * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
+ * is not 0, then the contents of a random number contained in OR[RANDOUT] are
+ * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
+ *
+ * Values:
+ * - 0b00000000 - No words (empty)
+ * - 0b00000001 - One word (valid)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_LVL field. */
+#define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT)
+#define RNG_BRD_SR_OREG_LVL(base) (RNG_RD_SR_OREG_LVL(base))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
+ *
+ * Indicates the size of the Output (OR) register in terms of the number of
+ * 32-bit random-data words it can hold.
+ *
+ * Values:
+ * - 0b00000001 - One word (this value is fixed)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
+#define RNG_RD_SR_OREG_SIZE(base) ((RNG_SR_REG(base) & RNG_SR_OREG_SIZE_MASK) >> RNG_SR_OREG_SIZE_SHIFT)
+#define RNG_BRD_SR_OREG_SIZE(base) (RNG_RD_SR_OREG_SIZE(base))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_ER - RNGA Entropy Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_ER - RNGA Entropy Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies an entropy value that RNGA uses in addition to its ring oscillators
+ * to seed its pseudorandom algorithm. This is a write-only register; reads
+ * return all zeros.
+ */
+/*!
+ * @name Constants and macros for entire RNG_ER register
+ */
+/*@{*/
+#define RNG_RD_ER(base)          (RNG_ER_REG(base))
+#define RNG_WR_ER(base, value)   (RNG_ER_REG(base) = (value))
+#define RNG_RMW_ER(base, mask, value) (RNG_WR_ER(base, (RNG_RD_ER(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_OR - RNGA Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_OR - RNGA Output Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Stores a random-data word generated by RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_OR register
+ */
+/*@{*/
+#define RNG_RD_OR(base)          (RNG_OR_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 RTC
+ *
+ * Secure Real Time Clock
+ *
+ * Registers defined in this header file:
+ * - RTC_TSR - RTC Time Seconds Register
+ * - RTC_TPR - RTC Time Prescaler Register
+ * - RTC_TAR - RTC Time Alarm Register
+ * - RTC_TCR - RTC Time Compensation Register
+ * - RTC_CR - RTC Control Register
+ * - RTC_SR - RTC Status Register
+ * - RTC_LR - RTC Lock Register
+ * - RTC_IER - RTC Interrupt Enable Register
+ * - RTC_WAR - RTC Write Access Register
+ * - RTC_RAR - RTC Read Access Register
+ */
+
+#define RTC_INSTANCE_COUNT (1U) /*!< Number of instances of the RTC module. */
+#define RTC_IDX (0U) /*!< Instance number for RTC. */
+
+/*******************************************************************************
+ * RTC_TSR - RTC Time Seconds Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TSR - RTC Time Seconds Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TSR register
+ */
+/*@{*/
+#define RTC_RD_TSR(base)         (RTC_TSR_REG(base))
+#define RTC_WR_TSR(base, value)  (RTC_TSR_REG(base) = (value))
+#define RTC_RMW_TSR(base, mask, value) (RTC_WR_TSR(base, (RTC_RD_TSR(base) & ~(mask)) | (value)))
+#define RTC_SET_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) |  (value)))
+#define RTC_CLR_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) & ~(value)))
+#define RTC_TOG_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TPR - RTC Time Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TPR - RTC Time Prescaler Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TPR register
+ */
+/*@{*/
+#define RTC_RD_TPR(base)         (RTC_TPR_REG(base))
+#define RTC_WR_TPR(base, value)  (RTC_TPR_REG(base) = (value))
+#define RTC_RMW_TPR(base, mask, value) (RTC_WR_TPR(base, (RTC_RD_TPR(base) & ~(mask)) | (value)))
+#define RTC_SET_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) |  (value)))
+#define RTC_CLR_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) & ~(value)))
+#define RTC_TOG_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TPR bitfields
+ */
+
+/*!
+ * @name Register RTC_TPR, field TPR[15:0] (RW)
+ *
+ * When the time counter is enabled, the TPR is read only and increments every
+ * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
+ * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
+ * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
+ * to a logic zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TPR_TPR field. */
+#define RTC_RD_TPR_TPR(base) ((RTC_TPR_REG(base) & RTC_TPR_TPR_MASK) >> RTC_TPR_TPR_SHIFT)
+#define RTC_BRD_TPR_TPR(base) (RTC_RD_TPR_TPR(base))
+
+/*! @brief Set the TPR field to a new value. */
+#define RTC_WR_TPR_TPR(base, value) (RTC_RMW_TPR(base, RTC_TPR_TPR_MASK, RTC_TPR_TPR(value)))
+#define RTC_BWR_TPR_TPR(base, value) (RTC_WR_TPR_TPR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TAR - RTC Time Alarm Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TAR - RTC Time Alarm Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TAR register
+ */
+/*@{*/
+#define RTC_RD_TAR(base)         (RTC_TAR_REG(base))
+#define RTC_WR_TAR(base, value)  (RTC_TAR_REG(base) = (value))
+#define RTC_RMW_TAR(base, mask, value) (RTC_WR_TAR(base, (RTC_RD_TAR(base) & ~(mask)) | (value)))
+#define RTC_SET_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) |  (value)))
+#define RTC_CLR_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) & ~(value)))
+#define RTC_TOG_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TCR - RTC Time Compensation Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TCR - RTC Time Compensation Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TCR register
+ */
+/*@{*/
+#define RTC_RD_TCR(base)         (RTC_TCR_REG(base))
+#define RTC_WR_TCR(base, value)  (RTC_TCR_REG(base) = (value))
+#define RTC_RMW_TCR(base, mask, value) (RTC_WR_TCR(base, (RTC_RD_TCR(base) & ~(mask)) | (value)))
+#define RTC_SET_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) |  (value)))
+#define RTC_CLR_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) & ~(value)))
+#define RTC_TOG_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TCR bitfields
+ */
+
+/*!
+ * @name Register RTC_TCR, field TCR[7:0] (RW)
+ *
+ * Configures the number of 32.768 kHz clock cycles in each second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ *
+ * Values:
+ * - 0b10000000 - Time Prescaler Register overflows every 32896 clock cycles.
+ * - 0b11111111 - Time Prescaler Register overflows every 32769 clock cycles.
+ * - 0b00000000 - Time Prescaler Register overflows every 32768 clock cycles.
+ * - 0b00000001 - Time Prescaler Register overflows every 32767 clock cycles.
+ * - 0b01111111 - Time Prescaler Register overflows every 32641 clock cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCR field. */
+#define RTC_RD_TCR_TCR(base) ((RTC_TCR_REG(base) & RTC_TCR_TCR_MASK) >> RTC_TCR_TCR_SHIFT)
+#define RTC_BRD_TCR_TCR(base) (RTC_RD_TCR_TCR(base))
+
+/*! @brief Set the TCR field to a new value. */
+#define RTC_WR_TCR_TCR(base, value) (RTC_RMW_TCR(base, RTC_TCR_TCR_MASK, RTC_TCR_TCR(value)))
+#define RTC_BWR_TCR_TCR(base, value) (RTC_WR_TCR_TCR(base, value))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIR[15:8] (RW)
+ *
+ * Configures the compensation interval in seconds from 1 to 256 to control how
+ * frequently the TCR should adjust the number of 32.768 kHz cycles in each
+ * second. The value written should be one less than the number of seconds. For
+ * example, write zero to configure for a compensation interval of one second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIR field. */
+#define RTC_RD_TCR_CIR(base) ((RTC_TCR_REG(base) & RTC_TCR_CIR_MASK) >> RTC_TCR_CIR_SHIFT)
+#define RTC_BRD_TCR_CIR(base) (RTC_RD_TCR_CIR(base))
+
+/*! @brief Set the CIR field to a new value. */
+#define RTC_WR_TCR_CIR(base, value) (RTC_RMW_TCR(base, RTC_TCR_CIR_MASK, RTC_TCR_CIR(value)))
+#define RTC_BWR_TCR_CIR(base, value) (RTC_WR_TCR_CIR(base, value))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field TCV[23:16] (RO)
+ *
+ * Current value used by the compensation logic for the present second interval.
+ * Updated once a second if the CIC equals 0 with the contents of the TCR field.
+ * If the CIC does not equal zero then it is loaded with zero (compensation is
+ * not enabled for that second increment).
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCV field. */
+#define RTC_RD_TCR_TCV(base) ((RTC_TCR_REG(base) & RTC_TCR_TCV_MASK) >> RTC_TCR_TCV_SHIFT)
+#define RTC_BRD_TCR_TCV(base) (RTC_RD_TCR_TCV(base))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIC[31:24] (RO)
+ *
+ * Current value of the compensation interval counter. If the compensation
+ * interval counter equals zero then it is loaded with the contents of the CIR. If the
+ * CIC does not equal zero then it is decremented once a second.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIC field. */
+#define RTC_RD_TCR_CIC(base) ((RTC_TCR_REG(base) & RTC_TCR_CIC_MASK) >> RTC_TCR_CIC_SHIFT)
+#define RTC_BRD_TCR_CIC(base) (RTC_RD_TCR_CIC(base))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_CR - RTC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_CR - RTC Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_CR register
+ */
+/*@{*/
+#define RTC_RD_CR(base)          (RTC_CR_REG(base))
+#define RTC_WR_CR(base, value)   (RTC_CR_REG(base) = (value))
+#define RTC_RMW_CR(base, mask, value) (RTC_WR_CR(base, (RTC_RD_CR(base) & ~(mask)) | (value)))
+#define RTC_SET_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) |  (value)))
+#define RTC_CLR_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) & ~(value)))
+#define RTC_TOG_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_CR bitfields
+ */
+
+/*!
+ * @name Register RTC_CR, field SWR[0] (RW)
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
+ *     RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
+ *     explicitly clearing it.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SWR field. */
+#define RTC_RD_CR_SWR(base)  ((RTC_CR_REG(base) & RTC_CR_SWR_MASK) >> RTC_CR_SWR_SHIFT)
+#define RTC_BRD_CR_SWR(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT))
+
+/*! @brief Set the SWR field to a new value. */
+#define RTC_WR_CR_SWR(base, value) (RTC_RMW_CR(base, RTC_CR_SWR_MASK, RTC_CR_SWR(value)))
+#define RTC_BWR_CR_SWR(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPE[1] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0b0 - Wakeup pin is disabled.
+ * - 0b1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPE field. */
+#define RTC_RD_CR_WPE(base)  ((RTC_CR_REG(base) & RTC_CR_WPE_MASK) >> RTC_CR_WPE_SHIFT)
+#define RTC_BRD_CR_WPE(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT))
+
+/*! @brief Set the WPE field to a new value. */
+#define RTC_WR_CR_WPE(base, value) (RTC_RMW_CR(base, RTC_CR_WPE_MASK, RTC_CR_WPE(value)))
+#define RTC_BWR_CR_WPE(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SUP[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Non-supervisor mode write accesses are not supported and generate a
+ *     bus error.
+ * - 0b1 - Non-supervisor mode write accesses are supported.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SUP field. */
+#define RTC_RD_CR_SUP(base)  ((RTC_CR_REG(base) & RTC_CR_SUP_MASK) >> RTC_CR_SUP_SHIFT)
+#define RTC_BRD_CR_SUP(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT))
+
+/*! @brief Set the SUP field to a new value. */
+#define RTC_WR_CR_SUP(base, value) (RTC_RMW_CR(base, RTC_CR_SUP_MASK, RTC_CR_SUP(value)))
+#define RTC_BWR_CR_SUP(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field UM[3] (RW)
+ *
+ * Allows SR[TCE] to be written even when the Status Register is locked. When
+ * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
+ * the SR[TCE] is clear.
+ *
+ * Values:
+ * - 0b0 - Registers cannot be written when locked.
+ * - 0b1 - Registers can be written when locked under limited conditions.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_UM field. */
+#define RTC_RD_CR_UM(base)   ((RTC_CR_REG(base) & RTC_CR_UM_MASK) >> RTC_CR_UM_SHIFT)
+#define RTC_BRD_CR_UM(base)  (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT))
+
+/*! @brief Set the UM field to a new value. */
+#define RTC_WR_CR_UM(base, value) (RTC_RMW_CR(base, RTC_CR_UM_MASK, RTC_CR_UM(value)))
+#define RTC_BWR_CR_UM(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPS[4] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0b0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ * - 0b1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup
+ *     pin is turned on and the 32kHz clock is output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPS field. */
+#define RTC_RD_CR_WPS(base)  ((RTC_CR_REG(base) & RTC_CR_WPS_MASK) >> RTC_CR_WPS_SHIFT)
+#define RTC_BRD_CR_WPS(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT))
+
+/*! @brief Set the WPS field to a new value. */
+#define RTC_WR_CR_WPS(base, value) (RTC_RMW_CR(base, RTC_CR_WPS_MASK, RTC_CR_WPS(value)))
+#define RTC_BWR_CR_WPS(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field OSCE[8] (RW)
+ *
+ * Values:
+ * - 0b0 - 32.768 kHz oscillator is disabled.
+ * - 0b1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
+ *     oscillator startup time before enabling the time counter to allow the 32.768
+ *     kHz clock time to stabilize.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_OSCE field. */
+#define RTC_RD_CR_OSCE(base) ((RTC_CR_REG(base) & RTC_CR_OSCE_MASK) >> RTC_CR_OSCE_SHIFT)
+#define RTC_BRD_CR_OSCE(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT))
+
+/*! @brief Set the OSCE field to a new value. */
+#define RTC_WR_CR_OSCE(base, value) (RTC_RMW_CR(base, RTC_CR_OSCE_MASK, RTC_CR_OSCE(value)))
+#define RTC_BWR_CR_OSCE(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field CLKO[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The 32 kHz clock is output to other peripherals.
+ * - 0b1 - The 32 kHz clock is not output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_CLKO field. */
+#define RTC_RD_CR_CLKO(base) ((RTC_CR_REG(base) & RTC_CR_CLKO_MASK) >> RTC_CR_CLKO_SHIFT)
+#define RTC_BRD_CR_CLKO(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT))
+
+/*! @brief Set the CLKO field to a new value. */
+#define RTC_WR_CR_CLKO(base, value) (RTC_RMW_CR(base, RTC_CR_CLKO_MASK, RTC_CR_CLKO(value)))
+#define RTC_BWR_CR_CLKO(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC16P[10] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC16P field. */
+#define RTC_RD_CR_SC16P(base) ((RTC_CR_REG(base) & RTC_CR_SC16P_MASK) >> RTC_CR_SC16P_SHIFT)
+#define RTC_BRD_CR_SC16P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT))
+
+/*! @brief Set the SC16P field to a new value. */
+#define RTC_WR_CR_SC16P(base, value) (RTC_RMW_CR(base, RTC_CR_SC16P_MASK, RTC_CR_SC16P(value)))
+#define RTC_BWR_CR_SC16P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC8P[11] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC8P field. */
+#define RTC_RD_CR_SC8P(base) ((RTC_CR_REG(base) & RTC_CR_SC8P_MASK) >> RTC_CR_SC8P_SHIFT)
+#define RTC_BRD_CR_SC8P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT))
+
+/*! @brief Set the SC8P field to a new value. */
+#define RTC_WR_CR_SC8P(base, value) (RTC_RMW_CR(base, RTC_CR_SC8P_MASK, RTC_CR_SC8P(value)))
+#define RTC_BWR_CR_SC8P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC4P[12] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC4P field. */
+#define RTC_RD_CR_SC4P(base) ((RTC_CR_REG(base) & RTC_CR_SC4P_MASK) >> RTC_CR_SC4P_SHIFT)
+#define RTC_BRD_CR_SC4P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT))
+
+/*! @brief Set the SC4P field to a new value. */
+#define RTC_WR_CR_SC4P(base, value) (RTC_RMW_CR(base, RTC_CR_SC4P_MASK, RTC_CR_SC4P(value)))
+#define RTC_BWR_CR_SC4P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC2P[13] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC2P field. */
+#define RTC_RD_CR_SC2P(base) ((RTC_CR_REG(base) & RTC_CR_SC2P_MASK) >> RTC_CR_SC2P_SHIFT)
+#define RTC_BRD_CR_SC2P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT))
+
+/*! @brief Set the SC2P field to a new value. */
+#define RTC_WR_CR_SC2P(base, value) (RTC_RMW_CR(base, RTC_CR_SC2P_MASK, RTC_CR_SC2P(value)))
+#define RTC_BWR_CR_SC2P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_SR - RTC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_SR - RTC Status Register (RW)
+ *
+ * Reset value: 0x00000001U
+ */
+/*!
+ * @name Constants and macros for entire RTC_SR register
+ */
+/*@{*/
+#define RTC_RD_SR(base)          (RTC_SR_REG(base))
+#define RTC_WR_SR(base, value)   (RTC_SR_REG(base) = (value))
+#define RTC_RMW_SR(base, mask, value) (RTC_WR_SR(base, (RTC_RD_SR(base) & ~(mask)) | (value)))
+#define RTC_SET_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) |  (value)))
+#define RTC_CLR_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) & ~(value)))
+#define RTC_TOG_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_SR bitfields
+ */
+
+/*!
+ * @name Register RTC_SR, field TIF[0] (RO)
+ *
+ * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
+ * do not increment and read as zero when this bit is set. This bit is cleared by
+ * writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0b0 - Time is valid.
+ * - 0b1 - Time is invalid and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TIF field. */
+#define RTC_RD_SR_TIF(base)  ((RTC_SR_REG(base) & RTC_SR_TIF_MASK) >> RTC_SR_TIF_SHIFT)
+#define RTC_BRD_SR_TIF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TIF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TOF[1] (RO)
+ *
+ * Time overflow flag is set when the time counter is enabled and overflows. The
+ * TSR and TPR do not increment and read as zero when this bit is set. This bit
+ * is cleared by writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0b0 - Time overflow has not occurred.
+ * - 0b1 - Time overflow has occurred and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TOF field. */
+#define RTC_RD_SR_TOF(base)  ((RTC_SR_REG(base) & RTC_SR_TOF_MASK) >> RTC_SR_TOF_SHIFT)
+#define RTC_BRD_SR_TOF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TOF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TAF[2] (RO)
+ *
+ * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
+ * increments. This bit is cleared by writing the TAR register.
+ *
+ * Values:
+ * - 0b0 - Time alarm has not occurred.
+ * - 0b1 - Time alarm has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TAF field. */
+#define RTC_RD_SR_TAF(base)  ((RTC_SR_REG(base) & RTC_SR_TAF_MASK) >> RTC_SR_TAF_SHIFT)
+#define RTC_BRD_SR_TAF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TAF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TCE[4] (RW)
+ *
+ * When time counter is disabled the TSR register and TPR register are
+ * writeable, but do not increment. When time counter is enabled the TSR register and TPR
+ * register are not writeable, but increment.
+ *
+ * Values:
+ * - 0b0 - Time counter is disabled.
+ * - 0b1 - Time counter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TCE field. */
+#define RTC_RD_SR_TCE(base)  ((RTC_SR_REG(base) & RTC_SR_TCE_MASK) >> RTC_SR_TCE_SHIFT)
+#define RTC_BRD_SR_TCE(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT))
+
+/*! @brief Set the TCE field to a new value. */
+#define RTC_WR_SR_TCE(base, value) (RTC_RMW_SR(base, RTC_SR_TCE_MASK, RTC_SR_TCE(value)))
+#define RTC_BWR_SR_TCE(base, value) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_LR - RTC Lock Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_LR - RTC Lock Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_LR register
+ */
+/*@{*/
+#define RTC_RD_LR(base)          (RTC_LR_REG(base))
+#define RTC_WR_LR(base, value)   (RTC_LR_REG(base) = (value))
+#define RTC_RMW_LR(base, mask, value) (RTC_WR_LR(base, (RTC_RD_LR(base) & ~(mask)) | (value)))
+#define RTC_SET_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) |  (value)))
+#define RTC_CLR_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) & ~(value)))
+#define RTC_TOG_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_LR bitfields
+ */
+
+/*!
+ * @name Register RTC_LR, field TCL[3] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Time Compensation Register is locked and writes are ignored.
+ * - 0b1 - Time Compensation Register is not locked and writes complete as
+ *     normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_TCL field. */
+#define RTC_RD_LR_TCL(base)  ((RTC_LR_REG(base) & RTC_LR_TCL_MASK) >> RTC_LR_TCL_SHIFT)
+#define RTC_BRD_LR_TCL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT))
+
+/*! @brief Set the TCL field to a new value. */
+#define RTC_WR_LR_TCL(base, value) (RTC_RMW_LR(base, RTC_LR_TCL_MASK, RTC_LR_TCL(value)))
+#define RTC_BWR_LR_TCL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field CRL[4] (RW)
+ *
+ * After being cleared, this bit can only be set by VBAT POR.
+ *
+ * Values:
+ * - 0b0 - Control Register is locked and writes are ignored.
+ * - 0b1 - Control Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_CRL field. */
+#define RTC_RD_LR_CRL(base)  ((RTC_LR_REG(base) & RTC_LR_CRL_MASK) >> RTC_LR_CRL_SHIFT)
+#define RTC_BRD_LR_CRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT))
+
+/*! @brief Set the CRL field to a new value. */
+#define RTC_WR_LR_CRL(base, value) (RTC_RMW_LR(base, RTC_LR_CRL_MASK, RTC_LR_CRL(value)))
+#define RTC_BWR_LR_CRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field SRL[5] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Status Register is locked and writes are ignored.
+ * - 0b1 - Status Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_SRL field. */
+#define RTC_RD_LR_SRL(base)  ((RTC_LR_REG(base) & RTC_LR_SRL_MASK) >> RTC_LR_SRL_SHIFT)
+#define RTC_BRD_LR_SRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT))
+
+/*! @brief Set the SRL field to a new value. */
+#define RTC_WR_LR_SRL(base, value) (RTC_RMW_LR(base, RTC_LR_SRL_MASK, RTC_LR_SRL(value)))
+#define RTC_BWR_LR_SRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field LRL[6] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Lock Register is locked and writes are ignored.
+ * - 0b1 - Lock Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_LRL field. */
+#define RTC_RD_LR_LRL(base)  ((RTC_LR_REG(base) & RTC_LR_LRL_MASK) >> RTC_LR_LRL_SHIFT)
+#define RTC_BRD_LR_LRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT))
+
+/*! @brief Set the LRL field to a new value. */
+#define RTC_WR_LR_LRL(base, value) (RTC_RMW_LR(base, RTC_LR_LRL_MASK, RTC_LR_LRL(value)))
+#define RTC_BWR_LR_LRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_IER - RTC Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_IER - RTC Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00000007U
+ */
+/*!
+ * @name Constants and macros for entire RTC_IER register
+ */
+/*@{*/
+#define RTC_RD_IER(base)         (RTC_IER_REG(base))
+#define RTC_WR_IER(base, value)  (RTC_IER_REG(base) = (value))
+#define RTC_RMW_IER(base, mask, value) (RTC_WR_IER(base, (RTC_RD_IER(base) & ~(mask)) | (value)))
+#define RTC_SET_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) |  (value)))
+#define RTC_CLR_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) & ~(value)))
+#define RTC_TOG_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_IER bitfields
+ */
+
+/*!
+ * @name Register RTC_IER, field TIIE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Time invalid flag does not generate an interrupt.
+ * - 0b1 - Time invalid flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TIIE field. */
+#define RTC_RD_IER_TIIE(base) ((RTC_IER_REG(base) & RTC_IER_TIIE_MASK) >> RTC_IER_TIIE_SHIFT)
+#define RTC_BRD_IER_TIIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT))
+
+/*! @brief Set the TIIE field to a new value. */
+#define RTC_WR_IER_TIIE(base, value) (RTC_RMW_IER(base, RTC_IER_TIIE_MASK, RTC_IER_TIIE(value)))
+#define RTC_BWR_IER_TIIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TOIE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Time overflow flag does not generate an interrupt.
+ * - 0b1 - Time overflow flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TOIE field. */
+#define RTC_RD_IER_TOIE(base) ((RTC_IER_REG(base) & RTC_IER_TOIE_MASK) >> RTC_IER_TOIE_SHIFT)
+#define RTC_BRD_IER_TOIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT))
+
+/*! @brief Set the TOIE field to a new value. */
+#define RTC_WR_IER_TOIE(base, value) (RTC_RMW_IER(base, RTC_IER_TOIE_MASK, RTC_IER_TOIE(value)))
+#define RTC_BWR_IER_TOIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TAIE[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Time alarm flag does not generate an interrupt.
+ * - 0b1 - Time alarm flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TAIE field. */
+#define RTC_RD_IER_TAIE(base) ((RTC_IER_REG(base) & RTC_IER_TAIE_MASK) >> RTC_IER_TAIE_SHIFT)
+#define RTC_BRD_IER_TAIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT))
+
+/*! @brief Set the TAIE field to a new value. */
+#define RTC_WR_IER_TAIE(base, value) (RTC_RMW_IER(base, RTC_IER_TAIE_MASK, RTC_IER_TAIE(value)))
+#define RTC_BWR_IER_TAIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TSIE[4] (RW)
+ *
+ * The seconds interrupt is an edge-sensitive interrupt with a dedicated
+ * interrupt vector. It is generated once a second and requires no software overhead
+ * (there is no corresponding status flag to clear).
+ *
+ * Values:
+ * - 0b0 - Seconds interrupt is disabled.
+ * - 0b1 - Seconds interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TSIE field. */
+#define RTC_RD_IER_TSIE(base) ((RTC_IER_REG(base) & RTC_IER_TSIE_MASK) >> RTC_IER_TSIE_SHIFT)
+#define RTC_BRD_IER_TSIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT))
+
+/*! @brief Set the TSIE field to a new value. */
+#define RTC_WR_IER_TSIE(base, value) (RTC_RMW_IER(base, RTC_IER_TSIE_MASK, RTC_IER_TSIE(value)))
+#define RTC_BWR_IER_TSIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field WPON[7] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices. Whenever the
+ * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - If the wakeup pin is enabled, then the wakeup pin will assert.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_WPON field. */
+#define RTC_RD_IER_WPON(base) ((RTC_IER_REG(base) & RTC_IER_WPON_MASK) >> RTC_IER_WPON_SHIFT)
+#define RTC_BRD_IER_WPON(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT))
+
+/*! @brief Set the WPON field to a new value. */
+#define RTC_WR_IER_WPON(base, value) (RTC_RMW_IER(base, RTC_IER_WPON_MASK, RTC_IER_WPON(value)))
+#define RTC_BWR_IER_WPON(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_WAR - RTC Write Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_WAR - RTC Write Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_WAR register
+ */
+/*@{*/
+#define RTC_RD_WAR(base)         (RTC_WAR_REG(base))
+#define RTC_WR_WAR(base, value)  (RTC_WAR_REG(base) = (value))
+#define RTC_RMW_WAR(base, mask, value) (RTC_WR_WAR(base, (RTC_RD_WAR(base) & ~(mask)) | (value)))
+#define RTC_SET_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) |  (value)))
+#define RTC_CLR_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) & ~(value)))
+#define RTC_TOG_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_WAR bitfields
+ */
+
+/*!
+ * @name Register RTC_WAR, field TSRW[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Seconds Register are ignored.
+ * - 0b1 - Writes to the Time Seconds Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TSRW field. */
+#define RTC_RD_WAR_TSRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TSRW_MASK) >> RTC_WAR_TSRW_SHIFT)
+#define RTC_BRD_WAR_TSRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TSRW_SHIFT))
+
+/*! @brief Set the TSRW field to a new value. */
+#define RTC_WR_WAR_TSRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TSRW_MASK, RTC_WAR_TSRW(value)))
+#define RTC_BWR_WAR_TSRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TSRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TPRW[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Prescaler Register are ignored.
+ * - 0b1 - Writes to the Time Prescaler Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TPRW field. */
+#define RTC_RD_WAR_TPRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TPRW_MASK) >> RTC_WAR_TPRW_SHIFT)
+#define RTC_BRD_WAR_TPRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TPRW_SHIFT))
+
+/*! @brief Set the TPRW field to a new value. */
+#define RTC_WR_WAR_TPRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TPRW_MASK, RTC_WAR_TPRW(value)))
+#define RTC_BWR_WAR_TPRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TPRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TARW[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Alarm Register are ignored.
+ * - 0b1 - Writes to the Time Alarm Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TARW field. */
+#define RTC_RD_WAR_TARW(base) ((RTC_WAR_REG(base) & RTC_WAR_TARW_MASK) >> RTC_WAR_TARW_SHIFT)
+#define RTC_BRD_WAR_TARW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TARW_SHIFT))
+
+/*! @brief Set the TARW field to a new value. */
+#define RTC_WR_WAR_TARW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TARW_MASK, RTC_WAR_TARW(value)))
+#define RTC_BWR_WAR_TARW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TARW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TCRW[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Compensation Register are ignored.
+ * - 0b1 - Writes to the Time Compensation Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TCRW field. */
+#define RTC_RD_WAR_TCRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TCRW_MASK) >> RTC_WAR_TCRW_SHIFT)
+#define RTC_BRD_WAR_TCRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TCRW_SHIFT))
+
+/*! @brief Set the TCRW field to a new value. */
+#define RTC_WR_WAR_TCRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TCRW_MASK, RTC_WAR_TCRW(value)))
+#define RTC_BWR_WAR_TCRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TCRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field CRW[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Control Register are ignored.
+ * - 0b1 - Writes to the Control Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_CRW field. */
+#define RTC_RD_WAR_CRW(base) ((RTC_WAR_REG(base) & RTC_WAR_CRW_MASK) >> RTC_WAR_CRW_SHIFT)
+#define RTC_BRD_WAR_CRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_CRW_SHIFT))
+
+/*! @brief Set the CRW field to a new value. */
+#define RTC_WR_WAR_CRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_CRW_MASK, RTC_WAR_CRW(value)))
+#define RTC_BWR_WAR_CRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_CRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field SRW[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Status Register are ignored.
+ * - 0b1 - Writes to the Status Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_SRW field. */
+#define RTC_RD_WAR_SRW(base) ((RTC_WAR_REG(base) & RTC_WAR_SRW_MASK) >> RTC_WAR_SRW_SHIFT)
+#define RTC_BRD_WAR_SRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_SRW_SHIFT))
+
+/*! @brief Set the SRW field to a new value. */
+#define RTC_WR_WAR_SRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_SRW_MASK, RTC_WAR_SRW(value)))
+#define RTC_BWR_WAR_SRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_SRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field LRW[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Lock Register are ignored.
+ * - 0b1 - Writes to the Lock Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_LRW field. */
+#define RTC_RD_WAR_LRW(base) ((RTC_WAR_REG(base) & RTC_WAR_LRW_MASK) >> RTC_WAR_LRW_SHIFT)
+#define RTC_BRD_WAR_LRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_LRW_SHIFT))
+
+/*! @brief Set the LRW field to a new value. */
+#define RTC_WR_WAR_LRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_LRW_MASK, RTC_WAR_LRW(value)))
+#define RTC_BWR_WAR_LRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_LRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field IERW[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Interupt Enable Register are ignored.
+ * - 0b1 - Writes to the Interrupt Enable Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_IERW field. */
+#define RTC_RD_WAR_IERW(base) ((RTC_WAR_REG(base) & RTC_WAR_IERW_MASK) >> RTC_WAR_IERW_SHIFT)
+#define RTC_BRD_WAR_IERW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_IERW_SHIFT))
+
+/*! @brief Set the IERW field to a new value. */
+#define RTC_WR_WAR_IERW(base, value) (RTC_RMW_WAR(base, RTC_WAR_IERW_MASK, RTC_WAR_IERW(value)))
+#define RTC_BWR_WAR_IERW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_IERW_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_RAR - RTC Read Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_RAR - RTC Read Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_RAR register
+ */
+/*@{*/
+#define RTC_RD_RAR(base)         (RTC_RAR_REG(base))
+#define RTC_WR_RAR(base, value)  (RTC_RAR_REG(base) = (value))
+#define RTC_RMW_RAR(base, mask, value) (RTC_WR_RAR(base, (RTC_RD_RAR(base) & ~(mask)) | (value)))
+#define RTC_SET_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) |  (value)))
+#define RTC_CLR_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) & ~(value)))
+#define RTC_TOG_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_RAR bitfields
+ */
+
+/*!
+ * @name Register RTC_RAR, field TSRR[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Seconds Register are ignored.
+ * - 0b1 - Reads to the Time Seconds Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TSRR field. */
+#define RTC_RD_RAR_TSRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TSRR_MASK) >> RTC_RAR_TSRR_SHIFT)
+#define RTC_BRD_RAR_TSRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TSRR_SHIFT))
+
+/*! @brief Set the TSRR field to a new value. */
+#define RTC_WR_RAR_TSRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TSRR_MASK, RTC_RAR_TSRR(value)))
+#define RTC_BWR_RAR_TSRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TSRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TPRR[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Pprescaler Register are ignored.
+ * - 0b1 - Reads to the Time Prescaler Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TPRR field. */
+#define RTC_RD_RAR_TPRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TPRR_MASK) >> RTC_RAR_TPRR_SHIFT)
+#define RTC_BRD_RAR_TPRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TPRR_SHIFT))
+
+/*! @brief Set the TPRR field to a new value. */
+#define RTC_WR_RAR_TPRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TPRR_MASK, RTC_RAR_TPRR(value)))
+#define RTC_BWR_RAR_TPRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TPRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TARR[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Alarm Register are ignored.
+ * - 0b1 - Reads to the Time Alarm Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TARR field. */
+#define RTC_RD_RAR_TARR(base) ((RTC_RAR_REG(base) & RTC_RAR_TARR_MASK) >> RTC_RAR_TARR_SHIFT)
+#define RTC_BRD_RAR_TARR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TARR_SHIFT))
+
+/*! @brief Set the TARR field to a new value. */
+#define RTC_WR_RAR_TARR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TARR_MASK, RTC_RAR_TARR(value)))
+#define RTC_BWR_RAR_TARR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TARR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TCRR[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Compensation Register are ignored.
+ * - 0b1 - Reads to the Time Compensation Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TCRR field. */
+#define RTC_RD_RAR_TCRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TCRR_MASK) >> RTC_RAR_TCRR_SHIFT)
+#define RTC_BRD_RAR_TCRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TCRR_SHIFT))
+
+/*! @brief Set the TCRR field to a new value. */
+#define RTC_WR_RAR_TCRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TCRR_MASK, RTC_RAR_TCRR(value)))
+#define RTC_BWR_RAR_TCRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TCRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field CRR[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Control Register are ignored.
+ * - 0b1 - Reads to the Control Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_CRR field. */
+#define RTC_RD_RAR_CRR(base) ((RTC_RAR_REG(base) & RTC_RAR_CRR_MASK) >> RTC_RAR_CRR_SHIFT)
+#define RTC_BRD_RAR_CRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_CRR_SHIFT))
+
+/*! @brief Set the CRR field to a new value. */
+#define RTC_WR_RAR_CRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_CRR_MASK, RTC_RAR_CRR(value)))
+#define RTC_BWR_RAR_CRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_CRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field SRR[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Status Register are ignored.
+ * - 0b1 - Reads to the Status Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_SRR field. */
+#define RTC_RD_RAR_SRR(base) ((RTC_RAR_REG(base) & RTC_RAR_SRR_MASK) >> RTC_RAR_SRR_SHIFT)
+#define RTC_BRD_RAR_SRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_SRR_SHIFT))
+
+/*! @brief Set the SRR field to a new value. */
+#define RTC_WR_RAR_SRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_SRR_MASK, RTC_RAR_SRR(value)))
+#define RTC_BWR_RAR_SRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_SRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field LRR[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Lock Register are ignored.
+ * - 0b1 - Reads to the Lock Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_LRR field. */
+#define RTC_RD_RAR_LRR(base) ((RTC_RAR_REG(base) & RTC_RAR_LRR_MASK) >> RTC_RAR_LRR_SHIFT)
+#define RTC_BRD_RAR_LRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_LRR_SHIFT))
+
+/*! @brief Set the LRR field to a new value. */
+#define RTC_WR_RAR_LRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_LRR_MASK, RTC_RAR_LRR(value)))
+#define RTC_BWR_RAR_LRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_LRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field IERR[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Interrupt Enable Register are ignored.
+ * - 0b1 - Reads to the Interrupt Enable Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_IERR field. */
+#define RTC_RD_RAR_IERR(base) ((RTC_RAR_REG(base) & RTC_RAR_IERR_MASK) >> RTC_RAR_IERR_SHIFT)
+#define RTC_BRD_RAR_IERR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_IERR_SHIFT))
+
+/*! @brief Set the IERR field to a new value. */
+#define RTC_WR_RAR_IERR(base, value) (RTC_RMW_RAR(base, RTC_RAR_IERR_MASK, RTC_RAR_IERR(value)))
+#define RTC_BWR_RAR_IERR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_IERR_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 SDHC
+ *
+ * Secured Digital Host Controller
+ *
+ * Registers defined in this header file:
+ * - SDHC_DSADDR - DMA System Address register
+ * - SDHC_BLKATTR - Block Attributes register
+ * - SDHC_CMDARG - Command Argument register
+ * - SDHC_XFERTYP - Transfer Type register
+ * - SDHC_CMDRSP - Command Response 0
+ * - SDHC_DATPORT - Buffer Data Port register
+ * - SDHC_PRSSTAT - Present State register
+ * - SDHC_PROCTL - Protocol Control register
+ * - SDHC_SYSCTL - System Control register
+ * - SDHC_IRQSTAT - Interrupt Status register
+ * - SDHC_IRQSTATEN - Interrupt Status Enable register
+ * - SDHC_IRQSIGEN - Interrupt Signal Enable register
+ * - SDHC_AC12ERR - Auto CMD12 Error Status Register
+ * - SDHC_HTCAPBLT - Host Controller Capabilities
+ * - SDHC_WML - Watermark Level Register
+ * - SDHC_FEVT - Force Event register
+ * - SDHC_ADMAES - ADMA Error Status register
+ * - SDHC_ADSADDR - ADMA System Addressregister
+ * - SDHC_VENDOR - Vendor Specific register
+ * - SDHC_MMCBOOT - MMC Boot register
+ * - SDHC_HOSTVER - Host Controller Version
+ */
+
+#define SDHC_INSTANCE_COUNT (1U) /*!< Number of instances of the SDHC module. */
+#define SDHC_IDX (0U) /*!< Instance number for SDHC. */
+
+/*******************************************************************************
+ * SDHC_DSADDR - DMA System Address register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_DSADDR - DMA System Address register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for DMA
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_DSADDR register
+ */
+/*@{*/
+#define SDHC_RD_DSADDR(base)     (SDHC_DSADDR_REG(base))
+#define SDHC_WR_DSADDR(base, value) (SDHC_DSADDR_REG(base) = (value))
+#define SDHC_RMW_DSADDR(base, mask, value) (SDHC_WR_DSADDR(base, (SDHC_RD_DSADDR(base) & ~(mask)) | (value)))
+#define SDHC_SET_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) |  (value)))
+#define SDHC_CLR_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) & ~(value)))
+#define SDHC_TOG_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_DSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
+ *
+ * Contains the 32-bit system memory address for a DMA transfer. Because the
+ * address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
+ * When the SDHC stops a DMA transfer, this register points to the system address
+ * of the next contiguous data position. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read operation
+ * during transfers may return an invalid value. The host driver shall initialize
+ * this register before starting a DMA transaction. After DMA has stopped, the
+ * system address of the next contiguous data position can be read from this register.
+ * This register is protected during a data transfer. When data lines are
+ * active, write to this register is ignored. The host driver shall wait, until
+ * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
+ * not support a virtual memory system. It supports only continuous physical
+ * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
+ * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
+ * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
+ * automatically alters the value of internal address counter, so SW cannot
+ * change this register when IRQSTAT[TC] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_DSADDR_DSADDR field. */
+#define SDHC_RD_DSADDR_DSADDR(base) ((SDHC_DSADDR_REG(base) & SDHC_DSADDR_DSADDR_MASK) >> SDHC_DSADDR_DSADDR_SHIFT)
+#define SDHC_BRD_DSADDR_DSADDR(base) (SDHC_RD_DSADDR_DSADDR(base))
+
+/*! @brief Set the DSADDR field to a new value. */
+#define SDHC_WR_DSADDR_DSADDR(base, value) (SDHC_RMW_DSADDR(base, SDHC_DSADDR_DSADDR_MASK, SDHC_DSADDR_DSADDR(value)))
+#define SDHC_BWR_DSADDR_DSADDR(base, value) (SDHC_WR_DSADDR_DSADDR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_BLKATTR - Block Attributes register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_BLKATTR - Block Attributes register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to configure the number of data blocks and the number
+ * of bytes in each block.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_BLKATTR register
+ */
+/*@{*/
+#define SDHC_RD_BLKATTR(base)    (SDHC_BLKATTR_REG(base))
+#define SDHC_WR_BLKATTR(base, value) (SDHC_BLKATTR_REG(base) = (value))
+#define SDHC_RMW_BLKATTR(base, mask, value) (SDHC_WR_BLKATTR(base, (SDHC_RD_BLKATTR(base) & ~(mask)) | (value)))
+#define SDHC_SET_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) |  (value)))
+#define SDHC_CLR_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) & ~(value)))
+#define SDHC_TOG_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_BLKATTR bitfields
+ */
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
+ *
+ * Specifies the block size for block data transfers. Values ranging from 1 byte
+ * up to the maximum buffer size can be set. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read
+ * operations during transfers may return an invalid value, and write operations will be
+ * ignored.
+ *
+ * Values:
+ * - 0b0000000000000 - No data transfer.
+ * - 0b0000000000001 - 1 Byte
+ * - 0b0000000000010 - 2 Bytes
+ * - 0b0000000000011 - 3 Bytes
+ * - 0b0000000000100 - 4 Bytes
+ * - 0b0000111111111 - 511 Bytes
+ * - 0b0001000000000 - 512 Bytes
+ * - 0b0100000000000 - 2048 Bytes
+ * - 0b1000000000000 - 4096 Bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field. */
+#define SDHC_RD_BLKATTR_BLKSIZE(base) ((SDHC_BLKATTR_REG(base) & SDHC_BLKATTR_BLKSIZE_MASK) >> SDHC_BLKATTR_BLKSIZE_SHIFT)
+#define SDHC_BRD_BLKATTR_BLKSIZE(base) (SDHC_RD_BLKATTR_BLKSIZE(base))
+
+/*! @brief Set the BLKSIZE field to a new value. */
+#define SDHC_WR_BLKATTR_BLKSIZE(base, value) (SDHC_RMW_BLKATTR(base, SDHC_BLKATTR_BLKSIZE_MASK, SDHC_BLKATTR_BLKSIZE(value)))
+#define SDHC_BWR_BLKATTR_BLKSIZE(base, value) (SDHC_WR_BLKATTR_BLKSIZE(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
+ *
+ * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
+ * multiple block transfers. For single block transfer, this register will
+ * always read as 1. The host driver shall set this register to a value between 1 and
+ * the maximum block count. The SDHC decrements the block count after each block
+ * transfer and stops when the count reaches zero. Setting the block count to 0
+ * results in no data blocks being transferred. This register must be accessed
+ * only when no transaction is executing, that is, after transactions are stopped.
+ * During data transfer, read operations on this register may return an invalid
+ * value and write operations are ignored. When saving transfer content as a result
+ * of a suspend command, the number of blocks yet to be transferred can be
+ * determined by reading this register. The reading of this register must be applied
+ * after transfer is paused by stop at block gap operation and before sending the
+ * command marked as suspend. This is because when suspend command is sent out,
+ * SDHC will regard the current transfer as aborted and change BLKCNT back to its
+ * original value instead of keeping the dynamical indicator of remained block
+ * count. When restoring transfer content prior to issuing a resume command, the
+ * host driver shall restore the previously saved block count. Although the BLKCNT
+ * field is 0 after reset, the read of reset value is 0x1. This is because when
+ * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
+ * BLKCNT is always 1.
+ *
+ * Values:
+ * - 0b0000000000000000 - Stop count.
+ * - 0b0000000000000001 - 1 block
+ * - 0b0000000000000010 - 2 blocks
+ * - 0b1111111111111111 - 65535 blocks
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_BLKATTR_BLKCNT field. */
+#define SDHC_RD_BLKATTR_BLKCNT(base) ((SDHC_BLKATTR_REG(base) & SDHC_BLKATTR_BLKCNT_MASK) >> SDHC_BLKATTR_BLKCNT_SHIFT)
+#define SDHC_BRD_BLKATTR_BLKCNT(base) (SDHC_RD_BLKATTR_BLKCNT(base))
+
+/*! @brief Set the BLKCNT field to a new value. */
+#define SDHC_WR_BLKATTR_BLKCNT(base, value) (SDHC_RMW_BLKATTR(base, SDHC_BLKATTR_BLKCNT_MASK, SDHC_BLKATTR_BLKCNT(value)))
+#define SDHC_BWR_BLKATTR_BLKCNT(base, value) (SDHC_WR_BLKATTR_BLKCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_CMDARG - Command Argument register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_CMDARG - Command Argument register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the SD/MMC command argument.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_CMDARG register
+ */
+/*@{*/
+#define SDHC_RD_CMDARG(base)     (SDHC_CMDARG_REG(base))
+#define SDHC_WR_CMDARG(base, value) (SDHC_CMDARG_REG(base) = (value))
+#define SDHC_RMW_CMDARG(base, mask, value) (SDHC_WR_CMDARG(base, (SDHC_RD_CMDARG(base) & ~(mask)) | (value)))
+#define SDHC_SET_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) |  (value)))
+#define SDHC_CLR_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) & ~(value)))
+#define SDHC_TOG_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_XFERTYP - Transfer Type register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_XFERTYP - Transfer Type register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to control the operation of data transfers. The host
+ * driver shall set this register before issuing a command followed by a data
+ * transfer, or before issuing a resume command. To prevent data loss, the SDHC
+ * prevents writing to the bits that are involved in the data transfer of this
+ * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
+ * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
+ * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
+ * send a command with data by writing to this register is ignored; when
+ * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
+ * data transfer involved, it is mandatory that the block size is nonzero.
+ * Besides, block count must also be nonzero, or indicated as single block transfer
+ * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
+ * this register is 0 when written), otherwise SDHC will ignore the sending of
+ * this command and do nothing. For write command, with all above restrictions, it
+ * is also mandatory that the write protect switch is not active (WPSPL bit of
+ * Present State Register is 1), otherwise SDHC will also ignore the command. If
+ * the commands with data transfer does not receive the response in 64 clock
+ * cycles, that is, response time-out, SDHC will regard the external device does not
+ * accept the command and abort the data transfer. In this scenario, the driver
+ * must issue the command again to retry the transfer. It is also possible that,
+ * for some reason, the card responds to the command but SDHC does not receive the
+ * response, and if it is internal DMA (either simple DMA or ADMA) read
+ * operation, the external system memory is over-written by the internal DMA with data
+ * sent back from the card. The following table shows the summary of how register
+ * settings determine the type of data transfer. Transfer Type register setting for
+ * various transfer types Multi/Single block select Block count enable Block
+ * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
+ * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
+ * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
+ * in regards to XFERTYP[RSPTYP] as well as the name of the response type.
+ * Relationship between parameters and the name of the response type Response type
+ * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
+ * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
+ * the SDIO specification, response type notation for R5b is not defined. R5
+ * includes R5b in the SDIO specification. But R5b is defined in this specification
+ * to specify that the SDHC will check the busy status after receiving a
+ * response. For example, usually CMD52 is used with R5, but the I/O abort command shall
+ * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
+ * The CRC check shall be disabled for these response types.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_XFERTYP register
+ */
+/*@{*/
+#define SDHC_RD_XFERTYP(base)    (SDHC_XFERTYP_REG(base))
+#define SDHC_WR_XFERTYP(base, value) (SDHC_XFERTYP_REG(base) = (value))
+#define SDHC_RMW_XFERTYP(base, mask, value) (SDHC_WR_XFERTYP(base, (SDHC_RD_XFERTYP(base) & ~(mask)) | (value)))
+#define SDHC_SET_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) |  (value)))
+#define SDHC_CLR_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) & ~(value)))
+#define SDHC_TOG_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_XFERTYP bitfields
+ */
+
+/*!
+ * @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
+ *
+ * Enables DMA functionality. If this bit is set to 1, a DMA operation shall
+ * begin when the host driver sets the DPSEL bit of this register. Whether the
+ * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DMAEN field. */
+#define SDHC_RD_XFERTYP_DMAEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DMAEN_MASK) >> SDHC_XFERTYP_DMAEN_SHIFT)
+#define SDHC_BRD_XFERTYP_DMAEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define SDHC_WR_XFERTYP_DMAEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DMAEN_MASK, SDHC_XFERTYP_DMAEN(value)))
+#define SDHC_BWR_XFERTYP_DMAEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field BCEN[1] (RW)
+ *
+ * Used to enable the Block Count register, which is only relevant for multiple
+ * block transfers. When this bit is 0, the internal counter for block is
+ * disabled, which is useful in executing an infinite transfer.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_BCEN field. */
+#define SDHC_RD_XFERTYP_BCEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_BCEN_MASK) >> SDHC_XFERTYP_BCEN_SHIFT)
+#define SDHC_BRD_XFERTYP_BCEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_BCEN_SHIFT))
+
+/*! @brief Set the BCEN field to a new value. */
+#define SDHC_WR_XFERTYP_BCEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_BCEN_MASK, SDHC_XFERTYP_BCEN(value)))
+#define SDHC_BWR_XFERTYP_BCEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_BCEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
+ *
+ * Multiple block transfers for memory require a CMD12 to stop the transaction.
+ * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
+ * last block transfer has completed. The host driver shall not set this bit to
+ * issue commands that do not require CMD12 to stop a multiple block data
+ * transfer. In particular, secure commands defined in File Security Specification (see
+ * reference list) do not require CMD12. In single block transfer, the SDHC will
+ * ignore this bit whether it is set or not.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_AC12EN field. */
+#define SDHC_RD_XFERTYP_AC12EN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_AC12EN_MASK) >> SDHC_XFERTYP_AC12EN_SHIFT)
+#define SDHC_BRD_XFERTYP_AC12EN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_AC12EN_SHIFT))
+
+/*! @brief Set the AC12EN field to a new value. */
+#define SDHC_WR_XFERTYP_AC12EN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_AC12EN_MASK, SDHC_XFERTYP_AC12EN(value)))
+#define SDHC_BWR_XFERTYP_AC12EN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_AC12EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
+ *
+ * Defines the direction of DAT line data transfers. The bit is set to 1 by the
+ * host driver to transfer data from the SD card to the SDHC and is set to 0 for
+ * all other commands.
+ *
+ * Values:
+ * - 0b0 - Write host to card.
+ * - 0b1 - Read card to host.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DTDSEL field. */
+#define SDHC_RD_XFERTYP_DTDSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DTDSEL_MASK) >> SDHC_XFERTYP_DTDSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_DTDSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DTDSEL_SHIFT))
+
+/*! @brief Set the DTDSEL field to a new value. */
+#define SDHC_WR_XFERTYP_DTDSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DTDSEL_MASK, SDHC_XFERTYP_DTDSEL(value)))
+#define SDHC_BWR_XFERTYP_DTDSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DTDSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
+ *
+ * Enables multiple block DAT line data transfers. For any other commands, this
+ * bit shall be set to 0. If this bit is 0, it is not necessary to set the block
+ * count register.
+ *
+ * Values:
+ * - 0b0 - Single block.
+ * - 0b1 - Multiple blocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_MSBSEL field. */
+#define SDHC_RD_XFERTYP_MSBSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_MSBSEL_MASK) >> SDHC_XFERTYP_MSBSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_MSBSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_MSBSEL_SHIFT))
+
+/*! @brief Set the MSBSEL field to a new value. */
+#define SDHC_WR_XFERTYP_MSBSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_MSBSEL_MASK, SDHC_XFERTYP_MSBSEL(value)))
+#define SDHC_BWR_XFERTYP_MSBSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_MSBSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
+ *
+ * Values:
+ * - 0b00 - No response.
+ * - 0b01 - Response length 136.
+ * - 0b10 - Response length 48.
+ * - 0b11 - Response length 48, check busy after response.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_RSPTYP field. */
+#define SDHC_RD_XFERTYP_RSPTYP(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_RSPTYP_MASK) >> SDHC_XFERTYP_RSPTYP_SHIFT)
+#define SDHC_BRD_XFERTYP_RSPTYP(base) (SDHC_RD_XFERTYP_RSPTYP(base))
+
+/*! @brief Set the RSPTYP field to a new value. */
+#define SDHC_WR_XFERTYP_RSPTYP(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_RSPTYP_MASK, SDHC_XFERTYP_RSPTYP(value)))
+#define SDHC_BWR_XFERTYP_RSPTYP(base, value) (SDHC_WR_XFERTYP_RSPTYP(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
+ *
+ * If this bit is set to 1, the SDHC shall check the CRC field in the response.
+ * If an error is detected, it is reported as a Command CRC Error. If this bit is
+ * set to 0, the CRC field is not checked. The number of bits checked by the CRC
+ * field value changes according to the length of the response.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CCCEN field. */
+#define SDHC_RD_XFERTYP_CCCEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CCCEN_MASK) >> SDHC_XFERTYP_CCCEN_SHIFT)
+#define SDHC_BRD_XFERTYP_CCCEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CCCEN_SHIFT))
+
+/*! @brief Set the CCCEN field to a new value. */
+#define SDHC_WR_XFERTYP_CCCEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CCCEN_MASK, SDHC_XFERTYP_CCCEN(value)))
+#define SDHC_BWR_XFERTYP_CCCEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CCCEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CICEN[20] (RW)
+ *
+ * If this bit is set to 1, the SDHC will check the index field in the response
+ * to see if it has the same value as the command index. If it is not, it is
+ * reported as a command index error. If this bit is set to 0, the index field is not
+ * checked.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CICEN field. */
+#define SDHC_RD_XFERTYP_CICEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CICEN_MASK) >> SDHC_XFERTYP_CICEN_SHIFT)
+#define SDHC_BRD_XFERTYP_CICEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CICEN_SHIFT))
+
+/*! @brief Set the CICEN field to a new value. */
+#define SDHC_WR_XFERTYP_CICEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CICEN_MASK, SDHC_XFERTYP_CICEN(value)))
+#define SDHC_BWR_XFERTYP_CICEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CICEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
+ *
+ * This bit is set to 1 to indicate that data is present and shall be
+ * transferred using the DAT line. It is set to 0 for the following: Commands using only
+ * the CMD line, for example: CMD52. Commands with no data transfer, but using the
+ * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
+ * this bit shall be set, and other bits in this register shall be set the same
+ * as when the transfer was initially launched. When the Write Protect switch is
+ * on, that is, the WPSPL bit is active as 0, any command with a write operation
+ * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
+ * 0, writes to the register Transfer Type are ignored.
+ *
+ * Values:
+ * - 0b0 - No data present.
+ * - 0b1 - Data present.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DPSEL field. */
+#define SDHC_RD_XFERTYP_DPSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DPSEL_MASK) >> SDHC_XFERTYP_DPSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_DPSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DPSEL_SHIFT))
+
+/*! @brief Set the DPSEL field to a new value. */
+#define SDHC_WR_XFERTYP_DPSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DPSEL_MASK, SDHC_XFERTYP_DPSEL(value)))
+#define SDHC_BWR_XFERTYP_DPSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DPSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
+ *
+ * There are three types of special commands: suspend, resume, and abort. These
+ * bits shall be set to 00b for all other commands. Suspend command: If the
+ * suspend command succeeds, the SDHC shall assume that the card bus has been released
+ * and that it is possible to issue the next command which uses the DAT line.
+ * Because the SDHC does not monitor the content of command response, it does not
+ * know if the suspend command succeeded or not. It is the host driver's
+ * responsibility to check the status of the suspend command and send another command
+ * marked as suspend to inform the SDHC that a suspend command was successfully
+ * issued. After the end bit of command is sent, the SDHC deasserts read wait for read
+ * transactions and stops checking busy for write transactions. In 4-bit mode,
+ * the interrupt cycle starts. If the suspend command fails, the SDHC will
+ * maintain its current state, and the host driver shall restart the transfer by setting
+ * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
+ * restoring the registers saved before sending the suspend command and then sends
+ * the resume command. The SDHC will check for a pending busy state before
+ * starting write transfers. Abort command: If this command is set when executing a
+ * read transfer, the SDHC will stop reads to the buffer. If this command is set
+ * when executing a write transfer, the SDHC will stop driving the DAT line. After
+ * issuing the abort command, the host driver must issue a software reset (abort
+ * transaction).
+ *
+ * Values:
+ * - 0b00 - Normal other commands.
+ * - 0b01 - Suspend CMD52 for writing bus suspend in CCCR.
+ * - 0b10 - Resume CMD52 for writing function select in CCCR.
+ * - 0b11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CMDTYP field. */
+#define SDHC_RD_XFERTYP_CMDTYP(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CMDTYP_MASK) >> SDHC_XFERTYP_CMDTYP_SHIFT)
+#define SDHC_BRD_XFERTYP_CMDTYP(base) (SDHC_RD_XFERTYP_CMDTYP(base))
+
+/*! @brief Set the CMDTYP field to a new value. */
+#define SDHC_WR_XFERTYP_CMDTYP(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CMDTYP_MASK, SDHC_XFERTYP_CMDTYP(value)))
+#define SDHC_BWR_XFERTYP_CMDTYP(base, value) (SDHC_WR_XFERTYP_CMDTYP(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
+ *
+ * These bits shall be set to the command number that is specified in bits 45-40
+ * of the command-format in the SD Memory Card Physical Layer Specification and
+ * SDIO Card Specification.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CMDINX field. */
+#define SDHC_RD_XFERTYP_CMDINX(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CMDINX_MASK) >> SDHC_XFERTYP_CMDINX_SHIFT)
+#define SDHC_BRD_XFERTYP_CMDINX(base) (SDHC_RD_XFERTYP_CMDINX(base))
+
+/*! @brief Set the CMDINX field to a new value. */
+#define SDHC_WR_XFERTYP_CMDINX(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CMDINX_MASK, SDHC_XFERTYP_CMDINX(value)))
+#define SDHC_BWR_XFERTYP_CMDINX(base, value) (SDHC_WR_XFERTYP_CMDINX(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_CMDRSP - Command Response 0
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_CMDRSP - Command Response 0 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 0 of the response bits from the card.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP register
+ */
+/*@{*/
+#define SDHC_RD_CMDRSP(base, index) (SDHC_CMDRSP_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_DATPORT - Buffer Data Port register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_DATPORT - Buffer Data Port register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This is a 32-bit data port register used to access the internal buffer and it
+ * cannot be updated in Idle mode.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_DATPORT register
+ */
+/*@{*/
+#define SDHC_RD_DATPORT(base)    (SDHC_DATPORT_REG(base))
+#define SDHC_WR_DATPORT(base, value) (SDHC_DATPORT_REG(base) = (value))
+#define SDHC_RMW_DATPORT(base, mask, value) (SDHC_WR_DATPORT(base, (SDHC_RD_DATPORT(base) & ~(mask)) | (value)))
+#define SDHC_SET_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) |  (value)))
+#define SDHC_CLR_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) & ~(value)))
+#define SDHC_TOG_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_PRSSTAT - Present State register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_PRSSTAT - Present State register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The host driver can get status of the SDHC from this 32-bit read-only
+ * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
+ * SDIO) when the DAT lines are busy during a data transfer. These commands can be
+ * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
+ * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
+ * Physical Specification may add other commands to this list in the future.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_PRSSTAT register
+ */
+/*@{*/
+#define SDHC_RD_PRSSTAT(base)    (SDHC_PRSSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_PRSSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
+ *
+ * If this status bit is 0, it indicates that the CMD line is not in use and the
+ * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
+ * immediately after the Transfer Type register is written. This bit is cleared when
+ * the command response is received. Even if the CDIHB bit is set to 1, Commands
+ * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
+ * generates a command complete interrupt in the interrupt status register. If the
+ * SDHC cannot issue the command because of a command conflict error (see
+ * command CRC error) or because of a command not issued by auto CMD12 error, this bit
+ * will remain 1 and the command complete is not set. The status of issuing an
+ * auto CMD12 does not show on this bit.
+ *
+ * Values:
+ * - 0b0 - Can issue command using only CMD line.
+ * - 0b1 - Cannot issue command.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CIHB field. */
+#define SDHC_RD_PRSSTAT_CIHB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CIHB_MASK) >> SDHC_PRSSTAT_CIHB_SHIFT)
+#define SDHC_BRD_PRSSTAT_CIHB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CIHB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
+ *
+ * This status bit is generated if either the DLA or the RTA is set to 1. If
+ * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
+ * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
+ * the case when the command busy is finished, changing from 1 to 0 generates a
+ * transfer complete interrupt in the Interrupt Status register. The SD host
+ * driver can save registers for a suspend transaction after this bit has changed
+ * from 1 to 0.
+ *
+ * Values:
+ * - 0b0 - Can issue command which uses the DAT line.
+ * - 0b1 - Cannot issue command which uses the DAT line.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CDIHB field. */
+#define SDHC_RD_PRSSTAT_CDIHB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CDIHB_MASK) >> SDHC_PRSSTAT_CDIHB_SHIFT)
+#define SDHC_BRD_PRSSTAT_CDIHB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CDIHB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLA[2] (RO)
+ *
+ * Indicates whether one of the DAT lines on the SD bus is in use. In the case
+ * of read transactions: This status indicates whether a read transfer is
+ * executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
+ * generates a block gap event interrupt in the Interrupt Status register. This bit
+ * will be set in either of the following cases: After the end bit of the read
+ * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
+ * will be cleared in either of the following cases: When the end bit of the last
+ * data block is sent from the SD bus to the SDHC. When the read wait state is
+ * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
+ * the next block gap by driving read wait at the start of the interrupt cycle.
+ * If the read wait signal is already driven (data buffer cannot receive data),
+ * the SDHC can wait for a current block gap by continuing to drive the read wait
+ * signal. It is necessary to support read wait to use the suspend / resume
+ * function. This bit will remain 1 during read wait. In the case of write
+ * transactions: This status indicates that a write transfer is executing on the SD bus.
+ * Changes in this value from 1 to 0 generate a transfer complete interrupt in the
+ * interrupt status register. This bit will be set in either of the following
+ * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
+ * continue a write transfer. This bit will be cleared in either of the
+ * following cases: When the SD card releases write busy of the last data block, the SDHC
+ * will also detect if the output is not busy. If the SD card does not drive the
+ * busy signal after the CRC status is received, the SDHC shall assume the card
+ * drive "Not busy". When the SD card releases write busy, prior to waiting for
+ * write transfer, and as a result of a stop at block gap request. In the case of
+ * command with busy pending: This status indicates that a busy state follows the
+ * command and the data line is in use. This bit will be cleared when the DAT0
+ * line is released.
+ *
+ * Values:
+ * - 0b0 - DAT line inactive.
+ * - 0b1 - DAT line active.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_DLA field. */
+#define SDHC_RD_PRSSTAT_DLA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_DLA_MASK) >> SDHC_PRSSTAT_DLA_SHIFT)
+#define SDHC_BRD_PRSSTAT_DLA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_DLA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
+ *
+ * Indicates that the internal card clock is stable. This bit is for the host
+ * driver to poll clock status when changing the clock frequency. It is recommended
+ * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
+ * frequency is changing.
+ *
+ * Values:
+ * - 0b0 - Clock is changing frequency and not stable.
+ * - 0b1 - Clock is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_SDSTB field. */
+#define SDHC_RD_PRSSTAT_SDSTB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_SDSTB_MASK) >> SDHC_PRSSTAT_SDSTB_SHIFT)
+#define SDHC_BRD_PRSSTAT_SDSTB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_SDSTB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
+ *
+ * Indicates that the bus clock is internally gated off. This bit is for the
+ * host driver to debug.
+ *
+ * Values:
+ * - 0b0 - Bus clock is active.
+ * - 0b1 - Bus clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field. */
+#define SDHC_RD_PRSSTAT_IPGOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_IPGOFF_MASK) >> SDHC_PRSSTAT_IPGOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_IPGOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_IPGOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
+ *
+ * Indicates that the system clock is internally gated off. This bit is for the
+ * host driver to debug during a data transfer.
+ *
+ * Values:
+ * - 0b0 - System clock is active.
+ * - 0b1 - System clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field. */
+#define SDHC_RD_PRSSTAT_HCKOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_HCKOFF_MASK) >> SDHC_PRSSTAT_HCKOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_HCKOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_HCKOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
+ *
+ * Indicates that the is internally gated off. This bit is for the host driver
+ * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
+ * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
+ * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
+ * clock SDHC clock bus clock
+ *
+ * Values:
+ * - 0b0 - SDHC clock is active.
+ * - 0b1 - SDHC clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_PEROFF field. */
+#define SDHC_RD_PRSSTAT_PEROFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_PEROFF_MASK) >> SDHC_PRSSTAT_PEROFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_PEROFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_PEROFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
+ *
+ * Indicates that the SD clock is internally gated off, because of buffer
+ * over/under-run or read pause without read wait assertion, or the driver has cleared
+ * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
+ * data transaction on the SD bus.
+ *
+ * Values:
+ * - 0b0 - SD clock is active.
+ * - 0b1 - SD clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_SDOFF field. */
+#define SDHC_RD_PRSSTAT_SDOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_SDOFF_MASK) >> SDHC_PRSSTAT_SDOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_SDOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_SDOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field WTA[8] (RO)
+ *
+ * Indicates that a write transfer is active. If this bit is 0, it means no
+ * valid write data exists in the SDHC. This bit is set in either of the following
+ * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
+ * restart a write transfer. This bit is cleared in either of the following
+ * cases: After getting the CRC status of the last data block as specified by the
+ * transfer count (single and multiple). After getting the CRC status of any block
+ * where data transmission is about to be stopped by a stop at block gap request.
+ * During a write transaction, a block gap event interrupt is generated when this
+ * bit is changed to 0, as result of the stop at block gap request being set.
+ * This status is useful for the host driver in determining when to issue commands
+ * during write busy state.
+ *
+ * Values:
+ * - 0b0 - No valid data.
+ * - 0b1 - Transferring data.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_WTA field. */
+#define SDHC_RD_PRSSTAT_WTA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_WTA_MASK) >> SDHC_PRSSTAT_WTA_SHIFT)
+#define SDHC_BRD_PRSSTAT_WTA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_WTA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field RTA[9] (RO)
+ *
+ * Used for detecting completion of a read transfer. This bit is set for either
+ * of the following conditions: After the end bit of the read command. When
+ * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
+ * interrupt is generated when this bit changes to 0. This bit is cleared for either of
+ * the following conditions: When the last data block as specified by block
+ * length is transferred to the system, that is, all data are read away from SDHC
+ * internal buffer. When all valid data blocks have been transferred from SDHC
+ * internal buffer to the system and no current block transfers are being sent as a
+ * result of the stop at block gap request being set to 1.
+ *
+ * Values:
+ * - 0b0 - No valid data.
+ * - 0b1 - Transferring data.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_RTA field. */
+#define SDHC_RD_PRSSTAT_RTA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_RTA_MASK) >> SDHC_PRSSTAT_RTA_SHIFT)
+#define SDHC_BRD_PRSSTAT_RTA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_RTA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
+ *
+ * Used for non-DMA write transfers. The SDHC can implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates whether space is
+ * available for write data. If this bit is 1, valid data greater than the watermark
+ * level can be written to the buffer. This read-only flag indicates whether
+ * space is available for write data.
+ *
+ * Values:
+ * - 0b0 - Write disable, the buffer can hold valid data less than the write
+ *     watermark level.
+ * - 0b1 - Write enable, the buffer can hold valid data greater than the write
+ *     watermark level.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_BWEN field. */
+#define SDHC_RD_PRSSTAT_BWEN(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_BWEN_MASK) >> SDHC_PRSSTAT_BWEN_SHIFT)
+#define SDHC_BRD_PRSSTAT_BWEN(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_BWEN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BREN[11] (RO)
+ *
+ * Used for non-DMA read transfers. The SDHC may implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates that valid data exists
+ * in the host side buffer. If this bit is high, valid data greater than the
+ * watermark level exist in the buffer. This read-only flag indicates that valid
+ * data exists in the host side buffer.
+ *
+ * Values:
+ * - 0b0 - Read disable, valid data less than the watermark level exist in the
+ *     buffer.
+ * - 0b1 - Read enable, valid data greater than the watermark level exist in the
+ *     buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_BREN field. */
+#define SDHC_RD_PRSSTAT_BREN(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_BREN_MASK) >> SDHC_PRSSTAT_BREN_SHIFT)
+#define SDHC_BRD_PRSSTAT_BREN(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_BREN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CINS[16] (RO)
+ *
+ * Indicates whether a card has been inserted. The SDHC debounces this signal so
+ * that the host driver will not need to wait for it to stabilize. Changing from
+ * a 0 to 1 generates a card insertion interrupt in the Interrupt Status
+ * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
+ * Status register. A write to the force event register does not effect this bit.
+ * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
+ * bit.
+ *
+ * Values:
+ * - 0b0 - Power on reset or no card.
+ * - 0b1 - Card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CINS field. */
+#define SDHC_RD_PRSSTAT_CINS(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CINS_MASK) >> SDHC_PRSSTAT_CINS_SHIFT)
+#define SDHC_BRD_PRSSTAT_CINS(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CINS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
+ *
+ * Used to check the CMD line level to recover from errors, and for debugging.
+ * The reset value is effected by the external pullup/pulldown resistor, by
+ * default, the read value of this bit after reset is 1b, when the command line is
+ * pulled up.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CLSL field. */
+#define SDHC_RD_PRSSTAT_CLSL(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CLSL_MASK) >> SDHC_PRSSTAT_CLSL_SHIFT)
+#define SDHC_BRD_PRSSTAT_CLSL(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CLSL_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
+ *
+ * Used to check the DAT line level to recover from errors, and for debugging.
+ * This is especially useful in detecting the busy signal level from DAT[0]. The
+ * reset value is effected by the external pullup/pulldown resistors. By default,
+ * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
+ * down and the other lines are pulled up.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_DLSL field. */
+#define SDHC_RD_PRSSTAT_DLSL(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_DLSL_MASK) >> SDHC_PRSSTAT_DLSL_SHIFT)
+#define SDHC_BRD_PRSSTAT_DLSL(base) (SDHC_RD_PRSSTAT_DLSL(base))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_PROCTL - Protocol Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_PROCTL - Protocol Control register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * There are three cases to restart the transfer after stop at the block gap.
+ * Which case is appropriate depends on whether the SDHC issues a suspend command
+ * or the SD card accepts the suspend command: If the host driver does not issue a
+ * suspend command, the continue request shall be used to restart the transfer.
+ * If the host driver issues a suspend command and the SD card accepts it, a
+ * resume command shall be used to restart the transfer. If the host driver issues a
+ * suspend command and the SD card does not accept it, the continue request shall
+ * be used to restart the transfer. Any time stop at block gap request stops the
+ * data transfer, the host driver shall wait for a transfer complete (in the
+ * interrupt status register), before attempting to restart the transfer. When
+ * restarting the data transfer by continue request, the host driver shall clear the
+ * stop at block gap request before or simultaneously.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_PROCTL register
+ */
+/*@{*/
+#define SDHC_RD_PROCTL(base)     (SDHC_PROCTL_REG(base))
+#define SDHC_WR_PROCTL(base, value) (SDHC_PROCTL_REG(base) = (value))
+#define SDHC_RMW_PROCTL(base, mask, value) (SDHC_WR_PROCTL(base, (SDHC_RD_PROCTL(base) & ~(mask)) | (value)))
+#define SDHC_SET_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) |  (value)))
+#define SDHC_CLR_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) & ~(value)))
+#define SDHC_TOG_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_PROCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_PROCTL, field LCTL[0] (RW)
+ *
+ * This bit, fully controlled by the host driver, is used to caution the user
+ * not to remove the card while the card is being accessed. If the software is
+ * going to issue multiple SD commands, this bit can be set during all these
+ * transactions. It is not necessary to change for each transaction. When the software
+ * issues multiple SD commands, setting the bit once before the first command is
+ * sufficient: it is not necessary to reset the bit between commands.
+ *
+ * Values:
+ * - 0b0 - LED off.
+ * - 0b1 - LED on.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_LCTL field. */
+#define SDHC_RD_PROCTL_LCTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_LCTL_MASK) >> SDHC_PROCTL_LCTL_SHIFT)
+#define SDHC_BRD_PROCTL_LCTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_LCTL_SHIFT))
+
+/*! @brief Set the LCTL field to a new value. */
+#define SDHC_WR_PROCTL_LCTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_LCTL_MASK, SDHC_PROCTL_LCTL(value)))
+#define SDHC_BWR_PROCTL_LCTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_LCTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field DTW[2:1] (RW)
+ *
+ * Selects the data width of the SD bus for a data transfer. The host driver
+ * shall set it to match the data width of the card. Possible data transfer width is
+ * 1-bit, 4-bits or 8-bits.
+ *
+ * Values:
+ * - 0b00 - 1-bit mode
+ * - 0b01 - 4-bit mode
+ * - 0b10 - 8-bit mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_DTW field. */
+#define SDHC_RD_PROCTL_DTW(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_DTW_MASK) >> SDHC_PROCTL_DTW_SHIFT)
+#define SDHC_BRD_PROCTL_DTW(base) (SDHC_RD_PROCTL_DTW(base))
+
+/*! @brief Set the DTW field to a new value. */
+#define SDHC_WR_PROCTL_DTW(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_DTW_MASK, SDHC_PROCTL_DTW(value)))
+#define SDHC_BWR_PROCTL_DTW(base, value) (SDHC_WR_PROCTL_DTW(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field D3CD[3] (RW)
+ *
+ * If this bit is set, DAT3 should be pulled down to act as a card detection
+ * pin. Be cautious when using this feature, because DAT3 is also a chip-select for
+ * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
+ * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
+ * is used.
+ *
+ * Values:
+ * - 0b0 - DAT3 does not monitor card Insertion.
+ * - 0b1 - DAT3 as card detection pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_D3CD field. */
+#define SDHC_RD_PROCTL_D3CD(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_D3CD_MASK) >> SDHC_PROCTL_D3CD_SHIFT)
+#define SDHC_BRD_PROCTL_D3CD(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_D3CD_SHIFT))
+
+/*! @brief Set the D3CD field to a new value. */
+#define SDHC_WR_PROCTL_D3CD(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_D3CD_MASK, SDHC_PROCTL_D3CD(value)))
+#define SDHC_BWR_PROCTL_D3CD(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_D3CD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
+ *
+ * The SDHC supports all four endian modes in data transfer.
+ *
+ * Values:
+ * - 0b00 - Big endian mode
+ * - 0b01 - Half word big endian mode
+ * - 0b10 - Little endian mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_EMODE field. */
+#define SDHC_RD_PROCTL_EMODE(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_EMODE_MASK) >> SDHC_PROCTL_EMODE_SHIFT)
+#define SDHC_BRD_PROCTL_EMODE(base) (SDHC_RD_PROCTL_EMODE(base))
+
+/*! @brief Set the EMODE field to a new value. */
+#define SDHC_WR_PROCTL_EMODE(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_EMODE_MASK, SDHC_PROCTL_EMODE(value)))
+#define SDHC_BWR_PROCTL_EMODE(base, value) (SDHC_WR_PROCTL_EMODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CDTL[6] (RW)
+ *
+ * Enabled while the CDSS is set to 1 and it indicates card insertion.
+ *
+ * Values:
+ * - 0b0 - Card detect test level is 0, no card inserted.
+ * - 0b1 - Card detect test level is 1, card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CDTL field. */
+#define SDHC_RD_PROCTL_CDTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CDTL_MASK) >> SDHC_PROCTL_CDTL_SHIFT)
+#define SDHC_BRD_PROCTL_CDTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDTL_SHIFT))
+
+/*! @brief Set the CDTL field to a new value. */
+#define SDHC_WR_PROCTL_CDTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CDTL_MASK, SDHC_PROCTL_CDTL(value)))
+#define SDHC_BWR_PROCTL_CDTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CDSS[7] (RW)
+ *
+ * Selects the source for the card detection.
+ *
+ * Values:
+ * - 0b0 - Card detection level is selected for normal purpose.
+ * - 0b1 - Card detection test level is selected for test purpose.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CDSS field. */
+#define SDHC_RD_PROCTL_CDSS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CDSS_MASK) >> SDHC_PROCTL_CDSS_SHIFT)
+#define SDHC_BRD_PROCTL_CDSS(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDSS_SHIFT))
+
+/*! @brief Set the CDSS field to a new value. */
+#define SDHC_WR_PROCTL_CDSS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CDSS_MASK, SDHC_PROCTL_CDSS(value)))
+#define SDHC_BWR_PROCTL_CDSS(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDSS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
+ *
+ * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
+ * operation.
+ *
+ * Values:
+ * - 0b00 - No DMA or simple DMA is selected.
+ * - 0b01 - ADMA1 is selected.
+ * - 0b10 - ADMA2 is selected.
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_DMAS field. */
+#define SDHC_RD_PROCTL_DMAS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT)
+#define SDHC_BRD_PROCTL_DMAS(base) (SDHC_RD_PROCTL_DMAS(base))
+
+/*! @brief Set the DMAS field to a new value. */
+#define SDHC_WR_PROCTL_DMAS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_DMAS_MASK, SDHC_PROCTL_DMAS(value)))
+#define SDHC_BWR_PROCTL_DMAS(base, value) (SDHC_WR_PROCTL_DMAS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
+ *
+ * Used to stop executing a transaction at the next block gap for both DMA and
+ * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
+ * transfer completion, the host driver shall leave this bit set to 1. Clearing both
+ * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
+ * Wait is used to stop the read transaction at the block gap. The SDHC will
+ * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
+ * that SDIO card support read wait. Therefore, the host driver shall not set
+ * this bit during read transfers unless the SDIO card supports read wait and has
+ * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
+ * the read operation during block gap. In the case of write transfers in which
+ * the host driver writes data to the data port register, the host driver shall set
+ * this bit after all block data is written. If this bit is set to 1, the host
+ * driver shall not write data to the Data Port register after a block is sent.
+ * Once this bit is set, the host driver shall not clear this bit before
+ * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
+ * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
+ *
+ * Values:
+ * - 0b0 - Transfer
+ * - 0b1 - Stop
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_SABGREQ field. */
+#define SDHC_RD_PROCTL_SABGREQ(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_SABGREQ_MASK) >> SDHC_PROCTL_SABGREQ_SHIFT)
+#define SDHC_BRD_PROCTL_SABGREQ(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_SABGREQ_SHIFT))
+
+/*! @brief Set the SABGREQ field to a new value. */
+#define SDHC_WR_PROCTL_SABGREQ(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_SABGREQ_MASK, SDHC_PROCTL_SABGREQ(value)))
+#define SDHC_BWR_PROCTL_SABGREQ(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_SABGREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CREQ[17] (RW)
+ *
+ * Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
+ * When a suspend operation is not accepted by the card, it is also by setting this
+ * bit to restart the paused transfer. To cancel stop at the block gap, set
+ * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
+ * automatically clears this bit, therefore it is not necessary for the host driver to
+ * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
+ * request is ignored.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Restart
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CREQ field. */
+#define SDHC_RD_PROCTL_CREQ(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CREQ_MASK) >> SDHC_PROCTL_CREQ_SHIFT)
+#define SDHC_BRD_PROCTL_CREQ(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CREQ_SHIFT))
+
+/*! @brief Set the CREQ field to a new value. */
+#define SDHC_WR_PROCTL_CREQ(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CREQ_MASK, SDHC_PROCTL_CREQ(value)))
+#define SDHC_BWR_PROCTL_CREQ(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field RWCTL[18] (RW)
+ *
+ * The read wait function is optional for SDIO cards. If the card supports read
+ * wait, set this bit to enable use of the read wait protocol to stop read data
+ * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
+ * read data, which restricts commands generation. When the host driver detects an
+ * SDIO card insertion, it shall set this bit according to the CCCR of the card.
+ * If the card does not support read wait, this bit shall never be set to 1,
+ * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
+ * during read operation is also supported, but the SDHC will stop the SD Clock
+ * to pause reading operation.
+ *
+ * Values:
+ * - 0b0 - Disable read wait control, and stop SD clock at block gap when
+ *     SABGREQ is set.
+ * - 0b1 - Enable read wait control, and assert read wait without stopping SD
+ *     clock at block gap when SABGREQ bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_RWCTL field. */
+#define SDHC_RD_PROCTL_RWCTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_RWCTL_MASK) >> SDHC_PROCTL_RWCTL_SHIFT)
+#define SDHC_BRD_PROCTL_RWCTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_RWCTL_SHIFT))
+
+/*! @brief Set the RWCTL field to a new value. */
+#define SDHC_WR_PROCTL_RWCTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_RWCTL_MASK, SDHC_PROCTL_RWCTL(value)))
+#define SDHC_BWR_PROCTL_RWCTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_RWCTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field IABG[19] (RW)
+ *
+ * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
+ * interrupt cycle. Setting to 1 enables interrupt detection at the block gap
+ * for a multiple block transfer. Setting to 0 disables interrupt detection during
+ * a multiple block transfer. If the SDIO card can't signal an interrupt during a
+ * multiple block transfer, this bit must be set to 0 to avoid an inadvertent
+ * interrupt. When the host driver detects an SDIO card insertion, it shall set
+ * this bit according to the CCCR of the card.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_IABG field. */
+#define SDHC_RD_PROCTL_IABG(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_IABG_MASK) >> SDHC_PROCTL_IABG_SHIFT)
+#define SDHC_BRD_PROCTL_IABG(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_IABG_SHIFT))
+
+/*! @brief Set the IABG field to a new value. */
+#define SDHC_WR_PROCTL_IABG(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_IABG_MASK, SDHC_PROCTL_IABG(value)))
+#define SDHC_BWR_PROCTL_IABG(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_IABG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINT[24] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
+ * (Wake Up Support) in CIS is set to 1. When this bit is set, the card
+ * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
+ * the wakeup feature is not enabled, the SD_CLK must be active to assert the
+ * card interrupt status and the SDHC interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECINT field. */
+#define SDHC_RD_PROCTL_WECINT(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECINT_MASK) >> SDHC_PROCTL_WECINT_SHIFT)
+#define SDHC_BRD_PROCTL_WECINT(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINT_SHIFT))
+
+/*! @brief Set the WECINT field to a new value. */
+#define SDHC_WR_PROCTL_WECINT(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECINT_MASK, SDHC_PROCTL_WECINT(value)))
+#define SDHC_BWR_PROCTL_WECINT(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINS[25] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
+ * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
+ * interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECINS field. */
+#define SDHC_RD_PROCTL_WECINS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECINS_MASK) >> SDHC_PROCTL_WECINS_SHIFT)
+#define SDHC_BRD_PROCTL_WECINS(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINS_SHIFT))
+
+/*! @brief Set the WECINS field to a new value. */
+#define SDHC_WR_PROCTL_WECINS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECINS_MASK, SDHC_PROCTL_WECINS(value)))
+#define SDHC_BWR_PROCTL_WECINS(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECRM[26] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
+ * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECRM field. */
+#define SDHC_RD_PROCTL_WECRM(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECRM_MASK) >> SDHC_PROCTL_WECRM_SHIFT)
+#define SDHC_BRD_PROCTL_WECRM(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECRM_SHIFT))
+
+/*! @brief Set the WECRM field to a new value. */
+#define SDHC_WR_PROCTL_WECRM(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECRM_MASK, SDHC_PROCTL_WECRM(value)))
+#define SDHC_BWR_PROCTL_WECRM(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECRM_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_SYSCTL - System Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_SYSCTL - System Control register (RW)
+ *
+ * Reset value: 0x00008008U
+ */
+/*!
+ * @name Constants and macros for entire SDHC_SYSCTL register
+ */
+/*@{*/
+#define SDHC_RD_SYSCTL(base)     (SDHC_SYSCTL_REG(base))
+#define SDHC_WR_SYSCTL(base, value) (SDHC_SYSCTL_REG(base) = (value))
+#define SDHC_RMW_SYSCTL(base, mask, value) (SDHC_WR_SYSCTL(base, (SDHC_RD_SYSCTL(base) & ~(mask)) | (value)))
+#define SDHC_SET_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) |  (value)))
+#define SDHC_CLR_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) & ~(value)))
+#define SDHC_TOG_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_SYSCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
+ *
+ * If this bit is set, bus clock will always be active and no automatic gating
+ * is applied. The bus clock will be internally gated off, if none of the
+ * following factors are met: The cmd part is reset, or Data part is reset, or Soft
+ * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
+ * request is just set, or This bit is set, or Card insertion is detected, or Card
+ * removal is detected, or Card external interrupt is detected, or The SDHC
+ * clock is not gated off The bus clock will not be auto gated off if the SDHC clock
+ * is not gated off. So clearing only this bit has no effect unless the PEREN bit
+ * is also cleared.
+ *
+ * Values:
+ * - 0b0 - Bus clock will be internally gated off.
+ * - 0b1 - Bus clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_IPGEN field. */
+#define SDHC_RD_SYSCTL_IPGEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_IPGEN_MASK) >> SDHC_SYSCTL_IPGEN_SHIFT)
+#define SDHC_BRD_SYSCTL_IPGEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_IPGEN_SHIFT))
+
+/*! @brief Set the IPGEN field to a new value. */
+#define SDHC_WR_SYSCTL_IPGEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_IPGEN_MASK, SDHC_SYSCTL_IPGEN(value)))
+#define SDHC_BWR_SYSCTL_IPGEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_IPGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
+ *
+ * If this bit is set, system clock will always be active and no automatic
+ * gating is applied. When this bit is cleared, system clock will be automatically off
+ * when no data transfer is on the SD bus.
+ *
+ * Values:
+ * - 0b0 - System clock will be internally gated off.
+ * - 0b1 - System clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_HCKEN field. */
+#define SDHC_RD_SYSCTL_HCKEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_HCKEN_MASK) >> SDHC_SYSCTL_HCKEN_SHIFT)
+#define SDHC_BRD_SYSCTL_HCKEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_HCKEN_SHIFT))
+
+/*! @brief Set the HCKEN field to a new value. */
+#define SDHC_WR_SYSCTL_HCKEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_HCKEN_MASK, SDHC_SYSCTL_HCKEN(value)))
+#define SDHC_BWR_SYSCTL_HCKEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_HCKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field PEREN[2] (RW)
+ *
+ * If this bit is set, SDHC clock will always be active and no automatic gating
+ * is applied. Thus the SDCLK is active except for when auto gating-off during
+ * buffer danger (buffer about to over-run or under-run). When this bit is cleared,
+ * the SDHC clock will be automatically off whenever there is no transaction on
+ * the SD bus. Because this bit is only a feature enabling bit, clearing this bit
+ * does not stop SDCLK immediately. The SDHC clock will be internally gated off,
+ * if none of the following factors are met: The cmd part is reset, or Data part
+ * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
+ * just updated, or Continue request is just set, or This bit is set, or Card
+ * insertion is detected, or Card removal is detected, or Card external interrupt is
+ * detected, or 80 clocks for initialization phase is ongoing
+ *
+ * Values:
+ * - 0b0 - SDHC clock will be internally gated off.
+ * - 0b1 - SDHC clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_PEREN field. */
+#define SDHC_RD_SYSCTL_PEREN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_PEREN_MASK) >> SDHC_SYSCTL_PEREN_SHIFT)
+#define SDHC_BRD_SYSCTL_PEREN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_PEREN_SHIFT))
+
+/*! @brief Set the PEREN field to a new value. */
+#define SDHC_WR_SYSCTL_PEREN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_PEREN_MASK, SDHC_SYSCTL_PEREN(value)))
+#define SDHC_BWR_SYSCTL_PEREN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_PEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
+ *
+ * The host controller shall stop SDCLK when writing this bit to 0. SDCLK
+ * frequency can be changed when this bit is 0. Then, the host controller shall
+ * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
+ * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
+ * power.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field. */
+#define SDHC_RD_SYSCTL_SDCLKEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_SDCLKEN_MASK) >> SDHC_SYSCTL_SDCLKEN_SHIFT)
+#define SDHC_BRD_SYSCTL_SDCLKEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_SDCLKEN_SHIFT))
+
+/*! @brief Set the SDCLKEN field to a new value. */
+#define SDHC_WR_SYSCTL_SDCLKEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_SDCLKEN_MASK, SDHC_SYSCTL_SDCLKEN(value)))
+#define SDHC_BWR_SYSCTL_SDCLKEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_SDCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
+ *
+ * Used to provide a more exact divisor to generate the desired SD clock
+ * frequency. Note the divider can even support odd divisor without deterioration of
+ * duty cycle. The setting are as following:
+ *
+ * Values:
+ * - 0b0000 - Divisor by 1.
+ * - 0b0001 - Divisor by 2.
+ * - 0b1110 - Divisor by 15.
+ * - 0b1111 - Divisor by 16.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_DVS field. */
+#define SDHC_RD_SYSCTL_DVS(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_DVS_MASK) >> SDHC_SYSCTL_DVS_SHIFT)
+#define SDHC_BRD_SYSCTL_DVS(base) (SDHC_RD_SYSCTL_DVS(base))
+
+/*! @brief Set the DVS field to a new value. */
+#define SDHC_WR_SYSCTL_DVS(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_DVS_MASK, SDHC_SYSCTL_DVS(value)))
+#define SDHC_BWR_SYSCTL_DVS(base, value) (SDHC_WR_SYSCTL_DVS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
+ *
+ * Used to select the frequency of the SDCLK pin. The frequency is not
+ * programmed directly. Rather this register holds the prescaler (this register) and
+ * divisor (next register) of the base clock frequency register. Setting 00h bypasses
+ * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
+ * behavior of this prescaler is undefined. The two default divider values can
+ * be calculated by the frequency of SDHC clock and the following divisor bits.
+ * The frequency of SDCLK is set by the following formula: Clock frequency = (Base
+ * clock) / (prescaler x divisor) For example, if the base clock frequency is 96
+ * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
+ * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
+ * less than or equal to the target. Similarly, to approach a clock value of 400
+ * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
+ * value of 400 kHz. The reset value of this field is 80h, so if the input base
+ * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
+ * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
+ * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
+ * never exceed this limit. Only the following settings are allowed:
+ *
+ * Values:
+ * - 0b00000001 - Base clock divided by 2.
+ * - 0b00000010 - Base clock divided by 4.
+ * - 0b00000100 - Base clock divided by 8.
+ * - 0b00001000 - Base clock divided by 16.
+ * - 0b00010000 - Base clock divided by 32.
+ * - 0b00100000 - Base clock divided by 64.
+ * - 0b01000000 - Base clock divided by 128.
+ * - 0b10000000 - Base clock divided by 256.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field. */
+#define SDHC_RD_SYSCTL_SDCLKFS(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_SDCLKFS_MASK) >> SDHC_SYSCTL_SDCLKFS_SHIFT)
+#define SDHC_BRD_SYSCTL_SDCLKFS(base) (SDHC_RD_SYSCTL_SDCLKFS(base))
+
+/*! @brief Set the SDCLKFS field to a new value. */
+#define SDHC_WR_SYSCTL_SDCLKFS(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_SDCLKFS_MASK, SDHC_SYSCTL_SDCLKFS(value)))
+#define SDHC_BWR_SYSCTL_SDCLKFS(base, value) (SDHC_WR_SYSCTL_SDCLKFS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
+ *
+ * Determines the interval by which DAT line timeouts are detected. See
+ * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
+ * clock frequency will be generated by dividing the base clock SDCLK value by this
+ * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
+ * time-out events.
+ *
+ * Values:
+ * - 0b0000 - SDCLK x 2 13
+ * - 0b0001 - SDCLK x 2 14
+ * - 0b1110 - SDCLK x 2 27
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_DTOCV field. */
+#define SDHC_RD_SYSCTL_DTOCV(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_DTOCV_MASK) >> SDHC_SYSCTL_DTOCV_SHIFT)
+#define SDHC_BRD_SYSCTL_DTOCV(base) (SDHC_RD_SYSCTL_DTOCV(base))
+
+/*! @brief Set the DTOCV field to a new value. */
+#define SDHC_WR_SYSCTL_DTOCV(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_DTOCV_MASK, SDHC_SYSCTL_DTOCV(value)))
+#define SDHC_BWR_SYSCTL_DTOCV(base, value) (SDHC_WR_SYSCTL_DTOCV(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
+ *
+ * Effects the entire host controller except for the card detection circuit.
+ * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
+ * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
+ * reset this bit to 0 when the capabilities registers are valid and the host driver
+ * can read them. Additional use of software reset for all does not affect the
+ * value of the capabilities registers. After this bit is set, it is recommended
+ * that the host driver reset the external card and reinitialize it.
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define SDHC_WR_SYSCTL_RSTA(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTA_MASK, SDHC_SYSCTL_RSTA(value)))
+#define SDHC_BWR_SYSCTL_RSTA(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
+ *
+ * Only part of the command circuit is reset. The following registers and bits
+ * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTC field to a new value. */
+#define SDHC_WR_SYSCTL_RSTC(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTC_MASK, SDHC_SYSCTL_RSTC(value)))
+#define SDHC_BWR_SYSCTL_RSTC(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
+ *
+ * Only part of the data circuit is reset. DMA circuit is also reset. The
+ * following registers and bits are cleared by this bit: Data Port register Buffer Is
+ * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
+ * Enable Read Transfer Active Write Transfer Active DAT Line Active Command
+ * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
+ * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
+ * Block Gap Event Transfer Complete
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTD field to a new value. */
+#define SDHC_WR_SYSCTL_RSTD(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTD_MASK, SDHC_SYSCTL_RSTD(value)))
+#define SDHC_BWR_SYSCTL_RSTD(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field INITA[27] (RW)
+ *
+ * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
+ * are sent, this bit is self-cleared. This bit is very useful during the card
+ * power-up period when 74 SD-clocks are needed and the clock auto gating feature
+ * is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
+ * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
+ * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
+ * when command line or data lines are active, write to this bit is not allowed.
+ * On the otherhand, when this bit is set, that is, during intialization active
+ * period, it is allowed to issue command, and the command bit stream will appear
+ * on the CMD pad after all 80 clock cycles are done. So when this command ends,
+ * the driver can make sure the 80 clock cycles are sent out. This is very useful
+ * when the driver needs send 80 cycles to the card and does not want to wait
+ * till this bit is self-cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_INITA field. */
+#define SDHC_RD_SYSCTL_INITA(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_INITA_MASK) >> SDHC_SYSCTL_INITA_SHIFT)
+#define SDHC_BRD_SYSCTL_INITA(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_INITA_SHIFT))
+
+/*! @brief Set the INITA field to a new value. */
+#define SDHC_WR_SYSCTL_INITA(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_INITA_MASK, SDHC_SYSCTL_INITA(value)))
+#define SDHC_BWR_SYSCTL_INITA(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_INITA_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSTAT - Interrupt Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * An interrupt is generated when the Normal Interrupt Signal Enable is enabled
+ * and at least one of the status bits is set to 1. For all bits, writing 1 to a
+ * bit clears it; writing to 0 keeps the bit unchanged. More than one status can
+ * be cleared with a single register write. For Card Interrupt, before writing 1
+ * to clear, it is required that the card stops asserting the interrupt, meaning
+ * that when the Card Driver services the interrupt condition, otherwise the CINT
+ * bit will be asserted again. The table below shows the relationship between
+ * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
+ * complete Command timeout error Meaning of the status 0 0 X X 1 Response not
+ * received within 64 SDCLK cycles 1 0 Response received The table below shows the
+ * relationship between the Transfer Complete and the Data Timeout Error. SDHC status
+ * for data timeout error/transfer complete bit combinations Transfer complete
+ * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
+ * transfer 1 X Data transfer complete The table below shows the relationship between
+ * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
+ * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
+ * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
+ * CMD line conflict
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTAT register
+ */
+/*@{*/
+#define SDHC_RD_IRQSTAT(base)    (SDHC_IRQSTAT_REG(base))
+#define SDHC_WR_IRQSTAT(base, value) (SDHC_IRQSTAT_REG(base) = (value))
+#define SDHC_RMW_IRQSTAT(base, mask, value) (SDHC_WR_IRQSTAT(base, (SDHC_RD_IRQSTAT(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) |  (value)))
+#define SDHC_CLR_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) & ~(value)))
+#define SDHC_TOG_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CC[0] (W1C)
+ *
+ * This bit is set when you receive the end bit of the command response, except
+ * Auto CMD12. See PRSSTAT[CIHB].
+ *
+ * Values:
+ * - 0b0 - Command not complete.
+ * - 0b1 - Command complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CC field. */
+#define SDHC_RD_IRQSTAT_CC(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CC_MASK) >> SDHC_IRQSTAT_CC_SHIFT)
+#define SDHC_BRD_IRQSTAT_CC(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CC_SHIFT))
+
+/*! @brief Set the CC field to a new value. */
+#define SDHC_WR_IRQSTAT_CC(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CC(value)))
+#define SDHC_BWR_IRQSTAT_CC(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field TC[1] (W1C)
+ *
+ * This bit is set when a read or write transfer is completed. In the case of a
+ * read transaction: This bit is set at the falling edge of the read transfer
+ * active status. There are two cases in which this interrupt is generated. The
+ * first is when a data transfer is completed as specified by the data length, after
+ * the last data has been read to the host system. The second is when data has
+ * stopped at the block gap and completed the data transfer by setting
+ * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
+ * transaction: This bit is set at the falling edge of the DAT line active
+ * status. There are two cases in which this interrupt is generated. The first is when
+ * the last data is written to the SD card as specified by the data length and
+ * the busy signal is released. The second is when data transfers are stopped at
+ * the block gap, by setting PROCTL[SABGREQ], and the data transfers are
+ * completed,after valid data is written to the SD card and the busy signal released.
+ *
+ * Values:
+ * - 0b0 - Transfer not complete.
+ * - 0b1 - Transfer complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_TC field. */
+#define SDHC_RD_IRQSTAT_TC(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_TC_MASK) >> SDHC_IRQSTAT_TC_SHIFT)
+#define SDHC_BRD_IRQSTAT_TC(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_TC_SHIFT))
+
+/*! @brief Set the TC field to a new value. */
+#define SDHC_WR_IRQSTAT_TC(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_TC(value)))
+#define SDHC_BWR_IRQSTAT_TC(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_TC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
+ *
+ * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
+ * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
+ * set to 1. In the case of a read transaction: This bit is set at the falling
+ * edge of the DAT line active status, when the transaction is stopped at SD Bus
+ * timing. The read wait must be supported in order to use this function. In the
+ * case of write transaction: This bit is set at the falling edge of write transfer
+ * active status, after getting CRC status at SD bus timing.
+ *
+ * Values:
+ * - 0b0 - No block gap event.
+ * - 0b1 - Transaction stopped at block gap.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BGE field. */
+#define SDHC_RD_IRQSTAT_BGE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BGE_MASK) >> SDHC_IRQSTAT_BGE_SHIFT)
+#define SDHC_BRD_IRQSTAT_BGE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BGE_SHIFT))
+
+/*! @brief Set the BGE field to a new value. */
+#define SDHC_WR_IRQSTAT_BGE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BGE(value)))
+#define SDHC_BWR_IRQSTAT_BGE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
+ *
+ * Occurs only when the internal DMA finishes the data transfer successfully.
+ * Whenever errors occur during data transfer, this bit will not be set. Instead,
+ * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
+ * this bit will be set.
+ *
+ * Values:
+ * - 0b0 - No DMA Interrupt.
+ * - 0b1 - DMA Interrupt is generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DINT field. */
+#define SDHC_RD_IRQSTAT_DINT(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DINT_MASK) >> SDHC_IRQSTAT_DINT_SHIFT)
+#define SDHC_BRD_IRQSTAT_DINT(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DINT_SHIFT))
+
+/*! @brief Set the DINT field to a new value. */
+#define SDHC_WR_IRQSTAT_DINT(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DINT(value)))
+#define SDHC_BWR_IRQSTAT_DINT(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
+ *
+ * This status bit is set if the Buffer Write Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0b0 - Not ready to write buffer.
+ * - 0b1 - Ready to write buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BWR field. */
+#define SDHC_RD_IRQSTAT_BWR(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BWR_MASK) >> SDHC_IRQSTAT_BWR_SHIFT)
+#define SDHC_BRD_IRQSTAT_BWR(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BWR_SHIFT))
+
+/*! @brief Set the BWR field to a new value. */
+#define SDHC_WR_IRQSTAT_BWR(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BWR(value)))
+#define SDHC_BWR_IRQSTAT_BWR(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BWR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
+ *
+ * This status bit is set if the Buffer Read Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0b0 - Not ready to read buffer.
+ * - 0b1 - Ready to read buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BRR field. */
+#define SDHC_RD_IRQSTAT_BRR(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BRR_MASK) >> SDHC_IRQSTAT_BRR_SHIFT)
+#define SDHC_BRD_IRQSTAT_BRR(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BRR_SHIFT))
+
+/*! @brief Set the BRR field to a new value. */
+#define SDHC_WR_IRQSTAT_BRR(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BRR(value)))
+#define SDHC_BWR_IRQSTAT_BRR(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 0 to 1. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if a card is inserted. To leave it cleared,
+ * clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0b0 - Card state unstable or removed.
+ * - 0b1 - Card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CINS field. */
+#define SDHC_RD_IRQSTAT_CINS(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CINS_MASK) >> SDHC_IRQSTAT_CINS_SHIFT)
+#define SDHC_BRD_IRQSTAT_CINS(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINS_SHIFT))
+
+/*! @brief Set the CINS field to a new value. */
+#define SDHC_WR_IRQSTAT_CINS(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CINS(value)))
+#define SDHC_BWR_IRQSTAT_CINS(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 1 to 0. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if no card is inserted. To leave it cleared,
+ * clear the Card Removal Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0b0 - Card state unstable or inserted.
+ * - 0b1 - Card removed.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CRM field. */
+#define SDHC_RD_IRQSTAT_CRM(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CRM_MASK) >> SDHC_IRQSTAT_CRM_SHIFT)
+#define SDHC_BRD_IRQSTAT_CRM(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CRM_SHIFT))
+
+/*! @brief Set the CRM field to a new value. */
+#define SDHC_WR_IRQSTAT_CRM(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CRM(value)))
+#define SDHC_BWR_IRQSTAT_CRM(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CRM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
+ *
+ * This status bit is set when an interrupt signal is detected from the external
+ * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
+ * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
+ * during the interrupt cycle, so the interrupt from card can only be sampled
+ * during interrupt cycle, introducing some delay between the interrupt signal from
+ * the SDIO card and the interrupt to the host system. Writing this bit to 1 can
+ * clear this bit, but as the interrupt factor from the SDIO card does not clear,
+ * this bit is set again. To clear this bit, it is required to reset the interrupt
+ * factor from the external card followed by a writing 1 to this bit. When this
+ * status has been set, and the host driver needs to service this interrupt, the
+ * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
+ * 0 to stop driving the interrupt signal to the host system. After completion
+ * of the card interrupt service (it must reset the interrupt factors in the SDIO
+ * card and the interrupt signal may not be asserted), write 1 to clear this bit,
+ * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
+ * signal again.
+ *
+ * Values:
+ * - 0b0 - No Card Interrupt.
+ * - 0b1 - Generate Card Interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CINT field. */
+#define SDHC_RD_IRQSTAT_CINT(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CINT_MASK) >> SDHC_IRQSTAT_CINT_SHIFT)
+#define SDHC_BRD_IRQSTAT_CINT(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINT_SHIFT))
+
+/*! @brief Set the CINT field to a new value. */
+#define SDHC_WR_IRQSTAT_CINT(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CINT(value)))
+#define SDHC_BWR_IRQSTAT_CINT(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
+ *
+ * Occurs only if no response is returned within 64 SDCLK cycles from the end
+ * bit of the command. If the SDHC detects a CMD line conflict, in which case a
+ * Command CRC Error shall also be set, this bit shall be set without waiting for 64
+ * SDCLK cycles. This is because the command will be aborted by the SDHC.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CTOE field. */
+#define SDHC_RD_IRQSTAT_CTOE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CTOE_MASK) >> SDHC_IRQSTAT_CTOE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CTOE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CTOE_SHIFT))
+
+/*! @brief Set the CTOE field to a new value. */
+#define SDHC_WR_IRQSTAT_CTOE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CTOE(value)))
+#define SDHC_BWR_IRQSTAT_CTOE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
+ *
+ * Command CRC Error is generated in two cases. If a response is returned and
+ * the Command Timeout Error is set to 0, indicating no time-out, this bit is set
+ * when detecting a CRC error in the command response. The SDHC detects a CMD line
+ * conflict by monitoring the CMD line when a command is issued. If the SDHC
+ * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
+ * then the SDHC shall abort the command (Stop driving CMD line) and set this bit
+ * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
+ * conflict.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - CRC Error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CCE field. */
+#define SDHC_RD_IRQSTAT_CCE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CCE_MASK) >> SDHC_IRQSTAT_CCE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CCE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CCE_SHIFT))
+
+/*! @brief Set the CCE field to a new value. */
+#define SDHC_WR_IRQSTAT_CCE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CCE(value)))
+#define SDHC_BWR_IRQSTAT_CCE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
+ *
+ * Occurs when detecting that the end bit of a command response is 0.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - End Bit Error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CEBE field. */
+#define SDHC_RD_IRQSTAT_CEBE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CEBE_MASK) >> SDHC_IRQSTAT_CEBE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CEBE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CEBE_SHIFT))
+
+/*! @brief Set the CEBE field to a new value. */
+#define SDHC_WR_IRQSTAT_CEBE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CEBE(value)))
+#define SDHC_BWR_IRQSTAT_CEBE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
+ *
+ * Occurs if a Command Index error occurs in the command response.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CIE field. */
+#define SDHC_RD_IRQSTAT_CIE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CIE_MASK) >> SDHC_IRQSTAT_CIE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CIE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CIE_SHIFT))
+
+/*! @brief Set the CIE field to a new value. */
+#define SDHC_WR_IRQSTAT_CIE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CIE(value)))
+#define SDHC_BWR_IRQSTAT_CIE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
+ *
+ * Occurs when detecting one of following time-out conditions. Busy time-out for
+ * R1b,R5b type Busy time-out after Write CRC status Read Data time-out
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DTOE field. */
+#define SDHC_RD_IRQSTAT_DTOE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DTOE_MASK) >> SDHC_IRQSTAT_DTOE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DTOE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DTOE_SHIFT))
+
+/*! @brief Set the DTOE field to a new value. */
+#define SDHC_WR_IRQSTAT_DTOE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DTOE(value)))
+#define SDHC_BWR_IRQSTAT_DTOE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
+ *
+ * Occurs when detecting a CRC error when transferring read data, which uses the
+ * DAT line, or when detecting the Write CRC status having a value other than
+ * 010.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DCE field. */
+#define SDHC_RD_IRQSTAT_DCE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DCE_MASK) >> SDHC_IRQSTAT_DCE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DCE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DCE_SHIFT))
+
+/*! @brief Set the DCE field to a new value. */
+#define SDHC_WR_IRQSTAT_DCE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DCE(value)))
+#define SDHC_BWR_IRQSTAT_DCE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
+ *
+ * Occurs either when detecting 0 at the end bit position of read data, which
+ * uses the DAT line, or at the end bit position of the CRC.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DEBE field. */
+#define SDHC_RD_IRQSTAT_DEBE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DEBE_MASK) >> SDHC_IRQSTAT_DEBE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DEBE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DEBE_SHIFT))
+
+/*! @brief Set the DEBE field to a new value. */
+#define SDHC_WR_IRQSTAT_DEBE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DEBE(value)))
+#define SDHC_BWR_IRQSTAT_DEBE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
+ *
+ * Occurs when detecting that one of the bits in the Auto CMD12 Error Status
+ * register has changed from 0 to 1. This bit is set to 1, not only when the errors
+ * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
+ * previous command error.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_AC12E field. */
+#define SDHC_RD_IRQSTAT_AC12E(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_AC12E_MASK) >> SDHC_IRQSTAT_AC12E_SHIFT)
+#define SDHC_BRD_IRQSTAT_AC12E(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_AC12E_SHIFT))
+
+/*! @brief Set the AC12E field to a new value. */
+#define SDHC_WR_IRQSTAT_AC12E(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_AC12E(value)))
+#define SDHC_BWR_IRQSTAT_AC12E(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_AC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
+ *
+ * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
+ * some error occurs in the data transfer. This error can be caused by either
+ * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
+ * Address register is the next fetch address where the error occurs. Because any
+ * error corrupts the whole data block, the host driver shall restart the transfer
+ * from the corrupted block boundary. The address of the block boundary can be
+ * calculated either from the current DSADDR value or from the remaining number of
+ * blocks and the block size.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DMAE field. */
+#define SDHC_RD_IRQSTAT_DMAE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DMAE_MASK) >> SDHC_IRQSTAT_DMAE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DMAE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DMAE_SHIFT))
+
+/*! @brief Set the DMAE field to a new value. */
+#define SDHC_WR_IRQSTAT_DMAE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DMAE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK), SDHC_IRQSTAT_DMAE(value)))
+#define SDHC_BWR_IRQSTAT_DMAE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DMAE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSTATEN - Interrupt Status Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
+ *
+ * Reset value: 0x117F013FU
+ *
+ * Setting the bits in this register to 1 enables the corresponding interrupt
+ * status to be set by the specified event. If any bit is cleared, the
+ * corresponding interrupt status bit is also cleared, that is, when the bit in this register
+ * is cleared, the corresponding bit in interrupt status register is always 0.
+ * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
+ * card interrupt signal during the interrupt period and hold its value in the
+ * flip-flop. There will be some delays on the card interrupt, asserted from the card,
+ * to the time the host system is informed. To detect a CMD line conflict, the
+ * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTATEN register
+ */
+/*@{*/
+#define SDHC_RD_IRQSTATEN(base)  (SDHC_IRQSTATEN_REG(base))
+#define SDHC_WR_IRQSTATEN(base, value) (SDHC_IRQSTATEN_REG(base) = (value))
+#define SDHC_RMW_IRQSTATEN(base, mask, value) (SDHC_WR_IRQSTATEN(base, (SDHC_RD_IRQSTATEN(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) |  (value)))
+#define SDHC_CLR_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) & ~(value)))
+#define SDHC_TOG_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSTATEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field. */
+#define SDHC_RD_IRQSTATEN_CCSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CCSEN_MASK) >> SDHC_IRQSTATEN_CCSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CCSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCSEN_SHIFT))
+
+/*! @brief Set the CCSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CCSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CCSEN_MASK, SDHC_IRQSTATEN_CCSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CCSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field. */
+#define SDHC_RD_IRQSTATEN_TCSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_TCSEN_MASK) >> SDHC_IRQSTATEN_TCSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_TCSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_TCSEN_SHIFT))
+
+/*! @brief Set the TCSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_TCSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_TCSEN_MASK, SDHC_IRQSTATEN_TCSEN(value)))
+#define SDHC_BWR_IRQSTATEN_TCSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_TCSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field. */
+#define SDHC_RD_IRQSTATEN_BGESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BGESEN_MASK) >> SDHC_IRQSTATEN_BGESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BGESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BGESEN_SHIFT))
+
+/*! @brief Set the BGESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BGESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BGESEN_MASK, SDHC_IRQSTATEN_BGESEN(value)))
+#define SDHC_BWR_IRQSTATEN_BGESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BGESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field. */
+#define SDHC_RD_IRQSTATEN_DINTSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DINTSEN_MASK) >> SDHC_IRQSTATEN_DINTSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DINTSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DINTSEN_SHIFT))
+
+/*! @brief Set the DINTSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DINTSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DINTSEN_MASK, SDHC_IRQSTATEN_DINTSEN(value)))
+#define SDHC_BWR_IRQSTATEN_DINTSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DINTSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field. */
+#define SDHC_RD_IRQSTATEN_BWRSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BWRSEN_MASK) >> SDHC_IRQSTATEN_BWRSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BWRSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BWRSEN_SHIFT))
+
+/*! @brief Set the BWRSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BWRSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BWRSEN_MASK, SDHC_IRQSTATEN_BWRSEN(value)))
+#define SDHC_BWR_IRQSTATEN_BWRSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BWRSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field. */
+#define SDHC_RD_IRQSTATEN_BRRSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BRRSEN_MASK) >> SDHC_IRQSTATEN_BRRSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BRRSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BRRSEN_SHIFT))
+
+/*! @brief Set the BRRSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BRRSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BRRSEN_MASK, SDHC_IRQSTATEN_BRRSEN(value)))
+#define SDHC_BWR_IRQSTATEN_BRRSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BRRSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field. */
+#define SDHC_RD_IRQSTATEN_CINSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CINSEN_MASK) >> SDHC_IRQSTATEN_CINSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CINSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINSEN_SHIFT))
+
+/*! @brief Set the CINSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CINSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CINSEN_MASK, SDHC_IRQSTATEN_CINSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CINSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field. */
+#define SDHC_RD_IRQSTATEN_CRMSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CRMSEN_MASK) >> SDHC_IRQSTATEN_CRMSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CRMSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CRMSEN_SHIFT))
+
+/*! @brief Set the CRMSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CRMSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CRMSEN_MASK, SDHC_IRQSTATEN_CRMSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CRMSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CRMSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
+ *
+ * If this bit is set to 0, the SDHC will clear the interrupt request to the
+ * system. The card interrupt detection is stopped when this bit is cleared and
+ * restarted when this bit is set to 1. The host driver must clear the this bit
+ * before servicing the card interrupt and must set this bit again after all interrupt
+ * requests from the card are cleared to prevent inadvertent interrupts.
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field. */
+#define SDHC_RD_IRQSTATEN_CINTSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CINTSEN_MASK) >> SDHC_IRQSTATEN_CINTSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CINTSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINTSEN_SHIFT))
+
+/*! @brief Set the CINTSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CINTSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CINTSEN_MASK, SDHC_IRQSTATEN_CINTSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CINTSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINTSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field. */
+#define SDHC_RD_IRQSTATEN_CTOESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CTOESEN_MASK) >> SDHC_IRQSTATEN_CTOESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CTOESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CTOESEN_SHIFT))
+
+/*! @brief Set the CTOESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CTOESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CTOESEN_MASK, SDHC_IRQSTATEN_CTOESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CTOESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CTOESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field. */
+#define SDHC_RD_IRQSTATEN_CCESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CCESEN_MASK) >> SDHC_IRQSTATEN_CCESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CCESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCESEN_SHIFT))
+
+/*! @brief Set the CCESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CCESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CCESEN_MASK, SDHC_IRQSTATEN_CCESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CCESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field. */
+#define SDHC_RD_IRQSTATEN_CEBESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CEBESEN_MASK) >> SDHC_IRQSTATEN_CEBESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CEBESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CEBESEN_SHIFT))
+
+/*! @brief Set the CEBESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CEBESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CEBESEN_MASK, SDHC_IRQSTATEN_CEBESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CEBESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CEBESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field. */
+#define SDHC_RD_IRQSTATEN_CIESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CIESEN_MASK) >> SDHC_IRQSTATEN_CIESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CIESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CIESEN_SHIFT))
+
+/*! @brief Set the CIESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CIESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CIESEN_MASK, SDHC_IRQSTATEN_CIESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CIESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CIESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field. */
+#define SDHC_RD_IRQSTATEN_DTOESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DTOESEN_MASK) >> SDHC_IRQSTATEN_DTOESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DTOESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DTOESEN_SHIFT))
+
+/*! @brief Set the DTOESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DTOESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DTOESEN_MASK, SDHC_IRQSTATEN_DTOESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DTOESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DTOESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field. */
+#define SDHC_RD_IRQSTATEN_DCESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DCESEN_MASK) >> SDHC_IRQSTATEN_DCESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DCESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DCESEN_SHIFT))
+
+/*! @brief Set the DCESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DCESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DCESEN_MASK, SDHC_IRQSTATEN_DCESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DCESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DCESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field. */
+#define SDHC_RD_IRQSTATEN_DEBESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DEBESEN_MASK) >> SDHC_IRQSTATEN_DEBESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DEBESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DEBESEN_SHIFT))
+
+/*! @brief Set the DEBESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DEBESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DEBESEN_MASK, SDHC_IRQSTATEN_DEBESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DEBESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DEBESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field. */
+#define SDHC_RD_IRQSTATEN_AC12ESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_AC12ESEN_MASK) >> SDHC_IRQSTATEN_AC12ESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_AC12ESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_AC12ESEN_SHIFT))
+
+/*! @brief Set the AC12ESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_AC12ESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_AC12ESEN_MASK, SDHC_IRQSTATEN_AC12ESEN(value)))
+#define SDHC_BWR_IRQSTATEN_AC12ESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_AC12ESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field. */
+#define SDHC_RD_IRQSTATEN_DMAESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DMAESEN_MASK) >> SDHC_IRQSTATEN_DMAESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DMAESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DMAESEN_SHIFT))
+
+/*! @brief Set the DMAESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DMAESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DMAESEN_MASK, SDHC_IRQSTATEN_DMAESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DMAESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DMAESEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSIGEN - Interrupt Signal Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to select which interrupt status is indicated to the
+ * host system as the interrupt. All of these status bits share the same interrupt
+ * line. Setting any of these bits to 1 enables interrupt generation. The
+ * corresponding status register bit will generate an interrupt when the corresponding
+ * interrupt signal enable bit is set.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSIGEN register
+ */
+/*@{*/
+#define SDHC_RD_IRQSIGEN(base)   (SDHC_IRQSIGEN_REG(base))
+#define SDHC_WR_IRQSIGEN(base, value) (SDHC_IRQSIGEN_REG(base) = (value))
+#define SDHC_RMW_IRQSIGEN(base, mask, value) (SDHC_WR_IRQSIGEN(base, (SDHC_RD_IRQSIGEN(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) |  (value)))
+#define SDHC_CLR_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) & ~(value)))
+#define SDHC_TOG_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSIGEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field. */
+#define SDHC_RD_IRQSIGEN_CCIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CCIEN_MASK) >> SDHC_IRQSIGEN_CCIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CCIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCIEN_SHIFT))
+
+/*! @brief Set the CCIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CCIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CCIEN_MASK, SDHC_IRQSIGEN_CCIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CCIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field. */
+#define SDHC_RD_IRQSIGEN_TCIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_TCIEN_MASK) >> SDHC_IRQSIGEN_TCIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_TCIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_TCIEN_SHIFT))
+
+/*! @brief Set the TCIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_TCIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_TCIEN_MASK, SDHC_IRQSIGEN_TCIEN(value)))
+#define SDHC_BWR_IRQSIGEN_TCIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_TCIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field. */
+#define SDHC_RD_IRQSIGEN_BGEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BGEIEN_MASK) >> SDHC_IRQSIGEN_BGEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BGEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BGEIEN_SHIFT))
+
+/*! @brief Set the BGEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BGEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BGEIEN_MASK, SDHC_IRQSIGEN_BGEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BGEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BGEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field. */
+#define SDHC_RD_IRQSIGEN_DINTIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DINTIEN_MASK) >> SDHC_IRQSIGEN_DINTIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DINTIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DINTIEN_SHIFT))
+
+/*! @brief Set the DINTIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DINTIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DINTIEN_MASK, SDHC_IRQSIGEN_DINTIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DINTIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DINTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field. */
+#define SDHC_RD_IRQSIGEN_BWRIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BWRIEN_MASK) >> SDHC_IRQSIGEN_BWRIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BWRIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BWRIEN_SHIFT))
+
+/*! @brief Set the BWRIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BWRIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BWRIEN_MASK, SDHC_IRQSIGEN_BWRIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BWRIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BWRIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field. */
+#define SDHC_RD_IRQSIGEN_BRRIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BRRIEN_MASK) >> SDHC_IRQSIGEN_BRRIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BRRIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BRRIEN_SHIFT))
+
+/*! @brief Set the BRRIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BRRIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BRRIEN_MASK, SDHC_IRQSIGEN_BRRIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BRRIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BRRIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field. */
+#define SDHC_RD_IRQSIGEN_CINSIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CINSIEN_MASK) >> SDHC_IRQSIGEN_CINSIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CINSIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINSIEN_SHIFT))
+
+/*! @brief Set the CINSIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CINSIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CINSIEN_MASK, SDHC_IRQSIGEN_CINSIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CINSIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINSIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field. */
+#define SDHC_RD_IRQSIGEN_CRMIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CRMIEN_MASK) >> SDHC_IRQSIGEN_CRMIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CRMIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CRMIEN_SHIFT))
+
+/*! @brief Set the CRMIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CRMIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CRMIEN_MASK, SDHC_IRQSIGEN_CRMIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CRMIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CRMIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field. */
+#define SDHC_RD_IRQSIGEN_CINTIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CINTIEN_MASK) >> SDHC_IRQSIGEN_CINTIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CINTIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINTIEN_SHIFT))
+
+/*! @brief Set the CINTIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CINTIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CINTIEN_MASK, SDHC_IRQSIGEN_CINTIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CINTIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field. */
+#define SDHC_RD_IRQSIGEN_CTOEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CTOEIEN_MASK) >> SDHC_IRQSIGEN_CTOEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CTOEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CTOEIEN_SHIFT))
+
+/*! @brief Set the CTOEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CTOEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CTOEIEN_MASK, SDHC_IRQSIGEN_CTOEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CTOEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CTOEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field. */
+#define SDHC_RD_IRQSIGEN_CCEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CCEIEN_MASK) >> SDHC_IRQSIGEN_CCEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CCEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCEIEN_SHIFT))
+
+/*! @brief Set the CCEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CCEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CCEIEN_MASK, SDHC_IRQSIGEN_CCEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CCEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field. */
+#define SDHC_RD_IRQSIGEN_CEBEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CEBEIEN_MASK) >> SDHC_IRQSIGEN_CEBEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CEBEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CEBEIEN_SHIFT))
+
+/*! @brief Set the CEBEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CEBEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CEBEIEN_MASK, SDHC_IRQSIGEN_CEBEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CEBEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CEBEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field. */
+#define SDHC_RD_IRQSIGEN_CIEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CIEIEN_MASK) >> SDHC_IRQSIGEN_CIEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CIEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CIEIEN_SHIFT))
+
+/*! @brief Set the CIEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CIEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CIEIEN_MASK, SDHC_IRQSIGEN_CIEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CIEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CIEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field. */
+#define SDHC_RD_IRQSIGEN_DTOEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DTOEIEN_MASK) >> SDHC_IRQSIGEN_DTOEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DTOEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DTOEIEN_SHIFT))
+
+/*! @brief Set the DTOEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DTOEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DTOEIEN_MASK, SDHC_IRQSIGEN_DTOEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DTOEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DTOEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field. */
+#define SDHC_RD_IRQSIGEN_DCEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DCEIEN_MASK) >> SDHC_IRQSIGEN_DCEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DCEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DCEIEN_SHIFT))
+
+/*! @brief Set the DCEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DCEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DCEIEN_MASK, SDHC_IRQSIGEN_DCEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DCEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DCEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field. */
+#define SDHC_RD_IRQSIGEN_DEBEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DEBEIEN_MASK) >> SDHC_IRQSIGEN_DEBEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DEBEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DEBEIEN_SHIFT))
+
+/*! @brief Set the DEBEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DEBEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DEBEIEN_MASK, SDHC_IRQSIGEN_DEBEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DEBEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DEBEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field. */
+#define SDHC_RD_IRQSIGEN_AC12EIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_AC12EIEN_MASK) >> SDHC_IRQSIGEN_AC12EIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_AC12EIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_AC12EIEN_SHIFT))
+
+/*! @brief Set the AC12EIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_AC12EIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_AC12EIEN_MASK, SDHC_IRQSIGEN_AC12EIEN(value)))
+#define SDHC_BWR_IRQSIGEN_AC12EIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_AC12EIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field. */
+#define SDHC_RD_IRQSIGEN_DMAEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DMAEIEN_MASK) >> SDHC_IRQSIGEN_DMAEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DMAEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DMAEIEN_SHIFT))
+
+/*! @brief Set the DMAEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DMAEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DMAEIEN_MASK, SDHC_IRQSIGEN_DMAEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DMAEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DMAEIEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_AC12ERR - Auto CMD12 Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the AC12ESEN bit in the Status register is set, the host driver shall
+ * check this register to identify what kind of error the Auto CMD12 indicated.
+ * This register is valid only when the Auto CMD12 Error status bit is set. The
+ * following table shows the relationship between the Auto CMGD12 CRC error and the
+ * Auto CMD12 command timeout error. Relationship between Command CRC Error and
+ * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
+ * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
+ * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
+ * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
+ * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
+ * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
+ * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
+ * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
+ * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
+ * command that can't be issued. Clear bit 7 if there is no command to issue. The
+ * timing for generating the auto CMD12 error and writing to the command register
+ * are asynchronous. After that, bit 7 shall be sampled when the driver is not
+ * writing to the command register. So it is suggested to read this register only
+ * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
+ * of the error bits (0-4) is set to 1. The command not issued by auto CMD12
+ * error does not generate an interrupt.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_AC12ERR register
+ */
+/*@{*/
+#define SDHC_RD_AC12ERR(base)    (SDHC_AC12ERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_AC12ERR bitfields
+ */
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
+ *
+ * If memory multiple block data transfer is not started, due to a command
+ * error, this bit is not set because it is not necessary to issue an auto CMD12.
+ * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
+ * multiple block data transfer due to some error. If this bit is set to 1, other
+ * error status bits (1-4) have no meaning.
+ *
+ * Values:
+ * - 0b0 - Executed.
+ * - 0b1 - Not executed.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12NE field. */
+#define SDHC_RD_AC12ERR_AC12NE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12NE_MASK) >> SDHC_AC12ERR_AC12NE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12NE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12NE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
+ *
+ * Occurs if no response is returned within 64 SDCLK cycles from the end bit of
+ * the command. If this bit is set to 1, the other error status bits (2-4) have
+ * no meaning.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12TOE field. */
+#define SDHC_RD_AC12ERR_AC12TOE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12TOE_MASK) >> SDHC_AC12ERR_AC12TOE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12TOE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12TOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
+ *
+ * Occurs when detecting that the end bit of command response is 0 which must be
+ * 1.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - End bit error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12EBE field. */
+#define SDHC_RD_AC12ERR_AC12EBE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12EBE_MASK) >> SDHC_AC12ERR_AC12EBE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12EBE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12EBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
+ *
+ * Occurs when detecting a CRC error in the command response.
+ *
+ * Values:
+ * - 0b0 - No CRC error.
+ * - 0b1 - CRC error met in Auto CMD12 response.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12CE field. */
+#define SDHC_RD_AC12ERR_AC12CE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12CE_MASK) >> SDHC_AC12ERR_AC12CE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12CE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12CE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
+ *
+ * Occurs if the command index error occurs in response to a command.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error, the CMD index in response is not CMD12.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12IE field. */
+#define SDHC_RD_AC12ERR_AC12IE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12IE_MASK) >> SDHC_AC12ERR_AC12IE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12IE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12IE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
+ *
+ * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
+ * error (D04-D01) in this register.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Not issued.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field. */
+#define SDHC_RD_AC12ERR_CNIBAC12E(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_CNIBAC12E_MASK) >> SDHC_AC12ERR_CNIBAC12E_SHIFT)
+#define SDHC_BRD_AC12ERR_CNIBAC12E(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_CNIBAC12E_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_HTCAPBLT - Host Controller Capabilities
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_HTCAPBLT - Host Controller Capabilities (RO)
+ *
+ * Reset value: 0x07F30000U
+ *
+ * This register provides the host driver with information specific to the SDHC
+ * implementation. The value in this register is the power-on-reset value, and
+ * does not change with a software reset. Any write to this register is ignored.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_HTCAPBLT register
+ */
+/*@{*/
+#define SDHC_RD_HTCAPBLT(base)   (SDHC_HTCAPBLT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_HTCAPBLT bitfields
+ */
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
+ *
+ * This value indicates the maximum block size that the host driver can read and
+ * write to the buffer in the SDHC. The buffer shall transfer block size without
+ * wait cycles.
+ *
+ * Values:
+ * - 0b000 - 512 bytes
+ * - 0b001 - 1024 bytes
+ * - 0b010 - 2048 bytes
+ * - 0b011 - 4096 bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_MBL field. */
+#define SDHC_RD_HTCAPBLT_MBL(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_MBL_MASK) >> SDHC_HTCAPBLT_MBL_SHIFT)
+#define SDHC_BRD_HTCAPBLT_MBL(base) (SDHC_RD_HTCAPBLT_MBL(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
+ *
+ * This bit indicates whether the SDHC supports the ADMA feature.
+ *
+ * Values:
+ * - 0b0 - Advanced DMA not supported.
+ * - 0b1 - Advanced DMA supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field. */
+#define SDHC_RD_HTCAPBLT_ADMAS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_ADMAS_MASK) >> SDHC_HTCAPBLT_ADMAS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_ADMAS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_ADMAS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
+ *
+ * This bit indicates whether the SDHC supports high speed mode and the host
+ * system can supply a SD Clock frequency from 25 MHz to 50 MHz.
+ *
+ * Values:
+ * - 0b0 - High speed not supported.
+ * - 0b1 - High speed supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_HSS field. */
+#define SDHC_RD_HTCAPBLT_HSS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_HSS_MASK) >> SDHC_HTCAPBLT_HSS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_HSS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_HSS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
+ *
+ * This bit indicates whether the SDHC is capable of using the internal DMA to
+ * transfer data between system memory and the data buffer directly.
+ *
+ * Values:
+ * - 0b0 - DMA not supported.
+ * - 0b1 - DMA supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_DMAS field. */
+#define SDHC_RD_HTCAPBLT_DMAS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_DMAS_MASK) >> SDHC_HTCAPBLT_DMAS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_DMAS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_DMAS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
+ *
+ * This bit indicates whether the SDHC supports suspend / resume functionality.
+ * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
+ * are not supported, and the host driver shall not issue either suspend or
+ * resume commands.
+ *
+ * Values:
+ * - 0b0 - Not supported.
+ * - 0b1 - Supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_SRS field. */
+#define SDHC_RD_HTCAPBLT_SRS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_SRS_MASK) >> SDHC_HTCAPBLT_SRS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_SRS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_SRS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
+ *
+ * This bit shall depend on the host system ability.
+ *
+ * Values:
+ * - 0b0 - 3.3 V not supported.
+ * - 0b1 - 3.3 V supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_VS33 field. */
+#define SDHC_RD_HTCAPBLT_VS33(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_VS33_MASK) >> SDHC_HTCAPBLT_VS33_SHIFT)
+#define SDHC_BRD_HTCAPBLT_VS33(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_VS33_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_WML - Watermark Level Register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_WML - Watermark Level Register (RW)
+ *
+ * Reset value: 0x00100010U
+ *
+ * Both write and read watermark levels (FIFO threshold) are configurable. There
+ * value can range from 1 to 128 words. Both write and read burst lengths are
+ * also configurable. There value can range from 1 to 31 words.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_WML register
+ */
+/*@{*/
+#define SDHC_RD_WML(base)        (SDHC_WML_REG(base))
+#define SDHC_WR_WML(base, value) (SDHC_WML_REG(base) = (value))
+#define SDHC_RMW_WML(base, mask, value) (SDHC_WR_WML(base, (SDHC_RD_WML(base) & ~(mask)) | (value)))
+#define SDHC_SET_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) |  (value)))
+#define SDHC_CLR_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) & ~(value)))
+#define SDHC_TOG_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_WML bitfields
+ */
+
+/*!
+ * @name Register SDHC_WML, field RDWML[7:0] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * read operation. Also the number of words as a sequence of read bursts in
+ * back-to-back mode. The maximum legal value for the read water mark level is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_WML_RDWML field. */
+#define SDHC_RD_WML_RDWML(base) ((SDHC_WML_REG(base) & SDHC_WML_RDWML_MASK) >> SDHC_WML_RDWML_SHIFT)
+#define SDHC_BRD_WML_RDWML(base) (SDHC_RD_WML_RDWML(base))
+
+/*! @brief Set the RDWML field to a new value. */
+#define SDHC_WR_WML_RDWML(base, value) (SDHC_RMW_WML(base, SDHC_WML_RDWML_MASK, SDHC_WML_RDWML(value)))
+#define SDHC_BWR_WML_RDWML(base, value) (SDHC_WR_WML_RDWML(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_WML, field WRWML[23:16] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * write operation. Also the number of words as a sequence of write bursts in
+ * back-to-back mode. The maximum legal value for the write watermark level is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_WML_WRWML field. */
+#define SDHC_RD_WML_WRWML(base) ((SDHC_WML_REG(base) & SDHC_WML_WRWML_MASK) >> SDHC_WML_WRWML_SHIFT)
+#define SDHC_BRD_WML_WRWML(base) (SDHC_RD_WML_WRWML(base))
+
+/*! @brief Set the WRWML field to a new value. */
+#define SDHC_WR_WML_WRWML(base, value) (SDHC_RMW_WML(base, SDHC_WML_WRWML_MASK, SDHC_WML_WRWML(value)))
+#define SDHC_BWR_WML_WRWML(base, value) (SDHC_WR_WML_WRWML(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_FEVT - Force Event register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_FEVT - Force Event register (WO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Force Event (FEVT) register is not a physically implemented register.
+ * Rather, it is an address at which the Interrupt Status register can be written if
+ * the corresponding bit of the Interrupt Status Enable register is set. This
+ * register is a write only register and writing 0 to it has no effect. Writing 1
+ * to this register actually sets the corresponding bit of Interrupt Status
+ * register. A read from this register always results in 0's. To change the
+ * corresponding status bits in the interrupt status register, make sure to set
+ * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
+ * short pulse on the DAT[1] line, and the driver may treat this interrupt as a
+ * normal interrupt. The interrupt service routine may skip polling the card
+ * interrupt factor as the interrupt is selfcleared.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_FEVT register
+ */
+/*@{*/
+#define SDHC_RD_FEVT(base)       (SDHC_FEVT_REG(base))
+#define SDHC_WR_FEVT(base, value) (SDHC_FEVT_REG(base) = (value))
+#define SDHC_RMW_FEVT(base, mask, value) (SDHC_WR_FEVT(base, (SDHC_RD_FEVT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_FEVT bitfields
+ */
+
+/*!
+ * @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
+ *
+ * Forces AC12ERR[AC12NE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12NE field to a new value. */
+#define SDHC_WR_FEVT_AC12NE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12NE_MASK, SDHC_FEVT_AC12NE(value)))
+#define SDHC_BWR_FEVT_AC12NE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12NE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
+ *
+ * Forces AC12ERR[AC12TOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12TOE field to a new value. */
+#define SDHC_WR_FEVT_AC12TOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12TOE_MASK, SDHC_FEVT_AC12TOE(value)))
+#define SDHC_BWR_FEVT_AC12TOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12TOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
+ *
+ * Forces AC12ERR[AC12CE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12CE field to a new value. */
+#define SDHC_WR_FEVT_AC12CE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12CE_MASK, SDHC_FEVT_AC12CE(value)))
+#define SDHC_BWR_FEVT_AC12CE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12CE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
+ *
+ * Forces AC12ERR[AC12EBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12EBE field to a new value. */
+#define SDHC_WR_FEVT_AC12EBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12EBE_MASK, SDHC_FEVT_AC12EBE(value)))
+#define SDHC_BWR_FEVT_AC12EBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12EBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
+ *
+ * Forces AC12ERR[AC12IE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12IE field to a new value. */
+#define SDHC_WR_FEVT_AC12IE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12IE_MASK, SDHC_FEVT_AC12IE(value)))
+#define SDHC_BWR_FEVT_AC12IE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
+ *
+ * Forces AC12ERR[CNIBAC12E] to be set.
+ */
+/*@{*/
+/*! @brief Set the CNIBAC12E field to a new value. */
+#define SDHC_WR_FEVT_CNIBAC12E(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CNIBAC12E_MASK, SDHC_FEVT_CNIBAC12E(value)))
+#define SDHC_BWR_FEVT_CNIBAC12E(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CNIBAC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CTOE[16] (WORZ)
+ *
+ * Forces IRQSTAT[CTOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CTOE field to a new value. */
+#define SDHC_WR_FEVT_CTOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CTOE_MASK, SDHC_FEVT_CTOE(value)))
+#define SDHC_BWR_FEVT_CTOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CCE[17] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CCE field to a new value. */
+#define SDHC_WR_FEVT_CCE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CCE_MASK, SDHC_FEVT_CCE(value)))
+#define SDHC_BWR_FEVT_CCE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CEBE[18] (WORZ)
+ *
+ * Forces IRQSTAT[CEBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CEBE field to a new value. */
+#define SDHC_WR_FEVT_CEBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CEBE_MASK, SDHC_FEVT_CEBE(value)))
+#define SDHC_BWR_FEVT_CEBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CIE[19] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CIE field to a new value. */
+#define SDHC_WR_FEVT_CIE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CIE_MASK, SDHC_FEVT_CIE(value)))
+#define SDHC_BWR_FEVT_CIE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DTOE[20] (WORZ)
+ *
+ * Forces IRQSTAT[DTOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DTOE field to a new value. */
+#define SDHC_WR_FEVT_DTOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DTOE_MASK, SDHC_FEVT_DTOE(value)))
+#define SDHC_BWR_FEVT_DTOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DCE[21] (WORZ)
+ *
+ * Forces IRQSTAT[DCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DCE field to a new value. */
+#define SDHC_WR_FEVT_DCE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DCE_MASK, SDHC_FEVT_DCE(value)))
+#define SDHC_BWR_FEVT_DCE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DEBE[22] (WORZ)
+ *
+ * Forces IRQSTAT[DEBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DEBE field to a new value. */
+#define SDHC_WR_FEVT_DEBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DEBE_MASK, SDHC_FEVT_DEBE(value)))
+#define SDHC_BWR_FEVT_DEBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12E[24] (WORZ)
+ *
+ * Forces IRQSTAT[AC12E] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12E field to a new value. */
+#define SDHC_WR_FEVT_AC12E(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12E_MASK, SDHC_FEVT_AC12E(value)))
+#define SDHC_BWR_FEVT_AC12E(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DMAE[28] (WORZ)
+ *
+ * Forces the DMAE bit of Interrupt Status Register to be set.
+ */
+/*@{*/
+/*! @brief Set the DMAE field to a new value. */
+#define SDHC_WR_FEVT_DMAE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DMAE_MASK, SDHC_FEVT_DMAE(value)))
+#define SDHC_BWR_FEVT_DMAE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DMAE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CINT[31] (WORZ)
+ *
+ * Writing 1 to this bit generates a short low-level pulse on the internal
+ * DAT[1] line, as if a self-clearing interrupt was received from the external card.
+ * If enabled, the CINT bit will be set and the interrupt service routine may
+ * treat this interrupt as a normal interrupt from the external card.
+ */
+/*@{*/
+/*! @brief Set the CINT field to a new value. */
+#define SDHC_WR_FEVT_CINT(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CINT_MASK, SDHC_FEVT_CINT(value)))
+#define SDHC_BWR_FEVT_CINT(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CINT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_ADMAES - ADMA Error Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_ADMAES - ADMA Error Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an ADMA error interrupt has occurred, the ADMA Error States field in
+ * this register holds the ADMA state and the ADMA System Address register holds the
+ * address around the error descriptor. For recovering from this error, the host
+ * driver requires the ADMA state to identify the error descriptor address as
+ * follows: ST_STOP: Previous location set in the ADMA System Address register is
+ * the error descriptor address. ST_FDS: Current location set in the ADMA System
+ * Address register is the error descriptor address. ST_CADR: This state is never
+ * set because it only increments the descriptor pointer and doesn't generate an
+ * ADMA error. ST_TFR: Previous location set in the ADMA System Address register
+ * is the error descriptor address. In case of a write operation, the host driver
+ * must use the ACMD22 to get the number of the written block, rather than using
+ * this information, because unwritten data may exist in the host controller.
+ * The host controller generates the ADMA error interrupt when it detects invalid
+ * descriptor data (valid = 0) in the ST_FDS state. The host driver can
+ * distinguish this error by reading the valid bit of the error descriptor. ADMA Error
+ * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
+ * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
+ * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
+ * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
+ * (Transfer Data) Holds the address of the next executable descriptor command
+ */
+/*!
+ * @name Constants and macros for entire SDHC_ADMAES register
+ */
+/*@{*/
+#define SDHC_RD_ADMAES(base)     (SDHC_ADMAES_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_ADMAES bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
+ *
+ * Indicates the state of the ADMA when an error has occurred during an ADMA
+ * data transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMAES field. */
+#define SDHC_RD_ADMAES_ADMAES(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMAES_MASK) >> SDHC_ADMAES_ADMAES_SHIFT)
+#define SDHC_BRD_ADMAES_ADMAES(base) (SDHC_RD_ADMAES_ADMAES(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMALME[2] (RO)
+ *
+ * This error occurs in the following 2 cases: While the block count enable is
+ * being set, the total data length specified by the descriptor table is different
+ * from that specified by the block count and block length. Total data length
+ * can not be divided by the block length.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMALME field. */
+#define SDHC_RD_ADMAES_ADMALME(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMALME_MASK) >> SDHC_ADMAES_ADMALME_SHIFT)
+#define SDHC_BRD_ADMAES_ADMALME(base) (BITBAND_ACCESS32(&SDHC_ADMAES_REG(base), SDHC_ADMAES_ADMALME_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
+ *
+ * This error occurs when an invalid descriptor is fetched by ADMA.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMADCE field. */
+#define SDHC_RD_ADMAES_ADMADCE(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMADCE_MASK) >> SDHC_ADMAES_ADMADCE_SHIFT)
+#define SDHC_BRD_ADMAES_ADMADCE(base) (BITBAND_ACCESS32(&SDHC_ADMAES_REG(base), SDHC_ADMAES_ADMADCE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_ADSADDR - ADMA System Addressregister
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_ADSADDR - ADMA System Addressregister (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for ADMA
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_ADSADDR register
+ */
+/*@{*/
+#define SDHC_RD_ADSADDR(base)    (SDHC_ADSADDR_REG(base))
+#define SDHC_WR_ADSADDR(base, value) (SDHC_ADSADDR_REG(base) = (value))
+#define SDHC_RMW_ADSADDR(base, mask, value) (SDHC_WR_ADSADDR(base, (SDHC_RD_ADSADDR(base) & ~(mask)) | (value)))
+#define SDHC_SET_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) |  (value)))
+#define SDHC_CLR_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) & ~(value)))
+#define SDHC_TOG_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_ADSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
+ *
+ * Holds the word address of the executing command in the descriptor table. At
+ * the start of ADMA, the host driver shall set the start address of the
+ * Descriptor table. The ADMA engine increments this register address whenever fetching a
+ * descriptor command. When the ADMA is stopped at the block gap, this register
+ * indicates the address of the next executable descriptor command. When the ADMA
+ * error interrupt is generated, this register shall hold the valid descriptor
+ * address depending on the ADMA state. The lower 2 bits of this register is tied
+ * to '0' so the ADMA address is always word-aligned. Because this register
+ * supports dynamic address reflecting, when TC bit is set, it automatically alters the
+ * value of internal address counter, so SW cannot change this register when TC
+ * bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADSADDR_ADSADDR field. */
+#define SDHC_RD_ADSADDR_ADSADDR(base) ((SDHC_ADSADDR_REG(base) & SDHC_ADSADDR_ADSADDR_MASK) >> SDHC_ADSADDR_ADSADDR_SHIFT)
+#define SDHC_BRD_ADSADDR_ADSADDR(base) (SDHC_RD_ADSADDR_ADSADDR(base))
+
+/*! @brief Set the ADSADDR field to a new value. */
+#define SDHC_WR_ADSADDR_ADSADDR(base, value) (SDHC_RMW_ADSADDR(base, SDHC_ADSADDR_ADSADDR_MASK, SDHC_ADSADDR_ADSADDR(value)))
+#define SDHC_BWR_ADSADDR_ADSADDR(base, value) (SDHC_WR_ADSADDR_ADSADDR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_VENDOR - Vendor Specific register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_VENDOR - Vendor Specific register (RW)
+ *
+ * Reset value: 0x00000001U
+ *
+ * This register contains the vendor-specific control/status register.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_VENDOR register
+ */
+/*@{*/
+#define SDHC_RD_VENDOR(base)     (SDHC_VENDOR_REG(base))
+#define SDHC_WR_VENDOR(base, value) (SDHC_VENDOR_REG(base) = (value))
+#define SDHC_RMW_VENDOR(base, mask, value) (SDHC_WR_VENDOR(base, (SDHC_RD_VENDOR(base) & ~(mask)) | (value)))
+#define SDHC_SET_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) |  (value)))
+#define SDHC_CLR_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) & ~(value)))
+#define SDHC_TOG_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_VENDOR bitfields
+ */
+
+/*!
+ * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
+ *
+ * Enables the request to external DMA. When the internal DMA (either simple DMA
+ * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
+ * request when the internal buffer is ready. This bit is particularly useful when
+ * transferring data by CPU polling mode, and it is not allowed to send out the
+ * external DMA request. By default, this bit is set.
+ *
+ * Values:
+ * - 0b0 - In any scenario, SDHC does not send out the external DMA request.
+ * - 0b1 - When internal DMA is not active, the external DMA request will be
+ *     sent out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field. */
+#define SDHC_RD_VENDOR_EXTDMAEN(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_EXTDMAEN_MASK) >> SDHC_VENDOR_EXTDMAEN_SHIFT)
+#define SDHC_BRD_VENDOR_EXTDMAEN(base) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXTDMAEN_SHIFT))
+
+/*! @brief Set the EXTDMAEN field to a new value. */
+#define SDHC_WR_VENDOR_EXTDMAEN(base, value) (SDHC_RMW_VENDOR(base, SDHC_VENDOR_EXTDMAEN_MASK, SDHC_VENDOR_EXTDMAEN(value)))
+#define SDHC_BWR_VENDOR_EXTDMAEN(base, value) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXTDMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
+ *
+ * This bit must be set before S/W issues CMD53 multi-block read with exact
+ * block number. This bit must not be set if the CMD53 multi-block read is not exact
+ * block number.
+ *
+ * Values:
+ * - 0b0 - None exact block read.
+ * - 0b1 - Exact block read for SDIO CMD53.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_EXBLKNU field. */
+#define SDHC_RD_VENDOR_EXBLKNU(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_EXBLKNU_MASK) >> SDHC_VENDOR_EXBLKNU_SHIFT)
+#define SDHC_BRD_VENDOR_EXBLKNU(base) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXBLKNU_SHIFT))
+
+/*! @brief Set the EXBLKNU field to a new value. */
+#define SDHC_WR_VENDOR_EXBLKNU(base, value) (SDHC_RMW_VENDOR(base, SDHC_VENDOR_EXBLKNU_MASK, SDHC_VENDOR_EXBLKNU(value)))
+#define SDHC_BWR_VENDOR_EXBLKNU(base, value) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXBLKNU_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
+ *
+ * Internal state value, reflecting the corresponding state value selected by
+ * Debug Select field. This field is read-only and write to this field does not
+ * have effect.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_INTSTVAL field. */
+#define SDHC_RD_VENDOR_INTSTVAL(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_INTSTVAL_MASK) >> SDHC_VENDOR_INTSTVAL_SHIFT)
+#define SDHC_BRD_VENDOR_INTSTVAL(base) (SDHC_RD_VENDOR_INTSTVAL(base))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_MMCBOOT - MMC Boot register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_MMCBOOT - MMC Boot register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the MMC fast boot control register.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_MMCBOOT register
+ */
+/*@{*/
+#define SDHC_RD_MMCBOOT(base)    (SDHC_MMCBOOT_REG(base))
+#define SDHC_WR_MMCBOOT(base, value) (SDHC_MMCBOOT_REG(base) = (value))
+#define SDHC_RMW_MMCBOOT(base, mask, value) (SDHC_WR_MMCBOOT(base, (SDHC_RD_MMCBOOT(base) & ~(mask)) | (value)))
+#define SDHC_SET_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) |  (value)))
+#define SDHC_CLR_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) & ~(value)))
+#define SDHC_TOG_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_MMCBOOT bitfields
+ */
+
+/*!
+ * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
+ *
+ * Values:
+ * - 0b0000 - SDCLK x 2^8
+ * - 0b0001 - SDCLK x 2^9
+ * - 0b0010 - SDCLK x 2^10
+ * - 0b0011 - SDCLK x 2^11
+ * - 0b0100 - SDCLK x 2^12
+ * - 0b0101 - SDCLK x 2^13
+ * - 0b0110 - SDCLK x 2^14
+ * - 0b0111 - SDCLK x 2^15
+ * - 0b1110 - SDCLK x 2^22
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field. */
+#define SDHC_RD_MMCBOOT_DTOCVACK(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_DTOCVACK_MASK) >> SDHC_MMCBOOT_DTOCVACK_SHIFT)
+#define SDHC_BRD_MMCBOOT_DTOCVACK(base) (SDHC_RD_MMCBOOT_DTOCVACK(base))
+
+/*! @brief Set the DTOCVACK field to a new value. */
+#define SDHC_WR_MMCBOOT_DTOCVACK(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_DTOCVACK_MASK, SDHC_MMCBOOT_DTOCVACK(value)))
+#define SDHC_BWR_MMCBOOT_DTOCVACK(base, value) (SDHC_WR_MMCBOOT_DTOCVACK(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
+ *
+ * Values:
+ * - 0b0 - No ack.
+ * - 0b1 - Ack.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field. */
+#define SDHC_RD_MMCBOOT_BOOTACK(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTACK_MASK) >> SDHC_MMCBOOT_BOOTACK_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTACK(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTACK_SHIFT))
+
+/*! @brief Set the BOOTACK field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTACK(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTACK_MASK, SDHC_MMCBOOT_BOOTACK(value)))
+#define SDHC_BWR_MMCBOOT_BOOTACK(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal boot.
+ * - 0b1 - Alternative boot.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field. */
+#define SDHC_RD_MMCBOOT_BOOTMODE(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTMODE_MASK) >> SDHC_MMCBOOT_BOOTMODE_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTMODE(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTMODE_SHIFT))
+
+/*! @brief Set the BOOTMODE field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTMODE(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTMODE_MASK, SDHC_MMCBOOT_BOOTMODE(value)))
+#define SDHC_BWR_MMCBOOT_BOOTMODE(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Fast boot disable.
+ * - 0b1 - Fast boot enable.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field. */
+#define SDHC_RD_MMCBOOT_BOOTEN(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTEN_MASK) >> SDHC_MMCBOOT_BOOTEN_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTEN(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTEN_SHIFT))
+
+/*! @brief Set the BOOTEN field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTEN(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTEN_MASK, SDHC_MMCBOOT_BOOTEN(value)))
+#define SDHC_BWR_MMCBOOT_BOOTEN(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
+ *
+ * When boot, enable auto stop at block gap function. This function will be
+ * triggered, and host will stop at block gap when received card block cnt is equal
+ * to BOOTBLKCNT.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field. */
+#define SDHC_RD_MMCBOOT_AUTOSABGEN(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_AUTOSABGEN_MASK) >> SDHC_MMCBOOT_AUTOSABGEN_SHIFT)
+#define SDHC_BRD_MMCBOOT_AUTOSABGEN(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_AUTOSABGEN_SHIFT))
+
+/*! @brief Set the AUTOSABGEN field to a new value. */
+#define SDHC_WR_MMCBOOT_AUTOSABGEN(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_AUTOSABGEN_MASK, SDHC_MMCBOOT_AUTOSABGEN(value)))
+#define SDHC_BWR_MMCBOOT_AUTOSABGEN(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_AUTOSABGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
+ *
+ * Defines the stop at block gap value of automatic mode. When received card
+ * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field. */
+#define SDHC_RD_MMCBOOT_BOOTBLKCNT(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTBLKCNT_MASK) >> SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTBLKCNT(base) (SDHC_RD_MMCBOOT_BOOTBLKCNT(base))
+
+/*! @brief Set the BOOTBLKCNT field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTBLKCNT(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTBLKCNT_MASK, SDHC_MMCBOOT_BOOTBLKCNT(value)))
+#define SDHC_BWR_MMCBOOT_BOOTBLKCNT(base, value) (SDHC_WR_MMCBOOT_BOOTBLKCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_HOSTVER - Host Controller Version
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_HOSTVER - Host Controller Version (RO)
+ *
+ * Reset value: 0x00001201U
+ *
+ * This register contains the vendor host controller version information. All
+ * bits are read only and will read the same as the power-reset value.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_HOSTVER register
+ */
+/*@{*/
+#define SDHC_RD_HOSTVER(base)    (SDHC_HOSTVER_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_HOSTVER bitfields
+ */
+
+/*!
+ * @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
+ *
+ * These status bits indicate the host controller specification version.
+ *
+ * Values:
+ * - 0b00000001 - SD host specification version 2.0, supports test event
+ *     register and ADMA.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HOSTVER_SVN field. */
+#define SDHC_RD_HOSTVER_SVN(base) ((SDHC_HOSTVER_REG(base) & SDHC_HOSTVER_SVN_MASK) >> SDHC_HOSTVER_SVN_SHIFT)
+#define SDHC_BRD_HOSTVER_SVN(base) (SDHC_RD_HOSTVER_SVN(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
+ *
+ * These status bits are reserved for the vendor version number. The host driver
+ * shall not use this status.
+ *
+ * Values:
+ * - 0b00000000 - Freescale SDHC version 1.0
+ * - 0b00010000 - Freescale SDHC version 2.0
+ * - 0b00010001 - Freescale SDHC version 2.1
+ * - 0b00010010 - Freescale SDHC version 2.2
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HOSTVER_VVN field. */
+#define SDHC_RD_HOSTVER_VVN(base) ((SDHC_HOSTVER_REG(base) & SDHC_HOSTVER_VVN_MASK) >> SDHC_HOSTVER_VVN_SHIFT)
+#define SDHC_BRD_HOSTVER_VVN(base) (SDHC_RD_HOSTVER_VVN(base))
+/*@}*/
+
+/*
+ * MK64F12 SIM
+ *
+ * System Integration Module
+ *
+ * Registers defined in this header file:
+ * - SIM_SOPT1 - System Options Register 1
+ * - SIM_SOPT1CFG - SOPT1 Configuration Register
+ * - SIM_SOPT2 - System Options Register 2
+ * - SIM_SOPT4 - System Options Register 4
+ * - SIM_SOPT5 - System Options Register 5
+ * - SIM_SOPT7 - System Options Register 7
+ * - SIM_SDID - System Device Identification Register
+ * - SIM_SCGC1 - System Clock Gating Control Register 1
+ * - SIM_SCGC2 - System Clock Gating Control Register 2
+ * - SIM_SCGC3 - System Clock Gating Control Register 3
+ * - SIM_SCGC4 - System Clock Gating Control Register 4
+ * - SIM_SCGC5 - System Clock Gating Control Register 5
+ * - SIM_SCGC6 - System Clock Gating Control Register 6
+ * - SIM_SCGC7 - System Clock Gating Control Register 7
+ * - SIM_CLKDIV1 - System Clock Divider Register 1
+ * - SIM_CLKDIV2 - System Clock Divider Register 2
+ * - SIM_FCFG1 - Flash Configuration Register 1
+ * - SIM_FCFG2 - Flash Configuration Register 2
+ * - SIM_UIDH - Unique Identification Register High
+ * - SIM_UIDMH - Unique Identification Register Mid-High
+ * - SIM_UIDML - Unique Identification Register Mid Low
+ * - SIM_UIDL - Unique Identification Register Low
+ */
+
+#define SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */
+#define SIM_IDX (0U) /*!< Instance number for SIM. */
+
+/*******************************************************************************
+ * SIM_SOPT1 - System Options Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1 - System Options Register 1 (RW)
+ *
+ * Reset value: 0x80000000U
+ *
+ * The SOPT1 register is only reset on POR or LVD.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1 register
+ */
+/*@{*/
+#define SIM_RD_SOPT1(base)       (SIM_SOPT1_REG(base))
+#define SIM_WR_SOPT1(base, value) (SIM_SOPT1_REG(base) = (value))
+#define SIM_RMW_SOPT1(base, mask, value) (SIM_WR_SOPT1(base, (SIM_RD_SOPT1(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) |  (value)))
+#define SIM_CLR_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) & ~(value)))
+#define SIM_TOG_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
+ *
+ * This field specifies the amount of system RAM available on the device.
+ *
+ * Values:
+ * - 0b0001 - 8 KB
+ * - 0b0011 - 16 KB
+ * - 0b0100 - 24 KB
+ * - 0b0101 - 32 KB
+ * - 0b0110 - 48 KB
+ * - 0b0111 - 64 KB
+ * - 0b1000 - 96 KB
+ * - 0b1001 - 128 KB
+ * - 0b1011 - 256 KB
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */
+#define SIM_RD_SOPT1_RAMSIZE(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_RAMSIZE_MASK) >> SIM_SOPT1_RAMSIZE_SHIFT)
+#define SIM_BRD_SOPT1_RAMSIZE(base) (SIM_RD_SOPT1_RAMSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
+ *
+ * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
+ * only on POR/LVD.
+ *
+ * Values:
+ * - 0b00 - System oscillator (OSC32KCLK)
+ * - 0b01 - Reserved
+ * - 0b10 - RTC 32.768kHz oscillator
+ * - 0b11 - LPO 1 kHz
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */
+#define SIM_RD_SOPT1_OSC32KSEL(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
+#define SIM_BRD_SOPT1_OSC32KSEL(base) (SIM_RD_SOPT1_OSC32KSEL(base))
+
+/*! @brief Set the OSC32KSEL field to a new value. */
+#define SIM_WR_SOPT1_OSC32KSEL(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_OSC32KSEL_MASK, SIM_SOPT1_OSC32KSEL(value)))
+#define SIM_BWR_SOPT1_OSC32KSEL(base, value) (SIM_WR_SOPT1_OSC32KSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * VLPR and VLPW modes.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator not in standby during VLPR and VLPW modes.
+ * - 0b1 - USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */
+#define SIM_RD_SOPT1_USBVSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBVSTBY_MASK) >> SIM_SOPT1_USBVSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBVSTBY(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT))
+
+/*! @brief Set the USBVSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBVSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBVSTBY_MASK, SIM_SOPT1_USBVSTBY(value)))
+#define SIM_BWR_SOPT1_USBVSTBY(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * Stop, VLPS, LLS and VLLS modes.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ * - 0b1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */
+#define SIM_RD_SOPT1_USBSSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBSSTBY_MASK) >> SIM_SOPT1_USBSSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBSSTBY(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT))
+
+/*! @brief Set the USBSSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBSSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBSSTBY_MASK, SIM_SOPT1_USBSSTBY(value)))
+#define SIM_BWR_SOPT1_USBSSTBY(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
+ *
+ * Controls whether the USB voltage regulator is enabled.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator is disabled.
+ * - 0b1 - USB voltage regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */
+#define SIM_RD_SOPT1_USBREGEN(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBREGEN_MASK) >> SIM_SOPT1_USBREGEN_SHIFT)
+#define SIM_BRD_SOPT1_USBREGEN(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT))
+
+/*! @brief Set the USBREGEN field to a new value. */
+#define SIM_WR_SOPT1_USBREGEN(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBREGEN_MASK, SIM_SOPT1_USBREGEN(value)))
+#define SIM_BWR_SOPT1_USBREGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT1CFG - SOPT1 Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The SOPT1CFG register is reset on System Reset not VLLS.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1CFG register
+ */
+/*@{*/
+#define SIM_RD_SOPT1CFG(base)    (SIM_SOPT1CFG_REG(base))
+#define SIM_WR_SOPT1CFG(base, value) (SIM_SOPT1CFG_REG(base) = (value))
+#define SIM_RMW_SOPT1CFG(base, mask, value) (SIM_WR_SOPT1CFG(base, (SIM_RD_SOPT1CFG(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) |  (value)))
+#define SIM_CLR_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) & ~(value)))
+#define SIM_TOG_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1CFG bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
+ *
+ * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
+ * register bit clears after a write to USBREGEN.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBREGEN cannot be written.
+ * - 0b1 - SOPT1 USBREGEN can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */
+#define SIM_RD_SOPT1CFG_URWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_URWE_MASK) >> SIM_SOPT1CFG_URWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_URWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT))
+
+/*! @brief Set the URWE field to a new value. */
+#define SIM_WR_SOPT1CFG_URWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_URWE_MASK, SIM_SOPT1CFG_URWE(value)))
+#define SIM_BWR_SOPT1CFG_URWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
+ *
+ * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
+ * This register bit clears after a write to USBVSTBY.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBVSTBY cannot be written.
+ * - 0b1 - SOPT1 USBVSTBY can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */
+#define SIM_RD_SOPT1CFG_UVSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_UVSWE_MASK) >> SIM_SOPT1CFG_UVSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_UVSWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT))
+
+/*! @brief Set the UVSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_UVSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_UVSWE_MASK, SIM_SOPT1CFG_UVSWE(value)))
+#define SIM_BWR_SOPT1CFG_UVSWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
+ *
+ * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
+ * This register bit clears after a write to USBSSTBY.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBSSTBY cannot be written.
+ * - 0b1 - SOPT1 USBSSTBY can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */
+#define SIM_RD_SOPT1CFG_USSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_USSWE_MASK) >> SIM_SOPT1CFG_USSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_USSWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT))
+
+/*! @brief Set the USSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_USSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_USSWE_MASK, SIM_SOPT1CFG_USSWE(value)))
+#define SIM_BWR_SOPT1CFG_USSWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT2 - System Options Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT2 - System Options Register 2 (RW)
+ *
+ * Reset value: 0x00001000U
+ *
+ * SOPT2 contains the controls for selecting many of the module clock source
+ * options on this device. See the Clock Distribution chapter for more information
+ * including clocking diagrams and definitions of device clocks.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT2 register
+ */
+/*@{*/
+#define SIM_RD_SOPT2(base)       (SIM_SOPT2_REG(base))
+#define SIM_WR_SOPT2(base, value) (SIM_SOPT2_REG(base) = (value))
+#define SIM_RMW_SOPT2(base, mask, value) (SIM_WR_SOPT2(base, (SIM_RD_SOPT2(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) |  (value)))
+#define SIM_CLR_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) & ~(value)))
+#define SIM_TOG_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
+ *
+ * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
+ * RTC_CLKOUT pin.
+ *
+ * Values:
+ * - 0b0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
+ * - 0b1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */
+#define SIM_RD_SOPT2_RTCCLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RTCCLKOUTSEL_MASK) >> SIM_SOPT2_RTCCLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_RTCCLKOUTSEL(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT))
+
+/*! @brief Set the RTCCLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_RTCCLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RTCCLKOUTSEL_MASK, SIM_SOPT2_RTCCLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_RTCCLKOUTSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
+ *
+ * Selects the clock to output on the CLKOUT pin.
+ *
+ * Values:
+ * - 0b000 - FlexBus CLKOUT
+ * - 0b001 - Reserved
+ * - 0b010 - Flash clock
+ * - 0b011 - LPO clock (1 kHz)
+ * - 0b100 - MCGIRCLK
+ * - 0b101 - RTC 32.768kHz clock
+ * - 0b110 - OSCERCLK0
+ * - 0b111 - IRC 48 MHz clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */
+#define SIM_RD_SOPT2_CLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_CLKOUTSEL_MASK) >> SIM_SOPT2_CLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_CLKOUTSEL(base) (SIM_RD_SOPT2_CLKOUTSEL(base))
+
+/*! @brief Set the CLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_CLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_CLKOUTSEL_MASK, SIM_SOPT2_CLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_CLKOUTSEL(base, value) (SIM_WR_SOPT2_CLKOUTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
+ *
+ * If flash security is enabled, then this field affects what CPU operations can
+ * access off-chip via the FlexBus interface. This field has no effect if flash
+ * security is not enabled.
+ *
+ * Values:
+ * - 0b00 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 0b01 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 0b10 - Off-chip instruction accesses are disallowed. Data accesses are
+ *     allowed.
+ * - 0b11 - Off-chip instruction accesses and data accesses are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_FBSL field. */
+#define SIM_RD_SOPT2_FBSL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_FBSL_MASK) >> SIM_SOPT2_FBSL_SHIFT)
+#define SIM_BRD_SOPT2_FBSL(base) (SIM_RD_SOPT2_FBSL(base))
+
+/*! @brief Set the FBSL field to a new value. */
+#define SIM_WR_SOPT2_FBSL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_FBSL_MASK, SIM_SOPT2_FBSL(value)))
+#define SIM_BWR_SOPT2_FBSL(base, value) (SIM_WR_SOPT2_FBSL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
+ *
+ * Controls the output drive strength of the PTD7 pin by selecting either one or
+ * two pads to drive it.
+ *
+ * Values:
+ * - 0b0 - Single-pad drive strength for PTD7.
+ * - 0b1 - Double pad drive strength for PTD7.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_PTD7PAD field. */
+#define SIM_RD_SOPT2_PTD7PAD(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_PTD7PAD_MASK) >> SIM_SOPT2_PTD7PAD_SHIFT)
+#define SIM_BRD_SOPT2_PTD7PAD(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_PTD7PAD_SHIFT))
+
+/*! @brief Set the PTD7PAD field to a new value. */
+#define SIM_WR_SOPT2_PTD7PAD(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_PTD7PAD_MASK, SIM_SOPT2_PTD7PAD(value)))
+#define SIM_BWR_SOPT2_PTD7PAD(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_PTD7PAD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
+ *
+ * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
+ * clock source.
+ *
+ * Values:
+ * - 0b0 - MCGOUTCLK
+ * - 0b1 - Core/system clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */
+#define SIM_RD_SOPT2_TRACECLKSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TRACECLKSEL_MASK) >> SIM_SOPT2_TRACECLKSEL_SHIFT)
+#define SIM_BRD_SOPT2_TRACECLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_TRACECLKSEL_SHIFT))
+
+/*! @brief Set the TRACECLKSEL field to a new value. */
+#define SIM_WR_SOPT2_TRACECLKSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TRACECLKSEL_MASK, SIM_SOPT2_TRACECLKSEL(value)))
+#define SIM_BWR_SOPT2_TRACECLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_TRACECLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
+ *
+ * Selects the high frequency clock for various peripheral clocking options.
+ *
+ * Values:
+ * - 0b00 - MCGFLLCLK clock
+ * - 0b01 - MCGPLLCLK clock
+ * - 0b10 - Reserved
+ * - 0b11 - IRC48 MHz clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */
+#define SIM_RD_SOPT2_PLLFLLSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
+#define SIM_BRD_SOPT2_PLLFLLSEL(base) (SIM_RD_SOPT2_PLLFLLSEL(base))
+
+/*! @brief Set the PLLFLLSEL field to a new value. */
+#define SIM_WR_SOPT2_PLLFLLSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_PLLFLLSEL_MASK, SIM_SOPT2_PLLFLLSEL(value)))
+#define SIM_BWR_SOPT2_PLLFLLSEL(base, value) (SIM_WR_SOPT2_PLLFLLSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field USBSRC[18] (RW)
+ *
+ * Selects the clock source for the USB 48 MHz clock.
+ *
+ * Values:
+ * - 0b0 - External bypass clock (USB_CLKIN).
+ * - 0b1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
+ *     SIM_CLKDIV2[USBFRAC, USBDIV].
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_USBSRC field. */
+#define SIM_RD_SOPT2_USBSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_USBSRC_MASK) >> SIM_SOPT2_USBSRC_SHIFT)
+#define SIM_BRD_SOPT2_USBSRC(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT))
+
+/*! @brief Set the USBSRC field to a new value. */
+#define SIM_WR_SOPT2_USBSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_USBSRC_MASK, SIM_SOPT2_USBSRC(value)))
+#define SIM_BWR_SOPT2_USBSRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field RMIISRC[19] (RW)
+ *
+ * Selects the clock source for the Ethernet RMII interface
+ *
+ * Values:
+ * - 0b0 - EXTAL clock
+ * - 0b1 - External bypass clock (ENET_1588_CLKIN).
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RMIISRC field. */
+#define SIM_RD_SOPT2_RMIISRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RMIISRC_MASK) >> SIM_SOPT2_RMIISRC_SHIFT)
+#define SIM_BRD_SOPT2_RMIISRC(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RMIISRC_SHIFT))
+
+/*! @brief Set the RMIISRC field to a new value. */
+#define SIM_WR_SOPT2_RMIISRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RMIISRC_MASK, SIM_SOPT2_RMIISRC(value)))
+#define SIM_BWR_SOPT2_RMIISRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RMIISRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
+ *
+ * Selects the clock source for the Ethernet timestamp clock.
+ *
+ * Values:
+ * - 0b00 - Core/system clock.
+ * - 0b01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 0b10 - OSCERCLK clock
+ * - 0b11 - External bypass clock (ENET_1588_CLKIN).
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TIMESRC field. */
+#define SIM_RD_SOPT2_TIMESRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TIMESRC_MASK) >> SIM_SOPT2_TIMESRC_SHIFT)
+#define SIM_BRD_SOPT2_TIMESRC(base) (SIM_RD_SOPT2_TIMESRC(base))
+
+/*! @brief Set the TIMESRC field to a new value. */
+#define SIM_WR_SOPT2_TIMESRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TIMESRC_MASK, SIM_SOPT2_TIMESRC(value)))
+#define SIM_BWR_SOPT2_TIMESRC(base, value) (SIM_WR_SOPT2_TIMESRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
+ *
+ * Selects the clock source for the SDHC clock .
+ *
+ * Values:
+ * - 0b00 - Core/system clock.
+ * - 0b01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 0b10 - OSCERCLK clock
+ * - 0b11 - External bypass clock (SDHC0_CLKIN)
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_SDHCSRC field. */
+#define SIM_RD_SOPT2_SDHCSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_SDHCSRC_MASK) >> SIM_SOPT2_SDHCSRC_SHIFT)
+#define SIM_BRD_SOPT2_SDHCSRC(base) (SIM_RD_SOPT2_SDHCSRC(base))
+
+/*! @brief Set the SDHCSRC field to a new value. */
+#define SIM_WR_SOPT2_SDHCSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_SDHCSRC_MASK, SIM_SOPT2_SDHCSRC(value)))
+#define SIM_BWR_SOPT2_SDHCSRC(base, value) (SIM_WR_SOPT2_SDHCSRC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT4 - System Options Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT4 - System Options Register 4 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT4 register
+ */
+/*@{*/
+#define SIM_RD_SOPT4(base)       (SIM_SOPT4_REG(base))
+#define SIM_WR_SOPT4(base, value) (SIM_SOPT4_REG(base) = (value))
+#define SIM_RMW_SOPT4(base, mask, value) (SIM_WR_SOPT4(base, (SIM_RD_SOPT4(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) |  (value)))
+#define SIM_CLR_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) & ~(value)))
+#define SIM_TOG_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
+ *
+ * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */
+#define SIM_RD_SOPT4_FTM0FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT0_MASK) >> SIM_SOPT4_FTM0FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT0_SHIFT))
+
+/*! @brief Set the FTM0FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT0_MASK, SIM_SOPT4_FTM0FLT0(value)))
+#define SIM_BWR_SOPT4_FTM0FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
+ *
+ * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT1 pin
+ * - 0b1 - CMP1 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */
+#define SIM_RD_SOPT4_FTM0FLT1(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT1_MASK) >> SIM_SOPT4_FTM0FLT1_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT1(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT1_SHIFT))
+
+/*! @brief Set the FTM0FLT1 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT1(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT1_MASK, SIM_SOPT4_FTM0FLT1(value)))
+#define SIM_BWR_SOPT4_FTM0FLT1(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
+ *
+ * Selects the source of FTM0 fault 2. The pin source for fault 2 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT2 pin
+ * - 0b1 - CMP2 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. */
+#define SIM_RD_SOPT4_FTM0FLT2(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT2_MASK) >> SIM_SOPT4_FTM0FLT2_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT2(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT2_SHIFT))
+
+/*! @brief Set the FTM0FLT2 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT2(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT2_MASK, SIM_SOPT4_FTM0FLT2(value)))
+#define SIM_BWR_SOPT4_FTM0FLT2(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
+ *
+ * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM1_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */
+#define SIM_RD_SOPT4_FTM1FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1FLT0_MASK) >> SIM_SOPT4_FTM1FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM1FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1FLT0_SHIFT))
+
+/*! @brief Set the FTM1FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM1FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1FLT0_MASK, SIM_SOPT4_FTM1FLT0(value)))
+#define SIM_BWR_SOPT4_FTM1FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
+ *
+ * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0b0 - FTM2_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */
+#define SIM_RD_SOPT4_FTM2FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2FLT0_MASK) >> SIM_SOPT4_FTM2FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM2FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2FLT0_SHIFT))
+
+/*! @brief Set the FTM2FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM2FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2FLT0_MASK, SIM_SOPT4_FTM2FLT0(value)))
+#define SIM_BWR_SOPT4_FTM2FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
+ *
+ * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0b0 - FTM3_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */
+#define SIM_RD_SOPT4_FTM3FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3FLT0_MASK) >> SIM_SOPT4_FTM3FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM3FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3FLT0_SHIFT))
+
+/*! @brief Set the FTM3FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM3FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3FLT0_MASK, SIM_SOPT4_FTM3FLT0(value)))
+#define SIM_BWR_SOPT4_FTM3FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
+ *
+ * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0b00 - FTM1_CH0 signal
+ * - 0b01 - CMP0 output
+ * - 0b10 - CMP1 output
+ * - 0b11 - USB start of frame pulse
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */
+#define SIM_RD_SOPT4_FTM1CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1CH0SRC_MASK) >> SIM_SOPT4_FTM1CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM1CH0SRC(base) (SIM_RD_SOPT4_FTM1CH0SRC(base))
+
+/*! @brief Set the FTM1CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM1CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1CH0SRC_MASK, SIM_SOPT4_FTM1CH0SRC(value)))
+#define SIM_BWR_SOPT4_FTM1CH0SRC(base, value) (SIM_WR_SOPT4_FTM1CH0SRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
+ *
+ * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0b00 - FTM2_CH0 signal
+ * - 0b01 - CMP0 output
+ * - 0b10 - CMP1 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */
+#define SIM_RD_SOPT4_FTM2CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2CH0SRC_MASK) >> SIM_SOPT4_FTM2CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM2CH0SRC(base) (SIM_RD_SOPT4_FTM2CH0SRC(base))
+
+/*! @brief Set the FTM2CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM2CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2CH0SRC_MASK, SIM_SOPT4_FTM2CH0SRC(value)))
+#define SIM_BWR_SOPT4_FTM2CH0SRC(base, value) (SIM_WR_SOPT4_FTM2CH0SRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM0 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM_CLK0 pin
+ * - 0b1 - FTM_CLK1 pin
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */
+#define SIM_RD_SOPT4_FTM0CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0CLKSEL_MASK) >> SIM_SOPT4_FTM0CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM0CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0CLKSEL_SHIFT))
+
+/*! @brief Set the FTM0CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM0CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0CLKSEL_MASK, SIM_SOPT4_FTM0CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM0CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM1 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM_CLK0 pin
+ * - 0b1 - FTM_CLK1 pin
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */
+#define SIM_RD_SOPT4_FTM1CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1CLKSEL_MASK) >> SIM_SOPT4_FTM1CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM1CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1CLKSEL_SHIFT))
+
+/*! @brief Set the FTM1CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM1CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1CLKSEL_MASK, SIM_SOPT4_FTM1CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM1CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM2 module. The
+ * selected pin must also be configured for the FTM2 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM2 external clock driven by FTM_CLK0 pin.
+ * - 0b1 - FTM2 external clock driven by FTM_CLK1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */
+#define SIM_RD_SOPT4_FTM2CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2CLKSEL_MASK) >> SIM_SOPT4_FTM2CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM2CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2CLKSEL_SHIFT))
+
+/*! @brief Set the FTM2CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM2CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2CLKSEL_MASK, SIM_SOPT4_FTM2CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM2CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM3 module. The
+ * selected pin must also be configured for the FTM3 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM3 external clock driven by FTM_CLK0 pin.
+ * - 0b1 - FTM3 external clock driven by FTM_CLK1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */
+#define SIM_RD_SOPT4_FTM3CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3CLKSEL_MASK) >> SIM_SOPT4_FTM3CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM3CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3CLKSEL_SHIFT))
+
+/*! @brief Set the FTM3CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM3CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3CLKSEL_MASK, SIM_SOPT4_FTM3CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM3CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 0.
+ *
+ * Values:
+ * - 0b0 - HSCMP0 output drives FTM0 hardware trigger 0
+ * - 0b1 - FTM1 channel match drives FTM0 hardware trigger 0
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */
+#define SIM_RD_SOPT4_FTM0TRG0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0TRG0SRC_MASK) >> SIM_SOPT4_FTM0TRG0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM0TRG0SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG0SRC_SHIFT))
+
+/*! @brief Set the FTM0TRG0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM0TRG0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0TRG0SRC_MASK, SIM_SOPT4_FTM0TRG0SRC(value)))
+#define SIM_BWR_SOPT4_FTM0TRG0SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG0SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 1.
+ *
+ * Values:
+ * - 0b0 - PDB output trigger 1 drives FTM0 hardware trigger 1
+ * - 0b1 - FTM2 channel match drives FTM0 hardware trigger 1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */
+#define SIM_RD_SOPT4_FTM0TRG1SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0TRG1SRC_MASK) >> SIM_SOPT4_FTM0TRG1SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM0TRG1SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG1SRC_SHIFT))
+
+/*! @brief Set the FTM0TRG1SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM0TRG1SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0TRG1SRC_MASK, SIM_SOPT4_FTM0TRG1SRC(value)))
+#define SIM_BWR_SOPT4_FTM0TRG1SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG1SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 0.
+ *
+ * Values:
+ * - 0b0 - Reserved
+ * - 0b1 - FTM1 channel match drives FTM3 hardware trigger 0
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */
+#define SIM_RD_SOPT4_FTM3TRG0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3TRG0SRC_MASK) >> SIM_SOPT4_FTM3TRG0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM3TRG0SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG0SRC_SHIFT))
+
+/*! @brief Set the FTM3TRG0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM3TRG0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3TRG0SRC_MASK, SIM_SOPT4_FTM3TRG0SRC(value)))
+#define SIM_BWR_SOPT4_FTM3TRG0SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG0SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 1.
+ *
+ * Values:
+ * - 0b0 - Reserved
+ * - 0b1 - FTM2 channel match drives FTM3 hardware trigger 1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */
+#define SIM_RD_SOPT4_FTM3TRG1SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3TRG1SRC_MASK) >> SIM_SOPT4_FTM3TRG1SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM3TRG1SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG1SRC_SHIFT))
+
+/*! @brief Set the FTM3TRG1SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM3TRG1SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3TRG1SRC_MASK, SIM_SOPT4_FTM3TRG1SRC(value)))
+#define SIM_BWR_SOPT4_FTM3TRG1SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG1SRC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT5 - System Options Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT5 - System Options Register 5 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT5 register
+ */
+/*@{*/
+#define SIM_RD_SOPT5(base)       (SIM_SOPT5_REG(base))
+#define SIM_WR_SOPT5(base, value) (SIM_SOPT5_REG(base) = (value))
+#define SIM_RMW_SOPT5(base, mask, value) (SIM_WR_SOPT5(base, (SIM_RD_SOPT5(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) |  (value)))
+#define SIM_CLR_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) & ~(value)))
+#define SIM_TOG_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
+ *
+ * Selects the source for the UART 0 transmit data.
+ *
+ * Values:
+ * - 0b00 - UART0_TX pin
+ * - 0b01 - UART0_TX pin modulated with FTM1 channel 0 output
+ * - 0b10 - UART0_TX pin modulated with FTM2 channel 0 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */
+#define SIM_RD_SOPT5_UART0TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART0TXSRC_MASK) >> SIM_SOPT5_UART0TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART0TXSRC(base) (SIM_RD_SOPT5_UART0TXSRC(base))
+
+/*! @brief Set the UART0TXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART0TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART0TXSRC_MASK, SIM_SOPT5_UART0TXSRC(value)))
+#define SIM_BWR_SOPT5_UART0TXSRC(base, value) (SIM_WR_SOPT5_UART0TXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
+ *
+ * Selects the source for the UART 0 receive data.
+ *
+ * Values:
+ * - 0b00 - UART0_RX pin
+ * - 0b01 - CMP0
+ * - 0b10 - CMP1
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */
+#define SIM_RD_SOPT5_UART0RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART0RXSRC_MASK) >> SIM_SOPT5_UART0RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART0RXSRC(base) (SIM_RD_SOPT5_UART0RXSRC(base))
+
+/*! @brief Set the UART0RXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART0RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART0RXSRC_MASK, SIM_SOPT5_UART0RXSRC(value)))
+#define SIM_BWR_SOPT5_UART0RXSRC(base, value) (SIM_WR_SOPT5_UART0RXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
+ *
+ * Selects the source for the UART 1 transmit data.
+ *
+ * Values:
+ * - 0b00 - UART1_TX pin
+ * - 0b01 - UART1_TX pin modulated with FTM1 channel 0 output
+ * - 0b10 - UART1_TX pin modulated with FTM2 channel 0 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */
+#define SIM_RD_SOPT5_UART1TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART1TXSRC_MASK) >> SIM_SOPT5_UART1TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART1TXSRC(base) (SIM_RD_SOPT5_UART1TXSRC(base))
+
+/*! @brief Set the UART1TXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART1TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART1TXSRC_MASK, SIM_SOPT5_UART1TXSRC(value)))
+#define SIM_BWR_SOPT5_UART1TXSRC(base, value) (SIM_WR_SOPT5_UART1TXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
+ *
+ * Selects the source for the UART 1 receive data.
+ *
+ * Values:
+ * - 0b00 - UART1_RX pin
+ * - 0b01 - CMP0
+ * - 0b10 - CMP1
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */
+#define SIM_RD_SOPT5_UART1RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART1RXSRC_MASK) >> SIM_SOPT5_UART1RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART1RXSRC(base) (SIM_RD_SOPT5_UART1RXSRC(base))
+
+/*! @brief Set the UART1RXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART1RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART1RXSRC_MASK, SIM_SOPT5_UART1RXSRC(value)))
+#define SIM_BWR_SOPT5_UART1RXSRC(base, value) (SIM_WR_SOPT5_UART1RXSRC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT7 - System Options Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT7 - System Options Register 7 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT7 register
+ */
+/*@{*/
+#define SIM_RD_SOPT7(base)       (SIM_SOPT7_REG(base))
+#define SIM_WR_SOPT7(base, value) (SIM_SOPT7_REG(base) = (value))
+#define SIM_RMW_SOPT7(base, mask, value) (SIM_WR_SOPT7(base, (SIM_RD_SOPT7(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) |  (value)))
+#define SIM_CLR_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) & ~(value)))
+#define SIM_TOG_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
+ *
+ * Selects the ADC0 trigger source when alternative triggers are functional in
+ * stop and VLPS modes. .
+ *
+ * Values:
+ * - 0b0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0b0001 - High speed comparator 0 output
+ * - 0b0010 - High speed comparator 1 output
+ * - 0b0011 - High speed comparator 2 output
+ * - 0b0100 - PIT trigger 0
+ * - 0b0101 - PIT trigger 1
+ * - 0b0110 - PIT trigger 2
+ * - 0b0111 - PIT trigger 3
+ * - 0b1000 - FTM0 trigger
+ * - 0b1001 - FTM1 trigger
+ * - 0b1010 - FTM2 trigger
+ * - 0b1011 - FTM3 trigger
+ * - 0b1100 - RTC alarm
+ * - 0b1101 - RTC seconds
+ * - 0b1110 - Low-power timer (LPTMR) trigger
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */
+#define SIM_RD_SOPT7_ADC0TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0TRGSEL_MASK) >> SIM_SOPT7_ADC0TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0TRGSEL(base) (SIM_RD_SOPT7_ADC0TRGSEL(base))
+
+/*! @brief Set the ADC0TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0TRGSEL_MASK, SIM_SOPT7_ADC0TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0TRGSEL(base, value) (SIM_WR_SOPT7_ADC0TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
+ *
+ * Selects the ADC0 pre-trigger source when alternative triggers are enabled
+ * through ADC0ALTTRGEN.
+ *
+ * Values:
+ * - 0b0 - Pre-trigger A
+ * - 0b1 - Pre-trigger B
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC0PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0PRETRGSEL_MASK) >> SIM_SOPT7_ADC0PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0PRETRGSEL(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT))
+
+/*! @brief Set the ADC0PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0PRETRGSEL_MASK, SIM_SOPT7_ADC0PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0PRETRGSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
+ *
+ * Enable alternative conversion triggers for ADC0.
+ *
+ * Values:
+ * - 0b0 - PDB trigger selected for ADC0.
+ * - 0b1 - Alternate trigger selected for ADC0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC0ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0ALTTRGEN_MASK) >> SIM_SOPT7_ADC0ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC0ALTTRGEN(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT))
+
+/*! @brief Set the ADC0ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC0ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0ALTTRGEN_MASK, SIM_SOPT7_ADC0ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC0ALTTRGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
+ *
+ * Selects the ADC1 trigger source when alternative triggers are functional in
+ * stop and VLPS modes.
+ *
+ * Values:
+ * - 0b0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0b0001 - High speed comparator 0 output
+ * - 0b0010 - High speed comparator 1 output
+ * - 0b0011 - High speed comparator 2 output
+ * - 0b0100 - PIT trigger 0
+ * - 0b0101 - PIT trigger 1
+ * - 0b0110 - PIT trigger 2
+ * - 0b0111 - PIT trigger 3
+ * - 0b1000 - FTM0 trigger
+ * - 0b1001 - FTM1 trigger
+ * - 0b1010 - FTM2 trigger
+ * - 0b1011 - FTM3 trigger
+ * - 0b1100 - RTC alarm
+ * - 0b1101 - RTC seconds
+ * - 0b1110 - Low-power timer (LPTMR) trigger
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */
+#define SIM_RD_SOPT7_ADC1TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1TRGSEL_MASK) >> SIM_SOPT7_ADC1TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC1TRGSEL(base) (SIM_RD_SOPT7_ADC1TRGSEL(base))
+
+/*! @brief Set the ADC1TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC1TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1TRGSEL_MASK, SIM_SOPT7_ADC1TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC1TRGSEL(base, value) (SIM_WR_SOPT7_ADC1TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
+ *
+ * Selects the ADC1 pre-trigger source when alternative triggers are enabled
+ * through ADC1ALTTRGEN.
+ *
+ * Values:
+ * - 0b0 - Pre-trigger A selected for ADC1.
+ * - 0b1 - Pre-trigger B selected for ADC1.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC1PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1PRETRGSEL_MASK) >> SIM_SOPT7_ADC1PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC1PRETRGSEL(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1PRETRGSEL_SHIFT))
+
+/*! @brief Set the ADC1PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC1PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1PRETRGSEL_MASK, SIM_SOPT7_ADC1PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC1PRETRGSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1PRETRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
+ *
+ * Enable alternative conversion triggers for ADC1.
+ *
+ * Values:
+ * - 0b0 - PDB trigger selected for ADC1
+ * - 0b1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC1ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1ALTTRGEN_MASK) >> SIM_SOPT7_ADC1ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC1ALTTRGEN(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1ALTTRGEN_SHIFT))
+
+/*! @brief Set the ADC1ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC1ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1ALTTRGEN_MASK, SIM_SOPT7_ADC1ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC1ALTTRGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1ALTTRGEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SDID - System Device Identification Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SDID - System Device Identification Register (RO)
+ *
+ * Reset value: 0x00000380U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SDID register
+ */
+/*@{*/
+#define SIM_RD_SDID(base)        (SIM_SDID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SDID bitfields
+ */
+
+/*!
+ * @name Register SIM_SDID, field PINID[3:0] (RO)
+ *
+ * Specifies the pincount of the device.
+ *
+ * Values:
+ * - 0b0000 - Reserved
+ * - 0b0001 - Reserved
+ * - 0b0010 - 32-pin
+ * - 0b0011 - Reserved
+ * - 0b0100 - 48-pin
+ * - 0b0101 - 64-pin
+ * - 0b0110 - 80-pin
+ * - 0b0111 - 81-pin or 121-pin
+ * - 0b1000 - 100-pin
+ * - 0b1001 - 121-pin
+ * - 0b1010 - 144-pin
+ * - 0b1011 - Custom pinout (WLCSP)
+ * - 0b1100 - 169-pin
+ * - 0b1101 - Reserved
+ * - 0b1110 - 256-pin
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_PINID field. */
+#define SIM_RD_SDID_PINID(base) ((SIM_SDID_REG(base) & SIM_SDID_PINID_MASK) >> SIM_SDID_PINID_SHIFT)
+#define SIM_BRD_SDID_PINID(base) (SIM_RD_SDID_PINID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMID[6:4] (RO)
+ *
+ * This field is maintained for compatibility only, but has been superceded by
+ * the SERIESID, FAMILYID and SUBFAMID fields in this register.
+ *
+ * Values:
+ * - 0b000 - K1x Family (without tamper)
+ * - 0b001 - K2x Family (without tamper)
+ * - 0b010 - K3x Family or K1x/K6x Family (with tamper)
+ * - 0b011 - K4x Family or K2x Family (with tamper)
+ * - 0b100 - K6x Family (without tamper)
+ * - 0b101 - K7x Family
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMID field. */
+#define SIM_RD_SDID_FAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMID_MASK) >> SIM_SDID_FAMID_SHIFT)
+#define SIM_BRD_SDID_FAMID(base) (SIM_RD_SDID_FAMID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field DIEID[11:7] (RO)
+ *
+ * Specifies the silicon feature set identication number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_DIEID field. */
+#define SIM_RD_SDID_DIEID(base) ((SIM_SDID_REG(base) & SIM_SDID_DIEID_MASK) >> SIM_SDID_DIEID_SHIFT)
+#define SIM_BRD_SDID_DIEID(base) (SIM_RD_SDID_DIEID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field REVID[15:12] (RO)
+ *
+ * Specifies the silicon implementation number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_REVID field. */
+#define SIM_RD_SDID_REVID(base) ((SIM_SDID_REG(base) & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT)
+#define SIM_BRD_SDID_REVID(base) (SIM_RD_SDID_REVID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SERIESID[23:20] (RO)
+ *
+ * Specifies the Kinetis series of the device.
+ *
+ * Values:
+ * - 0b0000 - Kinetis K series
+ * - 0b0001 - Kinetis L series
+ * - 0b0101 - Kinetis W series
+ * - 0b0110 - Kinetis V series
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SERIESID field. */
+#define SIM_RD_SDID_SERIESID(base) ((SIM_SDID_REG(base) & SIM_SDID_SERIESID_MASK) >> SIM_SDID_SERIESID_SHIFT)
+#define SIM_BRD_SDID_SERIESID(base) (SIM_RD_SDID_SERIESID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
+ *
+ * Specifies the Kinetis sub-family of the device.
+ *
+ * Values:
+ * - 0b0000 - Kx0 Subfamily
+ * - 0b0001 - Kx1 Subfamily (tamper detect)
+ * - 0b0010 - Kx2 Subfamily
+ * - 0b0011 - Kx3 Subfamily (tamper detect)
+ * - 0b0100 - Kx4 Subfamily
+ * - 0b0101 - Kx5 Subfamily (tamper detect)
+ * - 0b0110 - Kx6 Subfamily
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SUBFAMID field. */
+#define SIM_RD_SDID_SUBFAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_SUBFAMID_MASK) >> SIM_SDID_SUBFAMID_SHIFT)
+#define SIM_BRD_SDID_SUBFAMID(base) (SIM_RD_SDID_SUBFAMID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
+ *
+ * Specifies the Kinetis family of the device.
+ *
+ * Values:
+ * - 0b0001 - K1x Family
+ * - 0b0010 - K2x Family
+ * - 0b0011 - K3x Family
+ * - 0b0100 - K4x Family
+ * - 0b0110 - K6x Family
+ * - 0b0111 - K7x Family
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMILYID field. */
+#define SIM_RD_SDID_FAMILYID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMILYID_MASK) >> SIM_SDID_FAMILYID_SHIFT)
+#define SIM_BRD_SDID_FAMILYID(base) (SIM_RD_SDID_FAMILYID(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC1 - System Clock Gating Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC1 register
+ */
+/*@{*/
+#define SIM_RD_SCGC1(base)       (SIM_SCGC1_REG(base))
+#define SIM_WR_SCGC1(base, value) (SIM_SCGC1_REG(base) = (value))
+#define SIM_RMW_SCGC1(base, mask, value) (SIM_WR_SCGC1(base, (SIM_RD_SCGC1(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) |  (value)))
+#define SIM_CLR_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) & ~(value)))
+#define SIM_TOG_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) ^  (value)))
+/*@}*/
+
+/* Unified clock gate bit access macros */
+#define SIM_SCGC_BIT_REG(base, index)        (*((volatile uint32_t *)&SIM_SCGC1_REG(base) + (((uint32_t)(index) >> 5) - 0U)))
+#define SIM_SCGC_BIT_SHIFT(index)            ((uint32_t)(index) & ((1U << 5) - 1U))
+#define SIM_RD_SCGC_BIT(base, index)         (SIM_SCGC_BIT_REG((base), (index)) & (1U << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BRD_SCGC_BIT(base, index)        (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_WR_SCGC_BIT(base, index, value)  (SIM_SCGC_BIT_REG((base), (index)) = (SIM_SCGC_BIT_REG((base), (index)) & ~(1U << SIM_SCGC_BIT_SHIFT(index))) | ((uint32_t)(value) << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BWR_SCGC_BIT(base, index, value) (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)) = (uint32_t)(value))
+
+/*
+ * Constants & macros for individual SIM_SCGC1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC1, field I2C2[6] (RW)
+ *
+ * This bit controls the clock gate to the I2C2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_I2C2 field. */
+#define SIM_RD_SCGC1_I2C2(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_I2C2_MASK) >> SIM_SCGC1_I2C2_SHIFT)
+#define SIM_BRD_SCGC1_I2C2(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_I2C2_SHIFT))
+
+/*! @brief Set the I2C2 field to a new value. */
+#define SIM_WR_SCGC1_I2C2(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_I2C2_MASK, SIM_SCGC1_I2C2(value)))
+#define SIM_BWR_SCGC1_I2C2(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_I2C2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC1, field UART4[10] (RW)
+ *
+ * This bit controls the clock gate to the UART4 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_UART4 field. */
+#define SIM_RD_SCGC1_UART4(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_UART4_MASK) >> SIM_SCGC1_UART4_SHIFT)
+#define SIM_BRD_SCGC1_UART4(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART4_SHIFT))
+
+/*! @brief Set the UART4 field to a new value. */
+#define SIM_WR_SCGC1_UART4(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_UART4_MASK, SIM_SCGC1_UART4(value)))
+#define SIM_BWR_SCGC1_UART4(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC1, field UART5[11] (RW)
+ *
+ * This bit controls the clock gate to the UART5 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_UART5 field. */
+#define SIM_RD_SCGC1_UART5(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_UART5_MASK) >> SIM_SCGC1_UART5_SHIFT)
+#define SIM_BRD_SCGC1_UART5(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART5_SHIFT))
+
+/*! @brief Set the UART5 field to a new value. */
+#define SIM_WR_SCGC1_UART5(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_UART5_MASK, SIM_SCGC1_UART5(value)))
+#define SIM_BWR_SCGC1_UART5(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART5_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC2 - System Clock Gating Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
+ * AIPS1, define the clock gate control bits in the SCGC2. When accessing through
+ * AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC2 register
+ */
+/*@{*/
+#define SIM_RD_SCGC2(base)       (SIM_SCGC2_REG(base))
+#define SIM_WR_SCGC2(base, value) (SIM_SCGC2_REG(base) = (value))
+#define SIM_RMW_SCGC2(base, mask, value) (SIM_WR_SCGC2(base, (SIM_RD_SCGC2(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) |  (value)))
+#define SIM_CLR_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) & ~(value)))
+#define SIM_TOG_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC2, field ENET[0] (RW)
+ *
+ * This bit controls the clock gate to the ENET module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_ENET field. */
+#define SIM_RD_SCGC2_ENET(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_ENET_MASK) >> SIM_SCGC2_ENET_SHIFT)
+#define SIM_BRD_SCGC2_ENET(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_ENET_SHIFT))
+
+/*! @brief Set the ENET field to a new value. */
+#define SIM_WR_SCGC2_ENET(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_ENET_MASK, SIM_SCGC2_ENET(value)))
+#define SIM_BWR_SCGC2_ENET(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_ENET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC2, field DAC0[12] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_DAC0 field. */
+#define SIM_RD_SCGC2_DAC0(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_DAC0_MASK) >> SIM_SCGC2_DAC0_SHIFT)
+#define SIM_BRD_SCGC2_DAC0(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC0_SHIFT))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC2_DAC0(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_DAC0_MASK, SIM_SCGC2_DAC0(value)))
+#define SIM_BWR_SCGC2_DAC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC2, field DAC1[13] (RW)
+ *
+ * This bit controls the clock gate to the DAC1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_DAC1 field. */
+#define SIM_RD_SCGC2_DAC1(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_DAC1_MASK) >> SIM_SCGC2_DAC1_SHIFT)
+#define SIM_BRD_SCGC2_DAC1(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC1_SHIFT))
+
+/*! @brief Set the DAC1 field to a new value. */
+#define SIM_WR_SCGC2_DAC1(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_DAC1_MASK, SIM_SCGC2_DAC1(value)))
+#define SIM_BWR_SCGC2_DAC1(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC3 - System Clock Gating Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
+ * through AIPS1, define the clock gate control bits in the SCGC3. When accessing
+ * through AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC3 register
+ */
+/*@{*/
+#define SIM_RD_SCGC3(base)       (SIM_SCGC3_REG(base))
+#define SIM_WR_SCGC3(base, value) (SIM_SCGC3_REG(base) = (value))
+#define SIM_RMW_SCGC3(base, mask, value) (SIM_WR_SCGC3(base, (SIM_RD_SCGC3(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) |  (value)))
+#define SIM_CLR_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) & ~(value)))
+#define SIM_TOG_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC3 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC3, field RNGA[0] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_RNGA field. */
+#define SIM_RD_SCGC3_RNGA(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_RNGA_MASK) >> SIM_SCGC3_RNGA_SHIFT)
+#define SIM_BRD_SCGC3_RNGA(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_RNGA_SHIFT))
+
+/*! @brief Set the RNGA field to a new value. */
+#define SIM_WR_SCGC3_RNGA(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_RNGA_MASK, SIM_SCGC3_RNGA(value)))
+#define SIM_BWR_SCGC3_RNGA(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_RNGA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field SPI2[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_SPI2 field. */
+#define SIM_RD_SCGC3_SPI2(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_SPI2_MASK) >> SIM_SCGC3_SPI2_SHIFT)
+#define SIM_BRD_SCGC3_SPI2(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SPI2_SHIFT))
+
+/*! @brief Set the SPI2 field to a new value. */
+#define SIM_WR_SCGC3_SPI2(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_SPI2_MASK, SIM_SCGC3_SPI2(value)))
+#define SIM_BWR_SCGC3_SPI2(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SPI2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field SDHC[17] (RW)
+ *
+ * This bit controls the clock gate to the SDHC module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_SDHC field. */
+#define SIM_RD_SCGC3_SDHC(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_SDHC_MASK) >> SIM_SCGC3_SDHC_SHIFT)
+#define SIM_BRD_SCGC3_SDHC(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SDHC_SHIFT))
+
+/*! @brief Set the SDHC field to a new value. */
+#define SIM_WR_SCGC3_SDHC(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_SDHC_MASK, SIM_SCGC3_SDHC(value)))
+#define SIM_BWR_SCGC3_SDHC(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SDHC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field FTM2[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_FTM2 field. */
+#define SIM_RD_SCGC3_FTM2(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_FTM2_MASK) >> SIM_SCGC3_FTM2_SHIFT)
+#define SIM_BRD_SCGC3_FTM2(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM2_SHIFT))
+
+/*! @brief Set the FTM2 field to a new value. */
+#define SIM_WR_SCGC3_FTM2(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_FTM2_MASK, SIM_SCGC3_FTM2(value)))
+#define SIM_BWR_SCGC3_FTM2(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field FTM3[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM3 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_FTM3 field. */
+#define SIM_RD_SCGC3_FTM3(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_FTM3_MASK) >> SIM_SCGC3_FTM3_SHIFT)
+#define SIM_BRD_SCGC3_FTM3(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM3_SHIFT))
+
+/*! @brief Set the FTM3 field to a new value. */
+#define SIM_WR_SCGC3_FTM3(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_FTM3_MASK, SIM_SCGC3_FTM3(value)))
+#define SIM_BWR_SCGC3_FTM3(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field ADC1[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_ADC1 field. */
+#define SIM_RD_SCGC3_ADC1(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_ADC1_MASK) >> SIM_SCGC3_ADC1_SHIFT)
+#define SIM_BRD_SCGC3_ADC1(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_ADC1_SHIFT))
+
+/*! @brief Set the ADC1 field to a new value. */
+#define SIM_WR_SCGC3_ADC1(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_ADC1_MASK, SIM_SCGC3_ADC1(value)))
+#define SIM_BWR_SCGC3_ADC1(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_ADC1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC4 - System Clock Gating Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
+ *
+ * Reset value: 0xF0100030U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC4 register
+ */
+/*@{*/
+#define SIM_RD_SCGC4(base)       (SIM_SCGC4_REG(base))
+#define SIM_WR_SCGC4(base, value) (SIM_SCGC4_REG(base) = (value))
+#define SIM_RMW_SCGC4(base, mask, value) (SIM_WR_SCGC4(base, (SIM_RD_SCGC4(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) |  (value)))
+#define SIM_CLR_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) & ~(value)))
+#define SIM_TOG_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC4, field EWM[1] (RW)
+ *
+ * This bit controls the clock gate to the EWM module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_EWM field. */
+#define SIM_RD_SCGC4_EWM(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_EWM_MASK) >> SIM_SCGC4_EWM_SHIFT)
+#define SIM_BRD_SCGC4_EWM(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_EWM_SHIFT))
+
+/*! @brief Set the EWM field to a new value. */
+#define SIM_WR_SCGC4_EWM(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_EWM_MASK, SIM_SCGC4_EWM(value)))
+#define SIM_BWR_SCGC4_EWM(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_EWM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMT[2] (RW)
+ *
+ * This bit controls the clock gate to the CMT module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMT field. */
+#define SIM_RD_SCGC4_CMT(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMT_MASK) >> SIM_SCGC4_CMT_SHIFT)
+#define SIM_BRD_SCGC4_CMT(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT))
+
+/*! @brief Set the CMT field to a new value. */
+#define SIM_WR_SCGC4_CMT(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMT_MASK, SIM_SCGC4_CMT(value)))
+#define SIM_BWR_SCGC4_CMT(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C0[6] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C0 field. */
+#define SIM_RD_SCGC4_I2C0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C0_MASK) >> SIM_SCGC4_I2C0_SHIFT)
+#define SIM_BRD_SCGC4_I2C0(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT))
+
+/*! @brief Set the I2C0 field to a new value. */
+#define SIM_WR_SCGC4_I2C0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C0_MASK, SIM_SCGC4_I2C0(value)))
+#define SIM_BWR_SCGC4_I2C0(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C1[7] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C1 field. */
+#define SIM_RD_SCGC4_I2C1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C1_MASK) >> SIM_SCGC4_I2C1_SHIFT)
+#define SIM_BRD_SCGC4_I2C1(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT))
+
+/*! @brief Set the I2C1 field to a new value. */
+#define SIM_WR_SCGC4_I2C1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C1_MASK, SIM_SCGC4_I2C1(value)))
+#define SIM_BWR_SCGC4_I2C1(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART0[10] (RW)
+ *
+ * This bit controls the clock gate to the UART0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART0 field. */
+#define SIM_RD_SCGC4_UART0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT)
+#define SIM_BRD_SCGC4_UART0(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART0_SHIFT))
+
+/*! @brief Set the UART0 field to a new value. */
+#define SIM_WR_SCGC4_UART0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART0_MASK, SIM_SCGC4_UART0(value)))
+#define SIM_BWR_SCGC4_UART0(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART1[11] (RW)
+ *
+ * This bit controls the clock gate to the UART1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART1 field. */
+#define SIM_RD_SCGC4_UART1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT)
+#define SIM_BRD_SCGC4_UART1(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART1_SHIFT))
+
+/*! @brief Set the UART1 field to a new value. */
+#define SIM_WR_SCGC4_UART1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART1_MASK, SIM_SCGC4_UART1(value)))
+#define SIM_BWR_SCGC4_UART1(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART2[12] (RW)
+ *
+ * This bit controls the clock gate to the UART2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART2 field. */
+#define SIM_RD_SCGC4_UART2(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT)
+#define SIM_BRD_SCGC4_UART2(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT))
+
+/*! @brief Set the UART2 field to a new value. */
+#define SIM_WR_SCGC4_UART2(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART2_MASK, SIM_SCGC4_UART2(value)))
+#define SIM_BWR_SCGC4_UART2(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART3[13] (RW)
+ *
+ * This bit controls the clock gate to the UART3 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART3 field. */
+#define SIM_RD_SCGC4_UART3(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART3_MASK) >> SIM_SCGC4_UART3_SHIFT)
+#define SIM_BRD_SCGC4_UART3(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART3_SHIFT))
+
+/*! @brief Set the UART3 field to a new value. */
+#define SIM_WR_SCGC4_UART3(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART3_MASK, SIM_SCGC4_UART3(value)))
+#define SIM_BWR_SCGC4_UART3(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field USBOTG[18] (RW)
+ *
+ * This bit controls the clock gate to the USB module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_USBOTG field. */
+#define SIM_RD_SCGC4_USBOTG(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_USBOTG_MASK) >> SIM_SCGC4_USBOTG_SHIFT)
+#define SIM_BRD_SCGC4_USBOTG(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBOTG_SHIFT))
+
+/*! @brief Set the USBOTG field to a new value. */
+#define SIM_WR_SCGC4_USBOTG(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_USBOTG_MASK, SIM_SCGC4_USBOTG(value)))
+#define SIM_BWR_SCGC4_USBOTG(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBOTG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMP[19] (RW)
+ *
+ * This bit controls the clock gate to the comparator module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMP field. */
+#define SIM_RD_SCGC4_CMP(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMP_MASK) >> SIM_SCGC4_CMP_SHIFT)
+#define SIM_BRD_SCGC4_CMP(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT))
+
+/*! @brief Set the CMP field to a new value. */
+#define SIM_WR_SCGC4_CMP(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMP_MASK, SIM_SCGC4_CMP(value)))
+#define SIM_BWR_SCGC4_CMP(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field VREF[20] (RW)
+ *
+ * This bit controls the clock gate to the VREF module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_VREF field. */
+#define SIM_RD_SCGC4_VREF(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_VREF_MASK) >> SIM_SCGC4_VREF_SHIFT)
+#define SIM_BRD_SCGC4_VREF(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT))
+
+/*! @brief Set the VREF field to a new value. */
+#define SIM_WR_SCGC4_VREF(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_VREF_MASK, SIM_SCGC4_VREF(value)))
+#define SIM_BWR_SCGC4_VREF(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC5 - System Clock Gating Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
+ *
+ * Reset value: 0x00040182U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC5 register
+ */
+/*@{*/
+#define SIM_RD_SCGC5(base)       (SIM_SCGC5_REG(base))
+#define SIM_WR_SCGC5(base, value) (SIM_SCGC5_REG(base) = (value))
+#define SIM_RMW_SCGC5(base, mask, value) (SIM_WR_SCGC5(base, (SIM_RD_SCGC5(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) |  (value)))
+#define SIM_CLR_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) & ~(value)))
+#define SIM_TOG_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC5, field LPTMR[0] (RW)
+ *
+ * This bit controls software access to the Low Power Timer module.
+ *
+ * Values:
+ * - 0b0 - Access disabled
+ * - 0b1 - Access enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_LPTMR field. */
+#define SIM_RD_SCGC5_LPTMR(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPTMR_MASK) >> SIM_SCGC5_LPTMR_SHIFT)
+#define SIM_BRD_SCGC5_LPTMR(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT))
+
+/*! @brief Set the LPTMR field to a new value. */
+#define SIM_WR_SCGC5_LPTMR(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPTMR_MASK, SIM_SCGC5_LPTMR(value)))
+#define SIM_BWR_SCGC5_LPTMR(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTA[9] (RW)
+ *
+ * This bit controls the clock gate to the Port A module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTA field. */
+#define SIM_RD_SCGC5_PORTA(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTA_MASK) >> SIM_SCGC5_PORTA_SHIFT)
+#define SIM_BRD_SCGC5_PORTA(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT))
+
+/*! @brief Set the PORTA field to a new value. */
+#define SIM_WR_SCGC5_PORTA(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTA_MASK, SIM_SCGC5_PORTA(value)))
+#define SIM_BWR_SCGC5_PORTA(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTB[10] (RW)
+ *
+ * This bit controls the clock gate to the Port B module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTB field. */
+#define SIM_RD_SCGC5_PORTB(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTB_MASK) >> SIM_SCGC5_PORTB_SHIFT)
+#define SIM_BRD_SCGC5_PORTB(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT))
+
+/*! @brief Set the PORTB field to a new value. */
+#define SIM_WR_SCGC5_PORTB(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTB_MASK, SIM_SCGC5_PORTB(value)))
+#define SIM_BWR_SCGC5_PORTB(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTC[11] (RW)
+ *
+ * This bit controls the clock gate to the Port C module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTC field. */
+#define SIM_RD_SCGC5_PORTC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTC_MASK) >> SIM_SCGC5_PORTC_SHIFT)
+#define SIM_BRD_SCGC5_PORTC(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT))
+
+/*! @brief Set the PORTC field to a new value. */
+#define SIM_WR_SCGC5_PORTC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTC_MASK, SIM_SCGC5_PORTC(value)))
+#define SIM_BWR_SCGC5_PORTC(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTD[12] (RW)
+ *
+ * This bit controls the clock gate to the Port D module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTD field. */
+#define SIM_RD_SCGC5_PORTD(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTD_MASK) >> SIM_SCGC5_PORTD_SHIFT)
+#define SIM_BRD_SCGC5_PORTD(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT))
+
+/*! @brief Set the PORTD field to a new value. */
+#define SIM_WR_SCGC5_PORTD(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTD_MASK, SIM_SCGC5_PORTD(value)))
+#define SIM_BWR_SCGC5_PORTD(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTE[13] (RW)
+ *
+ * This bit controls the clock gate to the Port E module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTE field. */
+#define SIM_RD_SCGC5_PORTE(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTE_MASK) >> SIM_SCGC5_PORTE_SHIFT)
+#define SIM_BRD_SCGC5_PORTE(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT))
+
+/*! @brief Set the PORTE field to a new value. */
+#define SIM_WR_SCGC5_PORTE(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTE_MASK, SIM_SCGC5_PORTE(value)))
+#define SIM_BWR_SCGC5_PORTE(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC6 - System Clock Gating Control Register 6
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
+ *
+ * Reset value: 0x40000001U
+ *
+ * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
+ * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
+ * When accessing through AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC6 register
+ */
+/*@{*/
+#define SIM_RD_SCGC6(base)       (SIM_SCGC6_REG(base))
+#define SIM_WR_SCGC6(base, value) (SIM_SCGC6_REG(base) = (value))
+#define SIM_RMW_SCGC6(base, mask, value) (SIM_WR_SCGC6(base, (SIM_RD_SCGC6(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) |  (value)))
+#define SIM_CLR_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) & ~(value)))
+#define SIM_TOG_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC6 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC6, field FTF[0] (RW)
+ *
+ * This bit controls the clock gate to the flash memory. Flash reads are still
+ * supported while the flash memory is clock gated, but entry into low power modes
+ * is blocked.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTF field. */
+#define SIM_RD_SCGC6_FTF(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTF_MASK) >> SIM_SCGC6_FTF_SHIFT)
+#define SIM_BRD_SCGC6_FTF(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT))
+
+/*! @brief Set the FTF field to a new value. */
+#define SIM_WR_SCGC6_FTF(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTF_MASK, SIM_SCGC6_FTF(value)))
+#define SIM_BWR_SCGC6_FTF(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA Mux module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */
+#define SIM_RD_SCGC6_DMAMUX(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DMAMUX_MASK) >> SIM_SCGC6_DMAMUX_SHIFT)
+#define SIM_BRD_SCGC6_DMAMUX(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT))
+
+/*! @brief Set the DMAMUX field to a new value. */
+#define SIM_WR_SCGC6_DMAMUX(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DMAMUX_MASK, SIM_SCGC6_DMAMUX(value)))
+#define SIM_BWR_SCGC6_DMAMUX(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
+ *
+ * This bit controls the clock gate to the FlexCAN0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. */
+#define SIM_RD_SCGC6_FLEXCAN0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FLEXCAN0_MASK) >> SIM_SCGC6_FLEXCAN0_SHIFT)
+#define SIM_BRD_SCGC6_FLEXCAN0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FLEXCAN0_SHIFT))
+
+/*! @brief Set the FLEXCAN0 field to a new value. */
+#define SIM_WR_SCGC6_FLEXCAN0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FLEXCAN0_MASK, SIM_SCGC6_FLEXCAN0(value)))
+#define SIM_BWR_SCGC6_FLEXCAN0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FLEXCAN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RNGA[9] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RNGA field. */
+#define SIM_RD_SCGC6_RNGA(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RNGA_MASK) >> SIM_SCGC6_RNGA_SHIFT)
+#define SIM_BRD_SCGC6_RNGA(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RNGA_SHIFT))
+
+/*! @brief Set the RNGA field to a new value. */
+#define SIM_WR_SCGC6_RNGA(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RNGA_MASK, SIM_SCGC6_RNGA(value)))
+#define SIM_BWR_SCGC6_RNGA(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RNGA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field SPI0[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_SPI0 field. */
+#define SIM_RD_SCGC6_SPI0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI0_MASK) >> SIM_SCGC6_SPI0_SHIFT)
+#define SIM_BRD_SCGC6_SPI0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT))
+
+/*! @brief Set the SPI0 field to a new value. */
+#define SIM_WR_SCGC6_SPI0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI0_MASK, SIM_SCGC6_SPI0(value)))
+#define SIM_BWR_SCGC6_SPI0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field SPI1[13] (RW)
+ *
+ * This bit controls the clock gate to the SPI1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_SPI1 field. */
+#define SIM_RD_SCGC6_SPI1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI1_MASK) >> SIM_SCGC6_SPI1_SHIFT)
+#define SIM_BRD_SCGC6_SPI1(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT))
+
+/*! @brief Set the SPI1 field to a new value. */
+#define SIM_WR_SCGC6_SPI1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI1_MASK, SIM_SCGC6_SPI1(value)))
+#define SIM_BWR_SCGC6_SPI1(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field I2S[15] (RW)
+ *
+ * This bit controls the clock gate to the I 2 S module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_I2S field. */
+#define SIM_RD_SCGC6_I2S(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_I2S_MASK) >> SIM_SCGC6_I2S_SHIFT)
+#define SIM_BRD_SCGC6_I2S(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT))
+
+/*! @brief Set the I2S field to a new value. */
+#define SIM_WR_SCGC6_I2S(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_I2S_MASK, SIM_SCGC6_I2S(value)))
+#define SIM_BWR_SCGC6_I2S(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field CRC[18] (RW)
+ *
+ * This bit controls the clock gate to the CRC module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_CRC field. */
+#define SIM_RD_SCGC6_CRC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_CRC_MASK) >> SIM_SCGC6_CRC_SHIFT)
+#define SIM_BRD_SCGC6_CRC(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_CRC_SHIFT))
+
+/*! @brief Set the CRC field to a new value. */
+#define SIM_WR_SCGC6_CRC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_CRC_MASK, SIM_SCGC6_CRC(value)))
+#define SIM_BWR_SCGC6_CRC(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_CRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field USBDCD[21] (RW)
+ *
+ * This bit controls the clock gate to the USB DCD module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_USBDCD field. */
+#define SIM_RD_SCGC6_USBDCD(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_USBDCD_MASK) >> SIM_SCGC6_USBDCD_SHIFT)
+#define SIM_BRD_SCGC6_USBDCD(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_USBDCD_SHIFT))
+
+/*! @brief Set the USBDCD field to a new value. */
+#define SIM_WR_SCGC6_USBDCD(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_USBDCD_MASK, SIM_SCGC6_USBDCD(value)))
+#define SIM_BWR_SCGC6_USBDCD(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_USBDCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PDB[22] (RW)
+ *
+ * This bit controls the clock gate to the PDB module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PDB field. */
+#define SIM_RD_SCGC6_PDB(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PDB_MASK) >> SIM_SCGC6_PDB_SHIFT)
+#define SIM_BRD_SCGC6_PDB(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PDB_SHIFT))
+
+/*! @brief Set the PDB field to a new value. */
+#define SIM_WR_SCGC6_PDB(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PDB_MASK, SIM_SCGC6_PDB(value)))
+#define SIM_BWR_SCGC6_PDB(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PDB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PIT[23] (RW)
+ *
+ * This bit controls the clock gate to the PIT module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PIT field. */
+#define SIM_RD_SCGC6_PIT(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PIT_MASK) >> SIM_SCGC6_PIT_SHIFT)
+#define SIM_BRD_SCGC6_PIT(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT))
+
+/*! @brief Set the PIT field to a new value. */
+#define SIM_WR_SCGC6_PIT(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PIT_MASK, SIM_SCGC6_PIT(value)))
+#define SIM_BWR_SCGC6_PIT(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM0[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM0 field. */
+#define SIM_RD_SCGC6_FTM0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM0_MASK) >> SIM_SCGC6_FTM0_SHIFT)
+#define SIM_BRD_SCGC6_FTM0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM0_SHIFT))
+
+/*! @brief Set the FTM0 field to a new value. */
+#define SIM_WR_SCGC6_FTM0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM0_MASK, SIM_SCGC6_FTM0(value)))
+#define SIM_BWR_SCGC6_FTM0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM1[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM1 field. */
+#define SIM_RD_SCGC6_FTM1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM1_MASK) >> SIM_SCGC6_FTM1_SHIFT)
+#define SIM_BRD_SCGC6_FTM1(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM1_SHIFT))
+
+/*! @brief Set the FTM1 field to a new value. */
+#define SIM_WR_SCGC6_FTM1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM1_MASK, SIM_SCGC6_FTM1(value)))
+#define SIM_BWR_SCGC6_FTM1(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM2[26] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM2 field. */
+#define SIM_RD_SCGC6_FTM2(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM2_MASK) >> SIM_SCGC6_FTM2_SHIFT)
+#define SIM_BRD_SCGC6_FTM2(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM2_SHIFT))
+
+/*! @brief Set the FTM2 field to a new value. */
+#define SIM_WR_SCGC6_FTM2(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM2_MASK, SIM_SCGC6_FTM2(value)))
+#define SIM_BWR_SCGC6_FTM2(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field ADC0[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_ADC0 field. */
+#define SIM_RD_SCGC6_ADC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_ADC0_MASK) >> SIM_SCGC6_ADC0_SHIFT)
+#define SIM_BRD_SCGC6_ADC0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT))
+
+/*! @brief Set the ADC0 field to a new value. */
+#define SIM_WR_SCGC6_ADC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_ADC0_MASK, SIM_SCGC6_ADC0(value)))
+#define SIM_BWR_SCGC6_ADC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RTC[29] (RW)
+ *
+ * This bit controls software access and interrupts to the RTC module.
+ *
+ * Values:
+ * - 0b0 - Access and interrupts disabled
+ * - 0b1 - Access and interrupts enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RTC field. */
+#define SIM_RD_SCGC6_RTC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RTC_MASK) >> SIM_SCGC6_RTC_SHIFT)
+#define SIM_BRD_SCGC6_RTC(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT))
+
+/*! @brief Set the RTC field to a new value. */
+#define SIM_WR_SCGC6_RTC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RTC_MASK, SIM_SCGC6_RTC(value)))
+#define SIM_BWR_SCGC6_RTC(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DAC0[31] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DAC0 field. */
+#define SIM_RD_SCGC6_DAC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DAC0_MASK) >> SIM_SCGC6_DAC0_SHIFT)
+#define SIM_BRD_SCGC6_DAC0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC6_DAC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DAC0_MASK, SIM_SCGC6_DAC0(value)))
+#define SIM_BWR_SCGC6_DAC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC7 - System Clock Gating Control Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
+ *
+ * Reset value: 0x00000006U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC7 register
+ */
+/*@{*/
+#define SIM_RD_SCGC7(base)       (SIM_SCGC7_REG(base))
+#define SIM_WR_SCGC7(base, value) (SIM_SCGC7_REG(base) = (value))
+#define SIM_RMW_SCGC7(base, mask, value) (SIM_WR_SCGC7(base, (SIM_RD_SCGC7(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) |  (value)))
+#define SIM_CLR_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) & ~(value)))
+#define SIM_TOG_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
+ *
+ * This bit controls the clock gate to the FlexBus module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */
+#define SIM_RD_SCGC7_FLEXBUS(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_FLEXBUS_MASK) >> SIM_SCGC7_FLEXBUS_SHIFT)
+#define SIM_BRD_SCGC7_FLEXBUS(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_FLEXBUS_SHIFT))
+
+/*! @brief Set the FLEXBUS field to a new value. */
+#define SIM_WR_SCGC7_FLEXBUS(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_FLEXBUS_MASK, SIM_SCGC7_FLEXBUS(value)))
+#define SIM_BWR_SCGC7_FLEXBUS(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_FLEXBUS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC7, field DMA[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_DMA field. */
+#define SIM_RD_SCGC7_DMA(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_DMA_MASK) >> SIM_SCGC7_DMA_SHIFT)
+#define SIM_BRD_SCGC7_DMA(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define SIM_WR_SCGC7_DMA(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_DMA_MASK, SIM_SCGC7_DMA(value)))
+#define SIM_BWR_SCGC7_DMA(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC7, field MPU[2] (RW)
+ *
+ * This bit controls the clock gate to the MPU module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_MPU field. */
+#define SIM_RD_SCGC7_MPU(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_MPU_MASK) >> SIM_SCGC7_MPU_SHIFT)
+#define SIM_BRD_SCGC7_MPU(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_MPU_SHIFT))
+
+/*! @brief Set the MPU field to a new value. */
+#define SIM_WR_SCGC7_MPU(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_MPU_MASK, SIM_SCGC7_MPU(value)))
+#define SIM_BWR_SCGC7_MPU(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_MPU_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV1 - System Clock Divider Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * When updating CLKDIV1, update all fields using the one write command.
+ * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
+ * write to be ignored. The maximum divide ratio that can be programmed between
+ * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
+ * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
+ * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
+ * mode.
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV1 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV1(base)     (SIM_CLKDIV1_REG(base))
+#define SIM_WR_CLKDIV1(base, value) (SIM_CLKDIV1_REG(base) = (value))
+#define SIM_RMW_CLKDIV1(base, mask, value) (SIM_WR_CLKDIV1(base, (SIM_RD_CLKDIV1(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) |  (value)))
+#define SIM_CLR_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) & ~(value)))
+#define SIM_TOG_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV1 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
+ *
+ * This field sets the divide value for the flash clock from MCGOUTCLK. At the
+ * end of reset, it is loaded with either 0001 or 1111 depending on
+ * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
+ * frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */
+#define SIM_RD_CLKDIV1_OUTDIV4(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV4(base) (SIM_RD_CLKDIV1_OUTDIV4(base))
+
+/*! @brief Set the OUTDIV4 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV4(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV4_MASK, SIM_CLKDIV1_OUTDIV4(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV4(base, value) (SIM_WR_CLKDIV1_OUTDIV4(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
+ *
+ * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
+ * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
+ * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
+ * divide of the system clock frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */
+#define SIM_RD_CLKDIV1_OUTDIV3(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV3(base) (SIM_RD_CLKDIV1_OUTDIV3(base))
+
+/*! @brief Set the OUTDIV3 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV3(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV3_MASK, SIM_CLKDIV1_OUTDIV3(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV3(base, value) (SIM_WR_CLKDIV1_OUTDIV3(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
+ *
+ * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
+ * of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
+ * frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */
+#define SIM_RD_CLKDIV1_OUTDIV2(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV2(base) (SIM_RD_CLKDIV1_OUTDIV2(base))
+
+/*! @brief Set the OUTDIV2 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV2(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV2_MASK, SIM_CLKDIV1_OUTDIV2(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV2(base, value) (SIM_WR_CLKDIV1_OUTDIV2(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
+ *
+ * This field sets the divide value for the core/system clock from MCGOUTCLK. At
+ * the end of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT].
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */
+#define SIM_RD_CLKDIV1_OUTDIV1(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV1(base) (SIM_RD_CLKDIV1_OUTDIV1(base))
+
+/*! @brief Set the OUTDIV1 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV1(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV1_MASK, SIM_CLKDIV1_OUTDIV1(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV1(base, value) (SIM_WR_CLKDIV1_OUTDIV1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV2 - System Clock Divider Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV2 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV2(base)     (SIM_CLKDIV2_REG(base))
+#define SIM_WR_CLKDIV2(base, value) (SIM_CLKDIV2_REG(base) = (value))
+#define SIM_RMW_CLKDIV2(base, mask, value) (SIM_WR_CLKDIV2(base, (SIM_RD_CLKDIV2(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) |  (value)))
+#define SIM_CLR_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) & ~(value)))
+#define SIM_TOG_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV2 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
+ *
+ * This field sets the fraction multiply value for the fractional clock divider
+ * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
+ * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. */
+#define SIM_RD_CLKDIV2_USBFRAC(base) ((SIM_CLKDIV2_REG(base) & SIM_CLKDIV2_USBFRAC_MASK) >> SIM_CLKDIV2_USBFRAC_SHIFT)
+#define SIM_BRD_CLKDIV2_USBFRAC(base) (BITBAND_ACCESS32(&SIM_CLKDIV2_REG(base), SIM_CLKDIV2_USBFRAC_SHIFT))
+
+/*! @brief Set the USBFRAC field to a new value. */
+#define SIM_WR_CLKDIV2_USBFRAC(base, value) (SIM_RMW_CLKDIV2(base, SIM_CLKDIV2_USBFRAC_MASK, SIM_CLKDIV2_USBFRAC(value)))
+#define SIM_BWR_CLKDIV2_USBFRAC(base, value) (BITBAND_ACCESS32(&SIM_CLKDIV2_REG(base), SIM_CLKDIV2_USBFRAC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
+ *
+ * This field sets the divide value for the fractional clock divider when the
+ * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
+ * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV2_USBDIV field. */
+#define SIM_RD_CLKDIV2_USBDIV(base) ((SIM_CLKDIV2_REG(base) & SIM_CLKDIV2_USBDIV_MASK) >> SIM_CLKDIV2_USBDIV_SHIFT)
+#define SIM_BRD_CLKDIV2_USBDIV(base) (SIM_RD_CLKDIV2_USBDIV(base))
+
+/*! @brief Set the USBDIV field to a new value. */
+#define SIM_WR_CLKDIV2_USBDIV(base, value) (SIM_RMW_CLKDIV2(base, SIM_CLKDIV2_USBDIV_MASK, SIM_CLKDIV2_USBDIV(value)))
+#define SIM_BWR_CLKDIV2_USBDIV(base, value) (SIM_WR_CLKDIV2_USBDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG1 - Flash Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG1 - Flash Configuration Register 1 (RW)
+ *
+ * Reset value: 0xFF0F0F00U
+ *
+ * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
+ * user programming in user IFR via the PGMPART flash command. For devices with
+ * program flash only:
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG1 register
+ */
+/*@{*/
+#define SIM_RD_FCFG1(base)       (SIM_FCFG1_REG(base))
+#define SIM_WR_FCFG1(base, value) (SIM_FCFG1_REG(base) = (value))
+#define SIM_RMW_FCFG1(base, mask, value) (SIM_WR_FCFG1(base, (SIM_RD_FCFG1(base) & ~(mask)) | (value)))
+#define SIM_SET_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) |  (value)))
+#define SIM_CLR_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) & ~(value)))
+#define SIM_TOG_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG1 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
+ *
+ * Flash accesses are disabled (and generate a bus error) and the Flash memory
+ * is placed in a low power state. This bit should not be changed during VLP
+ * modes. Relocate the interrupt vectors out of Flash memory before disabling the
+ * Flash.
+ *
+ * Values:
+ * - 0b0 - Flash is enabled
+ * - 0b1 - Flash is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */
+#define SIM_RD_FCFG1_FLASHDIS(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDIS_MASK) >> SIM_FCFG1_FLASHDIS_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDIS(base) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT))
+
+/*! @brief Set the FLASHDIS field to a new value. */
+#define SIM_WR_FCFG1_FLASHDIS(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDIS_MASK, SIM_FCFG1_FLASHDIS(value)))
+#define SIM_BWR_FCFG1_FLASHDIS(base, value) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
+ *
+ * When set, Flash memory is disabled for the duration of Wait mode. An attempt
+ * by the DMA or other bus master to access the Flash when the Flash is disabled
+ * will result in a bus error. This bit should be clear during VLP modes. The
+ * Flash will be automatically enabled again at the end of Wait mode so interrupt
+ * vectors do not need to be relocated out of Flash memory. The wakeup time from
+ * Wait mode is extended when this bit is set.
+ *
+ * Values:
+ * - 0b0 - Flash remains enabled during Wait mode
+ * - 0b1 - Flash is disabled for the duration of Wait mode
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */
+#define SIM_RD_FCFG1_FLASHDOZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDOZE_MASK) >> SIM_FCFG1_FLASHDOZE_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDOZE(base) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT))
+
+/*! @brief Set the FLASHDOZE field to a new value. */
+#define SIM_WR_FCFG1_FLASHDOZE(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDOZE_MASK, SIM_FCFG1_FLASHDOZE(value)))
+#define SIM_BWR_FCFG1_FLASHDOZE(base, value) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
+ *
+ * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
+ * description in FTFE chapter. For devices without FlexNVM: Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_DEPART field. */
+#define SIM_RD_FCFG1_DEPART(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT)
+#define SIM_BRD_FCFG1_DEPART(base) (SIM_RD_FCFG1_DEPART(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
+ *
+ * EEPROM data size .
+ *
+ * Values:
+ * - 0b0000 - 16 KB
+ * - 0b0001 - 8 KB
+ * - 0b0010 - 4 KB
+ * - 0b0011 - 2 KB
+ * - 0b0100 - 1 KB
+ * - 0b0101 - 512 Bytes
+ * - 0b0110 - 256 Bytes
+ * - 0b0111 - 128 Bytes
+ * - 0b1000 - 64 Bytes
+ * - 0b1001 - 32 Bytes
+ * - 0b1111 - 0 Bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_EESIZE field. */
+#define SIM_RD_FCFG1_EESIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_EESIZE_MASK) >> SIM_FCFG1_EESIZE_SHIFT)
+#define SIM_BRD_FCFG1_EESIZE(base) (SIM_RD_FCFG1_EESIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
+ *
+ * This field specifies the amount of program flash memory available on the
+ * device . Undefined values are reserved.
+ *
+ * Values:
+ * - 0b0011 - 32 KB of program flash memory
+ * - 0b0101 - 64 KB of program flash memory
+ * - 0b0111 - 128 KB of program flash memory
+ * - 0b1001 - 256 KB of program flash memory
+ * - 0b1011 - 512 KB of program flash memory
+ * - 0b1101 - 1024 KB of program flash memory
+ * - 0b1111 - 1024 KB of program flash memory
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */
+#define SIM_RD_FCFG1_PFSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT)
+#define SIM_BRD_FCFG1_PFSIZE(base) (SIM_RD_FCFG1_PFSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
+ *
+ * This field specifies the amount of FlexNVM memory available on the device .
+ * Undefined values are reserved.
+ *
+ * Values:
+ * - 0b0000 - 0 KB of FlexNVM
+ * - 0b0011 - 32 KB of FlexNVM
+ * - 0b0101 - 64 KB of FlexNVM
+ * - 0b0111 - 128 KB of FlexNVM
+ * - 0b1001 - 256 KB of FlexNVM
+ * - 0b1011 - 512 KB of FlexNVM
+ * - 0b1111 - 512 KB of FlexNVM
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_NVMSIZE field. */
+#define SIM_RD_FCFG1_NVMSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_NVMSIZE_MASK) >> SIM_FCFG1_NVMSIZE_SHIFT)
+#define SIM_BRD_FCFG1_NVMSIZE(base) (SIM_RD_FCFG1_NVMSIZE(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG2 - Flash Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG2 - Flash Configuration Register 2 (RO)
+ *
+ * Reset value: 0x7F7F0000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG2 register
+ */
+/*@{*/
+#define SIM_RD_FCFG2(base)       (SIM_FCFG2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG2 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
+ *
+ * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
+ * the FlexNVM base address indicates the first invalid address of the FlexNVM
+ * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
+ * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
+ * for a device with 256 KB FlexNVM. For devices with program flash only: This
+ * field equals zero if there is only one program flash block, otherwise it equals
+ * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
+ * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
+ * the MAXADDR1 value for a device with 512 KB program flash memory across two
+ * flash blocks and no FlexNVM.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */
+#define SIM_RD_FCFG2_MAXADDR1(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR1_MASK) >> SIM_FCFG2_MAXADDR1_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR1(base) (SIM_RD_FCFG2_MAXADDR1(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field PFLSH[23] (RO)
+ *
+ * For devices with FlexNVM, this bit is always clear. For devices without
+ * FlexNVM, this bit is always set.
+ *
+ * Values:
+ * - 0b0 - Device supports FlexNVM
+ * - 0b1 - Program Flash only, device does not support FlexNVM
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_PFLSH field. */
+#define SIM_RD_FCFG2_PFLSH(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_PFLSH_MASK) >> SIM_FCFG2_PFLSH_SHIFT)
+#define SIM_BRD_FCFG2_PFLSH(base) (BITBAND_ACCESS32(&SIM_FCFG2_REG(base), SIM_FCFG2_PFLSH_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
+ *
+ * This field concatenated with 13 trailing zeros indicates the first invalid
+ * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
+ * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
+ * value for a device with 256 KB program flash in flash block 0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */
+#define SIM_RD_FCFG2_MAXADDR0(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR0_MASK) >> SIM_FCFG2_MAXADDR0_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR0(base) (SIM_RD_FCFG2_MAXADDR0(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDH - Unique Identification Register High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDH - Unique Identification Register High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDH register
+ */
+/*@{*/
+#define SIM_RD_UIDH(base)        (SIM_UIDH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDMH - Unique Identification Register Mid-High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDMH - Unique Identification Register Mid-High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDMH register
+ */
+/*@{*/
+#define SIM_RD_UIDMH(base)       (SIM_UIDMH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDML - Unique Identification Register Mid Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDML - Unique Identification Register Mid Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDML register
+ */
+/*@{*/
+#define SIM_RD_UIDML(base)       (SIM_UIDML_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDL - Unique Identification Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDL - Unique Identification Register Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDL register
+ */
+/*@{*/
+#define SIM_RD_UIDL(base)        (SIM_UIDL_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 SMC
+ *
+ * System Mode Controller
+ *
+ * Registers defined in this header file:
+ * - SMC_PMPROT - Power Mode Protection register
+ * - SMC_PMCTRL - Power Mode Control register
+ * - SMC_VLLSCTRL - VLLS Control register
+ * - SMC_PMSTAT - Power Mode Status register
+ */
+
+#define SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
+#define SMC_IDX (0U) /*!< Instance number for SMC. */
+
+/*******************************************************************************
+ * SMC_PMPROT - Power Mode Protection register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMPROT - Power Mode Protection register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides protection for entry into any low-power run or stop
+ * mode. The enabling of the low-power run or stop mode occurs by configuring the
+ * Power Mode Control register (PMCTRL). The PMPROT register can be written only
+ * once after any system reset. If the MCU is configured for a disallowed or
+ * reserved power mode, the MCU remains in its current power mode. For example, if the
+ * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
+ * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
+ * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
+ * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
+ * that do not trigger Chip Reset not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMPROT register
+ */
+/*@{*/
+#define SMC_RD_PMPROT(base)      (SMC_PMPROT_REG(base))
+#define SMC_WR_PMPROT(base, value) (SMC_PMPROT_REG(base) = (value))
+#define SMC_RMW_PMPROT(base, mask, value) (SMC_WR_PMPROT(base, (SMC_RD_PMPROT(base) & ~(mask)) | (value)))
+#define SMC_SET_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) |  (value)))
+#define SMC_CLR_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) & ~(value)))
+#define SMC_TOG_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMPROT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMPROT, field AVLLS[1] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write once
+ * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
+ *
+ * Values:
+ * - 0b0 - Any VLLSx mode is not allowed
+ * - 0b1 - Any VLLSx mode is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
+#define SMC_RD_PMPROT_AVLLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLLS_MASK) >> SMC_PMPROT_AVLLS_SHIFT)
+#define SMC_BRD_PMPROT_AVLLS(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT))
+
+/*! @brief Set the AVLLS field to a new value. */
+#define SMC_WR_PMPROT_AVLLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLLS_MASK, SMC_PMPROT_AVLLS(value)))
+#define SMC_BWR_PMPROT_AVLLS(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field ALLS[3] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any low-leakage stop mode (LLS).
+ *
+ * Values:
+ * - 0b0 - LLS is not allowed
+ * - 0b1 - LLS is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_ALLS field. */
+#define SMC_RD_PMPROT_ALLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_ALLS_MASK) >> SMC_PMPROT_ALLS_SHIFT)
+#define SMC_BRD_PMPROT_ALLS(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT))
+
+/*! @brief Set the ALLS field to a new value. */
+#define SMC_WR_PMPROT_ALLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_ALLS_MASK, SMC_PMPROT_ALLS(value)))
+#define SMC_BWR_PMPROT_ALLS(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field AVLP[5] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
+ *
+ * Values:
+ * - 0b0 - VLPR, VLPW, and VLPS are not allowed.
+ * - 0b1 - VLPR, VLPW, and VLPS are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLP field. */
+#define SMC_RD_PMPROT_AVLP(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLP_MASK) >> SMC_PMPROT_AVLP_SHIFT)
+#define SMC_BRD_PMPROT_AVLP(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT))
+
+/*! @brief Set the AVLP field to a new value. */
+#define SMC_WR_PMPROT_AVLP(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLP_MASK, SMC_PMPROT_AVLP(value)))
+#define SMC_BWR_PMPROT_AVLP(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMCTRL - Power Mode Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMCTRL - Power Mode Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The PMCTRL register controls entry into low-power Run and Stop modes,
+ * provided that the selected power mode is allowed via an appropriate setting of the
+ * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
+ * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
+ * that do not trigger Chip POR not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMCTRL register
+ */
+/*@{*/
+#define SMC_RD_PMCTRL(base)      (SMC_PMCTRL_REG(base))
+#define SMC_WR_PMCTRL(base, value) (SMC_PMCTRL_REG(base) = (value))
+#define SMC_RMW_PMCTRL(base, mask, value) (SMC_WR_PMCTRL(base, (SMC_RD_PMCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) |  (value)))
+#define SMC_CLR_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) & ~(value)))
+#define SMC_TOG_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
+ *
+ * When written, controls entry into the selected stop mode when Sleep-Now or
+ * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
+ * blocked if the protection level has not been enabled using the PMPROT register.
+ * After any system reset, this field is cleared by hardware on any successful write
+ * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
+ * register is used to further select the particular VLLS submode which will be
+ * entered.
+ *
+ * Values:
+ * - 0b000 - Normal Stop (STOP)
+ * - 0b001 - Reserved
+ * - 0b010 - Very-Low-Power Stop (VLPS)
+ * - 0b011 - Low-Leakage Stop (LLS)
+ * - 0b100 - Very-Low-Leakage Stop (VLLSx)
+ * - 0b101 - Reserved
+ * - 0b110 - Reseved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
+#define SMC_RD_PMCTRL_STOPM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPM_MASK) >> SMC_PMCTRL_STOPM_SHIFT)
+#define SMC_BRD_PMCTRL_STOPM(base) (SMC_RD_PMCTRL_STOPM(base))
+
+/*! @brief Set the STOPM field to a new value. */
+#define SMC_WR_PMCTRL_STOPM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_STOPM_MASK, SMC_PMCTRL_STOPM(value)))
+#define SMC_BWR_PMCTRL_STOPM(base, value) (SMC_WR_PMCTRL_STOPM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPA[3] (RO)
+ *
+ * When set, this read-only status bit indicates an interrupt or reset occured
+ * during the previous stop mode entry sequence, preventing the system from
+ * entering that mode. This field is cleared by hardware at the beginning of any stop
+ * mode entry sequence and is set if the sequence was aborted.
+ *
+ * Values:
+ * - 0b0 - The previous stop mode entry was successsful.
+ * - 0b1 - The previous stop mode entry was aborted.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
+#define SMC_RD_PMCTRL_STOPA(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPA_MASK) >> SMC_PMCTRL_STOPA_SHIFT)
+#define SMC_BRD_PMCTRL_STOPA(base) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_STOPA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
+ *
+ * When written, causes entry into the selected run mode. Writes to this field
+ * are blocked if the protection level has not been enabled using the PMPROT
+ * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
+ * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
+ *
+ * Values:
+ * - 0b00 - Normal Run mode (RUN)
+ * - 0b01 - Reserved
+ * - 0b10 - Very-Low-Power Run mode (VLPR)
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
+#define SMC_RD_PMCTRL_RUNM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_RUNM_MASK) >> SMC_PMCTRL_RUNM_SHIFT)
+#define SMC_BRD_PMCTRL_RUNM(base) (SMC_RD_PMCTRL_RUNM(base))
+
+/*! @brief Set the RUNM field to a new value. */
+#define SMC_WR_PMCTRL_RUNM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_RUNM_MASK, SMC_PMCTRL_RUNM(value)))
+#define SMC_BWR_PMCTRL_RUNM(base, value) (SMC_WR_PMCTRL_RUNM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
+ *
+ * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
+ * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
+ * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
+ * the LPWUI setting. LPWUI must be modified only while the system is in RUN
+ * mode, that is, when PMSTAT=RUN.
+ *
+ * Values:
+ * - 0b0 - The system remains in a VLP mode on an interrupt
+ * - 0b1 - The system exits to Normal RUN mode on an interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_LPWUI field. */
+#define SMC_RD_PMCTRL_LPWUI(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_LPWUI_MASK) >> SMC_PMCTRL_LPWUI_SHIFT)
+#define SMC_BRD_PMCTRL_LPWUI(base) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_LPWUI_SHIFT))
+
+/*! @brief Set the LPWUI field to a new value. */
+#define SMC_WR_PMCTRL_LPWUI(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_LPWUI_MASK, SMC_PMCTRL_LPWUI(value)))
+#define SMC_BWR_PMCTRL_LPWUI(base, value) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_LPWUI_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_VLLSCTRL - VLLS Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_VLLSCTRL - VLLS Control register (RW)
+ *
+ * Reset value: 0x03U
+ *
+ * The VLLSCTRL register controls features related to VLLS modes. This register
+ * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
+ * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
+ * the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_VLLSCTRL register
+ */
+/*@{*/
+#define SMC_RD_VLLSCTRL(base)    (SMC_VLLSCTRL_REG(base))
+#define SMC_WR_VLLSCTRL(base, value) (SMC_VLLSCTRL_REG(base) = (value))
+#define SMC_RMW_VLLSCTRL(base, mask, value) (SMC_WR_VLLSCTRL(base, (SMC_RD_VLLSCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) |  (value)))
+#define SMC_CLR_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) & ~(value)))
+#define SMC_TOG_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_VLLSCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
+ *
+ * Controls which VLLS sub-mode to enter if STOPM=VLLS.
+ *
+ * Values:
+ * - 0b000 - VLLS0
+ * - 0b001 - VLLS1
+ * - 0b010 - VLLS2
+ * - 0b011 - VLLS3
+ * - 0b100 - Reserved
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_VLLSCTRL_VLLSM field. */
+#define SMC_RD_VLLSCTRL_VLLSM(base) ((SMC_VLLSCTRL_REG(base) & SMC_VLLSCTRL_VLLSM_MASK) >> SMC_VLLSCTRL_VLLSM_SHIFT)
+#define SMC_BRD_VLLSCTRL_VLLSM(base) (SMC_RD_VLLSCTRL_VLLSM(base))
+
+/*! @brief Set the VLLSM field to a new value. */
+#define SMC_WR_VLLSCTRL_VLLSM(base, value) (SMC_RMW_VLLSCTRL(base, SMC_VLLSCTRL_VLLSM_MASK, SMC_VLLSCTRL_VLLSM(value)))
+#define SMC_BWR_VLLSCTRL_VLLSM(base, value) (SMC_WR_VLLSCTRL_VLLSM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
+ *
+ * Controls whether the POR detect circuit (for brown-out detection) is enabled
+ * in VLLS0 mode.
+ *
+ * Values:
+ * - 0b0 - POR detect circuit is enabled in VLLS0.
+ * - 0b1 - POR detect circuit is disabled in VLLS0.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_VLLSCTRL_PORPO field. */
+#define SMC_RD_VLLSCTRL_PORPO(base) ((SMC_VLLSCTRL_REG(base) & SMC_VLLSCTRL_PORPO_MASK) >> SMC_VLLSCTRL_PORPO_SHIFT)
+#define SMC_BRD_VLLSCTRL_PORPO(base) (BITBAND_ACCESS8(&SMC_VLLSCTRL_REG(base), SMC_VLLSCTRL_PORPO_SHIFT))
+
+/*! @brief Set the PORPO field to a new value. */
+#define SMC_WR_VLLSCTRL_PORPO(base, value) (SMC_RMW_VLLSCTRL(base, SMC_VLLSCTRL_PORPO_MASK, SMC_VLLSCTRL_PORPO(value)))
+#define SMC_BWR_VLLSCTRL_PORPO(base, value) (BITBAND_ACCESS8(&SMC_VLLSCTRL_REG(base), SMC_VLLSCTRL_PORPO_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMSTAT - Power Mode Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMSTAT - Power Mode Status register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * PMSTAT is a read-only, one-hot register which indicates the current power
+ * mode of the system. This register is reset on Chip POR not VLLS and by reset
+ * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
+ * trigger Chip POR not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMSTAT register
+ */
+/*@{*/
+#define SMC_RD_PMSTAT(base)      (SMC_PMSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMSTAT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
+ *
+ * When debug is enabled, the PMSTAT will not update to STOP or VLPS
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */
+#define SMC_RD_PMSTAT_PMSTAT(base) ((SMC_PMSTAT_REG(base) & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT)
+#define SMC_BRD_PMSTAT_PMSTAT(base) (SMC_RD_PMSTAT_PMSTAT(base))
+/*@}*/
+
+/*
+ * MK64F12 SPI
+ *
+ * Serial Peripheral Interface
+ *
+ * Registers defined in this header file:
+ * - SPI_MCR - Module Configuration Register
+ * - SPI_TCR - Transfer Count Register
+ * - SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
+ * - SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ * - SPI_SR - Status Register
+ * - SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ * - SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ * - SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ * - SPI_POPR - POP RX FIFO Register
+ * - SPI_TXFR0 - Transmit FIFO Registers
+ * - SPI_TXFR1 - Transmit FIFO Registers
+ * - SPI_TXFR2 - Transmit FIFO Registers
+ * - SPI_TXFR3 - Transmit FIFO Registers
+ * - SPI_RXFR0 - Receive FIFO Registers
+ * - SPI_RXFR1 - Receive FIFO Registers
+ * - SPI_RXFR2 - Receive FIFO Registers
+ * - SPI_RXFR3 - Receive FIFO Registers
+ */
+
+#define SPI_INSTANCE_COUNT (3U) /*!< Number of instances of the SPI module. */
+#define SPI0_IDX (0U) /*!< Instance number for SPI0. */
+#define SPI1_IDX (1U) /*!< Instance number for SPI1. */
+#define SPI2_IDX (2U) /*!< Instance number for SPI2. */
+
+/*******************************************************************************
+ * SPI_MCR - Module Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0x00004001U
+ *
+ * Contains bits to configure various attributes associated with the module
+ * operations. The HALT and MDIS bits can be changed at any time, but the effect
+ * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
+ * MCR can be changed, while the module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_MCR register
+ */
+/*@{*/
+#define SPI_RD_MCR(base)         (SPI_MCR_REG(base))
+#define SPI_WR_MCR(base, value)  (SPI_MCR_REG(base) = (value))
+#define SPI_RMW_MCR(base, mask, value) (SPI_WR_MCR(base, (SPI_RD_MCR(base) & ~(mask)) | (value)))
+#define SPI_SET_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) |  (value)))
+#define SPI_CLR_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) & ~(value)))
+#define SPI_TOG_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_MCR bitfields
+ */
+
+/*!
+ * @name Register SPI_MCR, field HALT[0] (RW)
+ *
+ * The HALT bit starts and stops frame transfers. See Start and Stop of Module
+ * transfers
+ *
+ * Values:
+ * - 0b0 - Start transfers.
+ * - 0b1 - Stop transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_HALT field. */
+#define SPI_RD_MCR_HALT(base) ((SPI_MCR_REG(base) & SPI_MCR_HALT_MASK) >> SPI_MCR_HALT_SHIFT)
+#define SPI_BRD_MCR_HALT(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define SPI_WR_MCR_HALT(base, value) (SPI_RMW_MCR(base, SPI_MCR_HALT_MASK, SPI_MCR_HALT(value)))
+#define SPI_BWR_MCR_HALT(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
+ *
+ * Controls when the module master samples SIN in Modified Transfer Format. This
+ * field is valid only when CPHA bit in CTARn[CPHA] is 0.
+ *
+ * Values:
+ * - 0b00 - 0 protocol clock cycles between SCK edge and SIN sample
+ * - 0b01 - 1 protocol clock cycle between SCK edge and SIN sample
+ * - 0b10 - 2 protocol clock cycles between SCK edge and SIN sample
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_SMPL_PT field. */
+#define SPI_RD_MCR_SMPL_PT(base) ((SPI_MCR_REG(base) & SPI_MCR_SMPL_PT_MASK) >> SPI_MCR_SMPL_PT_SHIFT)
+#define SPI_BRD_MCR_SMPL_PT(base) (SPI_RD_MCR_SMPL_PT(base))
+
+/*! @brief Set the SMPL_PT field to a new value. */
+#define SPI_WR_MCR_SMPL_PT(base, value) (SPI_RMW_MCR(base, SPI_MCR_SMPL_PT_MASK, SPI_MCR_SMPL_PT(value)))
+#define SPI_BWR_MCR_SMPL_PT(base, value) (SPI_WR_MCR_SMPL_PT(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
+ *
+ * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
+ * CLR_RXF bit is always read as zero.
+ *
+ * Values:
+ * - 0b0 - Do not clear the RX FIFO counter.
+ * - 0b1 - Clear the RX FIFO counter.
+ */
+/*@{*/
+/*! @brief Set the CLR_RXF field to a new value. */
+#define SPI_WR_MCR_CLR_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_RXF_MASK, SPI_MCR_CLR_RXF(value)))
+#define SPI_BWR_MCR_CLR_RXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CLR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
+ *
+ * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
+ * CLR_TXF bit is always read as zero.
+ *
+ * Values:
+ * - 0b0 - Do not clear the TX FIFO counter.
+ * - 0b1 - Clear the TX FIFO counter.
+ */
+/*@{*/
+/*! @brief Set the CLR_TXF field to a new value. */
+#define SPI_WR_MCR_CLR_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_TXF_MASK, SPI_MCR_CLR_TXF(value)))
+#define SPI_BWR_MCR_CLR_TXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CLR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DIS_RXF[12] (RW)
+ *
+ * When the RX FIFO is disabled, the receive part of the module operates as a
+ * simplified double-buffered SPI. This bit can only be written when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0b0 - RX FIFO is enabled.
+ * - 0b1 - RX FIFO is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DIS_RXF field. */
+#define SPI_RD_MCR_DIS_RXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_RXF_MASK) >> SPI_MCR_DIS_RXF_SHIFT)
+#define SPI_BRD_MCR_DIS_RXF(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT))
+
+/*! @brief Set the DIS_RXF field to a new value. */
+#define SPI_WR_MCR_DIS_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_RXF_MASK, SPI_MCR_DIS_RXF(value)))
+#define SPI_BWR_MCR_DIS_RXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DIS_TXF[13] (RW)
+ *
+ * When the TX FIFO is disabled, the transmit part of the module operates as a
+ * simplified double-buffered SPI. This bit can be written only when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0b0 - TX FIFO is enabled.
+ * - 0b1 - TX FIFO is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DIS_TXF field. */
+#define SPI_RD_MCR_DIS_TXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_TXF_MASK) >> SPI_MCR_DIS_TXF_SHIFT)
+#define SPI_BRD_MCR_DIS_TXF(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT))
+
+/*! @brief Set the DIS_TXF field to a new value. */
+#define SPI_WR_MCR_DIS_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_TXF_MASK, SPI_MCR_DIS_TXF(value)))
+#define SPI_BWR_MCR_DIS_TXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MDIS[14] (RW)
+ *
+ * Allows the clock to be stopped to the non-memory mapped logic in the module
+ * effectively putting it in a software-controlled power-saving state. The reset
+ * value of the MDIS bit is parameterized, with a default reset value of 0. When
+ * the module is used in Slave Mode, we recommend leaving this bit 0, because a
+ * slave doesn't have control over master transactions.
+ *
+ * Values:
+ * - 0b0 - Enables the module clocks.
+ * - 0b1 - Allows external logic to disable the module clocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MDIS field. */
+#define SPI_RD_MCR_MDIS(base) ((SPI_MCR_REG(base) & SPI_MCR_MDIS_MASK) >> SPI_MCR_MDIS_SHIFT)
+#define SPI_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define SPI_WR_MCR_MDIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_MDIS_MASK, SPI_MCR_MDIS(value)))
+#define SPI_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DOZE[15] (RW)
+ *
+ * Provides support for an externally controlled Doze mode power-saving
+ * mechanism.
+ *
+ * Values:
+ * - 0b0 - Doze mode has no effect on the module.
+ * - 0b1 - Doze mode disables the module.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DOZE field. */
+#define SPI_RD_MCR_DOZE(base) ((SPI_MCR_REG(base) & SPI_MCR_DOZE_MASK) >> SPI_MCR_DOZE_SHIFT)
+#define SPI_BRD_MCR_DOZE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT))
+
+/*! @brief Set the DOZE field to a new value. */
+#define SPI_WR_MCR_DOZE(base, value) (SPI_RMW_MCR(base, SPI_MCR_DOZE_MASK, SPI_MCR_DOZE(value)))
+#define SPI_BWR_MCR_DOZE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field PCSIS[21:16] (RW)
+ *
+ * Determines the inactive state of PCSx.
+ *
+ * Values:
+ * - 0b000000 - The inactive state of PCSx is low.
+ * - 0b000001 - The inactive state of PCSx is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_PCSIS field. */
+#define SPI_RD_MCR_PCSIS(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSIS_MASK) >> SPI_MCR_PCSIS_SHIFT)
+#define SPI_BRD_MCR_PCSIS(base) (SPI_RD_MCR_PCSIS(base))
+
+/*! @brief Set the PCSIS field to a new value. */
+#define SPI_WR_MCR_PCSIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSIS_MASK, SPI_MCR_PCSIS(value)))
+#define SPI_BWR_MCR_PCSIS(base, value) (SPI_WR_MCR_PCSIS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field ROOE[24] (RW)
+ *
+ * In the RX FIFO overflow condition, configures the module to ignore the
+ * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
+ * is received, the data from the transfer, generating the overflow, is ignored
+ * or shifted into the shift register.
+ *
+ * Values:
+ * - 0b0 - Incoming data is ignored.
+ * - 0b1 - Incoming data is shifted into the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_ROOE field. */
+#define SPI_RD_MCR_ROOE(base) ((SPI_MCR_REG(base) & SPI_MCR_ROOE_MASK) >> SPI_MCR_ROOE_SHIFT)
+#define SPI_BRD_MCR_ROOE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT))
+
+/*! @brief Set the ROOE field to a new value. */
+#define SPI_WR_MCR_ROOE(base, value) (SPI_RMW_MCR(base, SPI_MCR_ROOE_MASK, SPI_MCR_ROOE(value)))
+#define SPI_BWR_MCR_ROOE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field PCSSE[25] (RW)
+ *
+ * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
+ *
+ * Values:
+ * - 0b0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
+ * - 0b1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_PCSSE field. */
+#define SPI_RD_MCR_PCSSE(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSSE_MASK) >> SPI_MCR_PCSSE_SHIFT)
+#define SPI_BRD_MCR_PCSSE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_PCSSE_SHIFT))
+
+/*! @brief Set the PCSSE field to a new value. */
+#define SPI_WR_MCR_PCSSE(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSSE_MASK, SPI_MCR_PCSSE(value)))
+#define SPI_BWR_MCR_PCSSE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_PCSSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MTFE[26] (RW)
+ *
+ * Enables a modified transfer format to be used.
+ *
+ * Values:
+ * - 0b0 - Modified SPI transfer format disabled.
+ * - 0b1 - Modified SPI transfer format enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MTFE field. */
+#define SPI_RD_MCR_MTFE(base) ((SPI_MCR_REG(base) & SPI_MCR_MTFE_MASK) >> SPI_MCR_MTFE_SHIFT)
+#define SPI_BRD_MCR_MTFE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT))
+
+/*! @brief Set the MTFE field to a new value. */
+#define SPI_WR_MCR_MTFE(base, value) (SPI_RMW_MCR(base, SPI_MCR_MTFE_MASK, SPI_MCR_MTFE(value)))
+#define SPI_BWR_MCR_MTFE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field FRZ[27] (RW)
+ *
+ * Enables transfers to be stopped on the next frame boundary when the device
+ * enters Debug mode.
+ *
+ * Values:
+ * - 0b0 - Do not halt serial transfers in Debug mode.
+ * - 0b1 - Halt serial transfers in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_FRZ field. */
+#define SPI_RD_MCR_FRZ(base) ((SPI_MCR_REG(base) & SPI_MCR_FRZ_MASK) >> SPI_MCR_FRZ_SHIFT)
+#define SPI_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define SPI_WR_MCR_FRZ(base, value) (SPI_RMW_MCR(base, SPI_MCR_FRZ_MASK, SPI_MCR_FRZ(value)))
+#define SPI_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DCONF[29:28] (RO)
+ *
+ * Selects among the different configurations of the module.
+ *
+ * Values:
+ * - 0b00 - SPI
+ * - 0b01 - Reserved
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DCONF field. */
+#define SPI_RD_MCR_DCONF(base) ((SPI_MCR_REG(base) & SPI_MCR_DCONF_MASK) >> SPI_MCR_DCONF_SHIFT)
+#define SPI_BRD_MCR_DCONF(base) (SPI_RD_MCR_DCONF(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
+ *
+ * Enables the Serial Communication Clock (SCK) to run continuously.
+ *
+ * Values:
+ * - 0b0 - Continuous SCK disabled.
+ * - 0b1 - Continuous SCK enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */
+#define SPI_RD_MCR_CONT_SCKE(base) ((SPI_MCR_REG(base) & SPI_MCR_CONT_SCKE_MASK) >> SPI_MCR_CONT_SCKE_SHIFT)
+#define SPI_BRD_MCR_CONT_SCKE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT))
+
+/*! @brief Set the CONT_SCKE field to a new value. */
+#define SPI_WR_MCR_CONT_SCKE(base, value) (SPI_RMW_MCR(base, SPI_MCR_CONT_SCKE_MASK, SPI_MCR_CONT_SCKE(value)))
+#define SPI_BWR_MCR_CONT_SCKE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MSTR[31] (RW)
+ *
+ * Enables either Master mode (if supported) or Slave mode (if supported)
+ * operation.
+ *
+ * Values:
+ * - 0b0 - Enables Slave mode
+ * - 0b1 - Enables Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MSTR field. */
+#define SPI_RD_MCR_MSTR(base) ((SPI_MCR_REG(base) & SPI_MCR_MSTR_MASK) >> SPI_MCR_MSTR_SHIFT)
+#define SPI_BRD_MCR_MSTR(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT))
+
+/*! @brief Set the MSTR field to a new value. */
+#define SPI_WR_MCR_MSTR(base, value) (SPI_RMW_MCR(base, SPI_MCR_MSTR_MASK, SPI_MCR_MSTR(value)))
+#define SPI_BWR_MCR_MSTR(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TCR - Transfer Count Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TCR - Transfer Count Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR contains a counter that indicates the number of SPI transfers made. The
+ * transfer counter is intended to assist in queue management. Do not write the
+ * TCR when the module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TCR register
+ */
+/*@{*/
+#define SPI_RD_TCR(base)         (SPI_TCR_REG(base))
+#define SPI_WR_TCR(base, value)  (SPI_TCR_REG(base) = (value))
+#define SPI_RMW_TCR(base, mask, value) (SPI_WR_TCR(base, (SPI_RD_TCR(base) & ~(mask)) | (value)))
+#define SPI_SET_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) |  (value)))
+#define SPI_CLR_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) & ~(value)))
+#define SPI_TOG_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TCR bitfields
+ */
+
+/*!
+ * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
+ *
+ * Counts the number of SPI transfers the module makes. The SPI_TCNT field
+ * increments every time the last bit of an SPI frame is transmitted. A value written
+ * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
+ * the beginning of the frame when the CTCNT field is set in the executing SPI
+ * command. The Transfer Counter wraps around; incrementing the counter past 65535
+ * resets the counter to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */
+#define SPI_RD_TCR_SPI_TCNT(base) ((SPI_TCR_REG(base) & SPI_TCR_SPI_TCNT_MASK) >> SPI_TCR_SPI_TCNT_SHIFT)
+#define SPI_BRD_TCR_SPI_TCNT(base) (SPI_RD_TCR_SPI_TCNT(base))
+
+/*! @brief Set the SPI_TCNT field to a new value. */
+#define SPI_WR_TCR_SPI_TCNT(base, value) (SPI_RMW_TCR(base, SPI_TCR_SPI_TCNT_MASK, SPI_TCR_SPI_TCNT(value)))
+#define SPI_BWR_TCR_SPI_TCNT(base, value) (SPI_WR_TCR_SPI_TCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * When the module is configured as an SPI bus slave, the CTAR0 register is used.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CTAR_SLAVE register
+ */
+/*@{*/
+#define SPI_RD_CTAR_SLAVE(base, index) (SPI_CTAR_SLAVE_REG(base, index))
+#define SPI_WR_CTAR_SLAVE(base, index, value) (SPI_CTAR_SLAVE_REG(base, index) = (value))
+#define SPI_RMW_CTAR_SLAVE(base, index, mask, value) (SPI_WR_CTAR_SLAVE(base, index, (SPI_RD_CTAR_SLAVE(base, index) & ~(mask)) | (value)))
+#define SPI_SET_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) |  (value)))
+#define SPI_CLR_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) & ~(value)))
+#define SPI_TOG_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CTAR_SLAVE bitfields
+ */
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0b0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 0b1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_CPHA field. */
+#define SPI_RD_CTAR_SLAVE_CPHA(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPHA_MASK) >> SPI_CTAR_SLAVE_CPHA_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_CPHA(base, index) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_CTAR_SLAVE_CPHA(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPHA_MASK, SPI_CTAR_SLAVE_CPHA(value)))
+#define SPI_BWR_CTAR_SLAVE_CPHA(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0b0 - The inactive state value of SCK is low.
+ * - 0b1 - The inactive state value of SCK is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_CPOL field. */
+#define SPI_RD_CTAR_SLAVE_CPOL(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPOL_MASK) >> SPI_CTAR_SLAVE_CPOL_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_CPOL(base, index) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_CTAR_SLAVE_CPOL(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPOL_MASK, SPI_CTAR_SLAVE_CPOL(value)))
+#define SPI_BWR_CTAR_SLAVE_CPOL(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field FMSZ[31:27] (RW)
+ *
+ * The number of bits transfered per frame is equal to the FMSZ field value plus
+ * 1. Note that the minimum valid value of frame size is 4.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_FMSZ field. */
+#define SPI_RD_CTAR_SLAVE_FMSZ(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_FMSZ(base, index) (SPI_RD_CTAR_SLAVE_FMSZ(base, index))
+
+/*! @brief Set the FMSZ field to a new value. */
+#define SPI_WR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_FMSZ_MASK, SPI_CTAR_SLAVE_FMSZ(value)))
+#define SPI_BWR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_WR_CTAR_SLAVE_FMSZ(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * CTAR registers are used to define different transfer attributes. Do not write
+ * to the CTAR registers while the module is in the Running state. In Master
+ * mode, the CTAR registers define combinations of transfer attributes such as frame
+ * size, clock phase and polarity, data bit ordering, baud rate, and various
+ * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
+ * slave transfer attributes. When the module is configured as an SPI master, the
+ * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
+ * registers is used. When the module is configured as an SPI bus slave, it uses
+ * the CTAR0 register.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CTAR register
+ */
+/*@{*/
+#define SPI_RD_CTAR(base, index) (SPI_CTAR_REG(base, index))
+#define SPI_WR_CTAR(base, index, value) (SPI_CTAR_REG(base, index) = (value))
+#define SPI_RMW_CTAR(base, index, mask, value) (SPI_WR_CTAR(base, index, (SPI_RD_CTAR(base, index) & ~(mask)) | (value)))
+#define SPI_SET_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) |  (value)))
+#define SPI_CLR_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) & ~(value)))
+#define SPI_TOG_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CTAR bitfields
+ */
+
+/*!
+ * @name Register SPI_CTAR, field BR[3:0] (RW)
+ *
+ * Selects the scaler value for the baud rate. This field is used only in master
+ * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
+ * generate the frequency of the SCK. The baud rate is computed according to the
+ * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
+ * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
+ * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
+ * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_BR field. */
+#define SPI_RD_CTAR_BR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_BR_MASK) >> SPI_CTAR_BR_SHIFT)
+#define SPI_BRD_CTAR_BR(base, index) (SPI_RD_CTAR_BR(base, index))
+
+/*! @brief Set the BR field to a new value. */
+#define SPI_WR_CTAR_BR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_BR_MASK, SPI_CTAR_BR(value)))
+#define SPI_BWR_CTAR_BR(base, index, value) (SPI_WR_CTAR_BR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field DT[7:4] (RW)
+ *
+ * Selects the Delay after Transfer Scaler. This field is used only in master
+ * mode. The Delay after Transfer is the time between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the next
+ * frame. In the Continuous Serial Communications Clock operation, the DT value
+ * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
+ * protocol clock period, and it is computed according to the following
+ * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
+ * field description for scaler values.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_DT field. */
+#define SPI_RD_CTAR_DT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DT_MASK) >> SPI_CTAR_DT_SHIFT)
+#define SPI_BRD_CTAR_DT(base, index) (SPI_RD_CTAR_DT(base, index))
+
+/*! @brief Set the DT field to a new value. */
+#define SPI_WR_CTAR_DT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DT_MASK, SPI_CTAR_DT(value)))
+#define SPI_BWR_CTAR_DT(base, index, value) (SPI_WR_CTAR_DT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field ASC[11:8] (RW)
+ *
+ * Selects the scaler value for the After SCK Delay. This field is used only in
+ * master mode. The After SCK Delay is the delay between the last edge of SCK and
+ * the negation of PCS. The delay is a multiple of the protocol clock period,
+ * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
+ * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
+ * scaler values. Refer After SCK Delay (tASC ) for more details.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_ASC field. */
+#define SPI_RD_CTAR_ASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_ASC_MASK) >> SPI_CTAR_ASC_SHIFT)
+#define SPI_BRD_CTAR_ASC(base, index) (SPI_RD_CTAR_ASC(base, index))
+
+/*! @brief Set the ASC field to a new value. */
+#define SPI_WR_CTAR_ASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_ASC_MASK, SPI_CTAR_ASC(value)))
+#define SPI_BWR_CTAR_ASC(base, index, value) (SPI_WR_CTAR_ASC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CSSCK[15:12] (RW)
+ *
+ * Selects the scaler value for the PCS to SCK delay. This field is used only in
+ * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
+ * and the first edge of the SCK. The delay is a multiple of the protocol clock
+ * period, and it is computed according to the following equation: t CSC = (1/fP )
+ * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
+ * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
+ * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
+ * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
+ * details.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CSSCK field. */
+#define SPI_RD_CTAR_CSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CSSCK_MASK) >> SPI_CTAR_CSSCK_SHIFT)
+#define SPI_BRD_CTAR_CSSCK(base, index) (SPI_RD_CTAR_CSSCK(base, index))
+
+/*! @brief Set the CSSCK field to a new value. */
+#define SPI_WR_CTAR_CSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CSSCK_MASK, SPI_CTAR_CSSCK(value)))
+#define SPI_BWR_CTAR_CSSCK(base, index, value) (SPI_WR_CTAR_CSSCK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PBR[17:16] (RW)
+ *
+ * Selects the prescaler value for the baud rate. This field is used only in
+ * master mode. The baud rate is the frequency of the SCK. The protocol clock is
+ * divided by the prescaler value before the baud rate selection takes place. See
+ * the BR field description for details on how to compute the baud rate.
+ *
+ * Values:
+ * - 0b00 - Baud Rate Prescaler value is 2.
+ * - 0b01 - Baud Rate Prescaler value is 3.
+ * - 0b10 - Baud Rate Prescaler value is 5.
+ * - 0b11 - Baud Rate Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PBR field. */
+#define SPI_RD_CTAR_PBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PBR_MASK) >> SPI_CTAR_PBR_SHIFT)
+#define SPI_BRD_CTAR_PBR(base, index) (SPI_RD_CTAR_PBR(base, index))
+
+/*! @brief Set the PBR field to a new value. */
+#define SPI_WR_CTAR_PBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PBR_MASK, SPI_CTAR_PBR(value)))
+#define SPI_BWR_CTAR_PBR(base, index, value) (SPI_WR_CTAR_PBR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PDT[19:18] (RW)
+ *
+ * Selects the prescaler value for the delay between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the
+ * next frame. The PDT field is only used in master mode. See the DT field
+ * description for details on how to compute the Delay after Transfer. Refer Delay after
+ * Transfer (tDT ) for more details.
+ *
+ * Values:
+ * - 0b00 - Delay after Transfer Prescaler value is 1.
+ * - 0b01 - Delay after Transfer Prescaler value is 3.
+ * - 0b10 - Delay after Transfer Prescaler value is 5.
+ * - 0b11 - Delay after Transfer Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PDT field. */
+#define SPI_RD_CTAR_PDT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PDT_MASK) >> SPI_CTAR_PDT_SHIFT)
+#define SPI_BRD_CTAR_PDT(base, index) (SPI_RD_CTAR_PDT(base, index))
+
+/*! @brief Set the PDT field to a new value. */
+#define SPI_WR_CTAR_PDT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PDT_MASK, SPI_CTAR_PDT(value)))
+#define SPI_BWR_CTAR_PDT(base, index, value) (SPI_WR_CTAR_PDT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PASC[21:20] (RW)
+ *
+ * Selects the prescaler value for the delay between the last edge of SCK and
+ * the negation of PCS. See the ASC field description for information on how to
+ * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
+ *
+ * Values:
+ * - 0b00 - Delay after Transfer Prescaler value is 1.
+ * - 0b01 - Delay after Transfer Prescaler value is 3.
+ * - 0b10 - Delay after Transfer Prescaler value is 5.
+ * - 0b11 - Delay after Transfer Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PASC field. */
+#define SPI_RD_CTAR_PASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PASC_MASK) >> SPI_CTAR_PASC_SHIFT)
+#define SPI_BRD_CTAR_PASC(base, index) (SPI_RD_CTAR_PASC(base, index))
+
+/*! @brief Set the PASC field to a new value. */
+#define SPI_WR_CTAR_PASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PASC_MASK, SPI_CTAR_PASC(value)))
+#define SPI_BWR_CTAR_PASC(base, index, value) (SPI_WR_CTAR_PASC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PCSSCK[23:22] (RW)
+ *
+ * Selects the prescaler value for the delay between assertion of PCS and the
+ * first edge of the SCK. See the CSSCK field description for information on how to
+ * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
+ *
+ * Values:
+ * - 0b00 - PCS to SCK Prescaler value is 1.
+ * - 0b01 - PCS to SCK Prescaler value is 3.
+ * - 0b10 - PCS to SCK Prescaler value is 5.
+ * - 0b11 - PCS to SCK Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PCSSCK field. */
+#define SPI_RD_CTAR_PCSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PCSSCK_MASK) >> SPI_CTAR_PCSSCK_SHIFT)
+#define SPI_BRD_CTAR_PCSSCK(base, index) (SPI_RD_CTAR_PCSSCK(base, index))
+
+/*! @brief Set the PCSSCK field to a new value. */
+#define SPI_WR_CTAR_PCSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PCSSCK_MASK, SPI_CTAR_PCSSCK(value)))
+#define SPI_BWR_CTAR_PCSSCK(base, index, value) (SPI_WR_CTAR_PCSSCK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field LSBFE[24] (RW)
+ *
+ * Specifies whether the LSB or MSB of the frame is transferred first.
+ *
+ * Values:
+ * - 0b0 - Data is transferred MSB first.
+ * - 0b1 - Data is transferred LSB first.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_LSBFE field. */
+#define SPI_RD_CTAR_LSBFE(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_LSBFE_MASK) >> SPI_CTAR_LSBFE_SHIFT)
+#define SPI_BRD_CTAR_LSBFE(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT))
+
+/*! @brief Set the LSBFE field to a new value. */
+#define SPI_WR_CTAR_LSBFE(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_LSBFE_MASK, SPI_CTAR_LSBFE(value)))
+#define SPI_BWR_CTAR_LSBFE(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0b0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 0b1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CPHA field. */
+#define SPI_RD_CTAR_CPHA(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPHA_MASK) >> SPI_CTAR_CPHA_SHIFT)
+#define SPI_BRD_CTAR_CPHA(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_CTAR_CPHA(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPHA_MASK, SPI_CTAR_CPHA(value)))
+#define SPI_BWR_CTAR_CPHA(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). This bit
+ * is used in both master and slave mode. For successful communication between
+ * serial devices, the devices must have identical clock polarities. When the
+ * Continuous Selection Format is selected, switching between clock polarities
+ * without stopping the module can cause errors in the transfer due to the peripheral
+ * device interpreting the switch of clock polarity as a valid clock edge. In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0b0 - The inactive state value of SCK is low.
+ * - 0b1 - The inactive state value of SCK is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CPOL field. */
+#define SPI_RD_CTAR_CPOL(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPOL_MASK) >> SPI_CTAR_CPOL_SHIFT)
+#define SPI_BRD_CTAR_CPOL(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_CTAR_CPOL(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPOL_MASK, SPI_CTAR_CPOL(value)))
+#define SPI_BWR_CTAR_CPOL(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field FMSZ[30:27] (RW)
+ *
+ * The number of bits transferred per frame is equal to the FMSZ value plus 1.
+ * Regardless of the transmission mode, the minimum valid frame size value is 4.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_FMSZ field. */
+#define SPI_RD_CTAR_FMSZ(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT)
+#define SPI_BRD_CTAR_FMSZ(base, index) (SPI_RD_CTAR_FMSZ(base, index))
+
+/*! @brief Set the FMSZ field to a new value. */
+#define SPI_WR_CTAR_FMSZ(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_FMSZ_MASK, SPI_CTAR_FMSZ(value)))
+#define SPI_BWR_CTAR_FMSZ(base, index, value) (SPI_WR_CTAR_FMSZ(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field DBR[31] (RW)
+ *
+ * Doubles the effective baud rate of the Serial Communications Clock (SCK).
+ * This field is used only in master mode. It effectively halves the Baud Rate
+ * division ratio, supporting faster frequencies, and odd division ratios for the
+ * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
+ * Serial Communications Clock (SCK) depends on the value in the Baud Rate
+ * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
+ * description for details on how to compute the baud rate. SPI SCK Duty Cycle
+ * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
+ * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
+ *
+ * Values:
+ * - 0b0 - The baud rate is computed normally with a 50/50 duty cycle.
+ * - 0b1 - The baud rate is doubled with the duty cycle depending on the Baud
+ *     Rate Prescaler.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_DBR field. */
+#define SPI_RD_CTAR_DBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DBR_MASK) >> SPI_CTAR_DBR_SHIFT)
+#define SPI_BRD_CTAR_DBR(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT))
+
+/*! @brief Set the DBR field to a new value. */
+#define SPI_WR_CTAR_DBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DBR_MASK, SPI_CTAR_DBR(value)))
+#define SPI_BWR_CTAR_DBR(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_SR - Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_SR - Status Register (RW)
+ *
+ * Reset value: 0x02000000U
+ *
+ * SR contains status and flag bits. The bits reflect the status of the module
+ * and indicate the occurrence of events that can generate interrupt or DMA
+ * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
+ * to a flag bit has no effect. This register may not be writable in Module
+ * Disable mode due to the use of power saving mechanisms.
+ */
+/*!
+ * @name Constants and macros for entire SPI_SR register
+ */
+/*@{*/
+#define SPI_RD_SR(base)          (SPI_SR_REG(base))
+#define SPI_WR_SR(base, value)   (SPI_SR_REG(base) = (value))
+#define SPI_RMW_SR(base, mask, value) (SPI_WR_SR(base, (SPI_RD_SR(base) & ~(mask)) | (value)))
+#define SPI_SET_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) |  (value)))
+#define SPI_CLR_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) & ~(value)))
+#define SPI_TOG_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_SR bitfields
+ */
+
+/*!
+ * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
+ *
+ * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
+ * The POPNXTPTR is updated when the POPR is read.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_POPNXTPTR field. */
+#define SPI_RD_SR_POPNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_POPNXTPTR_MASK) >> SPI_SR_POPNXTPTR_SHIFT)
+#define SPI_BRD_SR_POPNXTPTR(base) (SPI_RD_SR_POPNXTPTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RXCTR[7:4] (RO)
+ *
+ * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
+ * every time the POPR is read. The RXCTR is incremented every time data is
+ * transferred from the shift register to the RX FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RXCTR field. */
+#define SPI_RD_SR_RXCTR(base) ((SPI_SR_REG(base) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT)
+#define SPI_BRD_SR_RXCTR(base) (SPI_RD_SR_RXCTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
+ *
+ * Indicates which TX FIFO entry is transmitted during the next transfer. The
+ * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
+ * the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXNXTPTR field. */
+#define SPI_RD_SR_TXNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_TXNXTPTR_MASK) >> SPI_SR_TXNXTPTR_SHIFT)
+#define SPI_BRD_SR_TXNXTPTR(base) (SPI_RD_SR_TXNXTPTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXCTR[15:12] (RO)
+ *
+ * Indicates the number of valid entries in the TX FIFO. The TXCTR is
+ * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
+ * command is executed and the SPI data is transferred to the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXCTR field. */
+#define SPI_RD_SR_TXCTR(base) ((SPI_SR_REG(base) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT)
+#define SPI_BRD_SR_TXCTR(base) (SPI_RD_SR_TXCTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RFDF[17] (W1C)
+ *
+ * Provides a method for the module to request that entries be removed from the
+ * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller when
+ * the RX FIFO is empty.
+ *
+ * Values:
+ * - 0b0 - RX FIFO is empty.
+ * - 0b1 - RX FIFO is not empty.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RFDF field. */
+#define SPI_RD_SR_RFDF(base) ((SPI_SR_REG(base) & SPI_SR_RFDF_MASK) >> SPI_SR_RFDF_SHIFT)
+#define SPI_BRD_SR_RFDF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT))
+
+/*! @brief Set the RFDF field to a new value. */
+#define SPI_WR_SR_RFDF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFDF(value)))
+#define SPI_BWR_SR_RFDF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RFOF[19] (W1C)
+ *
+ * Indicates an overflow condition in the RX FIFO. The field is set when the RX
+ * FIFO and shift register are full and a transfer is initiated. The bit remains
+ * set until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - No Rx FIFO overflow.
+ * - 0b1 - Rx FIFO overflow has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RFOF field. */
+#define SPI_RD_SR_RFOF(base) ((SPI_SR_REG(base) & SPI_SR_RFOF_MASK) >> SPI_SR_RFOF_SHIFT)
+#define SPI_BRD_SR_RFOF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT))
+
+/*! @brief Set the RFOF field to a new value. */
+#define SPI_WR_SR_RFOF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFOF(value)))
+#define SPI_BWR_SR_RFOF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TFFF[25] (W1C)
+ *
+ * Provides a method for the module to request more entries to be added to the
+ * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller to
+ * the TX FIFO full request.
+ *
+ * Values:
+ * - 0b0 - TX FIFO is full.
+ * - 0b1 - TX FIFO is not full.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TFFF field. */
+#define SPI_RD_SR_TFFF(base) ((SPI_SR_REG(base) & SPI_SR_TFFF_MASK) >> SPI_SR_TFFF_SHIFT)
+#define SPI_BRD_SR_TFFF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT))
+
+/*! @brief Set the TFFF field to a new value. */
+#define SPI_WR_SR_TFFF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFFF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFFF(value)))
+#define SPI_BWR_SR_TFFF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TFUF[27] (W1C)
+ *
+ * Indicates an underflow condition in the TX FIFO. The transmit underflow
+ * condition is detected only for SPI blocks operating in Slave mode and SPI
+ * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
+ * is empty and an external SPI master initiates a transfer. The TFUF bit remains
+ * set until cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No TX FIFO underflow.
+ * - 0b1 - TX FIFO underflow has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TFUF field. */
+#define SPI_RD_SR_TFUF(base) ((SPI_SR_REG(base) & SPI_SR_TFUF_MASK) >> SPI_SR_TFUF_SHIFT)
+#define SPI_BRD_SR_TFUF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT))
+
+/*! @brief Set the TFUF field to a new value. */
+#define SPI_WR_SR_TFUF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFUF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFUF(value)))
+#define SPI_BWR_SR_TFUF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field EOQF[28] (W1C)
+ *
+ * Indicates that the last entry in a queue has been transmitted when the module
+ * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
+ * set in the command halfword and the end of the transfer is reached. The EOQF
+ * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
+ * the TXRXS bit is automatically cleared.
+ *
+ * Values:
+ * - 0b0 - EOQ is not set in the executing command.
+ * - 0b1 - EOQ is set in the executing SPI command.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_EOQF field. */
+#define SPI_RD_SR_EOQF(base) ((SPI_SR_REG(base) & SPI_SR_EOQF_MASK) >> SPI_SR_EOQF_SHIFT)
+#define SPI_BRD_SR_EOQF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT))
+
+/*! @brief Set the EOQF field to a new value. */
+#define SPI_WR_SR_EOQF(base, value) (SPI_RMW_SR(base, (SPI_SR_EOQF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_EOQF(value)))
+#define SPI_BWR_SR_EOQF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXRXS[30] (W1C)
+ *
+ * Reflects the run status of the module.
+ *
+ * Values:
+ * - 0b0 - Transmit and receive operations are disabled (The module is in
+ *     Stopped state).
+ * - 0b1 - Transmit and receive operations are enabled (The module is in Running
+ *     state).
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXRXS field. */
+#define SPI_RD_SR_TXRXS(base) ((SPI_SR_REG(base) & SPI_SR_TXRXS_MASK) >> SPI_SR_TXRXS_SHIFT)
+#define SPI_BRD_SR_TXRXS(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT))
+
+/*! @brief Set the TXRXS field to a new value. */
+#define SPI_WR_SR_TXRXS(base, value) (SPI_RMW_SR(base, (SPI_SR_TXRXS_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TCF_MASK), SPI_SR_TXRXS(value)))
+#define SPI_BWR_SR_TXRXS(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TCF[31] (W1C)
+ *
+ * Indicates that all bits in a frame have been shifted out. TCF remains set
+ * until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - Transfer not complete.
+ * - 0b1 - Transfer complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TCF field. */
+#define SPI_RD_SR_TCF(base)  ((SPI_SR_REG(base) & SPI_SR_TCF_MASK) >> SPI_SR_TCF_SHIFT)
+#define SPI_BRD_SR_TCF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT))
+
+/*! @brief Set the TCF field to a new value. */
+#define SPI_WR_SR_TCF(base, value) (SPI_RMW_SR(base, (SPI_SR_TCF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK), SPI_SR_TCF(value)))
+#define SPI_BWR_SR_TCF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RSER controls DMA and interrupt requests. Do not write to the RSER while the
+ * module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RSER register
+ */
+/*@{*/
+#define SPI_RD_RSER(base)        (SPI_RSER_REG(base))
+#define SPI_WR_RSER(base, value) (SPI_RSER_REG(base) = (value))
+#define SPI_RMW_RSER(base, mask, value) (SPI_WR_RSER(base, (SPI_RD_RSER(base) & ~(mask)) | (value)))
+#define SPI_SET_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) |  (value)))
+#define SPI_CLR_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) & ~(value)))
+#define SPI_TOG_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_RSER bitfields
+ */
+
+/*!
+ * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When the
+ * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
+ * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - Interrupt request.
+ * - 0b1 - DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */
+#define SPI_RD_RSER_RFDF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_DIRS_MASK) >> SPI_RSER_RFDF_DIRS_SHIFT)
+#define SPI_BRD_RSER_RFDF_DIRS(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT))
+
+/*! @brief Set the RFDF_DIRS field to a new value. */
+#define SPI_WR_RSER_RFDF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_DIRS_MASK, SPI_RSER_RFDF_DIRS(value)))
+#define SPI_BWR_RSER_RFDF_DIRS(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field RFDF_RE[17] (RW)
+ *
+ * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - RFDF interrupt or DMA requests are disabled.
+ * - 0b1 - RFDF interrupt or DMA requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFDF_RE field. */
+#define SPI_RD_RSER_RFDF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_RE_MASK) >> SPI_RSER_RFDF_RE_SHIFT)
+#define SPI_BRD_RSER_RFDF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT))
+
+/*! @brief Set the RFDF_RE field to a new value. */
+#define SPI_WR_RSER_RFDF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_RE_MASK, SPI_RSER_RFDF_RE(value)))
+#define SPI_BWR_RSER_RFDF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field RFOF_RE[19] (RW)
+ *
+ * Enables the RFOF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - RFOF interrupt requests are disabled.
+ * - 0b1 - RFOF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFOF_RE field. */
+#define SPI_RD_RSER_RFOF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFOF_RE_MASK) >> SPI_RSER_RFOF_RE_SHIFT)
+#define SPI_BRD_RSER_RFOF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT))
+
+/*! @brief Set the RFOF_RE field to a new value. */
+#define SPI_WR_RSER_RFOF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFOF_RE_MASK, SPI_RSER_RFOF_RE(value)))
+#define SPI_BWR_RSER_RFOF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When
+ * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
+ * interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - TFFF flag generates interrupt requests.
+ * - 0b1 - TFFF flag generates DMA requests.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */
+#define SPI_RD_RSER_TFFF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_DIRS_MASK) >> SPI_RSER_TFFF_DIRS_SHIFT)
+#define SPI_BRD_RSER_TFFF_DIRS(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT))
+
+/*! @brief Set the TFFF_DIRS field to a new value. */
+#define SPI_WR_RSER_TFFF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_DIRS_MASK, SPI_RSER_TFFF_DIRS(value)))
+#define SPI_BWR_RSER_TFFF_DIRS(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFFF_RE[25] (RW)
+ *
+ * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - TFFF interrupts or DMA requests are disabled.
+ * - 0b1 - TFFF interrupts or DMA requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFFF_RE field. */
+#define SPI_RD_RSER_TFFF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_RE_MASK) >> SPI_RSER_TFFF_RE_SHIFT)
+#define SPI_BRD_RSER_TFFF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT))
+
+/*! @brief Set the TFFF_RE field to a new value. */
+#define SPI_WR_RSER_TFFF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_RE_MASK, SPI_RSER_TFFF_RE(value)))
+#define SPI_BWR_RSER_TFFF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFUF_RE[27] (RW)
+ *
+ * Enables the TFUF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - TFUF interrupt requests are disabled.
+ * - 0b1 - TFUF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFUF_RE field. */
+#define SPI_RD_RSER_TFUF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFUF_RE_MASK) >> SPI_RSER_TFUF_RE_SHIFT)
+#define SPI_BRD_RSER_TFUF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT))
+
+/*! @brief Set the TFUF_RE field to a new value. */
+#define SPI_WR_RSER_TFUF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFUF_RE_MASK, SPI_RSER_TFUF_RE(value)))
+#define SPI_BWR_RSER_TFUF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field EOQF_RE[28] (RW)
+ *
+ * Enables the EOQF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - EOQF interrupt requests are disabled.
+ * - 0b1 - EOQF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_EOQF_RE field. */
+#define SPI_RD_RSER_EOQF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_EOQF_RE_MASK) >> SPI_RSER_EOQF_RE_SHIFT)
+#define SPI_BRD_RSER_EOQF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT))
+
+/*! @brief Set the EOQF_RE field to a new value. */
+#define SPI_WR_RSER_EOQF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_EOQF_RE_MASK, SPI_RSER_EOQF_RE(value)))
+#define SPI_BWR_RSER_EOQF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TCF_RE[31] (RW)
+ *
+ * Enables TCF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - TCF interrupt requests are disabled.
+ * - 0b1 - TCF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TCF_RE field. */
+#define SPI_RD_RSER_TCF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TCF_RE_MASK) >> SPI_RSER_TCF_RE_SHIFT)
+#define SPI_BRD_RSER_TCF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT))
+
+/*! @brief Set the TCF_RE field to a new value. */
+#define SPI_WR_RSER_TCF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TCF_RE_MASK, SPI_RSER_TCF_RE(value)))
+#define SPI_BWR_RSER_TCF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
+ * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
+ * can be used as data, supporting up to 32-bit frame operation. A read access
+ * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
+ * writing to this register does not update the FIFO. Therefore, any reads performed
+ * while the module is disabled return the last PUSHR write performed while the
+ * module was still enabled.
+ */
+/*!
+ * @name Constants and macros for entire SPI_PUSHR register
+ */
+/*@{*/
+#define SPI_RD_PUSHR(base)       (SPI_PUSHR_REG(base))
+#define SPI_WR_PUSHR(base, value) (SPI_PUSHR_REG(base) = (value))
+#define SPI_RMW_PUSHR(base, mask, value) (SPI_WR_PUSHR(base, (SPI_RD_PUSHR(base) & ~(mask)) | (value)))
+#define SPI_SET_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) |  (value)))
+#define SPI_CLR_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) & ~(value)))
+#define SPI_TOG_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_PUSHR bitfields
+ */
+
+/*!
+ * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
+ *
+ * Holds SPI data to be transferred according to the associated SPI command.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_TXDATA field. */
+#define SPI_RD_PUSHR_TXDATA(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_TXDATA_MASK) >> SPI_PUSHR_TXDATA_SHIFT)
+#define SPI_BRD_PUSHR_TXDATA(base) (SPI_RD_PUSHR_TXDATA(base))
+
+/*! @brief Set the TXDATA field to a new value. */
+#define SPI_WR_PUSHR_TXDATA(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_TXDATA_MASK, SPI_PUSHR_TXDATA(value)))
+#define SPI_BWR_PUSHR_TXDATA(base, value) (SPI_WR_PUSHR_TXDATA(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field PCS[21:16] (RW)
+ *
+ * Select which PCS signals are to be asserted for the transfer. Refer to the
+ * chip configuration details for the number of PCS signals used in this MCU.
+ *
+ * Values:
+ * - 0b000000 - Negate the PCS[x] signal.
+ * - 0b000001 - Assert the PCS[x] signal.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_PCS field. */
+#define SPI_RD_PUSHR_PCS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_PCS_MASK) >> SPI_PUSHR_PCS_SHIFT)
+#define SPI_BRD_PUSHR_PCS(base) (SPI_RD_PUSHR_PCS(base))
+
+/*! @brief Set the PCS field to a new value. */
+#define SPI_WR_PUSHR_PCS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_PCS_MASK, SPI_PUSHR_PCS(value)))
+#define SPI_BWR_PUSHR_PCS(base, value) (SPI_WR_PUSHR_PCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CTCNT[26] (RW)
+ *
+ * Clears the TCNT field in the TCR register. The TCNT field is cleared before
+ * the module starts transmitting the current SPI frame.
+ *
+ * Values:
+ * - 0b0 - Do not clear the TCR[TCNT] field.
+ * - 0b1 - Clear the TCR[TCNT] field.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CTCNT field. */
+#define SPI_RD_PUSHR_CTCNT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTCNT_MASK) >> SPI_PUSHR_CTCNT_SHIFT)
+#define SPI_BRD_PUSHR_CTCNT(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT))
+
+/*! @brief Set the CTCNT field to a new value. */
+#define SPI_WR_PUSHR_CTCNT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTCNT_MASK, SPI_PUSHR_CTCNT(value)))
+#define SPI_BWR_PUSHR_CTCNT(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field EOQ[27] (RW)
+ *
+ * Host software uses this bit to signal to the module that the current SPI
+ * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
+ * SR is set.
+ *
+ * Values:
+ * - 0b0 - The SPI data is not the last data to transfer.
+ * - 0b1 - The SPI data is the last data to transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_EOQ field. */
+#define SPI_RD_PUSHR_EOQ(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_EOQ_MASK) >> SPI_PUSHR_EOQ_SHIFT)
+#define SPI_BRD_PUSHR_EOQ(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT))
+
+/*! @brief Set the EOQ field to a new value. */
+#define SPI_WR_PUSHR_EOQ(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_EOQ_MASK, SPI_PUSHR_EOQ(value)))
+#define SPI_BWR_PUSHR_EOQ(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
+ *
+ * Selects which CTAR to use in master mode to specify the transfer attributes
+ * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
+ * configuration details to determine how many CTARs this device has. You should
+ * not program a value in this field for a register that is not present.
+ *
+ * Values:
+ * - 0b000 - CTAR0
+ * - 0b001 - CTAR1
+ * - 0b010 - Reserved
+ * - 0b011 - Reserved
+ * - 0b100 - Reserved
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CTAS field. */
+#define SPI_RD_PUSHR_CTAS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTAS_MASK) >> SPI_PUSHR_CTAS_SHIFT)
+#define SPI_BRD_PUSHR_CTAS(base) (SPI_RD_PUSHR_CTAS(base))
+
+/*! @brief Set the CTAS field to a new value. */
+#define SPI_WR_PUSHR_CTAS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTAS_MASK, SPI_PUSHR_CTAS(value)))
+#define SPI_BWR_PUSHR_CTAS(base, value) (SPI_WR_PUSHR_CTAS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CONT[31] (RW)
+ *
+ * Selects a continuous selection format. The bit is used in SPI Master mode.
+ * The bit enables the selected PCS signals to remain asserted between transfers.
+ *
+ * Values:
+ * - 0b0 - Return PCSn signals to their inactive state between transfers.
+ * - 0b1 - Keep PCSn signals asserted between transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CONT field. */
+#define SPI_RD_PUSHR_CONT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CONT_MASK) >> SPI_PUSHR_CONT_SHIFT)
+#define SPI_BRD_PUSHR_CONT(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT))
+
+/*! @brief Set the CONT field to a new value. */
+#define SPI_WR_PUSHR_CONT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CONT_MASK, SPI_PUSHR_CONT(value)))
+#define SPI_BWR_PUSHR_CONT(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
+ * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
+ * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
+ * SPI Frame operation.
+ */
+/*!
+ * @name Constants and macros for entire SPI_PUSHR_SLAVE register
+ */
+/*@{*/
+#define SPI_RD_PUSHR_SLAVE(base) (SPI_PUSHR_SLAVE_REG(base))
+#define SPI_WR_PUSHR_SLAVE(base, value) (SPI_PUSHR_SLAVE_REG(base) = (value))
+#define SPI_RMW_PUSHR_SLAVE(base, mask, value) (SPI_WR_PUSHR_SLAVE(base, (SPI_RD_PUSHR_SLAVE(base) & ~(mask)) | (value)))
+#define SPI_SET_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) |  (value)))
+#define SPI_CLR_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) & ~(value)))
+#define SPI_TOG_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_POPR - POP RX FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_POPR - POP RX FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
+ * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
+ * this register will generate a Transfer Error.
+ */
+/*!
+ * @name Constants and macros for entire SPI_POPR register
+ */
+/*@{*/
+#define SPI_RD_POPR(base)        (SPI_POPR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR0 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR0 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR0 register
+ */
+/*@{*/
+#define SPI_RD_TXFR0(base)       (SPI_TXFR0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR0 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR0, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR0_TXDATA field. */
+#define SPI_RD_TXFR0_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXDATA_MASK) >> SPI_TXFR0_TXDATA_SHIFT)
+#define SPI_BRD_TXFR0_TXDATA(base) (SPI_RD_TXFR0_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR0, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR0_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR0_TXCMD_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXCMD_TXDATA_MASK) >> SPI_TXFR0_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR0_TXCMD_TXDATA(base) (SPI_RD_TXFR0_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR1 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR1 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR1 register
+ */
+/*@{*/
+#define SPI_RD_TXFR1(base)       (SPI_TXFR1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR1 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR1, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR1_TXDATA field. */
+#define SPI_RD_TXFR1_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXDATA_MASK) >> SPI_TXFR1_TXDATA_SHIFT)
+#define SPI_BRD_TXFR1_TXDATA(base) (SPI_RD_TXFR1_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR1, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR1_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR1_TXCMD_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXCMD_TXDATA_MASK) >> SPI_TXFR1_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR1_TXCMD_TXDATA(base) (SPI_RD_TXFR1_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR2 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR2 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR2 register
+ */
+/*@{*/
+#define SPI_RD_TXFR2(base)       (SPI_TXFR2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR2 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR2, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR2_TXDATA field. */
+#define SPI_RD_TXFR2_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXDATA_MASK) >> SPI_TXFR2_TXDATA_SHIFT)
+#define SPI_BRD_TXFR2_TXDATA(base) (SPI_RD_TXFR2_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR2, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR2_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR2_TXCMD_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXCMD_TXDATA_MASK) >> SPI_TXFR2_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR2_TXCMD_TXDATA(base) (SPI_RD_TXFR2_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR3 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR3 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR3 register
+ */
+/*@{*/
+#define SPI_RD_TXFR3(base)       (SPI_TXFR3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR3 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR3, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR3_TXDATA field. */
+#define SPI_RD_TXFR3_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXDATA_MASK) >> SPI_TXFR3_TXDATA_SHIFT)
+#define SPI_BRD_TXFR3_TXDATA(base) (SPI_RD_TXFR3_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR3, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR3_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR3_TXCMD_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXCMD_TXDATA_MASK) >> SPI_TXFR3_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR3_TXCMD_TXDATA(base) (SPI_RD_TXFR3_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR0 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR0 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR0 register
+ */
+/*@{*/
+#define SPI_RD_RXFR0(base)       (SPI_RXFR0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR1 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR1 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR1 register
+ */
+/*@{*/
+#define SPI_RD_RXFR1(base)       (SPI_RXFR1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR2 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR2 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR2 register
+ */
+/*@{*/
+#define SPI_RD_RXFR2(base)       (SPI_RXFR2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR3 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR3 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR3 register
+ */
+/*@{*/
+#define SPI_RD_RXFR3(base)       (SPI_RXFR3_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 UART
+ *
+ * Serial Communication Interface
+ *
+ * Registers defined in this header file:
+ * - UART_BDH - UART Baud Rate Registers: High
+ * - UART_BDL - UART Baud Rate Registers: Low
+ * - UART_C1 - UART Control Register 1
+ * - UART_C2 - UART Control Register 2
+ * - UART_S1 - UART Status Register 1
+ * - UART_S2 - UART Status Register 2
+ * - UART_C3 - UART Control Register 3
+ * - UART_D - UART Data Register
+ * - UART_MA1 - UART Match Address Registers 1
+ * - UART_MA2 - UART Match Address Registers 2
+ * - UART_C4 - UART Control Register 4
+ * - UART_C5 - UART Control Register 5
+ * - UART_ED - UART Extended Data Register
+ * - UART_MODEM - UART Modem Register
+ * - UART_IR - UART Infrared Register
+ * - UART_PFIFO - UART FIFO Parameters
+ * - UART_CFIFO - UART FIFO Control Register
+ * - UART_SFIFO - UART FIFO Status Register
+ * - UART_TWFIFO - UART FIFO Transmit Watermark
+ * - UART_TCFIFO - UART FIFO Transmit Count
+ * - UART_RWFIFO - UART FIFO Receive Watermark
+ * - UART_RCFIFO - UART FIFO Receive Count
+ * - UART_C7816 - UART 7816 Control Register
+ * - UART_IE7816 - UART 7816 Interrupt Enable Register
+ * - UART_IS7816 - UART 7816 Interrupt Status Register
+ * - UART_WP7816T0 - UART 7816 Wait Parameter Register
+ * - UART_WP7816T1 - UART 7816 Wait Parameter Register
+ * - UART_WN7816 - UART 7816 Wait N Register
+ * - UART_WF7816 - UART 7816 Wait FD Register
+ * - UART_ET7816 - UART 7816 Error Threshold Register
+ * - UART_TL7816 - UART 7816 Transmit Length Register
+ */
+
+#define UART_INSTANCE_COUNT (6U) /*!< Number of instances of the UART module. */
+#define UART0_IDX (0U) /*!< Instance number for UART0. */
+#define UART1_IDX (1U) /*!< Instance number for UART1. */
+#define UART2_IDX (2U) /*!< Instance number for UART2. */
+#define UART3_IDX (3U) /*!< Instance number for UART3. */
+#define UART4_IDX (4U) /*!< Instance number for UART4. */
+#define UART5_IDX (5U) /*!< Instance number for UART5. */
+
+/*******************************************************************************
+ * UART_BDH - UART Baud Rate Registers: High
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDH - UART Baud Rate Registers: High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register, along with the BDL register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting
+ * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
+ * to BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is,
+ * when C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDH register
+ */
+/*@{*/
+#define UART_RD_BDH(base)        (UART_BDH_REG(base))
+#define UART_WR_BDH(base, value) (UART_BDH_REG(base) = (value))
+#define UART_RMW_BDH(base, mask, value) (UART_WR_BDH(base, (UART_RD_BDH(base) & ~(mask)) | (value)))
+#define UART_SET_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) |  (value)))
+#define UART_CLR_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) & ~(value)))
+#define UART_TOG_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_BDH bitfields
+ */
+
+/*!
+ * @name Register UART_BDH, field SBR[4:0] (RW)
+ *
+ * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
+ * generation for details. The baud rate generator is disabled until C2[TE] or
+ * C2[RE] is set for the first time after reset.The baud rate generator is disabled
+ * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
+ * writing to BDH puts the data in a temporary location until BDL is written.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBR field. */
+#define UART_RD_BDH_SBR(base) ((UART_BDH_REG(base) & UART_BDH_SBR_MASK) >> UART_BDH_SBR_SHIFT)
+#define UART_BRD_BDH_SBR(base) (UART_RD_BDH_SBR(base))
+
+/*! @brief Set the SBR field to a new value. */
+#define UART_WR_BDH_SBR(base, value) (UART_RMW_BDH(base, UART_BDH_SBR_MASK, UART_BDH_SBR(value)))
+#define UART_BWR_BDH_SBR(base, value) (UART_WR_BDH_SBR(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field SBNS[5] (RW)
+ *
+ * SBNS selects the number of stop bits present in a data frame. This field
+ * valid for all 8, 9 and 10 bit data formats available. This field is not valid when
+ * C7816[ISO7816E] is enabled.
+ *
+ * Values:
+ * - 0b0 - Data frame consists of a single stop bit.
+ * - 0b1 - Data frame consists of two stop bits.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBNS field. */
+#define UART_RD_BDH_SBNS(base) ((UART_BDH_REG(base) & UART_BDH_SBNS_MASK) >> UART_BDH_SBNS_SHIFT)
+#define UART_BRD_BDH_SBNS(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_SBNS_SHIFT))
+
+/*! @brief Set the SBNS field to a new value. */
+#define UART_WR_BDH_SBNS(base, value) (UART_RMW_BDH(base, UART_BDH_SBNS_MASK, UART_BDH_SBNS(value)))
+#define UART_BWR_BDH_SBNS(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_SBNS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field RXEDGIE[6] (RW)
+ *
+ * Enables the receive input active edge, RXEDGIF, to generate interrupt
+ * requests.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupts from RXEDGIF disabled using polling.
+ * - 0b1 - RXEDGIF interrupt request enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_RXEDGIE field. */
+#define UART_RD_BDH_RXEDGIE(base) ((UART_BDH_REG(base) & UART_BDH_RXEDGIE_MASK) >> UART_BDH_RXEDGIE_SHIFT)
+#define UART_BRD_BDH_RXEDGIE(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT))
+
+/*! @brief Set the RXEDGIE field to a new value. */
+#define UART_WR_BDH_RXEDGIE(base, value) (UART_RMW_BDH(base, UART_BDH_RXEDGIE_MASK, UART_BDH_RXEDGIE(value)))
+#define UART_BWR_BDH_RXEDGIE(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field LBKDIE[7] (RW)
+ *
+ * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
+ * based on the state of LBKDDMAS. or DMA transfer requests,
+ *
+ * Values:
+ * - 0b0 - LBKDIF interrupt and DMA transfer requests disabled.
+ * - 0b1 - LBKDIF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_LBKDIE field. */
+#define UART_RD_BDH_LBKDIE(base) ((UART_BDH_REG(base) & UART_BDH_LBKDIE_MASK) >> UART_BDH_LBKDIE_SHIFT)
+#define UART_BRD_BDH_LBKDIE(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_LBKDIE_SHIFT))
+
+/*! @brief Set the LBKDIE field to a new value. */
+#define UART_WR_BDH_LBKDIE(base, value) (UART_RMW_BDH(base, UART_BDH_LBKDIE_MASK, UART_BDH_LBKDIE(value)))
+#define UART_BWR_BDH_LBKDIE(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_LBKDIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_BDL - UART Baud Rate Registers: Low
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDL - UART Baud Rate Registers: Low (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * This register, along with the BDH register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
+ * first write to BDH to buffer the high half of the new value and then write to
+ * BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is, when
+ * C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDL register
+ */
+/*@{*/
+#define UART_RD_BDL(base)        (UART_BDL_REG(base))
+#define UART_WR_BDL(base, value) (UART_BDL_REG(base) = (value))
+#define UART_RMW_BDL(base, mask, value) (UART_WR_BDL(base, (UART_RD_BDL(base) & ~(mask)) | (value)))
+#define UART_SET_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) |  (value)))
+#define UART_CLR_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) & ~(value)))
+#define UART_TOG_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C1 - UART Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C1 - UART Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This read/write register controls various optional features of the UART
+ * system.
+ */
+/*!
+ * @name Constants and macros for entire UART_C1 register
+ */
+/*@{*/
+#define UART_RD_C1(base)         (UART_C1_REG(base))
+#define UART_WR_C1(base, value)  (UART_C1_REG(base) = (value))
+#define UART_RMW_C1(base, mask, value) (UART_WR_C1(base, (UART_RD_C1(base) & ~(mask)) | (value)))
+#define UART_SET_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) |  (value)))
+#define UART_CLR_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) & ~(value)))
+#define UART_TOG_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C1 bitfields
+ */
+
+/*!
+ * @name Register UART_C1, field PT[0] (RW)
+ *
+ * Determines whether the UART generates and checks for even parity or odd
+ * parity. With even parity, an even number of 1s clears the parity bit and an odd
+ * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
+ * parity bit and an even number of 1s sets the parity bit. This field must be
+ * cleared when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Even parity.
+ * - 0b1 - Odd parity.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PT field. */
+#define UART_RD_C1_PT(base)  ((UART_C1_REG(base) & UART_C1_PT_MASK) >> UART_C1_PT_SHIFT)
+#define UART_BRD_C1_PT(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PT_SHIFT))
+
+/*! @brief Set the PT field to a new value. */
+#define UART_WR_C1_PT(base, value) (UART_RMW_C1(base, UART_C1_PT_MASK, UART_C1_PT(value)))
+#define UART_BWR_C1_PT(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field PE[1] (RW)
+ *
+ * Enables the parity function. When parity is enabled, parity function inserts
+ * a parity bit in the bit position immediately preceding the stop bit. This
+ * field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Parity function disabled.
+ * - 0b1 - Parity function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PE field. */
+#define UART_RD_C1_PE(base)  ((UART_C1_REG(base) & UART_C1_PE_MASK) >> UART_C1_PE_SHIFT)
+#define UART_BRD_C1_PE(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PE_SHIFT))
+
+/*! @brief Set the PE field to a new value. */
+#define UART_WR_C1_PE(base, value) (UART_RMW_C1(base, UART_C1_PE_MASK, UART_C1_PE(value)))
+#define UART_BWR_C1_PE(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field ILT[2] (RW)
+ *
+ * Determines when the receiver starts counting logic 1s as idle character bits.
+ * The count begins either after a valid start bit or after the stop bit. If the
+ * count begins after the start bit, then a string of logic 1s preceding the
+ * stop bit can cause false recognition of an idle character. Beginning the count
+ * after the stop bit avoids false idle character recognition, but requires
+ * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
+ * logic of 1'b0 is automatically shifted after a received stop bit, therefore
+ * resetting the idle count. In case the UART is programmed for IDLE line wakeup
+ * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
+ * logic 1s as idle character bits. In idle line wakeup, an idle character is
+ * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
+ * and C4[M10] fields.
+ *
+ * Values:
+ * - 0b0 - Idle character bit count starts after start bit.
+ * - 0b1 - Idle character bit count starts after stop bit.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_ILT field. */
+#define UART_RD_C1_ILT(base) ((UART_C1_REG(base) & UART_C1_ILT_MASK) >> UART_C1_ILT_SHIFT)
+#define UART_BRD_C1_ILT(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_ILT_SHIFT))
+
+/*! @brief Set the ILT field to a new value. */
+#define UART_WR_C1_ILT(base, value) (UART_RMW_C1(base, UART_C1_ILT_MASK, UART_C1_ILT(value)))
+#define UART_BWR_C1_ILT(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_ILT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field WAKE[3] (RW)
+ *
+ * Determines which condition wakes the UART: Address mark in the most
+ * significant bit position of a received data character, or An idle condition on the
+ * receive pin input signal.
+ *
+ * Values:
+ * - 0b0 - Idle line wakeup.
+ * - 0b1 - Address mark wakeup.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_WAKE field. */
+#define UART_RD_C1_WAKE(base) ((UART_C1_REG(base) & UART_C1_WAKE_MASK) >> UART_C1_WAKE_SHIFT)
+#define UART_BRD_C1_WAKE(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT))
+
+/*! @brief Set the WAKE field to a new value. */
+#define UART_WR_C1_WAKE(base, value) (UART_RMW_C1(base, UART_C1_WAKE_MASK, UART_C1_WAKE(value)))
+#define UART_BWR_C1_WAKE(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field M[4] (RW)
+ *
+ * This field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) +
+ *     stop.
+ * - 0b1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_M field. */
+#define UART_RD_C1_M(base)   ((UART_C1_REG(base) & UART_C1_M_MASK) >> UART_C1_M_SHIFT)
+#define UART_BRD_C1_M(base)  (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_M_SHIFT))
+
+/*! @brief Set the M field to a new value. */
+#define UART_WR_C1_M(base, value) (UART_RMW_C1(base, UART_C1_M_MASK, UART_C1_M(value)))
+#define UART_BWR_C1_M(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_M_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field RSRC[5] (RW)
+ *
+ * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
+ * is set, the RSRC field determines the source for the receiver shift register
+ * input.
+ *
+ * Values:
+ * - 0b0 - Selects internal loop back mode. The receiver input is internally
+ *     connected to transmitter output.
+ * - 0b1 - Single wire UART mode where the receiver input is connected to the
+ *     transmit pin input signal.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_RSRC field. */
+#define UART_RD_C1_RSRC(base) ((UART_C1_REG(base) & UART_C1_RSRC_MASK) >> UART_C1_RSRC_SHIFT)
+#define UART_BRD_C1_RSRC(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT))
+
+/*! @brief Set the RSRC field to a new value. */
+#define UART_WR_C1_RSRC(base, value) (UART_RMW_C1(base, UART_C1_RSRC_MASK, UART_C1_RSRC(value)))
+#define UART_BWR_C1_RSRC(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field UARTSWAI[6] (RW)
+ *
+ * Values:
+ * - 0b0 - UART clock continues to run in Wait mode.
+ * - 0b1 - UART clock freezes while CPU is in Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_UARTSWAI field. */
+#define UART_RD_C1_UARTSWAI(base) ((UART_C1_REG(base) & UART_C1_UARTSWAI_MASK) >> UART_C1_UARTSWAI_SHIFT)
+#define UART_BRD_C1_UARTSWAI(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_UARTSWAI_SHIFT))
+
+/*! @brief Set the UARTSWAI field to a new value. */
+#define UART_WR_C1_UARTSWAI(base, value) (UART_RMW_C1(base, UART_C1_UARTSWAI_MASK, UART_C1_UARTSWAI(value)))
+#define UART_BWR_C1_UARTSWAI(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_UARTSWAI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field LOOPS[7] (RW)
+ *
+ * When LOOPS is set, the RxD pin is disconnected from the UART and the
+ * transmitter output is internally connected to the receiver input. The transmitter and
+ * the receiver must be enabled to use the loop function.
+ *
+ * Values:
+ * - 0b0 - Normal operation.
+ * - 0b1 - Loop mode where transmitter output is internally connected to
+ *     receiver input. The receiver input is determined by RSRC.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_LOOPS field. */
+#define UART_RD_C1_LOOPS(base) ((UART_C1_REG(base) & UART_C1_LOOPS_MASK) >> UART_C1_LOOPS_SHIFT)
+#define UART_BRD_C1_LOOPS(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT))
+
+/*! @brief Set the LOOPS field to a new value. */
+#define UART_WR_C1_LOOPS(base, value) (UART_RMW_C1(base, UART_C1_LOOPS_MASK, UART_C1_LOOPS(value)))
+#define UART_BWR_C1_LOOPS(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C2 - UART Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C2 - UART Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register can be read or written at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_C2 register
+ */
+/*@{*/
+#define UART_RD_C2(base)         (UART_C2_REG(base))
+#define UART_WR_C2(base, value)  (UART_C2_REG(base) = (value))
+#define UART_RMW_C2(base, mask, value) (UART_WR_C2(base, (UART_RD_C2(base) & ~(mask)) | (value)))
+#define UART_SET_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) |  (value)))
+#define UART_CLR_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) & ~(value)))
+#define UART_TOG_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C2 bitfields
+ */
+
+/*!
+ * @name Register UART_C2, field SBK[0] (RW)
+ *
+ * Toggling SBK sends one break character from the following: See Transmitting
+ * break characters for the number of logic 0s for the different configurations.
+ * Toggling implies clearing the SBK field before the break character has finished
+ * transmitting. As long as SBK is set, the transmitter continues to send
+ * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
+ * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
+ * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
+ * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
+ * C7816[ISO_7816E] is set.
+ *
+ * Values:
+ * - 0b0 - Normal transmitter operation.
+ * - 0b1 - Queue break characters to be sent.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_SBK field. */
+#define UART_RD_C2_SBK(base) ((UART_C2_REG(base) & UART_C2_SBK_MASK) >> UART_C2_SBK_SHIFT)
+#define UART_BRD_C2_SBK(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_SBK_SHIFT))
+
+/*! @brief Set the SBK field to a new value. */
+#define UART_WR_C2_SBK(base, value) (UART_RMW_C2(base, UART_C2_SBK_MASK, UART_C2_SBK(value)))
+#define UART_BWR_C2_SBK(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_SBK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RWU[1] (RW)
+ *
+ * This field can be set to place the UART receiver in a standby state. RWU
+ * automatically clears when an RWU event occurs, that is, an IDLE event when
+ * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
+ * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
+ * on idle) if the channel is currently not idle. This can be determined by
+ * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
+ * idle, it is possible that the UART will discard data. This is because the data
+ * must be received or a LIN break detected after an IDLE is detected before IDLE
+ * is allowed to reasserted.
+ *
+ * Values:
+ * - 0b0 - Normal operation.
+ * - 0b1 - RWU enables the wakeup function and inhibits further receiver
+ *     interrupt requests. Normally, hardware wakes the receiver by automatically
+ *     clearing RWU.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RWU field. */
+#define UART_RD_C2_RWU(base) ((UART_C2_REG(base) & UART_C2_RWU_MASK) >> UART_C2_RWU_SHIFT)
+#define UART_BRD_C2_RWU(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RWU_SHIFT))
+
+/*! @brief Set the RWU field to a new value. */
+#define UART_WR_C2_RWU(base, value) (UART_RMW_C2(base, UART_C2_RWU_MASK, UART_C2_RWU(value)))
+#define UART_BWR_C2_RWU(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RWU_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RE[2] (RW)
+ *
+ * Enables the UART receiver.
+ *
+ * Values:
+ * - 0b0 - Receiver off.
+ * - 0b1 - Receiver on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RE field. */
+#define UART_RD_C2_RE(base)  ((UART_C2_REG(base) & UART_C2_RE_MASK) >> UART_C2_RE_SHIFT)
+#define UART_BRD_C2_RE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RE_SHIFT))
+
+/*! @brief Set the RE field to a new value. */
+#define UART_WR_C2_RE(base, value) (UART_RMW_C2(base, UART_C2_RE_MASK, UART_C2_RE(value)))
+#define UART_BWR_C2_RE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TE[3] (RW)
+ *
+ * Enables the UART transmitter. TE can be used to queue an idle preamble by
+ * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
+ * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
+ * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
+ * additional characters are transmitted.
+ *
+ * Values:
+ * - 0b0 - Transmitter off.
+ * - 0b1 - Transmitter on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TE field. */
+#define UART_RD_C2_TE(base)  ((UART_C2_REG(base) & UART_C2_TE_MASK) >> UART_C2_TE_SHIFT)
+#define UART_BRD_C2_TE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TE_SHIFT))
+
+/*! @brief Set the TE field to a new value. */
+#define UART_WR_C2_TE(base, value) (UART_RMW_C2(base, UART_C2_TE_MASK, UART_C2_TE(value)))
+#define UART_BWR_C2_TE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field ILIE[4] (RW)
+ *
+ * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
+ * transfer requests based on the state of C5[ILDMAS].
+ *
+ * Values:
+ * - 0b0 - IDLE interrupt requests disabled. and DMA transfer
+ * - 0b1 - IDLE interrupt requests enabled. or DMA transfer
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_ILIE field. */
+#define UART_RD_C2_ILIE(base) ((UART_C2_REG(base) & UART_C2_ILIE_MASK) >> UART_C2_ILIE_SHIFT)
+#define UART_BRD_C2_ILIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT))
+
+/*! @brief Set the ILIE field to a new value. */
+#define UART_WR_C2_ILIE(base, value) (UART_RMW_C2(base, UART_C2_ILIE_MASK, UART_C2_ILIE(value)))
+#define UART_BWR_C2_ILIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RIE[5] (RW)
+ *
+ * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[RDMAS].
+ *
+ * Values:
+ * - 0b0 - RDRF interrupt and DMA transfer requests disabled.
+ * - 0b1 - RDRF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RIE field. */
+#define UART_RD_C2_RIE(base) ((UART_C2_REG(base) & UART_C2_RIE_MASK) >> UART_C2_RIE_SHIFT)
+#define UART_BRD_C2_RIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RIE_SHIFT))
+
+/*! @brief Set the RIE field to a new value. */
+#define UART_WR_C2_RIE(base, value) (UART_RMW_C2(base, UART_C2_RIE_MASK, UART_C2_RIE(value)))
+#define UART_BWR_C2_RIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TCIE[6] (RW)
+ *
+ * Enables the transmission complete flag, S1[TC], to generate interrupt
+ * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
+ * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
+ * written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0b0 - TC interrupt and DMA transfer requests disabled.
+ * - 0b1 - TC interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TCIE field. */
+#define UART_RD_C2_TCIE(base) ((UART_C2_REG(base) & UART_C2_TCIE_MASK) >> UART_C2_TCIE_SHIFT)
+#define UART_BRD_C2_TCIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT))
+
+/*! @brief Set the TCIE field to a new value. */
+#define UART_WR_C2_TCIE(base, value) (UART_RMW_C2(base, UART_C2_TCIE_MASK, UART_C2_TCIE(value)))
+#define UART_BWR_C2_TCIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TIE[7] (RW)
+ *
+ * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
+ * must be cleared, and D[D] must not be written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0b0 - TDRE interrupt and DMA transfer requests disabled.
+ * - 0b1 - TDRE interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TIE field. */
+#define UART_RD_C2_TIE(base) ((UART_C2_REG(base) & UART_C2_TIE_MASK) >> UART_C2_TIE_SHIFT)
+#define UART_BRD_C2_TIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define UART_WR_C2_TIE(base, value) (UART_RMW_C2(base, UART_C2_TIE_MASK, UART_C2_TIE(value)))
+#define UART_BWR_C2_TIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S1 - UART Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S1 - UART Status Register 1 (RO)
+ *
+ * Reset value: 0xC0U
+ *
+ * The S1 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. This register can also be polled by the MCU to check the
+ * status of its fields. To clear a flag, the status register should be read followed
+ * by a read or write to D register, depending on the interrupt flag type. Other
+ * instructions can be executed between the two steps as long the handling of
+ * I/O is not compromised, but the order of operations is important for flag
+ * clearing. When a flag is configured to trigger a DMA request, assertion of the
+ * associated DMA done signal from the DMA controller clears the flag. If the
+ * condition that results in the assertion of the flag, interrupt, or DMA request is not
+ * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
+ * reasserts. For example, if the DMA or interrupt service routine fails to write
+ * sufficient data to the transmit buffer to raise it above the watermark level, the
+ * flag reasserts and generates another interrupt or DMA request. Reading an
+ * empty data register to clear one of the flags of the S1 register causes the FIFO
+ * pointers to become misaligned. A receive FIFO flush reinitializes the
+ * pointers. A better way to prevent this situation is to always leave one byte in FIFO
+ * and this byte will be read eventually in clearing the flag bit.
+ */
+/*!
+ * @name Constants and macros for entire UART_S1 register
+ */
+/*@{*/
+#define UART_RD_S1(base)         (UART_S1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S1 bitfields
+ */
+
+/*!
+ * @name Register UART_S1, field PF[0] (RO)
+ *
+ * PF is set when PE is set and the parity of the received data does not match
+ * its parity bit. The PF is not set in the case of an overrun condition. When PF
+ * is set, it indicates only that a dataword was received with parity error since
+ * the last time it was cleared. There is no guarantee that the first dataword
+ * read from the receive buffer has a parity error or that there is only one
+ * dataword in the buffer that was received with a parity error, unless the receive
+ * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
+ * disabled, Within the receive buffer structure the received dataword is tagged
+ * if it is received with a parity error. This information is available by reading
+ * the ED register prior to reading the D register.
+ *
+ * Values:
+ * - 0b0 - No parity error detected since the last time this flag was cleared.
+ *     If the receive buffer has a depth greater than 1, then there may be data in
+ *     the receive buffer what was received with a parity error.
+ * - 0b1 - At least one dataword was received with a parity error since the last
+ *     time this flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_PF field. */
+#define UART_RD_S1_PF(base)  ((UART_S1_REG(base) & UART_S1_PF_MASK) >> UART_S1_PF_SHIFT)
+#define UART_BRD_S1_PF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_PF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field FE[1] (RO)
+ *
+ * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
+ * then FE will set when a logic 0 is accepted for either of the two stop bits.
+ * FE does not set in the case of an overrun or while the LIN break detect feature
+ * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
+ * cleared. To clear FE, read S1 with FE set and then read D. The last data in the
+ * receive buffer represents the data that was received with the frame error
+ * enabled. Framing errors are not supported when 7816E is set/enabled. However, if
+ * this flag is set, data is still not received in 7816 mode.
+ *
+ * Values:
+ * - 0b0 - No framing error detected.
+ * - 0b1 - Framing error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_FE field. */
+#define UART_RD_S1_FE(base)  ((UART_S1_REG(base) & UART_S1_FE_MASK) >> UART_S1_FE_SHIFT)
+#define UART_BRD_S1_FE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_FE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field NF[2] (RO)
+ *
+ * NF is set when the UART detects noise on the receiver input. NF does not
+ * become set in the case of an overrun or while the LIN break detect feature is
+ * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
+ * been received with noise since the last time it was cleared. There is no
+ * guarantee that the first dataword read from the receive buffer has noise or that there
+ * is only one dataword in the buffer that was received with noise unless the
+ * receive buffer has a depth of one. To clear NF, read S1 and then read D.
+ *
+ * Values:
+ * - 0b0 - No noise detected since the last time this flag was cleared. If the
+ *     receive buffer has a depth greater than 1 then there may be data in the
+ *     receiver buffer that was received with noise.
+ * - 0b1 - At least one dataword was received with noise detected since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_NF field. */
+#define UART_RD_S1_NF(base)  ((UART_S1_REG(base) & UART_S1_NF_MASK) >> UART_S1_NF_SHIFT)
+#define UART_BRD_S1_NF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_NF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field OR[3] (RO)
+ *
+ * OR is set when software fails to prevent the receive data register from
+ * overflowing with data. The OR bit is set immediately after the stop bit has been
+ * completely received for the dataword that overflows the buffer and all the other
+ * error flags (FE, NF, and PF) are prevented from setting. The data in the
+ * shift register is lost, but the data already in the UART data registers is not
+ * affected. If the OR flag is set, no data is stored in the data buffer even if
+ * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
+ * flags are blocked from asserting, that is, transition from an inactive to an
+ * active state. To clear OR, read S1 when OR is set and then read D. See
+ * functional description for more details regarding the operation of the OR bit.If
+ * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
+ * is not cleared before the next data character is received. In 7816 mode, it is
+ * possible to configure a NACK to be returned by programing C7816[ONACK].
+ *
+ * Values:
+ * - 0b0 - No overrun has occurred since the last time the flag was cleared.
+ * - 0b1 - Overrun has occurred or the overrun flag has not been cleared since
+ *     the last overrun occured.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_OR field. */
+#define UART_RD_S1_OR(base)  ((UART_S1_REG(base) & UART_S1_OR_MASK) >> UART_S1_OR_SHIFT)
+#define UART_BRD_S1_OR(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_OR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field IDLE[4] (RO)
+ *
+ * After the IDLE flag is cleared, a frame must be received (although not
+ * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
+ * break character must set the S2[LBKDIF] flag before an idle condition can set the
+ * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
+ * IDLE is set when either of the following appear on the receiver input: 10
+ * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
+ * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
+ * detection is not supported when 7816E is set/enabled and hence this flag is
+ * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
+ * flag if RWUID is set, else the IDLE flag does not become set.
+ *
+ * Values:
+ * - 0b0 - Receiver input is either active now or has never become active since
+ *     the IDLE flag was last cleared.
+ * - 0b1 - Receiver input has become idle or the flag has not been cleared since
+ *     it last asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_IDLE field. */
+#define UART_RD_S1_IDLE(base) ((UART_S1_REG(base) & UART_S1_IDLE_MASK) >> UART_S1_IDLE_SHIFT)
+#define UART_BRD_S1_IDLE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field RDRF[5] (RO)
+ *
+ * RDRF is set when the number of datawords in the receive buffer is equal to or
+ * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
+ * process of being received is not included in the count. To clear RDRF, read S1
+ * when RDRF is set and then read D. For more efficient interrupt and DMA
+ * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
+ * Then read S1 and the final data value, resulting in the clearing of the RDRF
+ * flag. Even if RDRF is set, data will continue to be received until an overrun
+ * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
+ * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
+ * buffer but over-write each other.
+ *
+ * Values:
+ * - 0b0 - The number of datawords in the receive buffer is less than the number
+ *     indicated by RXWATER.
+ * - 0b1 - The number of datawords in the receive buffer is equal to or greater
+ *     than the number indicated by RXWATER at some point in time since this flag
+ *     was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_RDRF field. */
+#define UART_RD_S1_RDRF(base) ((UART_S1_REG(base) & UART_S1_RDRF_MASK) >> UART_S1_RDRF_SHIFT)
+#define UART_BRD_S1_RDRF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_RDRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TC[6] (RO)
+ *
+ * TC is set when the transmit buffer is empty and no data, preamble, or break
+ * character is being transmitted. When TC is set, the transmit data output signal
+ * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
+ * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
+ * set after any NACK signal has been received, but prior to any corresponding
+ * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
+ * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
+ * in C2.
+ *
+ * Values:
+ * - 0b0 - Transmitter active (sending data, a preamble, or a break).
+ * - 0b1 - Transmitter idle (transmission activity complete).
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TC field. */
+#define UART_RD_S1_TC(base)  ((UART_S1_REG(base) & UART_S1_TC_MASK) >> UART_S1_TC_SHIFT)
+#define UART_BRD_S1_TC(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_TC_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TDRE[7] (RO)
+ *
+ * TDRE will set when the number of datawords in the transmit buffer (D and
+ * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
+ * character that is in the process of being transmitted is not included in the count.
+ * To clear TDRE, read S1 when TDRE is set and then write to the UART data
+ * register (D). For more efficient interrupt servicing, all data except the final value
+ * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
+ * before writing the final data value, resulting in the clearing of the TRDE
+ * flag. This is more efficient because the TDRE reasserts until the watermark has
+ * been exceeded. So, attempting to clear the TDRE with every write will be
+ * ineffective until sufficient data has been written.
+ *
+ * Values:
+ * - 0b0 - The amount of data in the transmit buffer is greater than the value
+ *     indicated by TWFIFO[TXWATER].
+ * - 0b1 - The amount of data in the transmit buffer is less than or equal to
+ *     the value indicated by TWFIFO[TXWATER] at some point in time since the flag
+ *     has been cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TDRE field. */
+#define UART_RD_S1_TDRE(base) ((UART_S1_REG(base) & UART_S1_TDRE_MASK) >> UART_S1_TDRE_SHIFT)
+#define UART_BRD_S1_TDRE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_TDRE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S2 - UART Status Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S2 - UART Status Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The S2 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. Also, this register can be polled by the MCU to check the
+ * status of these bits. This register can be read or written at any time, with the
+ * exception of the MSBF and RXINV bits, which should be changed by the user only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_S2 register
+ */
+/*@{*/
+#define UART_RD_S2(base)         (UART_S2_REG(base))
+#define UART_WR_S2(base, value)  (UART_S2_REG(base) = (value))
+#define UART_RMW_S2(base, mask, value) (UART_WR_S2(base, (UART_RD_S2(base) & ~(mask)) | (value)))
+#define UART_SET_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) |  (value)))
+#define UART_CLR_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) & ~(value)))
+#define UART_TOG_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S2 bitfields
+ */
+
+/*!
+ * @name Register UART_S2, field RAF[0] (RO)
+ *
+ * RAF is set when the UART receiver detects a logic 0 during the RT1 time
+ * period of the start bit search. RAF is cleared when the receiver detects an idle
+ * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
+ * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
+ * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
+ * to configure the guard time to 12. However, if a NACK is required to be
+ * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
+ * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
+ * prior to actually being inactive.
+ *
+ * Values:
+ * - 0b0 - UART receiver idle/inactive waiting for a start bit.
+ * - 0b1 - UART receiver active, RxD input not idle.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RAF field. */
+#define UART_RD_S2_RAF(base) ((UART_S2_REG(base) & UART_S2_RAF_MASK) >> UART_S2_RAF_SHIFT)
+#define UART_BRD_S2_RAF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RAF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field LBKDE[1] (RW)
+ *
+ * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
+ * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
+ * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
+ *
+ * Values:
+ * - 0b0 - Break character detection is disabled.
+ * - 0b1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
+ *     12 bits time if C1[M] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_LBKDE field. */
+#define UART_RD_S2_LBKDE(base) ((UART_S2_REG(base) & UART_S2_LBKDE_MASK) >> UART_S2_LBKDE_SHIFT)
+#define UART_BRD_S2_LBKDE(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDE_SHIFT))
+
+/*! @brief Set the LBKDE field to a new value. */
+#define UART_WR_S2_LBKDE(base, value) (UART_RMW_S2(base, (UART_S2_LBKDE_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_LBKDE(value)))
+#define UART_BWR_S2_LBKDE(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field BRK13[2] (RW)
+ *
+ * Determines whether the transmit break character is 10, 11, or 12 bits long,
+ * or 13 or 14 bits long. See for the length of the break character for the
+ * different configurations. The detection of a framing error is not affected by this
+ * field. Transmitting break characters
+ *
+ * Values:
+ * - 0b0 - Break character is 10, 11, or 12 bits long.
+ * - 0b1 - Break character is 13 or 14 bits long.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_BRK13 field. */
+#define UART_RD_S2_BRK13(base) ((UART_S2_REG(base) & UART_S2_BRK13_MASK) >> UART_S2_BRK13_SHIFT)
+#define UART_BRD_S2_BRK13(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT))
+
+/*! @brief Set the BRK13 field to a new value. */
+#define UART_WR_S2_BRK13(base, value) (UART_RMW_S2(base, (UART_S2_BRK13_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_BRK13(value)))
+#define UART_BWR_S2_BRK13(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RWUID[3] (RW)
+ *
+ * When RWU is set and WAKE is cleared, this field controls whether the idle
+ * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - S1[IDLE] is not set upon detection of an idle character.
+ * - 0b1 - S1[IDLE] is set upon detection of an idle character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RWUID field. */
+#define UART_RD_S2_RWUID(base) ((UART_S2_REG(base) & UART_S2_RWUID_MASK) >> UART_S2_RWUID_SHIFT)
+#define UART_BRD_S2_RWUID(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT))
+
+/*! @brief Set the RWUID field to a new value. */
+#define UART_WR_S2_RWUID(base, value) (UART_RMW_S2(base, (UART_S2_RWUID_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RWUID(value)))
+#define UART_BWR_S2_RWUID(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the received data input. In NRZ
+ * format, a one is represented by a mark and a zero is represented by a space for
+ * normal polarity, and the opposite for inverted polarity. In IrDA format, a
+ * zero is represented by short high pulse in the middle of a bit time remaining
+ * idle low for a one for normal polarity. A zero is represented by a short low
+ * pulse in the middle of a bit time remaining idle high for a one for inverted
+ * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
+ * enabled and an initial character is detected in T = 0 protocol mode. Setting
+ * RXINV inverts the RxD input for data bits, start and stop bits, break, and
+ * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
+ * are inverted.
+ *
+ * Values:
+ * - 0b0 - Receive data is not inverted.
+ * - 0b1 - Receive data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXINV field. */
+#define UART_RD_S2_RXINV(base) ((UART_S2_REG(base) & UART_S2_RXINV_MASK) >> UART_S2_RXINV_SHIFT)
+#define UART_BRD_S2_RXINV(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT))
+
+/*! @brief Set the RXINV field to a new value. */
+#define UART_WR_S2_RXINV(base, value) (UART_RMW_S2(base, (UART_S2_RXINV_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RXINV(value)))
+#define UART_BWR_S2_RXINV(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field MSBF[5] (RW)
+ *
+ * Setting this field reverses the order of the bits that are transmitted and
+ * received on the wire. This field does not affect the polarity of the bits, the
+ * location of the parity bit, or the location of the start or stop bits. This
+ * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
+ * an initial character is detected in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0b0 - LSB (bit0) is the first bit that is transmitted following the start
+ *     bit. Further, the first bit received after the start bit is identified as
+ *     bit0.
+ * - 0b1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted
+ *     following the start bit, depending on the setting of C1[M] and C1[PE]. Further,
+ *     the first bit received after the start bit is identified as bit8, bit7, or
+ *     bit6, depending on the setting of C1[M] and C1[PE].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_MSBF field. */
+#define UART_RD_S2_MSBF(base) ((UART_S2_REG(base) & UART_S2_MSBF_MASK) >> UART_S2_MSBF_SHIFT)
+#define UART_BRD_S2_MSBF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT))
+
+/*! @brief Set the MSBF field to a new value. */
+#define UART_WR_S2_MSBF(base, value) (UART_RMW_S2(base, (UART_S2_MSBF_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_MSBF(value)))
+#define UART_BWR_S2_MSBF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXEDGIF[6] (W1C)
+ *
+ * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
+ * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
+ * to it. See for additional details. RXEDGIF description The active edge is
+ * detected only in two wire mode and on receiving data coming from the RxD pin.
+ *
+ * Values:
+ * - 0b0 - No active edge on the receive pin has occurred.
+ * - 0b1 - An active edge on the receive pin has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXEDGIF field. */
+#define UART_RD_S2_RXEDGIF(base) ((UART_S2_REG(base) & UART_S2_RXEDGIF_MASK) >> UART_S2_RXEDGIF_SHIFT)
+#define UART_BRD_S2_RXEDGIF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT))
+
+/*! @brief Set the RXEDGIF field to a new value. */
+#define UART_WR_S2_RXEDGIF(base, value) (UART_RMW_S2(base, (UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RXEDGIF(value)))
+#define UART_BWR_S2_RXEDGIF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field LBKDIF[7] (W1C)
+ *
+ * LBKDIF is set when LBKDE is set and a LIN break character is detected on the
+ * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
+ * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
+ * last LIN break character. LBKDIF is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - No LIN break character detected.
+ * - 0b1 - LIN break character detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_LBKDIF field. */
+#define UART_RD_S2_LBKDIF(base) ((UART_S2_REG(base) & UART_S2_LBKDIF_MASK) >> UART_S2_LBKDIF_SHIFT)
+#define UART_BRD_S2_LBKDIF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDIF_SHIFT))
+
+/*! @brief Set the LBKDIF field to a new value. */
+#define UART_WR_S2_LBKDIF(base, value) (UART_RMW_S2(base, (UART_S2_LBKDIF_MASK | UART_S2_RXEDGIF_MASK), UART_S2_LBKDIF(value)))
+#define UART_BWR_S2_LBKDIF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDIF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C3 - UART Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C3 - UART Control Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_C3 register
+ */
+/*@{*/
+#define UART_RD_C3(base)         (UART_C3_REG(base))
+#define UART_WR_C3(base, value)  (UART_C3_REG(base) = (value))
+#define UART_RMW_C3(base, mask, value) (UART_WR_C3(base, (UART_RD_C3(base) & ~(mask)) | (value)))
+#define UART_SET_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) |  (value)))
+#define UART_CLR_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) & ~(value)))
+#define UART_TOG_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C3 bitfields
+ */
+
+/*!
+ * @name Register UART_C3, field PEIE[0] (RW)
+ *
+ * Enables the parity error flag, S1[PF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - PF interrupt requests are disabled.
+ * - 0b1 - PF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_PEIE field. */
+#define UART_RD_C3_PEIE(base) ((UART_C3_REG(base) & UART_C3_PEIE_MASK) >> UART_C3_PEIE_SHIFT)
+#define UART_BRD_C3_PEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT))
+
+/*! @brief Set the PEIE field to a new value. */
+#define UART_WR_C3_PEIE(base, value) (UART_RMW_C3(base, UART_C3_PEIE_MASK, UART_C3_PEIE(value)))
+#define UART_BWR_C3_PEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field FEIE[1] (RW)
+ *
+ * Enables the framing error flag, S1[FE], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - FE interrupt requests are disabled.
+ * - 0b1 - FE interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_FEIE field. */
+#define UART_RD_C3_FEIE(base) ((UART_C3_REG(base) & UART_C3_FEIE_MASK) >> UART_C3_FEIE_SHIFT)
+#define UART_BRD_C3_FEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define UART_WR_C3_FEIE(base, value) (UART_RMW_C3(base, UART_C3_FEIE_MASK, UART_C3_FEIE(value)))
+#define UART_BWR_C3_FEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field NEIE[2] (RW)
+ *
+ * Enables the noise flag, S1[NF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - NF interrupt requests are disabled.
+ * - 0b1 - NF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_NEIE field. */
+#define UART_RD_C3_NEIE(base) ((UART_C3_REG(base) & UART_C3_NEIE_MASK) >> UART_C3_NEIE_SHIFT)
+#define UART_BRD_C3_NEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT))
+
+/*! @brief Set the NEIE field to a new value. */
+#define UART_WR_C3_NEIE(base, value) (UART_RMW_C3(base, UART_C3_NEIE_MASK, UART_C3_NEIE(value)))
+#define UART_BWR_C3_NEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field ORIE[3] (RW)
+ *
+ * Enables the overrun error flag, S1[OR], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - OR interrupts are disabled.
+ * - 0b1 - OR interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_ORIE field. */
+#define UART_RD_C3_ORIE(base) ((UART_C3_REG(base) & UART_C3_ORIE_MASK) >> UART_C3_ORIE_SHIFT)
+#define UART_BRD_C3_ORIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT))
+
+/*! @brief Set the ORIE field to a new value. */
+#define UART_WR_C3_ORIE(base, value) (UART_RMW_C3(base, UART_C3_ORIE_MASK, UART_C3_ORIE(value)))
+#define UART_BWR_C3_ORIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the transmitted data output. In
+ * NRZ format, a one is represented by a mark and a zero is represented by a space
+ * for normal polarity, and the opposite for inverted polarity. In IrDA format,
+ * a zero is represented by short high pulse in the middle of a bit time
+ * remaining idle low for a one for normal polarity, and a zero is represented by short
+ * low pulse in the middle of a bit time remaining idle high for a one for
+ * inverted polarity. This field is automatically set when C7816[INIT] and
+ * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
+ * Setting TXINV inverts all transmitted values, including idle, break, start, and
+ * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
+ * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
+ * the transmitted data bits and parity bit are inverted.
+ *
+ * Values:
+ * - 0b0 - Transmit data is not inverted.
+ * - 0b1 - Transmit data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXINV field. */
+#define UART_RD_C3_TXINV(base) ((UART_C3_REG(base) & UART_C3_TXINV_MASK) >> UART_C3_TXINV_SHIFT)
+#define UART_BRD_C3_TXINV(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT))
+
+/*! @brief Set the TXINV field to a new value. */
+#define UART_WR_C3_TXINV(base, value) (UART_RMW_C3(base, UART_C3_TXINV_MASK, UART_C3_TXINV(value)))
+#define UART_BWR_C3_TXINV(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXDIR[5] (RW)
+ *
+ * Determines whether the TXD pin is used as an input or output in the
+ * single-wire mode of operation. This field is relevant only to the single wire mode.
+ * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
+ * automatically cleared after the requested block is transmitted. This condition is
+ * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
+ * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
+ * being transmitted, the hardware automatically overrides this field as needed. In
+ * this situation, TXDIR does not reflect the temporary state associated with
+ * the NACK.
+ *
+ * Values:
+ * - 0b0 - TXD pin is an input in single wire mode.
+ * - 0b1 - TXD pin is an output in single wire mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXDIR field. */
+#define UART_RD_C3_TXDIR(base) ((UART_C3_REG(base) & UART_C3_TXDIR_MASK) >> UART_C3_TXDIR_SHIFT)
+#define UART_BRD_C3_TXDIR(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT))
+
+/*! @brief Set the TXDIR field to a new value. */
+#define UART_WR_C3_TXDIR(base, value) (UART_RMW_C3(base, UART_C3_TXDIR_MASK, UART_C3_TXDIR(value)))
+#define UART_BWR_C3_TXDIR(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field T8[6] (RW)
+ *
+ * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
+ * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
+ * same as in the previous transmission, T8 does not have to be rewritten. The same
+ * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
+ * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
+ * the remaining data.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_T8 field. */
+#define UART_RD_C3_T8(base)  ((UART_C3_REG(base) & UART_C3_T8_MASK) >> UART_C3_T8_SHIFT)
+#define UART_BRD_C3_T8(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_T8_SHIFT))
+
+/*! @brief Set the T8 field to a new value. */
+#define UART_WR_C3_T8(base, value) (UART_RMW_C3(base, UART_C3_T8_MASK, UART_C3_T8(value)))
+#define UART_BWR_C3_T8(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_T8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field R8[7] (RO)
+ *
+ * R8 is the ninth data bit received when the UART is configured for 9-bit data
+ * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
+ * current data value in the UARTx_D register. To read the 9th bit, read the
+ * value of UARTx_C3[R8], then read the UARTx_D register.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_R8 field. */
+#define UART_RD_C3_R8(base)  ((UART_C3_REG(base) & UART_C3_R8_MASK) >> UART_C3_R8_SHIFT)
+#define UART_BRD_C3_R8(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_R8_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_D - UART Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_D - UART Data Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is actually two separate registers. Reads return the contents
+ * of the read-only receive data register and writes go to the write-only transmit
+ * data register. In 8-bit or 9-bit data format, only UART data register (D)
+ * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
+ * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
+ * register, only if the ninth bit of data needs to be captured. Similarly, the
+ * ED register needs to be read, prior to the D register, only if the additional
+ * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
+ * bit cleared) if the parity is enabled, you get seven data bits and one parity
+ * bit. That one parity bit is loaded into the D register. So, for the data bits,
+ * mask off the parity bit from the value you read out of this register. When
+ * transmitting in 9-bit data format and using 8-bit write instructions, write first
+ * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
+ * C3[T8] stores the data in a temporary register. If D register is written first,
+ * and then the new data on data bus is stored in D, the temporary value written by
+ * the last write to C3[T8] gets stored in the C3[T8] register.
+ */
+/*!
+ * @name Constants and macros for entire UART_D register
+ */
+/*@{*/
+#define UART_RD_D(base)          (UART_D_REG(base))
+#define UART_WR_D(base, value)   (UART_D_REG(base) = (value))
+#define UART_RMW_D(base, mask, value) (UART_WR_D(base, (UART_RD_D(base) & ~(mask)) | (value)))
+#define UART_SET_D(base, value)  (UART_WR_D(base, UART_RD_D(base) |  (value)))
+#define UART_CLR_D(base, value)  (UART_WR_D(base, UART_RD_D(base) & ~(value)))
+#define UART_TOG_D(base, value)  (UART_WR_D(base, UART_RD_D(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA1 - UART Match Address Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA1 - UART Match Address Registers 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MA1 and MA2 registers are compared to input data addresses when the most
+ * significant bit is set and the associated C4[MAEN] field is set. If a match
+ * occurs, the following data is transferred to the data register. If a match
+ * fails, the following data is discarded. These registers can be read and written at
+ * anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA1 register
+ */
+/*@{*/
+#define UART_RD_MA1(base)        (UART_MA1_REG(base))
+#define UART_WR_MA1(base, value) (UART_MA1_REG(base) = (value))
+#define UART_RMW_MA1(base, mask, value) (UART_WR_MA1(base, (UART_RD_MA1(base) & ~(mask)) | (value)))
+#define UART_SET_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) |  (value)))
+#define UART_CLR_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) & ~(value)))
+#define UART_TOG_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA2 - UART Match Address Registers 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA2 - UART Match Address Registers 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * These registers can be read and written at anytime. The MA1 and MA2 registers
+ * are compared to input data addresses when the most significant bit is set and
+ * the associated C4[MAEN] field is set. If a match occurs, the following data
+ * is transferred to the data register. If a match fails, the following data is
+ * discarded.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA2 register
+ */
+/*@{*/
+#define UART_RD_MA2(base)        (UART_MA2_REG(base))
+#define UART_WR_MA2(base, value) (UART_MA2_REG(base) = (value))
+#define UART_RMW_MA2(base, mask, value) (UART_WR_MA2(base, (UART_RD_MA2(base) & ~(mask)) | (value)))
+#define UART_SET_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) |  (value)))
+#define UART_CLR_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) & ~(value)))
+#define UART_TOG_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C4 - UART Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C4 - UART Control Register 4 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C4 register
+ */
+/*@{*/
+#define UART_RD_C4(base)         (UART_C4_REG(base))
+#define UART_WR_C4(base, value)  (UART_C4_REG(base) = (value))
+#define UART_RMW_C4(base, mask, value) (UART_WR_C4(base, (UART_RD_C4(base) & ~(mask)) | (value)))
+#define UART_SET_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) |  (value)))
+#define UART_CLR_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) & ~(value)))
+#define UART_TOG_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C4 bitfields
+ */
+
+/*!
+ * @name Register UART_C4, field BRFA[4:0] (RW)
+ *
+ * This bit field is used to add more timing resolution to the average baud
+ * frequency, in increments of 1/32. See Baud rate generation for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_BRFA field. */
+#define UART_RD_C4_BRFA(base) ((UART_C4_REG(base) & UART_C4_BRFA_MASK) >> UART_C4_BRFA_SHIFT)
+#define UART_BRD_C4_BRFA(base) (UART_RD_C4_BRFA(base))
+
+/*! @brief Set the BRFA field to a new value. */
+#define UART_WR_C4_BRFA(base, value) (UART_RMW_C4(base, UART_C4_BRFA_MASK, UART_C4_BRFA(value)))
+#define UART_BWR_C4_BRFA(base, value) (UART_WR_C4_BRFA(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field M10[5] (RW)
+ *
+ * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
+ * This tenth bit is generated and interpreted as a parity bit. The M10 field
+ * does not affect the LIN send or detect break behavior. If M10 is set, then both
+ * C1[M] and C1[PE] must also be set. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
+ *
+ * Values:
+ * - 0b0 - The parity bit is the ninth bit in the serial transmission.
+ * - 0b1 - The parity bit is the tenth bit in the serial transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_M10 field. */
+#define UART_RD_C4_M10(base) ((UART_C4_REG(base) & UART_C4_M10_MASK) >> UART_C4_M10_SHIFT)
+#define UART_BRD_C4_M10(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_M10_SHIFT))
+
+/*! @brief Set the M10 field to a new value. */
+#define UART_WR_C4_M10(base, value) (UART_RMW_C4(base, UART_C4_M10_MASK, UART_C4_M10(value)))
+#define UART_BWR_C4_M10(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_M10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN2[6] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0b0 - All data received is transferred to the data buffer if MAEN1 is
+ *     cleared.
+ * - 0b1 - All data received with the most significant bit cleared, is
+ *     discarded. All data received with the most significant bit set, is compared with
+ *     contents of MA2 register. If no match occurs, the data is discarded. If a
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN2 field. */
+#define UART_RD_C4_MAEN2(base) ((UART_C4_REG(base) & UART_C4_MAEN2_MASK) >> UART_C4_MAEN2_SHIFT)
+#define UART_BRD_C4_MAEN2(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT))
+
+/*! @brief Set the MAEN2 field to a new value. */
+#define UART_WR_C4_MAEN2(base, value) (UART_RMW_C4(base, UART_C4_MAEN2_MASK, UART_C4_MAEN2(value)))
+#define UART_BWR_C4_MAEN2(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN1[7] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0b0 - All data received is transferred to the data buffer if MAEN2 is
+ *     cleared.
+ * - 0b1 - All data received with the most significant bit cleared, is
+ *     discarded. All data received with the most significant bit set, is compared with
+ *     contents of MA1 register. If no match occurs, the data is discarded. If
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN1 field. */
+#define UART_RD_C4_MAEN1(base) ((UART_C4_REG(base) & UART_C4_MAEN1_MASK) >> UART_C4_MAEN1_SHIFT)
+#define UART_BRD_C4_MAEN1(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT))
+
+/*! @brief Set the MAEN1 field to a new value. */
+#define UART_WR_C4_MAEN1(base, value) (UART_RMW_C4(base, UART_C4_MAEN1_MASK, UART_C4_MAEN1(value)))
+#define UART_BWR_C4_MAEN1(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C5 - UART Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C5 - UART Control Register 5 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C5 register
+ */
+/*@{*/
+#define UART_RD_C5(base)         (UART_C5_REG(base))
+#define UART_WR_C5(base, value)  (UART_C5_REG(base) = (value))
+#define UART_RMW_C5(base, mask, value) (UART_WR_C5(base, (UART_RD_C5(base) & ~(mask)) | (value)))
+#define UART_SET_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) |  (value)))
+#define UART_CLR_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) & ~(value)))
+#define UART_TOG_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C5 bitfields
+ */
+
+/*!
+ * @name Register UART_C5, field LBKDDMAS[3] (RW)
+ *
+ * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
+ * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
+ * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
+ * of the state of LBKDDMAS.
+ *
+ * Values:
+ * - 0b0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
+ *     asserted to request an interrupt service.
+ * - 0b1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal
+ *     is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_LBKDDMAS field. */
+#define UART_RD_C5_LBKDDMAS(base) ((UART_C5_REG(base) & UART_C5_LBKDDMAS_MASK) >> UART_C5_LBKDDMAS_SHIFT)
+#define UART_BRD_C5_LBKDDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_LBKDDMAS_SHIFT))
+
+/*! @brief Set the LBKDDMAS field to a new value. */
+#define UART_WR_C5_LBKDDMAS(base, value) (UART_RMW_C5(base, UART_C5_LBKDDMAS_MASK, UART_C5_LBKDDMAS(value)))
+#define UART_BWR_C5_LBKDDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_LBKDDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field ILDMAS[4] (RW)
+ *
+ * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
+ * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
+ * DMA and IDLE interrupt request signals are not asserted, regardless of the state
+ * of ILDMAS.
+ *
+ * Values:
+ * - 0b0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal
+ *     is asserted to request an interrupt service.
+ * - 0b1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_ILDMAS field. */
+#define UART_RD_C5_ILDMAS(base) ((UART_C5_REG(base) & UART_C5_ILDMAS_MASK) >> UART_C5_ILDMAS_SHIFT)
+#define UART_BRD_C5_ILDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_ILDMAS_SHIFT))
+
+/*! @brief Set the ILDMAS field to a new value. */
+#define UART_WR_C5_ILDMAS(base, value) (UART_RMW_C5(base, UART_C5_ILDMAS_MASK, UART_C5_ILDMAS(value)))
+#define UART_BWR_C5_ILDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_ILDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field RDMAS[5] (RW)
+ *
+ * Configures the receiver data register full flag, S1[RDRF], to generate
+ * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
+ * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
+ * regardless of the state of RDMAS.
+ *
+ * Values:
+ * - 0b0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
+ *     asserted to request an interrupt service.
+ * - 0b1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_RDMAS field. */
+#define UART_RD_C5_RDMAS(base) ((UART_C5_REG(base) & UART_C5_RDMAS_MASK) >> UART_C5_RDMAS_SHIFT)
+#define UART_BRD_C5_RDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT))
+
+/*! @brief Set the RDMAS field to a new value. */
+#define UART_WR_C5_RDMAS(base, value) (UART_RMW_C5(base, UART_C5_RDMAS_MASK, UART_C5_RDMAS(value)))
+#define UART_BWR_C5_RDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TCDMAS[6] (RW)
+ *
+ * Configures the transmission complete flag, S1[TC], to generate interrupt or
+ * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
+ * interrupt request signals are not asserted when the S1[TC] flag is set, regardless
+ * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
+ * must be cleared, and D must not be written unless a DMA request is being serviced.
+ *
+ * Values:
+ * - 0b0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt
+ *     request signal is asserted to request an interrupt service.
+ * - 0b1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TCDMAS field. */
+#define UART_RD_C5_TCDMAS(base) ((UART_C5_REG(base) & UART_C5_TCDMAS_MASK) >> UART_C5_TCDMAS_SHIFT)
+#define UART_BRD_C5_TCDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TCDMAS_SHIFT))
+
+/*! @brief Set the TCDMAS field to a new value. */
+#define UART_WR_C5_TCDMAS(base, value) (UART_RMW_C5(base, UART_C5_TCDMAS_MASK, UART_C5_TCDMAS(value)))
+#define UART_BWR_C5_TCDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TCDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TDMAS[7] (RW)
+ *
+ * Configures the transmit data register empty flag, S1[TDRE], to generate
+ * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
+ * TDRE interrupt request signals are not asserted when the TDRE flag is set,
+ * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
+ * must be cleared, and D must not be written unless a DMA request is being
+ * serviced.
+ *
+ * Values:
+ * - 0b0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
+ *     request signal is asserted to request interrupt service.
+ * - 0b1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TDMAS field. */
+#define UART_RD_C5_TDMAS(base) ((UART_C5_REG(base) & UART_C5_TDMAS_MASK) >> UART_C5_TDMAS_SHIFT)
+#define UART_BRD_C5_TDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT))
+
+/*! @brief Set the TDMAS field to a new value. */
+#define UART_WR_C5_TDMAS(base, value) (UART_RMW_C5(base, UART_C5_TDMAS_MASK, UART_C5_TDMAS(value)))
+#define UART_BWR_C5_TDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ED - UART Extended Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ED - UART Extended Data Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains additional information flags that are stored with a
+ * received dataword. This register may be read at any time but contains valid data
+ * only if there is a dataword in the receive FIFO. The data contained in this
+ * register represents additional information regarding the conditions on which a
+ * dataword was received. The importance of this data varies with the
+ * application, and in some cases maybe completely optional. These fields automatically
+ * update to reflect the conditions of the next dataword whenever D is read. If
+ * S1[NF] and S1[PF] have not been set since the last time the receive buffer was
+ * empty, the NOISY and PARITYE fields will be zero.
+ */
+/*!
+ * @name Constants and macros for entire UART_ED register
+ */
+/*@{*/
+#define UART_RD_ED(base)         (UART_ED_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ED bitfields
+ */
+
+/*!
+ * @name Register UART_ED, field PARITYE[6] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with a
+ * parity error.
+ *
+ * Values:
+ * - 0b0 - The dataword was received without a parity error.
+ * - 0b1 - The dataword was received with a parity error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ED_PARITYE field. */
+#define UART_RD_ED_PARITYE(base) ((UART_ED_REG(base) & UART_ED_PARITYE_MASK) >> UART_ED_PARITYE_SHIFT)
+#define UART_BRD_ED_PARITYE(base) (BITBAND_ACCESS8(&UART_ED_REG(base), UART_ED_PARITYE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_ED, field NOISY[7] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with
+ * noise.
+ *
+ * Values:
+ * - 0b0 - The dataword was received without noise.
+ * - 0b1 - The data was received with noise.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ED_NOISY field. */
+#define UART_RD_ED_NOISY(base) ((UART_ED_REG(base) & UART_ED_NOISY_MASK) >> UART_ED_NOISY_SHIFT)
+#define UART_BRD_ED_NOISY(base) (BITBAND_ACCESS8(&UART_ED_REG(base), UART_ED_NOISY_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MODEM - UART Modem Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MODEM - UART Modem Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MODEM register controls options for setting the modem configuration.
+ * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
+ * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
+ * ISO-7816 protocol does not use the RTS and CTS signals.
+ */
+/*!
+ * @name Constants and macros for entire UART_MODEM register
+ */
+/*@{*/
+#define UART_RD_MODEM(base)      (UART_MODEM_REG(base))
+#define UART_WR_MODEM(base, value) (UART_MODEM_REG(base) = (value))
+#define UART_RMW_MODEM(base, mask, value) (UART_WR_MODEM(base, (UART_RD_MODEM(base) & ~(mask)) | (value)))
+#define UART_SET_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) |  (value)))
+#define UART_CLR_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) & ~(value)))
+#define UART_TOG_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_MODEM bitfields
+ */
+
+/*!
+ * @name Register UART_MODEM, field TXCTSE[0] (RW)
+ *
+ * TXCTSE controls the operation of the transmitter. TXCTSE can be set
+ * independently from the state of TXRTSE and RXRTSE.
+ *
+ * Values:
+ * - 0b0 - CTS has no effect on the transmitter.
+ * - 0b1 - Enables clear-to-send operation. The transmitter checks the state of
+ *     CTS each time it is ready to send a character. If CTS is asserted, the
+ *     character is sent. If CTS is deasserted, the signal TXD remains in the mark
+ *     state and transmission is delayed until CTS is asserted. Changes in CTS as
+ *     a character is being sent do not affect its transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXCTSE field. */
+#define UART_RD_MODEM_TXCTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_TXCTSE_MASK) >> UART_MODEM_TXCTSE_SHIFT)
+#define UART_BRD_MODEM_TXCTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXCTSE_SHIFT))
+
+/*! @brief Set the TXCTSE field to a new value. */
+#define UART_WR_MODEM_TXCTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXCTSE_MASK, UART_MODEM_TXCTSE(value)))
+#define UART_BWR_MODEM_TXCTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXCTSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field TXRTSE[1] (RW)
+ *
+ * Controls RTS before and after a transmission.
+ *
+ * Values:
+ * - 0b0 - The transmitter has no effect on RTS.
+ * - 0b1 - When a character is placed into an empty transmitter data buffer ,
+ *     RTS asserts one bit time before the start bit is transmitted. RTS deasserts
+ *     one bit time after all characters in the transmitter data buffer and shift
+ *     register are completely sent, including the last stop bit. (FIFO) (FIFO)
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXRTSE field. */
+#define UART_RD_MODEM_TXRTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_TXRTSE_MASK) >> UART_MODEM_TXRTSE_SHIFT)
+#define UART_BRD_MODEM_TXRTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSE_SHIFT))
+
+/*! @brief Set the TXRTSE field to a new value. */
+#define UART_WR_MODEM_TXRTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXRTSE_MASK, UART_MODEM_TXRTSE(value)))
+#define UART_BWR_MODEM_TXRTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field TXRTSPOL[2] (RW)
+ *
+ * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
+ * polarity of the receiver RTS. RTS will remain negated in the active low state
+ * unless TXRTSE is set.
+ *
+ * Values:
+ * - 0b0 - Transmitter RTS is active low.
+ * - 0b1 - Transmitter RTS is active high.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXRTSPOL field. */
+#define UART_RD_MODEM_TXRTSPOL(base) ((UART_MODEM_REG(base) & UART_MODEM_TXRTSPOL_MASK) >> UART_MODEM_TXRTSPOL_SHIFT)
+#define UART_BRD_MODEM_TXRTSPOL(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSPOL_SHIFT))
+
+/*! @brief Set the TXRTSPOL field to a new value. */
+#define UART_WR_MODEM_TXRTSPOL(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXRTSPOL_MASK, UART_MODEM_TXRTSPOL(value)))
+#define UART_BWR_MODEM_TXRTSPOL(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field RXRTSE[3] (RW)
+ *
+ * Allows the RTS output to control the CTS input of the transmitting device to
+ * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
+ *
+ * Values:
+ * - 0b0 - The receiver has no effect on RTS.
+ * - 0b1 - RTS is deasserted if the number of characters in the receiver data
+ *     register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
+ *     when the number of characters in the receiver data register (FIFO) is
+ *     less than RWFIFO[RXWATER].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_RXRTSE field. */
+#define UART_RD_MODEM_RXRTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_RXRTSE_MASK) >> UART_MODEM_RXRTSE_SHIFT)
+#define UART_BRD_MODEM_RXRTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_RXRTSE_SHIFT))
+
+/*! @brief Set the RXRTSE field to a new value. */
+#define UART_WR_MODEM_RXRTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_RXRTSE_MASK, UART_MODEM_RXRTSE(value)))
+#define UART_BWR_MODEM_RXRTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_RXRTSE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IR - UART Infrared Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IR - UART Infrared Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IR register controls options for setting the infrared configuration.
+ */
+/*!
+ * @name Constants and macros for entire UART_IR register
+ */
+/*@{*/
+#define UART_RD_IR(base)         (UART_IR_REG(base))
+#define UART_WR_IR(base, value)  (UART_IR_REG(base) = (value))
+#define UART_RMW_IR(base, mask, value) (UART_WR_IR(base, (UART_RD_IR(base) & ~(mask)) | (value)))
+#define UART_SET_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) |  (value)))
+#define UART_CLR_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) & ~(value)))
+#define UART_TOG_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IR bitfields
+ */
+
+/*!
+ * @name Register UART_IR, field TNP[1:0] (RW)
+ *
+ * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
+ *
+ * Values:
+ * - 0b00 - 3/16.
+ * - 0b01 - 1/16.
+ * - 0b10 - 1/32.
+ * - 0b11 - 1/4.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IR_TNP field. */
+#define UART_RD_IR_TNP(base) ((UART_IR_REG(base) & UART_IR_TNP_MASK) >> UART_IR_TNP_SHIFT)
+#define UART_BRD_IR_TNP(base) (UART_RD_IR_TNP(base))
+
+/*! @brief Set the TNP field to a new value. */
+#define UART_WR_IR_TNP(base, value) (UART_RMW_IR(base, UART_IR_TNP_MASK, UART_IR_TNP(value)))
+#define UART_BWR_IR_TNP(base, value) (UART_WR_IR_TNP(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_IR, field IREN[2] (RW)
+ *
+ * Enables/disables the infrared modulation/demodulation.
+ *
+ * Values:
+ * - 0b0 - IR disabled.
+ * - 0b1 - IR enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IR_IREN field. */
+#define UART_RD_IR_IREN(base) ((UART_IR_REG(base) & UART_IR_IREN_MASK) >> UART_IR_IREN_SHIFT)
+#define UART_BRD_IR_IREN(base) (BITBAND_ACCESS8(&UART_IR_REG(base), UART_IR_IREN_SHIFT))
+
+/*! @brief Set the IREN field to a new value. */
+#define UART_WR_IR_IREN(base, value) (UART_RMW_IR(base, UART_IR_IREN_MASK, UART_IR_IREN(value)))
+#define UART_BWR_IR_IREN(base, value) (BITBAND_ACCESS8(&UART_IR_REG(base), UART_IR_IREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_PFIFO - UART FIFO Parameters
+ ******************************************************************************/
+
+/*!
+ * @brief UART_PFIFO - UART FIFO Parameters (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability for the programmer to turn on and off FIFO
+ * functionality. It also provides the size of the FIFO that has been
+ * implemented. This register may be read at any time. This register must be written only
+ * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
+ * empty.
+ */
+/*!
+ * @name Constants and macros for entire UART_PFIFO register
+ */
+/*@{*/
+#define UART_RD_PFIFO(base)      (UART_PFIFO_REG(base))
+#define UART_WR_PFIFO(base, value) (UART_PFIFO_REG(base) = (value))
+#define UART_RMW_PFIFO(base, mask, value) (UART_WR_PFIFO(base, (UART_RD_PFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) |  (value)))
+#define UART_CLR_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) & ~(value)))
+#define UART_TOG_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_PFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
+ *
+ * The maximum number of receive datawords that can be stored in the receive
+ * buffer before an overrun occurs. This field is read only.
+ *
+ * Values:
+ * - 0b000 - Receive FIFO/Buffer depth = 1 dataword.
+ * - 0b001 - Receive FIFO/Buffer depth = 4 datawords.
+ * - 0b010 - Receive FIFO/Buffer depth = 8 datawords.
+ * - 0b011 - Receive FIFO/Buffer depth = 16 datawords.
+ * - 0b100 - Receive FIFO/Buffer depth = 32 datawords.
+ * - 0b101 - Receive FIFO/Buffer depth = 64 datawords.
+ * - 0b110 - Receive FIFO/Buffer depth = 128 datawords.
+ * - 0b111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. */
+#define UART_RD_PFIFO_RXFIFOSIZE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_RXFIFOSIZE_MASK) >> UART_PFIFO_RXFIFOSIZE_SHIFT)
+#define UART_BRD_PFIFO_RXFIFOSIZE(base) (UART_RD_PFIFO_RXFIFOSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field RXFE[3] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the receive buffer is
+ * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
+ * If this field is not set, the receive buffer operates as a FIFO of depth one
+ * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
+ * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
+ * commands must be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0b0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
+ * - 0b1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_RXFE field. */
+#define UART_RD_PFIFO_RXFE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_RXFE_MASK) >> UART_PFIFO_RXFE_SHIFT)
+#define UART_BRD_PFIFO_RXFE(base) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_RXFE_SHIFT))
+
+/*! @brief Set the RXFE field to a new value. */
+#define UART_WR_PFIFO_RXFE(base, value) (UART_RMW_PFIFO(base, UART_PFIFO_RXFE_MASK, UART_PFIFO_RXFE(value)))
+#define UART_BWR_PFIFO_RXFE(base, value) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_RXFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
+ *
+ * The maximum number of transmit datawords that can be stored in the transmit
+ * buffer. This field is read only.
+ *
+ * Values:
+ * - 0b000 - Transmit FIFO/Buffer depth = 1 dataword.
+ * - 0b001 - Transmit FIFO/Buffer depth = 4 datawords.
+ * - 0b010 - Transmit FIFO/Buffer depth = 8 datawords.
+ * - 0b011 - Transmit FIFO/Buffer depth = 16 datawords.
+ * - 0b100 - Transmit FIFO/Buffer depth = 32 datawords.
+ * - 0b101 - Transmit FIFO/Buffer depth = 64 datawords.
+ * - 0b110 - Transmit FIFO/Buffer depth = 128 datawords.
+ * - 0b111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. */
+#define UART_RD_PFIFO_TXFIFOSIZE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_TXFIFOSIZE_MASK) >> UART_PFIFO_TXFIFOSIZE_SHIFT)
+#define UART_BRD_PFIFO_TXFIFOSIZE(base) (UART_RD_PFIFO_TXFIFOSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field TXFE[7] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the transmit buffer
+ * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
+ * field is not set, the transmit buffer operates as a FIFO of depth one dataword
+ * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
+ * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
+ * be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0b0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
+ * - 0b1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_TXFE field. */
+#define UART_RD_PFIFO_TXFE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_TXFE_MASK) >> UART_PFIFO_TXFE_SHIFT)
+#define UART_BRD_PFIFO_TXFE(base) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_TXFE_SHIFT))
+
+/*! @brief Set the TXFE field to a new value. */
+#define UART_WR_PFIFO_TXFE(base, value) (UART_RMW_PFIFO(base, UART_PFIFO_TXFE_MASK, UART_PFIFO_TXFE(value)))
+#define UART_BWR_PFIFO_TXFE(base, value) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_TXFE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_CFIFO - UART FIFO Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_CFIFO - UART FIFO Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to program various control fields for FIFO
+ * operation. This register may be read or written at any time. Note that
+ * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
+ * to prevent unintended/unpredictable behavior. Therefore, it is recommended that
+ * TE and RE be cleared prior to flushing the corresponding FIFO.
+ */
+/*!
+ * @name Constants and macros for entire UART_CFIFO register
+ */
+/*@{*/
+#define UART_RD_CFIFO(base)      (UART_CFIFO_REG(base))
+#define UART_WR_CFIFO(base, value) (UART_CFIFO_REG(base) = (value))
+#define UART_RMW_CFIFO(base, mask, value) (UART_WR_CFIFO(base, (UART_RD_CFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) |  (value)))
+#define UART_CLR_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) & ~(value)))
+#define UART_TOG_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_CFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_CFIFO, field RXUFE[0] (RW)
+ *
+ * When this field is set, the RXUF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - RXUF flag does not generate an interrupt to the host.
+ * - 0b1 - RXUF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_RXUFE field. */
+#define UART_RD_CFIFO_RXUFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_RXUFE_MASK) >> UART_CFIFO_RXUFE_SHIFT)
+#define UART_BRD_CFIFO_RXUFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXUFE_SHIFT))
+
+/*! @brief Set the RXUFE field to a new value. */
+#define UART_WR_CFIFO_RXUFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXUFE_MASK, UART_CFIFO_RXUFE(value)))
+#define UART_BWR_CFIFO_RXUFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXUFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field TXOFE[1] (RW)
+ *
+ * When this field is set, the TXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - TXOF flag does not generate an interrupt to the host.
+ * - 0b1 - TXOF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_TXOFE field. */
+#define UART_RD_CFIFO_TXOFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_TXOFE_MASK) >> UART_CFIFO_TXOFE_SHIFT)
+#define UART_BRD_CFIFO_TXOFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXOFE_SHIFT))
+
+/*! @brief Set the TXOFE field to a new value. */
+#define UART_WR_CFIFO_TXOFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_TXOFE_MASK, UART_CFIFO_TXOFE(value)))
+#define UART_BWR_CFIFO_TXOFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXOFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field RXOFE[2] (RW)
+ *
+ * When this field is set, the RXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - RXOF flag does not generate an interrupt to the host.
+ * - 0b1 - RXOF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_RXOFE field. */
+#define UART_RD_CFIFO_RXOFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_RXOFE_MASK) >> UART_CFIFO_RXOFE_SHIFT)
+#define UART_BRD_CFIFO_RXOFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXOFE_SHIFT))
+
+/*! @brief Set the RXOFE field to a new value. */
+#define UART_WR_CFIFO_RXOFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXOFE_MASK, UART_CFIFO_RXOFE(value)))
+#define UART_BWR_CFIFO_RXOFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXOFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the receive
+ * FIFO/buffer to be flushed. This does not affect data that is in the receive shift
+ * register.
+ *
+ * Values:
+ * - 0b0 - No flush operation occurs.
+ * - 0b1 - All data in the receive FIFO/buffer is cleared out.
+ */
+/*@{*/
+/*! @brief Set the RXFLUSH field to a new value. */
+#define UART_WR_CFIFO_RXFLUSH(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXFLUSH_MASK, UART_CFIFO_RXFLUSH(value)))
+#define UART_BWR_CFIFO_RXFLUSH(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXFLUSH_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the transmit
+ * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
+ * register.
+ *
+ * Values:
+ * - 0b0 - No flush operation occurs.
+ * - 0b1 - All data in the transmit FIFO/Buffer is cleared out.
+ */
+/*@{*/
+/*! @brief Set the TXFLUSH field to a new value. */
+#define UART_WR_CFIFO_TXFLUSH(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_TXFLUSH_MASK, UART_CFIFO_TXFLUSH(value)))
+#define UART_BWR_CFIFO_TXFLUSH(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXFLUSH_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_SFIFO - UART FIFO Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_SFIFO - UART FIFO Status Register (RW)
+ *
+ * Reset value: 0xC0U
+ *
+ * This register provides status information regarding the transmit and receiver
+ * buffers/FIFOs, including interrupt information. This register may be written
+ * to or read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_SFIFO register
+ */
+/*@{*/
+#define UART_RD_SFIFO(base)      (UART_SFIFO_REG(base))
+#define UART_WR_SFIFO(base, value) (UART_SFIFO_REG(base) = (value))
+#define UART_RMW_SFIFO(base, mask, value) (UART_WR_SFIFO(base, (UART_RD_SFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) |  (value)))
+#define UART_CLR_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) & ~(value)))
+#define UART_TOG_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_SFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_SFIFO, field RXUF[0] (W1C)
+ *
+ * Indicates that more data has been read from the receive buffer than was
+ * present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No receive buffer underflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one receive buffer underflow has occurred since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXUF field. */
+#define UART_RD_SFIFO_RXUF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXUF_MASK) >> UART_SFIFO_RXUF_SHIFT)
+#define UART_BRD_SFIFO_RXUF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXUF_SHIFT))
+
+/*! @brief Set the RXUF field to a new value. */
+#define UART_WR_SFIFO_RXUF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_RXUF_MASK | UART_SFIFO_TXOF_MASK | UART_SFIFO_RXOF_MASK), UART_SFIFO_RXUF(value)))
+#define UART_BWR_SFIFO_RXUF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field TXOF[1] (W1C)
+ *
+ * Indicates that more data has been written to the transmit buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
+ * flag is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No transmit buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one transmit buffer overflow has occurred since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_TXOF field. */
+#define UART_RD_SFIFO_TXOF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_TXOF_MASK) >> UART_SFIFO_TXOF_SHIFT)
+#define UART_BRD_SFIFO_TXOF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXOF_SHIFT))
+
+/*! @brief Set the TXOF field to a new value. */
+#define UART_WR_SFIFO_TXOF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_TXOF_MASK | UART_SFIFO_RXUF_MASK | UART_SFIFO_RXOF_MASK), UART_SFIFO_TXOF(value)))
+#define UART_BWR_SFIFO_TXOF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field RXOF[2] (W1C)
+ *
+ * Indicates that more data has been written to the receive buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No receive buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one receive buffer overflow has occurred since the last time
+ *     the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXOF field. */
+#define UART_RD_SFIFO_RXOF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXOF_MASK) >> UART_SFIFO_RXOF_SHIFT)
+#define UART_BRD_SFIFO_RXOF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXOF_SHIFT))
+
+/*! @brief Set the RXOF field to a new value. */
+#define UART_WR_SFIFO_RXOF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_RXOF_MASK | UART_SFIFO_RXUF_MASK | UART_SFIFO_TXOF_MASK), UART_SFIFO_RXOF(value)))
+#define UART_BWR_SFIFO_RXOF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field RXEMPT[6] (RO)
+ *
+ * Asserts when there is no data in the receive FIFO/Buffer. This field does not
+ * take into account data that is in the receive shift register.
+ *
+ * Values:
+ * - 0b0 - Receive buffer is not empty.
+ * - 0b1 - Receive buffer is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXEMPT field. */
+#define UART_RD_SFIFO_RXEMPT(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXEMPT_MASK) >> UART_SFIFO_RXEMPT_SHIFT)
+#define UART_BRD_SFIFO_RXEMPT(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXEMPT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field TXEMPT[7] (RO)
+ *
+ * Asserts when there is no data in the Transmit FIFO/buffer. This field does
+ * not take into account data that is in the transmit shift register.
+ *
+ * Values:
+ * - 0b0 - Transmit buffer is not empty.
+ * - 0b1 - Transmit buffer is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_TXEMPT field. */
+#define UART_RD_SFIFO_TXEMPT(base) ((UART_SFIFO_REG(base) & UART_SFIFO_TXEMPT_MASK) >> UART_SFIFO_TXEMPT_SHIFT)
+#define UART_BRD_SFIFO_TXEMPT(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXEMPT_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TWFIFO - UART FIFO Transmit Watermark
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TWFIFO - UART FIFO Transmit Watermark (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of needing additional transmit data. This register may be read at any
+ * time but must be written only when C2[TE] is not set. Changing the value of the
+ * watermark will not clear the S1[TDRE] flag.
+ */
+/*!
+ * @name Constants and macros for entire UART_TWFIFO register
+ */
+/*@{*/
+#define UART_RD_TWFIFO(base)     (UART_TWFIFO_REG(base))
+#define UART_WR_TWFIFO(base, value) (UART_TWFIFO_REG(base) = (value))
+#define UART_RMW_TWFIFO(base, mask, value) (UART_WR_TWFIFO(base, (UART_RD_TWFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) |  (value)))
+#define UART_CLR_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) & ~(value)))
+#define UART_TOG_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TCFIFO - UART FIFO Transmit Count
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TCFIFO - UART FIFO Transmit Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the transmit buffer/FIFO. It may be read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_TCFIFO register
+ */
+/*@{*/
+#define UART_RD_TCFIFO(base)     (UART_TCFIFO_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * UART_RWFIFO - UART FIFO Receive Watermark
+ ******************************************************************************/
+
+/*!
+ * @brief UART_RWFIFO - UART FIFO Receive Watermark (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of the need to remove data from the receiver FIFO/buffer. This register
+ * may be read at any time but must be written only when C2[RE] is not asserted.
+ * Changing the value in this register will not clear S1[RDRF].
+ */
+/*!
+ * @name Constants and macros for entire UART_RWFIFO register
+ */
+/*@{*/
+#define UART_RD_RWFIFO(base)     (UART_RWFIFO_REG(base))
+#define UART_WR_RWFIFO(base, value) (UART_RWFIFO_REG(base) = (value))
+#define UART_RMW_RWFIFO(base, mask, value) (UART_WR_RWFIFO(base, (UART_RD_RWFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) |  (value)))
+#define UART_CLR_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) & ~(value)))
+#define UART_TOG_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_RCFIFO - UART FIFO Receive Count
+ ******************************************************************************/
+
+/*!
+ * @brief UART_RCFIFO - UART FIFO Receive Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the receive FIFO/buffer. It may be read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_RCFIFO register
+ */
+/*@{*/
+#define UART_RD_RCFIFO(base)     (UART_RCFIFO_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C7816 - UART 7816 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C7816 - UART 7816 Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The C7816 register is the primary control register for ISO-7816 specific
+ * functionality. This register is specific to 7816 functionality and the values in
+ * this register have no effect on UART operation and should be ignored if
+ * ISO_7816E is not set/enabled. This register may be read at any time but values must
+ * be changed only when ISO_7816E is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_C7816 register
+ */
+/*@{*/
+#define UART_RD_C7816(base)      (UART_C7816_REG(base))
+#define UART_WR_C7816(base, value) (UART_C7816_REG(base) = (value))
+#define UART_RMW_C7816(base, mask, value) (UART_WR_C7816(base, (UART_RD_C7816(base) & ~(mask)) | (value)))
+#define UART_SET_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) |  (value)))
+#define UART_CLR_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) & ~(value)))
+#define UART_TOG_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C7816 bitfields
+ */
+
+/*!
+ * @name Register UART_C7816, field ISO_7816E[0] (RW)
+ *
+ * Indicates that the UART is operating according to the ISO-7816 protocol. This
+ * field must be modified only when no transmit or receive is occurring. If this
+ * field is changed during a data transfer, the data being transmitted or
+ * received may be transferred incorrectly.
+ *
+ * Values:
+ * - 0b0 - ISO-7816 functionality is turned off/not enabled.
+ * - 0b1 - ISO-7816 functionality is turned on/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ISO_7816E field. */
+#define UART_RD_C7816_ISO_7816E(base) ((UART_C7816_REG(base) & UART_C7816_ISO_7816E_MASK) >> UART_C7816_ISO_7816E_SHIFT)
+#define UART_BRD_C7816_ISO_7816E(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT))
+
+/*! @brief Set the ISO_7816E field to a new value. */
+#define UART_WR_C7816_ISO_7816E(base, value) (UART_RMW_C7816(base, UART_C7816_ISO_7816E_MASK, UART_C7816_ISO_7816E(value)))
+#define UART_BWR_C7816_ISO_7816E(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field TTYPE[1] (RW)
+ *
+ * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
+ * for more details.
+ *
+ * Values:
+ * - 0b0 - T = 0 per the ISO-7816 specification.
+ * - 0b1 - T = 1 per the ISO-7816 specification.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_TTYPE field. */
+#define UART_RD_C7816_TTYPE(base) ((UART_C7816_REG(base) & UART_C7816_TTYPE_MASK) >> UART_C7816_TTYPE_SHIFT)
+#define UART_BRD_C7816_TTYPE(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT))
+
+/*! @brief Set the TTYPE field to a new value. */
+#define UART_WR_C7816_TTYPE(base, value) (UART_RMW_C7816(base, UART_C7816_TTYPE_MASK, UART_C7816_TTYPE(value)))
+#define UART_BWR_C7816_TTYPE(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field INIT[2] (RW)
+ *
+ * When this field is set, all received characters are searched for a valid
+ * initial character. If an invalid initial character is identified, and ANACK is
+ * set, a NACK is sent. All received data is discarded and error flags blocked
+ * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
+ * until a valid initial character is detected. Upon detecting a valid initial
+ * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
+ * automatically updated to reflect the initial character that was received. The
+ * actual INIT data value is not stored in the receive buffer. Additionally, upon
+ * detection of a valid initial character, IS7816[INITD] is set and an interrupt
+ * issued as programmed by IE7816[INITDE]. When a valid initial character is
+ * detected, INIT is automatically cleared. This Initial Character Detect feature is
+ * supported only in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0b0 - Normal operating mode. Receiver does not seek to identify initial
+ *     character.
+ * - 0b1 - Receiver searches for initial character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_INIT field. */
+#define UART_RD_C7816_INIT(base) ((UART_C7816_REG(base) & UART_C7816_INIT_MASK) >> UART_C7816_INIT_SHIFT)
+#define UART_BRD_C7816_INIT(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT))
+
+/*! @brief Set the INIT field to a new value. */
+#define UART_WR_C7816_INIT(base, value) (UART_RMW_C7816(base, UART_C7816_INIT_MASK, UART_C7816_INIT(value)))
+#define UART_BWR_C7816_INIT(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ANACK[3] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a parity error occurs or if INIT is set and an invalid initial character is
+ * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
+ * attempts to retransmit the data indefinitely. To stop retransmission attempts,
+ * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
+ *
+ * Values:
+ * - 0b0 - No NACK is automatically generated.
+ * - 0b1 - A NACK is automatically generated if a parity error is detected or if
+ *     an invalid initial character is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ANACK field. */
+#define UART_RD_C7816_ANACK(base) ((UART_C7816_REG(base) & UART_C7816_ANACK_MASK) >> UART_C7816_ANACK_SHIFT)
+#define UART_BRD_C7816_ANACK(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT))
+
+/*! @brief Set the ANACK field to a new value. */
+#define UART_WR_C7816_ANACK(base, value) (UART_RMW_C7816(base, UART_C7816_ANACK_MASK, UART_C7816_ANACK(value)))
+#define UART_BWR_C7816_ANACK(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ONACK[4] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
+ * this results in the transmitter resending the packet that overflowed until the
+ * retransmit threshold for that transmitter is reached. A NACK is generated only
+ * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
+ * considerations
+ *
+ * Values:
+ * - 0b0 - The received data does not generate a NACK when the receipt of the
+ *     data results in an overflow event.
+ * - 0b1 - If the receiver buffer overflows, a NACK is automatically sent on a
+ *     received character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ONACK field. */
+#define UART_RD_C7816_ONACK(base) ((UART_C7816_REG(base) & UART_C7816_ONACK_MASK) >> UART_C7816_ONACK_SHIFT)
+#define UART_BRD_C7816_ONACK(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT))
+
+/*! @brief Set the ONACK field to a new value. */
+#define UART_WR_C7816_ONACK(base, value) (UART_RMW_C7816(base, UART_C7816_ONACK_MASK, UART_C7816_ONACK(value)))
+#define UART_BWR_C7816_ONACK(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IE7816 - UART 7816 Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IE7816 register controls which flags result in an interrupt being issued.
+ * This register is specific to 7816 functionality, the corresponding flags that
+ * drive the interrupts are not asserted when 7816E is not set/enabled. However,
+ * these flags may remain set if they are asserted while 7816E was set and not
+ * subsequently cleared. This register may be read or written to at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_IE7816 register
+ */
+/*@{*/
+#define UART_RD_IE7816(base)     (UART_IE7816_REG(base))
+#define UART_WR_IE7816(base, value) (UART_IE7816_REG(base) = (value))
+#define UART_RMW_IE7816(base, mask, value) (UART_WR_IE7816(base, (UART_RD_IE7816(base) & ~(mask)) | (value)))
+#define UART_SET_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) |  (value)))
+#define UART_CLR_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) & ~(value)))
+#define UART_TOG_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IE7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IE7816, field RXTE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[RXT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[RXT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_RXTE field. */
+#define UART_RD_IE7816_RXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_RXTE_MASK) >> UART_IE7816_RXTE_SHIFT)
+#define UART_BRD_IE7816_RXTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT))
+
+/*! @brief Set the RXTE field to a new value. */
+#define UART_WR_IE7816_RXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_RXTE_MASK, UART_IE7816_RXTE(value)))
+#define UART_BWR_IE7816_RXTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field TXTE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[TXT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[TXT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_TXTE field. */
+#define UART_RD_IE7816_TXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_TXTE_MASK) >> UART_IE7816_TXTE_SHIFT)
+#define UART_BRD_IE7816_TXTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT))
+
+/*! @brief Set the TXTE field to a new value. */
+#define UART_WR_IE7816_TXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_TXTE_MASK, UART_IE7816_TXTE(value)))
+#define UART_BWR_IE7816_TXTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field GTVE[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[GTV] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[GTV] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_GTVE field. */
+#define UART_RD_IE7816_GTVE(base) ((UART_IE7816_REG(base) & UART_IE7816_GTVE_MASK) >> UART_IE7816_GTVE_SHIFT)
+#define UART_BRD_IE7816_GTVE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT))
+
+/*! @brief Set the GTVE field to a new value. */
+#define UART_WR_IE7816_GTVE(base, value) (UART_RMW_IE7816(base, UART_IE7816_GTVE_MASK, UART_IE7816_GTVE(value)))
+#define UART_BWR_IE7816_GTVE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field INITDE[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[INITD] does not result in the generation of
+ *     an interrupt.
+ * - 0b1 - The assertion of IS7816[INITD] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_INITDE field. */
+#define UART_RD_IE7816_INITDE(base) ((UART_IE7816_REG(base) & UART_IE7816_INITDE_MASK) >> UART_IE7816_INITDE_SHIFT)
+#define UART_BRD_IE7816_INITDE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT))
+
+/*! @brief Set the INITDE field to a new value. */
+#define UART_WR_IE7816_INITDE(base, value) (UART_RMW_IE7816(base, UART_IE7816_INITDE_MASK, UART_IE7816_INITDE(value)))
+#define UART_BWR_IE7816_INITDE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field BWTE[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[BWT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[BWT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_BWTE field. */
+#define UART_RD_IE7816_BWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_BWTE_MASK) >> UART_IE7816_BWTE_SHIFT)
+#define UART_BRD_IE7816_BWTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT))
+
+/*! @brief Set the BWTE field to a new value. */
+#define UART_WR_IE7816_BWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_BWTE_MASK, UART_IE7816_BWTE(value)))
+#define UART_BWR_IE7816_BWTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field CWTE[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[CWT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[CWT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_CWTE field. */
+#define UART_RD_IE7816_CWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_CWTE_MASK) >> UART_IE7816_CWTE_SHIFT)
+#define UART_BRD_IE7816_CWTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT))
+
+/*! @brief Set the CWTE field to a new value. */
+#define UART_WR_IE7816_CWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_CWTE_MASK, UART_IE7816_CWTE(value)))
+#define UART_BWR_IE7816_CWTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field WTE[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[WT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[WT] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_WTE field. */
+#define UART_RD_IE7816_WTE(base) ((UART_IE7816_REG(base) & UART_IE7816_WTE_MASK) >> UART_IE7816_WTE_SHIFT)
+#define UART_BRD_IE7816_WTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT))
+
+/*! @brief Set the WTE field to a new value. */
+#define UART_WR_IE7816_WTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_WTE_MASK, UART_IE7816_WTE(value)))
+#define UART_BWR_IE7816_WTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IS7816 - UART 7816 Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IS7816 - UART 7816 Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IS7816 register provides a mechanism to read and clear the interrupt
+ * flags. All flags/interrupts are cleared by writing a 1 to the field location.
+ * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
+ * the flag condition that occurred since the last time the bit was cleared, not
+ * that the condition currently exists. The status flags are set regardless of
+ * whether the corresponding field in the IE7816 is set or cleared. The IE7816
+ * controls only if an interrupt is issued to the host processor. This register is
+ * specific to 7816 functionality and the values in this register have no affect on
+ * UART operation and should be ignored if 7816E is not set/enabled. This
+ * register may be read or written at anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_IS7816 register
+ */
+/*@{*/
+#define UART_RD_IS7816(base)     (UART_IS7816_REG(base))
+#define UART_WR_IS7816(base, value) (UART_IS7816_REG(base) = (value))
+#define UART_RMW_IS7816(base, mask, value) (UART_WR_IS7816(base, (UART_RD_IS7816(base) & ~(mask)) | (value)))
+#define UART_SET_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) |  (value)))
+#define UART_CLR_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) & ~(value)))
+#define UART_TOG_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IS7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IS7816, field RXT[0] (W1C)
+ *
+ * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
+ * generated in response to parity errors on received data. This flag requires ANACK
+ * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
+ * Clearing this field also resets the counter keeping track of consecutive NACKS. The
+ * UART will continue to attempt to receive data regardless of whether this flag
+ * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
+ * or packet is received without needing to issue a NACK, the internal NACK
+ * detection counter is cleared and the count restarts from zero on the next
+ * transmitted NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - The number of consecutive NACKS generated as a result of parity
+ *     errors and buffer overruns is less than or equal to the value in
+ *     ET7816[RXTHRESHOLD].
+ * - 0b1 - The number of consecutive NACKS generated as a result of parity
+ *     errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_RXT field. */
+#define UART_RD_IS7816_RXT(base) ((UART_IS7816_REG(base) & UART_IS7816_RXT_MASK) >> UART_IS7816_RXT_SHIFT)
+#define UART_BRD_IS7816_RXT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT))
+
+/*! @brief Set the RXT field to a new value. */
+#define UART_WR_IS7816_RXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_RXT(value)))
+#define UART_BWR_IS7816_RXT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field TXT[1] (W1C)
+ *
+ * Indicates that the transmit NACK threshold has been exceeded as indicated by
+ * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
+ * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
+ * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
+ * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
+ * internal NACK detection counter is cleared and the count restarts from zero on
+ * the next received NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - The number of retries and corresponding NACKS does not exceed the
+ *     value in ET7816[TXTHRESHOLD].
+ * - 0b1 - The number of retries and corresponding NACKS exceeds the value in
+ *     ET7816[TXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_TXT field. */
+#define UART_RD_IS7816_TXT(base) ((UART_IS7816_REG(base) & UART_IS7816_TXT_MASK) >> UART_IS7816_TXT_SHIFT)
+#define UART_BRD_IS7816_TXT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT))
+
+/*! @brief Set the TXT field to a new value. */
+#define UART_WR_IS7816_TXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_TXT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_TXT(value)))
+#define UART_BWR_IS7816_TXT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field GTV[2] (W1C)
+ *
+ * Indicates that one or more of the character guard time, block guard time, or
+ * guard time are violated. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - A guard time (GT, CGT, or BGT) has not been violated.
+ * - 0b1 - A guard time (GT, CGT, or BGT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_GTV field. */
+#define UART_RD_IS7816_GTV(base) ((UART_IS7816_REG(base) & UART_IS7816_GTV_MASK) >> UART_IS7816_GTV_SHIFT)
+#define UART_BRD_IS7816_GTV(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT))
+
+/*! @brief Set the GTV field to a new value. */
+#define UART_WR_IS7816_GTV(base, value) (UART_RMW_IS7816(base, (UART_IS7816_GTV_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_GTV(value)))
+#define UART_BWR_IS7816_GTV(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field INITD[4] (W1C)
+ *
+ * Indicates that a valid initial character is received. This interrupt is
+ * cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - A valid initial character has not been received.
+ * - 0b1 - A valid initial character has been received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_INITD field. */
+#define UART_RD_IS7816_INITD(base) ((UART_IS7816_REG(base) & UART_IS7816_INITD_MASK) >> UART_IS7816_INITD_SHIFT)
+#define UART_BRD_IS7816_INITD(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT))
+
+/*! @brief Set the INITD field to a new value. */
+#define UART_WR_IS7816_INITD(base, value) (UART_RMW_IS7816(base, (UART_IS7816_INITD_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_INITD(value)))
+#define UART_BWR_IS7816_INITD(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field BWT[5] (W1C)
+ *
+ * Indicates that the block wait time, the time between the leading edge of
+ * first received character of a block and the leading edge of the last character the
+ * previously transmitted block, has exceeded the programmed value. This flag
+ * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - Block wait time (BWT) has not been violated.
+ * - 0b1 - Block wait time (BWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_BWT field. */
+#define UART_RD_IS7816_BWT(base) ((UART_IS7816_REG(base) & UART_IS7816_BWT_MASK) >> UART_IS7816_BWT_SHIFT)
+#define UART_BRD_IS7816_BWT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT))
+
+/*! @brief Set the BWT field to a new value. */
+#define UART_WR_IS7816_BWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_BWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_BWT(value)))
+#define UART_BWR_IS7816_BWT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field CWT[6] (W1C)
+ *
+ * Indicates that the character wait time, the time between the leading edges of
+ * two consecutive characters in a block, has exceeded the programmed value.
+ * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
+ * writing 1.
+ *
+ * Values:
+ * - 0b0 - Character wait time (CWT) has not been violated.
+ * - 0b1 - Character wait time (CWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_CWT field. */
+#define UART_RD_IS7816_CWT(base) ((UART_IS7816_REG(base) & UART_IS7816_CWT_MASK) >> UART_IS7816_CWT_SHIFT)
+#define UART_BRD_IS7816_CWT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT))
+
+/*! @brief Set the CWT field to a new value. */
+#define UART_WR_IS7816_CWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_CWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_CWT(value)))
+#define UART_BWR_IS7816_CWT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field WT[7] (W1C)
+ *
+ * Indicates that the wait time, the time between the leading edge of a
+ * character being transmitted and the leading edge of the next response character, has
+ * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
+ * This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - Wait time (WT) has not been violated.
+ * - 0b1 - Wait time (WT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_WT field. */
+#define UART_RD_IS7816_WT(base) ((UART_IS7816_REG(base) & UART_IS7816_WT_MASK) >> UART_IS7816_WT_SHIFT)
+#define UART_BRD_IS7816_WT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT))
+
+/*! @brief Set the WT field to a new value. */
+#define UART_WR_IS7816_WT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_WT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK), UART_IS7816_WT(value)))
+#define UART_BWR_IS7816_WT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816T0 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816T0 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816T0 register
+ */
+/*@{*/
+#define UART_RD_WP7816T0(base)   (UART_WP7816T0_REG(base))
+#define UART_WR_WP7816T0(base, value) (UART_WP7816T0_REG(base) = (value))
+#define UART_RMW_WP7816T0(base, mask, value) (UART_WR_WP7816T0(base, (UART_RD_WP7816T0(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) |  (value)))
+#define UART_CLR_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) & ~(value)))
+#define UART_TOG_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816T1 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816T1 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816T1 register
+ */
+/*@{*/
+#define UART_RD_WP7816T1(base)   (UART_WP7816T1_REG(base))
+#define UART_WR_WP7816T1(base, value) (UART_WP7816T1_REG(base) = (value))
+#define UART_RMW_WP7816T1(base, mask, value) (UART_WR_WP7816T1(base, (UART_RD_WP7816T1(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) |  (value)))
+#define UART_CLR_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) & ~(value)))
+#define UART_TOG_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_WP7816T1 bitfields
+ */
+
+/*!
+ * @name Register UART_WP7816T1, field BWI[3:0] (RW)
+ *
+ * Used to calculate the value used for the BWT counter. It represent a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816T1_BWI field. */
+#define UART_RD_WP7816T1_BWI(base) ((UART_WP7816T1_REG(base) & UART_WP7816T1_BWI_MASK) >> UART_WP7816T1_BWI_SHIFT)
+#define UART_BRD_WP7816T1_BWI(base) (UART_RD_WP7816T1_BWI(base))
+
+/*! @brief Set the BWI field to a new value. */
+#define UART_WR_WP7816T1_BWI(base, value) (UART_RMW_WP7816T1(base, UART_WP7816T1_BWI_MASK, UART_WP7816T1_BWI(value)))
+#define UART_BWR_WP7816T1_BWI(base, value) (UART_WR_WP7816T1_BWI(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_WP7816T1, field CWI[7:4] (RW)
+ *
+ * Used to calculate the value used for the CWT counter. It represents a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816T1_CWI field. */
+#define UART_RD_WP7816T1_CWI(base) ((UART_WP7816T1_REG(base) & UART_WP7816T1_CWI_MASK) >> UART_WP7816T1_CWI_SHIFT)
+#define UART_BRD_WP7816T1_CWI(base) (UART_RD_WP7816T1_CWI(base))
+
+/*! @brief Set the CWI field to a new value. */
+#define UART_WR_WP7816T1_CWI(base, value) (UART_RMW_WP7816T1(base, UART_WP7816T1_CWI_MASK, UART_WP7816T1_CWI(value)))
+#define UART_BWR_WP7816T1_CWI(base, value) (UART_WR_WP7816T1_CWI(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WN7816 - UART 7816 Wait N Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WN7816 - UART 7816 Wait N Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The WN7816 register contains a parameter that is used in the calculation of
+ * the guard time counter. This register may be read at any time. This register
+ * must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WN7816 register
+ */
+/*@{*/
+#define UART_RD_WN7816(base)     (UART_WN7816_REG(base))
+#define UART_WR_WN7816(base, value) (UART_WN7816_REG(base) = (value))
+#define UART_RMW_WN7816(base, mask, value) (UART_WR_WN7816(base, (UART_RD_WN7816(base) & ~(mask)) | (value)))
+#define UART_SET_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) |  (value)))
+#define UART_CLR_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) & ~(value)))
+#define UART_TOG_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WF7816 - UART 7816 Wait FD Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WF7816 - UART 7816 Wait FD Register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * The WF7816 contains parameters that are used in the generation of various
+ * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WF7816 register
+ */
+/*@{*/
+#define UART_RD_WF7816(base)     (UART_WF7816_REG(base))
+#define UART_WR_WF7816(base, value) (UART_WF7816_REG(base) = (value))
+#define UART_RMW_WF7816(base, mask, value) (UART_WR_WF7816(base, (UART_RD_WF7816(base) & ~(mask)) | (value)))
+#define UART_SET_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) |  (value)))
+#define UART_CLR_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) & ~(value)))
+#define UART_TOG_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ET7816 - UART 7816 Error Threshold Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ET7816 - UART 7816 Error Threshold Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The ET7816 register contains fields that determine the number of NACKs that
+ * must be received or transmitted before the host processor is notified. This
+ * register may be read at anytime. This register must be written to only when
+ * C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_ET7816 register
+ */
+/*@{*/
+#define UART_RD_ET7816(base)     (UART_ET7816_REG(base))
+#define UART_WR_ET7816(base, value) (UART_ET7816_REG(base) = (value))
+#define UART_RMW_ET7816(base, mask, value) (UART_WR_ET7816(base, (UART_RD_ET7816(base) & ~(mask)) | (value)))
+#define UART_SET_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) |  (value)))
+#define UART_CLR_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) & ~(value)))
+#define UART_TOG_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ET7816 bitfields
+ */
+
+/*!
+ * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
+ *
+ * The value written to this field indicates the maximum number of consecutive
+ * NACKs generated as a result of a parity error or receiver buffer overruns
+ * before the host processor is notified. After the counter exceeds that value in the
+ * field, the IS7816[RXT] is asserted. This field is meaningful only when
+ * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
+ * NACKs that have been transmitted since the last successful reception. This
+ * counter saturates at 4'hF and does not wrap around. Regardless of the number of
+ * NACKs sent, the UART continues to receive valid packets indefinitely. For
+ * additional information, see IS7816[RXT] field description.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */
+#define UART_RD_ET7816_RXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_RXTHRESHOLD_MASK) >> UART_ET7816_RXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_RXTHRESHOLD(base) (UART_RD_ET7816_RXTHRESHOLD(base))
+
+/*! @brief Set the RXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_RXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_RXTHRESHOLD_MASK, UART_ET7816_RXTHRESHOLD(value)))
+#define UART_BWR_ET7816_RXTHRESHOLD(base, value) (UART_WR_ET7816_RXTHRESHOLD(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
+ *
+ * The value written to this field indicates the maximum number of failed
+ * attempts (NACKs) a transmitted character can have before the host processor is
+ * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
+ * The value read from this field represents the number of consecutive NACKs
+ * that have been received since the last successful transmission. This counter
+ * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
+ * received, the UART continues to retransmit indefinitely. This flag only
+ * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
+ * description.
+ *
+ * Values:
+ * - 0b0000 - TXT asserts on the first NACK that is received.
+ * - 0b0001 - TXT asserts on the second NACK that is received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */
+#define UART_RD_ET7816_TXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_TXTHRESHOLD_MASK) >> UART_ET7816_TXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_TXTHRESHOLD(base) (UART_RD_ET7816_TXTHRESHOLD(base))
+
+/*! @brief Set the TXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_TXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_TXTHRESHOLD_MASK, UART_ET7816_TXTHRESHOLD(value)))
+#define UART_BWR_ET7816_TXTHRESHOLD(base, value) (UART_WR_ET7816_TXTHRESHOLD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TL7816 - UART 7816 Transmit Length Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TL7816 - UART 7816 Transmit Length Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The TL7816 register is used to indicate the number of characters contained in
+ * the block being transmitted. This register is used only when C7816[TTYPE] =
+ * 1. This register may be read at anytime. This register must be written only
+ * when C2[TE] is not enabled.
+ */
+/*!
+ * @name Constants and macros for entire UART_TL7816 register
+ */
+/*@{*/
+#define UART_RD_TL7816(base)     (UART_TL7816_REG(base))
+#define UART_WR_TL7816(base, value) (UART_TL7816_REG(base) = (value))
+#define UART_RMW_TL7816(base, mask, value) (UART_WR_TL7816(base, (UART_RD_TL7816(base) & ~(mask)) | (value)))
+#define UART_SET_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) |  (value)))
+#define UART_CLR_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) & ~(value)))
+#define UART_TOG_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 USB
+ *
+ * Universal Serial Bus, OTG Capable Controller
+ *
+ * Registers defined in this header file:
+ * - USB_PERID - Peripheral ID register
+ * - USB_IDCOMP - Peripheral ID Complement register
+ * - USB_REV - Peripheral Revision register
+ * - USB_ADDINFO - Peripheral Additional Info register
+ * - USB_OTGISTAT - OTG Interrupt Status register
+ * - USB_OTGICR - OTG Interrupt Control register
+ * - USB_OTGSTAT - OTG Status register
+ * - USB_OTGCTL - OTG Control register
+ * - USB_ISTAT - Interrupt Status register
+ * - USB_INTEN - Interrupt Enable register
+ * - USB_ERRSTAT - Error Interrupt Status register
+ * - USB_ERREN - Error Interrupt Enable register
+ * - USB_STAT - Status register
+ * - USB_CTL - Control register
+ * - USB_ADDR - Address register
+ * - USB_BDTPAGE1 - BDT Page register 1
+ * - USB_FRMNUML - Frame Number register Low
+ * - USB_FRMNUMH - Frame Number register High
+ * - USB_TOKEN - Token register
+ * - USB_SOFTHLD - SOF Threshold register
+ * - USB_BDTPAGE2 - BDT Page Register 2
+ * - USB_BDTPAGE3 - BDT Page Register 3
+ * - USB_ENDPT - Endpoint Control register
+ * - USB_USBCTRL - USB Control register
+ * - USB_OBSERVE - USB OTG Observe register
+ * - USB_CONTROL - USB OTG Control register
+ * - USB_USBTRC0 - USB Transceiver Control register 0
+ * - USB_USBFRMADJUST - Frame Adjust Register
+ * - USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ * - USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ * - USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ */
+
+#define USB_INSTANCE_COUNT (1U) /*!< Number of instances of the USB module. */
+#define USB0_IDX (0U) /*!< Instance number for USB0. */
+
+/*******************************************************************************
+ * USB_PERID - Peripheral ID register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_PERID - Peripheral ID register (RO)
+ *
+ * Reset value: 0x04U
+ *
+ * Reads back the value of 0x04. This value is defined for the USB peripheral.
+ */
+/*!
+ * @name Constants and macros for entire USB_PERID register
+ */
+/*@{*/
+#define USB_RD_PERID(base)       (USB_PERID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_PERID bitfields
+ */
+
+/*!
+ * @name Register USB_PERID, field ID[5:0] (RO)
+ *
+ * This field always reads 0x4h.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_PERID_ID field. */
+#define USB_RD_PERID_ID(base) ((USB_PERID_REG(base) & USB_PERID_ID_MASK) >> USB_PERID_ID_SHIFT)
+#define USB_BRD_PERID_ID(base) (USB_RD_PERID_ID(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_IDCOMP - Peripheral ID Complement register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_IDCOMP - Peripheral ID Complement register (RO)
+ *
+ * Reset value: 0xFBU
+ *
+ * Reads back the complement of the Peripheral ID register. For the USB
+ * peripheral, the value is 0xFB.
+ */
+/*!
+ * @name Constants and macros for entire USB_IDCOMP register
+ */
+/*@{*/
+#define USB_RD_IDCOMP(base)      (USB_IDCOMP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_IDCOMP bitfields
+ */
+
+/*!
+ * @name Register USB_IDCOMP, field NID[5:0] (RO)
+ *
+ * Ones' complement of PERID[ID]. bits.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_IDCOMP_NID field. */
+#define USB_RD_IDCOMP_NID(base) ((USB_IDCOMP_REG(base) & USB_IDCOMP_NID_MASK) >> USB_IDCOMP_NID_SHIFT)
+#define USB_BRD_IDCOMP_NID(base) (USB_RD_IDCOMP_NID(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_REV - Peripheral Revision register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_REV - Peripheral Revision register (RO)
+ *
+ * Reset value: 0x33U
+ *
+ * Contains the revision number of the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_REV register
+ */
+/*@{*/
+#define USB_RD_REV(base)         (USB_REV_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDINFO - Peripheral Additional Info register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDINFO - Peripheral Additional Info register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with
+ * the Host Enable bit.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDINFO register
+ */
+/*@{*/
+#define USB_RD_ADDINFO(base)     (USB_ADDINFO_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDINFO bitfields
+ */
+
+/*!
+ * @name Register USB_ADDINFO, field IEHOST[0] (RO)
+ *
+ * This bit is set if host mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IEHOST field. */
+#define USB_RD_ADDINFO_IEHOST(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IEHOST_MASK) >> USB_ADDINFO_IEHOST_SHIFT)
+#define USB_BRD_ADDINFO_IEHOST(base) (BITBAND_ACCESS8(&USB_ADDINFO_REG(base), USB_ADDINFO_IEHOST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_ADDINFO, field IRQNUM[7:3] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IRQNUM field. */
+#define USB_RD_ADDINFO_IRQNUM(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IRQNUM_MASK) >> USB_ADDINFO_IRQNUM_SHIFT)
+#define USB_BRD_ADDINFO_IRQNUM(base) (USB_RD_ADDINFO_IRQNUM(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGISTAT - OTG Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGISTAT - OTG Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Records changes of the ID sense and VBUS signals. Software can read this
+ * register to determine the event that triggers an interrupt. Only bits that have
+ * changed since the last software read are set. Writing a one to a bit clears the
+ * associated interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGISTAT register
+ */
+/*@{*/
+#define USB_RD_OTGISTAT(base)    (USB_OTGISTAT_REG(base))
+#define USB_WR_OTGISTAT(base, value) (USB_OTGISTAT_REG(base) = (value))
+#define USB_RMW_OTGISTAT(base, mask, value) (USB_WR_OTGISTAT(base, (USB_RD_OTGISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) |  (value)))
+#define USB_CLR_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) & ~(value)))
+#define USB_TOG_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on an A device.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field. */
+#define USB_RD_OTGISTAT_AVBUSCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_AVBUSCHG_MASK) >> USB_OTGISTAT_AVBUSCHG_SHIFT)
+#define USB_BRD_OTGISTAT_AVBUSCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_AVBUSCHG_SHIFT))
+
+/*! @brief Set the AVBUSCHG field to a new value. */
+#define USB_WR_OTGISTAT_AVBUSCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_AVBUSCHG_MASK, USB_OTGISTAT_AVBUSCHG(value)))
+#define USB_BWR_OTGISTAT_AVBUSCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_AVBUSCHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on a B device.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field. */
+#define USB_RD_OTGISTAT_B_SESS_CHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_B_SESS_CHG_MASK) >> USB_OTGISTAT_B_SESS_CHG_SHIFT)
+#define USB_BRD_OTGISTAT_B_SESS_CHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_B_SESS_CHG_SHIFT))
+
+/*! @brief Set the B_SESS_CHG field to a new value. */
+#define USB_WR_OTGISTAT_B_SESS_CHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_B_SESS_CHG_MASK, USB_OTGISTAT_B_SESS_CHG(value)))
+#define USB_BWR_OTGISTAT_B_SESS_CHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_B_SESS_CHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW)
+ *
+ * This bit is set when a change in VBUS is detected indicating a session valid
+ * or a session no longer valid.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field. */
+#define USB_RD_OTGISTAT_SESSVLDCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_SESSVLDCHG_MASK) >> USB_OTGISTAT_SESSVLDCHG_SHIFT)
+#define USB_BRD_OTGISTAT_SESSVLDCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_SESSVLDCHG_SHIFT))
+
+/*! @brief Set the SESSVLDCHG field to a new value. */
+#define USB_WR_OTGISTAT_SESSVLDCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_SESSVLDCHG_MASK, USB_OTGISTAT_SESSVLDCHG(value)))
+#define USB_BWR_OTGISTAT_SESSVLDCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_SESSVLDCHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW)
+ *
+ * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits)
+ * are stable without change for 1 millisecond, and the value of the line state
+ * is different from the last time when the line state was stable. It is set on
+ * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
+ * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt
+ * can be used in detecting Reset, Resume, Connect, and Data Line Pulse
+ * signaling.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field. */
+#define USB_RD_OTGISTAT_LINE_STATE_CHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_LINE_STATE_CHG_MASK) >> USB_OTGISTAT_LINE_STATE_CHG_SHIFT)
+#define USB_BRD_OTGISTAT_LINE_STATE_CHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_LINE_STATE_CHG_SHIFT))
+
+/*! @brief Set the LINE_STATE_CHG field to a new value. */
+#define USB_WR_OTGISTAT_LINE_STATE_CHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_LINE_STATE_CHG_MASK, USB_OTGISTAT_LINE_STATE_CHG(value)))
+#define USB_BWR_OTGISTAT_LINE_STATE_CHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_LINE_STATE_CHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW)
+ *
+ * This bit is set when the 1 millisecond timer expires. This bit stays asserted
+ * until cleared by software. The interrupt must be serviced every millisecond
+ * to avoid losing 1msec counts.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_ONEMSEC field. */
+#define USB_RD_OTGISTAT_ONEMSEC(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_ONEMSEC_MASK) >> USB_OTGISTAT_ONEMSEC_SHIFT)
+#define USB_BRD_OTGISTAT_ONEMSEC(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_ONEMSEC_SHIFT))
+
+/*! @brief Set the ONEMSEC field to a new value. */
+#define USB_WR_OTGISTAT_ONEMSEC(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_ONEMSEC_MASK, USB_OTGISTAT_ONEMSEC(value)))
+#define USB_BWR_OTGISTAT_ONEMSEC(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_ONEMSEC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field IDCHG[7] (RW)
+ *
+ * This bit is set when a change in the ID Signal from the USB connector is
+ * sensed.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_IDCHG field. */
+#define USB_RD_OTGISTAT_IDCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_IDCHG_MASK) >> USB_OTGISTAT_IDCHG_SHIFT)
+#define USB_BRD_OTGISTAT_IDCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_IDCHG_SHIFT))
+
+/*! @brief Set the IDCHG field to a new value. */
+#define USB_WR_OTGISTAT_IDCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_IDCHG_MASK, USB_OTGISTAT_IDCHG(value)))
+#define USB_BWR_OTGISTAT_IDCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_IDCHG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGICR - OTG Interrupt Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGICR - OTG Interrupt Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Enables the corresponding interrupt status bits defined in the OTG Interrupt
+ * Status Register.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGICR register
+ */
+/*@{*/
+#define USB_RD_OTGICR(base)      (USB_OTGICR_REG(base))
+#define USB_WR_OTGICR(base, value) (USB_OTGICR_REG(base) = (value))
+#define USB_RMW_OTGICR(base, mask, value) (USB_WR_OTGICR(base, (USB_RD_OTGICR(base) & ~(mask)) | (value)))
+#define USB_SET_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) |  (value)))
+#define USB_CLR_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) & ~(value)))
+#define USB_TOG_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGICR bitfields
+ */
+
+/*!
+ * @name Register USB_OTGICR, field AVBUSEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the AVBUSCHG interrupt.
+ * - 0b1 - Enables the AVBUSCHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_AVBUSEN field. */
+#define USB_RD_OTGICR_AVBUSEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_AVBUSEN_MASK) >> USB_OTGICR_AVBUSEN_SHIFT)
+#define USB_BRD_OTGICR_AVBUSEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_AVBUSEN_SHIFT))
+
+/*! @brief Set the AVBUSEN field to a new value. */
+#define USB_WR_OTGICR_AVBUSEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_AVBUSEN_MASK, USB_OTGICR_AVBUSEN(value)))
+#define USB_BWR_OTGICR_AVBUSEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_AVBUSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field BSESSEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the B_SESS_CHG interrupt.
+ * - 0b1 - Enables the B_SESS_CHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_BSESSEN field. */
+#define USB_RD_OTGICR_BSESSEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_BSESSEN_MASK) >> USB_OTGICR_BSESSEN_SHIFT)
+#define USB_BRD_OTGICR_BSESSEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_BSESSEN_SHIFT))
+
+/*! @brief Set the BSESSEN field to a new value. */
+#define USB_WR_OTGICR_BSESSEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_BSESSEN_MASK, USB_OTGICR_BSESSEN(value)))
+#define USB_BWR_OTGICR_BSESSEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_BSESSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field SESSVLDEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the SESSVLDCHG interrupt.
+ * - 0b1 - Enables the SESSVLDCHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_SESSVLDEN field. */
+#define USB_RD_OTGICR_SESSVLDEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_SESSVLDEN_MASK) >> USB_OTGICR_SESSVLDEN_SHIFT)
+#define USB_BRD_OTGICR_SESSVLDEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_SESSVLDEN_SHIFT))
+
+/*! @brief Set the SESSVLDEN field to a new value. */
+#define USB_WR_OTGICR_SESSVLDEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_SESSVLDEN_MASK, USB_OTGICR_SESSVLDEN(value)))
+#define USB_BWR_OTGICR_SESSVLDEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_SESSVLDEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field LINESTATEEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the LINE_STAT_CHG interrupt.
+ * - 0b1 - Enables the LINE_STAT_CHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_LINESTATEEN field. */
+#define USB_RD_OTGICR_LINESTATEEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_LINESTATEEN_MASK) >> USB_OTGICR_LINESTATEEN_SHIFT)
+#define USB_BRD_OTGICR_LINESTATEEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_LINESTATEEN_SHIFT))
+
+/*! @brief Set the LINESTATEEN field to a new value. */
+#define USB_WR_OTGICR_LINESTATEEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_LINESTATEEN_MASK, USB_OTGICR_LINESTATEEN(value)))
+#define USB_BWR_OTGICR_LINESTATEEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_LINESTATEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field ONEMSECEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Diables the 1ms timer interrupt.
+ * - 0b1 - Enables the 1ms timer interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_ONEMSECEN field. */
+#define USB_RD_OTGICR_ONEMSECEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_ONEMSECEN_MASK) >> USB_OTGICR_ONEMSECEN_SHIFT)
+#define USB_BRD_OTGICR_ONEMSECEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_ONEMSECEN_SHIFT))
+
+/*! @brief Set the ONEMSECEN field to a new value. */
+#define USB_WR_OTGICR_ONEMSECEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_ONEMSECEN_MASK, USB_OTGICR_ONEMSECEN(value)))
+#define USB_BWR_OTGICR_ONEMSECEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_ONEMSECEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field IDEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The ID interrupt is disabled
+ * - 0b1 - The ID interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_IDEN field. */
+#define USB_RD_OTGICR_IDEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_IDEN_MASK) >> USB_OTGICR_IDEN_SHIFT)
+#define USB_BRD_OTGICR_IDEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_IDEN_SHIFT))
+
+/*! @brief Set the IDEN field to a new value. */
+#define USB_WR_OTGICR_IDEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_IDEN_MASK, USB_OTGICR_IDEN(value)))
+#define USB_BWR_OTGICR_IDEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_IDEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGSTAT - OTG Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGSTAT - OTG Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Displays the actual value from the external comparator outputs of the ID pin
+ * and VBUS.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGSTAT register
+ */
+/*@{*/
+#define USB_RD_OTGSTAT(base)     (USB_OTGSTAT_REG(base))
+#define USB_WR_OTGSTAT(base, value) (USB_OTGSTAT_REG(base) = (value))
+#define USB_RMW_OTGSTAT(base, mask, value) (USB_WR_OTGSTAT(base, (USB_RD_OTGSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) |  (value)))
+#define USB_CLR_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) & ~(value)))
+#define USB_TOG_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is below the A VBUS Valid threshold.
+ * - 0b1 - The VBUS voltage is above the A VBUS Valid threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field. */
+#define USB_RD_OTGSTAT_AVBUSVLD(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_AVBUSVLD_MASK) >> USB_OTGSTAT_AVBUSVLD_SHIFT)
+#define USB_BRD_OTGSTAT_AVBUSVLD(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_AVBUSVLD_SHIFT))
+
+/*! @brief Set the AVBUSVLD field to a new value. */
+#define USB_WR_OTGSTAT_AVBUSVLD(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_AVBUSVLD_MASK, USB_OTGSTAT_AVBUSVLD(value)))
+#define USB_BWR_OTGSTAT_AVBUSVLD(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_AVBUSVLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field BSESSEND[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is above the B session end threshold.
+ * - 0b1 - The VBUS voltage is below the B session end threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_BSESSEND field. */
+#define USB_RD_OTGSTAT_BSESSEND(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_BSESSEND_MASK) >> USB_OTGSTAT_BSESSEND_SHIFT)
+#define USB_BRD_OTGSTAT_BSESSEND(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_BSESSEND_SHIFT))
+
+/*! @brief Set the BSESSEND field to a new value. */
+#define USB_WR_OTGSTAT_BSESSEND(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_BSESSEND_MASK, USB_OTGSTAT_BSESSEND(value)))
+#define USB_BWR_OTGSTAT_BSESSEND(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_BSESSEND_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is below the B session valid threshold
+ * - 0b1 - The VBUS voltage is above the B session valid threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_SESS_VLD field. */
+#define USB_RD_OTGSTAT_SESS_VLD(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_SESS_VLD_MASK) >> USB_OTGSTAT_SESS_VLD_SHIFT)
+#define USB_BRD_OTGSTAT_SESS_VLD(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_SESS_VLD_SHIFT))
+
+/*! @brief Set the SESS_VLD field to a new value. */
+#define USB_WR_OTGSTAT_SESS_VLD(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_SESS_VLD_MASK, USB_OTGSTAT_SESS_VLD(value)))
+#define USB_BWR_OTGSTAT_SESS_VLD(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_SESS_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
+ *
+ * Indicates that the internal signals that control the LINE_STATE_CHG field of
+ * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG
+ * field and then read this field. If this field reads as 1, then the value of
+ * LINE_STATE_CHG can be considered stable.
+ *
+ * Values:
+ * - 0b0 - The LINE_STAT_CHG bit is not yet stable.
+ * - 0b1 - The LINE_STAT_CHG bit has been debounced and is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field. */
+#define USB_RD_OTGSTAT_LINESTATESTABLE(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_LINESTATESTABLE_MASK) >> USB_OTGSTAT_LINESTATESTABLE_SHIFT)
+#define USB_BRD_OTGSTAT_LINESTATESTABLE(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_LINESTATESTABLE_SHIFT))
+
+/*! @brief Set the LINESTATESTABLE field to a new value. */
+#define USB_WR_OTGSTAT_LINESTATESTABLE(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_LINESTATESTABLE_MASK, USB_OTGSTAT_LINESTATESTABLE(value)))
+#define USB_BWR_OTGSTAT_LINESTATESTABLE(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_LINESTATESTABLE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW)
+ *
+ * This bit is reserved for the 1ms count, but it is not useful to software.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field. */
+#define USB_RD_OTGSTAT_ONEMSECEN(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_ONEMSECEN_MASK) >> USB_OTGSTAT_ONEMSECEN_SHIFT)
+#define USB_BRD_OTGSTAT_ONEMSECEN(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ONEMSECEN_SHIFT))
+
+/*! @brief Set the ONEMSECEN field to a new value. */
+#define USB_WR_OTGSTAT_ONEMSECEN(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_ONEMSECEN_MASK, USB_OTGSTAT_ONEMSECEN(value)))
+#define USB_BWR_OTGSTAT_ONEMSECEN(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ONEMSECEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field ID[7] (RW)
+ *
+ * Indicates the current state of the ID pin on the USB connector
+ *
+ * Values:
+ * - 0b0 - Indicates a Type A cable is plugged into the USB connector.
+ * - 0b1 - Indicates no cable is attached or a Type B cable is plugged into the
+ *     USB connector.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_ID field. */
+#define USB_RD_OTGSTAT_ID(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_ID_MASK) >> USB_OTGSTAT_ID_SHIFT)
+#define USB_BRD_OTGSTAT_ID(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ID_SHIFT))
+
+/*! @brief Set the ID field to a new value. */
+#define USB_WR_OTGSTAT_ID(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_ID_MASK, USB_OTGSTAT_ID(value)))
+#define USB_BWR_OTGSTAT_ID(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ID_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGCTL - OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGCTL - OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Controls the operation of VBUS and Data Line termination resistors.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGCTL register
+ */
+/*@{*/
+#define USB_RD_OTGCTL(base)      (USB_OTGCTL_REG(base))
+#define USB_WR_OTGCTL(base, value) (USB_OTGCTL_REG(base) = (value))
+#define USB_RMW_OTGCTL(base, mask, value) (USB_WR_OTGCTL(base, (USB_RD_OTGCTL(base) & ~(mask)) | (value)))
+#define USB_SET_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) |  (value)))
+#define USB_CLR_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) & ~(value)))
+#define USB_TOG_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGCTL bitfields
+ */
+
+/*!
+ * @name Register USB_OTGCTL, field OTGEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then
+ *     the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+
+ *     and D- Data Line pull-down resistors are engaged.
+ * - 0b1 - The pull-up and pull-down controls in this register are used.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_OTGEN field. */
+#define USB_RD_OTGCTL_OTGEN(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_OTGEN_MASK) >> USB_OTGCTL_OTGEN_SHIFT)
+#define USB_BRD_OTGCTL_OTGEN(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_OTGEN_SHIFT))
+
+/*! @brief Set the OTGEN field to a new value. */
+#define USB_WR_OTGCTL_OTGEN(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_OTGEN_MASK, USB_OTGCTL_OTGEN(value)))
+#define USB_BWR_OTGCTL_OTGEN(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_OTGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DMLOW[4] (RW)
+ *
+ * Values:
+ * - 0b0 - D- pulldown resistor is not enabled.
+ * - 0b1 - D- pulldown resistor is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DMLOW field. */
+#define USB_RD_OTGCTL_DMLOW(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DMLOW_MASK) >> USB_OTGCTL_DMLOW_SHIFT)
+#define USB_BRD_OTGCTL_DMLOW(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DMLOW_SHIFT))
+
+/*! @brief Set the DMLOW field to a new value. */
+#define USB_WR_OTGCTL_DMLOW(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DMLOW_MASK, USB_OTGCTL_DMLOW(value)))
+#define USB_BWR_OTGCTL_DMLOW(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DMLOW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DPLOW[5] (RW)
+ *
+ * This bit should always be enabled together with bit 4 (DMLOW)
+ *
+ * Values:
+ * - 0b0 - D+ pulldown resistor is not enabled.
+ * - 0b1 - D+ pulldown resistor is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPLOW field. */
+#define USB_RD_OTGCTL_DPLOW(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPLOW_MASK) >> USB_OTGCTL_DPLOW_SHIFT)
+#define USB_BRD_OTGCTL_DPLOW(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPLOW_SHIFT))
+
+/*! @brief Set the DPLOW field to a new value. */
+#define USB_WR_OTGCTL_DPLOW(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPLOW_MASK, USB_OTGCTL_DPLOW(value)))
+#define USB_BWR_OTGCTL_DPLOW(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPLOW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DPHIGH[7] (RW)
+ *
+ * Values:
+ * - 0b0 - D+ pullup resistor is not enabled
+ * - 0b1 - D+ pullup resistor is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPHIGH field. */
+#define USB_RD_OTGCTL_DPHIGH(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPHIGH_MASK) >> USB_OTGCTL_DPHIGH_SHIFT)
+#define USB_BRD_OTGCTL_DPHIGH(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT))
+
+/*! @brief Set the DPHIGH field to a new value. */
+#define USB_WR_OTGCTL_DPHIGH(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPHIGH_MASK, USB_OTGCTL_DPHIGH(value)))
+#define USB_BWR_OTGCTL_DPHIGH(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ISTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ISTAT - Interrupt Status register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains fields for each of the interrupt sources within the USB Module. Each
+ * of these fields are qualified with their respective interrupt enable bits.
+ * All fields of this register are logically OR'd together along with the OTG
+ * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the
+ * processor's interrupt controller. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ISTAT register
+ */
+/*@{*/
+#define USB_RD_ISTAT(base)       (USB_ISTAT_REG(base))
+#define USB_WR_ISTAT(base, value) (USB_ISTAT_REG(base) = (value))
+#define USB_RMW_ISTAT(base, mask, value) (USB_WR_ISTAT(base, (USB_RD_ISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) |  (value)))
+#define USB_CLR_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) & ~(value)))
+#define USB_TOG_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ISTAT, field USBRST[0] (W1C)
+ *
+ * This bit is set when the USB Module has decoded a valid USB reset. This
+ * informs the processor that it should write 0x00 into the address register and
+ * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5
+ * microseconds. It is not asserted again until the USB reset condition has been
+ * removed and then reasserted.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_USBRST field. */
+#define USB_RD_ISTAT_USBRST(base) ((USB_ISTAT_REG(base) & USB_ISTAT_USBRST_MASK) >> USB_ISTAT_USBRST_SHIFT)
+#define USB_BRD_ISTAT_USBRST(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT))
+
+/*! @brief Set the USBRST field to a new value. */
+#define USB_WR_ISTAT_USBRST(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_USBRST(value)))
+#define USB_BWR_ISTAT_USBRST(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ERROR[1] (W1C)
+ *
+ * This bit is set when any of the error conditions within Error Interrupt
+ * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register
+ * to determine the source of the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ERROR field. */
+#define USB_RD_ISTAT_ERROR(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ERROR_MASK) >> USB_ISTAT_ERROR_SHIFT)
+#define USB_BRD_ISTAT_ERROR(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT))
+
+/*! @brief Set the ERROR field to a new value. */
+#define USB_WR_ISTAT_ERROR(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ERROR_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ERROR(value)))
+#define USB_BWR_ISTAT_ERROR(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SOFTOK[2] (W1C)
+ *
+ * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In
+ * Host mode this field is set when the SOF threshold is reached, so that
+ * software can prepare for the next SOF.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SOFTOK field. */
+#define USB_RD_ISTAT_SOFTOK(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SOFTOK_MASK) >> USB_ISTAT_SOFTOK_SHIFT)
+#define USB_BRD_ISTAT_SOFTOK(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT))
+
+/*! @brief Set the SOFTOK field to a new value. */
+#define USB_WR_ISTAT_SOFTOK(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SOFTOK_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SOFTOK(value)))
+#define USB_BWR_ISTAT_SOFTOK(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field TOKDNE[3] (W1C)
+ *
+ * This bit is set when the current token being processed has completed. The
+ * processor must immediately read the STATUS (STAT) register to determine the
+ * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes
+ * STAT to be cleared or the STAT holding register to be loaded into the STAT
+ * register.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_TOKDNE field. */
+#define USB_RD_ISTAT_TOKDNE(base) ((USB_ISTAT_REG(base) & USB_ISTAT_TOKDNE_MASK) >> USB_ISTAT_TOKDNE_SHIFT)
+#define USB_BRD_ISTAT_TOKDNE(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT))
+
+/*! @brief Set the TOKDNE field to a new value. */
+#define USB_WR_ISTAT_TOKDNE(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_TOKDNE_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_TOKDNE(value)))
+#define USB_BWR_ISTAT_TOKDNE(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SLEEP[4] (W1C)
+ *
+ * This bit is set when the USB Module detects a constant idle on the USB bus
+ * for 3 ms. The sleep timer is reset by activity on the USB bus.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SLEEP field. */
+#define USB_RD_ISTAT_SLEEP(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SLEEP_MASK) >> USB_ISTAT_SLEEP_SHIFT)
+#define USB_BRD_ISTAT_SLEEP(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define USB_WR_ISTAT_SLEEP(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SLEEP_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SLEEP(value)))
+#define USB_BWR_ISTAT_SLEEP(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field RESUME[5] (W1C)
+ *
+ * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us.
+ * When not in suspend mode this interrupt must be disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_RESUME field. */
+#define USB_RD_ISTAT_RESUME(base) ((USB_ISTAT_REG(base) & USB_ISTAT_RESUME_MASK) >> USB_ISTAT_RESUME_SHIFT)
+#define USB_BRD_ISTAT_RESUME(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_ISTAT_RESUME(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_RESUME_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_RESUME(value)))
+#define USB_BWR_ISTAT_RESUME(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ATTACH[6] (W1C)
+ *
+ * This bit is set when the USB Module detects an attach of a USB device. This
+ * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a
+ * peripheral is now present and must be configured; it is asserted if there have
+ * been no transitions on the USB for 2.5 us and the current bus state is not SE0."
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ATTACH field. */
+#define USB_RD_ISTAT_ATTACH(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ATTACH_MASK) >> USB_ISTAT_ATTACH_SHIFT)
+#define USB_BRD_ISTAT_ATTACH(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ATTACH_SHIFT))
+
+/*! @brief Set the ATTACH field to a new value. */
+#define USB_WR_ISTAT_ATTACH(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ATTACH_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ATTACH(value)))
+#define USB_BWR_ISTAT_ATTACH(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ATTACH_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field STALL[7] (W1C)
+ *
+ * In Target mode this bit is asserted when a STALL handshake is sent by the
+ * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge
+ * during the handshake phase of a USB transaction.This interrupt can be used to
+ * determine whether the last USB transaction was completed successfully or
+ * stalled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_STALL field. */
+#define USB_RD_ISTAT_STALL(base) ((USB_ISTAT_REG(base) & USB_ISTAT_STALL_MASK) >> USB_ISTAT_STALL_SHIFT)
+#define USB_BRD_ISTAT_STALL(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT))
+
+/*! @brief Set the STALL field to a new value. */
+#define USB_WR_ISTAT_STALL(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_STALL_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK), USB_ISTAT_STALL(value)))
+#define USB_BWR_ISTAT_STALL(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_INTEN - Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_INTEN - Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable fields for each of the interrupt sources within the USB
+ * Module. Setting any of these bits enables the respective interrupt source in the
+ * ISTAT register. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_INTEN register
+ */
+/*@{*/
+#define USB_RD_INTEN(base)       (USB_INTEN_REG(base))
+#define USB_WR_INTEN(base, value) (USB_INTEN_REG(base) = (value))
+#define USB_RMW_INTEN(base, mask, value) (USB_WR_INTEN(base, (USB_RD_INTEN(base) & ~(mask)) | (value)))
+#define USB_SET_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) |  (value)))
+#define USB_CLR_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) & ~(value)))
+#define USB_TOG_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_INTEN bitfields
+ */
+
+/*!
+ * @name Register USB_INTEN, field USBRSTEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the USBRST interrupt.
+ * - 0b1 - Enables the USBRST interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_USBRSTEN field. */
+#define USB_RD_INTEN_USBRSTEN(base) ((USB_INTEN_REG(base) & USB_INTEN_USBRSTEN_MASK) >> USB_INTEN_USBRSTEN_SHIFT)
+#define USB_BRD_INTEN_USBRSTEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT))
+
+/*! @brief Set the USBRSTEN field to a new value. */
+#define USB_WR_INTEN_USBRSTEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_USBRSTEN_MASK, USB_INTEN_USBRSTEN(value)))
+#define USB_BWR_INTEN_USBRSTEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ERROREN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the ERROR interrupt.
+ * - 0b1 - Enables the ERROR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ERROREN field. */
+#define USB_RD_INTEN_ERROREN(base) ((USB_INTEN_REG(base) & USB_INTEN_ERROREN_MASK) >> USB_INTEN_ERROREN_SHIFT)
+#define USB_BRD_INTEN_ERROREN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT))
+
+/*! @brief Set the ERROREN field to a new value. */
+#define USB_WR_INTEN_ERROREN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ERROREN_MASK, USB_INTEN_ERROREN(value)))
+#define USB_BWR_INTEN_ERROREN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SOFTOKEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disbles the SOFTOK interrupt.
+ * - 0b1 - Enables the SOFTOK interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SOFTOKEN field. */
+#define USB_RD_INTEN_SOFTOKEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SOFTOKEN_MASK) >> USB_INTEN_SOFTOKEN_SHIFT)
+#define USB_BRD_INTEN_SOFTOKEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT))
+
+/*! @brief Set the SOFTOKEN field to a new value. */
+#define USB_WR_INTEN_SOFTOKEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SOFTOKEN_MASK, USB_INTEN_SOFTOKEN(value)))
+#define USB_BWR_INTEN_SOFTOKEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field TOKDNEEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the TOKDNE interrupt.
+ * - 0b1 - Enables the TOKDNE interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_TOKDNEEN field. */
+#define USB_RD_INTEN_TOKDNEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_TOKDNEEN_MASK) >> USB_INTEN_TOKDNEEN_SHIFT)
+#define USB_BRD_INTEN_TOKDNEEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT))
+
+/*! @brief Set the TOKDNEEN field to a new value. */
+#define USB_WR_INTEN_TOKDNEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_TOKDNEEN_MASK, USB_INTEN_TOKDNEEN(value)))
+#define USB_BWR_INTEN_TOKDNEEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SLEEPEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the SLEEP interrupt.
+ * - 0b1 - Enables the SLEEP interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SLEEPEN field. */
+#define USB_RD_INTEN_SLEEPEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SLEEPEN_MASK) >> USB_INTEN_SLEEPEN_SHIFT)
+#define USB_BRD_INTEN_SLEEPEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT))
+
+/*! @brief Set the SLEEPEN field to a new value. */
+#define USB_WR_INTEN_SLEEPEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SLEEPEN_MASK, USB_INTEN_SLEEPEN(value)))
+#define USB_BWR_INTEN_SLEEPEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field RESUMEEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the RESUME interrupt.
+ * - 0b1 - Enables the RESUME interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_RESUMEEN field. */
+#define USB_RD_INTEN_RESUMEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_RESUMEEN_MASK) >> USB_INTEN_RESUMEEN_SHIFT)
+#define USB_BRD_INTEN_RESUMEEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT))
+
+/*! @brief Set the RESUMEEN field to a new value. */
+#define USB_WR_INTEN_RESUMEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_RESUMEEN_MASK, USB_INTEN_RESUMEEN(value)))
+#define USB_BWR_INTEN_RESUMEEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ATTACHEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the ATTACH interrupt.
+ * - 0b1 - Enables the ATTACH interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ATTACHEN field. */
+#define USB_RD_INTEN_ATTACHEN(base) ((USB_INTEN_REG(base) & USB_INTEN_ATTACHEN_MASK) >> USB_INTEN_ATTACHEN_SHIFT)
+#define USB_BRD_INTEN_ATTACHEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ATTACHEN_SHIFT))
+
+/*! @brief Set the ATTACHEN field to a new value. */
+#define USB_WR_INTEN_ATTACHEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ATTACHEN_MASK, USB_INTEN_ATTACHEN(value)))
+#define USB_BWR_INTEN_ATTACHEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ATTACHEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field STALLEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Diasbles the STALL interrupt.
+ * - 0b1 - Enables the STALL interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_STALLEN field. */
+#define USB_RD_INTEN_STALLEN(base) ((USB_INTEN_REG(base) & USB_INTEN_STALLEN_MASK) >> USB_INTEN_STALLEN_SHIFT)
+#define USB_BRD_INTEN_STALLEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT))
+
+/*! @brief Set the STALLEN field to a new value. */
+#define USB_WR_INTEN_STALLEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_STALLEN_MASK, USB_INTEN_STALLEN(value)))
+#define USB_BWR_INTEN_STALLEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERRSTAT - Error Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERRSTAT - Error Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error sources within the USB Module.
+ * Each of these bits are qualified with their respective error enable bits. All
+ * bits of this register are logically OR'd together and the result placed in the
+ * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. Each bit is set
+ * as soon as the error condition is detected. Therefore, the interrupt does not
+ * typically correspond with the end of a token being processed. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERRSTAT register
+ */
+/*@{*/
+#define USB_RD_ERRSTAT(base)     (USB_ERRSTAT_REG(base))
+#define USB_WR_ERRSTAT(base, value) (USB_ERRSTAT_REG(base) = (value))
+#define USB_RMW_ERRSTAT(base, mask, value) (USB_WR_ERRSTAT(base, (USB_RD_ERRSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) |  (value)))
+#define USB_CLR_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) & ~(value)))
+#define USB_TOG_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERRSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ERRSTAT, field PIDERR[0] (W1C)
+ *
+ * This bit is set when the PID check field fails.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_PIDERR field. */
+#define USB_RD_ERRSTAT_PIDERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_PIDERR_MASK) >> USB_ERRSTAT_PIDERR_SHIFT)
+#define USB_BRD_ERRSTAT_PIDERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT))
+
+/*! @brief Set the PIDERR field to a new value. */
+#define USB_WR_ERRSTAT_PIDERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_PIDERR(value)))
+#define USB_BWR_ERRSTAT_PIDERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C)
+ *
+ * This error interrupt has two functions. When the USB Module is operating in
+ * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token
+ * packets generated by the host. If set the token packet was rejected due to a
+ * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this
+ * interrupt detects End Of Frame (EOF) error conditions. This occurs when the
+ * USB Module is transmitting or receiving data and the SOF counter reaches zero.
+ * This interrupt is useful when developing USB packet scheduling software to
+ * ensure that no USB transactions cross the start of the next frame.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC5EOF field. */
+#define USB_RD_ERRSTAT_CRC5EOF(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC5EOF_MASK) >> USB_ERRSTAT_CRC5EOF_SHIFT)
+#define USB_BRD_ERRSTAT_CRC5EOF(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5EOF_SHIFT))
+
+/*! @brief Set the CRC5EOF field to a new value. */
+#define USB_WR_ERRSTAT_CRC5EOF(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC5EOF(value)))
+#define USB_BWR_ERRSTAT_CRC5EOF(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5EOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC16[2] (W1C)
+ *
+ * This bit is set when a data packet is rejected due to a CRC16 error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC16 field. */
+#define USB_RD_ERRSTAT_CRC16(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC16_MASK) >> USB_ERRSTAT_CRC16_SHIFT)
+#define USB_BRD_ERRSTAT_CRC16(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT))
+
+/*! @brief Set the CRC16 field to a new value. */
+#define USB_WR_ERRSTAT_CRC16(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC16(value)))
+#define USB_BWR_ERRSTAT_CRC16(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DFN8[3] (W1C)
+ *
+ * This bit is set if the data field received was not 8 bits in length. USB
+ * Specification 1.0 requires that data fields be an integral number of bytes. If the
+ * data field was not an integral number of bytes, this bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DFN8 field. */
+#define USB_RD_ERRSTAT_DFN8(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DFN8_MASK) >> USB_ERRSTAT_DFN8_SHIFT)
+#define USB_BRD_ERRSTAT_DFN8(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT))
+
+/*! @brief Set the DFN8 field to a new value. */
+#define USB_WR_ERRSTAT_DFN8(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DFN8(value)))
+#define USB_BWR_ERRSTAT_DFN8(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTOERR[4] (W1C)
+ *
+ * This bit is set when a bus turnaround timeout error occurs. The USB module
+ * contains a bus turnaround timer that keeps track of the amount of time elapsed
+ * between the token and data phases of a SETUP or OUT TOKEN or the data and
+ * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the
+ * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTOERR field. */
+#define USB_RD_ERRSTAT_BTOERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTOERR_MASK) >> USB_ERRSTAT_BTOERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTOERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT))
+
+/*! @brief Set the BTOERR field to a new value. */
+#define USB_WR_ERRSTAT_BTOERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_BTOERR(value)))
+#define USB_BWR_ERRSTAT_BTOERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DMAERR[5] (W1C)
+ *
+ * This bit is set if the USB Module has requested a DMA access to read a new
+ * BDT but has not been given the bus before it needs to receive or transmit data.
+ * If processing a TX transfer this would cause a transmit data underflow
+ * condition. If processing a RX transfer this would cause a receive data overflow
+ * condition. This interrupt is useful when developing device arbitration hardware for
+ * the microprocessor and the USB module to minimize bus request and bus grant
+ * latency. This bit is also set if a data packet to or from the host is larger
+ * than the buffer size allocated in the BDT. In this case the data packet is
+ * truncated as it is put in buffer memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DMAERR field. */
+#define USB_RD_ERRSTAT_DMAERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DMAERR_MASK) >> USB_ERRSTAT_DMAERR_SHIFT)
+#define USB_BRD_ERRSTAT_DMAERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT))
+
+/*! @brief Set the DMAERR field to a new value. */
+#define USB_WR_ERRSTAT_DMAERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DMAERR(value)))
+#define USB_BWR_ERRSTAT_DMAERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTSERR[7] (W1C)
+ *
+ * This bit is set when a bit stuff error is detected. If set, the corresponding
+ * packet is rejected due to the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTSERR field. */
+#define USB_RD_ERRSTAT_BTSERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTSERR_MASK) >> USB_ERRSTAT_BTSERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTSERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT))
+
+/*! @brief Set the BTSERR field to a new value. */
+#define USB_WR_ERRSTAT_BTSERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTSERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK), USB_ERRSTAT_BTSERR(value)))
+#define USB_BWR_ERRSTAT_BTSERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERREN - Error Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERREN - Error Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error interrupt sources within the USB
+ * module. Setting any of these bits enables the respective interrupt source in
+ * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore,
+ * the interrupt does not typically correspond with the end of a token being
+ * processed. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERREN register
+ */
+/*@{*/
+#define USB_RD_ERREN(base)       (USB_ERREN_REG(base))
+#define USB_WR_ERREN(base, value) (USB_ERREN_REG(base) = (value))
+#define USB_RMW_ERREN(base, mask, value) (USB_WR_ERREN(base, (USB_RD_ERREN(base) & ~(mask)) | (value)))
+#define USB_SET_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) |  (value)))
+#define USB_CLR_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) & ~(value)))
+#define USB_TOG_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERREN bitfields
+ */
+
+/*!
+ * @name Register USB_ERREN, field PIDERREN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the PIDERR interrupt.
+ * - 0b1 - Enters the PIDERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_PIDERREN field. */
+#define USB_RD_ERREN_PIDERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_PIDERREN_MASK) >> USB_ERREN_PIDERREN_SHIFT)
+#define USB_BRD_ERREN_PIDERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT))
+
+/*! @brief Set the PIDERREN field to a new value. */
+#define USB_WR_ERREN_PIDERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_PIDERREN_MASK, USB_ERREN_PIDERREN(value)))
+#define USB_BWR_ERREN_PIDERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC5EOFEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the CRC5/EOF interrupt.
+ * - 0b1 - Enables the CRC5/EOF interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC5EOFEN field. */
+#define USB_RD_ERREN_CRC5EOFEN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC5EOFEN_MASK) >> USB_ERREN_CRC5EOFEN_SHIFT)
+#define USB_BRD_ERREN_CRC5EOFEN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT))
+
+/*! @brief Set the CRC5EOFEN field to a new value. */
+#define USB_WR_ERREN_CRC5EOFEN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC5EOFEN_MASK, USB_ERREN_CRC5EOFEN(value)))
+#define USB_BWR_ERREN_CRC5EOFEN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC16EN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the CRC16 interrupt.
+ * - 0b1 - Enables the CRC16 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC16EN field. */
+#define USB_RD_ERREN_CRC16EN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC16EN_MASK) >> USB_ERREN_CRC16EN_SHIFT)
+#define USB_BRD_ERREN_CRC16EN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT))
+
+/*! @brief Set the CRC16EN field to a new value. */
+#define USB_WR_ERREN_CRC16EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC16EN_MASK, USB_ERREN_CRC16EN(value)))
+#define USB_BWR_ERREN_CRC16EN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DFN8EN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the DFN8 interrupt.
+ * - 0b1 - Enables the DFN8 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DFN8EN field. */
+#define USB_RD_ERREN_DFN8EN(base) ((USB_ERREN_REG(base) & USB_ERREN_DFN8EN_MASK) >> USB_ERREN_DFN8EN_SHIFT)
+#define USB_BRD_ERREN_DFN8EN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT))
+
+/*! @brief Set the DFN8EN field to a new value. */
+#define USB_WR_ERREN_DFN8EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DFN8EN_MASK, USB_ERREN_DFN8EN(value)))
+#define USB_BWR_ERREN_DFN8EN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTOERREN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the BTOERR interrupt.
+ * - 0b1 - Enables the BTOERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTOERREN field. */
+#define USB_RD_ERREN_BTOERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTOERREN_MASK) >> USB_ERREN_BTOERREN_SHIFT)
+#define USB_BRD_ERREN_BTOERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT))
+
+/*! @brief Set the BTOERREN field to a new value. */
+#define USB_WR_ERREN_BTOERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTOERREN_MASK, USB_ERREN_BTOERREN(value)))
+#define USB_BWR_ERREN_BTOERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DMAERREN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the DMAERR interrupt.
+ * - 0b1 - Enables the DMAERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DMAERREN field. */
+#define USB_RD_ERREN_DMAERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_DMAERREN_MASK) >> USB_ERREN_DMAERREN_SHIFT)
+#define USB_BRD_ERREN_DMAERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT))
+
+/*! @brief Set the DMAERREN field to a new value. */
+#define USB_WR_ERREN_DMAERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DMAERREN_MASK, USB_ERREN_DMAERREN(value)))
+#define USB_BWR_ERREN_DMAERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTSERREN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the BTSERR interrupt.
+ * - 0b1 - Enables the BTSERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTSERREN field. */
+#define USB_RD_ERREN_BTSERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTSERREN_MASK) >> USB_ERREN_BTSERREN_SHIFT)
+#define USB_BRD_ERREN_BTSERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT))
+
+/*! @brief Set the BTSERREN field to a new value. */
+#define USB_WR_ERREN_BTSERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTSERREN_MASK, USB_ERREN_BTSERREN(value)))
+#define USB_BWR_ERREN_BTSERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_STAT - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_STAT - Status register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * Reports the transaction status within the USB module. When the processor's
+ * interrupt controller has received a TOKDNE, interrupt the Status Register must
+ * be read to determine the status of the previous endpoint communication. The
+ * data in the status register is valid when TOKDNE interrupt is asserted. The
+ * Status register is actually a read window into a status FIFO maintained by the USB
+ * module. When the USB module uses a BD, it updates the Status register. If
+ * another USB transaction is performed before the TOKDNE interrupt is serviced, the
+ * USB module stores the status of the next transaction in the STAT FIFO. Thus
+ * STAT is actually a four byte FIFO that allows the processor core to process one
+ * transaction while the SIE is processing the next transaction. Clearing the
+ * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents
+ * of the next STAT value. If the data in the STAT holding register is valid, the
+ * SIE immediately reasserts to TOKDNE interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_STAT register
+ */
+/*@{*/
+#define USB_RD_STAT(base)        (USB_STAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_STAT bitfields
+ */
+
+/*!
+ * @name Register USB_STAT, field ODD[2] (RO)
+ *
+ * This bit is set if the last buffer descriptor updated was in the odd bank of
+ * the BDT.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ODD field. */
+#define USB_RD_STAT_ODD(base) ((USB_STAT_REG(base) & USB_STAT_ODD_MASK) >> USB_STAT_ODD_SHIFT)
+#define USB_BRD_STAT_ODD(base) (BITBAND_ACCESS8(&USB_STAT_REG(base), USB_STAT_ODD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field TX[3] (RO)
+ *
+ * Values:
+ * - 0b0 - The most recent transaction was a receive operation.
+ * - 0b1 - The most recent transaction was a transmit operation.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_TX field. */
+#define USB_RD_STAT_TX(base) ((USB_STAT_REG(base) & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT)
+#define USB_BRD_STAT_TX(base) (BITBAND_ACCESS8(&USB_STAT_REG(base), USB_STAT_TX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field ENDP[7:4] (RO)
+ *
+ * This four-bit field encodes the endpoint address that received or transmitted
+ * the previous token. This allows the processor core to determine the BDT entry
+ * that was updated by the last USB transaction.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ENDP field. */
+#define USB_RD_STAT_ENDP(base) ((USB_STAT_REG(base) & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT)
+#define USB_BRD_STAT_ENDP(base) (USB_RD_STAT_ENDP(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CTL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CTL - Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides various control and configuration information for the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_CTL register
+ */
+/*@{*/
+#define USB_RD_CTL(base)         (USB_CTL_REG(base))
+#define USB_WR_CTL(base, value)  (USB_CTL_REG(base) = (value))
+#define USB_RMW_CTL(base, mask, value) (USB_WR_CTL(base, (USB_RD_CTL(base) & ~(mask)) | (value)))
+#define USB_SET_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) |  (value)))
+#define USB_CLR_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) & ~(value)))
+#define USB_TOG_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CTL bitfields
+ */
+
+/*!
+ * @name Register USB_CTL, field USBENSOFEN[0] (RW)
+ *
+ * Setting this bit enables the USB-FS to operate; clearing it disables the
+ * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs.
+ * Therefore, setting this bit resets much of the logic in the SIE. When host mode
+ * is enabled, clearing this bit causes the SIE to stop sending SOF tokens.
+ *
+ * Values:
+ * - 0b0 - Disables the USB Module.
+ * - 0b1 - Enables the USB Module.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_USBENSOFEN field. */
+#define USB_RD_CTL_USBENSOFEN(base) ((USB_CTL_REG(base) & USB_CTL_USBENSOFEN_MASK) >> USB_CTL_USBENSOFEN_SHIFT)
+#define USB_BRD_CTL_USBENSOFEN(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT))
+
+/*! @brief Set the USBENSOFEN field to a new value. */
+#define USB_WR_CTL_USBENSOFEN(base, value) (USB_RMW_CTL(base, USB_CTL_USBENSOFEN_MASK, USB_CTL_USBENSOFEN(value)))
+#define USB_BWR_CTL_USBENSOFEN(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field ODDRST[1] (RW)
+ *
+ * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which
+ * then specifies the EVEN BDT bank.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_ODDRST field. */
+#define USB_RD_CTL_ODDRST(base) ((USB_CTL_REG(base) & USB_CTL_ODDRST_MASK) >> USB_CTL_ODDRST_SHIFT)
+#define USB_BRD_CTL_ODDRST(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT))
+
+/*! @brief Set the ODDRST field to a new value. */
+#define USB_WR_CTL_ODDRST(base, value) (USB_RMW_CTL(base, USB_CTL_ODDRST_MASK, USB_CTL_ODDRST(value)))
+#define USB_BWR_CTL_ODDRST(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field RESUME[2] (RW)
+ *
+ * When set to 1 this bit enables the USB Module to execute resume signaling.
+ * This allows the USB Module to perform remote wake-up. Software must set RESUME
+ * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN
+ * bit is set, the USB module appends a Low Speed End of Packet to the Resume
+ * signaling when the RESUME bit is cleared. For more information on RESUME
+ * signaling see Section 7.1.4.5 of the USB specification version 1.0.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_RESUME field. */
+#define USB_RD_CTL_RESUME(base) ((USB_CTL_REG(base) & USB_CTL_RESUME_MASK) >> USB_CTL_RESUME_SHIFT)
+#define USB_BRD_CTL_RESUME(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESUME_SHIFT))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_CTL_RESUME(base, value) (USB_RMW_CTL(base, USB_CTL_RESUME_MASK, USB_CTL_RESUME(value)))
+#define USB_BWR_CTL_RESUME(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESUME_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field HOSTMODEEN[3] (RW)
+ *
+ * When set to 1, this bit enables the USB Module to operate in Host mode. In
+ * host mode, the USB module performs USB transactions under the programmed control
+ * of the host processor.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_HOSTMODEEN field. */
+#define USB_RD_CTL_HOSTMODEEN(base) ((USB_CTL_REG(base) & USB_CTL_HOSTMODEEN_MASK) >> USB_CTL_HOSTMODEEN_SHIFT)
+#define USB_BRD_CTL_HOSTMODEEN(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_HOSTMODEEN_SHIFT))
+
+/*! @brief Set the HOSTMODEEN field to a new value. */
+#define USB_WR_CTL_HOSTMODEEN(base, value) (USB_RMW_CTL(base, USB_CTL_HOSTMODEEN_MASK, USB_CTL_HOSTMODEEN(value)))
+#define USB_BWR_CTL_HOSTMODEEN(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_HOSTMODEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field RESET[4] (RW)
+ *
+ * Setting this bit enables the USB Module to generate USB reset signaling. This
+ * allows the USB Module to reset USB peripherals. This control signal is only
+ * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the
+ * required amount of time and then clear it to 0 to end reset signaling. For more
+ * information on reset signaling see Section 7.1.4.3 of the USB specification version
+ * 1.0.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_RESET field. */
+#define USB_RD_CTL_RESET(base) ((USB_CTL_REG(base) & USB_CTL_RESET_MASK) >> USB_CTL_RESET_SHIFT)
+#define USB_BRD_CTL_RESET(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESET_SHIFT))
+
+/*! @brief Set the RESET field to a new value. */
+#define USB_WR_CTL_RESET(base, value) (USB_RMW_CTL(base, USB_CTL_RESET_MASK, USB_CTL_RESET(value)))
+#define USB_BWR_CTL_RESET(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW)
+ *
+ * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB
+ * token. Software must not write more token commands to the Token Register when
+ * TOKEN_BUSY is set. Software should check this field before writing any tokens
+ * to the Token Register to ensure that token commands are not lost. In Target
+ * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and
+ * reception. Clearing this bit allows the SIE to continue token processing. This bit
+ * is set by the SIE when a SETUP Token is received allowing software to dequeue
+ * any pending packet transactions in the BDT before resuming token processing.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field. */
+#define USB_RD_CTL_TXSUSPENDTOKENBUSY(base) ((USB_CTL_REG(base) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) >> USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)
+#define USB_BRD_CTL_TXSUSPENDTOKENBUSY(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))
+
+/*! @brief Set the TXSUSPENDTOKENBUSY field to a new value. */
+#define USB_WR_CTL_TXSUSPENDTOKENBUSY(base, value) (USB_RMW_CTL(base, USB_CTL_TXSUSPENDTOKENBUSY_MASK, USB_CTL_TXSUSPENDTOKENBUSY(value)))
+#define USB_BWR_CTL_TXSUSPENDTOKENBUSY(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field SE0[6] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_SE0 field. */
+#define USB_RD_CTL_SE0(base) ((USB_CTL_REG(base) & USB_CTL_SE0_MASK) >> USB_CTL_SE0_SHIFT)
+#define USB_BRD_CTL_SE0(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT))
+
+/*! @brief Set the SE0 field to a new value. */
+#define USB_WR_CTL_SE0(base, value) (USB_RMW_CTL(base, USB_CTL_SE0_MASK, USB_CTL_SE0(value)))
+#define USB_BWR_CTL_SE0(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field JSTATE[7] (RW)
+ *
+ * The polarity of this signal is affected by the current state of LSEN .
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_JSTATE field. */
+#define USB_RD_CTL_JSTATE(base) ((USB_CTL_REG(base) & USB_CTL_JSTATE_MASK) >> USB_CTL_JSTATE_SHIFT)
+#define USB_BRD_CTL_JSTATE(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT))
+
+/*! @brief Set the JSTATE field to a new value. */
+#define USB_WR_CTL_JSTATE(base, value) (USB_RMW_CTL(base, USB_CTL_JSTATE_MASK, USB_CTL_JSTATE(value)))
+#define USB_BWR_CTL_JSTATE(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDR - Address register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDR - Address register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Holds the unique USB address that the USB module decodes when in Peripheral
+ * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module
+ * transmits this address with a TOKEN packet. This enables the USB module to
+ * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1.
+ * The Address register is reset to 0x00 after the reset input becomes active or
+ * the USB module decodes a USB reset signal. This action initializes the Address
+ * register to decode address 0x00 as required by the USB specification.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDR register
+ */
+/*@{*/
+#define USB_RD_ADDR(base)        (USB_ADDR_REG(base))
+#define USB_WR_ADDR(base, value) (USB_ADDR_REG(base) = (value))
+#define USB_RMW_ADDR(base, mask, value) (USB_WR_ADDR(base, (USB_RD_ADDR(base) & ~(mask)) | (value)))
+#define USB_SET_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) |  (value)))
+#define USB_CLR_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) & ~(value)))
+#define USB_TOG_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDR bitfields
+ */
+
+/*!
+ * @name Register USB_ADDR, field ADDR[6:0] (RW)
+ *
+ * Defines the USB address that the USB module decodes in peripheral mode, or
+ * transmits when in host mode.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_ADDR field. */
+#define USB_RD_ADDR_ADDR(base) ((USB_ADDR_REG(base) & USB_ADDR_ADDR_MASK) >> USB_ADDR_ADDR_SHIFT)
+#define USB_BRD_ADDR_ADDR(base) (USB_RD_ADDR_ADDR(base))
+
+/*! @brief Set the ADDR field to a new value. */
+#define USB_WR_ADDR_ADDR(base, value) (USB_RMW_ADDR(base, USB_ADDR_ADDR_MASK, USB_ADDR_ADDR(value)))
+#define USB_BWR_ADDR_ADDR(base, value) (USB_WR_ADDR_ADDR(base, value))
+/*@}*/
+
+/*!
+ * @name Register USB_ADDR, field LSEN[7] (RW)
+ *
+ * Informs the USB module that the next token command written to the token
+ * register must be performed at low speed. This enables the USB module to perform the
+ * necessary preamble required for low-speed data transmissions.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_LSEN field. */
+#define USB_RD_ADDR_LSEN(base) ((USB_ADDR_REG(base) & USB_ADDR_LSEN_MASK) >> USB_ADDR_LSEN_SHIFT)
+#define USB_BRD_ADDR_LSEN(base) (BITBAND_ACCESS8(&USB_ADDR_REG(base), USB_ADDR_LSEN_SHIFT))
+
+/*! @brief Set the LSEN field to a new value. */
+#define USB_WR_ADDR_LSEN(base, value) (USB_RMW_ADDR(base, USB_ADDR_LSEN_MASK, USB_ADDR_LSEN(value)))
+#define USB_BWR_ADDR_LSEN(base, value) (BITBAND_ACCESS8(&USB_ADDR_REG(base), USB_ADDR_LSEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE1 - BDT Page register 1
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE1 - BDT Page register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides address bits 15 through 9 of the base address where the current
+ * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor
+ * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so
+ * bits 8 through 0 of the base address are always zero.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE1 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE1(base)    (USB_BDTPAGE1_REG(base))
+#define USB_WR_BDTPAGE1(base, value) (USB_BDTPAGE1_REG(base) = (value))
+#define USB_RMW_BDTPAGE1(base, mask, value) (USB_WR_BDTPAGE1(base, (USB_RD_BDTPAGE1(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) |  (value)))
+#define USB_CLR_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) & ~(value)))
+#define USB_TOG_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_BDTPAGE1 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW)
+ *
+ * Provides address bits 15 through 9 of the BDT base address.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_BDTPAGE1_BDTBA field. */
+#define USB_RD_BDTPAGE1_BDTBA(base) ((USB_BDTPAGE1_REG(base) & USB_BDTPAGE1_BDTBA_MASK) >> USB_BDTPAGE1_BDTBA_SHIFT)
+#define USB_BRD_BDTPAGE1_BDTBA(base) (USB_RD_BDTPAGE1_BDTBA(base))
+
+/*! @brief Set the BDTBA field to a new value. */
+#define USB_WR_BDTPAGE1_BDTBA(base, value) (USB_RMW_BDTPAGE1(base, USB_BDTPAGE1_BDTBA_MASK, USB_BDTPAGE1_BDTBA(value)))
+#define USB_BWR_BDTPAGE1_BDTBA(base, value) (USB_WR_BDTPAGE1_BDTBA(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUML - Frame Number register Low
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUML - Frame Number register Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUML register
+ */
+/*@{*/
+#define USB_RD_FRMNUML(base)     (USB_FRMNUML_REG(base))
+#define USB_WR_FRMNUML(base, value) (USB_FRMNUML_REG(base) = (value))
+#define USB_RMW_FRMNUML(base, mask, value) (USB_WR_FRMNUML(base, (USB_RD_FRMNUML(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) |  (value)))
+#define USB_CLR_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) & ~(value)))
+#define USB_TOG_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUMH - Frame Number register High
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUMH - Frame Number register High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUMH register
+ */
+/*@{*/
+#define USB_RD_FRMNUMH(base)     (USB_FRMNUMH_REG(base))
+#define USB_WR_FRMNUMH(base, value) (USB_FRMNUMH_REG(base) = (value))
+#define USB_RMW_FRMNUMH(base, mask, value) (USB_WR_FRMNUMH(base, (USB_RD_FRMNUMH(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) |  (value)))
+#define USB_CLR_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) & ~(value)))
+#define USB_TOG_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_FRMNUMH bitfields
+ */
+
+/*!
+ * @name Register USB_FRMNUMH, field FRM[2:0] (RW)
+ *
+ * This 3-bit field and the 8-bit field in the Frame Number Register Low are
+ * used to compute the address where the current Buffer Descriptor Table (BDT)
+ * resides in system memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_FRMNUMH_FRM field. */
+#define USB_RD_FRMNUMH_FRM(base) ((USB_FRMNUMH_REG(base) & USB_FRMNUMH_FRM_MASK) >> USB_FRMNUMH_FRM_SHIFT)
+#define USB_BRD_FRMNUMH_FRM(base) (USB_RD_FRMNUMH_FRM(base))
+
+/*! @brief Set the FRM field to a new value. */
+#define USB_WR_FRMNUMH_FRM(base, value) (USB_RMW_FRMNUMH(base, USB_FRMNUMH_FRM_MASK, USB_FRMNUMH_FRM(value)))
+#define USB_BWR_FRMNUMH_FRM(base, value) (USB_WR_FRMNUMH_FRM(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_TOKEN - Token register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_TOKEN - Token register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the
+ * software needs to execute a USB transaction to a peripheral, it writes the
+ * TOKEN type and endpoint to this register. After this register has been written,
+ * the USB module begins the specified USB transaction to the address contained in
+ * the address register. The processor core must always check that the
+ * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register.
+ * This ensures that the token commands are not overwritten before they can be
+ * executed. The address register and endpoint control register 0 are also used when
+ * performing a token command and therefore must also be written before the
+ * Token Register. The address register is used to select the USB peripheral address
+ * transmitted by the token command. The endpoint control register determines the
+ * handshake and retry policies used during the transfer.
+ */
+/*!
+ * @name Constants and macros for entire USB_TOKEN register
+ */
+/*@{*/
+#define USB_RD_TOKEN(base)       (USB_TOKEN_REG(base))
+#define USB_WR_TOKEN(base, value) (USB_TOKEN_REG(base) = (value))
+#define USB_RMW_TOKEN(base, mask, value) (USB_WR_TOKEN(base, (USB_RD_TOKEN(base) & ~(mask)) | (value)))
+#define USB_SET_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) |  (value)))
+#define USB_CLR_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) & ~(value)))
+#define USB_TOG_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_TOKEN bitfields
+ */
+
+/*!
+ * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW)
+ *
+ * Holds the Endpoint address for the token command. The four bit value written
+ * must be a valid endpoint.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_TOKEN_TOKENENDPT field. */
+#define USB_RD_TOKEN_TOKENENDPT(base) ((USB_TOKEN_REG(base) & USB_TOKEN_TOKENENDPT_MASK) >> USB_TOKEN_TOKENENDPT_SHIFT)
+#define USB_BRD_TOKEN_TOKENENDPT(base) (USB_RD_TOKEN_TOKENENDPT(base))
+
+/*! @brief Set the TOKENENDPT field to a new value. */
+#define USB_WR_TOKEN_TOKENENDPT(base, value) (USB_RMW_TOKEN(base, USB_TOKEN_TOKENENDPT_MASK, USB_TOKEN_TOKENENDPT(value)))
+#define USB_BWR_TOKEN_TOKENENDPT(base, value) (USB_WR_TOKEN_TOKENENDPT(base, value))
+/*@}*/
+
+/*!
+ * @name Register USB_TOKEN, field TOKENPID[7:4] (RW)
+ *
+ * Contains the token type executed by the USB module.
+ *
+ * Values:
+ * - 0b0001 - OUT Token. USB Module performs an OUT (TX) transaction.
+ * - 0b1001 - IN Token. USB Module performs an In (RX) transaction.
+ * - 0b1101 - SETUP Token. USB Module performs a SETUP (TX) transaction
+ */
+/*@{*/
+/*! @brief Read current value of the USB_TOKEN_TOKENPID field. */
+#define USB_RD_TOKEN_TOKENPID(base) ((USB_TOKEN_REG(base) & USB_TOKEN_TOKENPID_MASK) >> USB_TOKEN_TOKENPID_SHIFT)
+#define USB_BRD_TOKEN_TOKENPID(base) (USB_RD_TOKEN_TOKENPID(base))
+
+/*! @brief Set the TOKENPID field to a new value. */
+#define USB_WR_TOKEN_TOKENPID(base, value) (USB_RMW_TOKEN(base, USB_TOKEN_TOKENPID_MASK, USB_TOKEN_TOKENPID(value)))
+#define USB_BWR_TOKEN_TOKENPID(base, value) (USB_WR_TOKEN_TOKENPID(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_SOFTHLD - SOF Threshold register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_SOFTHLD - SOF Threshold register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in
+ * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The
+ * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with
+ * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF)
+ * token is transmitted. The SOF threshold register is used to program the number
+ * of USB byte times before the SOF to stop initiating token packet transactions.
+ * This register must be set to a value that ensures that other packets are not
+ * actively being transmitted when the SOF time counts to zero. When the SOF
+ * counter reaches the threshold value, no more tokens are transmitted until after the
+ * SOF has been transmitted. The value programmed into the threshold register
+ * must reserve enough time to ensure the worst case transaction completes. In
+ * general the worst case transaction is an IN token followed by a data packet from
+ * the target followed by the response from the host. The actual time required is
+ * a function of the maximum packet size on the bus. Typical values for the SOF
+ * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26;
+ * 8-byte packets=18.
+ */
+/*!
+ * @name Constants and macros for entire USB_SOFTHLD register
+ */
+/*@{*/
+#define USB_RD_SOFTHLD(base)     (USB_SOFTHLD_REG(base))
+#define USB_WR_SOFTHLD(base, value) (USB_SOFTHLD_REG(base) = (value))
+#define USB_RMW_SOFTHLD(base, mask, value) (USB_WR_SOFTHLD(base, (USB_RD_SOFTHLD(base) & ~(mask)) | (value)))
+#define USB_SET_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) |  (value)))
+#define USB_CLR_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) & ~(value)))
+#define USB_TOG_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE2 - BDT Page Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE2 - BDT Page Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE2 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE2(base)    (USB_BDTPAGE2_REG(base))
+#define USB_WR_BDTPAGE2(base, value) (USB_BDTPAGE2_REG(base) = (value))
+#define USB_RMW_BDTPAGE2(base, mask, value) (USB_WR_BDTPAGE2(base, (USB_RD_BDTPAGE2(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) |  (value)))
+#define USB_CLR_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) & ~(value)))
+#define USB_TOG_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE3 - BDT Page Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE3 - BDT Page Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE3 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE3(base)    (USB_BDTPAGE3_REG(base))
+#define USB_WR_BDTPAGE3(base, value) (USB_BDTPAGE3_REG(base) = (value))
+#define USB_RMW_BDTPAGE3(base, mask, value) (USB_WR_BDTPAGE3(base, (USB_RD_BDTPAGE3(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) |  (value)))
+#define USB_CLR_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) & ~(value)))
+#define USB_TOG_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ENDPT - Endpoint Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ENDPT - Endpoint Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains the endpoint control bits for each of the 16 endpoints available
+ * within the USB module for a decoded address. The format for these registers is
+ * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control
+ * pipe 0, which is required for all USB functions. Therefore, after a USBRST
+ * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode
+ * ENDPT0 is used to determine the handshake, retry and low speed
+ * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
+ * bit should be 1. For Isochronous transfers it should be 0. Common values to
+ * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
+ * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and
+ * EPTXEN define if an endpoint is enabled and define the direction of the endpoint.
+ * The endpoint enable/direction control is defined in the following table.
+ * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint
+ * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only
+ * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and
+ * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP)
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire USB_ENDPT register
+ */
+/*@{*/
+#define USB_RD_ENDPT(base, index) (USB_ENDPT_REG(base, index))
+#define USB_WR_ENDPT(base, index, value) (USB_ENDPT_REG(base, index) = (value))
+#define USB_RMW_ENDPT(base, index, mask, value) (USB_WR_ENDPT(base, index, (USB_RD_ENDPT(base, index) & ~(mask)) | (value)))
+#define USB_SET_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) |  (value)))
+#define USB_CLR_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) & ~(value)))
+#define USB_TOG_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ENDPT bitfields
+ */
+
+/*!
+ * @name Register USB_ENDPT, field EPHSHK[0] (RW)
+ *
+ * When set this bit enables an endpoint to perform handshaking during a
+ * transaction to this endpoint. This bit is generally 1 unless the endpoint is
+ * Isochronous.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPHSHK field. */
+#define USB_RD_ENDPT_EPHSHK(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPHSHK_MASK) >> USB_ENDPT_EPHSHK_SHIFT)
+#define USB_BRD_ENDPT_EPHSHK(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT))
+
+/*! @brief Set the EPHSHK field to a new value. */
+#define USB_WR_ENDPT_EPHSHK(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPHSHK_MASK, USB_ENDPT_EPHSHK(value)))
+#define USB_BWR_ENDPT_EPHSHK(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPSTALL[1] (RW)
+ *
+ * When set this bit indicates that the endpoint is called. This bit has
+ * priority over all other control bits in the EndPoint Enable Register, but it is only
+ * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB
+ * Module to return a STALL handshake. After an endpoint is stalled it requires
+ * intervention from the Host Controller.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPSTALL field. */
+#define USB_RD_ENDPT_EPSTALL(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPSTALL_MASK) >> USB_ENDPT_EPSTALL_SHIFT)
+#define USB_BRD_ENDPT_EPSTALL(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT))
+
+/*! @brief Set the EPSTALL field to a new value. */
+#define USB_WR_ENDPT_EPSTALL(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPSTALL_MASK, USB_ENDPT_EPSTALL(value)))
+#define USB_BWR_ENDPT_EPSTALL(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPTXEN[2] (RW)
+ *
+ * This bit, when set, enables the endpoint for TX transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPTXEN field. */
+#define USB_RD_ENDPT_EPTXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPTXEN_MASK) >> USB_ENDPT_EPTXEN_SHIFT)
+#define USB_BRD_ENDPT_EPTXEN(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT))
+
+/*! @brief Set the EPTXEN field to a new value. */
+#define USB_WR_ENDPT_EPTXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPTXEN_MASK, USB_ENDPT_EPTXEN(value)))
+#define USB_BWR_ENDPT_EPTXEN(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPRXEN[3] (RW)
+ *
+ * This bit, when set, enables the endpoint for RX transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPRXEN field. */
+#define USB_RD_ENDPT_EPRXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPRXEN_MASK) >> USB_ENDPT_EPRXEN_SHIFT)
+#define USB_BRD_ENDPT_EPRXEN(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT))
+
+/*! @brief Set the EPRXEN field to a new value. */
+#define USB_WR_ENDPT_EPRXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPRXEN_MASK, USB_ENDPT_EPRXEN(value)))
+#define USB_BWR_ENDPT_EPRXEN(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPCTLDIS[4] (RW)
+ *
+ * This bit, when set, disables control (SETUP) transfers. When cleared, control
+ * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
+ * are also set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPCTLDIS field. */
+#define USB_RD_ENDPT_EPCTLDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPCTLDIS_MASK) >> USB_ENDPT_EPCTLDIS_SHIFT)
+#define USB_BRD_ENDPT_EPCTLDIS(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT))
+
+/*! @brief Set the EPCTLDIS field to a new value. */
+#define USB_WR_ENDPT_EPCTLDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPCTLDIS_MASK, USB_ENDPT_EPCTLDIS(value)))
+#define USB_BWR_ENDPT_EPCTLDIS(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field RETRYDIS[6] (RW)
+ *
+ * This is a Host mode only bit and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed
+ * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID
+ * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When
+ * this bit is cleared, NAKed transactions are retried in hardware. This bit must
+ * be set when the host is attempting to poll an interrupt endpoint.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_RETRYDIS field. */
+#define USB_RD_ENDPT_RETRYDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_RETRYDIS_MASK) >> USB_ENDPT_RETRYDIS_SHIFT)
+#define USB_BRD_ENDPT_RETRYDIS(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_RETRYDIS_SHIFT))
+
+/*! @brief Set the RETRYDIS field to a new value. */
+#define USB_WR_ENDPT_RETRYDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_RETRYDIS_MASK, USB_ENDPT_RETRYDIS(value)))
+#define USB_BWR_ENDPT_RETRYDIS(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_RETRYDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field HOSTWOHUB[7] (RW)
+ *
+ * This is a Host mode only field and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a
+ * directly connected low speed device. When cleared, the host produces the
+ * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed
+ * device as required to communicate with a low speed device through a hub.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_HOSTWOHUB field. */
+#define USB_RD_ENDPT_HOSTWOHUB(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_HOSTWOHUB_MASK) >> USB_ENDPT_HOSTWOHUB_SHIFT)
+#define USB_BRD_ENDPT_HOSTWOHUB(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_HOSTWOHUB_SHIFT))
+
+/*! @brief Set the HOSTWOHUB field to a new value. */
+#define USB_WR_ENDPT_HOSTWOHUB(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_HOSTWOHUB_MASK, USB_ENDPT_HOSTWOHUB(value)))
+#define USB_BWR_ENDPT_HOSTWOHUB(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_HOSTWOHUB_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBCTRL - USB Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBCTRL - USB Control register (RW)
+ *
+ * Reset value: 0xC0U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBCTRL register
+ */
+/*@{*/
+#define USB_RD_USBCTRL(base)     (USB_USBCTRL_REG(base))
+#define USB_WR_USBCTRL(base, value) (USB_USBCTRL_REG(base) = (value))
+#define USB_RMW_USBCTRL(base, mask, value) (USB_WR_USBCTRL(base, (USB_RD_USBCTRL(base) & ~(mask)) | (value)))
+#define USB_SET_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) |  (value)))
+#define USB_CLR_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) & ~(value)))
+#define USB_TOG_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBCTRL bitfields
+ */
+
+/*!
+ * @name Register USB_USBCTRL, field PDE[6] (RW)
+ *
+ * Enables the weak pulldowns on the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - Weak pulldowns are disabled on D+ and D-.
+ * - 0b1 - Weak pulldowns are enabled on D+ and D-.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_PDE field. */
+#define USB_RD_USBCTRL_PDE(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_PDE_MASK) >> USB_USBCTRL_PDE_SHIFT)
+#define USB_BRD_USBCTRL_PDE(base) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT))
+
+/*! @brief Set the PDE field to a new value. */
+#define USB_WR_USBCTRL_PDE(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_PDE_MASK, USB_USBCTRL_PDE(value)))
+#define USB_BWR_USBCTRL_PDE(base, value) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_USBCTRL, field SUSP[7] (RW)
+ *
+ * Places the USB transceiver into the suspend state.
+ *
+ * Values:
+ * - 0b0 - USB transceiver is not in suspend state.
+ * - 0b1 - USB transceiver is in suspend state.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_SUSP field. */
+#define USB_RD_USBCTRL_SUSP(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_SUSP_MASK) >> USB_USBCTRL_SUSP_SHIFT)
+#define USB_BRD_USBCTRL_SUSP(base) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT))
+
+/*! @brief Set the SUSP field to a new value. */
+#define USB_WR_USBCTRL_SUSP(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_SUSP_MASK, USB_USBCTRL_SUSP(value)))
+#define USB_BWR_USBCTRL_SUSP(base, value) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OBSERVE - USB OTG Observe register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OBSERVE - USB OTG Observe register (RO)
+ *
+ * Reset value: 0x50U
+ *
+ * Provides visibility on the state of the pull-ups and pull-downs at the
+ * transceiver. Useful when interfacing to an external OTG control module via a serial
+ * interface.
+ */
+/*!
+ * @name Constants and macros for entire USB_OBSERVE register
+ */
+/*@{*/
+#define USB_RD_OBSERVE(base)     (USB_OBSERVE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OBSERVE bitfields
+ */
+
+/*!
+ * @name Register USB_OBSERVE, field DMPD[4] (RO)
+ *
+ * Provides observability of the D- Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D- pulldown disabled.
+ * - 0b1 - D- pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DMPD field. */
+#define USB_RD_OBSERVE_DMPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DMPD_MASK) >> USB_OBSERVE_DMPD_SHIFT)
+#define USB_BRD_OBSERVE_DMPD(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DMPD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPD[6] (RO)
+ *
+ * Provides observability of the D+ Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D+ pulldown disabled.
+ * - 0b1 - D+ pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPD field. */
+#define USB_RD_OBSERVE_DPPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPD_MASK) >> USB_OBSERVE_DPPD_SHIFT)
+#define USB_BRD_OBSERVE_DPPD(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPU[7] (RO)
+ *
+ * Provides observability of the D+ Pullup enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D+ pullup disabled.
+ * - 0b1 - D+ pullup enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPU field. */
+#define USB_RD_OBSERVE_DPPU(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPU_MASK) >> USB_OBSERVE_DPPU_SHIFT)
+#define USB_BRD_OBSERVE_DPPU(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPU_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CONTROL - USB OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CONTROL - USB OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_CONTROL register
+ */
+/*@{*/
+#define USB_RD_CONTROL(base)     (USB_CONTROL_REG(base))
+#define USB_WR_CONTROL(base, value) (USB_CONTROL_REG(base) = (value))
+#define USB_RMW_CONTROL(base, mask, value) (USB_WR_CONTROL(base, (USB_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USB_SET_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) |  (value)))
+#define USB_CLR_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) & ~(value)))
+#define USB_TOG_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW)
+ *
+ * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG
+ * device mode.
+ *
+ * Values:
+ * - 0b0 - DP Pullup in non-OTG device mode is not enabled.
+ * - 0b1 - DP Pullup in non-OTG device mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field. */
+#define USB_RD_CONTROL_DPPULLUPNONOTG(base) ((USB_CONTROL_REG(base) & USB_CONTROL_DPPULLUPNONOTG_MASK) >> USB_CONTROL_DPPULLUPNONOTG_SHIFT)
+#define USB_BRD_CONTROL_DPPULLUPNONOTG(base) (BITBAND_ACCESS8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT))
+
+/*! @brief Set the DPPULLUPNONOTG field to a new value. */
+#define USB_WR_CONTROL_DPPULLUPNONOTG(base, value) (USB_RMW_CONTROL(base, USB_CONTROL_DPPULLUPNONOTG_MASK, USB_CONTROL_DPPULLUPNONOTG(value)))
+#define USB_BWR_CONTROL_DPPULLUPNONOTG(base, value) (BITBAND_ACCESS8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBTRC0 - USB Transceiver Control register 0
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBTRC0 - USB Transceiver Control register 0 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Includes signals for basic operation of the on-chip USB Full Speed
+ * transceiver and configuration of the USB data connection that are not otherwise included
+ * in the USB Full Speed controller registers.
+ */
+/*!
+ * @name Constants and macros for entire USB_USBTRC0 register
+ */
+/*@{*/
+#define USB_RD_USBTRC0(base)     (USB_USBTRC0_REG(base))
+#define USB_WR_USBTRC0(base, value) (USB_USBTRC0_REG(base) = (value))
+#define USB_RMW_USBTRC0(base, mask, value) (USB_WR_USBTRC0(base, (USB_RD_USBTRC0(base) & ~(mask)) | (value)))
+#define USB_SET_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) |  (value)))
+#define USB_CLR_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) & ~(value)))
+#define USB_TOG_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBTRC0 bitfields
+ */
+
+/*!
+ * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No interrupt was generated.
+ * - 0b1 - Interrupt was generated because of the USB asynchronous interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field. */
+#define USB_RD_USBTRC0_USB_RESUME_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_RESUME_INT_MASK) >> USB_USBTRC0_USB_RESUME_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_RESUME_INT(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_RESUME_INT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field SYNC_DET[1] (RO)
+ *
+ * Values:
+ * - 0b0 - Synchronous interrupt has not been detected.
+ * - 0b1 - Synchronous interrupt has been detected.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_SYNC_DET field. */
+#define USB_RD_USBTRC0_SYNC_DET(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_SYNC_DET_MASK) >> USB_USBTRC0_SYNC_DET_SHIFT)
+#define USB_BRD_USBTRC0_SYNC_DET(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_SYNC_DET_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO)
+ *
+ * This read-only field will be set to value high at 1'b1 when any of USB clock
+ * recovery interrupt conditions are detected and those interrupts are unmasked.
+ * For customer use the only unmasked USB clock recovery interrupt condition
+ * results from an overflow of the frequency trim setting values indicating that the
+ * frequency trim calculated is out of the adjustment range of the IRC48M output
+ * clock. To clear this bit after it has been set, Write 0xFF to register
+ * USB_CLK_RECOVER_INT_STATUS.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field. */
+#define USB_RD_USBTRC0_USB_CLK_RECOVERY_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) >> USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_CLK_RECOVERY_INT(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESMEN[5] (RW)
+ *
+ * This bit, when set, allows the USB module to send an asynchronous wakeup
+ * event to the MCU upon detection of resume signaling on the USB bus. The MCU then
+ * re-enables clocks to the USB module. It is used for low-power suspend mode when
+ * USB module clocks are stopped or the USB transceiver is in Suspend mode.
+ * Async wakeup only works in device mode.
+ *
+ * Values:
+ * - 0b0 - USB asynchronous wakeup from suspend mode disabled.
+ * - 0b1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous
+ *     resume interrupt differs from the synchronous resume interrupt in that it
+ *     asynchronously detects K-state using the unfiltered state of the D+ and D-
+ *     pins. This interrupt should only be enabled when the Transceiver is
+ *     suspended.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USBRESMEN field. */
+#define USB_RD_USBTRC0_USBRESMEN(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USBRESMEN_MASK) >> USB_USBTRC0_USBRESMEN_SHIFT)
+#define USB_BRD_USBTRC0_USBRESMEN(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT))
+
+/*! @brief Set the USBRESMEN field to a new value. */
+#define USB_WR_USBTRC0_USBRESMEN(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESMEN_MASK, USB_USBTRC0_USBRESMEN(value)))
+#define USB_BWR_USBTRC0_USBRESMEN(base, value) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESET[7] (WO)
+ *
+ * Generates a hard reset to USBOTG. After this bit is set and the reset occurs,
+ * this bit is automatically cleared. This bit is always read as zero. Wait two
+ * USB clock cycles after setting this bit.
+ *
+ * Values:
+ * - 0b0 - Normal USB module operation.
+ * - 0b1 - Returns the USB module to its reset state.
+ */
+/*@{*/
+/*! @brief Set the USBRESET field to a new value. */
+#define USB_WR_USBTRC0_USBRESET(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESET_MASK, USB_USBTRC0_USBRESET(value)))
+#define USB_BWR_USBTRC0_USBRESET(base, value) (USB_WR_USBTRC0_USBRESET(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBFRMADJUST - Frame Adjust Register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBFRMADJUST - Frame Adjust Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBFRMADJUST register
+ */
+/*@{*/
+#define USB_RD_USBFRMADJUST(base) (USB_USBFRMADJUST_REG(base))
+#define USB_WR_USBFRMADJUST(base, value) (USB_USBFRMADJUST_REG(base) = (value))
+#define USB_RMW_USBFRMADJUST(base, mask, value) (USB_WR_USBFRMADJUST(base, (USB_RD_USBFRMADJUST(base) & ~(mask)) | (value)))
+#define USB_SET_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) |  (value)))
+#define USB_CLR_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) & ~(value)))
+#define USB_TOG_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Signals in this register control the crystal-less USB clock mode in which the
+ * internal IRC48M oscillator is tuned to match the clock extracted from the
+ * incoming USB data stream. The IRC48M internal oscillator module must be enabled
+ * in register USB_CLK_RECOVER_IRC_EN for this mode.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_CTRL(base) (USB_CLK_RECOVER_CTRL_REG(base))
+#define USB_WR_CLK_RECOVER_CTRL(base, value) (USB_CLK_RECOVER_CTRL_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_CTRL(base, mask, value) (USB_WR_CLK_RECOVER_CTRL(base, (USB_RD_CLK_RECOVER_CTRL(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW)
+ *
+ * IRC48 has a default trim fine value whose default value is factory trimmed
+ * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz
+ * and keeps updating the trim fine value accordingly
+ *
+ * Values:
+ * - 0b0 - Trim fine adjustment always works based on the previous updated trim
+ *     fine value (default)
+ * - 0b1 - Trim fine restarts from the IFR trim value whenever
+ *     bus_reset/bus_resume is detected or module enable is desasserted
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))
+
+/*! @brief Set the RESTART_IFRTRIM_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW)
+ *
+ * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock.
+ * It has two phases after user enables clock_recover_en bit, rough phase and
+ * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine
+ * value is different during these two phases. The step in rough phase is larger
+ * than that in tracking phase. Switch back to rough stage whenever USB bus reset
+ * or bus resume occurs.
+ *
+ * Values:
+ * - 0b0 - Always works in tracking phase after the 1st time rough to track
+ *     transition (default)
+ * - 0b1 - Go back to rough stage whenever bus reset or bus resume occurs
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))
+
+/*! @brief Set the RESET_RESUME_ROUGH_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW)
+ *
+ * This bit must be enabled if user wants to use the crystal-less USB mode for
+ * the Full Speed USB controller and transceiver. This bit should not be set for
+ * USB host mode or OTG.
+ *
+ * Values:
+ * - 0b0 - Disable clock recovery block (default)
+ * - 0b1 - Enable clock recovery block
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) >> USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))
+
+/*! @brief Set the CLOCK_RECOVER_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * Controls basic operation of the on-chip IRC48M module used to produce nominal
+ * 48MHz clocks for USB crystal-less operation and other functions. See
+ * additional information about the IRC48M operation in the Clock Distribution chapter.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_IRC_EN(base) (USB_CLK_RECOVER_IRC_EN_REG(base))
+#define USB_WR_CLK_RECOVER_IRC_EN(base, value) (USB_CLK_RECOVER_IRC_EN_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_IRC_EN(base, mask, value) (USB_WR_CLK_RECOVER_IRC_EN(base, (USB_RD_CLK_RECOVER_IRC_EN(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW)
+ *
+ * This bit is used to enable the local analog regulator for IRC48Mhz module.
+ * This bit must be set if user wants to use the crystal-less USB clock
+ * configuration.
+ *
+ * Values:
+ * - 0b0 - IRC48M local regulator is disabled
+ * - 0b1 - IRC48M local regulator is enabled (default)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_REG_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_REG_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))
+
+/*! @brief Set the REG_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_REG_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_REG_EN_MASK, USB_CLK_RECOVER_IRC_EN_REG_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_REG_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
+ *
+ * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
+ * crystal-less USB. It can only be used for FS USB device mode operation. This
+ * bit must be set before using the crystal-less USB clock configuration.
+ *
+ * Values:
+ * - 0b0 - Disable the IRC48M module (default)
+ * - 0b1 - Enable the IRC48M module
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_IRC_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_IRC_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))
+
+/*! @brief Set the IRC_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK, USB_CLK_RECOVER_IRC_EN_IRC_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * A Write operation with value high at 1'b1 on any combination of individual
+ * bits will clear those bits.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_INT_STATUS(base) (USB_CLK_RECOVER_INT_STATUS_REG(base))
+#define USB_WR_CLK_RECOVER_INT_STATUS(base, value) (USB_CLK_RECOVER_INT_STATUS_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_INT_STATUS(base, mask, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, (USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C)
+ *
+ * Indicates that the USB clock recovery algorithm has detected that the
+ * frequency trim adjustment needed for the IRC48M output clock is outside the available
+ * TRIM_FINE adjustment range for the IRC48M module.
+ *
+ * Values:
+ * - 0b0 - No interrupt is reported
+ * - 0b1 - Unmasked interrupt has been generated
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field. */
+#define USB_RD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) ((USB_CLK_RECOVER_INT_STATUS_REG(base) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) >> USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)
+#define USB_BRD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))
+
+/*! @brief Set the OVF_ERROR field to a new value. */
+#define USB_WR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (USB_RMW_CLK_RECOVER_INT_STATUS(base, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(value)))
+#define USB_BWR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 USBDCD
+ *
+ * USB Device Charger Detection module
+ *
+ * Registers defined in this header file:
+ * - USBDCD_CONTROL - Control register
+ * - USBDCD_CLOCK - Clock register
+ * - USBDCD_STATUS - Status register
+ * - USBDCD_TIMER0 - TIMER0 register
+ * - USBDCD_TIMER1 - TIMER1 register
+ * - USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ * - USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ */
+
+#define USBDCD_INSTANCE_COUNT (1U) /*!< Number of instances of the USBDCD module. */
+#define USBDCD_IDX (0U) /*!< Instance number for USBDCD. */
+
+/*******************************************************************************
+ * USBDCD_CONTROL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_CONTROL - Control register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Contains the control and interrupt bit fields.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_CONTROL register
+ */
+/*@{*/
+#define USBDCD_RD_CONTROL(base)  (USBDCD_CONTROL_REG(base))
+#define USBDCD_WR_CONTROL(base, value) (USBDCD_CONTROL_REG(base) = (value))
+#define USBDCD_RMW_CONTROL(base, mask, value) (USBDCD_WR_CONTROL(base, (USBDCD_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USBDCD_SET_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) |  (value)))
+#define USBDCD_CLR_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) & ~(value)))
+#define USBDCD_TOG_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CONTROL, field IACK[0] (WORZ)
+ *
+ * Determines whether the interrupt is cleared.
+ *
+ * Values:
+ * - 0b0 - Do not clear the interrupt.
+ * - 0b1 - Clear the IF bit (interrupt flag).
+ */
+/*@{*/
+/*! @brief Set the IACK field to a new value. */
+#define USBDCD_WR_CONTROL_IACK(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_IACK_MASK, USBDCD_CONTROL_IACK(value)))
+#define USBDCD_BWR_CONTROL_IACK(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field IF[8] (RO)
+ *
+ * Determines whether an interrupt is pending.
+ *
+ * Values:
+ * - 0b0 - No interrupt is pending.
+ * - 0b1 - An interrupt is pending.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_IF field. */
+#define USBDCD_RD_CONTROL_IF(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_IF_MASK) >> USBDCD_CONTROL_IF_SHIFT)
+#define USBDCD_BRD_CONTROL_IF(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field IE[16] (RW)
+ *
+ * Enables/disables interrupts to the system.
+ *
+ * Values:
+ * - 0b0 - Disable interrupts to the system.
+ * - 0b1 - Enable interrupts to the system.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_IE field. */
+#define USBDCD_RD_CONTROL_IE(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_IE_MASK) >> USBDCD_CONTROL_IE_SHIFT)
+#define USBDCD_BRD_CONTROL_IE(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IE_SHIFT))
+
+/*! @brief Set the IE field to a new value. */
+#define USBDCD_WR_CONTROL_IE(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_IE_MASK, USBDCD_CONTROL_IE(value)))
+#define USBDCD_BWR_CONTROL_IE(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field BC12[17] (RW)
+ *
+ * BC1.2 compatibility. This bit cannot be changed after start detection.
+ *
+ * Values:
+ * - 0b0 - Compatible with BC1.1 (default)
+ * - 0b1 - Compatible with BC1.2
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_BC12 field. */
+#define USBDCD_RD_CONTROL_BC12(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_BC12_MASK) >> USBDCD_CONTROL_BC12_SHIFT)
+#define USBDCD_BRD_CONTROL_BC12(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_BC12_SHIFT))
+
+/*! @brief Set the BC12 field to a new value. */
+#define USBDCD_WR_CONTROL_BC12(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_BC12_MASK, USBDCD_CONTROL_BC12(value)))
+#define USBDCD_BWR_CONTROL_BC12(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_BC12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field START[24] (WORZ)
+ *
+ * Determines whether the charger detection sequence is initiated.
+ *
+ * Values:
+ * - 0b0 - Do not start the sequence. Writes of this value have no effect.
+ * - 0b1 - Initiate the charger detection sequence. If the sequence is already
+ *     running, writes of this value have no effect.
+ */
+/*@{*/
+/*! @brief Set the START field to a new value. */
+#define USBDCD_WR_CONTROL_START(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_START_MASK, USBDCD_CONTROL_START(value)))
+#define USBDCD_BWR_CONTROL_START(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_START_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field SR[25] (WORZ)
+ *
+ * Determines whether a software reset is performed.
+ *
+ * Values:
+ * - 0b0 - Do not perform a software reset.
+ * - 0b1 - Perform a software reset.
+ */
+/*@{*/
+/*! @brief Set the SR field to a new value. */
+#define USBDCD_WR_CONTROL_SR(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_SR_MASK, USBDCD_CONTROL_SR(value)))
+#define USBDCD_BWR_CONTROL_SR(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_SR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_CLOCK - Clock register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_CLOCK - Clock register (RW)
+ *
+ * Reset value: 0x000000C1U
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_CLOCK register
+ */
+/*@{*/
+#define USBDCD_RD_CLOCK(base)    (USBDCD_CLOCK_REG(base))
+#define USBDCD_WR_CLOCK(base, value) (USBDCD_CLOCK_REG(base) = (value))
+#define USBDCD_RMW_CLOCK(base, mask, value) (USBDCD_WR_CLOCK(base, (USBDCD_RD_CLOCK(base) & ~(mask)) | (value)))
+#define USBDCD_SET_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) |  (value)))
+#define USBDCD_CLR_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) & ~(value)))
+#define USBDCD_TOG_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_CLOCK bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW)
+ *
+ * Specifies the unit of measure for the clock speed.
+ *
+ * Values:
+ * - 0b0 - kHz Speed (between 1 kHz and 1023 kHz)
+ * - 0b1 - MHz Speed (between 1 MHz and 1023 MHz)
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field. */
+#define USBDCD_RD_CLOCK_CLOCK_UNIT(base) ((USBDCD_CLOCK_REG(base) & USBDCD_CLOCK_CLOCK_UNIT_MASK) >> USBDCD_CLOCK_CLOCK_UNIT_SHIFT)
+#define USBDCD_BRD_CLOCK_CLOCK_UNIT(base) (BITBAND_ACCESS32(&USBDCD_CLOCK_REG(base), USBDCD_CLOCK_CLOCK_UNIT_SHIFT))
+
+/*! @brief Set the CLOCK_UNIT field to a new value. */
+#define USBDCD_WR_CLOCK_CLOCK_UNIT(base, value) (USBDCD_RMW_CLOCK(base, USBDCD_CLOCK_CLOCK_UNIT_MASK, USBDCD_CLOCK_CLOCK_UNIT(value)))
+#define USBDCD_BWR_CLOCK_CLOCK_UNIT(base, value) (BITBAND_ACCESS32(&USBDCD_CLOCK_REG(base), USBDCD_CLOCK_CLOCK_UNIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW)
+ *
+ * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to
+ * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples
+ * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz:
+ * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100)
+ * For 500 kHz: 0b01_1111_0100 (500)
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field. */
+#define USBDCD_RD_CLOCK_CLOCK_SPEED(base) ((USBDCD_CLOCK_REG(base) & USBDCD_CLOCK_CLOCK_SPEED_MASK) >> USBDCD_CLOCK_CLOCK_SPEED_SHIFT)
+#define USBDCD_BRD_CLOCK_CLOCK_SPEED(base) (USBDCD_RD_CLOCK_CLOCK_SPEED(base))
+
+/*! @brief Set the CLOCK_SPEED field to a new value. */
+#define USBDCD_WR_CLOCK_CLOCK_SPEED(base, value) (USBDCD_RMW_CLOCK(base, USBDCD_CLOCK_CLOCK_SPEED_MASK, USBDCD_CLOCK_CLOCK_SPEED(value)))
+#define USBDCD_BWR_CLOCK_CLOCK_SPEED(base, value) (USBDCD_WR_CLOCK_CLOCK_SPEED(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_STATUS - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_STATUS - Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Provides the current state of the module for system software monitoring.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_STATUS register
+ */
+/*@{*/
+#define USBDCD_RD_STATUS(base)   (USBDCD_STATUS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_STATUS bitfields
+ */
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO)
+ *
+ * Reports how the charger detection is attached.
+ *
+ * Values:
+ * - 0b00 - No results to report.
+ * - 0b01 - Attached to a standard host. Must comply with USB 2.0 by drawing
+ *     only 2.5 mA (max) until connected.
+ * - 0b10 - Attached to a charging port. The exact meaning depends on bit 18: 0:
+ *     Attached to either a charging host or a dedicated charger. The charger
+ *     type detection has not completed. 1: Attached to a charging host. The
+ *     charger type detection has completed.
+ * - 0b11 - Attached to a dedicated charger.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_SEQ_RES field. */
+#define USBDCD_RD_STATUS_SEQ_RES(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_SEQ_RES_MASK) >> USBDCD_STATUS_SEQ_RES_SHIFT)
+#define USBDCD_BRD_STATUS_SEQ_RES(base) (USBDCD_RD_STATUS_SEQ_RES(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO)
+ *
+ * Indicates the status of the charger detection sequence.
+ *
+ * Values:
+ * - 0b00 - The module is either not enabled, or the module is enabled but the
+ *     data pins have not yet been detected.
+ * - 0b01 - Data pin contact detection is complete.
+ * - 0b10 - Charging port detection is complete.
+ * - 0b11 - Charger type detection is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field. */
+#define USBDCD_RD_STATUS_SEQ_STAT(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_SEQ_STAT_MASK) >> USBDCD_STATUS_SEQ_STAT_SHIFT)
+#define USBDCD_BRD_STATUS_SEQ_STAT(base) (USBDCD_RD_STATUS_SEQ_STAT(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field ERR[20] (RO)
+ *
+ * Indicates whether there is an error in the detection sequence.
+ *
+ * Values:
+ * - 0b0 - No sequence errors.
+ * - 0b1 - Error in the detection sequence. See the SEQ_STAT field to determine
+ *     the phase in which the error occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_ERR field. */
+#define USBDCD_RD_STATUS_ERR(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_ERR_MASK) >> USBDCD_STATUS_ERR_SHIFT)
+#define USBDCD_BRD_STATUS_ERR(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field TO[21] (RO)
+ *
+ * Indicates whether the detection sequence has passed the timeout threshhold.
+ *
+ * Values:
+ * - 0b0 - The detection sequence has not been running for over 1 s.
+ * - 0b1 - It has been over 1 s since the data pin contact was detected and
+ *     debounced.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_TO field. */
+#define USBDCD_RD_STATUS_TO(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_TO_MASK) >> USBDCD_STATUS_TO_SHIFT)
+#define USBDCD_BRD_STATUS_TO(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_TO_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field ACTIVE[22] (RO)
+ *
+ * Indicates whether the sequence is running.
+ *
+ * Values:
+ * - 0b0 - The sequence is not running.
+ * - 0b1 - The sequence is running.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_ACTIVE field. */
+#define USBDCD_RD_STATUS_ACTIVE(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_ACTIVE_MASK) >> USBDCD_STATUS_ACTIVE_SHIFT)
+#define USBDCD_BRD_STATUS_ACTIVE(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_ACTIVE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER0 - TIMER0 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER0 - TIMER0 register (RW)
+ *
+ * Reset value: 0x00100000U
+ *
+ * TIMER0 has an TSEQ_INIT field that represents the system latency in ms.
+ * Latency is measured from the time when VBUS goes active until the time system
+ * software initiates charger detection sequence in USBDCD module. When software sets
+ * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized
+ * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery
+ * Charging Specification requires the entire sequence, including TSEQ_INIT, to be
+ * completed in 1s or less.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER0 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER0(base)   (USBDCD_TIMER0_REG(base))
+#define USBDCD_WR_TIMER0(base, value) (USBDCD_TIMER0_REG(base) = (value))
+#define USBDCD_RMW_TIMER0(base, mask, value) (USBDCD_WR_TIMER0(base, (USBDCD_RD_TIMER0(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) |  (value)))
+#define USBDCD_CLR_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) & ~(value)))
+#define USBDCD_TOG_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER0 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO)
+ *
+ * Displays the amount of elapsed time since the event of setting the START bit
+ * plus the value of TSEQ_INIT. The timer is automatically initialized with the
+ * value of TSEQ_INIT before starting to count. This timer enables compliance with
+ * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging
+ * Specification. If the timer reaches the one second limit, the module triggers
+ * an interrupt and sets the error flag STATUS[ERR]. The timer continues
+ * counting throughout the charger detection sequence, even when control has been passed
+ * to software. As long as the module is active, the timer continues to count
+ * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not
+ * rollover to zero. A software reset clears the timer.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER0_TUNITCON field. */
+#define USBDCD_RD_TIMER0_TUNITCON(base) ((USBDCD_TIMER0_REG(base) & USBDCD_TIMER0_TUNITCON_MASK) >> USBDCD_TIMER0_TUNITCON_SHIFT)
+#define USBDCD_BRD_TIMER0_TUNITCON(base) (USBDCD_RD_TIMER0_TUNITCON(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW)
+ *
+ * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS
+ * goes active to the time system software initiates the charger detection
+ * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit
+ * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid
+ * values are 0-1023, but the USB Battery Charging Specification requires the
+ * entire sequence, including TSEQ_INIT, to be completed in 1s or less.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field. */
+#define USBDCD_RD_TIMER0_TSEQ_INIT(base) ((USBDCD_TIMER0_REG(base) & USBDCD_TIMER0_TSEQ_INIT_MASK) >> USBDCD_TIMER0_TSEQ_INIT_SHIFT)
+#define USBDCD_BRD_TIMER0_TSEQ_INIT(base) (USBDCD_RD_TIMER0_TSEQ_INIT(base))
+
+/*! @brief Set the TSEQ_INIT field to a new value. */
+#define USBDCD_WR_TIMER0_TSEQ_INIT(base, value) (USBDCD_RMW_TIMER0(base, USBDCD_TIMER0_TSEQ_INIT_MASK, USBDCD_TIMER0_TSEQ_INIT(value)))
+#define USBDCD_BWR_TIMER0_TSEQ_INIT(base, value) (USBDCD_WR_TIMER0_TSEQ_INIT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER1 - TIMER1 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER1 - TIMER1 register (RW)
+ *
+ * Reset value: 0x000A0028U
+ *
+ * TIMER1 contains timing parameters. Note that register values can be written
+ * that are not compliant with the USB Battery Charging Specification, so care
+ * should be taken when overwriting the default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER1 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER1(base)   (USBDCD_TIMER1_REG(base))
+#define USBDCD_WR_TIMER1(base, value) (USBDCD_TIMER1_REG(base) = (value))
+#define USBDCD_RMW_TIMER1(base, mask, value) (USBDCD_WR_TIMER1(base, (USBDCD_RD_TIMER1(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) |  (value)))
+#define USBDCD_CLR_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) & ~(value)))
+#define USBDCD_TOG_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER1 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW)
+ *
+ * This timing parameter is used after detection of the data pin. See "Charging
+ * Port Detection". Valid values are 1-1023, but the USB Battery Charging
+ * Specification requires a minimum value of 40 ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field. */
+#define USBDCD_RD_TIMER1_TVDPSRC_ON(base) ((USBDCD_TIMER1_REG(base) & USBDCD_TIMER1_TVDPSRC_ON_MASK) >> USBDCD_TIMER1_TVDPSRC_ON_SHIFT)
+#define USBDCD_BRD_TIMER1_TVDPSRC_ON(base) (USBDCD_RD_TIMER1_TVDPSRC_ON(base))
+
+/*! @brief Set the TVDPSRC_ON field to a new value. */
+#define USBDCD_WR_TIMER1_TVDPSRC_ON(base, value) (USBDCD_RMW_TIMER1(base, USBDCD_TIMER1_TVDPSRC_ON_MASK, USBDCD_TIMER1_TVDPSRC_ON(value)))
+#define USBDCD_BWR_TIMER1_TVDPSRC_ON(base, value) (USBDCD_WR_TIMER1_TVDPSRC_ON(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW)
+ *
+ * Sets the time period (ms) to debounce the D+ signal during the data pin
+ * contact detection phase. See "Debouncing the data pin contact" Valid values are
+ * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10
+ * ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field. */
+#define USBDCD_RD_TIMER1_TDCD_DBNC(base) ((USBDCD_TIMER1_REG(base) & USBDCD_TIMER1_TDCD_DBNC_MASK) >> USBDCD_TIMER1_TDCD_DBNC_SHIFT)
+#define USBDCD_BRD_TIMER1_TDCD_DBNC(base) (USBDCD_RD_TIMER1_TDCD_DBNC(base))
+
+/*! @brief Set the TDCD_DBNC field to a new value. */
+#define USBDCD_WR_TIMER1_TDCD_DBNC(base, value) (USBDCD_RMW_TIMER1(base, USBDCD_TIMER1_TDCD_DBNC_MASK, USBDCD_TIMER1_TDCD_DBNC(value)))
+#define USBDCD_BWR_TIMER1_TDCD_DBNC(base, value) (USBDCD_WR_TIMER1_TDCD_DBNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW)
+ *
+ * Reset value: 0x00280001U
+ *
+ * TIMER2_BC11 contains timing parameters for USB Battery Charging
+ * Specification, v1.1. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC11 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER2_BC11(base) (USBDCD_TIMER2_BC11_REG(base))
+#define USBDCD_WR_TIMER2_BC11(base, value) (USBDCD_TIMER2_BC11_REG(base) = (value))
+#define USBDCD_RMW_TIMER2_BC11(base, mask, value) (USBDCD_WR_TIMER2_BC11(base, (USBDCD_RD_TIMER2_BC11(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) |  (value)))
+#define USBDCD_CLR_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) & ~(value)))
+#define USBDCD_TOG_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after the device
+ * connects to the USB bus until checking the state of the D- line to determine the
+ * type of charging port. See "Charger Type Detection." Valid values are 1-15ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field. */
+#define USBDCD_RD_TIMER2_BC11_CHECK_DM(base) ((USBDCD_TIMER2_BC11_REG(base) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) >> USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)
+#define USBDCD_BRD_TIMER2_BC11_CHECK_DM(base) (USBDCD_RD_TIMER2_BC11_CHECK_DM(base))
+
+/*! @brief Set the CHECK_DM field to a new value. */
+#define USBDCD_WR_TIMER2_BC11_CHECK_DM(base, value) (USBDCD_RMW_TIMER2_BC11(base, USBDCD_TIMER2_BC11_CHECK_DM_MASK, USBDCD_TIMER2_BC11_CHECK_DM(value)))
+#define USBDCD_BWR_TIMER2_BC11_CHECK_DM(base, value) (USBDCD_WR_TIMER2_BC11_CHECK_DM(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW)
+ *
+ * Sets the time period (ms) that the module waits after charging port detection
+ * before system software must enable the D+ pullup to connect to the USB host.
+ * Valid values are 1-1023, but the USB Battery Charging Specification requires a
+ * minimum value of 40 ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field. */
+#define USBDCD_RD_TIMER2_BC11_TVDPSRC_CON(base) ((USBDCD_TIMER2_BC11_REG(base) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) >> USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)
+#define USBDCD_BRD_TIMER2_BC11_TVDPSRC_CON(base) (USBDCD_RD_TIMER2_BC11_TVDPSRC_CON(base))
+
+/*! @brief Set the TVDPSRC_CON field to a new value. */
+#define USBDCD_WR_TIMER2_BC11_TVDPSRC_CON(base, value) (USBDCD_RMW_TIMER2_BC11(base, USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK, USBDCD_TIMER2_BC11_TVDPSRC_CON(value)))
+#define USBDCD_BWR_TIMER2_BC11_TVDPSRC_CON(base, value) (USBDCD_WR_TIMER2_BC11_TVDPSRC_CON(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW)
+ *
+ * Reset value: 0x00010028U
+ *
+ * TIMER2_BC12 contains timing parameters for USB Battery Charging
+ * Specification, v1.2. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC12 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER2_BC12(base) (USBDCD_TIMER2_BC12_REG(base))
+#define USBDCD_WR_TIMER2_BC12(base, value) (USBDCD_TIMER2_BC12_REG(base) = (value))
+#define USBDCD_RMW_TIMER2_BC12(base, mask, value) (USBDCD_WR_TIMER2_BC12(base, (USBDCD_RD_TIMER2_BC12(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) |  (value)))
+#define USBDCD_CLR_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) & ~(value)))
+#define USBDCD_TOG_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid
+ * values are 0-40ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field. */
+#define USBDCD_RD_TIMER2_BC12_TVDMSRC_ON(base) ((USBDCD_TIMER2_BC12_REG(base) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) >> USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)
+#define USBDCD_BRD_TIMER2_BC12_TVDMSRC_ON(base) (USBDCD_RD_TIMER2_BC12_TVDMSRC_ON(base))
+
+/*! @brief Set the TVDMSRC_ON field to a new value. */
+#define USBDCD_WR_TIMER2_BC12_TVDMSRC_ON(base, value) (USBDCD_RMW_TIMER2_BC12(base, USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK, USBDCD_TIMER2_BC12_TVDMSRC_ON(value)))
+#define USBDCD_BWR_TIMER2_BC12_TVDMSRC_ON(base, value) (USBDCD_WR_TIMER2_BC12_TVDMSRC_ON(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after primary detection
+ * before start to secondary detection. Valid values are 1-1023ms. Default is
+ * 1ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field. */
+#define USBDCD_RD_TIMER2_BC12_TWAIT_AFTER_PRD(base) ((USBDCD_TIMER2_BC12_REG(base) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) >> USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)
+#define USBDCD_BRD_TIMER2_BC12_TWAIT_AFTER_PRD(base) (USBDCD_RD_TIMER2_BC12_TWAIT_AFTER_PRD(base))
+
+/*! @brief Set the TWAIT_AFTER_PRD field to a new value. */
+#define USBDCD_WR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value) (USBDCD_RMW_TIMER2_BC12(base, USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK, USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(value)))
+#define USBDCD_BWR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value) (USBDCD_WR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value))
+/*@}*/
+
+/*
+ * MK64F12 VREF
+ *
+ * Voltage Reference
+ *
+ * Registers defined in this header file:
+ * - VREF_TRM - VREF Trim Register
+ * - VREF_SC - VREF Status and Control Register
+ */
+
+#define VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
+#define VREF_IDX (0U) /*!< Instance number for VREF. */
+
+/*******************************************************************************
+ * VREF_TRM - VREF Trim Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_TRM - VREF Trim Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains bits that contain the trim data for the Voltage
+ * Reference.
+ */
+/*!
+ * @name Constants and macros for entire VREF_TRM register
+ */
+/*@{*/
+#define VREF_RD_TRM(base)        (VREF_TRM_REG(base))
+#define VREF_WR_TRM(base, value) (VREF_TRM_REG(base) = (value))
+#define VREF_RMW_TRM(base, mask, value) (VREF_WR_TRM(base, (VREF_RD_TRM(base) & ~(mask)) | (value)))
+#define VREF_SET_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) |  (value)))
+#define VREF_CLR_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) & ~(value)))
+#define VREF_TOG_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_TRM bitfields
+ */
+
+/*!
+ * @name Register VREF_TRM, field TRIM[5:0] (RW)
+ *
+ * These bits change the resulting VREF by approximately +/- 0.5 mV for each
+ * step. Min = minimum and max = maximum voltage reference output. For minimum and
+ * maximum voltage reference output values, refer to the Data Sheet for this chip.
+ *
+ * Values:
+ * - 0b000000 - Min
+ * - 0b111111 - Max
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_TRIM field. */
+#define VREF_RD_TRM_TRIM(base) ((VREF_TRM_REG(base) & VREF_TRM_TRIM_MASK) >> VREF_TRM_TRIM_SHIFT)
+#define VREF_BRD_TRM_TRIM(base) (VREF_RD_TRM_TRIM(base))
+
+/*! @brief Set the TRIM field to a new value. */
+#define VREF_WR_TRM_TRIM(base, value) (VREF_RMW_TRM(base, VREF_TRM_TRIM_MASK, VREF_TRM_TRIM(value)))
+#define VREF_BWR_TRM_TRIM(base, value) (VREF_WR_TRM_TRIM(base, value))
+/*@}*/
+
+/*!
+ * @name Register VREF_TRM, field CHOPEN[6] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0b0 - Chop oscillator is disabled.
+ * - 0b1 - Chop oscillator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_CHOPEN field. */
+#define VREF_RD_TRM_CHOPEN(base) ((VREF_TRM_REG(base) & VREF_TRM_CHOPEN_MASK) >> VREF_TRM_CHOPEN_SHIFT)
+#define VREF_BRD_TRM_CHOPEN(base) (BITBAND_ACCESS8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT))
+
+/*! @brief Set the CHOPEN field to a new value. */
+#define VREF_WR_TRM_CHOPEN(base, value) (VREF_RMW_TRM(base, VREF_TRM_CHOPEN_MASK, VREF_TRM_CHOPEN(value)))
+#define VREF_BWR_TRM_CHOPEN(base, value) (BITBAND_ACCESS8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * VREF_SC - VREF Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_SC - VREF Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the control bits used to enable the internal voltage
+ * reference and to select the buffer mode to be used.
+ */
+/*!
+ * @name Constants and macros for entire VREF_SC register
+ */
+/*@{*/
+#define VREF_RD_SC(base)         (VREF_SC_REG(base))
+#define VREF_WR_SC(base, value)  (VREF_SC_REG(base) = (value))
+#define VREF_RMW_SC(base, mask, value) (VREF_WR_SC(base, (VREF_RD_SC(base) & ~(mask)) | (value)))
+#define VREF_SET_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) |  (value)))
+#define VREF_CLR_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) & ~(value)))
+#define VREF_TOG_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_SC bitfields
+ */
+
+/*!
+ * @name Register VREF_SC, field MODE_LV[1:0] (RW)
+ *
+ * These bits select the buffer modes for the Voltage Reference module.
+ *
+ * Values:
+ * - 0b00 - Bandgap on only, for stabilization and startup
+ * - 0b01 - High power buffer mode enabled
+ * - 0b10 - Low-power buffer mode enabled
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_MODE_LV field. */
+#define VREF_RD_SC_MODE_LV(base) ((VREF_SC_REG(base) & VREF_SC_MODE_LV_MASK) >> VREF_SC_MODE_LV_SHIFT)
+#define VREF_BRD_SC_MODE_LV(base) (VREF_RD_SC_MODE_LV(base))
+
+/*! @brief Set the MODE_LV field to a new value. */
+#define VREF_WR_SC_MODE_LV(base, value) (VREF_RMW_SC(base, VREF_SC_MODE_LV_MASK, VREF_SC_MODE_LV(value)))
+#define VREF_BWR_SC_MODE_LV(base, value) (VREF_WR_SC_MODE_LV(base, value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFST[2] (RO)
+ *
+ * This bit indicates that the bandgap reference within the Voltage Reference
+ * module has completed its startup and stabilization.
+ *
+ * Values:
+ * - 0b0 - The module is disabled or not stable.
+ * - 0b1 - The module is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFST field. */
+#define VREF_RD_SC_VREFST(base) ((VREF_SC_REG(base) & VREF_SC_VREFST_MASK) >> VREF_SC_VREFST_SHIFT)
+#define VREF_BRD_SC_VREFST(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field ICOMPEN[5] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_ICOMPEN field. */
+#define VREF_RD_SC_ICOMPEN(base) ((VREF_SC_REG(base) & VREF_SC_ICOMPEN_MASK) >> VREF_SC_ICOMPEN_SHIFT)
+#define VREF_BRD_SC_ICOMPEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT))
+
+/*! @brief Set the ICOMPEN field to a new value. */
+#define VREF_WR_SC_ICOMPEN(base, value) (VREF_RMW_SC(base, VREF_SC_ICOMPEN_MASK, VREF_SC_ICOMPEN(value)))
+#define VREF_BWR_SC_ICOMPEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field REGEN[6] (RW)
+ *
+ * This bit is used to enable the internal 1.75 V regulator to produce a
+ * constant internal voltage supply in order to reduce the sensitivity to external
+ * supply noise and variation. If it is desired to keep the regulator enabled in very
+ * low power modes, refer to the Chip Configuration details for a description on
+ * how this can be achieved. This bit is set during factory trimming of the VREF
+ * voltage. This bit should be written to 1 to achieve the performance stated in
+ * the data sheet.
+ *
+ * Values:
+ * - 0b0 - Internal 1.75 V regulator is disabled.
+ * - 0b1 - Internal 1.75 V regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_REGEN field. */
+#define VREF_RD_SC_REGEN(base) ((VREF_SC_REG(base) & VREF_SC_REGEN_MASK) >> VREF_SC_REGEN_SHIFT)
+#define VREF_BRD_SC_REGEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT))
+
+/*! @brief Set the REGEN field to a new value. */
+#define VREF_WR_SC_REGEN(base, value) (VREF_RMW_SC(base, VREF_SC_REGEN_MASK, VREF_SC_REGEN(value)))
+#define VREF_BWR_SC_REGEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFEN[7] (RW)
+ *
+ * This bit is used to enable the bandgap reference within the Voltage Reference
+ * module. After the VREF is enabled, turning off the clock to the VREF module
+ * via the corresponding clock gate register will not disable the VREF. VREF must
+ * be disabled via this VREFEN bit.
+ *
+ * Values:
+ * - 0b0 - The module is disabled.
+ * - 0b1 - The module is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFEN field. */
+#define VREF_RD_SC_VREFEN(base) ((VREF_SC_REG(base) & VREF_SC_VREFEN_MASK) >> VREF_SC_VREFEN_SHIFT)
+#define VREF_BRD_SC_VREFEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT))
+
+/*! @brief Set the VREFEN field to a new value. */
+#define VREF_WR_SC_VREFEN(base, value) (VREF_RMW_SC(base, VREF_SC_VREFEN_MASK, VREF_SC_VREFEN(value)))
+#define VREF_BWR_SC_VREFEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 WDOG
+ *
+ * Generation 2008 Watchdog Timer
+ *
+ * Registers defined in this header file:
+ * - WDOG_STCTRLH - Watchdog Status and Control Register High
+ * - WDOG_STCTRLL - Watchdog Status and Control Register Low
+ * - WDOG_TOVALH - Watchdog Time-out Value Register High
+ * - WDOG_TOVALL - Watchdog Time-out Value Register Low
+ * - WDOG_WINH - Watchdog Window Register High
+ * - WDOG_WINL - Watchdog Window Register Low
+ * - WDOG_REFRESH - Watchdog Refresh register
+ * - WDOG_UNLOCK - Watchdog Unlock register
+ * - WDOG_TMROUTH - Watchdog Timer Output Register High
+ * - WDOG_TMROUTL - Watchdog Timer Output Register Low
+ * - WDOG_RSTCNT - Watchdog Reset Count register
+ * - WDOG_PRESC - Watchdog Prescaler register
+ */
+
+#define WDOG_INSTANCE_COUNT (1U) /*!< Number of instances of the WDOG module. */
+#define WDOG_IDX (0U) /*!< Instance number for WDOG. */
+
+/*******************************************************************************
+ * WDOG_STCTRLH - Watchdog Status and Control Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
+ *
+ * Reset value: 0x01D3U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLH register
+ */
+/*@{*/
+#define WDOG_RD_STCTRLH(base)    (WDOG_STCTRLH_REG(base))
+#define WDOG_WR_STCTRLH(base, value) (WDOG_STCTRLH_REG(base) = (value))
+#define WDOG_RMW_STCTRLH(base, mask, value) (WDOG_WR_STCTRLH(base, (WDOG_RD_STCTRLH(base) & ~(mask)) | (value)))
+#define WDOG_SET_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) |  (value)))
+#define WDOG_CLR_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) & ~(value)))
+#define WDOG_TOG_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_STCTRLH bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
+ *
+ * Enables or disables the WDOG's operation. In the disabled state, the watchdog
+ * timer is kept in the reset state, but the other exception conditions can
+ * still trigger a reset/interrupt. A change in the value of this bit must be held
+ * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled.
+ * - 0b1 - WDOG is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. */
+#define WDOG_RD_STCTRLH_WDOGEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WDOGEN_MASK) >> WDOG_STCTRLH_WDOGEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WDOGEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WDOGEN_SHIFT))
+
+/*! @brief Set the WDOGEN field to a new value. */
+#define WDOG_WR_STCTRLH_WDOGEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WDOGEN_MASK, WDOG_STCTRLH_WDOGEN(value)))
+#define WDOG_BWR_STCTRLH_WDOGEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WDOGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
+ *
+ * Selects clock source for the WDOG timer and other internal timing operations.
+ *
+ * Values:
+ * - 0b0 - WDOG clock sourced from LPO .
+ * - 0b1 - WDOG clock sourced from alternate clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. */
+#define WDOG_RD_STCTRLH_CLKSRC(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_CLKSRC_MASK) >> WDOG_STCTRLH_CLKSRC_SHIFT)
+#define WDOG_BRD_STCTRLH_CLKSRC(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_CLKSRC_SHIFT))
+
+/*! @brief Set the CLKSRC field to a new value. */
+#define WDOG_WR_STCTRLH_CLKSRC(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_CLKSRC_MASK, WDOG_STCTRLH_CLKSRC(value)))
+#define WDOG_BWR_STCTRLH_CLKSRC(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_CLKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
+ *
+ * Used to enable the debug breadcrumbs feature. A change in this bit is updated
+ * immediately, as opposed to updating after WCT.
+ *
+ * Values:
+ * - 0b0 - WDOG time-out generates reset only.
+ * - 0b1 - WDOG time-out initially generates an interrupt. After WCT, it
+ *     generates a reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. */
+#define WDOG_RD_STCTRLH_IRQRSTEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_IRQRSTEN_MASK) >> WDOG_STCTRLH_IRQRSTEN_SHIFT)
+#define WDOG_BRD_STCTRLH_IRQRSTEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_IRQRSTEN_SHIFT))
+
+/*! @brief Set the IRQRSTEN field to a new value. */
+#define WDOG_WR_STCTRLH_IRQRSTEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_IRQRSTEN_MASK, WDOG_STCTRLH_IRQRSTEN(value)))
+#define WDOG_BWR_STCTRLH_IRQRSTEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_IRQRSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
+ *
+ * Enables Windowing mode.
+ *
+ * Values:
+ * - 0b0 - Windowing mode is disabled.
+ * - 0b1 - Windowing mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WINEN field. */
+#define WDOG_RD_STCTRLH_WINEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WINEN_MASK) >> WDOG_STCTRLH_WINEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WINEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WINEN_SHIFT))
+
+/*! @brief Set the WINEN field to a new value. */
+#define WDOG_WR_STCTRLH_WINEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WINEN_MASK, WDOG_STCTRLH_WINEN(value)))
+#define WDOG_BWR_STCTRLH_WINEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WINEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
+ *
+ * Enables updates to watchdog write-once registers, after the reset-triggered
+ * initial configuration window (WCT) closes, through unlock sequence.
+ *
+ * Values:
+ * - 0b0 - No further updates allowed to WDOG write-once registers.
+ * - 0b1 - WDOG write-once registers can be unlocked for updating.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. */
+#define WDOG_RD_STCTRLH_ALLOWUPDATE(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_ALLOWUPDATE_MASK) >> WDOG_STCTRLH_ALLOWUPDATE_SHIFT)
+#define WDOG_BRD_STCTRLH_ALLOWUPDATE(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_ALLOWUPDATE_SHIFT))
+
+/*! @brief Set the ALLOWUPDATE field to a new value. */
+#define WDOG_WR_STCTRLH_ALLOWUPDATE(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_ALLOWUPDATE_MASK, WDOG_STCTRLH_ALLOWUPDATE(value)))
+#define WDOG_BWR_STCTRLH_ALLOWUPDATE(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_ALLOWUPDATE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
+ *
+ * Enables or disables WDOG in Debug mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Debug mode.
+ * - 0b1 - WDOG is enabled in CPU Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_DBGEN field. */
+#define WDOG_RD_STCTRLH_DBGEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_DBGEN_MASK) >> WDOG_STCTRLH_DBGEN_SHIFT)
+#define WDOG_BRD_STCTRLH_DBGEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DBGEN_SHIFT))
+
+/*! @brief Set the DBGEN field to a new value. */
+#define WDOG_WR_STCTRLH_DBGEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_DBGEN_MASK, WDOG_STCTRLH_DBGEN(value)))
+#define WDOG_BWR_STCTRLH_DBGEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DBGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
+ *
+ * Enables or disables WDOG in Stop mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Stop mode.
+ * - 0b1 - WDOG is enabled in CPU Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_STOPEN field. */
+#define WDOG_RD_STCTRLH_STOPEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_STOPEN_MASK) >> WDOG_STCTRLH_STOPEN_SHIFT)
+#define WDOG_BRD_STCTRLH_STOPEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_STOPEN_SHIFT))
+
+/*! @brief Set the STOPEN field to a new value. */
+#define WDOG_WR_STCTRLH_STOPEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_STOPEN_MASK, WDOG_STCTRLH_STOPEN(value)))
+#define WDOG_BWR_STCTRLH_STOPEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_STOPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
+ *
+ * Enables or disables WDOG in Wait mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Wait mode.
+ * - 0b1 - WDOG is enabled in CPU Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WAITEN field. */
+#define WDOG_RD_STCTRLH_WAITEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WAITEN_MASK) >> WDOG_STCTRLH_WAITEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WAITEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WAITEN_SHIFT))
+
+/*! @brief Set the WAITEN field to a new value. */
+#define WDOG_WR_STCTRLH_WAITEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WAITEN_MASK, WDOG_STCTRLH_WAITEN(value)))
+#define WDOG_BWR_STCTRLH_WAITEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WAITEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
+ *
+ * Puts the watchdog in the functional test mode. In this mode, the watchdog
+ * timer and the associated compare and reset generation logic is tested for correct
+ * operation. The clock for the timer is switched from the main watchdog clock
+ * to the fast clock input for watchdog functional test. The TESTSEL bit selects
+ * the test to be run.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. */
+#define WDOG_RD_STCTRLH_TESTWDOG(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_TESTWDOG_MASK) >> WDOG_STCTRLH_TESTWDOG_SHIFT)
+#define WDOG_BRD_STCTRLH_TESTWDOG(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTWDOG_SHIFT))
+
+/*! @brief Set the TESTWDOG field to a new value. */
+#define WDOG_WR_STCTRLH_TESTWDOG(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_TESTWDOG_MASK, WDOG_STCTRLH_TESTWDOG(value)))
+#define WDOG_BWR_STCTRLH_TESTWDOG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTWDOG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
+ *
+ * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
+ * timer.
+ *
+ * Values:
+ * - 0b0 - Quick test. The timer runs in normal operation. You can load a small
+ *     time-out value to do a quick test.
+ * - 0b1 - Byte test. Puts the timer in the byte test mode where individual
+ *     bytes of the timer are enabled for operation and are compared for time-out
+ *     against the corresponding byte of the programmed time-out value. Select the
+ *     byte through BYTESEL[1:0] for testing.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. */
+#define WDOG_RD_STCTRLH_TESTSEL(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_TESTSEL_MASK) >> WDOG_STCTRLH_TESTSEL_SHIFT)
+#define WDOG_BRD_STCTRLH_TESTSEL(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTSEL_SHIFT))
+
+/*! @brief Set the TESTSEL field to a new value. */
+#define WDOG_WR_STCTRLH_TESTSEL(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_TESTSEL_MASK, WDOG_STCTRLH_TESTSEL(value)))
+#define WDOG_BWR_STCTRLH_TESTSEL(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
+ *
+ * This 2-bit field selects the byte to be tested when the watchdog is in the
+ * byte test mode.
+ *
+ * Values:
+ * - 0b00 - Byte 0 selected
+ * - 0b01 - Byte 1 selected
+ * - 0b10 - Byte 2 selected
+ * - 0b11 - Byte 3 selected
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. */
+#define WDOG_RD_STCTRLH_BYTESEL(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_BYTESEL_MASK) >> WDOG_STCTRLH_BYTESEL_SHIFT)
+#define WDOG_BRD_STCTRLH_BYTESEL(base) (WDOG_RD_STCTRLH_BYTESEL(base))
+
+/*! @brief Set the BYTESEL field to a new value. */
+#define WDOG_WR_STCTRLH_BYTESEL(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_BYTESEL_MASK, WDOG_STCTRLH_BYTESEL(value)))
+#define WDOG_BWR_STCTRLH_BYTESEL(base, value) (WDOG_WR_STCTRLH_BYTESEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
+ *
+ * Allows the WDOG's functional test mode to be disabled permanently. After it
+ * is set, it can only be cleared by a reset. It cannot be unlocked for editing
+ * after it is set.
+ *
+ * Values:
+ * - 0b0 - WDOG functional test mode is not disabled.
+ * - 0b1 - WDOG functional test mode is disabled permanently until reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. */
+#define WDOG_RD_STCTRLH_DISTESTWDOG(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_DISTESTWDOG_MASK) >> WDOG_STCTRLH_DISTESTWDOG_SHIFT)
+#define WDOG_BRD_STCTRLH_DISTESTWDOG(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DISTESTWDOG_SHIFT))
+
+/*! @brief Set the DISTESTWDOG field to a new value. */
+#define WDOG_WR_STCTRLH_DISTESTWDOG(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_DISTESTWDOG_MASK, WDOG_STCTRLH_DISTESTWDOG(value)))
+#define WDOG_BWR_STCTRLH_DISTESTWDOG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DISTESTWDOG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_STCTRLL - Watchdog Status and Control Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
+ *
+ * Reset value: 0x0001U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLL register
+ */
+/*@{*/
+#define WDOG_RD_STCTRLL(base)    (WDOG_STCTRLL_REG(base))
+#define WDOG_WR_STCTRLL(base, value) (WDOG_STCTRLL_REG(base) = (value))
+#define WDOG_RMW_STCTRLL(base, mask, value) (WDOG_WR_STCTRLL(base, (WDOG_RD_STCTRLL(base) & ~(mask)) | (value)))
+#define WDOG_SET_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) |  (value)))
+#define WDOG_CLR_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) & ~(value)))
+#define WDOG_TOG_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_STCTRLL bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
+ *
+ * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
+ * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
+ * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
+ * bit. It also gets cleared on a system reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLL_INTFLG field. */
+#define WDOG_RD_STCTRLL_INTFLG(base) ((WDOG_STCTRLL_REG(base) & WDOG_STCTRLL_INTFLG_MASK) >> WDOG_STCTRLL_INTFLG_SHIFT)
+#define WDOG_BRD_STCTRLL_INTFLG(base) (BITBAND_ACCESS16(&WDOG_STCTRLL_REG(base), WDOG_STCTRLL_INTFLG_SHIFT))
+
+/*! @brief Set the INTFLG field to a new value. */
+#define WDOG_WR_STCTRLL_INTFLG(base, value) (WDOG_RMW_STCTRLL(base, WDOG_STCTRLL_INTFLG_MASK, WDOG_STCTRLL_INTFLG(value)))
+#define WDOG_BWR_STCTRLL_INTFLG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLL_REG(base), WDOG_STCTRLL_INTFLG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TOVALH - Watchdog Time-out Value Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
+ *
+ * Reset value: 0x004CU
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TOVALH register
+ */
+/*@{*/
+#define WDOG_RD_TOVALH(base)     (WDOG_TOVALH_REG(base))
+#define WDOG_WR_TOVALH(base, value) (WDOG_TOVALH_REG(base) = (value))
+#define WDOG_RMW_TOVALH(base, mask, value) (WDOG_WR_TOVALH(base, (WDOG_RD_TOVALH(base) & ~(mask)) | (value)))
+#define WDOG_SET_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) |  (value)))
+#define WDOG_CLR_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) & ~(value)))
+#define WDOG_TOG_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TOVALL - Watchdog Time-out Value Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
+ *
+ * Reset value: 0x4B4CU
+ *
+ * The time-out value of the watchdog must be set to a minimum of four watchdog
+ * clock cycles. This is to take into account the delay in new settings taking
+ * effect in the watchdog clock domain.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TOVALL register
+ */
+/*@{*/
+#define WDOG_RD_TOVALL(base)     (WDOG_TOVALL_REG(base))
+#define WDOG_WR_TOVALL(base, value) (WDOG_TOVALL_REG(base) = (value))
+#define WDOG_RMW_TOVALL(base, mask, value) (WDOG_WR_TOVALL(base, (WDOG_RD_TOVALL(base) & ~(mask)) | (value)))
+#define WDOG_SET_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) |  (value)))
+#define WDOG_CLR_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) & ~(value)))
+#define WDOG_TOG_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_WINH - Watchdog Window Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_WINH - Watchdog Window Register High (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_WINH register
+ */
+/*@{*/
+#define WDOG_RD_WINH(base)       (WDOG_WINH_REG(base))
+#define WDOG_WR_WINH(base, value) (WDOG_WINH_REG(base) = (value))
+#define WDOG_RMW_WINH(base, mask, value) (WDOG_WR_WINH(base, (WDOG_RD_WINH(base) & ~(mask)) | (value)))
+#define WDOG_SET_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) |  (value)))
+#define WDOG_CLR_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) & ~(value)))
+#define WDOG_TOG_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_WINL - Watchdog Window Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_WINL - Watchdog Window Register Low (RW)
+ *
+ * Reset value: 0x0010U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_WINL register
+ */
+/*@{*/
+#define WDOG_RD_WINL(base)       (WDOG_WINL_REG(base))
+#define WDOG_WR_WINL(base, value) (WDOG_WINL_REG(base) = (value))
+#define WDOG_RMW_WINL(base, mask, value) (WDOG_WR_WINL(base, (WDOG_RD_WINL(base) & ~(mask)) | (value)))
+#define WDOG_SET_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) |  (value)))
+#define WDOG_CLR_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) & ~(value)))
+#define WDOG_TOG_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_REFRESH - Watchdog Refresh register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_REFRESH - Watchdog Refresh register (RW)
+ *
+ * Reset value: 0xB480U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_REFRESH register
+ */
+/*@{*/
+#define WDOG_RD_REFRESH(base)    (WDOG_REFRESH_REG(base))
+#define WDOG_WR_REFRESH(base, value) (WDOG_REFRESH_REG(base) = (value))
+#define WDOG_RMW_REFRESH(base, mask, value) (WDOG_WR_REFRESH(base, (WDOG_RD_REFRESH(base) & ~(mask)) | (value)))
+#define WDOG_SET_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) |  (value)))
+#define WDOG_CLR_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) & ~(value)))
+#define WDOG_TOG_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_UNLOCK - Watchdog Unlock register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_UNLOCK - Watchdog Unlock register (RW)
+ *
+ * Reset value: 0xD928U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_UNLOCK register
+ */
+/*@{*/
+#define WDOG_RD_UNLOCK(base)     (WDOG_UNLOCK_REG(base))
+#define WDOG_WR_UNLOCK(base, value) (WDOG_UNLOCK_REG(base) = (value))
+#define WDOG_RMW_UNLOCK(base, mask, value) (WDOG_WR_UNLOCK(base, (WDOG_RD_UNLOCK(base) & ~(mask)) | (value)))
+#define WDOG_SET_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) |  (value)))
+#define WDOG_CLR_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) & ~(value)))
+#define WDOG_TOG_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TMROUTH - Watchdog Timer Output Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTH register
+ */
+/*@{*/
+#define WDOG_RD_TMROUTH(base)    (WDOG_TMROUTH_REG(base))
+#define WDOG_WR_TMROUTH(base, value) (WDOG_TMROUTH_REG(base) = (value))
+#define WDOG_RMW_TMROUTH(base, mask, value) (WDOG_WR_TMROUTH(base, (WDOG_RD_TMROUTH(base) & ~(mask)) | (value)))
+#define WDOG_SET_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) |  (value)))
+#define WDOG_CLR_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) & ~(value)))
+#define WDOG_TOG_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TMROUTL - Watchdog Timer Output Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
+ * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
+ * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
+ * the watchdog timer.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTL register
+ */
+/*@{*/
+#define WDOG_RD_TMROUTL(base)    (WDOG_TMROUTL_REG(base))
+#define WDOG_WR_TMROUTL(base, value) (WDOG_TMROUTL_REG(base) = (value))
+#define WDOG_RMW_TMROUTL(base, mask, value) (WDOG_WR_TMROUTL(base, (WDOG_RD_TMROUTL(base) & ~(mask)) | (value)))
+#define WDOG_SET_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) |  (value)))
+#define WDOG_CLR_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) & ~(value)))
+#define WDOG_TOG_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_RSTCNT - Watchdog Reset Count register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_RSTCNT - Watchdog Reset Count register (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_RSTCNT register
+ */
+/*@{*/
+#define WDOG_RD_RSTCNT(base)     (WDOG_RSTCNT_REG(base))
+#define WDOG_WR_RSTCNT(base, value) (WDOG_RSTCNT_REG(base) = (value))
+#define WDOG_RMW_RSTCNT(base, mask, value) (WDOG_WR_RSTCNT(base, (WDOG_RD_RSTCNT(base) & ~(mask)) | (value)))
+#define WDOG_SET_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) |  (value)))
+#define WDOG_CLR_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) & ~(value)))
+#define WDOG_TOG_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_PRESC - Watchdog Prescaler register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_PRESC - Watchdog Prescaler register (RW)
+ *
+ * Reset value: 0x0400U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_PRESC register
+ */
+/*@{*/
+#define WDOG_RD_PRESC(base)      (WDOG_PRESC_REG(base))
+#define WDOG_WR_PRESC(base, value) (WDOG_PRESC_REG(base) = (value))
+#define WDOG_RMW_PRESC(base, mask, value) (WDOG_WR_PRESC(base, (WDOG_RD_PRESC(base) & ~(mask)) | (value)))
+#define WDOG_SET_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) |  (value)))
+#define WDOG_CLR_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) & ~(value)))
+#define WDOG_TOG_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_PRESC bitfields
+ */
+
+/*!
+ * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
+ *
+ * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
+ * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
+ * 1) to provide the prescaled WDOG_CLK.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_PRESC_PRESCVAL field. */
+#define WDOG_RD_PRESC_PRESCVAL(base) ((WDOG_PRESC_REG(base) & WDOG_PRESC_PRESCVAL_MASK) >> WDOG_PRESC_PRESCVAL_SHIFT)
+#define WDOG_BRD_PRESC_PRESCVAL(base) (WDOG_RD_PRESC_PRESCVAL(base))
+
+/*! @brief Set the PRESCVAL field to a new value. */
+#define WDOG_WR_PRESC_PRESCVAL(base, value) (WDOG_RMW_PRESC(base, WDOG_PRESC_PRESCVAL_MASK, WDOG_PRESC_PRESCVAL(value)))
+#define WDOG_BWR_PRESC_PRESCVAL(base, value) (WDOG_WR_PRESC_PRESCVAL(base, value))
+/*@}*/
+
+/* Instance numbers for core modules */
+#define JTAG_IDX (0) /*!< Instance number for JTAG. */
+#define TPIU_IDX (0) /*!< Instance number for TPIU. */
+#define SCB_IDX (0) /*!< Instance number for SCB. */
+#define CoreDebug_IDX (0) /*!< Instance number for CoreDebug. */
+
+#if defined(__IAR_SYSTEMS_ICC__)
+  /* Restore checking of "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)" */
+  #pragma diag_default=pm008
+#endif
+
+#endif /* __MK64F12_EXTENSION_H__ */
+/* EOF */
diff --git a/Workspace/FTM_AND_PWM/SDK/platform/devices/MK64F12/include/MK64F12_features.h b/Workspace/FTM_AND_PWM/SDK/platform/devices/MK64F12/include/MK64F12_features.h
new file mode 100644
index 0000000..9c826df
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/SDK/platform/devices/MK64F12/include/MK64F12_features.h
@@ -0,0 +1,1901 @@
+/*
+** ###################################################################
+**     Version:             rev. 2.14, 2015-06-08
+**     Build:               b150715
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-01-30)
+**         Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.6 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.7 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.8 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.9 (2015-01-21)
+**         Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
+**     - rev. 2.10 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**     - rev. 2.11 (2015-05-19)
+**         FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
+**         Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
+**         Added features for PDB and PORT.
+**     - rev. 2.12 (2015-05-25)
+**         Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
+**     - rev. 2.13 (2015-05-27)
+**         Several USB features added.
+**     - rev. 2.14 (2015-06-08)
+**         FTM features BUS_CLOCK and FAST_CLOCK removed.
+**
+** ###################################################################
+*/
+
+#if !defined(__FSL_MK64F12_FEATURES_H__)
+#define __FSL_MK64F12_FEATURES_H__
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* FLEXCAN module features */
+
+/* @brief Message buffer size */
+#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
+/* @brief Has doze mode support (register bit field MCR[DOZE]). */
+#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
+/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
+#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
+/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
+/* @brief Has extended bit timing register (register CBT). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
+/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
+#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
+/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
+#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
+/* @brief Number of interrupt vectors. */
+#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* SOC module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief ACMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_ACMP_COUNT (0)
+    /* @brief ADC16 availability on the SoC. */
+    #define FSL_FEATURE_SOC_ADC16_COUNT (2)
+    /* @brief AFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_AFE_COUNT (0)
+    /* @brief AIPS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AIPS_COUNT (2)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (0)
+    /* @brief AXBS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AXBS_COUNT (1)
+    /* @brief CADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CADC_COUNT (0)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief MMCAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
+    /* @brief CMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMP_COUNT (3)
+    /* @brief CMT availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMT_COUNT (1)
+    /* @brief CNC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CNC_COUNT (0)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief DAC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DAC_COUNT (2)
+    /* @brief DCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DCDC_COUNT (0)
+    /* @brief DDR availability on the SoC. */
+    #define FSL_FEATURE_SOC_DDR_COUNT (0)
+    /* @brief DMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMA_COUNT (0)
+    /* @brief DMAMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+    /* @brief DRY availability on the SoC. */
+    #define FSL_FEATURE_SOC_DRY_COUNT (0)
+    /* @brief DSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_DSPI_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EMVSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+    /* @brief ENC availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENC_COUNT (0)
+    /* @brief ENET availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENET_COUNT (1)
+    /* @brief EWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EWM_COUNT (1)
+    /* @brief FB availability on the SoC. */
+    #define FSL_FEATURE_SOC_FB_COUNT (1)
+    /* @brief FGPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+    /* @brief FLEXIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FSKDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+    /* @brief FTFA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFA_COUNT (0)
+    /* @brief FTFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFE_COUNT (1)
+    /* @brief FTFL availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFL_COUNT (0)
+    /* @brief FTM availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTM_COUNT (4)
+    /* @brief FTMRA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+    /* @brief FTMRE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+    /* @brief FTMRH availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief HSADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_HSADC_COUNT (0)
+    /* @brief I2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2C_COUNT (3)
+    /* @brief I2S availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2S_COUNT (1)
+    /* @brief ICS availability on the SoC. */
+    #define FSL_FEATURE_SOC_ICS_COUNT (0)
+    /* @brief IRQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_IRQ_COUNT (0)
+    /* @brief KBI availability on the SoC. */
+    #define FSL_FEATURE_SOC_KBI_COUNT (0)
+    /* @brief SLCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_SLCD_COUNT (0)
+    /* @brief LCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LCDC_COUNT (0)
+    /* @brief LDO availability on the SoC. */
+    #define FSL_FEATURE_SOC_LDO_COUNT (0)
+    /* @brief LLWU availability on the SoC. */
+    #define FSL_FEATURE_SOC_LLWU_COUNT (1)
+    /* @brief LMEM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LMEM_COUNT (0)
+    /* @brief LPSCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPTPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (0)
+    /* @brief LTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LTC_COUNT (0)
+    /* @brief MC availability on the SoC. */
+    #define FSL_FEATURE_SOC_MC_COUNT (0)
+    /* @brief MCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCG_COUNT (1)
+    /* @brief MCGLITE availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+    /* @brief MCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCM_COUNT (1)
+    /* @brief MMAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMAU_COUNT (0)
+    /* @brief MMDVSQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+    /* @brief MPU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MPU_COUNT (1)
+    /* @brief MSCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+    /* @brief MTB availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTB_COUNT (0)
+    /* @brief MTBDWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
+    /* @brief NFC availability on the SoC. */
+    #define FSL_FEATURE_SOC_NFC_COUNT (0)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+    /* @brief OSC availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSC_COUNT (1)
+    /* @brief OTFAD availability on the SoC. */
+    #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+    /* @brief PDB availability on the SoC. */
+    #define FSL_FEATURE_SOC_PDB_COUNT (1)
+    /* @brief PGA availability on the SoC. */
+    #define FSL_FEATURE_SOC_PGA_COUNT (0)
+    /* @brief PIT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PIT_COUNT (1)
+    /* @brief PMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_PMC_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (0)
+    /* @brief PWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWT_COUNT (0)
+    /* @brief QuadSPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+    /* @brief RCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RCM_COUNT (1)
+    /* @brief RFSYS availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+    /* @brief RFVBAT availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+    /* @brief RNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNG_COUNT (1)
+    /* @brief RNGB availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNGB_COUNT (0)
+    /* @brief ROM availability on the SoC. */
+    #define FSL_FEATURE_SOC_ROM_COUNT (0)
+    /* @brief RSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RSIM_COUNT (0)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCI_COUNT (0)
+    /* @brief SDHC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDHC_COUNT (1)
+    /* @brief SDRAM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+    /* @brief SIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SIM_COUNT (1)
+    /* @brief SMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMC_COUNT (1)
+    /* @brief SPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPI_COUNT (0)
+    /* @brief TMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_TMR_COUNT (0)
+    /* @brief TPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_TPM_COUNT (0)
+    /* @brief TRIAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+    /* @brief TRNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRNG_COUNT (0)
+    /* @brief TSI availability on the SoC. */
+    #define FSL_FEATURE_SOC_TSI_COUNT (0)
+    /* @brief UART availability on the SoC. */
+    #define FSL_FEATURE_SOC_UART_COUNT (6)
+    /* @brief USB availability on the SoC. */
+    #define FSL_FEATURE_SOC_USB_COUNT (1)
+    /* @brief USBDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+    /* @brief USBHSDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+    /* @brief USBPHY availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+    /* @brief VREF availability on the SoC. */
+    #define FSL_FEATURE_SOC_VREF_COUNT (1)
+    /* @brief WDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_WDOG_COUNT (1)
+    /* @brief XBAR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XBAR_COUNT (0)
+    /* @brief XCVR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XCVR_COUNT (0)
+    /* @brief ZLL availability on the SoC. */
+    #define FSL_FEATURE_SOC_ZLL_COUNT (0)
+#elif defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12)
+    /* @brief ACMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_ACMP_COUNT (0)
+    /* @brief ADC16 availability on the SoC. */
+    #define FSL_FEATURE_SOC_ADC16_COUNT (2)
+    /* @brief AFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_AFE_COUNT (0)
+    /* @brief AIPS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AIPS_COUNT (2)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (0)
+    /* @brief AXBS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AXBS_COUNT (1)
+    /* @brief CADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CADC_COUNT (0)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief MMCAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
+    /* @brief CMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMP_COUNT (3)
+    /* @brief CMT availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMT_COUNT (1)
+    /* @brief CNC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CNC_COUNT (0)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief DAC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DAC_COUNT (1)
+    /* @brief DCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DCDC_COUNT (0)
+    /* @brief DDR availability on the SoC. */
+    #define FSL_FEATURE_SOC_DDR_COUNT (0)
+    /* @brief DMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMA_COUNT (0)
+    /* @brief DMAMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+    /* @brief DRY availability on the SoC. */
+    #define FSL_FEATURE_SOC_DRY_COUNT (0)
+    /* @brief DSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_DSPI_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EMVSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+    /* @brief ENC availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENC_COUNT (0)
+    /* @brief ENET availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENET_COUNT (1)
+    /* @brief EWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EWM_COUNT (1)
+    /* @brief FB availability on the SoC. */
+    #define FSL_FEATURE_SOC_FB_COUNT (1)
+    /* @brief FGPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+    /* @brief FLEXIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FSKDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+    /* @brief FTFA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFA_COUNT (0)
+    /* @brief FTFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFE_COUNT (1)
+    /* @brief FTFL availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFL_COUNT (0)
+    /* @brief FTM availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTM_COUNT (4)
+    /* @brief FTMRA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+    /* @brief FTMRE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+    /* @brief FTMRH availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief HSADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_HSADC_COUNT (0)
+    /* @brief I2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2C_COUNT (3)
+    /* @brief I2S availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2S_COUNT (1)
+    /* @brief ICS availability on the SoC. */
+    #define FSL_FEATURE_SOC_ICS_COUNT (0)
+    /* @brief IRQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_IRQ_COUNT (0)
+    /* @brief KBI availability on the SoC. */
+    #define FSL_FEATURE_SOC_KBI_COUNT (0)
+    /* @brief SLCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_SLCD_COUNT (0)
+    /* @brief LCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LCDC_COUNT (0)
+    /* @brief LDO availability on the SoC. */
+    #define FSL_FEATURE_SOC_LDO_COUNT (0)
+    /* @brief LLWU availability on the SoC. */
+    #define FSL_FEATURE_SOC_LLWU_COUNT (1)
+    /* @brief LMEM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LMEM_COUNT (0)
+    /* @brief LPSCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPTPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (0)
+    /* @brief LTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LTC_COUNT (0)
+    /* @brief MC availability on the SoC. */
+    #define FSL_FEATURE_SOC_MC_COUNT (0)
+    /* @brief MCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCG_COUNT (1)
+    /* @brief MCGLITE availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+    /* @brief MCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCM_COUNT (1)
+    /* @brief MMAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMAU_COUNT (0)
+    /* @brief MMDVSQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+    /* @brief MPU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MPU_COUNT (1)
+    /* @brief MSCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+    /* @brief MTB availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTB_COUNT (0)
+    /* @brief MTBDWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
+    /* @brief NFC availability on the SoC. */
+    #define FSL_FEATURE_SOC_NFC_COUNT (0)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+    /* @brief OSC availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSC_COUNT (1)
+    /* @brief OTFAD availability on the SoC. */
+    #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+    /* @brief PDB availability on the SoC. */
+    #define FSL_FEATURE_SOC_PDB_COUNT (1)
+    /* @brief PGA availability on the SoC. */
+    #define FSL_FEATURE_SOC_PGA_COUNT (0)
+    /* @brief PIT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PIT_COUNT (1)
+    /* @brief PMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_PMC_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (0)
+    /* @brief PWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWT_COUNT (0)
+    /* @brief QuadSPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+    /* @brief RCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RCM_COUNT (1)
+    /* @brief RFSYS availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+    /* @brief RFVBAT availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+    /* @brief RNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNG_COUNT (1)
+    /* @brief RNGB availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNGB_COUNT (0)
+    /* @brief ROM availability on the SoC. */
+    #define FSL_FEATURE_SOC_ROM_COUNT (0)
+    /* @brief RSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RSIM_COUNT (0)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCI_COUNT (0)
+    /* @brief SDHC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDHC_COUNT (1)
+    /* @brief SDRAM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+    /* @brief SIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SIM_COUNT (1)
+    /* @brief SMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMC_COUNT (1)
+    /* @brief SPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPI_COUNT (0)
+    /* @brief TMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_TMR_COUNT (0)
+    /* @brief TPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_TPM_COUNT (0)
+    /* @brief TRIAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+    /* @brief TRNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRNG_COUNT (0)
+    /* @brief TSI availability on the SoC. */
+    #define FSL_FEATURE_SOC_TSI_COUNT (0)
+    /* @brief UART availability on the SoC. */
+    #define FSL_FEATURE_SOC_UART_COUNT (6)
+    /* @brief USB availability on the SoC. */
+    #define FSL_FEATURE_SOC_USB_COUNT (1)
+    /* @brief USBDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+    /* @brief USBHSDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+    /* @brief USBPHY availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+    /* @brief VREF availability on the SoC. */
+    #define FSL_FEATURE_SOC_VREF_COUNT (1)
+    /* @brief WDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_WDOG_COUNT (1)
+    /* @brief XBAR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XBAR_COUNT (0)
+    /* @brief XCVR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XCVR_COUNT (0)
+    /* @brief ZLL availability on the SoC. */
+    #define FSL_FEATURE_SOC_ZLL_COUNT (0)
+#endif
+
+/* CRC module features */
+
+/* @brief Has data register with name CRC */
+#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (DMA_INSTANCE_COUNT * 16)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (DMAMUX_INSTANCE_COUNT * 16)
+/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+
+/* ENET module features */
+
+/* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */
+#define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0)
+/* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */
+#define FSL_FEATURE_ENET_SUPPORT_PTP (1)
+/* @brief Number of associated interrupt vectors. */
+#define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
+/* @brief Errata 2597: No support for IEEE 1588 timestamp timer overflow interrupt. */
+#define FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT_ERRATA_2579 (0)
+/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
+#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
+
+/* EWM module features */
+
+/* @brief Has clock prescaler (register CLKPRESCALER). */
+#define FSL_FEATURE_EWM_HAS_PRESCALER  (0)
+
+/* FLEXBUS module features */
+
+/* No feature definitions */
+
+/* FLASH module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (0)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (1)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (131072)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00020000)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0001C000)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00018000)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00010000)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00000000)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00020000)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+#elif defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (0)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (1)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+#endif
+
+/* FTM module features */
+
+/* @brief Number of channels. */
+#define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
+#define FSL_FEATURE_FTM_CHANNEL_COUNTx { 8, 2, 2, 8 }
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
+
+/* SAI module features */
+
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+#define FSL_FEATURE_SAI_FIFO_COUNT (8)
+/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
+#define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
+#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
+/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
+#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
+/* @brief Ihe interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
+
+/* LLWU module features */
+
+/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+/* @brief Has pins 8-15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+/* @brief Maximum number of internal modules connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+/* @brief Number of digital filters. */
+#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+/* @brief Has MF5 register. */
+#define FSL_FEATURE_LLWU_HAS_MF (0)
+/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1)
+/* @brief Has external pin 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
+/* @brief Has external pin 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
+/* @brief Has external pin 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
+/* @brief Has external pin 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
+/* @brief Has external pin 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
+/* @brief Has external pin 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
+/* @brief Has external pin 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
+/* @brief Has external pin 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
+/* @brief Has external pin 8 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
+/* @brief Has external pin 9 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
+/* @brief Has external pin 10 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
+/* @brief Has external pin 11 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
+/* @brief Has external pin 12 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
+/* @brief Has external pin 13 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
+/* @brief Has external pin 14 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
+/* @brief Has external pin 15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
+/* @brief Has external pin 16 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+/* @brief Has external pin 17 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+/* @brief Has external pin 18 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+/* @brief Has external pin 19 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+/* @brief Has external pin 20 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+/* @brief Has external pin 21 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+/* @brief Has external pin 22 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+/* @brief Has external pin 23 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+/* @brief Has external pin 24 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+/* @brief Has external pin 25 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+/* @brief Has external pin 26 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+/* @brief Has external pin 27 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+/* @brief Has external pin 28 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+/* @brief Has external pin 29 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+/* @brief Has external pin 30 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+/* @brief Has external pin 31 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+/* @brief Has internal module 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+/* @brief Has internal module 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+/* @brief Has internal module 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+/* @brief Has internal module 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+/* @brief Has internal module 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
+/* @brief Has internal module 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+/* @brief Has internal module 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+/* @brief Has internal module 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+
+/* MCG module features */
+
+/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
+/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
+/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
+/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
+/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
+/* @brief The PLL clock is divided by 2 before VCO divider. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
+/* @brief FRDIV supports 1280. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
+/* @brief FRDIV supports 1536. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
+#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
+/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
+#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
+/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_PLL1 (0)
+/* @brief Has 48MHz internal oscillator. */
+#define FSL_FEATURE_MCG_HAS_IRC_48M (1)
+/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_OSC1 (0)
+/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
+#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
+/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
+#define FSL_FEATURE_MCG_HAS_LOLRE (1)
+/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
+#define FSL_FEATURE_MCG_USE_OSCSEL (1)
+/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
+#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
+/* @brief TBD */
+#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL (1)
+/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
+/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
+/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
+#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
+/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
+#define FSL_FEATURE_MCG_HAS_FLL (1)
+/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
+/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
+#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
+/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
+/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
+/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
+#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
+/* @brief Has external clock monitor (register bit C6[CME]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
+/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
+#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
+/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
+#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
+/* @brief Has PEI mode or PBI mode. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
+/* @brief Reset clock mode is BLPI. */
+#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
+
+/* MPU module features */
+
+/* @brief Specifies number of descriptors available. */
+#define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12)
+/* @brief Has process identifier support. */
+#define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1)
+/* @brief Has master 0. */
+#define FSL_FEATURE_MPU_HAS_MASTER0 (1)
+/* @brief Has master 1. */
+#define FSL_FEATURE_MPU_HAS_MASTER1 (1)
+/* @brief Has master 2. */
+#define FSL_FEATURE_MPU_HAS_MASTER2 (1)
+/* @brief Has master 3. */
+#define FSL_FEATURE_MPU_HAS_MASTER3 (1)
+/* @brief Has master 4. */
+#define FSL_FEATURE_MPU_HAS_MASTER4 (1)
+/* @brief Has master 5. */
+#define FSL_FEATURE_MPU_HAS_MASTER5 (1)
+/* @brief Has master 6. */
+#define FSL_FEATURE_MPU_HAS_MASTER6 (0)
+/* @brief Has master 7. */
+#define FSL_FEATURE_MPU_HAS_MASTER7 (0)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
+
+/* OSC module features */
+
+/* @brief Has OSC1 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC1 (0)
+/* @brief Has OSC0 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC0 (0)
+/* @brief Has OSC external oscillator (without index). */
+#define FSL_FEATURE_OSC_HAS_OSC (1)
+/* @brief Number of OSC external oscillators. */
+#define FSL_FEATURE_OSC_OSC_COUNT (1)
+/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
+#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
+
+/* PDB module features */
+
+/* @brief Define the count of supporting ADC pre-trigger for each channel. */
+#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2)
+/* @brief Has DAC support. */
+#define FSL_FEATURE_PDB_HAS_DAC (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (4)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (1)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (1)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (1)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (1)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (1)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (0)
+
+/* RTC module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \
+    defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12)
+    /* @brief Has wakeup pin (bit field CR[WPS]). */
+    #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+    /* @brief Has low power features (registers MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+    /* @brief Has read/write access control (registers WAR and RAR). */
+    #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+    /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_SECURITY (1)
+#elif defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief Has wakeup pin (bit field CR[WPS]). */
+    #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+    /* @brief Has low power features (registers MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+    /* @brief Has read/write access control (registers WAR and RAR). */
+    #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+    /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_SECURITY (0)
+#endif
+
+/* SDHC module features */
+
+/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
+#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1)
+/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
+#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0)
+/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
+#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (1)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
+
+/* DSPI module features */
+
+/* @brief Receive/transmit FIFO size in number of items. */
+#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
+#define FSL_FEATURE_DSPI_FIFO_SIZEx { 4, 1, 1 }
+/* @brief Maximum transfer data width in bits. */
+#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
+/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
+#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
+/* @brief Number of chip select pins. */
+#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
+/* @brief Has chip select strobe capability on the PCS5 pin. */
+#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
+/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+/* @brief Has 16-bit data transfer support. */
+#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (0) : \
+    ((x) == 2 ? (0) : (-1))))
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
+
+/* UART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_HAS_FIFO (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_UART_IS_SCI (0)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_FIFO_SIZE (8)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
+/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
+#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (1) : \
+    ((x) == 2 ? (1) : \
+    ((x) == 3 ? (1) : \
+    ((x) == 4 ? (0) : \
+    ((x) == 5 ? (0) : (-1)))))))
+
+/* USB module features */
+
+/* @brief HOST mode enabled */
+#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
+/* @brief OTG mode enabled */
+#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
+/* @brief Has KEEP_ALIVE_CTRL register */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
+/* @brief Has the Dynamic SOF threshold compare support */
+#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
+/* @brief Has the VBUS detect support */
+#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
+/* @brief Has the IRC48M module clock support */
+#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief Describes the set of SC[MODE_LV] bitfield values */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+
+/* WDOG module features */
+
+/* @brief Watchdog is available. */
+#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
+/* @brief Has Wait mode support. */
+#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
+
+#endif /* __FSL_MK64F12_FEATURES_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/Workspace/FTM_AND_PWM/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h b/Workspace/FTM_AND_PWM/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
new file mode 100644
index 0000000..0044bbf
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
@@ -0,0 +1,111 @@
+/*
+** ###################################################################
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Register bit field access macros.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+#ifndef _FSL_BITACCESS_H
+#define _FSL_BITACCESS_H  1
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/**
+ * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+#endif /* _FSL_BITACCESS_H */
+
+/******************************************************************************/
diff --git a/Workspace/FTM_AND_PWM/SDK/platform/devices/fsl_device_registers.h b/Workspace/FTM_AND_PWM/SDK/platform/devices/fsl_device_registers.h
new file mode 100644
index 0000000..abeb4ac
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/SDK/platform/devices/fsl_device_registers.h
@@ -0,0 +1,1083 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2014-05-15
+**     Build:               b141209
+**
+**     Abstract:
+**         Common include file for CMSIS register access layer headers.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-05-15)
+**         Customer release.
+**
+** ###################################################################
+*/
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \
+    defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10))
+
+    #define K02F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK02F12810/include/MK02F12810.h"
+    /* Extension register definitions */
+    #include "MK02F12810/include/MK02F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK02F12810/include/MK02F12810_features.h"
+
+#elif (defined(CPU_MK10DN512VLK10) || defined(CPU_MK10DN512VLL10) || defined(CPU_MK10DX128VLQ10) || \
+    defined(CPU_MK10DX256VLQ10) || defined(CPU_MK10DN512VLQ10) || defined(CPU_MK10DN512VMC10) || \
+    defined(CPU_MK10DX128VMD10) || defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10))
+
+    #define K10D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK10D10/include/MK10D10.h"
+    /* Extension register definitions */
+    #include "MK10D10/include/MK10D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK10D10/include/MK10D10_features.h"
+
+#elif (defined(CPU_MK11DX128AVLK5) || defined(CPU_MK11DX256AVLK5) || defined(CPU_MK11DN512AVLK5) || \
+    defined(CPU_MK11DX128AVMC5) || defined(CPU_MK11DX256AVMC5) || defined(CPU_MK11DN512AVMC5))
+
+    #define K11DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK11DA5/include/MK11DA5.h"
+    /* Extension register definitions */
+    #include "MK11DA5/include/MK11DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK11DA5/include/MK11DA5_features.h"
+
+#elif (defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DX256VLK10) || defined(CPU_MK20DN512VLL10) || \
+    defined(CPU_MK20DX256VLL10) || defined(CPU_MK20DX128VLQ10) || defined(CPU_MK20DX256VLQ10) || \
+    defined(CPU_MK20DN512VLQ10) || defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || \
+    defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || defined(CPU_MK20DN512VMD10))
+
+    #define K20D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D10/include/MK20D10.h"
+    /* Extension register definitions */
+    #include "MK20D10/include/MK20D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D10/include/MK20D10_features.h"
+
+#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \
+    defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
+    defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
+    defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
+    defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \
+    defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
+    defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \
+    defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
+    defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
+    defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5))
+
+    #define K20D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D5/include/MK20D5.h"
+    /* Extension register definitions */
+    #include "MK20D5/include/MK20D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D5/include/MK20D5_features.h"
+
+#elif (defined(CPU_MK21DX128AVLK5) || defined(CPU_MK21DX256AVLK5) || defined(CPU_MK21DN512AVLK5) || \
+    defined(CPU_MK21DX128AVMC5) || defined(CPU_MK21DX256AVMC5) || defined(CPU_MK21DN512AVMC5))
+
+    #define K21DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21DA5/include/MK21DA5.h"
+    /* Extension register definitions */
+    #include "MK21DA5/include/MK21DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21DA5/include/MK21DA5_features.h"
+
+#elif (defined(CPU_MK21FX512AVLQ12) || defined(CPU_MK21FN1M0AVLQ12) || defined(CPU_MK21FX512AVMC12) || \
+    defined(CPU_MK21FN1M0AVMC12) || defined(CPU_MK21FX512AVMD12) || defined(CPU_MK21FN1M0AVMD12))
+
+    #define K21FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21FA12/include/MK21FA12.h"
+    /* Extension register definitions */
+    #include "MK21FA12/include/MK21FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21FA12/include/MK21FA12_features.h"
+
+#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \
+    defined(CPU_MK22FN128VMP10))
+
+    #define K22F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F12810/include/MK22F12810.h"
+    /* Extension register definitions */
+    #include "MK22F12810/include/MK22F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F12810/include/MK22F12810_features.h"
+
+#elif (defined(CPU_MK22FX512AVLH12) || defined(CPU_MK22FN1M0AVLH12) || defined(CPU_MK22FX512AVLK12) || \
+    defined(CPU_MK22FN1M0AVLK12) || defined(CPU_MK22FX512AVLL12) || defined(CPU_MK22FN1M0AVLL12) || \
+    defined(CPU_MK22FX512AVLQ12) || defined(CPU_MK22FN1M0AVLQ12) || defined(CPU_MK22FX512AVMC12) || \
+    defined(CPU_MK22FN1M0AVMC12) || defined(CPU_MK22FX512AVMD12) || defined(CPU_MK22FN1M0AVMD12))
+
+    #define K22FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22FA12/include/MK22FA12.h"
+    /* Extension register definitions */
+    #include "MK22FA12/include/MK22FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22FA12/include/MK22FA12_features.h"
+
+#elif (defined(CPU_MK22FN256CAH12) || defined(CPU_MK22FN128CAH12) || defined(CPU_MK22FN256VDC12) || \
+    defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12))
+
+    #define K22F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F25612/include/MK22F25612.h"
+    /* Extension register definitions */
+    #include "MK22F25612/include/MK22F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F25612/include/MK22F25612_features.h"
+
+#elif (defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
+    defined(CPU_MK22FN512VLL12) || defined(CPU_MK22FN512VMP12))
+
+    #define K22F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F51212/include/MK22F51212.h"
+    /* Extension register definitions */
+    #include "MK22F51212/include/MK22F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F51212/include/MK22F51212_features.h"
+
+#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12))
+
+    #define K24F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F12/include/MK24F12.h"
+    /* Extension register definitions */
+    #include "MK24F12/include/MK24F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F12/include/MK24F12_features.h"
+
+#elif (defined(CPU_MK24FN256VDC12))
+
+    #define K24F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F25612/include/MK24F25612.h"
+    /* Extension register definitions */
+    #include "MK24F25612/include/MK24F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F25612/include/MK24F25612_features.h"
+
+#elif (defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VLQ18) || defined(CPU_MK26FN2M0VMD18) || \
+    defined(CPU_MK26FN2M0VMI18))
+
+    #define K26F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK26F18/include/MK26F18.h"
+    /* Extension register definitions */
+    #include "MK26F18/include/MK26F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK26F18/include/MK26F18_features.h"
+
+#elif (defined(CPU_MK30DN512VLK10) || defined(CPU_MK30DN512VLL10) || defined(CPU_MK30DX128VLQ10) || \
+    defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMC10) || \
+    defined(CPU_MK30DX128VMD10) || defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10))
+
+    #define K30D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK30D10/include/MK30D10.h"
+    /* Extension register definitions */
+    #include "MK30D10/include/MK30D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK30D10/include/MK30D10_features.h"
+
+#elif (defined(CPU_MK40DN512VLK10) || defined(CPU_MK40DN512VLL10) || defined(CPU_MK40DX128VLQ10) || \
+    defined(CPU_MK40DX256VLQ10) || defined(CPU_MK40DN512VLQ10) || defined(CPU_MK40DN512VMC10) || \
+    defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || defined(CPU_MK40DN512VMD10))
+
+    #define K40D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK40D10/include/MK40D10.h"
+    /* Extension register definitions */
+    #include "MK40D10/include/MK40D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK40D10/include/MK40D10_features.h"
+
+#elif (defined(CPU_MK50DX256CLL10) || defined(CPU_MK50DN512CLL10) || defined(CPU_MK50DN512CLQ10) || \
+    defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || defined(CPU_MK50DN512CMD10) || \
+    defined(CPU_MK50DX256CMD10) || defined(CPU_MK50DX256CLK10))
+
+    #define K50D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK50D10/include/MK50D10.h"
+    /* Extension register definitions */
+    #include "MK50D10/include/MK50D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK50D10/include/MK50D10_features.h"
+
+#elif (defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10) || defined(CPU_MK51DN256CLQ10) || \
+    defined(CPU_MK51DN512CLQ10) || defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || \
+    defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10) || defined(CPU_MK51DX256CLK10))
+
+    #define K51D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK51D10/include/MK51D10.h"
+    /* Extension register definitions */
+    #include "MK51D10/include/MK51D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK51D10/include/MK51D10_features.h"
+
+#elif (defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10))
+
+    #define K52D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK52D10/include/MK52D10.h"
+    /* Extension register definitions */
+    #include "MK52D10/include/MK52D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK52D10/include/MK52D10_features.h"
+
+#elif (defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || defined(CPU_MK53DN512CMD10) || \
+    defined(CPU_MK53DX256CMD10))
+
+    #define K53D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK53D10/include/MK53D10.h"
+    /* Extension register definitions */
+    #include "MK53D10/include/MK53D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK53D10/include/MK53D10_features.h"
+
+#elif (defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DN512VLL10) || \
+    defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DN512VLQ10) || \
+    defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || defined(CPU_MK60DN512VMC10) || \
+    defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10))
+
+    #define K60D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK60D10/include/MK60D10.h"
+    /* Extension register definitions */
+    #include "MK60D10/include/MK60D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK60D10/include/MK60D10_features.h"
+
+#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12))
+
+    #define K63F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK63F12/include/MK63F12.h"
+    /* Extension register definitions */
+    #include "MK63F12/include/MK63F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK63F12/include/MK63F12_features.h"
+
+#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
+    defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12))
+
+
+    #define K64F12_SERIES
+    /* CMSIS-style register definitions */
+    #include "MK64F12/include/MK64F12.h"
+    /* Extension register definitions */
+    #include "MK64F12/include/MK64F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK64F12/include/MK64F12_features.h"
+
+#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
+    defined(CPU_MK65FX1M0VMI18))
+
+    #define K65F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK65F18/include/MK65F18.h"
+    /* Extension register definitions */
+    #include "MK65F18/include/MK65F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK65F18/include/MK65F18_features.h"
+
+#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
+    defined(CPU_MK66FX1M0VMD18))
+
+    #define K66F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK66F18/include/MK66F18.h"
+    /* Extension register definitions */
+    #include "MK66F18/include/MK66F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK66F18/include/MK66F18_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12))
+
+    #define K70F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F12/include/MK70F12.h"
+    /* Extension register definitions */
+    #include "MK70F12/include/MK70F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F12/include/MK70F12_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+
+    #define K70F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F15/include/MK70F15.h"
+    /* Extension register definitions */
+    #include "MK70F15/include/MK70F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F15/include/MK70F15_features.h"
+
+#elif (defined(CPU_MK80FN256CAx15) || defined(CPU_MK80FN256VDC15) || defined(CPU_MK80FN256VLL15) || \
+    defined(CPU_MK80FN256VLQ15))
+
+    #define K80F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK80F25615/include/MK80F25615.h"
+    /* Extension register definitions */
+    #include "MK80F25615/include/MK80F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK80F25615/include/MK80F25615_features.h"
+
+#elif (defined(CPU_MK81FN256CAx15) || defined(CPU_MK81FN256VDC15) || defined(CPU_MK81FN256VLL15) || \
+    defined(CPU_MK81FN256VLQ15))
+
+    #define K81F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK81F25615/include/MK81F25615.h"
+    /* Extension register definitions */
+    #include "MK81F25615/include/MK81F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK81F25615/include/MK81F25615_features.h"
+
+#elif (defined(CPU_MK82FN256CAx15) || defined(CPU_MK82FN256VDC15) || defined(CPU_MK82FN256VLL15) || \
+    defined(CPU_MK82FN256VLQ15))
+
+    #define K82F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK82F25615/include/MK82F25615.h"
+    /* Extension register definitions */
+    #include "MK82F25615/include/MK82F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK82F25615/include/MK82F25615_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC2) || defined(CPU_MKE02Z32VLC2) || defined(CPU_MKE02Z16VLC2) || \
+    defined(CPU_MKE02Z64VLD2) || defined(CPU_MKE02Z32VLD2) || defined(CPU_MKE02Z16VLD2) || \
+    defined(CPU_MKE02Z64VLH2) || defined(CPU_MKE02Z64VQH2) || defined(CPU_MKE02Z32VLH2) || \
+    defined(CPU_MKE02Z32VQH2))
+
+    #define KE02Z2_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z2/include/MKE02Z2.h"
+    /* Extension register definitions */
+    #include "MKE02Z2/include/MKE02Z2_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z2/include/MKE02Z2_features.h"
+
+#elif (defined(CPU_SKEAZN64MLC2) || defined(CPU_SKEAZN32MLC2) || defined(CPU_SKEAZN16MLC2) || \
+    defined(CPU_SKEAZN64MLD2) || defined(CPU_SKEAZN32MLD2) || defined(CPU_SKEAZN16MLD2) || \
+    defined(CPU_SKEAZN64MLH2) || defined(CPU_SKEAZN32MLH2))
+
+    #define SKEAZN642_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN642/include/SKEAZN642.h"
+    /* Extension register definitions */
+    #include "SKEAZN642/include/SKEAZN642_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN642/include/SKEAZN642_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC4) || defined(CPU_MKE02Z32VLC4) || defined(CPU_MKE02Z16VLC4) || \
+    defined(CPU_MKE02Z64VLD4) || defined(CPU_MKE02Z32VLD4) || defined(CPU_MKE02Z16VLD4) || \
+    defined(CPU_MKE02Z64VLH4) || defined(CPU_MKE02Z64VQH4) || defined(CPU_MKE02Z32VLH4) || \
+    defined(CPU_MKE02Z32VQH4))
+
+    #define KE02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z4/include/MKE02Z4.h"
+    /* Extension register definitions */
+    #include "MKE02Z4/include/MKE02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z4/include/MKE02Z4_features.h"
+
+#elif (defined(CPU_MKE04Z128VLD4) || defined(CPU_MKE04Z64VLD4) || defined(CPU_MKE04Z128VLK4) || \
+    defined(CPU_MKE04Z64VLK4) || defined(CPU_MKE04Z128VQH4) || defined(CPU_MKE04Z64VQH4) || \
+    defined(CPU_MKE04Z128VLH4) || defined(CPU_MKE04Z64VLH4))
+
+    #define KE04Z1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284.h"
+    /* Extension register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_features.h"
+
+#elif (defined(CPU_MKE04Z8VFK4) || defined(CPU_MKE04Z8VTG4) || defined(CPU_MKE04Z8VWJ4))
+
+    #define KE04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z4/include/MKE04Z4.h"
+    /* Extension register definitions */
+    #include "MKE04Z4/include/MKE04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z4/include/MKE04Z4_features.h"
+
+#elif (defined(CPU_SKEAZN8MFK) || defined(CPU_SKEAZN8MTG))
+
+    #define SKEAZN84_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN84/include/SKEAZN84.h"
+    /* Extension register definitions */
+    #include "SKEAZN84/include/SKEAZN84_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN84/include/SKEAZN84_features.h"
+
+#elif (defined(CPU_MKE06Z128VLD4) || defined(CPU_MKE06Z64VLD4) || defined(CPU_MKE06Z128VLK4) || \
+    defined(CPU_MKE06Z64VLK4) || defined(CPU_MKE06Z128VQH4) || defined(CPU_MKE06Z64VQH4) || \
+    defined(CPU_MKE06Z128VLH4) || defined(CPU_MKE06Z64VLH4))
+
+    #define KE06Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE06Z4/include/MKE06Z4.h"
+    /* Extension register definitions */
+    #include "MKE06Z4/include/MKE06Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE06Z4/include/MKE06Z4_features.h"
+
+#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
+    defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \
+    defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4))
+
+    #define KL02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL02Z4/include/MKL02Z4.h"
+    /* Extension register definitions */
+    #include "MKL02Z4/include/MKL02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL02Z4/include/MKL02Z4_features.h"
+
+#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \
+    defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \
+    defined(CPU_MKL03Z32VFK4))
+
+    #define KL03Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL03Z4/include/MKL03Z4.h"
+    /* Extension register definitions */
+    #include "MKL03Z4/include/MKL03Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL03Z4/include/MKL03Z4_features.h"
+
+#elif (defined(CPU_MKL04Z8VFK4) || defined(CPU_MKL04Z16VFK4) || defined(CPU_MKL04Z32VFK4) || \
+    defined(CPU_MKL04Z8VLC4) || defined(CPU_MKL04Z16VLC4) || defined(CPU_MKL04Z32VLC4) || \
+    defined(CPU_MKL04Z8VFM4) || defined(CPU_MKL04Z16VFM4) || defined(CPU_MKL04Z32VFM4) || \
+    defined(CPU_MKL04Z16VLF4) || defined(CPU_MKL04Z32VLF4))
+
+    #define KL04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL04Z4/include/MKL04Z4.h"
+    /* Extension register definitions */
+    #include "MKL04Z4/include/MKL04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL04Z4/include/MKL04Z4_features.h"
+
+#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \
+    defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
+    defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
+    defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4))
+
+    #define KL05Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL05Z4/include/MKL05Z4.h"
+    /* Extension register definitions */
+    #include "MKL05Z4/include/MKL05Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL05Z4/include/MKL05Z4_features.h"
+
+#elif (defined(CPU_MKL13Z32VFM4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z32VFT4) || \
+    defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z32VLH4) || defined(CPU_MKL13Z64VLH4) || \
+    defined(CPU_MKL13Z32VLK4) || defined(CPU_MKL13Z64VLK4) || defined(CPU_MKL13Z32VMP4) || \
+    defined(CPU_MKL13Z64VMP4))
+
+    #define KL13Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL13Z644/include/MKL13Z644.h"
+    /* Extension register definitions */
+    #include "MKL13Z644/include/MKL13Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL13Z644/include/MKL13Z644_features.h"
+
+#elif (defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || defined(CPU_MKL14Z32VFT4) || \
+    defined(CPU_MKL14Z64VFT4) || defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || \
+    defined(CPU_MKL14Z32VLK4) || defined(CPU_MKL14Z64VLK4))
+
+    #define KL14Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL14Z4/include/MKL14Z4.h"
+    /* Extension register definitions */
+    #include "MKL14Z4/include/MKL14Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL14Z4/include/MKL14Z4_features.h"
+
+#elif (defined(CPU_MKL15Z128CAD4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || \
+    defined(CPU_MKL15Z128VFM4) || defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || \
+    defined(CPU_MKL15Z128VFT4) || defined(CPU_MKL15Z32VLH4) || defined(CPU_MKL15Z64VLH4) || \
+    defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || defined(CPU_MKL15Z64VLK4) || \
+    defined(CPU_MKL15Z128VLK4))
+
+    #define KL15Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL15Z4/include/MKL15Z4.h"
+    /* Extension register definitions */
+    #include "MKL15Z4/include/MKL15Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL15Z4/include/MKL15Z4_features.h"
+
+#elif (defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || \
+    defined(CPU_MKL16Z32VFT4) || defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || \
+    defined(CPU_MKL16Z32VLH4) || defined(CPU_MKL16Z64VLH4) || defined(CPU_MKL16Z128VLH4) || \
+    defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VMP4))
+
+    #define KL16Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL16Z4/include/MKL16Z4.h"
+    /* Extension register definitions */
+    #include "MKL16Z4/include/MKL16Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL16Z4/include/MKL16Z4_features.h"
+
+#elif (defined(CPU_MKL17Z128VFM4) || defined(CPU_MKL17Z256VFM4) || defined(CPU_MKL17Z128VFT4) || \
+    defined(CPU_MKL17Z256VFT4) || defined(CPU_MKL17Z128VLH4) || defined(CPU_MKL17Z256VLH4) || \
+    defined(CPU_MKL17Z128VMP4) || defined(CPU_MKL17Z256VMP4))
+
+    #define KL17Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z4/include/MKL17Z4.h"
+    /* Extension register definitions */
+    #include "MKL17Z4/include/MKL17Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z4/include/MKL17Z4_features.h"
+
+#elif (defined(CPU_MKL17Z32VDA4) || defined(CPU_MKL17Z64VDA4) || defined(CPU_MKL17Z32VFM4) || \
+    defined(CPU_MKL17Z64VFM4) || defined(CPU_MKL17Z32VFT4) || defined(CPU_MKL17Z64VFT4) || \
+    defined(CPU_MKL17Z32VLH4) || defined(CPU_MKL17Z64VLH4) || defined(CPU_MKL17Z32VMP4) || \
+    defined(CPU_MKL17Z64VMP4))
+
+    #define KL17Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z644/include/MKL17Z644.h"
+    /* Extension register definitions */
+    #include "MKL17Z644/include/MKL17Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z644/include/MKL17Z644_features.h"
+
+#elif (defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || defined(CPU_MKL24Z32VFT4) || \
+    defined(CPU_MKL24Z64VFT4) || defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || \
+    defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4))
+
+    #define KL24Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL24Z4/include/MKL24Z4.h"
+    /* Extension register definitions */
+    #include "MKL24Z4/include/MKL24Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL24Z4/include/MKL24Z4_features.h"
+
+#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
+    defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
+    defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
+    defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
+
+    #define KL25Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL25Z4/include/MKL25Z4.h"
+    /* Extension register definitions */
+    #include "MKL25Z4/include/MKL25Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL25Z4/include/MKL25Z4_features.h"
+
+
+#elif (defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || \
+    defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || \
+    defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || \
+    defined(CPU_MKL26Z128VLH4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z128VLL4) || \
+    defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
+    defined(CPU_MKL26Z256VMP4))
+
+    #define KL26Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL26Z4/include/MKL26Z4.h"
+    /* Extension register definitions */
+    #include "MKL26Z4/include/MKL26Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL26Z4/include/MKL26Z4_features.h"
+
+#elif (defined(CPU_MKL27Z128VFM4) || defined(CPU_MKL27Z256VFM4) || defined(CPU_MKL27Z128VFT4) || \
+    defined(CPU_MKL27Z256VFT4) || defined(CPU_MKL27Z128VLH4) || defined(CPU_MKL27Z256VLH4) || \
+    defined(CPU_MKL27Z128VMP4) || defined(CPU_MKL27Z256VMP4))
+
+    #define KL27Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z4/include/MKL27Z4.h"
+    /* Extension register definitions */
+    #include "MKL27Z4/include/MKL27Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z4/include/MKL27Z4_features.h"
+
+#elif (defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z64VDA4) || defined(CPU_MKL27Z32VFM4) || \
+    defined(CPU_MKL27Z64VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z64VFT4) || \
+    defined(CPU_MKL27Z32VLH4) || defined(CPU_MKL27Z64VLH4) || defined(CPU_MKL27Z32VMP4) || \
+    defined(CPU_MKL27Z64VMP4))
+
+    #define KL27Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z644/include/MKL27Z644.h"
+    /* Extension register definitions */
+    #include "MKL27Z644/include/MKL27Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z644/include/MKL27Z644_features.h"
+
+#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \
+    defined(CPU_MKL33Z256VMP4))
+
+    #define KL33Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z4/include/MKL33Z4.h"
+    /* Extension register definitions */
+    #include "MKL33Z4/include/MKL33Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z4/include/MKL33Z4_features.h"
+
+#elif (defined(CPU_MKL33Z32VFT4) || defined(CPU_MKL33Z64VFT4) || defined(CPU_MKL33Z32VLH4) || \
+    defined(CPU_MKL33Z64VLH4) || defined(CPU_MKL33Z32VLK4) || defined(CPU_MKL33Z64VLK4) || \
+    defined(CPU_MKL33Z32VMP4) || defined(CPU_MKL33Z64VMP4))
+
+    #define KL33Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z644/include/MKL33Z644.h"
+    /* Extension register definitions */
+    #include "MKL33Z644/include/MKL33Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z644/include/MKL33Z644_features.h"
+
+#elif (defined(CPU_MKL34Z64VLH4) || defined(CPU_MKL34Z64VLL4))
+
+    #define KL34Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL34Z4/include/MKL34Z4.h"
+    /* Extension register definitions */
+    #include "MKL34Z4/include/MKL34Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL34Z4/include/MKL34Z4_features.h"
+
+#elif (defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || \
+    defined(CPU_MKL36Z64VLL4) || defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || \
+    defined(CPU_MKL36Z128VMC4) || defined(CPU_MKL36Z256VMC4) || defined(CPU_MKL36Z256VMP4))
+
+    #define KL36Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL36Z4/include/MKL36Z4.h"
+    /* Extension register definitions */
+    #include "MKL36Z4/include/MKL36Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL36Z4/include/MKL36Z4_features.h"
+
+#elif (defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z128VMP4) || \
+    defined(CPU_MKL43Z256VMP4))
+
+    #define KL43Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL43Z4/include/MKL43Z4.h"
+    /* Extension register definitions */
+    #include "MKL43Z4/include/MKL43Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL43Z4/include/MKL43Z4_features.h"
+
+#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
+    defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \
+    defined(CPU_MKL46Z256VMP4))
+
+    #define KL46Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL46Z4/include/MKL46Z4.h"
+    /* Extension register definitions */
+    #include "MKL46Z4/include/MKL46Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL46Z4/include/MKL46Z4_features.h"
+
+#elif (defined(CPU_MKM14Z128AHH5) || defined(CPU_MKM14Z64AHH5))
+
+    #define KM14ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5.h"
+    /* Extension register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_features.h"
+
+#elif (defined(CPU_MKM33Z128ALH5) || defined(CPU_MKM33Z64ALH5) || defined(CPU_MKM33Z128ALL5) || \
+    defined(CPU_MKM33Z64ALL5))
+
+    #define KM33ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5.h"
+    /* Extension register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z128ALL5))
+
+    #define KM34ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5.h"
+    /* Extension register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z256VLL7) || defined(CPU_MKM34Z256VLQ7))
+
+    #define KM34Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34Z7/include/MKM34Z7.h"
+    /* Extension register definitions */
+    #include "MKM34Z7/include/MKM34Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34Z7/include/MKM34Z7_features.h"
+
+#elif (defined(CPU_MKV10Z16VFM7) || defined(CPU_MKV10Z16VLC7) || defined(CPU_MKV10Z16VLF7) || \
+    defined(CPU_MKV10Z32VFM7) || defined(CPU_MKV10Z32VLC7) || defined(CPU_MKV10Z32VLF7))
+
+    #define KV10Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z7/include/MKV10Z7.h"
+    /* Extension register definitions */
+    #include "MKV10Z7/include/MKV10Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z7/include/MKV10Z7_features.h"
+
+#elif (defined(CPU_MKV10Z128VFM7) || defined(CPU_MKV10Z128VLC7) || defined(CPU_MKV10Z128VLF7) || \
+    defined(CPU_MKV10Z128VLH7) || defined(CPU_MKV10Z64VFM7) || defined(CPU_MKV10Z64VLC7) || \
+    defined(CPU_MKV10Z64VLF7) || defined(CPU_MKV10Z64VLH7))
+
+    #define KV10Z1287_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z1287/include/MKV10Z1287.h"
+    /* Extension register definitions */
+    #include "MKV10Z1287/include/MKV10Z1287_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z1287/include/MKV10Z1287_features.h"
+
+#elif (defined(CPU_MKV11Z128VFM7) || defined(CPU_MKV11Z128VLC7) || defined(CPU_MKV11Z128VLF7) || \
+    defined(CPU_MKV11Z128VLH7) || defined(CPU_MKV11Z64VFM7) || defined(CPU_MKV11Z64VLC7) || \
+    defined(CPU_MKV11Z64VLF7) || defined(CPU_MKV11Z64VLH7))
+
+    #define KV11Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV11Z7/include/MKV11Z7.h"
+    /* Extension register definitions */
+    #include "MKV11Z7/include/MKV11Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV11Z7/include/MKV11Z7_features.h"
+
+#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
+    defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10))
+
+    #define KV30F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV30F12810/include/MKV30F12810.h"
+    /* Extension register definitions */
+    #include "MKV30F12810/include/MKV30F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV30F12810/include/MKV30F12810_features.h"
+
+#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10))
+
+    #define KV31F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F12810/include/MKV31F12810.h"
+    /* Extension register definitions */
+    #include "MKV31F12810/include/MKV31F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F12810/include/MKV31F12810_features.h"
+
+#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12))
+
+    #define KV31F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F25612/include/MKV31F25612.h"
+    /* Extension register definitions */
+    #include "MKV31F25612/include/MKV31F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F25612/include/MKV31F25612_features.h"
+
+#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12))
+
+    #define KV31F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F51212/include/MKV31F51212.h"
+    /* Extension register definitions */
+    #include "MKV31F51212/include/MKV31F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F51212/include/MKV31F51212_features.h"
+
+#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
+    defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15))
+
+    #define KV40F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV40F15/include/MKV40F15.h"
+    /* Extension register definitions */
+    #include "MKV40F15/include/MKV40F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV40F15/include/MKV40F15_features.h"
+
+#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15))
+
+    #define KV43F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV43F15/include/MKV43F15.h"
+    /* Extension register definitions */
+    #include "MKV43F15/include/MKV43F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV43F15/include/MKV43F15_features.h"
+
+#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15))
+
+    #define KV44F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV44F15/include/MKV44F15.h"
+    /* Extension register definitions */
+    #include "MKV44F15/include/MKV44F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV44F15/include/MKV44F15_features.h"
+
+#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \
+    defined(CPU_MKV45F256VLL15))
+
+    #define KV45F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV45F15/include/MKV45F15.h"
+    /* Extension register definitions */
+    #include "MKV45F15/include/MKV45F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV45F15/include/MKV45F15_features.h"
+
+#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \
+    defined(CPU_MKV46F256VLL15))
+
+    #define KV46F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV46F15/include/MKV46F15.h"
+    /* Extension register definitions */
+    #include "MKV46F15/include/MKV46F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV46F15/include/MKV46F15_features.h"
+
+#elif (defined(CPU_MKW01Z128CHN4))
+
+    #define KW01Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW01Z4/include/MKW01Z4.h"
+    /* Extension register definitions */
+    #include "MKW01Z4/include/MKW01Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW01Z4/include/MKW01Z4_features.h"
+
+#elif (defined(CPU_MKW20Z160VHT4))
+
+    #define KW20Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW20Z4/include/MKW20Z4.h"
+    /* Extension register definitions */
+    #include "MKW20Z4/include/MKW20Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW20Z4/include/MKW20Z4_features.h"
+
+#elif (defined(CPU_MKW21D256VHA5) || defined(CPU_MKW21D512VHA5))
+
+    #define KW21D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW21D5/include/MKW21D5.h"
+    /* Extension register definitions */
+    #include "MKW21D5/include/MKW21D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW21D5/include/MKW21D5_features.h"
+
+#elif (defined(CPU_MKW22D512VHA5))
+
+    #define KW22D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW22D5/include/MKW22D5.h"
+    /* Extension register definitions */
+    #include "MKW22D5/include/MKW22D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW22D5/include/MKW22D5_features.h"
+
+#elif (defined(CPU_MKW24D512VHA5))
+
+    #define KW24D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW24D5/include/MKW24D5.h"
+    /* Extension register definitions */
+    #include "MKW24D5/include/MKW24D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW24D5/include/MKW24D5_features.h"
+
+#elif (defined(CPU_MKW30Z160VHM4))
+
+    #define KW30Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW30Z4/include/MKW30Z4.h"
+    /* Extension register definitions */
+    #include "MKW30Z4/include/MKW30Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW30Z4/include/MKW30Z4_features.h"
+
+#elif (defined(CPU_MKW40Z160VHT4))
+
+    #define KW40Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW40Z4/include/MKW40Z4.h"
+    /* Extension register definitions */
+    #include "MKW40Z4/include/MKW40Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW40Z4/include/MKW40Z4_features.h"
+
+#elif (defined(CPU_SKEAZ128MLH) || defined(CPU_SKEAZ64MLH) || defined(CPU_SKEAZ128MLK) || \
+    defined(CPU_SKEAZ64MLK))
+
+    #define SKEAZ1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284.h"
+    /* Extension register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/Workspace/FTM_AND_PWM/Sources/main.c b/Workspace/FTM_AND_PWM/Sources/main.c
new file mode 100644
index 0000000..2daa5a2
--- /dev/null
+++ b/Workspace/FTM_AND_PWM/Sources/main.c
@@ -0,0 +1,34 @@
+#include "MK64F12.h"
+
+int main(void)
+{
+    SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK;/*Enable the FTM0 Clock*/
+    SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK;/*Enable the PORTD Clock*/
+    PORTD_PCR5 = PORT_PCR_MUX(4);/*MUX = ALT 4*/
+    NVIC_EnableIRQ(FTM0_IRQn);/*Enable the FTM Interrupt*/
+    FTM0_SC |= 0x004F;/*Setting TOIE = 1,CLKS = 01, PS = 111*/
+    FTM0_MOD = 32000;/*Setting the Modulo register = 32000*/
+    FTM0_C5SC |= 0x0028;/*Setting MSB = 1, ELSnB= 1*/
+    FTM0_C5V = 500;/*Value of the Channel*/
+    int i;
+    for (;;) {
+        i++; /*Just a Count*/
+    }
+    return 0;
+}
+
+void FTM0_IRQHandler (void)
+{
+    //Clear interrupt flag
+    unsigned long ChannelValue= FTM0_C5V;/*Take the value of the Channel to compare it*/
+    (void)FTM0_SC;
+    FTM0_SC |= 0x0080;/*FTM counter has overflow*/
+    if(ChannelValue< 32000)/*Channel Value > Modulo Value*/
+    {
+        FTM0_C5V += 500;/*Add 500 to Channel*/
+    }
+    else
+    {
+        FTM0_C5V = 0;/*Set Channel in 0*/
+    }
+}
diff --git a/Workspace/GPIO/.cproject b/Workspace/GPIO/.cproject
new file mode 100644
index 0000000..6b51f26
--- /dev/null
+++ b/Workspace/GPIO/.cproject
@@ -0,0 +1,128 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<macros>
+					<stringMacro name="PROJECT_KSDK_PATH" type="VALUE_TEXT" value="C:\Freescale\KSDK_1.3.0"/>
+				</macros>
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="GPIO" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.138424891" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
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+							<builder buildPath="${workspace_loc:/GPIO}/Debug" id="ilg.gnuarmeclipse.managedbuild.cross.builder.2018125917" name="Gnu Make Builder.Debug" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
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+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.416132893" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.2026894627" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="-specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs" valueType="string"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.1394898970" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="&quot;MK64FN1M0xxx12_flash.ld&quot;"/>
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.672556956" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1276352763" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.830299569" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.282145612" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
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+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.338169926" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1783546987" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
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+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.805423770" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.1404268138" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
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+						</toolChain>
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+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="GPIO.ilg.gnuarmeclipse.managedbuild.cross.target.elf.1672910064" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1102412416;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.13072522">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1648336251;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.1060554805">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/Workspace/GPIO/.cwGeneratedFileSetLog b/Workspace/GPIO/.cwGeneratedFileSetLog
new file mode 100644
index 0000000..da94cd8
--- /dev/null
+++ b/Workspace/GPIO/.cwGeneratedFileSetLog
@@ -0,0 +1,19 @@
+Sources/main.c
+Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
+SDK/platform/devices/MK64F12/include/MK64F12_extension.h
+SDK/platform/CMSIS/Include/arm_math.h
+SDK/platform/CMSIS/Include/core_cmSimd.h
+SDK/platform/devices/MK64F12/include/MK64F12.h
+SDK/platform/CMSIS/Include/core_cm4.h
+SDK/platform/CMSIS/Include/arm_common_tables.h
+SDK/platform/devices/MK64F12/include/MK64F12_features.h
+SDK/platform/devices/fsl_device_registers.h
+SDK/platform/CMSIS/Include/arm_const_structs.h
+SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
+SDK/platform/CMSIS/Include/core_cmFunc.h
+SDK/platform/CMSIS/Include/core_cmInstr.h
+Project_Settings/Startup_Code/system_MK64F12.h
+Project_Settings/Startup_Code/startup.c
+Project_Settings/Startup_Code/startup_MK64F12.S
+Project_Settings/Startup_Code/startup.h
+Project_Settings/Startup_Code/system_MK64F12.c
\ No newline at end of file
diff --git a/Workspace/GPIO/.project b/Workspace/GPIO/.project
new file mode 100644
index 0000000..73d850d
--- /dev/null
+++ b/Workspace/GPIO/.project
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>GPIO</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<variableList>
+		<variable>
+			<name>PROJECT_KSDK_PATH</name>
+			<value>file:/C:/Freescale/KSDK_1.3.0</value>
+		</variable>
+	</variableList>
+</projectDescription>
diff --git a/Workspace/GPIO/.settings/com.freescale.processorexpert.derivative.prefs b/Workspace/GPIO/.settings/com.freescale.processorexpert.derivative.prefs
new file mode 100644
index 0000000..60d5016
--- /dev/null
+++ b/Workspace/GPIO/.settings/com.freescale.processorexpert.derivative.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+versionGenerated/versionGenerated=1.0.0.RT7_b1550-0615
diff --git a/Workspace/GPIO/.settings/com.processorexpert.sdk.legacy.legacyprojectupdater.prefs b/Workspace/GPIO/.settings/com.processorexpert.sdk.legacy.legacyprojectupdater.prefs
new file mode 100644
index 0000000..7733bda
--- /dev/null
+++ b/Workspace/GPIO/.settings/com.processorexpert.sdk.legacy.legacyprojectupdater.prefs
@@ -0,0 +1 @@
+skip=true
\ No newline at end of file
diff --git a/Workspace/GPIO/.settings/language.settings.xml b/Workspace/GPIO/.settings/language.settings.xml
new file mode 100644
index 0000000..63c81d5
--- /dev/null
+++ b/Workspace/GPIO/.settings/language.settings.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="355957199812988073" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings Cross ARM" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/Workspace/GPIO/Debug/GPIO.elf b/Workspace/GPIO/Debug/GPIO.elf
new file mode 100644
index 0000000..cf29611
Binary files /dev/null and b/Workspace/GPIO/Debug/GPIO.elf differ
diff --git a/Workspace/GPIO/Debug/GPIO.map b/Workspace/GPIO/Debug/GPIO.map
new file mode 100644
index 0000000..fa23313
--- /dev/null
+++ b/Workspace/GPIO/Debug/GPIO.map
@@ -0,0 +1,610 @@
+Archive member included because of file (symbol)
+
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+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (exit)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_global_impure_ptr)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (__libc_init_array)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (memset)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_exit)
+
+Discarded input sections
+
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+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.extab     0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
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+ .debug_macro   0x00000000      0x180 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x22 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000       0x16 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000    0x16273 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000     0x1182 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data._impure_ptr
+                0x00000000        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .eh_frame      0x00000000        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+m_interrupts     0x00000000         0x00000400         xr
+m_flash_config   0x00000400         0x00000010         xr
+m_text           0x00000410         0x000ffbf0         xr
+m_data           0x1fff0000         0x00010000         rw
+m_data_2         0x20000000         0x00030000         rw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+LOAD ./Sources/main.o
+LOAD ./Project_Settings/Startup_Code/startup.o
+LOAD ./Project_Settings/Startup_Code/startup_MK64F12.o
+LOAD ./Project_Settings/Startup_Code/system_MK64F12.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libstdc++_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libm.a
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000400                HEAP_SIZE = DEFINED (__heap_size__)?__heap_size__:0x400
+                0x00000400                STACK_SIZE = DEFINED (__stack_size__)?__stack_size__:0x400
+                0x00000000                M_VECTOR_RAM_SIZE = DEFINED (__ram_vector_table__)?0x400:0x0
+
+.interrupts     0x00000000      0x400
+                0x00000000                __VECTOR_TABLE = .
+                0x00000000                . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector    0x00000000      0x400 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000000                __isr_vector
+                0x00000400                . = ALIGN (0x4)
+
+.flash_config   0x00000400       0x10
+                0x00000400                . = ALIGN (0x4)
+ *(.FlashConfig)
+ .FlashConfig   0x00000400       0x10 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000410                . = ALIGN (0x4)
+
+.text           0x00000410      0x444
+                0x00000410                . = ALIGN (0x4)
+ *(.text)
+ .text          0x00000410       0x54 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .text          0x00000464       0x74 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00000464                _start
+                0x00000464                _mainCRTStartup
+ .text          0x000004d8       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x000004d8                Reset_Handler
+                0x000004e8                DebugMon_Handler
+                0x000004e8                I2C0_IRQHandler
+                0x000004e8                HardFault_Handler
+                0x000004e8                SysTick_Handler
+                0x000004e8                UART3_RX_TX_IRQHandler
+                0x000004e8                PendSV_Handler
+                0x000004e8                NMI_Handler
+                0x000004e8                UART0_RX_TX_IRQHandler
+                0x000004e8                I2C1_IRQHandler
+                0x000004e8                DMA2_IRQHandler
+                0x000004e8                ENET_Error_IRQHandler
+                0x000004e8                CAN0_Tx_Warning_IRQHandler
+                0x000004e8                PIT0_IRQHandler
+                0x000004e8                CAN0_ORed_Message_buffer_IRQHandler
+                0x000004e8                CMP2_IRQHandler
+                0x000004e8                LLWU_IRQHandler
+                0x000004e8                ENET_Receive_IRQHandler
+                0x000004e8                ENET_1588_Timer_IRQHandler
+                0x000004e8                UART2_RX_TX_IRQHandler
+                0x000004e8                SWI_IRQHandler
+                0x000004e8                ADC0_IRQHandler
+                0x000004e8                UsageFault_Handler
+                0x000004e8                I2S0_Tx_IRQHandler
+                0x000004e8                CMT_IRQHandler
+                0x000004e8                UART4_RX_TX_IRQHandler
+                0x000004e8                SPI1_IRQHandler
+                0x000004e8                DefaultISR
+                0x000004e8                DMA9_IRQHandler
+                0x000004e8                DMA14_IRQHandler
+                0x000004e8                CMP1_IRQHandler
+                0x000004e8                Reserved71_IRQHandler
+                0x000004e8                PORTD_IRQHandler
+                0x000004e8                PORTB_IRQHandler
+                0x000004e8                UART4_ERR_IRQHandler
+                0x000004e8                ADC1_IRQHandler
+                0x000004e8                I2C2_IRQHandler
+                0x000004e8                PIT2_IRQHandler
+                0x000004e8                I2S0_Rx_IRQHandler
+                0x000004e8                DMA5_IRQHandler
+                0x000004e8                RTC_IRQHandler
+                0x000004e8                PDB0_IRQHandler
+                0x000004e8                CAN0_Rx_Warning_IRQHandler
+                0x000004e8                FTM1_IRQHandler
+                0x000004e8                UART5_RX_TX_IRQHandler
+                0x000004e8                UART3_ERR_IRQHandler
+                0x000004e8                PIT3_IRQHandler
+                0x000004e8                SDHC_IRQHandler
+                0x000004e8                RTC_Seconds_IRQHandler
+                0x000004e8                MCG_IRQHandler
+                0x000004e8                FTFE_IRQHandler
+                0x000004e8                UART2_ERR_IRQHandler
+                0x000004e8                DMA11_IRQHandler
+                0x000004e8                UART5_ERR_IRQHandler
+                0x000004e8                Read_Collision_IRQHandler
+                0x000004e8                DMA7_IRQHandler
+                0x000004e8                ENET_Transmit_IRQHandler
+                0x000004e8                USBDCD_IRQHandler
+                0x000004e8                USB0_IRQHandler
+                0x000004e8                SPI2_IRQHandler
+                0x000004e8                WDOG_EWM_IRQHandler
+                0x000004e8                MemManage_Handler
+                0x000004e8                SVC_Handler
+                0x000004e8                DMA13_IRQHandler
+                0x000004e8                DMA3_IRQHandler
+                0x000004e8                UART0_LON_IRQHandler
+                0x000004e8                RNG_IRQHandler
+                0x000004e8                DMA0_IRQHandler
+                0x000004e8                DMA15_IRQHandler
+                0x000004e8                DAC0_IRQHandler
+                0x000004e8                CAN0_Error_IRQHandler
+                0x000004e8                DMA4_IRQHandler
+                0x000004e8                PIT1_IRQHandler
+                0x000004e8                UART0_ERR_IRQHandler
+                0x000004e8                DMA_Error_IRQHandler
+                0x000004e8                LVD_LVW_IRQHandler
+                0x000004e8                SPI0_IRQHandler
+                0x000004e8                FTM0_IRQHandler
+                0x000004e8                PORTA_IRQHandler
+                0x000004e8                DAC1_IRQHandler
+                0x000004e8                MCM_IRQHandler
+                0x000004e8                DMA12_IRQHandler
+                0x000004e8                CAN0_Bus_Off_IRQHandler
+                0x000004e8                FTM3_IRQHandler
+                0x000004e8                PORTE_IRQHandler
+                0x000004e8                FTM2_IRQHandler
+                0x000004e8                LPTMR0_IRQHandler
+                0x000004e8                BusFault_Handler
+                0x000004e8                DMA8_IRQHandler
+                0x000004e8                DMA10_IRQHandler
+                0x000004e8                CAN0_Wake_Up_IRQHandler
+                0x000004e8                UART1_ERR_IRQHandler
+                0x000004e8                UART1_RX_TX_IRQHandler
+                0x000004e8                CMP0_IRQHandler
+                0x000004e8                PORTC_IRQHandler
+                0x000004e8                DMA6_IRQHandler
+                0x000004e8                DMA1_IRQHandler
+ *(.text*)
+ .text.main     0x000004ec      0x1b8 ./Sources/main.o
+                0x000004ec                main
+ .text.init_data_bss
+                0x000006a4       0xcc ./Project_Settings/Startup_Code/startup.o
+                0x000006a4                init_data_bss
+ .text.SystemInit
+                0x00000770       0x3c ./Project_Settings/Startup_Code/system_MK64F12.o
+                0x00000770                SystemInit
+ .text.exit     0x000007ac       0x28 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+                0x000007ac                exit
+ .text.__libc_init_array
+                0x000007d4       0x4c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                0x000007d4                __libc_init_array
+ .text.memset   0x00000820       0x10 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                0x00000820                memset
+ .text._exit    0x00000830        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                0x00000830                _exit
+ *(.rodata)
+ *(.rodata*)
+ .rodata.str1.1
+                0x00000834        0x2 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *fill*         0x00000836        0x2 
+ .rodata._global_impure_ptr
+                0x00000838        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                0x00000838                _global_impure_ptr
+ *(.glue_7)
+ .glue_7        0x00000000        0x0 linker stubs
+ *(.glue_7t)
+ .glue_7t       0x00000000        0x0 linker stubs
+ *(.eh_frame)
+ .eh_frame      0x0000083c        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.init)
+ .init          0x0000083c        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x0000083c                _init
+ .init          0x00000840        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ *(.fini)
+ .fini          0x00000848        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x00000848                _fini
+ .fini          0x0000084c        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000854                . = ALIGN (0x4)
+
+.vfp11_veneer   0x00000854        0x0
+ .vfp11_veneer  0x00000000        0x0 linker stubs
+
+.v4_bx          0x00000854        0x0
+ .v4_bx         0x00000000        0x0 linker stubs
+
+.iplt           0x00000854        0x0
+ .iplt          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM            0x00000854        0x8
+                0x00000854                __exidx_start = .
+ *(.ARM.exidx*)
+ .ARM.exidx     0x00000854        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x0000085c                __exidx_end = .
+
+.rel.dyn        0x0000085c        0x0
+ .rel.iplt      0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ctors          0x0000085c        0x0
+                0x0000085c                __CTOR_LIST__ = .
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+                0x0000085c                __CTOR_END__ = .
+
+.dtors          0x0000085c        0x0
+                0x0000085c                __DTOR_LIST__ = .
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+                0x0000085c                __DTOR_END__ = .
+
+.preinit_array  0x0000085c        0x0
+                0x0000085c                PROVIDE (__preinit_array_start, .)
+ *(.preinit_array*)
+                0x0000085c                PROVIDE (__preinit_array_end, .)
+
+.init_array     0x0000085c        0x4
+                0x0000085c                PROVIDE (__init_array_start, .)
+ *(SORT(.init_array.*))
+ *(.init_array*)
+ .init_array    0x0000085c        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x00000860                PROVIDE (__init_array_end, .)
+
+.fini_array     0x00000860        0x4
+                0x00000860                PROVIDE (__fini_array_start, .)
+ *(SORT(.fini_array.*))
+ *(.fini_array*)
+ .fini_array    0x00000860        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x00000864                PROVIDE (__fini_array_end, .)
+                0x00000864                __etext = .
+                0x00000864                __DATA_ROM = .
+
+.interrupts_ram
+                0x1fff0000        0x0
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __VECTOR_RAM__ = .
+                0x1fff0000                __interrupts_ram_start__ = .
+ *(.m_interrupts_ram)
+                0x1fff0000                . = (. + M_VECTOR_RAM_SIZE)
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __interrupts_ram_end__ = .
+                0x00000000                __VECTOR_RAM = DEFINED (__ram_vector_table__)?__VECTOR_RAM__:ORIGIN (m_interrupts)
+                0x00000000                __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED (__ram_vector_table__)?(__interrupts_ram_end__ - __interrupts_ram_start__):0x0
+
+.data           0x1fff0000       0x64 load address 0x00000864
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __DATA_RAM = .
+                0x1fff0000                __data_start__ = .
+ *(.data)
+ *(.data*)
+ .data.impure_data
+                0x1fff0000       0x60 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *(.jcr*)
+ .jcr           0x1fff0060        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .jcr           0x1fff0060        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __data_end__ = .
+                0x000008c8                __DATA_END = (__DATA_ROM + (__data_end__ - __data_start__))
+                0x00100000                text_end = (ORIGIN (m_text) + 0xffbf0)
+                0x00000001                ASSERT ((__DATA_END <= text_end), region m_text overflowed with text and data)
+
+.igot.plt       0x1fff0064        0x0 load address 0x000008c8
+ .igot.plt      0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.bss            0x1fff0064       0x1c load address 0x000008c8
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __START_BSS = .
+                0x1fff0064                __bss_start__ = .
+ *(.bss)
+ .bss           0x1fff0064       0x1c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.bss*)
+ *(COMMON)
+                0x1fff0080                . = ALIGN (0x4)
+                0x1fff0080                __bss_end__ = .
+                0x1fff0080                __END_BSS = .
+
+.heap           0x20000000      0x400
+                0x20000000                . = ALIGN (0x8)
+                0x20000000                __end__ = .
+                0x20000000                PROVIDE (end, .)
+                0x20000000                __HeapBase = .
+                0x20000400                . = (. + HEAP_SIZE)
+ *fill*         0x20000000      0x400 
+                0x20000400                __HeapLimit = .
+
+.stack          0x20000400      0x400
+                0x20000400                . = ALIGN (0x8)
+                0x20000800                . = (. + STACK_SIZE)
+ *fill*         0x20000400      0x400 
+                0x20030000                __StackTop = (ORIGIN (m_data_2) + 0x30000)
+                0x2002fc00                __StackLimit = (__StackTop - STACK_SIZE)
+                0x20030000                PROVIDE (__stack, __StackTop)
+
+.ARM.attributes
+                0x00000000       0x30
+ *(.ARM.attributes)
+ .ARM.attributes
+                0x00000000       0x22 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .ARM.attributes
+                0x00000022       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .ARM.attributes
+                0x00000056       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.attributes
+                0x00000076       0x39 ./Sources/main.o
+ .ARM.attributes
+                0x000000af       0x39 ./Project_Settings/Startup_Code/startup.o
+ .ARM.attributes
+                0x000000e8       0x1f ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .ARM.attributes
+                0x00000107       0x39 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .ARM.attributes
+                0x00000140       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .ARM.attributes
+                0x00000174       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .ARM.attributes
+                0x000001a8       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .ARM.attributes
+                0x000001dc       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .ARM.attributes
+                0x00000210       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .ARM.attributes
+                0x00000244       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .ARM.attributes
+                0x00000278       0x22 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000001                ASSERT ((__StackLimit >= __HeapLimit), region m_data_2 overflowed with stack and heap)
+OUTPUT(GPIO.elf elf32-littlearm)
+
+.debug_info     0x00000000      0xe12
+ .debug_info    0x00000000      0x3d1 ./Sources/main.o
+ .debug_info    0x000003d1      0x3a7 ./Project_Settings/Startup_Code/startup.o
+ .debug_info    0x00000778       0x8a ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_info    0x00000802      0x610 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_abbrev   0x00000000      0x31b
+ .debug_abbrev  0x00000000       0xf3 ./Sources/main.o
+ .debug_abbrev  0x000000f3       0xfa ./Project_Settings/Startup_Code/startup.o
+ .debug_abbrev  0x000001ed       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_abbrev  0x00000201      0x11a ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_aranges  0x00000000       0x88
+ .debug_aranges
+                0x00000000       0x20 ./Sources/main.o
+ .debug_aranges
+                0x00000020       0x20 ./Project_Settings/Startup_Code/startup.o
+ .debug_aranges
+                0x00000040       0x20 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_aranges
+                0x00000060       0x28 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_ranges   0x00000000       0x38
+ .debug_ranges  0x00000000       0x10 ./Sources/main.o
+ .debug_ranges  0x00000010       0x10 ./Project_Settings/Startup_Code/startup.o
+ .debug_ranges  0x00000020       0x18 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_macro    0x00000000    0x30d8e
+ .debug_macro   0x00000000       0x8d ./Sources/main.o
+ .debug_macro   0x0000008d      0x856 ./Sources/main.o
+ .debug_macro   0x000008e3       0x16 ./Sources/main.o
+ .debug_macro   0x000008f9       0x16 ./Sources/main.o
+ .debug_macro   0x0000090f       0x44 ./Sources/main.o
+ .debug_macro   0x00000953      0x209 ./Sources/main.o
+ .debug_macro   0x00000b5c       0x56 ./Sources/main.o
+ .debug_macro   0x00000bb2       0x3b ./Sources/main.o
+ .debug_macro   0x00000bed       0x34 ./Sources/main.o
+ .debug_macro   0x00000c21       0x26 ./Sources/main.o
+ .debug_macro   0x00000c47      0xd1d ./Sources/main.o
+ .debug_macro   0x00001964       0x78 ./Sources/main.o
+ .debug_macro   0x000019dc    0x1773b ./Sources/main.o
+ .debug_macro   0x00019117      0x171 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019288       0x11 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019299       0x58 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000192f1       0x35 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019326       0xa3 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193c9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193df      0x10e ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000194ed       0x7f ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0001956c       0x52 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195be       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195d4       0x43 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019617      0x180 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019797       0x22 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197b9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197cf    0x16273 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0002fa42     0x1182 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00030bc4      0x162 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00030d26       0x68 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_line     0x00000000      0x9c3
+ .debug_line    0x00000000      0x276 ./Sources/main.o
+ .debug_line    0x00000276      0x358 ./Project_Settings/Startup_Code/startup.o
+ .debug_line    0x000005ce       0x6a ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_line    0x00000638      0x38b ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_str      0x00000000   0x19cab2
+ .debug_str     0x00000000    0x8fafc ./Sources/main.o
+                              0x8fc66 (size before relaxing)
+ .debug_str     0x0008fafc   0x10cec1 ./Project_Settings/Startup_Code/startup.o
+                             0x19ca78 (size before relaxing)
+ .debug_str     0x0019c9bd       0xf5 ./Project_Settings/Startup_Code/system_MK64F12.o
+                             0x19cb33 (size before relaxing)
+
+.comment        0x00000000       0x70
+ .comment       0x00000000       0x70 ./Sources/main.o
+                                 0x71 (size before relaxing)
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/startup.o
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_frame    0x00000000      0x130
+ .debug_frame   0x00000000       0x2c ./Sources/main.o
+ .debug_frame   0x0000002c       0x2c ./Project_Settings/Startup_Code/startup.o
+ .debug_frame   0x00000058       0x44 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_frame   0x0000009c       0x28 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .debug_frame   0x000000c4       0x2c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .debug_frame   0x000000f0       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .debug_frame   0x00000110       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
diff --git a/Workspace/GPIO/Debug/Project_Settings/Startup_Code/startup.d b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/startup.d
new file mode 100644
index 0000000..09df623
--- /dev/null
+++ b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/startup.d
@@ -0,0 +1,38 @@
+Project_Settings/Startup_Code/startup.o: \
+ ../Project_Settings/Startup_Code/startup.c \
+ ../Project_Settings/Startup_Code/startup.h \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h
+
+../Project_Settings/Startup_Code/startup.h:
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
diff --git a/Workspace/GPIO/Debug/Project_Settings/Startup_Code/startup.o b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/startup.o
new file mode 100644
index 0000000..83add89
Binary files /dev/null and b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/startup.o differ
diff --git a/Workspace/GPIO/Debug/Project_Settings/Startup_Code/startup_MK64F12.d b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/startup_MK64F12.d
new file mode 100644
index 0000000..15e90f1
--- /dev/null
+++ b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/startup_MK64F12.d
@@ -0,0 +1,2 @@
+Project_Settings/Startup_Code/startup_MK64F12.o: \
+ ../Project_Settings/Startup_Code/startup_MK64F12.S
diff --git a/Workspace/GPIO/Debug/Project_Settings/Startup_Code/startup_MK64F12.o b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/startup_MK64F12.o
new file mode 100644
index 0000000..abfb149
Binary files /dev/null and b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/startup_MK64F12.o differ
diff --git a/Workspace/GPIO/Debug/Project_Settings/Startup_Code/subdir.mk b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/subdir.mk
new file mode 100644
index 0000000..1e5a1fb
--- /dev/null
+++ b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/subdir.mk
@@ -0,0 +1,41 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Project_Settings/Startup_Code/startup.c \
+../Project_Settings/Startup_Code/system_MK64F12.c 
+
+S_UPPER_SRCS += \
+../Project_Settings/Startup_Code/startup_MK64F12.S 
+
+OBJS += \
+./Project_Settings/Startup_Code/startup.o \
+./Project_Settings/Startup_Code/startup_MK64F12.o \
+./Project_Settings/Startup_Code/system_MK64F12.o 
+
+C_DEPS += \
+./Project_Settings/Startup_Code/startup.d \
+./Project_Settings/Startup_Code/system_MK64F12.d 
+
+S_UPPER_DEPS += \
+./Project_Settings/Startup_Code/startup_MK64F12.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Project_Settings/Startup_Code/%.o: ../Project_Settings/Startup_Code/%.c
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM C Compiler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+Project_Settings/Startup_Code/%.o: ../Project_Settings/Startup_Code/%.S
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM GNU Assembler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+
diff --git a/Workspace/GPIO/Debug/Project_Settings/Startup_Code/system_MK64F12.d b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/system_MK64F12.d
new file mode 100644
index 0000000..d0e2961
--- /dev/null
+++ b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/system_MK64F12.d
@@ -0,0 +1,35 @@
+Project_Settings/Startup_Code/system_MK64F12.o: \
+ ../Project_Settings/Startup_Code/system_MK64F12.c \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
diff --git a/Workspace/GPIO/Debug/Project_Settings/Startup_Code/system_MK64F12.o b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/system_MK64F12.o
new file mode 100644
index 0000000..0dd820e
Binary files /dev/null and b/Workspace/GPIO/Debug/Project_Settings/Startup_Code/system_MK64F12.o differ
diff --git a/Workspace/GPIO/Debug/Sources/main.d b/Workspace/GPIO/Debug/Sources/main.d
new file mode 100644
index 0000000..6984a8b
--- /dev/null
+++ b/Workspace/GPIO/Debug/Sources/main.d
@@ -0,0 +1,19 @@
+Sources/main.o: ../Sources/main.c \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
diff --git a/Workspace/GPIO/Debug/Sources/main.o b/Workspace/GPIO/Debug/Sources/main.o
new file mode 100644
index 0000000..f2f586a
Binary files /dev/null and b/Workspace/GPIO/Debug/Sources/main.o differ
diff --git a/Workspace/GPIO/Debug/Sources/subdir.mk b/Workspace/GPIO/Debug/Sources/subdir.mk
new file mode 100644
index 0000000..95aa41f
--- /dev/null
+++ b/Workspace/GPIO/Debug/Sources/subdir.mk
@@ -0,0 +1,24 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Sources/main.c 
+
+OBJS += \
+./Sources/main.o 
+
+C_DEPS += \
+./Sources/main.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Sources/%.o: ../Sources/%.c
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM C Compiler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+
diff --git a/Workspace/GPIO/Debug/makefile b/Workspace/GPIO/Debug/makefile
new file mode 100644
index 0000000..ab1d5d6
--- /dev/null
+++ b/Workspace/GPIO/Debug/makefile
@@ -0,0 +1,77 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include Sources/subdir.mk
+-include Project_Settings/Startup_Code/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C++_DEPS)),)
+-include $(C++_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+ifneq ($(strip $(ASM_DEPS)),)
+-include $(ASM_DEPS)
+endif
+ifneq ($(strip $(CC_DEPS)),)
+-include $(CC_DEPS)
+endif
+ifneq ($(strip $(CPP_DEPS)),)
+-include $(CPP_DEPS)
+endif
+ifneq ($(strip $(CXX_DEPS)),)
+-include $(CXX_DEPS)
+endif
+ifneq ($(strip $(C_UPPER_DEPS)),)
+-include $(C_UPPER_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables 
+SECONDARY_SIZE += \
+GPIO.siz \
+
+
+# All Target
+all: GPIO.elf secondary-outputs
+
+# Tool invocations
+GPIO.elf: $(OBJS) $(USER_OBJS)
+	@echo 'Building target: $@'
+	@echo 'Invoking: Cross ARM C++ Linker'
+	arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -T "MK64FN1M0xxx12_flash.ld" -Xlinker --gc-sections -L"C:/Users/pkalgaon/Desktop/Workspace/GPIO/Project_Settings/Linker_Files" -Wl,-Map,"GPIO.map" -specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs -o "GPIO.elf" $(OBJS) $(USER_OBJS) $(LIBS)
+	@echo 'Finished building target: $@'
+	@echo ' '
+
+GPIO.siz: GPIO.elf
+	@echo 'Invoking: Cross ARM GNU Print Size'
+	arm-none-eabi-size --format=berkeley "GPIO.elf"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+# Other Targets
+clean:
+	-$(RM) $(SECONDARY_SIZE)$(C++_DEPS)$(OBJS)$(C_DEPS)$(ASM_DEPS)$(CC_DEPS)$(CPP_DEPS)$(CXX_DEPS)$(C_UPPER_DEPS)$(S_UPPER_DEPS) GPIO.elf
+	-@echo ' '
+
+secondary-outputs: $(SECONDARY_SIZE)
+
+.PHONY: all clean dependents
+.SECONDARY:
+
+-include ../makefile.targets
diff --git a/Workspace/GPIO/Debug/objects.mk b/Workspace/GPIO/Debug/objects.mk
new file mode 100644
index 0000000..742c2da
--- /dev/null
+++ b/Workspace/GPIO/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/Workspace/GPIO/Debug/sources.mk b/Workspace/GPIO/Debug/sources.mk
new file mode 100644
index 0000000..80f8a41
--- /dev/null
+++ b/Workspace/GPIO/Debug/sources.mk
@@ -0,0 +1,31 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ELF_SRCS := 
+O_SRCS := 
+CPP_SRCS := 
+C_UPPER_SRCS := 
+C_SRCS := 
+S_UPPER_SRCS := 
+OBJ_SRCS := 
+ASM_SRCS := 
+CXX_SRCS := 
+C++_SRCS := 
+CC_SRCS := 
+SECONDARY_SIZE := 
+C++_DEPS := 
+OBJS := 
+C_DEPS := 
+ASM_DEPS := 
+CC_DEPS := 
+CPP_DEPS := 
+CXX_DEPS := 
+C_UPPER_DEPS := 
+S_UPPER_DEPS := 
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Sources \
+Project_Settings/Startup_Code \
+
diff --git a/Workspace/GPIO/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch b/Workspace/GPIO/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch
new file mode 100644
index 0000000..cae21a4
--- /dev/null
+++ b/Workspace/GPIO/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doConnectToRunning" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f kinetis.cfg"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/GPIO.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="GPIO"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/GPIO"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/GPIO/Project_Settings/Debugger/GPIO_Debug_Segger.launch b/Workspace/GPIO/Project_Settings/Debugger/GPIO_Debug_Segger.launch
new file mode 100644
index 0000000..68923d5
--- /dev/null
+++ b/Workspace/GPIO/Project_Settings/Debugger/GPIO_Debug_Segger.launch
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.jlink.launchConfigurationType">
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="MK64FN1M0xxx12"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="1000"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM J-Link"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/GPIO.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="GPIO"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/GPIO"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/GPIO/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld b/Workspace/GPIO/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
new file mode 100644
index 0000000..506082b
--- /dev/null
+++ b/Workspace/GPIO/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
@@ -0,0 +1,245 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150624
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
+  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0
+  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
+  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+  } > m_data_2
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data_2
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
+}
+
diff --git a/Workspace/GPIO/Project_Settings/Startup_Code/startup.c b/Workspace/GPIO/Project_Settings/Startup_Code/startup.c
new file mode 100644
index 0000000..b89e7fc
--- /dev/null
+++ b/Workspace/GPIO/Project_Settings/Startup_Code/startup.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "startup.h"
+#include "fsl_device_registers.h"
+
+#if (defined(__ICCARM__))
+    #pragma section = ".data"
+    #pragma section = ".data_init"
+    #pragma section = ".bss"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : init_data_bss
+ * Description   : Make necessary initializations for RAM.
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ *
+ * Tool Chians:
+ *   __GNUC__   : GCC
+ *   __CC_ARM   : KEIL
+ *   __ICCARM__ : IAR
+ *
+ *END**************************************************************************/
+void init_data_bss(void)
+{
+    uint32_t n; 
+    
+    /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+    #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base  
+    #define __VECTOR_RAM Image$$VECTOR_RAM$$Base  
+    #define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];  
+    extern uint32_t __VECTOR_RAM[];  
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif
+
+    if (__VECTOR_RAM != __VECTOR_TABLE)
+    {   
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+    else
+    {
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_TABLE;
+    }
+
+#if !defined(__CC_ARM) && !defined(__ICCARM__)
+    
+    /* Declare pointers for various data sections. These pointers
+     * are initialized using values pulled in from the linker file */
+    uint8_t * data_ram, * data_rom, * data_rom_end;
+    uint8_t * bss_start, * bss_end;
+
+    /* Get the addresses for the .data section (initialized data section) */
+#if defined(__GNUC__)
+    extern uint32_t __DATA_ROM[];
+    extern uint32_t __DATA_RAM[];
+    extern char __DATA_END[];
+    data_ram = (uint8_t *)__DATA_RAM;
+    data_rom = (uint8_t *)__DATA_ROM;
+    data_rom_end  = (uint8_t *)__DATA_END;
+    n = data_rom_end - data_rom;
+#endif
+
+    /* Copy initialized data from ROM to RAM */
+    while (n--)
+    {
+        *data_ram++ = *data_rom++;
+    }   
+    
+    /* Get the addresses for the .bss section (zero-initialized data) */
+#if defined(__GNUC__)
+    extern char __START_BSS[];
+    extern char __END_BSS[];
+    bss_start = (uint8_t *)__START_BSS;
+    bss_end = (uint8_t *)__END_BSS;
+#endif
+		
+    /* Clear the zero-initialized data section */
+    n = bss_end - bss_start;
+    while(n--)
+    {
+        *bss_start++ = 0;
+    }
+#endif /* !__CC_ARM && !__ICCARM__*/
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/Workspace/GPIO/Project_Settings/Startup_Code/startup.h b/Workspace/GPIO/Project_Settings/Startup_Code/startup.h
new file mode 100644
index 0000000..17ad55f
--- /dev/null
+++ b/Workspace/GPIO/Project_Settings/Startup_Code/startup.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _STARTUP_H_
+#define _STARTUP_H_
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Make necessary initializations for RAM.
+ *
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ */
+void init_data_bss(void);
+
+#endif /* _STARTUP_H_*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/Workspace/GPIO/Project_Settings/Startup_Code/startup_MK64F12.S b/Workspace/GPIO/Project_Settings/Startup_Code/startup_MK64F12.S
new file mode 100644
index 0000000..aebe2e6
--- /dev/null
+++ b/Workspace/GPIO/Project_Settings/Startup_Code/startup_MK64F12.S
@@ -0,0 +1,457 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK64F12.s                                                           */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK64F12                                                                     */
+/*  @version: 2.8                                                                         */
+/*  @date:    2015-2-19                                                                   */
+/*  @build:   b150225                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_IRQHandler                                 /* DMA Channel 0 Transfer Complete*/
+    .long   DMA1_IRQHandler                                 /* DMA Channel 1 Transfer Complete*/
+    .long   DMA2_IRQHandler                                 /* DMA Channel 2 Transfer Complete*/
+    .long   DMA3_IRQHandler                                 /* DMA Channel 3 Transfer Complete*/
+    .long   DMA4_IRQHandler                                 /* DMA Channel 4 Transfer Complete*/
+    .long   DMA5_IRQHandler                                 /* DMA Channel 5 Transfer Complete*/
+    .long   DMA6_IRQHandler                                 /* DMA Channel 6 Transfer Complete*/
+    .long   DMA7_IRQHandler                                 /* DMA Channel 7 Transfer Complete*/
+    .long   DMA8_IRQHandler                                 /* DMA Channel 8 Transfer Complete*/
+    .long   DMA9_IRQHandler                                 /* DMA Channel 9 Transfer Complete*/
+    .long   DMA10_IRQHandler                                /* DMA Channel 10 Transfer Complete*/
+    .long   DMA11_IRQHandler                                /* DMA Channel 11 Transfer Complete*/
+    .long   DMA12_IRQHandler                                /* DMA Channel 12 Transfer Complete*/
+    .long   DMA13_IRQHandler                                /* DMA Channel 13 Transfer Complete*/
+    .long   DMA14_IRQHandler                                /* DMA Channel 14 Transfer Complete*/
+    .long   DMA15_IRQHandler                                /* DMA Channel 15 Transfer Complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA Error Interrupt*/
+    .long   MCM_IRQHandler                                  /* Normal Interrupt*/
+    .long   FTFE_IRQHandler                                 /* FTFE Command complete interrupt*/
+    .long   Read_Collision_IRQHandler                       /* Read Collision Interrupt*/
+    .long   LVD_LVW_IRQHandler                              /* Low Voltage Detect, Low Voltage Warning*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup Unit*/
+    .long   WDOG_EWM_IRQHandler                             /* WDOG Interrupt*/
+    .long   RNG_IRQHandler                                  /* RNG Interrupt*/
+    .long   I2C0_IRQHandler                                 /* I2C0 interrupt*/
+    .long   I2C1_IRQHandler                                 /* I2C1 interrupt*/
+    .long   SPI0_IRQHandler                                 /* SPI0 Interrupt*/
+    .long   SPI1_IRQHandler                                 /* SPI1 Interrupt*/
+    .long   I2S0_Tx_IRQHandler                              /* I2S0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* I2S0 receive interrupt*/
+    .long   UART0_LON_IRQHandler                            /* UART0 LON interrupt*/
+    .long   UART0_RX_TX_IRQHandler                          /* UART0 Receive/Transmit interrupt*/
+    .long   UART0_ERR_IRQHandler                            /* UART0 Error interrupt*/
+    .long   UART1_RX_TX_IRQHandler                          /* UART1 Receive/Transmit interrupt*/
+    .long   UART1_ERR_IRQHandler                            /* UART1 Error interrupt*/
+    .long   UART2_RX_TX_IRQHandler                          /* UART2 Receive/Transmit interrupt*/
+    .long   UART2_ERR_IRQHandler                            /* UART2 Error interrupt*/
+    .long   UART3_RX_TX_IRQHandler                          /* UART3 Receive/Transmit interrupt*/
+    .long   UART3_ERR_IRQHandler                            /* UART3 Error interrupt*/
+    .long   ADC0_IRQHandler                                 /* ADC0 interrupt*/
+    .long   CMP0_IRQHandler                                 /* CMP0 interrupt*/
+    .long   CMP1_IRQHandler                                 /* CMP1 interrupt*/
+    .long   FTM0_IRQHandler                                 /* FTM0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FTM1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FTM2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* CMT interrupt*/
+    .long   RTC_IRQHandler                                  /* RTC interrupt*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds interrupt*/
+    .long   PIT0_IRQHandler                                 /* PIT timer channel 0 interrupt*/
+    .long   PIT1_IRQHandler                                 /* PIT timer channel 1 interrupt*/
+    .long   PIT2_IRQHandler                                 /* PIT timer channel 2 interrupt*/
+    .long   PIT3_IRQHandler                                 /* PIT timer channel 3 interrupt*/
+    .long   PDB0_IRQHandler                                 /* PDB0 Interrupt*/
+    .long   USB0_IRQHandler                                 /* USB0 interrupt*/
+    .long   USBDCD_IRQHandler                               /* USBDCD Interrupt*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt 71*/
+    .long   DAC0_IRQHandler                                 /* DAC0 interrupt*/
+    .long   MCG_IRQHandler                                  /* MCG Interrupt*/
+    .long   LPTMR0_IRQHandler                               /* LPTimer interrupt*/
+    .long   PORTA_IRQHandler                                /* Port A interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* SPI2 Interrupt*/
+    .long   UART4_RX_TX_IRQHandler                          /* UART4 Receive/Transmit interrupt*/
+    .long   UART4_ERR_IRQHandler                            /* UART4 Error interrupt*/
+    .long   UART5_RX_TX_IRQHandler                          /* UART5 Receive/Transmit interrupt*/
+    .long   UART5_ERR_IRQHandler                            /* UART5 Error interrupt*/
+    .long   CMP2_IRQHandler                                 /* CMP2 interrupt*/
+    .long   FTM3_IRQHandler                                 /* FTM3 fault, overflow and channels interrupt*/
+    .long   DAC1_IRQHandler                                 /* DAC1 interrupt*/
+    .long   ADC1_IRQHandler                                 /* ADC1 interrupt*/
+    .long   I2C2_IRQHandler                                 /* I2C2 interrupt*/
+    .long   CAN0_ORed_Message_buffer_IRQHandler             /* CAN0 OR'd message buffers interrupt*/
+    .long   CAN0_Bus_Off_IRQHandler                         /* CAN0 bus off interrupt*/
+    .long   CAN0_Error_IRQHandler                           /* CAN0 error interrupt*/
+    .long   CAN0_Tx_Warning_IRQHandler                      /* CAN0 Tx warning interrupt*/
+    .long   CAN0_Rx_Warning_IRQHandler                      /* CAN0 Rx warning interrupt*/
+    .long   CAN0_Wake_Up_IRQHandler                         /* CAN0 wake up interrupt*/
+    .long   SDHC_IRQHandler                                 /* SDHC interrupt*/
+    .long   ENET_1588_Timer_IRQHandler                      /* Ethernet MAC IEEE 1588 Timer Interrupt*/
+    .long   ENET_Transmit_IRQHandler                        /* Ethernet MAC Transmit Interrupt*/
+    .long   ENET_Receive_IRQHandler                         /* Ethernet MAC Receive Interrupt*/
+    .long   ENET_Error_IRQHandler                           /* Ethernet MAC Error and miscelaneous Interrupt*/
+    .long   DefaultISR                                      /* 102*/
+    .long   DefaultISR                                      /* 103*/
+    .long   DefaultISR                                      /* 104*/
+    .long   DefaultISR                                      /* 105*/
+    .long   DefaultISR                                      /* 106*/
+    .long   DefaultISR                                      /* 107*/
+    .long   DefaultISR                                      /* 108*/
+    .long   DefaultISR                                      /* 109*/
+    .long   DefaultISR                                      /* 110*/
+    .long   DefaultISR                                      /* 111*/
+    .long   DefaultISR                                      /* 112*/
+    .long   DefaultISR                                      /* 113*/
+    .long   DefaultISR                                      /* 114*/
+    .long   DefaultISR                                      /* 115*/
+    .long   DefaultISR                                      /* 116*/
+    .long   DefaultISR                                      /* 117*/
+    .long   DefaultISR                                      /* 118*/
+    .long   DefaultISR                                      /* 119*/
+    .long   DefaultISR                                      /* 120*/
+    .long   DefaultISR                                      /* 121*/
+    .long   DefaultISR                                      /* 122*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+    .long   DefaultISR                                      /* 240*/
+    .long   DefaultISR                                      /* 241*/
+    .long   DefaultISR                                      /* 242*/
+    .long   DefaultISR                                      /* 243*/
+    .long   DefaultISR                                      /* 244*/
+    .long   DefaultISR                                      /* 245*/
+    .long   DefaultISR                                      /* 246*/
+    .long   DefaultISR                                      /* 247*/
+    .long   DefaultISR                                      /* 248*/
+    .long   DefaultISR                                      /* 249*/
+    .long   DefaultISR                                      /* 250*/
+    .long   DefaultISR                                      /* 251*/
+    .long   DefaultISR                                      /* 252*/
+    .long   DefaultISR                                      /* 253*/
+    .long   DefaultISR                                      /* 254*/
+    .long   0xFFFFFFFF                                      /*  Reserved for user TRIM value*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_IRQHandler
+    def_irq_handler    DMA1_IRQHandler
+    def_irq_handler    DMA2_IRQHandler
+    def_irq_handler    DMA3_IRQHandler
+    def_irq_handler    DMA4_IRQHandler
+    def_irq_handler    DMA5_IRQHandler
+    def_irq_handler    DMA6_IRQHandler
+    def_irq_handler    DMA7_IRQHandler
+    def_irq_handler    DMA8_IRQHandler
+    def_irq_handler    DMA9_IRQHandler
+    def_irq_handler    DMA10_IRQHandler
+    def_irq_handler    DMA11_IRQHandler
+    def_irq_handler    DMA12_IRQHandler
+    def_irq_handler    DMA13_IRQHandler
+    def_irq_handler    DMA14_IRQHandler
+    def_irq_handler    DMA15_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFE_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    RNG_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    UART0_LON_IRQHandler
+    def_irq_handler    UART0_RX_TX_IRQHandler
+    def_irq_handler    UART0_ERR_IRQHandler
+    def_irq_handler    UART1_RX_TX_IRQHandler
+    def_irq_handler    UART1_ERR_IRQHandler
+    def_irq_handler    UART2_RX_TX_IRQHandler
+    def_irq_handler    UART2_ERR_IRQHandler
+    def_irq_handler    UART3_RX_TX_IRQHandler
+    def_irq_handler    UART3_ERR_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    PIT1_IRQHandler
+    def_irq_handler    PIT2_IRQHandler
+    def_irq_handler    PIT3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    UART4_RX_TX_IRQHandler
+    def_irq_handler    UART4_ERR_IRQHandler
+    def_irq_handler    UART5_RX_TX_IRQHandler
+    def_irq_handler    UART5_ERR_IRQHandler
+    def_irq_handler    CMP2_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    DAC1_IRQHandler
+    def_irq_handler    ADC1_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    CAN0_ORed_Message_buffer_IRQHandler
+    def_irq_handler    CAN0_Bus_Off_IRQHandler
+    def_irq_handler    CAN0_Error_IRQHandler
+    def_irq_handler    CAN0_Tx_Warning_IRQHandler
+    def_irq_handler    CAN0_Rx_Warning_IRQHandler
+    def_irq_handler    CAN0_Wake_Up_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    ENET_1588_Timer_IRQHandler
+    def_irq_handler    ENET_Transmit_IRQHandler
+    def_irq_handler    ENET_Receive_IRQHandler
+    def_irq_handler    ENET_Error_IRQHandler
+
+    .end
diff --git a/Workspace/GPIO/Project_Settings/Startup_Code/system_MK64F12.c b/Workspace/GPIO/Project_Settings/Startup_Code/system_MK64F12.c
new file mode 100644
index 0000000..e3c1376
--- /dev/null
+++ b/Workspace/GPIO/Project_Settings/Startup_Code/system_MK64F12.c
@@ -0,0 +1,414 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief Device specific configuration file for MK64F12 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+#if (DISABLE_WDOG)
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+  /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+  WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+                 WDOG_STCTRLH_WAITEN_MASK |
+                 WDOG_STCTRLH_STOPEN_MASK |
+                 WDOG_STCTRLH_ALLOWUPDATE_MASK |
+                 WDOG_STCTRLH_CLKSRC_MASK |
+                 0x0100U;
+#endif /* (DISABLE_WDOG) */
+#ifdef CLOCK_SETUP
+  if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
+  {
+    if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
+    {
+       PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO:  Only has an effect if recovering from VLLSx.*/
+    }
+  } else {
+#ifdef SYSTEM_RTC_CR_VALUE
+    SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
+    if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
+      RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
+      RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
+      RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
+    }
+#endif
+  }
+
+  /* Power mode protection initialization */
+#ifdef SYSTEM_SMC_PMPROT_VALUE
+  SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
+#endif
+
+  /* System clock initialization */
+  /* Internal reference clock trim initialization */
+#if defined(SLOW_TRIM_ADDRESS)
+  if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) {                              /* Skip if non-volatile flash memory is erased */
+    MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
+  #endif /* defined(SLOW_TRIM_ADDRESS) */
+  #if defined(SLOW_FINE_TRIM_ADDRESS)
+    MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
+  #endif
+  #if defined(FAST_TRIM_ADDRESS)
+    MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
+  #endif
+  #if defined(FAST_FINE_TRIM_ADDRESS)
+    MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
+  #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
+#if defined(SLOW_TRIM_ADDRESS)
+  }
+  #endif /* defined(SLOW_TRIM_ADDRESS) */
+
+  /* Set system prescalers and clock sources */
+  SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
+  SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
+  SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+  /* Set MCG and OSC */
+#if  ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+  /* PORTA_PCR19: ISF=0,MUX=0 */
+  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
+  MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+  /* Check that the source of the FLL reference clock is the requested one. */
+  if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+    }
+  } else {
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+    }
+  }
+  MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+  MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+  OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
+  #if (MCG_MODE == MCG_MODE_BLPI)
+  /* BLPI specific */
+  MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
+  #endif
+
+#else /* MCG_MODE */
+  /* Set MCG and OSC */
+#if  (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+  /* PORTA_PCR19: ISF=0,MUX=0 */
+  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
+  MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+  OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
+  #if (MCG_MODE == MCG_MODE_PEE)
+  MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
+  #else
+  MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+  #endif
+  if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
+    while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
+    }
+  }
+  /* Check that the source of the FLL reference clock is the requested one. */
+  if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+    }
+  } else {
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+    }
+  }
+  MCG->C4 = ((SYSTEM_MCG_C4_VALUE)  & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+#endif /* MCG_MODE */
+
+  /* Common for all MCG modes */
+
+  /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
+  MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
+  MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+  if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
+    MCG->C5 |= MCG_C5_PLLCLKEN0_MASK;  /* PLL clock enable in mode other than PEE or PBE */
+  }
+  /* BLPE, PEE and PBE MCG mode specific */
+
+#if (MCG_MODE == MCG_MODE_BLPE)
+  MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
+#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
+  MCG->C6 |= (MCG_C6_PLLS_MASK);       /* Set C6 (PLL select, VCO divider etc.) */
+  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
+  }
+  #if (MCG_MODE == MCG_MODE_PEE)
+  MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
+  #endif
+#endif
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
+  }
+  /* Use LPTMR to wait for 1ms dor FLL clock stabilization */
+  SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;   /* Alow software control of LPMTR */
+  LPTMR0->CMR = LPTMR_CMR_COMPARE(0);  /* Default 1 LPO tick */
+  LPTMR0->CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00));
+  LPTMR0->PSR = (LPTMR_PSR_PCS(0x01) | LPTMR_PSR_PBYP_MASK); /* Clock source: LPO, Prescaler bypass enable */
+  LPTMR0->CSR = LPTMR_CSR_TEN_MASK;    /* LPMTR enable */
+  while((LPTMR0_CSR & LPTMR_CSR_TCF_MASK) == 0u) {
+  }
+  LPTMR0_CSR = 0x00;                   /* Disable LPTMR */
+  SIM_SCGC5 &= (uint32_t)~(uint32_t)SIM_SCGC5_LPTMR_MASK;
+#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
+  }
+#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+  }
+#elif (MCG_MODE == MCG_MODE_PEE)
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
+  }
+#endif
+#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
+  SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
+  while(SMC->PMSTAT != 0x04U) {        /* Wait until the system is in VLPR mode */
+  }
+#endif
+
+#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
+  SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
+#endif
+
+  /* PLL loss of lock interrupt request initialization */
+  if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
+    NVIC_EnableIRQ(MCG_IRQn);          /* Enable PLL loss of lock interrupt request */
+  }
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+  uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
+  uint16_t Divider;
+
+  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
+    /* Output of FLL or PLL is selected */
+    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
+      /* FLL is selected */
+      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+        case 0x00U:
+          MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+          break;
+        case 0x01U:
+          MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+          break;
+        case 0x02U:
+        default:
+          MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+          break;
+        }
+        if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
+          switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
+          case 0x38U:
+            Divider = 1536U;
+            break;
+          case 0x30U:
+            Divider = 1280U;
+            break;
+          default:
+            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+            break;
+          }
+        } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+          Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+        }
+        MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+        MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+      /* Select correct multiplier to calculate the MCG output clock  */
+      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+        case 0x00U:
+          MCGOUTClock *= 640U;
+          break;
+        case 0x20U:
+          MCGOUTClock *= 1280U;
+          break;
+        case 0x40U:
+          MCGOUTClock *= 1920U;
+          break;
+        case 0x60U:
+          MCGOUTClock *= 2560U;
+          break;
+        case 0x80U:
+          MCGOUTClock *= 732U;
+          break;
+        case 0xA0U:
+          MCGOUTClock *= 1464U;
+          break;
+        case 0xC0U:
+          MCGOUTClock *= 2197U;
+          break;
+        case 0xE0U:
+          MCGOUTClock *= 2929U;
+          break;
+        default:
+          break;
+      }
+    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+      /* PLL is selected */
+      Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
+      MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+      Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
+      MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
+    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
+    /* Internal reference clock is selected */
+    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+      Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+      MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
+    /* External reference clock is selected */
+    switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+    case 0x00U:
+      MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
+      break;
+    case 0x01U:
+      MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+      break;
+    case 0x02U:
+    default:
+      MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+      break;
+    }
+  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    /* Reserved value */
+    return;
+  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+  SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/Workspace/GPIO/Project_Settings/Startup_Code/system_MK64F12.h b/Workspace/GPIO/Project_Settings/Startup_Code/system_MK64F12.h
new file mode 100644
index 0000000..d6a5f05
--- /dev/null
+++ b/Workspace/GPIO/Project_Settings/Startup_Code/system_MK64F12.h
@@ -0,0 +1,352 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief Device specific configuration file for MK64F12 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK64F12_H_
+#define SYSTEM_MK64F12_H_                        /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG                 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI                   0U
+#define MCG_MODE_FBI                   1U
+#define MCG_MODE_BLPI                  2U
+#define MCG_MODE_FEE                   3U
+#define MCG_MODE_FBE                   4U
+#define MCG_MODE_BLPE                  5U
+#define MCG_MODE_PBE                   6U
+#define MCG_MODE_PEE                   7U
+
+/* Predefined clock setups
+   0 ... Default  part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock = 20.97152MHz
+         Bus clock  = 20.97152MHz
+   1 ... Maximum achievable clock frequency configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+   2 ... Chip internaly clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   3 ... Chip externally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: RTC oscillator reference clock
+         Core clock = 0.032768MHz
+         Bus clock  = 0.032768MHz
+   4 ... USB clock setup
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+ */
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ                50000000u           /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_XTAL32k_CLK_HZ             32768u              /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+#define CPU_INT_SLOW_CLK_HZ            32768u              /* Value of the slow internal oscillator clock frequency in Hz  */
+#define CPU_INT_FAST_CLK_HZ            4000000u            /* Value of the fast internal oscillator clock frequency in Hz  */
+#define CPU_INT_IRC_CLK_HZ             48000000u           /* Value of the 48M internal oscillator clock frequency in Hz  */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE            0x0300U             /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE        0x2AU               /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */                             /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */                        /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */                             /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */                        /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_FEI /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x06U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00110000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00U               /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 1)
+  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 2)
+  #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_BLPI /* Clock generator mode */
+  /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x46U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00040000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 3)
+  #define DEFAULT_SYSTEM_CLOCK         32768u              /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_BLPE /* Clock generator mode */
+  /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x82U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x02U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=1 */
+  #define SYSTEM_MCG_C7_VALUE          0x01U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00U               /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 4)
+  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
+  #define SYSTEM_SIM_CLKDIV2_VALUE     0x09U               /* SIM_CLKDIV2 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
+#endif
+#else
+  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* #if !defined(SYSTEM_MK64F12_H_) */
diff --git a/Workspace/GPIO/SDK/platform/CMSIS/Include/arm_common_tables.h b/Workspace/GPIO/SDK/platform/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000..039cc3d
--- /dev/null
+++ b/Workspace/GPIO/SDK/platform/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/Workspace/GPIO/SDK/platform/CMSIS/Include/arm_const_structs.h b/Workspace/GPIO/SDK/platform/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 0000000..726d06e
--- /dev/null
+++ b/Workspace/GPIO/SDK/platform/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/Workspace/GPIO/SDK/platform/CMSIS/Include/arm_math.h b/Workspace/GPIO/SDK/platform/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000..e4b2f62
--- /dev/null
+++ b/Workspace/GPIO/SDK/platform/CMSIS/Include/arm_math.h
@@ -0,0 +1,7556 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_math.h
+*
+* Description:	Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   * 
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   * 
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+  #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31	   0x400000
+#define TABLE_SPACING_Q15	   0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+#elif defined __GNUC__
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__			/* Cosmic */
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+#elif defined __TASKING__
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+//#define __CLZ __clz
+//#endif
+
+//note: function can be removed when all toolchain support __CLZ for Cortex-M0
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+      ((q15_t) x * (q15_t) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		 *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15( 
+    const arm_cfft_instance_q15 * S, 
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31( 
+    const arm_cfft_instance_q31 * S, 
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+  
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in >= 0.0f)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+   
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("push")         \
+         _Pragma ("O1")
+    #else
+      #define LOW_OPTIMIZATION_ENTER 
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_EXIT \
+         _Pragma ("pop")
+    #else
+      #define LOW_OPTIMIZATION_EXIT  
+    #endif
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)		// Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)		// TASKING
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/Workspace/GPIO/SDK/platform/CMSIS/Include/core_cm4.h b/Workspace/GPIO/SDK/platform/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000..9749c27
--- /dev/null
+++ b/Workspace/GPIO/SDK/platform/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1858 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)IRQn < 0) {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)IRQn < 0) {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                             /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Workspace/GPIO/SDK/platform/CMSIS/Include/core_cmFunc.h b/Workspace/GPIO/SDK/platform/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000..b6ad0a4
--- /dev/null
+++ b/Workspace/GPIO/SDK/platform/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,664 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+    or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+	or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/Workspace/GPIO/SDK/platform/CMSIS/Include/core_cmInstr.h b/Workspace/GPIO/SDK/platform/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000..fca425c
--- /dev/null
+++ b/Workspace/GPIO/SDK/platform/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,916 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+  return(result);
+}
+#endif
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+#endif
+  return(result);
+}
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/Workspace/GPIO/SDK/platform/CMSIS/Include/core_cmSimd.h b/Workspace/GPIO/SDK/platform/CMSIS/Include/core_cmSimd.h
new file mode 100644
index 0000000..7b8e37f
--- /dev/null
+++ b/Workspace/GPIO/SDK/platform/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/Workspace/GPIO/SDK/platform/devices/MK64F12/include/MK64F12.h b/Workspace/GPIO/SDK/platform/devices/MK64F12/include/MK64F12.h
new file mode 100644
index 0000000..3114ad7
--- /dev/null
+++ b/Workspace/GPIO/SDK/platform/devices/MK64F12/include/MK64F12.h
@@ -0,0 +1,18767 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MK64F12
+**
+**     Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12.h
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief CMSIS Peripheral Access Layer for MK64F12
+ *
+ * CMSIS Peripheral Access Layer for MK64F12
+ */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCU activation
+   ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MK64F12_H_)  /* Check if memory map has not been already included */
+#define MK64F12_H_
+#define MCU_MK64F12
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+  #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0008u
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ *        bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ *        0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return  Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 102                /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_IRQn                    = 0,                /**< DMA Channel 0 Transfer Complete */
+  DMA1_IRQn                    = 1,                /**< DMA Channel 1 Transfer Complete */
+  DMA2_IRQn                    = 2,                /**< DMA Channel 2 Transfer Complete */
+  DMA3_IRQn                    = 3,                /**< DMA Channel 3 Transfer Complete */
+  DMA4_IRQn                    = 4,                /**< DMA Channel 4 Transfer Complete */
+  DMA5_IRQn                    = 5,                /**< DMA Channel 5 Transfer Complete */
+  DMA6_IRQn                    = 6,                /**< DMA Channel 6 Transfer Complete */
+  DMA7_IRQn                    = 7,                /**< DMA Channel 7 Transfer Complete */
+  DMA8_IRQn                    = 8,                /**< DMA Channel 8 Transfer Complete */
+  DMA9_IRQn                    = 9,                /**< DMA Channel 9 Transfer Complete */
+  DMA10_IRQn                   = 10,               /**< DMA Channel 10 Transfer Complete */
+  DMA11_IRQn                   = 11,               /**< DMA Channel 11 Transfer Complete */
+  DMA12_IRQn                   = 12,               /**< DMA Channel 12 Transfer Complete */
+  DMA13_IRQn                   = 13,               /**< DMA Channel 13 Transfer Complete */
+  DMA14_IRQn                   = 14,               /**< DMA Channel 14 Transfer Complete */
+  DMA15_IRQn                   = 15,               /**< DMA Channel 15 Transfer Complete */
+  DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
+  MCM_IRQn                     = 17,               /**< Normal Interrupt */
+  FTFE_IRQn                    = 18,               /**< FTFE Command complete interrupt */
+  Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
+  LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
+  LLWU_IRQn                    = 21,               /**< Low Leakage Wakeup Unit */
+  WDOG_EWM_IRQn                = 22,               /**< WDOG Interrupt */
+  RNG_IRQn                     = 23,               /**< RNG Interrupt */
+  I2C0_IRQn                    = 24,               /**< I2C0 interrupt */
+  I2C1_IRQn                    = 25,               /**< I2C1 interrupt */
+  SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
+  SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
+  I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
+  I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
+  UART0_LON_IRQn               = 30,               /**< UART0 LON interrupt */
+  UART0_RX_TX_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
+  UART0_ERR_IRQn               = 32,               /**< UART0 Error interrupt */
+  UART1_RX_TX_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
+  UART1_ERR_IRQn               = 34,               /**< UART1 Error interrupt */
+  UART2_RX_TX_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
+  UART2_ERR_IRQn               = 36,               /**< UART2 Error interrupt */
+  UART3_RX_TX_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
+  UART3_ERR_IRQn               = 38,               /**< UART3 Error interrupt */
+  ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
+  CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
+  FTM0_IRQn                    = 42,               /**< FTM0 fault, overflow and channels interrupt */
+  FTM1_IRQn                    = 43,               /**< FTM1 fault, overflow and channels interrupt */
+  FTM2_IRQn                    = 44,               /**< FTM2 fault, overflow and channels interrupt */
+  CMT_IRQn                     = 45,               /**< CMT interrupt */
+  RTC_IRQn                     = 46,               /**< RTC interrupt */
+  RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
+  PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
+  PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
+  PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
+  PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
+  PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
+  USB0_IRQn                    = 53,               /**< USB0 interrupt */
+  USBDCD_IRQn                  = 54,               /**< USBDCD Interrupt */
+  Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
+  DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
+  MCG_IRQn                     = 57,               /**< MCG Interrupt */
+  LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
+  PORTA_IRQn                   = 59,               /**< Port A interrupt */
+  PORTB_IRQn                   = 60,               /**< Port B interrupt */
+  PORTC_IRQn                   = 61,               /**< Port C interrupt */
+  PORTD_IRQn                   = 62,               /**< Port D interrupt */
+  PORTE_IRQn                   = 63,               /**< Port E interrupt */
+  SWI_IRQn                     = 64,               /**< Software interrupt */
+  SPI2_IRQn                    = 65,               /**< SPI2 Interrupt */
+  UART4_RX_TX_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
+  UART4_ERR_IRQn               = 67,               /**< UART4 Error interrupt */
+  UART5_RX_TX_IRQn             = 68,               /**< UART5 Receive/Transmit interrupt */
+  UART5_ERR_IRQn               = 69,               /**< UART5 Error interrupt */
+  CMP2_IRQn                    = 70,               /**< CMP2 interrupt */
+  FTM3_IRQn                    = 71,               /**< FTM3 fault, overflow and channels interrupt */
+  DAC1_IRQn                    = 72,               /**< DAC1 interrupt */
+  ADC1_IRQn                    = 73,               /**< ADC1 interrupt */
+  I2C2_IRQn                    = 74,               /**< I2C2 interrupt */
+  CAN0_ORed_Message_buffer_IRQn = 75,              /**< CAN0 OR'd message buffers interrupt */
+  CAN0_Bus_Off_IRQn            = 76,               /**< CAN0 bus off interrupt */
+  CAN0_Error_IRQn              = 77,               /**< CAN0 error interrupt */
+  CAN0_Tx_Warning_IRQn         = 78,               /**< CAN0 Tx warning interrupt */
+  CAN0_Rx_Warning_IRQn         = 79,               /**< CAN0 Rx warning interrupt */
+  CAN0_Wake_Up_IRQn            = 80,               /**< CAN0 wake up interrupt */
+  SDHC_IRQn                    = 81,               /**< SDHC interrupt */
+  ENET_1588_Timer_IRQn         = 82,               /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+  ENET_Transmit_IRQn           = 83,               /**< Ethernet MAC Transmit Interrupt */
+  ENET_Receive_IRQn            = 84,               /**< Ethernet MAC Receive Interrupt */
+  ENET_Error_IRQn              = 85                /**< Ethernet MAC Error and miscelaneous Interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_MK64F12.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index)                  ((base)->SC1[index])
+#define ADC_SC1_COUNT                            2
+#define ADC_CFG1_REG(base)                       ((base)->CFG1)
+#define ADC_CFG2_REG(base)                       ((base)->CFG2)
+#define ADC_R_REG(base,index)                    ((base)->R[index])
+#define ADC_R_COUNT                              2
+#define ADC_CV1_REG(base)                        ((base)->CV1)
+#define ADC_CV2_REG(base)                        ((base)->CV2)
+#define ADC_SC2_REG(base)                        ((base)->SC2)
+#define ADC_SC3_REG(base)                        ((base)->SC3)
+#define ADC_OFS_REG(base)                        ((base)->OFS)
+#define ADC_PG_REG(base)                         ((base)->PG)
+#define ADC_MG_REG(base)                         ((base)->MG)
+#define ADC_CLPD_REG(base)                       ((base)->CLPD)
+#define ADC_CLPS_REG(base)                       ((base)->CLPS)
+#define ADC_CLP4_REG(base)                       ((base)->CLP4)
+#define ADC_CLP3_REG(base)                       ((base)->CLP3)
+#define ADC_CLP2_REG(base)                       ((base)->CLP2)
+#define ADC_CLP1_REG(base)                       ((base)->CLP1)
+#define ADC_CLP0_REG(base)                       ((base)->CLP0)
+#define ADC_CLMD_REG(base)                       ((base)->CLMD)
+#define ADC_CLMS_REG(base)                       ((base)->CLMS)
+#define ADC_CLM4_REG(base)                       ((base)->CLM4)
+#define ADC_CLM3_REG(base)                       ((base)->CLM3)
+#define ADC_CLM2_REG(base)                       ((base)->CLM2)
+#define ADC_CLM1_REG(base)                       ((base)->CLM1)
+#define ADC_CLM0_REG(base)                       ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK                        0x1Fu
+#define ADC_SC1_ADCH_SHIFT                       0
+#define ADC_SC1_ADCH_WIDTH                       5
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        0x20u
+#define ADC_SC1_DIFF_SHIFT                       5
+#define ADC_SC1_DIFF_WIDTH                       1
+#define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK                        0x40u
+#define ADC_SC1_AIEN_SHIFT                       6
+#define ADC_SC1_AIEN_WIDTH                       1
+#define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK                        0x80u
+#define ADC_SC1_COCO_SHIFT                       7
+#define ADC_SC1_COCO_WIDTH                       1
+#define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK                     0x3u
+#define ADC_CFG1_ADICLK_SHIFT                    0
+#define ADC_CFG1_ADICLK_WIDTH                    2
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       0xCu
+#define ADC_CFG1_MODE_SHIFT                      2
+#define ADC_CFG1_MODE_WIDTH                      2
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     0x10u
+#define ADC_CFG1_ADLSMP_SHIFT                    4
+#define ADC_CFG1_ADLSMP_WIDTH                    1
+#define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK                       0x60u
+#define ADC_CFG1_ADIV_SHIFT                      5
+#define ADC_CFG1_ADIV_WIDTH                      2
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      0x80u
+#define ADC_CFG1_ADLPC_SHIFT                     7
+#define ADC_CFG1_ADLPC_WIDTH                     1
+#define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK                     0x3u
+#define ADC_CFG2_ADLSTS_SHIFT                    0
+#define ADC_CFG2_ADLSTS_WIDTH                    2
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      0x4u
+#define ADC_CFG2_ADHSC_SHIFT                     2
+#define ADC_CFG2_ADHSC_WIDTH                     1
+#define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK                    0x8u
+#define ADC_CFG2_ADACKEN_SHIFT                   3
+#define ADC_CFG2_ADACKEN_WIDTH                   1
+#define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK                     0x10u
+#define ADC_CFG2_MUXSEL_SHIFT                    4
+#define ADC_CFG2_MUXSEL_WIDTH                    1
+#define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
+/* R Bit Fields */
+#define ADC_R_D_MASK                             0xFFFFu
+#define ADC_R_D_SHIFT                            0
+#define ADC_R_D_WIDTH                            16
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK                          0xFFFFu
+#define ADC_CV1_CV_SHIFT                         0
+#define ADC_CV1_CV_WIDTH                         16
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK                          0xFFFFu
+#define ADC_CV2_CV_SHIFT                         0
+#define ADC_CV2_CV_WIDTH                         16
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK                      0x3u
+#define ADC_SC2_REFSEL_SHIFT                     0
+#define ADC_SC2_REFSEL_WIDTH                     2
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       0x4u
+#define ADC_SC2_DMAEN_SHIFT                      2
+#define ADC_SC2_DMAEN_WIDTH                      1
+#define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK                       0x8u
+#define ADC_SC2_ACREN_SHIFT                      3
+#define ADC_SC2_ACREN_WIDTH                      1
+#define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK                       0x10u
+#define ADC_SC2_ACFGT_SHIFT                      4
+#define ADC_SC2_ACFGT_WIDTH                      1
+#define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK                        0x20u
+#define ADC_SC2_ACFE_SHIFT                       5
+#define ADC_SC2_ACFE_WIDTH                       1
+#define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK                       0x40u
+#define ADC_SC2_ADTRG_SHIFT                      6
+#define ADC_SC2_ADTRG_WIDTH                      1
+#define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK                       0x80u
+#define ADC_SC2_ADACT_SHIFT                      7
+#define ADC_SC2_ADACT_WIDTH                      1
+#define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK                        0x3u
+#define ADC_SC3_AVGS_SHIFT                       0
+#define ADC_SC3_AVGS_WIDTH                       2
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        0x4u
+#define ADC_SC3_AVGE_SHIFT                       2
+#define ADC_SC3_AVGE_WIDTH                       1
+#define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK                        0x8u
+#define ADC_SC3_ADCO_SHIFT                       3
+#define ADC_SC3_ADCO_WIDTH                       1
+#define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK                        0x40u
+#define ADC_SC3_CALF_SHIFT                       6
+#define ADC_SC3_CALF_WIDTH                       1
+#define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK                         0x80u
+#define ADC_SC3_CAL_SHIFT                        7
+#define ADC_SC3_CAL_WIDTH                        1
+#define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK                         0xFFFFu
+#define ADC_OFS_OFS_SHIFT                        0
+#define ADC_OFS_OFS_WIDTH                        16
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK                           0xFFFFu
+#define ADC_PG_PG_SHIFT                          0
+#define ADC_PG_PG_WIDTH                          16
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK                           0xFFFFu
+#define ADC_MG_MG_SHIFT                          0
+#define ADC_MG_MG_WIDTH                          16
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK                       0x3Fu
+#define ADC_CLPD_CLPD_SHIFT                      0
+#define ADC_CLPD_CLPD_WIDTH                      6
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK                       0x3Fu
+#define ADC_CLPS_CLPS_SHIFT                      0
+#define ADC_CLPS_CLPS_WIDTH                      6
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK                       0x3FFu
+#define ADC_CLP4_CLP4_SHIFT                      0
+#define ADC_CLP4_CLP4_WIDTH                      10
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK                       0x1FFu
+#define ADC_CLP3_CLP3_SHIFT                      0
+#define ADC_CLP3_CLP3_WIDTH                      9
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK                       0xFFu
+#define ADC_CLP2_CLP2_SHIFT                      0
+#define ADC_CLP2_CLP2_WIDTH                      8
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK                       0x7Fu
+#define ADC_CLP1_CLP1_SHIFT                      0
+#define ADC_CLP1_CLP1_WIDTH                      7
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK                       0x3Fu
+#define ADC_CLP0_CLP0_SHIFT                      0
+#define ADC_CLP0_CLP0_WIDTH                      6
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK                       0x3Fu
+#define ADC_CLMD_CLMD_SHIFT                      0
+#define ADC_CLMD_CLMD_WIDTH                      6
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK                       0x3Fu
+#define ADC_CLMS_CLMS_SHIFT                      0
+#define ADC_CLMS_CLMS_WIDTH                      6
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK                       0x3FFu
+#define ADC_CLM4_CLM4_SHIFT                      0
+#define ADC_CLM4_CLM4_WIDTH                      10
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK                       0x1FFu
+#define ADC_CLM3_CLM3_SHIFT                      0
+#define ADC_CLM3_CLM3_WIDTH                      9
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK                       0xFFu
+#define ADC_CLM2_CLM2_SHIFT                      0
+#define ADC_CLM2_CLM2_WIDTH                      8
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK                       0x7Fu
+#define ADC_CLM1_CLM1_SHIFT                      0
+#define ADC_CLM1_CLM1_WIDTH                      7
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK                       0x3Fu
+#define ADC_CLM0_CLM0_SHIFT                      0
+#define ADC_CLM0_CLM0_WIDTH                      6
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR                            (ADC0)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_Type *)ADC1_BASE)
+#define ADC1_BASE_PTR                            (ADC1)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A                                ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B                                ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1                                ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2                                ADC_CFG2_REG(ADC0)
+#define ADC0_RA                                  ADC_R_REG(ADC0,0)
+#define ADC0_RB                                  ADC_R_REG(ADC0,1)
+#define ADC0_CV1                                 ADC_CV1_REG(ADC0)
+#define ADC0_CV2                                 ADC_CV2_REG(ADC0)
+#define ADC0_SC2                                 ADC_SC2_REG(ADC0)
+#define ADC0_SC3                                 ADC_SC3_REG(ADC0)
+#define ADC0_OFS                                 ADC_OFS_REG(ADC0)
+#define ADC0_PG                                  ADC_PG_REG(ADC0)
+#define ADC0_MG                                  ADC_MG_REG(ADC0)
+#define ADC0_CLPD                                ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS                                ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4                                ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3                                ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2                                ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1                                ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0                                ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD                                ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS                                ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4                                ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3                                ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2                                ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1                                ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0                                ADC_CLM0_REG(ADC0)
+/* ADC1 */
+#define ADC1_SC1A                                ADC_SC1_REG(ADC1,0)
+#define ADC1_SC1B                                ADC_SC1_REG(ADC1,1)
+#define ADC1_CFG1                                ADC_CFG1_REG(ADC1)
+#define ADC1_CFG2                                ADC_CFG2_REG(ADC1)
+#define ADC1_RA                                  ADC_R_REG(ADC1,0)
+#define ADC1_RB                                  ADC_R_REG(ADC1,1)
+#define ADC1_CV1                                 ADC_CV1_REG(ADC1)
+#define ADC1_CV2                                 ADC_CV2_REG(ADC1)
+#define ADC1_SC2                                 ADC_SC2_REG(ADC1)
+#define ADC1_SC3                                 ADC_SC3_REG(ADC1)
+#define ADC1_OFS                                 ADC_OFS_REG(ADC1)
+#define ADC1_PG                                  ADC_PG_REG(ADC1)
+#define ADC1_MG                                  ADC_MG_REG(ADC1)
+#define ADC1_CLPD                                ADC_CLPD_REG(ADC1)
+#define ADC1_CLPS                                ADC_CLPS_REG(ADC1)
+#define ADC1_CLP4                                ADC_CLP4_REG(ADC1)
+#define ADC1_CLP3                                ADC_CLP3_REG(ADC1)
+#define ADC1_CLP2                                ADC_CLP2_REG(ADC1)
+#define ADC1_CLP1                                ADC_CLP1_REG(ADC1)
+#define ADC1_CLP0                                ADC_CLP0_REG(ADC1)
+#define ADC1_CLMD                                ADC_CLMD_REG(ADC1)
+#define ADC1_CLMS                                ADC_CLMS_REG(ADC1)
+#define ADC1_CLM4                                ADC_CLM4_REG(ADC1)
+#define ADC1_CLM3                                ADC_CLM3_REG(ADC1)
+#define ADC1_CLM2                                ADC_CLM2_REG(ADC1)
+#define ADC1_CLM1                                ADC_CLM1_REG(ADC1)
+#define ADC1_CLM0                                ADC_CLM0_REG(ADC1)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index)                          ADC_SC1_REG(ADC0,index)
+#define ADC1_SC1(index)                          ADC_SC1_REG(ADC1,index)
+#define ADC0_R(index)                            ADC_R_REG(ADC0,index)
+#define ADC1_R(index)                            ADC_R_REG(ADC1,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPRA;                              /**< Master Privilege Register A, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PACRA;                             /**< Peripheral Access Control Register, offset: 0x20 */
+  __IO uint32_t PACRB;                             /**< Peripheral Access Control Register, offset: 0x24 */
+  __IO uint32_t PACRC;                             /**< Peripheral Access Control Register, offset: 0x28 */
+  __IO uint32_t PACRD;                             /**< Peripheral Access Control Register, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PACRE;                             /**< Peripheral Access Control Register, offset: 0x40 */
+  __IO uint32_t PACRF;                             /**< Peripheral Access Control Register, offset: 0x44 */
+  __IO uint32_t PACRG;                             /**< Peripheral Access Control Register, offset: 0x48 */
+  __IO uint32_t PACRH;                             /**< Peripheral Access Control Register, offset: 0x4C */
+  __IO uint32_t PACRI;                             /**< Peripheral Access Control Register, offset: 0x50 */
+  __IO uint32_t PACRJ;                             /**< Peripheral Access Control Register, offset: 0x54 */
+  __IO uint32_t PACRK;                             /**< Peripheral Access Control Register, offset: 0x58 */
+  __IO uint32_t PACRL;                             /**< Peripheral Access Control Register, offset: 0x5C */
+  __IO uint32_t PACRM;                             /**< Peripheral Access Control Register, offset: 0x60 */
+  __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
+  __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
+  __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t PACRU;                             /**< Peripheral Access Control Register, offset: 0x80 */
+} AIPS_Type, *AIPS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register accessors */
+#define AIPS_MPRA_REG(base)                      ((base)->MPRA)
+#define AIPS_PACRA_REG(base)                     ((base)->PACRA)
+#define AIPS_PACRB_REG(base)                     ((base)->PACRB)
+#define AIPS_PACRC_REG(base)                     ((base)->PACRC)
+#define AIPS_PACRD_REG(base)                     ((base)->PACRD)
+#define AIPS_PACRE_REG(base)                     ((base)->PACRE)
+#define AIPS_PACRF_REG(base)                     ((base)->PACRF)
+#define AIPS_PACRG_REG(base)                     ((base)->PACRG)
+#define AIPS_PACRH_REG(base)                     ((base)->PACRH)
+#define AIPS_PACRI_REG(base)                     ((base)->PACRI)
+#define AIPS_PACRJ_REG(base)                     ((base)->PACRJ)
+#define AIPS_PACRK_REG(base)                     ((base)->PACRK)
+#define AIPS_PACRL_REG(base)                     ((base)->PACRL)
+#define AIPS_PACRM_REG(base)                     ((base)->PACRM)
+#define AIPS_PACRN_REG(base)                     ((base)->PACRN)
+#define AIPS_PACRO_REG(base)                     ((base)->PACRO)
+#define AIPS_PACRP_REG(base)                     ((base)->PACRP)
+#define AIPS_PACRU_REG(base)                     ((base)->PACRU)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/* MPRA Bit Fields */
+#define AIPS_MPRA_MPL5_MASK                      0x100u
+#define AIPS_MPRA_MPL5_SHIFT                     8
+#define AIPS_MPRA_MPL5_WIDTH                     1
+#define AIPS_MPRA_MPL5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL5_SHIFT))&AIPS_MPRA_MPL5_MASK)
+#define AIPS_MPRA_MTW5_MASK                      0x200u
+#define AIPS_MPRA_MTW5_SHIFT                     9
+#define AIPS_MPRA_MTW5_WIDTH                     1
+#define AIPS_MPRA_MTW5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW5_SHIFT))&AIPS_MPRA_MTW5_MASK)
+#define AIPS_MPRA_MTR5_MASK                      0x400u
+#define AIPS_MPRA_MTR5_SHIFT                     10
+#define AIPS_MPRA_MTR5_WIDTH                     1
+#define AIPS_MPRA_MTR5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR5_SHIFT))&AIPS_MPRA_MTR5_MASK)
+#define AIPS_MPRA_MPL4_MASK                      0x1000u
+#define AIPS_MPRA_MPL4_SHIFT                     12
+#define AIPS_MPRA_MPL4_WIDTH                     1
+#define AIPS_MPRA_MPL4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL4_SHIFT))&AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MTW4_MASK                      0x2000u
+#define AIPS_MPRA_MTW4_SHIFT                     13
+#define AIPS_MPRA_MTW4_WIDTH                     1
+#define AIPS_MPRA_MTW4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW4_SHIFT))&AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTR4_MASK                      0x4000u
+#define AIPS_MPRA_MTR4_SHIFT                     14
+#define AIPS_MPRA_MTR4_WIDTH                     1
+#define AIPS_MPRA_MTR4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR4_SHIFT))&AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MPL3_MASK                      0x10000u
+#define AIPS_MPRA_MPL3_SHIFT                     16
+#define AIPS_MPRA_MPL3_WIDTH                     1
+#define AIPS_MPRA_MPL3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL3_SHIFT))&AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MTW3_MASK                      0x20000u
+#define AIPS_MPRA_MTW3_SHIFT                     17
+#define AIPS_MPRA_MTW3_WIDTH                     1
+#define AIPS_MPRA_MTW3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW3_SHIFT))&AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTR3_MASK                      0x40000u
+#define AIPS_MPRA_MTR3_SHIFT                     18
+#define AIPS_MPRA_MTR3_WIDTH                     1
+#define AIPS_MPRA_MTR3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR3_SHIFT))&AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MPL2_MASK                      0x100000u
+#define AIPS_MPRA_MPL2_SHIFT                     20
+#define AIPS_MPRA_MPL2_WIDTH                     1
+#define AIPS_MPRA_MPL2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL2_SHIFT))&AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MTW2_MASK                      0x200000u
+#define AIPS_MPRA_MTW2_SHIFT                     21
+#define AIPS_MPRA_MTW2_WIDTH                     1
+#define AIPS_MPRA_MTW2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW2_SHIFT))&AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTR2_MASK                      0x400000u
+#define AIPS_MPRA_MTR2_SHIFT                     22
+#define AIPS_MPRA_MTR2_WIDTH                     1
+#define AIPS_MPRA_MTR2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR2_SHIFT))&AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MPL1_MASK                      0x1000000u
+#define AIPS_MPRA_MPL1_SHIFT                     24
+#define AIPS_MPRA_MPL1_WIDTH                     1
+#define AIPS_MPRA_MPL1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL1_SHIFT))&AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MTW1_MASK                      0x2000000u
+#define AIPS_MPRA_MTW1_SHIFT                     25
+#define AIPS_MPRA_MTW1_WIDTH                     1
+#define AIPS_MPRA_MTW1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW1_SHIFT))&AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTR1_MASK                      0x4000000u
+#define AIPS_MPRA_MTR1_SHIFT                     26
+#define AIPS_MPRA_MTR1_WIDTH                     1
+#define AIPS_MPRA_MTR1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR1_SHIFT))&AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MPL0_MASK                      0x10000000u
+#define AIPS_MPRA_MPL0_SHIFT                     28
+#define AIPS_MPRA_MPL0_WIDTH                     1
+#define AIPS_MPRA_MPL0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL0_SHIFT))&AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MTW0_MASK                      0x20000000u
+#define AIPS_MPRA_MTW0_SHIFT                     29
+#define AIPS_MPRA_MTW0_WIDTH                     1
+#define AIPS_MPRA_MTW0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW0_SHIFT))&AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTR0_MASK                      0x40000000u
+#define AIPS_MPRA_MTR0_SHIFT                     30
+#define AIPS_MPRA_MTR0_WIDTH                     1
+#define AIPS_MPRA_MTR0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR0_SHIFT))&AIPS_MPRA_MTR0_MASK)
+/* PACRA Bit Fields */
+#define AIPS_PACRA_TP7_MASK                      0x1u
+#define AIPS_PACRA_TP7_SHIFT                     0
+#define AIPS_PACRA_TP7_WIDTH                     1
+#define AIPS_PACRA_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP7_SHIFT))&AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_WP7_MASK                      0x2u
+#define AIPS_PACRA_WP7_SHIFT                     1
+#define AIPS_PACRA_WP7_WIDTH                     1
+#define AIPS_PACRA_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP7_SHIFT))&AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_SP7_MASK                      0x4u
+#define AIPS_PACRA_SP7_SHIFT                     2
+#define AIPS_PACRA_SP7_WIDTH                     1
+#define AIPS_PACRA_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP7_SHIFT))&AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_TP6_MASK                      0x10u
+#define AIPS_PACRA_TP6_SHIFT                     4
+#define AIPS_PACRA_TP6_WIDTH                     1
+#define AIPS_PACRA_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP6_SHIFT))&AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_WP6_MASK                      0x20u
+#define AIPS_PACRA_WP6_SHIFT                     5
+#define AIPS_PACRA_WP6_WIDTH                     1
+#define AIPS_PACRA_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP6_SHIFT))&AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_SP6_MASK                      0x40u
+#define AIPS_PACRA_SP6_SHIFT                     6
+#define AIPS_PACRA_SP6_WIDTH                     1
+#define AIPS_PACRA_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP6_SHIFT))&AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_TP5_MASK                      0x100u
+#define AIPS_PACRA_TP5_SHIFT                     8
+#define AIPS_PACRA_TP5_WIDTH                     1
+#define AIPS_PACRA_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP5_SHIFT))&AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_WP5_MASK                      0x200u
+#define AIPS_PACRA_WP5_SHIFT                     9
+#define AIPS_PACRA_WP5_WIDTH                     1
+#define AIPS_PACRA_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP5_SHIFT))&AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_SP5_MASK                      0x400u
+#define AIPS_PACRA_SP5_SHIFT                     10
+#define AIPS_PACRA_SP5_WIDTH                     1
+#define AIPS_PACRA_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP5_SHIFT))&AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_TP4_MASK                      0x1000u
+#define AIPS_PACRA_TP4_SHIFT                     12
+#define AIPS_PACRA_TP4_WIDTH                     1
+#define AIPS_PACRA_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP4_SHIFT))&AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_WP4_MASK                      0x2000u
+#define AIPS_PACRA_WP4_SHIFT                     13
+#define AIPS_PACRA_WP4_WIDTH                     1
+#define AIPS_PACRA_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP4_SHIFT))&AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_SP4_MASK                      0x4000u
+#define AIPS_PACRA_SP4_SHIFT                     14
+#define AIPS_PACRA_SP4_WIDTH                     1
+#define AIPS_PACRA_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP4_SHIFT))&AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_TP3_MASK                      0x10000u
+#define AIPS_PACRA_TP3_SHIFT                     16
+#define AIPS_PACRA_TP3_WIDTH                     1
+#define AIPS_PACRA_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP3_SHIFT))&AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_WP3_MASK                      0x20000u
+#define AIPS_PACRA_WP3_SHIFT                     17
+#define AIPS_PACRA_WP3_WIDTH                     1
+#define AIPS_PACRA_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP3_SHIFT))&AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_SP3_MASK                      0x40000u
+#define AIPS_PACRA_SP3_SHIFT                     18
+#define AIPS_PACRA_SP3_WIDTH                     1
+#define AIPS_PACRA_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP3_SHIFT))&AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_TP2_MASK                      0x100000u
+#define AIPS_PACRA_TP2_SHIFT                     20
+#define AIPS_PACRA_TP2_WIDTH                     1
+#define AIPS_PACRA_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP2_SHIFT))&AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_WP2_MASK                      0x200000u
+#define AIPS_PACRA_WP2_SHIFT                     21
+#define AIPS_PACRA_WP2_WIDTH                     1
+#define AIPS_PACRA_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP2_SHIFT))&AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_SP2_MASK                      0x400000u
+#define AIPS_PACRA_SP2_SHIFT                     22
+#define AIPS_PACRA_SP2_WIDTH                     1
+#define AIPS_PACRA_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP2_SHIFT))&AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_TP1_MASK                      0x1000000u
+#define AIPS_PACRA_TP1_SHIFT                     24
+#define AIPS_PACRA_TP1_WIDTH                     1
+#define AIPS_PACRA_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP1_SHIFT))&AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_WP1_MASK                      0x2000000u
+#define AIPS_PACRA_WP1_SHIFT                     25
+#define AIPS_PACRA_WP1_WIDTH                     1
+#define AIPS_PACRA_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP1_SHIFT))&AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_SP1_MASK                      0x4000000u
+#define AIPS_PACRA_SP1_SHIFT                     26
+#define AIPS_PACRA_SP1_WIDTH                     1
+#define AIPS_PACRA_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP1_SHIFT))&AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_TP0_MASK                      0x10000000u
+#define AIPS_PACRA_TP0_SHIFT                     28
+#define AIPS_PACRA_TP0_WIDTH                     1
+#define AIPS_PACRA_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP0_SHIFT))&AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_WP0_MASK                      0x20000000u
+#define AIPS_PACRA_WP0_SHIFT                     29
+#define AIPS_PACRA_WP0_WIDTH                     1
+#define AIPS_PACRA_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP0_SHIFT))&AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_SP0_MASK                      0x40000000u
+#define AIPS_PACRA_SP0_SHIFT                     30
+#define AIPS_PACRA_SP0_WIDTH                     1
+#define AIPS_PACRA_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP0_SHIFT))&AIPS_PACRA_SP0_MASK)
+/* PACRB Bit Fields */
+#define AIPS_PACRB_TP7_MASK                      0x1u
+#define AIPS_PACRB_TP7_SHIFT                     0
+#define AIPS_PACRB_TP7_WIDTH                     1
+#define AIPS_PACRB_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP7_SHIFT))&AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_WP7_MASK                      0x2u
+#define AIPS_PACRB_WP7_SHIFT                     1
+#define AIPS_PACRB_WP7_WIDTH                     1
+#define AIPS_PACRB_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP7_SHIFT))&AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_SP7_MASK                      0x4u
+#define AIPS_PACRB_SP7_SHIFT                     2
+#define AIPS_PACRB_SP7_WIDTH                     1
+#define AIPS_PACRB_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP7_SHIFT))&AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_TP6_MASK                      0x10u
+#define AIPS_PACRB_TP6_SHIFT                     4
+#define AIPS_PACRB_TP6_WIDTH                     1
+#define AIPS_PACRB_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP6_SHIFT))&AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_WP6_MASK                      0x20u
+#define AIPS_PACRB_WP6_SHIFT                     5
+#define AIPS_PACRB_WP6_WIDTH                     1
+#define AIPS_PACRB_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP6_SHIFT))&AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_SP6_MASK                      0x40u
+#define AIPS_PACRB_SP6_SHIFT                     6
+#define AIPS_PACRB_SP6_WIDTH                     1
+#define AIPS_PACRB_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP6_SHIFT))&AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_TP5_MASK                      0x100u
+#define AIPS_PACRB_TP5_SHIFT                     8
+#define AIPS_PACRB_TP5_WIDTH                     1
+#define AIPS_PACRB_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP5_SHIFT))&AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_WP5_MASK                      0x200u
+#define AIPS_PACRB_WP5_SHIFT                     9
+#define AIPS_PACRB_WP5_WIDTH                     1
+#define AIPS_PACRB_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP5_SHIFT))&AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_SP5_MASK                      0x400u
+#define AIPS_PACRB_SP5_SHIFT                     10
+#define AIPS_PACRB_SP5_WIDTH                     1
+#define AIPS_PACRB_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP5_SHIFT))&AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_TP4_MASK                      0x1000u
+#define AIPS_PACRB_TP4_SHIFT                     12
+#define AIPS_PACRB_TP4_WIDTH                     1
+#define AIPS_PACRB_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP4_SHIFT))&AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_WP4_MASK                      0x2000u
+#define AIPS_PACRB_WP4_SHIFT                     13
+#define AIPS_PACRB_WP4_WIDTH                     1
+#define AIPS_PACRB_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP4_SHIFT))&AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_SP4_MASK                      0x4000u
+#define AIPS_PACRB_SP4_SHIFT                     14
+#define AIPS_PACRB_SP4_WIDTH                     1
+#define AIPS_PACRB_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP4_SHIFT))&AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_TP3_MASK                      0x10000u
+#define AIPS_PACRB_TP3_SHIFT                     16
+#define AIPS_PACRB_TP3_WIDTH                     1
+#define AIPS_PACRB_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP3_SHIFT))&AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_WP3_MASK                      0x20000u
+#define AIPS_PACRB_WP3_SHIFT                     17
+#define AIPS_PACRB_WP3_WIDTH                     1
+#define AIPS_PACRB_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP3_SHIFT))&AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_SP3_MASK                      0x40000u
+#define AIPS_PACRB_SP3_SHIFT                     18
+#define AIPS_PACRB_SP3_WIDTH                     1
+#define AIPS_PACRB_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP3_SHIFT))&AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_TP2_MASK                      0x100000u
+#define AIPS_PACRB_TP2_SHIFT                     20
+#define AIPS_PACRB_TP2_WIDTH                     1
+#define AIPS_PACRB_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP2_SHIFT))&AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_WP2_MASK                      0x200000u
+#define AIPS_PACRB_WP2_SHIFT                     21
+#define AIPS_PACRB_WP2_WIDTH                     1
+#define AIPS_PACRB_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP2_SHIFT))&AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_SP2_MASK                      0x400000u
+#define AIPS_PACRB_SP2_SHIFT                     22
+#define AIPS_PACRB_SP2_WIDTH                     1
+#define AIPS_PACRB_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP2_SHIFT))&AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_TP1_MASK                      0x1000000u
+#define AIPS_PACRB_TP1_SHIFT                     24
+#define AIPS_PACRB_TP1_WIDTH                     1
+#define AIPS_PACRB_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP1_SHIFT))&AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_WP1_MASK                      0x2000000u
+#define AIPS_PACRB_WP1_SHIFT                     25
+#define AIPS_PACRB_WP1_WIDTH                     1
+#define AIPS_PACRB_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP1_SHIFT))&AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_SP1_MASK                      0x4000000u
+#define AIPS_PACRB_SP1_SHIFT                     26
+#define AIPS_PACRB_SP1_WIDTH                     1
+#define AIPS_PACRB_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP1_SHIFT))&AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_TP0_MASK                      0x10000000u
+#define AIPS_PACRB_TP0_SHIFT                     28
+#define AIPS_PACRB_TP0_WIDTH                     1
+#define AIPS_PACRB_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP0_SHIFT))&AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_WP0_MASK                      0x20000000u
+#define AIPS_PACRB_WP0_SHIFT                     29
+#define AIPS_PACRB_WP0_WIDTH                     1
+#define AIPS_PACRB_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP0_SHIFT))&AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_SP0_MASK                      0x40000000u
+#define AIPS_PACRB_SP0_SHIFT                     30
+#define AIPS_PACRB_SP0_WIDTH                     1
+#define AIPS_PACRB_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP0_SHIFT))&AIPS_PACRB_SP0_MASK)
+/* PACRC Bit Fields */
+#define AIPS_PACRC_TP7_MASK                      0x1u
+#define AIPS_PACRC_TP7_SHIFT                     0
+#define AIPS_PACRC_TP7_WIDTH                     1
+#define AIPS_PACRC_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP7_SHIFT))&AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_WP7_MASK                      0x2u
+#define AIPS_PACRC_WP7_SHIFT                     1
+#define AIPS_PACRC_WP7_WIDTH                     1
+#define AIPS_PACRC_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP7_SHIFT))&AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_SP7_MASK                      0x4u
+#define AIPS_PACRC_SP7_SHIFT                     2
+#define AIPS_PACRC_SP7_WIDTH                     1
+#define AIPS_PACRC_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP7_SHIFT))&AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_TP6_MASK                      0x10u
+#define AIPS_PACRC_TP6_SHIFT                     4
+#define AIPS_PACRC_TP6_WIDTH                     1
+#define AIPS_PACRC_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP6_SHIFT))&AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_WP6_MASK                      0x20u
+#define AIPS_PACRC_WP6_SHIFT                     5
+#define AIPS_PACRC_WP6_WIDTH                     1
+#define AIPS_PACRC_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP6_SHIFT))&AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_SP6_MASK                      0x40u
+#define AIPS_PACRC_SP6_SHIFT                     6
+#define AIPS_PACRC_SP6_WIDTH                     1
+#define AIPS_PACRC_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP6_SHIFT))&AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_TP5_MASK                      0x100u
+#define AIPS_PACRC_TP5_SHIFT                     8
+#define AIPS_PACRC_TP5_WIDTH                     1
+#define AIPS_PACRC_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP5_SHIFT))&AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_WP5_MASK                      0x200u
+#define AIPS_PACRC_WP5_SHIFT                     9
+#define AIPS_PACRC_WP5_WIDTH                     1
+#define AIPS_PACRC_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP5_SHIFT))&AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_SP5_MASK                      0x400u
+#define AIPS_PACRC_SP5_SHIFT                     10
+#define AIPS_PACRC_SP5_WIDTH                     1
+#define AIPS_PACRC_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP5_SHIFT))&AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_TP4_MASK                      0x1000u
+#define AIPS_PACRC_TP4_SHIFT                     12
+#define AIPS_PACRC_TP4_WIDTH                     1
+#define AIPS_PACRC_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP4_SHIFT))&AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_WP4_MASK                      0x2000u
+#define AIPS_PACRC_WP4_SHIFT                     13
+#define AIPS_PACRC_WP4_WIDTH                     1
+#define AIPS_PACRC_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP4_SHIFT))&AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_SP4_MASK                      0x4000u
+#define AIPS_PACRC_SP4_SHIFT                     14
+#define AIPS_PACRC_SP4_WIDTH                     1
+#define AIPS_PACRC_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP4_SHIFT))&AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_TP3_MASK                      0x10000u
+#define AIPS_PACRC_TP3_SHIFT                     16
+#define AIPS_PACRC_TP3_WIDTH                     1
+#define AIPS_PACRC_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP3_SHIFT))&AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_WP3_MASK                      0x20000u
+#define AIPS_PACRC_WP3_SHIFT                     17
+#define AIPS_PACRC_WP3_WIDTH                     1
+#define AIPS_PACRC_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP3_SHIFT))&AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_SP3_MASK                      0x40000u
+#define AIPS_PACRC_SP3_SHIFT                     18
+#define AIPS_PACRC_SP3_WIDTH                     1
+#define AIPS_PACRC_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP3_SHIFT))&AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_TP2_MASK                      0x100000u
+#define AIPS_PACRC_TP2_SHIFT                     20
+#define AIPS_PACRC_TP2_WIDTH                     1
+#define AIPS_PACRC_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP2_SHIFT))&AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_WP2_MASK                      0x200000u
+#define AIPS_PACRC_WP2_SHIFT                     21
+#define AIPS_PACRC_WP2_WIDTH                     1
+#define AIPS_PACRC_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP2_SHIFT))&AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_SP2_MASK                      0x400000u
+#define AIPS_PACRC_SP2_SHIFT                     22
+#define AIPS_PACRC_SP2_WIDTH                     1
+#define AIPS_PACRC_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP2_SHIFT))&AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_TP1_MASK                      0x1000000u
+#define AIPS_PACRC_TP1_SHIFT                     24
+#define AIPS_PACRC_TP1_WIDTH                     1
+#define AIPS_PACRC_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP1_SHIFT))&AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_WP1_MASK                      0x2000000u
+#define AIPS_PACRC_WP1_SHIFT                     25
+#define AIPS_PACRC_WP1_WIDTH                     1
+#define AIPS_PACRC_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP1_SHIFT))&AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_SP1_MASK                      0x4000000u
+#define AIPS_PACRC_SP1_SHIFT                     26
+#define AIPS_PACRC_SP1_WIDTH                     1
+#define AIPS_PACRC_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP1_SHIFT))&AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_TP0_MASK                      0x10000000u
+#define AIPS_PACRC_TP0_SHIFT                     28
+#define AIPS_PACRC_TP0_WIDTH                     1
+#define AIPS_PACRC_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP0_SHIFT))&AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_WP0_MASK                      0x20000000u
+#define AIPS_PACRC_WP0_SHIFT                     29
+#define AIPS_PACRC_WP0_WIDTH                     1
+#define AIPS_PACRC_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP0_SHIFT))&AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_SP0_MASK                      0x40000000u
+#define AIPS_PACRC_SP0_SHIFT                     30
+#define AIPS_PACRC_SP0_WIDTH                     1
+#define AIPS_PACRC_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP0_SHIFT))&AIPS_PACRC_SP0_MASK)
+/* PACRD Bit Fields */
+#define AIPS_PACRD_TP7_MASK                      0x1u
+#define AIPS_PACRD_TP7_SHIFT                     0
+#define AIPS_PACRD_TP7_WIDTH                     1
+#define AIPS_PACRD_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP7_SHIFT))&AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_WP7_MASK                      0x2u
+#define AIPS_PACRD_WP7_SHIFT                     1
+#define AIPS_PACRD_WP7_WIDTH                     1
+#define AIPS_PACRD_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP7_SHIFT))&AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_SP7_MASK                      0x4u
+#define AIPS_PACRD_SP7_SHIFT                     2
+#define AIPS_PACRD_SP7_WIDTH                     1
+#define AIPS_PACRD_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP7_SHIFT))&AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_TP6_MASK                      0x10u
+#define AIPS_PACRD_TP6_SHIFT                     4
+#define AIPS_PACRD_TP6_WIDTH                     1
+#define AIPS_PACRD_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP6_SHIFT))&AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_WP6_MASK                      0x20u
+#define AIPS_PACRD_WP6_SHIFT                     5
+#define AIPS_PACRD_WP6_WIDTH                     1
+#define AIPS_PACRD_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP6_SHIFT))&AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_SP6_MASK                      0x40u
+#define AIPS_PACRD_SP6_SHIFT                     6
+#define AIPS_PACRD_SP6_WIDTH                     1
+#define AIPS_PACRD_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP6_SHIFT))&AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_TP5_MASK                      0x100u
+#define AIPS_PACRD_TP5_SHIFT                     8
+#define AIPS_PACRD_TP5_WIDTH                     1
+#define AIPS_PACRD_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP5_SHIFT))&AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_WP5_MASK                      0x200u
+#define AIPS_PACRD_WP5_SHIFT                     9
+#define AIPS_PACRD_WP5_WIDTH                     1
+#define AIPS_PACRD_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP5_SHIFT))&AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_SP5_MASK                      0x400u
+#define AIPS_PACRD_SP5_SHIFT                     10
+#define AIPS_PACRD_SP5_WIDTH                     1
+#define AIPS_PACRD_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP5_SHIFT))&AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_TP4_MASK                      0x1000u
+#define AIPS_PACRD_TP4_SHIFT                     12
+#define AIPS_PACRD_TP4_WIDTH                     1
+#define AIPS_PACRD_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP4_SHIFT))&AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_WP4_MASK                      0x2000u
+#define AIPS_PACRD_WP4_SHIFT                     13
+#define AIPS_PACRD_WP4_WIDTH                     1
+#define AIPS_PACRD_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP4_SHIFT))&AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_SP4_MASK                      0x4000u
+#define AIPS_PACRD_SP4_SHIFT                     14
+#define AIPS_PACRD_SP4_WIDTH                     1
+#define AIPS_PACRD_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP4_SHIFT))&AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_TP3_MASK                      0x10000u
+#define AIPS_PACRD_TP3_SHIFT                     16
+#define AIPS_PACRD_TP3_WIDTH                     1
+#define AIPS_PACRD_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP3_SHIFT))&AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_WP3_MASK                      0x20000u
+#define AIPS_PACRD_WP3_SHIFT                     17
+#define AIPS_PACRD_WP3_WIDTH                     1
+#define AIPS_PACRD_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP3_SHIFT))&AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_SP3_MASK                      0x40000u
+#define AIPS_PACRD_SP3_SHIFT                     18
+#define AIPS_PACRD_SP3_WIDTH                     1
+#define AIPS_PACRD_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP3_SHIFT))&AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_TP2_MASK                      0x100000u
+#define AIPS_PACRD_TP2_SHIFT                     20
+#define AIPS_PACRD_TP2_WIDTH                     1
+#define AIPS_PACRD_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP2_SHIFT))&AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_WP2_MASK                      0x200000u
+#define AIPS_PACRD_WP2_SHIFT                     21
+#define AIPS_PACRD_WP2_WIDTH                     1
+#define AIPS_PACRD_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP2_SHIFT))&AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_SP2_MASK                      0x400000u
+#define AIPS_PACRD_SP2_SHIFT                     22
+#define AIPS_PACRD_SP2_WIDTH                     1
+#define AIPS_PACRD_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP2_SHIFT))&AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_TP1_MASK                      0x1000000u
+#define AIPS_PACRD_TP1_SHIFT                     24
+#define AIPS_PACRD_TP1_WIDTH                     1
+#define AIPS_PACRD_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP1_SHIFT))&AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_WP1_MASK                      0x2000000u
+#define AIPS_PACRD_WP1_SHIFT                     25
+#define AIPS_PACRD_WP1_WIDTH                     1
+#define AIPS_PACRD_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP1_SHIFT))&AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_SP1_MASK                      0x4000000u
+#define AIPS_PACRD_SP1_SHIFT                     26
+#define AIPS_PACRD_SP1_WIDTH                     1
+#define AIPS_PACRD_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP1_SHIFT))&AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_TP0_MASK                      0x10000000u
+#define AIPS_PACRD_TP0_SHIFT                     28
+#define AIPS_PACRD_TP0_WIDTH                     1
+#define AIPS_PACRD_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP0_SHIFT))&AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_WP0_MASK                      0x20000000u
+#define AIPS_PACRD_WP0_SHIFT                     29
+#define AIPS_PACRD_WP0_WIDTH                     1
+#define AIPS_PACRD_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP0_SHIFT))&AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_SP0_MASK                      0x40000000u
+#define AIPS_PACRD_SP0_SHIFT                     30
+#define AIPS_PACRD_SP0_WIDTH                     1
+#define AIPS_PACRD_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP0_SHIFT))&AIPS_PACRD_SP0_MASK)
+/* PACRE Bit Fields */
+#define AIPS_PACRE_TP7_MASK                      0x1u
+#define AIPS_PACRE_TP7_SHIFT                     0
+#define AIPS_PACRE_TP7_WIDTH                     1
+#define AIPS_PACRE_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP7_SHIFT))&AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_WP7_MASK                      0x2u
+#define AIPS_PACRE_WP7_SHIFT                     1
+#define AIPS_PACRE_WP7_WIDTH                     1
+#define AIPS_PACRE_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP7_SHIFT))&AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_SP7_MASK                      0x4u
+#define AIPS_PACRE_SP7_SHIFT                     2
+#define AIPS_PACRE_SP7_WIDTH                     1
+#define AIPS_PACRE_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP7_SHIFT))&AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_TP6_MASK                      0x10u
+#define AIPS_PACRE_TP6_SHIFT                     4
+#define AIPS_PACRE_TP6_WIDTH                     1
+#define AIPS_PACRE_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP6_SHIFT))&AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_WP6_MASK                      0x20u
+#define AIPS_PACRE_WP6_SHIFT                     5
+#define AIPS_PACRE_WP6_WIDTH                     1
+#define AIPS_PACRE_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP6_SHIFT))&AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_SP6_MASK                      0x40u
+#define AIPS_PACRE_SP6_SHIFT                     6
+#define AIPS_PACRE_SP6_WIDTH                     1
+#define AIPS_PACRE_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP6_SHIFT))&AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_TP5_MASK                      0x100u
+#define AIPS_PACRE_TP5_SHIFT                     8
+#define AIPS_PACRE_TP5_WIDTH                     1
+#define AIPS_PACRE_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP5_SHIFT))&AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_WP5_MASK                      0x200u
+#define AIPS_PACRE_WP5_SHIFT                     9
+#define AIPS_PACRE_WP5_WIDTH                     1
+#define AIPS_PACRE_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP5_SHIFT))&AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_SP5_MASK                      0x400u
+#define AIPS_PACRE_SP5_SHIFT                     10
+#define AIPS_PACRE_SP5_WIDTH                     1
+#define AIPS_PACRE_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP5_SHIFT))&AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_TP4_MASK                      0x1000u
+#define AIPS_PACRE_TP4_SHIFT                     12
+#define AIPS_PACRE_TP4_WIDTH                     1
+#define AIPS_PACRE_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP4_SHIFT))&AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_WP4_MASK                      0x2000u
+#define AIPS_PACRE_WP4_SHIFT                     13
+#define AIPS_PACRE_WP4_WIDTH                     1
+#define AIPS_PACRE_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP4_SHIFT))&AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_SP4_MASK                      0x4000u
+#define AIPS_PACRE_SP4_SHIFT                     14
+#define AIPS_PACRE_SP4_WIDTH                     1
+#define AIPS_PACRE_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP4_SHIFT))&AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_TP3_MASK                      0x10000u
+#define AIPS_PACRE_TP3_SHIFT                     16
+#define AIPS_PACRE_TP3_WIDTH                     1
+#define AIPS_PACRE_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP3_SHIFT))&AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_WP3_MASK                      0x20000u
+#define AIPS_PACRE_WP3_SHIFT                     17
+#define AIPS_PACRE_WP3_WIDTH                     1
+#define AIPS_PACRE_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP3_SHIFT))&AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_SP3_MASK                      0x40000u
+#define AIPS_PACRE_SP3_SHIFT                     18
+#define AIPS_PACRE_SP3_WIDTH                     1
+#define AIPS_PACRE_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP3_SHIFT))&AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_TP2_MASK                      0x100000u
+#define AIPS_PACRE_TP2_SHIFT                     20
+#define AIPS_PACRE_TP2_WIDTH                     1
+#define AIPS_PACRE_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP2_SHIFT))&AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_WP2_MASK                      0x200000u
+#define AIPS_PACRE_WP2_SHIFT                     21
+#define AIPS_PACRE_WP2_WIDTH                     1
+#define AIPS_PACRE_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP2_SHIFT))&AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_SP2_MASK                      0x400000u
+#define AIPS_PACRE_SP2_SHIFT                     22
+#define AIPS_PACRE_SP2_WIDTH                     1
+#define AIPS_PACRE_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP2_SHIFT))&AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_TP1_MASK                      0x1000000u
+#define AIPS_PACRE_TP1_SHIFT                     24
+#define AIPS_PACRE_TP1_WIDTH                     1
+#define AIPS_PACRE_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP1_SHIFT))&AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_WP1_MASK                      0x2000000u
+#define AIPS_PACRE_WP1_SHIFT                     25
+#define AIPS_PACRE_WP1_WIDTH                     1
+#define AIPS_PACRE_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP1_SHIFT))&AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_SP1_MASK                      0x4000000u
+#define AIPS_PACRE_SP1_SHIFT                     26
+#define AIPS_PACRE_SP1_WIDTH                     1
+#define AIPS_PACRE_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP1_SHIFT))&AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_TP0_MASK                      0x10000000u
+#define AIPS_PACRE_TP0_SHIFT                     28
+#define AIPS_PACRE_TP0_WIDTH                     1
+#define AIPS_PACRE_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP0_SHIFT))&AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_WP0_MASK                      0x20000000u
+#define AIPS_PACRE_WP0_SHIFT                     29
+#define AIPS_PACRE_WP0_WIDTH                     1
+#define AIPS_PACRE_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP0_SHIFT))&AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_SP0_MASK                      0x40000000u
+#define AIPS_PACRE_SP0_SHIFT                     30
+#define AIPS_PACRE_SP0_WIDTH                     1
+#define AIPS_PACRE_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP0_SHIFT))&AIPS_PACRE_SP0_MASK)
+/* PACRF Bit Fields */
+#define AIPS_PACRF_TP7_MASK                      0x1u
+#define AIPS_PACRF_TP7_SHIFT                     0
+#define AIPS_PACRF_TP7_WIDTH                     1
+#define AIPS_PACRF_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP7_SHIFT))&AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_WP7_MASK                      0x2u
+#define AIPS_PACRF_WP7_SHIFT                     1
+#define AIPS_PACRF_WP7_WIDTH                     1
+#define AIPS_PACRF_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP7_SHIFT))&AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_SP7_MASK                      0x4u
+#define AIPS_PACRF_SP7_SHIFT                     2
+#define AIPS_PACRF_SP7_WIDTH                     1
+#define AIPS_PACRF_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP7_SHIFT))&AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_TP6_MASK                      0x10u
+#define AIPS_PACRF_TP6_SHIFT                     4
+#define AIPS_PACRF_TP6_WIDTH                     1
+#define AIPS_PACRF_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP6_SHIFT))&AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_WP6_MASK                      0x20u
+#define AIPS_PACRF_WP6_SHIFT                     5
+#define AIPS_PACRF_WP6_WIDTH                     1
+#define AIPS_PACRF_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP6_SHIFT))&AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_SP6_MASK                      0x40u
+#define AIPS_PACRF_SP6_SHIFT                     6
+#define AIPS_PACRF_SP6_WIDTH                     1
+#define AIPS_PACRF_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP6_SHIFT))&AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_TP5_MASK                      0x100u
+#define AIPS_PACRF_TP5_SHIFT                     8
+#define AIPS_PACRF_TP5_WIDTH                     1
+#define AIPS_PACRF_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP5_SHIFT))&AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_WP5_MASK                      0x200u
+#define AIPS_PACRF_WP5_SHIFT                     9
+#define AIPS_PACRF_WP5_WIDTH                     1
+#define AIPS_PACRF_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP5_SHIFT))&AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_SP5_MASK                      0x400u
+#define AIPS_PACRF_SP5_SHIFT                     10
+#define AIPS_PACRF_SP5_WIDTH                     1
+#define AIPS_PACRF_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP5_SHIFT))&AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_TP4_MASK                      0x1000u
+#define AIPS_PACRF_TP4_SHIFT                     12
+#define AIPS_PACRF_TP4_WIDTH                     1
+#define AIPS_PACRF_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP4_SHIFT))&AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_WP4_MASK                      0x2000u
+#define AIPS_PACRF_WP4_SHIFT                     13
+#define AIPS_PACRF_WP4_WIDTH                     1
+#define AIPS_PACRF_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP4_SHIFT))&AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_SP4_MASK                      0x4000u
+#define AIPS_PACRF_SP4_SHIFT                     14
+#define AIPS_PACRF_SP4_WIDTH                     1
+#define AIPS_PACRF_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP4_SHIFT))&AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_TP3_MASK                      0x10000u
+#define AIPS_PACRF_TP3_SHIFT                     16
+#define AIPS_PACRF_TP3_WIDTH                     1
+#define AIPS_PACRF_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP3_SHIFT))&AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_WP3_MASK                      0x20000u
+#define AIPS_PACRF_WP3_SHIFT                     17
+#define AIPS_PACRF_WP3_WIDTH                     1
+#define AIPS_PACRF_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP3_SHIFT))&AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_SP3_MASK                      0x40000u
+#define AIPS_PACRF_SP3_SHIFT                     18
+#define AIPS_PACRF_SP3_WIDTH                     1
+#define AIPS_PACRF_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP3_SHIFT))&AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_TP2_MASK                      0x100000u
+#define AIPS_PACRF_TP2_SHIFT                     20
+#define AIPS_PACRF_TP2_WIDTH                     1
+#define AIPS_PACRF_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP2_SHIFT))&AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_WP2_MASK                      0x200000u
+#define AIPS_PACRF_WP2_SHIFT                     21
+#define AIPS_PACRF_WP2_WIDTH                     1
+#define AIPS_PACRF_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP2_SHIFT))&AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_SP2_MASK                      0x400000u
+#define AIPS_PACRF_SP2_SHIFT                     22
+#define AIPS_PACRF_SP2_WIDTH                     1
+#define AIPS_PACRF_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP2_SHIFT))&AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_TP1_MASK                      0x1000000u
+#define AIPS_PACRF_TP1_SHIFT                     24
+#define AIPS_PACRF_TP1_WIDTH                     1
+#define AIPS_PACRF_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP1_SHIFT))&AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_WP1_MASK                      0x2000000u
+#define AIPS_PACRF_WP1_SHIFT                     25
+#define AIPS_PACRF_WP1_WIDTH                     1
+#define AIPS_PACRF_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP1_SHIFT))&AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_SP1_MASK                      0x4000000u
+#define AIPS_PACRF_SP1_SHIFT                     26
+#define AIPS_PACRF_SP1_WIDTH                     1
+#define AIPS_PACRF_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP1_SHIFT))&AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_TP0_MASK                      0x10000000u
+#define AIPS_PACRF_TP0_SHIFT                     28
+#define AIPS_PACRF_TP0_WIDTH                     1
+#define AIPS_PACRF_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP0_SHIFT))&AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_WP0_MASK                      0x20000000u
+#define AIPS_PACRF_WP0_SHIFT                     29
+#define AIPS_PACRF_WP0_WIDTH                     1
+#define AIPS_PACRF_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP0_SHIFT))&AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_SP0_MASK                      0x40000000u
+#define AIPS_PACRF_SP0_SHIFT                     30
+#define AIPS_PACRF_SP0_WIDTH                     1
+#define AIPS_PACRF_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP0_SHIFT))&AIPS_PACRF_SP0_MASK)
+/* PACRG Bit Fields */
+#define AIPS_PACRG_TP7_MASK                      0x1u
+#define AIPS_PACRG_TP7_SHIFT                     0
+#define AIPS_PACRG_TP7_WIDTH                     1
+#define AIPS_PACRG_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP7_SHIFT))&AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_WP7_MASK                      0x2u
+#define AIPS_PACRG_WP7_SHIFT                     1
+#define AIPS_PACRG_WP7_WIDTH                     1
+#define AIPS_PACRG_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP7_SHIFT))&AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_SP7_MASK                      0x4u
+#define AIPS_PACRG_SP7_SHIFT                     2
+#define AIPS_PACRG_SP7_WIDTH                     1
+#define AIPS_PACRG_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP7_SHIFT))&AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_TP6_MASK                      0x10u
+#define AIPS_PACRG_TP6_SHIFT                     4
+#define AIPS_PACRG_TP6_WIDTH                     1
+#define AIPS_PACRG_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP6_SHIFT))&AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_WP6_MASK                      0x20u
+#define AIPS_PACRG_WP6_SHIFT                     5
+#define AIPS_PACRG_WP6_WIDTH                     1
+#define AIPS_PACRG_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP6_SHIFT))&AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_SP6_MASK                      0x40u
+#define AIPS_PACRG_SP6_SHIFT                     6
+#define AIPS_PACRG_SP6_WIDTH                     1
+#define AIPS_PACRG_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP6_SHIFT))&AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_TP5_MASK                      0x100u
+#define AIPS_PACRG_TP5_SHIFT                     8
+#define AIPS_PACRG_TP5_WIDTH                     1
+#define AIPS_PACRG_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP5_SHIFT))&AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_WP5_MASK                      0x200u
+#define AIPS_PACRG_WP5_SHIFT                     9
+#define AIPS_PACRG_WP5_WIDTH                     1
+#define AIPS_PACRG_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP5_SHIFT))&AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_SP5_MASK                      0x400u
+#define AIPS_PACRG_SP5_SHIFT                     10
+#define AIPS_PACRG_SP5_WIDTH                     1
+#define AIPS_PACRG_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP5_SHIFT))&AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_TP4_MASK                      0x1000u
+#define AIPS_PACRG_TP4_SHIFT                     12
+#define AIPS_PACRG_TP4_WIDTH                     1
+#define AIPS_PACRG_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP4_SHIFT))&AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_WP4_MASK                      0x2000u
+#define AIPS_PACRG_WP4_SHIFT                     13
+#define AIPS_PACRG_WP4_WIDTH                     1
+#define AIPS_PACRG_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP4_SHIFT))&AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_SP4_MASK                      0x4000u
+#define AIPS_PACRG_SP4_SHIFT                     14
+#define AIPS_PACRG_SP4_WIDTH                     1
+#define AIPS_PACRG_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP4_SHIFT))&AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_TP3_MASK                      0x10000u
+#define AIPS_PACRG_TP3_SHIFT                     16
+#define AIPS_PACRG_TP3_WIDTH                     1
+#define AIPS_PACRG_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP3_SHIFT))&AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_WP3_MASK                      0x20000u
+#define AIPS_PACRG_WP3_SHIFT                     17
+#define AIPS_PACRG_WP3_WIDTH                     1
+#define AIPS_PACRG_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP3_SHIFT))&AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_SP3_MASK                      0x40000u
+#define AIPS_PACRG_SP3_SHIFT                     18
+#define AIPS_PACRG_SP3_WIDTH                     1
+#define AIPS_PACRG_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP3_SHIFT))&AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_TP2_MASK                      0x100000u
+#define AIPS_PACRG_TP2_SHIFT                     20
+#define AIPS_PACRG_TP2_WIDTH                     1
+#define AIPS_PACRG_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP2_SHIFT))&AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_WP2_MASK                      0x200000u
+#define AIPS_PACRG_WP2_SHIFT                     21
+#define AIPS_PACRG_WP2_WIDTH                     1
+#define AIPS_PACRG_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP2_SHIFT))&AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_SP2_MASK                      0x400000u
+#define AIPS_PACRG_SP2_SHIFT                     22
+#define AIPS_PACRG_SP2_WIDTH                     1
+#define AIPS_PACRG_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP2_SHIFT))&AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_TP1_MASK                      0x1000000u
+#define AIPS_PACRG_TP1_SHIFT                     24
+#define AIPS_PACRG_TP1_WIDTH                     1
+#define AIPS_PACRG_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP1_SHIFT))&AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_WP1_MASK                      0x2000000u
+#define AIPS_PACRG_WP1_SHIFT                     25
+#define AIPS_PACRG_WP1_WIDTH                     1
+#define AIPS_PACRG_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP1_SHIFT))&AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_SP1_MASK                      0x4000000u
+#define AIPS_PACRG_SP1_SHIFT                     26
+#define AIPS_PACRG_SP1_WIDTH                     1
+#define AIPS_PACRG_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP1_SHIFT))&AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_TP0_MASK                      0x10000000u
+#define AIPS_PACRG_TP0_SHIFT                     28
+#define AIPS_PACRG_TP0_WIDTH                     1
+#define AIPS_PACRG_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP0_SHIFT))&AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_WP0_MASK                      0x20000000u
+#define AIPS_PACRG_WP0_SHIFT                     29
+#define AIPS_PACRG_WP0_WIDTH                     1
+#define AIPS_PACRG_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP0_SHIFT))&AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_SP0_MASK                      0x40000000u
+#define AIPS_PACRG_SP0_SHIFT                     30
+#define AIPS_PACRG_SP0_WIDTH                     1
+#define AIPS_PACRG_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP0_SHIFT))&AIPS_PACRG_SP0_MASK)
+/* PACRH Bit Fields */
+#define AIPS_PACRH_TP7_MASK                      0x1u
+#define AIPS_PACRH_TP7_SHIFT                     0
+#define AIPS_PACRH_TP7_WIDTH                     1
+#define AIPS_PACRH_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP7_SHIFT))&AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_WP7_MASK                      0x2u
+#define AIPS_PACRH_WP7_SHIFT                     1
+#define AIPS_PACRH_WP7_WIDTH                     1
+#define AIPS_PACRH_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP7_SHIFT))&AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_SP7_MASK                      0x4u
+#define AIPS_PACRH_SP7_SHIFT                     2
+#define AIPS_PACRH_SP7_WIDTH                     1
+#define AIPS_PACRH_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP7_SHIFT))&AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_TP6_MASK                      0x10u
+#define AIPS_PACRH_TP6_SHIFT                     4
+#define AIPS_PACRH_TP6_WIDTH                     1
+#define AIPS_PACRH_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP6_SHIFT))&AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_WP6_MASK                      0x20u
+#define AIPS_PACRH_WP6_SHIFT                     5
+#define AIPS_PACRH_WP6_WIDTH                     1
+#define AIPS_PACRH_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP6_SHIFT))&AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_SP6_MASK                      0x40u
+#define AIPS_PACRH_SP6_SHIFT                     6
+#define AIPS_PACRH_SP6_WIDTH                     1
+#define AIPS_PACRH_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP6_SHIFT))&AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_TP5_MASK                      0x100u
+#define AIPS_PACRH_TP5_SHIFT                     8
+#define AIPS_PACRH_TP5_WIDTH                     1
+#define AIPS_PACRH_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP5_SHIFT))&AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_WP5_MASK                      0x200u
+#define AIPS_PACRH_WP5_SHIFT                     9
+#define AIPS_PACRH_WP5_WIDTH                     1
+#define AIPS_PACRH_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP5_SHIFT))&AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_SP5_MASK                      0x400u
+#define AIPS_PACRH_SP5_SHIFT                     10
+#define AIPS_PACRH_SP5_WIDTH                     1
+#define AIPS_PACRH_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP5_SHIFT))&AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_TP4_MASK                      0x1000u
+#define AIPS_PACRH_TP4_SHIFT                     12
+#define AIPS_PACRH_TP4_WIDTH                     1
+#define AIPS_PACRH_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP4_SHIFT))&AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_WP4_MASK                      0x2000u
+#define AIPS_PACRH_WP4_SHIFT                     13
+#define AIPS_PACRH_WP4_WIDTH                     1
+#define AIPS_PACRH_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP4_SHIFT))&AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_SP4_MASK                      0x4000u
+#define AIPS_PACRH_SP4_SHIFT                     14
+#define AIPS_PACRH_SP4_WIDTH                     1
+#define AIPS_PACRH_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP4_SHIFT))&AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_TP3_MASK                      0x10000u
+#define AIPS_PACRH_TP3_SHIFT                     16
+#define AIPS_PACRH_TP3_WIDTH                     1
+#define AIPS_PACRH_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP3_SHIFT))&AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_WP3_MASK                      0x20000u
+#define AIPS_PACRH_WP3_SHIFT                     17
+#define AIPS_PACRH_WP3_WIDTH                     1
+#define AIPS_PACRH_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP3_SHIFT))&AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_SP3_MASK                      0x40000u
+#define AIPS_PACRH_SP3_SHIFT                     18
+#define AIPS_PACRH_SP3_WIDTH                     1
+#define AIPS_PACRH_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP3_SHIFT))&AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_TP2_MASK                      0x100000u
+#define AIPS_PACRH_TP2_SHIFT                     20
+#define AIPS_PACRH_TP2_WIDTH                     1
+#define AIPS_PACRH_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP2_SHIFT))&AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_WP2_MASK                      0x200000u
+#define AIPS_PACRH_WP2_SHIFT                     21
+#define AIPS_PACRH_WP2_WIDTH                     1
+#define AIPS_PACRH_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP2_SHIFT))&AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_SP2_MASK                      0x400000u
+#define AIPS_PACRH_SP2_SHIFT                     22
+#define AIPS_PACRH_SP2_WIDTH                     1
+#define AIPS_PACRH_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP2_SHIFT))&AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_TP1_MASK                      0x1000000u
+#define AIPS_PACRH_TP1_SHIFT                     24
+#define AIPS_PACRH_TP1_WIDTH                     1
+#define AIPS_PACRH_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP1_SHIFT))&AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_WP1_MASK                      0x2000000u
+#define AIPS_PACRH_WP1_SHIFT                     25
+#define AIPS_PACRH_WP1_WIDTH                     1
+#define AIPS_PACRH_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP1_SHIFT))&AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_SP1_MASK                      0x4000000u
+#define AIPS_PACRH_SP1_SHIFT                     26
+#define AIPS_PACRH_SP1_WIDTH                     1
+#define AIPS_PACRH_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP1_SHIFT))&AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_TP0_MASK                      0x10000000u
+#define AIPS_PACRH_TP0_SHIFT                     28
+#define AIPS_PACRH_TP0_WIDTH                     1
+#define AIPS_PACRH_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP0_SHIFT))&AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_WP0_MASK                      0x20000000u
+#define AIPS_PACRH_WP0_SHIFT                     29
+#define AIPS_PACRH_WP0_WIDTH                     1
+#define AIPS_PACRH_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP0_SHIFT))&AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_SP0_MASK                      0x40000000u
+#define AIPS_PACRH_SP0_SHIFT                     30
+#define AIPS_PACRH_SP0_WIDTH                     1
+#define AIPS_PACRH_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP0_SHIFT))&AIPS_PACRH_SP0_MASK)
+/* PACRI Bit Fields */
+#define AIPS_PACRI_TP7_MASK                      0x1u
+#define AIPS_PACRI_TP7_SHIFT                     0
+#define AIPS_PACRI_TP7_WIDTH                     1
+#define AIPS_PACRI_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP7_SHIFT))&AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_WP7_MASK                      0x2u
+#define AIPS_PACRI_WP7_SHIFT                     1
+#define AIPS_PACRI_WP7_WIDTH                     1
+#define AIPS_PACRI_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP7_SHIFT))&AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_SP7_MASK                      0x4u
+#define AIPS_PACRI_SP7_SHIFT                     2
+#define AIPS_PACRI_SP7_WIDTH                     1
+#define AIPS_PACRI_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP7_SHIFT))&AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_TP6_MASK                      0x10u
+#define AIPS_PACRI_TP6_SHIFT                     4
+#define AIPS_PACRI_TP6_WIDTH                     1
+#define AIPS_PACRI_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP6_SHIFT))&AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_WP6_MASK                      0x20u
+#define AIPS_PACRI_WP6_SHIFT                     5
+#define AIPS_PACRI_WP6_WIDTH                     1
+#define AIPS_PACRI_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP6_SHIFT))&AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_SP6_MASK                      0x40u
+#define AIPS_PACRI_SP6_SHIFT                     6
+#define AIPS_PACRI_SP6_WIDTH                     1
+#define AIPS_PACRI_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP6_SHIFT))&AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_TP5_MASK                      0x100u
+#define AIPS_PACRI_TP5_SHIFT                     8
+#define AIPS_PACRI_TP5_WIDTH                     1
+#define AIPS_PACRI_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP5_SHIFT))&AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_WP5_MASK                      0x200u
+#define AIPS_PACRI_WP5_SHIFT                     9
+#define AIPS_PACRI_WP5_WIDTH                     1
+#define AIPS_PACRI_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP5_SHIFT))&AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_SP5_MASK                      0x400u
+#define AIPS_PACRI_SP5_SHIFT                     10
+#define AIPS_PACRI_SP5_WIDTH                     1
+#define AIPS_PACRI_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP5_SHIFT))&AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_TP4_MASK                      0x1000u
+#define AIPS_PACRI_TP4_SHIFT                     12
+#define AIPS_PACRI_TP4_WIDTH                     1
+#define AIPS_PACRI_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP4_SHIFT))&AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_WP4_MASK                      0x2000u
+#define AIPS_PACRI_WP4_SHIFT                     13
+#define AIPS_PACRI_WP4_WIDTH                     1
+#define AIPS_PACRI_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP4_SHIFT))&AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_SP4_MASK                      0x4000u
+#define AIPS_PACRI_SP4_SHIFT                     14
+#define AIPS_PACRI_SP4_WIDTH                     1
+#define AIPS_PACRI_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP4_SHIFT))&AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_TP3_MASK                      0x10000u
+#define AIPS_PACRI_TP3_SHIFT                     16
+#define AIPS_PACRI_TP3_WIDTH                     1
+#define AIPS_PACRI_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP3_SHIFT))&AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_WP3_MASK                      0x20000u
+#define AIPS_PACRI_WP3_SHIFT                     17
+#define AIPS_PACRI_WP3_WIDTH                     1
+#define AIPS_PACRI_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP3_SHIFT))&AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_SP3_MASK                      0x40000u
+#define AIPS_PACRI_SP3_SHIFT                     18
+#define AIPS_PACRI_SP3_WIDTH                     1
+#define AIPS_PACRI_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP3_SHIFT))&AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_TP2_MASK                      0x100000u
+#define AIPS_PACRI_TP2_SHIFT                     20
+#define AIPS_PACRI_TP2_WIDTH                     1
+#define AIPS_PACRI_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP2_SHIFT))&AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_WP2_MASK                      0x200000u
+#define AIPS_PACRI_WP2_SHIFT                     21
+#define AIPS_PACRI_WP2_WIDTH                     1
+#define AIPS_PACRI_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP2_SHIFT))&AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_SP2_MASK                      0x400000u
+#define AIPS_PACRI_SP2_SHIFT                     22
+#define AIPS_PACRI_SP2_WIDTH                     1
+#define AIPS_PACRI_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP2_SHIFT))&AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_TP1_MASK                      0x1000000u
+#define AIPS_PACRI_TP1_SHIFT                     24
+#define AIPS_PACRI_TP1_WIDTH                     1
+#define AIPS_PACRI_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP1_SHIFT))&AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_WP1_MASK                      0x2000000u
+#define AIPS_PACRI_WP1_SHIFT                     25
+#define AIPS_PACRI_WP1_WIDTH                     1
+#define AIPS_PACRI_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP1_SHIFT))&AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_SP1_MASK                      0x4000000u
+#define AIPS_PACRI_SP1_SHIFT                     26
+#define AIPS_PACRI_SP1_WIDTH                     1
+#define AIPS_PACRI_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP1_SHIFT))&AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_TP0_MASK                      0x10000000u
+#define AIPS_PACRI_TP0_SHIFT                     28
+#define AIPS_PACRI_TP0_WIDTH                     1
+#define AIPS_PACRI_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP0_SHIFT))&AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_WP0_MASK                      0x20000000u
+#define AIPS_PACRI_WP0_SHIFT                     29
+#define AIPS_PACRI_WP0_WIDTH                     1
+#define AIPS_PACRI_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP0_SHIFT))&AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_SP0_MASK                      0x40000000u
+#define AIPS_PACRI_SP0_SHIFT                     30
+#define AIPS_PACRI_SP0_WIDTH                     1
+#define AIPS_PACRI_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP0_SHIFT))&AIPS_PACRI_SP0_MASK)
+/* PACRJ Bit Fields */
+#define AIPS_PACRJ_TP7_MASK                      0x1u
+#define AIPS_PACRJ_TP7_SHIFT                     0
+#define AIPS_PACRJ_TP7_WIDTH                     1
+#define AIPS_PACRJ_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP7_SHIFT))&AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_WP7_MASK                      0x2u
+#define AIPS_PACRJ_WP7_SHIFT                     1
+#define AIPS_PACRJ_WP7_WIDTH                     1
+#define AIPS_PACRJ_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP7_SHIFT))&AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_SP7_MASK                      0x4u
+#define AIPS_PACRJ_SP7_SHIFT                     2
+#define AIPS_PACRJ_SP7_WIDTH                     1
+#define AIPS_PACRJ_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP7_SHIFT))&AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_TP6_MASK                      0x10u
+#define AIPS_PACRJ_TP6_SHIFT                     4
+#define AIPS_PACRJ_TP6_WIDTH                     1
+#define AIPS_PACRJ_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP6_SHIFT))&AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_WP6_MASK                      0x20u
+#define AIPS_PACRJ_WP6_SHIFT                     5
+#define AIPS_PACRJ_WP6_WIDTH                     1
+#define AIPS_PACRJ_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP6_SHIFT))&AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_SP6_MASK                      0x40u
+#define AIPS_PACRJ_SP6_SHIFT                     6
+#define AIPS_PACRJ_SP6_WIDTH                     1
+#define AIPS_PACRJ_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP6_SHIFT))&AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_TP5_MASK                      0x100u
+#define AIPS_PACRJ_TP5_SHIFT                     8
+#define AIPS_PACRJ_TP5_WIDTH                     1
+#define AIPS_PACRJ_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP5_SHIFT))&AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_WP5_MASK                      0x200u
+#define AIPS_PACRJ_WP5_SHIFT                     9
+#define AIPS_PACRJ_WP5_WIDTH                     1
+#define AIPS_PACRJ_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP5_SHIFT))&AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_SP5_MASK                      0x400u
+#define AIPS_PACRJ_SP5_SHIFT                     10
+#define AIPS_PACRJ_SP5_WIDTH                     1
+#define AIPS_PACRJ_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP5_SHIFT))&AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_TP4_MASK                      0x1000u
+#define AIPS_PACRJ_TP4_SHIFT                     12
+#define AIPS_PACRJ_TP4_WIDTH                     1
+#define AIPS_PACRJ_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP4_SHIFT))&AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_WP4_MASK                      0x2000u
+#define AIPS_PACRJ_WP4_SHIFT                     13
+#define AIPS_PACRJ_WP4_WIDTH                     1
+#define AIPS_PACRJ_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP4_SHIFT))&AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_SP4_MASK                      0x4000u
+#define AIPS_PACRJ_SP4_SHIFT                     14
+#define AIPS_PACRJ_SP4_WIDTH                     1
+#define AIPS_PACRJ_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP4_SHIFT))&AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_TP3_MASK                      0x10000u
+#define AIPS_PACRJ_TP3_SHIFT                     16
+#define AIPS_PACRJ_TP3_WIDTH                     1
+#define AIPS_PACRJ_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP3_SHIFT))&AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_WP3_MASK                      0x20000u
+#define AIPS_PACRJ_WP3_SHIFT                     17
+#define AIPS_PACRJ_WP3_WIDTH                     1
+#define AIPS_PACRJ_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP3_SHIFT))&AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_SP3_MASK                      0x40000u
+#define AIPS_PACRJ_SP3_SHIFT                     18
+#define AIPS_PACRJ_SP3_WIDTH                     1
+#define AIPS_PACRJ_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP3_SHIFT))&AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_TP2_MASK                      0x100000u
+#define AIPS_PACRJ_TP2_SHIFT                     20
+#define AIPS_PACRJ_TP2_WIDTH                     1
+#define AIPS_PACRJ_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP2_SHIFT))&AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_WP2_MASK                      0x200000u
+#define AIPS_PACRJ_WP2_SHIFT                     21
+#define AIPS_PACRJ_WP2_WIDTH                     1
+#define AIPS_PACRJ_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP2_SHIFT))&AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_SP2_MASK                      0x400000u
+#define AIPS_PACRJ_SP2_SHIFT                     22
+#define AIPS_PACRJ_SP2_WIDTH                     1
+#define AIPS_PACRJ_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP2_SHIFT))&AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_TP1_MASK                      0x1000000u
+#define AIPS_PACRJ_TP1_SHIFT                     24
+#define AIPS_PACRJ_TP1_WIDTH                     1
+#define AIPS_PACRJ_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP1_SHIFT))&AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_WP1_MASK                      0x2000000u
+#define AIPS_PACRJ_WP1_SHIFT                     25
+#define AIPS_PACRJ_WP1_WIDTH                     1
+#define AIPS_PACRJ_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP1_SHIFT))&AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_SP1_MASK                      0x4000000u
+#define AIPS_PACRJ_SP1_SHIFT                     26
+#define AIPS_PACRJ_SP1_WIDTH                     1
+#define AIPS_PACRJ_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP1_SHIFT))&AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_TP0_MASK                      0x10000000u
+#define AIPS_PACRJ_TP0_SHIFT                     28
+#define AIPS_PACRJ_TP0_WIDTH                     1
+#define AIPS_PACRJ_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP0_SHIFT))&AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_WP0_MASK                      0x20000000u
+#define AIPS_PACRJ_WP0_SHIFT                     29
+#define AIPS_PACRJ_WP0_WIDTH                     1
+#define AIPS_PACRJ_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP0_SHIFT))&AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_SP0_MASK                      0x40000000u
+#define AIPS_PACRJ_SP0_SHIFT                     30
+#define AIPS_PACRJ_SP0_WIDTH                     1
+#define AIPS_PACRJ_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP0_SHIFT))&AIPS_PACRJ_SP0_MASK)
+/* PACRK Bit Fields */
+#define AIPS_PACRK_TP7_MASK                      0x1u
+#define AIPS_PACRK_TP7_SHIFT                     0
+#define AIPS_PACRK_TP7_WIDTH                     1
+#define AIPS_PACRK_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP7_SHIFT))&AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_WP7_MASK                      0x2u
+#define AIPS_PACRK_WP7_SHIFT                     1
+#define AIPS_PACRK_WP7_WIDTH                     1
+#define AIPS_PACRK_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP7_SHIFT))&AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_SP7_MASK                      0x4u
+#define AIPS_PACRK_SP7_SHIFT                     2
+#define AIPS_PACRK_SP7_WIDTH                     1
+#define AIPS_PACRK_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP7_SHIFT))&AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_TP6_MASK                      0x10u
+#define AIPS_PACRK_TP6_SHIFT                     4
+#define AIPS_PACRK_TP6_WIDTH                     1
+#define AIPS_PACRK_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP6_SHIFT))&AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_WP6_MASK                      0x20u
+#define AIPS_PACRK_WP6_SHIFT                     5
+#define AIPS_PACRK_WP6_WIDTH                     1
+#define AIPS_PACRK_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP6_SHIFT))&AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_SP6_MASK                      0x40u
+#define AIPS_PACRK_SP6_SHIFT                     6
+#define AIPS_PACRK_SP6_WIDTH                     1
+#define AIPS_PACRK_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP6_SHIFT))&AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_TP5_MASK                      0x100u
+#define AIPS_PACRK_TP5_SHIFT                     8
+#define AIPS_PACRK_TP5_WIDTH                     1
+#define AIPS_PACRK_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP5_SHIFT))&AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_WP5_MASK                      0x200u
+#define AIPS_PACRK_WP5_SHIFT                     9
+#define AIPS_PACRK_WP5_WIDTH                     1
+#define AIPS_PACRK_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP5_SHIFT))&AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_SP5_MASK                      0x400u
+#define AIPS_PACRK_SP5_SHIFT                     10
+#define AIPS_PACRK_SP5_WIDTH                     1
+#define AIPS_PACRK_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP5_SHIFT))&AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_TP4_MASK                      0x1000u
+#define AIPS_PACRK_TP4_SHIFT                     12
+#define AIPS_PACRK_TP4_WIDTH                     1
+#define AIPS_PACRK_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP4_SHIFT))&AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_WP4_MASK                      0x2000u
+#define AIPS_PACRK_WP4_SHIFT                     13
+#define AIPS_PACRK_WP4_WIDTH                     1
+#define AIPS_PACRK_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP4_SHIFT))&AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_SP4_MASK                      0x4000u
+#define AIPS_PACRK_SP4_SHIFT                     14
+#define AIPS_PACRK_SP4_WIDTH                     1
+#define AIPS_PACRK_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP4_SHIFT))&AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_TP3_MASK                      0x10000u
+#define AIPS_PACRK_TP3_SHIFT                     16
+#define AIPS_PACRK_TP3_WIDTH                     1
+#define AIPS_PACRK_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP3_SHIFT))&AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_WP3_MASK                      0x20000u
+#define AIPS_PACRK_WP3_SHIFT                     17
+#define AIPS_PACRK_WP3_WIDTH                     1
+#define AIPS_PACRK_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP3_SHIFT))&AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_SP3_MASK                      0x40000u
+#define AIPS_PACRK_SP3_SHIFT                     18
+#define AIPS_PACRK_SP3_WIDTH                     1
+#define AIPS_PACRK_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP3_SHIFT))&AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_TP2_MASK                      0x100000u
+#define AIPS_PACRK_TP2_SHIFT                     20
+#define AIPS_PACRK_TP2_WIDTH                     1
+#define AIPS_PACRK_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP2_SHIFT))&AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_WP2_MASK                      0x200000u
+#define AIPS_PACRK_WP2_SHIFT                     21
+#define AIPS_PACRK_WP2_WIDTH                     1
+#define AIPS_PACRK_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP2_SHIFT))&AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_SP2_MASK                      0x400000u
+#define AIPS_PACRK_SP2_SHIFT                     22
+#define AIPS_PACRK_SP2_WIDTH                     1
+#define AIPS_PACRK_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP2_SHIFT))&AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_TP1_MASK                      0x1000000u
+#define AIPS_PACRK_TP1_SHIFT                     24
+#define AIPS_PACRK_TP1_WIDTH                     1
+#define AIPS_PACRK_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP1_SHIFT))&AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_WP1_MASK                      0x2000000u
+#define AIPS_PACRK_WP1_SHIFT                     25
+#define AIPS_PACRK_WP1_WIDTH                     1
+#define AIPS_PACRK_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP1_SHIFT))&AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_SP1_MASK                      0x4000000u
+#define AIPS_PACRK_SP1_SHIFT                     26
+#define AIPS_PACRK_SP1_WIDTH                     1
+#define AIPS_PACRK_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP1_SHIFT))&AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_TP0_MASK                      0x10000000u
+#define AIPS_PACRK_TP0_SHIFT                     28
+#define AIPS_PACRK_TP0_WIDTH                     1
+#define AIPS_PACRK_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP0_SHIFT))&AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_WP0_MASK                      0x20000000u
+#define AIPS_PACRK_WP0_SHIFT                     29
+#define AIPS_PACRK_WP0_WIDTH                     1
+#define AIPS_PACRK_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP0_SHIFT))&AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_SP0_MASK                      0x40000000u
+#define AIPS_PACRK_SP0_SHIFT                     30
+#define AIPS_PACRK_SP0_WIDTH                     1
+#define AIPS_PACRK_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP0_SHIFT))&AIPS_PACRK_SP0_MASK)
+/* PACRL Bit Fields */
+#define AIPS_PACRL_TP7_MASK                      0x1u
+#define AIPS_PACRL_TP7_SHIFT                     0
+#define AIPS_PACRL_TP7_WIDTH                     1
+#define AIPS_PACRL_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP7_SHIFT))&AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_WP7_MASK                      0x2u
+#define AIPS_PACRL_WP7_SHIFT                     1
+#define AIPS_PACRL_WP7_WIDTH                     1
+#define AIPS_PACRL_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP7_SHIFT))&AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_SP7_MASK                      0x4u
+#define AIPS_PACRL_SP7_SHIFT                     2
+#define AIPS_PACRL_SP7_WIDTH                     1
+#define AIPS_PACRL_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP7_SHIFT))&AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_TP6_MASK                      0x10u
+#define AIPS_PACRL_TP6_SHIFT                     4
+#define AIPS_PACRL_TP6_WIDTH                     1
+#define AIPS_PACRL_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP6_SHIFT))&AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_WP6_MASK                      0x20u
+#define AIPS_PACRL_WP6_SHIFT                     5
+#define AIPS_PACRL_WP6_WIDTH                     1
+#define AIPS_PACRL_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP6_SHIFT))&AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_SP6_MASK                      0x40u
+#define AIPS_PACRL_SP6_SHIFT                     6
+#define AIPS_PACRL_SP6_WIDTH                     1
+#define AIPS_PACRL_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP6_SHIFT))&AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_TP5_MASK                      0x100u
+#define AIPS_PACRL_TP5_SHIFT                     8
+#define AIPS_PACRL_TP5_WIDTH                     1
+#define AIPS_PACRL_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP5_SHIFT))&AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_WP5_MASK                      0x200u
+#define AIPS_PACRL_WP5_SHIFT                     9
+#define AIPS_PACRL_WP5_WIDTH                     1
+#define AIPS_PACRL_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP5_SHIFT))&AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_SP5_MASK                      0x400u
+#define AIPS_PACRL_SP5_SHIFT                     10
+#define AIPS_PACRL_SP5_WIDTH                     1
+#define AIPS_PACRL_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP5_SHIFT))&AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_TP4_MASK                      0x1000u
+#define AIPS_PACRL_TP4_SHIFT                     12
+#define AIPS_PACRL_TP4_WIDTH                     1
+#define AIPS_PACRL_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP4_SHIFT))&AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_WP4_MASK                      0x2000u
+#define AIPS_PACRL_WP4_SHIFT                     13
+#define AIPS_PACRL_WP4_WIDTH                     1
+#define AIPS_PACRL_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP4_SHIFT))&AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_SP4_MASK                      0x4000u
+#define AIPS_PACRL_SP4_SHIFT                     14
+#define AIPS_PACRL_SP4_WIDTH                     1
+#define AIPS_PACRL_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP4_SHIFT))&AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_TP3_MASK                      0x10000u
+#define AIPS_PACRL_TP3_SHIFT                     16
+#define AIPS_PACRL_TP3_WIDTH                     1
+#define AIPS_PACRL_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP3_SHIFT))&AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_WP3_MASK                      0x20000u
+#define AIPS_PACRL_WP3_SHIFT                     17
+#define AIPS_PACRL_WP3_WIDTH                     1
+#define AIPS_PACRL_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP3_SHIFT))&AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_SP3_MASK                      0x40000u
+#define AIPS_PACRL_SP3_SHIFT                     18
+#define AIPS_PACRL_SP3_WIDTH                     1
+#define AIPS_PACRL_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP3_SHIFT))&AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_TP2_MASK                      0x100000u
+#define AIPS_PACRL_TP2_SHIFT                     20
+#define AIPS_PACRL_TP2_WIDTH                     1
+#define AIPS_PACRL_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP2_SHIFT))&AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_WP2_MASK                      0x200000u
+#define AIPS_PACRL_WP2_SHIFT                     21
+#define AIPS_PACRL_WP2_WIDTH                     1
+#define AIPS_PACRL_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP2_SHIFT))&AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_SP2_MASK                      0x400000u
+#define AIPS_PACRL_SP2_SHIFT                     22
+#define AIPS_PACRL_SP2_WIDTH                     1
+#define AIPS_PACRL_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP2_SHIFT))&AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_TP1_MASK                      0x1000000u
+#define AIPS_PACRL_TP1_SHIFT                     24
+#define AIPS_PACRL_TP1_WIDTH                     1
+#define AIPS_PACRL_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP1_SHIFT))&AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_WP1_MASK                      0x2000000u
+#define AIPS_PACRL_WP1_SHIFT                     25
+#define AIPS_PACRL_WP1_WIDTH                     1
+#define AIPS_PACRL_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP1_SHIFT))&AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_SP1_MASK                      0x4000000u
+#define AIPS_PACRL_SP1_SHIFT                     26
+#define AIPS_PACRL_SP1_WIDTH                     1
+#define AIPS_PACRL_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP1_SHIFT))&AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_TP0_MASK                      0x10000000u
+#define AIPS_PACRL_TP0_SHIFT                     28
+#define AIPS_PACRL_TP0_WIDTH                     1
+#define AIPS_PACRL_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP0_SHIFT))&AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_WP0_MASK                      0x20000000u
+#define AIPS_PACRL_WP0_SHIFT                     29
+#define AIPS_PACRL_WP0_WIDTH                     1
+#define AIPS_PACRL_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP0_SHIFT))&AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_SP0_MASK                      0x40000000u
+#define AIPS_PACRL_SP0_SHIFT                     30
+#define AIPS_PACRL_SP0_WIDTH                     1
+#define AIPS_PACRL_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP0_SHIFT))&AIPS_PACRL_SP0_MASK)
+/* PACRM Bit Fields */
+#define AIPS_PACRM_TP7_MASK                      0x1u
+#define AIPS_PACRM_TP7_SHIFT                     0
+#define AIPS_PACRM_TP7_WIDTH                     1
+#define AIPS_PACRM_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP7_SHIFT))&AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_WP7_MASK                      0x2u
+#define AIPS_PACRM_WP7_SHIFT                     1
+#define AIPS_PACRM_WP7_WIDTH                     1
+#define AIPS_PACRM_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP7_SHIFT))&AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_SP7_MASK                      0x4u
+#define AIPS_PACRM_SP7_SHIFT                     2
+#define AIPS_PACRM_SP7_WIDTH                     1
+#define AIPS_PACRM_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP7_SHIFT))&AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_TP6_MASK                      0x10u
+#define AIPS_PACRM_TP6_SHIFT                     4
+#define AIPS_PACRM_TP6_WIDTH                     1
+#define AIPS_PACRM_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP6_SHIFT))&AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_WP6_MASK                      0x20u
+#define AIPS_PACRM_WP6_SHIFT                     5
+#define AIPS_PACRM_WP6_WIDTH                     1
+#define AIPS_PACRM_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP6_SHIFT))&AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_SP6_MASK                      0x40u
+#define AIPS_PACRM_SP6_SHIFT                     6
+#define AIPS_PACRM_SP6_WIDTH                     1
+#define AIPS_PACRM_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP6_SHIFT))&AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_TP5_MASK                      0x100u
+#define AIPS_PACRM_TP5_SHIFT                     8
+#define AIPS_PACRM_TP5_WIDTH                     1
+#define AIPS_PACRM_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP5_SHIFT))&AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_WP5_MASK                      0x200u
+#define AIPS_PACRM_WP5_SHIFT                     9
+#define AIPS_PACRM_WP5_WIDTH                     1
+#define AIPS_PACRM_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP5_SHIFT))&AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_SP5_MASK                      0x400u
+#define AIPS_PACRM_SP5_SHIFT                     10
+#define AIPS_PACRM_SP5_WIDTH                     1
+#define AIPS_PACRM_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP5_SHIFT))&AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_TP4_MASK                      0x1000u
+#define AIPS_PACRM_TP4_SHIFT                     12
+#define AIPS_PACRM_TP4_WIDTH                     1
+#define AIPS_PACRM_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP4_SHIFT))&AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_WP4_MASK                      0x2000u
+#define AIPS_PACRM_WP4_SHIFT                     13
+#define AIPS_PACRM_WP4_WIDTH                     1
+#define AIPS_PACRM_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP4_SHIFT))&AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_SP4_MASK                      0x4000u
+#define AIPS_PACRM_SP4_SHIFT                     14
+#define AIPS_PACRM_SP4_WIDTH                     1
+#define AIPS_PACRM_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP4_SHIFT))&AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_TP3_MASK                      0x10000u
+#define AIPS_PACRM_TP3_SHIFT                     16
+#define AIPS_PACRM_TP3_WIDTH                     1
+#define AIPS_PACRM_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP3_SHIFT))&AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_WP3_MASK                      0x20000u
+#define AIPS_PACRM_WP3_SHIFT                     17
+#define AIPS_PACRM_WP3_WIDTH                     1
+#define AIPS_PACRM_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP3_SHIFT))&AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_SP3_MASK                      0x40000u
+#define AIPS_PACRM_SP3_SHIFT                     18
+#define AIPS_PACRM_SP3_WIDTH                     1
+#define AIPS_PACRM_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP3_SHIFT))&AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_TP2_MASK                      0x100000u
+#define AIPS_PACRM_TP2_SHIFT                     20
+#define AIPS_PACRM_TP2_WIDTH                     1
+#define AIPS_PACRM_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP2_SHIFT))&AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_WP2_MASK                      0x200000u
+#define AIPS_PACRM_WP2_SHIFT                     21
+#define AIPS_PACRM_WP2_WIDTH                     1
+#define AIPS_PACRM_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP2_SHIFT))&AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_SP2_MASK                      0x400000u
+#define AIPS_PACRM_SP2_SHIFT                     22
+#define AIPS_PACRM_SP2_WIDTH                     1
+#define AIPS_PACRM_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP2_SHIFT))&AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_TP1_MASK                      0x1000000u
+#define AIPS_PACRM_TP1_SHIFT                     24
+#define AIPS_PACRM_TP1_WIDTH                     1
+#define AIPS_PACRM_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP1_SHIFT))&AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_WP1_MASK                      0x2000000u
+#define AIPS_PACRM_WP1_SHIFT                     25
+#define AIPS_PACRM_WP1_WIDTH                     1
+#define AIPS_PACRM_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP1_SHIFT))&AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_SP1_MASK                      0x4000000u
+#define AIPS_PACRM_SP1_SHIFT                     26
+#define AIPS_PACRM_SP1_WIDTH                     1
+#define AIPS_PACRM_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP1_SHIFT))&AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_TP0_MASK                      0x10000000u
+#define AIPS_PACRM_TP0_SHIFT                     28
+#define AIPS_PACRM_TP0_WIDTH                     1
+#define AIPS_PACRM_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP0_SHIFT))&AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_WP0_MASK                      0x20000000u
+#define AIPS_PACRM_WP0_SHIFT                     29
+#define AIPS_PACRM_WP0_WIDTH                     1
+#define AIPS_PACRM_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP0_SHIFT))&AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_SP0_MASK                      0x40000000u
+#define AIPS_PACRM_SP0_SHIFT                     30
+#define AIPS_PACRM_SP0_WIDTH                     1
+#define AIPS_PACRM_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP0_SHIFT))&AIPS_PACRM_SP0_MASK)
+/* PACRN Bit Fields */
+#define AIPS_PACRN_TP7_MASK                      0x1u
+#define AIPS_PACRN_TP7_SHIFT                     0
+#define AIPS_PACRN_TP7_WIDTH                     1
+#define AIPS_PACRN_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP7_SHIFT))&AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_WP7_MASK                      0x2u
+#define AIPS_PACRN_WP7_SHIFT                     1
+#define AIPS_PACRN_WP7_WIDTH                     1
+#define AIPS_PACRN_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP7_SHIFT))&AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_SP7_MASK                      0x4u
+#define AIPS_PACRN_SP7_SHIFT                     2
+#define AIPS_PACRN_SP7_WIDTH                     1
+#define AIPS_PACRN_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP7_SHIFT))&AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_TP6_MASK                      0x10u
+#define AIPS_PACRN_TP6_SHIFT                     4
+#define AIPS_PACRN_TP6_WIDTH                     1
+#define AIPS_PACRN_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP6_SHIFT))&AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_WP6_MASK                      0x20u
+#define AIPS_PACRN_WP6_SHIFT                     5
+#define AIPS_PACRN_WP6_WIDTH                     1
+#define AIPS_PACRN_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP6_SHIFT))&AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_SP6_MASK                      0x40u
+#define AIPS_PACRN_SP6_SHIFT                     6
+#define AIPS_PACRN_SP6_WIDTH                     1
+#define AIPS_PACRN_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP6_SHIFT))&AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_TP5_MASK                      0x100u
+#define AIPS_PACRN_TP5_SHIFT                     8
+#define AIPS_PACRN_TP5_WIDTH                     1
+#define AIPS_PACRN_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP5_SHIFT))&AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_WP5_MASK                      0x200u
+#define AIPS_PACRN_WP5_SHIFT                     9
+#define AIPS_PACRN_WP5_WIDTH                     1
+#define AIPS_PACRN_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP5_SHIFT))&AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_SP5_MASK                      0x400u
+#define AIPS_PACRN_SP5_SHIFT                     10
+#define AIPS_PACRN_SP5_WIDTH                     1
+#define AIPS_PACRN_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP5_SHIFT))&AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_TP4_MASK                      0x1000u
+#define AIPS_PACRN_TP4_SHIFT                     12
+#define AIPS_PACRN_TP4_WIDTH                     1
+#define AIPS_PACRN_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP4_SHIFT))&AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_WP4_MASK                      0x2000u
+#define AIPS_PACRN_WP4_SHIFT                     13
+#define AIPS_PACRN_WP4_WIDTH                     1
+#define AIPS_PACRN_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP4_SHIFT))&AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_SP4_MASK                      0x4000u
+#define AIPS_PACRN_SP4_SHIFT                     14
+#define AIPS_PACRN_SP4_WIDTH                     1
+#define AIPS_PACRN_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP4_SHIFT))&AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_TP3_MASK                      0x10000u
+#define AIPS_PACRN_TP3_SHIFT                     16
+#define AIPS_PACRN_TP3_WIDTH                     1
+#define AIPS_PACRN_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP3_SHIFT))&AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_WP3_MASK                      0x20000u
+#define AIPS_PACRN_WP3_SHIFT                     17
+#define AIPS_PACRN_WP3_WIDTH                     1
+#define AIPS_PACRN_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP3_SHIFT))&AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_SP3_MASK                      0x40000u
+#define AIPS_PACRN_SP3_SHIFT                     18
+#define AIPS_PACRN_SP3_WIDTH                     1
+#define AIPS_PACRN_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP3_SHIFT))&AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_TP2_MASK                      0x100000u
+#define AIPS_PACRN_TP2_SHIFT                     20
+#define AIPS_PACRN_TP2_WIDTH                     1
+#define AIPS_PACRN_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP2_SHIFT))&AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_WP2_MASK                      0x200000u
+#define AIPS_PACRN_WP2_SHIFT                     21
+#define AIPS_PACRN_WP2_WIDTH                     1
+#define AIPS_PACRN_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP2_SHIFT))&AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_SP2_MASK                      0x400000u
+#define AIPS_PACRN_SP2_SHIFT                     22
+#define AIPS_PACRN_SP2_WIDTH                     1
+#define AIPS_PACRN_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP2_SHIFT))&AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_TP1_MASK                      0x1000000u
+#define AIPS_PACRN_TP1_SHIFT                     24
+#define AIPS_PACRN_TP1_WIDTH                     1
+#define AIPS_PACRN_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP1_SHIFT))&AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_WP1_MASK                      0x2000000u
+#define AIPS_PACRN_WP1_SHIFT                     25
+#define AIPS_PACRN_WP1_WIDTH                     1
+#define AIPS_PACRN_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP1_SHIFT))&AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_SP1_MASK                      0x4000000u
+#define AIPS_PACRN_SP1_SHIFT                     26
+#define AIPS_PACRN_SP1_WIDTH                     1
+#define AIPS_PACRN_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP1_SHIFT))&AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_TP0_MASK                      0x10000000u
+#define AIPS_PACRN_TP0_SHIFT                     28
+#define AIPS_PACRN_TP0_WIDTH                     1
+#define AIPS_PACRN_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP0_SHIFT))&AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_WP0_MASK                      0x20000000u
+#define AIPS_PACRN_WP0_SHIFT                     29
+#define AIPS_PACRN_WP0_WIDTH                     1
+#define AIPS_PACRN_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP0_SHIFT))&AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_SP0_MASK                      0x40000000u
+#define AIPS_PACRN_SP0_SHIFT                     30
+#define AIPS_PACRN_SP0_WIDTH                     1
+#define AIPS_PACRN_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP0_SHIFT))&AIPS_PACRN_SP0_MASK)
+/* PACRO Bit Fields */
+#define AIPS_PACRO_TP7_MASK                      0x1u
+#define AIPS_PACRO_TP7_SHIFT                     0
+#define AIPS_PACRO_TP7_WIDTH                     1
+#define AIPS_PACRO_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP7_SHIFT))&AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_WP7_MASK                      0x2u
+#define AIPS_PACRO_WP7_SHIFT                     1
+#define AIPS_PACRO_WP7_WIDTH                     1
+#define AIPS_PACRO_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP7_SHIFT))&AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_SP7_MASK                      0x4u
+#define AIPS_PACRO_SP7_SHIFT                     2
+#define AIPS_PACRO_SP7_WIDTH                     1
+#define AIPS_PACRO_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP7_SHIFT))&AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_TP6_MASK                      0x10u
+#define AIPS_PACRO_TP6_SHIFT                     4
+#define AIPS_PACRO_TP6_WIDTH                     1
+#define AIPS_PACRO_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP6_SHIFT))&AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_WP6_MASK                      0x20u
+#define AIPS_PACRO_WP6_SHIFT                     5
+#define AIPS_PACRO_WP6_WIDTH                     1
+#define AIPS_PACRO_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP6_SHIFT))&AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_SP6_MASK                      0x40u
+#define AIPS_PACRO_SP6_SHIFT                     6
+#define AIPS_PACRO_SP6_WIDTH                     1
+#define AIPS_PACRO_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP6_SHIFT))&AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_TP5_MASK                      0x100u
+#define AIPS_PACRO_TP5_SHIFT                     8
+#define AIPS_PACRO_TP5_WIDTH                     1
+#define AIPS_PACRO_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP5_SHIFT))&AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_WP5_MASK                      0x200u
+#define AIPS_PACRO_WP5_SHIFT                     9
+#define AIPS_PACRO_WP5_WIDTH                     1
+#define AIPS_PACRO_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP5_SHIFT))&AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_SP5_MASK                      0x400u
+#define AIPS_PACRO_SP5_SHIFT                     10
+#define AIPS_PACRO_SP5_WIDTH                     1
+#define AIPS_PACRO_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP5_SHIFT))&AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_TP4_MASK                      0x1000u
+#define AIPS_PACRO_TP4_SHIFT                     12
+#define AIPS_PACRO_TP4_WIDTH                     1
+#define AIPS_PACRO_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP4_SHIFT))&AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_WP4_MASK                      0x2000u
+#define AIPS_PACRO_WP4_SHIFT                     13
+#define AIPS_PACRO_WP4_WIDTH                     1
+#define AIPS_PACRO_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP4_SHIFT))&AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_SP4_MASK                      0x4000u
+#define AIPS_PACRO_SP4_SHIFT                     14
+#define AIPS_PACRO_SP4_WIDTH                     1
+#define AIPS_PACRO_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP4_SHIFT))&AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_TP3_MASK                      0x10000u
+#define AIPS_PACRO_TP3_SHIFT                     16
+#define AIPS_PACRO_TP3_WIDTH                     1
+#define AIPS_PACRO_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP3_SHIFT))&AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_WP3_MASK                      0x20000u
+#define AIPS_PACRO_WP3_SHIFT                     17
+#define AIPS_PACRO_WP3_WIDTH                     1
+#define AIPS_PACRO_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP3_SHIFT))&AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_SP3_MASK                      0x40000u
+#define AIPS_PACRO_SP3_SHIFT                     18
+#define AIPS_PACRO_SP3_WIDTH                     1
+#define AIPS_PACRO_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP3_SHIFT))&AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_TP2_MASK                      0x100000u
+#define AIPS_PACRO_TP2_SHIFT                     20
+#define AIPS_PACRO_TP2_WIDTH                     1
+#define AIPS_PACRO_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP2_SHIFT))&AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_WP2_MASK                      0x200000u
+#define AIPS_PACRO_WP2_SHIFT                     21
+#define AIPS_PACRO_WP2_WIDTH                     1
+#define AIPS_PACRO_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP2_SHIFT))&AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_SP2_MASK                      0x400000u
+#define AIPS_PACRO_SP2_SHIFT                     22
+#define AIPS_PACRO_SP2_WIDTH                     1
+#define AIPS_PACRO_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP2_SHIFT))&AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_TP1_MASK                      0x1000000u
+#define AIPS_PACRO_TP1_SHIFT                     24
+#define AIPS_PACRO_TP1_WIDTH                     1
+#define AIPS_PACRO_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP1_SHIFT))&AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_WP1_MASK                      0x2000000u
+#define AIPS_PACRO_WP1_SHIFT                     25
+#define AIPS_PACRO_WP1_WIDTH                     1
+#define AIPS_PACRO_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP1_SHIFT))&AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_SP1_MASK                      0x4000000u
+#define AIPS_PACRO_SP1_SHIFT                     26
+#define AIPS_PACRO_SP1_WIDTH                     1
+#define AIPS_PACRO_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP1_SHIFT))&AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_TP0_MASK                      0x10000000u
+#define AIPS_PACRO_TP0_SHIFT                     28
+#define AIPS_PACRO_TP0_WIDTH                     1
+#define AIPS_PACRO_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP0_SHIFT))&AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_WP0_MASK                      0x20000000u
+#define AIPS_PACRO_WP0_SHIFT                     29
+#define AIPS_PACRO_WP0_WIDTH                     1
+#define AIPS_PACRO_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP0_SHIFT))&AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_SP0_MASK                      0x40000000u
+#define AIPS_PACRO_SP0_SHIFT                     30
+#define AIPS_PACRO_SP0_WIDTH                     1
+#define AIPS_PACRO_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP0_SHIFT))&AIPS_PACRO_SP0_MASK)
+/* PACRP Bit Fields */
+#define AIPS_PACRP_TP7_MASK                      0x1u
+#define AIPS_PACRP_TP7_SHIFT                     0
+#define AIPS_PACRP_TP7_WIDTH                     1
+#define AIPS_PACRP_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP7_SHIFT))&AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_WP7_MASK                      0x2u
+#define AIPS_PACRP_WP7_SHIFT                     1
+#define AIPS_PACRP_WP7_WIDTH                     1
+#define AIPS_PACRP_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP7_SHIFT))&AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_SP7_MASK                      0x4u
+#define AIPS_PACRP_SP7_SHIFT                     2
+#define AIPS_PACRP_SP7_WIDTH                     1
+#define AIPS_PACRP_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP7_SHIFT))&AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_TP6_MASK                      0x10u
+#define AIPS_PACRP_TP6_SHIFT                     4
+#define AIPS_PACRP_TP6_WIDTH                     1
+#define AIPS_PACRP_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP6_SHIFT))&AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_WP6_MASK                      0x20u
+#define AIPS_PACRP_WP6_SHIFT                     5
+#define AIPS_PACRP_WP6_WIDTH                     1
+#define AIPS_PACRP_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP6_SHIFT))&AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_SP6_MASK                      0x40u
+#define AIPS_PACRP_SP6_SHIFT                     6
+#define AIPS_PACRP_SP6_WIDTH                     1
+#define AIPS_PACRP_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP6_SHIFT))&AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_TP5_MASK                      0x100u
+#define AIPS_PACRP_TP5_SHIFT                     8
+#define AIPS_PACRP_TP5_WIDTH                     1
+#define AIPS_PACRP_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP5_SHIFT))&AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_WP5_MASK                      0x200u
+#define AIPS_PACRP_WP5_SHIFT                     9
+#define AIPS_PACRP_WP5_WIDTH                     1
+#define AIPS_PACRP_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP5_SHIFT))&AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_SP5_MASK                      0x400u
+#define AIPS_PACRP_SP5_SHIFT                     10
+#define AIPS_PACRP_SP5_WIDTH                     1
+#define AIPS_PACRP_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP5_SHIFT))&AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_TP4_MASK                      0x1000u
+#define AIPS_PACRP_TP4_SHIFT                     12
+#define AIPS_PACRP_TP4_WIDTH                     1
+#define AIPS_PACRP_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP4_SHIFT))&AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_WP4_MASK                      0x2000u
+#define AIPS_PACRP_WP4_SHIFT                     13
+#define AIPS_PACRP_WP4_WIDTH                     1
+#define AIPS_PACRP_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP4_SHIFT))&AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_SP4_MASK                      0x4000u
+#define AIPS_PACRP_SP4_SHIFT                     14
+#define AIPS_PACRP_SP4_WIDTH                     1
+#define AIPS_PACRP_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP4_SHIFT))&AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_TP3_MASK                      0x10000u
+#define AIPS_PACRP_TP3_SHIFT                     16
+#define AIPS_PACRP_TP3_WIDTH                     1
+#define AIPS_PACRP_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP3_SHIFT))&AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_WP3_MASK                      0x20000u
+#define AIPS_PACRP_WP3_SHIFT                     17
+#define AIPS_PACRP_WP3_WIDTH                     1
+#define AIPS_PACRP_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP3_SHIFT))&AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_SP3_MASK                      0x40000u
+#define AIPS_PACRP_SP3_SHIFT                     18
+#define AIPS_PACRP_SP3_WIDTH                     1
+#define AIPS_PACRP_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP3_SHIFT))&AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_TP2_MASK                      0x100000u
+#define AIPS_PACRP_TP2_SHIFT                     20
+#define AIPS_PACRP_TP2_WIDTH                     1
+#define AIPS_PACRP_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP2_SHIFT))&AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_WP2_MASK                      0x200000u
+#define AIPS_PACRP_WP2_SHIFT                     21
+#define AIPS_PACRP_WP2_WIDTH                     1
+#define AIPS_PACRP_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP2_SHIFT))&AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_SP2_MASK                      0x400000u
+#define AIPS_PACRP_SP2_SHIFT                     22
+#define AIPS_PACRP_SP2_WIDTH                     1
+#define AIPS_PACRP_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP2_SHIFT))&AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_TP1_MASK                      0x1000000u
+#define AIPS_PACRP_TP1_SHIFT                     24
+#define AIPS_PACRP_TP1_WIDTH                     1
+#define AIPS_PACRP_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP1_SHIFT))&AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_WP1_MASK                      0x2000000u
+#define AIPS_PACRP_WP1_SHIFT                     25
+#define AIPS_PACRP_WP1_WIDTH                     1
+#define AIPS_PACRP_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP1_SHIFT))&AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_SP1_MASK                      0x4000000u
+#define AIPS_PACRP_SP1_SHIFT                     26
+#define AIPS_PACRP_SP1_WIDTH                     1
+#define AIPS_PACRP_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP1_SHIFT))&AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_TP0_MASK                      0x10000000u
+#define AIPS_PACRP_TP0_SHIFT                     28
+#define AIPS_PACRP_TP0_WIDTH                     1
+#define AIPS_PACRP_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP0_SHIFT))&AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_WP0_MASK                      0x20000000u
+#define AIPS_PACRP_WP0_SHIFT                     29
+#define AIPS_PACRP_WP0_WIDTH                     1
+#define AIPS_PACRP_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP0_SHIFT))&AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_SP0_MASK                      0x40000000u
+#define AIPS_PACRP_SP0_SHIFT                     30
+#define AIPS_PACRP_SP0_WIDTH                     1
+#define AIPS_PACRP_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP0_SHIFT))&AIPS_PACRP_SP0_MASK)
+/* PACRU Bit Fields */
+#define AIPS_PACRU_TP1_MASK                      0x1000000u
+#define AIPS_PACRU_TP1_SHIFT                     24
+#define AIPS_PACRU_TP1_WIDTH                     1
+#define AIPS_PACRU_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_TP1_SHIFT))&AIPS_PACRU_TP1_MASK)
+#define AIPS_PACRU_WP1_MASK                      0x2000000u
+#define AIPS_PACRU_WP1_SHIFT                     25
+#define AIPS_PACRU_WP1_WIDTH                     1
+#define AIPS_PACRU_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_WP1_SHIFT))&AIPS_PACRU_WP1_MASK)
+#define AIPS_PACRU_SP1_MASK                      0x4000000u
+#define AIPS_PACRU_SP1_SHIFT                     26
+#define AIPS_PACRU_SP1_WIDTH                     1
+#define AIPS_PACRU_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_SP1_SHIFT))&AIPS_PACRU_SP1_MASK)
+#define AIPS_PACRU_TP0_MASK                      0x10000000u
+#define AIPS_PACRU_TP0_SHIFT                     28
+#define AIPS_PACRU_TP0_WIDTH                     1
+#define AIPS_PACRU_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_TP0_SHIFT))&AIPS_PACRU_TP0_MASK)
+#define AIPS_PACRU_WP0_MASK                      0x20000000u
+#define AIPS_PACRU_WP0_SHIFT                     29
+#define AIPS_PACRU_WP0_WIDTH                     1
+#define AIPS_PACRU_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_WP0_SHIFT))&AIPS_PACRU_WP0_MASK)
+#define AIPS_PACRU_SP0_MASK                      0x40000000u
+#define AIPS_PACRU_SP0_SHIFT                     30
+#define AIPS_PACRU_SP0_WIDTH                     1
+#define AIPS_PACRU_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_SP0_SHIFT))&AIPS_PACRU_SP0_MASK)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base address */
+#define AIPS0_BASE                               (0x40000000u)
+/** Peripheral AIPS0 base pointer */
+#define AIPS0                                    ((AIPS_Type *)AIPS0_BASE)
+#define AIPS0_BASE_PTR                           (AIPS0)
+/** Peripheral AIPS1 base address */
+#define AIPS1_BASE                               (0x40080000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1                                    ((AIPS_Type *)AIPS1_BASE)
+#define AIPS1_BASE_PTR                           (AIPS1)
+/** Array initializer of AIPS peripheral base addresses */
+#define AIPS_BASE_ADDRS                          { AIPS0_BASE, AIPS1_BASE }
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS                           { AIPS0, AIPS1 }
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register instance definitions */
+/* AIPS0 */
+#define AIPS0_MPRA                               AIPS_MPRA_REG(AIPS0)
+#define AIPS0_PACRA                              AIPS_PACRA_REG(AIPS0)
+#define AIPS0_PACRB                              AIPS_PACRB_REG(AIPS0)
+#define AIPS0_PACRC                              AIPS_PACRC_REG(AIPS0)
+#define AIPS0_PACRD                              AIPS_PACRD_REG(AIPS0)
+#define AIPS0_PACRE                              AIPS_PACRE_REG(AIPS0)
+#define AIPS0_PACRF                              AIPS_PACRF_REG(AIPS0)
+#define AIPS0_PACRG                              AIPS_PACRG_REG(AIPS0)
+#define AIPS0_PACRH                              AIPS_PACRH_REG(AIPS0)
+#define AIPS0_PACRI                              AIPS_PACRI_REG(AIPS0)
+#define AIPS0_PACRJ                              AIPS_PACRJ_REG(AIPS0)
+#define AIPS0_PACRK                              AIPS_PACRK_REG(AIPS0)
+#define AIPS0_PACRL                              AIPS_PACRL_REG(AIPS0)
+#define AIPS0_PACRM                              AIPS_PACRM_REG(AIPS0)
+#define AIPS0_PACRN                              AIPS_PACRN_REG(AIPS0)
+#define AIPS0_PACRO                              AIPS_PACRO_REG(AIPS0)
+#define AIPS0_PACRP                              AIPS_PACRP_REG(AIPS0)
+#define AIPS0_PACRU                              AIPS_PACRU_REG(AIPS0)
+/* AIPS1 */
+#define AIPS1_MPRA                               AIPS_MPRA_REG(AIPS1)
+#define AIPS1_PACRA                              AIPS_PACRA_REG(AIPS1)
+#define AIPS1_PACRB                              AIPS_PACRB_REG(AIPS1)
+#define AIPS1_PACRC                              AIPS_PACRC_REG(AIPS1)
+#define AIPS1_PACRD                              AIPS_PACRD_REG(AIPS1)
+#define AIPS1_PACRE                              AIPS_PACRE_REG(AIPS1)
+#define AIPS1_PACRF                              AIPS_PACRF_REG(AIPS1)
+#define AIPS1_PACRG                              AIPS_PACRG_REG(AIPS1)
+#define AIPS1_PACRH                              AIPS_PACRH_REG(AIPS1)
+#define AIPS1_PACRI                              AIPS_PACRI_REG(AIPS1)
+#define AIPS1_PACRJ                              AIPS_PACRJ_REG(AIPS1)
+#define AIPS1_PACRK                              AIPS_PACRK_REG(AIPS1)
+#define AIPS1_PACRL                              AIPS_PACRL_REG(AIPS1)
+#define AIPS1_PACRM                              AIPS_PACRM_REG(AIPS1)
+#define AIPS1_PACRN                              AIPS_PACRN_REG(AIPS1)
+#define AIPS1_PACRO                              AIPS_PACRO_REG(AIPS1)
+#define AIPS1_PACRP                              AIPS_PACRP_REG(AIPS1)
+#define AIPS1_PACRU                              AIPS_PACRU_REG(AIPS1)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t PRS;                               /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CRS;                               /**< Control Register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_1[236];
+  } SLAVE[5];
+       uint8_t RESERVED_0[768];
+  __IO uint32_t MGPCR0;                            /**< Master General Purpose Control Register, offset: 0x800 */
+       uint8_t RESERVED_1[252];
+  __IO uint32_t MGPCR1;                            /**< Master General Purpose Control Register, offset: 0x900 */
+       uint8_t RESERVED_2[252];
+  __IO uint32_t MGPCR2;                            /**< Master General Purpose Control Register, offset: 0xA00 */
+       uint8_t RESERVED_3[252];
+  __IO uint32_t MGPCR3;                            /**< Master General Purpose Control Register, offset: 0xB00 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t MGPCR4;                            /**< Master General Purpose Control Register, offset: 0xC00 */
+       uint8_t RESERVED_5[252];
+  __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
+} AXBS_Type, *AXBS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register accessors */
+#define AXBS_PRS_REG(base,index)                 ((base)->SLAVE[index].PRS)
+#define AXBS_PRS_COUNT                           5
+#define AXBS_CRS_REG(base,index)                 ((base)->SLAVE[index].CRS)
+#define AXBS_CRS_COUNT                           5
+#define AXBS_MGPCR0_REG(base)                    ((base)->MGPCR0)
+#define AXBS_MGPCR1_REG(base)                    ((base)->MGPCR1)
+#define AXBS_MGPCR2_REG(base)                    ((base)->MGPCR2)
+#define AXBS_MGPCR3_REG(base)                    ((base)->MGPCR3)
+#define AXBS_MGPCR4_REG(base)                    ((base)->MGPCR4)
+#define AXBS_MGPCR5_REG(base)                    ((base)->MGPCR5)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/* PRS Bit Fields */
+#define AXBS_PRS_M0_MASK                         0x7u
+#define AXBS_PRS_M0_SHIFT                        0
+#define AXBS_PRS_M0_WIDTH                        3
+#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK                         0x70u
+#define AXBS_PRS_M1_SHIFT                        4
+#define AXBS_PRS_M1_WIDTH                        3
+#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK                         0x700u
+#define AXBS_PRS_M2_SHIFT                        8
+#define AXBS_PRS_M2_WIDTH                        3
+#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK                         0x7000u
+#define AXBS_PRS_M3_SHIFT                        12
+#define AXBS_PRS_M3_WIDTH                        3
+#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK                         0x70000u
+#define AXBS_PRS_M4_SHIFT                        16
+#define AXBS_PRS_M4_WIDTH                        3
+#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK                         0x700000u
+#define AXBS_PRS_M5_SHIFT                        20
+#define AXBS_PRS_M5_WIDTH                        3
+#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
+/* CRS Bit Fields */
+#define AXBS_CRS_PARK_MASK                       0x7u
+#define AXBS_CRS_PARK_SHIFT                      0
+#define AXBS_CRS_PARK_WIDTH                      3
+#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK                       0x30u
+#define AXBS_CRS_PCTL_SHIFT                      4
+#define AXBS_CRS_PCTL_WIDTH                      2
+#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK                        0x300u
+#define AXBS_CRS_ARB_SHIFT                       8
+#define AXBS_CRS_ARB_WIDTH                       2
+#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK                        0x40000000u
+#define AXBS_CRS_HLP_SHIFT                       30
+#define AXBS_CRS_HLP_WIDTH                       1
+#define AXBS_CRS_HLP(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_HLP_SHIFT))&AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_RO_MASK                         0x80000000u
+#define AXBS_CRS_RO_SHIFT                        31
+#define AXBS_CRS_RO_WIDTH                        1
+#define AXBS_CRS_RO(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_RO_SHIFT))&AXBS_CRS_RO_MASK)
+/* MGPCR0 Bit Fields */
+#define AXBS_MGPCR0_AULB_MASK                    0x7u
+#define AXBS_MGPCR0_AULB_SHIFT                   0
+#define AXBS_MGPCR0_AULB_WIDTH                   3
+#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
+/* MGPCR1 Bit Fields */
+#define AXBS_MGPCR1_AULB_MASK                    0x7u
+#define AXBS_MGPCR1_AULB_SHIFT                   0
+#define AXBS_MGPCR1_AULB_WIDTH                   3
+#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
+/* MGPCR2 Bit Fields */
+#define AXBS_MGPCR2_AULB_MASK                    0x7u
+#define AXBS_MGPCR2_AULB_SHIFT                   0
+#define AXBS_MGPCR2_AULB_WIDTH                   3
+#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
+/* MGPCR3 Bit Fields */
+#define AXBS_MGPCR3_AULB_MASK                    0x7u
+#define AXBS_MGPCR3_AULB_SHIFT                   0
+#define AXBS_MGPCR3_AULB_WIDTH                   3
+#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
+/* MGPCR4 Bit Fields */
+#define AXBS_MGPCR4_AULB_MASK                    0x7u
+#define AXBS_MGPCR4_AULB_SHIFT                   0
+#define AXBS_MGPCR4_AULB_WIDTH                   3
+#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
+/* MGPCR5 Bit Fields */
+#define AXBS_MGPCR5_AULB_MASK                    0x7u
+#define AXBS_MGPCR5_AULB_SHIFT                   0
+#define AXBS_MGPCR5_AULB_WIDTH                   3
+#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS base address */
+#define AXBS_BASE                                (0x40004000u)
+/** Peripheral AXBS base pointer */
+#define AXBS                                     ((AXBS_Type *)AXBS_BASE)
+#define AXBS_BASE_PTR                            (AXBS)
+/** Array initializer of AXBS peripheral base addresses */
+#define AXBS_BASE_ADDRS                          { AXBS_BASE }
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASE_PTRS                           { AXBS }
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register instance definitions */
+/* AXBS */
+#define AXBS_PRS0                                AXBS_PRS_REG(AXBS,0)
+#define AXBS_CRS0                                AXBS_CRS_REG(AXBS,0)
+#define AXBS_PRS1                                AXBS_PRS_REG(AXBS,1)
+#define AXBS_CRS1                                AXBS_CRS_REG(AXBS,1)
+#define AXBS_PRS2                                AXBS_PRS_REG(AXBS,2)
+#define AXBS_CRS2                                AXBS_CRS_REG(AXBS,2)
+#define AXBS_PRS3                                AXBS_PRS_REG(AXBS,3)
+#define AXBS_CRS3                                AXBS_CRS_REG(AXBS,3)
+#define AXBS_PRS4                                AXBS_PRS_REG(AXBS,4)
+#define AXBS_CRS4                                AXBS_CRS_REG(AXBS,4)
+#define AXBS_MGPCR0                              AXBS_MGPCR0_REG(AXBS)
+#define AXBS_MGPCR1                              AXBS_MGPCR1_REG(AXBS)
+#define AXBS_MGPCR2                              AXBS_MGPCR2_REG(AXBS)
+#define AXBS_MGPCR3                              AXBS_MGPCR3_REG(AXBS)
+#define AXBS_MGPCR4                              AXBS_MGPCR4_REG(AXBS)
+#define AXBS_MGPCR5                              AXBS_MGPCR5_REG(AXBS)
+
+/* AXBS - Register array accessors */
+#define AXBS_PRS(index)                          AXBS_PRS_REG(AXBS,index)
+#define AXBS_CRS(index)                          AXBS_CRS_REG(AXBS,index)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
+  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
+  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
+  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
+  __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
+  __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
+  __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
+  __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
+  __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
+       uint8_t RESERVED_4[48];
+  struct {                                         /* offset: 0x80, array step: 0x10 */
+    __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+    __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+    __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+    __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+  } MB[16];
+       uint8_t RESERVED_5[1792];
+  __IO uint32_t RXIMR[16];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_Type, *CAN_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register accessors */
+#define CAN_MCR_REG(base)                        ((base)->MCR)
+#define CAN_CTRL1_REG(base)                      ((base)->CTRL1)
+#define CAN_TIMER_REG(base)                      ((base)->TIMER)
+#define CAN_RXMGMASK_REG(base)                   ((base)->RXMGMASK)
+#define CAN_RX14MASK_REG(base)                   ((base)->RX14MASK)
+#define CAN_RX15MASK_REG(base)                   ((base)->RX15MASK)
+#define CAN_ECR_REG(base)                        ((base)->ECR)
+#define CAN_ESR1_REG(base)                       ((base)->ESR1)
+#define CAN_IMASK1_REG(base)                     ((base)->IMASK1)
+#define CAN_IFLAG1_REG(base)                     ((base)->IFLAG1)
+#define CAN_CTRL2_REG(base)                      ((base)->CTRL2)
+#define CAN_ESR2_REG(base)                       ((base)->ESR2)
+#define CAN_CRCR_REG(base)                       ((base)->CRCR)
+#define CAN_RXFGMASK_REG(base)                   ((base)->RXFGMASK)
+#define CAN_RXFIR_REG(base)                      ((base)->RXFIR)
+#define CAN_CS_REG(base,index)                   ((base)->MB[index].CS)
+#define CAN_CS_COUNT                             16
+#define CAN_ID_REG(base,index)                   ((base)->MB[index].ID)
+#define CAN_ID_COUNT                             16
+#define CAN_WORD0_REG(base,index)                ((base)->MB[index].WORD0)
+#define CAN_WORD0_COUNT                          16
+#define CAN_WORD1_REG(base,index)                ((base)->MB[index].WORD1)
+#define CAN_WORD1_COUNT                          16
+#define CAN_RXIMR_REG(base,index)                ((base)->RXIMR[index])
+#define CAN_RXIMR_COUNT                          16
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define CAN_MCR_MAXMB_MASK                       0x7Fu
+#define CAN_MCR_MAXMB_SHIFT                      0
+#define CAN_MCR_MAXMB_WIDTH                      7
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK                        0x300u
+#define CAN_MCR_IDAM_SHIFT                       8
+#define CAN_MCR_IDAM_WIDTH                       2
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK                         0x1000u
+#define CAN_MCR_AEN_SHIFT                        12
+#define CAN_MCR_AEN_WIDTH                        1
+#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK                     0x2000u
+#define CAN_MCR_LPRIOEN_SHIFT                    13
+#define CAN_MCR_LPRIOEN_WIDTH                    1
+#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_IRMQ_MASK                        0x10000u
+#define CAN_MCR_IRMQ_SHIFT                       16
+#define CAN_MCR_IRMQ_WIDTH                       1
+#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK                      0x20000u
+#define CAN_MCR_SRXDIS_SHIFT                     17
+#define CAN_MCR_SRXDIS_WIDTH                     1
+#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_WAKSRC_MASK                      0x80000u
+#define CAN_MCR_WAKSRC_SHIFT                     19
+#define CAN_MCR_WAKSRC_WIDTH                     1
+#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKSRC_SHIFT))&CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_LPMACK_MASK                      0x100000u
+#define CAN_MCR_LPMACK_SHIFT                     20
+#define CAN_MCR_LPMACK_WIDTH                     1
+#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK                       0x200000u
+#define CAN_MCR_WRNEN_SHIFT                      21
+#define CAN_MCR_WRNEN_WIDTH                      1
+#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SLFWAK_MASK                      0x400000u
+#define CAN_MCR_SLFWAK_SHIFT                     22
+#define CAN_MCR_SLFWAK_WIDTH                     1
+#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SLFWAK_SHIFT))&CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SUPV_MASK                        0x800000u
+#define CAN_MCR_SUPV_SHIFT                       23
+#define CAN_MCR_SUPV_WIDTH                       1
+#define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
+#define CAN_MCR_FRZACK_MASK                      0x1000000u
+#define CAN_MCR_FRZACK_SHIFT                     24
+#define CAN_MCR_FRZACK_WIDTH                     1
+#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK                     0x2000000u
+#define CAN_MCR_SOFTRST_SHIFT                    25
+#define CAN_MCR_SOFTRST_WIDTH                    1
+#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_WAKMSK_MASK                      0x4000000u
+#define CAN_MCR_WAKMSK_SHIFT                     26
+#define CAN_MCR_WAKMSK_WIDTH                     1
+#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKMSK_SHIFT))&CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_NOTRDY_MASK                      0x8000000u
+#define CAN_MCR_NOTRDY_SHIFT                     27
+#define CAN_MCR_NOTRDY_WIDTH                     1
+#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK                        0x10000000u
+#define CAN_MCR_HALT_SHIFT                       28
+#define CAN_MCR_HALT_WIDTH                       1
+#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK                        0x20000000u
+#define CAN_MCR_RFEN_SHIFT                       29
+#define CAN_MCR_RFEN_WIDTH                       1
+#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK                         0x40000000u
+#define CAN_MCR_FRZ_SHIFT                        30
+#define CAN_MCR_FRZ_WIDTH                        1
+#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK                        0x80000000u
+#define CAN_MCR_MDIS_SHIFT                       31
+#define CAN_MCR_MDIS_WIDTH                       1
+#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
+/* CTRL1 Bit Fields */
+#define CAN_CTRL1_PROPSEG_MASK                   0x7u
+#define CAN_CTRL1_PROPSEG_SHIFT                  0
+#define CAN_CTRL1_PROPSEG_WIDTH                  3
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK                       0x8u
+#define CAN_CTRL1_LOM_SHIFT                      3
+#define CAN_CTRL1_LOM_WIDTH                      1
+#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK                      0x10u
+#define CAN_CTRL1_LBUF_SHIFT                     4
+#define CAN_CTRL1_LBUF_WIDTH                     1
+#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK                      0x20u
+#define CAN_CTRL1_TSYN_SHIFT                     5
+#define CAN_CTRL1_TSYN_WIDTH                     1
+#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK                   0x40u
+#define CAN_CTRL1_BOFFREC_SHIFT                  6
+#define CAN_CTRL1_BOFFREC_WIDTH                  1
+#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK                       0x80u
+#define CAN_CTRL1_SMP_SHIFT                      7
+#define CAN_CTRL1_SMP_WIDTH                      1
+#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK                   0x400u
+#define CAN_CTRL1_RWRNMSK_SHIFT                  10
+#define CAN_CTRL1_RWRNMSK_WIDTH                  1
+#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK                   0x800u
+#define CAN_CTRL1_TWRNMSK_SHIFT                  11
+#define CAN_CTRL1_TWRNMSK_WIDTH                  1
+#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK                       0x1000u
+#define CAN_CTRL1_LPB_SHIFT                      12
+#define CAN_CTRL1_LPB_WIDTH                      1
+#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_CLKSRC_MASK                    0x2000u
+#define CAN_CTRL1_CLKSRC_SHIFT                   13
+#define CAN_CTRL1_CLKSRC_WIDTH                   1
+#define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_ERRMSK_MASK                    0x4000u
+#define CAN_CTRL1_ERRMSK_SHIFT                   14
+#define CAN_CTRL1_ERRMSK_WIDTH                   1
+#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK                   0x8000u
+#define CAN_CTRL1_BOFFMSK_SHIFT                  15
+#define CAN_CTRL1_BOFFMSK_WIDTH                  1
+#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK                     0x70000u
+#define CAN_CTRL1_PSEG2_SHIFT                    16
+#define CAN_CTRL1_PSEG2_WIDTH                    3
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK                     0x380000u
+#define CAN_CTRL1_PSEG1_SHIFT                    19
+#define CAN_CTRL1_PSEG1_WIDTH                    3
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK                       0xC00000u
+#define CAN_CTRL1_RJW_SHIFT                      22
+#define CAN_CTRL1_RJW_WIDTH                      2
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
+#define CAN_CTRL1_PRESDIV_SHIFT                  24
+#define CAN_CTRL1_PRESDIV_WIDTH                  8
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
+/* TIMER Bit Fields */
+#define CAN_TIMER_TIMER_MASK                     0xFFFFu
+#define CAN_TIMER_TIMER_SHIFT                    0
+#define CAN_TIMER_TIMER_WIDTH                    16
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
+/* RXMGMASK Bit Fields */
+#define CAN_RXMGMASK_MG_MASK                     0xFFFFFFFFu
+#define CAN_RXMGMASK_MG_SHIFT                    0
+#define CAN_RXMGMASK_MG_WIDTH                    32
+#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
+/* RX14MASK Bit Fields */
+#define CAN_RX14MASK_RX14M_MASK                  0xFFFFFFFFu
+#define CAN_RX14MASK_RX14M_SHIFT                 0
+#define CAN_RX14MASK_RX14M_WIDTH                 32
+#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
+/* RX15MASK Bit Fields */
+#define CAN_RX15MASK_RX15M_MASK                  0xFFFFFFFFu
+#define CAN_RX15MASK_RX15M_SHIFT                 0
+#define CAN_RX15MASK_RX15M_WIDTH                 32
+#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
+/* ECR Bit Fields */
+#define CAN_ECR_TXERRCNT_MASK                    0xFFu
+#define CAN_ECR_TXERRCNT_SHIFT                   0
+#define CAN_ECR_TXERRCNT_WIDTH                   8
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK                    0xFF00u
+#define CAN_ECR_RXERRCNT_SHIFT                   8
+#define CAN_ECR_RXERRCNT_WIDTH                   8
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
+/* ESR1 Bit Fields */
+#define CAN_ESR1_WAKINT_MASK                     0x1u
+#define CAN_ESR1_WAKINT_SHIFT                    0
+#define CAN_ESR1_WAKINT_WIDTH                    1
+#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_WAKINT_SHIFT))&CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_ERRINT_MASK                     0x2u
+#define CAN_ESR1_ERRINT_SHIFT                    1
+#define CAN_ESR1_ERRINT_WIDTH                    1
+#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK                    0x4u
+#define CAN_ESR1_BOFFINT_SHIFT                   2
+#define CAN_ESR1_BOFFINT_WIDTH                   1
+#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK                         0x8u
+#define CAN_ESR1_RX_SHIFT                        3
+#define CAN_ESR1_RX_WIDTH                        1
+#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK                    0x30u
+#define CAN_ESR1_FLTCONF_SHIFT                   4
+#define CAN_ESR1_FLTCONF_WIDTH                   2
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK                         0x40u
+#define CAN_ESR1_TX_SHIFT                        6
+#define CAN_ESR1_TX_WIDTH                        1
+#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK                       0x80u
+#define CAN_ESR1_IDLE_SHIFT                      7
+#define CAN_ESR1_IDLE_WIDTH                      1
+#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK                      0x100u
+#define CAN_ESR1_RXWRN_SHIFT                     8
+#define CAN_ESR1_RXWRN_WIDTH                     1
+#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK                      0x200u
+#define CAN_ESR1_TXWRN_SHIFT                     9
+#define CAN_ESR1_TXWRN_WIDTH                     1
+#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK                     0x400u
+#define CAN_ESR1_STFERR_SHIFT                    10
+#define CAN_ESR1_STFERR_WIDTH                    1
+#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK                     0x800u
+#define CAN_ESR1_FRMERR_SHIFT                    11
+#define CAN_ESR1_FRMERR_WIDTH                    1
+#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK                     0x1000u
+#define CAN_ESR1_CRCERR_SHIFT                    12
+#define CAN_ESR1_CRCERR_WIDTH                    1
+#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK                     0x2000u
+#define CAN_ESR1_ACKERR_SHIFT                    13
+#define CAN_ESR1_ACKERR_WIDTH                    1
+#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK                    0x4000u
+#define CAN_ESR1_BIT0ERR_SHIFT                   14
+#define CAN_ESR1_BIT0ERR_WIDTH                   1
+#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK                    0x8000u
+#define CAN_ESR1_BIT1ERR_SHIFT                   15
+#define CAN_ESR1_BIT1ERR_WIDTH                   1
+#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK                    0x10000u
+#define CAN_ESR1_RWRNINT_SHIFT                   16
+#define CAN_ESR1_RWRNINT_WIDTH                   1
+#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK                    0x20000u
+#define CAN_ESR1_TWRNINT_SHIFT                   17
+#define CAN_ESR1_TWRNINT_WIDTH                   1
+#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK                      0x40000u
+#define CAN_ESR1_SYNCH_SHIFT                     18
+#define CAN_ESR1_SYNCH_WIDTH                     1
+#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
+/* IMASK1 Bit Fields */
+#define CAN_IMASK1_BUFLM_MASK                    0xFFFFFFFFu
+#define CAN_IMASK1_BUFLM_SHIFT                   0
+#define CAN_IMASK1_BUFLM_WIDTH                   32
+#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
+/* IFLAG1 Bit Fields */
+#define CAN_IFLAG1_BUF0I_MASK                    0x1u
+#define CAN_IFLAG1_BUF0I_SHIFT                   0
+#define CAN_IFLAG1_BUF0I_WIDTH                   1
+#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF4TO1I_MASK                 0x1Eu
+#define CAN_IFLAG1_BUF4TO1I_SHIFT                1
+#define CAN_IFLAG1_BUF4TO1I_WIDTH                4
+#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK                    0x20u
+#define CAN_IFLAG1_BUF5I_SHIFT                   5
+#define CAN_IFLAG1_BUF5I_WIDTH                   1
+#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK                    0x40u
+#define CAN_IFLAG1_BUF6I_SHIFT                   6
+#define CAN_IFLAG1_BUF6I_WIDTH                   1
+#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK                    0x80u
+#define CAN_IFLAG1_BUF7I_SHIFT                   7
+#define CAN_IFLAG1_BUF7I_WIDTH                   1
+#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK                0xFFFFFF00u
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               8
+#define CAN_IFLAG1_BUF31TO8I_WIDTH               24
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
+/* CTRL2 Bit Fields */
+#define CAN_CTRL2_EACEN_MASK                     0x10000u
+#define CAN_CTRL2_EACEN_SHIFT                    16
+#define CAN_CTRL2_EACEN_WIDTH                    1
+#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK                       0x20000u
+#define CAN_CTRL2_RRS_SHIFT                      17
+#define CAN_CTRL2_RRS_WIDTH                      1
+#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK                       0x40000u
+#define CAN_CTRL2_MRP_SHIFT                      18
+#define CAN_CTRL2_MRP_WIDTH                      1
+#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK                      0xF80000u
+#define CAN_CTRL2_TASD_SHIFT                     19
+#define CAN_CTRL2_TASD_WIDTH                     5
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK                      0xF000000u
+#define CAN_CTRL2_RFFN_SHIFT                     24
+#define CAN_CTRL2_RFFN_WIDTH                     4
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK                    0x10000000u
+#define CAN_CTRL2_WRMFRZ_SHIFT                   28
+#define CAN_CTRL2_WRMFRZ_WIDTH                   1
+#define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_WRMFRZ_SHIFT))&CAN_CTRL2_WRMFRZ_MASK)
+/* ESR2 Bit Fields */
+#define CAN_ESR2_IMB_MASK                        0x2000u
+#define CAN_ESR2_IMB_SHIFT                       13
+#define CAN_ESR2_IMB_WIDTH                       1
+#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK                        0x4000u
+#define CAN_ESR2_VPS_SHIFT                       14
+#define CAN_ESR2_VPS_WIDTH                       1
+#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK                       0x7F0000u
+#define CAN_ESR2_LPTM_SHIFT                      16
+#define CAN_ESR2_LPTM_WIDTH                      7
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
+/* CRCR Bit Fields */
+#define CAN_CRCR_TXCRC_MASK                      0x7FFFu
+#define CAN_CRCR_TXCRC_SHIFT                     0
+#define CAN_CRCR_TXCRC_WIDTH                     15
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK                      0x7F0000u
+#define CAN_CRCR_MBCRC_SHIFT                     16
+#define CAN_CRCR_MBCRC_WIDTH                     7
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
+/* RXFGMASK Bit Fields */
+#define CAN_RXFGMASK_FGM_MASK                    0xFFFFFFFFu
+#define CAN_RXFGMASK_FGM_SHIFT                   0
+#define CAN_RXFGMASK_FGM_WIDTH                   32
+#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
+/* RXFIR Bit Fields */
+#define CAN_RXFIR_IDHIT_MASK                     0x1FFu
+#define CAN_RXFIR_IDHIT_SHIFT                    0
+#define CAN_RXFIR_IDHIT_WIDTH                    9
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
+/* CS Bit Fields */
+#define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
+#define CAN_CS_TIME_STAMP_SHIFT                  0
+#define CAN_CS_TIME_STAMP_WIDTH                  16
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK                          0xF0000u
+#define CAN_CS_DLC_SHIFT                         16
+#define CAN_CS_DLC_WIDTH                         4
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK                          0x100000u
+#define CAN_CS_RTR_SHIFT                         20
+#define CAN_CS_RTR_WIDTH                         1
+#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_RTR_SHIFT))&CAN_CS_RTR_MASK)
+#define CAN_CS_IDE_MASK                          0x200000u
+#define CAN_CS_IDE_SHIFT                         21
+#define CAN_CS_IDE_WIDTH                         1
+#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_IDE_SHIFT))&CAN_CS_IDE_MASK)
+#define CAN_CS_SRR_MASK                          0x400000u
+#define CAN_CS_SRR_SHIFT                         22
+#define CAN_CS_SRR_WIDTH                         1
+#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_SRR_SHIFT))&CAN_CS_SRR_MASK)
+#define CAN_CS_CODE_MASK                         0xF000000u
+#define CAN_CS_CODE_SHIFT                        24
+#define CAN_CS_CODE_WIDTH                        4
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
+/* ID Bit Fields */
+#define CAN_ID_EXT_MASK                          0x3FFFFu
+#define CAN_ID_EXT_SHIFT                         0
+#define CAN_ID_EXT_WIDTH                         18
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK                          0x1FFC0000u
+#define CAN_ID_STD_SHIFT                         18
+#define CAN_ID_STD_WIDTH                         11
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK                         0xE0000000u
+#define CAN_ID_PRIO_SHIFT                        29
+#define CAN_ID_PRIO_WIDTH                        3
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
+/* WORD0 Bit Fields */
+#define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              0
+#define CAN_WORD0_DATA_BYTE_3_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              8
+#define CAN_WORD0_DATA_BYTE_2_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              16
+#define CAN_WORD0_DATA_BYTE_1_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              24
+#define CAN_WORD0_DATA_BYTE_0_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
+/* WORD1 Bit Fields */
+#define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              0
+#define CAN_WORD1_DATA_BYTE_7_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              8
+#define CAN_WORD1_DATA_BYTE_6_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              16
+#define CAN_WORD1_DATA_BYTE_5_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              24
+#define CAN_WORD1_DATA_BYTE_4_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
+/* RXIMR Bit Fields */
+#define CAN_RXIMR_MI_MASK                        0xFFFFFFFFu
+#define CAN_RXIMR_MI_SHIFT                       0
+#define CAN_RXIMR_MI_WIDTH                       32
+#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+#define CAN0_BASE_PTR                            (CAN0)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS                      { CAN0_Rx_Warning_IRQn }
+#define CAN_Tx_Warning_IRQS                      { CAN0_Tx_Warning_IRQn }
+#define CAN_Wake_Up_IRQS                         { CAN0_Wake_Up_IRQn }
+#define CAN_Error_IRQS                           { CAN0_Error_IRQn }
+#define CAN_Bus_Off_IRQS                         { CAN0_Bus_Off_IRQn }
+#define CAN_ORed_Message_buffer_IRQS             { CAN0_ORed_Message_buffer_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register instance definitions */
+/* CAN0 */
+#define CAN0_MCR                                 CAN_MCR_REG(CAN0)
+#define CAN0_CTRL1                               CAN_CTRL1_REG(CAN0)
+#define CAN0_TIMER                               CAN_TIMER_REG(CAN0)
+#define CAN0_RXMGMASK                            CAN_RXMGMASK_REG(CAN0)
+#define CAN0_RX14MASK                            CAN_RX14MASK_REG(CAN0)
+#define CAN0_RX15MASK                            CAN_RX15MASK_REG(CAN0)
+#define CAN0_ECR                                 CAN_ECR_REG(CAN0)
+#define CAN0_ESR1                                CAN_ESR1_REG(CAN0)
+#define CAN0_IMASK1                              CAN_IMASK1_REG(CAN0)
+#define CAN0_IFLAG1                              CAN_IFLAG1_REG(CAN0)
+#define CAN0_CTRL2                               CAN_CTRL2_REG(CAN0)
+#define CAN0_ESR2                                CAN_ESR2_REG(CAN0)
+#define CAN0_CRCR                                CAN_CRCR_REG(CAN0)
+#define CAN0_RXFGMASK                            CAN_RXFGMASK_REG(CAN0)
+#define CAN0_RXFIR                               CAN_RXFIR_REG(CAN0)
+#define CAN0_CS0                                 CAN_CS_REG(CAN0,0)
+#define CAN0_ID0                                 CAN_ID_REG(CAN0,0)
+#define CAN0_WORD00                              CAN_WORD0_REG(CAN0,0)
+#define CAN0_WORD10                              CAN_WORD1_REG(CAN0,0)
+#define CAN0_CS1                                 CAN_CS_REG(CAN0,1)
+#define CAN0_ID1                                 CAN_ID_REG(CAN0,1)
+#define CAN0_WORD01                              CAN_WORD0_REG(CAN0,1)
+#define CAN0_WORD11                              CAN_WORD1_REG(CAN0,1)
+#define CAN0_CS2                                 CAN_CS_REG(CAN0,2)
+#define CAN0_ID2                                 CAN_ID_REG(CAN0,2)
+#define CAN0_WORD02                              CAN_WORD0_REG(CAN0,2)
+#define CAN0_WORD12                              CAN_WORD1_REG(CAN0,2)
+#define CAN0_CS3                                 CAN_CS_REG(CAN0,3)
+#define CAN0_ID3                                 CAN_ID_REG(CAN0,3)
+#define CAN0_WORD03                              CAN_WORD0_REG(CAN0,3)
+#define CAN0_WORD13                              CAN_WORD1_REG(CAN0,3)
+#define CAN0_CS4                                 CAN_CS_REG(CAN0,4)
+#define CAN0_ID4                                 CAN_ID_REG(CAN0,4)
+#define CAN0_WORD04                              CAN_WORD0_REG(CAN0,4)
+#define CAN0_WORD14                              CAN_WORD1_REG(CAN0,4)
+#define CAN0_CS5                                 CAN_CS_REG(CAN0,5)
+#define CAN0_ID5                                 CAN_ID_REG(CAN0,5)
+#define CAN0_WORD05                              CAN_WORD0_REG(CAN0,5)
+#define CAN0_WORD15                              CAN_WORD1_REG(CAN0,5)
+#define CAN0_CS6                                 CAN_CS_REG(CAN0,6)
+#define CAN0_ID6                                 CAN_ID_REG(CAN0,6)
+#define CAN0_WORD06                              CAN_WORD0_REG(CAN0,6)
+#define CAN0_WORD16                              CAN_WORD1_REG(CAN0,6)
+#define CAN0_CS7                                 CAN_CS_REG(CAN0,7)
+#define CAN0_ID7                                 CAN_ID_REG(CAN0,7)
+#define CAN0_WORD07                              CAN_WORD0_REG(CAN0,7)
+#define CAN0_WORD17                              CAN_WORD1_REG(CAN0,7)
+#define CAN0_CS8                                 CAN_CS_REG(CAN0,8)
+#define CAN0_ID8                                 CAN_ID_REG(CAN0,8)
+#define CAN0_WORD08                              CAN_WORD0_REG(CAN0,8)
+#define CAN0_WORD18                              CAN_WORD1_REG(CAN0,8)
+#define CAN0_CS9                                 CAN_CS_REG(CAN0,9)
+#define CAN0_ID9                                 CAN_ID_REG(CAN0,9)
+#define CAN0_WORD09                              CAN_WORD0_REG(CAN0,9)
+#define CAN0_WORD19                              CAN_WORD1_REG(CAN0,9)
+#define CAN0_CS10                                CAN_CS_REG(CAN0,10)
+#define CAN0_ID10                                CAN_ID_REG(CAN0,10)
+#define CAN0_WORD010                             CAN_WORD0_REG(CAN0,10)
+#define CAN0_WORD110                             CAN_WORD1_REG(CAN0,10)
+#define CAN0_CS11                                CAN_CS_REG(CAN0,11)
+#define CAN0_ID11                                CAN_ID_REG(CAN0,11)
+#define CAN0_WORD011                             CAN_WORD0_REG(CAN0,11)
+#define CAN0_WORD111                             CAN_WORD1_REG(CAN0,11)
+#define CAN0_CS12                                CAN_CS_REG(CAN0,12)
+#define CAN0_ID12                                CAN_ID_REG(CAN0,12)
+#define CAN0_WORD012                             CAN_WORD0_REG(CAN0,12)
+#define CAN0_WORD112                             CAN_WORD1_REG(CAN0,12)
+#define CAN0_CS13                                CAN_CS_REG(CAN0,13)
+#define CAN0_ID13                                CAN_ID_REG(CAN0,13)
+#define CAN0_WORD013                             CAN_WORD0_REG(CAN0,13)
+#define CAN0_WORD113                             CAN_WORD1_REG(CAN0,13)
+#define CAN0_CS14                                CAN_CS_REG(CAN0,14)
+#define CAN0_ID14                                CAN_ID_REG(CAN0,14)
+#define CAN0_WORD014                             CAN_WORD0_REG(CAN0,14)
+#define CAN0_WORD114                             CAN_WORD1_REG(CAN0,14)
+#define CAN0_CS15                                CAN_CS_REG(CAN0,15)
+#define CAN0_ID15                                CAN_ID_REG(CAN0,15)
+#define CAN0_WORD015                             CAN_WORD0_REG(CAN0,15)
+#define CAN0_WORD115                             CAN_WORD1_REG(CAN0,15)
+#define CAN0_RXIMR0                              CAN_RXIMR_REG(CAN0,0)
+#define CAN0_RXIMR1                              CAN_RXIMR_REG(CAN0,1)
+#define CAN0_RXIMR2                              CAN_RXIMR_REG(CAN0,2)
+#define CAN0_RXIMR3                              CAN_RXIMR_REG(CAN0,3)
+#define CAN0_RXIMR4                              CAN_RXIMR_REG(CAN0,4)
+#define CAN0_RXIMR5                              CAN_RXIMR_REG(CAN0,5)
+#define CAN0_RXIMR6                              CAN_RXIMR_REG(CAN0,6)
+#define CAN0_RXIMR7                              CAN_RXIMR_REG(CAN0,7)
+#define CAN0_RXIMR8                              CAN_RXIMR_REG(CAN0,8)
+#define CAN0_RXIMR9                              CAN_RXIMR_REG(CAN0,9)
+#define CAN0_RXIMR10                             CAN_RXIMR_REG(CAN0,10)
+#define CAN0_RXIMR11                             CAN_RXIMR_REG(CAN0,11)
+#define CAN0_RXIMR12                             CAN_RXIMR_REG(CAN0,12)
+#define CAN0_RXIMR13                             CAN_RXIMR_REG(CAN0,13)
+#define CAN0_RXIMR14                             CAN_RXIMR_REG(CAN0,14)
+#define CAN0_RXIMR15                             CAN_RXIMR_REG(CAN0,15)
+
+/* CAN - Register array accessors */
+#define CAN0_CS(index)                           CAN_CS_REG(CAN0,index)
+#define CAN0_ID(index)                           CAN_ID_REG(CAN0,index)
+#define CAN0_WORD0(index)                        CAN_WORD0_REG(CAN0,index)
+#define CAN0_WORD1(index)                        CAN_WORD1_REG(CAN0,index)
+#define CAN0_RXIMR(index)                        CAN_RXIMR_REG(CAN0,index)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+  __O  uint32_t DIRECT[16];                        /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[2048];
+  __O  uint32_t LDR_CASR;                          /**< Status register - Load Register command, offset: 0x840 */
+  __O  uint32_t LDR_CAA;                           /**< Accumulator register - Load Register command, offset: 0x844 */
+  __O  uint32_t LDR_CA[9];                         /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
+       uint8_t RESERVED_1[20];
+  __I  uint32_t STR_CASR;                          /**< Status register - Store Register command, offset: 0x880 */
+  __I  uint32_t STR_CAA;                           /**< Accumulator register - Store Register command, offset: 0x884 */
+  __I  uint32_t STR_CA[9];                         /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
+       uint8_t RESERVED_2[20];
+  __O  uint32_t ADR_CASR;                          /**< Status register - Add Register command, offset: 0x8C0 */
+  __O  uint32_t ADR_CAA;                           /**< Accumulator register - Add to register command, offset: 0x8C4 */
+  __O  uint32_t ADR_CA[9];                         /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
+       uint8_t RESERVED_3[20];
+  __O  uint32_t RADR_CASR;                         /**< Status register - Reverse and Add to Register command, offset: 0x900 */
+  __O  uint32_t RADR_CAA;                          /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
+  __O  uint32_t RADR_CA[9];                        /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
+       uint8_t RESERVED_4[84];
+  __O  uint32_t XOR_CASR;                          /**< Status register - Exclusive Or command, offset: 0x980 */
+  __O  uint32_t XOR_CAA;                           /**< Accumulator register - Exclusive Or command, offset: 0x984 */
+  __O  uint32_t XOR_CA[9];                         /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
+       uint8_t RESERVED_5[20];
+  __O  uint32_t ROTL_CASR;                         /**< Status register - Rotate Left command, offset: 0x9C0 */
+  __O  uint32_t ROTL_CAA;                          /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
+  __O  uint32_t ROTL_CA[9];                        /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
+       uint8_t RESERVED_6[276];
+  __O  uint32_t AESC_CASR;                         /**< Status register - AES Column Operation command, offset: 0xB00 */
+  __O  uint32_t AESC_CAA;                          /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
+  __O  uint32_t AESC_CA[9];                        /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
+       uint8_t RESERVED_7[20];
+  __O  uint32_t AESIC_CASR;                        /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
+  __O  uint32_t AESIC_CAA;                         /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
+  __O  uint32_t AESIC_CA[9];                       /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
+} CAU_Type, *CAU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register accessors */
+#define CAU_DIRECT_REG(base,index)               ((base)->DIRECT[index])
+#define CAU_DIRECT_COUNT                         16
+#define CAU_LDR_CASR_REG(base)                   ((base)->LDR_CASR)
+#define CAU_LDR_CAA_REG(base)                    ((base)->LDR_CAA)
+#define CAU_LDR_CA_REG(base,index)               ((base)->LDR_CA[index])
+#define CAU_LDR_CA_COUNT                         9
+#define CAU_STR_CASR_REG(base)                   ((base)->STR_CASR)
+#define CAU_STR_CAA_REG(base)                    ((base)->STR_CAA)
+#define CAU_STR_CA_REG(base,index)               ((base)->STR_CA[index])
+#define CAU_STR_CA_COUNT                         9
+#define CAU_ADR_CASR_REG(base)                   ((base)->ADR_CASR)
+#define CAU_ADR_CAA_REG(base)                    ((base)->ADR_CAA)
+#define CAU_ADR_CA_REG(base,index)               ((base)->ADR_CA[index])
+#define CAU_ADR_CA_COUNT                         9
+#define CAU_RADR_CASR_REG(base)                  ((base)->RADR_CASR)
+#define CAU_RADR_CAA_REG(base)                   ((base)->RADR_CAA)
+#define CAU_RADR_CA_REG(base,index)              ((base)->RADR_CA[index])
+#define CAU_RADR_CA_COUNT                        9
+#define CAU_XOR_CASR_REG(base)                   ((base)->XOR_CASR)
+#define CAU_XOR_CAA_REG(base)                    ((base)->XOR_CAA)
+#define CAU_XOR_CA_REG(base,index)               ((base)->XOR_CA[index])
+#define CAU_XOR_CA_COUNT                         9
+#define CAU_ROTL_CASR_REG(base)                  ((base)->ROTL_CASR)
+#define CAU_ROTL_CAA_REG(base)                   ((base)->ROTL_CAA)
+#define CAU_ROTL_CA_REG(base,index)              ((base)->ROTL_CA[index])
+#define CAU_ROTL_CA_COUNT                        9
+#define CAU_AESC_CASR_REG(base)                  ((base)->AESC_CASR)
+#define CAU_AESC_CAA_REG(base)                   ((base)->AESC_CAA)
+#define CAU_AESC_CA_REG(base,index)              ((base)->AESC_CA[index])
+#define CAU_AESC_CA_COUNT                        9
+#define CAU_AESIC_CASR_REG(base)                 ((base)->AESIC_CASR)
+#define CAU_AESIC_CAA_REG(base)                  ((base)->AESIC_CAA)
+#define CAU_AESIC_CA_REG(base,index)             ((base)->AESIC_CA[index])
+#define CAU_AESIC_CA_COUNT                       9
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/* DIRECT Bit Fields */
+#define CAU_DIRECT_CAU_DIRECT0_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT0_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT0_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT0(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
+#define CAU_DIRECT_CAU_DIRECT1_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT1_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT1_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT1(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
+#define CAU_DIRECT_CAU_DIRECT2_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT2_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT2_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT2(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
+#define CAU_DIRECT_CAU_DIRECT3_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT3_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT3_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT3(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
+#define CAU_DIRECT_CAU_DIRECT4_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT4_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT4_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT4(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
+#define CAU_DIRECT_CAU_DIRECT5_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT5_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT5_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT5(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
+#define CAU_DIRECT_CAU_DIRECT6_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT6_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT6_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT6(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
+#define CAU_DIRECT_CAU_DIRECT7_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT7_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT7_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT7(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
+#define CAU_DIRECT_CAU_DIRECT8_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT8_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT8_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT8(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
+#define CAU_DIRECT_CAU_DIRECT9_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT9_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT9_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT9(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
+#define CAU_DIRECT_CAU_DIRECT10_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT10_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT10_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT10(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
+#define CAU_DIRECT_CAU_DIRECT11_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT11_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT11_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT11(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
+#define CAU_DIRECT_CAU_DIRECT12_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT12_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT12_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT12(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
+#define CAU_DIRECT_CAU_DIRECT13_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT13_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT13_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT13(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
+#define CAU_DIRECT_CAU_DIRECT14_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT14_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT14_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT14(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
+#define CAU_DIRECT_CAU_DIRECT15_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT15_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT15_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT15(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
+/* LDR_CASR Bit Fields */
+#define CAU_LDR_CASR_IC_MASK                     0x1u
+#define CAU_LDR_CASR_IC_SHIFT                    0
+#define CAU_LDR_CASR_IC_WIDTH                    1
+#define CAU_LDR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_IC_SHIFT))&CAU_LDR_CASR_IC_MASK)
+#define CAU_LDR_CASR_DPE_MASK                    0x2u
+#define CAU_LDR_CASR_DPE_SHIFT                   1
+#define CAU_LDR_CASR_DPE_WIDTH                   1
+#define CAU_LDR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_DPE_SHIFT))&CAU_LDR_CASR_DPE_MASK)
+#define CAU_LDR_CASR_VER_MASK                    0xF0000000u
+#define CAU_LDR_CASR_VER_SHIFT                   28
+#define CAU_LDR_CASR_VER_WIDTH                   4
+#define CAU_LDR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
+/* LDR_CAA Bit Fields */
+#define CAU_LDR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_LDR_CAA_ACC_SHIFT                    0
+#define CAU_LDR_CAA_ACC_WIDTH                    32
+#define CAU_LDR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
+/* LDR_CA Bit Fields */
+#define CAU_LDR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA0_SHIFT                     0
+#define CAU_LDR_CA_CA0_WIDTH                     32
+#define CAU_LDR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
+#define CAU_LDR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA1_SHIFT                     0
+#define CAU_LDR_CA_CA1_WIDTH                     32
+#define CAU_LDR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
+#define CAU_LDR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA2_SHIFT                     0
+#define CAU_LDR_CA_CA2_WIDTH                     32
+#define CAU_LDR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
+#define CAU_LDR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA3_SHIFT                     0
+#define CAU_LDR_CA_CA3_WIDTH                     32
+#define CAU_LDR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
+#define CAU_LDR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA4_SHIFT                     0
+#define CAU_LDR_CA_CA4_WIDTH                     32
+#define CAU_LDR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
+#define CAU_LDR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA5_SHIFT                     0
+#define CAU_LDR_CA_CA5_WIDTH                     32
+#define CAU_LDR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
+#define CAU_LDR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA6_SHIFT                     0
+#define CAU_LDR_CA_CA6_WIDTH                     32
+#define CAU_LDR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
+#define CAU_LDR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA7_SHIFT                     0
+#define CAU_LDR_CA_CA7_WIDTH                     32
+#define CAU_LDR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
+#define CAU_LDR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA8_SHIFT                     0
+#define CAU_LDR_CA_CA8_WIDTH                     32
+#define CAU_LDR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
+/* STR_CASR Bit Fields */
+#define CAU_STR_CASR_IC_MASK                     0x1u
+#define CAU_STR_CASR_IC_SHIFT                    0
+#define CAU_STR_CASR_IC_WIDTH                    1
+#define CAU_STR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_IC_SHIFT))&CAU_STR_CASR_IC_MASK)
+#define CAU_STR_CASR_DPE_MASK                    0x2u
+#define CAU_STR_CASR_DPE_SHIFT                   1
+#define CAU_STR_CASR_DPE_WIDTH                   1
+#define CAU_STR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_DPE_SHIFT))&CAU_STR_CASR_DPE_MASK)
+#define CAU_STR_CASR_VER_MASK                    0xF0000000u
+#define CAU_STR_CASR_VER_SHIFT                   28
+#define CAU_STR_CASR_VER_WIDTH                   4
+#define CAU_STR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
+/* STR_CAA Bit Fields */
+#define CAU_STR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_STR_CAA_ACC_SHIFT                    0
+#define CAU_STR_CAA_ACC_WIDTH                    32
+#define CAU_STR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
+/* STR_CA Bit Fields */
+#define CAU_STR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA0_SHIFT                     0
+#define CAU_STR_CA_CA0_WIDTH                     32
+#define CAU_STR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
+#define CAU_STR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA1_SHIFT                     0
+#define CAU_STR_CA_CA1_WIDTH                     32
+#define CAU_STR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
+#define CAU_STR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA2_SHIFT                     0
+#define CAU_STR_CA_CA2_WIDTH                     32
+#define CAU_STR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
+#define CAU_STR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA3_SHIFT                     0
+#define CAU_STR_CA_CA3_WIDTH                     32
+#define CAU_STR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
+#define CAU_STR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA4_SHIFT                     0
+#define CAU_STR_CA_CA4_WIDTH                     32
+#define CAU_STR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
+#define CAU_STR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA5_SHIFT                     0
+#define CAU_STR_CA_CA5_WIDTH                     32
+#define CAU_STR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
+#define CAU_STR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA6_SHIFT                     0
+#define CAU_STR_CA_CA6_WIDTH                     32
+#define CAU_STR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
+#define CAU_STR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA7_SHIFT                     0
+#define CAU_STR_CA_CA7_WIDTH                     32
+#define CAU_STR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
+#define CAU_STR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA8_SHIFT                     0
+#define CAU_STR_CA_CA8_WIDTH                     32
+#define CAU_STR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
+/* ADR_CASR Bit Fields */
+#define CAU_ADR_CASR_IC_MASK                     0x1u
+#define CAU_ADR_CASR_IC_SHIFT                    0
+#define CAU_ADR_CASR_IC_WIDTH                    1
+#define CAU_ADR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_IC_SHIFT))&CAU_ADR_CASR_IC_MASK)
+#define CAU_ADR_CASR_DPE_MASK                    0x2u
+#define CAU_ADR_CASR_DPE_SHIFT                   1
+#define CAU_ADR_CASR_DPE_WIDTH                   1
+#define CAU_ADR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_DPE_SHIFT))&CAU_ADR_CASR_DPE_MASK)
+#define CAU_ADR_CASR_VER_MASK                    0xF0000000u
+#define CAU_ADR_CASR_VER_SHIFT                   28
+#define CAU_ADR_CASR_VER_WIDTH                   4
+#define CAU_ADR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
+/* ADR_CAA Bit Fields */
+#define CAU_ADR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_ADR_CAA_ACC_SHIFT                    0
+#define CAU_ADR_CAA_ACC_WIDTH                    32
+#define CAU_ADR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
+/* ADR_CA Bit Fields */
+#define CAU_ADR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA0_SHIFT                     0
+#define CAU_ADR_CA_CA0_WIDTH                     32
+#define CAU_ADR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
+#define CAU_ADR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA1_SHIFT                     0
+#define CAU_ADR_CA_CA1_WIDTH                     32
+#define CAU_ADR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
+#define CAU_ADR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA2_SHIFT                     0
+#define CAU_ADR_CA_CA2_WIDTH                     32
+#define CAU_ADR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
+#define CAU_ADR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA3_SHIFT                     0
+#define CAU_ADR_CA_CA3_WIDTH                     32
+#define CAU_ADR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
+#define CAU_ADR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA4_SHIFT                     0
+#define CAU_ADR_CA_CA4_WIDTH                     32
+#define CAU_ADR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
+#define CAU_ADR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA5_SHIFT                     0
+#define CAU_ADR_CA_CA5_WIDTH                     32
+#define CAU_ADR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
+#define CAU_ADR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA6_SHIFT                     0
+#define CAU_ADR_CA_CA6_WIDTH                     32
+#define CAU_ADR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
+#define CAU_ADR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA7_SHIFT                     0
+#define CAU_ADR_CA_CA7_WIDTH                     32
+#define CAU_ADR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
+#define CAU_ADR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA8_SHIFT                     0
+#define CAU_ADR_CA_CA8_WIDTH                     32
+#define CAU_ADR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
+/* RADR_CASR Bit Fields */
+#define CAU_RADR_CASR_IC_MASK                    0x1u
+#define CAU_RADR_CASR_IC_SHIFT                   0
+#define CAU_RADR_CASR_IC_WIDTH                   1
+#define CAU_RADR_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_IC_SHIFT))&CAU_RADR_CASR_IC_MASK)
+#define CAU_RADR_CASR_DPE_MASK                   0x2u
+#define CAU_RADR_CASR_DPE_SHIFT                  1
+#define CAU_RADR_CASR_DPE_WIDTH                  1
+#define CAU_RADR_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_DPE_SHIFT))&CAU_RADR_CASR_DPE_MASK)
+#define CAU_RADR_CASR_VER_MASK                   0xF0000000u
+#define CAU_RADR_CASR_VER_SHIFT                  28
+#define CAU_RADR_CASR_VER_WIDTH                  4
+#define CAU_RADR_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
+/* RADR_CAA Bit Fields */
+#define CAU_RADR_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_RADR_CAA_ACC_SHIFT                   0
+#define CAU_RADR_CAA_ACC_WIDTH                   32
+#define CAU_RADR_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
+/* RADR_CA Bit Fields */
+#define CAU_RADR_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA0_SHIFT                    0
+#define CAU_RADR_CA_CA0_WIDTH                    32
+#define CAU_RADR_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
+#define CAU_RADR_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA1_SHIFT                    0
+#define CAU_RADR_CA_CA1_WIDTH                    32
+#define CAU_RADR_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
+#define CAU_RADR_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA2_SHIFT                    0
+#define CAU_RADR_CA_CA2_WIDTH                    32
+#define CAU_RADR_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
+#define CAU_RADR_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA3_SHIFT                    0
+#define CAU_RADR_CA_CA3_WIDTH                    32
+#define CAU_RADR_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
+#define CAU_RADR_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA4_SHIFT                    0
+#define CAU_RADR_CA_CA4_WIDTH                    32
+#define CAU_RADR_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
+#define CAU_RADR_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA5_SHIFT                    0
+#define CAU_RADR_CA_CA5_WIDTH                    32
+#define CAU_RADR_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
+#define CAU_RADR_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA6_SHIFT                    0
+#define CAU_RADR_CA_CA6_WIDTH                    32
+#define CAU_RADR_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
+#define CAU_RADR_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA7_SHIFT                    0
+#define CAU_RADR_CA_CA7_WIDTH                    32
+#define CAU_RADR_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
+#define CAU_RADR_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA8_SHIFT                    0
+#define CAU_RADR_CA_CA8_WIDTH                    32
+#define CAU_RADR_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
+/* XOR_CASR Bit Fields */
+#define CAU_XOR_CASR_IC_MASK                     0x1u
+#define CAU_XOR_CASR_IC_SHIFT                    0
+#define CAU_XOR_CASR_IC_WIDTH                    1
+#define CAU_XOR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_IC_SHIFT))&CAU_XOR_CASR_IC_MASK)
+#define CAU_XOR_CASR_DPE_MASK                    0x2u
+#define CAU_XOR_CASR_DPE_SHIFT                   1
+#define CAU_XOR_CASR_DPE_WIDTH                   1
+#define CAU_XOR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_DPE_SHIFT))&CAU_XOR_CASR_DPE_MASK)
+#define CAU_XOR_CASR_VER_MASK                    0xF0000000u
+#define CAU_XOR_CASR_VER_SHIFT                   28
+#define CAU_XOR_CASR_VER_WIDTH                   4
+#define CAU_XOR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
+/* XOR_CAA Bit Fields */
+#define CAU_XOR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_XOR_CAA_ACC_SHIFT                    0
+#define CAU_XOR_CAA_ACC_WIDTH                    32
+#define CAU_XOR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
+/* XOR_CA Bit Fields */
+#define CAU_XOR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA0_SHIFT                     0
+#define CAU_XOR_CA_CA0_WIDTH                     32
+#define CAU_XOR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
+#define CAU_XOR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA1_SHIFT                     0
+#define CAU_XOR_CA_CA1_WIDTH                     32
+#define CAU_XOR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
+#define CAU_XOR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA2_SHIFT                     0
+#define CAU_XOR_CA_CA2_WIDTH                     32
+#define CAU_XOR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
+#define CAU_XOR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA3_SHIFT                     0
+#define CAU_XOR_CA_CA3_WIDTH                     32
+#define CAU_XOR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
+#define CAU_XOR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA4_SHIFT                     0
+#define CAU_XOR_CA_CA4_WIDTH                     32
+#define CAU_XOR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
+#define CAU_XOR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA5_SHIFT                     0
+#define CAU_XOR_CA_CA5_WIDTH                     32
+#define CAU_XOR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
+#define CAU_XOR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA6_SHIFT                     0
+#define CAU_XOR_CA_CA6_WIDTH                     32
+#define CAU_XOR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
+#define CAU_XOR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA7_SHIFT                     0
+#define CAU_XOR_CA_CA7_WIDTH                     32
+#define CAU_XOR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
+#define CAU_XOR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA8_SHIFT                     0
+#define CAU_XOR_CA_CA8_WIDTH                     32
+#define CAU_XOR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
+/* ROTL_CASR Bit Fields */
+#define CAU_ROTL_CASR_IC_MASK                    0x1u
+#define CAU_ROTL_CASR_IC_SHIFT                   0
+#define CAU_ROTL_CASR_IC_WIDTH                   1
+#define CAU_ROTL_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_IC_SHIFT))&CAU_ROTL_CASR_IC_MASK)
+#define CAU_ROTL_CASR_DPE_MASK                   0x2u
+#define CAU_ROTL_CASR_DPE_SHIFT                  1
+#define CAU_ROTL_CASR_DPE_WIDTH                  1
+#define CAU_ROTL_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_DPE_SHIFT))&CAU_ROTL_CASR_DPE_MASK)
+#define CAU_ROTL_CASR_VER_MASK                   0xF0000000u
+#define CAU_ROTL_CASR_VER_SHIFT                  28
+#define CAU_ROTL_CASR_VER_WIDTH                  4
+#define CAU_ROTL_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
+/* ROTL_CAA Bit Fields */
+#define CAU_ROTL_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_ROTL_CAA_ACC_SHIFT                   0
+#define CAU_ROTL_CAA_ACC_WIDTH                   32
+#define CAU_ROTL_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
+/* ROTL_CA Bit Fields */
+#define CAU_ROTL_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA0_SHIFT                    0
+#define CAU_ROTL_CA_CA0_WIDTH                    32
+#define CAU_ROTL_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
+#define CAU_ROTL_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA1_SHIFT                    0
+#define CAU_ROTL_CA_CA1_WIDTH                    32
+#define CAU_ROTL_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
+#define CAU_ROTL_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA2_SHIFT                    0
+#define CAU_ROTL_CA_CA2_WIDTH                    32
+#define CAU_ROTL_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
+#define CAU_ROTL_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA3_SHIFT                    0
+#define CAU_ROTL_CA_CA3_WIDTH                    32
+#define CAU_ROTL_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
+#define CAU_ROTL_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA4_SHIFT                    0
+#define CAU_ROTL_CA_CA4_WIDTH                    32
+#define CAU_ROTL_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
+#define CAU_ROTL_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA5_SHIFT                    0
+#define CAU_ROTL_CA_CA5_WIDTH                    32
+#define CAU_ROTL_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
+#define CAU_ROTL_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA6_SHIFT                    0
+#define CAU_ROTL_CA_CA6_WIDTH                    32
+#define CAU_ROTL_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
+#define CAU_ROTL_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA7_SHIFT                    0
+#define CAU_ROTL_CA_CA7_WIDTH                    32
+#define CAU_ROTL_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
+#define CAU_ROTL_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA8_SHIFT                    0
+#define CAU_ROTL_CA_CA8_WIDTH                    32
+#define CAU_ROTL_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
+/* AESC_CASR Bit Fields */
+#define CAU_AESC_CASR_IC_MASK                    0x1u
+#define CAU_AESC_CASR_IC_SHIFT                   0
+#define CAU_AESC_CASR_IC_WIDTH                   1
+#define CAU_AESC_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_IC_SHIFT))&CAU_AESC_CASR_IC_MASK)
+#define CAU_AESC_CASR_DPE_MASK                   0x2u
+#define CAU_AESC_CASR_DPE_SHIFT                  1
+#define CAU_AESC_CASR_DPE_WIDTH                  1
+#define CAU_AESC_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_DPE_SHIFT))&CAU_AESC_CASR_DPE_MASK)
+#define CAU_AESC_CASR_VER_MASK                   0xF0000000u
+#define CAU_AESC_CASR_VER_SHIFT                  28
+#define CAU_AESC_CASR_VER_WIDTH                  4
+#define CAU_AESC_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
+/* AESC_CAA Bit Fields */
+#define CAU_AESC_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_AESC_CAA_ACC_SHIFT                   0
+#define CAU_AESC_CAA_ACC_WIDTH                   32
+#define CAU_AESC_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
+/* AESC_CA Bit Fields */
+#define CAU_AESC_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA0_SHIFT                    0
+#define CAU_AESC_CA_CA0_WIDTH                    32
+#define CAU_AESC_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
+#define CAU_AESC_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA1_SHIFT                    0
+#define CAU_AESC_CA_CA1_WIDTH                    32
+#define CAU_AESC_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
+#define CAU_AESC_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA2_SHIFT                    0
+#define CAU_AESC_CA_CA2_WIDTH                    32
+#define CAU_AESC_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
+#define CAU_AESC_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA3_SHIFT                    0
+#define CAU_AESC_CA_CA3_WIDTH                    32
+#define CAU_AESC_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
+#define CAU_AESC_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA4_SHIFT                    0
+#define CAU_AESC_CA_CA4_WIDTH                    32
+#define CAU_AESC_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
+#define CAU_AESC_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA5_SHIFT                    0
+#define CAU_AESC_CA_CA5_WIDTH                    32
+#define CAU_AESC_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
+#define CAU_AESC_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA6_SHIFT                    0
+#define CAU_AESC_CA_CA6_WIDTH                    32
+#define CAU_AESC_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
+#define CAU_AESC_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA7_SHIFT                    0
+#define CAU_AESC_CA_CA7_WIDTH                    32
+#define CAU_AESC_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
+#define CAU_AESC_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA8_SHIFT                    0
+#define CAU_AESC_CA_CA8_WIDTH                    32
+#define CAU_AESC_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
+/* AESIC_CASR Bit Fields */
+#define CAU_AESIC_CASR_IC_MASK                   0x1u
+#define CAU_AESIC_CASR_IC_SHIFT                  0
+#define CAU_AESIC_CASR_IC_WIDTH                  1
+#define CAU_AESIC_CASR_IC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_IC_SHIFT))&CAU_AESIC_CASR_IC_MASK)
+#define CAU_AESIC_CASR_DPE_MASK                  0x2u
+#define CAU_AESIC_CASR_DPE_SHIFT                 1
+#define CAU_AESIC_CASR_DPE_WIDTH                 1
+#define CAU_AESIC_CASR_DPE(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_DPE_SHIFT))&CAU_AESIC_CASR_DPE_MASK)
+#define CAU_AESIC_CASR_VER_MASK                  0xF0000000u
+#define CAU_AESIC_CASR_VER_SHIFT                 28
+#define CAU_AESIC_CASR_VER_WIDTH                 4
+#define CAU_AESIC_CASR_VER(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
+/* AESIC_CAA Bit Fields */
+#define CAU_AESIC_CAA_ACC_MASK                   0xFFFFFFFFu
+#define CAU_AESIC_CAA_ACC_SHIFT                  0
+#define CAU_AESIC_CAA_ACC_WIDTH                  32
+#define CAU_AESIC_CAA_ACC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
+/* AESIC_CA Bit Fields */
+#define CAU_AESIC_CA_CA0_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA0_SHIFT                   0
+#define CAU_AESIC_CA_CA0_WIDTH                   32
+#define CAU_AESIC_CA_CA0(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
+#define CAU_AESIC_CA_CA1_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA1_SHIFT                   0
+#define CAU_AESIC_CA_CA1_WIDTH                   32
+#define CAU_AESIC_CA_CA1(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
+#define CAU_AESIC_CA_CA2_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA2_SHIFT                   0
+#define CAU_AESIC_CA_CA2_WIDTH                   32
+#define CAU_AESIC_CA_CA2(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
+#define CAU_AESIC_CA_CA3_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA3_SHIFT                   0
+#define CAU_AESIC_CA_CA3_WIDTH                   32
+#define CAU_AESIC_CA_CA3(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
+#define CAU_AESIC_CA_CA4_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA4_SHIFT                   0
+#define CAU_AESIC_CA_CA4_WIDTH                   32
+#define CAU_AESIC_CA_CA4(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
+#define CAU_AESIC_CA_CA5_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA5_SHIFT                   0
+#define CAU_AESIC_CA_CA5_WIDTH                   32
+#define CAU_AESIC_CA_CA5(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
+#define CAU_AESIC_CA_CA6_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA6_SHIFT                   0
+#define CAU_AESIC_CA_CA6_WIDTH                   32
+#define CAU_AESIC_CA_CA6(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
+#define CAU_AESIC_CA_CA7_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA7_SHIFT                   0
+#define CAU_AESIC_CA_CA7_WIDTH                   32
+#define CAU_AESIC_CA_CA7(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
+#define CAU_AESIC_CA_CA8_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA8_SHIFT                   0
+#define CAU_AESIC_CA_CA8_WIDTH                   32
+#define CAU_AESIC_CA_CA8(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+/** Peripheral CAU base address */
+#define CAU_BASE                                 (0xE0081000u)
+/** Peripheral CAU base pointer */
+#define CAU                                      ((CAU_Type *)CAU_BASE)
+#define CAU_BASE_PTR                             (CAU)
+/** Array initializer of CAU peripheral base addresses */
+#define CAU_BASE_ADDRS                           { CAU_BASE }
+/** Array initializer of CAU peripheral base pointers */
+#define CAU_BASE_PTRS                            { CAU }
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register instance definitions */
+/* CAU */
+#define CAU_DIRECT0                              CAU_DIRECT_REG(CAU,0)
+#define CAU_DIRECT1                              CAU_DIRECT_REG(CAU,1)
+#define CAU_DIRECT2                              CAU_DIRECT_REG(CAU,2)
+#define CAU_DIRECT3                              CAU_DIRECT_REG(CAU,3)
+#define CAU_DIRECT4                              CAU_DIRECT_REG(CAU,4)
+#define CAU_DIRECT5                              CAU_DIRECT_REG(CAU,5)
+#define CAU_DIRECT6                              CAU_DIRECT_REG(CAU,6)
+#define CAU_DIRECT7                              CAU_DIRECT_REG(CAU,7)
+#define CAU_DIRECT8                              CAU_DIRECT_REG(CAU,8)
+#define CAU_DIRECT9                              CAU_DIRECT_REG(CAU,9)
+#define CAU_DIRECT10                             CAU_DIRECT_REG(CAU,10)
+#define CAU_DIRECT11                             CAU_DIRECT_REG(CAU,11)
+#define CAU_DIRECT12                             CAU_DIRECT_REG(CAU,12)
+#define CAU_DIRECT13                             CAU_DIRECT_REG(CAU,13)
+#define CAU_DIRECT14                             CAU_DIRECT_REG(CAU,14)
+#define CAU_DIRECT15                             CAU_DIRECT_REG(CAU,15)
+#define CAU_LDR_CASR                             CAU_LDR_CASR_REG(CAU)
+#define CAU_LDR_CAA                              CAU_LDR_CAA_REG(CAU)
+#define CAU_LDR_CA0                              CAU_LDR_CA_REG(CAU,0)
+#define CAU_LDR_CA1                              CAU_LDR_CA_REG(CAU,1)
+#define CAU_LDR_CA2                              CAU_LDR_CA_REG(CAU,2)
+#define CAU_LDR_CA3                              CAU_LDR_CA_REG(CAU,3)
+#define CAU_LDR_CA4                              CAU_LDR_CA_REG(CAU,4)
+#define CAU_LDR_CA5                              CAU_LDR_CA_REG(CAU,5)
+#define CAU_LDR_CA6                              CAU_LDR_CA_REG(CAU,6)
+#define CAU_LDR_CA7                              CAU_LDR_CA_REG(CAU,7)
+#define CAU_LDR_CA8                              CAU_LDR_CA_REG(CAU,8)
+#define CAU_STR_CASR                             CAU_STR_CASR_REG(CAU)
+#define CAU_STR_CAA                              CAU_STR_CAA_REG(CAU)
+#define CAU_STR_CA0                              CAU_STR_CA_REG(CAU,0)
+#define CAU_STR_CA1                              CAU_STR_CA_REG(CAU,1)
+#define CAU_STR_CA2                              CAU_STR_CA_REG(CAU,2)
+#define CAU_STR_CA3                              CAU_STR_CA_REG(CAU,3)
+#define CAU_STR_CA4                              CAU_STR_CA_REG(CAU,4)
+#define CAU_STR_CA5                              CAU_STR_CA_REG(CAU,5)
+#define CAU_STR_CA6                              CAU_STR_CA_REG(CAU,6)
+#define CAU_STR_CA7                              CAU_STR_CA_REG(CAU,7)
+#define CAU_STR_CA8                              CAU_STR_CA_REG(CAU,8)
+#define CAU_ADR_CASR                             CAU_ADR_CASR_REG(CAU)
+#define CAU_ADR_CAA                              CAU_ADR_CAA_REG(CAU)
+#define CAU_ADR_CA0                              CAU_ADR_CA_REG(CAU,0)
+#define CAU_ADR_CA1                              CAU_ADR_CA_REG(CAU,1)
+#define CAU_ADR_CA2                              CAU_ADR_CA_REG(CAU,2)
+#define CAU_ADR_CA3                              CAU_ADR_CA_REG(CAU,3)
+#define CAU_ADR_CA4                              CAU_ADR_CA_REG(CAU,4)
+#define CAU_ADR_CA5                              CAU_ADR_CA_REG(CAU,5)
+#define CAU_ADR_CA6                              CAU_ADR_CA_REG(CAU,6)
+#define CAU_ADR_CA7                              CAU_ADR_CA_REG(CAU,7)
+#define CAU_ADR_CA8                              CAU_ADR_CA_REG(CAU,8)
+#define CAU_RADR_CASR                            CAU_RADR_CASR_REG(CAU)
+#define CAU_RADR_CAA                             CAU_RADR_CAA_REG(CAU)
+#define CAU_RADR_CA0                             CAU_RADR_CA_REG(CAU,0)
+#define CAU_RADR_CA1                             CAU_RADR_CA_REG(CAU,1)
+#define CAU_RADR_CA2                             CAU_RADR_CA_REG(CAU,2)
+#define CAU_RADR_CA3                             CAU_RADR_CA_REG(CAU,3)
+#define CAU_RADR_CA4                             CAU_RADR_CA_REG(CAU,4)
+#define CAU_RADR_CA5                             CAU_RADR_CA_REG(CAU,5)
+#define CAU_RADR_CA6                             CAU_RADR_CA_REG(CAU,6)
+#define CAU_RADR_CA7                             CAU_RADR_CA_REG(CAU,7)
+#define CAU_RADR_CA8                             CAU_RADR_CA_REG(CAU,8)
+#define CAU_XOR_CASR                             CAU_XOR_CASR_REG(CAU)
+#define CAU_XOR_CAA                              CAU_XOR_CAA_REG(CAU)
+#define CAU_XOR_CA0                              CAU_XOR_CA_REG(CAU,0)
+#define CAU_XOR_CA1                              CAU_XOR_CA_REG(CAU,1)
+#define CAU_XOR_CA2                              CAU_XOR_CA_REG(CAU,2)
+#define CAU_XOR_CA3                              CAU_XOR_CA_REG(CAU,3)
+#define CAU_XOR_CA4                              CAU_XOR_CA_REG(CAU,4)
+#define CAU_XOR_CA5                              CAU_XOR_CA_REG(CAU,5)
+#define CAU_XOR_CA6                              CAU_XOR_CA_REG(CAU,6)
+#define CAU_XOR_CA7                              CAU_XOR_CA_REG(CAU,7)
+#define CAU_XOR_CA8                              CAU_XOR_CA_REG(CAU,8)
+#define CAU_ROTL_CASR                            CAU_ROTL_CASR_REG(CAU)
+#define CAU_ROTL_CAA                             CAU_ROTL_CAA_REG(CAU)
+#define CAU_ROTL_CA0                             CAU_ROTL_CA_REG(CAU,0)
+#define CAU_ROTL_CA1                             CAU_ROTL_CA_REG(CAU,1)
+#define CAU_ROTL_CA2                             CAU_ROTL_CA_REG(CAU,2)
+#define CAU_ROTL_CA3                             CAU_ROTL_CA_REG(CAU,3)
+#define CAU_ROTL_CA4                             CAU_ROTL_CA_REG(CAU,4)
+#define CAU_ROTL_CA5                             CAU_ROTL_CA_REG(CAU,5)
+#define CAU_ROTL_CA6                             CAU_ROTL_CA_REG(CAU,6)
+#define CAU_ROTL_CA7                             CAU_ROTL_CA_REG(CAU,7)
+#define CAU_ROTL_CA8                             CAU_ROTL_CA_REG(CAU,8)
+#define CAU_AESC_CASR                            CAU_AESC_CASR_REG(CAU)
+#define CAU_AESC_CAA                             CAU_AESC_CAA_REG(CAU)
+#define CAU_AESC_CA0                             CAU_AESC_CA_REG(CAU,0)
+#define CAU_AESC_CA1                             CAU_AESC_CA_REG(CAU,1)
+#define CAU_AESC_CA2                             CAU_AESC_CA_REG(CAU,2)
+#define CAU_AESC_CA3                             CAU_AESC_CA_REG(CAU,3)
+#define CAU_AESC_CA4                             CAU_AESC_CA_REG(CAU,4)
+#define CAU_AESC_CA5                             CAU_AESC_CA_REG(CAU,5)
+#define CAU_AESC_CA6                             CAU_AESC_CA_REG(CAU,6)
+#define CAU_AESC_CA7                             CAU_AESC_CA_REG(CAU,7)
+#define CAU_AESC_CA8                             CAU_AESC_CA_REG(CAU,8)
+#define CAU_AESIC_CASR                           CAU_AESIC_CASR_REG(CAU)
+#define CAU_AESIC_CAA                            CAU_AESIC_CAA_REG(CAU)
+#define CAU_AESIC_CA0                            CAU_AESIC_CA_REG(CAU,0)
+#define CAU_AESIC_CA1                            CAU_AESIC_CA_REG(CAU,1)
+#define CAU_AESIC_CA2                            CAU_AESIC_CA_REG(CAU,2)
+#define CAU_AESIC_CA3                            CAU_AESIC_CA_REG(CAU,3)
+#define CAU_AESIC_CA4                            CAU_AESIC_CA_REG(CAU,4)
+#define CAU_AESIC_CA5                            CAU_AESIC_CA_REG(CAU,5)
+#define CAU_AESIC_CA6                            CAU_AESIC_CA_REG(CAU,6)
+#define CAU_AESIC_CA7                            CAU_AESIC_CA_REG(CAU,7)
+#define CAU_AESIC_CA8                            CAU_AESIC_CA_REG(CAU,8)
+
+/* CAU - Register array accessors */
+#define CAU_DIRECT(index)                        CAU_DIRECT_REG(CAU,index)
+#define CAU_LDR_CA(index)                        CAU_LDR_CA_REG(CAU,index)
+#define CAU_STR_CA(index)                        CAU_STR_CA_REG(CAU,index)
+#define CAU_ADR_CA(index)                        CAU_ADR_CA_REG(CAU,index)
+#define CAU_RADR_CA(index)                       CAU_RADR_CA_REG(CAU,index)
+#define CAU_XOR_CA(index)                        CAU_XOR_CA_REG(CAU,index)
+#define CAU_ROTL_CA(index)                       CAU_ROTL_CA_REG(CAU,index)
+#define CAU_AESC_CA(index)                       CAU_AESC_CA_REG(CAU,index)
+#define CAU_AESIC_CA(index)                      CAU_AESIC_CA_REG(CAU,index)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base)                        ((base)->CR0)
+#define CMP_CR1_REG(base)                        ((base)->CR1)
+#define CMP_FPR_REG(base)                        ((base)->FPR)
+#define CMP_SCR_REG(base)                        ((base)->SCR)
+#define CMP_DACCR_REG(base)                      ((base)->DACCR)
+#define CMP_MUXCR_REG(base)                      ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK                     0x3u
+#define CMP_CR0_HYSTCTR_SHIFT                    0
+#define CMP_CR0_HYSTCTR_WIDTH                    2
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT                 4
+#define CMP_CR0_FILTER_CNT_WIDTH                 3
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK                          0x1u
+#define CMP_CR1_EN_SHIFT                         0
+#define CMP_CR1_EN_WIDTH                         1
+#define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK                         0x2u
+#define CMP_CR1_OPE_SHIFT                        1
+#define CMP_CR1_OPE_WIDTH                        1
+#define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK                         0x4u
+#define CMP_CR1_COS_SHIFT                        2
+#define CMP_CR1_COS_WIDTH                        1
+#define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK                         0x8u
+#define CMP_CR1_INV_SHIFT                        3
+#define CMP_CR1_INV_WIDTH                        1
+#define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK                       0x10u
+#define CMP_CR1_PMODE_SHIFT                      4
+#define CMP_CR1_PMODE_WIDTH                      1
+#define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
+#define CMP_CR1_WE_MASK                          0x40u
+#define CMP_CR1_WE_SHIFT                         6
+#define CMP_CR1_WE_WIDTH                         1
+#define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK                          0x80u
+#define CMP_CR1_SE_SHIFT                         7
+#define CMP_CR1_SE_WIDTH                         1
+#define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK                    0xFFu
+#define CMP_FPR_FILT_PER_SHIFT                   0
+#define CMP_FPR_FILT_PER_WIDTH                   8
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK                        0x1u
+#define CMP_SCR_COUT_SHIFT                       0
+#define CMP_SCR_COUT_WIDTH                       1
+#define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK                         0x2u
+#define CMP_SCR_CFF_SHIFT                        1
+#define CMP_SCR_CFF_WIDTH                        1
+#define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK                         0x4u
+#define CMP_SCR_CFR_SHIFT                        2
+#define CMP_SCR_CFR_WIDTH                        1
+#define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK                         0x8u
+#define CMP_SCR_IEF_SHIFT                        3
+#define CMP_SCR_IEF_WIDTH                        1
+#define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK                         0x10u
+#define CMP_SCR_IER_SHIFT                        4
+#define CMP_SCR_IER_WIDTH                        1
+#define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK                       0x40u
+#define CMP_SCR_DMAEN_SHIFT                      6
+#define CMP_SCR_DMAEN_WIDTH                      1
+#define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK                     0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT                    0
+#define CMP_DACCR_VOSEL_WIDTH                    6
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     0x40u
+#define CMP_DACCR_VRSEL_SHIFT                    6
+#define CMP_DACCR_VRSEL_WIDTH                    1
+#define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK                     0x80u
+#define CMP_DACCR_DACEN_SHIFT                    7
+#define CMP_DACCR_DACEN_WIDTH                    1
+#define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK                      0x7u
+#define CMP_MUXCR_MSEL_SHIFT                     0
+#define CMP_MUXCR_MSEL_WIDTH                     3
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      0x38u
+#define CMP_MUXCR_PSEL_SHIFT                     3
+#define CMP_MUXCR_PSEL_WIDTH                     3
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK                      0x80u
+#define CMP_MUXCR_PSTM_SHIFT                     7
+#define CMP_MUXCR_PSTM_WIDTH                     1
+#define CMP_MUXCR_PSTM(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSTM_SHIFT))&CMP_MUXCR_PSTM_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR                            (CMP0)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE                                (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1                                     ((CMP_Type *)CMP1_BASE)
+#define CMP1_BASE_PTR                            (CMP1)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE                                (0x40073010u)
+/** Peripheral CMP2 base pointer */
+#define CMP2                                     ((CMP_Type *)CMP2_BASE)
+#define CMP2_BASE_PTR                            (CMP2)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS                           { CMP0_BASE, CMP1_BASE, CMP2_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS                            { CMP0, CMP1, CMP2 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0                                 CMP_CR0_REG(CMP0)
+#define CMP0_CR1                                 CMP_CR1_REG(CMP0)
+#define CMP0_FPR                                 CMP_FPR_REG(CMP0)
+#define CMP0_SCR                                 CMP_SCR_REG(CMP0)
+#define CMP0_DACCR                               CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR                               CMP_MUXCR_REG(CMP0)
+/* CMP1 */
+#define CMP1_CR0                                 CMP_CR0_REG(CMP1)
+#define CMP1_CR1                                 CMP_CR1_REG(CMP1)
+#define CMP1_FPR                                 CMP_FPR_REG(CMP1)
+#define CMP1_SCR                                 CMP_SCR_REG(CMP1)
+#define CMP1_DACCR                               CMP_DACCR_REG(CMP1)
+#define CMP1_MUXCR                               CMP_MUXCR_REG(CMP1)
+/* CMP2 */
+#define CMP2_CR0                                 CMP_CR0_REG(CMP2)
+#define CMP2_CR1                                 CMP_CR1_REG(CMP2)
+#define CMP2_FPR                                 CMP_FPR_REG(CMP2)
+#define CMP2_SCR                                 CMP_SCR_REG(CMP2)
+#define CMP2_DACCR                               CMP_DACCR_REG(CMP2)
+#define CMP2_MUXCR                               CMP_MUXCR_REG(CMP2)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CGH1;                               /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+  __IO uint8_t CGL1;                               /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+  __IO uint8_t CGH2;                               /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+  __IO uint8_t CGL2;                               /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+  __IO uint8_t OC;                                 /**< CMT Output Control Register, offset: 0x4 */
+  __IO uint8_t MSC;                                /**< CMT Modulator Status and Control Register, offset: 0x5 */
+  __IO uint8_t CMD1;                               /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+  __IO uint8_t CMD2;                               /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+  __IO uint8_t CMD3;                               /**< CMT Modulator Data Register Space High, offset: 0x8 */
+  __IO uint8_t CMD4;                               /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+  __IO uint8_t PPS;                                /**< CMT Primary Prescaler Register, offset: 0xA */
+  __IO uint8_t DMA;                                /**< CMT Direct Memory Access Register, offset: 0xB */
+} CMT_Type, *CMT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register accessors */
+#define CMT_CGH1_REG(base)                       ((base)->CGH1)
+#define CMT_CGL1_REG(base)                       ((base)->CGL1)
+#define CMT_CGH2_REG(base)                       ((base)->CGH2)
+#define CMT_CGL2_REG(base)                       ((base)->CGL2)
+#define CMT_OC_REG(base)                         ((base)->OC)
+#define CMT_MSC_REG(base)                        ((base)->MSC)
+#define CMT_CMD1_REG(base)                       ((base)->CMD1)
+#define CMT_CMD2_REG(base)                       ((base)->CMD2)
+#define CMT_CMD3_REG(base)                       ((base)->CMD3)
+#define CMT_CMD4_REG(base)                       ((base)->CMD4)
+#define CMT_PPS_REG(base)                        ((base)->PPS)
+#define CMT_DMA_REG(base)                        ((base)->DMA)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK                         0xFFu
+#define CMT_CGH1_PH_SHIFT                        0
+#define CMT_CGH1_PH_WIDTH                        8
+#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK                         0xFFu
+#define CMT_CGL1_PL_SHIFT                        0
+#define CMT_CGL1_PL_WIDTH                        8
+#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK                         0xFFu
+#define CMT_CGH2_SH_SHIFT                        0
+#define CMT_CGH2_SH_WIDTH                        8
+#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK                         0xFFu
+#define CMT_CGL2_SL_SHIFT                        0
+#define CMT_CGL2_SL_WIDTH                        8
+#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK                       0x20u
+#define CMT_OC_IROPEN_SHIFT                      5
+#define CMT_OC_IROPEN_WIDTH                      1
+#define CMT_OC_IROPEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROPEN_SHIFT))&CMT_OC_IROPEN_MASK)
+#define CMT_OC_CMTPOL_MASK                       0x40u
+#define CMT_OC_CMTPOL_SHIFT                      6
+#define CMT_OC_CMTPOL_WIDTH                      1
+#define CMT_OC_CMTPOL(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_OC_CMTPOL_SHIFT))&CMT_OC_CMTPOL_MASK)
+#define CMT_OC_IROL_MASK                         0x80u
+#define CMT_OC_IROL_SHIFT                        7
+#define CMT_OC_IROL_WIDTH                        1
+#define CMT_OC_IROL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROL_SHIFT))&CMT_OC_IROL_MASK)
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK                       0x1u
+#define CMT_MSC_MCGEN_SHIFT                      0
+#define CMT_MSC_MCGEN_WIDTH                      1
+#define CMT_MSC_MCGEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_MCGEN_SHIFT))&CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_EOCIE_MASK                       0x2u
+#define CMT_MSC_EOCIE_SHIFT                      1
+#define CMT_MSC_EOCIE_WIDTH                      1
+#define CMT_MSC_EOCIE(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCIE_SHIFT))&CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_FSK_MASK                         0x4u
+#define CMT_MSC_FSK_SHIFT                        2
+#define CMT_MSC_FSK_WIDTH                        1
+#define CMT_MSC_FSK(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_MSC_FSK_SHIFT))&CMT_MSC_FSK_MASK)
+#define CMT_MSC_BASE_MASK                        0x8u
+#define CMT_MSC_BASE_SHIFT                       3
+#define CMT_MSC_BASE_WIDTH                       1
+#define CMT_MSC_BASE(x)                          (((uint8_t)(((uint8_t)(x))<<CMT_MSC_BASE_SHIFT))&CMT_MSC_BASE_MASK)
+#define CMT_MSC_EXSPC_MASK                       0x10u
+#define CMT_MSC_EXSPC_SHIFT                      4
+#define CMT_MSC_EXSPC_WIDTH                      1
+#define CMT_MSC_EXSPC(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EXSPC_SHIFT))&CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_CMTDIV_MASK                      0x60u
+#define CMT_MSC_CMTDIV_SHIFT                     5
+#define CMT_MSC_CMTDIV_WIDTH                     2
+#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK                        0x80u
+#define CMT_MSC_EOCF_SHIFT                       7
+#define CMT_MSC_EOCF_WIDTH                       1
+#define CMT_MSC_EOCF(x)                          (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCF_SHIFT))&CMT_MSC_EOCF_MASK)
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK                         0xFFu
+#define CMT_CMD1_MB_SHIFT                        0
+#define CMT_CMD1_MB_WIDTH                        8
+#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK                         0xFFu
+#define CMT_CMD2_MB_SHIFT                        0
+#define CMT_CMD2_MB_WIDTH                        8
+#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK                         0xFFu
+#define CMT_CMD3_SB_SHIFT                        0
+#define CMT_CMD3_SB_WIDTH                        8
+#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK                         0xFFu
+#define CMT_CMD4_SB_SHIFT                        0
+#define CMT_CMD4_SB_WIDTH                        8
+#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK                      0xFu
+#define CMT_PPS_PPSDIV_SHIFT                     0
+#define CMT_PPS_PPSDIV_WIDTH                     4
+#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK                         0x1u
+#define CMT_DMA_DMA_SHIFT                        0
+#define CMT_DMA_DMA_WIDTH                        1
+#define CMT_DMA_DMA(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_DMA_DMA_SHIFT))&CMT_DMA_DMA_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE                                 (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT                                      ((CMT_Type *)CMT_BASE)
+#define CMT_BASE_PTR                             (CMT)
+/** Array initializer of CMT peripheral base addresses */
+#define CMT_BASE_ADDRS                           { CMT_BASE }
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASE_PTRS                            { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS                                 { CMT_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register instance definitions */
+/* CMT */
+#define CMT_CGH1                                 CMT_CGH1_REG(CMT)
+#define CMT_CGL1                                 CMT_CGL1_REG(CMT)
+#define CMT_CGH2                                 CMT_CGH2_REG(CMT)
+#define CMT_CGL2                                 CMT_CGL2_REG(CMT)
+#define CMT_OC                                   CMT_OC_REG(CMT)
+#define CMT_MSC                                  CMT_MSC_REG(CMT)
+#define CMT_CMD1                                 CMT_CMD1_REG(CMT)
+#define CMT_CMD2                                 CMT_CMD2_REG(CMT)
+#define CMT_CMD3                                 CMT_CMD3_REG(CMT)
+#define CMT_CMD4                                 CMT_CMD4_REG(CMT)
+#define CMT_PPS                                  CMT_PPS_REG(CMT)
+#define CMT_DMA                                  CMT_DMA_REG(CMT)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type, *CRC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register accessors */
+#define CRC_DATAL_REG(base)                      ((base)->ACCESS16BIT.DATAL)
+#define CRC_DATAH_REG(base)                      ((base)->ACCESS16BIT.DATAH)
+#define CRC_DATA_REG(base)                       ((base)->DATA)
+#define CRC_DATALL_REG(base)                     ((base)->ACCESS8BIT.DATALL)
+#define CRC_DATALU_REG(base)                     ((base)->ACCESS8BIT.DATALU)
+#define CRC_DATAHL_REG(base)                     ((base)->ACCESS8BIT.DATAHL)
+#define CRC_DATAHU_REG(base)                     ((base)->ACCESS8BIT.DATAHU)
+#define CRC_GPOLYL_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYL)
+#define CRC_GPOLYH_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYH)
+#define CRC_GPOLY_REG(base)                      ((base)->GPOLY)
+#define CRC_GPOLYLL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
+#define CRC_GPOLYLU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
+#define CRC_GPOLYHL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
+#define CRC_GPOLYHU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
+#define CRC_CTRL_REG(base)                       ((base)->CTRL)
+#define CRC_CTRLHU_REG(base)                     ((base)->CTRL_ACCESS8BIT.CTRLHU)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK                     0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT                    0
+#define CRC_DATAL_DATAL_WIDTH                    16
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK                     0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT                    0
+#define CRC_DATAH_DATAH_WIDTH                    16
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK                         0xFFu
+#define CRC_DATA_LL_SHIFT                        0
+#define CRC_DATA_LL_WIDTH                        8
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         0xFF00u
+#define CRC_DATA_LU_SHIFT                        8
+#define CRC_DATA_LU_WIDTH                        8
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         0xFF0000u
+#define CRC_DATA_HL_SHIFT                        16
+#define CRC_DATA_HL_WIDTH                        8
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         0xFF000000u
+#define CRC_DATA_HU_SHIFT                        24
+#define CRC_DATA_HU_WIDTH                        8
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK                   0xFFu
+#define CRC_DATALL_DATALL_SHIFT                  0
+#define CRC_DATALL_DATALL_WIDTH                  8
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK                   0xFFu
+#define CRC_DATALU_DATALU_SHIFT                  0
+#define CRC_DATALU_DATALU_WIDTH                  8
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK                   0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT                  0
+#define CRC_DATAHL_DATAHL_WIDTH                  8
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK                   0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT                  0
+#define CRC_DATAHU_DATAHU_WIDTH                  8
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT                  0
+#define CRC_GPOLYL_GPOLYL_WIDTH                  16
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT                  0
+#define CRC_GPOLYH_GPOLYH_WIDTH                  16
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK                       0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT                      0
+#define CRC_GPOLY_LOW_WIDTH                      16
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT                     16
+#define CRC_GPOLY_HIGH_WIDTH                     16
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                0
+#define CRC_GPOLYLL_GPOLYLL_WIDTH                8
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                0
+#define CRC_GPOLYLU_GPOLYLU_WIDTH                8
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                0
+#define CRC_GPOLYHL_GPOLYHL_WIDTH                8
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                0
+#define CRC_GPOLYHU_GPOLYHU_WIDTH                8
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK                       0x1000000u
+#define CRC_CTRL_TCRC_SHIFT                      24
+#define CRC_CTRL_TCRC_WIDTH                      1
+#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK                        0x2000000u
+#define CRC_CTRL_WAS_SHIFT                       25
+#define CRC_CTRL_WAS_WIDTH                       1
+#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK                       0x4000000u
+#define CRC_CTRL_FXOR_SHIFT                      26
+#define CRC_CTRL_FXOR_WIDTH                      1
+#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK                       0x30000000u
+#define CRC_CTRL_TOTR_SHIFT                      28
+#define CRC_CTRL_TOTR_WIDTH                      2
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        0xC0000000u
+#define CRC_CTRL_TOT_SHIFT                       30
+#define CRC_CTRL_TOT_WIDTH                       2
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK                     0x1u
+#define CRC_CTRLHU_TCRC_SHIFT                    0
+#define CRC_CTRLHU_TCRC_WIDTH                    1
+#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TCRC_SHIFT))&CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK                      0x2u
+#define CRC_CTRLHU_WAS_SHIFT                     1
+#define CRC_CTRLHU_WAS_WIDTH                     1
+#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_WAS_SHIFT))&CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK                     0x4u
+#define CRC_CTRLHU_FXOR_SHIFT                    2
+#define CRC_CTRLHU_FXOR_WIDTH                    1
+#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_FXOR_SHIFT))&CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK                     0x30u
+#define CRC_CTRLHU_TOTR_SHIFT                    4
+#define CRC_CTRLHU_TOTR_WIDTH                    2
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      0xC0u
+#define CRC_CTRLHU_TOT_SHIFT                     6
+#define CRC_CTRLHU_TOT_WIDTH                     2
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+#define CRC_BASE_PTR                             (CRC0)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register instance definitions */
+/* CRC */
+#define CRC_DATA                                 CRC_DATA_REG(CRC0)
+#define CRC_DATAL                                CRC_DATAL_REG(CRC0)
+#define CRC_DATALL                               CRC_DATALL_REG(CRC0)
+#define CRC_DATALU                               CRC_DATALU_REG(CRC0)
+#define CRC_DATAH                                CRC_DATAH_REG(CRC0)
+#define CRC_DATAHL                               CRC_DATAHL_REG(CRC0)
+#define CRC_DATAHU                               CRC_DATAHU_REG(CRC0)
+#define CRC_GPOLY                                CRC_GPOLY_REG(CRC0)
+#define CRC_GPOLYL                               CRC_GPOLYL_REG(CRC0)
+#define CRC_GPOLYLL                              CRC_GPOLYLL_REG(CRC0)
+#define CRC_GPOLYLU                              CRC_GPOLYLU_REG(CRC0)
+#define CRC_GPOLYH                               CRC_GPOLYH_REG(CRC0)
+#define CRC_GPOLYHL                              CRC_GPOLYHL_REG(CRC0)
+#define CRC_GPOLYHU                              CRC_GPOLYHU_REG(CRC0)
+#define CRC_CTRL                                 CRC_CTRL_REG(CRC0)
+#define CRC_CTRLHU                               CRC_CTRLHU_REG(CRC0)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[16];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index)                 ((base)->DAT[index].DATL)
+#define DAC_DATL_COUNT                           16
+#define DAC_DATH_REG(base,index)                 ((base)->DAT[index].DATH)
+#define DAC_DATH_COUNT                           16
+#define DAC_SR_REG(base)                         ((base)->SR)
+#define DAC_C0_REG(base)                         ((base)->C0)
+#define DAC_C1_REG(base)                         ((base)->C1)
+#define DAC_C2_REG(base)                         ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK                      0xFFu
+#define DAC_DATL_DATA0_SHIFT                     0
+#define DAC_DATL_DATA0_WIDTH                     8
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK                      0xFu
+#define DAC_DATH_DATA1_SHIFT                     0
+#define DAC_DATH_DATA1_WIDTH                     4
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK                    0x1u
+#define DAC_SR_DACBFRPBF_SHIFT                   0
+#define DAC_SR_DACBFRPBF_WIDTH                   1
+#define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK                    0x2u
+#define DAC_SR_DACBFRPTF_SHIFT                   1
+#define DAC_SR_DACBFRPTF_WIDTH                   1
+#define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK                     0x4u
+#define DAC_SR_DACBFWMF_SHIFT                    2
+#define DAC_SR_DACBFWMF_WIDTH                    1
+#define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFWMF_SHIFT))&DAC_SR_DACBFWMF_MASK)
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK                     0x1u
+#define DAC_C0_DACBBIEN_SHIFT                    0
+#define DAC_C0_DACBBIEN_WIDTH                    1
+#define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK                     0x2u
+#define DAC_C0_DACBTIEN_SHIFT                    1
+#define DAC_C0_DACBTIEN_WIDTH                    1
+#define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK                     0x4u
+#define DAC_C0_DACBWIEN_SHIFT                    2
+#define DAC_C0_DACBWIEN_WIDTH                    1
+#define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBWIEN_SHIFT))&DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK                         0x8u
+#define DAC_C0_LPEN_SHIFT                        3
+#define DAC_C0_LPEN_WIDTH                        1
+#define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK                     0x10u
+#define DAC_C0_DACSWTRG_SHIFT                    4
+#define DAC_C0_DACSWTRG_WIDTH                    1
+#define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK                    0x20u
+#define DAC_C0_DACTRGSEL_SHIFT                   5
+#define DAC_C0_DACTRGSEL_WIDTH                   1
+#define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK                       0x40u
+#define DAC_C0_DACRFS_SHIFT                      6
+#define DAC_C0_DACRFS_WIDTH                      1
+#define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK                        0x80u
+#define DAC_C0_DACEN_SHIFT                       7
+#define DAC_C0_DACEN_WIDTH                       1
+#define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK                      0x1u
+#define DAC_C1_DACBFEN_SHIFT                     0
+#define DAC_C1_DACBFEN_WIDTH                     1
+#define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK                      0x6u
+#define DAC_C1_DACBFMD_SHIFT                     1
+#define DAC_C1_DACBFMD_WIDTH                     2
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK                      0x18u
+#define DAC_C1_DACBFWM_SHIFT                     3
+#define DAC_C1_DACBFWM_WIDTH                     2
+#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK                        0x80u
+#define DAC_C1_DMAEN_SHIFT                       7
+#define DAC_C1_DMAEN_WIDTH                       1
+#define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK                      0xFu
+#define DAC_C2_DACBFUP_SHIFT                     0
+#define DAC_C2_DACBFUP_WIDTH                     4
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      0xF0u
+#define DAC_C2_DACBFRP_SHIFT                     4
+#define DAC_C2_DACBFRP_WIDTH                     4
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR                            (DAC0)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE                                (0x400CD000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1                                     ((DAC_Type *)DAC1_BASE)
+#define DAC1_BASE_PTR                            (DAC1)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS                           { DAC0_BASE, DAC1_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS                            { DAC0, DAC1 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn, DAC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L                               DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H                               DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L                               DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H                               DAC_DATH_REG(DAC0,1)
+#define DAC0_DAT2L                               DAC_DATL_REG(DAC0,2)
+#define DAC0_DAT2H                               DAC_DATH_REG(DAC0,2)
+#define DAC0_DAT3L                               DAC_DATL_REG(DAC0,3)
+#define DAC0_DAT3H                               DAC_DATH_REG(DAC0,3)
+#define DAC0_DAT4L                               DAC_DATL_REG(DAC0,4)
+#define DAC0_DAT4H                               DAC_DATH_REG(DAC0,4)
+#define DAC0_DAT5L                               DAC_DATL_REG(DAC0,5)
+#define DAC0_DAT5H                               DAC_DATH_REG(DAC0,5)
+#define DAC0_DAT6L                               DAC_DATL_REG(DAC0,6)
+#define DAC0_DAT6H                               DAC_DATH_REG(DAC0,6)
+#define DAC0_DAT7L                               DAC_DATL_REG(DAC0,7)
+#define DAC0_DAT7H                               DAC_DATH_REG(DAC0,7)
+#define DAC0_DAT8L                               DAC_DATL_REG(DAC0,8)
+#define DAC0_DAT8H                               DAC_DATH_REG(DAC0,8)
+#define DAC0_DAT9L                               DAC_DATL_REG(DAC0,9)
+#define DAC0_DAT9H                               DAC_DATH_REG(DAC0,9)
+#define DAC0_DAT10L                              DAC_DATL_REG(DAC0,10)
+#define DAC0_DAT10H                              DAC_DATH_REG(DAC0,10)
+#define DAC0_DAT11L                              DAC_DATL_REG(DAC0,11)
+#define DAC0_DAT11H                              DAC_DATH_REG(DAC0,11)
+#define DAC0_DAT12L                              DAC_DATL_REG(DAC0,12)
+#define DAC0_DAT12H                              DAC_DATH_REG(DAC0,12)
+#define DAC0_DAT13L                              DAC_DATL_REG(DAC0,13)
+#define DAC0_DAT13H                              DAC_DATH_REG(DAC0,13)
+#define DAC0_DAT14L                              DAC_DATL_REG(DAC0,14)
+#define DAC0_DAT14H                              DAC_DATH_REG(DAC0,14)
+#define DAC0_DAT15L                              DAC_DATL_REG(DAC0,15)
+#define DAC0_DAT15H                              DAC_DATH_REG(DAC0,15)
+#define DAC0_SR                                  DAC_SR_REG(DAC0)
+#define DAC0_C0                                  DAC_C0_REG(DAC0)
+#define DAC0_C1                                  DAC_C1_REG(DAC0)
+#define DAC0_C2                                  DAC_C2_REG(DAC0)
+/* DAC1 */
+#define DAC1_DAT0L                               DAC_DATL_REG(DAC1,0)
+#define DAC1_DAT0H                               DAC_DATH_REG(DAC1,0)
+#define DAC1_DAT1L                               DAC_DATL_REG(DAC1,1)
+#define DAC1_DAT1H                               DAC_DATH_REG(DAC1,1)
+#define DAC1_DAT2L                               DAC_DATL_REG(DAC1,2)
+#define DAC1_DAT2H                               DAC_DATH_REG(DAC1,2)
+#define DAC1_DAT3L                               DAC_DATL_REG(DAC1,3)
+#define DAC1_DAT3H                               DAC_DATH_REG(DAC1,3)
+#define DAC1_DAT4L                               DAC_DATL_REG(DAC1,4)
+#define DAC1_DAT4H                               DAC_DATH_REG(DAC1,4)
+#define DAC1_DAT5L                               DAC_DATL_REG(DAC1,5)
+#define DAC1_DAT5H                               DAC_DATH_REG(DAC1,5)
+#define DAC1_DAT6L                               DAC_DATL_REG(DAC1,6)
+#define DAC1_DAT6H                               DAC_DATH_REG(DAC1,6)
+#define DAC1_DAT7L                               DAC_DATL_REG(DAC1,7)
+#define DAC1_DAT7H                               DAC_DATH_REG(DAC1,7)
+#define DAC1_DAT8L                               DAC_DATL_REG(DAC1,8)
+#define DAC1_DAT8H                               DAC_DATH_REG(DAC1,8)
+#define DAC1_DAT9L                               DAC_DATL_REG(DAC1,9)
+#define DAC1_DAT9H                               DAC_DATH_REG(DAC1,9)
+#define DAC1_DAT10L                              DAC_DATL_REG(DAC1,10)
+#define DAC1_DAT10H                              DAC_DATH_REG(DAC1,10)
+#define DAC1_DAT11L                              DAC_DATL_REG(DAC1,11)
+#define DAC1_DAT11H                              DAC_DATH_REG(DAC1,11)
+#define DAC1_DAT12L                              DAC_DATL_REG(DAC1,12)
+#define DAC1_DAT12H                              DAC_DATH_REG(DAC1,12)
+#define DAC1_DAT13L                              DAC_DATL_REG(DAC1,13)
+#define DAC1_DAT13H                              DAC_DATH_REG(DAC1,13)
+#define DAC1_DAT14L                              DAC_DATL_REG(DAC1,14)
+#define DAC1_DAT14H                              DAC_DATH_REG(DAC1,14)
+#define DAC1_DAT15L                              DAC_DATL_REG(DAC1,15)
+#define DAC1_DAT15H                              DAC_DATH_REG(DAC1,15)
+#define DAC1_SR                                  DAC_SR_REG(DAC1)
+#define DAC1_C0                                  DAC_C0_REG(DAC1)
+#define DAC1_C1                                  DAC_C1_REG(DAC1)
+#define DAC1_C2                                  DAC_C2_REG(DAC1)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index)                         DAC_DATL_REG(DAC0,index)
+#define DAC1_DATL(index)                         DAC_DATL_REG(DAC1,index)
+#define DAC0_DATH(index)                         DAC_DATH_REG(DAC0,index)
+#define DAC1_DATH(index)                         DAC_DATH_REG(DAC1,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[200];
+  __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /**< Channel n Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /**< Channel n Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /**< Channel n Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /**< Channel n Priority Register, offset: 0x107 */
+  __IO uint8_t DCHPRI11;                           /**< Channel n Priority Register, offset: 0x108 */
+  __IO uint8_t DCHPRI10;                           /**< Channel n Priority Register, offset: 0x109 */
+  __IO uint8_t DCHPRI9;                            /**< Channel n Priority Register, offset: 0x10A */
+  __IO uint8_t DCHPRI8;                            /**< Channel n Priority Register, offset: 0x10B */
+  __IO uint8_t DCHPRI15;                           /**< Channel n Priority Register, offset: 0x10C */
+  __IO uint8_t DCHPRI14;                           /**< Channel n Priority Register, offset: 0x10D */
+  __IO uint8_t DCHPRI13;                           /**< Channel n Priority Register, offset: 0x10E */
+  __IO uint8_t DCHPRI12;                           /**< Channel n Priority Register, offset: 0x10F */
+       uint8_t RESERVED_6[3824];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[16];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_CR_REG(base)                         ((base)->CR)
+#define DMA_ES_REG(base)                         ((base)->ES)
+#define DMA_ERQ_REG(base)                        ((base)->ERQ)
+#define DMA_EEI_REG(base)                        ((base)->EEI)
+#define DMA_CEEI_REG(base)                       ((base)->CEEI)
+#define DMA_SEEI_REG(base)                       ((base)->SEEI)
+#define DMA_CERQ_REG(base)                       ((base)->CERQ)
+#define DMA_SERQ_REG(base)                       ((base)->SERQ)
+#define DMA_CDNE_REG(base)                       ((base)->CDNE)
+#define DMA_SSRT_REG(base)                       ((base)->SSRT)
+#define DMA_CERR_REG(base)                       ((base)->CERR)
+#define DMA_CINT_REG(base)                       ((base)->CINT)
+#define DMA_INT_REG(base)                        ((base)->INT)
+#define DMA_ERR_REG(base)                        ((base)->ERR)
+#define DMA_HRS_REG(base)                        ((base)->HRS)
+#define DMA_DCHPRI3_REG(base)                    ((base)->DCHPRI3)
+#define DMA_DCHPRI2_REG(base)                    ((base)->DCHPRI2)
+#define DMA_DCHPRI1_REG(base)                    ((base)->DCHPRI1)
+#define DMA_DCHPRI0_REG(base)                    ((base)->DCHPRI0)
+#define DMA_DCHPRI7_REG(base)                    ((base)->DCHPRI7)
+#define DMA_DCHPRI6_REG(base)                    ((base)->DCHPRI6)
+#define DMA_DCHPRI5_REG(base)                    ((base)->DCHPRI5)
+#define DMA_DCHPRI4_REG(base)                    ((base)->DCHPRI4)
+#define DMA_DCHPRI11_REG(base)                   ((base)->DCHPRI11)
+#define DMA_DCHPRI10_REG(base)                   ((base)->DCHPRI10)
+#define DMA_DCHPRI9_REG(base)                    ((base)->DCHPRI9)
+#define DMA_DCHPRI8_REG(base)                    ((base)->DCHPRI8)
+#define DMA_DCHPRI15_REG(base)                   ((base)->DCHPRI15)
+#define DMA_DCHPRI14_REG(base)                   ((base)->DCHPRI14)
+#define DMA_DCHPRI13_REG(base)                   ((base)->DCHPRI13)
+#define DMA_DCHPRI12_REG(base)                   ((base)->DCHPRI12)
+#define DMA_SADDR_REG(base,index)                ((base)->TCD[index].SADDR)
+#define DMA_SADDR_COUNT                          16
+#define DMA_SOFF_REG(base,index)                 ((base)->TCD[index].SOFF)
+#define DMA_SOFF_COUNT                           16
+#define DMA_ATTR_REG(base,index)                 ((base)->TCD[index].ATTR)
+#define DMA_ATTR_COUNT                           16
+#define DMA_NBYTES_MLNO_REG(base,index)          ((base)->TCD[index].NBYTES_MLNO)
+#define DMA_NBYTES_MLNO_COUNT                    16
+#define DMA_NBYTES_MLOFFNO_REG(base,index)       ((base)->TCD[index].NBYTES_MLOFFNO)
+#define DMA_NBYTES_MLOFFNO_COUNT                 16
+#define DMA_NBYTES_MLOFFYES_REG(base,index)      ((base)->TCD[index].NBYTES_MLOFFYES)
+#define DMA_NBYTES_MLOFFYES_COUNT                16
+#define DMA_SLAST_REG(base,index)                ((base)->TCD[index].SLAST)
+#define DMA_SLAST_COUNT                          16
+#define DMA_DADDR_REG(base,index)                ((base)->TCD[index].DADDR)
+#define DMA_DADDR_COUNT                          16
+#define DMA_DOFF_REG(base,index)                 ((base)->TCD[index].DOFF)
+#define DMA_DOFF_COUNT                           16
+#define DMA_CITER_ELINKNO_REG(base,index)        ((base)->TCD[index].CITER_ELINKNO)
+#define DMA_CITER_ELINKNO_COUNT                  16
+#define DMA_CITER_ELINKYES_REG(base,index)       ((base)->TCD[index].CITER_ELINKYES)
+#define DMA_CITER_ELINKYES_COUNT                 16
+#define DMA_DLAST_SGA_REG(base,index)            ((base)->TCD[index].DLAST_SGA)
+#define DMA_DLAST_SGA_COUNT                      16
+#define DMA_CSR_REG(base,index)                  ((base)->TCD[index].CSR)
+#define DMA_CSR_COUNT                            16
+#define DMA_BITER_ELINKNO_REG(base,index)        ((base)->TCD[index].BITER_ELINKNO)
+#define DMA_BITER_ELINKNO_COUNT                  16
+#define DMA_BITER_ELINKYES_REG(base,index)       ((base)->TCD[index].BITER_ELINKYES)
+#define DMA_BITER_ELINKYES_COUNT                 16
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK                         0x2u
+#define DMA_CR_EDBG_SHIFT                        1
+#define DMA_CR_EDBG_WIDTH                        1
+#define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK                         0x4u
+#define DMA_CR_ERCA_SHIFT                        2
+#define DMA_CR_ERCA_WIDTH                        1
+#define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK                          0x10u
+#define DMA_CR_HOE_SHIFT                         4
+#define DMA_CR_HOE_WIDTH                         1
+#define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK                         0x20u
+#define DMA_CR_HALT_SHIFT                        5
+#define DMA_CR_HALT_WIDTH                        1
+#define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK                          0x40u
+#define DMA_CR_CLM_SHIFT                         6
+#define DMA_CR_CLM_WIDTH                         1
+#define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK                         0x80u
+#define DMA_CR_EMLM_SHIFT                        7
+#define DMA_CR_EMLM_WIDTH                        1
+#define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK                          0x10000u
+#define DMA_CR_ECX_SHIFT                         16
+#define DMA_CR_ECX_WIDTH                         1
+#define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK                           0x20000u
+#define DMA_CR_CX_SHIFT                          17
+#define DMA_CR_CX_WIDTH                          1
+#define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK                          0x1u
+#define DMA_ES_DBE_SHIFT                         0
+#define DMA_ES_DBE_WIDTH                         1
+#define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK                          0x2u
+#define DMA_ES_SBE_SHIFT                         1
+#define DMA_ES_SBE_WIDTH                         1
+#define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK                          0x4u
+#define DMA_ES_SGE_SHIFT                         2
+#define DMA_ES_SGE_WIDTH                         1
+#define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK                          0x8u
+#define DMA_ES_NCE_SHIFT                         3
+#define DMA_ES_NCE_WIDTH                         1
+#define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK                          0x10u
+#define DMA_ES_DOE_SHIFT                         4
+#define DMA_ES_DOE_WIDTH                         1
+#define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK                          0x20u
+#define DMA_ES_DAE_SHIFT                         5
+#define DMA_ES_DAE_WIDTH                         1
+#define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK                          0x40u
+#define DMA_ES_SOE_SHIFT                         6
+#define DMA_ES_SOE_WIDTH                         1
+#define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK                          0x80u
+#define DMA_ES_SAE_SHIFT                         7
+#define DMA_ES_SAE_WIDTH                         1
+#define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK                       0xF00u
+#define DMA_ES_ERRCHN_SHIFT                      8
+#define DMA_ES_ERRCHN_WIDTH                      4
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          0x4000u
+#define DMA_ES_CPE_SHIFT                         14
+#define DMA_ES_CPE_WIDTH                         1
+#define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK                          0x10000u
+#define DMA_ES_ECX_SHIFT                         16
+#define DMA_ES_ECX_WIDTH                         1
+#define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK                          0x80000000u
+#define DMA_ES_VLD_SHIFT                         31
+#define DMA_ES_VLD_WIDTH                         1
+#define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK                        0x1u
+#define DMA_ERQ_ERQ0_SHIFT                       0
+#define DMA_ERQ_ERQ0_WIDTH                       1
+#define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK                        0x2u
+#define DMA_ERQ_ERQ1_SHIFT                       1
+#define DMA_ERQ_ERQ1_WIDTH                       1
+#define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK                        0x4u
+#define DMA_ERQ_ERQ2_SHIFT                       2
+#define DMA_ERQ_ERQ2_WIDTH                       1
+#define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK                        0x8u
+#define DMA_ERQ_ERQ3_SHIFT                       3
+#define DMA_ERQ_ERQ3_WIDTH                       1
+#define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK                        0x10u
+#define DMA_ERQ_ERQ4_SHIFT                       4
+#define DMA_ERQ_ERQ4_WIDTH                       1
+#define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK                        0x20u
+#define DMA_ERQ_ERQ5_SHIFT                       5
+#define DMA_ERQ_ERQ5_WIDTH                       1
+#define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK                        0x40u
+#define DMA_ERQ_ERQ6_SHIFT                       6
+#define DMA_ERQ_ERQ6_WIDTH                       1
+#define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK                        0x80u
+#define DMA_ERQ_ERQ7_SHIFT                       7
+#define DMA_ERQ_ERQ7_WIDTH                       1
+#define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK                        0x100u
+#define DMA_ERQ_ERQ8_SHIFT                       8
+#define DMA_ERQ_ERQ8_WIDTH                       1
+#define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK                        0x200u
+#define DMA_ERQ_ERQ9_SHIFT                       9
+#define DMA_ERQ_ERQ9_WIDTH                       1
+#define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK                       0x400u
+#define DMA_ERQ_ERQ10_SHIFT                      10
+#define DMA_ERQ_ERQ10_WIDTH                      1
+#define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK                       0x800u
+#define DMA_ERQ_ERQ11_SHIFT                      11
+#define DMA_ERQ_ERQ11_WIDTH                      1
+#define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK                       0x1000u
+#define DMA_ERQ_ERQ12_SHIFT                      12
+#define DMA_ERQ_ERQ12_WIDTH                      1
+#define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK                       0x2000u
+#define DMA_ERQ_ERQ13_SHIFT                      13
+#define DMA_ERQ_ERQ13_WIDTH                      1
+#define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK                       0x4000u
+#define DMA_ERQ_ERQ14_SHIFT                      14
+#define DMA_ERQ_ERQ14_WIDTH                      1
+#define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK                       0x8000u
+#define DMA_ERQ_ERQ15_SHIFT                      15
+#define DMA_ERQ_ERQ15_WIDTH                      1
+#define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK                        0x1u
+#define DMA_EEI_EEI0_SHIFT                       0
+#define DMA_EEI_EEI0_WIDTH                       1
+#define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK                        0x2u
+#define DMA_EEI_EEI1_SHIFT                       1
+#define DMA_EEI_EEI1_WIDTH                       1
+#define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK                        0x4u
+#define DMA_EEI_EEI2_SHIFT                       2
+#define DMA_EEI_EEI2_WIDTH                       1
+#define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK                        0x8u
+#define DMA_EEI_EEI3_SHIFT                       3
+#define DMA_EEI_EEI3_WIDTH                       1
+#define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK                        0x10u
+#define DMA_EEI_EEI4_SHIFT                       4
+#define DMA_EEI_EEI4_WIDTH                       1
+#define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK                        0x20u
+#define DMA_EEI_EEI5_SHIFT                       5
+#define DMA_EEI_EEI5_WIDTH                       1
+#define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK                        0x40u
+#define DMA_EEI_EEI6_SHIFT                       6
+#define DMA_EEI_EEI6_WIDTH                       1
+#define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK                        0x80u
+#define DMA_EEI_EEI7_SHIFT                       7
+#define DMA_EEI_EEI7_WIDTH                       1
+#define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK                        0x100u
+#define DMA_EEI_EEI8_SHIFT                       8
+#define DMA_EEI_EEI8_WIDTH                       1
+#define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK                        0x200u
+#define DMA_EEI_EEI9_SHIFT                       9
+#define DMA_EEI_EEI9_WIDTH                       1
+#define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK                       0x400u
+#define DMA_EEI_EEI10_SHIFT                      10
+#define DMA_EEI_EEI10_WIDTH                      1
+#define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK                       0x800u
+#define DMA_EEI_EEI11_SHIFT                      11
+#define DMA_EEI_EEI11_WIDTH                      1
+#define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK                       0x1000u
+#define DMA_EEI_EEI12_SHIFT                      12
+#define DMA_EEI_EEI12_WIDTH                      1
+#define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK                       0x2000u
+#define DMA_EEI_EEI13_SHIFT                      13
+#define DMA_EEI_EEI13_WIDTH                      1
+#define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK                       0x4000u
+#define DMA_EEI_EEI14_SHIFT                      14
+#define DMA_EEI_EEI14_WIDTH                      1
+#define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK                       0x8000u
+#define DMA_EEI_EEI15_SHIFT                      15
+#define DMA_EEI_EEI15_WIDTH                      1
+#define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK                       0xFu
+#define DMA_CEEI_CEEI_SHIFT                      0
+#define DMA_CEEI_CEEI_WIDTH                      4
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       0x40u
+#define DMA_CEEI_CAEE_SHIFT                      6
+#define DMA_CEEI_CAEE_WIDTH                      1
+#define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK                        0x80u
+#define DMA_CEEI_NOP_SHIFT                       7
+#define DMA_CEEI_NOP_WIDTH                       1
+#define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK                       0xFu
+#define DMA_SEEI_SEEI_SHIFT                      0
+#define DMA_SEEI_SEEI_WIDTH                      4
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       0x40u
+#define DMA_SEEI_SAEE_SHIFT                      6
+#define DMA_SEEI_SAEE_WIDTH                      1
+#define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK                        0x80u
+#define DMA_SEEI_NOP_SHIFT                       7
+#define DMA_SEEI_NOP_WIDTH                       1
+#define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK                       0xFu
+#define DMA_CERQ_CERQ_SHIFT                      0
+#define DMA_CERQ_CERQ_WIDTH                      4
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       0x40u
+#define DMA_CERQ_CAER_SHIFT                      6
+#define DMA_CERQ_CAER_WIDTH                      1
+#define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK                        0x80u
+#define DMA_CERQ_NOP_SHIFT                       7
+#define DMA_CERQ_NOP_WIDTH                       1
+#define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK                       0xFu
+#define DMA_SERQ_SERQ_SHIFT                      0
+#define DMA_SERQ_SERQ_WIDTH                      4
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       0x40u
+#define DMA_SERQ_SAER_SHIFT                      6
+#define DMA_SERQ_SAER_WIDTH                      1
+#define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK                        0x80u
+#define DMA_SERQ_NOP_SHIFT                       7
+#define DMA_SERQ_NOP_WIDTH                       1
+#define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK                       0xFu
+#define DMA_CDNE_CDNE_SHIFT                      0
+#define DMA_CDNE_CDNE_WIDTH                      4
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       0x40u
+#define DMA_CDNE_CADN_SHIFT                      6
+#define DMA_CDNE_CADN_WIDTH                      1
+#define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK                        0x80u
+#define DMA_CDNE_NOP_SHIFT                       7
+#define DMA_CDNE_NOP_WIDTH                       1
+#define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK                       0xFu
+#define DMA_SSRT_SSRT_SHIFT                      0
+#define DMA_SSRT_SSRT_WIDTH                      4
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       0x40u
+#define DMA_SSRT_SAST_SHIFT                      6
+#define DMA_SSRT_SAST_WIDTH                      1
+#define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK                        0x80u
+#define DMA_SSRT_NOP_SHIFT                       7
+#define DMA_SSRT_NOP_WIDTH                       1
+#define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK                       0xFu
+#define DMA_CERR_CERR_SHIFT                      0
+#define DMA_CERR_CERR_WIDTH                      4
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       0x40u
+#define DMA_CERR_CAEI_SHIFT                      6
+#define DMA_CERR_CAEI_WIDTH                      1
+#define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK                        0x80u
+#define DMA_CERR_NOP_SHIFT                       7
+#define DMA_CERR_NOP_WIDTH                       1
+#define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK                       0xFu
+#define DMA_CINT_CINT_SHIFT                      0
+#define DMA_CINT_CINT_WIDTH                      4
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       0x40u
+#define DMA_CINT_CAIR_SHIFT                      6
+#define DMA_CINT_CAIR_WIDTH                      1
+#define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK                        0x80u
+#define DMA_CINT_NOP_SHIFT                       7
+#define DMA_CINT_NOP_WIDTH                       1
+#define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK                        0x1u
+#define DMA_INT_INT0_SHIFT                       0
+#define DMA_INT_INT0_WIDTH                       1
+#define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK                        0x2u
+#define DMA_INT_INT1_SHIFT                       1
+#define DMA_INT_INT1_WIDTH                       1
+#define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK                        0x4u
+#define DMA_INT_INT2_SHIFT                       2
+#define DMA_INT_INT2_WIDTH                       1
+#define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK                        0x8u
+#define DMA_INT_INT3_SHIFT                       3
+#define DMA_INT_INT3_WIDTH                       1
+#define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK                        0x10u
+#define DMA_INT_INT4_SHIFT                       4
+#define DMA_INT_INT4_WIDTH                       1
+#define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK                        0x20u
+#define DMA_INT_INT5_SHIFT                       5
+#define DMA_INT_INT5_WIDTH                       1
+#define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK                        0x40u
+#define DMA_INT_INT6_SHIFT                       6
+#define DMA_INT_INT6_WIDTH                       1
+#define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK                        0x80u
+#define DMA_INT_INT7_SHIFT                       7
+#define DMA_INT_INT7_WIDTH                       1
+#define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK                        0x100u
+#define DMA_INT_INT8_SHIFT                       8
+#define DMA_INT_INT8_WIDTH                       1
+#define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK                        0x200u
+#define DMA_INT_INT9_SHIFT                       9
+#define DMA_INT_INT9_WIDTH                       1
+#define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK                       0x400u
+#define DMA_INT_INT10_SHIFT                      10
+#define DMA_INT_INT10_WIDTH                      1
+#define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK                       0x800u
+#define DMA_INT_INT11_SHIFT                      11
+#define DMA_INT_INT11_WIDTH                      1
+#define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK                       0x1000u
+#define DMA_INT_INT12_SHIFT                      12
+#define DMA_INT_INT12_WIDTH                      1
+#define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK                       0x2000u
+#define DMA_INT_INT13_SHIFT                      13
+#define DMA_INT_INT13_WIDTH                      1
+#define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK                       0x4000u
+#define DMA_INT_INT14_SHIFT                      14
+#define DMA_INT_INT14_WIDTH                      1
+#define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK                       0x8000u
+#define DMA_INT_INT15_SHIFT                      15
+#define DMA_INT_INT15_WIDTH                      1
+#define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK                        0x1u
+#define DMA_ERR_ERR0_SHIFT                       0
+#define DMA_ERR_ERR0_WIDTH                       1
+#define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK                        0x2u
+#define DMA_ERR_ERR1_SHIFT                       1
+#define DMA_ERR_ERR1_WIDTH                       1
+#define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK                        0x4u
+#define DMA_ERR_ERR2_SHIFT                       2
+#define DMA_ERR_ERR2_WIDTH                       1
+#define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK                        0x8u
+#define DMA_ERR_ERR3_SHIFT                       3
+#define DMA_ERR_ERR3_WIDTH                       1
+#define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK                        0x10u
+#define DMA_ERR_ERR4_SHIFT                       4
+#define DMA_ERR_ERR4_WIDTH                       1
+#define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK                        0x20u
+#define DMA_ERR_ERR5_SHIFT                       5
+#define DMA_ERR_ERR5_WIDTH                       1
+#define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK                        0x40u
+#define DMA_ERR_ERR6_SHIFT                       6
+#define DMA_ERR_ERR6_WIDTH                       1
+#define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK                        0x80u
+#define DMA_ERR_ERR7_SHIFT                       7
+#define DMA_ERR_ERR7_WIDTH                       1
+#define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK                        0x100u
+#define DMA_ERR_ERR8_SHIFT                       8
+#define DMA_ERR_ERR8_WIDTH                       1
+#define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK                        0x200u
+#define DMA_ERR_ERR9_SHIFT                       9
+#define DMA_ERR_ERR9_WIDTH                       1
+#define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK                       0x400u
+#define DMA_ERR_ERR10_SHIFT                      10
+#define DMA_ERR_ERR10_WIDTH                      1
+#define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK                       0x800u
+#define DMA_ERR_ERR11_SHIFT                      11
+#define DMA_ERR_ERR11_WIDTH                      1
+#define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK                       0x1000u
+#define DMA_ERR_ERR12_SHIFT                      12
+#define DMA_ERR_ERR12_WIDTH                      1
+#define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK                       0x2000u
+#define DMA_ERR_ERR13_SHIFT                      13
+#define DMA_ERR_ERR13_WIDTH                      1
+#define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK                       0x4000u
+#define DMA_ERR_ERR14_SHIFT                      14
+#define DMA_ERR_ERR14_WIDTH                      1
+#define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK                       0x8000u
+#define DMA_ERR_ERR15_SHIFT                      15
+#define DMA_ERR_ERR15_WIDTH                      1
+#define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK                        0x1u
+#define DMA_HRS_HRS0_SHIFT                       0
+#define DMA_HRS_HRS0_WIDTH                       1
+#define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK                        0x2u
+#define DMA_HRS_HRS1_SHIFT                       1
+#define DMA_HRS_HRS1_WIDTH                       1
+#define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK                        0x4u
+#define DMA_HRS_HRS2_SHIFT                       2
+#define DMA_HRS_HRS2_WIDTH                       1
+#define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK                        0x8u
+#define DMA_HRS_HRS3_SHIFT                       3
+#define DMA_HRS_HRS3_WIDTH                       1
+#define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK                        0x10u
+#define DMA_HRS_HRS4_SHIFT                       4
+#define DMA_HRS_HRS4_WIDTH                       1
+#define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK                        0x20u
+#define DMA_HRS_HRS5_SHIFT                       5
+#define DMA_HRS_HRS5_WIDTH                       1
+#define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK                        0x40u
+#define DMA_HRS_HRS6_SHIFT                       6
+#define DMA_HRS_HRS6_WIDTH                       1
+#define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK                        0x80u
+#define DMA_HRS_HRS7_SHIFT                       7
+#define DMA_HRS_HRS7_WIDTH                       1
+#define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK                        0x100u
+#define DMA_HRS_HRS8_SHIFT                       8
+#define DMA_HRS_HRS8_WIDTH                       1
+#define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK                        0x200u
+#define DMA_HRS_HRS9_SHIFT                       9
+#define DMA_HRS_HRS9_WIDTH                       1
+#define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK                       0x400u
+#define DMA_HRS_HRS10_SHIFT                      10
+#define DMA_HRS_HRS10_WIDTH                      1
+#define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK                       0x800u
+#define DMA_HRS_HRS11_SHIFT                      11
+#define DMA_HRS_HRS11_WIDTH                      1
+#define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK                       0x1000u
+#define DMA_HRS_HRS12_SHIFT                      12
+#define DMA_HRS_HRS12_WIDTH                      1
+#define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK                       0x2000u
+#define DMA_HRS_HRS13_SHIFT                      13
+#define DMA_HRS_HRS13_WIDTH                      1
+#define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK                       0x4000u
+#define DMA_HRS_HRS14_SHIFT                      14
+#define DMA_HRS_HRS14_WIDTH                      1
+#define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK                       0x8000u
+#define DMA_HRS_HRS15_SHIFT                      15
+#define DMA_HRS_HRS15_WIDTH                      1
+#define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT                  0
+#define DMA_DCHPRI3_CHPRI_WIDTH                  4
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     0x40u
+#define DMA_DCHPRI3_DPA_SHIFT                    6
+#define DMA_DCHPRI3_DPA_WIDTH                    1
+#define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_DPA_SHIFT))&DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK                     0x80u
+#define DMA_DCHPRI3_ECP_SHIFT                    7
+#define DMA_DCHPRI3_ECP_WIDTH                    1
+#define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_ECP_SHIFT))&DMA_DCHPRI3_ECP_MASK)
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT                  0
+#define DMA_DCHPRI2_CHPRI_WIDTH                  4
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     0x40u
+#define DMA_DCHPRI2_DPA_SHIFT                    6
+#define DMA_DCHPRI2_DPA_WIDTH                    1
+#define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_DPA_SHIFT))&DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK                     0x80u
+#define DMA_DCHPRI2_ECP_SHIFT                    7
+#define DMA_DCHPRI2_ECP_WIDTH                    1
+#define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_ECP_SHIFT))&DMA_DCHPRI2_ECP_MASK)
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT                  0
+#define DMA_DCHPRI1_CHPRI_WIDTH                  4
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     0x40u
+#define DMA_DCHPRI1_DPA_SHIFT                    6
+#define DMA_DCHPRI1_DPA_WIDTH                    1
+#define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_DPA_SHIFT))&DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK                     0x80u
+#define DMA_DCHPRI1_ECP_SHIFT                    7
+#define DMA_DCHPRI1_ECP_WIDTH                    1
+#define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_ECP_SHIFT))&DMA_DCHPRI1_ECP_MASK)
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT                  0
+#define DMA_DCHPRI0_CHPRI_WIDTH                  4
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     0x40u
+#define DMA_DCHPRI0_DPA_SHIFT                    6
+#define DMA_DCHPRI0_DPA_WIDTH                    1
+#define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_DPA_SHIFT))&DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK                     0x80u
+#define DMA_DCHPRI0_ECP_SHIFT                    7
+#define DMA_DCHPRI0_ECP_WIDTH                    1
+#define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_ECP_SHIFT))&DMA_DCHPRI0_ECP_MASK)
+/* DCHPRI7 Bit Fields */
+#define DMA_DCHPRI7_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI7_CHPRI_SHIFT                  0
+#define DMA_DCHPRI7_CHPRI_WIDTH                  4
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     0x40u
+#define DMA_DCHPRI7_DPA_SHIFT                    6
+#define DMA_DCHPRI7_DPA_WIDTH                    1
+#define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_DPA_SHIFT))&DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK                     0x80u
+#define DMA_DCHPRI7_ECP_SHIFT                    7
+#define DMA_DCHPRI7_ECP_WIDTH                    1
+#define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_ECP_SHIFT))&DMA_DCHPRI7_ECP_MASK)
+/* DCHPRI6 Bit Fields */
+#define DMA_DCHPRI6_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI6_CHPRI_SHIFT                  0
+#define DMA_DCHPRI6_CHPRI_WIDTH                  4
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     0x40u
+#define DMA_DCHPRI6_DPA_SHIFT                    6
+#define DMA_DCHPRI6_DPA_WIDTH                    1
+#define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_DPA_SHIFT))&DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK                     0x80u
+#define DMA_DCHPRI6_ECP_SHIFT                    7
+#define DMA_DCHPRI6_ECP_WIDTH                    1
+#define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_ECP_SHIFT))&DMA_DCHPRI6_ECP_MASK)
+/* DCHPRI5 Bit Fields */
+#define DMA_DCHPRI5_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI5_CHPRI_SHIFT                  0
+#define DMA_DCHPRI5_CHPRI_WIDTH                  4
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     0x40u
+#define DMA_DCHPRI5_DPA_SHIFT                    6
+#define DMA_DCHPRI5_DPA_WIDTH                    1
+#define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_DPA_SHIFT))&DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK                     0x80u
+#define DMA_DCHPRI5_ECP_SHIFT                    7
+#define DMA_DCHPRI5_ECP_WIDTH                    1
+#define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_ECP_SHIFT))&DMA_DCHPRI5_ECP_MASK)
+/* DCHPRI4 Bit Fields */
+#define DMA_DCHPRI4_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI4_CHPRI_SHIFT                  0
+#define DMA_DCHPRI4_CHPRI_WIDTH                  4
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     0x40u
+#define DMA_DCHPRI4_DPA_SHIFT                    6
+#define DMA_DCHPRI4_DPA_WIDTH                    1
+#define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_DPA_SHIFT))&DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK                     0x80u
+#define DMA_DCHPRI4_ECP_SHIFT                    7
+#define DMA_DCHPRI4_ECP_WIDTH                    1
+#define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_ECP_SHIFT))&DMA_DCHPRI4_ECP_MASK)
+/* DCHPRI11 Bit Fields */
+#define DMA_DCHPRI11_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI11_CHPRI_SHIFT                 0
+#define DMA_DCHPRI11_CHPRI_WIDTH                 4
+#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK                    0x40u
+#define DMA_DCHPRI11_DPA_SHIFT                   6
+#define DMA_DCHPRI11_DPA_WIDTH                   1
+#define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_DPA_SHIFT))&DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_ECP_MASK                    0x80u
+#define DMA_DCHPRI11_ECP_SHIFT                   7
+#define DMA_DCHPRI11_ECP_WIDTH                   1
+#define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_ECP_SHIFT))&DMA_DCHPRI11_ECP_MASK)
+/* DCHPRI10 Bit Fields */
+#define DMA_DCHPRI10_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI10_CHPRI_SHIFT                 0
+#define DMA_DCHPRI10_CHPRI_WIDTH                 4
+#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK                    0x40u
+#define DMA_DCHPRI10_DPA_SHIFT                   6
+#define DMA_DCHPRI10_DPA_WIDTH                   1
+#define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_DPA_SHIFT))&DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_ECP_MASK                    0x80u
+#define DMA_DCHPRI10_ECP_SHIFT                   7
+#define DMA_DCHPRI10_ECP_WIDTH                   1
+#define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_ECP_SHIFT))&DMA_DCHPRI10_ECP_MASK)
+/* DCHPRI9 Bit Fields */
+#define DMA_DCHPRI9_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI9_CHPRI_SHIFT                  0
+#define DMA_DCHPRI9_CHPRI_WIDTH                  4
+#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK                     0x40u
+#define DMA_DCHPRI9_DPA_SHIFT                    6
+#define DMA_DCHPRI9_DPA_WIDTH                    1
+#define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_DPA_SHIFT))&DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_ECP_MASK                     0x80u
+#define DMA_DCHPRI9_ECP_SHIFT                    7
+#define DMA_DCHPRI9_ECP_WIDTH                    1
+#define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_ECP_SHIFT))&DMA_DCHPRI9_ECP_MASK)
+/* DCHPRI8 Bit Fields */
+#define DMA_DCHPRI8_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI8_CHPRI_SHIFT                  0
+#define DMA_DCHPRI8_CHPRI_WIDTH                  4
+#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK                     0x40u
+#define DMA_DCHPRI8_DPA_SHIFT                    6
+#define DMA_DCHPRI8_DPA_WIDTH                    1
+#define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_DPA_SHIFT))&DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_ECP_MASK                     0x80u
+#define DMA_DCHPRI8_ECP_SHIFT                    7
+#define DMA_DCHPRI8_ECP_WIDTH                    1
+#define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_ECP_SHIFT))&DMA_DCHPRI8_ECP_MASK)
+/* DCHPRI15 Bit Fields */
+#define DMA_DCHPRI15_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI15_CHPRI_SHIFT                 0
+#define DMA_DCHPRI15_CHPRI_WIDTH                 4
+#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK                    0x40u
+#define DMA_DCHPRI15_DPA_SHIFT                   6
+#define DMA_DCHPRI15_DPA_WIDTH                   1
+#define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_DPA_SHIFT))&DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_ECP_MASK                    0x80u
+#define DMA_DCHPRI15_ECP_SHIFT                   7
+#define DMA_DCHPRI15_ECP_WIDTH                   1
+#define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_ECP_SHIFT))&DMA_DCHPRI15_ECP_MASK)
+/* DCHPRI14 Bit Fields */
+#define DMA_DCHPRI14_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI14_CHPRI_SHIFT                 0
+#define DMA_DCHPRI14_CHPRI_WIDTH                 4
+#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK                    0x40u
+#define DMA_DCHPRI14_DPA_SHIFT                   6
+#define DMA_DCHPRI14_DPA_WIDTH                   1
+#define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_DPA_SHIFT))&DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_ECP_MASK                    0x80u
+#define DMA_DCHPRI14_ECP_SHIFT                   7
+#define DMA_DCHPRI14_ECP_WIDTH                   1
+#define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_ECP_SHIFT))&DMA_DCHPRI14_ECP_MASK)
+/* DCHPRI13 Bit Fields */
+#define DMA_DCHPRI13_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI13_CHPRI_SHIFT                 0
+#define DMA_DCHPRI13_CHPRI_WIDTH                 4
+#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK                    0x40u
+#define DMA_DCHPRI13_DPA_SHIFT                   6
+#define DMA_DCHPRI13_DPA_WIDTH                   1
+#define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_DPA_SHIFT))&DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_ECP_MASK                    0x80u
+#define DMA_DCHPRI13_ECP_SHIFT                   7
+#define DMA_DCHPRI13_ECP_WIDTH                   1
+#define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_ECP_SHIFT))&DMA_DCHPRI13_ECP_MASK)
+/* DCHPRI12 Bit Fields */
+#define DMA_DCHPRI12_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI12_CHPRI_SHIFT                 0
+#define DMA_DCHPRI12_CHPRI_WIDTH                 4
+#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK                    0x40u
+#define DMA_DCHPRI12_DPA_SHIFT                   6
+#define DMA_DCHPRI12_DPA_WIDTH                   1
+#define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_DPA_SHIFT))&DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_ECP_MASK                    0x80u
+#define DMA_DCHPRI12_ECP_SHIFT                   7
+#define DMA_DCHPRI12_ECP_WIDTH                   1
+#define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_ECP_SHIFT))&DMA_DCHPRI12_ECP_MASK)
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK                     0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT                    0
+#define DMA_SADDR_SADDR_WIDTH                    32
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK                       0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT                      0
+#define DMA_SOFF_SOFF_WIDTH                      16
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK                      0x7u
+#define DMA_ATTR_DSIZE_SHIFT                     0
+#define DMA_ATTR_DSIZE_WIDTH                     3
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       0xF8u
+#define DMA_ATTR_DMOD_SHIFT                      3
+#define DMA_ATTR_DMOD_WIDTH                      5
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      0x700u
+#define DMA_ATTR_SSIZE_SHIFT                     8
+#define DMA_ATTR_SSIZE_WIDTH                     3
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       0xF800u
+#define DMA_ATTR_SMOD_SHIFT                      11
+#define DMA_ATTR_SMOD_WIDTH                      5
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             0
+#define DMA_NBYTES_MLNO_NBYTES_WIDTH             32
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          0
+#define DMA_NBYTES_MLOFFNO_NBYTES_WIDTH          30
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           30
+#define DMA_NBYTES_MLOFFNO_DMLOE_WIDTH           1
+#define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           31
+#define DMA_NBYTES_MLOFFNO_SMLOE_WIDTH           1
+#define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         0
+#define DMA_NBYTES_MLOFFYES_NBYTES_WIDTH         10
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          10
+#define DMA_NBYTES_MLOFFYES_MLOFF_WIDTH          20
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          30
+#define DMA_NBYTES_MLOFFYES_DMLOE_WIDTH          1
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          31
+#define DMA_NBYTES_MLOFFYES_SMLOE_WIDTH          1
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK                     0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT                    0
+#define DMA_SLAST_SLAST_WIDTH                    32
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK                     0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT                    0
+#define DMA_DADDR_DADDR_WIDTH                    32
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK                       0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT                      0
+#define DMA_DOFF_DOFF_WIDTH                      16
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK             0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT            0
+#define DMA_CITER_ELINKNO_CITER_WIDTH            15
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            15
+#define DMA_CITER_ELINKNO_ELINK_WIDTH            1
+#define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_ELINK_SHIFT))&DMA_CITER_ELINKNO_ELINK_MASK)
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK            0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT           0
+#define DMA_CITER_ELINKYES_CITER_WIDTH           9
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_CITER_ELINKYES_LINKCH_WIDTH          4
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           15
+#define DMA_CITER_ELINKYES_ELINK_WIDTH           1
+#define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_ELINK_SHIFT))&DMA_CITER_ELINKYES_ELINK_MASK)
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             0
+#define DMA_DLAST_SGA_DLASTSGA_WIDTH             32
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK                       0x1u
+#define DMA_CSR_START_SHIFT                      0
+#define DMA_CSR_START_WIDTH                      1
+#define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_CSR_START_SHIFT))&DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK                    0x2u
+#define DMA_CSR_INTMAJOR_SHIFT                   1
+#define DMA_CSR_INTMAJOR_WIDTH                   1
+#define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTMAJOR_SHIFT))&DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK                     0x4u
+#define DMA_CSR_INTHALF_SHIFT                    2
+#define DMA_CSR_INTHALF_WIDTH                    1
+#define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTHALF_SHIFT))&DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK                        0x8u
+#define DMA_CSR_DREQ_SHIFT                       3
+#define DMA_CSR_DREQ_WIDTH                       1
+#define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DREQ_SHIFT))&DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK                         0x10u
+#define DMA_CSR_ESG_SHIFT                        4
+#define DMA_CSR_ESG_WIDTH                        1
+#define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ESG_SHIFT))&DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK                  0x20u
+#define DMA_CSR_MAJORELINK_SHIFT                 5
+#define DMA_CSR_MAJORELINK_WIDTH                 1
+#define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORELINK_SHIFT))&DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK                      0x40u
+#define DMA_CSR_ACTIVE_SHIFT                     6
+#define DMA_CSR_ACTIVE_WIDTH                     1
+#define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ACTIVE_SHIFT))&DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK                        0x80u
+#define DMA_CSR_DONE_SHIFT                       7
+#define DMA_CSR_DONE_WIDTH                       1
+#define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DONE_SHIFT))&DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK                 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT                8
+#define DMA_CSR_MAJORLINKCH_WIDTH                4
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         0xC000u
+#define DMA_CSR_BWC_SHIFT                        14
+#define DMA_CSR_BWC_WIDTH                        2
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK             0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT            0
+#define DMA_BITER_ELINKNO_BITER_WIDTH            15
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            15
+#define DMA_BITER_ELINKNO_ELINK_WIDTH            1
+#define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_ELINK_SHIFT))&DMA_BITER_ELINKNO_ELINK_MASK)
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK            0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT           0
+#define DMA_BITER_ELINKYES_BITER_WIDTH           9
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_BITER_ELINKYES_LINKCH_WIDTH          4
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           15
+#define DMA_BITER_ELINKYES_ELINK_WIDTH           1
+#define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_ELINK_SHIFT))&DMA_BITER_ELINKYES_ELINK_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR                             (DMA0)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_CR                                   DMA_CR_REG(DMA0)
+#define DMA_ES                                   DMA_ES_REG(DMA0)
+#define DMA_ERQ                                  DMA_ERQ_REG(DMA0)
+#define DMA_EEI                                  DMA_EEI_REG(DMA0)
+#define DMA_CEEI                                 DMA_CEEI_REG(DMA0)
+#define DMA_SEEI                                 DMA_SEEI_REG(DMA0)
+#define DMA_CERQ                                 DMA_CERQ_REG(DMA0)
+#define DMA_SERQ                                 DMA_SERQ_REG(DMA0)
+#define DMA_CDNE                                 DMA_CDNE_REG(DMA0)
+#define DMA_SSRT                                 DMA_SSRT_REG(DMA0)
+#define DMA_CERR                                 DMA_CERR_REG(DMA0)
+#define DMA_CINT                                 DMA_CINT_REG(DMA0)
+#define DMA_INT                                  DMA_INT_REG(DMA0)
+#define DMA_ERR                                  DMA_ERR_REG(DMA0)
+#define DMA_HRS                                  DMA_HRS_REG(DMA0)
+#define DMA_DCHPRI3                              DMA_DCHPRI3_REG(DMA0)
+#define DMA_DCHPRI2                              DMA_DCHPRI2_REG(DMA0)
+#define DMA_DCHPRI1                              DMA_DCHPRI1_REG(DMA0)
+#define DMA_DCHPRI0                              DMA_DCHPRI0_REG(DMA0)
+#define DMA_DCHPRI7                              DMA_DCHPRI7_REG(DMA0)
+#define DMA_DCHPRI6                              DMA_DCHPRI6_REG(DMA0)
+#define DMA_DCHPRI5                              DMA_DCHPRI5_REG(DMA0)
+#define DMA_DCHPRI4                              DMA_DCHPRI4_REG(DMA0)
+#define DMA_DCHPRI11                             DMA_DCHPRI11_REG(DMA0)
+#define DMA_DCHPRI10                             DMA_DCHPRI10_REG(DMA0)
+#define DMA_DCHPRI9                              DMA_DCHPRI9_REG(DMA0)
+#define DMA_DCHPRI8                              DMA_DCHPRI8_REG(DMA0)
+#define DMA_DCHPRI15                             DMA_DCHPRI15_REG(DMA0)
+#define DMA_DCHPRI14                             DMA_DCHPRI14_REG(DMA0)
+#define DMA_DCHPRI13                             DMA_DCHPRI13_REG(DMA0)
+#define DMA_DCHPRI12                             DMA_DCHPRI12_REG(DMA0)
+#define DMA_TCD0_SADDR                           DMA_SADDR_REG(DMA0,0)
+#define DMA_TCD0_SOFF                            DMA_SOFF_REG(DMA0,0)
+#define DMA_TCD0_ATTR                            DMA_ATTR_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,0)
+#define DMA_TCD0_SLAST                           DMA_SLAST_REG(DMA0,0)
+#define DMA_TCD0_DADDR                           DMA_DADDR_REG(DMA0,0)
+#define DMA_TCD0_DOFF                            DMA_DOFF_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD0_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,0)
+#define DMA_TCD0_CSR                             DMA_CSR_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD1_SADDR                           DMA_SADDR_REG(DMA0,1)
+#define DMA_TCD1_SOFF                            DMA_SOFF_REG(DMA0,1)
+#define DMA_TCD1_ATTR                            DMA_ATTR_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,1)
+#define DMA_TCD1_SLAST                           DMA_SLAST_REG(DMA0,1)
+#define DMA_TCD1_DADDR                           DMA_DADDR_REG(DMA0,1)
+#define DMA_TCD1_DOFF                            DMA_DOFF_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD1_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,1)
+#define DMA_TCD1_CSR                             DMA_CSR_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD2_SADDR                           DMA_SADDR_REG(DMA0,2)
+#define DMA_TCD2_SOFF                            DMA_SOFF_REG(DMA0,2)
+#define DMA_TCD2_ATTR                            DMA_ATTR_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,2)
+#define DMA_TCD2_SLAST                           DMA_SLAST_REG(DMA0,2)
+#define DMA_TCD2_DADDR                           DMA_DADDR_REG(DMA0,2)
+#define DMA_TCD2_DOFF                            DMA_DOFF_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD2_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,2)
+#define DMA_TCD2_CSR                             DMA_CSR_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD3_SADDR                           DMA_SADDR_REG(DMA0,3)
+#define DMA_TCD3_SOFF                            DMA_SOFF_REG(DMA0,3)
+#define DMA_TCD3_ATTR                            DMA_ATTR_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,3)
+#define DMA_TCD3_SLAST                           DMA_SLAST_REG(DMA0,3)
+#define DMA_TCD3_DADDR                           DMA_DADDR_REG(DMA0,3)
+#define DMA_TCD3_DOFF                            DMA_DOFF_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD3_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,3)
+#define DMA_TCD3_CSR                             DMA_CSR_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD4_SADDR                           DMA_SADDR_REG(DMA0,4)
+#define DMA_TCD4_SOFF                            DMA_SOFF_REG(DMA0,4)
+#define DMA_TCD4_ATTR                            DMA_ATTR_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,4)
+#define DMA_TCD4_SLAST                           DMA_SLAST_REG(DMA0,4)
+#define DMA_TCD4_DADDR                           DMA_DADDR_REG(DMA0,4)
+#define DMA_TCD4_DOFF                            DMA_DOFF_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD4_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,4)
+#define DMA_TCD4_CSR                             DMA_CSR_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD5_SADDR                           DMA_SADDR_REG(DMA0,5)
+#define DMA_TCD5_SOFF                            DMA_SOFF_REG(DMA0,5)
+#define DMA_TCD5_ATTR                            DMA_ATTR_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,5)
+#define DMA_TCD5_SLAST                           DMA_SLAST_REG(DMA0,5)
+#define DMA_TCD5_DADDR                           DMA_DADDR_REG(DMA0,5)
+#define DMA_TCD5_DOFF                            DMA_DOFF_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD5_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,5)
+#define DMA_TCD5_CSR                             DMA_CSR_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD6_SADDR                           DMA_SADDR_REG(DMA0,6)
+#define DMA_TCD6_SOFF                            DMA_SOFF_REG(DMA0,6)
+#define DMA_TCD6_ATTR                            DMA_ATTR_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,6)
+#define DMA_TCD6_SLAST                           DMA_SLAST_REG(DMA0,6)
+#define DMA_TCD6_DADDR                           DMA_DADDR_REG(DMA0,6)
+#define DMA_TCD6_DOFF                            DMA_DOFF_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD6_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,6)
+#define DMA_TCD6_CSR                             DMA_CSR_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD7_SADDR                           DMA_SADDR_REG(DMA0,7)
+#define DMA_TCD7_SOFF                            DMA_SOFF_REG(DMA0,7)
+#define DMA_TCD7_ATTR                            DMA_ATTR_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,7)
+#define DMA_TCD7_SLAST                           DMA_SLAST_REG(DMA0,7)
+#define DMA_TCD7_DADDR                           DMA_DADDR_REG(DMA0,7)
+#define DMA_TCD7_DOFF                            DMA_DOFF_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD7_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,7)
+#define DMA_TCD7_CSR                             DMA_CSR_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD8_SADDR                           DMA_SADDR_REG(DMA0,8)
+#define DMA_TCD8_SOFF                            DMA_SOFF_REG(DMA0,8)
+#define DMA_TCD8_ATTR                            DMA_ATTR_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,8)
+#define DMA_TCD8_SLAST                           DMA_SLAST_REG(DMA0,8)
+#define DMA_TCD8_DADDR                           DMA_DADDR_REG(DMA0,8)
+#define DMA_TCD8_DOFF                            DMA_DOFF_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD8_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,8)
+#define DMA_TCD8_CSR                             DMA_CSR_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD9_SADDR                           DMA_SADDR_REG(DMA0,9)
+#define DMA_TCD9_SOFF                            DMA_SOFF_REG(DMA0,9)
+#define DMA_TCD9_ATTR                            DMA_ATTR_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,9)
+#define DMA_TCD9_SLAST                           DMA_SLAST_REG(DMA0,9)
+#define DMA_TCD9_DADDR                           DMA_DADDR_REG(DMA0,9)
+#define DMA_TCD9_DOFF                            DMA_DOFF_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD9_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,9)
+#define DMA_TCD9_CSR                             DMA_CSR_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD10_SADDR                          DMA_SADDR_REG(DMA0,10)
+#define DMA_TCD10_SOFF                           DMA_SOFF_REG(DMA0,10)
+#define DMA_TCD10_ATTR                           DMA_ATTR_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,10)
+#define DMA_TCD10_SLAST                          DMA_SLAST_REG(DMA0,10)
+#define DMA_TCD10_DADDR                          DMA_DADDR_REG(DMA0,10)
+#define DMA_TCD10_DOFF                           DMA_DOFF_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD10_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,10)
+#define DMA_TCD10_CSR                            DMA_CSR_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD11_SADDR                          DMA_SADDR_REG(DMA0,11)
+#define DMA_TCD11_SOFF                           DMA_SOFF_REG(DMA0,11)
+#define DMA_TCD11_ATTR                           DMA_ATTR_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,11)
+#define DMA_TCD11_SLAST                          DMA_SLAST_REG(DMA0,11)
+#define DMA_TCD11_DADDR                          DMA_DADDR_REG(DMA0,11)
+#define DMA_TCD11_DOFF                           DMA_DOFF_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD11_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,11)
+#define DMA_TCD11_CSR                            DMA_CSR_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD12_SADDR                          DMA_SADDR_REG(DMA0,12)
+#define DMA_TCD12_SOFF                           DMA_SOFF_REG(DMA0,12)
+#define DMA_TCD12_ATTR                           DMA_ATTR_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,12)
+#define DMA_TCD12_SLAST                          DMA_SLAST_REG(DMA0,12)
+#define DMA_TCD12_DADDR                          DMA_DADDR_REG(DMA0,12)
+#define DMA_TCD12_DOFF                           DMA_DOFF_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD12_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,12)
+#define DMA_TCD12_CSR                            DMA_CSR_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD13_SADDR                          DMA_SADDR_REG(DMA0,13)
+#define DMA_TCD13_SOFF                           DMA_SOFF_REG(DMA0,13)
+#define DMA_TCD13_ATTR                           DMA_ATTR_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,13)
+#define DMA_TCD13_SLAST                          DMA_SLAST_REG(DMA0,13)
+#define DMA_TCD13_DADDR                          DMA_DADDR_REG(DMA0,13)
+#define DMA_TCD13_DOFF                           DMA_DOFF_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD13_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,13)
+#define DMA_TCD13_CSR                            DMA_CSR_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD14_SADDR                          DMA_SADDR_REG(DMA0,14)
+#define DMA_TCD14_SOFF                           DMA_SOFF_REG(DMA0,14)
+#define DMA_TCD14_ATTR                           DMA_ATTR_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,14)
+#define DMA_TCD14_SLAST                          DMA_SLAST_REG(DMA0,14)
+#define DMA_TCD14_DADDR                          DMA_DADDR_REG(DMA0,14)
+#define DMA_TCD14_DOFF                           DMA_DOFF_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD14_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,14)
+#define DMA_TCD14_CSR                            DMA_CSR_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD15_SADDR                          DMA_SADDR_REG(DMA0,15)
+#define DMA_TCD15_SOFF                           DMA_SOFF_REG(DMA0,15)
+#define DMA_TCD15_ATTR                           DMA_ATTR_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,15)
+#define DMA_TCD15_SLAST                          DMA_SLAST_REG(DMA0,15)
+#define DMA_TCD15_DADDR                          DMA_DADDR_REG(DMA0,15)
+#define DMA_TCD15_DOFF                           DMA_DOFF_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,15)
+#define DMA_TCD15_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,15)
+#define DMA_TCD15_CSR                            DMA_CSR_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,15)
+
+/* DMA - Register array accessors */
+#define DMA_SADDR(index)                         DMA_SADDR_REG(DMA0,index)
+#define DMA_SOFF(index)                          DMA_SOFF_REG(DMA0,index)
+#define DMA_ATTR(index)                          DMA_ATTR_REG(DMA0,index)
+#define DMA_NBYTES_MLNO(index)                   DMA_NBYTES_MLNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFNO(index)                DMA_NBYTES_MLOFFNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFYES(index)               DMA_NBYTES_MLOFFYES_REG(DMA0,index)
+#define DMA_SLAST(index)                         DMA_SLAST_REG(DMA0,index)
+#define DMA_DADDR(index)                         DMA_DADDR_REG(DMA0,index)
+#define DMA_DOFF(index)                          DMA_DOFF_REG(DMA0,index)
+#define DMA_CITER_ELINKNO(index)                 DMA_CITER_ELINKNO_REG(DMA0,index)
+#define DMA_CITER_ELINKYES(index)                DMA_CITER_ELINKYES_REG(DMA0,index)
+#define DMA_DLAST_SGA(index)                     DMA_DLAST_SGA_REG(DMA0,index)
+#define DMA_CSR(index)                           DMA_CSR_REG(DMA0,index)
+#define DMA_BITER_ELINKNO(index)                 DMA_BITER_ELINKNO_REG(DMA0,index)
+#define DMA_BITER_ELINKYES(index)                DMA_BITER_ELINKYES_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[16];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index)             ((base)->CHCFG[index])
+#define DMAMUX_CHCFG_COUNT                       16
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT                0
+#define DMAMUX_CHCFG_SOURCE_WIDTH                6
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT                  6
+#define DMAMUX_CHCFG_TRIG_WIDTH                  1
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT                  7
+#define DMAMUX_CHCFG_ENBL_WIDTH                  1
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE                              (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
+#define DMAMUX_BASE_PTR                          (DMAMUX)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { DMAMUX }
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX */
+#define DMAMUX_CHCFG0                            DMAMUX_CHCFG_REG(DMAMUX,0)
+#define DMAMUX_CHCFG1                            DMAMUX_CHCFG_REG(DMAMUX,1)
+#define DMAMUX_CHCFG2                            DMAMUX_CHCFG_REG(DMAMUX,2)
+#define DMAMUX_CHCFG3                            DMAMUX_CHCFG_REG(DMAMUX,3)
+#define DMAMUX_CHCFG4                            DMAMUX_CHCFG_REG(DMAMUX,4)
+#define DMAMUX_CHCFG5                            DMAMUX_CHCFG_REG(DMAMUX,5)
+#define DMAMUX_CHCFG6                            DMAMUX_CHCFG_REG(DMAMUX,6)
+#define DMAMUX_CHCFG7                            DMAMUX_CHCFG_REG(DMAMUX,7)
+#define DMAMUX_CHCFG8                            DMAMUX_CHCFG_REG(DMAMUX,8)
+#define DMAMUX_CHCFG9                            DMAMUX_CHCFG_REG(DMAMUX,9)
+#define DMAMUX_CHCFG10                           DMAMUX_CHCFG_REG(DMAMUX,10)
+#define DMAMUX_CHCFG11                           DMAMUX_CHCFG_REG(DMAMUX,11)
+#define DMAMUX_CHCFG12                           DMAMUX_CHCFG_REG(DMAMUX,12)
+#define DMAMUX_CHCFG13                           DMAMUX_CHCFG_REG(DMAMUX,13)
+#define DMAMUX_CHCFG14                           DMAMUX_CHCFG_REG(DMAMUX,14)
+#define DMAMUX_CHCFG15                           DMAMUX_CHCFG_REG(DMAMUX,15)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX_CHCFG(index)                      DMAMUX_CHCFG_REG(DMAMUX,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4];
+  __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
+  __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register, offset: 0x10 */
+  __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register, offset: 0x14 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
+  __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
+       uint8_t RESERVED_4[28];
+  __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
+       uint8_t RESERVED_5[28];
+  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
+  __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
+  __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
+       uint8_t RESERVED_8[40];
+  __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+  __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+  __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
+  __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
+       uint8_t RESERVED_9[28];
+  __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
+       uint8_t RESERVED_10[56];
+  __IO uint32_t RDSR;                              /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+  __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+  __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+  __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+  __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+  __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+  __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+  __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+  __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+  __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+  __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
+       uint8_t RESERVED_12[12];
+  __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+  __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+       uint8_t RESERVED_13[60];
+  __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
+  __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
+  __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
+  __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
+  __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
+  __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
+  __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
+  __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
+  __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
+  __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
+  __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
+  __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
+  __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
+  __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
+  __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
+  __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
+  __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
+       uint8_t RESERVED_14[4];
+  __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
+  __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
+  __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
+  __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
+  __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
+  __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
+  __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
+  __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
+       uint8_t RESERVED_15[4];
+  __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
+  __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
+       uint8_t RESERVED_16[12];
+  __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
+  __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
+  __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
+  __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
+  __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
+  __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
+  __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
+  __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
+       uint8_t RESERVED_17[4];
+  __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
+  __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
+  __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
+  __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
+  __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
+  __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
+  __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
+  __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
+  __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
+  __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
+  __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
+  __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
+  __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
+  __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
+  __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
+       uint8_t RESERVED_18[284];
+  __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
+  __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
+  __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
+  __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
+  __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
+  __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
+  __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+       uint8_t RESERVED_19[488];
+  __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
+  struct {                                         /* offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+  } CHANNEL[4];
+} ENET_Type, *ENET_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register accessors */
+#define ENET_EIR_REG(base)                       ((base)->EIR)
+#define ENET_EIMR_REG(base)                      ((base)->EIMR)
+#define ENET_RDAR_REG(base)                      ((base)->RDAR)
+#define ENET_TDAR_REG(base)                      ((base)->TDAR)
+#define ENET_ECR_REG(base)                       ((base)->ECR)
+#define ENET_MMFR_REG(base)                      ((base)->MMFR)
+#define ENET_MSCR_REG(base)                      ((base)->MSCR)
+#define ENET_MIBC_REG(base)                      ((base)->MIBC)
+#define ENET_RCR_REG(base)                       ((base)->RCR)
+#define ENET_TCR_REG(base)                       ((base)->TCR)
+#define ENET_PALR_REG(base)                      ((base)->PALR)
+#define ENET_PAUR_REG(base)                      ((base)->PAUR)
+#define ENET_OPD_REG(base)                       ((base)->OPD)
+#define ENET_IAUR_REG(base)                      ((base)->IAUR)
+#define ENET_IALR_REG(base)                      ((base)->IALR)
+#define ENET_GAUR_REG(base)                      ((base)->GAUR)
+#define ENET_GALR_REG(base)                      ((base)->GALR)
+#define ENET_TFWR_REG(base)                      ((base)->TFWR)
+#define ENET_RDSR_REG(base)                      ((base)->RDSR)
+#define ENET_TDSR_REG(base)                      ((base)->TDSR)
+#define ENET_MRBR_REG(base)                      ((base)->MRBR)
+#define ENET_RSFL_REG(base)                      ((base)->RSFL)
+#define ENET_RSEM_REG(base)                      ((base)->RSEM)
+#define ENET_RAEM_REG(base)                      ((base)->RAEM)
+#define ENET_RAFL_REG(base)                      ((base)->RAFL)
+#define ENET_TSEM_REG(base)                      ((base)->TSEM)
+#define ENET_TAEM_REG(base)                      ((base)->TAEM)
+#define ENET_TAFL_REG(base)                      ((base)->TAFL)
+#define ENET_TIPG_REG(base)                      ((base)->TIPG)
+#define ENET_FTRL_REG(base)                      ((base)->FTRL)
+#define ENET_TACC_REG(base)                      ((base)->TACC)
+#define ENET_RACC_REG(base)                      ((base)->RACC)
+#define ENET_RMON_T_PACKETS_REG(base)            ((base)->RMON_T_PACKETS)
+#define ENET_RMON_T_BC_PKT_REG(base)             ((base)->RMON_T_BC_PKT)
+#define ENET_RMON_T_MC_PKT_REG(base)             ((base)->RMON_T_MC_PKT)
+#define ENET_RMON_T_CRC_ALIGN_REG(base)          ((base)->RMON_T_CRC_ALIGN)
+#define ENET_RMON_T_UNDERSIZE_REG(base)          ((base)->RMON_T_UNDERSIZE)
+#define ENET_RMON_T_OVERSIZE_REG(base)           ((base)->RMON_T_OVERSIZE)
+#define ENET_RMON_T_FRAG_REG(base)               ((base)->RMON_T_FRAG)
+#define ENET_RMON_T_JAB_REG(base)                ((base)->RMON_T_JAB)
+#define ENET_RMON_T_COL_REG(base)                ((base)->RMON_T_COL)
+#define ENET_RMON_T_P64_REG(base)                ((base)->RMON_T_P64)
+#define ENET_RMON_T_P65TO127_REG(base)           ((base)->RMON_T_P65TO127)
+#define ENET_RMON_T_P128TO255_REG(base)          ((base)->RMON_T_P128TO255)
+#define ENET_RMON_T_P256TO511_REG(base)          ((base)->RMON_T_P256TO511)
+#define ENET_RMON_T_P512TO1023_REG(base)         ((base)->RMON_T_P512TO1023)
+#define ENET_RMON_T_P1024TO2047_REG(base)        ((base)->RMON_T_P1024TO2047)
+#define ENET_RMON_T_P_GTE2048_REG(base)          ((base)->RMON_T_P_GTE2048)
+#define ENET_RMON_T_OCTETS_REG(base)             ((base)->RMON_T_OCTETS)
+#define ENET_IEEE_T_FRAME_OK_REG(base)           ((base)->IEEE_T_FRAME_OK)
+#define ENET_IEEE_T_1COL_REG(base)               ((base)->IEEE_T_1COL)
+#define ENET_IEEE_T_MCOL_REG(base)               ((base)->IEEE_T_MCOL)
+#define ENET_IEEE_T_DEF_REG(base)                ((base)->IEEE_T_DEF)
+#define ENET_IEEE_T_LCOL_REG(base)               ((base)->IEEE_T_LCOL)
+#define ENET_IEEE_T_EXCOL_REG(base)              ((base)->IEEE_T_EXCOL)
+#define ENET_IEEE_T_MACERR_REG(base)             ((base)->IEEE_T_MACERR)
+#define ENET_IEEE_T_CSERR_REG(base)              ((base)->IEEE_T_CSERR)
+#define ENET_IEEE_T_FDXFC_REG(base)              ((base)->IEEE_T_FDXFC)
+#define ENET_IEEE_T_OCTETS_OK_REG(base)          ((base)->IEEE_T_OCTETS_OK)
+#define ENET_RMON_R_PACKETS_REG(base)            ((base)->RMON_R_PACKETS)
+#define ENET_RMON_R_BC_PKT_REG(base)             ((base)->RMON_R_BC_PKT)
+#define ENET_RMON_R_MC_PKT_REG(base)             ((base)->RMON_R_MC_PKT)
+#define ENET_RMON_R_CRC_ALIGN_REG(base)          ((base)->RMON_R_CRC_ALIGN)
+#define ENET_RMON_R_UNDERSIZE_REG(base)          ((base)->RMON_R_UNDERSIZE)
+#define ENET_RMON_R_OVERSIZE_REG(base)           ((base)->RMON_R_OVERSIZE)
+#define ENET_RMON_R_FRAG_REG(base)               ((base)->RMON_R_FRAG)
+#define ENET_RMON_R_JAB_REG(base)                ((base)->RMON_R_JAB)
+#define ENET_RMON_R_P64_REG(base)                ((base)->RMON_R_P64)
+#define ENET_RMON_R_P65TO127_REG(base)           ((base)->RMON_R_P65TO127)
+#define ENET_RMON_R_P128TO255_REG(base)          ((base)->RMON_R_P128TO255)
+#define ENET_RMON_R_P256TO511_REG(base)          ((base)->RMON_R_P256TO511)
+#define ENET_RMON_R_P512TO1023_REG(base)         ((base)->RMON_R_P512TO1023)
+#define ENET_RMON_R_P1024TO2047_REG(base)        ((base)->RMON_R_P1024TO2047)
+#define ENET_RMON_R_P_GTE2048_REG(base)          ((base)->RMON_R_P_GTE2048)
+#define ENET_RMON_R_OCTETS_REG(base)             ((base)->RMON_R_OCTETS)
+#define ENET_IEEE_R_DROP_REG(base)               ((base)->IEEE_R_DROP)
+#define ENET_IEEE_R_FRAME_OK_REG(base)           ((base)->IEEE_R_FRAME_OK)
+#define ENET_IEEE_R_CRC_REG(base)                ((base)->IEEE_R_CRC)
+#define ENET_IEEE_R_ALIGN_REG(base)              ((base)->IEEE_R_ALIGN)
+#define ENET_IEEE_R_MACERR_REG(base)             ((base)->IEEE_R_MACERR)
+#define ENET_IEEE_R_FDXFC_REG(base)              ((base)->IEEE_R_FDXFC)
+#define ENET_IEEE_R_OCTETS_OK_REG(base)          ((base)->IEEE_R_OCTETS_OK)
+#define ENET_ATCR_REG(base)                      ((base)->ATCR)
+#define ENET_ATVR_REG(base)                      ((base)->ATVR)
+#define ENET_ATOFF_REG(base)                     ((base)->ATOFF)
+#define ENET_ATPER_REG(base)                     ((base)->ATPER)
+#define ENET_ATCOR_REG(base)                     ((base)->ATCOR)
+#define ENET_ATINC_REG(base)                     ((base)->ATINC)
+#define ENET_ATSTMP_REG(base)                    ((base)->ATSTMP)
+#define ENET_TGSR_REG(base)                      ((base)->TGSR)
+#define ENET_TCSR_REG(base,index)                ((base)->CHANNEL[index].TCSR)
+#define ENET_TCSR_COUNT                          4
+#define ENET_TCCR_REG(base,index)                ((base)->CHANNEL[index].TCCR)
+#define ENET_TCCR_COUNT                          4
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/* EIR Bit Fields */
+#define ENET_EIR_TS_TIMER_MASK                   0x8000u
+#define ENET_EIR_TS_TIMER_SHIFT                  15
+#define ENET_EIR_TS_TIMER_WIDTH                  1
+#define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_TIMER_SHIFT))&ENET_EIR_TS_TIMER_MASK)
+#define ENET_EIR_TS_AVAIL_MASK                   0x10000u
+#define ENET_EIR_TS_AVAIL_SHIFT                  16
+#define ENET_EIR_TS_AVAIL_WIDTH                  1
+#define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_AVAIL_SHIFT))&ENET_EIR_TS_AVAIL_MASK)
+#define ENET_EIR_WAKEUP_MASK                     0x20000u
+#define ENET_EIR_WAKEUP_SHIFT                    17
+#define ENET_EIR_WAKEUP_WIDTH                    1
+#define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_EIR_WAKEUP_SHIFT))&ENET_EIR_WAKEUP_MASK)
+#define ENET_EIR_PLR_MASK                        0x40000u
+#define ENET_EIR_PLR_SHIFT                       18
+#define ENET_EIR_PLR_WIDTH                       1
+#define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_PLR_SHIFT))&ENET_EIR_PLR_MASK)
+#define ENET_EIR_UN_MASK                         0x80000u
+#define ENET_EIR_UN_SHIFT                        19
+#define ENET_EIR_UN_WIDTH                        1
+#define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_UN_SHIFT))&ENET_EIR_UN_MASK)
+#define ENET_EIR_RL_MASK                         0x100000u
+#define ENET_EIR_RL_SHIFT                        20
+#define ENET_EIR_RL_WIDTH                        1
+#define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RL_SHIFT))&ENET_EIR_RL_MASK)
+#define ENET_EIR_LC_MASK                         0x200000u
+#define ENET_EIR_LC_SHIFT                        21
+#define ENET_EIR_LC_WIDTH                        1
+#define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_LC_SHIFT))&ENET_EIR_LC_MASK)
+#define ENET_EIR_EBERR_MASK                      0x400000u
+#define ENET_EIR_EBERR_SHIFT                     22
+#define ENET_EIR_EBERR_WIDTH                     1
+#define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIR_EBERR_SHIFT))&ENET_EIR_EBERR_MASK)
+#define ENET_EIR_MII_MASK                        0x800000u
+#define ENET_EIR_MII_SHIFT                       23
+#define ENET_EIR_MII_WIDTH                       1
+#define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_MII_SHIFT))&ENET_EIR_MII_MASK)
+#define ENET_EIR_RXB_MASK                        0x1000000u
+#define ENET_EIR_RXB_SHIFT                       24
+#define ENET_EIR_RXB_WIDTH                       1
+#define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXB_SHIFT))&ENET_EIR_RXB_MASK)
+#define ENET_EIR_RXF_MASK                        0x2000000u
+#define ENET_EIR_RXF_SHIFT                       25
+#define ENET_EIR_RXF_WIDTH                       1
+#define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXF_SHIFT))&ENET_EIR_RXF_MASK)
+#define ENET_EIR_TXB_MASK                        0x4000000u
+#define ENET_EIR_TXB_SHIFT                       26
+#define ENET_EIR_TXB_WIDTH                       1
+#define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXB_SHIFT))&ENET_EIR_TXB_MASK)
+#define ENET_EIR_TXF_MASK                        0x8000000u
+#define ENET_EIR_TXF_SHIFT                       27
+#define ENET_EIR_TXF_WIDTH                       1
+#define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXF_SHIFT))&ENET_EIR_TXF_MASK)
+#define ENET_EIR_GRA_MASK                        0x10000000u
+#define ENET_EIR_GRA_SHIFT                       28
+#define ENET_EIR_GRA_WIDTH                       1
+#define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_GRA_SHIFT))&ENET_EIR_GRA_MASK)
+#define ENET_EIR_BABT_MASK                       0x20000000u
+#define ENET_EIR_BABT_SHIFT                      29
+#define ENET_EIR_BABT_WIDTH                      1
+#define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABT_SHIFT))&ENET_EIR_BABT_MASK)
+#define ENET_EIR_BABR_MASK                       0x40000000u
+#define ENET_EIR_BABR_SHIFT                      30
+#define ENET_EIR_BABR_WIDTH                      1
+#define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABR_SHIFT))&ENET_EIR_BABR_MASK)
+/* EIMR Bit Fields */
+#define ENET_EIMR_TS_TIMER_MASK                  0x8000u
+#define ENET_EIMR_TS_TIMER_SHIFT                 15
+#define ENET_EIMR_TS_TIMER_WIDTH                 1
+#define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_TIMER_SHIFT))&ENET_EIMR_TS_TIMER_MASK)
+#define ENET_EIMR_TS_AVAIL_MASK                  0x10000u
+#define ENET_EIMR_TS_AVAIL_SHIFT                 16
+#define ENET_EIMR_TS_AVAIL_WIDTH                 1
+#define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_AVAIL_SHIFT))&ENET_EIMR_TS_AVAIL_MASK)
+#define ENET_EIMR_WAKEUP_MASK                    0x20000u
+#define ENET_EIMR_WAKEUP_SHIFT                   17
+#define ENET_EIMR_WAKEUP_WIDTH                   1
+#define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_WAKEUP_SHIFT))&ENET_EIMR_WAKEUP_MASK)
+#define ENET_EIMR_PLR_MASK                       0x40000u
+#define ENET_EIMR_PLR_SHIFT                      18
+#define ENET_EIMR_PLR_WIDTH                      1
+#define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_PLR_SHIFT))&ENET_EIMR_PLR_MASK)
+#define ENET_EIMR_UN_MASK                        0x80000u
+#define ENET_EIMR_UN_SHIFT                       19
+#define ENET_EIMR_UN_WIDTH                       1
+#define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_UN_SHIFT))&ENET_EIMR_UN_MASK)
+#define ENET_EIMR_RL_MASK                        0x100000u
+#define ENET_EIMR_RL_SHIFT                       20
+#define ENET_EIMR_RL_WIDTH                       1
+#define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RL_SHIFT))&ENET_EIMR_RL_MASK)
+#define ENET_EIMR_LC_MASK                        0x200000u
+#define ENET_EIMR_LC_SHIFT                       21
+#define ENET_EIMR_LC_WIDTH                       1
+#define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_LC_SHIFT))&ENET_EIMR_LC_MASK)
+#define ENET_EIMR_EBERR_MASK                     0x400000u
+#define ENET_EIMR_EBERR_SHIFT                    22
+#define ENET_EIMR_EBERR_WIDTH                    1
+#define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_EBERR_SHIFT))&ENET_EIMR_EBERR_MASK)
+#define ENET_EIMR_MII_MASK                       0x800000u
+#define ENET_EIMR_MII_SHIFT                      23
+#define ENET_EIMR_MII_WIDTH                      1
+#define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_MII_SHIFT))&ENET_EIMR_MII_MASK)
+#define ENET_EIMR_RXB_MASK                       0x1000000u
+#define ENET_EIMR_RXB_SHIFT                      24
+#define ENET_EIMR_RXB_WIDTH                      1
+#define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXB_SHIFT))&ENET_EIMR_RXB_MASK)
+#define ENET_EIMR_RXF_MASK                       0x2000000u
+#define ENET_EIMR_RXF_SHIFT                      25
+#define ENET_EIMR_RXF_WIDTH                      1
+#define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXF_SHIFT))&ENET_EIMR_RXF_MASK)
+#define ENET_EIMR_TXB_MASK                       0x4000000u
+#define ENET_EIMR_TXB_SHIFT                      26
+#define ENET_EIMR_TXB_WIDTH                      1
+#define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXB_SHIFT))&ENET_EIMR_TXB_MASK)
+#define ENET_EIMR_TXF_MASK                       0x8000000u
+#define ENET_EIMR_TXF_SHIFT                      27
+#define ENET_EIMR_TXF_WIDTH                      1
+#define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXF_SHIFT))&ENET_EIMR_TXF_MASK)
+#define ENET_EIMR_GRA_MASK                       0x10000000u
+#define ENET_EIMR_GRA_SHIFT                      28
+#define ENET_EIMR_GRA_WIDTH                      1
+#define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_GRA_SHIFT))&ENET_EIMR_GRA_MASK)
+#define ENET_EIMR_BABT_MASK                      0x20000000u
+#define ENET_EIMR_BABT_SHIFT                     29
+#define ENET_EIMR_BABT_WIDTH                     1
+#define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABT_SHIFT))&ENET_EIMR_BABT_MASK)
+#define ENET_EIMR_BABR_MASK                      0x40000000u
+#define ENET_EIMR_BABR_SHIFT                     30
+#define ENET_EIMR_BABR_WIDTH                     1
+#define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABR_SHIFT))&ENET_EIMR_BABR_MASK)
+/* RDAR Bit Fields */
+#define ENET_RDAR_RDAR_MASK                      0x1000000u
+#define ENET_RDAR_RDAR_SHIFT                     24
+#define ENET_RDAR_RDAR_WIDTH                     1
+#define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RDAR_RDAR_SHIFT))&ENET_RDAR_RDAR_MASK)
+/* TDAR Bit Fields */
+#define ENET_TDAR_TDAR_MASK                      0x1000000u
+#define ENET_TDAR_TDAR_SHIFT                     24
+#define ENET_TDAR_TDAR_WIDTH                     1
+#define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TDAR_TDAR_SHIFT))&ENET_TDAR_TDAR_MASK)
+/* ECR Bit Fields */
+#define ENET_ECR_RESET_MASK                      0x1u
+#define ENET_ECR_RESET_SHIFT                     0
+#define ENET_ECR_RESET_WIDTH                     1
+#define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_RESET_SHIFT))&ENET_ECR_RESET_MASK)
+#define ENET_ECR_ETHEREN_MASK                    0x2u
+#define ENET_ECR_ETHEREN_SHIFT                   1
+#define ENET_ECR_ETHEREN_WIDTH                   1
+#define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ECR_ETHEREN_SHIFT))&ENET_ECR_ETHEREN_MASK)
+#define ENET_ECR_MAGICEN_MASK                    0x4u
+#define ENET_ECR_MAGICEN_SHIFT                   2
+#define ENET_ECR_MAGICEN_WIDTH                   1
+#define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ECR_MAGICEN_SHIFT))&ENET_ECR_MAGICEN_MASK)
+#define ENET_ECR_SLEEP_MASK                      0x8u
+#define ENET_ECR_SLEEP_SHIFT                     3
+#define ENET_ECR_SLEEP_WIDTH                     1
+#define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_SLEEP_SHIFT))&ENET_ECR_SLEEP_MASK)
+#define ENET_ECR_EN1588_MASK                     0x10u
+#define ENET_ECR_EN1588_SHIFT                    4
+#define ENET_ECR_EN1588_WIDTH                    1
+#define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ECR_EN1588_SHIFT))&ENET_ECR_EN1588_MASK)
+#define ENET_ECR_DBGEN_MASK                      0x40u
+#define ENET_ECR_DBGEN_SHIFT                     6
+#define ENET_ECR_DBGEN_WIDTH                     1
+#define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBGEN_SHIFT))&ENET_ECR_DBGEN_MASK)
+#define ENET_ECR_STOPEN_MASK                     0x80u
+#define ENET_ECR_STOPEN_SHIFT                    7
+#define ENET_ECR_STOPEN_WIDTH                    1
+#define ENET_ECR_STOPEN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ECR_STOPEN_SHIFT))&ENET_ECR_STOPEN_MASK)
+#define ENET_ECR_DBSWP_MASK                      0x100u
+#define ENET_ECR_DBSWP_SHIFT                     8
+#define ENET_ECR_DBSWP_WIDTH                     1
+#define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBSWP_SHIFT))&ENET_ECR_DBSWP_MASK)
+/* MMFR Bit Fields */
+#define ENET_MMFR_DATA_MASK                      0xFFFFu
+#define ENET_MMFR_DATA_SHIFT                     0
+#define ENET_MMFR_DATA_WIDTH                     16
+#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK                        0x30000u
+#define ENET_MMFR_TA_SHIFT                       16
+#define ENET_MMFR_TA_WIDTH                       2
+#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK                        0x7C0000u
+#define ENET_MMFR_RA_SHIFT                       18
+#define ENET_MMFR_RA_WIDTH                       5
+#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK                        0xF800000u
+#define ENET_MMFR_PA_SHIFT                       23
+#define ENET_MMFR_PA_WIDTH                       5
+#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK                        0x30000000u
+#define ENET_MMFR_OP_SHIFT                       28
+#define ENET_MMFR_OP_WIDTH                       2
+#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK                        0xC0000000u
+#define ENET_MMFR_ST_SHIFT                       30
+#define ENET_MMFR_ST_WIDTH                       2
+#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
+/* MSCR Bit Fields */
+#define ENET_MSCR_MII_SPEED_MASK                 0x7Eu
+#define ENET_MSCR_MII_SPEED_SHIFT                1
+#define ENET_MSCR_MII_SPEED_WIDTH                6
+#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE_MASK                   0x80u
+#define ENET_MSCR_DIS_PRE_SHIFT                  7
+#define ENET_MSCR_DIS_PRE_WIDTH                  1
+#define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_DIS_PRE_SHIFT))&ENET_MSCR_DIS_PRE_MASK)
+#define ENET_MSCR_HOLDTIME_MASK                  0x700u
+#define ENET_MSCR_HOLDTIME_SHIFT                 8
+#define ENET_MSCR_HOLDTIME_WIDTH                 3
+#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
+/* MIBC Bit Fields */
+#define ENET_MIBC_MIB_CLEAR_MASK                 0x20000000u
+#define ENET_MIBC_MIB_CLEAR_SHIFT                29
+#define ENET_MIBC_MIB_CLEAR_WIDTH                1
+#define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_CLEAR_SHIFT))&ENET_MIBC_MIB_CLEAR_MASK)
+#define ENET_MIBC_MIB_IDLE_MASK                  0x40000000u
+#define ENET_MIBC_MIB_IDLE_SHIFT                 30
+#define ENET_MIBC_MIB_IDLE_WIDTH                 1
+#define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_IDLE_SHIFT))&ENET_MIBC_MIB_IDLE_MASK)
+#define ENET_MIBC_MIB_DIS_MASK                   0x80000000u
+#define ENET_MIBC_MIB_DIS_SHIFT                  31
+#define ENET_MIBC_MIB_DIS_WIDTH                  1
+#define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_DIS_SHIFT))&ENET_MIBC_MIB_DIS_MASK)
+/* RCR Bit Fields */
+#define ENET_RCR_LOOP_MASK                       0x1u
+#define ENET_RCR_LOOP_SHIFT                      0
+#define ENET_RCR_LOOP_WIDTH                      1
+#define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_LOOP_SHIFT))&ENET_RCR_LOOP_MASK)
+#define ENET_RCR_DRT_MASK                        0x2u
+#define ENET_RCR_DRT_SHIFT                       1
+#define ENET_RCR_DRT_WIDTH                       1
+#define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_DRT_SHIFT))&ENET_RCR_DRT_MASK)
+#define ENET_RCR_MII_MODE_MASK                   0x4u
+#define ENET_RCR_MII_MODE_SHIFT                  2
+#define ENET_RCR_MII_MODE_WIDTH                  1
+#define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MII_MODE_SHIFT))&ENET_RCR_MII_MODE_MASK)
+#define ENET_RCR_PROM_MASK                       0x8u
+#define ENET_RCR_PROM_SHIFT                      3
+#define ENET_RCR_PROM_WIDTH                      1
+#define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PROM_SHIFT))&ENET_RCR_PROM_MASK)
+#define ENET_RCR_BC_REJ_MASK                     0x10u
+#define ENET_RCR_BC_REJ_SHIFT                    4
+#define ENET_RCR_BC_REJ_WIDTH                    1
+#define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_BC_REJ_SHIFT))&ENET_RCR_BC_REJ_MASK)
+#define ENET_RCR_FCE_MASK                        0x20u
+#define ENET_RCR_FCE_SHIFT                       5
+#define ENET_RCR_FCE_WIDTH                       1
+#define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_FCE_SHIFT))&ENET_RCR_FCE_MASK)
+#define ENET_RCR_RMII_MODE_MASK                  0x100u
+#define ENET_RCR_RMII_MODE_SHIFT                 8
+#define ENET_RCR_RMII_MODE_WIDTH                 1
+#define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_MODE_SHIFT))&ENET_RCR_RMII_MODE_MASK)
+#define ENET_RCR_RMII_10T_MASK                   0x200u
+#define ENET_RCR_RMII_10T_SHIFT                  9
+#define ENET_RCR_RMII_10T_WIDTH                  1
+#define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_10T_SHIFT))&ENET_RCR_RMII_10T_MASK)
+#define ENET_RCR_PADEN_MASK                      0x1000u
+#define ENET_RCR_PADEN_SHIFT                     12
+#define ENET_RCR_PADEN_WIDTH                     1
+#define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PADEN_SHIFT))&ENET_RCR_PADEN_MASK)
+#define ENET_RCR_PAUFWD_MASK                     0x2000u
+#define ENET_RCR_PAUFWD_SHIFT                    13
+#define ENET_RCR_PAUFWD_WIDTH                    1
+#define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PAUFWD_SHIFT))&ENET_RCR_PAUFWD_MASK)
+#define ENET_RCR_CRCFWD_MASK                     0x4000u
+#define ENET_RCR_CRCFWD_SHIFT                    14
+#define ENET_RCR_CRCFWD_WIDTH                    1
+#define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CRCFWD_SHIFT))&ENET_RCR_CRCFWD_MASK)
+#define ENET_RCR_CFEN_MASK                       0x8000u
+#define ENET_RCR_CFEN_SHIFT                      15
+#define ENET_RCR_CFEN_WIDTH                      1
+#define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CFEN_SHIFT))&ENET_RCR_CFEN_MASK)
+#define ENET_RCR_MAX_FL_MASK                     0x3FFF0000u
+#define ENET_RCR_MAX_FL_SHIFT                    16
+#define ENET_RCR_MAX_FL_WIDTH                    14
+#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC_MASK                        0x40000000u
+#define ENET_RCR_NLC_SHIFT                       30
+#define ENET_RCR_NLC_WIDTH                       1
+#define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_NLC_SHIFT))&ENET_RCR_NLC_MASK)
+#define ENET_RCR_GRS_MASK                        0x80000000u
+#define ENET_RCR_GRS_SHIFT                       31
+#define ENET_RCR_GRS_WIDTH                       1
+#define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_GRS_SHIFT))&ENET_RCR_GRS_MASK)
+/* TCR Bit Fields */
+#define ENET_TCR_GTS_MASK                        0x1u
+#define ENET_TCR_GTS_SHIFT                       0
+#define ENET_TCR_GTS_WIDTH                       1
+#define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_TCR_GTS_SHIFT))&ENET_TCR_GTS_MASK)
+#define ENET_TCR_FDEN_MASK                       0x4u
+#define ENET_TCR_FDEN_SHIFT                      2
+#define ENET_TCR_FDEN_WIDTH                      1
+#define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCR_FDEN_SHIFT))&ENET_TCR_FDEN_MASK)
+#define ENET_TCR_TFC_PAUSE_MASK                  0x8u
+#define ENET_TCR_TFC_PAUSE_SHIFT                 3
+#define ENET_TCR_TFC_PAUSE_WIDTH                 1
+#define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_TCR_TFC_PAUSE_SHIFT))&ENET_TCR_TFC_PAUSE_MASK)
+#define ENET_TCR_RFC_PAUSE_MASK                  0x10u
+#define ENET_TCR_RFC_PAUSE_SHIFT                 4
+#define ENET_TCR_RFC_PAUSE_WIDTH                 1
+#define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_TCR_RFC_PAUSE_SHIFT))&ENET_TCR_RFC_PAUSE_MASK)
+#define ENET_TCR_ADDSEL_MASK                     0xE0u
+#define ENET_TCR_ADDSEL_SHIFT                    5
+#define ENET_TCR_ADDSEL_WIDTH                    3
+#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS_MASK                     0x100u
+#define ENET_TCR_ADDINS_SHIFT                    8
+#define ENET_TCR_ADDINS_WIDTH                    1
+#define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDINS_SHIFT))&ENET_TCR_ADDINS_MASK)
+#define ENET_TCR_CRCFWD_MASK                     0x200u
+#define ENET_TCR_CRCFWD_SHIFT                    9
+#define ENET_TCR_CRCFWD_WIDTH                    1
+#define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_CRCFWD_SHIFT))&ENET_TCR_CRCFWD_MASK)
+/* PALR Bit Fields */
+#define ENET_PALR_PADDR1_MASK                    0xFFFFFFFFu
+#define ENET_PALR_PADDR1_SHIFT                   0
+#define ENET_PALR_PADDR1_WIDTH                   32
+#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
+/* PAUR Bit Fields */
+#define ENET_PAUR_TYPE_MASK                      0xFFFFu
+#define ENET_PAUR_TYPE_SHIFT                     0
+#define ENET_PAUR_TYPE_WIDTH                     16
+#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK                    0xFFFF0000u
+#define ENET_PAUR_PADDR2_SHIFT                   16
+#define ENET_PAUR_PADDR2_WIDTH                   16
+#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
+/* OPD Bit Fields */
+#define ENET_OPD_PAUSE_DUR_MASK                  0xFFFFu
+#define ENET_OPD_PAUSE_DUR_SHIFT                 0
+#define ENET_OPD_PAUSE_DUR_WIDTH                 16
+#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK                     0xFFFF0000u
+#define ENET_OPD_OPCODE_SHIFT                    16
+#define ENET_OPD_OPCODE_WIDTH                    16
+#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
+/* IAUR Bit Fields */
+#define ENET_IAUR_IADDR1_MASK                    0xFFFFFFFFu
+#define ENET_IAUR_IADDR1_SHIFT                   0
+#define ENET_IAUR_IADDR1_WIDTH                   32
+#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
+/* IALR Bit Fields */
+#define ENET_IALR_IADDR2_MASK                    0xFFFFFFFFu
+#define ENET_IALR_IADDR2_SHIFT                   0
+#define ENET_IALR_IADDR2_WIDTH                   32
+#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
+/* GAUR Bit Fields */
+#define ENET_GAUR_GADDR1_MASK                    0xFFFFFFFFu
+#define ENET_GAUR_GADDR1_SHIFT                   0
+#define ENET_GAUR_GADDR1_WIDTH                   32
+#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
+/* GALR Bit Fields */
+#define ENET_GALR_GADDR2_MASK                    0xFFFFFFFFu
+#define ENET_GALR_GADDR2_SHIFT                   0
+#define ENET_GALR_GADDR2_WIDTH                   32
+#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
+/* TFWR Bit Fields */
+#define ENET_TFWR_TFWR_MASK                      0x3Fu
+#define ENET_TFWR_TFWR_SHIFT                     0
+#define ENET_TFWR_TFWR_WIDTH                     6
+#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD_MASK                    0x100u
+#define ENET_TFWR_STRFWD_SHIFT                   8
+#define ENET_TFWR_STRFWD_WIDTH                   1
+#define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_STRFWD_SHIFT))&ENET_TFWR_STRFWD_MASK)
+/* RDSR Bit Fields */
+#define ENET_RDSR_R_DES_START_MASK               0xFFFFFFF8u
+#define ENET_RDSR_R_DES_START_SHIFT              3
+#define ENET_RDSR_R_DES_START_WIDTH              29
+#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
+/* TDSR Bit Fields */
+#define ENET_TDSR_X_DES_START_MASK               0xFFFFFFF8u
+#define ENET_TDSR_X_DES_START_SHIFT              3
+#define ENET_TDSR_X_DES_START_WIDTH              29
+#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
+/* MRBR Bit Fields */
+#define ENET_MRBR_R_BUF_SIZE_MASK                0x3FF0u
+#define ENET_MRBR_R_BUF_SIZE_SHIFT               4
+#define ENET_MRBR_R_BUF_SIZE_WIDTH               10
+#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
+/* RSFL Bit Fields */
+#define ENET_RSFL_RX_SECTION_FULL_MASK           0xFFu
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT          0
+#define ENET_RSFL_RX_SECTION_FULL_WIDTH          8
+#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
+/* RSEM Bit Fields */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         0
+#define ENET_RSEM_RX_SECTION_EMPTY_WIDTH         8
+#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK        0x1F0000u
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       16
+#define ENET_RSEM_STAT_SECTION_EMPTY_WIDTH       5
+#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+/* RAEM Bit Fields */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          0
+#define ENET_RAEM_RX_ALMOST_EMPTY_WIDTH          8
+#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+/* RAFL Bit Fields */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK            0xFFu
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           0
+#define ENET_RAFL_RX_ALMOST_FULL_WIDTH           8
+#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
+/* TSEM Bit Fields */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         0
+#define ENET_TSEM_TX_SECTION_EMPTY_WIDTH         8
+#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
+/* TAEM Bit Fields */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          0
+#define ENET_TAEM_TX_ALMOST_EMPTY_WIDTH          8
+#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+/* TAFL Bit Fields */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK            0xFFu
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           0
+#define ENET_TAFL_TX_ALMOST_FULL_WIDTH           8
+#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
+/* TIPG Bit Fields */
+#define ENET_TIPG_IPG_MASK                       0x1Fu
+#define ENET_TIPG_IPG_SHIFT                      0
+#define ENET_TIPG_IPG_WIDTH                      5
+#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
+/* FTRL Bit Fields */
+#define ENET_FTRL_TRUNC_FL_MASK                  0x3FFFu
+#define ENET_FTRL_TRUNC_FL_SHIFT                 0
+#define ENET_FTRL_TRUNC_FL_WIDTH                 14
+#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
+/* TACC Bit Fields */
+#define ENET_TACC_SHIFT16_MASK                   0x1u
+#define ENET_TACC_SHIFT16_SHIFT                  0
+#define ENET_TACC_SHIFT16_WIDTH                  1
+#define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_TACC_SHIFT16_SHIFT))&ENET_TACC_SHIFT16_MASK)
+#define ENET_TACC_IPCHK_MASK                     0x8u
+#define ENET_TACC_IPCHK_SHIFT                    3
+#define ENET_TACC_IPCHK_WIDTH                    1
+#define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TACC_IPCHK_SHIFT))&ENET_TACC_IPCHK_MASK)
+#define ENET_TACC_PROCHK_MASK                    0x10u
+#define ENET_TACC_PROCHK_SHIFT                   4
+#define ENET_TACC_PROCHK_WIDTH                   1
+#define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_TACC_PROCHK_SHIFT))&ENET_TACC_PROCHK_MASK)
+/* RACC Bit Fields */
+#define ENET_RACC_PADREM_MASK                    0x1u
+#define ENET_RACC_PADREM_SHIFT                   0
+#define ENET_RACC_PADREM_WIDTH                   1
+#define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PADREM_SHIFT))&ENET_RACC_PADREM_MASK)
+#define ENET_RACC_IPDIS_MASK                     0x2u
+#define ENET_RACC_IPDIS_SHIFT                    1
+#define ENET_RACC_IPDIS_WIDTH                    1
+#define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RACC_IPDIS_SHIFT))&ENET_RACC_IPDIS_MASK)
+#define ENET_RACC_PRODIS_MASK                    0x4u
+#define ENET_RACC_PRODIS_SHIFT                   2
+#define ENET_RACC_PRODIS_WIDTH                   1
+#define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PRODIS_SHIFT))&ENET_RACC_PRODIS_MASK)
+#define ENET_RACC_LINEDIS_MASK                   0x40u
+#define ENET_RACC_LINEDIS_SHIFT                  6
+#define ENET_RACC_LINEDIS_WIDTH                  1
+#define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RACC_LINEDIS_SHIFT))&ENET_RACC_LINEDIS_MASK)
+#define ENET_RACC_SHIFT16_MASK                   0x80u
+#define ENET_RACC_SHIFT16_SHIFT                  7
+#define ENET_RACC_SHIFT16_WIDTH                  1
+#define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RACC_SHIFT16_SHIFT))&ENET_RACC_SHIFT16_MASK)
+/* RMON_T_PACKETS Bit Fields */
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK          0xFFFFu
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         0
+#define ENET_RMON_T_PACKETS_TXPKTS_WIDTH         16
+#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
+/* RMON_T_BC_PKT Bit Fields */
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           0xFFFFu
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          0
+#define ENET_RMON_T_BC_PKT_TXPKTS_WIDTH          16
+#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+/* RMON_T_MC_PKT Bit Fields */
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           0xFFFFu
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          0
+#define ENET_RMON_T_MC_PKT_TXPKTS_WIDTH          16
+#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+/* RMON_T_CRC_ALIGN Bit Fields */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       0
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_WIDTH       16
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+/* RMON_T_UNDERSIZE Bit Fields */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       0
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_WIDTH       16
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+/* RMON_T_OVERSIZE Bit Fields */
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         0xFFFFu
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        0
+#define ENET_RMON_T_OVERSIZE_TXPKTS_WIDTH        16
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+/* RMON_T_FRAG Bit Fields */
+#define ENET_RMON_T_FRAG_TXPKTS_MASK             0xFFFFu
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            0
+#define ENET_RMON_T_FRAG_TXPKTS_WIDTH            16
+#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
+/* RMON_T_JAB Bit Fields */
+#define ENET_RMON_T_JAB_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT             0
+#define ENET_RMON_T_JAB_TXPKTS_WIDTH             16
+#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
+/* RMON_T_COL Bit Fields */
+#define ENET_RMON_T_COL_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_COL_TXPKTS_SHIFT             0
+#define ENET_RMON_T_COL_TXPKTS_WIDTH             16
+#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
+/* RMON_T_P64 Bit Fields */
+#define ENET_RMON_T_P64_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_P64_TXPKTS_SHIFT             0
+#define ENET_RMON_T_P64_TXPKTS_WIDTH             16
+#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
+/* RMON_T_P65TO127 Bit Fields */
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK         0xFFFFu
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        0
+#define ENET_RMON_T_P65TO127_TXPKTS_WIDTH        16
+#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
+/* RMON_T_P128TO255 Bit Fields */
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P128TO255_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
+/* RMON_T_P256TO511 Bit Fields */
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P256TO511_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
+/* RMON_T_P512TO1023 Bit Fields */
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       0xFFFFu
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      0
+#define ENET_RMON_T_P512TO1023_TXPKTS_WIDTH      16
+#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+/* RMON_T_P1024TO2047 Bit Fields */
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      0xFFFFu
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     0
+#define ENET_RMON_T_P1024TO2047_TXPKTS_WIDTH     16
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+/* RMON_T_P_GTE2048 Bit Fields */
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P_GTE2048_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+/* RMON_T_OCTETS Bit Fields */
+#define ENET_RMON_T_OCTETS_TXOCTS_MASK           0xFFFFFFFFu
+#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          0
+#define ENET_RMON_T_OCTETS_TXOCTS_WIDTH          32
+#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
+/* IEEE_T_FRAME_OK Bit Fields */
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          0xFFFFu
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         0
+#define ENET_IEEE_T_FRAME_OK_COUNT_WIDTH         16
+#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+/* IEEE_T_1COL Bit Fields */
+#define ENET_IEEE_T_1COL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_1COL_COUNT_SHIFT             0
+#define ENET_IEEE_T_1COL_COUNT_WIDTH             16
+#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
+/* IEEE_T_MCOL Bit Fields */
+#define ENET_IEEE_T_MCOL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT             0
+#define ENET_IEEE_T_MCOL_COUNT_WIDTH             16
+#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
+/* IEEE_T_DEF Bit Fields */
+#define ENET_IEEE_T_DEF_COUNT_MASK               0xFFFFu
+#define ENET_IEEE_T_DEF_COUNT_SHIFT              0
+#define ENET_IEEE_T_DEF_COUNT_WIDTH              16
+#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
+/* IEEE_T_LCOL Bit Fields */
+#define ENET_IEEE_T_LCOL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT             0
+#define ENET_IEEE_T_LCOL_COUNT_WIDTH             16
+#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
+/* IEEE_T_EXCOL Bit Fields */
+#define ENET_IEEE_T_EXCOL_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            0
+#define ENET_IEEE_T_EXCOL_COUNT_WIDTH            16
+#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
+/* IEEE_T_MACERR Bit Fields */
+#define ENET_IEEE_T_MACERR_COUNT_MASK            0xFFFFu
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT           0
+#define ENET_IEEE_T_MACERR_COUNT_WIDTH           16
+#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
+/* IEEE_T_CSERR Bit Fields */
+#define ENET_IEEE_T_CSERR_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT            0
+#define ENET_IEEE_T_CSERR_COUNT_WIDTH            16
+#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
+/* IEEE_T_FDXFC Bit Fields */
+#define ENET_IEEE_T_FDXFC_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            0
+#define ENET_IEEE_T_FDXFC_COUNT_WIDTH            16
+#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
+/* IEEE_T_OCTETS_OK Bit Fields */
+#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        0
+#define ENET_IEEE_T_OCTETS_OK_COUNT_WIDTH        32
+#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+/* RMON_R_PACKETS Bit Fields */
+#define ENET_RMON_R_PACKETS_COUNT_MASK           0xFFFFu
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT          0
+#define ENET_RMON_R_PACKETS_COUNT_WIDTH          16
+#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
+/* RMON_R_BC_PKT Bit Fields */
+#define ENET_RMON_R_BC_PKT_COUNT_MASK            0xFFFFu
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           0
+#define ENET_RMON_R_BC_PKT_COUNT_WIDTH           16
+#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
+/* RMON_R_MC_PKT Bit Fields */
+#define ENET_RMON_R_MC_PKT_COUNT_MASK            0xFFFFu
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           0
+#define ENET_RMON_R_MC_PKT_COUNT_WIDTH           16
+#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
+/* RMON_R_CRC_ALIGN Bit Fields */
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        0
+#define ENET_RMON_R_CRC_ALIGN_COUNT_WIDTH        16
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+/* RMON_R_UNDERSIZE Bit Fields */
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        0
+#define ENET_RMON_R_UNDERSIZE_COUNT_WIDTH        16
+#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+/* RMON_R_OVERSIZE Bit Fields */
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK          0xFFFFu
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         0
+#define ENET_RMON_R_OVERSIZE_COUNT_WIDTH         16
+#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
+/* RMON_R_FRAG Bit Fields */
+#define ENET_RMON_R_FRAG_COUNT_MASK              0xFFFFu
+#define ENET_RMON_R_FRAG_COUNT_SHIFT             0
+#define ENET_RMON_R_FRAG_COUNT_WIDTH             16
+#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
+/* RMON_R_JAB Bit Fields */
+#define ENET_RMON_R_JAB_COUNT_MASK               0xFFFFu
+#define ENET_RMON_R_JAB_COUNT_SHIFT              0
+#define ENET_RMON_R_JAB_COUNT_WIDTH              16
+#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
+/* RMON_R_P64 Bit Fields */
+#define ENET_RMON_R_P64_COUNT_MASK               0xFFFFu
+#define ENET_RMON_R_P64_COUNT_SHIFT              0
+#define ENET_RMON_R_P64_COUNT_WIDTH              16
+#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
+/* RMON_R_P65TO127 Bit Fields */
+#define ENET_RMON_R_P65TO127_COUNT_MASK          0xFFFFu
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT         0
+#define ENET_RMON_R_P65TO127_COUNT_WIDTH         16
+#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
+/* RMON_R_P128TO255 Bit Fields */
+#define ENET_RMON_R_P128TO255_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT        0
+#define ENET_RMON_R_P128TO255_COUNT_WIDTH        16
+#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
+/* RMON_R_P256TO511 Bit Fields */
+#define ENET_RMON_R_P256TO511_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT        0
+#define ENET_RMON_R_P256TO511_COUNT_WIDTH        16
+#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
+/* RMON_R_P512TO1023 Bit Fields */
+#define ENET_RMON_R_P512TO1023_COUNT_MASK        0xFFFFu
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       0
+#define ENET_RMON_R_P512TO1023_COUNT_WIDTH       16
+#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
+/* RMON_R_P1024TO2047 Bit Fields */
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK       0xFFFFu
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      0
+#define ENET_RMON_R_P1024TO2047_COUNT_WIDTH      16
+#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
+/* RMON_R_P_GTE2048 Bit Fields */
+#define ENET_RMON_R_P_GTE2048_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        0
+#define ENET_RMON_R_P_GTE2048_COUNT_WIDTH        16
+#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
+/* RMON_R_OCTETS Bit Fields */
+#define ENET_RMON_R_OCTETS_COUNT_MASK            0xFFFFFFFFu
+#define ENET_RMON_R_OCTETS_COUNT_SHIFT           0
+#define ENET_RMON_R_OCTETS_COUNT_WIDTH           32
+#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
+/* IEEE_R_DROP Bit Fields */
+#define ENET_IEEE_R_DROP_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_R_DROP_COUNT_SHIFT             0
+#define ENET_IEEE_R_DROP_COUNT_WIDTH             16
+#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
+/* IEEE_R_FRAME_OK Bit Fields */
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          0xFFFFu
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         0
+#define ENET_IEEE_R_FRAME_OK_COUNT_WIDTH         16
+#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+/* IEEE_R_CRC Bit Fields */
+#define ENET_IEEE_R_CRC_COUNT_MASK               0xFFFFu
+#define ENET_IEEE_R_CRC_COUNT_SHIFT              0
+#define ENET_IEEE_R_CRC_COUNT_WIDTH              16
+#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
+/* IEEE_R_ALIGN Bit Fields */
+#define ENET_IEEE_R_ALIGN_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            0
+#define ENET_IEEE_R_ALIGN_COUNT_WIDTH            16
+#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
+/* IEEE_R_MACERR Bit Fields */
+#define ENET_IEEE_R_MACERR_COUNT_MASK            0xFFFFu
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT           0
+#define ENET_IEEE_R_MACERR_COUNT_WIDTH           16
+#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
+/* IEEE_R_FDXFC Bit Fields */
+#define ENET_IEEE_R_FDXFC_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            0
+#define ENET_IEEE_R_FDXFC_COUNT_WIDTH            16
+#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
+/* IEEE_R_OCTETS_OK Bit Fields */
+#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        0
+#define ENET_IEEE_R_OCTETS_OK_COUNT_WIDTH        32
+#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+/* ATCR Bit Fields */
+#define ENET_ATCR_EN_MASK                        0x1u
+#define ENET_ATCR_EN_SHIFT                       0
+#define ENET_ATCR_EN_WIDTH                       1
+#define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_EN_SHIFT))&ENET_ATCR_EN_MASK)
+#define ENET_ATCR_OFFEN_MASK                     0x4u
+#define ENET_ATCR_OFFEN_SHIFT                    2
+#define ENET_ATCR_OFFEN_WIDTH                    1
+#define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFEN_SHIFT))&ENET_ATCR_OFFEN_MASK)
+#define ENET_ATCR_OFFRST_MASK                    0x8u
+#define ENET_ATCR_OFFRST_SHIFT                   3
+#define ENET_ATCR_OFFRST_WIDTH                   1
+#define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFRST_SHIFT))&ENET_ATCR_OFFRST_MASK)
+#define ENET_ATCR_PEREN_MASK                     0x10u
+#define ENET_ATCR_PEREN_SHIFT                    4
+#define ENET_ATCR_PEREN_WIDTH                    1
+#define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PEREN_SHIFT))&ENET_ATCR_PEREN_MASK)
+#define ENET_ATCR_PINPER_MASK                    0x80u
+#define ENET_ATCR_PINPER_SHIFT                   7
+#define ENET_ATCR_PINPER_WIDTH                   1
+#define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PINPER_SHIFT))&ENET_ATCR_PINPER_MASK)
+#define ENET_ATCR_RESTART_MASK                   0x200u
+#define ENET_ATCR_RESTART_SHIFT                  9
+#define ENET_ATCR_RESTART_WIDTH                  1
+#define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_RESTART_SHIFT))&ENET_ATCR_RESTART_MASK)
+#define ENET_ATCR_CAPTURE_MASK                   0x800u
+#define ENET_ATCR_CAPTURE_SHIFT                  11
+#define ENET_ATCR_CAPTURE_WIDTH                  1
+#define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_CAPTURE_SHIFT))&ENET_ATCR_CAPTURE_MASK)
+#define ENET_ATCR_SLAVE_MASK                     0x2000u
+#define ENET_ATCR_SLAVE_SHIFT                    13
+#define ENET_ATCR_SLAVE_WIDTH                    1
+#define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_SLAVE_SHIFT))&ENET_ATCR_SLAVE_MASK)
+/* ATVR Bit Fields */
+#define ENET_ATVR_ATIME_MASK                     0xFFFFFFFFu
+#define ENET_ATVR_ATIME_SHIFT                    0
+#define ENET_ATVR_ATIME_WIDTH                    32
+#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
+/* ATOFF Bit Fields */
+#define ENET_ATOFF_OFFSET_MASK                   0xFFFFFFFFu
+#define ENET_ATOFF_OFFSET_SHIFT                  0
+#define ENET_ATOFF_OFFSET_WIDTH                  32
+#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
+/* ATPER Bit Fields */
+#define ENET_ATPER_PERIOD_MASK                   0xFFFFFFFFu
+#define ENET_ATPER_PERIOD_SHIFT                  0
+#define ENET_ATPER_PERIOD_WIDTH                  32
+#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
+/* ATCOR Bit Fields */
+#define ENET_ATCOR_COR_MASK                      0x7FFFFFFFu
+#define ENET_ATCOR_COR_SHIFT                     0
+#define ENET_ATCOR_COR_WIDTH                     31
+#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
+/* ATINC Bit Fields */
+#define ENET_ATINC_INC_MASK                      0x7Fu
+#define ENET_ATINC_INC_SHIFT                     0
+#define ENET_ATINC_INC_WIDTH                     7
+#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK                 0x7F00u
+#define ENET_ATINC_INC_CORR_SHIFT                8
+#define ENET_ATINC_INC_CORR_WIDTH                7
+#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
+/* ATSTMP Bit Fields */
+#define ENET_ATSTMP_TIMESTAMP_MASK               0xFFFFFFFFu
+#define ENET_ATSTMP_TIMESTAMP_SHIFT              0
+#define ENET_ATSTMP_TIMESTAMP_WIDTH              32
+#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
+/* TGSR Bit Fields */
+#define ENET_TGSR_TF0_MASK                       0x1u
+#define ENET_TGSR_TF0_SHIFT                      0
+#define ENET_TGSR_TF0_WIDTH                      1
+#define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF0_SHIFT))&ENET_TGSR_TF0_MASK)
+#define ENET_TGSR_TF1_MASK                       0x2u
+#define ENET_TGSR_TF1_SHIFT                      1
+#define ENET_TGSR_TF1_WIDTH                      1
+#define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF1_SHIFT))&ENET_TGSR_TF1_MASK)
+#define ENET_TGSR_TF2_MASK                       0x4u
+#define ENET_TGSR_TF2_SHIFT                      2
+#define ENET_TGSR_TF2_WIDTH                      1
+#define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF2_SHIFT))&ENET_TGSR_TF2_MASK)
+#define ENET_TGSR_TF3_MASK                       0x8u
+#define ENET_TGSR_TF3_SHIFT                      3
+#define ENET_TGSR_TF3_WIDTH                      1
+#define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF3_SHIFT))&ENET_TGSR_TF3_MASK)
+/* TCSR Bit Fields */
+#define ENET_TCSR_TDRE_MASK                      0x1u
+#define ENET_TCSR_TDRE_SHIFT                     0
+#define ENET_TCSR_TDRE_WIDTH                     1
+#define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TDRE_SHIFT))&ENET_TCSR_TDRE_MASK)
+#define ENET_TCSR_TMODE_MASK                     0x3Cu
+#define ENET_TCSR_TMODE_SHIFT                    2
+#define ENET_TCSR_TMODE_WIDTH                    4
+#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE_MASK                       0x40u
+#define ENET_TCSR_TIE_SHIFT                      6
+#define ENET_TCSR_TIE_WIDTH                      1
+#define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TIE_SHIFT))&ENET_TCSR_TIE_MASK)
+#define ENET_TCSR_TF_MASK                        0x80u
+#define ENET_TCSR_TF_SHIFT                       7
+#define ENET_TCSR_TF_WIDTH                       1
+#define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TF_SHIFT))&ENET_TCSR_TF_MASK)
+/* TCCR Bit Fields */
+#define ENET_TCCR_TCC_MASK                       0xFFFFFFFFu
+#define ENET_TCCR_TCC_SHIFT                      0
+#define ENET_TCCR_TCC_WIDTH                      32
+#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE                                (0x400C0000u)
+/** Peripheral ENET base pointer */
+#define ENET                                     ((ENET_Type *)ENET_BASE)
+#define ENET_BASE_PTR                            (ENET)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS                          { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS                           { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_Transmit_IRQS                       { ENET_Transmit_IRQn }
+#define ENET_Receive_IRQS                        { ENET_Receive_IRQn }
+#define ENET_Error_IRQS                          { ENET_Error_IRQn }
+#define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register instance definitions */
+/* ENET */
+#define ENET_EIR                                 ENET_EIR_REG(ENET)
+#define ENET_EIMR                                ENET_EIMR_REG(ENET)
+#define ENET_RDAR                                ENET_RDAR_REG(ENET)
+#define ENET_TDAR                                ENET_TDAR_REG(ENET)
+#define ENET_ECR                                 ENET_ECR_REG(ENET)
+#define ENET_MMFR                                ENET_MMFR_REG(ENET)
+#define ENET_MSCR                                ENET_MSCR_REG(ENET)
+#define ENET_MIBC                                ENET_MIBC_REG(ENET)
+#define ENET_RCR                                 ENET_RCR_REG(ENET)
+#define ENET_TCR                                 ENET_TCR_REG(ENET)
+#define ENET_PALR                                ENET_PALR_REG(ENET)
+#define ENET_PAUR                                ENET_PAUR_REG(ENET)
+#define ENET_OPD                                 ENET_OPD_REG(ENET)
+#define ENET_IAUR                                ENET_IAUR_REG(ENET)
+#define ENET_IALR                                ENET_IALR_REG(ENET)
+#define ENET_GAUR                                ENET_GAUR_REG(ENET)
+#define ENET_GALR                                ENET_GALR_REG(ENET)
+#define ENET_TFWR                                ENET_TFWR_REG(ENET)
+#define ENET_RDSR                                ENET_RDSR_REG(ENET)
+#define ENET_TDSR                                ENET_TDSR_REG(ENET)
+#define ENET_MRBR                                ENET_MRBR_REG(ENET)
+#define ENET_RSFL                                ENET_RSFL_REG(ENET)
+#define ENET_RSEM                                ENET_RSEM_REG(ENET)
+#define ENET_RAEM                                ENET_RAEM_REG(ENET)
+#define ENET_RAFL                                ENET_RAFL_REG(ENET)
+#define ENET_TSEM                                ENET_TSEM_REG(ENET)
+#define ENET_TAEM                                ENET_TAEM_REG(ENET)
+#define ENET_TAFL                                ENET_TAFL_REG(ENET)
+#define ENET_TIPG                                ENET_TIPG_REG(ENET)
+#define ENET_FTRL                                ENET_FTRL_REG(ENET)
+#define ENET_TACC                                ENET_TACC_REG(ENET)
+#define ENET_RACC                                ENET_RACC_REG(ENET)
+#define ENET_RMON_T_PACKETS                      ENET_RMON_T_PACKETS_REG(ENET)
+#define ENET_RMON_T_BC_PKT                       ENET_RMON_T_BC_PKT_REG(ENET)
+#define ENET_RMON_T_MC_PKT                       ENET_RMON_T_MC_PKT_REG(ENET)
+#define ENET_RMON_T_CRC_ALIGN                    ENET_RMON_T_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_T_UNDERSIZE                    ENET_RMON_T_UNDERSIZE_REG(ENET)
+#define ENET_RMON_T_OVERSIZE                     ENET_RMON_T_OVERSIZE_REG(ENET)
+#define ENET_RMON_T_FRAG                         ENET_RMON_T_FRAG_REG(ENET)
+#define ENET_RMON_T_JAB                          ENET_RMON_T_JAB_REG(ENET)
+#define ENET_RMON_T_COL                          ENET_RMON_T_COL_REG(ENET)
+#define ENET_RMON_T_P64                          ENET_RMON_T_P64_REG(ENET)
+#define ENET_RMON_T_P65TO127                     ENET_RMON_T_P65TO127_REG(ENET)
+#define ENET_RMON_T_P128TO255                    ENET_RMON_T_P128TO255_REG(ENET)
+#define ENET_RMON_T_P256TO511                    ENET_RMON_T_P256TO511_REG(ENET)
+#define ENET_RMON_T_P512TO1023                   ENET_RMON_T_P512TO1023_REG(ENET)
+#define ENET_RMON_T_P1024TO2047                  ENET_RMON_T_P1024TO2047_REG(ENET)
+#define ENET_RMON_T_P_GTE2048                    ENET_RMON_T_P_GTE2048_REG(ENET)
+#define ENET_RMON_T_OCTETS                       ENET_RMON_T_OCTETS_REG(ENET)
+#define ENET_IEEE_T_FRAME_OK                     ENET_IEEE_T_FRAME_OK_REG(ENET)
+#define ENET_IEEE_T_1COL                         ENET_IEEE_T_1COL_REG(ENET)
+#define ENET_IEEE_T_MCOL                         ENET_IEEE_T_MCOL_REG(ENET)
+#define ENET_IEEE_T_DEF                          ENET_IEEE_T_DEF_REG(ENET)
+#define ENET_IEEE_T_LCOL                         ENET_IEEE_T_LCOL_REG(ENET)
+#define ENET_IEEE_T_EXCOL                        ENET_IEEE_T_EXCOL_REG(ENET)
+#define ENET_IEEE_T_MACERR                       ENET_IEEE_T_MACERR_REG(ENET)
+#define ENET_IEEE_T_CSERR                        ENET_IEEE_T_CSERR_REG(ENET)
+#define ENET_IEEE_T_FDXFC                        ENET_IEEE_T_FDXFC_REG(ENET)
+#define ENET_IEEE_T_OCTETS_OK                    ENET_IEEE_T_OCTETS_OK_REG(ENET)
+#define ENET_RMON_R_PACKETS                      ENET_RMON_R_PACKETS_REG(ENET)
+#define ENET_RMON_R_BC_PKT                       ENET_RMON_R_BC_PKT_REG(ENET)
+#define ENET_RMON_R_MC_PKT                       ENET_RMON_R_MC_PKT_REG(ENET)
+#define ENET_RMON_R_CRC_ALIGN                    ENET_RMON_R_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_R_UNDERSIZE                    ENET_RMON_R_UNDERSIZE_REG(ENET)
+#define ENET_RMON_R_OVERSIZE                     ENET_RMON_R_OVERSIZE_REG(ENET)
+#define ENET_RMON_R_FRAG                         ENET_RMON_R_FRAG_REG(ENET)
+#define ENET_RMON_R_JAB                          ENET_RMON_R_JAB_REG(ENET)
+#define ENET_RMON_R_P64                          ENET_RMON_R_P64_REG(ENET)
+#define ENET_RMON_R_P65TO127                     ENET_RMON_R_P65TO127_REG(ENET)
+#define ENET_RMON_R_P128TO255                    ENET_RMON_R_P128TO255_REG(ENET)
+#define ENET_RMON_R_P256TO511                    ENET_RMON_R_P256TO511_REG(ENET)
+#define ENET_RMON_R_P512TO1023                   ENET_RMON_R_P512TO1023_REG(ENET)
+#define ENET_RMON_R_P1024TO2047                  ENET_RMON_R_P1024TO2047_REG(ENET)
+#define ENET_RMON_R_P_GTE2048                    ENET_RMON_R_P_GTE2048_REG(ENET)
+#define ENET_RMON_R_OCTETS                       ENET_RMON_R_OCTETS_REG(ENET)
+#define ENET_IEEE_R_DROP                         ENET_IEEE_R_DROP_REG(ENET)
+#define ENET_IEEE_R_FRAME_OK                     ENET_IEEE_R_FRAME_OK_REG(ENET)
+#define ENET_IEEE_R_CRC                          ENET_IEEE_R_CRC_REG(ENET)
+#define ENET_IEEE_R_ALIGN                        ENET_IEEE_R_ALIGN_REG(ENET)
+#define ENET_IEEE_R_MACERR                       ENET_IEEE_R_MACERR_REG(ENET)
+#define ENET_IEEE_R_FDXFC                        ENET_IEEE_R_FDXFC_REG(ENET)
+#define ENET_IEEE_R_OCTETS_OK                    ENET_IEEE_R_OCTETS_OK_REG(ENET)
+#define ENET_ATCR                                ENET_ATCR_REG(ENET)
+#define ENET_ATVR                                ENET_ATVR_REG(ENET)
+#define ENET_ATOFF                               ENET_ATOFF_REG(ENET)
+#define ENET_ATPER                               ENET_ATPER_REG(ENET)
+#define ENET_ATCOR                               ENET_ATCOR_REG(ENET)
+#define ENET_ATINC                               ENET_ATINC_REG(ENET)
+#define ENET_ATSTMP                              ENET_ATSTMP_REG(ENET)
+#define ENET_TGSR                                ENET_TGSR_REG(ENET)
+#define ENET_TCSR0                               ENET_TCSR_REG(ENET,0)
+#define ENET_TCCR0                               ENET_TCCR_REG(ENET,0)
+#define ENET_TCSR1                               ENET_TCSR_REG(ENET,1)
+#define ENET_TCCR1                               ENET_TCCR_REG(ENET,1)
+#define ENET_TCSR2                               ENET_TCSR_REG(ENET,2)
+#define ENET_TCCR2                               ENET_TCCR_REG(ENET,2)
+#define ENET_TCSR3                               ENET_TCSR_REG(ENET,3)
+#define ENET_TCCR3                               ENET_TCCR_REG(ENET,3)
+
+/* ENET - Register array accessors */
+#define ENET_TCSR(index)                         ENET_TCSR_REG(ENET,index)
+#define ENET_TCCR(index)                         ENET_TCCR_REG(ENET,index)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
+} EWM_Type, *EWM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register accessors */
+#define EWM_CTRL_REG(base)                       ((base)->CTRL)
+#define EWM_SERV_REG(base)                       ((base)->SERV)
+#define EWM_CMPL_REG(base)                       ((base)->CMPL)
+#define EWM_CMPH_REG(base)                       ((base)->CMPH)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK                      0x1u
+#define EWM_CTRL_EWMEN_SHIFT                     0
+#define EWM_CTRL_EWMEN_WIDTH                     1
+#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK                      0x2u
+#define EWM_CTRL_ASSIN_SHIFT                     1
+#define EWM_CTRL_ASSIN_WIDTH                     1
+#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK                       0x4u
+#define EWM_CTRL_INEN_SHIFT                      2
+#define EWM_CTRL_INEN_WIDTH                      1
+#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK                      0x8u
+#define EWM_CTRL_INTEN_SHIFT                     3
+#define EWM_CTRL_INTEN_WIDTH                     1
+#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK                    0xFFu
+#define EWM_SERV_SERVICE_SHIFT                   0
+#define EWM_SERV_SERVICE_WIDTH                   8
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK                   0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT                  0
+#define EWM_CMPL_COMPAREL_WIDTH                  8
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK                   0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT                  0
+#define EWM_CMPH_COMPAREH_WIDTH                  8
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE                                 (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM                                      ((EWM_Type *)EWM_BASE)
+#define EWM_BASE_PTR                             (EWM)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS                           { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS                            { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS                                 { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register instance definitions */
+/* EWM */
+#define EWM_CTRL                                 EWM_CTRL_REG(EWM)
+#define EWM_SERV                                 EWM_SERV_REG(EWM)
+#define EWM_CMPL                                 EWM_CMPL_REG(EWM)
+#define EWM_CMPH                                 EWM_CMPH_REG(EWM)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0xC */
+    __IO uint32_t CSAR;                              /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+    __IO uint32_t CSMR;                              /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+    __IO uint32_t CSCR;                              /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+  } CS[6];
+       uint8_t RESERVED_0[24];
+  __IO uint32_t CSPMCR;                            /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type, *FB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register accessors */
+#define FB_CSAR_REG(base,index)                  ((base)->CS[index].CSAR)
+#define FB_CSAR_COUNT                            6
+#define FB_CSMR_REG(base,index)                  ((base)->CS[index].CSMR)
+#define FB_CSMR_COUNT                            6
+#define FB_CSCR_REG(base,index)                  ((base)->CS[index].CSCR)
+#define FB_CSCR_COUNT                            6
+#define FB_CSPMCR_REG(base)                      ((base)->CSPMCR)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK                          0xFFFF0000u
+#define FB_CSAR_BA_SHIFT                         16
+#define FB_CSAR_BA_WIDTH                         16
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
+/* CSMR Bit Fields */
+#define FB_CSMR_V_MASK                           0x1u
+#define FB_CSMR_V_SHIFT                          0
+#define FB_CSMR_V_WIDTH                          1
+#define FB_CSMR_V(x)                             (((uint32_t)(((uint32_t)(x))<<FB_CSMR_V_SHIFT))&FB_CSMR_V_MASK)
+#define FB_CSMR_WP_MASK                          0x100u
+#define FB_CSMR_WP_SHIFT                         8
+#define FB_CSMR_WP_WIDTH                         1
+#define FB_CSMR_WP(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSMR_WP_SHIFT))&FB_CSMR_WP_MASK)
+#define FB_CSMR_BAM_MASK                         0xFFFF0000u
+#define FB_CSMR_BAM_SHIFT                        16
+#define FB_CSMR_BAM_WIDTH                        16
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
+/* CSCR Bit Fields */
+#define FB_CSCR_BSTW_MASK                        0x8u
+#define FB_CSCR_BSTW_SHIFT                       3
+#define FB_CSCR_BSTW_WIDTH                       1
+#define FB_CSCR_BSTW(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTW_SHIFT))&FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTR_MASK                        0x10u
+#define FB_CSCR_BSTR_SHIFT                       4
+#define FB_CSCR_BSTR_WIDTH                       1
+#define FB_CSCR_BSTR(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTR_SHIFT))&FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BEM_MASK                         0x20u
+#define FB_CSCR_BEM_SHIFT                        5
+#define FB_CSCR_BEM_WIDTH                        1
+#define FB_CSCR_BEM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BEM_SHIFT))&FB_CSCR_BEM_MASK)
+#define FB_CSCR_PS_MASK                          0xC0u
+#define FB_CSCR_PS_SHIFT                         6
+#define FB_CSCR_PS_WIDTH                         2
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK                          0x100u
+#define FB_CSCR_AA_SHIFT                         8
+#define FB_CSCR_AA_WIDTH                         1
+#define FB_CSCR_AA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_AA_SHIFT))&FB_CSCR_AA_MASK)
+#define FB_CSCR_BLS_MASK                         0x200u
+#define FB_CSCR_BLS_SHIFT                        9
+#define FB_CSCR_BLS_WIDTH                        1
+#define FB_CSCR_BLS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BLS_SHIFT))&FB_CSCR_BLS_MASK)
+#define FB_CSCR_WS_MASK                          0xFC00u
+#define FB_CSCR_WS_SHIFT                         10
+#define FB_CSCR_WS_WIDTH                         6
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        0x30000u
+#define FB_CSCR_WRAH_SHIFT                       16
+#define FB_CSCR_WRAH_WIDTH                       2
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        0xC0000u
+#define FB_CSCR_RDAH_SHIFT                       18
+#define FB_CSCR_RDAH_WIDTH                       2
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        0x300000u
+#define FB_CSCR_ASET_SHIFT                       20
+#define FB_CSCR_ASET_WIDTH                       2
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK                        0x400000u
+#define FB_CSCR_EXTS_SHIFT                       22
+#define FB_CSCR_EXTS_WIDTH                       1
+#define FB_CSCR_EXTS(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_EXTS_SHIFT))&FB_CSCR_EXTS_MASK)
+#define FB_CSCR_SWSEN_MASK                       0x800000u
+#define FB_CSCR_SWSEN_SHIFT                      23
+#define FB_CSCR_SWSEN_WIDTH                      1
+#define FB_CSCR_SWSEN(x)                         (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWSEN_SHIFT))&FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWS_MASK                         0xFC000000u
+#define FB_CSCR_SWS_SHIFT                        26
+#define FB_CSCR_SWS_WIDTH                        6
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
+/* CSPMCR Bit Fields */
+#define FB_CSPMCR_GROUP5_MASK                    0xF000u
+#define FB_CSPMCR_GROUP5_SHIFT                   12
+#define FB_CSPMCR_GROUP5_WIDTH                   4
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    0xF0000u
+#define FB_CSPMCR_GROUP4_SHIFT                   16
+#define FB_CSPMCR_GROUP4_WIDTH                   4
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    0xF00000u
+#define FB_CSPMCR_GROUP3_SHIFT                   20
+#define FB_CSPMCR_GROUP3_WIDTH                   4
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    0xF000000u
+#define FB_CSPMCR_GROUP2_SHIFT                   24
+#define FB_CSPMCR_GROUP2_WIDTH                   4
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    0xF0000000u
+#define FB_CSPMCR_GROUP1_SHIFT                   28
+#define FB_CSPMCR_GROUP1_WIDTH                   4
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE                                  (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB                                       ((FB_Type *)FB_BASE)
+#define FB_BASE_PTR                              (FB)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS                            { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS                             { FB }
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register instance definitions */
+/* FB */
+#define FB_CSAR0                                 FB_CSAR_REG(FB,0)
+#define FB_CSMR0                                 FB_CSMR_REG(FB,0)
+#define FB_CSCR0                                 FB_CSCR_REG(FB,0)
+#define FB_CSAR1                                 FB_CSAR_REG(FB,1)
+#define FB_CSMR1                                 FB_CSMR_REG(FB,1)
+#define FB_CSCR1                                 FB_CSCR_REG(FB,1)
+#define FB_CSAR2                                 FB_CSAR_REG(FB,2)
+#define FB_CSMR2                                 FB_CSMR_REG(FB,2)
+#define FB_CSCR2                                 FB_CSCR_REG(FB,2)
+#define FB_CSAR3                                 FB_CSAR_REG(FB,3)
+#define FB_CSMR3                                 FB_CSMR_REG(FB,3)
+#define FB_CSCR3                                 FB_CSCR_REG(FB,3)
+#define FB_CSAR4                                 FB_CSAR_REG(FB,4)
+#define FB_CSMR4                                 FB_CSMR_REG(FB,4)
+#define FB_CSCR4                                 FB_CSCR_REG(FB,4)
+#define FB_CSAR5                                 FB_CSAR_REG(FB,5)
+#define FB_CSMR5                                 FB_CSMR_REG(FB,5)
+#define FB_CSCR5                                 FB_CSCR_REG(FB,5)
+#define FB_CSPMCR                                FB_CSPMCR_REG(FB)
+
+/* FB - Register array accessors */
+#define FB_CSAR(index)                           FB_CSAR_REG(FB,index)
+#define FB_CSMR(index)                           FB_CSMR_REG(FB,index)
+#define FB_CSCR(index)                           FB_CSCR_REG(FB,index)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PFAPR;                             /**< Flash Access Protection Register, offset: 0x0 */
+  __IO uint32_t PFB0CR;                            /**< Flash Bank 0 Control Register, offset: 0x4 */
+  __IO uint32_t PFB1CR;                            /**< Flash Bank 1 Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[244];
+  __IO uint32_t TAGVDW0S[4];                       /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+  __IO uint32_t TAGVDW1S[4];                       /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
+  __IO uint32_t TAGVDW2S[4];                       /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+  __IO uint32_t TAGVDW3S[4];                       /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
+       uint8_t RESERVED_1[192];
+  struct {                                         /* offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_U;                            /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_L;                            /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
+  } SET[4][4];
+} FMC_Type, *FMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register accessors */
+#define FMC_PFAPR_REG(base)                      ((base)->PFAPR)
+#define FMC_PFB0CR_REG(base)                     ((base)->PFB0CR)
+#define FMC_PFB1CR_REG(base)                     ((base)->PFB1CR)
+#define FMC_TAGVDW0S_REG(base,index)             ((base)->TAGVDW0S[index])
+#define FMC_TAGVDW0S_COUNT                       4
+#define FMC_TAGVDW1S_REG(base,index)             ((base)->TAGVDW1S[index])
+#define FMC_TAGVDW1S_COUNT                       4
+#define FMC_TAGVDW2S_REG(base,index)             ((base)->TAGVDW2S[index])
+#define FMC_TAGVDW2S_COUNT                       4
+#define FMC_TAGVDW3S_REG(base,index)             ((base)->TAGVDW3S[index])
+#define FMC_TAGVDW3S_COUNT                       4
+#define FMC_DATA_U_REG(base,index,index2)        ((base)->SET[index][index2].DATA_U)
+#define FMC_DATA_U_COUNT                         4
+#define FMC_DATA_U_COUNT2                        4
+#define FMC_DATA_L_REG(base,index,index2)        ((base)->SET[index][index2].DATA_L)
+#define FMC_DATA_L_COUNT                         4
+#define FMC_DATA_L_COUNT2                        4
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK                      0x3u
+#define FMC_PFAPR_M0AP_SHIFT                     0
+#define FMC_PFAPR_M0AP_WIDTH                     2
+#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK                      0xCu
+#define FMC_PFAPR_M1AP_SHIFT                     2
+#define FMC_PFAPR_M1AP_WIDTH                     2
+#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK                      0x30u
+#define FMC_PFAPR_M2AP_SHIFT                     4
+#define FMC_PFAPR_M2AP_WIDTH                     2
+#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK                      0xC0u
+#define FMC_PFAPR_M3AP_SHIFT                     6
+#define FMC_PFAPR_M3AP_WIDTH                     2
+#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK                      0x300u
+#define FMC_PFAPR_M4AP_SHIFT                     8
+#define FMC_PFAPR_M4AP_WIDTH                     2
+#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK                      0xC00u
+#define FMC_PFAPR_M5AP_SHIFT                     10
+#define FMC_PFAPR_M5AP_WIDTH                     2
+#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK                      0x3000u
+#define FMC_PFAPR_M6AP_SHIFT                     12
+#define FMC_PFAPR_M6AP_WIDTH                     2
+#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK                      0xC000u
+#define FMC_PFAPR_M7AP_SHIFT                     14
+#define FMC_PFAPR_M7AP_WIDTH                     2
+#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK                     0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT                    16
+#define FMC_PFAPR_M0PFD_WIDTH                    1
+#define FMC_PFAPR_M0PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0PFD_SHIFT))&FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK                     0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT                    17
+#define FMC_PFAPR_M1PFD_WIDTH                    1
+#define FMC_PFAPR_M1PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1PFD_SHIFT))&FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK                     0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT                    18
+#define FMC_PFAPR_M2PFD_WIDTH                    1
+#define FMC_PFAPR_M2PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2PFD_SHIFT))&FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK                     0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT                    19
+#define FMC_PFAPR_M3PFD_WIDTH                    1
+#define FMC_PFAPR_M3PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3PFD_SHIFT))&FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M4PFD_MASK                     0x100000u
+#define FMC_PFAPR_M4PFD_SHIFT                    20
+#define FMC_PFAPR_M4PFD_WIDTH                    1
+#define FMC_PFAPR_M4PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4PFD_SHIFT))&FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M5PFD_MASK                     0x200000u
+#define FMC_PFAPR_M5PFD_SHIFT                    21
+#define FMC_PFAPR_M5PFD_WIDTH                    1
+#define FMC_PFAPR_M5PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5PFD_SHIFT))&FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M6PFD_MASK                     0x400000u
+#define FMC_PFAPR_M6PFD_SHIFT                    22
+#define FMC_PFAPR_M6PFD_WIDTH                    1
+#define FMC_PFAPR_M6PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6PFD_SHIFT))&FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M7PFD_MASK                     0x800000u
+#define FMC_PFAPR_M7PFD_SHIFT                    23
+#define FMC_PFAPR_M7PFD_WIDTH                    1
+#define FMC_PFAPR_M7PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7PFD_SHIFT))&FMC_PFAPR_M7PFD_MASK)
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK                   0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT                  0
+#define FMC_PFB0CR_B0SEBE_WIDTH                  1
+#define FMC_PFB0CR_B0SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0SEBE_SHIFT))&FMC_PFB0CR_B0SEBE_MASK)
+#define FMC_PFB0CR_B0IPE_MASK                    0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT                   1
+#define FMC_PFB0CR_B0IPE_WIDTH                   1
+#define FMC_PFB0CR_B0IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0IPE_SHIFT))&FMC_PFB0CR_B0IPE_MASK)
+#define FMC_PFB0CR_B0DPE_MASK                    0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT                   2
+#define FMC_PFB0CR_B0DPE_WIDTH                   1
+#define FMC_PFB0CR_B0DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DPE_SHIFT))&FMC_PFB0CR_B0DPE_MASK)
+#define FMC_PFB0CR_B0ICE_MASK                    0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT                   3
+#define FMC_PFB0CR_B0ICE_WIDTH                   1
+#define FMC_PFB0CR_B0ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0ICE_SHIFT))&FMC_PFB0CR_B0ICE_MASK)
+#define FMC_PFB0CR_B0DCE_MASK                    0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT                   4
+#define FMC_PFB0CR_B0DCE_WIDTH                   1
+#define FMC_PFB0CR_B0DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DCE_SHIFT))&FMC_PFB0CR_B0DCE_MASK)
+#define FMC_PFB0CR_CRC_MASK                      0xE0u
+#define FMC_PFB0CR_CRC_SHIFT                     5
+#define FMC_PFB0CR_CRC_WIDTH                     3
+#define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK                     0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT                    17
+#define FMC_PFB0CR_B0MW_WIDTH                    2
+#define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK                  0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT                 19
+#define FMC_PFB0CR_S_B_INV_WIDTH                 1
+#define FMC_PFB0CR_S_B_INV(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_S_B_INV_SHIFT))&FMC_PFB0CR_S_B_INV_MASK)
+#define FMC_PFB0CR_CINV_WAY_MASK                 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT                20
+#define FMC_PFB0CR_CINV_WAY_WIDTH                4
+#define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK                 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT                24
+#define FMC_PFB0CR_CLCK_WAY_WIDTH                4
+#define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK                   0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT                  28
+#define FMC_PFB0CR_B0RWSC_WIDTH                  4
+#define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* PFB1CR Bit Fields */
+#define FMC_PFB1CR_B1SEBE_MASK                   0x1u
+#define FMC_PFB1CR_B1SEBE_SHIFT                  0
+#define FMC_PFB1CR_B1SEBE_WIDTH                  1
+#define FMC_PFB1CR_B1SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1SEBE_SHIFT))&FMC_PFB1CR_B1SEBE_MASK)
+#define FMC_PFB1CR_B1IPE_MASK                    0x2u
+#define FMC_PFB1CR_B1IPE_SHIFT                   1
+#define FMC_PFB1CR_B1IPE_WIDTH                   1
+#define FMC_PFB1CR_B1IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1IPE_SHIFT))&FMC_PFB1CR_B1IPE_MASK)
+#define FMC_PFB1CR_B1DPE_MASK                    0x4u
+#define FMC_PFB1CR_B1DPE_SHIFT                   2
+#define FMC_PFB1CR_B1DPE_WIDTH                   1
+#define FMC_PFB1CR_B1DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DPE_SHIFT))&FMC_PFB1CR_B1DPE_MASK)
+#define FMC_PFB1CR_B1ICE_MASK                    0x8u
+#define FMC_PFB1CR_B1ICE_SHIFT                   3
+#define FMC_PFB1CR_B1ICE_WIDTH                   1
+#define FMC_PFB1CR_B1ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1ICE_SHIFT))&FMC_PFB1CR_B1ICE_MASK)
+#define FMC_PFB1CR_B1DCE_MASK                    0x10u
+#define FMC_PFB1CR_B1DCE_SHIFT                   4
+#define FMC_PFB1CR_B1DCE_WIDTH                   1
+#define FMC_PFB1CR_B1DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DCE_SHIFT))&FMC_PFB1CR_B1DCE_MASK)
+#define FMC_PFB1CR_B1MW_MASK                     0x60000u
+#define FMC_PFB1CR_B1MW_SHIFT                    17
+#define FMC_PFB1CR_B1MW_WIDTH                    2
+#define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK                   0xF0000000u
+#define FMC_PFB1CR_B1RWSC_SHIFT                  28
+#define FMC_PFB1CR_B1RWSC_WIDTH                  4
+#define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
+/* TAGVDW0S Bit Fields */
+#define FMC_TAGVDW0S_valid_MASK                  0x1u
+#define FMC_TAGVDW0S_valid_SHIFT                 0
+#define FMC_TAGVDW0S_valid_WIDTH                 1
+#define FMC_TAGVDW0S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_valid_SHIFT))&FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW0S_tag_SHIFT                   5
+#define FMC_TAGVDW0S_tag_WIDTH                   14
+#define FMC_TAGVDW0S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
+/* TAGVDW1S Bit Fields */
+#define FMC_TAGVDW1S_valid_MASK                  0x1u
+#define FMC_TAGVDW1S_valid_SHIFT                 0
+#define FMC_TAGVDW1S_valid_WIDTH                 1
+#define FMC_TAGVDW1S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_valid_SHIFT))&FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW1S_tag_SHIFT                   5
+#define FMC_TAGVDW1S_tag_WIDTH                   14
+#define FMC_TAGVDW1S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
+/* TAGVDW2S Bit Fields */
+#define FMC_TAGVDW2S_valid_MASK                  0x1u
+#define FMC_TAGVDW2S_valid_SHIFT                 0
+#define FMC_TAGVDW2S_valid_WIDTH                 1
+#define FMC_TAGVDW2S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_valid_SHIFT))&FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW2S_tag_SHIFT                   5
+#define FMC_TAGVDW2S_tag_WIDTH                   14
+#define FMC_TAGVDW2S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
+/* TAGVDW3S Bit Fields */
+#define FMC_TAGVDW3S_valid_MASK                  0x1u
+#define FMC_TAGVDW3S_valid_SHIFT                 0
+#define FMC_TAGVDW3S_valid_WIDTH                 1
+#define FMC_TAGVDW3S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_valid_SHIFT))&FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW3S_tag_SHIFT                   5
+#define FMC_TAGVDW3S_tag_WIDTH                   14
+#define FMC_TAGVDW3S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
+/* DATA_U Bit Fields */
+#define FMC_DATA_U_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_U_data_SHIFT                    0
+#define FMC_DATA_U_data_WIDTH                    32
+#define FMC_DATA_U_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
+/* DATA_L Bit Fields */
+#define FMC_DATA_L_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_L_data_SHIFT                    0
+#define FMC_DATA_L_data_WIDTH                    32
+#define FMC_DATA_L_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE                                 (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC                                      ((FMC_Type *)FMC_BASE)
+#define FMC_BASE_PTR                             (FMC)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS                           { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS                            { FMC }
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register instance definitions */
+/* FMC */
+#define FMC_PFAPR                                FMC_PFAPR_REG(FMC)
+#define FMC_PFB0CR                               FMC_PFB0CR_REG(FMC)
+#define FMC_PFB1CR                               FMC_PFB1CR_REG(FMC)
+#define FMC_TAGVDW0S0                            FMC_TAGVDW0S_REG(FMC,0)
+#define FMC_TAGVDW0S1                            FMC_TAGVDW0S_REG(FMC,1)
+#define FMC_TAGVDW0S2                            FMC_TAGVDW0S_REG(FMC,2)
+#define FMC_TAGVDW0S3                            FMC_TAGVDW0S_REG(FMC,3)
+#define FMC_TAGVDW1S0                            FMC_TAGVDW1S_REG(FMC,0)
+#define FMC_TAGVDW1S1                            FMC_TAGVDW1S_REG(FMC,1)
+#define FMC_TAGVDW1S2                            FMC_TAGVDW1S_REG(FMC,2)
+#define FMC_TAGVDW1S3                            FMC_TAGVDW1S_REG(FMC,3)
+#define FMC_TAGVDW2S0                            FMC_TAGVDW2S_REG(FMC,0)
+#define FMC_TAGVDW2S1                            FMC_TAGVDW2S_REG(FMC,1)
+#define FMC_TAGVDW2S2                            FMC_TAGVDW2S_REG(FMC,2)
+#define FMC_TAGVDW2S3                            FMC_TAGVDW2S_REG(FMC,3)
+#define FMC_TAGVDW3S0                            FMC_TAGVDW3S_REG(FMC,0)
+#define FMC_TAGVDW3S1                            FMC_TAGVDW3S_REG(FMC,1)
+#define FMC_TAGVDW3S2                            FMC_TAGVDW3S_REG(FMC,2)
+#define FMC_TAGVDW3S3                            FMC_TAGVDW3S_REG(FMC,3)
+#define FMC_DATAW0S0U                            FMC_DATA_U_REG(FMC,0,0)
+#define FMC_DATAW0S0L                            FMC_DATA_L_REG(FMC,0,0)
+#define FMC_DATAW0S1U                            FMC_DATA_U_REG(FMC,0,1)
+#define FMC_DATAW0S1L                            FMC_DATA_L_REG(FMC,0,1)
+#define FMC_DATAW0S2U                            FMC_DATA_U_REG(FMC,0,2)
+#define FMC_DATAW0S2L                            FMC_DATA_L_REG(FMC,0,2)
+#define FMC_DATAW0S3U                            FMC_DATA_U_REG(FMC,0,3)
+#define FMC_DATAW0S3L                            FMC_DATA_L_REG(FMC,0,3)
+#define FMC_DATAW1S0U                            FMC_DATA_U_REG(FMC,1,0)
+#define FMC_DATAW1S0L                            FMC_DATA_L_REG(FMC,1,0)
+#define FMC_DATAW1S1U                            FMC_DATA_U_REG(FMC,1,1)
+#define FMC_DATAW1S1L                            FMC_DATA_L_REG(FMC,1,1)
+#define FMC_DATAW1S2U                            FMC_DATA_U_REG(FMC,1,2)
+#define FMC_DATAW1S2L                            FMC_DATA_L_REG(FMC,1,2)
+#define FMC_DATAW1S3U                            FMC_DATA_U_REG(FMC,1,3)
+#define FMC_DATAW1S3L                            FMC_DATA_L_REG(FMC,1,3)
+#define FMC_DATAW2S0U                            FMC_DATA_U_REG(FMC,2,0)
+#define FMC_DATAW2S0L                            FMC_DATA_L_REG(FMC,2,0)
+#define FMC_DATAW2S1U                            FMC_DATA_U_REG(FMC,2,1)
+#define FMC_DATAW2S1L                            FMC_DATA_L_REG(FMC,2,1)
+#define FMC_DATAW2S2U                            FMC_DATA_U_REG(FMC,2,2)
+#define FMC_DATAW2S2L                            FMC_DATA_L_REG(FMC,2,2)
+#define FMC_DATAW2S3U                            FMC_DATA_U_REG(FMC,2,3)
+#define FMC_DATAW2S3L                            FMC_DATA_L_REG(FMC,2,3)
+#define FMC_DATAW3S0U                            FMC_DATA_U_REG(FMC,3,0)
+#define FMC_DATAW3S0L                            FMC_DATA_L_REG(FMC,3,0)
+#define FMC_DATAW3S1U                            FMC_DATA_U_REG(FMC,3,1)
+#define FMC_DATAW3S1L                            FMC_DATA_L_REG(FMC,3,1)
+#define FMC_DATAW3S2U                            FMC_DATA_U_REG(FMC,3,2)
+#define FMC_DATAW3S2L                            FMC_DATA_L_REG(FMC,3,2)
+#define FMC_DATAW3S3U                            FMC_DATA_U_REG(FMC,3,3)
+#define FMC_DATAW3S3L                            FMC_DATA_L_REG(FMC,3,3)
+
+/* FMC - Register array accessors */
+#define FMC_TAGVDW0S(index)                      FMC_TAGVDW0S_REG(FMC,index)
+#define FMC_TAGVDW1S(index)                      FMC_TAGVDW1S_REG(FMC,index)
+#define FMC_TAGVDW2S(index)                      FMC_TAGVDW2S_REG(FMC,index)
+#define FMC_TAGVDW3S(index)                      FMC_TAGVDW3S_REG(FMC,index)
+#define FMC_DATA_U(index,index2)                 FMC_DATA_U_REG(FMC,index,index2)
+#define FMC_DATA_L(index,index2)                 FMC_DATA_L_REG(FMC,index,index2)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t FEPROT;                             /**< EEPROM Protection Register, offset: 0x16 */
+  __IO uint8_t FDPROT;                             /**< Data Flash Protection Register, offset: 0x17 */
+} FTFE_Type, *FTFE_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register accessors */
+#define FTFE_FSTAT_REG(base)                     ((base)->FSTAT)
+#define FTFE_FCNFG_REG(base)                     ((base)->FCNFG)
+#define FTFE_FSEC_REG(base)                      ((base)->FSEC)
+#define FTFE_FOPT_REG(base)                      ((base)->FOPT)
+#define FTFE_FCCOB3_REG(base)                    ((base)->FCCOB3)
+#define FTFE_FCCOB2_REG(base)                    ((base)->FCCOB2)
+#define FTFE_FCCOB1_REG(base)                    ((base)->FCCOB1)
+#define FTFE_FCCOB0_REG(base)                    ((base)->FCCOB0)
+#define FTFE_FCCOB7_REG(base)                    ((base)->FCCOB7)
+#define FTFE_FCCOB6_REG(base)                    ((base)->FCCOB6)
+#define FTFE_FCCOB5_REG(base)                    ((base)->FCCOB5)
+#define FTFE_FCCOB4_REG(base)                    ((base)->FCCOB4)
+#define FTFE_FCCOBB_REG(base)                    ((base)->FCCOBB)
+#define FTFE_FCCOBA_REG(base)                    ((base)->FCCOBA)
+#define FTFE_FCCOB9_REG(base)                    ((base)->FCCOB9)
+#define FTFE_FCCOB8_REG(base)                    ((base)->FCCOB8)
+#define FTFE_FPROT3_REG(base)                    ((base)->FPROT3)
+#define FTFE_FPROT2_REG(base)                    ((base)->FPROT2)
+#define FTFE_FPROT1_REG(base)                    ((base)->FPROT1)
+#define FTFE_FPROT0_REG(base)                    ((base)->FPROT0)
+#define FTFE_FEPROT_REG(base)                    ((base)->FEPROT)
+#define FTFE_FDPROT_REG(base)                    ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFE_FSTAT_MGSTAT0_MASK                  0x1u
+#define FTFE_FSTAT_MGSTAT0_SHIFT                 0
+#define FTFE_FSTAT_MGSTAT0_WIDTH                 1
+#define FTFE_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_MGSTAT0_SHIFT))&FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_FPVIOL_MASK                   0x10u
+#define FTFE_FSTAT_FPVIOL_SHIFT                  4
+#define FTFE_FSTAT_FPVIOL_WIDTH                  1
+#define FTFE_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_FPVIOL_SHIFT))&FTFE_FSTAT_FPVIOL_MASK)
+#define FTFE_FSTAT_ACCERR_MASK                   0x20u
+#define FTFE_FSTAT_ACCERR_SHIFT                  5
+#define FTFE_FSTAT_ACCERR_WIDTH                  1
+#define FTFE_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_ACCERR_SHIFT))&FTFE_FSTAT_ACCERR_MASK)
+#define FTFE_FSTAT_RDCOLERR_MASK                 0x40u
+#define FTFE_FSTAT_RDCOLERR_SHIFT                6
+#define FTFE_FSTAT_RDCOLERR_WIDTH                1
+#define FTFE_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_RDCOLERR_SHIFT))&FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFE_FSTAT_CCIF_MASK                     0x80u
+#define FTFE_FSTAT_CCIF_SHIFT                    7
+#define FTFE_FSTAT_CCIF_WIDTH                    1
+#define FTFE_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_CCIF_SHIFT))&FTFE_FSTAT_CCIF_MASK)
+/* FCNFG Bit Fields */
+#define FTFE_FCNFG_EEERDY_MASK                   0x1u
+#define FTFE_FCNFG_EEERDY_SHIFT                  0
+#define FTFE_FCNFG_EEERDY_WIDTH                  1
+#define FTFE_FCNFG_EEERDY(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_EEERDY_SHIFT))&FTFE_FCNFG_EEERDY_MASK)
+#define FTFE_FCNFG_RAMRDY_MASK                   0x2u
+#define FTFE_FCNFG_RAMRDY_SHIFT                  1
+#define FTFE_FCNFG_RAMRDY_WIDTH                  1
+#define FTFE_FCNFG_RAMRDY(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RAMRDY_SHIFT))&FTFE_FCNFG_RAMRDY_MASK)
+#define FTFE_FCNFG_PFLSH_MASK                    0x4u
+#define FTFE_FCNFG_PFLSH_SHIFT                   2
+#define FTFE_FCNFG_PFLSH_WIDTH                   1
+#define FTFE_FCNFG_PFLSH(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_PFLSH_SHIFT))&FTFE_FCNFG_PFLSH_MASK)
+#define FTFE_FCNFG_SWAP_MASK                     0x8u
+#define FTFE_FCNFG_SWAP_SHIFT                    3
+#define FTFE_FCNFG_SWAP_WIDTH                    1
+#define FTFE_FCNFG_SWAP(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_SWAP_SHIFT))&FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_ERSSUSP_MASK                  0x10u
+#define FTFE_FCNFG_ERSSUSP_SHIFT                 4
+#define FTFE_FCNFG_ERSSUSP_WIDTH                 1
+#define FTFE_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSSUSP_SHIFT))&FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSAREQ_MASK                  0x20u
+#define FTFE_FCNFG_ERSAREQ_SHIFT                 5
+#define FTFE_FCNFG_ERSAREQ_WIDTH                 1
+#define FTFE_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSAREQ_SHIFT))&FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_RDCOLLIE_MASK                 0x40u
+#define FTFE_FCNFG_RDCOLLIE_SHIFT                6
+#define FTFE_FCNFG_RDCOLLIE_WIDTH                1
+#define FTFE_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RDCOLLIE_SHIFT))&FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_CCIE_MASK                     0x80u
+#define FTFE_FCNFG_CCIE_SHIFT                    7
+#define FTFE_FCNFG_CCIE_WIDTH                    1
+#define FTFE_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_CCIE_SHIFT))&FTFE_FCNFG_CCIE_MASK)
+/* FSEC Bit Fields */
+#define FTFE_FSEC_SEC_MASK                       0x3u
+#define FTFE_FSEC_SEC_SHIFT                      0
+#define FTFE_FSEC_SEC_WIDTH                      2
+#define FTFE_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK                    0xCu
+#define FTFE_FSEC_FSLACC_SHIFT                   2
+#define FTFE_FSEC_FSLACC_WIDTH                   2
+#define FTFE_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK                      0x30u
+#define FTFE_FSEC_MEEN_SHIFT                     4
+#define FTFE_FSEC_MEEN_WIDTH                     2
+#define FTFE_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK                     0xC0u
+#define FTFE_FSEC_KEYEN_SHIFT                    6
+#define FTFE_FSEC_KEYEN_WIDTH                    2
+#define FTFE_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFE_FOPT_OPT_MASK                       0xFFu
+#define FTFE_FOPT_OPT_SHIFT                      0
+#define FTFE_FOPT_OPT_WIDTH                      8
+#define FTFE_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFE_FCCOB3_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB3_CCOBn_SHIFT                  0
+#define FTFE_FCCOB3_CCOBn_WIDTH                  8
+#define FTFE_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFE_FCCOB2_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB2_CCOBn_SHIFT                  0
+#define FTFE_FCCOB2_CCOBn_WIDTH                  8
+#define FTFE_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFE_FCCOB1_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB1_CCOBn_SHIFT                  0
+#define FTFE_FCCOB1_CCOBn_WIDTH                  8
+#define FTFE_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFE_FCCOB0_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB0_CCOBn_SHIFT                  0
+#define FTFE_FCCOB0_CCOBn_WIDTH                  8
+#define FTFE_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFE_FCCOB7_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB7_CCOBn_SHIFT                  0
+#define FTFE_FCCOB7_CCOBn_WIDTH                  8
+#define FTFE_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFE_FCCOB6_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB6_CCOBn_SHIFT                  0
+#define FTFE_FCCOB6_CCOBn_WIDTH                  8
+#define FTFE_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFE_FCCOB5_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB5_CCOBn_SHIFT                  0
+#define FTFE_FCCOB5_CCOBn_WIDTH                  8
+#define FTFE_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFE_FCCOB4_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB4_CCOBn_SHIFT                  0
+#define FTFE_FCCOB4_CCOBn_WIDTH                  8
+#define FTFE_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFE_FCCOBB_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBB_CCOBn_SHIFT                  0
+#define FTFE_FCCOBB_CCOBn_WIDTH                  8
+#define FTFE_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFE_FCCOBA_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBA_CCOBn_SHIFT                  0
+#define FTFE_FCCOBA_CCOBn_WIDTH                  8
+#define FTFE_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFE_FCCOB9_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB9_CCOBn_SHIFT                  0
+#define FTFE_FCCOB9_CCOBn_WIDTH                  8
+#define FTFE_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFE_FCCOB8_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB8_CCOBn_SHIFT                  0
+#define FTFE_FCCOB8_CCOBn_WIDTH                  8
+#define FTFE_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFE_FPROT3_PROT_MASK                    0xFFu
+#define FTFE_FPROT3_PROT_SHIFT                   0
+#define FTFE_FPROT3_PROT_WIDTH                   8
+#define FTFE_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFE_FPROT2_PROT_MASK                    0xFFu
+#define FTFE_FPROT2_PROT_SHIFT                   0
+#define FTFE_FPROT2_PROT_WIDTH                   8
+#define FTFE_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFE_FPROT1_PROT_MASK                    0xFFu
+#define FTFE_FPROT1_PROT_SHIFT                   0
+#define FTFE_FPROT1_PROT_WIDTH                   8
+#define FTFE_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFE_FPROT0_PROT_MASK                    0xFFu
+#define FTFE_FPROT0_PROT_SHIFT                   0
+#define FTFE_FPROT0_PROT_WIDTH                   8
+#define FTFE_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFE_FEPROT_EPROT_MASK                   0xFFu
+#define FTFE_FEPROT_EPROT_SHIFT                  0
+#define FTFE_FEPROT_EPROT_WIDTH                  8
+#define FTFE_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFE_FDPROT_DPROT_MASK                   0xFFu
+#define FTFE_FDPROT_DPROT_SHIFT                  0
+#define FTFE_FDPROT_DPROT_WIDTH                  8
+#define FTFE_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE                                (0x40020000u)
+/** Peripheral FTFE base pointer */
+#define FTFE                                     ((FTFE_Type *)FTFE_BASE)
+#define FTFE_BASE_PTR                            (FTFE)
+/** Array initializer of FTFE peripheral base addresses */
+#define FTFE_BASE_ADDRS                          { FTFE_BASE }
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASE_PTRS                           { FTFE }
+/** Interrupt vectors for the FTFE peripheral type */
+#define FTFE_COMMAND_COMPLETE_IRQS               { FTFE_IRQn }
+#define FTFE_READ_COLLISION_IRQS                 { Read_Collision_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register instance definitions */
+/* FTFE */
+#define FTFE_FSTAT                               FTFE_FSTAT_REG(FTFE)
+#define FTFE_FCNFG                               FTFE_FCNFG_REG(FTFE)
+#define FTFE_FSEC                                FTFE_FSEC_REG(FTFE)
+#define FTFE_FOPT                                FTFE_FOPT_REG(FTFE)
+#define FTFE_FCCOB3                              FTFE_FCCOB3_REG(FTFE)
+#define FTFE_FCCOB2                              FTFE_FCCOB2_REG(FTFE)
+#define FTFE_FCCOB1                              FTFE_FCCOB1_REG(FTFE)
+#define FTFE_FCCOB0                              FTFE_FCCOB0_REG(FTFE)
+#define FTFE_FCCOB7                              FTFE_FCCOB7_REG(FTFE)
+#define FTFE_FCCOB6                              FTFE_FCCOB6_REG(FTFE)
+#define FTFE_FCCOB5                              FTFE_FCCOB5_REG(FTFE)
+#define FTFE_FCCOB4                              FTFE_FCCOB4_REG(FTFE)
+#define FTFE_FCCOBB                              FTFE_FCCOBB_REG(FTFE)
+#define FTFE_FCCOBA                              FTFE_FCCOBA_REG(FTFE)
+#define FTFE_FCCOB9                              FTFE_FCCOB9_REG(FTFE)
+#define FTFE_FCCOB8                              FTFE_FCCOB8_REG(FTFE)
+#define FTFE_FPROT3                              FTFE_FPROT3_REG(FTFE)
+#define FTFE_FPROT2                              FTFE_FPROT2_REG(FTFE)
+#define FTFE_FPROT1                              FTFE_FPROT1_REG(FTFE)
+#define FTFE_FPROT0                              FTFE_FPROT0_REG(FTFE)
+#define FTFE_FEPROT                              FTFE_FEPROT_REG(FTFE)
+#define FTFE_FDPROT                              FTFE_FDPROT_REG(FTFE)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[8];
+  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
+  __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
+  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
+  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
+  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
+  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
+  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
+  __IO uint32_t DEADTIME;                          /**< Deadtime Insertion Control, offset: 0x68 */
+  __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
+  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
+  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
+  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
+  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+  __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
+  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
+  __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
+  __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
+  __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type, *FTM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register accessors */
+#define FTM_SC_REG(base)                         ((base)->SC)
+#define FTM_CNT_REG(base)                        ((base)->CNT)
+#define FTM_MOD_REG(base)                        ((base)->MOD)
+#define FTM_CnSC_REG(base,index)                 ((base)->CONTROLS[index].CnSC)
+#define FTM_CnSC_COUNT                           8
+#define FTM_CnV_REG(base,index)                  ((base)->CONTROLS[index].CnV)
+#define FTM_CnV_COUNT                            8
+#define FTM_CNTIN_REG(base)                      ((base)->CNTIN)
+#define FTM_STATUS_REG(base)                     ((base)->STATUS)
+#define FTM_MODE_REG(base)                       ((base)->MODE)
+#define FTM_SYNC_REG(base)                       ((base)->SYNC)
+#define FTM_OUTINIT_REG(base)                    ((base)->OUTINIT)
+#define FTM_OUTMASK_REG(base)                    ((base)->OUTMASK)
+#define FTM_COMBINE_REG(base)                    ((base)->COMBINE)
+#define FTM_DEADTIME_REG(base)                   ((base)->DEADTIME)
+#define FTM_EXTTRIG_REG(base)                    ((base)->EXTTRIG)
+#define FTM_POL_REG(base)                        ((base)->POL)
+#define FTM_FMS_REG(base)                        ((base)->FMS)
+#define FTM_FILTER_REG(base)                     ((base)->FILTER)
+#define FTM_FLTCTRL_REG(base)                    ((base)->FLTCTRL)
+#define FTM_QDCTRL_REG(base)                     ((base)->QDCTRL)
+#define FTM_CONF_REG(base)                       ((base)->CONF)
+#define FTM_FLTPOL_REG(base)                     ((base)->FLTPOL)
+#define FTM_SYNCONF_REG(base)                    ((base)->SYNCONF)
+#define FTM_INVCTRL_REG(base)                    ((base)->INVCTRL)
+#define FTM_SWOCTRL_REG(base)                    ((base)->SWOCTRL)
+#define FTM_PWMLOAD_REG(base)                    ((base)->PWMLOAD)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK                           0x7u
+#define FTM_SC_PS_SHIFT                          0
+#define FTM_SC_PS_WIDTH                          3
+#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK                         0x18u
+#define FTM_SC_CLKS_SHIFT                        3
+#define FTM_SC_CLKS_WIDTH                        2
+#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK                        0x20u
+#define FTM_SC_CPWMS_SHIFT                       5
+#define FTM_SC_CPWMS_WIDTH                       1
+#define FTM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK                         0x40u
+#define FTM_SC_TOIE_SHIFT                        6
+#define FTM_SC_TOIE_WIDTH                        1
+#define FTM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK                          0x80u
+#define FTM_SC_TOF_SHIFT                         7
+#define FTM_SC_TOF_WIDTH                         1
+#define FTM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK                       0xFFFFu
+#define FTM_CNT_COUNT_SHIFT                      0
+#define FTM_CNT_COUNT_WIDTH                      16
+#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK                         0xFFFFu
+#define FTM_MOD_MOD_SHIFT                        0
+#define FTM_MOD_MOD_WIDTH                        16
+#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK                        0x1u
+#define FTM_CnSC_DMA_SHIFT                       0
+#define FTM_CnSC_DMA_WIDTH                       1
+#define FTM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ELSA_MASK                       0x4u
+#define FTM_CnSC_ELSA_SHIFT                      2
+#define FTM_CnSC_ELSA_WIDTH                      1
+#define FTM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK                       0x8u
+#define FTM_CnSC_ELSB_SHIFT                      3
+#define FTM_CnSC_ELSB_WIDTH                      1
+#define FTM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK                        0x10u
+#define FTM_CnSC_MSA_SHIFT                       4
+#define FTM_CnSC_MSA_WIDTH                       1
+#define FTM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK                        0x20u
+#define FTM_CnSC_MSB_SHIFT                       5
+#define FTM_CnSC_MSB_WIDTH                       1
+#define FTM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK                       0x40u
+#define FTM_CnSC_CHIE_SHIFT                      6
+#define FTM_CnSC_CHIE_WIDTH                      1
+#define FTM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK                        0x80u
+#define FTM_CnSC_CHF_SHIFT                       7
+#define FTM_CnSC_CHF_WIDTH                       1
+#define FTM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK                         0xFFFFu
+#define FTM_CnV_VAL_SHIFT                        0
+#define FTM_CnV_VAL_WIDTH                        16
+#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK                      0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT                     0
+#define FTM_CNTIN_INIT_WIDTH                     16
+#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK                     0x1u
+#define FTM_STATUS_CH0F_SHIFT                    0
+#define FTM_STATUS_CH0F_WIDTH                    1
+#define FTM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK                     0x2u
+#define FTM_STATUS_CH1F_SHIFT                    1
+#define FTM_STATUS_CH1F_WIDTH                    1
+#define FTM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK                     0x4u
+#define FTM_STATUS_CH2F_SHIFT                    2
+#define FTM_STATUS_CH2F_WIDTH                    1
+#define FTM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK                     0x8u
+#define FTM_STATUS_CH3F_SHIFT                    3
+#define FTM_STATUS_CH3F_WIDTH                    1
+#define FTM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK                     0x10u
+#define FTM_STATUS_CH4F_SHIFT                    4
+#define FTM_STATUS_CH4F_WIDTH                    1
+#define FTM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK                     0x20u
+#define FTM_STATUS_CH5F_SHIFT                    5
+#define FTM_STATUS_CH5F_WIDTH                    1
+#define FTM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK                     0x40u
+#define FTM_STATUS_CH6F_SHIFT                    6
+#define FTM_STATUS_CH6F_WIDTH                    1
+#define FTM_STATUS_CH6F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK                     0x80u
+#define FTM_STATUS_CH7F_SHIFT                    7
+#define FTM_STATUS_CH7F_WIDTH                    1
+#define FTM_STATUS_CH7F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK                      0x1u
+#define FTM_MODE_FTMEN_SHIFT                     0
+#define FTM_MODE_FTMEN_WIDTH                     1
+#define FTM_MODE_FTMEN(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK                       0x2u
+#define FTM_MODE_INIT_SHIFT                      1
+#define FTM_MODE_INIT_WIDTH                      1
+#define FTM_MODE_INIT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK                      0x4u
+#define FTM_MODE_WPDIS_SHIFT                     2
+#define FTM_MODE_WPDIS_WIDTH                     1
+#define FTM_MODE_WPDIS(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK                    0x8u
+#define FTM_MODE_PWMSYNC_SHIFT                   3
+#define FTM_MODE_PWMSYNC_WIDTH                   1
+#define FTM_MODE_PWMSYNC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK                    0x10u
+#define FTM_MODE_CAPTEST_SHIFT                   4
+#define FTM_MODE_CAPTEST_WIDTH                   1
+#define FTM_MODE_CAPTEST(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK                     0x60u
+#define FTM_MODE_FAULTM_SHIFT                    5
+#define FTM_MODE_FAULTM_WIDTH                    2
+#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK                    0x80u
+#define FTM_MODE_FAULTIE_SHIFT                   7
+#define FTM_MODE_FAULTIE_WIDTH                   1
+#define FTM_MODE_FAULTIE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK                     0x1u
+#define FTM_SYNC_CNTMIN_SHIFT                    0
+#define FTM_SYNC_CNTMIN_WIDTH                    1
+#define FTM_SYNC_CNTMIN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK                     0x2u
+#define FTM_SYNC_CNTMAX_SHIFT                    1
+#define FTM_SYNC_CNTMAX_WIDTH                    1
+#define FTM_SYNC_CNTMAX(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK                     0x4u
+#define FTM_SYNC_REINIT_SHIFT                    2
+#define FTM_SYNC_REINIT_WIDTH                    1
+#define FTM_SYNC_REINIT(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK                    0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT                   3
+#define FTM_SYNC_SYNCHOM_WIDTH                   1
+#define FTM_SYNC_SYNCHOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK                      0x10u
+#define FTM_SYNC_TRIG0_SHIFT                     4
+#define FTM_SYNC_TRIG0_WIDTH                     1
+#define FTM_SYNC_TRIG0(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK                      0x20u
+#define FTM_SYNC_TRIG1_SHIFT                     5
+#define FTM_SYNC_TRIG1_WIDTH                     1
+#define FTM_SYNC_TRIG1(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK                      0x40u
+#define FTM_SYNC_TRIG2_SHIFT                     6
+#define FTM_SYNC_TRIG2_WIDTH                     1
+#define FTM_SYNC_TRIG2(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK                     0x80u
+#define FTM_SYNC_SWSYNC_SHIFT                    7
+#define FTM_SYNC_SWSYNC_WIDTH                    1
+#define FTM_SYNC_SWSYNC(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK                   0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT                  0
+#define FTM_OUTINIT_CH0OI_WIDTH                  1
+#define FTM_OUTINIT_CH0OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK                   0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT                  1
+#define FTM_OUTINIT_CH1OI_WIDTH                  1
+#define FTM_OUTINIT_CH1OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK                   0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT                  2
+#define FTM_OUTINIT_CH2OI_WIDTH                  1
+#define FTM_OUTINIT_CH2OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK                   0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT                  3
+#define FTM_OUTINIT_CH3OI_WIDTH                  1
+#define FTM_OUTINIT_CH3OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK                   0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT                  4
+#define FTM_OUTINIT_CH4OI_WIDTH                  1
+#define FTM_OUTINIT_CH4OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK                   0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT                  5
+#define FTM_OUTINIT_CH5OI_WIDTH                  1
+#define FTM_OUTINIT_CH5OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK                   0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT                  6
+#define FTM_OUTINIT_CH6OI_WIDTH                  1
+#define FTM_OUTINIT_CH6OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK                   0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT                  7
+#define FTM_OUTINIT_CH7OI_WIDTH                  1
+#define FTM_OUTINIT_CH7OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK                   0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT                  0
+#define FTM_OUTMASK_CH0OM_WIDTH                  1
+#define FTM_OUTMASK_CH0OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK                   0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT                  1
+#define FTM_OUTMASK_CH1OM_WIDTH                  1
+#define FTM_OUTMASK_CH1OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK                   0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT                  2
+#define FTM_OUTMASK_CH2OM_WIDTH                  1
+#define FTM_OUTMASK_CH2OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK                   0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT                  3
+#define FTM_OUTMASK_CH3OM_WIDTH                  1
+#define FTM_OUTMASK_CH3OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK                   0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT                  4
+#define FTM_OUTMASK_CH4OM_WIDTH                  1
+#define FTM_OUTMASK_CH4OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK                   0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT                  5
+#define FTM_OUTMASK_CH5OM_WIDTH                  1
+#define FTM_OUTMASK_CH5OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK                   0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT                  6
+#define FTM_OUTMASK_CH6OM_WIDTH                  1
+#define FTM_OUTMASK_CH6OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK                   0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT                  7
+#define FTM_OUTMASK_CH7OM_WIDTH                  1
+#define FTM_OUTMASK_CH7OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK                0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT               0
+#define FTM_COMBINE_COMBINE0_WIDTH               1
+#define FTM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK                   0x2u
+#define FTM_COMBINE_COMP0_SHIFT                  1
+#define FTM_COMBINE_COMP0_WIDTH                  1
+#define FTM_COMBINE_COMP0(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK                0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT               2
+#define FTM_COMBINE_DECAPEN0_WIDTH               1
+#define FTM_COMBINE_DECAPEN0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK                  0x8u
+#define FTM_COMBINE_DECAP0_SHIFT                 3
+#define FTM_COMBINE_DECAP0_WIDTH                 1
+#define FTM_COMBINE_DECAP0(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK                   0x10u
+#define FTM_COMBINE_DTEN0_SHIFT                  4
+#define FTM_COMBINE_DTEN0_WIDTH                  1
+#define FTM_COMBINE_DTEN0(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK                 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT                5
+#define FTM_COMBINE_SYNCEN0_WIDTH                1
+#define FTM_COMBINE_SYNCEN0(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK                0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT               6
+#define FTM_COMBINE_FAULTEN0_WIDTH               1
+#define FTM_COMBINE_FAULTEN0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK                0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT               8
+#define FTM_COMBINE_COMBINE1_WIDTH               1
+#define FTM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK                   0x200u
+#define FTM_COMBINE_COMP1_SHIFT                  9
+#define FTM_COMBINE_COMP1_WIDTH                  1
+#define FTM_COMBINE_COMP1(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK                0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT               10
+#define FTM_COMBINE_DECAPEN1_WIDTH               1
+#define FTM_COMBINE_DECAPEN1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK                  0x800u
+#define FTM_COMBINE_DECAP1_SHIFT                 11
+#define FTM_COMBINE_DECAP1_WIDTH                 1
+#define FTM_COMBINE_DECAP1(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK                   0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT                  12
+#define FTM_COMBINE_DTEN1_WIDTH                  1
+#define FTM_COMBINE_DTEN1(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK                 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT                13
+#define FTM_COMBINE_SYNCEN1_WIDTH                1
+#define FTM_COMBINE_SYNCEN1(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK                0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT               14
+#define FTM_COMBINE_FAULTEN1_WIDTH               1
+#define FTM_COMBINE_FAULTEN1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK                0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT               16
+#define FTM_COMBINE_COMBINE2_WIDTH               1
+#define FTM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK                   0x20000u
+#define FTM_COMBINE_COMP2_SHIFT                  17
+#define FTM_COMBINE_COMP2_WIDTH                  1
+#define FTM_COMBINE_COMP2(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK                0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT               18
+#define FTM_COMBINE_DECAPEN2_WIDTH               1
+#define FTM_COMBINE_DECAPEN2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK                  0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT                 19
+#define FTM_COMBINE_DECAP2_WIDTH                 1
+#define FTM_COMBINE_DECAP2(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK                   0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT                  20
+#define FTM_COMBINE_DTEN2_WIDTH                  1
+#define FTM_COMBINE_DTEN2(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK                 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT                21
+#define FTM_COMBINE_SYNCEN2_WIDTH                1
+#define FTM_COMBINE_SYNCEN2(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK                0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT               22
+#define FTM_COMBINE_FAULTEN2_WIDTH               1
+#define FTM_COMBINE_FAULTEN2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK                0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT               24
+#define FTM_COMBINE_COMBINE3_WIDTH               1
+#define FTM_COMBINE_COMBINE3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK                   0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT                  25
+#define FTM_COMBINE_COMP3_WIDTH                  1
+#define FTM_COMBINE_COMP3(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK                0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT               26
+#define FTM_COMBINE_DECAPEN3_WIDTH               1
+#define FTM_COMBINE_DECAPEN3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK                  0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT                 27
+#define FTM_COMBINE_DECAP3_WIDTH                 1
+#define FTM_COMBINE_DECAP3(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK                   0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT                  28
+#define FTM_COMBINE_DTEN3_WIDTH                  1
+#define FTM_COMBINE_DTEN3(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK                 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT                29
+#define FTM_COMBINE_SYNCEN3_WIDTH                1
+#define FTM_COMBINE_SYNCEN3(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK                0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT               30
+#define FTM_COMBINE_FAULTEN3_WIDTH               1
+#define FTM_COMBINE_FAULTEN3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK                  0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT                 0
+#define FTM_DEADTIME_DTVAL_WIDTH                 6
+#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK                   0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT                  6
+#define FTM_DEADTIME_DTPS_WIDTH                  2
+#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK                 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT                0
+#define FTM_EXTTRIG_CH2TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH2TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK                 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT                1
+#define FTM_EXTTRIG_CH3TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH3TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK                 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT                2
+#define FTM_EXTTRIG_CH4TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH4TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK                 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT                3
+#define FTM_EXTTRIG_CH5TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH5TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK                 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT                4
+#define FTM_EXTTRIG_CH0TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH0TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK                 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT                5
+#define FTM_EXTTRIG_CH1TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH1TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK              0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT             6
+#define FTM_EXTTRIG_INITTRIGEN_WIDTH             1
+#define FTM_EXTTRIG_INITTRIGEN(x)                (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK                   0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT                  7
+#define FTM_EXTTRIG_TRIGF_WIDTH                  1
+#define FTM_EXTTRIG_TRIGF(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK                        0x1u
+#define FTM_POL_POL0_SHIFT                       0
+#define FTM_POL_POL0_WIDTH                       1
+#define FTM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK                        0x2u
+#define FTM_POL_POL1_SHIFT                       1
+#define FTM_POL_POL1_WIDTH                       1
+#define FTM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK                        0x4u
+#define FTM_POL_POL2_SHIFT                       2
+#define FTM_POL_POL2_WIDTH                       1
+#define FTM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK                        0x8u
+#define FTM_POL_POL3_SHIFT                       3
+#define FTM_POL_POL3_WIDTH                       1
+#define FTM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK                        0x10u
+#define FTM_POL_POL4_SHIFT                       4
+#define FTM_POL_POL4_WIDTH                       1
+#define FTM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK                        0x20u
+#define FTM_POL_POL5_SHIFT                       5
+#define FTM_POL_POL5_WIDTH                       1
+#define FTM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK                        0x40u
+#define FTM_POL_POL6_SHIFT                       6
+#define FTM_POL_POL6_WIDTH                       1
+#define FTM_POL_POL6(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK                        0x80u
+#define FTM_POL_POL7_SHIFT                       7
+#define FTM_POL_POL7_WIDTH                       1
+#define FTM_POL_POL7(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK                     0x1u
+#define FTM_FMS_FAULTF0_SHIFT                    0
+#define FTM_FMS_FAULTF0_WIDTH                    1
+#define FTM_FMS_FAULTF0(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK                     0x2u
+#define FTM_FMS_FAULTF1_SHIFT                    1
+#define FTM_FMS_FAULTF1_WIDTH                    1
+#define FTM_FMS_FAULTF1(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK                     0x4u
+#define FTM_FMS_FAULTF2_SHIFT                    2
+#define FTM_FMS_FAULTF2_WIDTH                    1
+#define FTM_FMS_FAULTF2(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK                     0x8u
+#define FTM_FMS_FAULTF3_SHIFT                    3
+#define FTM_FMS_FAULTF3_WIDTH                    1
+#define FTM_FMS_FAULTF3(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK                     0x20u
+#define FTM_FMS_FAULTIN_SHIFT                    5
+#define FTM_FMS_FAULTIN_WIDTH                    1
+#define FTM_FMS_FAULTIN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK                        0x40u
+#define FTM_FMS_WPEN_SHIFT                       6
+#define FTM_FMS_WPEN_WIDTH                       1
+#define FTM_FMS_WPEN(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK                      0x80u
+#define FTM_FMS_FAULTF_SHIFT                     7
+#define FTM_FMS_FAULTF_WIDTH                     1
+#define FTM_FMS_FAULTF(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK                  0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT                 0
+#define FTM_FILTER_CH0FVAL_WIDTH                 4
+#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK                  0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT                 4
+#define FTM_FILTER_CH1FVAL_WIDTH                 4
+#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK                  0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT                 8
+#define FTM_FILTER_CH2FVAL_WIDTH                 4
+#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK                  0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT                 12
+#define FTM_FILTER_CH3FVAL_WIDTH                 4
+#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK                0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT               0
+#define FTM_FLTCTRL_FAULT0EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT0EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK                0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT               1
+#define FTM_FLTCTRL_FAULT1EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT1EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK                0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT               2
+#define FTM_FLTCTRL_FAULT2EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT2EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK                0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT               3
+#define FTM_FLTCTRL_FAULT3EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT3EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK                0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT               4
+#define FTM_FLTCTRL_FFLTR0EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR0EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK                0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT               5
+#define FTM_FLTCTRL_FFLTR1EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR1EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK                0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT               6
+#define FTM_FLTCTRL_FFLTR2EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR2EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK                0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT               7
+#define FTM_FLTCTRL_FFLTR3EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR3EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK                   0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT                  8
+#define FTM_FLTCTRL_FFVAL_WIDTH                  4
+#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK                   0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT                  0
+#define FTM_QDCTRL_QUADEN_WIDTH                  1
+#define FTM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK                   0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT                  1
+#define FTM_QDCTRL_TOFDIR_WIDTH                  1
+#define FTM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK                   0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT                  2
+#define FTM_QDCTRL_QUADIR_WIDTH                  1
+#define FTM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK                 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT                3
+#define FTM_QDCTRL_QUADMODE_WIDTH                1
+#define FTM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK                   0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT                  4
+#define FTM_QDCTRL_PHBPOL_WIDTH                  1
+#define FTM_QDCTRL_PHBPOL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK                   0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT                  5
+#define FTM_QDCTRL_PHAPOL_WIDTH                  1
+#define FTM_QDCTRL_PHAPOL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK                0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT               6
+#define FTM_QDCTRL_PHBFLTREN_WIDTH               1
+#define FTM_QDCTRL_PHBFLTREN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK                0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT               7
+#define FTM_QDCTRL_PHAFLTREN_WIDTH               1
+#define FTM_QDCTRL_PHAFLTREN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK                     0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT                    0
+#define FTM_CONF_NUMTOF_WIDTH                    5
+#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK                    0xC0u
+#define FTM_CONF_BDMMODE_SHIFT                   6
+#define FTM_CONF_BDMMODE_WIDTH                   2
+#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK                     0x200u
+#define FTM_CONF_GTBEEN_SHIFT                    9
+#define FTM_CONF_GTBEEN_WIDTH                    1
+#define FTM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK                    0x400u
+#define FTM_CONF_GTBEOUT_SHIFT                   10
+#define FTM_CONF_GTBEOUT_WIDTH                   1
+#define FTM_CONF_GTBEOUT(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK                  0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT                 0
+#define FTM_FLTPOL_FLT0POL_WIDTH                 1
+#define FTM_FLTPOL_FLT0POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK                  0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT                 1
+#define FTM_FLTPOL_FLT1POL_WIDTH                 1
+#define FTM_FLTPOL_FLT1POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK                  0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT                 2
+#define FTM_FLTPOL_FLT2POL_WIDTH                 1
+#define FTM_FLTPOL_FLT2POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK                  0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT                 3
+#define FTM_FLTPOL_FLT3POL_WIDTH                 1
+#define FTM_FLTPOL_FLT3POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK              0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT             0
+#define FTM_SYNCONF_HWTRIGMODE_WIDTH             1
+#define FTM_SYNCONF_HWTRIGMODE(x)                (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK                  0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT                 2
+#define FTM_SYNCONF_CNTINC_WIDTH                 1
+#define FTM_SYNCONF_CNTINC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK                    0x10u
+#define FTM_SYNCONF_INVC_SHIFT                   4
+#define FTM_SYNCONF_INVC_WIDTH                   1
+#define FTM_SYNCONF_INVC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK                    0x20u
+#define FTM_SYNCONF_SWOC_SHIFT                   5
+#define FTM_SYNCONF_SWOC_WIDTH                   1
+#define FTM_SYNCONF_SWOC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK                0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT               7
+#define FTM_SYNCONF_SYNCMODE_WIDTH               1
+#define FTM_SYNCONF_SYNCMODE(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK                0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT               8
+#define FTM_SYNCONF_SWRSTCNT_WIDTH               1
+#define FTM_SYNCONF_SWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK                 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT                9
+#define FTM_SYNCONF_SWWRBUF_WIDTH                1
+#define FTM_SYNCONF_SWWRBUF(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK                    0x400u
+#define FTM_SYNCONF_SWOM_SHIFT                   10
+#define FTM_SYNCONF_SWOM_WIDTH                   1
+#define FTM_SYNCONF_SWOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK                  0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT                 11
+#define FTM_SYNCONF_SWINVC_WIDTH                 1
+#define FTM_SYNCONF_SWINVC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK                   0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT                  12
+#define FTM_SYNCONF_SWSOC_WIDTH                  1
+#define FTM_SYNCONF_SWSOC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK                0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT               16
+#define FTM_SYNCONF_HWRSTCNT_WIDTH               1
+#define FTM_SYNCONF_HWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK                 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT                17
+#define FTM_SYNCONF_HWWRBUF_WIDTH                1
+#define FTM_SYNCONF_HWWRBUF(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK                    0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT                   18
+#define FTM_SYNCONF_HWOM_WIDTH                   1
+#define FTM_SYNCONF_HWOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK                  0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT                 19
+#define FTM_SYNCONF_HWINVC_WIDTH                 1
+#define FTM_SYNCONF_HWINVC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK                   0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT                  20
+#define FTM_SYNCONF_HWSOC_WIDTH                  1
+#define FTM_SYNCONF_HWSOC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK                  0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT                 0
+#define FTM_INVCTRL_INV0EN_WIDTH                 1
+#define FTM_INVCTRL_INV0EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK                  0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT                 1
+#define FTM_INVCTRL_INV1EN_WIDTH                 1
+#define FTM_INVCTRL_INV1EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK                  0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT                 2
+#define FTM_INVCTRL_INV2EN_WIDTH                 1
+#define FTM_INVCTRL_INV2EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK                  0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT                 3
+#define FTM_INVCTRL_INV3EN_WIDTH                 1
+#define FTM_INVCTRL_INV3EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK                   0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT                  0
+#define FTM_SWOCTRL_CH0OC_WIDTH                  1
+#define FTM_SWOCTRL_CH0OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK                   0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT                  1
+#define FTM_SWOCTRL_CH1OC_WIDTH                  1
+#define FTM_SWOCTRL_CH1OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK                   0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT                  2
+#define FTM_SWOCTRL_CH2OC_WIDTH                  1
+#define FTM_SWOCTRL_CH2OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK                   0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT                  3
+#define FTM_SWOCTRL_CH3OC_WIDTH                  1
+#define FTM_SWOCTRL_CH3OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK                   0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT                  4
+#define FTM_SWOCTRL_CH4OC_WIDTH                  1
+#define FTM_SWOCTRL_CH4OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK                   0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT                  5
+#define FTM_SWOCTRL_CH5OC_WIDTH                  1
+#define FTM_SWOCTRL_CH5OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK                   0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT                  6
+#define FTM_SWOCTRL_CH6OC_WIDTH                  1
+#define FTM_SWOCTRL_CH6OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK                   0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT                  7
+#define FTM_SWOCTRL_CH7OC_WIDTH                  1
+#define FTM_SWOCTRL_CH7OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK                  0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT                 8
+#define FTM_SWOCTRL_CH0OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH0OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK                  0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT                 9
+#define FTM_SWOCTRL_CH1OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH1OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK                  0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT                 10
+#define FTM_SWOCTRL_CH2OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH2OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK                  0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT                 11
+#define FTM_SWOCTRL_CH3OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH3OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK                  0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT                 12
+#define FTM_SWOCTRL_CH4OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH4OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK                  0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT                 13
+#define FTM_SWOCTRL_CH5OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH5OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK                  0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT                 14
+#define FTM_SWOCTRL_CH6OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH6OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK                  0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT                 15
+#define FTM_SWOCTRL_CH7OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH7OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK                  0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT                 0
+#define FTM_PWMLOAD_CH0SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH0SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK                  0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT                 1
+#define FTM_PWMLOAD_CH1SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH1SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK                  0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT                 2
+#define FTM_PWMLOAD_CH2SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH2SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK                  0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT                 3
+#define FTM_PWMLOAD_CH3SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH3SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK                  0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT                 4
+#define FTM_PWMLOAD_CH4SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH4SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK                  0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT                 5
+#define FTM_PWMLOAD_CH5SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH5SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK                  0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT                 6
+#define FTM_PWMLOAD_CH6SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH6SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK                  0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT                 7
+#define FTM_PWMLOAD_CH7SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH7SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK                    0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT                   9
+#define FTM_PWMLOAD_LDOK_WIDTH                   1
+#define FTM_PWMLOAD_LDOK(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE                                (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0                                     ((FTM_Type *)FTM0_BASE)
+#define FTM0_BASE_PTR                            (FTM0)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE                                (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1                                     ((FTM_Type *)FTM1_BASE)
+#define FTM1_BASE_PTR                            (FTM1)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE                                (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2                                     ((FTM_Type *)FTM2_BASE)
+#define FTM2_BASE_PTR                            (FTM2)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE                                (0x400B9000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3                                     ((FTM_Type *)FTM3_BASE)
+#define FTM3_BASE_PTR                            (FTM3)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS                           { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS                            { FTM0, FTM1, FTM2, FTM3 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS                                 { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register instance definitions */
+/* FTM0 */
+#define FTM0_SC                                  FTM_SC_REG(FTM0)
+#define FTM0_CNT                                 FTM_CNT_REG(FTM0)
+#define FTM0_MOD                                 FTM_MOD_REG(FTM0)
+#define FTM0_C0SC                                FTM_CnSC_REG(FTM0,0)
+#define FTM0_C0V                                 FTM_CnV_REG(FTM0,0)
+#define FTM0_C1SC                                FTM_CnSC_REG(FTM0,1)
+#define FTM0_C1V                                 FTM_CnV_REG(FTM0,1)
+#define FTM0_C2SC                                FTM_CnSC_REG(FTM0,2)
+#define FTM0_C2V                                 FTM_CnV_REG(FTM0,2)
+#define FTM0_C3SC                                FTM_CnSC_REG(FTM0,3)
+#define FTM0_C3V                                 FTM_CnV_REG(FTM0,3)
+#define FTM0_C4SC                                FTM_CnSC_REG(FTM0,4)
+#define FTM0_C4V                                 FTM_CnV_REG(FTM0,4)
+#define FTM0_C5SC                                FTM_CnSC_REG(FTM0,5)
+#define FTM0_C5V                                 FTM_CnV_REG(FTM0,5)
+#define FTM0_C6SC                                FTM_CnSC_REG(FTM0,6)
+#define FTM0_C6V                                 FTM_CnV_REG(FTM0,6)
+#define FTM0_C7SC                                FTM_CnSC_REG(FTM0,7)
+#define FTM0_C7V                                 FTM_CnV_REG(FTM0,7)
+#define FTM0_CNTIN                               FTM_CNTIN_REG(FTM0)
+#define FTM0_STATUS                              FTM_STATUS_REG(FTM0)
+#define FTM0_MODE                                FTM_MODE_REG(FTM0)
+#define FTM0_SYNC                                FTM_SYNC_REG(FTM0)
+#define FTM0_OUTINIT                             FTM_OUTINIT_REG(FTM0)
+#define FTM0_OUTMASK                             FTM_OUTMASK_REG(FTM0)
+#define FTM0_COMBINE                             FTM_COMBINE_REG(FTM0)
+#define FTM0_DEADTIME                            FTM_DEADTIME_REG(FTM0)
+#define FTM0_EXTTRIG                             FTM_EXTTRIG_REG(FTM0)
+#define FTM0_POL                                 FTM_POL_REG(FTM0)
+#define FTM0_FMS                                 FTM_FMS_REG(FTM0)
+#define FTM0_FILTER                              FTM_FILTER_REG(FTM0)
+#define FTM0_FLTCTRL                             FTM_FLTCTRL_REG(FTM0)
+#define FTM0_QDCTRL                              FTM_QDCTRL_REG(FTM0)
+#define FTM0_CONF                                FTM_CONF_REG(FTM0)
+#define FTM0_FLTPOL                              FTM_FLTPOL_REG(FTM0)
+#define FTM0_SYNCONF                             FTM_SYNCONF_REG(FTM0)
+#define FTM0_INVCTRL                             FTM_INVCTRL_REG(FTM0)
+#define FTM0_SWOCTRL                             FTM_SWOCTRL_REG(FTM0)
+#define FTM0_PWMLOAD                             FTM_PWMLOAD_REG(FTM0)
+/* FTM1 */
+#define FTM1_SC                                  FTM_SC_REG(FTM1)
+#define FTM1_CNT                                 FTM_CNT_REG(FTM1)
+#define FTM1_MOD                                 FTM_MOD_REG(FTM1)
+#define FTM1_C0SC                                FTM_CnSC_REG(FTM1,0)
+#define FTM1_C0V                                 FTM_CnV_REG(FTM1,0)
+#define FTM1_C1SC                                FTM_CnSC_REG(FTM1,1)
+#define FTM1_C1V                                 FTM_CnV_REG(FTM1,1)
+#define FTM1_CNTIN                               FTM_CNTIN_REG(FTM1)
+#define FTM1_STATUS                              FTM_STATUS_REG(FTM1)
+#define FTM1_MODE                                FTM_MODE_REG(FTM1)
+#define FTM1_SYNC                                FTM_SYNC_REG(FTM1)
+#define FTM1_OUTINIT                             FTM_OUTINIT_REG(FTM1)
+#define FTM1_OUTMASK                             FTM_OUTMASK_REG(FTM1)
+#define FTM1_COMBINE                             FTM_COMBINE_REG(FTM1)
+#define FTM1_DEADTIME                            FTM_DEADTIME_REG(FTM1)
+#define FTM1_EXTTRIG                             FTM_EXTTRIG_REG(FTM1)
+#define FTM1_POL                                 FTM_POL_REG(FTM1)
+#define FTM1_FMS                                 FTM_FMS_REG(FTM1)
+#define FTM1_FILTER                              FTM_FILTER_REG(FTM1)
+#define FTM1_FLTCTRL                             FTM_FLTCTRL_REG(FTM1)
+#define FTM1_QDCTRL                              FTM_QDCTRL_REG(FTM1)
+#define FTM1_CONF                                FTM_CONF_REG(FTM1)
+#define FTM1_FLTPOL                              FTM_FLTPOL_REG(FTM1)
+#define FTM1_SYNCONF                             FTM_SYNCONF_REG(FTM1)
+#define FTM1_INVCTRL                             FTM_INVCTRL_REG(FTM1)
+#define FTM1_SWOCTRL                             FTM_SWOCTRL_REG(FTM1)
+#define FTM1_PWMLOAD                             FTM_PWMLOAD_REG(FTM1)
+/* FTM2 */
+#define FTM2_SC                                  FTM_SC_REG(FTM2)
+#define FTM2_CNT                                 FTM_CNT_REG(FTM2)
+#define FTM2_MOD                                 FTM_MOD_REG(FTM2)
+#define FTM2_C0SC                                FTM_CnSC_REG(FTM2,0)
+#define FTM2_C0V                                 FTM_CnV_REG(FTM2,0)
+#define FTM2_C1SC                                FTM_CnSC_REG(FTM2,1)
+#define FTM2_C1V                                 FTM_CnV_REG(FTM2,1)
+#define FTM2_CNTIN                               FTM_CNTIN_REG(FTM2)
+#define FTM2_STATUS                              FTM_STATUS_REG(FTM2)
+#define FTM2_MODE                                FTM_MODE_REG(FTM2)
+#define FTM2_SYNC                                FTM_SYNC_REG(FTM2)
+#define FTM2_OUTINIT                             FTM_OUTINIT_REG(FTM2)
+#define FTM2_OUTMASK                             FTM_OUTMASK_REG(FTM2)
+#define FTM2_COMBINE                             FTM_COMBINE_REG(FTM2)
+#define FTM2_DEADTIME                            FTM_DEADTIME_REG(FTM2)
+#define FTM2_EXTTRIG                             FTM_EXTTRIG_REG(FTM2)
+#define FTM2_POL                                 FTM_POL_REG(FTM2)
+#define FTM2_FMS                                 FTM_FMS_REG(FTM2)
+#define FTM2_FILTER                              FTM_FILTER_REG(FTM2)
+#define FTM2_FLTCTRL                             FTM_FLTCTRL_REG(FTM2)
+#define FTM2_QDCTRL                              FTM_QDCTRL_REG(FTM2)
+#define FTM2_CONF                                FTM_CONF_REG(FTM2)
+#define FTM2_FLTPOL                              FTM_FLTPOL_REG(FTM2)
+#define FTM2_SYNCONF                             FTM_SYNCONF_REG(FTM2)
+#define FTM2_INVCTRL                             FTM_INVCTRL_REG(FTM2)
+#define FTM2_SWOCTRL                             FTM_SWOCTRL_REG(FTM2)
+#define FTM2_PWMLOAD                             FTM_PWMLOAD_REG(FTM2)
+/* FTM3 */
+#define FTM3_SC                                  FTM_SC_REG(FTM3)
+#define FTM3_CNT                                 FTM_CNT_REG(FTM3)
+#define FTM3_MOD                                 FTM_MOD_REG(FTM3)
+#define FTM3_C0SC                                FTM_CnSC_REG(FTM3,0)
+#define FTM3_C0V                                 FTM_CnV_REG(FTM3,0)
+#define FTM3_C1SC                                FTM_CnSC_REG(FTM3,1)
+#define FTM3_C1V                                 FTM_CnV_REG(FTM3,1)
+#define FTM3_C2SC                                FTM_CnSC_REG(FTM3,2)
+#define FTM3_C2V                                 FTM_CnV_REG(FTM3,2)
+#define FTM3_C3SC                                FTM_CnSC_REG(FTM3,3)
+#define FTM3_C3V                                 FTM_CnV_REG(FTM3,3)
+#define FTM3_C4SC                                FTM_CnSC_REG(FTM3,4)
+#define FTM3_C4V                                 FTM_CnV_REG(FTM3,4)
+#define FTM3_C5SC                                FTM_CnSC_REG(FTM3,5)
+#define FTM3_C5V                                 FTM_CnV_REG(FTM3,5)
+#define FTM3_C6SC                                FTM_CnSC_REG(FTM3,6)
+#define FTM3_C6V                                 FTM_CnV_REG(FTM3,6)
+#define FTM3_C7SC                                FTM_CnSC_REG(FTM3,7)
+#define FTM3_C7V                                 FTM_CnV_REG(FTM3,7)
+#define FTM3_CNTIN                               FTM_CNTIN_REG(FTM3)
+#define FTM3_STATUS                              FTM_STATUS_REG(FTM3)
+#define FTM3_MODE                                FTM_MODE_REG(FTM3)
+#define FTM3_SYNC                                FTM_SYNC_REG(FTM3)
+#define FTM3_OUTINIT                             FTM_OUTINIT_REG(FTM3)
+#define FTM3_OUTMASK                             FTM_OUTMASK_REG(FTM3)
+#define FTM3_COMBINE                             FTM_COMBINE_REG(FTM3)
+#define FTM3_DEADTIME                            FTM_DEADTIME_REG(FTM3)
+#define FTM3_EXTTRIG                             FTM_EXTTRIG_REG(FTM3)
+#define FTM3_POL                                 FTM_POL_REG(FTM3)
+#define FTM3_FMS                                 FTM_FMS_REG(FTM3)
+#define FTM3_FILTER                              FTM_FILTER_REG(FTM3)
+#define FTM3_FLTCTRL                             FTM_FLTCTRL_REG(FTM3)
+#define FTM3_QDCTRL                              FTM_QDCTRL_REG(FTM3)
+#define FTM3_CONF                                FTM_CONF_REG(FTM3)
+#define FTM3_FLTPOL                              FTM_FLTPOL_REG(FTM3)
+#define FTM3_SYNCONF                             FTM_SYNCONF_REG(FTM3)
+#define FTM3_INVCTRL                             FTM_INVCTRL_REG(FTM3)
+#define FTM3_SWOCTRL                             FTM_SWOCTRL_REG(FTM3)
+#define FTM3_PWMLOAD                             FTM_PWMLOAD_REG(FTM3)
+
+/* FTM - Register array accessors */
+#define FTM0_CnSC(index)                         FTM_CnSC_REG(FTM0,index)
+#define FTM1_CnSC(index)                         FTM_CnSC_REG(FTM1,index)
+#define FTM2_CnSC(index)                         FTM_CnSC_REG(FTM2,index)
+#define FTM3_CnSC(index)                         FTM_CnSC_REG(FTM3,index)
+#define FTM0_CnV(index)                          FTM_CnV_REG(FTM0,index)
+#define FTM1_CnV(index)                          FTM_CnV_REG(FTM1,index)
+#define FTM2_CnV(index)                          FTM_CnV_REG(FTM2,index)
+#define FTM3_CnV(index)                          FTM_CnV_REG(FTM3,index)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base)                      ((base)->PDOR)
+#define GPIO_PSOR_REG(base)                      ((base)->PSOR)
+#define GPIO_PCOR_REG(base)                      ((base)->PCOR)
+#define GPIO_PTOR_REG(base)                      ((base)->PTOR)
+#define GPIO_PDIR_REG(base)                      ((base)->PDIR)
+#define GPIO_PDDR_REG(base)                      ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT                      0
+#define GPIO_PDOR_PDO_WIDTH                      32
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT                     0
+#define GPIO_PSOR_PTSO_WIDTH                     32
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT                     0
+#define GPIO_PCOR_PTCO_WIDTH                     32
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT                     0
+#define GPIO_PTOR_PTTO_WIDTH                     32
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT                      0
+#define GPIO_PDIR_PDI_WIDTH                      32
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT                      0
+#define GPIO_PDDR_PDD_WIDTH                      32
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE                                 (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA                                      ((GPIO_Type *)PTA_BASE)
+#define PTA_BASE_PTR                             (PTA)
+/** Peripheral PTB base address */
+#define PTB_BASE                                 (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB                                      ((GPIO_Type *)PTB_BASE)
+#define PTB_BASE_PTR                             (PTB)
+/** Peripheral PTC base address */
+#define PTC_BASE                                 (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC                                      ((GPIO_Type *)PTC_BASE)
+#define PTC_BASE_PTR                             (PTC)
+/** Peripheral PTD base address */
+#define PTD_BASE                                 (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD                                      ((GPIO_Type *)PTD_BASE)
+#define PTD_BASE_PTR                             (PTD)
+/** Peripheral PTE base address */
+#define PTE_BASE                                 (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE                                      ((GPIO_Type *)PTE_BASE)
+#define PTE_BASE_PTR                             (PTE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { PTA, PTB, PTC, PTD, PTE }
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* PTA */
+#define GPIOA_PDOR                               GPIO_PDOR_REG(PTA)
+#define GPIOA_PSOR                               GPIO_PSOR_REG(PTA)
+#define GPIOA_PCOR                               GPIO_PCOR_REG(PTA)
+#define GPIOA_PTOR                               GPIO_PTOR_REG(PTA)
+#define GPIOA_PDIR                               GPIO_PDIR_REG(PTA)
+#define GPIOA_PDDR                               GPIO_PDDR_REG(PTA)
+/* PTB */
+#define GPIOB_PDOR                               GPIO_PDOR_REG(PTB)
+#define GPIOB_PSOR                               GPIO_PSOR_REG(PTB)
+#define GPIOB_PCOR                               GPIO_PCOR_REG(PTB)
+#define GPIOB_PTOR                               GPIO_PTOR_REG(PTB)
+#define GPIOB_PDIR                               GPIO_PDIR_REG(PTB)
+#define GPIOB_PDDR                               GPIO_PDDR_REG(PTB)
+/* PTC */
+#define GPIOC_PDOR                               GPIO_PDOR_REG(PTC)
+#define GPIOC_PSOR                               GPIO_PSOR_REG(PTC)
+#define GPIOC_PCOR                               GPIO_PCOR_REG(PTC)
+#define GPIOC_PTOR                               GPIO_PTOR_REG(PTC)
+#define GPIOC_PDIR                               GPIO_PDIR_REG(PTC)
+#define GPIOC_PDDR                               GPIO_PDDR_REG(PTC)
+/* PTD */
+#define GPIOD_PDOR                               GPIO_PDOR_REG(PTD)
+#define GPIOD_PSOR                               GPIO_PSOR_REG(PTD)
+#define GPIOD_PCOR                               GPIO_PCOR_REG(PTD)
+#define GPIOD_PTOR                               GPIO_PTOR_REG(PTD)
+#define GPIOD_PDIR                               GPIO_PDIR_REG(PTD)
+#define GPIOD_PDDR                               GPIO_PDDR_REG(PTD)
+/* PTE */
+#define GPIOE_PDOR                               GPIO_PDOR_REG(PTE)
+#define GPIOE_PSOR                               GPIO_PSOR_REG(PTE)
+#define GPIOE_PCOR                               GPIO_PCOR_REG(PTE)
+#define GPIOE_PTOR                               GPIO_PTOR_REG(PTE)
+#define GPIOE_PDIR                               GPIO_PDIR_REG(PTE)
+#define GPIOE_PDDR                               GPIO_PDDR_REG(PTE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base)                         ((base)->A1)
+#define I2C_F_REG(base)                          ((base)->F)
+#define I2C_C1_REG(base)                         ((base)->C1)
+#define I2C_S_REG(base)                          ((base)->S)
+#define I2C_D_REG(base)                          ((base)->D)
+#define I2C_C2_REG(base)                         ((base)->C2)
+#define I2C_FLT_REG(base)                        ((base)->FLT)
+#define I2C_RA_REG(base)                         ((base)->RA)
+#define I2C_SMB_REG(base)                        ((base)->SMB)
+#define I2C_A2_REG(base)                         ((base)->A2)
+#define I2C_SLTH_REG(base)                       ((base)->SLTH)
+#define I2C_SLTL_REG(base)                       ((base)->SLTL)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK                           0xFEu
+#define I2C_A1_AD_SHIFT                          1
+#define I2C_A1_AD_WIDTH                          7
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK                           0x3Fu
+#define I2C_F_ICR_SHIFT                          0
+#define I2C_F_ICR_WIDTH                          6
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          0xC0u
+#define I2C_F_MULT_SHIFT                         6
+#define I2C_F_MULT_WIDTH                         2
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK                        0x1u
+#define I2C_C1_DMAEN_SHIFT                       0
+#define I2C_C1_DMAEN_WIDTH                       1
+#define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_DMAEN_SHIFT))&I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK                         0x2u
+#define I2C_C1_WUEN_SHIFT                        1
+#define I2C_C1_WUEN_WIDTH                        1
+#define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_WUEN_SHIFT))&I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK                         0x4u
+#define I2C_C1_RSTA_SHIFT                        2
+#define I2C_C1_RSTA_WIDTH                        1
+#define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_RSTA_SHIFT))&I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK                         0x8u
+#define I2C_C1_TXAK_SHIFT                        3
+#define I2C_C1_TXAK_WIDTH                        1
+#define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_TXAK_SHIFT))&I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK                           0x10u
+#define I2C_C1_TX_SHIFT                          4
+#define I2C_C1_TX_WIDTH                          1
+#define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C1_TX_SHIFT))&I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK                          0x20u
+#define I2C_C1_MST_SHIFT                         5
+#define I2C_C1_MST_WIDTH                         1
+#define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_C1_MST_SHIFT))&I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK                        0x40u
+#define I2C_C1_IICIE_SHIFT                       6
+#define I2C_C1_IICIE_WIDTH                       1
+#define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICIE_SHIFT))&I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK                        0x80u
+#define I2C_C1_IICEN_SHIFT                       7
+#define I2C_C1_IICEN_WIDTH                       1
+#define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICEN_SHIFT))&I2C_C1_IICEN_MASK)
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK                          0x1u
+#define I2C_S_RXAK_SHIFT                         0
+#define I2C_S_RXAK_WIDTH                         1
+#define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_RXAK_SHIFT))&I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK                         0x2u
+#define I2C_S_IICIF_SHIFT                        1
+#define I2C_S_IICIF_WIDTH                        1
+#define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_S_IICIF_SHIFT))&I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK                           0x4u
+#define I2C_S_SRW_SHIFT                          2
+#define I2C_S_SRW_WIDTH                          1
+#define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_SRW_SHIFT))&I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK                           0x8u
+#define I2C_S_RAM_SHIFT                          3
+#define I2C_S_RAM_WIDTH                          1
+#define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_RAM_SHIFT))&I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK                          0x10u
+#define I2C_S_ARBL_SHIFT                         4
+#define I2C_S_ARBL_WIDTH                         1
+#define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_ARBL_SHIFT))&I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK                          0x20u
+#define I2C_S_BUSY_SHIFT                         5
+#define I2C_S_BUSY_WIDTH                         1
+#define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_BUSY_SHIFT))&I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK                          0x40u
+#define I2C_S_IAAS_SHIFT                         6
+#define I2C_S_IAAS_WIDTH                         1
+#define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_IAAS_SHIFT))&I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK                           0x80u
+#define I2C_S_TCF_SHIFT                          7
+#define I2C_S_TCF_WIDTH                          1
+#define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_TCF_SHIFT))&I2C_S_TCF_MASK)
+/* D Bit Fields */
+#define I2C_D_DATA_MASK                          0xFFu
+#define I2C_D_DATA_SHIFT                         0
+#define I2C_D_DATA_WIDTH                         8
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK                           0x7u
+#define I2C_C2_AD_SHIFT                          0
+#define I2C_C2_AD_WIDTH                          3
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         0x8u
+#define I2C_C2_RMEN_SHIFT                        3
+#define I2C_C2_RMEN_WIDTH                        1
+#define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_RMEN_SHIFT))&I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK                         0x10u
+#define I2C_C2_SBRC_SHIFT                        4
+#define I2C_C2_SBRC_WIDTH                        1
+#define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_SBRC_SHIFT))&I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK                         0x20u
+#define I2C_C2_HDRS_SHIFT                        5
+#define I2C_C2_HDRS_WIDTH                        1
+#define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_HDRS_SHIFT))&I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK                        0x40u
+#define I2C_C2_ADEXT_SHIFT                       6
+#define I2C_C2_ADEXT_WIDTH                       1
+#define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_ADEXT_SHIFT))&I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK                        0x80u
+#define I2C_C2_GCAEN_SHIFT                       7
+#define I2C_C2_GCAEN_WIDTH                       1
+#define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_GCAEN_SHIFT))&I2C_C2_GCAEN_MASK)
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK                         0xFu
+#define I2C_FLT_FLT_SHIFT                        0
+#define I2C_FLT_FLT_WIDTH                        4
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK                      0x10u
+#define I2C_FLT_STARTF_SHIFT                     4
+#define I2C_FLT_STARTF_WIDTH                     1
+#define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STARTF_SHIFT))&I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK                        0x20u
+#define I2C_FLT_SSIE_SHIFT                       5
+#define I2C_FLT_SSIE_WIDTH                       1
+#define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SSIE_SHIFT))&I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK                       0x40u
+#define I2C_FLT_STOPF_SHIFT                      6
+#define I2C_FLT_STOPF_WIDTH                      1
+#define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STOPF_SHIFT))&I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK                        0x80u
+#define I2C_FLT_SHEN_SHIFT                       7
+#define I2C_FLT_SHEN_WIDTH                       1
+#define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SHEN_SHIFT))&I2C_FLT_SHEN_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK                          0xFEu
+#define I2C_RA_RAD_SHIFT                         1
+#define I2C_RA_RAD_WIDTH                         7
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK                     0x1u
+#define I2C_SMB_SHTF2IE_SHIFT                    0
+#define I2C_SMB_SHTF2IE_WIDTH                    1
+#define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2IE_SHIFT))&I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK                       0x2u
+#define I2C_SMB_SHTF2_SHIFT                      1
+#define I2C_SMB_SHTF2_WIDTH                      1
+#define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2_SHIFT))&I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK                       0x4u
+#define I2C_SMB_SHTF1_SHIFT                      2
+#define I2C_SMB_SHTF1_WIDTH                      1
+#define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF1_SHIFT))&I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK                        0x8u
+#define I2C_SMB_SLTF_SHIFT                       3
+#define I2C_SMB_SLTF_WIDTH                       1
+#define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SLTF_SHIFT))&I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK                      0x10u
+#define I2C_SMB_TCKSEL_SHIFT                     4
+#define I2C_SMB_TCKSEL_WIDTH                     1
+#define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_SMB_TCKSEL_SHIFT))&I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK                     0x20u
+#define I2C_SMB_SIICAEN_SHIFT                    5
+#define I2C_SMB_SIICAEN_WIDTH                    1
+#define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SIICAEN_SHIFT))&I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK                     0x40u
+#define I2C_SMB_ALERTEN_SHIFT                    6
+#define I2C_SMB_ALERTEN_WIDTH                    1
+#define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_ALERTEN_SHIFT))&I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK                        0x80u
+#define I2C_SMB_FACK_SHIFT                       7
+#define I2C_SMB_FACK_WIDTH                       1
+#define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_FACK_SHIFT))&I2C_SMB_FACK_MASK)
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK                          0xFEu
+#define I2C_A2_SAD_SHIFT                         1
+#define I2C_A2_SAD_WIDTH                         7
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK                       0xFFu
+#define I2C_SLTH_SSLT_SHIFT                      0
+#define I2C_SLTH_SSLT_WIDTH                      8
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK                       0xFFu
+#define I2C_SLTL_SSLT_SHIFT                      0
+#define I2C_SLTL_SSLT_WIDTH                      8
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR                            (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR                            (I2C1)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x400E6000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+#define I2C2_BASE_PTR                            (I2C2)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1                                  I2C_A1_REG(I2C0)
+#define I2C0_F                                   I2C_F_REG(I2C0)
+#define I2C0_C1                                  I2C_C1_REG(I2C0)
+#define I2C0_S                                   I2C_S_REG(I2C0)
+#define I2C0_D                                   I2C_D_REG(I2C0)
+#define I2C0_C2                                  I2C_C2_REG(I2C0)
+#define I2C0_FLT                                 I2C_FLT_REG(I2C0)
+#define I2C0_RA                                  I2C_RA_REG(I2C0)
+#define I2C0_SMB                                 I2C_SMB_REG(I2C0)
+#define I2C0_A2                                  I2C_A2_REG(I2C0)
+#define I2C0_SLTH                                I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL                                I2C_SLTL_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1                                  I2C_A1_REG(I2C1)
+#define I2C1_F                                   I2C_F_REG(I2C1)
+#define I2C1_C1                                  I2C_C1_REG(I2C1)
+#define I2C1_S                                   I2C_S_REG(I2C1)
+#define I2C1_D                                   I2C_D_REG(I2C1)
+#define I2C1_C2                                  I2C_C2_REG(I2C1)
+#define I2C1_FLT                                 I2C_FLT_REG(I2C1)
+#define I2C1_RA                                  I2C_RA_REG(I2C1)
+#define I2C1_SMB                                 I2C_SMB_REG(I2C1)
+#define I2C1_A2                                  I2C_A2_REG(I2C1)
+#define I2C1_SLTH                                I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL                                I2C_SLTL_REG(I2C1)
+/* I2C2 */
+#define I2C2_A1                                  I2C_A1_REG(I2C2)
+#define I2C2_F                                   I2C_F_REG(I2C2)
+#define I2C2_C1                                  I2C_C1_REG(I2C2)
+#define I2C2_S                                   I2C_S_REG(I2C2)
+#define I2C2_D                                   I2C_D_REG(I2C2)
+#define I2C2_C2                                  I2C_C2_REG(I2C2)
+#define I2C2_FLT                                 I2C_FLT_REG(I2C2)
+#define I2C2_RA                                  I2C_RA_REG(I2C2)
+#define I2C2_SMB                                 I2C_SMB_REG(I2C2)
+#define I2C2_A2                                  I2C_A2_REG(I2C2)
+#define I2C2_SLTH                                I2C_SLTH_REG(I2C2)
+#define I2C2_SLTL                                I2C_SLTL_REG(I2C2)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
+  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t TDR[2];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __I  uint32_t TFR[2];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_3[28];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
+  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t RDR[2];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[24];
+  __I  uint32_t RFR[2];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_6[24];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
+  __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base)                       ((base)->TCSR)
+#define I2S_TCR1_REG(base)                       ((base)->TCR1)
+#define I2S_TCR2_REG(base)                       ((base)->TCR2)
+#define I2S_TCR3_REG(base)                       ((base)->TCR3)
+#define I2S_TCR4_REG(base)                       ((base)->TCR4)
+#define I2S_TCR5_REG(base)                       ((base)->TCR5)
+#define I2S_TDR_REG(base,index)                  ((base)->TDR[index])
+#define I2S_TDR_COUNT                            2
+#define I2S_TFR_REG(base,index)                  ((base)->TFR[index])
+#define I2S_TFR_COUNT                            2
+#define I2S_TMR_REG(base)                        ((base)->TMR)
+#define I2S_RCSR_REG(base)                       ((base)->RCSR)
+#define I2S_RCR1_REG(base)                       ((base)->RCR1)
+#define I2S_RCR2_REG(base)                       ((base)->RCR2)
+#define I2S_RCR3_REG(base)                       ((base)->RCR3)
+#define I2S_RCR4_REG(base)                       ((base)->RCR4)
+#define I2S_RCR5_REG(base)                       ((base)->RCR5)
+#define I2S_RDR_REG(base,index)                  ((base)->RDR[index])
+#define I2S_RDR_COUNT                            2
+#define I2S_RFR_REG(base,index)                  ((base)->RFR[index])
+#define I2S_RFR_COUNT                            2
+#define I2S_RMR_REG(base)                        ((base)->RMR)
+#define I2S_MCR_REG(base)                        ((base)->MCR)
+#define I2S_MDR_REG(base)                        ((base)->MDR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK                       0x1u
+#define I2S_TCSR_FRDE_SHIFT                      0
+#define I2S_TCSR_FRDE_WIDTH                      1
+#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRDE_SHIFT))&I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK                       0x2u
+#define I2S_TCSR_FWDE_SHIFT                      1
+#define I2S_TCSR_FWDE_WIDTH                      1
+#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK                       0x100u
+#define I2S_TCSR_FRIE_SHIFT                      8
+#define I2S_TCSR_FRIE_WIDTH                      1
+#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRIE_SHIFT))&I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK                       0x200u
+#define I2S_TCSR_FWIE_SHIFT                      9
+#define I2S_TCSR_FWIE_WIDTH                      1
+#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK                       0x400u
+#define I2S_TCSR_FEIE_SHIFT                      10
+#define I2S_TCSR_FEIE_WIDTH                      1
+#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK                       0x800u
+#define I2S_TCSR_SEIE_SHIFT                      11
+#define I2S_TCSR_SEIE_WIDTH                      1
+#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK                       0x1000u
+#define I2S_TCSR_WSIE_SHIFT                      12
+#define I2S_TCSR_WSIE_WIDTH                      1
+#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK                        0x10000u
+#define I2S_TCSR_FRF_SHIFT                       16
+#define I2S_TCSR_FRF_WIDTH                       1
+#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRF_SHIFT))&I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK                        0x20000u
+#define I2S_TCSR_FWF_SHIFT                       17
+#define I2S_TCSR_FWF_WIDTH                       1
+#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK                        0x40000u
+#define I2S_TCSR_FEF_SHIFT                       18
+#define I2S_TCSR_FEF_WIDTH                       1
+#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK                        0x80000u
+#define I2S_TCSR_SEF_SHIFT                       19
+#define I2S_TCSR_SEF_WIDTH                       1
+#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK                        0x100000u
+#define I2S_TCSR_WSF_SHIFT                       20
+#define I2S_TCSR_WSF_WIDTH                       1
+#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK                         0x1000000u
+#define I2S_TCSR_SR_SHIFT                        24
+#define I2S_TCSR_SR_WIDTH                        1
+#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK                         0x2000000u
+#define I2S_TCSR_FR_SHIFT                        25
+#define I2S_TCSR_FR_WIDTH                        1
+#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK                        0x10000000u
+#define I2S_TCSR_BCE_SHIFT                       28
+#define I2S_TCSR_BCE_WIDTH                       1
+#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK                       0x20000000u
+#define I2S_TCSR_DBGE_SHIFT                      29
+#define I2S_TCSR_DBGE_WIDTH                      1
+#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK                      0x40000000u
+#define I2S_TCSR_STOPE_SHIFT                     30
+#define I2S_TCSR_STOPE_WIDTH                     1
+#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK                         0x80000000u
+#define I2S_TCSR_TE_SHIFT                        31
+#define I2S_TCSR_TE_WIDTH                        1
+#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK                        0x7u
+#define I2S_TCR1_TFW_SHIFT                       0
+#define I2S_TCR1_TFW_WIDTH                       3
+#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK                        0xFFu
+#define I2S_TCR2_DIV_SHIFT                       0
+#define I2S_TCR2_DIV_WIDTH                       8
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        0x1000000u
+#define I2S_TCR2_BCD_SHIFT                       24
+#define I2S_TCR2_BCD_WIDTH                       1
+#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK                        0x2000000u
+#define I2S_TCR2_BCP_SHIFT                       25
+#define I2S_TCR2_BCP_WIDTH                       1
+#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK                       0xC000000u
+#define I2S_TCR2_MSEL_SHIFT                      26
+#define I2S_TCR2_MSEL_WIDTH                      2
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK                        0x10000000u
+#define I2S_TCR2_BCI_SHIFT                       28
+#define I2S_TCR2_BCI_WIDTH                       1
+#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK                        0x20000000u
+#define I2S_TCR2_BCS_SHIFT                       29
+#define I2S_TCR2_BCS_WIDTH                       1
+#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK                       0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT                      30
+#define I2S_TCR2_SYNC_WIDTH                      2
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK                       0x1Fu
+#define I2S_TCR3_WDFL_SHIFT                      0
+#define I2S_TCR3_WDFL_WIDTH                      5
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        0x30000u
+#define I2S_TCR3_TCE_SHIFT                       16
+#define I2S_TCR3_TCE_WIDTH                       2
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK                        0x1u
+#define I2S_TCR4_FSD_SHIFT                       0
+#define I2S_TCR4_FSD_WIDTH                       1
+#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK                        0x2u
+#define I2S_TCR4_FSP_SHIFT                       1
+#define I2S_TCR4_FSP_WIDTH                       1
+#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSE_MASK                        0x8u
+#define I2S_TCR4_FSE_SHIFT                       3
+#define I2S_TCR4_FSE_WIDTH                       1
+#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK                         0x10u
+#define I2S_TCR4_MF_SHIFT                        4
+#define I2S_TCR4_MF_WIDTH                        1
+#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK                       0x1F00u
+#define I2S_TCR4_SYWD_SHIFT                      8
+#define I2S_TCR4_SYWD_WIDTH                      5
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT                      16
+#define I2S_TCR4_FRSZ_WIDTH                      5
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK                        0x1F00u
+#define I2S_TCR5_FBT_SHIFT                       8
+#define I2S_TCR5_FBT_WIDTH                       5
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        0x1F0000u
+#define I2S_TCR5_W0W_SHIFT                       16
+#define I2S_TCR5_W0W_WIDTH                       5
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        0x1F000000u
+#define I2S_TCR5_WNW_SHIFT                       24
+#define I2S_TCR5_WNW_WIDTH                       5
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT                        0
+#define I2S_TDR_TDR_WIDTH                        32
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK                         0xFu
+#define I2S_TFR_RFP_SHIFT                        0
+#define I2S_TFR_RFP_WIDTH                        4
+#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK                         0xF0000u
+#define I2S_TFR_WFP_SHIFT                        16
+#define I2S_TFR_WFP_WIDTH                        4
+#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK                         0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT                        0
+#define I2S_TMR_TWM_WIDTH                        32
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK                       0x1u
+#define I2S_RCSR_FRDE_SHIFT                      0
+#define I2S_RCSR_FRDE_WIDTH                      1
+#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRDE_SHIFT))&I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK                       0x2u
+#define I2S_RCSR_FWDE_SHIFT                      1
+#define I2S_RCSR_FWDE_WIDTH                      1
+#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK                       0x100u
+#define I2S_RCSR_FRIE_SHIFT                      8
+#define I2S_RCSR_FRIE_WIDTH                      1
+#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRIE_SHIFT))&I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK                       0x200u
+#define I2S_RCSR_FWIE_SHIFT                      9
+#define I2S_RCSR_FWIE_WIDTH                      1
+#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK                       0x400u
+#define I2S_RCSR_FEIE_SHIFT                      10
+#define I2S_RCSR_FEIE_WIDTH                      1
+#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK                       0x800u
+#define I2S_RCSR_SEIE_SHIFT                      11
+#define I2S_RCSR_SEIE_WIDTH                      1
+#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK                       0x1000u
+#define I2S_RCSR_WSIE_SHIFT                      12
+#define I2S_RCSR_WSIE_WIDTH                      1
+#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK                        0x10000u
+#define I2S_RCSR_FRF_SHIFT                       16
+#define I2S_RCSR_FRF_WIDTH                       1
+#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRF_SHIFT))&I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK                        0x20000u
+#define I2S_RCSR_FWF_SHIFT                       17
+#define I2S_RCSR_FWF_WIDTH                       1
+#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK                        0x40000u
+#define I2S_RCSR_FEF_SHIFT                       18
+#define I2S_RCSR_FEF_WIDTH                       1
+#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK                        0x80000u
+#define I2S_RCSR_SEF_SHIFT                       19
+#define I2S_RCSR_SEF_WIDTH                       1
+#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK                        0x100000u
+#define I2S_RCSR_WSF_SHIFT                       20
+#define I2S_RCSR_WSF_WIDTH                       1
+#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK                         0x1000000u
+#define I2S_RCSR_SR_SHIFT                        24
+#define I2S_RCSR_SR_WIDTH                        1
+#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK                         0x2000000u
+#define I2S_RCSR_FR_SHIFT                        25
+#define I2S_RCSR_FR_WIDTH                        1
+#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK                        0x10000000u
+#define I2S_RCSR_BCE_SHIFT                       28
+#define I2S_RCSR_BCE_WIDTH                       1
+#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK                       0x20000000u
+#define I2S_RCSR_DBGE_SHIFT                      29
+#define I2S_RCSR_DBGE_WIDTH                      1
+#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK                      0x40000000u
+#define I2S_RCSR_STOPE_SHIFT                     30
+#define I2S_RCSR_STOPE_WIDTH                     1
+#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK                         0x80000000u
+#define I2S_RCSR_RE_SHIFT                        31
+#define I2S_RCSR_RE_WIDTH                        1
+#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK                        0x7u
+#define I2S_RCR1_RFW_SHIFT                       0
+#define I2S_RCR1_RFW_WIDTH                       3
+#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK                        0xFFu
+#define I2S_RCR2_DIV_SHIFT                       0
+#define I2S_RCR2_DIV_WIDTH                       8
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        0x1000000u
+#define I2S_RCR2_BCD_SHIFT                       24
+#define I2S_RCR2_BCD_WIDTH                       1
+#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK                        0x2000000u
+#define I2S_RCR2_BCP_SHIFT                       25
+#define I2S_RCR2_BCP_WIDTH                       1
+#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK                       0xC000000u
+#define I2S_RCR2_MSEL_SHIFT                      26
+#define I2S_RCR2_MSEL_WIDTH                      2
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK                        0x10000000u
+#define I2S_RCR2_BCI_SHIFT                       28
+#define I2S_RCR2_BCI_WIDTH                       1
+#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK                        0x20000000u
+#define I2S_RCR2_BCS_SHIFT                       29
+#define I2S_RCR2_BCS_WIDTH                       1
+#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK                       0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT                      30
+#define I2S_RCR2_SYNC_WIDTH                      2
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK                       0x1Fu
+#define I2S_RCR3_WDFL_SHIFT                      0
+#define I2S_RCR3_WDFL_WIDTH                      5
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        0x30000u
+#define I2S_RCR3_RCE_SHIFT                       16
+#define I2S_RCR3_RCE_WIDTH                       2
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK                        0x1u
+#define I2S_RCR4_FSD_SHIFT                       0
+#define I2S_RCR4_FSD_WIDTH                       1
+#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK                        0x2u
+#define I2S_RCR4_FSP_SHIFT                       1
+#define I2S_RCR4_FSP_WIDTH                       1
+#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSE_MASK                        0x8u
+#define I2S_RCR4_FSE_SHIFT                       3
+#define I2S_RCR4_FSE_WIDTH                       1
+#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK                         0x10u
+#define I2S_RCR4_MF_SHIFT                        4
+#define I2S_RCR4_MF_WIDTH                        1
+#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK                       0x1F00u
+#define I2S_RCR4_SYWD_SHIFT                      8
+#define I2S_RCR4_SYWD_WIDTH                      5
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT                      16
+#define I2S_RCR4_FRSZ_WIDTH                      5
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK                        0x1F00u
+#define I2S_RCR5_FBT_SHIFT                       8
+#define I2S_RCR5_FBT_WIDTH                       5
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        0x1F0000u
+#define I2S_RCR5_W0W_SHIFT                       16
+#define I2S_RCR5_W0W_WIDTH                       5
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        0x1F000000u
+#define I2S_RCR5_WNW_SHIFT                       24
+#define I2S_RCR5_WNW_WIDTH                       5
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT                        0
+#define I2S_RDR_RDR_WIDTH                        32
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK                         0xFu
+#define I2S_RFR_RFP_SHIFT                        0
+#define I2S_RFR_RFP_WIDTH                        4
+#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK                         0xF0000u
+#define I2S_RFR_WFP_SHIFT                        16
+#define I2S_RFR_WFP_WIDTH                        4
+#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK                         0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT                        0
+#define I2S_RMR_RWM_WIDTH                        32
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK                        0x3000000u
+#define I2S_MCR_MICS_SHIFT                       24
+#define I2S_MCR_MICS_WIDTH                       2
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK                         0x40000000u
+#define I2S_MCR_MOE_SHIFT                        30
+#define I2S_MCR_MOE_WIDTH                        1
+#define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MOE_SHIFT))&I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK                         0x80000000u
+#define I2S_MCR_DUF_SHIFT                        31
+#define I2S_MCR_DUF_WIDTH                        1
+#define I2S_MCR_DUF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_DUF_SHIFT))&I2S_MCR_DUF_MASK)
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK                      0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT                     0
+#define I2S_MDR_DIVIDE_WIDTH                     12
+#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK                       0xFF000u
+#define I2S_MDR_FRACT_SHIFT                      12
+#define I2S_MDR_FRACT_WIDTH                      8
+#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR                            (I2S0)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS                              { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS                              { I2S0_Tx_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR                                I2S_TCSR_REG(I2S0)
+#define I2S0_TCR1                                I2S_TCR1_REG(I2S0)
+#define I2S0_TCR2                                I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3                                I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4                                I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5                                I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0                                I2S_TDR_REG(I2S0,0)
+#define I2S0_TDR1                                I2S_TDR_REG(I2S0,1)
+#define I2S0_TFR0                                I2S_TFR_REG(I2S0,0)
+#define I2S0_TFR1                                I2S_TFR_REG(I2S0,1)
+#define I2S0_TMR                                 I2S_TMR_REG(I2S0)
+#define I2S0_RCSR                                I2S_RCSR_REG(I2S0)
+#define I2S0_RCR1                                I2S_RCR1_REG(I2S0)
+#define I2S0_RCR2                                I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3                                I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4                                I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5                                I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0                                I2S_RDR_REG(I2S0,0)
+#define I2S0_RDR1                                I2S_RDR_REG(I2S0,1)
+#define I2S0_RFR0                                I2S_RFR_REG(I2S0,0)
+#define I2S0_RFR1                                I2S_RFR_REG(I2S0,1)
+#define I2S0_RMR                                 I2S_RMR_REG(I2S0)
+#define I2S0_MCR                                 I2S_MCR_REG(I2S0)
+#define I2S0_MDR                                 I2S_MDR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index)                          I2S_TDR_REG(I2S0,index)
+#define I2S0_TFR(index)                          I2S_TFR_REG(I2S0,index)
+#define I2S0_RDR(index)                          I2S_RDR_REG(I2S0,index)
+#define I2S0_RFR(index)                          I2S_RFR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
+  __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
+  __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
+  __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
+  __IO uint8_t RST;                                /**< LLWU Reset Enable register, offset: 0xA */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base)                       ((base)->PE1)
+#define LLWU_PE2_REG(base)                       ((base)->PE2)
+#define LLWU_PE3_REG(base)                       ((base)->PE3)
+#define LLWU_PE4_REG(base)                       ((base)->PE4)
+#define LLWU_ME_REG(base)                        ((base)->ME)
+#define LLWU_F1_REG(base)                        ((base)->F1)
+#define LLWU_F2_REG(base)                        ((base)->F2)
+#define LLWU_F3_REG(base)                        ((base)->F3)
+#define LLWU_FILT1_REG(base)                     ((base)->FILT1)
+#define LLWU_FILT2_REG(base)                     ((base)->FILT2)
+#define LLWU_RST_REG(base)                       ((base)->RST)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK                      0x3u
+#define LLWU_PE1_WUPE0_SHIFT                     0
+#define LLWU_PE1_WUPE0_WIDTH                     2
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      0xCu
+#define LLWU_PE1_WUPE1_SHIFT                     2
+#define LLWU_PE1_WUPE1_WIDTH                     2
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      0x30u
+#define LLWU_PE1_WUPE2_SHIFT                     4
+#define LLWU_PE1_WUPE2_WIDTH                     2
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      0xC0u
+#define LLWU_PE1_WUPE3_SHIFT                     6
+#define LLWU_PE1_WUPE3_WIDTH                     2
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK                      0x3u
+#define LLWU_PE2_WUPE4_SHIFT                     0
+#define LLWU_PE2_WUPE4_WIDTH                     2
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      0xCu
+#define LLWU_PE2_WUPE5_SHIFT                     2
+#define LLWU_PE2_WUPE5_WIDTH                     2
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      0x30u
+#define LLWU_PE2_WUPE6_SHIFT                     4
+#define LLWU_PE2_WUPE6_WIDTH                     2
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      0xC0u
+#define LLWU_PE2_WUPE7_SHIFT                     6
+#define LLWU_PE2_WUPE7_WIDTH                     2
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK                      0x3u
+#define LLWU_PE3_WUPE8_SHIFT                     0
+#define LLWU_PE3_WUPE8_WIDTH                     2
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      0xCu
+#define LLWU_PE3_WUPE9_SHIFT                     2
+#define LLWU_PE3_WUPE9_WIDTH                     2
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     0x30u
+#define LLWU_PE3_WUPE10_SHIFT                    4
+#define LLWU_PE3_WUPE10_WIDTH                    2
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     0xC0u
+#define LLWU_PE3_WUPE11_SHIFT                    6
+#define LLWU_PE3_WUPE11_WIDTH                    2
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK                     0x3u
+#define LLWU_PE4_WUPE12_SHIFT                    0
+#define LLWU_PE4_WUPE12_WIDTH                    2
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     0xCu
+#define LLWU_PE4_WUPE13_SHIFT                    2
+#define LLWU_PE4_WUPE13_WIDTH                    2
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     0x30u
+#define LLWU_PE4_WUPE14_SHIFT                    4
+#define LLWU_PE4_WUPE14_WIDTH                    2
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     0xC0u
+#define LLWU_PE4_WUPE15_SHIFT                    6
+#define LLWU_PE4_WUPE15_WIDTH                    2
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK                       0x1u
+#define LLWU_ME_WUME0_SHIFT                      0
+#define LLWU_ME_WUME0_WIDTH                      1
+#define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK                       0x2u
+#define LLWU_ME_WUME1_SHIFT                      1
+#define LLWU_ME_WUME1_WIDTH                      1
+#define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK                       0x4u
+#define LLWU_ME_WUME2_SHIFT                      2
+#define LLWU_ME_WUME2_WIDTH                      1
+#define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK                       0x8u
+#define LLWU_ME_WUME3_SHIFT                      3
+#define LLWU_ME_WUME3_WIDTH                      1
+#define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK                       0x10u
+#define LLWU_ME_WUME4_SHIFT                      4
+#define LLWU_ME_WUME4_WIDTH                      1
+#define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK                       0x20u
+#define LLWU_ME_WUME5_SHIFT                      5
+#define LLWU_ME_WUME5_WIDTH                      1
+#define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK                       0x40u
+#define LLWU_ME_WUME6_SHIFT                      6
+#define LLWU_ME_WUME6_WIDTH                      1
+#define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK                       0x80u
+#define LLWU_ME_WUME7_SHIFT                      7
+#define LLWU_ME_WUME7_WIDTH                      1
+#define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK                        0x1u
+#define LLWU_F1_WUF0_SHIFT                       0
+#define LLWU_F1_WUF0_WIDTH                       1
+#define LLWU_F1_WUF0(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF0_SHIFT))&LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK                        0x2u
+#define LLWU_F1_WUF1_SHIFT                       1
+#define LLWU_F1_WUF1_WIDTH                       1
+#define LLWU_F1_WUF1(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF1_SHIFT))&LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK                        0x4u
+#define LLWU_F1_WUF2_SHIFT                       2
+#define LLWU_F1_WUF2_WIDTH                       1
+#define LLWU_F1_WUF2(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF2_SHIFT))&LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK                        0x8u
+#define LLWU_F1_WUF3_SHIFT                       3
+#define LLWU_F1_WUF3_WIDTH                       1
+#define LLWU_F1_WUF3(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF3_SHIFT))&LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK                        0x10u
+#define LLWU_F1_WUF4_SHIFT                       4
+#define LLWU_F1_WUF4_WIDTH                       1
+#define LLWU_F1_WUF4(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF4_SHIFT))&LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK                        0x20u
+#define LLWU_F1_WUF5_SHIFT                       5
+#define LLWU_F1_WUF5_WIDTH                       1
+#define LLWU_F1_WUF5(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF5_SHIFT))&LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK                        0x40u
+#define LLWU_F1_WUF6_SHIFT                       6
+#define LLWU_F1_WUF6_WIDTH                       1
+#define LLWU_F1_WUF6(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF6_SHIFT))&LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK                        0x80u
+#define LLWU_F1_WUF7_SHIFT                       7
+#define LLWU_F1_WUF7_WIDTH                       1
+#define LLWU_F1_WUF7(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF7_SHIFT))&LLWU_F1_WUF7_MASK)
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK                        0x1u
+#define LLWU_F2_WUF8_SHIFT                       0
+#define LLWU_F2_WUF8_WIDTH                       1
+#define LLWU_F2_WUF8(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF8_SHIFT))&LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK                        0x2u
+#define LLWU_F2_WUF9_SHIFT                       1
+#define LLWU_F2_WUF9_WIDTH                       1
+#define LLWU_F2_WUF9(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF9_SHIFT))&LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK                       0x4u
+#define LLWU_F2_WUF10_SHIFT                      2
+#define LLWU_F2_WUF10_WIDTH                      1
+#define LLWU_F2_WUF10(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF10_SHIFT))&LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK                       0x8u
+#define LLWU_F2_WUF11_SHIFT                      3
+#define LLWU_F2_WUF11_WIDTH                      1
+#define LLWU_F2_WUF11(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF11_SHIFT))&LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK                       0x10u
+#define LLWU_F2_WUF12_SHIFT                      4
+#define LLWU_F2_WUF12_WIDTH                      1
+#define LLWU_F2_WUF12(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF12_SHIFT))&LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK                       0x20u
+#define LLWU_F2_WUF13_SHIFT                      5
+#define LLWU_F2_WUF13_WIDTH                      1
+#define LLWU_F2_WUF13(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF13_SHIFT))&LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK                       0x40u
+#define LLWU_F2_WUF14_SHIFT                      6
+#define LLWU_F2_WUF14_WIDTH                      1
+#define LLWU_F2_WUF14(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF14_SHIFT))&LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK                       0x80u
+#define LLWU_F2_WUF15_SHIFT                      7
+#define LLWU_F2_WUF15_WIDTH                      1
+#define LLWU_F2_WUF15(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF15_SHIFT))&LLWU_F2_WUF15_MASK)
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK                       0x1u
+#define LLWU_F3_MWUF0_SHIFT                      0
+#define LLWU_F3_MWUF0_WIDTH                      1
+#define LLWU_F3_MWUF0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF0_SHIFT))&LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK                       0x2u
+#define LLWU_F3_MWUF1_SHIFT                      1
+#define LLWU_F3_MWUF1_WIDTH                      1
+#define LLWU_F3_MWUF1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF1_SHIFT))&LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK                       0x4u
+#define LLWU_F3_MWUF2_SHIFT                      2
+#define LLWU_F3_MWUF2_WIDTH                      1
+#define LLWU_F3_MWUF2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF2_SHIFT))&LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK                       0x8u
+#define LLWU_F3_MWUF3_SHIFT                      3
+#define LLWU_F3_MWUF3_WIDTH                      1
+#define LLWU_F3_MWUF3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF3_SHIFT))&LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK                       0x10u
+#define LLWU_F3_MWUF4_SHIFT                      4
+#define LLWU_F3_MWUF4_WIDTH                      1
+#define LLWU_F3_MWUF4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF4_SHIFT))&LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK                       0x20u
+#define LLWU_F3_MWUF5_SHIFT                      5
+#define LLWU_F3_MWUF5_WIDTH                      1
+#define LLWU_F3_MWUF5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF5_SHIFT))&LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK                       0x40u
+#define LLWU_F3_MWUF6_SHIFT                      6
+#define LLWU_F3_MWUF6_WIDTH                      1
+#define LLWU_F3_MWUF6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF6_SHIFT))&LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK                       0x80u
+#define LLWU_F3_MWUF7_SHIFT                      7
+#define LLWU_F3_MWUF7_WIDTH                      1
+#define LLWU_F3_MWUF7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF7_SHIFT))&LLWU_F3_MWUF7_MASK)
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK                  0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT                 0
+#define LLWU_FILT1_FILTSEL_WIDTH                 4
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    0x60u
+#define LLWU_FILT1_FILTE_SHIFT                   5
+#define LLWU_FILT1_FILTE_WIDTH                   2
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK                    0x80u
+#define LLWU_FILT1_FILTF_SHIFT                   7
+#define LLWU_FILT1_FILTF_WIDTH                   1
+#define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK                  0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT                 0
+#define LLWU_FILT2_FILTSEL_WIDTH                 4
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    0x60u
+#define LLWU_FILT2_FILTE_SHIFT                   5
+#define LLWU_FILT2_FILTE_WIDTH                   2
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK                    0x80u
+#define LLWU_FILT2_FILTF_SHIFT                   7
+#define LLWU_FILT2_FILTF_WIDTH                   1
+#define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK                    0x1u
+#define LLWU_RST_RSTFILT_SHIFT                   0
+#define LLWU_RST_RSTFILT_WIDTH                   1
+#define LLWU_RST_RSTFILT(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_RST_RSTFILT_SHIFT))&LLWU_RST_RSTFILT_MASK)
+#define LLWU_RST_LLRSTE_MASK                     0x2u
+#define LLWU_RST_LLRSTE_SHIFT                    1
+#define LLWU_RST_LLRSTE_WIDTH                    1
+#define LLWU_RST_LLRSTE(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_RST_LLRSTE_SHIFT))&LLWU_RST_LLRSTE_MASK)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR                            (LLWU)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1                                 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2                                 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3                                 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4                                 LLWU_PE4_REG(LLWU)
+#define LLWU_ME                                  LLWU_ME_REG(LLWU)
+#define LLWU_F1                                  LLWU_F1_REG(LLWU)
+#define LLWU_F2                                  LLWU_F2_REG(LLWU)
+#define LLWU_F3                                  LLWU_F3_REG(LLWU)
+#define LLWU_FILT1                               LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2                               LLWU_FILT2_REG(LLWU)
+#define LLWU_RST                                 LLWU_RST_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base)                      ((base)->CSR)
+#define LPTMR_PSR_REG(base)                      ((base)->PSR)
+#define LPTMR_CMR_REG(base)                      ((base)->CMR)
+#define LPTMR_CNR_REG(base)                      ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK                       0x1u
+#define LPTMR_CSR_TEN_SHIFT                      0
+#define LPTMR_CSR_TEN_WIDTH                      1
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK                       0x2u
+#define LPTMR_CSR_TMS_SHIFT                      1
+#define LPTMR_CSR_TMS_WIDTH                      1
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK                       0x4u
+#define LPTMR_CSR_TFC_SHIFT                      2
+#define LPTMR_CSR_TFC_WIDTH                      1
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK                       0x8u
+#define LPTMR_CSR_TPP_SHIFT                      3
+#define LPTMR_CSR_TPP_WIDTH                      1
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK                       0x30u
+#define LPTMR_CSR_TPS_SHIFT                      4
+#define LPTMR_CSR_TPS_WIDTH                      2
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       0x40u
+#define LPTMR_CSR_TIE_SHIFT                      6
+#define LPTMR_CSR_TIE_WIDTH                      1
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK                       0x80u
+#define LPTMR_CSR_TCF_SHIFT                      7
+#define LPTMR_CSR_TCF_WIDTH                      1
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK                       0x3u
+#define LPTMR_PSR_PCS_SHIFT                      0
+#define LPTMR_PSR_PCS_WIDTH                      2
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      0x4u
+#define LPTMR_PSR_PBYP_SHIFT                     2
+#define LPTMR_PSR_PBYP_WIDTH                     1
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK                  0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT                 3
+#define LPTMR_PSR_PRESCALE_WIDTH                 4
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT                  0
+#define LPTMR_CMR_COMPARE_WIDTH                  16
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT                  0
+#define LPTMR_CNR_COUNTER_WIDTH                  16
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR                          (LPTMR0)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR                               LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR                               LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR                               LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR                               LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
+  __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
+  __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
+  __IO uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+  __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+  __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
+  __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base)                         ((base)->C1)
+#define MCG_C2_REG(base)                         ((base)->C2)
+#define MCG_C3_REG(base)                         ((base)->C3)
+#define MCG_C4_REG(base)                         ((base)->C4)
+#define MCG_C5_REG(base)                         ((base)->C5)
+#define MCG_C6_REG(base)                         ((base)->C6)
+#define MCG_S_REG(base)                          ((base)->S)
+#define MCG_SC_REG(base)                         ((base)->SC)
+#define MCG_ATCVH_REG(base)                      ((base)->ATCVH)
+#define MCG_ATCVL_REG(base)                      ((base)->ATCVL)
+#define MCG_C7_REG(base)                         ((base)->C7)
+#define MCG_C8_REG(base)                         ((base)->C8)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK                     0x1u
+#define MCG_C1_IREFSTEN_SHIFT                    0
+#define MCG_C1_IREFSTEN_WIDTH                    1
+#define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK                      0x2u
+#define MCG_C1_IRCLKEN_SHIFT                     1
+#define MCG_C1_IRCLKEN_WIDTH                     1
+#define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK                        0x4u
+#define MCG_C1_IREFS_SHIFT                       2
+#define MCG_C1_IREFS_WIDTH                       1
+#define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFS_SHIFT))&MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK                        0x38u
+#define MCG_C1_FRDIV_SHIFT                       3
+#define MCG_C1_FRDIV_WIDTH                       3
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         0xC0u
+#define MCG_C1_CLKS_SHIFT                        6
+#define MCG_C1_CLKS_WIDTH                        2
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK                         0x1u
+#define MCG_C2_IRCS_SHIFT                        0
+#define MCG_C2_IRCS_WIDTH                        1
+#define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK                           0x2u
+#define MCG_C2_LP_SHIFT                          1
+#define MCG_C2_LP_WIDTH                          1
+#define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x))<<MCG_C2_LP_SHIFT))&MCG_C2_LP_MASK)
+#define MCG_C2_EREFS_MASK                        0x4u
+#define MCG_C2_EREFS_SHIFT                       2
+#define MCG_C2_EREFS_WIDTH                       1
+#define MCG_C2_EREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS_SHIFT))&MCG_C2_EREFS_MASK)
+#define MCG_C2_HGO_MASK                          0x8u
+#define MCG_C2_HGO_SHIFT                         3
+#define MCG_C2_HGO_WIDTH                         1
+#define MCG_C2_HGO(x)                            (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO_SHIFT))&MCG_C2_HGO_MASK)
+#define MCG_C2_RANGE_MASK                        0x30u
+#define MCG_C2_RANGE_SHIFT                       4
+#define MCG_C2_RANGE_WIDTH                       2
+#define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK                      0x40u
+#define MCG_C2_FCFTRIM_SHIFT                     6
+#define MCG_C2_FCFTRIM_WIDTH                     1
+#define MCG_C2_FCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C2_FCFTRIM_SHIFT))&MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK                       0x80u
+#define MCG_C2_LOCRE0_SHIFT                      7
+#define MCG_C2_LOCRE0_WIDTH                      1
+#define MCG_C2_LOCRE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_LOCRE0_SHIFT))&MCG_C2_LOCRE0_MASK)
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK                       0xFFu
+#define MCG_C3_SCTRIM_SHIFT                      0
+#define MCG_C3_SCTRIM_WIDTH                      8
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK                      0x1u
+#define MCG_C4_SCFTRIM_SHIFT                     0
+#define MCG_C4_SCFTRIM_WIDTH                     1
+#define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C4_SCFTRIM_SHIFT))&MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK                       0x1Eu
+#define MCG_C4_FCTRIM_SHIFT                      1
+#define MCG_C4_FCTRIM_WIDTH                      4
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     0x60u
+#define MCG_C4_DRST_DRS_SHIFT                    5
+#define MCG_C4_DRST_DRS_WIDTH                    2
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK                        0x80u
+#define MCG_C4_DMX32_SHIFT                       7
+#define MCG_C4_DMX32_WIDTH                       1
+#define MCG_C4_DMX32(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C4_DMX32_SHIFT))&MCG_C4_DMX32_MASK)
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK                       0x1Fu
+#define MCG_C5_PRDIV0_SHIFT                      0
+#define MCG_C5_PRDIV0_WIDTH                      5
+#define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK                     0x20u
+#define MCG_C5_PLLSTEN0_SHIFT                    5
+#define MCG_C5_PLLSTEN0_WIDTH                    1
+#define MCG_C5_PLLSTEN0(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLSTEN0_SHIFT))&MCG_C5_PLLSTEN0_MASK)
+#define MCG_C5_PLLCLKEN0_MASK                    0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT                   6
+#define MCG_C5_PLLCLKEN0_WIDTH                   1
+#define MCG_C5_PLLCLKEN0(x)                      (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLCLKEN0_SHIFT))&MCG_C5_PLLCLKEN0_MASK)
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK                        0x1Fu
+#define MCG_C6_VDIV0_SHIFT                       0
+#define MCG_C6_VDIV0_WIDTH                       5
+#define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK                         0x20u
+#define MCG_C6_CME0_SHIFT                        5
+#define MCG_C6_CME0_WIDTH                        1
+#define MCG_C6_CME0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_CME0_SHIFT))&MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK                         0x40u
+#define MCG_C6_PLLS_SHIFT                        6
+#define MCG_C6_PLLS_WIDTH                        1
+#define MCG_C6_PLLS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_PLLS_SHIFT))&MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK                       0x80u
+#define MCG_C6_LOLIE0_SHIFT                      7
+#define MCG_C6_LOLIE0_WIDTH                      1
+#define MCG_C6_LOLIE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C6_LOLIE0_SHIFT))&MCG_C6_LOLIE0_MASK)
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK                         0x1u
+#define MCG_S_IRCST_SHIFT                        0
+#define MCG_S_IRCST_WIDTH                        1
+#define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_IRCST_SHIFT))&MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK                      0x2u
+#define MCG_S_OSCINIT0_SHIFT                     1
+#define MCG_S_OSCINIT0_WIDTH                     1
+#define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK                         0xCu
+#define MCG_S_CLKST_SHIFT                        2
+#define MCG_S_CLKST_WIDTH                        2
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK                        0x10u
+#define MCG_S_IREFST_SHIFT                       4
+#define MCG_S_IREFST_WIDTH                       1
+#define MCG_S_IREFST(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_S_IREFST_SHIFT))&MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK                         0x20u
+#define MCG_S_PLLST_SHIFT                        5
+#define MCG_S_PLLST_WIDTH                        1
+#define MCG_S_PLLST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_PLLST_SHIFT))&MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK                         0x40u
+#define MCG_S_LOCK0_SHIFT                        6
+#define MCG_S_LOCK0_WIDTH                        1
+#define MCG_S_LOCK0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOCK0_SHIFT))&MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK                         0x80u
+#define MCG_S_LOLS0_SHIFT                        7
+#define MCG_S_LOLS0_WIDTH                        1
+#define MCG_S_LOLS0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOLS0_SHIFT))&MCG_S_LOLS0_MASK)
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK                        0x1u
+#define MCG_SC_LOCS0_SHIFT                       0
+#define MCG_SC_LOCS0_WIDTH                       1
+#define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_SC_LOCS0_SHIFT))&MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK                       0xEu
+#define MCG_SC_FCRDIV_SHIFT                      1
+#define MCG_SC_FCRDIV_WIDTH                      3
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK                     0x10u
+#define MCG_SC_FLTPRSRV_SHIFT                    4
+#define MCG_SC_FLTPRSRV_WIDTH                    1
+#define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_SC_FLTPRSRV_SHIFT))&MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK                         0x20u
+#define MCG_SC_ATMF_SHIFT                        5
+#define MCG_SC_ATMF_WIDTH                        1
+#define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMF_SHIFT))&MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK                         0x40u
+#define MCG_SC_ATMS_SHIFT                        6
+#define MCG_SC_ATMS_WIDTH                        1
+#define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMS_SHIFT))&MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK                         0x80u
+#define MCG_SC_ATME_SHIFT                        7
+#define MCG_SC_ATME_WIDTH                        1
+#define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATME_SHIFT))&MCG_SC_ATME_MASK)
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK                     0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT                    0
+#define MCG_ATCVH_ATCVH_WIDTH                    8
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK                     0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT                    0
+#define MCG_ATCVL_ATCVL_WIDTH                    8
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK                       0x3u
+#define MCG_C7_OSCSEL_SHIFT                      0
+#define MCG_C7_OSCSEL_WIDTH                      2
+#define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK                        0x1u
+#define MCG_C8_LOCS1_SHIFT                       0
+#define MCG_C8_LOCS1_WIDTH                       1
+#define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCS1_SHIFT))&MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK                         0x20u
+#define MCG_C8_CME1_SHIFT                        5
+#define MCG_C8_CME1_WIDTH                        1
+#define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C8_CME1_SHIFT))&MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK                        0x40u
+#define MCG_C8_LOLRE_SHIFT                       6
+#define MCG_C8_LOLRE_WIDTH                       1
+#define MCG_C8_LOLRE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOLRE_SHIFT))&MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK                       0x80u
+#define MCG_C8_LOCRE1_SHIFT                      7
+#define MCG_C8_LOCRE1_WIDTH                      1
+#define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCRE1_SHIFT))&MCG_C8_LOCRE1_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR                             (MCG)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS                           { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS                            { MCG }
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1                                   MCG_C1_REG(MCG)
+#define MCG_C2                                   MCG_C2_REG(MCG)
+#define MCG_C3                                   MCG_C3_REG(MCG)
+#define MCG_C4                                   MCG_C4_REG(MCG)
+#define MCG_C5                                   MCG_C5_REG(MCG)
+#define MCG_C6                                   MCG_C6_REG(MCG)
+#define MCG_S                                    MCG_S_REG(MCG)
+#define MCG_SC                                   MCG_SC_REG(MCG)
+#define MCG_ATCVH                                MCG_ATCVH_REG(MCG)
+#define MCG_ATCVL                                MCG_ATCVL_REG(MCG)
+#define MCG_C7                                   MCG_C7_REG(MCG)
+#define MCG_C8                                   MCG_C8_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t CR;                                /**< Control Register, offset: 0xC */
+  __IO uint32_t ISCR;                              /**< Interrupt Status Register, offset: 0x10 */
+  __IO uint32_t ETBCC;                             /**< ETB Counter Control register, offset: 0x14 */
+  __IO uint32_t ETBRL;                             /**< ETB Reload register, offset: 0x18 */
+  __I  uint32_t ETBCNT;                            /**< ETB Counter Value register, offset: 0x1C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PID;                               /**< Process ID register, offset: 0x30 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base)                      ((base)->PLASC)
+#define MCM_PLAMC_REG(base)                      ((base)->PLAMC)
+#define MCM_CR_REG(base)                         ((base)->CR)
+#define MCM_ISCR_REG(base)                       ((base)->ISCR)
+#define MCM_ETBCC_REG(base)                      ((base)->ETBCC)
+#define MCM_ETBRL_REG(base)                      ((base)->ETBRL)
+#define MCM_ETBCNT_REG(base)                     ((base)->ETBCNT)
+#define MCM_PID_REG(base)                        ((base)->PID)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK                       0xFFu
+#define MCM_PLASC_ASC_SHIFT                      0
+#define MCM_PLASC_ASC_WIDTH                      8
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK                       0xFFu
+#define MCM_PLAMC_AMC_SHIFT                      0
+#define MCM_PLAMC_AMC_WIDTH                      8
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* CR Bit Fields */
+#define MCM_CR_SRAMUAP_MASK                      0x3000000u
+#define MCM_CR_SRAMUAP_SHIFT                     24
+#define MCM_CR_SRAMUAP_WIDTH                     2
+#define MCM_CR_SRAMUAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP_MASK                      0x4000000u
+#define MCM_CR_SRAMUWP_SHIFT                     26
+#define MCM_CR_SRAMUWP_WIDTH                     1
+#define MCM_CR_SRAMUWP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUWP_SHIFT))&MCM_CR_SRAMUWP_MASK)
+#define MCM_CR_SRAMLAP_MASK                      0x30000000u
+#define MCM_CR_SRAMLAP_SHIFT                     28
+#define MCM_CR_SRAMLAP_WIDTH                     2
+#define MCM_CR_SRAMLAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP_MASK                      0x40000000u
+#define MCM_CR_SRAMLWP_SHIFT                     30
+#define MCM_CR_SRAMLWP_WIDTH                     1
+#define MCM_CR_SRAMLWP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLWP_SHIFT))&MCM_CR_SRAMLWP_MASK)
+/* ISCR Bit Fields */
+#define MCM_ISCR_IRQ_MASK                        0x2u
+#define MCM_ISCR_IRQ_SHIFT                       1
+#define MCM_ISCR_IRQ_WIDTH                       1
+#define MCM_ISCR_IRQ(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_IRQ_SHIFT))&MCM_ISCR_IRQ_MASK)
+#define MCM_ISCR_NMI_MASK                        0x4u
+#define MCM_ISCR_NMI_SHIFT                       2
+#define MCM_ISCR_NMI_WIDTH                       1
+#define MCM_ISCR_NMI(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_NMI_SHIFT))&MCM_ISCR_NMI_MASK)
+#define MCM_ISCR_DHREQ_MASK                      0x8u
+#define MCM_ISCR_DHREQ_SHIFT                     3
+#define MCM_ISCR_DHREQ_WIDTH                     1
+#define MCM_ISCR_DHREQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_DHREQ_SHIFT))&MCM_ISCR_DHREQ_MASK)
+#define MCM_ISCR_FIOC_MASK                       0x100u
+#define MCM_ISCR_FIOC_SHIFT                      8
+#define MCM_ISCR_FIOC_WIDTH                      1
+#define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FDZC_MASK                       0x200u
+#define MCM_ISCR_FDZC_SHIFT                      9
+#define MCM_ISCR_FDZC_WIDTH                      1
+#define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FOFC_MASK                       0x400u
+#define MCM_ISCR_FOFC_SHIFT                      10
+#define MCM_ISCR_FOFC_WIDTH                      1
+#define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FUFC_MASK                       0x800u
+#define MCM_ISCR_FUFC_SHIFT                      11
+#define MCM_ISCR_FUFC_WIDTH                      1
+#define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FIXC_MASK                       0x1000u
+#define MCM_ISCR_FIXC_SHIFT                      12
+#define MCM_ISCR_FIXC_WIDTH                      1
+#define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIDC_MASK                       0x8000u
+#define MCM_ISCR_FIDC_SHIFT                      15
+#define MCM_ISCR_FIDC_WIDTH                      1
+#define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIOCE_MASK                      0x1000000u
+#define MCM_ISCR_FIOCE_SHIFT                     24
+#define MCM_ISCR_FIOCE_WIDTH                     1
+#define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FDZCE_MASK                      0x2000000u
+#define MCM_ISCR_FDZCE_SHIFT                     25
+#define MCM_ISCR_FDZCE_WIDTH                     1
+#define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FOFCE_MASK                      0x4000000u
+#define MCM_ISCR_FOFCE_SHIFT                     26
+#define MCM_ISCR_FOFCE_WIDTH                     1
+#define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FUFCE_MASK                      0x8000000u
+#define MCM_ISCR_FUFCE_SHIFT                     27
+#define MCM_ISCR_FUFCE_WIDTH                     1
+#define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FIXCE_MASK                      0x10000000u
+#define MCM_ISCR_FIXCE_SHIFT                     28
+#define MCM_ISCR_FIXCE_WIDTH                     1
+#define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIDCE_MASK                      0x80000000u
+#define MCM_ISCR_FIDCE_SHIFT                     31
+#define MCM_ISCR_FIDCE_WIDTH                     1
+#define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
+/* ETBCC Bit Fields */
+#define MCM_ETBCC_CNTEN_MASK                     0x1u
+#define MCM_ETBCC_CNTEN_SHIFT                    0
+#define MCM_ETBCC_CNTEN_WIDTH                    1
+#define MCM_ETBCC_CNTEN(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_CNTEN_SHIFT))&MCM_ETBCC_CNTEN_MASK)
+#define MCM_ETBCC_RSPT_MASK                      0x6u
+#define MCM_ETBCC_RSPT_SHIFT                     1
+#define MCM_ETBCC_RSPT_WIDTH                     2
+#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK                      0x8u
+#define MCM_ETBCC_RLRQ_SHIFT                     3
+#define MCM_ETBCC_RLRQ_WIDTH                     1
+#define MCM_ETBCC_RLRQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RLRQ_SHIFT))&MCM_ETBCC_RLRQ_MASK)
+#define MCM_ETBCC_ETDIS_MASK                     0x10u
+#define MCM_ETBCC_ETDIS_SHIFT                    4
+#define MCM_ETBCC_ETDIS_WIDTH                    1
+#define MCM_ETBCC_ETDIS(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ETDIS_SHIFT))&MCM_ETBCC_ETDIS_MASK)
+#define MCM_ETBCC_ITDIS_MASK                     0x20u
+#define MCM_ETBCC_ITDIS_SHIFT                    5
+#define MCM_ETBCC_ITDIS_WIDTH                    1
+#define MCM_ETBCC_ITDIS(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ITDIS_SHIFT))&MCM_ETBCC_ITDIS_MASK)
+/* ETBRL Bit Fields */
+#define MCM_ETBRL_RELOAD_MASK                    0x7FFu
+#define MCM_ETBRL_RELOAD_SHIFT                   0
+#define MCM_ETBRL_RELOAD_WIDTH                   11
+#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
+/* ETBCNT Bit Fields */
+#define MCM_ETBCNT_COUNTER_MASK                  0x7FFu
+#define MCM_ETBCNT_COUNTER_SHIFT                 0
+#define MCM_ETBCNT_COUNTER_WIDTH                 11
+#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
+/* PID Bit Fields */
+#define MCM_PID_PID_MASK                         0xFFu
+#define MCM_PID_PID_SHIFT                        0
+#define MCM_PID_PID_WIDTH                        8
+#define MCM_PID_PID(x)                           (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR                             (MCM)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { MCM }
+/** Interrupt vectors for the MCM peripheral type */
+#define MCM_IRQS                                 { MCM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC                                MCM_PLASC_REG(MCM)
+#define MCM_PLAMC                                MCM_PLAMC_REG(MCM)
+#define MCM_CR                                   MCM_CR_REG(MCM)
+#define MCM_ISCR                                 MCM_ISCR_REG(MCM)
+#define MCM_ETBCC                                MCM_ETBCC_REG(MCM)
+#define MCM_ETBRL                                MCM_ETBRL_REG(MCM)
+#define MCM_ETBCNT                               MCM_ETBCNT_REG(MCM)
+#define MCM_PID                                  MCM_PID_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
+ * @{
+ */
+
+/** MPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} MPU_Type, *MPU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register accessors */
+#define MPU_CESR_REG(base)                       ((base)->CESR)
+#define MPU_EAR_REG(base,index)                  ((base)->SP[index].EAR)
+#define MPU_EAR_COUNT                            5
+#define MPU_EDR_REG(base,index)                  ((base)->SP[index].EDR)
+#define MPU_EDR_COUNT                            5
+#define MPU_WORD_REG(base,index,index2)          ((base)->WORD[index][index2])
+#define MPU_WORD_COUNT                           12
+#define MPU_WORD_COUNT2                          4
+#define MPU_RGDAAC_REG(base,index)               ((base)->RGDAAC[index])
+#define MPU_RGDAAC_COUNT                         12
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Masks MPU Register Masks
+ * @{
+ */
+
+/* CESR Bit Fields */
+#define MPU_CESR_VLD_MASK                        0x1u
+#define MPU_CESR_VLD_SHIFT                       0
+#define MPU_CESR_VLD_WIDTH                       1
+#define MPU_CESR_VLD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_VLD_SHIFT))&MPU_CESR_VLD_MASK)
+#define MPU_CESR_NRGD_MASK                       0xF00u
+#define MPU_CESR_NRGD_SHIFT                      8
+#define MPU_CESR_NRGD_WIDTH                      4
+#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
+#define MPU_CESR_NSP_MASK                        0xF000u
+#define MPU_CESR_NSP_SHIFT                       12
+#define MPU_CESR_NSP_WIDTH                       4
+#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
+#define MPU_CESR_HRL_MASK                        0xF0000u
+#define MPU_CESR_HRL_SHIFT                       16
+#define MPU_CESR_HRL_WIDTH                       4
+#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
+#define MPU_CESR_SPERR_MASK                      0xF8000000u
+#define MPU_CESR_SPERR_SHIFT                     27
+#define MPU_CESR_SPERR_WIDTH                     5
+#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
+/* EAR Bit Fields */
+#define MPU_EAR_EADDR_MASK                       0xFFFFFFFFu
+#define MPU_EAR_EADDR_SHIFT                      0
+#define MPU_EAR_EADDR_WIDTH                      32
+#define MPU_EAR_EADDR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
+/* EDR Bit Fields */
+#define MPU_EDR_ERW_MASK                         0x1u
+#define MPU_EDR_ERW_SHIFT                        0
+#define MPU_EDR_ERW_WIDTH                        1
+#define MPU_EDR_ERW(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_ERW_SHIFT))&MPU_EDR_ERW_MASK)
+#define MPU_EDR_EATTR_MASK                       0xEu
+#define MPU_EDR_EATTR_SHIFT                      1
+#define MPU_EDR_EATTR_WIDTH                      3
+#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
+#define MPU_EDR_EMN_MASK                         0xF0u
+#define MPU_EDR_EMN_SHIFT                        4
+#define MPU_EDR_EMN_WIDTH                        4
+#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
+#define MPU_EDR_EPID_MASK                        0xFF00u
+#define MPU_EDR_EPID_SHIFT                       8
+#define MPU_EDR_EPID_WIDTH                       8
+#define MPU_EDR_EPID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
+#define MPU_EDR_EACD_MASK                        0xFFFF0000u
+#define MPU_EDR_EACD_SHIFT                       16
+#define MPU_EDR_EACD_WIDTH                       16
+#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
+/* WORD Bit Fields */
+#define MPU_WORD_VLD_MASK                        0x1u
+#define MPU_WORD_VLD_SHIFT                       0
+#define MPU_WORD_VLD_WIDTH                       1
+#define MPU_WORD_VLD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_VLD_SHIFT))&MPU_WORD_VLD_MASK)
+#define MPU_WORD_M0UM_MASK                       0x7u
+#define MPU_WORD_M0UM_SHIFT                      0
+#define MPU_WORD_M0UM_WIDTH                      3
+#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
+#define MPU_WORD_M0SM_MASK                       0x18u
+#define MPU_WORD_M0SM_SHIFT                      3
+#define MPU_WORD_M0SM_WIDTH                      2
+#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
+#define MPU_WORD_M0PE_MASK                       0x20u
+#define MPU_WORD_M0PE_SHIFT                      5
+#define MPU_WORD_M0PE_WIDTH                      1
+#define MPU_WORD_M0PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0PE_SHIFT))&MPU_WORD_M0PE_MASK)
+#define MPU_WORD_ENDADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_ENDADDR_SHIFT                   5
+#define MPU_WORD_ENDADDR_WIDTH                   27
+#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
+#define MPU_WORD_SRTADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_SRTADDR_SHIFT                   5
+#define MPU_WORD_SRTADDR_WIDTH                   27
+#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
+#define MPU_WORD_M1UM_MASK                       0x1C0u
+#define MPU_WORD_M1UM_SHIFT                      6
+#define MPU_WORD_M1UM_WIDTH                      3
+#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
+#define MPU_WORD_M1SM_MASK                       0x600u
+#define MPU_WORD_M1SM_SHIFT                      9
+#define MPU_WORD_M1SM_WIDTH                      2
+#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
+#define MPU_WORD_M1PE_MASK                       0x800u
+#define MPU_WORD_M1PE_SHIFT                      11
+#define MPU_WORD_M1PE_WIDTH                      1
+#define MPU_WORD_M1PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1PE_SHIFT))&MPU_WORD_M1PE_MASK)
+#define MPU_WORD_M2UM_MASK                       0x7000u
+#define MPU_WORD_M2UM_SHIFT                      12
+#define MPU_WORD_M2UM_WIDTH                      3
+#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
+#define MPU_WORD_M2SM_MASK                       0x18000u
+#define MPU_WORD_M2SM_SHIFT                      15
+#define MPU_WORD_M2SM_WIDTH                      2
+#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
+#define MPU_WORD_PIDMASK_MASK                    0xFF0000u
+#define MPU_WORD_PIDMASK_SHIFT                   16
+#define MPU_WORD_PIDMASK_WIDTH                   8
+#define MPU_WORD_PIDMASK(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
+#define MPU_WORD_M2PE_MASK                       0x20000u
+#define MPU_WORD_M2PE_SHIFT                      17
+#define MPU_WORD_M2PE_WIDTH                      1
+#define MPU_WORD_M2PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2PE_SHIFT))&MPU_WORD_M2PE_MASK)
+#define MPU_WORD_M3UM_MASK                       0x1C0000u
+#define MPU_WORD_M3UM_SHIFT                      18
+#define MPU_WORD_M3UM_WIDTH                      3
+#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
+#define MPU_WORD_M3SM_MASK                       0x600000u
+#define MPU_WORD_M3SM_SHIFT                      21
+#define MPU_WORD_M3SM_WIDTH                      2
+#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
+#define MPU_WORD_M3PE_MASK                       0x800000u
+#define MPU_WORD_M3PE_SHIFT                      23
+#define MPU_WORD_M3PE_WIDTH                      1
+#define MPU_WORD_M3PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3PE_SHIFT))&MPU_WORD_M3PE_MASK)
+#define MPU_WORD_PID_MASK                        0xFF000000u
+#define MPU_WORD_PID_SHIFT                       24
+#define MPU_WORD_PID_WIDTH                       8
+#define MPU_WORD_PID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
+#define MPU_WORD_M4WE_MASK                       0x1000000u
+#define MPU_WORD_M4WE_SHIFT                      24
+#define MPU_WORD_M4WE_WIDTH                      1
+#define MPU_WORD_M4WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4WE_SHIFT))&MPU_WORD_M4WE_MASK)
+#define MPU_WORD_M4RE_MASK                       0x2000000u
+#define MPU_WORD_M4RE_SHIFT                      25
+#define MPU_WORD_M4RE_WIDTH                      1
+#define MPU_WORD_M4RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4RE_SHIFT))&MPU_WORD_M4RE_MASK)
+#define MPU_WORD_M5WE_MASK                       0x4000000u
+#define MPU_WORD_M5WE_SHIFT                      26
+#define MPU_WORD_M5WE_WIDTH                      1
+#define MPU_WORD_M5WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5WE_SHIFT))&MPU_WORD_M5WE_MASK)
+#define MPU_WORD_M5RE_MASK                       0x8000000u
+#define MPU_WORD_M5RE_SHIFT                      27
+#define MPU_WORD_M5RE_WIDTH                      1
+#define MPU_WORD_M5RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5RE_SHIFT))&MPU_WORD_M5RE_MASK)
+#define MPU_WORD_M6WE_MASK                       0x10000000u
+#define MPU_WORD_M6WE_SHIFT                      28
+#define MPU_WORD_M6WE_WIDTH                      1
+#define MPU_WORD_M6WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6WE_SHIFT))&MPU_WORD_M6WE_MASK)
+#define MPU_WORD_M6RE_MASK                       0x20000000u
+#define MPU_WORD_M6RE_SHIFT                      29
+#define MPU_WORD_M6RE_WIDTH                      1
+#define MPU_WORD_M6RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6RE_SHIFT))&MPU_WORD_M6RE_MASK)
+#define MPU_WORD_M7WE_MASK                       0x40000000u
+#define MPU_WORD_M7WE_SHIFT                      30
+#define MPU_WORD_M7WE_WIDTH                      1
+#define MPU_WORD_M7WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7WE_SHIFT))&MPU_WORD_M7WE_MASK)
+#define MPU_WORD_M7RE_MASK                       0x80000000u
+#define MPU_WORD_M7RE_SHIFT                      31
+#define MPU_WORD_M7RE_WIDTH                      1
+#define MPU_WORD_M7RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7RE_SHIFT))&MPU_WORD_M7RE_MASK)
+/* RGDAAC Bit Fields */
+#define MPU_RGDAAC_M0UM_MASK                     0x7u
+#define MPU_RGDAAC_M0UM_SHIFT                    0
+#define MPU_RGDAAC_M0UM_WIDTH                    3
+#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
+#define MPU_RGDAAC_M0SM_MASK                     0x18u
+#define MPU_RGDAAC_M0SM_SHIFT                    3
+#define MPU_RGDAAC_M0SM_WIDTH                    2
+#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
+#define MPU_RGDAAC_M0PE_MASK                     0x20u
+#define MPU_RGDAAC_M0PE_SHIFT                    5
+#define MPU_RGDAAC_M0PE_WIDTH                    1
+#define MPU_RGDAAC_M0PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0PE_SHIFT))&MPU_RGDAAC_M0PE_MASK)
+#define MPU_RGDAAC_M1UM_MASK                     0x1C0u
+#define MPU_RGDAAC_M1UM_SHIFT                    6
+#define MPU_RGDAAC_M1UM_WIDTH                    3
+#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
+#define MPU_RGDAAC_M1SM_MASK                     0x600u
+#define MPU_RGDAAC_M1SM_SHIFT                    9
+#define MPU_RGDAAC_M1SM_WIDTH                    2
+#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
+#define MPU_RGDAAC_M1PE_MASK                     0x800u
+#define MPU_RGDAAC_M1PE_SHIFT                    11
+#define MPU_RGDAAC_M1PE_WIDTH                    1
+#define MPU_RGDAAC_M1PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1PE_SHIFT))&MPU_RGDAAC_M1PE_MASK)
+#define MPU_RGDAAC_M2UM_MASK                     0x7000u
+#define MPU_RGDAAC_M2UM_SHIFT                    12
+#define MPU_RGDAAC_M2UM_WIDTH                    3
+#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
+#define MPU_RGDAAC_M2SM_MASK                     0x18000u
+#define MPU_RGDAAC_M2SM_SHIFT                    15
+#define MPU_RGDAAC_M2SM_WIDTH                    2
+#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
+#define MPU_RGDAAC_M2PE_MASK                     0x20000u
+#define MPU_RGDAAC_M2PE_SHIFT                    17
+#define MPU_RGDAAC_M2PE_WIDTH                    1
+#define MPU_RGDAAC_M2PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2PE_SHIFT))&MPU_RGDAAC_M2PE_MASK)
+#define MPU_RGDAAC_M3UM_MASK                     0x1C0000u
+#define MPU_RGDAAC_M3UM_SHIFT                    18
+#define MPU_RGDAAC_M3UM_WIDTH                    3
+#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
+#define MPU_RGDAAC_M3SM_MASK                     0x600000u
+#define MPU_RGDAAC_M3SM_SHIFT                    21
+#define MPU_RGDAAC_M3SM_WIDTH                    2
+#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
+#define MPU_RGDAAC_M3PE_MASK                     0x800000u
+#define MPU_RGDAAC_M3PE_SHIFT                    23
+#define MPU_RGDAAC_M3PE_WIDTH                    1
+#define MPU_RGDAAC_M3PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3PE_SHIFT))&MPU_RGDAAC_M3PE_MASK)
+#define MPU_RGDAAC_M4WE_MASK                     0x1000000u
+#define MPU_RGDAAC_M4WE_SHIFT                    24
+#define MPU_RGDAAC_M4WE_WIDTH                    1
+#define MPU_RGDAAC_M4WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4WE_SHIFT))&MPU_RGDAAC_M4WE_MASK)
+#define MPU_RGDAAC_M4RE_MASK                     0x2000000u
+#define MPU_RGDAAC_M4RE_SHIFT                    25
+#define MPU_RGDAAC_M4RE_WIDTH                    1
+#define MPU_RGDAAC_M4RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4RE_SHIFT))&MPU_RGDAAC_M4RE_MASK)
+#define MPU_RGDAAC_M5WE_MASK                     0x4000000u
+#define MPU_RGDAAC_M5WE_SHIFT                    26
+#define MPU_RGDAAC_M5WE_WIDTH                    1
+#define MPU_RGDAAC_M5WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5WE_SHIFT))&MPU_RGDAAC_M5WE_MASK)
+#define MPU_RGDAAC_M5RE_MASK                     0x8000000u
+#define MPU_RGDAAC_M5RE_SHIFT                    27
+#define MPU_RGDAAC_M5RE_WIDTH                    1
+#define MPU_RGDAAC_M5RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5RE_SHIFT))&MPU_RGDAAC_M5RE_MASK)
+#define MPU_RGDAAC_M6WE_MASK                     0x10000000u
+#define MPU_RGDAAC_M6WE_SHIFT                    28
+#define MPU_RGDAAC_M6WE_WIDTH                    1
+#define MPU_RGDAAC_M6WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6WE_SHIFT))&MPU_RGDAAC_M6WE_MASK)
+#define MPU_RGDAAC_M6RE_MASK                     0x20000000u
+#define MPU_RGDAAC_M6RE_SHIFT                    29
+#define MPU_RGDAAC_M6RE_WIDTH                    1
+#define MPU_RGDAAC_M6RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6RE_SHIFT))&MPU_RGDAAC_M6RE_MASK)
+#define MPU_RGDAAC_M7WE_MASK                     0x40000000u
+#define MPU_RGDAAC_M7WE_SHIFT                    30
+#define MPU_RGDAAC_M7WE_WIDTH                    1
+#define MPU_RGDAAC_M7WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7WE_SHIFT))&MPU_RGDAAC_M7WE_MASK)
+#define MPU_RGDAAC_M7RE_MASK                     0x80000000u
+#define MPU_RGDAAC_M7RE_SHIFT                    31
+#define MPU_RGDAAC_M7RE_WIDTH                    1
+#define MPU_RGDAAC_M7RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7RE_SHIFT))&MPU_RGDAAC_M7RE_MASK)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Masks */
+
+
+/* MPU - Peripheral instance base addresses */
+/** Peripheral MPU base address */
+#define MPU_BASE                                 (0x4000D000u)
+/** Peripheral MPU base pointer */
+#define MPU                                      ((MPU_Type *)MPU_BASE)
+#define MPU_BASE_PTR                             (MPU)
+/** Array initializer of MPU peripheral base addresses */
+#define MPU_BASE_ADDRS                           { MPU_BASE }
+/** Array initializer of MPU peripheral base pointers */
+#define MPU_BASE_PTRS                            { MPU }
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register instance definitions */
+/* MPU */
+#define MPU_CESR                                 MPU_CESR_REG(MPU)
+#define MPU_EAR0                                 MPU_EAR_REG(MPU,0)
+#define MPU_EDR0                                 MPU_EDR_REG(MPU,0)
+#define MPU_EAR1                                 MPU_EAR_REG(MPU,1)
+#define MPU_EDR1                                 MPU_EDR_REG(MPU,1)
+#define MPU_EAR2                                 MPU_EAR_REG(MPU,2)
+#define MPU_EDR2                                 MPU_EDR_REG(MPU,2)
+#define MPU_EAR3                                 MPU_EAR_REG(MPU,3)
+#define MPU_EDR3                                 MPU_EDR_REG(MPU,3)
+#define MPU_EAR4                                 MPU_EAR_REG(MPU,4)
+#define MPU_EDR4                                 MPU_EDR_REG(MPU,4)
+#define MPU_RGD0_WORD0                           MPU_WORD_REG(MPU,0,0)
+#define MPU_RGD0_WORD1                           MPU_WORD_REG(MPU,0,1)
+#define MPU_RGD0_WORD2                           MPU_WORD_REG(MPU,0,2)
+#define MPU_RGD0_WORD3                           MPU_WORD_REG(MPU,0,3)
+#define MPU_RGD1_WORD0                           MPU_WORD_REG(MPU,1,0)
+#define MPU_RGD1_WORD1                           MPU_WORD_REG(MPU,1,1)
+#define MPU_RGD1_WORD2                           MPU_WORD_REG(MPU,1,2)
+#define MPU_RGD1_WORD3                           MPU_WORD_REG(MPU,1,3)
+#define MPU_RGD2_WORD0                           MPU_WORD_REG(MPU,2,0)
+#define MPU_RGD2_WORD1                           MPU_WORD_REG(MPU,2,1)
+#define MPU_RGD2_WORD2                           MPU_WORD_REG(MPU,2,2)
+#define MPU_RGD2_WORD3                           MPU_WORD_REG(MPU,2,3)
+#define MPU_RGD3_WORD0                           MPU_WORD_REG(MPU,3,0)
+#define MPU_RGD3_WORD1                           MPU_WORD_REG(MPU,3,1)
+#define MPU_RGD3_WORD2                           MPU_WORD_REG(MPU,3,2)
+#define MPU_RGD3_WORD3                           MPU_WORD_REG(MPU,3,3)
+#define MPU_RGD4_WORD0                           MPU_WORD_REG(MPU,4,0)
+#define MPU_RGD4_WORD1                           MPU_WORD_REG(MPU,4,1)
+#define MPU_RGD4_WORD2                           MPU_WORD_REG(MPU,4,2)
+#define MPU_RGD4_WORD3                           MPU_WORD_REG(MPU,4,3)
+#define MPU_RGD5_WORD0                           MPU_WORD_REG(MPU,5,0)
+#define MPU_RGD5_WORD1                           MPU_WORD_REG(MPU,5,1)
+#define MPU_RGD5_WORD2                           MPU_WORD_REG(MPU,5,2)
+#define MPU_RGD5_WORD3                           MPU_WORD_REG(MPU,5,3)
+#define MPU_RGD6_WORD0                           MPU_WORD_REG(MPU,6,0)
+#define MPU_RGD6_WORD1                           MPU_WORD_REG(MPU,6,1)
+#define MPU_RGD6_WORD2                           MPU_WORD_REG(MPU,6,2)
+#define MPU_RGD6_WORD3                           MPU_WORD_REG(MPU,6,3)
+#define MPU_RGD7_WORD0                           MPU_WORD_REG(MPU,7,0)
+#define MPU_RGD7_WORD1                           MPU_WORD_REG(MPU,7,1)
+#define MPU_RGD7_WORD2                           MPU_WORD_REG(MPU,7,2)
+#define MPU_RGD7_WORD3                           MPU_WORD_REG(MPU,7,3)
+#define MPU_RGD8_WORD0                           MPU_WORD_REG(MPU,8,0)
+#define MPU_RGD8_WORD1                           MPU_WORD_REG(MPU,8,1)
+#define MPU_RGD8_WORD2                           MPU_WORD_REG(MPU,8,2)
+#define MPU_RGD8_WORD3                           MPU_WORD_REG(MPU,8,3)
+#define MPU_RGD9_WORD0                           MPU_WORD_REG(MPU,9,0)
+#define MPU_RGD9_WORD1                           MPU_WORD_REG(MPU,9,1)
+#define MPU_RGD9_WORD2                           MPU_WORD_REG(MPU,9,2)
+#define MPU_RGD9_WORD3                           MPU_WORD_REG(MPU,9,3)
+#define MPU_RGD10_WORD0                          MPU_WORD_REG(MPU,10,0)
+#define MPU_RGD10_WORD1                          MPU_WORD_REG(MPU,10,1)
+#define MPU_RGD10_WORD2                          MPU_WORD_REG(MPU,10,2)
+#define MPU_RGD10_WORD3                          MPU_WORD_REG(MPU,10,3)
+#define MPU_RGD11_WORD0                          MPU_WORD_REG(MPU,11,0)
+#define MPU_RGD11_WORD1                          MPU_WORD_REG(MPU,11,1)
+#define MPU_RGD11_WORD2                          MPU_WORD_REG(MPU,11,2)
+#define MPU_RGD11_WORD3                          MPU_WORD_REG(MPU,11,3)
+#define MPU_RGDAAC0                              MPU_RGDAAC_REG(MPU,0)
+#define MPU_RGDAAC1                              MPU_RGDAAC_REG(MPU,1)
+#define MPU_RGDAAC2                              MPU_RGDAAC_REG(MPU,2)
+#define MPU_RGDAAC3                              MPU_RGDAAC_REG(MPU,3)
+#define MPU_RGDAAC4                              MPU_RGDAAC_REG(MPU,4)
+#define MPU_RGDAAC5                              MPU_RGDAAC_REG(MPU,5)
+#define MPU_RGDAAC6                              MPU_RGDAAC_REG(MPU,6)
+#define MPU_RGDAAC7                              MPU_RGDAAC_REG(MPU,7)
+#define MPU_RGDAAC8                              MPU_RGDAAC_REG(MPU,8)
+#define MPU_RGDAAC9                              MPU_RGDAAC_REG(MPU,9)
+#define MPU_RGDAAC10                             MPU_RGDAAC_REG(MPU,10)
+#define MPU_RGDAAC11                             MPU_RGDAAC_REG(MPU,11)
+
+/* MPU - Register array accessors */
+#define MPU_EAR(index)                           MPU_EAR_REG(MPU,index)
+#define MPU_EDR(index)                           MPU_EDR_REG(MPU,index)
+#define MPU_WORD(index,index2)                   MPU_WORD_REG(MPU,index,index2)
+#define MPU_RGDAAC(index)                        MPU_RGDAAC_REG(MPU,index)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+  __I  uint8_t FEPROT;                             /**< Non-volatile EERAM Protection Register, offset: 0xE */
+  __I  uint8_t FDPROT;                             /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base)                    ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base)                    ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base)                    ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base)                    ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base)                    ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base)                    ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base)                    ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base)                    ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base)                      ((base)->FPROT3)
+#define NV_FPROT2_REG(base)                      ((base)->FPROT2)
+#define NV_FPROT1_REG(base)                      ((base)->FPROT1)
+#define NV_FPROT0_REG(base)                      ((base)->FPROT0)
+#define NV_FSEC_REG(base)                        ((base)->FSEC)
+#define NV_FOPT_REG(base)                        ((base)->FOPT)
+#define NV_FEPROT_REG(base)                      ((base)->FEPROT)
+#define NV_FDPROT_REG(base)                      ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK                     0xFFu
+#define NV_BACKKEY3_KEY_SHIFT                    0
+#define NV_BACKKEY3_KEY_WIDTH                    8
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK                     0xFFu
+#define NV_BACKKEY2_KEY_SHIFT                    0
+#define NV_BACKKEY2_KEY_WIDTH                    8
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK                     0xFFu
+#define NV_BACKKEY1_KEY_SHIFT                    0
+#define NV_BACKKEY1_KEY_WIDTH                    8
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK                     0xFFu
+#define NV_BACKKEY0_KEY_SHIFT                    0
+#define NV_BACKKEY0_KEY_WIDTH                    8
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK                     0xFFu
+#define NV_BACKKEY7_KEY_SHIFT                    0
+#define NV_BACKKEY7_KEY_WIDTH                    8
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK                     0xFFu
+#define NV_BACKKEY6_KEY_SHIFT                    0
+#define NV_BACKKEY6_KEY_WIDTH                    8
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK                     0xFFu
+#define NV_BACKKEY5_KEY_SHIFT                    0
+#define NV_BACKKEY5_KEY_WIDTH                    8
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK                     0xFFu
+#define NV_BACKKEY4_KEY_SHIFT                    0
+#define NV_BACKKEY4_KEY_WIDTH                    8
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK                      0xFFu
+#define NV_FPROT3_PROT_SHIFT                     0
+#define NV_FPROT3_PROT_WIDTH                     8
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK                      0xFFu
+#define NV_FPROT2_PROT_SHIFT                     0
+#define NV_FPROT2_PROT_WIDTH                     8
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK                      0xFFu
+#define NV_FPROT1_PROT_SHIFT                     0
+#define NV_FPROT1_PROT_WIDTH                     8
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK                      0xFFu
+#define NV_FPROT0_PROT_SHIFT                     0
+#define NV_FPROT0_PROT_WIDTH                     8
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK                         0x3u
+#define NV_FSEC_SEC_SHIFT                        0
+#define NV_FSEC_SEC_WIDTH                        2
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      0xCu
+#define NV_FSEC_FSLACC_SHIFT                     2
+#define NV_FSEC_FSLACC_WIDTH                     2
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        0x30u
+#define NV_FSEC_MEEN_SHIFT                       4
+#define NV_FSEC_MEEN_WIDTH                       2
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       0xC0u
+#define NV_FSEC_KEYEN_SHIFT                      6
+#define NV_FSEC_KEYEN_WIDTH                      2
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK                      0x1u
+#define NV_FOPT_LPBOOT_SHIFT                     0
+#define NV_FOPT_LPBOOT_WIDTH                     1
+#define NV_FOPT_LPBOOT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT_SHIFT))&NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK                  0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT                 1
+#define NV_FOPT_EZPORT_DIS_WIDTH                 1
+#define NV_FOPT_EZPORT_DIS(x)                    (((uint8_t)(((uint8_t)(x))<<NV_FOPT_EZPORT_DIS_SHIFT))&NV_FOPT_EZPORT_DIS_MASK)
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK                     0xFFu
+#define NV_FEPROT_EPROT_SHIFT                    0
+#define NV_FEPROT_EPROT_WIDTH                    8
+#define NV_FEPROT_EPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK                     0xFFu
+#define NV_FDPROT_DPROT_SHIFT                    0
+#define NV_FDPROT_DPROT_WIDTH                    8
+#define NV_FDPROT_DPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFE_FlashConfig base address */
+#define FTFE_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFE_FlashConfig base pointer */
+#define FTFE_FlashConfig                         ((NV_Type *)FTFE_FlashConfig_BASE)
+#define FTFE_FlashConfig_BASE_PTR                (FTFE_FlashConfig)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS                            { FTFE_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS                             { FTFE_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFE_FlashConfig */
+#define NV_BACKKEY3                              NV_BACKKEY3_REG(FTFE_FlashConfig)
+#define NV_BACKKEY2                              NV_BACKKEY2_REG(FTFE_FlashConfig)
+#define NV_BACKKEY1                              NV_BACKKEY1_REG(FTFE_FlashConfig)
+#define NV_BACKKEY0                              NV_BACKKEY0_REG(FTFE_FlashConfig)
+#define NV_BACKKEY7                              NV_BACKKEY7_REG(FTFE_FlashConfig)
+#define NV_BACKKEY6                              NV_BACKKEY6_REG(FTFE_FlashConfig)
+#define NV_BACKKEY5                              NV_BACKKEY5_REG(FTFE_FlashConfig)
+#define NV_BACKKEY4                              NV_BACKKEY4_REG(FTFE_FlashConfig)
+#define NV_FPROT3                                NV_FPROT3_REG(FTFE_FlashConfig)
+#define NV_FPROT2                                NV_FPROT2_REG(FTFE_FlashConfig)
+#define NV_FPROT1                                NV_FPROT1_REG(FTFE_FlashConfig)
+#define NV_FPROT0                                NV_FPROT0_REG(FTFE_FlashConfig)
+#define NV_FSEC                                  NV_FSEC_REG(FTFE_FlashConfig)
+#define NV_FOPT                                  NV_FOPT_REG(FTFE_FlashConfig)
+#define NV_FEPROT                                NV_FEPROT_REG(FTFE_FlashConfig)
+#define NV_FDPROT                                NV_FDPROT_REG(FTFE_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base)                         ((base)->CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK                        0x1u
+#define OSC_CR_SC16P_SHIFT                       0
+#define OSC_CR_SC16P_WIDTH                       1
+#define OSC_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK                         0x2u
+#define OSC_CR_SC8P_SHIFT                        1
+#define OSC_CR_SC8P_WIDTH                        1
+#define OSC_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK                         0x4u
+#define OSC_CR_SC4P_SHIFT                        2
+#define OSC_CR_SC4P_WIDTH                        1
+#define OSC_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK                         0x8u
+#define OSC_CR_SC2P_SHIFT                        3
+#define OSC_CR_SC2P_WIDTH                        1
+#define OSC_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK                     0x20u
+#define OSC_CR_EREFSTEN_SHIFT                    5
+#define OSC_CR_EREFSTEN_WIDTH                    1
+#define OSC_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK                      0x80u
+#define OSC_CR_ERCLKEN_SHIFT                     7
+#define OSC_CR_ERCLKEN_WIDTH                     1
+#define OSC_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE                                 (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC                                      ((OSC_Type *)OSC_BASE)
+#define OSC_BASE_PTR                             (OSC)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS                           { OSC_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS                            { OSC }
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC */
+#define OSC_CR                                   OSC_CR_REG(OSC)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control register, offset: 0x0 */
+  __IO uint32_t MOD;                               /**< Modulus register, offset: 0x4 */
+  __I  uint32_t CNT;                               /**< Counter register, offset: 0x8 */
+  __IO uint32_t IDLY;                              /**< Interrupt Delay register, offset: 0xC */
+  struct {                                         /* offset: 0x10, array step: 0x28 */
+    __IO uint32_t C1;                                /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+    __IO uint32_t S;                                 /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+    __IO uint32_t DLY[2];                            /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+         uint8_t RESERVED_0[24];
+  } CH[2];
+       uint8_t RESERVED_0[240];
+  struct {                                         /* offset: 0x150, array step: 0x8 */
+    __IO uint32_t INTC;                              /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+    __IO uint32_t INT;                               /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+  } DAC[2];
+       uint8_t RESERVED_1[48];
+  __IO uint32_t POEN;                              /**< Pulse-Out n Enable register, offset: 0x190 */
+  __IO uint32_t PODLY[3];                          /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type, *PDB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register accessors */
+#define PDB_SC_REG(base)                         ((base)->SC)
+#define PDB_MOD_REG(base)                        ((base)->MOD)
+#define PDB_CNT_REG(base)                        ((base)->CNT)
+#define PDB_IDLY_REG(base)                       ((base)->IDLY)
+#define PDB_C1_REG(base,index)                   ((base)->CH[index].C1)
+#define PDB_C1_COUNT                             2
+#define PDB_S_REG(base,index)                    ((base)->CH[index].S)
+#define PDB_S_COUNT                              2
+#define PDB_DLY_REG(base,index,index2)           ((base)->CH[index].DLY[index2])
+#define PDB_DLY_COUNT                            2
+#define PDB_DLY_COUNT2                           2
+#define PDB_INTC_REG(base,index)                 ((base)->DAC[index].INTC)
+#define PDB_INTC_COUNT                           2
+#define PDB_INT_REG(base,index)                  ((base)->DAC[index].INT)
+#define PDB_INT_COUNT                            2
+#define PDB_POEN_REG(base)                       ((base)->POEN)
+#define PDB_PODLY_REG(base,index)                ((base)->PODLY[index])
+#define PDB_PODLY_COUNT                          3
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK                         0x1u
+#define PDB_SC_LDOK_SHIFT                        0
+#define PDB_SC_LDOK_WIDTH                        1
+#define PDB_SC_LDOK(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK                         0x2u
+#define PDB_SC_CONT_SHIFT                        1
+#define PDB_SC_CONT_WIDTH                        1
+#define PDB_SC_CONT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK                         0xCu
+#define PDB_SC_MULT_SHIFT                        2
+#define PDB_SC_MULT_WIDTH                        2
+#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK                        0x20u
+#define PDB_SC_PDBIE_SHIFT                       5
+#define PDB_SC_PDBIE_WIDTH                       1
+#define PDB_SC_PDBIE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK                        0x40u
+#define PDB_SC_PDBIF_SHIFT                       6
+#define PDB_SC_PDBIF_WIDTH                       1
+#define PDB_SC_PDBIF(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK                        0x80u
+#define PDB_SC_PDBEN_SHIFT                       7
+#define PDB_SC_PDBEN_WIDTH                       1
+#define PDB_SC_PDBEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK                       0xF00u
+#define PDB_SC_TRGSEL_SHIFT                      8
+#define PDB_SC_TRGSEL_WIDTH                      4
+#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK                    0x7000u
+#define PDB_SC_PRESCALER_SHIFT                   12
+#define PDB_SC_PRESCALER_WIDTH                   3
+#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK                        0x8000u
+#define PDB_SC_DMAEN_SHIFT                       15
+#define PDB_SC_DMAEN_WIDTH                       1
+#define PDB_SC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK                       0x10000u
+#define PDB_SC_SWTRIG_SHIFT                      16
+#define PDB_SC_SWTRIG_WIDTH                      1
+#define PDB_SC_SWTRIG(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK                       0x20000u
+#define PDB_SC_PDBEIE_SHIFT                      17
+#define PDB_SC_PDBEIE_WIDTH                      1
+#define PDB_SC_PDBEIE(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK                        0xC0000u
+#define PDB_SC_LDMOD_SHIFT                       18
+#define PDB_SC_LDMOD_WIDTH                       2
+#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK                         0xFFFFu
+#define PDB_MOD_MOD_SHIFT                        0
+#define PDB_MOD_MOD_WIDTH                        16
+#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK                         0xFFFFu
+#define PDB_CNT_CNT_SHIFT                        0
+#define PDB_CNT_CNT_WIDTH                        16
+#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK                       0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT                      0
+#define PDB_IDLY_IDLY_WIDTH                      16
+#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK                           0xFFu
+#define PDB_C1_EN_SHIFT                          0
+#define PDB_C1_EN_WIDTH                          8
+#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK                          0xFF00u
+#define PDB_C1_TOS_SHIFT                         8
+#define PDB_C1_TOS_WIDTH                         8
+#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK                           0xFF0000u
+#define PDB_C1_BB_SHIFT                          16
+#define PDB_C1_BB_WIDTH                          8
+#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK                           0xFFu
+#define PDB_S_ERR_SHIFT                          0
+#define PDB_S_ERR_WIDTH                          8
+#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK                            0xFF0000u
+#define PDB_S_CF_SHIFT                           16
+#define PDB_S_CF_WIDTH                           8
+#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK                         0xFFFFu
+#define PDB_DLY_DLY_SHIFT                        0
+#define PDB_DLY_DLY_WIDTH                        16
+#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* INTC Bit Fields */
+#define PDB_INTC_TOE_MASK                        0x1u
+#define PDB_INTC_TOE_SHIFT                       0
+#define PDB_INTC_TOE_WIDTH                       1
+#define PDB_INTC_TOE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_TOE_SHIFT))&PDB_INTC_TOE_MASK)
+#define PDB_INTC_EXT_MASK                        0x2u
+#define PDB_INTC_EXT_SHIFT                       1
+#define PDB_INTC_EXT_WIDTH                       1
+#define PDB_INTC_EXT(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_EXT_SHIFT))&PDB_INTC_EXT_MASK)
+/* INT Bit Fields */
+#define PDB_INT_INT_MASK                         0xFFFFu
+#define PDB_INT_INT_SHIFT                        0
+#define PDB_INT_INT_WIDTH                        16
+#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK                       0xFFu
+#define PDB_POEN_POEN_SHIFT                      0
+#define PDB_POEN_POEN_WIDTH                      8
+#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK                      0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT                     0
+#define PDB_PODLY_DLY2_WIDTH                     16
+#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK                      0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT                     16
+#define PDB_PODLY_DLY1_WIDTH                     16
+#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE                                (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0                                     ((PDB_Type *)PDB0_BASE)
+#define PDB0_BASE_PTR                            (PDB0)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS                           { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS                            { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS                                 { PDB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register instance definitions */
+/* PDB0 */
+#define PDB0_SC                                  PDB_SC_REG(PDB0)
+#define PDB0_MOD                                 PDB_MOD_REG(PDB0)
+#define PDB0_CNT                                 PDB_CNT_REG(PDB0)
+#define PDB0_IDLY                                PDB_IDLY_REG(PDB0)
+#define PDB0_CH0C1                               PDB_C1_REG(PDB0,0)
+#define PDB0_CH0S                                PDB_S_REG(PDB0,0)
+#define PDB0_CH0DLY0                             PDB_DLY_REG(PDB0,0,0)
+#define PDB0_CH0DLY1                             PDB_DLY_REG(PDB0,0,1)
+#define PDB0_CH1C1                               PDB_C1_REG(PDB0,1)
+#define PDB0_CH1S                                PDB_S_REG(PDB0,1)
+#define PDB0_CH1DLY0                             PDB_DLY_REG(PDB0,1,0)
+#define PDB0_CH1DLY1                             PDB_DLY_REG(PDB0,1,1)
+#define PDB0_DACINTC0                            PDB_INTC_REG(PDB0,0)
+#define PDB0_DACINT0                             PDB_INT_REG(PDB0,0)
+#define PDB0_DACINTC1                            PDB_INTC_REG(PDB0,1)
+#define PDB0_DACINT1                             PDB_INT_REG(PDB0,1)
+#define PDB0_POEN                                PDB_POEN_REG(PDB0)
+#define PDB0_PO0DLY                              PDB_PODLY_REG(PDB0,0)
+#define PDB0_PO1DLY                              PDB_PODLY_REG(PDB0,1)
+#define PDB0_PO2DLY                              PDB_PODLY_REG(PDB0,2)
+
+/* PDB - Register array accessors */
+#define PDB0_C1(index)                           PDB_C1_REG(PDB0,index)
+#define PDB0_S(index)                            PDB_S_REG(PDB0,index)
+#define PDB0_DLY(index,index2)                   PDB_DLY_REG(PDB0,index,index2)
+#define PDB0_INTC(index)                         PDB_INTC_REG(PDB0,index)
+#define PDB0_INT(index)                          PDB_INT_REG(PDB0,index)
+#define PDB0_PODLY(index)                        PDB_PODLY_REG(PDB0,index)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[252];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[4];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base)                        ((base)->MCR)
+#define PIT_LDVAL_REG(base,index)                ((base)->CHANNEL[index].LDVAL)
+#define PIT_LDVAL_COUNT                          4
+#define PIT_CVAL_REG(base,index)                 ((base)->CHANNEL[index].CVAL)
+#define PIT_CVAL_COUNT                           4
+#define PIT_TCTRL_REG(base,index)                ((base)->CHANNEL[index].TCTRL)
+#define PIT_TCTRL_COUNT                          4
+#define PIT_TFLG_REG(base,index)                 ((base)->CHANNEL[index].TFLG)
+#define PIT_TFLG_COUNT                           4
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK                         0x1u
+#define PIT_MCR_FRZ_SHIFT                        0
+#define PIT_MCR_FRZ_WIDTH                        1
+#define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK                        0x2u
+#define PIT_MCR_MDIS_SHIFT                       1
+#define PIT_MCR_MDIS_WIDTH                       1
+#define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT                      0
+#define PIT_LDVAL_TSV_WIDTH                      32
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT                       0
+#define PIT_CVAL_TVL_WIDTH                       32
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK                       0x1u
+#define PIT_TCTRL_TEN_SHIFT                      0
+#define PIT_TCTRL_TEN_WIDTH                      1
+#define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK                       0x2u
+#define PIT_TCTRL_TIE_SHIFT                      1
+#define PIT_TCTRL_TIE_WIDTH                      1
+#define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK                       0x4u
+#define PIT_TCTRL_CHN_SHIFT                      2
+#define PIT_TCTRL_CHN_WIDTH                      1
+#define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK                        0x1u
+#define PIT_TFLG_TIF_SHIFT                       0
+#define PIT_TFLG_TIF_WIDTH                       1
+#define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR                             (PIT)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS                           { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR                                  PIT_MCR_REG(PIT)
+#define PIT_LDVAL0                               PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0                                PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0                               PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0                                PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1                               PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1                                PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1                               PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1                                PIT_TFLG_REG(PIT,1)
+#define PIT_LDVAL2                               PIT_LDVAL_REG(PIT,2)
+#define PIT_CVAL2                                PIT_CVAL_REG(PIT,2)
+#define PIT_TCTRL2                               PIT_TCTRL_REG(PIT,2)
+#define PIT_TFLG2                                PIT_TFLG_REG(PIT,2)
+#define PIT_LDVAL3                               PIT_LDVAL_REG(PIT,3)
+#define PIT_CVAL3                                PIT_CVAL_REG(PIT,3)
+#define PIT_TCTRL3                               PIT_TCTRL_REG(PIT,3)
+#define PIT_TFLG3                                PIT_TFLG_REG(PIT,3)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index)                         PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index)                          PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index)                         PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index)                          PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base)                     ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base)                     ((base)->LVDSC2)
+#define PMC_REGSC_REG(base)                      ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK                     0x3u
+#define PMC_LVDSC1_LVDV_SHIFT                    0
+#define PMC_LVDSC1_LVDV_WIDTH                    2
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT                   4
+#define PMC_LVDSC1_LVDRE_WIDTH                   1
+#define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK                    0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT                   5
+#define PMC_LVDSC1_LVDIE_WIDTH                   1
+#define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK                   0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT                  6
+#define PMC_LVDSC1_LVDACK_WIDTH                  1
+#define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK                     0x80u
+#define PMC_LVDSC1_LVDF_SHIFT                    7
+#define PMC_LVDSC1_LVDF_WIDTH                    1
+#define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK                     0x3u
+#define PMC_LVDSC2_LVWV_SHIFT                    0
+#define PMC_LVDSC2_LVWV_WIDTH                    2
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT                   5
+#define PMC_LVDSC2_LVWIE_WIDTH                   1
+#define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK                   0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT                  6
+#define PMC_LVDSC2_LVWACK_WIDTH                  1
+#define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK                     0x80u
+#define PMC_LVDSC2_LVWF_SHIFT                    7
+#define PMC_LVDSC2_LVWF_WIDTH                    1
+#define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK                      0x1u
+#define PMC_REGSC_BGBE_SHIFT                     0
+#define PMC_REGSC_BGBE_WIDTH                     1
+#define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK                    0x4u
+#define PMC_REGSC_REGONS_SHIFT                   2
+#define PMC_REGSC_REGONS_WIDTH                   1
+#define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK                    0x8u
+#define PMC_REGSC_ACKISO_SHIFT                   3
+#define PMC_REGSC_ACKISO_WIDTH                   1
+#define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK                      0x10u
+#define PMC_REGSC_BGEN_SHIFT                     4
+#define PMC_REGSC_BGEN_WIDTH                     1
+#define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR                             (PMC)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS                           { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { LVD_LVW_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1                               PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2                               PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC                                PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
+  __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
+  __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index)                 ((base)->PCR[index])
+#define PORT_PCR_COUNT                           32
+#define PORT_GPCLR_REG(base)                     ((base)->GPCLR)
+#define PORT_GPCHR_REG(base)                     ((base)->GPCHR)
+#define PORT_ISFR_REG(base)                      ((base)->ISFR)
+#define PORT_DFER_REG(base)                      ((base)->DFER)
+#define PORT_DFCR_REG(base)                      ((base)->DFCR)
+#define PORT_DFWR_REG(base)                      ((base)->DFWR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK                         0x1u
+#define PORT_PCR_PS_SHIFT                        0
+#define PORT_PCR_PS_WIDTH                        1
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK                         0x2u
+#define PORT_PCR_PE_SHIFT                        1
+#define PORT_PCR_PE_WIDTH                        1
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK                        0x4u
+#define PORT_PCR_SRE_SHIFT                       2
+#define PORT_PCR_SRE_WIDTH                       1
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK                        0x10u
+#define PORT_PCR_PFE_SHIFT                       4
+#define PORT_PCR_PFE_WIDTH                       1
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK                        0x20u
+#define PORT_PCR_ODE_SHIFT                       5
+#define PORT_PCR_ODE_WIDTH                       1
+#define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK                        0x40u
+#define PORT_PCR_DSE_SHIFT                       6
+#define PORT_PCR_DSE_WIDTH                       1
+#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK                        0x700u
+#define PORT_PCR_MUX_SHIFT                       8
+#define PORT_PCR_MUX_WIDTH                       3
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK                         0x8000u
+#define PORT_PCR_LK_SHIFT                        15
+#define PORT_PCR_LK_WIDTH                        1
+#define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK                       0xF0000u
+#define PORT_PCR_IRQC_SHIFT                      16
+#define PORT_PCR_IRQC_WIDTH                      4
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        0x1000000u
+#define PORT_PCR_ISF_SHIFT                       24
+#define PORT_PCR_ISF_WIDTH                       1
+#define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT                    0
+#define PORT_GPCLR_GPWD_WIDTH                    16
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT                    16
+#define PORT_GPCLR_GPWE_WIDTH                    16
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT                    0
+#define PORT_GPCHR_GPWD_WIDTH                    16
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT                    16
+#define PORT_GPCHR_GPWE_WIDTH                    16
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT                      0
+#define PORT_ISFR_ISF_WIDTH                      32
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK                       0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT                      0
+#define PORT_DFER_DFE_WIDTH                      32
+#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK                        0x1u
+#define PORT_DFCR_CS_SHIFT                       0
+#define PORT_DFCR_CS_WIDTH                       1
+#define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK                      0x1Fu
+#define PORT_DFWR_FILT_SHIFT                     0
+#define PORT_DFWR_FILT_WIDTH                     5
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR                           (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR                           (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR                           (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR                           (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR                           (PORTE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0                               PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1                               PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2                               PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3                               PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4                               PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5                               PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6                               PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7                               PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8                               PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9                               PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10                              PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11                              PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12                              PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13                              PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14                              PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15                              PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16                              PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17                              PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18                              PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19                              PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20                              PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21                              PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22                              PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23                              PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24                              PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25                              PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26                              PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27                              PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28                              PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29                              PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30                              PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31                              PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR                              PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR                              PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR                               PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0                               PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1                               PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2                               PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3                               PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4                               PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5                               PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6                               PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7                               PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8                               PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9                               PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10                              PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11                              PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12                              PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13                              PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14                              PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15                              PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16                              PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17                              PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18                              PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19                              PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20                              PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21                              PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22                              PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23                              PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24                              PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25                              PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26                              PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27                              PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28                              PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29                              PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30                              PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31                              PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR                              PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR                              PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR                               PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0                               PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1                               PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2                               PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3                               PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4                               PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5                               PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6                               PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7                               PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8                               PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9                               PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10                              PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11                              PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12                              PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13                              PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14                              PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15                              PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16                              PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17                              PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18                              PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19                              PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20                              PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21                              PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22                              PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23                              PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24                              PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25                              PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26                              PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27                              PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28                              PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29                              PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30                              PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31                              PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR                              PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR                              PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR                               PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0                               PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1                               PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2                               PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3                               PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4                               PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5                               PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6                               PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7                               PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8                               PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9                               PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10                              PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11                              PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12                              PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13                              PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14                              PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15                              PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16                              PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17                              PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18                              PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19                              PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20                              PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21                              PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22                              PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23                              PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24                              PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25                              PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26                              PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27                              PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28                              PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29                              PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30                              PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31                              PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR                              PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR                              PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR                               PORT_ISFR_REG(PORTD)
+#define PORTD_DFER                               PORT_DFER_REG(PORTD)
+#define PORTD_DFCR                               PORT_DFCR_REG(PORTD)
+#define PORTD_DFWR                               PORT_DFWR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0                               PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1                               PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2                               PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3                               PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4                               PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5                               PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6                               PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7                               PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8                               PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9                               PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10                              PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11                              PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12                              PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13                              PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14                              PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15                              PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16                              PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17                              PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18                              PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19                              PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20                              PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21                              PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22                              PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23                              PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24                              PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25                              PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26                              PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27                              PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28                              PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29                              PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30                              PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31                              PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR                              PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR                              PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR                               PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index)                         PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index)                         PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index)                         PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index)                         PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index)                         PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+       uint8_t RESERVED_1[1];
+  __I  uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base)                       ((base)->SRS0)
+#define RCM_SRS1_REG(base)                       ((base)->SRS1)
+#define RCM_RPFC_REG(base)                       ((base)->RPFC)
+#define RCM_RPFW_REG(base)                       ((base)->RPFW)
+#define RCM_MR_REG(base)                         ((base)->MR)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK                     0x1u
+#define RCM_SRS0_WAKEUP_SHIFT                    0
+#define RCM_SRS0_WAKEUP_WIDTH                    1
+#define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK                        0x2u
+#define RCM_SRS0_LVD_SHIFT                       1
+#define RCM_SRS0_LVD_WIDTH                       1
+#define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK                        0x4u
+#define RCM_SRS0_LOC_SHIFT                       2
+#define RCM_SRS0_LOC_WIDTH                       1
+#define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOC_SHIFT))&RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK                        0x8u
+#define RCM_SRS0_LOL_SHIFT                       3
+#define RCM_SRS0_LOL_WIDTH                       1
+#define RCM_SRS0_LOL(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOL_SHIFT))&RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK                       0x20u
+#define RCM_SRS0_WDOG_SHIFT                      5
+#define RCM_SRS0_WDOG_WIDTH                      1
+#define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK                        0x40u
+#define RCM_SRS0_PIN_SHIFT                       6
+#define RCM_SRS0_PIN_WIDTH                       1
+#define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK                        0x80u
+#define RCM_SRS0_POR_SHIFT                       7
+#define RCM_SRS0_POR_WIDTH                       1
+#define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK                       0x1u
+#define RCM_SRS1_JTAG_SHIFT                      0
+#define RCM_SRS1_JTAG_WIDTH                      1
+#define RCM_SRS1_JTAG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_JTAG_SHIFT))&RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK                     0x2u
+#define RCM_SRS1_LOCKUP_SHIFT                    1
+#define RCM_SRS1_LOCKUP_WIDTH                    1
+#define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK                         0x4u
+#define RCM_SRS1_SW_SHIFT                        2
+#define RCM_SRS1_SW_WIDTH                        1
+#define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK                     0x8u
+#define RCM_SRS1_MDM_AP_SHIFT                    3
+#define RCM_SRS1_MDM_AP_WIDTH                    1
+#define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK                       0x10u
+#define RCM_SRS1_EZPT_SHIFT                      4
+#define RCM_SRS1_EZPT_WIDTH                      1
+#define RCM_SRS1_EZPT(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_EZPT_SHIFT))&RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK                    0x20u
+#define RCM_SRS1_SACKERR_SHIFT                   5
+#define RCM_SRS1_SACKERR_WIDTH                   1
+#define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 0
+#define RCM_RPFC_RSTFLTSRW_WIDTH                 2
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK                   0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT                  2
+#define RCM_RPFC_RSTFLTSS_WIDTH                  1
+#define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 0
+#define RCM_RPFW_RSTFLTSEL_WIDTH                 5
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK                       0x2u
+#define RCM_MR_EZP_MS_SHIFT                      1
+#define RCM_MR_EZP_MS_WIDTH                      1
+#define RCM_MR_EZP_MS(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_MR_EZP_MS_SHIFT))&RCM_MR_EZP_MS_MASK)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR                             (RCM)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS                           { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS                            { RCM }
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0                                 RCM_SRS0_REG(RCM)
+#define RCM_SRS1                                 RCM_SRS1_REG(RCM)
+#define RCM_RPFC                                 RCM_RPFC_REG(RCM)
+#define RCM_RPFW                                 RCM_RPFW_REG(RCM)
+#define RCM_MR                                   RCM_MR_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index)                ((base)->REG[index])
+#define RFSYS_REG_COUNT                          8
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK                        0xFFu
+#define RFSYS_REG_LL_SHIFT                       0
+#define RFSYS_REG_LL_WIDTH                       8
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        0xFF00u
+#define RFSYS_REG_LH_SHIFT                       8
+#define RFSYS_REG_LH_WIDTH                       8
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        0xFF0000u
+#define RFSYS_REG_HL_SHIFT                       16
+#define RFSYS_REG_HL_WIDTH                       8
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        0xFF000000u
+#define RFSYS_REG_HH_SHIFT                       24
+#define RFSYS_REG_HH_WIDTH                       8
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR                           (RFSYS)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS                          { RFSYS }
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0                               RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1                               RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2                               RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3                               RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4                               RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5                               RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6                               RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7                               RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index)                         RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type, *RFVBAT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register accessors */
+#define RFVBAT_REG_REG(base,index)               ((base)->REG[index])
+#define RFVBAT_REG_COUNT                         8
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK                       0xFFu
+#define RFVBAT_REG_LL_SHIFT                      0
+#define RFVBAT_REG_LL_WIDTH                      8
+#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK                       0xFF00u
+#define RFVBAT_REG_LH_SHIFT                      8
+#define RFVBAT_REG_LH_WIDTH                      8
+#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK                       0xFF0000u
+#define RFVBAT_REG_HL_SHIFT                      16
+#define RFVBAT_REG_HL_WIDTH                      8
+#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK                       0xFF000000u
+#define RFVBAT_REG_HH_SHIFT                      24
+#define RFVBAT_REG_HH_WIDTH                      8
+#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE                              (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
+#define RFVBAT_BASE_PTR                          (RFVBAT)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS                        { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS                         { RFVBAT }
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register instance definitions */
+/* RFVBAT */
+#define RFVBAT_REG0                              RFVBAT_REG_REG(RFVBAT,0)
+#define RFVBAT_REG1                              RFVBAT_REG_REG(RFVBAT,1)
+#define RFVBAT_REG2                              RFVBAT_REG_REG(RFVBAT,2)
+#define RFVBAT_REG3                              RFVBAT_REG_REG(RFVBAT,3)
+#define RFVBAT_REG4                              RFVBAT_REG_REG(RFVBAT,4)
+#define RFVBAT_REG5                              RFVBAT_REG_REG(RFVBAT,5)
+#define RFVBAT_REG6                              RFVBAT_REG_REG(RFVBAT,6)
+#define RFVBAT_REG7                              RFVBAT_REG_REG(RFVBAT,7)
+
+/* RFVBAT - Register array accessors */
+#define RFVBAT_REG(index)                        RFVBAT_REG_REG(RFVBAT,index)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< RNGA Control Register, offset: 0x0 */
+  __I  uint32_t SR;                                /**< RNGA Status Register, offset: 0x4 */
+  __O  uint32_t ER;                                /**< RNGA Entropy Register, offset: 0x8 */
+  __I  uint32_t OR;                                /**< RNGA Output Register, offset: 0xC */
+} RNG_Type, *RNG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register accessors */
+#define RNG_CR_REG(base)                         ((base)->CR)
+#define RNG_SR_REG(base)                         ((base)->SR)
+#define RNG_ER_REG(base)                         ((base)->ER)
+#define RNG_OR_REG(base)                         ((base)->OR)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define RNG_CR_GO_MASK                           0x1u
+#define RNG_CR_GO_SHIFT                          0
+#define RNG_CR_GO_WIDTH                          1
+#define RNG_CR_GO(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_GO_SHIFT))&RNG_CR_GO_MASK)
+#define RNG_CR_HA_MASK                           0x2u
+#define RNG_CR_HA_SHIFT                          1
+#define RNG_CR_HA_WIDTH                          1
+#define RNG_CR_HA(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_HA_SHIFT))&RNG_CR_HA_MASK)
+#define RNG_CR_INTM_MASK                         0x4u
+#define RNG_CR_INTM_SHIFT                        2
+#define RNG_CR_INTM_WIDTH                        1
+#define RNG_CR_INTM(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_INTM_SHIFT))&RNG_CR_INTM_MASK)
+#define RNG_CR_CLRI_MASK                         0x8u
+#define RNG_CR_CLRI_SHIFT                        3
+#define RNG_CR_CLRI_WIDTH                        1
+#define RNG_CR_CLRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_CLRI_SHIFT))&RNG_CR_CLRI_MASK)
+#define RNG_CR_SLP_MASK                          0x10u
+#define RNG_CR_SLP_SHIFT                         4
+#define RNG_CR_SLP_WIDTH                         1
+#define RNG_CR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_CR_SLP_SHIFT))&RNG_CR_SLP_MASK)
+/* SR Bit Fields */
+#define RNG_SR_SECV_MASK                         0x1u
+#define RNG_SR_SECV_SHIFT                        0
+#define RNG_SR_SECV_WIDTH                        1
+#define RNG_SR_SECV(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_SECV_SHIFT))&RNG_SR_SECV_MASK)
+#define RNG_SR_LRS_MASK                          0x2u
+#define RNG_SR_LRS_SHIFT                         1
+#define RNG_SR_LRS_WIDTH                         1
+#define RNG_SR_LRS(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_LRS_SHIFT))&RNG_SR_LRS_MASK)
+#define RNG_SR_ORU_MASK                          0x4u
+#define RNG_SR_ORU_SHIFT                         2
+#define RNG_SR_ORU_WIDTH                         1
+#define RNG_SR_ORU(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_ORU_SHIFT))&RNG_SR_ORU_MASK)
+#define RNG_SR_ERRI_MASK                         0x8u
+#define RNG_SR_ERRI_SHIFT                        3
+#define RNG_SR_ERRI_WIDTH                        1
+#define RNG_SR_ERRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_ERRI_SHIFT))&RNG_SR_ERRI_MASK)
+#define RNG_SR_SLP_MASK                          0x10u
+#define RNG_SR_SLP_SHIFT                         4
+#define RNG_SR_SLP_WIDTH                         1
+#define RNG_SR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_SLP_SHIFT))&RNG_SR_SLP_MASK)
+#define RNG_SR_OREG_LVL_MASK                     0xFF00u
+#define RNG_SR_OREG_LVL_SHIFT                    8
+#define RNG_SR_OREG_LVL_WIDTH                    8
+#define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK                    0xFF0000u
+#define RNG_SR_OREG_SIZE_SHIFT                   16
+#define RNG_SR_OREG_SIZE_WIDTH                   8
+#define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
+/* ER Bit Fields */
+#define RNG_ER_EXT_ENT_MASK                      0xFFFFFFFFu
+#define RNG_ER_EXT_ENT_SHIFT                     0
+#define RNG_ER_EXT_ENT_WIDTH                     32
+#define RNG_ER_EXT_ENT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
+/* OR Bit Fields */
+#define RNG_OR_RANDOUT_MASK                      0xFFFFFFFFu
+#define RNG_OR_RANDOUT_SHIFT                     0
+#define RNG_OR_RANDOUT_WIDTH                     32
+#define RNG_OR_RANDOUT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE                                 (0x40029000u)
+/** Peripheral RNG base pointer */
+#define RNG                                      ((RNG_Type *)RNG_BASE)
+#define RNG_BASE_PTR                             (RNG)
+/** Array initializer of RNG peripheral base addresses */
+#define RNG_BASE_ADDRS                           { RNG_BASE }
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASE_PTRS                            { RNG }
+/** Interrupt vectors for the RNG peripheral type */
+#define RNG_IRQS                                 { RNG_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register instance definitions */
+/* RNG */
+#define RNG_CR                                   RNG_CR_REG(RNG)
+#define RNG_SR                                   RNG_SR_REG(RNG)
+#define RNG_ER                                   RNG_ER_REG(RNG)
+#define RNG_OR                                   RNG_OR_REG(RNG)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+       uint8_t RESERVED_0[2016];
+  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base)                        ((base)->TSR)
+#define RTC_TPR_REG(base)                        ((base)->TPR)
+#define RTC_TAR_REG(base)                        ((base)->TAR)
+#define RTC_TCR_REG(base)                        ((base)->TCR)
+#define RTC_CR_REG(base)                         ((base)->CR)
+#define RTC_SR_REG(base)                         ((base)->SR)
+#define RTC_LR_REG(base)                         ((base)->LR)
+#define RTC_IER_REG(base)                        ((base)->IER)
+#define RTC_WAR_REG(base)                        ((base)->WAR)
+#define RTC_RAR_REG(base)                        ((base)->RAR)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT                        0
+#define RTC_TSR_TSR_WIDTH                        32
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK                         0xFFFFu
+#define RTC_TPR_TPR_SHIFT                        0
+#define RTC_TPR_TPR_WIDTH                        16
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT                        0
+#define RTC_TAR_TAR_WIDTH                        32
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK                         0xFFu
+#define RTC_TCR_TCR_SHIFT                        0
+#define RTC_TCR_TCR_WIDTH                        8
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         0xFF00u
+#define RTC_TCR_CIR_SHIFT                        8
+#define RTC_TCR_CIR_WIDTH                        8
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         0xFF0000u
+#define RTC_TCR_TCV_SHIFT                        16
+#define RTC_TCR_TCV_WIDTH                        8
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         0xFF000000u
+#define RTC_TCR_CIC_SHIFT                        24
+#define RTC_TCR_CIC_WIDTH                        8
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK                          0x1u
+#define RTC_CR_SWR_SHIFT                         0
+#define RTC_CR_SWR_WIDTH                         1
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK                          0x2u
+#define RTC_CR_WPE_SHIFT                         1
+#define RTC_CR_WPE_WIDTH                         1
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK                          0x4u
+#define RTC_CR_SUP_SHIFT                         2
+#define RTC_CR_SUP_WIDTH                         1
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK                           0x8u
+#define RTC_CR_UM_SHIFT                          3
+#define RTC_CR_UM_WIDTH                          1
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK                          0x10u
+#define RTC_CR_WPS_SHIFT                         4
+#define RTC_CR_WPS_WIDTH                         1
+#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK                         0x100u
+#define RTC_CR_OSCE_SHIFT                        8
+#define RTC_CR_OSCE_WIDTH                        1
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK                         0x200u
+#define RTC_CR_CLKO_SHIFT                        9
+#define RTC_CR_CLKO_WIDTH                        1
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK                        0x400u
+#define RTC_CR_SC16P_SHIFT                       10
+#define RTC_CR_SC16P_WIDTH                       1
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK                         0x800u
+#define RTC_CR_SC8P_SHIFT                        11
+#define RTC_CR_SC8P_WIDTH                        1
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK                         0x1000u
+#define RTC_CR_SC4P_SHIFT                        12
+#define RTC_CR_SC4P_WIDTH                        1
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK                         0x2000u
+#define RTC_CR_SC2P_SHIFT                        13
+#define RTC_CR_SC2P_WIDTH                        1
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK                          0x1u
+#define RTC_SR_TIF_SHIFT                         0
+#define RTC_SR_TIF_WIDTH                         1
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK                          0x2u
+#define RTC_SR_TOF_SHIFT                         1
+#define RTC_SR_TOF_WIDTH                         1
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK                          0x4u
+#define RTC_SR_TAF_SHIFT                         2
+#define RTC_SR_TAF_WIDTH                         1
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK                          0x10u
+#define RTC_SR_TCE_SHIFT                         4
+#define RTC_SR_TCE_WIDTH                         1
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK                          0x8u
+#define RTC_LR_TCL_SHIFT                         3
+#define RTC_LR_TCL_WIDTH                         1
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK                          0x10u
+#define RTC_LR_CRL_SHIFT                         4
+#define RTC_LR_CRL_WIDTH                         1
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK                          0x20u
+#define RTC_LR_SRL_SHIFT                         5
+#define RTC_LR_SRL_WIDTH                         1
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK                          0x40u
+#define RTC_LR_LRL_SHIFT                         6
+#define RTC_LR_LRL_WIDTH                         1
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK                        0x1u
+#define RTC_IER_TIIE_SHIFT                       0
+#define RTC_IER_TIIE_WIDTH                       1
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK                        0x2u
+#define RTC_IER_TOIE_SHIFT                       1
+#define RTC_IER_TOIE_WIDTH                       1
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK                        0x4u
+#define RTC_IER_TAIE_SHIFT                       2
+#define RTC_IER_TAIE_WIDTH                       1
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK                        0x10u
+#define RTC_IER_TSIE_SHIFT                       4
+#define RTC_IER_TSIE_WIDTH                       1
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK                        0x80u
+#define RTC_IER_WPON_SHIFT                       7
+#define RTC_IER_WPON_WIDTH                       1
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK                        0x1u
+#define RTC_WAR_TSRW_SHIFT                       0
+#define RTC_WAR_TSRW_WIDTH                       1
+#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TSRW_SHIFT))&RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK                        0x2u
+#define RTC_WAR_TPRW_SHIFT                       1
+#define RTC_WAR_TPRW_WIDTH                       1
+#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TPRW_SHIFT))&RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK                        0x4u
+#define RTC_WAR_TARW_SHIFT                       2
+#define RTC_WAR_TARW_WIDTH                       1
+#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TARW_SHIFT))&RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK                        0x8u
+#define RTC_WAR_TCRW_SHIFT                       3
+#define RTC_WAR_TCRW_WIDTH                       1
+#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TCRW_SHIFT))&RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK                         0x10u
+#define RTC_WAR_CRW_SHIFT                        4
+#define RTC_WAR_CRW_WIDTH                        1
+#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_CRW_SHIFT))&RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK                         0x20u
+#define RTC_WAR_SRW_SHIFT                        5
+#define RTC_WAR_SRW_WIDTH                        1
+#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_SRW_SHIFT))&RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK                         0x40u
+#define RTC_WAR_LRW_SHIFT                        6
+#define RTC_WAR_LRW_WIDTH                        1
+#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_LRW_SHIFT))&RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK                        0x80u
+#define RTC_WAR_IERW_SHIFT                       7
+#define RTC_WAR_IERW_WIDTH                       1
+#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_IERW_SHIFT))&RTC_WAR_IERW_MASK)
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK                        0x1u
+#define RTC_RAR_TSRR_SHIFT                       0
+#define RTC_RAR_TSRR_WIDTH                       1
+#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TSRR_SHIFT))&RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK                        0x2u
+#define RTC_RAR_TPRR_SHIFT                       1
+#define RTC_RAR_TPRR_WIDTH                       1
+#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TPRR_SHIFT))&RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK                        0x4u
+#define RTC_RAR_TARR_SHIFT                       2
+#define RTC_RAR_TARR_WIDTH                       1
+#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TARR_SHIFT))&RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK                        0x8u
+#define RTC_RAR_TCRR_SHIFT                       3
+#define RTC_RAR_TCRR_WIDTH                       1
+#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TCRR_SHIFT))&RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK                         0x10u
+#define RTC_RAR_CRR_SHIFT                        4
+#define RTC_RAR_CRR_WIDTH                        1
+#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_CRR_SHIFT))&RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK                         0x20u
+#define RTC_RAR_SRR_SHIFT                        5
+#define RTC_RAR_SRR_WIDTH                        1
+#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_SRR_SHIFT))&RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK                         0x40u
+#define RTC_RAR_LRR_SHIFT                        6
+#define RTC_RAR_LRR_WIDTH                        1
+#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_LRR_SHIFT))&RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK                        0x80u
+#define RTC_RAR_IERR_SHIFT                       7
+#define RTC_RAR_IERR_WIDTH                       1
+#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_IERR_SHIFT))&RTC_RAR_IERR_MASK)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR                             (RTC)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR                                  RTC_TSR_REG(RTC)
+#define RTC_TPR                                  RTC_TPR_REG(RTC)
+#define RTC_TAR                                  RTC_TAR_REG(RTC)
+#define RTC_TCR                                  RTC_TCR_REG(RTC)
+#define RTC_CR                                   RTC_CR_REG(RTC)
+#define RTC_SR                                   RTC_SR_REG(RTC)
+#define RTC_LR                                   RTC_LR_REG(RTC)
+#define RTC_IER                                  RTC_IER_REG(RTC)
+#define RTC_WAR                                  RTC_WAR_REG(RTC)
+#define RTC_RAR                                  RTC_RAR_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
+ * @{
+ */
+
+/** SDHC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DSADDR;                            /**< DMA System Address register, offset: 0x0 */
+  __IO uint32_t BLKATTR;                           /**< Block Attributes register, offset: 0x4 */
+  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x8 */
+  __IO uint32_t XFERTYP;                           /**< Transfer Type register, offset: 0xC */
+  __I  uint32_t CMDRSP[4];                         /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t DATPORT;                           /**< Buffer Data Port register, offset: 0x20 */
+  __I  uint32_t PRSSTAT;                           /**< Present State register, offset: 0x24 */
+  __IO uint32_t PROCTL;                            /**< Protocol Control register, offset: 0x28 */
+  __IO uint32_t SYSCTL;                            /**< System Control register, offset: 0x2C */
+  __IO uint32_t IRQSTAT;                           /**< Interrupt Status register, offset: 0x30 */
+  __IO uint32_t IRQSTATEN;                         /**< Interrupt Status Enable register, offset: 0x34 */
+  __IO uint32_t IRQSIGEN;                          /**< Interrupt Signal Enable register, offset: 0x38 */
+  __I  uint32_t AC12ERR;                           /**< Auto CMD12 Error Status Register, offset: 0x3C */
+  __I  uint32_t HTCAPBLT;                          /**< Host Controller Capabilities, offset: 0x40 */
+  __IO uint32_t WML;                               /**< Watermark Level Register, offset: 0x44 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t FEVT;                              /**< Force Event register, offset: 0x50 */
+  __I  uint32_t ADMAES;                            /**< ADMA Error Status register, offset: 0x54 */
+  __IO uint32_t ADSADDR;                           /**< ADMA System Addressregister, offset: 0x58 */
+       uint8_t RESERVED_1[100];
+  __IO uint32_t VENDOR;                            /**< Vendor Specific register, offset: 0xC0 */
+  __IO uint32_t MMCBOOT;                           /**< MMC Boot register, offset: 0xC4 */
+       uint8_t RESERVED_2[52];
+  __I  uint32_t HOSTVER;                           /**< Host Controller Version, offset: 0xFC */
+} SDHC_Type, *SDHC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register accessors */
+#define SDHC_DSADDR_REG(base)                    ((base)->DSADDR)
+#define SDHC_BLKATTR_REG(base)                   ((base)->BLKATTR)
+#define SDHC_CMDARG_REG(base)                    ((base)->CMDARG)
+#define SDHC_XFERTYP_REG(base)                   ((base)->XFERTYP)
+#define SDHC_CMDRSP_REG(base,index)              ((base)->CMDRSP[index])
+#define SDHC_CMDRSP_COUNT                        4
+#define SDHC_DATPORT_REG(base)                   ((base)->DATPORT)
+#define SDHC_PRSSTAT_REG(base)                   ((base)->PRSSTAT)
+#define SDHC_PROCTL_REG(base)                    ((base)->PROCTL)
+#define SDHC_SYSCTL_REG(base)                    ((base)->SYSCTL)
+#define SDHC_IRQSTAT_REG(base)                   ((base)->IRQSTAT)
+#define SDHC_IRQSTATEN_REG(base)                 ((base)->IRQSTATEN)
+#define SDHC_IRQSIGEN_REG(base)                  ((base)->IRQSIGEN)
+#define SDHC_AC12ERR_REG(base)                   ((base)->AC12ERR)
+#define SDHC_HTCAPBLT_REG(base)                  ((base)->HTCAPBLT)
+#define SDHC_WML_REG(base)                       ((base)->WML)
+#define SDHC_FEVT_REG(base)                      ((base)->FEVT)
+#define SDHC_ADMAES_REG(base)                    ((base)->ADMAES)
+#define SDHC_ADSADDR_REG(base)                   ((base)->ADSADDR)
+#define SDHC_VENDOR_REG(base)                    ((base)->VENDOR)
+#define SDHC_MMCBOOT_REG(base)                   ((base)->MMCBOOT)
+#define SDHC_HOSTVER_REG(base)                   ((base)->HOSTVER)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/* DSADDR Bit Fields */
+#define SDHC_DSADDR_DSADDR_MASK                  0xFFFFFFFCu
+#define SDHC_DSADDR_DSADDR_SHIFT                 2
+#define SDHC_DSADDR_DSADDR_WIDTH                 30
+#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
+/* BLKATTR Bit Fields */
+#define SDHC_BLKATTR_BLKSIZE_MASK                0x1FFFu
+#define SDHC_BLKATTR_BLKSIZE_SHIFT               0
+#define SDHC_BLKATTR_BLKSIZE_WIDTH               13
+#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK                 0xFFFF0000u
+#define SDHC_BLKATTR_BLKCNT_SHIFT                16
+#define SDHC_BLKATTR_BLKCNT_WIDTH                16
+#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
+/* CMDARG Bit Fields */
+#define SDHC_CMDARG_CMDARG_MASK                  0xFFFFFFFFu
+#define SDHC_CMDARG_CMDARG_SHIFT                 0
+#define SDHC_CMDARG_CMDARG_WIDTH                 32
+#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
+/* XFERTYP Bit Fields */
+#define SDHC_XFERTYP_DMAEN_MASK                  0x1u
+#define SDHC_XFERTYP_DMAEN_SHIFT                 0
+#define SDHC_XFERTYP_DMAEN_WIDTH                 1
+#define SDHC_XFERTYP_DMAEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DMAEN_SHIFT))&SDHC_XFERTYP_DMAEN_MASK)
+#define SDHC_XFERTYP_BCEN_MASK                   0x2u
+#define SDHC_XFERTYP_BCEN_SHIFT                  1
+#define SDHC_XFERTYP_BCEN_WIDTH                  1
+#define SDHC_XFERTYP_BCEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_BCEN_SHIFT))&SDHC_XFERTYP_BCEN_MASK)
+#define SDHC_XFERTYP_AC12EN_MASK                 0x4u
+#define SDHC_XFERTYP_AC12EN_SHIFT                2
+#define SDHC_XFERTYP_AC12EN_WIDTH                1
+#define SDHC_XFERTYP_AC12EN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_AC12EN_SHIFT))&SDHC_XFERTYP_AC12EN_MASK)
+#define SDHC_XFERTYP_DTDSEL_MASK                 0x10u
+#define SDHC_XFERTYP_DTDSEL_SHIFT                4
+#define SDHC_XFERTYP_DTDSEL_WIDTH                1
+#define SDHC_XFERTYP_DTDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DTDSEL_SHIFT))&SDHC_XFERTYP_DTDSEL_MASK)
+#define SDHC_XFERTYP_MSBSEL_MASK                 0x20u
+#define SDHC_XFERTYP_MSBSEL_SHIFT                5
+#define SDHC_XFERTYP_MSBSEL_WIDTH                1
+#define SDHC_XFERTYP_MSBSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_MSBSEL_SHIFT))&SDHC_XFERTYP_MSBSEL_MASK)
+#define SDHC_XFERTYP_RSPTYP_MASK                 0x30000u
+#define SDHC_XFERTYP_RSPTYP_SHIFT                16
+#define SDHC_XFERTYP_RSPTYP_WIDTH                2
+#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK                  0x80000u
+#define SDHC_XFERTYP_CCCEN_SHIFT                 19
+#define SDHC_XFERTYP_CCCEN_WIDTH                 1
+#define SDHC_XFERTYP_CCCEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CCCEN_SHIFT))&SDHC_XFERTYP_CCCEN_MASK)
+#define SDHC_XFERTYP_CICEN_MASK                  0x100000u
+#define SDHC_XFERTYP_CICEN_SHIFT                 20
+#define SDHC_XFERTYP_CICEN_WIDTH                 1
+#define SDHC_XFERTYP_CICEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CICEN_SHIFT))&SDHC_XFERTYP_CICEN_MASK)
+#define SDHC_XFERTYP_DPSEL_MASK                  0x200000u
+#define SDHC_XFERTYP_DPSEL_SHIFT                 21
+#define SDHC_XFERTYP_DPSEL_WIDTH                 1
+#define SDHC_XFERTYP_DPSEL(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DPSEL_SHIFT))&SDHC_XFERTYP_DPSEL_MASK)
+#define SDHC_XFERTYP_CMDTYP_MASK                 0xC00000u
+#define SDHC_XFERTYP_CMDTYP_SHIFT                22
+#define SDHC_XFERTYP_CMDTYP_WIDTH                2
+#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK                 0x3F000000u
+#define SDHC_XFERTYP_CMDINX_SHIFT                24
+#define SDHC_XFERTYP_CMDINX_WIDTH                6
+#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
+/* CMDRSP Bit Fields */
+#define SDHC_CMDRSP_CMDRSP0_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP0_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP0_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP1_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP1_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP2_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP2_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP3_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP3_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
+/* DATPORT Bit Fields */
+#define SDHC_DATPORT_DATCONT_MASK                0xFFFFFFFFu
+#define SDHC_DATPORT_DATCONT_SHIFT               0
+#define SDHC_DATPORT_DATCONT_WIDTH               32
+#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
+/* PRSSTAT Bit Fields */
+#define SDHC_PRSSTAT_CIHB_MASK                   0x1u
+#define SDHC_PRSSTAT_CIHB_SHIFT                  0
+#define SDHC_PRSSTAT_CIHB_WIDTH                  1
+#define SDHC_PRSSTAT_CIHB(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CIHB_SHIFT))&SDHC_PRSSTAT_CIHB_MASK)
+#define SDHC_PRSSTAT_CDIHB_MASK                  0x2u
+#define SDHC_PRSSTAT_CDIHB_SHIFT                 1
+#define SDHC_PRSSTAT_CDIHB_WIDTH                 1
+#define SDHC_PRSSTAT_CDIHB(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CDIHB_SHIFT))&SDHC_PRSSTAT_CDIHB_MASK)
+#define SDHC_PRSSTAT_DLA_MASK                    0x4u
+#define SDHC_PRSSTAT_DLA_SHIFT                   2
+#define SDHC_PRSSTAT_DLA_WIDTH                   1
+#define SDHC_PRSSTAT_DLA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLA_SHIFT))&SDHC_PRSSTAT_DLA_MASK)
+#define SDHC_PRSSTAT_SDSTB_MASK                  0x8u
+#define SDHC_PRSSTAT_SDSTB_SHIFT                 3
+#define SDHC_PRSSTAT_SDSTB_WIDTH                 1
+#define SDHC_PRSSTAT_SDSTB(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDSTB_SHIFT))&SDHC_PRSSTAT_SDSTB_MASK)
+#define SDHC_PRSSTAT_IPGOFF_MASK                 0x10u
+#define SDHC_PRSSTAT_IPGOFF_SHIFT                4
+#define SDHC_PRSSTAT_IPGOFF_WIDTH                1
+#define SDHC_PRSSTAT_IPGOFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_IPGOFF_SHIFT))&SDHC_PRSSTAT_IPGOFF_MASK)
+#define SDHC_PRSSTAT_HCKOFF_MASK                 0x20u
+#define SDHC_PRSSTAT_HCKOFF_SHIFT                5
+#define SDHC_PRSSTAT_HCKOFF_WIDTH                1
+#define SDHC_PRSSTAT_HCKOFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_HCKOFF_SHIFT))&SDHC_PRSSTAT_HCKOFF_MASK)
+#define SDHC_PRSSTAT_PEROFF_MASK                 0x40u
+#define SDHC_PRSSTAT_PEROFF_SHIFT                6
+#define SDHC_PRSSTAT_PEROFF_WIDTH                1
+#define SDHC_PRSSTAT_PEROFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_PEROFF_SHIFT))&SDHC_PRSSTAT_PEROFF_MASK)
+#define SDHC_PRSSTAT_SDOFF_MASK                  0x80u
+#define SDHC_PRSSTAT_SDOFF_SHIFT                 7
+#define SDHC_PRSSTAT_SDOFF_WIDTH                 1
+#define SDHC_PRSSTAT_SDOFF(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDOFF_SHIFT))&SDHC_PRSSTAT_SDOFF_MASK)
+#define SDHC_PRSSTAT_WTA_MASK                    0x100u
+#define SDHC_PRSSTAT_WTA_SHIFT                   8
+#define SDHC_PRSSTAT_WTA_WIDTH                   1
+#define SDHC_PRSSTAT_WTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_WTA_SHIFT))&SDHC_PRSSTAT_WTA_MASK)
+#define SDHC_PRSSTAT_RTA_MASK                    0x200u
+#define SDHC_PRSSTAT_RTA_SHIFT                   9
+#define SDHC_PRSSTAT_RTA_WIDTH                   1
+#define SDHC_PRSSTAT_RTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_RTA_SHIFT))&SDHC_PRSSTAT_RTA_MASK)
+#define SDHC_PRSSTAT_BWEN_MASK                   0x400u
+#define SDHC_PRSSTAT_BWEN_SHIFT                  10
+#define SDHC_PRSSTAT_BWEN_WIDTH                  1
+#define SDHC_PRSSTAT_BWEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BWEN_SHIFT))&SDHC_PRSSTAT_BWEN_MASK)
+#define SDHC_PRSSTAT_BREN_MASK                   0x800u
+#define SDHC_PRSSTAT_BREN_SHIFT                  11
+#define SDHC_PRSSTAT_BREN_WIDTH                  1
+#define SDHC_PRSSTAT_BREN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BREN_SHIFT))&SDHC_PRSSTAT_BREN_MASK)
+#define SDHC_PRSSTAT_CINS_MASK                   0x10000u
+#define SDHC_PRSSTAT_CINS_SHIFT                  16
+#define SDHC_PRSSTAT_CINS_WIDTH                  1
+#define SDHC_PRSSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CINS_SHIFT))&SDHC_PRSSTAT_CINS_MASK)
+#define SDHC_PRSSTAT_CLSL_MASK                   0x800000u
+#define SDHC_PRSSTAT_CLSL_SHIFT                  23
+#define SDHC_PRSSTAT_CLSL_WIDTH                  1
+#define SDHC_PRSSTAT_CLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CLSL_SHIFT))&SDHC_PRSSTAT_CLSL_MASK)
+#define SDHC_PRSSTAT_DLSL_MASK                   0xFF000000u
+#define SDHC_PRSSTAT_DLSL_SHIFT                  24
+#define SDHC_PRSSTAT_DLSL_WIDTH                  8
+#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
+/* PROCTL Bit Fields */
+#define SDHC_PROCTL_LCTL_MASK                    0x1u
+#define SDHC_PROCTL_LCTL_SHIFT                   0
+#define SDHC_PROCTL_LCTL_WIDTH                   1
+#define SDHC_PROCTL_LCTL(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_LCTL_SHIFT))&SDHC_PROCTL_LCTL_MASK)
+#define SDHC_PROCTL_DTW_MASK                     0x6u
+#define SDHC_PROCTL_DTW_SHIFT                    1
+#define SDHC_PROCTL_DTW_WIDTH                    2
+#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK                    0x8u
+#define SDHC_PROCTL_D3CD_SHIFT                   3
+#define SDHC_PROCTL_D3CD_WIDTH                   1
+#define SDHC_PROCTL_D3CD(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_D3CD_SHIFT))&SDHC_PROCTL_D3CD_MASK)
+#define SDHC_PROCTL_EMODE_MASK                   0x30u
+#define SDHC_PROCTL_EMODE_SHIFT                  4
+#define SDHC_PROCTL_EMODE_WIDTH                  2
+#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK                    0x40u
+#define SDHC_PROCTL_CDTL_SHIFT                   6
+#define SDHC_PROCTL_CDTL_WIDTH                   1
+#define SDHC_PROCTL_CDTL(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDTL_SHIFT))&SDHC_PROCTL_CDTL_MASK)
+#define SDHC_PROCTL_CDSS_MASK                    0x80u
+#define SDHC_PROCTL_CDSS_SHIFT                   7
+#define SDHC_PROCTL_CDSS_WIDTH                   1
+#define SDHC_PROCTL_CDSS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDSS_SHIFT))&SDHC_PROCTL_CDSS_MASK)
+#define SDHC_PROCTL_DMAS_MASK                    0x300u
+#define SDHC_PROCTL_DMAS_SHIFT                   8
+#define SDHC_PROCTL_DMAS_WIDTH                   2
+#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK                 0x10000u
+#define SDHC_PROCTL_SABGREQ_SHIFT                16
+#define SDHC_PROCTL_SABGREQ_WIDTH                1
+#define SDHC_PROCTL_SABGREQ(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_SABGREQ_SHIFT))&SDHC_PROCTL_SABGREQ_MASK)
+#define SDHC_PROCTL_CREQ_MASK                    0x20000u
+#define SDHC_PROCTL_CREQ_SHIFT                   17
+#define SDHC_PROCTL_CREQ_WIDTH                   1
+#define SDHC_PROCTL_CREQ(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CREQ_SHIFT))&SDHC_PROCTL_CREQ_MASK)
+#define SDHC_PROCTL_RWCTL_MASK                   0x40000u
+#define SDHC_PROCTL_RWCTL_SHIFT                  18
+#define SDHC_PROCTL_RWCTL_WIDTH                  1
+#define SDHC_PROCTL_RWCTL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_RWCTL_SHIFT))&SDHC_PROCTL_RWCTL_MASK)
+#define SDHC_PROCTL_IABG_MASK                    0x80000u
+#define SDHC_PROCTL_IABG_SHIFT                   19
+#define SDHC_PROCTL_IABG_WIDTH                   1
+#define SDHC_PROCTL_IABG(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_IABG_SHIFT))&SDHC_PROCTL_IABG_MASK)
+#define SDHC_PROCTL_WECINT_MASK                  0x1000000u
+#define SDHC_PROCTL_WECINT_SHIFT                 24
+#define SDHC_PROCTL_WECINT_WIDTH                 1
+#define SDHC_PROCTL_WECINT(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINT_SHIFT))&SDHC_PROCTL_WECINT_MASK)
+#define SDHC_PROCTL_WECINS_MASK                  0x2000000u
+#define SDHC_PROCTL_WECINS_SHIFT                 25
+#define SDHC_PROCTL_WECINS_WIDTH                 1
+#define SDHC_PROCTL_WECINS(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINS_SHIFT))&SDHC_PROCTL_WECINS_MASK)
+#define SDHC_PROCTL_WECRM_MASK                   0x4000000u
+#define SDHC_PROCTL_WECRM_SHIFT                  26
+#define SDHC_PROCTL_WECRM_WIDTH                  1
+#define SDHC_PROCTL_WECRM(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECRM_SHIFT))&SDHC_PROCTL_WECRM_MASK)
+/* SYSCTL Bit Fields */
+#define SDHC_SYSCTL_IPGEN_MASK                   0x1u
+#define SDHC_SYSCTL_IPGEN_SHIFT                  0
+#define SDHC_SYSCTL_IPGEN_WIDTH                  1
+#define SDHC_SYSCTL_IPGEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_IPGEN_SHIFT))&SDHC_SYSCTL_IPGEN_MASK)
+#define SDHC_SYSCTL_HCKEN_MASK                   0x2u
+#define SDHC_SYSCTL_HCKEN_SHIFT                  1
+#define SDHC_SYSCTL_HCKEN_WIDTH                  1
+#define SDHC_SYSCTL_HCKEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_HCKEN_SHIFT))&SDHC_SYSCTL_HCKEN_MASK)
+#define SDHC_SYSCTL_PEREN_MASK                   0x4u
+#define SDHC_SYSCTL_PEREN_SHIFT                  2
+#define SDHC_SYSCTL_PEREN_WIDTH                  1
+#define SDHC_SYSCTL_PEREN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_PEREN_SHIFT))&SDHC_SYSCTL_PEREN_MASK)
+#define SDHC_SYSCTL_SDCLKEN_MASK                 0x8u
+#define SDHC_SYSCTL_SDCLKEN_SHIFT                3
+#define SDHC_SYSCTL_SDCLKEN_WIDTH                1
+#define SDHC_SYSCTL_SDCLKEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKEN_SHIFT))&SDHC_SYSCTL_SDCLKEN_MASK)
+#define SDHC_SYSCTL_DVS_MASK                     0xF0u
+#define SDHC_SYSCTL_DVS_SHIFT                    4
+#define SDHC_SYSCTL_DVS_WIDTH                    4
+#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK                 0xFF00u
+#define SDHC_SYSCTL_SDCLKFS_SHIFT                8
+#define SDHC_SYSCTL_SDCLKFS_WIDTH                8
+#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK                   0xF0000u
+#define SDHC_SYSCTL_DTOCV_SHIFT                  16
+#define SDHC_SYSCTL_DTOCV_WIDTH                  4
+#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK                    0x1000000u
+#define SDHC_SYSCTL_RSTA_SHIFT                   24
+#define SDHC_SYSCTL_RSTA_WIDTH                   1
+#define SDHC_SYSCTL_RSTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTA_SHIFT))&SDHC_SYSCTL_RSTA_MASK)
+#define SDHC_SYSCTL_RSTC_MASK                    0x2000000u
+#define SDHC_SYSCTL_RSTC_SHIFT                   25
+#define SDHC_SYSCTL_RSTC_WIDTH                   1
+#define SDHC_SYSCTL_RSTC(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTC_SHIFT))&SDHC_SYSCTL_RSTC_MASK)
+#define SDHC_SYSCTL_RSTD_MASK                    0x4000000u
+#define SDHC_SYSCTL_RSTD_SHIFT                   26
+#define SDHC_SYSCTL_RSTD_WIDTH                   1
+#define SDHC_SYSCTL_RSTD(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTD_SHIFT))&SDHC_SYSCTL_RSTD_MASK)
+#define SDHC_SYSCTL_INITA_MASK                   0x8000000u
+#define SDHC_SYSCTL_INITA_SHIFT                  27
+#define SDHC_SYSCTL_INITA_WIDTH                  1
+#define SDHC_SYSCTL_INITA(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_INITA_SHIFT))&SDHC_SYSCTL_INITA_MASK)
+/* IRQSTAT Bit Fields */
+#define SDHC_IRQSTAT_CC_MASK                     0x1u
+#define SDHC_IRQSTAT_CC_SHIFT                    0
+#define SDHC_IRQSTAT_CC_WIDTH                    1
+#define SDHC_IRQSTAT_CC(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CC_SHIFT))&SDHC_IRQSTAT_CC_MASK)
+#define SDHC_IRQSTAT_TC_MASK                     0x2u
+#define SDHC_IRQSTAT_TC_SHIFT                    1
+#define SDHC_IRQSTAT_TC_WIDTH                    1
+#define SDHC_IRQSTAT_TC(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_TC_SHIFT))&SDHC_IRQSTAT_TC_MASK)
+#define SDHC_IRQSTAT_BGE_MASK                    0x4u
+#define SDHC_IRQSTAT_BGE_SHIFT                   2
+#define SDHC_IRQSTAT_BGE_WIDTH                   1
+#define SDHC_IRQSTAT_BGE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BGE_SHIFT))&SDHC_IRQSTAT_BGE_MASK)
+#define SDHC_IRQSTAT_DINT_MASK                   0x8u
+#define SDHC_IRQSTAT_DINT_SHIFT                  3
+#define SDHC_IRQSTAT_DINT_WIDTH                  1
+#define SDHC_IRQSTAT_DINT(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DINT_SHIFT))&SDHC_IRQSTAT_DINT_MASK)
+#define SDHC_IRQSTAT_BWR_MASK                    0x10u
+#define SDHC_IRQSTAT_BWR_SHIFT                   4
+#define SDHC_IRQSTAT_BWR_WIDTH                   1
+#define SDHC_IRQSTAT_BWR(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BWR_SHIFT))&SDHC_IRQSTAT_BWR_MASK)
+#define SDHC_IRQSTAT_BRR_MASK                    0x20u
+#define SDHC_IRQSTAT_BRR_SHIFT                   5
+#define SDHC_IRQSTAT_BRR_WIDTH                   1
+#define SDHC_IRQSTAT_BRR(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BRR_SHIFT))&SDHC_IRQSTAT_BRR_MASK)
+#define SDHC_IRQSTAT_CINS_MASK                   0x40u
+#define SDHC_IRQSTAT_CINS_SHIFT                  6
+#define SDHC_IRQSTAT_CINS_WIDTH                  1
+#define SDHC_IRQSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINS_SHIFT))&SDHC_IRQSTAT_CINS_MASK)
+#define SDHC_IRQSTAT_CRM_MASK                    0x80u
+#define SDHC_IRQSTAT_CRM_SHIFT                   7
+#define SDHC_IRQSTAT_CRM_WIDTH                   1
+#define SDHC_IRQSTAT_CRM(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CRM_SHIFT))&SDHC_IRQSTAT_CRM_MASK)
+#define SDHC_IRQSTAT_CINT_MASK                   0x100u
+#define SDHC_IRQSTAT_CINT_SHIFT                  8
+#define SDHC_IRQSTAT_CINT_WIDTH                  1
+#define SDHC_IRQSTAT_CINT(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINT_SHIFT))&SDHC_IRQSTAT_CINT_MASK)
+#define SDHC_IRQSTAT_CTOE_MASK                   0x10000u
+#define SDHC_IRQSTAT_CTOE_SHIFT                  16
+#define SDHC_IRQSTAT_CTOE_WIDTH                  1
+#define SDHC_IRQSTAT_CTOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CTOE_SHIFT))&SDHC_IRQSTAT_CTOE_MASK)
+#define SDHC_IRQSTAT_CCE_MASK                    0x20000u
+#define SDHC_IRQSTAT_CCE_SHIFT                   17
+#define SDHC_IRQSTAT_CCE_WIDTH                   1
+#define SDHC_IRQSTAT_CCE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CCE_SHIFT))&SDHC_IRQSTAT_CCE_MASK)
+#define SDHC_IRQSTAT_CEBE_MASK                   0x40000u
+#define SDHC_IRQSTAT_CEBE_SHIFT                  18
+#define SDHC_IRQSTAT_CEBE_WIDTH                  1
+#define SDHC_IRQSTAT_CEBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CEBE_SHIFT))&SDHC_IRQSTAT_CEBE_MASK)
+#define SDHC_IRQSTAT_CIE_MASK                    0x80000u
+#define SDHC_IRQSTAT_CIE_SHIFT                   19
+#define SDHC_IRQSTAT_CIE_WIDTH                   1
+#define SDHC_IRQSTAT_CIE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CIE_SHIFT))&SDHC_IRQSTAT_CIE_MASK)
+#define SDHC_IRQSTAT_DTOE_MASK                   0x100000u
+#define SDHC_IRQSTAT_DTOE_SHIFT                  20
+#define SDHC_IRQSTAT_DTOE_WIDTH                  1
+#define SDHC_IRQSTAT_DTOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DTOE_SHIFT))&SDHC_IRQSTAT_DTOE_MASK)
+#define SDHC_IRQSTAT_DCE_MASK                    0x200000u
+#define SDHC_IRQSTAT_DCE_SHIFT                   21
+#define SDHC_IRQSTAT_DCE_WIDTH                   1
+#define SDHC_IRQSTAT_DCE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DCE_SHIFT))&SDHC_IRQSTAT_DCE_MASK)
+#define SDHC_IRQSTAT_DEBE_MASK                   0x400000u
+#define SDHC_IRQSTAT_DEBE_SHIFT                  22
+#define SDHC_IRQSTAT_DEBE_WIDTH                  1
+#define SDHC_IRQSTAT_DEBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DEBE_SHIFT))&SDHC_IRQSTAT_DEBE_MASK)
+#define SDHC_IRQSTAT_AC12E_MASK                  0x1000000u
+#define SDHC_IRQSTAT_AC12E_SHIFT                 24
+#define SDHC_IRQSTAT_AC12E_WIDTH                 1
+#define SDHC_IRQSTAT_AC12E(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_AC12E_SHIFT))&SDHC_IRQSTAT_AC12E_MASK)
+#define SDHC_IRQSTAT_DMAE_MASK                   0x10000000u
+#define SDHC_IRQSTAT_DMAE_SHIFT                  28
+#define SDHC_IRQSTAT_DMAE_WIDTH                  1
+#define SDHC_IRQSTAT_DMAE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DMAE_SHIFT))&SDHC_IRQSTAT_DMAE_MASK)
+/* IRQSTATEN Bit Fields */
+#define SDHC_IRQSTATEN_CCSEN_MASK                0x1u
+#define SDHC_IRQSTATEN_CCSEN_SHIFT               0
+#define SDHC_IRQSTATEN_CCSEN_WIDTH               1
+#define SDHC_IRQSTATEN_CCSEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCSEN_SHIFT))&SDHC_IRQSTATEN_CCSEN_MASK)
+#define SDHC_IRQSTATEN_TCSEN_MASK                0x2u
+#define SDHC_IRQSTATEN_TCSEN_SHIFT               1
+#define SDHC_IRQSTATEN_TCSEN_WIDTH               1
+#define SDHC_IRQSTATEN_TCSEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_TCSEN_SHIFT))&SDHC_IRQSTATEN_TCSEN_MASK)
+#define SDHC_IRQSTATEN_BGESEN_MASK               0x4u
+#define SDHC_IRQSTATEN_BGESEN_SHIFT              2
+#define SDHC_IRQSTATEN_BGESEN_WIDTH              1
+#define SDHC_IRQSTATEN_BGESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BGESEN_SHIFT))&SDHC_IRQSTATEN_BGESEN_MASK)
+#define SDHC_IRQSTATEN_DINTSEN_MASK              0x8u
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT             3
+#define SDHC_IRQSTATEN_DINTSEN_WIDTH             1
+#define SDHC_IRQSTATEN_DINTSEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DINTSEN_SHIFT))&SDHC_IRQSTATEN_DINTSEN_MASK)
+#define SDHC_IRQSTATEN_BWRSEN_MASK               0x10u
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT              4
+#define SDHC_IRQSTATEN_BWRSEN_WIDTH              1
+#define SDHC_IRQSTATEN_BWRSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BWRSEN_SHIFT))&SDHC_IRQSTATEN_BWRSEN_MASK)
+#define SDHC_IRQSTATEN_BRRSEN_MASK               0x20u
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT              5
+#define SDHC_IRQSTATEN_BRRSEN_WIDTH              1
+#define SDHC_IRQSTATEN_BRRSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BRRSEN_SHIFT))&SDHC_IRQSTATEN_BRRSEN_MASK)
+#define SDHC_IRQSTATEN_CINSEN_MASK               0x40u
+#define SDHC_IRQSTATEN_CINSEN_SHIFT              6
+#define SDHC_IRQSTATEN_CINSEN_WIDTH              1
+#define SDHC_IRQSTATEN_CINSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINSEN_SHIFT))&SDHC_IRQSTATEN_CINSEN_MASK)
+#define SDHC_IRQSTATEN_CRMSEN_MASK               0x80u
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT              7
+#define SDHC_IRQSTATEN_CRMSEN_WIDTH              1
+#define SDHC_IRQSTATEN_CRMSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CRMSEN_SHIFT))&SDHC_IRQSTATEN_CRMSEN_MASK)
+#define SDHC_IRQSTATEN_CINTSEN_MASK              0x100u
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT             8
+#define SDHC_IRQSTATEN_CINTSEN_WIDTH             1
+#define SDHC_IRQSTATEN_CINTSEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINTSEN_SHIFT))&SDHC_IRQSTATEN_CINTSEN_MASK)
+#define SDHC_IRQSTATEN_CTOESEN_MASK              0x10000u
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT             16
+#define SDHC_IRQSTATEN_CTOESEN_WIDTH             1
+#define SDHC_IRQSTATEN_CTOESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CTOESEN_SHIFT))&SDHC_IRQSTATEN_CTOESEN_MASK)
+#define SDHC_IRQSTATEN_CCESEN_MASK               0x20000u
+#define SDHC_IRQSTATEN_CCESEN_SHIFT              17
+#define SDHC_IRQSTATEN_CCESEN_WIDTH              1
+#define SDHC_IRQSTATEN_CCESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCESEN_SHIFT))&SDHC_IRQSTATEN_CCESEN_MASK)
+#define SDHC_IRQSTATEN_CEBESEN_MASK              0x40000u
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT             18
+#define SDHC_IRQSTATEN_CEBESEN_WIDTH             1
+#define SDHC_IRQSTATEN_CEBESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CEBESEN_SHIFT))&SDHC_IRQSTATEN_CEBESEN_MASK)
+#define SDHC_IRQSTATEN_CIESEN_MASK               0x80000u
+#define SDHC_IRQSTATEN_CIESEN_SHIFT              19
+#define SDHC_IRQSTATEN_CIESEN_WIDTH              1
+#define SDHC_IRQSTATEN_CIESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CIESEN_SHIFT))&SDHC_IRQSTATEN_CIESEN_MASK)
+#define SDHC_IRQSTATEN_DTOESEN_MASK              0x100000u
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT             20
+#define SDHC_IRQSTATEN_DTOESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DTOESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DTOESEN_SHIFT))&SDHC_IRQSTATEN_DTOESEN_MASK)
+#define SDHC_IRQSTATEN_DCESEN_MASK               0x200000u
+#define SDHC_IRQSTATEN_DCESEN_SHIFT              21
+#define SDHC_IRQSTATEN_DCESEN_WIDTH              1
+#define SDHC_IRQSTATEN_DCESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DCESEN_SHIFT))&SDHC_IRQSTATEN_DCESEN_MASK)
+#define SDHC_IRQSTATEN_DEBESEN_MASK              0x400000u
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT             22
+#define SDHC_IRQSTATEN_DEBESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DEBESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DEBESEN_SHIFT))&SDHC_IRQSTATEN_DEBESEN_MASK)
+#define SDHC_IRQSTATEN_AC12ESEN_MASK             0x1000000u
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT            24
+#define SDHC_IRQSTATEN_AC12ESEN_WIDTH            1
+#define SDHC_IRQSTATEN_AC12ESEN(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_AC12ESEN_SHIFT))&SDHC_IRQSTATEN_AC12ESEN_MASK)
+#define SDHC_IRQSTATEN_DMAESEN_MASK              0x10000000u
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT             28
+#define SDHC_IRQSTATEN_DMAESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DMAESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DMAESEN_SHIFT))&SDHC_IRQSTATEN_DMAESEN_MASK)
+/* IRQSIGEN Bit Fields */
+#define SDHC_IRQSIGEN_CCIEN_MASK                 0x1u
+#define SDHC_IRQSIGEN_CCIEN_SHIFT                0
+#define SDHC_IRQSIGEN_CCIEN_WIDTH                1
+#define SDHC_IRQSIGEN_CCIEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCIEN_SHIFT))&SDHC_IRQSIGEN_CCIEN_MASK)
+#define SDHC_IRQSIGEN_TCIEN_MASK                 0x2u
+#define SDHC_IRQSIGEN_TCIEN_SHIFT                1
+#define SDHC_IRQSIGEN_TCIEN_WIDTH                1
+#define SDHC_IRQSIGEN_TCIEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_TCIEN_SHIFT))&SDHC_IRQSIGEN_TCIEN_MASK)
+#define SDHC_IRQSIGEN_BGEIEN_MASK                0x4u
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT               2
+#define SDHC_IRQSIGEN_BGEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BGEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BGEIEN_SHIFT))&SDHC_IRQSIGEN_BGEIEN_MASK)
+#define SDHC_IRQSIGEN_DINTIEN_MASK               0x8u
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT              3
+#define SDHC_IRQSIGEN_DINTIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DINTIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DINTIEN_SHIFT))&SDHC_IRQSIGEN_DINTIEN_MASK)
+#define SDHC_IRQSIGEN_BWRIEN_MASK                0x10u
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT               4
+#define SDHC_IRQSIGEN_BWRIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BWRIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BWRIEN_SHIFT))&SDHC_IRQSIGEN_BWRIEN_MASK)
+#define SDHC_IRQSIGEN_BRRIEN_MASK                0x20u
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT               5
+#define SDHC_IRQSIGEN_BRRIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BRRIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BRRIEN_SHIFT))&SDHC_IRQSIGEN_BRRIEN_MASK)
+#define SDHC_IRQSIGEN_CINSIEN_MASK               0x40u
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT              6
+#define SDHC_IRQSIGEN_CINSIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CINSIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINSIEN_SHIFT))&SDHC_IRQSIGEN_CINSIEN_MASK)
+#define SDHC_IRQSIGEN_CRMIEN_MASK                0x80u
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT               7
+#define SDHC_IRQSIGEN_CRMIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CRMIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CRMIEN_SHIFT))&SDHC_IRQSIGEN_CRMIEN_MASK)
+#define SDHC_IRQSIGEN_CINTIEN_MASK               0x100u
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT              8
+#define SDHC_IRQSIGEN_CINTIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CINTIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINTIEN_SHIFT))&SDHC_IRQSIGEN_CINTIEN_MASK)
+#define SDHC_IRQSIGEN_CTOEIEN_MASK               0x10000u
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT              16
+#define SDHC_IRQSIGEN_CTOEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CTOEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CTOEIEN_SHIFT))&SDHC_IRQSIGEN_CTOEIEN_MASK)
+#define SDHC_IRQSIGEN_CCEIEN_MASK                0x20000u
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT               17
+#define SDHC_IRQSIGEN_CCEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CCEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCEIEN_SHIFT))&SDHC_IRQSIGEN_CCEIEN_MASK)
+#define SDHC_IRQSIGEN_CEBEIEN_MASK               0x40000u
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT              18
+#define SDHC_IRQSIGEN_CEBEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CEBEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CEBEIEN_SHIFT))&SDHC_IRQSIGEN_CEBEIEN_MASK)
+#define SDHC_IRQSIGEN_CIEIEN_MASK                0x80000u
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT               19
+#define SDHC_IRQSIGEN_CIEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CIEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CIEIEN_SHIFT))&SDHC_IRQSIGEN_CIEIEN_MASK)
+#define SDHC_IRQSIGEN_DTOEIEN_MASK               0x100000u
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT              20
+#define SDHC_IRQSIGEN_DTOEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DTOEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DTOEIEN_SHIFT))&SDHC_IRQSIGEN_DTOEIEN_MASK)
+#define SDHC_IRQSIGEN_DCEIEN_MASK                0x200000u
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT               21
+#define SDHC_IRQSIGEN_DCEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_DCEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DCEIEN_SHIFT))&SDHC_IRQSIGEN_DCEIEN_MASK)
+#define SDHC_IRQSIGEN_DEBEIEN_MASK               0x400000u
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT              22
+#define SDHC_IRQSIGEN_DEBEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DEBEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DEBEIEN_SHIFT))&SDHC_IRQSIGEN_DEBEIEN_MASK)
+#define SDHC_IRQSIGEN_AC12EIEN_MASK              0x1000000u
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT             24
+#define SDHC_IRQSIGEN_AC12EIEN_WIDTH             1
+#define SDHC_IRQSIGEN_AC12EIEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_AC12EIEN_SHIFT))&SDHC_IRQSIGEN_AC12EIEN_MASK)
+#define SDHC_IRQSIGEN_DMAEIEN_MASK               0x10000000u
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT              28
+#define SDHC_IRQSIGEN_DMAEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DMAEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DMAEIEN_SHIFT))&SDHC_IRQSIGEN_DMAEIEN_MASK)
+/* AC12ERR Bit Fields */
+#define SDHC_AC12ERR_AC12NE_MASK                 0x1u
+#define SDHC_AC12ERR_AC12NE_SHIFT                0
+#define SDHC_AC12ERR_AC12NE_WIDTH                1
+#define SDHC_AC12ERR_AC12NE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12NE_SHIFT))&SDHC_AC12ERR_AC12NE_MASK)
+#define SDHC_AC12ERR_AC12TOE_MASK                0x2u
+#define SDHC_AC12ERR_AC12TOE_SHIFT               1
+#define SDHC_AC12ERR_AC12TOE_WIDTH               1
+#define SDHC_AC12ERR_AC12TOE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12TOE_SHIFT))&SDHC_AC12ERR_AC12TOE_MASK)
+#define SDHC_AC12ERR_AC12EBE_MASK                0x4u
+#define SDHC_AC12ERR_AC12EBE_SHIFT               2
+#define SDHC_AC12ERR_AC12EBE_WIDTH               1
+#define SDHC_AC12ERR_AC12EBE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12EBE_SHIFT))&SDHC_AC12ERR_AC12EBE_MASK)
+#define SDHC_AC12ERR_AC12CE_MASK                 0x8u
+#define SDHC_AC12ERR_AC12CE_SHIFT                3
+#define SDHC_AC12ERR_AC12CE_WIDTH                1
+#define SDHC_AC12ERR_AC12CE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12CE_SHIFT))&SDHC_AC12ERR_AC12CE_MASK)
+#define SDHC_AC12ERR_AC12IE_MASK                 0x10u
+#define SDHC_AC12ERR_AC12IE_SHIFT                4
+#define SDHC_AC12ERR_AC12IE_WIDTH                1
+#define SDHC_AC12ERR_AC12IE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12IE_SHIFT))&SDHC_AC12ERR_AC12IE_MASK)
+#define SDHC_AC12ERR_CNIBAC12E_MASK              0x80u
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT             7
+#define SDHC_AC12ERR_CNIBAC12E_WIDTH             1
+#define SDHC_AC12ERR_CNIBAC12E(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_CNIBAC12E_SHIFT))&SDHC_AC12ERR_CNIBAC12E_MASK)
+/* HTCAPBLT Bit Fields */
+#define SDHC_HTCAPBLT_MBL_MASK                   0x70000u
+#define SDHC_HTCAPBLT_MBL_SHIFT                  16
+#define SDHC_HTCAPBLT_MBL_WIDTH                  3
+#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK                 0x100000u
+#define SDHC_HTCAPBLT_ADMAS_SHIFT                20
+#define SDHC_HTCAPBLT_ADMAS_WIDTH                1
+#define SDHC_HTCAPBLT_ADMAS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_ADMAS_SHIFT))&SDHC_HTCAPBLT_ADMAS_MASK)
+#define SDHC_HTCAPBLT_HSS_MASK                   0x200000u
+#define SDHC_HTCAPBLT_HSS_SHIFT                  21
+#define SDHC_HTCAPBLT_HSS_WIDTH                  1
+#define SDHC_HTCAPBLT_HSS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_HSS_SHIFT))&SDHC_HTCAPBLT_HSS_MASK)
+#define SDHC_HTCAPBLT_DMAS_MASK                  0x400000u
+#define SDHC_HTCAPBLT_DMAS_SHIFT                 22
+#define SDHC_HTCAPBLT_DMAS_WIDTH                 1
+#define SDHC_HTCAPBLT_DMAS(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_DMAS_SHIFT))&SDHC_HTCAPBLT_DMAS_MASK)
+#define SDHC_HTCAPBLT_SRS_MASK                   0x800000u
+#define SDHC_HTCAPBLT_SRS_SHIFT                  23
+#define SDHC_HTCAPBLT_SRS_WIDTH                  1
+#define SDHC_HTCAPBLT_SRS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_SRS_SHIFT))&SDHC_HTCAPBLT_SRS_MASK)
+#define SDHC_HTCAPBLT_VS33_MASK                  0x1000000u
+#define SDHC_HTCAPBLT_VS33_SHIFT                 24
+#define SDHC_HTCAPBLT_VS33_WIDTH                 1
+#define SDHC_HTCAPBLT_VS33(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_VS33_SHIFT))&SDHC_HTCAPBLT_VS33_MASK)
+/* WML Bit Fields */
+#define SDHC_WML_RDWML_MASK                      0xFFu
+#define SDHC_WML_RDWML_SHIFT                     0
+#define SDHC_WML_RDWML_WIDTH                     8
+#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK                      0xFF0000u
+#define SDHC_WML_WRWML_SHIFT                     16
+#define SDHC_WML_WRWML_WIDTH                     8
+#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
+/* FEVT Bit Fields */
+#define SDHC_FEVT_AC12NE_MASK                    0x1u
+#define SDHC_FEVT_AC12NE_SHIFT                   0
+#define SDHC_FEVT_AC12NE_WIDTH                   1
+#define SDHC_FEVT_AC12NE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12NE_SHIFT))&SDHC_FEVT_AC12NE_MASK)
+#define SDHC_FEVT_AC12TOE_MASK                   0x2u
+#define SDHC_FEVT_AC12TOE_SHIFT                  1
+#define SDHC_FEVT_AC12TOE_WIDTH                  1
+#define SDHC_FEVT_AC12TOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12TOE_SHIFT))&SDHC_FEVT_AC12TOE_MASK)
+#define SDHC_FEVT_AC12CE_MASK                    0x4u
+#define SDHC_FEVT_AC12CE_SHIFT                   2
+#define SDHC_FEVT_AC12CE_WIDTH                   1
+#define SDHC_FEVT_AC12CE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12CE_SHIFT))&SDHC_FEVT_AC12CE_MASK)
+#define SDHC_FEVT_AC12EBE_MASK                   0x8u
+#define SDHC_FEVT_AC12EBE_SHIFT                  3
+#define SDHC_FEVT_AC12EBE_WIDTH                  1
+#define SDHC_FEVT_AC12EBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12EBE_SHIFT))&SDHC_FEVT_AC12EBE_MASK)
+#define SDHC_FEVT_AC12IE_MASK                    0x10u
+#define SDHC_FEVT_AC12IE_SHIFT                   4
+#define SDHC_FEVT_AC12IE_WIDTH                   1
+#define SDHC_FEVT_AC12IE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12IE_SHIFT))&SDHC_FEVT_AC12IE_MASK)
+#define SDHC_FEVT_CNIBAC12E_MASK                 0x80u
+#define SDHC_FEVT_CNIBAC12E_SHIFT                7
+#define SDHC_FEVT_CNIBAC12E_WIDTH                1
+#define SDHC_FEVT_CNIBAC12E(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CNIBAC12E_SHIFT))&SDHC_FEVT_CNIBAC12E_MASK)
+#define SDHC_FEVT_CTOE_MASK                      0x10000u
+#define SDHC_FEVT_CTOE_SHIFT                     16
+#define SDHC_FEVT_CTOE_WIDTH                     1
+#define SDHC_FEVT_CTOE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CTOE_SHIFT))&SDHC_FEVT_CTOE_MASK)
+#define SDHC_FEVT_CCE_MASK                       0x20000u
+#define SDHC_FEVT_CCE_SHIFT                      17
+#define SDHC_FEVT_CCE_WIDTH                      1
+#define SDHC_FEVT_CCE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CCE_SHIFT))&SDHC_FEVT_CCE_MASK)
+#define SDHC_FEVT_CEBE_MASK                      0x40000u
+#define SDHC_FEVT_CEBE_SHIFT                     18
+#define SDHC_FEVT_CEBE_WIDTH                     1
+#define SDHC_FEVT_CEBE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CEBE_SHIFT))&SDHC_FEVT_CEBE_MASK)
+#define SDHC_FEVT_CIE_MASK                       0x80000u
+#define SDHC_FEVT_CIE_SHIFT                      19
+#define SDHC_FEVT_CIE_WIDTH                      1
+#define SDHC_FEVT_CIE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CIE_SHIFT))&SDHC_FEVT_CIE_MASK)
+#define SDHC_FEVT_DTOE_MASK                      0x100000u
+#define SDHC_FEVT_DTOE_SHIFT                     20
+#define SDHC_FEVT_DTOE_WIDTH                     1
+#define SDHC_FEVT_DTOE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DTOE_SHIFT))&SDHC_FEVT_DTOE_MASK)
+#define SDHC_FEVT_DCE_MASK                       0x200000u
+#define SDHC_FEVT_DCE_SHIFT                      21
+#define SDHC_FEVT_DCE_WIDTH                      1
+#define SDHC_FEVT_DCE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DCE_SHIFT))&SDHC_FEVT_DCE_MASK)
+#define SDHC_FEVT_DEBE_MASK                      0x400000u
+#define SDHC_FEVT_DEBE_SHIFT                     22
+#define SDHC_FEVT_DEBE_WIDTH                     1
+#define SDHC_FEVT_DEBE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DEBE_SHIFT))&SDHC_FEVT_DEBE_MASK)
+#define SDHC_FEVT_AC12E_MASK                     0x1000000u
+#define SDHC_FEVT_AC12E_SHIFT                    24
+#define SDHC_FEVT_AC12E_WIDTH                    1
+#define SDHC_FEVT_AC12E(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12E_SHIFT))&SDHC_FEVT_AC12E_MASK)
+#define SDHC_FEVT_DMAE_MASK                      0x10000000u
+#define SDHC_FEVT_DMAE_SHIFT                     28
+#define SDHC_FEVT_DMAE_WIDTH                     1
+#define SDHC_FEVT_DMAE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DMAE_SHIFT))&SDHC_FEVT_DMAE_MASK)
+#define SDHC_FEVT_CINT_MASK                      0x80000000u
+#define SDHC_FEVT_CINT_SHIFT                     31
+#define SDHC_FEVT_CINT_WIDTH                     1
+#define SDHC_FEVT_CINT(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CINT_SHIFT))&SDHC_FEVT_CINT_MASK)
+/* ADMAES Bit Fields */
+#define SDHC_ADMAES_ADMAES_MASK                  0x3u
+#define SDHC_ADMAES_ADMAES_SHIFT                 0
+#define SDHC_ADMAES_ADMAES_WIDTH                 2
+#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK                 0x4u
+#define SDHC_ADMAES_ADMALME_SHIFT                2
+#define SDHC_ADMAES_ADMALME_WIDTH                1
+#define SDHC_ADMAES_ADMALME(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMALME_SHIFT))&SDHC_ADMAES_ADMALME_MASK)
+#define SDHC_ADMAES_ADMADCE_MASK                 0x8u
+#define SDHC_ADMAES_ADMADCE_SHIFT                3
+#define SDHC_ADMAES_ADMADCE_WIDTH                1
+#define SDHC_ADMAES_ADMADCE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMADCE_SHIFT))&SDHC_ADMAES_ADMADCE_MASK)
+/* ADSADDR Bit Fields */
+#define SDHC_ADSADDR_ADSADDR_MASK                0xFFFFFFFCu
+#define SDHC_ADSADDR_ADSADDR_SHIFT               2
+#define SDHC_ADSADDR_ADSADDR_WIDTH               30
+#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
+/* VENDOR Bit Fields */
+#define SDHC_VENDOR_EXTDMAEN_MASK                0x1u
+#define SDHC_VENDOR_EXTDMAEN_SHIFT               0
+#define SDHC_VENDOR_EXTDMAEN_WIDTH               1
+#define SDHC_VENDOR_EXTDMAEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXTDMAEN_SHIFT))&SDHC_VENDOR_EXTDMAEN_MASK)
+#define SDHC_VENDOR_EXBLKNU_MASK                 0x2u
+#define SDHC_VENDOR_EXBLKNU_SHIFT                1
+#define SDHC_VENDOR_EXBLKNU_WIDTH                1
+#define SDHC_VENDOR_EXBLKNU(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXBLKNU_SHIFT))&SDHC_VENDOR_EXBLKNU_MASK)
+#define SDHC_VENDOR_INTSTVAL_MASK                0xFF0000u
+#define SDHC_VENDOR_INTSTVAL_SHIFT               16
+#define SDHC_VENDOR_INTSTVAL_WIDTH               8
+#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
+/* MMCBOOT Bit Fields */
+#define SDHC_MMCBOOT_DTOCVACK_MASK               0xFu
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT              0
+#define SDHC_MMCBOOT_DTOCVACK_WIDTH              4
+#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK                0x10u
+#define SDHC_MMCBOOT_BOOTACK_SHIFT               4
+#define SDHC_MMCBOOT_BOOTACK_WIDTH               1
+#define SDHC_MMCBOOT_BOOTACK(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTACK_SHIFT))&SDHC_MMCBOOT_BOOTACK_MASK)
+#define SDHC_MMCBOOT_BOOTMODE_MASK               0x20u
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT              5
+#define SDHC_MMCBOOT_BOOTMODE_WIDTH              1
+#define SDHC_MMCBOOT_BOOTMODE(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTMODE_SHIFT))&SDHC_MMCBOOT_BOOTMODE_MASK)
+#define SDHC_MMCBOOT_BOOTEN_MASK                 0x40u
+#define SDHC_MMCBOOT_BOOTEN_SHIFT                6
+#define SDHC_MMCBOOT_BOOTEN_WIDTH                1
+#define SDHC_MMCBOOT_BOOTEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTEN_SHIFT))&SDHC_MMCBOOT_BOOTEN_MASK)
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK             0x80u
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            7
+#define SDHC_MMCBOOT_AUTOSABGEN_WIDTH            1
+#define SDHC_MMCBOOT_AUTOSABGEN(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_AUTOSABGEN_SHIFT))&SDHC_MMCBOOT_AUTOSABGEN_MASK)
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             0xFFFF0000u
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            16
+#define SDHC_MMCBOOT_BOOTBLKCNT_WIDTH            16
+#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+/* HOSTVER Bit Fields */
+#define SDHC_HOSTVER_SVN_MASK                    0xFFu
+#define SDHC_HOSTVER_SVN_SHIFT                   0
+#define SDHC_HOSTVER_SVN_WIDTH                   8
+#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK                    0xFF00u
+#define SDHC_HOSTVER_VVN_SHIFT                   8
+#define SDHC_HOSTVER_VVN_WIDTH                   8
+#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/** Peripheral SDHC base address */
+#define SDHC_BASE                                (0x400B1000u)
+/** Peripheral SDHC base pointer */
+#define SDHC                                     ((SDHC_Type *)SDHC_BASE)
+#define SDHC_BASE_PTR                            (SDHC)
+/** Array initializer of SDHC peripheral base addresses */
+#define SDHC_BASE_ADDRS                          { SDHC_BASE }
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASE_PTRS                           { SDHC }
+/** Interrupt vectors for the SDHC peripheral type */
+#define SDHC_IRQS                                { SDHC_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register instance definitions */
+/* SDHC */
+#define SDHC_DSADDR                              SDHC_DSADDR_REG(SDHC)
+#define SDHC_BLKATTR                             SDHC_BLKATTR_REG(SDHC)
+#define SDHC_CMDARG                              SDHC_CMDARG_REG(SDHC)
+#define SDHC_XFERTYP                             SDHC_XFERTYP_REG(SDHC)
+#define SDHC_CMDRSP0                             SDHC_CMDRSP_REG(SDHC,0)
+#define SDHC_CMDRSP1                             SDHC_CMDRSP_REG(SDHC,1)
+#define SDHC_CMDRSP2                             SDHC_CMDRSP_REG(SDHC,2)
+#define SDHC_CMDRSP3                             SDHC_CMDRSP_REG(SDHC,3)
+#define SDHC_DATPORT                             SDHC_DATPORT_REG(SDHC)
+#define SDHC_PRSSTAT                             SDHC_PRSSTAT_REG(SDHC)
+#define SDHC_PROCTL                              SDHC_PROCTL_REG(SDHC)
+#define SDHC_SYSCTL                              SDHC_SYSCTL_REG(SDHC)
+#define SDHC_IRQSTAT                             SDHC_IRQSTAT_REG(SDHC)
+#define SDHC_IRQSTATEN                           SDHC_IRQSTATEN_REG(SDHC)
+#define SDHC_IRQSIGEN                            SDHC_IRQSIGEN_REG(SDHC)
+#define SDHC_AC12ERR                             SDHC_AC12ERR_REG(SDHC)
+#define SDHC_HTCAPBLT                            SDHC_HTCAPBLT_REG(SDHC)
+#define SDHC_WML                                 SDHC_WML_REG(SDHC)
+#define SDHC_FEVT                                SDHC_FEVT_REG(SDHC)
+#define SDHC_ADMAES                              SDHC_ADMAES_REG(SDHC)
+#define SDHC_ADSADDR                             SDHC_ADSADDR_REG(SDHC)
+#define SDHC_VENDOR                              SDHC_VENDOR_REG(SDHC)
+#define SDHC_MMCBOOT                             SDHC_MMCBOOT_REG(SDHC)
+#define SDHC_HOSTVER                             SDHC_HOSTVER_REG(SDHC)
+
+/* SDHC - Register array accessors */
+#define SDHC_CMDRSP(index)                       SDHC_CMDRSP_REG(SDHC,index)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
+       uint8_t RESERVED_0[4092];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+  __IO uint32_t SCGC1;                             /**< System Clock Gating Control Register 1, offset: 0x1028 */
+  __IO uint32_t SCGC2;                             /**< System Clock Gating Control Register 2, offset: 0x102C */
+  __IO uint32_t SCGC3;                             /**< System Clock Gating Control Register 3, offset: 0x1030 */
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+  __IO uint32_t CLKDIV2;                           /**< System Clock Divider Register 2, offset: 0x1048 */
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+  __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base)                      ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base)                   ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base)                      ((base)->SOPT2)
+#define SIM_SOPT4_REG(base)                      ((base)->SOPT4)
+#define SIM_SOPT5_REG(base)                      ((base)->SOPT5)
+#define SIM_SOPT7_REG(base)                      ((base)->SOPT7)
+#define SIM_SDID_REG(base)                       ((base)->SDID)
+#define SIM_SCGC1_REG(base)                      ((base)->SCGC1)
+#define SIM_SCGC2_REG(base)                      ((base)->SCGC2)
+#define SIM_SCGC3_REG(base)                      ((base)->SCGC3)
+#define SIM_SCGC4_REG(base)                      ((base)->SCGC4)
+#define SIM_SCGC5_REG(base)                      ((base)->SCGC5)
+#define SIM_SCGC6_REG(base)                      ((base)->SCGC6)
+#define SIM_SCGC7_REG(base)                      ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base)                    ((base)->CLKDIV1)
+#define SIM_CLKDIV2_REG(base)                    ((base)->CLKDIV2)
+#define SIM_FCFG1_REG(base)                      ((base)->FCFG1)
+#define SIM_FCFG2_REG(base)                      ((base)->FCFG2)
+#define SIM_UIDH_REG(base)                       ((base)->UIDH)
+#define SIM_UIDMH_REG(base)                      ((base)->UIDMH)
+#define SIM_UIDML_REG(base)                      ((base)->UIDML)
+#define SIM_UIDL_REG(base)                       ((base)->UIDL)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK                   0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT                  12
+#define SIM_SOPT1_RAMSIZE_WIDTH                  4
+#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT                18
+#define SIM_SOPT1_OSC32KSEL_WIDTH                2
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK                  0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT                 29
+#define SIM_SOPT1_USBVSTBY_WIDTH                 1
+#define SIM_SOPT1_USBVSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBVSTBY_SHIFT))&SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK                  0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT                 30
+#define SIM_SOPT1_USBSSTBY_WIDTH                 1
+#define SIM_SOPT1_USBSSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBSSTBY_SHIFT))&SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK                  0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT                 31
+#define SIM_SOPT1_USBREGEN_WIDTH                 1
+#define SIM_SOPT1_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBREGEN_SHIFT))&SIM_SOPT1_USBREGEN_MASK)
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK                   0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT                  24
+#define SIM_SOPT1CFG_URWE_WIDTH                  1
+#define SIM_SOPT1CFG_URWE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_URWE_SHIFT))&SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK                  0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT                 25
+#define SIM_SOPT1CFG_UVSWE_WIDTH                 1
+#define SIM_SOPT1CFG_UVSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_UVSWE_SHIFT))&SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK                  0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT                 26
+#define SIM_SOPT1CFG_USSWE_WIDTH                 1
+#define SIM_SOPT1CFG_USSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_USSWE_SHIFT))&SIM_SOPT1CFG_USSWE_MASK)
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
+#define SIM_SOPT2_RTCCLKOUTSEL_WIDTH             1
+#define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                5
+#define SIM_SOPT2_CLKOUTSEL_WIDTH                3
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK                      0x300u
+#define SIM_SOPT2_FBSL_SHIFT                     8
+#define SIM_SOPT2_FBSL_WIDTH                     2
+#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK                   0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT                  11
+#define SIM_SOPT2_PTD7PAD_WIDTH                  1
+#define SIM_SOPT2_PTD7PAD(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PTD7PAD_SHIFT))&SIM_SOPT2_PTD7PAD_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK               0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT              12
+#define SIM_SOPT2_TRACECLKSEL_WIDTH              1
+#define SIM_SOPT2_TRACECLKSEL(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TRACECLKSEL_SHIFT))&SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK                 0x30000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                16
+#define SIM_SOPT2_PLLFLLSEL_WIDTH                2
+#define SIM_SOPT2_PLLFLLSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK                    0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT                   18
+#define SIM_SOPT2_USBSRC_WIDTH                   1
+#define SIM_SOPT2_USBSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_RMIISRC_MASK                   0x80000u
+#define SIM_SOPT2_RMIISRC_SHIFT                  19
+#define SIM_SOPT2_RMIISRC_WIDTH                  1
+#define SIM_SOPT2_RMIISRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RMIISRC_SHIFT))&SIM_SOPT2_RMIISRC_MASK)
+#define SIM_SOPT2_TIMESRC_MASK                   0x300000u
+#define SIM_SOPT2_TIMESRC_SHIFT                  20
+#define SIM_SOPT2_TIMESRC_WIDTH                  2
+#define SIM_SOPT2_TIMESRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK                   0x30000000u
+#define SIM_SOPT2_SDHCSRC_SHIFT                  28
+#define SIM_SOPT2_SDHCSRC_WIDTH                  2
+#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK                  0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT                 0
+#define SIM_SOPT4_FTM0FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT0_SHIFT))&SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK                  0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT                 1
+#define SIM_SOPT4_FTM0FLT1_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT1_SHIFT))&SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM0FLT2_MASK                  0x4u
+#define SIM_SOPT4_FTM0FLT2_SHIFT                 2
+#define SIM_SOPT4_FTM0FLT2_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT2(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT2_SHIFT))&SIM_SOPT4_FTM0FLT2_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK                  0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT                 4
+#define SIM_SOPT4_FTM1FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM1FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1FLT0_SHIFT))&SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_MASK                  0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT                 8
+#define SIM_SOPT4_FTM2FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM2FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2FLT0_SHIFT))&SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM3FLT0_MASK                  0x1000u
+#define SIM_SOPT4_FTM3FLT0_SHIFT                 12
+#define SIM_SOPT4_FTM3FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM3FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3FLT0_SHIFT))&SIM_SOPT4_FTM3FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK                0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT               18
+#define SIM_SOPT4_FTM1CH0SRC_WIDTH               2
+#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK                0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT               20
+#define SIM_SOPT4_FTM2CH0SRC_WIDTH               2
+#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK                0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT               24
+#define SIM_SOPT4_FTM0CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0CLKSEL_SHIFT))&SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK                0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT               25
+#define SIM_SOPT4_FTM1CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CLKSEL_SHIFT))&SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_MASK                0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT               26
+#define SIM_SOPT4_FTM2CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CLKSEL_SHIFT))&SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM3CLKSEL_MASK                0x8000000u
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT               27
+#define SIM_SOPT4_FTM3CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM3CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3CLKSEL_SHIFT))&SIM_SOPT4_FTM3CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK               0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT              28
+#define SIM_SOPT4_FTM0TRG0SRC_WIDTH              1
+#define SIM_SOPT4_FTM0TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG0SRC_SHIFT))&SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_MASK               0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT              29
+#define SIM_SOPT4_FTM0TRG1SRC_WIDTH              1
+#define SIM_SOPT4_FTM0TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG1SRC_SHIFT))&SIM_SOPT4_FTM0TRG1SRC_MASK)
+#define SIM_SOPT4_FTM3TRG0SRC_MASK               0x40000000u
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT              30
+#define SIM_SOPT4_FTM3TRG0SRC_WIDTH              1
+#define SIM_SOPT4_FTM3TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG0SRC_SHIFT))&SIM_SOPT4_FTM3TRG0SRC_MASK)
+#define SIM_SOPT4_FTM3TRG1SRC_MASK               0x80000000u
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT              31
+#define SIM_SOPT4_FTM3TRG1SRC_WIDTH              1
+#define SIM_SOPT4_FTM3TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG1SRC_SHIFT))&SIM_SOPT4_FTM3TRG1SRC_MASK)
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK                0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT               0
+#define SIM_SOPT5_UART0TXSRC_WIDTH               2
+#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK                0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT               2
+#define SIM_SOPT5_UART0RXSRC_WIDTH               2
+#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK                0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT               4
+#define SIM_SOPT5_UART1TXSRC_WIDTH               2
+#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK                0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT               6
+#define SIM_SOPT5_UART1RXSRC_WIDTH               2
+#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
+#define SIM_SOPT7_ADC0TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
+#define SIM_SOPT7_ADC0PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
+#define SIM_SOPT7_ADC0ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_MASK                0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT               8
+#define SIM_SOPT7_ADC1TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK             0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            12
+#define SIM_SOPT7_ADC1PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC1PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1PRETRGSEL_SHIFT))&SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK              0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             15
+#define SIM_SOPT7_ADC1ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC1ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1ALTTRGEN_SHIFT))&SIM_SOPT7_ADC1ALTTRGEN_MASK)
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK                      0xFu
+#define SIM_SDID_PINID_SHIFT                     0
+#define SIM_SDID_PINID_WIDTH                     4
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK                      0x70u
+#define SIM_SDID_FAMID_SHIFT                     4
+#define SIM_SDID_FAMID_WIDTH                     3
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK                      0xF80u
+#define SIM_SDID_DIEID_SHIFT                     7
+#define SIM_SDID_DIEID_WIDTH                     5
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      0xF000u
+#define SIM_SDID_REVID_SHIFT                     12
+#define SIM_SDID_REVID_WIDTH                     4
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK                   0xF00000u
+#define SIM_SDID_SERIESID_SHIFT                  20
+#define SIM_SDID_SERIESID_WIDTH                  4
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT                  24
+#define SIM_SDID_SUBFAMID_WIDTH                  4
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK                   0xF0000000u
+#define SIM_SDID_FAMILYID_SHIFT                  28
+#define SIM_SDID_FAMILYID_WIDTH                  4
+#define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
+/* SCGC1 Bit Fields */
+#define SIM_SCGC1_I2C2_MASK                      0x40u
+#define SIM_SCGC1_I2C2_SHIFT                     6
+#define SIM_SCGC1_I2C2_WIDTH                     1
+#define SIM_SCGC1_I2C2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_I2C2_SHIFT))&SIM_SCGC1_I2C2_MASK)
+#define SIM_SCGC1_UART4_MASK                     0x400u
+#define SIM_SCGC1_UART4_SHIFT                    10
+#define SIM_SCGC1_UART4_WIDTH                    1
+#define SIM_SCGC1_UART4(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART4_SHIFT))&SIM_SCGC1_UART4_MASK)
+#define SIM_SCGC1_UART5_MASK                     0x800u
+#define SIM_SCGC1_UART5_SHIFT                    11
+#define SIM_SCGC1_UART5_WIDTH                    1
+#define SIM_SCGC1_UART5(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART5_SHIFT))&SIM_SCGC1_UART5_MASK)
+/* SCGC2 Bit Fields */
+#define SIM_SCGC2_ENET_MASK                      0x1u
+#define SIM_SCGC2_ENET_SHIFT                     0
+#define SIM_SCGC2_ENET_WIDTH                     1
+#define SIM_SCGC2_ENET(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_ENET_SHIFT))&SIM_SCGC2_ENET_MASK)
+#define SIM_SCGC2_DAC0_MASK                      0x1000u
+#define SIM_SCGC2_DAC0_SHIFT                     12
+#define SIM_SCGC2_DAC0_WIDTH                     1
+#define SIM_SCGC2_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC0_SHIFT))&SIM_SCGC2_DAC0_MASK)
+#define SIM_SCGC2_DAC1_MASK                      0x2000u
+#define SIM_SCGC2_DAC1_SHIFT                     13
+#define SIM_SCGC2_DAC1_WIDTH                     1
+#define SIM_SCGC2_DAC1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC1_SHIFT))&SIM_SCGC2_DAC1_MASK)
+/* SCGC3 Bit Fields */
+#define SIM_SCGC3_RNGA_MASK                      0x1u
+#define SIM_SCGC3_RNGA_SHIFT                     0
+#define SIM_SCGC3_RNGA_WIDTH                     1
+#define SIM_SCGC3_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_RNGA_SHIFT))&SIM_SCGC3_RNGA_MASK)
+#define SIM_SCGC3_SPI2_MASK                      0x1000u
+#define SIM_SCGC3_SPI2_SHIFT                     12
+#define SIM_SCGC3_SPI2_WIDTH                     1
+#define SIM_SCGC3_SPI2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SPI2_SHIFT))&SIM_SCGC3_SPI2_MASK)
+#define SIM_SCGC3_SDHC_MASK                      0x20000u
+#define SIM_SCGC3_SDHC_SHIFT                     17
+#define SIM_SCGC3_SDHC_WIDTH                     1
+#define SIM_SCGC3_SDHC(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SDHC_SHIFT))&SIM_SCGC3_SDHC_MASK)
+#define SIM_SCGC3_FTM2_MASK                      0x1000000u
+#define SIM_SCGC3_FTM2_SHIFT                     24
+#define SIM_SCGC3_FTM2_WIDTH                     1
+#define SIM_SCGC3_FTM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM2_SHIFT))&SIM_SCGC3_FTM2_MASK)
+#define SIM_SCGC3_FTM3_MASK                      0x2000000u
+#define SIM_SCGC3_FTM3_SHIFT                     25
+#define SIM_SCGC3_FTM3_WIDTH                     1
+#define SIM_SCGC3_FTM3(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM3_SHIFT))&SIM_SCGC3_FTM3_MASK)
+#define SIM_SCGC3_ADC1_MASK                      0x8000000u
+#define SIM_SCGC3_ADC1_SHIFT                     27
+#define SIM_SCGC3_ADC1_WIDTH                     1
+#define SIM_SCGC3_ADC1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_ADC1_SHIFT))&SIM_SCGC3_ADC1_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK                       0x2u
+#define SIM_SCGC4_EWM_SHIFT                      1
+#define SIM_SCGC4_EWM_WIDTH                      1
+#define SIM_SCGC4_EWM(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_EWM_SHIFT))&SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_CMT_MASK                       0x4u
+#define SIM_SCGC4_CMT_SHIFT                      2
+#define SIM_SCGC4_CMT_WIDTH                      1
+#define SIM_SCGC4_CMT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMT_SHIFT))&SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_I2C0_MASK                      0x40u
+#define SIM_SCGC4_I2C0_SHIFT                     6
+#define SIM_SCGC4_I2C0_WIDTH                     1
+#define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C0_SHIFT))&SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK                      0x80u
+#define SIM_SCGC4_I2C1_SHIFT                     7
+#define SIM_SCGC4_I2C1_WIDTH                     1
+#define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C1_SHIFT))&SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK                     0x400u
+#define SIM_SCGC4_UART0_SHIFT                    10
+#define SIM_SCGC4_UART0_WIDTH                    1
+#define SIM_SCGC4_UART0(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART0_SHIFT))&SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK                     0x800u
+#define SIM_SCGC4_UART1_SHIFT                    11
+#define SIM_SCGC4_UART1_WIDTH                    1
+#define SIM_SCGC4_UART1(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART1_SHIFT))&SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK                     0x1000u
+#define SIM_SCGC4_UART2_SHIFT                    12
+#define SIM_SCGC4_UART2_WIDTH                    1
+#define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_UART3_MASK                     0x2000u
+#define SIM_SCGC4_UART3_SHIFT                    13
+#define SIM_SCGC4_UART3_WIDTH                    1
+#define SIM_SCGC4_UART3(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART3_SHIFT))&SIM_SCGC4_UART3_MASK)
+#define SIM_SCGC4_USBOTG_MASK                    0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT                   18
+#define SIM_SCGC4_USBOTG_WIDTH                   1
+#define SIM_SCGC4_USBOTG(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBOTG_SHIFT))&SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK                       0x80000u
+#define SIM_SCGC4_CMP_SHIFT                      19
+#define SIM_SCGC4_CMP_WIDTH                      1
+#define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK                      0x100000u
+#define SIM_SCGC4_VREF_SHIFT                     20
+#define SIM_SCGC4_VREF_WIDTH                     1
+#define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_VREF_SHIFT))&SIM_SCGC4_VREF_MASK)
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK                     0x1u
+#define SIM_SCGC5_LPTMR_SHIFT                    0
+#define SIM_SCGC5_LPTMR_WIDTH                    1
+#define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_PORTA_MASK                     0x200u
+#define SIM_SCGC5_PORTA_SHIFT                    9
+#define SIM_SCGC5_PORTA_WIDTH                    1
+#define SIM_SCGC5_PORTA(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK                     0x400u
+#define SIM_SCGC5_PORTB_SHIFT                    10
+#define SIM_SCGC5_PORTB_WIDTH                    1
+#define SIM_SCGC5_PORTB(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK                     0x800u
+#define SIM_SCGC5_PORTC_SHIFT                    11
+#define SIM_SCGC5_PORTC_WIDTH                    1
+#define SIM_SCGC5_PORTC(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK                     0x1000u
+#define SIM_SCGC5_PORTD_SHIFT                    12
+#define SIM_SCGC5_PORTD_WIDTH                    1
+#define SIM_SCGC5_PORTD(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK                     0x2000u
+#define SIM_SCGC5_PORTE_SHIFT                    13
+#define SIM_SCGC5_PORTE_WIDTH                    1
+#define SIM_SCGC5_PORTE(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK                       0x1u
+#define SIM_SCGC6_FTF_SHIFT                      0
+#define SIM_SCGC6_FTF_WIDTH                      1
+#define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK                    0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT                   1
+#define SIM_SCGC6_DMAMUX_WIDTH                   1
+#define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_FLEXCAN0_MASK                  0x10u
+#define SIM_SCGC6_FLEXCAN0_SHIFT                 4
+#define SIM_SCGC6_FLEXCAN0_WIDTH                 1
+#define SIM_SCGC6_FLEXCAN0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FLEXCAN0_SHIFT))&SIM_SCGC6_FLEXCAN0_MASK)
+#define SIM_SCGC6_RNGA_MASK                      0x200u
+#define SIM_SCGC6_RNGA_SHIFT                     9
+#define SIM_SCGC6_RNGA_WIDTH                     1
+#define SIM_SCGC6_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RNGA_SHIFT))&SIM_SCGC6_RNGA_MASK)
+#define SIM_SCGC6_SPI0_MASK                      0x1000u
+#define SIM_SCGC6_SPI0_SHIFT                     12
+#define SIM_SCGC6_SPI0_WIDTH                     1
+#define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI0_SHIFT))&SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK                      0x2000u
+#define SIM_SCGC6_SPI1_SHIFT                     13
+#define SIM_SCGC6_SPI1_WIDTH                     1
+#define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI1_SHIFT))&SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_I2S_MASK                       0x8000u
+#define SIM_SCGC6_I2S_SHIFT                      15
+#define SIM_SCGC6_I2S_WIDTH                      1
+#define SIM_SCGC6_I2S(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S_SHIFT))&SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK                       0x40000u
+#define SIM_SCGC6_CRC_SHIFT                      18
+#define SIM_SCGC6_CRC_WIDTH                      1
+#define SIM_SCGC6_CRC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_CRC_SHIFT))&SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_USBDCD_MASK                    0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT                   21
+#define SIM_SCGC6_USBDCD_WIDTH                   1
+#define SIM_SCGC6_USBDCD(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_USBDCD_SHIFT))&SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_PDB_MASK                       0x400000u
+#define SIM_SCGC6_PDB_SHIFT                      22
+#define SIM_SCGC6_PDB_WIDTH                      1
+#define SIM_SCGC6_PDB(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PDB_SHIFT))&SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK                       0x800000u
+#define SIM_SCGC6_PIT_SHIFT                      23
+#define SIM_SCGC6_PIT_WIDTH                      1
+#define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK                      0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT                     24
+#define SIM_SCGC6_FTM0_WIDTH                     1
+#define SIM_SCGC6_FTM0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM0_SHIFT))&SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK                      0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT                     25
+#define SIM_SCGC6_FTM1_WIDTH                     1
+#define SIM_SCGC6_FTM1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM1_SHIFT))&SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM2_MASK                      0x4000000u
+#define SIM_SCGC6_FTM2_SHIFT                     26
+#define SIM_SCGC6_FTM2_WIDTH                     1
+#define SIM_SCGC6_FTM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM2_SHIFT))&SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_ADC0_MASK                      0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT                     27
+#define SIM_SCGC6_ADC0_WIDTH                     1
+#define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK                       0x20000000u
+#define SIM_SCGC6_RTC_SHIFT                      29
+#define SIM_SCGC6_RTC_WIDTH                      1
+#define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK                      0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT                     31
+#define SIM_SCGC6_DAC0_WIDTH                     1
+#define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_FLEXBUS_MASK                   0x1u
+#define SIM_SCGC7_FLEXBUS_SHIFT                  0
+#define SIM_SCGC7_FLEXBUS_WIDTH                  1
+#define SIM_SCGC7_FLEXBUS(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_FLEXBUS_SHIFT))&SIM_SCGC7_FLEXBUS_MASK)
+#define SIM_SCGC7_DMA_MASK                       0x2u
+#define SIM_SCGC7_DMA_SHIFT                      1
+#define SIM_SCGC7_DMA_WIDTH                      1
+#define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_MPU_MASK                       0x4u
+#define SIM_SCGC7_MPU_SHIFT                      2
+#define SIM_SCGC7_MPU_WIDTH                      1
+#define SIM_SCGC7_MPU(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_MPU_SHIFT))&SIM_SCGC7_MPU_MASK)
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
+#define SIM_CLKDIV1_OUTDIV4_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK                 0xF00000u
+#define SIM_CLKDIV1_OUTDIV3_SHIFT                20
+#define SIM_CLKDIV1_OUTDIV3_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV3(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK                 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT                24
+#define SIM_CLKDIV1_OUTDIV2_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
+#define SIM_CLKDIV1_OUTDIV1_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK                 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT                0
+#define SIM_CLKDIV2_USBFRAC_WIDTH                1
+#define SIM_CLKDIV2_USBFRAC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBFRAC_SHIFT))&SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK                  0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT                 1
+#define SIM_CLKDIV2_USBDIV_WIDTH                 3
+#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK                  0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT                 0
+#define SIM_FCFG1_FLASHDIS_WIDTH                 1
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT                1
+#define SIM_FCFG1_FLASHDOZE_WIDTH                1
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_DEPART_MASK                    0xF00u
+#define SIM_FCFG1_DEPART_SHIFT                   8
+#define SIM_FCFG1_DEPART_WIDTH                   4
+#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK                    0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT                   16
+#define SIM_FCFG1_EESIZE_WIDTH                   4
+#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT                   24
+#define SIM_FCFG1_PFSIZE_WIDTH                   4
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK                   0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT                  28
+#define SIM_FCFG1_NVMSIZE_WIDTH                  4
+#define SIM_FCFG1_NVMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK                  0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT                 16
+#define SIM_FCFG2_MAXADDR1_WIDTH                 7
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK                     0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT                    23
+#define SIM_FCFG2_PFLSH_WIDTH                    1
+#define SIM_FCFG2_PFLSH(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_PFLSH_SHIFT))&SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK                  0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT                 24
+#define SIM_FCFG2_MAXADDR0_WIDTH                 7
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT                       0
+#define SIM_UIDH_UID_WIDTH                       32
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT                      0
+#define SIM_UIDMH_UID_WIDTH                      32
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT                      0
+#define SIM_UIDML_UID_WIDTH                      32
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT                       0
+#define SIM_UIDL_UID_WIDTH                       32
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR                             (SIM)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1                                SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG                             SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2                                SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4                                SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5                                SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7                                SIM_SOPT7_REG(SIM)
+#define SIM_SDID                                 SIM_SDID_REG(SIM)
+#define SIM_SCGC1                                SIM_SCGC1_REG(SIM)
+#define SIM_SCGC2                                SIM_SCGC2_REG(SIM)
+#define SIM_SCGC3                                SIM_SCGC3_REG(SIM)
+#define SIM_SCGC4                                SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5                                SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6                                SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7                                SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1                              SIM_CLKDIV1_REG(SIM)
+#define SIM_CLKDIV2                              SIM_CLKDIV2_REG(SIM)
+#define SIM_FCFG1                                SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2                                SIM_FCFG2_REG(SIM)
+#define SIM_UIDH                                 SIM_UIDH_REG(SIM)
+#define SIM_UIDMH                                SIM_UIDMH_REG(SIM)
+#define SIM_UIDML                                SIM_UIDML_REG(SIM)
+#define SIM_UIDL                                 SIM_UIDL_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t VLLSCTRL;                           /**< VLLS Control register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base)                     ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base)                     ((base)->PMCTRL)
+#define SMC_VLLSCTRL_REG(base)                   ((base)->VLLSCTRL)
+#define SMC_PMSTAT_REG(base)                     ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK                    0x2u
+#define SMC_PMPROT_AVLLS_SHIFT                   1
+#define SMC_PMPROT_AVLLS_WIDTH                   1
+#define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK                     0x8u
+#define SMC_PMPROT_ALLS_SHIFT                    3
+#define SMC_PMPROT_ALLS_WIDTH                    1
+#define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK                     0x20u
+#define SMC_PMPROT_AVLP_SHIFT                    5
+#define SMC_PMPROT_AVLP_WIDTH                    1
+#define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK                    0x7u
+#define SMC_PMCTRL_STOPM_SHIFT                   0
+#define SMC_PMCTRL_STOPM_WIDTH                   3
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK                    0x8u
+#define SMC_PMCTRL_STOPA_SHIFT                   3
+#define SMC_PMCTRL_STOPA_WIDTH                   1
+#define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK                     0x60u
+#define SMC_PMCTRL_RUNM_SHIFT                    5
+#define SMC_PMCTRL_RUNM_WIDTH                    2
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK                    0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT                   7
+#define SMC_PMCTRL_LPWUI_WIDTH                   1
+#define SMC_PMCTRL_LPWUI(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_LPWUI_SHIFT))&SMC_PMCTRL_LPWUI_MASK)
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK                  0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT                 0
+#define SMC_VLLSCTRL_VLLSM_WIDTH                 3
+#define SMC_VLLSCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK                  0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT                 5
+#define SMC_VLLSCTRL_PORPO_WIDTH                 1
+#define SMC_VLLSCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_PORPO_SHIFT))&SMC_VLLSCTRL_PORPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK                   0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT                  0
+#define SMC_PMSTAT_PMSTAT_WIDTH                  7
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR                             (SMC)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC }
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT                               SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL                               SMC_PMCTRL_REG(SMC)
+#define SMC_VLLSCTRL                             SMC_VLLSCTRL_REG(SMC)
+#define SMC_PMSTAT                               SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+    __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+  };
+       uint8_t RESERVED_1[24];
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
+  __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+  union {                                          /* offset: 0x34 */
+    __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+    __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+  };
+  __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
+  __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
+  __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
+  __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
+  __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
+       uint8_t RESERVED_2[48];
+  __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
+  __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
+  __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
+  __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_MCR_REG(base)                        ((base)->MCR)
+#define SPI_TCR_REG(base)                        ((base)->TCR)
+#define SPI_CTAR_REG(base,index2)                ((base)->CTAR[index2])
+#define SPI_CTAR_COUNT                           2
+#define SPI_CTAR_SLAVE_REG(base,index2)          ((base)->CTAR_SLAVE[index2])
+#define SPI_CTAR_SLAVE_COUNT                     1
+#define SPI_SR_REG(base)                         ((base)->SR)
+#define SPI_RSER_REG(base)                       ((base)->RSER)
+#define SPI_PUSHR_REG(base)                      ((base)->PUSHR)
+#define SPI_PUSHR_SLAVE_REG(base)                ((base)->PUSHR_SLAVE)
+#define SPI_POPR_REG(base)                       ((base)->POPR)
+#define SPI_TXFR0_REG(base)                      ((base)->TXFR0)
+#define SPI_TXFR1_REG(base)                      ((base)->TXFR1)
+#define SPI_TXFR2_REG(base)                      ((base)->TXFR2)
+#define SPI_TXFR3_REG(base)                      ((base)->TXFR3)
+#define SPI_RXFR0_REG(base)                      ((base)->RXFR0)
+#define SPI_RXFR1_REG(base)                      ((base)->RXFR1)
+#define SPI_RXFR2_REG(base)                      ((base)->RXFR2)
+#define SPI_RXFR3_REG(base)                      ((base)->RXFR3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK                        0x1u
+#define SPI_MCR_HALT_SHIFT                       0
+#define SPI_MCR_HALT_WIDTH                       1
+#define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_HALT_SHIFT))&SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK                     0x300u
+#define SPI_MCR_SMPL_PT_SHIFT                    8
+#define SPI_MCR_SMPL_PT_WIDTH                    2
+#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK                     0x400u
+#define SPI_MCR_CLR_RXF_SHIFT                    10
+#define SPI_MCR_CLR_RXF_WIDTH                    1
+#define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_RXF_SHIFT))&SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK                     0x800u
+#define SPI_MCR_CLR_TXF_SHIFT                    11
+#define SPI_MCR_CLR_TXF_WIDTH                    1
+#define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_TXF_SHIFT))&SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK                     0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT                    12
+#define SPI_MCR_DIS_RXF_WIDTH                    1
+#define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_RXF_SHIFT))&SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK                     0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT                    13
+#define SPI_MCR_DIS_TXF_WIDTH                    1
+#define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_TXF_SHIFT))&SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK                        0x4000u
+#define SPI_MCR_MDIS_SHIFT                       14
+#define SPI_MCR_MDIS_WIDTH                       1
+#define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MDIS_SHIFT))&SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK                        0x8000u
+#define SPI_MCR_DOZE_SHIFT                       15
+#define SPI_MCR_DOZE_WIDTH                       1
+#define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DOZE_SHIFT))&SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK                       0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT                      16
+#define SPI_MCR_PCSIS_WIDTH                      6
+#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK                        0x1000000u
+#define SPI_MCR_ROOE_SHIFT                       24
+#define SPI_MCR_ROOE_WIDTH                       1
+#define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_ROOE_SHIFT))&SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK                       0x2000000u
+#define SPI_MCR_PCSSE_SHIFT                      25
+#define SPI_MCR_PCSSE_WIDTH                      1
+#define SPI_MCR_PCSSE(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSSE_SHIFT))&SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK                        0x4000000u
+#define SPI_MCR_MTFE_SHIFT                       26
+#define SPI_MCR_MTFE_WIDTH                       1
+#define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MTFE_SHIFT))&SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK                         0x8000000u
+#define SPI_MCR_FRZ_SHIFT                        27
+#define SPI_MCR_FRZ_WIDTH                        1
+#define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_MCR_FRZ_SHIFT))&SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK                       0x30000000u
+#define SPI_MCR_DCONF_SHIFT                      28
+#define SPI_MCR_DCONF_WIDTH                      2
+#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK                   0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT                  30
+#define SPI_MCR_CONT_SCKE_WIDTH                  1
+#define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CONT_SCKE_SHIFT))&SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK                        0x80000000u
+#define SPI_MCR_MSTR_SHIFT                       31
+#define SPI_MCR_MSTR_WIDTH                       1
+#define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MSTR_SHIFT))&SPI_MCR_MSTR_MASK)
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK                    0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT                   16
+#define SPI_TCR_SPI_TCNT_WIDTH                   16
+#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK                         0xFu
+#define SPI_CTAR_BR_SHIFT                        0
+#define SPI_CTAR_BR_WIDTH                        4
+#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK                         0xF0u
+#define SPI_CTAR_DT_SHIFT                        4
+#define SPI_CTAR_DT_WIDTH                        4
+#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK                        0xF00u
+#define SPI_CTAR_ASC_SHIFT                       8
+#define SPI_CTAR_ASC_WIDTH                       4
+#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK                      0xF000u
+#define SPI_CTAR_CSSCK_SHIFT                     12
+#define SPI_CTAR_CSSCK_WIDTH                     4
+#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK                        0x30000u
+#define SPI_CTAR_PBR_SHIFT                       16
+#define SPI_CTAR_PBR_WIDTH                       2
+#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK                        0xC0000u
+#define SPI_CTAR_PDT_SHIFT                       18
+#define SPI_CTAR_PDT_WIDTH                       2
+#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK                       0x300000u
+#define SPI_CTAR_PASC_SHIFT                      20
+#define SPI_CTAR_PASC_WIDTH                      2
+#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK                     0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT                    22
+#define SPI_CTAR_PCSSCK_WIDTH                    2
+#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK                      0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT                     24
+#define SPI_CTAR_LSBFE_WIDTH                     1
+#define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_LSBFE_SHIFT))&SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK                       0x2000000u
+#define SPI_CTAR_CPHA_SHIFT                      25
+#define SPI_CTAR_CPHA_WIDTH                      1
+#define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPHA_SHIFT))&SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK                       0x4000000u
+#define SPI_CTAR_CPOL_SHIFT                      26
+#define SPI_CTAR_CPOL_WIDTH                      1
+#define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPOL_SHIFT))&SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK                       0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT                      27
+#define SPI_CTAR_FMSZ_WIDTH                      4
+#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK                        0x80000000u
+#define SPI_CTAR_DBR_SHIFT                       31
+#define SPI_CTAR_DBR_WIDTH                       1
+#define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DBR_SHIFT))&SPI_CTAR_DBR_MASK)
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK                 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT                25
+#define SPI_CTAR_SLAVE_CPHA_WIDTH                1
+#define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPHA_SHIFT))&SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK                 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT                26
+#define SPI_CTAR_SLAVE_CPOL_WIDTH                1
+#define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPOL_SHIFT))&SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK                 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT                27
+#define SPI_CTAR_SLAVE_FMSZ_WIDTH                5
+#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK                    0xFu
+#define SPI_SR_POPNXTPTR_SHIFT                   0
+#define SPI_SR_POPNXTPTR_WIDTH                   4
+#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK                        0xF0u
+#define SPI_SR_RXCTR_SHIFT                       4
+#define SPI_SR_RXCTR_WIDTH                       4
+#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK                     0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT                    8
+#define SPI_SR_TXNXTPTR_WIDTH                    4
+#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK                        0xF000u
+#define SPI_SR_TXCTR_SHIFT                       12
+#define SPI_SR_TXCTR_WIDTH                       4
+#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK                         0x20000u
+#define SPI_SR_RFDF_SHIFT                        17
+#define SPI_SR_RFDF_WIDTH                        1
+#define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFDF_SHIFT))&SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK                         0x80000u
+#define SPI_SR_RFOF_SHIFT                        19
+#define SPI_SR_RFOF_WIDTH                        1
+#define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFOF_SHIFT))&SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK                         0x2000000u
+#define SPI_SR_TFFF_SHIFT                        25
+#define SPI_SR_TFFF_WIDTH                        1
+#define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK                         0x8000000u
+#define SPI_SR_TFUF_SHIFT                        27
+#define SPI_SR_TFUF_WIDTH                        1
+#define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFUF_SHIFT))&SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK                         0x10000000u
+#define SPI_SR_EOQF_SHIFT                        28
+#define SPI_SR_EOQF_WIDTH                        1
+#define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_EOQF_SHIFT))&SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK                        0x40000000u
+#define SPI_SR_TXRXS_SHIFT                       30
+#define SPI_SR_TXRXS_WIDTH                       1
+#define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXRXS_SHIFT))&SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK                          0x80000000u
+#define SPI_SR_TCF_SHIFT                         31
+#define SPI_SR_TCF_WIDTH                         1
+#define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x))<<SPI_SR_TCF_SHIFT))&SPI_SR_TCF_MASK)
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK                  0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT                 16
+#define SPI_RSER_RFDF_DIRS_WIDTH                 1
+#define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_DIRS_SHIFT))&SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK                    0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT                   17
+#define SPI_RSER_RFDF_RE_WIDTH                   1
+#define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_RE_SHIFT))&SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK                    0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT                   19
+#define SPI_RSER_RFOF_RE_WIDTH                   1
+#define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFOF_RE_SHIFT))&SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK                  0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT                 24
+#define SPI_RSER_TFFF_DIRS_WIDTH                 1
+#define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_DIRS_SHIFT))&SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK                    0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT                   25
+#define SPI_RSER_TFFF_RE_WIDTH                   1
+#define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK                    0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT                   27
+#define SPI_RSER_TFUF_RE_WIDTH                   1
+#define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFUF_RE_SHIFT))&SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK                    0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT                   28
+#define SPI_RSER_EOQF_RE_WIDTH                   1
+#define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_EOQF_RE_SHIFT))&SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK                     0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT                    31
+#define SPI_RSER_TCF_RE_WIDTH                    1
+#define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TCF_RE_SHIFT))&SPI_RSER_TCF_RE_MASK)
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK                    0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT                   0
+#define SPI_PUSHR_TXDATA_WIDTH                   16
+#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK                       0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT                      16
+#define SPI_PUSHR_PCS_WIDTH                      6
+#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK                     0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT                    26
+#define SPI_PUSHR_CTCNT_WIDTH                    1
+#define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTCNT_SHIFT))&SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK                       0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT                      27
+#define SPI_PUSHR_EOQ_WIDTH                      1
+#define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_EOQ_SHIFT))&SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK                      0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT                     28
+#define SPI_PUSHR_CTAS_WIDTH                     3
+#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK                      0x80000000u
+#define SPI_PUSHR_CONT_SHIFT                     31
+#define SPI_PUSHR_CONT_WIDTH                     1
+#define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CONT_SHIFT))&SPI_PUSHR_CONT_MASK)
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK              0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             0
+#define SPI_PUSHR_SLAVE_TXDATA_WIDTH             32
+#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK                     0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT                    0
+#define SPI_POPR_RXDATA_WIDTH                    32
+#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT                   0
+#define SPI_TXFR0_TXDATA_WIDTH                   16
+#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR0_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT                   0
+#define SPI_TXFR1_TXDATA_WIDTH                   16
+#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR1_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT                   0
+#define SPI_TXFR2_TXDATA_WIDTH                   16
+#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR2_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT                   0
+#define SPI_TXFR3_TXDATA_WIDTH                   16
+#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR3_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT                   0
+#define SPI_RXFR0_RXDATA_WIDTH                   32
+#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT                   0
+#define SPI_RXFR1_RXDATA_WIDTH                   32
+#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT                   0
+#define SPI_RXFR2_RXDATA_WIDTH                   32
+#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT                   0
+#define SPI_RXFR3_RXDATA_WIDTH                   32
+#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR                            (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR                            (SPI1)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x400AC000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+#define SPI2_BASE_PTR                            (SPI2)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_MCR                                 SPI_MCR_REG(SPI0)
+#define SPI0_TCR                                 SPI_TCR_REG(SPI0)
+#define SPI0_CTAR0                               SPI_CTAR_REG(SPI0,0)
+#define SPI0_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI0,0)
+#define SPI0_CTAR1                               SPI_CTAR_REG(SPI0,1)
+#define SPI0_SR                                  SPI_SR_REG(SPI0)
+#define SPI0_RSER                                SPI_RSER_REG(SPI0)
+#define SPI0_PUSHR                               SPI_PUSHR_REG(SPI0)
+#define SPI0_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI0)
+#define SPI0_POPR                                SPI_POPR_REG(SPI0)
+#define SPI0_TXFR0                               SPI_TXFR0_REG(SPI0)
+#define SPI0_TXFR1                               SPI_TXFR1_REG(SPI0)
+#define SPI0_TXFR2                               SPI_TXFR2_REG(SPI0)
+#define SPI0_TXFR3                               SPI_TXFR3_REG(SPI0)
+#define SPI0_RXFR0                               SPI_RXFR0_REG(SPI0)
+#define SPI0_RXFR1                               SPI_RXFR1_REG(SPI0)
+#define SPI0_RXFR2                               SPI_RXFR2_REG(SPI0)
+#define SPI0_RXFR3                               SPI_RXFR3_REG(SPI0)
+/* SPI1 */
+#define SPI1_MCR                                 SPI_MCR_REG(SPI1)
+#define SPI1_TCR                                 SPI_TCR_REG(SPI1)
+#define SPI1_CTAR0                               SPI_CTAR_REG(SPI1,0)
+#define SPI1_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI1,0)
+#define SPI1_CTAR1                               SPI_CTAR_REG(SPI1,1)
+#define SPI1_SR                                  SPI_SR_REG(SPI1)
+#define SPI1_RSER                                SPI_RSER_REG(SPI1)
+#define SPI1_PUSHR                               SPI_PUSHR_REG(SPI1)
+#define SPI1_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI1)
+#define SPI1_POPR                                SPI_POPR_REG(SPI1)
+#define SPI1_TXFR0                               SPI_TXFR0_REG(SPI1)
+#define SPI1_TXFR1                               SPI_TXFR1_REG(SPI1)
+#define SPI1_TXFR2                               SPI_TXFR2_REG(SPI1)
+#define SPI1_TXFR3                               SPI_TXFR3_REG(SPI1)
+#define SPI1_RXFR0                               SPI_RXFR0_REG(SPI1)
+#define SPI1_RXFR1                               SPI_RXFR1_REG(SPI1)
+#define SPI1_RXFR2                               SPI_RXFR2_REG(SPI1)
+#define SPI1_RXFR3                               SPI_RXFR3_REG(SPI1)
+/* SPI2 */
+#define SPI2_MCR                                 SPI_MCR_REG(SPI2)
+#define SPI2_TCR                                 SPI_TCR_REG(SPI2)
+#define SPI2_CTAR0                               SPI_CTAR_REG(SPI2,0)
+#define SPI2_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI2,0)
+#define SPI2_CTAR1                               SPI_CTAR_REG(SPI2,1)
+#define SPI2_SR                                  SPI_SR_REG(SPI2)
+#define SPI2_RSER                                SPI_RSER_REG(SPI2)
+#define SPI2_PUSHR                               SPI_PUSHR_REG(SPI2)
+#define SPI2_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI2)
+#define SPI2_POPR                                SPI_POPR_REG(SPI2)
+#define SPI2_TXFR0                               SPI_TXFR0_REG(SPI2)
+#define SPI2_TXFR1                               SPI_TXFR1_REG(SPI2)
+#define SPI2_TXFR2                               SPI_TXFR2_REG(SPI2)
+#define SPI2_TXFR3                               SPI_TXFR3_REG(SPI2)
+#define SPI2_RXFR0                               SPI_RXFR0_REG(SPI2)
+#define SPI2_RXFR1                               SPI_RXFR1_REG(SPI2)
+#define SPI2_RXFR2                               SPI_RXFR2_REG(SPI2)
+#define SPI2_RXFR3                               SPI_RXFR3_REG(SPI2)
+
+/* SPI - Register array accessors */
+#define SPI0_CTAR(index2)                        SPI_CTAR_REG(SPI0,index2)
+#define SPI1_CTAR(index2)                        SPI_CTAR_REG(SPI1,index2)
+#define SPI2_CTAR(index2)                        SPI_CTAR_REG(SPI2,index2)
+#define SPI0_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI0,index2)
+#define SPI1_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI1,index2)
+#define SPI2_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI2,index2)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
+  __I  uint8_t ED;                                 /**< UART Extended Data Register, offset: 0xC */
+  __IO uint8_t MODEM;                              /**< UART Modem Register, offset: 0xD */
+  __IO uint8_t IR;                                 /**< UART Infrared Register, offset: 0xE */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t PFIFO;                              /**< UART FIFO Parameters, offset: 0x10 */
+  __IO uint8_t CFIFO;                              /**< UART FIFO Control Register, offset: 0x11 */
+  __IO uint8_t SFIFO;                              /**< UART FIFO Status Register, offset: 0x12 */
+  __IO uint8_t TWFIFO;                             /**< UART FIFO Transmit Watermark, offset: 0x13 */
+  __I  uint8_t TCFIFO;                             /**< UART FIFO Transmit Count, offset: 0x14 */
+  __IO uint8_t RWFIFO;                             /**< UART FIFO Receive Watermark, offset: 0x15 */
+  __I  uint8_t RCFIFO;                             /**< UART FIFO Receive Count, offset: 0x16 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
+  __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+  __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+  union {                                          /* offset: 0x1B */
+    __IO uint8_t WP7816T0;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+    __IO uint8_t WP7816T1;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+  };
+  __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
+  __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
+  __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
+  __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base)                       ((base)->BDH)
+#define UART_BDL_REG(base)                       ((base)->BDL)
+#define UART_C1_REG(base)                        ((base)->C1)
+#define UART_C2_REG(base)                        ((base)->C2)
+#define UART_S1_REG(base)                        ((base)->S1)
+#define UART_S2_REG(base)                        ((base)->S2)
+#define UART_C3_REG(base)                        ((base)->C3)
+#define UART_D_REG(base)                         ((base)->D)
+#define UART_MA1_REG(base)                       ((base)->MA1)
+#define UART_MA2_REG(base)                       ((base)->MA2)
+#define UART_C4_REG(base)                        ((base)->C4)
+#define UART_C5_REG(base)                        ((base)->C5)
+#define UART_ED_REG(base)                        ((base)->ED)
+#define UART_MODEM_REG(base)                     ((base)->MODEM)
+#define UART_IR_REG(base)                        ((base)->IR)
+#define UART_PFIFO_REG(base)                     ((base)->PFIFO)
+#define UART_CFIFO_REG(base)                     ((base)->CFIFO)
+#define UART_SFIFO_REG(base)                     ((base)->SFIFO)
+#define UART_TWFIFO_REG(base)                    ((base)->TWFIFO)
+#define UART_TCFIFO_REG(base)                    ((base)->TCFIFO)
+#define UART_RWFIFO_REG(base)                    ((base)->RWFIFO)
+#define UART_RCFIFO_REG(base)                    ((base)->RCFIFO)
+#define UART_C7816_REG(base)                     ((base)->C7816)
+#define UART_IE7816_REG(base)                    ((base)->IE7816)
+#define UART_IS7816_REG(base)                    ((base)->IS7816)
+#define UART_WP7816T0_REG(base)                  ((base)->WP7816T0)
+#define UART_WP7816T1_REG(base)                  ((base)->WP7816T1)
+#define UART_WN7816_REG(base)                    ((base)->WN7816)
+#define UART_WF7816_REG(base)                    ((base)->WF7816)
+#define UART_ET7816_REG(base)                    ((base)->ET7816)
+#define UART_TL7816_REG(base)                    ((base)->TL7816)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK                        0x1Fu
+#define UART_BDH_SBR_SHIFT                       0
+#define UART_BDH_SBR_WIDTH                       5
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK                       0x20u
+#define UART_BDH_SBNS_SHIFT                      5
+#define UART_BDH_SBNS_WIDTH                      1
+#define UART_BDH_SBNS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBNS_SHIFT))&UART_BDH_SBNS_MASK)
+#define UART_BDH_RXEDGIE_MASK                    0x40u
+#define UART_BDH_RXEDGIE_SHIFT                   6
+#define UART_BDH_RXEDGIE_WIDTH                   1
+#define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK                     0x80u
+#define UART_BDH_LBKDIE_SHIFT                    7
+#define UART_BDH_LBKDIE_WIDTH                    1
+#define UART_BDH_LBKDIE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_BDH_LBKDIE_SHIFT))&UART_BDH_LBKDIE_MASK)
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK                        0xFFu
+#define UART_BDL_SBR_SHIFT                       0
+#define UART_BDL_SBR_WIDTH                       8
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK                          0x1u
+#define UART_C1_PT_SHIFT                         0
+#define UART_C1_PT_WIDTH                         1
+#define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
+#define UART_C1_PE_MASK                          0x2u
+#define UART_C1_PE_SHIFT                         1
+#define UART_C1_PE_WIDTH                         1
+#define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK                         0x4u
+#define UART_C1_ILT_SHIFT                        2
+#define UART_C1_ILT_WIDTH                        1
+#define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK                        0x8u
+#define UART_C1_WAKE_SHIFT                       3
+#define UART_C1_WAKE_WIDTH                       1
+#define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK                           0x10u
+#define UART_C1_M_SHIFT                          4
+#define UART_C1_M_WIDTH                          1
+#define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK                        0x20u
+#define UART_C1_RSRC_SHIFT                       5
+#define UART_C1_RSRC_WIDTH                       1
+#define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK                    0x40u
+#define UART_C1_UARTSWAI_SHIFT                   6
+#define UART_C1_UARTSWAI_WIDTH                   1
+#define UART_C1_UARTSWAI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C1_UARTSWAI_SHIFT))&UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK                       0x80u
+#define UART_C1_LOOPS_SHIFT                      7
+#define UART_C1_LOOPS_WIDTH                      1
+#define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK                         0x1u
+#define UART_C2_SBK_SHIFT                        0
+#define UART_C2_SBK_WIDTH                        1
+#define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK                         0x2u
+#define UART_C2_RWU_SHIFT                        1
+#define UART_C2_RWU_WIDTH                        1
+#define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK                          0x4u
+#define UART_C2_RE_SHIFT                         2
+#define UART_C2_RE_WIDTH                         1
+#define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
+#define UART_C2_TE_MASK                          0x8u
+#define UART_C2_TE_SHIFT                         3
+#define UART_C2_TE_WIDTH                         1
+#define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK                        0x10u
+#define UART_C2_ILIE_SHIFT                       4
+#define UART_C2_ILIE_WIDTH                       1
+#define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK                         0x20u
+#define UART_C2_RIE_SHIFT                        5
+#define UART_C2_RIE_WIDTH                        1
+#define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK                        0x40u
+#define UART_C2_TCIE_SHIFT                       6
+#define UART_C2_TCIE_WIDTH                       1
+#define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK                         0x80u
+#define UART_C2_TIE_SHIFT                        7
+#define UART_C2_TIE_WIDTH                        1
+#define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK                          0x1u
+#define UART_S1_PF_SHIFT                         0
+#define UART_S1_PF_WIDTH                         1
+#define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
+#define UART_S1_FE_MASK                          0x2u
+#define UART_S1_FE_SHIFT                         1
+#define UART_S1_FE_WIDTH                         1
+#define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
+#define UART_S1_NF_MASK                          0x4u
+#define UART_S1_NF_SHIFT                         2
+#define UART_S1_NF_WIDTH                         1
+#define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
+#define UART_S1_OR_MASK                          0x8u
+#define UART_S1_OR_SHIFT                         3
+#define UART_S1_OR_WIDTH                         1
+#define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK                        0x10u
+#define UART_S1_IDLE_SHIFT                       4
+#define UART_S1_IDLE_WIDTH                       1
+#define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK                        0x20u
+#define UART_S1_RDRF_SHIFT                       5
+#define UART_S1_RDRF_WIDTH                       1
+#define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK                          0x40u
+#define UART_S1_TC_SHIFT                         6
+#define UART_S1_TC_WIDTH                         1
+#define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK                        0x80u
+#define UART_S1_TDRE_SHIFT                       7
+#define UART_S1_TDRE_WIDTH                       1
+#define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK                         0x1u
+#define UART_S2_RAF_SHIFT                        0
+#define UART_S2_RAF_WIDTH                        1
+#define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK                       0x2u
+#define UART_S2_LBKDE_SHIFT                      1
+#define UART_S2_LBKDE_WIDTH                      1
+#define UART_S2_LBKDE(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDE_SHIFT))&UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK                       0x4u
+#define UART_S2_BRK13_SHIFT                      2
+#define UART_S2_BRK13_WIDTH                      1
+#define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK                       0x8u
+#define UART_S2_RWUID_SHIFT                      3
+#define UART_S2_RWUID_WIDTH                      1
+#define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK                       0x10u
+#define UART_S2_RXINV_SHIFT                      4
+#define UART_S2_RXINV_WIDTH                      1
+#define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK                        0x20u
+#define UART_S2_MSBF_SHIFT                       5
+#define UART_S2_MSBF_WIDTH                       1
+#define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S2_MSBF_SHIFT))&UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK                     0x40u
+#define UART_S2_RXEDGIF_SHIFT                    6
+#define UART_S2_RXEDGIF_WIDTH                    1
+#define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK                      0x80u
+#define UART_S2_LBKDIF_SHIFT                     7
+#define UART_S2_LBKDIF_WIDTH                     1
+#define UART_S2_LBKDIF(x)                        (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDIF_SHIFT))&UART_S2_LBKDIF_MASK)
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK                        0x1u
+#define UART_C3_PEIE_SHIFT                       0
+#define UART_C3_PEIE_WIDTH                       1
+#define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK                        0x2u
+#define UART_C3_FEIE_SHIFT                       1
+#define UART_C3_FEIE_WIDTH                       1
+#define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK                        0x4u
+#define UART_C3_NEIE_SHIFT                       2
+#define UART_C3_NEIE_WIDTH                       1
+#define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK                        0x8u
+#define UART_C3_ORIE_SHIFT                       3
+#define UART_C3_ORIE_WIDTH                       1
+#define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK                       0x10u
+#define UART_C3_TXINV_SHIFT                      4
+#define UART_C3_TXINV_WIDTH                      1
+#define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK                       0x20u
+#define UART_C3_TXDIR_SHIFT                      5
+#define UART_C3_TXDIR_WIDTH                      1
+#define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK                          0x40u
+#define UART_C3_T8_SHIFT                         6
+#define UART_C3_T8_WIDTH                         1
+#define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
+#define UART_C3_R8_MASK                          0x80u
+#define UART_C3_R8_SHIFT                         7
+#define UART_C3_R8_WIDTH                         1
+#define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
+/* D Bit Fields */
+#define UART_D_RT_MASK                           0xFFu
+#define UART_D_RT_SHIFT                          0
+#define UART_D_RT_WIDTH                          8
+#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK                         0xFFu
+#define UART_MA1_MA_SHIFT                        0
+#define UART_MA1_MA_WIDTH                        8
+#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK                         0xFFu
+#define UART_MA2_MA_SHIFT                        0
+#define UART_MA2_MA_WIDTH                        8
+#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK                        0x1Fu
+#define UART_C4_BRFA_SHIFT                       0
+#define UART_C4_BRFA_WIDTH                       5
+#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK                         0x20u
+#define UART_C4_M10_SHIFT                        5
+#define UART_C4_M10_WIDTH                        1
+#define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C4_M10_SHIFT))&UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK                       0x40u
+#define UART_C4_MAEN2_SHIFT                      6
+#define UART_C4_MAEN2_WIDTH                      1
+#define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN2_SHIFT))&UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK                       0x80u
+#define UART_C4_MAEN1_SHIFT                      7
+#define UART_C4_MAEN1_WIDTH                      1
+#define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN1_SHIFT))&UART_C4_MAEN1_MASK)
+/* C5 Bit Fields */
+#define UART_C5_LBKDDMAS_MASK                    0x8u
+#define UART_C5_LBKDDMAS_SHIFT                   3
+#define UART_C5_LBKDDMAS_WIDTH                   1
+#define UART_C5_LBKDDMAS(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C5_LBKDDMAS_SHIFT))&UART_C5_LBKDDMAS_MASK)
+#define UART_C5_ILDMAS_MASK                      0x10u
+#define UART_C5_ILDMAS_SHIFT                     4
+#define UART_C5_ILDMAS_WIDTH                     1
+#define UART_C5_ILDMAS(x)                        (((uint8_t)(((uint8_t)(x))<<UART_C5_ILDMAS_SHIFT))&UART_C5_ILDMAS_MASK)
+#define UART_C5_RDMAS_MASK                       0x20u
+#define UART_C5_RDMAS_SHIFT                      5
+#define UART_C5_RDMAS_WIDTH                      1
+#define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_RDMAS_SHIFT))&UART_C5_RDMAS_MASK)
+#define UART_C5_TCDMAS_MASK                      0x40u
+#define UART_C5_TCDMAS_SHIFT                     6
+#define UART_C5_TCDMAS_WIDTH                     1
+#define UART_C5_TCDMAS(x)                        (((uint8_t)(((uint8_t)(x))<<UART_C5_TCDMAS_SHIFT))&UART_C5_TCDMAS_MASK)
+#define UART_C5_TDMAS_MASK                       0x80u
+#define UART_C5_TDMAS_SHIFT                      7
+#define UART_C5_TDMAS_WIDTH                      1
+#define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_TDMAS_SHIFT))&UART_C5_TDMAS_MASK)
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK                     0x40u
+#define UART_ED_PARITYE_SHIFT                    6
+#define UART_ED_PARITYE_WIDTH                    1
+#define UART_ED_PARITYE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_ED_PARITYE_SHIFT))&UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK                       0x80u
+#define UART_ED_NOISY_SHIFT                      7
+#define UART_ED_NOISY_WIDTH                      1
+#define UART_ED_NOISY(x)                         (((uint8_t)(((uint8_t)(x))<<UART_ED_NOISY_SHIFT))&UART_ED_NOISY_MASK)
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK                   0x1u
+#define UART_MODEM_TXCTSE_SHIFT                  0
+#define UART_MODEM_TXCTSE_WIDTH                  1
+#define UART_MODEM_TXCTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXCTSE_SHIFT))&UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK                   0x2u
+#define UART_MODEM_TXRTSE_SHIFT                  1
+#define UART_MODEM_TXRTSE_WIDTH                  1
+#define UART_MODEM_TXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSE_SHIFT))&UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK                 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT                2
+#define UART_MODEM_TXRTSPOL_WIDTH                1
+#define UART_MODEM_TXRTSPOL(x)                   (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSPOL_SHIFT))&UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK                   0x8u
+#define UART_MODEM_RXRTSE_SHIFT                  3
+#define UART_MODEM_RXRTSE_WIDTH                  1
+#define UART_MODEM_RXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_RXRTSE_SHIFT))&UART_MODEM_RXRTSE_MASK)
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK                         0x3u
+#define UART_IR_TNP_SHIFT                        0
+#define UART_IR_TNP_WIDTH                        2
+#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK                        0x4u
+#define UART_IR_IREN_SHIFT                       2
+#define UART_IR_IREN_WIDTH                       1
+#define UART_IR_IREN(x)                          (((uint8_t)(((uint8_t)(x))<<UART_IR_IREN_SHIFT))&UART_IR_IREN_MASK)
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK               0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT              0
+#define UART_PFIFO_RXFIFOSIZE_WIDTH              3
+#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK                     0x8u
+#define UART_PFIFO_RXFE_SHIFT                    3
+#define UART_PFIFO_RXFE_WIDTH                    1
+#define UART_PFIFO_RXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFE_SHIFT))&UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK               0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT              4
+#define UART_PFIFO_TXFIFOSIZE_WIDTH              3
+#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK                     0x80u
+#define UART_PFIFO_TXFE_SHIFT                    7
+#define UART_PFIFO_TXFE_WIDTH                    1
+#define UART_PFIFO_TXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFE_SHIFT))&UART_PFIFO_TXFE_MASK)
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK                    0x1u
+#define UART_CFIFO_RXUFE_SHIFT                   0
+#define UART_CFIFO_RXUFE_WIDTH                   1
+#define UART_CFIFO_RXUFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXUFE_SHIFT))&UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK                    0x2u
+#define UART_CFIFO_TXOFE_SHIFT                   1
+#define UART_CFIFO_TXOFE_WIDTH                   1
+#define UART_CFIFO_TXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXOFE_SHIFT))&UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXOFE_MASK                    0x4u
+#define UART_CFIFO_RXOFE_SHIFT                   2
+#define UART_CFIFO_RXOFE_WIDTH                   1
+#define UART_CFIFO_RXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXOFE_SHIFT))&UART_CFIFO_RXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK                  0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT                 6
+#define UART_CFIFO_RXFLUSH_WIDTH                 1
+#define UART_CFIFO_RXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXFLUSH_SHIFT))&UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK                  0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT                 7
+#define UART_CFIFO_TXFLUSH_WIDTH                 1
+#define UART_CFIFO_TXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXFLUSH_SHIFT))&UART_CFIFO_TXFLUSH_MASK)
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK                     0x1u
+#define UART_SFIFO_RXUF_SHIFT                    0
+#define UART_SFIFO_RXUF_WIDTH                    1
+#define UART_SFIFO_RXUF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXUF_SHIFT))&UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK                     0x2u
+#define UART_SFIFO_TXOF_SHIFT                    1
+#define UART_SFIFO_TXOF_WIDTH                    1
+#define UART_SFIFO_TXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXOF_SHIFT))&UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXOF_MASK                     0x4u
+#define UART_SFIFO_RXOF_SHIFT                    2
+#define UART_SFIFO_RXOF_WIDTH                    1
+#define UART_SFIFO_RXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXOF_SHIFT))&UART_SFIFO_RXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK                   0x40u
+#define UART_SFIFO_RXEMPT_SHIFT                  6
+#define UART_SFIFO_RXEMPT_WIDTH                  1
+#define UART_SFIFO_RXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXEMPT_SHIFT))&UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK                   0x80u
+#define UART_SFIFO_TXEMPT_SHIFT                  7
+#define UART_SFIFO_TXEMPT_WIDTH                  1
+#define UART_SFIFO_TXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXEMPT_SHIFT))&UART_SFIFO_TXEMPT_MASK)
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK                 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT                0
+#define UART_TWFIFO_TXWATER_WIDTH                8
+#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK                 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT                0
+#define UART_TCFIFO_TXCOUNT_WIDTH                8
+#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK                 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT                0
+#define UART_RWFIFO_RXWATER_WIDTH                8
+#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK                 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT                0
+#define UART_RCFIFO_RXCOUNT_WIDTH                8
+#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK                0x1u
+#define UART_C7816_ISO_7816E_SHIFT               0
+#define UART_C7816_ISO_7816E_WIDTH               1
+#define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x))<<UART_C7816_ISO_7816E_SHIFT))&UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK                    0x2u
+#define UART_C7816_TTYPE_SHIFT                   1
+#define UART_C7816_TTYPE_WIDTH                   1
+#define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_TTYPE_SHIFT))&UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK                     0x4u
+#define UART_C7816_INIT_SHIFT                    2
+#define UART_C7816_INIT_WIDTH                    1
+#define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_C7816_INIT_SHIFT))&UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK                    0x8u
+#define UART_C7816_ANACK_SHIFT                   3
+#define UART_C7816_ANACK_WIDTH                   1
+#define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ANACK_SHIFT))&UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK                    0x10u
+#define UART_C7816_ONACK_SHIFT                   4
+#define UART_C7816_ONACK_WIDTH                   1
+#define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ONACK_SHIFT))&UART_C7816_ONACK_MASK)
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK                    0x1u
+#define UART_IE7816_RXTE_SHIFT                   0
+#define UART_IE7816_RXTE_WIDTH                   1
+#define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_RXTE_SHIFT))&UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK                    0x2u
+#define UART_IE7816_TXTE_SHIFT                   1
+#define UART_IE7816_TXTE_WIDTH                   1
+#define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_TXTE_SHIFT))&UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK                    0x4u
+#define UART_IE7816_GTVE_SHIFT                   2
+#define UART_IE7816_GTVE_WIDTH                   1
+#define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_GTVE_SHIFT))&UART_IE7816_GTVE_MASK)
+#define UART_IE7816_INITDE_MASK                  0x10u
+#define UART_IE7816_INITDE_SHIFT                 4
+#define UART_IE7816_INITDE_WIDTH                 1
+#define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x))<<UART_IE7816_INITDE_SHIFT))&UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK                    0x20u
+#define UART_IE7816_BWTE_SHIFT                   5
+#define UART_IE7816_BWTE_WIDTH                   1
+#define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_BWTE_SHIFT))&UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK                    0x40u
+#define UART_IE7816_CWTE_SHIFT                   6
+#define UART_IE7816_CWTE_WIDTH                   1
+#define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_CWTE_SHIFT))&UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK                     0x80u
+#define UART_IE7816_WTE_SHIFT                    7
+#define UART_IE7816_WTE_WIDTH                    1
+#define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IE7816_WTE_SHIFT))&UART_IE7816_WTE_MASK)
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK                     0x1u
+#define UART_IS7816_RXT_SHIFT                    0
+#define UART_IS7816_RXT_WIDTH                    1
+#define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_RXT_SHIFT))&UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK                     0x2u
+#define UART_IS7816_TXT_SHIFT                    1
+#define UART_IS7816_TXT_WIDTH                    1
+#define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_TXT_SHIFT))&UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK                     0x4u
+#define UART_IS7816_GTV_SHIFT                    2
+#define UART_IS7816_GTV_WIDTH                    1
+#define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_GTV_SHIFT))&UART_IS7816_GTV_MASK)
+#define UART_IS7816_INITD_MASK                   0x10u
+#define UART_IS7816_INITD_SHIFT                  4
+#define UART_IS7816_INITD_WIDTH                  1
+#define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x))<<UART_IS7816_INITD_SHIFT))&UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK                     0x20u
+#define UART_IS7816_BWT_SHIFT                    5
+#define UART_IS7816_BWT_WIDTH                    1
+#define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_BWT_SHIFT))&UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK                     0x40u
+#define UART_IS7816_CWT_SHIFT                    6
+#define UART_IS7816_CWT_WIDTH                    1
+#define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_CWT_SHIFT))&UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK                      0x80u
+#define UART_IS7816_WT_SHIFT                     7
+#define UART_IS7816_WT_WIDTH                     1
+#define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x))<<UART_IS7816_WT_SHIFT))&UART_IS7816_WT_MASK)
+/* WP7816T0 Bit Fields */
+#define UART_WP7816T0_WI_MASK                    0xFFu
+#define UART_WP7816T0_WI_SHIFT                   0
+#define UART_WP7816T0_WI_WIDTH                   8
+#define UART_WP7816T0_WI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
+/* WP7816T1 Bit Fields */
+#define UART_WP7816T1_BWI_MASK                   0xFu
+#define UART_WP7816T1_BWI_SHIFT                  0
+#define UART_WP7816T1_BWI_WIDTH                  4
+#define UART_WP7816T1_BWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
+#define UART_WP7816T1_CWI_MASK                   0xF0u
+#define UART_WP7816T1_CWI_SHIFT                  4
+#define UART_WP7816T1_CWI_WIDTH                  4
+#define UART_WP7816T1_CWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK                     0xFFu
+#define UART_WN7816_GTN_SHIFT                    0
+#define UART_WN7816_GTN_WIDTH                    8
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK                    0xFFu
+#define UART_WF7816_GTFD_SHIFT                   0
+#define UART_WF7816_GTFD_WIDTH                   8
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK             0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT            0
+#define UART_ET7816_RXTHRESHOLD_WIDTH            4
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK             0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT            4
+#define UART_ET7816_TXTHRESHOLD_WIDTH            4
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK                    0xFFu
+#define UART_TL7816_TLEN_SHIFT                   0
+#define UART_TL7816_TLEN_WIDTH                   8
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0                                    ((UART_Type *)UART0_BASE)
+#define UART0_BASE_PTR                           (UART0)
+/** Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1                                    ((UART_Type *)UART1_BASE)
+#define UART1_BASE_PTR                           (UART1)
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR                           (UART2)
+/** Peripheral UART3 base address */
+#define UART3_BASE                               (0x4006D000u)
+/** Peripheral UART3 base pointer */
+#define UART3                                    ((UART_Type *)UART3_BASE)
+#define UART3_BASE_PTR                           (UART3)
+/** Peripheral UART4 base address */
+#define UART4_BASE                               (0x400EA000u)
+/** Peripheral UART4 base pointer */
+#define UART4                                    ((UART_Type *)UART4_BASE)
+#define UART4_BASE_PTR                           (UART4)
+/** Peripheral UART5 base address */
+#define UART5_BASE                               (0x400EB000u)
+/** Peripheral UART5 base pointer */
+#define UART5                                    ((UART_Type *)UART5_BASE)
+#define UART5_BASE_PTR                           (UART5)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS                           { UART0, UART1, UART2, UART3, UART4, UART5 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS                          { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
+#define UART_ERR_IRQS                            { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
+#define UART_LON_IRQS                            { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART0 */
+#define UART0_BDH                                UART_BDH_REG(UART0)
+#define UART0_BDL                                UART_BDL_REG(UART0)
+#define UART0_C1                                 UART_C1_REG(UART0)
+#define UART0_C2                                 UART_C2_REG(UART0)
+#define UART0_S1                                 UART_S1_REG(UART0)
+#define UART0_S2                                 UART_S2_REG(UART0)
+#define UART0_C3                                 UART_C3_REG(UART0)
+#define UART0_D                                  UART_D_REG(UART0)
+#define UART0_MA1                                UART_MA1_REG(UART0)
+#define UART0_MA2                                UART_MA2_REG(UART0)
+#define UART0_C4                                 UART_C4_REG(UART0)
+#define UART0_C5                                 UART_C5_REG(UART0)
+#define UART0_ED                                 UART_ED_REG(UART0)
+#define UART0_MODEM                              UART_MODEM_REG(UART0)
+#define UART0_IR                                 UART_IR_REG(UART0)
+#define UART0_PFIFO                              UART_PFIFO_REG(UART0)
+#define UART0_CFIFO                              UART_CFIFO_REG(UART0)
+#define UART0_SFIFO                              UART_SFIFO_REG(UART0)
+#define UART0_TWFIFO                             UART_TWFIFO_REG(UART0)
+#define UART0_TCFIFO                             UART_TCFIFO_REG(UART0)
+#define UART0_RWFIFO                             UART_RWFIFO_REG(UART0)
+#define UART0_RCFIFO                             UART_RCFIFO_REG(UART0)
+#define UART0_C7816                              UART_C7816_REG(UART0)
+#define UART0_IE7816                             UART_IE7816_REG(UART0)
+#define UART0_IS7816                             UART_IS7816_REG(UART0)
+#define UART0_WP7816T0                           UART_WP7816T0_REG(UART0)
+#define UART0_WP7816T1                           UART_WP7816T1_REG(UART0)
+#define UART0_WN7816                             UART_WN7816_REG(UART0)
+#define UART0_WF7816                             UART_WF7816_REG(UART0)
+#define UART0_ET7816                             UART_ET7816_REG(UART0)
+#define UART0_TL7816                             UART_TL7816_REG(UART0)
+/* UART1 */
+#define UART1_BDH                                UART_BDH_REG(UART1)
+#define UART1_BDL                                UART_BDL_REG(UART1)
+#define UART1_C1                                 UART_C1_REG(UART1)
+#define UART1_C2                                 UART_C2_REG(UART1)
+#define UART1_S1                                 UART_S1_REG(UART1)
+#define UART1_S2                                 UART_S2_REG(UART1)
+#define UART1_C3                                 UART_C3_REG(UART1)
+#define UART1_D                                  UART_D_REG(UART1)
+#define UART1_MA1                                UART_MA1_REG(UART1)
+#define UART1_MA2                                UART_MA2_REG(UART1)
+#define UART1_C4                                 UART_C4_REG(UART1)
+#define UART1_C5                                 UART_C5_REG(UART1)
+#define UART1_ED                                 UART_ED_REG(UART1)
+#define UART1_MODEM                              UART_MODEM_REG(UART1)
+#define UART1_IR                                 UART_IR_REG(UART1)
+#define UART1_PFIFO                              UART_PFIFO_REG(UART1)
+#define UART1_CFIFO                              UART_CFIFO_REG(UART1)
+#define UART1_SFIFO                              UART_SFIFO_REG(UART1)
+#define UART1_TWFIFO                             UART_TWFIFO_REG(UART1)
+#define UART1_TCFIFO                             UART_TCFIFO_REG(UART1)
+#define UART1_RWFIFO                             UART_RWFIFO_REG(UART1)
+#define UART1_RCFIFO                             UART_RCFIFO_REG(UART1)
+/* UART2 */
+#define UART2_BDH                                UART_BDH_REG(UART2)
+#define UART2_BDL                                UART_BDL_REG(UART2)
+#define UART2_C1                                 UART_C1_REG(UART2)
+#define UART2_C2                                 UART_C2_REG(UART2)
+#define UART2_S1                                 UART_S1_REG(UART2)
+#define UART2_S2                                 UART_S2_REG(UART2)
+#define UART2_C3                                 UART_C3_REG(UART2)
+#define UART2_D                                  UART_D_REG(UART2)
+#define UART2_MA1                                UART_MA1_REG(UART2)
+#define UART2_MA2                                UART_MA2_REG(UART2)
+#define UART2_C4                                 UART_C4_REG(UART2)
+#define UART2_C5                                 UART_C5_REG(UART2)
+#define UART2_ED                                 UART_ED_REG(UART2)
+#define UART2_MODEM                              UART_MODEM_REG(UART2)
+#define UART2_IR                                 UART_IR_REG(UART2)
+#define UART2_PFIFO                              UART_PFIFO_REG(UART2)
+#define UART2_CFIFO                              UART_CFIFO_REG(UART2)
+#define UART2_SFIFO                              UART_SFIFO_REG(UART2)
+#define UART2_TWFIFO                             UART_TWFIFO_REG(UART2)
+#define UART2_TCFIFO                             UART_TCFIFO_REG(UART2)
+#define UART2_RWFIFO                             UART_RWFIFO_REG(UART2)
+#define UART2_RCFIFO                             UART_RCFIFO_REG(UART2)
+/* UART3 */
+#define UART3_BDH                                UART_BDH_REG(UART3)
+#define UART3_BDL                                UART_BDL_REG(UART3)
+#define UART3_C1                                 UART_C1_REG(UART3)
+#define UART3_C2                                 UART_C2_REG(UART3)
+#define UART3_S1                                 UART_S1_REG(UART3)
+#define UART3_S2                                 UART_S2_REG(UART3)
+#define UART3_C3                                 UART_C3_REG(UART3)
+#define UART3_D                                  UART_D_REG(UART3)
+#define UART3_MA1                                UART_MA1_REG(UART3)
+#define UART3_MA2                                UART_MA2_REG(UART3)
+#define UART3_C4                                 UART_C4_REG(UART3)
+#define UART3_C5                                 UART_C5_REG(UART3)
+#define UART3_ED                                 UART_ED_REG(UART3)
+#define UART3_MODEM                              UART_MODEM_REG(UART3)
+#define UART3_IR                                 UART_IR_REG(UART3)
+#define UART3_PFIFO                              UART_PFIFO_REG(UART3)
+#define UART3_CFIFO                              UART_CFIFO_REG(UART3)
+#define UART3_SFIFO                              UART_SFIFO_REG(UART3)
+#define UART3_TWFIFO                             UART_TWFIFO_REG(UART3)
+#define UART3_TCFIFO                             UART_TCFIFO_REG(UART3)
+#define UART3_RWFIFO                             UART_RWFIFO_REG(UART3)
+#define UART3_RCFIFO                             UART_RCFIFO_REG(UART3)
+/* UART4 */
+#define UART4_BDH                                UART_BDH_REG(UART4)
+#define UART4_BDL                                UART_BDL_REG(UART4)
+#define UART4_C1                                 UART_C1_REG(UART4)
+#define UART4_C2                                 UART_C2_REG(UART4)
+#define UART4_S1                                 UART_S1_REG(UART4)
+#define UART4_S2                                 UART_S2_REG(UART4)
+#define UART4_C3                                 UART_C3_REG(UART4)
+#define UART4_D                                  UART_D_REG(UART4)
+#define UART4_MA1                                UART_MA1_REG(UART4)
+#define UART4_MA2                                UART_MA2_REG(UART4)
+#define UART4_C4                                 UART_C4_REG(UART4)
+#define UART4_C5                                 UART_C5_REG(UART4)
+#define UART4_ED                                 UART_ED_REG(UART4)
+#define UART4_MODEM                              UART_MODEM_REG(UART4)
+#define UART4_IR                                 UART_IR_REG(UART4)
+#define UART4_PFIFO                              UART_PFIFO_REG(UART4)
+#define UART4_CFIFO                              UART_CFIFO_REG(UART4)
+#define UART4_SFIFO                              UART_SFIFO_REG(UART4)
+#define UART4_TWFIFO                             UART_TWFIFO_REG(UART4)
+#define UART4_TCFIFO                             UART_TCFIFO_REG(UART4)
+#define UART4_RWFIFO                             UART_RWFIFO_REG(UART4)
+#define UART4_RCFIFO                             UART_RCFIFO_REG(UART4)
+/* UART5 */
+#define UART5_BDH                                UART_BDH_REG(UART5)
+#define UART5_BDL                                UART_BDL_REG(UART5)
+#define UART5_C1                                 UART_C1_REG(UART5)
+#define UART5_C2                                 UART_C2_REG(UART5)
+#define UART5_S1                                 UART_S1_REG(UART5)
+#define UART5_S2                                 UART_S2_REG(UART5)
+#define UART5_C3                                 UART_C3_REG(UART5)
+#define UART5_D                                  UART_D_REG(UART5)
+#define UART5_MA1                                UART_MA1_REG(UART5)
+#define UART5_MA2                                UART_MA2_REG(UART5)
+#define UART5_C4                                 UART_C4_REG(UART5)
+#define UART5_C5                                 UART_C5_REG(UART5)
+#define UART5_ED                                 UART_ED_REG(UART5)
+#define UART5_MODEM                              UART_MODEM_REG(UART5)
+#define UART5_IR                                 UART_IR_REG(UART5)
+#define UART5_PFIFO                              UART_PFIFO_REG(UART5)
+#define UART5_CFIFO                              UART_CFIFO_REG(UART5)
+#define UART5_SFIFO                              UART_SFIFO_REG(UART5)
+#define UART5_TWFIFO                             UART_TWFIFO_REG(UART5)
+#define UART5_TCFIFO                             UART_TCFIFO_REG(UART5)
+#define UART5_RWFIFO                             UART_RWFIFO_REG(UART5)
+#define UART5_RCFIFO                             UART_RCFIFO_REG(UART5)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[3];
+  __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t OTGICR;                             /**< OTG Interrupt Control register, offset: 0x14 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_7[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_11[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_16[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t SOFTHLD;                            /**< SOF Threshold register, offset: 0xAC */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_20[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_21[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_22[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_25[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
+       uint8_t RESERVED_26[43];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_27[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48M oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_28[23];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base)                      ((base)->PERID)
+#define USB_IDCOMP_REG(base)                     ((base)->IDCOMP)
+#define USB_REV_REG(base)                        ((base)->REV)
+#define USB_ADDINFO_REG(base)                    ((base)->ADDINFO)
+#define USB_OTGISTAT_REG(base)                   ((base)->OTGISTAT)
+#define USB_OTGICR_REG(base)                     ((base)->OTGICR)
+#define USB_OTGSTAT_REG(base)                    ((base)->OTGSTAT)
+#define USB_OTGCTL_REG(base)                     ((base)->OTGCTL)
+#define USB_ISTAT_REG(base)                      ((base)->ISTAT)
+#define USB_INTEN_REG(base)                      ((base)->INTEN)
+#define USB_ERRSTAT_REG(base)                    ((base)->ERRSTAT)
+#define USB_ERREN_REG(base)                      ((base)->ERREN)
+#define USB_STAT_REG(base)                       ((base)->STAT)
+#define USB_CTL_REG(base)                        ((base)->CTL)
+#define USB_ADDR_REG(base)                       ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base)                   ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base)                    ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base)                    ((base)->FRMNUMH)
+#define USB_TOKEN_REG(base)                      ((base)->TOKEN)
+#define USB_SOFTHLD_REG(base)                    ((base)->SOFTHLD)
+#define USB_BDTPAGE2_REG(base)                   ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base)                   ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index)                ((base)->ENDPOINT[index].ENDPT)
+#define USB_ENDPT_COUNT                          16
+#define USB_USBCTRL_REG(base)                    ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base)                    ((base)->OBSERVE)
+#define USB_CONTROL_REG(base)                    ((base)->CONTROL)
+#define USB_USBTRC0_REG(base)                    ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base)               ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base)           ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base)         ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base)     ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK                        0x3Fu
+#define USB_PERID_ID_SHIFT                       0
+#define USB_PERID_ID_WIDTH                       6
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK                      0x3Fu
+#define USB_IDCOMP_NID_SHIFT                     0
+#define USB_IDCOMP_NID_WIDTH                     6
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK                         0xFFu
+#define USB_REV_REV_SHIFT                        0
+#define USB_REV_REV_WIDTH                        8
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK                  0x1u
+#define USB_ADDINFO_IEHOST_SHIFT                 0
+#define USB_ADDINFO_IEHOST_WIDTH                 1
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
+#define USB_ADDINFO_IRQNUM_MASK                  0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT                 3
+#define USB_ADDINFO_IRQNUM_WIDTH                 5
+#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK               0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT              0
+#define USB_OTGISTAT_AVBUSCHG_WIDTH              1
+#define USB_OTGISTAT_AVBUSCHG(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_AVBUSCHG_SHIFT))&USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK             0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT            2
+#define USB_OTGISTAT_B_SESS_CHG_WIDTH            1
+#define USB_OTGISTAT_B_SESS_CHG(x)               (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_B_SESS_CHG_SHIFT))&USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK             0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT            3
+#define USB_OTGISTAT_SESSVLDCHG_WIDTH            1
+#define USB_OTGISTAT_SESSVLDCHG(x)               (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_SESSVLDCHG_SHIFT))&USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK         0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        5
+#define USB_OTGISTAT_LINE_STATE_CHG_WIDTH        1
+#define USB_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK                0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT               6
+#define USB_OTGISTAT_ONEMSEC_WIDTH               1
+#define USB_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK                  0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT                 7
+#define USB_OTGISTAT_IDCHG_WIDTH                 1
+#define USB_OTGISTAT_IDCHG(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_IDCHG_SHIFT))&USB_OTGISTAT_IDCHG_MASK)
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK                  0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT                 0
+#define USB_OTGICR_AVBUSEN_WIDTH                 1
+#define USB_OTGICR_AVBUSEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_AVBUSEN_SHIFT))&USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK                  0x4u
+#define USB_OTGICR_BSESSEN_SHIFT                 2
+#define USB_OTGICR_BSESSEN_WIDTH                 1
+#define USB_OTGICR_BSESSEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_BSESSEN_SHIFT))&USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK                0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT               3
+#define USB_OTGICR_SESSVLDEN_WIDTH               1
+#define USB_OTGICR_SESSVLDEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_SESSVLDEN_SHIFT))&USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK              0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT             5
+#define USB_OTGICR_LINESTATEEN_WIDTH             1
+#define USB_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK                0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT               6
+#define USB_OTGICR_ONEMSECEN_WIDTH               1
+#define USB_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK                     0x80u
+#define USB_OTGICR_IDEN_SHIFT                    7
+#define USB_OTGICR_IDEN_WIDTH                    1
+#define USB_OTGICR_IDEN(x)                       (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_IDEN_SHIFT))&USB_OTGICR_IDEN_MASK)
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK                0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT               0
+#define USB_OTGSTAT_AVBUSVLD_WIDTH               1
+#define USB_OTGSTAT_AVBUSVLD(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_AVBUSVLD_SHIFT))&USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK                0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT               2
+#define USB_OTGSTAT_BSESSEND_WIDTH               1
+#define USB_OTGSTAT_BSESSEND(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_BSESSEND_SHIFT))&USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK                0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT               3
+#define USB_OTGSTAT_SESS_VLD_WIDTH               1
+#define USB_OTGSTAT_SESS_VLD(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_SESS_VLD_SHIFT))&USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK         0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        5
+#define USB_OTGSTAT_LINESTATESTABLE_WIDTH        1
+#define USB_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK               0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT              6
+#define USB_OTGSTAT_ONEMSECEN_WIDTH              1
+#define USB_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK                      0x80u
+#define USB_OTGSTAT_ID_SHIFT                     7
+#define USB_OTGSTAT_ID_WIDTH                     1
+#define USB_OTGSTAT_ID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ID_SHIFT))&USB_OTGSTAT_ID_MASK)
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK                    0x4u
+#define USB_OTGCTL_OTGEN_SHIFT                   2
+#define USB_OTGCTL_OTGEN_WIDTH                   1
+#define USB_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK                    0x10u
+#define USB_OTGCTL_DMLOW_SHIFT                   4
+#define USB_OTGCTL_DMLOW_WIDTH                   1
+#define USB_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK                    0x20u
+#define USB_OTGCTL_DPLOW_SHIFT                   5
+#define USB_OTGCTL_DPLOW_WIDTH                   1
+#define USB_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK                   0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT                  7
+#define USB_OTGCTL_DPHIGH_WIDTH                  1
+#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK                    0x1u
+#define USB_ISTAT_USBRST_SHIFT                   0
+#define USB_ISTAT_USBRST_WIDTH                   1
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK                     0x2u
+#define USB_ISTAT_ERROR_SHIFT                    1
+#define USB_ISTAT_ERROR_WIDTH                    1
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK                    0x4u
+#define USB_ISTAT_SOFTOK_SHIFT                   2
+#define USB_ISTAT_SOFTOK_WIDTH                   1
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK                    0x8u
+#define USB_ISTAT_TOKDNE_SHIFT                   3
+#define USB_ISTAT_TOKDNE_WIDTH                   1
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK                     0x10u
+#define USB_ISTAT_SLEEP_SHIFT                    4
+#define USB_ISTAT_SLEEP_WIDTH                    1
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK                    0x20u
+#define USB_ISTAT_RESUME_SHIFT                   5
+#define USB_ISTAT_RESUME_WIDTH                   1
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK                    0x40u
+#define USB_ISTAT_ATTACH_SHIFT                   6
+#define USB_ISTAT_ATTACH_WIDTH                   1
+#define USB_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK                     0x80u
+#define USB_ISTAT_STALL_SHIFT                    7
+#define USB_ISTAT_STALL_WIDTH                    1
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK                  0x1u
+#define USB_INTEN_USBRSTEN_SHIFT                 0
+#define USB_INTEN_USBRSTEN_WIDTH                 1
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK                   0x2u
+#define USB_INTEN_ERROREN_SHIFT                  1
+#define USB_INTEN_ERROREN_WIDTH                  1
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK                  0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT                 2
+#define USB_INTEN_SOFTOKEN_WIDTH                 1
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK                  0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT                 3
+#define USB_INTEN_TOKDNEEN_WIDTH                 1
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK                   0x10u
+#define USB_INTEN_SLEEPEN_SHIFT                  4
+#define USB_INTEN_SLEEPEN_WIDTH                  1
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK                  0x20u
+#define USB_INTEN_RESUMEEN_SHIFT                 5
+#define USB_INTEN_RESUMEEN_WIDTH                 1
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK                  0x40u
+#define USB_INTEN_ATTACHEN_SHIFT                 6
+#define USB_INTEN_ATTACHEN_WIDTH                 1
+#define USB_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK                   0x80u
+#define USB_INTEN_STALLEN_SHIFT                  7
+#define USB_INTEN_STALLEN_WIDTH                  1
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK                  0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT                 0
+#define USB_ERRSTAT_PIDERR_WIDTH                 1
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK                 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT                1
+#define USB_ERRSTAT_CRC5EOF_WIDTH                1
+#define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK                   0x4u
+#define USB_ERRSTAT_CRC16_SHIFT                  2
+#define USB_ERRSTAT_CRC16_WIDTH                  1
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK                    0x8u
+#define USB_ERRSTAT_DFN8_SHIFT                   3
+#define USB_ERRSTAT_DFN8_WIDTH                   1
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK                  0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT                 4
+#define USB_ERRSTAT_BTOERR_WIDTH                 1
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK                  0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT                 5
+#define USB_ERRSTAT_DMAERR_WIDTH                 1
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK                  0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT                 7
+#define USB_ERRSTAT_BTSERR_WIDTH                 1
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK                  0x1u
+#define USB_ERREN_PIDERREN_SHIFT                 0
+#define USB_ERREN_PIDERREN_WIDTH                 1
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK                 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT                1
+#define USB_ERREN_CRC5EOFEN_WIDTH                1
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK                   0x4u
+#define USB_ERREN_CRC16EN_SHIFT                  2
+#define USB_ERREN_CRC16EN_WIDTH                  1
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK                    0x8u
+#define USB_ERREN_DFN8EN_SHIFT                   3
+#define USB_ERREN_DFN8EN_WIDTH                   1
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK                  0x10u
+#define USB_ERREN_BTOERREN_SHIFT                 4
+#define USB_ERREN_BTOERREN_WIDTH                 1
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK                  0x20u
+#define USB_ERREN_DMAERREN_SHIFT                 5
+#define USB_ERREN_DMAERREN_WIDTH                 1
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK                  0x80u
+#define USB_ERREN_BTSERREN_SHIFT                 7
+#define USB_ERREN_BTSERREN_WIDTH                 1
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK                        0x4u
+#define USB_STAT_ODD_SHIFT                       2
+#define USB_STAT_ODD_WIDTH                       1
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK                         0x8u
+#define USB_STAT_TX_SHIFT                        3
+#define USB_STAT_TX_WIDTH                        1
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK                       0xF0u
+#define USB_STAT_ENDP_SHIFT                      4
+#define USB_STAT_ENDP_WIDTH                      4
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK                  0x1u
+#define USB_CTL_USBENSOFEN_SHIFT                 0
+#define USB_CTL_USBENSOFEN_WIDTH                 1
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK                      0x2u
+#define USB_CTL_ODDRST_SHIFT                     1
+#define USB_CTL_ODDRST_WIDTH                     1
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK                      0x4u
+#define USB_CTL_RESUME_SHIFT                     2
+#define USB_CTL_RESUME_WIDTH                     1
+#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK                  0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT                 3
+#define USB_CTL_HOSTMODEEN_WIDTH                 1
+#define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK                       0x10u
+#define USB_CTL_RESET_SHIFT                      4
+#define USB_CTL_RESET_WIDTH                      1
+#define USB_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
+#define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH         1
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK                         0x40u
+#define USB_CTL_SE0_SHIFT                        6
+#define USB_CTL_SE0_WIDTH                        1
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK                      0x80u
+#define USB_CTL_JSTATE_SHIFT                     7
+#define USB_CTL_JSTATE_WIDTH                     1
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK                       0x7Fu
+#define USB_ADDR_ADDR_SHIFT                      0
+#define USB_ADDR_ADDR_WIDTH                      7
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK                       0x80u
+#define USB_ADDR_LSEN_SHIFT                      7
+#define USB_ADDR_LSEN_WIDTH                      1
+#define USB_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT                 1
+#define USB_BDTPAGE1_BDTBA_WIDTH                 7
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK                     0xFFu
+#define USB_FRMNUML_FRM_SHIFT                    0
+#define USB_FRMNUML_FRM_WIDTH                    8
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK                     0x7u
+#define USB_FRMNUMH_FRM_SHIFT                    0
+#define USB_FRMNUMH_FRM_WIDTH                    3
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK                0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT               0
+#define USB_TOKEN_TOKENENDPT_WIDTH               4
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT                 4
+#define USB_TOKEN_TOKENPID_WIDTH                 4
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK                     0xFFu
+#define USB_SOFTHLD_CNT_SHIFT                    0
+#define USB_SOFTHLD_CNT_WIDTH                    8
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT                 0
+#define USB_BDTPAGE2_BDTBA_WIDTH                 8
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT                 0
+#define USB_BDTPAGE3_BDTBA_WIDTH                 8
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK                    0x1u
+#define USB_ENDPT_EPHSHK_SHIFT                   0
+#define USB_ENDPT_EPHSHK_WIDTH                   1
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK                   0x2u
+#define USB_ENDPT_EPSTALL_SHIFT                  1
+#define USB_ENDPT_EPSTALL_WIDTH                  1
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK                    0x4u
+#define USB_ENDPT_EPTXEN_SHIFT                   2
+#define USB_ENDPT_EPTXEN_WIDTH                   1
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK                    0x8u
+#define USB_ENDPT_EPRXEN_SHIFT                   3
+#define USB_ENDPT_EPRXEN_WIDTH                   1
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK                  0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT                 4
+#define USB_ENDPT_EPCTLDIS_WIDTH                 1
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK                  0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT                 6
+#define USB_ENDPT_RETRYDIS_WIDTH                 1
+#define USB_ENDPT_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK                 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT                7
+#define USB_ENDPT_HOSTWOHUB_WIDTH                1
+#define USB_ENDPT_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK                     0x40u
+#define USB_USBCTRL_PDE_SHIFT                    6
+#define USB_USBCTRL_PDE_WIDTH                    1
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK                    0x80u
+#define USB_USBCTRL_SUSP_SHIFT                   7
+#define USB_USBCTRL_SUSP_WIDTH                   1
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK                    0x10u
+#define USB_OBSERVE_DMPD_SHIFT                   4
+#define USB_OBSERVE_DMPD_WIDTH                   1
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK                    0x40u
+#define USB_OBSERVE_DPPD_SHIFT                   6
+#define USB_OBSERVE_DPPD_WIDTH                   1
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK                    0x80u
+#define USB_OBSERVE_DPPU_SHIFT                   7
+#define USB_OBSERVE_DPPU_WIDTH                   1
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
+#define USB_CONTROL_DPPULLUPNONOTG_WIDTH         1
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
+#define USB_USBTRC0_USB_RESUME_INT_WIDTH         1
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK                0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT               1
+#define USB_USBTRC0_SYNC_DET_WIDTH               1
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   2
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH   1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))&USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK               0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT              5
+#define USB_USBTRC0_USBRESMEN_WIDTH              1
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK                0x80u
+#define USB_USBTRC0_USBRESET_SHIFT               7
+#define USB_USBTRC0_USBRESET_WIDTH               1
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK                0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT               0
+#define USB_USBFRMADJUST_ADJ_WIDTH               8
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))&USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK       0x1u
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      0
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH 1
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))&USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR                            (USB0)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID                               USB_PERID_REG(USB0)
+#define USB0_IDCOMP                              USB_IDCOMP_REG(USB0)
+#define USB0_REV                                 USB_REV_REG(USB0)
+#define USB0_ADDINFO                             USB_ADDINFO_REG(USB0)
+#define USB0_OTGISTAT                            USB_OTGISTAT_REG(USB0)
+#define USB0_OTGICR                              USB_OTGICR_REG(USB0)
+#define USB0_OTGSTAT                             USB_OTGSTAT_REG(USB0)
+#define USB0_OTGCTL                              USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT                               USB_ISTAT_REG(USB0)
+#define USB0_INTEN                               USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT                             USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN                               USB_ERREN_REG(USB0)
+#define USB0_STAT                                USB_STAT_REG(USB0)
+#define USB0_CTL                                 USB_CTL_REG(USB0)
+#define USB0_ADDR                                USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1                            USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML                             USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH                             USB_FRMNUMH_REG(USB0)
+#define USB0_TOKEN                               USB_TOKEN_REG(USB0)
+#define USB0_SOFTHLD                             USB_SOFTHLD_REG(USB0)
+#define USB0_BDTPAGE2                            USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3                            USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0                              USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1                              USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2                              USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3                              USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4                              USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5                              USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6                              USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7                              USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8                              USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9                              USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10                             USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11                             USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12                             USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13                             USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14                             USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15                             USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL                             USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE                             USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL                             USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0                             USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST                        USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL                    USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN                  USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS              USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index)                        USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
+  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
+  __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
+  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
+  union {                                          /* offset: 0x18 */
+    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
+    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
+  };
+} USBDCD_Type, *USBDCD_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register accessors */
+#define USBDCD_CONTROL_REG(base)                 ((base)->CONTROL)
+#define USBDCD_CLOCK_REG(base)                   ((base)->CLOCK)
+#define USBDCD_STATUS_REG(base)                  ((base)->STATUS)
+#define USBDCD_TIMER0_REG(base)                  ((base)->TIMER0)
+#define USBDCD_TIMER1_REG(base)                  ((base)->TIMER1)
+#define USBDCD_TIMER2_BC11_REG(base)             ((base)->TIMER2_BC11)
+#define USBDCD_TIMER2_BC12_REG(base)             ((base)->TIMER2_BC12)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK                 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT                0
+#define USBDCD_CONTROL_IACK_WIDTH                1
+#define USBDCD_CONTROL_IACK(x)                   (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IACK_SHIFT))&USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IF_MASK                   0x100u
+#define USBDCD_CONTROL_IF_SHIFT                  8
+#define USBDCD_CONTROL_IF_WIDTH                  1
+#define USBDCD_CONTROL_IF(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IF_SHIFT))&USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IE_MASK                   0x10000u
+#define USBDCD_CONTROL_IE_SHIFT                  16
+#define USBDCD_CONTROL_IE_WIDTH                  1
+#define USBDCD_CONTROL_IE(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IE_SHIFT))&USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_BC12_MASK                 0x20000u
+#define USBDCD_CONTROL_BC12_SHIFT                17
+#define USBDCD_CONTROL_BC12_WIDTH                1
+#define USBDCD_CONTROL_BC12(x)                   (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_BC12_SHIFT))&USBDCD_CONTROL_BC12_MASK)
+#define USBDCD_CONTROL_START_MASK                0x1000000u
+#define USBDCD_CONTROL_START_SHIFT               24
+#define USBDCD_CONTROL_START_WIDTH               1
+#define USBDCD_CONTROL_START(x)                  (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_START_SHIFT))&USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_SR_MASK                   0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT                  25
+#define USBDCD_CONTROL_SR_WIDTH                  1
+#define USBDCD_CONTROL_SR(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_SR_SHIFT))&USBDCD_CONTROL_SR_MASK)
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK             0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            0
+#define USBDCD_CLOCK_CLOCK_UNIT_WIDTH            1
+#define USBDCD_CLOCK_CLOCK_UNIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_UNIT_SHIFT))&USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK            0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           2
+#define USBDCD_CLOCK_CLOCK_SPEED_WIDTH           10
+#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK               0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT              16
+#define USBDCD_STATUS_SEQ_RES_WIDTH              2
+#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK              0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT             18
+#define USBDCD_STATUS_SEQ_STAT_WIDTH             2
+#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK                   0x100000u
+#define USBDCD_STATUS_ERR_SHIFT                  20
+#define USBDCD_STATUS_ERR_WIDTH                  1
+#define USBDCD_STATUS_ERR(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ERR_SHIFT))&USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_TO_MASK                    0x200000u
+#define USBDCD_STATUS_TO_SHIFT                   21
+#define USBDCD_STATUS_TO_WIDTH                   1
+#define USBDCD_STATUS_TO(x)                      (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_TO_SHIFT))&USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_ACTIVE_MASK                0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT               22
+#define USBDCD_STATUS_ACTIVE_WIDTH               1
+#define USBDCD_STATUS_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ACTIVE_SHIFT))&USBDCD_STATUS_ACTIVE_MASK)
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK              0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT             0
+#define USBDCD_TIMER0_TUNITCON_WIDTH             12
+#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK             0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            16
+#define USBDCD_TIMER0_TSEQ_INIT_WIDTH            10
+#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK            0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           0
+#define USBDCD_TIMER1_TVDPSRC_ON_WIDTH           10
+#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK             0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            16
+#define USBDCD_TIMER1_TDCD_DBNC_WIDTH            10
+#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2_BC11 Bit Fields */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK         0xFu
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        0
+#define USBDCD_TIMER2_BC11_CHECK_DM_WIDTH        4
+#define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      0x3FF0000u
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     16
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_WIDTH     10
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+/* TIMER2_BC12 Bit Fields */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       0x3FFu
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      0
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_WIDTH      10
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  0x3FF0000u
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_WIDTH 10
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE                              (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD                                   ((USBDCD_Type *)USBDCD_BASE)
+#define USBDCD_BASE_PTR                          (USBDCD)
+/** Array initializer of USBDCD peripheral base addresses */
+#define USBDCD_BASE_ADDRS                        { USBDCD_BASE }
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASE_PTRS                         { USBDCD }
+/** Interrupt vectors for the USBDCD peripheral type */
+#define USBDCD_IRQS                              { USBDCD_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register instance definitions */
+/* USBDCD */
+#define USBDCD_CONTROL                           USBDCD_CONTROL_REG(USBDCD)
+#define USBDCD_CLOCK                             USBDCD_CLOCK_REG(USBDCD)
+#define USBDCD_STATUS                            USBDCD_STATUS_REG(USBDCD)
+#define USBDCD_TIMER0                            USBDCD_TIMER0_REG(USBDCD)
+#define USBDCD_TIMER1                            USBDCD_TIMER1_REG(USBDCD)
+#define USBDCD_TIMER2_BC11                       USBDCD_TIMER2_BC11_REG(USBDCD)
+#define USBDCD_TIMER2_BC12                       USBDCD_TIMER2_BC12_REG(USBDCD)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base)                       ((base)->TRM)
+#define VREF_SC_REG(base)                        ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK                       0x3Fu
+#define VREF_TRM_TRIM_SHIFT                      0
+#define VREF_TRM_TRIM_WIDTH                      6
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     0x40u
+#define VREF_TRM_CHOPEN_SHIFT                    6
+#define VREF_TRM_CHOPEN_WIDTH                    1
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_TRM_CHOPEN_SHIFT))&VREF_TRM_CHOPEN_MASK)
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK                     0x3u
+#define VREF_SC_MODE_LV_SHIFT                    0
+#define VREF_SC_MODE_LV_WIDTH                    2
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      0x4u
+#define VREF_SC_VREFST_SHIFT                     2
+#define VREF_SC_VREFST_WIDTH                     1
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFST_SHIFT))&VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK                     0x20u
+#define VREF_SC_ICOMPEN_SHIFT                    5
+#define VREF_SC_ICOMPEN_WIDTH                    1
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_ICOMPEN_SHIFT))&VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK                       0x40u
+#define VREF_SC_REGEN_SHIFT                      6
+#define VREF_SC_REGEN_WIDTH                      1
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_SC_REGEN_SHIFT))&VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK                      0x80u
+#define VREF_SC_VREFEN_SHIFT                     7
+#define VREF_SC_VREFEN_WIDTH                     1
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFEN_SHIFT))&VREF_SC_VREFEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR                            (VREF)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM                                 VREF_TRM_REG(VREF)
+#define VREF_SC                                  VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t STCTRLH;                           /**< Watchdog Status and Control Register High, offset: 0x0 */
+  __IO uint16_t STCTRLL;                           /**< Watchdog Status and Control Register Low, offset: 0x2 */
+  __IO uint16_t TOVALH;                            /**< Watchdog Time-out Value Register High, offset: 0x4 */
+  __IO uint16_t TOVALL;                            /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+  __IO uint16_t WINH;                              /**< Watchdog Window Register High, offset: 0x8 */
+  __IO uint16_t WINL;                              /**< Watchdog Window Register Low, offset: 0xA */
+  __IO uint16_t REFRESH;                           /**< Watchdog Refresh register, offset: 0xC */
+  __IO uint16_t UNLOCK;                            /**< Watchdog Unlock register, offset: 0xE */
+  __IO uint16_t TMROUTH;                           /**< Watchdog Timer Output Register High, offset: 0x10 */
+  __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
+  __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
+  __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type, *WDOG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register accessors */
+#define WDOG_STCTRLH_REG(base)                   ((base)->STCTRLH)
+#define WDOG_STCTRLL_REG(base)                   ((base)->STCTRLL)
+#define WDOG_TOVALH_REG(base)                    ((base)->TOVALH)
+#define WDOG_TOVALL_REG(base)                    ((base)->TOVALL)
+#define WDOG_WINH_REG(base)                      ((base)->WINH)
+#define WDOG_WINL_REG(base)                      ((base)->WINL)
+#define WDOG_REFRESH_REG(base)                   ((base)->REFRESH)
+#define WDOG_UNLOCK_REG(base)                    ((base)->UNLOCK)
+#define WDOG_TMROUTH_REG(base)                   ((base)->TMROUTH)
+#define WDOG_TMROUTL_REG(base)                   ((base)->TMROUTL)
+#define WDOG_RSTCNT_REG(base)                    ((base)->RSTCNT)
+#define WDOG_PRESC_REG(base)                     ((base)->PRESC)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK                 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT                0
+#define WDOG_STCTRLH_WDOGEN_WIDTH                1
+#define WDOG_STCTRLH_WDOGEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WDOGEN_SHIFT))&WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK                 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT                1
+#define WDOG_STCTRLH_CLKSRC_WIDTH                1
+#define WDOG_STCTRLH_CLKSRC(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_CLKSRC_SHIFT))&WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK               0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT              2
+#define WDOG_STCTRLH_IRQRSTEN_WIDTH              1
+#define WDOG_STCTRLH_IRQRSTEN(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_IRQRSTEN_SHIFT))&WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK                  0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT                 3
+#define WDOG_STCTRLH_WINEN_WIDTH                 1
+#define WDOG_STCTRLH_WINEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WINEN_SHIFT))&WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK            0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           4
+#define WDOG_STCTRLH_ALLOWUPDATE_WIDTH           1
+#define WDOG_STCTRLH_ALLOWUPDATE(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_ALLOWUPDATE_SHIFT))&WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK                  0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT                 5
+#define WDOG_STCTRLH_DBGEN_WIDTH                 1
+#define WDOG_STCTRLH_DBGEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DBGEN_SHIFT))&WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK                 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT                6
+#define WDOG_STCTRLH_STOPEN_WIDTH                1
+#define WDOG_STCTRLH_STOPEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_STOPEN_SHIFT))&WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK                 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT                7
+#define WDOG_STCTRLH_WAITEN_WIDTH                1
+#define WDOG_STCTRLH_WAITEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WAITEN_SHIFT))&WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK               0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT              10
+#define WDOG_STCTRLH_TESTWDOG_WIDTH              1
+#define WDOG_STCTRLH_TESTWDOG(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTWDOG_SHIFT))&WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK                0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT               11
+#define WDOG_STCTRLH_TESTSEL_WIDTH               1
+#define WDOG_STCTRLH_TESTSEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTSEL_SHIFT))&WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK                0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT               12
+#define WDOG_STCTRLH_BYTESEL_WIDTH               2
+#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK            0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT           14
+#define WDOG_STCTRLH_DISTESTWDOG_WIDTH           1
+#define WDOG_STCTRLH_DISTESTWDOG(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DISTESTWDOG_SHIFT))&WDOG_STCTRLH_DISTESTWDOG_MASK)
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK                 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT                15
+#define WDOG_STCTRLL_INTFLG_WIDTH                1
+#define WDOG_STCTRLL_INTFLG(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLL_INTFLG_SHIFT))&WDOG_STCTRLL_INTFLG_MASK)
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK               0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              0
+#define WDOG_TOVALH_TOVALHIGH_WIDTH              16
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK                0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT               0
+#define WDOG_TOVALL_TOVALLOW_WIDTH               16
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK                   0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT                  0
+#define WDOG_WINH_WINHIGH_WIDTH                  16
+#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK                    0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT                   0
+#define WDOG_WINL_WINLOW_WIDTH                   16
+#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK            0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT           0
+#define WDOG_REFRESH_WDOGREFRESH_WIDTH           16
+#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK              0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             0
+#define WDOG_UNLOCK_WDOGUNLOCK_WIDTH             16
+#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK           0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          0
+#define WDOG_TMROUTH_TIMEROUTHIGH_WIDTH          16
+#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK            0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           0
+#define WDOG_TMROUTL_TIMEROUTLOW_WIDTH           16
+#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK                  0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT                 0
+#define WDOG_RSTCNT_RSTCNT_WIDTH                 16
+#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK                 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT                8
+#define WDOG_PRESC_PRESCVAL_WIDTH                3
+#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+#define WDOG_BASE_PTR                            (WDOG)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS                          { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS                           { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS                                { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register instance definitions */
+/* WDOG */
+#define WDOG_STCTRLH                             WDOG_STCTRLH_REG(WDOG)
+#define WDOG_STCTRLL                             WDOG_STCTRLL_REG(WDOG)
+#define WDOG_TOVALH                              WDOG_TOVALH_REG(WDOG)
+#define WDOG_TOVALL                              WDOG_TOVALL_REG(WDOG)
+#define WDOG_WINH                                WDOG_WINH_REG(WDOG)
+#define WDOG_WINL                                WDOG_WINL_REG(WDOG)
+#define WDOG_REFRESH                             WDOG_REFRESH_REG(WDOG)
+#define WDOG_UNLOCK                              WDOG_UNLOCK_REG(WDOG)
+#define WDOG_TMROUTH                             WDOG_TMROUTH_REG(WDOG)
+#define WDOG_TMROUTL                             WDOG_TMROUTL_REG(WDOG)
+#define WDOG_RSTCNT                              WDOG_RSTCNT_REG(WDOG)
+#define WDOG_PRESC                               WDOG_PRESC_REG(WDOG)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Backward Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define DMA_EARS_REG(base)                       This_symbol_has_been_deprecated
+#define DMA_EARS                                 This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_SHIFT                  This_symbol_has_been_deprecated
+#define ENET_RMON_T_DROP_REG(base)               This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP_REG(base)               This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE_REG(base)                This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0_REG(base)            This_symbol_has_been_deprecated
+#define ENET_RMON_R_DROP_REG(base)               ENET_IEEE_R_DROP_REG(base)
+#define ENET_RMON_R_FRAME_OK_REG(base)           ENET_IEEE_R_FRAME_OK_REG(base)
+#define ENET_RMON_T_DROP                         This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP                         This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE                          This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0                      This_symbol_has_been_deprecated
+#define MCG_C9_REG(base)                         This_symbol_has_been_deprecated
+#define MCG_C2_EREFS0_MASK                       MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT                      MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK                         MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT                        MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK                       MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT                      MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x)                         MCG_C2_RANGE(x)
+#define MCG_C9                                   This_symbol_has_been_deprecated
+#define MCM_PLACR_REG(base)                      This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_MASK                       This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_SHIFT                      This_symbol_has_been_deprecated
+#define MCM_PLACR                                This_symbol_has_been_deprecated
+#define ADC_BASES                    ADC_BASE_PTRS
+#define AIPS_BASES                   AIPS_BASE_PTRS
+#define AXBS_BASES                   AXBS_BASE_PTRS
+#define CAN_BASES                    CAN_BASE_PTRS
+#define CAU_BASES                    CAU_BASE_PTRS
+#define CMP_BASES                    CMP_BASE_PTRS
+#define CMT_BASES                    CMT_BASE_PTRS
+#define CRC_BASES                    CRC_BASE_PTRS
+#define DAC_BASES                    DAC_BASE_PTRS
+#define DMA_BASES                    DMA_BASE_PTRS
+#define DMAMUX_BASES                 DMAMUX_BASE_PTRS
+#define ENET_BASES                   ENET_BASE_PTRS
+#define EWM_BASES                    EWM_BASE_PTRS
+#define FB_BASES                     FB_BASE_PTRS
+#define FMC_BASES                    FMC_BASE_PTRS
+#define FTFE_BASES                   FTFE_BASE_PTRS
+#define FTM_BASES                    FTM_BASE_PTRS
+#define GPIO_BASES                   GPIO_BASE_PTRS
+#define I2C_BASES                    I2C_BASE_PTRS
+#define I2S_BASES                    I2S_BASE_PTRS
+#define LLWU_BASES                   LLWU_BASE_PTRS
+#define LPTMR_BASES                  LPTMR_BASE_PTRS
+#define MCG_BASES                    MCG_BASE_PTRS
+#define MCM_ISR_REG(base)            MCM_ISCR_REG(base)
+#define MCM_ISR_FIOC_MASK            MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT           MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK            MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT           MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK            MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT           MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK            MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT           MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK            MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT           MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK            MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT           MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK           MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT          MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK           MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT          MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK           MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT          MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK           MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT          MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK           MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT          MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK           MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT          MCM_ISCR_FIDCE_SHIFT
+#define MCM_BASES                    MCM_BASE_PTRS
+#define MPU_BASES                    MPU_BASE_PTRS
+#define NV_BASES                     NV_BASE_PTRS
+#define OSC_BASES                    OSC_BASE_PTRS
+#define PDB_BASES                    PDB_BASE_PTRS
+#define PIT_BASES                    PIT_BASE_PTRS
+#define PMC_BASES                    PMC_BASE_PTRS
+#define PORT_BASES                   PORT_BASE_PTRS
+#define RCM_BASES                    RCM_BASE_PTRS
+#define RFSYS_BASES                  RFSYS_BASE_PTRS
+#define RFVBAT_BASES                 RFVBAT_BASE_PTRS
+#define RNG_BASES                    RNG_BASE_PTRS
+#define RTC_BASES                    RTC_BASE_PTRS
+#define SDHC_BASES                   SDHC_BASE_PTRS
+#define SIM_BASES                    SIM_BASE_PTRS
+#define SMC_BASES                    SMC_BASE_PTRS
+#define SPI_BASES                    SPI_BASE_PTRS
+#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
+#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
+#define UART_WP7816_T_TYPE0_WI_MASK  UART_WP7816T0_WI_MASK
+#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
+#define UART_WP7816_T_TYPE0_WI(x)    UART_WP7816T0_WI(x)
+#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
+#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
+#define UART_WP7816_T_TYPE1_BWI(x)   UART_WP7816T1_BWI(x)
+#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
+#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
+#define UART_WP7816_T_TYPE1_CWI(x)   UART_WP7816T1_CWI(x)
+#define UART_BASES                   UART_BASE_PTRS
+#define USB_BASES                    USB_BASE_PTRS
+#define USBDCD_BASES                 USBDCD_BASE_PTRS
+#define VREF_BASES                   VREF_BASE_PTRS
+#define WDOG_BASES                   WDOG_BASE_PTRS
+#define Watchdog_IRQn                WDOG_EWM_IRQn
+#define Watchdog_IRQHandler          WDOG_EWM_IRQHandler
+#define LPTimer_IRQn                 LPTMR0_IRQn
+#define LPTimer_IRQHandler           LPTMR0_IRQHandler
+#define LLW_IRQn                     LLWU_IRQn
+#define LLW_IRQHandler               LLWU_IRQHandler
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MK64F12_H_) */
+  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+  #if (MCU_MEM_MAP_VERSION != 0x0200u)
+    #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+      #warning There are included two not compatible versions of memory maps. Please check possible differences.
+    #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+  #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
+#endif  /* #if !defined(MK64F12_H_) */
+
+/* MK64F12.h, eof. */
diff --git a/Workspace/GPIO/SDK/platform/devices/MK64F12/include/MK64F12_extension.h b/Workspace/GPIO/SDK/platform/devices/MK64F12/include/MK64F12_extension.h
new file mode 100644
index 0000000..c47b6c4
--- /dev/null
+++ b/Workspace/GPIO/SDK/platform/devices/MK64F12/include/MK64F12_extension.h
@@ -0,0 +1,63846 @@
+/*
+** ###################################################################
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150612
+**
+**     Abstract:
+**         Extension to the CMSIS register access layer header.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __MK64F12_EXTENSION_H__
+#define __MK64F12_EXTENSION_H__
+
+#include "MK64F12.h"
+#include "fsl_bitaccess.h"
+
+#if defined(__IAR_SYSTEMS_ICC__)
+  /*
+   * Suppress "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)"
+   * as some register descriptions contain code examples
+   */
+  #pragma diag_suppress=pm008
+#endif
+
+/*
+ * MK64F12 ADC
+ *
+ * Analog-to-Digital Converter
+ *
+ * Registers defined in this header file:
+ * - ADC_SC1 - ADC Status and Control Registers 1
+ * - ADC_CFG1 - ADC Configuration Register 1
+ * - ADC_CFG2 - ADC Configuration Register 2
+ * - ADC_R - ADC Data Result Register
+ * - ADC_CV1 - Compare Value Registers
+ * - ADC_CV2 - Compare Value Registers
+ * - ADC_SC2 - Status and Control Register 2
+ * - ADC_SC3 - Status and Control Register 3
+ * - ADC_OFS - ADC Offset Correction Register
+ * - ADC_PG - ADC Plus-Side Gain Register
+ * - ADC_MG - ADC Minus-Side Gain Register
+ * - ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ */
+
+#define ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
+#define ADC0_IDX (0U) /*!< Instance number for ADC0. */
+#define ADC1_IDX (1U) /*!< Instance number for ADC1. */
+
+/*******************************************************************************
+ * ADC_SC1 - ADC Status and Control Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC1 - ADC Status and Control Registers 1 (RW)
+ *
+ * Reset value: 0x0000001FU
+ *
+ * SC1A is used for both software and hardware trigger modes of operation. To
+ * allow sequential conversions of the ADC to be triggered by internal peripherals,
+ * the ADC can have more than one status and control register: one for each
+ * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
+ * for use only in hardware trigger mode. See the chip configuration information
+ * about the number of SC1n registers specific to this device. The SC1n registers
+ * have identical fields, and are used in a "ping-pong" approach to control ADC
+ * operation. At any one point in time, only one of the SC1n registers is actively
+ * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
+ * a conversion is allowed, and vice-versa for any of the SC1n registers specific
+ * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
+ * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
+ * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
+ * value other than all 1s. Writing any of the SC1n registers while that specific
+ * SC1n register is actively controlling a conversion aborts the current conversion.
+ * None of the SC1B-SC1n registers are used for software trigger operation and
+ * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC1 register
+ */
+/*@{*/
+#define ADC_RD_SC1(base, index)  (ADC_SC1_REG(base, index))
+#define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value))
+#define ADC_RMW_SC1(base, index, mask, value) (ADC_WR_SC1(base, index, (ADC_RD_SC1(base, index) & ~(mask)) | (value)))
+#define ADC_SET_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) |  (value)))
+#define ADC_CLR_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) & ~(value)))
+#define ADC_TOG_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC1 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC1, field ADCH[4:0] (RW)
+ *
+ * Selects one of the input channels. The input channel decode depends on the
+ * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
+ * DADMx. Some of the input channel options in the bitfield-setting descriptions might
+ * not be available for your device. For the actual ADC channel assignments for
+ * your device, see the Chip Configuration details. The successive approximation
+ * converter subsystem is turned off when the channel select bits are all set,
+ * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
+ * isolation of the input channel from all sources. Terminating continuous
+ * conversions this way prevents an additional single conversion from being performed. It
+ * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
+ * when continuous conversions are not enabled because the module automatically
+ * enters a low-power state when a conversion completes.
+ *
+ * Values:
+ * - 0b00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
+ *     selected as input.
+ * - 0b00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
+ *     selected as input.
+ * - 0b00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
+ *     selected as input.
+ * - 0b00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
+ *     selected as input.
+ * - 0b00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b11000 - Reserved.
+ * - 0b11001 - Reserved.
+ * - 0b11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input;
+ *     when DIFF=1, Temp Sensor (differential) is selected as input.
+ * - 0b11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
+ *     DIFF=1, Bandgap (differential) is selected as input.
+ * - 0b11100 - Reserved.
+ * - 0b11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
+ *     (differential) is selected as input. Voltage reference selected is determined
+ *     by SC2[REFSEL].
+ * - 0b11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
+ *     reserved. Voltage reference selected is determined by SC2[REFSEL].
+ * - 0b11111 - Module is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_ADCH field. */
+#define ADC_RD_SC1_ADCH(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_ADCH_MASK) >> ADC_SC1_ADCH_SHIFT)
+#define ADC_BRD_SC1_ADCH(base, index) (ADC_RD_SC1_ADCH(base, index))
+
+/*! @brief Set the ADCH field to a new value. */
+#define ADC_WR_SC1_ADCH(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_ADCH_MASK, ADC_SC1_ADCH(value)))
+#define ADC_BWR_SC1_ADCH(base, index, value) (ADC_WR_SC1_ADCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field DIFF[5] (RW)
+ *
+ * Configures the ADC to operate in differential mode. When enabled, this mode
+ * automatically selects from the differential channels, and changes the
+ * conversion algorithm and the number of cycles to complete a conversion.
+ *
+ * Values:
+ * - 0b0 - Single-ended conversions and input channels are selected.
+ * - 0b1 - Differential conversions and input channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_DIFF field. */
+#define ADC_RD_SC1_DIFF(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_DIFF_MASK) >> ADC_SC1_DIFF_SHIFT)
+#define ADC_BRD_SC1_DIFF(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT))
+
+/*! @brief Set the DIFF field to a new value. */
+#define ADC_WR_SC1_DIFF(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_DIFF_MASK, ADC_SC1_DIFF(value)))
+#define ADC_BWR_SC1_DIFF(base, index, value) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field AIEN[6] (RW)
+ *
+ * Enables conversion complete interrupts. When COCO becomes set while the
+ * respective AIEN is high, an interrupt is asserted.
+ *
+ * Values:
+ * - 0b0 - Conversion complete interrupt is disabled.
+ * - 0b1 - Conversion complete interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_AIEN field. */
+#define ADC_RD_SC1_AIEN(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIEN_SHIFT)
+#define ADC_BRD_SC1_AIEN(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT))
+
+/*! @brief Set the AIEN field to a new value. */
+#define ADC_WR_SC1_AIEN(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_AIEN_MASK, ADC_SC1_AIEN(value)))
+#define ADC_BWR_SC1_AIEN(base, index, value) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field COCO[7] (RO)
+ *
+ * This is a read-only field that is set each time a conversion is completed
+ * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
+ * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
+ * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
+ * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
+ * COCO is set upon completion of the selected number of conversions (determined
+ * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
+ * COCO is cleared when the respective SC1n register is written or when the
+ * respective Rn register is read.
+ *
+ * Values:
+ * - 0b0 - Conversion is not completed.
+ * - 0b1 - Conversion is completed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_COCO field. */
+#define ADC_RD_SC1_COCO(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_COCO_MASK) >> ADC_SC1_COCO_SHIFT)
+#define ADC_BRD_SC1_COCO(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG1 - ADC Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG1 - ADC Configuration Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The configuration Register 1 (CFG1) selects the mode of operation, clock
+ * source, clock divide, and configuration for low power or long sample time.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG1 register
+ */
+/*@{*/
+#define ADC_RD_CFG1(base)        (ADC_CFG1_REG(base))
+#define ADC_WR_CFG1(base, value) (ADC_CFG1_REG(base) = (value))
+#define ADC_RMW_CFG1(base, mask, value) (ADC_WR_CFG1(base, (ADC_RD_CFG1(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) |  (value)))
+#define ADC_CLR_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) & ~(value)))
+#define ADC_TOG_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
+ *
+ * Selects the input clock source to generate the internal clock, ADCK. Note
+ * that when the ADACK clock source is selected, it is not required to be active
+ * prior to conversion start. When it is selected and it is not active prior to a
+ * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
+ * the start of a conversion and deactivated when conversions are terminated. In
+ * this case, there is an associated clock startup delay each time the clock
+ * source is re-activated.
+ *
+ * Values:
+ * - 0b00 - Bus clock
+ * - 0b01 - Alternate clock 2 (ALTCLK2)
+ * - 0b10 - Alternate clock (ALTCLK)
+ * - 0b11 - Asynchronous clock (ADACK)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADICLK field. */
+#define ADC_RD_CFG1_ADICLK(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADICLK_MASK) >> ADC_CFG1_ADICLK_SHIFT)
+#define ADC_BRD_CFG1_ADICLK(base) (ADC_RD_CFG1_ADICLK(base))
+
+/*! @brief Set the ADICLK field to a new value. */
+#define ADC_WR_CFG1_ADICLK(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADICLK_MASK, ADC_CFG1_ADICLK(value)))
+#define ADC_BWR_CFG1_ADICLK(base, value) (ADC_WR_CFG1_ADICLK(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field MODE[3:2] (RW)
+ *
+ * Selects the ADC resolution mode.
+ *
+ * Values:
+ * - 0b00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
+ *     differential 9-bit conversion with 2's complement output.
+ * - 0b01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it
+ *     is differential 13-bit conversion with 2's complement output.
+ * - 0b10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it
+ *     is differential 11-bit conversion with 2's complement output
+ * - 0b11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it
+ *     is differential 16-bit conversion with 2's complement output
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_MODE field. */
+#define ADC_RD_CFG1_MODE(base) ((ADC_CFG1_REG(base) & ADC_CFG1_MODE_MASK) >> ADC_CFG1_MODE_SHIFT)
+#define ADC_BRD_CFG1_MODE(base) (ADC_RD_CFG1_MODE(base))
+
+/*! @brief Set the MODE field to a new value. */
+#define ADC_WR_CFG1_MODE(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_MODE_MASK, ADC_CFG1_MODE(value)))
+#define ADC_BWR_CFG1_MODE(base, value) (ADC_WR_CFG1_MODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLSMP[4] (RW)
+ *
+ * Selects between different sample times based on the conversion mode selected.
+ * This field adjusts the sample period to allow higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption if
+ * continuous conversions are enabled and high conversion rates are not required.
+ * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
+ * extent of the long sample time.
+ *
+ * Values:
+ * - 0b0 - Short sample time.
+ * - 0b1 - Long sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
+#define ADC_RD_CFG1_ADLSMP(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLSMP_MASK) >> ADC_CFG1_ADLSMP_SHIFT)
+#define ADC_BRD_CFG1_ADLSMP(base) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT))
+
+/*! @brief Set the ADLSMP field to a new value. */
+#define ADC_WR_CFG1_ADLSMP(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLSMP_MASK, ADC_CFG1_ADLSMP(value)))
+#define ADC_BWR_CFG1_ADLSMP(base, value) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADIV[6:5] (RW)
+ *
+ * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
+ *
+ * Values:
+ * - 0b00 - The divide ratio is 1 and the clock rate is input clock.
+ * - 0b01 - The divide ratio is 2 and the clock rate is (input clock)/2.
+ * - 0b10 - The divide ratio is 4 and the clock rate is (input clock)/4.
+ * - 0b11 - The divide ratio is 8 and the clock rate is (input clock)/8.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADIV field. */
+#define ADC_RD_CFG1_ADIV(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT)
+#define ADC_BRD_CFG1_ADIV(base) (ADC_RD_CFG1_ADIV(base))
+
+/*! @brief Set the ADIV field to a new value. */
+#define ADC_WR_CFG1_ADIV(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADIV_MASK, ADC_CFG1_ADIV(value)))
+#define ADC_BWR_CFG1_ADIV(base, value) (ADC_WR_CFG1_ADIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLPC[7] (RW)
+ *
+ * Controls the power configuration of the successive approximation converter.
+ * This optimizes power consumption when higher sample rates are not required.
+ *
+ * Values:
+ * - 0b0 - Normal power configuration.
+ * - 0b1 - Low-power configuration. The power is reduced at the expense of
+ *     maximum clock speed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLPC field. */
+#define ADC_RD_CFG1_ADLPC(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLPC_MASK) >> ADC_CFG1_ADLPC_SHIFT)
+#define ADC_BRD_CFG1_ADLPC(base) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT))
+
+/*! @brief Set the ADLPC field to a new value. */
+#define ADC_WR_CFG1_ADLPC(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLPC_MASK, ADC_CFG1_ADLPC(value)))
+#define ADC_BWR_CFG1_ADLPC(base, value) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG2 - ADC Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG2 - ADC Configuration Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Configuration Register 2 (CFG2) selects the special high-speed configuration
+ * for very high speed conversions and selects the long sample time duration
+ * during long sample mode.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG2 register
+ */
+/*@{*/
+#define ADC_RD_CFG2(base)        (ADC_CFG2_REG(base))
+#define ADC_WR_CFG2(base, value) (ADC_CFG2_REG(base) = (value))
+#define ADC_RMW_CFG2(base, mask, value) (ADC_WR_CFG2(base, (ADC_RD_CFG2(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) |  (value)))
+#define ADC_CLR_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) & ~(value)))
+#define ADC_TOG_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
+ *
+ * Selects between the extended sample times when long sample time is selected,
+ * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption when
+ * continuous conversions are enabled if high conversion rates are not required.
+ *
+ * Values:
+ * - 0b00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
+ *     total.
+ * - 0b01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
+ * - 0b10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
+ * - 0b11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
+#define ADC_RD_CFG2_ADLSTS(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADLSTS_MASK) >> ADC_CFG2_ADLSTS_SHIFT)
+#define ADC_BRD_CFG2_ADLSTS(base) (ADC_RD_CFG2_ADLSTS(base))
+
+/*! @brief Set the ADLSTS field to a new value. */
+#define ADC_WR_CFG2_ADLSTS(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADLSTS_MASK, ADC_CFG2_ADLSTS(value)))
+#define ADC_BWR_CFG2_ADLSTS(base, value) (ADC_WR_CFG2_ADLSTS(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADHSC[2] (RW)
+ *
+ * Configures the ADC for very high-speed operation. The conversion sequence is
+ * altered with 2 ADCK cycles added to the conversion time to allow higher speed
+ * conversion clocks.
+ *
+ * Values:
+ * - 0b0 - Normal conversion sequence selected.
+ * - 0b1 - High-speed conversion sequence selected with 2 additional ADCK cycles
+ *     to total conversion time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADHSC field. */
+#define ADC_RD_CFG2_ADHSC(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADHSC_MASK) >> ADC_CFG2_ADHSC_SHIFT)
+#define ADC_BRD_CFG2_ADHSC(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT))
+
+/*! @brief Set the ADHSC field to a new value. */
+#define ADC_WR_CFG2_ADHSC(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADHSC_MASK, ADC_CFG2_ADHSC(value)))
+#define ADC_BWR_CFG2_ADHSC(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADACKEN[3] (RW)
+ *
+ * Enables the asynchronous clock source and the clock source output regardless
+ * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
+ * asynchronous clock may be used by other modules. See chip configuration
+ * information. Setting this field allows the clock to be used even while the ADC is
+ * idle or operating from a different clock source. Also, latency of initiating a
+ * single or first-continuous conversion with the asynchronous clock selected is
+ * reduced because the ADACK clock is already operational.
+ *
+ * Values:
+ * - 0b0 - Asynchronous clock output disabled; Asynchronous clock is enabled
+ *     only if selected by ADICLK and a conversion is active.
+ * - 0b1 - Asynchronous clock and clock output is enabled regardless of the
+ *     state of the ADC.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
+#define ADC_RD_CFG2_ADACKEN(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADACKEN_MASK) >> ADC_CFG2_ADACKEN_SHIFT)
+#define ADC_BRD_CFG2_ADACKEN(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT))
+
+/*! @brief Set the ADACKEN field to a new value. */
+#define ADC_WR_CFG2_ADACKEN(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADACKEN_MASK, ADC_CFG2_ADACKEN(value)))
+#define ADC_BWR_CFG2_ADACKEN(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field MUXSEL[4] (RW)
+ *
+ * Changes the ADC mux setting to select between alternate sets of ADC channels.
+ *
+ * Values:
+ * - 0b0 - ADxxa channels are selected.
+ * - 0b1 - ADxxb channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
+#define ADC_RD_CFG2_MUXSEL(base) ((ADC_CFG2_REG(base) & ADC_CFG2_MUXSEL_MASK) >> ADC_CFG2_MUXSEL_SHIFT)
+#define ADC_BRD_CFG2_MUXSEL(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT))
+
+/*! @brief Set the MUXSEL field to a new value. */
+#define ADC_WR_CFG2_MUXSEL(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_MUXSEL_MASK, ADC_CFG2_MUXSEL(value)))
+#define ADC_BWR_CFG2_MUXSEL(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_R - ADC Data Result Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_R - ADC Data Result Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The data result registers (Rn) contain the result of an ADC conversion of the
+ * channel selected by the corresponding status and channel control register
+ * (SC1A:SC1n). For every status and channel control register, there is a
+ * corresponding data result register. Unused bits in R n are cleared in unsigned
+ * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
+ * For example, when configured for 10-bit single-ended mode, D[15:10] are
+ * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
+ * that is, bit 10 extended through bit 15. The following table describes the
+ * behavior of the data result registers in the different modes of operation. Data
+ * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
+ * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
+ * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
+ * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
+ * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
+ * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
+ * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
+ * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
+ * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
+ * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
+ * 2's complement data if indicated
+ */
+/*!
+ * @name Constants and macros for entire ADC_R register
+ */
+/*@{*/
+#define ADC_RD_R(base, index)    (ADC_R_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_R bitfields
+ */
+
+/*!
+ * @name Register ADC_R, field D[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_R_D field. */
+#define ADC_RD_R_D(base, index) ((ADC_R_REG(base, index) & ADC_R_D_MASK) >> ADC_R_D_SHIFT)
+#define ADC_BRD_R_D(base, index) (ADC_RD_R_D(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV1 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV1 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV1 register
+ */
+/*@{*/
+#define ADC_RD_CV1(base)         (ADC_CV1_REG(base))
+#define ADC_WR_CV1(base, value)  (ADC_CV1_REG(base) = (value))
+#define ADC_RMW_CV1(base, mask, value) (ADC_WR_CV1(base, (ADC_RD_CV1(base) & ~(mask)) | (value)))
+#define ADC_SET_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) |  (value)))
+#define ADC_CLR_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) & ~(value)))
+#define ADC_TOG_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV1, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV1_CV field. */
+#define ADC_RD_CV1_CV(base)  ((ADC_CV1_REG(base) & ADC_CV1_CV_MASK) >> ADC_CV1_CV_SHIFT)
+#define ADC_BRD_CV1_CV(base) (ADC_RD_CV1_CV(base))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV1_CV(base, value) (ADC_RMW_CV1(base, ADC_CV1_CV_MASK, ADC_CV1_CV(value)))
+#define ADC_BWR_CV1_CV(base, value) (ADC_WR_CV1_CV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV2 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV2 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV2 register
+ */
+/*@{*/
+#define ADC_RD_CV2(base)         (ADC_CV2_REG(base))
+#define ADC_WR_CV2(base, value)  (ADC_CV2_REG(base) = (value))
+#define ADC_RMW_CV2(base, mask, value) (ADC_WR_CV2(base, (ADC_RD_CV2(base) & ~(mask)) | (value)))
+#define ADC_SET_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) |  (value)))
+#define ADC_CLR_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) & ~(value)))
+#define ADC_TOG_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV2, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV2_CV field. */
+#define ADC_RD_CV2_CV(base)  ((ADC_CV2_REG(base) & ADC_CV2_CV_MASK) >> ADC_CV2_CV_SHIFT)
+#define ADC_BRD_CV2_CV(base) (ADC_RD_CV2_CV(base))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV2_CV(base, value) (ADC_RMW_CV2(base, ADC_CV2_CV_MASK, ADC_CV2_CV(value)))
+#define ADC_BWR_CV2_CV(base, value) (ADC_WR_CV2_CV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC2 - Status and Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC2 - Status and Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The status and control register 2 (SC2) contains the conversion active,
+ * hardware/software trigger select, compare function, and voltage reference select of
+ * the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC2 register
+ */
+/*@{*/
+#define ADC_RD_SC2(base)         (ADC_SC2_REG(base))
+#define ADC_WR_SC2(base, value)  (ADC_SC2_REG(base) = (value))
+#define ADC_RMW_SC2(base, mask, value) (ADC_WR_SC2(base, (ADC_RD_SC2(base) & ~(mask)) | (value)))
+#define ADC_SET_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) |  (value)))
+#define ADC_CLR_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) & ~(value)))
+#define ADC_TOG_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC2 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC2, field REFSEL[1:0] (RW)
+ *
+ * Selects the voltage reference source used for conversions.
+ *
+ * Values:
+ * - 0b00 - Default voltage reference pin pair, that is, external pins VREFH and
+ *     VREFL
+ * - 0b01 - Alternate reference pair, that is, VALTH and VALTL . This pair may
+ *     be additional external pins or internal sources depending on the MCU
+ *     configuration. See the chip configuration information for details specific to
+ *     this MCU
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_REFSEL field. */
+#define ADC_RD_SC2_REFSEL(base) ((ADC_SC2_REG(base) & ADC_SC2_REFSEL_MASK) >> ADC_SC2_REFSEL_SHIFT)
+#define ADC_BRD_SC2_REFSEL(base) (ADC_RD_SC2_REFSEL(base))
+
+/*! @brief Set the REFSEL field to a new value. */
+#define ADC_WR_SC2_REFSEL(base, value) (ADC_RMW_SC2(base, ADC_SC2_REFSEL_MASK, ADC_SC2_REFSEL(value)))
+#define ADC_BWR_SC2_REFSEL(base, value) (ADC_WR_SC2_REFSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field DMAEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled and will assert the ADC DMA request during an ADC
+ *     conversion complete event noted when any of the SC1n[COCO] flags is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_DMAEN field. */
+#define ADC_RD_SC2_DMAEN(base) ((ADC_SC2_REG(base) & ADC_SC2_DMAEN_MASK) >> ADC_SC2_DMAEN_SHIFT)
+#define ADC_BRD_SC2_DMAEN(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define ADC_WR_SC2_DMAEN(base, value) (ADC_RMW_SC2(base, ADC_SC2_DMAEN_MASK, ADC_SC2_DMAEN(value)))
+#define ADC_BWR_SC2_DMAEN(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACREN[3] (RW)
+ *
+ * Configures the compare function to check if the conversion result of the
+ * input being monitored is either between or outside the range formed by CV1 and CV2
+ * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
+ * effect.
+ *
+ * Values:
+ * - 0b0 - Range function disabled. Only CV1 is compared.
+ * - 0b1 - Range function enabled. Both CV1 and CV2 are compared.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACREN field. */
+#define ADC_RD_SC2_ACREN(base) ((ADC_SC2_REG(base) & ADC_SC2_ACREN_MASK) >> ADC_SC2_ACREN_SHIFT)
+#define ADC_BRD_SC2_ACREN(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT))
+
+/*! @brief Set the ACREN field to a new value. */
+#define ADC_WR_SC2_ACREN(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACREN_MASK, ADC_SC2_ACREN(value)))
+#define ADC_BWR_SC2_ACREN(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFGT[4] (RW)
+ *
+ * Configures the compare function to check the conversion result relative to
+ * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
+ * have any effect.
+ *
+ * Values:
+ * - 0b0 - Configures less than threshold, outside range not inclusive and
+ *     inside range not inclusive; functionality based on the values placed in CV1 and
+ *     CV2.
+ * - 0b1 - Configures greater than or equal to threshold, outside and inside
+ *     ranges inclusive; functionality based on the values placed in CV1 and CV2.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFGT field. */
+#define ADC_RD_SC2_ACFGT(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFGT_MASK) >> ADC_SC2_ACFGT_SHIFT)
+#define ADC_BRD_SC2_ACFGT(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT))
+
+/*! @brief Set the ACFGT field to a new value. */
+#define ADC_WR_SC2_ACFGT(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFGT_MASK, ADC_SC2_ACFGT(value)))
+#define ADC_BWR_SC2_ACFGT(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFE[5] (RW)
+ *
+ * Enables the compare function.
+ *
+ * Values:
+ * - 0b0 - Compare function disabled.
+ * - 0b1 - Compare function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFE field. */
+#define ADC_RD_SC2_ACFE(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFE_MASK) >> ADC_SC2_ACFE_SHIFT)
+#define ADC_BRD_SC2_ACFE(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT))
+
+/*! @brief Set the ACFE field to a new value. */
+#define ADC_WR_SC2_ACFE(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFE_MASK, ADC_SC2_ACFE(value)))
+#define ADC_BWR_SC2_ACFE(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADTRG[6] (RW)
+ *
+ * Selects the type of trigger used for initiating a conversion. Two types of
+ * trigger are selectable: Software trigger: When software trigger is selected, a
+ * conversion is initiated following a write to SC1A. Hardware trigger: When
+ * hardware trigger is selected, a conversion is initiated following the assertion of
+ * the ADHWT input after a pulse of the ADHWTSn input.
+ *
+ * Values:
+ * - 0b0 - Software trigger selected.
+ * - 0b1 - Hardware trigger selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADTRG field. */
+#define ADC_RD_SC2_ADTRG(base) ((ADC_SC2_REG(base) & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT)
+#define ADC_BRD_SC2_ADTRG(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT))
+
+/*! @brief Set the ADTRG field to a new value. */
+#define ADC_WR_SC2_ADTRG(base, value) (ADC_RMW_SC2(base, ADC_SC2_ADTRG_MASK, ADC_SC2_ADTRG(value)))
+#define ADC_BWR_SC2_ADTRG(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADACT[7] (RO)
+ *
+ * Indicates that a conversion or hardware averaging is in progress. ADACT is
+ * set when a conversion is initiated and cleared when a conversion is completed or
+ * aborted.
+ *
+ * Values:
+ * - 0b0 - Conversion not in progress.
+ * - 0b1 - Conversion in progress.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADACT field. */
+#define ADC_RD_SC2_ADACT(base) ((ADC_SC2_REG(base) & ADC_SC2_ADACT_MASK) >> ADC_SC2_ADACT_SHIFT)
+#define ADC_BRD_SC2_ADACT(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADACT_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC3 - Status and Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC3 - Status and Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Status and Control Register 3 (SC3) controls the calibration, continuous
+ * convert, and hardware averaging functions of the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC3 register
+ */
+/*@{*/
+#define ADC_RD_SC3(base)         (ADC_SC3_REG(base))
+#define ADC_WR_SC3(base, value)  (ADC_SC3_REG(base) = (value))
+#define ADC_RMW_SC3(base, mask, value) (ADC_WR_SC3(base, (ADC_RD_SC3(base) & ~(mask)) | (value)))
+#define ADC_SET_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) |  (value)))
+#define ADC_CLR_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) & ~(value)))
+#define ADC_TOG_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC3 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC3, field AVGS[1:0] (RW)
+ *
+ * Determines how many ADC conversions will be averaged to create the ADC
+ * average result.
+ *
+ * Values:
+ * - 0b00 - 4 samples averaged.
+ * - 0b01 - 8 samples averaged.
+ * - 0b10 - 16 samples averaged.
+ * - 0b11 - 32 samples averaged.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGS field. */
+#define ADC_RD_SC3_AVGS(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGS_MASK) >> ADC_SC3_AVGS_SHIFT)
+#define ADC_BRD_SC3_AVGS(base) (ADC_RD_SC3_AVGS(base))
+
+/*! @brief Set the AVGS field to a new value. */
+#define ADC_WR_SC3_AVGS(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGS_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGS(value)))
+#define ADC_BWR_SC3_AVGS(base, value) (ADC_WR_SC3_AVGS(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field AVGE[2] (RW)
+ *
+ * Enables the hardware average function of the ADC.
+ *
+ * Values:
+ * - 0b0 - Hardware average function disabled.
+ * - 0b1 - Hardware average function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGE field. */
+#define ADC_RD_SC3_AVGE(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGE_MASK) >> ADC_SC3_AVGE_SHIFT)
+#define ADC_BRD_SC3_AVGE(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT))
+
+/*! @brief Set the AVGE field to a new value. */
+#define ADC_WR_SC3_AVGE(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGE_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGE(value)))
+#define ADC_BWR_SC3_AVGE(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field ADCO[3] (RW)
+ *
+ * Enables continuous conversions.
+ *
+ * Values:
+ * - 0b0 - One conversion or one set of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ * - 0b1 - Continuous conversions or sets of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_ADCO field. */
+#define ADC_RD_SC3_ADCO(base) ((ADC_SC3_REG(base) & ADC_SC3_ADCO_MASK) >> ADC_SC3_ADCO_SHIFT)
+#define ADC_BRD_SC3_ADCO(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT))
+
+/*! @brief Set the ADCO field to a new value. */
+#define ADC_WR_SC3_ADCO(base, value) (ADC_RMW_SC3(base, (ADC_SC3_ADCO_MASK | ADC_SC3_CALF_MASK), ADC_SC3_ADCO(value)))
+#define ADC_BWR_SC3_ADCO(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CALF[6] (W1C)
+ *
+ * Displays the result of the calibration sequence. The calibration sequence
+ * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
+ * entered before the calibration sequence completes. Writing 1 to CALF clears it.
+ *
+ * Values:
+ * - 0b0 - Calibration completed normally.
+ * - 0b1 - Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CALF field. */
+#define ADC_RD_SC3_CALF(base) ((ADC_SC3_REG(base) & ADC_SC3_CALF_MASK) >> ADC_SC3_CALF_SHIFT)
+#define ADC_BRD_SC3_CALF(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT))
+
+/*! @brief Set the CALF field to a new value. */
+#define ADC_WR_SC3_CALF(base, value) (ADC_RMW_SC3(base, ADC_SC3_CALF_MASK, ADC_SC3_CALF(value)))
+#define ADC_BWR_SC3_CALF(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CAL[7] (RW)
+ *
+ * Begins the calibration sequence when set. This field stays set while the
+ * calibration is in progress and is cleared when the calibration sequence is
+ * completed. CALF must be checked to determine the result of the calibration sequence.
+ * Once started, the calibration routine cannot be interrupted by writes to the
+ * ADC registers or the results will be invalid and CALF will set. Setting CAL
+ * will abort any current conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CAL field. */
+#define ADC_RD_SC3_CAL(base) ((ADC_SC3_REG(base) & ADC_SC3_CAL_MASK) >> ADC_SC3_CAL_SHIFT)
+#define ADC_BRD_SC3_CAL(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT))
+
+/*! @brief Set the CAL field to a new value. */
+#define ADC_WR_SC3_CAL(base, value) (ADC_RMW_SC3(base, (ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK), ADC_SC3_CAL(value)))
+#define ADC_BWR_SC3_CAL(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_OFS - ADC Offset Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_OFS - ADC Offset Correction Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * The ADC Offset Correction Register (OFS) contains the user-selected or
+ * calibration-generated offset error correction value. This register is a 2's
+ * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
+ * conversion and the result is transferred into the result registers, Rn. If the
+ * result is greater than the maximum or less than the minimum result value, it is
+ * forced to the appropriate limit for the current mode of operation.
+ */
+/*!
+ * @name Constants and macros for entire ADC_OFS register
+ */
+/*@{*/
+#define ADC_RD_OFS(base)         (ADC_OFS_REG(base))
+#define ADC_WR_OFS(base, value)  (ADC_OFS_REG(base) = (value))
+#define ADC_RMW_OFS(base, mask, value) (ADC_WR_OFS(base, (ADC_RD_OFS(base) & ~(mask)) | (value)))
+#define ADC_SET_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) |  (value)))
+#define ADC_CLR_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) & ~(value)))
+#define ADC_TOG_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_OFS bitfields
+ */
+
+/*!
+ * @name Register ADC_OFS, field OFS[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_OFS_OFS field. */
+#define ADC_RD_OFS_OFS(base) ((ADC_OFS_REG(base) & ADC_OFS_OFS_MASK) >> ADC_OFS_OFS_SHIFT)
+#define ADC_BRD_OFS_OFS(base) (ADC_RD_OFS_OFS(base))
+
+/*! @brief Set the OFS field to a new value. */
+#define ADC_WR_OFS_OFS(base, value) (ADC_RMW_OFS(base, ADC_OFS_OFS_MASK, ADC_OFS_OFS(value)))
+#define ADC_BWR_OFS_OFS(base, value) (ADC_WR_OFS_OFS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_PG - ADC Plus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_PG - ADC Plus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Plus-Side Gain Register (PG) contains the gain error correction for the
+ * plus-side input in differential mode or the overall conversion in single-ended
+ * mode. PG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
+ * written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_PG register
+ */
+/*@{*/
+#define ADC_RD_PG(base)          (ADC_PG_REG(base))
+#define ADC_WR_PG(base, value)   (ADC_PG_REG(base) = (value))
+#define ADC_RMW_PG(base, mask, value) (ADC_WR_PG(base, (ADC_RD_PG(base) & ~(mask)) | (value)))
+#define ADC_SET_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) |  (value)))
+#define ADC_CLR_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) & ~(value)))
+#define ADC_TOG_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_PG bitfields
+ */
+
+/*!
+ * @name Register ADC_PG, field PG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_PG_PG field. */
+#define ADC_RD_PG_PG(base)   ((ADC_PG_REG(base) & ADC_PG_PG_MASK) >> ADC_PG_PG_SHIFT)
+#define ADC_BRD_PG_PG(base)  (ADC_RD_PG_PG(base))
+
+/*! @brief Set the PG field to a new value. */
+#define ADC_WR_PG_PG(base, value) (ADC_RMW_PG(base, ADC_PG_PG_MASK, ADC_PG_PG(value)))
+#define ADC_BWR_PG_PG(base, value) (ADC_WR_PG_PG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_MG - ADC Minus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_MG - ADC Minus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Minus-Side Gain Register (MG) contains the gain error correction for the
+ * minus-side input in differential mode. This register is ignored in
+ * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
+ * be written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_MG register
+ */
+/*@{*/
+#define ADC_RD_MG(base)          (ADC_MG_REG(base))
+#define ADC_WR_MG(base, value)   (ADC_MG_REG(base) = (value))
+#define ADC_RMW_MG(base, mask, value) (ADC_WR_MG(base, (ADC_RD_MG(base) & ~(mask)) | (value)))
+#define ADC_SET_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) |  (value)))
+#define ADC_CLR_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) & ~(value)))
+#define ADC_TOG_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_MG bitfields
+ */
+
+/*!
+ * @name Register ADC_MG, field MG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_MG_MG field. */
+#define ADC_RD_MG_MG(base)   ((ADC_MG_REG(base) & ADC_MG_MG_MASK) >> ADC_MG_MG_SHIFT)
+#define ADC_BRD_MG_MG(base)  (ADC_RD_MG_MG(base))
+
+/*! @brief Set the MG field to a new value. */
+#define ADC_WR_MG_MG(base, value) (ADC_RMW_MG(base, ADC_MG_MG_MASK, ADC_MG_MG(value)))
+#define ADC_BWR_MG_MG(base, value) (ADC_WR_MG_MG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
+ * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
+ * when the self-calibration sequence is done, that is, CAL is cleared. If these
+ * registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPD register
+ */
+/*@{*/
+#define ADC_RD_CLPD(base)        (ADC_CLPD_REG(base))
+#define ADC_WR_CLPD(base, value) (ADC_CLPD_REG(base) = (value))
+#define ADC_RMW_CLPD(base, mask, value) (ADC_WR_CLPD(base, (ADC_RD_CLPD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) |  (value)))
+#define ADC_CLR_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) & ~(value)))
+#define ADC_TOG_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPD, field CLPD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPD_CLPD field. */
+#define ADC_RD_CLPD_CLPD(base) ((ADC_CLPD_REG(base) & ADC_CLPD_CLPD_MASK) >> ADC_CLPD_CLPD_SHIFT)
+#define ADC_BRD_CLPD_CLPD(base) (ADC_RD_CLPD_CLPD(base))
+
+/*! @brief Set the CLPD field to a new value. */
+#define ADC_WR_CLPD_CLPD(base, value) (ADC_RMW_CLPD(base, ADC_CLPD_CLPD_MASK, ADC_CLPD_CLPD(value)))
+#define ADC_BWR_CLPD_CLPD(base, value) (ADC_WR_CLPD_CLPD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPS register
+ */
+/*@{*/
+#define ADC_RD_CLPS(base)        (ADC_CLPS_REG(base))
+#define ADC_WR_CLPS(base, value) (ADC_CLPS_REG(base) = (value))
+#define ADC_RMW_CLPS(base, mask, value) (ADC_WR_CLPS(base, (ADC_RD_CLPS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) |  (value)))
+#define ADC_CLR_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) & ~(value)))
+#define ADC_TOG_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPS, field CLPS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPS_CLPS field. */
+#define ADC_RD_CLPS_CLPS(base) ((ADC_CLPS_REG(base) & ADC_CLPS_CLPS_MASK) >> ADC_CLPS_CLPS_SHIFT)
+#define ADC_BRD_CLPS_CLPS(base) (ADC_RD_CLPS_CLPS(base))
+
+/*! @brief Set the CLPS field to a new value. */
+#define ADC_WR_CLPS_CLPS(base, value) (ADC_RMW_CLPS(base, ADC_CLPS_CLPS_MASK, ADC_CLPS_CLPS(value)))
+#define ADC_BWR_CLPS_CLPS(base, value) (ADC_WR_CLPS_CLPS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP4 register
+ */
+/*@{*/
+#define ADC_RD_CLP4(base)        (ADC_CLP4_REG(base))
+#define ADC_WR_CLP4(base, value) (ADC_CLP4_REG(base) = (value))
+#define ADC_RMW_CLP4(base, mask, value) (ADC_WR_CLP4(base, (ADC_RD_CLP4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) |  (value)))
+#define ADC_CLR_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) & ~(value)))
+#define ADC_TOG_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP4, field CLP4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP4_CLP4 field. */
+#define ADC_RD_CLP4_CLP4(base) ((ADC_CLP4_REG(base) & ADC_CLP4_CLP4_MASK) >> ADC_CLP4_CLP4_SHIFT)
+#define ADC_BRD_CLP4_CLP4(base) (ADC_RD_CLP4_CLP4(base))
+
+/*! @brief Set the CLP4 field to a new value. */
+#define ADC_WR_CLP4_CLP4(base, value) (ADC_RMW_CLP4(base, ADC_CLP4_CLP4_MASK, ADC_CLP4_CLP4(value)))
+#define ADC_BWR_CLP4_CLP4(base, value) (ADC_WR_CLP4_CLP4(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP3 register
+ */
+/*@{*/
+#define ADC_RD_CLP3(base)        (ADC_CLP3_REG(base))
+#define ADC_WR_CLP3(base, value) (ADC_CLP3_REG(base) = (value))
+#define ADC_RMW_CLP3(base, mask, value) (ADC_WR_CLP3(base, (ADC_RD_CLP3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) |  (value)))
+#define ADC_CLR_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) & ~(value)))
+#define ADC_TOG_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP3, field CLP3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP3_CLP3 field. */
+#define ADC_RD_CLP3_CLP3(base) ((ADC_CLP3_REG(base) & ADC_CLP3_CLP3_MASK) >> ADC_CLP3_CLP3_SHIFT)
+#define ADC_BRD_CLP3_CLP3(base) (ADC_RD_CLP3_CLP3(base))
+
+/*! @brief Set the CLP3 field to a new value. */
+#define ADC_WR_CLP3_CLP3(base, value) (ADC_RMW_CLP3(base, ADC_CLP3_CLP3_MASK, ADC_CLP3_CLP3(value)))
+#define ADC_BWR_CLP3_CLP3(base, value) (ADC_WR_CLP3_CLP3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP2 register
+ */
+/*@{*/
+#define ADC_RD_CLP2(base)        (ADC_CLP2_REG(base))
+#define ADC_WR_CLP2(base, value) (ADC_CLP2_REG(base) = (value))
+#define ADC_RMW_CLP2(base, mask, value) (ADC_WR_CLP2(base, (ADC_RD_CLP2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) |  (value)))
+#define ADC_CLR_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) & ~(value)))
+#define ADC_TOG_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP2, field CLP2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP2_CLP2 field. */
+#define ADC_RD_CLP2_CLP2(base) ((ADC_CLP2_REG(base) & ADC_CLP2_CLP2_MASK) >> ADC_CLP2_CLP2_SHIFT)
+#define ADC_BRD_CLP2_CLP2(base) (ADC_RD_CLP2_CLP2(base))
+
+/*! @brief Set the CLP2 field to a new value. */
+#define ADC_WR_CLP2_CLP2(base, value) (ADC_RMW_CLP2(base, ADC_CLP2_CLP2_MASK, ADC_CLP2_CLP2(value)))
+#define ADC_BWR_CLP2_CLP2(base, value) (ADC_WR_CLP2_CLP2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP1 register
+ */
+/*@{*/
+#define ADC_RD_CLP1(base)        (ADC_CLP1_REG(base))
+#define ADC_WR_CLP1(base, value) (ADC_CLP1_REG(base) = (value))
+#define ADC_RMW_CLP1(base, mask, value) (ADC_WR_CLP1(base, (ADC_RD_CLP1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) |  (value)))
+#define ADC_CLR_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) & ~(value)))
+#define ADC_TOG_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP1, field CLP1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP1_CLP1 field. */
+#define ADC_RD_CLP1_CLP1(base) ((ADC_CLP1_REG(base) & ADC_CLP1_CLP1_MASK) >> ADC_CLP1_CLP1_SHIFT)
+#define ADC_BRD_CLP1_CLP1(base) (ADC_RD_CLP1_CLP1(base))
+
+/*! @brief Set the CLP1 field to a new value. */
+#define ADC_WR_CLP1_CLP1(base, value) (ADC_RMW_CLP1(base, ADC_CLP1_CLP1_MASK, ADC_CLP1_CLP1(value)))
+#define ADC_BWR_CLP1_CLP1(base, value) (ADC_WR_CLP1_CLP1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP0 register
+ */
+/*@{*/
+#define ADC_RD_CLP0(base)        (ADC_CLP0_REG(base))
+#define ADC_WR_CLP0(base, value) (ADC_CLP0_REG(base) = (value))
+#define ADC_RMW_CLP0(base, mask, value) (ADC_WR_CLP0(base, (ADC_RD_CLP0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) |  (value)))
+#define ADC_CLR_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) & ~(value)))
+#define ADC_TOG_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP0, field CLP0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP0_CLP0 field. */
+#define ADC_RD_CLP0_CLP0(base) ((ADC_CLP0_REG(base) & ADC_CLP0_CLP0_MASK) >> ADC_CLP0_CLP0_SHIFT)
+#define ADC_BRD_CLP0_CLP0(base) (ADC_RD_CLP0_CLP0(base))
+
+/*! @brief Set the CLP0 field to a new value. */
+#define ADC_WR_CLP0_CLP0(base, value) (ADC_RMW_CLP0(base, ADC_CLP0_CLP0_MASK, ADC_CLP0_CLP0(value)))
+#define ADC_BWR_CLP0_CLP0(base, value) (ADC_WR_CLP0_CLP0(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Minus-Side General Calibration Value (CLMx) registers contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
+ * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
+ * set when the self-calibration sequence is done, that is, CAL is cleared. If
+ * these registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMD register
+ */
+/*@{*/
+#define ADC_RD_CLMD(base)        (ADC_CLMD_REG(base))
+#define ADC_WR_CLMD(base, value) (ADC_CLMD_REG(base) = (value))
+#define ADC_RMW_CLMD(base, mask, value) (ADC_WR_CLMD(base, (ADC_RD_CLMD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) |  (value)))
+#define ADC_CLR_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) & ~(value)))
+#define ADC_TOG_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMD, field CLMD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMD_CLMD field. */
+#define ADC_RD_CLMD_CLMD(base) ((ADC_CLMD_REG(base) & ADC_CLMD_CLMD_MASK) >> ADC_CLMD_CLMD_SHIFT)
+#define ADC_BRD_CLMD_CLMD(base) (ADC_RD_CLMD_CLMD(base))
+
+/*! @brief Set the CLMD field to a new value. */
+#define ADC_WR_CLMD_CLMD(base, value) (ADC_RMW_CLMD(base, ADC_CLMD_CLMD_MASK, ADC_CLMD_CLMD(value)))
+#define ADC_BWR_CLMD_CLMD(base, value) (ADC_WR_CLMD_CLMD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMS register
+ */
+/*@{*/
+#define ADC_RD_CLMS(base)        (ADC_CLMS_REG(base))
+#define ADC_WR_CLMS(base, value) (ADC_CLMS_REG(base) = (value))
+#define ADC_RMW_CLMS(base, mask, value) (ADC_WR_CLMS(base, (ADC_RD_CLMS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) |  (value)))
+#define ADC_CLR_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) & ~(value)))
+#define ADC_TOG_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMS, field CLMS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMS_CLMS field. */
+#define ADC_RD_CLMS_CLMS(base) ((ADC_CLMS_REG(base) & ADC_CLMS_CLMS_MASK) >> ADC_CLMS_CLMS_SHIFT)
+#define ADC_BRD_CLMS_CLMS(base) (ADC_RD_CLMS_CLMS(base))
+
+/*! @brief Set the CLMS field to a new value. */
+#define ADC_WR_CLMS_CLMS(base, value) (ADC_RMW_CLMS(base, ADC_CLMS_CLMS_MASK, ADC_CLMS_CLMS(value)))
+#define ADC_BWR_CLMS_CLMS(base, value) (ADC_WR_CLMS_CLMS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM4 register
+ */
+/*@{*/
+#define ADC_RD_CLM4(base)        (ADC_CLM4_REG(base))
+#define ADC_WR_CLM4(base, value) (ADC_CLM4_REG(base) = (value))
+#define ADC_RMW_CLM4(base, mask, value) (ADC_WR_CLM4(base, (ADC_RD_CLM4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) |  (value)))
+#define ADC_CLR_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) & ~(value)))
+#define ADC_TOG_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM4, field CLM4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM4_CLM4 field. */
+#define ADC_RD_CLM4_CLM4(base) ((ADC_CLM4_REG(base) & ADC_CLM4_CLM4_MASK) >> ADC_CLM4_CLM4_SHIFT)
+#define ADC_BRD_CLM4_CLM4(base) (ADC_RD_CLM4_CLM4(base))
+
+/*! @brief Set the CLM4 field to a new value. */
+#define ADC_WR_CLM4_CLM4(base, value) (ADC_RMW_CLM4(base, ADC_CLM4_CLM4_MASK, ADC_CLM4_CLM4(value)))
+#define ADC_BWR_CLM4_CLM4(base, value) (ADC_WR_CLM4_CLM4(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM3 register
+ */
+/*@{*/
+#define ADC_RD_CLM3(base)        (ADC_CLM3_REG(base))
+#define ADC_WR_CLM3(base, value) (ADC_CLM3_REG(base) = (value))
+#define ADC_RMW_CLM3(base, mask, value) (ADC_WR_CLM3(base, (ADC_RD_CLM3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) |  (value)))
+#define ADC_CLR_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) & ~(value)))
+#define ADC_TOG_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM3, field CLM3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM3_CLM3 field. */
+#define ADC_RD_CLM3_CLM3(base) ((ADC_CLM3_REG(base) & ADC_CLM3_CLM3_MASK) >> ADC_CLM3_CLM3_SHIFT)
+#define ADC_BRD_CLM3_CLM3(base) (ADC_RD_CLM3_CLM3(base))
+
+/*! @brief Set the CLM3 field to a new value. */
+#define ADC_WR_CLM3_CLM3(base, value) (ADC_RMW_CLM3(base, ADC_CLM3_CLM3_MASK, ADC_CLM3_CLM3(value)))
+#define ADC_BWR_CLM3_CLM3(base, value) (ADC_WR_CLM3_CLM3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM2 register
+ */
+/*@{*/
+#define ADC_RD_CLM2(base)        (ADC_CLM2_REG(base))
+#define ADC_WR_CLM2(base, value) (ADC_CLM2_REG(base) = (value))
+#define ADC_RMW_CLM2(base, mask, value) (ADC_WR_CLM2(base, (ADC_RD_CLM2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) |  (value)))
+#define ADC_CLR_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) & ~(value)))
+#define ADC_TOG_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM2, field CLM2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM2_CLM2 field. */
+#define ADC_RD_CLM2_CLM2(base) ((ADC_CLM2_REG(base) & ADC_CLM2_CLM2_MASK) >> ADC_CLM2_CLM2_SHIFT)
+#define ADC_BRD_CLM2_CLM2(base) (ADC_RD_CLM2_CLM2(base))
+
+/*! @brief Set the CLM2 field to a new value. */
+#define ADC_WR_CLM2_CLM2(base, value) (ADC_RMW_CLM2(base, ADC_CLM2_CLM2_MASK, ADC_CLM2_CLM2(value)))
+#define ADC_BWR_CLM2_CLM2(base, value) (ADC_WR_CLM2_CLM2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM1 register
+ */
+/*@{*/
+#define ADC_RD_CLM1(base)        (ADC_CLM1_REG(base))
+#define ADC_WR_CLM1(base, value) (ADC_CLM1_REG(base) = (value))
+#define ADC_RMW_CLM1(base, mask, value) (ADC_WR_CLM1(base, (ADC_RD_CLM1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) |  (value)))
+#define ADC_CLR_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) & ~(value)))
+#define ADC_TOG_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM1, field CLM1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM1_CLM1 field. */
+#define ADC_RD_CLM1_CLM1(base) ((ADC_CLM1_REG(base) & ADC_CLM1_CLM1_MASK) >> ADC_CLM1_CLM1_SHIFT)
+#define ADC_BRD_CLM1_CLM1(base) (ADC_RD_CLM1_CLM1(base))
+
+/*! @brief Set the CLM1 field to a new value. */
+#define ADC_WR_CLM1_CLM1(base, value) (ADC_RMW_CLM1(base, ADC_CLM1_CLM1_MASK, ADC_CLM1_CLM1(value)))
+#define ADC_BWR_CLM1_CLM1(base, value) (ADC_WR_CLM1_CLM1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM0 register
+ */
+/*@{*/
+#define ADC_RD_CLM0(base)        (ADC_CLM0_REG(base))
+#define ADC_WR_CLM0(base, value) (ADC_CLM0_REG(base) = (value))
+#define ADC_RMW_CLM0(base, mask, value) (ADC_WR_CLM0(base, (ADC_RD_CLM0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) |  (value)))
+#define ADC_CLR_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) & ~(value)))
+#define ADC_TOG_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM0, field CLM0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM0_CLM0 field. */
+#define ADC_RD_CLM0_CLM0(base) ((ADC_CLM0_REG(base) & ADC_CLM0_CLM0_MASK) >> ADC_CLM0_CLM0_SHIFT)
+#define ADC_BRD_CLM0_CLM0(base) (ADC_RD_CLM0_CLM0(base))
+
+/*! @brief Set the CLM0 field to a new value. */
+#define ADC_WR_CLM0_CLM0(base, value) (ADC_RMW_CLM0(base, ADC_CLM0_CLM0_MASK, ADC_CLM0_CLM0(value)))
+#define ADC_BWR_CLM0_CLM0(base, value) (ADC_WR_CLM0_CLM0(base, value))
+/*@}*/
+
+/*
+ * MK64F12 AIPS
+ *
+ * AIPS-Lite Bridge
+ *
+ * Registers defined in this header file:
+ * - AIPS_MPRA - Master Privilege Register A
+ * - AIPS_PACRA - Peripheral Access Control Register
+ * - AIPS_PACRB - Peripheral Access Control Register
+ * - AIPS_PACRC - Peripheral Access Control Register
+ * - AIPS_PACRD - Peripheral Access Control Register
+ * - AIPS_PACRE - Peripheral Access Control Register
+ * - AIPS_PACRF - Peripheral Access Control Register
+ * - AIPS_PACRG - Peripheral Access Control Register
+ * - AIPS_PACRH - Peripheral Access Control Register
+ * - AIPS_PACRI - Peripheral Access Control Register
+ * - AIPS_PACRJ - Peripheral Access Control Register
+ * - AIPS_PACRK - Peripheral Access Control Register
+ * - AIPS_PACRL - Peripheral Access Control Register
+ * - AIPS_PACRM - Peripheral Access Control Register
+ * - AIPS_PACRN - Peripheral Access Control Register
+ * - AIPS_PACRO - Peripheral Access Control Register
+ * - AIPS_PACRP - Peripheral Access Control Register
+ * - AIPS_PACRU - Peripheral Access Control Register
+ */
+
+#define AIPS_INSTANCE_COUNT (2U) /*!< Number of instances of the AIPS module. */
+#define AIPS0_IDX (0U) /*!< Instance number for AIPS0. */
+#define AIPS1_IDX (1U) /*!< Instance number for AIPS1. */
+
+/*******************************************************************************
+ * AIPS_MPRA - Master Privilege Register A
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_MPRA - Master Privilege Register A (RW)
+ *
+ * Reset value: 0x77700000U
+ *
+ * The MPRA specifies identical 4-bit fields defining the access-privilege level
+ * associated with a bus master to various peripherals on the chip. The register
+ * provides one field per bus master. At reset, the default value loaded into
+ * the MPRA fields is chip-specific. See the chip configuration details for the
+ * value of a particular device. A register field that maps to an unimplemented
+ * master or peripheral behaves as read-only-zero. Each master is assigned a logical
+ * ID from 0 to 15. See the master logical ID assignment table in the
+ * chip-specific AIPS information.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_MPRA register
+ */
+/*@{*/
+#define AIPS_RD_MPRA(base)       (AIPS_MPRA_REG(base))
+#define AIPS_WR_MPRA(base, value) (AIPS_MPRA_REG(base) = (value))
+#define AIPS_RMW_MPRA(base, mask, value) (AIPS_WR_MPRA(base, (AIPS_RD_MPRA(base) & ~(mask)) | (value)))
+#define AIPS_SET_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) |  (value)))
+#define AIPS_CLR_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) & ~(value)))
+#define AIPS_TOG_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_MPRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_MPRA, field MPL5[8] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL5 field. */
+#define AIPS_RD_MPRA_MPL5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL5_MASK) >> AIPS_MPRA_MPL5_SHIFT)
+#define AIPS_BRD_MPRA_MPL5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL5_SHIFT))
+
+/*! @brief Set the MPL5 field to a new value. */
+#define AIPS_WR_MPRA_MPL5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL5_MASK, AIPS_MPRA_MPL5(value)))
+#define AIPS_BWR_MPRA_MPL5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW5[9] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW5 field. */
+#define AIPS_RD_MPRA_MTW5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW5_MASK) >> AIPS_MPRA_MTW5_SHIFT)
+#define AIPS_BRD_MPRA_MTW5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW5_SHIFT))
+
+/*! @brief Set the MTW5 field to a new value. */
+#define AIPS_WR_MPRA_MTW5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW5_MASK, AIPS_MPRA_MTW5(value)))
+#define AIPS_BWR_MPRA_MTW5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR5[10] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR5 field. */
+#define AIPS_RD_MPRA_MTR5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR5_MASK) >> AIPS_MPRA_MTR5_SHIFT)
+#define AIPS_BRD_MPRA_MTR5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR5_SHIFT))
+
+/*! @brief Set the MTR5 field to a new value. */
+#define AIPS_WR_MPRA_MTR5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR5_MASK, AIPS_MPRA_MTR5(value)))
+#define AIPS_BWR_MPRA_MTR5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL4[12] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL4 field. */
+#define AIPS_RD_MPRA_MPL4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL4_MASK) >> AIPS_MPRA_MPL4_SHIFT)
+#define AIPS_BRD_MPRA_MPL4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL4_SHIFT))
+
+/*! @brief Set the MPL4 field to a new value. */
+#define AIPS_WR_MPRA_MPL4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL4_MASK, AIPS_MPRA_MPL4(value)))
+#define AIPS_BWR_MPRA_MPL4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW4[13] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW4 field. */
+#define AIPS_RD_MPRA_MTW4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW4_MASK) >> AIPS_MPRA_MTW4_SHIFT)
+#define AIPS_BRD_MPRA_MTW4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW4_SHIFT))
+
+/*! @brief Set the MTW4 field to a new value. */
+#define AIPS_WR_MPRA_MTW4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW4_MASK, AIPS_MPRA_MTW4(value)))
+#define AIPS_BWR_MPRA_MTW4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR4[14] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR4 field. */
+#define AIPS_RD_MPRA_MTR4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR4_MASK) >> AIPS_MPRA_MTR4_SHIFT)
+#define AIPS_BRD_MPRA_MTR4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR4_SHIFT))
+
+/*! @brief Set the MTR4 field to a new value. */
+#define AIPS_WR_MPRA_MTR4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR4_MASK, AIPS_MPRA_MTR4(value)))
+#define AIPS_BWR_MPRA_MTR4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL3[16] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL3 field. */
+#define AIPS_RD_MPRA_MPL3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL3_MASK) >> AIPS_MPRA_MPL3_SHIFT)
+#define AIPS_BRD_MPRA_MPL3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL3_SHIFT))
+
+/*! @brief Set the MPL3 field to a new value. */
+#define AIPS_WR_MPRA_MPL3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL3_MASK, AIPS_MPRA_MPL3(value)))
+#define AIPS_BWR_MPRA_MPL3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW3[17] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW3 field. */
+#define AIPS_RD_MPRA_MTW3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW3_MASK) >> AIPS_MPRA_MTW3_SHIFT)
+#define AIPS_BRD_MPRA_MTW3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW3_SHIFT))
+
+/*! @brief Set the MTW3 field to a new value. */
+#define AIPS_WR_MPRA_MTW3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW3_MASK, AIPS_MPRA_MTW3(value)))
+#define AIPS_BWR_MPRA_MTW3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR3[18] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR3 field. */
+#define AIPS_RD_MPRA_MTR3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR3_MASK) >> AIPS_MPRA_MTR3_SHIFT)
+#define AIPS_BRD_MPRA_MTR3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR3_SHIFT))
+
+/*! @brief Set the MTR3 field to a new value. */
+#define AIPS_WR_MPRA_MTR3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR3_MASK, AIPS_MPRA_MTR3(value)))
+#define AIPS_BWR_MPRA_MTR3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL2[20] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL2 field. */
+#define AIPS_RD_MPRA_MPL2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL2_MASK) >> AIPS_MPRA_MPL2_SHIFT)
+#define AIPS_BRD_MPRA_MPL2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL2_SHIFT))
+
+/*! @brief Set the MPL2 field to a new value. */
+#define AIPS_WR_MPRA_MPL2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL2_MASK, AIPS_MPRA_MPL2(value)))
+#define AIPS_BWR_MPRA_MPL2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW2[21] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW2 field. */
+#define AIPS_RD_MPRA_MTW2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW2_MASK) >> AIPS_MPRA_MTW2_SHIFT)
+#define AIPS_BRD_MPRA_MTW2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW2_SHIFT))
+
+/*! @brief Set the MTW2 field to a new value. */
+#define AIPS_WR_MPRA_MTW2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW2_MASK, AIPS_MPRA_MTW2(value)))
+#define AIPS_BWR_MPRA_MTW2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR2[22] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR2 field. */
+#define AIPS_RD_MPRA_MTR2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR2_MASK) >> AIPS_MPRA_MTR2_SHIFT)
+#define AIPS_BRD_MPRA_MTR2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR2_SHIFT))
+
+/*! @brief Set the MTR2 field to a new value. */
+#define AIPS_WR_MPRA_MTR2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR2_MASK, AIPS_MPRA_MTR2(value)))
+#define AIPS_BWR_MPRA_MTR2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL1[24] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL1 field. */
+#define AIPS_RD_MPRA_MPL1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL1_MASK) >> AIPS_MPRA_MPL1_SHIFT)
+#define AIPS_BRD_MPRA_MPL1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL1_SHIFT))
+
+/*! @brief Set the MPL1 field to a new value. */
+#define AIPS_WR_MPRA_MPL1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL1_MASK, AIPS_MPRA_MPL1(value)))
+#define AIPS_BWR_MPRA_MPL1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW1[25] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW1 field. */
+#define AIPS_RD_MPRA_MTW1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW1_MASK) >> AIPS_MPRA_MTW1_SHIFT)
+#define AIPS_BRD_MPRA_MTW1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW1_SHIFT))
+
+/*! @brief Set the MTW1 field to a new value. */
+#define AIPS_WR_MPRA_MTW1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW1_MASK, AIPS_MPRA_MTW1(value)))
+#define AIPS_BWR_MPRA_MTW1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR1[26] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR1 field. */
+#define AIPS_RD_MPRA_MTR1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR1_MASK) >> AIPS_MPRA_MTR1_SHIFT)
+#define AIPS_BRD_MPRA_MTR1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR1_SHIFT))
+
+/*! @brief Set the MTR1 field to a new value. */
+#define AIPS_WR_MPRA_MTR1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR1_MASK, AIPS_MPRA_MTR1(value)))
+#define AIPS_BWR_MPRA_MTR1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL0[28] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL0 field. */
+#define AIPS_RD_MPRA_MPL0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL0_MASK) >> AIPS_MPRA_MPL0_SHIFT)
+#define AIPS_BRD_MPRA_MPL0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL0_SHIFT))
+
+/*! @brief Set the MPL0 field to a new value. */
+#define AIPS_WR_MPRA_MPL0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL0_MASK, AIPS_MPRA_MPL0(value)))
+#define AIPS_BWR_MPRA_MPL0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW0[29] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW0 field. */
+#define AIPS_RD_MPRA_MTW0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW0_MASK) >> AIPS_MPRA_MTW0_SHIFT)
+#define AIPS_BRD_MPRA_MTW0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW0_SHIFT))
+
+/*! @brief Set the MTW0 field to a new value. */
+#define AIPS_WR_MPRA_MTW0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW0_MASK, AIPS_MPRA_MTW0(value)))
+#define AIPS_BWR_MPRA_MTW0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR0[30] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR0 field. */
+#define AIPS_RD_MPRA_MTR0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR0_MASK) >> AIPS_MPRA_MTR0_SHIFT)
+#define AIPS_BRD_MPRA_MTR0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR0_SHIFT))
+
+/*! @brief Set the MTR0 field to a new value. */
+#define AIPS_WR_MPRA_MTR0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR0_MASK, AIPS_MPRA_MTR0(value)))
+#define AIPS_BWR_MPRA_MTR0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRA - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRA - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x50004000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRA register
+ */
+/*@{*/
+#define AIPS_RD_PACRA(base)      (AIPS_PACRA_REG(base))
+#define AIPS_WR_PACRA(base, value) (AIPS_PACRA_REG(base) = (value))
+#define AIPS_RMW_PACRA(base, mask, value) (AIPS_WR_PACRA(base, (AIPS_RD_PACRA(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) |  (value)))
+#define AIPS_CLR_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) & ~(value)))
+#define AIPS_TOG_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRA, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP7 field. */
+#define AIPS_RD_PACRA_TP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP7_MASK) >> AIPS_PACRA_TP7_SHIFT)
+#define AIPS_BRD_PACRA_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRA_TP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP7_MASK, AIPS_PACRA_TP7(value)))
+#define AIPS_BWR_PACRA_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP7 field. */
+#define AIPS_RD_PACRA_WP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP7_MASK) >> AIPS_PACRA_WP7_SHIFT)
+#define AIPS_BRD_PACRA_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRA_WP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP7_MASK, AIPS_PACRA_WP7(value)))
+#define AIPS_BWR_PACRA_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP7 field. */
+#define AIPS_RD_PACRA_SP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP7_MASK) >> AIPS_PACRA_SP7_SHIFT)
+#define AIPS_BRD_PACRA_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRA_SP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP7_MASK, AIPS_PACRA_SP7(value)))
+#define AIPS_BWR_PACRA_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP6 field. */
+#define AIPS_RD_PACRA_TP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP6_MASK) >> AIPS_PACRA_TP6_SHIFT)
+#define AIPS_BRD_PACRA_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRA_TP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP6_MASK, AIPS_PACRA_TP6(value)))
+#define AIPS_BWR_PACRA_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP6 field. */
+#define AIPS_RD_PACRA_WP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP6_MASK) >> AIPS_PACRA_WP6_SHIFT)
+#define AIPS_BRD_PACRA_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRA_WP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP6_MASK, AIPS_PACRA_WP6(value)))
+#define AIPS_BWR_PACRA_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP6 field. */
+#define AIPS_RD_PACRA_SP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP6_MASK) >> AIPS_PACRA_SP6_SHIFT)
+#define AIPS_BRD_PACRA_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRA_SP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP6_MASK, AIPS_PACRA_SP6(value)))
+#define AIPS_BWR_PACRA_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP5 field. */
+#define AIPS_RD_PACRA_TP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP5_MASK) >> AIPS_PACRA_TP5_SHIFT)
+#define AIPS_BRD_PACRA_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRA_TP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP5_MASK, AIPS_PACRA_TP5(value)))
+#define AIPS_BWR_PACRA_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP5 field. */
+#define AIPS_RD_PACRA_WP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP5_MASK) >> AIPS_PACRA_WP5_SHIFT)
+#define AIPS_BRD_PACRA_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRA_WP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP5_MASK, AIPS_PACRA_WP5(value)))
+#define AIPS_BWR_PACRA_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP5 field. */
+#define AIPS_RD_PACRA_SP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP5_MASK) >> AIPS_PACRA_SP5_SHIFT)
+#define AIPS_BRD_PACRA_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRA_SP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP5_MASK, AIPS_PACRA_SP5(value)))
+#define AIPS_BWR_PACRA_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP4 field. */
+#define AIPS_RD_PACRA_TP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP4_MASK) >> AIPS_PACRA_TP4_SHIFT)
+#define AIPS_BRD_PACRA_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRA_TP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP4_MASK, AIPS_PACRA_TP4(value)))
+#define AIPS_BWR_PACRA_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP4 field. */
+#define AIPS_RD_PACRA_WP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP4_MASK) >> AIPS_PACRA_WP4_SHIFT)
+#define AIPS_BRD_PACRA_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRA_WP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP4_MASK, AIPS_PACRA_WP4(value)))
+#define AIPS_BWR_PACRA_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP4 field. */
+#define AIPS_RD_PACRA_SP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP4_MASK) >> AIPS_PACRA_SP4_SHIFT)
+#define AIPS_BRD_PACRA_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRA_SP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP4_MASK, AIPS_PACRA_SP4(value)))
+#define AIPS_BWR_PACRA_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP3 field. */
+#define AIPS_RD_PACRA_TP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP3_MASK) >> AIPS_PACRA_TP3_SHIFT)
+#define AIPS_BRD_PACRA_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRA_TP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP3_MASK, AIPS_PACRA_TP3(value)))
+#define AIPS_BWR_PACRA_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP3 field. */
+#define AIPS_RD_PACRA_WP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP3_MASK) >> AIPS_PACRA_WP3_SHIFT)
+#define AIPS_BRD_PACRA_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRA_WP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP3_MASK, AIPS_PACRA_WP3(value)))
+#define AIPS_BWR_PACRA_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP3 field. */
+#define AIPS_RD_PACRA_SP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP3_MASK) >> AIPS_PACRA_SP3_SHIFT)
+#define AIPS_BRD_PACRA_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRA_SP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP3_MASK, AIPS_PACRA_SP3(value)))
+#define AIPS_BWR_PACRA_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP2 field. */
+#define AIPS_RD_PACRA_TP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP2_MASK) >> AIPS_PACRA_TP2_SHIFT)
+#define AIPS_BRD_PACRA_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRA_TP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP2_MASK, AIPS_PACRA_TP2(value)))
+#define AIPS_BWR_PACRA_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP2 field. */
+#define AIPS_RD_PACRA_WP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP2_MASK) >> AIPS_PACRA_WP2_SHIFT)
+#define AIPS_BRD_PACRA_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRA_WP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP2_MASK, AIPS_PACRA_WP2(value)))
+#define AIPS_BWR_PACRA_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP2 field. */
+#define AIPS_RD_PACRA_SP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP2_MASK) >> AIPS_PACRA_SP2_SHIFT)
+#define AIPS_BRD_PACRA_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRA_SP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP2_MASK, AIPS_PACRA_SP2(value)))
+#define AIPS_BWR_PACRA_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP1 field. */
+#define AIPS_RD_PACRA_TP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP1_MASK) >> AIPS_PACRA_TP1_SHIFT)
+#define AIPS_BRD_PACRA_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRA_TP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP1_MASK, AIPS_PACRA_TP1(value)))
+#define AIPS_BWR_PACRA_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP1 field. */
+#define AIPS_RD_PACRA_WP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP1_MASK) >> AIPS_PACRA_WP1_SHIFT)
+#define AIPS_BRD_PACRA_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRA_WP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP1_MASK, AIPS_PACRA_WP1(value)))
+#define AIPS_BWR_PACRA_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP1 field. */
+#define AIPS_RD_PACRA_SP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP1_MASK) >> AIPS_PACRA_SP1_SHIFT)
+#define AIPS_BRD_PACRA_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRA_SP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP1_MASK, AIPS_PACRA_SP1(value)))
+#define AIPS_BWR_PACRA_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP0 field. */
+#define AIPS_RD_PACRA_TP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP0_MASK) >> AIPS_PACRA_TP0_SHIFT)
+#define AIPS_BRD_PACRA_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRA_TP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP0_MASK, AIPS_PACRA_TP0(value)))
+#define AIPS_BWR_PACRA_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP0 field. */
+#define AIPS_RD_PACRA_WP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP0_MASK) >> AIPS_PACRA_WP0_SHIFT)
+#define AIPS_BRD_PACRA_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRA_WP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP0_MASK, AIPS_PACRA_WP0(value)))
+#define AIPS_BWR_PACRA_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP0 field. */
+#define AIPS_RD_PACRA_SP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP0_MASK) >> AIPS_PACRA_SP0_SHIFT)
+#define AIPS_BRD_PACRA_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRA_SP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP0_MASK, AIPS_PACRA_SP0(value)))
+#define AIPS_BWR_PACRA_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRB - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRB - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44004400U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRB register
+ */
+/*@{*/
+#define AIPS_RD_PACRB(base)      (AIPS_PACRB_REG(base))
+#define AIPS_WR_PACRB(base, value) (AIPS_PACRB_REG(base) = (value))
+#define AIPS_RMW_PACRB(base, mask, value) (AIPS_WR_PACRB(base, (AIPS_RD_PACRB(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) |  (value)))
+#define AIPS_CLR_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) & ~(value)))
+#define AIPS_TOG_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRB bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRB, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP7 field. */
+#define AIPS_RD_PACRB_TP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP7_MASK) >> AIPS_PACRB_TP7_SHIFT)
+#define AIPS_BRD_PACRB_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRB_TP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP7_MASK, AIPS_PACRB_TP7(value)))
+#define AIPS_BWR_PACRB_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP7 field. */
+#define AIPS_RD_PACRB_WP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP7_MASK) >> AIPS_PACRB_WP7_SHIFT)
+#define AIPS_BRD_PACRB_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRB_WP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP7_MASK, AIPS_PACRB_WP7(value)))
+#define AIPS_BWR_PACRB_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP7 field. */
+#define AIPS_RD_PACRB_SP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP7_MASK) >> AIPS_PACRB_SP7_SHIFT)
+#define AIPS_BRD_PACRB_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRB_SP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP7_MASK, AIPS_PACRB_SP7(value)))
+#define AIPS_BWR_PACRB_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP6 field. */
+#define AIPS_RD_PACRB_TP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP6_MASK) >> AIPS_PACRB_TP6_SHIFT)
+#define AIPS_BRD_PACRB_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRB_TP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP6_MASK, AIPS_PACRB_TP6(value)))
+#define AIPS_BWR_PACRB_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP6 field. */
+#define AIPS_RD_PACRB_WP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP6_MASK) >> AIPS_PACRB_WP6_SHIFT)
+#define AIPS_BRD_PACRB_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRB_WP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP6_MASK, AIPS_PACRB_WP6(value)))
+#define AIPS_BWR_PACRB_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP6 field. */
+#define AIPS_RD_PACRB_SP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP6_MASK) >> AIPS_PACRB_SP6_SHIFT)
+#define AIPS_BRD_PACRB_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRB_SP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP6_MASK, AIPS_PACRB_SP6(value)))
+#define AIPS_BWR_PACRB_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP5 field. */
+#define AIPS_RD_PACRB_TP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP5_MASK) >> AIPS_PACRB_TP5_SHIFT)
+#define AIPS_BRD_PACRB_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRB_TP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP5_MASK, AIPS_PACRB_TP5(value)))
+#define AIPS_BWR_PACRB_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP5 field. */
+#define AIPS_RD_PACRB_WP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP5_MASK) >> AIPS_PACRB_WP5_SHIFT)
+#define AIPS_BRD_PACRB_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRB_WP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP5_MASK, AIPS_PACRB_WP5(value)))
+#define AIPS_BWR_PACRB_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP5 field. */
+#define AIPS_RD_PACRB_SP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP5_MASK) >> AIPS_PACRB_SP5_SHIFT)
+#define AIPS_BRD_PACRB_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRB_SP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP5_MASK, AIPS_PACRB_SP5(value)))
+#define AIPS_BWR_PACRB_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP4 field. */
+#define AIPS_RD_PACRB_TP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP4_MASK) >> AIPS_PACRB_TP4_SHIFT)
+#define AIPS_BRD_PACRB_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRB_TP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP4_MASK, AIPS_PACRB_TP4(value)))
+#define AIPS_BWR_PACRB_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP4 field. */
+#define AIPS_RD_PACRB_WP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP4_MASK) >> AIPS_PACRB_WP4_SHIFT)
+#define AIPS_BRD_PACRB_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRB_WP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP4_MASK, AIPS_PACRB_WP4(value)))
+#define AIPS_BWR_PACRB_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP4 field. */
+#define AIPS_RD_PACRB_SP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP4_MASK) >> AIPS_PACRB_SP4_SHIFT)
+#define AIPS_BRD_PACRB_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRB_SP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP4_MASK, AIPS_PACRB_SP4(value)))
+#define AIPS_BWR_PACRB_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP3 field. */
+#define AIPS_RD_PACRB_TP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP3_MASK) >> AIPS_PACRB_TP3_SHIFT)
+#define AIPS_BRD_PACRB_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRB_TP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP3_MASK, AIPS_PACRB_TP3(value)))
+#define AIPS_BWR_PACRB_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP3 field. */
+#define AIPS_RD_PACRB_WP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP3_MASK) >> AIPS_PACRB_WP3_SHIFT)
+#define AIPS_BRD_PACRB_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRB_WP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP3_MASK, AIPS_PACRB_WP3(value)))
+#define AIPS_BWR_PACRB_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP3 field. */
+#define AIPS_RD_PACRB_SP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP3_MASK) >> AIPS_PACRB_SP3_SHIFT)
+#define AIPS_BRD_PACRB_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRB_SP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP3_MASK, AIPS_PACRB_SP3(value)))
+#define AIPS_BWR_PACRB_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP2 field. */
+#define AIPS_RD_PACRB_TP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP2_MASK) >> AIPS_PACRB_TP2_SHIFT)
+#define AIPS_BRD_PACRB_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRB_TP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP2_MASK, AIPS_PACRB_TP2(value)))
+#define AIPS_BWR_PACRB_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP2 field. */
+#define AIPS_RD_PACRB_WP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP2_MASK) >> AIPS_PACRB_WP2_SHIFT)
+#define AIPS_BRD_PACRB_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRB_WP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP2_MASK, AIPS_PACRB_WP2(value)))
+#define AIPS_BWR_PACRB_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP2 field. */
+#define AIPS_RD_PACRB_SP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP2_MASK) >> AIPS_PACRB_SP2_SHIFT)
+#define AIPS_BRD_PACRB_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRB_SP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP2_MASK, AIPS_PACRB_SP2(value)))
+#define AIPS_BWR_PACRB_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP1 field. */
+#define AIPS_RD_PACRB_TP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP1_MASK) >> AIPS_PACRB_TP1_SHIFT)
+#define AIPS_BRD_PACRB_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRB_TP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP1_MASK, AIPS_PACRB_TP1(value)))
+#define AIPS_BWR_PACRB_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP1 field. */
+#define AIPS_RD_PACRB_WP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP1_MASK) >> AIPS_PACRB_WP1_SHIFT)
+#define AIPS_BRD_PACRB_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRB_WP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP1_MASK, AIPS_PACRB_WP1(value)))
+#define AIPS_BWR_PACRB_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP1 field. */
+#define AIPS_RD_PACRB_SP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP1_MASK) >> AIPS_PACRB_SP1_SHIFT)
+#define AIPS_BRD_PACRB_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRB_SP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP1_MASK, AIPS_PACRB_SP1(value)))
+#define AIPS_BWR_PACRB_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP0 field. */
+#define AIPS_RD_PACRB_TP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP0_MASK) >> AIPS_PACRB_TP0_SHIFT)
+#define AIPS_BRD_PACRB_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRB_TP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP0_MASK, AIPS_PACRB_TP0(value)))
+#define AIPS_BWR_PACRB_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP0 field. */
+#define AIPS_RD_PACRB_WP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP0_MASK) >> AIPS_PACRB_WP0_SHIFT)
+#define AIPS_BRD_PACRB_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRB_WP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP0_MASK, AIPS_PACRB_WP0(value)))
+#define AIPS_BWR_PACRB_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP0 field. */
+#define AIPS_RD_PACRB_SP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP0_MASK) >> AIPS_PACRB_SP0_SHIFT)
+#define AIPS_BRD_PACRB_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRB_SP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP0_MASK, AIPS_PACRB_SP0(value)))
+#define AIPS_BWR_PACRB_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRC - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRC - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRC register
+ */
+/*@{*/
+#define AIPS_RD_PACRC(base)      (AIPS_PACRC_REG(base))
+#define AIPS_WR_PACRC(base, value) (AIPS_PACRC_REG(base) = (value))
+#define AIPS_RMW_PACRC(base, mask, value) (AIPS_WR_PACRC(base, (AIPS_RD_PACRC(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) |  (value)))
+#define AIPS_CLR_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) & ~(value)))
+#define AIPS_TOG_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRC bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRC, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP7 field. */
+#define AIPS_RD_PACRC_TP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP7_MASK) >> AIPS_PACRC_TP7_SHIFT)
+#define AIPS_BRD_PACRC_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRC_TP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP7_MASK, AIPS_PACRC_TP7(value)))
+#define AIPS_BWR_PACRC_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP7 field. */
+#define AIPS_RD_PACRC_WP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP7_MASK) >> AIPS_PACRC_WP7_SHIFT)
+#define AIPS_BRD_PACRC_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRC_WP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP7_MASK, AIPS_PACRC_WP7(value)))
+#define AIPS_BWR_PACRC_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP7 field. */
+#define AIPS_RD_PACRC_SP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP7_MASK) >> AIPS_PACRC_SP7_SHIFT)
+#define AIPS_BRD_PACRC_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRC_SP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP7_MASK, AIPS_PACRC_SP7(value)))
+#define AIPS_BWR_PACRC_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP6 field. */
+#define AIPS_RD_PACRC_TP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP6_MASK) >> AIPS_PACRC_TP6_SHIFT)
+#define AIPS_BRD_PACRC_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRC_TP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP6_MASK, AIPS_PACRC_TP6(value)))
+#define AIPS_BWR_PACRC_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP6 field. */
+#define AIPS_RD_PACRC_WP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP6_MASK) >> AIPS_PACRC_WP6_SHIFT)
+#define AIPS_BRD_PACRC_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRC_WP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP6_MASK, AIPS_PACRC_WP6(value)))
+#define AIPS_BWR_PACRC_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP6 field. */
+#define AIPS_RD_PACRC_SP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP6_MASK) >> AIPS_PACRC_SP6_SHIFT)
+#define AIPS_BRD_PACRC_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRC_SP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP6_MASK, AIPS_PACRC_SP6(value)))
+#define AIPS_BWR_PACRC_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP5 field. */
+#define AIPS_RD_PACRC_TP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP5_MASK) >> AIPS_PACRC_TP5_SHIFT)
+#define AIPS_BRD_PACRC_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRC_TP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP5_MASK, AIPS_PACRC_TP5(value)))
+#define AIPS_BWR_PACRC_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP5 field. */
+#define AIPS_RD_PACRC_WP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP5_MASK) >> AIPS_PACRC_WP5_SHIFT)
+#define AIPS_BRD_PACRC_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRC_WP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP5_MASK, AIPS_PACRC_WP5(value)))
+#define AIPS_BWR_PACRC_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP5 field. */
+#define AIPS_RD_PACRC_SP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP5_MASK) >> AIPS_PACRC_SP5_SHIFT)
+#define AIPS_BRD_PACRC_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRC_SP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP5_MASK, AIPS_PACRC_SP5(value)))
+#define AIPS_BWR_PACRC_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP4 field. */
+#define AIPS_RD_PACRC_TP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP4_MASK) >> AIPS_PACRC_TP4_SHIFT)
+#define AIPS_BRD_PACRC_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRC_TP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP4_MASK, AIPS_PACRC_TP4(value)))
+#define AIPS_BWR_PACRC_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP4 field. */
+#define AIPS_RD_PACRC_WP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP4_MASK) >> AIPS_PACRC_WP4_SHIFT)
+#define AIPS_BRD_PACRC_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRC_WP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP4_MASK, AIPS_PACRC_WP4(value)))
+#define AIPS_BWR_PACRC_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP4 field. */
+#define AIPS_RD_PACRC_SP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP4_MASK) >> AIPS_PACRC_SP4_SHIFT)
+#define AIPS_BRD_PACRC_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRC_SP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP4_MASK, AIPS_PACRC_SP4(value)))
+#define AIPS_BWR_PACRC_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP3 field. */
+#define AIPS_RD_PACRC_TP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP3_MASK) >> AIPS_PACRC_TP3_SHIFT)
+#define AIPS_BRD_PACRC_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRC_TP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP3_MASK, AIPS_PACRC_TP3(value)))
+#define AIPS_BWR_PACRC_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP3 field. */
+#define AIPS_RD_PACRC_WP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP3_MASK) >> AIPS_PACRC_WP3_SHIFT)
+#define AIPS_BRD_PACRC_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRC_WP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP3_MASK, AIPS_PACRC_WP3(value)))
+#define AIPS_BWR_PACRC_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP3 field. */
+#define AIPS_RD_PACRC_SP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP3_MASK) >> AIPS_PACRC_SP3_SHIFT)
+#define AIPS_BRD_PACRC_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRC_SP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP3_MASK, AIPS_PACRC_SP3(value)))
+#define AIPS_BWR_PACRC_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP2 field. */
+#define AIPS_RD_PACRC_TP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP2_MASK) >> AIPS_PACRC_TP2_SHIFT)
+#define AIPS_BRD_PACRC_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRC_TP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP2_MASK, AIPS_PACRC_TP2(value)))
+#define AIPS_BWR_PACRC_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP2 field. */
+#define AIPS_RD_PACRC_WP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP2_MASK) >> AIPS_PACRC_WP2_SHIFT)
+#define AIPS_BRD_PACRC_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRC_WP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP2_MASK, AIPS_PACRC_WP2(value)))
+#define AIPS_BWR_PACRC_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP2 field. */
+#define AIPS_RD_PACRC_SP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP2_MASK) >> AIPS_PACRC_SP2_SHIFT)
+#define AIPS_BRD_PACRC_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRC_SP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP2_MASK, AIPS_PACRC_SP2(value)))
+#define AIPS_BWR_PACRC_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP1 field. */
+#define AIPS_RD_PACRC_TP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP1_MASK) >> AIPS_PACRC_TP1_SHIFT)
+#define AIPS_BRD_PACRC_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRC_TP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP1_MASK, AIPS_PACRC_TP1(value)))
+#define AIPS_BWR_PACRC_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP1 field. */
+#define AIPS_RD_PACRC_WP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP1_MASK) >> AIPS_PACRC_WP1_SHIFT)
+#define AIPS_BRD_PACRC_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRC_WP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP1_MASK, AIPS_PACRC_WP1(value)))
+#define AIPS_BWR_PACRC_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP1 field. */
+#define AIPS_RD_PACRC_SP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP1_MASK) >> AIPS_PACRC_SP1_SHIFT)
+#define AIPS_BRD_PACRC_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRC_SP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP1_MASK, AIPS_PACRC_SP1(value)))
+#define AIPS_BWR_PACRC_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP0 field. */
+#define AIPS_RD_PACRC_TP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP0_MASK) >> AIPS_PACRC_TP0_SHIFT)
+#define AIPS_BRD_PACRC_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRC_TP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP0_MASK, AIPS_PACRC_TP0(value)))
+#define AIPS_BWR_PACRC_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP0 field. */
+#define AIPS_RD_PACRC_WP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP0_MASK) >> AIPS_PACRC_WP0_SHIFT)
+#define AIPS_BRD_PACRC_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRC_WP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP0_MASK, AIPS_PACRC_WP0(value)))
+#define AIPS_BWR_PACRC_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP0 field. */
+#define AIPS_RD_PACRC_SP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP0_MASK) >> AIPS_PACRC_SP0_SHIFT)
+#define AIPS_BRD_PACRC_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRC_SP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP0_MASK, AIPS_PACRC_SP0(value)))
+#define AIPS_BWR_PACRC_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRD - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRD - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRD register
+ */
+/*@{*/
+#define AIPS_RD_PACRD(base)      (AIPS_PACRD_REG(base))
+#define AIPS_WR_PACRD(base, value) (AIPS_PACRD_REG(base) = (value))
+#define AIPS_RMW_PACRD(base, mask, value) (AIPS_WR_PACRD(base, (AIPS_RD_PACRD(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) |  (value)))
+#define AIPS_CLR_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) & ~(value)))
+#define AIPS_TOG_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRD bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRD, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP7 field. */
+#define AIPS_RD_PACRD_TP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP7_MASK) >> AIPS_PACRD_TP7_SHIFT)
+#define AIPS_BRD_PACRD_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRD_TP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP7_MASK, AIPS_PACRD_TP7(value)))
+#define AIPS_BWR_PACRD_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP7 field. */
+#define AIPS_RD_PACRD_WP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP7_MASK) >> AIPS_PACRD_WP7_SHIFT)
+#define AIPS_BRD_PACRD_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRD_WP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP7_MASK, AIPS_PACRD_WP7(value)))
+#define AIPS_BWR_PACRD_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP7 field. */
+#define AIPS_RD_PACRD_SP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP7_MASK) >> AIPS_PACRD_SP7_SHIFT)
+#define AIPS_BRD_PACRD_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRD_SP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP7_MASK, AIPS_PACRD_SP7(value)))
+#define AIPS_BWR_PACRD_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP6 field. */
+#define AIPS_RD_PACRD_TP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP6_MASK) >> AIPS_PACRD_TP6_SHIFT)
+#define AIPS_BRD_PACRD_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRD_TP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP6_MASK, AIPS_PACRD_TP6(value)))
+#define AIPS_BWR_PACRD_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP6 field. */
+#define AIPS_RD_PACRD_WP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP6_MASK) >> AIPS_PACRD_WP6_SHIFT)
+#define AIPS_BRD_PACRD_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRD_WP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP6_MASK, AIPS_PACRD_WP6(value)))
+#define AIPS_BWR_PACRD_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP6 field. */
+#define AIPS_RD_PACRD_SP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP6_MASK) >> AIPS_PACRD_SP6_SHIFT)
+#define AIPS_BRD_PACRD_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRD_SP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP6_MASK, AIPS_PACRD_SP6(value)))
+#define AIPS_BWR_PACRD_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP5 field. */
+#define AIPS_RD_PACRD_TP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP5_MASK) >> AIPS_PACRD_TP5_SHIFT)
+#define AIPS_BRD_PACRD_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRD_TP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP5_MASK, AIPS_PACRD_TP5(value)))
+#define AIPS_BWR_PACRD_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP5 field. */
+#define AIPS_RD_PACRD_WP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP5_MASK) >> AIPS_PACRD_WP5_SHIFT)
+#define AIPS_BRD_PACRD_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRD_WP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP5_MASK, AIPS_PACRD_WP5(value)))
+#define AIPS_BWR_PACRD_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP5 field. */
+#define AIPS_RD_PACRD_SP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP5_MASK) >> AIPS_PACRD_SP5_SHIFT)
+#define AIPS_BRD_PACRD_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRD_SP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP5_MASK, AIPS_PACRD_SP5(value)))
+#define AIPS_BWR_PACRD_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP4 field. */
+#define AIPS_RD_PACRD_TP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP4_MASK) >> AIPS_PACRD_TP4_SHIFT)
+#define AIPS_BRD_PACRD_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRD_TP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP4_MASK, AIPS_PACRD_TP4(value)))
+#define AIPS_BWR_PACRD_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP4 field. */
+#define AIPS_RD_PACRD_WP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP4_MASK) >> AIPS_PACRD_WP4_SHIFT)
+#define AIPS_BRD_PACRD_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRD_WP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP4_MASK, AIPS_PACRD_WP4(value)))
+#define AIPS_BWR_PACRD_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP4 field. */
+#define AIPS_RD_PACRD_SP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP4_MASK) >> AIPS_PACRD_SP4_SHIFT)
+#define AIPS_BRD_PACRD_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRD_SP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP4_MASK, AIPS_PACRD_SP4(value)))
+#define AIPS_BWR_PACRD_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP3 field. */
+#define AIPS_RD_PACRD_TP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP3_MASK) >> AIPS_PACRD_TP3_SHIFT)
+#define AIPS_BRD_PACRD_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRD_TP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP3_MASK, AIPS_PACRD_TP3(value)))
+#define AIPS_BWR_PACRD_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP3 field. */
+#define AIPS_RD_PACRD_WP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP3_MASK) >> AIPS_PACRD_WP3_SHIFT)
+#define AIPS_BRD_PACRD_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRD_WP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP3_MASK, AIPS_PACRD_WP3(value)))
+#define AIPS_BWR_PACRD_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP3 field. */
+#define AIPS_RD_PACRD_SP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP3_MASK) >> AIPS_PACRD_SP3_SHIFT)
+#define AIPS_BRD_PACRD_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRD_SP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP3_MASK, AIPS_PACRD_SP3(value)))
+#define AIPS_BWR_PACRD_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP2 field. */
+#define AIPS_RD_PACRD_TP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP2_MASK) >> AIPS_PACRD_TP2_SHIFT)
+#define AIPS_BRD_PACRD_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRD_TP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP2_MASK, AIPS_PACRD_TP2(value)))
+#define AIPS_BWR_PACRD_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP2 field. */
+#define AIPS_RD_PACRD_WP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP2_MASK) >> AIPS_PACRD_WP2_SHIFT)
+#define AIPS_BRD_PACRD_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRD_WP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP2_MASK, AIPS_PACRD_WP2(value)))
+#define AIPS_BWR_PACRD_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP2 field. */
+#define AIPS_RD_PACRD_SP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP2_MASK) >> AIPS_PACRD_SP2_SHIFT)
+#define AIPS_BRD_PACRD_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRD_SP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP2_MASK, AIPS_PACRD_SP2(value)))
+#define AIPS_BWR_PACRD_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP1 field. */
+#define AIPS_RD_PACRD_TP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP1_MASK) >> AIPS_PACRD_TP1_SHIFT)
+#define AIPS_BRD_PACRD_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRD_TP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP1_MASK, AIPS_PACRD_TP1(value)))
+#define AIPS_BWR_PACRD_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP1 field. */
+#define AIPS_RD_PACRD_WP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP1_MASK) >> AIPS_PACRD_WP1_SHIFT)
+#define AIPS_BRD_PACRD_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRD_WP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP1_MASK, AIPS_PACRD_WP1(value)))
+#define AIPS_BWR_PACRD_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP1 field. */
+#define AIPS_RD_PACRD_SP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP1_MASK) >> AIPS_PACRD_SP1_SHIFT)
+#define AIPS_BRD_PACRD_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRD_SP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP1_MASK, AIPS_PACRD_SP1(value)))
+#define AIPS_BWR_PACRD_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP0 field. */
+#define AIPS_RD_PACRD_TP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP0_MASK) >> AIPS_PACRD_TP0_SHIFT)
+#define AIPS_BRD_PACRD_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRD_TP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP0_MASK, AIPS_PACRD_TP0(value)))
+#define AIPS_BWR_PACRD_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP0 field. */
+#define AIPS_RD_PACRD_WP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP0_MASK) >> AIPS_PACRD_WP0_SHIFT)
+#define AIPS_BRD_PACRD_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRD_WP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP0_MASK, AIPS_PACRD_WP0(value)))
+#define AIPS_BWR_PACRD_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP0 field. */
+#define AIPS_RD_PACRD_SP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP0_MASK) >> AIPS_PACRD_SP0_SHIFT)
+#define AIPS_BRD_PACRD_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRD_SP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP0_MASK, AIPS_PACRD_SP0(value)))
+#define AIPS_BWR_PACRD_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRE - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRE - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRE register
+ */
+/*@{*/
+#define AIPS_RD_PACRE(base)      (AIPS_PACRE_REG(base))
+#define AIPS_WR_PACRE(base, value) (AIPS_PACRE_REG(base) = (value))
+#define AIPS_RMW_PACRE(base, mask, value) (AIPS_WR_PACRE(base, (AIPS_RD_PACRE(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) |  (value)))
+#define AIPS_CLR_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) & ~(value)))
+#define AIPS_TOG_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRE bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRE, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP7 field. */
+#define AIPS_RD_PACRE_TP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP7_MASK) >> AIPS_PACRE_TP7_SHIFT)
+#define AIPS_BRD_PACRE_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRE_TP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP7_MASK, AIPS_PACRE_TP7(value)))
+#define AIPS_BWR_PACRE_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP7 field. */
+#define AIPS_RD_PACRE_WP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP7_MASK) >> AIPS_PACRE_WP7_SHIFT)
+#define AIPS_BRD_PACRE_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRE_WP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP7_MASK, AIPS_PACRE_WP7(value)))
+#define AIPS_BWR_PACRE_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP7 field. */
+#define AIPS_RD_PACRE_SP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP7_MASK) >> AIPS_PACRE_SP7_SHIFT)
+#define AIPS_BRD_PACRE_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRE_SP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP7_MASK, AIPS_PACRE_SP7(value)))
+#define AIPS_BWR_PACRE_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP6 field. */
+#define AIPS_RD_PACRE_TP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP6_MASK) >> AIPS_PACRE_TP6_SHIFT)
+#define AIPS_BRD_PACRE_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRE_TP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP6_MASK, AIPS_PACRE_TP6(value)))
+#define AIPS_BWR_PACRE_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP6 field. */
+#define AIPS_RD_PACRE_WP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP6_MASK) >> AIPS_PACRE_WP6_SHIFT)
+#define AIPS_BRD_PACRE_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRE_WP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP6_MASK, AIPS_PACRE_WP6(value)))
+#define AIPS_BWR_PACRE_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP6 field. */
+#define AIPS_RD_PACRE_SP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP6_MASK) >> AIPS_PACRE_SP6_SHIFT)
+#define AIPS_BRD_PACRE_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRE_SP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP6_MASK, AIPS_PACRE_SP6(value)))
+#define AIPS_BWR_PACRE_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP5 field. */
+#define AIPS_RD_PACRE_TP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP5_MASK) >> AIPS_PACRE_TP5_SHIFT)
+#define AIPS_BRD_PACRE_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRE_TP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP5_MASK, AIPS_PACRE_TP5(value)))
+#define AIPS_BWR_PACRE_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP5 field. */
+#define AIPS_RD_PACRE_WP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP5_MASK) >> AIPS_PACRE_WP5_SHIFT)
+#define AIPS_BRD_PACRE_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRE_WP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP5_MASK, AIPS_PACRE_WP5(value)))
+#define AIPS_BWR_PACRE_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP5 field. */
+#define AIPS_RD_PACRE_SP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP5_MASK) >> AIPS_PACRE_SP5_SHIFT)
+#define AIPS_BRD_PACRE_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRE_SP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP5_MASK, AIPS_PACRE_SP5(value)))
+#define AIPS_BWR_PACRE_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP4 field. */
+#define AIPS_RD_PACRE_TP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP4_MASK) >> AIPS_PACRE_TP4_SHIFT)
+#define AIPS_BRD_PACRE_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRE_TP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP4_MASK, AIPS_PACRE_TP4(value)))
+#define AIPS_BWR_PACRE_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP4 field. */
+#define AIPS_RD_PACRE_WP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP4_MASK) >> AIPS_PACRE_WP4_SHIFT)
+#define AIPS_BRD_PACRE_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRE_WP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP4_MASK, AIPS_PACRE_WP4(value)))
+#define AIPS_BWR_PACRE_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP4 field. */
+#define AIPS_RD_PACRE_SP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP4_MASK) >> AIPS_PACRE_SP4_SHIFT)
+#define AIPS_BRD_PACRE_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRE_SP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP4_MASK, AIPS_PACRE_SP4(value)))
+#define AIPS_BWR_PACRE_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP3 field. */
+#define AIPS_RD_PACRE_TP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP3_MASK) >> AIPS_PACRE_TP3_SHIFT)
+#define AIPS_BRD_PACRE_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRE_TP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP3_MASK, AIPS_PACRE_TP3(value)))
+#define AIPS_BWR_PACRE_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP3 field. */
+#define AIPS_RD_PACRE_WP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP3_MASK) >> AIPS_PACRE_WP3_SHIFT)
+#define AIPS_BRD_PACRE_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRE_WP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP3_MASK, AIPS_PACRE_WP3(value)))
+#define AIPS_BWR_PACRE_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP3 field. */
+#define AIPS_RD_PACRE_SP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP3_MASK) >> AIPS_PACRE_SP3_SHIFT)
+#define AIPS_BRD_PACRE_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRE_SP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP3_MASK, AIPS_PACRE_SP3(value)))
+#define AIPS_BWR_PACRE_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP2 field. */
+#define AIPS_RD_PACRE_TP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP2_MASK) >> AIPS_PACRE_TP2_SHIFT)
+#define AIPS_BRD_PACRE_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRE_TP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP2_MASK, AIPS_PACRE_TP2(value)))
+#define AIPS_BWR_PACRE_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP2 field. */
+#define AIPS_RD_PACRE_WP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP2_MASK) >> AIPS_PACRE_WP2_SHIFT)
+#define AIPS_BRD_PACRE_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRE_WP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP2_MASK, AIPS_PACRE_WP2(value)))
+#define AIPS_BWR_PACRE_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP2 field. */
+#define AIPS_RD_PACRE_SP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP2_MASK) >> AIPS_PACRE_SP2_SHIFT)
+#define AIPS_BRD_PACRE_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRE_SP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP2_MASK, AIPS_PACRE_SP2(value)))
+#define AIPS_BWR_PACRE_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP1 field. */
+#define AIPS_RD_PACRE_TP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP1_MASK) >> AIPS_PACRE_TP1_SHIFT)
+#define AIPS_BRD_PACRE_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRE_TP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP1_MASK, AIPS_PACRE_TP1(value)))
+#define AIPS_BWR_PACRE_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP1 field. */
+#define AIPS_RD_PACRE_WP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP1_MASK) >> AIPS_PACRE_WP1_SHIFT)
+#define AIPS_BRD_PACRE_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRE_WP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP1_MASK, AIPS_PACRE_WP1(value)))
+#define AIPS_BWR_PACRE_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP1 field. */
+#define AIPS_RD_PACRE_SP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP1_MASK) >> AIPS_PACRE_SP1_SHIFT)
+#define AIPS_BRD_PACRE_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRE_SP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP1_MASK, AIPS_PACRE_SP1(value)))
+#define AIPS_BWR_PACRE_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP0 field. */
+#define AIPS_RD_PACRE_TP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP0_MASK) >> AIPS_PACRE_TP0_SHIFT)
+#define AIPS_BRD_PACRE_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRE_TP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP0_MASK, AIPS_PACRE_TP0(value)))
+#define AIPS_BWR_PACRE_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP0 field. */
+#define AIPS_RD_PACRE_WP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP0_MASK) >> AIPS_PACRE_WP0_SHIFT)
+#define AIPS_BRD_PACRE_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRE_WP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP0_MASK, AIPS_PACRE_WP0(value)))
+#define AIPS_BWR_PACRE_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP0 field. */
+#define AIPS_RD_PACRE_SP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP0_MASK) >> AIPS_PACRE_SP0_SHIFT)
+#define AIPS_BRD_PACRE_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRE_SP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP0_MASK, AIPS_PACRE_SP0(value)))
+#define AIPS_BWR_PACRE_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRF - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRF - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRF register
+ */
+/*@{*/
+#define AIPS_RD_PACRF(base)      (AIPS_PACRF_REG(base))
+#define AIPS_WR_PACRF(base, value) (AIPS_PACRF_REG(base) = (value))
+#define AIPS_RMW_PACRF(base, mask, value) (AIPS_WR_PACRF(base, (AIPS_RD_PACRF(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) |  (value)))
+#define AIPS_CLR_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) & ~(value)))
+#define AIPS_TOG_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRF bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRF, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP7 field. */
+#define AIPS_RD_PACRF_TP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP7_MASK) >> AIPS_PACRF_TP7_SHIFT)
+#define AIPS_BRD_PACRF_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRF_TP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP7_MASK, AIPS_PACRF_TP7(value)))
+#define AIPS_BWR_PACRF_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP7 field. */
+#define AIPS_RD_PACRF_WP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP7_MASK) >> AIPS_PACRF_WP7_SHIFT)
+#define AIPS_BRD_PACRF_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRF_WP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP7_MASK, AIPS_PACRF_WP7(value)))
+#define AIPS_BWR_PACRF_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP7 field. */
+#define AIPS_RD_PACRF_SP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP7_MASK) >> AIPS_PACRF_SP7_SHIFT)
+#define AIPS_BRD_PACRF_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRF_SP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP7_MASK, AIPS_PACRF_SP7(value)))
+#define AIPS_BWR_PACRF_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP6 field. */
+#define AIPS_RD_PACRF_TP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP6_MASK) >> AIPS_PACRF_TP6_SHIFT)
+#define AIPS_BRD_PACRF_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRF_TP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP6_MASK, AIPS_PACRF_TP6(value)))
+#define AIPS_BWR_PACRF_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP6 field. */
+#define AIPS_RD_PACRF_WP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP6_MASK) >> AIPS_PACRF_WP6_SHIFT)
+#define AIPS_BRD_PACRF_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRF_WP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP6_MASK, AIPS_PACRF_WP6(value)))
+#define AIPS_BWR_PACRF_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP6 field. */
+#define AIPS_RD_PACRF_SP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP6_MASK) >> AIPS_PACRF_SP6_SHIFT)
+#define AIPS_BRD_PACRF_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRF_SP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP6_MASK, AIPS_PACRF_SP6(value)))
+#define AIPS_BWR_PACRF_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP5 field. */
+#define AIPS_RD_PACRF_TP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP5_MASK) >> AIPS_PACRF_TP5_SHIFT)
+#define AIPS_BRD_PACRF_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRF_TP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP5_MASK, AIPS_PACRF_TP5(value)))
+#define AIPS_BWR_PACRF_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP5 field. */
+#define AIPS_RD_PACRF_WP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP5_MASK) >> AIPS_PACRF_WP5_SHIFT)
+#define AIPS_BRD_PACRF_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRF_WP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP5_MASK, AIPS_PACRF_WP5(value)))
+#define AIPS_BWR_PACRF_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP5 field. */
+#define AIPS_RD_PACRF_SP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP5_MASK) >> AIPS_PACRF_SP5_SHIFT)
+#define AIPS_BRD_PACRF_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRF_SP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP5_MASK, AIPS_PACRF_SP5(value)))
+#define AIPS_BWR_PACRF_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP4 field. */
+#define AIPS_RD_PACRF_TP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP4_MASK) >> AIPS_PACRF_TP4_SHIFT)
+#define AIPS_BRD_PACRF_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRF_TP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP4_MASK, AIPS_PACRF_TP4(value)))
+#define AIPS_BWR_PACRF_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP4 field. */
+#define AIPS_RD_PACRF_WP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP4_MASK) >> AIPS_PACRF_WP4_SHIFT)
+#define AIPS_BRD_PACRF_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRF_WP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP4_MASK, AIPS_PACRF_WP4(value)))
+#define AIPS_BWR_PACRF_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP4 field. */
+#define AIPS_RD_PACRF_SP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP4_MASK) >> AIPS_PACRF_SP4_SHIFT)
+#define AIPS_BRD_PACRF_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRF_SP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP4_MASK, AIPS_PACRF_SP4(value)))
+#define AIPS_BWR_PACRF_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP3 field. */
+#define AIPS_RD_PACRF_TP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP3_MASK) >> AIPS_PACRF_TP3_SHIFT)
+#define AIPS_BRD_PACRF_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRF_TP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP3_MASK, AIPS_PACRF_TP3(value)))
+#define AIPS_BWR_PACRF_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP3 field. */
+#define AIPS_RD_PACRF_WP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP3_MASK) >> AIPS_PACRF_WP3_SHIFT)
+#define AIPS_BRD_PACRF_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRF_WP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP3_MASK, AIPS_PACRF_WP3(value)))
+#define AIPS_BWR_PACRF_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP3 field. */
+#define AIPS_RD_PACRF_SP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP3_MASK) >> AIPS_PACRF_SP3_SHIFT)
+#define AIPS_BRD_PACRF_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRF_SP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP3_MASK, AIPS_PACRF_SP3(value)))
+#define AIPS_BWR_PACRF_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP2 field. */
+#define AIPS_RD_PACRF_TP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP2_MASK) >> AIPS_PACRF_TP2_SHIFT)
+#define AIPS_BRD_PACRF_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRF_TP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP2_MASK, AIPS_PACRF_TP2(value)))
+#define AIPS_BWR_PACRF_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP2 field. */
+#define AIPS_RD_PACRF_WP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP2_MASK) >> AIPS_PACRF_WP2_SHIFT)
+#define AIPS_BRD_PACRF_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRF_WP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP2_MASK, AIPS_PACRF_WP2(value)))
+#define AIPS_BWR_PACRF_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP2 field. */
+#define AIPS_RD_PACRF_SP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP2_MASK) >> AIPS_PACRF_SP2_SHIFT)
+#define AIPS_BRD_PACRF_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRF_SP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP2_MASK, AIPS_PACRF_SP2(value)))
+#define AIPS_BWR_PACRF_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP1 field. */
+#define AIPS_RD_PACRF_TP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP1_MASK) >> AIPS_PACRF_TP1_SHIFT)
+#define AIPS_BRD_PACRF_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRF_TP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP1_MASK, AIPS_PACRF_TP1(value)))
+#define AIPS_BWR_PACRF_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP1 field. */
+#define AIPS_RD_PACRF_WP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP1_MASK) >> AIPS_PACRF_WP1_SHIFT)
+#define AIPS_BRD_PACRF_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRF_WP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP1_MASK, AIPS_PACRF_WP1(value)))
+#define AIPS_BWR_PACRF_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP1 field. */
+#define AIPS_RD_PACRF_SP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP1_MASK) >> AIPS_PACRF_SP1_SHIFT)
+#define AIPS_BRD_PACRF_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRF_SP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP1_MASK, AIPS_PACRF_SP1(value)))
+#define AIPS_BWR_PACRF_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP0 field. */
+#define AIPS_RD_PACRF_TP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP0_MASK) >> AIPS_PACRF_TP0_SHIFT)
+#define AIPS_BRD_PACRF_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRF_TP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP0_MASK, AIPS_PACRF_TP0(value)))
+#define AIPS_BWR_PACRF_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP0 field. */
+#define AIPS_RD_PACRF_WP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP0_MASK) >> AIPS_PACRF_WP0_SHIFT)
+#define AIPS_BRD_PACRF_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRF_WP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP0_MASK, AIPS_PACRF_WP0(value)))
+#define AIPS_BWR_PACRF_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP0 field. */
+#define AIPS_RD_PACRF_SP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP0_MASK) >> AIPS_PACRF_SP0_SHIFT)
+#define AIPS_BRD_PACRF_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRF_SP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP0_MASK, AIPS_PACRF_SP0(value)))
+#define AIPS_BWR_PACRF_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRG - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRG - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRG register
+ */
+/*@{*/
+#define AIPS_RD_PACRG(base)      (AIPS_PACRG_REG(base))
+#define AIPS_WR_PACRG(base, value) (AIPS_PACRG_REG(base) = (value))
+#define AIPS_RMW_PACRG(base, mask, value) (AIPS_WR_PACRG(base, (AIPS_RD_PACRG(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) |  (value)))
+#define AIPS_CLR_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) & ~(value)))
+#define AIPS_TOG_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRG bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRG, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP7 field. */
+#define AIPS_RD_PACRG_TP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP7_MASK) >> AIPS_PACRG_TP7_SHIFT)
+#define AIPS_BRD_PACRG_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRG_TP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP7_MASK, AIPS_PACRG_TP7(value)))
+#define AIPS_BWR_PACRG_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP7 field. */
+#define AIPS_RD_PACRG_WP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP7_MASK) >> AIPS_PACRG_WP7_SHIFT)
+#define AIPS_BRD_PACRG_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRG_WP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP7_MASK, AIPS_PACRG_WP7(value)))
+#define AIPS_BWR_PACRG_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP7 field. */
+#define AIPS_RD_PACRG_SP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP7_MASK) >> AIPS_PACRG_SP7_SHIFT)
+#define AIPS_BRD_PACRG_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRG_SP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP7_MASK, AIPS_PACRG_SP7(value)))
+#define AIPS_BWR_PACRG_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP6 field. */
+#define AIPS_RD_PACRG_TP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP6_MASK) >> AIPS_PACRG_TP6_SHIFT)
+#define AIPS_BRD_PACRG_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRG_TP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP6_MASK, AIPS_PACRG_TP6(value)))
+#define AIPS_BWR_PACRG_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP6 field. */
+#define AIPS_RD_PACRG_WP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP6_MASK) >> AIPS_PACRG_WP6_SHIFT)
+#define AIPS_BRD_PACRG_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRG_WP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP6_MASK, AIPS_PACRG_WP6(value)))
+#define AIPS_BWR_PACRG_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP6 field. */
+#define AIPS_RD_PACRG_SP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP6_MASK) >> AIPS_PACRG_SP6_SHIFT)
+#define AIPS_BRD_PACRG_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRG_SP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP6_MASK, AIPS_PACRG_SP6(value)))
+#define AIPS_BWR_PACRG_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP5 field. */
+#define AIPS_RD_PACRG_TP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP5_MASK) >> AIPS_PACRG_TP5_SHIFT)
+#define AIPS_BRD_PACRG_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRG_TP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP5_MASK, AIPS_PACRG_TP5(value)))
+#define AIPS_BWR_PACRG_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP5 field. */
+#define AIPS_RD_PACRG_WP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP5_MASK) >> AIPS_PACRG_WP5_SHIFT)
+#define AIPS_BRD_PACRG_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRG_WP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP5_MASK, AIPS_PACRG_WP5(value)))
+#define AIPS_BWR_PACRG_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP5 field. */
+#define AIPS_RD_PACRG_SP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP5_MASK) >> AIPS_PACRG_SP5_SHIFT)
+#define AIPS_BRD_PACRG_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRG_SP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP5_MASK, AIPS_PACRG_SP5(value)))
+#define AIPS_BWR_PACRG_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP4 field. */
+#define AIPS_RD_PACRG_TP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP4_MASK) >> AIPS_PACRG_TP4_SHIFT)
+#define AIPS_BRD_PACRG_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRG_TP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP4_MASK, AIPS_PACRG_TP4(value)))
+#define AIPS_BWR_PACRG_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP4 field. */
+#define AIPS_RD_PACRG_WP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP4_MASK) >> AIPS_PACRG_WP4_SHIFT)
+#define AIPS_BRD_PACRG_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRG_WP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP4_MASK, AIPS_PACRG_WP4(value)))
+#define AIPS_BWR_PACRG_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP4 field. */
+#define AIPS_RD_PACRG_SP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP4_MASK) >> AIPS_PACRG_SP4_SHIFT)
+#define AIPS_BRD_PACRG_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRG_SP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP4_MASK, AIPS_PACRG_SP4(value)))
+#define AIPS_BWR_PACRG_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP3 field. */
+#define AIPS_RD_PACRG_TP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP3_MASK) >> AIPS_PACRG_TP3_SHIFT)
+#define AIPS_BRD_PACRG_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRG_TP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP3_MASK, AIPS_PACRG_TP3(value)))
+#define AIPS_BWR_PACRG_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP3 field. */
+#define AIPS_RD_PACRG_WP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP3_MASK) >> AIPS_PACRG_WP3_SHIFT)
+#define AIPS_BRD_PACRG_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRG_WP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP3_MASK, AIPS_PACRG_WP3(value)))
+#define AIPS_BWR_PACRG_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP3 field. */
+#define AIPS_RD_PACRG_SP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP3_MASK) >> AIPS_PACRG_SP3_SHIFT)
+#define AIPS_BRD_PACRG_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRG_SP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP3_MASK, AIPS_PACRG_SP3(value)))
+#define AIPS_BWR_PACRG_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP2 field. */
+#define AIPS_RD_PACRG_TP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP2_MASK) >> AIPS_PACRG_TP2_SHIFT)
+#define AIPS_BRD_PACRG_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRG_TP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP2_MASK, AIPS_PACRG_TP2(value)))
+#define AIPS_BWR_PACRG_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP2 field. */
+#define AIPS_RD_PACRG_WP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP2_MASK) >> AIPS_PACRG_WP2_SHIFT)
+#define AIPS_BRD_PACRG_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRG_WP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP2_MASK, AIPS_PACRG_WP2(value)))
+#define AIPS_BWR_PACRG_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP2 field. */
+#define AIPS_RD_PACRG_SP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP2_MASK) >> AIPS_PACRG_SP2_SHIFT)
+#define AIPS_BRD_PACRG_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRG_SP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP2_MASK, AIPS_PACRG_SP2(value)))
+#define AIPS_BWR_PACRG_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP1 field. */
+#define AIPS_RD_PACRG_TP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP1_MASK) >> AIPS_PACRG_TP1_SHIFT)
+#define AIPS_BRD_PACRG_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRG_TP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP1_MASK, AIPS_PACRG_TP1(value)))
+#define AIPS_BWR_PACRG_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP1 field. */
+#define AIPS_RD_PACRG_WP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP1_MASK) >> AIPS_PACRG_WP1_SHIFT)
+#define AIPS_BRD_PACRG_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRG_WP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP1_MASK, AIPS_PACRG_WP1(value)))
+#define AIPS_BWR_PACRG_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP1 field. */
+#define AIPS_RD_PACRG_SP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP1_MASK) >> AIPS_PACRG_SP1_SHIFT)
+#define AIPS_BRD_PACRG_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRG_SP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP1_MASK, AIPS_PACRG_SP1(value)))
+#define AIPS_BWR_PACRG_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP0 field. */
+#define AIPS_RD_PACRG_TP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP0_MASK) >> AIPS_PACRG_TP0_SHIFT)
+#define AIPS_BRD_PACRG_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRG_TP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP0_MASK, AIPS_PACRG_TP0(value)))
+#define AIPS_BWR_PACRG_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP0 field. */
+#define AIPS_RD_PACRG_WP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP0_MASK) >> AIPS_PACRG_WP0_SHIFT)
+#define AIPS_BRD_PACRG_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRG_WP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP0_MASK, AIPS_PACRG_WP0(value)))
+#define AIPS_BWR_PACRG_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP0 field. */
+#define AIPS_RD_PACRG_SP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP0_MASK) >> AIPS_PACRG_SP0_SHIFT)
+#define AIPS_BRD_PACRG_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRG_SP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP0_MASK, AIPS_PACRG_SP0(value)))
+#define AIPS_BWR_PACRG_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRH - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRH - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRH register
+ */
+/*@{*/
+#define AIPS_RD_PACRH(base)      (AIPS_PACRH_REG(base))
+#define AIPS_WR_PACRH(base, value) (AIPS_PACRH_REG(base) = (value))
+#define AIPS_RMW_PACRH(base, mask, value) (AIPS_WR_PACRH(base, (AIPS_RD_PACRH(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) |  (value)))
+#define AIPS_CLR_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) & ~(value)))
+#define AIPS_TOG_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRH bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRH, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP7 field. */
+#define AIPS_RD_PACRH_TP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP7_MASK) >> AIPS_PACRH_TP7_SHIFT)
+#define AIPS_BRD_PACRH_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRH_TP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP7_MASK, AIPS_PACRH_TP7(value)))
+#define AIPS_BWR_PACRH_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP7 field. */
+#define AIPS_RD_PACRH_WP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP7_MASK) >> AIPS_PACRH_WP7_SHIFT)
+#define AIPS_BRD_PACRH_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRH_WP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP7_MASK, AIPS_PACRH_WP7(value)))
+#define AIPS_BWR_PACRH_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP7 field. */
+#define AIPS_RD_PACRH_SP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP7_MASK) >> AIPS_PACRH_SP7_SHIFT)
+#define AIPS_BRD_PACRH_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRH_SP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP7_MASK, AIPS_PACRH_SP7(value)))
+#define AIPS_BWR_PACRH_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP6 field. */
+#define AIPS_RD_PACRH_TP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP6_MASK) >> AIPS_PACRH_TP6_SHIFT)
+#define AIPS_BRD_PACRH_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRH_TP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP6_MASK, AIPS_PACRH_TP6(value)))
+#define AIPS_BWR_PACRH_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP6 field. */
+#define AIPS_RD_PACRH_WP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP6_MASK) >> AIPS_PACRH_WP6_SHIFT)
+#define AIPS_BRD_PACRH_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRH_WP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP6_MASK, AIPS_PACRH_WP6(value)))
+#define AIPS_BWR_PACRH_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP6 field. */
+#define AIPS_RD_PACRH_SP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP6_MASK) >> AIPS_PACRH_SP6_SHIFT)
+#define AIPS_BRD_PACRH_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRH_SP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP6_MASK, AIPS_PACRH_SP6(value)))
+#define AIPS_BWR_PACRH_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP5 field. */
+#define AIPS_RD_PACRH_TP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP5_MASK) >> AIPS_PACRH_TP5_SHIFT)
+#define AIPS_BRD_PACRH_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRH_TP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP5_MASK, AIPS_PACRH_TP5(value)))
+#define AIPS_BWR_PACRH_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP5 field. */
+#define AIPS_RD_PACRH_WP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP5_MASK) >> AIPS_PACRH_WP5_SHIFT)
+#define AIPS_BRD_PACRH_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRH_WP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP5_MASK, AIPS_PACRH_WP5(value)))
+#define AIPS_BWR_PACRH_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP5 field. */
+#define AIPS_RD_PACRH_SP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP5_MASK) >> AIPS_PACRH_SP5_SHIFT)
+#define AIPS_BRD_PACRH_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRH_SP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP5_MASK, AIPS_PACRH_SP5(value)))
+#define AIPS_BWR_PACRH_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP4 field. */
+#define AIPS_RD_PACRH_TP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP4_MASK) >> AIPS_PACRH_TP4_SHIFT)
+#define AIPS_BRD_PACRH_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRH_TP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP4_MASK, AIPS_PACRH_TP4(value)))
+#define AIPS_BWR_PACRH_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP4 field. */
+#define AIPS_RD_PACRH_WP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP4_MASK) >> AIPS_PACRH_WP4_SHIFT)
+#define AIPS_BRD_PACRH_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRH_WP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP4_MASK, AIPS_PACRH_WP4(value)))
+#define AIPS_BWR_PACRH_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP4 field. */
+#define AIPS_RD_PACRH_SP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP4_MASK) >> AIPS_PACRH_SP4_SHIFT)
+#define AIPS_BRD_PACRH_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRH_SP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP4_MASK, AIPS_PACRH_SP4(value)))
+#define AIPS_BWR_PACRH_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP3 field. */
+#define AIPS_RD_PACRH_TP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP3_MASK) >> AIPS_PACRH_TP3_SHIFT)
+#define AIPS_BRD_PACRH_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRH_TP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP3_MASK, AIPS_PACRH_TP3(value)))
+#define AIPS_BWR_PACRH_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP3 field. */
+#define AIPS_RD_PACRH_WP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP3_MASK) >> AIPS_PACRH_WP3_SHIFT)
+#define AIPS_BRD_PACRH_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRH_WP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP3_MASK, AIPS_PACRH_WP3(value)))
+#define AIPS_BWR_PACRH_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP3 field. */
+#define AIPS_RD_PACRH_SP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP3_MASK) >> AIPS_PACRH_SP3_SHIFT)
+#define AIPS_BRD_PACRH_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRH_SP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP3_MASK, AIPS_PACRH_SP3(value)))
+#define AIPS_BWR_PACRH_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP2 field. */
+#define AIPS_RD_PACRH_TP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP2_MASK) >> AIPS_PACRH_TP2_SHIFT)
+#define AIPS_BRD_PACRH_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRH_TP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP2_MASK, AIPS_PACRH_TP2(value)))
+#define AIPS_BWR_PACRH_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP2 field. */
+#define AIPS_RD_PACRH_WP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP2_MASK) >> AIPS_PACRH_WP2_SHIFT)
+#define AIPS_BRD_PACRH_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRH_WP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP2_MASK, AIPS_PACRH_WP2(value)))
+#define AIPS_BWR_PACRH_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP2 field. */
+#define AIPS_RD_PACRH_SP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP2_MASK) >> AIPS_PACRH_SP2_SHIFT)
+#define AIPS_BRD_PACRH_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRH_SP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP2_MASK, AIPS_PACRH_SP2(value)))
+#define AIPS_BWR_PACRH_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP1 field. */
+#define AIPS_RD_PACRH_TP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP1_MASK) >> AIPS_PACRH_TP1_SHIFT)
+#define AIPS_BRD_PACRH_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRH_TP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP1_MASK, AIPS_PACRH_TP1(value)))
+#define AIPS_BWR_PACRH_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP1 field. */
+#define AIPS_RD_PACRH_WP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP1_MASK) >> AIPS_PACRH_WP1_SHIFT)
+#define AIPS_BRD_PACRH_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRH_WP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP1_MASK, AIPS_PACRH_WP1(value)))
+#define AIPS_BWR_PACRH_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP1 field. */
+#define AIPS_RD_PACRH_SP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP1_MASK) >> AIPS_PACRH_SP1_SHIFT)
+#define AIPS_BRD_PACRH_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRH_SP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP1_MASK, AIPS_PACRH_SP1(value)))
+#define AIPS_BWR_PACRH_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP0 field. */
+#define AIPS_RD_PACRH_TP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP0_MASK) >> AIPS_PACRH_TP0_SHIFT)
+#define AIPS_BRD_PACRH_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRH_TP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP0_MASK, AIPS_PACRH_TP0(value)))
+#define AIPS_BWR_PACRH_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP0 field. */
+#define AIPS_RD_PACRH_WP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP0_MASK) >> AIPS_PACRH_WP0_SHIFT)
+#define AIPS_BRD_PACRH_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRH_WP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP0_MASK, AIPS_PACRH_WP0(value)))
+#define AIPS_BWR_PACRH_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP0 field. */
+#define AIPS_RD_PACRH_SP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP0_MASK) >> AIPS_PACRH_SP0_SHIFT)
+#define AIPS_BRD_PACRH_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRH_SP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP0_MASK, AIPS_PACRH_SP0(value)))
+#define AIPS_BWR_PACRH_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRI - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRI - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRI register
+ */
+/*@{*/
+#define AIPS_RD_PACRI(base)      (AIPS_PACRI_REG(base))
+#define AIPS_WR_PACRI(base, value) (AIPS_PACRI_REG(base) = (value))
+#define AIPS_RMW_PACRI(base, mask, value) (AIPS_WR_PACRI(base, (AIPS_RD_PACRI(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) |  (value)))
+#define AIPS_CLR_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) & ~(value)))
+#define AIPS_TOG_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRI bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRI, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP7 field. */
+#define AIPS_RD_PACRI_TP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP7_MASK) >> AIPS_PACRI_TP7_SHIFT)
+#define AIPS_BRD_PACRI_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRI_TP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP7_MASK, AIPS_PACRI_TP7(value)))
+#define AIPS_BWR_PACRI_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP7 field. */
+#define AIPS_RD_PACRI_WP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP7_MASK) >> AIPS_PACRI_WP7_SHIFT)
+#define AIPS_BRD_PACRI_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRI_WP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP7_MASK, AIPS_PACRI_WP7(value)))
+#define AIPS_BWR_PACRI_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP7 field. */
+#define AIPS_RD_PACRI_SP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP7_MASK) >> AIPS_PACRI_SP7_SHIFT)
+#define AIPS_BRD_PACRI_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRI_SP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP7_MASK, AIPS_PACRI_SP7(value)))
+#define AIPS_BWR_PACRI_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP6 field. */
+#define AIPS_RD_PACRI_TP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP6_MASK) >> AIPS_PACRI_TP6_SHIFT)
+#define AIPS_BRD_PACRI_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRI_TP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP6_MASK, AIPS_PACRI_TP6(value)))
+#define AIPS_BWR_PACRI_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP6 field. */
+#define AIPS_RD_PACRI_WP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP6_MASK) >> AIPS_PACRI_WP6_SHIFT)
+#define AIPS_BRD_PACRI_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRI_WP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP6_MASK, AIPS_PACRI_WP6(value)))
+#define AIPS_BWR_PACRI_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP6 field. */
+#define AIPS_RD_PACRI_SP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP6_MASK) >> AIPS_PACRI_SP6_SHIFT)
+#define AIPS_BRD_PACRI_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRI_SP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP6_MASK, AIPS_PACRI_SP6(value)))
+#define AIPS_BWR_PACRI_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP5 field. */
+#define AIPS_RD_PACRI_TP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP5_MASK) >> AIPS_PACRI_TP5_SHIFT)
+#define AIPS_BRD_PACRI_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRI_TP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP5_MASK, AIPS_PACRI_TP5(value)))
+#define AIPS_BWR_PACRI_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP5 field. */
+#define AIPS_RD_PACRI_WP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP5_MASK) >> AIPS_PACRI_WP5_SHIFT)
+#define AIPS_BRD_PACRI_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRI_WP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP5_MASK, AIPS_PACRI_WP5(value)))
+#define AIPS_BWR_PACRI_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP5 field. */
+#define AIPS_RD_PACRI_SP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP5_MASK) >> AIPS_PACRI_SP5_SHIFT)
+#define AIPS_BRD_PACRI_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRI_SP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP5_MASK, AIPS_PACRI_SP5(value)))
+#define AIPS_BWR_PACRI_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP4 field. */
+#define AIPS_RD_PACRI_TP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP4_MASK) >> AIPS_PACRI_TP4_SHIFT)
+#define AIPS_BRD_PACRI_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRI_TP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP4_MASK, AIPS_PACRI_TP4(value)))
+#define AIPS_BWR_PACRI_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP4 field. */
+#define AIPS_RD_PACRI_WP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP4_MASK) >> AIPS_PACRI_WP4_SHIFT)
+#define AIPS_BRD_PACRI_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRI_WP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP4_MASK, AIPS_PACRI_WP4(value)))
+#define AIPS_BWR_PACRI_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP4 field. */
+#define AIPS_RD_PACRI_SP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP4_MASK) >> AIPS_PACRI_SP4_SHIFT)
+#define AIPS_BRD_PACRI_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRI_SP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP4_MASK, AIPS_PACRI_SP4(value)))
+#define AIPS_BWR_PACRI_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP3 field. */
+#define AIPS_RD_PACRI_TP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP3_MASK) >> AIPS_PACRI_TP3_SHIFT)
+#define AIPS_BRD_PACRI_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRI_TP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP3_MASK, AIPS_PACRI_TP3(value)))
+#define AIPS_BWR_PACRI_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP3 field. */
+#define AIPS_RD_PACRI_WP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP3_MASK) >> AIPS_PACRI_WP3_SHIFT)
+#define AIPS_BRD_PACRI_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRI_WP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP3_MASK, AIPS_PACRI_WP3(value)))
+#define AIPS_BWR_PACRI_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP3 field. */
+#define AIPS_RD_PACRI_SP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP3_MASK) >> AIPS_PACRI_SP3_SHIFT)
+#define AIPS_BRD_PACRI_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRI_SP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP3_MASK, AIPS_PACRI_SP3(value)))
+#define AIPS_BWR_PACRI_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP2 field. */
+#define AIPS_RD_PACRI_TP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP2_MASK) >> AIPS_PACRI_TP2_SHIFT)
+#define AIPS_BRD_PACRI_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRI_TP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP2_MASK, AIPS_PACRI_TP2(value)))
+#define AIPS_BWR_PACRI_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP2 field. */
+#define AIPS_RD_PACRI_WP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP2_MASK) >> AIPS_PACRI_WP2_SHIFT)
+#define AIPS_BRD_PACRI_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRI_WP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP2_MASK, AIPS_PACRI_WP2(value)))
+#define AIPS_BWR_PACRI_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP2 field. */
+#define AIPS_RD_PACRI_SP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP2_MASK) >> AIPS_PACRI_SP2_SHIFT)
+#define AIPS_BRD_PACRI_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRI_SP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP2_MASK, AIPS_PACRI_SP2(value)))
+#define AIPS_BWR_PACRI_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP1 field. */
+#define AIPS_RD_PACRI_TP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP1_MASK) >> AIPS_PACRI_TP1_SHIFT)
+#define AIPS_BRD_PACRI_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRI_TP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP1_MASK, AIPS_PACRI_TP1(value)))
+#define AIPS_BWR_PACRI_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP1 field. */
+#define AIPS_RD_PACRI_WP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP1_MASK) >> AIPS_PACRI_WP1_SHIFT)
+#define AIPS_BRD_PACRI_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRI_WP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP1_MASK, AIPS_PACRI_WP1(value)))
+#define AIPS_BWR_PACRI_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP1 field. */
+#define AIPS_RD_PACRI_SP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP1_MASK) >> AIPS_PACRI_SP1_SHIFT)
+#define AIPS_BRD_PACRI_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRI_SP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP1_MASK, AIPS_PACRI_SP1(value)))
+#define AIPS_BWR_PACRI_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP0 field. */
+#define AIPS_RD_PACRI_TP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP0_MASK) >> AIPS_PACRI_TP0_SHIFT)
+#define AIPS_BRD_PACRI_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRI_TP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP0_MASK, AIPS_PACRI_TP0(value)))
+#define AIPS_BWR_PACRI_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP0 field. */
+#define AIPS_RD_PACRI_WP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP0_MASK) >> AIPS_PACRI_WP0_SHIFT)
+#define AIPS_BRD_PACRI_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRI_WP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP0_MASK, AIPS_PACRI_WP0(value)))
+#define AIPS_BWR_PACRI_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP0 field. */
+#define AIPS_RD_PACRI_SP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP0_MASK) >> AIPS_PACRI_SP0_SHIFT)
+#define AIPS_BRD_PACRI_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRI_SP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP0_MASK, AIPS_PACRI_SP0(value)))
+#define AIPS_BWR_PACRI_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRJ - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRJ - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRJ register
+ */
+/*@{*/
+#define AIPS_RD_PACRJ(base)      (AIPS_PACRJ_REG(base))
+#define AIPS_WR_PACRJ(base, value) (AIPS_PACRJ_REG(base) = (value))
+#define AIPS_RMW_PACRJ(base, mask, value) (AIPS_WR_PACRJ(base, (AIPS_RD_PACRJ(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) |  (value)))
+#define AIPS_CLR_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) & ~(value)))
+#define AIPS_TOG_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRJ bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRJ, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP7 field. */
+#define AIPS_RD_PACRJ_TP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP7_MASK) >> AIPS_PACRJ_TP7_SHIFT)
+#define AIPS_BRD_PACRJ_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRJ_TP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP7_MASK, AIPS_PACRJ_TP7(value)))
+#define AIPS_BWR_PACRJ_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP7 field. */
+#define AIPS_RD_PACRJ_WP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP7_MASK) >> AIPS_PACRJ_WP7_SHIFT)
+#define AIPS_BRD_PACRJ_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRJ_WP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP7_MASK, AIPS_PACRJ_WP7(value)))
+#define AIPS_BWR_PACRJ_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP7 field. */
+#define AIPS_RD_PACRJ_SP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP7_MASK) >> AIPS_PACRJ_SP7_SHIFT)
+#define AIPS_BRD_PACRJ_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRJ_SP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP7_MASK, AIPS_PACRJ_SP7(value)))
+#define AIPS_BWR_PACRJ_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP6 field. */
+#define AIPS_RD_PACRJ_TP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP6_MASK) >> AIPS_PACRJ_TP6_SHIFT)
+#define AIPS_BRD_PACRJ_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRJ_TP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP6_MASK, AIPS_PACRJ_TP6(value)))
+#define AIPS_BWR_PACRJ_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP6 field. */
+#define AIPS_RD_PACRJ_WP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP6_MASK) >> AIPS_PACRJ_WP6_SHIFT)
+#define AIPS_BRD_PACRJ_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRJ_WP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP6_MASK, AIPS_PACRJ_WP6(value)))
+#define AIPS_BWR_PACRJ_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP6 field. */
+#define AIPS_RD_PACRJ_SP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP6_MASK) >> AIPS_PACRJ_SP6_SHIFT)
+#define AIPS_BRD_PACRJ_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRJ_SP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP6_MASK, AIPS_PACRJ_SP6(value)))
+#define AIPS_BWR_PACRJ_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP5 field. */
+#define AIPS_RD_PACRJ_TP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP5_MASK) >> AIPS_PACRJ_TP5_SHIFT)
+#define AIPS_BRD_PACRJ_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRJ_TP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP5_MASK, AIPS_PACRJ_TP5(value)))
+#define AIPS_BWR_PACRJ_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP5 field. */
+#define AIPS_RD_PACRJ_WP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP5_MASK) >> AIPS_PACRJ_WP5_SHIFT)
+#define AIPS_BRD_PACRJ_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRJ_WP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP5_MASK, AIPS_PACRJ_WP5(value)))
+#define AIPS_BWR_PACRJ_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP5 field. */
+#define AIPS_RD_PACRJ_SP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP5_MASK) >> AIPS_PACRJ_SP5_SHIFT)
+#define AIPS_BRD_PACRJ_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRJ_SP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP5_MASK, AIPS_PACRJ_SP5(value)))
+#define AIPS_BWR_PACRJ_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP4 field. */
+#define AIPS_RD_PACRJ_TP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP4_MASK) >> AIPS_PACRJ_TP4_SHIFT)
+#define AIPS_BRD_PACRJ_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRJ_TP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP4_MASK, AIPS_PACRJ_TP4(value)))
+#define AIPS_BWR_PACRJ_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP4 field. */
+#define AIPS_RD_PACRJ_WP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP4_MASK) >> AIPS_PACRJ_WP4_SHIFT)
+#define AIPS_BRD_PACRJ_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRJ_WP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP4_MASK, AIPS_PACRJ_WP4(value)))
+#define AIPS_BWR_PACRJ_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP4 field. */
+#define AIPS_RD_PACRJ_SP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP4_MASK) >> AIPS_PACRJ_SP4_SHIFT)
+#define AIPS_BRD_PACRJ_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRJ_SP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP4_MASK, AIPS_PACRJ_SP4(value)))
+#define AIPS_BWR_PACRJ_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP3 field. */
+#define AIPS_RD_PACRJ_TP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP3_MASK) >> AIPS_PACRJ_TP3_SHIFT)
+#define AIPS_BRD_PACRJ_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRJ_TP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP3_MASK, AIPS_PACRJ_TP3(value)))
+#define AIPS_BWR_PACRJ_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP3 field. */
+#define AIPS_RD_PACRJ_WP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP3_MASK) >> AIPS_PACRJ_WP3_SHIFT)
+#define AIPS_BRD_PACRJ_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRJ_WP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP3_MASK, AIPS_PACRJ_WP3(value)))
+#define AIPS_BWR_PACRJ_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP3 field. */
+#define AIPS_RD_PACRJ_SP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP3_MASK) >> AIPS_PACRJ_SP3_SHIFT)
+#define AIPS_BRD_PACRJ_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRJ_SP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP3_MASK, AIPS_PACRJ_SP3(value)))
+#define AIPS_BWR_PACRJ_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP2 field. */
+#define AIPS_RD_PACRJ_TP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP2_MASK) >> AIPS_PACRJ_TP2_SHIFT)
+#define AIPS_BRD_PACRJ_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRJ_TP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP2_MASK, AIPS_PACRJ_TP2(value)))
+#define AIPS_BWR_PACRJ_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP2 field. */
+#define AIPS_RD_PACRJ_WP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP2_MASK) >> AIPS_PACRJ_WP2_SHIFT)
+#define AIPS_BRD_PACRJ_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRJ_WP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP2_MASK, AIPS_PACRJ_WP2(value)))
+#define AIPS_BWR_PACRJ_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP2 field. */
+#define AIPS_RD_PACRJ_SP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP2_MASK) >> AIPS_PACRJ_SP2_SHIFT)
+#define AIPS_BRD_PACRJ_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRJ_SP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP2_MASK, AIPS_PACRJ_SP2(value)))
+#define AIPS_BWR_PACRJ_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP1 field. */
+#define AIPS_RD_PACRJ_TP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP1_MASK) >> AIPS_PACRJ_TP1_SHIFT)
+#define AIPS_BRD_PACRJ_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRJ_TP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP1_MASK, AIPS_PACRJ_TP1(value)))
+#define AIPS_BWR_PACRJ_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP1 field. */
+#define AIPS_RD_PACRJ_WP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP1_MASK) >> AIPS_PACRJ_WP1_SHIFT)
+#define AIPS_BRD_PACRJ_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRJ_WP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP1_MASK, AIPS_PACRJ_WP1(value)))
+#define AIPS_BWR_PACRJ_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP1 field. */
+#define AIPS_RD_PACRJ_SP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP1_MASK) >> AIPS_PACRJ_SP1_SHIFT)
+#define AIPS_BRD_PACRJ_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRJ_SP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP1_MASK, AIPS_PACRJ_SP1(value)))
+#define AIPS_BWR_PACRJ_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP0 field. */
+#define AIPS_RD_PACRJ_TP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP0_MASK) >> AIPS_PACRJ_TP0_SHIFT)
+#define AIPS_BRD_PACRJ_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRJ_TP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP0_MASK, AIPS_PACRJ_TP0(value)))
+#define AIPS_BWR_PACRJ_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP0 field. */
+#define AIPS_RD_PACRJ_WP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP0_MASK) >> AIPS_PACRJ_WP0_SHIFT)
+#define AIPS_BRD_PACRJ_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRJ_WP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP0_MASK, AIPS_PACRJ_WP0(value)))
+#define AIPS_BWR_PACRJ_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP0 field. */
+#define AIPS_RD_PACRJ_SP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP0_MASK) >> AIPS_PACRJ_SP0_SHIFT)
+#define AIPS_BRD_PACRJ_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRJ_SP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP0_MASK, AIPS_PACRJ_SP0(value)))
+#define AIPS_BWR_PACRJ_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRK - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRK - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRK register
+ */
+/*@{*/
+#define AIPS_RD_PACRK(base)      (AIPS_PACRK_REG(base))
+#define AIPS_WR_PACRK(base, value) (AIPS_PACRK_REG(base) = (value))
+#define AIPS_RMW_PACRK(base, mask, value) (AIPS_WR_PACRK(base, (AIPS_RD_PACRK(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) |  (value)))
+#define AIPS_CLR_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) & ~(value)))
+#define AIPS_TOG_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRK bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRK, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP7 field. */
+#define AIPS_RD_PACRK_TP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP7_MASK) >> AIPS_PACRK_TP7_SHIFT)
+#define AIPS_BRD_PACRK_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRK_TP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP7_MASK, AIPS_PACRK_TP7(value)))
+#define AIPS_BWR_PACRK_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP7 field. */
+#define AIPS_RD_PACRK_WP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP7_MASK) >> AIPS_PACRK_WP7_SHIFT)
+#define AIPS_BRD_PACRK_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRK_WP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP7_MASK, AIPS_PACRK_WP7(value)))
+#define AIPS_BWR_PACRK_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP7 field. */
+#define AIPS_RD_PACRK_SP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP7_MASK) >> AIPS_PACRK_SP7_SHIFT)
+#define AIPS_BRD_PACRK_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRK_SP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP7_MASK, AIPS_PACRK_SP7(value)))
+#define AIPS_BWR_PACRK_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP6 field. */
+#define AIPS_RD_PACRK_TP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP6_MASK) >> AIPS_PACRK_TP6_SHIFT)
+#define AIPS_BRD_PACRK_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRK_TP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP6_MASK, AIPS_PACRK_TP6(value)))
+#define AIPS_BWR_PACRK_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP6 field. */
+#define AIPS_RD_PACRK_WP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP6_MASK) >> AIPS_PACRK_WP6_SHIFT)
+#define AIPS_BRD_PACRK_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRK_WP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP6_MASK, AIPS_PACRK_WP6(value)))
+#define AIPS_BWR_PACRK_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP6 field. */
+#define AIPS_RD_PACRK_SP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP6_MASK) >> AIPS_PACRK_SP6_SHIFT)
+#define AIPS_BRD_PACRK_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRK_SP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP6_MASK, AIPS_PACRK_SP6(value)))
+#define AIPS_BWR_PACRK_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP5 field. */
+#define AIPS_RD_PACRK_TP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP5_MASK) >> AIPS_PACRK_TP5_SHIFT)
+#define AIPS_BRD_PACRK_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRK_TP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP5_MASK, AIPS_PACRK_TP5(value)))
+#define AIPS_BWR_PACRK_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP5 field. */
+#define AIPS_RD_PACRK_WP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP5_MASK) >> AIPS_PACRK_WP5_SHIFT)
+#define AIPS_BRD_PACRK_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRK_WP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP5_MASK, AIPS_PACRK_WP5(value)))
+#define AIPS_BWR_PACRK_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP5 field. */
+#define AIPS_RD_PACRK_SP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP5_MASK) >> AIPS_PACRK_SP5_SHIFT)
+#define AIPS_BRD_PACRK_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRK_SP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP5_MASK, AIPS_PACRK_SP5(value)))
+#define AIPS_BWR_PACRK_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP4 field. */
+#define AIPS_RD_PACRK_TP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP4_MASK) >> AIPS_PACRK_TP4_SHIFT)
+#define AIPS_BRD_PACRK_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRK_TP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP4_MASK, AIPS_PACRK_TP4(value)))
+#define AIPS_BWR_PACRK_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP4 field. */
+#define AIPS_RD_PACRK_WP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP4_MASK) >> AIPS_PACRK_WP4_SHIFT)
+#define AIPS_BRD_PACRK_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRK_WP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP4_MASK, AIPS_PACRK_WP4(value)))
+#define AIPS_BWR_PACRK_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP4 field. */
+#define AIPS_RD_PACRK_SP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP4_MASK) >> AIPS_PACRK_SP4_SHIFT)
+#define AIPS_BRD_PACRK_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRK_SP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP4_MASK, AIPS_PACRK_SP4(value)))
+#define AIPS_BWR_PACRK_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP3 field. */
+#define AIPS_RD_PACRK_TP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP3_MASK) >> AIPS_PACRK_TP3_SHIFT)
+#define AIPS_BRD_PACRK_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRK_TP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP3_MASK, AIPS_PACRK_TP3(value)))
+#define AIPS_BWR_PACRK_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP3 field. */
+#define AIPS_RD_PACRK_WP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP3_MASK) >> AIPS_PACRK_WP3_SHIFT)
+#define AIPS_BRD_PACRK_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRK_WP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP3_MASK, AIPS_PACRK_WP3(value)))
+#define AIPS_BWR_PACRK_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP3 field. */
+#define AIPS_RD_PACRK_SP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP3_MASK) >> AIPS_PACRK_SP3_SHIFT)
+#define AIPS_BRD_PACRK_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRK_SP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP3_MASK, AIPS_PACRK_SP3(value)))
+#define AIPS_BWR_PACRK_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP2 field. */
+#define AIPS_RD_PACRK_TP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP2_MASK) >> AIPS_PACRK_TP2_SHIFT)
+#define AIPS_BRD_PACRK_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRK_TP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP2_MASK, AIPS_PACRK_TP2(value)))
+#define AIPS_BWR_PACRK_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP2 field. */
+#define AIPS_RD_PACRK_WP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP2_MASK) >> AIPS_PACRK_WP2_SHIFT)
+#define AIPS_BRD_PACRK_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRK_WP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP2_MASK, AIPS_PACRK_WP2(value)))
+#define AIPS_BWR_PACRK_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP2 field. */
+#define AIPS_RD_PACRK_SP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP2_MASK) >> AIPS_PACRK_SP2_SHIFT)
+#define AIPS_BRD_PACRK_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRK_SP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP2_MASK, AIPS_PACRK_SP2(value)))
+#define AIPS_BWR_PACRK_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP1 field. */
+#define AIPS_RD_PACRK_TP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP1_MASK) >> AIPS_PACRK_TP1_SHIFT)
+#define AIPS_BRD_PACRK_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRK_TP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP1_MASK, AIPS_PACRK_TP1(value)))
+#define AIPS_BWR_PACRK_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP1 field. */
+#define AIPS_RD_PACRK_WP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP1_MASK) >> AIPS_PACRK_WP1_SHIFT)
+#define AIPS_BRD_PACRK_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRK_WP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP1_MASK, AIPS_PACRK_WP1(value)))
+#define AIPS_BWR_PACRK_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP1 field. */
+#define AIPS_RD_PACRK_SP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP1_MASK) >> AIPS_PACRK_SP1_SHIFT)
+#define AIPS_BRD_PACRK_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRK_SP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP1_MASK, AIPS_PACRK_SP1(value)))
+#define AIPS_BWR_PACRK_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP0 field. */
+#define AIPS_RD_PACRK_TP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP0_MASK) >> AIPS_PACRK_TP0_SHIFT)
+#define AIPS_BRD_PACRK_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRK_TP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP0_MASK, AIPS_PACRK_TP0(value)))
+#define AIPS_BWR_PACRK_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP0 field. */
+#define AIPS_RD_PACRK_WP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP0_MASK) >> AIPS_PACRK_WP0_SHIFT)
+#define AIPS_BRD_PACRK_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRK_WP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP0_MASK, AIPS_PACRK_WP0(value)))
+#define AIPS_BWR_PACRK_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP0 field. */
+#define AIPS_RD_PACRK_SP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP0_MASK) >> AIPS_PACRK_SP0_SHIFT)
+#define AIPS_BRD_PACRK_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRK_SP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP0_MASK, AIPS_PACRK_SP0(value)))
+#define AIPS_BWR_PACRK_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRL - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRL - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRL register
+ */
+/*@{*/
+#define AIPS_RD_PACRL(base)      (AIPS_PACRL_REG(base))
+#define AIPS_WR_PACRL(base, value) (AIPS_PACRL_REG(base) = (value))
+#define AIPS_RMW_PACRL(base, mask, value) (AIPS_WR_PACRL(base, (AIPS_RD_PACRL(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) |  (value)))
+#define AIPS_CLR_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) & ~(value)))
+#define AIPS_TOG_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRL bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRL, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP7 field. */
+#define AIPS_RD_PACRL_TP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP7_MASK) >> AIPS_PACRL_TP7_SHIFT)
+#define AIPS_BRD_PACRL_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRL_TP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP7_MASK, AIPS_PACRL_TP7(value)))
+#define AIPS_BWR_PACRL_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP7 field. */
+#define AIPS_RD_PACRL_WP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP7_MASK) >> AIPS_PACRL_WP7_SHIFT)
+#define AIPS_BRD_PACRL_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRL_WP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP7_MASK, AIPS_PACRL_WP7(value)))
+#define AIPS_BWR_PACRL_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP7 field. */
+#define AIPS_RD_PACRL_SP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP7_MASK) >> AIPS_PACRL_SP7_SHIFT)
+#define AIPS_BRD_PACRL_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRL_SP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP7_MASK, AIPS_PACRL_SP7(value)))
+#define AIPS_BWR_PACRL_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP6 field. */
+#define AIPS_RD_PACRL_TP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP6_MASK) >> AIPS_PACRL_TP6_SHIFT)
+#define AIPS_BRD_PACRL_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRL_TP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP6_MASK, AIPS_PACRL_TP6(value)))
+#define AIPS_BWR_PACRL_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP6 field. */
+#define AIPS_RD_PACRL_WP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP6_MASK) >> AIPS_PACRL_WP6_SHIFT)
+#define AIPS_BRD_PACRL_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRL_WP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP6_MASK, AIPS_PACRL_WP6(value)))
+#define AIPS_BWR_PACRL_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP6 field. */
+#define AIPS_RD_PACRL_SP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP6_MASK) >> AIPS_PACRL_SP6_SHIFT)
+#define AIPS_BRD_PACRL_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRL_SP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP6_MASK, AIPS_PACRL_SP6(value)))
+#define AIPS_BWR_PACRL_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP5 field. */
+#define AIPS_RD_PACRL_TP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP5_MASK) >> AIPS_PACRL_TP5_SHIFT)
+#define AIPS_BRD_PACRL_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRL_TP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP5_MASK, AIPS_PACRL_TP5(value)))
+#define AIPS_BWR_PACRL_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP5 field. */
+#define AIPS_RD_PACRL_WP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP5_MASK) >> AIPS_PACRL_WP5_SHIFT)
+#define AIPS_BRD_PACRL_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRL_WP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP5_MASK, AIPS_PACRL_WP5(value)))
+#define AIPS_BWR_PACRL_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP5 field. */
+#define AIPS_RD_PACRL_SP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP5_MASK) >> AIPS_PACRL_SP5_SHIFT)
+#define AIPS_BRD_PACRL_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRL_SP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP5_MASK, AIPS_PACRL_SP5(value)))
+#define AIPS_BWR_PACRL_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP4 field. */
+#define AIPS_RD_PACRL_TP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP4_MASK) >> AIPS_PACRL_TP4_SHIFT)
+#define AIPS_BRD_PACRL_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRL_TP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP4_MASK, AIPS_PACRL_TP4(value)))
+#define AIPS_BWR_PACRL_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP4 field. */
+#define AIPS_RD_PACRL_WP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP4_MASK) >> AIPS_PACRL_WP4_SHIFT)
+#define AIPS_BRD_PACRL_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRL_WP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP4_MASK, AIPS_PACRL_WP4(value)))
+#define AIPS_BWR_PACRL_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP4 field. */
+#define AIPS_RD_PACRL_SP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP4_MASK) >> AIPS_PACRL_SP4_SHIFT)
+#define AIPS_BRD_PACRL_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRL_SP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP4_MASK, AIPS_PACRL_SP4(value)))
+#define AIPS_BWR_PACRL_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP3 field. */
+#define AIPS_RD_PACRL_TP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP3_MASK) >> AIPS_PACRL_TP3_SHIFT)
+#define AIPS_BRD_PACRL_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRL_TP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP3_MASK, AIPS_PACRL_TP3(value)))
+#define AIPS_BWR_PACRL_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP3 field. */
+#define AIPS_RD_PACRL_WP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP3_MASK) >> AIPS_PACRL_WP3_SHIFT)
+#define AIPS_BRD_PACRL_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRL_WP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP3_MASK, AIPS_PACRL_WP3(value)))
+#define AIPS_BWR_PACRL_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP3 field. */
+#define AIPS_RD_PACRL_SP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP3_MASK) >> AIPS_PACRL_SP3_SHIFT)
+#define AIPS_BRD_PACRL_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRL_SP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP3_MASK, AIPS_PACRL_SP3(value)))
+#define AIPS_BWR_PACRL_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP2 field. */
+#define AIPS_RD_PACRL_TP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP2_MASK) >> AIPS_PACRL_TP2_SHIFT)
+#define AIPS_BRD_PACRL_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRL_TP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP2_MASK, AIPS_PACRL_TP2(value)))
+#define AIPS_BWR_PACRL_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP2 field. */
+#define AIPS_RD_PACRL_WP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP2_MASK) >> AIPS_PACRL_WP2_SHIFT)
+#define AIPS_BRD_PACRL_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRL_WP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP2_MASK, AIPS_PACRL_WP2(value)))
+#define AIPS_BWR_PACRL_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP2 field. */
+#define AIPS_RD_PACRL_SP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP2_MASK) >> AIPS_PACRL_SP2_SHIFT)
+#define AIPS_BRD_PACRL_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRL_SP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP2_MASK, AIPS_PACRL_SP2(value)))
+#define AIPS_BWR_PACRL_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP1 field. */
+#define AIPS_RD_PACRL_TP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP1_MASK) >> AIPS_PACRL_TP1_SHIFT)
+#define AIPS_BRD_PACRL_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRL_TP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP1_MASK, AIPS_PACRL_TP1(value)))
+#define AIPS_BWR_PACRL_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP1 field. */
+#define AIPS_RD_PACRL_WP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP1_MASK) >> AIPS_PACRL_WP1_SHIFT)
+#define AIPS_BRD_PACRL_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRL_WP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP1_MASK, AIPS_PACRL_WP1(value)))
+#define AIPS_BWR_PACRL_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP1 field. */
+#define AIPS_RD_PACRL_SP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP1_MASK) >> AIPS_PACRL_SP1_SHIFT)
+#define AIPS_BRD_PACRL_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRL_SP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP1_MASK, AIPS_PACRL_SP1(value)))
+#define AIPS_BWR_PACRL_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP0 field. */
+#define AIPS_RD_PACRL_TP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP0_MASK) >> AIPS_PACRL_TP0_SHIFT)
+#define AIPS_BRD_PACRL_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRL_TP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP0_MASK, AIPS_PACRL_TP0(value)))
+#define AIPS_BWR_PACRL_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP0 field. */
+#define AIPS_RD_PACRL_WP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP0_MASK) >> AIPS_PACRL_WP0_SHIFT)
+#define AIPS_BRD_PACRL_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRL_WP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP0_MASK, AIPS_PACRL_WP0(value)))
+#define AIPS_BWR_PACRL_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP0 field. */
+#define AIPS_RD_PACRL_SP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP0_MASK) >> AIPS_PACRL_SP0_SHIFT)
+#define AIPS_BRD_PACRL_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRL_SP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP0_MASK, AIPS_PACRL_SP0(value)))
+#define AIPS_BWR_PACRL_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRM - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRM - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRM register
+ */
+/*@{*/
+#define AIPS_RD_PACRM(base)      (AIPS_PACRM_REG(base))
+#define AIPS_WR_PACRM(base, value) (AIPS_PACRM_REG(base) = (value))
+#define AIPS_RMW_PACRM(base, mask, value) (AIPS_WR_PACRM(base, (AIPS_RD_PACRM(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) |  (value)))
+#define AIPS_CLR_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) & ~(value)))
+#define AIPS_TOG_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRM bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRM, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP7 field. */
+#define AIPS_RD_PACRM_TP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP7_MASK) >> AIPS_PACRM_TP7_SHIFT)
+#define AIPS_BRD_PACRM_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRM_TP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP7_MASK, AIPS_PACRM_TP7(value)))
+#define AIPS_BWR_PACRM_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP7 field. */
+#define AIPS_RD_PACRM_WP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP7_MASK) >> AIPS_PACRM_WP7_SHIFT)
+#define AIPS_BRD_PACRM_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRM_WP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP7_MASK, AIPS_PACRM_WP7(value)))
+#define AIPS_BWR_PACRM_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP7 field. */
+#define AIPS_RD_PACRM_SP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP7_MASK) >> AIPS_PACRM_SP7_SHIFT)
+#define AIPS_BRD_PACRM_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRM_SP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP7_MASK, AIPS_PACRM_SP7(value)))
+#define AIPS_BWR_PACRM_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP6 field. */
+#define AIPS_RD_PACRM_TP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP6_MASK) >> AIPS_PACRM_TP6_SHIFT)
+#define AIPS_BRD_PACRM_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRM_TP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP6_MASK, AIPS_PACRM_TP6(value)))
+#define AIPS_BWR_PACRM_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP6 field. */
+#define AIPS_RD_PACRM_WP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP6_MASK) >> AIPS_PACRM_WP6_SHIFT)
+#define AIPS_BRD_PACRM_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRM_WP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP6_MASK, AIPS_PACRM_WP6(value)))
+#define AIPS_BWR_PACRM_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP6 field. */
+#define AIPS_RD_PACRM_SP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP6_MASK) >> AIPS_PACRM_SP6_SHIFT)
+#define AIPS_BRD_PACRM_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRM_SP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP6_MASK, AIPS_PACRM_SP6(value)))
+#define AIPS_BWR_PACRM_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP5 field. */
+#define AIPS_RD_PACRM_TP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP5_MASK) >> AIPS_PACRM_TP5_SHIFT)
+#define AIPS_BRD_PACRM_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRM_TP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP5_MASK, AIPS_PACRM_TP5(value)))
+#define AIPS_BWR_PACRM_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP5 field. */
+#define AIPS_RD_PACRM_WP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP5_MASK) >> AIPS_PACRM_WP5_SHIFT)
+#define AIPS_BRD_PACRM_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRM_WP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP5_MASK, AIPS_PACRM_WP5(value)))
+#define AIPS_BWR_PACRM_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP5 field. */
+#define AIPS_RD_PACRM_SP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP5_MASK) >> AIPS_PACRM_SP5_SHIFT)
+#define AIPS_BRD_PACRM_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRM_SP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP5_MASK, AIPS_PACRM_SP5(value)))
+#define AIPS_BWR_PACRM_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP4 field. */
+#define AIPS_RD_PACRM_TP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP4_MASK) >> AIPS_PACRM_TP4_SHIFT)
+#define AIPS_BRD_PACRM_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRM_TP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP4_MASK, AIPS_PACRM_TP4(value)))
+#define AIPS_BWR_PACRM_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP4 field. */
+#define AIPS_RD_PACRM_WP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP4_MASK) >> AIPS_PACRM_WP4_SHIFT)
+#define AIPS_BRD_PACRM_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRM_WP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP4_MASK, AIPS_PACRM_WP4(value)))
+#define AIPS_BWR_PACRM_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP4 field. */
+#define AIPS_RD_PACRM_SP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP4_MASK) >> AIPS_PACRM_SP4_SHIFT)
+#define AIPS_BRD_PACRM_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRM_SP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP4_MASK, AIPS_PACRM_SP4(value)))
+#define AIPS_BWR_PACRM_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP3 field. */
+#define AIPS_RD_PACRM_TP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP3_MASK) >> AIPS_PACRM_TP3_SHIFT)
+#define AIPS_BRD_PACRM_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRM_TP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP3_MASK, AIPS_PACRM_TP3(value)))
+#define AIPS_BWR_PACRM_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP3 field. */
+#define AIPS_RD_PACRM_WP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP3_MASK) >> AIPS_PACRM_WP3_SHIFT)
+#define AIPS_BRD_PACRM_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRM_WP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP3_MASK, AIPS_PACRM_WP3(value)))
+#define AIPS_BWR_PACRM_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP3 field. */
+#define AIPS_RD_PACRM_SP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP3_MASK) >> AIPS_PACRM_SP3_SHIFT)
+#define AIPS_BRD_PACRM_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRM_SP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP3_MASK, AIPS_PACRM_SP3(value)))
+#define AIPS_BWR_PACRM_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP2 field. */
+#define AIPS_RD_PACRM_TP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP2_MASK) >> AIPS_PACRM_TP2_SHIFT)
+#define AIPS_BRD_PACRM_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRM_TP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP2_MASK, AIPS_PACRM_TP2(value)))
+#define AIPS_BWR_PACRM_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP2 field. */
+#define AIPS_RD_PACRM_WP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP2_MASK) >> AIPS_PACRM_WP2_SHIFT)
+#define AIPS_BRD_PACRM_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRM_WP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP2_MASK, AIPS_PACRM_WP2(value)))
+#define AIPS_BWR_PACRM_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP2 field. */
+#define AIPS_RD_PACRM_SP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP2_MASK) >> AIPS_PACRM_SP2_SHIFT)
+#define AIPS_BRD_PACRM_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRM_SP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP2_MASK, AIPS_PACRM_SP2(value)))
+#define AIPS_BWR_PACRM_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP1 field. */
+#define AIPS_RD_PACRM_TP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP1_MASK) >> AIPS_PACRM_TP1_SHIFT)
+#define AIPS_BRD_PACRM_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRM_TP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP1_MASK, AIPS_PACRM_TP1(value)))
+#define AIPS_BWR_PACRM_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP1 field. */
+#define AIPS_RD_PACRM_WP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP1_MASK) >> AIPS_PACRM_WP1_SHIFT)
+#define AIPS_BRD_PACRM_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRM_WP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP1_MASK, AIPS_PACRM_WP1(value)))
+#define AIPS_BWR_PACRM_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP1 field. */
+#define AIPS_RD_PACRM_SP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP1_MASK) >> AIPS_PACRM_SP1_SHIFT)
+#define AIPS_BRD_PACRM_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRM_SP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP1_MASK, AIPS_PACRM_SP1(value)))
+#define AIPS_BWR_PACRM_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP0 field. */
+#define AIPS_RD_PACRM_TP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP0_MASK) >> AIPS_PACRM_TP0_SHIFT)
+#define AIPS_BRD_PACRM_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRM_TP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP0_MASK, AIPS_PACRM_TP0(value)))
+#define AIPS_BWR_PACRM_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP0 field. */
+#define AIPS_RD_PACRM_WP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP0_MASK) >> AIPS_PACRM_WP0_SHIFT)
+#define AIPS_BRD_PACRM_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRM_WP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP0_MASK, AIPS_PACRM_WP0(value)))
+#define AIPS_BWR_PACRM_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP0 field. */
+#define AIPS_RD_PACRM_SP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP0_MASK) >> AIPS_PACRM_SP0_SHIFT)
+#define AIPS_BRD_PACRM_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRM_SP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP0_MASK, AIPS_PACRM_SP0(value)))
+#define AIPS_BWR_PACRM_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRN - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRN - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRN register
+ */
+/*@{*/
+#define AIPS_RD_PACRN(base)      (AIPS_PACRN_REG(base))
+#define AIPS_WR_PACRN(base, value) (AIPS_PACRN_REG(base) = (value))
+#define AIPS_RMW_PACRN(base, mask, value) (AIPS_WR_PACRN(base, (AIPS_RD_PACRN(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) |  (value)))
+#define AIPS_CLR_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) & ~(value)))
+#define AIPS_TOG_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRN bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRN, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP7 field. */
+#define AIPS_RD_PACRN_TP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP7_MASK) >> AIPS_PACRN_TP7_SHIFT)
+#define AIPS_BRD_PACRN_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRN_TP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP7_MASK, AIPS_PACRN_TP7(value)))
+#define AIPS_BWR_PACRN_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP7 field. */
+#define AIPS_RD_PACRN_WP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP7_MASK) >> AIPS_PACRN_WP7_SHIFT)
+#define AIPS_BRD_PACRN_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRN_WP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP7_MASK, AIPS_PACRN_WP7(value)))
+#define AIPS_BWR_PACRN_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP7 field. */
+#define AIPS_RD_PACRN_SP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP7_MASK) >> AIPS_PACRN_SP7_SHIFT)
+#define AIPS_BRD_PACRN_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRN_SP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP7_MASK, AIPS_PACRN_SP7(value)))
+#define AIPS_BWR_PACRN_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP6 field. */
+#define AIPS_RD_PACRN_TP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP6_MASK) >> AIPS_PACRN_TP6_SHIFT)
+#define AIPS_BRD_PACRN_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRN_TP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP6_MASK, AIPS_PACRN_TP6(value)))
+#define AIPS_BWR_PACRN_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP6 field. */
+#define AIPS_RD_PACRN_WP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP6_MASK) >> AIPS_PACRN_WP6_SHIFT)
+#define AIPS_BRD_PACRN_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRN_WP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP6_MASK, AIPS_PACRN_WP6(value)))
+#define AIPS_BWR_PACRN_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP6 field. */
+#define AIPS_RD_PACRN_SP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP6_MASK) >> AIPS_PACRN_SP6_SHIFT)
+#define AIPS_BRD_PACRN_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRN_SP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP6_MASK, AIPS_PACRN_SP6(value)))
+#define AIPS_BWR_PACRN_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP5 field. */
+#define AIPS_RD_PACRN_TP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP5_MASK) >> AIPS_PACRN_TP5_SHIFT)
+#define AIPS_BRD_PACRN_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRN_TP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP5_MASK, AIPS_PACRN_TP5(value)))
+#define AIPS_BWR_PACRN_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP5 field. */
+#define AIPS_RD_PACRN_WP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP5_MASK) >> AIPS_PACRN_WP5_SHIFT)
+#define AIPS_BRD_PACRN_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRN_WP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP5_MASK, AIPS_PACRN_WP5(value)))
+#define AIPS_BWR_PACRN_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP5 field. */
+#define AIPS_RD_PACRN_SP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP5_MASK) >> AIPS_PACRN_SP5_SHIFT)
+#define AIPS_BRD_PACRN_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRN_SP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP5_MASK, AIPS_PACRN_SP5(value)))
+#define AIPS_BWR_PACRN_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP4 field. */
+#define AIPS_RD_PACRN_TP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP4_MASK) >> AIPS_PACRN_TP4_SHIFT)
+#define AIPS_BRD_PACRN_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRN_TP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP4_MASK, AIPS_PACRN_TP4(value)))
+#define AIPS_BWR_PACRN_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP4 field. */
+#define AIPS_RD_PACRN_WP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP4_MASK) >> AIPS_PACRN_WP4_SHIFT)
+#define AIPS_BRD_PACRN_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRN_WP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP4_MASK, AIPS_PACRN_WP4(value)))
+#define AIPS_BWR_PACRN_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP4 field. */
+#define AIPS_RD_PACRN_SP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP4_MASK) >> AIPS_PACRN_SP4_SHIFT)
+#define AIPS_BRD_PACRN_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRN_SP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP4_MASK, AIPS_PACRN_SP4(value)))
+#define AIPS_BWR_PACRN_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP3 field. */
+#define AIPS_RD_PACRN_TP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP3_MASK) >> AIPS_PACRN_TP3_SHIFT)
+#define AIPS_BRD_PACRN_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRN_TP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP3_MASK, AIPS_PACRN_TP3(value)))
+#define AIPS_BWR_PACRN_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP3 field. */
+#define AIPS_RD_PACRN_WP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP3_MASK) >> AIPS_PACRN_WP3_SHIFT)
+#define AIPS_BRD_PACRN_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRN_WP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP3_MASK, AIPS_PACRN_WP3(value)))
+#define AIPS_BWR_PACRN_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP3 field. */
+#define AIPS_RD_PACRN_SP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP3_MASK) >> AIPS_PACRN_SP3_SHIFT)
+#define AIPS_BRD_PACRN_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRN_SP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP3_MASK, AIPS_PACRN_SP3(value)))
+#define AIPS_BWR_PACRN_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP2 field. */
+#define AIPS_RD_PACRN_TP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP2_MASK) >> AIPS_PACRN_TP2_SHIFT)
+#define AIPS_BRD_PACRN_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRN_TP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP2_MASK, AIPS_PACRN_TP2(value)))
+#define AIPS_BWR_PACRN_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP2 field. */
+#define AIPS_RD_PACRN_WP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP2_MASK) >> AIPS_PACRN_WP2_SHIFT)
+#define AIPS_BRD_PACRN_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRN_WP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP2_MASK, AIPS_PACRN_WP2(value)))
+#define AIPS_BWR_PACRN_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP2 field. */
+#define AIPS_RD_PACRN_SP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP2_MASK) >> AIPS_PACRN_SP2_SHIFT)
+#define AIPS_BRD_PACRN_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRN_SP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP2_MASK, AIPS_PACRN_SP2(value)))
+#define AIPS_BWR_PACRN_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP1 field. */
+#define AIPS_RD_PACRN_TP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP1_MASK) >> AIPS_PACRN_TP1_SHIFT)
+#define AIPS_BRD_PACRN_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRN_TP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP1_MASK, AIPS_PACRN_TP1(value)))
+#define AIPS_BWR_PACRN_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP1 field. */
+#define AIPS_RD_PACRN_WP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP1_MASK) >> AIPS_PACRN_WP1_SHIFT)
+#define AIPS_BRD_PACRN_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRN_WP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP1_MASK, AIPS_PACRN_WP1(value)))
+#define AIPS_BWR_PACRN_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP1 field. */
+#define AIPS_RD_PACRN_SP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP1_MASK) >> AIPS_PACRN_SP1_SHIFT)
+#define AIPS_BRD_PACRN_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRN_SP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP1_MASK, AIPS_PACRN_SP1(value)))
+#define AIPS_BWR_PACRN_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP0 field. */
+#define AIPS_RD_PACRN_TP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP0_MASK) >> AIPS_PACRN_TP0_SHIFT)
+#define AIPS_BRD_PACRN_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRN_TP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP0_MASK, AIPS_PACRN_TP0(value)))
+#define AIPS_BWR_PACRN_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP0 field. */
+#define AIPS_RD_PACRN_WP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP0_MASK) >> AIPS_PACRN_WP0_SHIFT)
+#define AIPS_BRD_PACRN_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRN_WP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP0_MASK, AIPS_PACRN_WP0(value)))
+#define AIPS_BWR_PACRN_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP0 field. */
+#define AIPS_RD_PACRN_SP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP0_MASK) >> AIPS_PACRN_SP0_SHIFT)
+#define AIPS_BRD_PACRN_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRN_SP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP0_MASK, AIPS_PACRN_SP0(value)))
+#define AIPS_BWR_PACRN_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRO - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRO - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRO register
+ */
+/*@{*/
+#define AIPS_RD_PACRO(base)      (AIPS_PACRO_REG(base))
+#define AIPS_WR_PACRO(base, value) (AIPS_PACRO_REG(base) = (value))
+#define AIPS_RMW_PACRO(base, mask, value) (AIPS_WR_PACRO(base, (AIPS_RD_PACRO(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) |  (value)))
+#define AIPS_CLR_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) & ~(value)))
+#define AIPS_TOG_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRO bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRO, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP7 field. */
+#define AIPS_RD_PACRO_TP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP7_MASK) >> AIPS_PACRO_TP7_SHIFT)
+#define AIPS_BRD_PACRO_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRO_TP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP7_MASK, AIPS_PACRO_TP7(value)))
+#define AIPS_BWR_PACRO_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP7 field. */
+#define AIPS_RD_PACRO_WP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP7_MASK) >> AIPS_PACRO_WP7_SHIFT)
+#define AIPS_BRD_PACRO_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRO_WP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP7_MASK, AIPS_PACRO_WP7(value)))
+#define AIPS_BWR_PACRO_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP7 field. */
+#define AIPS_RD_PACRO_SP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP7_MASK) >> AIPS_PACRO_SP7_SHIFT)
+#define AIPS_BRD_PACRO_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRO_SP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP7_MASK, AIPS_PACRO_SP7(value)))
+#define AIPS_BWR_PACRO_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP6 field. */
+#define AIPS_RD_PACRO_TP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP6_MASK) >> AIPS_PACRO_TP6_SHIFT)
+#define AIPS_BRD_PACRO_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRO_TP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP6_MASK, AIPS_PACRO_TP6(value)))
+#define AIPS_BWR_PACRO_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP6 field. */
+#define AIPS_RD_PACRO_WP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP6_MASK) >> AIPS_PACRO_WP6_SHIFT)
+#define AIPS_BRD_PACRO_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRO_WP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP6_MASK, AIPS_PACRO_WP6(value)))
+#define AIPS_BWR_PACRO_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP6 field. */
+#define AIPS_RD_PACRO_SP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP6_MASK) >> AIPS_PACRO_SP6_SHIFT)
+#define AIPS_BRD_PACRO_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRO_SP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP6_MASK, AIPS_PACRO_SP6(value)))
+#define AIPS_BWR_PACRO_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP5 field. */
+#define AIPS_RD_PACRO_TP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP5_MASK) >> AIPS_PACRO_TP5_SHIFT)
+#define AIPS_BRD_PACRO_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRO_TP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP5_MASK, AIPS_PACRO_TP5(value)))
+#define AIPS_BWR_PACRO_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP5 field. */
+#define AIPS_RD_PACRO_WP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP5_MASK) >> AIPS_PACRO_WP5_SHIFT)
+#define AIPS_BRD_PACRO_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRO_WP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP5_MASK, AIPS_PACRO_WP5(value)))
+#define AIPS_BWR_PACRO_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP5 field. */
+#define AIPS_RD_PACRO_SP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP5_MASK) >> AIPS_PACRO_SP5_SHIFT)
+#define AIPS_BRD_PACRO_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRO_SP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP5_MASK, AIPS_PACRO_SP5(value)))
+#define AIPS_BWR_PACRO_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP4 field. */
+#define AIPS_RD_PACRO_TP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP4_MASK) >> AIPS_PACRO_TP4_SHIFT)
+#define AIPS_BRD_PACRO_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRO_TP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP4_MASK, AIPS_PACRO_TP4(value)))
+#define AIPS_BWR_PACRO_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP4 field. */
+#define AIPS_RD_PACRO_WP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP4_MASK) >> AIPS_PACRO_WP4_SHIFT)
+#define AIPS_BRD_PACRO_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRO_WP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP4_MASK, AIPS_PACRO_WP4(value)))
+#define AIPS_BWR_PACRO_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP4 field. */
+#define AIPS_RD_PACRO_SP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP4_MASK) >> AIPS_PACRO_SP4_SHIFT)
+#define AIPS_BRD_PACRO_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRO_SP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP4_MASK, AIPS_PACRO_SP4(value)))
+#define AIPS_BWR_PACRO_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP3 field. */
+#define AIPS_RD_PACRO_TP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP3_MASK) >> AIPS_PACRO_TP3_SHIFT)
+#define AIPS_BRD_PACRO_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRO_TP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP3_MASK, AIPS_PACRO_TP3(value)))
+#define AIPS_BWR_PACRO_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP3 field. */
+#define AIPS_RD_PACRO_WP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP3_MASK) >> AIPS_PACRO_WP3_SHIFT)
+#define AIPS_BRD_PACRO_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRO_WP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP3_MASK, AIPS_PACRO_WP3(value)))
+#define AIPS_BWR_PACRO_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP3 field. */
+#define AIPS_RD_PACRO_SP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP3_MASK) >> AIPS_PACRO_SP3_SHIFT)
+#define AIPS_BRD_PACRO_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRO_SP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP3_MASK, AIPS_PACRO_SP3(value)))
+#define AIPS_BWR_PACRO_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP2 field. */
+#define AIPS_RD_PACRO_TP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP2_MASK) >> AIPS_PACRO_TP2_SHIFT)
+#define AIPS_BRD_PACRO_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRO_TP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP2_MASK, AIPS_PACRO_TP2(value)))
+#define AIPS_BWR_PACRO_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP2 field. */
+#define AIPS_RD_PACRO_WP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP2_MASK) >> AIPS_PACRO_WP2_SHIFT)
+#define AIPS_BRD_PACRO_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRO_WP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP2_MASK, AIPS_PACRO_WP2(value)))
+#define AIPS_BWR_PACRO_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP2 field. */
+#define AIPS_RD_PACRO_SP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP2_MASK) >> AIPS_PACRO_SP2_SHIFT)
+#define AIPS_BRD_PACRO_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRO_SP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP2_MASK, AIPS_PACRO_SP2(value)))
+#define AIPS_BWR_PACRO_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP1 field. */
+#define AIPS_RD_PACRO_TP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP1_MASK) >> AIPS_PACRO_TP1_SHIFT)
+#define AIPS_BRD_PACRO_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRO_TP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP1_MASK, AIPS_PACRO_TP1(value)))
+#define AIPS_BWR_PACRO_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP1 field. */
+#define AIPS_RD_PACRO_WP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP1_MASK) >> AIPS_PACRO_WP1_SHIFT)
+#define AIPS_BRD_PACRO_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRO_WP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP1_MASK, AIPS_PACRO_WP1(value)))
+#define AIPS_BWR_PACRO_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP1 field. */
+#define AIPS_RD_PACRO_SP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP1_MASK) >> AIPS_PACRO_SP1_SHIFT)
+#define AIPS_BRD_PACRO_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRO_SP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP1_MASK, AIPS_PACRO_SP1(value)))
+#define AIPS_BWR_PACRO_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP0 field. */
+#define AIPS_RD_PACRO_TP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP0_MASK) >> AIPS_PACRO_TP0_SHIFT)
+#define AIPS_BRD_PACRO_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRO_TP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP0_MASK, AIPS_PACRO_TP0(value)))
+#define AIPS_BWR_PACRO_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP0 field. */
+#define AIPS_RD_PACRO_WP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP0_MASK) >> AIPS_PACRO_WP0_SHIFT)
+#define AIPS_BRD_PACRO_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRO_WP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP0_MASK, AIPS_PACRO_WP0(value)))
+#define AIPS_BWR_PACRO_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP0 field. */
+#define AIPS_RD_PACRO_SP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP0_MASK) >> AIPS_PACRO_SP0_SHIFT)
+#define AIPS_BRD_PACRO_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRO_SP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP0_MASK, AIPS_PACRO_SP0(value)))
+#define AIPS_BWR_PACRO_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRP - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRP - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRP register
+ */
+/*@{*/
+#define AIPS_RD_PACRP(base)      (AIPS_PACRP_REG(base))
+#define AIPS_WR_PACRP(base, value) (AIPS_PACRP_REG(base) = (value))
+#define AIPS_RMW_PACRP(base, mask, value) (AIPS_WR_PACRP(base, (AIPS_RD_PACRP(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) |  (value)))
+#define AIPS_CLR_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) & ~(value)))
+#define AIPS_TOG_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRP bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRP, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP7 field. */
+#define AIPS_RD_PACRP_TP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP7_MASK) >> AIPS_PACRP_TP7_SHIFT)
+#define AIPS_BRD_PACRP_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRP_TP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP7_MASK, AIPS_PACRP_TP7(value)))
+#define AIPS_BWR_PACRP_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP7 field. */
+#define AIPS_RD_PACRP_WP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP7_MASK) >> AIPS_PACRP_WP7_SHIFT)
+#define AIPS_BRD_PACRP_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRP_WP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP7_MASK, AIPS_PACRP_WP7(value)))
+#define AIPS_BWR_PACRP_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP7 field. */
+#define AIPS_RD_PACRP_SP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP7_MASK) >> AIPS_PACRP_SP7_SHIFT)
+#define AIPS_BRD_PACRP_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRP_SP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP7_MASK, AIPS_PACRP_SP7(value)))
+#define AIPS_BWR_PACRP_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP6 field. */
+#define AIPS_RD_PACRP_TP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP6_MASK) >> AIPS_PACRP_TP6_SHIFT)
+#define AIPS_BRD_PACRP_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRP_TP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP6_MASK, AIPS_PACRP_TP6(value)))
+#define AIPS_BWR_PACRP_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP6 field. */
+#define AIPS_RD_PACRP_WP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP6_MASK) >> AIPS_PACRP_WP6_SHIFT)
+#define AIPS_BRD_PACRP_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRP_WP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP6_MASK, AIPS_PACRP_WP6(value)))
+#define AIPS_BWR_PACRP_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP6 field. */
+#define AIPS_RD_PACRP_SP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP6_MASK) >> AIPS_PACRP_SP6_SHIFT)
+#define AIPS_BRD_PACRP_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRP_SP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP6_MASK, AIPS_PACRP_SP6(value)))
+#define AIPS_BWR_PACRP_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP5 field. */
+#define AIPS_RD_PACRP_TP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP5_MASK) >> AIPS_PACRP_TP5_SHIFT)
+#define AIPS_BRD_PACRP_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRP_TP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP5_MASK, AIPS_PACRP_TP5(value)))
+#define AIPS_BWR_PACRP_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP5 field. */
+#define AIPS_RD_PACRP_WP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP5_MASK) >> AIPS_PACRP_WP5_SHIFT)
+#define AIPS_BRD_PACRP_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRP_WP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP5_MASK, AIPS_PACRP_WP5(value)))
+#define AIPS_BWR_PACRP_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP5 field. */
+#define AIPS_RD_PACRP_SP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP5_MASK) >> AIPS_PACRP_SP5_SHIFT)
+#define AIPS_BRD_PACRP_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRP_SP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP5_MASK, AIPS_PACRP_SP5(value)))
+#define AIPS_BWR_PACRP_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP4 field. */
+#define AIPS_RD_PACRP_TP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP4_MASK) >> AIPS_PACRP_TP4_SHIFT)
+#define AIPS_BRD_PACRP_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRP_TP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP4_MASK, AIPS_PACRP_TP4(value)))
+#define AIPS_BWR_PACRP_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP4 field. */
+#define AIPS_RD_PACRP_WP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP4_MASK) >> AIPS_PACRP_WP4_SHIFT)
+#define AIPS_BRD_PACRP_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRP_WP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP4_MASK, AIPS_PACRP_WP4(value)))
+#define AIPS_BWR_PACRP_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP4 field. */
+#define AIPS_RD_PACRP_SP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP4_MASK) >> AIPS_PACRP_SP4_SHIFT)
+#define AIPS_BRD_PACRP_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRP_SP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP4_MASK, AIPS_PACRP_SP4(value)))
+#define AIPS_BWR_PACRP_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP3 field. */
+#define AIPS_RD_PACRP_TP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP3_MASK) >> AIPS_PACRP_TP3_SHIFT)
+#define AIPS_BRD_PACRP_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRP_TP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP3_MASK, AIPS_PACRP_TP3(value)))
+#define AIPS_BWR_PACRP_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP3 field. */
+#define AIPS_RD_PACRP_WP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP3_MASK) >> AIPS_PACRP_WP3_SHIFT)
+#define AIPS_BRD_PACRP_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRP_WP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP3_MASK, AIPS_PACRP_WP3(value)))
+#define AIPS_BWR_PACRP_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP3 field. */
+#define AIPS_RD_PACRP_SP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP3_MASK) >> AIPS_PACRP_SP3_SHIFT)
+#define AIPS_BRD_PACRP_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRP_SP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP3_MASK, AIPS_PACRP_SP3(value)))
+#define AIPS_BWR_PACRP_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP2 field. */
+#define AIPS_RD_PACRP_TP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP2_MASK) >> AIPS_PACRP_TP2_SHIFT)
+#define AIPS_BRD_PACRP_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRP_TP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP2_MASK, AIPS_PACRP_TP2(value)))
+#define AIPS_BWR_PACRP_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP2 field. */
+#define AIPS_RD_PACRP_WP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP2_MASK) >> AIPS_PACRP_WP2_SHIFT)
+#define AIPS_BRD_PACRP_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRP_WP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP2_MASK, AIPS_PACRP_WP2(value)))
+#define AIPS_BWR_PACRP_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP2 field. */
+#define AIPS_RD_PACRP_SP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP2_MASK) >> AIPS_PACRP_SP2_SHIFT)
+#define AIPS_BRD_PACRP_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRP_SP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP2_MASK, AIPS_PACRP_SP2(value)))
+#define AIPS_BWR_PACRP_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP1 field. */
+#define AIPS_RD_PACRP_TP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP1_MASK) >> AIPS_PACRP_TP1_SHIFT)
+#define AIPS_BRD_PACRP_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRP_TP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP1_MASK, AIPS_PACRP_TP1(value)))
+#define AIPS_BWR_PACRP_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP1 field. */
+#define AIPS_RD_PACRP_WP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP1_MASK) >> AIPS_PACRP_WP1_SHIFT)
+#define AIPS_BRD_PACRP_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRP_WP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP1_MASK, AIPS_PACRP_WP1(value)))
+#define AIPS_BWR_PACRP_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP1 field. */
+#define AIPS_RD_PACRP_SP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP1_MASK) >> AIPS_PACRP_SP1_SHIFT)
+#define AIPS_BRD_PACRP_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRP_SP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP1_MASK, AIPS_PACRP_SP1(value)))
+#define AIPS_BWR_PACRP_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP0 field. */
+#define AIPS_RD_PACRP_TP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP0_MASK) >> AIPS_PACRP_TP0_SHIFT)
+#define AIPS_BRD_PACRP_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRP_TP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP0_MASK, AIPS_PACRP_TP0(value)))
+#define AIPS_BWR_PACRP_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP0 field. */
+#define AIPS_RD_PACRP_WP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP0_MASK) >> AIPS_PACRP_WP0_SHIFT)
+#define AIPS_BRD_PACRP_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRP_WP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP0_MASK, AIPS_PACRP_WP0(value)))
+#define AIPS_BWR_PACRP_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP0 field. */
+#define AIPS_RD_PACRP_SP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP0_MASK) >> AIPS_PACRP_SP0_SHIFT)
+#define AIPS_BRD_PACRP_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRP_SP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP0_MASK, AIPS_PACRP_SP0(value)))
+#define AIPS_BWR_PACRP_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRU - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRU - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44000000U
+ *
+ * PACRU defines the access levels for the two global spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRU register
+ */
+/*@{*/
+#define AIPS_RD_PACRU(base)      (AIPS_PACRU_REG(base))
+#define AIPS_WR_PACRU(base, value) (AIPS_PACRU_REG(base) = (value))
+#define AIPS_RMW_PACRU(base, mask, value) (AIPS_WR_PACRU(base, (AIPS_RD_PACRU(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) |  (value)))
+#define AIPS_CLR_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) & ~(value)))
+#define AIPS_TOG_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRU bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRU, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_TP1 field. */
+#define AIPS_RD_PACRU_TP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_TP1_MASK) >> AIPS_PACRU_TP1_SHIFT)
+#define AIPS_BRD_PACRU_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRU_TP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_TP1_MASK, AIPS_PACRU_TP1(value)))
+#define AIPS_BWR_PACRU_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_WP1 field. */
+#define AIPS_RD_PACRU_WP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_WP1_MASK) >> AIPS_PACRU_WP1_SHIFT)
+#define AIPS_BRD_PACRU_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRU_WP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_WP1_MASK, AIPS_PACRU_WP1(value)))
+#define AIPS_BWR_PACRU_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_SP1 field. */
+#define AIPS_RD_PACRU_SP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_SP1_MASK) >> AIPS_PACRU_SP1_SHIFT)
+#define AIPS_BRD_PACRU_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRU_SP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_SP1_MASK, AIPS_PACRU_SP1(value)))
+#define AIPS_BWR_PACRU_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_TP0 field. */
+#define AIPS_RD_PACRU_TP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_TP0_MASK) >> AIPS_PACRU_TP0_SHIFT)
+#define AIPS_BRD_PACRU_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRU_TP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_TP0_MASK, AIPS_PACRU_TP0(value)))
+#define AIPS_BWR_PACRU_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_WP0 field. */
+#define AIPS_RD_PACRU_WP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_WP0_MASK) >> AIPS_PACRU_WP0_SHIFT)
+#define AIPS_BRD_PACRU_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRU_WP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_WP0_MASK, AIPS_PACRU_WP0(value)))
+#define AIPS_BWR_PACRU_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_SP0 field. */
+#define AIPS_RD_PACRU_SP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_SP0_MASK) >> AIPS_PACRU_SP0_SHIFT)
+#define AIPS_BRD_PACRU_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRU_SP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_SP0_MASK, AIPS_PACRU_SP0(value)))
+#define AIPS_BWR_PACRU_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP0_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 AXBS
+ *
+ * Crossbar switch
+ *
+ * Registers defined in this header file:
+ * - AXBS_PRS - Priority Registers Slave
+ * - AXBS_CRS - Control Register
+ * - AXBS_MGPCR0 - Master General Purpose Control Register
+ * - AXBS_MGPCR1 - Master General Purpose Control Register
+ * - AXBS_MGPCR2 - Master General Purpose Control Register
+ * - AXBS_MGPCR3 - Master General Purpose Control Register
+ * - AXBS_MGPCR4 - Master General Purpose Control Register
+ * - AXBS_MGPCR5 - Master General Purpose Control Register
+ */
+
+#define AXBS_INSTANCE_COUNT (1U) /*!< Number of instances of the AXBS module. */
+#define AXBS_IDX (0U) /*!< Instance number for AXBS. */
+
+/*******************************************************************************
+ * AXBS_PRS - Priority Registers Slave
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_PRS - Priority Registers Slave (RW)
+ *
+ * Reset value: 0x00543210U
+ *
+ * The priority registers (PRSn) set the priority of each master port on a per
+ * slave port basis and reside in each slave port. The priority register can be
+ * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
+ * register can only be read; attempts to write to it have no effect on PRSn and
+ * result in a bus-error response to the master initiating the write. Two available
+ * masters must not be programmed with the same priority level. Attempts to
+ * program two or more masters with the same priority level result in a bus-error
+ * response and the PRSn is not updated. Valid values for the Mn priority fields
+ * depend on which masters are available on the chip. This information can be found in
+ * the chip-specific information for the crossbar. If the chip contains less
+ * than five masters, values 0 to 3 are valid. Writing other values will result in
+ * an error. If the chip contains five or more masters, valid values are 0 to n-1,
+ * where n is the number of masters attached to the AXBS module. Other values
+ * will result in an error.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_PRS register
+ */
+/*@{*/
+#define AXBS_RD_PRS(base, index) (AXBS_PRS_REG(base, index))
+#define AXBS_WR_PRS(base, index, value) (AXBS_PRS_REG(base, index) = (value))
+#define AXBS_RMW_PRS(base, index, mask, value) (AXBS_WR_PRS(base, index, (AXBS_RD_PRS(base, index) & ~(mask)) | (value)))
+#define AXBS_SET_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) |  (value)))
+#define AXBS_CLR_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) & ~(value)))
+#define AXBS_TOG_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_PRS bitfields
+ */
+
+/*!
+ * @name Register AXBS_PRS, field M0[2:0] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M0 field. */
+#define AXBS_RD_PRS_M0(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M0_MASK) >> AXBS_PRS_M0_SHIFT)
+#define AXBS_BRD_PRS_M0(base, index) (AXBS_RD_PRS_M0(base, index))
+
+/*! @brief Set the M0 field to a new value. */
+#define AXBS_WR_PRS_M0(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M0_MASK, AXBS_PRS_M0(value)))
+#define AXBS_BWR_PRS_M0(base, index, value) (AXBS_WR_PRS_M0(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M1[6:4] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M1 field. */
+#define AXBS_RD_PRS_M1(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M1_MASK) >> AXBS_PRS_M1_SHIFT)
+#define AXBS_BRD_PRS_M1(base, index) (AXBS_RD_PRS_M1(base, index))
+
+/*! @brief Set the M1 field to a new value. */
+#define AXBS_WR_PRS_M1(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M1_MASK, AXBS_PRS_M1(value)))
+#define AXBS_BWR_PRS_M1(base, index, value) (AXBS_WR_PRS_M1(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M2[10:8] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M2 field. */
+#define AXBS_RD_PRS_M2(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M2_MASK) >> AXBS_PRS_M2_SHIFT)
+#define AXBS_BRD_PRS_M2(base, index) (AXBS_RD_PRS_M2(base, index))
+
+/*! @brief Set the M2 field to a new value. */
+#define AXBS_WR_PRS_M2(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M2_MASK, AXBS_PRS_M2(value)))
+#define AXBS_BWR_PRS_M2(base, index, value) (AXBS_WR_PRS_M2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M3[14:12] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M3 field. */
+#define AXBS_RD_PRS_M3(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M3_MASK) >> AXBS_PRS_M3_SHIFT)
+#define AXBS_BRD_PRS_M3(base, index) (AXBS_RD_PRS_M3(base, index))
+
+/*! @brief Set the M3 field to a new value. */
+#define AXBS_WR_PRS_M3(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M3_MASK, AXBS_PRS_M3(value)))
+#define AXBS_BWR_PRS_M3(base, index, value) (AXBS_WR_PRS_M3(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M4[18:16] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M4 field. */
+#define AXBS_RD_PRS_M4(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M4_MASK) >> AXBS_PRS_M4_SHIFT)
+#define AXBS_BRD_PRS_M4(base, index) (AXBS_RD_PRS_M4(base, index))
+
+/*! @brief Set the M4 field to a new value. */
+#define AXBS_WR_PRS_M4(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M4_MASK, AXBS_PRS_M4(value)))
+#define AXBS_BWR_PRS_M4(base, index, value) (AXBS_WR_PRS_M4(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M5[22:20] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M5 field. */
+#define AXBS_RD_PRS_M5(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M5_MASK) >> AXBS_PRS_M5_SHIFT)
+#define AXBS_BRD_PRS_M5(base, index) (AXBS_RD_PRS_M5(base, index))
+
+/*! @brief Set the M5 field to a new value. */
+#define AXBS_WR_PRS_M5(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M5_MASK, AXBS_PRS_M5(value)))
+#define AXBS_BWR_PRS_M5(base, index, value) (AXBS_WR_PRS_M5(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_CRS - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_CRS - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers control several features of each slave port and must be
+ * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
+ * attempts to write to it have no effect and result in an error response.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_CRS register
+ */
+/*@{*/
+#define AXBS_RD_CRS(base, index) (AXBS_CRS_REG(base, index))
+#define AXBS_WR_CRS(base, index, value) (AXBS_CRS_REG(base, index) = (value))
+#define AXBS_RMW_CRS(base, index, mask, value) (AXBS_WR_CRS(base, index, (AXBS_RD_CRS(base, index) & ~(mask)) | (value)))
+#define AXBS_SET_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) |  (value)))
+#define AXBS_CLR_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) & ~(value)))
+#define AXBS_TOG_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_CRS bitfields
+ */
+
+/*!
+ * @name Register AXBS_CRS, field PARK[2:0] (RW)
+ *
+ * Determines which master port the current slave port parks on when no masters
+ * are actively making requests and the PCTL bits are cleared. Select only master
+ * ports that are present on the chip. Otherwise, undefined behavior might occur.
+ *
+ * Values:
+ * - 0b000 - Park on master port M0
+ * - 0b001 - Park on master port M1
+ * - 0b010 - Park on master port M2
+ * - 0b011 - Park on master port M3
+ * - 0b100 - Park on master port M4
+ * - 0b101 - Park on master port M5
+ * - 0b110 - Park on master port M6
+ * - 0b111 - Park on master port M7
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_PARK field. */
+#define AXBS_RD_CRS_PARK(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_PARK_MASK) >> AXBS_CRS_PARK_SHIFT)
+#define AXBS_BRD_CRS_PARK(base, index) (AXBS_RD_CRS_PARK(base, index))
+
+/*! @brief Set the PARK field to a new value. */
+#define AXBS_WR_CRS_PARK(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_PARK_MASK, AXBS_CRS_PARK(value)))
+#define AXBS_BWR_CRS_PARK(base, index, value) (AXBS_WR_CRS_PARK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field PCTL[5:4] (RW)
+ *
+ * Determines the slave port's parking control. The low-power park feature
+ * results in an overall power savings if the slave port is not saturated. However,
+ * this forces an extra latency clock when any master tries to access the slave
+ * port while not in use because it is not parked on any master.
+ *
+ * Values:
+ * - 0b00 - When no master makes a request, the arbiter parks the slave port on
+ *     the master port defined by the PARK field
+ * - 0b01 - When no master makes a request, the arbiter parks the slave port on
+ *     the last master to be in control of the slave port
+ * - 0b10 - When no master makes a request, the slave port is not parked on a
+ *     master and the arbiter drives all outputs to a constant safe state
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_PCTL field. */
+#define AXBS_RD_CRS_PCTL(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_PCTL_MASK) >> AXBS_CRS_PCTL_SHIFT)
+#define AXBS_BRD_CRS_PCTL(base, index) (AXBS_RD_CRS_PCTL(base, index))
+
+/*! @brief Set the PCTL field to a new value. */
+#define AXBS_WR_CRS_PCTL(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_PCTL_MASK, AXBS_CRS_PCTL(value)))
+#define AXBS_BWR_CRS_PCTL(base, index, value) (AXBS_WR_CRS_PCTL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field ARB[9:8] (RW)
+ *
+ * Selects the arbitration policy for the slave port.
+ *
+ * Values:
+ * - 0b00 - Fixed priority
+ * - 0b01 - Round-robin, or rotating, priority
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_ARB field. */
+#define AXBS_RD_CRS_ARB(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_ARB_MASK) >> AXBS_CRS_ARB_SHIFT)
+#define AXBS_BRD_CRS_ARB(base, index) (AXBS_RD_CRS_ARB(base, index))
+
+/*! @brief Set the ARB field to a new value. */
+#define AXBS_WR_CRS_ARB(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_ARB_MASK, AXBS_CRS_ARB(value)))
+#define AXBS_BWR_CRS_ARB(base, index, value) (AXBS_WR_CRS_ARB(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field HLP[30] (RW)
+ *
+ * Sets the initial arbitration priority for low power mode requests . Setting
+ * this bit will not affect the request for low power mode from attaining highest
+ * priority once it has control of the slave ports.
+ *
+ * Values:
+ * - 0b0 - The low power mode request has the highest priority for arbitration
+ *     on this slave port
+ * - 0b1 - The low power mode request has the lowest initial priority for
+ *     arbitration on this slave port
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_HLP field. */
+#define AXBS_RD_CRS_HLP(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_HLP_MASK) >> AXBS_CRS_HLP_SHIFT)
+#define AXBS_BRD_CRS_HLP(base, index) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_HLP_SHIFT))
+
+/*! @brief Set the HLP field to a new value. */
+#define AXBS_WR_CRS_HLP(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_HLP_MASK, AXBS_CRS_HLP(value)))
+#define AXBS_BWR_CRS_HLP(base, index, value) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_HLP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field RO[31] (RW)
+ *
+ * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
+ * only a hardware reset clears it.
+ *
+ * Values:
+ * - 0b0 - The slave port's registers are writeable
+ * - 0b1 - The slave port's registers are read-only and cannot be written.
+ *     Attempted writes have no effect on the registers and result in a bus error
+ *     response.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_RO field. */
+#define AXBS_RD_CRS_RO(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_RO_MASK) >> AXBS_CRS_RO_SHIFT)
+#define AXBS_BRD_CRS_RO(base, index) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_RO_SHIFT))
+
+/*! @brief Set the RO field to a new value. */
+#define AXBS_WR_CRS_RO(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_RO_MASK, AXBS_CRS_RO(value)))
+#define AXBS_BWR_CRS_RO(base, index, value) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_RO_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR0 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR0 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR0 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR0(base)     (AXBS_MGPCR0_REG(base))
+#define AXBS_WR_MGPCR0(base, value) (AXBS_MGPCR0_REG(base) = (value))
+#define AXBS_RMW_MGPCR0(base, mask, value) (AXBS_WR_MGPCR0(base, (AXBS_RD_MGPCR0(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) |  (value)))
+#define AXBS_CLR_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) & ~(value)))
+#define AXBS_TOG_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR0 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR0_AULB field. */
+#define AXBS_RD_MGPCR0_AULB(base) ((AXBS_MGPCR0_REG(base) & AXBS_MGPCR0_AULB_MASK) >> AXBS_MGPCR0_AULB_SHIFT)
+#define AXBS_BRD_MGPCR0_AULB(base) (AXBS_RD_MGPCR0_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR0_AULB(base, value) (AXBS_RMW_MGPCR0(base, AXBS_MGPCR0_AULB_MASK, AXBS_MGPCR0_AULB(value)))
+#define AXBS_BWR_MGPCR0_AULB(base, value) (AXBS_WR_MGPCR0_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR1 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR1 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR1 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR1(base)     (AXBS_MGPCR1_REG(base))
+#define AXBS_WR_MGPCR1(base, value) (AXBS_MGPCR1_REG(base) = (value))
+#define AXBS_RMW_MGPCR1(base, mask, value) (AXBS_WR_MGPCR1(base, (AXBS_RD_MGPCR1(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) |  (value)))
+#define AXBS_CLR_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) & ~(value)))
+#define AXBS_TOG_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR1 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR1_AULB field. */
+#define AXBS_RD_MGPCR1_AULB(base) ((AXBS_MGPCR1_REG(base) & AXBS_MGPCR1_AULB_MASK) >> AXBS_MGPCR1_AULB_SHIFT)
+#define AXBS_BRD_MGPCR1_AULB(base) (AXBS_RD_MGPCR1_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR1_AULB(base, value) (AXBS_RMW_MGPCR1(base, AXBS_MGPCR1_AULB_MASK, AXBS_MGPCR1_AULB(value)))
+#define AXBS_BWR_MGPCR1_AULB(base, value) (AXBS_WR_MGPCR1_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR2 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR2 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR2 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR2(base)     (AXBS_MGPCR2_REG(base))
+#define AXBS_WR_MGPCR2(base, value) (AXBS_MGPCR2_REG(base) = (value))
+#define AXBS_RMW_MGPCR2(base, mask, value) (AXBS_WR_MGPCR2(base, (AXBS_RD_MGPCR2(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) |  (value)))
+#define AXBS_CLR_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) & ~(value)))
+#define AXBS_TOG_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR2 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR2_AULB field. */
+#define AXBS_RD_MGPCR2_AULB(base) ((AXBS_MGPCR2_REG(base) & AXBS_MGPCR2_AULB_MASK) >> AXBS_MGPCR2_AULB_SHIFT)
+#define AXBS_BRD_MGPCR2_AULB(base) (AXBS_RD_MGPCR2_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR2_AULB(base, value) (AXBS_RMW_MGPCR2(base, AXBS_MGPCR2_AULB_MASK, AXBS_MGPCR2_AULB(value)))
+#define AXBS_BWR_MGPCR2_AULB(base, value) (AXBS_WR_MGPCR2_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR3 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR3 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR3 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR3(base)     (AXBS_MGPCR3_REG(base))
+#define AXBS_WR_MGPCR3(base, value) (AXBS_MGPCR3_REG(base) = (value))
+#define AXBS_RMW_MGPCR3(base, mask, value) (AXBS_WR_MGPCR3(base, (AXBS_RD_MGPCR3(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) |  (value)))
+#define AXBS_CLR_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) & ~(value)))
+#define AXBS_TOG_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR3 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR3_AULB field. */
+#define AXBS_RD_MGPCR3_AULB(base) ((AXBS_MGPCR3_REG(base) & AXBS_MGPCR3_AULB_MASK) >> AXBS_MGPCR3_AULB_SHIFT)
+#define AXBS_BRD_MGPCR3_AULB(base) (AXBS_RD_MGPCR3_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR3_AULB(base, value) (AXBS_RMW_MGPCR3(base, AXBS_MGPCR3_AULB_MASK, AXBS_MGPCR3_AULB(value)))
+#define AXBS_BWR_MGPCR3_AULB(base, value) (AXBS_WR_MGPCR3_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR4 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR4 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR4 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR4(base)     (AXBS_MGPCR4_REG(base))
+#define AXBS_WR_MGPCR4(base, value) (AXBS_MGPCR4_REG(base) = (value))
+#define AXBS_RMW_MGPCR4(base, mask, value) (AXBS_WR_MGPCR4(base, (AXBS_RD_MGPCR4(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) |  (value)))
+#define AXBS_CLR_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) & ~(value)))
+#define AXBS_TOG_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR4 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR4_AULB field. */
+#define AXBS_RD_MGPCR4_AULB(base) ((AXBS_MGPCR4_REG(base) & AXBS_MGPCR4_AULB_MASK) >> AXBS_MGPCR4_AULB_SHIFT)
+#define AXBS_BRD_MGPCR4_AULB(base) (AXBS_RD_MGPCR4_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR4_AULB(base, value) (AXBS_RMW_MGPCR4(base, AXBS_MGPCR4_AULB_MASK, AXBS_MGPCR4_AULB(value)))
+#define AXBS_BWR_MGPCR4_AULB(base, value) (AXBS_WR_MGPCR4_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR5 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR5 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR5 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR5(base)     (AXBS_MGPCR5_REG(base))
+#define AXBS_WR_MGPCR5(base, value) (AXBS_MGPCR5_REG(base) = (value))
+#define AXBS_RMW_MGPCR5(base, mask, value) (AXBS_WR_MGPCR5(base, (AXBS_RD_MGPCR5(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) |  (value)))
+#define AXBS_CLR_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) & ~(value)))
+#define AXBS_TOG_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR5 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR5_AULB field. */
+#define AXBS_RD_MGPCR5_AULB(base) ((AXBS_MGPCR5_REG(base) & AXBS_MGPCR5_AULB_MASK) >> AXBS_MGPCR5_AULB_SHIFT)
+#define AXBS_BRD_MGPCR5_AULB(base) (AXBS_RD_MGPCR5_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR5_AULB(base, value) (AXBS_RMW_MGPCR5(base, AXBS_MGPCR5_AULB_MASK, AXBS_MGPCR5_AULB(value)))
+#define AXBS_BWR_MGPCR5_AULB(base, value) (AXBS_WR_MGPCR5_AULB(base, value))
+/*@}*/
+
+/*
+ * MK64F12 CAN
+ *
+ * Flex Controller Area Network module
+ *
+ * Registers defined in this header file:
+ * - CAN_MCR - Module Configuration Register
+ * - CAN_CTRL1 - Control 1 register
+ * - CAN_TIMER - Free Running Timer
+ * - CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ * - CAN_RX14MASK - Rx 14 Mask register
+ * - CAN_RX15MASK - Rx 15 Mask register
+ * - CAN_ECR - Error Counter
+ * - CAN_ESR1 - Error and Status 1 register
+ * - CAN_IMASK1 - Interrupt Masks 1 register
+ * - CAN_IFLAG1 - Interrupt Flags 1 register
+ * - CAN_CTRL2 - Control 2 register
+ * - CAN_ESR2 - Error and Status 2 register
+ * - CAN_CRCR - CRC Register
+ * - CAN_RXFGMASK - Rx FIFO Global Mask register
+ * - CAN_RXFIR - Rx FIFO Information Register
+ * - CAN_CS - Message Buffer 0 CS Register
+ * - CAN_ID - Message Buffer 0 ID Register
+ * - CAN_WORD0 - Message Buffer 0 WORD0 Register
+ * - CAN_WORD1 - Message Buffer 0 WORD1 Register
+ * - CAN_RXIMR - Rx Individual Mask Registers
+ */
+
+#define CAN_INSTANCE_COUNT (1U) /*!< Number of instances of the CAN module. */
+#define CAN0_IDX (0U) /*!< Instance number for CAN0. */
+
+/*******************************************************************************
+ * CAN_MCR - Module Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0xD890000FU
+ *
+ * This register defines global system configurations, such as the module
+ * operation modes and the maximum message buffer configuration.
+ */
+/*!
+ * @name Constants and macros for entire CAN_MCR register
+ */
+/*@{*/
+#define CAN_RD_MCR(base)         (CAN_MCR_REG(base))
+#define CAN_WR_MCR(base, value)  (CAN_MCR_REG(base) = (value))
+#define CAN_RMW_MCR(base, mask, value) (CAN_WR_MCR(base, (CAN_RD_MCR(base) & ~(mask)) | (value)))
+#define CAN_SET_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) |  (value)))
+#define CAN_CLR_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) & ~(value)))
+#define CAN_TOG_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_MCR bitfields
+ */
+
+/*!
+ * @name Register CAN_MCR, field MAXMB[6:0] (RW)
+ *
+ * This 7-bit field defines the number of the last Message Buffers that will
+ * take part in the matching and arbitration processes. The reset value (0x0F) is
+ * equivalent to a 16 MB configuration. This field can be written only in Freeze
+ * mode because it is blocked by hardware in other modes. Number of the last MB =
+ * MAXMB MAXMB must be programmed with a value smaller than the parameter
+ * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
+ * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
+ * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
+ * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
+ * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
+ * Matching Timing").
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_MAXMB field. */
+#define CAN_RD_MCR_MAXMB(base) ((CAN_MCR_REG(base) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT)
+#define CAN_BRD_MCR_MAXMB(base) (CAN_RD_MCR_MAXMB(base))
+
+/*! @brief Set the MAXMB field to a new value. */
+#define CAN_WR_MCR_MAXMB(base, value) (CAN_RMW_MCR(base, CAN_MCR_MAXMB_MASK, CAN_MCR_MAXMB(value)))
+#define CAN_BWR_MCR_MAXMB(base, value) (CAN_WR_MCR_MAXMB(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field IDAM[9:8] (RW)
+ *
+ * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
+ * elements. Note that all elements of the table are configured at the same time by this
+ * field (they are all the same format). See Section "Rx FIFO Structure". This
+ * field can be written only in Freeze mode because it is blocked by hardware in
+ * other modes.
+ *
+ * Values:
+ * - 0b00 - Format A: One full ID (standard and extended) per ID Filter Table
+ *     element.
+ * - 0b01 - Format B: Two full standard IDs or two partial 14-bit (standard and
+ *     extended) IDs per ID Filter Table element.
+ * - 0b10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table
+ *     element.
+ * - 0b11 - Format D: All frames rejected.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_IDAM field. */
+#define CAN_RD_MCR_IDAM(base) ((CAN_MCR_REG(base) & CAN_MCR_IDAM_MASK) >> CAN_MCR_IDAM_SHIFT)
+#define CAN_BRD_MCR_IDAM(base) (CAN_RD_MCR_IDAM(base))
+
+/*! @brief Set the IDAM field to a new value. */
+#define CAN_WR_MCR_IDAM(base, value) (CAN_RMW_MCR(base, CAN_MCR_IDAM_MASK, CAN_MCR_IDAM(value)))
+#define CAN_BWR_MCR_IDAM(base, value) (CAN_WR_MCR_IDAM(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field AEN[12] (RW)
+ *
+ * This bit is supplied for backwards compatibility with legacy applications.
+ * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
+ * safe procedure for aborting a pending transmission, so that no frame is sent in
+ * the CAN bus without notification. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
+ * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
+ * used for updating Mailboxes configured for transmission. Writing the Abort code
+ * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Abort disabled.
+ * - 0b1 - Abort enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_AEN field. */
+#define CAN_RD_MCR_AEN(base) ((CAN_MCR_REG(base) & CAN_MCR_AEN_MASK) >> CAN_MCR_AEN_SHIFT)
+#define CAN_BRD_MCR_AEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_AEN_SHIFT))
+
+/*! @brief Set the AEN field to a new value. */
+#define CAN_WR_MCR_AEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_AEN_MASK, CAN_MCR_AEN(value)))
+#define CAN_BWR_MCR_AEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_AEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field LPRIOEN[13] (RW)
+ *
+ * This bit is provided for backwards compatibility with legacy applications. It
+ * controls whether the local priority feature is enabled or not. It is used to
+ * expand the ID used during the arbitration process. With this expanded ID
+ * concept, the arbitration process is done based on the full 32-bit word, but the
+ * actual transmitted ID still has 11-bit for standard frames and 29-bit for
+ * extended frames. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Local Priority disabled.
+ * - 0b1 - Local Priority enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_LPRIOEN field. */
+#define CAN_RD_MCR_LPRIOEN(base) ((CAN_MCR_REG(base) & CAN_MCR_LPRIOEN_MASK) >> CAN_MCR_LPRIOEN_SHIFT)
+#define CAN_BRD_MCR_LPRIOEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPRIOEN_SHIFT))
+
+/*! @brief Set the LPRIOEN field to a new value. */
+#define CAN_WR_MCR_LPRIOEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_LPRIOEN_MASK, CAN_MCR_LPRIOEN(value)))
+#define CAN_BWR_MCR_LPRIOEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPRIOEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field IRMQ[16] (RW)
+ *
+ * This bit indicates whether Rx matching process will be based either on
+ * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
+ * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Individual Rx masking and queue feature are disabled. For backward
+ *     compatibility with legacy applications, the reading of C/S word locks the MB
+ *     even if it is EMPTY.
+ * - 0b1 - Individual Rx masking and queue feature are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_IRMQ field. */
+#define CAN_RD_MCR_IRMQ(base) ((CAN_MCR_REG(base) & CAN_MCR_IRMQ_MASK) >> CAN_MCR_IRMQ_SHIFT)
+#define CAN_BRD_MCR_IRMQ(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_IRMQ_SHIFT))
+
+/*! @brief Set the IRMQ field to a new value. */
+#define CAN_WR_MCR_IRMQ(base, value) (CAN_RMW_MCR(base, CAN_MCR_IRMQ_MASK, CAN_MCR_IRMQ(value)))
+#define CAN_BWR_MCR_IRMQ(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_IRMQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SRXDIS[17] (RW)
+ *
+ * This bit defines whether FlexCAN is allowed to receive frames transmitted by
+ * itself. If this bit is asserted, frames transmitted by the module will not be
+ * stored in any MB, regardless if the MB is programmed with an ID that matches
+ * the transmitted frame, and no interrupt flag or interrupt signal will be
+ * generated due to the frame reception. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Self reception enabled.
+ * - 0b1 - Self reception disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SRXDIS field. */
+#define CAN_RD_MCR_SRXDIS(base) ((CAN_MCR_REG(base) & CAN_MCR_SRXDIS_MASK) >> CAN_MCR_SRXDIS_SHIFT)
+#define CAN_BRD_MCR_SRXDIS(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SRXDIS_SHIFT))
+
+/*! @brief Set the SRXDIS field to a new value. */
+#define CAN_WR_MCR_SRXDIS(base, value) (CAN_RMW_MCR(base, CAN_MCR_SRXDIS_MASK, CAN_MCR_SRXDIS(value)))
+#define CAN_BWR_MCR_SRXDIS(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SRXDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WAKSRC[19] (RW)
+ *
+ * This bit defines whether the integrated low-pass filter is applied to protect
+ * the Rx CAN input from spurious wake up. This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ * - 0b1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WAKSRC field. */
+#define CAN_RD_MCR_WAKSRC(base) ((CAN_MCR_REG(base) & CAN_MCR_WAKSRC_MASK) >> CAN_MCR_WAKSRC_SHIFT)
+#define CAN_BRD_MCR_WAKSRC(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKSRC_SHIFT))
+
+/*! @brief Set the WAKSRC field to a new value. */
+#define CAN_WR_MCR_WAKSRC(base, value) (CAN_RMW_MCR(base, CAN_MCR_WAKSRC_MASK, CAN_MCR_WAKSRC(value)))
+#define CAN_BWR_MCR_WAKSRC(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field LPMACK[20] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
+ * mode , Stop mode ). A low-power mode cannot be entered until all current
+ * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
+ * to know when FlexCAN has actually entered low power mode. LPMACK will be
+ * asserted within 180 CAN bits from the low-power mode request by the CPU, and
+ * negated within 2 CAN bits after the low-power mode request removal (see Section
+ * "Protocol Timing").
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not in a low-power mode.
+ * - 0b1 - FlexCAN is in a low-power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_LPMACK field. */
+#define CAN_RD_MCR_LPMACK(base) ((CAN_MCR_REG(base) & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT)
+#define CAN_BRD_MCR_LPMACK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPMACK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WRNEN[21] (RW)
+ *
+ * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
+ * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
+ * RWRNINT flags will always be zero, independent of the values of the error
+ * counters, and no warning interrupt will ever be generated. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
+ *     error counters.
+ * - 0b1 - TWRNINT and RWRNINT bits are set when the respective error counter
+ *     transitions from less than 96 to greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WRNEN field. */
+#define CAN_RD_MCR_WRNEN(base) ((CAN_MCR_REG(base) & CAN_MCR_WRNEN_MASK) >> CAN_MCR_WRNEN_SHIFT)
+#define CAN_BRD_MCR_WRNEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WRNEN_SHIFT))
+
+/*! @brief Set the WRNEN field to a new value. */
+#define CAN_WR_MCR_WRNEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_WRNEN_MASK, CAN_MCR_WRNEN(value)))
+#define CAN_BWR_MCR_WRNEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WRNEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SLFWAK[22] (RW)
+ *
+ * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
+ * other than Disable mode. When this feature is enabled, the FlexCAN module
+ * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
+ * If a wake up event is detected during Stop mode, then FlexCAN generates, if
+ * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
+ * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
+ * low-power mode other than Disable mode, this bit cannot be written as it is
+ * blocked by hardware.
+ *
+ * Values:
+ * - 0b0 - FlexCAN Self Wake Up feature is disabled.
+ * - 0b1 - FlexCAN Self Wake Up feature is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SLFWAK field. */
+#define CAN_RD_MCR_SLFWAK(base) ((CAN_MCR_REG(base) & CAN_MCR_SLFWAK_MASK) >> CAN_MCR_SLFWAK_SHIFT)
+#define CAN_BRD_MCR_SLFWAK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SLFWAK_SHIFT))
+
+/*! @brief Set the SLFWAK field to a new value. */
+#define CAN_WR_MCR_SLFWAK(base, value) (CAN_RMW_MCR(base, CAN_MCR_SLFWAK_MASK, CAN_MCR_SLFWAK(value)))
+#define CAN_BWR_MCR_SLFWAK(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SLFWAK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SUPV[23] (RW)
+ *
+ * This bit configures the FlexCAN to be either in Supervisor or User mode. The
+ * registers affected by this bit are marked as S/U in the Access Type column of
+ * the module memory map. Reset value of this bit is 1, so the affected registers
+ * start with Supervisor access allowance only . This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
+ *     Unrestricted accesses .
+ * - 0b1 - FlexCAN is in Supervisor mode. Affected registers allow only
+ *     Supervisor access. Unrestricted access behaves as though the access was done to an
+ *     unimplemented register location .
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SUPV field. */
+#define CAN_RD_MCR_SUPV(base) ((CAN_MCR_REG(base) & CAN_MCR_SUPV_MASK) >> CAN_MCR_SUPV_SHIFT)
+#define CAN_BRD_MCR_SUPV(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SUPV_SHIFT))
+
+/*! @brief Set the SUPV field to a new value. */
+#define CAN_WR_MCR_SUPV(base, value) (CAN_RMW_MCR(base, CAN_MCR_SUPV_MASK, CAN_MCR_SUPV(value)))
+#define CAN_BWR_MCR_SUPV(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SUPV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field FRZACK[24] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
+ * is stopped. The Freeze mode request cannot be granted until current
+ * transmission or reception processes have finished. Therefore the software can poll the
+ * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
+ * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
+ * running again. If Freeze mode is requested while FlexCAN is in a low power
+ * mode, then the FRZACK bit will be set only when the low-power mode is exited.
+ * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
+ * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
+ * mode request removal (see Section "Protocol Timing").
+ *
+ * Values:
+ * - 0b0 - FlexCAN not in Freeze mode, prescaler running.
+ * - 0b1 - FlexCAN in Freeze mode, prescaler stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_FRZACK field. */
+#define CAN_RD_MCR_FRZACK(base) ((CAN_MCR_REG(base) & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)
+#define CAN_BRD_MCR_FRZACK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZACK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SOFTRST[25] (RW)
+ *
+ * When this bit is asserted, FlexCAN resets its internal state machines and
+ * some of the memory mapped registers. The following registers are reset: MCR
+ * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
+ * CRCR. Configuration registers that control the interface to the CAN bus are
+ * not affected by soft reset. The following registers are unaffected: CTRL1,
+ * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
+ * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
+ * writes to the MCR Register, but it is also asserted when global soft reset is
+ * requested at MCU level . Because soft reset is synchronous and has to follow a
+ * request/acknowledge procedure across clock domains, it may take some time to
+ * fully propagate its effect. The SOFTRST bit remains asserted while reset is
+ * pending, and is automatically negated when reset completes. Therefore, software can
+ * poll this bit to know when the soft reset has completed. Soft reset cannot be
+ * applied while clocks are shut down in a low power mode. The module should be
+ * first removed from low power mode, and then soft reset can be applied.
+ *
+ * Values:
+ * - 0b0 - No reset request.
+ * - 0b1 - Resets the registers affected by soft reset.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SOFTRST field. */
+#define CAN_RD_MCR_SOFTRST(base) ((CAN_MCR_REG(base) & CAN_MCR_SOFTRST_MASK) >> CAN_MCR_SOFTRST_SHIFT)
+#define CAN_BRD_MCR_SOFTRST(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SOFTRST_SHIFT))
+
+/*! @brief Set the SOFTRST field to a new value. */
+#define CAN_WR_MCR_SOFTRST(base, value) (CAN_RMW_MCR(base, CAN_MCR_SOFTRST_MASK, CAN_MCR_SOFTRST(value)))
+#define CAN_BWR_MCR_SOFTRST(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SOFTRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WAKMSK[26] (RW)
+ *
+ * This bit enables the Wake Up Interrupt generation under Self Wake Up
+ * mechanism.
+ *
+ * Values:
+ * - 0b0 - Wake Up Interrupt is disabled.
+ * - 0b1 - Wake Up Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WAKMSK field. */
+#define CAN_RD_MCR_WAKMSK(base) ((CAN_MCR_REG(base) & CAN_MCR_WAKMSK_MASK) >> CAN_MCR_WAKMSK_SHIFT)
+#define CAN_BRD_MCR_WAKMSK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKMSK_SHIFT))
+
+/*! @brief Set the WAKMSK field to a new value. */
+#define CAN_WR_MCR_WAKMSK(base, value) (CAN_RMW_MCR(base, CAN_MCR_WAKMSK_MASK, CAN_MCR_WAKMSK(value)))
+#define CAN_BWR_MCR_WAKMSK(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field NOTRDY[27] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
+ * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN module is either in Normal mode, Listen-Only mode or
+ *     Loop-Back mode.
+ * - 0b1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_NOTRDY field. */
+#define CAN_RD_MCR_NOTRDY(base) ((CAN_MCR_REG(base) & CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT)
+#define CAN_BRD_MCR_NOTRDY(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_NOTRDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field HALT[28] (RW)
+ *
+ * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
+ * should clear it after initializing the Message Buffers and Control Register. No
+ * reception or transmission is performed by FlexCAN before this bit is cleared.
+ * Freeze mode cannot be entered while FlexCAN is in a low power mode.
+ *
+ * Values:
+ * - 0b0 - No Freeze mode request.
+ * - 0b1 - Enters Freeze mode if the FRZ bit is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_HALT field. */
+#define CAN_RD_MCR_HALT(base) ((CAN_MCR_REG(base) & CAN_MCR_HALT_MASK) >> CAN_MCR_HALT_SHIFT)
+#define CAN_BRD_MCR_HALT(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define CAN_WR_MCR_HALT(base, value) (CAN_RMW_MCR(base, CAN_MCR_HALT_MASK, CAN_MCR_HALT(value)))
+#define CAN_BWR_MCR_HALT(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field RFEN[29] (RW)
+ *
+ * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
+ * set, MBs 0 to 5 cannot be used for normal reception and transmission because
+ * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
+ * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
+ * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
+ * minimum number of peripheral clocks per CAN bit as described in the table
+ * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
+ * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Rx FIFO not enabled.
+ * - 0b1 - Rx FIFO enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_RFEN field. */
+#define CAN_RD_MCR_RFEN(base) ((CAN_MCR_REG(base) & CAN_MCR_RFEN_MASK) >> CAN_MCR_RFEN_SHIFT)
+#define CAN_BRD_MCR_RFEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_RFEN_SHIFT))
+
+/*! @brief Set the RFEN field to a new value. */
+#define CAN_WR_MCR_RFEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_RFEN_MASK, CAN_MCR_RFEN(value)))
+#define CAN_BWR_MCR_RFEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_RFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field FRZ[30] (RW)
+ *
+ * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
+ * Register is set or when Debug mode is requested at MCU level . When FRZ is
+ * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
+ * FlexCAN to exit from Freeze mode.
+ *
+ * Values:
+ * - 0b0 - Not enabled to enter Freeze mode.
+ * - 0b1 - Enabled to enter Freeze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_FRZ field. */
+#define CAN_RD_MCR_FRZ(base) ((CAN_MCR_REG(base) & CAN_MCR_FRZ_MASK) >> CAN_MCR_FRZ_SHIFT)
+#define CAN_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define CAN_WR_MCR_FRZ(base, value) (CAN_RMW_MCR(base, CAN_MCR_FRZ_MASK, CAN_MCR_FRZ(value)))
+#define CAN_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field MDIS[31] (RW)
+ *
+ * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
+ * disables the clocks to the CAN Protocol Engine and Controller Host Interface
+ * sub-modules. This is the only bit within this register not affected by soft
+ * reset.
+ *
+ * Values:
+ * - 0b0 - Enable the FlexCAN module.
+ * - 0b1 - Disable the FlexCAN module.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_MDIS field. */
+#define CAN_RD_MCR_MDIS(base) ((CAN_MCR_REG(base) & CAN_MCR_MDIS_MASK) >> CAN_MCR_MDIS_SHIFT)
+#define CAN_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define CAN_WR_MCR_MDIS(base, value) (CAN_RMW_MCR(base, CAN_MCR_MDIS_MASK, CAN_MCR_MDIS(value)))
+#define CAN_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CTRL1 - Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CTRL1 - Control 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is defined for specific FlexCAN control features related to the
+ * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
+ * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
+ * (Bus-Off, Error, Warning). It also determines the Division Factor for the
+ * clock prescaler.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CTRL1 register
+ */
+/*@{*/
+#define CAN_RD_CTRL1(base)       (CAN_CTRL1_REG(base))
+#define CAN_WR_CTRL1(base, value) (CAN_CTRL1_REG(base) = (value))
+#define CAN_RMW_CTRL1(base, mask, value) (CAN_WR_CTRL1(base, (CAN_RD_CTRL1(base) & ~(mask)) | (value)))
+#define CAN_SET_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) |  (value)))
+#define CAN_CLR_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) & ~(value)))
+#define CAN_TOG_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CTRL1 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
+ *
+ * This 3-bit field defines the length of the Propagation Segment in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Propagation
+ * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PROPSEG field. */
+#define CAN_RD_CTRL1_PROPSEG(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PROPSEG_MASK) >> CAN_CTRL1_PROPSEG_SHIFT)
+#define CAN_BRD_CTRL1_PROPSEG(base) (CAN_RD_CTRL1_PROPSEG(base))
+
+/*! @brief Set the PROPSEG field to a new value. */
+#define CAN_WR_CTRL1_PROPSEG(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PROPSEG_MASK, CAN_CTRL1_PROPSEG(value)))
+#define CAN_BWR_CTRL1_PROPSEG(base, value) (CAN_WR_CTRL1_PROPSEG(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LOM[3] (RW)
+ *
+ * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
+ * transmission is disabled, all error counters are frozen and the module operates
+ * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
+ * will be received. If FlexCAN detects a message that has not been acknowledged,
+ * it will flag a BIT0 error without changing the REC, as if it was trying to
+ * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
+ * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
+ * entered. There can be some delay between the Listen-Only mode request and
+ * acknowledge. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Listen-Only mode is deactivated.
+ * - 0b1 - FlexCAN module operates in Listen-Only mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LOM field. */
+#define CAN_RD_CTRL1_LOM(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LOM_MASK) >> CAN_CTRL1_LOM_SHIFT)
+#define CAN_BRD_CTRL1_LOM(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LOM_SHIFT))
+
+/*! @brief Set the LOM field to a new value. */
+#define CAN_WR_CTRL1_LOM(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LOM_MASK, CAN_CTRL1_LOM(value)))
+#define CAN_BWR_CTRL1_LOM(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LBUF[4] (RW)
+ *
+ * This bit defines the ordering mechanism for Message Buffer transmission. When
+ * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0b0 - Buffer with highest priority is transmitted first.
+ * - 0b1 - Lowest number buffer is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LBUF field. */
+#define CAN_RD_CTRL1_LBUF(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LBUF_MASK) >> CAN_CTRL1_LBUF_SHIFT)
+#define CAN_BRD_CTRL1_LBUF(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LBUF_SHIFT))
+
+/*! @brief Set the LBUF field to a new value. */
+#define CAN_WR_CTRL1_LBUF(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LBUF_MASK, CAN_CTRL1_LBUF(value)))
+#define CAN_BWR_CTRL1_LBUF(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field TSYN[5] (RW)
+ *
+ * This bit enables a mechanism that resets the free-running timer each time a
+ * message is received in Message Buffer 0. This feature provides means to
+ * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
+ * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
+ * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
+ * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Timer Sync feature disabled
+ * - 0b1 - Timer Sync feature enabled
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_TSYN field. */
+#define CAN_RD_CTRL1_TSYN(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_TSYN_MASK) >> CAN_CTRL1_TSYN_SHIFT)
+#define CAN_BRD_CTRL1_TSYN(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TSYN_SHIFT))
+
+/*! @brief Set the TSYN field to a new value. */
+#define CAN_WR_CTRL1_TSYN(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_TSYN_MASK, CAN_CTRL1_TSYN(value)))
+#define CAN_BWR_CTRL1_TSYN(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TSYN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
+ *
+ * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
+ * negated, automatic recovering from Bus Off state occurs according to the CAN
+ * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
+ * disabled and the module remains in Bus Off state until the bit is negated by the
+ * user. If the negation occurs before 128 sequences of 11 recessive bits are
+ * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
+ * never been asserted. If the negation occurs after 128 sequences of 11
+ * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
+ * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
+ * be re-asserted again during Bus Off, but it will be effective only the next
+ * time the module enters Bus Off. If BOFFREC was negated when the module entered
+ * Bus Off, asserting it during Bus Off will not be effective for the current Bus
+ * Off recovery.
+ *
+ * Values:
+ * - 0b0 - Automatic recovering from Bus Off state enabled, according to CAN
+ *     Spec 2.0 part B.
+ * - 0b1 - Automatic recovering from Bus Off state disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_BOFFREC field. */
+#define CAN_RD_CTRL1_BOFFREC(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_BOFFREC_MASK) >> CAN_CTRL1_BOFFREC_SHIFT)
+#define CAN_BRD_CTRL1_BOFFREC(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFREC_SHIFT))
+
+/*! @brief Set the BOFFREC field to a new value. */
+#define CAN_WR_CTRL1_BOFFREC(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_BOFFREC_MASK, CAN_CTRL1_BOFFREC(value)))
+#define CAN_BWR_CTRL1_BOFFREC(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFREC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field SMP[7] (RW)
+ *
+ * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
+ * be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0b0 - Just one sample is used to determine the bit value.
+ * - 0b1 - Three samples are used to determine the value of the received bit:
+ *     the regular one (sample point) and 2 preceding samples; a majority rule is
+ *     used.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_SMP field. */
+#define CAN_RD_CTRL1_SMP(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_SMP_MASK) >> CAN_CTRL1_SMP_SHIFT)
+#define CAN_BRD_CTRL1_SMP(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_SMP_SHIFT))
+
+/*! @brief Set the SMP field to a new value. */
+#define CAN_WR_CTRL1_SMP(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_SMP_MASK, CAN_CTRL1_SMP(value)))
+#define CAN_BWR_CTRL1_SMP(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_SMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
+ *
+ * This bit provides a mask for the Rx Warning Interrupt associated with the
+ * RWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Rx Warning Interrupt disabled.
+ * - 0b1 - Rx Warning Interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_RWRNMSK field. */
+#define CAN_RD_CTRL1_RWRNMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_RWRNMSK_MASK) >> CAN_CTRL1_RWRNMSK_SHIFT)
+#define CAN_BRD_CTRL1_RWRNMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_RWRNMSK_SHIFT))
+
+/*! @brief Set the RWRNMSK field to a new value. */
+#define CAN_WR_CTRL1_RWRNMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_RWRNMSK_MASK, CAN_CTRL1_RWRNMSK(value)))
+#define CAN_BWR_CTRL1_RWRNMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_RWRNMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
+ *
+ * This bit provides a mask for the Tx Warning Interrupt associated with the
+ * TWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Tx Warning Interrupt disabled.
+ * - 0b1 - Tx Warning Interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_TWRNMSK field. */
+#define CAN_RD_CTRL1_TWRNMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_TWRNMSK_MASK) >> CAN_CTRL1_TWRNMSK_SHIFT)
+#define CAN_BRD_CTRL1_TWRNMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TWRNMSK_SHIFT))
+
+/*! @brief Set the TWRNMSK field to a new value. */
+#define CAN_WR_CTRL1_TWRNMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_TWRNMSK_MASK, CAN_CTRL1_TWRNMSK(value)))
+#define CAN_BWR_CTRL1_TWRNMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TWRNMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LPB[12] (RW)
+ *
+ * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
+ * FlexCAN performs an internal loop back that can be used for self test operation.
+ * The bit stream output of the transmitter is fed back internally to the receiver
+ * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
+ * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
+ * and treats its own transmitted message as a message received from a remote
+ * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
+ * frame acknowledge field, generating an internal acknowledge bit to ensure proper
+ * reception of its own message. Both transmit and receive interrupts are
+ * generated. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
+ * this will impede the self reception of a transmitted message.
+ *
+ * Values:
+ * - 0b0 - Loop Back disabled.
+ * - 0b1 - Loop Back enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LPB field. */
+#define CAN_RD_CTRL1_LPB(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LPB_MASK) >> CAN_CTRL1_LPB_SHIFT)
+#define CAN_BRD_CTRL1_LPB(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LPB_SHIFT))
+
+/*! @brief Set the LPB field to a new value. */
+#define CAN_WR_CTRL1_LPB(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LPB_MASK, CAN_CTRL1_LPB(value)))
+#define CAN_BWR_CTRL1_LPB(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LPB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
+ *
+ * This bit selects the clock source to the CAN Protocol Engine (PE) to be
+ * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
+ * The selected clock is the one fed to the prescaler to generate the Serial Clock
+ * (Sclock). In order to guarantee reliable operation, this bit can be written
+ * only in Disable mode because it is blocked by hardware in other modes. See
+ * Section "Protocol Timing".
+ *
+ * Values:
+ * - 0b0 - The CAN engine clock source is the oscillator clock. Under this
+ *     condition, the oscillator clock frequency must be lower than the bus clock.
+ * - 0b1 - The CAN engine clock source is the peripheral clock.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_CLKSRC field. */
+#define CAN_RD_CTRL1_CLKSRC(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_CLKSRC_MASK) >> CAN_CTRL1_CLKSRC_SHIFT)
+#define CAN_BRD_CTRL1_CLKSRC(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_CLKSRC_SHIFT))
+
+/*! @brief Set the CLKSRC field to a new value. */
+#define CAN_WR_CTRL1_CLKSRC(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_CLKSRC_MASK, CAN_CTRL1_CLKSRC(value)))
+#define CAN_BWR_CTRL1_CLKSRC(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_CLKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
+ *
+ * This bit provides a mask for the Error Interrupt.
+ *
+ * Values:
+ * - 0b0 - Error interrupt disabled.
+ * - 0b1 - Error interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_ERRMSK field. */
+#define CAN_RD_CTRL1_ERRMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_ERRMSK_MASK) >> CAN_CTRL1_ERRMSK_SHIFT)
+#define CAN_BRD_CTRL1_ERRMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_ERRMSK_SHIFT))
+
+/*! @brief Set the ERRMSK field to a new value. */
+#define CAN_WR_CTRL1_ERRMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_ERRMSK_MASK, CAN_CTRL1_ERRMSK(value)))
+#define CAN_BWR_CTRL1_ERRMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_ERRMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
+ *
+ * This bit provides a mask for the Bus Off Interrupt.
+ *
+ * Values:
+ * - 0b0 - Bus Off interrupt disabled.
+ * - 0b1 - Bus Off interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_BOFFMSK field. */
+#define CAN_RD_CTRL1_BOFFMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_BOFFMSK_MASK) >> CAN_CTRL1_BOFFMSK_SHIFT)
+#define CAN_BRD_CTRL1_BOFFMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFMSK_SHIFT))
+
+/*! @brief Set the BOFFMSK field to a new value. */
+#define CAN_WR_CTRL1_BOFFMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_BOFFMSK_MASK, CAN_CTRL1_BOFFMSK(value)))
+#define CAN_BWR_CTRL1_BOFFMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
+ * time. The valid programmable values are 1-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 2 = (PSEG2 + 1) * Time-Quanta.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PSEG2 field. */
+#define CAN_RD_CTRL1_PSEG2(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PSEG2_MASK) >> CAN_CTRL1_PSEG2_SHIFT)
+#define CAN_BRD_CTRL1_PSEG2(base) (CAN_RD_CTRL1_PSEG2(base))
+
+/*! @brief Set the PSEG2 field to a new value. */
+#define CAN_WR_CTRL1_PSEG2(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PSEG2_MASK, CAN_CTRL1_PSEG2(value)))
+#define CAN_BWR_CTRL1_PSEG2(base, value) (CAN_WR_CTRL1_PSEG2(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 1 = (PSEG1 + 1) * Time-Quanta.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PSEG1 field. */
+#define CAN_RD_CTRL1_PSEG1(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PSEG1_MASK) >> CAN_CTRL1_PSEG1_SHIFT)
+#define CAN_BRD_CTRL1_PSEG1(base) (CAN_RD_CTRL1_PSEG1(base))
+
+/*! @brief Set the PSEG1 field to a new value. */
+#define CAN_WR_CTRL1_PSEG1(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PSEG1_MASK, CAN_CTRL1_PSEG1(value)))
+#define CAN_BWR_CTRL1_PSEG1(base, value) (CAN_WR_CTRL1_PSEG1(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field RJW[23:22] (RW)
+ *
+ * This 2-bit field defines the maximum number of time quanta that a bit time
+ * can be changed by one re-synchronization. One time quantum is equal to the
+ * Sclock period. The valid programmable values are 0-3. This field can be written
+ * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
+ * Width = RJW + 1.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_RJW field. */
+#define CAN_RD_CTRL1_RJW(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_RJW_MASK) >> CAN_CTRL1_RJW_SHIFT)
+#define CAN_BRD_CTRL1_RJW(base) (CAN_RD_CTRL1_RJW(base))
+
+/*! @brief Set the RJW field to a new value. */
+#define CAN_WR_CTRL1_RJW(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_RJW_MASK, CAN_CTRL1_RJW(value)))
+#define CAN_BWR_CTRL1_RJW(base, value) (CAN_WR_CTRL1_RJW(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
+ *
+ * This 8-bit field defines the ratio between the PE clock frequency and the
+ * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
+ * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
+ * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
+ * Sclock frequency equal to the PE clock frequency divided by 256. See Section
+ * "Protocol Timing". This field can be written only in Freeze mode because it is
+ * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
+ * (PRESDIV + 1)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PRESDIV field. */
+#define CAN_RD_CTRL1_PRESDIV(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PRESDIV_MASK) >> CAN_CTRL1_PRESDIV_SHIFT)
+#define CAN_BRD_CTRL1_PRESDIV(base) (CAN_RD_CTRL1_PRESDIV(base))
+
+/*! @brief Set the PRESDIV field to a new value. */
+#define CAN_WR_CTRL1_PRESDIV(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PRESDIV_MASK, CAN_CTRL1_PRESDIV(value)))
+#define CAN_BWR_CTRL1_PRESDIV(base, value) (CAN_WR_CTRL1_PRESDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_TIMER - Free Running Timer
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_TIMER - Free Running Timer (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register represents a 16-bit free running counter that can be read and
+ * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
+ * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
+ * defines the baud rate on the CAN bus. During a message transmission/reception,
+ * it increments by one for each bit that is received or transmitted. When there
+ * is no message on the bus, it counts using the previously programmed baud
+ * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
+ * timer value is captured when the second bit of the identifier field of any frame
+ * is on the CAN bus. This captured value is written into the Time Stamp entry
+ * in a message buffer after a successful reception or transmission of a message.
+ * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
+ * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
+ * can write to this register anytime. However, if the write occurs at the same
+ * time that the Timer is being reset by a reception in the first Mailbox, then
+ * the write value is discarded. Reading this register affects the Mailbox
+ * Unlocking procedure; see Section "Mailbox Lock Mechanism".
+ */
+/*!
+ * @name Constants and macros for entire CAN_TIMER register
+ */
+/*@{*/
+#define CAN_RD_TIMER(base)       (CAN_TIMER_REG(base))
+#define CAN_WR_TIMER(base, value) (CAN_TIMER_REG(base) = (value))
+#define CAN_RMW_TIMER(base, mask, value) (CAN_WR_TIMER(base, (CAN_RD_TIMER(base) & ~(mask)) | (value)))
+#define CAN_SET_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) |  (value)))
+#define CAN_CLR_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) & ~(value)))
+#define CAN_TOG_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_TIMER bitfields
+ */
+
+/*!
+ * @name Register CAN_TIMER, field TIMER[15:0] (RW)
+ *
+ * Contains the free-running counter value.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_TIMER_TIMER field. */
+#define CAN_RD_TIMER_TIMER(base) ((CAN_TIMER_REG(base) & CAN_TIMER_TIMER_MASK) >> CAN_TIMER_TIMER_SHIFT)
+#define CAN_BRD_TIMER_TIMER(base) (CAN_RD_TIMER_TIMER(base))
+
+/*! @brief Set the TIMER field to a new value. */
+#define CAN_WR_TIMER_TIMER(base, value) (CAN_RMW_TIMER(base, CAN_TIMER_TIMER_MASK, CAN_TIMER_TIMER(value)))
+#define CAN_BWR_TIMER_TIMER(base, value) (CAN_WR_TIMER_TIMER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RXMGMASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
+ * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
+ * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
+ * mask registers. This register can only be written in Freeze mode as it is
+ * blocked by hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXMGMASK register
+ */
+/*@{*/
+#define CAN_RD_RXMGMASK(base)    (CAN_RXMGMASK_REG(base))
+#define CAN_WR_RXMGMASK(base, value) (CAN_RXMGMASK_REG(base) = (value))
+#define CAN_RMW_RXMGMASK(base, mask, value) (CAN_WR_RXMGMASK(base, (CAN_RD_RXMGMASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) |  (value)))
+#define CAN_CLR_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) & ~(value)))
+#define CAN_TOG_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RX14MASK - Rx 14 Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RX14MASK - Rx 14 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX14MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
+ * is used to mask the filter fields of Message Buffer 14. This register can only
+ * be programmed while the module is in Freeze mode as it is blocked by hardware
+ * in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RX14MASK register
+ */
+/*@{*/
+#define CAN_RD_RX14MASK(base)    (CAN_RX14MASK_REG(base))
+#define CAN_WR_RX14MASK(base, value) (CAN_RX14MASK_REG(base) = (value))
+#define CAN_RMW_RX14MASK(base, mask, value) (CAN_WR_RX14MASK(base, (CAN_RD_RX14MASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) |  (value)))
+#define CAN_CLR_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) & ~(value)))
+#define CAN_TOG_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RX15MASK - Rx 15 Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RX15MASK - Rx 15 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX15MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
+ * is used to mask the filter fields of Message Buffer 15. This register can be
+ * programmed only while the module is in Freeze mode because it is blocked by
+ * hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RX15MASK register
+ */
+/*@{*/
+#define CAN_RD_RX15MASK(base)    (CAN_RX15MASK_REG(base))
+#define CAN_WR_RX15MASK(base, value) (CAN_RX15MASK_REG(base) = (value))
+#define CAN_RMW_RX15MASK(base, mask, value) (CAN_WR_RX15MASK(base, (CAN_RD_RX15MASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) |  (value)))
+#define CAN_CLR_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) & ~(value)))
+#define CAN_TOG_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ECR - Error Counter
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ECR - Error Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has two 8-bit fields reflecting the value of two FlexCAN error
+ * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
+ * (RXERRCNT field). The rules for increasing and decreasing these counters are
+ * described in the CAN protocol and are completely implemented in the FlexCAN
+ * module. Both counters are read-only except in Freeze mode, where they can be
+ * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
+ * for example, transmit Error Active or Error Passive flag, delay its
+ * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
+ * Off state. The following are the basic rules for FlexCAN bus state transitions:
+ * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
+ * 128, the FLTCONF field in the Error and Status Register is updated to reflect
+ * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
+ * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
+ * other already satisfies this condition, the FLTCONF field in the Error and
+ * Status Register is updated to reflect 'Error Active' state. If the value of
+ * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
+ * Register is updated to reflect 'Bus Off' state, and an interrupt may be
+ * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
+ * state, then TXERRCNT is cascaded together with another internal counter to count
+ * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
+ * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
+ * 11 such bits and then wraps around while incrementing the TXERRCNT. When
+ * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
+ * Register is updated to be 'Error Active' and both error counters are reset to zero.
+ * At any instance of dominant bit following a stream of less than 11
+ * consecutive recessive bits, the internal counter resets itself to zero without affecting
+ * the TXERRCNT value. If during system start-up, only one node is operating,
+ * then its TXERRCNT increases in each message it is trying to transmit, as a
+ * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
+ * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
+ * increment anymore by acknowledge errors. Therefore the device never goes to
+ * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
+ * is not incremented further, even if more errors are detected while being a
+ * receiver. At the next successful message reception, the counter is set to a value
+ * between 119 and 127 to resume to 'Error Active' state.
+ */
+/*!
+ * @name Constants and macros for entire CAN_ECR register
+ */
+/*@{*/
+#define CAN_RD_ECR(base)         (CAN_ECR_REG(base))
+#define CAN_WR_ECR(base, value)  (CAN_ECR_REG(base) = (value))
+#define CAN_RMW_ECR(base, mask, value) (CAN_WR_ECR(base, (CAN_RD_ECR(base) & ~(mask)) | (value)))
+#define CAN_SET_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) |  (value)))
+#define CAN_CLR_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) & ~(value)))
+#define CAN_TOG_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ECR bitfields
+ */
+
+/*!
+ * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ECR_TXERRCNT field. */
+#define CAN_RD_ECR_TXERRCNT(base) ((CAN_ECR_REG(base) & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT)
+#define CAN_BRD_ECR_TXERRCNT(base) (CAN_RD_ECR_TXERRCNT(base))
+
+/*! @brief Set the TXERRCNT field to a new value. */
+#define CAN_WR_ECR_TXERRCNT(base, value) (CAN_RMW_ECR(base, CAN_ECR_TXERRCNT_MASK, CAN_ECR_TXERRCNT(value)))
+#define CAN_BWR_ECR_TXERRCNT(base, value) (CAN_WR_ECR_TXERRCNT(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ECR_RXERRCNT field. */
+#define CAN_RD_ECR_RXERRCNT(base) ((CAN_ECR_REG(base) & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT)
+#define CAN_BRD_ECR_RXERRCNT(base) (CAN_RD_ECR_RXERRCNT(base))
+
+/*! @brief Set the RXERRCNT field to a new value. */
+#define CAN_WR_ECR_RXERRCNT(base, value) (CAN_RMW_ECR(base, CAN_ECR_RXERRCNT_MASK, CAN_ECR_RXERRCNT(value)))
+#define CAN_BWR_ECR_RXERRCNT(base, value) (CAN_WR_ECR_RXERRCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ESR1 - Error and Status 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ESR1 - Error and Status 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various error conditions, some general status of the
+ * device and it is the source of interrupts to the CPU. The CPU read action
+ * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
+ * that occurred since the last time the CPU read this register. Bits 9-3 are
+ * status bits. The following table shows the FlexCAN state variables and their
+ * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
+ * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
+ * Transmitting 1 0 0 1 Receiving
+ */
+/*!
+ * @name Constants and macros for entire CAN_ESR1 register
+ */
+/*@{*/
+#define CAN_RD_ESR1(base)        (CAN_ESR1_REG(base))
+#define CAN_WR_ESR1(base, value) (CAN_ESR1_REG(base) = (value))
+#define CAN_RMW_ESR1(base, mask, value) (CAN_WR_ESR1(base, (CAN_RD_ESR1(base) & ~(mask)) | (value)))
+#define CAN_SET_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) |  (value)))
+#define CAN_CLR_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) & ~(value)))
+#define CAN_TOG_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ESR1 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR1, field WAKINT[0] (W1C)
+ *
+ * This field applies when FlexCAN is in low-power mode under Self Wake Up
+ * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
+ * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
+ * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
+ * is masked. The CPU must clear this flag before disabling the bit. Otherwise
+ * it will be set when the SLFWAK is set again. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - Indicates a recessive to dominant transition was received on the CAN
+ *     bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_WAKINT field. */
+#define CAN_RD_ESR1_WAKINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_WAKINT_MASK) >> CAN_ESR1_WAKINT_SHIFT)
+#define CAN_BRD_ESR1_WAKINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_WAKINT_SHIFT))
+
+/*! @brief Set the WAKINT field to a new value. */
+#define CAN_WR_ESR1_WAKINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_WAKINT(value)))
+#define CAN_BWR_ESR1_WAKINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_WAKINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field ERRINT[1] (W1C)
+ *
+ * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
+ * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
+ * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - Indicates setting of any Error Bit in the Error and Status Register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_ERRINT field. */
+#define CAN_RD_ESR1_ERRINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_ERRINT_MASK) >> CAN_ESR1_ERRINT_SHIFT)
+#define CAN_BRD_ESR1_ERRINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ERRINT_SHIFT))
+
+/*! @brief Set the ERRINT field to a new value. */
+#define CAN_WR_ESR1_ERRINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_ERRINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_ERRINT(value)))
+#define CAN_BWR_ESR1_ERRINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ERRINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
+ *
+ * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
+ * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
+ * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - FlexCAN module entered Bus Off state.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BOFFINT field. */
+#define CAN_RD_ESR1_BOFFINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BOFFINT_MASK) >> CAN_ESR1_BOFFINT_SHIFT)
+#define CAN_BRD_ESR1_BOFFINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BOFFINT_SHIFT))
+
+/*! @brief Set the BOFFINT field to a new value. */
+#define CAN_WR_ESR1_BOFFINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_BOFFINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_BOFFINT(value)))
+#define CAN_BWR_ESR1_BOFFINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BOFFINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RX[3] (RO)
+ *
+ * This bit indicates if FlexCAN is receiving a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not receiving a message.
+ * - 0b1 - FlexCAN is receiving a message.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RX field. */
+#define CAN_RD_ESR1_RX(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RX_MASK) >> CAN_ESR1_RX_SHIFT)
+#define CAN_BRD_ESR1_RX(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
+ *
+ * This 2-bit field indicates the Confinement State of the FlexCAN module. If
+ * the LOM bit in the Control Register is asserted, after some delay that depends
+ * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
+ * same delay affects the way how FLTCONF reflects an update to ECR register by
+ * the CPU. It may be necessary up to one CAN bit time to get them coherent
+ * again. Because the Control Register is not affected by soft reset, the FLTCONF
+ * field will not be affected by soft reset if the LOM bit is asserted.
+ *
+ * Values:
+ * - 0b00 - Error Active
+ * - 0b01 - Error Passive
+ * - 0b1x - Bus Off
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_FLTCONF field. */
+#define CAN_RD_ESR1_FLTCONF(base) ((CAN_ESR1_REG(base) & CAN_ESR1_FLTCONF_MASK) >> CAN_ESR1_FLTCONF_SHIFT)
+#define CAN_BRD_ESR1_FLTCONF(base) (CAN_RD_ESR1_FLTCONF(base))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TX[6] (RO)
+ *
+ * This bit indicates if FlexCAN is transmitting a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not transmitting a message.
+ * - 0b1 - FlexCAN is transmitting a message.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TX field. */
+#define CAN_RD_ESR1_TX(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TX_MASK) >> CAN_ESR1_TX_SHIFT)
+#define CAN_BRD_ESR1_TX(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field IDLE[7] (RO)
+ *
+ * This bit indicates when CAN bus is in IDLE state. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - CAN bus is now IDLE.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_IDLE field. */
+#define CAN_RD_ESR1_IDLE(base) ((CAN_ESR1_REG(base) & CAN_ESR1_IDLE_MASK) >> CAN_ESR1_IDLE_SHIFT)
+#define CAN_BRD_ESR1_IDLE(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RXWRN[8] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * reception. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - RXERRCNT is greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RXWRN field. */
+#define CAN_RD_ESR1_RXWRN(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RXWRN_MASK) >> CAN_ESR1_RXWRN_SHIFT)
+#define CAN_BRD_ESR1_RXWRN(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RXWRN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TXWRN[9] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * transmission. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - TXERRCNT is greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TXWRN field. */
+#define CAN_RD_ESR1_TXWRN(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TXWRN_MASK) >> CAN_ESR1_TXWRN_SHIFT)
+#define CAN_BRD_ESR1_TXWRN(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TXWRN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field STFERR[10] (RO)
+ *
+ * This bit indicates that a Stuffing Error has been etected.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A Stuffing Error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_STFERR field. */
+#define CAN_RD_ESR1_STFERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_STFERR_MASK) >> CAN_ESR1_STFERR_SHIFT)
+#define CAN_BRD_ESR1_STFERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_STFERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field FRMERR[11] (RO)
+ *
+ * This bit indicates that a Form Error has been detected by the receiver node,
+ * that is, a fixed-form bit field contains at least one illegal bit.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A Form Error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_FRMERR field. */
+#define CAN_RD_ESR1_FRMERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_FRMERR_MASK) >> CAN_ESR1_FRMERR_SHIFT)
+#define CAN_BRD_ESR1_FRMERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_FRMERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field CRCERR[12] (RO)
+ *
+ * This bit indicates that a CRC Error has been detected by the receiver node,
+ * that is, the calculated CRC is different from the received.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A CRC error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_CRCERR field. */
+#define CAN_RD_ESR1_CRCERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_CRCERR_MASK) >> CAN_ESR1_CRCERR_SHIFT)
+#define CAN_BRD_ESR1_CRCERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_CRCERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field ACKERR[13] (RO)
+ *
+ * This bit indicates that an Acknowledge Error has been detected by the
+ * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - An ACK error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_ACKERR field. */
+#define CAN_RD_ESR1_ACKERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_ACKERR_MASK) >> CAN_ESR1_ACKERR_SHIFT)
+#define CAN_BRD_ESR1_ACKERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ACKERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - At least one bit sent as dominant is received as recessive.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BIT0ERR field. */
+#define CAN_RD_ESR1_BIT0ERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BIT0ERR_MASK) >> CAN_ESR1_BIT0ERR_SHIFT)
+#define CAN_BRD_ESR1_BIT0ERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BIT0ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message. This bit is not set by a transmitter in case of
+ * arbitration field or ACK slot, or in case of a node sending a passive error
+ * flag that detects dominant bits.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - At least one bit sent as recessive is received as dominant.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BIT1ERR field. */
+#define CAN_RD_ESR1_BIT1ERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BIT1ERR_MASK) >> CAN_ESR1_BIT1ERR_SHIFT)
+#define CAN_BRD_ESR1_BIT1ERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BIT1ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
+ * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
+ * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
+ * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - The Rx error counter transitioned from less than 96 to greater than
+ *     or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RWRNINT field. */
+#define CAN_RD_ESR1_RWRNINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RWRNINT_MASK) >> CAN_ESR1_RWRNINT_SHIFT)
+#define CAN_BRD_ESR1_RWRNINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RWRNINT_SHIFT))
+
+/*! @brief Set the RWRNINT field to a new value. */
+#define CAN_WR_ESR1_RWRNINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_RWRNINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_RWRNINT(value)))
+#define CAN_BWR_ESR1_RWRNINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RWRNINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
+ * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
+ * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
+ * is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This flag is not generated during Bus Off state. This bit is not
+ * updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - The Tx error counter transitioned from less than 96 to greater than
+ *     or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TWRNINT field. */
+#define CAN_RD_ESR1_TWRNINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TWRNINT_MASK) >> CAN_ESR1_TWRNINT_SHIFT)
+#define CAN_BRD_ESR1_TWRNINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TWRNINT_SHIFT))
+
+/*! @brief Set the TWRNINT field to a new value. */
+#define CAN_WR_ESR1_TWRNINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_TWRNINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK), CAN_ESR1_TWRNINT(value)))
+#define CAN_BWR_ESR1_TWRNINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TWRNINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field SYNCH[18] (RO)
+ *
+ * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
+ * bus and able to participate in the communication process. It is set and
+ * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not synchronized to the CAN bus.
+ * - 0b1 - FlexCAN is synchronized to the CAN bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_SYNCH field. */
+#define CAN_RD_ESR1_SYNCH(base) ((CAN_ESR1_REG(base) & CAN_ESR1_SYNCH_MASK) >> CAN_ESR1_SYNCH_SHIFT)
+#define CAN_BRD_ESR1_SYNCH(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_SYNCH_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_IMASK1 - Interrupt Masks 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_IMASK1 - Interrupt Masks 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register allows any number of a range of the 32 Message Buffer
+ * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
+ * bit per buffer, enabling the CPU to determine which buffer generates an
+ * interrupt after a successful transmission or reception, that is, when the
+ * corresponding IFLAG1 bit is set.
+ */
+/*!
+ * @name Constants and macros for entire CAN_IMASK1 register
+ */
+/*@{*/
+#define CAN_RD_IMASK1(base)      (CAN_IMASK1_REG(base))
+#define CAN_WR_IMASK1(base, value) (CAN_IMASK1_REG(base) = (value))
+#define CAN_RMW_IMASK1(base, mask, value) (CAN_WR_IMASK1(base, (CAN_RD_IMASK1(base) & ~(mask)) | (value)))
+#define CAN_SET_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) |  (value)))
+#define CAN_CLR_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) & ~(value)))
+#define CAN_TOG_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_IFLAG1 - Interrupt Flags 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the flags for the 32 Message Buffer interrupts for MB31
+ * to MB0. It contains one interrupt flag bit per buffer. Each successful
+ * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
+ * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
+ * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
+ * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
+ * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
+ * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
+ * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
+ * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
+ * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
+ * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
+ * the FIFO flags must be cleared. The same care must be taken when an RFFN
+ * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
+ * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
+ * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
+ * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
+ * they will remain set and be inconsistent with the number of MBs available.
+ */
+/*!
+ * @name Constants and macros for entire CAN_IFLAG1 register
+ */
+/*@{*/
+#define CAN_RD_IFLAG1(base)      (CAN_IFLAG1_REG(base))
+#define CAN_WR_IFLAG1(base, value) (CAN_IFLAG1_REG(base) = (value))
+#define CAN_RMW_IFLAG1(base, mask, value) (CAN_WR_IFLAG1(base, (CAN_RD_IFLAG1(base) & ~(mask)) | (value)))
+#define CAN_SET_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) |  (value)))
+#define CAN_CLR_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) & ~(value)))
+#define CAN_TOG_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_IFLAG1 bitfields
+ */
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
+ * set.
+ *
+ * Values:
+ * - 0b0 - The corresponding buffer has no occurrence of successfully completed
+ *     transmission or reception when MCR[RFEN]=0.
+ * - 0b1 - The corresponding buffer has successfully completed transmission or
+ *     reception when MCR[RFEN]=0.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF0I field. */
+#define CAN_RD_IFLAG1_BUF0I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF0I_MASK) >> CAN_IFLAG1_BUF0I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF0I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF0I_SHIFT))
+
+/*! @brief Set the BUF0I field to a new value. */
+#define CAN_WR_IFLAG1_BUF0I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF0I(value)))
+#define CAN_BWR_IFLAG1_BUF0I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF0I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
+ * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
+ * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
+ * when MCR[RFEN] is set.
+ *
+ * Values:
+ * - 0b0000 - The corresponding buffer has no occurrence of successfully
+ *     completed transmission or reception when MCR[RFEN]=0.
+ * - 0b0001 - The corresponding buffer has successfully completed transmission
+ *     or reception when MCR[RFEN]=0.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field. */
+#define CAN_RD_IFLAG1_BUF4TO1I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF4TO1I_MASK) >> CAN_IFLAG1_BUF4TO1I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF4TO1I(base) (CAN_RD_IFLAG1_BUF4TO1I(base))
+
+/*! @brief Set the BUF4TO1I field to a new value. */
+#define CAN_WR_IFLAG1_BUF4TO1I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF4TO1I(value)))
+#define CAN_BWR_IFLAG1_BUF4TO1I(base, value) (CAN_WR_IFLAG1_BUF4TO1I(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
+ * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
+ * least one frame is available to be read from the Rx FIFO.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB5 completing transmission/reception when
+ *     MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
+ * - 0b1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
+ *     available in the Rx FIFO when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF5I field. */
+#define CAN_RD_IFLAG1_BUF5I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF5I_MASK) >> CAN_IFLAG1_BUF5I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF5I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF5I_SHIFT))
+
+/*! @brief Set the BUF5I field to a new value. */
+#define CAN_WR_IFLAG1_BUF5I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF5I(value)))
+#define CAN_BWR_IFLAG1_BUF5I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF5I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
+ * when MCR[RFEN] is set. In this case, the flag indicates when the number of
+ * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
+ * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
+ * cleared while the number of unread messages is greater than 4, it does not
+ * assert again until the number of unread messages within the Rx FIFO is decreased
+ * to be equal to or less than 4.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB6 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
+ * - 0b1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     almost full when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF6I field. */
+#define CAN_RD_IFLAG1_BUF6I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF6I_MASK) >> CAN_IFLAG1_BUF6I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF6I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF6I_SHIFT))
+
+/*! @brief Set the BUF6I field to a new value. */
+#define CAN_WR_IFLAG1_BUF6I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF6I(value)))
+#define CAN_BWR_IFLAG1_BUF6I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF6I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
+ * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
+ * because the Rx FIFO is full. Note that the flag will not be asserted when the
+ * Rx FIFO is full and the message was captured by a Mailbox.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB7 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
+ * - 0b1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     overflow when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF7I field. */
+#define CAN_RD_IFLAG1_BUF7I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF7I_MASK) >> CAN_IFLAG1_BUF7I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF7I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF7I_SHIFT))
+
+/*! @brief Set the BUF7I field to a new value. */
+#define CAN_WR_IFLAG1_BUF7I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF7I(value)))
+#define CAN_BWR_IFLAG1_BUF7I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF7I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
+ *
+ * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
+ * MB8.
+ *
+ * Values:
+ * - 0b000000000000000000000000 - The corresponding buffer has no occurrence of
+ *     successfully completed transmission or reception.
+ * - 0b000000000000000000000001 - The corresponding buffer has successfully
+ *     completed transmission or reception.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field. */
+#define CAN_RD_IFLAG1_BUF31TO8I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF31TO8I_MASK) >> CAN_IFLAG1_BUF31TO8I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF31TO8I(base) (CAN_RD_IFLAG1_BUF31TO8I(base))
+
+/*! @brief Set the BUF31TO8I field to a new value. */
+#define CAN_WR_IFLAG1_BUF31TO8I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF31TO8I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK), CAN_IFLAG1_BUF31TO8I(value)))
+#define CAN_BWR_IFLAG1_BUF31TO8I(base, value) (CAN_WR_IFLAG1_BUF31TO8I(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CTRL2 - Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CTRL2 - Control 2 register (RW)
+ *
+ * Reset value: 0x00B00000U
+ *
+ * This register contains control bits for CAN errors, FIFO features, and mode
+ * selection.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CTRL2 register
+ */
+/*@{*/
+#define CAN_RD_CTRL2(base)       (CAN_CTRL2_REG(base))
+#define CAN_WR_CTRL2(base, value) (CAN_CTRL2_REG(base) = (value))
+#define CAN_RMW_CTRL2(base, mask, value) (CAN_WR_CTRL2(base, (CAN_RD_CTRL2(base) & ~(mask)) | (value)))
+#define CAN_SET_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) |  (value)))
+#define CAN_CLR_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) & ~(value)))
+#define CAN_TOG_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CTRL2 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL2, field EACEN[16] (RW)
+ *
+ * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
+ * filters with their corresponding bits in the incoming frame by the matching
+ * process. This bit does not affect matching for Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
+ *     compared despite mask bits.
+ * - 0b1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit
+ *     with their corresponding bits within the incoming frame. Mask bits do apply.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_EACEN field. */
+#define CAN_RD_CTRL2_EACEN(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_EACEN_MASK) >> CAN_CTRL2_EACEN_SHIFT)
+#define CAN_BRD_CTRL2_EACEN(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_EACEN_SHIFT))
+
+/*! @brief Set the EACEN field to a new value. */
+#define CAN_WR_CTRL2_EACEN(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_EACEN_MASK, CAN_CTRL2_EACEN(value)))
+#define CAN_BWR_CTRL2_EACEN(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_EACEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field RRS[17] (RW)
+ *
+ * If this bit is asserted Remote Request Frame is submitted to a matching
+ * process and stored in the corresponding Message Buffer in the same fashion of a
+ * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
+ * negated the Remote Request Frame is submitted to a matching process and an
+ * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
+ * is found with the same ID. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Remote Response Frame is generated.
+ * - 0b1 - Remote Request Frame is stored.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_RRS field. */
+#define CAN_RD_CTRL2_RRS(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_RRS_MASK) >> CAN_CTRL2_RRS_SHIFT)
+#define CAN_BRD_CTRL2_RRS(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_RRS_SHIFT))
+
+/*! @brief Set the RRS field to a new value. */
+#define CAN_WR_CTRL2_RRS(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_RRS_MASK, CAN_CTRL2_RRS(value)))
+#define CAN_BWR_CTRL2_RRS(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_RRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field MRP[18] (RW)
+ *
+ * If this bit is set the matching process starts from the Mailboxes and if no
+ * match occurs the matching continues on the Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Matching starts from Rx FIFO and continues on Mailboxes.
+ * - 0b1 - Matching starts from Mailboxes and continues on Rx FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_MRP field. */
+#define CAN_RD_CTRL2_MRP(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_MRP_MASK) >> CAN_CTRL2_MRP_SHIFT)
+#define CAN_BRD_CTRL2_MRP(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_MRP_SHIFT))
+
+/*! @brief Set the MRP field to a new value. */
+#define CAN_WR_CTRL2_MRP(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_MRP_MASK, CAN_CTRL2_MRP(value)))
+#define CAN_BWR_CTRL2_MRP(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_MRP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field TASD[23:19] (RW)
+ *
+ * This 5-bit field indicates how many CAN bits the Tx arbitration process start
+ * point can be delayed from the first bit of CRC field on CAN bus. This field
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes. This field is useful to optimize the transmit performance based on
+ * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
+ * The duration of an arbitration process, in terms of CAN bits, is directly
+ * proportional to the number of available MBs and CAN baud rate and inversely
+ * proportional to the peripheral clock frequency. The optimal arbitration timing is
+ * that in which the last MB is scanned right before the first bit of the
+ * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
+ * clock ratio is high and the CAN baud rate is low then the arbitration can be
+ * delayed and vice-versa. If TASD is 0 then the arbitration start is not
+ * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
+ * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
+ * the CPU can configure a Tx MB later and less time is reserved for
+ * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
+ * to find winner MBs in time to compete with other nodes for the CAN bus. If the
+ * arbitration ends too much time before the first bit of Intermission field then
+ * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
+ * not the best to be transmitted. The optimal configuration for TASD can be
+ * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
+ * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
+ * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
+ * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
+ * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
+ * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
+ * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
+ * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
+ * Timing" for more details.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_TASD field. */
+#define CAN_RD_CTRL2_TASD(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_TASD_MASK) >> CAN_CTRL2_TASD_SHIFT)
+#define CAN_BRD_CTRL2_TASD(base) (CAN_RD_CTRL2_TASD(base))
+
+/*! @brief Set the TASD field to a new value. */
+#define CAN_WR_CTRL2_TASD(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_TASD_MASK, CAN_CTRL2_TASD(value)))
+#define CAN_BWR_CTRL2_TASD(base, value) (CAN_WR_CTRL2_TASD(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
+ *
+ * This 4-bit field defines the number of Rx FIFO filters, as shown in the
+ * following table. The maximum selectable number of filters is determined by the MCU.
+ * This field can only be written in Freeze mode as it is blocked by hardware in
+ * other modes. This field must not be programmed with values that make the
+ * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
+ * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
+ * a memory space equivalent to two Message Buffers which means that the more
+ * filters are implemented the less Mailboxes will be available. Considering that
+ * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
+ * be programmed with a value correponding to a number of filters not greater
+ * than the number of available memory words which can be calculated as follows:
+ * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
+ * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
+ * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
+ * SETUP_MB value (memory space available) the exceeding ones will not be functional.
+ * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
+ * Filter Table Remaining Available MailboxesThe number of the last remaining
+ * available mailboxes is defined by the least value between the parameter
+ * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
+ * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
+ * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
+ * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
+ * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
+ * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
+ * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
+ * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
+ * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
+ * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
+ * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
+ * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
+ * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
+ * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
+ * 0-37 MB 38-63 Elements 0-31 Elements 32-127
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_RFFN field. */
+#define CAN_RD_CTRL2_RFFN(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT)
+#define CAN_BRD_CTRL2_RFFN(base) (CAN_RD_CTRL2_RFFN(base))
+
+/*! @brief Set the RFFN field to a new value. */
+#define CAN_WR_CTRL2_RFFN(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_RFFN_MASK, CAN_CTRL2_RFFN(value)))
+#define CAN_BWR_CTRL2_RFFN(base, value) (CAN_WR_CTRL2_RFFN(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
+ *
+ * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
+ * can only be written in Freeze mode and has no effect out of Freeze mode.
+ *
+ * Values:
+ * - 0b0 - Maintain the write access restrictions.
+ * - 0b1 - Enable unrestricted write access to FlexCAN memory.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_WRMFRZ field. */
+#define CAN_RD_CTRL2_WRMFRZ(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_WRMFRZ_MASK) >> CAN_CTRL2_WRMFRZ_SHIFT)
+#define CAN_BRD_CTRL2_WRMFRZ(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_WRMFRZ_SHIFT))
+
+/*! @brief Set the WRMFRZ field to a new value. */
+#define CAN_WR_CTRL2_WRMFRZ(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_WRMFRZ_MASK, CAN_CTRL2_WRMFRZ(value)))
+#define CAN_BWR_CTRL2_WRMFRZ(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_WRMFRZ_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ESR2 - Error and Status 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ESR2 - Error and Status 2 register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various interrupt flags and some general status.
+ */
+/*!
+ * @name Constants and macros for entire CAN_ESR2 register
+ */
+/*@{*/
+#define CAN_RD_ESR2(base)        (CAN_ESR2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ESR2 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR2, field IMB[13] (RO)
+ *
+ * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
+ * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
+ * following cases: During arbitration, if an LPTM is found and it is inactive. If
+ * IMB is not asserted and a frame is transmitted successfully. This bit is
+ * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
+ * mechanism have the following behavior: if an MB is successfully transmitted and
+ * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
+ * the index related to the MB just transmitted is loaded into ESR2[LPTM].
+ *
+ * Values:
+ * - 0b0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
+ * - 0b1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox.
+ *     LPTM content is the number of the first one.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_IMB field. */
+#define CAN_RD_ESR2_IMB(base) ((CAN_ESR2_REG(base) & CAN_ESR2_IMB_MASK) >> CAN_ESR2_IMB_SHIFT)
+#define CAN_BRD_ESR2_IMB(base) (BITBAND_ACCESS32(&CAN_ESR2_REG(base), CAN_ESR2_IMB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR2, field VPS[14] (RO)
+ *
+ * This bit indicates whether IMB and LPTM contents are currently valid or not.
+ * VPS is asserted upon every complete Tx arbitration process unless the CPU
+ * writes to Control and Status word of a Mailbox that has already been scanned, that
+ * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
+ * If there is no inactive Mailbox and only one Tx Mailbox that is being
+ * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
+ * arbitration process or upon a write to Control and Status word of any Mailbox.
+ * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
+ * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
+ * in C/S of a MB that is being transmitted (pending abort), or any write attempt
+ * into a Tx MB with IFLAG set is blocked.
+ *
+ * Values:
+ * - 0b0 - Contents of IMB and LPTM are invalid.
+ * - 0b1 - Contents of IMB and LPTM are valid.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_VPS field. */
+#define CAN_RD_ESR2_VPS(base) ((CAN_ESR2_REG(base) & CAN_ESR2_VPS_MASK) >> CAN_ESR2_VPS_SHIFT)
+#define CAN_BRD_ESR2_VPS(base) (BITBAND_ACCESS32(&CAN_ESR2_REG(base), CAN_ESR2_VPS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR2, field LPTM[22:16] (RO)
+ *
+ * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
+ * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
+ * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
+ * negated then the Mailbox indicated is the one that has the greatest arbitration
+ * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
+ * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
+ * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
+ * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
+ * updated with its Mailbox number.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_LPTM field. */
+#define CAN_RD_ESR2_LPTM(base) ((CAN_ESR2_REG(base) & CAN_ESR2_LPTM_MASK) >> CAN_ESR2_LPTM_SHIFT)
+#define CAN_BRD_ESR2_LPTM(base) (CAN_RD_ESR2_LPTM(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CRCR - CRC Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CRCR - CRC Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides information about the CRC of transmitted messages.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CRCR register
+ */
+/*@{*/
+#define CAN_RD_CRCR(base)        (CAN_CRCR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CRCR bitfields
+ */
+
+/*!
+ * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
+ *
+ * This field indicates the CRC value of the last message transmitted. This
+ * field is updated at the same time the Tx Interrupt Flag is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CRCR_TXCRC field. */
+#define CAN_RD_CRCR_TXCRC(base) ((CAN_CRCR_REG(base) & CAN_CRCR_TXCRC_MASK) >> CAN_CRCR_TXCRC_SHIFT)
+#define CAN_BRD_CRCR_TXCRC(base) (CAN_RD_CRCR_TXCRC(base))
+/*@}*/
+
+/*!
+ * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
+ *
+ * This field indicates the number of the Mailbox corresponding to the value in
+ * TXCRC field.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CRCR_MBCRC field. */
+#define CAN_RD_CRCR_MBCRC(base) ((CAN_CRCR_REG(base) & CAN_CRCR_MBCRC_MASK) >> CAN_CRCR_MBCRC_SHIFT)
+#define CAN_BRD_CRCR_MBCRC(base) (CAN_RD_CRCR_MBCRC(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXFGMASK - Rx FIFO Global Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
+ * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
+ * according to CTRL2[RFFN] field setting. This register can only be written in
+ * Freeze mode as it is blocked by hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXFGMASK register
+ */
+/*@{*/
+#define CAN_RD_RXFGMASK(base)    (CAN_RXFGMASK_REG(base))
+#define CAN_WR_RXFGMASK(base, value) (CAN_RXFGMASK_REG(base) = (value))
+#define CAN_RMW_RXFGMASK(base, mask, value) (CAN_WR_RXFGMASK(base, (CAN_RD_RXFGMASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) |  (value)))
+#define CAN_CLR_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) & ~(value)))
+#define CAN_TOG_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXFIR - Rx FIFO Information Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXFIR - Rx FIFO Information Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFIR provides information on Rx FIFO. This register is the port through
+ * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
+ * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
+ * well as its output is updated whenever the output of the Rx FIFO is updated
+ * with the next message. See Section "Rx FIFO" for instructions on reading this
+ * register.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXFIR register
+ */
+/*@{*/
+#define CAN_RD_RXFIR(base)       (CAN_RXFIR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_RXFIR bitfields
+ */
+
+/*!
+ * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
+ *
+ * This field indicates which Identifier Acceptance Filter was hit by the
+ * received message that is in the output of the Rx FIFO. If multiple filters match the
+ * incoming message ID then the first matching IDAF found (lowest number) by the
+ * matching process is indicated. This field is valid only while the
+ * IFLAG[BUF5I] is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_RXFIR_IDHIT field. */
+#define CAN_RD_RXFIR_IDHIT(base) ((CAN_RXFIR_REG(base) & CAN_RXFIR_IDHIT_MASK) >> CAN_RXFIR_IDHIT_SHIFT)
+#define CAN_BRD_RXFIR_IDHIT(base) (CAN_RD_RXFIR_IDHIT(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CS - Message Buffer 0 CS Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CS - Message Buffer 0 CS Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_CS register
+ */
+/*@{*/
+#define CAN_RD_CS(base, index)   (CAN_CS_REG(base, index))
+#define CAN_WR_CS(base, index, value) (CAN_CS_REG(base, index) = (value))
+#define CAN_RMW_CS(base, index, mask, value) (CAN_WR_CS(base, index, (CAN_RD_CS(base, index) & ~(mask)) | (value)))
+#define CAN_SET_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) |  (value)))
+#define CAN_CLR_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) & ~(value)))
+#define CAN_TOG_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CS bitfields
+ */
+
+/*!
+ * @name Register CAN_CS, field TIME_STAMP[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_TIME_STAMP field. */
+#define CAN_RD_CS_TIME_STAMP(base, index) ((CAN_CS_REG(base, index) & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT)
+#define CAN_BRD_CS_TIME_STAMP(base, index) (CAN_RD_CS_TIME_STAMP(base, index))
+
+/*! @brief Set the TIME_STAMP field to a new value. */
+#define CAN_WR_CS_TIME_STAMP(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_TIME_STAMP_MASK, CAN_CS_TIME_STAMP(value)))
+#define CAN_BWR_CS_TIME_STAMP(base, index, value) (CAN_WR_CS_TIME_STAMP(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field DLC[19:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_DLC field. */
+#define CAN_RD_CS_DLC(base, index) ((CAN_CS_REG(base, index) & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT)
+#define CAN_BRD_CS_DLC(base, index) (CAN_RD_CS_DLC(base, index))
+
+/*! @brief Set the DLC field to a new value. */
+#define CAN_WR_CS_DLC(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_DLC_MASK, CAN_CS_DLC(value)))
+#define CAN_BWR_CS_DLC(base, index, value) (CAN_WR_CS_DLC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field RTR[20] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_RTR field. */
+#define CAN_RD_CS_RTR(base, index) ((CAN_CS_REG(base, index) & CAN_CS_RTR_MASK) >> CAN_CS_RTR_SHIFT)
+#define CAN_BRD_CS_RTR(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_RTR_SHIFT))
+
+/*! @brief Set the RTR field to a new value. */
+#define CAN_WR_CS_RTR(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_RTR_MASK, CAN_CS_RTR(value)))
+#define CAN_BWR_CS_RTR(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_RTR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field IDE[21] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_IDE field. */
+#define CAN_RD_CS_IDE(base, index) ((CAN_CS_REG(base, index) & CAN_CS_IDE_MASK) >> CAN_CS_IDE_SHIFT)
+#define CAN_BRD_CS_IDE(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_IDE_SHIFT))
+
+/*! @brief Set the IDE field to a new value. */
+#define CAN_WR_CS_IDE(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_IDE_MASK, CAN_CS_IDE(value)))
+#define CAN_BWR_CS_IDE(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_IDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field SRR[22] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_SRR field. */
+#define CAN_RD_CS_SRR(base, index) ((CAN_CS_REG(base, index) & CAN_CS_SRR_MASK) >> CAN_CS_SRR_SHIFT)
+#define CAN_BRD_CS_SRR(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_SRR_SHIFT))
+
+/*! @brief Set the SRR field to a new value. */
+#define CAN_WR_CS_SRR(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_SRR_MASK, CAN_CS_SRR(value)))
+#define CAN_BWR_CS_SRR(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_SRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field CODE[27:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_CODE field. */
+#define CAN_RD_CS_CODE(base, index) ((CAN_CS_REG(base, index) & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT)
+#define CAN_BRD_CS_CODE(base, index) (CAN_RD_CS_CODE(base, index))
+
+/*! @brief Set the CODE field to a new value. */
+#define CAN_WR_CS_CODE(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_CODE_MASK, CAN_CS_CODE(value)))
+#define CAN_BWR_CS_CODE(base, index, value) (CAN_WR_CS_CODE(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ID - Message Buffer 0 ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ID - Message Buffer 0 ID Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_ID register
+ */
+/*@{*/
+#define CAN_RD_ID(base, index)   (CAN_ID_REG(base, index))
+#define CAN_WR_ID(base, index, value) (CAN_ID_REG(base, index) = (value))
+#define CAN_RMW_ID(base, index, mask, value) (CAN_WR_ID(base, index, (CAN_RD_ID(base, index) & ~(mask)) | (value)))
+#define CAN_SET_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) |  (value)))
+#define CAN_CLR_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) & ~(value)))
+#define CAN_TOG_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ID bitfields
+ */
+
+/*!
+ * @name Register CAN_ID, field EXT[17:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_EXT field. */
+#define CAN_RD_ID_EXT(base, index) ((CAN_ID_REG(base, index) & CAN_ID_EXT_MASK) >> CAN_ID_EXT_SHIFT)
+#define CAN_BRD_ID_EXT(base, index) (CAN_RD_ID_EXT(base, index))
+
+/*! @brief Set the EXT field to a new value. */
+#define CAN_WR_ID_EXT(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_EXT_MASK, CAN_ID_EXT(value)))
+#define CAN_BWR_ID_EXT(base, index, value) (CAN_WR_ID_EXT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ID, field STD[28:18] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_STD field. */
+#define CAN_RD_ID_STD(base, index) ((CAN_ID_REG(base, index) & CAN_ID_STD_MASK) >> CAN_ID_STD_SHIFT)
+#define CAN_BRD_ID_STD(base, index) (CAN_RD_ID_STD(base, index))
+
+/*! @brief Set the STD field to a new value. */
+#define CAN_WR_ID_STD(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_STD_MASK, CAN_ID_STD(value)))
+#define CAN_BWR_ID_STD(base, index, value) (CAN_WR_ID_STD(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ID, field PRIO[31:29] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_PRIO field. */
+#define CAN_RD_ID_PRIO(base, index) ((CAN_ID_REG(base, index) & CAN_ID_PRIO_MASK) >> CAN_ID_PRIO_SHIFT)
+#define CAN_BRD_ID_PRIO(base, index) (CAN_RD_ID_PRIO(base, index))
+
+/*! @brief Set the PRIO field to a new value. */
+#define CAN_WR_ID_PRIO(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_PRIO_MASK, CAN_ID_PRIO(value)))
+#define CAN_BWR_ID_PRIO(base, index, value) (CAN_WR_ID_PRIO(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_WORD0 - Message Buffer 0 WORD0 Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_WORD0 - Message Buffer 0 WORD0 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_WORD0 register
+ */
+/*@{*/
+#define CAN_RD_WORD0(base, index) (CAN_WORD0_REG(base, index))
+#define CAN_WR_WORD0(base, index, value) (CAN_WORD0_REG(base, index) = (value))
+#define CAN_RMW_WORD0(base, index, mask, value) (CAN_WR_WORD0(base, index, (CAN_RD_WORD0(base, index) & ~(mask)) | (value)))
+#define CAN_SET_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) |  (value)))
+#define CAN_CLR_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) & ~(value)))
+#define CAN_TOG_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_WORD0 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_3[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_3 field. */
+#define CAN_RD_WORD0_DATA_BYTE_3(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_3_MASK) >> CAN_WORD0_DATA_BYTE_3_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_3(base, index) (CAN_RD_WORD0_DATA_BYTE_3(base, index))
+
+/*! @brief Set the DATA_BYTE_3 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_3(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_3_MASK, CAN_WORD0_DATA_BYTE_3(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_3(base, index, value) (CAN_WR_WORD0_DATA_BYTE_3(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_2[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_2 field. */
+#define CAN_RD_WORD0_DATA_BYTE_2(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_2_MASK) >> CAN_WORD0_DATA_BYTE_2_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_2(base, index) (CAN_RD_WORD0_DATA_BYTE_2(base, index))
+
+/*! @brief Set the DATA_BYTE_2 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_2(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_2_MASK, CAN_WORD0_DATA_BYTE_2(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_2(base, index, value) (CAN_WR_WORD0_DATA_BYTE_2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_1[23:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_1 field. */
+#define CAN_RD_WORD0_DATA_BYTE_1(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_1_MASK) >> CAN_WORD0_DATA_BYTE_1_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_1(base, index) (CAN_RD_WORD0_DATA_BYTE_1(base, index))
+
+/*! @brief Set the DATA_BYTE_1 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_1(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_1_MASK, CAN_WORD0_DATA_BYTE_1(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_1(base, index, value) (CAN_WR_WORD0_DATA_BYTE_1(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_0[31:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_0 field. */
+#define CAN_RD_WORD0_DATA_BYTE_0(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_0_MASK) >> CAN_WORD0_DATA_BYTE_0_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_0(base, index) (CAN_RD_WORD0_DATA_BYTE_0(base, index))
+
+/*! @brief Set the DATA_BYTE_0 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_0(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_0_MASK, CAN_WORD0_DATA_BYTE_0(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_0(base, index, value) (CAN_WR_WORD0_DATA_BYTE_0(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_WORD1 - Message Buffer 0 WORD1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_WORD1 - Message Buffer 0 WORD1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_WORD1 register
+ */
+/*@{*/
+#define CAN_RD_WORD1(base, index) (CAN_WORD1_REG(base, index))
+#define CAN_WR_WORD1(base, index, value) (CAN_WORD1_REG(base, index) = (value))
+#define CAN_RMW_WORD1(base, index, mask, value) (CAN_WR_WORD1(base, index, (CAN_RD_WORD1(base, index) & ~(mask)) | (value)))
+#define CAN_SET_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) |  (value)))
+#define CAN_CLR_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) & ~(value)))
+#define CAN_TOG_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_WORD1 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_7[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_7 field. */
+#define CAN_RD_WORD1_DATA_BYTE_7(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_7_MASK) >> CAN_WORD1_DATA_BYTE_7_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_7(base, index) (CAN_RD_WORD1_DATA_BYTE_7(base, index))
+
+/*! @brief Set the DATA_BYTE_7 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_7(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_7_MASK, CAN_WORD1_DATA_BYTE_7(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_7(base, index, value) (CAN_WR_WORD1_DATA_BYTE_7(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_6[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_6 field. */
+#define CAN_RD_WORD1_DATA_BYTE_6(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_6_MASK) >> CAN_WORD1_DATA_BYTE_6_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_6(base, index) (CAN_RD_WORD1_DATA_BYTE_6(base, index))
+
+/*! @brief Set the DATA_BYTE_6 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_6(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_6_MASK, CAN_WORD1_DATA_BYTE_6(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_6(base, index, value) (CAN_WR_WORD1_DATA_BYTE_6(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_5[23:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_5 field. */
+#define CAN_RD_WORD1_DATA_BYTE_5(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_5_MASK) >> CAN_WORD1_DATA_BYTE_5_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_5(base, index) (CAN_RD_WORD1_DATA_BYTE_5(base, index))
+
+/*! @brief Set the DATA_BYTE_5 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_5(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_5_MASK, CAN_WORD1_DATA_BYTE_5(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_5(base, index, value) (CAN_WR_WORD1_DATA_BYTE_5(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_4[31:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_4 field. */
+#define CAN_RD_WORD1_DATA_BYTE_4(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_4_MASK) >> CAN_WORD1_DATA_BYTE_4_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_4(base, index) (CAN_RD_WORD1_DATA_BYTE_4(base, index))
+
+/*! @brief Set the DATA_BYTE_4 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_4(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_4_MASK, CAN_WORD1_DATA_BYTE_4(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_4(base, index, value) (CAN_WR_WORD1_DATA_BYTE_4(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXIMR - Rx Individual Mask Registers
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXIMR - Rx Individual Mask Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers are located in RAM. RXIMR are used as acceptance masks for ID
+ * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
+ * register is provided for each available Mailbox, providing ID masking
+ * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
+ * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
+ * Table elements on a one-to-one correspondence depending on the setting of
+ * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
+ * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
+ * are not affected by reset and must be explicitly initialized prior to any
+ * reception.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXIMR register
+ */
+/*@{*/
+#define CAN_RD_RXIMR(base, index) (CAN_RXIMR_REG(base, index))
+#define CAN_WR_RXIMR(base, index, value) (CAN_RXIMR_REG(base, index) = (value))
+#define CAN_RMW_RXIMR(base, index, mask, value) (CAN_WR_RXIMR(base, index, (CAN_RD_RXIMR(base, index) & ~(mask)) | (value)))
+#define CAN_SET_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) |  (value)))
+#define CAN_CLR_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) & ~(value)))
+#define CAN_TOG_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 CAU
+ *
+ * Memory Mapped Cryptographic Acceleration Unit (MMCAU)
+ *
+ * Registers defined in this header file:
+ * - CAU_DIRECT - Direct access register 0
+ * - CAU_LDR_CASR - Status register - Load Register command
+ * - CAU_LDR_CAA - Accumulator register - Load Register command
+ * - CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ * - CAU_STR_CASR - Status register - Store Register command
+ * - CAU_STR_CAA - Accumulator register - Store Register command
+ * - CAU_STR_CA - General Purpose Register 0 - Store Register command
+ * - CAU_ADR_CASR - Status register - Add Register command
+ * - CAU_ADR_CAA - Accumulator register - Add to register command
+ * - CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ * - CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ * - CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ * - CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ * - CAU_XOR_CASR - Status register - Exclusive Or command
+ * - CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ * - CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ * - CAU_ROTL_CASR - Status register - Rotate Left command
+ * - CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ * - CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ * - CAU_AESC_CASR - Status register - AES Column Operation command
+ * - CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ * - CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ * - CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ * - CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ * - CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ */
+
+#define CAU_INSTANCE_COUNT (1U) /*!< Number of instances of the CAU module. */
+#define CAU_IDX (0U) /*!< Instance number for CAU. */
+
+/*******************************************************************************
+ * CAU_DIRECT - Direct access register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_DIRECT - Direct access register 0 (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_DIRECT register
+ */
+/*@{*/
+#define CAU_WR_DIRECT(base, index, value) (CAU_DIRECT_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CASR - Status register - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CASR - Status register - Load Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CASR register
+ */
+/*@{*/
+#define CAU_WR_LDR_CASR(base, value) (CAU_LDR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_LDR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_LDR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_LDR_CASR_IC(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_IC(value)))
+#define CAU_BWR_LDR_CASR_IC(base, value) (CAU_WR_LDR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_LDR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_LDR_CASR_DPE(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_DPE(value)))
+#define CAU_BWR_LDR_CASR_DPE(base, value) (CAU_WR_LDR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_LDR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_LDR_CASR_VER(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_VER(value)))
+#define CAU_BWR_LDR_CASR_VER(base, value) (CAU_WR_LDR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CAA - Accumulator register - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CAA - Accumulator register - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CAA register
+ */
+/*@{*/
+#define CAU_WR_LDR_CAA(base, value) (CAU_LDR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CA - General Purpose Register 0 - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CA register
+ */
+/*@{*/
+#define CAU_WR_LDR_CA(base, index, value) (CAU_LDR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CASR - Status register - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CASR - Status register - Store Register command (RO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CASR register
+ */
+/*@{*/
+#define CAU_RD_STR_CASR(base)    (CAU_STR_CASR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_STR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_STR_CASR, field IC[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_IC field. */
+#define CAU_RD_STR_CASR_IC(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_IC_MASK) >> CAU_STR_CASR_IC_SHIFT)
+#define CAU_BRD_STR_CASR_IC(base) (CAU_RD_STR_CASR_IC(base))
+/*@}*/
+
+/*!
+ * @name Register CAU_STR_CASR, field DPE[1] (RO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_DPE field. */
+#define CAU_RD_STR_CASR_DPE(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_DPE_MASK) >> CAU_STR_CASR_DPE_SHIFT)
+#define CAU_BRD_STR_CASR_DPE(base) (CAU_RD_STR_CASR_DPE(base))
+/*@}*/
+
+/*!
+ * @name Register CAU_STR_CASR, field VER[31:28] (RO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_VER field. */
+#define CAU_RD_STR_CASR_VER(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_VER_MASK) >> CAU_STR_CASR_VER_SHIFT)
+#define CAU_BRD_STR_CASR_VER(base) (CAU_RD_STR_CASR_VER(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CAA - Accumulator register - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CAA - Accumulator register - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CAA register
+ */
+/*@{*/
+#define CAU_RD_STR_CAA(base)     (CAU_STR_CAA_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CA - General Purpose Register 0 - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CA - General Purpose Register 0 - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CA register
+ */
+/*@{*/
+#define CAU_RD_STR_CA(base, index) (CAU_STR_CA_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CASR - Status register - Add Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CASR - Status register - Add Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CASR register
+ */
+/*@{*/
+#define CAU_WR_ADR_CASR(base, value) (CAU_ADR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_ADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_ADR_CASR_IC(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_IC(value)))
+#define CAU_BWR_ADR_CASR_IC(base, value) (CAU_WR_ADR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_ADR_CASR_DPE(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_DPE(value)))
+#define CAU_BWR_ADR_CASR_DPE(base, value) (CAU_WR_ADR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_ADR_CASR_VER(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_VER(value)))
+#define CAU_BWR_ADR_CASR_VER(base, value) (CAU_WR_ADR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CAA - Accumulator register - Add to register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CAA - Accumulator register - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CAA register
+ */
+/*@{*/
+#define CAU_WR_ADR_CAA(base, value) (CAU_ADR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CA - General Purpose Register 0 - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CA register
+ */
+/*@{*/
+#define CAU_WR_ADR_CA(base, index, value) (CAU_ADR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CASR - Status register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CASR register
+ */
+/*@{*/
+#define CAU_WR_RADR_CASR(base, value) (CAU_RADR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_RADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_RADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_RADR_CASR_IC(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_IC(value)))
+#define CAU_BWR_RADR_CASR_IC(base, value) (CAU_WR_RADR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_RADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_RADR_CASR_DPE(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_DPE(value)))
+#define CAU_BWR_RADR_CASR_DPE(base, value) (CAU_WR_RADR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_RADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_RADR_CASR_VER(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_VER(value)))
+#define CAU_BWR_RADR_CASR_VER(base, value) (CAU_WR_RADR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CAA register
+ */
+/*@{*/
+#define CAU_WR_RADR_CAA(base, value) (CAU_RADR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CA register
+ */
+/*@{*/
+#define CAU_WR_RADR_CA(base, index, value) (CAU_RADR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CASR - Status register - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CASR - Status register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CASR register
+ */
+/*@{*/
+#define CAU_WR_XOR_CASR(base, value) (CAU_XOR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_XOR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_XOR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_XOR_CASR_IC(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_IC(value)))
+#define CAU_BWR_XOR_CASR_IC(base, value) (CAU_WR_XOR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_XOR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_XOR_CASR_DPE(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_DPE(value)))
+#define CAU_BWR_XOR_CASR_DPE(base, value) (CAU_WR_XOR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_XOR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_XOR_CASR_VER(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_VER(value)))
+#define CAU_BWR_XOR_CASR_VER(base, value) (CAU_WR_XOR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CAA register
+ */
+/*@{*/
+#define CAU_WR_XOR_CAA(base, value) (CAU_XOR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CA register
+ */
+/*@{*/
+#define CAU_WR_XOR_CA(base, index, value) (CAU_XOR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CASR - Status register - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CASR - Status register - Rotate Left command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CASR register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CASR(base, value) (CAU_ROTL_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_ROTL_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ROTL_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_ROTL_CASR_IC(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_IC(value)))
+#define CAU_BWR_ROTL_CASR_IC(base, value) (CAU_WR_ROTL_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ROTL_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_ROTL_CASR_DPE(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_DPE(value)))
+#define CAU_BWR_ROTL_CASR_DPE(base, value) (CAU_WR_ROTL_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_ROTL_CASR_VER(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_VER(value)))
+#define CAU_BWR_ROTL_CASR_VER(base, value) (CAU_WR_ROTL_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CAA register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CAA(base, value) (CAU_ROTL_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CA register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CA(base, index, value) (CAU_ROTL_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CASR - Status register - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CASR - Status register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CASR register
+ */
+/*@{*/
+#define CAU_WR_AESC_CASR(base, value) (CAU_AESC_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_AESC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_AESC_CASR_IC(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_IC(value)))
+#define CAU_BWR_AESC_CASR_IC(base, value) (CAU_WR_AESC_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_AESC_CASR_DPE(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_DPE(value)))
+#define CAU_BWR_AESC_CASR_DPE(base, value) (CAU_WR_AESC_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_AESC_CASR_VER(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_VER(value)))
+#define CAU_BWR_AESC_CASR_VER(base, value) (CAU_WR_AESC_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CAA register
+ */
+/*@{*/
+#define CAU_WR_AESC_CAA(base, value) (CAU_AESC_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CA register
+ */
+/*@{*/
+#define CAU_WR_AESC_CA(base, index, value) (CAU_AESC_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CASR - Status register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CASR register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CASR(base, value) (CAU_AESIC_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_AESIC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESIC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_AESIC_CASR_IC(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_IC(value)))
+#define CAU_BWR_AESIC_CASR_IC(base, value) (CAU_WR_AESIC_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESIC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_AESIC_CASR_DPE(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_DPE(value)))
+#define CAU_BWR_AESIC_CASR_DPE(base, value) (CAU_WR_AESIC_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_AESIC_CASR_VER(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_VER(value)))
+#define CAU_BWR_AESIC_CASR_VER(base, value) (CAU_WR_AESIC_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CAA register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CAA(base, value) (CAU_AESIC_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CA register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CA(base, index, value) (CAU_AESIC_CA_REG(base, index) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CMP
+ *
+ * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
+ *
+ * Registers defined in this header file:
+ * - CMP_CR0 - CMP Control Register 0
+ * - CMP_CR1 - CMP Control Register 1
+ * - CMP_FPR - CMP Filter Period Register
+ * - CMP_SCR - CMP Status and Control Register
+ * - CMP_DACCR - DAC Control Register
+ * - CMP_MUXCR - MUX Control Register
+ */
+
+#define CMP_INSTANCE_COUNT (3U) /*!< Number of instances of the CMP module. */
+#define CMP0_IDX (0U) /*!< Instance number for CMP0. */
+#define CMP1_IDX (1U) /*!< Instance number for CMP1. */
+#define CMP2_IDX (2U) /*!< Instance number for CMP2. */
+
+/*******************************************************************************
+ * CMP_CR0 - CMP Control Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR0 - CMP Control Register 0 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR0 register
+ */
+/*@{*/
+#define CMP_RD_CR0(base)         (CMP_CR0_REG(base))
+#define CMP_WR_CR0(base, value)  (CMP_CR0_REG(base) = (value))
+#define CMP_RMW_CR0(base, mask, value) (CMP_WR_CR0(base, (CMP_RD_CR0(base) & ~(mask)) | (value)))
+#define CMP_SET_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) |  (value)))
+#define CMP_CLR_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) & ~(value)))
+#define CMP_TOG_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR0 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
+ *
+ * Defines the programmable hysteresis level. The hysteresis values associated
+ * with each level are device-specific. See the Data Sheet of the device for the
+ * exact values.
+ *
+ * Values:
+ * - 0b00 - Level 0
+ * - 0b01 - Level 1
+ * - 0b10 - Level 2
+ * - 0b11 - Level 3
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
+#define CMP_RD_CR0_HYSTCTR(base) ((CMP_CR0_REG(base) & CMP_CR0_HYSTCTR_MASK) >> CMP_CR0_HYSTCTR_SHIFT)
+#define CMP_BRD_CR0_HYSTCTR(base) (CMP_RD_CR0_HYSTCTR(base))
+
+/*! @brief Set the HYSTCTR field to a new value. */
+#define CMP_WR_CR0_HYSTCTR(base, value) (CMP_RMW_CR0(base, CMP_CR0_HYSTCTR_MASK, CMP_CR0_HYSTCTR(value)))
+#define CMP_BWR_CR0_HYSTCTR(base, value) (CMP_WR_CR0_HYSTCTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
+ *
+ * Represents the number of consecutive samples that must agree prior to the
+ * comparator ouput filter accepting a new output state. For information regarding
+ * filter programming and latency, see the Functional descriptionThe CMP module
+ * can be used to compare two analog input voltages applied to INP and INM. .
+ *
+ * Values:
+ * - 0b000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not
+ *     a legal state, and is not recommended. If SE = 0, COUT = COUTA.
+ * - 0b001 - One sample must agree. The comparator output is simply sampled.
+ * - 0b010 - 2 consecutive samples must agree.
+ * - 0b011 - 3 consecutive samples must agree.
+ * - 0b100 - 4 consecutive samples must agree.
+ * - 0b101 - 5 consecutive samples must agree.
+ * - 0b110 - 6 consecutive samples must agree.
+ * - 0b111 - 7 consecutive samples must agree.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
+#define CMP_RD_CR0_FILTER_CNT(base) ((CMP_CR0_REG(base) & CMP_CR0_FILTER_CNT_MASK) >> CMP_CR0_FILTER_CNT_SHIFT)
+#define CMP_BRD_CR0_FILTER_CNT(base) (CMP_RD_CR0_FILTER_CNT(base))
+
+/*! @brief Set the FILTER_CNT field to a new value. */
+#define CMP_WR_CR0_FILTER_CNT(base, value) (CMP_RMW_CR0(base, CMP_CR0_FILTER_CNT_MASK, CMP_CR0_FILTER_CNT(value)))
+#define CMP_BWR_CR0_FILTER_CNT(base, value) (CMP_WR_CR0_FILTER_CNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_CR1 - CMP Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR1 - CMP Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR1 register
+ */
+/*@{*/
+#define CMP_RD_CR1(base)         (CMP_CR1_REG(base))
+#define CMP_WR_CR1(base, value)  (CMP_CR1_REG(base) = (value))
+#define CMP_RMW_CR1(base, mask, value) (CMP_WR_CR1(base, (CMP_RD_CR1(base) & ~(mask)) | (value)))
+#define CMP_SET_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) |  (value)))
+#define CMP_CLR_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) & ~(value)))
+#define CMP_TOG_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR1 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR1, field EN[0] (RW)
+ *
+ * Enables the Analog Comparator module. When the module is not enabled, it
+ * remains in the off state, and consumes no power. When the user selects the same
+ * input from analog mux to the positive and negative port, the comparator is
+ * disabled automatically.
+ *
+ * Values:
+ * - 0b0 - Analog Comparator is disabled.
+ * - 0b1 - Analog Comparator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_EN field. */
+#define CMP_RD_CR1_EN(base)  ((CMP_CR1_REG(base) & CMP_CR1_EN_MASK) >> CMP_CR1_EN_SHIFT)
+#define CMP_BRD_CR1_EN(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT))
+
+/*! @brief Set the EN field to a new value. */
+#define CMP_WR_CR1_EN(base, value) (CMP_RMW_CR1(base, CMP_CR1_EN_MASK, CMP_CR1_EN(value)))
+#define CMP_BWR_CR1_EN(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field OPE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - CMPO is not available on the associated CMPO output pin. If the
+ *     comparator does not own the pin, this field has no effect.
+ * - 0b1 - CMPO is available on the associated CMPO output pin. The comparator
+ *     output (CMPO) is driven out on the associated CMPO output pin if the
+ *     comparator owns the pin. If the comparator does not own the field, this bit has
+ *     no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_OPE field. */
+#define CMP_RD_CR1_OPE(base) ((CMP_CR1_REG(base) & CMP_CR1_OPE_MASK) >> CMP_CR1_OPE_SHIFT)
+#define CMP_BRD_CR1_OPE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT))
+
+/*! @brief Set the OPE field to a new value. */
+#define CMP_WR_CR1_OPE(base, value) (CMP_RMW_CR1(base, CMP_CR1_OPE_MASK, CMP_CR1_OPE(value)))
+#define CMP_BWR_CR1_OPE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field COS[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Set the filtered comparator output (CMPO) to equal COUT.
+ * - 0b1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_COS field. */
+#define CMP_RD_CR1_COS(base) ((CMP_CR1_REG(base) & CMP_CR1_COS_MASK) >> CMP_CR1_COS_SHIFT)
+#define CMP_BRD_CR1_COS(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT))
+
+/*! @brief Set the COS field to a new value. */
+#define CMP_WR_CR1_COS(base, value) (CMP_RMW_CR1(base, CMP_CR1_COS_MASK, CMP_CR1_COS(value)))
+#define CMP_BWR_CR1_COS(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field INV[3] (RW)
+ *
+ * Allows selection of the polarity of the analog comparator function. It is
+ * also driven to the COUT output, on both the device pin and as SCR[COUT], when
+ * OPE=0.
+ *
+ * Values:
+ * - 0b0 - Does not invert the comparator output.
+ * - 0b1 - Inverts the comparator output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_INV field. */
+#define CMP_RD_CR1_INV(base) ((CMP_CR1_REG(base) & CMP_CR1_INV_MASK) >> CMP_CR1_INV_SHIFT)
+#define CMP_BRD_CR1_INV(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT))
+
+/*! @brief Set the INV field to a new value. */
+#define CMP_WR_CR1_INV(base, value) (CMP_RMW_CR1(base, CMP_CR1_INV_MASK, CMP_CR1_INV(value)))
+#define CMP_BWR_CR1_INV(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field PMODE[4] (RW)
+ *
+ * See the electrical specifications table in the device Data Sheet for details.
+ *
+ * Values:
+ * - 0b0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
+ *     output propagation delay and lower current consumption.
+ * - 0b1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has
+ *     faster output propagation delay and higher current consumption.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_PMODE field. */
+#define CMP_RD_CR1_PMODE(base) ((CMP_CR1_REG(base) & CMP_CR1_PMODE_MASK) >> CMP_CR1_PMODE_SHIFT)
+#define CMP_BRD_CR1_PMODE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT))
+
+/*! @brief Set the PMODE field to a new value. */
+#define CMP_WR_CR1_PMODE(base, value) (CMP_RMW_CR1(base, CMP_CR1_PMODE_MASK, CMP_CR1_PMODE(value)))
+#define CMP_BWR_CR1_PMODE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field WE[6] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0b0 - Windowing mode is not selected.
+ * - 0b1 - Windowing mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_WE field. */
+#define CMP_RD_CR1_WE(base)  ((CMP_CR1_REG(base) & CMP_CR1_WE_MASK) >> CMP_CR1_WE_SHIFT)
+#define CMP_BRD_CR1_WE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT))
+
+/*! @brief Set the WE field to a new value. */
+#define CMP_WR_CR1_WE(base, value) (CMP_RMW_CR1(base, CMP_CR1_WE_MASK, CMP_CR1_WE(value)))
+#define CMP_BWR_CR1_WE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field SE[7] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0b0 - Sampling mode is not selected.
+ * - 0b1 - Sampling mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_SE field. */
+#define CMP_RD_CR1_SE(base)  ((CMP_CR1_REG(base) & CMP_CR1_SE_MASK) >> CMP_CR1_SE_SHIFT)
+#define CMP_BRD_CR1_SE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT))
+
+/*! @brief Set the SE field to a new value. */
+#define CMP_WR_CR1_SE(base, value) (CMP_RMW_CR1(base, CMP_CR1_SE_MASK, CMP_CR1_SE(value)))
+#define CMP_BWR_CR1_SE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_FPR - CMP Filter Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_FPR - CMP Filter Period Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_FPR register
+ */
+/*@{*/
+#define CMP_RD_FPR(base)         (CMP_FPR_REG(base))
+#define CMP_WR_FPR(base, value)  (CMP_FPR_REG(base) = (value))
+#define CMP_RMW_FPR(base, mask, value) (CMP_WR_FPR(base, (CMP_RD_FPR(base) & ~(mask)) | (value)))
+#define CMP_SET_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) |  (value)))
+#define CMP_CLR_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) & ~(value)))
+#define CMP_TOG_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_SCR - CMP Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_SCR - CMP Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_SCR register
+ */
+/*@{*/
+#define CMP_RD_SCR(base)         (CMP_SCR_REG(base))
+#define CMP_WR_SCR(base, value)  (CMP_SCR_REG(base) = (value))
+#define CMP_RMW_SCR(base, mask, value) (CMP_WR_SCR(base, (CMP_RD_SCR(base) & ~(mask)) | (value)))
+#define CMP_SET_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) |  (value)))
+#define CMP_CLR_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) & ~(value)))
+#define CMP_TOG_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_SCR bitfields
+ */
+
+/*!
+ * @name Register CMP_SCR, field COUT[0] (RO)
+ *
+ * Returns the current value of the Analog Comparator output, when read. The
+ * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
+ * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_COUT field. */
+#define CMP_RD_SCR_COUT(base) ((CMP_SCR_REG(base) & CMP_SCR_COUT_MASK) >> CMP_SCR_COUT_SHIFT)
+#define CMP_BRD_SCR_COUT(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_COUT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFF[1] (W1C)
+ *
+ * Detects a falling-edge on COUT, when set, during normal operation. CFF is
+ * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0b0 - Falling-edge on COUT has not been detected.
+ * - 0b1 - Falling-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFF field. */
+#define CMP_RD_SCR_CFF(base) ((CMP_SCR_REG(base) & CMP_SCR_CFF_MASK) >> CMP_SCR_CFF_SHIFT)
+#define CMP_BRD_SCR_CFF(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT))
+
+/*! @brief Set the CFF field to a new value. */
+#define CMP_WR_SCR_CFF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_CFF(value)))
+#define CMP_BWR_SCR_CFF(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFR[2] (W1C)
+ *
+ * Detects a rising-edge on COUT, when set, during normal operation. CFR is
+ * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0b0 - Rising-edge on COUT has not been detected.
+ * - 0b1 - Rising-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFR field. */
+#define CMP_RD_SCR_CFR(base) ((CMP_SCR_REG(base) & CMP_SCR_CFR_MASK) >> CMP_SCR_CFR_SHIFT)
+#define CMP_BRD_SCR_CFR(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT))
+
+/*! @brief Set the CFR field to a new value. */
+#define CMP_WR_SCR_CFR(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK), CMP_SCR_CFR(value)))
+#define CMP_BWR_SCR_CFR(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IEF[3] (RW)
+ *
+ * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFF is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled.
+ * - 0b1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IEF field. */
+#define CMP_RD_SCR_IEF(base) ((CMP_SCR_REG(base) & CMP_SCR_IEF_MASK) >> CMP_SCR_IEF_SHIFT)
+#define CMP_BRD_SCR_IEF(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT))
+
+/*! @brief Set the IEF field to a new value. */
+#define CMP_WR_SCR_IEF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IEF_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IEF(value)))
+#define CMP_BWR_SCR_IEF(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IER[4] (RW)
+ *
+ * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFR is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled.
+ * - 0b1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IER field. */
+#define CMP_RD_SCR_IER(base) ((CMP_SCR_REG(base) & CMP_SCR_IER_MASK) >> CMP_SCR_IER_SHIFT)
+#define CMP_BRD_SCR_IER(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT))
+
+/*! @brief Set the IER field to a new value. */
+#define CMP_WR_SCR_IER(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IER_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IER(value)))
+#define CMP_BWR_SCR_IER(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field DMAEN[6] (RW)
+ *
+ * Enables the DMA transfer triggered from the CMP module. When this field is
+ * set, a DMA request is asserted when CFR or CFF is set.
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_DMAEN field. */
+#define CMP_RD_SCR_DMAEN(base) ((CMP_SCR_REG(base) & CMP_SCR_DMAEN_MASK) >> CMP_SCR_DMAEN_SHIFT)
+#define CMP_BRD_SCR_DMAEN(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define CMP_WR_SCR_DMAEN(base, value) (CMP_RMW_SCR(base, (CMP_SCR_DMAEN_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_DMAEN(value)))
+#define CMP_BWR_SCR_DMAEN(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_DACCR - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_DACCR - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_DACCR register
+ */
+/*@{*/
+#define CMP_RD_DACCR(base)       (CMP_DACCR_REG(base))
+#define CMP_WR_DACCR(base, value) (CMP_DACCR_REG(base) = (value))
+#define CMP_RMW_DACCR(base, mask, value) (CMP_WR_DACCR(base, (CMP_RD_DACCR(base) & ~(mask)) | (value)))
+#define CMP_SET_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) |  (value)))
+#define CMP_CLR_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) & ~(value)))
+#define CMP_TOG_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_DACCR bitfields
+ */
+
+/*!
+ * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
+ *
+ * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
+ * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VOSEL field. */
+#define CMP_RD_DACCR_VOSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VOSEL_MASK) >> CMP_DACCR_VOSEL_SHIFT)
+#define CMP_BRD_DACCR_VOSEL(base) (CMP_RD_DACCR_VOSEL(base))
+
+/*! @brief Set the VOSEL field to a new value. */
+#define CMP_WR_DACCR_VOSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VOSEL_MASK, CMP_DACCR_VOSEL(value)))
+#define CMP_BWR_DACCR_VOSEL(base, value) (CMP_WR_DACCR_VOSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field VRSEL[6] (RW)
+ *
+ * Values:
+ * - 0b0 - V is selected as resistor ladder network supply reference V. in1 in
+ * - 0b1 - V is selected as resistor ladder network supply reference V. in2 in
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VRSEL field. */
+#define CMP_RD_DACCR_VRSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VRSEL_MASK) >> CMP_DACCR_VRSEL_SHIFT)
+#define CMP_BRD_DACCR_VRSEL(base) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT))
+
+/*! @brief Set the VRSEL field to a new value. */
+#define CMP_WR_DACCR_VRSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VRSEL_MASK, CMP_DACCR_VRSEL(value)))
+#define CMP_BWR_DACCR_VRSEL(base, value) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field DACEN[7] (RW)
+ *
+ * Enables the DAC. When the DAC is disabled, it is powered down to conserve
+ * power.
+ *
+ * Values:
+ * - 0b0 - DAC is disabled.
+ * - 0b1 - DAC is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_DACEN field. */
+#define CMP_RD_DACCR_DACEN(base) ((CMP_DACCR_REG(base) & CMP_DACCR_DACEN_MASK) >> CMP_DACCR_DACEN_SHIFT)
+#define CMP_BRD_DACCR_DACEN(base) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT))
+
+/*! @brief Set the DACEN field to a new value. */
+#define CMP_WR_DACCR_DACEN(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_DACEN_MASK, CMP_DACCR_DACEN(value)))
+#define CMP_BWR_DACCR_DACEN(base, value) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_MUXCR - MUX Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_MUXCR - MUX Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_MUXCR register
+ */
+/*@{*/
+#define CMP_RD_MUXCR(base)       (CMP_MUXCR_REG(base))
+#define CMP_WR_MUXCR(base, value) (CMP_MUXCR_REG(base) = (value))
+#define CMP_RMW_MUXCR(base, mask, value) (CMP_WR_MUXCR(base, (CMP_RD_MUXCR(base) & ~(mask)) | (value)))
+#define CMP_SET_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) |  (value)))
+#define CMP_CLR_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) & ~(value)))
+#define CMP_TOG_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_MUXCR bitfields
+ */
+
+/*!
+ * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
+ *
+ * Determines which input is selected for the minus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 0b000 - IN0
+ * - 0b001 - IN1
+ * - 0b010 - IN2
+ * - 0b011 - IN3
+ * - 0b100 - IN4
+ * - 0b101 - IN5
+ * - 0b110 - IN6
+ * - 0b111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_MSEL field. */
+#define CMP_RD_MUXCR_MSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_MSEL_MASK) >> CMP_MUXCR_MSEL_SHIFT)
+#define CMP_BRD_MUXCR_MSEL(base) (CMP_RD_MUXCR_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define CMP_WR_MUXCR_MSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_MSEL_MASK, CMP_MUXCR_MSEL(value)))
+#define CMP_BWR_MUXCR_MSEL(base, value) (CMP_WR_MUXCR_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
+ *
+ * Determines which input is selected for the plus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 0b000 - IN0
+ * - 0b001 - IN1
+ * - 0b010 - IN2
+ * - 0b011 - IN3
+ * - 0b100 - IN4
+ * - 0b101 - IN5
+ * - 0b110 - IN6
+ * - 0b111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSEL field. */
+#define CMP_RD_MUXCR_PSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSEL_MASK) >> CMP_MUXCR_PSEL_SHIFT)
+#define CMP_BRD_MUXCR_PSEL(base) (CMP_RD_MUXCR_PSEL(base))
+
+/*! @brief Set the PSEL field to a new value. */
+#define CMP_WR_MUXCR_PSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSEL_MASK, CMP_MUXCR_PSEL(value)))
+#define CMP_BWR_MUXCR_PSEL(base, value) (CMP_WR_MUXCR_PSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSTM[7] (RW)
+ *
+ * This bit is used to enable to MUX pass through mode. Pass through mode is
+ * always available but for some devices this feature must be always disabled due to
+ * the lack of package pins.
+ *
+ * Values:
+ * - 0b0 - Pass Through Mode is disabled.
+ * - 0b1 - Pass Through Mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSTM field. */
+#define CMP_RD_MUXCR_PSTM(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSTM_MASK) >> CMP_MUXCR_PSTM_SHIFT)
+#define CMP_BRD_MUXCR_PSTM(base) (BITBAND_ACCESS8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT))
+
+/*! @brief Set the PSTM field to a new value. */
+#define CMP_WR_MUXCR_PSTM(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSTM_MASK, CMP_MUXCR_PSTM(value)))
+#define CMP_BWR_MUXCR_PSTM(base, value) (BITBAND_ACCESS8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CMT
+ *
+ * Carrier Modulator Transmitter
+ *
+ * Registers defined in this header file:
+ * - CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ * - CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ * - CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ * - CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ * - CMT_OC - CMT Output Control Register
+ * - CMT_MSC - CMT Modulator Status and Control Register
+ * - CMT_CMD1 - CMT Modulator Data Register Mark High
+ * - CMT_CMD2 - CMT Modulator Data Register Mark Low
+ * - CMT_CMD3 - CMT Modulator Data Register Space High
+ * - CMT_CMD4 - CMT Modulator Data Register Space Low
+ * - CMT_PPS - CMT Primary Prescaler Register
+ * - CMT_DMA - CMT Direct Memory Access Register
+ */
+
+#define CMT_INSTANCE_COUNT (1U) /*!< Number of instances of the CMT module. */
+#define CMT_IDX (0U) /*!< Instance number for CMT. */
+
+/*******************************************************************************
+ * CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary high value for generating the carrier
+ * output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGH1 register
+ */
+/*@{*/
+#define CMT_RD_CGH1(base)        (CMT_CGH1_REG(base))
+#define CMT_WR_CGH1(base, value) (CMT_CGH1_REG(base) = (value))
+#define CMT_RMW_CGH1(base, mask, value) (CMT_WR_CGH1(base, (CMT_RD_CGH1(base) & ~(mask)) | (value)))
+#define CMT_SET_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) |  (value)))
+#define CMT_CLR_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) & ~(value)))
+#define CMT_TOG_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary low value for generating the carrier
+ * output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGL1 register
+ */
+/*@{*/
+#define CMT_RD_CGL1(base)        (CMT_CGL1_REG(base))
+#define CMT_WR_CGL1(base, value) (CMT_CGL1_REG(base) = (value))
+#define CMT_RMW_CGL1(base, mask, value) (CMT_WR_CGL1(base, (CMT_RD_CGL1(base) & ~(mask)) | (value)))
+#define CMT_SET_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) |  (value)))
+#define CMT_CLR_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) & ~(value)))
+#define CMT_TOG_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary high value for generating the
+ * carrier output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGH2 register
+ */
+/*@{*/
+#define CMT_RD_CGH2(base)        (CMT_CGH2_REG(base))
+#define CMT_WR_CGH2(base, value) (CMT_CGH2_REG(base) = (value))
+#define CMT_RMW_CGH2(base, mask, value) (CMT_WR_CGH2(base, (CMT_RD_CGH2(base) & ~(mask)) | (value)))
+#define CMT_SET_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) |  (value)))
+#define CMT_CLR_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) & ~(value)))
+#define CMT_TOG_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary low value for generating the
+ * carrier output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGL2 register
+ */
+/*@{*/
+#define CMT_RD_CGL2(base)        (CMT_CGL2_REG(base))
+#define CMT_WR_CGL2(base, value) (CMT_CGL2_REG(base) = (value))
+#define CMT_RMW_CGL2(base, mask, value) (CMT_WR_CGL2(base, (CMT_RD_CGL2(base) & ~(mask)) | (value)))
+#define CMT_SET_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) |  (value)))
+#define CMT_CLR_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) & ~(value)))
+#define CMT_TOG_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_OC - CMT Output Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_OC - CMT Output Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to control the IRO signal of the CMT module.
+ */
+/*!
+ * @name Constants and macros for entire CMT_OC register
+ */
+/*@{*/
+#define CMT_RD_OC(base)          (CMT_OC_REG(base))
+#define CMT_WR_OC(base, value)   (CMT_OC_REG(base) = (value))
+#define CMT_RMW_OC(base, mask, value) (CMT_WR_OC(base, (CMT_RD_OC(base) & ~(mask)) | (value)))
+#define CMT_SET_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) |  (value)))
+#define CMT_CLR_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) & ~(value)))
+#define CMT_TOG_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_OC bitfields
+ */
+
+/*!
+ * @name Register CMT_OC, field IROPEN[5] (RW)
+ *
+ * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
+ * output that drives out either the CMT transmitter output or the state of IROL
+ * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
+ * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
+ * signal is disabled, it is in a high-impedance state and is unable to draw any
+ * current. This signal is disabled during reset.
+ *
+ * Values:
+ * - 0b0 - The IRO signal is disabled.
+ * - 0b1 - The IRO signal is enabled as output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_IROPEN field. */
+#define CMT_RD_OC_IROPEN(base) ((CMT_OC_REG(base) & CMT_OC_IROPEN_MASK) >> CMT_OC_IROPEN_SHIFT)
+#define CMT_BRD_OC_IROPEN(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT))
+
+/*! @brief Set the IROPEN field to a new value. */
+#define CMT_WR_OC_IROPEN(base, value) (CMT_RMW_OC(base, CMT_OC_IROPEN_MASK, CMT_OC_IROPEN(value)))
+#define CMT_BWR_OC_IROPEN(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_OC, field CMTPOL[6] (RW)
+ *
+ * Controls the polarity of the IRO signal.
+ *
+ * Values:
+ * - 0b0 - The IRO signal is active-low.
+ * - 0b1 - The IRO signal is active-high.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_CMTPOL field. */
+#define CMT_RD_OC_CMTPOL(base) ((CMT_OC_REG(base) & CMT_OC_CMTPOL_MASK) >> CMT_OC_CMTPOL_SHIFT)
+#define CMT_BRD_OC_CMTPOL(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT))
+
+/*! @brief Set the CMTPOL field to a new value. */
+#define CMT_WR_OC_CMTPOL(base, value) (CMT_RMW_OC(base, CMT_OC_CMTPOL_MASK, CMT_OC_CMTPOL(value)))
+#define CMT_BWR_OC_CMTPOL(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_OC, field IROL[7] (RW)
+ *
+ * Reads the state of the IRO latch. Writing to IROL changes the state of the
+ * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_IROL field. */
+#define CMT_RD_OC_IROL(base) ((CMT_OC_REG(base) & CMT_OC_IROL_MASK) >> CMT_OC_IROL_SHIFT)
+#define CMT_BRD_OC_IROL(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT))
+
+/*! @brief Set the IROL field to a new value. */
+#define CMT_WR_OC_IROL(base, value) (CMT_RMW_OC(base, CMT_OC_IROL_MASK, CMT_OC_IROL(value)))
+#define CMT_BWR_OC_IROL(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_MSC - CMT Modulator Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_MSC - CMT Modulator Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the modulator and carrier generator enable (MCGEN),
+ * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
+ * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
+ * (EOCF) status bit.
+ */
+/*!
+ * @name Constants and macros for entire CMT_MSC register
+ */
+/*@{*/
+#define CMT_RD_MSC(base)         (CMT_MSC_REG(base))
+#define CMT_WR_MSC(base, value)  (CMT_MSC_REG(base) = (value))
+#define CMT_RMW_MSC(base, mask, value) (CMT_WR_MSC(base, (CMT_RD_MSC(base) & ~(mask)) | (value)))
+#define CMT_SET_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) |  (value)))
+#define CMT_CLR_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) & ~(value)))
+#define CMT_TOG_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_MSC bitfields
+ */
+
+/*!
+ * @name Register CMT_MSC, field MCGEN[0] (RW)
+ *
+ * Setting MCGEN will initialize the carrier generator and modulator and will
+ * enable all clocks. When enabled, the carrier generator and modulator will
+ * function continuously. When MCGEN is cleared, the current modulator cycle will be
+ * allowed to expire before all carrier and modulator clocks are disabled to save
+ * power and the modulator output is forced low. To prevent spurious operation,
+ * the user should initialize all data and control registers before enabling the
+ * system.
+ *
+ * Values:
+ * - 0b0 - Modulator and carrier generator disabled
+ * - 0b1 - Modulator and carrier generator enabled
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_MCGEN field. */
+#define CMT_RD_MSC_MCGEN(base) ((CMT_MSC_REG(base) & CMT_MSC_MCGEN_MASK) >> CMT_MSC_MCGEN_SHIFT)
+#define CMT_BRD_MSC_MCGEN(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT))
+
+/*! @brief Set the MCGEN field to a new value. */
+#define CMT_WR_MSC_MCGEN(base, value) (CMT_RMW_MSC(base, CMT_MSC_MCGEN_MASK, CMT_MSC_MCGEN(value)))
+#define CMT_BWR_MSC_MCGEN(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EOCIE[1] (RW)
+ *
+ * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
+ *
+ * Values:
+ * - 0b0 - CPU interrupt is disabled.
+ * - 0b1 - CPU interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EOCIE field. */
+#define CMT_RD_MSC_EOCIE(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCIE_MASK) >> CMT_MSC_EOCIE_SHIFT)
+#define CMT_BRD_MSC_EOCIE(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT))
+
+/*! @brief Set the EOCIE field to a new value. */
+#define CMT_WR_MSC_EOCIE(base, value) (CMT_RMW_MSC(base, CMT_MSC_EOCIE_MASK, CMT_MSC_EOCIE(value)))
+#define CMT_BWR_MSC_EOCIE(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field FSK[2] (RW)
+ *
+ * Enables FSK operation.
+ *
+ * Values:
+ * - 0b0 - The CMT operates in Time or Baseband mode.
+ * - 0b1 - The CMT operates in FSK mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_FSK field. */
+#define CMT_RD_MSC_FSK(base) ((CMT_MSC_REG(base) & CMT_MSC_FSK_MASK) >> CMT_MSC_FSK_SHIFT)
+#define CMT_BRD_MSC_FSK(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT))
+
+/*! @brief Set the FSK field to a new value. */
+#define CMT_WR_MSC_FSK(base, value) (CMT_RMW_MSC(base, CMT_MSC_FSK_MASK, CMT_MSC_FSK(value)))
+#define CMT_BWR_MSC_FSK(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field BASE[3] (RW)
+ *
+ * When set, BASE disables the carrier generator and forces the carrier output
+ * high for generation of baseband protocols. When BASE is cleared, the carrier
+ * generator is enabled and the carrier output toggles at the frequency determined
+ * by values stored in the carrier data registers. This field is cleared by
+ * reset. This field is not double-buffered and must not be written to during a
+ * transmission.
+ *
+ * Values:
+ * - 0b0 - Baseband mode is disabled.
+ * - 0b1 - Baseband mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_BASE field. */
+#define CMT_RD_MSC_BASE(base) ((CMT_MSC_REG(base) & CMT_MSC_BASE_MASK) >> CMT_MSC_BASE_SHIFT)
+#define CMT_BRD_MSC_BASE(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT))
+
+/*! @brief Set the BASE field to a new value. */
+#define CMT_WR_MSC_BASE(base, value) (CMT_RMW_MSC(base, CMT_MSC_BASE_MASK, CMT_MSC_BASE(value)))
+#define CMT_BWR_MSC_BASE(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EXSPC[4] (RW)
+ *
+ * Enables the extended space operation.
+ *
+ * Values:
+ * - 0b0 - Extended space is disabled.
+ * - 0b1 - Extended space is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EXSPC field. */
+#define CMT_RD_MSC_EXSPC(base) ((CMT_MSC_REG(base) & CMT_MSC_EXSPC_MASK) >> CMT_MSC_EXSPC_SHIFT)
+#define CMT_BRD_MSC_EXSPC(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT))
+
+/*! @brief Set the EXSPC field to a new value. */
+#define CMT_WR_MSC_EXSPC(base, value) (CMT_RMW_MSC(base, CMT_MSC_EXSPC_MASK, CMT_MSC_EXSPC(value)))
+#define CMT_BWR_MSC_EXSPC(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
+ *
+ * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
+ * divided by 2 ,4, or 8 . This field must not be changed during a transmission
+ * because it is not double-buffered.
+ *
+ * Values:
+ * - 0b00 - IF * 1
+ * - 0b01 - IF * 2
+ * - 0b10 - IF * 4
+ * - 0b11 - IF * 8
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_CMTDIV field. */
+#define CMT_RD_MSC_CMTDIV(base) ((CMT_MSC_REG(base) & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT)
+#define CMT_BRD_MSC_CMTDIV(base) (CMT_RD_MSC_CMTDIV(base))
+
+/*! @brief Set the CMTDIV field to a new value. */
+#define CMT_WR_MSC_CMTDIV(base, value) (CMT_RMW_MSC(base, CMT_MSC_CMTDIV_MASK, CMT_MSC_CMTDIV(value)))
+#define CMT_BWR_MSC_CMTDIV(base, value) (CMT_WR_MSC_CMTDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EOCF[7] (RO)
+ *
+ * Sets when: The modulator is not currently active and MCGEN is set to begin
+ * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
+ * set. This is recognized when a match occurs between the contents of the space
+ * period register and the down counter. At this time, the counter is
+ * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
+ * the space period register is loaded with, possibly new contents of the space
+ * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
+ * access of CMD2 or CMD4, or by the DMA transfer.
+ *
+ * Values:
+ * - 0b0 - End of modulation cycle has not occured since the flag last cleared.
+ * - 0b1 - End of modulator cycle has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EOCF field. */
+#define CMT_RD_MSC_EOCF(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCF_MASK) >> CMT_MSC_EOCF_SHIFT)
+#define CMT_BRD_MSC_EOCF(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD1 - CMT Modulator Data Register Mark High
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD1 register
+ */
+/*@{*/
+#define CMT_RD_CMD1(base)        (CMT_CMD1_REG(base))
+#define CMT_WR_CMD1(base, value) (CMT_CMD1_REG(base) = (value))
+#define CMT_RMW_CMD1(base, mask, value) (CMT_WR_CMD1(base, (CMT_RD_CMD1(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) |  (value)))
+#define CMT_CLR_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) & ~(value)))
+#define CMT_TOG_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD2 - CMT Modulator Data Register Mark Low
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD2 register
+ */
+/*@{*/
+#define CMT_RD_CMD2(base)        (CMT_CMD2_REG(base))
+#define CMT_WR_CMD2(base, value) (CMT_CMD2_REG(base) = (value))
+#define CMT_RMW_CMD2(base, mask, value) (CMT_WR_CMD2(base, (CMT_RD_CMD2(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) |  (value)))
+#define CMT_CLR_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) & ~(value)))
+#define CMT_TOG_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD3 - CMT Modulator Data Register Space High
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD3 - CMT Modulator Data Register Space High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD3 register
+ */
+/*@{*/
+#define CMT_RD_CMD3(base)        (CMT_CMD3_REG(base))
+#define CMT_WR_CMD3(base, value) (CMT_CMD3_REG(base) = (value))
+#define CMT_RMW_CMD3(base, mask, value) (CMT_WR_CMD3(base, (CMT_RD_CMD3(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) |  (value)))
+#define CMT_CLR_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) & ~(value)))
+#define CMT_TOG_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD4 - CMT Modulator Data Register Space Low
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD4 register
+ */
+/*@{*/
+#define CMT_RD_CMD4(base)        (CMT_CMD4_REG(base))
+#define CMT_WR_CMD4(base, value) (CMT_CMD4_REG(base) = (value))
+#define CMT_RMW_CMD4(base, mask, value) (CMT_WR_CMD4(base, (CMT_RD_CMD4(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) |  (value)))
+#define CMT_CLR_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) & ~(value)))
+#define CMT_TOG_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_PPS - CMT Primary Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_PPS - CMT Primary Prescaler Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to set the Primary Prescaler Divider field (PPSDIV).
+ */
+/*!
+ * @name Constants and macros for entire CMT_PPS register
+ */
+/*@{*/
+#define CMT_RD_PPS(base)         (CMT_PPS_REG(base))
+#define CMT_WR_PPS(base, value)  (CMT_PPS_REG(base) = (value))
+#define CMT_RMW_PPS(base, mask, value) (CMT_WR_PPS(base, (CMT_RD_PPS(base) & ~(mask)) | (value)))
+#define CMT_SET_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) |  (value)))
+#define CMT_CLR_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) & ~(value)))
+#define CMT_TOG_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_PPS bitfields
+ */
+
+/*!
+ * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
+ *
+ * Divides the CMT clock to generate the Intermediate Frequency clock enable to
+ * the secondary prescaler.
+ *
+ * Values:
+ * - 0b0000 - Bus clock * 1
+ * - 0b0001 - Bus clock * 2
+ * - 0b0010 - Bus clock * 3
+ * - 0b0011 - Bus clock * 4
+ * - 0b0100 - Bus clock * 5
+ * - 0b0101 - Bus clock * 6
+ * - 0b0110 - Bus clock * 7
+ * - 0b0111 - Bus clock * 8
+ * - 0b1000 - Bus clock * 9
+ * - 0b1001 - Bus clock * 10
+ * - 0b1010 - Bus clock * 11
+ * - 0b1011 - Bus clock * 12
+ * - 0b1100 - Bus clock * 13
+ * - 0b1101 - Bus clock * 14
+ * - 0b1110 - Bus clock * 15
+ * - 0b1111 - Bus clock * 16
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_PPS_PPSDIV field. */
+#define CMT_RD_PPS_PPSDIV(base) ((CMT_PPS_REG(base) & CMT_PPS_PPSDIV_MASK) >> CMT_PPS_PPSDIV_SHIFT)
+#define CMT_BRD_PPS_PPSDIV(base) (CMT_RD_PPS_PPSDIV(base))
+
+/*! @brief Set the PPSDIV field to a new value. */
+#define CMT_WR_PPS_PPSDIV(base, value) (CMT_RMW_PPS(base, CMT_PPS_PPSDIV_MASK, CMT_PPS_PPSDIV(value)))
+#define CMT_BWR_PPS_PPSDIV(base, value) (CMT_WR_PPS_PPSDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_DMA - CMT Direct Memory Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_DMA - CMT Direct Memory Access Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to enable/disable direct memory access (DMA).
+ */
+/*!
+ * @name Constants and macros for entire CMT_DMA register
+ */
+/*@{*/
+#define CMT_RD_DMA(base)         (CMT_DMA_REG(base))
+#define CMT_WR_DMA(base, value)  (CMT_DMA_REG(base) = (value))
+#define CMT_RMW_DMA(base, mask, value) (CMT_WR_DMA(base, (CMT_RD_DMA(base) & ~(mask)) | (value)))
+#define CMT_SET_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) |  (value)))
+#define CMT_CLR_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) & ~(value)))
+#define CMT_TOG_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_DMA bitfields
+ */
+
+/*!
+ * @name Register CMT_DMA, field DMA[0] (RW)
+ *
+ * Enables the DMA protocol.
+ *
+ * Values:
+ * - 0b0 - DMA transfer request and done are disabled.
+ * - 0b1 - DMA transfer request and done are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_DMA_DMA field. */
+#define CMT_RD_DMA_DMA(base) ((CMT_DMA_REG(base) & CMT_DMA_DMA_MASK) >> CMT_DMA_DMA_SHIFT)
+#define CMT_BRD_DMA_DMA(base) (BITBAND_ACCESS8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define CMT_WR_DMA_DMA(base, value) (CMT_RMW_DMA(base, CMT_DMA_DMA_MASK, CMT_DMA_DMA(value)))
+#define CMT_BWR_DMA_DMA(base, value) (BITBAND_ACCESS8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CRC
+ *
+ * Cyclic Redundancy Check
+ *
+ * Registers defined in this header file:
+ * - CRC_DATAL - CRC_DATAL register.
+ * - CRC_DATAH - CRC_DATAH register.
+ * - CRC_DATALL - CRC_DATALL register.
+ * - CRC_DATALU - CRC_DATALU register.
+ * - CRC_DATAHL - CRC_DATAHL register.
+ * - CRC_DATAHU - CRC_DATAHU register.
+ * - CRC_DATA - CRC Data register
+ * - CRC_GPOLY - CRC Polynomial register
+ * - CRC_GPOLYL - CRC_GPOLYL register.
+ * - CRC_GPOLYH - CRC_GPOLYH register.
+ * - CRC_GPOLYLL - CRC_GPOLYLL register.
+ * - CRC_GPOLYLU - CRC_GPOLYLU register.
+ * - CRC_GPOLYHL - CRC_GPOLYHL register.
+ * - CRC_GPOLYHU - CRC_GPOLYHU register.
+ * - CRC_CTRL - CRC Control register
+ * - CRC_CTRLHU - CRC_CTRLHU register.
+ */
+
+#define CRC_INSTANCE_COUNT (1U) /*!< Number of instances of the CRC module. */
+#define CRC_IDX (0U) /*!< Instance number for CRC. */
+
+/*******************************************************************************
+ * CRC_DATALL - CRC_DATALL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATALL - CRC_DATALL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATALL register
+ */
+/*@{*/
+#define CRC_RD_DATALL(base)      (CRC_DATALL_REG(base))
+#define CRC_WR_DATALL(base, value) (CRC_DATALL_REG(base) = (value))
+#define CRC_RMW_DATALL(base, mask, value) (CRC_WR_DATALL(base, (CRC_RD_DATALL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) |  (value)))
+#define CRC_CLR_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) & ~(value)))
+#define CRC_TOG_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAL - CRC_DATAL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAL - CRC_DATAL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAL register
+ */
+/*@{*/
+#define CRC_RD_DATAL(base)       (CRC_DATAL_REG(base))
+#define CRC_WR_DATAL(base, value) (CRC_DATAL_REG(base) = (value))
+#define CRC_RMW_DATAL(base, mask, value) (CRC_WR_DATAL(base, (CRC_RD_DATAL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) |  (value)))
+#define CRC_CLR_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) & ~(value)))
+#define CRC_TOG_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATA - CRC Data register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATA - CRC Data register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * The CRC Data register contains the value of the seed, data, and checksum.
+ * When CTRL[WAS] is set, any write to the data register is regarded as the seed
+ * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
+ * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
+ * not used for programming the seed value, and reads of these fields return an
+ * indeterminate value. In 32-bit CRC mode, all fields are used for programming
+ * the seed value. When programming data values, the values can be written 8 bits,
+ * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
+ * data value written first. After all data values are written, the CRC result
+ * can be read from this data register. In 16-bit CRC mode, the CRC result is
+ * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
+ * result. Reads of this register at any time return the intermediate CRC value,
+ * provided the CRC module is configured.
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATA register
+ */
+/*@{*/
+#define CRC_RD_DATA(base)        (CRC_DATA_REG(base))
+#define CRC_WR_DATA(base, value) (CRC_DATA_REG(base) = (value))
+#define CRC_RMW_DATA(base, mask, value) (CRC_WR_DATA(base, (CRC_RD_DATA(base) & ~(mask)) | (value)))
+#define CRC_SET_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) |  (value)))
+#define CRC_CLR_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) & ~(value)))
+#define CRC_TOG_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_DATA bitfields
+ */
+
+/*!
+ * @name Register CRC_DATA, field LL[7:0] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_LL field. */
+#define CRC_RD_DATA_LL(base) ((CRC_DATA_REG(base) & CRC_DATA_LL_MASK) >> CRC_DATA_LL_SHIFT)
+#define CRC_BRD_DATA_LL(base) (CRC_RD_DATA_LL(base))
+
+/*! @brief Set the LL field to a new value. */
+#define CRC_WR_DATA_LL(base, value) (CRC_RMW_DATA(base, CRC_DATA_LL_MASK, CRC_DATA_LL(value)))
+#define CRC_BWR_DATA_LL(base, value) (CRC_WR_DATA_LL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field LU[15:8] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_LU field. */
+#define CRC_RD_DATA_LU(base) ((CRC_DATA_REG(base) & CRC_DATA_LU_MASK) >> CRC_DATA_LU_SHIFT)
+#define CRC_BRD_DATA_LU(base) (CRC_RD_DATA_LU(base))
+
+/*! @brief Set the LU field to a new value. */
+#define CRC_WR_DATA_LU(base, value) (CRC_RMW_DATA(base, CRC_DATA_LU_MASK, CRC_DATA_LU(value)))
+#define CRC_BWR_DATA_LU(base, value) (CRC_WR_DATA_LU(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field HL[23:16] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_HL field. */
+#define CRC_RD_DATA_HL(base) ((CRC_DATA_REG(base) & CRC_DATA_HL_MASK) >> CRC_DATA_HL_SHIFT)
+#define CRC_BRD_DATA_HL(base) (CRC_RD_DATA_HL(base))
+
+/*! @brief Set the HL field to a new value. */
+#define CRC_WR_DATA_HL(base, value) (CRC_RMW_DATA(base, CRC_DATA_HL_MASK, CRC_DATA_HL(value)))
+#define CRC_BWR_DATA_HL(base, value) (CRC_WR_DATA_HL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field HU[31:24] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_HU field. */
+#define CRC_RD_DATA_HU(base) ((CRC_DATA_REG(base) & CRC_DATA_HU_MASK) >> CRC_DATA_HU_SHIFT)
+#define CRC_BRD_DATA_HU(base) (CRC_RD_DATA_HU(base))
+
+/*! @brief Set the HU field to a new value. */
+#define CRC_WR_DATA_HU(base, value) (CRC_RMW_DATA(base, CRC_DATA_HU_MASK, CRC_DATA_HU(value)))
+#define CRC_BWR_DATA_HU(base, value) (CRC_WR_DATA_HU(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATALU - CRC_DATALU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATALU - CRC_DATALU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATALU register
+ */
+/*@{*/
+#define CRC_RD_DATALU(base)      (CRC_DATALU_REG(base))
+#define CRC_WR_DATALU(base, value) (CRC_DATALU_REG(base) = (value))
+#define CRC_RMW_DATALU(base, mask, value) (CRC_WR_DATALU(base, (CRC_RD_DATALU(base) & ~(mask)) | (value)))
+#define CRC_SET_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) |  (value)))
+#define CRC_CLR_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) & ~(value)))
+#define CRC_TOG_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAHL - CRC_DATAHL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAHL - CRC_DATAHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAHL register
+ */
+/*@{*/
+#define CRC_RD_DATAHL(base)      (CRC_DATAHL_REG(base))
+#define CRC_WR_DATAHL(base, value) (CRC_DATAHL_REG(base) = (value))
+#define CRC_RMW_DATAHL(base, mask, value) (CRC_WR_DATAHL(base, (CRC_RD_DATAHL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) |  (value)))
+#define CRC_CLR_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) & ~(value)))
+#define CRC_TOG_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAH - CRC_DATAH register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAH - CRC_DATAH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAH register
+ */
+/*@{*/
+#define CRC_RD_DATAH(base)       (CRC_DATAH_REG(base))
+#define CRC_WR_DATAH(base, value) (CRC_DATAH_REG(base) = (value))
+#define CRC_RMW_DATAH(base, mask, value) (CRC_WR_DATAH(base, (CRC_RD_DATAH(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) |  (value)))
+#define CRC_CLR_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) & ~(value)))
+#define CRC_TOG_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAHU - CRC_DATAHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAHU - CRC_DATAHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAHU register
+ */
+/*@{*/
+#define CRC_RD_DATAHU(base)      (CRC_DATAHU_REG(base))
+#define CRC_WR_DATAHU(base, value) (CRC_DATAHU_REG(base) = (value))
+#define CRC_RMW_DATAHU(base, mask, value) (CRC_WR_DATAHU(base, (CRC_RD_DATAHU(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) |  (value)))
+#define CRC_CLR_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) & ~(value)))
+#define CRC_TOG_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYLL - CRC_GPOLYLL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYLL(base)     (CRC_GPOLYLL_REG(base))
+#define CRC_WR_GPOLYLL(base, value) (CRC_GPOLYLL_REG(base) = (value))
+#define CRC_RMW_GPOLYLL(base, mask, value) (CRC_WR_GPOLYLL(base, (CRC_RD_GPOLYLL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) |  (value)))
+#define CRC_CLR_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) & ~(value)))
+#define CRC_TOG_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLY - CRC Polynomial register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLY - CRC Polynomial register (RW)
+ *
+ * Reset value: 0x00001021U
+ *
+ * This register contains the value of the polynomial for the CRC calculation.
+ * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
+ * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
+ * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
+ * used in both 16- and 32-bit CRC modes.
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLY register
+ */
+/*@{*/
+#define CRC_RD_GPOLY(base)       (CRC_GPOLY_REG(base))
+#define CRC_WR_GPOLY(base, value) (CRC_GPOLY_REG(base) = (value))
+#define CRC_RMW_GPOLY(base, mask, value) (CRC_WR_GPOLY(base, (CRC_RD_GPOLY(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) |  (value)))
+#define CRC_CLR_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) & ~(value)))
+#define CRC_TOG_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_GPOLY bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLY, field LOW[15:0] (RW)
+ *
+ * Writable and readable in both 32-bit and 16-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_GPOLY_LOW field. */
+#define CRC_RD_GPOLY_LOW(base) ((CRC_GPOLY_REG(base) & CRC_GPOLY_LOW_MASK) >> CRC_GPOLY_LOW_SHIFT)
+#define CRC_BRD_GPOLY_LOW(base) (CRC_RD_GPOLY_LOW(base))
+
+/*! @brief Set the LOW field to a new value. */
+#define CRC_WR_GPOLY_LOW(base, value) (CRC_RMW_GPOLY(base, CRC_GPOLY_LOW_MASK, CRC_GPOLY_LOW(value)))
+#define CRC_BWR_GPOLY_LOW(base, value) (CRC_WR_GPOLY_LOW(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
+ *
+ * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
+ * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_GPOLY_HIGH field. */
+#define CRC_RD_GPOLY_HIGH(base) ((CRC_GPOLY_REG(base) & CRC_GPOLY_HIGH_MASK) >> CRC_GPOLY_HIGH_SHIFT)
+#define CRC_BRD_GPOLY_HIGH(base) (CRC_RD_GPOLY_HIGH(base))
+
+/*! @brief Set the HIGH field to a new value. */
+#define CRC_WR_GPOLY_HIGH(base, value) (CRC_RMW_GPOLY(base, CRC_GPOLY_HIGH_MASK, CRC_GPOLY_HIGH(value)))
+#define CRC_BWR_GPOLY_HIGH(base, value) (CRC_WR_GPOLY_HIGH(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYL - CRC_GPOLYL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYL - CRC_GPOLYL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYL(base)      (CRC_GPOLYL_REG(base))
+#define CRC_WR_GPOLYL(base, value) (CRC_GPOLYL_REG(base) = (value))
+#define CRC_RMW_GPOLYL(base, mask, value) (CRC_WR_GPOLYL(base, (CRC_RD_GPOLYL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) |  (value)))
+#define CRC_CLR_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) & ~(value)))
+#define CRC_TOG_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYLU - CRC_GPOLYLU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLU register
+ */
+/*@{*/
+#define CRC_RD_GPOLYLU(base)     (CRC_GPOLYLU_REG(base))
+#define CRC_WR_GPOLYLU(base, value) (CRC_GPOLYLU_REG(base) = (value))
+#define CRC_RMW_GPOLYLU(base, mask, value) (CRC_WR_GPOLYLU(base, (CRC_RD_GPOLYLU(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) |  (value)))
+#define CRC_CLR_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) & ~(value)))
+#define CRC_TOG_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYH - CRC_GPOLYH register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYH - CRC_GPOLYH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYH register
+ */
+/*@{*/
+#define CRC_RD_GPOLYH(base)      (CRC_GPOLYH_REG(base))
+#define CRC_WR_GPOLYH(base, value) (CRC_GPOLYH_REG(base) = (value))
+#define CRC_RMW_GPOLYH(base, mask, value) (CRC_WR_GPOLYH(base, (CRC_RD_GPOLYH(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) |  (value)))
+#define CRC_CLR_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) & ~(value)))
+#define CRC_TOG_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYHL - CRC_GPOLYHL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYHL(base)     (CRC_GPOLYHL_REG(base))
+#define CRC_WR_GPOLYHL(base, value) (CRC_GPOLYHL_REG(base) = (value))
+#define CRC_RMW_GPOLYHL(base, mask, value) (CRC_WR_GPOLYHL(base, (CRC_RD_GPOLYHL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) |  (value)))
+#define CRC_CLR_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) & ~(value)))
+#define CRC_TOG_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYHU - CRC_GPOLYHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHU register
+ */
+/*@{*/
+#define CRC_RD_GPOLYHU(base)     (CRC_GPOLYHU_REG(base))
+#define CRC_WR_GPOLYHU(base, value) (CRC_GPOLYHU_REG(base) = (value))
+#define CRC_RMW_GPOLYHU(base, mask, value) (CRC_WR_GPOLYHU(base, (CRC_RD_GPOLYHU(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) |  (value)))
+#define CRC_CLR_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) & ~(value)))
+#define CRC_TOG_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_CTRL - CRC Control register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_CTRL - CRC Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls the configuration and working of the CRC module.
+ * Appropriate bits must be set before starting a new CRC calculation. A new CRC
+ * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
+ * the CRC data register.
+ */
+/*!
+ * @name Constants and macros for entire CRC_CTRL register
+ */
+/*@{*/
+#define CRC_RD_CTRL(base)        (CRC_CTRL_REG(base))
+#define CRC_WR_CTRL(base, value) (CRC_CTRL_REG(base) = (value))
+#define CRC_RMW_CTRL(base, mask, value) (CRC_WR_CTRL(base, (CRC_RD_CTRL(base) & ~(mask)) | (value)))
+#define CRC_SET_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) |  (value)))
+#define CRC_CLR_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) & ~(value)))
+#define CRC_TOG_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_CTRL bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRL, field TCRC[24] (RW)
+ *
+ * Width of CRC protocol.
+ *
+ * Values:
+ * - 0b0 - 16-bit CRC protocol.
+ * - 0b1 - 32-bit CRC protocol.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TCRC field. */
+#define CRC_RD_CTRL_TCRC(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TCRC_MASK) >> CRC_CTRL_TCRC_SHIFT)
+#define CRC_BRD_CTRL_TCRC(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_TCRC_SHIFT))
+
+/*! @brief Set the TCRC field to a new value. */
+#define CRC_WR_CTRL_TCRC(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TCRC_MASK, CRC_CTRL_TCRC(value)))
+#define CRC_BWR_CTRL_TCRC(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_TCRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field WAS[25] (RW)
+ *
+ * When asserted, a value written to the CRC data register is considered a seed
+ * value. When deasserted, a value written to the CRC data register is taken as
+ * data for CRC computation.
+ *
+ * Values:
+ * - 0b0 - Writes to the CRC data register are data values.
+ * - 0b1 - Writes to the CRC data register are seed values.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_WAS field. */
+#define CRC_RD_CTRL_WAS(base) ((CRC_CTRL_REG(base) & CRC_CTRL_WAS_MASK) >> CRC_CTRL_WAS_SHIFT)
+#define CRC_BRD_CTRL_WAS(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_WAS_SHIFT))
+
+/*! @brief Set the WAS field to a new value. */
+#define CRC_WR_CTRL_WAS(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_WAS_MASK, CRC_CTRL_WAS(value)))
+#define CRC_BWR_CTRL_WAS(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_WAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field FXOR[26] (RW)
+ *
+ * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
+ * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
+ *
+ * Values:
+ * - 0b0 - No XOR on reading.
+ * - 0b1 - Invert or complement the read value of the CRC Data register.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_FXOR field. */
+#define CRC_RD_CTRL_FXOR(base) ((CRC_CTRL_REG(base) & CRC_CTRL_FXOR_MASK) >> CRC_CTRL_FXOR_SHIFT)
+#define CRC_BRD_CTRL_FXOR(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_FXOR_SHIFT))
+
+/*! @brief Set the FXOR field to a new value. */
+#define CRC_WR_CTRL_FXOR(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_FXOR_MASK, CRC_CTRL_FXOR(value)))
+#define CRC_BWR_CTRL_FXOR(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_FXOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field TOTR[29:28] (RW)
+ *
+ * Identifies the transpose configuration of the value read from the CRC Data
+ * register. See the description of the transpose feature for the available
+ * transpose options.
+ *
+ * Values:
+ * - 0b00 - No transposition.
+ * - 0b01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TOTR field. */
+#define CRC_RD_CTRL_TOTR(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT)
+#define CRC_BRD_CTRL_TOTR(base) (CRC_RD_CTRL_TOTR(base))
+
+/*! @brief Set the TOTR field to a new value. */
+#define CRC_WR_CTRL_TOTR(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TOTR_MASK, CRC_CTRL_TOTR(value)))
+#define CRC_BWR_CTRL_TOTR(base, value) (CRC_WR_CTRL_TOTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field TOT[31:30] (RW)
+ *
+ * Defines the transpose configuration of the data written to the CRC data
+ * register. See the description of the transpose feature for the available transpose
+ * options.
+ *
+ * Values:
+ * - 0b00 - No transposition.
+ * - 0b01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TOT field. */
+#define CRC_RD_CTRL_TOT(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TOT_MASK) >> CRC_CTRL_TOT_SHIFT)
+#define CRC_BRD_CTRL_TOT(base) (CRC_RD_CTRL_TOT(base))
+
+/*! @brief Set the TOT field to a new value. */
+#define CRC_WR_CTRL_TOT(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TOT_MASK, CRC_CTRL_TOT(value)))
+#define CRC_BWR_CTRL_TOT(base, value) (CRC_WR_CTRL_TOT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_CTRLHU - CRC_CTRLHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_CTRLHU - CRC_CTRLHU register. (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CRC_CTRLHU register
+ */
+/*@{*/
+#define CRC_RD_CTRLHU(base)      (CRC_CTRLHU_REG(base))
+#define CRC_WR_CTRLHU(base, value) (CRC_CTRLHU_REG(base) = (value))
+#define CRC_RMW_CTRLHU(base, mask, value) (CRC_WR_CTRLHU(base, (CRC_RD_CTRLHU(base) & ~(mask)) | (value)))
+#define CRC_SET_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) |  (value)))
+#define CRC_CLR_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) & ~(value)))
+#define CRC_TOG_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_CTRLHU bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRLHU, field TCRC[0] (RW)
+ *
+ * Values:
+ * - 0b0 - 16-bit CRC protocol.
+ * - 0b1 - 32-bit CRC protocol.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TCRC field. */
+#define CRC_RD_CTRLHU_TCRC(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TCRC_MASK) >> CRC_CTRLHU_TCRC_SHIFT)
+#define CRC_BRD_CTRLHU_TCRC(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_TCRC_SHIFT))
+
+/*! @brief Set the TCRC field to a new value. */
+#define CRC_WR_CTRLHU_TCRC(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TCRC_MASK, CRC_CTRLHU_TCRC(value)))
+#define CRC_BWR_CTRLHU_TCRC(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_TCRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field WAS[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Writes to CRC data register are data values.
+ * - 0b1 - Writes to CRC data reguster are seed values.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_WAS field. */
+#define CRC_RD_CTRLHU_WAS(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_WAS_MASK) >> CRC_CTRLHU_WAS_SHIFT)
+#define CRC_BRD_CTRLHU_WAS(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_WAS_SHIFT))
+
+/*! @brief Set the WAS field to a new value. */
+#define CRC_WR_CTRLHU_WAS(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_WAS_MASK, CRC_CTRLHU_WAS(value)))
+#define CRC_BWR_CTRLHU_WAS(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_WAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field FXOR[2] (RW)
+ *
+ * Values:
+ * - 0b0 - No XOR on reading.
+ * - 0b1 - Invert or complement the read value of CRC data register.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_FXOR field. */
+#define CRC_RD_CTRLHU_FXOR(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_FXOR_MASK) >> CRC_CTRLHU_FXOR_SHIFT)
+#define CRC_BRD_CTRLHU_FXOR(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_FXOR_SHIFT))
+
+/*! @brief Set the FXOR field to a new value. */
+#define CRC_WR_CTRLHU_FXOR(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_FXOR_MASK, CRC_CTRLHU_FXOR(value)))
+#define CRC_BWR_CTRLHU_FXOR(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_FXOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
+ *
+ * Values:
+ * - 0b00 - No Transposition.
+ * - 0b01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TOTR field. */
+#define CRC_RD_CTRLHU_TOTR(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TOTR_MASK) >> CRC_CTRLHU_TOTR_SHIFT)
+#define CRC_BRD_CTRLHU_TOTR(base) (CRC_RD_CTRLHU_TOTR(base))
+
+/*! @brief Set the TOTR field to a new value. */
+#define CRC_WR_CTRLHU_TOTR(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TOTR_MASK, CRC_CTRLHU_TOTR(value)))
+#define CRC_BWR_CTRLHU_TOTR(base, value) (CRC_WR_CTRLHU_TOTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
+ *
+ * Values:
+ * - 0b00 - No Transposition.
+ * - 0b01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TOT field. */
+#define CRC_RD_CTRLHU_TOT(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TOT_MASK) >> CRC_CTRLHU_TOT_SHIFT)
+#define CRC_BRD_CTRLHU_TOT(base) (CRC_RD_CTRLHU_TOT(base))
+
+/*! @brief Set the TOT field to a new value. */
+#define CRC_WR_CTRLHU_TOT(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TOT_MASK, CRC_CTRLHU_TOT(value)))
+#define CRC_BWR_CTRLHU_TOT(base, value) (CRC_WR_CTRLHU_TOT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 DAC
+ *
+ * 12-Bit Digital-to-Analog Converter
+ *
+ * Registers defined in this header file:
+ * - DAC_DATL - DAC Data Low Register
+ * - DAC_DATH - DAC Data High Register
+ * - DAC_SR - DAC Status Register
+ * - DAC_C0 - DAC Control Register
+ * - DAC_C1 - DAC Control Register 1
+ * - DAC_C2 - DAC Control Register 2
+ */
+
+#define DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
+#define DAC0_IDX (0U) /*!< Instance number for DAC0. */
+#define DAC1_IDX (1U) /*!< Instance number for DAC1. */
+
+/*******************************************************************************
+ * DAC_DATL - DAC Data Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATL - DAC Data Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATL register
+ */
+/*@{*/
+#define DAC_RD_DATL(base, index) (DAC_DATL_REG(base, index))
+#define DAC_WR_DATL(base, index, value) (DAC_DATL_REG(base, index) = (value))
+#define DAC_RMW_DATL(base, index, mask, value) (DAC_WR_DATL(base, index, (DAC_RD_DATL(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) |  (value)))
+#define DAC_CLR_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) & ~(value)))
+#define DAC_TOG_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_DATH - DAC Data High Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATH - DAC Data High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATH register
+ */
+/*@{*/
+#define DAC_RD_DATH(base, index) (DAC_DATH_REG(base, index))
+#define DAC_WR_DATH(base, index, value) (DAC_DATH_REG(base, index) = (value))
+#define DAC_RMW_DATH(base, index, mask, value) (DAC_WR_DATH(base, index, (DAC_RD_DATH(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) |  (value)))
+#define DAC_CLR_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) & ~(value)))
+#define DAC_TOG_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_DATH bitfields
+ */
+
+/*!
+ * @name Register DAC_DATH, field DATA1[3:0] (RW)
+ *
+ * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
+ * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
+ * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_DATH_DATA1 field. */
+#define DAC_RD_DATH_DATA1(base, index) ((DAC_DATH_REG(base, index) & DAC_DATH_DATA1_MASK) >> DAC_DATH_DATA1_SHIFT)
+#define DAC_BRD_DATH_DATA1(base, index) (DAC_RD_DATH_DATA1(base, index))
+
+/*! @brief Set the DATA1 field to a new value. */
+#define DAC_WR_DATH_DATA1(base, index, value) (DAC_RMW_DATH(base, index, DAC_DATH_DATA1_MASK, DAC_DATH_DATA1(value)))
+#define DAC_BWR_DATH_DATA1(base, index, value) (DAC_WR_DATH_DATA1(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_SR - DAC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_SR - DAC Status Register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
+ * request is done. Writing 0 to a field clears it whereas writing 1 has no
+ * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
+ * The flags are set only when the data buffer status is changed. Do not use
+ * 32/16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_SR register
+ */
+/*@{*/
+#define DAC_RD_SR(base)          (DAC_SR_REG(base))
+#define DAC_WR_SR(base, value)   (DAC_SR_REG(base) = (value))
+#define DAC_RMW_SR(base, mask, value) (DAC_WR_SR(base, (DAC_RD_SR(base) & ~(mask)) | (value)))
+#define DAC_SET_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) |  (value)))
+#define DAC_CLR_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) & ~(value)))
+#define DAC_TOG_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_SR bitfields
+ */
+
+/*!
+ * @name Register DAC_SR, field DACBFRPBF[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
+ * - 0b1 - The DAC buffer read pointer is equal to C2[DACBFUP].
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
+#define DAC_RD_SR_DACBFRPBF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPBF_MASK) >> DAC_SR_DACBFRPBF_SHIFT)
+#define DAC_BRD_SR_DACBFRPBF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT))
+
+/*! @brief Set the DACBFRPBF field to a new value. */
+#define DAC_WR_SR_DACBFRPBF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPBF_MASK, DAC_SR_DACBFRPBF(value)))
+#define DAC_BWR_SR_DACBFRPBF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFRPTF[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer is not zero.
+ * - 0b1 - The DAC buffer read pointer is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
+#define DAC_RD_SR_DACBFRPTF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPTF_MASK) >> DAC_SR_DACBFRPTF_SHIFT)
+#define DAC_BRD_SR_DACBFRPTF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT))
+
+/*! @brief Set the DACBFRPTF field to a new value. */
+#define DAC_WR_SR_DACBFRPTF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPTF_MASK, DAC_SR_DACBFRPTF(value)))
+#define DAC_BWR_SR_DACBFRPTF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFWMF[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer has not reached the watermark level.
+ * - 0b1 - The DAC buffer read pointer has reached the watermark level.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFWMF field. */
+#define DAC_RD_SR_DACBFWMF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFWMF_MASK) >> DAC_SR_DACBFWMF_SHIFT)
+#define DAC_BRD_SR_DACBFWMF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFWMF_SHIFT))
+
+/*! @brief Set the DACBFWMF field to a new value. */
+#define DAC_WR_SR_DACBFWMF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFWMF_MASK, DAC_SR_DACBFWMF(value)))
+#define DAC_BWR_SR_DACBFWMF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFWMF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C0 - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C0 - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_C0 register
+ */
+/*@{*/
+#define DAC_RD_C0(base)          (DAC_C0_REG(base))
+#define DAC_WR_C0(base, value)   (DAC_C0_REG(base) = (value))
+#define DAC_RMW_C0(base, mask, value) (DAC_WR_C0(base, (DAC_RD_C0(base) & ~(mask)) | (value)))
+#define DAC_SET_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) |  (value)))
+#define DAC_CLR_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) & ~(value)))
+#define DAC_TOG_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C0 bitfields
+ */
+
+/*!
+ * @name Register DAC_C0, field DACBBIEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer bottom flag interrupt is disabled.
+ * - 0b1 - The DAC buffer read pointer bottom flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBBIEN field. */
+#define DAC_RD_C0_DACBBIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBBIEN_MASK) >> DAC_C0_DACBBIEN_SHIFT)
+#define DAC_BRD_C0_DACBBIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT))
+
+/*! @brief Set the DACBBIEN field to a new value. */
+#define DAC_WR_C0_DACBBIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBBIEN_MASK, DAC_C0_DACBBIEN(value)))
+#define DAC_BWR_C0_DACBBIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBTIEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer top flag interrupt is disabled.
+ * - 0b1 - The DAC buffer read pointer top flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBTIEN field. */
+#define DAC_RD_C0_DACBTIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBTIEN_MASK) >> DAC_C0_DACBTIEN_SHIFT)
+#define DAC_BRD_C0_DACBTIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT))
+
+/*! @brief Set the DACBTIEN field to a new value. */
+#define DAC_WR_C0_DACBTIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBTIEN_MASK, DAC_C0_DACBTIEN(value)))
+#define DAC_BWR_C0_DACBTIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBWIEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer watermark interrupt is disabled.
+ * - 0b1 - The DAC buffer watermark interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBWIEN field. */
+#define DAC_RD_C0_DACBWIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBWIEN_MASK) >> DAC_C0_DACBWIEN_SHIFT)
+#define DAC_BRD_C0_DACBWIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBWIEN_SHIFT))
+
+/*! @brief Set the DACBWIEN field to a new value. */
+#define DAC_WR_C0_DACBWIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBWIEN_MASK, DAC_C0_DACBWIEN(value)))
+#define DAC_BWR_C0_DACBWIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBWIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field LPEN[3] (RW)
+ *
+ * See the 12-bit DAC electrical characteristics of the device data sheet for
+ * details on the impact of the modes below.
+ *
+ * Values:
+ * - 0b0 - High-Power mode
+ * - 0b1 - Low-Power mode
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_LPEN field. */
+#define DAC_RD_C0_LPEN(base) ((DAC_C0_REG(base) & DAC_C0_LPEN_MASK) >> DAC_C0_LPEN_SHIFT)
+#define DAC_BRD_C0_LPEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT))
+
+/*! @brief Set the LPEN field to a new value. */
+#define DAC_WR_C0_LPEN(base, value) (DAC_RMW_C0(base, DAC_C0_LPEN_MASK, DAC_C0_LPEN(value)))
+#define DAC_BWR_C0_LPEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
+ *
+ * Active high. This is a write-only field, which always reads 0. If DAC
+ * software trigger is selected and buffer is enabled, writing 1 to this field will
+ * advance the buffer read pointer once.
+ *
+ * Values:
+ * - 0b0 - The DAC soft trigger is not valid.
+ * - 0b1 - The DAC soft trigger is valid.
+ */
+/*@{*/
+/*! @brief Set the DACSWTRG field to a new value. */
+#define DAC_WR_C0_DACSWTRG(base, value) (DAC_RMW_C0(base, DAC_C0_DACSWTRG_MASK, DAC_C0_DACSWTRG(value)))
+#define DAC_BWR_C0_DACSWTRG(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACSWTRG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACTRGSEL[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC hardware trigger is selected.
+ * - 0b1 - The DAC software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
+#define DAC_RD_C0_DACTRGSEL(base) ((DAC_C0_REG(base) & DAC_C0_DACTRGSEL_MASK) >> DAC_C0_DACTRGSEL_SHIFT)
+#define DAC_BRD_C0_DACTRGSEL(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT))
+
+/*! @brief Set the DACTRGSEL field to a new value. */
+#define DAC_WR_C0_DACTRGSEL(base, value) (DAC_RMW_C0(base, DAC_C0_DACTRGSEL_MASK, DAC_C0_DACTRGSEL(value)))
+#define DAC_BWR_C0_DACTRGSEL(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACRFS[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC selects DACREF_1 as the reference voltage.
+ * - 0b1 - The DAC selects DACREF_2 as the reference voltage.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACRFS field. */
+#define DAC_RD_C0_DACRFS(base) ((DAC_C0_REG(base) & DAC_C0_DACRFS_MASK) >> DAC_C0_DACRFS_SHIFT)
+#define DAC_BRD_C0_DACRFS(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT))
+
+/*! @brief Set the DACRFS field to a new value. */
+#define DAC_WR_C0_DACRFS(base, value) (DAC_RMW_C0(base, DAC_C0_DACRFS_MASK, DAC_C0_DACRFS(value)))
+#define DAC_BWR_C0_DACRFS(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACEN[7] (RW)
+ *
+ * Starts the Programmable Reference Generator operation.
+ *
+ * Values:
+ * - 0b0 - The DAC system is disabled.
+ * - 0b1 - The DAC system is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACEN field. */
+#define DAC_RD_C0_DACEN(base) ((DAC_C0_REG(base) & DAC_C0_DACEN_MASK) >> DAC_C0_DACEN_SHIFT)
+#define DAC_BRD_C0_DACEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT))
+
+/*! @brief Set the DACEN field to a new value. */
+#define DAC_WR_C0_DACEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACEN_MASK, DAC_C0_DACEN(value)))
+#define DAC_BWR_C0_DACEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C1 - DAC Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C1 - DAC Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_C1 register
+ */
+/*@{*/
+#define DAC_RD_C1(base)          (DAC_C1_REG(base))
+#define DAC_WR_C1(base, value)   (DAC_C1_REG(base) = (value))
+#define DAC_RMW_C1(base, mask, value) (DAC_WR_C1(base, (DAC_RD_C1(base) & ~(mask)) | (value)))
+#define DAC_SET_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) |  (value)))
+#define DAC_CLR_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) & ~(value)))
+#define DAC_TOG_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C1 bitfields
+ */
+
+/*!
+ * @name Register DAC_C1, field DACBFEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Buffer read pointer is disabled. The converted data is always the
+ *     first word of the buffer.
+ * - 0b1 - Buffer read pointer is enabled. The converted data is the word that
+ *     the read pointer points to. It means converted data can be from any word of
+ *     the buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFEN field. */
+#define DAC_RD_C1_DACBFEN(base) ((DAC_C1_REG(base) & DAC_C1_DACBFEN_MASK) >> DAC_C1_DACBFEN_SHIFT)
+#define DAC_BRD_C1_DACBFEN(base) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT))
+
+/*! @brief Set the DACBFEN field to a new value. */
+#define DAC_WR_C1_DACBFEN(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFEN_MASK, DAC_C1_DACBFEN(value)))
+#define DAC_BWR_C1_DACBFEN(base, value) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFMD[2:1] (RW)
+ *
+ * Values:
+ * - 0b00 - Normal mode
+ * - 0b01 - Swing mode
+ * - 0b10 - One-Time Scan mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFMD field. */
+#define DAC_RD_C1_DACBFMD(base) ((DAC_C1_REG(base) & DAC_C1_DACBFMD_MASK) >> DAC_C1_DACBFMD_SHIFT)
+#define DAC_BRD_C1_DACBFMD(base) (DAC_RD_C1_DACBFMD(base))
+
+/*! @brief Set the DACBFMD field to a new value. */
+#define DAC_WR_C1_DACBFMD(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFMD_MASK, DAC_C1_DACBFMD(value)))
+#define DAC_BWR_C1_DACBFMD(base, value) (DAC_WR_C1_DACBFMD(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFWM[4:3] (RW)
+ *
+ * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
+ * the word defined by this field, which is 1-4 words away from the upper limit
+ * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
+ * watermark interrupt.
+ *
+ * Values:
+ * - 0b00 - 1 word
+ * - 0b01 - 2 words
+ * - 0b10 - 3 words
+ * - 0b11 - 4 words
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFWM field. */
+#define DAC_RD_C1_DACBFWM(base) ((DAC_C1_REG(base) & DAC_C1_DACBFWM_MASK) >> DAC_C1_DACBFWM_SHIFT)
+#define DAC_BRD_C1_DACBFWM(base) (DAC_RD_C1_DACBFWM(base))
+
+/*! @brief Set the DACBFWM field to a new value. */
+#define DAC_WR_C1_DACBFWM(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFWM_MASK, DAC_C1_DACBFWM(value)))
+#define DAC_BWR_C1_DACBFWM(base, value) (DAC_WR_C1_DACBFWM(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DMAEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled. When DMA is enabled, the DMA request will be
+ *     generated by original interrupts. The interrupts will not be presented on this
+ *     module at the same time.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DMAEN field. */
+#define DAC_RD_C1_DMAEN(base) ((DAC_C1_REG(base) & DAC_C1_DMAEN_MASK) >> DAC_C1_DMAEN_SHIFT)
+#define DAC_BRD_C1_DMAEN(base) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define DAC_WR_C1_DMAEN(base, value) (DAC_RMW_C1(base, DAC_C1_DMAEN_MASK, DAC_C1_DMAEN(value)))
+#define DAC_BWR_C1_DMAEN(base, value) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C2 - DAC Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C2 - DAC Control Register 2 (RW)
+ *
+ * Reset value: 0x0FU
+ */
+/*!
+ * @name Constants and macros for entire DAC_C2 register
+ */
+/*@{*/
+#define DAC_RD_C2(base)          (DAC_C2_REG(base))
+#define DAC_WR_C2(base, value)   (DAC_C2_REG(base) = (value))
+#define DAC_RMW_C2(base, mask, value) (DAC_WR_C2(base, (DAC_RD_C2(base) & ~(mask)) | (value)))
+#define DAC_SET_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) |  (value)))
+#define DAC_CLR_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) & ~(value)))
+#define DAC_TOG_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C2 bitfields
+ */
+
+/*!
+ * @name Register DAC_C2, field DACBFUP[3:0] (RW)
+ *
+ * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
+ * exceed it.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFUP field. */
+#define DAC_RD_C2_DACBFUP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFUP_MASK) >> DAC_C2_DACBFUP_SHIFT)
+#define DAC_BRD_C2_DACBFUP(base) (DAC_RD_C2_DACBFUP(base))
+
+/*! @brief Set the DACBFUP field to a new value. */
+#define DAC_WR_C2_DACBFUP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFUP_MASK, DAC_C2_DACBFUP(value)))
+#define DAC_BWR_C2_DACBFUP(base, value) (DAC_WR_C2_DACBFUP(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C2, field DACBFRP[7:4] (RW)
+ *
+ * Keeps the current value of the buffer read pointer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFRP field. */
+#define DAC_RD_C2_DACBFRP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT)
+#define DAC_BRD_C2_DACBFRP(base) (DAC_RD_C2_DACBFRP(base))
+
+/*! @brief Set the DACBFRP field to a new value. */
+#define DAC_WR_C2_DACBFRP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFRP_MASK, DAC_C2_DACBFRP(value)))
+#define DAC_BWR_C2_DACBFRP(base, value) (DAC_WR_C2_DACBFRP(base, value))
+/*@}*/
+
+/*
+ * MK64F12 DMA
+ *
+ * Enhanced direct memory access controller
+ *
+ * Registers defined in this header file:
+ * - DMA_CR - Control Register
+ * - DMA_ES - Error Status Register
+ * - DMA_ERQ - Enable Request Register
+ * - DMA_EEI - Enable Error Interrupt Register
+ * - DMA_CEEI - Clear Enable Error Interrupt Register
+ * - DMA_SEEI - Set Enable Error Interrupt Register
+ * - DMA_CERQ - Clear Enable Request Register
+ * - DMA_SERQ - Set Enable Request Register
+ * - DMA_CDNE - Clear DONE Status Bit Register
+ * - DMA_SSRT - Set START Bit Register
+ * - DMA_CERR - Clear Error Register
+ * - DMA_CINT - Clear Interrupt Request Register
+ * - DMA_INT - Interrupt Request Register
+ * - DMA_ERR - Error Register
+ * - DMA_HRS - Hardware Request Status Register
+ * - DMA_DCHPRI3 - Channel n Priority Register
+ * - DMA_DCHPRI2 - Channel n Priority Register
+ * - DMA_DCHPRI1 - Channel n Priority Register
+ * - DMA_DCHPRI0 - Channel n Priority Register
+ * - DMA_DCHPRI7 - Channel n Priority Register
+ * - DMA_DCHPRI6 - Channel n Priority Register
+ * - DMA_DCHPRI5 - Channel n Priority Register
+ * - DMA_DCHPRI4 - Channel n Priority Register
+ * - DMA_DCHPRI11 - Channel n Priority Register
+ * - DMA_DCHPRI10 - Channel n Priority Register
+ * - DMA_DCHPRI9 - Channel n Priority Register
+ * - DMA_DCHPRI8 - Channel n Priority Register
+ * - DMA_DCHPRI15 - Channel n Priority Register
+ * - DMA_DCHPRI14 - Channel n Priority Register
+ * - DMA_DCHPRI13 - Channel n Priority Register
+ * - DMA_DCHPRI12 - Channel n Priority Register
+ * - DMA_SADDR - TCD Source Address
+ * - DMA_SOFF - TCD Signed Source Address Offset
+ * - DMA_ATTR - TCD Transfer Attributes
+ * - DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ * - DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ * - DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ * - DMA_SLAST - TCD Last Source Address Adjustment
+ * - DMA_DADDR - TCD Destination Address
+ * - DMA_DOFF - TCD Signed Destination Address Offset
+ * - DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ * - DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ * - DMA_CSR - TCD Control and Status
+ * - DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ */
+
+#define DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
+#define DMA_IDX (0U) /*!< Instance number for DMA. */
+
+/*******************************************************************************
+ * DMA_CR - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CR defines the basic operating configuration of the DMA. Arbitration can
+ * be configured to use either a fixed-priority or a round-robin scheme. For
+ * fixed-priority arbitration, the highest priority channel requesting service is
+ * selected to execute. The channel priority registers assign the priorities; see
+ * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
+ * ignored and channels are cycled through (from high to low channel number)
+ * without regard to priority. For correct operation, writes to the CR register must
+ * be performed only when the DMA channels are inactive; that is, when
+ * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
+ * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
+ * minor loop completion. When minor loop offsets are enabled, the minor loop
+ * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
+ * destination address (TCDn_DADDR), or to both prior to the addresses being
+ * written back into the TCD. If the major loop is complete, the minor loop offset is
+ * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
+ * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
+ * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
+ * is used to specify multiple fields: a source enable bit (SMLOE) to specify
+ * the minor loop offset should be applied to the source address (TCDn_SADDR) upon
+ * minor loop completion, a destination enable bit (DMLOE) to specify the minor
+ * loop offset should be applied to the destination address (TCDn_DADDR) upon
+ * minor loop completion, and the sign extended minor loop offset value (MLOFF). The
+ * same offset value (MLOFF) is used for both source and destination minor loop
+ * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
+ * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
+ * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
+ * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
+ * assigned to the NBYTES field.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CR register
+ */
+/*@{*/
+#define DMA_RD_CR(base)          (DMA_CR_REG(base))
+#define DMA_WR_CR(base, value)   (DMA_CR_REG(base) = (value))
+#define DMA_RMW_CR(base, mask, value) (DMA_WR_CR(base, (DMA_RD_CR(base) & ~(mask)) | (value)))
+#define DMA_SET_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) |  (value)))
+#define DMA_CLR_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) & ~(value)))
+#define DMA_TOG_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CR bitfields
+ */
+
+/*!
+ * @name Register DMA_CR, field EDBG[1] (RW)
+ *
+ * Values:
+ * - 0b0 - When in debug mode, the DMA continues to operate.
+ * - 0b1 - When in debug mode, the DMA stalls the start of a new channel.
+ *     Executing channels are allowed to complete. Channel execution resumes when the
+ *     system exits debug mode or the EDBG bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_EDBG field. */
+#define DMA_RD_CR_EDBG(base) ((DMA_CR_REG(base) & DMA_CR_EDBG_MASK) >> DMA_CR_EDBG_SHIFT)
+#define DMA_BRD_CR_EDBG(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EDBG_SHIFT))
+
+/*! @brief Set the EDBG field to a new value. */
+#define DMA_WR_CR_EDBG(base, value) (DMA_RMW_CR(base, DMA_CR_EDBG_MASK, DMA_CR_EDBG(value)))
+#define DMA_BWR_CR_EDBG(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EDBG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field ERCA[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Fixed priority arbitration is used for channel selection .
+ * - 0b1 - Round robin arbitration is used for channel selection .
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_ERCA field. */
+#define DMA_RD_CR_ERCA(base) ((DMA_CR_REG(base) & DMA_CR_ERCA_MASK) >> DMA_CR_ERCA_SHIFT)
+#define DMA_BRD_CR_ERCA(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ERCA_SHIFT))
+
+/*! @brief Set the ERCA field to a new value. */
+#define DMA_WR_CR_ERCA(base, value) (DMA_RMW_CR(base, DMA_CR_ERCA_MASK, DMA_CR_ERCA(value)))
+#define DMA_BWR_CR_ERCA(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ERCA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field HOE[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Any error causes the HALT bit to set. Subsequently, all service
+ *     requests are ignored until the HALT bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_HOE field. */
+#define DMA_RD_CR_HOE(base)  ((DMA_CR_REG(base) & DMA_CR_HOE_MASK) >> DMA_CR_HOE_SHIFT)
+#define DMA_BRD_CR_HOE(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HOE_SHIFT))
+
+/*! @brief Set the HOE field to a new value. */
+#define DMA_WR_CR_HOE(base, value) (DMA_RMW_CR(base, DMA_CR_HOE_MASK, DMA_CR_HOE(value)))
+#define DMA_BWR_CR_HOE(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field HALT[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Stall the start of any new channels. Executing channels are allowed
+ *     to complete. Channel execution resumes when this bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_HALT field. */
+#define DMA_RD_CR_HALT(base) ((DMA_CR_REG(base) & DMA_CR_HALT_MASK) >> DMA_CR_HALT_SHIFT)
+#define DMA_BRD_CR_HALT(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define DMA_WR_CR_HALT(base, value) (DMA_RMW_CR(base, DMA_CR_HALT_MASK, DMA_CR_HALT(value)))
+#define DMA_BWR_CR_HALT(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field CLM[6] (RW)
+ *
+ * Values:
+ * - 0b0 - A minor loop channel link made to itself goes through channel
+ *     arbitration before being activated again.
+ * - 0b1 - A minor loop channel link made to itself does not go through channel
+ *     arbitration before being activated again. Upon minor loop completion, the
+ *     channel activates again if that channel has a minor loop channel link
+ *     enabled and the link channel is itself. This effectively applies the minor
+ *     loop offsets and restarts the next minor loop.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_CLM field. */
+#define DMA_RD_CR_CLM(base)  ((DMA_CR_REG(base) & DMA_CR_CLM_MASK) >> DMA_CR_CLM_SHIFT)
+#define DMA_BRD_CR_CLM(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CLM_SHIFT))
+
+/*! @brief Set the CLM field to a new value. */
+#define DMA_WR_CR_CLM(base, value) (DMA_RMW_CR(base, DMA_CR_CLM_MASK, DMA_CR_CLM(value)))
+#define DMA_BWR_CR_CLM(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CLM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field EMLM[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
+ * - 0b1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
+ *     an offset field, and the NBYTES field. The individual enable fields allow
+ *     the minor loop offset to be applied to the source address, the
+ *     destination address, or both. The NBYTES field is reduced when either offset is
+ *     enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_EMLM field. */
+#define DMA_RD_CR_EMLM(base) ((DMA_CR_REG(base) & DMA_CR_EMLM_MASK) >> DMA_CR_EMLM_SHIFT)
+#define DMA_BRD_CR_EMLM(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EMLM_SHIFT))
+
+/*! @brief Set the EMLM field to a new value. */
+#define DMA_WR_CR_EMLM(base, value) (DMA_RMW_CR(base, DMA_CR_EMLM_MASK, DMA_CR_EMLM(value)))
+#define DMA_BWR_CR_EMLM(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EMLM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field ECX[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Cancel the remaining data transfer in the same fashion as the CX bit.
+ *     Stop the executing channel and force the minor loop to finish. The cancel
+ *     takes effect after the last write of the current read/write sequence. The
+ *     ECX bit clears itself after the cancel is honored. In addition to
+ *     cancelling the transfer, ECX treats the cancel as an error condition, thus
+ *     updating the Error Status register (DMAx_ES) and generating an optional error
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_ECX field. */
+#define DMA_RD_CR_ECX(base)  ((DMA_CR_REG(base) & DMA_CR_ECX_MASK) >> DMA_CR_ECX_SHIFT)
+#define DMA_BRD_CR_ECX(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ECX_SHIFT))
+
+/*! @brief Set the ECX field to a new value. */
+#define DMA_WR_CR_ECX(base, value) (DMA_RMW_CR(base, DMA_CR_ECX_MASK, DMA_CR_ECX(value)))
+#define DMA_BWR_CR_ECX(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ECX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field CX[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Cancel the remaining data transfer. Stop the executing channel and
+ *     force the minor loop to finish. The cancel takes effect after the last write
+ *     of the current read/write sequence. The CX bit clears itself after the
+ *     cancel has been honored. This cancel retires the channel normally as if the
+ *     minor loop was completed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_CX field. */
+#define DMA_RD_CR_CX(base)   ((DMA_CR_REG(base) & DMA_CR_CX_MASK) >> DMA_CR_CX_SHIFT)
+#define DMA_BRD_CR_CX(base)  (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CX_SHIFT))
+
+/*! @brief Set the CX field to a new value. */
+#define DMA_WR_CR_CX(base, value) (DMA_RMW_CR(base, DMA_CR_CX_MASK, DMA_CR_CX(value)))
+#define DMA_BWR_CR_CX(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CX_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ES - Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ES - Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ES provides information concerning the last recorded channel error.
+ * Channel errors can be caused by: A configuration error, that is: An illegal setting
+ * in the transfer-control descriptor, or An illegal priority register setting
+ * in fixed-arbitration An error termination to a bus master read or write cycle
+ * See the Error Reporting and Handling section for more details.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ES register
+ */
+/*@{*/
+#define DMA_RD_ES(base)          (DMA_ES_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ES bitfields
+ */
+
+/*!
+ * @name Register DMA_ES, field DBE[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination bus error
+ * - 0b1 - The last recorded error was a bus error on a destination write
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DBE field. */
+#define DMA_RD_ES_DBE(base)  ((DMA_ES_REG(base) & DMA_ES_DBE_MASK) >> DMA_ES_DBE_SHIFT)
+#define DMA_BRD_ES_DBE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SBE[1] (RO)
+ *
+ * Values:
+ * - 0b0 - No source bus error
+ * - 0b1 - The last recorded error was a bus error on a source read
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SBE field. */
+#define DMA_RD_ES_SBE(base)  ((DMA_ES_REG(base) & DMA_ES_SBE_MASK) >> DMA_ES_SBE_SHIFT)
+#define DMA_BRD_ES_SBE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SGE[2] (RO)
+ *
+ * Values:
+ * - 0b0 - No scatter/gather configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DLASTSGA field. This field is checked at the beginning of a
+ *     scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled.
+ *     TCDn_DLASTSGA is not on a 32 byte boundary.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SGE field. */
+#define DMA_RD_ES_SGE(base)  ((DMA_ES_REG(base) & DMA_ES_SGE_MASK) >> DMA_ES_SGE_SHIFT)
+#define DMA_BRD_ES_SGE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SGE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field NCE[3] (RO)
+ *
+ * Values:
+ * - 0b0 - No NBYTES/CITER configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
+ *     TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
+ *     TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_NCE field. */
+#define DMA_RD_ES_NCE(base)  ((DMA_ES_REG(base) & DMA_ES_NCE_MASK) >> DMA_ES_NCE_SHIFT)
+#define DMA_BRD_ES_NCE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_NCE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field DOE[4] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination offset configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DOE field. */
+#define DMA_RD_ES_DOE(base)  ((DMA_ES_REG(base) & DMA_ES_DOE_MASK) >> DMA_ES_DOE_SHIFT)
+#define DMA_BRD_ES_DOE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field DAE[5] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination address configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DAE field. */
+#define DMA_RD_ES_DAE(base)  ((DMA_ES_REG(base) & DMA_ES_DAE_MASK) >> DMA_ES_DAE_SHIFT)
+#define DMA_BRD_ES_DAE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DAE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SOE[6] (RO)
+ *
+ * Values:
+ * - 0b0 - No source offset configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SOE field. */
+#define DMA_RD_ES_SOE(base)  ((DMA_ES_REG(base) & DMA_ES_SOE_MASK) >> DMA_ES_SOE_SHIFT)
+#define DMA_BRD_ES_SOE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SAE[7] (RO)
+ *
+ * Values:
+ * - 0b0 - No source address configuration error.
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SAE field. */
+#define DMA_RD_ES_SAE(base)  ((DMA_ES_REG(base) & DMA_ES_SAE_MASK) >> DMA_ES_SAE_SHIFT)
+#define DMA_BRD_ES_SAE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SAE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field ERRCHN[11:8] (RO)
+ *
+ * The channel number of the last recorded error (excluding CPE errors) or last
+ * recorded error canceled transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_ERRCHN field. */
+#define DMA_RD_ES_ERRCHN(base) ((DMA_ES_REG(base) & DMA_ES_ERRCHN_MASK) >> DMA_ES_ERRCHN_SHIFT)
+#define DMA_BRD_ES_ERRCHN(base) (DMA_RD_ES_ERRCHN(base))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field CPE[14] (RO)
+ *
+ * Values:
+ * - 0b0 - No channel priority error
+ * - 0b1 - The last recorded error was a configuration error in the channel
+ *     priorities . Channel priorities are not unique.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_CPE field. */
+#define DMA_RD_ES_CPE(base)  ((DMA_ES_REG(base) & DMA_ES_CPE_MASK) >> DMA_ES_CPE_SHIFT)
+#define DMA_BRD_ES_CPE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_CPE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field ECX[16] (RO)
+ *
+ * Values:
+ * - 0b0 - No canceled transfers
+ * - 0b1 - The last recorded entry was a canceled transfer by the error cancel
+ *     transfer input
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_ECX field. */
+#define DMA_RD_ES_ECX(base)  ((DMA_ES_REG(base) & DMA_ES_ECX_MASK) >> DMA_ES_ECX_SHIFT)
+#define DMA_BRD_ES_ECX(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_ECX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field VLD[31] (RO)
+ *
+ * Logical OR of all ERR status bits
+ *
+ * Values:
+ * - 0b0 - No ERR bits are set
+ * - 0b1 - At least one ERR bit is set indicating a valid error exists that has
+ *     not been cleared
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_VLD field. */
+#define DMA_RD_ES_VLD(base)  ((DMA_ES_REG(base) & DMA_ES_VLD_MASK) >> DMA_ES_VLD_SHIFT)
+#define DMA_BRD_ES_VLD(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_VLD_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ERQ - Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ERQ - Enable Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERQ register provides a bit map for the 16 implemented channels to enable
+ * the request signal for each channel. The state of any given channel enable is
+ * directly affected by writes to this register; it is also affected by writes
+ * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
+ * for a single channel can easily be modified without needing to perform a
+ * read-modify-write sequence to the ERQ. DMA request input signals and this enable
+ * request flag must be asserted before a channel's hardware service request is
+ * accepted. The state of the DMA enable request flag does not affect a channel
+ * service request made explicitly through software or a linked channel request.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ERQ register
+ */
+/*@{*/
+#define DMA_RD_ERQ(base)         (DMA_ERQ_REG(base))
+#define DMA_WR_ERQ(base, value)  (DMA_ERQ_REG(base) = (value))
+#define DMA_RMW_ERQ(base, mask, value) (DMA_WR_ERQ(base, (DMA_RD_ERQ(base) & ~(mask)) | (value)))
+#define DMA_SET_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) |  (value)))
+#define DMA_CLR_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) & ~(value)))
+#define DMA_TOG_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_ERQ, field ERQ0[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ0 field. */
+#define DMA_RD_ERQ_ERQ0(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ0_MASK) >> DMA_ERQ_ERQ0_SHIFT)
+#define DMA_BRD_ERQ_ERQ0(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ0_SHIFT))
+
+/*! @brief Set the ERQ0 field to a new value. */
+#define DMA_WR_ERQ_ERQ0(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ0_MASK, DMA_ERQ_ERQ0(value)))
+#define DMA_BWR_ERQ_ERQ0(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ1[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ1 field. */
+#define DMA_RD_ERQ_ERQ1(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ1_MASK) >> DMA_ERQ_ERQ1_SHIFT)
+#define DMA_BRD_ERQ_ERQ1(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ1_SHIFT))
+
+/*! @brief Set the ERQ1 field to a new value. */
+#define DMA_WR_ERQ_ERQ1(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ1_MASK, DMA_ERQ_ERQ1(value)))
+#define DMA_BWR_ERQ_ERQ1(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ2[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ2 field. */
+#define DMA_RD_ERQ_ERQ2(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ2_MASK) >> DMA_ERQ_ERQ2_SHIFT)
+#define DMA_BRD_ERQ_ERQ2(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ2_SHIFT))
+
+/*! @brief Set the ERQ2 field to a new value. */
+#define DMA_WR_ERQ_ERQ2(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ2_MASK, DMA_ERQ_ERQ2(value)))
+#define DMA_BWR_ERQ_ERQ2(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ3[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ3 field. */
+#define DMA_RD_ERQ_ERQ3(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ3_MASK) >> DMA_ERQ_ERQ3_SHIFT)
+#define DMA_BRD_ERQ_ERQ3(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ3_SHIFT))
+
+/*! @brief Set the ERQ3 field to a new value. */
+#define DMA_WR_ERQ_ERQ3(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ3_MASK, DMA_ERQ_ERQ3(value)))
+#define DMA_BWR_ERQ_ERQ3(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ4[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ4 field. */
+#define DMA_RD_ERQ_ERQ4(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ4_MASK) >> DMA_ERQ_ERQ4_SHIFT)
+#define DMA_BRD_ERQ_ERQ4(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ4_SHIFT))
+
+/*! @brief Set the ERQ4 field to a new value. */
+#define DMA_WR_ERQ_ERQ4(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ4_MASK, DMA_ERQ_ERQ4(value)))
+#define DMA_BWR_ERQ_ERQ4(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ5[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ5 field. */
+#define DMA_RD_ERQ_ERQ5(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ5_MASK) >> DMA_ERQ_ERQ5_SHIFT)
+#define DMA_BRD_ERQ_ERQ5(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ5_SHIFT))
+
+/*! @brief Set the ERQ5 field to a new value. */
+#define DMA_WR_ERQ_ERQ5(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ5_MASK, DMA_ERQ_ERQ5(value)))
+#define DMA_BWR_ERQ_ERQ5(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ6[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ6 field. */
+#define DMA_RD_ERQ_ERQ6(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ6_MASK) >> DMA_ERQ_ERQ6_SHIFT)
+#define DMA_BRD_ERQ_ERQ6(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ6_SHIFT))
+
+/*! @brief Set the ERQ6 field to a new value. */
+#define DMA_WR_ERQ_ERQ6(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ6_MASK, DMA_ERQ_ERQ6(value)))
+#define DMA_BWR_ERQ_ERQ6(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ7[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ7 field. */
+#define DMA_RD_ERQ_ERQ7(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ7_MASK) >> DMA_ERQ_ERQ7_SHIFT)
+#define DMA_BRD_ERQ_ERQ7(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ7_SHIFT))
+
+/*! @brief Set the ERQ7 field to a new value. */
+#define DMA_WR_ERQ_ERQ7(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ7_MASK, DMA_ERQ_ERQ7(value)))
+#define DMA_BWR_ERQ_ERQ7(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ8[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ8 field. */
+#define DMA_RD_ERQ_ERQ8(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ8_MASK) >> DMA_ERQ_ERQ8_SHIFT)
+#define DMA_BRD_ERQ_ERQ8(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ8_SHIFT))
+
+/*! @brief Set the ERQ8 field to a new value. */
+#define DMA_WR_ERQ_ERQ8(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ8_MASK, DMA_ERQ_ERQ8(value)))
+#define DMA_BWR_ERQ_ERQ8(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ9[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ9 field. */
+#define DMA_RD_ERQ_ERQ9(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ9_MASK) >> DMA_ERQ_ERQ9_SHIFT)
+#define DMA_BRD_ERQ_ERQ9(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ9_SHIFT))
+
+/*! @brief Set the ERQ9 field to a new value. */
+#define DMA_WR_ERQ_ERQ9(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ9_MASK, DMA_ERQ_ERQ9(value)))
+#define DMA_BWR_ERQ_ERQ9(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ10[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ10 field. */
+#define DMA_RD_ERQ_ERQ10(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ10_MASK) >> DMA_ERQ_ERQ10_SHIFT)
+#define DMA_BRD_ERQ_ERQ10(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ10_SHIFT))
+
+/*! @brief Set the ERQ10 field to a new value. */
+#define DMA_WR_ERQ_ERQ10(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ10_MASK, DMA_ERQ_ERQ10(value)))
+#define DMA_BWR_ERQ_ERQ10(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ11[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ11 field. */
+#define DMA_RD_ERQ_ERQ11(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ11_MASK) >> DMA_ERQ_ERQ11_SHIFT)
+#define DMA_BRD_ERQ_ERQ11(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ11_SHIFT))
+
+/*! @brief Set the ERQ11 field to a new value. */
+#define DMA_WR_ERQ_ERQ11(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ11_MASK, DMA_ERQ_ERQ11(value)))
+#define DMA_BWR_ERQ_ERQ11(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ12[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ12 field. */
+#define DMA_RD_ERQ_ERQ12(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ12_MASK) >> DMA_ERQ_ERQ12_SHIFT)
+#define DMA_BRD_ERQ_ERQ12(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ12_SHIFT))
+
+/*! @brief Set the ERQ12 field to a new value. */
+#define DMA_WR_ERQ_ERQ12(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ12_MASK, DMA_ERQ_ERQ12(value)))
+#define DMA_BWR_ERQ_ERQ12(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ13[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ13 field. */
+#define DMA_RD_ERQ_ERQ13(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ13_MASK) >> DMA_ERQ_ERQ13_SHIFT)
+#define DMA_BRD_ERQ_ERQ13(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ13_SHIFT))
+
+/*! @brief Set the ERQ13 field to a new value. */
+#define DMA_WR_ERQ_ERQ13(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ13_MASK, DMA_ERQ_ERQ13(value)))
+#define DMA_BWR_ERQ_ERQ13(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ14[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ14 field. */
+#define DMA_RD_ERQ_ERQ14(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ14_MASK) >> DMA_ERQ_ERQ14_SHIFT)
+#define DMA_BRD_ERQ_ERQ14(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ14_SHIFT))
+
+/*! @brief Set the ERQ14 field to a new value. */
+#define DMA_WR_ERQ_ERQ14(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ14_MASK, DMA_ERQ_ERQ14(value)))
+#define DMA_BWR_ERQ_ERQ14(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ15[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ15 field. */
+#define DMA_RD_ERQ_ERQ15(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ15_MASK) >> DMA_ERQ_ERQ15_SHIFT)
+#define DMA_BRD_ERQ_ERQ15(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ15_SHIFT))
+
+/*! @brief Set the ERQ15 field to a new value. */
+#define DMA_WR_ERQ_ERQ15(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ15_MASK, DMA_ERQ_ERQ15(value)))
+#define DMA_BWR_ERQ_ERQ15(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_EEI - Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_EEI - Enable Error Interrupt Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The EEI register provides a bit map for the 16 channels to enable the error
+ * interrupt signal for each channel. The state of any given channel's error
+ * interrupt enable is directly affected by writes to this register; it is also
+ * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
+ * interrupt enable for a single channel can easily be modified without the need to
+ * perform a read-modify-write sequence to the EEI register. The DMA error
+ * indicator and the error interrupt enable flag must be asserted before an error
+ * interrupt request for a given channel is asserted to the interrupt controller.
+ */
+/*!
+ * @name Constants and macros for entire DMA_EEI register
+ */
+/*@{*/
+#define DMA_RD_EEI(base)         (DMA_EEI_REG(base))
+#define DMA_WR_EEI(base, value)  (DMA_EEI_REG(base) = (value))
+#define DMA_RMW_EEI(base, mask, value) (DMA_WR_EEI(base, (DMA_RD_EEI(base) & ~(mask)) | (value)))
+#define DMA_SET_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) |  (value)))
+#define DMA_CLR_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) & ~(value)))
+#define DMA_TOG_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_EEI bitfields
+ */
+
+/*!
+ * @name Register DMA_EEI, field EEI0[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI0 field. */
+#define DMA_RD_EEI_EEI0(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI0_MASK) >> DMA_EEI_EEI0_SHIFT)
+#define DMA_BRD_EEI_EEI0(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI0_SHIFT))
+
+/*! @brief Set the EEI0 field to a new value. */
+#define DMA_WR_EEI_EEI0(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI0_MASK, DMA_EEI_EEI0(value)))
+#define DMA_BWR_EEI_EEI0(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI1[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI1 field. */
+#define DMA_RD_EEI_EEI1(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI1_MASK) >> DMA_EEI_EEI1_SHIFT)
+#define DMA_BRD_EEI_EEI1(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI1_SHIFT))
+
+/*! @brief Set the EEI1 field to a new value. */
+#define DMA_WR_EEI_EEI1(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI1_MASK, DMA_EEI_EEI1(value)))
+#define DMA_BWR_EEI_EEI1(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI2[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI2 field. */
+#define DMA_RD_EEI_EEI2(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI2_MASK) >> DMA_EEI_EEI2_SHIFT)
+#define DMA_BRD_EEI_EEI2(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI2_SHIFT))
+
+/*! @brief Set the EEI2 field to a new value. */
+#define DMA_WR_EEI_EEI2(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI2_MASK, DMA_EEI_EEI2(value)))
+#define DMA_BWR_EEI_EEI2(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI3[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI3 field. */
+#define DMA_RD_EEI_EEI3(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI3_MASK) >> DMA_EEI_EEI3_SHIFT)
+#define DMA_BRD_EEI_EEI3(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI3_SHIFT))
+
+/*! @brief Set the EEI3 field to a new value. */
+#define DMA_WR_EEI_EEI3(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI3_MASK, DMA_EEI_EEI3(value)))
+#define DMA_BWR_EEI_EEI3(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI4[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI4 field. */
+#define DMA_RD_EEI_EEI4(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI4_MASK) >> DMA_EEI_EEI4_SHIFT)
+#define DMA_BRD_EEI_EEI4(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI4_SHIFT))
+
+/*! @brief Set the EEI4 field to a new value. */
+#define DMA_WR_EEI_EEI4(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI4_MASK, DMA_EEI_EEI4(value)))
+#define DMA_BWR_EEI_EEI4(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI5[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI5 field. */
+#define DMA_RD_EEI_EEI5(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI5_MASK) >> DMA_EEI_EEI5_SHIFT)
+#define DMA_BRD_EEI_EEI5(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI5_SHIFT))
+
+/*! @brief Set the EEI5 field to a new value. */
+#define DMA_WR_EEI_EEI5(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI5_MASK, DMA_EEI_EEI5(value)))
+#define DMA_BWR_EEI_EEI5(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI6[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI6 field. */
+#define DMA_RD_EEI_EEI6(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI6_MASK) >> DMA_EEI_EEI6_SHIFT)
+#define DMA_BRD_EEI_EEI6(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI6_SHIFT))
+
+/*! @brief Set the EEI6 field to a new value. */
+#define DMA_WR_EEI_EEI6(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI6_MASK, DMA_EEI_EEI6(value)))
+#define DMA_BWR_EEI_EEI6(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI7[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI7 field. */
+#define DMA_RD_EEI_EEI7(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI7_MASK) >> DMA_EEI_EEI7_SHIFT)
+#define DMA_BRD_EEI_EEI7(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI7_SHIFT))
+
+/*! @brief Set the EEI7 field to a new value. */
+#define DMA_WR_EEI_EEI7(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI7_MASK, DMA_EEI_EEI7(value)))
+#define DMA_BWR_EEI_EEI7(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI8[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI8 field. */
+#define DMA_RD_EEI_EEI8(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI8_MASK) >> DMA_EEI_EEI8_SHIFT)
+#define DMA_BRD_EEI_EEI8(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI8_SHIFT))
+
+/*! @brief Set the EEI8 field to a new value. */
+#define DMA_WR_EEI_EEI8(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI8_MASK, DMA_EEI_EEI8(value)))
+#define DMA_BWR_EEI_EEI8(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI9[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI9 field. */
+#define DMA_RD_EEI_EEI9(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI9_MASK) >> DMA_EEI_EEI9_SHIFT)
+#define DMA_BRD_EEI_EEI9(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI9_SHIFT))
+
+/*! @brief Set the EEI9 field to a new value. */
+#define DMA_WR_EEI_EEI9(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI9_MASK, DMA_EEI_EEI9(value)))
+#define DMA_BWR_EEI_EEI9(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI10[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI10 field. */
+#define DMA_RD_EEI_EEI10(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI10_MASK) >> DMA_EEI_EEI10_SHIFT)
+#define DMA_BRD_EEI_EEI10(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI10_SHIFT))
+
+/*! @brief Set the EEI10 field to a new value. */
+#define DMA_WR_EEI_EEI10(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI10_MASK, DMA_EEI_EEI10(value)))
+#define DMA_BWR_EEI_EEI10(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI11[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI11 field. */
+#define DMA_RD_EEI_EEI11(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI11_MASK) >> DMA_EEI_EEI11_SHIFT)
+#define DMA_BRD_EEI_EEI11(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI11_SHIFT))
+
+/*! @brief Set the EEI11 field to a new value. */
+#define DMA_WR_EEI_EEI11(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI11_MASK, DMA_EEI_EEI11(value)))
+#define DMA_BWR_EEI_EEI11(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI12[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI12 field. */
+#define DMA_RD_EEI_EEI12(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI12_MASK) >> DMA_EEI_EEI12_SHIFT)
+#define DMA_BRD_EEI_EEI12(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI12_SHIFT))
+
+/*! @brief Set the EEI12 field to a new value. */
+#define DMA_WR_EEI_EEI12(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI12_MASK, DMA_EEI_EEI12(value)))
+#define DMA_BWR_EEI_EEI12(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI13[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI13 field. */
+#define DMA_RD_EEI_EEI13(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI13_MASK) >> DMA_EEI_EEI13_SHIFT)
+#define DMA_BRD_EEI_EEI13(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI13_SHIFT))
+
+/*! @brief Set the EEI13 field to a new value. */
+#define DMA_WR_EEI_EEI13(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI13_MASK, DMA_EEI_EEI13(value)))
+#define DMA_BWR_EEI_EEI13(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI14[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI14 field. */
+#define DMA_RD_EEI_EEI14(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI14_MASK) >> DMA_EEI_EEI14_SHIFT)
+#define DMA_BRD_EEI_EEI14(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI14_SHIFT))
+
+/*! @brief Set the EEI14 field to a new value. */
+#define DMA_WR_EEI_EEI14(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI14_MASK, DMA_EEI_EEI14(value)))
+#define DMA_BWR_EEI_EEI14(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI15[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI15 field. */
+#define DMA_RD_EEI_EEI15(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI15_MASK) >> DMA_EEI_EEI15_SHIFT)
+#define DMA_BRD_EEI_EEI15(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI15_SHIFT))
+
+/*! @brief Set the EEI15 field to a new value. */
+#define DMA_WR_EEI_EEI15(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI15_MASK, DMA_EEI_EEI15(value)))
+#define DMA_BWR_EEI_EEI15(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CEEI - Clear Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CEEI - Clear Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
+ * the EEI to disable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be cleared. Setting
+ * the CAEE bit provides a global clear function, forcing the EEI contents to be
+ * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
+ * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
+ * Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CEEI register
+ */
+/*@{*/
+#define DMA_RD_CEEI(base)        (DMA_CEEI_REG(base))
+#define DMA_WR_CEEI(base, value) (DMA_CEEI_REG(base) = (value))
+#define DMA_RMW_CEEI(base, mask, value) (DMA_WR_CEEI(base, (DMA_RD_CEEI(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in EEI
+ */
+/*@{*/
+/*! @brief Set the CEEI field to a new value. */
+#define DMA_WR_CEEI_CEEI(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_CEEI_MASK, DMA_CEEI_CEEI(value)))
+#define DMA_BWR_CEEI_CEEI(base, value) (DMA_WR_CEEI_CEEI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CEEI, field CAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the EEI bit specified in the CEEI field
+ * - 0b1 - Clear all bits in EEI
+ */
+/*@{*/
+/*! @brief Set the CAEE field to a new value. */
+#define DMA_WR_CEEI_CAEE(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_CAEE_MASK, DMA_CEEI_CAEE(value)))
+#define DMA_BWR_CEEI_CAEE(base, value) (BITBAND_ACCESS8(&DMA_CEEI_REG(base), DMA_CEEI_CAEE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CEEI_NOP(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_NOP_MASK, DMA_CEEI_NOP(value)))
+#define DMA_BWR_CEEI_NOP(base, value) (BITBAND_ACCESS8(&DMA_CEEI_REG(base), DMA_CEEI_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SEEI - Set Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SEEI - Set Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
+ * EEI to enable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be set. Setting the
+ * SAEE bit provides a global set function, forcing the entire EEI contents to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SEEI register
+ */
+/*@{*/
+#define DMA_RD_SEEI(base)        (DMA_SEEI_REG(base))
+#define DMA_WR_SEEI(base, value) (DMA_SEEI_REG(base) = (value))
+#define DMA_RMW_SEEI(base, mask, value) (DMA_WR_SEEI(base, (DMA_RD_SEEI(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in EEI
+ */
+/*@{*/
+/*! @brief Set the SEEI field to a new value. */
+#define DMA_WR_SEEI_SEEI(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_SEEI_MASK, DMA_SEEI_SEEI(value)))
+#define DMA_BWR_SEEI_SEEI(base, value) (DMA_WR_SEEI_SEEI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SEEI, field SAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the EEI bit specified in the SEEI field.
+ * - 0b1 - Sets all bits in EEI
+ */
+/*@{*/
+/*! @brief Set the SAEE field to a new value. */
+#define DMA_WR_SEEI_SAEE(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_SAEE_MASK, DMA_SEEI_SAEE(value)))
+#define DMA_BWR_SEEI_SAEE(base, value) (BITBAND_ACCESS8(&DMA_SEEI_REG(base), DMA_SEEI_SAEE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SEEI_NOP(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_NOP_MASK, DMA_SEEI_NOP(value)))
+#define DMA_BWR_SEEI_NOP(base, value) (BITBAND_ACCESS8(&DMA_SEEI_REG(base), DMA_SEEI_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CERQ - Clear Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CERQ - Clear Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERQ to disable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be cleared. Setting the
+ * CAER bit provides a global clear function, forcing the entire contents of the
+ * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
+ * command is ignored. This allows you to write multiple-byte registers as a 32-bit
+ * word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CERQ register
+ */
+/*@{*/
+#define DMA_RD_CERQ(base)        (DMA_CERQ_REG(base))
+#define DMA_WR_CERQ(base, value) (DMA_CERQ_REG(base) = (value))
+#define DMA_RMW_CERQ(base, mask, value) (DMA_WR_CERQ(base, (DMA_RD_CERQ(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERQ
+ */
+/*@{*/
+/*! @brief Set the CERQ field to a new value. */
+#define DMA_WR_CERQ_CERQ(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_CERQ_MASK, DMA_CERQ_CERQ(value)))
+#define DMA_BWR_CERQ_CERQ(base, value) (DMA_WR_CERQ_CERQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERQ, field CAER[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the ERQ bit specified in the CERQ field
+ * - 0b1 - Clear all bits in ERQ
+ */
+/*@{*/
+/*! @brief Set the CAER field to a new value. */
+#define DMA_WR_CERQ_CAER(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_CAER_MASK, DMA_CERQ_CAER(value)))
+#define DMA_BWR_CERQ_CAER(base, value) (BITBAND_ACCESS8(&DMA_CERQ_REG(base), DMA_CERQ_CAER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CERQ_NOP(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_NOP_MASK, DMA_CERQ_NOP(value)))
+#define DMA_BWR_CERQ_NOP(base, value) (BITBAND_ACCESS8(&DMA_CERQ_REG(base), DMA_CERQ_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SERQ - Set Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SERQ - Set Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
+ * ERQ to enable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
+ * bit provides a global set function, forcing the entire contents of ERQ to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SERQ register
+ */
+/*@{*/
+#define DMA_RD_SERQ(base)        (DMA_SERQ_REG(base))
+#define DMA_WR_SERQ(base, value) (DMA_SERQ_REG(base) = (value))
+#define DMA_RMW_SERQ(base, mask, value) (DMA_WR_SERQ(base, (DMA_RD_SERQ(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in ERQ
+ */
+/*@{*/
+/*! @brief Set the SERQ field to a new value. */
+#define DMA_WR_SERQ_SERQ(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_SERQ_MASK, DMA_SERQ_SERQ(value)))
+#define DMA_BWR_SERQ_SERQ(base, value) (DMA_WR_SERQ_SERQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SERQ, field SAER[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the ERQ bit specified in the SERQ field
+ * - 0b1 - Set all bits in ERQ
+ */
+/*@{*/
+/*! @brief Set the SAER field to a new value. */
+#define DMA_WR_SERQ_SAER(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_SAER_MASK, DMA_SERQ_SAER(value)))
+#define DMA_BWR_SERQ_SAER(base, value) (BITBAND_ACCESS8(&DMA_SERQ_REG(base), DMA_SERQ_SAER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SERQ_NOP(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_NOP_MASK, DMA_SERQ_NOP(value)))
+#define DMA_BWR_SERQ_NOP(base, value) (BITBAND_ACCESS8(&DMA_SERQ_REG(base), DMA_SERQ_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CDNE - Clear DONE Status Bit Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CDNE - Clear DONE Status Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
+ * the CADN bit provides a global clear function, forcing all DONE bits to be
+ * cleared. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CDNE register
+ */
+/*@{*/
+#define DMA_RD_CDNE(base)        (DMA_CDNE_REG(base))
+#define DMA_WR_CDNE(base, value) (DMA_CDNE_REG(base) = (value))
+#define DMA_RMW_CDNE(base, mask, value) (DMA_WR_CDNE(base, (DMA_RD_CDNE(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CDNE bitfields
+ */
+
+/*!
+ * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in TCDn_CSR[DONE]
+ */
+/*@{*/
+/*! @brief Set the CDNE field to a new value. */
+#define DMA_WR_CDNE_CDNE(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_CDNE_MASK, DMA_CDNE_CDNE(value)))
+#define DMA_BWR_CDNE_CDNE(base, value) (DMA_WR_CDNE_CDNE(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CDNE, field CADN[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
+ * - 0b1 - Clears all bits in TCDn_CSR[DONE]
+ */
+/*@{*/
+/*! @brief Set the CADN field to a new value. */
+#define DMA_WR_CDNE_CADN(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_CADN_MASK, DMA_CDNE_CADN(value)))
+#define DMA_BWR_CDNE_CADN(base, value) (BITBAND_ACCESS8(&DMA_CDNE_REG(base), DMA_CDNE_CADN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CDNE, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CDNE_NOP(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_NOP_MASK, DMA_CDNE_NOP(value)))
+#define DMA_BWR_CDNE_NOP(base, value) (BITBAND_ACCESS8(&DMA_CDNE_REG(base), DMA_CDNE_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SSRT - Set START Bit Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SSRT - Set START Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SSRT provides a simple memory-mapped mechanism to set the START bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * START bit in the corresponding transfer control descriptor to be set. Setting the
+ * SAST bit provides a global set function, forcing all START bits to be set. If
+ * the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SSRT register
+ */
+/*@{*/
+#define DMA_RD_SSRT(base)        (DMA_SSRT_REG(base))
+#define DMA_WR_SSRT(base, value) (DMA_SSRT_REG(base) = (value))
+#define DMA_RMW_SSRT(base, mask, value) (DMA_WR_SSRT(base, (DMA_RD_SSRT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SSRT bitfields
+ */
+
+/*!
+ * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in TCDn_CSR[START]
+ */
+/*@{*/
+/*! @brief Set the SSRT field to a new value. */
+#define DMA_WR_SSRT_SSRT(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_SSRT_MASK, DMA_SSRT_SSRT(value)))
+#define DMA_BWR_SSRT_SSRT(base, value) (DMA_WR_SSRT_SSRT(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SSRT, field SAST[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
+ * - 0b1 - Set all bits in TCDn_CSR[START]
+ */
+/*@{*/
+/*! @brief Set the SAST field to a new value. */
+#define DMA_WR_SSRT_SAST(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_SAST_MASK, DMA_SSRT_SAST(value)))
+#define DMA_BWR_SSRT_SAST(base, value) (BITBAND_ACCESS8(&DMA_SSRT_REG(base), DMA_SSRT_SAST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SSRT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SSRT_NOP(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_NOP_MASK, DMA_SSRT_NOP(value)))
+#define DMA_BWR_SSRT_NOP(base, value) (BITBAND_ACCESS8(&DMA_SSRT_REG(base), DMA_SSRT_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CERR - Clear Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CERR - Clear Error Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERR provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERR to disable the error condition flag for a given channel. The given value
+ * on a register write causes the corresponding bit in the ERR to be cleared.
+ * Setting the CAEI bit provides a global clear function, forcing the ERR contents
+ * to be cleared, clearing all channel error indicators. If the NOP bit is set,
+ * the command is ignored. This allows you to write multiple-byte registers as a
+ * 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CERR register
+ */
+/*@{*/
+#define DMA_RD_CERR(base)        (DMA_CERR_REG(base))
+#define DMA_WR_CERR(base, value) (DMA_CERR_REG(base) = (value))
+#define DMA_RMW_CERR(base, mask, value) (DMA_WR_CERR(base, (DMA_RD_CERR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CERR bitfields
+ */
+
+/*!
+ * @name Register DMA_CERR, field CERR[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERR
+ */
+/*@{*/
+/*! @brief Set the CERR field to a new value. */
+#define DMA_WR_CERR_CERR(base, value) (DMA_RMW_CERR(base, DMA_CERR_CERR_MASK, DMA_CERR_CERR(value)))
+#define DMA_BWR_CERR_CERR(base, value) (DMA_WR_CERR_CERR(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERR, field CAEI[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the ERR bit specified in the CERR field
+ * - 0b1 - Clear all bits in ERR
+ */
+/*@{*/
+/*! @brief Set the CAEI field to a new value. */
+#define DMA_WR_CERR_CAEI(base, value) (DMA_RMW_CERR(base, DMA_CERR_CAEI_MASK, DMA_CERR_CAEI(value)))
+#define DMA_BWR_CERR_CAEI(base, value) (BITBAND_ACCESS8(&DMA_CERR_REG(base), DMA_CERR_CAEI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERR, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CERR_NOP(base, value) (DMA_RMW_CERR(base, DMA_CERR_NOP_MASK, DMA_CERR_NOP(value)))
+#define DMA_BWR_CERR_NOP(base, value) (BITBAND_ACCESS8(&DMA_CERR_REG(base), DMA_CERR_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CINT - Clear Interrupt Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CINT - Clear Interrupt Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
+ * the INT to disable the interrupt request for a given channel. The given value
+ * on a register write causes the corresponding bit in the INT to be cleared.
+ * Setting the CAIR bit provides a global clear function, forcing the entire contents
+ * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
+ * bit is set, the command is ignored. This allows you to write multiple-byte
+ * registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CINT register
+ */
+/*@{*/
+#define DMA_RD_CINT(base)        (DMA_CINT_REG(base))
+#define DMA_WR_CINT(base, value) (DMA_CINT_REG(base) = (value))
+#define DMA_RMW_CINT(base, mask, value) (DMA_WR_CINT(base, (DMA_RD_CINT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CINT bitfields
+ */
+
+/*!
+ * @name Register DMA_CINT, field CINT[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in INT
+ */
+/*@{*/
+/*! @brief Set the CINT field to a new value. */
+#define DMA_WR_CINT_CINT(base, value) (DMA_RMW_CINT(base, DMA_CINT_CINT_MASK, DMA_CINT_CINT(value)))
+#define DMA_BWR_CINT_CINT(base, value) (DMA_WR_CINT_CINT(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CINT, field CAIR[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the INT bit specified in the CINT field
+ * - 0b1 - Clear all bits in INT
+ */
+/*@{*/
+/*! @brief Set the CAIR field to a new value. */
+#define DMA_WR_CINT_CAIR(base, value) (DMA_RMW_CINT(base, DMA_CINT_CAIR_MASK, DMA_CINT_CAIR(value)))
+#define DMA_BWR_CINT_CAIR(base, value) (BITBAND_ACCESS8(&DMA_CINT_REG(base), DMA_CINT_CAIR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CINT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CINT_NOP(base, value) (DMA_RMW_CINT(base, DMA_CINT_NOP_MASK, DMA_CINT_NOP(value)))
+#define DMA_BWR_CINT_NOP(base, value) (BITBAND_ACCESS8(&DMA_CINT_REG(base), DMA_CINT_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_INT - Interrupt Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_INT - Interrupt Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The INT register provides a bit map for the 16 channels signaling the
+ * presence of an interrupt request for each channel. Depending on the appropriate bit
+ * setting in the transfer-control descriptors, the eDMA engine generates an
+ * interrupt on data transfer completion. The outputs of this register are directly
+ * routed to the interrupt controller (INTC). During the interrupt-service routine
+ * associated with any given channel, it is the software's responsibility to
+ * clear the appropriate bit, negating the interrupt request. Typically, a write to
+ * the CINT register in the interrupt service routine is used for this purpose.
+ * The state of any given channel's interrupt request is directly affected by
+ * writes to this register; it is also affected by writes to the CINT register. On
+ * writes to INT, a 1 in any bit position clears the corresponding channel's
+ * interrupt request. A zero in any bit position has no affect on the corresponding
+ * channel's current interrupt status. The CINT register is provided so the interrupt
+ * request for a single channel can easily be cleared without the need to
+ * perform a read-modify-write sequence to the INT register.
+ */
+/*!
+ * @name Constants and macros for entire DMA_INT register
+ */
+/*@{*/
+#define DMA_RD_INT(base)         (DMA_INT_REG(base))
+#define DMA_WR_INT(base, value)  (DMA_INT_REG(base) = (value))
+#define DMA_RMW_INT(base, mask, value) (DMA_WR_INT(base, (DMA_RD_INT(base) & ~(mask)) | (value)))
+#define DMA_SET_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) |  (value)))
+#define DMA_CLR_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) & ~(value)))
+#define DMA_TOG_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_INT bitfields
+ */
+
+/*!
+ * @name Register DMA_INT, field INT0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT0 field. */
+#define DMA_RD_INT_INT0(base) ((DMA_INT_REG(base) & DMA_INT_INT0_MASK) >> DMA_INT_INT0_SHIFT)
+#define DMA_BRD_INT_INT0(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT0_SHIFT))
+
+/*! @brief Set the INT0 field to a new value. */
+#define DMA_WR_INT_INT0(base, value) (DMA_RMW_INT(base, (DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT0(value)))
+#define DMA_BWR_INT_INT0(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT1 field. */
+#define DMA_RD_INT_INT1(base) ((DMA_INT_REG(base) & DMA_INT_INT1_MASK) >> DMA_INT_INT1_SHIFT)
+#define DMA_BRD_INT_INT1(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT1_SHIFT))
+
+/*! @brief Set the INT1 field to a new value. */
+#define DMA_WR_INT_INT1(base, value) (DMA_RMW_INT(base, (DMA_INT_INT1_MASK | DMA_INT_INT0_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT1(value)))
+#define DMA_BWR_INT_INT1(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT2 field. */
+#define DMA_RD_INT_INT2(base) ((DMA_INT_REG(base) & DMA_INT_INT2_MASK) >> DMA_INT_INT2_SHIFT)
+#define DMA_BRD_INT_INT2(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT2_SHIFT))
+
+/*! @brief Set the INT2 field to a new value. */
+#define DMA_WR_INT_INT2(base, value) (DMA_RMW_INT(base, (DMA_INT_INT2_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT2(value)))
+#define DMA_BWR_INT_INT2(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT3 field. */
+#define DMA_RD_INT_INT3(base) ((DMA_INT_REG(base) & DMA_INT_INT3_MASK) >> DMA_INT_INT3_SHIFT)
+#define DMA_BRD_INT_INT3(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT3_SHIFT))
+
+/*! @brief Set the INT3 field to a new value. */
+#define DMA_WR_INT_INT3(base, value) (DMA_RMW_INT(base, (DMA_INT_INT3_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT3(value)))
+#define DMA_BWR_INT_INT3(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT4[4] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT4 field. */
+#define DMA_RD_INT_INT4(base) ((DMA_INT_REG(base) & DMA_INT_INT4_MASK) >> DMA_INT_INT4_SHIFT)
+#define DMA_BRD_INT_INT4(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT4_SHIFT))
+
+/*! @brief Set the INT4 field to a new value. */
+#define DMA_WR_INT_INT4(base, value) (DMA_RMW_INT(base, (DMA_INT_INT4_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT4(value)))
+#define DMA_BWR_INT_INT4(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT5[5] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT5 field. */
+#define DMA_RD_INT_INT5(base) ((DMA_INT_REG(base) & DMA_INT_INT5_MASK) >> DMA_INT_INT5_SHIFT)
+#define DMA_BRD_INT_INT5(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT5_SHIFT))
+
+/*! @brief Set the INT5 field to a new value. */
+#define DMA_WR_INT_INT5(base, value) (DMA_RMW_INT(base, (DMA_INT_INT5_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT5(value)))
+#define DMA_BWR_INT_INT5(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT6[6] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT6 field. */
+#define DMA_RD_INT_INT6(base) ((DMA_INT_REG(base) & DMA_INT_INT6_MASK) >> DMA_INT_INT6_SHIFT)
+#define DMA_BRD_INT_INT6(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT6_SHIFT))
+
+/*! @brief Set the INT6 field to a new value. */
+#define DMA_WR_INT_INT6(base, value) (DMA_RMW_INT(base, (DMA_INT_INT6_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT6(value)))
+#define DMA_BWR_INT_INT6(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT7[7] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT7 field. */
+#define DMA_RD_INT_INT7(base) ((DMA_INT_REG(base) & DMA_INT_INT7_MASK) >> DMA_INT_INT7_SHIFT)
+#define DMA_BRD_INT_INT7(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT7_SHIFT))
+
+/*! @brief Set the INT7 field to a new value. */
+#define DMA_WR_INT_INT7(base, value) (DMA_RMW_INT(base, (DMA_INT_INT7_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT7(value)))
+#define DMA_BWR_INT_INT7(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT8[8] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT8 field. */
+#define DMA_RD_INT_INT8(base) ((DMA_INT_REG(base) & DMA_INT_INT8_MASK) >> DMA_INT_INT8_SHIFT)
+#define DMA_BRD_INT_INT8(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT8_SHIFT))
+
+/*! @brief Set the INT8 field to a new value. */
+#define DMA_WR_INT_INT8(base, value) (DMA_RMW_INT(base, (DMA_INT_INT8_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT8(value)))
+#define DMA_BWR_INT_INT8(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT9[9] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT9 field. */
+#define DMA_RD_INT_INT9(base) ((DMA_INT_REG(base) & DMA_INT_INT9_MASK) >> DMA_INT_INT9_SHIFT)
+#define DMA_BRD_INT_INT9(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT9_SHIFT))
+
+/*! @brief Set the INT9 field to a new value. */
+#define DMA_WR_INT_INT9(base, value) (DMA_RMW_INT(base, (DMA_INT_INT9_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT9(value)))
+#define DMA_BWR_INT_INT9(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT10[10] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT10 field. */
+#define DMA_RD_INT_INT10(base) ((DMA_INT_REG(base) & DMA_INT_INT10_MASK) >> DMA_INT_INT10_SHIFT)
+#define DMA_BRD_INT_INT10(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT10_SHIFT))
+
+/*! @brief Set the INT10 field to a new value. */
+#define DMA_WR_INT_INT10(base, value) (DMA_RMW_INT(base, (DMA_INT_INT10_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT10(value)))
+#define DMA_BWR_INT_INT10(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT11[11] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT11 field. */
+#define DMA_RD_INT_INT11(base) ((DMA_INT_REG(base) & DMA_INT_INT11_MASK) >> DMA_INT_INT11_SHIFT)
+#define DMA_BRD_INT_INT11(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT11_SHIFT))
+
+/*! @brief Set the INT11 field to a new value. */
+#define DMA_WR_INT_INT11(base, value) (DMA_RMW_INT(base, (DMA_INT_INT11_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT11(value)))
+#define DMA_BWR_INT_INT11(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT12[12] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT12 field. */
+#define DMA_RD_INT_INT12(base) ((DMA_INT_REG(base) & DMA_INT_INT12_MASK) >> DMA_INT_INT12_SHIFT)
+#define DMA_BRD_INT_INT12(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT12_SHIFT))
+
+/*! @brief Set the INT12 field to a new value. */
+#define DMA_WR_INT_INT12(base, value) (DMA_RMW_INT(base, (DMA_INT_INT12_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT12(value)))
+#define DMA_BWR_INT_INT12(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT13[13] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT13 field. */
+#define DMA_RD_INT_INT13(base) ((DMA_INT_REG(base) & DMA_INT_INT13_MASK) >> DMA_INT_INT13_SHIFT)
+#define DMA_BRD_INT_INT13(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT13_SHIFT))
+
+/*! @brief Set the INT13 field to a new value. */
+#define DMA_WR_INT_INT13(base, value) (DMA_RMW_INT(base, (DMA_INT_INT13_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT13(value)))
+#define DMA_BWR_INT_INT13(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT14[14] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT14 field. */
+#define DMA_RD_INT_INT14(base) ((DMA_INT_REG(base) & DMA_INT_INT14_MASK) >> DMA_INT_INT14_SHIFT)
+#define DMA_BRD_INT_INT14(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT14_SHIFT))
+
+/*! @brief Set the INT14 field to a new value. */
+#define DMA_WR_INT_INT14(base, value) (DMA_RMW_INT(base, (DMA_INT_INT14_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT15_MASK), DMA_INT_INT14(value)))
+#define DMA_BWR_INT_INT14(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT15[15] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT15 field. */
+#define DMA_RD_INT_INT15(base) ((DMA_INT_REG(base) & DMA_INT_INT15_MASK) >> DMA_INT_INT15_SHIFT)
+#define DMA_BRD_INT_INT15(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT15_SHIFT))
+
+/*! @brief Set the INT15 field to a new value. */
+#define DMA_WR_INT_INT15(base, value) (DMA_RMW_INT(base, (DMA_INT_INT15_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK), DMA_INT_INT15(value)))
+#define DMA_BWR_INT_INT15(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ERR - Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ERR - Error Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERR provides a bit map for the 16 channels, signaling the presence of an
+ * error for each channel. The eDMA engine signals the occurrence of an error
+ * condition by setting the appropriate bit in this register. The outputs of this
+ * register are enabled by the contents of the EEI, and then routed to the
+ * interrupt controller. During the execution of the interrupt-service routine associated
+ * with any DMA errors, it is software's responsibility to clear the appropriate
+ * bit, negating the error-interrupt request. Typically, a write to the CERR in
+ * the interrupt-service routine is used for this purpose. The normal DMA channel
+ * completion indicators (setting the transfer control descriptor DONE flag and
+ * the possible assertion of an interrupt request) are not affected when an error
+ * is detected. The contents of this register can also be polled because a
+ * non-zero value indicates the presence of a channel error regardless of the state of
+ * the EEI. The state of any given channel's error indicators is affected by
+ * writes to this register; it is also affected by writes to the CERR. On writes to
+ * the ERR, a one in any bit position clears the corresponding channel's error
+ * status. A zero in any bit position has no affect on the corresponding channel's
+ * current error status. The CERR is provided so the error indicator for a single
+ * channel can easily be cleared.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ERR register
+ */
+/*@{*/
+#define DMA_RD_ERR(base)         (DMA_ERR_REG(base))
+#define DMA_WR_ERR(base, value)  (DMA_ERR_REG(base) = (value))
+#define DMA_RMW_ERR(base, mask, value) (DMA_WR_ERR(base, (DMA_RD_ERR(base) & ~(mask)) | (value)))
+#define DMA_SET_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) |  (value)))
+#define DMA_CLR_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) & ~(value)))
+#define DMA_TOG_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ERR bitfields
+ */
+
+/*!
+ * @name Register DMA_ERR, field ERR0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR0 field. */
+#define DMA_RD_ERR_ERR0(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR0_MASK) >> DMA_ERR_ERR0_SHIFT)
+#define DMA_BRD_ERR_ERR0(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR0_SHIFT))
+
+/*! @brief Set the ERR0 field to a new value. */
+#define DMA_WR_ERR_ERR0(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR0(value)))
+#define DMA_BWR_ERR_ERR0(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR1 field. */
+#define DMA_RD_ERR_ERR1(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR1_MASK) >> DMA_ERR_ERR1_SHIFT)
+#define DMA_BRD_ERR_ERR1(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR1_SHIFT))
+
+/*! @brief Set the ERR1 field to a new value. */
+#define DMA_WR_ERR_ERR1(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR1_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR1(value)))
+#define DMA_BWR_ERR_ERR1(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR2 field. */
+#define DMA_RD_ERR_ERR2(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR2_MASK) >> DMA_ERR_ERR2_SHIFT)
+#define DMA_BRD_ERR_ERR2(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR2_SHIFT))
+
+/*! @brief Set the ERR2 field to a new value. */
+#define DMA_WR_ERR_ERR2(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR2_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR2(value)))
+#define DMA_BWR_ERR_ERR2(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR3 field. */
+#define DMA_RD_ERR_ERR3(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR3_MASK) >> DMA_ERR_ERR3_SHIFT)
+#define DMA_BRD_ERR_ERR3(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR3_SHIFT))
+
+/*! @brief Set the ERR3 field to a new value. */
+#define DMA_WR_ERR_ERR3(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR3_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR3(value)))
+#define DMA_BWR_ERR_ERR3(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR4[4] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR4 field. */
+#define DMA_RD_ERR_ERR4(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR4_MASK) >> DMA_ERR_ERR4_SHIFT)
+#define DMA_BRD_ERR_ERR4(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR4_SHIFT))
+
+/*! @brief Set the ERR4 field to a new value. */
+#define DMA_WR_ERR_ERR4(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR4_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR4(value)))
+#define DMA_BWR_ERR_ERR4(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR5[5] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR5 field. */
+#define DMA_RD_ERR_ERR5(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR5_MASK) >> DMA_ERR_ERR5_SHIFT)
+#define DMA_BRD_ERR_ERR5(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR5_SHIFT))
+
+/*! @brief Set the ERR5 field to a new value. */
+#define DMA_WR_ERR_ERR5(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR5_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR5(value)))
+#define DMA_BWR_ERR_ERR5(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR6[6] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR6 field. */
+#define DMA_RD_ERR_ERR6(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR6_MASK) >> DMA_ERR_ERR6_SHIFT)
+#define DMA_BRD_ERR_ERR6(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR6_SHIFT))
+
+/*! @brief Set the ERR6 field to a new value. */
+#define DMA_WR_ERR_ERR6(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR6_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR6(value)))
+#define DMA_BWR_ERR_ERR6(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR7[7] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR7 field. */
+#define DMA_RD_ERR_ERR7(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR7_MASK) >> DMA_ERR_ERR7_SHIFT)
+#define DMA_BRD_ERR_ERR7(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR7_SHIFT))
+
+/*! @brief Set the ERR7 field to a new value. */
+#define DMA_WR_ERR_ERR7(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR7_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR7(value)))
+#define DMA_BWR_ERR_ERR7(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR8[8] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR8 field. */
+#define DMA_RD_ERR_ERR8(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR8_MASK) >> DMA_ERR_ERR8_SHIFT)
+#define DMA_BRD_ERR_ERR8(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR8_SHIFT))
+
+/*! @brief Set the ERR8 field to a new value. */
+#define DMA_WR_ERR_ERR8(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR8_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR8(value)))
+#define DMA_BWR_ERR_ERR8(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR9[9] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR9 field. */
+#define DMA_RD_ERR_ERR9(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR9_MASK) >> DMA_ERR_ERR9_SHIFT)
+#define DMA_BRD_ERR_ERR9(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR9_SHIFT))
+
+/*! @brief Set the ERR9 field to a new value. */
+#define DMA_WR_ERR_ERR9(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR9_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR9(value)))
+#define DMA_BWR_ERR_ERR9(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR10[10] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR10 field. */
+#define DMA_RD_ERR_ERR10(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR10_MASK) >> DMA_ERR_ERR10_SHIFT)
+#define DMA_BRD_ERR_ERR10(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR10_SHIFT))
+
+/*! @brief Set the ERR10 field to a new value. */
+#define DMA_WR_ERR_ERR10(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR10_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR10(value)))
+#define DMA_BWR_ERR_ERR10(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR11[11] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR11 field. */
+#define DMA_RD_ERR_ERR11(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR11_MASK) >> DMA_ERR_ERR11_SHIFT)
+#define DMA_BRD_ERR_ERR11(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR11_SHIFT))
+
+/*! @brief Set the ERR11 field to a new value. */
+#define DMA_WR_ERR_ERR11(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR11_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR11(value)))
+#define DMA_BWR_ERR_ERR11(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR12[12] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR12 field. */
+#define DMA_RD_ERR_ERR12(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR12_MASK) >> DMA_ERR_ERR12_SHIFT)
+#define DMA_BRD_ERR_ERR12(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR12_SHIFT))
+
+/*! @brief Set the ERR12 field to a new value. */
+#define DMA_WR_ERR_ERR12(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR12_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR12(value)))
+#define DMA_BWR_ERR_ERR12(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR13[13] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR13 field. */
+#define DMA_RD_ERR_ERR13(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR13_MASK) >> DMA_ERR_ERR13_SHIFT)
+#define DMA_BRD_ERR_ERR13(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR13_SHIFT))
+
+/*! @brief Set the ERR13 field to a new value. */
+#define DMA_WR_ERR_ERR13(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR13_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR13(value)))
+#define DMA_BWR_ERR_ERR13(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR14[14] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR14 field. */
+#define DMA_RD_ERR_ERR14(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR14_MASK) >> DMA_ERR_ERR14_SHIFT)
+#define DMA_BRD_ERR_ERR14(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR14_SHIFT))
+
+/*! @brief Set the ERR14 field to a new value. */
+#define DMA_WR_ERR_ERR14(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR14_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR14(value)))
+#define DMA_BWR_ERR_ERR14(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR15[15] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR15 field. */
+#define DMA_RD_ERR_ERR15(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR15_MASK) >> DMA_ERR_ERR15_SHIFT)
+#define DMA_BRD_ERR_ERR15(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR15_SHIFT))
+
+/*! @brief Set the ERR15 field to a new value. */
+#define DMA_WR_ERR_ERR15(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR15_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK), DMA_ERR_ERR15(value)))
+#define DMA_BWR_ERR_ERR15(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_HRS - Hardware Request Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_HRS - Hardware Request Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The HRS register provides a bit map for the DMA channels, signaling the
+ * presence of a hardware request for each channel. The hardware request status bits
+ * reflect the current state of the register and qualified (via the ERQ fields)
+ * DMA request signals as seen by the DMA's arbitration logic. This view into the
+ * hardware request signals may be used for debug purposes. These bits reflect the
+ * state of the request as seen by the arbitration logic. Therefore, this status
+ * is affected by the ERQ bits.
+ */
+/*!
+ * @name Constants and macros for entire DMA_HRS register
+ */
+/*@{*/
+#define DMA_RD_HRS(base)         (DMA_HRS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_HRS bitfields
+ */
+
+/*!
+ * @name Register DMA_HRS, field HRS0[0] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 0 is not present
+ * - 0b1 - A hardware service request for channel 0 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS0 field. */
+#define DMA_RD_HRS_HRS0(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS0_MASK) >> DMA_HRS_HRS0_SHIFT)
+#define DMA_BRD_HRS_HRS0(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS1[1] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 1 is not present
+ * - 0b1 - A hardware service request for channel 1 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS1 field. */
+#define DMA_RD_HRS_HRS1(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS1_MASK) >> DMA_HRS_HRS1_SHIFT)
+#define DMA_BRD_HRS_HRS1(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS2[2] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 2 is not present
+ * - 0b1 - A hardware service request for channel 2 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS2 field. */
+#define DMA_RD_HRS_HRS2(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS2_MASK) >> DMA_HRS_HRS2_SHIFT)
+#define DMA_BRD_HRS_HRS2(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS2_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS3[3] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 3 is not present
+ * - 0b1 - A hardware service request for channel 3 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS3 field. */
+#define DMA_RD_HRS_HRS3(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS3_MASK) >> DMA_HRS_HRS3_SHIFT)
+#define DMA_BRD_HRS_HRS3(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS3_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS4[4] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 4 is not present
+ * - 0b1 - A hardware service request for channel 4 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS4 field. */
+#define DMA_RD_HRS_HRS4(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS4_MASK) >> DMA_HRS_HRS4_SHIFT)
+#define DMA_BRD_HRS_HRS4(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS4_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS5[5] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 5 is not present
+ * - 0b1 - A hardware service request for channel 5 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS5 field. */
+#define DMA_RD_HRS_HRS5(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS5_MASK) >> DMA_HRS_HRS5_SHIFT)
+#define DMA_BRD_HRS_HRS5(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS5_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS6[6] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 6 is not present
+ * - 0b1 - A hardware service request for channel 6 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS6 field. */
+#define DMA_RD_HRS_HRS6(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS6_MASK) >> DMA_HRS_HRS6_SHIFT)
+#define DMA_BRD_HRS_HRS6(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS6_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS7[7] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 7 is not present
+ * - 0b1 - A hardware service request for channel 7 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS7 field. */
+#define DMA_RD_HRS_HRS7(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS7_MASK) >> DMA_HRS_HRS7_SHIFT)
+#define DMA_BRD_HRS_HRS7(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS7_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS8[8] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 8 is not present
+ * - 0b1 - A hardware service request for channel 8 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS8 field. */
+#define DMA_RD_HRS_HRS8(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS8_MASK) >> DMA_HRS_HRS8_SHIFT)
+#define DMA_BRD_HRS_HRS8(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS8_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS9[9] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 9 is not present
+ * - 0b1 - A hardware service request for channel 9 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS9 field. */
+#define DMA_RD_HRS_HRS9(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS9_MASK) >> DMA_HRS_HRS9_SHIFT)
+#define DMA_BRD_HRS_HRS9(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS9_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS10[10] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 10 is not present
+ * - 0b1 - A hardware service request for channel 10 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS10 field. */
+#define DMA_RD_HRS_HRS10(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS10_MASK) >> DMA_HRS_HRS10_SHIFT)
+#define DMA_BRD_HRS_HRS10(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS10_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS11[11] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 11 is not present
+ * - 0b1 - A hardware service request for channel 11 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS11 field. */
+#define DMA_RD_HRS_HRS11(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS11_MASK) >> DMA_HRS_HRS11_SHIFT)
+#define DMA_BRD_HRS_HRS11(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS11_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS12[12] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 12 is not present
+ * - 0b1 - A hardware service request for channel 12 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS12 field. */
+#define DMA_RD_HRS_HRS12(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS12_MASK) >> DMA_HRS_HRS12_SHIFT)
+#define DMA_BRD_HRS_HRS12(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS12_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS13[13] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 13 is not present
+ * - 0b1 - A hardware service request for channel 13 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS13 field. */
+#define DMA_RD_HRS_HRS13(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS13_MASK) >> DMA_HRS_HRS13_SHIFT)
+#define DMA_BRD_HRS_HRS13(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS13_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS14[14] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 14 is not present
+ * - 0b1 - A hardware service request for channel 14 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS14 field. */
+#define DMA_RD_HRS_HRS14(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS14_MASK) >> DMA_HRS_HRS14_SHIFT)
+#define DMA_BRD_HRS_HRS14(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS14_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS15[15] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 15 is not present
+ * - 0b1 - A hardware service request for channel 15 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS15 field. */
+#define DMA_RD_HRS_HRS15(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS15_MASK) >> DMA_HRS_HRS15_SHIFT)
+#define DMA_BRD_HRS_HRS15(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS15_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI3 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI3 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI3 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI3(base)     (DMA_DCHPRI3_REG(base))
+#define DMA_WR_DCHPRI3(base, value) (DMA_DCHPRI3_REG(base) = (value))
+#define DMA_RMW_DCHPRI3(base, mask, value) (DMA_WR_DCHPRI3(base, (DMA_RD_DCHPRI3(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) |  (value)))
+#define DMA_CLR_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) & ~(value)))
+#define DMA_TOG_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI3 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI3, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_CHPRI field. */
+#define DMA_RD_DCHPRI3_CHPRI(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_CHPRI_MASK) >> DMA_DCHPRI3_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI3_CHPRI(base) (DMA_RD_DCHPRI3_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI3_CHPRI(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_CHPRI_MASK, DMA_DCHPRI3_CHPRI(value)))
+#define DMA_BWR_DCHPRI3_CHPRI(base, value) (DMA_WR_DCHPRI3_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI3, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_DPA field. */
+#define DMA_RD_DCHPRI3_DPA(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_DPA_MASK) >> DMA_DCHPRI3_DPA_SHIFT)
+#define DMA_BRD_DCHPRI3_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI3_DPA(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_DPA_MASK, DMA_DCHPRI3_DPA(value)))
+#define DMA_BWR_DCHPRI3_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI3, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_ECP field. */
+#define DMA_RD_DCHPRI3_ECP(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_ECP_MASK) >> DMA_DCHPRI3_ECP_SHIFT)
+#define DMA_BRD_DCHPRI3_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI3_ECP(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_ECP_MASK, DMA_DCHPRI3_ECP(value)))
+#define DMA_BWR_DCHPRI3_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI2 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI2 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI2 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI2(base)     (DMA_DCHPRI2_REG(base))
+#define DMA_WR_DCHPRI2(base, value) (DMA_DCHPRI2_REG(base) = (value))
+#define DMA_RMW_DCHPRI2(base, mask, value) (DMA_WR_DCHPRI2(base, (DMA_RD_DCHPRI2(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) |  (value)))
+#define DMA_CLR_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) & ~(value)))
+#define DMA_TOG_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI2 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI2, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_CHPRI field. */
+#define DMA_RD_DCHPRI2_CHPRI(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_CHPRI_MASK) >> DMA_DCHPRI2_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI2_CHPRI(base) (DMA_RD_DCHPRI2_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI2_CHPRI(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_CHPRI_MASK, DMA_DCHPRI2_CHPRI(value)))
+#define DMA_BWR_DCHPRI2_CHPRI(base, value) (DMA_WR_DCHPRI2_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI2, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_DPA field. */
+#define DMA_RD_DCHPRI2_DPA(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_DPA_MASK) >> DMA_DCHPRI2_DPA_SHIFT)
+#define DMA_BRD_DCHPRI2_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI2_DPA(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_DPA_MASK, DMA_DCHPRI2_DPA(value)))
+#define DMA_BWR_DCHPRI2_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI2, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_ECP field. */
+#define DMA_RD_DCHPRI2_ECP(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_ECP_MASK) >> DMA_DCHPRI2_ECP_SHIFT)
+#define DMA_BRD_DCHPRI2_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI2_ECP(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_ECP_MASK, DMA_DCHPRI2_ECP(value)))
+#define DMA_BWR_DCHPRI2_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI1 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI1 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI1 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI1(base)     (DMA_DCHPRI1_REG(base))
+#define DMA_WR_DCHPRI1(base, value) (DMA_DCHPRI1_REG(base) = (value))
+#define DMA_RMW_DCHPRI1(base, mask, value) (DMA_WR_DCHPRI1(base, (DMA_RD_DCHPRI1(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) |  (value)))
+#define DMA_CLR_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) & ~(value)))
+#define DMA_TOG_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI1 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI1, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_CHPRI field. */
+#define DMA_RD_DCHPRI1_CHPRI(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_CHPRI_MASK) >> DMA_DCHPRI1_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI1_CHPRI(base) (DMA_RD_DCHPRI1_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI1_CHPRI(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_CHPRI_MASK, DMA_DCHPRI1_CHPRI(value)))
+#define DMA_BWR_DCHPRI1_CHPRI(base, value) (DMA_WR_DCHPRI1_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI1, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_DPA field. */
+#define DMA_RD_DCHPRI1_DPA(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_DPA_MASK) >> DMA_DCHPRI1_DPA_SHIFT)
+#define DMA_BRD_DCHPRI1_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI1_DPA(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_DPA_MASK, DMA_DCHPRI1_DPA(value)))
+#define DMA_BWR_DCHPRI1_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI1, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_ECP field. */
+#define DMA_RD_DCHPRI1_ECP(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_ECP_MASK) >> DMA_DCHPRI1_ECP_SHIFT)
+#define DMA_BRD_DCHPRI1_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI1_ECP(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_ECP_MASK, DMA_DCHPRI1_ECP(value)))
+#define DMA_BWR_DCHPRI1_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI0 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI0 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI0 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI0(base)     (DMA_DCHPRI0_REG(base))
+#define DMA_WR_DCHPRI0(base, value) (DMA_DCHPRI0_REG(base) = (value))
+#define DMA_RMW_DCHPRI0(base, mask, value) (DMA_WR_DCHPRI0(base, (DMA_RD_DCHPRI0(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) |  (value)))
+#define DMA_CLR_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) & ~(value)))
+#define DMA_TOG_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI0 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI0, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_CHPRI field. */
+#define DMA_RD_DCHPRI0_CHPRI(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_CHPRI_MASK) >> DMA_DCHPRI0_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI0_CHPRI(base) (DMA_RD_DCHPRI0_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI0_CHPRI(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_CHPRI_MASK, DMA_DCHPRI0_CHPRI(value)))
+#define DMA_BWR_DCHPRI0_CHPRI(base, value) (DMA_WR_DCHPRI0_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI0, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_DPA field. */
+#define DMA_RD_DCHPRI0_DPA(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_DPA_MASK) >> DMA_DCHPRI0_DPA_SHIFT)
+#define DMA_BRD_DCHPRI0_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI0_DPA(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_DPA_MASK, DMA_DCHPRI0_DPA(value)))
+#define DMA_BWR_DCHPRI0_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI0, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_ECP field. */
+#define DMA_RD_DCHPRI0_ECP(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_ECP_MASK) >> DMA_DCHPRI0_ECP_SHIFT)
+#define DMA_BRD_DCHPRI0_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI0_ECP(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_ECP_MASK, DMA_DCHPRI0_ECP(value)))
+#define DMA_BWR_DCHPRI0_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI7 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI7 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI7 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI7(base)     (DMA_DCHPRI7_REG(base))
+#define DMA_WR_DCHPRI7(base, value) (DMA_DCHPRI7_REG(base) = (value))
+#define DMA_RMW_DCHPRI7(base, mask, value) (DMA_WR_DCHPRI7(base, (DMA_RD_DCHPRI7(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) |  (value)))
+#define DMA_CLR_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) & ~(value)))
+#define DMA_TOG_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI7 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI7, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_CHPRI field. */
+#define DMA_RD_DCHPRI7_CHPRI(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_CHPRI_MASK) >> DMA_DCHPRI7_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI7_CHPRI(base) (DMA_RD_DCHPRI7_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI7_CHPRI(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_CHPRI_MASK, DMA_DCHPRI7_CHPRI(value)))
+#define DMA_BWR_DCHPRI7_CHPRI(base, value) (DMA_WR_DCHPRI7_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI7, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_DPA field. */
+#define DMA_RD_DCHPRI7_DPA(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_DPA_MASK) >> DMA_DCHPRI7_DPA_SHIFT)
+#define DMA_BRD_DCHPRI7_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI7_DPA(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_DPA_MASK, DMA_DCHPRI7_DPA(value)))
+#define DMA_BWR_DCHPRI7_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI7, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_ECP field. */
+#define DMA_RD_DCHPRI7_ECP(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_ECP_MASK) >> DMA_DCHPRI7_ECP_SHIFT)
+#define DMA_BRD_DCHPRI7_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI7_ECP(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_ECP_MASK, DMA_DCHPRI7_ECP(value)))
+#define DMA_BWR_DCHPRI7_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI6 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI6 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI6 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI6(base)     (DMA_DCHPRI6_REG(base))
+#define DMA_WR_DCHPRI6(base, value) (DMA_DCHPRI6_REG(base) = (value))
+#define DMA_RMW_DCHPRI6(base, mask, value) (DMA_WR_DCHPRI6(base, (DMA_RD_DCHPRI6(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) |  (value)))
+#define DMA_CLR_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) & ~(value)))
+#define DMA_TOG_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI6 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI6, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_CHPRI field. */
+#define DMA_RD_DCHPRI6_CHPRI(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_CHPRI_MASK) >> DMA_DCHPRI6_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI6_CHPRI(base) (DMA_RD_DCHPRI6_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI6_CHPRI(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_CHPRI_MASK, DMA_DCHPRI6_CHPRI(value)))
+#define DMA_BWR_DCHPRI6_CHPRI(base, value) (DMA_WR_DCHPRI6_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI6, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_DPA field. */
+#define DMA_RD_DCHPRI6_DPA(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_DPA_MASK) >> DMA_DCHPRI6_DPA_SHIFT)
+#define DMA_BRD_DCHPRI6_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI6_DPA(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_DPA_MASK, DMA_DCHPRI6_DPA(value)))
+#define DMA_BWR_DCHPRI6_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI6, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_ECP field. */
+#define DMA_RD_DCHPRI6_ECP(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_ECP_MASK) >> DMA_DCHPRI6_ECP_SHIFT)
+#define DMA_BRD_DCHPRI6_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI6_ECP(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_ECP_MASK, DMA_DCHPRI6_ECP(value)))
+#define DMA_BWR_DCHPRI6_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI5 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI5 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI5 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI5(base)     (DMA_DCHPRI5_REG(base))
+#define DMA_WR_DCHPRI5(base, value) (DMA_DCHPRI5_REG(base) = (value))
+#define DMA_RMW_DCHPRI5(base, mask, value) (DMA_WR_DCHPRI5(base, (DMA_RD_DCHPRI5(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) |  (value)))
+#define DMA_CLR_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) & ~(value)))
+#define DMA_TOG_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI5 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI5, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_CHPRI field. */
+#define DMA_RD_DCHPRI5_CHPRI(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_CHPRI_MASK) >> DMA_DCHPRI5_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI5_CHPRI(base) (DMA_RD_DCHPRI5_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI5_CHPRI(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_CHPRI_MASK, DMA_DCHPRI5_CHPRI(value)))
+#define DMA_BWR_DCHPRI5_CHPRI(base, value) (DMA_WR_DCHPRI5_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI5, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_DPA field. */
+#define DMA_RD_DCHPRI5_DPA(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_DPA_MASK) >> DMA_DCHPRI5_DPA_SHIFT)
+#define DMA_BRD_DCHPRI5_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI5_DPA(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_DPA_MASK, DMA_DCHPRI5_DPA(value)))
+#define DMA_BWR_DCHPRI5_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI5, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_ECP field. */
+#define DMA_RD_DCHPRI5_ECP(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_ECP_MASK) >> DMA_DCHPRI5_ECP_SHIFT)
+#define DMA_BRD_DCHPRI5_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI5_ECP(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_ECP_MASK, DMA_DCHPRI5_ECP(value)))
+#define DMA_BWR_DCHPRI5_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI4 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI4 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI4 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI4(base)     (DMA_DCHPRI4_REG(base))
+#define DMA_WR_DCHPRI4(base, value) (DMA_DCHPRI4_REG(base) = (value))
+#define DMA_RMW_DCHPRI4(base, mask, value) (DMA_WR_DCHPRI4(base, (DMA_RD_DCHPRI4(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) |  (value)))
+#define DMA_CLR_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) & ~(value)))
+#define DMA_TOG_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI4 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI4, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_CHPRI field. */
+#define DMA_RD_DCHPRI4_CHPRI(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_CHPRI_MASK) >> DMA_DCHPRI4_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI4_CHPRI(base) (DMA_RD_DCHPRI4_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI4_CHPRI(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_CHPRI_MASK, DMA_DCHPRI4_CHPRI(value)))
+#define DMA_BWR_DCHPRI4_CHPRI(base, value) (DMA_WR_DCHPRI4_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI4, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_DPA field. */
+#define DMA_RD_DCHPRI4_DPA(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_DPA_MASK) >> DMA_DCHPRI4_DPA_SHIFT)
+#define DMA_BRD_DCHPRI4_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI4_DPA(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_DPA_MASK, DMA_DCHPRI4_DPA(value)))
+#define DMA_BWR_DCHPRI4_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI4, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_ECP field. */
+#define DMA_RD_DCHPRI4_ECP(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_ECP_MASK) >> DMA_DCHPRI4_ECP_SHIFT)
+#define DMA_BRD_DCHPRI4_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI4_ECP(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_ECP_MASK, DMA_DCHPRI4_ECP(value)))
+#define DMA_BWR_DCHPRI4_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI11 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI11 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI11 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI11(base)    (DMA_DCHPRI11_REG(base))
+#define DMA_WR_DCHPRI11(base, value) (DMA_DCHPRI11_REG(base) = (value))
+#define DMA_RMW_DCHPRI11(base, mask, value) (DMA_WR_DCHPRI11(base, (DMA_RD_DCHPRI11(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) |  (value)))
+#define DMA_CLR_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) & ~(value)))
+#define DMA_TOG_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI11 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI11, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_CHPRI field. */
+#define DMA_RD_DCHPRI11_CHPRI(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_CHPRI_MASK) >> DMA_DCHPRI11_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI11_CHPRI(base) (DMA_RD_DCHPRI11_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI11_CHPRI(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_CHPRI_MASK, DMA_DCHPRI11_CHPRI(value)))
+#define DMA_BWR_DCHPRI11_CHPRI(base, value) (DMA_WR_DCHPRI11_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI11, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_DPA field. */
+#define DMA_RD_DCHPRI11_DPA(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_DPA_MASK) >> DMA_DCHPRI11_DPA_SHIFT)
+#define DMA_BRD_DCHPRI11_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI11_DPA(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_DPA_MASK, DMA_DCHPRI11_DPA(value)))
+#define DMA_BWR_DCHPRI11_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI11, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_ECP field. */
+#define DMA_RD_DCHPRI11_ECP(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_ECP_MASK) >> DMA_DCHPRI11_ECP_SHIFT)
+#define DMA_BRD_DCHPRI11_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI11_ECP(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_ECP_MASK, DMA_DCHPRI11_ECP(value)))
+#define DMA_BWR_DCHPRI11_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI10 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI10 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI10 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI10(base)    (DMA_DCHPRI10_REG(base))
+#define DMA_WR_DCHPRI10(base, value) (DMA_DCHPRI10_REG(base) = (value))
+#define DMA_RMW_DCHPRI10(base, mask, value) (DMA_WR_DCHPRI10(base, (DMA_RD_DCHPRI10(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) |  (value)))
+#define DMA_CLR_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) & ~(value)))
+#define DMA_TOG_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI10 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI10, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_CHPRI field. */
+#define DMA_RD_DCHPRI10_CHPRI(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_CHPRI_MASK) >> DMA_DCHPRI10_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI10_CHPRI(base) (DMA_RD_DCHPRI10_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI10_CHPRI(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_CHPRI_MASK, DMA_DCHPRI10_CHPRI(value)))
+#define DMA_BWR_DCHPRI10_CHPRI(base, value) (DMA_WR_DCHPRI10_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI10, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_DPA field. */
+#define DMA_RD_DCHPRI10_DPA(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_DPA_MASK) >> DMA_DCHPRI10_DPA_SHIFT)
+#define DMA_BRD_DCHPRI10_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI10_DPA(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_DPA_MASK, DMA_DCHPRI10_DPA(value)))
+#define DMA_BWR_DCHPRI10_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI10, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_ECP field. */
+#define DMA_RD_DCHPRI10_ECP(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_ECP_MASK) >> DMA_DCHPRI10_ECP_SHIFT)
+#define DMA_BRD_DCHPRI10_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI10_ECP(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_ECP_MASK, DMA_DCHPRI10_ECP(value)))
+#define DMA_BWR_DCHPRI10_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI9 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI9 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI9 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI9(base)     (DMA_DCHPRI9_REG(base))
+#define DMA_WR_DCHPRI9(base, value) (DMA_DCHPRI9_REG(base) = (value))
+#define DMA_RMW_DCHPRI9(base, mask, value) (DMA_WR_DCHPRI9(base, (DMA_RD_DCHPRI9(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) |  (value)))
+#define DMA_CLR_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) & ~(value)))
+#define DMA_TOG_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI9 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI9, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_CHPRI field. */
+#define DMA_RD_DCHPRI9_CHPRI(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_CHPRI_MASK) >> DMA_DCHPRI9_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI9_CHPRI(base) (DMA_RD_DCHPRI9_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI9_CHPRI(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_CHPRI_MASK, DMA_DCHPRI9_CHPRI(value)))
+#define DMA_BWR_DCHPRI9_CHPRI(base, value) (DMA_WR_DCHPRI9_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI9, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_DPA field. */
+#define DMA_RD_DCHPRI9_DPA(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_DPA_MASK) >> DMA_DCHPRI9_DPA_SHIFT)
+#define DMA_BRD_DCHPRI9_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI9_DPA(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_DPA_MASK, DMA_DCHPRI9_DPA(value)))
+#define DMA_BWR_DCHPRI9_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI9, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_ECP field. */
+#define DMA_RD_DCHPRI9_ECP(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_ECP_MASK) >> DMA_DCHPRI9_ECP_SHIFT)
+#define DMA_BRD_DCHPRI9_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI9_ECP(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_ECP_MASK, DMA_DCHPRI9_ECP(value)))
+#define DMA_BWR_DCHPRI9_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI8 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI8 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI8 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI8(base)     (DMA_DCHPRI8_REG(base))
+#define DMA_WR_DCHPRI8(base, value) (DMA_DCHPRI8_REG(base) = (value))
+#define DMA_RMW_DCHPRI8(base, mask, value) (DMA_WR_DCHPRI8(base, (DMA_RD_DCHPRI8(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) |  (value)))
+#define DMA_CLR_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) & ~(value)))
+#define DMA_TOG_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI8 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI8, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_CHPRI field. */
+#define DMA_RD_DCHPRI8_CHPRI(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_CHPRI_MASK) >> DMA_DCHPRI8_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI8_CHPRI(base) (DMA_RD_DCHPRI8_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI8_CHPRI(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_CHPRI_MASK, DMA_DCHPRI8_CHPRI(value)))
+#define DMA_BWR_DCHPRI8_CHPRI(base, value) (DMA_WR_DCHPRI8_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI8, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_DPA field. */
+#define DMA_RD_DCHPRI8_DPA(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_DPA_MASK) >> DMA_DCHPRI8_DPA_SHIFT)
+#define DMA_BRD_DCHPRI8_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI8_DPA(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_DPA_MASK, DMA_DCHPRI8_DPA(value)))
+#define DMA_BWR_DCHPRI8_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI8, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_ECP field. */
+#define DMA_RD_DCHPRI8_ECP(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_ECP_MASK) >> DMA_DCHPRI8_ECP_SHIFT)
+#define DMA_BRD_DCHPRI8_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI8_ECP(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_ECP_MASK, DMA_DCHPRI8_ECP(value)))
+#define DMA_BWR_DCHPRI8_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI15 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI15 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI15 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI15(base)    (DMA_DCHPRI15_REG(base))
+#define DMA_WR_DCHPRI15(base, value) (DMA_DCHPRI15_REG(base) = (value))
+#define DMA_RMW_DCHPRI15(base, mask, value) (DMA_WR_DCHPRI15(base, (DMA_RD_DCHPRI15(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) |  (value)))
+#define DMA_CLR_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) & ~(value)))
+#define DMA_TOG_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI15 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI15, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_CHPRI field. */
+#define DMA_RD_DCHPRI15_CHPRI(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_CHPRI_MASK) >> DMA_DCHPRI15_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI15_CHPRI(base) (DMA_RD_DCHPRI15_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI15_CHPRI(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_CHPRI_MASK, DMA_DCHPRI15_CHPRI(value)))
+#define DMA_BWR_DCHPRI15_CHPRI(base, value) (DMA_WR_DCHPRI15_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI15, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_DPA field. */
+#define DMA_RD_DCHPRI15_DPA(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_DPA_MASK) >> DMA_DCHPRI15_DPA_SHIFT)
+#define DMA_BRD_DCHPRI15_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI15_DPA(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_DPA_MASK, DMA_DCHPRI15_DPA(value)))
+#define DMA_BWR_DCHPRI15_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI15, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_ECP field. */
+#define DMA_RD_DCHPRI15_ECP(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_ECP_MASK) >> DMA_DCHPRI15_ECP_SHIFT)
+#define DMA_BRD_DCHPRI15_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI15_ECP(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_ECP_MASK, DMA_DCHPRI15_ECP(value)))
+#define DMA_BWR_DCHPRI15_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI14 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI14 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI14 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI14(base)    (DMA_DCHPRI14_REG(base))
+#define DMA_WR_DCHPRI14(base, value) (DMA_DCHPRI14_REG(base) = (value))
+#define DMA_RMW_DCHPRI14(base, mask, value) (DMA_WR_DCHPRI14(base, (DMA_RD_DCHPRI14(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) |  (value)))
+#define DMA_CLR_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) & ~(value)))
+#define DMA_TOG_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI14 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI14, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_CHPRI field. */
+#define DMA_RD_DCHPRI14_CHPRI(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_CHPRI_MASK) >> DMA_DCHPRI14_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI14_CHPRI(base) (DMA_RD_DCHPRI14_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI14_CHPRI(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_CHPRI_MASK, DMA_DCHPRI14_CHPRI(value)))
+#define DMA_BWR_DCHPRI14_CHPRI(base, value) (DMA_WR_DCHPRI14_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI14, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_DPA field. */
+#define DMA_RD_DCHPRI14_DPA(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_DPA_MASK) >> DMA_DCHPRI14_DPA_SHIFT)
+#define DMA_BRD_DCHPRI14_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI14_DPA(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_DPA_MASK, DMA_DCHPRI14_DPA(value)))
+#define DMA_BWR_DCHPRI14_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI14, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_ECP field. */
+#define DMA_RD_DCHPRI14_ECP(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_ECP_MASK) >> DMA_DCHPRI14_ECP_SHIFT)
+#define DMA_BRD_DCHPRI14_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI14_ECP(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_ECP_MASK, DMA_DCHPRI14_ECP(value)))
+#define DMA_BWR_DCHPRI14_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI13 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI13 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI13 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI13(base)    (DMA_DCHPRI13_REG(base))
+#define DMA_WR_DCHPRI13(base, value) (DMA_DCHPRI13_REG(base) = (value))
+#define DMA_RMW_DCHPRI13(base, mask, value) (DMA_WR_DCHPRI13(base, (DMA_RD_DCHPRI13(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) |  (value)))
+#define DMA_CLR_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) & ~(value)))
+#define DMA_TOG_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI13 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI13, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_CHPRI field. */
+#define DMA_RD_DCHPRI13_CHPRI(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_CHPRI_MASK) >> DMA_DCHPRI13_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI13_CHPRI(base) (DMA_RD_DCHPRI13_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI13_CHPRI(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_CHPRI_MASK, DMA_DCHPRI13_CHPRI(value)))
+#define DMA_BWR_DCHPRI13_CHPRI(base, value) (DMA_WR_DCHPRI13_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI13, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_DPA field. */
+#define DMA_RD_DCHPRI13_DPA(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_DPA_MASK) >> DMA_DCHPRI13_DPA_SHIFT)
+#define DMA_BRD_DCHPRI13_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI13_DPA(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_DPA_MASK, DMA_DCHPRI13_DPA(value)))
+#define DMA_BWR_DCHPRI13_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI13, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_ECP field. */
+#define DMA_RD_DCHPRI13_ECP(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_ECP_MASK) >> DMA_DCHPRI13_ECP_SHIFT)
+#define DMA_BRD_DCHPRI13_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI13_ECP(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_ECP_MASK, DMA_DCHPRI13_ECP(value)))
+#define DMA_BWR_DCHPRI13_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI12 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI12 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI12 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI12(base)    (DMA_DCHPRI12_REG(base))
+#define DMA_WR_DCHPRI12(base, value) (DMA_DCHPRI12_REG(base) = (value))
+#define DMA_RMW_DCHPRI12(base, mask, value) (DMA_WR_DCHPRI12(base, (DMA_RD_DCHPRI12(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) |  (value)))
+#define DMA_CLR_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) & ~(value)))
+#define DMA_TOG_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI12 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI12, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_CHPRI field. */
+#define DMA_RD_DCHPRI12_CHPRI(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_CHPRI_MASK) >> DMA_DCHPRI12_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI12_CHPRI(base) (DMA_RD_DCHPRI12_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI12_CHPRI(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_CHPRI_MASK, DMA_DCHPRI12_CHPRI(value)))
+#define DMA_BWR_DCHPRI12_CHPRI(base, value) (DMA_WR_DCHPRI12_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI12, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_DPA field. */
+#define DMA_RD_DCHPRI12_DPA(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_DPA_MASK) >> DMA_DCHPRI12_DPA_SHIFT)
+#define DMA_BRD_DCHPRI12_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI12_DPA(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_DPA_MASK, DMA_DCHPRI12_DPA(value)))
+#define DMA_BWR_DCHPRI12_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI12, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_ECP field. */
+#define DMA_RD_DCHPRI12_ECP(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_ECP_MASK) >> DMA_DCHPRI12_ECP_SHIFT)
+#define DMA_BRD_DCHPRI12_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI12_ECP(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_ECP_MASK, DMA_DCHPRI12_ECP(value)))
+#define DMA_BWR_DCHPRI12_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SADDR - TCD Source Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SADDR - TCD Source Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SADDR register
+ */
+/*@{*/
+#define DMA_RD_SADDR(base, index) (DMA_SADDR_REG(base, index))
+#define DMA_WR_SADDR(base, index, value) (DMA_SADDR_REG(base, index) = (value))
+#define DMA_RMW_SADDR(base, index, mask, value) (DMA_WR_SADDR(base, index, (DMA_RD_SADDR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) |  (value)))
+#define DMA_CLR_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) & ~(value)))
+#define DMA_TOG_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SOFF - TCD Signed Source Address Offset
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SOFF - TCD Signed Source Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SOFF register
+ */
+/*@{*/
+#define DMA_RD_SOFF(base, index) (DMA_SOFF_REG(base, index))
+#define DMA_WR_SOFF(base, index, value) (DMA_SOFF_REG(base, index) = (value))
+#define DMA_RMW_SOFF(base, index, mask, value) (DMA_WR_SOFF(base, index, (DMA_RD_SOFF(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) |  (value)))
+#define DMA_CLR_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) & ~(value)))
+#define DMA_TOG_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ATTR - TCD Transfer Attributes
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ATTR - TCD Transfer Attributes (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_ATTR register
+ */
+/*@{*/
+#define DMA_RD_ATTR(base, index) (DMA_ATTR_REG(base, index))
+#define DMA_WR_ATTR(base, index, value) (DMA_ATTR_REG(base, index) = (value))
+#define DMA_RMW_ATTR(base, index, mask, value) (DMA_WR_ATTR(base, index, (DMA_RD_ATTR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) |  (value)))
+#define DMA_CLR_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) & ~(value)))
+#define DMA_TOG_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ATTR bitfields
+ */
+
+/*!
+ * @name Register DMA_ATTR, field DSIZE[2:0] (RW)
+ *
+ * See the SSIZE definition
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_DSIZE field. */
+#define DMA_RD_ATTR_DSIZE(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_DSIZE_MASK) >> DMA_ATTR_DSIZE_SHIFT)
+#define DMA_BRD_ATTR_DSIZE(base, index) (DMA_RD_ATTR_DSIZE(base, index))
+
+/*! @brief Set the DSIZE field to a new value. */
+#define DMA_WR_ATTR_DSIZE(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_DSIZE_MASK, DMA_ATTR_DSIZE(value)))
+#define DMA_BWR_ATTR_DSIZE(base, index, value) (DMA_WR_ATTR_DSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field DMOD[7:3] (RW)
+ *
+ * See the SMOD definition
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_DMOD field. */
+#define DMA_RD_ATTR_DMOD(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_DMOD_MASK) >> DMA_ATTR_DMOD_SHIFT)
+#define DMA_BRD_ATTR_DMOD(base, index) (DMA_RD_ATTR_DMOD(base, index))
+
+/*! @brief Set the DMOD field to a new value. */
+#define DMA_WR_ATTR_DMOD(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_DMOD_MASK, DMA_ATTR_DMOD(value)))
+#define DMA_BWR_ATTR_DMOD(base, index, value) (DMA_WR_ATTR_DMOD(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field SSIZE[10:8] (RW)
+ *
+ * The attempted use of a Reserved encoding causes a configuration error.
+ *
+ * Values:
+ * - 0b000 - 8-bit
+ * - 0b001 - 16-bit
+ * - 0b010 - 32-bit
+ * - 0b011 - Reserved
+ * - 0b100 - 16-byte
+ * - 0b101 - 32-byte
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_SSIZE field. */
+#define DMA_RD_ATTR_SSIZE(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_SSIZE_MASK) >> DMA_ATTR_SSIZE_SHIFT)
+#define DMA_BRD_ATTR_SSIZE(base, index) (DMA_RD_ATTR_SSIZE(base, index))
+
+/*! @brief Set the SSIZE field to a new value. */
+#define DMA_WR_ATTR_SSIZE(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_SSIZE_MASK, DMA_ATTR_SSIZE(value)))
+#define DMA_BWR_ATTR_SSIZE(base, index, value) (DMA_WR_ATTR_SSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field SMOD[15:11] (RW)
+ *
+ * Values:
+ * - 0b00000 - Source address modulo feature is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_SMOD field. */
+#define DMA_RD_ATTR_SMOD(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_SMOD_MASK) >> DMA_ATTR_SMOD_SHIFT)
+#define DMA_BRD_ATTR_SMOD(base, index) (DMA_RD_ATTR_SMOD(base, index))
+
+/*! @brief Set the SMOD field to a new value. */
+#define DMA_WR_ATTR_SMOD(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_SMOD_MASK, DMA_ATTR_SMOD(value)))
+#define DMA_BWR_ATTR_SMOD(base, index, value) (DMA_WR_ATTR_SMOD(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
+ * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
+ * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
+ * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLOFFYES register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLOFFYES(base, index) (DMA_NBYTES_MLOFFYES_REG(base, index))
+#define DMA_WR_NBYTES_MLOFFYES(base, index, value) (DMA_NBYTES_MLOFFYES_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLOFFYES(base, index, mask, value) (DMA_WR_NBYTES_MLOFFYES(base, index, (DMA_RD_NBYTES_MLOFFYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_NBYTES_MLOFFYES bitfields
+ */
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted.
+ * (Although, it may be stalled by using the bandwidth control field, or via
+ * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
+ * written back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_NBYTES field. */
+#define DMA_RD_NBYTES_MLOFFYES_NBYTES(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) >> DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_NBYTES(base, index) (DMA_RD_NBYTES_MLOFFYES_NBYTES(base, index))
+
+/*! @brief Set the NBYTES field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_NBYTES(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_NBYTES_MASK, DMA_NBYTES_MLOFFYES_NBYTES(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_NBYTES(base, index, value) (DMA_WR_NBYTES_MLOFFYES_NBYTES(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_MLOFF field. */
+#define DMA_RD_NBYTES_MLOFFYES_MLOFF(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) >> DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_MLOFF(base, index) (DMA_RD_NBYTES_MLOFFYES_MLOFF(base, index))
+
+/*! @brief Set the MLOFF field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_MLOFF(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_MLOFF_MASK, DMA_NBYTES_MLOFFYES_MLOFF(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_MLOFF(base, index, value) (DMA_WR_NBYTES_MLOFFYES_MLOFF(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the DADDR
+ * - 0b1 - The minor loop offset is applied to the DADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_DMLOE field. */
+#define DMA_RD_NBYTES_MLOFFYES_DMLOE(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) >> DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_DMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))
+
+/*! @brief Set the DMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_DMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_DMLOE_MASK, DMA_NBYTES_MLOFFYES_DMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_DMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_DMLOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the SADDR
+ * - 0b1 - The minor loop offset is applied to the SADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_SMLOE field. */
+#define DMA_RD_NBYTES_MLOFFYES_SMLOE(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) >> DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_SMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))
+
+/*! @brief Set the SMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_SMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_SMLOE_MASK, DMA_NBYTES_MLOFFYES_SMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_SMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_SMLOE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
+ * register to use depends on whether minor loop mapping is disabled, enabled but not
+ * used for this channel, or enabled and used. TCD word 2 is defined as follows
+ * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
+ * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
+ * for TCD word 2's definition.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLNO register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLNO(base, index) (DMA_NBYTES_MLNO_REG(base, index))
+#define DMA_WR_NBYTES_MLNO(base, index, value) (DMA_NBYTES_MLNO_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLNO(base, index, mask, value) (DMA_WR_NBYTES_MLNO(base, index, (DMA_RD_NBYTES_MLNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
+ * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
+ * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
+ * the TCD_NBYTES_MLNO register description.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLOFFNO register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLOFFNO(base, index) (DMA_NBYTES_MLOFFNO_REG(base, index))
+#define DMA_WR_NBYTES_MLOFFNO(base, index, value) (DMA_NBYTES_MLOFFNO_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLOFFNO(base, index, mask, value) (DMA_WR_NBYTES_MLOFFNO(base, index, (DMA_RD_NBYTES_MLOFFNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_NBYTES_MLOFFNO bitfields
+ */
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted;
+ * although, it may be stalled by using the bandwidth control field, or via
+ * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
+ * back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_NBYTES field. */
+#define DMA_RD_NBYTES_MLOFFNO_NBYTES(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) >> DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_NBYTES(base, index) (DMA_RD_NBYTES_MLOFFNO_NBYTES(base, index))
+
+/*! @brief Set the NBYTES field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_NBYTES(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_NBYTES_MASK, DMA_NBYTES_MLOFFNO_NBYTES(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_NBYTES(base, index, value) (DMA_WR_NBYTES_MLOFFNO_NBYTES(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the DADDR
+ * - 0b1 - The minor loop offset is applied to the DADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_DMLOE field. */
+#define DMA_RD_NBYTES_MLOFFNO_DMLOE(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) >> DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_DMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))
+
+/*! @brief Set the DMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_DMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_DMLOE_MASK, DMA_NBYTES_MLOFFNO_DMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_DMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_DMLOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the SADDR
+ * - 0b1 - The minor loop offset is applied to the SADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_SMLOE field. */
+#define DMA_RD_NBYTES_MLOFFNO_SMLOE(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) >> DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_SMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))
+
+/*! @brief Set the SMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_SMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_SMLOE_MASK, DMA_NBYTES_MLOFFNO_SMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_SMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_SMLOE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SLAST - TCD Last Source Address Adjustment
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SLAST - TCD Last Source Address Adjustment (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SLAST register
+ */
+/*@{*/
+#define DMA_RD_SLAST(base, index) (DMA_SLAST_REG(base, index))
+#define DMA_WR_SLAST(base, index, value) (DMA_SLAST_REG(base, index) = (value))
+#define DMA_RMW_SLAST(base, index, mask, value) (DMA_WR_SLAST(base, index, (DMA_RD_SLAST(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) |  (value)))
+#define DMA_CLR_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) & ~(value)))
+#define DMA_TOG_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DADDR - TCD Destination Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DADDR - TCD Destination Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DADDR register
+ */
+/*@{*/
+#define DMA_RD_DADDR(base, index) (DMA_DADDR_REG(base, index))
+#define DMA_WR_DADDR(base, index, value) (DMA_DADDR_REG(base, index) = (value))
+#define DMA_RMW_DADDR(base, index, mask, value) (DMA_WR_DADDR(base, index, (DMA_RD_DADDR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) |  (value)))
+#define DMA_CLR_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) & ~(value)))
+#define DMA_TOG_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DOFF - TCD Signed Destination Address Offset
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DOFF - TCD Signed Destination Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DOFF register
+ */
+/*@{*/
+#define DMA_RD_DOFF(base, index) (DMA_DOFF_REG(base, index))
+#define DMA_WR_DOFF(base, index, value) (DMA_DOFF_REG(base, index) = (value))
+#define DMA_RMW_DOFF(base, index, mask, value) (DMA_WR_DOFF(base, index, (DMA_RD_DOFF(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) |  (value)))
+#define DMA_CLR_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) & ~(value)))
+#define DMA_TOG_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
+ * follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CITER_ELINKNO register
+ */
+/*@{*/
+#define DMA_RD_CITER_ELINKNO(base, index) (DMA_CITER_ELINKNO_REG(base, index))
+#define DMA_WR_CITER_ELINKNO(base, index, value) (DMA_CITER_ELINKNO_REG(base, index) = (value))
+#define DMA_RMW_CITER_ELINKNO(base, index, mask, value) (DMA_WR_CITER_ELINKNO(base, index, (DMA_RD_CITER_ELINKNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) |  (value)))
+#define DMA_CLR_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) & ~(value)))
+#define DMA_TOG_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_CITER_ELINKNO, field CITER[14:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKNO_CITER field. */
+#define DMA_RD_CITER_ELINKNO_CITER(base, index) ((DMA_CITER_ELINKNO_REG(base, index) & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT)
+#define DMA_BRD_CITER_ELINKNO_CITER(base, index) (DMA_RD_CITER_ELINKNO_CITER(base, index))
+
+/*! @brief Set the CITER field to a new value. */
+#define DMA_WR_CITER_ELINKNO_CITER(base, index, value) (DMA_RMW_CITER_ELINKNO(base, index, DMA_CITER_ELINKNO_CITER_MASK, DMA_CITER_ELINKNO_CITER(value)))
+#define DMA_BWR_CITER_ELINKNO_CITER(base, index, value) (DMA_WR_CITER_ELINKNO_CITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKNO_ELINK field. */
+#define DMA_RD_CITER_ELINKNO_ELINK(base, index) ((DMA_CITER_ELINKNO_REG(base, index) & DMA_CITER_ELINKNO_ELINK_MASK) >> DMA_CITER_ELINKNO_ELINK_SHIFT)
+#define DMA_BRD_CITER_ELINKNO_ELINK(base, index) (BITBAND_ACCESS16(&DMA_CITER_ELINKNO_REG(base, index), DMA_CITER_ELINKNO_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_CITER_ELINKNO_ELINK(base, index, value) (DMA_RMW_CITER_ELINKNO(base, index, DMA_CITER_ELINKNO_ELINK_MASK, DMA_CITER_ELINKNO_ELINK(value)))
+#define DMA_BWR_CITER_ELINKNO_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CITER_ELINKNO_REG(base, index), DMA_CITER_ELINKNO_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CITER_ELINKYES register
+ */
+/*@{*/
+#define DMA_RD_CITER_ELINKYES(base, index) (DMA_CITER_ELINKYES_REG(base, index))
+#define DMA_WR_CITER_ELINKYES(base, index, value) (DMA_CITER_ELINKYES_REG(base, index) = (value))
+#define DMA_RMW_CITER_ELINKYES(base, index, mask, value) (DMA_WR_CITER_ELINKYES(base, index, (DMA_RD_CITER_ELINKYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) |  (value)))
+#define DMA_CLR_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) & ~(value)))
+#define DMA_TOG_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field CITER[8:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_CITER field. */
+#define DMA_RD_CITER_ELINKYES_CITER(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_CITER(base, index) (DMA_RD_CITER_ELINKYES_CITER(base, index))
+
+/*! @brief Set the CITER field to a new value. */
+#define DMA_WR_CITER_ELINKYES_CITER(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_CITER_MASK, DMA_CITER_ELINKYES_CITER(value)))
+#define DMA_BWR_CITER_ELINKYES_CITER(base, index, value) (DMA_WR_CITER_ELINKYES_CITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request to the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_LINKCH field. */
+#define DMA_RD_CITER_ELINKYES_LINKCH(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_LINKCH_MASK) >> DMA_CITER_ELINKYES_LINKCH_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_LINKCH(base, index) (DMA_RD_CITER_ELINKYES_LINKCH(base, index))
+
+/*! @brief Set the LINKCH field to a new value. */
+#define DMA_WR_CITER_ELINKYES_LINKCH(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_LINKCH_MASK, DMA_CITER_ELINKYES_LINKCH(value)))
+#define DMA_BWR_CITER_ELINKYES_LINKCH(base, index, value) (DMA_WR_CITER_ELINKYES_LINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_ELINK field. */
+#define DMA_RD_CITER_ELINKYES_ELINK(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_ELINK_MASK) >> DMA_CITER_ELINKYES_ELINK_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_ELINK(base, index) (BITBAND_ACCESS16(&DMA_CITER_ELINKYES_REG(base, index), DMA_CITER_ELINKYES_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_CITER_ELINKYES_ELINK(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_ELINK_MASK, DMA_CITER_ELINKYES_ELINK(value)))
+#define DMA_BWR_CITER_ELINKYES_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CITER_ELINKYES_REG(base, index), DMA_CITER_ELINKYES_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DLAST_SGA register
+ */
+/*@{*/
+#define DMA_RD_DLAST_SGA(base, index) (DMA_DLAST_SGA_REG(base, index))
+#define DMA_WR_DLAST_SGA(base, index, value) (DMA_DLAST_SGA_REG(base, index) = (value))
+#define DMA_RMW_DLAST_SGA(base, index, mask, value) (DMA_WR_DLAST_SGA(base, index, (DMA_RD_DLAST_SGA(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) |  (value)))
+#define DMA_CLR_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) & ~(value)))
+#define DMA_TOG_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CSR - TCD Control and Status
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CSR - TCD Control and Status (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_CSR register
+ */
+/*@{*/
+#define DMA_RD_CSR(base, index)  (DMA_CSR_REG(base, index))
+#define DMA_WR_CSR(base, index, value) (DMA_CSR_REG(base, index) = (value))
+#define DMA_RMW_CSR(base, index, mask, value) (DMA_WR_CSR(base, index, (DMA_RD_CSR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) |  (value)))
+#define DMA_CLR_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) & ~(value)))
+#define DMA_TOG_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CSR bitfields
+ */
+
+/*!
+ * @name Register DMA_CSR, field START[0] (RW)
+ *
+ * If this flag is set, the channel is requesting service. The eDMA hardware
+ * automatically clears this flag after the channel begins execution.
+ *
+ * Values:
+ * - 0b0 - The channel is not explicitly started
+ * - 0b1 - The channel is explicitly started via a software initiated service
+ *     request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_START field. */
+#define DMA_RD_CSR_START(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_START_MASK) >> DMA_CSR_START_SHIFT)
+#define DMA_BRD_CSR_START(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_START_SHIFT))
+
+/*! @brief Set the START field to a new value. */
+#define DMA_WR_CSR_START(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_START_MASK, DMA_CSR_START(value)))
+#define DMA_BWR_CSR_START(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_START_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field INTMAJOR[1] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT when the current major iteration count reaches
+ * zero.
+ *
+ * Values:
+ * - 0b0 - The end-of-major loop interrupt is disabled
+ * - 0b1 - The end-of-major loop interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_INTMAJOR field. */
+#define DMA_RD_CSR_INTMAJOR(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_INTMAJOR_MASK) >> DMA_CSR_INTMAJOR_SHIFT)
+#define DMA_BRD_CSR_INTMAJOR(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTMAJOR_SHIFT))
+
+/*! @brief Set the INTMAJOR field to a new value. */
+#define DMA_WR_CSR_INTMAJOR(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_INTMAJOR_MASK, DMA_CSR_INTMAJOR(value)))
+#define DMA_BWR_CSR_INTMAJOR(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTMAJOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field INTHALF[2] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT register when the current major iteration count
+ * reaches the halfway point. Specifically, the comparison performed by the eDMA
+ * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
+ * provided to support double-buffered (aka ping-pong) schemes or other types of data
+ * movement where the processor needs an early indication of the transfer's
+ * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
+ *
+ * Values:
+ * - 0b0 - The half-point interrupt is disabled
+ * - 0b1 - The half-point interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_INTHALF field. */
+#define DMA_RD_CSR_INTHALF(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_INTHALF_MASK) >> DMA_CSR_INTHALF_SHIFT)
+#define DMA_BRD_CSR_INTHALF(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTHALF_SHIFT))
+
+/*! @brief Set the INTHALF field to a new value. */
+#define DMA_WR_CSR_INTHALF(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_INTHALF_MASK, DMA_CSR_INTHALF(value)))
+#define DMA_BWR_CSR_INTHALF(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTHALF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field DREQ[3] (RW)
+ *
+ * If this flag is set, the eDMA hardware automatically clears the corresponding
+ * ERQ bit when the current major iteration count reaches zero.
+ *
+ * Values:
+ * - 0b0 - The channel's ERQ bit is not affected
+ * - 0b1 - The channel's ERQ bit is cleared when the major loop is complete
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_DREQ field. */
+#define DMA_RD_CSR_DREQ(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_DREQ_MASK) >> DMA_CSR_DREQ_SHIFT)
+#define DMA_BRD_CSR_DREQ(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DREQ_SHIFT))
+
+/*! @brief Set the DREQ field to a new value. */
+#define DMA_WR_CSR_DREQ(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_DREQ_MASK, DMA_CSR_DREQ(value)))
+#define DMA_BWR_CSR_DREQ(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field ESG[4] (RW)
+ *
+ * As the channel completes the major loop, this flag enables scatter/gather
+ * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
+ * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
+ * loaded as the transfer control descriptor into the local memory. To support the
+ * dynamic scatter/gather coherency model, this field is forced to zero when
+ * written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0b0 - The current channel's TCD is normal format.
+ * - 0b1 - The current channel's TCD specifies a scatter gather format. The
+ *     DLASTSGA field provides a memory pointer to the next TCD to be loaded into
+ *     this channel after the major loop completes its execution.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_ESG field. */
+#define DMA_RD_CSR_ESG(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_ESG_MASK) >> DMA_CSR_ESG_SHIFT)
+#define DMA_BRD_CSR_ESG(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ESG_SHIFT))
+
+/*! @brief Set the ESG field to a new value. */
+#define DMA_WR_CSR_ESG(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_ESG_MASK, DMA_CSR_ESG(value)))
+#define DMA_BWR_CSR_ESG(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ESG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field MAJORELINK[5] (RW)
+ *
+ * As the channel completes the major loop, this flag enables the linking to
+ * another channel, defined by MAJORLINKCH. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. To support the dynamic linking coherency model,
+ * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_MAJORELINK field. */
+#define DMA_RD_CSR_MAJORELINK(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_MAJORELINK_MASK) >> DMA_CSR_MAJORELINK_SHIFT)
+#define DMA_BRD_CSR_MAJORELINK(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_MAJORELINK_SHIFT))
+
+/*! @brief Set the MAJORELINK field to a new value. */
+#define DMA_WR_CSR_MAJORELINK(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_MAJORELINK_MASK, DMA_CSR_MAJORELINK(value)))
+#define DMA_BWR_CSR_MAJORELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_MAJORELINK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field ACTIVE[6] (RW)
+ *
+ * This flag signals the channel is currently in execution. It is set when
+ * channel service begins, and the eDMA clears it as the minor loop completes or if
+ * any error condition is detected. This bit resets to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_ACTIVE field. */
+#define DMA_RD_CSR_ACTIVE(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_ACTIVE_MASK) >> DMA_CSR_ACTIVE_SHIFT)
+#define DMA_BRD_CSR_ACTIVE(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ACTIVE_SHIFT))
+
+/*! @brief Set the ACTIVE field to a new value. */
+#define DMA_WR_CSR_ACTIVE(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_ACTIVE_MASK, DMA_CSR_ACTIVE(value)))
+#define DMA_BWR_CSR_ACTIVE(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ACTIVE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field DONE[7] (RW)
+ *
+ * This flag indicates the eDMA has completed the major loop. The eDMA engine
+ * sets it as the CITER count reaches zero; The software clears it, or the hardware
+ * when the channel is activated. This bit must be cleared to write the
+ * MAJORELINK or ESG bits.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_DONE field. */
+#define DMA_RD_CSR_DONE(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT)
+#define DMA_BRD_CSR_DONE(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DONE_SHIFT))
+
+/*! @brief Set the DONE field to a new value. */
+#define DMA_WR_CSR_DONE(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_DONE_MASK, DMA_CSR_DONE(value)))
+#define DMA_BWR_CSR_DONE(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DONE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field MAJORLINKCH[11:8] (RW)
+ *
+ * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
+ * performed after the major loop counter is exhausted. else After the major loop
+ * counter is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_MAJORLINKCH field. */
+#define DMA_RD_CSR_MAJORLINKCH(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_MAJORLINKCH_MASK) >> DMA_CSR_MAJORLINKCH_SHIFT)
+#define DMA_BRD_CSR_MAJORLINKCH(base, index) (DMA_RD_CSR_MAJORLINKCH(base, index))
+
+/*! @brief Set the MAJORLINKCH field to a new value. */
+#define DMA_WR_CSR_MAJORLINKCH(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_MAJORLINKCH_MASK, DMA_CSR_MAJORLINKCH(value)))
+#define DMA_BWR_CSR_MAJORLINKCH(base, index, value) (DMA_WR_CSR_MAJORLINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field BWC[15:14] (RW)
+ *
+ * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
+ * the eDMA processes the minor loop, it continuously generates read/write
+ * sequences until the minor count is exhausted. This field forces the eDMA to stall
+ * after the completion of each read/write access to control the bus request
+ * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
+ * this field is ignored between the first and second transfers and after the
+ * last write of each minor loop. This behavior is a side effect of reducing
+ * start-up latency.
+ *
+ * Values:
+ * - 0b00 - No eDMA engine stalls
+ * - 0b01 - Reserved
+ * - 0b10 - eDMA engine stalls for 4 cycles after each r/w
+ * - 0b11 - eDMA engine stalls for 8 cycles after each r/w
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_BWC field. */
+#define DMA_RD_CSR_BWC(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_BWC_MASK) >> DMA_CSR_BWC_SHIFT)
+#define DMA_BRD_CSR_BWC(base, index) (DMA_RD_CSR_BWC(base, index))
+
+/*! @brief Set the BWC field to a new value. */
+#define DMA_WR_CSR_BWC(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_BWC_MASK, DMA_CSR_BWC(value)))
+#define DMA_BWR_CSR_BWC(base, index, value) (DMA_WR_CSR_BWC(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
+ * follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_BITER_ELINKYES register
+ */
+/*@{*/
+#define DMA_RD_BITER_ELINKYES(base, index) (DMA_BITER_ELINKYES_REG(base, index))
+#define DMA_WR_BITER_ELINKYES(base, index, value) (DMA_BITER_ELINKYES_REG(base, index) = (value))
+#define DMA_RMW_BITER_ELINKYES(base, index, mask, value) (DMA_WR_BITER_ELINKYES(base, index, (DMA_RD_BITER_ELINKYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) |  (value)))
+#define DMA_CLR_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) & ~(value)))
+#define DMA_TOG_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_BITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field BITER[8:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_BITER field. */
+#define DMA_RD_BITER_ELINKYES_BITER(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_BITER_MASK) >> DMA_BITER_ELINKYES_BITER_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_BITER(base, index) (DMA_RD_BITER_ELINKYES_BITER(base, index))
+
+/*! @brief Set the BITER field to a new value. */
+#define DMA_WR_BITER_ELINKYES_BITER(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_BITER_MASK, DMA_BITER_ELINKYES_BITER(value)))
+#define DMA_BWR_BITER_ELINKYES_BITER(base, index, value) (DMA_WR_BITER_ELINKYES_BITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START]
+ * bit. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the major
+ * iteration count is exhausted, the contents of this field is reloaded into the
+ * CITER field.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_LINKCH field. */
+#define DMA_RD_BITER_ELINKYES_LINKCH(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_LINKCH_MASK) >> DMA_BITER_ELINKYES_LINKCH_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_LINKCH(base, index) (DMA_RD_BITER_ELINKYES_LINKCH(base, index))
+
+/*! @brief Set the LINKCH field to a new value. */
+#define DMA_WR_BITER_ELINKYES_LINKCH(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_LINKCH_MASK, DMA_BITER_ELINKYES_LINKCH(value)))
+#define DMA_BWR_BITER_ELINKYES_LINKCH(base, index, value) (DMA_WR_BITER_ELINKYES_LINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking disables, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded into
+ * the CITER field.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_ELINK field. */
+#define DMA_RD_BITER_ELINKYES_ELINK(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_ELINK_MASK) >> DMA_BITER_ELINKYES_ELINK_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_ELINK(base, index) (BITBAND_ACCESS16(&DMA_BITER_ELINKYES_REG(base, index), DMA_BITER_ELINKYES_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_BITER_ELINKYES_ELINK(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_ELINK_MASK, DMA_BITER_ELINKYES_ELINK(value)))
+#define DMA_BWR_BITER_ELINKYES_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_BITER_ELINKYES_REG(base, index), DMA_BITER_ELINKYES_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
+ * as follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_BITER_ELINKNO register
+ */
+/*@{*/
+#define DMA_RD_BITER_ELINKNO(base, index) (DMA_BITER_ELINKNO_REG(base, index))
+#define DMA_WR_BITER_ELINKNO(base, index, value) (DMA_BITER_ELINKNO_REG(base, index) = (value))
+#define DMA_RMW_BITER_ELINKNO(base, index, mask, value) (DMA_WR_BITER_ELINKNO(base, index, (DMA_RD_BITER_ELINKNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) |  (value)))
+#define DMA_CLR_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) & ~(value)))
+#define DMA_TOG_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_BITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_BITER_ELINKNO, field BITER[14:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKNO_BITER field. */
+#define DMA_RD_BITER_ELINKNO_BITER(base, index) ((DMA_BITER_ELINKNO_REG(base, index) & DMA_BITER_ELINKNO_BITER_MASK) >> DMA_BITER_ELINKNO_BITER_SHIFT)
+#define DMA_BRD_BITER_ELINKNO_BITER(base, index) (DMA_RD_BITER_ELINKNO_BITER(base, index))
+
+/*! @brief Set the BITER field to a new value. */
+#define DMA_WR_BITER_ELINKNO_BITER(base, index, value) (DMA_RMW_BITER_ELINKNO(base, index, DMA_BITER_ELINKNO_BITER_MASK, DMA_BITER_ELINKNO_BITER(value)))
+#define DMA_BWR_BITER_ELINKNO_BITER(base, index, value) (DMA_WR_BITER_ELINKNO_BITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded
+ * into the CITER field.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKNO_ELINK field. */
+#define DMA_RD_BITER_ELINKNO_ELINK(base, index) ((DMA_BITER_ELINKNO_REG(base, index) & DMA_BITER_ELINKNO_ELINK_MASK) >> DMA_BITER_ELINKNO_ELINK_SHIFT)
+#define DMA_BRD_BITER_ELINKNO_ELINK(base, index) (BITBAND_ACCESS16(&DMA_BITER_ELINKNO_REG(base, index), DMA_BITER_ELINKNO_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_BITER_ELINKNO_ELINK(base, index, value) (DMA_RMW_BITER_ELINKNO(base, index, DMA_BITER_ELINKNO_ELINK_MASK, DMA_BITER_ELINKNO_ELINK(value)))
+#define DMA_BWR_BITER_ELINKNO_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_BITER_ELINKNO_REG(base, index), DMA_BITER_ELINKNO_ELINK_SHIFT) = (value))
+/*@}*/
+
+/* Register macros for indexed access to DMA channel priority registers */
+/*
+ * Constants and macros for entire DMA_DCHPRIn register
+ */
+#define DMA_DCHPRIn_INDEX(channel)          (((channel) & ~0x03U) | (3 - ((channel) & 0x03U)))
+#define DMA_DCHPRIn_REG(base, index)        (((volatile uint8_t *)&DMA_DCHPRI3_REG(base))[DMA_DCHPRIn_INDEX(index)])
+#define DMA_RD_DCHPRIn(base, index)         (DMA_DCHPRIn_REG((base), (index)))
+#define DMA_WR_DCHPRIn(base, index, value)  (DMA_DCHPRIn_REG((base), (index)) = (value))
+#define DMA_SET_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) |  (value)))
+#define DMA_CLR_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) & ~(value)))
+#define DMA_TOG_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) ^  (value)))
+
+/*
+ * Register DMA_DCHPRIn, bit field CHPRI
+ */
+/* Read current value of the CHPRI bit field. */
+#define DMA_RD_DCHPRIn_CHPRI(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_CHPRI_MASK) >> DMA_DCHPRI0_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRIn_CHPRI(base, index) (DMA_RD_DCHPRIn_CHPRI((base), (index)))
+
+/* Set the CHPRI bit field to a new value. */
+#define DMA_WR_DCHPRIn_CHPRI(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_CHPRI_MASK) | DMA_DCHPRI0_CHPRI(value)))
+#define DMA_BWR_DCHPRIn_CHPRI(base, index, value) (DMA_WR_DCHPRIn_CHPRI((base), (index), (value)))
+
+/*
+ * Register DMA_DCHPRIn, bit field DPA
+ */
+/* Read current value of the DPA bit field. */
+#define DMA_RD_DCHPRIn_DPA(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_DPA_MASK) >> DMA_DCHPRI0_DPA_SHIFT)
+#define DMA_BRD_DCHPRIn_DPA(base, index) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_DPA_SHIFT))
+
+/* Set the DPA bit field to a new value. */
+#define DMA_WR_DCHPRIn_DPA(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_DPA_MASK) | DMA_DCHPRI0_DPA(value)))
+#define DMA_BWR_DCHPRIn_DPA(base, index, value) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_DPA_SHIFT) = (value))
+
+/*
+ * Register DMA_DCHPRIn, bit field ECP
+ */
+/* Read current value of the ECP bit field. */
+#define DMA_RD_DCHPRIn_ECP(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_ECP_MASK) >> DMA_DCHPRI0_ECP_SHIFT)
+#define DMA_BRD_DCHPRIn_ECP(base, index) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_ECP_SHIFT))
+
+/* Set the ECP bit field to a new value. */
+#define DMA_WR_DCHPRIn_ECP(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_ECP_MASK) | DMA_DCHPRI0_ECP(value)))
+#define DMA_BWR_DCHPRIn_ECP(base, index, value) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_ECP_SHIFT) = (value))
+
+/*
+ * MK64F12 DMAMUX
+ *
+ * DMA channel multiplexor
+ *
+ * Registers defined in this header file:
+ * - DMAMUX_CHCFG - Channel Configuration register
+ */
+
+#define DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
+#define DMAMUX_IDX (0U) /*!< Instance number for DMAMUX. */
+
+/*******************************************************************************
+ * DMAMUX_CHCFG - Channel Configuration register
+ ******************************************************************************/
+
+/*!
+ * @brief DMAMUX_CHCFG - Channel Configuration register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Each of the DMA channels can be independently enabled/disabled and associated
+ * with one of the DMA slots (peripheral slots or always-on slots) in the
+ * system. Setting multiple CHCFG registers with the same source value will result in
+ * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
+ * Before changing the trigger or source settings, a DMA channel must be disabled
+ * via CHCFGn[ENBL].
+ */
+/*!
+ * @name Constants and macros for entire DMAMUX_CHCFG register
+ */
+/*@{*/
+#define DMAMUX_RD_CHCFG(base, index) (DMAMUX_CHCFG_REG(base, index))
+#define DMAMUX_WR_CHCFG(base, index, value) (DMAMUX_CHCFG_REG(base, index) = (value))
+#define DMAMUX_RMW_CHCFG(base, index, mask, value) (DMAMUX_WR_CHCFG(base, index, (DMAMUX_RD_CHCFG(base, index) & ~(mask)) | (value)))
+#define DMAMUX_SET_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) |  (value)))
+#define DMAMUX_CLR_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) & ~(value)))
+#define DMAMUX_TOG_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMAMUX_CHCFG bitfields
+ */
+
+/*!
+ * @name Register DMAMUX_CHCFG, field SOURCE[5:0] (RW)
+ *
+ * Specifies which DMA source, if any, is routed to a particular DMA channel.
+ * See your device's chip configuration details for information about the
+ * peripherals and their slot numbers.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_SOURCE field. */
+#define DMAMUX_RD_CHCFG_SOURCE(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT)
+#define DMAMUX_BRD_CHCFG_SOURCE(base, index) (DMAMUX_RD_CHCFG_SOURCE(base, index))
+
+/*! @brief Set the SOURCE field to a new value. */
+#define DMAMUX_WR_CHCFG_SOURCE(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_SOURCE_MASK, DMAMUX_CHCFG_SOURCE(value)))
+#define DMAMUX_BWR_CHCFG_SOURCE(base, index, value) (DMAMUX_WR_CHCFG_SOURCE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field TRIG[6] (RW)
+ *
+ * Enables the periodic trigger capability for the triggered DMA channel.
+ *
+ * Values:
+ * - 0b0 - Triggering is disabled. If triggering is disabled and ENBL is set,
+ *     the DMA Channel will simply route the specified source to the DMA channel.
+ *     (Normal mode)
+ * - 0b1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
+ *     DMAMUX is in Periodic Trigger mode.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_TRIG field. */
+#define DMAMUX_RD_CHCFG_TRIG(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_TRIG_MASK) >> DMAMUX_CHCFG_TRIG_SHIFT)
+#define DMAMUX_BRD_CHCFG_TRIG(base, index) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT))
+
+/*! @brief Set the TRIG field to a new value. */
+#define DMAMUX_WR_CHCFG_TRIG(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_TRIG_MASK, DMAMUX_CHCFG_TRIG(value)))
+#define DMAMUX_BWR_CHCFG_TRIG(base, index, value) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field ENBL[7] (RW)
+ *
+ * Enables the DMA channel.
+ *
+ * Values:
+ * - 0b0 - DMA channel is disabled. This mode is primarily used during
+ *     configuration of the DMAMux. The DMA has separate channel enables/disables, which
+ *     should be used to disable or reconfigure a DMA channel.
+ * - 0b1 - DMA channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_ENBL field. */
+#define DMAMUX_RD_CHCFG_ENBL(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT)
+#define DMAMUX_BRD_CHCFG_ENBL(base, index) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT))
+
+/*! @brief Set the ENBL field to a new value. */
+#define DMAMUX_WR_CHCFG_ENBL(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_ENBL_MASK, DMAMUX_CHCFG_ENBL(value)))
+#define DMAMUX_BWR_CHCFG_ENBL(base, index, value) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 ENET
+ *
+ * Ethernet MAC-NET Core
+ *
+ * Registers defined in this header file:
+ * - ENET_EIR - Interrupt Event Register
+ * - ENET_EIMR - Interrupt Mask Register
+ * - ENET_RDAR - Receive Descriptor Active Register
+ * - ENET_TDAR - Transmit Descriptor Active Register
+ * - ENET_ECR - Ethernet Control Register
+ * - ENET_MMFR - MII Management Frame Register
+ * - ENET_MSCR - MII Speed Control Register
+ * - ENET_MIBC - MIB Control Register
+ * - ENET_RCR - Receive Control Register
+ * - ENET_TCR - Transmit Control Register
+ * - ENET_PALR - Physical Address Lower Register
+ * - ENET_PAUR - Physical Address Upper Register
+ * - ENET_OPD - Opcode/Pause Duration Register
+ * - ENET_IAUR - Descriptor Individual Upper Address Register
+ * - ENET_IALR - Descriptor Individual Lower Address Register
+ * - ENET_GAUR - Descriptor Group Upper Address Register
+ * - ENET_GALR - Descriptor Group Lower Address Register
+ * - ENET_TFWR - Transmit FIFO Watermark Register
+ * - ENET_RDSR - Receive Descriptor Ring Start Register
+ * - ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ * - ENET_MRBR - Maximum Receive Buffer Size Register
+ * - ENET_RSFL - Receive FIFO Section Full Threshold
+ * - ENET_RSEM - Receive FIFO Section Empty Threshold
+ * - ENET_RAEM - Receive FIFO Almost Empty Threshold
+ * - ENET_RAFL - Receive FIFO Almost Full Threshold
+ * - ENET_TSEM - Transmit FIFO Section Empty Threshold
+ * - ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ * - ENET_TAFL - Transmit FIFO Almost Full Threshold
+ * - ENET_TIPG - Transmit Inter-Packet Gap
+ * - ENET_FTRL - Frame Truncation Length
+ * - ENET_TACC - Transmit Accelerator Function Configuration
+ * - ENET_RACC - Receive Accelerator Function Configuration
+ * - ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ * - ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ * - ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ * - ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ * - ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ * - ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ * - ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ * - ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ * - ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ * - ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ * - ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ * - ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ * - ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ * - ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ * - ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ * - ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ * - ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ * - ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ * - ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ * - ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ * - ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ * - ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ * - ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ * - ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ * - ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ * - ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ * - ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ * - ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ * - ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ * - ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ * - ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ * - ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ * - ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ * - ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ * - ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ * - ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ * - ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ * - ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ * - ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ * - ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ * - ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ * - ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ * - ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ * - ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ * - ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ * - ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ * - ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ * - ENET_ATCR - Adjustable Timer Control Register
+ * - ENET_ATVR - Timer Value Register
+ * - ENET_ATOFF - Timer Offset Register
+ * - ENET_ATPER - Timer Period Register
+ * - ENET_ATCOR - Timer Correction Register
+ * - ENET_ATINC - Time-Stamping Clock Period Register
+ * - ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ * - ENET_TGSR - Timer Global Status Register
+ * - ENET_TCSR - Timer Control Status Register
+ * - ENET_TCCR - Timer Compare Capture Register
+ */
+
+#define ENET_INSTANCE_COUNT (1U) /*!< Number of instances of the ENET module. */
+#define ENET_IDX (0U) /*!< Instance number for ENET. */
+
+/*******************************************************************************
+ * ENET_EIR - Interrupt Event Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_EIR - Interrupt Event Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an event occurs that sets a bit in EIR, an interrupt occurs if the
+ * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
+ * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
+ * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
+ * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
+ * Legacy mode does not require these flags to be enabled.
+ */
+/*!
+ * @name Constants and macros for entire ENET_EIR register
+ */
+/*@{*/
+#define ENET_RD_EIR(base)        (ENET_EIR_REG(base))
+#define ENET_WR_EIR(base, value) (ENET_EIR_REG(base) = (value))
+#define ENET_RMW_EIR(base, mask, value) (ENET_WR_EIR(base, (ENET_RD_EIR(base) & ~(mask)) | (value)))
+#define ENET_SET_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) |  (value)))
+#define ENET_CLR_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) & ~(value)))
+#define ENET_TOG_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_EIR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
+ *
+ * The adjustable timer reached the period event. A period event interrupt can
+ * be generated if ATCR[PEREN] is set and the timer wraps according to the
+ * periodic setting in the ATPER register. Set the timer period value before setting
+ * ATCR[PEREN].
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TS_TIMER field. */
+#define ENET_RD_EIR_TS_TIMER(base) ((ENET_EIR_REG(base) & ENET_EIR_TS_TIMER_MASK) >> ENET_EIR_TS_TIMER_SHIFT)
+#define ENET_BRD_EIR_TS_TIMER(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_TIMER_SHIFT))
+
+/*! @brief Set the TS_TIMER field to a new value. */
+#define ENET_WR_EIR_TS_TIMER(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TS_TIMER(value)))
+#define ENET_BWR_EIR_TS_TIMER(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_TIMER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
+ *
+ * Indicates that the timestamp of the last transmitted timing frame is
+ * available in the ATSTMP register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TS_AVAIL field. */
+#define ENET_RD_EIR_TS_AVAIL(base) ((ENET_EIR_REG(base) & ENET_EIR_TS_AVAIL_MASK) >> ENET_EIR_TS_AVAIL_SHIFT)
+#define ENET_BRD_EIR_TS_AVAIL(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_AVAIL_SHIFT))
+
+/*! @brief Set the TS_AVAIL field to a new value. */
+#define ENET_WR_EIR_TS_AVAIL(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TS_AVAIL_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TS_AVAIL(value)))
+#define ENET_BWR_EIR_TS_AVAIL(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_AVAIL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field WAKEUP[17] (W1C)
+ *
+ * Read-only status bit to indicate that a magic packet has been detected. Will
+ * act only if ECR[MAGICEN] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_WAKEUP field. */
+#define ENET_RD_EIR_WAKEUP(base) ((ENET_EIR_REG(base) & ENET_EIR_WAKEUP_MASK) >> ENET_EIR_WAKEUP_SHIFT)
+#define ENET_BRD_EIR_WAKEUP(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_WAKEUP_SHIFT))
+
+/*! @brief Set the WAKEUP field to a new value. */
+#define ENET_WR_EIR_WAKEUP(base, value) (ENET_RMW_EIR(base, (ENET_EIR_WAKEUP_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_WAKEUP(value)))
+#define ENET_BWR_EIR_WAKEUP(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_WAKEUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field PLR[18] (W1C)
+ *
+ * Indicates a frame was received with a payload length error. See Frame
+ * Length/Type Verification: Payload Length Check for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_PLR field. */
+#define ENET_RD_EIR_PLR(base) ((ENET_EIR_REG(base) & ENET_EIR_PLR_MASK) >> ENET_EIR_PLR_SHIFT)
+#define ENET_BRD_EIR_PLR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_PLR_SHIFT))
+
+/*! @brief Set the PLR field to a new value. */
+#define ENET_WR_EIR_PLR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_PLR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_PLR(value)))
+#define ENET_BWR_EIR_PLR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_PLR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field UN[19] (W1C)
+ *
+ * Indicates the transmit FIFO became empty before the complete frame was
+ * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
+ * frame is discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_UN field. */
+#define ENET_RD_EIR_UN(base) ((ENET_EIR_REG(base) & ENET_EIR_UN_MASK) >> ENET_EIR_UN_SHIFT)
+#define ENET_BRD_EIR_UN(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_UN_SHIFT))
+
+/*! @brief Set the UN field to a new value. */
+#define ENET_WR_EIR_UN(base, value) (ENET_RMW_EIR(base, (ENET_EIR_UN_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_UN(value)))
+#define ENET_BWR_EIR_UN(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_UN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RL[20] (W1C)
+ *
+ * Indicates a collision occurred on each of 16 successive attempts to transmit
+ * the frame. The frame is discarded without being transmitted and transmission
+ * of the next frame commences. This error can only occur in half-duplex mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RL field. */
+#define ENET_RD_EIR_RL(base) ((ENET_EIR_REG(base) & ENET_EIR_RL_MASK) >> ENET_EIR_RL_SHIFT)
+#define ENET_BRD_EIR_RL(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RL_SHIFT))
+
+/*! @brief Set the RL field to a new value. */
+#define ENET_WR_EIR_RL(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RL_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RL(value)))
+#define ENET_BWR_EIR_RL(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field LC[21] (W1C)
+ *
+ * Indicates a collision occurred beyond the collision window (slot time) in
+ * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
+ * frame is discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_LC field. */
+#define ENET_RD_EIR_LC(base) ((ENET_EIR_REG(base) & ENET_EIR_LC_MASK) >> ENET_EIR_LC_SHIFT)
+#define ENET_BRD_EIR_LC(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_LC_SHIFT))
+
+/*! @brief Set the LC field to a new value. */
+#define ENET_WR_EIR_LC(base, value) (ENET_RMW_EIR(base, (ENET_EIR_LC_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_LC(value)))
+#define ENET_BWR_EIR_LC(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_LC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field EBERR[22] (W1C)
+ *
+ * Indicates a system bus error occurred when a uDMA transaction is underway.
+ * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
+ * MAC. When this occurs, software must ensure proper actions, possibly resetting
+ * the system, to resume normal operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_EBERR field. */
+#define ENET_RD_EIR_EBERR(base) ((ENET_EIR_REG(base) & ENET_EIR_EBERR_MASK) >> ENET_EIR_EBERR_SHIFT)
+#define ENET_BRD_EIR_EBERR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_EBERR_SHIFT))
+
+/*! @brief Set the EBERR field to a new value. */
+#define ENET_WR_EIR_EBERR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_EBERR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_EBERR(value)))
+#define ENET_BWR_EIR_EBERR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_EBERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field MII[23] (W1C)
+ *
+ * Indicates that the MII has completed the data transfer requested.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_MII field. */
+#define ENET_RD_EIR_MII(base) ((ENET_EIR_REG(base) & ENET_EIR_MII_MASK) >> ENET_EIR_MII_SHIFT)
+#define ENET_BRD_EIR_MII(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_MII_SHIFT))
+
+/*! @brief Set the MII field to a new value. */
+#define ENET_WR_EIR_MII(base, value) (ENET_RMW_EIR(base, (ENET_EIR_MII_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_MII(value)))
+#define ENET_BWR_EIR_MII(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_MII_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RXB[24] (W1C)
+ *
+ * Indicates a receive buffer descriptor is not the last in the frame has been
+ * updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RXB field. */
+#define ENET_RD_EIR_RXB(base) ((ENET_EIR_REG(base) & ENET_EIR_RXB_MASK) >> ENET_EIR_RXB_SHIFT)
+#define ENET_BRD_EIR_RXB(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXB_SHIFT))
+
+/*! @brief Set the RXB field to a new value. */
+#define ENET_WR_EIR_RXB(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RXB_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RXB(value)))
+#define ENET_BWR_EIR_RXB(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RXF[25] (W1C)
+ *
+ * Indicates a frame has been received and the last corresponding buffer
+ * descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RXF field. */
+#define ENET_RD_EIR_RXF(base) ((ENET_EIR_REG(base) & ENET_EIR_RXF_MASK) >> ENET_EIR_RXF_SHIFT)
+#define ENET_BRD_EIR_RXF(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXF_SHIFT))
+
+/*! @brief Set the RXF field to a new value. */
+#define ENET_WR_EIR_RXF(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RXF_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RXF(value)))
+#define ENET_BWR_EIR_RXF(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TXB[26] (W1C)
+ *
+ * Indicates a transmit buffer descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TXB field. */
+#define ENET_RD_EIR_TXB(base) ((ENET_EIR_REG(base) & ENET_EIR_TXB_MASK) >> ENET_EIR_TXB_SHIFT)
+#define ENET_BRD_EIR_TXB(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXB_SHIFT))
+
+/*! @brief Set the TXB field to a new value. */
+#define ENET_WR_EIR_TXB(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TXB_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TXB(value)))
+#define ENET_BWR_EIR_TXB(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TXF[27] (W1C)
+ *
+ * Indicates a frame has been transmitted and the last corresponding buffer
+ * descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TXF field. */
+#define ENET_RD_EIR_TXF(base) ((ENET_EIR_REG(base) & ENET_EIR_TXF_MASK) >> ENET_EIR_TXF_SHIFT)
+#define ENET_BRD_EIR_TXF(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXF_SHIFT))
+
+/*! @brief Set the TXF field to a new value. */
+#define ENET_WR_EIR_TXF(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TXF_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TXF(value)))
+#define ENET_BWR_EIR_TXF(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field GRA[28] (W1C)
+ *
+ * This interrupt is asserted after the transmitter is put into a pause state
+ * after completion of the frame currently being transmitted. See Graceful Transmit
+ * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
+ * asserted only when the TX transitions into the stopped state. If this bit is
+ * cleared by writing 1 and the TX is still stopped, the bit is not set again.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_GRA field. */
+#define ENET_RD_EIR_GRA(base) ((ENET_EIR_REG(base) & ENET_EIR_GRA_MASK) >> ENET_EIR_GRA_SHIFT)
+#define ENET_BRD_EIR_GRA(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_GRA_SHIFT))
+
+/*! @brief Set the GRA field to a new value. */
+#define ENET_WR_EIR_GRA(base, value) (ENET_RMW_EIR(base, (ENET_EIR_GRA_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_GRA(value)))
+#define ENET_BWR_EIR_GRA(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_GRA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field BABT[29] (W1C)
+ *
+ * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
+ * this condition is caused when a frame that is too long is placed into the
+ * transmit data buffer(s). Truncation does not occur.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_BABT field. */
+#define ENET_RD_EIR_BABT(base) ((ENET_EIR_REG(base) & ENET_EIR_BABT_MASK) >> ENET_EIR_BABT_SHIFT)
+#define ENET_BRD_EIR_BABT(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABT_SHIFT))
+
+/*! @brief Set the BABT field to a new value. */
+#define ENET_WR_EIR_BABT(base, value) (ENET_RMW_EIR(base, (ENET_EIR_BABT_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABR_MASK), ENET_EIR_BABT(value)))
+#define ENET_BWR_EIR_BABT(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field BABR[30] (W1C)
+ *
+ * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_BABR field. */
+#define ENET_RD_EIR_BABR(base) ((ENET_EIR_REG(base) & ENET_EIR_BABR_MASK) >> ENET_EIR_BABR_SHIFT)
+#define ENET_BRD_EIR_BABR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABR_SHIFT))
+
+/*! @brief Set the BABR field to a new value. */
+#define ENET_WR_EIR_BABR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_BABR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK), ENET_EIR_BABR(value)))
+#define ENET_BWR_EIR_BABR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_EIMR - Interrupt Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_EIMR - Interrupt Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * EIMR controls which interrupt events are allowed to generate actual
+ * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
+ * and EIMR registers are set, an interrupt is generated. The interrupt signal
+ * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
+ * 0 is written to the EIMR field.
+ */
+/*!
+ * @name Constants and macros for entire ENET_EIMR register
+ */
+/*@{*/
+#define ENET_RD_EIMR(base)       (ENET_EIMR_REG(base))
+#define ENET_WR_EIMR(base, value) (ENET_EIMR_REG(base) = (value))
+#define ENET_RMW_EIMR(base, mask, value) (ENET_WR_EIMR(base, (ENET_RD_EIMR(base) & ~(mask)) | (value)))
+#define ENET_SET_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) |  (value)))
+#define ENET_CLR_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) & ~(value)))
+#define ENET_TOG_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_EIMR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_TIMER field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TS_TIMER field. */
+#define ENET_RD_EIMR_TS_TIMER(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TS_TIMER_MASK) >> ENET_EIMR_TS_TIMER_SHIFT)
+#define ENET_BRD_EIMR_TS_TIMER(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_TIMER_SHIFT))
+
+/*! @brief Set the TS_TIMER field to a new value. */
+#define ENET_WR_EIMR_TS_TIMER(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TS_TIMER_MASK, ENET_EIMR_TS_TIMER(value)))
+#define ENET_BWR_EIMR_TS_TIMER(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_TIMER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TS_AVAIL field. */
+#define ENET_RD_EIMR_TS_AVAIL(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TS_AVAIL_MASK) >> ENET_EIMR_TS_AVAIL_SHIFT)
+#define ENET_BRD_EIMR_TS_AVAIL(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_AVAIL_SHIFT))
+
+/*! @brief Set the TS_AVAIL field to a new value. */
+#define ENET_WR_EIMR_TS_AVAIL(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TS_AVAIL_MASK, ENET_EIMR_TS_AVAIL(value)))
+#define ENET_BWR_EIMR_TS_AVAIL(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_AVAIL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field WAKEUP[17] (RW)
+ *
+ * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR WAKEUP field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_WAKEUP field. */
+#define ENET_RD_EIMR_WAKEUP(base) ((ENET_EIMR_REG(base) & ENET_EIMR_WAKEUP_MASK) >> ENET_EIMR_WAKEUP_SHIFT)
+#define ENET_BRD_EIMR_WAKEUP(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_WAKEUP_SHIFT))
+
+/*! @brief Set the WAKEUP field to a new value. */
+#define ENET_WR_EIMR_WAKEUP(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_WAKEUP_MASK, ENET_EIMR_WAKEUP(value)))
+#define ENET_BWR_EIMR_WAKEUP(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_WAKEUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field PLR[18] (RW)
+ *
+ * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR PLR field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_PLR field. */
+#define ENET_RD_EIMR_PLR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_PLR_MASK) >> ENET_EIMR_PLR_SHIFT)
+#define ENET_BRD_EIMR_PLR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_PLR_SHIFT))
+
+/*! @brief Set the PLR field to a new value. */
+#define ENET_WR_EIMR_PLR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_PLR_MASK, ENET_EIMR_PLR(value)))
+#define ENET_BWR_EIMR_PLR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_PLR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field UN[19] (RW)
+ *
+ * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR UN field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_UN field. */
+#define ENET_RD_EIMR_UN(base) ((ENET_EIMR_REG(base) & ENET_EIMR_UN_MASK) >> ENET_EIMR_UN_SHIFT)
+#define ENET_BRD_EIMR_UN(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_UN_SHIFT))
+
+/*! @brief Set the UN field to a new value. */
+#define ENET_WR_EIMR_UN(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_UN_MASK, ENET_EIMR_UN(value)))
+#define ENET_BWR_EIMR_UN(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_UN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RL[20] (RW)
+ *
+ * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR RL field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RL field. */
+#define ENET_RD_EIMR_RL(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RL_MASK) >> ENET_EIMR_RL_SHIFT)
+#define ENET_BRD_EIMR_RL(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RL_SHIFT))
+
+/*! @brief Set the RL field to a new value. */
+#define ENET_WR_EIMR_RL(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RL_MASK, ENET_EIMR_RL(value)))
+#define ENET_BWR_EIMR_RL(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field LC[21] (RW)
+ *
+ * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR LC field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_LC field. */
+#define ENET_RD_EIMR_LC(base) ((ENET_EIMR_REG(base) & ENET_EIMR_LC_MASK) >> ENET_EIMR_LC_SHIFT)
+#define ENET_BRD_EIMR_LC(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_LC_SHIFT))
+
+/*! @brief Set the LC field to a new value. */
+#define ENET_WR_EIMR_LC(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_LC_MASK, ENET_EIMR_LC(value)))
+#define ENET_BWR_EIMR_LC(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_LC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field EBERR[22] (RW)
+ *
+ * Corresponds to interrupt source EIR[EBERR] and determines whether an
+ * interrupt condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR EBERR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_EBERR field. */
+#define ENET_RD_EIMR_EBERR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_EBERR_MASK) >> ENET_EIMR_EBERR_SHIFT)
+#define ENET_BRD_EIMR_EBERR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_EBERR_SHIFT))
+
+/*! @brief Set the EBERR field to a new value. */
+#define ENET_WR_EIMR_EBERR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_EBERR_MASK, ENET_EIMR_EBERR(value)))
+#define ENET_BWR_EIMR_EBERR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_EBERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field MII[23] (RW)
+ *
+ * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR MII field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_MII field. */
+#define ENET_RD_EIMR_MII(base) ((ENET_EIMR_REG(base) & ENET_EIMR_MII_MASK) >> ENET_EIMR_MII_SHIFT)
+#define ENET_BRD_EIMR_MII(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_MII_SHIFT))
+
+/*! @brief Set the MII field to a new value. */
+#define ENET_WR_EIMR_MII(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_MII_MASK, ENET_EIMR_MII(value)))
+#define ENET_BWR_EIMR_MII(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_MII_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RXB[24] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXB field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RXB field. */
+#define ENET_RD_EIMR_RXB(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RXB_MASK) >> ENET_EIMR_RXB_SHIFT)
+#define ENET_BRD_EIMR_RXB(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXB_SHIFT))
+
+/*! @brief Set the RXB field to a new value. */
+#define ENET_WR_EIMR_RXB(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RXB_MASK, ENET_EIMR_RXB(value)))
+#define ENET_BWR_EIMR_RXB(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RXF[25] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RXF field. */
+#define ENET_RD_EIMR_RXF(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RXF_MASK) >> ENET_EIMR_RXF_SHIFT)
+#define ENET_BRD_EIMR_RXF(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXF_SHIFT))
+
+/*! @brief Set the RXF field to a new value. */
+#define ENET_WR_EIMR_RXF(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RXF_MASK, ENET_EIMR_RXF(value)))
+#define ENET_BWR_EIMR_RXF(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TXB[26] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TXB field. */
+#define ENET_RD_EIMR_TXB(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TXB_MASK) >> ENET_EIMR_TXB_SHIFT)
+#define ENET_BRD_EIMR_TXB(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXB_SHIFT))
+
+/*! @brief Set the TXB field to a new value. */
+#define ENET_WR_EIMR_TXB(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TXB_MASK, ENET_EIMR_TXB(value)))
+#define ENET_BWR_EIMR_TXB(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TXF[27] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TXF field. */
+#define ENET_RD_EIMR_TXF(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TXF_MASK) >> ENET_EIMR_TXF_SHIFT)
+#define ENET_BRD_EIMR_TXF(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXF_SHIFT))
+
+/*! @brief Set the TXF field to a new value. */
+#define ENET_WR_EIMR_TXF(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TXF_MASK, ENET_EIMR_TXF(value)))
+#define ENET_BWR_EIMR_TXF(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field GRA[28] (RW)
+ *
+ * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR GRA field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_GRA field. */
+#define ENET_RD_EIMR_GRA(base) ((ENET_EIMR_REG(base) & ENET_EIMR_GRA_MASK) >> ENET_EIMR_GRA_SHIFT)
+#define ENET_BRD_EIMR_GRA(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_GRA_SHIFT))
+
+/*! @brief Set the GRA field to a new value. */
+#define ENET_WR_EIMR_GRA(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_GRA_MASK, ENET_EIMR_GRA(value)))
+#define ENET_BWR_EIMR_GRA(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_GRA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field BABT[29] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABT
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_BABT field. */
+#define ENET_RD_EIMR_BABT(base) ((ENET_EIMR_REG(base) & ENET_EIMR_BABT_MASK) >> ENET_EIMR_BABT_SHIFT)
+#define ENET_BRD_EIMR_BABT(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABT_SHIFT))
+
+/*! @brief Set the BABT field to a new value. */
+#define ENET_WR_EIMR_BABT(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_BABT_MASK, ENET_EIMR_BABT(value)))
+#define ENET_BWR_EIMR_BABT(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field BABR[30] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_BABR field. */
+#define ENET_RD_EIMR_BABR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_BABR_MASK) >> ENET_EIMR_BABR_SHIFT)
+#define ENET_BRD_EIMR_BABR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABR_SHIFT))
+
+/*! @brief Set the BABR field to a new value. */
+#define ENET_WR_EIMR_BABR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_BABR_MASK, ENET_EIMR_BABR(value)))
+#define ENET_BWR_EIMR_BABR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RDAR - Receive Descriptor Active Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RDAR - Receive Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDAR is a command register, written by the user, to indicate that the receive
+ * descriptor ring has been updated, that is, that the driver produced empty
+ * receive buffers with the empty bit set.
+ */
+/*!
+ * @name Constants and macros for entire ENET_RDAR register
+ */
+/*@{*/
+#define ENET_RD_RDAR(base)       (ENET_RDAR_REG(base))
+#define ENET_WR_RDAR(base, value) (ENET_RDAR_REG(base) = (value))
+#define ENET_RMW_RDAR(base, mask, value) (ENET_WR_RDAR(base, (ENET_RD_RDAR(base) & ~(mask)) | (value)))
+#define ENET_SET_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) |  (value)))
+#define ENET_CLR_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) & ~(value)))
+#define ENET_TOG_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDAR, field RDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This field is cleared by the MAC device when no additional empty
+ * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
+ * from set to cleared or when ECR[RESET] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RDAR_RDAR field. */
+#define ENET_RD_RDAR_RDAR(base) ((ENET_RDAR_REG(base) & ENET_RDAR_RDAR_MASK) >> ENET_RDAR_RDAR_SHIFT)
+#define ENET_BRD_RDAR_RDAR(base) (BITBAND_ACCESS32(&ENET_RDAR_REG(base), ENET_RDAR_RDAR_SHIFT))
+
+/*! @brief Set the RDAR field to a new value. */
+#define ENET_WR_RDAR_RDAR(base, value) (ENET_RMW_RDAR(base, ENET_RDAR_RDAR_MASK, ENET_RDAR_RDAR(value)))
+#define ENET_BWR_RDAR_RDAR(base, value) (BITBAND_ACCESS32(&ENET_RDAR_REG(base), ENET_RDAR_RDAR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TDAR - Transmit Descriptor Active Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TDAR - Transmit Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The TDAR is a command register that the user writes to indicate that the
+ * transmit descriptor ring has been updated, that is, that transmit buffers have
+ * been produced by the driver with the ready bit set in the buffer descriptor. The
+ * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
+ * cleared, or when ECR[RESET] is set.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TDAR register
+ */
+/*@{*/
+#define ENET_RD_TDAR(base)       (ENET_TDAR_REG(base))
+#define ENET_WR_TDAR(base, value) (ENET_TDAR_REG(base) = (value))
+#define ENET_RMW_TDAR(base, mask, value) (ENET_WR_TDAR(base, (ENET_RD_TDAR(base) & ~(mask)) | (value)))
+#define ENET_SET_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) |  (value)))
+#define ENET_CLR_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) & ~(value)))
+#define ENET_TOG_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDAR, field TDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This bit is cleared by the MAC device when no additional ready descriptors
+ * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
+ * set to cleared or when ECR[RESET] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TDAR_TDAR field. */
+#define ENET_RD_TDAR_TDAR(base) ((ENET_TDAR_REG(base) & ENET_TDAR_TDAR_MASK) >> ENET_TDAR_TDAR_SHIFT)
+#define ENET_BRD_TDAR_TDAR(base) (BITBAND_ACCESS32(&ENET_TDAR_REG(base), ENET_TDAR_TDAR_SHIFT))
+
+/*! @brief Set the TDAR field to a new value. */
+#define ENET_WR_TDAR_TDAR(base, value) (ENET_RMW_TDAR(base, ENET_TDAR_TDAR_MASK, ENET_TDAR_TDAR(value)))
+#define ENET_BWR_TDAR_TDAR(base, value) (BITBAND_ACCESS32(&ENET_TDAR_REG(base), ENET_TDAR_TDAR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ECR - Ethernet Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ECR - Ethernet Control Register (RW)
+ *
+ * Reset value: 0xF0000000U
+ *
+ * ECR is a read/write user register, though hardware may also alter fields in
+ * this register. It controls many of the high level features of the Ethernet MAC,
+ * including legacy FEC support through the EN1588 field.
+ */
+/*!
+ * @name Constants and macros for entire ENET_ECR register
+ */
+/*@{*/
+#define ENET_RD_ECR(base)        (ENET_ECR_REG(base))
+#define ENET_WR_ECR(base, value) (ENET_ECR_REG(base) = (value))
+#define ENET_RMW_ECR(base, mask, value) (ENET_WR_ECR(base, (ENET_RD_ECR(base) & ~(mask)) | (value)))
+#define ENET_SET_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) |  (value)))
+#define ENET_CLR_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) & ~(value)))
+#define ENET_TOG_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ECR bitfields
+ */
+
+/*!
+ * @name Register ENET_ECR, field RESET[0] (RW)
+ *
+ * When this field is set, it clears the ETHEREN field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_RESET field. */
+#define ENET_RD_ECR_RESET(base) ((ENET_ECR_REG(base) & ENET_ECR_RESET_MASK) >> ENET_ECR_RESET_SHIFT)
+#define ENET_BRD_ECR_RESET(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_RESET_SHIFT))
+
+/*! @brief Set the RESET field to a new value. */
+#define ENET_WR_ECR_RESET(base, value) (ENET_RMW_ECR(base, ENET_ECR_RESET_MASK, ENET_ECR_RESET(value)))
+#define ENET_BWR_ECR_RESET(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_RESET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field ETHEREN[1] (RW)
+ *
+ * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
+ * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
+ * descriptor, and FIFO control logic are reset, including the buffer descriptor and
+ * FIFO pointers. Hardware clears this field under the following conditions: RESET
+ * is set by software An error condition causes the EBERR field to set. ETHEREN
+ * must be set at the very last step during ENET
+ * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
+ * is cleared to 0 by software then then next time ETHEREN is set, the EIR
+ * interrupts must cleared to 0 due to previous pending interrupts.
+ *
+ * Values:
+ * - 0b0 - Reception immediately stops and transmission stops after a bad CRC is
+ *     appended to any currently transmitted frame.
+ * - 0b1 - MAC is enabled, and reception and transmission are possible.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_ETHEREN field. */
+#define ENET_RD_ECR_ETHEREN(base) ((ENET_ECR_REG(base) & ENET_ECR_ETHEREN_MASK) >> ENET_ECR_ETHEREN_SHIFT)
+#define ENET_BRD_ECR_ETHEREN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_ETHEREN_SHIFT))
+
+/*! @brief Set the ETHEREN field to a new value. */
+#define ENET_WR_ECR_ETHEREN(base, value) (ENET_RMW_ECR(base, ENET_ECR_ETHEREN_MASK, ENET_ECR_ETHEREN(value)))
+#define ENET_BWR_ECR_ETHEREN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_ETHEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field MAGICEN[2] (RW)
+ *
+ * Enables/disables magic packet detection. MAGICEN is relevant only if the
+ * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
+ * sleep mode and magic packet detection.
+ *
+ * Values:
+ * - 0b0 - Magic detection logic disabled.
+ * - 0b1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a
+ *     frame is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_MAGICEN field. */
+#define ENET_RD_ECR_MAGICEN(base) ((ENET_ECR_REG(base) & ENET_ECR_MAGICEN_MASK) >> ENET_ECR_MAGICEN_SHIFT)
+#define ENET_BRD_ECR_MAGICEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_MAGICEN_SHIFT))
+
+/*! @brief Set the MAGICEN field to a new value. */
+#define ENET_WR_ECR_MAGICEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_MAGICEN_MASK, ENET_ECR_MAGICEN(value)))
+#define ENET_BWR_ECR_MAGICEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_MAGICEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field SLEEP[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operating mode.
+ * - 0b1 - Sleep mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_SLEEP field. */
+#define ENET_RD_ECR_SLEEP(base) ((ENET_ECR_REG(base) & ENET_ECR_SLEEP_MASK) >> ENET_ECR_SLEEP_SHIFT)
+#define ENET_BRD_ECR_SLEEP(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_SLEEP_SHIFT))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define ENET_WR_ECR_SLEEP(base, value) (ENET_RMW_ECR(base, ENET_ECR_SLEEP_MASK, ENET_ECR_SLEEP(value)))
+#define ENET_BWR_ECR_SLEEP(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_SLEEP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field EN1588[4] (RW)
+ *
+ * Enables enhanced functionality of the MAC.
+ *
+ * Values:
+ * - 0b0 - Legacy FEC buffer descriptors and functions enabled.
+ * - 0b1 - Enhanced frame time-stamping functions enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_EN1588 field. */
+#define ENET_RD_ECR_EN1588(base) ((ENET_ECR_REG(base) & ENET_ECR_EN1588_MASK) >> ENET_ECR_EN1588_SHIFT)
+#define ENET_BRD_ECR_EN1588(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_EN1588_SHIFT))
+
+/*! @brief Set the EN1588 field to a new value. */
+#define ENET_WR_ECR_EN1588(base, value) (ENET_RMW_ECR(base, ENET_ECR_EN1588_MASK, ENET_ECR_EN1588(value)))
+#define ENET_BWR_ECR_EN1588(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_EN1588_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field DBGEN[6] (RW)
+ *
+ * Enables the MAC to enter hardware freeze mode when the device enters debug
+ * mode.
+ *
+ * Values:
+ * - 0b0 - MAC continues operation in debug mode.
+ * - 0b1 - MAC enters hardware freeze mode when the processor is in debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_DBGEN field. */
+#define ENET_RD_ECR_DBGEN(base) ((ENET_ECR_REG(base) & ENET_ECR_DBGEN_MASK) >> ENET_ECR_DBGEN_SHIFT)
+#define ENET_BRD_ECR_DBGEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBGEN_SHIFT))
+
+/*! @brief Set the DBGEN field to a new value. */
+#define ENET_WR_ECR_DBGEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_DBGEN_MASK, ENET_ECR_DBGEN(value)))
+#define ENET_BWR_ECR_DBGEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field STOPEN[7] (RW)
+ *
+ * Controls device behavior in doze mode. In doze mode, if this field is set
+ * then all the clocks of the ENET assembly are disabled, except the RMII /MII
+ * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
+ * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
+ * can still wake the system after receiving a magic packet in stop mode. MAGICEN
+ * must be set prior to entering sleep/stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_STOPEN field. */
+#define ENET_RD_ECR_STOPEN(base) ((ENET_ECR_REG(base) & ENET_ECR_STOPEN_MASK) >> ENET_ECR_STOPEN_SHIFT)
+#define ENET_BRD_ECR_STOPEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_STOPEN_SHIFT))
+
+/*! @brief Set the STOPEN field to a new value. */
+#define ENET_WR_ECR_STOPEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_STOPEN_MASK, ENET_ECR_STOPEN(value)))
+#define ENET_BWR_ECR_STOPEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_STOPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field DBSWP[8] (RW)
+ *
+ * Swaps the byte locations of the buffer descriptors. This field must be
+ * written to 1 after reset.
+ *
+ * Values:
+ * - 0b0 - The buffer descriptor bytes are not swapped to support big-endian
+ *     devices.
+ * - 0b1 - The buffer descriptor bytes are swapped to support little-endian
+ *     devices.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_DBSWP field. */
+#define ENET_RD_ECR_DBSWP(base) ((ENET_ECR_REG(base) & ENET_ECR_DBSWP_MASK) >> ENET_ECR_DBSWP_SHIFT)
+#define ENET_BRD_ECR_DBSWP(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBSWP_SHIFT))
+
+/*! @brief Set the DBSWP field to a new value. */
+#define ENET_WR_ECR_DBSWP(base, value) (ENET_RMW_ECR(base, ENET_ECR_DBSWP_MASK, ENET_ECR_DBSWP(value)))
+#define ENET_BWR_ECR_DBSWP(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBSWP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MMFR - MII Management Frame Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MMFR - MII Management Frame Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Writing to MMFR triggers a management frame transaction to the PHY device
+ * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
+ * during a write to MMFR, an MII frame is generated with the data previously written
+ * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
+ * MSCR is currently zero. If the MMFR register is written while frame generation is
+ * in progress, the frame contents are altered. Software must use the EIR[MII]
+ * interrupt indication to avoid writing to the MMFR register while frame
+ * generation is in progress.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MMFR register
+ */
+/*@{*/
+#define ENET_RD_MMFR(base)       (ENET_MMFR_REG(base))
+#define ENET_WR_MMFR(base, value) (ENET_MMFR_REG(base) = (value))
+#define ENET_RMW_MMFR(base, mask, value) (ENET_WR_MMFR(base, (ENET_RD_MMFR(base) & ~(mask)) | (value)))
+#define ENET_SET_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) |  (value)))
+#define ENET_CLR_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) & ~(value)))
+#define ENET_TOG_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MMFR bitfields
+ */
+
+/*!
+ * @name Register ENET_MMFR, field DATA[15:0] (RW)
+ *
+ * This is the field for data to be written to or read from the PHY register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_DATA field. */
+#define ENET_RD_MMFR_DATA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT)
+#define ENET_BRD_MMFR_DATA(base) (ENET_RD_MMFR_DATA(base))
+
+/*! @brief Set the DATA field to a new value. */
+#define ENET_WR_MMFR_DATA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_DATA_MASK, ENET_MMFR_DATA(value)))
+#define ENET_BWR_MMFR_DATA(base, value) (ENET_WR_MMFR_DATA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field TA[17:16] (RW)
+ *
+ * This field must be programmed to 10 to generate a valid MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_TA field. */
+#define ENET_RD_MMFR_TA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_TA_MASK) >> ENET_MMFR_TA_SHIFT)
+#define ENET_BRD_MMFR_TA(base) (ENET_RD_MMFR_TA(base))
+
+/*! @brief Set the TA field to a new value. */
+#define ENET_WR_MMFR_TA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_TA_MASK, ENET_MMFR_TA(value)))
+#define ENET_BWR_MMFR_TA(base, value) (ENET_WR_MMFR_TA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field RA[22:18] (RW)
+ *
+ * Specifies one of up to 32 registers within the specified PHY device.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_RA field. */
+#define ENET_RD_MMFR_RA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_RA_MASK) >> ENET_MMFR_RA_SHIFT)
+#define ENET_BRD_MMFR_RA(base) (ENET_RD_MMFR_RA(base))
+
+/*! @brief Set the RA field to a new value. */
+#define ENET_WR_MMFR_RA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_RA_MASK, ENET_MMFR_RA(value)))
+#define ENET_BWR_MMFR_RA(base, value) (ENET_WR_MMFR_RA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field PA[27:23] (RW)
+ *
+ * Specifies one of up to 32 attached PHY devices.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_PA field. */
+#define ENET_RD_MMFR_PA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_PA_MASK) >> ENET_MMFR_PA_SHIFT)
+#define ENET_BRD_MMFR_PA(base) (ENET_RD_MMFR_PA(base))
+
+/*! @brief Set the PA field to a new value. */
+#define ENET_WR_MMFR_PA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_PA_MASK, ENET_MMFR_PA(value)))
+#define ENET_BWR_MMFR_PA(base, value) (ENET_WR_MMFR_PA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field OP[29:28] (RW)
+ *
+ * Determines the frame operation.
+ *
+ * Values:
+ * - 0b00 - Write frame operation, but not MII compliant.
+ * - 0b01 - Write frame operation for a valid MII management frame.
+ * - 0b10 - Read frame operation for a valid MII management frame.
+ * - 0b11 - Read frame operation, but not MII compliant.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_OP field. */
+#define ENET_RD_MMFR_OP(base) ((ENET_MMFR_REG(base) & ENET_MMFR_OP_MASK) >> ENET_MMFR_OP_SHIFT)
+#define ENET_BRD_MMFR_OP(base) (ENET_RD_MMFR_OP(base))
+
+/*! @brief Set the OP field to a new value. */
+#define ENET_WR_MMFR_OP(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_OP_MASK, ENET_MMFR_OP(value)))
+#define ENET_BWR_MMFR_OP(base, value) (ENET_WR_MMFR_OP(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field ST[31:30] (RW)
+ *
+ * These fields must be programmed to 01 for a valid MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_ST field. */
+#define ENET_RD_MMFR_ST(base) ((ENET_MMFR_REG(base) & ENET_MMFR_ST_MASK) >> ENET_MMFR_ST_SHIFT)
+#define ENET_BRD_MMFR_ST(base) (ENET_RD_MMFR_ST(base))
+
+/*! @brief Set the ST field to a new value. */
+#define ENET_WR_MMFR_ST(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_ST_MASK, ENET_MMFR_ST(value)))
+#define ENET_BWR_MMFR_ST(base, value) (ENET_WR_MMFR_ST(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MSCR - MII Speed Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MSCR - MII Speed Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * MSCR provides control of the MII clock (MDC pin) frequency and allows a
+ * preamble drop on the MII management frame. The MII_SPEED field must be programmed
+ * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
+ * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
+ * a non-zero value to source a read or write management frame. After the
+ * management frame is complete, the MSCR register may optionally be cleared to turn
+ * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
+ * changes during operation. This change takes effect following a rising or falling
+ * edge of MDC. If the internal module clock is 25 MHz, programming this register
+ * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
+ * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
+ * MII_SPEED as a function of internal module clock frequency. Programming Examples
+ * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
+ * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
+ * 0xD 2.36 MHz
+ */
+/*!
+ * @name Constants and macros for entire ENET_MSCR register
+ */
+/*@{*/
+#define ENET_RD_MSCR(base)       (ENET_MSCR_REG(base))
+#define ENET_WR_MSCR(base, value) (ENET_MSCR_REG(base) = (value))
+#define ENET_RMW_MSCR(base, mask, value) (ENET_WR_MSCR(base, (ENET_RD_MSCR(base) & ~(mask)) | (value)))
+#define ENET_SET_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) |  (value)))
+#define ENET_CLR_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) & ~(value)))
+#define ENET_TOG_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MSCR bitfields
+ */
+
+/*!
+ * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
+ *
+ * Controls the frequency of the MII management interface clock (MDC) relative
+ * to the internal module clock. A value of 0 in this field turns off MDC and
+ * leaves it in low voltage state. Any non-zero value results in the MDC frequency
+ * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_MII_SPEED field. */
+#define ENET_RD_MSCR_MII_SPEED(base) ((ENET_MSCR_REG(base) & ENET_MSCR_MII_SPEED_MASK) >> ENET_MSCR_MII_SPEED_SHIFT)
+#define ENET_BRD_MSCR_MII_SPEED(base) (ENET_RD_MSCR_MII_SPEED(base))
+
+/*! @brief Set the MII_SPEED field to a new value. */
+#define ENET_WR_MSCR_MII_SPEED(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_MII_SPEED_MASK, ENET_MSCR_MII_SPEED(value)))
+#define ENET_BWR_MSCR_MII_SPEED(base, value) (ENET_WR_MSCR_MII_SPEED(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
+ *
+ * Enables/disables prepending a preamble to the MII management frame. The MII
+ * standard allows the preamble to be dropped if the attached PHY devices do not
+ * require it.
+ *
+ * Values:
+ * - 0b0 - Preamble enabled.
+ * - 0b1 - Preamble (32 ones) is not prepended to the MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_DIS_PRE field. */
+#define ENET_RD_MSCR_DIS_PRE(base) ((ENET_MSCR_REG(base) & ENET_MSCR_DIS_PRE_MASK) >> ENET_MSCR_DIS_PRE_SHIFT)
+#define ENET_BRD_MSCR_DIS_PRE(base) (BITBAND_ACCESS32(&ENET_MSCR_REG(base), ENET_MSCR_DIS_PRE_SHIFT))
+
+/*! @brief Set the DIS_PRE field to a new value. */
+#define ENET_WR_MSCR_DIS_PRE(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_DIS_PRE_MASK, ENET_MSCR_DIS_PRE(value)))
+#define ENET_BWR_MSCR_DIS_PRE(base, value) (BITBAND_ACCESS32(&ENET_MSCR_REG(base), ENET_MSCR_DIS_PRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
+ *
+ * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
+ * output. Depending on the host bus frequency, the setting may need to be
+ * increased.
+ *
+ * Values:
+ * - 0b000 - 1 internal module clock cycle
+ * - 0b001 - 2 internal module clock cycles
+ * - 0b010 - 3 internal module clock cycles
+ * - 0b111 - 8 internal module clock cycles
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_HOLDTIME field. */
+#define ENET_RD_MSCR_HOLDTIME(base) ((ENET_MSCR_REG(base) & ENET_MSCR_HOLDTIME_MASK) >> ENET_MSCR_HOLDTIME_SHIFT)
+#define ENET_BRD_MSCR_HOLDTIME(base) (ENET_RD_MSCR_HOLDTIME(base))
+
+/*! @brief Set the HOLDTIME field to a new value. */
+#define ENET_WR_MSCR_HOLDTIME(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_HOLDTIME_MASK, ENET_MSCR_HOLDTIME(value)))
+#define ENET_BWR_MSCR_HOLDTIME(base, value) (ENET_WR_MSCR_HOLDTIME(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MIBC - MIB Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MIBC - MIB Control Register (RW)
+ *
+ * Reset value: 0xC0000000U
+ *
+ * MIBC is a read/write register controlling and observing the state of the MIB
+ * block. Access this register to disable the MIB block operation or clear the
+ * MIB counters. The MIB_DIS field resets to 1.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MIBC register
+ */
+/*@{*/
+#define ENET_RD_MIBC(base)       (ENET_MIBC_REG(base))
+#define ENET_WR_MIBC(base, value) (ENET_MIBC_REG(base) = (value))
+#define ENET_RMW_MIBC(base, mask, value) (ENET_WR_MIBC(base, (ENET_RD_MIBC(base) & ~(mask)) | (value)))
+#define ENET_SET_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) |  (value)))
+#define ENET_CLR_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) & ~(value)))
+#define ENET_TOG_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MIBC bitfields
+ */
+
+/*!
+ * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
+ *
+ * If set, all statistics counters are reset to 0. This field is not
+ * self-clearing. To clear the MIB counters set and then clear the field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_CLEAR field. */
+#define ENET_RD_MIBC_MIB_CLEAR(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_CLEAR_MASK) >> ENET_MIBC_MIB_CLEAR_SHIFT)
+#define ENET_BRD_MIBC_MIB_CLEAR(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_CLEAR_SHIFT))
+
+/*! @brief Set the MIB_CLEAR field to a new value. */
+#define ENET_WR_MIBC_MIB_CLEAR(base, value) (ENET_RMW_MIBC(base, ENET_MIBC_MIB_CLEAR_MASK, ENET_MIBC_MIB_CLEAR(value)))
+#define ENET_BWR_MIBC_MIB_CLEAR(base, value) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_CLEAR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
+ *
+ * If this status field is set, the MIB block is not currently updating any MIB
+ * counters.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_IDLE field. */
+#define ENET_RD_MIBC_MIB_IDLE(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_IDLE_MASK) >> ENET_MIBC_MIB_IDLE_SHIFT)
+#define ENET_BRD_MIBC_MIB_IDLE(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
+ *
+ * If this control field is set, the MIB logic halts and does not update any MIB
+ * counters.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_DIS field. */
+#define ENET_RD_MIBC_MIB_DIS(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_DIS_MASK) >> ENET_MIBC_MIB_DIS_SHIFT)
+#define ENET_BRD_MIBC_MIB_DIS(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_DIS_SHIFT))
+
+/*! @brief Set the MIB_DIS field to a new value. */
+#define ENET_WR_MIBC_MIB_DIS(base, value) (ENET_RMW_MIBC(base, ENET_MIBC_MIB_DIS_MASK, ENET_MIBC_MIB_DIS(value)))
+#define ENET_BWR_MIBC_MIB_DIS(base, value) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_DIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RCR - Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RCR - Receive Control Register (RW)
+ *
+ * Reset value: 0x05EE0001U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RCR register
+ */
+/*@{*/
+#define ENET_RD_RCR(base)        (ENET_RCR_REG(base))
+#define ENET_WR_RCR(base, value) (ENET_RCR_REG(base) = (value))
+#define ENET_RMW_RCR(base, mask, value) (ENET_WR_RCR(base, (ENET_RD_RCR(base) & ~(mask)) | (value)))
+#define ENET_SET_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) |  (value)))
+#define ENET_CLR_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) & ~(value)))
+#define ENET_TOG_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RCR bitfields
+ */
+
+/*!
+ * @name Register ENET_RCR, field LOOP[0] (RW)
+ *
+ * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
+ * RMII_MODE must be written to 0.
+ *
+ * Values:
+ * - 0b0 - Loopback disabled.
+ * - 0b1 - Transmitted frames are looped back internal to the device and
+ *     transmit MII output signals are not asserted. DRT must be cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_LOOP field. */
+#define ENET_RD_RCR_LOOP(base) ((ENET_RCR_REG(base) & ENET_RCR_LOOP_MASK) >> ENET_RCR_LOOP_SHIFT)
+#define ENET_BRD_RCR_LOOP(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_LOOP_SHIFT))
+
+/*! @brief Set the LOOP field to a new value. */
+#define ENET_WR_RCR_LOOP(base, value) (ENET_RMW_RCR(base, ENET_RCR_LOOP_MASK, ENET_RCR_LOOP(value)))
+#define ENET_BWR_RCR_LOOP(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_LOOP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field DRT[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Receive path operates independently of transmit. Used for full-duplex
+ *     or to monitor transmit activity in half-duplex mode.
+ * - 0b1 - Disable reception of frames while transmitting. Normally used for
+ *     half-duplex mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_DRT field. */
+#define ENET_RD_RCR_DRT(base) ((ENET_RCR_REG(base) & ENET_RCR_DRT_MASK) >> ENET_RCR_DRT_SHIFT)
+#define ENET_BRD_RCR_DRT(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_DRT_SHIFT))
+
+/*! @brief Set the DRT field to a new value. */
+#define ENET_WR_RCR_DRT(base, value) (ENET_RMW_RCR(base, ENET_RCR_DRT_MASK, ENET_RCR_DRT(value)))
+#define ENET_BWR_RCR_DRT(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_DRT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field MII_MODE[2] (RW)
+ *
+ * This field must always be set.
+ *
+ * Values:
+ * - 0b0 - Reserved.
+ * - 0b1 - MII or RMII mode, as indicated by the RMII_MODE field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_MII_MODE field. */
+#define ENET_RD_RCR_MII_MODE(base) ((ENET_RCR_REG(base) & ENET_RCR_MII_MODE_MASK) >> ENET_RCR_MII_MODE_SHIFT)
+#define ENET_BRD_RCR_MII_MODE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_MII_MODE_SHIFT))
+
+/*! @brief Set the MII_MODE field to a new value. */
+#define ENET_WR_RCR_MII_MODE(base, value) (ENET_RMW_RCR(base, ENET_RCR_MII_MODE_MASK, ENET_RCR_MII_MODE(value)))
+#define ENET_BWR_RCR_MII_MODE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_MII_MODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PROM[3] (RW)
+ *
+ * All frames are accepted regardless of address matching.
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PROM field. */
+#define ENET_RD_RCR_PROM(base) ((ENET_RCR_REG(base) & ENET_RCR_PROM_MASK) >> ENET_RCR_PROM_SHIFT)
+#define ENET_BRD_RCR_PROM(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PROM_SHIFT))
+
+/*! @brief Set the PROM field to a new value. */
+#define ENET_WR_RCR_PROM(base, value) (ENET_RMW_RCR(base, ENET_RCR_PROM_MASK, ENET_RCR_PROM(value)))
+#define ENET_BWR_RCR_PROM(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PROM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field BC_REJ[4] (RW)
+ *
+ * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
+ * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
+ * broadcast DA are accepted and the MISS (M) is set in the receive buffer
+ * descriptor.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_BC_REJ field. */
+#define ENET_RD_RCR_BC_REJ(base) ((ENET_RCR_REG(base) & ENET_RCR_BC_REJ_MASK) >> ENET_RCR_BC_REJ_SHIFT)
+#define ENET_BRD_RCR_BC_REJ(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_BC_REJ_SHIFT))
+
+/*! @brief Set the BC_REJ field to a new value. */
+#define ENET_WR_RCR_BC_REJ(base, value) (ENET_RMW_RCR(base, ENET_RCR_BC_REJ_MASK, ENET_RCR_BC_REJ(value)))
+#define ENET_BWR_RCR_BC_REJ(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_BC_REJ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field FCE[5] (RW)
+ *
+ * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
+ * transmitter stops transmitting data frames for a given duration.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_FCE field. */
+#define ENET_RD_RCR_FCE(base) ((ENET_RCR_REG(base) & ENET_RCR_FCE_MASK) >> ENET_RCR_FCE_SHIFT)
+#define ENET_BRD_RCR_FCE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_FCE_SHIFT))
+
+/*! @brief Set the FCE field to a new value. */
+#define ENET_WR_RCR_FCE(base, value) (ENET_RMW_RCR(base, ENET_RCR_FCE_MASK, ENET_RCR_FCE(value)))
+#define ENET_BWR_RCR_FCE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_FCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field RMII_MODE[8] (RW)
+ *
+ * Specifies whether the MAC is configured for MII mode or RMII operation .
+ *
+ * Values:
+ * - 0b0 - MAC configured for MII mode.
+ * - 0b1 - MAC configured for RMII operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_RMII_MODE field. */
+#define ENET_RD_RCR_RMII_MODE(base) ((ENET_RCR_REG(base) & ENET_RCR_RMII_MODE_MASK) >> ENET_RCR_RMII_MODE_SHIFT)
+#define ENET_BRD_RCR_RMII_MODE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_MODE_SHIFT))
+
+/*! @brief Set the RMII_MODE field to a new value. */
+#define ENET_WR_RCR_RMII_MODE(base, value) (ENET_RMW_RCR(base, ENET_RCR_RMII_MODE_MASK, ENET_RCR_RMII_MODE(value)))
+#define ENET_BWR_RCR_RMII_MODE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_MODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field RMII_10T[9] (RW)
+ *
+ * Enables 10-Mbps mode of the RMII .
+ *
+ * Values:
+ * - 0b0 - 100 Mbps operation.
+ * - 0b1 - 10 Mbps operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_RMII_10T field. */
+#define ENET_RD_RCR_RMII_10T(base) ((ENET_RCR_REG(base) & ENET_RCR_RMII_10T_MASK) >> ENET_RCR_RMII_10T_SHIFT)
+#define ENET_BRD_RCR_RMII_10T(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_10T_SHIFT))
+
+/*! @brief Set the RMII_10T field to a new value. */
+#define ENET_WR_RCR_RMII_10T(base, value) (ENET_RMW_RCR(base, ENET_RCR_RMII_10T_MASK, ENET_RCR_RMII_10T(value)))
+#define ENET_BWR_RCR_RMII_10T(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_10T_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PADEN[12] (RW)
+ *
+ * Specifies whether the MAC removes padding from received frames.
+ *
+ * Values:
+ * - 0b0 - No padding is removed on receive by the MAC.
+ * - 0b1 - Padding is removed from received frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PADEN field. */
+#define ENET_RD_RCR_PADEN(base) ((ENET_RCR_REG(base) & ENET_RCR_PADEN_MASK) >> ENET_RCR_PADEN_SHIFT)
+#define ENET_BRD_RCR_PADEN(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PADEN_SHIFT))
+
+/*! @brief Set the PADEN field to a new value. */
+#define ENET_WR_RCR_PADEN(base, value) (ENET_RMW_RCR(base, ENET_RCR_PADEN_MASK, ENET_RCR_PADEN(value)))
+#define ENET_BWR_RCR_PADEN(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PADEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PAUFWD[13] (RW)
+ *
+ * Specifies whether pause frames are terminated or forwarded.
+ *
+ * Values:
+ * - 0b0 - Pause frames are terminated and discarded in the MAC.
+ * - 0b1 - Pause frames are forwarded to the user application.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PAUFWD field. */
+#define ENET_RD_RCR_PAUFWD(base) ((ENET_RCR_REG(base) & ENET_RCR_PAUFWD_MASK) >> ENET_RCR_PAUFWD_SHIFT)
+#define ENET_BRD_RCR_PAUFWD(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PAUFWD_SHIFT))
+
+/*! @brief Set the PAUFWD field to a new value. */
+#define ENET_WR_RCR_PAUFWD(base, value) (ENET_RMW_RCR(base, ENET_RCR_PAUFWD_MASK, ENET_RCR_PAUFWD(value)))
+#define ENET_BWR_RCR_PAUFWD(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PAUFWD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field CRCFWD[14] (RW)
+ *
+ * Specifies whether the CRC field of received frames is transmitted or
+ * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
+ * field is checked and always terminated and removed.
+ *
+ * Values:
+ * - 0b0 - The CRC field of received frames is transmitted to the user
+ *     application.
+ * - 0b1 - The CRC field is stripped from the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_CRCFWD field. */
+#define ENET_RD_RCR_CRCFWD(base) ((ENET_RCR_REG(base) & ENET_RCR_CRCFWD_MASK) >> ENET_RCR_CRCFWD_SHIFT)
+#define ENET_BRD_RCR_CRCFWD(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CRCFWD_SHIFT))
+
+/*! @brief Set the CRCFWD field to a new value. */
+#define ENET_WR_RCR_CRCFWD(base, value) (ENET_RMW_RCR(base, ENET_RCR_CRCFWD_MASK, ENET_RCR_CRCFWD(value)))
+#define ENET_BWR_RCR_CRCFWD(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CRCFWD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field CFEN[15] (RW)
+ *
+ * Enables/disables the MAC control frame.
+ *
+ * Values:
+ * - 0b0 - MAC control frames with any opcode other than 0x0001 (pause frame)
+ *     are accepted and forwarded to the client interface.
+ * - 0b1 - MAC control frames with any opcode other than 0x0001 (pause frame)
+ *     are silently discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_CFEN field. */
+#define ENET_RD_RCR_CFEN(base) ((ENET_RCR_REG(base) & ENET_RCR_CFEN_MASK) >> ENET_RCR_CFEN_SHIFT)
+#define ENET_BRD_RCR_CFEN(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CFEN_SHIFT))
+
+/*! @brief Set the CFEN field to a new value. */
+#define ENET_WR_RCR_CFEN(base, value) (ENET_RMW_RCR(base, ENET_RCR_CFEN_MASK, ENET_RCR_CFEN(value)))
+#define ENET_BWR_RCR_CFEN(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
+ *
+ * Resets to decimal 1518. Length is measured starting at DA and includes the
+ * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
+ * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
+ * to occur and set the LG field in the end of frame receive buffer descriptor.
+ * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
+ * supported.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_MAX_FL field. */
+#define ENET_RD_RCR_MAX_FL(base) ((ENET_RCR_REG(base) & ENET_RCR_MAX_FL_MASK) >> ENET_RCR_MAX_FL_SHIFT)
+#define ENET_BRD_RCR_MAX_FL(base) (ENET_RD_RCR_MAX_FL(base))
+
+/*! @brief Set the MAX_FL field to a new value. */
+#define ENET_WR_RCR_MAX_FL(base, value) (ENET_RMW_RCR(base, ENET_RCR_MAX_FL_MASK, ENET_RCR_MAX_FL(value)))
+#define ENET_BWR_RCR_MAX_FL(base, value) (ENET_WR_RCR_MAX_FL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field NLC[30] (RW)
+ *
+ * Enables/disables a payload length check.
+ *
+ * Values:
+ * - 0b0 - The payload length check is disabled.
+ * - 0b1 - The core checks the frame's payload length with the frame length/type
+ *     field. Errors are indicated in the EIR[PLC] field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_NLC field. */
+#define ENET_RD_RCR_NLC(base) ((ENET_RCR_REG(base) & ENET_RCR_NLC_MASK) >> ENET_RCR_NLC_SHIFT)
+#define ENET_BRD_RCR_NLC(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_NLC_SHIFT))
+
+/*! @brief Set the NLC field to a new value. */
+#define ENET_WR_RCR_NLC(base, value) (ENET_RMW_RCR(base, ENET_RCR_NLC_MASK, ENET_RCR_NLC(value)))
+#define ENET_BWR_RCR_NLC(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_NLC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field GRS[31] (RO)
+ *
+ * Read-only status indicating that the MAC receive datapath is stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_GRS field. */
+#define ENET_RD_RCR_GRS(base) ((ENET_RCR_REG(base) & ENET_RCR_GRS_MASK) >> ENET_RCR_GRS_SHIFT)
+#define ENET_BRD_RCR_GRS(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_GRS_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCR - Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCR - Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR is read/write and configures the transmit block. This register is cleared
+ * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCR register
+ */
+/*@{*/
+#define ENET_RD_TCR(base)        (ENET_TCR_REG(base))
+#define ENET_WR_TCR(base, value) (ENET_TCR_REG(base) = (value))
+#define ENET_RMW_TCR(base, mask, value) (ENET_WR_TCR(base, (ENET_RD_TCR(base) & ~(mask)) | (value)))
+#define ENET_SET_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) |  (value)))
+#define ENET_CLR_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) & ~(value)))
+#define ENET_TOG_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TCR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCR, field GTS[0] (RW)
+ *
+ * When this field is set, MAC stops transmission after any frame currently
+ * transmitted is complete and EIR[GRA] is set. If frame transmission is not
+ * currently underway, the GRA interrupt is asserted immediately. After transmission
+ * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
+ * transmitted. If an early collision occurs during transmission when GTS is set,
+ * transmission stops after the collision. The frame is transmitted again after GTS is
+ * cleared. There may be old frames in the transmit FIFO that transmit when GTS
+ * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_GTS field. */
+#define ENET_RD_TCR_GTS(base) ((ENET_TCR_REG(base) & ENET_TCR_GTS_MASK) >> ENET_TCR_GTS_SHIFT)
+#define ENET_BRD_TCR_GTS(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_GTS_SHIFT))
+
+/*! @brief Set the GTS field to a new value. */
+#define ENET_WR_TCR_GTS(base, value) (ENET_RMW_TCR(base, ENET_TCR_GTS_MASK, ENET_TCR_GTS(value)))
+#define ENET_BWR_TCR_GTS(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_GTS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field FDEN[2] (RW)
+ *
+ * If this field is set, frames transmit independent of carrier sense and
+ * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_FDEN field. */
+#define ENET_RD_TCR_FDEN(base) ((ENET_TCR_REG(base) & ENET_TCR_FDEN_MASK) >> ENET_TCR_FDEN_SHIFT)
+#define ENET_BRD_TCR_FDEN(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_FDEN_SHIFT))
+
+/*! @brief Set the FDEN field to a new value. */
+#define ENET_WR_TCR_FDEN(base, value) (ENET_RMW_TCR(base, ENET_TCR_FDEN_MASK, ENET_TCR_FDEN(value)))
+#define ENET_BWR_TCR_FDEN(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_FDEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
+ *
+ * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
+ * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
+ * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
+ * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
+ * the MAC may continue transmitting a MAC control PAUSE frame.
+ *
+ * Values:
+ * - 0b0 - No PAUSE frame transmitted.
+ * - 0b1 - The MAC stops transmission of data frames after the current
+ *     transmission is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_TFC_PAUSE field. */
+#define ENET_RD_TCR_TFC_PAUSE(base) ((ENET_TCR_REG(base) & ENET_TCR_TFC_PAUSE_MASK) >> ENET_TCR_TFC_PAUSE_SHIFT)
+#define ENET_BRD_TCR_TFC_PAUSE(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_TFC_PAUSE_SHIFT))
+
+/*! @brief Set the TFC_PAUSE field to a new value. */
+#define ENET_WR_TCR_TFC_PAUSE(base, value) (ENET_RMW_TCR(base, ENET_TCR_TFC_PAUSE_MASK, ENET_TCR_TFC_PAUSE(value)))
+#define ENET_BWR_TCR_TFC_PAUSE(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_TFC_PAUSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
+ *
+ * This status field is set when a full-duplex flow control pause frame is
+ * received and the transmitter pauses for the duration defined in this pause frame.
+ * This field automatically clears when the pause duration is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_RFC_PAUSE field. */
+#define ENET_RD_TCR_RFC_PAUSE(base) ((ENET_TCR_REG(base) & ENET_TCR_RFC_PAUSE_MASK) >> ENET_TCR_RFC_PAUSE_SHIFT)
+#define ENET_BRD_TCR_RFC_PAUSE(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_RFC_PAUSE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
+ *
+ * If ADDINS is set, indicates the MAC address that overwrites the source MAC
+ * address.
+ *
+ * Values:
+ * - 0b000 - Node MAC address programmed on PADDR1/2 registers.
+ * - 0b100 - Reserved.
+ * - 0b101 - Reserved.
+ * - 0b110 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_ADDSEL field. */
+#define ENET_RD_TCR_ADDSEL(base) ((ENET_TCR_REG(base) & ENET_TCR_ADDSEL_MASK) >> ENET_TCR_ADDSEL_SHIFT)
+#define ENET_BRD_TCR_ADDSEL(base) (ENET_RD_TCR_ADDSEL(base))
+
+/*! @brief Set the ADDSEL field to a new value. */
+#define ENET_WR_TCR_ADDSEL(base, value) (ENET_RMW_TCR(base, ENET_TCR_ADDSEL_MASK, ENET_TCR_ADDSEL(value)))
+#define ENET_BWR_TCR_ADDSEL(base, value) (ENET_WR_TCR_ADDSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field ADDINS[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The source MAC address is not modified by the MAC.
+ * - 0b1 - The MAC overwrites the source MAC address with the programmed MAC
+ *     address according to ADDSEL.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_ADDINS field. */
+#define ENET_RD_TCR_ADDINS(base) ((ENET_TCR_REG(base) & ENET_TCR_ADDINS_MASK) >> ENET_TCR_ADDINS_SHIFT)
+#define ENET_BRD_TCR_ADDINS(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_ADDINS_SHIFT))
+
+/*! @brief Set the ADDINS field to a new value. */
+#define ENET_WR_TCR_ADDINS(base, value) (ENET_RMW_TCR(base, ENET_TCR_ADDINS_MASK, ENET_TCR_ADDINS(value)))
+#define ENET_BWR_TCR_ADDINS(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_ADDINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field CRCFWD[9] (RW)
+ *
+ * Values:
+ * - 0b0 - TxBD[TC] controls whether the frame has a CRC from the application.
+ * - 0b1 - The transmitter does not append any CRC to transmitted frames, as it
+ *     is expecting a frame with CRC from the application.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_CRCFWD field. */
+#define ENET_RD_TCR_CRCFWD(base) ((ENET_TCR_REG(base) & ENET_TCR_CRCFWD_MASK) >> ENET_TCR_CRCFWD_SHIFT)
+#define ENET_BRD_TCR_CRCFWD(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_CRCFWD_SHIFT))
+
+/*! @brief Set the CRCFWD field to a new value. */
+#define ENET_WR_TCR_CRCFWD(base, value) (ENET_RMW_TCR(base, ENET_TCR_CRCFWD_MASK, ENET_TCR_CRCFWD(value)))
+#define ENET_BWR_TCR_CRCFWD(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_CRCFWD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_PALR - Physical Address Lower Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_PALR - Physical Address Lower Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
+ * in the address recognition process to compare with the destination address
+ * (DA) field of receive frames with an individual DA. In addition, this register
+ * is used in bytes 0 through 3 of the six-byte source address field when
+ * transmitting PAUSE frames. This register is not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_PALR register
+ */
+/*@{*/
+#define ENET_RD_PALR(base)       (ENET_PALR_REG(base))
+#define ENET_WR_PALR(base, value) (ENET_PALR_REG(base) = (value))
+#define ENET_RMW_PALR(base, mask, value) (ENET_WR_PALR(base, (ENET_RD_PALR(base) & ~(mask)) | (value)))
+#define ENET_SET_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) |  (value)))
+#define ENET_CLR_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) & ~(value)))
+#define ENET_TOG_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_PAUR - Physical Address Upper Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_PAUR - Physical Address Upper Register (RW)
+ *
+ * Reset value: 0x00008808U
+ *
+ * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
+ * the address recognition process to compare with the destination address (DA)
+ * field of receive frames with an individual DA. In addition, this register is
+ * used in bytes 4 and 5 of the six-byte source address field when transmitting
+ * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
+ * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
+ * you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_PAUR register
+ */
+/*@{*/
+#define ENET_RD_PAUR(base)       (ENET_PAUR_REG(base))
+#define ENET_WR_PAUR(base, value) (ENET_PAUR_REG(base) = (value))
+#define ENET_RMW_PAUR(base, mask, value) (ENET_WR_PAUR(base, (ENET_RD_PAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) |  (value)))
+#define ENET_CLR_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) & ~(value)))
+#define ENET_TOG_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_PAUR bitfields
+ */
+
+/*!
+ * @name Register ENET_PAUR, field TYPE[15:0] (RO)
+ *
+ * These fields have a constant value of 0x8808.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_PAUR_TYPE field. */
+#define ENET_RD_PAUR_TYPE(base) ((ENET_PAUR_REG(base) & ENET_PAUR_TYPE_MASK) >> ENET_PAUR_TYPE_SHIFT)
+#define ENET_BRD_PAUR_TYPE(base) (ENET_RD_PAUR_TYPE(base))
+/*@}*/
+
+/*!
+ * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
+ *
+ * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
+ * for exact match, and the source address field in PAUSE frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_PAUR_PADDR2 field. */
+#define ENET_RD_PAUR_PADDR2(base) ((ENET_PAUR_REG(base) & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT)
+#define ENET_BRD_PAUR_PADDR2(base) (ENET_RD_PAUR_PADDR2(base))
+
+/*! @brief Set the PADDR2 field to a new value. */
+#define ENET_WR_PAUR_PADDR2(base, value) (ENET_RMW_PAUR(base, ENET_PAUR_PADDR2_MASK, ENET_PAUR_PADDR2(value)))
+#define ENET_BWR_PAUR_PADDR2(base, value) (ENET_WR_PAUR_PADDR2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_OPD - Opcode/Pause Duration Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_OPD - Opcode/Pause Duration Register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * OPD is read/write accessible. This register contains the 16-bit opcode and
+ * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
+ * field is a constant value, 0x0001. When another node detects a PAUSE frame,
+ * that node pauses transmission for the duration specified in the pause duration
+ * field. The lower 16 bits of this register are not reset and you must initialize
+ * it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_OPD register
+ */
+/*@{*/
+#define ENET_RD_OPD(base)        (ENET_OPD_REG(base))
+#define ENET_WR_OPD(base, value) (ENET_OPD_REG(base) = (value))
+#define ENET_RMW_OPD(base, mask, value) (ENET_WR_OPD(base, (ENET_RD_OPD(base) & ~(mask)) | (value)))
+#define ENET_SET_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) |  (value)))
+#define ENET_CLR_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) & ~(value)))
+#define ENET_TOG_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_OPD bitfields
+ */
+
+/*!
+ * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
+ *
+ * Pause duration field used in PAUSE frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_OPD_PAUSE_DUR field. */
+#define ENET_RD_OPD_PAUSE_DUR(base) ((ENET_OPD_REG(base) & ENET_OPD_PAUSE_DUR_MASK) >> ENET_OPD_PAUSE_DUR_SHIFT)
+#define ENET_BRD_OPD_PAUSE_DUR(base) (ENET_RD_OPD_PAUSE_DUR(base))
+
+/*! @brief Set the PAUSE_DUR field to a new value. */
+#define ENET_WR_OPD_PAUSE_DUR(base, value) (ENET_RMW_OPD(base, ENET_OPD_PAUSE_DUR_MASK, ENET_OPD_PAUSE_DUR(value)))
+#define ENET_BWR_OPD_PAUSE_DUR(base, value) (ENET_WR_OPD_PAUSE_DUR(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_OPD, field OPCODE[31:16] (RO)
+ *
+ * These fields have a constant value of 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_OPD_OPCODE field. */
+#define ENET_RD_OPD_OPCODE(base) ((ENET_OPD_REG(base) & ENET_OPD_OPCODE_MASK) >> ENET_OPD_OPCODE_SHIFT)
+#define ENET_BRD_OPD_OPCODE(base) (ENET_RD_OPD_OPCODE(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IAUR - Descriptor Individual Upper Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IAUR - Descriptor Individual Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the destination address (DA) field of receive frames with an individual
+ * DA. This register is not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IAUR register
+ */
+/*@{*/
+#define ENET_RD_IAUR(base)       (ENET_IAUR_REG(base))
+#define ENET_WR_IAUR(base, value) (ENET_IAUR_REG(base) = (value))
+#define ENET_RMW_IAUR(base, mask, value) (ENET_WR_IAUR(base, (ENET_RD_IAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) |  (value)))
+#define ENET_CLR_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) & ~(value)))
+#define ENET_TOG_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IALR - Descriptor Individual Lower Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IALR - Descriptor Individual Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IALR contains the lower 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the DA field of receive frames with an individual DA. This register is
+ * not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IALR register
+ */
+/*@{*/
+#define ENET_RD_IALR(base)       (ENET_IALR_REG(base))
+#define ENET_WR_IALR(base, value) (ENET_IALR_REG(base) = (value))
+#define ENET_RMW_IALR(base, mask, value) (ENET_WR_IALR(base, (ENET_RD_IALR(base) & ~(mask)) | (value)))
+#define ENET_SET_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) |  (value)))
+#define ENET_CLR_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) & ~(value)))
+#define ENET_TOG_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_GAUR - Descriptor Group Upper Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_GAUR - Descriptor Group Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+/*!
+ * @name Constants and macros for entire ENET_GAUR register
+ */
+/*@{*/
+#define ENET_RD_GAUR(base)       (ENET_GAUR_REG(base))
+#define ENET_WR_GAUR(base, value) (ENET_GAUR_REG(base) = (value))
+#define ENET_RMW_GAUR(base, mask, value) (ENET_WR_GAUR(base, (ENET_RD_GAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) |  (value)))
+#define ENET_CLR_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) & ~(value)))
+#define ENET_TOG_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_GALR - Descriptor Group Lower Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_GALR - Descriptor Group Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GALR contains the lower 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+/*!
+ * @name Constants and macros for entire ENET_GALR register
+ */
+/*@{*/
+#define ENET_RD_GALR(base)       (ENET_GALR_REG(base))
+#define ENET_WR_GALR(base, value) (ENET_GALR_REG(base) = (value))
+#define ENET_RMW_GALR(base, mask, value) (ENET_WR_GALR(base, (ENET_RD_GALR(base) & ~(mask)) | (value)))
+#define ENET_SET_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) |  (value)))
+#define ENET_CLR_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) & ~(value)))
+#define ENET_TOG_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TFWR - Transmit FIFO Watermark Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TFWR - Transmit FIFO Watermark Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
+ * in the transmit FIFO before transmission of a frame can begin. This allows you
+ * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
+ * latency (TFWR = 11) due to contention for the system bus. Setting the
+ * watermark to a high value minimizes the risk of transmit FIFO underrun due to
+ * contention for the system bus. The byte counts associated with the TFWR field may need
+ * to be modified to match a given system requirement. For example, worst case
+ * bus access latency by the transmit data DMA channel. When the FIFO level
+ * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
+ * transmit control logic starts frame transmission even before the end-of-frame is
+ * available in the FIFO (cut-through operation). If a complete frame has a size
+ * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
+ * to the line. To enable store and forward on the Transmit path, set STR_FWD to
+ * '1'. In this case, the MAC starts to transmit data only when a complete frame
+ * is stored in the Transmit FIFO.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TFWR register
+ */
+/*@{*/
+#define ENET_RD_TFWR(base)       (ENET_TFWR_REG(base))
+#define ENET_WR_TFWR(base, value) (ENET_TFWR_REG(base) = (value))
+#define ENET_RMW_TFWR(base, mask, value) (ENET_WR_TFWR(base, (ENET_RD_TFWR(base) & ~(mask)) | (value)))
+#define ENET_SET_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) |  (value)))
+#define ENET_CLR_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) & ~(value)))
+#define ENET_TOG_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TFWR bitfields
+ */
+
+/*!
+ * @name Register ENET_TFWR, field TFWR[5:0] (RW)
+ *
+ * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
+ * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
+ * begins. If a frame with less than the threshold is written, it is still sent
+ * independently of this threshold setting. The threshold is relevant only if the
+ * frame is larger than the threshold given. This chip may not support the maximum
+ * number of bytes written shown below. See the chip-specific information for the
+ * ENET module for this value.
+ *
+ * Values:
+ * - 0b000000 - 64 bytes written.
+ * - 0b000001 - 64 bytes written.
+ * - 0b000010 - 128 bytes written.
+ * - 0b000011 - 192 bytes written.
+ * - 0b111110 - 3968 bytes written.
+ * - 0b111111 - 4032 bytes written.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TFWR_TFWR field. */
+#define ENET_RD_TFWR_TFWR(base) ((ENET_TFWR_REG(base) & ENET_TFWR_TFWR_MASK) >> ENET_TFWR_TFWR_SHIFT)
+#define ENET_BRD_TFWR_TFWR(base) (ENET_RD_TFWR_TFWR(base))
+
+/*! @brief Set the TFWR field to a new value. */
+#define ENET_WR_TFWR_TFWR(base, value) (ENET_RMW_TFWR(base, ENET_TFWR_TFWR_MASK, ENET_TFWR_TFWR(value)))
+#define ENET_BWR_TFWR_TFWR(base, value) (ENET_WR_TFWR_TFWR(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TFWR, field STRFWD[8] (RW)
+ *
+ * Values:
+ * - 0b0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
+ * - 0b1 - Enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TFWR_STRFWD field. */
+#define ENET_RD_TFWR_STRFWD(base) ((ENET_TFWR_REG(base) & ENET_TFWR_STRFWD_MASK) >> ENET_TFWR_STRFWD_SHIFT)
+#define ENET_BRD_TFWR_STRFWD(base) (BITBAND_ACCESS32(&ENET_TFWR_REG(base), ENET_TFWR_STRFWD_SHIFT))
+
+/*! @brief Set the STRFWD field to a new value. */
+#define ENET_WR_TFWR_STRFWD(base, value) (ENET_RMW_TFWR(base, ENET_TFWR_STRFWD_MASK, ENET_TFWR_STRFWD(value)))
+#define ENET_BWR_TFWR_STRFWD(base, value) (BITBAND_ACCESS32(&ENET_TFWR_REG(base), ENET_TFWR_STRFWD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RDSR - Receive Descriptor Ring Start Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RDSR - Receive Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDSR points to the beginning of the circular receive buffer descriptor queue
+ * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
+ * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
+ * by 16. This register must be initialized prior to operation
+ */
+/*!
+ * @name Constants and macros for entire ENET_RDSR register
+ */
+/*@{*/
+#define ENET_RD_RDSR(base)       (ENET_RDSR_REG(base))
+#define ENET_WR_RDSR(base, value) (ENET_RDSR_REG(base) = (value))
+#define ENET_RMW_RDSR(base, mask, value) (ENET_WR_RDSR(base, (ENET_RD_RDSR(base) & ~(mask)) | (value)))
+#define ENET_SET_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) |  (value)))
+#define ENET_CLR_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) & ~(value)))
+#define ENET_TOG_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the receive buffer descriptor queue.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RDSR_R_DES_START field. */
+#define ENET_RD_RDSR_R_DES_START(base) ((ENET_RDSR_REG(base) & ENET_RDSR_R_DES_START_MASK) >> ENET_RDSR_R_DES_START_SHIFT)
+#define ENET_BRD_RDSR_R_DES_START(base) (ENET_RD_RDSR_R_DES_START(base))
+
+/*! @brief Set the R_DES_START field to a new value. */
+#define ENET_WR_RDSR_R_DES_START(base, value) (ENET_RMW_RDSR(base, ENET_RDSR_R_DES_START_MASK, ENET_RDSR_R_DES_START(value)))
+#define ENET_BWR_RDSR_R_DES_START(base, value) (ENET_WR_RDSR_R_DES_START(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TDSR provides a pointer to the beginning of the circular transmit buffer
+ * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
+ * must be zero); however, it is recommended to be 128-bit aligned, that is,
+ * evenly divisible by 16. This register must be initialized prior to operation.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TDSR register
+ */
+/*@{*/
+#define ENET_RD_TDSR(base)       (ENET_TDSR_REG(base))
+#define ENET_WR_TDSR(base, value) (ENET_TDSR_REG(base) = (value))
+#define ENET_RMW_TDSR(base, mask, value) (ENET_WR_TDSR(base, (ENET_RD_TDSR(base) & ~(mask)) | (value)))
+#define ENET_SET_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) |  (value)))
+#define ENET_CLR_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) & ~(value)))
+#define ENET_TOG_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the transmit buffer descriptor queue.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TDSR_X_DES_START field. */
+#define ENET_RD_TDSR_X_DES_START(base) ((ENET_TDSR_REG(base) & ENET_TDSR_X_DES_START_MASK) >> ENET_TDSR_X_DES_START_SHIFT)
+#define ENET_BRD_TDSR_X_DES_START(base) (ENET_RD_TDSR_X_DES_START(base))
+
+/*! @brief Set the X_DES_START field to a new value. */
+#define ENET_WR_TDSR_X_DES_START(base, value) (ENET_RMW_TDSR(base, ENET_TDSR_X_DES_START_MASK, ENET_TDSR_X_DES_START(value)))
+#define ENET_BWR_TDSR_X_DES_START(base, value) (ENET_WR_TDSR_X_DES_START(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MRBR - Maximum Receive Buffer Size Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MRBR - Maximum Receive Buffer Size Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MRBR is a user-programmable register that dictates the maximum size of
+ * all receive buffers. This value should take into consideration that the receive
+ * CRC is always written into the last receive buffer. To allow one maximum size
+ * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
+ * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
+ * set to zero by the device. To minimize bus usage (descriptor fetches), set
+ * MRBR greater than or equal to 256 bytes. This register must be initialized
+ * before operation.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MRBR register
+ */
+/*@{*/
+#define ENET_RD_MRBR(base)       (ENET_MRBR_REG(base))
+#define ENET_WR_MRBR(base, value) (ENET_MRBR_REG(base) = (value))
+#define ENET_RMW_MRBR(base, mask, value) (ENET_WR_MRBR(base, (ENET_RD_MRBR(base) & ~(mask)) | (value)))
+#define ENET_SET_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) |  (value)))
+#define ENET_CLR_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) & ~(value)))
+#define ENET_TOG_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MRBR bitfields
+ */
+
+/*!
+ * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
+ *
+ * Receive buffer size in bytes.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field. */
+#define ENET_RD_MRBR_R_BUF_SIZE(base) ((ENET_MRBR_REG(base) & ENET_MRBR_R_BUF_SIZE_MASK) >> ENET_MRBR_R_BUF_SIZE_SHIFT)
+#define ENET_BRD_MRBR_R_BUF_SIZE(base) (ENET_RD_MRBR_R_BUF_SIZE(base))
+
+/*! @brief Set the R_BUF_SIZE field to a new value. */
+#define ENET_WR_MRBR_R_BUF_SIZE(base, value) (ENET_RMW_MRBR(base, ENET_MRBR_R_BUF_SIZE_MASK, ENET_MRBR_R_BUF_SIZE(value)))
+#define ENET_BWR_MRBR_R_BUF_SIZE(base, value) (ENET_WR_MRBR_R_BUF_SIZE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RSFL - Receive FIFO Section Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RSFL - Receive FIFO Section Full Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RSFL register
+ */
+/*@{*/
+#define ENET_RD_RSFL(base)       (ENET_RSFL_REG(base))
+#define ENET_WR_RSFL(base, value) (ENET_RSFL_REG(base) = (value))
+#define ENET_RMW_RSFL(base, mask, value) (ENET_WR_RSFL(base, (ENET_RD_RSFL(base) & ~(mask)) | (value)))
+#define ENET_SET_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) |  (value)))
+#define ENET_CLR_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) & ~(value)))
+#define ENET_TOG_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RSFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
+ * this field to enable store and forward on the RX FIFO. When programming a value
+ * greater than 0 (cut-through operation), it must be greater than
+ * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
+ * in the Receive FIFO (cut-through operation).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field. */
+#define ENET_RD_RSFL_RX_SECTION_FULL(base) ((ENET_RSFL_REG(base) & ENET_RSFL_RX_SECTION_FULL_MASK) >> ENET_RSFL_RX_SECTION_FULL_SHIFT)
+#define ENET_BRD_RSFL_RX_SECTION_FULL(base) (ENET_RD_RSFL_RX_SECTION_FULL(base))
+
+/*! @brief Set the RX_SECTION_FULL field to a new value. */
+#define ENET_WR_RSFL_RX_SECTION_FULL(base, value) (ENET_RMW_RSFL(base, ENET_RSFL_RX_SECTION_FULL_MASK, ENET_RSFL_RX_SECTION_FULL(value)))
+#define ENET_BWR_RSFL_RX_SECTION_FULL(base, value) (ENET_WR_RSFL_RX_SECTION_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RSEM - Receive FIFO Section Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RSEM register
+ */
+/*@{*/
+#define ENET_RD_RSEM(base)       (ENET_RSEM_REG(base))
+#define ENET_WR_RSEM(base, value) (ENET_RSEM_REG(base) = (value))
+#define ENET_RMW_RSEM(base, mask, value) (ENET_WR_RSEM(base, (ENET_RD_RSEM(base) & ~(mask)) | (value)))
+#define ENET_SET_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) |  (value)))
+#define ENET_CLR_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) & ~(value)))
+#define ENET_TOG_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
+ * FIFO has reached this level, a pause frame will be issued. A value of 0
+ * disables automatic pause frame generation. When the FIFO level goes below the value
+ * programmed in this field, an XON pause frame is issued to indicate the FIFO
+ * congestion is cleared to the remote Ethernet client. The section-empty
+ * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field. */
+#define ENET_RD_RSEM_RX_SECTION_EMPTY(base) ((ENET_RSEM_REG(base) & ENET_RSEM_RX_SECTION_EMPTY_MASK) >> ENET_RSEM_RX_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_RSEM_RX_SECTION_EMPTY(base) (ENET_RD_RSEM_RX_SECTION_EMPTY(base))
+
+/*! @brief Set the RX_SECTION_EMPTY field to a new value. */
+#define ENET_WR_RSEM_RX_SECTION_EMPTY(base, value) (ENET_RMW_RSEM(base, ENET_RSEM_RX_SECTION_EMPTY_MASK, ENET_RSEM_RX_SECTION_EMPTY(value)))
+#define ENET_BWR_RSEM_RX_SECTION_EMPTY(base, value) (ENET_WR_RSEM_RX_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
+ *
+ * Defines number of frames in the receive FIFO, independent of its size, that
+ * can be accepted. If the limit is reached, reception will continue normally,
+ * however a pause frame will be triggered to indicate a possible congestion to the
+ * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
+ * frame generation
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field. */
+#define ENET_RD_RSEM_STAT_SECTION_EMPTY(base) ((ENET_RSEM_REG(base) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) >> ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_RSEM_STAT_SECTION_EMPTY(base) (ENET_RD_RSEM_STAT_SECTION_EMPTY(base))
+
+/*! @brief Set the STAT_SECTION_EMPTY field to a new value. */
+#define ENET_WR_RSEM_STAT_SECTION_EMPTY(base, value) (ENET_RMW_RSEM(base, ENET_RSEM_STAT_SECTION_EMPTY_MASK, ENET_RSEM_STAT_SECTION_EMPTY(value)))
+#define ENET_BWR_RSEM_STAT_SECTION_EMPTY(base, value) (ENET_WR_RSEM_STAT_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RAEM - Receive FIFO Almost Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RAEM register
+ */
+/*@{*/
+#define ENET_RD_RAEM(base)       (ENET_RAEM_REG(base))
+#define ENET_WR_RAEM(base, value) (ENET_RAEM_REG(base) = (value))
+#define ENET_RMW_RAEM(base, mask, value) (ENET_WR_RAEM(base, (ENET_RD_RAEM(base) & ~(mask)) | (value)))
+#define ENET_SET_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) |  (value)))
+#define ENET_CLR_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) & ~(value)))
+#define ENET_TOG_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field and the end-of-frame has
+ * not been received for the frame yet, the core receive read control stops FIFO
+ * read (and subsequently stops transferring data to the MAC client
+ * application). It continues to deliver the frame, if again more data than the threshold or
+ * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field. */
+#define ENET_RD_RAEM_RX_ALMOST_EMPTY(base) ((ENET_RAEM_REG(base) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) >> ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)
+#define ENET_BRD_RAEM_RX_ALMOST_EMPTY(base) (ENET_RD_RAEM_RX_ALMOST_EMPTY(base))
+
+/*! @brief Set the RX_ALMOST_EMPTY field to a new value. */
+#define ENET_WR_RAEM_RX_ALMOST_EMPTY(base, value) (ENET_RMW_RAEM(base, ENET_RAEM_RX_ALMOST_EMPTY_MASK, ENET_RAEM_RX_ALMOST_EMPTY(value)))
+#define ENET_BWR_RAEM_RX_ALMOST_EMPTY(base, value) (ENET_WR_RAEM_RX_ALMOST_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RAFL - Receive FIFO Almost Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RAFL register
+ */
+/*@{*/
+#define ENET_RD_RAFL(base)       (ENET_RAFL_REG(base))
+#define ENET_WR_RAFL(base, value) (ENET_RAFL_REG(base) = (value))
+#define ENET_RMW_RAFL(base, mask, value) (ENET_WR_RAFL(base, (ENET_RD_RAFL(base) & ~(mask)) | (value)))
+#define ENET_SET_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) |  (value)))
+#define ENET_CLR_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) & ~(value)))
+#define ENET_TOG_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
+ * truncates the received frame to avoid FIFO overflow. The corresponding error
+ * status will be set when the frame is delivered to the application. A minimum
+ * value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field. */
+#define ENET_RD_RAFL_RX_ALMOST_FULL(base) ((ENET_RAFL_REG(base) & ENET_RAFL_RX_ALMOST_FULL_MASK) >> ENET_RAFL_RX_ALMOST_FULL_SHIFT)
+#define ENET_BRD_RAFL_RX_ALMOST_FULL(base) (ENET_RD_RAFL_RX_ALMOST_FULL(base))
+
+/*! @brief Set the RX_ALMOST_FULL field to a new value. */
+#define ENET_WR_RAFL_RX_ALMOST_FULL(base, value) (ENET_RMW_RAFL(base, ENET_RAFL_RX_ALMOST_FULL_MASK, ENET_RAFL_RX_ALMOST_FULL(value)))
+#define ENET_BWR_RAFL_RX_ALMOST_FULL(base, value) (ENET_WR_RAFL_RX_ALMOST_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TSEM - Transmit FIFO Section Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TSEM register
+ */
+/*@{*/
+#define ENET_RD_TSEM(base)       (ENET_TSEM_REG(base))
+#define ENET_WR_TSEM(base, value) (ENET_TSEM_REG(base) = (value))
+#define ENET_RMW_TSEM(base, mask, value) (ENET_WR_TSEM(base, (ENET_RD_TSEM(base) & ~(mask)) | (value)))
+#define ENET_SET_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) |  (value)))
+#define ENET_CLR_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) & ~(value)))
+#define ENET_TOG_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field. */
+#define ENET_RD_TSEM_TX_SECTION_EMPTY(base) ((ENET_TSEM_REG(base) & ENET_TSEM_TX_SECTION_EMPTY_MASK) >> ENET_TSEM_TX_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_TSEM_TX_SECTION_EMPTY(base) (ENET_RD_TSEM_TX_SECTION_EMPTY(base))
+
+/*! @brief Set the TX_SECTION_EMPTY field to a new value. */
+#define ENET_WR_TSEM_TX_SECTION_EMPTY(base, value) (ENET_RMW_TSEM(base, ENET_TSEM_TX_SECTION_EMPTY_MASK, ENET_TSEM_TX_SECTION_EMPTY(value)))
+#define ENET_BWR_TSEM_TX_SECTION_EMPTY(base, value) (ENET_WR_TSEM_TX_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TAEM register
+ */
+/*@{*/
+#define ENET_RD_TAEM(base)       (ENET_TAEM_REG(base))
+#define ENET_WR_TAEM(base, value) (ENET_TAEM_REG(base) = (value))
+#define ENET_RMW_TAEM(base, mask, value) (ENET_WR_TAEM(base, (ENET_RD_TAEM(base) & ~(mask)) | (value)))
+#define ENET_SET_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) |  (value)))
+#define ENET_CLR_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) & ~(value)))
+#define ENET_TOG_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field, and no end-of-frame is
+ * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
+ * stops reading the FIFO and transmits a frame with an MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A minimum value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field. */
+#define ENET_RD_TAEM_TX_ALMOST_EMPTY(base) ((ENET_TAEM_REG(base) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) >> ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)
+#define ENET_BRD_TAEM_TX_ALMOST_EMPTY(base) (ENET_RD_TAEM_TX_ALMOST_EMPTY(base))
+
+/*! @brief Set the TX_ALMOST_EMPTY field to a new value. */
+#define ENET_WR_TAEM_TX_ALMOST_EMPTY(base, value) (ENET_RMW_TAEM(base, ENET_TAEM_TX_ALMOST_EMPTY_MASK, ENET_TAEM_TX_ALMOST_EMPTY(value)))
+#define ENET_BWR_TAEM_TX_ALMOST_EMPTY(base, value) (ENET_WR_TAEM_TX_ALMOST_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TAFL - Transmit FIFO Almost Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000008U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TAFL register
+ */
+/*@{*/
+#define ENET_RD_TAFL(base)       (ENET_TAFL_REG(base))
+#define ENET_WR_TAFL(base, value) (ENET_TAFL_REG(base) = (value))
+#define ENET_RMW_TAFL(base, mask, value) (ENET_WR_TAFL(base, (ENET_RD_TAFL(base) & ~(mask)) | (value)))
+#define ENET_SET_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) |  (value)))
+#define ENET_CLR_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) & ~(value)))
+#define ENET_TOG_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
+ * value of six is required . A recommended value of at least 8 should be set
+ * allowing a latency of two clock cycles to the application. If more latency is
+ * required the value can be increased as necessary (latency = TAFL - 5). When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
+ * application does not react on this signal, the FIFO write control logic, to
+ * avoid FIFO overflow, truncates the current frame and sets the error status. As a
+ * result, the frame will be transmitted with an GMII/MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A FIFO overflow is a fatal error and requires
+ * a global reset on the transmit datapath or at least deassertion of ETHEREN.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field. */
+#define ENET_RD_TAFL_TX_ALMOST_FULL(base) ((ENET_TAFL_REG(base) & ENET_TAFL_TX_ALMOST_FULL_MASK) >> ENET_TAFL_TX_ALMOST_FULL_SHIFT)
+#define ENET_BRD_TAFL_TX_ALMOST_FULL(base) (ENET_RD_TAFL_TX_ALMOST_FULL(base))
+
+/*! @brief Set the TX_ALMOST_FULL field to a new value. */
+#define ENET_WR_TAFL_TX_ALMOST_FULL(base, value) (ENET_RMW_TAFL(base, ENET_TAFL_TX_ALMOST_FULL_MASK, ENET_TAFL_TX_ALMOST_FULL(value)))
+#define ENET_BWR_TAFL_TX_ALMOST_FULL(base, value) (ENET_WR_TAFL_TX_ALMOST_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TIPG - Transmit Inter-Packet Gap
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TIPG - Transmit Inter-Packet Gap (RW)
+ *
+ * Reset value: 0x0000000CU
+ */
+/*!
+ * @name Constants and macros for entire ENET_TIPG register
+ */
+/*@{*/
+#define ENET_RD_TIPG(base)       (ENET_TIPG_REG(base))
+#define ENET_WR_TIPG(base, value) (ENET_TIPG_REG(base) = (value))
+#define ENET_RMW_TIPG(base, mask, value) (ENET_WR_TIPG(base, (ENET_RD_TIPG(base) & ~(mask)) | (value)))
+#define ENET_SET_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) |  (value)))
+#define ENET_CLR_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) & ~(value)))
+#define ENET_TOG_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TIPG bitfields
+ */
+
+/*!
+ * @name Register ENET_TIPG, field IPG[4:0] (RW)
+ *
+ * Indicates the IPG, in bytes, between transmitted frames. Valid values range
+ * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
+ * 27, the IPG is 27.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TIPG_IPG field. */
+#define ENET_RD_TIPG_IPG(base) ((ENET_TIPG_REG(base) & ENET_TIPG_IPG_MASK) >> ENET_TIPG_IPG_SHIFT)
+#define ENET_BRD_TIPG_IPG(base) (ENET_RD_TIPG_IPG(base))
+
+/*! @brief Set the IPG field to a new value. */
+#define ENET_WR_TIPG_IPG(base, value) (ENET_RMW_TIPG(base, ENET_TIPG_IPG_MASK, ENET_TIPG_IPG(value)))
+#define ENET_BWR_TIPG_IPG(base, value) (ENET_WR_TIPG_IPG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_FTRL - Frame Truncation Length
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_FTRL - Frame Truncation Length (RW)
+ *
+ * Reset value: 0x000007FFU
+ */
+/*!
+ * @name Constants and macros for entire ENET_FTRL register
+ */
+/*@{*/
+#define ENET_RD_FTRL(base)       (ENET_FTRL_REG(base))
+#define ENET_WR_FTRL(base, value) (ENET_FTRL_REG(base) = (value))
+#define ENET_RMW_FTRL(base, mask, value) (ENET_WR_FTRL(base, (ENET_RD_FTRL(base) & ~(mask)) | (value)))
+#define ENET_SET_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) |  (value)))
+#define ENET_CLR_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) & ~(value)))
+#define ENET_TOG_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_FTRL bitfields
+ */
+
+/*!
+ * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
+ *
+ * Indicates the value a receive frame is truncated, if it is greater than this
+ * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
+ * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
+ * less data, guaranteeing that it never receives more than the set limit.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_FTRL_TRUNC_FL field. */
+#define ENET_RD_FTRL_TRUNC_FL(base) ((ENET_FTRL_REG(base) & ENET_FTRL_TRUNC_FL_MASK) >> ENET_FTRL_TRUNC_FL_SHIFT)
+#define ENET_BRD_FTRL_TRUNC_FL(base) (ENET_RD_FTRL_TRUNC_FL(base))
+
+/*! @brief Set the TRUNC_FL field to a new value. */
+#define ENET_WR_FTRL_TRUNC_FL(base, value) (ENET_RMW_FTRL(base, ENET_FTRL_TRUNC_FL_MASK, ENET_FTRL_TRUNC_FL(value)))
+#define ENET_BWR_FTRL_TRUNC_FL(base, value) (ENET_WR_FTRL_TRUNC_FL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TACC - Transmit Accelerator Function Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TACC - Transmit Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TACC controls accelerator actions when sending frames. The register can be
+ * changed before or after each frame, but it must remain unmodified during frame
+ * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
+ * checksum feature.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TACC register
+ */
+/*@{*/
+#define ENET_RD_TACC(base)       (ENET_TACC_REG(base))
+#define ENET_WR_TACC(base, value) (ENET_TACC_REG(base) = (value))
+#define ENET_RMW_TACC(base, mask, value) (ENET_WR_TACC(base, (ENET_RD_TACC(base) & ~(mask)) | (value)))
+#define ENET_SET_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) |  (value)))
+#define ENET_CLR_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) & ~(value)))
+#define ENET_TOG_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TACC bitfields
+ */
+
+/*!
+ * @name Register ENET_TACC, field SHIFT16[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Indicates to the transmit data FIFO that the written frames contain
+ *     two additional octets before the frame data. This means the actual frame
+ *     begins at bit 16 of the first word written into the FIFO. This function
+ *     allows putting the frame payload on a 32-bit boundary in memory, as the
+ *     14-byte Ethernet header is extended to a 16-byte header.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_SHIFT16 field. */
+#define ENET_RD_TACC_SHIFT16(base) ((ENET_TACC_REG(base) & ENET_TACC_SHIFT16_MASK) >> ENET_TACC_SHIFT16_SHIFT)
+#define ENET_BRD_TACC_SHIFT16(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_SHIFT16_SHIFT))
+
+/*! @brief Set the SHIFT16 field to a new value. */
+#define ENET_WR_TACC_SHIFT16(base, value) (ENET_RMW_TACC(base, ENET_TACC_SHIFT16_MASK, ENET_TACC_SHIFT16(value)))
+#define ENET_BWR_TACC_SHIFT16(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_SHIFT16_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TACC, field IPCHK[3] (RW)
+ *
+ * Enables insertion of IP header checksum.
+ *
+ * Values:
+ * - 0b0 - Checksum is not inserted.
+ * - 0b1 - If an IP frame is transmitted, the checksum is inserted
+ *     automatically. The IP header checksum field must be cleared. If a non-IP frame is
+ *     transmitted the frame is not modified.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_IPCHK field. */
+#define ENET_RD_TACC_IPCHK(base) ((ENET_TACC_REG(base) & ENET_TACC_IPCHK_MASK) >> ENET_TACC_IPCHK_SHIFT)
+#define ENET_BRD_TACC_IPCHK(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_IPCHK_SHIFT))
+
+/*! @brief Set the IPCHK field to a new value. */
+#define ENET_WR_TACC_IPCHK(base, value) (ENET_RMW_TACC(base, ENET_TACC_IPCHK_MASK, ENET_TACC_IPCHK(value)))
+#define ENET_BWR_TACC_IPCHK(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_IPCHK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TACC, field PROCHK[4] (RW)
+ *
+ * Enables insertion of protocol checksum.
+ *
+ * Values:
+ * - 0b0 - Checksum not inserted.
+ * - 0b1 - If an IP frame with a known protocol is transmitted, the checksum is
+ *     inserted automatically into the frame. The checksum field must be cleared.
+ *     The other frames are not modified.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_PROCHK field. */
+#define ENET_RD_TACC_PROCHK(base) ((ENET_TACC_REG(base) & ENET_TACC_PROCHK_MASK) >> ENET_TACC_PROCHK_SHIFT)
+#define ENET_BRD_TACC_PROCHK(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_PROCHK_SHIFT))
+
+/*! @brief Set the PROCHK field to a new value. */
+#define ENET_WR_TACC_PROCHK(base, value) (ENET_RMW_TACC(base, ENET_TACC_PROCHK_MASK, ENET_TACC_PROCHK(value)))
+#define ENET_BWR_TACC_PROCHK(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_PROCHK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RACC - Receive Accelerator Function Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RACC - Receive Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RACC register
+ */
+/*@{*/
+#define ENET_RD_RACC(base)       (ENET_RACC_REG(base))
+#define ENET_WR_RACC(base, value) (ENET_RACC_REG(base) = (value))
+#define ENET_RMW_RACC(base, mask, value) (ENET_WR_RACC(base, (ENET_RD_RACC(base) & ~(mask)) | (value)))
+#define ENET_SET_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) |  (value)))
+#define ENET_CLR_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) & ~(value)))
+#define ENET_TOG_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RACC bitfields
+ */
+
+/*!
+ * @name Register ENET_RACC, field PADREM[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Padding not removed.
+ * - 0b1 - Any bytes following the IP payload section of the frame are removed
+ *     from the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_PADREM field. */
+#define ENET_RD_RACC_PADREM(base) ((ENET_RACC_REG(base) & ENET_RACC_PADREM_MASK) >> ENET_RACC_PADREM_SHIFT)
+#define ENET_BRD_RACC_PADREM(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PADREM_SHIFT))
+
+/*! @brief Set the PADREM field to a new value. */
+#define ENET_WR_RACC_PADREM(base, value) (ENET_RMW_RACC(base, ENET_RACC_PADREM_MASK, ENET_RACC_PADREM(value)))
+#define ENET_BWR_RACC_PADREM(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PADREM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field IPDIS[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with wrong IPv4 header checksum are not discarded.
+ * - 0b1 - If an IPv4 frame is received with a mismatching header checksum, the
+ *     frame is discarded. IPv6 has no header checksum and is not affected by
+ *     this setting. Discarding is only available when the RX FIFO operates in store
+ *     and forward mode (RSFL cleared).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_IPDIS field. */
+#define ENET_RD_RACC_IPDIS(base) ((ENET_RACC_REG(base) & ENET_RACC_IPDIS_MASK) >> ENET_RACC_IPDIS_SHIFT)
+#define ENET_BRD_RACC_IPDIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_IPDIS_SHIFT))
+
+/*! @brief Set the IPDIS field to a new value. */
+#define ENET_WR_RACC_IPDIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_IPDIS_MASK, ENET_RACC_IPDIS(value)))
+#define ENET_BWR_RACC_IPDIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_IPDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field PRODIS[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with wrong checksum are not discarded.
+ * - 0b1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong
+ *     TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only
+ *     available when the RX FIFO operates in store and forward mode (RSFL cleared).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_PRODIS field. */
+#define ENET_RD_RACC_PRODIS(base) ((ENET_RACC_REG(base) & ENET_RACC_PRODIS_MASK) >> ENET_RACC_PRODIS_SHIFT)
+#define ENET_BRD_RACC_PRODIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PRODIS_SHIFT))
+
+/*! @brief Set the PRODIS field to a new value. */
+#define ENET_WR_RACC_PRODIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_PRODIS_MASK, ENET_RACC_PRODIS(value)))
+#define ENET_BWR_RACC_PRODIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PRODIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field LINEDIS[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with errors are not discarded.
+ * - 0b1 - Any frame received with a CRC, length, or PHY error is automatically
+ *     discarded and not forwarded to the user application interface.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_LINEDIS field. */
+#define ENET_RD_RACC_LINEDIS(base) ((ENET_RACC_REG(base) & ENET_RACC_LINEDIS_MASK) >> ENET_RACC_LINEDIS_SHIFT)
+#define ENET_BRD_RACC_LINEDIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_LINEDIS_SHIFT))
+
+/*! @brief Set the LINEDIS field to a new value. */
+#define ENET_WR_RACC_LINEDIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_LINEDIS_MASK, ENET_RACC_LINEDIS(value)))
+#define ENET_BWR_RACC_LINEDIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_LINEDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field SHIFT16[7] (RW)
+ *
+ * When this field is set, the actual frame data starts at bit 16 of the first
+ * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
+ * This function only affects the FIFO storage and has no influence on the
+ * statistics, which use the actual length of the frame received.
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Instructs the MAC to write two additional bytes in front of each
+ *     frame received into the RX FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_SHIFT16 field. */
+#define ENET_RD_RACC_SHIFT16(base) ((ENET_RACC_REG(base) & ENET_RACC_SHIFT16_MASK) >> ENET_RACC_SHIFT16_SHIFT)
+#define ENET_BRD_RACC_SHIFT16(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_SHIFT16_SHIFT))
+
+/*! @brief Set the SHIFT16 field to a new value. */
+#define ENET_WR_RACC_SHIFT16(base, value) (ENET_RMW_RACC(base, ENET_RACC_SHIFT16_MASK, ENET_RACC_SHIFT16(value)))
+#define ENET_BWR_RACC_SHIFT16(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_SHIFT16_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_PACKETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_PACKETS(base) (ENET_RMON_T_PACKETS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field. */
+#define ENET_RD_RMON_T_PACKETS_TXPKTS(base) ((ENET_RMON_T_PACKETS_REG(base) & ENET_RMON_T_PACKETS_TXPKTS_MASK) >> ENET_RMON_T_PACKETS_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_PACKETS_TXPKTS(base) (ENET_RD_RMON_T_PACKETS_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RMON Tx Broadcast Packets
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_BC_PKT(base) (ENET_RMON_T_BC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field. */
+#define ENET_RD_RMON_T_BC_PKT_TXPKTS(base) ((ENET_RMON_T_BC_PKT_REG(base) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) >> ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_BC_PKT_TXPKTS(base) (ENET_RD_RMON_T_BC_PKT_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_MC_PKT(base) (ENET_RMON_T_MC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field. */
+#define ENET_RD_RMON_T_MC_PKT_TXPKTS(base) ((ENET_RMON_T_MC_PKT_REG(base) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) >> ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_MC_PKT_TXPKTS(base) (ENET_RD_RMON_T_MC_PKT_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_CRC_ALIGN(base) (ENET_RMON_T_CRC_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field. */
+#define ENET_RD_RMON_T_CRC_ALIGN_TXPKTS(base) ((ENET_RMON_T_CRC_ALIGN_REG(base) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) >> ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_CRC_ALIGN_TXPKTS(base) (ENET_RD_RMON_T_CRC_ALIGN_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_UNDERSIZE(base) (ENET_RMON_T_UNDERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field. */
+#define ENET_RD_RMON_T_UNDERSIZE_TXPKTS(base) ((ENET_RMON_T_UNDERSIZE_REG(base) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) >> ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_UNDERSIZE_TXPKTS(base) (ENET_RD_RMON_T_UNDERSIZE_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_OVERSIZE(base) (ENET_RMON_T_OVERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field. */
+#define ENET_RD_RMON_T_OVERSIZE_TXPKTS(base) ((ENET_RMON_T_OVERSIZE_REG(base) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) >> ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_OVERSIZE_TXPKTS(base) (ENET_RD_RMON_T_OVERSIZE_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_FRAG register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_FRAG(base) (ENET_RMON_T_FRAG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field. */
+#define ENET_RD_RMON_T_FRAG_TXPKTS(base) ((ENET_RMON_T_FRAG_REG(base) & ENET_RMON_T_FRAG_TXPKTS_MASK) >> ENET_RMON_T_FRAG_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_FRAG_TXPKTS(base) (ENET_RD_RMON_T_FRAG_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_JAB register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_JAB(base) (ENET_RMON_T_JAB_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field. */
+#define ENET_RD_RMON_T_JAB_TXPKTS(base) ((ENET_RMON_T_JAB_REG(base) & ENET_RMON_T_JAB_TXPKTS_MASK) >> ENET_RMON_T_JAB_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_JAB_TXPKTS(base) (ENET_RD_RMON_T_JAB_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_COL register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_COL(base) (ENET_RMON_T_COL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_COL bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field. */
+#define ENET_RD_RMON_T_COL_TXPKTS(base) ((ENET_RMON_T_COL_REG(base) & ENET_RMON_T_COL_TXPKTS_MASK) >> ENET_RMON_T_COL_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_COL_TXPKTS(base) (ENET_RD_RMON_T_COL_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P64 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P64(base) (ENET_RMON_T_P64_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field. */
+#define ENET_RD_RMON_T_P64_TXPKTS(base) ((ENET_RMON_T_P64_REG(base) & ENET_RMON_T_P64_TXPKTS_MASK) >> ENET_RMON_T_P64_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P64_TXPKTS(base) (ENET_RD_RMON_T_P64_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P65TO127(base) (ENET_RMON_T_P65TO127_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field. */
+#define ENET_RD_RMON_T_P65TO127_TXPKTS(base) ((ENET_RMON_T_P65TO127_REG(base) & ENET_RMON_T_P65TO127_TXPKTS_MASK) >> ENET_RMON_T_P65TO127_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P65TO127_TXPKTS(base) (ENET_RD_RMON_T_P65TO127_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P128TO255(base) (ENET_RMON_T_P128TO255_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field. */
+#define ENET_RD_RMON_T_P128TO255_TXPKTS(base) ((ENET_RMON_T_P128TO255_REG(base) & ENET_RMON_T_P128TO255_TXPKTS_MASK) >> ENET_RMON_T_P128TO255_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P128TO255_TXPKTS(base) (ENET_RD_RMON_T_P128TO255_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P256TO511(base) (ENET_RMON_T_P256TO511_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field. */
+#define ENET_RD_RMON_T_P256TO511_TXPKTS(base) ((ENET_RMON_T_P256TO511_REG(base) & ENET_RMON_T_P256TO511_TXPKTS_MASK) >> ENET_RMON_T_P256TO511_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P256TO511_TXPKTS(base) (ENET_RD_RMON_T_P256TO511_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P512TO1023(base) (ENET_RMON_T_P512TO1023_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field. */
+#define ENET_RD_RMON_T_P512TO1023_TXPKTS(base) ((ENET_RMON_T_P512TO1023_REG(base) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) >> ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P512TO1023_TXPKTS(base) (ENET_RD_RMON_T_P512TO1023_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P1024TO2047(base) (ENET_RMON_T_P1024TO2047_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field. */
+#define ENET_RD_RMON_T_P1024TO2047_TXPKTS(base) ((ENET_RMON_T_P1024TO2047_REG(base) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) >> ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P1024TO2047_TXPKTS(base) (ENET_RD_RMON_T_P1024TO2047_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P_GTE2048(base) (ENET_RMON_T_P_GTE2048_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field. */
+#define ENET_RD_RMON_T_P_GTE2048_TXPKTS(base) ((ENET_RMON_T_P_GTE2048_REG(base) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) >> ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P_GTE2048_TXPKTS(base) (ENET_RD_RMON_T_P_GTE2048_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OCTETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_OCTETS(base) (ENET_RMON_T_OCTETS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_FRAME_OK(base) (ENET_IEEE_T_FRAME_OK_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field. */
+#define ENET_RD_IEEE_T_FRAME_OK_COUNT(base) ((ENET_IEEE_T_FRAME_OK_REG(base) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) >> ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_FRAME_OK_COUNT(base) (ENET_RD_IEEE_T_FRAME_OK_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_1COL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_1COL(base) (ENET_IEEE_T_1COL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_1COL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field. */
+#define ENET_RD_IEEE_T_1COL_COUNT(base) ((ENET_IEEE_T_1COL_REG(base) & ENET_IEEE_T_1COL_COUNT_MASK) >> ENET_IEEE_T_1COL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_1COL_COUNT(base) (ENET_RD_IEEE_T_1COL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_MCOL(base) (ENET_IEEE_T_MCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field. */
+#define ENET_RD_IEEE_T_MCOL_COUNT(base) ((ENET_IEEE_T_MCOL_REG(base) & ENET_IEEE_T_MCOL_COUNT_MASK) >> ENET_IEEE_T_MCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_MCOL_COUNT(base) (ENET_RD_IEEE_T_MCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_DEF register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_DEF(base) (ENET_IEEE_T_DEF_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_DEF bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field. */
+#define ENET_RD_IEEE_T_DEF_COUNT(base) ((ENET_IEEE_T_DEF_REG(base) & ENET_IEEE_T_DEF_COUNT_MASK) >> ENET_IEEE_T_DEF_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_DEF_COUNT(base) (ENET_RD_IEEE_T_DEF_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_LCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_LCOL(base) (ENET_IEEE_T_LCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field. */
+#define ENET_RD_IEEE_T_LCOL_COUNT(base) ((ENET_IEEE_T_LCOL_REG(base) & ENET_IEEE_T_LCOL_COUNT_MASK) >> ENET_IEEE_T_LCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_LCOL_COUNT(base) (ENET_RD_IEEE_T_LCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_EXCOL(base) (ENET_IEEE_T_EXCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field. */
+#define ENET_RD_IEEE_T_EXCOL_COUNT(base) ((ENET_IEEE_T_EXCOL_REG(base) & ENET_IEEE_T_EXCOL_COUNT_MASK) >> ENET_IEEE_T_EXCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_EXCOL_COUNT(base) (ENET_RD_IEEE_T_EXCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MACERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_MACERR(base) (ENET_IEEE_T_MACERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field. */
+#define ENET_RD_IEEE_T_MACERR_COUNT(base) ((ENET_IEEE_T_MACERR_REG(base) & ENET_IEEE_T_MACERR_COUNT_MASK) >> ENET_IEEE_T_MACERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_MACERR_COUNT(base) (ENET_RD_IEEE_T_MACERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_CSERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_CSERR(base) (ENET_IEEE_T_CSERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field. */
+#define ENET_RD_IEEE_T_CSERR_COUNT(base) ((ENET_IEEE_T_CSERR_REG(base) & ENET_IEEE_T_CSERR_COUNT_MASK) >> ENET_IEEE_T_CSERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_CSERR_COUNT(base) (ENET_RD_IEEE_T_CSERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_FDXFC(base) (ENET_IEEE_T_FDXFC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field. */
+#define ENET_RD_IEEE_T_FDXFC_COUNT(base) ((ENET_IEEE_T_FDXFC_REG(base) & ENET_IEEE_T_FDXFC_COUNT_MASK) >> ENET_IEEE_T_FDXFC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_FDXFC_COUNT(base) (ENET_RD_IEEE_T_FDXFC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counts total octets (includes header and FCS fields).
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_OCTETS_OK(base) (ENET_IEEE_T_OCTETS_OK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_PACKETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_PACKETS(base) (ENET_RMON_R_PACKETS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field. */
+#define ENET_RD_RMON_R_PACKETS_COUNT(base) ((ENET_RMON_R_PACKETS_REG(base) & ENET_RMON_R_PACKETS_COUNT_MASK) >> ENET_RMON_R_PACKETS_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_PACKETS_COUNT(base) (ENET_RD_RMON_R_PACKETS_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_BC_PKT(base) (ENET_RMON_R_BC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field. */
+#define ENET_RD_RMON_R_BC_PKT_COUNT(base) ((ENET_RMON_R_BC_PKT_REG(base) & ENET_RMON_R_BC_PKT_COUNT_MASK) >> ENET_RMON_R_BC_PKT_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_BC_PKT_COUNT(base) (ENET_RD_RMON_R_BC_PKT_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_MC_PKT(base) (ENET_RMON_R_MC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field. */
+#define ENET_RD_RMON_R_MC_PKT_COUNT(base) ((ENET_RMON_R_MC_PKT_REG(base) & ENET_RMON_R_MC_PKT_COUNT_MASK) >> ENET_RMON_R_MC_PKT_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_MC_PKT_COUNT(base) (ENET_RD_RMON_R_MC_PKT_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_CRC_ALIGN(base) (ENET_RMON_R_CRC_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field. */
+#define ENET_RD_RMON_R_CRC_ALIGN_COUNT(base) ((ENET_RMON_R_CRC_ALIGN_REG(base) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) >> ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_CRC_ALIGN_COUNT(base) (ENET_RD_RMON_R_CRC_ALIGN_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_UNDERSIZE(base) (ENET_RMON_R_UNDERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field. */
+#define ENET_RD_RMON_R_UNDERSIZE_COUNT(base) ((ENET_RMON_R_UNDERSIZE_REG(base) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) >> ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_UNDERSIZE_COUNT(base) (ENET_RD_RMON_R_UNDERSIZE_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_OVERSIZE(base) (ENET_RMON_R_OVERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field. */
+#define ENET_RD_RMON_R_OVERSIZE_COUNT(base) ((ENET_RMON_R_OVERSIZE_REG(base) & ENET_RMON_R_OVERSIZE_COUNT_MASK) >> ENET_RMON_R_OVERSIZE_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_OVERSIZE_COUNT(base) (ENET_RD_RMON_R_OVERSIZE_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_FRAG register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_FRAG(base) (ENET_RMON_R_FRAG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field. */
+#define ENET_RD_RMON_R_FRAG_COUNT(base) ((ENET_RMON_R_FRAG_REG(base) & ENET_RMON_R_FRAG_COUNT_MASK) >> ENET_RMON_R_FRAG_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_FRAG_COUNT(base) (ENET_RD_RMON_R_FRAG_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_JAB register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_JAB(base) (ENET_RMON_R_JAB_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_JAB_COUNT field. */
+#define ENET_RD_RMON_R_JAB_COUNT(base) ((ENET_RMON_R_JAB_REG(base) & ENET_RMON_R_JAB_COUNT_MASK) >> ENET_RMON_R_JAB_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_JAB_COUNT(base) (ENET_RD_RMON_R_JAB_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P64 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P64(base) (ENET_RMON_R_P64_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P64_COUNT field. */
+#define ENET_RD_RMON_R_P64_COUNT(base) ((ENET_RMON_R_P64_REG(base) & ENET_RMON_R_P64_COUNT_MASK) >> ENET_RMON_R_P64_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P64_COUNT(base) (ENET_RD_RMON_R_P64_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P65TO127(base) (ENET_RMON_R_P65TO127_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field. */
+#define ENET_RD_RMON_R_P65TO127_COUNT(base) ((ENET_RMON_R_P65TO127_REG(base) & ENET_RMON_R_P65TO127_COUNT_MASK) >> ENET_RMON_R_P65TO127_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P65TO127_COUNT(base) (ENET_RD_RMON_R_P65TO127_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P128TO255(base) (ENET_RMON_R_P128TO255_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field. */
+#define ENET_RD_RMON_R_P128TO255_COUNT(base) ((ENET_RMON_R_P128TO255_REG(base) & ENET_RMON_R_P128TO255_COUNT_MASK) >> ENET_RMON_R_P128TO255_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P128TO255_COUNT(base) (ENET_RD_RMON_R_P128TO255_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P256TO511(base) (ENET_RMON_R_P256TO511_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field. */
+#define ENET_RD_RMON_R_P256TO511_COUNT(base) ((ENET_RMON_R_P256TO511_REG(base) & ENET_RMON_R_P256TO511_COUNT_MASK) >> ENET_RMON_R_P256TO511_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P256TO511_COUNT(base) (ENET_RD_RMON_R_P256TO511_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P512TO1023(base) (ENET_RMON_R_P512TO1023_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field. */
+#define ENET_RD_RMON_R_P512TO1023_COUNT(base) ((ENET_RMON_R_P512TO1023_REG(base) & ENET_RMON_R_P512TO1023_COUNT_MASK) >> ENET_RMON_R_P512TO1023_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P512TO1023_COUNT(base) (ENET_RD_RMON_R_P512TO1023_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P1024TO2047(base) (ENET_RMON_R_P1024TO2047_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field. */
+#define ENET_RD_RMON_R_P1024TO2047_COUNT(base) ((ENET_RMON_R_P1024TO2047_REG(base) & ENET_RMON_R_P1024TO2047_COUNT_MASK) >> ENET_RMON_R_P1024TO2047_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P1024TO2047_COUNT(base) (ENET_RD_RMON_R_P1024TO2047_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P_GTE2048 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P_GTE2048(base) (ENET_RMON_R_P_GTE2048_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P_GTE2048, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P_GTE2048_COUNT field. */
+#define ENET_RD_RMON_R_P_GTE2048_COUNT(base) ((ENET_RMON_R_P_GTE2048_REG(base) & ENET_RMON_R_P_GTE2048_COUNT_MASK) >> ENET_RMON_R_P_GTE2048_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P_GTE2048_COUNT(base) (ENET_RD_RMON_R_P_GTE2048_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OCTETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_OCTETS(base) (ENET_RMON_R_OCTETS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counter increments if a frame with invalid or missing SFD character is
+ * detected and has been dropped. None of the other counters increments if this counter
+ * increments.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_DROP register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_DROP(base) (ENET_IEEE_R_DROP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_DROP bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field. */
+#define ENET_RD_IEEE_R_DROP_COUNT(base) ((ENET_IEEE_R_DROP_REG(base) & ENET_IEEE_R_DROP_COUNT_MASK) >> ENET_IEEE_R_DROP_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_DROP_COUNT(base) (ENET_RD_IEEE_R_DROP_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_FRAME_OK(base) (ENET_IEEE_R_FRAME_OK_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field. */
+#define ENET_RD_IEEE_R_FRAME_OK_COUNT(base) ((ENET_IEEE_R_FRAME_OK_REG(base) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) >> ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_FRAME_OK_COUNT(base) (ENET_RD_IEEE_R_FRAME_OK_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_CRC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_CRC(base) (ENET_IEEE_R_CRC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_CRC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field. */
+#define ENET_RD_IEEE_R_CRC_COUNT(base) ((ENET_IEEE_R_CRC_REG(base) & ENET_IEEE_R_CRC_COUNT_MASK) >> ENET_IEEE_R_CRC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_CRC_COUNT(base) (ENET_RD_IEEE_R_CRC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_ALIGN(base) (ENET_IEEE_R_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field. */
+#define ENET_RD_IEEE_R_ALIGN_COUNT(base) ((ENET_IEEE_R_ALIGN_REG(base) & ENET_IEEE_R_ALIGN_COUNT_MASK) >> ENET_IEEE_R_ALIGN_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_ALIGN_COUNT(base) (ENET_RD_IEEE_R_ALIGN_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_MACERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_MACERR(base) (ENET_IEEE_R_MACERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field. */
+#define ENET_RD_IEEE_R_MACERR_COUNT(base) ((ENET_IEEE_R_MACERR_REG(base) & ENET_IEEE_R_MACERR_COUNT_MASK) >> ENET_IEEE_R_MACERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_MACERR_COUNT(base) (ENET_RD_IEEE_R_MACERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_FDXFC(base) (ENET_IEEE_R_FDXFC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field. */
+#define ENET_RD_IEEE_R_FDXFC_COUNT(base) ((ENET_IEEE_R_FDXFC_REG(base) & ENET_IEEE_R_FDXFC_COUNT_MASK) >> ENET_IEEE_R_FDXFC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_FDXFC_COUNT(base) (ENET_RD_IEEE_R_FDXFC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_OCTETS_OK(base) (ENET_IEEE_R_OCTETS_OK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATCR - Adjustable Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATCR - Adjustable Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * ATCR command fields can trigger the corresponding events directly. It is not
+ * necessary to preserve any of the configuration fields when a command field is
+ * set in the register, that is, no read-modify-write is required. The fields are
+ * automatically cleared after the command completes.
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATCR register
+ */
+/*@{*/
+#define ENET_RD_ATCR(base)       (ENET_ATCR_REG(base))
+#define ENET_WR_ATCR(base, value) (ENET_ATCR_REG(base) = (value))
+#define ENET_RMW_ATCR(base, mask, value) (ENET_WR_ATCR(base, (ENET_RD_ATCR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) |  (value)))
+#define ENET_CLR_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) & ~(value)))
+#define ENET_TOG_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATCR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCR, field EN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer stops at the current value.
+ * - 0b1 - The timer starts incrementing.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_EN field. */
+#define ENET_RD_ATCR_EN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_EN_MASK) >> ENET_ATCR_EN_SHIFT)
+#define ENET_BRD_ATCR_EN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_EN_SHIFT))
+
+/*! @brief Set the EN field to a new value. */
+#define ENET_WR_ATCR_EN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_EN_MASK, ENET_ATCR_EN(value)))
+#define ENET_BWR_ATCR_EN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field OFFEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - The timer can be reset to zero when the given offset time is reached
+ *     (offset event). The field is cleared when the offset event is reached, so
+ *     no further event occurs until the field is set again. The timer offset
+ *     value must be set before setting this field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_OFFEN field. */
+#define ENET_RD_ATCR_OFFEN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_OFFEN_MASK) >> ENET_ATCR_OFFEN_SHIFT)
+#define ENET_BRD_ATCR_OFFEN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFEN_SHIFT))
+
+/*! @brief Set the OFFEN field to a new value. */
+#define ENET_WR_ATCR_OFFEN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_OFFEN_MASK, ENET_ATCR_OFFEN(value)))
+#define ENET_BWR_ATCR_OFFEN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field OFFRST[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer is not affected and no action occurs, besides clearing
+ *     OFFEN, when the offset is reached.
+ * - 0b1 - If OFFEN is set, the timer resets to zero when the offset setting is
+ *     reached. The offset event does not cause a timer interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_OFFRST field. */
+#define ENET_RD_ATCR_OFFRST(base) ((ENET_ATCR_REG(base) & ENET_ATCR_OFFRST_MASK) >> ENET_ATCR_OFFRST_SHIFT)
+#define ENET_BRD_ATCR_OFFRST(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFRST_SHIFT))
+
+/*! @brief Set the OFFRST field to a new value. */
+#define ENET_WR_ATCR_OFFRST(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_OFFRST_MASK, ENET_ATCR_OFFRST(value)))
+#define ENET_BWR_ATCR_OFFRST(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field PEREN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the
+ *     event signal output is asserted when the timer wraps around according to the
+ *     periodic setting ATPER. The timer period value must be set before setting
+ *     this bit. Not all devices contain the event signal output. See the chip
+ *     configuration details.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_PEREN field. */
+#define ENET_RD_ATCR_PEREN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_PEREN_MASK) >> ENET_ATCR_PEREN_SHIFT)
+#define ENET_BRD_ATCR_PEREN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PEREN_SHIFT))
+
+/*! @brief Set the PEREN field to a new value. */
+#define ENET_WR_ATCR_PEREN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_PEREN_MASK, ENET_ATCR_PEREN(value)))
+#define ENET_BWR_ATCR_PEREN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field PINPER[7] (RW)
+ *
+ * Enables event signal output assertion on period event. Not all devices
+ * contain the event signal output. See the chip configuration details.
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - Enable.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_PINPER field. */
+#define ENET_RD_ATCR_PINPER(base) ((ENET_ATCR_REG(base) & ENET_ATCR_PINPER_MASK) >> ENET_ATCR_PINPER_SHIFT)
+#define ENET_BRD_ATCR_PINPER(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PINPER_SHIFT))
+
+/*! @brief Set the PINPER field to a new value. */
+#define ENET_WR_ATCR_PINPER(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_PINPER_MASK, ENET_ATCR_PINPER(value)))
+#define ENET_BWR_ATCR_PINPER(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PINPER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field RESTART[9] (RW)
+ *
+ * Resets the timer to zero. This has no effect on the counter enable. If the
+ * counter is enabled when this field is set, the timer is reset to zero and starts
+ * counting from there. When set, all other fields are ignored during a write.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_RESTART field. */
+#define ENET_RD_ATCR_RESTART(base) ((ENET_ATCR_REG(base) & ENET_ATCR_RESTART_MASK) >> ENET_ATCR_RESTART_SHIFT)
+#define ENET_BRD_ATCR_RESTART(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_RESTART_SHIFT))
+
+/*! @brief Set the RESTART field to a new value. */
+#define ENET_WR_ATCR_RESTART(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_RESTART_MASK, ENET_ATCR_RESTART(value)))
+#define ENET_BWR_ATCR_RESTART(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_RESTART_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field CAPTURE[11] (RW)
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - The current time is captured and can be read from the ATVR register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_CAPTURE field. */
+#define ENET_RD_ATCR_CAPTURE(base) ((ENET_ATCR_REG(base) & ENET_ATCR_CAPTURE_MASK) >> ENET_ATCR_CAPTURE_SHIFT)
+#define ENET_BRD_ATCR_CAPTURE(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_CAPTURE_SHIFT))
+
+/*! @brief Set the CAPTURE field to a new value. */
+#define ENET_WR_ATCR_CAPTURE(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_CAPTURE_MASK, ENET_ATCR_CAPTURE(value)))
+#define ENET_BWR_ATCR_CAPTURE(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_CAPTURE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field SLAVE[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer is active and all configuration fields in this register are
+ *     relevant.
+ * - 0b1 - The internal timer is disabled and the externally provided timer
+ *     value is used. All other fields, except CAPTURE, in this register have no
+ *     effect. CAPTURE can still be used to capture the current timer value.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_SLAVE field. */
+#define ENET_RD_ATCR_SLAVE(base) ((ENET_ATCR_REG(base) & ENET_ATCR_SLAVE_MASK) >> ENET_ATCR_SLAVE_SHIFT)
+#define ENET_BRD_ATCR_SLAVE(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_SLAVE_SHIFT))
+
+/*! @brief Set the SLAVE field to a new value. */
+#define ENET_WR_ATCR_SLAVE(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_SLAVE_MASK, ENET_ATCR_SLAVE(value)))
+#define ENET_BWR_ATCR_SLAVE(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_SLAVE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATVR - Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATVR - Timer Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATVR register
+ */
+/*@{*/
+#define ENET_RD_ATVR(base)       (ENET_ATVR_REG(base))
+#define ENET_WR_ATVR(base, value) (ENET_ATVR_REG(base) = (value))
+#define ENET_RMW_ATVR(base, mask, value) (ENET_WR_ATVR(base, (ENET_RD_ATVR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) |  (value)))
+#define ENET_CLR_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) & ~(value)))
+#define ENET_TOG_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATOFF - Timer Offset Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATOFF - Timer Offset Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATOFF register
+ */
+/*@{*/
+#define ENET_RD_ATOFF(base)      (ENET_ATOFF_REG(base))
+#define ENET_WR_ATOFF(base, value) (ENET_ATOFF_REG(base) = (value))
+#define ENET_RMW_ATOFF(base, mask, value) (ENET_WR_ATOFF(base, (ENET_RD_ATOFF(base) & ~(mask)) | (value)))
+#define ENET_SET_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) |  (value)))
+#define ENET_CLR_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) & ~(value)))
+#define ENET_TOG_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATPER - Timer Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATPER - Timer Period Register (RW)
+ *
+ * Reset value: 0x3B9ACA00U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATPER register
+ */
+/*@{*/
+#define ENET_RD_ATPER(base)      (ENET_ATPER_REG(base))
+#define ENET_WR_ATPER(base, value) (ENET_ATPER_REG(base) = (value))
+#define ENET_RMW_ATPER(base, mask, value) (ENET_WR_ATPER(base, (ENET_RD_ATPER(base) & ~(mask)) | (value)))
+#define ENET_SET_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) |  (value)))
+#define ENET_CLR_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) & ~(value)))
+#define ENET_TOG_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATCOR - Timer Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATCOR - Timer Correction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATCOR register
+ */
+/*@{*/
+#define ENET_RD_ATCOR(base)      (ENET_ATCOR_REG(base))
+#define ENET_WR_ATCOR(base, value) (ENET_ATCOR_REG(base) = (value))
+#define ENET_RMW_ATCOR(base, mask, value) (ENET_WR_ATCOR(base, (ENET_RD_ATCOR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) |  (value)))
+#define ENET_CLR_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) & ~(value)))
+#define ENET_TOG_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATCOR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCOR, field COR[30:0] (RW)
+ *
+ * Defines after how many timer clock cycles (ts_clk) the correction counter
+ * should be reset and trigger a correction increment on the timer. The amount of
+ * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
+ * counter and no corrections occur. This value is given in clock cycles, not in
+ * nanoseconds as all other values.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCOR_COR field. */
+#define ENET_RD_ATCOR_COR(base) ((ENET_ATCOR_REG(base) & ENET_ATCOR_COR_MASK) >> ENET_ATCOR_COR_SHIFT)
+#define ENET_BRD_ATCOR_COR(base) (ENET_RD_ATCOR_COR(base))
+
+/*! @brief Set the COR field to a new value. */
+#define ENET_WR_ATCOR_COR(base, value) (ENET_RMW_ATCOR(base, ENET_ATCOR_COR_MASK, ENET_ATCOR_COR(value)))
+#define ENET_BWR_ATCOR_COR(base, value) (ENET_WR_ATCOR_COR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATINC - Time-Stamping Clock Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATINC - Time-Stamping Clock Period Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATINC register
+ */
+/*@{*/
+#define ENET_RD_ATINC(base)      (ENET_ATINC_REG(base))
+#define ENET_WR_ATINC(base, value) (ENET_ATINC_REG(base) = (value))
+#define ENET_RMW_ATINC(base, mask, value) (ENET_WR_ATINC(base, (ENET_RD_ATINC(base) & ~(mask)) | (value)))
+#define ENET_SET_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) |  (value)))
+#define ENET_CLR_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) & ~(value)))
+#define ENET_TOG_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATINC bitfields
+ */
+
+/*!
+ * @name Register ENET_ATINC, field INC[6:0] (RW)
+ *
+ * The timer increments by this amount each clock cycle. For example, set to 10
+ * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
+ * that is an integer fraction of the period set in ATPER.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATINC_INC field. */
+#define ENET_RD_ATINC_INC(base) ((ENET_ATINC_REG(base) & ENET_ATINC_INC_MASK) >> ENET_ATINC_INC_SHIFT)
+#define ENET_BRD_ATINC_INC(base) (ENET_RD_ATINC_INC(base))
+
+/*! @brief Set the INC field to a new value. */
+#define ENET_WR_ATINC_INC(base, value) (ENET_RMW_ATINC(base, ENET_ATINC_INC_MASK, ENET_ATINC_INC(value)))
+#define ENET_BWR_ATINC_INC(base, value) (ENET_WR_ATINC_INC(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
+ *
+ * This value is added every time the correction timer expires (every clock
+ * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
+ * than INC speeds up the timer.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATINC_INC_CORR field. */
+#define ENET_RD_ATINC_INC_CORR(base) ((ENET_ATINC_REG(base) & ENET_ATINC_INC_CORR_MASK) >> ENET_ATINC_INC_CORR_SHIFT)
+#define ENET_BRD_ATINC_INC_CORR(base) (ENET_RD_ATINC_INC_CORR(base))
+
+/*! @brief Set the INC_CORR field to a new value. */
+#define ENET_WR_ATINC_INC_CORR(base, value) (ENET_RMW_ATINC(base, ENET_ATINC_INC_CORR_MASK, ENET_ATINC_INC_CORR(value)))
+#define ENET_BWR_ATINC_INC_CORR(base, value) (ENET_WR_ATINC_INC_CORR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATSTMP register
+ */
+/*@{*/
+#define ENET_RD_ATSTMP(base)     (ENET_ATSTMP_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TGSR - Timer Global Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TGSR - Timer Global Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TGSR register
+ */
+/*@{*/
+#define ENET_RD_TGSR(base)       (ENET_TGSR_REG(base))
+#define ENET_WR_TGSR(base, value) (ENET_TGSR_REG(base) = (value))
+#define ENET_RMW_TGSR(base, mask, value) (ENET_WR_TGSR(base, (ENET_RD_TGSR(base) & ~(mask)) | (value)))
+#define ENET_SET_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) |  (value)))
+#define ENET_CLR_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) & ~(value)))
+#define ENET_TOG_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TGSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TGSR, field TF0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 0 is clear
+ * - 0b1 - Timer Flag for Channel 0 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF0 field. */
+#define ENET_RD_TGSR_TF0(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF0_MASK) >> ENET_TGSR_TF0_SHIFT)
+#define ENET_BRD_TGSR_TF0(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF0_SHIFT))
+
+/*! @brief Set the TF0 field to a new value. */
+#define ENET_WR_TGSR_TF0(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF2_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF0(value)))
+#define ENET_BWR_TGSR_TF0(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 1 is clear
+ * - 0b1 - Timer Flag for Channel 1 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF1 field. */
+#define ENET_RD_TGSR_TF1(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF1_MASK) >> ENET_TGSR_TF1_SHIFT)
+#define ENET_BRD_TGSR_TF1(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF1_SHIFT))
+
+/*! @brief Set the TF1 field to a new value. */
+#define ENET_WR_TGSR_TF1(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF1_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF2_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF1(value)))
+#define ENET_BWR_TGSR_TF1(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 2 is clear
+ * - 0b1 - Timer Flag for Channel 2 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF2 field. */
+#define ENET_RD_TGSR_TF2(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF2_MASK) >> ENET_TGSR_TF2_SHIFT)
+#define ENET_BRD_TGSR_TF2(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF2_SHIFT))
+
+/*! @brief Set the TF2 field to a new value. */
+#define ENET_WR_TGSR_TF2(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF2_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF2(value)))
+#define ENET_BWR_TGSR_TF2(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 3 is clear
+ * - 0b1 - Timer Flag for Channel 3 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF3 field. */
+#define ENET_RD_TGSR_TF3(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF3_MASK) >> ENET_TGSR_TF3_SHIFT)
+#define ENET_BRD_TGSR_TF3(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF3_SHIFT))
+
+/*! @brief Set the TF3 field to a new value. */
+#define ENET_WR_TGSR_TF3(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF3_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF2_MASK), ENET_TGSR_TF3(value)))
+#define ENET_BWR_TGSR_TF3(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF3_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCSR - Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCSR - Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCSR register
+ */
+/*@{*/
+#define ENET_RD_TCSR(base, index) (ENET_TCSR_REG(base, index))
+#define ENET_WR_TCSR(base, index, value) (ENET_TCSR_REG(base, index) = (value))
+#define ENET_RMW_TCSR(base, index, mask, value) (ENET_WR_TCSR(base, index, (ENET_RD_TCSR(base, index) & ~(mask)) | (value)))
+#define ENET_SET_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) |  (value)))
+#define ENET_CLR_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) & ~(value)))
+#define ENET_TOG_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TCSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCSR, field TDRE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA request is disabled
+ * - 0b1 - DMA request is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TDRE field. */
+#define ENET_RD_TCSR_TDRE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TDRE_MASK) >> ENET_TCSR_TDRE_SHIFT)
+#define ENET_BRD_TCSR_TDRE(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TDRE_SHIFT))
+
+/*! @brief Set the TDRE field to a new value. */
+#define ENET_WR_TCSR_TDRE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TDRE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TDRE(value)))
+#define ENET_BWR_TCSR_TDRE(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TDRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TMODE[5:2] (RW)
+ *
+ * Updating the Timer Mode field takes a few cycles to register because it is
+ * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
+ * from the 1588 clock domain. When changing Timer Mode, always disable the
+ * channel and read this register to verify the channel is disabled first.
+ *
+ * Values:
+ * - 0b0000 - Timer Channel is disabled.
+ * - 0b0001 - Timer Channel is configured for Input Capture on rising edge
+ * - 0b0010 - Timer Channel is configured for Input Capture on falling edge
+ * - 0b0011 - Timer Channel is configured for Input Capture on both edges
+ * - 0b0100 - Timer Channel is configured for Output Compare - software only
+ * - 0b0101 - Timer Channel is configured for Output Compare - toggle output on
+ *     compare
+ * - 0b0110 - Timer Channel is configured for Output Compare - clear output on
+ *     compare
+ * - 0b0111 - Timer Channel is configured for Output Compare - set output on
+ *     compare
+ * - 0b1000 - Reserved
+ * - 0b1010 - Timer Channel is configured for Output Compare - clear output on
+ *     compare, set output on overflow
+ * - 0b10x1 - Timer Channel is configured for Output Compare - set output on
+ *     compare, clear output on overflow
+ * - 0b1100 - Reserved
+ * - 0b1110 - Timer Channel is configured for Output Compare - pulse output low
+ *     on compare for one 1588 clock cycle
+ * - 0b1111 - Timer Channel is configured for Output Compare - pulse output high
+ *     on compare for one 1588 clock cycle
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TMODE field. */
+#define ENET_RD_TCSR_TMODE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TMODE_MASK) >> ENET_TCSR_TMODE_SHIFT)
+#define ENET_BRD_TCSR_TMODE(base, index) (ENET_RD_TCSR_TMODE(base, index))
+
+/*! @brief Set the TMODE field to a new value. */
+#define ENET_WR_TCSR_TMODE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TMODE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TMODE(value)))
+#define ENET_BWR_TCSR_TMODE(base, index, value) (ENET_WR_TCSR_TMODE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TIE[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled
+ * - 0b1 - Interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TIE field. */
+#define ENET_RD_TCSR_TIE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TIE_MASK) >> ENET_TCSR_TIE_SHIFT)
+#define ENET_BRD_TCSR_TIE(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define ENET_WR_TCSR_TIE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TIE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TIE(value)))
+#define ENET_BWR_TCSR_TIE(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TF[7] (W1C)
+ *
+ * Sets when input capture or output compare occurs. This flag is double
+ * buffered between the module clock and 1588 clock domains. When this field is 1, it
+ * can be cleared to 0 by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - Input Capture or Output Compare has not occurred
+ * - 0b1 - Input Capture or Output Compare has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TF field. */
+#define ENET_RD_TCSR_TF(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TF_MASK) >> ENET_TCSR_TF_SHIFT)
+#define ENET_BRD_TCSR_TF(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TF_SHIFT))
+
+/*! @brief Set the TF field to a new value. */
+#define ENET_WR_TCSR_TF(base, index, value) (ENET_RMW_TCSR(base, index, ENET_TCSR_TF_MASK, ENET_TCSR_TF(value)))
+#define ENET_BWR_TCSR_TF(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCCR - Timer Compare Capture Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCCR - Timer Compare Capture Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCCR register
+ */
+/*@{*/
+#define ENET_RD_TCCR(base, index) (ENET_TCCR_REG(base, index))
+#define ENET_WR_TCCR(base, index, value) (ENET_TCCR_REG(base, index) = (value))
+#define ENET_RMW_TCCR(base, index, mask, value) (ENET_WR_TCCR(base, index, (ENET_RD_TCCR(base, index) & ~(mask)) | (value)))
+#define ENET_SET_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) |  (value)))
+#define ENET_CLR_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) & ~(value)))
+#define ENET_TOG_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 EWM
+ *
+ * External Watchdog Monitor
+ *
+ * Registers defined in this header file:
+ * - EWM_CTRL - Control Register
+ * - EWM_SERV - Service Register
+ * - EWM_CMPL - Compare Low Register
+ * - EWM_CMPH - Compare High Register
+ */
+
+#define EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
+#define EWM_IDX (0U) /*!< Instance number for EWM. */
+
+/*******************************************************************************
+ * EWM_CTRL - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CTRL - Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
+ * written once after a CPU reset. Modifying these bits more than once, generates
+ * a bus transfer error.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CTRL register
+ */
+/*@{*/
+#define EWM_RD_CTRL(base)        (EWM_CTRL_REG(base))
+#define EWM_WR_CTRL(base, value) (EWM_CTRL_REG(base) = (value))
+#define EWM_RMW_CTRL(base, mask, value) (EWM_WR_CTRL(base, (EWM_RD_CTRL(base) & ~(mask)) | (value)))
+#define EWM_SET_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) |  (value)))
+#define EWM_CLR_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) & ~(value)))
+#define EWM_TOG_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual EWM_CTRL bitfields
+ */
+
+/*!
+ * @name Register EWM_CTRL, field EWMEN[0] (RW)
+ *
+ * This bit when set, enables the EWM module. This resets the EWM counter to
+ * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
+ * therefore it cannot be enabled until a reset occurs, due to the write-once
+ * nature of this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_EWMEN field. */
+#define EWM_RD_CTRL_EWMEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_EWMEN_MASK) >> EWM_CTRL_EWMEN_SHIFT)
+#define EWM_BRD_CTRL_EWMEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_EWMEN_SHIFT))
+
+/*! @brief Set the EWMEN field to a new value. */
+#define EWM_WR_CTRL_EWMEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_EWMEN_MASK, EWM_CTRL_EWMEN(value)))
+#define EWM_BWR_CTRL_EWMEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_EWMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field ASSIN[1] (RW)
+ *
+ * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
+ * inverts the assert state to a logic one.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_ASSIN field. */
+#define EWM_RD_CTRL_ASSIN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_ASSIN_MASK) >> EWM_CTRL_ASSIN_SHIFT)
+#define EWM_BRD_CTRL_ASSIN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_ASSIN_SHIFT))
+
+/*! @brief Set the ASSIN field to a new value. */
+#define EWM_WR_CTRL_ASSIN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_ASSIN_MASK, EWM_CTRL_ASSIN(value)))
+#define EWM_BWR_CTRL_ASSIN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_ASSIN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field INEN[2] (RW)
+ *
+ * This bit when set, enables the EWM_in port.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_INEN field. */
+#define EWM_RD_CTRL_INEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_INEN_MASK) >> EWM_CTRL_INEN_SHIFT)
+#define EWM_BRD_CTRL_INEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INEN_SHIFT))
+
+/*! @brief Set the INEN field to a new value. */
+#define EWM_WR_CTRL_INEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_INEN_MASK, EWM_CTRL_INEN(value)))
+#define EWM_BWR_CTRL_INEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field INTEN[3] (RW)
+ *
+ * This bit when set and EWM_out is asserted, an interrupt request is generated.
+ * To de-assert interrupt request, user should clear this bit by writing 0.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_INTEN field. */
+#define EWM_RD_CTRL_INTEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_INTEN_MASK) >> EWM_CTRL_INTEN_SHIFT)
+#define EWM_BRD_CTRL_INTEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INTEN_SHIFT))
+
+/*! @brief Set the INTEN field to a new value. */
+#define EWM_WR_CTRL_INTEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_INTEN_MASK, EWM_CTRL_INTEN(value)))
+#define EWM_BWR_CTRL_INTEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INTEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_SERV - Service Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_SERV - Service Register (WORZ)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERV register provides the interface from the CPU to the EWM module. It
+ * is write-only and reads of this register return zero.
+ */
+/*!
+ * @name Constants and macros for entire EWM_SERV register
+ */
+/*@{*/
+#define EWM_RD_SERV(base)        (EWM_SERV_REG(base))
+#define EWM_WR_SERV(base, value) (EWM_SERV_REG(base) = (value))
+#define EWM_RMW_SERV(base, mask, value) (EWM_WR_SERV(base, (EWM_RD_SERV(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_CMPL - Compare Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CMPL - Compare Low Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CMPL register is reset to zero after a CPU reset. This provides no
+ * minimum time for the CPU to service the EWM counter. This register can be written
+ * only once after a CPU reset. Writing this register more than once generates a
+ * bus transfer error.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CMPL register
+ */
+/*@{*/
+#define EWM_RD_CMPL(base)        (EWM_CMPL_REG(base))
+#define EWM_WR_CMPL(base, value) (EWM_CMPL_REG(base) = (value))
+#define EWM_RMW_CMPL(base, mask, value) (EWM_WR_CMPL(base, (EWM_RD_CMPL(base) & ~(mask)) | (value)))
+#define EWM_SET_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) |  (value)))
+#define EWM_CLR_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) & ~(value)))
+#define EWM_TOG_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_CMPH - Compare High Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CMPH - Compare High Register (RW)
+ *
+ * Reset value: 0xFFU
+ *
+ * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
+ * of 256 clocks time, for the CPU to service the EWM counter. This register can
+ * be written only once after a CPU reset. Writing this register more than once
+ * generates a bus transfer error. The valid values for CMPH are up to 0xFE
+ * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
+ * if EWM counter is greater than CMPH.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CMPH register
+ */
+/*@{*/
+#define EWM_RD_CMPH(base)        (EWM_CMPH_REG(base))
+#define EWM_WR_CMPH(base, value) (EWM_CMPH_REG(base) = (value))
+#define EWM_RMW_CMPH(base, mask, value) (EWM_WR_CMPH(base, (EWM_RD_CMPH(base) & ~(mask)) | (value)))
+#define EWM_SET_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) |  (value)))
+#define EWM_CLR_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) & ~(value)))
+#define EWM_TOG_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FB
+ *
+ * FlexBus external bus interface
+ *
+ * Registers defined in this header file:
+ * - FB_CSAR - Chip Select Address Register
+ * - FB_CSMR - Chip Select Mask Register
+ * - FB_CSCR - Chip Select Control Register
+ * - FB_CSPMCR - Chip Select port Multiplexing Control Register
+ */
+
+#define FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
+#define FB_IDX (0U) /*!< Instance number for FB. */
+
+/*******************************************************************************
+ * FB_CSAR - Chip Select Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSAR - Chip Select Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the associated chip-select's base address.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSAR register
+ */
+/*@{*/
+#define FB_RD_CSAR(base, index)  (FB_CSAR_REG(base, index))
+#define FB_WR_CSAR(base, index, value) (FB_CSAR_REG(base, index) = (value))
+#define FB_RMW_CSAR(base, index, mask, value) (FB_WR_CSAR(base, index, (FB_RD_CSAR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) |  (value)))
+#define FB_CLR_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) & ~(value)))
+#define FB_TOG_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSAR bitfields
+ */
+
+/*!
+ * @name Register FB_CSAR, field BA[31:16] (RW)
+ *
+ * Defines the base address for memory dedicated to the associated chip-select.
+ * BA is compared to bits 31-16 on the internal address bus to determine if the
+ * associated chip-select's memory is being accessed. Because the FlexBus module
+ * is one of the slaves connected to the crossbar switch, it is only accessible
+ * within a certain memory range. See the chip memory map for the applicable
+ * FlexBus "expansion" address range for which the chip-selects can be active. Set the
+ * CSARn and CSMRn registers appropriately before accessing this region.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSAR_BA field. */
+#define FB_RD_CSAR_BA(base, index) ((FB_CSAR_REG(base, index) & FB_CSAR_BA_MASK) >> FB_CSAR_BA_SHIFT)
+#define FB_BRD_CSAR_BA(base, index) (FB_RD_CSAR_BA(base, index))
+
+/*! @brief Set the BA field to a new value. */
+#define FB_WR_CSAR_BA(base, index, value) (FB_RMW_CSAR(base, index, FB_CSAR_BA_MASK, FB_CSAR_BA(value)))
+#define FB_BWR_CSAR_BA(base, index, value) (FB_WR_CSAR_BA(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSMR - Chip Select Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSMR - Chip Select Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the address mask and allowable access types for the associated
+ * chip-select.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSMR register
+ */
+/*@{*/
+#define FB_RD_CSMR(base, index)  (FB_CSMR_REG(base, index))
+#define FB_WR_CSMR(base, index, value) (FB_CSMR_REG(base, index) = (value))
+#define FB_RMW_CSMR(base, index, mask, value) (FB_WR_CSMR(base, index, (FB_RD_CSMR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) |  (value)))
+#define FB_CLR_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) & ~(value)))
+#define FB_TOG_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSMR bitfields
+ */
+
+/*!
+ * @name Register FB_CSMR, field V[0] (RW)
+ *
+ * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
+ * Programmed chip-selects do not assert until the V bit is 1b (except for
+ * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
+ * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
+ * select initialization sequence to allow other chip selects to function as
+ * programmed.
+ *
+ * Values:
+ * - 0b0 - Chip-select is invalid.
+ * - 0b1 - Chip-select is valid.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_V field. */
+#define FB_RD_CSMR_V(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_V_MASK) >> FB_CSMR_V_SHIFT)
+#define FB_BRD_CSMR_V(base, index) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_V_SHIFT))
+
+/*! @brief Set the V field to a new value. */
+#define FB_WR_CSMR_V(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_V_MASK, FB_CSMR_V(value)))
+#define FB_BWR_CSMR_V(base, index, value) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_V_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSMR, field WP[8] (RW)
+ *
+ * Controls write accesses to the address range in the corresponding CSAR.
+ *
+ * Values:
+ * - 0b0 - Write accesses are allowed.
+ * - 0b1 - Write accesses are not allowed. Attempting to write to the range of
+ *     addresses for which the WP bit is set results in a bus error termination of
+ *     the internal cycle and no external cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_WP field. */
+#define FB_RD_CSMR_WP(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_WP_MASK) >> FB_CSMR_WP_SHIFT)
+#define FB_BRD_CSMR_WP(base, index) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_WP_SHIFT))
+
+/*! @brief Set the WP field to a new value. */
+#define FB_WR_CSMR_WP(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_WP_MASK, FB_CSMR_WP(value)))
+#define FB_BWR_CSMR_WP(base, index, value) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_WP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSMR, field BAM[31:16] (RW)
+ *
+ * Defines the associated chip-select's block size by masking address bits.
+ *
+ * Values:
+ * - 0b0000000000000000 - The corresponding address bit in CSAR is used in the
+ *     chip-select decode.
+ * - 0b0000000000000001 - The corresponding address bit in CSAR is a don't care
+ *     in the chip-select decode.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_BAM field. */
+#define FB_RD_CSMR_BAM(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_BAM_MASK) >> FB_CSMR_BAM_SHIFT)
+#define FB_BRD_CSMR_BAM(base, index) (FB_RD_CSMR_BAM(base, index))
+
+/*! @brief Set the BAM field to a new value. */
+#define FB_WR_CSMR_BAM(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_BAM_MASK, FB_CSMR_BAM(value)))
+#define FB_BWR_CSMR_BAM(base, index, value) (FB_WR_CSMR_BAM(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSCR - Chip Select Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSCR - Chip Select Control Register (RW)
+ *
+ * Reset value: 0x003FFC00U
+ *
+ * Controls the auto-acknowledge, address setup and hold times, port size, burst
+ * capability, and number of wait states for the associated chip select. To
+ * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
+ * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
+ * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
+ * particular chip for information on the exact CSCR0 reset value.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSCR register
+ */
+/*@{*/
+#define FB_RD_CSCR(base, index)  (FB_CSCR_REG(base, index))
+#define FB_WR_CSCR(base, index, value) (FB_CSCR_REG(base, index) = (value))
+#define FB_RMW_CSCR(base, index, mask, value) (FB_WR_CSCR(base, index, (FB_RD_CSCR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) |  (value)))
+#define FB_CLR_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) & ~(value)))
+#define FB_TOG_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSCR, field BSTW[3] (RW)
+ *
+ * Specifies whether burst writes are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0b0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst writes. For example, a 32-bit write to an
+ *     8-bit port takes four byte writes.
+ * - 0b1 - Enabled. Enables burst write of data larger than the specified port
+ *     size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to
+ *     8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BSTW field. */
+#define FB_RD_CSCR_BSTW(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BSTW_MASK) >> FB_CSCR_BSTW_SHIFT)
+#define FB_BRD_CSCR_BSTW(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTW_SHIFT))
+
+/*! @brief Set the BSTW field to a new value. */
+#define FB_WR_CSCR_BSTW(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BSTW_MASK, FB_CSCR_BSTW(value)))
+#define FB_BWR_CSCR_BSTW(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BSTR[4] (RW)
+ *
+ * Specifies whether burst reads are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0b0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst reads. For example, a 32-bit read from an
+ *     8-bit port is broken into four 8-bit reads.
+ * - 0b1 - Enabled. Enables data burst reads larger than the specified port
+ *     size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
+ *     ports, and line reads from 8-, 16-, and 32-bit ports.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BSTR field. */
+#define FB_RD_CSCR_BSTR(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BSTR_MASK) >> FB_CSCR_BSTR_SHIFT)
+#define FB_BRD_CSCR_BSTR(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTR_SHIFT))
+
+/*! @brief Set the BSTR field to a new value. */
+#define FB_WR_CSCR_BSTR(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BSTR_MASK, FB_CSCR_BSTR(value)))
+#define FB_BWR_CSCR_BSTR(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BEM[5] (RW)
+ *
+ * Specifies whether the corresponding FB_BE is asserted for read accesses.
+ * Certain memories have byte enables that must be asserted during reads and writes.
+ * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
+ * of byte enable support for these SRAMs.
+ *
+ * Values:
+ * - 0b0 - FB_BE is asserted for data write only.
+ * - 0b1 - FB_BE is asserted for data read and write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BEM field. */
+#define FB_RD_CSCR_BEM(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BEM_MASK) >> FB_CSCR_BEM_SHIFT)
+#define FB_BRD_CSCR_BEM(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BEM_SHIFT))
+
+/*! @brief Set the BEM field to a new value. */
+#define FB_WR_CSCR_BEM(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BEM_MASK, FB_CSCR_BEM(value)))
+#define FB_BWR_CSCR_BEM(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BEM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field PS[7:6] (RW)
+ *
+ * Specifies the data port width of the associated chip-select, and determines
+ * where data is driven during write cycles and where data is sampled during read
+ * cycles.
+ *
+ * Values:
+ * - 0b00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
+ * - 0b01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24]
+ *     when BLS is 0b, or FB_D[7:0] when BLS is 1b.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_PS field. */
+#define FB_RD_CSCR_PS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_PS_MASK) >> FB_CSCR_PS_SHIFT)
+#define FB_BRD_CSCR_PS(base, index) (FB_RD_CSCR_PS(base, index))
+
+/*! @brief Set the PS field to a new value. */
+#define FB_WR_CSCR_PS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_PS_MASK, FB_CSCR_PS(value)))
+#define FB_BWR_CSCR_PS(base, index, value) (FB_WR_CSCR_PS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field AA[8] (RW)
+ *
+ * Asserts the internal transfer acknowledge for accesses specified by the
+ * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
+ * asserts an external FB_TA before the wait-state countdown asserts the
+ * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
+ * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
+ *
+ * Values:
+ * - 0b0 - Disabled. No internal transfer acknowledge is asserted and the cycle
+ *     is terminated externally.
+ * - 0b1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_AA field. */
+#define FB_RD_CSCR_AA(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_AA_MASK) >> FB_CSCR_AA_SHIFT)
+#define FB_BRD_CSCR_AA(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_AA_SHIFT))
+
+/*! @brief Set the AA field to a new value. */
+#define FB_WR_CSCR_AA(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_AA_MASK, FB_CSCR_AA(value)))
+#define FB_BWR_CSCR_AA(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_AA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BLS[9] (RW)
+ *
+ * Specifies if data on FB_AD appears left-aligned or right-aligned during the
+ * data phase of a FlexBus access.
+ *
+ * Values:
+ * - 0b0 - Not shifted. Data is left-aligned on FB_AD.
+ * - 0b1 - Shifted. Data is right-aligned on FB_AD.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BLS field. */
+#define FB_RD_CSCR_BLS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BLS_MASK) >> FB_CSCR_BLS_SHIFT)
+#define FB_BRD_CSCR_BLS(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BLS_SHIFT))
+
+/*! @brief Set the BLS field to a new value. */
+#define FB_WR_CSCR_BLS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BLS_MASK, FB_CSCR_BLS(value)))
+#define FB_BWR_CSCR_BLS(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field WS[15:10] (RW)
+ *
+ * Specifies the number of wait states inserted after FlexBus asserts the
+ * associated chip-select and before an internal transfer acknowledge is generated (WS
+ * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_WS field. */
+#define FB_RD_CSCR_WS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_WS_MASK) >> FB_CSCR_WS_SHIFT)
+#define FB_BRD_CSCR_WS(base, index) (FB_RD_CSCR_WS(base, index))
+
+/*! @brief Set the WS field to a new value. */
+#define FB_WR_CSCR_WS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_WS_MASK, FB_CSCR_WS(value)))
+#define FB_BWR_CSCR_WS(base, index, value) (FB_WR_CSCR_WS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field WRAH[17:16] (RW)
+ *
+ * Controls the address, data, and attribute hold time after the termination of
+ * a write cycle that hits in the associated chip-select's address space. The
+ * hold time applies only at the end of a transfer. Therefore, during a burst
+ * transfer or a transfer to a port size smaller than the transfer size, the hold time
+ * is only added after the last bus cycle.
+ *
+ * Values:
+ * - 0b00 - 1 cycle (default for all but FB_CS0 )
+ * - 0b01 - 2 cycles
+ * - 0b10 - 3 cycles
+ * - 0b11 - 4 cycles (default for FB_CS0 )
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_WRAH field. */
+#define FB_RD_CSCR_WRAH(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_WRAH_MASK) >> FB_CSCR_WRAH_SHIFT)
+#define FB_BRD_CSCR_WRAH(base, index) (FB_RD_CSCR_WRAH(base, index))
+
+/*! @brief Set the WRAH field to a new value. */
+#define FB_WR_CSCR_WRAH(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_WRAH_MASK, FB_CSCR_WRAH(value)))
+#define FB_BWR_CSCR_WRAH(base, index, value) (FB_WR_CSCR_WRAH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field RDAH[19:18] (RW)
+ *
+ * Controls the address and attribute hold time after the termination during a
+ * read cycle that hits in the associated chip-select's address space. The hold
+ * time applies only at the end of a transfer. Therefore, during a burst transfer
+ * or a transfer to a port size smaller than the transfer size, the hold time is
+ * only added after the last bus cycle. The number of cycles the address and
+ * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
+ *
+ * Values:
+ * - 0b00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
+ * - 0b01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
+ * - 0b10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
+ * - 0b11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_RDAH field. */
+#define FB_RD_CSCR_RDAH(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_RDAH_MASK) >> FB_CSCR_RDAH_SHIFT)
+#define FB_BRD_CSCR_RDAH(base, index) (FB_RD_CSCR_RDAH(base, index))
+
+/*! @brief Set the RDAH field to a new value. */
+#define FB_WR_CSCR_RDAH(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_RDAH_MASK, FB_CSCR_RDAH(value)))
+#define FB_BWR_CSCR_RDAH(base, index, value) (FB_WR_CSCR_RDAH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field ASET[21:20] (RW)
+ *
+ * Controls when the chip-select is asserted with respect to assertion of a
+ * valid address and attributes.
+ *
+ * Values:
+ * - 0b00 - Assert FB_CSn on the first rising clock edge after the address is
+ *     asserted (default for all but FB_CS0 ).
+ * - 0b01 - Assert FB_CSn on the second rising clock edge after the address is
+ *     asserted.
+ * - 0b10 - Assert FB_CSn on the third rising clock edge after the address is
+ *     asserted.
+ * - 0b11 - Assert FB_CSn on the fourth rising clock edge after the address is
+ *     asserted (default for FB_CS0 ).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_ASET field. */
+#define FB_RD_CSCR_ASET(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_ASET_MASK) >> FB_CSCR_ASET_SHIFT)
+#define FB_BRD_CSCR_ASET(base, index) (FB_RD_CSCR_ASET(base, index))
+
+/*! @brief Set the ASET field to a new value. */
+#define FB_WR_CSCR_ASET(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_ASET_MASK, FB_CSCR_ASET(value)))
+#define FB_BWR_CSCR_ASET(base, index, value) (FB_WR_CSCR_ASET(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field EXTS[22] (RW)
+ *
+ * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
+ * /FB_ALE is asserted.
+ *
+ * Values:
+ * - 0b0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
+ * - 0b1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive
+ *     clock edge after FB_CSn asserts.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_EXTS field. */
+#define FB_RD_CSCR_EXTS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_EXTS_MASK) >> FB_CSCR_EXTS_SHIFT)
+#define FB_BRD_CSCR_EXTS(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_EXTS_SHIFT))
+
+/*! @brief Set the EXTS field to a new value. */
+#define FB_WR_CSCR_EXTS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_EXTS_MASK, FB_CSCR_EXTS(value)))
+#define FB_BWR_CSCR_EXTS(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_EXTS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field SWSEN[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled. A number of wait states (specified by WS) are inserted
+ *     before an internal transfer acknowledge is generated for all transfers.
+ * - 0b1 - Enabled. A number of wait states (specified by SWS) are inserted
+ *     before an internal transfer acknowledge is generated for burst transfer
+ *     secondary terminations.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_SWSEN field. */
+#define FB_RD_CSCR_SWSEN(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_SWSEN_MASK) >> FB_CSCR_SWSEN_SHIFT)
+#define FB_BRD_CSCR_SWSEN(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_SWSEN_SHIFT))
+
+/*! @brief Set the SWSEN field to a new value. */
+#define FB_WR_CSCR_SWSEN(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_SWSEN_MASK, FB_CSCR_SWSEN(value)))
+#define FB_BWR_CSCR_SWSEN(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_SWSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field SWS[31:26] (RW)
+ *
+ * Used only when the SWSEN bit is 1b. Specifies the number of wait states
+ * inserted before an internal transfer acknowledge is generated for a burst transfer
+ * (except for the first termination, which is controlled by WS).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_SWS field. */
+#define FB_RD_CSCR_SWS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_SWS_MASK) >> FB_CSCR_SWS_SHIFT)
+#define FB_BRD_CSCR_SWS(base, index) (FB_RD_CSCR_SWS(base, index))
+
+/*! @brief Set the SWS field to a new value. */
+#define FB_WR_CSCR_SWS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_SWS_MASK, FB_CSCR_SWS(value)))
+#define FB_BWR_CSCR_SWS(base, index, value) (FB_WR_CSCR_SWS(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSPMCR - Chip Select port Multiplexing Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
+ * do any of the following: Write to a reserved address Write to a reserved
+ * field in this register, or Access this register using a size other than 32 bits.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSPMCR register
+ */
+/*@{*/
+#define FB_RD_CSPMCR(base)       (FB_CSPMCR_REG(base))
+#define FB_WR_CSPMCR(base, value) (FB_CSPMCR_REG(base) = (value))
+#define FB_RMW_CSPMCR(base, mask, value) (FB_WR_CSPMCR(base, (FB_RD_CSPMCR(base) & ~(mask)) | (value)))
+#define FB_SET_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) |  (value)))
+#define FB_CLR_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) & ~(value)))
+#define FB_TOG_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSPMCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
+ *
+ * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
+ * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
+ * bus hangs during a transfer.
+ *
+ * Values:
+ * - 0b0000 - FB_TA
+ * - 0b0001 - FB_CS3 . You must also write 1b to CSCR[AA].
+ * - 0b0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
+#define FB_RD_CSPMCR_GROUP5(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP5_MASK) >> FB_CSPMCR_GROUP5_SHIFT)
+#define FB_BRD_CSPMCR_GROUP5(base) (FB_RD_CSPMCR_GROUP5(base))
+
+/*! @brief Set the GROUP5 field to a new value. */
+#define FB_WR_CSPMCR_GROUP5(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP5_MASK, FB_CSPMCR_GROUP5(value)))
+#define FB_BWR_CSPMCR_GROUP5(base, value) (FB_WR_CSPMCR_GROUP5(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
+ *
+ * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_TBST
+ * - 0b0001 - FB_CS2
+ * - 0b0010 - FB_BE_15_8
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
+#define FB_RD_CSPMCR_GROUP4(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP4_MASK) >> FB_CSPMCR_GROUP4_SHIFT)
+#define FB_BRD_CSPMCR_GROUP4(base) (FB_RD_CSPMCR_GROUP4(base))
+
+/*! @brief Set the GROUP4 field to a new value. */
+#define FB_WR_CSPMCR_GROUP4(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP4_MASK, FB_CSPMCR_GROUP4(value)))
+#define FB_BWR_CSPMCR_GROUP4(base, value) (FB_WR_CSPMCR_GROUP4(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
+ *
+ * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_CS5
+ * - 0b0001 - FB_TSIZ1
+ * - 0b0010 - FB_BE_23_16
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
+#define FB_RD_CSPMCR_GROUP3(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP3_MASK) >> FB_CSPMCR_GROUP3_SHIFT)
+#define FB_BRD_CSPMCR_GROUP3(base) (FB_RD_CSPMCR_GROUP3(base))
+
+/*! @brief Set the GROUP3 field to a new value. */
+#define FB_WR_CSPMCR_GROUP3(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP3_MASK, FB_CSPMCR_GROUP3(value)))
+#define FB_BWR_CSPMCR_GROUP3(base, value) (FB_WR_CSPMCR_GROUP3(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
+ *
+ * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_CS4
+ * - 0b0001 - FB_TSIZ0
+ * - 0b0010 - FB_BE_31_24
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
+#define FB_RD_CSPMCR_GROUP2(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP2_MASK) >> FB_CSPMCR_GROUP2_SHIFT)
+#define FB_BRD_CSPMCR_GROUP2(base) (FB_RD_CSPMCR_GROUP2(base))
+
+/*! @brief Set the GROUP2 field to a new value. */
+#define FB_WR_CSPMCR_GROUP2(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP2_MASK, FB_CSPMCR_GROUP2(value)))
+#define FB_BWR_CSPMCR_GROUP2(base, value) (FB_WR_CSPMCR_GROUP2(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
+ *
+ * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
+ *
+ * Values:
+ * - 0b0000 - FB_ALE
+ * - 0b0001 - FB_CS1
+ * - 0b0010 - FB_TS
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
+#define FB_RD_CSPMCR_GROUP1(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP1_MASK) >> FB_CSPMCR_GROUP1_SHIFT)
+#define FB_BRD_CSPMCR_GROUP1(base) (FB_RD_CSPMCR_GROUP1(base))
+
+/*! @brief Set the GROUP1 field to a new value. */
+#define FB_WR_CSPMCR_GROUP1(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP1_MASK, FB_CSPMCR_GROUP1(value)))
+#define FB_BWR_CSPMCR_GROUP1(base, value) (FB_WR_CSPMCR_GROUP1(base, value))
+/*@}*/
+
+/*
+ * MK64F12 FMC
+ *
+ * Flash Memory Controller
+ *
+ * Registers defined in this header file:
+ * - FMC_PFAPR - Flash Access Protection Register
+ * - FMC_PFB0CR - Flash Bank 0 Control Register
+ * - FMC_PFB1CR - Flash Bank 1 Control Register
+ * - FMC_TAGVDW0S - Cache Tag Storage
+ * - FMC_TAGVDW1S - Cache Tag Storage
+ * - FMC_TAGVDW2S - Cache Tag Storage
+ * - FMC_TAGVDW3S - Cache Tag Storage
+ * - FMC_DATA_U - Cache Data Storage (upper word)
+ * - FMC_DATA_L - Cache Data Storage (lower word)
+ */
+
+#define FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */
+#define FMC_IDX (0U) /*!< Instance number for FMC. */
+
+/*******************************************************************************
+ * FMC_PFAPR - Flash Access Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFAPR - Flash Access Protection Register (RW)
+ *
+ * Reset value: 0x00F8003FU
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFAPR register
+ */
+/*@{*/
+#define FMC_RD_PFAPR(base)       (FMC_PFAPR_REG(base))
+#define FMC_WR_PFAPR(base, value) (FMC_PFAPR_REG(base) = (value))
+#define FMC_RMW_PFAPR(base, mask, value) (FMC_WR_PFAPR(base, (FMC_RD_PFAPR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) |  (value)))
+#define FMC_CLR_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) & ~(value)))
+#define FMC_TOG_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFAPR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M0AP field. */
+#define FMC_RD_PFAPR_M0AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M0AP_MASK) >> FMC_PFAPR_M0AP_SHIFT)
+#define FMC_BRD_PFAPR_M0AP(base) (FMC_RD_PFAPR_M0AP(base))
+
+/*! @brief Set the M0AP field to a new value. */
+#define FMC_WR_PFAPR_M0AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M0AP_MASK, FMC_PFAPR_M0AP(value)))
+#define FMC_BWR_PFAPR_M0AP(base, value) (FMC_WR_PFAPR_M0AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M1AP field. */
+#define FMC_RD_PFAPR_M1AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M1AP_MASK) >> FMC_PFAPR_M1AP_SHIFT)
+#define FMC_BRD_PFAPR_M1AP(base) (FMC_RD_PFAPR_M1AP(base))
+
+/*! @brief Set the M1AP field to a new value. */
+#define FMC_WR_PFAPR_M1AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M1AP_MASK, FMC_PFAPR_M1AP(value)))
+#define FMC_BWR_PFAPR_M1AP(base, value) (FMC_WR_PFAPR_M1AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M2AP field. */
+#define FMC_RD_PFAPR_M2AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M2AP_MASK) >> FMC_PFAPR_M2AP_SHIFT)
+#define FMC_BRD_PFAPR_M2AP(base) (FMC_RD_PFAPR_M2AP(base))
+
+/*! @brief Set the M2AP field to a new value. */
+#define FMC_WR_PFAPR_M2AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M2AP_MASK, FMC_PFAPR_M2AP(value)))
+#define FMC_BWR_PFAPR_M2AP(base, value) (FMC_WR_PFAPR_M2AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M3AP field. */
+#define FMC_RD_PFAPR_M3AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M3AP_MASK) >> FMC_PFAPR_M3AP_SHIFT)
+#define FMC_BRD_PFAPR_M3AP(base) (FMC_RD_PFAPR_M3AP(base))
+
+/*! @brief Set the M3AP field to a new value. */
+#define FMC_WR_PFAPR_M3AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M3AP_MASK, FMC_PFAPR_M3AP(value)))
+#define FMC_BWR_PFAPR_M3AP(base, value) (FMC_WR_PFAPR_M3AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M4AP field. */
+#define FMC_RD_PFAPR_M4AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M4AP_MASK) >> FMC_PFAPR_M4AP_SHIFT)
+#define FMC_BRD_PFAPR_M4AP(base) (FMC_RD_PFAPR_M4AP(base))
+
+/*! @brief Set the M4AP field to a new value. */
+#define FMC_WR_PFAPR_M4AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M4AP_MASK, FMC_PFAPR_M4AP(value)))
+#define FMC_BWR_PFAPR_M4AP(base, value) (FMC_WR_PFAPR_M4AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M5AP field. */
+#define FMC_RD_PFAPR_M5AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M5AP_MASK) >> FMC_PFAPR_M5AP_SHIFT)
+#define FMC_BRD_PFAPR_M5AP(base) (FMC_RD_PFAPR_M5AP(base))
+
+/*! @brief Set the M5AP field to a new value. */
+#define FMC_WR_PFAPR_M5AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M5AP_MASK, FMC_PFAPR_M5AP(value)))
+#define FMC_BWR_PFAPR_M5AP(base, value) (FMC_WR_PFAPR_M5AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M6AP field. */
+#define FMC_RD_PFAPR_M6AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M6AP_MASK) >> FMC_PFAPR_M6AP_SHIFT)
+#define FMC_BRD_PFAPR_M6AP(base) (FMC_RD_PFAPR_M6AP(base))
+
+/*! @brief Set the M6AP field to a new value. */
+#define FMC_WR_PFAPR_M6AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M6AP_MASK, FMC_PFAPR_M6AP(value)))
+#define FMC_BWR_PFAPR_M6AP(base, value) (FMC_WR_PFAPR_M6AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master.
+ * - 0b01 - Only read accesses may be performed by this master.
+ * - 0b10 - Only write accesses may be performed by this master.
+ * - 0b11 - Both read and write accesses may be performed by this master.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M7AP field. */
+#define FMC_RD_PFAPR_M7AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M7AP_MASK) >> FMC_PFAPR_M7AP_SHIFT)
+#define FMC_BRD_PFAPR_M7AP(base) (FMC_RD_PFAPR_M7AP(base))
+
+/*! @brief Set the M7AP field to a new value. */
+#define FMC_WR_PFAPR_M7AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M7AP_MASK, FMC_PFAPR_M7AP(value)))
+#define FMC_BWR_PFAPR_M7AP(base, value) (FMC_WR_PFAPR_M7AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M0PFD[16] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M0PFD field. */
+#define FMC_RD_PFAPR_M0PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M0PFD_MASK) >> FMC_PFAPR_M0PFD_SHIFT)
+#define FMC_BRD_PFAPR_M0PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M0PFD_SHIFT))
+
+/*! @brief Set the M0PFD field to a new value. */
+#define FMC_WR_PFAPR_M0PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M0PFD_MASK, FMC_PFAPR_M0PFD(value)))
+#define FMC_BWR_PFAPR_M0PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M0PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M1PFD[17] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M1PFD field. */
+#define FMC_RD_PFAPR_M1PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M1PFD_MASK) >> FMC_PFAPR_M1PFD_SHIFT)
+#define FMC_BRD_PFAPR_M1PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M1PFD_SHIFT))
+
+/*! @brief Set the M1PFD field to a new value. */
+#define FMC_WR_PFAPR_M1PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M1PFD_MASK, FMC_PFAPR_M1PFD(value)))
+#define FMC_BWR_PFAPR_M1PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M1PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M2PFD[18] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M2PFD field. */
+#define FMC_RD_PFAPR_M2PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M2PFD_MASK) >> FMC_PFAPR_M2PFD_SHIFT)
+#define FMC_BRD_PFAPR_M2PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M2PFD_SHIFT))
+
+/*! @brief Set the M2PFD field to a new value. */
+#define FMC_WR_PFAPR_M2PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M2PFD_MASK, FMC_PFAPR_M2PFD(value)))
+#define FMC_BWR_PFAPR_M2PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M2PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M3PFD[19] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M3PFD field. */
+#define FMC_RD_PFAPR_M3PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M3PFD_MASK) >> FMC_PFAPR_M3PFD_SHIFT)
+#define FMC_BRD_PFAPR_M3PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M3PFD_SHIFT))
+
+/*! @brief Set the M3PFD field to a new value. */
+#define FMC_WR_PFAPR_M3PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M3PFD_MASK, FMC_PFAPR_M3PFD(value)))
+#define FMC_BWR_PFAPR_M3PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M3PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M4PFD[20] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M4PFD field. */
+#define FMC_RD_PFAPR_M4PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M4PFD_MASK) >> FMC_PFAPR_M4PFD_SHIFT)
+#define FMC_BRD_PFAPR_M4PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M4PFD_SHIFT))
+
+/*! @brief Set the M4PFD field to a new value. */
+#define FMC_WR_PFAPR_M4PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M4PFD_MASK, FMC_PFAPR_M4PFD(value)))
+#define FMC_BWR_PFAPR_M4PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M4PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M5PFD[21] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M5PFD field. */
+#define FMC_RD_PFAPR_M5PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M5PFD_MASK) >> FMC_PFAPR_M5PFD_SHIFT)
+#define FMC_BRD_PFAPR_M5PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M5PFD_SHIFT))
+
+/*! @brief Set the M5PFD field to a new value. */
+#define FMC_WR_PFAPR_M5PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M5PFD_MASK, FMC_PFAPR_M5PFD(value)))
+#define FMC_BWR_PFAPR_M5PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M5PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M6PFD[22] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M6PFD field. */
+#define FMC_RD_PFAPR_M6PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M6PFD_MASK) >> FMC_PFAPR_M6PFD_SHIFT)
+#define FMC_BRD_PFAPR_M6PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M6PFD_SHIFT))
+
+/*! @brief Set the M6PFD field to a new value. */
+#define FMC_WR_PFAPR_M6PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M6PFD_MASK, FMC_PFAPR_M6PFD(value)))
+#define FMC_BWR_PFAPR_M6PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M6PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M7PFD[23] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M7PFD field. */
+#define FMC_RD_PFAPR_M7PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M7PFD_MASK) >> FMC_PFAPR_M7PFD_SHIFT)
+#define FMC_BRD_PFAPR_M7PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M7PFD_SHIFT))
+
+/*! @brief Set the M7PFD field to a new value. */
+#define FMC_WR_PFAPR_M7PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M7PFD_MASK, FMC_PFAPR_M7PFD(value)))
+#define FMC_BWR_PFAPR_M7PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M7PFD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_PFB0CR - Flash Bank 0 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFB0CR - Flash Bank 0 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFB0CR register
+ */
+/*@{*/
+#define FMC_RD_PFB0CR(base)      (FMC_PFB0CR_REG(base))
+#define FMC_WR_PFB0CR(base, value) (FMC_PFB0CR_REG(base) = (value))
+#define FMC_RMW_PFB0CR(base, mask, value) (FMC_WR_PFB0CR(base, (FMC_RD_PFB0CR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) |  (value)))
+#define FMC_CLR_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) & ~(value)))
+#define FMC_TOG_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFB0CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry page buffer is enabled in response
+ * to flash read accesses. Its operation is independent from bank 1's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0b0 - Single entry buffer is disabled.
+ * - 0b1 - Single entry buffer is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */
+#define FMC_RD_PFB0CR_B0SEBE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0SEBE_MASK) >> FMC_PFB0CR_B0SEBE_SHIFT)
+#define FMC_BRD_PFB0CR_B0SEBE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0SEBE_SHIFT))
+
+/*! @brief Set the B0SEBE field to a new value. */
+#define FMC_WR_PFB0CR_B0SEBE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0SEBE_MASK, FMC_PFB0CR_B0SEBE(value)))
+#define FMC_BWR_PFB0CR_B0SEBE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0SEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to instruction fetches.
+ * - 0b1 - Enable prefetches in response to instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */
+#define FMC_RD_PFB0CR_B0IPE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0IPE_MASK) >> FMC_PFB0CR_B0IPE_SHIFT)
+#define FMC_BRD_PFB0CR_B0IPE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0IPE_SHIFT))
+
+/*! @brief Set the B0IPE field to a new value. */
+#define FMC_WR_PFB0CR_B0IPE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0IPE_MASK, FMC_PFB0CR_B0IPE(value)))
+#define FMC_BWR_PFB0CR_B0IPE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0IPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to data references.
+ * - 0b1 - Enable prefetches in response to data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */
+#define FMC_RD_PFB0CR_B0DPE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0DPE_MASK) >> FMC_PFB0CR_B0DPE_SHIFT)
+#define FMC_BRD_PFB0CR_B0DPE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DPE_SHIFT))
+
+/*! @brief Set the B0DPE field to a new value. */
+#define FMC_WR_PFB0CR_B0DPE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0DPE_MASK, FMC_PFB0CR_B0DPE(value)))
+#define FMC_BWR_PFB0CR_B0DPE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache instruction fetches.
+ * - 0b1 - Cache instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */
+#define FMC_RD_PFB0CR_B0ICE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0ICE_MASK) >> FMC_PFB0CR_B0ICE_SHIFT)
+#define FMC_BRD_PFB0CR_B0ICE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0ICE_SHIFT))
+
+/*! @brief Set the B0ICE field to a new value. */
+#define FMC_WR_PFB0CR_B0ICE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0ICE_MASK, FMC_PFB0CR_B0ICE(value)))
+#define FMC_BWR_PFB0CR_B0ICE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0ICE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache data references.
+ * - 0b1 - Cache data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */
+#define FMC_RD_PFB0CR_B0DCE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0DCE_MASK) >> FMC_PFB0CR_B0DCE_SHIFT)
+#define FMC_BRD_PFB0CR_B0DCE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DCE_SHIFT))
+
+/*! @brief Set the B0DCE field to a new value. */
+#define FMC_WR_PFB0CR_B0DCE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0DCE_MASK, FMC_PFB0CR_B0DCE(value)))
+#define FMC_BWR_PFB0CR_B0DCE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
+ *
+ * This 3-bit field defines the replacement algorithm for accesses that are
+ * cached.
+ *
+ * Values:
+ * - 0b000 - LRU replacement algorithm per set across all four ways
+ * - 0b001 - Reserved
+ * - 0b010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
+ * - 0b011 - Independent LRU with ways [0-2] for ifetches, [3] for data
+ * - 0b1xx - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_CRC field. */
+#define FMC_RD_PFB0CR_CRC(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_CRC_MASK) >> FMC_PFB0CR_CRC_SHIFT)
+#define FMC_BRD_PFB0CR_CRC(base) (FMC_RD_PFB0CR_CRC(base))
+
+/*! @brief Set the CRC field to a new value. */
+#define FMC_WR_PFB0CR_CRC(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CRC_MASK, FMC_PFB0CR_CRC(value)))
+#define FMC_BWR_PFB0CR_CRC(base, value) (FMC_WR_PFB0CR_CRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 0 memory.
+ *
+ * Values:
+ * - 0b00 - 32 bits
+ * - 0b01 - 64 bits
+ * - 0b10 - 128 bits
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0MW field. */
+#define FMC_RD_PFB0CR_B0MW(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0MW_MASK) >> FMC_PFB0CR_B0MW_SHIFT)
+#define FMC_BRD_PFB0CR_B0MW(base) (FMC_RD_PFB0CR_B0MW(base))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
+ *
+ * This bit determines if the FMC's prefetch speculation buffer and the single
+ * entry page buffer are to be invalidated (cleared). When this bit is written,
+ * the speculation buffer and single entry buffer are immediately cleared. This bit
+ * always reads as zero.
+ *
+ * Values:
+ * - 0b0 - Speculation buffer and single entry buffer are not affected.
+ * - 0b1 - Invalidate (clear) speculation buffer and single entry buffer.
+ */
+/*@{*/
+/*! @brief Set the S_B_INV field to a new value. */
+#define FMC_WR_PFB0CR_S_B_INV(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_S_B_INV_MASK, FMC_PFB0CR_S_B_INV(value)))
+#define FMC_BWR_PFB0CR_S_B_INV(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_S_B_INV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
+ *
+ * These bits determine if the given cache way is to be invalidated (cleared).
+ * When a bit within this field is written, the corresponding cache way is
+ * immediately invalidated: the way's tag, data, and valid contents are cleared. This
+ * field always reads as zero. Cache invalidation takes precedence over locking.
+ * The cache is invalidated by system reset. System software is required to
+ * maintain memory coherency when any segment of the flash memory is programmed or
+ * erased. Accordingly, cache invalidations must occur after a programming or erase
+ * event is completed and before the new memory image is accessed. The bit setting
+ * definitions are for each bit in the field.
+ *
+ * Values:
+ * - 0b0000 - No cache way invalidation for the corresponding cache
+ * - 0b0001 - Invalidate cache way for the corresponding cache: clear the tag,
+ *     data, and vld bits of ways selected
+ */
+/*@{*/
+/*! @brief Set the CINV_WAY field to a new value. */
+#define FMC_WR_PFB0CR_CINV_WAY(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY(value)))
+#define FMC_BWR_PFB0CR_CINV_WAY(base, value) (FMC_WR_PFB0CR_CINV_WAY(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
+ *
+ * These bits determine if the given cache way is locked such that its contents
+ * will not be displaced by future misses. The bit setting definitions are for
+ * each bit in the field.
+ *
+ * Values:
+ * - 0b0000 - Cache way is unlocked and may be displaced
+ * - 0b0001 - Cache way is locked and its contents are not displaced
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */
+#define FMC_RD_PFB0CR_CLCK_WAY(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_CLCK_WAY_MASK) >> FMC_PFB0CR_CLCK_WAY_SHIFT)
+#define FMC_BRD_PFB0CR_CLCK_WAY(base) (FMC_RD_PFB0CR_CLCK_WAY(base))
+
+/*! @brief Set the CLCK_WAY field to a new value. */
+#define FMC_WR_PFB0CR_CLCK_WAY(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CLCK_WAY_MASK, FMC_PFB0CR_CLCK_WAY(value)))
+#define FMC_BWR_PFB0CR_CLCK_WAY(base, value) (FMC_WR_PFB0CR_CLCK_WAY(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 0 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */
+#define FMC_RD_PFB0CR_B0RWSC(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0RWSC_MASK) >> FMC_PFB0CR_B0RWSC_SHIFT)
+#define FMC_BRD_PFB0CR_B0RWSC(base) (FMC_RD_PFB0CR_B0RWSC(base))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_PFB1CR - Flash Bank 1 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFB1CR - Flash Bank 1 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ *
+ * This register has a format similar to that for PFB0CR, except it controls the
+ * operation of flash bank 1, and the "global" cache control fields are empty.
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFB1CR register
+ */
+/*@{*/
+#define FMC_RD_PFB1CR(base)      (FMC_PFB1CR_REG(base))
+#define FMC_WR_PFB1CR(base, value) (FMC_PFB1CR_REG(base) = (value))
+#define FMC_RMW_PFB1CR(base, mask, value) (FMC_WR_PFB1CR(base, (FMC_RD_PFB1CR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) |  (value)))
+#define FMC_CLR_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) & ~(value)))
+#define FMC_TOG_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFB1CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry buffer is enabled in response to
+ * flash read accesses. Its operation is independent from bank 0's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0b0 - Single entry buffer is disabled.
+ * - 0b1 - Single entry buffer is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */
+#define FMC_RD_PFB1CR_B1SEBE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1SEBE_MASK) >> FMC_PFB1CR_B1SEBE_SHIFT)
+#define FMC_BRD_PFB1CR_B1SEBE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1SEBE_SHIFT))
+
+/*! @brief Set the B1SEBE field to a new value. */
+#define FMC_WR_PFB1CR_B1SEBE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1SEBE_MASK, FMC_PFB1CR_B1SEBE(value)))
+#define FMC_BWR_PFB1CR_B1SEBE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1SEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to instruction fetches.
+ * - 0b1 - Enable prefetches in response to instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */
+#define FMC_RD_PFB1CR_B1IPE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1IPE_MASK) >> FMC_PFB1CR_B1IPE_SHIFT)
+#define FMC_BRD_PFB1CR_B1IPE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1IPE_SHIFT))
+
+/*! @brief Set the B1IPE field to a new value. */
+#define FMC_WR_PFB1CR_B1IPE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1IPE_MASK, FMC_PFB1CR_B1IPE(value)))
+#define FMC_BWR_PFB1CR_B1IPE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1IPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to data references.
+ * - 0b1 - Enable prefetches in response to data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */
+#define FMC_RD_PFB1CR_B1DPE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1DPE_MASK) >> FMC_PFB1CR_B1DPE_SHIFT)
+#define FMC_BRD_PFB1CR_B1DPE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DPE_SHIFT))
+
+/*! @brief Set the B1DPE field to a new value. */
+#define FMC_WR_PFB1CR_B1DPE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1DPE_MASK, FMC_PFB1CR_B1DPE(value)))
+#define FMC_BWR_PFB1CR_B1DPE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache instruction fetches.
+ * - 0b1 - Cache instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */
+#define FMC_RD_PFB1CR_B1ICE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1ICE_MASK) >> FMC_PFB1CR_B1ICE_SHIFT)
+#define FMC_BRD_PFB1CR_B1ICE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1ICE_SHIFT))
+
+/*! @brief Set the B1ICE field to a new value. */
+#define FMC_WR_PFB1CR_B1ICE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1ICE_MASK, FMC_PFB1CR_B1ICE(value)))
+#define FMC_BWR_PFB1CR_B1ICE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1ICE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache data references.
+ * - 0b1 - Cache data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */
+#define FMC_RD_PFB1CR_B1DCE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1DCE_MASK) >> FMC_PFB1CR_B1DCE_SHIFT)
+#define FMC_BRD_PFB1CR_B1DCE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DCE_SHIFT))
+
+/*! @brief Set the B1DCE field to a new value. */
+#define FMC_WR_PFB1CR_B1DCE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1DCE_MASK, FMC_PFB1CR_B1DCE(value)))
+#define FMC_BWR_PFB1CR_B1DCE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 1 memory.
+ *
+ * Values:
+ * - 0b00 - 32 bits
+ * - 0b01 - 64 bits
+ * - 0b10 - 128 bits
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1MW field. */
+#define FMC_RD_PFB1CR_B1MW(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1MW_MASK) >> FMC_PFB1CR_B1MW_SHIFT)
+#define FMC_BRD_PFB1CR_B1MW(base) (FMC_RD_PFB1CR_B1MW(base))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 1 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */
+#define FMC_RD_PFB1CR_B1RWSC(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1RWSC_MASK) >> FMC_PFB1CR_B1RWSC_SHIFT)
+#define FMC_BRD_PFB1CR_B1RWSC(base) (FMC_RD_PFB1CR_B1RWSC(base))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW0S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW0S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW0S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW0S(base, index) (FMC_TAGVDW0S_REG(base, index))
+#define FMC_WR_TAGVDW0S(base, index, value) (FMC_TAGVDW0S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW0S(base, index, mask, value) (FMC_WR_TAGVDW0S(base, index, (FMC_RD_TAGVDW0S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW0S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW0S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW0S_valid field. */
+#define FMC_RD_TAGVDW0S_valid(base, index) ((FMC_TAGVDW0S_REG(base, index) & FMC_TAGVDW0S_valid_MASK) >> FMC_TAGVDW0S_valid_SHIFT)
+#define FMC_BRD_TAGVDW0S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW0S_REG(base, index), FMC_TAGVDW0S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW0S_valid(base, index, value) (FMC_RMW_TAGVDW0S(base, index, FMC_TAGVDW0S_valid_MASK, FMC_TAGVDW0S_valid(value)))
+#define FMC_BWR_TAGVDW0S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW0S_REG(base, index), FMC_TAGVDW0S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW0S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW0S_tag field. */
+#define FMC_RD_TAGVDW0S_tag(base, index) ((FMC_TAGVDW0S_REG(base, index) & FMC_TAGVDW0S_tag_MASK) >> FMC_TAGVDW0S_tag_SHIFT)
+#define FMC_BRD_TAGVDW0S_tag(base, index) (FMC_RD_TAGVDW0S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW0S_tag(base, index, value) (FMC_RMW_TAGVDW0S(base, index, FMC_TAGVDW0S_tag_MASK, FMC_TAGVDW0S_tag(value)))
+#define FMC_BWR_TAGVDW0S_tag(base, index, value) (FMC_WR_TAGVDW0S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW1S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW1S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW1S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW1S(base, index) (FMC_TAGVDW1S_REG(base, index))
+#define FMC_WR_TAGVDW1S(base, index, value) (FMC_TAGVDW1S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW1S(base, index, mask, value) (FMC_WR_TAGVDW1S(base, index, (FMC_RD_TAGVDW1S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW1S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW1S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW1S_valid field. */
+#define FMC_RD_TAGVDW1S_valid(base, index) ((FMC_TAGVDW1S_REG(base, index) & FMC_TAGVDW1S_valid_MASK) >> FMC_TAGVDW1S_valid_SHIFT)
+#define FMC_BRD_TAGVDW1S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW1S_REG(base, index), FMC_TAGVDW1S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW1S_valid(base, index, value) (FMC_RMW_TAGVDW1S(base, index, FMC_TAGVDW1S_valid_MASK, FMC_TAGVDW1S_valid(value)))
+#define FMC_BWR_TAGVDW1S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW1S_REG(base, index), FMC_TAGVDW1S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW1S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW1S_tag field. */
+#define FMC_RD_TAGVDW1S_tag(base, index) ((FMC_TAGVDW1S_REG(base, index) & FMC_TAGVDW1S_tag_MASK) >> FMC_TAGVDW1S_tag_SHIFT)
+#define FMC_BRD_TAGVDW1S_tag(base, index) (FMC_RD_TAGVDW1S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW1S_tag(base, index, value) (FMC_RMW_TAGVDW1S(base, index, FMC_TAGVDW1S_tag_MASK, FMC_TAGVDW1S_tag(value)))
+#define FMC_BWR_TAGVDW1S_tag(base, index, value) (FMC_WR_TAGVDW1S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW2S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW2S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW2S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW2S(base, index) (FMC_TAGVDW2S_REG(base, index))
+#define FMC_WR_TAGVDW2S(base, index, value) (FMC_TAGVDW2S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW2S(base, index, mask, value) (FMC_WR_TAGVDW2S(base, index, (FMC_RD_TAGVDW2S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW2S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW2S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW2S_valid field. */
+#define FMC_RD_TAGVDW2S_valid(base, index) ((FMC_TAGVDW2S_REG(base, index) & FMC_TAGVDW2S_valid_MASK) >> FMC_TAGVDW2S_valid_SHIFT)
+#define FMC_BRD_TAGVDW2S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW2S_REG(base, index), FMC_TAGVDW2S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW2S_valid(base, index, value) (FMC_RMW_TAGVDW2S(base, index, FMC_TAGVDW2S_valid_MASK, FMC_TAGVDW2S_valid(value)))
+#define FMC_BWR_TAGVDW2S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW2S_REG(base, index), FMC_TAGVDW2S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW2S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW2S_tag field. */
+#define FMC_RD_TAGVDW2S_tag(base, index) ((FMC_TAGVDW2S_REG(base, index) & FMC_TAGVDW2S_tag_MASK) >> FMC_TAGVDW2S_tag_SHIFT)
+#define FMC_BRD_TAGVDW2S_tag(base, index) (FMC_RD_TAGVDW2S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW2S_tag(base, index, value) (FMC_RMW_TAGVDW2S(base, index, FMC_TAGVDW2S_tag_MASK, FMC_TAGVDW2S_tag(value)))
+#define FMC_BWR_TAGVDW2S_tag(base, index, value) (FMC_WR_TAGVDW2S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW3S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW3S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW3S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW3S(base, index) (FMC_TAGVDW3S_REG(base, index))
+#define FMC_WR_TAGVDW3S(base, index, value) (FMC_TAGVDW3S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW3S(base, index, mask, value) (FMC_WR_TAGVDW3S(base, index, (FMC_RD_TAGVDW3S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW3S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW3S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW3S_valid field. */
+#define FMC_RD_TAGVDW3S_valid(base, index) ((FMC_TAGVDW3S_REG(base, index) & FMC_TAGVDW3S_valid_MASK) >> FMC_TAGVDW3S_valid_SHIFT)
+#define FMC_BRD_TAGVDW3S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW3S_REG(base, index), FMC_TAGVDW3S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW3S_valid(base, index, value) (FMC_RMW_TAGVDW3S(base, index, FMC_TAGVDW3S_valid_MASK, FMC_TAGVDW3S_valid(value)))
+#define FMC_BWR_TAGVDW3S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW3S_REG(base, index), FMC_TAGVDW3S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW3S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW3S_tag field. */
+#define FMC_RD_TAGVDW3S_tag(base, index) ((FMC_TAGVDW3S_REG(base, index) & FMC_TAGVDW3S_tag_MASK) >> FMC_TAGVDW3S_tag_SHIFT)
+#define FMC_BRD_TAGVDW3S_tag(base, index) (FMC_RD_TAGVDW3S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW3S_tag(base, index, value) (FMC_RMW_TAGVDW3S(base, index, FMC_TAGVDW3S_tag_MASK, FMC_TAGVDW3S_tag(value)))
+#define FMC_BWR_TAGVDW3S_tag(base, index, value) (FMC_WR_TAGVDW3S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_DATA_U - Cache Data Storage (upper word)
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_DATA_U - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_DATA_U register
+ */
+/*@{*/
+#define FMC_RD_DATA_U(base, index, index2) (FMC_DATA_U_REG(base, index, index2))
+#define FMC_WR_DATA_U(base, index, index2, value) (FMC_DATA_U_REG(base, index, index2) = (value))
+#define FMC_RMW_DATA_U(base, index, index2, mask, value) (FMC_WR_DATA_U(base, index, index2, (FMC_RD_DATA_U(base, index, index2) & ~(mask)) | (value)))
+#define FMC_SET_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) |  (value)))
+#define FMC_CLR_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) & ~(value)))
+#define FMC_TOG_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_DATA_L - Cache Data Storage (lower word)
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_DATA_L - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_DATA_L register
+ */
+/*@{*/
+#define FMC_RD_DATA_L(base, index, index2) (FMC_DATA_L_REG(base, index, index2))
+#define FMC_WR_DATA_L(base, index, index2, value) (FMC_DATA_L_REG(base, index, index2) = (value))
+#define FMC_RMW_DATA_L(base, index, index2, mask, value) (FMC_WR_DATA_L(base, index, index2, (FMC_RD_DATA_L(base, index, index2) & ~(mask)) | (value)))
+#define FMC_SET_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) |  (value)))
+#define FMC_CLR_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) & ~(value)))
+#define FMC_TOG_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FTFE
+ *
+ * Flash Memory Interface
+ *
+ * Registers defined in this header file:
+ * - FTFE_FSTAT - Flash Status Register
+ * - FTFE_FCNFG - Flash Configuration Register
+ * - FTFE_FSEC - Flash Security Register
+ * - FTFE_FOPT - Flash Option Register
+ * - FTFE_FCCOB3 - Flash Common Command Object Registers
+ * - FTFE_FCCOB2 - Flash Common Command Object Registers
+ * - FTFE_FCCOB1 - Flash Common Command Object Registers
+ * - FTFE_FCCOB0 - Flash Common Command Object Registers
+ * - FTFE_FCCOB7 - Flash Common Command Object Registers
+ * - FTFE_FCCOB6 - Flash Common Command Object Registers
+ * - FTFE_FCCOB5 - Flash Common Command Object Registers
+ * - FTFE_FCCOB4 - Flash Common Command Object Registers
+ * - FTFE_FCCOBB - Flash Common Command Object Registers
+ * - FTFE_FCCOBA - Flash Common Command Object Registers
+ * - FTFE_FCCOB9 - Flash Common Command Object Registers
+ * - FTFE_FCCOB8 - Flash Common Command Object Registers
+ * - FTFE_FPROT3 - Program Flash Protection Registers
+ * - FTFE_FPROT2 - Program Flash Protection Registers
+ * - FTFE_FPROT1 - Program Flash Protection Registers
+ * - FTFE_FPROT0 - Program Flash Protection Registers
+ * - FTFE_FEPROT - EEPROM Protection Register
+ * - FTFE_FDPROT - Data Flash Protection Register
+ */
+
+#define FTFE_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFE module. */
+#define FTFE_IDX (0U) /*!< Instance number for FTFE. */
+
+/*******************************************************************************
+ * FTFE_FSTAT - Flash Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FSTAT - Flash Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FSTAT register reports the operational status of the FTFE module. The
+ * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0
+ * bit is read only. The unassigned bits read 0 and are not writable. When set, the
+ * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this
+ * register prevent the launch of any more commands or writes to the FlexRAM (when
+ * EEERDY is set) until the flag is cleared (by writing a one to it).
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FSTAT register
+ */
+/*@{*/
+#define FTFE_RD_FSTAT(base)      (FTFE_FSTAT_REG(base))
+#define FTFE_WR_FSTAT(base, value) (FTFE_FSTAT_REG(base) = (value))
+#define FTFE_RMW_FSTAT(base, mask, value) (FTFE_WR_FSTAT(base, (FTFE_RD_FSTAT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) |  (value)))
+#define FTFE_CLR_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) & ~(value)))
+#define FTFE_TOG_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FSTAT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO)
+ *
+ * The MGSTAT0 status flag is set if an error is detected during execution of an
+ * FTFE command or during the flash reset sequence. As a status flag, this bit
+ * cannot (and need not) be cleared by the user like the other error flags in this
+ * register. The value of the MGSTAT0 bit for "command-N" is valid only at the
+ * end of the "command-N" execution when CCIF=1 and before the next command has
+ * been launched. At some point during the execution of "command-N+1," the previous
+ * result is discarded and any previous error is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field. */
+#define FTFE_RD_FSTAT_MGSTAT0(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_MGSTAT0_MASK) >> FTFE_FSTAT_MGSTAT0_SHIFT)
+#define FTFE_BRD_FSTAT_MGSTAT0(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_MGSTAT0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C)
+ *
+ * The FPVIOL error bit indicates an attempt was made to program or erase an
+ * address in a protected area of program flash or data flash memory during a
+ * command write sequence or a write was attempted to a protected area of the FlexRAM
+ * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared
+ * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a
+ * 0 to the FPVIOL bit has no effect.
+ *
+ * Values:
+ * - 0b0 - No protection violation detected
+ * - 0b1 - Protection violation detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_FPVIOL field. */
+#define FTFE_RD_FSTAT_FPVIOL(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_FPVIOL_MASK) >> FTFE_FSTAT_FPVIOL_SHIFT)
+#define FTFE_BRD_FSTAT_FPVIOL(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_FPVIOL_SHIFT))
+
+/*! @brief Set the FPVIOL field to a new value. */
+#define FTFE_WR_FSTAT_FPVIOL(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_FPVIOL(value)))
+#define FTFE_BWR_FSTAT_FPVIOL(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_FPVIOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field ACCERR[5] (W1C)
+ *
+ * The ACCERR error bit indicates an illegal access has occurred to an FTFE
+ * resource caused by a violation of the command write sequence or issuing an illegal
+ * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch
+ * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
+ * ACCERR bit has no effect.
+ *
+ * Values:
+ * - 0b0 - No access error detected
+ * - 0b1 - Access error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_ACCERR field. */
+#define FTFE_RD_FSTAT_ACCERR(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_ACCERR_MASK) >> FTFE_FSTAT_ACCERR_SHIFT)
+#define FTFE_BRD_FSTAT_ACCERR(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_ACCERR_SHIFT))
+
+/*! @brief Set the ACCERR field to a new value. */
+#define FTFE_WR_FSTAT_ACCERR(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_ACCERR(value)))
+#define FTFE_BWR_FSTAT_ACCERR(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_ACCERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C)
+ *
+ * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE
+ * resource that was being manipulated by an FTFE command (CCIF=0). Any
+ * simultaneous access is detected as a collision error by the block arbitration logic. The
+ * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by
+ * writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
+ *
+ * Values:
+ * - 0b0 - No collision error detected
+ * - 0b1 - Collision error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_RDCOLERR field. */
+#define FTFE_RD_FSTAT_RDCOLERR(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_RDCOLERR_MASK) >> FTFE_FSTAT_RDCOLERR_SHIFT)
+#define FTFE_BRD_FSTAT_RDCOLERR(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_RDCOLERR_SHIFT))
+
+/*! @brief Set the RDCOLERR field to a new value. */
+#define FTFE_WR_FSTAT_RDCOLERR(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_RDCOLERR(value)))
+#define FTFE_BWR_FSTAT_RDCOLERR(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_RDCOLERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field CCIF[7] (W1C)
+ *
+ * The CCIF flag indicates that a FTFE command or EEPROM file system operation
+ * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a
+ * command, and CCIF stays low until command completion or command violation. The
+ * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE,
+ * and CCIF stays low until the EEPROM file system has created the associated
+ * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory
+ * controller at the end of the reset initialization sequence. Depending on how
+ * quickly the read occurs after reset release, the user may or may not see the 0
+ * hardware reset value.
+ *
+ * Values:
+ * - 0b0 - FTFE command or EEPROM file system operation in progress
+ * - 0b1 - FTFE command or EEPROM file system operation has completed
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_CCIF field. */
+#define FTFE_RD_FSTAT_CCIF(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_CCIF_MASK) >> FTFE_FSTAT_CCIF_SHIFT)
+#define FTFE_BRD_FSTAT_CCIF(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_CCIF_SHIFT))
+
+/*! @brief Set the CCIF field to a new value. */
+#define FTFE_WR_FSTAT_CCIF(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_CCIF_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_RDCOLERR_MASK), FTFE_FSTAT_CCIF(value)))
+#define FTFE_BWR_FSTAT_CCIF(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_CCIF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCNFG - Flash Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCNFG - Flash Configuration Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides information on the current functional state of the
+ * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write
+ * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned
+ * bits read as noted and are not writable. The reset values for the SWAP, PFLSH,
+ * RAMRDY, and EEERDY bits are determined during the reset sequence.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCNFG register
+ */
+/*@{*/
+#define FTFE_RD_FCNFG(base)      (FTFE_FCNFG_REG(base))
+#define FTFE_WR_FCNFG(base, value) (FTFE_FCNFG_REG(base) = (value))
+#define FTFE_RMW_FCNFG(base, mask, value) (FTFE_WR_FCNFG(base, (FTFE_RD_FCNFG(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) |  (value)))
+#define FTFE_CLR_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) & ~(value)))
+#define FTFE_TOG_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FCNFG bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCNFG, field EEERDY[0] (RO)
+ *
+ * For devices with FlexNVM: This flag indicates if the EEPROM backup data has
+ * been copied to the FlexRAM and is therefore available for read access. During
+ * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if
+ * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM:
+ * This bit is reserved.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FlexRAM is not available for EEPROM
+ *     operation.
+ * - 0b1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations
+ *     where: reads from the FlexRAM return data previously written to the
+ *     FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the
+ *     written data in the FlexRAM and EEPROM backup.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_EEERDY field. */
+#define FTFE_RD_FCNFG_EEERDY(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_EEERDY_MASK) >> FTFE_FCNFG_EEERDY_SHIFT)
+#define FTFE_BRD_FCNFG_EEERDY(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_EEERDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field RAMRDY[1] (RO)
+ *
+ * This flag indicates the current status of the FlexRAM/ programming
+ * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally
+ * controlled by the Set FlexRAM Function command. During the reset sequence, the
+ * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will
+ * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is
+ * cleared if the Program Partition command is run to partition the FlexNVM block
+ * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks
+ * command or execution of the erase-all operation triggered external to the FTFE.
+ * For devices without FlexNVM: This bit should always be set.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FlexRAM is not available for traditional
+ *     RAM access. For devices without FlexNVM: Programming acceleration RAM is not
+ *     available.
+ * - 0b1 - For devices with FlexNVM: FlexRAM is available as traditional RAM
+ *     only; writes to the FlexRAM do not trigger EEPROM operations. For devices
+ *     without FlexNVM: Programming acceleration RAM is available.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_RAMRDY field. */
+#define FTFE_RD_FCNFG_RAMRDY(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_RAMRDY_MASK) >> FTFE_FCNFG_RAMRDY_SHIFT)
+#define FTFE_BRD_FCNFG_RAMRDY(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RAMRDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field PFLSH[2] (RO)
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FTFE configuration supports two program
+ *     flash blocks and two FlexNVM blocks For devices with program flash only:
+ *     Reserved
+ * - 0b1 - For devices with FlexNVM: Reserved For devices with program flash
+ *     only: FTFE configuration supports four program flash blocks
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_PFLSH field. */
+#define FTFE_RD_FCNFG_PFLSH(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_PFLSH_MASK) >> FTFE_FCNFG_PFLSH_SHIFT)
+#define FTFE_BRD_FCNFG_PFLSH(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_PFLSH_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field SWAP[3] (RO)
+ *
+ * The SWAP flag indicates which half of the program flash space is located at
+ * relative address 0x0000. The state of the SWAP flag is set by the FTFE during
+ * the reset sequence. See for information on swap management.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: Program flash 0 block is located at
+ *     relative address 0x0000 For devices with program flash only: Program flash 0
+ *     block is located at relative address 0x0000
+ * - 0b1 - For devices with FlexNVM: Reserved For devices with program flash
+ *     only: Program flash 1 block is located at relative address 0x0000
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_SWAP field. */
+#define FTFE_RD_FCNFG_SWAP(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_SWAP_MASK) >> FTFE_FCNFG_SWAP_SHIFT)
+#define FTFE_BRD_FCNFG_SWAP(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_SWAP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW)
+ *
+ * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector
+ * command while it is executing.
+ *
+ * Values:
+ * - 0b0 - No suspend requested
+ * - 0b1 - Suspend the current Erase Flash Sector command execution.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_ERSSUSP field. */
+#define FTFE_RD_FCNFG_ERSSUSP(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_ERSSUSP_MASK) >> FTFE_FCNFG_ERSSUSP_SHIFT)
+#define FTFE_BRD_FCNFG_ERSSUSP(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSSUSP_SHIFT))
+
+/*! @brief Set the ERSSUSP field to a new value. */
+#define FTFE_WR_FCNFG_ERSSUSP(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_ERSSUSP_MASK, FTFE_FCNFG_ERSSUSP(value)))
+#define FTFE_BWR_FCNFG_ERSSUSP(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSSUSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO)
+ *
+ * This bit issues a request to the memory controller to execute the Erase All
+ * Blocks command and release security. ERSAREQ is not directly writable but is
+ * under indirect user control. Refer to the device's Chip Configuration details on
+ * how to request this command. The ERSAREQ bit sets when an erase all request
+ * is triggered external to the FTFE and CCIF is set (no command is currently
+ * being executed). ERSAREQ is cleared by the FTFE when the operation completes.
+ *
+ * Values:
+ * - 0b0 - No request or request complete
+ * - 0b1 - Request to: run the Erase All Blocks command, verify the erased
+ *     state, program the security byte in the Flash Configuration Field to the
+ *     unsecure state, and release MCU security by setting the FSEC[SEC] field to the
+ *     unsecure state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_ERSAREQ field. */
+#define FTFE_RD_FCNFG_ERSAREQ(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_ERSAREQ_MASK) >> FTFE_FCNFG_ERSAREQ_SHIFT)
+#define FTFE_BRD_FCNFG_ERSAREQ(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSAREQ_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW)
+ *
+ * The RDCOLLIE bit controls interrupt generation when an FTFE read collision
+ * error occurs.
+ *
+ * Values:
+ * - 0b0 - Read collision error interrupt disabled
+ * - 0b1 - Read collision error interrupt enabled. An interrupt request is
+ *     generated whenever an FTFE read collision error is detected (see the
+ *     description of FSTAT[RDCOLERR]).
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field. */
+#define FTFE_RD_FCNFG_RDCOLLIE(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_RDCOLLIE_MASK) >> FTFE_FCNFG_RDCOLLIE_SHIFT)
+#define FTFE_BRD_FCNFG_RDCOLLIE(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RDCOLLIE_SHIFT))
+
+/*! @brief Set the RDCOLLIE field to a new value. */
+#define FTFE_WR_FCNFG_RDCOLLIE(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_RDCOLLIE_MASK, FTFE_FCNFG_RDCOLLIE(value)))
+#define FTFE_BWR_FCNFG_RDCOLLIE(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RDCOLLIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field CCIE[7] (RW)
+ *
+ * The CCIE bit controls interrupt generation when an FTFE command completes.
+ *
+ * Values:
+ * - 0b0 - Command complete interrupt disabled
+ * - 0b1 - Command complete interrupt enabled. An interrupt request is generated
+ *     whenever the FSTAT[CCIF] flag is set.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_CCIE field. */
+#define FTFE_RD_FCNFG_CCIE(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_CCIE_MASK) >> FTFE_FCNFG_CCIE_SHIFT)
+#define FTFE_BRD_FCNFG_CCIE(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_CCIE_SHIFT))
+
+/*! @brief Set the CCIE field to a new value. */
+#define FTFE_WR_FCNFG_CCIE(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_CCIE_MASK, FTFE_FCNFG_CCIE(value)))
+#define FTFE_BWR_FCNFG_CCIE(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_CCIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FSEC - Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FSEC - Flash Security Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This read-only register holds all bits associated with the security of the
+ * MCU and FTFE module. During the reset sequence, the register is loaded with the
+ * contents of the flash security byte in the Flash Configuration Field located
+ * in program flash memory. The Flash basis for the values is signified by X in
+ * the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FSEC register
+ */
+/*@{*/
+#define FTFE_RD_FSEC(base)       (FTFE_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FSEC bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSEC, field SEC[1:0] (RO)
+ *
+ * These bits define the security state of the MCU. In the secure state, the MCU
+ * limits access to FTFE module resources. The limitations are defined per
+ * device and are detailed in the Chip Configuration details. If the FTFE module is
+ * unsecured using backdoor key access, the SEC bits are forced to 10b.
+ *
+ * Values:
+ * - 0b00 - MCU security status is secure
+ * - 0b01 - MCU security status is secure
+ * - 0b10 - MCU security status is unsecure (The standard shipping condition of
+ *     the FTFE is unsecure.)
+ * - 0b11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_SEC field. */
+#define FTFE_RD_FSEC_SEC(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_SEC_MASK) >> FTFE_FSEC_SEC_SHIFT)
+#define FTFE_BRD_FSEC_SEC(base) (FTFE_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field FSLACC[3:2] (RO)
+ *
+ * These bits enable or disable access to the flash memory contents during
+ * returned part failure analysis at Freescale. When SEC is secure and FSLACC is
+ * denied, access to the program flash contents is denied and any failure analysis
+ * performed by Freescale factory test must begin with a full erase to unsecure the
+ * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is
+ * granted), Freescale factory testing has visibility of the current flash
+ * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to
+ * secure. When the SEC field is set to unsecure, the FSLACC setting does not
+ * matter.
+ *
+ * Values:
+ * - 0b00 - Freescale factory access granted
+ * - 0b01 - Freescale factory access denied
+ * - 0b10 - Freescale factory access denied
+ * - 0b11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_FSLACC field. */
+#define FTFE_RD_FSEC_FSLACC(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_FSLACC_MASK) >> FTFE_FSEC_FSLACC_SHIFT)
+#define FTFE_BRD_FSEC_FSLACC(base) (FTFE_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field MEEN[5:4] (RO)
+ *
+ * Enables and disables mass erase capability of the FTFE module. The state of
+ * the MEEN bits is only relevant when the SEC bits are set to secure outside of
+ * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does
+ * not matter.
+ *
+ * Values:
+ * - 0b00 - Mass erase is enabled
+ * - 0b01 - Mass erase is enabled
+ * - 0b10 - Mass erase is disabled
+ * - 0b11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_MEEN field. */
+#define FTFE_RD_FSEC_MEEN(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_MEEN_MASK) >> FTFE_FSEC_MEEN_SHIFT)
+#define FTFE_BRD_FSEC_MEEN(base) (FTFE_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field KEYEN[7:6] (RO)
+ *
+ * These bits enable and disable backdoor key access to the FTFE module.
+ *
+ * Values:
+ * - 0b00 - Backdoor key access disabled
+ * - 0b01 - Backdoor key access disabled (preferred KEYEN state to disable
+ *     backdoor key access)
+ * - 0b10 - Backdoor key access enabled
+ * - 0b11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_KEYEN field. */
+#define FTFE_RD_FSEC_KEYEN(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_KEYEN_MASK) >> FTFE_FSEC_KEYEN_SHIFT)
+#define FTFE_BRD_FSEC_KEYEN(base) (FTFE_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FOPT - Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FOPT - Flash Option Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * The flash option register allows the MCU to customize its operations by
+ * examining the state of these read-only bits, which are loaded from NVM at reset.
+ * The function of the bits is defined in the device's Chip Configuration details.
+ * All bits in the register are read-only. During the reset sequence, the
+ * register is loaded from the flash nonvolatile option byte in the Flash Configuration
+ * Field located in program flash memory. The flash basis for the values is
+ * signified by X in the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FOPT register
+ */
+/*@{*/
+#define FTFE_RD_FOPT(base)       (FTFE_FOPT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB3 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB3 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB3 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB3(base)     (FTFE_FCCOB3_REG(base))
+#define FTFE_WR_FCCOB3(base, value) (FTFE_FCCOB3_REG(base) = (value))
+#define FTFE_RMW_FCCOB3(base, mask, value) (FTFE_WR_FCCOB3(base, (FTFE_RD_FCCOB3(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) |  (value)))
+#define FTFE_CLR_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) & ~(value)))
+#define FTFE_TOG_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB2 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB2 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB2 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB2(base)     (FTFE_FCCOB2_REG(base))
+#define FTFE_WR_FCCOB2(base, value) (FTFE_FCCOB2_REG(base) = (value))
+#define FTFE_RMW_FCCOB2(base, mask, value) (FTFE_WR_FCCOB2(base, (FTFE_RD_FCCOB2(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) |  (value)))
+#define FTFE_CLR_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) & ~(value)))
+#define FTFE_TOG_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB1 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB1 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB1 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB1(base)     (FTFE_FCCOB1_REG(base))
+#define FTFE_WR_FCCOB1(base, value) (FTFE_FCCOB1_REG(base) = (value))
+#define FTFE_RMW_FCCOB1(base, mask, value) (FTFE_WR_FCCOB1(base, (FTFE_RD_FCCOB1(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) |  (value)))
+#define FTFE_CLR_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) & ~(value)))
+#define FTFE_TOG_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB0 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB0 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB0 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB0(base)     (FTFE_FCCOB0_REG(base))
+#define FTFE_WR_FCCOB0(base, value) (FTFE_FCCOB0_REG(base) = (value))
+#define FTFE_RMW_FCCOB0(base, mask, value) (FTFE_WR_FCCOB0(base, (FTFE_RD_FCCOB0(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) |  (value)))
+#define FTFE_CLR_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) & ~(value)))
+#define FTFE_TOG_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB7 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB7 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB7 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB7(base)     (FTFE_FCCOB7_REG(base))
+#define FTFE_WR_FCCOB7(base, value) (FTFE_FCCOB7_REG(base) = (value))
+#define FTFE_RMW_FCCOB7(base, mask, value) (FTFE_WR_FCCOB7(base, (FTFE_RD_FCCOB7(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) |  (value)))
+#define FTFE_CLR_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) & ~(value)))
+#define FTFE_TOG_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB6 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB6 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB6 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB6(base)     (FTFE_FCCOB6_REG(base))
+#define FTFE_WR_FCCOB6(base, value) (FTFE_FCCOB6_REG(base) = (value))
+#define FTFE_RMW_FCCOB6(base, mask, value) (FTFE_WR_FCCOB6(base, (FTFE_RD_FCCOB6(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) |  (value)))
+#define FTFE_CLR_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) & ~(value)))
+#define FTFE_TOG_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB5 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB5 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB5 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB5(base)     (FTFE_FCCOB5_REG(base))
+#define FTFE_WR_FCCOB5(base, value) (FTFE_FCCOB5_REG(base) = (value))
+#define FTFE_RMW_FCCOB5(base, mask, value) (FTFE_WR_FCCOB5(base, (FTFE_RD_FCCOB5(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) |  (value)))
+#define FTFE_CLR_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) & ~(value)))
+#define FTFE_TOG_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB4 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB4 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB4 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB4(base)     (FTFE_FCCOB4_REG(base))
+#define FTFE_WR_FCCOB4(base, value) (FTFE_FCCOB4_REG(base) = (value))
+#define FTFE_RMW_FCCOB4(base, mask, value) (FTFE_WR_FCCOB4(base, (FTFE_RD_FCCOB4(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) |  (value)))
+#define FTFE_CLR_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) & ~(value)))
+#define FTFE_TOG_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOBB - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOBB - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBB register
+ */
+/*@{*/
+#define FTFE_RD_FCCOBB(base)     (FTFE_FCCOBB_REG(base))
+#define FTFE_WR_FCCOBB(base, value) (FTFE_FCCOBB_REG(base) = (value))
+#define FTFE_RMW_FCCOBB(base, mask, value) (FTFE_WR_FCCOBB(base, (FTFE_RD_FCCOBB(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) |  (value)))
+#define FTFE_CLR_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) & ~(value)))
+#define FTFE_TOG_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOBA - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOBA - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBA register
+ */
+/*@{*/
+#define FTFE_RD_FCCOBA(base)     (FTFE_FCCOBA_REG(base))
+#define FTFE_WR_FCCOBA(base, value) (FTFE_FCCOBA_REG(base) = (value))
+#define FTFE_RMW_FCCOBA(base, mask, value) (FTFE_WR_FCCOBA(base, (FTFE_RD_FCCOBA(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) |  (value)))
+#define FTFE_CLR_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) & ~(value)))
+#define FTFE_TOG_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB9 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB9 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB9 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB9(base)     (FTFE_FCCOB9_REG(base))
+#define FTFE_WR_FCCOB9(base, value) (FTFE_FCCOB9_REG(base) = (value))
+#define FTFE_RMW_FCCOB9(base, mask, value) (FTFE_WR_FCCOB9(base, (FTFE_RD_FCCOB9(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) |  (value)))
+#define FTFE_CLR_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) & ~(value)))
+#define FTFE_TOG_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB8 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB8 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB8 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB8(base)     (FTFE_FCCOB8_REG(base))
+#define FTFE_WR_FCCOB8(base, value) (FTFE_FCCOB8_REG(base) = (value))
+#define FTFE_RMW_FCCOB8(base, mask, value) (FTFE_WR_FCCOB8(base, (FTFE_RD_FCCOB8(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) |  (value)))
+#define FTFE_CLR_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) & ~(value)))
+#define FTFE_TOG_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT3 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT3 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT3 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT3(base)     (FTFE_FPROT3_REG(base))
+#define FTFE_WR_FPROT3(base, value) (FTFE_FPROT3_REG(base) = (value))
+#define FTFE_RMW_FPROT3(base, mask, value) (FTFE_WR_FPROT3(base, (FTFE_RD_FPROT3(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) |  (value)))
+#define FTFE_CLR_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) & ~(value)))
+#define FTFE_TOG_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT2 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT2 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT2 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT2(base)     (FTFE_FPROT2_REG(base))
+#define FTFE_WR_FPROT2(base, value) (FTFE_FPROT2_REG(base) = (value))
+#define FTFE_RMW_FPROT2(base, mask, value) (FTFE_WR_FPROT2(base, (FTFE_RD_FPROT2(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) |  (value)))
+#define FTFE_CLR_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) & ~(value)))
+#define FTFE_TOG_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT1 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT1 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT1 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT1(base)     (FTFE_FPROT1_REG(base))
+#define FTFE_WR_FPROT1(base, value) (FTFE_FPROT1_REG(base) = (value))
+#define FTFE_RMW_FPROT1(base, mask, value) (FTFE_WR_FPROT1(base, (FTFE_RD_FPROT1(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) |  (value)))
+#define FTFE_CLR_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) & ~(value)))
+#define FTFE_TOG_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT0 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT0 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT0 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT0(base)     (FTFE_FPROT0_REG(base))
+#define FTFE_WR_FPROT0(base, value) (FTFE_FPROT0_REG(base) = (value))
+#define FTFE_RMW_FPROT0(base, mask, value) (FTFE_WR_FPROT0(base, (FTFE_RD_FPROT0(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) |  (value)))
+#define FTFE_CLR_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) & ~(value)))
+#define FTFE_TOG_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FEPROT - EEPROM Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FEPROT - EEPROM Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of
+ * the FlexRAM are protected against program and erase operations. Protected
+ * EEPROM regions cannot have their content changed by writing to it. Unprotected
+ * regions can be changed by writing to the FlexRAM. For devices with program flash
+ * only: This register is reserved and not used.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FEPROT register
+ */
+/*@{*/
+#define FTFE_RD_FEPROT(base)     (FTFE_FEPROT_REG(base))
+#define FTFE_WR_FEPROT(base, value) (FTFE_FEPROT_REG(base) = (value))
+#define FTFE_RMW_FEPROT(base, mask, value) (FTFE_WR_FEPROT(base, (FTFE_RD_FEPROT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) |  (value)))
+#define FTFE_CLR_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) & ~(value)))
+#define FTFE_TOG_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FDPROT - Data Flash Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FDPROT - Data Flash Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FDPROT register defines which data flash regions are protected against
+ * program and erase operations. Protected Flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by both program and erase
+ * operations.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FDPROT register
+ */
+/*@{*/
+#define FTFE_RD_FDPROT(base)     (FTFE_FDPROT_REG(base))
+#define FTFE_WR_FDPROT(base, value) (FTFE_FDPROT_REG(base) = (value))
+#define FTFE_RMW_FDPROT(base, mask, value) (FTFE_WR_FDPROT(base, (FTFE_RD_FDPROT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) |  (value)))
+#define FTFE_CLR_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) & ~(value)))
+#define FTFE_TOG_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FTM
+ *
+ * FlexTimer Module
+ *
+ * Registers defined in this header file:
+ * - FTM_SC - Status And Control
+ * - FTM_CNT - Counter
+ * - FTM_MOD - Modulo
+ * - FTM_CnSC - Channel (n) Status And Control
+ * - FTM_CnV - Channel (n) Value
+ * - FTM_CNTIN - Counter Initial Value
+ * - FTM_STATUS - Capture And Compare Status
+ * - FTM_MODE - Features Mode Selection
+ * - FTM_SYNC - Synchronization
+ * - FTM_OUTINIT - Initial State For Channels Output
+ * - FTM_OUTMASK - Output Mask
+ * - FTM_COMBINE - Function For Linked Channels
+ * - FTM_DEADTIME - Deadtime Insertion Control
+ * - FTM_EXTTRIG - FTM External Trigger
+ * - FTM_POL - Channels Polarity
+ * - FTM_FMS - Fault Mode Status
+ * - FTM_FILTER - Input Capture Filter Control
+ * - FTM_FLTCTRL - Fault Control
+ * - FTM_QDCTRL - Quadrature Decoder Control And Status
+ * - FTM_CONF - Configuration
+ * - FTM_FLTPOL - FTM Fault Input Polarity
+ * - FTM_SYNCONF - Synchronization Configuration
+ * - FTM_INVCTRL - FTM Inverting Control
+ * - FTM_SWOCTRL - FTM Software Output Control
+ * - FTM_PWMLOAD - FTM PWM Load
+ */
+
+#define FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
+#define FTM0_IDX (0U) /*!< Instance number for FTM0. */
+#define FTM1_IDX (1U) /*!< Instance number for FTM1. */
+#define FTM2_IDX (2U) /*!< Instance number for FTM2. */
+#define FTM3_IDX (3U) /*!< Instance number for FTM3. */
+
+/*******************************************************************************
+ * FTM_SC - Status And Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SC - Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * SC contains the overflow status flag and control bits used to configure the
+ * interrupt enable, FTM configuration, clock source, and prescaler factor. These
+ * controls relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SC register
+ */
+/*@{*/
+#define FTM_RD_SC(base)          (FTM_SC_REG(base))
+#define FTM_WR_SC(base, value)   (FTM_SC_REG(base) = (value))
+#define FTM_RMW_SC(base, mask, value) (FTM_WR_SC(base, (FTM_RD_SC(base) & ~(mask)) | (value)))
+#define FTM_SET_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) |  (value)))
+#define FTM_CLR_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) & ~(value)))
+#define FTM_TOG_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SC bitfields
+ */
+
+/*!
+ * @name Register FTM_SC, field PS[2:0] (RW)
+ *
+ * Selects one of 8 division factors for the clock source selected by CLKS. The
+ * new prescaler factor affects the clock source on the next system clock cycle
+ * after the new value is updated into the register bits. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b000 - Divide by 1
+ * - 0b001 - Divide by 2
+ * - 0b010 - Divide by 4
+ * - 0b011 - Divide by 8
+ * - 0b100 - Divide by 16
+ * - 0b101 - Divide by 32
+ * - 0b110 - Divide by 64
+ * - 0b111 - Divide by 128
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_PS field. */
+#define FTM_RD_SC_PS(base)   ((FTM_SC_REG(base) & FTM_SC_PS_MASK) >> FTM_SC_PS_SHIFT)
+#define FTM_BRD_SC_PS(base)  (FTM_RD_SC_PS(base))
+
+/*! @brief Set the PS field to a new value. */
+#define FTM_WR_SC_PS(base, value) (FTM_RMW_SC(base, FTM_SC_PS_MASK, FTM_SC_PS(value)))
+#define FTM_BWR_SC_PS(base, value) (FTM_WR_SC_PS(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field CLKS[4:3] (RW)
+ *
+ * Selects one of the three FTM counter clock sources. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b00 - No clock selected. This in effect disables the FTM counter.
+ * - 0b01 - System clock
+ * - 0b10 - Fixed frequency clock
+ * - 0b11 - External clock
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_CLKS field. */
+#define FTM_RD_SC_CLKS(base) ((FTM_SC_REG(base) & FTM_SC_CLKS_MASK) >> FTM_SC_CLKS_SHIFT)
+#define FTM_BRD_SC_CLKS(base) (FTM_RD_SC_CLKS(base))
+
+/*! @brief Set the CLKS field to a new value. */
+#define FTM_WR_SC_CLKS(base, value) (FTM_RMW_SC(base, FTM_SC_CLKS_MASK, FTM_SC_CLKS(value)))
+#define FTM_BWR_SC_CLKS(base, value) (FTM_WR_SC_CLKS(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field CPWMS[5] (RW)
+ *
+ * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
+ * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ *
+ * Values:
+ * - 0b0 - FTM counter operates in Up Counting mode.
+ * - 0b1 - FTM counter operates in Up-Down Counting mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_CPWMS field. */
+#define FTM_RD_SC_CPWMS(base) ((FTM_SC_REG(base) & FTM_SC_CPWMS_MASK) >> FTM_SC_CPWMS_SHIFT)
+#define FTM_BRD_SC_CPWMS(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_CPWMS_SHIFT))
+
+/*! @brief Set the CPWMS field to a new value. */
+#define FTM_WR_SC_CPWMS(base, value) (FTM_RMW_SC(base, FTM_SC_CPWMS_MASK, FTM_SC_CPWMS(value)))
+#define FTM_BWR_SC_CPWMS(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_CPWMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field TOIE[6] (RW)
+ *
+ * Enables FTM overflow interrupts.
+ *
+ * Values:
+ * - 0b0 - Disable TOF interrupts. Use software polling.
+ * - 0b1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_TOIE field. */
+#define FTM_RD_SC_TOIE(base) ((FTM_SC_REG(base) & FTM_SC_TOIE_MASK) >> FTM_SC_TOIE_SHIFT)
+#define FTM_BRD_SC_TOIE(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOIE_SHIFT))
+
+/*! @brief Set the TOIE field to a new value. */
+#define FTM_WR_SC_TOIE(base, value) (FTM_RMW_SC(base, FTM_SC_TOIE_MASK, FTM_SC_TOIE(value)))
+#define FTM_BWR_SC_TOIE(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field TOF[7] (ROWZ)
+ *
+ * Set by hardware when the FTM counter passes the value in the MOD register.
+ * The TOF bit is cleared by reading the SC register while TOF is set and then
+ * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
+ * occurs between the read and write operations, the write operation has no
+ * effect; therefore, TOF remains set indicating an overflow has occurred. In this
+ * case, a TOF interrupt request is not lost due to the clearing sequence for a
+ * previous TOF.
+ *
+ * Values:
+ * - 0b0 - FTM counter has not overflowed.
+ * - 0b1 - FTM counter has overflowed.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_TOF field. */
+#define FTM_RD_SC_TOF(base)  ((FTM_SC_REG(base) & FTM_SC_TOF_MASK) >> FTM_SC_TOF_SHIFT)
+#define FTM_BRD_SC_TOF(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOF_SHIFT))
+
+/*! @brief Set the TOF field to a new value. */
+#define FTM_WR_SC_TOF(base, value) (FTM_RMW_SC(base, FTM_SC_TOF_MASK, FTM_SC_TOF(value)))
+#define FTM_BWR_SC_TOF(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CNT - Counter
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CNT - Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CNT register contains the FTM counter value. Reset clears the CNT
+ * register. Writing any value to COUNT updates the counter with its initial value,
+ * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
+ * may read.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CNT register
+ */
+/*@{*/
+#define FTM_RD_CNT(base)         (FTM_CNT_REG(base))
+#define FTM_WR_CNT(base, value)  (FTM_CNT_REG(base) = (value))
+#define FTM_RMW_CNT(base, mask, value) (FTM_WR_CNT(base, (FTM_RD_CNT(base) & ~(mask)) | (value)))
+#define FTM_SET_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) |  (value)))
+#define FTM_CLR_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) & ~(value)))
+#define FTM_TOG_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CNT bitfields
+ */
+
+/*!
+ * @name Register FTM_CNT, field COUNT[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CNT_COUNT field. */
+#define FTM_RD_CNT_COUNT(base) ((FTM_CNT_REG(base) & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT)
+#define FTM_BRD_CNT_COUNT(base) (FTM_RD_CNT_COUNT(base))
+
+/*! @brief Set the COUNT field to a new value. */
+#define FTM_WR_CNT_COUNT(base, value) (FTM_RMW_CNT(base, FTM_CNT_COUNT_MASK, FTM_CNT_COUNT(value)))
+#define FTM_BWR_CNT_COUNT(base, value) (FTM_WR_CNT_COUNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_MOD - Modulo
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_MOD - Modulo (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Modulo register contains the modulo value for the FTM counter. After the
+ * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
+ * the next clock, and the next value of FTM counter depends on the selected
+ * counting method; see Counter. Writing to the MOD register latches the value into a
+ * buffer. The MOD register is updated with the value of its write buffer
+ * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
+ * mechanism may be manually reset by writing to the SC register whether BDM is
+ * active or not. Initialize the FTM counter, by writing to CNT, before writing
+ * to the MOD register to avoid confusion about when the first counter overflow
+ * will occur.
+ */
+/*!
+ * @name Constants and macros for entire FTM_MOD register
+ */
+/*@{*/
+#define FTM_RD_MOD(base)         (FTM_MOD_REG(base))
+#define FTM_WR_MOD(base, value)  (FTM_MOD_REG(base) = (value))
+#define FTM_RMW_MOD(base, mask, value) (FTM_WR_MOD(base, (FTM_RD_MOD(base) & ~(mask)) | (value)))
+#define FTM_SET_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) |  (value)))
+#define FTM_CLR_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) & ~(value)))
+#define FTM_TOG_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_MOD bitfields
+ */
+
+/*!
+ * @name Register FTM_MOD, field MOD[15:0] (RW)
+ *
+ * Modulo Value
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MOD_MOD field. */
+#define FTM_RD_MOD_MOD(base) ((FTM_MOD_REG(base) & FTM_MOD_MOD_MASK) >> FTM_MOD_MOD_SHIFT)
+#define FTM_BRD_MOD_MOD(base) (FTM_RD_MOD_MOD(base))
+
+/*! @brief Set the MOD field to a new value. */
+#define FTM_WR_MOD_MOD(base, value) (FTM_RMW_MOD(base, FTM_MOD_MOD_MASK, FTM_MOD_MOD(value)))
+#define FTM_BWR_MOD_MOD(base, value) (FTM_WR_MOD_MOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CnSC - Channel (n) Status And Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CnSC - Channel (n) Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CnSC contains the channel-interrupt-status flag and control bits used to
+ * configure the interrupt enable, channel configuration, and pin function. Mode,
+ * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
+ * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
+ * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
+ * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
+ * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
+ * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
+ * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
+ * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
+ * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
+ * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
+ * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
+ * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
+ * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
+ * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
+ * Enabled Rising and falling edges
+ */
+/*!
+ * @name Constants and macros for entire FTM_CnSC register
+ */
+/*@{*/
+#define FTM_RD_CnSC(base, index) (FTM_CnSC_REG(base, index))
+#define FTM_WR_CnSC(base, index, value) (FTM_CnSC_REG(base, index) = (value))
+#define FTM_RMW_CnSC(base, index, mask, value) (FTM_WR_CnSC(base, index, (FTM_RD_CnSC(base, index) & ~(mask)) | (value)))
+#define FTM_SET_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) |  (value)))
+#define FTM_CLR_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) & ~(value)))
+#define FTM_TOG_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CnSC bitfields
+ */
+
+/*!
+ * @name Register FTM_CnSC, field DMA[0] (RW)
+ *
+ * Enables DMA transfers for the channel.
+ *
+ * Values:
+ * - 0b0 - Disable DMA transfers.
+ * - 0b1 - Enable DMA transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_DMA field. */
+#define FTM_RD_CnSC_DMA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_DMA_MASK) >> FTM_CnSC_DMA_SHIFT)
+#define FTM_BRD_CnSC_DMA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define FTM_WR_CnSC_DMA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_DMA_MASK, FTM_CnSC_DMA(value)))
+#define FTM_BWR_CnSC_DMA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_DMA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field ELSA[2] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_ELSA field. */
+#define FTM_RD_CnSC_ELSA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_ELSA_MASK) >> FTM_CnSC_ELSA_SHIFT)
+#define FTM_BRD_CnSC_ELSA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSA_SHIFT))
+
+/*! @brief Set the ELSA field to a new value. */
+#define FTM_WR_CnSC_ELSA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_ELSA_MASK, FTM_CnSC_ELSA(value)))
+#define FTM_BWR_CnSC_ELSA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field ELSB[3] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_ELSB field. */
+#define FTM_RD_CnSC_ELSB(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_ELSB_MASK) >> FTM_CnSC_ELSB_SHIFT)
+#define FTM_BRD_CnSC_ELSB(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSB_SHIFT))
+
+/*! @brief Set the ELSB field to a new value. */
+#define FTM_WR_CnSC_ELSB(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_ELSB_MASK, FTM_CnSC_ELSB(value)))
+#define FTM_BWR_CnSC_ELSB(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field MSA[4] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_MSA field. */
+#define FTM_RD_CnSC_MSA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_MSA_MASK) >> FTM_CnSC_MSA_SHIFT)
+#define FTM_BRD_CnSC_MSA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSA_SHIFT))
+
+/*! @brief Set the MSA field to a new value. */
+#define FTM_WR_CnSC_MSA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_MSA_MASK, FTM_CnSC_MSA(value)))
+#define FTM_BWR_CnSC_MSA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field MSB[5] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_MSB field. */
+#define FTM_RD_CnSC_MSB(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_MSB_MASK) >> FTM_CnSC_MSB_SHIFT)
+#define FTM_BRD_CnSC_MSB(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSB_SHIFT))
+
+/*! @brief Set the MSB field to a new value. */
+#define FTM_WR_CnSC_MSB(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_MSB_MASK, FTM_CnSC_MSB(value)))
+#define FTM_BWR_CnSC_MSB(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field CHIE[6] (RW)
+ *
+ * Enables channel interrupts.
+ *
+ * Values:
+ * - 0b0 - Disable channel interrupts. Use software polling.
+ * - 0b1 - Enable channel interrupts.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_CHIE field. */
+#define FTM_RD_CnSC_CHIE(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_CHIE_MASK) >> FTM_CnSC_CHIE_SHIFT)
+#define FTM_BRD_CnSC_CHIE(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHIE_SHIFT))
+
+/*! @brief Set the CHIE field to a new value. */
+#define FTM_WR_CnSC_CHIE(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_CHIE_MASK, FTM_CnSC_CHIE(value)))
+#define FTM_BWR_CnSC_CHIE(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field CHF[7] (ROWZ)
+ *
+ * Set by hardware when an event occurs on the channel. CHF is cleared by
+ * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
+ * Writing a 1 to CHF has no effect. If another event occurs between the read and
+ * write operations, the write operation has no effect; therefore, CHF remains set
+ * indicating an event has occurred. In this case a CHF interrupt request is not
+ * lost due to the clearing sequence for a previous CHF.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_CHF field. */
+#define FTM_RD_CnSC_CHF(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_CHF_MASK) >> FTM_CnSC_CHF_SHIFT)
+#define FTM_BRD_CnSC_CHF(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHF_SHIFT))
+
+/*! @brief Set the CHF field to a new value. */
+#define FTM_WR_CnSC_CHF(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_CHF_MASK, FTM_CnSC_CHF(value)))
+#define FTM_BWR_CnSC_CHF(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CnV - Channel (n) Value
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CnV - Channel (n) Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the captured FTM counter value for the input modes or
+ * the match value for the output modes. In Input Capture, Capture Test, and
+ * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
+ * writing to a CnV register latches the value into a buffer. A CnV register is
+ * updated with the value of its write buffer according to Registers updated from
+ * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
+ * reset by writing to the CnSC register whether BDM mode is active or not.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CnV register
+ */
+/*@{*/
+#define FTM_RD_CnV(base, index)  (FTM_CnV_REG(base, index))
+#define FTM_WR_CnV(base, index, value) (FTM_CnV_REG(base, index) = (value))
+#define FTM_RMW_CnV(base, index, mask, value) (FTM_WR_CnV(base, index, (FTM_RD_CnV(base, index) & ~(mask)) | (value)))
+#define FTM_SET_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) |  (value)))
+#define FTM_CLR_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) & ~(value)))
+#define FTM_TOG_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CnV bitfields
+ */
+
+/*!
+ * @name Register FTM_CnV, field VAL[15:0] (RW)
+ *
+ * Captured FTM counter value of the input modes or the match value for the
+ * output modes
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnV_VAL field. */
+#define FTM_RD_CnV_VAL(base, index) ((FTM_CnV_REG(base, index) & FTM_CnV_VAL_MASK) >> FTM_CnV_VAL_SHIFT)
+#define FTM_BRD_CnV_VAL(base, index) (FTM_RD_CnV_VAL(base, index))
+
+/*! @brief Set the VAL field to a new value. */
+#define FTM_WR_CnV_VAL(base, index, value) (FTM_RMW_CnV(base, index, FTM_CnV_VAL_MASK, FTM_CnV_VAL(value)))
+#define FTM_BWR_CnV_VAL(base, index, value) (FTM_WR_CnV_VAL(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CNTIN - Counter Initial Value
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CNTIN - Counter Initial Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Counter Initial Value register contains the initial value for the FTM
+ * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
+ * register is updated with the value of its write buffer according to Registers
+ * updated from write buffers. When the FTM clock is initially selected, by
+ * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
+ * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
+ * write the new value to the the CNTIN register and then initialize the FTM
+ * counter by writing any value to the CNT register.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CNTIN register
+ */
+/*@{*/
+#define FTM_RD_CNTIN(base)       (FTM_CNTIN_REG(base))
+#define FTM_WR_CNTIN(base, value) (FTM_CNTIN_REG(base) = (value))
+#define FTM_RMW_CNTIN(base, mask, value) (FTM_WR_CNTIN(base, (FTM_RD_CNTIN(base) & ~(mask)) | (value)))
+#define FTM_SET_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) |  (value)))
+#define FTM_CLR_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) & ~(value)))
+#define FTM_TOG_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CNTIN bitfields
+ */
+
+/*!
+ * @name Register FTM_CNTIN, field INIT[15:0] (RW)
+ *
+ * Initial Value Of The FTM Counter
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CNTIN_INIT field. */
+#define FTM_RD_CNTIN_INIT(base) ((FTM_CNTIN_REG(base) & FTM_CNTIN_INIT_MASK) >> FTM_CNTIN_INIT_SHIFT)
+#define FTM_BRD_CNTIN_INIT(base) (FTM_RD_CNTIN_INIT(base))
+
+/*! @brief Set the INIT field to a new value. */
+#define FTM_WR_CNTIN_INIT(base, value) (FTM_RMW_CNTIN(base, FTM_CNTIN_INIT_MASK, FTM_CNTIN_INIT(value)))
+#define FTM_BWR_CNTIN_INIT(base, value) (FTM_WR_CNTIN_INIT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_STATUS - Capture And Compare Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_STATUS - Capture And Compare Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
+ * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
+ * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
+ * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
+ * STATUS. Hardware sets the individual channel flags when an event occurs on the
+ * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
+ * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
+ * occurs between the read and write operations, the write operation has no effect;
+ * therefore, CHnF remains set indicating an event has occurred. In this case, a
+ * CHnF interrupt request is not lost due to the clearing sequence for a previous
+ * CHnF. The STATUS register should be used only in Combine mode.
+ */
+/*!
+ * @name Constants and macros for entire FTM_STATUS register
+ */
+/*@{*/
+#define FTM_RD_STATUS(base)      (FTM_STATUS_REG(base))
+#define FTM_WR_STATUS(base, value) (FTM_STATUS_REG(base) = (value))
+#define FTM_RMW_STATUS(base, mask, value) (FTM_WR_STATUS(base, (FTM_RD_STATUS(base) & ~(mask)) | (value)))
+#define FTM_SET_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) |  (value)))
+#define FTM_CLR_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) & ~(value)))
+#define FTM_TOG_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_STATUS bitfields
+ */
+
+/*!
+ * @name Register FTM_STATUS, field CH0F[0] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH0F field. */
+#define FTM_RD_STATUS_CH0F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH0F_MASK) >> FTM_STATUS_CH0F_SHIFT)
+#define FTM_BRD_STATUS_CH0F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH0F_SHIFT))
+
+/*! @brief Set the CH0F field to a new value. */
+#define FTM_WR_STATUS_CH0F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH0F(value)))
+#define FTM_BWR_STATUS_CH0F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH0F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH1F[1] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH1F field. */
+#define FTM_RD_STATUS_CH1F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH1F_MASK) >> FTM_STATUS_CH1F_SHIFT)
+#define FTM_BRD_STATUS_CH1F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH1F_SHIFT))
+
+/*! @brief Set the CH1F field to a new value. */
+#define FTM_WR_STATUS_CH1F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH1F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH1F(value)))
+#define FTM_BWR_STATUS_CH1F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH1F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH2F[2] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH2F field. */
+#define FTM_RD_STATUS_CH2F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH2F_MASK) >> FTM_STATUS_CH2F_SHIFT)
+#define FTM_BRD_STATUS_CH2F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH2F_SHIFT))
+
+/*! @brief Set the CH2F field to a new value. */
+#define FTM_WR_STATUS_CH2F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH2F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH2F(value)))
+#define FTM_BWR_STATUS_CH2F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH2F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH3F[3] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH3F field. */
+#define FTM_RD_STATUS_CH3F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH3F_MASK) >> FTM_STATUS_CH3F_SHIFT)
+#define FTM_BRD_STATUS_CH3F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH3F_SHIFT))
+
+/*! @brief Set the CH3F field to a new value. */
+#define FTM_WR_STATUS_CH3F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH3F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH3F(value)))
+#define FTM_BWR_STATUS_CH3F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH3F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH4F[4] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH4F field. */
+#define FTM_RD_STATUS_CH4F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH4F_MASK) >> FTM_STATUS_CH4F_SHIFT)
+#define FTM_BRD_STATUS_CH4F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH4F_SHIFT))
+
+/*! @brief Set the CH4F field to a new value. */
+#define FTM_WR_STATUS_CH4F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH4F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH4F(value)))
+#define FTM_BWR_STATUS_CH4F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH4F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH5F[5] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH5F field. */
+#define FTM_RD_STATUS_CH5F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH5F_MASK) >> FTM_STATUS_CH5F_SHIFT)
+#define FTM_BRD_STATUS_CH5F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH5F_SHIFT))
+
+/*! @brief Set the CH5F field to a new value. */
+#define FTM_WR_STATUS_CH5F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH5F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH5F(value)))
+#define FTM_BWR_STATUS_CH5F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH5F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH6F[6] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH6F field. */
+#define FTM_RD_STATUS_CH6F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH6F_MASK) >> FTM_STATUS_CH6F_SHIFT)
+#define FTM_BRD_STATUS_CH6F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH6F_SHIFT))
+
+/*! @brief Set the CH6F field to a new value. */
+#define FTM_WR_STATUS_CH6F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH6F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH6F(value)))
+#define FTM_BWR_STATUS_CH6F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH6F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH7F[7] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH7F field. */
+#define FTM_RD_STATUS_CH7F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH7F_MASK) >> FTM_STATUS_CH7F_SHIFT)
+#define FTM_BRD_STATUS_CH7F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH7F_SHIFT))
+
+/*! @brief Set the CH7F field to a new value. */
+#define FTM_WR_STATUS_CH7F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH7F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK), FTM_STATUS_CH7F(value)))
+#define FTM_BWR_STATUS_CH7F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH7F_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_MODE - Features Mode Selection
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_MODE - Features Mode Selection (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * This register contains the global enable bit for FTM-specific features and
+ * the control bits used to configure: Fault control mode and interrupt Capture
+ * Test mode PWM synchronization Write protection Channel output initialization
+ * These controls relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire FTM_MODE register
+ */
+/*@{*/
+#define FTM_RD_MODE(base)        (FTM_MODE_REG(base))
+#define FTM_WR_MODE(base, value) (FTM_MODE_REG(base) = (value))
+#define FTM_RMW_MODE(base, mask, value) (FTM_WR_MODE(base, (FTM_RD_MODE(base) & ~(mask)) | (value)))
+#define FTM_SET_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) |  (value)))
+#define FTM_CLR_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) & ~(value)))
+#define FTM_TOG_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_MODE bitfields
+ */
+
+/*!
+ * @name Register FTM_MODE, field FTMEN[0] (RW)
+ *
+ * This field is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Only the TPM-compatible registers (first set of registers) can be
+ *     used without any restriction. Do not use the FTM-specific registers.
+ * - 0b1 - All registers including the FTM-specific registers (second set of
+ *     registers) are available for use with no restrictions.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FTMEN field. */
+#define FTM_RD_MODE_FTMEN(base) ((FTM_MODE_REG(base) & FTM_MODE_FTMEN_MASK) >> FTM_MODE_FTMEN_SHIFT)
+#define FTM_BRD_MODE_FTMEN(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FTMEN_SHIFT))
+
+/*! @brief Set the FTMEN field to a new value. */
+#define FTM_WR_MODE_FTMEN(base, value) (FTM_RMW_MODE(base, FTM_MODE_FTMEN_MASK, FTM_MODE_FTMEN(value)))
+#define FTM_BWR_MODE_FTMEN(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FTMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field INIT[1] (RW)
+ *
+ * When a 1 is written to INIT bit the channels output is initialized according
+ * to the state of their corresponding bit in the OUTINIT register. Writing a 0
+ * to INIT bit has no effect. The INIT bit is always read as 0.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_INIT field. */
+#define FTM_RD_MODE_INIT(base) ((FTM_MODE_REG(base) & FTM_MODE_INIT_MASK) >> FTM_MODE_INIT_SHIFT)
+#define FTM_BRD_MODE_INIT(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_INIT_SHIFT))
+
+/*! @brief Set the INIT field to a new value. */
+#define FTM_WR_MODE_INIT(base, value) (FTM_RMW_MODE(base, FTM_MODE_INIT_MASK, FTM_MODE_INIT(value)))
+#define FTM_BWR_MODE_INIT(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_INIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field WPDIS[2] (RW)
+ *
+ * When write protection is enabled (WPDIS = 0), write protected bits cannot be
+ * written. When write protection is disabled (WPDIS = 1), write protected bits
+ * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
+ * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
+ * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
+ *
+ * Values:
+ * - 0b0 - Write protection is enabled.
+ * - 0b1 - Write protection is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_WPDIS field. */
+#define FTM_RD_MODE_WPDIS(base) ((FTM_MODE_REG(base) & FTM_MODE_WPDIS_MASK) >> FTM_MODE_WPDIS_SHIFT)
+#define FTM_BRD_MODE_WPDIS(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_WPDIS_SHIFT))
+
+/*! @brief Set the WPDIS field to a new value. */
+#define FTM_WR_MODE_WPDIS(base, value) (FTM_RMW_MODE(base, FTM_MODE_WPDIS_MASK, FTM_MODE_WPDIS(value)))
+#define FTM_BWR_MODE_WPDIS(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_WPDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field PWMSYNC[3] (RW)
+ *
+ * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
+ * synchronization. See PWM synchronization. The PWMSYNC bit configures the
+ * synchronization when SYNCMODE is 0.
+ *
+ * Values:
+ * - 0b0 - No restrictions. Software and hardware triggers can be used by MOD,
+ *     CnV, OUTMASK, and FTM counter synchronization.
+ * - 0b1 - Software trigger can only be used by MOD and CnV synchronization, and
+ *     hardware triggers can only be used by OUTMASK and FTM counter
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_PWMSYNC field. */
+#define FTM_RD_MODE_PWMSYNC(base) ((FTM_MODE_REG(base) & FTM_MODE_PWMSYNC_MASK) >> FTM_MODE_PWMSYNC_SHIFT)
+#define FTM_BRD_MODE_PWMSYNC(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_PWMSYNC_SHIFT))
+
+/*! @brief Set the PWMSYNC field to a new value. */
+#define FTM_WR_MODE_PWMSYNC(base, value) (FTM_RMW_MODE(base, FTM_MODE_PWMSYNC_MASK, FTM_MODE_PWMSYNC(value)))
+#define FTM_BWR_MODE_PWMSYNC(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_PWMSYNC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field CAPTEST[4] (RW)
+ *
+ * Enables the capture test mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Capture test mode is disabled.
+ * - 0b1 - Capture test mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_CAPTEST field. */
+#define FTM_RD_MODE_CAPTEST(base) ((FTM_MODE_REG(base) & FTM_MODE_CAPTEST_MASK) >> FTM_MODE_CAPTEST_SHIFT)
+#define FTM_BRD_MODE_CAPTEST(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_CAPTEST_SHIFT))
+
+/*! @brief Set the CAPTEST field to a new value. */
+#define FTM_WR_MODE_CAPTEST(base, value) (FTM_RMW_MODE(base, FTM_MODE_CAPTEST_MASK, FTM_MODE_CAPTEST(value)))
+#define FTM_BWR_MODE_CAPTEST(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_CAPTEST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field FAULTM[6:5] (RW)
+ *
+ * Defines the FTM fault control mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b00 - Fault control is disabled for all channels.
+ * - 0b01 - Fault control is enabled for even channels only (channels 0, 2, 4,
+ *     and 6), and the selected mode is the manual fault clearing.
+ * - 0b10 - Fault control is enabled for all channels, and the selected mode is
+ *     the manual fault clearing.
+ * - 0b11 - Fault control is enabled for all channels, and the selected mode is
+ *     the automatic fault clearing.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FAULTM field. */
+#define FTM_RD_MODE_FAULTM(base) ((FTM_MODE_REG(base) & FTM_MODE_FAULTM_MASK) >> FTM_MODE_FAULTM_SHIFT)
+#define FTM_BRD_MODE_FAULTM(base) (FTM_RD_MODE_FAULTM(base))
+
+/*! @brief Set the FAULTM field to a new value. */
+#define FTM_WR_MODE_FAULTM(base, value) (FTM_RMW_MODE(base, FTM_MODE_FAULTM_MASK, FTM_MODE_FAULTM(value)))
+#define FTM_BWR_MODE_FAULTM(base, value) (FTM_WR_MODE_FAULTM(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field FAULTIE[7] (RW)
+ *
+ * Enables the generation of an interrupt when a fault is detected by FTM and
+ * the FTM fault control is enabled.
+ *
+ * Values:
+ * - 0b0 - Fault control interrupt is disabled.
+ * - 0b1 - Fault control interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FAULTIE field. */
+#define FTM_RD_MODE_FAULTIE(base) ((FTM_MODE_REG(base) & FTM_MODE_FAULTIE_MASK) >> FTM_MODE_FAULTIE_SHIFT)
+#define FTM_BRD_MODE_FAULTIE(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FAULTIE_SHIFT))
+
+/*! @brief Set the FAULTIE field to a new value. */
+#define FTM_WR_MODE_FAULTIE(base, value) (FTM_RMW_MODE(base, FTM_MODE_FAULTIE_MASK, FTM_MODE_FAULTIE(value)))
+#define FTM_BWR_MODE_FAULTIE(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FAULTIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SYNC - Synchronization
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SYNC - Synchronization (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the PWM synchronization. A synchronization event can
+ * perform the synchronized update of MOD, CV, and OUTMASK registers with the
+ * value of their write buffer and the FTM counter initialization. The software
+ * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
+ * potential conflict if used together when SYNCMODE = 0. Use only hardware or
+ * software triggers but not both at the same time, otherwise unpredictable behavior
+ * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
+ * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
+ * all enabled channels simultaneously. The use of the loading point selection
+ * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
+ * bits, is likely to result in unpredictable behavior. The synchronization
+ * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
+ * register) bits. See PWM synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SYNC register
+ */
+/*@{*/
+#define FTM_RD_SYNC(base)        (FTM_SYNC_REG(base))
+#define FTM_WR_SYNC(base, value) (FTM_SYNC_REG(base) = (value))
+#define FTM_RMW_SYNC(base, mask, value) (FTM_WR_SYNC(base, (FTM_RD_SYNC(base) & ~(mask)) | (value)))
+#define FTM_SET_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) |  (value)))
+#define FTM_CLR_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) & ~(value)))
+#define FTM_TOG_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SYNC bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNC, field CNTMIN[0] (RW)
+ *
+ * Selects the minimum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMIN is one, the selected loading point is when the
+ * FTM counter reaches its minimum value (CNTIN register).
+ *
+ * Values:
+ * - 0b0 - The minimum loading point is disabled.
+ * - 0b1 - The minimum loading point is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_CNTMIN field. */
+#define FTM_RD_SYNC_CNTMIN(base) ((FTM_SYNC_REG(base) & FTM_SYNC_CNTMIN_MASK) >> FTM_SYNC_CNTMIN_SHIFT)
+#define FTM_BRD_SYNC_CNTMIN(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMIN_SHIFT))
+
+/*! @brief Set the CNTMIN field to a new value. */
+#define FTM_WR_SYNC_CNTMIN(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_CNTMIN_MASK, FTM_SYNC_CNTMIN(value)))
+#define FTM_BWR_SYNC_CNTMIN(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMIN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field CNTMAX[1] (RW)
+ *
+ * Selects the maximum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
+ * counter reaches its maximum value (MOD register).
+ *
+ * Values:
+ * - 0b0 - The maximum loading point is disabled.
+ * - 0b1 - The maximum loading point is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_CNTMAX field. */
+#define FTM_RD_SYNC_CNTMAX(base) ((FTM_SYNC_REG(base) & FTM_SYNC_CNTMAX_MASK) >> FTM_SYNC_CNTMAX_SHIFT)
+#define FTM_BRD_SYNC_CNTMAX(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMAX_SHIFT))
+
+/*! @brief Set the CNTMAX field to a new value. */
+#define FTM_WR_SYNC_CNTMAX(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_CNTMAX_MASK, FTM_SYNC_CNTMAX(value)))
+#define FTM_BWR_SYNC_CNTMAX(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMAX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field REINIT[2] (RW)
+ *
+ * Determines if the FTM counter is reinitialized when the selected trigger for
+ * the synchronization is detected. The REINIT bit configures the synchronization
+ * when SYNCMODE is zero.
+ *
+ * Values:
+ * - 0b0 - FTM counter continues to count normally.
+ * - 0b1 - FTM counter is updated with its initial value when the selected
+ *     trigger is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_REINIT field. */
+#define FTM_RD_SYNC_REINIT(base) ((FTM_SYNC_REG(base) & FTM_SYNC_REINIT_MASK) >> FTM_SYNC_REINIT_SHIFT)
+#define FTM_BRD_SYNC_REINIT(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_REINIT_SHIFT))
+
+/*! @brief Set the REINIT field to a new value. */
+#define FTM_WR_SYNC_REINIT(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_REINIT_MASK, FTM_SYNC_REINIT(value)))
+#define FTM_BWR_SYNC_REINIT(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_REINIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
+ *
+ * Selects when the OUTMASK register is updated with the value of its buffer.
+ *
+ * Values:
+ * - 0b0 - OUTMASK register is updated with the value of its buffer in all
+ *     rising edges of the system clock.
+ * - 0b1 - OUTMASK register is updated with the value of its buffer only by the
+ *     PWM synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */
+#define FTM_RD_SYNC_SYNCHOM(base) ((FTM_SYNC_REG(base) & FTM_SYNC_SYNCHOM_MASK) >> FTM_SYNC_SYNCHOM_SHIFT)
+#define FTM_BRD_SYNC_SYNCHOM(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SYNCHOM_SHIFT))
+
+/*! @brief Set the SYNCHOM field to a new value. */
+#define FTM_WR_SYNC_SYNCHOM(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_SYNCHOM_MASK, FTM_SYNC_SYNCHOM(value)))
+#define FTM_BWR_SYNC_SYNCHOM(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SYNCHOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG0[4] (RW)
+ *
+ * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
+ * occurs when a rising edge is detected at the trigger 0 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG0 field. */
+#define FTM_RD_SYNC_TRIG0(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG0_MASK) >> FTM_SYNC_TRIG0_SHIFT)
+#define FTM_BRD_SYNC_TRIG0(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG0_SHIFT))
+
+/*! @brief Set the TRIG0 field to a new value. */
+#define FTM_WR_SYNC_TRIG0(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG0_MASK, FTM_SYNC_TRIG0(value)))
+#define FTM_BWR_SYNC_TRIG0(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG1[5] (RW)
+ *
+ * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
+ * happens when a rising edge is detected at the trigger 1 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG1 field. */
+#define FTM_RD_SYNC_TRIG1(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG1_MASK) >> FTM_SYNC_TRIG1_SHIFT)
+#define FTM_BRD_SYNC_TRIG1(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG1_SHIFT))
+
+/*! @brief Set the TRIG1 field to a new value. */
+#define FTM_WR_SYNC_TRIG1(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG1_MASK, FTM_SYNC_TRIG1(value)))
+#define FTM_BWR_SYNC_TRIG1(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG2[6] (RW)
+ *
+ * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
+ * happens when a rising edge is detected at the trigger 2 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG2 field. */
+#define FTM_RD_SYNC_TRIG2(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG2_MASK) >> FTM_SYNC_TRIG2_SHIFT)
+#define FTM_BRD_SYNC_TRIG2(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG2_SHIFT))
+
+/*! @brief Set the TRIG2 field to a new value. */
+#define FTM_WR_SYNC_TRIG2(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG2_MASK, FTM_SYNC_TRIG2(value)))
+#define FTM_BWR_SYNC_TRIG2(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field SWSYNC[7] (RW)
+ *
+ * Selects the software trigger as the PWM synchronization trigger. The software
+ * trigger happens when a 1 is written to SWSYNC bit.
+ *
+ * Values:
+ * - 0b0 - Software trigger is not selected.
+ * - 0b1 - Software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_SWSYNC field. */
+#define FTM_RD_SYNC_SWSYNC(base) ((FTM_SYNC_REG(base) & FTM_SYNC_SWSYNC_MASK) >> FTM_SYNC_SWSYNC_SHIFT)
+#define FTM_BRD_SYNC_SWSYNC(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SWSYNC_SHIFT))
+
+/*! @brief Set the SWSYNC field to a new value. */
+#define FTM_WR_SYNC_SWSYNC(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_SWSYNC_MASK, FTM_SYNC_SWSYNC(value)))
+#define FTM_BWR_SYNC_SWSYNC(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SWSYNC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_OUTINIT - Initial State For Channels Output
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_OUTINIT - Initial State For Channels Output (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire FTM_OUTINIT register
+ */
+/*@{*/
+#define FTM_RD_OUTINIT(base)     (FTM_OUTINIT_REG(base))
+#define FTM_WR_OUTINIT(base, value) (FTM_OUTINIT_REG(base) = (value))
+#define FTM_RMW_OUTINIT(base, mask, value) (FTM_WR_OUTINIT(base, (FTM_RD_OUTINIT(base) & ~(mask)) | (value)))
+#define FTM_SET_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) |  (value)))
+#define FTM_CLR_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) & ~(value)))
+#define FTM_TOG_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_OUTINIT bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */
+#define FTM_RD_OUTINIT_CH0OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH0OI_MASK) >> FTM_OUTINIT_CH0OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH0OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH0OI_SHIFT))
+
+/*! @brief Set the CH0OI field to a new value. */
+#define FTM_WR_OUTINIT_CH0OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH0OI_MASK, FTM_OUTINIT_CH0OI(value)))
+#define FTM_BWR_OUTINIT_CH0OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH0OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */
+#define FTM_RD_OUTINIT_CH1OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH1OI_MASK) >> FTM_OUTINIT_CH1OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH1OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH1OI_SHIFT))
+
+/*! @brief Set the CH1OI field to a new value. */
+#define FTM_WR_OUTINIT_CH1OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH1OI_MASK, FTM_OUTINIT_CH1OI(value)))
+#define FTM_BWR_OUTINIT_CH1OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH1OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */
+#define FTM_RD_OUTINIT_CH2OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH2OI_MASK) >> FTM_OUTINIT_CH2OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH2OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH2OI_SHIFT))
+
+/*! @brief Set the CH2OI field to a new value. */
+#define FTM_WR_OUTINIT_CH2OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH2OI_MASK, FTM_OUTINIT_CH2OI(value)))
+#define FTM_BWR_OUTINIT_CH2OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH2OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */
+#define FTM_RD_OUTINIT_CH3OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH3OI_MASK) >> FTM_OUTINIT_CH3OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH3OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH3OI_SHIFT))
+
+/*! @brief Set the CH3OI field to a new value. */
+#define FTM_WR_OUTINIT_CH3OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH3OI_MASK, FTM_OUTINIT_CH3OI(value)))
+#define FTM_BWR_OUTINIT_CH3OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH3OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */
+#define FTM_RD_OUTINIT_CH4OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH4OI_MASK) >> FTM_OUTINIT_CH4OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH4OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH4OI_SHIFT))
+
+/*! @brief Set the CH4OI field to a new value. */
+#define FTM_WR_OUTINIT_CH4OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH4OI_MASK, FTM_OUTINIT_CH4OI(value)))
+#define FTM_BWR_OUTINIT_CH4OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH4OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */
+#define FTM_RD_OUTINIT_CH5OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH5OI_MASK) >> FTM_OUTINIT_CH5OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH5OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH5OI_SHIFT))
+
+/*! @brief Set the CH5OI field to a new value. */
+#define FTM_WR_OUTINIT_CH5OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH5OI_MASK, FTM_OUTINIT_CH5OI(value)))
+#define FTM_BWR_OUTINIT_CH5OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH5OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */
+#define FTM_RD_OUTINIT_CH6OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH6OI_MASK) >> FTM_OUTINIT_CH6OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH6OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH6OI_SHIFT))
+
+/*! @brief Set the CH6OI field to a new value. */
+#define FTM_WR_OUTINIT_CH6OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH6OI_MASK, FTM_OUTINIT_CH6OI(value)))
+#define FTM_BWR_OUTINIT_CH6OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH6OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */
+#define FTM_RD_OUTINIT_CH7OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH7OI_MASK) >> FTM_OUTINIT_CH7OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH7OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH7OI_SHIFT))
+
+/*! @brief Set the CH7OI field to a new value. */
+#define FTM_WR_OUTINIT_CH7OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH7OI_MASK, FTM_OUTINIT_CH7OI(value)))
+#define FTM_BWR_OUTINIT_CH7OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH7OI_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_OUTMASK - Output Mask
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_OUTMASK - Output Mask (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides a mask for each FTM channel. The mask of a channel
+ * determines if its output responds, that is, it is masked or not, when a match
+ * occurs. This feature is used for BLDC control where the PWM signal is presented
+ * to an electric motor at specific times to provide electronic commutation. Any
+ * write to the OUTMASK register, stores the value in its write buffer. The
+ * register is updated with the value of its write buffer according to PWM
+ * synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_OUTMASK register
+ */
+/*@{*/
+#define FTM_RD_OUTMASK(base)     (FTM_OUTMASK_REG(base))
+#define FTM_WR_OUTMASK(base, value) (FTM_OUTMASK_REG(base) = (value))
+#define FTM_RMW_OUTMASK(base, mask, value) (FTM_WR_OUTMASK(base, (FTM_RD_OUTMASK(base) & ~(mask)) | (value)))
+#define FTM_SET_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) |  (value)))
+#define FTM_CLR_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) & ~(value)))
+#define FTM_TOG_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_OUTMASK bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */
+#define FTM_RD_OUTMASK_CH0OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH0OM_MASK) >> FTM_OUTMASK_CH0OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH0OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH0OM_SHIFT))
+
+/*! @brief Set the CH0OM field to a new value. */
+#define FTM_WR_OUTMASK_CH0OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH0OM_MASK, FTM_OUTMASK_CH0OM(value)))
+#define FTM_BWR_OUTMASK_CH0OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH0OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */
+#define FTM_RD_OUTMASK_CH1OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH1OM_MASK) >> FTM_OUTMASK_CH1OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH1OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH1OM_SHIFT))
+
+/*! @brief Set the CH1OM field to a new value. */
+#define FTM_WR_OUTMASK_CH1OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH1OM_MASK, FTM_OUTMASK_CH1OM(value)))
+#define FTM_BWR_OUTMASK_CH1OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH1OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */
+#define FTM_RD_OUTMASK_CH2OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH2OM_MASK) >> FTM_OUTMASK_CH2OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH2OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH2OM_SHIFT))
+
+/*! @brief Set the CH2OM field to a new value. */
+#define FTM_WR_OUTMASK_CH2OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH2OM_MASK, FTM_OUTMASK_CH2OM(value)))
+#define FTM_BWR_OUTMASK_CH2OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH2OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */
+#define FTM_RD_OUTMASK_CH3OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH3OM_MASK) >> FTM_OUTMASK_CH3OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH3OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH3OM_SHIFT))
+
+/*! @brief Set the CH3OM field to a new value. */
+#define FTM_WR_OUTMASK_CH3OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH3OM_MASK, FTM_OUTMASK_CH3OM(value)))
+#define FTM_BWR_OUTMASK_CH3OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH3OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */
+#define FTM_RD_OUTMASK_CH4OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH4OM_MASK) >> FTM_OUTMASK_CH4OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH4OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH4OM_SHIFT))
+
+/*! @brief Set the CH4OM field to a new value. */
+#define FTM_WR_OUTMASK_CH4OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH4OM_MASK, FTM_OUTMASK_CH4OM(value)))
+#define FTM_BWR_OUTMASK_CH4OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH4OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */
+#define FTM_RD_OUTMASK_CH5OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH5OM_MASK) >> FTM_OUTMASK_CH5OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH5OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH5OM_SHIFT))
+
+/*! @brief Set the CH5OM field to a new value. */
+#define FTM_WR_OUTMASK_CH5OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH5OM_MASK, FTM_OUTMASK_CH5OM(value)))
+#define FTM_BWR_OUTMASK_CH5OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH5OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */
+#define FTM_RD_OUTMASK_CH6OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH6OM_MASK) >> FTM_OUTMASK_CH6OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH6OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH6OM_SHIFT))
+
+/*! @brief Set the CH6OM field to a new value. */
+#define FTM_WR_OUTMASK_CH6OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH6OM_MASK, FTM_OUTMASK_CH6OM(value)))
+#define FTM_BWR_OUTMASK_CH6OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH6OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */
+#define FTM_RD_OUTMASK_CH7OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH7OM_MASK) >> FTM_OUTMASK_CH7OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH7OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH7OM_SHIFT))
+
+/*! @brief Set the CH7OM field to a new value. */
+#define FTM_WR_OUTMASK_CH7OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH7OM_MASK, FTM_OUTMASK_CH7OM(value)))
+#define FTM_BWR_OUTMASK_CH7OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH7OM_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_COMBINE - Function For Linked Channels
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_COMBINE - Function For Linked Channels (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the control bits used to configure the fault control,
+ * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
+ * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
+ * 4, and 6.
+ */
+/*!
+ * @name Constants and macros for entire FTM_COMBINE register
+ */
+/*@{*/
+#define FTM_RD_COMBINE(base)     (FTM_COMBINE_REG(base))
+#define FTM_WR_COMBINE(base, value) (FTM_COMBINE_REG(base) = (value))
+#define FTM_RMW_COMBINE(base, mask, value) (FTM_WR_COMBINE(base, (FTM_RD_COMBINE(base) & ~(mask)) | (value)))
+#define FTM_SET_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) |  (value)))
+#define FTM_CLR_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) & ~(value)))
+#define FTM_TOG_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_COMBINE bitfields
+ */
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */
+#define FTM_RD_COMBINE_COMBINE0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE0_MASK) >> FTM_COMBINE_COMBINE0_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE0_SHIFT))
+
+/*! @brief Set the COMBINE0 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE0_MASK, FTM_COMBINE_COMBINE0(value)))
+#define FTM_BWR_COMBINE_COMBINE0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP0[1] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP0 field. */
+#define FTM_RD_COMBINE_COMP0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP0_MASK) >> FTM_COMBINE_COMP0_SHIFT)
+#define FTM_BRD_COMBINE_COMP0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP0_SHIFT))
+
+/*! @brief Set the COMP0 field to a new value. */
+#define FTM_WR_COMBINE_COMP0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP0_MASK, FTM_COMBINE_COMP0(value)))
+#define FTM_BWR_COMBINE_COMP0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */
+#define FTM_RD_COMBINE_DECAPEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN0_MASK) >> FTM_COMBINE_DECAPEN0_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN0_SHIFT))
+
+/*! @brief Set the DECAPEN0 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN0_MASK, FTM_COMBINE_DECAPEN0(value)))
+#define FTM_BWR_COMBINE_DECAPEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP0[3] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */
+#define FTM_RD_COMBINE_DECAP0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP0_MASK) >> FTM_COMBINE_DECAP0_SHIFT)
+#define FTM_BRD_COMBINE_DECAP0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP0_SHIFT))
+
+/*! @brief Set the DECAP0 field to a new value. */
+#define FTM_WR_COMBINE_DECAP0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP0_MASK, FTM_COMBINE_DECAP0(value)))
+#define FTM_BWR_COMBINE_DECAP0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN0[4] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */
+#define FTM_RD_COMBINE_DTEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN0_MASK) >> FTM_COMBINE_DTEN0_SHIFT)
+#define FTM_BRD_COMBINE_DTEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN0_SHIFT))
+
+/*! @brief Set the DTEN0 field to a new value. */
+#define FTM_WR_COMBINE_DTEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN0_MASK, FTM_COMBINE_DTEN0(value)))
+#define FTM_BWR_COMBINE_DTEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */
+#define FTM_RD_COMBINE_SYNCEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN0_MASK) >> FTM_COMBINE_SYNCEN0_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN0_SHIFT))
+
+/*! @brief Set the SYNCEN0 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN0_MASK, FTM_COMBINE_SYNCEN0(value)))
+#define FTM_BWR_COMBINE_SYNCEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */
+#define FTM_RD_COMBINE_FAULTEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN0_MASK) >> FTM_COMBINE_FAULTEN0_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN0_SHIFT))
+
+/*! @brief Set the FAULTEN0 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN0_MASK, FTM_COMBINE_FAULTEN0(value)))
+#define FTM_BWR_COMBINE_FAULTEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */
+#define FTM_RD_COMBINE_COMBINE1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE1_MASK) >> FTM_COMBINE_COMBINE1_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE1_SHIFT))
+
+/*! @brief Set the COMBINE1 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE1_MASK, FTM_COMBINE_COMBINE1(value)))
+#define FTM_BWR_COMBINE_COMBINE1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP1[9] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP1 field. */
+#define FTM_RD_COMBINE_COMP1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP1_MASK) >> FTM_COMBINE_COMP1_SHIFT)
+#define FTM_BRD_COMBINE_COMP1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP1_SHIFT))
+
+/*! @brief Set the COMP1 field to a new value. */
+#define FTM_WR_COMBINE_COMP1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP1_MASK, FTM_COMBINE_COMP1(value)))
+#define FTM_BWR_COMBINE_COMP1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */
+#define FTM_RD_COMBINE_DECAPEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN1_MASK) >> FTM_COMBINE_DECAPEN1_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN1_SHIFT))
+
+/*! @brief Set the DECAPEN1 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN1_MASK, FTM_COMBINE_DECAPEN1(value)))
+#define FTM_BWR_COMBINE_DECAPEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP1[11] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */
+#define FTM_RD_COMBINE_DECAP1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP1_MASK) >> FTM_COMBINE_DECAP1_SHIFT)
+#define FTM_BRD_COMBINE_DECAP1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP1_SHIFT))
+
+/*! @brief Set the DECAP1 field to a new value. */
+#define FTM_WR_COMBINE_DECAP1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP1_MASK, FTM_COMBINE_DECAP1(value)))
+#define FTM_BWR_COMBINE_DECAP1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN1[12] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */
+#define FTM_RD_COMBINE_DTEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN1_MASK) >> FTM_COMBINE_DTEN1_SHIFT)
+#define FTM_BRD_COMBINE_DTEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN1_SHIFT))
+
+/*! @brief Set the DTEN1 field to a new value. */
+#define FTM_WR_COMBINE_DTEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN1_MASK, FTM_COMBINE_DTEN1(value)))
+#define FTM_BWR_COMBINE_DTEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */
+#define FTM_RD_COMBINE_SYNCEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN1_MASK) >> FTM_COMBINE_SYNCEN1_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN1_SHIFT))
+
+/*! @brief Set the SYNCEN1 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN1_MASK, FTM_COMBINE_SYNCEN1(value)))
+#define FTM_BWR_COMBINE_SYNCEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */
+#define FTM_RD_COMBINE_FAULTEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN1_MASK) >> FTM_COMBINE_FAULTEN1_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN1_SHIFT))
+
+/*! @brief Set the FAULTEN1 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN1_MASK, FTM_COMBINE_FAULTEN1(value)))
+#define FTM_BWR_COMBINE_FAULTEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */
+#define FTM_RD_COMBINE_COMBINE2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE2_MASK) >> FTM_COMBINE_COMBINE2_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE2_SHIFT))
+
+/*! @brief Set the COMBINE2 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE2_MASK, FTM_COMBINE_COMBINE2(value)))
+#define FTM_BWR_COMBINE_COMBINE2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP2[17] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP2 field. */
+#define FTM_RD_COMBINE_COMP2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP2_MASK) >> FTM_COMBINE_COMP2_SHIFT)
+#define FTM_BRD_COMBINE_COMP2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP2_SHIFT))
+
+/*! @brief Set the COMP2 field to a new value. */
+#define FTM_WR_COMBINE_COMP2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP2_MASK, FTM_COMBINE_COMP2(value)))
+#define FTM_BWR_COMBINE_COMP2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */
+#define FTM_RD_COMBINE_DECAPEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN2_MASK) >> FTM_COMBINE_DECAPEN2_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN2_SHIFT))
+
+/*! @brief Set the DECAPEN2 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN2_MASK, FTM_COMBINE_DECAPEN2(value)))
+#define FTM_BWR_COMBINE_DECAPEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP2[19] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */
+#define FTM_RD_COMBINE_DECAP2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP2_MASK) >> FTM_COMBINE_DECAP2_SHIFT)
+#define FTM_BRD_COMBINE_DECAP2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP2_SHIFT))
+
+/*! @brief Set the DECAP2 field to a new value. */
+#define FTM_WR_COMBINE_DECAP2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP2_MASK, FTM_COMBINE_DECAP2(value)))
+#define FTM_BWR_COMBINE_DECAP2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN2[20] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */
+#define FTM_RD_COMBINE_DTEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN2_MASK) >> FTM_COMBINE_DTEN2_SHIFT)
+#define FTM_BRD_COMBINE_DTEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN2_SHIFT))
+
+/*! @brief Set the DTEN2 field to a new value. */
+#define FTM_WR_COMBINE_DTEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN2_MASK, FTM_COMBINE_DTEN2(value)))
+#define FTM_BWR_COMBINE_DTEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */
+#define FTM_RD_COMBINE_SYNCEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN2_MASK) >> FTM_COMBINE_SYNCEN2_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN2_SHIFT))
+
+/*! @brief Set the SYNCEN2 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN2_MASK, FTM_COMBINE_SYNCEN2(value)))
+#define FTM_BWR_COMBINE_SYNCEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */
+#define FTM_RD_COMBINE_FAULTEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN2_MASK) >> FTM_COMBINE_FAULTEN2_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN2_SHIFT))
+
+/*! @brief Set the FAULTEN2 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN2_MASK, FTM_COMBINE_FAULTEN2(value)))
+#define FTM_BWR_COMBINE_FAULTEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */
+#define FTM_RD_COMBINE_COMBINE3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE3_MASK) >> FTM_COMBINE_COMBINE3_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE3_SHIFT))
+
+/*! @brief Set the COMBINE3 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE3_MASK, FTM_COMBINE_COMBINE3(value)))
+#define FTM_BWR_COMBINE_COMBINE3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP3[25] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP3 field. */
+#define FTM_RD_COMBINE_COMP3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP3_MASK) >> FTM_COMBINE_COMP3_SHIFT)
+#define FTM_BRD_COMBINE_COMP3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP3_SHIFT))
+
+/*! @brief Set the COMP3 field to a new value. */
+#define FTM_WR_COMBINE_COMP3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP3_MASK, FTM_COMBINE_COMP3(value)))
+#define FTM_BWR_COMBINE_COMP3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */
+#define FTM_RD_COMBINE_DECAPEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN3_MASK) >> FTM_COMBINE_DECAPEN3_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN3_SHIFT))
+
+/*! @brief Set the DECAPEN3 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN3_MASK, FTM_COMBINE_DECAPEN3(value)))
+#define FTM_BWR_COMBINE_DECAPEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP3[27] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */
+#define FTM_RD_COMBINE_DECAP3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP3_MASK) >> FTM_COMBINE_DECAP3_SHIFT)
+#define FTM_BRD_COMBINE_DECAP3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP3_SHIFT))
+
+/*! @brief Set the DECAP3 field to a new value. */
+#define FTM_WR_COMBINE_DECAP3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP3_MASK, FTM_COMBINE_DECAP3(value)))
+#define FTM_BWR_COMBINE_DECAP3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN3[28] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */
+#define FTM_RD_COMBINE_DTEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN3_MASK) >> FTM_COMBINE_DTEN3_SHIFT)
+#define FTM_BRD_COMBINE_DTEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN3_SHIFT))
+
+/*! @brief Set the DTEN3 field to a new value. */
+#define FTM_WR_COMBINE_DTEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN3_MASK, FTM_COMBINE_DTEN3(value)))
+#define FTM_BWR_COMBINE_DTEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */
+#define FTM_RD_COMBINE_SYNCEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN3_MASK) >> FTM_COMBINE_SYNCEN3_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN3_SHIFT))
+
+/*! @brief Set the SYNCEN3 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN3_MASK, FTM_COMBINE_SYNCEN3(value)))
+#define FTM_BWR_COMBINE_SYNCEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */
+#define FTM_RD_COMBINE_FAULTEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN3_MASK) >> FTM_COMBINE_FAULTEN3_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN3_SHIFT))
+
+/*! @brief Set the FAULTEN3 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN3_MASK, FTM_COMBINE_FAULTEN3(value)))
+#define FTM_BWR_COMBINE_FAULTEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN3_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_DEADTIME - Deadtime Insertion Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_DEADTIME - Deadtime Insertion Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the deadtime prescaler factor and deadtime value. All
+ * FTM channels use this clock prescaler and this deadtime value for the deadtime
+ * insertion.
+ */
+/*!
+ * @name Constants and macros for entire FTM_DEADTIME register
+ */
+/*@{*/
+#define FTM_RD_DEADTIME(base)    (FTM_DEADTIME_REG(base))
+#define FTM_WR_DEADTIME(base, value) (FTM_DEADTIME_REG(base) = (value))
+#define FTM_RMW_DEADTIME(base, mask, value) (FTM_WR_DEADTIME(base, (FTM_RD_DEADTIME(base) & ~(mask)) | (value)))
+#define FTM_SET_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) |  (value)))
+#define FTM_CLR_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) & ~(value)))
+#define FTM_TOG_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_DEADTIME bitfields
+ */
+
+/*!
+ * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
+ *
+ * Selects the deadtime insertion value for the deadtime counter. The deadtime
+ * counter is clocked by a scaled version of the system clock. See the description
+ * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
+ * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
+ * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
+ * This pattern continues up to a possible 63 counts. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */
+#define FTM_RD_DEADTIME_DTVAL(base) ((FTM_DEADTIME_REG(base) & FTM_DEADTIME_DTVAL_MASK) >> FTM_DEADTIME_DTVAL_SHIFT)
+#define FTM_BRD_DEADTIME_DTVAL(base) (FTM_RD_DEADTIME_DTVAL(base))
+
+/*! @brief Set the DTVAL field to a new value. */
+#define FTM_WR_DEADTIME_DTVAL(base, value) (FTM_RMW_DEADTIME(base, FTM_DEADTIME_DTVAL_MASK, FTM_DEADTIME_DTVAL(value)))
+#define FTM_BWR_DEADTIME_DTVAL(base, value) (FTM_WR_DEADTIME_DTVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
+ *
+ * Selects the division factor of the system clock. This prescaled clock is used
+ * by the deadtime counter. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0x - Divide the system clock by 1.
+ * - 0b10 - Divide the system clock by 4.
+ * - 0b11 - Divide the system clock by 16.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_DEADTIME_DTPS field. */
+#define FTM_RD_DEADTIME_DTPS(base) ((FTM_DEADTIME_REG(base) & FTM_DEADTIME_DTPS_MASK) >> FTM_DEADTIME_DTPS_SHIFT)
+#define FTM_BRD_DEADTIME_DTPS(base) (FTM_RD_DEADTIME_DTPS(base))
+
+/*! @brief Set the DTPS field to a new value. */
+#define FTM_WR_DEADTIME_DTPS(base, value) (FTM_RMW_DEADTIME(base, FTM_DEADTIME_DTPS_MASK, FTM_DEADTIME_DTPS(value)))
+#define FTM_BWR_DEADTIME_DTPS(base, value) (FTM_WR_DEADTIME_DTPS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_EXTTRIG - FTM External Trigger
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_EXTTRIG - FTM External Trigger (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register: Indicates when a channel trigger was generated Enables the
+ * generation of a trigger when the FTM counter is equal to its initial value
+ * Selects which channels are used in the generation of the channel triggers Several
+ * channels can be selected to generate multiple triggers in one PWM period.
+ * Channels 6 and 7 are not used to generate channel triggers.
+ */
+/*!
+ * @name Constants and macros for entire FTM_EXTTRIG register
+ */
+/*@{*/
+#define FTM_RD_EXTTRIG(base)     (FTM_EXTTRIG_REG(base))
+#define FTM_WR_EXTTRIG(base, value) (FTM_EXTTRIG_REG(base) = (value))
+#define FTM_RMW_EXTTRIG(base, mask, value) (FTM_WR_EXTTRIG(base, (FTM_RD_EXTTRIG(base) & ~(mask)) | (value)))
+#define FTM_SET_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) |  (value)))
+#define FTM_CLR_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) & ~(value)))
+#define FTM_TOG_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_EXTTRIG bitfields
+ */
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */
+#define FTM_RD_EXTTRIG_CH2TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH2TRIG_MASK) >> FTM_EXTTRIG_CH2TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH2TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH2TRIG_SHIFT))
+
+/*! @brief Set the CH2TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH2TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH2TRIG_MASK, FTM_EXTTRIG_CH2TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH2TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH2TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */
+#define FTM_RD_EXTTRIG_CH3TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH3TRIG_MASK) >> FTM_EXTTRIG_CH3TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH3TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH3TRIG_SHIFT))
+
+/*! @brief Set the CH3TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH3TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH3TRIG_MASK, FTM_EXTTRIG_CH3TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH3TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH3TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */
+#define FTM_RD_EXTTRIG_CH4TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH4TRIG_MASK) >> FTM_EXTTRIG_CH4TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH4TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH4TRIG_SHIFT))
+
+/*! @brief Set the CH4TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH4TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH4TRIG_MASK, FTM_EXTTRIG_CH4TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH4TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH4TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */
+#define FTM_RD_EXTTRIG_CH5TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH5TRIG_MASK) >> FTM_EXTTRIG_CH5TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH5TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH5TRIG_SHIFT))
+
+/*! @brief Set the CH5TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH5TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH5TRIG_MASK, FTM_EXTTRIG_CH5TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH5TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH5TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */
+#define FTM_RD_EXTTRIG_CH0TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH0TRIG_MASK) >> FTM_EXTTRIG_CH0TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH0TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH0TRIG_SHIFT))
+
+/*! @brief Set the CH0TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH0TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH0TRIG_MASK, FTM_EXTTRIG_CH0TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH0TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH0TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */
+#define FTM_RD_EXTTRIG_CH1TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH1TRIG_MASK) >> FTM_EXTTRIG_CH1TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH1TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH1TRIG_SHIFT))
+
+/*! @brief Set the CH1TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH1TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH1TRIG_MASK, FTM_EXTTRIG_CH1TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH1TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH1TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
+ *
+ * Enables the generation of the trigger when the FTM counter is equal to the
+ * CNTIN register.
+ *
+ * Values:
+ * - 0b0 - The generation of initialization trigger is disabled.
+ * - 0b1 - The generation of initialization trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */
+#define FTM_RD_EXTTRIG_INITTRIGEN(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_INITTRIGEN_MASK) >> FTM_EXTTRIG_INITTRIGEN_SHIFT)
+#define FTM_BRD_EXTTRIG_INITTRIGEN(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_INITTRIGEN_SHIFT))
+
+/*! @brief Set the INITTRIGEN field to a new value. */
+#define FTM_WR_EXTTRIG_INITTRIGEN(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_INITTRIGEN_MASK, FTM_EXTTRIG_INITTRIGEN(value)))
+#define FTM_BWR_EXTTRIG_INITTRIGEN(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_INITTRIGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
+ *
+ * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
+ * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
+ * has no effect. If another channel trigger is generated before the clearing
+ * sequence is completed, the sequence is reset so TRIGF remains set after the clear
+ * sequence is completed for the earlier TRIGF.
+ *
+ * Values:
+ * - 0b0 - No channel trigger was generated.
+ * - 0b1 - A channel trigger was generated.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */
+#define FTM_RD_EXTTRIG_TRIGF(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_TRIGF_MASK) >> FTM_EXTTRIG_TRIGF_SHIFT)
+#define FTM_BRD_EXTTRIG_TRIGF(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_TRIGF_SHIFT))
+
+/*! @brief Set the TRIGF field to a new value. */
+#define FTM_WR_EXTTRIG_TRIGF(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_TRIGF_MASK, FTM_EXTTRIG_TRIGF(value)))
+#define FTM_BWR_EXTTRIG_TRIGF(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_TRIGF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_POL - Channels Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_POL - Channels Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the output polarity of the FTM channels. The safe value
+ * that is driven in a channel output when the fault control is enabled and a
+ * fault condition is detected is the inactive state of the channel. That is, the
+ * safe value of a channel is the value of its POL bit.
+ */
+/*!
+ * @name Constants and macros for entire FTM_POL register
+ */
+/*@{*/
+#define FTM_RD_POL(base)         (FTM_POL_REG(base))
+#define FTM_WR_POL(base, value)  (FTM_POL_REG(base) = (value))
+#define FTM_RMW_POL(base, mask, value) (FTM_WR_POL(base, (FTM_RD_POL(base) & ~(mask)) | (value)))
+#define FTM_SET_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) |  (value)))
+#define FTM_CLR_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) & ~(value)))
+#define FTM_TOG_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_POL bitfields
+ */
+
+/*!
+ * @name Register FTM_POL, field POL0[0] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL0 field. */
+#define FTM_RD_POL_POL0(base) ((FTM_POL_REG(base) & FTM_POL_POL0_MASK) >> FTM_POL_POL0_SHIFT)
+#define FTM_BRD_POL_POL0(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL0_SHIFT))
+
+/*! @brief Set the POL0 field to a new value. */
+#define FTM_WR_POL_POL0(base, value) (FTM_RMW_POL(base, FTM_POL_POL0_MASK, FTM_POL_POL0(value)))
+#define FTM_BWR_POL_POL0(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL1[1] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL1 field. */
+#define FTM_RD_POL_POL1(base) ((FTM_POL_REG(base) & FTM_POL_POL1_MASK) >> FTM_POL_POL1_SHIFT)
+#define FTM_BRD_POL_POL1(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL1_SHIFT))
+
+/*! @brief Set the POL1 field to a new value. */
+#define FTM_WR_POL_POL1(base, value) (FTM_RMW_POL(base, FTM_POL_POL1_MASK, FTM_POL_POL1(value)))
+#define FTM_BWR_POL_POL1(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL2[2] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL2 field. */
+#define FTM_RD_POL_POL2(base) ((FTM_POL_REG(base) & FTM_POL_POL2_MASK) >> FTM_POL_POL2_SHIFT)
+#define FTM_BRD_POL_POL2(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL2_SHIFT))
+
+/*! @brief Set the POL2 field to a new value. */
+#define FTM_WR_POL_POL2(base, value) (FTM_RMW_POL(base, FTM_POL_POL2_MASK, FTM_POL_POL2(value)))
+#define FTM_BWR_POL_POL2(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL3[3] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL3 field. */
+#define FTM_RD_POL_POL3(base) ((FTM_POL_REG(base) & FTM_POL_POL3_MASK) >> FTM_POL_POL3_SHIFT)
+#define FTM_BRD_POL_POL3(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL3_SHIFT))
+
+/*! @brief Set the POL3 field to a new value. */
+#define FTM_WR_POL_POL3(base, value) (FTM_RMW_POL(base, FTM_POL_POL3_MASK, FTM_POL_POL3(value)))
+#define FTM_BWR_POL_POL3(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL4[4] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL4 field. */
+#define FTM_RD_POL_POL4(base) ((FTM_POL_REG(base) & FTM_POL_POL4_MASK) >> FTM_POL_POL4_SHIFT)
+#define FTM_BRD_POL_POL4(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL4_SHIFT))
+
+/*! @brief Set the POL4 field to a new value. */
+#define FTM_WR_POL_POL4(base, value) (FTM_RMW_POL(base, FTM_POL_POL4_MASK, FTM_POL_POL4(value)))
+#define FTM_BWR_POL_POL4(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL5[5] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL5 field. */
+#define FTM_RD_POL_POL5(base) ((FTM_POL_REG(base) & FTM_POL_POL5_MASK) >> FTM_POL_POL5_SHIFT)
+#define FTM_BRD_POL_POL5(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL5_SHIFT))
+
+/*! @brief Set the POL5 field to a new value. */
+#define FTM_WR_POL_POL5(base, value) (FTM_RMW_POL(base, FTM_POL_POL5_MASK, FTM_POL_POL5(value)))
+#define FTM_BWR_POL_POL5(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL6[6] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL6 field. */
+#define FTM_RD_POL_POL6(base) ((FTM_POL_REG(base) & FTM_POL_POL6_MASK) >> FTM_POL_POL6_SHIFT)
+#define FTM_BRD_POL_POL6(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL6_SHIFT))
+
+/*! @brief Set the POL6 field to a new value. */
+#define FTM_WR_POL_POL6(base, value) (FTM_RMW_POL(base, FTM_POL_POL6_MASK, FTM_POL_POL6(value)))
+#define FTM_BWR_POL_POL6(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL7[7] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL7 field. */
+#define FTM_RD_POL_POL7(base) ((FTM_POL_REG(base) & FTM_POL_POL7_MASK) >> FTM_POL_POL7_SHIFT)
+#define FTM_BRD_POL_POL7(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL7_SHIFT))
+
+/*! @brief Set the POL7 field to a new value. */
+#define FTM_WR_POL_POL7(base, value) (FTM_RMW_POL(base, FTM_POL_POL7_MASK, FTM_POL_POL7(value)))
+#define FTM_BWR_POL_POL7(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FMS - Fault Mode Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FMS - Fault Mode Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the fault detection flags, write protection enable
+ * bit, and the logic OR of the enabled fault inputs.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FMS register
+ */
+/*@{*/
+#define FTM_RD_FMS(base)         (FTM_FMS_REG(base))
+#define FTM_WR_FMS(base, value)  (FTM_FMS_REG(base) = (value))
+#define FTM_RMW_FMS(base, mask, value) (FTM_WR_FMS(base, (FTM_RD_FMS(base) & ~(mask)) | (value)))
+#define FTM_SET_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) |  (value)))
+#define FTM_CLR_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) & ~(value)))
+#define FTM_TOG_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FMS bitfields
+ */
+
+/*!
+ * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
+ * by reading the FMS register while FAULTF0 is set and then writing a 0 to
+ * FAULTF0 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF0 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF0 field. */
+#define FTM_RD_FMS_FAULTF0(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF0_MASK) >> FTM_FMS_FAULTF0_SHIFT)
+#define FTM_BRD_FMS_FAULTF0(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF0_SHIFT))
+
+/*! @brief Set the FAULTF0 field to a new value. */
+#define FTM_WR_FMS_FAULTF0(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF0_MASK, FTM_FMS_FAULTF0(value)))
+#define FTM_BWR_FMS_FAULTF0(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
+ * by reading the FMS register while FAULTF1 is set and then writing a 0 to
+ * FAULTF1 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF1 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF1 field. */
+#define FTM_RD_FMS_FAULTF1(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF1_MASK) >> FTM_FMS_FAULTF1_SHIFT)
+#define FTM_BRD_FMS_FAULTF1(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF1_SHIFT))
+
+/*! @brief Set the FAULTF1 field to a new value. */
+#define FTM_WR_FMS_FAULTF1(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF1_MASK, FTM_FMS_FAULTF1(value)))
+#define FTM_BWR_FMS_FAULTF1(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
+ * by reading the FMS register while FAULTF2 is set and then writing a 0 to
+ * FAULTF2 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF2 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF2 field. */
+#define FTM_RD_FMS_FAULTF2(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF2_MASK) >> FTM_FMS_FAULTF2_SHIFT)
+#define FTM_BRD_FMS_FAULTF2(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF2_SHIFT))
+
+/*! @brief Set the FAULTF2 field to a new value. */
+#define FTM_WR_FMS_FAULTF2(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF2_MASK, FTM_FMS_FAULTF2(value)))
+#define FTM_BWR_FMS_FAULTF2(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
+ * by reading the FMS register while FAULTF3 is set and then writing a 0 to
+ * FAULTF3 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF3 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF3 field. */
+#define FTM_RD_FMS_FAULTF3(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF3_MASK) >> FTM_FMS_FAULTF3_SHIFT)
+#define FTM_BRD_FMS_FAULTF3(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF3_SHIFT))
+
+/*! @brief Set the FAULTF3 field to a new value. */
+#define FTM_WR_FMS_FAULTF3(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF3_MASK, FTM_FMS_FAULTF3(value)))
+#define FTM_BWR_FMS_FAULTF3(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTIN[5] (RO)
+ *
+ * Represents the logic OR of the enabled fault inputs after their filter (if
+ * their filter is enabled) when fault control is enabled.
+ *
+ * Values:
+ * - 0b0 - The logic OR of the enabled fault inputs is 0.
+ * - 0b1 - The logic OR of the enabled fault inputs is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTIN field. */
+#define FTM_RD_FMS_FAULTIN(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTIN_MASK) >> FTM_FMS_FAULTIN_SHIFT)
+#define FTM_BRD_FMS_FAULTIN(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTIN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field WPEN[6] (RW)
+ *
+ * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
+ * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
+ * WPDIS. Writing 0 to WPEN has no effect.
+ *
+ * Values:
+ * - 0b0 - Write protection is disabled. Write protected bits can be written.
+ * - 0b1 - Write protection is enabled. Write protected bits cannot be written.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_WPEN field. */
+#define FTM_RD_FMS_WPEN(base) ((FTM_FMS_REG(base) & FTM_FMS_WPEN_MASK) >> FTM_FMS_WPEN_SHIFT)
+#define FTM_BRD_FMS_WPEN(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_WPEN_SHIFT))
+
+/*! @brief Set the WPEN field to a new value. */
+#define FTM_WR_FMS_WPEN(base, value) (FTM_RMW_FMS(base, FTM_FMS_WPEN_MASK, FTM_FMS_WPEN(value)))
+#define FTM_BWR_FMS_WPEN(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_WPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
+ *
+ * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
+ * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
+ * a 0 to FAULTF while there is no existing fault condition at the enabled fault
+ * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
+ * detected in an enabled fault input before the clearing sequence is completed, the
+ * sequence is reset so FAULTF remains set after the clearing sequence is
+ * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
+ * are cleared individually.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected.
+ * - 0b1 - A fault condition was detected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF field. */
+#define FTM_RD_FMS_FAULTF(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF_MASK) >> FTM_FMS_FAULTF_SHIFT)
+#define FTM_BRD_FMS_FAULTF(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF_SHIFT))
+
+/*! @brief Set the FAULTF field to a new value. */
+#define FTM_WR_FMS_FAULTF(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF_MASK, FTM_FMS_FAULTF(value)))
+#define FTM_BWR_FMS_FAULTF(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FILTER - Input Capture Filter Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FILTER - Input Capture Filter Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the inputs of channels. Channels
+ * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
+ * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
+ * in input modes. Failure to do this could result in a missing valid signal.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FILTER register
+ */
+/*@{*/
+#define FTM_RD_FILTER(base)      (FTM_FILTER_REG(base))
+#define FTM_WR_FILTER(base, value) (FTM_FILTER_REG(base) = (value))
+#define FTM_RMW_FILTER(base, mask, value) (FTM_WR_FILTER(base, (FTM_RD_FILTER(base) & ~(mask)) | (value)))
+#define FTM_SET_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) |  (value)))
+#define FTM_CLR_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) & ~(value)))
+#define FTM_TOG_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FILTER bitfields
+ */
+
+/*!
+ * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */
+#define FTM_RD_FILTER_CH0FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH0FVAL_MASK) >> FTM_FILTER_CH0FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH0FVAL(base) (FTM_RD_FILTER_CH0FVAL(base))
+
+/*! @brief Set the CH0FVAL field to a new value. */
+#define FTM_WR_FILTER_CH0FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH0FVAL_MASK, FTM_FILTER_CH0FVAL(value)))
+#define FTM_BWR_FILTER_CH0FVAL(base, value) (FTM_WR_FILTER_CH0FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */
+#define FTM_RD_FILTER_CH1FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH1FVAL_MASK) >> FTM_FILTER_CH1FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH1FVAL(base) (FTM_RD_FILTER_CH1FVAL(base))
+
+/*! @brief Set the CH1FVAL field to a new value. */
+#define FTM_WR_FILTER_CH1FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH1FVAL_MASK, FTM_FILTER_CH1FVAL(value)))
+#define FTM_BWR_FILTER_CH1FVAL(base, value) (FTM_WR_FILTER_CH1FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */
+#define FTM_RD_FILTER_CH2FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH2FVAL_MASK) >> FTM_FILTER_CH2FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH2FVAL(base) (FTM_RD_FILTER_CH2FVAL(base))
+
+/*! @brief Set the CH2FVAL field to a new value. */
+#define FTM_WR_FILTER_CH2FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH2FVAL_MASK, FTM_FILTER_CH2FVAL(value)))
+#define FTM_BWR_FILTER_CH2FVAL(base, value) (FTM_WR_FILTER_CH2FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */
+#define FTM_RD_FILTER_CH3FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH3FVAL_MASK) >> FTM_FILTER_CH3FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH3FVAL(base) (FTM_RD_FILTER_CH3FVAL(base))
+
+/*! @brief Set the CH3FVAL field to a new value. */
+#define FTM_WR_FILTER_CH3FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH3FVAL_MASK, FTM_FILTER_CH3FVAL(value)))
+#define FTM_BWR_FILTER_CH3FVAL(base, value) (FTM_WR_FILTER_CH3FVAL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FLTCTRL - Fault Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FLTCTRL - Fault Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the fault inputs, enables the
+ * fault inputs and the fault inputs filter.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FLTCTRL register
+ */
+/*@{*/
+#define FTM_RD_FLTCTRL(base)     (FTM_FLTCTRL_REG(base))
+#define FTM_WR_FLTCTRL(base, value) (FTM_FLTCTRL_REG(base) = (value))
+#define FTM_RMW_FLTCTRL(base, mask, value) (FTM_WR_FLTCTRL(base, (FTM_RD_FLTCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) |  (value)))
+#define FTM_CLR_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) & ~(value)))
+#define FTM_TOG_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FLTCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */
+#define FTM_RD_FLTCTRL_FAULT0EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT0EN_MASK) >> FTM_FLTCTRL_FAULT0EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT0EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT0EN_SHIFT))
+
+/*! @brief Set the FAULT0EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT0EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT0EN_MASK, FTM_FLTCTRL_FAULT0EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT0EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */
+#define FTM_RD_FLTCTRL_FAULT1EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT1EN_MASK) >> FTM_FLTCTRL_FAULT1EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT1EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT1EN_SHIFT))
+
+/*! @brief Set the FAULT1EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT1EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT1EN_MASK, FTM_FLTCTRL_FAULT1EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT1EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */
+#define FTM_RD_FLTCTRL_FAULT2EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT2EN_MASK) >> FTM_FLTCTRL_FAULT2EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT2EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT2EN_SHIFT))
+
+/*! @brief Set the FAULT2EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT2EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT2EN_MASK, FTM_FLTCTRL_FAULT2EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT2EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */
+#define FTM_RD_FLTCTRL_FAULT3EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT3EN_MASK) >> FTM_FLTCTRL_FAULT3EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT3EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT3EN_SHIFT))
+
+/*! @brief Set the FAULT3EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT3EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT3EN_MASK, FTM_FLTCTRL_FAULT3EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT3EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT3EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */
+#define FTM_RD_FLTCTRL_FFLTR0EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR0EN_MASK) >> FTM_FLTCTRL_FFLTR0EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR0EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR0EN_SHIFT))
+
+/*! @brief Set the FFLTR0EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR0EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR0EN_MASK, FTM_FLTCTRL_FFLTR0EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR0EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */
+#define FTM_RD_FLTCTRL_FFLTR1EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR1EN_MASK) >> FTM_FLTCTRL_FFLTR1EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR1EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR1EN_SHIFT))
+
+/*! @brief Set the FFLTR1EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR1EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR1EN_MASK, FTM_FLTCTRL_FFLTR1EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR1EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */
+#define FTM_RD_FLTCTRL_FFLTR2EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR2EN_MASK) >> FTM_FLTCTRL_FFLTR2EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR2EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR2EN_SHIFT))
+
+/*! @brief Set the FFLTR2EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR2EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR2EN_MASK, FTM_FLTCTRL_FFLTR2EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR2EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */
+#define FTM_RD_FLTCTRL_FFLTR3EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR3EN_MASK) >> FTM_FLTCTRL_FFLTR3EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR3EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR3EN_SHIFT))
+
+/*! @brief Set the FFLTR3EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR3EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR3EN_MASK, FTM_FLTCTRL_FFLTR3EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR3EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR3EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
+ *
+ * Selects the filter value for the fault inputs. The fault filter is disabled
+ * when the value is zero. Writing to this field has immediate effect and must be
+ * done only when the fault control or all fault inputs are disabled. Failure to
+ * do this could result in a missing fault detection.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */
+#define FTM_RD_FLTCTRL_FFVAL(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFVAL_MASK) >> FTM_FLTCTRL_FFVAL_SHIFT)
+#define FTM_BRD_FLTCTRL_FFVAL(base) (FTM_RD_FLTCTRL_FFVAL(base))
+
+/*! @brief Set the FFVAL field to a new value. */
+#define FTM_WR_FLTCTRL_FFVAL(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFVAL_MASK, FTM_FLTCTRL_FFVAL(value)))
+#define FTM_BWR_FLTCTRL_FFVAL(base, value) (FTM_WR_FLTCTRL_FFVAL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_QDCTRL - Quadrature Decoder Control And Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has the control and status bits for the Quadrature Decoder mode.
+ */
+/*!
+ * @name Constants and macros for entire FTM_QDCTRL register
+ */
+/*@{*/
+#define FTM_RD_QDCTRL(base)      (FTM_QDCTRL_REG(base))
+#define FTM_WR_QDCTRL(base, value) (FTM_QDCTRL_REG(base) = (value))
+#define FTM_RMW_QDCTRL(base, mask, value) (FTM_WR_QDCTRL(base, (FTM_RD_QDCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) |  (value)))
+#define FTM_CLR_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) & ~(value)))
+#define FTM_TOG_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_QDCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
+ *
+ * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
+ * signals control the FTM counter direction. The Quadrature Decoder mode has
+ * precedence over the other modes. See #ModeSel1Table. This field is write protected.
+ * It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Quadrature Decoder mode is disabled.
+ * - 0b1 - Quadrature Decoder mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */
+#define FTM_RD_QDCTRL_QUADEN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADEN_MASK) >> FTM_QDCTRL_QUADEN_SHIFT)
+#define FTM_BRD_QDCTRL_QUADEN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADEN_SHIFT))
+
+/*! @brief Set the QUADEN field to a new value. */
+#define FTM_WR_QDCTRL_QUADEN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_QUADEN_MASK, FTM_QDCTRL_QUADEN(value)))
+#define FTM_BWR_QDCTRL_QUADEN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
+ *
+ * Indicates if the TOF bit was set on the top or the bottom of counting.
+ *
+ * Values:
+ * - 0b0 - TOF bit was set on the bottom of counting. There was an FTM counter
+ *     decrement and FTM counter changes from its minimum value (CNTIN register)
+ *     to its maximum value (MOD register).
+ * - 0b1 - TOF bit was set on the top of counting. There was an FTM counter
+ *     increment and FTM counter changes from its maximum value (MOD register) to its
+ *     minimum value (CNTIN register).
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */
+#define FTM_RD_QDCTRL_TOFDIR(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_TOFDIR_MASK) >> FTM_QDCTRL_TOFDIR_SHIFT)
+#define FTM_BRD_QDCTRL_TOFDIR(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_TOFDIR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
+ *
+ * Indicates the counting direction.
+ *
+ * Values:
+ * - 0b0 - Counting direction is decreasing (FTM counter decrement).
+ * - 0b1 - Counting direction is increasing (FTM counter increment).
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */
+#define FTM_RD_QDCTRL_QUADIR(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADIR_MASK) >> FTM_QDCTRL_QUADIR_SHIFT)
+#define FTM_BRD_QDCTRL_QUADIR(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADIR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
+ *
+ * Selects the encoding mode used in the Quadrature Decoder mode.
+ *
+ * Values:
+ * - 0b0 - Phase A and phase B encoding mode.
+ * - 0b1 - Count and direction encoding mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */
+#define FTM_RD_QDCTRL_QUADMODE(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADMODE_MASK) >> FTM_QDCTRL_QUADMODE_SHIFT)
+#define FTM_BRD_QDCTRL_QUADMODE(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADMODE_SHIFT))
+
+/*! @brief Set the QUADMODE field to a new value. */
+#define FTM_WR_QDCTRL_QUADMODE(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_QUADMODE_MASK, FTM_QDCTRL_QUADMODE(value)))
+#define FTM_BWR_QDCTRL_QUADMODE(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase B input.
+ *
+ * Values:
+ * - 0b0 - Normal polarity. Phase B input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 0b1 - Inverted polarity. Phase B input signal is inverted before
+ *     identifying the rising and falling edges of this signal.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */
+#define FTM_RD_QDCTRL_PHBPOL(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHBPOL_MASK) >> FTM_QDCTRL_PHBPOL_SHIFT)
+#define FTM_BRD_QDCTRL_PHBPOL(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBPOL_SHIFT))
+
+/*! @brief Set the PHBPOL field to a new value. */
+#define FTM_WR_QDCTRL_PHBPOL(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHBPOL_MASK, FTM_QDCTRL_PHBPOL(value)))
+#define FTM_BWR_QDCTRL_PHBPOL(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase A input.
+ *
+ * Values:
+ * - 0b0 - Normal polarity. Phase A input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 0b1 - Inverted polarity. Phase A input signal is inverted before
+ *     identifying the rising and falling edges of this signal.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */
+#define FTM_RD_QDCTRL_PHAPOL(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHAPOL_MASK) >> FTM_QDCTRL_PHAPOL_SHIFT)
+#define FTM_BRD_QDCTRL_PHAPOL(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAPOL_SHIFT))
+
+/*! @brief Set the PHAPOL field to a new value. */
+#define FTM_WR_QDCTRL_PHAPOL(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHAPOL_MASK, FTM_QDCTRL_PHAPOL(value)))
+#define FTM_BWR_QDCTRL_PHAPOL(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase B input. The filter value
+ * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
+ * filter is also disabled when CH1FVAL is zero.
+ *
+ * Values:
+ * - 0b0 - Phase B input filter is disabled.
+ * - 0b1 - Phase B input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */
+#define FTM_RD_QDCTRL_PHBFLTREN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHBFLTREN_MASK) >> FTM_QDCTRL_PHBFLTREN_SHIFT)
+#define FTM_BRD_QDCTRL_PHBFLTREN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBFLTREN_SHIFT))
+
+/*! @brief Set the PHBFLTREN field to a new value. */
+#define FTM_WR_QDCTRL_PHBFLTREN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHBFLTREN_MASK, FTM_QDCTRL_PHBFLTREN(value)))
+#define FTM_BWR_QDCTRL_PHBFLTREN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBFLTREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase A input. The filter value
+ * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
+ * filter is also disabled when CH0FVAL is zero.
+ *
+ * Values:
+ * - 0b0 - Phase A input filter is disabled.
+ * - 0b1 - Phase A input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */
+#define FTM_RD_QDCTRL_PHAFLTREN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHAFLTREN_MASK) >> FTM_QDCTRL_PHAFLTREN_SHIFT)
+#define FTM_BRD_QDCTRL_PHAFLTREN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAFLTREN_SHIFT))
+
+/*! @brief Set the PHAFLTREN field to a new value. */
+#define FTM_WR_QDCTRL_PHAFLTREN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHAFLTREN_MASK, FTM_QDCTRL_PHAFLTREN(value)))
+#define FTM_BWR_QDCTRL_PHAFLTREN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAFLTREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CONF - Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CONF - Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the number of times that the FTM counter overflow
+ * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
+ * of an external global time base, and the global time base signal generation.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CONF register
+ */
+/*@{*/
+#define FTM_RD_CONF(base)        (FTM_CONF_REG(base))
+#define FTM_WR_CONF(base, value) (FTM_CONF_REG(base) = (value))
+#define FTM_RMW_CONF(base, mask, value) (FTM_WR_CONF(base, (FTM_RD_CONF(base) & ~(mask)) | (value)))
+#define FTM_SET_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) |  (value)))
+#define FTM_CLR_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) & ~(value)))
+#define FTM_TOG_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CONF bitfields
+ */
+
+/*!
+ * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
+ *
+ * Selects the ratio between the number of counter overflows to the number of
+ * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
+ * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
+ * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
+ * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
+ * first counter overflow but not for the next 3 overflows. This pattern continues
+ * up to a maximum of 31.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_NUMTOF field. */
+#define FTM_RD_CONF_NUMTOF(base) ((FTM_CONF_REG(base) & FTM_CONF_NUMTOF_MASK) >> FTM_CONF_NUMTOF_SHIFT)
+#define FTM_BRD_CONF_NUMTOF(base) (FTM_RD_CONF_NUMTOF(base))
+
+/*! @brief Set the NUMTOF field to a new value. */
+#define FTM_WR_CONF_NUMTOF(base, value) (FTM_RMW_CONF(base, FTM_CONF_NUMTOF_MASK, FTM_CONF_NUMTOF(value)))
+#define FTM_BWR_CONF_NUMTOF(base, value) (FTM_WR_CONF_NUMTOF(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
+ *
+ * Selects the FTM behavior in BDM mode. See BDM mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_BDMMODE field. */
+#define FTM_RD_CONF_BDMMODE(base) ((FTM_CONF_REG(base) & FTM_CONF_BDMMODE_MASK) >> FTM_CONF_BDMMODE_SHIFT)
+#define FTM_BRD_CONF_BDMMODE(base) (FTM_RD_CONF_BDMMODE(base))
+
+/*! @brief Set the BDMMODE field to a new value. */
+#define FTM_WR_CONF_BDMMODE(base, value) (FTM_RMW_CONF(base, FTM_CONF_BDMMODE_MASK, FTM_CONF_BDMMODE(value)))
+#define FTM_BWR_CONF_BDMMODE(base, value) (FTM_WR_CONF_BDMMODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field GTBEEN[9] (RW)
+ *
+ * Configures the FTM to use an external global time base signal that is
+ * generated by another FTM.
+ *
+ * Values:
+ * - 0b0 - Use of an external global time base is disabled.
+ * - 0b1 - Use of an external global time base is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_GTBEEN field. */
+#define FTM_RD_CONF_GTBEEN(base) ((FTM_CONF_REG(base) & FTM_CONF_GTBEEN_MASK) >> FTM_CONF_GTBEEN_SHIFT)
+#define FTM_BRD_CONF_GTBEEN(base) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEEN_SHIFT))
+
+/*! @brief Set the GTBEEN field to a new value. */
+#define FTM_WR_CONF_GTBEEN(base, value) (FTM_RMW_CONF(base, FTM_CONF_GTBEEN_MASK, FTM_CONF_GTBEEN(value)))
+#define FTM_BWR_CONF_GTBEEN(base, value) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field GTBEOUT[10] (RW)
+ *
+ * Enables the global time base signal generation to other FTMs.
+ *
+ * Values:
+ * - 0b0 - A global time base signal generation is disabled.
+ * - 0b1 - A global time base signal generation is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_GTBEOUT field. */
+#define FTM_RD_CONF_GTBEOUT(base) ((FTM_CONF_REG(base) & FTM_CONF_GTBEOUT_MASK) >> FTM_CONF_GTBEOUT_SHIFT)
+#define FTM_BRD_CONF_GTBEOUT(base) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEOUT_SHIFT))
+
+/*! @brief Set the GTBEOUT field to a new value. */
+#define FTM_WR_CONF_GTBEOUT(base, value) (FTM_RMW_CONF(base, FTM_CONF_GTBEOUT_MASK, FTM_CONF_GTBEOUT(value)))
+#define FTM_BWR_CONF_GTBEOUT(base, value) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEOUT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FLTPOL - FTM Fault Input Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FLTPOL - FTM Fault Input Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the fault inputs polarity.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FLTPOL register
+ */
+/*@{*/
+#define FTM_RD_FLTPOL(base)      (FTM_FLTPOL_REG(base))
+#define FTM_WR_FLTPOL(base, value) (FTM_FLTPOL_REG(base) = (value))
+#define FTM_RMW_FLTPOL(base, mask, value) (FTM_WR_FLTPOL(base, (FTM_RD_FLTPOL(base) & ~(mask)) | (value)))
+#define FTM_SET_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) |  (value)))
+#define FTM_CLR_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) & ~(value)))
+#define FTM_TOG_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FLTPOL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */
+#define FTM_RD_FLTPOL_FLT0POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT0POL_MASK) >> FTM_FLTPOL_FLT0POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT0POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT0POL_SHIFT))
+
+/*! @brief Set the FLT0POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT0POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT0POL_MASK, FTM_FLTPOL_FLT0POL(value)))
+#define FTM_BWR_FLTPOL_FLT0POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT0POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */
+#define FTM_RD_FLTPOL_FLT1POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT1POL_MASK) >> FTM_FLTPOL_FLT1POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT1POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT1POL_SHIFT))
+
+/*! @brief Set the FLT1POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT1POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT1POL_MASK, FTM_FLTPOL_FLT1POL(value)))
+#define FTM_BWR_FLTPOL_FLT1POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT1POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */
+#define FTM_RD_FLTPOL_FLT2POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT2POL_MASK) >> FTM_FLTPOL_FLT2POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT2POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT2POL_SHIFT))
+
+/*! @brief Set the FLT2POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT2POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT2POL_MASK, FTM_FLTPOL_FLT2POL(value)))
+#define FTM_BWR_FLTPOL_FLT2POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT2POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */
+#define FTM_RD_FLTPOL_FLT3POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT3POL_MASK) >> FTM_FLTPOL_FLT3POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT3POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT3POL_SHIFT))
+
+/*! @brief Set the FLT3POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT3POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT3POL_MASK, FTM_FLTPOL_FLT3POL(value)))
+#define FTM_BWR_FLTPOL_FLT3POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT3POL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SYNCONF - Synchronization Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SYNCONF - Synchronization Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
+ * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
+ * 0, 1, 2, when the hardware trigger j is detected.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SYNCONF register
+ */
+/*@{*/
+#define FTM_RD_SYNCONF(base)     (FTM_SYNCONF_REG(base))
+#define FTM_WR_SYNCONF(base, value) (FTM_SYNCONF_REG(base) = (value))
+#define FTM_RMW_SYNCONF(base, mask, value) (FTM_WR_SYNCONF(base, (FTM_RD_SYNCONF(base) & ~(mask)) | (value)))
+#define FTM_SET_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) |  (value)))
+#define FTM_CLR_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) & ~(value)))
+#define FTM_TOG_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SYNCONF bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - FTM clears the TRIGj bit when the hardware trigger j is detected,
+ *     where j = 0, 1,2.
+ * - 0b1 - FTM does not clear the TRIGj bit when the hardware trigger j is
+ *     detected, where j = 0, 1,2.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */
+#define FTM_RD_SYNCONF_HWTRIGMODE(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWTRIGMODE_MASK) >> FTM_SYNCONF_HWTRIGMODE_SHIFT)
+#define FTM_BRD_SYNCONF_HWTRIGMODE(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWTRIGMODE_SHIFT))
+
+/*! @brief Set the HWTRIGMODE field to a new value. */
+#define FTM_WR_SYNCONF_HWTRIGMODE(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWTRIGMODE_MASK, FTM_SYNCONF_HWTRIGMODE(value)))
+#define FTM_BWR_SYNCONF_HWTRIGMODE(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWTRIGMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
+ *
+ * Values:
+ * - 0b0 - CNTIN register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - CNTIN register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */
+#define FTM_RD_SYNCONF_CNTINC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_CNTINC_MASK) >> FTM_SYNCONF_CNTINC_SHIFT)
+#define FTM_BRD_SYNCONF_CNTINC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_CNTINC_SHIFT))
+
+/*! @brief Set the CNTINC field to a new value. */
+#define FTM_WR_SYNCONF_CNTINC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_CNTINC_MASK, FTM_SYNCONF_CNTINC(value)))
+#define FTM_BWR_SYNCONF_CNTINC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_CNTINC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field INVC[4] (RW)
+ *
+ * Values:
+ * - 0b0 - INVCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - INVCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_INVC field. */
+#define FTM_RD_SYNCONF_INVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_INVC_MASK) >> FTM_SYNCONF_INVC_SHIFT)
+#define FTM_BRD_SYNCONF_INVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_INVC_SHIFT))
+
+/*! @brief Set the INVC field to a new value. */
+#define FTM_WR_SYNCONF_INVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_INVC_MASK, FTM_SYNCONF_INVC(value)))
+#define FTM_BWR_SYNCONF_INVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_INVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOC[5] (RW)
+ *
+ * Values:
+ * - 0b0 - SWOCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - SWOCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWOC field. */
+#define FTM_RD_SYNCONF_SWOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWOC_MASK) >> FTM_SYNCONF_SWOC_SHIFT)
+#define FTM_BRD_SYNCONF_SWOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOC_SHIFT))
+
+/*! @brief Set the SWOC field to a new value. */
+#define FTM_WR_SYNCONF_SWOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWOC_MASK, FTM_SYNCONF_SWOC(value)))
+#define FTM_BWR_SYNCONF_SWOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
+ *
+ * Selects the PWM Synchronization mode.
+ *
+ * Values:
+ * - 0b0 - Legacy PWM synchronization is selected.
+ * - 0b1 - Enhanced PWM synchronization is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */
+#define FTM_RD_SYNCONF_SYNCMODE(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SYNCMODE_MASK) >> FTM_SYNCONF_SYNCMODE_SHIFT)
+#define FTM_BRD_SYNCONF_SYNCMODE(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SYNCMODE_SHIFT))
+
+/*! @brief Set the SYNCMODE field to a new value. */
+#define FTM_WR_SYNCONF_SYNCMODE(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SYNCMODE_MASK, FTM_SYNCONF_SYNCMODE(value)))
+#define FTM_BWR_SYNCONF_SYNCMODE(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SYNCMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
+ *
+ * FTM counter synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the FTM counter
+ *     synchronization.
+ * - 0b1 - The software trigger activates the FTM counter synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */
+#define FTM_RD_SYNCONF_SWRSTCNT(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWRSTCNT_MASK) >> FTM_SYNCONF_SWRSTCNT_SHIFT)
+#define FTM_BRD_SYNCONF_SWRSTCNT(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWRSTCNT_SHIFT))
+
+/*! @brief Set the SWRSTCNT field to a new value. */
+#define FTM_WR_SYNCONF_SWRSTCNT(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWRSTCNT_MASK, FTM_SYNCONF_SWRSTCNT(value)))
+#define FTM_BWR_SYNCONF_SWRSTCNT(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWRSTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by the software
+ * trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 0b1 - The software trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */
+#define FTM_RD_SYNCONF_SWWRBUF(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWWRBUF_MASK) >> FTM_SYNCONF_SWWRBUF_SHIFT)
+#define FTM_BRD_SYNCONF_SWWRBUF(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWWRBUF_SHIFT))
+
+/*! @brief Set the SWWRBUF field to a new value. */
+#define FTM_WR_SYNCONF_SWWRBUF(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWWRBUF_MASK, FTM_SYNCONF_SWWRBUF(value)))
+#define FTM_BWR_SYNCONF_SWWRBUF(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWWRBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOM[10] (RW)
+ *
+ * Output mask synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the OUTMASK register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWOM field. */
+#define FTM_RD_SYNCONF_SWOM(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWOM_MASK) >> FTM_SYNCONF_SWOM_SHIFT)
+#define FTM_BRD_SYNCONF_SWOM(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOM_SHIFT))
+
+/*! @brief Set the SWOM field to a new value. */
+#define FTM_WR_SYNCONF_SWOM(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWOM_MASK, FTM_SYNCONF_SWOM(value)))
+#define FTM_BWR_SYNCONF_SWOM(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
+ *
+ * Inverting control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the INVCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */
+#define FTM_RD_SYNCONF_SWINVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWINVC_MASK) >> FTM_SYNCONF_SWINVC_SHIFT)
+#define FTM_BRD_SYNCONF_SWINVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWINVC_SHIFT))
+
+/*! @brief Set the SWINVC field to a new value. */
+#define FTM_WR_SYNCONF_SWINVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWINVC_MASK, FTM_SYNCONF_SWINVC(value)))
+#define FTM_BWR_SYNCONF_SWINVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWINVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
+ *
+ * Software output control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the SWOCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */
+#define FTM_RD_SYNCONF_SWSOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWSOC_MASK) >> FTM_SYNCONF_SWSOC_SHIFT)
+#define FTM_BRD_SYNCONF_SWSOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWSOC_SHIFT))
+
+/*! @brief Set the SWSOC field to a new value. */
+#define FTM_WR_SYNCONF_SWSOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWSOC_MASK, FTM_SYNCONF_SWSOC(value)))
+#define FTM_BWR_SYNCONF_SWSOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWSOC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
+ *
+ * FTM counter synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the FTM counter synchronization.
+ * - 0b1 - A hardware trigger activates the FTM counter synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */
+#define FTM_RD_SYNCONF_HWRSTCNT(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWRSTCNT_MASK) >> FTM_SYNCONF_HWRSTCNT_SHIFT)
+#define FTM_BRD_SYNCONF_HWRSTCNT(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWRSTCNT_SHIFT))
+
+/*! @brief Set the HWRSTCNT field to a new value. */
+#define FTM_WR_SYNCONF_HWRSTCNT(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWRSTCNT_MASK, FTM_SYNCONF_HWRSTCNT(value)))
+#define FTM_BWR_SYNCONF_HWRSTCNT(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWRSTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by a hardware
+ * trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */
+#define FTM_RD_SYNCONF_HWWRBUF(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWWRBUF_MASK) >> FTM_SYNCONF_HWWRBUF_SHIFT)
+#define FTM_BRD_SYNCONF_HWWRBUF(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWWRBUF_SHIFT))
+
+/*! @brief Set the HWWRBUF field to a new value. */
+#define FTM_WR_SYNCONF_HWWRBUF(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWWRBUF_MASK, FTM_SYNCONF_HWWRBUF(value)))
+#define FTM_BWR_SYNCONF_HWWRBUF(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWWRBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWOM[18] (RW)
+ *
+ * Output mask synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the OUTMASK register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWOM field. */
+#define FTM_RD_SYNCONF_HWOM(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWOM_MASK) >> FTM_SYNCONF_HWOM_SHIFT)
+#define FTM_BRD_SYNCONF_HWOM(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWOM_SHIFT))
+
+/*! @brief Set the HWOM field to a new value. */
+#define FTM_WR_SYNCONF_HWOM(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWOM_MASK, FTM_SYNCONF_HWOM(value)))
+#define FTM_BWR_SYNCONF_HWOM(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
+ *
+ * Inverting control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the INVCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */
+#define FTM_RD_SYNCONF_HWINVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWINVC_MASK) >> FTM_SYNCONF_HWINVC_SHIFT)
+#define FTM_BRD_SYNCONF_HWINVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWINVC_SHIFT))
+
+/*! @brief Set the HWINVC field to a new value. */
+#define FTM_WR_SYNCONF_HWINVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWINVC_MASK, FTM_SYNCONF_HWINVC(value)))
+#define FTM_BWR_SYNCONF_HWINVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWINVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
+ *
+ * Software output control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the SWOCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */
+#define FTM_RD_SYNCONF_HWSOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWSOC_MASK) >> FTM_SYNCONF_HWSOC_SHIFT)
+#define FTM_BRD_SYNCONF_HWSOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWSOC_SHIFT))
+
+/*! @brief Set the HWSOC field to a new value. */
+#define FTM_WR_SYNCONF_HWSOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWSOC_MASK, FTM_SYNCONF_HWSOC(value)))
+#define FTM_BWR_SYNCONF_HWSOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWSOC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_INVCTRL - FTM Inverting Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_INVCTRL - FTM Inverting Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls when the channel (n) output becomes the channel (n+1)
+ * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
+ * bit enables the inverting operation for the corresponding pair channels m. This
+ * register has a write buffer. The INVmEN bit is updated by the INVCTRL
+ * register synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_INVCTRL register
+ */
+/*@{*/
+#define FTM_RD_INVCTRL(base)     (FTM_INVCTRL_REG(base))
+#define FTM_WR_INVCTRL(base, value) (FTM_INVCTRL_REG(base) = (value))
+#define FTM_RMW_INVCTRL(base, mask, value) (FTM_WR_INVCTRL(base, (FTM_RD_INVCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) |  (value)))
+#define FTM_CLR_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) & ~(value)))
+#define FTM_TOG_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_INVCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */
+#define FTM_RD_INVCTRL_INV0EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV0EN_MASK) >> FTM_INVCTRL_INV0EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV0EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV0EN_SHIFT))
+
+/*! @brief Set the INV0EN field to a new value. */
+#define FTM_WR_INVCTRL_INV0EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV0EN_MASK, FTM_INVCTRL_INV0EN(value)))
+#define FTM_BWR_INVCTRL_INV0EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */
+#define FTM_RD_INVCTRL_INV1EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV1EN_MASK) >> FTM_INVCTRL_INV1EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV1EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV1EN_SHIFT))
+
+/*! @brief Set the INV1EN field to a new value. */
+#define FTM_WR_INVCTRL_INV1EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV1EN_MASK, FTM_INVCTRL_INV1EN(value)))
+#define FTM_BWR_INVCTRL_INV1EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */
+#define FTM_RD_INVCTRL_INV2EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV2EN_MASK) >> FTM_INVCTRL_INV2EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV2EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV2EN_SHIFT))
+
+/*! @brief Set the INV2EN field to a new value. */
+#define FTM_WR_INVCTRL_INV2EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV2EN_MASK, FTM_INVCTRL_INV2EN(value)))
+#define FTM_BWR_INVCTRL_INV2EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */
+#define FTM_RD_INVCTRL_INV3EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV3EN_MASK) >> FTM_INVCTRL_INV3EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV3EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV3EN_SHIFT))
+
+/*! @brief Set the INV3EN field to a new value. */
+#define FTM_WR_INVCTRL_INV3EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV3EN_MASK, FTM_INVCTRL_INV3EN(value)))
+#define FTM_BWR_INVCTRL_INV3EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV3EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SWOCTRL - FTM Software Output Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SWOCTRL - FTM Software Output Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register enables software control of channel (n) output and defines the
+ * value forced to the channel (n) output: The CHnOC bits enable the control of
+ * the corresponding channel (n) output by software. The CHnOCV bits select the
+ * value that is forced at the corresponding channel (n) output. This register has
+ * a write buffer. The fields are updated by the SWOCTRL register synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SWOCTRL register
+ */
+/*@{*/
+#define FTM_RD_SWOCTRL(base)     (FTM_SWOCTRL_REG(base))
+#define FTM_WR_SWOCTRL(base, value) (FTM_SWOCTRL_REG(base) = (value))
+#define FTM_RMW_SWOCTRL(base, mask, value) (FTM_WR_SWOCTRL(base, (FTM_RD_SWOCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) |  (value)))
+#define FTM_CLR_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) & ~(value)))
+#define FTM_TOG_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SWOCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */
+#define FTM_RD_SWOCTRL_CH0OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH0OC_MASK) >> FTM_SWOCTRL_CH0OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH0OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OC_SHIFT))
+
+/*! @brief Set the CH0OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH0OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH0OC_MASK, FTM_SWOCTRL_CH0OC(value)))
+#define FTM_BWR_SWOCTRL_CH0OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */
+#define FTM_RD_SWOCTRL_CH1OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH1OC_MASK) >> FTM_SWOCTRL_CH1OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH1OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OC_SHIFT))
+
+/*! @brief Set the CH1OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH1OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH1OC_MASK, FTM_SWOCTRL_CH1OC(value)))
+#define FTM_BWR_SWOCTRL_CH1OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */
+#define FTM_RD_SWOCTRL_CH2OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH2OC_MASK) >> FTM_SWOCTRL_CH2OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH2OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OC_SHIFT))
+
+/*! @brief Set the CH2OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH2OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH2OC_MASK, FTM_SWOCTRL_CH2OC(value)))
+#define FTM_BWR_SWOCTRL_CH2OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */
+#define FTM_RD_SWOCTRL_CH3OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH3OC_MASK) >> FTM_SWOCTRL_CH3OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH3OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OC_SHIFT))
+
+/*! @brief Set the CH3OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH3OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH3OC_MASK, FTM_SWOCTRL_CH3OC(value)))
+#define FTM_BWR_SWOCTRL_CH3OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */
+#define FTM_RD_SWOCTRL_CH4OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH4OC_MASK) >> FTM_SWOCTRL_CH4OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH4OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OC_SHIFT))
+
+/*! @brief Set the CH4OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH4OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH4OC_MASK, FTM_SWOCTRL_CH4OC(value)))
+#define FTM_BWR_SWOCTRL_CH4OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */
+#define FTM_RD_SWOCTRL_CH5OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH5OC_MASK) >> FTM_SWOCTRL_CH5OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH5OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OC_SHIFT))
+
+/*! @brief Set the CH5OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH5OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH5OC_MASK, FTM_SWOCTRL_CH5OC(value)))
+#define FTM_BWR_SWOCTRL_CH5OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */
+#define FTM_RD_SWOCTRL_CH6OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH6OC_MASK) >> FTM_SWOCTRL_CH6OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH6OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OC_SHIFT))
+
+/*! @brief Set the CH6OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH6OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH6OC_MASK, FTM_SWOCTRL_CH6OC(value)))
+#define FTM_BWR_SWOCTRL_CH6OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */
+#define FTM_RD_SWOCTRL_CH7OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH7OC_MASK) >> FTM_SWOCTRL_CH7OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH7OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OC_SHIFT))
+
+/*! @brief Set the CH7OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH7OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH7OC_MASK, FTM_SWOCTRL_CH7OC(value)))
+#define FTM_BWR_SWOCTRL_CH7OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */
+#define FTM_RD_SWOCTRL_CH0OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH0OCV_MASK) >> FTM_SWOCTRL_CH0OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH0OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OCV_SHIFT))
+
+/*! @brief Set the CH0OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH0OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH0OCV_MASK, FTM_SWOCTRL_CH0OCV(value)))
+#define FTM_BWR_SWOCTRL_CH0OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */
+#define FTM_RD_SWOCTRL_CH1OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH1OCV_MASK) >> FTM_SWOCTRL_CH1OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH1OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OCV_SHIFT))
+
+/*! @brief Set the CH1OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH1OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH1OCV_MASK, FTM_SWOCTRL_CH1OCV(value)))
+#define FTM_BWR_SWOCTRL_CH1OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */
+#define FTM_RD_SWOCTRL_CH2OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH2OCV_MASK) >> FTM_SWOCTRL_CH2OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH2OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OCV_SHIFT))
+
+/*! @brief Set the CH2OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH2OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH2OCV_MASK, FTM_SWOCTRL_CH2OCV(value)))
+#define FTM_BWR_SWOCTRL_CH2OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */
+#define FTM_RD_SWOCTRL_CH3OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH3OCV_MASK) >> FTM_SWOCTRL_CH3OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH3OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OCV_SHIFT))
+
+/*! @brief Set the CH3OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH3OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH3OCV_MASK, FTM_SWOCTRL_CH3OCV(value)))
+#define FTM_BWR_SWOCTRL_CH3OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */
+#define FTM_RD_SWOCTRL_CH4OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH4OCV_MASK) >> FTM_SWOCTRL_CH4OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH4OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OCV_SHIFT))
+
+/*! @brief Set the CH4OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH4OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH4OCV_MASK, FTM_SWOCTRL_CH4OCV(value)))
+#define FTM_BWR_SWOCTRL_CH4OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */
+#define FTM_RD_SWOCTRL_CH5OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH5OCV_MASK) >> FTM_SWOCTRL_CH5OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH5OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OCV_SHIFT))
+
+/*! @brief Set the CH5OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH5OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH5OCV_MASK, FTM_SWOCTRL_CH5OCV(value)))
+#define FTM_BWR_SWOCTRL_CH5OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */
+#define FTM_RD_SWOCTRL_CH6OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH6OCV_MASK) >> FTM_SWOCTRL_CH6OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH6OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OCV_SHIFT))
+
+/*! @brief Set the CH6OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH6OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH6OCV_MASK, FTM_SWOCTRL_CH6OCV(value)))
+#define FTM_BWR_SWOCTRL_CH6OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */
+#define FTM_RD_SWOCTRL_CH7OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH7OCV_MASK) >> FTM_SWOCTRL_CH7OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH7OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OCV_SHIFT))
+
+/*! @brief Set the CH7OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH7OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH7OCV_MASK, FTM_SWOCTRL_CH7OCV(value)))
+#define FTM_BWR_SWOCTRL_CH7OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OCV_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_PWMLOAD - FTM PWM Load
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_PWMLOAD - FTM PWM Load (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
+ * values of their write buffers when the FTM counter changes from the MOD
+ * register value to its next value or when a channel (j) match occurs. A match occurs
+ * for the channel (j) when FTM counter = C(j)V.
+ */
+/*!
+ * @name Constants and macros for entire FTM_PWMLOAD register
+ */
+/*@{*/
+#define FTM_RD_PWMLOAD(base)     (FTM_PWMLOAD_REG(base))
+#define FTM_WR_PWMLOAD(base, value) (FTM_PWMLOAD_REG(base) = (value))
+#define FTM_RMW_PWMLOAD(base, mask, value) (FTM_WR_PWMLOAD(base, (FTM_RD_PWMLOAD(base) & ~(mask)) | (value)))
+#define FTM_SET_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) |  (value)))
+#define FTM_CLR_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) & ~(value)))
+#define FTM_TOG_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_PWMLOAD bitfields
+ */
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */
+#define FTM_RD_PWMLOAD_CH0SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH0SEL_MASK) >> FTM_PWMLOAD_CH0SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH0SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH0SEL_SHIFT))
+
+/*! @brief Set the CH0SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH0SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH0SEL_MASK, FTM_PWMLOAD_CH0SEL(value)))
+#define FTM_BWR_PWMLOAD_CH0SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH0SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */
+#define FTM_RD_PWMLOAD_CH1SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH1SEL_MASK) >> FTM_PWMLOAD_CH1SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH1SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH1SEL_SHIFT))
+
+/*! @brief Set the CH1SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH1SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH1SEL_MASK, FTM_PWMLOAD_CH1SEL(value)))
+#define FTM_BWR_PWMLOAD_CH1SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH1SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */
+#define FTM_RD_PWMLOAD_CH2SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH2SEL_MASK) >> FTM_PWMLOAD_CH2SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH2SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH2SEL_SHIFT))
+
+/*! @brief Set the CH2SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH2SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH2SEL_MASK, FTM_PWMLOAD_CH2SEL(value)))
+#define FTM_BWR_PWMLOAD_CH2SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH2SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */
+#define FTM_RD_PWMLOAD_CH3SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH3SEL_MASK) >> FTM_PWMLOAD_CH3SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH3SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH3SEL_SHIFT))
+
+/*! @brief Set the CH3SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH3SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH3SEL_MASK, FTM_PWMLOAD_CH3SEL(value)))
+#define FTM_BWR_PWMLOAD_CH3SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH3SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */
+#define FTM_RD_PWMLOAD_CH4SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH4SEL_MASK) >> FTM_PWMLOAD_CH4SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH4SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH4SEL_SHIFT))
+
+/*! @brief Set the CH4SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH4SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH4SEL_MASK, FTM_PWMLOAD_CH4SEL(value)))
+#define FTM_BWR_PWMLOAD_CH4SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH4SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */
+#define FTM_RD_PWMLOAD_CH5SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH5SEL_MASK) >> FTM_PWMLOAD_CH5SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH5SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH5SEL_SHIFT))
+
+/*! @brief Set the CH5SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH5SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH5SEL_MASK, FTM_PWMLOAD_CH5SEL(value)))
+#define FTM_BWR_PWMLOAD_CH5SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH5SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */
+#define FTM_RD_PWMLOAD_CH6SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH6SEL_MASK) >> FTM_PWMLOAD_CH6SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH6SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH6SEL_SHIFT))
+
+/*! @brief Set the CH6SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH6SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH6SEL_MASK, FTM_PWMLOAD_CH6SEL(value)))
+#define FTM_BWR_PWMLOAD_CH6SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH6SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */
+#define FTM_RD_PWMLOAD_CH7SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH7SEL_MASK) >> FTM_PWMLOAD_CH7SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH7SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH7SEL_SHIFT))
+
+/*! @brief Set the CH7SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH7SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH7SEL_MASK, FTM_PWMLOAD_CH7SEL(value)))
+#define FTM_BWR_PWMLOAD_CH7SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH7SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
+ *
+ * Enables the loading of the MOD, CNTIN, and CV registers with the values of
+ * their write buffers.
+ *
+ * Values:
+ * - 0b0 - Loading updated values is disabled.
+ * - 0b1 - Loading updated values is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */
+#define FTM_RD_PWMLOAD_LDOK(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_LDOK_MASK) >> FTM_PWMLOAD_LDOK_SHIFT)
+#define FTM_BRD_PWMLOAD_LDOK(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_LDOK_SHIFT))
+
+/*! @brief Set the LDOK field to a new value. */
+#define FTM_WR_PWMLOAD_LDOK(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_LDOK_MASK, FTM_PWMLOAD_LDOK(value)))
+#define FTM_BWR_PWMLOAD_LDOK(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_LDOK_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 GPIO
+ *
+ * General Purpose Input/Output
+ *
+ * Registers defined in this header file:
+ * - GPIO_PDOR - Port Data Output Register
+ * - GPIO_PSOR - Port Set Output Register
+ * - GPIO_PCOR - Port Clear Output Register
+ * - GPIO_PTOR - Port Toggle Output Register
+ * - GPIO_PDIR - Port Data Input Register
+ * - GPIO_PDDR - Port Data Direction Register
+ */
+
+#define GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
+#define GPIOA_IDX (0U) /*!< Instance number for GPIOA. */
+#define GPIOB_IDX (1U) /*!< Instance number for GPIOB. */
+#define GPIOC_IDX (2U) /*!< Instance number for GPIOC. */
+#define GPIOD_IDX (3U) /*!< Instance number for GPIOD. */
+#define GPIOE_IDX (4U) /*!< Instance number for GPIOE. */
+
+/*******************************************************************************
+ * GPIO_PDOR - Port Data Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDOR - Port Data Output Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the logic levels that are driven on each
+ * general-purpose output pins. Do not modify pin configuration registers associated with
+ * pins not available in your selected package. All unbonded pins not available in
+ * your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDOR register
+ */
+/*@{*/
+#define GPIO_RD_PDOR(base)       (GPIO_PDOR_REG(base))
+#define GPIO_WR_PDOR(base, value) (GPIO_PDOR_REG(base) = (value))
+#define GPIO_RMW_PDOR(base, mask, value) (GPIO_WR_PDOR(base, (GPIO_RD_PDOR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) |  (value)))
+#define GPIO_CLR_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) & ~(value)))
+#define GPIO_TOG_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PSOR - Port Set Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PSOR - Port Set Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to set the fields of the PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PSOR register
+ */
+/*@{*/
+#define GPIO_RD_PSOR(base)       (GPIO_PSOR_REG(base))
+#define GPIO_WR_PSOR(base, value) (GPIO_PSOR_REG(base) = (value))
+#define GPIO_RMW_PSOR(base, mask, value) (GPIO_WR_PSOR(base, (GPIO_RD_PSOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PCOR - Port Clear Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PCOR - Port Clear Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to clear the fields of PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PCOR register
+ */
+/*@{*/
+#define GPIO_RD_PCOR(base)       (GPIO_PCOR_REG(base))
+#define GPIO_WR_PCOR(base, value) (GPIO_PCOR_REG(base) = (value))
+#define GPIO_RMW_PCOR(base, mask, value) (GPIO_WR_PCOR(base, (GPIO_RD_PCOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PTOR - Port Toggle Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PTOR - Port Toggle Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PTOR register
+ */
+/*@{*/
+#define GPIO_RD_PTOR(base)       (GPIO_PTOR_REG(base))
+#define GPIO_WR_PTOR(base, value) (GPIO_PTOR_REG(base) = (value))
+#define GPIO_RMW_PTOR(base, mask, value) (GPIO_WR_PTOR(base, (GPIO_RD_PTOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDIR - Port Data Input Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDIR - Port Data Input Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Do not modify pin configuration registers associated with pins not available
+ * in your selected package. All unbonded pins not available in your package will
+ * default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDIR register
+ */
+/*@{*/
+#define GPIO_RD_PDIR(base)       (GPIO_PDIR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDDR - Port Data Direction Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDDR - Port Data Direction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The PDDR configures the individual port pins for input or output.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDDR register
+ */
+/*@{*/
+#define GPIO_RD_PDDR(base)       (GPIO_PDDR_REG(base))
+#define GPIO_WR_PDDR(base, value) (GPIO_PDDR_REG(base) = (value))
+#define GPIO_RMW_PDDR(base, mask, value) (GPIO_WR_PDDR(base, (GPIO_RD_PDDR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) |  (value)))
+#define GPIO_CLR_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) & ~(value)))
+#define GPIO_TOG_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 I2C
+ *
+ * Inter-Integrated Circuit
+ *
+ * Registers defined in this header file:
+ * - I2C_A1 - I2C Address Register 1
+ * - I2C_F - I2C Frequency Divider register
+ * - I2C_C1 - I2C Control Register 1
+ * - I2C_S - I2C Status register
+ * - I2C_D - I2C Data I/O register
+ * - I2C_C2 - I2C Control Register 2
+ * - I2C_FLT - I2C Programmable Input Glitch Filter register
+ * - I2C_RA - I2C Range Address register
+ * - I2C_SMB - I2C SMBus Control and Status register
+ * - I2C_A2 - I2C Address Register 2
+ * - I2C_SLTH - I2C SCL Low Timeout Register High
+ * - I2C_SLTL - I2C SCL Low Timeout Register Low
+ */
+
+#define I2C_INSTANCE_COUNT (3U) /*!< Number of instances of the I2C module. */
+#define I2C0_IDX (0U) /*!< Instance number for I2C0. */
+#define I2C1_IDX (1U) /*!< Instance number for I2C1. */
+#define I2C2_IDX (2U) /*!< Instance number for I2C2. */
+
+/*******************************************************************************
+ * I2C_A1 - I2C Address Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A1 - I2C Address Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the slave address to be used by the I2C module.
+ */
+/*!
+ * @name Constants and macros for entire I2C_A1 register
+ */
+/*@{*/
+#define I2C_RD_A1(base)          (I2C_A1_REG(base))
+#define I2C_WR_A1(base, value)   (I2C_A1_REG(base) = (value))
+#define I2C_RMW_A1(base, mask, value) (I2C_WR_A1(base, (I2C_RD_A1(base) & ~(mask)) | (value)))
+#define I2C_SET_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) |  (value)))
+#define I2C_CLR_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) & ~(value)))
+#define I2C_TOG_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A1 bitfields
+ */
+
+/*!
+ * @name Register I2C_A1, field AD[7:1] (RW)
+ *
+ * Contains the primary slave address used by the I2C module when it is
+ * addressed as a slave. This field is used in the 7-bit address scheme and the lower
+ * seven bits in the 10-bit address scheme.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A1_AD field. */
+#define I2C_RD_A1_AD(base)   ((I2C_A1_REG(base) & I2C_A1_AD_MASK) >> I2C_A1_AD_SHIFT)
+#define I2C_BRD_A1_AD(base)  (I2C_RD_A1_AD(base))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_A1_AD(base, value) (I2C_RMW_A1(base, I2C_A1_AD_MASK, I2C_A1_AD(value)))
+#define I2C_BWR_A1_AD(base, value) (I2C_WR_A1_AD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_F - I2C Frequency Divider register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_F - I2C Frequency Divider register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_F register
+ */
+/*@{*/
+#define I2C_RD_F(base)           (I2C_F_REG(base))
+#define I2C_WR_F(base, value)    (I2C_F_REG(base) = (value))
+#define I2C_RMW_F(base, mask, value) (I2C_WR_F(base, (I2C_RD_F(base) & ~(mask)) | (value)))
+#define I2C_SET_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) |  (value)))
+#define I2C_CLR_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) & ~(value)))
+#define I2C_TOG_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_F bitfields
+ */
+
+/*!
+ * @name Register I2C_F, field ICR[5:0] (RW)
+ *
+ * Prescales the I2C module clock for bit rate selection. This field and the
+ * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
+ * time, and the SCL stop hold time. For a list of values corresponding to each ICR
+ * setting, see I2C divider and hold values. The SCL divider multiplied by
+ * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
+ * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
+ * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
+ * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
+ * the delay from the falling edge of SDA (I2C data) while SCL is high (start
+ * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
+ * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
+ * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
+ * data) while SCL is high (stop condition). SCL stop hold time = I2C module
+ * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
+ * speed is 8 MHz, the following table shows the possible hold time values with
+ * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
+ * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h
+ * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
+ * 1.125 4.750 5.125
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_ICR field. */
+#define I2C_RD_F_ICR(base)   ((I2C_F_REG(base) & I2C_F_ICR_MASK) >> I2C_F_ICR_SHIFT)
+#define I2C_BRD_F_ICR(base)  (I2C_RD_F_ICR(base))
+
+/*! @brief Set the ICR field to a new value. */
+#define I2C_WR_F_ICR(base, value) (I2C_RMW_F(base, I2C_F_ICR_MASK, I2C_F_ICR(value)))
+#define I2C_BWR_F_ICR(base, value) (I2C_WR_F_ICR(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_F, field MULT[7:6] (RW)
+ *
+ * Defines the multiplier factor (mul). This factor is used along with the SCL
+ * divider to generate the I2C baud rate.
+ *
+ * Values:
+ * - 0b00 - mul = 1
+ * - 0b01 - mul = 2
+ * - 0b10 - mul = 4
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_MULT field. */
+#define I2C_RD_F_MULT(base)  ((I2C_F_REG(base) & I2C_F_MULT_MASK) >> I2C_F_MULT_SHIFT)
+#define I2C_BRD_F_MULT(base) (I2C_RD_F_MULT(base))
+
+/*! @brief Set the MULT field to a new value. */
+#define I2C_WR_F_MULT(base, value) (I2C_RMW_F(base, I2C_F_MULT_MASK, I2C_F_MULT(value)))
+#define I2C_BWR_F_MULT(base, value) (I2C_WR_F_MULT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C1 - I2C Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C1 - I2C Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C1 register
+ */
+/*@{*/
+#define I2C_RD_C1(base)          (I2C_C1_REG(base))
+#define I2C_WR_C1(base, value)   (I2C_C1_REG(base) = (value))
+#define I2C_RMW_C1(base, mask, value) (I2C_WR_C1(base, (I2C_RD_C1(base) & ~(mask)) | (value)))
+#define I2C_SET_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) |  (value)))
+#define I2C_CLR_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) & ~(value)))
+#define I2C_TOG_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C1 bitfields
+ */
+
+/*!
+ * @name Register I2C_C1, field DMAEN[0] (RW)
+ *
+ * Enables or disables the DMA function.
+ *
+ * Values:
+ * - 0b0 - All DMA signalling disabled.
+ * - 0b1 - DMA transfer is enabled. While SMB[FACK] = 0, the following
+ *     conditions trigger the DMA request: a data byte is received, and either address or
+ *     data is transmitted. (ACK/NACK is automatic) the first byte received
+ *     matches the A1 register or is a general call address. If any address matching
+ *     occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
+ *     from master to slave, then it is not required to check S[SRW]. With this
+ *     assumption, DMA can also be used in this case. In other cases, if the master
+ *     reads data from the slave, then it is required to rewrite the C1 register
+ *     operation. With this assumption, DMA cannot be used. When FACK = 1, an
+ *     address or a data byte is transmitted.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_DMAEN field. */
+#define I2C_RD_C1_DMAEN(base) ((I2C_C1_REG(base) & I2C_C1_DMAEN_MASK) >> I2C_C1_DMAEN_SHIFT)
+#define I2C_BRD_C1_DMAEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define I2C_WR_C1_DMAEN(base, value) (I2C_RMW_C1(base, I2C_C1_DMAEN_MASK, I2C_C1_DMAEN(value)))
+#define I2C_BWR_C1_DMAEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field WUEN[1] (RW)
+ *
+ * The I2C module can wake the MCU from low power mode with no peripheral bus
+ * running when slave address matching occurs.
+ *
+ * Values:
+ * - 0b0 - Normal operation. No interrupt generated when address matching in low
+ *     power mode.
+ * - 0b1 - Enables the wakeup function in low power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_WUEN field. */
+#define I2C_RD_C1_WUEN(base) ((I2C_C1_REG(base) & I2C_C1_WUEN_MASK) >> I2C_C1_WUEN_SHIFT)
+#define I2C_BRD_C1_WUEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT))
+
+/*! @brief Set the WUEN field to a new value. */
+#define I2C_WR_C1_WUEN(base, value) (I2C_RMW_C1(base, I2C_C1_WUEN_MASK, I2C_C1_WUEN(value)))
+#define I2C_BWR_C1_WUEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field RSTA[2] (WORZ)
+ *
+ * Writing 1 to this bit generates a repeated START condition provided it is the
+ * current master. This bit will always be read as 0. Attempting a repeat at the
+ * wrong time results in loss of arbitration.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define I2C_WR_C1_RSTA(base, value) (I2C_RMW_C1(base, I2C_C1_RSTA_MASK, I2C_C1_RSTA(value)))
+#define I2C_BWR_C1_RSTA(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_RSTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TXAK[3] (RW)
+ *
+ * Specifies the value driven onto the SDA during data acknowledge cycles for
+ * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
+ * generation. SCL is held low until TXAK is written.
+ *
+ * Values:
+ * - 0b0 - An acknowledge signal is sent to the bus on the following receiving
+ *     byte (if FACK is cleared) or the current receiving byte (if FACK is set).
+ * - 0b1 - No acknowledge signal is sent to the bus on the following receiving
+ *     data byte (if FACK is cleared) or the current receiving data byte (if FACK
+ *     is set).
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TXAK field. */
+#define I2C_RD_C1_TXAK(base) ((I2C_C1_REG(base) & I2C_C1_TXAK_MASK) >> I2C_C1_TXAK_SHIFT)
+#define I2C_BRD_C1_TXAK(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT))
+
+/*! @brief Set the TXAK field to a new value. */
+#define I2C_WR_C1_TXAK(base, value) (I2C_RMW_C1(base, I2C_C1_TXAK_MASK, I2C_C1_TXAK(value)))
+#define I2C_BWR_C1_TXAK(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TX[4] (RW)
+ *
+ * Selects the direction of master and slave transfers. In master mode this bit
+ * must be set according to the type of transfer required. Therefore, for address
+ * cycles, this bit is always set. When addressed as a slave this bit must be
+ * set by software according to the SRW bit in the status register.
+ *
+ * Values:
+ * - 0b0 - Receive
+ * - 0b1 - Transmit
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TX field. */
+#define I2C_RD_C1_TX(base)   ((I2C_C1_REG(base) & I2C_C1_TX_MASK) >> I2C_C1_TX_SHIFT)
+#define I2C_BRD_C1_TX(base)  (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT))
+
+/*! @brief Set the TX field to a new value. */
+#define I2C_WR_C1_TX(base, value) (I2C_RMW_C1(base, I2C_C1_TX_MASK, I2C_C1_TX(value)))
+#define I2C_BWR_C1_TX(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field MST[5] (RW)
+ *
+ * When MST is changed from 0 to 1, a START signal is generated on the bus and
+ * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
+ * generated and the mode of operation changes from master to slave.
+ *
+ * Values:
+ * - 0b0 - Slave mode
+ * - 0b1 - Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_MST field. */
+#define I2C_RD_C1_MST(base)  ((I2C_C1_REG(base) & I2C_C1_MST_MASK) >> I2C_C1_MST_SHIFT)
+#define I2C_BRD_C1_MST(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT))
+
+/*! @brief Set the MST field to a new value. */
+#define I2C_WR_C1_MST(base, value) (I2C_RMW_C1(base, I2C_C1_MST_MASK, I2C_C1_MST(value)))
+#define I2C_BWR_C1_MST(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICIE[6] (RW)
+ *
+ * Enables I2C interrupt requests.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICIE field. */
+#define I2C_RD_C1_IICIE(base) ((I2C_C1_REG(base) & I2C_C1_IICIE_MASK) >> I2C_C1_IICIE_SHIFT)
+#define I2C_BRD_C1_IICIE(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT))
+
+/*! @brief Set the IICIE field to a new value. */
+#define I2C_WR_C1_IICIE(base, value) (I2C_RMW_C1(base, I2C_C1_IICIE_MASK, I2C_C1_IICIE(value)))
+#define I2C_BWR_C1_IICIE(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICEN[7] (RW)
+ *
+ * Enables I2C module operation.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICEN field. */
+#define I2C_RD_C1_IICEN(base) ((I2C_C1_REG(base) & I2C_C1_IICEN_MASK) >> I2C_C1_IICEN_SHIFT)
+#define I2C_BRD_C1_IICEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT))
+
+/*! @brief Set the IICEN field to a new value. */
+#define I2C_WR_C1_IICEN(base, value) (I2C_RMW_C1(base, I2C_C1_IICEN_MASK, I2C_C1_IICEN(value)))
+#define I2C_BWR_C1_IICEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_S - I2C Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_S - I2C Status register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire I2C_S register
+ */
+/*@{*/
+#define I2C_RD_S(base)           (I2C_S_REG(base))
+#define I2C_WR_S(base, value)    (I2C_S_REG(base) = (value))
+#define I2C_RMW_S(base, mask, value) (I2C_WR_S(base, (I2C_RD_S(base) & ~(mask)) | (value)))
+#define I2C_SET_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) |  (value)))
+#define I2C_CLR_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) & ~(value)))
+#define I2C_TOG_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_S bitfields
+ */
+
+/*!
+ * @name Register I2C_S, field RXAK[0] (RO)
+ *
+ * Values:
+ * - 0b0 - Acknowledge signal was received after the completion of one byte of
+ *     data transmission on the bus
+ * - 0b1 - No acknowledge signal detected
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RXAK field. */
+#define I2C_RD_S_RXAK(base)  ((I2C_S_REG(base) & I2C_S_RXAK_MASK) >> I2C_S_RXAK_SHIFT)
+#define I2C_BRD_S_RXAK(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RXAK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IICIF[1] (W1C)
+ *
+ * This bit sets when an interrupt is pending. This bit must be cleared by
+ * software by writing 1 to it, such as in the interrupt routine. One of the following
+ * events can set this bit: One byte transfer, including ACK/NACK bit, completes
+ * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
+ * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
+ * completes if FACK is 1. Match of slave address to calling address including
+ * primary slave address, range slave address , alert response address, second
+ * slave address, or general call address. Arbitration lost In SMBus mode, any
+ * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
+ * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
+ * start detection interrupt: In the interrupt service routine, first clear the
+ * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
+ * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
+ * asserted again.
+ *
+ * Values:
+ * - 0b0 - No interrupt pending
+ * - 0b1 - Interrupt pending
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IICIF field. */
+#define I2C_RD_S_IICIF(base) ((I2C_S_REG(base) & I2C_S_IICIF_MASK) >> I2C_S_IICIF_SHIFT)
+#define I2C_BRD_S_IICIF(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT))
+
+/*! @brief Set the IICIF field to a new value. */
+#define I2C_WR_S_IICIF(base, value) (I2C_RMW_S(base, (I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IICIF(value)))
+#define I2C_BWR_S_IICIF(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field SRW[2] (RO)
+ *
+ * When addressed as a slave, SRW indicates the value of the R/W command bit of
+ * the calling address sent to the master.
+ *
+ * Values:
+ * - 0b0 - Slave receive, master writing to slave
+ * - 0b1 - Slave transmit, master reading from slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_SRW field. */
+#define I2C_RD_S_SRW(base)   ((I2C_S_REG(base) & I2C_S_SRW_MASK) >> I2C_S_SRW_SHIFT)
+#define I2C_BRD_S_SRW(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_SRW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field RAM[3] (RW)
+ *
+ * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
+ * Any nonzero calling address is received that matches the address in the RA
+ * register. The calling address is within the range of values of the A1 and RA
+ * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
+ * Writing the C1 register with any value clears this bit to 0.
+ *
+ * Values:
+ * - 0b0 - Not addressed
+ * - 0b1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RAM field. */
+#define I2C_RD_S_RAM(base)   ((I2C_S_REG(base) & I2C_S_RAM_MASK) >> I2C_S_RAM_SHIFT)
+#define I2C_BRD_S_RAM(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RAM_SHIFT))
+
+/*! @brief Set the RAM field to a new value. */
+#define I2C_WR_S_RAM(base, value) (I2C_RMW_S(base, (I2C_S_RAM_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_RAM(value)))
+#define I2C_BWR_S_RAM(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RAM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field ARBL[4] (W1C)
+ *
+ * This bit is set by hardware when the arbitration procedure is lost. The ARBL
+ * bit must be cleared by software, by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - Standard bus operation.
+ * - 0b1 - Loss of arbitration.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_ARBL field. */
+#define I2C_RD_S_ARBL(base)  ((I2C_S_REG(base) & I2C_S_ARBL_MASK) >> I2C_S_ARBL_SHIFT)
+#define I2C_BRD_S_ARBL(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT))
+
+/*! @brief Set the ARBL field to a new value. */
+#define I2C_WR_S_ARBL(base, value) (I2C_RMW_S(base, (I2C_S_ARBL_MASK | I2C_S_IICIF_MASK), I2C_S_ARBL(value)))
+#define I2C_BWR_S_ARBL(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field BUSY[5] (RO)
+ *
+ * Indicates the status of the bus regardless of slave or master mode. This bit
+ * is set when a START signal is detected and cleared when a STOP signal is
+ * detected.
+ *
+ * Values:
+ * - 0b0 - Bus is idle
+ * - 0b1 - Bus is busy
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_BUSY field. */
+#define I2C_RD_S_BUSY(base)  ((I2C_S_REG(base) & I2C_S_BUSY_MASK) >> I2C_S_BUSY_SHIFT)
+#define I2C_BRD_S_BUSY(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_BUSY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IAAS[6] (RW)
+ *
+ * This bit is set by one of the following conditions: The calling address
+ * matches the programmed primary slave address in the A1 register, or matches the
+ * range address in the RA register (which must be set to a nonzero value and under
+ * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
+ * received. SMB[SIICAEN] is set and the calling address matches the second programmed
+ * slave address. ALERTEN is set and an SMBus alert response address is received
+ * RMEN is set and an address is received that is within the range between the
+ * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
+ * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
+ * value clears this bit.
+ *
+ * Values:
+ * - 0b0 - Not addressed
+ * - 0b1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IAAS field. */
+#define I2C_RD_S_IAAS(base)  ((I2C_S_REG(base) & I2C_S_IAAS_MASK) >> I2C_S_IAAS_SHIFT)
+#define I2C_BRD_S_IAAS(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT))
+
+/*! @brief Set the IAAS field to a new value. */
+#define I2C_WR_S_IAAS(base, value) (I2C_RMW_S(base, (I2C_S_IAAS_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IAAS(value)))
+#define I2C_BWR_S_IAAS(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field TCF[7] (RO)
+ *
+ * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
+ * This bit is valid only during or immediately following a transfer to or from
+ * the I2C module. TCF is cleared by reading the I2C data register in receive mode
+ * or by writing to the I2C data register in transmit mode.
+ *
+ * Values:
+ * - 0b0 - Transfer in progress
+ * - 0b1 - Transfer complete
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_TCF field. */
+#define I2C_RD_S_TCF(base)   ((I2C_S_REG(base) & I2C_S_TCF_MASK) >> I2C_S_TCF_SHIFT)
+#define I2C_BRD_S_TCF(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_TCF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_D - I2C Data I/O register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_D - I2C Data I/O register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_D register
+ */
+/*@{*/
+#define I2C_RD_D(base)           (I2C_D_REG(base))
+#define I2C_WR_D(base, value)    (I2C_D_REG(base) = (value))
+#define I2C_RMW_D(base, mask, value) (I2C_WR_D(base, (I2C_RD_D(base) & ~(mask)) | (value)))
+#define I2C_SET_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) |  (value)))
+#define I2C_CLR_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) & ~(value)))
+#define I2C_TOG_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C2 - I2C Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C2 - I2C Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C2 register
+ */
+/*@{*/
+#define I2C_RD_C2(base)          (I2C_C2_REG(base))
+#define I2C_WR_C2(base, value)   (I2C_C2_REG(base) = (value))
+#define I2C_RMW_C2(base, mask, value) (I2C_WR_C2(base, (I2C_RD_C2(base) & ~(mask)) | (value)))
+#define I2C_SET_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) |  (value)))
+#define I2C_CLR_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) & ~(value)))
+#define I2C_TOG_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C2 bitfields
+ */
+
+/*!
+ * @name Register I2C_C2, field AD[2:0] (RW)
+ *
+ * Contains the upper three bits of the slave address in the 10-bit address
+ * scheme. This field is valid only while the ADEXT bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_AD field. */
+#define I2C_RD_C2_AD(base)   ((I2C_C2_REG(base) & I2C_C2_AD_MASK) >> I2C_C2_AD_SHIFT)
+#define I2C_BRD_C2_AD(base)  (I2C_RD_C2_AD(base))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_C2_AD(base, value) (I2C_RMW_C2(base, I2C_C2_AD_MASK, I2C_C2_AD(value)))
+#define I2C_BWR_C2_AD(base, value) (I2C_WR_C2_AD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field RMEN[3] (RW)
+ *
+ * This bit controls the slave address matching for addresses between the values
+ * of the A1 and RA registers. When this bit is set, a slave address matching
+ * occurs for any address greater than the value of the A1 register and less than
+ * or equal to the value of the RA register.
+ *
+ * Values:
+ * - 0b0 - Range mode disabled. No address matching occurs for an address within
+ *     the range of values of the A1 and RA registers.
+ * - 0b1 - Range mode enabled. Address matching occurs when a slave receives an
+ *     address within the range of values of the A1 and RA registers.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_RMEN field. */
+#define I2C_RD_C2_RMEN(base) ((I2C_C2_REG(base) & I2C_C2_RMEN_MASK) >> I2C_C2_RMEN_SHIFT)
+#define I2C_BRD_C2_RMEN(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT))
+
+/*! @brief Set the RMEN field to a new value. */
+#define I2C_WR_C2_RMEN(base, value) (I2C_RMW_C2(base, I2C_C2_RMEN_MASK, I2C_C2_RMEN(value)))
+#define I2C_BWR_C2_RMEN(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field SBRC[4] (RW)
+ *
+ * Enables independent slave mode baud rate at maximum frequency, which forces
+ * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
+ * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
+ * capture the master's data at only 10 kbit/s.
+ *
+ * Values:
+ * - 0b0 - The slave baud rate follows the master baud rate and clock stretching
+ *     may occur
+ * - 0b1 - Slave baud rate is independent of the master baud rate
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_SBRC field. */
+#define I2C_RD_C2_SBRC(base) ((I2C_C2_REG(base) & I2C_C2_SBRC_MASK) >> I2C_C2_SBRC_SHIFT)
+#define I2C_BRD_C2_SBRC(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT))
+
+/*! @brief Set the SBRC field to a new value. */
+#define I2C_WR_C2_SBRC(base, value) (I2C_RMW_C2(base, I2C_C2_SBRC_MASK, I2C_C2_SBRC(value)))
+#define I2C_BWR_C2_SBRC(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field HDRS[5] (RW)
+ *
+ * Controls the drive capability of the I2C pads.
+ *
+ * Values:
+ * - 0b0 - Normal drive mode
+ * - 0b1 - High drive mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_HDRS field. */
+#define I2C_RD_C2_HDRS(base) ((I2C_C2_REG(base) & I2C_C2_HDRS_MASK) >> I2C_C2_HDRS_SHIFT)
+#define I2C_BRD_C2_HDRS(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT))
+
+/*! @brief Set the HDRS field to a new value. */
+#define I2C_WR_C2_HDRS(base, value) (I2C_RMW_C2(base, I2C_C2_HDRS_MASK, I2C_C2_HDRS(value)))
+#define I2C_BWR_C2_HDRS(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field ADEXT[6] (RW)
+ *
+ * Controls the number of bits used for the slave address.
+ *
+ * Values:
+ * - 0b0 - 7-bit address scheme
+ * - 0b1 - 10-bit address scheme
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_ADEXT field. */
+#define I2C_RD_C2_ADEXT(base) ((I2C_C2_REG(base) & I2C_C2_ADEXT_MASK) >> I2C_C2_ADEXT_SHIFT)
+#define I2C_BRD_C2_ADEXT(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT))
+
+/*! @brief Set the ADEXT field to a new value. */
+#define I2C_WR_C2_ADEXT(base, value) (I2C_RMW_C2(base, I2C_C2_ADEXT_MASK, I2C_C2_ADEXT(value)))
+#define I2C_BWR_C2_ADEXT(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field GCAEN[7] (RW)
+ *
+ * Enables general call address.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_GCAEN field. */
+#define I2C_RD_C2_GCAEN(base) ((I2C_C2_REG(base) & I2C_C2_GCAEN_MASK) >> I2C_C2_GCAEN_SHIFT)
+#define I2C_BRD_C2_GCAEN(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT))
+
+/*! @brief Set the GCAEN field to a new value. */
+#define I2C_WR_C2_GCAEN(base, value) (I2C_RMW_C2(base, I2C_C2_GCAEN_MASK, I2C_C2_GCAEN(value)))
+#define I2C_BWR_C2_GCAEN(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_FLT - I2C Programmable Input Glitch Filter register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_FLT register
+ */
+/*@{*/
+#define I2C_RD_FLT(base)         (I2C_FLT_REG(base))
+#define I2C_WR_FLT(base, value)  (I2C_FLT_REG(base) = (value))
+#define I2C_RMW_FLT(base, mask, value) (I2C_WR_FLT(base, (I2C_RD_FLT(base) & ~(mask)) | (value)))
+#define I2C_SET_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) |  (value)))
+#define I2C_CLR_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) & ~(value)))
+#define I2C_TOG_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_FLT bitfields
+ */
+
+/*!
+ * @name Register I2C_FLT, field FLT[3:0] (RW)
+ *
+ * Controls the width of the glitch, in terms of I2C module clock cycles, that
+ * the filter must absorb. For any glitch whose size is less than or equal to this
+ * width setting, the filter does not allow the glitch to pass.
+ *
+ * Values:
+ * - 0b0000 - No filter/bypass
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_FLT field. */
+#define I2C_RD_FLT_FLT(base) ((I2C_FLT_REG(base) & I2C_FLT_FLT_MASK) >> I2C_FLT_FLT_SHIFT)
+#define I2C_BRD_FLT_FLT(base) (I2C_RD_FLT_FLT(base))
+
+/*! @brief Set the FLT field to a new value. */
+#define I2C_WR_FLT_FLT(base, value) (I2C_RMW_FLT(base, (I2C_FLT_FLT_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_FLT(value)))
+#define I2C_BWR_FLT_FLT(base, value) (I2C_WR_FLT_FLT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STARTF[4] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's start status is detected. The
+ * STARTF bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No start happens on I2C bus
+ * - 0b1 - Start detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STARTF field. */
+#define I2C_RD_FLT_STARTF(base) ((I2C_FLT_REG(base) & I2C_FLT_STARTF_MASK) >> I2C_FLT_STARTF_SHIFT)
+#define I2C_BRD_FLT_STARTF(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT))
+
+/*! @brief Set the STARTF field to a new value. */
+#define I2C_WR_FLT_STARTF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_STARTF(value)))
+#define I2C_BWR_FLT_STARTF(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SSIE[5] (RW)
+ *
+ * This bit enables the interrupt for I2C bus stop or start detection. To clear
+ * the I2C bus stop or start detection interrupt: In the interrupt service
+ * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
+ * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
+ * is asserted again.
+ *
+ * Values:
+ * - 0b0 - Stop or start detection interrupt is disabled
+ * - 0b1 - Stop or start detection interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SSIE field. */
+#define I2C_RD_FLT_SSIE(base) ((I2C_FLT_REG(base) & I2C_FLT_SSIE_MASK) >> I2C_FLT_SSIE_SHIFT)
+#define I2C_BRD_FLT_SSIE(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT))
+
+/*! @brief Set the SSIE field to a new value. */
+#define I2C_WR_FLT_SSIE(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SSIE_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SSIE(value)))
+#define I2C_BWR_FLT_SSIE(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STOPF[6] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
+ * bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No stop happens on I2C bus
+ * - 0b1 - Stop detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STOPF field. */
+#define I2C_RD_FLT_STOPF(base) ((I2C_FLT_REG(base) & I2C_FLT_STOPF_MASK) >> I2C_FLT_STOPF_SHIFT)
+#define I2C_BRD_FLT_STOPF(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT))
+
+/*! @brief Set the STOPF field to a new value. */
+#define I2C_WR_FLT_STOPF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK), I2C_FLT_STOPF(value)))
+#define I2C_BWR_FLT_STOPF(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SHEN[7] (RW)
+ *
+ * Set this bit to hold off entry to stop mode when any data transmission or
+ * reception is occurring. The following scenario explains the holdoff
+ * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
+ * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
+ * byte currently being transferred, including both address and data, completes
+ * its transfer. The I2C slave or master acknowledges that the in-transfer byte
+ * completed its transfer and acknowledges the request to enter stop mode. After
+ * receiving the I2C module's acknowledgment of the request to enter stop mode,
+ * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
+ * is set to 1 and the I2C module is in an idle or disabled state when the MCU
+ * signals to enter stop mode, the module immediately acknowledges the request to
+ * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
+ * reception that was suspended by stop mode entry was incomplete: To resume the
+ * overall transmission or reception after the MCU exits stop mode, software must
+ * reinitialize the transfer by resending the address of the slave. If the I2C
+ * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
+ * system software will receive the interrupt triggered by the I2C Status Register's
+ * TCF bit after the MCU wakes from the stop mode.
+ *
+ * Values:
+ * - 0b0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
+ * - 0b1 - Stop holdoff is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SHEN field. */
+#define I2C_RD_FLT_SHEN(base) ((I2C_FLT_REG(base) & I2C_FLT_SHEN_MASK) >> I2C_FLT_SHEN_SHIFT)
+#define I2C_BRD_FLT_SHEN(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT))
+
+/*! @brief Set the SHEN field to a new value. */
+#define I2C_WR_FLT_SHEN(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SHEN_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SHEN(value)))
+#define I2C_BWR_FLT_SHEN(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_RA - I2C Range Address register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_RA - I2C Range Address register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_RA register
+ */
+/*@{*/
+#define I2C_RD_RA(base)          (I2C_RA_REG(base))
+#define I2C_WR_RA(base, value)   (I2C_RA_REG(base) = (value))
+#define I2C_RMW_RA(base, mask, value) (I2C_WR_RA(base, (I2C_RD_RA(base) & ~(mask)) | (value)))
+#define I2C_SET_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) |  (value)))
+#define I2C_CLR_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) & ~(value)))
+#define I2C_TOG_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_RA bitfields
+ */
+
+/*!
+ * @name Register I2C_RA, field RAD[7:1] (RW)
+ *
+ * This field contains the slave address to be used by the I2C module. The field
+ * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
+ * value write enables this register. This register value can be considered as a
+ * maximum boundary in the range matching mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_RA_RAD field. */
+#define I2C_RD_RA_RAD(base)  ((I2C_RA_REG(base) & I2C_RA_RAD_MASK) >> I2C_RA_RAD_SHIFT)
+#define I2C_BRD_RA_RAD(base) (I2C_RD_RA_RAD(base))
+
+/*! @brief Set the RAD field to a new value. */
+#define I2C_WR_RA_RAD(base, value) (I2C_RMW_RA(base, I2C_RA_RAD_MASK, I2C_RA_RAD(value)))
+#define I2C_BWR_RA_RAD(base, value) (I2C_WR_RA_RAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SMB - I2C SMBus Control and Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SMB - I2C SMBus Control and Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When the SCL and SDA signals are held high for a length of time greater than
+ * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
+ * while the system is detecting how long these signals are being held high, a
+ * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
+ * bus transmission process with the idle bus state. When the TCKSEL bit is set,
+ * there is no need to monitor the SHTF1 bit because the bus speed is too high to
+ * match the protocol of SMBus.
+ */
+/*!
+ * @name Constants and macros for entire I2C_SMB register
+ */
+/*@{*/
+#define I2C_RD_SMB(base)         (I2C_SMB_REG(base))
+#define I2C_WR_SMB(base, value)  (I2C_SMB_REG(base) = (value))
+#define I2C_RMW_SMB(base, mask, value) (I2C_WR_SMB(base, (I2C_RD_SMB(base) & ~(mask)) | (value)))
+#define I2C_SET_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) |  (value)))
+#define I2C_CLR_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) & ~(value)))
+#define I2C_TOG_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_SMB bitfields
+ */
+
+/*!
+ * @name Register I2C_SMB, field SHTF2IE[0] (RW)
+ *
+ * Enables SCL high and SDA low timeout interrupt.
+ *
+ * Values:
+ * - 0b0 - SHTF2 interrupt is disabled
+ * - 0b1 - SHTF2 interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2IE field. */
+#define I2C_RD_SMB_SHTF2IE(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2IE_MASK) >> I2C_SMB_SHTF2IE_SHIFT)
+#define I2C_BRD_SMB_SHTF2IE(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT))
+
+/*! @brief Set the SHTF2IE field to a new value. */
+#define I2C_WR_SMB_SHTF2IE(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2IE_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2IE(value)))
+#define I2C_BWR_SMB_SHTF2IE(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF2[1] (W1C)
+ *
+ * This bit sets when SCL is held high and SDA is held low more than clock *
+ * LoValue / 512. Software clears this bit by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No SCL high and SDA low timeout occurs
+ * - 0b1 - SCL high and SDA low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2 field. */
+#define I2C_RD_SMB_SHTF2(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2_MASK) >> I2C_SMB_SHTF2_SHIFT)
+#define I2C_BRD_SMB_SHTF2(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT))
+
+/*! @brief Set the SHTF2 field to a new value. */
+#define I2C_WR_SMB_SHTF2(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2(value)))
+#define I2C_BWR_SMB_SHTF2(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF1[2] (RO)
+ *
+ * This read-only bit sets when SCL and SDA are held high more than clock *
+ * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
+ *
+ * Values:
+ * - 0b0 - No SCL high and SDA high timeout occurs
+ * - 0b1 - SCL high and SDA high timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF1 field. */
+#define I2C_RD_SMB_SHTF1(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF1_MASK) >> I2C_SMB_SHTF1_SHIFT)
+#define I2C_BRD_SMB_SHTF1(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SLTF[3] (W1C)
+ *
+ * This bit is set when the SLT register (consisting of the SLTH and SLTL
+ * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
+ * Software clears this bit by writing a logic 1 to it. The low timeout function
+ * is disabled when the SLT register's value is 0.
+ *
+ * Values:
+ * - 0b0 - No low timeout occurs
+ * - 0b1 - Low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SLTF field. */
+#define I2C_RD_SMB_SLTF(base) ((I2C_SMB_REG(base) & I2C_SMB_SLTF_MASK) >> I2C_SMB_SLTF_SHIFT)
+#define I2C_BRD_SMB_SLTF(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT))
+
+/*! @brief Set the SLTF field to a new value. */
+#define I2C_WR_SMB_SLTF(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SLTF_MASK | I2C_SMB_SHTF2_MASK), I2C_SMB_SLTF(value)))
+#define I2C_BWR_SMB_SLTF(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field TCKSEL[4] (RW)
+ *
+ * Selects the clock source of the timeout counter.
+ *
+ * Values:
+ * - 0b0 - Timeout counter counts at the frequency of the I2C module clock / 64
+ * - 0b1 - Timeout counter counts at the frequency of the I2C module clock
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_TCKSEL field. */
+#define I2C_RD_SMB_TCKSEL(base) ((I2C_SMB_REG(base) & I2C_SMB_TCKSEL_MASK) >> I2C_SMB_TCKSEL_SHIFT)
+#define I2C_BRD_SMB_TCKSEL(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT))
+
+/*! @brief Set the TCKSEL field to a new value. */
+#define I2C_WR_SMB_TCKSEL(base, value) (I2C_RMW_SMB(base, (I2C_SMB_TCKSEL_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_TCKSEL(value)))
+#define I2C_BWR_SMB_TCKSEL(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SIICAEN[5] (RW)
+ *
+ * Enables or disables SMBus device default address.
+ *
+ * Values:
+ * - 0b0 - I2C address register 2 matching is disabled
+ * - 0b1 - I2C address register 2 matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SIICAEN field. */
+#define I2C_RD_SMB_SIICAEN(base) ((I2C_SMB_REG(base) & I2C_SMB_SIICAEN_MASK) >> I2C_SMB_SIICAEN_SHIFT)
+#define I2C_BRD_SMB_SIICAEN(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT))
+
+/*! @brief Set the SIICAEN field to a new value. */
+#define I2C_WR_SMB_SIICAEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SIICAEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SIICAEN(value)))
+#define I2C_BWR_SMB_SIICAEN(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field ALERTEN[6] (RW)
+ *
+ * Enables or disables SMBus alert response address matching. After the host
+ * responds to a device that used the alert response address, you must use software
+ * to put the device's address on the bus. The alert protocol is described in the
+ * SMBus specification.
+ *
+ * Values:
+ * - 0b0 - SMBus alert response address matching is disabled
+ * - 0b1 - SMBus alert response address matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_ALERTEN field. */
+#define I2C_RD_SMB_ALERTEN(base) ((I2C_SMB_REG(base) & I2C_SMB_ALERTEN_MASK) >> I2C_SMB_ALERTEN_SHIFT)
+#define I2C_BRD_SMB_ALERTEN(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT))
+
+/*! @brief Set the ALERTEN field to a new value. */
+#define I2C_WR_SMB_ALERTEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_ALERTEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_ALERTEN(value)))
+#define I2C_BWR_SMB_ALERTEN(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field FACK[7] (RW)
+ *
+ * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
+ * according to the result of receiving data byte.
+ *
+ * Values:
+ * - 0b0 - An ACK or NACK is sent on the following receiving data byte
+ * - 0b1 - Writing 0 to TXAK after receiving a data byte generates an ACK.
+ *     Writing 1 to TXAK after receiving a data byte generates a NACK.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_FACK field. */
+#define I2C_RD_SMB_FACK(base) ((I2C_SMB_REG(base) & I2C_SMB_FACK_MASK) >> I2C_SMB_FACK_SHIFT)
+#define I2C_BRD_SMB_FACK(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT))
+
+/*! @brief Set the FACK field to a new value. */
+#define I2C_WR_SMB_FACK(base, value) (I2C_RMW_SMB(base, (I2C_SMB_FACK_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_FACK(value)))
+#define I2C_BWR_SMB_FACK(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_A2 - I2C Address Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A2 - I2C Address Register 2 (RW)
+ *
+ * Reset value: 0xC2U
+ */
+/*!
+ * @name Constants and macros for entire I2C_A2 register
+ */
+/*@{*/
+#define I2C_RD_A2(base)          (I2C_A2_REG(base))
+#define I2C_WR_A2(base, value)   (I2C_A2_REG(base) = (value))
+#define I2C_RMW_A2(base, mask, value) (I2C_WR_A2(base, (I2C_RD_A2(base) & ~(mask)) | (value)))
+#define I2C_SET_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) |  (value)))
+#define I2C_CLR_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) & ~(value)))
+#define I2C_TOG_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A2 bitfields
+ */
+
+/*!
+ * @name Register I2C_A2, field SAD[7:1] (RW)
+ *
+ * Contains the slave address used by the SMBus. This field is used on the
+ * device default address or other related addresses.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A2_SAD field. */
+#define I2C_RD_A2_SAD(base)  ((I2C_A2_REG(base) & I2C_A2_SAD_MASK) >> I2C_A2_SAD_SHIFT)
+#define I2C_BRD_A2_SAD(base) (I2C_RD_A2_SAD(base))
+
+/*! @brief Set the SAD field to a new value. */
+#define I2C_WR_A2_SAD(base, value) (I2C_RMW_A2(base, I2C_A2_SAD_MASK, I2C_A2_SAD(value)))
+#define I2C_BWR_A2_SAD(base, value) (I2C_WR_A2_SAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTH - I2C SCL Low Timeout Register High
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTH - I2C SCL Low Timeout Register High (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTH register
+ */
+/*@{*/
+#define I2C_RD_SLTH(base)        (I2C_SLTH_REG(base))
+#define I2C_WR_SLTH(base, value) (I2C_SLTH_REG(base) = (value))
+#define I2C_RMW_SLTH(base, mask, value) (I2C_WR_SLTH(base, (I2C_RD_SLTH(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) |  (value)))
+#define I2C_CLR_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) & ~(value)))
+#define I2C_TOG_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTL - I2C SCL Low Timeout Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTL register
+ */
+/*@{*/
+#define I2C_RD_SLTL(base)        (I2C_SLTL_REG(base))
+#define I2C_WR_SLTL(base, value) (I2C_SLTL_REG(base) = (value))
+#define I2C_RMW_SLTL(base, mask, value) (I2C_WR_SLTL(base, (I2C_RD_SLTL(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) |  (value)))
+#define I2C_CLR_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) & ~(value)))
+#define I2C_TOG_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 I2S
+ *
+ * Inter-IC Sound / Synchronous Audio Interface
+ *
+ * Registers defined in this header file:
+ * - I2S_TCSR - SAI Transmit Control Register
+ * - I2S_TCR1 - SAI Transmit Configuration 1 Register
+ * - I2S_TCR2 - SAI Transmit Configuration 2 Register
+ * - I2S_TCR3 - SAI Transmit Configuration 3 Register
+ * - I2S_TCR4 - SAI Transmit Configuration 4 Register
+ * - I2S_TCR5 - SAI Transmit Configuration 5 Register
+ * - I2S_TDR - SAI Transmit Data Register
+ * - I2S_TFR - SAI Transmit FIFO Register
+ * - I2S_TMR - SAI Transmit Mask Register
+ * - I2S_RCSR - SAI Receive Control Register
+ * - I2S_RCR1 - SAI Receive Configuration 1 Register
+ * - I2S_RCR2 - SAI Receive Configuration 2 Register
+ * - I2S_RCR3 - SAI Receive Configuration 3 Register
+ * - I2S_RCR4 - SAI Receive Configuration 4 Register
+ * - I2S_RCR5 - SAI Receive Configuration 5 Register
+ * - I2S_RDR - SAI Receive Data Register
+ * - I2S_RFR - SAI Receive FIFO Register
+ * - I2S_RMR - SAI Receive Mask Register
+ * - I2S_MCR - SAI MCLK Control Register
+ * - I2S_MDR - SAI MCLK Divide Register
+ */
+
+#define I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */
+#define I2S0_IDX (0U) /*!< Instance number for I2S0. */
+
+/*******************************************************************************
+ * I2S_TCSR - SAI Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCSR - SAI Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCSR register
+ */
+/*@{*/
+#define I2S_RD_TCSR(base)        (I2S_TCSR_REG(base))
+#define I2S_WR_TCSR(base, value) (I2S_TCSR_REG(base) = (value))
+#define I2S_RMW_TCSR(base, mask, value) (I2S_WR_TCSR(base, (I2S_RD_TCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) |  (value)))
+#define I2S_CLR_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) & ~(value)))
+#define I2S_TOG_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_TCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRDE field. */
+#define I2S_RD_TCSR_FRDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRDE_MASK) >> I2S_TCSR_FRDE_SHIFT)
+#define I2S_BRD_TCSR_FRDE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRDE_SHIFT))
+
+/*! @brief Set the FRDE field to a new value. */
+#define I2S_WR_TCSR_FRDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FRDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FRDE(value)))
+#define I2S_BWR_TCSR_FRDE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWDE field. */
+#define I2S_RD_TCSR_FWDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWDE_MASK) >> I2S_TCSR_FWDE_SHIFT)
+#define I2S_BRD_TCSR_FWDE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_TCSR_FWDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWDE(value)))
+#define I2S_BWR_TCSR_FWDE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRIE field. */
+#define I2S_RD_TCSR_FRIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRIE_MASK) >> I2S_TCSR_FRIE_SHIFT)
+#define I2S_BRD_TCSR_FRIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRIE_SHIFT))
+
+/*! @brief Set the FRIE field to a new value. */
+#define I2S_WR_TCSR_FRIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FRIE(value)))
+#define I2S_BWR_TCSR_FRIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWIE field. */
+#define I2S_RD_TCSR_FWIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWIE_MASK) >> I2S_TCSR_FWIE_SHIFT)
+#define I2S_BRD_TCSR_FWIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_TCSR_FWIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWIE(value)))
+#define I2S_BWR_TCSR_FWIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEIE field. */
+#define I2S_RD_TCSR_FEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEIE_MASK) >> I2S_TCSR_FEIE_SHIFT)
+#define I2S_BRD_TCSR_FEIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_TCSR_FEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEIE(value)))
+#define I2S_BWR_TCSR_FEIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEIE field. */
+#define I2S_RD_TCSR_SEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEIE_MASK) >> I2S_TCSR_SEIE_SHIFT)
+#define I2S_BRD_TCSR_SEIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_TCSR_SEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEIE(value)))
+#define I2S_BWR_TCSR_SEIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSIE field. */
+#define I2S_RD_TCSR_WSIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSIE_MASK) >> I2S_TCSR_WSIE_SHIFT)
+#define I2S_BRD_TCSR_WSIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_TCSR_WSIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_WSIE(value)))
+#define I2S_BWR_TCSR_WSIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled transmit channel FIFO is
+ * less than or equal to the transmit FIFO watermark.
+ *
+ * Values:
+ * - 0b0 - Transmit FIFO watermark has not been reached.
+ * - 0b1 - Transmit FIFO watermark has been reached.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRF field. */
+#define I2S_RD_TCSR_FRF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRF_MASK) >> I2S_TCSR_FRF_SHIFT)
+#define I2S_BRD_TCSR_FRF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled transmit FIFO is empty.
+ *
+ * Values:
+ * - 0b0 - No enabled transmit FIFO is empty.
+ * - 0b1 - Enabled transmit FIFO is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWF field. */
+#define I2S_RD_TCSR_FWF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWF_MASK) >> I2S_TCSR_FWF_SHIFT)
+#define I2S_BRD_TCSR_FWF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
+ * field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Transmit underrun not detected.
+ * - 0b1 - Transmit underrun detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEF field. */
+#define I2S_RD_TCSR_FEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEF_MASK) >> I2S_TCSR_FEF_SHIFT)
+#define I2S_BRD_TCSR_FEF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_TCSR_FEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEF(value)))
+#define I2S_BWR_TCSR_FEF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Sync error not detected.
+ * - 0b1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEF field. */
+#define I2S_RD_TCSR_SEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEF_MASK) >> I2S_TCSR_SEF_SHIFT)
+#define I2S_BRD_TCSR_SEF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_TCSR_SEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEF(value)))
+#define I2S_BWR_TCSR_SEF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Start of word not detected.
+ * - 0b1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSF field. */
+#define I2S_RD_TCSR_WSF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSF_MASK) >> I2S_TCSR_WSF_SHIFT)
+#define I2S_BRD_TCSR_WSF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_TCSR_WSF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK), I2S_TCSR_WSF(value)))
+#define I2S_BWR_TCSR_WSF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SR[24] (RW)
+ *
+ * When set, resets the internal transmitter logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SR field. */
+#define I2S_RD_TCSR_SR(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SR_MASK) >> I2S_TCSR_SR_SHIFT)
+#define I2S_BRD_TCSR_SR(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_TCSR_SR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SR(value)))
+#define I2S_BWR_TCSR_SR(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the transmitter is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_TCSR_FR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FR(value)))
+#define I2S_BWR_TCSR_FR(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field BCE[28] (RW)
+ *
+ * Enables the transmit bit clock, separately from the TE. This field is
+ * automatically set whenever TE is set. When software clears this field, the transmit
+ * bit clock remains enabled, and this bit remains set, until the end of the
+ * current frame.
+ *
+ * Values:
+ * - 0b0 - Transmit bit clock is disabled.
+ * - 0b1 - Transmit bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_BCE field. */
+#define I2S_RD_TCSR_BCE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_BCE_MASK) >> I2S_TCSR_BCE_SHIFT)
+#define I2S_BRD_TCSR_BCE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_TCSR_BCE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_BCE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_BCE(value)))
+#define I2S_BWR_TCSR_BCE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables transmitter operation in Debug mode. The transmit bit clock
+ * is not affected by debug mode.
+ *
+ * Values:
+ * - 0b0 - Transmitter is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 0b1 - Transmitter is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_DBGE field. */
+#define I2S_RD_TCSR_DBGE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_DBGE_MASK) >> I2S_TCSR_DBGE_SHIFT)
+#define I2S_BRD_TCSR_DBGE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_TCSR_DBGE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_DBGE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_DBGE(value)))
+#define I2S_BWR_TCSR_DBGE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field STOPE[30] (RW)
+ *
+ * Configures transmitter operation in Stop mode. This field is ignored and the
+ * transmitter is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0b0 - Transmitter disabled in Stop mode.
+ * - 0b1 - Transmitter enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_STOPE field. */
+#define I2S_RD_TCSR_STOPE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_STOPE_MASK) >> I2S_TCSR_STOPE_SHIFT)
+#define I2S_BRD_TCSR_STOPE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_TCSR_STOPE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_STOPE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_STOPE(value)))
+#define I2S_BWR_TCSR_STOPE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field TE[31] (RW)
+ *
+ * Enables/disables the transmitter. When software clears this field, the
+ * transmitter remains enabled, and this bit remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0b0 - Transmitter is disabled.
+ * - 0b1 - Transmitter is enabled, or transmitter has been disabled and has not
+ *     yet reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_TE field. */
+#define I2S_RD_TCSR_TE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_TE_MASK) >> I2S_TCSR_TE_SHIFT)
+#define I2S_BRD_TCSR_TE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT))
+
+/*! @brief Set the TE field to a new value. */
+#define I2S_WR_TCSR_TE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_TE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_TE(value)))
+#define I2S_BWR_TCSR_TE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR1 - SAI Transmit Configuration 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR1 register
+ */
+/*@{*/
+#define I2S_RD_TCR1(base)        (I2S_TCR1_REG(base))
+#define I2S_WR_TCR1(base, value) (I2S_TCR1_REG(base) = (value))
+#define I2S_RMW_TCR1(base, mask, value) (I2S_WR_TCR1(base, (I2S_RD_TCR1(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) |  (value)))
+#define I2S_CLR_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) & ~(value)))
+#define I2S_TOG_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR1, field TFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled transmit channels.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR1_TFW field. */
+#define I2S_RD_TCR1_TFW(base) ((I2S_TCR1_REG(base) & I2S_TCR1_TFW_MASK) >> I2S_TCR1_TFW_SHIFT)
+#define I2S_BRD_TCR1_TFW(base) (I2S_RD_TCR1_TFW(base))
+
+/*! @brief Set the TFW field to a new value. */
+#define I2S_WR_TCR1_TFW(base, value) (I2S_RMW_TCR1(base, I2S_TCR1_TFW_MASK, I2S_TCR1_TFW(value)))
+#define I2S_BWR_TCR1_TFW(base, value) (I2S_WR_TCR1_TFW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR2 - SAI Transmit Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR2 register
+ */
+/*@{*/
+#define I2S_RD_TCR2(base)        (I2S_TCR2_REG(base))
+#define I2S_WR_TCR2(base, value) (I2S_TCR2_REG(base) = (value))
+#define I2S_RMW_TCR2(base, mask, value) (I2S_WR_TCR2(base, (I2S_RD_TCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) |  (value)))
+#define I2S_CLR_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) & ~(value)))
+#define I2S_TOG_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_DIV field. */
+#define I2S_RD_TCR2_DIV(base) ((I2S_TCR2_REG(base) & I2S_TCR2_DIV_MASK) >> I2S_TCR2_DIV_SHIFT)
+#define I2S_BRD_TCR2_DIV(base) (I2S_RD_TCR2_DIV(base))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_TCR2_DIV(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_DIV_MASK, I2S_TCR2_DIV(value)))
+#define I2S_BWR_TCR2_DIV(base, value) (I2S_WR_TCR2_DIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is generated externally in Slave mode.
+ * - 0b1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCD field. */
+#define I2S_RD_TCR2_BCD(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCD_MASK) >> I2S_TCR2_BCD_SHIFT)
+#define I2S_BRD_TCR2_BCD(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_TCR2_BCD(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCD_MASK, I2S_TCR2_BCD(value)))
+#define I2S_BWR_TCR2_BCD(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 0b1 - Bit clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCP field. */
+#define I2S_RD_TCR2_BCP(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCP_MASK) >> I2S_TCR2_BCP_SHIFT)
+#define I2S_BRD_TCR2_BCP(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_TCR2_BCP(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCP_MASK, I2S_TCR2_BCP(value)))
+#define I2S_BWR_TCR2_BCP(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 0b00 - Bus Clock selected.
+ * - 0b01 - Master Clock (MCLK) 1 option selected.
+ * - 0b10 - Master Clock (MCLK) 2 option selected.
+ * - 0b11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_MSEL field. */
+#define I2S_RD_TCR2_MSEL(base) ((I2S_TCR2_REG(base) & I2S_TCR2_MSEL_MASK) >> I2S_TCR2_MSEL_SHIFT)
+#define I2S_BRD_TCR2_MSEL(base) (I2S_RD_TCR2_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_TCR2_MSEL(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_MSEL_MASK, I2S_TCR2_MSEL(value)))
+#define I2S_BWR_TCR2_MSEL(base, value) (I2S_WR_TCR2_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the
+ * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
+ * input as if the clock was externally generated). This has the effect of
+ * decreasing the data input setup time, but increasing the data output valid time. The
+ * slave mode timing from the datasheet should be used for the transmitter when
+ * this bit is set. In synchronous mode, this bit allows the transmitter to use
+ * the slave mode timing from the datasheet, while the receiver uses the master
+ * mode timing. This field has no effect when configured for an externally generated
+ * bit clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCI field. */
+#define I2S_RD_TCR2_BCI(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCI_MASK) >> I2S_TCR2_BCI_SHIFT)
+#define I2S_BRD_TCR2_BCI(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_TCR2_BCI(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCI_MASK, I2S_TCR2_BCI(value)))
+#define I2S_BWR_TCR2_BCI(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the transmitter. When the transmitter
+ * is configured in asynchronous mode and this bit is set, the transmitter is
+ * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the transmitter continues to use the
+ * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
+ * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
+ * the same value. When both are set, the transmitter and receiver are both
+ * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
+ * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
+ * peripheral.
+ *
+ * Values:
+ * - 0b0 - Use the normal bit clock source.
+ * - 0b1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCS field. */
+#define I2S_RD_TCR2_BCS(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCS_MASK) >> I2S_TCR2_BCS_SHIFT)
+#define I2S_BRD_TCR2_BCS(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_TCR2_BCS(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCS_MASK, I2S_TCR2_BCS(value)))
+#define I2S_BWR_TCR2_BCS(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the receiver or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 0b00 - Asynchronous mode.
+ * - 0b01 - Synchronous with receiver.
+ * - 0b10 - Synchronous with another SAI transmitter.
+ * - 0b11 - Synchronous with another SAI receiver.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_SYNC field. */
+#define I2S_RD_TCR2_SYNC(base) ((I2S_TCR2_REG(base) & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT)
+#define I2S_BRD_TCR2_SYNC(base) (I2S_RD_TCR2_SYNC(base))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_TCR2_SYNC(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_SYNC_MASK, I2S_TCR2_SYNC(value)))
+#define I2S_BWR_TCR2_SYNC(base, value) (I2S_WR_TCR2_SYNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR3 - SAI Transmit Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR3 register
+ */
+/*@{*/
+#define I2S_RD_TCR3(base)        (I2S_TCR3_REG(base))
+#define I2S_WR_TCR3(base, value) (I2S_TCR3_REG(base) = (value))
+#define I2S_RMW_TCR3(base, mask, value) (I2S_WR_TCR3(base, (I2S_RD_TCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) |  (value)))
+#define I2S_CLR_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) & ~(value)))
+#define I2S_TOG_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word sets the start of word flag. The value written must be
+ * one less than the word number. For example, writing 0 configures the first
+ * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
+ * start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_WDFL field. */
+#define I2S_RD_TCR3_WDFL(base) ((I2S_TCR3_REG(base) & I2S_TCR3_WDFL_MASK) >> I2S_TCR3_WDFL_SHIFT)
+#define I2S_BRD_TCR3_WDFL(base) (I2S_RD_TCR3_WDFL(base))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_TCR3_WDFL(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_WDFL_MASK, I2S_TCR3_WDFL(value)))
+#define I2S_BWR_TCR3_WDFL(base, value) (I2S_WR_TCR3_WDFL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR3, field TCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for transmit operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0b00 - Transmit data channel N is disabled.
+ * - 0b01 - Transmit data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_TCE field. */
+#define I2S_RD_TCR3_TCE(base) ((I2S_TCR3_REG(base) & I2S_TCR3_TCE_MASK) >> I2S_TCR3_TCE_SHIFT)
+#define I2S_BRD_TCR3_TCE(base) (I2S_RD_TCR3_TCE(base))
+
+/*! @brief Set the TCE field to a new value. */
+#define I2S_WR_TCR3_TCE(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_TCE_MASK, I2S_TCR3_TCE(value)))
+#define I2S_BWR_TCR3_TCE(base, value) (I2S_WR_TCR3_TCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR4 - SAI Transmit Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR4 register
+ */
+/*@{*/
+#define I2S_RD_TCR4(base)        (I2S_TCR4_REG(base))
+#define I2S_WR_TCR4(base, value) (I2S_TCR4_REG(base) = (value))
+#define I2S_RMW_TCR4(base, mask, value) (I2S_WR_TCR4(base, (I2S_RD_TCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) |  (value)))
+#define I2S_CLR_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) & ~(value)))
+#define I2S_TOG_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is generated externally in Slave mode.
+ * - 0b1 - Frame sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSD field. */
+#define I2S_RD_TCR4_FSD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSD_MASK) >> I2S_TCR4_FSD_SHIFT)
+#define I2S_BRD_TCR4_FSD(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_TCR4_FSD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSD_MASK, I2S_TCR4_FSD(value)))
+#define I2S_BWR_TCR4_FSD(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is active high.
+ * - 0b1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSP field. */
+#define I2S_RD_TCR4_FSP(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSP_MASK) >> I2S_TCR4_FSP_SHIFT)
+#define I2S_BRD_TCR4_FSP(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_TCR4_FSP(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSP_MASK, I2S_TCR4_FSP(value)))
+#define I2S_BWR_TCR4_FSP(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Frame sync asserts with the first bit of the frame.
+ * - 0b1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSE field. */
+#define I2S_RD_TCR4_FSE(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSE_MASK) >> I2S_TCR4_FSE_SHIFT)
+#define I2S_BRD_TCR4_FSE(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_TCR4_FSE(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSE_MASK, I2S_TCR4_FSE(value)))
+#define I2S_BWR_TCR4_FSE(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is transmitted first.
+ *
+ * Values:
+ * - 0b0 - LSB is transmitted first.
+ * - 0b1 - MSB is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_MF field. */
+#define I2S_RD_TCR4_MF(base) ((I2S_TCR4_REG(base) & I2S_TCR4_MF_MASK) >> I2S_TCR4_MF_SHIFT)
+#define I2S_BRD_TCR4_MF(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_TCR4_MF(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_MF_MASK, I2S_TCR4_MF(value)))
+#define I2S_BWR_TCR4_MF(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_SYWD field. */
+#define I2S_RD_TCR4_SYWD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_SYWD_MASK) >> I2S_TCR4_SYWD_SHIFT)
+#define I2S_BRD_TCR4_SYWD(base) (I2S_RD_TCR4_SYWD(base))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_TCR4_SYWD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_SYWD_MASK, I2S_TCR4_SYWD(value)))
+#define I2S_BWR_TCR4_SYWD(base, value) (I2S_WR_TCR4_SYWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FRSZ field. */
+#define I2S_RD_TCR4_FRSZ(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FRSZ_MASK) >> I2S_TCR4_FRSZ_SHIFT)
+#define I2S_BRD_TCR4_FRSZ(base) (I2S_RD_TCR4_FRSZ(base))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_TCR4_FRSZ(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FRSZ_MASK, I2S_TCR4_FRSZ(value)))
+#define I2S_BWR_TCR4_FRSZ(base, value) (I2S_WR_TCR4_FRSZ(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR5 - SAI Transmit Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR5 register
+ */
+/*@{*/
+#define I2S_RD_TCR5(base)        (I2S_TCR5_REG(base))
+#define I2S_WR_TCR5(base, value) (I2S_TCR5_REG(base) = (value))
+#define I2S_RMW_TCR5(base, mask, value) (I2S_WR_TCR5(base, (I2S_RD_TCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) |  (value)))
+#define I2S_CLR_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) & ~(value)))
+#define I2S_TOG_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit transmitted for each word in the
+ * frame. If configured for MSB First, the index of the next bit transmitted is
+ * one less than the current bit transmitted. If configured for LSB First, the
+ * index of the next bit transmitted is one more than the current bit transmitted.
+ * The value written must be greater than or equal to the word width when
+ * configured for MSB First. The value written must be less than or equal to 31-word width
+ * when configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_FBT field. */
+#define I2S_RD_TCR5_FBT(base) ((I2S_TCR5_REG(base) & I2S_TCR5_FBT_MASK) >> I2S_TCR5_FBT_SHIFT)
+#define I2S_BRD_TCR5_FBT(base) (I2S_RD_TCR5_FBT(base))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_TCR5_FBT(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_FBT_MASK, I2S_TCR5_FBT(value)))
+#define I2S_BWR_TCR5_FBT(base, value) (I2S_WR_TCR5_FBT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_W0W field. */
+#define I2S_RD_TCR5_W0W(base) ((I2S_TCR5_REG(base) & I2S_TCR5_W0W_MASK) >> I2S_TCR5_W0W_SHIFT)
+#define I2S_BRD_TCR5_W0W(base) (I2S_RD_TCR5_W0W(base))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_TCR5_W0W(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_W0W_MASK, I2S_TCR5_W0W(value)))
+#define I2S_BWR_TCR5_W0W(base, value) (I2S_WR_TCR5_W0W(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_WNW field. */
+#define I2S_RD_TCR5_WNW(base) ((I2S_TCR5_REG(base) & I2S_TCR5_WNW_MASK) >> I2S_TCR5_WNW_SHIFT)
+#define I2S_BRD_TCR5_WNW(base) (I2S_RD_TCR5_WNW(base))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_TCR5_WNW(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_WNW_MASK, I2S_TCR5_WNW(value)))
+#define I2S_BWR_TCR5_WNW(base, value) (I2S_WR_TCR5_WNW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TDR - SAI Transmit Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TDR - SAI Transmit Data Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TDR register
+ */
+/*@{*/
+#define I2S_RD_TDR(base, index)  (I2S_TDR_REG(base, index))
+#define I2S_WR_TDR(base, index, value) (I2S_TDR_REG(base, index) = (value))
+#define I2S_RMW_TDR(base, index, mask, value) (I2S_WR_TDR(base, index, (I2S_RD_TDR(base, index) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TFR - SAI Transmit FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TFR - SAI Transmit FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TFR register
+ */
+/*@{*/
+#define I2S_RD_TFR(base, index)  (I2S_TFR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TFR bitfields
+ */
+
+/*!
+ * @name Register I2S_TFR, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for transmit data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TFR_RFP field. */
+#define I2S_RD_TFR_RFP(base, index) ((I2S_TFR_REG(base, index) & I2S_TFR_RFP_MASK) >> I2S_TFR_RFP_SHIFT)
+#define I2S_BRD_TFR_RFP(base, index) (I2S_RD_TFR_RFP(base, index))
+/*@}*/
+
+/*!
+ * @name Register I2S_TFR, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for transmit data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TFR_WFP field. */
+#define I2S_RD_TFR_WFP(base, index) ((I2S_TFR_REG(base, index) & I2S_TFR_WFP_MASK) >> I2S_TFR_WFP_SHIFT)
+#define I2S_BRD_TFR_WFP(base, index) (I2S_RD_TFR_WFP(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TMR - SAI Transmit Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TMR - SAI Transmit Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When TCSR[TE] is first set At
+ * the end of each frame. This allows the masked words in each frame to change
+ * from frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TMR register
+ */
+/*@{*/
+#define I2S_RD_TMR(base)         (I2S_TMR_REG(base))
+#define I2S_WR_TMR(base, value)  (I2S_TMR_REG(base) = (value))
+#define I2S_RMW_TMR(base, mask, value) (I2S_WR_TMR(base, (I2S_RD_TMR(base) & ~(mask)) | (value)))
+#define I2S_SET_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) |  (value)))
+#define I2S_CLR_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) & ~(value)))
+#define I2S_TOG_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCSR - SAI Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCSR - SAI Receive Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCSR register
+ */
+/*@{*/
+#define I2S_RD_RCSR(base)        (I2S_RCSR_REG(base))
+#define I2S_WR_RCSR(base, value) (I2S_RCSR_REG(base) = (value))
+#define I2S_RMW_RCSR(base, mask, value) (I2S_WR_RCSR(base, (I2S_RD_RCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) |  (value)))
+#define I2S_CLR_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) & ~(value)))
+#define I2S_TOG_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_RCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRDE field. */
+#define I2S_RD_RCSR_FRDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRDE_MASK) >> I2S_RCSR_FRDE_SHIFT)
+#define I2S_BRD_RCSR_FRDE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRDE_SHIFT))
+
+/*! @brief Set the FRDE field to a new value. */
+#define I2S_WR_RCSR_FRDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FRDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FRDE(value)))
+#define I2S_BWR_RCSR_FRDE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWDE field. */
+#define I2S_RD_RCSR_FWDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWDE_MASK) >> I2S_RCSR_FWDE_SHIFT)
+#define I2S_BRD_RCSR_FWDE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_RCSR_FWDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWDE(value)))
+#define I2S_BWR_RCSR_FWDE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRIE field. */
+#define I2S_RD_RCSR_FRIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRIE_MASK) >> I2S_RCSR_FRIE_SHIFT)
+#define I2S_BRD_RCSR_FRIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRIE_SHIFT))
+
+/*! @brief Set the FRIE field to a new value. */
+#define I2S_WR_RCSR_FRIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FRIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FRIE(value)))
+#define I2S_BWR_RCSR_FRIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWIE field. */
+#define I2S_RD_RCSR_FWIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWIE_MASK) >> I2S_RCSR_FWIE_SHIFT)
+#define I2S_BRD_RCSR_FWIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_RCSR_FWIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWIE(value)))
+#define I2S_BWR_RCSR_FWIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEIE field. */
+#define I2S_RD_RCSR_FEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEIE_MASK) >> I2S_RCSR_FEIE_SHIFT)
+#define I2S_BRD_RCSR_FEIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_RCSR_FEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEIE(value)))
+#define I2S_BWR_RCSR_FEIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEIE field. */
+#define I2S_RD_RCSR_SEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEIE_MASK) >> I2S_RCSR_SEIE_SHIFT)
+#define I2S_BRD_RCSR_SEIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_RCSR_SEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEIE(value)))
+#define I2S_BWR_RCSR_SEIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSIE field. */
+#define I2S_RD_RCSR_WSIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSIE_MASK) >> I2S_RCSR_WSIE_SHIFT)
+#define I2S_BRD_RCSR_WSIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_RCSR_WSIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_WSIE(value)))
+#define I2S_BWR_RCSR_WSIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled receive channel FIFO is
+ * greater than the receive FIFO watermark.
+ *
+ * Values:
+ * - 0b0 - Receive FIFO watermark not reached.
+ * - 0b1 - Receive FIFO watermark has been reached.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRF field. */
+#define I2S_RD_RCSR_FRF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRF_MASK) >> I2S_RCSR_FRF_SHIFT)
+#define I2S_BRD_RCSR_FRF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled receive FIFO is full.
+ *
+ * Values:
+ * - 0b0 - No enabled receive FIFO is full.
+ * - 0b1 - Enabled receive FIFO is full.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWF field. */
+#define I2S_RD_RCSR_FWF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWF_MASK) >> I2S_RCSR_FWF_SHIFT)
+#define I2S_BRD_RCSR_FWF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
+ * this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Receive overflow not detected.
+ * - 0b1 - Receive overflow detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEF field. */
+#define I2S_RD_RCSR_FEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEF_MASK) >> I2S_RCSR_FEF_SHIFT)
+#define I2S_BRD_RCSR_FEF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_RCSR_FEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEF(value)))
+#define I2S_BWR_RCSR_FEF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Sync error not detected.
+ * - 0b1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEF field. */
+#define I2S_RD_RCSR_SEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEF_MASK) >> I2S_RCSR_SEF_SHIFT)
+#define I2S_BRD_RCSR_SEF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_RCSR_SEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEF(value)))
+#define I2S_BWR_RCSR_SEF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Start of word not detected.
+ * - 0b1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSF field. */
+#define I2S_RD_RCSR_WSF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSF_MASK) >> I2S_RCSR_WSF_SHIFT)
+#define I2S_BRD_RCSR_WSF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_RCSR_WSF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK), I2S_RCSR_WSF(value)))
+#define I2S_BWR_RCSR_WSF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SR[24] (RW)
+ *
+ * Resets the internal receiver logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SR field. */
+#define I2S_RD_RCSR_SR(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SR_MASK) >> I2S_RCSR_SR_SHIFT)
+#define I2S_BRD_RCSR_SR(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_RCSR_SR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SR(value)))
+#define I2S_BWR_RCSR_SR(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the receiver is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_RCSR_FR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FR(value)))
+#define I2S_BWR_RCSR_FR(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field BCE[28] (RW)
+ *
+ * Enables the receive bit clock, separately from RE. This field is
+ * automatically set whenever RE is set. When software clears this field, the receive bit
+ * clock remains enabled, and this field remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0b0 - Receive bit clock is disabled.
+ * - 0b1 - Receive bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_BCE field. */
+#define I2S_RD_RCSR_BCE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_BCE_MASK) >> I2S_RCSR_BCE_SHIFT)
+#define I2S_BRD_RCSR_BCE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_RCSR_BCE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_BCE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_BCE(value)))
+#define I2S_BWR_RCSR_BCE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables receiver operation in Debug mode. The receive bit clock is
+ * not affected by Debug mode.
+ *
+ * Values:
+ * - 0b0 - Receiver is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 0b1 - Receiver is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_DBGE field. */
+#define I2S_RD_RCSR_DBGE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_DBGE_MASK) >> I2S_RCSR_DBGE_SHIFT)
+#define I2S_BRD_RCSR_DBGE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_RCSR_DBGE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_DBGE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_DBGE(value)))
+#define I2S_BWR_RCSR_DBGE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field STOPE[30] (RW)
+ *
+ * Configures receiver operation in Stop mode. This bit is ignored and the
+ * receiver is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0b0 - Receiver disabled in Stop mode.
+ * - 0b1 - Receiver enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_STOPE field. */
+#define I2S_RD_RCSR_STOPE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_STOPE_MASK) >> I2S_RCSR_STOPE_SHIFT)
+#define I2S_BRD_RCSR_STOPE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_RCSR_STOPE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_STOPE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_STOPE(value)))
+#define I2S_BWR_RCSR_STOPE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field RE[31] (RW)
+ *
+ * Enables/disables the receiver. When software clears this field, the receiver
+ * remains enabled, and this bit remains set, until the end of the current frame.
+ *
+ * Values:
+ * - 0b0 - Receiver is disabled.
+ * - 0b1 - Receiver is enabled, or receiver has been disabled and has not yet
+ *     reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_RE field. */
+#define I2S_RD_RCSR_RE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_RE_MASK) >> I2S_RCSR_RE_SHIFT)
+#define I2S_BRD_RCSR_RE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT))
+
+/*! @brief Set the RE field to a new value. */
+#define I2S_WR_RCSR_RE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_RE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_RE(value)))
+#define I2S_BWR_RCSR_RE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR1 - SAI Receive Configuration 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR1 register
+ */
+/*@{*/
+#define I2S_RD_RCR1(base)        (I2S_RCR1_REG(base))
+#define I2S_WR_RCR1(base, value) (I2S_RCR1_REG(base) = (value))
+#define I2S_RMW_RCR1(base, mask, value) (I2S_WR_RCR1(base, (I2S_RD_RCR1(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) |  (value)))
+#define I2S_CLR_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) & ~(value)))
+#define I2S_TOG_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR1, field RFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled receiver channels.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR1_RFW field. */
+#define I2S_RD_RCR1_RFW(base) ((I2S_RCR1_REG(base) & I2S_RCR1_RFW_MASK) >> I2S_RCR1_RFW_SHIFT)
+#define I2S_BRD_RCR1_RFW(base) (I2S_RD_RCR1_RFW(base))
+
+/*! @brief Set the RFW field to a new value. */
+#define I2S_WR_RCR1_RFW(base, value) (I2S_RMW_RCR1(base, I2S_RCR1_RFW_MASK, I2S_RCR1_RFW(value)))
+#define I2S_BWR_RCR1_RFW(base, value) (I2S_WR_RCR1_RFW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR2 - SAI Receive Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR2 register
+ */
+/*@{*/
+#define I2S_RD_RCR2(base)        (I2S_RCR2_REG(base))
+#define I2S_WR_RCR2(base, value) (I2S_RCR2_REG(base) = (value))
+#define I2S_RMW_RCR2(base, mask, value) (I2S_WR_RCR2(base, (I2S_RD_RCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) |  (value)))
+#define I2S_CLR_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) & ~(value)))
+#define I2S_TOG_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_DIV field. */
+#define I2S_RD_RCR2_DIV(base) ((I2S_RCR2_REG(base) & I2S_RCR2_DIV_MASK) >> I2S_RCR2_DIV_SHIFT)
+#define I2S_BRD_RCR2_DIV(base) (I2S_RD_RCR2_DIV(base))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_RCR2_DIV(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_DIV_MASK, I2S_RCR2_DIV(value)))
+#define I2S_BWR_RCR2_DIV(base, value) (I2S_WR_RCR2_DIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is generated externally in Slave mode.
+ * - 0b1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCD field. */
+#define I2S_RD_RCR2_BCD(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCD_MASK) >> I2S_RCR2_BCD_SHIFT)
+#define I2S_BRD_RCR2_BCD(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_RCR2_BCD(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCD_MASK, I2S_RCR2_BCD(value)))
+#define I2S_BWR_RCR2_BCD(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit Clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 0b1 - Bit Clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCP field. */
+#define I2S_RD_RCR2_BCP(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCP_MASK) >> I2S_RCR2_BCP_SHIFT)
+#define I2S_BRD_RCR2_BCP(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_RCR2_BCP(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCP_MASK, I2S_RCR2_BCP(value)))
+#define I2S_BWR_RCR2_BCP(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 0b00 - Bus Clock selected.
+ * - 0b01 - Master Clock (MCLK) 1 option selected.
+ * - 0b10 - Master Clock (MCLK) 2 option selected.
+ * - 0b11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_MSEL field. */
+#define I2S_RD_RCR2_MSEL(base) ((I2S_RCR2_REG(base) & I2S_RCR2_MSEL_MASK) >> I2S_RCR2_MSEL_SHIFT)
+#define I2S_BRD_RCR2_MSEL(base) (I2S_RD_RCR2_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_RCR2_MSEL(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_MSEL_MASK, I2S_RCR2_MSEL(value)))
+#define I2S_BWR_RCR2_MSEL(base, value) (I2S_WR_RCR2_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the receiver
+ * is delayed by the pad output delay (the receiver is clocked by the pad input
+ * as if the clock was externally generated). This has the effect of decreasing
+ * the data input setup time, but increasing the data output valid time. The slave
+ * mode timing from the datasheet should be used for the receiver when this bit
+ * is set. In synchronous mode, this bit allows the receiver to use the slave mode
+ * timing from the datasheet, while the transmitter uses the master mode timing.
+ * This field has no effect when configured for an externally generated bit
+ * clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCI field. */
+#define I2S_RD_RCR2_BCI(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCI_MASK) >> I2S_RCR2_BCI_SHIFT)
+#define I2S_BRD_RCR2_BCI(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_RCR2_BCI(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCI_MASK, I2S_RCR2_BCI(value)))
+#define I2S_BWR_RCR2_BCI(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the receiver. When the receiver is
+ * configured in asynchronous mode and this bit is set, the receiver is clocked by
+ * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the receiver continues to use the receiver
+ * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
+ * mode, the transmitter BCS field and receiver BCS field must be set to the same
+ * value. When both are set, the transmitter and receiver are both clocked by the
+ * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
+ * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
+ *
+ * Values:
+ * - 0b0 - Use the normal bit clock source.
+ * - 0b1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCS field. */
+#define I2S_RD_RCR2_BCS(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCS_MASK) >> I2S_RCR2_BCS_SHIFT)
+#define I2S_BRD_RCR2_BCS(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_RCR2_BCS(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCS_MASK, I2S_RCR2_BCS(value)))
+#define I2S_BWR_RCR2_BCS(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the transmitter or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 0b00 - Asynchronous mode.
+ * - 0b01 - Synchronous with transmitter.
+ * - 0b10 - Synchronous with another SAI receiver.
+ * - 0b11 - Synchronous with another SAI transmitter.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_SYNC field. */
+#define I2S_RD_RCR2_SYNC(base) ((I2S_RCR2_REG(base) & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT)
+#define I2S_BRD_RCR2_SYNC(base) (I2S_RD_RCR2_SYNC(base))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_RCR2_SYNC(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_SYNC_MASK, I2S_RCR2_SYNC(value)))
+#define I2S_BWR_RCR2_SYNC(base, value) (I2S_WR_RCR2_SYNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR3 - SAI Receive Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR3 register
+ */
+/*@{*/
+#define I2S_RD_RCR3(base)        (I2S_RCR3_REG(base))
+#define I2S_WR_RCR3(base, value) (I2S_RCR3_REG(base) = (value))
+#define I2S_RMW_RCR3(base, mask, value) (I2S_WR_RCR3(base, (I2S_RD_RCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) |  (value)))
+#define I2S_CLR_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) & ~(value)))
+#define I2S_TOG_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word the start of word flag is set. The value written should
+ * be one less than the word number (for example, write zero to configure for
+ * the first word in the frame). When configured to a value greater than the Frame
+ * Size field, then the start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_WDFL field. */
+#define I2S_RD_RCR3_WDFL(base) ((I2S_RCR3_REG(base) & I2S_RCR3_WDFL_MASK) >> I2S_RCR3_WDFL_SHIFT)
+#define I2S_BRD_RCR3_WDFL(base) (I2S_RD_RCR3_WDFL(base))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_RCR3_WDFL(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_WDFL_MASK, I2S_RCR3_WDFL(value)))
+#define I2S_BWR_RCR3_WDFL(base, value) (I2S_WR_RCR3_WDFL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR3, field RCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for receive operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0b00 - Receive data channel N is disabled.
+ * - 0b01 - Receive data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_RCE field. */
+#define I2S_RD_RCR3_RCE(base) ((I2S_RCR3_REG(base) & I2S_RCR3_RCE_MASK) >> I2S_RCR3_RCE_SHIFT)
+#define I2S_BRD_RCR3_RCE(base) (I2S_RD_RCR3_RCE(base))
+
+/*! @brief Set the RCE field to a new value. */
+#define I2S_WR_RCR3_RCE(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_RCE_MASK, I2S_RCR3_RCE(value)))
+#define I2S_BWR_RCR3_RCE(base, value) (I2S_WR_RCR3_RCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR4 - SAI Receive Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR4 register
+ */
+/*@{*/
+#define I2S_RD_RCR4(base)        (I2S_RCR4_REG(base))
+#define I2S_WR_RCR4(base, value) (I2S_RCR4_REG(base) = (value))
+#define I2S_RMW_RCR4(base, mask, value) (I2S_WR_RCR4(base, (I2S_RD_RCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) |  (value)))
+#define I2S_CLR_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) & ~(value)))
+#define I2S_TOG_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame Sync is generated externally in Slave mode.
+ * - 0b1 - Frame Sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSD field. */
+#define I2S_RD_RCR4_FSD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSD_MASK) >> I2S_RCR4_FSD_SHIFT)
+#define I2S_BRD_RCR4_FSD(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_RCR4_FSD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSD_MASK, I2S_RCR4_FSD(value)))
+#define I2S_BWR_RCR4_FSD(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is active high.
+ * - 0b1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSP field. */
+#define I2S_RD_RCR4_FSP(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSP_MASK) >> I2S_RCR4_FSP_SHIFT)
+#define I2S_BRD_RCR4_FSP(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_RCR4_FSP(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSP_MASK, I2S_RCR4_FSP(value)))
+#define I2S_BWR_RCR4_FSP(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Frame sync asserts with the first bit of the frame.
+ * - 0b1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSE field. */
+#define I2S_RD_RCR4_FSE(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSE_MASK) >> I2S_RCR4_FSE_SHIFT)
+#define I2S_BRD_RCR4_FSE(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_RCR4_FSE(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSE_MASK, I2S_RCR4_FSE(value)))
+#define I2S_BWR_RCR4_FSE(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is received first.
+ *
+ * Values:
+ * - 0b0 - LSB is received first.
+ * - 0b1 - MSB is received first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_MF field. */
+#define I2S_RD_RCR4_MF(base) ((I2S_RCR4_REG(base) & I2S_RCR4_MF_MASK) >> I2S_RCR4_MF_SHIFT)
+#define I2S_BRD_RCR4_MF(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_RCR4_MF(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_MF_MASK, I2S_RCR4_MF(value)))
+#define I2S_BWR_RCR4_MF(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_SYWD field. */
+#define I2S_RD_RCR4_SYWD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_SYWD_MASK) >> I2S_RCR4_SYWD_SHIFT)
+#define I2S_BRD_RCR4_SYWD(base) (I2S_RD_RCR4_SYWD(base))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_RCR4_SYWD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_SYWD_MASK, I2S_RCR4_SYWD(value)))
+#define I2S_BWR_RCR4_SYWD(base, value) (I2S_WR_RCR4_SYWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FRSZ field. */
+#define I2S_RD_RCR4_FRSZ(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FRSZ_MASK) >> I2S_RCR4_FRSZ_SHIFT)
+#define I2S_BRD_RCR4_FRSZ(base) (I2S_RD_RCR4_FRSZ(base))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_RCR4_FRSZ(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FRSZ_MASK, I2S_RCR4_FRSZ(value)))
+#define I2S_BWR_RCR4_FRSZ(base, value) (I2S_WR_RCR4_FRSZ(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR5 - SAI Receive Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR5 register
+ */
+/*@{*/
+#define I2S_RD_RCR5(base)        (I2S_RCR5_REG(base))
+#define I2S_WR_RCR5(base, value) (I2S_RCR5_REG(base) = (value))
+#define I2S_RMW_RCR5(base, mask, value) (I2S_WR_RCR5(base, (I2S_RD_RCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) |  (value)))
+#define I2S_CLR_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) & ~(value)))
+#define I2S_TOG_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit received for each word in the
+ * frame. If configured for MSB First, the index of the next bit received is one less
+ * than the current bit received. If configured for LSB First, the index of the
+ * next bit received is one more than the current bit received. The value written
+ * must be greater than or equal to the word width when configured for MSB
+ * First. The value written must be less than or equal to 31-word width when
+ * configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_FBT field. */
+#define I2S_RD_RCR5_FBT(base) ((I2S_RCR5_REG(base) & I2S_RCR5_FBT_MASK) >> I2S_RCR5_FBT_SHIFT)
+#define I2S_BRD_RCR5_FBT(base) (I2S_RD_RCR5_FBT(base))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_RCR5_FBT(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_FBT_MASK, I2S_RCR5_FBT(value)))
+#define I2S_BWR_RCR5_FBT(base, value) (I2S_WR_RCR5_FBT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_W0W field. */
+#define I2S_RD_RCR5_W0W(base) ((I2S_RCR5_REG(base) & I2S_RCR5_W0W_MASK) >> I2S_RCR5_W0W_SHIFT)
+#define I2S_BRD_RCR5_W0W(base) (I2S_RD_RCR5_W0W(base))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_RCR5_W0W(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_W0W_MASK, I2S_RCR5_W0W(value)))
+#define I2S_BWR_RCR5_W0W(base, value) (I2S_WR_RCR5_W0W(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_WNW field. */
+#define I2S_RD_RCR5_WNW(base) ((I2S_RCR5_REG(base) & I2S_RCR5_WNW_MASK) >> I2S_RCR5_WNW_SHIFT)
+#define I2S_BRD_RCR5_WNW(base) (I2S_RD_RCR5_WNW(base))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_RCR5_WNW(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_WNW_MASK, I2S_RCR5_WNW(value)))
+#define I2S_BWR_RCR5_WNW(base, value) (I2S_WR_RCR5_WNW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RDR - SAI Receive Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RDR - SAI Receive Data Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Reading this register introduces one additional peripheral clock wait state
+ * on each read.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RDR register
+ */
+/*@{*/
+#define I2S_RD_RDR(base, index)  (I2S_RDR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RFR - SAI Receive FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RFR - SAI Receive FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RFR register
+ */
+/*@{*/
+#define I2S_RD_RFR(base, index)  (I2S_RFR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RFR bitfields
+ */
+
+/*!
+ * @name Register I2S_RFR, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for receive data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RFR_RFP field. */
+#define I2S_RD_RFR_RFP(base, index) ((I2S_RFR_REG(base, index) & I2S_RFR_RFP_MASK) >> I2S_RFR_RFP_SHIFT)
+#define I2S_BRD_RFR_RFP(base, index) (I2S_RD_RFR_RFP(base, index))
+/*@}*/
+
+/*!
+ * @name Register I2S_RFR, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for receive data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RFR_WFP field. */
+#define I2S_RD_RFR_WFP(base, index) ((I2S_RFR_REG(base, index) & I2S_RFR_WFP_MASK) >> I2S_RFR_WFP_SHIFT)
+#define I2S_BRD_RFR_WFP(base, index) (I2S_RD_RFR_WFP(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RMR - SAI Receive Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RMR - SAI Receive Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When RCSR[RE] is first set At
+ * the end of each frame This allows the masked words in each frame to change from
+ * frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RMR register
+ */
+/*@{*/
+#define I2S_RD_RMR(base)         (I2S_RMR_REG(base))
+#define I2S_WR_RMR(base, value)  (I2S_RMR_REG(base) = (value))
+#define I2S_RMW_RMR(base, mask, value) (I2S_WR_RMR(base, (I2S_RD_RMR(base) & ~(mask)) | (value)))
+#define I2S_SET_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) |  (value)))
+#define I2S_CLR_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) & ~(value)))
+#define I2S_TOG_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MCR - SAI MCLK Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MCR - SAI MCLK Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Control Register (MCR) controls the clock source and direction of
+ * the audio master clock.
+ */
+/*!
+ * @name Constants and macros for entire I2S_MCR register
+ */
+/*@{*/
+#define I2S_RD_MCR(base)         (I2S_MCR_REG(base))
+#define I2S_WR_MCR(base, value)  (I2S_MCR_REG(base) = (value))
+#define I2S_RMW_MCR(base, mask, value) (I2S_WR_MCR(base, (I2S_RD_MCR(base) & ~(mask)) | (value)))
+#define I2S_SET_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) |  (value)))
+#define I2S_CLR_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) & ~(value)))
+#define I2S_TOG_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MCR bitfields
+ */
+
+/*!
+ * @name Register I2S_MCR, field MICS[25:24] (RW)
+ *
+ * Selects the clock input to the MCLK divider. This field cannot be changed
+ * while the MCLK divider is enabled. See the chip configuration details for
+ * information about the connections to these inputs.
+ *
+ * Values:
+ * - 0b00 - MCLK divider input clock 0 selected.
+ * - 0b01 - MCLK divider input clock 1 selected.
+ * - 0b10 - MCLK divider input clock 2 selected.
+ * - 0b11 - MCLK divider input clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MICS field. */
+#define I2S_RD_MCR_MICS(base) ((I2S_MCR_REG(base) & I2S_MCR_MICS_MASK) >> I2S_MCR_MICS_SHIFT)
+#define I2S_BRD_MCR_MICS(base) (I2S_RD_MCR_MICS(base))
+
+/*! @brief Set the MICS field to a new value. */
+#define I2S_WR_MCR_MICS(base, value) (I2S_RMW_MCR(base, I2S_MCR_MICS_MASK, I2S_MCR_MICS(value)))
+#define I2S_BWR_MCR_MICS(base, value) (I2S_WR_MCR_MICS(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field MOE[30] (RW)
+ *
+ * Enables the MCLK divider and configures the MCLK signal pin as an output.
+ * When software clears this field, it remains set until the MCLK divider is fully
+ * disabled.
+ *
+ * Values:
+ * - 0b0 - MCLK signal pin is configured as an input that bypasses the MCLK
+ *     divider.
+ * - 0b1 - MCLK signal pin is configured as an output from the MCLK divider and
+ *     the MCLK divider is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MOE field. */
+#define I2S_RD_MCR_MOE(base) ((I2S_MCR_REG(base) & I2S_MCR_MOE_MASK) >> I2S_MCR_MOE_SHIFT)
+#define I2S_BRD_MCR_MOE(base) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT))
+
+/*! @brief Set the MOE field to a new value. */
+#define I2S_WR_MCR_MOE(base, value) (I2S_RMW_MCR(base, I2S_MCR_MOE_MASK, I2S_MCR_MOE(value)))
+#define I2S_BWR_MCR_MOE(base, value) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field DUF[31] (RO)
+ *
+ * Provides the status of on-the-fly updates to the MCLK divider ratio.
+ *
+ * Values:
+ * - 0b0 - MCLK divider ratio is not being updated currently.
+ * - 0b1 - MCLK divider ratio is updating on-the-fly. Further updates to the
+ *     MCLK divider ratio are blocked while this flag remains set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_DUF field. */
+#define I2S_RD_MCR_DUF(base) ((I2S_MCR_REG(base) & I2S_MCR_DUF_MASK) >> I2S_MCR_DUF_SHIFT)
+#define I2S_BRD_MCR_DUF(base) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_DUF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MDR - SAI MCLK Divide Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MDR - SAI MCLK Divide Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
+ * MDR can be changed when the MCLK divider clock is enabled, additional writes
+ * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
+ * divided clock is disabled do not set MCR[DUF].
+ */
+/*!
+ * @name Constants and macros for entire I2S_MDR register
+ */
+/*@{*/
+#define I2S_RD_MDR(base)         (I2S_MDR_REG(base))
+#define I2S_WR_MDR(base, value)  (I2S_MDR_REG(base) = (value))
+#define I2S_RMW_MDR(base, mask, value) (I2S_WR_MDR(base, (I2S_RD_MDR(base) & ~(mask)) | (value)))
+#define I2S_SET_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) |  (value)))
+#define I2S_CLR_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) & ~(value)))
+#define I2S_TOG_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MDR bitfields
+ */
+
+/*!
+ * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MDR_DIVIDE field. */
+#define I2S_RD_MDR_DIVIDE(base) ((I2S_MDR_REG(base) & I2S_MDR_DIVIDE_MASK) >> I2S_MDR_DIVIDE_SHIFT)
+#define I2S_BRD_MDR_DIVIDE(base) (I2S_RD_MDR_DIVIDE(base))
+
+/*! @brief Set the DIVIDE field to a new value. */
+#define I2S_WR_MDR_DIVIDE(base, value) (I2S_RMW_MDR(base, I2S_MDR_DIVIDE_MASK, I2S_MDR_DIVIDE(value)))
+#define I2S_BWR_MDR_DIVIDE(base, value) (I2S_WR_MDR_DIVIDE(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MDR, field FRACT[19:12] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MDR_FRACT field. */
+#define I2S_RD_MDR_FRACT(base) ((I2S_MDR_REG(base) & I2S_MDR_FRACT_MASK) >> I2S_MDR_FRACT_SHIFT)
+#define I2S_BRD_MDR_FRACT(base) (I2S_RD_MDR_FRACT(base))
+
+/*! @brief Set the FRACT field to a new value. */
+#define I2S_WR_MDR_FRACT(base, value) (I2S_RMW_MDR(base, I2S_MDR_FRACT_MASK, I2S_MDR_FRACT(value)))
+#define I2S_BWR_MDR_FRACT(base, value) (I2S_WR_MDR_FRACT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 LLWU
+ *
+ * Low leakage wakeup unit
+ *
+ * Registers defined in this header file:
+ * - LLWU_PE1 - LLWU Pin Enable 1 register
+ * - LLWU_PE2 - LLWU Pin Enable 2 register
+ * - LLWU_PE3 - LLWU Pin Enable 3 register
+ * - LLWU_PE4 - LLWU Pin Enable 4 register
+ * - LLWU_ME - LLWU Module Enable register
+ * - LLWU_F1 - LLWU Flag 1 register
+ * - LLWU_F2 - LLWU Flag 2 register
+ * - LLWU_F3 - LLWU Flag 3 register
+ * - LLWU_FILT1 - LLWU Pin Filter 1 register
+ * - LLWU_FILT2 - LLWU Pin Filter 2 register
+ * - LLWU_RST - LLWU Reset Enable register
+ */
+
+#define LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
+#define LLWU_IDX (0U) /*!< Instance number for LLWU. */
+
+/*******************************************************************************
+ * LLWU_PE1 - LLWU Pin Enable 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE1 - LLWU Pin Enable 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE1 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE1 register
+ */
+/*@{*/
+#define LLWU_RD_PE1(base)        (LLWU_PE1_REG(base))
+#define LLWU_WR_PE1(base, value) (LLWU_PE1_REG(base) = (value))
+#define LLWU_RMW_PE1(base, mask, value) (LLWU_WR_PE1(base, (LLWU_RD_PE1(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) |  (value)))
+#define LLWU_CLR_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) & ~(value)))
+#define LLWU_TOG_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
+#define LLWU_RD_PE1_WUPE0(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE0_MASK) >> LLWU_PE1_WUPE0_SHIFT)
+#define LLWU_BRD_PE1_WUPE0(base) (LLWU_RD_PE1_WUPE0(base))
+
+/*! @brief Set the WUPE0 field to a new value. */
+#define LLWU_WR_PE1_WUPE0(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE0_MASK, LLWU_PE1_WUPE0(value)))
+#define LLWU_BWR_PE1_WUPE0(base, value) (LLWU_WR_PE1_WUPE0(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
+#define LLWU_RD_PE1_WUPE1(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE1_MASK) >> LLWU_PE1_WUPE1_SHIFT)
+#define LLWU_BRD_PE1_WUPE1(base) (LLWU_RD_PE1_WUPE1(base))
+
+/*! @brief Set the WUPE1 field to a new value. */
+#define LLWU_WR_PE1_WUPE1(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE1_MASK, LLWU_PE1_WUPE1(value)))
+#define LLWU_BWR_PE1_WUPE1(base, value) (LLWU_WR_PE1_WUPE1(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
+#define LLWU_RD_PE1_WUPE2(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE2_MASK) >> LLWU_PE1_WUPE2_SHIFT)
+#define LLWU_BRD_PE1_WUPE2(base) (LLWU_RD_PE1_WUPE2(base))
+
+/*! @brief Set the WUPE2 field to a new value. */
+#define LLWU_WR_PE1_WUPE2(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE2_MASK, LLWU_PE1_WUPE2(value)))
+#define LLWU_BWR_PE1_WUPE2(base, value) (LLWU_WR_PE1_WUPE2(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
+#define LLWU_RD_PE1_WUPE3(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE3_MASK) >> LLWU_PE1_WUPE3_SHIFT)
+#define LLWU_BRD_PE1_WUPE3(base) (LLWU_RD_PE1_WUPE3(base))
+
+/*! @brief Set the WUPE3 field to a new value. */
+#define LLWU_WR_PE1_WUPE3(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE3_MASK, LLWU_PE1_WUPE3(value)))
+#define LLWU_BWR_PE1_WUPE3(base, value) (LLWU_WR_PE1_WUPE3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE2 - LLWU Pin Enable 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE2 - LLWU Pin Enable 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE2 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE2 register
+ */
+/*@{*/
+#define LLWU_RD_PE2(base)        (LLWU_PE2_REG(base))
+#define LLWU_WR_PE2(base, value) (LLWU_PE2_REG(base) = (value))
+#define LLWU_RMW_PE2(base, mask, value) (LLWU_WR_PE2(base, (LLWU_RD_PE2(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) |  (value)))
+#define LLWU_CLR_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) & ~(value)))
+#define LLWU_TOG_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
+#define LLWU_RD_PE2_WUPE4(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE4_MASK) >> LLWU_PE2_WUPE4_SHIFT)
+#define LLWU_BRD_PE2_WUPE4(base) (LLWU_RD_PE2_WUPE4(base))
+
+/*! @brief Set the WUPE4 field to a new value. */
+#define LLWU_WR_PE2_WUPE4(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE4_MASK, LLWU_PE2_WUPE4(value)))
+#define LLWU_BWR_PE2_WUPE4(base, value) (LLWU_WR_PE2_WUPE4(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
+#define LLWU_RD_PE2_WUPE5(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE5_MASK) >> LLWU_PE2_WUPE5_SHIFT)
+#define LLWU_BRD_PE2_WUPE5(base) (LLWU_RD_PE2_WUPE5(base))
+
+/*! @brief Set the WUPE5 field to a new value. */
+#define LLWU_WR_PE2_WUPE5(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE5_MASK, LLWU_PE2_WUPE5(value)))
+#define LLWU_BWR_PE2_WUPE5(base, value) (LLWU_WR_PE2_WUPE5(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
+#define LLWU_RD_PE2_WUPE6(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE6_MASK) >> LLWU_PE2_WUPE6_SHIFT)
+#define LLWU_BRD_PE2_WUPE6(base) (LLWU_RD_PE2_WUPE6(base))
+
+/*! @brief Set the WUPE6 field to a new value. */
+#define LLWU_WR_PE2_WUPE6(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE6_MASK, LLWU_PE2_WUPE6(value)))
+#define LLWU_BWR_PE2_WUPE6(base, value) (LLWU_WR_PE2_WUPE6(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
+#define LLWU_RD_PE2_WUPE7(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE7_MASK) >> LLWU_PE2_WUPE7_SHIFT)
+#define LLWU_BRD_PE2_WUPE7(base) (LLWU_RD_PE2_WUPE7(base))
+
+/*! @brief Set the WUPE7 field to a new value. */
+#define LLWU_WR_PE2_WUPE7(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE7_MASK, LLWU_PE2_WUPE7(value)))
+#define LLWU_BWR_PE2_WUPE7(base, value) (LLWU_WR_PE2_WUPE7(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE3 - LLWU Pin Enable 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE3 - LLWU Pin Enable 3 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE3 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE3 register
+ */
+/*@{*/
+#define LLWU_RD_PE3(base)        (LLWU_PE3_REG(base))
+#define LLWU_WR_PE3(base, value) (LLWU_PE3_REG(base) = (value))
+#define LLWU_RMW_PE3(base, mask, value) (LLWU_WR_PE3(base, (LLWU_RD_PE3(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) |  (value)))
+#define LLWU_CLR_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) & ~(value)))
+#define LLWU_TOG_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
+#define LLWU_RD_PE3_WUPE8(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE8_MASK) >> LLWU_PE3_WUPE8_SHIFT)
+#define LLWU_BRD_PE3_WUPE8(base) (LLWU_RD_PE3_WUPE8(base))
+
+/*! @brief Set the WUPE8 field to a new value. */
+#define LLWU_WR_PE3_WUPE8(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE8_MASK, LLWU_PE3_WUPE8(value)))
+#define LLWU_BWR_PE3_WUPE8(base, value) (LLWU_WR_PE3_WUPE8(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
+#define LLWU_RD_PE3_WUPE9(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE9_MASK) >> LLWU_PE3_WUPE9_SHIFT)
+#define LLWU_BRD_PE3_WUPE9(base) (LLWU_RD_PE3_WUPE9(base))
+
+/*! @brief Set the WUPE9 field to a new value. */
+#define LLWU_WR_PE3_WUPE9(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE9_MASK, LLWU_PE3_WUPE9(value)))
+#define LLWU_BWR_PE3_WUPE9(base, value) (LLWU_WR_PE3_WUPE9(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
+#define LLWU_RD_PE3_WUPE10(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE10_MASK) >> LLWU_PE3_WUPE10_SHIFT)
+#define LLWU_BRD_PE3_WUPE10(base) (LLWU_RD_PE3_WUPE10(base))
+
+/*! @brief Set the WUPE10 field to a new value. */
+#define LLWU_WR_PE3_WUPE10(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE10_MASK, LLWU_PE3_WUPE10(value)))
+#define LLWU_BWR_PE3_WUPE10(base, value) (LLWU_WR_PE3_WUPE10(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
+#define LLWU_RD_PE3_WUPE11(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE11_MASK) >> LLWU_PE3_WUPE11_SHIFT)
+#define LLWU_BRD_PE3_WUPE11(base) (LLWU_RD_PE3_WUPE11(base))
+
+/*! @brief Set the WUPE11 field to a new value. */
+#define LLWU_WR_PE3_WUPE11(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE11_MASK, LLWU_PE3_WUPE11(value)))
+#define LLWU_BWR_PE3_WUPE11(base, value) (LLWU_WR_PE3_WUPE11(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE4 - LLWU Pin Enable 4 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE4 - LLWU Pin Enable 4 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE4 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE4 register
+ */
+/*@{*/
+#define LLWU_RD_PE4(base)        (LLWU_PE4_REG(base))
+#define LLWU_WR_PE4(base, value) (LLWU_PE4_REG(base) = (value))
+#define LLWU_RMW_PE4(base, mask, value) (LLWU_WR_PE4(base, (LLWU_RD_PE4(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) |  (value)))
+#define LLWU_CLR_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) & ~(value)))
+#define LLWU_TOG_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE4 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
+#define LLWU_RD_PE4_WUPE12(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE12_MASK) >> LLWU_PE4_WUPE12_SHIFT)
+#define LLWU_BRD_PE4_WUPE12(base) (LLWU_RD_PE4_WUPE12(base))
+
+/*! @brief Set the WUPE12 field to a new value. */
+#define LLWU_WR_PE4_WUPE12(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE12_MASK, LLWU_PE4_WUPE12(value)))
+#define LLWU_BWR_PE4_WUPE12(base, value) (LLWU_WR_PE4_WUPE12(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
+#define LLWU_RD_PE4_WUPE13(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE13_MASK) >> LLWU_PE4_WUPE13_SHIFT)
+#define LLWU_BRD_PE4_WUPE13(base) (LLWU_RD_PE4_WUPE13(base))
+
+/*! @brief Set the WUPE13 field to a new value. */
+#define LLWU_WR_PE4_WUPE13(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE13_MASK, LLWU_PE4_WUPE13(value)))
+#define LLWU_BWR_PE4_WUPE13(base, value) (LLWU_WR_PE4_WUPE13(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
+#define LLWU_RD_PE4_WUPE14(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE14_MASK) >> LLWU_PE4_WUPE14_SHIFT)
+#define LLWU_BRD_PE4_WUPE14(base) (LLWU_RD_PE4_WUPE14(base))
+
+/*! @brief Set the WUPE14 field to a new value. */
+#define LLWU_WR_PE4_WUPE14(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE14_MASK, LLWU_PE4_WUPE14(value)))
+#define LLWU_BWR_PE4_WUPE14(base, value) (LLWU_WR_PE4_WUPE14(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
+#define LLWU_RD_PE4_WUPE15(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE15_MASK) >> LLWU_PE4_WUPE15_SHIFT)
+#define LLWU_BRD_PE4_WUPE15(base) (LLWU_RD_PE4_WUPE15(base))
+
+/*! @brief Set the WUPE15 field to a new value. */
+#define LLWU_WR_PE4_WUPE15(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE15_MASK, LLWU_PE4_WUPE15(value)))
+#define LLWU_BWR_PE4_WUPE15(base, value) (LLWU_WR_PE4_WUPE15(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_ME - LLWU Module Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_ME - LLWU Module Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_ME contains the bits to enable the internal module flag as a wakeup
+ * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
+ * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
+ * reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
+ * RCM implements many of the reset functions for the chip. See the chip's reset
+ * chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_ME register
+ */
+/*@{*/
+#define LLWU_RD_ME(base)         (LLWU_ME_REG(base))
+#define LLWU_WR_ME(base, value)  (LLWU_ME_REG(base) = (value))
+#define LLWU_RMW_ME(base, mask, value) (LLWU_WR_ME(base, (LLWU_RD_ME(base) & ~(mask)) | (value)))
+#define LLWU_SET_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) |  (value)))
+#define LLWU_CLR_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) & ~(value)))
+#define LLWU_TOG_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_ME bitfields
+ */
+
+/*!
+ * @name Register LLWU_ME, field WUME0[0] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME0 field. */
+#define LLWU_RD_ME_WUME0(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME0_MASK) >> LLWU_ME_WUME0_SHIFT)
+#define LLWU_BRD_ME_WUME0(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT))
+
+/*! @brief Set the WUME0 field to a new value. */
+#define LLWU_WR_ME_WUME0(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME0_MASK, LLWU_ME_WUME0(value)))
+#define LLWU_BWR_ME_WUME0(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME1[1] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME1 field. */
+#define LLWU_RD_ME_WUME1(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME1_MASK) >> LLWU_ME_WUME1_SHIFT)
+#define LLWU_BRD_ME_WUME1(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT))
+
+/*! @brief Set the WUME1 field to a new value. */
+#define LLWU_WR_ME_WUME1(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME1_MASK, LLWU_ME_WUME1(value)))
+#define LLWU_BWR_ME_WUME1(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME2[2] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME2 field. */
+#define LLWU_RD_ME_WUME2(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME2_MASK) >> LLWU_ME_WUME2_SHIFT)
+#define LLWU_BRD_ME_WUME2(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT))
+
+/*! @brief Set the WUME2 field to a new value. */
+#define LLWU_WR_ME_WUME2(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME2_MASK, LLWU_ME_WUME2(value)))
+#define LLWU_BWR_ME_WUME2(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME3[3] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME3 field. */
+#define LLWU_RD_ME_WUME3(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME3_MASK) >> LLWU_ME_WUME3_SHIFT)
+#define LLWU_BRD_ME_WUME3(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT))
+
+/*! @brief Set the WUME3 field to a new value. */
+#define LLWU_WR_ME_WUME3(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME3_MASK, LLWU_ME_WUME3(value)))
+#define LLWU_BWR_ME_WUME3(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME4[4] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME4 field. */
+#define LLWU_RD_ME_WUME4(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME4_MASK) >> LLWU_ME_WUME4_SHIFT)
+#define LLWU_BRD_ME_WUME4(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT))
+
+/*! @brief Set the WUME4 field to a new value. */
+#define LLWU_WR_ME_WUME4(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME4_MASK, LLWU_ME_WUME4(value)))
+#define LLWU_BWR_ME_WUME4(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME5[5] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME5 field. */
+#define LLWU_RD_ME_WUME5(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME5_MASK) >> LLWU_ME_WUME5_SHIFT)
+#define LLWU_BRD_ME_WUME5(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT))
+
+/*! @brief Set the WUME5 field to a new value. */
+#define LLWU_WR_ME_WUME5(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME5_MASK, LLWU_ME_WUME5(value)))
+#define LLWU_BWR_ME_WUME5(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME6[6] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME6 field. */
+#define LLWU_RD_ME_WUME6(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME6_MASK) >> LLWU_ME_WUME6_SHIFT)
+#define LLWU_BRD_ME_WUME6(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT))
+
+/*! @brief Set the WUME6 field to a new value. */
+#define LLWU_WR_ME_WUME6(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME6_MASK, LLWU_ME_WUME6(value)))
+#define LLWU_BWR_ME_WUME6(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME7[7] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME7 field. */
+#define LLWU_RD_ME_WUME7(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME7_MASK) >> LLWU_ME_WUME7_SHIFT)
+#define LLWU_BRD_ME_WUME7(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT))
+
+/*! @brief Set the WUME7 field to a new value. */
+#define LLWU_WR_ME_WUME7(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME7_MASK, LLWU_ME_WUME7(value)))
+#define LLWU_BWR_ME_WUME7(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F1 - LLWU Flag 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F1 - LLWU Flag 1 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F1 register
+ */
+/*@{*/
+#define LLWU_RD_F1(base)         (LLWU_F1_REG(base))
+#define LLWU_WR_F1(base, value)  (LLWU_F1_REG(base) = (value))
+#define LLWU_RMW_F1(base, mask, value) (LLWU_WR_F1(base, (LLWU_RD_F1(base) & ~(mask)) | (value)))
+#define LLWU_SET_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) |  (value)))
+#define LLWU_CLR_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) & ~(value)))
+#define LLWU_TOG_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F1, field WUF0[0] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF0.
+ *
+ * Values:
+ * - 0b0 - LLWU_P0 input was not a wakeup source
+ * - 0b1 - LLWU_P0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF0 field. */
+#define LLWU_RD_F1_WUF0(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF0_MASK) >> LLWU_F1_WUF0_SHIFT)
+#define LLWU_BRD_F1_WUF0(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT))
+
+/*! @brief Set the WUF0 field to a new value. */
+#define LLWU_WR_F1_WUF0(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF0(value)))
+#define LLWU_BWR_F1_WUF0(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF1[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF1.
+ *
+ * Values:
+ * - 0b0 - LLWU_P1 input was not a wakeup source
+ * - 0b1 - LLWU_P1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF1 field. */
+#define LLWU_RD_F1_WUF1(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF1_MASK) >> LLWU_F1_WUF1_SHIFT)
+#define LLWU_BRD_F1_WUF1(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT))
+
+/*! @brief Set the WUF1 field to a new value. */
+#define LLWU_WR_F1_WUF1(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF1_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF1(value)))
+#define LLWU_BWR_F1_WUF1(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF2[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF2.
+ *
+ * Values:
+ * - 0b0 - LLWU_P2 input was not a wakeup source
+ * - 0b1 - LLWU_P2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF2 field. */
+#define LLWU_RD_F1_WUF2(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF2_MASK) >> LLWU_F1_WUF2_SHIFT)
+#define LLWU_BRD_F1_WUF2(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT))
+
+/*! @brief Set the WUF2 field to a new value. */
+#define LLWU_WR_F1_WUF2(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF2_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF2(value)))
+#define LLWU_BWR_F1_WUF2(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF3[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF3.
+ *
+ * Values:
+ * - 0b0 - LLWU_P3 input was not a wake-up source
+ * - 0b1 - LLWU_P3 input was a wake-up source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF3 field. */
+#define LLWU_RD_F1_WUF3(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF3_MASK) >> LLWU_F1_WUF3_SHIFT)
+#define LLWU_BRD_F1_WUF3(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT))
+
+/*! @brief Set the WUF3 field to a new value. */
+#define LLWU_WR_F1_WUF3(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF3_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF3(value)))
+#define LLWU_BWR_F1_WUF3(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF4[4] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF4.
+ *
+ * Values:
+ * - 0b0 - LLWU_P4 input was not a wakeup source
+ * - 0b1 - LLWU_P4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF4 field. */
+#define LLWU_RD_F1_WUF4(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF4_MASK) >> LLWU_F1_WUF4_SHIFT)
+#define LLWU_BRD_F1_WUF4(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT))
+
+/*! @brief Set the WUF4 field to a new value. */
+#define LLWU_WR_F1_WUF4(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF4_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF4(value)))
+#define LLWU_BWR_F1_WUF4(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF5[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF5.
+ *
+ * Values:
+ * - 0b0 - LLWU_P5 input was not a wakeup source
+ * - 0b1 - LLWU_P5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF5 field. */
+#define LLWU_RD_F1_WUF5(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF5_MASK) >> LLWU_F1_WUF5_SHIFT)
+#define LLWU_BRD_F1_WUF5(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT))
+
+/*! @brief Set the WUF5 field to a new value. */
+#define LLWU_WR_F1_WUF5(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF5_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF5(value)))
+#define LLWU_BWR_F1_WUF5(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF6[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF6.
+ *
+ * Values:
+ * - 0b0 - LLWU_P6 input was not a wakeup source
+ * - 0b1 - LLWU_P6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF6 field. */
+#define LLWU_RD_F1_WUF6(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF6_MASK) >> LLWU_F1_WUF6_SHIFT)
+#define LLWU_BRD_F1_WUF6(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT))
+
+/*! @brief Set the WUF6 field to a new value. */
+#define LLWU_WR_F1_WUF6(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF6_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF6(value)))
+#define LLWU_BWR_F1_WUF6(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF7[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF7.
+ *
+ * Values:
+ * - 0b0 - LLWU_P7 input was not a wakeup source
+ * - 0b1 - LLWU_P7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF7 field. */
+#define LLWU_RD_F1_WUF7(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF7_MASK) >> LLWU_F1_WUF7_SHIFT)
+#define LLWU_BRD_F1_WUF7(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT))
+
+/*! @brief Set the WUF7 field to a new value. */
+#define LLWU_WR_F1_WUF7(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF7_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK), LLWU_F1_WUF7(value)))
+#define LLWU_BWR_F1_WUF7(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F2 - LLWU Flag 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F2 - LLWU Flag 2 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F2 register
+ */
+/*@{*/
+#define LLWU_RD_F2(base)         (LLWU_F2_REG(base))
+#define LLWU_WR_F2(base, value)  (LLWU_F2_REG(base) = (value))
+#define LLWU_RMW_F2(base, mask, value) (LLWU_WR_F2(base, (LLWU_RD_F2(base) & ~(mask)) | (value)))
+#define LLWU_SET_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) |  (value)))
+#define LLWU_CLR_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) & ~(value)))
+#define LLWU_TOG_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F2, field WUF8[0] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF8.
+ *
+ * Values:
+ * - 0b0 - LLWU_P8 input was not a wakeup source
+ * - 0b1 - LLWU_P8 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF8 field. */
+#define LLWU_RD_F2_WUF8(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF8_MASK) >> LLWU_F2_WUF8_SHIFT)
+#define LLWU_BRD_F2_WUF8(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT))
+
+/*! @brief Set the WUF8 field to a new value. */
+#define LLWU_WR_F2_WUF8(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF8(value)))
+#define LLWU_BWR_F2_WUF8(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF9[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF9.
+ *
+ * Values:
+ * - 0b0 - LLWU_P9 input was not a wakeup source
+ * - 0b1 - LLWU_P9 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF9 field. */
+#define LLWU_RD_F2_WUF9(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF9_MASK) >> LLWU_F2_WUF9_SHIFT)
+#define LLWU_BRD_F2_WUF9(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT))
+
+/*! @brief Set the WUF9 field to a new value. */
+#define LLWU_WR_F2_WUF9(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF9_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF9(value)))
+#define LLWU_BWR_F2_WUF9(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF10[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF10.
+ *
+ * Values:
+ * - 0b0 - LLWU_P10 input was not a wakeup source
+ * - 0b1 - LLWU_P10 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF10 field. */
+#define LLWU_RD_F2_WUF10(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF10_MASK) >> LLWU_F2_WUF10_SHIFT)
+#define LLWU_BRD_F2_WUF10(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT))
+
+/*! @brief Set the WUF10 field to a new value. */
+#define LLWU_WR_F2_WUF10(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF10_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF10(value)))
+#define LLWU_BWR_F2_WUF10(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF11[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF11.
+ *
+ * Values:
+ * - 0b0 - LLWU_P11 input was not a wakeup source
+ * - 0b1 - LLWU_P11 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF11 field. */
+#define LLWU_RD_F2_WUF11(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF11_MASK) >> LLWU_F2_WUF11_SHIFT)
+#define LLWU_BRD_F2_WUF11(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT))
+
+/*! @brief Set the WUF11 field to a new value. */
+#define LLWU_WR_F2_WUF11(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF11_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF11(value)))
+#define LLWU_BWR_F2_WUF11(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF12[4] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF12.
+ *
+ * Values:
+ * - 0b0 - LLWU_P12 input was not a wakeup source
+ * - 0b1 - LLWU_P12 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF12 field. */
+#define LLWU_RD_F2_WUF12(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF12_MASK) >> LLWU_F2_WUF12_SHIFT)
+#define LLWU_BRD_F2_WUF12(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT))
+
+/*! @brief Set the WUF12 field to a new value. */
+#define LLWU_WR_F2_WUF12(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF12_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF12(value)))
+#define LLWU_BWR_F2_WUF12(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF13[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF13.
+ *
+ * Values:
+ * - 0b0 - LLWU_P13 input was not a wakeup source
+ * - 0b1 - LLWU_P13 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF13 field. */
+#define LLWU_RD_F2_WUF13(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF13_MASK) >> LLWU_F2_WUF13_SHIFT)
+#define LLWU_BRD_F2_WUF13(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT))
+
+/*! @brief Set the WUF13 field to a new value. */
+#define LLWU_WR_F2_WUF13(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF13_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF13(value)))
+#define LLWU_BWR_F2_WUF13(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF14[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF14.
+ *
+ * Values:
+ * - 0b0 - LLWU_P14 input was not a wakeup source
+ * - 0b1 - LLWU_P14 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF14 field. */
+#define LLWU_RD_F2_WUF14(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF14_MASK) >> LLWU_F2_WUF14_SHIFT)
+#define LLWU_BRD_F2_WUF14(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT))
+
+/*! @brief Set the WUF14 field to a new value. */
+#define LLWU_WR_F2_WUF14(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF14_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF14(value)))
+#define LLWU_BWR_F2_WUF14(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF15[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF15.
+ *
+ * Values:
+ * - 0b0 - LLWU_P15 input was not a wakeup source
+ * - 0b1 - LLWU_P15 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF15 field. */
+#define LLWU_RD_F2_WUF15(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF15_MASK) >> LLWU_F2_WUF15_SHIFT)
+#define LLWU_BRD_F2_WUF15(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT))
+
+/*! @brief Set the WUF15 field to a new value. */
+#define LLWU_WR_F2_WUF15(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF15_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK), LLWU_F2_WUF15(value)))
+#define LLWU_BWR_F2_WUF15(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F3 - LLWU Flag 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F3 - LLWU Flag 3 register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
+ * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
+ * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
+ * For internal peripherals that are capable of running in a low-leakage power
+ * mode, such as a real time clock module or CMP module, the flag from the
+ * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
+ * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
+ * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
+ * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
+ * the IntroductionInformation found here describes the registers of the Reset
+ * Control Module (RCM). The RCM implements many of the reset functions for the
+ * chip. See the chip's reset chapter for more information. details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F3 register
+ */
+/*@{*/
+#define LLWU_RD_F3(base)         (LLWU_F3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F3, field MWUF0[0] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 0 input was not a wakeup source
+ * - 0b1 - Module 0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF0 field. */
+#define LLWU_RD_F3_MWUF0(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF0_MASK) >> LLWU_F3_MWUF0_SHIFT)
+#define LLWU_BRD_F3_MWUF0(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF1[1] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 1 input was not a wakeup source
+ * - 0b1 - Module 1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF1 field. */
+#define LLWU_RD_F3_MWUF1(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF1_MASK) >> LLWU_F3_MWUF1_SHIFT)
+#define LLWU_BRD_F3_MWUF1(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF2[2] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 2 input was not a wakeup source
+ * - 0b1 - Module 2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF2 field. */
+#define LLWU_RD_F3_MWUF2(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF2_MASK) >> LLWU_F3_MWUF2_SHIFT)
+#define LLWU_BRD_F3_MWUF2(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF2_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF3[3] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 3 input was not a wakeup source
+ * - 0b1 - Module 3 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF3 field. */
+#define LLWU_RD_F3_MWUF3(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF3_MASK) >> LLWU_F3_MWUF3_SHIFT)
+#define LLWU_BRD_F3_MWUF3(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF3_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF4[4] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 4 input was not a wakeup source
+ * - 0b1 - Module 4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF4 field. */
+#define LLWU_RD_F3_MWUF4(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF4_MASK) >> LLWU_F3_MWUF4_SHIFT)
+#define LLWU_BRD_F3_MWUF4(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF4_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF5[5] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 5 input was not a wakeup source
+ * - 0b1 - Module 5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF5 field. */
+#define LLWU_RD_F3_MWUF5(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF5_MASK) >> LLWU_F3_MWUF5_SHIFT)
+#define LLWU_BRD_F3_MWUF5(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF5_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF6[6] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 6 input was not a wakeup source
+ * - 0b1 - Module 6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF6 field. */
+#define LLWU_RD_F3_MWUF6(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF6_MASK) >> LLWU_F3_MWUF6_SHIFT)
+#define LLWU_BRD_F3_MWUF6(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF6_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF7[7] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 7 input was not a wakeup source
+ * - 0b1 - Module 7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF7 field. */
+#define LLWU_RD_F3_MWUF7(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF7_MASK) >> LLWU_F3_MWUF7_SHIFT)
+#define LLWU_BRD_F3_MWUF7(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF7_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT1 - LLWU Pin Filter 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT1 is a control and status register that is used to enable/disable
+ * the digital filter 1 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT1 register
+ */
+/*@{*/
+#define LLWU_RD_FILT1(base)      (LLWU_FILT1_REG(base))
+#define LLWU_WR_FILT1(base, value) (LLWU_FILT1_REG(base) = (value))
+#define LLWU_RMW_FILT1(base, mask, value) (LLWU_WR_FILT1(base, (LLWU_RD_FILT1(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) |  (value)))
+#define LLWU_CLR_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) & ~(value)))
+#define LLWU_TOG_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0b0000 - Select LLWU_P0 for filter
+ * - 0b1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
+#define LLWU_RD_FILT1_FILTSEL(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTSEL_MASK) >> LLWU_FILT1_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT1_FILTSEL(base) (LLWU_RD_FILT1_FILTSEL(base))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT1_FILTSEL(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTSEL(value)))
+#define LLWU_BWR_FILT1_FILTSEL(base, value) (LLWU_WR_FILT1_FILTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 0b00 - Filter disabled
+ * - 0b01 - Filter posedge detect enabled
+ * - 0b10 - Filter negedge detect enabled
+ * - 0b11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTE field. */
+#define LLWU_RD_FILT1_FILTE(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTE_MASK) >> LLWU_FILT1_FILTE_SHIFT)
+#define LLWU_BRD_FILT1_FILTE(base) (LLWU_RD_FILT1_FILTE(base))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT1_FILTE(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTE_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTE(value)))
+#define LLWU_BWR_FILT1_FILTE(base, value) (LLWU_WR_FILT1_FILTE(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0b0 - Pin Filter 1 was not a wakeup source
+ * - 0b1 - Pin Filter 1 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTF field. */
+#define LLWU_RD_FILT1_FILTF(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTF_MASK) >> LLWU_FILT1_FILTF_SHIFT)
+#define LLWU_BRD_FILT1_FILTF(base) (BITBAND_ACCESS8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT1_FILTF(base, value) (LLWU_RMW_FILT1(base, LLWU_FILT1_FILTF_MASK, LLWU_FILT1_FILTF(value)))
+#define LLWU_BWR_FILT1_FILTF(base, value) (BITBAND_ACCESS8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT2 - LLWU Pin Filter 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT2 is a control and status register that is used to enable/disable
+ * the digital filter 2 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT2 register
+ */
+/*@{*/
+#define LLWU_RD_FILT2(base)      (LLWU_FILT2_REG(base))
+#define LLWU_WR_FILT2(base, value) (LLWU_FILT2_REG(base) = (value))
+#define LLWU_RMW_FILT2(base, mask, value) (LLWU_WR_FILT2(base, (LLWU_RD_FILT2(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) |  (value)))
+#define LLWU_CLR_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) & ~(value)))
+#define LLWU_TOG_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0b0000 - Select LLWU_P0 for filter
+ * - 0b1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
+#define LLWU_RD_FILT2_FILTSEL(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTSEL_MASK) >> LLWU_FILT2_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT2_FILTSEL(base) (LLWU_RD_FILT2_FILTSEL(base))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT2_FILTSEL(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTSEL_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTSEL(value)))
+#define LLWU_BWR_FILT2_FILTSEL(base, value) (LLWU_WR_FILT2_FILTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 0b00 - Filter disabled
+ * - 0b01 - Filter posedge detect enabled
+ * - 0b10 - Filter negedge detect enabled
+ * - 0b11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTE field. */
+#define LLWU_RD_FILT2_FILTE(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTE_MASK) >> LLWU_FILT2_FILTE_SHIFT)
+#define LLWU_BRD_FILT2_FILTE(base) (LLWU_RD_FILT2_FILTE(base))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT2_FILTE(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTE_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTE(value)))
+#define LLWU_BWR_FILT2_FILTE(base, value) (LLWU_WR_FILT2_FILTE(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0b0 - Pin Filter 2 was not a wakeup source
+ * - 0b1 - Pin Filter 2 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTF field. */
+#define LLWU_RD_FILT2_FILTF(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTF_MASK) >> LLWU_FILT2_FILTF_SHIFT)
+#define LLWU_BRD_FILT2_FILTF(base) (BITBAND_ACCESS8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT2_FILTF(base, value) (LLWU_RMW_FILT2(base, LLWU_FILT2_FILTF_MASK, LLWU_FILT2_FILTF(value)))
+#define LLWU_BWR_FILT2_FILTF(base, value) (BITBAND_ACCESS8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_RST - LLWU Reset Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_RST - LLWU Reset Enable register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * LLWU_RST is a control register that is used to enable/disable the digital
+ * filter for the external pin detect and RESET pin. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_RST register
+ */
+/*@{*/
+#define LLWU_RD_RST(base)        (LLWU_RST_REG(base))
+#define LLWU_WR_RST(base, value) (LLWU_RST_REG(base) = (value))
+#define LLWU_RMW_RST(base, mask, value) (LLWU_WR_RST(base, (LLWU_RD_RST(base) & ~(mask)) | (value)))
+#define LLWU_SET_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) |  (value)))
+#define LLWU_CLR_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) & ~(value)))
+#define LLWU_TOG_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_RST bitfields
+ */
+
+/*!
+ * @name Register LLWU_RST, field RSTFILT[0] (RW)
+ *
+ * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
+ * VLLS1 modes.
+ *
+ * Values:
+ * - 0b0 - Filter not enabled
+ * - 0b1 - Filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_RST_RSTFILT field. */
+#define LLWU_RD_RST_RSTFILT(base) ((LLWU_RST_REG(base) & LLWU_RST_RSTFILT_MASK) >> LLWU_RST_RSTFILT_SHIFT)
+#define LLWU_BRD_RST_RSTFILT(base) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_RSTFILT_SHIFT))
+
+/*! @brief Set the RSTFILT field to a new value. */
+#define LLWU_WR_RST_RSTFILT(base, value) (LLWU_RMW_RST(base, LLWU_RST_RSTFILT_MASK, LLWU_RST_RSTFILT(value)))
+#define LLWU_BWR_RST_RSTFILT(base, value) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_RSTFILT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_RST, field LLRSTE[1] (RW)
+ *
+ * This bit must be set to allow the device to be reset while in a low-leakage
+ * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
+ * also be enabled in the explicit port mux control.
+ *
+ * Values:
+ * - 0b0 - RESET pin not enabled as a leakage mode exit source
+ * - 0b1 - RESET pin enabled as a low leakage mode exit source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_RST_LLRSTE field. */
+#define LLWU_RD_RST_LLRSTE(base) ((LLWU_RST_REG(base) & LLWU_RST_LLRSTE_MASK) >> LLWU_RST_LLRSTE_SHIFT)
+#define LLWU_BRD_RST_LLRSTE(base) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_LLRSTE_SHIFT))
+
+/*! @brief Set the LLRSTE field to a new value. */
+#define LLWU_WR_RST_LLRSTE(base, value) (LLWU_RMW_RST(base, LLWU_RST_LLRSTE_MASK, LLWU_RST_LLRSTE(value)))
+#define LLWU_BWR_RST_LLRSTE(base, value) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_LLRSTE_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 LPTMR
+ *
+ * Low Power Timer
+ *
+ * Registers defined in this header file:
+ * - LPTMR_CSR - Low Power Timer Control Status Register
+ * - LPTMR_PSR - Low Power Timer Prescale Register
+ * - LPTMR_CMR - Low Power Timer Compare Register
+ * - LPTMR_CNR - Low Power Timer Counter Register
+ */
+
+#define LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
+#define LPTMR0_IDX (0U) /*!< Instance number for LPTMR0. */
+
+/*******************************************************************************
+ * LPTMR_CSR - Low Power Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CSR - Low Power Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CSR register
+ */
+/*@{*/
+#define LPTMR_RD_CSR(base)       (LPTMR_CSR_REG(base))
+#define LPTMR_WR_CSR(base, value) (LPTMR_CSR_REG(base) = (value))
+#define LPTMR_RMW_CSR(base, mask, value) (LPTMR_WR_CSR(base, (LPTMR_RD_CSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) |  (value)))
+#define LPTMR_CLR_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) & ~(value)))
+#define LPTMR_TOG_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CSR, field TEN[0] (RW)
+ *
+ * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
+ * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
+ * CSR[5:1] must not be altered.
+ *
+ * Values:
+ * - 0b0 - LPTMR is disabled and internal logic is reset.
+ * - 0b1 - LPTMR is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TEN field. */
+#define LPTMR_RD_CSR_TEN(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TEN_MASK) >> LPTMR_CSR_TEN_SHIFT)
+#define LPTMR_BRD_CSR_TEN(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT))
+
+/*! @brief Set the TEN field to a new value. */
+#define LPTMR_WR_CSR_TEN(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TEN_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TEN(value)))
+#define LPTMR_BWR_CSR_TEN(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TMS[1] (RW)
+ *
+ * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
+ * disabled.
+ *
+ * Values:
+ * - 0b0 - Time Counter mode.
+ * - 0b1 - Pulse Counter mode.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TMS field. */
+#define LPTMR_RD_CSR_TMS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TMS_MASK) >> LPTMR_CSR_TMS_SHIFT)
+#define LPTMR_BRD_CSR_TMS(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT))
+
+/*! @brief Set the TMS field to a new value. */
+#define LPTMR_WR_CSR_TMS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TMS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TMS(value)))
+#define LPTMR_BWR_CSR_TMS(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TFC[2] (RW)
+ *
+ * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
+ * TFC configures the CNR to reset on overflow. TFC must be altered only when the
+ * LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - CNR is reset whenever TCF is set.
+ * - 0b1 - CNR is reset on overflow.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TFC field. */
+#define LPTMR_RD_CSR_TFC(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TFC_MASK) >> LPTMR_CSR_TFC_SHIFT)
+#define LPTMR_BRD_CSR_TFC(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT))
+
+/*! @brief Set the TFC field to a new value. */
+#define LPTMR_WR_CSR_TFC(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TFC_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TFC(value)))
+#define LPTMR_BWR_CSR_TFC(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPP[3] (RW)
+ *
+ * Configures the polarity of the input source in Pulse Counter mode. TPP must
+ * be changed only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - Pulse Counter input source is active-high, and the CNR will increment
+ *     on the rising-edge.
+ * - 0b1 - Pulse Counter input source is active-low, and the CNR will increment
+ *     on the falling-edge.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPP field. */
+#define LPTMR_RD_CSR_TPP(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPP_MASK) >> LPTMR_CSR_TPP_SHIFT)
+#define LPTMR_BRD_CSR_TPP(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT))
+
+/*! @brief Set the TPP field to a new value. */
+#define LPTMR_WR_CSR_TPP(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPP_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPP(value)))
+#define LPTMR_BWR_CSR_TPP(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPS[5:4] (RW)
+ *
+ * Configures the input source to be used in Pulse Counter mode. TPS must be
+ * altered only when the LPTMR is disabled. The input connections vary by device.
+ * See the chip configuration details for information on the connections to these
+ * inputs.
+ *
+ * Values:
+ * - 0b00 - Pulse counter input 0 is selected.
+ * - 0b01 - Pulse counter input 1 is selected.
+ * - 0b10 - Pulse counter input 2 is selected.
+ * - 0b11 - Pulse counter input 3 is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPS field. */
+#define LPTMR_RD_CSR_TPS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPS_MASK) >> LPTMR_CSR_TPS_SHIFT)
+#define LPTMR_BRD_CSR_TPS(base) (LPTMR_RD_CSR_TPS(base))
+
+/*! @brief Set the TPS field to a new value. */
+#define LPTMR_WR_CSR_TPS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPS(value)))
+#define LPTMR_BWR_CSR_TPS(base, value) (LPTMR_WR_CSR_TPS(base, value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TIE[6] (RW)
+ *
+ * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
+ *
+ * Values:
+ * - 0b0 - Timer interrupt disabled.
+ * - 0b1 - Timer interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TIE field. */
+#define LPTMR_RD_CSR_TIE(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TIE_MASK) >> LPTMR_CSR_TIE_SHIFT)
+#define LPTMR_BRD_CSR_TIE(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define LPTMR_WR_CSR_TIE(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TIE_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TIE(value)))
+#define LPTMR_BWR_CSR_TIE(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TCF[7] (W1C)
+ *
+ * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
+ * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
+ *
+ * Values:
+ * - 0b0 - The value of CNR is not equal to CMR and increments.
+ * - 0b1 - The value of CNR is equal to CMR and increments.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TCF field. */
+#define LPTMR_RD_CSR_TCF(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TCF_MASK) >> LPTMR_CSR_TCF_SHIFT)
+#define LPTMR_BRD_CSR_TCF(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT))
+
+/*! @brief Set the TCF field to a new value. */
+#define LPTMR_WR_CSR_TCF(base, value) (LPTMR_RMW_CSR(base, LPTMR_CSR_TCF_MASK, LPTMR_CSR_TCF(value)))
+#define LPTMR_BWR_CSR_TCF(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_PSR - Low Power Timer Prescale Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_PSR - Low Power Timer Prescale Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_PSR register
+ */
+/*@{*/
+#define LPTMR_RD_PSR(base)       (LPTMR_PSR_REG(base))
+#define LPTMR_WR_PSR(base, value) (LPTMR_PSR_REG(base) = (value))
+#define LPTMR_RMW_PSR(base, mask, value) (LPTMR_WR_PSR(base, (LPTMR_RD_PSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) |  (value)))
+#define LPTMR_CLR_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) & ~(value)))
+#define LPTMR_TOG_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_PSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_PSR, field PCS[1:0] (RW)
+ *
+ * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
+ * be altered only when the LPTMR is disabled. The clock connections vary by
+ * device. See the chip configuration details for information on the connections to
+ * these inputs.
+ *
+ * Values:
+ * - 0b00 - Prescaler/glitch filter clock 0 selected.
+ * - 0b01 - Prescaler/glitch filter clock 1 selected.
+ * - 0b10 - Prescaler/glitch filter clock 2 selected.
+ * - 0b11 - Prescaler/glitch filter clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PCS field. */
+#define LPTMR_RD_PSR_PCS(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PCS_MASK) >> LPTMR_PSR_PCS_SHIFT)
+#define LPTMR_BRD_PSR_PCS(base) (LPTMR_RD_PSR_PCS(base))
+
+/*! @brief Set the PCS field to a new value. */
+#define LPTMR_WR_PSR_PCS(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PCS_MASK, LPTMR_PSR_PCS(value)))
+#define LPTMR_BWR_PSR_PCS(base, value) (LPTMR_WR_PSR_PCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PBYP[2] (RW)
+ *
+ * When PBYP is set, the selected prescaler clock in Time Counter mode or
+ * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
+ * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
+ * must be altered only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - Prescaler/glitch filter is enabled.
+ * - 0b1 - Prescaler/glitch filter is bypassed.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PBYP field. */
+#define LPTMR_RD_PSR_PBYP(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PBYP_MASK) >> LPTMR_PSR_PBYP_SHIFT)
+#define LPTMR_BRD_PSR_PBYP(base) (BITBAND_ACCESS32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT))
+
+/*! @brief Set the PBYP field to a new value. */
+#define LPTMR_WR_PSR_PBYP(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PBYP_MASK, LPTMR_PSR_PBYP(value)))
+#define LPTMR_BWR_PSR_PBYP(base, value) (BITBAND_ACCESS32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
+ *
+ * Configures the size of the Prescaler in Time Counter mode or width of the
+ * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
+ * is disabled.
+ *
+ * Values:
+ * - 0b0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
+ *     support this configuration.
+ * - 0b0001 - Prescaler divides the prescaler clock by 4; glitch filter
+ *     recognizes change on input pin after 2 rising clock edges.
+ * - 0b0010 - Prescaler divides the prescaler clock by 8; glitch filter
+ *     recognizes change on input pin after 4 rising clock edges.
+ * - 0b0011 - Prescaler divides the prescaler clock by 16; glitch filter
+ *     recognizes change on input pin after 8 rising clock edges.
+ * - 0b0100 - Prescaler divides the prescaler clock by 32; glitch filter
+ *     recognizes change on input pin after 16 rising clock edges.
+ * - 0b0101 - Prescaler divides the prescaler clock by 64; glitch filter
+ *     recognizes change on input pin after 32 rising clock edges.
+ * - 0b0110 - Prescaler divides the prescaler clock by 128; glitch filter
+ *     recognizes change on input pin after 64 rising clock edges.
+ * - 0b0111 - Prescaler divides the prescaler clock by 256; glitch filter
+ *     recognizes change on input pin after 128 rising clock edges.
+ * - 0b1000 - Prescaler divides the prescaler clock by 512; glitch filter
+ *     recognizes change on input pin after 256 rising clock edges.
+ * - 0b1001 - Prescaler divides the prescaler clock by 1024; glitch filter
+ *     recognizes change on input pin after 512 rising clock edges.
+ * - 0b1010 - Prescaler divides the prescaler clock by 2048; glitch filter
+ *     recognizes change on input pin after 1024 rising clock edges.
+ * - 0b1011 - Prescaler divides the prescaler clock by 4096; glitch filter
+ *     recognizes change on input pin after 2048 rising clock edges.
+ * - 0b1100 - Prescaler divides the prescaler clock by 8192; glitch filter
+ *     recognizes change on input pin after 4096 rising clock edges.
+ * - 0b1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
+ *     recognizes change on input pin after 8192 rising clock edges.
+ * - 0b1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
+ *     recognizes change on input pin after 16,384 rising clock edges.
+ * - 0b1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
+ *     recognizes change on input pin after 32,768 rising clock edges.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
+#define LPTMR_RD_PSR_PRESCALE(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PRESCALE_MASK) >> LPTMR_PSR_PRESCALE_SHIFT)
+#define LPTMR_BRD_PSR_PRESCALE(base) (LPTMR_RD_PSR_PRESCALE(base))
+
+/*! @brief Set the PRESCALE field to a new value. */
+#define LPTMR_WR_PSR_PRESCALE(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PRESCALE_MASK, LPTMR_PSR_PRESCALE(value)))
+#define LPTMR_BWR_PSR_PRESCALE(base, value) (LPTMR_WR_PSR_PRESCALE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CMR - Low Power Timer Compare Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CMR - Low Power Timer Compare Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CMR register
+ */
+/*@{*/
+#define LPTMR_RD_CMR(base)       (LPTMR_CMR_REG(base))
+#define LPTMR_WR_CMR(base, value) (LPTMR_CMR_REG(base) = (value))
+#define LPTMR_RMW_CMR(base, mask, value) (LPTMR_WR_CMR(base, (LPTMR_RD_CMR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) |  (value)))
+#define LPTMR_CLR_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) & ~(value)))
+#define LPTMR_TOG_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CMR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
+ *
+ * When the LPTMR is enabled and the CNR equals the value in the CMR and
+ * increments, TCF is set and the hardware trigger asserts until the next time the CNR
+ * increments. If the CMR is 0, the hardware trigger will remain asserted until
+ * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
+ * when TCF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
+#define LPTMR_RD_CMR_COMPARE(base) ((LPTMR_CMR_REG(base) & LPTMR_CMR_COMPARE_MASK) >> LPTMR_CMR_COMPARE_SHIFT)
+#define LPTMR_BRD_CMR_COMPARE(base) (LPTMR_RD_CMR_COMPARE(base))
+
+/*! @brief Set the COMPARE field to a new value. */
+#define LPTMR_WR_CMR_COMPARE(base, value) (LPTMR_RMW_CMR(base, LPTMR_CMR_COMPARE_MASK, LPTMR_CMR_COMPARE(value)))
+#define LPTMR_BWR_CMR_COMPARE(base, value) (LPTMR_WR_CMR_COMPARE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CNR - Low Power Timer Counter Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CNR - Low Power Timer Counter Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CNR register
+ */
+/*@{*/
+#define LPTMR_RD_CNR(base)       (LPTMR_CNR_REG(base))
+#define LPTMR_WR_CNR(base, value) (LPTMR_CNR_REG(base) = (value))
+#define LPTMR_RMW_CNR(base, mask, value) (LPTMR_WR_CNR(base, (LPTMR_RD_CNR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) |  (value)))
+#define LPTMR_CLR_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) & ~(value)))
+#define LPTMR_TOG_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CNR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
+#define LPTMR_RD_CNR_COUNTER(base) ((LPTMR_CNR_REG(base) & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT)
+#define LPTMR_BRD_CNR_COUNTER(base) (LPTMR_RD_CNR_COUNTER(base))
+
+/*! @brief Set the COUNTER field to a new value. */
+#define LPTMR_WR_CNR_COUNTER(base, value) (LPTMR_RMW_CNR(base, LPTMR_CNR_COUNTER_MASK, LPTMR_CNR_COUNTER(value)))
+#define LPTMR_BWR_CNR_COUNTER(base, value) (LPTMR_WR_CNR_COUNTER(base, value))
+/*@}*/
+
+/*
+ * MK64F12 MCG
+ *
+ * Multipurpose Clock Generator module
+ *
+ * Registers defined in this header file:
+ * - MCG_C1 - MCG Control 1 Register
+ * - MCG_C2 - MCG Control 2 Register
+ * - MCG_C3 - MCG Control 3 Register
+ * - MCG_C4 - MCG Control 4 Register
+ * - MCG_C5 - MCG Control 5 Register
+ * - MCG_C6 - MCG Control 6 Register
+ * - MCG_S - MCG Status Register
+ * - MCG_SC - MCG Status and Control Register
+ * - MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ * - MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ * - MCG_C7 - MCG Control 7 Register
+ * - MCG_C8 - MCG Control 8 Register
+ */
+
+#define MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */
+#define MCG_IDX (0U) /*!< Instance number for MCG. */
+
+/*******************************************************************************
+ * MCG_C1 - MCG Control 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C1 - MCG Control 1 Register (RW)
+ *
+ * Reset value: 0x04U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C1 register
+ */
+/*@{*/
+#define MCG_RD_C1(base)          (MCG_C1_REG(base))
+#define MCG_WR_C1(base, value)   (MCG_C1_REG(base) = (value))
+#define MCG_RMW_C1(base, mask, value) (MCG_WR_C1(base, (MCG_RD_C1(base) & ~(mask)) | (value)))
+#define MCG_SET_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) |  (value)))
+#define MCG_CLR_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) & ~(value)))
+#define MCG_TOG_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C1 bitfields
+ */
+
+/*!
+ * @name Register MCG_C1, field IREFSTEN[0] (RW)
+ *
+ * Controls whether or not the internal reference clock remains enabled when the
+ * MCG enters Stop mode.
+ *
+ * Values:
+ * - 0b0 - Internal reference clock is disabled in Stop mode.
+ * - 0b1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
+ *     if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFSTEN field. */
+#define MCG_RD_C1_IREFSTEN(base) ((MCG_C1_REG(base) & MCG_C1_IREFSTEN_MASK) >> MCG_C1_IREFSTEN_SHIFT)
+#define MCG_BRD_C1_IREFSTEN(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT))
+
+/*! @brief Set the IREFSTEN field to a new value. */
+#define MCG_WR_C1_IREFSTEN(base, value) (MCG_RMW_C1(base, MCG_C1_IREFSTEN_MASK, MCG_C1_IREFSTEN(value)))
+#define MCG_BWR_C1_IREFSTEN(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IRCLKEN[1] (RW)
+ *
+ * Enables the internal reference clock for use as MCGIRCLK.
+ *
+ * Values:
+ * - 0b0 - MCGIRCLK inactive.
+ * - 0b1 - MCGIRCLK active.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IRCLKEN field. */
+#define MCG_RD_C1_IRCLKEN(base) ((MCG_C1_REG(base) & MCG_C1_IRCLKEN_MASK) >> MCG_C1_IRCLKEN_SHIFT)
+#define MCG_BRD_C1_IRCLKEN(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT))
+
+/*! @brief Set the IRCLKEN field to a new value. */
+#define MCG_WR_C1_IRCLKEN(base, value) (MCG_RMW_C1(base, MCG_C1_IRCLKEN_MASK, MCG_C1_IRCLKEN(value)))
+#define MCG_BWR_C1_IRCLKEN(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IREFS[2] (RW)
+ *
+ * Selects the reference clock source for the FLL.
+ *
+ * Values:
+ * - 0b0 - External reference clock is selected.
+ * - 0b1 - The slow internal reference clock is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFS field. */
+#define MCG_RD_C1_IREFS(base) ((MCG_C1_REG(base) & MCG_C1_IREFS_MASK) >> MCG_C1_IREFS_SHIFT)
+#define MCG_BRD_C1_IREFS(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT))
+
+/*! @brief Set the IREFS field to a new value. */
+#define MCG_WR_C1_IREFS(base, value) (MCG_RMW_C1(base, MCG_C1_IREFS_MASK, MCG_C1_IREFS(value)))
+#define MCG_BWR_C1_IREFS(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field FRDIV[5:3] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the FLL.
+ * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
+ * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
+ * not required to meet this range, but it is recommended in the cases when trying
+ * to enter a FLL mode from FBE).
+ *
+ * Values:
+ * - 0b000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
+ *     values, Divide Factor is 32.
+ * - 0b001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
+ *     values, Divide Factor is 64.
+ * - 0b010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
+ *     values, Divide Factor is 128.
+ * - 0b011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
+ *     values, Divide Factor is 256.
+ * - 0b100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
+ *     values, Divide Factor is 512.
+ * - 0b101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
+ *     values, Divide Factor is 1024.
+ * - 0b110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
+ *     values, Divide Factor is 1280 .
+ * - 0b111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other
+ *     RANGE values, Divide Factor is 1536 .
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_FRDIV field. */
+#define MCG_RD_C1_FRDIV(base) ((MCG_C1_REG(base) & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
+#define MCG_BRD_C1_FRDIV(base) (MCG_RD_C1_FRDIV(base))
+
+/*! @brief Set the FRDIV field to a new value. */
+#define MCG_WR_C1_FRDIV(base, value) (MCG_RMW_C1(base, MCG_C1_FRDIV_MASK, MCG_C1_FRDIV(value)))
+#define MCG_BWR_C1_FRDIV(base, value) (MCG_WR_C1_FRDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field CLKS[7:6] (RW)
+ *
+ * Selects the clock source for MCGOUTCLK .
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS
+ *     control bit).
+ * - 0b01 - Encoding 1 - Internal reference clock is selected.
+ * - 0b10 - Encoding 2 - External reference clock is selected.
+ * - 0b11 - Encoding 3 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_CLKS field. */
+#define MCG_RD_C1_CLKS(base) ((MCG_C1_REG(base) & MCG_C1_CLKS_MASK) >> MCG_C1_CLKS_SHIFT)
+#define MCG_BRD_C1_CLKS(base) (MCG_RD_C1_CLKS(base))
+
+/*! @brief Set the CLKS field to a new value. */
+#define MCG_WR_C1_CLKS(base, value) (MCG_RMW_C1(base, MCG_C1_CLKS_MASK, MCG_C1_CLKS(value)))
+#define MCG_BWR_C1_CLKS(base, value) (MCG_WR_C1_CLKS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C2 - MCG Control 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C2 - MCG Control 2 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C2 register
+ */
+/*@{*/
+#define MCG_RD_C2(base)          (MCG_C2_REG(base))
+#define MCG_WR_C2(base, value)   (MCG_C2_REG(base) = (value))
+#define MCG_RMW_C2(base, mask, value) (MCG_WR_C2(base, (MCG_RD_C2(base) & ~(mask)) | (value)))
+#define MCG_SET_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) |  (value)))
+#define MCG_CLR_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) & ~(value)))
+#define MCG_TOG_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C2 bitfields
+ */
+
+/*!
+ * @name Register MCG_C2, field IRCS[0] (RW)
+ *
+ * Selects between the fast or slow internal reference clock source.
+ *
+ * Values:
+ * - 0b0 - Slow internal reference clock selected.
+ * - 0b1 - Fast internal reference clock selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_IRCS field. */
+#define MCG_RD_C2_IRCS(base) ((MCG_C2_REG(base) & MCG_C2_IRCS_MASK) >> MCG_C2_IRCS_SHIFT)
+#define MCG_BRD_C2_IRCS(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT))
+
+/*! @brief Set the IRCS field to a new value. */
+#define MCG_WR_C2_IRCS(base, value) (MCG_RMW_C2(base, MCG_C2_IRCS_MASK, MCG_C2_IRCS(value)))
+#define MCG_BWR_C2_IRCS(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field LP[1] (RW)
+ *
+ * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
+ * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
+ * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
+ * other MCG mode, LP bit has no affect.
+ *
+ * Values:
+ * - 0b0 - FLL or PLL is not disabled in bypass modes.
+ * - 0b1 - FLL or PLL is disabled in bypass modes (lower power)
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_LP field. */
+#define MCG_RD_C2_LP(base)   ((MCG_C2_REG(base) & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
+#define MCG_BRD_C2_LP(base)  (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT))
+
+/*! @brief Set the LP field to a new value. */
+#define MCG_WR_C2_LP(base, value) (MCG_RMW_C2(base, MCG_C2_LP_MASK, MCG_C2_LP(value)))
+#define MCG_BWR_C2_LP(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field EREFS[2] (RW)
+ *
+ * Selects the source for the external reference clock. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0b0 - External reference clock requested.
+ * - 0b1 - Oscillator requested.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_EREFS field. */
+#define MCG_RD_C2_EREFS(base) ((MCG_C2_REG(base) & MCG_C2_EREFS_MASK) >> MCG_C2_EREFS_SHIFT)
+#define MCG_BRD_C2_EREFS(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT))
+
+/*! @brief Set the EREFS field to a new value. */
+#define MCG_WR_C2_EREFS(base, value) (MCG_RMW_C2(base, MCG_C2_EREFS_MASK, MCG_C2_EREFS(value)))
+#define MCG_BWR_C2_EREFS(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field HGO[3] (RW)
+ *
+ * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0b0 - Configure crystal oscillator for low-power operation.
+ * - 0b1 - Configure crystal oscillator for high-gain operation.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_HGO field. */
+#define MCG_RD_C2_HGO(base)  ((MCG_C2_REG(base) & MCG_C2_HGO_MASK) >> MCG_C2_HGO_SHIFT)
+#define MCG_BRD_C2_HGO(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT))
+
+/*! @brief Set the HGO field to a new value. */
+#define MCG_WR_C2_HGO(base, value) (MCG_RMW_C2(base, MCG_C2_HGO_MASK, MCG_C2_HGO(value)))
+#define MCG_BWR_C2_HGO(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field RANGE[5:4] (RW)
+ *
+ * Selects the frequency range for the crystal oscillator or external clock
+ * source. See the Oscillator (OSC) chapter for more details and the device data
+ * sheet for the frequency ranges used.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Low frequency range selected for the crystal oscillator
+ *     .
+ * - 0b01 - Encoding 1 - High frequency range selected for the crystal
+ *     oscillator .
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_RANGE field. */
+#define MCG_RD_C2_RANGE(base) ((MCG_C2_REG(base) & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
+#define MCG_BRD_C2_RANGE(base) (MCG_RD_C2_RANGE(base))
+
+/*! @brief Set the RANGE field to a new value. */
+#define MCG_WR_C2_RANGE(base, value) (MCG_RMW_C2(base, MCG_C2_RANGE_MASK, MCG_C2_RANGE(value)))
+#define MCG_BWR_C2_RANGE(base, value) (MCG_WR_C2_RANGE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field FCFTRIM[6] (RW)
+ *
+ * FCFTRIM controls the smallest adjustment of the fast internal reference clock
+ * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
+ * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_FCFTRIM field. */
+#define MCG_RD_C2_FCFTRIM(base) ((MCG_C2_REG(base) & MCG_C2_FCFTRIM_MASK) >> MCG_C2_FCFTRIM_SHIFT)
+#define MCG_BRD_C2_FCFTRIM(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT))
+
+/*! @brief Set the FCFTRIM field to a new value. */
+#define MCG_WR_C2_FCFTRIM(base, value) (MCG_RMW_C2(base, MCG_C2_FCFTRIM_MASK, MCG_C2_FCFTRIM(value)))
+#define MCG_BWR_C2_FCFTRIM(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field LOCRE0[7] (RW)
+ *
+ * Determines whether an interrupt or a reset request is made following a loss
+ * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
+ * set.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a loss of OSC0 external reference
+ *     clock.
+ * - 0b1 - Generate a reset request on a loss of OSC0 external reference clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_LOCRE0 field. */
+#define MCG_RD_C2_LOCRE0(base) ((MCG_C2_REG(base) & MCG_C2_LOCRE0_MASK) >> MCG_C2_LOCRE0_SHIFT)
+#define MCG_BRD_C2_LOCRE0(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT))
+
+/*! @brief Set the LOCRE0 field to a new value. */
+#define MCG_WR_C2_LOCRE0(base, value) (MCG_RMW_C2(base, MCG_C2_LOCRE0_MASK, MCG_C2_LOCRE0(value)))
+#define MCG_BWR_C2_LOCRE0(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C3 - MCG Control 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C3 - MCG Control 3 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C3 register
+ */
+/*@{*/
+#define MCG_RD_C3(base)          (MCG_C3_REG(base))
+#define MCG_WR_C3(base, value)   (MCG_C3_REG(base) = (value))
+#define MCG_RMW_C3(base, mask, value) (MCG_WR_C3(base, (MCG_RD_C3(base) & ~(mask)) | (value)))
+#define MCG_SET_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) |  (value)))
+#define MCG_CLR_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) & ~(value)))
+#define MCG_TOG_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C4 - MCG Control 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C4 - MCG Control 4 Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Reset values for DRST and DMX32 bits are 0.
+ */
+/*!
+ * @name Constants and macros for entire MCG_C4 register
+ */
+/*@{*/
+#define MCG_RD_C4(base)          (MCG_C4_REG(base))
+#define MCG_WR_C4(base, value)   (MCG_C4_REG(base) = (value))
+#define MCG_RMW_C4(base, mask, value) (MCG_WR_C4(base, (MCG_RD_C4(base) & ~(mask)) | (value)))
+#define MCG_SET_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) |  (value)))
+#define MCG_CLR_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) & ~(value)))
+#define MCG_TOG_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C4 bitfields
+ */
+
+/*!
+ * @name Register MCG_C4, field SCFTRIM[0] (RW)
+ *
+ * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
+ * location . controls the smallest adjustment of the slow internal reference
+ * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
+ * decreases the period by the smallest amount possible. If an SCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_SCFTRIM field. */
+#define MCG_RD_C4_SCFTRIM(base) ((MCG_C4_REG(base) & MCG_C4_SCFTRIM_MASK) >> MCG_C4_SCFTRIM_SHIFT)
+#define MCG_BRD_C4_SCFTRIM(base) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT))
+
+/*! @brief Set the SCFTRIM field to a new value. */
+#define MCG_WR_C4_SCFTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_SCFTRIM_MASK, MCG_C4_SCFTRIM(value)))
+#define MCG_BWR_C4_SCFTRIM(base, value) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field FCTRIM[4:1] (RW)
+ *
+ * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
+ * location. controls the fast internal reference clock frequency by controlling
+ * the fast internal reference clock period. The FCTRIM bits are binary weighted,
+ * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
+ * increases the period, and decreasing the value decreases the period. If an
+ * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
+ * responsibility to copy that value from the nonvolatile memory location to this register.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_FCTRIM field. */
+#define MCG_RD_C4_FCTRIM(base) ((MCG_C4_REG(base) & MCG_C4_FCTRIM_MASK) >> MCG_C4_FCTRIM_SHIFT)
+#define MCG_BRD_C4_FCTRIM(base) (MCG_RD_C4_FCTRIM(base))
+
+/*! @brief Set the FCTRIM field to a new value. */
+#define MCG_WR_C4_FCTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_FCTRIM_MASK, MCG_C4_FCTRIM(value)))
+#define MCG_BWR_C4_FCTRIM(base, value) (MCG_WR_C4_FCTRIM(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
+ *
+ * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
+ * LP bit is set, writes to the DRS bits are ignored. The DRST read field
+ * indicates the current frequency range for DCOOUT. The DRST field does not update
+ * immediately after a write to the DRS field due to internal synchronization between
+ * clock domains. See the DCO Frequency Range table for more details.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Low range (reset default).
+ * - 0b01 - Encoding 1 - Mid range.
+ * - 0b10 - Encoding 2 - Mid-high range.
+ * - 0b11 - Encoding 3 - High range.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_DRST_DRS field. */
+#define MCG_RD_C4_DRST_DRS(base) ((MCG_C4_REG(base) & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
+#define MCG_BRD_C4_DRST_DRS(base) (MCG_RD_C4_DRST_DRS(base))
+
+/*! @brief Set the DRST_DRS field to a new value. */
+#define MCG_WR_C4_DRST_DRS(base, value) (MCG_RMW_C4(base, MCG_C4_DRST_DRS_MASK, MCG_C4_DRST_DRS(value)))
+#define MCG_BWR_C4_DRST_DRS(base, value) (MCG_WR_C4_DRST_DRS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field DMX32[7] (RW)
+ *
+ * The DMX32 bit controls whether the DCO frequency range is narrowed to its
+ * maximum frequency with a 32.768 kHz reference. The following table identifies
+ * settings for the DCO frequency range. The system clocks derived from this source
+ * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
+ * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
+ * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
+ * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
+ * 80-100 MHz 1 32.768 kHz 2929 96 MHz
+ *
+ * Values:
+ * - 0b0 - DCO has a default range of 25%.
+ * - 0b1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_DMX32 field. */
+#define MCG_RD_C4_DMX32(base) ((MCG_C4_REG(base) & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
+#define MCG_BRD_C4_DMX32(base) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT))
+
+/*! @brief Set the DMX32 field to a new value. */
+#define MCG_WR_C4_DMX32(base, value) (MCG_RMW_C4(base, MCG_C4_DMX32_MASK, MCG_C4_DMX32(value)))
+#define MCG_BWR_C4_DMX32(base, value) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C5 - MCG Control 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C5 - MCG Control 5 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C5 register
+ */
+/*@{*/
+#define MCG_RD_C5(base)          (MCG_C5_REG(base))
+#define MCG_WR_C5(base, value)   (MCG_C5_REG(base) = (value))
+#define MCG_RMW_C5(base, mask, value) (MCG_WR_C5(base, (MCG_RD_C5(base) & ~(mask)) | (value)))
+#define MCG_SET_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) |  (value)))
+#define MCG_CLR_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) & ~(value)))
+#define MCG_TOG_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C5 bitfields
+ */
+
+/*!
+ * @name Register MCG_C5, field PRDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the PLL.
+ * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
+ * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
+ * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
+ * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
+ * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
+ * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
+ * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
+ * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
+ * Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PRDIV0 field. */
+#define MCG_RD_C5_PRDIV0(base) ((MCG_C5_REG(base) & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
+#define MCG_BRD_C5_PRDIV0(base) (MCG_RD_C5_PRDIV0(base))
+
+/*! @brief Set the PRDIV0 field to a new value. */
+#define MCG_WR_C5_PRDIV0(base, value) (MCG_RMW_C5(base, MCG_C5_PRDIV0_MASK, MCG_C5_PRDIV0(value)))
+#define MCG_BWR_C5_PRDIV0(base, value) (MCG_WR_C5_PRDIV0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C5, field PLLSTEN0[5] (RW)
+ *
+ * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
+ * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
+ * has no affect and does not enable the PLL Clock to run if it is written to 1.
+ *
+ * Values:
+ * - 0b0 - MCGPLLCLK is disabled in any of the Stop modes.
+ * - 0b1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */
+#define MCG_RD_C5_PLLSTEN0(base) ((MCG_C5_REG(base) & MCG_C5_PLLSTEN0_MASK) >> MCG_C5_PLLSTEN0_SHIFT)
+#define MCG_BRD_C5_PLLSTEN0(base) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLSTEN0_SHIFT))
+
+/*! @brief Set the PLLSTEN0 field to a new value. */
+#define MCG_WR_C5_PLLSTEN0(base, value) (MCG_RMW_C5(base, MCG_C5_PLLSTEN0_MASK, MCG_C5_PLLSTEN0(value)))
+#define MCG_BWR_C5_PLLSTEN0(base, value) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLSTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C5, field PLLCLKEN0[6] (RW)
+ *
+ * Enables the PLL independent of PLLS and enables the PLL clock for use as
+ * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
+ * PLL reference clock in the range of 2 - 4 MHz range prior to setting the
+ * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
+ * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
+ * and the external oscillator is being used as the reference clock, the OSCINIT 0
+ * bit should be checked to make sure it is set.
+ *
+ * Values:
+ * - 0b0 - MCGPLLCLK is inactive.
+ * - 0b1 - MCGPLLCLK is active.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */
+#define MCG_RD_C5_PLLCLKEN0(base) ((MCG_C5_REG(base) & MCG_C5_PLLCLKEN0_MASK) >> MCG_C5_PLLCLKEN0_SHIFT)
+#define MCG_BRD_C5_PLLCLKEN0(base) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLCLKEN0_SHIFT))
+
+/*! @brief Set the PLLCLKEN0 field to a new value. */
+#define MCG_WR_C5_PLLCLKEN0(base, value) (MCG_RMW_C5(base, MCG_C5_PLLCLKEN0_MASK, MCG_C5_PLLCLKEN0(value)))
+#define MCG_BWR_C5_PLLCLKEN0(base, value) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLCLKEN0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C6 - MCG Control 6 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C6 - MCG Control 6 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C6 register
+ */
+/*@{*/
+#define MCG_RD_C6(base)          (MCG_C6_REG(base))
+#define MCG_WR_C6(base, value)   (MCG_C6_REG(base) = (value))
+#define MCG_RMW_C6(base, mask, value) (MCG_WR_C6(base, (MCG_RD_C6(base) & ~(mask)) | (value)))
+#define MCG_SET_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) |  (value)))
+#define MCG_CLR_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) & ~(value)))
+#define MCG_TOG_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C6 bitfields
+ */
+
+/*!
+ * @name Register MCG_C6, field VDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
+ * establish the multiplication factor (M) applied to the reference clock frequency.
+ * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
+ * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
+ * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
+ * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
+ * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
+ * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
+ * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_VDIV0 field. */
+#define MCG_RD_C6_VDIV0(base) ((MCG_C6_REG(base) & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
+#define MCG_BRD_C6_VDIV0(base) (MCG_RD_C6_VDIV0(base))
+
+/*! @brief Set the VDIV0 field to a new value. */
+#define MCG_WR_C6_VDIV0(base, value) (MCG_RMW_C6(base, MCG_C6_VDIV0_MASK, MCG_C6_VDIV0(value)))
+#define MCG_BWR_C6_VDIV0(base, value) (MCG_WR_C6_VDIV0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field CME0[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the OSC0 external reference
+ * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
+ * generated following a loss of OSC0 indication. The CME0 bit must only be set
+ * to a logic 1 when the MCG is in an operational mode that uses the external
+ * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
+ * the value of the RANGE0 bits in the C2 register should not be changed. CME0
+ * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur while in Stop mode. CME0 should also be set to a
+ * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
+ *
+ * Values:
+ * - 0b0 - External clock monitor is disabled for OSC0.
+ * - 0b1 - External clock monitor is enabled for OSC0.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_CME0 field. */
+#define MCG_RD_C6_CME0(base) ((MCG_C6_REG(base) & MCG_C6_CME0_MASK) >> MCG_C6_CME0_SHIFT)
+#define MCG_BRD_C6_CME0(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_CME0_SHIFT))
+
+/*! @brief Set the CME0 field to a new value. */
+#define MCG_WR_C6_CME0(base, value) (MCG_RMW_C6(base, MCG_C6_CME0_MASK, MCG_C6_CME0(value)))
+#define MCG_BWR_C6_CME0(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_CME0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field PLLS[6] (RW)
+ *
+ * Controls whether the PLL or FLL output is selected as the MCG source when
+ * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
+ * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
+ *
+ * Values:
+ * - 0b0 - FLL is selected.
+ * - 0b1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
+ *     to generate a PLL reference clock in the range of 2-4 MHz prior to
+ *     setting the PLLS bit).
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_PLLS field. */
+#define MCG_RD_C6_PLLS(base) ((MCG_C6_REG(base) & MCG_C6_PLLS_MASK) >> MCG_C6_PLLS_SHIFT)
+#define MCG_BRD_C6_PLLS(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_PLLS_SHIFT))
+
+/*! @brief Set the PLLS field to a new value. */
+#define MCG_WR_C6_PLLS(base, value) (MCG_RMW_C6(base, MCG_C6_PLLS_MASK, MCG_C6_PLLS(value)))
+#define MCG_BWR_C6_PLLS(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_PLLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field LOLIE0[7] (RW)
+ *
+ * Determines if an interrupt request is made following a loss of lock
+ * indication. This bit only has an effect when LOLS 0 is set.
+ *
+ * Values:
+ * - 0b0 - No interrupt request is generated on loss of lock.
+ * - 0b1 - Generate an interrupt request on loss of lock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_LOLIE0 field. */
+#define MCG_RD_C6_LOLIE0(base) ((MCG_C6_REG(base) & MCG_C6_LOLIE0_MASK) >> MCG_C6_LOLIE0_SHIFT)
+#define MCG_BRD_C6_LOLIE0(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_LOLIE0_SHIFT))
+
+/*! @brief Set the LOLIE0 field to a new value. */
+#define MCG_WR_C6_LOLIE0(base, value) (MCG_RMW_C6(base, MCG_C6_LOLIE0_MASK, MCG_C6_LOLIE0(value)))
+#define MCG_BWR_C6_LOLIE0(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_LOLIE0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_S - MCG Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_S - MCG Status Register (RW)
+ *
+ * Reset value: 0x10U
+ */
+/*!
+ * @name Constants and macros for entire MCG_S register
+ */
+/*@{*/
+#define MCG_RD_S(base)           (MCG_S_REG(base))
+#define MCG_WR_S(base, value)    (MCG_S_REG(base) = (value))
+#define MCG_RMW_S(base, mask, value) (MCG_WR_S(base, (MCG_RD_S(base) & ~(mask)) | (value)))
+#define MCG_SET_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) |  (value)))
+#define MCG_CLR_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) & ~(value)))
+#define MCG_TOG_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_S bitfields
+ */
+
+/*!
+ * @name Register MCG_S, field IRCST[0] (RO)
+ *
+ * The IRCST bit indicates the current source for the internal reference clock
+ * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
+ * to the IRCS bit due to internal synchronization between clock domains. The
+ * IRCST bit will only be updated if the internal reference clock is enabled,
+ * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
+ * bit .
+ *
+ * Values:
+ * - 0b0 - Source of internal reference clock is the slow clock (32 kHz IRC).
+ * - 0b1 - Source of internal reference clock is the fast clock (4 MHz IRC).
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_IRCST field. */
+#define MCG_RD_S_IRCST(base) ((MCG_S_REG(base) & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT)
+#define MCG_BRD_S_IRCST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_IRCST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field OSCINIT0[1] (RO)
+ *
+ * This bit, which resets to 0, is set to 1 after the initialization cycles of
+ * the crystal oscillator clock have completed. After being set, the bit is
+ * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
+ * description for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_OSCINIT0 field. */
+#define MCG_RD_S_OSCINIT0(base) ((MCG_S_REG(base) & MCG_S_OSCINIT0_MASK) >> MCG_S_OSCINIT0_SHIFT)
+#define MCG_BRD_S_OSCINIT0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_OSCINIT0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field CLKST[3:2] (RO)
+ *
+ * These bits indicate the current clock mode. The CLKST bits do not update
+ * immediately after a write to the CLKS bits due to internal synchronization between
+ * clock domains.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Output of the FLL is selected (reset default).
+ * - 0b01 - Encoding 1 - Internal reference clock is selected.
+ * - 0b10 - Encoding 2 - External reference clock is selected.
+ * - 0b11 - Encoding 3 - Output of the PLL is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_CLKST field. */
+#define MCG_RD_S_CLKST(base) ((MCG_S_REG(base) & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
+#define MCG_BRD_S_CLKST(base) (MCG_RD_S_CLKST(base))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field IREFST[4] (RO)
+ *
+ * This bit indicates the current source for the FLL reference clock. The IREFST
+ * bit does not update immediately after a write to the IREFS bit due to
+ * internal synchronization between clock domains.
+ *
+ * Values:
+ * - 0b0 - Source of FLL reference clock is the external reference clock.
+ * - 0b1 - Source of FLL reference clock is the internal reference clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_IREFST field. */
+#define MCG_RD_S_IREFST(base) ((MCG_S_REG(base) & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
+#define MCG_BRD_S_IREFST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_IREFST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field PLLST[5] (RO)
+ *
+ * This bit indicates the clock source selected by PLLS . The PLLST bit does not
+ * update immediately after a write to the PLLS bit due to internal
+ * synchronization between clock domains.
+ *
+ * Values:
+ * - 0b0 - Source of PLLS clock is FLL clock.
+ * - 0b1 - Source of PLLS clock is PLL output clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_PLLST field. */
+#define MCG_RD_S_PLLST(base) ((MCG_S_REG(base) & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT)
+#define MCG_BRD_S_PLLST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_PLLST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field LOCK0[6] (RO)
+ *
+ * This bit indicates whether the PLL has acquired lock. Lock detection is only
+ * enabled when the PLL is enabled (either through clock mode selection or
+ * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
+ * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
+ * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
+ * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
+ * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
+ * reference clock will also cause the LOCK0 bit to clear until the PLL has
+ * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
+ * the lock status bit to clear and stay cleared until the Stop mode is exited
+ * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
+ * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
+ * again.
+ *
+ * Values:
+ * - 0b0 - PLL is currently unlocked.
+ * - 0b1 - PLL is currently locked.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_LOCK0 field. */
+#define MCG_RD_S_LOCK0(base) ((MCG_S_REG(base) & MCG_S_LOCK0_MASK) >> MCG_S_LOCK0_SHIFT)
+#define MCG_BRD_S_LOCK0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOCK0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field LOLS0[7] (W1C)
+ *
+ * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
+ * if after acquiring lock, the PLL output frequency has fallen outside the lock
+ * exit frequency tolerance, D unl . LOLIE determines whether an interrupt
+ * request is made when LOLS is set. LOLRE determines whether a reset request is made
+ * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
+ * when set. Writing a logic 0 to this bit has no effect.
+ *
+ * Values:
+ * - 0b0 - PLL has not lost lock since LOLS 0 was last cleared.
+ * - 0b1 - PLL has lost lock since LOLS 0 was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_LOLS0 field. */
+#define MCG_RD_S_LOLS0(base) ((MCG_S_REG(base) & MCG_S_LOLS0_MASK) >> MCG_S_LOLS0_SHIFT)
+#define MCG_BRD_S_LOLS0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOLS0_SHIFT))
+
+/*! @brief Set the LOLS0 field to a new value. */
+#define MCG_WR_S_LOLS0(base, value) (MCG_RMW_S(base, MCG_S_LOLS0_MASK, MCG_S_LOLS0(value)))
+#define MCG_BWR_S_LOLS0(base, value) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOLS0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_SC - MCG Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_SC - MCG Status and Control Register (RW)
+ *
+ * Reset value: 0x02U
+ */
+/*!
+ * @name Constants and macros for entire MCG_SC register
+ */
+/*@{*/
+#define MCG_RD_SC(base)          (MCG_SC_REG(base))
+#define MCG_WR_SC(base, value)   (MCG_SC_REG(base) = (value))
+#define MCG_RMW_SC(base, mask, value) (MCG_WR_SC(base, (MCG_RD_SC(base) & ~(mask)) | (value)))
+#define MCG_SET_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) |  (value)))
+#define MCG_CLR_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) & ~(value)))
+#define MCG_TOG_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_SC bitfields
+ */
+
+/*!
+ * @name Register MCG_SC, field LOCS0[0] (W1C)
+ *
+ * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
+ * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
+ * logic 1 to it when set.
+ *
+ * Values:
+ * - 0b0 - Loss of OSC0 has not occurred.
+ * - 0b1 - Loss of OSC0 has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_LOCS0 field. */
+#define MCG_RD_SC_LOCS0(base) ((MCG_SC_REG(base) & MCG_SC_LOCS0_MASK) >> MCG_SC_LOCS0_SHIFT)
+#define MCG_BRD_SC_LOCS0(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT))
+
+/*! @brief Set the LOCS0 field to a new value. */
+#define MCG_WR_SC_LOCS0(base, value) (MCG_RMW_SC(base, MCG_SC_LOCS0_MASK, MCG_SC_LOCS0(value)))
+#define MCG_BWR_SC_LOCS0(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field FCRDIV[3:1] (RW)
+ *
+ * Selects the amount to divide down the fast internal reference clock. The
+ * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
+ * divider when the Fast IRC is enabled is not supported).
+ *
+ * Values:
+ * - 0b000 - Divide Factor is 1
+ * - 0b001 - Divide Factor is 2.
+ * - 0b010 - Divide Factor is 4.
+ * - 0b011 - Divide Factor is 8.
+ * - 0b100 - Divide Factor is 16
+ * - 0b101 - Divide Factor is 32
+ * - 0b110 - Divide Factor is 64
+ * - 0b111 - Divide Factor is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FCRDIV field. */
+#define MCG_RD_SC_FCRDIV(base) ((MCG_SC_REG(base) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
+#define MCG_BRD_SC_FCRDIV(base) (MCG_RD_SC_FCRDIV(base))
+
+/*! @brief Set the FCRDIV field to a new value. */
+#define MCG_WR_SC_FCRDIV(base, value) (MCG_RMW_SC(base, (MCG_SC_FCRDIV_MASK | MCG_SC_LOCS0_MASK), MCG_SC_FCRDIV(value)))
+#define MCG_BWR_SC_FCRDIV(base, value) (MCG_WR_SC_FCRDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field FLTPRSRV[4] (RW)
+ *
+ * This bit will prevent the FLL filter values from resetting allowing the FLL
+ * output frequency to remain the same during clock mode changes where the FLL/DCO
+ * output is still valid. (Note: This requires that the FLL reference frequency
+ * to remain the same as what it was prior to the new clock mode switch.
+ * Otherwise FLL filter and frequency values will change.)
+ *
+ * Values:
+ * - 0b0 - FLL filter and FLL frequency will reset on changes to currect clock
+ *     mode.
+ * - 0b1 - Fll filter and FLL frequency retain their previous values during new
+ *     clock mode change.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FLTPRSRV field. */
+#define MCG_RD_SC_FLTPRSRV(base) ((MCG_SC_REG(base) & MCG_SC_FLTPRSRV_MASK) >> MCG_SC_FLTPRSRV_SHIFT)
+#define MCG_BRD_SC_FLTPRSRV(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT))
+
+/*! @brief Set the FLTPRSRV field to a new value. */
+#define MCG_WR_SC_FLTPRSRV(base, value) (MCG_RMW_SC(base, (MCG_SC_FLTPRSRV_MASK | MCG_SC_LOCS0_MASK), MCG_SC_FLTPRSRV(value)))
+#define MCG_BWR_SC_FLTPRSRV(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATMF[5] (RW)
+ *
+ * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
+ * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
+ * registers is detected or the MCG enters into any Stop mode. A write to ATMF
+ * clears the flag.
+ *
+ * Values:
+ * - 0b0 - Automatic Trim Machine completed normally.
+ * - 0b1 - Automatic Trim Machine failed.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATMF field. */
+#define MCG_RD_SC_ATMF(base) ((MCG_SC_REG(base) & MCG_SC_ATMF_MASK) >> MCG_SC_ATMF_SHIFT)
+#define MCG_BRD_SC_ATMF(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT))
+
+/*! @brief Set the ATMF field to a new value. */
+#define MCG_WR_SC_ATMF(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMF(value)))
+#define MCG_BWR_SC_ATMF(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATMS[6] (RW)
+ *
+ * Selects the IRCS clock for Auto Trim Test.
+ *
+ * Values:
+ * - 0b0 - 32 kHz Internal Reference Clock selected.
+ * - 0b1 - 4 MHz Internal Reference Clock selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATMS field. */
+#define MCG_RD_SC_ATMS(base) ((MCG_SC_REG(base) & MCG_SC_ATMS_MASK) >> MCG_SC_ATMS_SHIFT)
+#define MCG_BRD_SC_ATMS(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT))
+
+/*! @brief Set the ATMS field to a new value. */
+#define MCG_WR_SC_ATMS(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMS(value)))
+#define MCG_BWR_SC_ATMS(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATME[7] (RW)
+ *
+ * Enables the Auto Trim Machine to start automatically trimming the selected
+ * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
+ * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
+ * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
+ * operation and clears this bit.
+ *
+ * Values:
+ * - 0b0 - Auto Trim Machine disabled.
+ * - 0b1 - Auto Trim Machine enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATME field. */
+#define MCG_RD_SC_ATME(base) ((MCG_SC_REG(base) & MCG_SC_ATME_MASK) >> MCG_SC_ATME_SHIFT)
+#define MCG_BRD_SC_ATME(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT))
+
+/*! @brief Set the ATME field to a new value. */
+#define MCG_WR_SC_ATME(base, value) (MCG_RMW_SC(base, (MCG_SC_ATME_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATME(value)))
+#define MCG_BWR_SC_ATME(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_ATCVH register
+ */
+/*@{*/
+#define MCG_RD_ATCVH(base)       (MCG_ATCVH_REG(base))
+#define MCG_WR_ATCVH(base, value) (MCG_ATCVH_REG(base) = (value))
+#define MCG_RMW_ATCVH(base, mask, value) (MCG_WR_ATCVH(base, (MCG_RD_ATCVH(base) & ~(mask)) | (value)))
+#define MCG_SET_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) |  (value)))
+#define MCG_CLR_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) & ~(value)))
+#define MCG_TOG_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_ATCVL register
+ */
+/*@{*/
+#define MCG_RD_ATCVL(base)       (MCG_ATCVL_REG(base))
+#define MCG_WR_ATCVL(base, value) (MCG_ATCVL_REG(base) = (value))
+#define MCG_RMW_ATCVL(base, mask, value) (MCG_WR_ATCVL(base, (MCG_RD_ATCVL(base) & ~(mask)) | (value)))
+#define MCG_SET_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) |  (value)))
+#define MCG_CLR_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) & ~(value)))
+#define MCG_TOG_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C7 - MCG Control 7 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C7 - MCG Control 7 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C7 register
+ */
+/*@{*/
+#define MCG_RD_C7(base)          (MCG_C7_REG(base))
+#define MCG_WR_C7(base, value)   (MCG_C7_REG(base) = (value))
+#define MCG_RMW_C7(base, mask, value) (MCG_WR_C7(base, (MCG_RD_C7(base) & ~(mask)) | (value)))
+#define MCG_SET_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) |  (value)))
+#define MCG_CLR_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) & ~(value)))
+#define MCG_TOG_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C7 bitfields
+ */
+
+/*!
+ * @name Register MCG_C7, field OSCSEL[1:0] (RW)
+ *
+ * Selects the MCG FLL external reference clock
+ *
+ * Values:
+ * - 0b00 - Selects Oscillator (OSCCLK0).
+ * - 0b01 - Selects 32 kHz RTC Oscillator.
+ * - 0b10 - Selects Oscillator (OSCCLK1).
+ * - 0b11 - RESERVED
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C7_OSCSEL field. */
+#define MCG_RD_C7_OSCSEL(base) ((MCG_C7_REG(base) & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
+#define MCG_BRD_C7_OSCSEL(base) (MCG_RD_C7_OSCSEL(base))
+
+/*! @brief Set the OSCSEL field to a new value. */
+#define MCG_WR_C7_OSCSEL(base, value) (MCG_RMW_C7(base, MCG_C7_OSCSEL_MASK, MCG_C7_OSCSEL(value)))
+#define MCG_BWR_C7_OSCSEL(base, value) (MCG_WR_C7_OSCSEL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C8 - MCG Control 8 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C8 - MCG Control 8 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C8 register
+ */
+/*@{*/
+#define MCG_RD_C8(base)          (MCG_C8_REG(base))
+#define MCG_WR_C8(base, value)   (MCG_C8_REG(base) = (value))
+#define MCG_RMW_C8(base, mask, value) (MCG_WR_C8(base, (MCG_RD_C8(base) & ~(mask)) | (value)))
+#define MCG_SET_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) |  (value)))
+#define MCG_CLR_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) & ~(value)))
+#define MCG_TOG_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C8 bitfields
+ */
+
+/*!
+ * @name Register MCG_C8, field LOCS1[0] (W1C)
+ *
+ * This bit indicates when a loss of clock has occurred. This bit is cleared by
+ * writing a logic 1 to it when set.
+ *
+ * Values:
+ * - 0b0 - Loss of RTC has not occur.
+ * - 0b1 - Loss of RTC has occur
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOCS1 field. */
+#define MCG_RD_C8_LOCS1(base) ((MCG_C8_REG(base) & MCG_C8_LOCS1_MASK) >> MCG_C8_LOCS1_SHIFT)
+#define MCG_BRD_C8_LOCS1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT))
+
+/*! @brief Set the LOCS1 field to a new value. */
+#define MCG_WR_C8_LOCS1(base, value) (MCG_RMW_C8(base, MCG_C8_LOCS1_MASK, MCG_C8_LOCS1(value)))
+#define MCG_BWR_C8_LOCS1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field CME1[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the output of the RTC
+ * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
+ * reset request is generated following a loss of RTC clock indication. The CME1
+ * bit should be set to a logic 1 when the MCG is in an operational mode that uses
+ * the RTC as its external reference clock or if the RTC is operational. CME1 bit
+ * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
+ * before entering VLPR or VLPW power modes.
+ *
+ * Values:
+ * - 0b0 - External clock monitor is disabled for RTC clock.
+ * - 0b1 - External clock monitor is enabled for RTC clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_CME1 field. */
+#define MCG_RD_C8_CME1(base) ((MCG_C8_REG(base) & MCG_C8_CME1_MASK) >> MCG_C8_CME1_SHIFT)
+#define MCG_BRD_C8_CME1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT))
+
+/*! @brief Set the CME1 field to a new value. */
+#define MCG_WR_C8_CME1(base, value) (MCG_RMW_C8(base, (MCG_C8_CME1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_CME1(value)))
+#define MCG_BWR_C8_CME1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field LOLRE[6] (RW)
+ *
+ * Determines if an interrupt or a reset request is made following a PLL loss of
+ * lock.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a PLL loss of lock indication. The
+ *     PLL loss of lock interrupt enable bit must also be set to generate the
+ *     interrupt request.
+ * - 0b1 - Generate a reset request on a PLL loss of lock indication.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOLRE field. */
+#define MCG_RD_C8_LOLRE(base) ((MCG_C8_REG(base) & MCG_C8_LOLRE_MASK) >> MCG_C8_LOLRE_SHIFT)
+#define MCG_BRD_C8_LOLRE(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOLRE_SHIFT))
+
+/*! @brief Set the LOLRE field to a new value. */
+#define MCG_WR_C8_LOLRE(base, value) (MCG_RMW_C8(base, (MCG_C8_LOLRE_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOLRE(value)))
+#define MCG_BWR_C8_LOLRE(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOLRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field LOCRE1[7] (RW)
+ *
+ * Determines if a interrupt or a reset request is made following a loss of RTC
+ * external reference clock. The LOCRE1 only has an affect when CME1 is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a loss of RTC external reference
+ *     clock.
+ * - 0b1 - Generate a reset request on a loss of RTC external reference clock
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOCRE1 field. */
+#define MCG_RD_C8_LOCRE1(base) ((MCG_C8_REG(base) & MCG_C8_LOCRE1_MASK) >> MCG_C8_LOCRE1_SHIFT)
+#define MCG_BRD_C8_LOCRE1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT))
+
+/*! @brief Set the LOCRE1 field to a new value. */
+#define MCG_WR_C8_LOCRE1(base, value) (MCG_RMW_C8(base, (MCG_C8_LOCRE1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOCRE1(value)))
+#define MCG_BWR_C8_LOCRE1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 MCM
+ *
+ * Core Platform Miscellaneous Control Module
+ *
+ * Registers defined in this header file:
+ * - MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ * - MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ * - MCM_CR - Control Register
+ * - MCM_ISCR - Interrupt Status Register
+ * - MCM_ETBCC - ETB Counter Control register
+ * - MCM_ETBRL - ETB Reload register
+ * - MCM_ETBCNT - ETB Counter Value register
+ * - MCM_PID - Process ID register
+ */
+
+#define MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
+#define MCM_IDX (0U) /*!< Instance number for MCM. */
+
+/*******************************************************************************
+ * MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
+ *
+ * Reset value: 0x001FU
+ *
+ * PLASC is a 16-bit read-only register identifying the presence/absence of bus
+ * slave connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLASC register
+ */
+/*@{*/
+#define MCM_RD_PLASC(base)       (MCM_PLASC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLASC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLASC, field ASC[7:0] (RO)
+ *
+ * Values:
+ * - 0b00000000 - A bus slave connection to AXBS input port n is absent
+ * - 0b00000001 - A bus slave connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLASC_ASC field. */
+#define MCM_RD_PLASC_ASC(base) ((MCM_PLASC_REG(base) & MCM_PLASC_ASC_MASK) >> MCM_PLASC_ASC_SHIFT)
+#define MCM_BRD_PLASC_ASC(base) (MCM_RD_PLASC_ASC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
+ *
+ * Reset value: 0x0037U
+ *
+ * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
+ * master connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLAMC register
+ */
+/*@{*/
+#define MCM_RD_PLAMC(base)       (MCM_PLAMC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLAMC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLAMC, field AMC[7:0] (RO)
+ *
+ * Values:
+ * - 0b00000000 - A bus master connection to AXBS input port n is absent
+ * - 0b00000001 - A bus master connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLAMC_AMC field. */
+#define MCM_RD_PLAMC_AMC(base) ((MCM_PLAMC_REG(base) & MCM_PLAMC_AMC_MASK) >> MCM_PLAMC_AMC_SHIFT)
+#define MCM_BRD_PLAMC_AMC(base) (MCM_RD_PLAMC_AMC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_CR - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CR defines the arbitration and protection schemes for the two system RAM
+ * arrays.
+ */
+/*!
+ * @name Constants and macros for entire MCM_CR register
+ */
+/*@{*/
+#define MCM_RD_CR(base)          (MCM_CR_REG(base))
+#define MCM_WR_CR(base, value)   (MCM_CR_REG(base) = (value))
+#define MCM_RMW_CR(base, mask, value) (MCM_WR_CR(base, (MCM_RD_CR(base) & ~(mask)) | (value)))
+#define MCM_SET_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) |  (value)))
+#define MCM_CLR_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) & ~(value)))
+#define MCM_TOG_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_CR bitfields
+ */
+
+/*!
+ * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_U array.
+ *
+ * Values:
+ * - 0b00 - Round robin
+ * - 0b01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 0b10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 0b11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMUAP field. */
+#define MCM_RD_CR_SRAMUAP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMUAP_MASK) >> MCM_CR_SRAMUAP_SHIFT)
+#define MCM_BRD_CR_SRAMUAP(base) (MCM_RD_CR_SRAMUAP(base))
+
+/*! @brief Set the SRAMUAP field to a new value. */
+#define MCM_WR_CR_SRAMUAP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMUAP_MASK, MCM_CR_SRAMUAP(value)))
+#define MCM_BWR_CR_SRAMUAP(base, value) (MCM_WR_CR_SRAMUAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMUWP[26] (RW)
+ *
+ * When this bit is set, writes to SRAM_U array generates a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMUWP field. */
+#define MCM_RD_CR_SRAMUWP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMUWP_MASK) >> MCM_CR_SRAMUWP_SHIFT)
+#define MCM_BRD_CR_SRAMUWP(base) (MCM_RD_CR_SRAMUWP(base))
+
+/*! @brief Set the SRAMUWP field to a new value. */
+#define MCM_WR_CR_SRAMUWP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMUWP_MASK, MCM_CR_SRAMUWP(value)))
+#define MCM_BWR_CR_SRAMUWP(base, value) (MCM_WR_CR_SRAMUWP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_L array.
+ *
+ * Values:
+ * - 0b00 - Round robin
+ * - 0b01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 0b10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 0b11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMLAP field. */
+#define MCM_RD_CR_SRAMLAP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMLAP_MASK) >> MCM_CR_SRAMLAP_SHIFT)
+#define MCM_BRD_CR_SRAMLAP(base) (MCM_RD_CR_SRAMLAP(base))
+
+/*! @brief Set the SRAMLAP field to a new value. */
+#define MCM_WR_CR_SRAMLAP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMLAP_MASK, MCM_CR_SRAMLAP(value)))
+#define MCM_BWR_CR_SRAMLAP(base, value) (MCM_WR_CR_SRAMLAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMLWP[30] (RW)
+ *
+ * When this bit is set, writes to SRAM_L array generates a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMLWP field. */
+#define MCM_RD_CR_SRAMLWP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMLWP_MASK) >> MCM_CR_SRAMLWP_SHIFT)
+#define MCM_BRD_CR_SRAMLWP(base) (MCM_RD_CR_SRAMLWP(base))
+
+/*! @brief Set the SRAMLWP field to a new value. */
+#define MCM_WR_CR_SRAMLWP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMLWP_MASK, MCM_CR_SRAMLWP(value)))
+#define MCM_BWR_CR_SRAMLWP(base, value) (MCM_WR_CR_SRAMLWP(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ISCR - Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ISCR - Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ISCR register
+ */
+/*@{*/
+#define MCM_RD_ISCR(base)        (MCM_ISCR_REG(base))
+#define MCM_WR_ISCR(base, value) (MCM_ISCR_REG(base) = (value))
+#define MCM_RMW_ISCR(base, mask, value) (MCM_WR_ISCR(base, (MCM_RD_ISCR(base) & ~(mask)) | (value)))
+#define MCM_SET_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) |  (value)))
+#define MCM_CLR_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) & ~(value)))
+#define MCM_TOG_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ISCR bitfields
+ */
+
+/*!
+ * @name Register MCM_ISCR, field IRQ[1] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0b0 - No pending interrupt
+ * - 0b1 - Due to the ETB counter expiring, a normal interrupt is pending
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_IRQ field. */
+#define MCM_RD_ISCR_IRQ(base) ((MCM_ISCR_REG(base) & MCM_ISCR_IRQ_MASK) >> MCM_ISCR_IRQ_SHIFT)
+#define MCM_BRD_ISCR_IRQ(base) (MCM_RD_ISCR_IRQ(base))
+
+/*! @brief Set the IRQ field to a new value. */
+#define MCM_WR_ISCR_IRQ(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_IRQ(value)))
+#define MCM_BWR_ISCR_IRQ(base, value) (MCM_WR_ISCR_IRQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field NMI[2] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0b0 - No pending NMI
+ * - 0b1 - Due to the ETB counter expiring, an NMI is pending
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_NMI field. */
+#define MCM_RD_ISCR_NMI(base) ((MCM_ISCR_REG(base) & MCM_ISCR_NMI_MASK) >> MCM_ISCR_NMI_SHIFT)
+#define MCM_BRD_ISCR_NMI(base) (MCM_RD_ISCR_NMI(base))
+
+/*! @brief Set the NMI field to a new value. */
+#define MCM_WR_ISCR_NMI(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_NMI_MASK | MCM_ISCR_IRQ_MASK), MCM_ISCR_NMI(value)))
+#define MCM_BWR_ISCR_NMI(base, value) (MCM_WR_ISCR_NMI(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field DHREQ[3] (RO)
+ *
+ * Indicates that a debug halt request is initiated due to a ETB counter
+ * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
+ * counter is disabled or when the ETB counter is reloaded.
+ *
+ * Values:
+ * - 0b0 - No debug halt request
+ * - 0b1 - Debug halt request initiated
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_DHREQ field. */
+#define MCM_RD_ISCR_DHREQ(base) ((MCM_ISCR_REG(base) & MCM_ISCR_DHREQ_MASK) >> MCM_ISCR_DHREQ_SHIFT)
+#define MCM_BRD_ISCR_DHREQ(base) (MCM_RD_ISCR_DHREQ(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIOC[8] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
+ * illegal operation has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IOC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIOC field. */
+#define MCM_RD_ISCR_FIOC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIOC_MASK) >> MCM_ISCR_FIOC_SHIFT)
+#define MCM_BRD_ISCR_FIOC(base) (MCM_RD_ISCR_FIOC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FDZC[9] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
+ * divide by zero has been detected in the processor's FPU. Once set, this bit remains
+ * set until software clears the FPSCR[DZC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FDZC field. */
+#define MCM_RD_ISCR_FDZC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FDZC_MASK) >> MCM_ISCR_FDZC_SHIFT)
+#define MCM_BRD_ISCR_FDZC(base) (MCM_RD_ISCR_FDZC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FOFC[10] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
+ * overflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[OFC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FOFC field. */
+#define MCM_RD_ISCR_FOFC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FOFC_MASK) >> MCM_ISCR_FOFC_SHIFT)
+#define MCM_BRD_ISCR_FOFC(base) (MCM_RD_ISCR_FOFC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FUFC[11] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
+ * underflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[UFC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FUFC field. */
+#define MCM_RD_ISCR_FUFC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FUFC_MASK) >> MCM_ISCR_FUFC_SHIFT)
+#define MCM_BRD_ISCR_FUFC(base) (MCM_RD_ISCR_FUFC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIXC[12] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
+ * inexact number has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IXC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIXC field. */
+#define MCM_RD_ISCR_FIXC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIXC_MASK) >> MCM_ISCR_FIXC_SHIFT)
+#define MCM_BRD_ISCR_FIXC(base) (MCM_RD_ISCR_FIXC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIDC[15] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
+ * denormalized number has been detected in the processor's FPU. Once set, this
+ * bit remains set until software clears the FPSCR[IDC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIDC field. */
+#define MCM_RD_ISCR_FIDC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIDC_MASK) >> MCM_ISCR_FIDC_SHIFT)
+#define MCM_BRD_ISCR_FIDC(base) (MCM_RD_ISCR_FIDC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIOCE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIOCE field. */
+#define MCM_RD_ISCR_FIOCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIOCE_MASK) >> MCM_ISCR_FIOCE_SHIFT)
+#define MCM_BRD_ISCR_FIOCE(base) (MCM_RD_ISCR_FIOCE(base))
+
+/*! @brief Set the FIOCE field to a new value. */
+#define MCM_WR_ISCR_FIOCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIOCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIOCE(value)))
+#define MCM_BWR_ISCR_FIOCE(base, value) (MCM_WR_ISCR_FIOCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FDZCE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FDZCE field. */
+#define MCM_RD_ISCR_FDZCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FDZCE_MASK) >> MCM_ISCR_FDZCE_SHIFT)
+#define MCM_BRD_ISCR_FDZCE(base) (MCM_RD_ISCR_FDZCE(base))
+
+/*! @brief Set the FDZCE field to a new value. */
+#define MCM_WR_ISCR_FDZCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FDZCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FDZCE(value)))
+#define MCM_BWR_ISCR_FDZCE(base, value) (MCM_WR_ISCR_FDZCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FOFCE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FOFCE field. */
+#define MCM_RD_ISCR_FOFCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FOFCE_MASK) >> MCM_ISCR_FOFCE_SHIFT)
+#define MCM_BRD_ISCR_FOFCE(base) (MCM_RD_ISCR_FOFCE(base))
+
+/*! @brief Set the FOFCE field to a new value. */
+#define MCM_WR_ISCR_FOFCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FOFCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FOFCE(value)))
+#define MCM_BWR_ISCR_FOFCE(base, value) (MCM_WR_ISCR_FOFCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FUFCE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FUFCE field. */
+#define MCM_RD_ISCR_FUFCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FUFCE_MASK) >> MCM_ISCR_FUFCE_SHIFT)
+#define MCM_BRD_ISCR_FUFCE(base) (MCM_RD_ISCR_FUFCE(base))
+
+/*! @brief Set the FUFCE field to a new value. */
+#define MCM_WR_ISCR_FUFCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FUFCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FUFCE(value)))
+#define MCM_BWR_ISCR_FUFCE(base, value) (MCM_WR_ISCR_FUFCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIXCE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIXCE field. */
+#define MCM_RD_ISCR_FIXCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIXCE_MASK) >> MCM_ISCR_FIXCE_SHIFT)
+#define MCM_BRD_ISCR_FIXCE(base) (MCM_RD_ISCR_FIXCE(base))
+
+/*! @brief Set the FIXCE field to a new value. */
+#define MCM_WR_ISCR_FIXCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIXCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIXCE(value)))
+#define MCM_BWR_ISCR_FIXCE(base, value) (MCM_WR_ISCR_FIXCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIDCE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIDCE field. */
+#define MCM_RD_ISCR_FIDCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIDCE_MASK) >> MCM_ISCR_FIDCE_SHIFT)
+#define MCM_BRD_ISCR_FIDCE(base) (MCM_RD_ISCR_FIDCE(base))
+
+/*! @brief Set the FIDCE field to a new value. */
+#define MCM_WR_ISCR_FIDCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIDCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIDCE(value)))
+#define MCM_BWR_ISCR_FIDCE(base, value) (MCM_WR_ISCR_FIDCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBCC - ETB Counter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBCC - ETB Counter Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBCC register
+ */
+/*@{*/
+#define MCM_RD_ETBCC(base)       (MCM_ETBCC_REG(base))
+#define MCM_WR_ETBCC(base, value) (MCM_ETBCC_REG(base) = (value))
+#define MCM_RMW_ETBCC(base, mask, value) (MCM_WR_ETBCC(base, (MCM_RD_ETBCC(base) & ~(mask)) | (value)))
+#define MCM_SET_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) |  (value)))
+#define MCM_CLR_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) & ~(value)))
+#define MCM_TOG_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBCC bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCC, field CNTEN[0] (RW)
+ *
+ * Enables the ETB counter.
+ *
+ * Values:
+ * - 0b0 - ETB counter disabled
+ * - 0b1 - ETB counter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_CNTEN field. */
+#define MCM_RD_ETBCC_CNTEN(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_CNTEN_MASK) >> MCM_ETBCC_CNTEN_SHIFT)
+#define MCM_BRD_ETBCC_CNTEN(base) (MCM_RD_ETBCC_CNTEN(base))
+
+/*! @brief Set the CNTEN field to a new value. */
+#define MCM_WR_ETBCC_CNTEN(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_CNTEN_MASK, MCM_ETBCC_CNTEN(value)))
+#define MCM_BWR_ETBCC_CNTEN(base, value) (MCM_WR_ETBCC_CNTEN(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
+ *
+ * Values:
+ * - 0b00 - No response when the ETB count expires
+ * - 0b01 - Generate a normal interrupt when the ETB count expires
+ * - 0b10 - Generate an NMI when the ETB count expires
+ * - 0b11 - Generate a debug halt when the ETB count expires
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_RSPT field. */
+#define MCM_RD_ETBCC_RSPT(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_RSPT_MASK) >> MCM_ETBCC_RSPT_SHIFT)
+#define MCM_BRD_ETBCC_RSPT(base) (MCM_RD_ETBCC_RSPT(base))
+
+/*! @brief Set the RSPT field to a new value. */
+#define MCM_WR_ETBCC_RSPT(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_RSPT_MASK, MCM_ETBCC_RSPT(value)))
+#define MCM_BWR_ETBCC_RSPT(base, value) (MCM_WR_ETBCC_RSPT(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field RLRQ[3] (RW)
+ *
+ * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
+ * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
+ * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
+ * If debug halt was enabled and a debug halt request was asserted on counter
+ * expiration, setting this bit clears the debug halt request.
+ *
+ * Values:
+ * - 0b0 - No effect
+ * - 0b1 - Clears pending debug halt, NMI, or IRQ interrupt requests
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_RLRQ field. */
+#define MCM_RD_ETBCC_RLRQ(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_RLRQ_MASK) >> MCM_ETBCC_RLRQ_SHIFT)
+#define MCM_BRD_ETBCC_RLRQ(base) (MCM_RD_ETBCC_RLRQ(base))
+
+/*! @brief Set the RLRQ field to a new value. */
+#define MCM_WR_ETBCC_RLRQ(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_RLRQ_MASK, MCM_ETBCC_RLRQ(value)))
+#define MCM_BWR_ETBCC_RLRQ(base, value) (MCM_WR_ETBCC_RLRQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field ETDIS[4] (RW)
+ *
+ * Disables the trace path from ETM to TPIU.
+ *
+ * Values:
+ * - 0b0 - ETM-to-TPIU trace path enabled
+ * - 0b1 - ETM-to-TPIU trace path disabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_ETDIS field. */
+#define MCM_RD_ETBCC_ETDIS(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_ETDIS_MASK) >> MCM_ETBCC_ETDIS_SHIFT)
+#define MCM_BRD_ETBCC_ETDIS(base) (MCM_RD_ETBCC_ETDIS(base))
+
+/*! @brief Set the ETDIS field to a new value. */
+#define MCM_WR_ETBCC_ETDIS(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_ETDIS_MASK, MCM_ETBCC_ETDIS(value)))
+#define MCM_BWR_ETBCC_ETDIS(base, value) (MCM_WR_ETBCC_ETDIS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field ITDIS[5] (RW)
+ *
+ * Disables the trace path from ITM to TPIU.
+ *
+ * Values:
+ * - 0b0 - ITM-to-TPIU trace path enabled
+ * - 0b1 - ITM-to-TPIU trace path disabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_ITDIS field. */
+#define MCM_RD_ETBCC_ITDIS(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_ITDIS_MASK) >> MCM_ETBCC_ITDIS_SHIFT)
+#define MCM_BRD_ETBCC_ITDIS(base) (MCM_RD_ETBCC_ITDIS(base))
+
+/*! @brief Set the ITDIS field to a new value. */
+#define MCM_WR_ETBCC_ITDIS(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_ITDIS_MASK, MCM_ETBCC_ITDIS(value)))
+#define MCM_BWR_ETBCC_ITDIS(base, value) (MCM_WR_ETBCC_ITDIS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBRL - ETB Reload register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBRL - ETB Reload register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBRL register
+ */
+/*@{*/
+#define MCM_RD_ETBRL(base)       (MCM_ETBRL_REG(base))
+#define MCM_WR_ETBRL(base, value) (MCM_ETBRL_REG(base) = (value))
+#define MCM_RMW_ETBRL(base, mask, value) (MCM_WR_ETBRL(base, (MCM_RD_ETBRL(base) & ~(mask)) | (value)))
+#define MCM_SET_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) |  (value)))
+#define MCM_CLR_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) & ~(value)))
+#define MCM_TOG_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBRL bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
+ *
+ * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
+ * value to this field results in a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBRL_RELOAD field. */
+#define MCM_RD_ETBRL_RELOAD(base) ((MCM_ETBRL_REG(base) & MCM_ETBRL_RELOAD_MASK) >> MCM_ETBRL_RELOAD_SHIFT)
+#define MCM_BRD_ETBRL_RELOAD(base) (MCM_RD_ETBRL_RELOAD(base))
+
+/*! @brief Set the RELOAD field to a new value. */
+#define MCM_WR_ETBRL_RELOAD(base, value) (MCM_RMW_ETBRL(base, MCM_ETBRL_RELOAD_MASK, MCM_ETBRL_RELOAD(value)))
+#define MCM_BWR_ETBRL_RELOAD(base, value) (MCM_WR_ETBRL_RELOAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBCNT - ETB Counter Value register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBCNT - ETB Counter Value register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBCNT register
+ */
+/*@{*/
+#define MCM_RD_ETBCNT(base)      (MCM_ETBCNT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBCNT bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
+ *
+ * Indicates the current 0-mod-4 value of the counter.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCNT_COUNTER field. */
+#define MCM_RD_ETBCNT_COUNTER(base) ((MCM_ETBCNT_REG(base) & MCM_ETBCNT_COUNTER_MASK) >> MCM_ETBCNT_COUNTER_SHIFT)
+#define MCM_BRD_ETBCNT_COUNTER(base) (MCM_RD_ETBCNT_COUNTER(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PID - Process ID register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PID - Process ID register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register drives the M0_PID and M1_PID values in the Memory Protection
+ * Unit(MPU). System software loads this register before passing control to a given
+ * user mode process. If the PID of the process does not match the value in this
+ * register, a bus error occurs. See the MPU chapter for more details.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PID register
+ */
+/*@{*/
+#define MCM_RD_PID(base)         (MCM_PID_REG(base))
+#define MCM_WR_PID(base, value)  (MCM_PID_REG(base) = (value))
+#define MCM_RMW_PID(base, mask, value) (MCM_WR_PID(base, (MCM_RD_PID(base) & ~(mask)) | (value)))
+#define MCM_SET_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) |  (value)))
+#define MCM_CLR_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) & ~(value)))
+#define MCM_TOG_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PID bitfields
+ */
+
+/*!
+ * @name Register MCM_PID, field PID[7:0] (RW)
+ *
+ * Drives the M0_PID and M1_PID values in the MPU.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PID_PID field. */
+#define MCM_RD_PID_PID(base) ((MCM_PID_REG(base) & MCM_PID_PID_MASK) >> MCM_PID_PID_SHIFT)
+#define MCM_BRD_PID_PID(base) (MCM_RD_PID_PID(base))
+
+/*! @brief Set the PID field to a new value. */
+#define MCM_WR_PID_PID(base, value) (MCM_RMW_PID(base, MCM_PID_PID_MASK, MCM_PID_PID(value)))
+#define MCM_BWR_PID_PID(base, value) (MCM_WR_PID_PID(base, value))
+/*@}*/
+
+/*
+ * MK64F12 MPU
+ *
+ * Memory protection unit
+ *
+ * Registers defined in this header file:
+ * - MPU_CESR - Control/Error Status Register
+ * - MPU_EAR - Error Address Register, slave port n
+ * - MPU_EDR - Error Detail Register, slave port n
+ * - MPU_WORD - Region Descriptor n, Word 0
+ * - MPU_RGDAAC - Region Descriptor Alternate Access Control n
+ */
+
+#define MPU_INSTANCE_COUNT (1U) /*!< Number of instances of the MPU module. */
+#define MPU_IDX (0U) /*!< Instance number for MPU. */
+
+/*******************************************************************************
+ * MPU_CESR - Control/Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_CESR - Control/Error Status Register (RW)
+ *
+ * Reset value: 0x00815101U
+ */
+/*!
+ * @name Constants and macros for entire MPU_CESR register
+ */
+/*@{*/
+#define MPU_RD_CESR(base)        (MPU_CESR_REG(base))
+#define MPU_WR_CESR(base, value) (MPU_CESR_REG(base) = (value))
+#define MPU_RMW_CESR(base, mask, value) (MPU_WR_CESR(base, (MPU_RD_CESR(base) & ~(mask)) | (value)))
+#define MPU_SET_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) |  (value)))
+#define MPU_CLR_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) & ~(value)))
+#define MPU_TOG_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_CESR bitfields
+ */
+
+/*!
+ * @name Register MPU_CESR, field VLD[0] (RW)
+ *
+ * Global enable/disable for the MPU.
+ *
+ * Values:
+ * - 0b0 - MPU is disabled. All accesses from all bus masters are allowed.
+ * - 0b1 - MPU is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_VLD field. */
+#define MPU_RD_CESR_VLD(base) ((MPU_CESR_REG(base) & MPU_CESR_VLD_MASK) >> MPU_CESR_VLD_SHIFT)
+#define MPU_BRD_CESR_VLD(base) (BITBAND_ACCESS32(&MPU_CESR_REG(base), MPU_CESR_VLD_SHIFT))
+
+/*! @brief Set the VLD field to a new value. */
+#define MPU_WR_CESR_VLD(base, value) (MPU_RMW_CESR(base, (MPU_CESR_VLD_MASK | MPU_CESR_SPERR_MASK), MPU_CESR_VLD(value)))
+#define MPU_BWR_CESR_VLD(base, value) (BITBAND_ACCESS32(&MPU_CESR_REG(base), MPU_CESR_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field NRGD[11:8] (RO)
+ *
+ * Indicates the number of region descriptors implemented in the MPU.
+ *
+ * Values:
+ * - 0b0000 - 8 region descriptors
+ * - 0b0001 - 12 region descriptors
+ * - 0b0010 - 16 region descriptors
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_NRGD field. */
+#define MPU_RD_CESR_NRGD(base) ((MPU_CESR_REG(base) & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT)
+#define MPU_BRD_CESR_NRGD(base) (MPU_RD_CESR_NRGD(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field NSP[15:12] (RO)
+ *
+ * Specifies the number of slave ports connected to the MPU.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_NSP field. */
+#define MPU_RD_CESR_NSP(base) ((MPU_CESR_REG(base) & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT)
+#define MPU_BRD_CESR_NSP(base) (MPU_RD_CESR_NSP(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field HRL[19:16] (RO)
+ *
+ * Specifies the MPU's hardware and definition revision level. It can be read by
+ * software to determine the functional definition of the module.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_HRL field. */
+#define MPU_RD_CESR_HRL(base) ((MPU_CESR_REG(base) & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT)
+#define MPU_BRD_CESR_HRL(base) (MPU_RD_CESR_HRL(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field SPERR[31:27] (W1C)
+ *
+ * Indicates a captured error in EARn and EDRn. This bit is set when the
+ * hardware detects an error and records the faulting address and attributes. It is
+ * cleared by writing one to it. If another error is captured at the exact same cycle
+ * as the write, the flag remains set. A find-first-one instruction or
+ * equivalent can detect the presence of a captured error. The following shows the
+ * correspondence between the bit number and slave port number: Bit 31 corresponds to
+ * slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
+ * port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
+ *
+ * Values:
+ * - 0b00000 - No error has occurred for slave port n.
+ * - 0b00001 - An error has occurred for slave port n.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_SPERR field. */
+#define MPU_RD_CESR_SPERR(base) ((MPU_CESR_REG(base) & MPU_CESR_SPERR_MASK) >> MPU_CESR_SPERR_SHIFT)
+#define MPU_BRD_CESR_SPERR(base) (MPU_RD_CESR_SPERR(base))
+
+/*! @brief Set the SPERR field to a new value. */
+#define MPU_WR_CESR_SPERR(base, value) (MPU_RMW_CESR(base, MPU_CESR_SPERR_MASK, MPU_CESR_SPERR(value)))
+#define MPU_BWR_CESR_SPERR(base, value) (MPU_WR_CESR_SPERR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_EAR - Error Address Register, slave port n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_EAR - Error Address Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, the 32-bit reference
+ * address is captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] set. Additional information about the faulting access is captured in
+ * the corresponding EDRn at the same time. This register and the corresponding
+ * EDRn contain the most recent access error; there are no hardware interlocks with
+ * CESR[SPERR], as the error registers are always loaded upon the occurrence of
+ * each protection violation.
+ */
+/*!
+ * @name Constants and macros for entire MPU_EAR register
+ */
+/*@{*/
+#define MPU_RD_EAR(base, index)  (MPU_EAR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_EDR - Error Detail Register, slave port n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_EDR - Error Detail Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, 32 bits of error detail
+ * are captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] is set. Information on the faulting address is captured in the
+ * corresponding EARn register at the same time. This register and the corresponding EARn
+ * register contain the most recent access error; there are no hardware interlocks
+ * with CESR[SPERR] as the error registers are always loaded upon the occurrence
+ * of each protection violation.
+ */
+/*!
+ * @name Constants and macros for entire MPU_EDR register
+ */
+/*@{*/
+#define MPU_RD_EDR(base, index)  (MPU_EDR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_EDR bitfields
+ */
+
+/*!
+ * @name Register MPU_EDR, field ERW[0] (RO)
+ *
+ * Indicates the access type of the faulting reference.
+ *
+ * Values:
+ * - 0b0 - Read
+ * - 0b1 - Write
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_ERW field. */
+#define MPU_RD_EDR_ERW(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT)
+#define MPU_BRD_EDR_ERW(base, index) (BITBAND_ACCESS32(&MPU_EDR_REG(base, index), MPU_EDR_ERW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EATTR[3:1] (RO)
+ *
+ * Indicates attribute information about the faulting reference. All other
+ * encodings are reserved.
+ *
+ * Values:
+ * - 0b000 - User mode, instruction access
+ * - 0b001 - User mode, data access
+ * - 0b010 - Supervisor mode, instruction access
+ * - 0b011 - Supervisor mode, data access
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EATTR field. */
+#define MPU_RD_EDR_EATTR(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT)
+#define MPU_BRD_EDR_EATTR(base, index) (MPU_RD_EDR_EATTR(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EMN[7:4] (RO)
+ *
+ * Indicates the bus master that generated the access error.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EMN field. */
+#define MPU_RD_EDR_EMN(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT)
+#define MPU_BRD_EDR_EMN(base, index) (MPU_RD_EDR_EMN(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EPID[15:8] (RO)
+ *
+ * Records the process identifier of the faulting reference. The process
+ * identifier is typically driven only by processor cores; for other bus masters, this
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EPID field. */
+#define MPU_RD_EDR_EPID(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT)
+#define MPU_BRD_EDR_EPID(base, index) (MPU_RD_EDR_EPID(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EACD[31:16] (RO)
+ *
+ * Indicates the region descriptor with the access error. If EDRn contains a
+ * captured error and EACD is cleared, an access did not hit in any region
+ * descriptor. If only a single EACD bit is set, the protection error was caused by a
+ * single non-overlapping region descriptor. If two or more EACD bits are set, the
+ * protection error was caused by an overlapping set of region descriptors.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EACD field. */
+#define MPU_RD_EDR_EACD(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EACD_MASK) >> MPU_EDR_EACD_SHIFT)
+#define MPU_BRD_EDR_EACD(base, index) (MPU_RD_EDR_EACD(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_WORD - Region Descriptor n, Word 0
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_WORD - Region Descriptor n, Word 0 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The first word of the region descriptor defines the 0-modulo-32 byte start
+ * address of the memory region. Writes to this register clear the region
+ * descriptor's valid bit (RGDn_WORD3[VLD]).
+ */
+/*!
+ * @name Constants and macros for entire MPU_WORD register
+ */
+/*@{*/
+#define MPU_RD_WORD(base, index, index2) (MPU_WORD_REG(base, index, index2))
+#define MPU_WR_WORD(base, index, index2, value) (MPU_WORD_REG(base, index, index2) = (value))
+#define MPU_RMW_WORD(base, index, index2, mask, value) (MPU_WR_WORD(base, index, index2, (MPU_RD_WORD(base, index, index2) & ~(mask)) | (value)))
+#define MPU_SET_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) |  (value)))
+#define MPU_CLR_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) & ~(value)))
+#define MPU_TOG_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_WORD bitfields
+ */
+
+/*!
+ * @name Register MPU_WORD, field VLD[0] (RW)
+ *
+ * Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
+ * bit.
+ *
+ * Values:
+ * - 0b0 - Region descriptor is invalid
+ * - 0b1 - Region descriptor is valid
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_VLD field. */
+#define MPU_RD_WORD_VLD(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_VLD_MASK) >> MPU_WORD_VLD_SHIFT)
+#define MPU_BRD_WORD_VLD(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_VLD_SHIFT))
+
+/*! @brief Set the VLD field to a new value. */
+#define MPU_WR_WORD_VLD(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_VLD_MASK, MPU_WORD_VLD(value)))
+#define MPU_BWR_WORD_VLD(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0UM field. */
+#define MPU_RD_WORD_M0UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0UM_MASK) >> MPU_WORD_M0UM_SHIFT)
+#define MPU_BRD_WORD_M0UM(base, index, index2) (MPU_RD_WORD_M0UM(base, index, index2))
+
+/*! @brief Set the M0UM field to a new value. */
+#define MPU_WR_WORD_M0UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0UM_MASK, MPU_WORD_M0UM(value)))
+#define MPU_BWR_WORD_M0UM(base, index, index2, value) (MPU_WR_WORD_M0UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0SM field. */
+#define MPU_RD_WORD_M0SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0SM_MASK) >> MPU_WORD_M0SM_SHIFT)
+#define MPU_BRD_WORD_M0SM(base, index, index2) (MPU_RD_WORD_M0SM(base, index, index2))
+
+/*! @brief Set the M0SM field to a new value. */
+#define MPU_WR_WORD_M0SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0SM_MASK, MPU_WORD_M0SM(value)))
+#define MPU_BWR_WORD_M0SM(base, index, index2, value) (MPU_WR_WORD_M0SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0PE[5] (RW)
+ *
+ * See M0PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0PE field. */
+#define MPU_RD_WORD_M0PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0PE_MASK) >> MPU_WORD_M0PE_SHIFT)
+#define MPU_BRD_WORD_M0PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M0PE_SHIFT))
+
+/*! @brief Set the M0PE field to a new value. */
+#define MPU_WR_WORD_M0PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0PE_MASK, MPU_WORD_M0PE(value)))
+#define MPU_BWR_WORD_M0PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M0PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field ENDADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 31-modulo-32 byte end address of the
+ * memory region. The MPU does not verify that ENDADDR >= SRTADDR.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_ENDADDR field. */
+#define MPU_RD_WORD_ENDADDR(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_ENDADDR_MASK) >> MPU_WORD_ENDADDR_SHIFT)
+#define MPU_BRD_WORD_ENDADDR(base, index, index2) (MPU_RD_WORD_ENDADDR(base, index, index2))
+
+/*! @brief Set the ENDADDR field to a new value. */
+#define MPU_WR_WORD_ENDADDR(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_ENDADDR_MASK, MPU_WORD_ENDADDR(value)))
+#define MPU_BWR_WORD_ENDADDR(base, index, index2, value) (MPU_WR_WORD_ENDADDR(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field SRTADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 0-modulo-32 byte start address of
+ * the memory region.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_SRTADDR field. */
+#define MPU_RD_WORD_SRTADDR(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_SRTADDR_MASK) >> MPU_WORD_SRTADDR_SHIFT)
+#define MPU_BRD_WORD_SRTADDR(base, index, index2) (MPU_RD_WORD_SRTADDR(base, index, index2))
+
+/*! @brief Set the SRTADDR field to a new value. */
+#define MPU_WR_WORD_SRTADDR(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_SRTADDR_MASK, MPU_WORD_SRTADDR(value)))
+#define MPU_BWR_WORD_SRTADDR(base, index, index2, value) (MPU_WR_WORD_SRTADDR(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1UM field. */
+#define MPU_RD_WORD_M1UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1UM_MASK) >> MPU_WORD_M1UM_SHIFT)
+#define MPU_BRD_WORD_M1UM(base, index, index2) (MPU_RD_WORD_M1UM(base, index, index2))
+
+/*! @brief Set the M1UM field to a new value. */
+#define MPU_WR_WORD_M1UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1UM_MASK, MPU_WORD_M1UM(value)))
+#define MPU_BWR_WORD_M1UM(base, index, index2, value) (MPU_WR_WORD_M1UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1SM field. */
+#define MPU_RD_WORD_M1SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1SM_MASK) >> MPU_WORD_M1SM_SHIFT)
+#define MPU_BRD_WORD_M1SM(base, index, index2) (MPU_RD_WORD_M1SM(base, index, index2))
+
+/*! @brief Set the M1SM field to a new value. */
+#define MPU_WR_WORD_M1SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1SM_MASK, MPU_WORD_M1SM(value)))
+#define MPU_BWR_WORD_M1SM(base, index, index2, value) (MPU_WR_WORD_M1SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1PE field. */
+#define MPU_RD_WORD_M1PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1PE_MASK) >> MPU_WORD_M1PE_SHIFT)
+#define MPU_BRD_WORD_M1PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M1PE_SHIFT))
+
+/*! @brief Set the M1PE field to a new value. */
+#define MPU_WR_WORD_M1PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1PE_MASK, MPU_WORD_M1PE(value)))
+#define MPU_BWR_WORD_M1PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M1PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2UM field. */
+#define MPU_RD_WORD_M2UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2UM_MASK) >> MPU_WORD_M2UM_SHIFT)
+#define MPU_BRD_WORD_M2UM(base, index, index2) (MPU_RD_WORD_M2UM(base, index, index2))
+
+/*! @brief Set the M2UM field to a new value. */
+#define MPU_WR_WORD_M2UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2UM_MASK, MPU_WORD_M2UM(value)))
+#define MPU_BWR_WORD_M2UM(base, index, index2, value) (MPU_WR_WORD_M2UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2SM field. */
+#define MPU_RD_WORD_M2SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2SM_MASK) >> MPU_WORD_M2SM_SHIFT)
+#define MPU_BRD_WORD_M2SM(base, index, index2) (MPU_RD_WORD_M2SM(base, index, index2))
+
+/*! @brief Set the M2SM field to a new value. */
+#define MPU_WR_WORD_M2SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2SM_MASK, MPU_WORD_M2SM(value)))
+#define MPU_BWR_WORD_M2SM(base, index, index2, value) (MPU_WR_WORD_M2SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field PIDMASK[23:16] (RW)
+ *
+ * Provides a masking capability so that multiple process identifiers can be
+ * included as part of the region hit determination. If a bit in PIDMASK is set,
+ * then the corresponding PID bit is ignored in the comparison. This field and PID
+ * are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
+ * more information on the handling of the PID and PIDMASK, see "Access Evaluation
+ * - Hit Determination."
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_PIDMASK field. */
+#define MPU_RD_WORD_PIDMASK(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_PIDMASK_MASK) >> MPU_WORD_PIDMASK_SHIFT)
+#define MPU_BRD_WORD_PIDMASK(base, index, index2) (MPU_RD_WORD_PIDMASK(base, index, index2))
+
+/*! @brief Set the PIDMASK field to a new value. */
+#define MPU_WR_WORD_PIDMASK(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_PIDMASK_MASK, MPU_WORD_PIDMASK(value)))
+#define MPU_BWR_WORD_PIDMASK(base, index, index2, value) (MPU_WR_WORD_PIDMASK(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2PE field. */
+#define MPU_RD_WORD_M2PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2PE_MASK) >> MPU_WORD_M2PE_SHIFT)
+#define MPU_BRD_WORD_M2PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M2PE_SHIFT))
+
+/*! @brief Set the M2PE field to a new value. */
+#define MPU_WR_WORD_M2PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2PE_MASK, MPU_WORD_M2PE(value)))
+#define MPU_BWR_WORD_M2PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M2PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in User mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0b000 - An attempted access of that mode may be terminated with an access
+ *     error (if not allowed by another descriptor) and the access not performed.
+ * - 0b001 - Allows the given access type to occur
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3UM field. */
+#define MPU_RD_WORD_M3UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3UM_MASK) >> MPU_WORD_M3UM_SHIFT)
+#define MPU_BRD_WORD_M3UM(base, index, index2) (MPU_RD_WORD_M3UM(base, index, index2))
+
+/*! @brief Set the M3UM field to a new value. */
+#define MPU_WR_WORD_M3UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3UM_MASK, MPU_WORD_M3UM(value)))
+#define MPU_BWR_WORD_M3UM(base, index, index2, value) (MPU_WR_WORD_M3UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 0b00 - r/w/x; read, write and execute allowed
+ * - 0b01 - r/x; read and execute allowed, but no write
+ * - 0b10 - r/w; read and write allowed, but no execute
+ * - 0b11 - Same as User mode defined in M3UM
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3SM field. */
+#define MPU_RD_WORD_M3SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3SM_MASK) >> MPU_WORD_M3SM_SHIFT)
+#define MPU_BRD_WORD_M3SM(base, index, index2) (MPU_RD_WORD_M3SM(base, index, index2))
+
+/*! @brief Set the M3SM field to a new value. */
+#define MPU_WR_WORD_M3SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3SM_MASK, MPU_WORD_M3SM(value)))
+#define MPU_BWR_WORD_M3SM(base, index, index2, value) (MPU_WR_WORD_M3SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the process identifier in the evaluation
+ * - 0b1 - Include the process identifier and mask (RGDn_WORD3) in the region
+ *     hit evaluation
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3PE field. */
+#define MPU_RD_WORD_M3PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3PE_MASK) >> MPU_WORD_M3PE_SHIFT)
+#define MPU_BRD_WORD_M3PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M3PE_SHIFT))
+
+/*! @brief Set the M3PE field to a new value. */
+#define MPU_WR_WORD_M3PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3PE_MASK, MPU_WORD_M3PE(value)))
+#define MPU_BWR_WORD_M3PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M3PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field PID[31:24] (RW)
+ *
+ * Specifies the process identifier that is included in the region hit
+ * determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
+ * field.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_PID field. */
+#define MPU_RD_WORD_PID(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_PID_MASK) >> MPU_WORD_PID_SHIFT)
+#define MPU_BRD_WORD_PID(base, index, index2) (MPU_RD_WORD_PID(base, index, index2))
+
+/*! @brief Set the PID field to a new value. */
+#define MPU_WR_WORD_PID(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_PID_MASK, MPU_WORD_PID(value)))
+#define MPU_BWR_WORD_PID(base, index, index2, value) (MPU_WR_WORD_PID(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 4 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M4WE field. */
+#define MPU_RD_WORD_M4WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M4WE_MASK) >> MPU_WORD_M4WE_SHIFT)
+#define MPU_BRD_WORD_M4WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4WE_SHIFT))
+
+/*! @brief Set the M4WE field to a new value. */
+#define MPU_WR_WORD_M4WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M4WE_MASK, MPU_WORD_M4WE(value)))
+#define MPU_BWR_WORD_M4WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 4 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M4RE field. */
+#define MPU_RD_WORD_M4RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M4RE_MASK) >> MPU_WORD_M4RE_SHIFT)
+#define MPU_BRD_WORD_M4RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4RE_SHIFT))
+
+/*! @brief Set the M4RE field to a new value. */
+#define MPU_WR_WORD_M4RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M4RE_MASK, MPU_WORD_M4RE(value)))
+#define MPU_BWR_WORD_M4RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 5 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M5WE field. */
+#define MPU_RD_WORD_M5WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M5WE_MASK) >> MPU_WORD_M5WE_SHIFT)
+#define MPU_BRD_WORD_M5WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5WE_SHIFT))
+
+/*! @brief Set the M5WE field to a new value. */
+#define MPU_WR_WORD_M5WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M5WE_MASK, MPU_WORD_M5WE(value)))
+#define MPU_BWR_WORD_M5WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 5 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M5RE field. */
+#define MPU_RD_WORD_M5RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M5RE_MASK) >> MPU_WORD_M5RE_SHIFT)
+#define MPU_BRD_WORD_M5RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5RE_SHIFT))
+
+/*! @brief Set the M5RE field to a new value. */
+#define MPU_WR_WORD_M5RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M5RE_MASK, MPU_WORD_M5RE(value)))
+#define MPU_BWR_WORD_M5RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 6 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M6WE field. */
+#define MPU_RD_WORD_M6WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M6WE_MASK) >> MPU_WORD_M6WE_SHIFT)
+#define MPU_BRD_WORD_M6WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6WE_SHIFT))
+
+/*! @brief Set the M6WE field to a new value. */
+#define MPU_WR_WORD_M6WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M6WE_MASK, MPU_WORD_M6WE(value)))
+#define MPU_BWR_WORD_M6WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 6 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M6RE field. */
+#define MPU_RD_WORD_M6RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M6RE_MASK) >> MPU_WORD_M6RE_SHIFT)
+#define MPU_BRD_WORD_M6RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6RE_SHIFT))
+
+/*! @brief Set the M6RE field to a new value. */
+#define MPU_WR_WORD_M6RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M6RE_MASK, MPU_WORD_M6RE(value)))
+#define MPU_BWR_WORD_M6RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 7 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M7WE field. */
+#define MPU_RD_WORD_M7WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M7WE_MASK) >> MPU_WORD_M7WE_SHIFT)
+#define MPU_BRD_WORD_M7WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7WE_SHIFT))
+
+/*! @brief Set the M7WE field to a new value. */
+#define MPU_WR_WORD_M7WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M7WE_MASK, MPU_WORD_M7WE(value)))
+#define MPU_BWR_WORD_M7WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 7 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M7RE field. */
+#define MPU_RD_WORD_M7RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M7RE_MASK) >> MPU_WORD_M7RE_SHIFT)
+#define MPU_BRD_WORD_M7RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7RE_SHIFT))
+
+/*! @brief Set the M7RE field to a new value. */
+#define MPU_WR_WORD_M7RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M7RE_MASK, MPU_WORD_M7RE(value)))
+#define MPU_BWR_WORD_M7RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_RGDAAC - Region Descriptor Alternate Access Control n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_RGDAAC - Region Descriptor Alternate Access Control n (RW)
+ *
+ * Reset value: 0x0061F7DFU
+ *
+ * Because software may adjust only the access controls within a region
+ * descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
+ * this 32-bit entity is available. Writing to this register does not affect the
+ * descriptor's valid bit.
+ */
+/*!
+ * @name Constants and macros for entire MPU_RGDAAC register
+ */
+/*@{*/
+#define MPU_RD_RGDAAC(base, index) (MPU_RGDAAC_REG(base, index))
+#define MPU_WR_RGDAAC(base, index, value) (MPU_RGDAAC_REG(base, index) = (value))
+#define MPU_RMW_RGDAAC(base, index, mask, value) (MPU_WR_RGDAAC(base, index, (MPU_RD_RGDAAC(base, index) & ~(mask)) | (value)))
+#define MPU_SET_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) |  (value)))
+#define MPU_CLR_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) & ~(value)))
+#define MPU_TOG_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_RGDAAC bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDAAC, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0UM field. */
+#define MPU_RD_RGDAAC_M0UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0UM_MASK) >> MPU_RGDAAC_M0UM_SHIFT)
+#define MPU_BRD_RGDAAC_M0UM(base, index) (MPU_RD_RGDAAC_M0UM(base, index))
+
+/*! @brief Set the M0UM field to a new value. */
+#define MPU_WR_RGDAAC_M0UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0UM_MASK, MPU_RGDAAC_M0UM(value)))
+#define MPU_BWR_RGDAAC_M0UM(base, index, value) (MPU_WR_RGDAAC_M0UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0SM field. */
+#define MPU_RD_RGDAAC_M0SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0SM_MASK) >> MPU_RGDAAC_M0SM_SHIFT)
+#define MPU_BRD_RGDAAC_M0SM(base, index) (MPU_RD_RGDAAC_M0SM(base, index))
+
+/*! @brief Set the M0SM field to a new value. */
+#define MPU_WR_RGDAAC_M0SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0SM_MASK, MPU_RGDAAC_M0SM(value)))
+#define MPU_BWR_RGDAAC_M0SM(base, index, value) (MPU_WR_RGDAAC_M0SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M0PE[5] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0PE field. */
+#define MPU_RD_RGDAAC_M0PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0PE_MASK) >> MPU_RGDAAC_M0PE_SHIFT)
+#define MPU_BRD_RGDAAC_M0PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M0PE_SHIFT))
+
+/*! @brief Set the M0PE field to a new value. */
+#define MPU_WR_RGDAAC_M0PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0PE_MASK, MPU_RGDAAC_M0PE(value)))
+#define MPU_BWR_RGDAAC_M0PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M0PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1UM field. */
+#define MPU_RD_RGDAAC_M1UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1UM_MASK) >> MPU_RGDAAC_M1UM_SHIFT)
+#define MPU_BRD_RGDAAC_M1UM(base, index) (MPU_RD_RGDAAC_M1UM(base, index))
+
+/*! @brief Set the M1UM field to a new value. */
+#define MPU_WR_RGDAAC_M1UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1UM_MASK, MPU_RGDAAC_M1UM(value)))
+#define MPU_BWR_RGDAAC_M1UM(base, index, value) (MPU_WR_RGDAAC_M1UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1SM field. */
+#define MPU_RD_RGDAAC_M1SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1SM_MASK) >> MPU_RGDAAC_M1SM_SHIFT)
+#define MPU_BRD_RGDAAC_M1SM(base, index) (MPU_RD_RGDAAC_M1SM(base, index))
+
+/*! @brief Set the M1SM field to a new value. */
+#define MPU_WR_RGDAAC_M1SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1SM_MASK, MPU_RGDAAC_M1SM(value)))
+#define MPU_BWR_RGDAAC_M1SM(base, index, value) (MPU_WR_RGDAAC_M1SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1PE field. */
+#define MPU_RD_RGDAAC_M1PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1PE_MASK) >> MPU_RGDAAC_M1PE_SHIFT)
+#define MPU_BRD_RGDAAC_M1PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M1PE_SHIFT))
+
+/*! @brief Set the M1PE field to a new value. */
+#define MPU_WR_RGDAAC_M1PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1PE_MASK, MPU_RGDAAC_M1PE(value)))
+#define MPU_BWR_RGDAAC_M1PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M1PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2UM field. */
+#define MPU_RD_RGDAAC_M2UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2UM_MASK) >> MPU_RGDAAC_M2UM_SHIFT)
+#define MPU_BRD_RGDAAC_M2UM(base, index) (MPU_RD_RGDAAC_M2UM(base, index))
+
+/*! @brief Set the M2UM field to a new value. */
+#define MPU_WR_RGDAAC_M2UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2UM_MASK, MPU_RGDAAC_M2UM(value)))
+#define MPU_BWR_RGDAAC_M2UM(base, index, value) (MPU_WR_RGDAAC_M2UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2SM field. */
+#define MPU_RD_RGDAAC_M2SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2SM_MASK) >> MPU_RGDAAC_M2SM_SHIFT)
+#define MPU_BRD_RGDAAC_M2SM(base, index) (MPU_RD_RGDAAC_M2SM(base, index))
+
+/*! @brief Set the M2SM field to a new value. */
+#define MPU_WR_RGDAAC_M2SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2SM_MASK, MPU_RGDAAC_M2SM(value)))
+#define MPU_BWR_RGDAAC_M2SM(base, index, value) (MPU_WR_RGDAAC_M2SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2PE field. */
+#define MPU_RD_RGDAAC_M2PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2PE_MASK) >> MPU_RGDAAC_M2PE_SHIFT)
+#define MPU_BRD_RGDAAC_M2PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M2PE_SHIFT))
+
+/*! @brief Set the M2PE field to a new value. */
+#define MPU_WR_RGDAAC_M2PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2PE_MASK, MPU_RGDAAC_M2PE(value)))
+#define MPU_BWR_RGDAAC_M2PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M2PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in user mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0b000 - An attempted access of that mode may be terminated with an access
+ *     error (if not allowed by another descriptor) and the access not performed.
+ * - 0b001 - Allows the given access type to occur
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3UM field. */
+#define MPU_RD_RGDAAC_M3UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3UM_MASK) >> MPU_RGDAAC_M3UM_SHIFT)
+#define MPU_BRD_RGDAAC_M3UM(base, index) (MPU_RD_RGDAAC_M3UM(base, index))
+
+/*! @brief Set the M3UM field to a new value. */
+#define MPU_WR_RGDAAC_M3UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3UM_MASK, MPU_RGDAAC_M3UM(value)))
+#define MPU_BWR_RGDAAC_M3UM(base, index, value) (MPU_WR_RGDAAC_M3UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 0b00 - r/w/x; read, write and execute allowed
+ * - 0b01 - r/x; read and execute allowed, but no write
+ * - 0b10 - r/w; read and write allowed, but no execute
+ * - 0b11 - Same as User mode defined in M3UM
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3SM field. */
+#define MPU_RD_RGDAAC_M3SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3SM_MASK) >> MPU_RGDAAC_M3SM_SHIFT)
+#define MPU_BRD_RGDAAC_M3SM(base, index) (MPU_RD_RGDAAC_M3SM(base, index))
+
+/*! @brief Set the M3SM field to a new value. */
+#define MPU_WR_RGDAAC_M3SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3SM_MASK, MPU_RGDAAC_M3SM(value)))
+#define MPU_BWR_RGDAAC_M3SM(base, index, value) (MPU_WR_RGDAAC_M3SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the process identifier in the evaluation
+ * - 0b1 - Include the process identifier and mask (RGDn.RGDAAC) in the region
+ *     hit evaluation
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3PE field. */
+#define MPU_RD_RGDAAC_M3PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3PE_MASK) >> MPU_RGDAAC_M3PE_SHIFT)
+#define MPU_BRD_RGDAAC_M3PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M3PE_SHIFT))
+
+/*! @brief Set the M3PE field to a new value. */
+#define MPU_WR_RGDAAC_M3PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3PE_MASK, MPU_RGDAAC_M3PE(value)))
+#define MPU_BWR_RGDAAC_M3PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M3PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 4 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M4WE field. */
+#define MPU_RD_RGDAAC_M4WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M4WE_MASK) >> MPU_RGDAAC_M4WE_SHIFT)
+#define MPU_BRD_RGDAAC_M4WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4WE_SHIFT))
+
+/*! @brief Set the M4WE field to a new value. */
+#define MPU_WR_RGDAAC_M4WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M4WE_MASK, MPU_RGDAAC_M4WE(value)))
+#define MPU_BWR_RGDAAC_M4WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 4 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M4RE field. */
+#define MPU_RD_RGDAAC_M4RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M4RE_MASK) >> MPU_RGDAAC_M4RE_SHIFT)
+#define MPU_BRD_RGDAAC_M4RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4RE_SHIFT))
+
+/*! @brief Set the M4RE field to a new value. */
+#define MPU_WR_RGDAAC_M4RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M4RE_MASK, MPU_RGDAAC_M4RE(value)))
+#define MPU_BWR_RGDAAC_M4RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 5 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M5WE field. */
+#define MPU_RD_RGDAAC_M5WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M5WE_MASK) >> MPU_RGDAAC_M5WE_SHIFT)
+#define MPU_BRD_RGDAAC_M5WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5WE_SHIFT))
+
+/*! @brief Set the M5WE field to a new value. */
+#define MPU_WR_RGDAAC_M5WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M5WE_MASK, MPU_RGDAAC_M5WE(value)))
+#define MPU_BWR_RGDAAC_M5WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 5 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M5RE field. */
+#define MPU_RD_RGDAAC_M5RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M5RE_MASK) >> MPU_RGDAAC_M5RE_SHIFT)
+#define MPU_BRD_RGDAAC_M5RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5RE_SHIFT))
+
+/*! @brief Set the M5RE field to a new value. */
+#define MPU_WR_RGDAAC_M5RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M5RE_MASK, MPU_RGDAAC_M5RE(value)))
+#define MPU_BWR_RGDAAC_M5RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 6 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M6WE field. */
+#define MPU_RD_RGDAAC_M6WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M6WE_MASK) >> MPU_RGDAAC_M6WE_SHIFT)
+#define MPU_BRD_RGDAAC_M6WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6WE_SHIFT))
+
+/*! @brief Set the M6WE field to a new value. */
+#define MPU_WR_RGDAAC_M6WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M6WE_MASK, MPU_RGDAAC_M6WE(value)))
+#define MPU_BWR_RGDAAC_M6WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 6 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M6RE field. */
+#define MPU_RD_RGDAAC_M6RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M6RE_MASK) >> MPU_RGDAAC_M6RE_SHIFT)
+#define MPU_BRD_RGDAAC_M6RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6RE_SHIFT))
+
+/*! @brief Set the M6RE field to a new value. */
+#define MPU_WR_RGDAAC_M6RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M6RE_MASK, MPU_RGDAAC_M6RE(value)))
+#define MPU_BWR_RGDAAC_M6RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 7 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M7WE field. */
+#define MPU_RD_RGDAAC_M7WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M7WE_MASK) >> MPU_RGDAAC_M7WE_SHIFT)
+#define MPU_BRD_RGDAAC_M7WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7WE_SHIFT))
+
+/*! @brief Set the M7WE field to a new value. */
+#define MPU_WR_RGDAAC_M7WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M7WE_MASK, MPU_RGDAAC_M7WE(value)))
+#define MPU_BWR_RGDAAC_M7WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 7 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M7RE field. */
+#define MPU_RD_RGDAAC_M7RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M7RE_MASK) >> MPU_RGDAAC_M7RE_SHIFT)
+#define MPU_BRD_RGDAAC_M7RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7RE_SHIFT))
+
+/*! @brief Set the M7RE field to a new value. */
+#define MPU_WR_RGDAAC_M7RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M7RE_MASK, MPU_RGDAAC_M7RE(value)))
+#define MPU_BWR_RGDAAC_M7RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7RE_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 NV
+ *
+ * Flash configuration field
+ *
+ * Registers defined in this header file:
+ * - NV_BACKKEY3 - Backdoor Comparison Key 3.
+ * - NV_BACKKEY2 - Backdoor Comparison Key 2.
+ * - NV_BACKKEY1 - Backdoor Comparison Key 1.
+ * - NV_BACKKEY0 - Backdoor Comparison Key 0.
+ * - NV_BACKKEY7 - Backdoor Comparison Key 7.
+ * - NV_BACKKEY6 - Backdoor Comparison Key 6.
+ * - NV_BACKKEY5 - Backdoor Comparison Key 5.
+ * - NV_BACKKEY4 - Backdoor Comparison Key 4.
+ * - NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ * - NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ * - NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ * - NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ * - NV_FSEC - Non-volatile Flash Security Register
+ * - NV_FOPT - Non-volatile Flash Option Register
+ * - NV_FEPROT - Non-volatile EERAM Protection Register
+ * - NV_FDPROT - Non-volatile D-Flash Protection Register
+ */
+
+#define NV_INSTANCE_COUNT (1U) /*!< Number of instances of the NV module. */
+#define FTFE_FlashConfig_IDX (0U) /*!< Instance number for FTFE_FlashConfig. */
+
+/*******************************************************************************
+ * NV_BACKKEY3 - Backdoor Comparison Key 3.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY3 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY3(base)     (NV_BACKKEY3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY2 - Backdoor Comparison Key 2.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY2 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY2(base)     (NV_BACKKEY2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY1 - Backdoor Comparison Key 1.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY1 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY1(base)     (NV_BACKKEY1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY0 - Backdoor Comparison Key 0.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY0 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY0(base)     (NV_BACKKEY0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY7 - Backdoor Comparison Key 7.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY7 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY7(base)     (NV_BACKKEY7_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY6 - Backdoor Comparison Key 6.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY6 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY6(base)     (NV_BACKKEY6_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY5 - Backdoor Comparison Key 5.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY5 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY5(base)     (NV_BACKKEY5_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY4 - Backdoor Comparison Key 4.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY4 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY4(base)     (NV_BACKKEY4_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT3 register
+ */
+/*@{*/
+#define NV_RD_FPROT3(base)       (NV_FPROT3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT2 register
+ */
+/*@{*/
+#define NV_RD_FPROT2(base)       (NV_FPROT2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT1 register
+ */
+/*@{*/
+#define NV_RD_FPROT1(base)       (NV_FPROT1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT0 register
+ */
+/*@{*/
+#define NV_RD_FPROT0(base)       (NV_FPROT0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FSEC - Non-volatile Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FSEC - Non-volatile Flash Security Register (RO)
+ *
+ * Reset value: 0xFFU
+ *
+ * Allows the user to customize the operation of the MCU at boot time
+ */
+/*!
+ * @name Constants and macros for entire NV_FSEC register
+ */
+/*@{*/
+#define NV_RD_FSEC(base)         (NV_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FSEC bitfields
+ */
+
+/*!
+ * @name Register NV_FSEC, field SEC[1:0] (RO)
+ *
+ * Values:
+ * - 0b10 - MCU security status is unsecure
+ * - 0b11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_SEC field. */
+#define NV_RD_FSEC_SEC(base) ((NV_FSEC_REG(base) & NV_FSEC_SEC_MASK) >> NV_FSEC_SEC_SHIFT)
+#define NV_BRD_FSEC_SEC(base) (NV_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field FSLACC[3:2] (RO)
+ *
+ * Values:
+ * - 0b10 - Freescale factory access denied
+ * - 0b11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_FSLACC field. */
+#define NV_RD_FSEC_FSLACC(base) ((NV_FSEC_REG(base) & NV_FSEC_FSLACC_MASK) >> NV_FSEC_FSLACC_SHIFT)
+#define NV_BRD_FSEC_FSLACC(base) (NV_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field MEEN[5:4] (RO)
+ *
+ * Values:
+ * - 0b10 - Mass erase is disabled
+ * - 0b11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_MEEN field. */
+#define NV_RD_FSEC_MEEN(base) ((NV_FSEC_REG(base) & NV_FSEC_MEEN_MASK) >> NV_FSEC_MEEN_SHIFT)
+#define NV_BRD_FSEC_MEEN(base) (NV_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field KEYEN[7:6] (RO)
+ *
+ * Values:
+ * - 0b10 - Backdoor key access enabled
+ * - 0b11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_KEYEN field. */
+#define NV_RD_FSEC_KEYEN(base) ((NV_FSEC_REG(base) & NV_FSEC_KEYEN_MASK) >> NV_FSEC_KEYEN_SHIFT)
+#define NV_BRD_FSEC_KEYEN(base) (NV_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FOPT - Non-volatile Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FOPT - Non-volatile Flash Option Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FOPT register
+ */
+/*@{*/
+#define NV_RD_FOPT(base)         (NV_FOPT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FOPT bitfields
+ */
+
+/*!
+ * @name Register NV_FOPT, field LPBOOT[0] (RO)
+ *
+ * Values:
+ * - 0b0 - Low-power boot
+ * - 0b1 - Normal boot
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_LPBOOT field. */
+#define NV_RD_FOPT_LPBOOT(base) ((NV_FOPT_REG(base) & NV_FOPT_LPBOOT_MASK) >> NV_FOPT_LPBOOT_SHIFT)
+#define NV_BRD_FOPT_LPBOOT(base) (BITBAND_ACCESS8(&NV_FOPT_REG(base), NV_FOPT_LPBOOT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register NV_FOPT, field EZPORT_DIS[1] (RO)
+ *
+ * Values:
+ * - 0b0 - EzPort operation is disabled
+ * - 0b1 - EzPort operation is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_EZPORT_DIS field. */
+#define NV_RD_FOPT_EZPORT_DIS(base) ((NV_FOPT_REG(base) & NV_FOPT_EZPORT_DIS_MASK) >> NV_FOPT_EZPORT_DIS_SHIFT)
+#define NV_BRD_FOPT_EZPORT_DIS(base) (BITBAND_ACCESS8(&NV_FOPT_REG(base), NV_FOPT_EZPORT_DIS_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FEPROT - Non-volatile EERAM Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FEPROT - Non-volatile EERAM Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FEPROT register
+ */
+/*@{*/
+#define NV_RD_FEPROT(base)       (NV_FEPROT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FDPROT - Non-volatile D-Flash Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FDPROT - Non-volatile D-Flash Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FDPROT register
+ */
+/*@{*/
+#define NV_RD_FDPROT(base)       (NV_FDPROT_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 OSC
+ *
+ * Oscillator
+ *
+ * Registers defined in this header file:
+ * - OSC_CR - OSC Control Register
+ */
+
+#define OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */
+#define OSC_IDX (0U) /*!< Instance number for OSC. */
+
+/*******************************************************************************
+ * OSC_CR - OSC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief OSC_CR - OSC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * After OSC is enabled and starts generating the clocks, the configurations
+ * such as low power and frequency range, must not be changed.
+ */
+/*!
+ * @name Constants and macros for entire OSC_CR register
+ */
+/*@{*/
+#define OSC_RD_CR(base)          (OSC_CR_REG(base))
+#define OSC_WR_CR(base, value)   (OSC_CR_REG(base) = (value))
+#define OSC_RMW_CR(base, mask, value) (OSC_WR_CR(base, (OSC_RD_CR(base) & ~(mask)) | (value)))
+#define OSC_SET_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) |  (value)))
+#define OSC_CLR_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) & ~(value)))
+#define OSC_TOG_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual OSC_CR bitfields
+ */
+
+/*!
+ * @name Register OSC_CR, field SC16P[0] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 16 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC16P field. */
+#define OSC_RD_CR_SC16P(base) ((OSC_CR_REG(base) & OSC_CR_SC16P_MASK) >> OSC_CR_SC16P_SHIFT)
+#define OSC_BRD_CR_SC16P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT))
+
+/*! @brief Set the SC16P field to a new value. */
+#define OSC_WR_CR_SC16P(base, value) (OSC_RMW_CR(base, OSC_CR_SC16P_MASK, OSC_CR_SC16P(value)))
+#define OSC_BWR_CR_SC16P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC8P[1] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 8 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC8P field. */
+#define OSC_RD_CR_SC8P(base) ((OSC_CR_REG(base) & OSC_CR_SC8P_MASK) >> OSC_CR_SC8P_SHIFT)
+#define OSC_BRD_CR_SC8P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT))
+
+/*! @brief Set the SC8P field to a new value. */
+#define OSC_WR_CR_SC8P(base, value) (OSC_RMW_CR(base, OSC_CR_SC8P_MASK, OSC_CR_SC8P(value)))
+#define OSC_BWR_CR_SC8P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC4P[2] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 4 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC4P field. */
+#define OSC_RD_CR_SC4P(base) ((OSC_CR_REG(base) & OSC_CR_SC4P_MASK) >> OSC_CR_SC4P_SHIFT)
+#define OSC_BRD_CR_SC4P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT))
+
+/*! @brief Set the SC4P field to a new value. */
+#define OSC_WR_CR_SC4P(base, value) (OSC_RMW_CR(base, OSC_CR_SC4P_MASK, OSC_CR_SC4P(value)))
+#define OSC_BWR_CR_SC4P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC2P[3] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 2 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC2P field. */
+#define OSC_RD_CR_SC2P(base) ((OSC_CR_REG(base) & OSC_CR_SC2P_MASK) >> OSC_CR_SC2P_SHIFT)
+#define OSC_BRD_CR_SC2P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT))
+
+/*! @brief Set the SC2P field to a new value. */
+#define OSC_WR_CR_SC2P(base, value) (OSC_RMW_CR(base, OSC_CR_SC2P_MASK, OSC_CR_SC2P(value)))
+#define OSC_BWR_CR_SC2P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field EREFSTEN[5] (RW)
+ *
+ * Controls whether or not the external reference clock (OSCERCLK) remains
+ * enabled when MCU enters Stop mode.
+ *
+ * Values:
+ * - 0b0 - External reference clock is disabled in Stop mode.
+ * - 0b1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
+ *     before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_EREFSTEN field. */
+#define OSC_RD_CR_EREFSTEN(base) ((OSC_CR_REG(base) & OSC_CR_EREFSTEN_MASK) >> OSC_CR_EREFSTEN_SHIFT)
+#define OSC_BRD_CR_EREFSTEN(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT))
+
+/*! @brief Set the EREFSTEN field to a new value. */
+#define OSC_WR_CR_EREFSTEN(base, value) (OSC_RMW_CR(base, OSC_CR_EREFSTEN_MASK, OSC_CR_EREFSTEN(value)))
+#define OSC_BWR_CR_EREFSTEN(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field ERCLKEN[7] (RW)
+ *
+ * Enables external reference clock (OSCERCLK).
+ *
+ * Values:
+ * - 0b0 - External reference clock is inactive.
+ * - 0b1 - External reference clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_ERCLKEN field. */
+#define OSC_RD_CR_ERCLKEN(base) ((OSC_CR_REG(base) & OSC_CR_ERCLKEN_MASK) >> OSC_CR_ERCLKEN_SHIFT)
+#define OSC_BRD_CR_ERCLKEN(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT))
+
+/*! @brief Set the ERCLKEN field to a new value. */
+#define OSC_WR_CR_ERCLKEN(base, value) (OSC_RMW_CR(base, OSC_CR_ERCLKEN_MASK, OSC_CR_ERCLKEN(value)))
+#define OSC_BWR_CR_ERCLKEN(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PDB
+ *
+ * Programmable Delay Block
+ *
+ * Registers defined in this header file:
+ * - PDB_SC - Status and Control register
+ * - PDB_MOD - Modulus register
+ * - PDB_CNT - Counter register
+ * - PDB_IDLY - Interrupt Delay register
+ * - PDB_C1 - Channel n Control register 1
+ * - PDB_S - Channel n Status register
+ * - PDB_DLY - Channel n Delay 0 register
+ * - PDB_INTC - DAC Interval Trigger n Control register
+ * - PDB_INT - DAC Interval n register
+ * - PDB_POEN - Pulse-Out n Enable register
+ * - PDB_PODLY - Pulse-Out n Delay register
+ */
+
+#define PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */
+#define PDB0_IDX (0U) /*!< Instance number for PDB0. */
+
+/*******************************************************************************
+ * PDB_SC - Status and Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_SC - Status and Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_SC register
+ */
+/*@{*/
+#define PDB_RD_SC(base)          (PDB_SC_REG(base))
+#define PDB_WR_SC(base, value)   (PDB_SC_REG(base) = (value))
+#define PDB_RMW_SC(base, mask, value) (PDB_WR_SC(base, (PDB_RD_SC(base) & ~(mask)) | (value)))
+#define PDB_SET_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) |  (value)))
+#define PDB_CLR_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) & ~(value)))
+#define PDB_TOG_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_SC bitfields
+ */
+
+/*!
+ * @name Register PDB_SC, field LDOK[0] (RW)
+ *
+ * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
+ * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
+ * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
+ * written to the LDOK field, the values in the buffers of above registers are
+ * not effective and the buffers cannot be written until the values in buffers are
+ * loaded into their internal registers. LDOK can be written only when PDBEN is
+ * set or it can be written at the same time with PDBEN being written to 1. It is
+ * automatically cleared when the values in buffers are loaded into the internal
+ * registers or the PDBEN is cleared. Writing 0 to it has no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_LDOK field. */
+#define PDB_RD_SC_LDOK(base) ((PDB_SC_REG(base) & PDB_SC_LDOK_MASK) >> PDB_SC_LDOK_SHIFT)
+#define PDB_BRD_SC_LDOK(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_LDOK_SHIFT))
+
+/*! @brief Set the LDOK field to a new value. */
+#define PDB_WR_SC_LDOK(base, value) (PDB_RMW_SC(base, PDB_SC_LDOK_MASK, PDB_SC_LDOK(value)))
+#define PDB_BWR_SC_LDOK(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_LDOK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field CONT[1] (RW)
+ *
+ * Enables the PDB operation in Continuous mode.
+ *
+ * Values:
+ * - 0b0 - PDB operation in One-Shot mode
+ * - 0b1 - PDB operation in Continuous mode
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_CONT field. */
+#define PDB_RD_SC_CONT(base) ((PDB_SC_REG(base) & PDB_SC_CONT_MASK) >> PDB_SC_CONT_SHIFT)
+#define PDB_BRD_SC_CONT(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_CONT_SHIFT))
+
+/*! @brief Set the CONT field to a new value. */
+#define PDB_WR_SC_CONT(base, value) (PDB_RMW_SC(base, PDB_SC_CONT_MASK, PDB_SC_CONT(value)))
+#define PDB_BWR_SC_CONT(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_CONT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field MULT[3:2] (RW)
+ *
+ * Selects the multiplication factor of the prescaler divider for the counter
+ * clock.
+ *
+ * Values:
+ * - 0b00 - Multiplication factor is 1.
+ * - 0b01 - Multiplication factor is 10.
+ * - 0b10 - Multiplication factor is 20.
+ * - 0b11 - Multiplication factor is 40.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_MULT field. */
+#define PDB_RD_SC_MULT(base) ((PDB_SC_REG(base) & PDB_SC_MULT_MASK) >> PDB_SC_MULT_SHIFT)
+#define PDB_BRD_SC_MULT(base) (PDB_RD_SC_MULT(base))
+
+/*! @brief Set the MULT field to a new value. */
+#define PDB_WR_SC_MULT(base, value) (PDB_RMW_SC(base, PDB_SC_MULT_MASK, PDB_SC_MULT(value)))
+#define PDB_BWR_SC_MULT(base, value) (PDB_WR_SC_MULT(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBIE[5] (RW)
+ *
+ * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
+ * generates a PDB interrupt.
+ *
+ * Values:
+ * - 0b0 - PDB interrupt disabled.
+ * - 0b1 - PDB interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBIE field. */
+#define PDB_RD_SC_PDBIE(base) ((PDB_SC_REG(base) & PDB_SC_PDBIE_MASK) >> PDB_SC_PDBIE_SHIFT)
+#define PDB_BRD_SC_PDBIE(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIE_SHIFT))
+
+/*! @brief Set the PDBIE field to a new value. */
+#define PDB_WR_SC_PDBIE(base, value) (PDB_RMW_SC(base, PDB_SC_PDBIE_MASK, PDB_SC_PDBIE(value)))
+#define PDB_BWR_SC_PDBIE(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBIF[6] (RW)
+ *
+ * This field is set when the counter value is equal to the IDLY register.
+ * Writing zero clears this field.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBIF field. */
+#define PDB_RD_SC_PDBIF(base) ((PDB_SC_REG(base) & PDB_SC_PDBIF_MASK) >> PDB_SC_PDBIF_SHIFT)
+#define PDB_BRD_SC_PDBIF(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIF_SHIFT))
+
+/*! @brief Set the PDBIF field to a new value. */
+#define PDB_WR_SC_PDBIF(base, value) (PDB_RMW_SC(base, PDB_SC_PDBIF_MASK, PDB_SC_PDBIF(value)))
+#define PDB_BWR_SC_PDBIF(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - PDB disabled. Counter is off.
+ * - 0b1 - PDB enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBEN field. */
+#define PDB_RD_SC_PDBEN(base) ((PDB_SC_REG(base) & PDB_SC_PDBEN_MASK) >> PDB_SC_PDBEN_SHIFT)
+#define PDB_BRD_SC_PDBEN(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEN_SHIFT))
+
+/*! @brief Set the PDBEN field to a new value. */
+#define PDB_WR_SC_PDBEN(base, value) (PDB_RMW_SC(base, PDB_SC_PDBEN_MASK, PDB_SC_PDBEN(value)))
+#define PDB_BWR_SC_PDBEN(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field TRGSEL[11:8] (RW)
+ *
+ * Selects the trigger input source for the PDB. The trigger input source can be
+ * internal or external (EXTRG pin), or the software trigger. Refer to chip
+ * configuration details for the actual PDB input trigger connections.
+ *
+ * Values:
+ * - 0b0000 - Trigger-In 0 is selected.
+ * - 0b0001 - Trigger-In 1 is selected.
+ * - 0b0010 - Trigger-In 2 is selected.
+ * - 0b0011 - Trigger-In 3 is selected.
+ * - 0b0100 - Trigger-In 4 is selected.
+ * - 0b0101 - Trigger-In 5 is selected.
+ * - 0b0110 - Trigger-In 6 is selected.
+ * - 0b0111 - Trigger-In 7 is selected.
+ * - 0b1000 - Trigger-In 8 is selected.
+ * - 0b1001 - Trigger-In 9 is selected.
+ * - 0b1010 - Trigger-In 10 is selected.
+ * - 0b1011 - Trigger-In 11 is selected.
+ * - 0b1100 - Trigger-In 12 is selected.
+ * - 0b1101 - Trigger-In 13 is selected.
+ * - 0b1110 - Trigger-In 14 is selected.
+ * - 0b1111 - Software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_TRGSEL field. */
+#define PDB_RD_SC_TRGSEL(base) ((PDB_SC_REG(base) & PDB_SC_TRGSEL_MASK) >> PDB_SC_TRGSEL_SHIFT)
+#define PDB_BRD_SC_TRGSEL(base) (PDB_RD_SC_TRGSEL(base))
+
+/*! @brief Set the TRGSEL field to a new value. */
+#define PDB_WR_SC_TRGSEL(base, value) (PDB_RMW_SC(base, PDB_SC_TRGSEL_MASK, PDB_SC_TRGSEL(value)))
+#define PDB_BWR_SC_TRGSEL(base, value) (PDB_WR_SC_TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PRESCALER[14:12] (RW)
+ *
+ * Values:
+ * - 0b000 - Counting uses the peripheral clock divided by multiplication factor
+ *     selected by MULT.
+ * - 0b001 - Counting uses the peripheral clock divided by twice of the
+ *     multiplication factor selected by MULT.
+ * - 0b010 - Counting uses the peripheral clock divided by four times of the
+ *     multiplication factor selected by MULT.
+ * - 0b011 - Counting uses the peripheral clock divided by eight times of the
+ *     multiplication factor selected by MULT.
+ * - 0b100 - Counting uses the peripheral clock divided by 16 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b101 - Counting uses the peripheral clock divided by 32 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b110 - Counting uses the peripheral clock divided by 64 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b111 - Counting uses the peripheral clock divided by 128 times of the
+ *     multiplication factor selected by MULT.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PRESCALER field. */
+#define PDB_RD_SC_PRESCALER(base) ((PDB_SC_REG(base) & PDB_SC_PRESCALER_MASK) >> PDB_SC_PRESCALER_SHIFT)
+#define PDB_BRD_SC_PRESCALER(base) (PDB_RD_SC_PRESCALER(base))
+
+/*! @brief Set the PRESCALER field to a new value. */
+#define PDB_WR_SC_PRESCALER(base, value) (PDB_RMW_SC(base, PDB_SC_PRESCALER_MASK, PDB_SC_PRESCALER(value)))
+#define PDB_BWR_SC_PRESCALER(base, value) (PDB_WR_SC_PRESCALER(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field DMAEN[15] (RW)
+ *
+ * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
+ * interrupt.
+ *
+ * Values:
+ * - 0b0 - DMA disabled.
+ * - 0b1 - DMA enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_DMAEN field. */
+#define PDB_RD_SC_DMAEN(base) ((PDB_SC_REG(base) & PDB_SC_DMAEN_MASK) >> PDB_SC_DMAEN_SHIFT)
+#define PDB_BRD_SC_DMAEN(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define PDB_WR_SC_DMAEN(base, value) (PDB_RMW_SC(base, PDB_SC_DMAEN_MASK, PDB_SC_DMAEN(value)))
+#define PDB_BWR_SC_DMAEN(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field SWTRIG[16] (WORZ)
+ *
+ * When PDB is enabled and the software trigger is selected as the trigger input
+ * source, writing 1 to this field resets and restarts the counter. Writing 0 to
+ * this field has no effect. Reading this field results 0.
+ */
+/*@{*/
+/*! @brief Set the SWTRIG field to a new value. */
+#define PDB_WR_SC_SWTRIG(base, value) (PDB_RMW_SC(base, PDB_SC_SWTRIG_MASK, PDB_SC_SWTRIG(value)))
+#define PDB_BWR_SC_SWTRIG(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_SWTRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBEIE[17] (RW)
+ *
+ * Enables the PDB sequence error interrupt. When this field is set, any of the
+ * PDB channel sequence error flags generates a PDB sequence error interrupt.
+ *
+ * Values:
+ * - 0b0 - PDB sequence error interrupt disabled.
+ * - 0b1 - PDB sequence error interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBEIE field. */
+#define PDB_RD_SC_PDBEIE(base) ((PDB_SC_REG(base) & PDB_SC_PDBEIE_MASK) >> PDB_SC_PDBEIE_SHIFT)
+#define PDB_BRD_SC_PDBEIE(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEIE_SHIFT))
+
+/*! @brief Set the PDBEIE field to a new value. */
+#define PDB_WR_SC_PDBEIE(base, value) (PDB_RMW_SC(base, PDB_SC_PDBEIE_MASK, PDB_SC_PDBEIE(value)))
+#define PDB_BWR_SC_PDBEIE(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field LDMOD[19:18] (RW)
+ *
+ * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
+ * after 1 is written to LDOK.
+ *
+ * Values:
+ * - 0b00 - The internal registers are loaded with the values from their buffers
+ *     immediately after 1 is written to LDOK.
+ * - 0b01 - The internal registers are loaded with the values from their buffers
+ *     when the PDB counter reaches the MOD register value after 1 is written to
+ *     LDOK.
+ * - 0b10 - The internal registers are loaded with the values from their buffers
+ *     when a trigger input event is detected after 1 is written to LDOK.
+ * - 0b11 - The internal registers are loaded with the values from their buffers
+ *     when either the PDB counter reaches the MOD register value or a trigger
+ *     input event is detected, after 1 is written to LDOK.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_LDMOD field. */
+#define PDB_RD_SC_LDMOD(base) ((PDB_SC_REG(base) & PDB_SC_LDMOD_MASK) >> PDB_SC_LDMOD_SHIFT)
+#define PDB_BRD_SC_LDMOD(base) (PDB_RD_SC_LDMOD(base))
+
+/*! @brief Set the LDMOD field to a new value. */
+#define PDB_WR_SC_LDMOD(base, value) (PDB_RMW_SC(base, PDB_SC_LDMOD_MASK, PDB_SC_LDMOD(value)))
+#define PDB_BWR_SC_LDMOD(base, value) (PDB_WR_SC_LDMOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_MOD - Modulus register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_MOD - Modulus register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+/*!
+ * @name Constants and macros for entire PDB_MOD register
+ */
+/*@{*/
+#define PDB_RD_MOD(base)         (PDB_MOD_REG(base))
+#define PDB_WR_MOD(base, value)  (PDB_MOD_REG(base) = (value))
+#define PDB_RMW_MOD(base, mask, value) (PDB_WR_MOD(base, (PDB_RD_MOD(base) & ~(mask)) | (value)))
+#define PDB_SET_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) |  (value)))
+#define PDB_CLR_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) & ~(value)))
+#define PDB_TOG_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_MOD bitfields
+ */
+
+/*!
+ * @name Register PDB_MOD, field MOD[15:0] (RW)
+ *
+ * Specifies the period of the counter. When the counter reaches this value, it
+ * will be reset back to zero. If the PDB is in Continuous mode, the count begins
+ * anew. Reading this field returns the value of the internal register that is
+ * effective for the current cycle of PDB.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_MOD_MOD field. */
+#define PDB_RD_MOD_MOD(base) ((PDB_MOD_REG(base) & PDB_MOD_MOD_MASK) >> PDB_MOD_MOD_SHIFT)
+#define PDB_BRD_MOD_MOD(base) (PDB_RD_MOD_MOD(base))
+
+/*! @brief Set the MOD field to a new value. */
+#define PDB_WR_MOD_MOD(base, value) (PDB_RMW_MOD(base, PDB_MOD_MOD_MASK, PDB_MOD_MOD(value)))
+#define PDB_BWR_MOD_MOD(base, value) (PDB_WR_MOD_MOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_CNT - Counter register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_CNT - Counter register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_CNT register
+ */
+/*@{*/
+#define PDB_RD_CNT(base)         (PDB_CNT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_CNT bitfields
+ */
+
+/*!
+ * @name Register PDB_CNT, field CNT[15:0] (RO)
+ *
+ * Contains the current value of the counter.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_CNT_CNT field. */
+#define PDB_RD_CNT_CNT(base) ((PDB_CNT_REG(base) & PDB_CNT_CNT_MASK) >> PDB_CNT_CNT_SHIFT)
+#define PDB_BRD_CNT_CNT(base) (PDB_RD_CNT_CNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_IDLY - Interrupt Delay register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_IDLY - Interrupt Delay register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+/*!
+ * @name Constants and macros for entire PDB_IDLY register
+ */
+/*@{*/
+#define PDB_RD_IDLY(base)        (PDB_IDLY_REG(base))
+#define PDB_WR_IDLY(base, value) (PDB_IDLY_REG(base) = (value))
+#define PDB_RMW_IDLY(base, mask, value) (PDB_WR_IDLY(base, (PDB_RD_IDLY(base) & ~(mask)) | (value)))
+#define PDB_SET_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) |  (value)))
+#define PDB_CLR_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) & ~(value)))
+#define PDB_TOG_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_IDLY bitfields
+ */
+
+/*!
+ * @name Register PDB_IDLY, field IDLY[15:0] (RW)
+ *
+ * Specifies the delay value to schedule the PDB interrupt. It can be used to
+ * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
+ * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
+ * this field returns the value of internal register that is effective for the
+ * current cycle of the PDB.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_IDLY_IDLY field. */
+#define PDB_RD_IDLY_IDLY(base) ((PDB_IDLY_REG(base) & PDB_IDLY_IDLY_MASK) >> PDB_IDLY_IDLY_SHIFT)
+#define PDB_BRD_IDLY_IDLY(base) (PDB_RD_IDLY_IDLY(base))
+
+/*! @brief Set the IDLY field to a new value. */
+#define PDB_WR_IDLY_IDLY(base, value) (PDB_RMW_IDLY(base, PDB_IDLY_IDLY_MASK, PDB_IDLY_IDLY(value)))
+#define PDB_BWR_IDLY_IDLY(base, value) (PDB_WR_IDLY_IDLY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_C1 - Channel n Control register 1
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_C1 - Channel n Control register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PDB channel has one control register, CHnC1. The bits in this register
+ * control the functionality of each PDB channel operation.
+ */
+/*!
+ * @name Constants and macros for entire PDB_C1 register
+ */
+/*@{*/
+#define PDB_RD_C1(base, index)   (PDB_C1_REG(base, index))
+#define PDB_WR_C1(base, index, value) (PDB_C1_REG(base, index) = (value))
+#define PDB_RMW_C1(base, index, mask, value) (PDB_WR_C1(base, index, (PDB_RD_C1(base, index) & ~(mask)) | (value)))
+#define PDB_SET_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) |  (value)))
+#define PDB_CLR_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) & ~(value)))
+#define PDB_TOG_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_C1 bitfields
+ */
+
+/*!
+ * @name Register PDB_C1, field EN[7:0] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
+ * bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger disabled.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_EN field. */
+#define PDB_RD_C1_EN(base, index) ((PDB_C1_REG(base, index) & PDB_C1_EN_MASK) >> PDB_C1_EN_SHIFT)
+#define PDB_BRD_C1_EN(base, index) (PDB_RD_C1_EN(base, index))
+
+/*! @brief Set the EN field to a new value. */
+#define PDB_WR_C1_EN(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_EN_MASK, PDB_C1_EN(value)))
+#define PDB_BWR_C1_EN(base, index, value) (PDB_WR_C1_EN(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_C1, field TOS[15:8] (RW)
+ *
+ * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
+ * implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger is in bypassed mode.
+ *     The pre-trigger asserts one peripheral clock cycle after a rising edge is
+ *     detected on selected trigger input source or software trigger is selected
+ *     and SWTRIG is written with 1.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger asserts when the
+ *     counter reaches the channel delay register and one peripheral clock cycle after
+ *     a rising edge is detected on selected trigger input source or software
+ *     trigger is selected and SETRIG is written with 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_TOS field. */
+#define PDB_RD_C1_TOS(base, index) ((PDB_C1_REG(base, index) & PDB_C1_TOS_MASK) >> PDB_C1_TOS_SHIFT)
+#define PDB_BRD_C1_TOS(base, index) (PDB_RD_C1_TOS(base, index))
+
+/*! @brief Set the TOS field to a new value. */
+#define PDB_WR_C1_TOS(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_TOS_MASK, PDB_C1_TOS(value)))
+#define PDB_BWR_C1_TOS(base, index, value) (PDB_WR_C1_TOS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_C1, field BB[23:16] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
+ * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
+ * enables the ADC conversions complete to trigger the next PDB channel
+ * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
+ * set of configuration and results registers. Application code must only enable
+ * the back-to-back operation of the PDB pre-triggers at the leading of the
+ * back-to-back connection chain.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger back-to-back operation
+ *     disabled.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger back-to-back operation
+ *     enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_BB field. */
+#define PDB_RD_C1_BB(base, index) ((PDB_C1_REG(base, index) & PDB_C1_BB_MASK) >> PDB_C1_BB_SHIFT)
+#define PDB_BRD_C1_BB(base, index) (PDB_RD_C1_BB(base, index))
+
+/*! @brief Set the BB field to a new value. */
+#define PDB_WR_C1_BB(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_BB_MASK, PDB_C1_BB(value)))
+#define PDB_BWR_C1_BB(base, index, value) (PDB_WR_C1_BB(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_S - Channel n Status register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_S - Channel n Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_S register
+ */
+/*@{*/
+#define PDB_RD_S(base, index)    (PDB_S_REG(base, index))
+#define PDB_WR_S(base, index, value) (PDB_S_REG(base, index) = (value))
+#define PDB_RMW_S(base, index, mask, value) (PDB_WR_S(base, index, (PDB_RD_S(base, index) & ~(mask)) | (value)))
+#define PDB_SET_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) |  (value)))
+#define PDB_CLR_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) & ~(value)))
+#define PDB_TOG_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_S bitfields
+ */
+
+/*!
+ * @name Register PDB_S, field ERR[7:0] (RW)
+ *
+ * Only the lower M bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - Sequence error not detected on PDB channel's corresponding
+ *     pre-trigger.
+ * - 0b00000001 - Sequence error detected on PDB channel's corresponding
+ *     pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from
+ *     PDB channel n. When one conversion, which is triggered by one of the
+ *     pre-triggers from PDB channel n, is in progress, new trigger from PDB
+ *     channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is
+ *     set. Writing 0's to clear the sequence error flags.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_S_ERR field. */
+#define PDB_RD_S_ERR(base, index) ((PDB_S_REG(base, index) & PDB_S_ERR_MASK) >> PDB_S_ERR_SHIFT)
+#define PDB_BRD_S_ERR(base, index) (PDB_RD_S_ERR(base, index))
+
+/*! @brief Set the ERR field to a new value. */
+#define PDB_WR_S_ERR(base, index, value) (PDB_RMW_S(base, index, PDB_S_ERR_MASK, PDB_S_ERR(value)))
+#define PDB_BWR_S_ERR(base, index, value) (PDB_WR_S_ERR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_S, field CF[23:16] (RW)
+ *
+ * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
+ * clear these bits.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_S_CF field. */
+#define PDB_RD_S_CF(base, index) ((PDB_S_REG(base, index) & PDB_S_CF_MASK) >> PDB_S_CF_SHIFT)
+#define PDB_BRD_S_CF(base, index) (PDB_RD_S_CF(base, index))
+
+/*! @brief Set the CF field to a new value. */
+#define PDB_WR_S_CF(base, index, value) (PDB_RMW_S(base, index, PDB_S_CF_MASK, PDB_S_CF(value)))
+#define PDB_BWR_S_CF(base, index, value) (PDB_WR_S_CF(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_DLY - Channel n Delay 0 register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_DLY - Channel n Delay 0 register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_DLY register
+ */
+/*@{*/
+#define PDB_RD_DLY(base, index, index2) (PDB_DLY_REG(base, index, index2))
+#define PDB_WR_DLY(base, index, index2, value) (PDB_DLY_REG(base, index, index2) = (value))
+#define PDB_RMW_DLY(base, index, index2, mask, value) (PDB_WR_DLY(base, index, index2, (PDB_RD_DLY(base, index, index2) & ~(mask)) | (value)))
+#define PDB_SET_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) |  (value)))
+#define PDB_CLR_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) & ~(value)))
+#define PDB_TOG_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_DLY bitfields
+ */
+
+/*!
+ * @name Register PDB_DLY, field DLY[15:0] (RW)
+ *
+ * Specifies the delay value for the channel's corresponding pre-trigger. The
+ * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
+ * the value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_DLY_DLY field. */
+#define PDB_RD_DLY_DLY(base, index, index2) ((PDB_DLY_REG(base, index, index2) & PDB_DLY_DLY_MASK) >> PDB_DLY_DLY_SHIFT)
+#define PDB_BRD_DLY_DLY(base, index, index2) (PDB_RD_DLY_DLY(base, index, index2))
+
+/*! @brief Set the DLY field to a new value. */
+#define PDB_WR_DLY_DLY(base, index, index2, value) (PDB_RMW_DLY(base, index, index2, PDB_DLY_DLY_MASK, PDB_DLY_DLY(value)))
+#define PDB_BWR_DLY_DLY(base, index, index2, value) (PDB_WR_DLY_DLY(base, index, index2, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_INTC - DAC Interval Trigger n Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_INTC - DAC Interval Trigger n Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_INTC register
+ */
+/*@{*/
+#define PDB_RD_INTC(base, index) (PDB_INTC_REG(base, index))
+#define PDB_WR_INTC(base, index, value) (PDB_INTC_REG(base, index) = (value))
+#define PDB_RMW_INTC(base, index, mask, value) (PDB_WR_INTC(base, index, (PDB_RD_INTC(base, index) & ~(mask)) | (value)))
+#define PDB_SET_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) |  (value)))
+#define PDB_CLR_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) & ~(value)))
+#define PDB_TOG_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_INTC bitfields
+ */
+
+/*!
+ * @name Register PDB_INTC, field TOE[0] (RW)
+ *
+ * This bit enables the DAC interval trigger.
+ *
+ * Values:
+ * - 0b0 - DAC interval trigger disabled.
+ * - 0b1 - DAC interval trigger enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INTC_TOE field. */
+#define PDB_RD_INTC_TOE(base, index) ((PDB_INTC_REG(base, index) & PDB_INTC_TOE_MASK) >> PDB_INTC_TOE_SHIFT)
+#define PDB_BRD_INTC_TOE(base, index) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_TOE_SHIFT))
+
+/*! @brief Set the TOE field to a new value. */
+#define PDB_WR_INTC_TOE(base, index, value) (PDB_RMW_INTC(base, index, PDB_INTC_TOE_MASK, PDB_INTC_TOE(value)))
+#define PDB_BWR_INTC_TOE(base, index, value) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_TOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_INTC, field EXT[1] (RW)
+ *
+ * Enables the external trigger for DAC interval counter.
+ *
+ * Values:
+ * - 0b0 - DAC external trigger input disabled. DAC interval counter is reset
+ *     and counting starts when a rising edge is detected on selected trigger input
+ *     source or software trigger is selected and SWTRIG is written with 1.
+ * - 0b1 - DAC external trigger input enabled. DAC interval counter is bypassed
+ *     and DAC external trigger input triggers the DAC interval trigger.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INTC_EXT field. */
+#define PDB_RD_INTC_EXT(base, index) ((PDB_INTC_REG(base, index) & PDB_INTC_EXT_MASK) >> PDB_INTC_EXT_SHIFT)
+#define PDB_BRD_INTC_EXT(base, index) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_EXT_SHIFT))
+
+/*! @brief Set the EXT field to a new value. */
+#define PDB_WR_INTC_EXT(base, index, value) (PDB_RMW_INTC(base, index, PDB_INTC_EXT_MASK, PDB_INTC_EXT(value)))
+#define PDB_BWR_INTC_EXT(base, index, value) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_EXT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_INT - DAC Interval n register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_INT - DAC Interval n register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_INT register
+ */
+/*@{*/
+#define PDB_RD_INT(base, index)  (PDB_INT_REG(base, index))
+#define PDB_WR_INT(base, index, value) (PDB_INT_REG(base, index) = (value))
+#define PDB_RMW_INT(base, index, mask, value) (PDB_WR_INT(base, index, (PDB_RD_INT(base, index) & ~(mask)) | (value)))
+#define PDB_SET_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) |  (value)))
+#define PDB_CLR_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) & ~(value)))
+#define PDB_TOG_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_INT bitfields
+ */
+
+/*!
+ * @name Register PDB_INT, field INT[15:0] (RW)
+ *
+ * Specifies the interval value for DAC interval trigger. DAC interval trigger
+ * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
+ * Reading this field returns the value of internal register that is effective
+ * for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INT_INT field. */
+#define PDB_RD_INT_INT(base, index) ((PDB_INT_REG(base, index) & PDB_INT_INT_MASK) >> PDB_INT_INT_SHIFT)
+#define PDB_BRD_INT_INT(base, index) (PDB_RD_INT_INT(base, index))
+
+/*! @brief Set the INT field to a new value. */
+#define PDB_WR_INT_INT(base, index, value) (PDB_RMW_INT(base, index, PDB_INT_INT_MASK, PDB_INT_INT(value)))
+#define PDB_BWR_INT_INT(base, index, value) (PDB_WR_INT_INT(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_POEN - Pulse-Out n Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_POEN - Pulse-Out n Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_POEN register
+ */
+/*@{*/
+#define PDB_RD_POEN(base)        (PDB_POEN_REG(base))
+#define PDB_WR_POEN(base, value) (PDB_POEN_REG(base) = (value))
+#define PDB_RMW_POEN(base, mask, value) (PDB_WR_POEN(base, (PDB_RD_POEN(base) & ~(mask)) | (value)))
+#define PDB_SET_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) |  (value)))
+#define PDB_CLR_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) & ~(value)))
+#define PDB_TOG_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_POEN bitfields
+ */
+
+/*!
+ * @name Register PDB_POEN, field POEN[7:0] (RW)
+ *
+ * Enables the pulse output. Only lower Y bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB Pulse-Out disabled
+ * - 0b00000001 - PDB Pulse-Out enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_POEN_POEN field. */
+#define PDB_RD_POEN_POEN(base) ((PDB_POEN_REG(base) & PDB_POEN_POEN_MASK) >> PDB_POEN_POEN_SHIFT)
+#define PDB_BRD_POEN_POEN(base) (PDB_RD_POEN_POEN(base))
+
+/*! @brief Set the POEN field to a new value. */
+#define PDB_WR_POEN_POEN(base, value) (PDB_RMW_POEN(base, PDB_POEN_POEN_MASK, PDB_POEN_POEN(value)))
+#define PDB_BWR_POEN_POEN(base, value) (PDB_WR_POEN_POEN(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_PODLY - Pulse-Out n Delay register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_PODLY - Pulse-Out n Delay register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_PODLY register
+ */
+/*@{*/
+#define PDB_RD_PODLY(base, index) (PDB_PODLY_REG(base, index))
+#define PDB_WR_PODLY(base, index, value) (PDB_PODLY_REG(base, index) = (value))
+#define PDB_RMW_PODLY(base, index, mask, value) (PDB_WR_PODLY(base, index, (PDB_RD_PODLY(base, index) & ~(mask)) | (value)))
+#define PDB_SET_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) |  (value)))
+#define PDB_CLR_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) & ~(value)))
+#define PDB_TOG_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_PODLY bitfields
+ */
+
+/*!
+ * @name Register PDB_PODLY, field DLY2[15:0] (RW)
+ *
+ * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
+ * low when the PDB counter is equal to the DLY2. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_PODLY_DLY2 field. */
+#define PDB_RD_PODLY_DLY2(base, index) ((PDB_PODLY_REG(base, index) & PDB_PODLY_DLY2_MASK) >> PDB_PODLY_DLY2_SHIFT)
+#define PDB_BRD_PODLY_DLY2(base, index) (PDB_RD_PODLY_DLY2(base, index))
+
+/*! @brief Set the DLY2 field to a new value. */
+#define PDB_WR_PODLY_DLY2(base, index, value) (PDB_RMW_PODLY(base, index, PDB_PODLY_DLY2_MASK, PDB_PODLY_DLY2(value)))
+#define PDB_BWR_PODLY_DLY2(base, index, value) (PDB_WR_PODLY_DLY2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_PODLY, field DLY1[31:16] (RW)
+ *
+ * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
+ * high when the PDB counter is equal to the DLY1. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_PODLY_DLY1 field. */
+#define PDB_RD_PODLY_DLY1(base, index) ((PDB_PODLY_REG(base, index) & PDB_PODLY_DLY1_MASK) >> PDB_PODLY_DLY1_SHIFT)
+#define PDB_BRD_PODLY_DLY1(base, index) (PDB_RD_PODLY_DLY1(base, index))
+
+/*! @brief Set the DLY1 field to a new value. */
+#define PDB_WR_PODLY_DLY1(base, index, value) (PDB_RMW_PODLY(base, index, PDB_PODLY_DLY1_MASK, PDB_PODLY_DLY1(value)))
+#define PDB_BWR_PODLY_DLY1(base, index, value) (PDB_WR_PODLY_DLY1(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 PIT
+ *
+ * Periodic Interrupt Timer
+ *
+ * Registers defined in this header file:
+ * - PIT_MCR - PIT Module Control Register
+ * - PIT_LDVAL - Timer Load Value Register
+ * - PIT_CVAL - Current Timer Value Register
+ * - PIT_TCTRL - Timer Control Register
+ * - PIT_TFLG - Timer Flag Register
+ */
+
+#define PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
+#define PIT_IDX (0U) /*!< Instance number for PIT. */
+
+/*******************************************************************************
+ * PIT_MCR - PIT Module Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_MCR - PIT Module Control Register (RW)
+ *
+ * Reset value: 0x00000006U
+ *
+ * This register enables or disables the PIT timer clocks and controls the
+ * timers when the PIT enters the Debug mode.
+ */
+/*!
+ * @name Constants and macros for entire PIT_MCR register
+ */
+/*@{*/
+#define PIT_RD_MCR(base)         (PIT_MCR_REG(base))
+#define PIT_WR_MCR(base, value)  (PIT_MCR_REG(base) = (value))
+#define PIT_RMW_MCR(base, mask, value) (PIT_WR_MCR(base, (PIT_RD_MCR(base) & ~(mask)) | (value)))
+#define PIT_SET_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) |  (value)))
+#define PIT_CLR_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) & ~(value)))
+#define PIT_TOG_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_MCR bitfields
+ */
+
+/*!
+ * @name Register PIT_MCR, field FRZ[0] (RW)
+ *
+ * Allows the timers to be stopped when the device enters the Debug mode.
+ *
+ * Values:
+ * - 0b0 - Timers continue to run in Debug mode.
+ * - 0b1 - Timers are stopped in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_FRZ field. */
+#define PIT_RD_MCR_FRZ(base) ((PIT_MCR_REG(base) & PIT_MCR_FRZ_MASK) >> PIT_MCR_FRZ_SHIFT)
+#define PIT_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define PIT_WR_MCR_FRZ(base, value) (PIT_RMW_MCR(base, PIT_MCR_FRZ_MASK, PIT_MCR_FRZ(value)))
+#define PIT_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_MCR, field MDIS[1] (RW)
+ *
+ * Disables the standard timers. This field must be enabled before any other
+ * setup is done.
+ *
+ * Values:
+ * - 0b0 - Clock for standard PIT timers is enabled.
+ * - 0b1 - Clock for standard PIT timers is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_MDIS field. */
+#define PIT_RD_MCR_MDIS(base) ((PIT_MCR_REG(base) & PIT_MCR_MDIS_MASK) >> PIT_MCR_MDIS_SHIFT)
+#define PIT_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define PIT_WR_MCR_MDIS(base, value) (PIT_RMW_MCR(base, PIT_MCR_MDIS_MASK, PIT_MCR_MDIS(value)))
+#define PIT_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_LDVAL - Timer Load Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_LDVAL - Timer Load Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers select the timeout period for the timer interrupts.
+ */
+/*!
+ * @name Constants and macros for entire PIT_LDVAL register
+ */
+/*@{*/
+#define PIT_RD_LDVAL(base, index) (PIT_LDVAL_REG(base, index))
+#define PIT_WR_LDVAL(base, index, value) (PIT_LDVAL_REG(base, index) = (value))
+#define PIT_RMW_LDVAL(base, index, mask, value) (PIT_WR_LDVAL(base, index, (PIT_RD_LDVAL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) |  (value)))
+#define PIT_CLR_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) & ~(value)))
+#define PIT_TOG_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_CVAL - Current Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_CVAL - Current Timer Value Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the current timer position.
+ */
+/*!
+ * @name Constants and macros for entire PIT_CVAL register
+ */
+/*@{*/
+#define PIT_RD_CVAL(base, index) (PIT_CVAL_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TCTRL - Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TCTRL - Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the control bits for each timer.
+ */
+/*!
+ * @name Constants and macros for entire PIT_TCTRL register
+ */
+/*@{*/
+#define PIT_RD_TCTRL(base, index) (PIT_TCTRL_REG(base, index))
+#define PIT_WR_TCTRL(base, index, value) (PIT_TCTRL_REG(base, index) = (value))
+#define PIT_RMW_TCTRL(base, index, mask, value) (PIT_WR_TCTRL(base, index, (PIT_RD_TCTRL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) |  (value)))
+#define PIT_CLR_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) & ~(value)))
+#define PIT_TOG_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TCTRL bitfields
+ */
+
+/*!
+ * @name Register PIT_TCTRL, field TEN[0] (RW)
+ *
+ * Enables or disables the timer.
+ *
+ * Values:
+ * - 0b0 - Timer n is disabled.
+ * - 0b1 - Timer n is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TEN field. */
+#define PIT_RD_TCTRL_TEN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TEN_MASK) >> PIT_TCTRL_TEN_SHIFT)
+#define PIT_BRD_TCTRL_TEN(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT))
+
+/*! @brief Set the TEN field to a new value. */
+#define PIT_WR_TCTRL_TEN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TEN_MASK, PIT_TCTRL_TEN(value)))
+#define PIT_BWR_TCTRL_TEN(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field TIE[1] (RW)
+ *
+ * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
+ * will immediately cause an interrupt event. To avoid this, the associated
+ * TFLGn[TIF] must be cleared first.
+ *
+ * Values:
+ * - 0b0 - Interrupt requests from Timer n are disabled.
+ * - 0b1 - Interrupt will be requested whenever TIF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TIE field. */
+#define PIT_RD_TCTRL_TIE(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TIE_MASK) >> PIT_TCTRL_TIE_SHIFT)
+#define PIT_BRD_TCTRL_TIE(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define PIT_WR_TCTRL_TIE(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TIE_MASK, PIT_TCTRL_TIE(value)))
+#define PIT_BWR_TCTRL_TIE(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field CHN[2] (RW)
+ *
+ * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
+ * Timer 0 cannot be chained.
+ *
+ * Values:
+ * - 0b0 - Timer is not chained.
+ * - 0b1 - Timer is chained to previous timer. For example, for Channel 2, if
+ *     this field is set, Timer 2 is chained to Timer 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_CHN field. */
+#define PIT_RD_TCTRL_CHN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_CHN_MASK) >> PIT_TCTRL_CHN_SHIFT)
+#define PIT_BRD_TCTRL_CHN(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT))
+
+/*! @brief Set the CHN field to a new value. */
+#define PIT_WR_TCTRL_CHN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_CHN_MASK, PIT_TCTRL_CHN(value)))
+#define PIT_BWR_TCTRL_CHN(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TFLG - Timer Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TFLG - Timer Flag Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers hold the PIT interrupt flags.
+ */
+/*!
+ * @name Constants and macros for entire PIT_TFLG register
+ */
+/*@{*/
+#define PIT_RD_TFLG(base, index) (PIT_TFLG_REG(base, index))
+#define PIT_WR_TFLG(base, index, value) (PIT_TFLG_REG(base, index) = (value))
+#define PIT_RMW_TFLG(base, index, mask, value) (PIT_WR_TFLG(base, index, (PIT_RD_TFLG(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) |  (value)))
+#define PIT_CLR_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) & ~(value)))
+#define PIT_TOG_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TFLG bitfields
+ */
+
+/*!
+ * @name Register PIT_TFLG, field TIF[0] (W1C)
+ *
+ * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
+ * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
+ * interrupt request.
+ *
+ * Values:
+ * - 0b0 - Timeout has not yet occurred.
+ * - 0b1 - Timeout has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TFLG_TIF field. */
+#define PIT_RD_TFLG_TIF(base, index) ((PIT_TFLG_REG(base, index) & PIT_TFLG_TIF_MASK) >> PIT_TFLG_TIF_SHIFT)
+#define PIT_BRD_TFLG_TIF(base, index) (BITBAND_ACCESS32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT))
+
+/*! @brief Set the TIF field to a new value. */
+#define PIT_WR_TFLG_TIF(base, index, value) (PIT_RMW_TFLG(base, index, PIT_TFLG_TIF_MASK, PIT_TFLG_TIF(value)))
+#define PIT_BWR_TFLG_TIF(base, index, value) (BITBAND_ACCESS32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PMC
+ *
+ * Power Management Controller
+ *
+ * Registers defined in this header file:
+ * - PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ * - PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ * - PMC_REGSC - Regulator Status And Control register
+ */
+
+#define PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
+#define PMC_IDX (0U) /*!< Instance number for PMC. */
+
+/*******************************************************************************
+ * PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
+ *
+ * Reset value: 0x10U
+ *
+ * This register contains status and control bits to support the low voltage
+ * detect function. This register should be written during the reset initialization
+ * program to set the desired controls even if the desired settings are the same
+ * as the reset settings. While the device is in the very low power or low
+ * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
+ * systems that must have LVD always on, configure the Power Mode Protection
+ * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
+ * low leakage modes from being enabled. See the device's data sheet for the
+ * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
+ * register's other bits are reset on Chip Reset Not VLLS. For more information
+ * about these reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC1 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC1(base)      (PMC_LVDSC1_REG(base))
+#define PMC_WR_LVDSC1(base, value) (PMC_LVDSC1_REG(base) = (value))
+#define PMC_RMW_LVDSC1(base, mask, value) (PMC_WR_LVDSC1(base, (PMC_RD_LVDSC1(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) |  (value)))
+#define PMC_CLR_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) & ~(value)))
+#define PMC_TOG_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC1 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
+ *
+ * Selects the LVD trip point voltage (V LVD ).
+ *
+ * Values:
+ * - 0b00 - Low trip point selected (V LVD = V LVDL )
+ * - 0b01 - High trip point selected (V LVD = V LVDH )
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
+#define PMC_RD_LVDSC1_LVDV(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDV_MASK) >> PMC_LVDSC1_LVDV_SHIFT)
+#define PMC_BRD_LVDSC1_LVDV(base) (PMC_RD_LVDSC1_LVDV(base))
+
+/*! @brief Set the LVDV field to a new value. */
+#define PMC_WR_LVDSC1_LVDV(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDV_MASK, PMC_LVDSC1_LVDV(value)))
+#define PMC_BWR_LVDSC1_LVDV(base, value) (PMC_WR_LVDSC1_LVDV(base, value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
+ *
+ * This write-once bit enables LVDF events to generate a hardware reset.
+ * Additional writes are ignored.
+ *
+ * Values:
+ * - 0b0 - LVDF does not generate hardware resets
+ * - 0b1 - Force an MCU reset when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
+#define PMC_RD_LVDSC1_LVDRE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDRE_MASK) >> PMC_LVDSC1_LVDRE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDRE(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT))
+
+/*! @brief Set the LVDRE field to a new value. */
+#define PMC_WR_LVDSC1_LVDRE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDRE_MASK, PMC_LVDSC1_LVDRE(value)))
+#define PMC_BWR_LVDSC1_LVDRE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVDF.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupt disabled (use polling)
+ * - 0b1 - Request a hardware interrupt when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
+#define PMC_RD_LVDSC1_LVDIE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDIE_MASK) >> PMC_LVDSC1_LVDIE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDIE(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT))
+
+/*! @brief Set the LVDIE field to a new value. */
+#define PMC_WR_LVDSC1_LVDIE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDIE_MASK, PMC_LVDSC1_LVDIE(value)))
+#define PMC_BWR_LVDSC1_LVDIE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage detection errors.
+ * Write 1 to clear LVDF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVDACK field to a new value. */
+#define PMC_WR_LVDSC1_LVDACK(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDACK_MASK, PMC_LVDSC1_LVDACK(value)))
+#define PMC_BWR_LVDSC1_LVDACK(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage detect event.
+ *
+ * Values:
+ * - 0b0 - Low-voltage event not detected
+ * - 0b1 - Low-voltage event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
+#define PMC_RD_LVDSC1_LVDF(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDF_MASK) >> PMC_LVDSC1_LVDF_SHIFT)
+#define PMC_BRD_LVDSC1_LVDF(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains status and control bits to support the low voltage
+ * warning function. While the device is in the very low power or low leakage modes,
+ * the LVD system is disabled regardless of LVDSC2 settings. See the device's
+ * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
+ * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
+ * register are reset on Chip Reset Not VLLS. For more information about these
+ * reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC2 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC2(base)      (PMC_LVDSC2_REG(base))
+#define PMC_WR_LVDSC2(base, value) (PMC_LVDSC2_REG(base) = (value))
+#define PMC_RMW_LVDSC2(base, mask, value) (PMC_WR_LVDSC2(base, (PMC_RD_LVDSC2(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) |  (value)))
+#define PMC_CLR_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) & ~(value)))
+#define PMC_TOG_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC2 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
+ *
+ * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
+ * depends on LVDSC1[LVDV].
+ *
+ * Values:
+ * - 0b00 - Low trip point selected (VLVW = VLVW1)
+ * - 0b01 - Mid 1 trip point selected (VLVW = VLVW2)
+ * - 0b10 - Mid 2 trip point selected (VLVW = VLVW3)
+ * - 0b11 - High trip point selected (VLVW = VLVW4)
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
+#define PMC_RD_LVDSC2_LVWV(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWV_MASK) >> PMC_LVDSC2_LVWV_SHIFT)
+#define PMC_BRD_LVDSC2_LVWV(base) (PMC_RD_LVDSC2_LVWV(base))
+
+/*! @brief Set the LVWV field to a new value. */
+#define PMC_WR_LVDSC2_LVWV(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWV_MASK, PMC_LVDSC2_LVWV(value)))
+#define PMC_BWR_LVDSC2_LVWV(base, value) (PMC_WR_LVDSC2_LVWV(base, value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVWF.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupt disabled (use polling)
+ * - 0b1 - Request a hardware interrupt when LVWF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
+#define PMC_RD_LVDSC2_LVWIE(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWIE_MASK) >> PMC_LVDSC2_LVWIE_SHIFT)
+#define PMC_BRD_LVDSC2_LVWIE(base) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT))
+
+/*! @brief Set the LVWIE field to a new value. */
+#define PMC_WR_LVDSC2_LVWIE(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWIE_MASK, PMC_LVDSC2_LVWIE(value)))
+#define PMC_BWR_LVDSC2_LVWIE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage warning errors.
+ * Write 1 to clear LVWF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVWACK field to a new value. */
+#define PMC_WR_LVDSC2_LVWACK(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWACK_MASK, PMC_LVDSC2_LVWACK(value)))
+#define PMC_BWR_LVDSC2_LVWACK(base, value) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage warning event. LVWF is
+ * set when VSupply transitions below the trip point, or after reset and VSupply is
+ * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
+ * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
+ * LVWACK first.
+ *
+ * Values:
+ * - 0b0 - Low-voltage warning event not detected
+ * - 0b1 - Low-voltage warning event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
+#define PMC_RD_LVDSC2_LVWF(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWF_MASK) >> PMC_LVDSC2_LVWF_SHIFT)
+#define PMC_BRD_LVDSC2_LVWF(base) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_REGSC - Regulator Status And Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_REGSC - Regulator Status And Control register (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * The PMC contains an internal voltage regulator. The voltage regulator design
+ * uses a bandgap reference that is also available through a buffer as input to
+ * certain internal peripherals, such as the CMP and ADC. The internal regulator
+ * provides a status bit (REGONS) indicating the regulator is in run regulation.
+ * This register is reset on Chip Reset Not VLLS and by reset types that trigger
+ * Chip Reset not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire PMC_REGSC register
+ */
+/*@{*/
+#define PMC_RD_REGSC(base)       (PMC_REGSC_REG(base))
+#define PMC_WR_REGSC(base, value) (PMC_REGSC_REG(base) = (value))
+#define PMC_RMW_REGSC(base, mask, value) (PMC_WR_REGSC(base, (PMC_RD_REGSC(base) & ~(mask)) | (value)))
+#define PMC_SET_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) |  (value)))
+#define PMC_CLR_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) & ~(value)))
+#define PMC_TOG_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_REGSC bitfields
+ */
+
+/*!
+ * @name Register PMC_REGSC, field BGBE[0] (RW)
+ *
+ * Enables the bandgap buffer.
+ *
+ * Values:
+ * - 0b0 - Bandgap buffer not enabled
+ * - 0b1 - Bandgap buffer enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGBE field. */
+#define PMC_RD_REGSC_BGBE(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGBE_MASK) >> PMC_REGSC_BGBE_SHIFT)
+#define PMC_BRD_REGSC_BGBE(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT))
+
+/*! @brief Set the BGBE field to a new value. */
+#define PMC_WR_REGSC_BGBE(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGBE_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGBE(value)))
+#define PMC_BWR_REGSC_BGBE(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field REGONS[2] (RO)
+ *
+ * This read-only field provides the current status of the internal voltage
+ * regulator.
+ *
+ * Values:
+ * - 0b0 - Regulator is in stop regulation or in transition to/from it
+ * - 0b1 - Regulator is in run regulation
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_REGONS field. */
+#define PMC_RD_REGSC_REGONS(base) ((PMC_REGSC_REG(base) & PMC_REGSC_REGONS_MASK) >> PMC_REGSC_REGONS_SHIFT)
+#define PMC_BRD_REGSC_REGONS(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_REGONS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field ACKISO[3] (W1C)
+ *
+ * Reading this field indicates whether certain peripherals and the I/O pads are
+ * in a latched state as a result of having been in a VLLS mode. Writing 1 to
+ * this field when it is set releases the I/O pads and certain peripherals to their
+ * normal run mode state. After recovering from a VLLS mode, user should restore
+ * chip configuration before clearing ACKISO. In particular, pin configuration
+ * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
+ * being falsely set when ACKISO is cleared.
+ *
+ * Values:
+ * - 0b0 - Peripherals and I/O pads are in normal run state.
+ * - 0b1 - Certain peripherals and I/O pads are in an isolated and latched state.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_ACKISO field. */
+#define PMC_RD_REGSC_ACKISO(base) ((PMC_REGSC_REG(base) & PMC_REGSC_ACKISO_MASK) >> PMC_REGSC_ACKISO_SHIFT)
+#define PMC_BRD_REGSC_ACKISO(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT))
+
+/*! @brief Set the ACKISO field to a new value. */
+#define PMC_WR_REGSC_ACKISO(base, value) (PMC_RMW_REGSC(base, PMC_REGSC_ACKISO_MASK, PMC_REGSC_ACKISO(value)))
+#define PMC_BWR_REGSC_ACKISO(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field BGEN[4] (RW)
+ *
+ * BGEN controls whether the bandgap is enabled in lower power modes of
+ * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
+ * reference in low power modes of operation, set BGEN to continue to enable the
+ * bandgap operation. When the bandgap voltage reference is not needed in low
+ * power modes, clear BGEN to avoid excess power consumption.
+ *
+ * Values:
+ * - 0b0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
+ * - 0b1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGEN field. */
+#define PMC_RD_REGSC_BGEN(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGEN_MASK) >> PMC_REGSC_BGEN_SHIFT)
+#define PMC_BRD_REGSC_BGEN(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT))
+
+/*! @brief Set the BGEN field to a new value. */
+#define PMC_WR_REGSC_BGEN(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGEN_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGEN(value)))
+#define PMC_BWR_REGSC_BGEN(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PORT
+ *
+ * Pin Control and Interrupts
+ *
+ * Registers defined in this header file:
+ * - PORT_PCR - Pin Control Register n
+ * - PORT_GPCLR - Global Pin Control Low Register
+ * - PORT_GPCHR - Global Pin Control High Register
+ * - PORT_ISFR - Interrupt Status Flag Register
+ * - PORT_DFER - Digital Filter Enable Register
+ * - PORT_DFCR - Digital Filter Clock Register
+ * - PORT_DFWR - Digital Filter Width Register
+ */
+
+#define PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
+#define PORTA_IDX (0U) /*!< Instance number for PORTA. */
+#define PORTB_IDX (1U) /*!< Instance number for PORTB. */
+#define PORTC_IDX (2U) /*!< Instance number for PORTC. */
+#define PORTD_IDX (3U) /*!< Instance number for PORTD. */
+#define PORTE_IDX (4U) /*!< Instance number for PORTE. */
+
+/*******************************************************************************
+ * PORT_PCR - Pin Control Register n
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_PCR - Pin Control Register n (RW)
+ *
+ * Reset value: 0x00000746U
+ *
+ * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
+ * this device. See the GPIO Configuration section for details on the available
+ * functions for each pin. Do not modify pin configuration registers associated
+ * with pins not available in your selected package. All unbonded pins not
+ * available in your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire PORT_PCR register
+ */
+/*@{*/
+#define PORT_RD_PCR(base, index) (PORT_PCR_REG(base, index))
+#define PORT_WR_PCR(base, index, value) (PORT_PCR_REG(base, index) = (value))
+#define PORT_RMW_PCR(base, index, mask, value) (PORT_WR_PCR(base, index, (PORT_RD_PCR(base, index) & ~(mask)) | (value)))
+#define PORT_SET_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) |  (value)))
+#define PORT_CLR_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) & ~(value)))
+#define PORT_TOG_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_PCR bitfields
+ */
+
+/*!
+ * @name Register PORT_PCR, field PS[0] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Internal pulldown resistor is enabled on the corresponding pin, if
+ *     the corresponding PE field is set.
+ * - 0b1 - Internal pullup resistor is enabled on the corresponding pin, if the
+ *     corresponding PE field is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PS field. */
+#define PORT_RD_PCR_PS(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PS_MASK) >> PORT_PCR_PS_SHIFT)
+#define PORT_BRD_PCR_PS(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT))
+
+/*! @brief Set the PS field to a new value. */
+#define PORT_WR_PCR_PS(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PS_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PS(value)))
+#define PORT_BWR_PCR_PS(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PE[1] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Internal pullup or pulldown resistor is not enabled on the
+ *     corresponding pin.
+ * - 0b1 - Internal pullup or pulldown resistor is enabled on the corresponding
+ *     pin, if the pin is configured as a digital input.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PE field. */
+#define PORT_RD_PCR_PE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PE_MASK) >> PORT_PCR_PE_SHIFT)
+#define PORT_BRD_PCR_PE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT))
+
+/*! @brief Set the PE field to a new value. */
+#define PORT_WR_PCR_PE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PE(value)))
+#define PORT_BWR_PCR_PE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field SRE[2] (RW)
+ *
+ * Slew rate configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Fast slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ * - 0b1 - Slow slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_SRE field. */
+#define PORT_RD_PCR_SRE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_SRE_MASK) >> PORT_PCR_SRE_SHIFT)
+#define PORT_BRD_PCR_SRE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT))
+
+/*! @brief Set the SRE field to a new value. */
+#define PORT_WR_PCR_SRE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_SRE(value)))
+#define PORT_BWR_PCR_SRE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PFE[4] (RW)
+ *
+ * Passive filter configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Passive input filter is disabled on the corresponding pin.
+ * - 0b1 - Passive input filter is enabled on the corresponding pin, if the pin
+ *     is configured as a digital input. Refer to the device data sheet for
+ *     filter characteristics.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PFE field. */
+#define PORT_RD_PCR_PFE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PFE_MASK) >> PORT_PCR_PFE_SHIFT)
+#define PORT_BRD_PCR_PFE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT))
+
+/*! @brief Set the PFE field to a new value. */
+#define PORT_WR_PCR_PFE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PFE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PFE(value)))
+#define PORT_BWR_PCR_PFE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ODE[5] (RW)
+ *
+ * Open drain configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Open drain output is disabled on the corresponding pin.
+ * - 0b1 - Open drain output is enabled on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ODE field. */
+#define PORT_RD_PCR_ODE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ODE_MASK) >> PORT_PCR_ODE_SHIFT)
+#define PORT_BRD_PCR_ODE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ODE_SHIFT))
+
+/*! @brief Set the ODE field to a new value. */
+#define PORT_WR_PCR_ODE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_ODE(value)))
+#define PORT_BWR_PCR_ODE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field DSE[6] (RW)
+ *
+ * Drive strength configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Low drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ * - 0b1 - High drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_DSE field. */
+#define PORT_RD_PCR_DSE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_DSE_MASK) >> PORT_PCR_DSE_SHIFT)
+#define PORT_BRD_PCR_DSE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT))
+
+/*! @brief Set the DSE field to a new value. */
+#define PORT_WR_PCR_DSE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_DSE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_DSE(value)))
+#define PORT_BWR_PCR_DSE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field MUX[10:8] (RW)
+ *
+ * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
+ * reserved and may result in configuring the pin for a different pin muxing
+ * slot. The corresponding pin is configured in the following pin muxing slot as
+ * follows:
+ *
+ * Values:
+ * - 0b000 - Pin disabled (analog).
+ * - 0b001 - Alternative 1 (GPIO).
+ * - 0b010 - Alternative 2 (chip-specific).
+ * - 0b011 - Alternative 3 (chip-specific).
+ * - 0b100 - Alternative 4 (chip-specific).
+ * - 0b101 - Alternative 5 (chip-specific).
+ * - 0b110 - Alternative 6 (chip-specific).
+ * - 0b111 - Alternative 7 (chip-specific).
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_MUX field. */
+#define PORT_RD_PCR_MUX(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_MUX_MASK) >> PORT_PCR_MUX_SHIFT)
+#define PORT_BRD_PCR_MUX(base, index) (PORT_RD_PCR_MUX(base, index))
+
+/*! @brief Set the MUX field to a new value. */
+#define PORT_WR_PCR_MUX(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_MUX_MASK | PORT_PCR_ISF_MASK), PORT_PCR_MUX(value)))
+#define PORT_BWR_PCR_MUX(base, index, value) (PORT_WR_PCR_MUX(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field LK[15] (RW)
+ *
+ * Values:
+ * - 0b0 - Pin Control Register fields [15:0] are not locked.
+ * - 0b1 - Pin Control Register fields [15:0] are locked and cannot be updated
+ *     until the next system reset.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_LK field. */
+#define PORT_RD_PCR_LK(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_LK_MASK) >> PORT_PCR_LK_SHIFT)
+#define PORT_BRD_PCR_LK(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_LK_SHIFT))
+
+/*! @brief Set the LK field to a new value. */
+#define PORT_WR_PCR_LK(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_LK_MASK | PORT_PCR_ISF_MASK), PORT_PCR_LK(value)))
+#define PORT_BWR_PCR_LK(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_LK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field IRQC[19:16] (RW)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * corresponding pin is configured to generate interrupt/DMA request as follows:
+ *
+ * Values:
+ * - 0b0000 - Interrupt/DMA request disabled.
+ * - 0b0001 - DMA request on rising edge.
+ * - 0b0010 - DMA request on falling edge.
+ * - 0b0011 - DMA request on either edge.
+ * - 0b1000 - Interrupt when logic 0.
+ * - 0b1001 - Interrupt on rising-edge.
+ * - 0b1010 - Interrupt on falling-edge.
+ * - 0b1011 - Interrupt on either edge.
+ * - 0b1100 - Interrupt when logic 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_IRQC field. */
+#define PORT_RD_PCR_IRQC(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_IRQC_MASK) >> PORT_PCR_IRQC_SHIFT)
+#define PORT_BRD_PCR_IRQC(base, index) (PORT_RD_PCR_IRQC(base, index))
+
+/*! @brief Set the IRQC field to a new value. */
+#define PORT_WR_PCR_IRQC(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_IRQC_MASK | PORT_PCR_ISF_MASK), PORT_PCR_IRQC(value)))
+#define PORT_BWR_PCR_IRQC(base, index, value) (PORT_WR_PCR_IRQC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ISF[24] (W1C)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Configured interrupt is not detected.
+ * - 0b1 - Configured interrupt is detected. If the pin is configured to
+ *     generate a DMA request, then the corresponding flag will be cleared automatically
+ *     at the completion of the requested DMA transfer. Otherwise, the flag
+ *     remains set until a logic 1 is written to the flag. If the pin is configured
+ *     for a level sensitive interrupt and the pin remains asserted, then the flag
+ *     is set again immediately after it is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ISF field. */
+#define PORT_RD_PCR_ISF(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ISF_MASK) >> PORT_PCR_ISF_SHIFT)
+#define PORT_BRD_PCR_ISF(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT))
+
+/*! @brief Set the ISF field to a new value. */
+#define PORT_WR_PCR_ISF(base, index, value) (PORT_RMW_PCR(base, index, PORT_PCR_ISF_MASK, PORT_PCR_ISF(value)))
+#define PORT_BWR_PCR_ISF(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCLR - Global Pin Control Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCLR - Global Pin Control Low Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCLR register
+ */
+/*@{*/
+#define PORT_RD_GPCLR(base)      (PORT_GPCLR_REG(base))
+#define PORT_WR_GPCLR(base, value) (PORT_GPCLR_REG(base) = (value))
+#define PORT_RMW_GPCLR(base, mask, value) (PORT_WR_GPCLR(base, (PORT_RD_GPCLR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCLR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCLR_GPWD(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWD_MASK, PORT_GPCLR_GPWD(value)))
+#define PORT_BWR_GPCLR_GPWD(base, value) (PORT_WR_GPCLR_GPWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
+ *     the value in GPWD.
+ * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
+ *     value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCLR_GPWE(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWE_MASK, PORT_GPCLR_GPWE(value)))
+#define PORT_BWR_GPCLR_GPWE(base, value) (PORT_WR_GPCLR_GPWE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCHR - Global Pin Control High Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCHR - Global Pin Control High Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCHR register
+ */
+/*@{*/
+#define PORT_RD_GPCHR(base)      (PORT_GPCHR_REG(base))
+#define PORT_WR_GPCHR(base, value) (PORT_GPCHR_REG(base) = (value))
+#define PORT_RMW_GPCHR(base, mask, value) (PORT_WR_GPCHR(base, (PORT_RD_GPCHR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCHR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCHR_GPWD(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWD_MASK, PORT_GPCHR_GPWD(value)))
+#define PORT_BWR_GPCHR_GPWD(base, value) (PORT_WR_GPCHR_GPWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
+ *     the value in GPWD.
+ * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
+ *     value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCHR_GPWE(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWE_MASK, PORT_GPCHR_GPWE(value)))
+#define PORT_BWR_GPCHR_GPWE(base, value) (PORT_WR_GPCHR_GPWE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_ISFR - Interrupt Status Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_ISFR - Interrupt Status Flag Register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * Interrupt Status Flag for each pin is also visible in the corresponding Pin
+ * Control Register, and each flag can be cleared in either location.
+ */
+/*!
+ * @name Constants and macros for entire PORT_ISFR register
+ */
+/*@{*/
+#define PORT_RD_ISFR(base)       (PORT_ISFR_REG(base))
+#define PORT_WR_ISFR(base, value) (PORT_ISFR_REG(base) = (value))
+#define PORT_RMW_ISFR(base, mask, value) (PORT_WR_ISFR(base, (PORT_RD_ISFR(base) & ~(mask)) | (value)))
+#define PORT_SET_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) |  (value)))
+#define PORT_CLR_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) & ~(value)))
+#define PORT_TOG_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFER - Digital Filter Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFER - Digital Filter Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The corresponding bit is read only for pins that do not support a digital
+ * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
+ * the pins that support digital filter. The digital filter configuration is valid
+ * in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFER register
+ */
+/*@{*/
+#define PORT_RD_DFER(base)       (PORT_DFER_REG(base))
+#define PORT_WR_DFER(base, value) (PORT_DFER_REG(base) = (value))
+#define PORT_RMW_DFER(base, mask, value) (PORT_WR_DFER(base, (PORT_RD_DFER(base) & ~(mask)) | (value)))
+#define PORT_SET_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) |  (value)))
+#define PORT_CLR_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) & ~(value)))
+#define PORT_TOG_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFCR - Digital Filter Clock Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFCR - Digital Filter Clock Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFCR register
+ */
+/*@{*/
+#define PORT_RD_DFCR(base)       (PORT_DFCR_REG(base))
+#define PORT_WR_DFCR(base, value) (PORT_DFCR_REG(base) = (value))
+#define PORT_RMW_DFCR(base, mask, value) (PORT_WR_DFCR(base, (PORT_RD_DFCR(base) & ~(mask)) | (value)))
+#define PORT_SET_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) |  (value)))
+#define PORT_CLR_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) & ~(value)))
+#define PORT_TOG_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_DFCR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFCR, field CS[0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the clock source for the digital input filters. Changing the filter
+ * clock source must be done only when all digital filters are disabled.
+ *
+ * Values:
+ * - 0b0 - Digital filters are clocked by the bus clock.
+ * - 0b1 - Digital filters are clocked by the 1 kHz LPO clock.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_DFCR_CS field. */
+#define PORT_RD_DFCR_CS(base) ((PORT_DFCR_REG(base) & PORT_DFCR_CS_MASK) >> PORT_DFCR_CS_SHIFT)
+#define PORT_BRD_DFCR_CS(base) (BITBAND_ACCESS32(&PORT_DFCR_REG(base), PORT_DFCR_CS_SHIFT))
+
+/*! @brief Set the CS field to a new value. */
+#define PORT_WR_DFCR_CS(base, value) (PORT_RMW_DFCR(base, PORT_DFCR_CS_MASK, PORT_DFCR_CS(value)))
+#define PORT_BWR_DFCR_CS(base, value) (BITBAND_ACCESS32(&PORT_DFCR_REG(base), PORT_DFCR_CS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFWR - Digital Filter Width Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFWR - Digital Filter Width Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFWR register
+ */
+/*@{*/
+#define PORT_RD_DFWR(base)       (PORT_DFWR_REG(base))
+#define PORT_WR_DFWR(base, value) (PORT_DFWR_REG(base) = (value))
+#define PORT_RMW_DFWR(base, mask, value) (PORT_WR_DFWR(base, (PORT_RD_DFWR(base) & ~(mask)) | (value)))
+#define PORT_SET_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) |  (value)))
+#define PORT_CLR_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) & ~(value)))
+#define PORT_TOG_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_DFWR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFWR, field FILT[4:0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the maximum size of the glitches, in clock cycles, that the digital
+ * filter absorbs for the enabled digital filters. Glitches that are longer than
+ * this register setting will pass through the digital filter, and glitches that
+ * are equal to or less than this register setting are filtered. Changing the
+ * filter length must be done only after all filters are disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_DFWR_FILT field. */
+#define PORT_RD_DFWR_FILT(base) ((PORT_DFWR_REG(base) & PORT_DFWR_FILT_MASK) >> PORT_DFWR_FILT_SHIFT)
+#define PORT_BRD_DFWR_FILT(base) (PORT_RD_DFWR_FILT(base))
+
+/*! @brief Set the FILT field to a new value. */
+#define PORT_WR_DFWR_FILT(base, value) (PORT_RMW_DFWR(base, PORT_DFWR_FILT_MASK, PORT_DFWR_FILT(value)))
+#define PORT_BWR_DFWR_FILT(base, value) (PORT_WR_DFWR_FILT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 RCM
+ *
+ * Reset Control Module
+ *
+ * Registers defined in this header file:
+ * - RCM_SRS0 - System Reset Status Register 0
+ * - RCM_SRS1 - System Reset Status Register 1
+ * - RCM_RPFC - Reset Pin Filter Control register
+ * - RCM_RPFW - Reset Pin Filter Width register
+ * - RCM_MR - Mode Register
+ */
+
+#define RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */
+#define RCM_IDX (0U) /*!< Instance number for RCM. */
+
+/*******************************************************************************
+ * RCM_SRS0 - System Reset Status Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS0 - System Reset Status Register 0 (RO)
+ *
+ * Reset value: 0x82U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
+ * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS0 register
+ */
+/*@{*/
+#define RCM_RD_SRS0(base)        (RCM_SRS0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS0 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS0, field WAKEUP[0] (RO)
+ *
+ * Indicates a reset has been caused by an enabled LLWU module wakeup source
+ * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
+ * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
+ * mode causes a reset. This bit is cleared by any reset except WAKEUP.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by LLWU module wakeup source
+ * - 0b1 - Reset caused by LLWU module wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WAKEUP field. */
+#define RCM_RD_SRS0_WAKEUP(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WAKEUP_MASK) >> RCM_SRS0_WAKEUP_SHIFT)
+#define RCM_BRD_SRS0_WAKEUP(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_WAKEUP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LVD[1] (RO)
+ *
+ * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
+ * an LVD reset occurs. This field is also set by POR.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by LVD trip or POR
+ * - 0b1 - Reset caused by LVD trip or POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LVD field. */
+#define RCM_RD_SRS0_LVD(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LVD_MASK) >> RCM_SRS0_LVD_SHIFT)
+#define RCM_BRD_SRS0_LVD(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LVD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LOC[2] (RO)
+ *
+ * Indicates a reset has been caused by a loss of external clock. The MCG clock
+ * monitor must be enabled for a loss of clock to be detected. Refer to the
+ * detailed MCG description for information on enabling the clock monitor.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by a loss of external clock.
+ * - 0b1 - Reset caused by a loss of external clock.
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LOC field. */
+#define RCM_RD_SRS0_LOC(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOC_MASK) >> RCM_SRS0_LOC_SHIFT)
+#define RCM_BRD_SRS0_LOC(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LOC_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LOL[3] (RO)
+ *
+ * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
+ * MCG description for information on the loss-of-clock event.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by a loss of lock in the PLL
+ * - 0b1 - Reset caused by a loss of lock in the PLL
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LOL field. */
+#define RCM_RD_SRS0_LOL(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOL_MASK) >> RCM_SRS0_LOL_SHIFT)
+#define RCM_BRD_SRS0_LOL(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LOL_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field WDOG[5] (RO)
+ *
+ * Indicates a reset has been caused by the watchdog timer Computer Operating
+ * Properly (COP) timing out. This reset source can be blocked by disabling the COP
+ * watchdog: write 00 to SIM_COPCTRL[COPT].
+ *
+ * Values:
+ * - 0b0 - Reset not caused by watchdog timeout
+ * - 0b1 - Reset caused by watchdog timeout
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WDOG field. */
+#define RCM_RD_SRS0_WDOG(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WDOG_MASK) >> RCM_SRS0_WDOG_SHIFT)
+#define RCM_BRD_SRS0_WDOG(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_WDOG_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field PIN[6] (RO)
+ *
+ * Indicates a reset has been caused by an active-low level on the external
+ * RESET pin.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by external reset pin
+ * - 0b1 - Reset caused by external reset pin
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_PIN field. */
+#define RCM_RD_SRS0_PIN(base) ((RCM_SRS0_REG(base) & RCM_SRS0_PIN_MASK) >> RCM_SRS0_PIN_SHIFT)
+#define RCM_BRD_SRS0_PIN(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_PIN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field POR[7] (RO)
+ *
+ * Indicates a reset has been caused by the power-on detection logic. Because
+ * the internal supply voltage was ramping up at the time, the low-voltage reset
+ * (LVD) status bit is also set to indicate that the reset occurred while the
+ * internal supply was below the LVD threshold.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by POR
+ * - 0b1 - Reset caused by POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_POR field. */
+#define RCM_RD_SRS0_POR(base) ((RCM_SRS0_REG(base) & RCM_SRS0_POR_MASK) >> RCM_SRS0_POR_SHIFT)
+#define RCM_BRD_SRS0_POR(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_POR_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_SRS1 - System Reset Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS1 - System Reset Status Register 1 (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS1 register
+ */
+/*@{*/
+#define RCM_RD_SRS1(base)        (RCM_SRS1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS1 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS1, field JTAG[0] (RO)
+ *
+ * Indicates a reset has been caused by JTAG selection of certain IR codes:
+ * EZPORT, EXTEST, HIGHZ, and CLAMP.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by JTAG
+ * - 0b1 - Reset caused by JTAG
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_JTAG field. */
+#define RCM_RD_SRS1_JTAG(base) ((RCM_SRS1_REG(base) & RCM_SRS1_JTAG_MASK) >> RCM_SRS1_JTAG_SHIFT)
+#define RCM_BRD_SRS1_JTAG(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_JTAG_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field LOCKUP[1] (RO)
+ *
+ * Indicates a reset has been caused by the ARM core indication of a LOCKUP
+ * event.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by core LOCKUP event
+ * - 0b1 - Reset caused by core LOCKUP event
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_LOCKUP field. */
+#define RCM_RD_SRS1_LOCKUP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_LOCKUP_MASK) >> RCM_SRS1_LOCKUP_SHIFT)
+#define RCM_BRD_SRS1_LOCKUP(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_LOCKUP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SW[2] (RO)
+ *
+ * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
+ * Application Interrupt and Reset Control Register in the ARM core.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by software setting of SYSRESETREQ bit
+ * - 0b1 - Reset caused by software setting of SYSRESETREQ bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SW field. */
+#define RCM_RD_SRS1_SW(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SW_MASK) >> RCM_SRS1_SW_SHIFT)
+#define RCM_BRD_SRS1_SW(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_SW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field MDM_AP[3] (RO)
+ *
+ * Indicates a reset has been caused by the host debugger system setting of the
+ * System Reset Request bit in the MDM-AP Control Register.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by host debugger system setting of the System Reset
+ *     Request bit
+ * - 0b1 - Reset caused by host debugger system setting of the System Reset
+ *     Request bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_MDM_AP field. */
+#define RCM_RD_SRS1_MDM_AP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_MDM_AP_MASK) >> RCM_SRS1_MDM_AP_SHIFT)
+#define RCM_BRD_SRS1_MDM_AP(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_MDM_AP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field EZPT[4] (RO)
+ *
+ * Indicates a reset has been caused by EzPort receiving the RESET command while
+ * the device is in EzPort mode.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by EzPort receiving the RESET command while the
+ *     device is in EzPort mode
+ * - 0b1 - Reset caused by EzPort receiving the RESET command while the device
+ *     is in EzPort mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_EZPT field. */
+#define RCM_RD_SRS1_EZPT(base) ((RCM_SRS1_REG(base) & RCM_SRS1_EZPT_MASK) >> RCM_SRS1_EZPT_SHIFT)
+#define RCM_BRD_SRS1_EZPT(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_EZPT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SACKERR[5] (RO)
+ *
+ * Indicates that after an attempt to enter Stop mode, a reset has been caused
+ * by a failure of one or more peripherals to acknowledge within approximately one
+ * second to enter stop mode.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by peripheral failure to acknowledge attempt to
+ *     enter stop mode
+ * - 0b1 - Reset caused by peripheral failure to acknowledge attempt to enter
+ *     stop mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SACKERR field. */
+#define RCM_RD_SRS1_SACKERR(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SACKERR_MASK) >> RCM_SRS1_SACKERR_SHIFT)
+#define RCM_BRD_SRS1_SACKERR(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_SACKERR_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFC - Reset Pin Filter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFC - Reset Pin Filter Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
+ * other reset types. The bus clock filter is reset when disabled or when entering
+ * stop mode. The LPO filter is reset when disabled or when entering any low
+ * leakage stop mode .
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFC register
+ */
+/*@{*/
+#define RCM_RD_RPFC(base)        (RCM_RPFC_REG(base))
+#define RCM_WR_RPFC(base, value) (RCM_RPFC_REG(base) = (value))
+#define RCM_RMW_RPFC(base, mask, value) (RCM_WR_RPFC(base, (RCM_RD_RPFC(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) |  (value)))
+#define RCM_CLR_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) & ~(value)))
+#define RCM_TOG_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFC bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
+ *
+ * Selects how the reset pin filter is enabled in run and wait modes.
+ *
+ * Values:
+ * - 0b00 - All filtering disabled
+ * - 0b01 - Bus clock filter enabled for normal operation
+ * - 0b10 - LPO clock filter enabled for normal operation
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */
+#define RCM_RD_RPFC_RSTFLTSRW(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSRW_MASK) >> RCM_RPFC_RSTFLTSRW_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSRW(base) (RCM_RD_RPFC_RSTFLTSRW(base))
+
+/*! @brief Set the RSTFLTSRW field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSRW(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSRW_MASK, RCM_RPFC_RSTFLTSRW(value)))
+#define RCM_BWR_RPFC_RSTFLTSRW(base, value) (RCM_WR_RPFC_RSTFLTSRW(base, value))
+/*@}*/
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
+ *
+ * Selects how the reset pin filter is enabled in Stop and VLPS modes
+ *
+ * Values:
+ * - 0b0 - All filtering disabled
+ * - 0b1 - LPO clock filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */
+#define RCM_RD_RPFC_RSTFLTSS(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSS_MASK) >> RCM_RPFC_RSTFLTSS_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSS(base) (BITBAND_ACCESS8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT))
+
+/*! @brief Set the RSTFLTSS field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSS(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSS_MASK, RCM_RPFC_RSTFLTSS(value)))
+#define RCM_BWR_RPFC_RSTFLTSS(base, value) (BITBAND_ACCESS8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFW - Reset Pin Filter Width register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFW - Reset Pin Filter Width register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
+ * They are unaffected by other reset types.
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFW register
+ */
+/*@{*/
+#define RCM_RD_RPFW(base)        (RCM_RPFW_REG(base))
+#define RCM_WR_RPFW(base, value) (RCM_RPFW_REG(base) = (value))
+#define RCM_RMW_RPFW(base, mask, value) (RCM_WR_RPFW(base, (RCM_RD_RPFW(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) |  (value)))
+#define RCM_CLR_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) & ~(value)))
+#define RCM_TOG_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFW bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
+ *
+ * Selects the reset pin bus clock filter width.
+ *
+ * Values:
+ * - 0b00000 - Bus clock filter count is 1
+ * - 0b00001 - Bus clock filter count is 2
+ * - 0b00010 - Bus clock filter count is 3
+ * - 0b00011 - Bus clock filter count is 4
+ * - 0b00100 - Bus clock filter count is 5
+ * - 0b00101 - Bus clock filter count is 6
+ * - 0b00110 - Bus clock filter count is 7
+ * - 0b00111 - Bus clock filter count is 8
+ * - 0b01000 - Bus clock filter count is 9
+ * - 0b01001 - Bus clock filter count is 10
+ * - 0b01010 - Bus clock filter count is 11
+ * - 0b01011 - Bus clock filter count is 12
+ * - 0b01100 - Bus clock filter count is 13
+ * - 0b01101 - Bus clock filter count is 14
+ * - 0b01110 - Bus clock filter count is 15
+ * - 0b01111 - Bus clock filter count is 16
+ * - 0b10000 - Bus clock filter count is 17
+ * - 0b10001 - Bus clock filter count is 18
+ * - 0b10010 - Bus clock filter count is 19
+ * - 0b10011 - Bus clock filter count is 20
+ * - 0b10100 - Bus clock filter count is 21
+ * - 0b10101 - Bus clock filter count is 22
+ * - 0b10110 - Bus clock filter count is 23
+ * - 0b10111 - Bus clock filter count is 24
+ * - 0b11000 - Bus clock filter count is 25
+ * - 0b11001 - Bus clock filter count is 26
+ * - 0b11010 - Bus clock filter count is 27
+ * - 0b11011 - Bus clock filter count is 28
+ * - 0b11100 - Bus clock filter count is 29
+ * - 0b11101 - Bus clock filter count is 30
+ * - 0b11110 - Bus clock filter count is 31
+ * - 0b11111 - Bus clock filter count is 32
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */
+#define RCM_RD_RPFW_RSTFLTSEL(base) ((RCM_RPFW_REG(base) & RCM_RPFW_RSTFLTSEL_MASK) >> RCM_RPFW_RSTFLTSEL_SHIFT)
+#define RCM_BRD_RPFW_RSTFLTSEL(base) (RCM_RD_RPFW_RSTFLTSEL(base))
+
+/*! @brief Set the RSTFLTSEL field to a new value. */
+#define RCM_WR_RPFW_RSTFLTSEL(base, value) (RCM_RMW_RPFW(base, RCM_RPFW_RSTFLTSEL_MASK, RCM_RPFW_RSTFLTSEL(value)))
+#define RCM_BWR_RPFW_RSTFLTSEL(base, value) (RCM_WR_RPFW_RSTFLTSEL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_MR - Mode Register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_MR - Mode Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the state of the
+ * mode pins during the last Chip Reset.
+ */
+/*!
+ * @name Constants and macros for entire RCM_MR register
+ */
+/*@{*/
+#define RCM_RD_MR(base)          (RCM_MR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_MR bitfields
+ */
+
+/*!
+ * @name Register RCM_MR, field EZP_MS[1] (RO)
+ *
+ * Reflects the state of the EZP_MS pin during the last Chip Reset
+ *
+ * Values:
+ * - 0b0 - Pin deasserted (logic 1)
+ * - 0b1 - Pin asserted (logic 0)
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_MR_EZP_MS field. */
+#define RCM_RD_MR_EZP_MS(base) ((RCM_MR_REG(base) & RCM_MR_EZP_MS_MASK) >> RCM_MR_EZP_MS_SHIFT)
+#define RCM_BRD_MR_EZP_MS(base) (BITBAND_ACCESS8(&RCM_MR_REG(base), RCM_MR_EZP_MS_SHIFT))
+/*@}*/
+
+/*
+ * MK64F12 RFSYS
+ *
+ * System register file
+ *
+ * Registers defined in this header file:
+ * - RFSYS_REG - Register file register
+ */
+
+#define RFSYS_INSTANCE_COUNT (1U) /*!< Number of instances of the RFSYS module. */
+#define RFSYS_IDX (0U) /*!< Instance number for RFSYS. */
+
+/*******************************************************************************
+ * RFSYS_REG - Register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFSYS_REG - Register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFSYS_REG register
+ */
+/*@{*/
+#define RFSYS_RD_REG(base, index) (RFSYS_REG_REG(base, index))
+#define RFSYS_WR_REG(base, index, value) (RFSYS_REG_REG(base, index) = (value))
+#define RFSYS_RMW_REG(base, index, mask, value) (RFSYS_WR_REG(base, index, (RFSYS_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFSYS_SET_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) |  (value)))
+#define RFSYS_CLR_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) & ~(value)))
+#define RFSYS_TOG_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFSYS_REG bitfields
+ */
+
+/*!
+ * @name Register RFSYS_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LL field. */
+#define RFSYS_RD_REG_LL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LL_MASK) >> RFSYS_REG_LL_SHIFT)
+#define RFSYS_BRD_REG_LL(base, index) (RFSYS_RD_REG_LL(base, index))
+
+/*! @brief Set the LL field to a new value. */
+#define RFSYS_WR_REG_LL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LL_MASK, RFSYS_REG_LL(value)))
+#define RFSYS_BWR_REG_LL(base, index, value) (RFSYS_WR_REG_LL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LH field. */
+#define RFSYS_RD_REG_LH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LH_MASK) >> RFSYS_REG_LH_SHIFT)
+#define RFSYS_BRD_REG_LH(base, index) (RFSYS_RD_REG_LH(base, index))
+
+/*! @brief Set the LH field to a new value. */
+#define RFSYS_WR_REG_LH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LH_MASK, RFSYS_REG_LH(value)))
+#define RFSYS_BWR_REG_LH(base, index, value) (RFSYS_WR_REG_LH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HL field. */
+#define RFSYS_RD_REG_HL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HL_MASK) >> RFSYS_REG_HL_SHIFT)
+#define RFSYS_BRD_REG_HL(base, index) (RFSYS_RD_REG_HL(base, index))
+
+/*! @brief Set the HL field to a new value. */
+#define RFSYS_WR_REG_HL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HL_MASK, RFSYS_REG_HL(value)))
+#define RFSYS_BWR_REG_HL(base, index, value) (RFSYS_WR_REG_HL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HH field. */
+#define RFSYS_RD_REG_HH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HH_MASK) >> RFSYS_REG_HH_SHIFT)
+#define RFSYS_BRD_REG_HH(base, index) (RFSYS_RD_REG_HH(base, index))
+
+/*! @brief Set the HH field to a new value. */
+#define RFSYS_WR_REG_HH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HH_MASK, RFSYS_REG_HH(value)))
+#define RFSYS_BWR_REG_HH(base, index, value) (RFSYS_WR_REG_HH(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 RFVBAT
+ *
+ * VBAT register file
+ *
+ * Registers defined in this header file:
+ * - RFVBAT_REG - VBAT register file register
+ */
+
+#define RFVBAT_INSTANCE_COUNT (1U) /*!< Number of instances of the RFVBAT module. */
+#define RFVBAT_IDX (0U) /*!< Instance number for RFVBAT. */
+
+/*******************************************************************************
+ * RFVBAT_REG - VBAT register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFVBAT_REG - VBAT register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFVBAT_REG register
+ */
+/*@{*/
+#define RFVBAT_RD_REG(base, index) (RFVBAT_REG_REG(base, index))
+#define RFVBAT_WR_REG(base, index, value) (RFVBAT_REG_REG(base, index) = (value))
+#define RFVBAT_RMW_REG(base, index, mask, value) (RFVBAT_WR_REG(base, index, (RFVBAT_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFVBAT_SET_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) |  (value)))
+#define RFVBAT_CLR_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) & ~(value)))
+#define RFVBAT_TOG_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFVBAT_REG bitfields
+ */
+
+/*!
+ * @name Register RFVBAT_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_LL field. */
+#define RFVBAT_RD_REG_LL(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_LL_MASK) >> RFVBAT_REG_LL_SHIFT)
+#define RFVBAT_BRD_REG_LL(base, index) (RFVBAT_RD_REG_LL(base, index))
+
+/*! @brief Set the LL field to a new value. */
+#define RFVBAT_WR_REG_LL(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_LL_MASK, RFVBAT_REG_LL(value)))
+#define RFVBAT_BWR_REG_LL(base, index, value) (RFVBAT_WR_REG_LL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_LH field. */
+#define RFVBAT_RD_REG_LH(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_LH_MASK) >> RFVBAT_REG_LH_SHIFT)
+#define RFVBAT_BRD_REG_LH(base, index) (RFVBAT_RD_REG_LH(base, index))
+
+/*! @brief Set the LH field to a new value. */
+#define RFVBAT_WR_REG_LH(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_LH_MASK, RFVBAT_REG_LH(value)))
+#define RFVBAT_BWR_REG_LH(base, index, value) (RFVBAT_WR_REG_LH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_HL field. */
+#define RFVBAT_RD_REG_HL(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_HL_MASK) >> RFVBAT_REG_HL_SHIFT)
+#define RFVBAT_BRD_REG_HL(base, index) (RFVBAT_RD_REG_HL(base, index))
+
+/*! @brief Set the HL field to a new value. */
+#define RFVBAT_WR_REG_HL(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_HL_MASK, RFVBAT_REG_HL(value)))
+#define RFVBAT_BWR_REG_HL(base, index, value) (RFVBAT_WR_REG_HL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_HH field. */
+#define RFVBAT_RD_REG_HH(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_HH_MASK) >> RFVBAT_REG_HH_SHIFT)
+#define RFVBAT_BRD_REG_HH(base, index) (RFVBAT_RD_REG_HH(base, index))
+
+/*! @brief Set the HH field to a new value. */
+#define RFVBAT_WR_REG_HH(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_HH_MASK, RFVBAT_REG_HH(value)))
+#define RFVBAT_BWR_REG_HH(base, index, value) (RFVBAT_WR_REG_HH(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 RNG
+ *
+ * Random Number Generator Accelerator
+ *
+ * Registers defined in this header file:
+ * - RNG_CR - RNGA Control Register
+ * - RNG_SR - RNGA Status Register
+ * - RNG_ER - RNGA Entropy Register
+ * - RNG_OR - RNGA Output Register
+ */
+
+#define RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
+#define RNG_IDX (0U) /*!< Instance number for RNG. */
+
+/*******************************************************************************
+ * RNG_CR - RNGA Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_CR - RNGA Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the operation of RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_CR register
+ */
+/*@{*/
+#define RNG_RD_CR(base)          (RNG_CR_REG(base))
+#define RNG_WR_CR(base, value)   (RNG_CR_REG(base) = (value))
+#define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value)))
+#define RNG_SET_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) |  (value)))
+#define RNG_CLR_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) & ~(value)))
+#define RNG_TOG_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RNG_CR bitfields
+ */
+
+/*!
+ * @name Register RNG_CR, field GO[0] (RW)
+ *
+ * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
+ * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
+ * OR[RANDOUT] with data.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_GO field. */
+#define RNG_RD_CR_GO(base)   ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT)
+#define RNG_BRD_CR_GO(base)  (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_GO_SHIFT))
+
+/*! @brief Set the GO field to a new value. */
+#define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value)))
+#define RNG_BWR_CR_GO(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_GO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field HA[1] (RW)
+ *
+ * Enables notification of security violations (via SR[SECV]). A security
+ * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
+ * After enabling notification of security violations, you must reset RNGA to
+ * disable them again.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_HA field. */
+#define RNG_RD_CR_HA(base)   ((RNG_CR_REG(base) & RNG_CR_HA_MASK) >> RNG_CR_HA_SHIFT)
+#define RNG_BRD_CR_HA(base)  (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_HA_SHIFT))
+
+/*! @brief Set the HA field to a new value. */
+#define RNG_WR_CR_HA(base, value) (RNG_RMW_CR(base, RNG_CR_HA_MASK, RNG_CR_HA(value)))
+#define RNG_BWR_CR_HA(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_HA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field INTM[2] (RW)
+ *
+ * Masks the triggering of an error interrupt to the interrupt controller when
+ * an OR underflow condition occurs. An OR underflow condition occurs when you
+ * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
+ *
+ * Values:
+ * - 0b0 - Not masked
+ * - 0b1 - Masked
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_INTM field. */
+#define RNG_RD_CR_INTM(base) ((RNG_CR_REG(base) & RNG_CR_INTM_MASK) >> RNG_CR_INTM_SHIFT)
+#define RNG_BRD_CR_INTM(base) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_INTM_SHIFT))
+
+/*! @brief Set the INTM field to a new value. */
+#define RNG_WR_CR_INTM(base, value) (RNG_RMW_CR(base, RNG_CR_INTM_MASK, RNG_CR_INTM(value)))
+#define RNG_BWR_CR_INTM(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_INTM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field CLRI[3] (WORZ)
+ *
+ * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
+ *
+ * Values:
+ * - 0b0 - Do not clear the interrupt.
+ * - 0b1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
+ *     the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
+ */
+/*@{*/
+/*! @brief Set the CLRI field to a new value. */
+#define RNG_WR_CR_CLRI(base, value) (RNG_RMW_CR(base, RNG_CR_CLRI_MASK, RNG_CR_CLRI(value)))
+#define RNG_BWR_CR_CLRI(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_CLRI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field SLP[4] (RW)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_SLP field. */
+#define RNG_RD_CR_SLP(base)  ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT)
+#define RNG_BRD_CR_SLP(base) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_SLP_SHIFT))
+
+/*! @brief Set the SLP field to a new value. */
+#define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value)))
+#define RNG_BWR_CR_SLP(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_SLP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_SR - RNGA Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_SR - RNGA Status Register (RO)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Indicates the status of RNGA. This register is read-only.
+ */
+/*!
+ * @name Constants and macros for entire RNG_SR register
+ */
+/*@{*/
+#define RNG_RD_SR(base)          (RNG_SR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RNG_SR bitfields
+ */
+
+/*!
+ * @name Register RNG_SR, field SECV[0] (RO)
+ *
+ * Used only when high assurance is enabled (CR[HA]). Indicates that a security
+ * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
+ * RNGA.
+ *
+ * Values:
+ * - 0b0 - No security violation
+ * - 0b1 - Security violation
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SECV field. */
+#define RNG_RD_SR_SECV(base) ((RNG_SR_REG(base) & RNG_SR_SECV_MASK) >> RNG_SR_SECV_SHIFT)
+#define RNG_BRD_SR_SECV(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_SECV_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field LRS[1] (RO)
+ *
+ * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
+ * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
+ * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
+ * After you read this register, RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_LRS field. */
+#define RNG_RD_SR_LRS(base)  ((RNG_SR_REG(base) & RNG_SR_LRS_MASK) >> RNG_SR_LRS_SHIFT)
+#define RNG_BRD_SR_LRS(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_LRS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field ORU[2] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last read
+ * this register (SR) or RNGA was reset, regardless of whether the error
+ * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
+ * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
+ * field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_ORU field. */
+#define RNG_RD_SR_ORU(base)  ((RNG_SR_REG(base) & RNG_SR_ORU_MASK) >> RNG_SR_ORU_SHIFT)
+#define RNG_BRD_SR_ORU(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_ORU_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field ERRI[3] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last
+ * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
+ * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
+ * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
+ * indicator (via CR[CLRI]), RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_ERRI field. */
+#define RNG_RD_SR_ERRI(base) ((RNG_SR_REG(base) & RNG_SR_ERRI_MASK) >> RNG_SR_ERRI_SHIFT)
+#define RNG_BRD_SR_ERRI(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_ERRI_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field SLP[4] (RO)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SLP field. */
+#define RNG_RD_SR_SLP(base)  ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT)
+#define RNG_BRD_SR_SLP(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_SLP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
+ *
+ * Indicates the number of random-data words that are in OR[RANDOUT], which
+ * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
+ * is not 0, then the contents of a random number contained in OR[RANDOUT] are
+ * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
+ *
+ * Values:
+ * - 0b00000000 - No words (empty)
+ * - 0b00000001 - One word (valid)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_LVL field. */
+#define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT)
+#define RNG_BRD_SR_OREG_LVL(base) (RNG_RD_SR_OREG_LVL(base))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
+ *
+ * Indicates the size of the Output (OR) register in terms of the number of
+ * 32-bit random-data words it can hold.
+ *
+ * Values:
+ * - 0b00000001 - One word (this value is fixed)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
+#define RNG_RD_SR_OREG_SIZE(base) ((RNG_SR_REG(base) & RNG_SR_OREG_SIZE_MASK) >> RNG_SR_OREG_SIZE_SHIFT)
+#define RNG_BRD_SR_OREG_SIZE(base) (RNG_RD_SR_OREG_SIZE(base))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_ER - RNGA Entropy Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_ER - RNGA Entropy Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies an entropy value that RNGA uses in addition to its ring oscillators
+ * to seed its pseudorandom algorithm. This is a write-only register; reads
+ * return all zeros.
+ */
+/*!
+ * @name Constants and macros for entire RNG_ER register
+ */
+/*@{*/
+#define RNG_RD_ER(base)          (RNG_ER_REG(base))
+#define RNG_WR_ER(base, value)   (RNG_ER_REG(base) = (value))
+#define RNG_RMW_ER(base, mask, value) (RNG_WR_ER(base, (RNG_RD_ER(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_OR - RNGA Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_OR - RNGA Output Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Stores a random-data word generated by RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_OR register
+ */
+/*@{*/
+#define RNG_RD_OR(base)          (RNG_OR_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 RTC
+ *
+ * Secure Real Time Clock
+ *
+ * Registers defined in this header file:
+ * - RTC_TSR - RTC Time Seconds Register
+ * - RTC_TPR - RTC Time Prescaler Register
+ * - RTC_TAR - RTC Time Alarm Register
+ * - RTC_TCR - RTC Time Compensation Register
+ * - RTC_CR - RTC Control Register
+ * - RTC_SR - RTC Status Register
+ * - RTC_LR - RTC Lock Register
+ * - RTC_IER - RTC Interrupt Enable Register
+ * - RTC_WAR - RTC Write Access Register
+ * - RTC_RAR - RTC Read Access Register
+ */
+
+#define RTC_INSTANCE_COUNT (1U) /*!< Number of instances of the RTC module. */
+#define RTC_IDX (0U) /*!< Instance number for RTC. */
+
+/*******************************************************************************
+ * RTC_TSR - RTC Time Seconds Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TSR - RTC Time Seconds Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TSR register
+ */
+/*@{*/
+#define RTC_RD_TSR(base)         (RTC_TSR_REG(base))
+#define RTC_WR_TSR(base, value)  (RTC_TSR_REG(base) = (value))
+#define RTC_RMW_TSR(base, mask, value) (RTC_WR_TSR(base, (RTC_RD_TSR(base) & ~(mask)) | (value)))
+#define RTC_SET_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) |  (value)))
+#define RTC_CLR_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) & ~(value)))
+#define RTC_TOG_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TPR - RTC Time Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TPR - RTC Time Prescaler Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TPR register
+ */
+/*@{*/
+#define RTC_RD_TPR(base)         (RTC_TPR_REG(base))
+#define RTC_WR_TPR(base, value)  (RTC_TPR_REG(base) = (value))
+#define RTC_RMW_TPR(base, mask, value) (RTC_WR_TPR(base, (RTC_RD_TPR(base) & ~(mask)) | (value)))
+#define RTC_SET_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) |  (value)))
+#define RTC_CLR_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) & ~(value)))
+#define RTC_TOG_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TPR bitfields
+ */
+
+/*!
+ * @name Register RTC_TPR, field TPR[15:0] (RW)
+ *
+ * When the time counter is enabled, the TPR is read only and increments every
+ * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
+ * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
+ * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
+ * to a logic zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TPR_TPR field. */
+#define RTC_RD_TPR_TPR(base) ((RTC_TPR_REG(base) & RTC_TPR_TPR_MASK) >> RTC_TPR_TPR_SHIFT)
+#define RTC_BRD_TPR_TPR(base) (RTC_RD_TPR_TPR(base))
+
+/*! @brief Set the TPR field to a new value. */
+#define RTC_WR_TPR_TPR(base, value) (RTC_RMW_TPR(base, RTC_TPR_TPR_MASK, RTC_TPR_TPR(value)))
+#define RTC_BWR_TPR_TPR(base, value) (RTC_WR_TPR_TPR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TAR - RTC Time Alarm Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TAR - RTC Time Alarm Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TAR register
+ */
+/*@{*/
+#define RTC_RD_TAR(base)         (RTC_TAR_REG(base))
+#define RTC_WR_TAR(base, value)  (RTC_TAR_REG(base) = (value))
+#define RTC_RMW_TAR(base, mask, value) (RTC_WR_TAR(base, (RTC_RD_TAR(base) & ~(mask)) | (value)))
+#define RTC_SET_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) |  (value)))
+#define RTC_CLR_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) & ~(value)))
+#define RTC_TOG_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TCR - RTC Time Compensation Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TCR - RTC Time Compensation Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TCR register
+ */
+/*@{*/
+#define RTC_RD_TCR(base)         (RTC_TCR_REG(base))
+#define RTC_WR_TCR(base, value)  (RTC_TCR_REG(base) = (value))
+#define RTC_RMW_TCR(base, mask, value) (RTC_WR_TCR(base, (RTC_RD_TCR(base) & ~(mask)) | (value)))
+#define RTC_SET_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) |  (value)))
+#define RTC_CLR_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) & ~(value)))
+#define RTC_TOG_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TCR bitfields
+ */
+
+/*!
+ * @name Register RTC_TCR, field TCR[7:0] (RW)
+ *
+ * Configures the number of 32.768 kHz clock cycles in each second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ *
+ * Values:
+ * - 0b10000000 - Time Prescaler Register overflows every 32896 clock cycles.
+ * - 0b11111111 - Time Prescaler Register overflows every 32769 clock cycles.
+ * - 0b00000000 - Time Prescaler Register overflows every 32768 clock cycles.
+ * - 0b00000001 - Time Prescaler Register overflows every 32767 clock cycles.
+ * - 0b01111111 - Time Prescaler Register overflows every 32641 clock cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCR field. */
+#define RTC_RD_TCR_TCR(base) ((RTC_TCR_REG(base) & RTC_TCR_TCR_MASK) >> RTC_TCR_TCR_SHIFT)
+#define RTC_BRD_TCR_TCR(base) (RTC_RD_TCR_TCR(base))
+
+/*! @brief Set the TCR field to a new value. */
+#define RTC_WR_TCR_TCR(base, value) (RTC_RMW_TCR(base, RTC_TCR_TCR_MASK, RTC_TCR_TCR(value)))
+#define RTC_BWR_TCR_TCR(base, value) (RTC_WR_TCR_TCR(base, value))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIR[15:8] (RW)
+ *
+ * Configures the compensation interval in seconds from 1 to 256 to control how
+ * frequently the TCR should adjust the number of 32.768 kHz cycles in each
+ * second. The value written should be one less than the number of seconds. For
+ * example, write zero to configure for a compensation interval of one second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIR field. */
+#define RTC_RD_TCR_CIR(base) ((RTC_TCR_REG(base) & RTC_TCR_CIR_MASK) >> RTC_TCR_CIR_SHIFT)
+#define RTC_BRD_TCR_CIR(base) (RTC_RD_TCR_CIR(base))
+
+/*! @brief Set the CIR field to a new value. */
+#define RTC_WR_TCR_CIR(base, value) (RTC_RMW_TCR(base, RTC_TCR_CIR_MASK, RTC_TCR_CIR(value)))
+#define RTC_BWR_TCR_CIR(base, value) (RTC_WR_TCR_CIR(base, value))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field TCV[23:16] (RO)
+ *
+ * Current value used by the compensation logic for the present second interval.
+ * Updated once a second if the CIC equals 0 with the contents of the TCR field.
+ * If the CIC does not equal zero then it is loaded with zero (compensation is
+ * not enabled for that second increment).
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCV field. */
+#define RTC_RD_TCR_TCV(base) ((RTC_TCR_REG(base) & RTC_TCR_TCV_MASK) >> RTC_TCR_TCV_SHIFT)
+#define RTC_BRD_TCR_TCV(base) (RTC_RD_TCR_TCV(base))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIC[31:24] (RO)
+ *
+ * Current value of the compensation interval counter. If the compensation
+ * interval counter equals zero then it is loaded with the contents of the CIR. If the
+ * CIC does not equal zero then it is decremented once a second.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIC field. */
+#define RTC_RD_TCR_CIC(base) ((RTC_TCR_REG(base) & RTC_TCR_CIC_MASK) >> RTC_TCR_CIC_SHIFT)
+#define RTC_BRD_TCR_CIC(base) (RTC_RD_TCR_CIC(base))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_CR - RTC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_CR - RTC Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_CR register
+ */
+/*@{*/
+#define RTC_RD_CR(base)          (RTC_CR_REG(base))
+#define RTC_WR_CR(base, value)   (RTC_CR_REG(base) = (value))
+#define RTC_RMW_CR(base, mask, value) (RTC_WR_CR(base, (RTC_RD_CR(base) & ~(mask)) | (value)))
+#define RTC_SET_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) |  (value)))
+#define RTC_CLR_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) & ~(value)))
+#define RTC_TOG_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_CR bitfields
+ */
+
+/*!
+ * @name Register RTC_CR, field SWR[0] (RW)
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
+ *     RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
+ *     explicitly clearing it.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SWR field. */
+#define RTC_RD_CR_SWR(base)  ((RTC_CR_REG(base) & RTC_CR_SWR_MASK) >> RTC_CR_SWR_SHIFT)
+#define RTC_BRD_CR_SWR(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT))
+
+/*! @brief Set the SWR field to a new value. */
+#define RTC_WR_CR_SWR(base, value) (RTC_RMW_CR(base, RTC_CR_SWR_MASK, RTC_CR_SWR(value)))
+#define RTC_BWR_CR_SWR(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPE[1] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0b0 - Wakeup pin is disabled.
+ * - 0b1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPE field. */
+#define RTC_RD_CR_WPE(base)  ((RTC_CR_REG(base) & RTC_CR_WPE_MASK) >> RTC_CR_WPE_SHIFT)
+#define RTC_BRD_CR_WPE(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT))
+
+/*! @brief Set the WPE field to a new value. */
+#define RTC_WR_CR_WPE(base, value) (RTC_RMW_CR(base, RTC_CR_WPE_MASK, RTC_CR_WPE(value)))
+#define RTC_BWR_CR_WPE(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SUP[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Non-supervisor mode write accesses are not supported and generate a
+ *     bus error.
+ * - 0b1 - Non-supervisor mode write accesses are supported.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SUP field. */
+#define RTC_RD_CR_SUP(base)  ((RTC_CR_REG(base) & RTC_CR_SUP_MASK) >> RTC_CR_SUP_SHIFT)
+#define RTC_BRD_CR_SUP(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT))
+
+/*! @brief Set the SUP field to a new value. */
+#define RTC_WR_CR_SUP(base, value) (RTC_RMW_CR(base, RTC_CR_SUP_MASK, RTC_CR_SUP(value)))
+#define RTC_BWR_CR_SUP(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field UM[3] (RW)
+ *
+ * Allows SR[TCE] to be written even when the Status Register is locked. When
+ * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
+ * the SR[TCE] is clear.
+ *
+ * Values:
+ * - 0b0 - Registers cannot be written when locked.
+ * - 0b1 - Registers can be written when locked under limited conditions.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_UM field. */
+#define RTC_RD_CR_UM(base)   ((RTC_CR_REG(base) & RTC_CR_UM_MASK) >> RTC_CR_UM_SHIFT)
+#define RTC_BRD_CR_UM(base)  (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT))
+
+/*! @brief Set the UM field to a new value. */
+#define RTC_WR_CR_UM(base, value) (RTC_RMW_CR(base, RTC_CR_UM_MASK, RTC_CR_UM(value)))
+#define RTC_BWR_CR_UM(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPS[4] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0b0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ * - 0b1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup
+ *     pin is turned on and the 32kHz clock is output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPS field. */
+#define RTC_RD_CR_WPS(base)  ((RTC_CR_REG(base) & RTC_CR_WPS_MASK) >> RTC_CR_WPS_SHIFT)
+#define RTC_BRD_CR_WPS(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT))
+
+/*! @brief Set the WPS field to a new value. */
+#define RTC_WR_CR_WPS(base, value) (RTC_RMW_CR(base, RTC_CR_WPS_MASK, RTC_CR_WPS(value)))
+#define RTC_BWR_CR_WPS(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field OSCE[8] (RW)
+ *
+ * Values:
+ * - 0b0 - 32.768 kHz oscillator is disabled.
+ * - 0b1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
+ *     oscillator startup time before enabling the time counter to allow the 32.768
+ *     kHz clock time to stabilize.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_OSCE field. */
+#define RTC_RD_CR_OSCE(base) ((RTC_CR_REG(base) & RTC_CR_OSCE_MASK) >> RTC_CR_OSCE_SHIFT)
+#define RTC_BRD_CR_OSCE(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT))
+
+/*! @brief Set the OSCE field to a new value. */
+#define RTC_WR_CR_OSCE(base, value) (RTC_RMW_CR(base, RTC_CR_OSCE_MASK, RTC_CR_OSCE(value)))
+#define RTC_BWR_CR_OSCE(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field CLKO[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The 32 kHz clock is output to other peripherals.
+ * - 0b1 - The 32 kHz clock is not output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_CLKO field. */
+#define RTC_RD_CR_CLKO(base) ((RTC_CR_REG(base) & RTC_CR_CLKO_MASK) >> RTC_CR_CLKO_SHIFT)
+#define RTC_BRD_CR_CLKO(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT))
+
+/*! @brief Set the CLKO field to a new value. */
+#define RTC_WR_CR_CLKO(base, value) (RTC_RMW_CR(base, RTC_CR_CLKO_MASK, RTC_CR_CLKO(value)))
+#define RTC_BWR_CR_CLKO(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC16P[10] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC16P field. */
+#define RTC_RD_CR_SC16P(base) ((RTC_CR_REG(base) & RTC_CR_SC16P_MASK) >> RTC_CR_SC16P_SHIFT)
+#define RTC_BRD_CR_SC16P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT))
+
+/*! @brief Set the SC16P field to a new value. */
+#define RTC_WR_CR_SC16P(base, value) (RTC_RMW_CR(base, RTC_CR_SC16P_MASK, RTC_CR_SC16P(value)))
+#define RTC_BWR_CR_SC16P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC8P[11] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC8P field. */
+#define RTC_RD_CR_SC8P(base) ((RTC_CR_REG(base) & RTC_CR_SC8P_MASK) >> RTC_CR_SC8P_SHIFT)
+#define RTC_BRD_CR_SC8P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT))
+
+/*! @brief Set the SC8P field to a new value. */
+#define RTC_WR_CR_SC8P(base, value) (RTC_RMW_CR(base, RTC_CR_SC8P_MASK, RTC_CR_SC8P(value)))
+#define RTC_BWR_CR_SC8P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC4P[12] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC4P field. */
+#define RTC_RD_CR_SC4P(base) ((RTC_CR_REG(base) & RTC_CR_SC4P_MASK) >> RTC_CR_SC4P_SHIFT)
+#define RTC_BRD_CR_SC4P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT))
+
+/*! @brief Set the SC4P field to a new value. */
+#define RTC_WR_CR_SC4P(base, value) (RTC_RMW_CR(base, RTC_CR_SC4P_MASK, RTC_CR_SC4P(value)))
+#define RTC_BWR_CR_SC4P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC2P[13] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC2P field. */
+#define RTC_RD_CR_SC2P(base) ((RTC_CR_REG(base) & RTC_CR_SC2P_MASK) >> RTC_CR_SC2P_SHIFT)
+#define RTC_BRD_CR_SC2P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT))
+
+/*! @brief Set the SC2P field to a new value. */
+#define RTC_WR_CR_SC2P(base, value) (RTC_RMW_CR(base, RTC_CR_SC2P_MASK, RTC_CR_SC2P(value)))
+#define RTC_BWR_CR_SC2P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_SR - RTC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_SR - RTC Status Register (RW)
+ *
+ * Reset value: 0x00000001U
+ */
+/*!
+ * @name Constants and macros for entire RTC_SR register
+ */
+/*@{*/
+#define RTC_RD_SR(base)          (RTC_SR_REG(base))
+#define RTC_WR_SR(base, value)   (RTC_SR_REG(base) = (value))
+#define RTC_RMW_SR(base, mask, value) (RTC_WR_SR(base, (RTC_RD_SR(base) & ~(mask)) | (value)))
+#define RTC_SET_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) |  (value)))
+#define RTC_CLR_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) & ~(value)))
+#define RTC_TOG_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_SR bitfields
+ */
+
+/*!
+ * @name Register RTC_SR, field TIF[0] (RO)
+ *
+ * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
+ * do not increment and read as zero when this bit is set. This bit is cleared by
+ * writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0b0 - Time is valid.
+ * - 0b1 - Time is invalid and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TIF field. */
+#define RTC_RD_SR_TIF(base)  ((RTC_SR_REG(base) & RTC_SR_TIF_MASK) >> RTC_SR_TIF_SHIFT)
+#define RTC_BRD_SR_TIF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TIF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TOF[1] (RO)
+ *
+ * Time overflow flag is set when the time counter is enabled and overflows. The
+ * TSR and TPR do not increment and read as zero when this bit is set. This bit
+ * is cleared by writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0b0 - Time overflow has not occurred.
+ * - 0b1 - Time overflow has occurred and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TOF field. */
+#define RTC_RD_SR_TOF(base)  ((RTC_SR_REG(base) & RTC_SR_TOF_MASK) >> RTC_SR_TOF_SHIFT)
+#define RTC_BRD_SR_TOF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TOF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TAF[2] (RO)
+ *
+ * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
+ * increments. This bit is cleared by writing the TAR register.
+ *
+ * Values:
+ * - 0b0 - Time alarm has not occurred.
+ * - 0b1 - Time alarm has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TAF field. */
+#define RTC_RD_SR_TAF(base)  ((RTC_SR_REG(base) & RTC_SR_TAF_MASK) >> RTC_SR_TAF_SHIFT)
+#define RTC_BRD_SR_TAF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TAF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TCE[4] (RW)
+ *
+ * When time counter is disabled the TSR register and TPR register are
+ * writeable, but do not increment. When time counter is enabled the TSR register and TPR
+ * register are not writeable, but increment.
+ *
+ * Values:
+ * - 0b0 - Time counter is disabled.
+ * - 0b1 - Time counter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TCE field. */
+#define RTC_RD_SR_TCE(base)  ((RTC_SR_REG(base) & RTC_SR_TCE_MASK) >> RTC_SR_TCE_SHIFT)
+#define RTC_BRD_SR_TCE(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT))
+
+/*! @brief Set the TCE field to a new value. */
+#define RTC_WR_SR_TCE(base, value) (RTC_RMW_SR(base, RTC_SR_TCE_MASK, RTC_SR_TCE(value)))
+#define RTC_BWR_SR_TCE(base, value) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_LR - RTC Lock Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_LR - RTC Lock Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_LR register
+ */
+/*@{*/
+#define RTC_RD_LR(base)          (RTC_LR_REG(base))
+#define RTC_WR_LR(base, value)   (RTC_LR_REG(base) = (value))
+#define RTC_RMW_LR(base, mask, value) (RTC_WR_LR(base, (RTC_RD_LR(base) & ~(mask)) | (value)))
+#define RTC_SET_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) |  (value)))
+#define RTC_CLR_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) & ~(value)))
+#define RTC_TOG_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_LR bitfields
+ */
+
+/*!
+ * @name Register RTC_LR, field TCL[3] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Time Compensation Register is locked and writes are ignored.
+ * - 0b1 - Time Compensation Register is not locked and writes complete as
+ *     normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_TCL field. */
+#define RTC_RD_LR_TCL(base)  ((RTC_LR_REG(base) & RTC_LR_TCL_MASK) >> RTC_LR_TCL_SHIFT)
+#define RTC_BRD_LR_TCL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT))
+
+/*! @brief Set the TCL field to a new value. */
+#define RTC_WR_LR_TCL(base, value) (RTC_RMW_LR(base, RTC_LR_TCL_MASK, RTC_LR_TCL(value)))
+#define RTC_BWR_LR_TCL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field CRL[4] (RW)
+ *
+ * After being cleared, this bit can only be set by VBAT POR.
+ *
+ * Values:
+ * - 0b0 - Control Register is locked and writes are ignored.
+ * - 0b1 - Control Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_CRL field. */
+#define RTC_RD_LR_CRL(base)  ((RTC_LR_REG(base) & RTC_LR_CRL_MASK) >> RTC_LR_CRL_SHIFT)
+#define RTC_BRD_LR_CRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT))
+
+/*! @brief Set the CRL field to a new value. */
+#define RTC_WR_LR_CRL(base, value) (RTC_RMW_LR(base, RTC_LR_CRL_MASK, RTC_LR_CRL(value)))
+#define RTC_BWR_LR_CRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field SRL[5] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Status Register is locked and writes are ignored.
+ * - 0b1 - Status Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_SRL field. */
+#define RTC_RD_LR_SRL(base)  ((RTC_LR_REG(base) & RTC_LR_SRL_MASK) >> RTC_LR_SRL_SHIFT)
+#define RTC_BRD_LR_SRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT))
+
+/*! @brief Set the SRL field to a new value. */
+#define RTC_WR_LR_SRL(base, value) (RTC_RMW_LR(base, RTC_LR_SRL_MASK, RTC_LR_SRL(value)))
+#define RTC_BWR_LR_SRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field LRL[6] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Lock Register is locked and writes are ignored.
+ * - 0b1 - Lock Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_LRL field. */
+#define RTC_RD_LR_LRL(base)  ((RTC_LR_REG(base) & RTC_LR_LRL_MASK) >> RTC_LR_LRL_SHIFT)
+#define RTC_BRD_LR_LRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT))
+
+/*! @brief Set the LRL field to a new value. */
+#define RTC_WR_LR_LRL(base, value) (RTC_RMW_LR(base, RTC_LR_LRL_MASK, RTC_LR_LRL(value)))
+#define RTC_BWR_LR_LRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_IER - RTC Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_IER - RTC Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00000007U
+ */
+/*!
+ * @name Constants and macros for entire RTC_IER register
+ */
+/*@{*/
+#define RTC_RD_IER(base)         (RTC_IER_REG(base))
+#define RTC_WR_IER(base, value)  (RTC_IER_REG(base) = (value))
+#define RTC_RMW_IER(base, mask, value) (RTC_WR_IER(base, (RTC_RD_IER(base) & ~(mask)) | (value)))
+#define RTC_SET_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) |  (value)))
+#define RTC_CLR_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) & ~(value)))
+#define RTC_TOG_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_IER bitfields
+ */
+
+/*!
+ * @name Register RTC_IER, field TIIE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Time invalid flag does not generate an interrupt.
+ * - 0b1 - Time invalid flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TIIE field. */
+#define RTC_RD_IER_TIIE(base) ((RTC_IER_REG(base) & RTC_IER_TIIE_MASK) >> RTC_IER_TIIE_SHIFT)
+#define RTC_BRD_IER_TIIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT))
+
+/*! @brief Set the TIIE field to a new value. */
+#define RTC_WR_IER_TIIE(base, value) (RTC_RMW_IER(base, RTC_IER_TIIE_MASK, RTC_IER_TIIE(value)))
+#define RTC_BWR_IER_TIIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TOIE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Time overflow flag does not generate an interrupt.
+ * - 0b1 - Time overflow flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TOIE field. */
+#define RTC_RD_IER_TOIE(base) ((RTC_IER_REG(base) & RTC_IER_TOIE_MASK) >> RTC_IER_TOIE_SHIFT)
+#define RTC_BRD_IER_TOIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT))
+
+/*! @brief Set the TOIE field to a new value. */
+#define RTC_WR_IER_TOIE(base, value) (RTC_RMW_IER(base, RTC_IER_TOIE_MASK, RTC_IER_TOIE(value)))
+#define RTC_BWR_IER_TOIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TAIE[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Time alarm flag does not generate an interrupt.
+ * - 0b1 - Time alarm flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TAIE field. */
+#define RTC_RD_IER_TAIE(base) ((RTC_IER_REG(base) & RTC_IER_TAIE_MASK) >> RTC_IER_TAIE_SHIFT)
+#define RTC_BRD_IER_TAIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT))
+
+/*! @brief Set the TAIE field to a new value. */
+#define RTC_WR_IER_TAIE(base, value) (RTC_RMW_IER(base, RTC_IER_TAIE_MASK, RTC_IER_TAIE(value)))
+#define RTC_BWR_IER_TAIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TSIE[4] (RW)
+ *
+ * The seconds interrupt is an edge-sensitive interrupt with a dedicated
+ * interrupt vector. It is generated once a second and requires no software overhead
+ * (there is no corresponding status flag to clear).
+ *
+ * Values:
+ * - 0b0 - Seconds interrupt is disabled.
+ * - 0b1 - Seconds interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TSIE field. */
+#define RTC_RD_IER_TSIE(base) ((RTC_IER_REG(base) & RTC_IER_TSIE_MASK) >> RTC_IER_TSIE_SHIFT)
+#define RTC_BRD_IER_TSIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT))
+
+/*! @brief Set the TSIE field to a new value. */
+#define RTC_WR_IER_TSIE(base, value) (RTC_RMW_IER(base, RTC_IER_TSIE_MASK, RTC_IER_TSIE(value)))
+#define RTC_BWR_IER_TSIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field WPON[7] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices. Whenever the
+ * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - If the wakeup pin is enabled, then the wakeup pin will assert.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_WPON field. */
+#define RTC_RD_IER_WPON(base) ((RTC_IER_REG(base) & RTC_IER_WPON_MASK) >> RTC_IER_WPON_SHIFT)
+#define RTC_BRD_IER_WPON(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT))
+
+/*! @brief Set the WPON field to a new value. */
+#define RTC_WR_IER_WPON(base, value) (RTC_RMW_IER(base, RTC_IER_WPON_MASK, RTC_IER_WPON(value)))
+#define RTC_BWR_IER_WPON(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_WAR - RTC Write Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_WAR - RTC Write Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_WAR register
+ */
+/*@{*/
+#define RTC_RD_WAR(base)         (RTC_WAR_REG(base))
+#define RTC_WR_WAR(base, value)  (RTC_WAR_REG(base) = (value))
+#define RTC_RMW_WAR(base, mask, value) (RTC_WR_WAR(base, (RTC_RD_WAR(base) & ~(mask)) | (value)))
+#define RTC_SET_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) |  (value)))
+#define RTC_CLR_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) & ~(value)))
+#define RTC_TOG_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_WAR bitfields
+ */
+
+/*!
+ * @name Register RTC_WAR, field TSRW[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Seconds Register are ignored.
+ * - 0b1 - Writes to the Time Seconds Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TSRW field. */
+#define RTC_RD_WAR_TSRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TSRW_MASK) >> RTC_WAR_TSRW_SHIFT)
+#define RTC_BRD_WAR_TSRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TSRW_SHIFT))
+
+/*! @brief Set the TSRW field to a new value. */
+#define RTC_WR_WAR_TSRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TSRW_MASK, RTC_WAR_TSRW(value)))
+#define RTC_BWR_WAR_TSRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TSRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TPRW[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Prescaler Register are ignored.
+ * - 0b1 - Writes to the Time Prescaler Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TPRW field. */
+#define RTC_RD_WAR_TPRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TPRW_MASK) >> RTC_WAR_TPRW_SHIFT)
+#define RTC_BRD_WAR_TPRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TPRW_SHIFT))
+
+/*! @brief Set the TPRW field to a new value. */
+#define RTC_WR_WAR_TPRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TPRW_MASK, RTC_WAR_TPRW(value)))
+#define RTC_BWR_WAR_TPRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TPRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TARW[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Alarm Register are ignored.
+ * - 0b1 - Writes to the Time Alarm Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TARW field. */
+#define RTC_RD_WAR_TARW(base) ((RTC_WAR_REG(base) & RTC_WAR_TARW_MASK) >> RTC_WAR_TARW_SHIFT)
+#define RTC_BRD_WAR_TARW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TARW_SHIFT))
+
+/*! @brief Set the TARW field to a new value. */
+#define RTC_WR_WAR_TARW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TARW_MASK, RTC_WAR_TARW(value)))
+#define RTC_BWR_WAR_TARW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TARW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TCRW[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Compensation Register are ignored.
+ * - 0b1 - Writes to the Time Compensation Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TCRW field. */
+#define RTC_RD_WAR_TCRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TCRW_MASK) >> RTC_WAR_TCRW_SHIFT)
+#define RTC_BRD_WAR_TCRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TCRW_SHIFT))
+
+/*! @brief Set the TCRW field to a new value. */
+#define RTC_WR_WAR_TCRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TCRW_MASK, RTC_WAR_TCRW(value)))
+#define RTC_BWR_WAR_TCRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TCRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field CRW[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Control Register are ignored.
+ * - 0b1 - Writes to the Control Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_CRW field. */
+#define RTC_RD_WAR_CRW(base) ((RTC_WAR_REG(base) & RTC_WAR_CRW_MASK) >> RTC_WAR_CRW_SHIFT)
+#define RTC_BRD_WAR_CRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_CRW_SHIFT))
+
+/*! @brief Set the CRW field to a new value. */
+#define RTC_WR_WAR_CRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_CRW_MASK, RTC_WAR_CRW(value)))
+#define RTC_BWR_WAR_CRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_CRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field SRW[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Status Register are ignored.
+ * - 0b1 - Writes to the Status Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_SRW field. */
+#define RTC_RD_WAR_SRW(base) ((RTC_WAR_REG(base) & RTC_WAR_SRW_MASK) >> RTC_WAR_SRW_SHIFT)
+#define RTC_BRD_WAR_SRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_SRW_SHIFT))
+
+/*! @brief Set the SRW field to a new value. */
+#define RTC_WR_WAR_SRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_SRW_MASK, RTC_WAR_SRW(value)))
+#define RTC_BWR_WAR_SRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_SRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field LRW[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Lock Register are ignored.
+ * - 0b1 - Writes to the Lock Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_LRW field. */
+#define RTC_RD_WAR_LRW(base) ((RTC_WAR_REG(base) & RTC_WAR_LRW_MASK) >> RTC_WAR_LRW_SHIFT)
+#define RTC_BRD_WAR_LRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_LRW_SHIFT))
+
+/*! @brief Set the LRW field to a new value. */
+#define RTC_WR_WAR_LRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_LRW_MASK, RTC_WAR_LRW(value)))
+#define RTC_BWR_WAR_LRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_LRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field IERW[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Interupt Enable Register are ignored.
+ * - 0b1 - Writes to the Interrupt Enable Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_IERW field. */
+#define RTC_RD_WAR_IERW(base) ((RTC_WAR_REG(base) & RTC_WAR_IERW_MASK) >> RTC_WAR_IERW_SHIFT)
+#define RTC_BRD_WAR_IERW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_IERW_SHIFT))
+
+/*! @brief Set the IERW field to a new value. */
+#define RTC_WR_WAR_IERW(base, value) (RTC_RMW_WAR(base, RTC_WAR_IERW_MASK, RTC_WAR_IERW(value)))
+#define RTC_BWR_WAR_IERW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_IERW_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_RAR - RTC Read Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_RAR - RTC Read Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_RAR register
+ */
+/*@{*/
+#define RTC_RD_RAR(base)         (RTC_RAR_REG(base))
+#define RTC_WR_RAR(base, value)  (RTC_RAR_REG(base) = (value))
+#define RTC_RMW_RAR(base, mask, value) (RTC_WR_RAR(base, (RTC_RD_RAR(base) & ~(mask)) | (value)))
+#define RTC_SET_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) |  (value)))
+#define RTC_CLR_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) & ~(value)))
+#define RTC_TOG_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_RAR bitfields
+ */
+
+/*!
+ * @name Register RTC_RAR, field TSRR[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Seconds Register are ignored.
+ * - 0b1 - Reads to the Time Seconds Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TSRR field. */
+#define RTC_RD_RAR_TSRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TSRR_MASK) >> RTC_RAR_TSRR_SHIFT)
+#define RTC_BRD_RAR_TSRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TSRR_SHIFT))
+
+/*! @brief Set the TSRR field to a new value. */
+#define RTC_WR_RAR_TSRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TSRR_MASK, RTC_RAR_TSRR(value)))
+#define RTC_BWR_RAR_TSRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TSRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TPRR[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Pprescaler Register are ignored.
+ * - 0b1 - Reads to the Time Prescaler Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TPRR field. */
+#define RTC_RD_RAR_TPRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TPRR_MASK) >> RTC_RAR_TPRR_SHIFT)
+#define RTC_BRD_RAR_TPRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TPRR_SHIFT))
+
+/*! @brief Set the TPRR field to a new value. */
+#define RTC_WR_RAR_TPRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TPRR_MASK, RTC_RAR_TPRR(value)))
+#define RTC_BWR_RAR_TPRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TPRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TARR[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Alarm Register are ignored.
+ * - 0b1 - Reads to the Time Alarm Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TARR field. */
+#define RTC_RD_RAR_TARR(base) ((RTC_RAR_REG(base) & RTC_RAR_TARR_MASK) >> RTC_RAR_TARR_SHIFT)
+#define RTC_BRD_RAR_TARR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TARR_SHIFT))
+
+/*! @brief Set the TARR field to a new value. */
+#define RTC_WR_RAR_TARR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TARR_MASK, RTC_RAR_TARR(value)))
+#define RTC_BWR_RAR_TARR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TARR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TCRR[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Compensation Register are ignored.
+ * - 0b1 - Reads to the Time Compensation Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TCRR field. */
+#define RTC_RD_RAR_TCRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TCRR_MASK) >> RTC_RAR_TCRR_SHIFT)
+#define RTC_BRD_RAR_TCRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TCRR_SHIFT))
+
+/*! @brief Set the TCRR field to a new value. */
+#define RTC_WR_RAR_TCRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TCRR_MASK, RTC_RAR_TCRR(value)))
+#define RTC_BWR_RAR_TCRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TCRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field CRR[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Control Register are ignored.
+ * - 0b1 - Reads to the Control Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_CRR field. */
+#define RTC_RD_RAR_CRR(base) ((RTC_RAR_REG(base) & RTC_RAR_CRR_MASK) >> RTC_RAR_CRR_SHIFT)
+#define RTC_BRD_RAR_CRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_CRR_SHIFT))
+
+/*! @brief Set the CRR field to a new value. */
+#define RTC_WR_RAR_CRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_CRR_MASK, RTC_RAR_CRR(value)))
+#define RTC_BWR_RAR_CRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_CRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field SRR[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Status Register are ignored.
+ * - 0b1 - Reads to the Status Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_SRR field. */
+#define RTC_RD_RAR_SRR(base) ((RTC_RAR_REG(base) & RTC_RAR_SRR_MASK) >> RTC_RAR_SRR_SHIFT)
+#define RTC_BRD_RAR_SRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_SRR_SHIFT))
+
+/*! @brief Set the SRR field to a new value. */
+#define RTC_WR_RAR_SRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_SRR_MASK, RTC_RAR_SRR(value)))
+#define RTC_BWR_RAR_SRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_SRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field LRR[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Lock Register are ignored.
+ * - 0b1 - Reads to the Lock Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_LRR field. */
+#define RTC_RD_RAR_LRR(base) ((RTC_RAR_REG(base) & RTC_RAR_LRR_MASK) >> RTC_RAR_LRR_SHIFT)
+#define RTC_BRD_RAR_LRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_LRR_SHIFT))
+
+/*! @brief Set the LRR field to a new value. */
+#define RTC_WR_RAR_LRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_LRR_MASK, RTC_RAR_LRR(value)))
+#define RTC_BWR_RAR_LRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_LRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field IERR[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Interrupt Enable Register are ignored.
+ * - 0b1 - Reads to the Interrupt Enable Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_IERR field. */
+#define RTC_RD_RAR_IERR(base) ((RTC_RAR_REG(base) & RTC_RAR_IERR_MASK) >> RTC_RAR_IERR_SHIFT)
+#define RTC_BRD_RAR_IERR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_IERR_SHIFT))
+
+/*! @brief Set the IERR field to a new value. */
+#define RTC_WR_RAR_IERR(base, value) (RTC_RMW_RAR(base, RTC_RAR_IERR_MASK, RTC_RAR_IERR(value)))
+#define RTC_BWR_RAR_IERR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_IERR_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 SDHC
+ *
+ * Secured Digital Host Controller
+ *
+ * Registers defined in this header file:
+ * - SDHC_DSADDR - DMA System Address register
+ * - SDHC_BLKATTR - Block Attributes register
+ * - SDHC_CMDARG - Command Argument register
+ * - SDHC_XFERTYP - Transfer Type register
+ * - SDHC_CMDRSP - Command Response 0
+ * - SDHC_DATPORT - Buffer Data Port register
+ * - SDHC_PRSSTAT - Present State register
+ * - SDHC_PROCTL - Protocol Control register
+ * - SDHC_SYSCTL - System Control register
+ * - SDHC_IRQSTAT - Interrupt Status register
+ * - SDHC_IRQSTATEN - Interrupt Status Enable register
+ * - SDHC_IRQSIGEN - Interrupt Signal Enable register
+ * - SDHC_AC12ERR - Auto CMD12 Error Status Register
+ * - SDHC_HTCAPBLT - Host Controller Capabilities
+ * - SDHC_WML - Watermark Level Register
+ * - SDHC_FEVT - Force Event register
+ * - SDHC_ADMAES - ADMA Error Status register
+ * - SDHC_ADSADDR - ADMA System Addressregister
+ * - SDHC_VENDOR - Vendor Specific register
+ * - SDHC_MMCBOOT - MMC Boot register
+ * - SDHC_HOSTVER - Host Controller Version
+ */
+
+#define SDHC_INSTANCE_COUNT (1U) /*!< Number of instances of the SDHC module. */
+#define SDHC_IDX (0U) /*!< Instance number for SDHC. */
+
+/*******************************************************************************
+ * SDHC_DSADDR - DMA System Address register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_DSADDR - DMA System Address register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for DMA
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_DSADDR register
+ */
+/*@{*/
+#define SDHC_RD_DSADDR(base)     (SDHC_DSADDR_REG(base))
+#define SDHC_WR_DSADDR(base, value) (SDHC_DSADDR_REG(base) = (value))
+#define SDHC_RMW_DSADDR(base, mask, value) (SDHC_WR_DSADDR(base, (SDHC_RD_DSADDR(base) & ~(mask)) | (value)))
+#define SDHC_SET_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) |  (value)))
+#define SDHC_CLR_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) & ~(value)))
+#define SDHC_TOG_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_DSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
+ *
+ * Contains the 32-bit system memory address for a DMA transfer. Because the
+ * address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
+ * When the SDHC stops a DMA transfer, this register points to the system address
+ * of the next contiguous data position. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read operation
+ * during transfers may return an invalid value. The host driver shall initialize
+ * this register before starting a DMA transaction. After DMA has stopped, the
+ * system address of the next contiguous data position can be read from this register.
+ * This register is protected during a data transfer. When data lines are
+ * active, write to this register is ignored. The host driver shall wait, until
+ * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
+ * not support a virtual memory system. It supports only continuous physical
+ * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
+ * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
+ * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
+ * automatically alters the value of internal address counter, so SW cannot
+ * change this register when IRQSTAT[TC] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_DSADDR_DSADDR field. */
+#define SDHC_RD_DSADDR_DSADDR(base) ((SDHC_DSADDR_REG(base) & SDHC_DSADDR_DSADDR_MASK) >> SDHC_DSADDR_DSADDR_SHIFT)
+#define SDHC_BRD_DSADDR_DSADDR(base) (SDHC_RD_DSADDR_DSADDR(base))
+
+/*! @brief Set the DSADDR field to a new value. */
+#define SDHC_WR_DSADDR_DSADDR(base, value) (SDHC_RMW_DSADDR(base, SDHC_DSADDR_DSADDR_MASK, SDHC_DSADDR_DSADDR(value)))
+#define SDHC_BWR_DSADDR_DSADDR(base, value) (SDHC_WR_DSADDR_DSADDR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_BLKATTR - Block Attributes register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_BLKATTR - Block Attributes register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to configure the number of data blocks and the number
+ * of bytes in each block.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_BLKATTR register
+ */
+/*@{*/
+#define SDHC_RD_BLKATTR(base)    (SDHC_BLKATTR_REG(base))
+#define SDHC_WR_BLKATTR(base, value) (SDHC_BLKATTR_REG(base) = (value))
+#define SDHC_RMW_BLKATTR(base, mask, value) (SDHC_WR_BLKATTR(base, (SDHC_RD_BLKATTR(base) & ~(mask)) | (value)))
+#define SDHC_SET_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) |  (value)))
+#define SDHC_CLR_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) & ~(value)))
+#define SDHC_TOG_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_BLKATTR bitfields
+ */
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
+ *
+ * Specifies the block size for block data transfers. Values ranging from 1 byte
+ * up to the maximum buffer size can be set. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read
+ * operations during transfers may return an invalid value, and write operations will be
+ * ignored.
+ *
+ * Values:
+ * - 0b0000000000000 - No data transfer.
+ * - 0b0000000000001 - 1 Byte
+ * - 0b0000000000010 - 2 Bytes
+ * - 0b0000000000011 - 3 Bytes
+ * - 0b0000000000100 - 4 Bytes
+ * - 0b0000111111111 - 511 Bytes
+ * - 0b0001000000000 - 512 Bytes
+ * - 0b0100000000000 - 2048 Bytes
+ * - 0b1000000000000 - 4096 Bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field. */
+#define SDHC_RD_BLKATTR_BLKSIZE(base) ((SDHC_BLKATTR_REG(base) & SDHC_BLKATTR_BLKSIZE_MASK) >> SDHC_BLKATTR_BLKSIZE_SHIFT)
+#define SDHC_BRD_BLKATTR_BLKSIZE(base) (SDHC_RD_BLKATTR_BLKSIZE(base))
+
+/*! @brief Set the BLKSIZE field to a new value. */
+#define SDHC_WR_BLKATTR_BLKSIZE(base, value) (SDHC_RMW_BLKATTR(base, SDHC_BLKATTR_BLKSIZE_MASK, SDHC_BLKATTR_BLKSIZE(value)))
+#define SDHC_BWR_BLKATTR_BLKSIZE(base, value) (SDHC_WR_BLKATTR_BLKSIZE(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
+ *
+ * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
+ * multiple block transfers. For single block transfer, this register will
+ * always read as 1. The host driver shall set this register to a value between 1 and
+ * the maximum block count. The SDHC decrements the block count after each block
+ * transfer and stops when the count reaches zero. Setting the block count to 0
+ * results in no data blocks being transferred. This register must be accessed
+ * only when no transaction is executing, that is, after transactions are stopped.
+ * During data transfer, read operations on this register may return an invalid
+ * value and write operations are ignored. When saving transfer content as a result
+ * of a suspend command, the number of blocks yet to be transferred can be
+ * determined by reading this register. The reading of this register must be applied
+ * after transfer is paused by stop at block gap operation and before sending the
+ * command marked as suspend. This is because when suspend command is sent out,
+ * SDHC will regard the current transfer as aborted and change BLKCNT back to its
+ * original value instead of keeping the dynamical indicator of remained block
+ * count. When restoring transfer content prior to issuing a resume command, the
+ * host driver shall restore the previously saved block count. Although the BLKCNT
+ * field is 0 after reset, the read of reset value is 0x1. This is because when
+ * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
+ * BLKCNT is always 1.
+ *
+ * Values:
+ * - 0b0000000000000000 - Stop count.
+ * - 0b0000000000000001 - 1 block
+ * - 0b0000000000000010 - 2 blocks
+ * - 0b1111111111111111 - 65535 blocks
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_BLKATTR_BLKCNT field. */
+#define SDHC_RD_BLKATTR_BLKCNT(base) ((SDHC_BLKATTR_REG(base) & SDHC_BLKATTR_BLKCNT_MASK) >> SDHC_BLKATTR_BLKCNT_SHIFT)
+#define SDHC_BRD_BLKATTR_BLKCNT(base) (SDHC_RD_BLKATTR_BLKCNT(base))
+
+/*! @brief Set the BLKCNT field to a new value. */
+#define SDHC_WR_BLKATTR_BLKCNT(base, value) (SDHC_RMW_BLKATTR(base, SDHC_BLKATTR_BLKCNT_MASK, SDHC_BLKATTR_BLKCNT(value)))
+#define SDHC_BWR_BLKATTR_BLKCNT(base, value) (SDHC_WR_BLKATTR_BLKCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_CMDARG - Command Argument register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_CMDARG - Command Argument register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the SD/MMC command argument.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_CMDARG register
+ */
+/*@{*/
+#define SDHC_RD_CMDARG(base)     (SDHC_CMDARG_REG(base))
+#define SDHC_WR_CMDARG(base, value) (SDHC_CMDARG_REG(base) = (value))
+#define SDHC_RMW_CMDARG(base, mask, value) (SDHC_WR_CMDARG(base, (SDHC_RD_CMDARG(base) & ~(mask)) | (value)))
+#define SDHC_SET_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) |  (value)))
+#define SDHC_CLR_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) & ~(value)))
+#define SDHC_TOG_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_XFERTYP - Transfer Type register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_XFERTYP - Transfer Type register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to control the operation of data transfers. The host
+ * driver shall set this register before issuing a command followed by a data
+ * transfer, or before issuing a resume command. To prevent data loss, the SDHC
+ * prevents writing to the bits that are involved in the data transfer of this
+ * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
+ * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
+ * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
+ * send a command with data by writing to this register is ignored; when
+ * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
+ * data transfer involved, it is mandatory that the block size is nonzero.
+ * Besides, block count must also be nonzero, or indicated as single block transfer
+ * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
+ * this register is 0 when written), otherwise SDHC will ignore the sending of
+ * this command and do nothing. For write command, with all above restrictions, it
+ * is also mandatory that the write protect switch is not active (WPSPL bit of
+ * Present State Register is 1), otherwise SDHC will also ignore the command. If
+ * the commands with data transfer does not receive the response in 64 clock
+ * cycles, that is, response time-out, SDHC will regard the external device does not
+ * accept the command and abort the data transfer. In this scenario, the driver
+ * must issue the command again to retry the transfer. It is also possible that,
+ * for some reason, the card responds to the command but SDHC does not receive the
+ * response, and if it is internal DMA (either simple DMA or ADMA) read
+ * operation, the external system memory is over-written by the internal DMA with data
+ * sent back from the card. The following table shows the summary of how register
+ * settings determine the type of data transfer. Transfer Type register setting for
+ * various transfer types Multi/Single block select Block count enable Block
+ * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
+ * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
+ * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
+ * in regards to XFERTYP[RSPTYP] as well as the name of the response type.
+ * Relationship between parameters and the name of the response type Response type
+ * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
+ * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
+ * the SDIO specification, response type notation for R5b is not defined. R5
+ * includes R5b in the SDIO specification. But R5b is defined in this specification
+ * to specify that the SDHC will check the busy status after receiving a
+ * response. For example, usually CMD52 is used with R5, but the I/O abort command shall
+ * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
+ * The CRC check shall be disabled for these response types.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_XFERTYP register
+ */
+/*@{*/
+#define SDHC_RD_XFERTYP(base)    (SDHC_XFERTYP_REG(base))
+#define SDHC_WR_XFERTYP(base, value) (SDHC_XFERTYP_REG(base) = (value))
+#define SDHC_RMW_XFERTYP(base, mask, value) (SDHC_WR_XFERTYP(base, (SDHC_RD_XFERTYP(base) & ~(mask)) | (value)))
+#define SDHC_SET_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) |  (value)))
+#define SDHC_CLR_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) & ~(value)))
+#define SDHC_TOG_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_XFERTYP bitfields
+ */
+
+/*!
+ * @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
+ *
+ * Enables DMA functionality. If this bit is set to 1, a DMA operation shall
+ * begin when the host driver sets the DPSEL bit of this register. Whether the
+ * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DMAEN field. */
+#define SDHC_RD_XFERTYP_DMAEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DMAEN_MASK) >> SDHC_XFERTYP_DMAEN_SHIFT)
+#define SDHC_BRD_XFERTYP_DMAEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define SDHC_WR_XFERTYP_DMAEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DMAEN_MASK, SDHC_XFERTYP_DMAEN(value)))
+#define SDHC_BWR_XFERTYP_DMAEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field BCEN[1] (RW)
+ *
+ * Used to enable the Block Count register, which is only relevant for multiple
+ * block transfers. When this bit is 0, the internal counter for block is
+ * disabled, which is useful in executing an infinite transfer.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_BCEN field. */
+#define SDHC_RD_XFERTYP_BCEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_BCEN_MASK) >> SDHC_XFERTYP_BCEN_SHIFT)
+#define SDHC_BRD_XFERTYP_BCEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_BCEN_SHIFT))
+
+/*! @brief Set the BCEN field to a new value. */
+#define SDHC_WR_XFERTYP_BCEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_BCEN_MASK, SDHC_XFERTYP_BCEN(value)))
+#define SDHC_BWR_XFERTYP_BCEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_BCEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
+ *
+ * Multiple block transfers for memory require a CMD12 to stop the transaction.
+ * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
+ * last block transfer has completed. The host driver shall not set this bit to
+ * issue commands that do not require CMD12 to stop a multiple block data
+ * transfer. In particular, secure commands defined in File Security Specification (see
+ * reference list) do not require CMD12. In single block transfer, the SDHC will
+ * ignore this bit whether it is set or not.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_AC12EN field. */
+#define SDHC_RD_XFERTYP_AC12EN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_AC12EN_MASK) >> SDHC_XFERTYP_AC12EN_SHIFT)
+#define SDHC_BRD_XFERTYP_AC12EN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_AC12EN_SHIFT))
+
+/*! @brief Set the AC12EN field to a new value. */
+#define SDHC_WR_XFERTYP_AC12EN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_AC12EN_MASK, SDHC_XFERTYP_AC12EN(value)))
+#define SDHC_BWR_XFERTYP_AC12EN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_AC12EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
+ *
+ * Defines the direction of DAT line data transfers. The bit is set to 1 by the
+ * host driver to transfer data from the SD card to the SDHC and is set to 0 for
+ * all other commands.
+ *
+ * Values:
+ * - 0b0 - Write host to card.
+ * - 0b1 - Read card to host.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DTDSEL field. */
+#define SDHC_RD_XFERTYP_DTDSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DTDSEL_MASK) >> SDHC_XFERTYP_DTDSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_DTDSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DTDSEL_SHIFT))
+
+/*! @brief Set the DTDSEL field to a new value. */
+#define SDHC_WR_XFERTYP_DTDSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DTDSEL_MASK, SDHC_XFERTYP_DTDSEL(value)))
+#define SDHC_BWR_XFERTYP_DTDSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DTDSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
+ *
+ * Enables multiple block DAT line data transfers. For any other commands, this
+ * bit shall be set to 0. If this bit is 0, it is not necessary to set the block
+ * count register.
+ *
+ * Values:
+ * - 0b0 - Single block.
+ * - 0b1 - Multiple blocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_MSBSEL field. */
+#define SDHC_RD_XFERTYP_MSBSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_MSBSEL_MASK) >> SDHC_XFERTYP_MSBSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_MSBSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_MSBSEL_SHIFT))
+
+/*! @brief Set the MSBSEL field to a new value. */
+#define SDHC_WR_XFERTYP_MSBSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_MSBSEL_MASK, SDHC_XFERTYP_MSBSEL(value)))
+#define SDHC_BWR_XFERTYP_MSBSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_MSBSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
+ *
+ * Values:
+ * - 0b00 - No response.
+ * - 0b01 - Response length 136.
+ * - 0b10 - Response length 48.
+ * - 0b11 - Response length 48, check busy after response.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_RSPTYP field. */
+#define SDHC_RD_XFERTYP_RSPTYP(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_RSPTYP_MASK) >> SDHC_XFERTYP_RSPTYP_SHIFT)
+#define SDHC_BRD_XFERTYP_RSPTYP(base) (SDHC_RD_XFERTYP_RSPTYP(base))
+
+/*! @brief Set the RSPTYP field to a new value. */
+#define SDHC_WR_XFERTYP_RSPTYP(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_RSPTYP_MASK, SDHC_XFERTYP_RSPTYP(value)))
+#define SDHC_BWR_XFERTYP_RSPTYP(base, value) (SDHC_WR_XFERTYP_RSPTYP(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
+ *
+ * If this bit is set to 1, the SDHC shall check the CRC field in the response.
+ * If an error is detected, it is reported as a Command CRC Error. If this bit is
+ * set to 0, the CRC field is not checked. The number of bits checked by the CRC
+ * field value changes according to the length of the response.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CCCEN field. */
+#define SDHC_RD_XFERTYP_CCCEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CCCEN_MASK) >> SDHC_XFERTYP_CCCEN_SHIFT)
+#define SDHC_BRD_XFERTYP_CCCEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CCCEN_SHIFT))
+
+/*! @brief Set the CCCEN field to a new value. */
+#define SDHC_WR_XFERTYP_CCCEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CCCEN_MASK, SDHC_XFERTYP_CCCEN(value)))
+#define SDHC_BWR_XFERTYP_CCCEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CCCEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CICEN[20] (RW)
+ *
+ * If this bit is set to 1, the SDHC will check the index field in the response
+ * to see if it has the same value as the command index. If it is not, it is
+ * reported as a command index error. If this bit is set to 0, the index field is not
+ * checked.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CICEN field. */
+#define SDHC_RD_XFERTYP_CICEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CICEN_MASK) >> SDHC_XFERTYP_CICEN_SHIFT)
+#define SDHC_BRD_XFERTYP_CICEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CICEN_SHIFT))
+
+/*! @brief Set the CICEN field to a new value. */
+#define SDHC_WR_XFERTYP_CICEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CICEN_MASK, SDHC_XFERTYP_CICEN(value)))
+#define SDHC_BWR_XFERTYP_CICEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CICEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
+ *
+ * This bit is set to 1 to indicate that data is present and shall be
+ * transferred using the DAT line. It is set to 0 for the following: Commands using only
+ * the CMD line, for example: CMD52. Commands with no data transfer, but using the
+ * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
+ * this bit shall be set, and other bits in this register shall be set the same
+ * as when the transfer was initially launched. When the Write Protect switch is
+ * on, that is, the WPSPL bit is active as 0, any command with a write operation
+ * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
+ * 0, writes to the register Transfer Type are ignored.
+ *
+ * Values:
+ * - 0b0 - No data present.
+ * - 0b1 - Data present.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DPSEL field. */
+#define SDHC_RD_XFERTYP_DPSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DPSEL_MASK) >> SDHC_XFERTYP_DPSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_DPSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DPSEL_SHIFT))
+
+/*! @brief Set the DPSEL field to a new value. */
+#define SDHC_WR_XFERTYP_DPSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DPSEL_MASK, SDHC_XFERTYP_DPSEL(value)))
+#define SDHC_BWR_XFERTYP_DPSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DPSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
+ *
+ * There are three types of special commands: suspend, resume, and abort. These
+ * bits shall be set to 00b for all other commands. Suspend command: If the
+ * suspend command succeeds, the SDHC shall assume that the card bus has been released
+ * and that it is possible to issue the next command which uses the DAT line.
+ * Because the SDHC does not monitor the content of command response, it does not
+ * know if the suspend command succeeded or not. It is the host driver's
+ * responsibility to check the status of the suspend command and send another command
+ * marked as suspend to inform the SDHC that a suspend command was successfully
+ * issued. After the end bit of command is sent, the SDHC deasserts read wait for read
+ * transactions and stops checking busy for write transactions. In 4-bit mode,
+ * the interrupt cycle starts. If the suspend command fails, the SDHC will
+ * maintain its current state, and the host driver shall restart the transfer by setting
+ * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
+ * restoring the registers saved before sending the suspend command and then sends
+ * the resume command. The SDHC will check for a pending busy state before
+ * starting write transfers. Abort command: If this command is set when executing a
+ * read transfer, the SDHC will stop reads to the buffer. If this command is set
+ * when executing a write transfer, the SDHC will stop driving the DAT line. After
+ * issuing the abort command, the host driver must issue a software reset (abort
+ * transaction).
+ *
+ * Values:
+ * - 0b00 - Normal other commands.
+ * - 0b01 - Suspend CMD52 for writing bus suspend in CCCR.
+ * - 0b10 - Resume CMD52 for writing function select in CCCR.
+ * - 0b11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CMDTYP field. */
+#define SDHC_RD_XFERTYP_CMDTYP(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CMDTYP_MASK) >> SDHC_XFERTYP_CMDTYP_SHIFT)
+#define SDHC_BRD_XFERTYP_CMDTYP(base) (SDHC_RD_XFERTYP_CMDTYP(base))
+
+/*! @brief Set the CMDTYP field to a new value. */
+#define SDHC_WR_XFERTYP_CMDTYP(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CMDTYP_MASK, SDHC_XFERTYP_CMDTYP(value)))
+#define SDHC_BWR_XFERTYP_CMDTYP(base, value) (SDHC_WR_XFERTYP_CMDTYP(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
+ *
+ * These bits shall be set to the command number that is specified in bits 45-40
+ * of the command-format in the SD Memory Card Physical Layer Specification and
+ * SDIO Card Specification.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CMDINX field. */
+#define SDHC_RD_XFERTYP_CMDINX(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CMDINX_MASK) >> SDHC_XFERTYP_CMDINX_SHIFT)
+#define SDHC_BRD_XFERTYP_CMDINX(base) (SDHC_RD_XFERTYP_CMDINX(base))
+
+/*! @brief Set the CMDINX field to a new value. */
+#define SDHC_WR_XFERTYP_CMDINX(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CMDINX_MASK, SDHC_XFERTYP_CMDINX(value)))
+#define SDHC_BWR_XFERTYP_CMDINX(base, value) (SDHC_WR_XFERTYP_CMDINX(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_CMDRSP - Command Response 0
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_CMDRSP - Command Response 0 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 0 of the response bits from the card.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP register
+ */
+/*@{*/
+#define SDHC_RD_CMDRSP(base, index) (SDHC_CMDRSP_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_DATPORT - Buffer Data Port register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_DATPORT - Buffer Data Port register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This is a 32-bit data port register used to access the internal buffer and it
+ * cannot be updated in Idle mode.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_DATPORT register
+ */
+/*@{*/
+#define SDHC_RD_DATPORT(base)    (SDHC_DATPORT_REG(base))
+#define SDHC_WR_DATPORT(base, value) (SDHC_DATPORT_REG(base) = (value))
+#define SDHC_RMW_DATPORT(base, mask, value) (SDHC_WR_DATPORT(base, (SDHC_RD_DATPORT(base) & ~(mask)) | (value)))
+#define SDHC_SET_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) |  (value)))
+#define SDHC_CLR_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) & ~(value)))
+#define SDHC_TOG_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_PRSSTAT - Present State register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_PRSSTAT - Present State register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The host driver can get status of the SDHC from this 32-bit read-only
+ * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
+ * SDIO) when the DAT lines are busy during a data transfer. These commands can be
+ * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
+ * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
+ * Physical Specification may add other commands to this list in the future.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_PRSSTAT register
+ */
+/*@{*/
+#define SDHC_RD_PRSSTAT(base)    (SDHC_PRSSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_PRSSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
+ *
+ * If this status bit is 0, it indicates that the CMD line is not in use and the
+ * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
+ * immediately after the Transfer Type register is written. This bit is cleared when
+ * the command response is received. Even if the CDIHB bit is set to 1, Commands
+ * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
+ * generates a command complete interrupt in the interrupt status register. If the
+ * SDHC cannot issue the command because of a command conflict error (see
+ * command CRC error) or because of a command not issued by auto CMD12 error, this bit
+ * will remain 1 and the command complete is not set. The status of issuing an
+ * auto CMD12 does not show on this bit.
+ *
+ * Values:
+ * - 0b0 - Can issue command using only CMD line.
+ * - 0b1 - Cannot issue command.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CIHB field. */
+#define SDHC_RD_PRSSTAT_CIHB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CIHB_MASK) >> SDHC_PRSSTAT_CIHB_SHIFT)
+#define SDHC_BRD_PRSSTAT_CIHB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CIHB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
+ *
+ * This status bit is generated if either the DLA or the RTA is set to 1. If
+ * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
+ * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
+ * the case when the command busy is finished, changing from 1 to 0 generates a
+ * transfer complete interrupt in the Interrupt Status register. The SD host
+ * driver can save registers for a suspend transaction after this bit has changed
+ * from 1 to 0.
+ *
+ * Values:
+ * - 0b0 - Can issue command which uses the DAT line.
+ * - 0b1 - Cannot issue command which uses the DAT line.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CDIHB field. */
+#define SDHC_RD_PRSSTAT_CDIHB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CDIHB_MASK) >> SDHC_PRSSTAT_CDIHB_SHIFT)
+#define SDHC_BRD_PRSSTAT_CDIHB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CDIHB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLA[2] (RO)
+ *
+ * Indicates whether one of the DAT lines on the SD bus is in use. In the case
+ * of read transactions: This status indicates whether a read transfer is
+ * executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
+ * generates a block gap event interrupt in the Interrupt Status register. This bit
+ * will be set in either of the following cases: After the end bit of the read
+ * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
+ * will be cleared in either of the following cases: When the end bit of the last
+ * data block is sent from the SD bus to the SDHC. When the read wait state is
+ * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
+ * the next block gap by driving read wait at the start of the interrupt cycle.
+ * If the read wait signal is already driven (data buffer cannot receive data),
+ * the SDHC can wait for a current block gap by continuing to drive the read wait
+ * signal. It is necessary to support read wait to use the suspend / resume
+ * function. This bit will remain 1 during read wait. In the case of write
+ * transactions: This status indicates that a write transfer is executing on the SD bus.
+ * Changes in this value from 1 to 0 generate a transfer complete interrupt in the
+ * interrupt status register. This bit will be set in either of the following
+ * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
+ * continue a write transfer. This bit will be cleared in either of the
+ * following cases: When the SD card releases write busy of the last data block, the SDHC
+ * will also detect if the output is not busy. If the SD card does not drive the
+ * busy signal after the CRC status is received, the SDHC shall assume the card
+ * drive "Not busy". When the SD card releases write busy, prior to waiting for
+ * write transfer, and as a result of a stop at block gap request. In the case of
+ * command with busy pending: This status indicates that a busy state follows the
+ * command and the data line is in use. This bit will be cleared when the DAT0
+ * line is released.
+ *
+ * Values:
+ * - 0b0 - DAT line inactive.
+ * - 0b1 - DAT line active.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_DLA field. */
+#define SDHC_RD_PRSSTAT_DLA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_DLA_MASK) >> SDHC_PRSSTAT_DLA_SHIFT)
+#define SDHC_BRD_PRSSTAT_DLA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_DLA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
+ *
+ * Indicates that the internal card clock is stable. This bit is for the host
+ * driver to poll clock status when changing the clock frequency. It is recommended
+ * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
+ * frequency is changing.
+ *
+ * Values:
+ * - 0b0 - Clock is changing frequency and not stable.
+ * - 0b1 - Clock is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_SDSTB field. */
+#define SDHC_RD_PRSSTAT_SDSTB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_SDSTB_MASK) >> SDHC_PRSSTAT_SDSTB_SHIFT)
+#define SDHC_BRD_PRSSTAT_SDSTB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_SDSTB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
+ *
+ * Indicates that the bus clock is internally gated off. This bit is for the
+ * host driver to debug.
+ *
+ * Values:
+ * - 0b0 - Bus clock is active.
+ * - 0b1 - Bus clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field. */
+#define SDHC_RD_PRSSTAT_IPGOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_IPGOFF_MASK) >> SDHC_PRSSTAT_IPGOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_IPGOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_IPGOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
+ *
+ * Indicates that the system clock is internally gated off. This bit is for the
+ * host driver to debug during a data transfer.
+ *
+ * Values:
+ * - 0b0 - System clock is active.
+ * - 0b1 - System clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field. */
+#define SDHC_RD_PRSSTAT_HCKOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_HCKOFF_MASK) >> SDHC_PRSSTAT_HCKOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_HCKOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_HCKOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
+ *
+ * Indicates that the is internally gated off. This bit is for the host driver
+ * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
+ * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
+ * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
+ * clock SDHC clock bus clock
+ *
+ * Values:
+ * - 0b0 - SDHC clock is active.
+ * - 0b1 - SDHC clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_PEROFF field. */
+#define SDHC_RD_PRSSTAT_PEROFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_PEROFF_MASK) >> SDHC_PRSSTAT_PEROFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_PEROFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_PEROFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
+ *
+ * Indicates that the SD clock is internally gated off, because of buffer
+ * over/under-run or read pause without read wait assertion, or the driver has cleared
+ * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
+ * data transaction on the SD bus.
+ *
+ * Values:
+ * - 0b0 - SD clock is active.
+ * - 0b1 - SD clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_SDOFF field. */
+#define SDHC_RD_PRSSTAT_SDOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_SDOFF_MASK) >> SDHC_PRSSTAT_SDOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_SDOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_SDOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field WTA[8] (RO)
+ *
+ * Indicates that a write transfer is active. If this bit is 0, it means no
+ * valid write data exists in the SDHC. This bit is set in either of the following
+ * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
+ * restart a write transfer. This bit is cleared in either of the following
+ * cases: After getting the CRC status of the last data block as specified by the
+ * transfer count (single and multiple). After getting the CRC status of any block
+ * where data transmission is about to be stopped by a stop at block gap request.
+ * During a write transaction, a block gap event interrupt is generated when this
+ * bit is changed to 0, as result of the stop at block gap request being set.
+ * This status is useful for the host driver in determining when to issue commands
+ * during write busy state.
+ *
+ * Values:
+ * - 0b0 - No valid data.
+ * - 0b1 - Transferring data.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_WTA field. */
+#define SDHC_RD_PRSSTAT_WTA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_WTA_MASK) >> SDHC_PRSSTAT_WTA_SHIFT)
+#define SDHC_BRD_PRSSTAT_WTA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_WTA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field RTA[9] (RO)
+ *
+ * Used for detecting completion of a read transfer. This bit is set for either
+ * of the following conditions: After the end bit of the read command. When
+ * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
+ * interrupt is generated when this bit changes to 0. This bit is cleared for either of
+ * the following conditions: When the last data block as specified by block
+ * length is transferred to the system, that is, all data are read away from SDHC
+ * internal buffer. When all valid data blocks have been transferred from SDHC
+ * internal buffer to the system and no current block transfers are being sent as a
+ * result of the stop at block gap request being set to 1.
+ *
+ * Values:
+ * - 0b0 - No valid data.
+ * - 0b1 - Transferring data.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_RTA field. */
+#define SDHC_RD_PRSSTAT_RTA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_RTA_MASK) >> SDHC_PRSSTAT_RTA_SHIFT)
+#define SDHC_BRD_PRSSTAT_RTA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_RTA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
+ *
+ * Used for non-DMA write transfers. The SDHC can implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates whether space is
+ * available for write data. If this bit is 1, valid data greater than the watermark
+ * level can be written to the buffer. This read-only flag indicates whether
+ * space is available for write data.
+ *
+ * Values:
+ * - 0b0 - Write disable, the buffer can hold valid data less than the write
+ *     watermark level.
+ * - 0b1 - Write enable, the buffer can hold valid data greater than the write
+ *     watermark level.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_BWEN field. */
+#define SDHC_RD_PRSSTAT_BWEN(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_BWEN_MASK) >> SDHC_PRSSTAT_BWEN_SHIFT)
+#define SDHC_BRD_PRSSTAT_BWEN(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_BWEN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BREN[11] (RO)
+ *
+ * Used for non-DMA read transfers. The SDHC may implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates that valid data exists
+ * in the host side buffer. If this bit is high, valid data greater than the
+ * watermark level exist in the buffer. This read-only flag indicates that valid
+ * data exists in the host side buffer.
+ *
+ * Values:
+ * - 0b0 - Read disable, valid data less than the watermark level exist in the
+ *     buffer.
+ * - 0b1 - Read enable, valid data greater than the watermark level exist in the
+ *     buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_BREN field. */
+#define SDHC_RD_PRSSTAT_BREN(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_BREN_MASK) >> SDHC_PRSSTAT_BREN_SHIFT)
+#define SDHC_BRD_PRSSTAT_BREN(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_BREN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CINS[16] (RO)
+ *
+ * Indicates whether a card has been inserted. The SDHC debounces this signal so
+ * that the host driver will not need to wait for it to stabilize. Changing from
+ * a 0 to 1 generates a card insertion interrupt in the Interrupt Status
+ * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
+ * Status register. A write to the force event register does not effect this bit.
+ * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
+ * bit.
+ *
+ * Values:
+ * - 0b0 - Power on reset or no card.
+ * - 0b1 - Card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CINS field. */
+#define SDHC_RD_PRSSTAT_CINS(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CINS_MASK) >> SDHC_PRSSTAT_CINS_SHIFT)
+#define SDHC_BRD_PRSSTAT_CINS(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CINS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
+ *
+ * Used to check the CMD line level to recover from errors, and for debugging.
+ * The reset value is effected by the external pullup/pulldown resistor, by
+ * default, the read value of this bit after reset is 1b, when the command line is
+ * pulled up.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CLSL field. */
+#define SDHC_RD_PRSSTAT_CLSL(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CLSL_MASK) >> SDHC_PRSSTAT_CLSL_SHIFT)
+#define SDHC_BRD_PRSSTAT_CLSL(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CLSL_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
+ *
+ * Used to check the DAT line level to recover from errors, and for debugging.
+ * This is especially useful in detecting the busy signal level from DAT[0]. The
+ * reset value is effected by the external pullup/pulldown resistors. By default,
+ * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
+ * down and the other lines are pulled up.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_DLSL field. */
+#define SDHC_RD_PRSSTAT_DLSL(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_DLSL_MASK) >> SDHC_PRSSTAT_DLSL_SHIFT)
+#define SDHC_BRD_PRSSTAT_DLSL(base) (SDHC_RD_PRSSTAT_DLSL(base))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_PROCTL - Protocol Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_PROCTL - Protocol Control register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * There are three cases to restart the transfer after stop at the block gap.
+ * Which case is appropriate depends on whether the SDHC issues a suspend command
+ * or the SD card accepts the suspend command: If the host driver does not issue a
+ * suspend command, the continue request shall be used to restart the transfer.
+ * If the host driver issues a suspend command and the SD card accepts it, a
+ * resume command shall be used to restart the transfer. If the host driver issues a
+ * suspend command and the SD card does not accept it, the continue request shall
+ * be used to restart the transfer. Any time stop at block gap request stops the
+ * data transfer, the host driver shall wait for a transfer complete (in the
+ * interrupt status register), before attempting to restart the transfer. When
+ * restarting the data transfer by continue request, the host driver shall clear the
+ * stop at block gap request before or simultaneously.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_PROCTL register
+ */
+/*@{*/
+#define SDHC_RD_PROCTL(base)     (SDHC_PROCTL_REG(base))
+#define SDHC_WR_PROCTL(base, value) (SDHC_PROCTL_REG(base) = (value))
+#define SDHC_RMW_PROCTL(base, mask, value) (SDHC_WR_PROCTL(base, (SDHC_RD_PROCTL(base) & ~(mask)) | (value)))
+#define SDHC_SET_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) |  (value)))
+#define SDHC_CLR_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) & ~(value)))
+#define SDHC_TOG_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_PROCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_PROCTL, field LCTL[0] (RW)
+ *
+ * This bit, fully controlled by the host driver, is used to caution the user
+ * not to remove the card while the card is being accessed. If the software is
+ * going to issue multiple SD commands, this bit can be set during all these
+ * transactions. It is not necessary to change for each transaction. When the software
+ * issues multiple SD commands, setting the bit once before the first command is
+ * sufficient: it is not necessary to reset the bit between commands.
+ *
+ * Values:
+ * - 0b0 - LED off.
+ * - 0b1 - LED on.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_LCTL field. */
+#define SDHC_RD_PROCTL_LCTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_LCTL_MASK) >> SDHC_PROCTL_LCTL_SHIFT)
+#define SDHC_BRD_PROCTL_LCTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_LCTL_SHIFT))
+
+/*! @brief Set the LCTL field to a new value. */
+#define SDHC_WR_PROCTL_LCTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_LCTL_MASK, SDHC_PROCTL_LCTL(value)))
+#define SDHC_BWR_PROCTL_LCTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_LCTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field DTW[2:1] (RW)
+ *
+ * Selects the data width of the SD bus for a data transfer. The host driver
+ * shall set it to match the data width of the card. Possible data transfer width is
+ * 1-bit, 4-bits or 8-bits.
+ *
+ * Values:
+ * - 0b00 - 1-bit mode
+ * - 0b01 - 4-bit mode
+ * - 0b10 - 8-bit mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_DTW field. */
+#define SDHC_RD_PROCTL_DTW(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_DTW_MASK) >> SDHC_PROCTL_DTW_SHIFT)
+#define SDHC_BRD_PROCTL_DTW(base) (SDHC_RD_PROCTL_DTW(base))
+
+/*! @brief Set the DTW field to a new value. */
+#define SDHC_WR_PROCTL_DTW(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_DTW_MASK, SDHC_PROCTL_DTW(value)))
+#define SDHC_BWR_PROCTL_DTW(base, value) (SDHC_WR_PROCTL_DTW(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field D3CD[3] (RW)
+ *
+ * If this bit is set, DAT3 should be pulled down to act as a card detection
+ * pin. Be cautious when using this feature, because DAT3 is also a chip-select for
+ * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
+ * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
+ * is used.
+ *
+ * Values:
+ * - 0b0 - DAT3 does not monitor card Insertion.
+ * - 0b1 - DAT3 as card detection pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_D3CD field. */
+#define SDHC_RD_PROCTL_D3CD(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_D3CD_MASK) >> SDHC_PROCTL_D3CD_SHIFT)
+#define SDHC_BRD_PROCTL_D3CD(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_D3CD_SHIFT))
+
+/*! @brief Set the D3CD field to a new value. */
+#define SDHC_WR_PROCTL_D3CD(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_D3CD_MASK, SDHC_PROCTL_D3CD(value)))
+#define SDHC_BWR_PROCTL_D3CD(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_D3CD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
+ *
+ * The SDHC supports all four endian modes in data transfer.
+ *
+ * Values:
+ * - 0b00 - Big endian mode
+ * - 0b01 - Half word big endian mode
+ * - 0b10 - Little endian mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_EMODE field. */
+#define SDHC_RD_PROCTL_EMODE(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_EMODE_MASK) >> SDHC_PROCTL_EMODE_SHIFT)
+#define SDHC_BRD_PROCTL_EMODE(base) (SDHC_RD_PROCTL_EMODE(base))
+
+/*! @brief Set the EMODE field to a new value. */
+#define SDHC_WR_PROCTL_EMODE(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_EMODE_MASK, SDHC_PROCTL_EMODE(value)))
+#define SDHC_BWR_PROCTL_EMODE(base, value) (SDHC_WR_PROCTL_EMODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CDTL[6] (RW)
+ *
+ * Enabled while the CDSS is set to 1 and it indicates card insertion.
+ *
+ * Values:
+ * - 0b0 - Card detect test level is 0, no card inserted.
+ * - 0b1 - Card detect test level is 1, card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CDTL field. */
+#define SDHC_RD_PROCTL_CDTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CDTL_MASK) >> SDHC_PROCTL_CDTL_SHIFT)
+#define SDHC_BRD_PROCTL_CDTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDTL_SHIFT))
+
+/*! @brief Set the CDTL field to a new value. */
+#define SDHC_WR_PROCTL_CDTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CDTL_MASK, SDHC_PROCTL_CDTL(value)))
+#define SDHC_BWR_PROCTL_CDTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CDSS[7] (RW)
+ *
+ * Selects the source for the card detection.
+ *
+ * Values:
+ * - 0b0 - Card detection level is selected for normal purpose.
+ * - 0b1 - Card detection test level is selected for test purpose.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CDSS field. */
+#define SDHC_RD_PROCTL_CDSS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CDSS_MASK) >> SDHC_PROCTL_CDSS_SHIFT)
+#define SDHC_BRD_PROCTL_CDSS(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDSS_SHIFT))
+
+/*! @brief Set the CDSS field to a new value. */
+#define SDHC_WR_PROCTL_CDSS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CDSS_MASK, SDHC_PROCTL_CDSS(value)))
+#define SDHC_BWR_PROCTL_CDSS(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDSS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
+ *
+ * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
+ * operation.
+ *
+ * Values:
+ * - 0b00 - No DMA or simple DMA is selected.
+ * - 0b01 - ADMA1 is selected.
+ * - 0b10 - ADMA2 is selected.
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_DMAS field. */
+#define SDHC_RD_PROCTL_DMAS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT)
+#define SDHC_BRD_PROCTL_DMAS(base) (SDHC_RD_PROCTL_DMAS(base))
+
+/*! @brief Set the DMAS field to a new value. */
+#define SDHC_WR_PROCTL_DMAS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_DMAS_MASK, SDHC_PROCTL_DMAS(value)))
+#define SDHC_BWR_PROCTL_DMAS(base, value) (SDHC_WR_PROCTL_DMAS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
+ *
+ * Used to stop executing a transaction at the next block gap for both DMA and
+ * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
+ * transfer completion, the host driver shall leave this bit set to 1. Clearing both
+ * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
+ * Wait is used to stop the read transaction at the block gap. The SDHC will
+ * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
+ * that SDIO card support read wait. Therefore, the host driver shall not set
+ * this bit during read transfers unless the SDIO card supports read wait and has
+ * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
+ * the read operation during block gap. In the case of write transfers in which
+ * the host driver writes data to the data port register, the host driver shall set
+ * this bit after all block data is written. If this bit is set to 1, the host
+ * driver shall not write data to the Data Port register after a block is sent.
+ * Once this bit is set, the host driver shall not clear this bit before
+ * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
+ * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
+ *
+ * Values:
+ * - 0b0 - Transfer
+ * - 0b1 - Stop
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_SABGREQ field. */
+#define SDHC_RD_PROCTL_SABGREQ(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_SABGREQ_MASK) >> SDHC_PROCTL_SABGREQ_SHIFT)
+#define SDHC_BRD_PROCTL_SABGREQ(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_SABGREQ_SHIFT))
+
+/*! @brief Set the SABGREQ field to a new value. */
+#define SDHC_WR_PROCTL_SABGREQ(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_SABGREQ_MASK, SDHC_PROCTL_SABGREQ(value)))
+#define SDHC_BWR_PROCTL_SABGREQ(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_SABGREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CREQ[17] (RW)
+ *
+ * Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
+ * When a suspend operation is not accepted by the card, it is also by setting this
+ * bit to restart the paused transfer. To cancel stop at the block gap, set
+ * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
+ * automatically clears this bit, therefore it is not necessary for the host driver to
+ * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
+ * request is ignored.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Restart
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CREQ field. */
+#define SDHC_RD_PROCTL_CREQ(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CREQ_MASK) >> SDHC_PROCTL_CREQ_SHIFT)
+#define SDHC_BRD_PROCTL_CREQ(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CREQ_SHIFT))
+
+/*! @brief Set the CREQ field to a new value. */
+#define SDHC_WR_PROCTL_CREQ(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CREQ_MASK, SDHC_PROCTL_CREQ(value)))
+#define SDHC_BWR_PROCTL_CREQ(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field RWCTL[18] (RW)
+ *
+ * The read wait function is optional for SDIO cards. If the card supports read
+ * wait, set this bit to enable use of the read wait protocol to stop read data
+ * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
+ * read data, which restricts commands generation. When the host driver detects an
+ * SDIO card insertion, it shall set this bit according to the CCCR of the card.
+ * If the card does not support read wait, this bit shall never be set to 1,
+ * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
+ * during read operation is also supported, but the SDHC will stop the SD Clock
+ * to pause reading operation.
+ *
+ * Values:
+ * - 0b0 - Disable read wait control, and stop SD clock at block gap when
+ *     SABGREQ is set.
+ * - 0b1 - Enable read wait control, and assert read wait without stopping SD
+ *     clock at block gap when SABGREQ bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_RWCTL field. */
+#define SDHC_RD_PROCTL_RWCTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_RWCTL_MASK) >> SDHC_PROCTL_RWCTL_SHIFT)
+#define SDHC_BRD_PROCTL_RWCTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_RWCTL_SHIFT))
+
+/*! @brief Set the RWCTL field to a new value. */
+#define SDHC_WR_PROCTL_RWCTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_RWCTL_MASK, SDHC_PROCTL_RWCTL(value)))
+#define SDHC_BWR_PROCTL_RWCTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_RWCTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field IABG[19] (RW)
+ *
+ * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
+ * interrupt cycle. Setting to 1 enables interrupt detection at the block gap
+ * for a multiple block transfer. Setting to 0 disables interrupt detection during
+ * a multiple block transfer. If the SDIO card can't signal an interrupt during a
+ * multiple block transfer, this bit must be set to 0 to avoid an inadvertent
+ * interrupt. When the host driver detects an SDIO card insertion, it shall set
+ * this bit according to the CCCR of the card.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_IABG field. */
+#define SDHC_RD_PROCTL_IABG(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_IABG_MASK) >> SDHC_PROCTL_IABG_SHIFT)
+#define SDHC_BRD_PROCTL_IABG(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_IABG_SHIFT))
+
+/*! @brief Set the IABG field to a new value. */
+#define SDHC_WR_PROCTL_IABG(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_IABG_MASK, SDHC_PROCTL_IABG(value)))
+#define SDHC_BWR_PROCTL_IABG(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_IABG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINT[24] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
+ * (Wake Up Support) in CIS is set to 1. When this bit is set, the card
+ * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
+ * the wakeup feature is not enabled, the SD_CLK must be active to assert the
+ * card interrupt status and the SDHC interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECINT field. */
+#define SDHC_RD_PROCTL_WECINT(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECINT_MASK) >> SDHC_PROCTL_WECINT_SHIFT)
+#define SDHC_BRD_PROCTL_WECINT(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINT_SHIFT))
+
+/*! @brief Set the WECINT field to a new value. */
+#define SDHC_WR_PROCTL_WECINT(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECINT_MASK, SDHC_PROCTL_WECINT(value)))
+#define SDHC_BWR_PROCTL_WECINT(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINS[25] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
+ * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
+ * interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECINS field. */
+#define SDHC_RD_PROCTL_WECINS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECINS_MASK) >> SDHC_PROCTL_WECINS_SHIFT)
+#define SDHC_BRD_PROCTL_WECINS(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINS_SHIFT))
+
+/*! @brief Set the WECINS field to a new value. */
+#define SDHC_WR_PROCTL_WECINS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECINS_MASK, SDHC_PROCTL_WECINS(value)))
+#define SDHC_BWR_PROCTL_WECINS(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECRM[26] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
+ * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECRM field. */
+#define SDHC_RD_PROCTL_WECRM(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECRM_MASK) >> SDHC_PROCTL_WECRM_SHIFT)
+#define SDHC_BRD_PROCTL_WECRM(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECRM_SHIFT))
+
+/*! @brief Set the WECRM field to a new value. */
+#define SDHC_WR_PROCTL_WECRM(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECRM_MASK, SDHC_PROCTL_WECRM(value)))
+#define SDHC_BWR_PROCTL_WECRM(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECRM_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_SYSCTL - System Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_SYSCTL - System Control register (RW)
+ *
+ * Reset value: 0x00008008U
+ */
+/*!
+ * @name Constants and macros for entire SDHC_SYSCTL register
+ */
+/*@{*/
+#define SDHC_RD_SYSCTL(base)     (SDHC_SYSCTL_REG(base))
+#define SDHC_WR_SYSCTL(base, value) (SDHC_SYSCTL_REG(base) = (value))
+#define SDHC_RMW_SYSCTL(base, mask, value) (SDHC_WR_SYSCTL(base, (SDHC_RD_SYSCTL(base) & ~(mask)) | (value)))
+#define SDHC_SET_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) |  (value)))
+#define SDHC_CLR_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) & ~(value)))
+#define SDHC_TOG_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_SYSCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
+ *
+ * If this bit is set, bus clock will always be active and no automatic gating
+ * is applied. The bus clock will be internally gated off, if none of the
+ * following factors are met: The cmd part is reset, or Data part is reset, or Soft
+ * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
+ * request is just set, or This bit is set, or Card insertion is detected, or Card
+ * removal is detected, or Card external interrupt is detected, or The SDHC
+ * clock is not gated off The bus clock will not be auto gated off if the SDHC clock
+ * is not gated off. So clearing only this bit has no effect unless the PEREN bit
+ * is also cleared.
+ *
+ * Values:
+ * - 0b0 - Bus clock will be internally gated off.
+ * - 0b1 - Bus clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_IPGEN field. */
+#define SDHC_RD_SYSCTL_IPGEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_IPGEN_MASK) >> SDHC_SYSCTL_IPGEN_SHIFT)
+#define SDHC_BRD_SYSCTL_IPGEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_IPGEN_SHIFT))
+
+/*! @brief Set the IPGEN field to a new value. */
+#define SDHC_WR_SYSCTL_IPGEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_IPGEN_MASK, SDHC_SYSCTL_IPGEN(value)))
+#define SDHC_BWR_SYSCTL_IPGEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_IPGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
+ *
+ * If this bit is set, system clock will always be active and no automatic
+ * gating is applied. When this bit is cleared, system clock will be automatically off
+ * when no data transfer is on the SD bus.
+ *
+ * Values:
+ * - 0b0 - System clock will be internally gated off.
+ * - 0b1 - System clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_HCKEN field. */
+#define SDHC_RD_SYSCTL_HCKEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_HCKEN_MASK) >> SDHC_SYSCTL_HCKEN_SHIFT)
+#define SDHC_BRD_SYSCTL_HCKEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_HCKEN_SHIFT))
+
+/*! @brief Set the HCKEN field to a new value. */
+#define SDHC_WR_SYSCTL_HCKEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_HCKEN_MASK, SDHC_SYSCTL_HCKEN(value)))
+#define SDHC_BWR_SYSCTL_HCKEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_HCKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field PEREN[2] (RW)
+ *
+ * If this bit is set, SDHC clock will always be active and no automatic gating
+ * is applied. Thus the SDCLK is active except for when auto gating-off during
+ * buffer danger (buffer about to over-run or under-run). When this bit is cleared,
+ * the SDHC clock will be automatically off whenever there is no transaction on
+ * the SD bus. Because this bit is only a feature enabling bit, clearing this bit
+ * does not stop SDCLK immediately. The SDHC clock will be internally gated off,
+ * if none of the following factors are met: The cmd part is reset, or Data part
+ * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
+ * just updated, or Continue request is just set, or This bit is set, or Card
+ * insertion is detected, or Card removal is detected, or Card external interrupt is
+ * detected, or 80 clocks for initialization phase is ongoing
+ *
+ * Values:
+ * - 0b0 - SDHC clock will be internally gated off.
+ * - 0b1 - SDHC clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_PEREN field. */
+#define SDHC_RD_SYSCTL_PEREN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_PEREN_MASK) >> SDHC_SYSCTL_PEREN_SHIFT)
+#define SDHC_BRD_SYSCTL_PEREN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_PEREN_SHIFT))
+
+/*! @brief Set the PEREN field to a new value. */
+#define SDHC_WR_SYSCTL_PEREN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_PEREN_MASK, SDHC_SYSCTL_PEREN(value)))
+#define SDHC_BWR_SYSCTL_PEREN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_PEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
+ *
+ * The host controller shall stop SDCLK when writing this bit to 0. SDCLK
+ * frequency can be changed when this bit is 0. Then, the host controller shall
+ * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
+ * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
+ * power.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field. */
+#define SDHC_RD_SYSCTL_SDCLKEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_SDCLKEN_MASK) >> SDHC_SYSCTL_SDCLKEN_SHIFT)
+#define SDHC_BRD_SYSCTL_SDCLKEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_SDCLKEN_SHIFT))
+
+/*! @brief Set the SDCLKEN field to a new value. */
+#define SDHC_WR_SYSCTL_SDCLKEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_SDCLKEN_MASK, SDHC_SYSCTL_SDCLKEN(value)))
+#define SDHC_BWR_SYSCTL_SDCLKEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_SDCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
+ *
+ * Used to provide a more exact divisor to generate the desired SD clock
+ * frequency. Note the divider can even support odd divisor without deterioration of
+ * duty cycle. The setting are as following:
+ *
+ * Values:
+ * - 0b0000 - Divisor by 1.
+ * - 0b0001 - Divisor by 2.
+ * - 0b1110 - Divisor by 15.
+ * - 0b1111 - Divisor by 16.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_DVS field. */
+#define SDHC_RD_SYSCTL_DVS(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_DVS_MASK) >> SDHC_SYSCTL_DVS_SHIFT)
+#define SDHC_BRD_SYSCTL_DVS(base) (SDHC_RD_SYSCTL_DVS(base))
+
+/*! @brief Set the DVS field to a new value. */
+#define SDHC_WR_SYSCTL_DVS(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_DVS_MASK, SDHC_SYSCTL_DVS(value)))
+#define SDHC_BWR_SYSCTL_DVS(base, value) (SDHC_WR_SYSCTL_DVS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
+ *
+ * Used to select the frequency of the SDCLK pin. The frequency is not
+ * programmed directly. Rather this register holds the prescaler (this register) and
+ * divisor (next register) of the base clock frequency register. Setting 00h bypasses
+ * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
+ * behavior of this prescaler is undefined. The two default divider values can
+ * be calculated by the frequency of SDHC clock and the following divisor bits.
+ * The frequency of SDCLK is set by the following formula: Clock frequency = (Base
+ * clock) / (prescaler x divisor) For example, if the base clock frequency is 96
+ * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
+ * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
+ * less than or equal to the target. Similarly, to approach a clock value of 400
+ * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
+ * value of 400 kHz. The reset value of this field is 80h, so if the input base
+ * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
+ * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
+ * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
+ * never exceed this limit. Only the following settings are allowed:
+ *
+ * Values:
+ * - 0b00000001 - Base clock divided by 2.
+ * - 0b00000010 - Base clock divided by 4.
+ * - 0b00000100 - Base clock divided by 8.
+ * - 0b00001000 - Base clock divided by 16.
+ * - 0b00010000 - Base clock divided by 32.
+ * - 0b00100000 - Base clock divided by 64.
+ * - 0b01000000 - Base clock divided by 128.
+ * - 0b10000000 - Base clock divided by 256.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field. */
+#define SDHC_RD_SYSCTL_SDCLKFS(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_SDCLKFS_MASK) >> SDHC_SYSCTL_SDCLKFS_SHIFT)
+#define SDHC_BRD_SYSCTL_SDCLKFS(base) (SDHC_RD_SYSCTL_SDCLKFS(base))
+
+/*! @brief Set the SDCLKFS field to a new value. */
+#define SDHC_WR_SYSCTL_SDCLKFS(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_SDCLKFS_MASK, SDHC_SYSCTL_SDCLKFS(value)))
+#define SDHC_BWR_SYSCTL_SDCLKFS(base, value) (SDHC_WR_SYSCTL_SDCLKFS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
+ *
+ * Determines the interval by which DAT line timeouts are detected. See
+ * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
+ * clock frequency will be generated by dividing the base clock SDCLK value by this
+ * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
+ * time-out events.
+ *
+ * Values:
+ * - 0b0000 - SDCLK x 2 13
+ * - 0b0001 - SDCLK x 2 14
+ * - 0b1110 - SDCLK x 2 27
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_DTOCV field. */
+#define SDHC_RD_SYSCTL_DTOCV(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_DTOCV_MASK) >> SDHC_SYSCTL_DTOCV_SHIFT)
+#define SDHC_BRD_SYSCTL_DTOCV(base) (SDHC_RD_SYSCTL_DTOCV(base))
+
+/*! @brief Set the DTOCV field to a new value. */
+#define SDHC_WR_SYSCTL_DTOCV(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_DTOCV_MASK, SDHC_SYSCTL_DTOCV(value)))
+#define SDHC_BWR_SYSCTL_DTOCV(base, value) (SDHC_WR_SYSCTL_DTOCV(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
+ *
+ * Effects the entire host controller except for the card detection circuit.
+ * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
+ * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
+ * reset this bit to 0 when the capabilities registers are valid and the host driver
+ * can read them. Additional use of software reset for all does not affect the
+ * value of the capabilities registers. After this bit is set, it is recommended
+ * that the host driver reset the external card and reinitialize it.
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define SDHC_WR_SYSCTL_RSTA(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTA_MASK, SDHC_SYSCTL_RSTA(value)))
+#define SDHC_BWR_SYSCTL_RSTA(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
+ *
+ * Only part of the command circuit is reset. The following registers and bits
+ * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTC field to a new value. */
+#define SDHC_WR_SYSCTL_RSTC(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTC_MASK, SDHC_SYSCTL_RSTC(value)))
+#define SDHC_BWR_SYSCTL_RSTC(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
+ *
+ * Only part of the data circuit is reset. DMA circuit is also reset. The
+ * following registers and bits are cleared by this bit: Data Port register Buffer Is
+ * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
+ * Enable Read Transfer Active Write Transfer Active DAT Line Active Command
+ * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
+ * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
+ * Block Gap Event Transfer Complete
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTD field to a new value. */
+#define SDHC_WR_SYSCTL_RSTD(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTD_MASK, SDHC_SYSCTL_RSTD(value)))
+#define SDHC_BWR_SYSCTL_RSTD(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field INITA[27] (RW)
+ *
+ * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
+ * are sent, this bit is self-cleared. This bit is very useful during the card
+ * power-up period when 74 SD-clocks are needed and the clock auto gating feature
+ * is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
+ * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
+ * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
+ * when command line or data lines are active, write to this bit is not allowed.
+ * On the otherhand, when this bit is set, that is, during intialization active
+ * period, it is allowed to issue command, and the command bit stream will appear
+ * on the CMD pad after all 80 clock cycles are done. So when this command ends,
+ * the driver can make sure the 80 clock cycles are sent out. This is very useful
+ * when the driver needs send 80 cycles to the card and does not want to wait
+ * till this bit is self-cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_INITA field. */
+#define SDHC_RD_SYSCTL_INITA(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_INITA_MASK) >> SDHC_SYSCTL_INITA_SHIFT)
+#define SDHC_BRD_SYSCTL_INITA(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_INITA_SHIFT))
+
+/*! @brief Set the INITA field to a new value. */
+#define SDHC_WR_SYSCTL_INITA(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_INITA_MASK, SDHC_SYSCTL_INITA(value)))
+#define SDHC_BWR_SYSCTL_INITA(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_INITA_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSTAT - Interrupt Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * An interrupt is generated when the Normal Interrupt Signal Enable is enabled
+ * and at least one of the status bits is set to 1. For all bits, writing 1 to a
+ * bit clears it; writing to 0 keeps the bit unchanged. More than one status can
+ * be cleared with a single register write. For Card Interrupt, before writing 1
+ * to clear, it is required that the card stops asserting the interrupt, meaning
+ * that when the Card Driver services the interrupt condition, otherwise the CINT
+ * bit will be asserted again. The table below shows the relationship between
+ * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
+ * complete Command timeout error Meaning of the status 0 0 X X 1 Response not
+ * received within 64 SDCLK cycles 1 0 Response received The table below shows the
+ * relationship between the Transfer Complete and the Data Timeout Error. SDHC status
+ * for data timeout error/transfer complete bit combinations Transfer complete
+ * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
+ * transfer 1 X Data transfer complete The table below shows the relationship between
+ * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
+ * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
+ * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
+ * CMD line conflict
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTAT register
+ */
+/*@{*/
+#define SDHC_RD_IRQSTAT(base)    (SDHC_IRQSTAT_REG(base))
+#define SDHC_WR_IRQSTAT(base, value) (SDHC_IRQSTAT_REG(base) = (value))
+#define SDHC_RMW_IRQSTAT(base, mask, value) (SDHC_WR_IRQSTAT(base, (SDHC_RD_IRQSTAT(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) |  (value)))
+#define SDHC_CLR_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) & ~(value)))
+#define SDHC_TOG_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CC[0] (W1C)
+ *
+ * This bit is set when you receive the end bit of the command response, except
+ * Auto CMD12. See PRSSTAT[CIHB].
+ *
+ * Values:
+ * - 0b0 - Command not complete.
+ * - 0b1 - Command complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CC field. */
+#define SDHC_RD_IRQSTAT_CC(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CC_MASK) >> SDHC_IRQSTAT_CC_SHIFT)
+#define SDHC_BRD_IRQSTAT_CC(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CC_SHIFT))
+
+/*! @brief Set the CC field to a new value. */
+#define SDHC_WR_IRQSTAT_CC(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CC(value)))
+#define SDHC_BWR_IRQSTAT_CC(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field TC[1] (W1C)
+ *
+ * This bit is set when a read or write transfer is completed. In the case of a
+ * read transaction: This bit is set at the falling edge of the read transfer
+ * active status. There are two cases in which this interrupt is generated. The
+ * first is when a data transfer is completed as specified by the data length, after
+ * the last data has been read to the host system. The second is when data has
+ * stopped at the block gap and completed the data transfer by setting
+ * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
+ * transaction: This bit is set at the falling edge of the DAT line active
+ * status. There are two cases in which this interrupt is generated. The first is when
+ * the last data is written to the SD card as specified by the data length and
+ * the busy signal is released. The second is when data transfers are stopped at
+ * the block gap, by setting PROCTL[SABGREQ], and the data transfers are
+ * completed,after valid data is written to the SD card and the busy signal released.
+ *
+ * Values:
+ * - 0b0 - Transfer not complete.
+ * - 0b1 - Transfer complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_TC field. */
+#define SDHC_RD_IRQSTAT_TC(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_TC_MASK) >> SDHC_IRQSTAT_TC_SHIFT)
+#define SDHC_BRD_IRQSTAT_TC(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_TC_SHIFT))
+
+/*! @brief Set the TC field to a new value. */
+#define SDHC_WR_IRQSTAT_TC(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_TC(value)))
+#define SDHC_BWR_IRQSTAT_TC(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_TC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
+ *
+ * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
+ * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
+ * set to 1. In the case of a read transaction: This bit is set at the falling
+ * edge of the DAT line active status, when the transaction is stopped at SD Bus
+ * timing. The read wait must be supported in order to use this function. In the
+ * case of write transaction: This bit is set at the falling edge of write transfer
+ * active status, after getting CRC status at SD bus timing.
+ *
+ * Values:
+ * - 0b0 - No block gap event.
+ * - 0b1 - Transaction stopped at block gap.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BGE field. */
+#define SDHC_RD_IRQSTAT_BGE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BGE_MASK) >> SDHC_IRQSTAT_BGE_SHIFT)
+#define SDHC_BRD_IRQSTAT_BGE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BGE_SHIFT))
+
+/*! @brief Set the BGE field to a new value. */
+#define SDHC_WR_IRQSTAT_BGE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BGE(value)))
+#define SDHC_BWR_IRQSTAT_BGE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
+ *
+ * Occurs only when the internal DMA finishes the data transfer successfully.
+ * Whenever errors occur during data transfer, this bit will not be set. Instead,
+ * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
+ * this bit will be set.
+ *
+ * Values:
+ * - 0b0 - No DMA Interrupt.
+ * - 0b1 - DMA Interrupt is generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DINT field. */
+#define SDHC_RD_IRQSTAT_DINT(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DINT_MASK) >> SDHC_IRQSTAT_DINT_SHIFT)
+#define SDHC_BRD_IRQSTAT_DINT(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DINT_SHIFT))
+
+/*! @brief Set the DINT field to a new value. */
+#define SDHC_WR_IRQSTAT_DINT(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DINT(value)))
+#define SDHC_BWR_IRQSTAT_DINT(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
+ *
+ * This status bit is set if the Buffer Write Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0b0 - Not ready to write buffer.
+ * - 0b1 - Ready to write buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BWR field. */
+#define SDHC_RD_IRQSTAT_BWR(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BWR_MASK) >> SDHC_IRQSTAT_BWR_SHIFT)
+#define SDHC_BRD_IRQSTAT_BWR(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BWR_SHIFT))
+
+/*! @brief Set the BWR field to a new value. */
+#define SDHC_WR_IRQSTAT_BWR(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BWR(value)))
+#define SDHC_BWR_IRQSTAT_BWR(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BWR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
+ *
+ * This status bit is set if the Buffer Read Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0b0 - Not ready to read buffer.
+ * - 0b1 - Ready to read buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BRR field. */
+#define SDHC_RD_IRQSTAT_BRR(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BRR_MASK) >> SDHC_IRQSTAT_BRR_SHIFT)
+#define SDHC_BRD_IRQSTAT_BRR(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BRR_SHIFT))
+
+/*! @brief Set the BRR field to a new value. */
+#define SDHC_WR_IRQSTAT_BRR(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BRR(value)))
+#define SDHC_BWR_IRQSTAT_BRR(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 0 to 1. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if a card is inserted. To leave it cleared,
+ * clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0b0 - Card state unstable or removed.
+ * - 0b1 - Card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CINS field. */
+#define SDHC_RD_IRQSTAT_CINS(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CINS_MASK) >> SDHC_IRQSTAT_CINS_SHIFT)
+#define SDHC_BRD_IRQSTAT_CINS(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINS_SHIFT))
+
+/*! @brief Set the CINS field to a new value. */
+#define SDHC_WR_IRQSTAT_CINS(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CINS(value)))
+#define SDHC_BWR_IRQSTAT_CINS(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 1 to 0. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if no card is inserted. To leave it cleared,
+ * clear the Card Removal Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0b0 - Card state unstable or inserted.
+ * - 0b1 - Card removed.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CRM field. */
+#define SDHC_RD_IRQSTAT_CRM(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CRM_MASK) >> SDHC_IRQSTAT_CRM_SHIFT)
+#define SDHC_BRD_IRQSTAT_CRM(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CRM_SHIFT))
+
+/*! @brief Set the CRM field to a new value. */
+#define SDHC_WR_IRQSTAT_CRM(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CRM(value)))
+#define SDHC_BWR_IRQSTAT_CRM(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CRM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
+ *
+ * This status bit is set when an interrupt signal is detected from the external
+ * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
+ * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
+ * during the interrupt cycle, so the interrupt from card can only be sampled
+ * during interrupt cycle, introducing some delay between the interrupt signal from
+ * the SDIO card and the interrupt to the host system. Writing this bit to 1 can
+ * clear this bit, but as the interrupt factor from the SDIO card does not clear,
+ * this bit is set again. To clear this bit, it is required to reset the interrupt
+ * factor from the external card followed by a writing 1 to this bit. When this
+ * status has been set, and the host driver needs to service this interrupt, the
+ * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
+ * 0 to stop driving the interrupt signal to the host system. After completion
+ * of the card interrupt service (it must reset the interrupt factors in the SDIO
+ * card and the interrupt signal may not be asserted), write 1 to clear this bit,
+ * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
+ * signal again.
+ *
+ * Values:
+ * - 0b0 - No Card Interrupt.
+ * - 0b1 - Generate Card Interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CINT field. */
+#define SDHC_RD_IRQSTAT_CINT(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CINT_MASK) >> SDHC_IRQSTAT_CINT_SHIFT)
+#define SDHC_BRD_IRQSTAT_CINT(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINT_SHIFT))
+
+/*! @brief Set the CINT field to a new value. */
+#define SDHC_WR_IRQSTAT_CINT(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CINT(value)))
+#define SDHC_BWR_IRQSTAT_CINT(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
+ *
+ * Occurs only if no response is returned within 64 SDCLK cycles from the end
+ * bit of the command. If the SDHC detects a CMD line conflict, in which case a
+ * Command CRC Error shall also be set, this bit shall be set without waiting for 64
+ * SDCLK cycles. This is because the command will be aborted by the SDHC.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CTOE field. */
+#define SDHC_RD_IRQSTAT_CTOE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CTOE_MASK) >> SDHC_IRQSTAT_CTOE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CTOE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CTOE_SHIFT))
+
+/*! @brief Set the CTOE field to a new value. */
+#define SDHC_WR_IRQSTAT_CTOE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CTOE(value)))
+#define SDHC_BWR_IRQSTAT_CTOE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
+ *
+ * Command CRC Error is generated in two cases. If a response is returned and
+ * the Command Timeout Error is set to 0, indicating no time-out, this bit is set
+ * when detecting a CRC error in the command response. The SDHC detects a CMD line
+ * conflict by monitoring the CMD line when a command is issued. If the SDHC
+ * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
+ * then the SDHC shall abort the command (Stop driving CMD line) and set this bit
+ * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
+ * conflict.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - CRC Error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CCE field. */
+#define SDHC_RD_IRQSTAT_CCE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CCE_MASK) >> SDHC_IRQSTAT_CCE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CCE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CCE_SHIFT))
+
+/*! @brief Set the CCE field to a new value. */
+#define SDHC_WR_IRQSTAT_CCE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CCE(value)))
+#define SDHC_BWR_IRQSTAT_CCE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
+ *
+ * Occurs when detecting that the end bit of a command response is 0.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - End Bit Error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CEBE field. */
+#define SDHC_RD_IRQSTAT_CEBE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CEBE_MASK) >> SDHC_IRQSTAT_CEBE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CEBE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CEBE_SHIFT))
+
+/*! @brief Set the CEBE field to a new value. */
+#define SDHC_WR_IRQSTAT_CEBE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CEBE(value)))
+#define SDHC_BWR_IRQSTAT_CEBE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
+ *
+ * Occurs if a Command Index error occurs in the command response.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CIE field. */
+#define SDHC_RD_IRQSTAT_CIE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CIE_MASK) >> SDHC_IRQSTAT_CIE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CIE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CIE_SHIFT))
+
+/*! @brief Set the CIE field to a new value. */
+#define SDHC_WR_IRQSTAT_CIE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CIE(value)))
+#define SDHC_BWR_IRQSTAT_CIE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
+ *
+ * Occurs when detecting one of following time-out conditions. Busy time-out for
+ * R1b,R5b type Busy time-out after Write CRC status Read Data time-out
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DTOE field. */
+#define SDHC_RD_IRQSTAT_DTOE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DTOE_MASK) >> SDHC_IRQSTAT_DTOE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DTOE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DTOE_SHIFT))
+
+/*! @brief Set the DTOE field to a new value. */
+#define SDHC_WR_IRQSTAT_DTOE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DTOE(value)))
+#define SDHC_BWR_IRQSTAT_DTOE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
+ *
+ * Occurs when detecting a CRC error when transferring read data, which uses the
+ * DAT line, or when detecting the Write CRC status having a value other than
+ * 010.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DCE field. */
+#define SDHC_RD_IRQSTAT_DCE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DCE_MASK) >> SDHC_IRQSTAT_DCE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DCE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DCE_SHIFT))
+
+/*! @brief Set the DCE field to a new value. */
+#define SDHC_WR_IRQSTAT_DCE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DCE(value)))
+#define SDHC_BWR_IRQSTAT_DCE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
+ *
+ * Occurs either when detecting 0 at the end bit position of read data, which
+ * uses the DAT line, or at the end bit position of the CRC.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DEBE field. */
+#define SDHC_RD_IRQSTAT_DEBE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DEBE_MASK) >> SDHC_IRQSTAT_DEBE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DEBE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DEBE_SHIFT))
+
+/*! @brief Set the DEBE field to a new value. */
+#define SDHC_WR_IRQSTAT_DEBE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DEBE(value)))
+#define SDHC_BWR_IRQSTAT_DEBE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
+ *
+ * Occurs when detecting that one of the bits in the Auto CMD12 Error Status
+ * register has changed from 0 to 1. This bit is set to 1, not only when the errors
+ * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
+ * previous command error.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_AC12E field. */
+#define SDHC_RD_IRQSTAT_AC12E(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_AC12E_MASK) >> SDHC_IRQSTAT_AC12E_SHIFT)
+#define SDHC_BRD_IRQSTAT_AC12E(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_AC12E_SHIFT))
+
+/*! @brief Set the AC12E field to a new value. */
+#define SDHC_WR_IRQSTAT_AC12E(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_AC12E(value)))
+#define SDHC_BWR_IRQSTAT_AC12E(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_AC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
+ *
+ * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
+ * some error occurs in the data transfer. This error can be caused by either
+ * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
+ * Address register is the next fetch address where the error occurs. Because any
+ * error corrupts the whole data block, the host driver shall restart the transfer
+ * from the corrupted block boundary. The address of the block boundary can be
+ * calculated either from the current DSADDR value or from the remaining number of
+ * blocks and the block size.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DMAE field. */
+#define SDHC_RD_IRQSTAT_DMAE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DMAE_MASK) >> SDHC_IRQSTAT_DMAE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DMAE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DMAE_SHIFT))
+
+/*! @brief Set the DMAE field to a new value. */
+#define SDHC_WR_IRQSTAT_DMAE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DMAE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK), SDHC_IRQSTAT_DMAE(value)))
+#define SDHC_BWR_IRQSTAT_DMAE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DMAE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSTATEN - Interrupt Status Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
+ *
+ * Reset value: 0x117F013FU
+ *
+ * Setting the bits in this register to 1 enables the corresponding interrupt
+ * status to be set by the specified event. If any bit is cleared, the
+ * corresponding interrupt status bit is also cleared, that is, when the bit in this register
+ * is cleared, the corresponding bit in interrupt status register is always 0.
+ * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
+ * card interrupt signal during the interrupt period and hold its value in the
+ * flip-flop. There will be some delays on the card interrupt, asserted from the card,
+ * to the time the host system is informed. To detect a CMD line conflict, the
+ * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTATEN register
+ */
+/*@{*/
+#define SDHC_RD_IRQSTATEN(base)  (SDHC_IRQSTATEN_REG(base))
+#define SDHC_WR_IRQSTATEN(base, value) (SDHC_IRQSTATEN_REG(base) = (value))
+#define SDHC_RMW_IRQSTATEN(base, mask, value) (SDHC_WR_IRQSTATEN(base, (SDHC_RD_IRQSTATEN(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) |  (value)))
+#define SDHC_CLR_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) & ~(value)))
+#define SDHC_TOG_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSTATEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field. */
+#define SDHC_RD_IRQSTATEN_CCSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CCSEN_MASK) >> SDHC_IRQSTATEN_CCSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CCSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCSEN_SHIFT))
+
+/*! @brief Set the CCSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CCSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CCSEN_MASK, SDHC_IRQSTATEN_CCSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CCSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field. */
+#define SDHC_RD_IRQSTATEN_TCSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_TCSEN_MASK) >> SDHC_IRQSTATEN_TCSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_TCSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_TCSEN_SHIFT))
+
+/*! @brief Set the TCSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_TCSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_TCSEN_MASK, SDHC_IRQSTATEN_TCSEN(value)))
+#define SDHC_BWR_IRQSTATEN_TCSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_TCSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field. */
+#define SDHC_RD_IRQSTATEN_BGESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BGESEN_MASK) >> SDHC_IRQSTATEN_BGESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BGESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BGESEN_SHIFT))
+
+/*! @brief Set the BGESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BGESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BGESEN_MASK, SDHC_IRQSTATEN_BGESEN(value)))
+#define SDHC_BWR_IRQSTATEN_BGESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BGESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field. */
+#define SDHC_RD_IRQSTATEN_DINTSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DINTSEN_MASK) >> SDHC_IRQSTATEN_DINTSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DINTSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DINTSEN_SHIFT))
+
+/*! @brief Set the DINTSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DINTSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DINTSEN_MASK, SDHC_IRQSTATEN_DINTSEN(value)))
+#define SDHC_BWR_IRQSTATEN_DINTSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DINTSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field. */
+#define SDHC_RD_IRQSTATEN_BWRSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BWRSEN_MASK) >> SDHC_IRQSTATEN_BWRSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BWRSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BWRSEN_SHIFT))
+
+/*! @brief Set the BWRSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BWRSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BWRSEN_MASK, SDHC_IRQSTATEN_BWRSEN(value)))
+#define SDHC_BWR_IRQSTATEN_BWRSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BWRSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field. */
+#define SDHC_RD_IRQSTATEN_BRRSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BRRSEN_MASK) >> SDHC_IRQSTATEN_BRRSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BRRSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BRRSEN_SHIFT))
+
+/*! @brief Set the BRRSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BRRSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BRRSEN_MASK, SDHC_IRQSTATEN_BRRSEN(value)))
+#define SDHC_BWR_IRQSTATEN_BRRSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BRRSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field. */
+#define SDHC_RD_IRQSTATEN_CINSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CINSEN_MASK) >> SDHC_IRQSTATEN_CINSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CINSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINSEN_SHIFT))
+
+/*! @brief Set the CINSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CINSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CINSEN_MASK, SDHC_IRQSTATEN_CINSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CINSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field. */
+#define SDHC_RD_IRQSTATEN_CRMSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CRMSEN_MASK) >> SDHC_IRQSTATEN_CRMSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CRMSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CRMSEN_SHIFT))
+
+/*! @brief Set the CRMSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CRMSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CRMSEN_MASK, SDHC_IRQSTATEN_CRMSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CRMSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CRMSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
+ *
+ * If this bit is set to 0, the SDHC will clear the interrupt request to the
+ * system. The card interrupt detection is stopped when this bit is cleared and
+ * restarted when this bit is set to 1. The host driver must clear the this bit
+ * before servicing the card interrupt and must set this bit again after all interrupt
+ * requests from the card are cleared to prevent inadvertent interrupts.
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field. */
+#define SDHC_RD_IRQSTATEN_CINTSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CINTSEN_MASK) >> SDHC_IRQSTATEN_CINTSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CINTSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINTSEN_SHIFT))
+
+/*! @brief Set the CINTSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CINTSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CINTSEN_MASK, SDHC_IRQSTATEN_CINTSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CINTSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINTSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field. */
+#define SDHC_RD_IRQSTATEN_CTOESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CTOESEN_MASK) >> SDHC_IRQSTATEN_CTOESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CTOESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CTOESEN_SHIFT))
+
+/*! @brief Set the CTOESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CTOESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CTOESEN_MASK, SDHC_IRQSTATEN_CTOESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CTOESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CTOESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field. */
+#define SDHC_RD_IRQSTATEN_CCESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CCESEN_MASK) >> SDHC_IRQSTATEN_CCESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CCESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCESEN_SHIFT))
+
+/*! @brief Set the CCESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CCESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CCESEN_MASK, SDHC_IRQSTATEN_CCESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CCESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field. */
+#define SDHC_RD_IRQSTATEN_CEBESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CEBESEN_MASK) >> SDHC_IRQSTATEN_CEBESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CEBESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CEBESEN_SHIFT))
+
+/*! @brief Set the CEBESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CEBESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CEBESEN_MASK, SDHC_IRQSTATEN_CEBESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CEBESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CEBESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field. */
+#define SDHC_RD_IRQSTATEN_CIESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CIESEN_MASK) >> SDHC_IRQSTATEN_CIESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CIESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CIESEN_SHIFT))
+
+/*! @brief Set the CIESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CIESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CIESEN_MASK, SDHC_IRQSTATEN_CIESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CIESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CIESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field. */
+#define SDHC_RD_IRQSTATEN_DTOESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DTOESEN_MASK) >> SDHC_IRQSTATEN_DTOESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DTOESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DTOESEN_SHIFT))
+
+/*! @brief Set the DTOESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DTOESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DTOESEN_MASK, SDHC_IRQSTATEN_DTOESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DTOESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DTOESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field. */
+#define SDHC_RD_IRQSTATEN_DCESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DCESEN_MASK) >> SDHC_IRQSTATEN_DCESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DCESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DCESEN_SHIFT))
+
+/*! @brief Set the DCESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DCESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DCESEN_MASK, SDHC_IRQSTATEN_DCESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DCESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DCESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field. */
+#define SDHC_RD_IRQSTATEN_DEBESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DEBESEN_MASK) >> SDHC_IRQSTATEN_DEBESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DEBESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DEBESEN_SHIFT))
+
+/*! @brief Set the DEBESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DEBESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DEBESEN_MASK, SDHC_IRQSTATEN_DEBESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DEBESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DEBESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field. */
+#define SDHC_RD_IRQSTATEN_AC12ESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_AC12ESEN_MASK) >> SDHC_IRQSTATEN_AC12ESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_AC12ESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_AC12ESEN_SHIFT))
+
+/*! @brief Set the AC12ESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_AC12ESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_AC12ESEN_MASK, SDHC_IRQSTATEN_AC12ESEN(value)))
+#define SDHC_BWR_IRQSTATEN_AC12ESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_AC12ESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field. */
+#define SDHC_RD_IRQSTATEN_DMAESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DMAESEN_MASK) >> SDHC_IRQSTATEN_DMAESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DMAESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DMAESEN_SHIFT))
+
+/*! @brief Set the DMAESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DMAESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DMAESEN_MASK, SDHC_IRQSTATEN_DMAESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DMAESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DMAESEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSIGEN - Interrupt Signal Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to select which interrupt status is indicated to the
+ * host system as the interrupt. All of these status bits share the same interrupt
+ * line. Setting any of these bits to 1 enables interrupt generation. The
+ * corresponding status register bit will generate an interrupt when the corresponding
+ * interrupt signal enable bit is set.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSIGEN register
+ */
+/*@{*/
+#define SDHC_RD_IRQSIGEN(base)   (SDHC_IRQSIGEN_REG(base))
+#define SDHC_WR_IRQSIGEN(base, value) (SDHC_IRQSIGEN_REG(base) = (value))
+#define SDHC_RMW_IRQSIGEN(base, mask, value) (SDHC_WR_IRQSIGEN(base, (SDHC_RD_IRQSIGEN(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) |  (value)))
+#define SDHC_CLR_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) & ~(value)))
+#define SDHC_TOG_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSIGEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field. */
+#define SDHC_RD_IRQSIGEN_CCIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CCIEN_MASK) >> SDHC_IRQSIGEN_CCIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CCIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCIEN_SHIFT))
+
+/*! @brief Set the CCIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CCIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CCIEN_MASK, SDHC_IRQSIGEN_CCIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CCIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field. */
+#define SDHC_RD_IRQSIGEN_TCIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_TCIEN_MASK) >> SDHC_IRQSIGEN_TCIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_TCIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_TCIEN_SHIFT))
+
+/*! @brief Set the TCIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_TCIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_TCIEN_MASK, SDHC_IRQSIGEN_TCIEN(value)))
+#define SDHC_BWR_IRQSIGEN_TCIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_TCIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field. */
+#define SDHC_RD_IRQSIGEN_BGEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BGEIEN_MASK) >> SDHC_IRQSIGEN_BGEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BGEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BGEIEN_SHIFT))
+
+/*! @brief Set the BGEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BGEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BGEIEN_MASK, SDHC_IRQSIGEN_BGEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BGEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BGEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field. */
+#define SDHC_RD_IRQSIGEN_DINTIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DINTIEN_MASK) >> SDHC_IRQSIGEN_DINTIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DINTIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DINTIEN_SHIFT))
+
+/*! @brief Set the DINTIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DINTIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DINTIEN_MASK, SDHC_IRQSIGEN_DINTIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DINTIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DINTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field. */
+#define SDHC_RD_IRQSIGEN_BWRIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BWRIEN_MASK) >> SDHC_IRQSIGEN_BWRIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BWRIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BWRIEN_SHIFT))
+
+/*! @brief Set the BWRIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BWRIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BWRIEN_MASK, SDHC_IRQSIGEN_BWRIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BWRIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BWRIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field. */
+#define SDHC_RD_IRQSIGEN_BRRIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BRRIEN_MASK) >> SDHC_IRQSIGEN_BRRIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BRRIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BRRIEN_SHIFT))
+
+/*! @brief Set the BRRIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BRRIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BRRIEN_MASK, SDHC_IRQSIGEN_BRRIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BRRIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BRRIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field. */
+#define SDHC_RD_IRQSIGEN_CINSIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CINSIEN_MASK) >> SDHC_IRQSIGEN_CINSIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CINSIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINSIEN_SHIFT))
+
+/*! @brief Set the CINSIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CINSIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CINSIEN_MASK, SDHC_IRQSIGEN_CINSIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CINSIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINSIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field. */
+#define SDHC_RD_IRQSIGEN_CRMIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CRMIEN_MASK) >> SDHC_IRQSIGEN_CRMIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CRMIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CRMIEN_SHIFT))
+
+/*! @brief Set the CRMIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CRMIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CRMIEN_MASK, SDHC_IRQSIGEN_CRMIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CRMIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CRMIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field. */
+#define SDHC_RD_IRQSIGEN_CINTIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CINTIEN_MASK) >> SDHC_IRQSIGEN_CINTIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CINTIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINTIEN_SHIFT))
+
+/*! @brief Set the CINTIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CINTIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CINTIEN_MASK, SDHC_IRQSIGEN_CINTIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CINTIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field. */
+#define SDHC_RD_IRQSIGEN_CTOEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CTOEIEN_MASK) >> SDHC_IRQSIGEN_CTOEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CTOEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CTOEIEN_SHIFT))
+
+/*! @brief Set the CTOEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CTOEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CTOEIEN_MASK, SDHC_IRQSIGEN_CTOEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CTOEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CTOEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field. */
+#define SDHC_RD_IRQSIGEN_CCEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CCEIEN_MASK) >> SDHC_IRQSIGEN_CCEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CCEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCEIEN_SHIFT))
+
+/*! @brief Set the CCEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CCEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CCEIEN_MASK, SDHC_IRQSIGEN_CCEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CCEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field. */
+#define SDHC_RD_IRQSIGEN_CEBEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CEBEIEN_MASK) >> SDHC_IRQSIGEN_CEBEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CEBEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CEBEIEN_SHIFT))
+
+/*! @brief Set the CEBEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CEBEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CEBEIEN_MASK, SDHC_IRQSIGEN_CEBEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CEBEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CEBEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field. */
+#define SDHC_RD_IRQSIGEN_CIEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CIEIEN_MASK) >> SDHC_IRQSIGEN_CIEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CIEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CIEIEN_SHIFT))
+
+/*! @brief Set the CIEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CIEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CIEIEN_MASK, SDHC_IRQSIGEN_CIEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CIEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CIEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field. */
+#define SDHC_RD_IRQSIGEN_DTOEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DTOEIEN_MASK) >> SDHC_IRQSIGEN_DTOEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DTOEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DTOEIEN_SHIFT))
+
+/*! @brief Set the DTOEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DTOEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DTOEIEN_MASK, SDHC_IRQSIGEN_DTOEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DTOEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DTOEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field. */
+#define SDHC_RD_IRQSIGEN_DCEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DCEIEN_MASK) >> SDHC_IRQSIGEN_DCEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DCEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DCEIEN_SHIFT))
+
+/*! @brief Set the DCEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DCEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DCEIEN_MASK, SDHC_IRQSIGEN_DCEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DCEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DCEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field. */
+#define SDHC_RD_IRQSIGEN_DEBEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DEBEIEN_MASK) >> SDHC_IRQSIGEN_DEBEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DEBEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DEBEIEN_SHIFT))
+
+/*! @brief Set the DEBEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DEBEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DEBEIEN_MASK, SDHC_IRQSIGEN_DEBEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DEBEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DEBEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field. */
+#define SDHC_RD_IRQSIGEN_AC12EIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_AC12EIEN_MASK) >> SDHC_IRQSIGEN_AC12EIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_AC12EIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_AC12EIEN_SHIFT))
+
+/*! @brief Set the AC12EIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_AC12EIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_AC12EIEN_MASK, SDHC_IRQSIGEN_AC12EIEN(value)))
+#define SDHC_BWR_IRQSIGEN_AC12EIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_AC12EIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field. */
+#define SDHC_RD_IRQSIGEN_DMAEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DMAEIEN_MASK) >> SDHC_IRQSIGEN_DMAEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DMAEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DMAEIEN_SHIFT))
+
+/*! @brief Set the DMAEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DMAEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DMAEIEN_MASK, SDHC_IRQSIGEN_DMAEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DMAEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DMAEIEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_AC12ERR - Auto CMD12 Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the AC12ESEN bit in the Status register is set, the host driver shall
+ * check this register to identify what kind of error the Auto CMD12 indicated.
+ * This register is valid only when the Auto CMD12 Error status bit is set. The
+ * following table shows the relationship between the Auto CMGD12 CRC error and the
+ * Auto CMD12 command timeout error. Relationship between Command CRC Error and
+ * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
+ * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
+ * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
+ * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
+ * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
+ * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
+ * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
+ * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
+ * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
+ * command that can't be issued. Clear bit 7 if there is no command to issue. The
+ * timing for generating the auto CMD12 error and writing to the command register
+ * are asynchronous. After that, bit 7 shall be sampled when the driver is not
+ * writing to the command register. So it is suggested to read this register only
+ * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
+ * of the error bits (0-4) is set to 1. The command not issued by auto CMD12
+ * error does not generate an interrupt.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_AC12ERR register
+ */
+/*@{*/
+#define SDHC_RD_AC12ERR(base)    (SDHC_AC12ERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_AC12ERR bitfields
+ */
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
+ *
+ * If memory multiple block data transfer is not started, due to a command
+ * error, this bit is not set because it is not necessary to issue an auto CMD12.
+ * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
+ * multiple block data transfer due to some error. If this bit is set to 1, other
+ * error status bits (1-4) have no meaning.
+ *
+ * Values:
+ * - 0b0 - Executed.
+ * - 0b1 - Not executed.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12NE field. */
+#define SDHC_RD_AC12ERR_AC12NE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12NE_MASK) >> SDHC_AC12ERR_AC12NE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12NE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12NE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
+ *
+ * Occurs if no response is returned within 64 SDCLK cycles from the end bit of
+ * the command. If this bit is set to 1, the other error status bits (2-4) have
+ * no meaning.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12TOE field. */
+#define SDHC_RD_AC12ERR_AC12TOE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12TOE_MASK) >> SDHC_AC12ERR_AC12TOE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12TOE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12TOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
+ *
+ * Occurs when detecting that the end bit of command response is 0 which must be
+ * 1.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - End bit error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12EBE field. */
+#define SDHC_RD_AC12ERR_AC12EBE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12EBE_MASK) >> SDHC_AC12ERR_AC12EBE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12EBE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12EBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
+ *
+ * Occurs when detecting a CRC error in the command response.
+ *
+ * Values:
+ * - 0b0 - No CRC error.
+ * - 0b1 - CRC error met in Auto CMD12 response.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12CE field. */
+#define SDHC_RD_AC12ERR_AC12CE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12CE_MASK) >> SDHC_AC12ERR_AC12CE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12CE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12CE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
+ *
+ * Occurs if the command index error occurs in response to a command.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error, the CMD index in response is not CMD12.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12IE field. */
+#define SDHC_RD_AC12ERR_AC12IE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12IE_MASK) >> SDHC_AC12ERR_AC12IE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12IE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12IE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
+ *
+ * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
+ * error (D04-D01) in this register.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Not issued.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field. */
+#define SDHC_RD_AC12ERR_CNIBAC12E(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_CNIBAC12E_MASK) >> SDHC_AC12ERR_CNIBAC12E_SHIFT)
+#define SDHC_BRD_AC12ERR_CNIBAC12E(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_CNIBAC12E_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_HTCAPBLT - Host Controller Capabilities
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_HTCAPBLT - Host Controller Capabilities (RO)
+ *
+ * Reset value: 0x07F30000U
+ *
+ * This register provides the host driver with information specific to the SDHC
+ * implementation. The value in this register is the power-on-reset value, and
+ * does not change with a software reset. Any write to this register is ignored.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_HTCAPBLT register
+ */
+/*@{*/
+#define SDHC_RD_HTCAPBLT(base)   (SDHC_HTCAPBLT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_HTCAPBLT bitfields
+ */
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
+ *
+ * This value indicates the maximum block size that the host driver can read and
+ * write to the buffer in the SDHC. The buffer shall transfer block size without
+ * wait cycles.
+ *
+ * Values:
+ * - 0b000 - 512 bytes
+ * - 0b001 - 1024 bytes
+ * - 0b010 - 2048 bytes
+ * - 0b011 - 4096 bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_MBL field. */
+#define SDHC_RD_HTCAPBLT_MBL(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_MBL_MASK) >> SDHC_HTCAPBLT_MBL_SHIFT)
+#define SDHC_BRD_HTCAPBLT_MBL(base) (SDHC_RD_HTCAPBLT_MBL(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
+ *
+ * This bit indicates whether the SDHC supports the ADMA feature.
+ *
+ * Values:
+ * - 0b0 - Advanced DMA not supported.
+ * - 0b1 - Advanced DMA supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field. */
+#define SDHC_RD_HTCAPBLT_ADMAS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_ADMAS_MASK) >> SDHC_HTCAPBLT_ADMAS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_ADMAS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_ADMAS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
+ *
+ * This bit indicates whether the SDHC supports high speed mode and the host
+ * system can supply a SD Clock frequency from 25 MHz to 50 MHz.
+ *
+ * Values:
+ * - 0b0 - High speed not supported.
+ * - 0b1 - High speed supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_HSS field. */
+#define SDHC_RD_HTCAPBLT_HSS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_HSS_MASK) >> SDHC_HTCAPBLT_HSS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_HSS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_HSS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
+ *
+ * This bit indicates whether the SDHC is capable of using the internal DMA to
+ * transfer data between system memory and the data buffer directly.
+ *
+ * Values:
+ * - 0b0 - DMA not supported.
+ * - 0b1 - DMA supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_DMAS field. */
+#define SDHC_RD_HTCAPBLT_DMAS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_DMAS_MASK) >> SDHC_HTCAPBLT_DMAS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_DMAS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_DMAS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
+ *
+ * This bit indicates whether the SDHC supports suspend / resume functionality.
+ * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
+ * are not supported, and the host driver shall not issue either suspend or
+ * resume commands.
+ *
+ * Values:
+ * - 0b0 - Not supported.
+ * - 0b1 - Supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_SRS field. */
+#define SDHC_RD_HTCAPBLT_SRS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_SRS_MASK) >> SDHC_HTCAPBLT_SRS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_SRS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_SRS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
+ *
+ * This bit shall depend on the host system ability.
+ *
+ * Values:
+ * - 0b0 - 3.3 V not supported.
+ * - 0b1 - 3.3 V supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_VS33 field. */
+#define SDHC_RD_HTCAPBLT_VS33(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_VS33_MASK) >> SDHC_HTCAPBLT_VS33_SHIFT)
+#define SDHC_BRD_HTCAPBLT_VS33(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_VS33_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_WML - Watermark Level Register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_WML - Watermark Level Register (RW)
+ *
+ * Reset value: 0x00100010U
+ *
+ * Both write and read watermark levels (FIFO threshold) are configurable. There
+ * value can range from 1 to 128 words. Both write and read burst lengths are
+ * also configurable. There value can range from 1 to 31 words.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_WML register
+ */
+/*@{*/
+#define SDHC_RD_WML(base)        (SDHC_WML_REG(base))
+#define SDHC_WR_WML(base, value) (SDHC_WML_REG(base) = (value))
+#define SDHC_RMW_WML(base, mask, value) (SDHC_WR_WML(base, (SDHC_RD_WML(base) & ~(mask)) | (value)))
+#define SDHC_SET_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) |  (value)))
+#define SDHC_CLR_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) & ~(value)))
+#define SDHC_TOG_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_WML bitfields
+ */
+
+/*!
+ * @name Register SDHC_WML, field RDWML[7:0] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * read operation. Also the number of words as a sequence of read bursts in
+ * back-to-back mode. The maximum legal value for the read water mark level is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_WML_RDWML field. */
+#define SDHC_RD_WML_RDWML(base) ((SDHC_WML_REG(base) & SDHC_WML_RDWML_MASK) >> SDHC_WML_RDWML_SHIFT)
+#define SDHC_BRD_WML_RDWML(base) (SDHC_RD_WML_RDWML(base))
+
+/*! @brief Set the RDWML field to a new value. */
+#define SDHC_WR_WML_RDWML(base, value) (SDHC_RMW_WML(base, SDHC_WML_RDWML_MASK, SDHC_WML_RDWML(value)))
+#define SDHC_BWR_WML_RDWML(base, value) (SDHC_WR_WML_RDWML(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_WML, field WRWML[23:16] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * write operation. Also the number of words as a sequence of write bursts in
+ * back-to-back mode. The maximum legal value for the write watermark level is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_WML_WRWML field. */
+#define SDHC_RD_WML_WRWML(base) ((SDHC_WML_REG(base) & SDHC_WML_WRWML_MASK) >> SDHC_WML_WRWML_SHIFT)
+#define SDHC_BRD_WML_WRWML(base) (SDHC_RD_WML_WRWML(base))
+
+/*! @brief Set the WRWML field to a new value. */
+#define SDHC_WR_WML_WRWML(base, value) (SDHC_RMW_WML(base, SDHC_WML_WRWML_MASK, SDHC_WML_WRWML(value)))
+#define SDHC_BWR_WML_WRWML(base, value) (SDHC_WR_WML_WRWML(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_FEVT - Force Event register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_FEVT - Force Event register (WO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Force Event (FEVT) register is not a physically implemented register.
+ * Rather, it is an address at which the Interrupt Status register can be written if
+ * the corresponding bit of the Interrupt Status Enable register is set. This
+ * register is a write only register and writing 0 to it has no effect. Writing 1
+ * to this register actually sets the corresponding bit of Interrupt Status
+ * register. A read from this register always results in 0's. To change the
+ * corresponding status bits in the interrupt status register, make sure to set
+ * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
+ * short pulse on the DAT[1] line, and the driver may treat this interrupt as a
+ * normal interrupt. The interrupt service routine may skip polling the card
+ * interrupt factor as the interrupt is selfcleared.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_FEVT register
+ */
+/*@{*/
+#define SDHC_RD_FEVT(base)       (SDHC_FEVT_REG(base))
+#define SDHC_WR_FEVT(base, value) (SDHC_FEVT_REG(base) = (value))
+#define SDHC_RMW_FEVT(base, mask, value) (SDHC_WR_FEVT(base, (SDHC_RD_FEVT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_FEVT bitfields
+ */
+
+/*!
+ * @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
+ *
+ * Forces AC12ERR[AC12NE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12NE field to a new value. */
+#define SDHC_WR_FEVT_AC12NE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12NE_MASK, SDHC_FEVT_AC12NE(value)))
+#define SDHC_BWR_FEVT_AC12NE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12NE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
+ *
+ * Forces AC12ERR[AC12TOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12TOE field to a new value. */
+#define SDHC_WR_FEVT_AC12TOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12TOE_MASK, SDHC_FEVT_AC12TOE(value)))
+#define SDHC_BWR_FEVT_AC12TOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12TOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
+ *
+ * Forces AC12ERR[AC12CE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12CE field to a new value. */
+#define SDHC_WR_FEVT_AC12CE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12CE_MASK, SDHC_FEVT_AC12CE(value)))
+#define SDHC_BWR_FEVT_AC12CE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12CE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
+ *
+ * Forces AC12ERR[AC12EBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12EBE field to a new value. */
+#define SDHC_WR_FEVT_AC12EBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12EBE_MASK, SDHC_FEVT_AC12EBE(value)))
+#define SDHC_BWR_FEVT_AC12EBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12EBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
+ *
+ * Forces AC12ERR[AC12IE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12IE field to a new value. */
+#define SDHC_WR_FEVT_AC12IE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12IE_MASK, SDHC_FEVT_AC12IE(value)))
+#define SDHC_BWR_FEVT_AC12IE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
+ *
+ * Forces AC12ERR[CNIBAC12E] to be set.
+ */
+/*@{*/
+/*! @brief Set the CNIBAC12E field to a new value. */
+#define SDHC_WR_FEVT_CNIBAC12E(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CNIBAC12E_MASK, SDHC_FEVT_CNIBAC12E(value)))
+#define SDHC_BWR_FEVT_CNIBAC12E(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CNIBAC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CTOE[16] (WORZ)
+ *
+ * Forces IRQSTAT[CTOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CTOE field to a new value. */
+#define SDHC_WR_FEVT_CTOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CTOE_MASK, SDHC_FEVT_CTOE(value)))
+#define SDHC_BWR_FEVT_CTOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CCE[17] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CCE field to a new value. */
+#define SDHC_WR_FEVT_CCE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CCE_MASK, SDHC_FEVT_CCE(value)))
+#define SDHC_BWR_FEVT_CCE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CEBE[18] (WORZ)
+ *
+ * Forces IRQSTAT[CEBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CEBE field to a new value. */
+#define SDHC_WR_FEVT_CEBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CEBE_MASK, SDHC_FEVT_CEBE(value)))
+#define SDHC_BWR_FEVT_CEBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CIE[19] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CIE field to a new value. */
+#define SDHC_WR_FEVT_CIE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CIE_MASK, SDHC_FEVT_CIE(value)))
+#define SDHC_BWR_FEVT_CIE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DTOE[20] (WORZ)
+ *
+ * Forces IRQSTAT[DTOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DTOE field to a new value. */
+#define SDHC_WR_FEVT_DTOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DTOE_MASK, SDHC_FEVT_DTOE(value)))
+#define SDHC_BWR_FEVT_DTOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DCE[21] (WORZ)
+ *
+ * Forces IRQSTAT[DCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DCE field to a new value. */
+#define SDHC_WR_FEVT_DCE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DCE_MASK, SDHC_FEVT_DCE(value)))
+#define SDHC_BWR_FEVT_DCE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DEBE[22] (WORZ)
+ *
+ * Forces IRQSTAT[DEBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DEBE field to a new value. */
+#define SDHC_WR_FEVT_DEBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DEBE_MASK, SDHC_FEVT_DEBE(value)))
+#define SDHC_BWR_FEVT_DEBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12E[24] (WORZ)
+ *
+ * Forces IRQSTAT[AC12E] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12E field to a new value. */
+#define SDHC_WR_FEVT_AC12E(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12E_MASK, SDHC_FEVT_AC12E(value)))
+#define SDHC_BWR_FEVT_AC12E(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DMAE[28] (WORZ)
+ *
+ * Forces the DMAE bit of Interrupt Status Register to be set.
+ */
+/*@{*/
+/*! @brief Set the DMAE field to a new value. */
+#define SDHC_WR_FEVT_DMAE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DMAE_MASK, SDHC_FEVT_DMAE(value)))
+#define SDHC_BWR_FEVT_DMAE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DMAE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CINT[31] (WORZ)
+ *
+ * Writing 1 to this bit generates a short low-level pulse on the internal
+ * DAT[1] line, as if a self-clearing interrupt was received from the external card.
+ * If enabled, the CINT bit will be set and the interrupt service routine may
+ * treat this interrupt as a normal interrupt from the external card.
+ */
+/*@{*/
+/*! @brief Set the CINT field to a new value. */
+#define SDHC_WR_FEVT_CINT(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CINT_MASK, SDHC_FEVT_CINT(value)))
+#define SDHC_BWR_FEVT_CINT(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CINT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_ADMAES - ADMA Error Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_ADMAES - ADMA Error Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an ADMA error interrupt has occurred, the ADMA Error States field in
+ * this register holds the ADMA state and the ADMA System Address register holds the
+ * address around the error descriptor. For recovering from this error, the host
+ * driver requires the ADMA state to identify the error descriptor address as
+ * follows: ST_STOP: Previous location set in the ADMA System Address register is
+ * the error descriptor address. ST_FDS: Current location set in the ADMA System
+ * Address register is the error descriptor address. ST_CADR: This state is never
+ * set because it only increments the descriptor pointer and doesn't generate an
+ * ADMA error. ST_TFR: Previous location set in the ADMA System Address register
+ * is the error descriptor address. In case of a write operation, the host driver
+ * must use the ACMD22 to get the number of the written block, rather than using
+ * this information, because unwritten data may exist in the host controller.
+ * The host controller generates the ADMA error interrupt when it detects invalid
+ * descriptor data (valid = 0) in the ST_FDS state. The host driver can
+ * distinguish this error by reading the valid bit of the error descriptor. ADMA Error
+ * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
+ * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
+ * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
+ * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
+ * (Transfer Data) Holds the address of the next executable descriptor command
+ */
+/*!
+ * @name Constants and macros for entire SDHC_ADMAES register
+ */
+/*@{*/
+#define SDHC_RD_ADMAES(base)     (SDHC_ADMAES_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_ADMAES bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
+ *
+ * Indicates the state of the ADMA when an error has occurred during an ADMA
+ * data transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMAES field. */
+#define SDHC_RD_ADMAES_ADMAES(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMAES_MASK) >> SDHC_ADMAES_ADMAES_SHIFT)
+#define SDHC_BRD_ADMAES_ADMAES(base) (SDHC_RD_ADMAES_ADMAES(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMALME[2] (RO)
+ *
+ * This error occurs in the following 2 cases: While the block count enable is
+ * being set, the total data length specified by the descriptor table is different
+ * from that specified by the block count and block length. Total data length
+ * can not be divided by the block length.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMALME field. */
+#define SDHC_RD_ADMAES_ADMALME(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMALME_MASK) >> SDHC_ADMAES_ADMALME_SHIFT)
+#define SDHC_BRD_ADMAES_ADMALME(base) (BITBAND_ACCESS32(&SDHC_ADMAES_REG(base), SDHC_ADMAES_ADMALME_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
+ *
+ * This error occurs when an invalid descriptor is fetched by ADMA.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMADCE field. */
+#define SDHC_RD_ADMAES_ADMADCE(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMADCE_MASK) >> SDHC_ADMAES_ADMADCE_SHIFT)
+#define SDHC_BRD_ADMAES_ADMADCE(base) (BITBAND_ACCESS32(&SDHC_ADMAES_REG(base), SDHC_ADMAES_ADMADCE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_ADSADDR - ADMA System Addressregister
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_ADSADDR - ADMA System Addressregister (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for ADMA
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_ADSADDR register
+ */
+/*@{*/
+#define SDHC_RD_ADSADDR(base)    (SDHC_ADSADDR_REG(base))
+#define SDHC_WR_ADSADDR(base, value) (SDHC_ADSADDR_REG(base) = (value))
+#define SDHC_RMW_ADSADDR(base, mask, value) (SDHC_WR_ADSADDR(base, (SDHC_RD_ADSADDR(base) & ~(mask)) | (value)))
+#define SDHC_SET_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) |  (value)))
+#define SDHC_CLR_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) & ~(value)))
+#define SDHC_TOG_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_ADSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
+ *
+ * Holds the word address of the executing command in the descriptor table. At
+ * the start of ADMA, the host driver shall set the start address of the
+ * Descriptor table. The ADMA engine increments this register address whenever fetching a
+ * descriptor command. When the ADMA is stopped at the block gap, this register
+ * indicates the address of the next executable descriptor command. When the ADMA
+ * error interrupt is generated, this register shall hold the valid descriptor
+ * address depending on the ADMA state. The lower 2 bits of this register is tied
+ * to '0' so the ADMA address is always word-aligned. Because this register
+ * supports dynamic address reflecting, when TC bit is set, it automatically alters the
+ * value of internal address counter, so SW cannot change this register when TC
+ * bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADSADDR_ADSADDR field. */
+#define SDHC_RD_ADSADDR_ADSADDR(base) ((SDHC_ADSADDR_REG(base) & SDHC_ADSADDR_ADSADDR_MASK) >> SDHC_ADSADDR_ADSADDR_SHIFT)
+#define SDHC_BRD_ADSADDR_ADSADDR(base) (SDHC_RD_ADSADDR_ADSADDR(base))
+
+/*! @brief Set the ADSADDR field to a new value. */
+#define SDHC_WR_ADSADDR_ADSADDR(base, value) (SDHC_RMW_ADSADDR(base, SDHC_ADSADDR_ADSADDR_MASK, SDHC_ADSADDR_ADSADDR(value)))
+#define SDHC_BWR_ADSADDR_ADSADDR(base, value) (SDHC_WR_ADSADDR_ADSADDR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_VENDOR - Vendor Specific register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_VENDOR - Vendor Specific register (RW)
+ *
+ * Reset value: 0x00000001U
+ *
+ * This register contains the vendor-specific control/status register.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_VENDOR register
+ */
+/*@{*/
+#define SDHC_RD_VENDOR(base)     (SDHC_VENDOR_REG(base))
+#define SDHC_WR_VENDOR(base, value) (SDHC_VENDOR_REG(base) = (value))
+#define SDHC_RMW_VENDOR(base, mask, value) (SDHC_WR_VENDOR(base, (SDHC_RD_VENDOR(base) & ~(mask)) | (value)))
+#define SDHC_SET_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) |  (value)))
+#define SDHC_CLR_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) & ~(value)))
+#define SDHC_TOG_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_VENDOR bitfields
+ */
+
+/*!
+ * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
+ *
+ * Enables the request to external DMA. When the internal DMA (either simple DMA
+ * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
+ * request when the internal buffer is ready. This bit is particularly useful when
+ * transferring data by CPU polling mode, and it is not allowed to send out the
+ * external DMA request. By default, this bit is set.
+ *
+ * Values:
+ * - 0b0 - In any scenario, SDHC does not send out the external DMA request.
+ * - 0b1 - When internal DMA is not active, the external DMA request will be
+ *     sent out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field. */
+#define SDHC_RD_VENDOR_EXTDMAEN(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_EXTDMAEN_MASK) >> SDHC_VENDOR_EXTDMAEN_SHIFT)
+#define SDHC_BRD_VENDOR_EXTDMAEN(base) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXTDMAEN_SHIFT))
+
+/*! @brief Set the EXTDMAEN field to a new value. */
+#define SDHC_WR_VENDOR_EXTDMAEN(base, value) (SDHC_RMW_VENDOR(base, SDHC_VENDOR_EXTDMAEN_MASK, SDHC_VENDOR_EXTDMAEN(value)))
+#define SDHC_BWR_VENDOR_EXTDMAEN(base, value) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXTDMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
+ *
+ * This bit must be set before S/W issues CMD53 multi-block read with exact
+ * block number. This bit must not be set if the CMD53 multi-block read is not exact
+ * block number.
+ *
+ * Values:
+ * - 0b0 - None exact block read.
+ * - 0b1 - Exact block read for SDIO CMD53.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_EXBLKNU field. */
+#define SDHC_RD_VENDOR_EXBLKNU(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_EXBLKNU_MASK) >> SDHC_VENDOR_EXBLKNU_SHIFT)
+#define SDHC_BRD_VENDOR_EXBLKNU(base) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXBLKNU_SHIFT))
+
+/*! @brief Set the EXBLKNU field to a new value. */
+#define SDHC_WR_VENDOR_EXBLKNU(base, value) (SDHC_RMW_VENDOR(base, SDHC_VENDOR_EXBLKNU_MASK, SDHC_VENDOR_EXBLKNU(value)))
+#define SDHC_BWR_VENDOR_EXBLKNU(base, value) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXBLKNU_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
+ *
+ * Internal state value, reflecting the corresponding state value selected by
+ * Debug Select field. This field is read-only and write to this field does not
+ * have effect.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_INTSTVAL field. */
+#define SDHC_RD_VENDOR_INTSTVAL(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_INTSTVAL_MASK) >> SDHC_VENDOR_INTSTVAL_SHIFT)
+#define SDHC_BRD_VENDOR_INTSTVAL(base) (SDHC_RD_VENDOR_INTSTVAL(base))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_MMCBOOT - MMC Boot register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_MMCBOOT - MMC Boot register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the MMC fast boot control register.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_MMCBOOT register
+ */
+/*@{*/
+#define SDHC_RD_MMCBOOT(base)    (SDHC_MMCBOOT_REG(base))
+#define SDHC_WR_MMCBOOT(base, value) (SDHC_MMCBOOT_REG(base) = (value))
+#define SDHC_RMW_MMCBOOT(base, mask, value) (SDHC_WR_MMCBOOT(base, (SDHC_RD_MMCBOOT(base) & ~(mask)) | (value)))
+#define SDHC_SET_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) |  (value)))
+#define SDHC_CLR_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) & ~(value)))
+#define SDHC_TOG_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_MMCBOOT bitfields
+ */
+
+/*!
+ * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
+ *
+ * Values:
+ * - 0b0000 - SDCLK x 2^8
+ * - 0b0001 - SDCLK x 2^9
+ * - 0b0010 - SDCLK x 2^10
+ * - 0b0011 - SDCLK x 2^11
+ * - 0b0100 - SDCLK x 2^12
+ * - 0b0101 - SDCLK x 2^13
+ * - 0b0110 - SDCLK x 2^14
+ * - 0b0111 - SDCLK x 2^15
+ * - 0b1110 - SDCLK x 2^22
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field. */
+#define SDHC_RD_MMCBOOT_DTOCVACK(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_DTOCVACK_MASK) >> SDHC_MMCBOOT_DTOCVACK_SHIFT)
+#define SDHC_BRD_MMCBOOT_DTOCVACK(base) (SDHC_RD_MMCBOOT_DTOCVACK(base))
+
+/*! @brief Set the DTOCVACK field to a new value. */
+#define SDHC_WR_MMCBOOT_DTOCVACK(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_DTOCVACK_MASK, SDHC_MMCBOOT_DTOCVACK(value)))
+#define SDHC_BWR_MMCBOOT_DTOCVACK(base, value) (SDHC_WR_MMCBOOT_DTOCVACK(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
+ *
+ * Values:
+ * - 0b0 - No ack.
+ * - 0b1 - Ack.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field. */
+#define SDHC_RD_MMCBOOT_BOOTACK(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTACK_MASK) >> SDHC_MMCBOOT_BOOTACK_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTACK(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTACK_SHIFT))
+
+/*! @brief Set the BOOTACK field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTACK(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTACK_MASK, SDHC_MMCBOOT_BOOTACK(value)))
+#define SDHC_BWR_MMCBOOT_BOOTACK(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal boot.
+ * - 0b1 - Alternative boot.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field. */
+#define SDHC_RD_MMCBOOT_BOOTMODE(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTMODE_MASK) >> SDHC_MMCBOOT_BOOTMODE_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTMODE(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTMODE_SHIFT))
+
+/*! @brief Set the BOOTMODE field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTMODE(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTMODE_MASK, SDHC_MMCBOOT_BOOTMODE(value)))
+#define SDHC_BWR_MMCBOOT_BOOTMODE(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Fast boot disable.
+ * - 0b1 - Fast boot enable.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field. */
+#define SDHC_RD_MMCBOOT_BOOTEN(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTEN_MASK) >> SDHC_MMCBOOT_BOOTEN_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTEN(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTEN_SHIFT))
+
+/*! @brief Set the BOOTEN field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTEN(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTEN_MASK, SDHC_MMCBOOT_BOOTEN(value)))
+#define SDHC_BWR_MMCBOOT_BOOTEN(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
+ *
+ * When boot, enable auto stop at block gap function. This function will be
+ * triggered, and host will stop at block gap when received card block cnt is equal
+ * to BOOTBLKCNT.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field. */
+#define SDHC_RD_MMCBOOT_AUTOSABGEN(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_AUTOSABGEN_MASK) >> SDHC_MMCBOOT_AUTOSABGEN_SHIFT)
+#define SDHC_BRD_MMCBOOT_AUTOSABGEN(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_AUTOSABGEN_SHIFT))
+
+/*! @brief Set the AUTOSABGEN field to a new value. */
+#define SDHC_WR_MMCBOOT_AUTOSABGEN(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_AUTOSABGEN_MASK, SDHC_MMCBOOT_AUTOSABGEN(value)))
+#define SDHC_BWR_MMCBOOT_AUTOSABGEN(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_AUTOSABGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
+ *
+ * Defines the stop at block gap value of automatic mode. When received card
+ * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field. */
+#define SDHC_RD_MMCBOOT_BOOTBLKCNT(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTBLKCNT_MASK) >> SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTBLKCNT(base) (SDHC_RD_MMCBOOT_BOOTBLKCNT(base))
+
+/*! @brief Set the BOOTBLKCNT field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTBLKCNT(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTBLKCNT_MASK, SDHC_MMCBOOT_BOOTBLKCNT(value)))
+#define SDHC_BWR_MMCBOOT_BOOTBLKCNT(base, value) (SDHC_WR_MMCBOOT_BOOTBLKCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_HOSTVER - Host Controller Version
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_HOSTVER - Host Controller Version (RO)
+ *
+ * Reset value: 0x00001201U
+ *
+ * This register contains the vendor host controller version information. All
+ * bits are read only and will read the same as the power-reset value.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_HOSTVER register
+ */
+/*@{*/
+#define SDHC_RD_HOSTVER(base)    (SDHC_HOSTVER_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_HOSTVER bitfields
+ */
+
+/*!
+ * @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
+ *
+ * These status bits indicate the host controller specification version.
+ *
+ * Values:
+ * - 0b00000001 - SD host specification version 2.0, supports test event
+ *     register and ADMA.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HOSTVER_SVN field. */
+#define SDHC_RD_HOSTVER_SVN(base) ((SDHC_HOSTVER_REG(base) & SDHC_HOSTVER_SVN_MASK) >> SDHC_HOSTVER_SVN_SHIFT)
+#define SDHC_BRD_HOSTVER_SVN(base) (SDHC_RD_HOSTVER_SVN(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
+ *
+ * These status bits are reserved for the vendor version number. The host driver
+ * shall not use this status.
+ *
+ * Values:
+ * - 0b00000000 - Freescale SDHC version 1.0
+ * - 0b00010000 - Freescale SDHC version 2.0
+ * - 0b00010001 - Freescale SDHC version 2.1
+ * - 0b00010010 - Freescale SDHC version 2.2
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HOSTVER_VVN field. */
+#define SDHC_RD_HOSTVER_VVN(base) ((SDHC_HOSTVER_REG(base) & SDHC_HOSTVER_VVN_MASK) >> SDHC_HOSTVER_VVN_SHIFT)
+#define SDHC_BRD_HOSTVER_VVN(base) (SDHC_RD_HOSTVER_VVN(base))
+/*@}*/
+
+/*
+ * MK64F12 SIM
+ *
+ * System Integration Module
+ *
+ * Registers defined in this header file:
+ * - SIM_SOPT1 - System Options Register 1
+ * - SIM_SOPT1CFG - SOPT1 Configuration Register
+ * - SIM_SOPT2 - System Options Register 2
+ * - SIM_SOPT4 - System Options Register 4
+ * - SIM_SOPT5 - System Options Register 5
+ * - SIM_SOPT7 - System Options Register 7
+ * - SIM_SDID - System Device Identification Register
+ * - SIM_SCGC1 - System Clock Gating Control Register 1
+ * - SIM_SCGC2 - System Clock Gating Control Register 2
+ * - SIM_SCGC3 - System Clock Gating Control Register 3
+ * - SIM_SCGC4 - System Clock Gating Control Register 4
+ * - SIM_SCGC5 - System Clock Gating Control Register 5
+ * - SIM_SCGC6 - System Clock Gating Control Register 6
+ * - SIM_SCGC7 - System Clock Gating Control Register 7
+ * - SIM_CLKDIV1 - System Clock Divider Register 1
+ * - SIM_CLKDIV2 - System Clock Divider Register 2
+ * - SIM_FCFG1 - Flash Configuration Register 1
+ * - SIM_FCFG2 - Flash Configuration Register 2
+ * - SIM_UIDH - Unique Identification Register High
+ * - SIM_UIDMH - Unique Identification Register Mid-High
+ * - SIM_UIDML - Unique Identification Register Mid Low
+ * - SIM_UIDL - Unique Identification Register Low
+ */
+
+#define SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */
+#define SIM_IDX (0U) /*!< Instance number for SIM. */
+
+/*******************************************************************************
+ * SIM_SOPT1 - System Options Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1 - System Options Register 1 (RW)
+ *
+ * Reset value: 0x80000000U
+ *
+ * The SOPT1 register is only reset on POR or LVD.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1 register
+ */
+/*@{*/
+#define SIM_RD_SOPT1(base)       (SIM_SOPT1_REG(base))
+#define SIM_WR_SOPT1(base, value) (SIM_SOPT1_REG(base) = (value))
+#define SIM_RMW_SOPT1(base, mask, value) (SIM_WR_SOPT1(base, (SIM_RD_SOPT1(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) |  (value)))
+#define SIM_CLR_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) & ~(value)))
+#define SIM_TOG_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
+ *
+ * This field specifies the amount of system RAM available on the device.
+ *
+ * Values:
+ * - 0b0001 - 8 KB
+ * - 0b0011 - 16 KB
+ * - 0b0100 - 24 KB
+ * - 0b0101 - 32 KB
+ * - 0b0110 - 48 KB
+ * - 0b0111 - 64 KB
+ * - 0b1000 - 96 KB
+ * - 0b1001 - 128 KB
+ * - 0b1011 - 256 KB
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */
+#define SIM_RD_SOPT1_RAMSIZE(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_RAMSIZE_MASK) >> SIM_SOPT1_RAMSIZE_SHIFT)
+#define SIM_BRD_SOPT1_RAMSIZE(base) (SIM_RD_SOPT1_RAMSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
+ *
+ * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
+ * only on POR/LVD.
+ *
+ * Values:
+ * - 0b00 - System oscillator (OSC32KCLK)
+ * - 0b01 - Reserved
+ * - 0b10 - RTC 32.768kHz oscillator
+ * - 0b11 - LPO 1 kHz
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */
+#define SIM_RD_SOPT1_OSC32KSEL(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
+#define SIM_BRD_SOPT1_OSC32KSEL(base) (SIM_RD_SOPT1_OSC32KSEL(base))
+
+/*! @brief Set the OSC32KSEL field to a new value. */
+#define SIM_WR_SOPT1_OSC32KSEL(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_OSC32KSEL_MASK, SIM_SOPT1_OSC32KSEL(value)))
+#define SIM_BWR_SOPT1_OSC32KSEL(base, value) (SIM_WR_SOPT1_OSC32KSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * VLPR and VLPW modes.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator not in standby during VLPR and VLPW modes.
+ * - 0b1 - USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */
+#define SIM_RD_SOPT1_USBVSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBVSTBY_MASK) >> SIM_SOPT1_USBVSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBVSTBY(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT))
+
+/*! @brief Set the USBVSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBVSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBVSTBY_MASK, SIM_SOPT1_USBVSTBY(value)))
+#define SIM_BWR_SOPT1_USBVSTBY(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * Stop, VLPS, LLS and VLLS modes.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ * - 0b1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */
+#define SIM_RD_SOPT1_USBSSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBSSTBY_MASK) >> SIM_SOPT1_USBSSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBSSTBY(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT))
+
+/*! @brief Set the USBSSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBSSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBSSTBY_MASK, SIM_SOPT1_USBSSTBY(value)))
+#define SIM_BWR_SOPT1_USBSSTBY(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
+ *
+ * Controls whether the USB voltage regulator is enabled.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator is disabled.
+ * - 0b1 - USB voltage regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */
+#define SIM_RD_SOPT1_USBREGEN(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBREGEN_MASK) >> SIM_SOPT1_USBREGEN_SHIFT)
+#define SIM_BRD_SOPT1_USBREGEN(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT))
+
+/*! @brief Set the USBREGEN field to a new value. */
+#define SIM_WR_SOPT1_USBREGEN(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBREGEN_MASK, SIM_SOPT1_USBREGEN(value)))
+#define SIM_BWR_SOPT1_USBREGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT1CFG - SOPT1 Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The SOPT1CFG register is reset on System Reset not VLLS.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1CFG register
+ */
+/*@{*/
+#define SIM_RD_SOPT1CFG(base)    (SIM_SOPT1CFG_REG(base))
+#define SIM_WR_SOPT1CFG(base, value) (SIM_SOPT1CFG_REG(base) = (value))
+#define SIM_RMW_SOPT1CFG(base, mask, value) (SIM_WR_SOPT1CFG(base, (SIM_RD_SOPT1CFG(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) |  (value)))
+#define SIM_CLR_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) & ~(value)))
+#define SIM_TOG_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1CFG bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
+ *
+ * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
+ * register bit clears after a write to USBREGEN.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBREGEN cannot be written.
+ * - 0b1 - SOPT1 USBREGEN can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */
+#define SIM_RD_SOPT1CFG_URWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_URWE_MASK) >> SIM_SOPT1CFG_URWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_URWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT))
+
+/*! @brief Set the URWE field to a new value. */
+#define SIM_WR_SOPT1CFG_URWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_URWE_MASK, SIM_SOPT1CFG_URWE(value)))
+#define SIM_BWR_SOPT1CFG_URWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
+ *
+ * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
+ * This register bit clears after a write to USBVSTBY.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBVSTBY cannot be written.
+ * - 0b1 - SOPT1 USBVSTBY can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */
+#define SIM_RD_SOPT1CFG_UVSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_UVSWE_MASK) >> SIM_SOPT1CFG_UVSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_UVSWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT))
+
+/*! @brief Set the UVSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_UVSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_UVSWE_MASK, SIM_SOPT1CFG_UVSWE(value)))
+#define SIM_BWR_SOPT1CFG_UVSWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
+ *
+ * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
+ * This register bit clears after a write to USBSSTBY.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBSSTBY cannot be written.
+ * - 0b1 - SOPT1 USBSSTBY can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */
+#define SIM_RD_SOPT1CFG_USSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_USSWE_MASK) >> SIM_SOPT1CFG_USSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_USSWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT))
+
+/*! @brief Set the USSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_USSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_USSWE_MASK, SIM_SOPT1CFG_USSWE(value)))
+#define SIM_BWR_SOPT1CFG_USSWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT2 - System Options Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT2 - System Options Register 2 (RW)
+ *
+ * Reset value: 0x00001000U
+ *
+ * SOPT2 contains the controls for selecting many of the module clock source
+ * options on this device. See the Clock Distribution chapter for more information
+ * including clocking diagrams and definitions of device clocks.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT2 register
+ */
+/*@{*/
+#define SIM_RD_SOPT2(base)       (SIM_SOPT2_REG(base))
+#define SIM_WR_SOPT2(base, value) (SIM_SOPT2_REG(base) = (value))
+#define SIM_RMW_SOPT2(base, mask, value) (SIM_WR_SOPT2(base, (SIM_RD_SOPT2(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) |  (value)))
+#define SIM_CLR_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) & ~(value)))
+#define SIM_TOG_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
+ *
+ * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
+ * RTC_CLKOUT pin.
+ *
+ * Values:
+ * - 0b0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
+ * - 0b1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */
+#define SIM_RD_SOPT2_RTCCLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RTCCLKOUTSEL_MASK) >> SIM_SOPT2_RTCCLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_RTCCLKOUTSEL(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT))
+
+/*! @brief Set the RTCCLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_RTCCLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RTCCLKOUTSEL_MASK, SIM_SOPT2_RTCCLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_RTCCLKOUTSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
+ *
+ * Selects the clock to output on the CLKOUT pin.
+ *
+ * Values:
+ * - 0b000 - FlexBus CLKOUT
+ * - 0b001 - Reserved
+ * - 0b010 - Flash clock
+ * - 0b011 - LPO clock (1 kHz)
+ * - 0b100 - MCGIRCLK
+ * - 0b101 - RTC 32.768kHz clock
+ * - 0b110 - OSCERCLK0
+ * - 0b111 - IRC 48 MHz clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */
+#define SIM_RD_SOPT2_CLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_CLKOUTSEL_MASK) >> SIM_SOPT2_CLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_CLKOUTSEL(base) (SIM_RD_SOPT2_CLKOUTSEL(base))
+
+/*! @brief Set the CLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_CLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_CLKOUTSEL_MASK, SIM_SOPT2_CLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_CLKOUTSEL(base, value) (SIM_WR_SOPT2_CLKOUTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
+ *
+ * If flash security is enabled, then this field affects what CPU operations can
+ * access off-chip via the FlexBus interface. This field has no effect if flash
+ * security is not enabled.
+ *
+ * Values:
+ * - 0b00 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 0b01 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 0b10 - Off-chip instruction accesses are disallowed. Data accesses are
+ *     allowed.
+ * - 0b11 - Off-chip instruction accesses and data accesses are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_FBSL field. */
+#define SIM_RD_SOPT2_FBSL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_FBSL_MASK) >> SIM_SOPT2_FBSL_SHIFT)
+#define SIM_BRD_SOPT2_FBSL(base) (SIM_RD_SOPT2_FBSL(base))
+
+/*! @brief Set the FBSL field to a new value. */
+#define SIM_WR_SOPT2_FBSL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_FBSL_MASK, SIM_SOPT2_FBSL(value)))
+#define SIM_BWR_SOPT2_FBSL(base, value) (SIM_WR_SOPT2_FBSL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
+ *
+ * Controls the output drive strength of the PTD7 pin by selecting either one or
+ * two pads to drive it.
+ *
+ * Values:
+ * - 0b0 - Single-pad drive strength for PTD7.
+ * - 0b1 - Double pad drive strength for PTD7.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_PTD7PAD field. */
+#define SIM_RD_SOPT2_PTD7PAD(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_PTD7PAD_MASK) >> SIM_SOPT2_PTD7PAD_SHIFT)
+#define SIM_BRD_SOPT2_PTD7PAD(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_PTD7PAD_SHIFT))
+
+/*! @brief Set the PTD7PAD field to a new value. */
+#define SIM_WR_SOPT2_PTD7PAD(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_PTD7PAD_MASK, SIM_SOPT2_PTD7PAD(value)))
+#define SIM_BWR_SOPT2_PTD7PAD(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_PTD7PAD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
+ *
+ * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
+ * clock source.
+ *
+ * Values:
+ * - 0b0 - MCGOUTCLK
+ * - 0b1 - Core/system clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */
+#define SIM_RD_SOPT2_TRACECLKSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TRACECLKSEL_MASK) >> SIM_SOPT2_TRACECLKSEL_SHIFT)
+#define SIM_BRD_SOPT2_TRACECLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_TRACECLKSEL_SHIFT))
+
+/*! @brief Set the TRACECLKSEL field to a new value. */
+#define SIM_WR_SOPT2_TRACECLKSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TRACECLKSEL_MASK, SIM_SOPT2_TRACECLKSEL(value)))
+#define SIM_BWR_SOPT2_TRACECLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_TRACECLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
+ *
+ * Selects the high frequency clock for various peripheral clocking options.
+ *
+ * Values:
+ * - 0b00 - MCGFLLCLK clock
+ * - 0b01 - MCGPLLCLK clock
+ * - 0b10 - Reserved
+ * - 0b11 - IRC48 MHz clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */
+#define SIM_RD_SOPT2_PLLFLLSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
+#define SIM_BRD_SOPT2_PLLFLLSEL(base) (SIM_RD_SOPT2_PLLFLLSEL(base))
+
+/*! @brief Set the PLLFLLSEL field to a new value. */
+#define SIM_WR_SOPT2_PLLFLLSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_PLLFLLSEL_MASK, SIM_SOPT2_PLLFLLSEL(value)))
+#define SIM_BWR_SOPT2_PLLFLLSEL(base, value) (SIM_WR_SOPT2_PLLFLLSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field USBSRC[18] (RW)
+ *
+ * Selects the clock source for the USB 48 MHz clock.
+ *
+ * Values:
+ * - 0b0 - External bypass clock (USB_CLKIN).
+ * - 0b1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
+ *     SIM_CLKDIV2[USBFRAC, USBDIV].
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_USBSRC field. */
+#define SIM_RD_SOPT2_USBSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_USBSRC_MASK) >> SIM_SOPT2_USBSRC_SHIFT)
+#define SIM_BRD_SOPT2_USBSRC(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT))
+
+/*! @brief Set the USBSRC field to a new value. */
+#define SIM_WR_SOPT2_USBSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_USBSRC_MASK, SIM_SOPT2_USBSRC(value)))
+#define SIM_BWR_SOPT2_USBSRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field RMIISRC[19] (RW)
+ *
+ * Selects the clock source for the Ethernet RMII interface
+ *
+ * Values:
+ * - 0b0 - EXTAL clock
+ * - 0b1 - External bypass clock (ENET_1588_CLKIN).
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RMIISRC field. */
+#define SIM_RD_SOPT2_RMIISRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RMIISRC_MASK) >> SIM_SOPT2_RMIISRC_SHIFT)
+#define SIM_BRD_SOPT2_RMIISRC(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RMIISRC_SHIFT))
+
+/*! @brief Set the RMIISRC field to a new value. */
+#define SIM_WR_SOPT2_RMIISRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RMIISRC_MASK, SIM_SOPT2_RMIISRC(value)))
+#define SIM_BWR_SOPT2_RMIISRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RMIISRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
+ *
+ * Selects the clock source for the Ethernet timestamp clock.
+ *
+ * Values:
+ * - 0b00 - Core/system clock.
+ * - 0b01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 0b10 - OSCERCLK clock
+ * - 0b11 - External bypass clock (ENET_1588_CLKIN).
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TIMESRC field. */
+#define SIM_RD_SOPT2_TIMESRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TIMESRC_MASK) >> SIM_SOPT2_TIMESRC_SHIFT)
+#define SIM_BRD_SOPT2_TIMESRC(base) (SIM_RD_SOPT2_TIMESRC(base))
+
+/*! @brief Set the TIMESRC field to a new value. */
+#define SIM_WR_SOPT2_TIMESRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TIMESRC_MASK, SIM_SOPT2_TIMESRC(value)))
+#define SIM_BWR_SOPT2_TIMESRC(base, value) (SIM_WR_SOPT2_TIMESRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
+ *
+ * Selects the clock source for the SDHC clock .
+ *
+ * Values:
+ * - 0b00 - Core/system clock.
+ * - 0b01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 0b10 - OSCERCLK clock
+ * - 0b11 - External bypass clock (SDHC0_CLKIN)
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_SDHCSRC field. */
+#define SIM_RD_SOPT2_SDHCSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_SDHCSRC_MASK) >> SIM_SOPT2_SDHCSRC_SHIFT)
+#define SIM_BRD_SOPT2_SDHCSRC(base) (SIM_RD_SOPT2_SDHCSRC(base))
+
+/*! @brief Set the SDHCSRC field to a new value. */
+#define SIM_WR_SOPT2_SDHCSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_SDHCSRC_MASK, SIM_SOPT2_SDHCSRC(value)))
+#define SIM_BWR_SOPT2_SDHCSRC(base, value) (SIM_WR_SOPT2_SDHCSRC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT4 - System Options Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT4 - System Options Register 4 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT4 register
+ */
+/*@{*/
+#define SIM_RD_SOPT4(base)       (SIM_SOPT4_REG(base))
+#define SIM_WR_SOPT4(base, value) (SIM_SOPT4_REG(base) = (value))
+#define SIM_RMW_SOPT4(base, mask, value) (SIM_WR_SOPT4(base, (SIM_RD_SOPT4(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) |  (value)))
+#define SIM_CLR_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) & ~(value)))
+#define SIM_TOG_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
+ *
+ * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */
+#define SIM_RD_SOPT4_FTM0FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT0_MASK) >> SIM_SOPT4_FTM0FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT0_SHIFT))
+
+/*! @brief Set the FTM0FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT0_MASK, SIM_SOPT4_FTM0FLT0(value)))
+#define SIM_BWR_SOPT4_FTM0FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
+ *
+ * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT1 pin
+ * - 0b1 - CMP1 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */
+#define SIM_RD_SOPT4_FTM0FLT1(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT1_MASK) >> SIM_SOPT4_FTM0FLT1_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT1(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT1_SHIFT))
+
+/*! @brief Set the FTM0FLT1 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT1(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT1_MASK, SIM_SOPT4_FTM0FLT1(value)))
+#define SIM_BWR_SOPT4_FTM0FLT1(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
+ *
+ * Selects the source of FTM0 fault 2. The pin source for fault 2 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT2 pin
+ * - 0b1 - CMP2 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. */
+#define SIM_RD_SOPT4_FTM0FLT2(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT2_MASK) >> SIM_SOPT4_FTM0FLT2_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT2(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT2_SHIFT))
+
+/*! @brief Set the FTM0FLT2 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT2(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT2_MASK, SIM_SOPT4_FTM0FLT2(value)))
+#define SIM_BWR_SOPT4_FTM0FLT2(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
+ *
+ * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM1_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */
+#define SIM_RD_SOPT4_FTM1FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1FLT0_MASK) >> SIM_SOPT4_FTM1FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM1FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1FLT0_SHIFT))
+
+/*! @brief Set the FTM1FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM1FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1FLT0_MASK, SIM_SOPT4_FTM1FLT0(value)))
+#define SIM_BWR_SOPT4_FTM1FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
+ *
+ * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0b0 - FTM2_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */
+#define SIM_RD_SOPT4_FTM2FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2FLT0_MASK) >> SIM_SOPT4_FTM2FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM2FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2FLT0_SHIFT))
+
+/*! @brief Set the FTM2FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM2FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2FLT0_MASK, SIM_SOPT4_FTM2FLT0(value)))
+#define SIM_BWR_SOPT4_FTM2FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
+ *
+ * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0b0 - FTM3_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */
+#define SIM_RD_SOPT4_FTM3FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3FLT0_MASK) >> SIM_SOPT4_FTM3FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM3FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3FLT0_SHIFT))
+
+/*! @brief Set the FTM3FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM3FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3FLT0_MASK, SIM_SOPT4_FTM3FLT0(value)))
+#define SIM_BWR_SOPT4_FTM3FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
+ *
+ * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0b00 - FTM1_CH0 signal
+ * - 0b01 - CMP0 output
+ * - 0b10 - CMP1 output
+ * - 0b11 - USB start of frame pulse
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */
+#define SIM_RD_SOPT4_FTM1CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1CH0SRC_MASK) >> SIM_SOPT4_FTM1CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM1CH0SRC(base) (SIM_RD_SOPT4_FTM1CH0SRC(base))
+
+/*! @brief Set the FTM1CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM1CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1CH0SRC_MASK, SIM_SOPT4_FTM1CH0SRC(value)))
+#define SIM_BWR_SOPT4_FTM1CH0SRC(base, value) (SIM_WR_SOPT4_FTM1CH0SRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
+ *
+ * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0b00 - FTM2_CH0 signal
+ * - 0b01 - CMP0 output
+ * - 0b10 - CMP1 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */
+#define SIM_RD_SOPT4_FTM2CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2CH0SRC_MASK) >> SIM_SOPT4_FTM2CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM2CH0SRC(base) (SIM_RD_SOPT4_FTM2CH0SRC(base))
+
+/*! @brief Set the FTM2CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM2CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2CH0SRC_MASK, SIM_SOPT4_FTM2CH0SRC(value)))
+#define SIM_BWR_SOPT4_FTM2CH0SRC(base, value) (SIM_WR_SOPT4_FTM2CH0SRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM0 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM_CLK0 pin
+ * - 0b1 - FTM_CLK1 pin
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */
+#define SIM_RD_SOPT4_FTM0CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0CLKSEL_MASK) >> SIM_SOPT4_FTM0CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM0CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0CLKSEL_SHIFT))
+
+/*! @brief Set the FTM0CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM0CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0CLKSEL_MASK, SIM_SOPT4_FTM0CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM0CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM1 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM_CLK0 pin
+ * - 0b1 - FTM_CLK1 pin
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */
+#define SIM_RD_SOPT4_FTM1CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1CLKSEL_MASK) >> SIM_SOPT4_FTM1CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM1CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1CLKSEL_SHIFT))
+
+/*! @brief Set the FTM1CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM1CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1CLKSEL_MASK, SIM_SOPT4_FTM1CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM1CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM2 module. The
+ * selected pin must also be configured for the FTM2 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM2 external clock driven by FTM_CLK0 pin.
+ * - 0b1 - FTM2 external clock driven by FTM_CLK1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */
+#define SIM_RD_SOPT4_FTM2CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2CLKSEL_MASK) >> SIM_SOPT4_FTM2CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM2CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2CLKSEL_SHIFT))
+
+/*! @brief Set the FTM2CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM2CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2CLKSEL_MASK, SIM_SOPT4_FTM2CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM2CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM3 module. The
+ * selected pin must also be configured for the FTM3 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM3 external clock driven by FTM_CLK0 pin.
+ * - 0b1 - FTM3 external clock driven by FTM_CLK1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */
+#define SIM_RD_SOPT4_FTM3CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3CLKSEL_MASK) >> SIM_SOPT4_FTM3CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM3CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3CLKSEL_SHIFT))
+
+/*! @brief Set the FTM3CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM3CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3CLKSEL_MASK, SIM_SOPT4_FTM3CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM3CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 0.
+ *
+ * Values:
+ * - 0b0 - HSCMP0 output drives FTM0 hardware trigger 0
+ * - 0b1 - FTM1 channel match drives FTM0 hardware trigger 0
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */
+#define SIM_RD_SOPT4_FTM0TRG0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0TRG0SRC_MASK) >> SIM_SOPT4_FTM0TRG0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM0TRG0SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG0SRC_SHIFT))
+
+/*! @brief Set the FTM0TRG0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM0TRG0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0TRG0SRC_MASK, SIM_SOPT4_FTM0TRG0SRC(value)))
+#define SIM_BWR_SOPT4_FTM0TRG0SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG0SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 1.
+ *
+ * Values:
+ * - 0b0 - PDB output trigger 1 drives FTM0 hardware trigger 1
+ * - 0b1 - FTM2 channel match drives FTM0 hardware trigger 1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */
+#define SIM_RD_SOPT4_FTM0TRG1SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0TRG1SRC_MASK) >> SIM_SOPT4_FTM0TRG1SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM0TRG1SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG1SRC_SHIFT))
+
+/*! @brief Set the FTM0TRG1SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM0TRG1SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0TRG1SRC_MASK, SIM_SOPT4_FTM0TRG1SRC(value)))
+#define SIM_BWR_SOPT4_FTM0TRG1SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG1SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 0.
+ *
+ * Values:
+ * - 0b0 - Reserved
+ * - 0b1 - FTM1 channel match drives FTM3 hardware trigger 0
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */
+#define SIM_RD_SOPT4_FTM3TRG0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3TRG0SRC_MASK) >> SIM_SOPT4_FTM3TRG0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM3TRG0SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG0SRC_SHIFT))
+
+/*! @brief Set the FTM3TRG0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM3TRG0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3TRG0SRC_MASK, SIM_SOPT4_FTM3TRG0SRC(value)))
+#define SIM_BWR_SOPT4_FTM3TRG0SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG0SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 1.
+ *
+ * Values:
+ * - 0b0 - Reserved
+ * - 0b1 - FTM2 channel match drives FTM3 hardware trigger 1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */
+#define SIM_RD_SOPT4_FTM3TRG1SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3TRG1SRC_MASK) >> SIM_SOPT4_FTM3TRG1SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM3TRG1SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG1SRC_SHIFT))
+
+/*! @brief Set the FTM3TRG1SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM3TRG1SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3TRG1SRC_MASK, SIM_SOPT4_FTM3TRG1SRC(value)))
+#define SIM_BWR_SOPT4_FTM3TRG1SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG1SRC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT5 - System Options Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT5 - System Options Register 5 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT5 register
+ */
+/*@{*/
+#define SIM_RD_SOPT5(base)       (SIM_SOPT5_REG(base))
+#define SIM_WR_SOPT5(base, value) (SIM_SOPT5_REG(base) = (value))
+#define SIM_RMW_SOPT5(base, mask, value) (SIM_WR_SOPT5(base, (SIM_RD_SOPT5(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) |  (value)))
+#define SIM_CLR_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) & ~(value)))
+#define SIM_TOG_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
+ *
+ * Selects the source for the UART 0 transmit data.
+ *
+ * Values:
+ * - 0b00 - UART0_TX pin
+ * - 0b01 - UART0_TX pin modulated with FTM1 channel 0 output
+ * - 0b10 - UART0_TX pin modulated with FTM2 channel 0 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */
+#define SIM_RD_SOPT5_UART0TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART0TXSRC_MASK) >> SIM_SOPT5_UART0TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART0TXSRC(base) (SIM_RD_SOPT5_UART0TXSRC(base))
+
+/*! @brief Set the UART0TXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART0TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART0TXSRC_MASK, SIM_SOPT5_UART0TXSRC(value)))
+#define SIM_BWR_SOPT5_UART0TXSRC(base, value) (SIM_WR_SOPT5_UART0TXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
+ *
+ * Selects the source for the UART 0 receive data.
+ *
+ * Values:
+ * - 0b00 - UART0_RX pin
+ * - 0b01 - CMP0
+ * - 0b10 - CMP1
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */
+#define SIM_RD_SOPT5_UART0RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART0RXSRC_MASK) >> SIM_SOPT5_UART0RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART0RXSRC(base) (SIM_RD_SOPT5_UART0RXSRC(base))
+
+/*! @brief Set the UART0RXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART0RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART0RXSRC_MASK, SIM_SOPT5_UART0RXSRC(value)))
+#define SIM_BWR_SOPT5_UART0RXSRC(base, value) (SIM_WR_SOPT5_UART0RXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
+ *
+ * Selects the source for the UART 1 transmit data.
+ *
+ * Values:
+ * - 0b00 - UART1_TX pin
+ * - 0b01 - UART1_TX pin modulated with FTM1 channel 0 output
+ * - 0b10 - UART1_TX pin modulated with FTM2 channel 0 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */
+#define SIM_RD_SOPT5_UART1TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART1TXSRC_MASK) >> SIM_SOPT5_UART1TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART1TXSRC(base) (SIM_RD_SOPT5_UART1TXSRC(base))
+
+/*! @brief Set the UART1TXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART1TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART1TXSRC_MASK, SIM_SOPT5_UART1TXSRC(value)))
+#define SIM_BWR_SOPT5_UART1TXSRC(base, value) (SIM_WR_SOPT5_UART1TXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
+ *
+ * Selects the source for the UART 1 receive data.
+ *
+ * Values:
+ * - 0b00 - UART1_RX pin
+ * - 0b01 - CMP0
+ * - 0b10 - CMP1
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */
+#define SIM_RD_SOPT5_UART1RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART1RXSRC_MASK) >> SIM_SOPT5_UART1RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART1RXSRC(base) (SIM_RD_SOPT5_UART1RXSRC(base))
+
+/*! @brief Set the UART1RXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART1RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART1RXSRC_MASK, SIM_SOPT5_UART1RXSRC(value)))
+#define SIM_BWR_SOPT5_UART1RXSRC(base, value) (SIM_WR_SOPT5_UART1RXSRC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT7 - System Options Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT7 - System Options Register 7 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT7 register
+ */
+/*@{*/
+#define SIM_RD_SOPT7(base)       (SIM_SOPT7_REG(base))
+#define SIM_WR_SOPT7(base, value) (SIM_SOPT7_REG(base) = (value))
+#define SIM_RMW_SOPT7(base, mask, value) (SIM_WR_SOPT7(base, (SIM_RD_SOPT7(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) |  (value)))
+#define SIM_CLR_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) & ~(value)))
+#define SIM_TOG_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
+ *
+ * Selects the ADC0 trigger source when alternative triggers are functional in
+ * stop and VLPS modes. .
+ *
+ * Values:
+ * - 0b0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0b0001 - High speed comparator 0 output
+ * - 0b0010 - High speed comparator 1 output
+ * - 0b0011 - High speed comparator 2 output
+ * - 0b0100 - PIT trigger 0
+ * - 0b0101 - PIT trigger 1
+ * - 0b0110 - PIT trigger 2
+ * - 0b0111 - PIT trigger 3
+ * - 0b1000 - FTM0 trigger
+ * - 0b1001 - FTM1 trigger
+ * - 0b1010 - FTM2 trigger
+ * - 0b1011 - FTM3 trigger
+ * - 0b1100 - RTC alarm
+ * - 0b1101 - RTC seconds
+ * - 0b1110 - Low-power timer (LPTMR) trigger
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */
+#define SIM_RD_SOPT7_ADC0TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0TRGSEL_MASK) >> SIM_SOPT7_ADC0TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0TRGSEL(base) (SIM_RD_SOPT7_ADC0TRGSEL(base))
+
+/*! @brief Set the ADC0TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0TRGSEL_MASK, SIM_SOPT7_ADC0TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0TRGSEL(base, value) (SIM_WR_SOPT7_ADC0TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
+ *
+ * Selects the ADC0 pre-trigger source when alternative triggers are enabled
+ * through ADC0ALTTRGEN.
+ *
+ * Values:
+ * - 0b0 - Pre-trigger A
+ * - 0b1 - Pre-trigger B
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC0PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0PRETRGSEL_MASK) >> SIM_SOPT7_ADC0PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0PRETRGSEL(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT))
+
+/*! @brief Set the ADC0PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0PRETRGSEL_MASK, SIM_SOPT7_ADC0PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0PRETRGSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
+ *
+ * Enable alternative conversion triggers for ADC0.
+ *
+ * Values:
+ * - 0b0 - PDB trigger selected for ADC0.
+ * - 0b1 - Alternate trigger selected for ADC0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC0ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0ALTTRGEN_MASK) >> SIM_SOPT7_ADC0ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC0ALTTRGEN(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT))
+
+/*! @brief Set the ADC0ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC0ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0ALTTRGEN_MASK, SIM_SOPT7_ADC0ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC0ALTTRGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
+ *
+ * Selects the ADC1 trigger source when alternative triggers are functional in
+ * stop and VLPS modes.
+ *
+ * Values:
+ * - 0b0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0b0001 - High speed comparator 0 output
+ * - 0b0010 - High speed comparator 1 output
+ * - 0b0011 - High speed comparator 2 output
+ * - 0b0100 - PIT trigger 0
+ * - 0b0101 - PIT trigger 1
+ * - 0b0110 - PIT trigger 2
+ * - 0b0111 - PIT trigger 3
+ * - 0b1000 - FTM0 trigger
+ * - 0b1001 - FTM1 trigger
+ * - 0b1010 - FTM2 trigger
+ * - 0b1011 - FTM3 trigger
+ * - 0b1100 - RTC alarm
+ * - 0b1101 - RTC seconds
+ * - 0b1110 - Low-power timer (LPTMR) trigger
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */
+#define SIM_RD_SOPT7_ADC1TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1TRGSEL_MASK) >> SIM_SOPT7_ADC1TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC1TRGSEL(base) (SIM_RD_SOPT7_ADC1TRGSEL(base))
+
+/*! @brief Set the ADC1TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC1TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1TRGSEL_MASK, SIM_SOPT7_ADC1TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC1TRGSEL(base, value) (SIM_WR_SOPT7_ADC1TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
+ *
+ * Selects the ADC1 pre-trigger source when alternative triggers are enabled
+ * through ADC1ALTTRGEN.
+ *
+ * Values:
+ * - 0b0 - Pre-trigger A selected for ADC1.
+ * - 0b1 - Pre-trigger B selected for ADC1.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC1PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1PRETRGSEL_MASK) >> SIM_SOPT7_ADC1PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC1PRETRGSEL(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1PRETRGSEL_SHIFT))
+
+/*! @brief Set the ADC1PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC1PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1PRETRGSEL_MASK, SIM_SOPT7_ADC1PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC1PRETRGSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1PRETRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
+ *
+ * Enable alternative conversion triggers for ADC1.
+ *
+ * Values:
+ * - 0b0 - PDB trigger selected for ADC1
+ * - 0b1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC1ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1ALTTRGEN_MASK) >> SIM_SOPT7_ADC1ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC1ALTTRGEN(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1ALTTRGEN_SHIFT))
+
+/*! @brief Set the ADC1ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC1ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1ALTTRGEN_MASK, SIM_SOPT7_ADC1ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC1ALTTRGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1ALTTRGEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SDID - System Device Identification Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SDID - System Device Identification Register (RO)
+ *
+ * Reset value: 0x00000380U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SDID register
+ */
+/*@{*/
+#define SIM_RD_SDID(base)        (SIM_SDID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SDID bitfields
+ */
+
+/*!
+ * @name Register SIM_SDID, field PINID[3:0] (RO)
+ *
+ * Specifies the pincount of the device.
+ *
+ * Values:
+ * - 0b0000 - Reserved
+ * - 0b0001 - Reserved
+ * - 0b0010 - 32-pin
+ * - 0b0011 - Reserved
+ * - 0b0100 - 48-pin
+ * - 0b0101 - 64-pin
+ * - 0b0110 - 80-pin
+ * - 0b0111 - 81-pin or 121-pin
+ * - 0b1000 - 100-pin
+ * - 0b1001 - 121-pin
+ * - 0b1010 - 144-pin
+ * - 0b1011 - Custom pinout (WLCSP)
+ * - 0b1100 - 169-pin
+ * - 0b1101 - Reserved
+ * - 0b1110 - 256-pin
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_PINID field. */
+#define SIM_RD_SDID_PINID(base) ((SIM_SDID_REG(base) & SIM_SDID_PINID_MASK) >> SIM_SDID_PINID_SHIFT)
+#define SIM_BRD_SDID_PINID(base) (SIM_RD_SDID_PINID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMID[6:4] (RO)
+ *
+ * This field is maintained for compatibility only, but has been superceded by
+ * the SERIESID, FAMILYID and SUBFAMID fields in this register.
+ *
+ * Values:
+ * - 0b000 - K1x Family (without tamper)
+ * - 0b001 - K2x Family (without tamper)
+ * - 0b010 - K3x Family or K1x/K6x Family (with tamper)
+ * - 0b011 - K4x Family or K2x Family (with tamper)
+ * - 0b100 - K6x Family (without tamper)
+ * - 0b101 - K7x Family
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMID field. */
+#define SIM_RD_SDID_FAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMID_MASK) >> SIM_SDID_FAMID_SHIFT)
+#define SIM_BRD_SDID_FAMID(base) (SIM_RD_SDID_FAMID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field DIEID[11:7] (RO)
+ *
+ * Specifies the silicon feature set identication number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_DIEID field. */
+#define SIM_RD_SDID_DIEID(base) ((SIM_SDID_REG(base) & SIM_SDID_DIEID_MASK) >> SIM_SDID_DIEID_SHIFT)
+#define SIM_BRD_SDID_DIEID(base) (SIM_RD_SDID_DIEID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field REVID[15:12] (RO)
+ *
+ * Specifies the silicon implementation number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_REVID field. */
+#define SIM_RD_SDID_REVID(base) ((SIM_SDID_REG(base) & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT)
+#define SIM_BRD_SDID_REVID(base) (SIM_RD_SDID_REVID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SERIESID[23:20] (RO)
+ *
+ * Specifies the Kinetis series of the device.
+ *
+ * Values:
+ * - 0b0000 - Kinetis K series
+ * - 0b0001 - Kinetis L series
+ * - 0b0101 - Kinetis W series
+ * - 0b0110 - Kinetis V series
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SERIESID field. */
+#define SIM_RD_SDID_SERIESID(base) ((SIM_SDID_REG(base) & SIM_SDID_SERIESID_MASK) >> SIM_SDID_SERIESID_SHIFT)
+#define SIM_BRD_SDID_SERIESID(base) (SIM_RD_SDID_SERIESID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
+ *
+ * Specifies the Kinetis sub-family of the device.
+ *
+ * Values:
+ * - 0b0000 - Kx0 Subfamily
+ * - 0b0001 - Kx1 Subfamily (tamper detect)
+ * - 0b0010 - Kx2 Subfamily
+ * - 0b0011 - Kx3 Subfamily (tamper detect)
+ * - 0b0100 - Kx4 Subfamily
+ * - 0b0101 - Kx5 Subfamily (tamper detect)
+ * - 0b0110 - Kx6 Subfamily
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SUBFAMID field. */
+#define SIM_RD_SDID_SUBFAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_SUBFAMID_MASK) >> SIM_SDID_SUBFAMID_SHIFT)
+#define SIM_BRD_SDID_SUBFAMID(base) (SIM_RD_SDID_SUBFAMID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
+ *
+ * Specifies the Kinetis family of the device.
+ *
+ * Values:
+ * - 0b0001 - K1x Family
+ * - 0b0010 - K2x Family
+ * - 0b0011 - K3x Family
+ * - 0b0100 - K4x Family
+ * - 0b0110 - K6x Family
+ * - 0b0111 - K7x Family
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMILYID field. */
+#define SIM_RD_SDID_FAMILYID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMILYID_MASK) >> SIM_SDID_FAMILYID_SHIFT)
+#define SIM_BRD_SDID_FAMILYID(base) (SIM_RD_SDID_FAMILYID(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC1 - System Clock Gating Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC1 register
+ */
+/*@{*/
+#define SIM_RD_SCGC1(base)       (SIM_SCGC1_REG(base))
+#define SIM_WR_SCGC1(base, value) (SIM_SCGC1_REG(base) = (value))
+#define SIM_RMW_SCGC1(base, mask, value) (SIM_WR_SCGC1(base, (SIM_RD_SCGC1(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) |  (value)))
+#define SIM_CLR_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) & ~(value)))
+#define SIM_TOG_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) ^  (value)))
+/*@}*/
+
+/* Unified clock gate bit access macros */
+#define SIM_SCGC_BIT_REG(base, index)        (*((volatile uint32_t *)&SIM_SCGC1_REG(base) + (((uint32_t)(index) >> 5) - 0U)))
+#define SIM_SCGC_BIT_SHIFT(index)            ((uint32_t)(index) & ((1U << 5) - 1U))
+#define SIM_RD_SCGC_BIT(base, index)         (SIM_SCGC_BIT_REG((base), (index)) & (1U << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BRD_SCGC_BIT(base, index)        (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_WR_SCGC_BIT(base, index, value)  (SIM_SCGC_BIT_REG((base), (index)) = (SIM_SCGC_BIT_REG((base), (index)) & ~(1U << SIM_SCGC_BIT_SHIFT(index))) | ((uint32_t)(value) << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BWR_SCGC_BIT(base, index, value) (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)) = (uint32_t)(value))
+
+/*
+ * Constants & macros for individual SIM_SCGC1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC1, field I2C2[6] (RW)
+ *
+ * This bit controls the clock gate to the I2C2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_I2C2 field. */
+#define SIM_RD_SCGC1_I2C2(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_I2C2_MASK) >> SIM_SCGC1_I2C2_SHIFT)
+#define SIM_BRD_SCGC1_I2C2(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_I2C2_SHIFT))
+
+/*! @brief Set the I2C2 field to a new value. */
+#define SIM_WR_SCGC1_I2C2(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_I2C2_MASK, SIM_SCGC1_I2C2(value)))
+#define SIM_BWR_SCGC1_I2C2(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_I2C2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC1, field UART4[10] (RW)
+ *
+ * This bit controls the clock gate to the UART4 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_UART4 field. */
+#define SIM_RD_SCGC1_UART4(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_UART4_MASK) >> SIM_SCGC1_UART4_SHIFT)
+#define SIM_BRD_SCGC1_UART4(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART4_SHIFT))
+
+/*! @brief Set the UART4 field to a new value. */
+#define SIM_WR_SCGC1_UART4(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_UART4_MASK, SIM_SCGC1_UART4(value)))
+#define SIM_BWR_SCGC1_UART4(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC1, field UART5[11] (RW)
+ *
+ * This bit controls the clock gate to the UART5 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_UART5 field. */
+#define SIM_RD_SCGC1_UART5(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_UART5_MASK) >> SIM_SCGC1_UART5_SHIFT)
+#define SIM_BRD_SCGC1_UART5(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART5_SHIFT))
+
+/*! @brief Set the UART5 field to a new value. */
+#define SIM_WR_SCGC1_UART5(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_UART5_MASK, SIM_SCGC1_UART5(value)))
+#define SIM_BWR_SCGC1_UART5(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART5_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC2 - System Clock Gating Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
+ * AIPS1, define the clock gate control bits in the SCGC2. When accessing through
+ * AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC2 register
+ */
+/*@{*/
+#define SIM_RD_SCGC2(base)       (SIM_SCGC2_REG(base))
+#define SIM_WR_SCGC2(base, value) (SIM_SCGC2_REG(base) = (value))
+#define SIM_RMW_SCGC2(base, mask, value) (SIM_WR_SCGC2(base, (SIM_RD_SCGC2(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) |  (value)))
+#define SIM_CLR_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) & ~(value)))
+#define SIM_TOG_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC2, field ENET[0] (RW)
+ *
+ * This bit controls the clock gate to the ENET module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_ENET field. */
+#define SIM_RD_SCGC2_ENET(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_ENET_MASK) >> SIM_SCGC2_ENET_SHIFT)
+#define SIM_BRD_SCGC2_ENET(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_ENET_SHIFT))
+
+/*! @brief Set the ENET field to a new value. */
+#define SIM_WR_SCGC2_ENET(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_ENET_MASK, SIM_SCGC2_ENET(value)))
+#define SIM_BWR_SCGC2_ENET(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_ENET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC2, field DAC0[12] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_DAC0 field. */
+#define SIM_RD_SCGC2_DAC0(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_DAC0_MASK) >> SIM_SCGC2_DAC0_SHIFT)
+#define SIM_BRD_SCGC2_DAC0(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC0_SHIFT))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC2_DAC0(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_DAC0_MASK, SIM_SCGC2_DAC0(value)))
+#define SIM_BWR_SCGC2_DAC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC2, field DAC1[13] (RW)
+ *
+ * This bit controls the clock gate to the DAC1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_DAC1 field. */
+#define SIM_RD_SCGC2_DAC1(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_DAC1_MASK) >> SIM_SCGC2_DAC1_SHIFT)
+#define SIM_BRD_SCGC2_DAC1(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC1_SHIFT))
+
+/*! @brief Set the DAC1 field to a new value. */
+#define SIM_WR_SCGC2_DAC1(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_DAC1_MASK, SIM_SCGC2_DAC1(value)))
+#define SIM_BWR_SCGC2_DAC1(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC3 - System Clock Gating Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
+ * through AIPS1, define the clock gate control bits in the SCGC3. When accessing
+ * through AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC3 register
+ */
+/*@{*/
+#define SIM_RD_SCGC3(base)       (SIM_SCGC3_REG(base))
+#define SIM_WR_SCGC3(base, value) (SIM_SCGC3_REG(base) = (value))
+#define SIM_RMW_SCGC3(base, mask, value) (SIM_WR_SCGC3(base, (SIM_RD_SCGC3(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) |  (value)))
+#define SIM_CLR_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) & ~(value)))
+#define SIM_TOG_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC3 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC3, field RNGA[0] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_RNGA field. */
+#define SIM_RD_SCGC3_RNGA(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_RNGA_MASK) >> SIM_SCGC3_RNGA_SHIFT)
+#define SIM_BRD_SCGC3_RNGA(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_RNGA_SHIFT))
+
+/*! @brief Set the RNGA field to a new value. */
+#define SIM_WR_SCGC3_RNGA(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_RNGA_MASK, SIM_SCGC3_RNGA(value)))
+#define SIM_BWR_SCGC3_RNGA(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_RNGA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field SPI2[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_SPI2 field. */
+#define SIM_RD_SCGC3_SPI2(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_SPI2_MASK) >> SIM_SCGC3_SPI2_SHIFT)
+#define SIM_BRD_SCGC3_SPI2(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SPI2_SHIFT))
+
+/*! @brief Set the SPI2 field to a new value. */
+#define SIM_WR_SCGC3_SPI2(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_SPI2_MASK, SIM_SCGC3_SPI2(value)))
+#define SIM_BWR_SCGC3_SPI2(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SPI2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field SDHC[17] (RW)
+ *
+ * This bit controls the clock gate to the SDHC module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_SDHC field. */
+#define SIM_RD_SCGC3_SDHC(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_SDHC_MASK) >> SIM_SCGC3_SDHC_SHIFT)
+#define SIM_BRD_SCGC3_SDHC(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SDHC_SHIFT))
+
+/*! @brief Set the SDHC field to a new value. */
+#define SIM_WR_SCGC3_SDHC(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_SDHC_MASK, SIM_SCGC3_SDHC(value)))
+#define SIM_BWR_SCGC3_SDHC(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SDHC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field FTM2[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_FTM2 field. */
+#define SIM_RD_SCGC3_FTM2(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_FTM2_MASK) >> SIM_SCGC3_FTM2_SHIFT)
+#define SIM_BRD_SCGC3_FTM2(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM2_SHIFT))
+
+/*! @brief Set the FTM2 field to a new value. */
+#define SIM_WR_SCGC3_FTM2(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_FTM2_MASK, SIM_SCGC3_FTM2(value)))
+#define SIM_BWR_SCGC3_FTM2(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field FTM3[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM3 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_FTM3 field. */
+#define SIM_RD_SCGC3_FTM3(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_FTM3_MASK) >> SIM_SCGC3_FTM3_SHIFT)
+#define SIM_BRD_SCGC3_FTM3(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM3_SHIFT))
+
+/*! @brief Set the FTM3 field to a new value. */
+#define SIM_WR_SCGC3_FTM3(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_FTM3_MASK, SIM_SCGC3_FTM3(value)))
+#define SIM_BWR_SCGC3_FTM3(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field ADC1[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_ADC1 field. */
+#define SIM_RD_SCGC3_ADC1(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_ADC1_MASK) >> SIM_SCGC3_ADC1_SHIFT)
+#define SIM_BRD_SCGC3_ADC1(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_ADC1_SHIFT))
+
+/*! @brief Set the ADC1 field to a new value. */
+#define SIM_WR_SCGC3_ADC1(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_ADC1_MASK, SIM_SCGC3_ADC1(value)))
+#define SIM_BWR_SCGC3_ADC1(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_ADC1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC4 - System Clock Gating Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
+ *
+ * Reset value: 0xF0100030U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC4 register
+ */
+/*@{*/
+#define SIM_RD_SCGC4(base)       (SIM_SCGC4_REG(base))
+#define SIM_WR_SCGC4(base, value) (SIM_SCGC4_REG(base) = (value))
+#define SIM_RMW_SCGC4(base, mask, value) (SIM_WR_SCGC4(base, (SIM_RD_SCGC4(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) |  (value)))
+#define SIM_CLR_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) & ~(value)))
+#define SIM_TOG_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC4, field EWM[1] (RW)
+ *
+ * This bit controls the clock gate to the EWM module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_EWM field. */
+#define SIM_RD_SCGC4_EWM(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_EWM_MASK) >> SIM_SCGC4_EWM_SHIFT)
+#define SIM_BRD_SCGC4_EWM(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_EWM_SHIFT))
+
+/*! @brief Set the EWM field to a new value. */
+#define SIM_WR_SCGC4_EWM(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_EWM_MASK, SIM_SCGC4_EWM(value)))
+#define SIM_BWR_SCGC4_EWM(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_EWM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMT[2] (RW)
+ *
+ * This bit controls the clock gate to the CMT module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMT field. */
+#define SIM_RD_SCGC4_CMT(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMT_MASK) >> SIM_SCGC4_CMT_SHIFT)
+#define SIM_BRD_SCGC4_CMT(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT))
+
+/*! @brief Set the CMT field to a new value. */
+#define SIM_WR_SCGC4_CMT(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMT_MASK, SIM_SCGC4_CMT(value)))
+#define SIM_BWR_SCGC4_CMT(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C0[6] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C0 field. */
+#define SIM_RD_SCGC4_I2C0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C0_MASK) >> SIM_SCGC4_I2C0_SHIFT)
+#define SIM_BRD_SCGC4_I2C0(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT))
+
+/*! @brief Set the I2C0 field to a new value. */
+#define SIM_WR_SCGC4_I2C0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C0_MASK, SIM_SCGC4_I2C0(value)))
+#define SIM_BWR_SCGC4_I2C0(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C1[7] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C1 field. */
+#define SIM_RD_SCGC4_I2C1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C1_MASK) >> SIM_SCGC4_I2C1_SHIFT)
+#define SIM_BRD_SCGC4_I2C1(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT))
+
+/*! @brief Set the I2C1 field to a new value. */
+#define SIM_WR_SCGC4_I2C1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C1_MASK, SIM_SCGC4_I2C1(value)))
+#define SIM_BWR_SCGC4_I2C1(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART0[10] (RW)
+ *
+ * This bit controls the clock gate to the UART0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART0 field. */
+#define SIM_RD_SCGC4_UART0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT)
+#define SIM_BRD_SCGC4_UART0(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART0_SHIFT))
+
+/*! @brief Set the UART0 field to a new value. */
+#define SIM_WR_SCGC4_UART0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART0_MASK, SIM_SCGC4_UART0(value)))
+#define SIM_BWR_SCGC4_UART0(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART1[11] (RW)
+ *
+ * This bit controls the clock gate to the UART1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART1 field. */
+#define SIM_RD_SCGC4_UART1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT)
+#define SIM_BRD_SCGC4_UART1(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART1_SHIFT))
+
+/*! @brief Set the UART1 field to a new value. */
+#define SIM_WR_SCGC4_UART1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART1_MASK, SIM_SCGC4_UART1(value)))
+#define SIM_BWR_SCGC4_UART1(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART2[12] (RW)
+ *
+ * This bit controls the clock gate to the UART2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART2 field. */
+#define SIM_RD_SCGC4_UART2(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT)
+#define SIM_BRD_SCGC4_UART2(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT))
+
+/*! @brief Set the UART2 field to a new value. */
+#define SIM_WR_SCGC4_UART2(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART2_MASK, SIM_SCGC4_UART2(value)))
+#define SIM_BWR_SCGC4_UART2(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART3[13] (RW)
+ *
+ * This bit controls the clock gate to the UART3 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART3 field. */
+#define SIM_RD_SCGC4_UART3(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART3_MASK) >> SIM_SCGC4_UART3_SHIFT)
+#define SIM_BRD_SCGC4_UART3(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART3_SHIFT))
+
+/*! @brief Set the UART3 field to a new value. */
+#define SIM_WR_SCGC4_UART3(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART3_MASK, SIM_SCGC4_UART3(value)))
+#define SIM_BWR_SCGC4_UART3(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field USBOTG[18] (RW)
+ *
+ * This bit controls the clock gate to the USB module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_USBOTG field. */
+#define SIM_RD_SCGC4_USBOTG(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_USBOTG_MASK) >> SIM_SCGC4_USBOTG_SHIFT)
+#define SIM_BRD_SCGC4_USBOTG(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBOTG_SHIFT))
+
+/*! @brief Set the USBOTG field to a new value. */
+#define SIM_WR_SCGC4_USBOTG(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_USBOTG_MASK, SIM_SCGC4_USBOTG(value)))
+#define SIM_BWR_SCGC4_USBOTG(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBOTG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMP[19] (RW)
+ *
+ * This bit controls the clock gate to the comparator module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMP field. */
+#define SIM_RD_SCGC4_CMP(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMP_MASK) >> SIM_SCGC4_CMP_SHIFT)
+#define SIM_BRD_SCGC4_CMP(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT))
+
+/*! @brief Set the CMP field to a new value. */
+#define SIM_WR_SCGC4_CMP(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMP_MASK, SIM_SCGC4_CMP(value)))
+#define SIM_BWR_SCGC4_CMP(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field VREF[20] (RW)
+ *
+ * This bit controls the clock gate to the VREF module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_VREF field. */
+#define SIM_RD_SCGC4_VREF(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_VREF_MASK) >> SIM_SCGC4_VREF_SHIFT)
+#define SIM_BRD_SCGC4_VREF(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT))
+
+/*! @brief Set the VREF field to a new value. */
+#define SIM_WR_SCGC4_VREF(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_VREF_MASK, SIM_SCGC4_VREF(value)))
+#define SIM_BWR_SCGC4_VREF(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC5 - System Clock Gating Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
+ *
+ * Reset value: 0x00040182U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC5 register
+ */
+/*@{*/
+#define SIM_RD_SCGC5(base)       (SIM_SCGC5_REG(base))
+#define SIM_WR_SCGC5(base, value) (SIM_SCGC5_REG(base) = (value))
+#define SIM_RMW_SCGC5(base, mask, value) (SIM_WR_SCGC5(base, (SIM_RD_SCGC5(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) |  (value)))
+#define SIM_CLR_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) & ~(value)))
+#define SIM_TOG_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC5, field LPTMR[0] (RW)
+ *
+ * This bit controls software access to the Low Power Timer module.
+ *
+ * Values:
+ * - 0b0 - Access disabled
+ * - 0b1 - Access enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_LPTMR field. */
+#define SIM_RD_SCGC5_LPTMR(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPTMR_MASK) >> SIM_SCGC5_LPTMR_SHIFT)
+#define SIM_BRD_SCGC5_LPTMR(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT))
+
+/*! @brief Set the LPTMR field to a new value. */
+#define SIM_WR_SCGC5_LPTMR(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPTMR_MASK, SIM_SCGC5_LPTMR(value)))
+#define SIM_BWR_SCGC5_LPTMR(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTA[9] (RW)
+ *
+ * This bit controls the clock gate to the Port A module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTA field. */
+#define SIM_RD_SCGC5_PORTA(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTA_MASK) >> SIM_SCGC5_PORTA_SHIFT)
+#define SIM_BRD_SCGC5_PORTA(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT))
+
+/*! @brief Set the PORTA field to a new value. */
+#define SIM_WR_SCGC5_PORTA(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTA_MASK, SIM_SCGC5_PORTA(value)))
+#define SIM_BWR_SCGC5_PORTA(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTB[10] (RW)
+ *
+ * This bit controls the clock gate to the Port B module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTB field. */
+#define SIM_RD_SCGC5_PORTB(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTB_MASK) >> SIM_SCGC5_PORTB_SHIFT)
+#define SIM_BRD_SCGC5_PORTB(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT))
+
+/*! @brief Set the PORTB field to a new value. */
+#define SIM_WR_SCGC5_PORTB(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTB_MASK, SIM_SCGC5_PORTB(value)))
+#define SIM_BWR_SCGC5_PORTB(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTC[11] (RW)
+ *
+ * This bit controls the clock gate to the Port C module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTC field. */
+#define SIM_RD_SCGC5_PORTC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTC_MASK) >> SIM_SCGC5_PORTC_SHIFT)
+#define SIM_BRD_SCGC5_PORTC(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT))
+
+/*! @brief Set the PORTC field to a new value. */
+#define SIM_WR_SCGC5_PORTC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTC_MASK, SIM_SCGC5_PORTC(value)))
+#define SIM_BWR_SCGC5_PORTC(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTD[12] (RW)
+ *
+ * This bit controls the clock gate to the Port D module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTD field. */
+#define SIM_RD_SCGC5_PORTD(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTD_MASK) >> SIM_SCGC5_PORTD_SHIFT)
+#define SIM_BRD_SCGC5_PORTD(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT))
+
+/*! @brief Set the PORTD field to a new value. */
+#define SIM_WR_SCGC5_PORTD(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTD_MASK, SIM_SCGC5_PORTD(value)))
+#define SIM_BWR_SCGC5_PORTD(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTE[13] (RW)
+ *
+ * This bit controls the clock gate to the Port E module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTE field. */
+#define SIM_RD_SCGC5_PORTE(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTE_MASK) >> SIM_SCGC5_PORTE_SHIFT)
+#define SIM_BRD_SCGC5_PORTE(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT))
+
+/*! @brief Set the PORTE field to a new value. */
+#define SIM_WR_SCGC5_PORTE(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTE_MASK, SIM_SCGC5_PORTE(value)))
+#define SIM_BWR_SCGC5_PORTE(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC6 - System Clock Gating Control Register 6
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
+ *
+ * Reset value: 0x40000001U
+ *
+ * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
+ * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
+ * When accessing through AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC6 register
+ */
+/*@{*/
+#define SIM_RD_SCGC6(base)       (SIM_SCGC6_REG(base))
+#define SIM_WR_SCGC6(base, value) (SIM_SCGC6_REG(base) = (value))
+#define SIM_RMW_SCGC6(base, mask, value) (SIM_WR_SCGC6(base, (SIM_RD_SCGC6(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) |  (value)))
+#define SIM_CLR_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) & ~(value)))
+#define SIM_TOG_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC6 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC6, field FTF[0] (RW)
+ *
+ * This bit controls the clock gate to the flash memory. Flash reads are still
+ * supported while the flash memory is clock gated, but entry into low power modes
+ * is blocked.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTF field. */
+#define SIM_RD_SCGC6_FTF(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTF_MASK) >> SIM_SCGC6_FTF_SHIFT)
+#define SIM_BRD_SCGC6_FTF(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT))
+
+/*! @brief Set the FTF field to a new value. */
+#define SIM_WR_SCGC6_FTF(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTF_MASK, SIM_SCGC6_FTF(value)))
+#define SIM_BWR_SCGC6_FTF(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA Mux module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */
+#define SIM_RD_SCGC6_DMAMUX(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DMAMUX_MASK) >> SIM_SCGC6_DMAMUX_SHIFT)
+#define SIM_BRD_SCGC6_DMAMUX(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT))
+
+/*! @brief Set the DMAMUX field to a new value. */
+#define SIM_WR_SCGC6_DMAMUX(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DMAMUX_MASK, SIM_SCGC6_DMAMUX(value)))
+#define SIM_BWR_SCGC6_DMAMUX(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
+ *
+ * This bit controls the clock gate to the FlexCAN0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. */
+#define SIM_RD_SCGC6_FLEXCAN0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FLEXCAN0_MASK) >> SIM_SCGC6_FLEXCAN0_SHIFT)
+#define SIM_BRD_SCGC6_FLEXCAN0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FLEXCAN0_SHIFT))
+
+/*! @brief Set the FLEXCAN0 field to a new value. */
+#define SIM_WR_SCGC6_FLEXCAN0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FLEXCAN0_MASK, SIM_SCGC6_FLEXCAN0(value)))
+#define SIM_BWR_SCGC6_FLEXCAN0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FLEXCAN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RNGA[9] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RNGA field. */
+#define SIM_RD_SCGC6_RNGA(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RNGA_MASK) >> SIM_SCGC6_RNGA_SHIFT)
+#define SIM_BRD_SCGC6_RNGA(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RNGA_SHIFT))
+
+/*! @brief Set the RNGA field to a new value. */
+#define SIM_WR_SCGC6_RNGA(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RNGA_MASK, SIM_SCGC6_RNGA(value)))
+#define SIM_BWR_SCGC6_RNGA(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RNGA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field SPI0[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_SPI0 field. */
+#define SIM_RD_SCGC6_SPI0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI0_MASK) >> SIM_SCGC6_SPI0_SHIFT)
+#define SIM_BRD_SCGC6_SPI0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT))
+
+/*! @brief Set the SPI0 field to a new value. */
+#define SIM_WR_SCGC6_SPI0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI0_MASK, SIM_SCGC6_SPI0(value)))
+#define SIM_BWR_SCGC6_SPI0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field SPI1[13] (RW)
+ *
+ * This bit controls the clock gate to the SPI1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_SPI1 field. */
+#define SIM_RD_SCGC6_SPI1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI1_MASK) >> SIM_SCGC6_SPI1_SHIFT)
+#define SIM_BRD_SCGC6_SPI1(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT))
+
+/*! @brief Set the SPI1 field to a new value. */
+#define SIM_WR_SCGC6_SPI1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI1_MASK, SIM_SCGC6_SPI1(value)))
+#define SIM_BWR_SCGC6_SPI1(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field I2S[15] (RW)
+ *
+ * This bit controls the clock gate to the I 2 S module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_I2S field. */
+#define SIM_RD_SCGC6_I2S(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_I2S_MASK) >> SIM_SCGC6_I2S_SHIFT)
+#define SIM_BRD_SCGC6_I2S(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT))
+
+/*! @brief Set the I2S field to a new value. */
+#define SIM_WR_SCGC6_I2S(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_I2S_MASK, SIM_SCGC6_I2S(value)))
+#define SIM_BWR_SCGC6_I2S(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field CRC[18] (RW)
+ *
+ * This bit controls the clock gate to the CRC module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_CRC field. */
+#define SIM_RD_SCGC6_CRC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_CRC_MASK) >> SIM_SCGC6_CRC_SHIFT)
+#define SIM_BRD_SCGC6_CRC(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_CRC_SHIFT))
+
+/*! @brief Set the CRC field to a new value. */
+#define SIM_WR_SCGC6_CRC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_CRC_MASK, SIM_SCGC6_CRC(value)))
+#define SIM_BWR_SCGC6_CRC(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_CRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field USBDCD[21] (RW)
+ *
+ * This bit controls the clock gate to the USB DCD module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_USBDCD field. */
+#define SIM_RD_SCGC6_USBDCD(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_USBDCD_MASK) >> SIM_SCGC6_USBDCD_SHIFT)
+#define SIM_BRD_SCGC6_USBDCD(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_USBDCD_SHIFT))
+
+/*! @brief Set the USBDCD field to a new value. */
+#define SIM_WR_SCGC6_USBDCD(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_USBDCD_MASK, SIM_SCGC6_USBDCD(value)))
+#define SIM_BWR_SCGC6_USBDCD(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_USBDCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PDB[22] (RW)
+ *
+ * This bit controls the clock gate to the PDB module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PDB field. */
+#define SIM_RD_SCGC6_PDB(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PDB_MASK) >> SIM_SCGC6_PDB_SHIFT)
+#define SIM_BRD_SCGC6_PDB(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PDB_SHIFT))
+
+/*! @brief Set the PDB field to a new value. */
+#define SIM_WR_SCGC6_PDB(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PDB_MASK, SIM_SCGC6_PDB(value)))
+#define SIM_BWR_SCGC6_PDB(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PDB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PIT[23] (RW)
+ *
+ * This bit controls the clock gate to the PIT module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PIT field. */
+#define SIM_RD_SCGC6_PIT(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PIT_MASK) >> SIM_SCGC6_PIT_SHIFT)
+#define SIM_BRD_SCGC6_PIT(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT))
+
+/*! @brief Set the PIT field to a new value. */
+#define SIM_WR_SCGC6_PIT(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PIT_MASK, SIM_SCGC6_PIT(value)))
+#define SIM_BWR_SCGC6_PIT(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM0[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM0 field. */
+#define SIM_RD_SCGC6_FTM0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM0_MASK) >> SIM_SCGC6_FTM0_SHIFT)
+#define SIM_BRD_SCGC6_FTM0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM0_SHIFT))
+
+/*! @brief Set the FTM0 field to a new value. */
+#define SIM_WR_SCGC6_FTM0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM0_MASK, SIM_SCGC6_FTM0(value)))
+#define SIM_BWR_SCGC6_FTM0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM1[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM1 field. */
+#define SIM_RD_SCGC6_FTM1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM1_MASK) >> SIM_SCGC6_FTM1_SHIFT)
+#define SIM_BRD_SCGC6_FTM1(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM1_SHIFT))
+
+/*! @brief Set the FTM1 field to a new value. */
+#define SIM_WR_SCGC6_FTM1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM1_MASK, SIM_SCGC6_FTM1(value)))
+#define SIM_BWR_SCGC6_FTM1(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM2[26] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM2 field. */
+#define SIM_RD_SCGC6_FTM2(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM2_MASK) >> SIM_SCGC6_FTM2_SHIFT)
+#define SIM_BRD_SCGC6_FTM2(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM2_SHIFT))
+
+/*! @brief Set the FTM2 field to a new value. */
+#define SIM_WR_SCGC6_FTM2(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM2_MASK, SIM_SCGC6_FTM2(value)))
+#define SIM_BWR_SCGC6_FTM2(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field ADC0[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_ADC0 field. */
+#define SIM_RD_SCGC6_ADC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_ADC0_MASK) >> SIM_SCGC6_ADC0_SHIFT)
+#define SIM_BRD_SCGC6_ADC0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT))
+
+/*! @brief Set the ADC0 field to a new value. */
+#define SIM_WR_SCGC6_ADC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_ADC0_MASK, SIM_SCGC6_ADC0(value)))
+#define SIM_BWR_SCGC6_ADC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RTC[29] (RW)
+ *
+ * This bit controls software access and interrupts to the RTC module.
+ *
+ * Values:
+ * - 0b0 - Access and interrupts disabled
+ * - 0b1 - Access and interrupts enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RTC field. */
+#define SIM_RD_SCGC6_RTC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RTC_MASK) >> SIM_SCGC6_RTC_SHIFT)
+#define SIM_BRD_SCGC6_RTC(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT))
+
+/*! @brief Set the RTC field to a new value. */
+#define SIM_WR_SCGC6_RTC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RTC_MASK, SIM_SCGC6_RTC(value)))
+#define SIM_BWR_SCGC6_RTC(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DAC0[31] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DAC0 field. */
+#define SIM_RD_SCGC6_DAC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DAC0_MASK) >> SIM_SCGC6_DAC0_SHIFT)
+#define SIM_BRD_SCGC6_DAC0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC6_DAC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DAC0_MASK, SIM_SCGC6_DAC0(value)))
+#define SIM_BWR_SCGC6_DAC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC7 - System Clock Gating Control Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
+ *
+ * Reset value: 0x00000006U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC7 register
+ */
+/*@{*/
+#define SIM_RD_SCGC7(base)       (SIM_SCGC7_REG(base))
+#define SIM_WR_SCGC7(base, value) (SIM_SCGC7_REG(base) = (value))
+#define SIM_RMW_SCGC7(base, mask, value) (SIM_WR_SCGC7(base, (SIM_RD_SCGC7(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) |  (value)))
+#define SIM_CLR_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) & ~(value)))
+#define SIM_TOG_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
+ *
+ * This bit controls the clock gate to the FlexBus module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */
+#define SIM_RD_SCGC7_FLEXBUS(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_FLEXBUS_MASK) >> SIM_SCGC7_FLEXBUS_SHIFT)
+#define SIM_BRD_SCGC7_FLEXBUS(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_FLEXBUS_SHIFT))
+
+/*! @brief Set the FLEXBUS field to a new value. */
+#define SIM_WR_SCGC7_FLEXBUS(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_FLEXBUS_MASK, SIM_SCGC7_FLEXBUS(value)))
+#define SIM_BWR_SCGC7_FLEXBUS(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_FLEXBUS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC7, field DMA[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_DMA field. */
+#define SIM_RD_SCGC7_DMA(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_DMA_MASK) >> SIM_SCGC7_DMA_SHIFT)
+#define SIM_BRD_SCGC7_DMA(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define SIM_WR_SCGC7_DMA(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_DMA_MASK, SIM_SCGC7_DMA(value)))
+#define SIM_BWR_SCGC7_DMA(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC7, field MPU[2] (RW)
+ *
+ * This bit controls the clock gate to the MPU module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_MPU field. */
+#define SIM_RD_SCGC7_MPU(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_MPU_MASK) >> SIM_SCGC7_MPU_SHIFT)
+#define SIM_BRD_SCGC7_MPU(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_MPU_SHIFT))
+
+/*! @brief Set the MPU field to a new value. */
+#define SIM_WR_SCGC7_MPU(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_MPU_MASK, SIM_SCGC7_MPU(value)))
+#define SIM_BWR_SCGC7_MPU(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_MPU_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV1 - System Clock Divider Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * When updating CLKDIV1, update all fields using the one write command.
+ * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
+ * write to be ignored. The maximum divide ratio that can be programmed between
+ * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
+ * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
+ * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
+ * mode.
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV1 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV1(base)     (SIM_CLKDIV1_REG(base))
+#define SIM_WR_CLKDIV1(base, value) (SIM_CLKDIV1_REG(base) = (value))
+#define SIM_RMW_CLKDIV1(base, mask, value) (SIM_WR_CLKDIV1(base, (SIM_RD_CLKDIV1(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) |  (value)))
+#define SIM_CLR_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) & ~(value)))
+#define SIM_TOG_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV1 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
+ *
+ * This field sets the divide value for the flash clock from MCGOUTCLK. At the
+ * end of reset, it is loaded with either 0001 or 1111 depending on
+ * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
+ * frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */
+#define SIM_RD_CLKDIV1_OUTDIV4(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV4(base) (SIM_RD_CLKDIV1_OUTDIV4(base))
+
+/*! @brief Set the OUTDIV4 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV4(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV4_MASK, SIM_CLKDIV1_OUTDIV4(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV4(base, value) (SIM_WR_CLKDIV1_OUTDIV4(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
+ *
+ * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
+ * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
+ * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
+ * divide of the system clock frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */
+#define SIM_RD_CLKDIV1_OUTDIV3(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV3(base) (SIM_RD_CLKDIV1_OUTDIV3(base))
+
+/*! @brief Set the OUTDIV3 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV3(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV3_MASK, SIM_CLKDIV1_OUTDIV3(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV3(base, value) (SIM_WR_CLKDIV1_OUTDIV3(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
+ *
+ * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
+ * of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
+ * frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */
+#define SIM_RD_CLKDIV1_OUTDIV2(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV2(base) (SIM_RD_CLKDIV1_OUTDIV2(base))
+
+/*! @brief Set the OUTDIV2 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV2(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV2_MASK, SIM_CLKDIV1_OUTDIV2(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV2(base, value) (SIM_WR_CLKDIV1_OUTDIV2(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
+ *
+ * This field sets the divide value for the core/system clock from MCGOUTCLK. At
+ * the end of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT].
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */
+#define SIM_RD_CLKDIV1_OUTDIV1(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV1(base) (SIM_RD_CLKDIV1_OUTDIV1(base))
+
+/*! @brief Set the OUTDIV1 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV1(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV1_MASK, SIM_CLKDIV1_OUTDIV1(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV1(base, value) (SIM_WR_CLKDIV1_OUTDIV1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV2 - System Clock Divider Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV2 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV2(base)     (SIM_CLKDIV2_REG(base))
+#define SIM_WR_CLKDIV2(base, value) (SIM_CLKDIV2_REG(base) = (value))
+#define SIM_RMW_CLKDIV2(base, mask, value) (SIM_WR_CLKDIV2(base, (SIM_RD_CLKDIV2(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) |  (value)))
+#define SIM_CLR_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) & ~(value)))
+#define SIM_TOG_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV2 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
+ *
+ * This field sets the fraction multiply value for the fractional clock divider
+ * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
+ * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. */
+#define SIM_RD_CLKDIV2_USBFRAC(base) ((SIM_CLKDIV2_REG(base) & SIM_CLKDIV2_USBFRAC_MASK) >> SIM_CLKDIV2_USBFRAC_SHIFT)
+#define SIM_BRD_CLKDIV2_USBFRAC(base) (BITBAND_ACCESS32(&SIM_CLKDIV2_REG(base), SIM_CLKDIV2_USBFRAC_SHIFT))
+
+/*! @brief Set the USBFRAC field to a new value. */
+#define SIM_WR_CLKDIV2_USBFRAC(base, value) (SIM_RMW_CLKDIV2(base, SIM_CLKDIV2_USBFRAC_MASK, SIM_CLKDIV2_USBFRAC(value)))
+#define SIM_BWR_CLKDIV2_USBFRAC(base, value) (BITBAND_ACCESS32(&SIM_CLKDIV2_REG(base), SIM_CLKDIV2_USBFRAC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
+ *
+ * This field sets the divide value for the fractional clock divider when the
+ * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
+ * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV2_USBDIV field. */
+#define SIM_RD_CLKDIV2_USBDIV(base) ((SIM_CLKDIV2_REG(base) & SIM_CLKDIV2_USBDIV_MASK) >> SIM_CLKDIV2_USBDIV_SHIFT)
+#define SIM_BRD_CLKDIV2_USBDIV(base) (SIM_RD_CLKDIV2_USBDIV(base))
+
+/*! @brief Set the USBDIV field to a new value. */
+#define SIM_WR_CLKDIV2_USBDIV(base, value) (SIM_RMW_CLKDIV2(base, SIM_CLKDIV2_USBDIV_MASK, SIM_CLKDIV2_USBDIV(value)))
+#define SIM_BWR_CLKDIV2_USBDIV(base, value) (SIM_WR_CLKDIV2_USBDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG1 - Flash Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG1 - Flash Configuration Register 1 (RW)
+ *
+ * Reset value: 0xFF0F0F00U
+ *
+ * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
+ * user programming in user IFR via the PGMPART flash command. For devices with
+ * program flash only:
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG1 register
+ */
+/*@{*/
+#define SIM_RD_FCFG1(base)       (SIM_FCFG1_REG(base))
+#define SIM_WR_FCFG1(base, value) (SIM_FCFG1_REG(base) = (value))
+#define SIM_RMW_FCFG1(base, mask, value) (SIM_WR_FCFG1(base, (SIM_RD_FCFG1(base) & ~(mask)) | (value)))
+#define SIM_SET_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) |  (value)))
+#define SIM_CLR_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) & ~(value)))
+#define SIM_TOG_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG1 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
+ *
+ * Flash accesses are disabled (and generate a bus error) and the Flash memory
+ * is placed in a low power state. This bit should not be changed during VLP
+ * modes. Relocate the interrupt vectors out of Flash memory before disabling the
+ * Flash.
+ *
+ * Values:
+ * - 0b0 - Flash is enabled
+ * - 0b1 - Flash is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */
+#define SIM_RD_FCFG1_FLASHDIS(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDIS_MASK) >> SIM_FCFG1_FLASHDIS_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDIS(base) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT))
+
+/*! @brief Set the FLASHDIS field to a new value. */
+#define SIM_WR_FCFG1_FLASHDIS(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDIS_MASK, SIM_FCFG1_FLASHDIS(value)))
+#define SIM_BWR_FCFG1_FLASHDIS(base, value) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
+ *
+ * When set, Flash memory is disabled for the duration of Wait mode. An attempt
+ * by the DMA or other bus master to access the Flash when the Flash is disabled
+ * will result in a bus error. This bit should be clear during VLP modes. The
+ * Flash will be automatically enabled again at the end of Wait mode so interrupt
+ * vectors do not need to be relocated out of Flash memory. The wakeup time from
+ * Wait mode is extended when this bit is set.
+ *
+ * Values:
+ * - 0b0 - Flash remains enabled during Wait mode
+ * - 0b1 - Flash is disabled for the duration of Wait mode
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */
+#define SIM_RD_FCFG1_FLASHDOZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDOZE_MASK) >> SIM_FCFG1_FLASHDOZE_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDOZE(base) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT))
+
+/*! @brief Set the FLASHDOZE field to a new value. */
+#define SIM_WR_FCFG1_FLASHDOZE(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDOZE_MASK, SIM_FCFG1_FLASHDOZE(value)))
+#define SIM_BWR_FCFG1_FLASHDOZE(base, value) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
+ *
+ * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
+ * description in FTFE chapter. For devices without FlexNVM: Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_DEPART field. */
+#define SIM_RD_FCFG1_DEPART(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT)
+#define SIM_BRD_FCFG1_DEPART(base) (SIM_RD_FCFG1_DEPART(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
+ *
+ * EEPROM data size .
+ *
+ * Values:
+ * - 0b0000 - 16 KB
+ * - 0b0001 - 8 KB
+ * - 0b0010 - 4 KB
+ * - 0b0011 - 2 KB
+ * - 0b0100 - 1 KB
+ * - 0b0101 - 512 Bytes
+ * - 0b0110 - 256 Bytes
+ * - 0b0111 - 128 Bytes
+ * - 0b1000 - 64 Bytes
+ * - 0b1001 - 32 Bytes
+ * - 0b1111 - 0 Bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_EESIZE field. */
+#define SIM_RD_FCFG1_EESIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_EESIZE_MASK) >> SIM_FCFG1_EESIZE_SHIFT)
+#define SIM_BRD_FCFG1_EESIZE(base) (SIM_RD_FCFG1_EESIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
+ *
+ * This field specifies the amount of program flash memory available on the
+ * device . Undefined values are reserved.
+ *
+ * Values:
+ * - 0b0011 - 32 KB of program flash memory
+ * - 0b0101 - 64 KB of program flash memory
+ * - 0b0111 - 128 KB of program flash memory
+ * - 0b1001 - 256 KB of program flash memory
+ * - 0b1011 - 512 KB of program flash memory
+ * - 0b1101 - 1024 KB of program flash memory
+ * - 0b1111 - 1024 KB of program flash memory
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */
+#define SIM_RD_FCFG1_PFSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT)
+#define SIM_BRD_FCFG1_PFSIZE(base) (SIM_RD_FCFG1_PFSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
+ *
+ * This field specifies the amount of FlexNVM memory available on the device .
+ * Undefined values are reserved.
+ *
+ * Values:
+ * - 0b0000 - 0 KB of FlexNVM
+ * - 0b0011 - 32 KB of FlexNVM
+ * - 0b0101 - 64 KB of FlexNVM
+ * - 0b0111 - 128 KB of FlexNVM
+ * - 0b1001 - 256 KB of FlexNVM
+ * - 0b1011 - 512 KB of FlexNVM
+ * - 0b1111 - 512 KB of FlexNVM
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_NVMSIZE field. */
+#define SIM_RD_FCFG1_NVMSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_NVMSIZE_MASK) >> SIM_FCFG1_NVMSIZE_SHIFT)
+#define SIM_BRD_FCFG1_NVMSIZE(base) (SIM_RD_FCFG1_NVMSIZE(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG2 - Flash Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG2 - Flash Configuration Register 2 (RO)
+ *
+ * Reset value: 0x7F7F0000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG2 register
+ */
+/*@{*/
+#define SIM_RD_FCFG2(base)       (SIM_FCFG2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG2 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
+ *
+ * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
+ * the FlexNVM base address indicates the first invalid address of the FlexNVM
+ * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
+ * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
+ * for a device with 256 KB FlexNVM. For devices with program flash only: This
+ * field equals zero if there is only one program flash block, otherwise it equals
+ * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
+ * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
+ * the MAXADDR1 value for a device with 512 KB program flash memory across two
+ * flash blocks and no FlexNVM.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */
+#define SIM_RD_FCFG2_MAXADDR1(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR1_MASK) >> SIM_FCFG2_MAXADDR1_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR1(base) (SIM_RD_FCFG2_MAXADDR1(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field PFLSH[23] (RO)
+ *
+ * For devices with FlexNVM, this bit is always clear. For devices without
+ * FlexNVM, this bit is always set.
+ *
+ * Values:
+ * - 0b0 - Device supports FlexNVM
+ * - 0b1 - Program Flash only, device does not support FlexNVM
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_PFLSH field. */
+#define SIM_RD_FCFG2_PFLSH(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_PFLSH_MASK) >> SIM_FCFG2_PFLSH_SHIFT)
+#define SIM_BRD_FCFG2_PFLSH(base) (BITBAND_ACCESS32(&SIM_FCFG2_REG(base), SIM_FCFG2_PFLSH_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
+ *
+ * This field concatenated with 13 trailing zeros indicates the first invalid
+ * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
+ * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
+ * value for a device with 256 KB program flash in flash block 0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */
+#define SIM_RD_FCFG2_MAXADDR0(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR0_MASK) >> SIM_FCFG2_MAXADDR0_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR0(base) (SIM_RD_FCFG2_MAXADDR0(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDH - Unique Identification Register High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDH - Unique Identification Register High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDH register
+ */
+/*@{*/
+#define SIM_RD_UIDH(base)        (SIM_UIDH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDMH - Unique Identification Register Mid-High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDMH - Unique Identification Register Mid-High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDMH register
+ */
+/*@{*/
+#define SIM_RD_UIDMH(base)       (SIM_UIDMH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDML - Unique Identification Register Mid Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDML - Unique Identification Register Mid Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDML register
+ */
+/*@{*/
+#define SIM_RD_UIDML(base)       (SIM_UIDML_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDL - Unique Identification Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDL - Unique Identification Register Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDL register
+ */
+/*@{*/
+#define SIM_RD_UIDL(base)        (SIM_UIDL_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 SMC
+ *
+ * System Mode Controller
+ *
+ * Registers defined in this header file:
+ * - SMC_PMPROT - Power Mode Protection register
+ * - SMC_PMCTRL - Power Mode Control register
+ * - SMC_VLLSCTRL - VLLS Control register
+ * - SMC_PMSTAT - Power Mode Status register
+ */
+
+#define SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
+#define SMC_IDX (0U) /*!< Instance number for SMC. */
+
+/*******************************************************************************
+ * SMC_PMPROT - Power Mode Protection register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMPROT - Power Mode Protection register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides protection for entry into any low-power run or stop
+ * mode. The enabling of the low-power run or stop mode occurs by configuring the
+ * Power Mode Control register (PMCTRL). The PMPROT register can be written only
+ * once after any system reset. If the MCU is configured for a disallowed or
+ * reserved power mode, the MCU remains in its current power mode. For example, if the
+ * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
+ * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
+ * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
+ * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
+ * that do not trigger Chip Reset not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMPROT register
+ */
+/*@{*/
+#define SMC_RD_PMPROT(base)      (SMC_PMPROT_REG(base))
+#define SMC_WR_PMPROT(base, value) (SMC_PMPROT_REG(base) = (value))
+#define SMC_RMW_PMPROT(base, mask, value) (SMC_WR_PMPROT(base, (SMC_RD_PMPROT(base) & ~(mask)) | (value)))
+#define SMC_SET_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) |  (value)))
+#define SMC_CLR_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) & ~(value)))
+#define SMC_TOG_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMPROT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMPROT, field AVLLS[1] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write once
+ * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
+ *
+ * Values:
+ * - 0b0 - Any VLLSx mode is not allowed
+ * - 0b1 - Any VLLSx mode is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
+#define SMC_RD_PMPROT_AVLLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLLS_MASK) >> SMC_PMPROT_AVLLS_SHIFT)
+#define SMC_BRD_PMPROT_AVLLS(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT))
+
+/*! @brief Set the AVLLS field to a new value. */
+#define SMC_WR_PMPROT_AVLLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLLS_MASK, SMC_PMPROT_AVLLS(value)))
+#define SMC_BWR_PMPROT_AVLLS(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field ALLS[3] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any low-leakage stop mode (LLS).
+ *
+ * Values:
+ * - 0b0 - LLS is not allowed
+ * - 0b1 - LLS is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_ALLS field. */
+#define SMC_RD_PMPROT_ALLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_ALLS_MASK) >> SMC_PMPROT_ALLS_SHIFT)
+#define SMC_BRD_PMPROT_ALLS(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT))
+
+/*! @brief Set the ALLS field to a new value. */
+#define SMC_WR_PMPROT_ALLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_ALLS_MASK, SMC_PMPROT_ALLS(value)))
+#define SMC_BWR_PMPROT_ALLS(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field AVLP[5] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
+ *
+ * Values:
+ * - 0b0 - VLPR, VLPW, and VLPS are not allowed.
+ * - 0b1 - VLPR, VLPW, and VLPS are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLP field. */
+#define SMC_RD_PMPROT_AVLP(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLP_MASK) >> SMC_PMPROT_AVLP_SHIFT)
+#define SMC_BRD_PMPROT_AVLP(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT))
+
+/*! @brief Set the AVLP field to a new value. */
+#define SMC_WR_PMPROT_AVLP(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLP_MASK, SMC_PMPROT_AVLP(value)))
+#define SMC_BWR_PMPROT_AVLP(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMCTRL - Power Mode Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMCTRL - Power Mode Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The PMCTRL register controls entry into low-power Run and Stop modes,
+ * provided that the selected power mode is allowed via an appropriate setting of the
+ * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
+ * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
+ * that do not trigger Chip POR not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMCTRL register
+ */
+/*@{*/
+#define SMC_RD_PMCTRL(base)      (SMC_PMCTRL_REG(base))
+#define SMC_WR_PMCTRL(base, value) (SMC_PMCTRL_REG(base) = (value))
+#define SMC_RMW_PMCTRL(base, mask, value) (SMC_WR_PMCTRL(base, (SMC_RD_PMCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) |  (value)))
+#define SMC_CLR_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) & ~(value)))
+#define SMC_TOG_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
+ *
+ * When written, controls entry into the selected stop mode when Sleep-Now or
+ * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
+ * blocked if the protection level has not been enabled using the PMPROT register.
+ * After any system reset, this field is cleared by hardware on any successful write
+ * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
+ * register is used to further select the particular VLLS submode which will be
+ * entered.
+ *
+ * Values:
+ * - 0b000 - Normal Stop (STOP)
+ * - 0b001 - Reserved
+ * - 0b010 - Very-Low-Power Stop (VLPS)
+ * - 0b011 - Low-Leakage Stop (LLS)
+ * - 0b100 - Very-Low-Leakage Stop (VLLSx)
+ * - 0b101 - Reserved
+ * - 0b110 - Reseved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
+#define SMC_RD_PMCTRL_STOPM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPM_MASK) >> SMC_PMCTRL_STOPM_SHIFT)
+#define SMC_BRD_PMCTRL_STOPM(base) (SMC_RD_PMCTRL_STOPM(base))
+
+/*! @brief Set the STOPM field to a new value. */
+#define SMC_WR_PMCTRL_STOPM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_STOPM_MASK, SMC_PMCTRL_STOPM(value)))
+#define SMC_BWR_PMCTRL_STOPM(base, value) (SMC_WR_PMCTRL_STOPM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPA[3] (RO)
+ *
+ * When set, this read-only status bit indicates an interrupt or reset occured
+ * during the previous stop mode entry sequence, preventing the system from
+ * entering that mode. This field is cleared by hardware at the beginning of any stop
+ * mode entry sequence and is set if the sequence was aborted.
+ *
+ * Values:
+ * - 0b0 - The previous stop mode entry was successsful.
+ * - 0b1 - The previous stop mode entry was aborted.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
+#define SMC_RD_PMCTRL_STOPA(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPA_MASK) >> SMC_PMCTRL_STOPA_SHIFT)
+#define SMC_BRD_PMCTRL_STOPA(base) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_STOPA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
+ *
+ * When written, causes entry into the selected run mode. Writes to this field
+ * are blocked if the protection level has not been enabled using the PMPROT
+ * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
+ * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
+ *
+ * Values:
+ * - 0b00 - Normal Run mode (RUN)
+ * - 0b01 - Reserved
+ * - 0b10 - Very-Low-Power Run mode (VLPR)
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
+#define SMC_RD_PMCTRL_RUNM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_RUNM_MASK) >> SMC_PMCTRL_RUNM_SHIFT)
+#define SMC_BRD_PMCTRL_RUNM(base) (SMC_RD_PMCTRL_RUNM(base))
+
+/*! @brief Set the RUNM field to a new value. */
+#define SMC_WR_PMCTRL_RUNM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_RUNM_MASK, SMC_PMCTRL_RUNM(value)))
+#define SMC_BWR_PMCTRL_RUNM(base, value) (SMC_WR_PMCTRL_RUNM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
+ *
+ * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
+ * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
+ * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
+ * the LPWUI setting. LPWUI must be modified only while the system is in RUN
+ * mode, that is, when PMSTAT=RUN.
+ *
+ * Values:
+ * - 0b0 - The system remains in a VLP mode on an interrupt
+ * - 0b1 - The system exits to Normal RUN mode on an interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_LPWUI field. */
+#define SMC_RD_PMCTRL_LPWUI(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_LPWUI_MASK) >> SMC_PMCTRL_LPWUI_SHIFT)
+#define SMC_BRD_PMCTRL_LPWUI(base) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_LPWUI_SHIFT))
+
+/*! @brief Set the LPWUI field to a new value. */
+#define SMC_WR_PMCTRL_LPWUI(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_LPWUI_MASK, SMC_PMCTRL_LPWUI(value)))
+#define SMC_BWR_PMCTRL_LPWUI(base, value) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_LPWUI_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_VLLSCTRL - VLLS Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_VLLSCTRL - VLLS Control register (RW)
+ *
+ * Reset value: 0x03U
+ *
+ * The VLLSCTRL register controls features related to VLLS modes. This register
+ * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
+ * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
+ * the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_VLLSCTRL register
+ */
+/*@{*/
+#define SMC_RD_VLLSCTRL(base)    (SMC_VLLSCTRL_REG(base))
+#define SMC_WR_VLLSCTRL(base, value) (SMC_VLLSCTRL_REG(base) = (value))
+#define SMC_RMW_VLLSCTRL(base, mask, value) (SMC_WR_VLLSCTRL(base, (SMC_RD_VLLSCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) |  (value)))
+#define SMC_CLR_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) & ~(value)))
+#define SMC_TOG_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_VLLSCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
+ *
+ * Controls which VLLS sub-mode to enter if STOPM=VLLS.
+ *
+ * Values:
+ * - 0b000 - VLLS0
+ * - 0b001 - VLLS1
+ * - 0b010 - VLLS2
+ * - 0b011 - VLLS3
+ * - 0b100 - Reserved
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_VLLSCTRL_VLLSM field. */
+#define SMC_RD_VLLSCTRL_VLLSM(base) ((SMC_VLLSCTRL_REG(base) & SMC_VLLSCTRL_VLLSM_MASK) >> SMC_VLLSCTRL_VLLSM_SHIFT)
+#define SMC_BRD_VLLSCTRL_VLLSM(base) (SMC_RD_VLLSCTRL_VLLSM(base))
+
+/*! @brief Set the VLLSM field to a new value. */
+#define SMC_WR_VLLSCTRL_VLLSM(base, value) (SMC_RMW_VLLSCTRL(base, SMC_VLLSCTRL_VLLSM_MASK, SMC_VLLSCTRL_VLLSM(value)))
+#define SMC_BWR_VLLSCTRL_VLLSM(base, value) (SMC_WR_VLLSCTRL_VLLSM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
+ *
+ * Controls whether the POR detect circuit (for brown-out detection) is enabled
+ * in VLLS0 mode.
+ *
+ * Values:
+ * - 0b0 - POR detect circuit is enabled in VLLS0.
+ * - 0b1 - POR detect circuit is disabled in VLLS0.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_VLLSCTRL_PORPO field. */
+#define SMC_RD_VLLSCTRL_PORPO(base) ((SMC_VLLSCTRL_REG(base) & SMC_VLLSCTRL_PORPO_MASK) >> SMC_VLLSCTRL_PORPO_SHIFT)
+#define SMC_BRD_VLLSCTRL_PORPO(base) (BITBAND_ACCESS8(&SMC_VLLSCTRL_REG(base), SMC_VLLSCTRL_PORPO_SHIFT))
+
+/*! @brief Set the PORPO field to a new value. */
+#define SMC_WR_VLLSCTRL_PORPO(base, value) (SMC_RMW_VLLSCTRL(base, SMC_VLLSCTRL_PORPO_MASK, SMC_VLLSCTRL_PORPO(value)))
+#define SMC_BWR_VLLSCTRL_PORPO(base, value) (BITBAND_ACCESS8(&SMC_VLLSCTRL_REG(base), SMC_VLLSCTRL_PORPO_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMSTAT - Power Mode Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMSTAT - Power Mode Status register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * PMSTAT is a read-only, one-hot register which indicates the current power
+ * mode of the system. This register is reset on Chip POR not VLLS and by reset
+ * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
+ * trigger Chip POR not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMSTAT register
+ */
+/*@{*/
+#define SMC_RD_PMSTAT(base)      (SMC_PMSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMSTAT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
+ *
+ * When debug is enabled, the PMSTAT will not update to STOP or VLPS
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */
+#define SMC_RD_PMSTAT_PMSTAT(base) ((SMC_PMSTAT_REG(base) & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT)
+#define SMC_BRD_PMSTAT_PMSTAT(base) (SMC_RD_PMSTAT_PMSTAT(base))
+/*@}*/
+
+/*
+ * MK64F12 SPI
+ *
+ * Serial Peripheral Interface
+ *
+ * Registers defined in this header file:
+ * - SPI_MCR - Module Configuration Register
+ * - SPI_TCR - Transfer Count Register
+ * - SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
+ * - SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ * - SPI_SR - Status Register
+ * - SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ * - SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ * - SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ * - SPI_POPR - POP RX FIFO Register
+ * - SPI_TXFR0 - Transmit FIFO Registers
+ * - SPI_TXFR1 - Transmit FIFO Registers
+ * - SPI_TXFR2 - Transmit FIFO Registers
+ * - SPI_TXFR3 - Transmit FIFO Registers
+ * - SPI_RXFR0 - Receive FIFO Registers
+ * - SPI_RXFR1 - Receive FIFO Registers
+ * - SPI_RXFR2 - Receive FIFO Registers
+ * - SPI_RXFR3 - Receive FIFO Registers
+ */
+
+#define SPI_INSTANCE_COUNT (3U) /*!< Number of instances of the SPI module. */
+#define SPI0_IDX (0U) /*!< Instance number for SPI0. */
+#define SPI1_IDX (1U) /*!< Instance number for SPI1. */
+#define SPI2_IDX (2U) /*!< Instance number for SPI2. */
+
+/*******************************************************************************
+ * SPI_MCR - Module Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0x00004001U
+ *
+ * Contains bits to configure various attributes associated with the module
+ * operations. The HALT and MDIS bits can be changed at any time, but the effect
+ * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
+ * MCR can be changed, while the module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_MCR register
+ */
+/*@{*/
+#define SPI_RD_MCR(base)         (SPI_MCR_REG(base))
+#define SPI_WR_MCR(base, value)  (SPI_MCR_REG(base) = (value))
+#define SPI_RMW_MCR(base, mask, value) (SPI_WR_MCR(base, (SPI_RD_MCR(base) & ~(mask)) | (value)))
+#define SPI_SET_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) |  (value)))
+#define SPI_CLR_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) & ~(value)))
+#define SPI_TOG_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_MCR bitfields
+ */
+
+/*!
+ * @name Register SPI_MCR, field HALT[0] (RW)
+ *
+ * The HALT bit starts and stops frame transfers. See Start and Stop of Module
+ * transfers
+ *
+ * Values:
+ * - 0b0 - Start transfers.
+ * - 0b1 - Stop transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_HALT field. */
+#define SPI_RD_MCR_HALT(base) ((SPI_MCR_REG(base) & SPI_MCR_HALT_MASK) >> SPI_MCR_HALT_SHIFT)
+#define SPI_BRD_MCR_HALT(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define SPI_WR_MCR_HALT(base, value) (SPI_RMW_MCR(base, SPI_MCR_HALT_MASK, SPI_MCR_HALT(value)))
+#define SPI_BWR_MCR_HALT(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
+ *
+ * Controls when the module master samples SIN in Modified Transfer Format. This
+ * field is valid only when CPHA bit in CTARn[CPHA] is 0.
+ *
+ * Values:
+ * - 0b00 - 0 protocol clock cycles between SCK edge and SIN sample
+ * - 0b01 - 1 protocol clock cycle between SCK edge and SIN sample
+ * - 0b10 - 2 protocol clock cycles between SCK edge and SIN sample
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_SMPL_PT field. */
+#define SPI_RD_MCR_SMPL_PT(base) ((SPI_MCR_REG(base) & SPI_MCR_SMPL_PT_MASK) >> SPI_MCR_SMPL_PT_SHIFT)
+#define SPI_BRD_MCR_SMPL_PT(base) (SPI_RD_MCR_SMPL_PT(base))
+
+/*! @brief Set the SMPL_PT field to a new value. */
+#define SPI_WR_MCR_SMPL_PT(base, value) (SPI_RMW_MCR(base, SPI_MCR_SMPL_PT_MASK, SPI_MCR_SMPL_PT(value)))
+#define SPI_BWR_MCR_SMPL_PT(base, value) (SPI_WR_MCR_SMPL_PT(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
+ *
+ * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
+ * CLR_RXF bit is always read as zero.
+ *
+ * Values:
+ * - 0b0 - Do not clear the RX FIFO counter.
+ * - 0b1 - Clear the RX FIFO counter.
+ */
+/*@{*/
+/*! @brief Set the CLR_RXF field to a new value. */
+#define SPI_WR_MCR_CLR_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_RXF_MASK, SPI_MCR_CLR_RXF(value)))
+#define SPI_BWR_MCR_CLR_RXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CLR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
+ *
+ * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
+ * CLR_TXF bit is always read as zero.
+ *
+ * Values:
+ * - 0b0 - Do not clear the TX FIFO counter.
+ * - 0b1 - Clear the TX FIFO counter.
+ */
+/*@{*/
+/*! @brief Set the CLR_TXF field to a new value. */
+#define SPI_WR_MCR_CLR_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_TXF_MASK, SPI_MCR_CLR_TXF(value)))
+#define SPI_BWR_MCR_CLR_TXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CLR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DIS_RXF[12] (RW)
+ *
+ * When the RX FIFO is disabled, the receive part of the module operates as a
+ * simplified double-buffered SPI. This bit can only be written when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0b0 - RX FIFO is enabled.
+ * - 0b1 - RX FIFO is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DIS_RXF field. */
+#define SPI_RD_MCR_DIS_RXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_RXF_MASK) >> SPI_MCR_DIS_RXF_SHIFT)
+#define SPI_BRD_MCR_DIS_RXF(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT))
+
+/*! @brief Set the DIS_RXF field to a new value. */
+#define SPI_WR_MCR_DIS_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_RXF_MASK, SPI_MCR_DIS_RXF(value)))
+#define SPI_BWR_MCR_DIS_RXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DIS_TXF[13] (RW)
+ *
+ * When the TX FIFO is disabled, the transmit part of the module operates as a
+ * simplified double-buffered SPI. This bit can be written only when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0b0 - TX FIFO is enabled.
+ * - 0b1 - TX FIFO is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DIS_TXF field. */
+#define SPI_RD_MCR_DIS_TXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_TXF_MASK) >> SPI_MCR_DIS_TXF_SHIFT)
+#define SPI_BRD_MCR_DIS_TXF(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT))
+
+/*! @brief Set the DIS_TXF field to a new value. */
+#define SPI_WR_MCR_DIS_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_TXF_MASK, SPI_MCR_DIS_TXF(value)))
+#define SPI_BWR_MCR_DIS_TXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MDIS[14] (RW)
+ *
+ * Allows the clock to be stopped to the non-memory mapped logic in the module
+ * effectively putting it in a software-controlled power-saving state. The reset
+ * value of the MDIS bit is parameterized, with a default reset value of 0. When
+ * the module is used in Slave Mode, we recommend leaving this bit 0, because a
+ * slave doesn't have control over master transactions.
+ *
+ * Values:
+ * - 0b0 - Enables the module clocks.
+ * - 0b1 - Allows external logic to disable the module clocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MDIS field. */
+#define SPI_RD_MCR_MDIS(base) ((SPI_MCR_REG(base) & SPI_MCR_MDIS_MASK) >> SPI_MCR_MDIS_SHIFT)
+#define SPI_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define SPI_WR_MCR_MDIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_MDIS_MASK, SPI_MCR_MDIS(value)))
+#define SPI_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DOZE[15] (RW)
+ *
+ * Provides support for an externally controlled Doze mode power-saving
+ * mechanism.
+ *
+ * Values:
+ * - 0b0 - Doze mode has no effect on the module.
+ * - 0b1 - Doze mode disables the module.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DOZE field. */
+#define SPI_RD_MCR_DOZE(base) ((SPI_MCR_REG(base) & SPI_MCR_DOZE_MASK) >> SPI_MCR_DOZE_SHIFT)
+#define SPI_BRD_MCR_DOZE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT))
+
+/*! @brief Set the DOZE field to a new value. */
+#define SPI_WR_MCR_DOZE(base, value) (SPI_RMW_MCR(base, SPI_MCR_DOZE_MASK, SPI_MCR_DOZE(value)))
+#define SPI_BWR_MCR_DOZE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field PCSIS[21:16] (RW)
+ *
+ * Determines the inactive state of PCSx.
+ *
+ * Values:
+ * - 0b000000 - The inactive state of PCSx is low.
+ * - 0b000001 - The inactive state of PCSx is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_PCSIS field. */
+#define SPI_RD_MCR_PCSIS(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSIS_MASK) >> SPI_MCR_PCSIS_SHIFT)
+#define SPI_BRD_MCR_PCSIS(base) (SPI_RD_MCR_PCSIS(base))
+
+/*! @brief Set the PCSIS field to a new value. */
+#define SPI_WR_MCR_PCSIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSIS_MASK, SPI_MCR_PCSIS(value)))
+#define SPI_BWR_MCR_PCSIS(base, value) (SPI_WR_MCR_PCSIS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field ROOE[24] (RW)
+ *
+ * In the RX FIFO overflow condition, configures the module to ignore the
+ * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
+ * is received, the data from the transfer, generating the overflow, is ignored
+ * or shifted into the shift register.
+ *
+ * Values:
+ * - 0b0 - Incoming data is ignored.
+ * - 0b1 - Incoming data is shifted into the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_ROOE field. */
+#define SPI_RD_MCR_ROOE(base) ((SPI_MCR_REG(base) & SPI_MCR_ROOE_MASK) >> SPI_MCR_ROOE_SHIFT)
+#define SPI_BRD_MCR_ROOE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT))
+
+/*! @brief Set the ROOE field to a new value. */
+#define SPI_WR_MCR_ROOE(base, value) (SPI_RMW_MCR(base, SPI_MCR_ROOE_MASK, SPI_MCR_ROOE(value)))
+#define SPI_BWR_MCR_ROOE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field PCSSE[25] (RW)
+ *
+ * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
+ *
+ * Values:
+ * - 0b0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
+ * - 0b1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_PCSSE field. */
+#define SPI_RD_MCR_PCSSE(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSSE_MASK) >> SPI_MCR_PCSSE_SHIFT)
+#define SPI_BRD_MCR_PCSSE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_PCSSE_SHIFT))
+
+/*! @brief Set the PCSSE field to a new value. */
+#define SPI_WR_MCR_PCSSE(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSSE_MASK, SPI_MCR_PCSSE(value)))
+#define SPI_BWR_MCR_PCSSE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_PCSSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MTFE[26] (RW)
+ *
+ * Enables a modified transfer format to be used.
+ *
+ * Values:
+ * - 0b0 - Modified SPI transfer format disabled.
+ * - 0b1 - Modified SPI transfer format enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MTFE field. */
+#define SPI_RD_MCR_MTFE(base) ((SPI_MCR_REG(base) & SPI_MCR_MTFE_MASK) >> SPI_MCR_MTFE_SHIFT)
+#define SPI_BRD_MCR_MTFE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT))
+
+/*! @brief Set the MTFE field to a new value. */
+#define SPI_WR_MCR_MTFE(base, value) (SPI_RMW_MCR(base, SPI_MCR_MTFE_MASK, SPI_MCR_MTFE(value)))
+#define SPI_BWR_MCR_MTFE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field FRZ[27] (RW)
+ *
+ * Enables transfers to be stopped on the next frame boundary when the device
+ * enters Debug mode.
+ *
+ * Values:
+ * - 0b0 - Do not halt serial transfers in Debug mode.
+ * - 0b1 - Halt serial transfers in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_FRZ field. */
+#define SPI_RD_MCR_FRZ(base) ((SPI_MCR_REG(base) & SPI_MCR_FRZ_MASK) >> SPI_MCR_FRZ_SHIFT)
+#define SPI_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define SPI_WR_MCR_FRZ(base, value) (SPI_RMW_MCR(base, SPI_MCR_FRZ_MASK, SPI_MCR_FRZ(value)))
+#define SPI_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DCONF[29:28] (RO)
+ *
+ * Selects among the different configurations of the module.
+ *
+ * Values:
+ * - 0b00 - SPI
+ * - 0b01 - Reserved
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DCONF field. */
+#define SPI_RD_MCR_DCONF(base) ((SPI_MCR_REG(base) & SPI_MCR_DCONF_MASK) >> SPI_MCR_DCONF_SHIFT)
+#define SPI_BRD_MCR_DCONF(base) (SPI_RD_MCR_DCONF(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
+ *
+ * Enables the Serial Communication Clock (SCK) to run continuously.
+ *
+ * Values:
+ * - 0b0 - Continuous SCK disabled.
+ * - 0b1 - Continuous SCK enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */
+#define SPI_RD_MCR_CONT_SCKE(base) ((SPI_MCR_REG(base) & SPI_MCR_CONT_SCKE_MASK) >> SPI_MCR_CONT_SCKE_SHIFT)
+#define SPI_BRD_MCR_CONT_SCKE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT))
+
+/*! @brief Set the CONT_SCKE field to a new value. */
+#define SPI_WR_MCR_CONT_SCKE(base, value) (SPI_RMW_MCR(base, SPI_MCR_CONT_SCKE_MASK, SPI_MCR_CONT_SCKE(value)))
+#define SPI_BWR_MCR_CONT_SCKE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MSTR[31] (RW)
+ *
+ * Enables either Master mode (if supported) or Slave mode (if supported)
+ * operation.
+ *
+ * Values:
+ * - 0b0 - Enables Slave mode
+ * - 0b1 - Enables Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MSTR field. */
+#define SPI_RD_MCR_MSTR(base) ((SPI_MCR_REG(base) & SPI_MCR_MSTR_MASK) >> SPI_MCR_MSTR_SHIFT)
+#define SPI_BRD_MCR_MSTR(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT))
+
+/*! @brief Set the MSTR field to a new value. */
+#define SPI_WR_MCR_MSTR(base, value) (SPI_RMW_MCR(base, SPI_MCR_MSTR_MASK, SPI_MCR_MSTR(value)))
+#define SPI_BWR_MCR_MSTR(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TCR - Transfer Count Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TCR - Transfer Count Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR contains a counter that indicates the number of SPI transfers made. The
+ * transfer counter is intended to assist in queue management. Do not write the
+ * TCR when the module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TCR register
+ */
+/*@{*/
+#define SPI_RD_TCR(base)         (SPI_TCR_REG(base))
+#define SPI_WR_TCR(base, value)  (SPI_TCR_REG(base) = (value))
+#define SPI_RMW_TCR(base, mask, value) (SPI_WR_TCR(base, (SPI_RD_TCR(base) & ~(mask)) | (value)))
+#define SPI_SET_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) |  (value)))
+#define SPI_CLR_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) & ~(value)))
+#define SPI_TOG_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TCR bitfields
+ */
+
+/*!
+ * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
+ *
+ * Counts the number of SPI transfers the module makes. The SPI_TCNT field
+ * increments every time the last bit of an SPI frame is transmitted. A value written
+ * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
+ * the beginning of the frame when the CTCNT field is set in the executing SPI
+ * command. The Transfer Counter wraps around; incrementing the counter past 65535
+ * resets the counter to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */
+#define SPI_RD_TCR_SPI_TCNT(base) ((SPI_TCR_REG(base) & SPI_TCR_SPI_TCNT_MASK) >> SPI_TCR_SPI_TCNT_SHIFT)
+#define SPI_BRD_TCR_SPI_TCNT(base) (SPI_RD_TCR_SPI_TCNT(base))
+
+/*! @brief Set the SPI_TCNT field to a new value. */
+#define SPI_WR_TCR_SPI_TCNT(base, value) (SPI_RMW_TCR(base, SPI_TCR_SPI_TCNT_MASK, SPI_TCR_SPI_TCNT(value)))
+#define SPI_BWR_TCR_SPI_TCNT(base, value) (SPI_WR_TCR_SPI_TCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * When the module is configured as an SPI bus slave, the CTAR0 register is used.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CTAR_SLAVE register
+ */
+/*@{*/
+#define SPI_RD_CTAR_SLAVE(base, index) (SPI_CTAR_SLAVE_REG(base, index))
+#define SPI_WR_CTAR_SLAVE(base, index, value) (SPI_CTAR_SLAVE_REG(base, index) = (value))
+#define SPI_RMW_CTAR_SLAVE(base, index, mask, value) (SPI_WR_CTAR_SLAVE(base, index, (SPI_RD_CTAR_SLAVE(base, index) & ~(mask)) | (value)))
+#define SPI_SET_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) |  (value)))
+#define SPI_CLR_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) & ~(value)))
+#define SPI_TOG_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CTAR_SLAVE bitfields
+ */
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0b0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 0b1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_CPHA field. */
+#define SPI_RD_CTAR_SLAVE_CPHA(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPHA_MASK) >> SPI_CTAR_SLAVE_CPHA_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_CPHA(base, index) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_CTAR_SLAVE_CPHA(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPHA_MASK, SPI_CTAR_SLAVE_CPHA(value)))
+#define SPI_BWR_CTAR_SLAVE_CPHA(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0b0 - The inactive state value of SCK is low.
+ * - 0b1 - The inactive state value of SCK is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_CPOL field. */
+#define SPI_RD_CTAR_SLAVE_CPOL(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPOL_MASK) >> SPI_CTAR_SLAVE_CPOL_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_CPOL(base, index) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_CTAR_SLAVE_CPOL(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPOL_MASK, SPI_CTAR_SLAVE_CPOL(value)))
+#define SPI_BWR_CTAR_SLAVE_CPOL(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field FMSZ[31:27] (RW)
+ *
+ * The number of bits transfered per frame is equal to the FMSZ field value plus
+ * 1. Note that the minimum valid value of frame size is 4.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_FMSZ field. */
+#define SPI_RD_CTAR_SLAVE_FMSZ(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_FMSZ(base, index) (SPI_RD_CTAR_SLAVE_FMSZ(base, index))
+
+/*! @brief Set the FMSZ field to a new value. */
+#define SPI_WR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_FMSZ_MASK, SPI_CTAR_SLAVE_FMSZ(value)))
+#define SPI_BWR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_WR_CTAR_SLAVE_FMSZ(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * CTAR registers are used to define different transfer attributes. Do not write
+ * to the CTAR registers while the module is in the Running state. In Master
+ * mode, the CTAR registers define combinations of transfer attributes such as frame
+ * size, clock phase and polarity, data bit ordering, baud rate, and various
+ * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
+ * slave transfer attributes. When the module is configured as an SPI master, the
+ * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
+ * registers is used. When the module is configured as an SPI bus slave, it uses
+ * the CTAR0 register.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CTAR register
+ */
+/*@{*/
+#define SPI_RD_CTAR(base, index) (SPI_CTAR_REG(base, index))
+#define SPI_WR_CTAR(base, index, value) (SPI_CTAR_REG(base, index) = (value))
+#define SPI_RMW_CTAR(base, index, mask, value) (SPI_WR_CTAR(base, index, (SPI_RD_CTAR(base, index) & ~(mask)) | (value)))
+#define SPI_SET_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) |  (value)))
+#define SPI_CLR_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) & ~(value)))
+#define SPI_TOG_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CTAR bitfields
+ */
+
+/*!
+ * @name Register SPI_CTAR, field BR[3:0] (RW)
+ *
+ * Selects the scaler value for the baud rate. This field is used only in master
+ * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
+ * generate the frequency of the SCK. The baud rate is computed according to the
+ * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
+ * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
+ * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
+ * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_BR field. */
+#define SPI_RD_CTAR_BR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_BR_MASK) >> SPI_CTAR_BR_SHIFT)
+#define SPI_BRD_CTAR_BR(base, index) (SPI_RD_CTAR_BR(base, index))
+
+/*! @brief Set the BR field to a new value. */
+#define SPI_WR_CTAR_BR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_BR_MASK, SPI_CTAR_BR(value)))
+#define SPI_BWR_CTAR_BR(base, index, value) (SPI_WR_CTAR_BR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field DT[7:4] (RW)
+ *
+ * Selects the Delay after Transfer Scaler. This field is used only in master
+ * mode. The Delay after Transfer is the time between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the next
+ * frame. In the Continuous Serial Communications Clock operation, the DT value
+ * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
+ * protocol clock period, and it is computed according to the following
+ * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
+ * field description for scaler values.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_DT field. */
+#define SPI_RD_CTAR_DT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DT_MASK) >> SPI_CTAR_DT_SHIFT)
+#define SPI_BRD_CTAR_DT(base, index) (SPI_RD_CTAR_DT(base, index))
+
+/*! @brief Set the DT field to a new value. */
+#define SPI_WR_CTAR_DT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DT_MASK, SPI_CTAR_DT(value)))
+#define SPI_BWR_CTAR_DT(base, index, value) (SPI_WR_CTAR_DT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field ASC[11:8] (RW)
+ *
+ * Selects the scaler value for the After SCK Delay. This field is used only in
+ * master mode. The After SCK Delay is the delay between the last edge of SCK and
+ * the negation of PCS. The delay is a multiple of the protocol clock period,
+ * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
+ * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
+ * scaler values. Refer After SCK Delay (tASC ) for more details.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_ASC field. */
+#define SPI_RD_CTAR_ASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_ASC_MASK) >> SPI_CTAR_ASC_SHIFT)
+#define SPI_BRD_CTAR_ASC(base, index) (SPI_RD_CTAR_ASC(base, index))
+
+/*! @brief Set the ASC field to a new value. */
+#define SPI_WR_CTAR_ASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_ASC_MASK, SPI_CTAR_ASC(value)))
+#define SPI_BWR_CTAR_ASC(base, index, value) (SPI_WR_CTAR_ASC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CSSCK[15:12] (RW)
+ *
+ * Selects the scaler value for the PCS to SCK delay. This field is used only in
+ * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
+ * and the first edge of the SCK. The delay is a multiple of the protocol clock
+ * period, and it is computed according to the following equation: t CSC = (1/fP )
+ * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
+ * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
+ * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
+ * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
+ * details.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CSSCK field. */
+#define SPI_RD_CTAR_CSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CSSCK_MASK) >> SPI_CTAR_CSSCK_SHIFT)
+#define SPI_BRD_CTAR_CSSCK(base, index) (SPI_RD_CTAR_CSSCK(base, index))
+
+/*! @brief Set the CSSCK field to a new value. */
+#define SPI_WR_CTAR_CSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CSSCK_MASK, SPI_CTAR_CSSCK(value)))
+#define SPI_BWR_CTAR_CSSCK(base, index, value) (SPI_WR_CTAR_CSSCK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PBR[17:16] (RW)
+ *
+ * Selects the prescaler value for the baud rate. This field is used only in
+ * master mode. The baud rate is the frequency of the SCK. The protocol clock is
+ * divided by the prescaler value before the baud rate selection takes place. See
+ * the BR field description for details on how to compute the baud rate.
+ *
+ * Values:
+ * - 0b00 - Baud Rate Prescaler value is 2.
+ * - 0b01 - Baud Rate Prescaler value is 3.
+ * - 0b10 - Baud Rate Prescaler value is 5.
+ * - 0b11 - Baud Rate Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PBR field. */
+#define SPI_RD_CTAR_PBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PBR_MASK) >> SPI_CTAR_PBR_SHIFT)
+#define SPI_BRD_CTAR_PBR(base, index) (SPI_RD_CTAR_PBR(base, index))
+
+/*! @brief Set the PBR field to a new value. */
+#define SPI_WR_CTAR_PBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PBR_MASK, SPI_CTAR_PBR(value)))
+#define SPI_BWR_CTAR_PBR(base, index, value) (SPI_WR_CTAR_PBR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PDT[19:18] (RW)
+ *
+ * Selects the prescaler value for the delay between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the
+ * next frame. The PDT field is only used in master mode. See the DT field
+ * description for details on how to compute the Delay after Transfer. Refer Delay after
+ * Transfer (tDT ) for more details.
+ *
+ * Values:
+ * - 0b00 - Delay after Transfer Prescaler value is 1.
+ * - 0b01 - Delay after Transfer Prescaler value is 3.
+ * - 0b10 - Delay after Transfer Prescaler value is 5.
+ * - 0b11 - Delay after Transfer Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PDT field. */
+#define SPI_RD_CTAR_PDT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PDT_MASK) >> SPI_CTAR_PDT_SHIFT)
+#define SPI_BRD_CTAR_PDT(base, index) (SPI_RD_CTAR_PDT(base, index))
+
+/*! @brief Set the PDT field to a new value. */
+#define SPI_WR_CTAR_PDT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PDT_MASK, SPI_CTAR_PDT(value)))
+#define SPI_BWR_CTAR_PDT(base, index, value) (SPI_WR_CTAR_PDT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PASC[21:20] (RW)
+ *
+ * Selects the prescaler value for the delay between the last edge of SCK and
+ * the negation of PCS. See the ASC field description for information on how to
+ * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
+ *
+ * Values:
+ * - 0b00 - Delay after Transfer Prescaler value is 1.
+ * - 0b01 - Delay after Transfer Prescaler value is 3.
+ * - 0b10 - Delay after Transfer Prescaler value is 5.
+ * - 0b11 - Delay after Transfer Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PASC field. */
+#define SPI_RD_CTAR_PASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PASC_MASK) >> SPI_CTAR_PASC_SHIFT)
+#define SPI_BRD_CTAR_PASC(base, index) (SPI_RD_CTAR_PASC(base, index))
+
+/*! @brief Set the PASC field to a new value. */
+#define SPI_WR_CTAR_PASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PASC_MASK, SPI_CTAR_PASC(value)))
+#define SPI_BWR_CTAR_PASC(base, index, value) (SPI_WR_CTAR_PASC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PCSSCK[23:22] (RW)
+ *
+ * Selects the prescaler value for the delay between assertion of PCS and the
+ * first edge of the SCK. See the CSSCK field description for information on how to
+ * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
+ *
+ * Values:
+ * - 0b00 - PCS to SCK Prescaler value is 1.
+ * - 0b01 - PCS to SCK Prescaler value is 3.
+ * - 0b10 - PCS to SCK Prescaler value is 5.
+ * - 0b11 - PCS to SCK Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PCSSCK field. */
+#define SPI_RD_CTAR_PCSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PCSSCK_MASK) >> SPI_CTAR_PCSSCK_SHIFT)
+#define SPI_BRD_CTAR_PCSSCK(base, index) (SPI_RD_CTAR_PCSSCK(base, index))
+
+/*! @brief Set the PCSSCK field to a new value. */
+#define SPI_WR_CTAR_PCSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PCSSCK_MASK, SPI_CTAR_PCSSCK(value)))
+#define SPI_BWR_CTAR_PCSSCK(base, index, value) (SPI_WR_CTAR_PCSSCK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field LSBFE[24] (RW)
+ *
+ * Specifies whether the LSB or MSB of the frame is transferred first.
+ *
+ * Values:
+ * - 0b0 - Data is transferred MSB first.
+ * - 0b1 - Data is transferred LSB first.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_LSBFE field. */
+#define SPI_RD_CTAR_LSBFE(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_LSBFE_MASK) >> SPI_CTAR_LSBFE_SHIFT)
+#define SPI_BRD_CTAR_LSBFE(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT))
+
+/*! @brief Set the LSBFE field to a new value. */
+#define SPI_WR_CTAR_LSBFE(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_LSBFE_MASK, SPI_CTAR_LSBFE(value)))
+#define SPI_BWR_CTAR_LSBFE(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0b0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 0b1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CPHA field. */
+#define SPI_RD_CTAR_CPHA(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPHA_MASK) >> SPI_CTAR_CPHA_SHIFT)
+#define SPI_BRD_CTAR_CPHA(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_CTAR_CPHA(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPHA_MASK, SPI_CTAR_CPHA(value)))
+#define SPI_BWR_CTAR_CPHA(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). This bit
+ * is used in both master and slave mode. For successful communication between
+ * serial devices, the devices must have identical clock polarities. When the
+ * Continuous Selection Format is selected, switching between clock polarities
+ * without stopping the module can cause errors in the transfer due to the peripheral
+ * device interpreting the switch of clock polarity as a valid clock edge. In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0b0 - The inactive state value of SCK is low.
+ * - 0b1 - The inactive state value of SCK is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CPOL field. */
+#define SPI_RD_CTAR_CPOL(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPOL_MASK) >> SPI_CTAR_CPOL_SHIFT)
+#define SPI_BRD_CTAR_CPOL(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_CTAR_CPOL(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPOL_MASK, SPI_CTAR_CPOL(value)))
+#define SPI_BWR_CTAR_CPOL(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field FMSZ[30:27] (RW)
+ *
+ * The number of bits transferred per frame is equal to the FMSZ value plus 1.
+ * Regardless of the transmission mode, the minimum valid frame size value is 4.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_FMSZ field. */
+#define SPI_RD_CTAR_FMSZ(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT)
+#define SPI_BRD_CTAR_FMSZ(base, index) (SPI_RD_CTAR_FMSZ(base, index))
+
+/*! @brief Set the FMSZ field to a new value. */
+#define SPI_WR_CTAR_FMSZ(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_FMSZ_MASK, SPI_CTAR_FMSZ(value)))
+#define SPI_BWR_CTAR_FMSZ(base, index, value) (SPI_WR_CTAR_FMSZ(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field DBR[31] (RW)
+ *
+ * Doubles the effective baud rate of the Serial Communications Clock (SCK).
+ * This field is used only in master mode. It effectively halves the Baud Rate
+ * division ratio, supporting faster frequencies, and odd division ratios for the
+ * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
+ * Serial Communications Clock (SCK) depends on the value in the Baud Rate
+ * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
+ * description for details on how to compute the baud rate. SPI SCK Duty Cycle
+ * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
+ * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
+ *
+ * Values:
+ * - 0b0 - The baud rate is computed normally with a 50/50 duty cycle.
+ * - 0b1 - The baud rate is doubled with the duty cycle depending on the Baud
+ *     Rate Prescaler.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_DBR field. */
+#define SPI_RD_CTAR_DBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DBR_MASK) >> SPI_CTAR_DBR_SHIFT)
+#define SPI_BRD_CTAR_DBR(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT))
+
+/*! @brief Set the DBR field to a new value. */
+#define SPI_WR_CTAR_DBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DBR_MASK, SPI_CTAR_DBR(value)))
+#define SPI_BWR_CTAR_DBR(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_SR - Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_SR - Status Register (RW)
+ *
+ * Reset value: 0x02000000U
+ *
+ * SR contains status and flag bits. The bits reflect the status of the module
+ * and indicate the occurrence of events that can generate interrupt or DMA
+ * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
+ * to a flag bit has no effect. This register may not be writable in Module
+ * Disable mode due to the use of power saving mechanisms.
+ */
+/*!
+ * @name Constants and macros for entire SPI_SR register
+ */
+/*@{*/
+#define SPI_RD_SR(base)          (SPI_SR_REG(base))
+#define SPI_WR_SR(base, value)   (SPI_SR_REG(base) = (value))
+#define SPI_RMW_SR(base, mask, value) (SPI_WR_SR(base, (SPI_RD_SR(base) & ~(mask)) | (value)))
+#define SPI_SET_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) |  (value)))
+#define SPI_CLR_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) & ~(value)))
+#define SPI_TOG_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_SR bitfields
+ */
+
+/*!
+ * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
+ *
+ * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
+ * The POPNXTPTR is updated when the POPR is read.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_POPNXTPTR field. */
+#define SPI_RD_SR_POPNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_POPNXTPTR_MASK) >> SPI_SR_POPNXTPTR_SHIFT)
+#define SPI_BRD_SR_POPNXTPTR(base) (SPI_RD_SR_POPNXTPTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RXCTR[7:4] (RO)
+ *
+ * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
+ * every time the POPR is read. The RXCTR is incremented every time data is
+ * transferred from the shift register to the RX FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RXCTR field. */
+#define SPI_RD_SR_RXCTR(base) ((SPI_SR_REG(base) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT)
+#define SPI_BRD_SR_RXCTR(base) (SPI_RD_SR_RXCTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
+ *
+ * Indicates which TX FIFO entry is transmitted during the next transfer. The
+ * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
+ * the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXNXTPTR field. */
+#define SPI_RD_SR_TXNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_TXNXTPTR_MASK) >> SPI_SR_TXNXTPTR_SHIFT)
+#define SPI_BRD_SR_TXNXTPTR(base) (SPI_RD_SR_TXNXTPTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXCTR[15:12] (RO)
+ *
+ * Indicates the number of valid entries in the TX FIFO. The TXCTR is
+ * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
+ * command is executed and the SPI data is transferred to the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXCTR field. */
+#define SPI_RD_SR_TXCTR(base) ((SPI_SR_REG(base) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT)
+#define SPI_BRD_SR_TXCTR(base) (SPI_RD_SR_TXCTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RFDF[17] (W1C)
+ *
+ * Provides a method for the module to request that entries be removed from the
+ * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller when
+ * the RX FIFO is empty.
+ *
+ * Values:
+ * - 0b0 - RX FIFO is empty.
+ * - 0b1 - RX FIFO is not empty.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RFDF field. */
+#define SPI_RD_SR_RFDF(base) ((SPI_SR_REG(base) & SPI_SR_RFDF_MASK) >> SPI_SR_RFDF_SHIFT)
+#define SPI_BRD_SR_RFDF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT))
+
+/*! @brief Set the RFDF field to a new value. */
+#define SPI_WR_SR_RFDF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFDF(value)))
+#define SPI_BWR_SR_RFDF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RFOF[19] (W1C)
+ *
+ * Indicates an overflow condition in the RX FIFO. The field is set when the RX
+ * FIFO and shift register are full and a transfer is initiated. The bit remains
+ * set until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - No Rx FIFO overflow.
+ * - 0b1 - Rx FIFO overflow has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RFOF field. */
+#define SPI_RD_SR_RFOF(base) ((SPI_SR_REG(base) & SPI_SR_RFOF_MASK) >> SPI_SR_RFOF_SHIFT)
+#define SPI_BRD_SR_RFOF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT))
+
+/*! @brief Set the RFOF field to a new value. */
+#define SPI_WR_SR_RFOF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFOF(value)))
+#define SPI_BWR_SR_RFOF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TFFF[25] (W1C)
+ *
+ * Provides a method for the module to request more entries to be added to the
+ * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller to
+ * the TX FIFO full request.
+ *
+ * Values:
+ * - 0b0 - TX FIFO is full.
+ * - 0b1 - TX FIFO is not full.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TFFF field. */
+#define SPI_RD_SR_TFFF(base) ((SPI_SR_REG(base) & SPI_SR_TFFF_MASK) >> SPI_SR_TFFF_SHIFT)
+#define SPI_BRD_SR_TFFF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT))
+
+/*! @brief Set the TFFF field to a new value. */
+#define SPI_WR_SR_TFFF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFFF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFFF(value)))
+#define SPI_BWR_SR_TFFF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TFUF[27] (W1C)
+ *
+ * Indicates an underflow condition in the TX FIFO. The transmit underflow
+ * condition is detected only for SPI blocks operating in Slave mode and SPI
+ * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
+ * is empty and an external SPI master initiates a transfer. The TFUF bit remains
+ * set until cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No TX FIFO underflow.
+ * - 0b1 - TX FIFO underflow has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TFUF field. */
+#define SPI_RD_SR_TFUF(base) ((SPI_SR_REG(base) & SPI_SR_TFUF_MASK) >> SPI_SR_TFUF_SHIFT)
+#define SPI_BRD_SR_TFUF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT))
+
+/*! @brief Set the TFUF field to a new value. */
+#define SPI_WR_SR_TFUF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFUF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFUF(value)))
+#define SPI_BWR_SR_TFUF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field EOQF[28] (W1C)
+ *
+ * Indicates that the last entry in a queue has been transmitted when the module
+ * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
+ * set in the command halfword and the end of the transfer is reached. The EOQF
+ * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
+ * the TXRXS bit is automatically cleared.
+ *
+ * Values:
+ * - 0b0 - EOQ is not set in the executing command.
+ * - 0b1 - EOQ is set in the executing SPI command.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_EOQF field. */
+#define SPI_RD_SR_EOQF(base) ((SPI_SR_REG(base) & SPI_SR_EOQF_MASK) >> SPI_SR_EOQF_SHIFT)
+#define SPI_BRD_SR_EOQF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT))
+
+/*! @brief Set the EOQF field to a new value. */
+#define SPI_WR_SR_EOQF(base, value) (SPI_RMW_SR(base, (SPI_SR_EOQF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_EOQF(value)))
+#define SPI_BWR_SR_EOQF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXRXS[30] (W1C)
+ *
+ * Reflects the run status of the module.
+ *
+ * Values:
+ * - 0b0 - Transmit and receive operations are disabled (The module is in
+ *     Stopped state).
+ * - 0b1 - Transmit and receive operations are enabled (The module is in Running
+ *     state).
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXRXS field. */
+#define SPI_RD_SR_TXRXS(base) ((SPI_SR_REG(base) & SPI_SR_TXRXS_MASK) >> SPI_SR_TXRXS_SHIFT)
+#define SPI_BRD_SR_TXRXS(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT))
+
+/*! @brief Set the TXRXS field to a new value. */
+#define SPI_WR_SR_TXRXS(base, value) (SPI_RMW_SR(base, (SPI_SR_TXRXS_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TCF_MASK), SPI_SR_TXRXS(value)))
+#define SPI_BWR_SR_TXRXS(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TCF[31] (W1C)
+ *
+ * Indicates that all bits in a frame have been shifted out. TCF remains set
+ * until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - Transfer not complete.
+ * - 0b1 - Transfer complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TCF field. */
+#define SPI_RD_SR_TCF(base)  ((SPI_SR_REG(base) & SPI_SR_TCF_MASK) >> SPI_SR_TCF_SHIFT)
+#define SPI_BRD_SR_TCF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT))
+
+/*! @brief Set the TCF field to a new value. */
+#define SPI_WR_SR_TCF(base, value) (SPI_RMW_SR(base, (SPI_SR_TCF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK), SPI_SR_TCF(value)))
+#define SPI_BWR_SR_TCF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RSER controls DMA and interrupt requests. Do not write to the RSER while the
+ * module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RSER register
+ */
+/*@{*/
+#define SPI_RD_RSER(base)        (SPI_RSER_REG(base))
+#define SPI_WR_RSER(base, value) (SPI_RSER_REG(base) = (value))
+#define SPI_RMW_RSER(base, mask, value) (SPI_WR_RSER(base, (SPI_RD_RSER(base) & ~(mask)) | (value)))
+#define SPI_SET_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) |  (value)))
+#define SPI_CLR_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) & ~(value)))
+#define SPI_TOG_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_RSER bitfields
+ */
+
+/*!
+ * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When the
+ * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
+ * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - Interrupt request.
+ * - 0b1 - DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */
+#define SPI_RD_RSER_RFDF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_DIRS_MASK) >> SPI_RSER_RFDF_DIRS_SHIFT)
+#define SPI_BRD_RSER_RFDF_DIRS(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT))
+
+/*! @brief Set the RFDF_DIRS field to a new value. */
+#define SPI_WR_RSER_RFDF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_DIRS_MASK, SPI_RSER_RFDF_DIRS(value)))
+#define SPI_BWR_RSER_RFDF_DIRS(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field RFDF_RE[17] (RW)
+ *
+ * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - RFDF interrupt or DMA requests are disabled.
+ * - 0b1 - RFDF interrupt or DMA requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFDF_RE field. */
+#define SPI_RD_RSER_RFDF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_RE_MASK) >> SPI_RSER_RFDF_RE_SHIFT)
+#define SPI_BRD_RSER_RFDF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT))
+
+/*! @brief Set the RFDF_RE field to a new value. */
+#define SPI_WR_RSER_RFDF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_RE_MASK, SPI_RSER_RFDF_RE(value)))
+#define SPI_BWR_RSER_RFDF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field RFOF_RE[19] (RW)
+ *
+ * Enables the RFOF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - RFOF interrupt requests are disabled.
+ * - 0b1 - RFOF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFOF_RE field. */
+#define SPI_RD_RSER_RFOF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFOF_RE_MASK) >> SPI_RSER_RFOF_RE_SHIFT)
+#define SPI_BRD_RSER_RFOF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT))
+
+/*! @brief Set the RFOF_RE field to a new value. */
+#define SPI_WR_RSER_RFOF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFOF_RE_MASK, SPI_RSER_RFOF_RE(value)))
+#define SPI_BWR_RSER_RFOF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When
+ * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
+ * interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - TFFF flag generates interrupt requests.
+ * - 0b1 - TFFF flag generates DMA requests.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */
+#define SPI_RD_RSER_TFFF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_DIRS_MASK) >> SPI_RSER_TFFF_DIRS_SHIFT)
+#define SPI_BRD_RSER_TFFF_DIRS(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT))
+
+/*! @brief Set the TFFF_DIRS field to a new value. */
+#define SPI_WR_RSER_TFFF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_DIRS_MASK, SPI_RSER_TFFF_DIRS(value)))
+#define SPI_BWR_RSER_TFFF_DIRS(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFFF_RE[25] (RW)
+ *
+ * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - TFFF interrupts or DMA requests are disabled.
+ * - 0b1 - TFFF interrupts or DMA requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFFF_RE field. */
+#define SPI_RD_RSER_TFFF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_RE_MASK) >> SPI_RSER_TFFF_RE_SHIFT)
+#define SPI_BRD_RSER_TFFF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT))
+
+/*! @brief Set the TFFF_RE field to a new value. */
+#define SPI_WR_RSER_TFFF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_RE_MASK, SPI_RSER_TFFF_RE(value)))
+#define SPI_BWR_RSER_TFFF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFUF_RE[27] (RW)
+ *
+ * Enables the TFUF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - TFUF interrupt requests are disabled.
+ * - 0b1 - TFUF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFUF_RE field. */
+#define SPI_RD_RSER_TFUF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFUF_RE_MASK) >> SPI_RSER_TFUF_RE_SHIFT)
+#define SPI_BRD_RSER_TFUF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT))
+
+/*! @brief Set the TFUF_RE field to a new value. */
+#define SPI_WR_RSER_TFUF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFUF_RE_MASK, SPI_RSER_TFUF_RE(value)))
+#define SPI_BWR_RSER_TFUF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field EOQF_RE[28] (RW)
+ *
+ * Enables the EOQF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - EOQF interrupt requests are disabled.
+ * - 0b1 - EOQF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_EOQF_RE field. */
+#define SPI_RD_RSER_EOQF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_EOQF_RE_MASK) >> SPI_RSER_EOQF_RE_SHIFT)
+#define SPI_BRD_RSER_EOQF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT))
+
+/*! @brief Set the EOQF_RE field to a new value. */
+#define SPI_WR_RSER_EOQF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_EOQF_RE_MASK, SPI_RSER_EOQF_RE(value)))
+#define SPI_BWR_RSER_EOQF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TCF_RE[31] (RW)
+ *
+ * Enables TCF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - TCF interrupt requests are disabled.
+ * - 0b1 - TCF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TCF_RE field. */
+#define SPI_RD_RSER_TCF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TCF_RE_MASK) >> SPI_RSER_TCF_RE_SHIFT)
+#define SPI_BRD_RSER_TCF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT))
+
+/*! @brief Set the TCF_RE field to a new value. */
+#define SPI_WR_RSER_TCF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TCF_RE_MASK, SPI_RSER_TCF_RE(value)))
+#define SPI_BWR_RSER_TCF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
+ * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
+ * can be used as data, supporting up to 32-bit frame operation. A read access
+ * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
+ * writing to this register does not update the FIFO. Therefore, any reads performed
+ * while the module is disabled return the last PUSHR write performed while the
+ * module was still enabled.
+ */
+/*!
+ * @name Constants and macros for entire SPI_PUSHR register
+ */
+/*@{*/
+#define SPI_RD_PUSHR(base)       (SPI_PUSHR_REG(base))
+#define SPI_WR_PUSHR(base, value) (SPI_PUSHR_REG(base) = (value))
+#define SPI_RMW_PUSHR(base, mask, value) (SPI_WR_PUSHR(base, (SPI_RD_PUSHR(base) & ~(mask)) | (value)))
+#define SPI_SET_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) |  (value)))
+#define SPI_CLR_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) & ~(value)))
+#define SPI_TOG_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_PUSHR bitfields
+ */
+
+/*!
+ * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
+ *
+ * Holds SPI data to be transferred according to the associated SPI command.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_TXDATA field. */
+#define SPI_RD_PUSHR_TXDATA(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_TXDATA_MASK) >> SPI_PUSHR_TXDATA_SHIFT)
+#define SPI_BRD_PUSHR_TXDATA(base) (SPI_RD_PUSHR_TXDATA(base))
+
+/*! @brief Set the TXDATA field to a new value. */
+#define SPI_WR_PUSHR_TXDATA(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_TXDATA_MASK, SPI_PUSHR_TXDATA(value)))
+#define SPI_BWR_PUSHR_TXDATA(base, value) (SPI_WR_PUSHR_TXDATA(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field PCS[21:16] (RW)
+ *
+ * Select which PCS signals are to be asserted for the transfer. Refer to the
+ * chip configuration details for the number of PCS signals used in this MCU.
+ *
+ * Values:
+ * - 0b000000 - Negate the PCS[x] signal.
+ * - 0b000001 - Assert the PCS[x] signal.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_PCS field. */
+#define SPI_RD_PUSHR_PCS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_PCS_MASK) >> SPI_PUSHR_PCS_SHIFT)
+#define SPI_BRD_PUSHR_PCS(base) (SPI_RD_PUSHR_PCS(base))
+
+/*! @brief Set the PCS field to a new value. */
+#define SPI_WR_PUSHR_PCS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_PCS_MASK, SPI_PUSHR_PCS(value)))
+#define SPI_BWR_PUSHR_PCS(base, value) (SPI_WR_PUSHR_PCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CTCNT[26] (RW)
+ *
+ * Clears the TCNT field in the TCR register. The TCNT field is cleared before
+ * the module starts transmitting the current SPI frame.
+ *
+ * Values:
+ * - 0b0 - Do not clear the TCR[TCNT] field.
+ * - 0b1 - Clear the TCR[TCNT] field.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CTCNT field. */
+#define SPI_RD_PUSHR_CTCNT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTCNT_MASK) >> SPI_PUSHR_CTCNT_SHIFT)
+#define SPI_BRD_PUSHR_CTCNT(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT))
+
+/*! @brief Set the CTCNT field to a new value. */
+#define SPI_WR_PUSHR_CTCNT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTCNT_MASK, SPI_PUSHR_CTCNT(value)))
+#define SPI_BWR_PUSHR_CTCNT(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field EOQ[27] (RW)
+ *
+ * Host software uses this bit to signal to the module that the current SPI
+ * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
+ * SR is set.
+ *
+ * Values:
+ * - 0b0 - The SPI data is not the last data to transfer.
+ * - 0b1 - The SPI data is the last data to transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_EOQ field. */
+#define SPI_RD_PUSHR_EOQ(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_EOQ_MASK) >> SPI_PUSHR_EOQ_SHIFT)
+#define SPI_BRD_PUSHR_EOQ(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT))
+
+/*! @brief Set the EOQ field to a new value. */
+#define SPI_WR_PUSHR_EOQ(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_EOQ_MASK, SPI_PUSHR_EOQ(value)))
+#define SPI_BWR_PUSHR_EOQ(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
+ *
+ * Selects which CTAR to use in master mode to specify the transfer attributes
+ * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
+ * configuration details to determine how many CTARs this device has. You should
+ * not program a value in this field for a register that is not present.
+ *
+ * Values:
+ * - 0b000 - CTAR0
+ * - 0b001 - CTAR1
+ * - 0b010 - Reserved
+ * - 0b011 - Reserved
+ * - 0b100 - Reserved
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CTAS field. */
+#define SPI_RD_PUSHR_CTAS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTAS_MASK) >> SPI_PUSHR_CTAS_SHIFT)
+#define SPI_BRD_PUSHR_CTAS(base) (SPI_RD_PUSHR_CTAS(base))
+
+/*! @brief Set the CTAS field to a new value. */
+#define SPI_WR_PUSHR_CTAS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTAS_MASK, SPI_PUSHR_CTAS(value)))
+#define SPI_BWR_PUSHR_CTAS(base, value) (SPI_WR_PUSHR_CTAS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CONT[31] (RW)
+ *
+ * Selects a continuous selection format. The bit is used in SPI Master mode.
+ * The bit enables the selected PCS signals to remain asserted between transfers.
+ *
+ * Values:
+ * - 0b0 - Return PCSn signals to their inactive state between transfers.
+ * - 0b1 - Keep PCSn signals asserted between transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CONT field. */
+#define SPI_RD_PUSHR_CONT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CONT_MASK) >> SPI_PUSHR_CONT_SHIFT)
+#define SPI_BRD_PUSHR_CONT(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT))
+
+/*! @brief Set the CONT field to a new value. */
+#define SPI_WR_PUSHR_CONT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CONT_MASK, SPI_PUSHR_CONT(value)))
+#define SPI_BWR_PUSHR_CONT(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
+ * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
+ * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
+ * SPI Frame operation.
+ */
+/*!
+ * @name Constants and macros for entire SPI_PUSHR_SLAVE register
+ */
+/*@{*/
+#define SPI_RD_PUSHR_SLAVE(base) (SPI_PUSHR_SLAVE_REG(base))
+#define SPI_WR_PUSHR_SLAVE(base, value) (SPI_PUSHR_SLAVE_REG(base) = (value))
+#define SPI_RMW_PUSHR_SLAVE(base, mask, value) (SPI_WR_PUSHR_SLAVE(base, (SPI_RD_PUSHR_SLAVE(base) & ~(mask)) | (value)))
+#define SPI_SET_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) |  (value)))
+#define SPI_CLR_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) & ~(value)))
+#define SPI_TOG_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_POPR - POP RX FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_POPR - POP RX FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
+ * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
+ * this register will generate a Transfer Error.
+ */
+/*!
+ * @name Constants and macros for entire SPI_POPR register
+ */
+/*@{*/
+#define SPI_RD_POPR(base)        (SPI_POPR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR0 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR0 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR0 register
+ */
+/*@{*/
+#define SPI_RD_TXFR0(base)       (SPI_TXFR0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR0 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR0, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR0_TXDATA field. */
+#define SPI_RD_TXFR0_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXDATA_MASK) >> SPI_TXFR0_TXDATA_SHIFT)
+#define SPI_BRD_TXFR0_TXDATA(base) (SPI_RD_TXFR0_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR0, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR0_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR0_TXCMD_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXCMD_TXDATA_MASK) >> SPI_TXFR0_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR0_TXCMD_TXDATA(base) (SPI_RD_TXFR0_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR1 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR1 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR1 register
+ */
+/*@{*/
+#define SPI_RD_TXFR1(base)       (SPI_TXFR1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR1 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR1, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR1_TXDATA field. */
+#define SPI_RD_TXFR1_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXDATA_MASK) >> SPI_TXFR1_TXDATA_SHIFT)
+#define SPI_BRD_TXFR1_TXDATA(base) (SPI_RD_TXFR1_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR1, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR1_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR1_TXCMD_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXCMD_TXDATA_MASK) >> SPI_TXFR1_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR1_TXCMD_TXDATA(base) (SPI_RD_TXFR1_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR2 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR2 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR2 register
+ */
+/*@{*/
+#define SPI_RD_TXFR2(base)       (SPI_TXFR2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR2 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR2, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR2_TXDATA field. */
+#define SPI_RD_TXFR2_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXDATA_MASK) >> SPI_TXFR2_TXDATA_SHIFT)
+#define SPI_BRD_TXFR2_TXDATA(base) (SPI_RD_TXFR2_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR2, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR2_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR2_TXCMD_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXCMD_TXDATA_MASK) >> SPI_TXFR2_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR2_TXCMD_TXDATA(base) (SPI_RD_TXFR2_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR3 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR3 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR3 register
+ */
+/*@{*/
+#define SPI_RD_TXFR3(base)       (SPI_TXFR3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR3 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR3, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR3_TXDATA field. */
+#define SPI_RD_TXFR3_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXDATA_MASK) >> SPI_TXFR3_TXDATA_SHIFT)
+#define SPI_BRD_TXFR3_TXDATA(base) (SPI_RD_TXFR3_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR3, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR3_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR3_TXCMD_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXCMD_TXDATA_MASK) >> SPI_TXFR3_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR3_TXCMD_TXDATA(base) (SPI_RD_TXFR3_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR0 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR0 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR0 register
+ */
+/*@{*/
+#define SPI_RD_RXFR0(base)       (SPI_RXFR0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR1 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR1 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR1 register
+ */
+/*@{*/
+#define SPI_RD_RXFR1(base)       (SPI_RXFR1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR2 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR2 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR2 register
+ */
+/*@{*/
+#define SPI_RD_RXFR2(base)       (SPI_RXFR2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR3 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR3 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR3 register
+ */
+/*@{*/
+#define SPI_RD_RXFR3(base)       (SPI_RXFR3_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 UART
+ *
+ * Serial Communication Interface
+ *
+ * Registers defined in this header file:
+ * - UART_BDH - UART Baud Rate Registers: High
+ * - UART_BDL - UART Baud Rate Registers: Low
+ * - UART_C1 - UART Control Register 1
+ * - UART_C2 - UART Control Register 2
+ * - UART_S1 - UART Status Register 1
+ * - UART_S2 - UART Status Register 2
+ * - UART_C3 - UART Control Register 3
+ * - UART_D - UART Data Register
+ * - UART_MA1 - UART Match Address Registers 1
+ * - UART_MA2 - UART Match Address Registers 2
+ * - UART_C4 - UART Control Register 4
+ * - UART_C5 - UART Control Register 5
+ * - UART_ED - UART Extended Data Register
+ * - UART_MODEM - UART Modem Register
+ * - UART_IR - UART Infrared Register
+ * - UART_PFIFO - UART FIFO Parameters
+ * - UART_CFIFO - UART FIFO Control Register
+ * - UART_SFIFO - UART FIFO Status Register
+ * - UART_TWFIFO - UART FIFO Transmit Watermark
+ * - UART_TCFIFO - UART FIFO Transmit Count
+ * - UART_RWFIFO - UART FIFO Receive Watermark
+ * - UART_RCFIFO - UART FIFO Receive Count
+ * - UART_C7816 - UART 7816 Control Register
+ * - UART_IE7816 - UART 7816 Interrupt Enable Register
+ * - UART_IS7816 - UART 7816 Interrupt Status Register
+ * - UART_WP7816T0 - UART 7816 Wait Parameter Register
+ * - UART_WP7816T1 - UART 7816 Wait Parameter Register
+ * - UART_WN7816 - UART 7816 Wait N Register
+ * - UART_WF7816 - UART 7816 Wait FD Register
+ * - UART_ET7816 - UART 7816 Error Threshold Register
+ * - UART_TL7816 - UART 7816 Transmit Length Register
+ */
+
+#define UART_INSTANCE_COUNT (6U) /*!< Number of instances of the UART module. */
+#define UART0_IDX (0U) /*!< Instance number for UART0. */
+#define UART1_IDX (1U) /*!< Instance number for UART1. */
+#define UART2_IDX (2U) /*!< Instance number for UART2. */
+#define UART3_IDX (3U) /*!< Instance number for UART3. */
+#define UART4_IDX (4U) /*!< Instance number for UART4. */
+#define UART5_IDX (5U) /*!< Instance number for UART5. */
+
+/*******************************************************************************
+ * UART_BDH - UART Baud Rate Registers: High
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDH - UART Baud Rate Registers: High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register, along with the BDL register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting
+ * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
+ * to BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is,
+ * when C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDH register
+ */
+/*@{*/
+#define UART_RD_BDH(base)        (UART_BDH_REG(base))
+#define UART_WR_BDH(base, value) (UART_BDH_REG(base) = (value))
+#define UART_RMW_BDH(base, mask, value) (UART_WR_BDH(base, (UART_RD_BDH(base) & ~(mask)) | (value)))
+#define UART_SET_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) |  (value)))
+#define UART_CLR_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) & ~(value)))
+#define UART_TOG_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_BDH bitfields
+ */
+
+/*!
+ * @name Register UART_BDH, field SBR[4:0] (RW)
+ *
+ * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
+ * generation for details. The baud rate generator is disabled until C2[TE] or
+ * C2[RE] is set for the first time after reset.The baud rate generator is disabled
+ * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
+ * writing to BDH puts the data in a temporary location until BDL is written.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBR field. */
+#define UART_RD_BDH_SBR(base) ((UART_BDH_REG(base) & UART_BDH_SBR_MASK) >> UART_BDH_SBR_SHIFT)
+#define UART_BRD_BDH_SBR(base) (UART_RD_BDH_SBR(base))
+
+/*! @brief Set the SBR field to a new value. */
+#define UART_WR_BDH_SBR(base, value) (UART_RMW_BDH(base, UART_BDH_SBR_MASK, UART_BDH_SBR(value)))
+#define UART_BWR_BDH_SBR(base, value) (UART_WR_BDH_SBR(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field SBNS[5] (RW)
+ *
+ * SBNS selects the number of stop bits present in a data frame. This field
+ * valid for all 8, 9 and 10 bit data formats available. This field is not valid when
+ * C7816[ISO7816E] is enabled.
+ *
+ * Values:
+ * - 0b0 - Data frame consists of a single stop bit.
+ * - 0b1 - Data frame consists of two stop bits.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBNS field. */
+#define UART_RD_BDH_SBNS(base) ((UART_BDH_REG(base) & UART_BDH_SBNS_MASK) >> UART_BDH_SBNS_SHIFT)
+#define UART_BRD_BDH_SBNS(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_SBNS_SHIFT))
+
+/*! @brief Set the SBNS field to a new value. */
+#define UART_WR_BDH_SBNS(base, value) (UART_RMW_BDH(base, UART_BDH_SBNS_MASK, UART_BDH_SBNS(value)))
+#define UART_BWR_BDH_SBNS(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_SBNS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field RXEDGIE[6] (RW)
+ *
+ * Enables the receive input active edge, RXEDGIF, to generate interrupt
+ * requests.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupts from RXEDGIF disabled using polling.
+ * - 0b1 - RXEDGIF interrupt request enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_RXEDGIE field. */
+#define UART_RD_BDH_RXEDGIE(base) ((UART_BDH_REG(base) & UART_BDH_RXEDGIE_MASK) >> UART_BDH_RXEDGIE_SHIFT)
+#define UART_BRD_BDH_RXEDGIE(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT))
+
+/*! @brief Set the RXEDGIE field to a new value. */
+#define UART_WR_BDH_RXEDGIE(base, value) (UART_RMW_BDH(base, UART_BDH_RXEDGIE_MASK, UART_BDH_RXEDGIE(value)))
+#define UART_BWR_BDH_RXEDGIE(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field LBKDIE[7] (RW)
+ *
+ * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
+ * based on the state of LBKDDMAS. or DMA transfer requests,
+ *
+ * Values:
+ * - 0b0 - LBKDIF interrupt and DMA transfer requests disabled.
+ * - 0b1 - LBKDIF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_LBKDIE field. */
+#define UART_RD_BDH_LBKDIE(base) ((UART_BDH_REG(base) & UART_BDH_LBKDIE_MASK) >> UART_BDH_LBKDIE_SHIFT)
+#define UART_BRD_BDH_LBKDIE(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_LBKDIE_SHIFT))
+
+/*! @brief Set the LBKDIE field to a new value. */
+#define UART_WR_BDH_LBKDIE(base, value) (UART_RMW_BDH(base, UART_BDH_LBKDIE_MASK, UART_BDH_LBKDIE(value)))
+#define UART_BWR_BDH_LBKDIE(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_LBKDIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_BDL - UART Baud Rate Registers: Low
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDL - UART Baud Rate Registers: Low (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * This register, along with the BDH register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
+ * first write to BDH to buffer the high half of the new value and then write to
+ * BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is, when
+ * C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDL register
+ */
+/*@{*/
+#define UART_RD_BDL(base)        (UART_BDL_REG(base))
+#define UART_WR_BDL(base, value) (UART_BDL_REG(base) = (value))
+#define UART_RMW_BDL(base, mask, value) (UART_WR_BDL(base, (UART_RD_BDL(base) & ~(mask)) | (value)))
+#define UART_SET_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) |  (value)))
+#define UART_CLR_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) & ~(value)))
+#define UART_TOG_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C1 - UART Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C1 - UART Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This read/write register controls various optional features of the UART
+ * system.
+ */
+/*!
+ * @name Constants and macros for entire UART_C1 register
+ */
+/*@{*/
+#define UART_RD_C1(base)         (UART_C1_REG(base))
+#define UART_WR_C1(base, value)  (UART_C1_REG(base) = (value))
+#define UART_RMW_C1(base, mask, value) (UART_WR_C1(base, (UART_RD_C1(base) & ~(mask)) | (value)))
+#define UART_SET_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) |  (value)))
+#define UART_CLR_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) & ~(value)))
+#define UART_TOG_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C1 bitfields
+ */
+
+/*!
+ * @name Register UART_C1, field PT[0] (RW)
+ *
+ * Determines whether the UART generates and checks for even parity or odd
+ * parity. With even parity, an even number of 1s clears the parity bit and an odd
+ * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
+ * parity bit and an even number of 1s sets the parity bit. This field must be
+ * cleared when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Even parity.
+ * - 0b1 - Odd parity.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PT field. */
+#define UART_RD_C1_PT(base)  ((UART_C1_REG(base) & UART_C1_PT_MASK) >> UART_C1_PT_SHIFT)
+#define UART_BRD_C1_PT(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PT_SHIFT))
+
+/*! @brief Set the PT field to a new value. */
+#define UART_WR_C1_PT(base, value) (UART_RMW_C1(base, UART_C1_PT_MASK, UART_C1_PT(value)))
+#define UART_BWR_C1_PT(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field PE[1] (RW)
+ *
+ * Enables the parity function. When parity is enabled, parity function inserts
+ * a parity bit in the bit position immediately preceding the stop bit. This
+ * field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Parity function disabled.
+ * - 0b1 - Parity function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PE field. */
+#define UART_RD_C1_PE(base)  ((UART_C1_REG(base) & UART_C1_PE_MASK) >> UART_C1_PE_SHIFT)
+#define UART_BRD_C1_PE(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PE_SHIFT))
+
+/*! @brief Set the PE field to a new value. */
+#define UART_WR_C1_PE(base, value) (UART_RMW_C1(base, UART_C1_PE_MASK, UART_C1_PE(value)))
+#define UART_BWR_C1_PE(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field ILT[2] (RW)
+ *
+ * Determines when the receiver starts counting logic 1s as idle character bits.
+ * The count begins either after a valid start bit or after the stop bit. If the
+ * count begins after the start bit, then a string of logic 1s preceding the
+ * stop bit can cause false recognition of an idle character. Beginning the count
+ * after the stop bit avoids false idle character recognition, but requires
+ * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
+ * logic of 1'b0 is automatically shifted after a received stop bit, therefore
+ * resetting the idle count. In case the UART is programmed for IDLE line wakeup
+ * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
+ * logic 1s as idle character bits. In idle line wakeup, an idle character is
+ * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
+ * and C4[M10] fields.
+ *
+ * Values:
+ * - 0b0 - Idle character bit count starts after start bit.
+ * - 0b1 - Idle character bit count starts after stop bit.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_ILT field. */
+#define UART_RD_C1_ILT(base) ((UART_C1_REG(base) & UART_C1_ILT_MASK) >> UART_C1_ILT_SHIFT)
+#define UART_BRD_C1_ILT(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_ILT_SHIFT))
+
+/*! @brief Set the ILT field to a new value. */
+#define UART_WR_C1_ILT(base, value) (UART_RMW_C1(base, UART_C1_ILT_MASK, UART_C1_ILT(value)))
+#define UART_BWR_C1_ILT(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_ILT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field WAKE[3] (RW)
+ *
+ * Determines which condition wakes the UART: Address mark in the most
+ * significant bit position of a received data character, or An idle condition on the
+ * receive pin input signal.
+ *
+ * Values:
+ * - 0b0 - Idle line wakeup.
+ * - 0b1 - Address mark wakeup.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_WAKE field. */
+#define UART_RD_C1_WAKE(base) ((UART_C1_REG(base) & UART_C1_WAKE_MASK) >> UART_C1_WAKE_SHIFT)
+#define UART_BRD_C1_WAKE(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT))
+
+/*! @brief Set the WAKE field to a new value. */
+#define UART_WR_C1_WAKE(base, value) (UART_RMW_C1(base, UART_C1_WAKE_MASK, UART_C1_WAKE(value)))
+#define UART_BWR_C1_WAKE(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field M[4] (RW)
+ *
+ * This field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) +
+ *     stop.
+ * - 0b1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_M field. */
+#define UART_RD_C1_M(base)   ((UART_C1_REG(base) & UART_C1_M_MASK) >> UART_C1_M_SHIFT)
+#define UART_BRD_C1_M(base)  (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_M_SHIFT))
+
+/*! @brief Set the M field to a new value. */
+#define UART_WR_C1_M(base, value) (UART_RMW_C1(base, UART_C1_M_MASK, UART_C1_M(value)))
+#define UART_BWR_C1_M(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_M_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field RSRC[5] (RW)
+ *
+ * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
+ * is set, the RSRC field determines the source for the receiver shift register
+ * input.
+ *
+ * Values:
+ * - 0b0 - Selects internal loop back mode. The receiver input is internally
+ *     connected to transmitter output.
+ * - 0b1 - Single wire UART mode where the receiver input is connected to the
+ *     transmit pin input signal.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_RSRC field. */
+#define UART_RD_C1_RSRC(base) ((UART_C1_REG(base) & UART_C1_RSRC_MASK) >> UART_C1_RSRC_SHIFT)
+#define UART_BRD_C1_RSRC(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT))
+
+/*! @brief Set the RSRC field to a new value. */
+#define UART_WR_C1_RSRC(base, value) (UART_RMW_C1(base, UART_C1_RSRC_MASK, UART_C1_RSRC(value)))
+#define UART_BWR_C1_RSRC(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field UARTSWAI[6] (RW)
+ *
+ * Values:
+ * - 0b0 - UART clock continues to run in Wait mode.
+ * - 0b1 - UART clock freezes while CPU is in Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_UARTSWAI field. */
+#define UART_RD_C1_UARTSWAI(base) ((UART_C1_REG(base) & UART_C1_UARTSWAI_MASK) >> UART_C1_UARTSWAI_SHIFT)
+#define UART_BRD_C1_UARTSWAI(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_UARTSWAI_SHIFT))
+
+/*! @brief Set the UARTSWAI field to a new value. */
+#define UART_WR_C1_UARTSWAI(base, value) (UART_RMW_C1(base, UART_C1_UARTSWAI_MASK, UART_C1_UARTSWAI(value)))
+#define UART_BWR_C1_UARTSWAI(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_UARTSWAI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field LOOPS[7] (RW)
+ *
+ * When LOOPS is set, the RxD pin is disconnected from the UART and the
+ * transmitter output is internally connected to the receiver input. The transmitter and
+ * the receiver must be enabled to use the loop function.
+ *
+ * Values:
+ * - 0b0 - Normal operation.
+ * - 0b1 - Loop mode where transmitter output is internally connected to
+ *     receiver input. The receiver input is determined by RSRC.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_LOOPS field. */
+#define UART_RD_C1_LOOPS(base) ((UART_C1_REG(base) & UART_C1_LOOPS_MASK) >> UART_C1_LOOPS_SHIFT)
+#define UART_BRD_C1_LOOPS(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT))
+
+/*! @brief Set the LOOPS field to a new value. */
+#define UART_WR_C1_LOOPS(base, value) (UART_RMW_C1(base, UART_C1_LOOPS_MASK, UART_C1_LOOPS(value)))
+#define UART_BWR_C1_LOOPS(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C2 - UART Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C2 - UART Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register can be read or written at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_C2 register
+ */
+/*@{*/
+#define UART_RD_C2(base)         (UART_C2_REG(base))
+#define UART_WR_C2(base, value)  (UART_C2_REG(base) = (value))
+#define UART_RMW_C2(base, mask, value) (UART_WR_C2(base, (UART_RD_C2(base) & ~(mask)) | (value)))
+#define UART_SET_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) |  (value)))
+#define UART_CLR_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) & ~(value)))
+#define UART_TOG_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C2 bitfields
+ */
+
+/*!
+ * @name Register UART_C2, field SBK[0] (RW)
+ *
+ * Toggling SBK sends one break character from the following: See Transmitting
+ * break characters for the number of logic 0s for the different configurations.
+ * Toggling implies clearing the SBK field before the break character has finished
+ * transmitting. As long as SBK is set, the transmitter continues to send
+ * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
+ * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
+ * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
+ * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
+ * C7816[ISO_7816E] is set.
+ *
+ * Values:
+ * - 0b0 - Normal transmitter operation.
+ * - 0b1 - Queue break characters to be sent.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_SBK field. */
+#define UART_RD_C2_SBK(base) ((UART_C2_REG(base) & UART_C2_SBK_MASK) >> UART_C2_SBK_SHIFT)
+#define UART_BRD_C2_SBK(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_SBK_SHIFT))
+
+/*! @brief Set the SBK field to a new value. */
+#define UART_WR_C2_SBK(base, value) (UART_RMW_C2(base, UART_C2_SBK_MASK, UART_C2_SBK(value)))
+#define UART_BWR_C2_SBK(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_SBK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RWU[1] (RW)
+ *
+ * This field can be set to place the UART receiver in a standby state. RWU
+ * automatically clears when an RWU event occurs, that is, an IDLE event when
+ * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
+ * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
+ * on idle) if the channel is currently not idle. This can be determined by
+ * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
+ * idle, it is possible that the UART will discard data. This is because the data
+ * must be received or a LIN break detected after an IDLE is detected before IDLE
+ * is allowed to reasserted.
+ *
+ * Values:
+ * - 0b0 - Normal operation.
+ * - 0b1 - RWU enables the wakeup function and inhibits further receiver
+ *     interrupt requests. Normally, hardware wakes the receiver by automatically
+ *     clearing RWU.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RWU field. */
+#define UART_RD_C2_RWU(base) ((UART_C2_REG(base) & UART_C2_RWU_MASK) >> UART_C2_RWU_SHIFT)
+#define UART_BRD_C2_RWU(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RWU_SHIFT))
+
+/*! @brief Set the RWU field to a new value. */
+#define UART_WR_C2_RWU(base, value) (UART_RMW_C2(base, UART_C2_RWU_MASK, UART_C2_RWU(value)))
+#define UART_BWR_C2_RWU(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RWU_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RE[2] (RW)
+ *
+ * Enables the UART receiver.
+ *
+ * Values:
+ * - 0b0 - Receiver off.
+ * - 0b1 - Receiver on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RE field. */
+#define UART_RD_C2_RE(base)  ((UART_C2_REG(base) & UART_C2_RE_MASK) >> UART_C2_RE_SHIFT)
+#define UART_BRD_C2_RE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RE_SHIFT))
+
+/*! @brief Set the RE field to a new value. */
+#define UART_WR_C2_RE(base, value) (UART_RMW_C2(base, UART_C2_RE_MASK, UART_C2_RE(value)))
+#define UART_BWR_C2_RE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TE[3] (RW)
+ *
+ * Enables the UART transmitter. TE can be used to queue an idle preamble by
+ * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
+ * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
+ * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
+ * additional characters are transmitted.
+ *
+ * Values:
+ * - 0b0 - Transmitter off.
+ * - 0b1 - Transmitter on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TE field. */
+#define UART_RD_C2_TE(base)  ((UART_C2_REG(base) & UART_C2_TE_MASK) >> UART_C2_TE_SHIFT)
+#define UART_BRD_C2_TE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TE_SHIFT))
+
+/*! @brief Set the TE field to a new value. */
+#define UART_WR_C2_TE(base, value) (UART_RMW_C2(base, UART_C2_TE_MASK, UART_C2_TE(value)))
+#define UART_BWR_C2_TE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field ILIE[4] (RW)
+ *
+ * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
+ * transfer requests based on the state of C5[ILDMAS].
+ *
+ * Values:
+ * - 0b0 - IDLE interrupt requests disabled. and DMA transfer
+ * - 0b1 - IDLE interrupt requests enabled. or DMA transfer
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_ILIE field. */
+#define UART_RD_C2_ILIE(base) ((UART_C2_REG(base) & UART_C2_ILIE_MASK) >> UART_C2_ILIE_SHIFT)
+#define UART_BRD_C2_ILIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT))
+
+/*! @brief Set the ILIE field to a new value. */
+#define UART_WR_C2_ILIE(base, value) (UART_RMW_C2(base, UART_C2_ILIE_MASK, UART_C2_ILIE(value)))
+#define UART_BWR_C2_ILIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RIE[5] (RW)
+ *
+ * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[RDMAS].
+ *
+ * Values:
+ * - 0b0 - RDRF interrupt and DMA transfer requests disabled.
+ * - 0b1 - RDRF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RIE field. */
+#define UART_RD_C2_RIE(base) ((UART_C2_REG(base) & UART_C2_RIE_MASK) >> UART_C2_RIE_SHIFT)
+#define UART_BRD_C2_RIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RIE_SHIFT))
+
+/*! @brief Set the RIE field to a new value. */
+#define UART_WR_C2_RIE(base, value) (UART_RMW_C2(base, UART_C2_RIE_MASK, UART_C2_RIE(value)))
+#define UART_BWR_C2_RIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TCIE[6] (RW)
+ *
+ * Enables the transmission complete flag, S1[TC], to generate interrupt
+ * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
+ * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
+ * written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0b0 - TC interrupt and DMA transfer requests disabled.
+ * - 0b1 - TC interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TCIE field. */
+#define UART_RD_C2_TCIE(base) ((UART_C2_REG(base) & UART_C2_TCIE_MASK) >> UART_C2_TCIE_SHIFT)
+#define UART_BRD_C2_TCIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT))
+
+/*! @brief Set the TCIE field to a new value. */
+#define UART_WR_C2_TCIE(base, value) (UART_RMW_C2(base, UART_C2_TCIE_MASK, UART_C2_TCIE(value)))
+#define UART_BWR_C2_TCIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TIE[7] (RW)
+ *
+ * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
+ * must be cleared, and D[D] must not be written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0b0 - TDRE interrupt and DMA transfer requests disabled.
+ * - 0b1 - TDRE interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TIE field. */
+#define UART_RD_C2_TIE(base) ((UART_C2_REG(base) & UART_C2_TIE_MASK) >> UART_C2_TIE_SHIFT)
+#define UART_BRD_C2_TIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define UART_WR_C2_TIE(base, value) (UART_RMW_C2(base, UART_C2_TIE_MASK, UART_C2_TIE(value)))
+#define UART_BWR_C2_TIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S1 - UART Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S1 - UART Status Register 1 (RO)
+ *
+ * Reset value: 0xC0U
+ *
+ * The S1 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. This register can also be polled by the MCU to check the
+ * status of its fields. To clear a flag, the status register should be read followed
+ * by a read or write to D register, depending on the interrupt flag type. Other
+ * instructions can be executed between the two steps as long the handling of
+ * I/O is not compromised, but the order of operations is important for flag
+ * clearing. When a flag is configured to trigger a DMA request, assertion of the
+ * associated DMA done signal from the DMA controller clears the flag. If the
+ * condition that results in the assertion of the flag, interrupt, or DMA request is not
+ * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
+ * reasserts. For example, if the DMA or interrupt service routine fails to write
+ * sufficient data to the transmit buffer to raise it above the watermark level, the
+ * flag reasserts and generates another interrupt or DMA request. Reading an
+ * empty data register to clear one of the flags of the S1 register causes the FIFO
+ * pointers to become misaligned. A receive FIFO flush reinitializes the
+ * pointers. A better way to prevent this situation is to always leave one byte in FIFO
+ * and this byte will be read eventually in clearing the flag bit.
+ */
+/*!
+ * @name Constants and macros for entire UART_S1 register
+ */
+/*@{*/
+#define UART_RD_S1(base)         (UART_S1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S1 bitfields
+ */
+
+/*!
+ * @name Register UART_S1, field PF[0] (RO)
+ *
+ * PF is set when PE is set and the parity of the received data does not match
+ * its parity bit. The PF is not set in the case of an overrun condition. When PF
+ * is set, it indicates only that a dataword was received with parity error since
+ * the last time it was cleared. There is no guarantee that the first dataword
+ * read from the receive buffer has a parity error or that there is only one
+ * dataword in the buffer that was received with a parity error, unless the receive
+ * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
+ * disabled, Within the receive buffer structure the received dataword is tagged
+ * if it is received with a parity error. This information is available by reading
+ * the ED register prior to reading the D register.
+ *
+ * Values:
+ * - 0b0 - No parity error detected since the last time this flag was cleared.
+ *     If the receive buffer has a depth greater than 1, then there may be data in
+ *     the receive buffer what was received with a parity error.
+ * - 0b1 - At least one dataword was received with a parity error since the last
+ *     time this flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_PF field. */
+#define UART_RD_S1_PF(base)  ((UART_S1_REG(base) & UART_S1_PF_MASK) >> UART_S1_PF_SHIFT)
+#define UART_BRD_S1_PF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_PF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field FE[1] (RO)
+ *
+ * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
+ * then FE will set when a logic 0 is accepted for either of the two stop bits.
+ * FE does not set in the case of an overrun or while the LIN break detect feature
+ * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
+ * cleared. To clear FE, read S1 with FE set and then read D. The last data in the
+ * receive buffer represents the data that was received with the frame error
+ * enabled. Framing errors are not supported when 7816E is set/enabled. However, if
+ * this flag is set, data is still not received in 7816 mode.
+ *
+ * Values:
+ * - 0b0 - No framing error detected.
+ * - 0b1 - Framing error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_FE field. */
+#define UART_RD_S1_FE(base)  ((UART_S1_REG(base) & UART_S1_FE_MASK) >> UART_S1_FE_SHIFT)
+#define UART_BRD_S1_FE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_FE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field NF[2] (RO)
+ *
+ * NF is set when the UART detects noise on the receiver input. NF does not
+ * become set in the case of an overrun or while the LIN break detect feature is
+ * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
+ * been received with noise since the last time it was cleared. There is no
+ * guarantee that the first dataword read from the receive buffer has noise or that there
+ * is only one dataword in the buffer that was received with noise unless the
+ * receive buffer has a depth of one. To clear NF, read S1 and then read D.
+ *
+ * Values:
+ * - 0b0 - No noise detected since the last time this flag was cleared. If the
+ *     receive buffer has a depth greater than 1 then there may be data in the
+ *     receiver buffer that was received with noise.
+ * - 0b1 - At least one dataword was received with noise detected since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_NF field. */
+#define UART_RD_S1_NF(base)  ((UART_S1_REG(base) & UART_S1_NF_MASK) >> UART_S1_NF_SHIFT)
+#define UART_BRD_S1_NF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_NF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field OR[3] (RO)
+ *
+ * OR is set when software fails to prevent the receive data register from
+ * overflowing with data. The OR bit is set immediately after the stop bit has been
+ * completely received for the dataword that overflows the buffer and all the other
+ * error flags (FE, NF, and PF) are prevented from setting. The data in the
+ * shift register is lost, but the data already in the UART data registers is not
+ * affected. If the OR flag is set, no data is stored in the data buffer even if
+ * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
+ * flags are blocked from asserting, that is, transition from an inactive to an
+ * active state. To clear OR, read S1 when OR is set and then read D. See
+ * functional description for more details regarding the operation of the OR bit.If
+ * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
+ * is not cleared before the next data character is received. In 7816 mode, it is
+ * possible to configure a NACK to be returned by programing C7816[ONACK].
+ *
+ * Values:
+ * - 0b0 - No overrun has occurred since the last time the flag was cleared.
+ * - 0b1 - Overrun has occurred or the overrun flag has not been cleared since
+ *     the last overrun occured.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_OR field. */
+#define UART_RD_S1_OR(base)  ((UART_S1_REG(base) & UART_S1_OR_MASK) >> UART_S1_OR_SHIFT)
+#define UART_BRD_S1_OR(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_OR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field IDLE[4] (RO)
+ *
+ * After the IDLE flag is cleared, a frame must be received (although not
+ * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
+ * break character must set the S2[LBKDIF] flag before an idle condition can set the
+ * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
+ * IDLE is set when either of the following appear on the receiver input: 10
+ * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
+ * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
+ * detection is not supported when 7816E is set/enabled and hence this flag is
+ * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
+ * flag if RWUID is set, else the IDLE flag does not become set.
+ *
+ * Values:
+ * - 0b0 - Receiver input is either active now or has never become active since
+ *     the IDLE flag was last cleared.
+ * - 0b1 - Receiver input has become idle or the flag has not been cleared since
+ *     it last asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_IDLE field. */
+#define UART_RD_S1_IDLE(base) ((UART_S1_REG(base) & UART_S1_IDLE_MASK) >> UART_S1_IDLE_SHIFT)
+#define UART_BRD_S1_IDLE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field RDRF[5] (RO)
+ *
+ * RDRF is set when the number of datawords in the receive buffer is equal to or
+ * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
+ * process of being received is not included in the count. To clear RDRF, read S1
+ * when RDRF is set and then read D. For more efficient interrupt and DMA
+ * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
+ * Then read S1 and the final data value, resulting in the clearing of the RDRF
+ * flag. Even if RDRF is set, data will continue to be received until an overrun
+ * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
+ * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
+ * buffer but over-write each other.
+ *
+ * Values:
+ * - 0b0 - The number of datawords in the receive buffer is less than the number
+ *     indicated by RXWATER.
+ * - 0b1 - The number of datawords in the receive buffer is equal to or greater
+ *     than the number indicated by RXWATER at some point in time since this flag
+ *     was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_RDRF field. */
+#define UART_RD_S1_RDRF(base) ((UART_S1_REG(base) & UART_S1_RDRF_MASK) >> UART_S1_RDRF_SHIFT)
+#define UART_BRD_S1_RDRF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_RDRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TC[6] (RO)
+ *
+ * TC is set when the transmit buffer is empty and no data, preamble, or break
+ * character is being transmitted. When TC is set, the transmit data output signal
+ * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
+ * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
+ * set after any NACK signal has been received, but prior to any corresponding
+ * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
+ * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
+ * in C2.
+ *
+ * Values:
+ * - 0b0 - Transmitter active (sending data, a preamble, or a break).
+ * - 0b1 - Transmitter idle (transmission activity complete).
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TC field. */
+#define UART_RD_S1_TC(base)  ((UART_S1_REG(base) & UART_S1_TC_MASK) >> UART_S1_TC_SHIFT)
+#define UART_BRD_S1_TC(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_TC_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TDRE[7] (RO)
+ *
+ * TDRE will set when the number of datawords in the transmit buffer (D and
+ * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
+ * character that is in the process of being transmitted is not included in the count.
+ * To clear TDRE, read S1 when TDRE is set and then write to the UART data
+ * register (D). For more efficient interrupt servicing, all data except the final value
+ * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
+ * before writing the final data value, resulting in the clearing of the TRDE
+ * flag. This is more efficient because the TDRE reasserts until the watermark has
+ * been exceeded. So, attempting to clear the TDRE with every write will be
+ * ineffective until sufficient data has been written.
+ *
+ * Values:
+ * - 0b0 - The amount of data in the transmit buffer is greater than the value
+ *     indicated by TWFIFO[TXWATER].
+ * - 0b1 - The amount of data in the transmit buffer is less than or equal to
+ *     the value indicated by TWFIFO[TXWATER] at some point in time since the flag
+ *     has been cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TDRE field. */
+#define UART_RD_S1_TDRE(base) ((UART_S1_REG(base) & UART_S1_TDRE_MASK) >> UART_S1_TDRE_SHIFT)
+#define UART_BRD_S1_TDRE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_TDRE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S2 - UART Status Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S2 - UART Status Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The S2 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. Also, this register can be polled by the MCU to check the
+ * status of these bits. This register can be read or written at any time, with the
+ * exception of the MSBF and RXINV bits, which should be changed by the user only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_S2 register
+ */
+/*@{*/
+#define UART_RD_S2(base)         (UART_S2_REG(base))
+#define UART_WR_S2(base, value)  (UART_S2_REG(base) = (value))
+#define UART_RMW_S2(base, mask, value) (UART_WR_S2(base, (UART_RD_S2(base) & ~(mask)) | (value)))
+#define UART_SET_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) |  (value)))
+#define UART_CLR_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) & ~(value)))
+#define UART_TOG_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S2 bitfields
+ */
+
+/*!
+ * @name Register UART_S2, field RAF[0] (RO)
+ *
+ * RAF is set when the UART receiver detects a logic 0 during the RT1 time
+ * period of the start bit search. RAF is cleared when the receiver detects an idle
+ * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
+ * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
+ * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
+ * to configure the guard time to 12. However, if a NACK is required to be
+ * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
+ * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
+ * prior to actually being inactive.
+ *
+ * Values:
+ * - 0b0 - UART receiver idle/inactive waiting for a start bit.
+ * - 0b1 - UART receiver active, RxD input not idle.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RAF field. */
+#define UART_RD_S2_RAF(base) ((UART_S2_REG(base) & UART_S2_RAF_MASK) >> UART_S2_RAF_SHIFT)
+#define UART_BRD_S2_RAF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RAF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field LBKDE[1] (RW)
+ *
+ * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
+ * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
+ * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
+ *
+ * Values:
+ * - 0b0 - Break character detection is disabled.
+ * - 0b1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
+ *     12 bits time if C1[M] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_LBKDE field. */
+#define UART_RD_S2_LBKDE(base) ((UART_S2_REG(base) & UART_S2_LBKDE_MASK) >> UART_S2_LBKDE_SHIFT)
+#define UART_BRD_S2_LBKDE(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDE_SHIFT))
+
+/*! @brief Set the LBKDE field to a new value. */
+#define UART_WR_S2_LBKDE(base, value) (UART_RMW_S2(base, (UART_S2_LBKDE_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_LBKDE(value)))
+#define UART_BWR_S2_LBKDE(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field BRK13[2] (RW)
+ *
+ * Determines whether the transmit break character is 10, 11, or 12 bits long,
+ * or 13 or 14 bits long. See for the length of the break character for the
+ * different configurations. The detection of a framing error is not affected by this
+ * field. Transmitting break characters
+ *
+ * Values:
+ * - 0b0 - Break character is 10, 11, or 12 bits long.
+ * - 0b1 - Break character is 13 or 14 bits long.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_BRK13 field. */
+#define UART_RD_S2_BRK13(base) ((UART_S2_REG(base) & UART_S2_BRK13_MASK) >> UART_S2_BRK13_SHIFT)
+#define UART_BRD_S2_BRK13(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT))
+
+/*! @brief Set the BRK13 field to a new value. */
+#define UART_WR_S2_BRK13(base, value) (UART_RMW_S2(base, (UART_S2_BRK13_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_BRK13(value)))
+#define UART_BWR_S2_BRK13(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RWUID[3] (RW)
+ *
+ * When RWU is set and WAKE is cleared, this field controls whether the idle
+ * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - S1[IDLE] is not set upon detection of an idle character.
+ * - 0b1 - S1[IDLE] is set upon detection of an idle character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RWUID field. */
+#define UART_RD_S2_RWUID(base) ((UART_S2_REG(base) & UART_S2_RWUID_MASK) >> UART_S2_RWUID_SHIFT)
+#define UART_BRD_S2_RWUID(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT))
+
+/*! @brief Set the RWUID field to a new value. */
+#define UART_WR_S2_RWUID(base, value) (UART_RMW_S2(base, (UART_S2_RWUID_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RWUID(value)))
+#define UART_BWR_S2_RWUID(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the received data input. In NRZ
+ * format, a one is represented by a mark and a zero is represented by a space for
+ * normal polarity, and the opposite for inverted polarity. In IrDA format, a
+ * zero is represented by short high pulse in the middle of a bit time remaining
+ * idle low for a one for normal polarity. A zero is represented by a short low
+ * pulse in the middle of a bit time remaining idle high for a one for inverted
+ * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
+ * enabled and an initial character is detected in T = 0 protocol mode. Setting
+ * RXINV inverts the RxD input for data bits, start and stop bits, break, and
+ * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
+ * are inverted.
+ *
+ * Values:
+ * - 0b0 - Receive data is not inverted.
+ * - 0b1 - Receive data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXINV field. */
+#define UART_RD_S2_RXINV(base) ((UART_S2_REG(base) & UART_S2_RXINV_MASK) >> UART_S2_RXINV_SHIFT)
+#define UART_BRD_S2_RXINV(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT))
+
+/*! @brief Set the RXINV field to a new value. */
+#define UART_WR_S2_RXINV(base, value) (UART_RMW_S2(base, (UART_S2_RXINV_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RXINV(value)))
+#define UART_BWR_S2_RXINV(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field MSBF[5] (RW)
+ *
+ * Setting this field reverses the order of the bits that are transmitted and
+ * received on the wire. This field does not affect the polarity of the bits, the
+ * location of the parity bit, or the location of the start or stop bits. This
+ * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
+ * an initial character is detected in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0b0 - LSB (bit0) is the first bit that is transmitted following the start
+ *     bit. Further, the first bit received after the start bit is identified as
+ *     bit0.
+ * - 0b1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted
+ *     following the start bit, depending on the setting of C1[M] and C1[PE]. Further,
+ *     the first bit received after the start bit is identified as bit8, bit7, or
+ *     bit6, depending on the setting of C1[M] and C1[PE].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_MSBF field. */
+#define UART_RD_S2_MSBF(base) ((UART_S2_REG(base) & UART_S2_MSBF_MASK) >> UART_S2_MSBF_SHIFT)
+#define UART_BRD_S2_MSBF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT))
+
+/*! @brief Set the MSBF field to a new value. */
+#define UART_WR_S2_MSBF(base, value) (UART_RMW_S2(base, (UART_S2_MSBF_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_MSBF(value)))
+#define UART_BWR_S2_MSBF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXEDGIF[6] (W1C)
+ *
+ * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
+ * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
+ * to it. See for additional details. RXEDGIF description The active edge is
+ * detected only in two wire mode and on receiving data coming from the RxD pin.
+ *
+ * Values:
+ * - 0b0 - No active edge on the receive pin has occurred.
+ * - 0b1 - An active edge on the receive pin has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXEDGIF field. */
+#define UART_RD_S2_RXEDGIF(base) ((UART_S2_REG(base) & UART_S2_RXEDGIF_MASK) >> UART_S2_RXEDGIF_SHIFT)
+#define UART_BRD_S2_RXEDGIF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT))
+
+/*! @brief Set the RXEDGIF field to a new value. */
+#define UART_WR_S2_RXEDGIF(base, value) (UART_RMW_S2(base, (UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RXEDGIF(value)))
+#define UART_BWR_S2_RXEDGIF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field LBKDIF[7] (W1C)
+ *
+ * LBKDIF is set when LBKDE is set and a LIN break character is detected on the
+ * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
+ * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
+ * last LIN break character. LBKDIF is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - No LIN break character detected.
+ * - 0b1 - LIN break character detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_LBKDIF field. */
+#define UART_RD_S2_LBKDIF(base) ((UART_S2_REG(base) & UART_S2_LBKDIF_MASK) >> UART_S2_LBKDIF_SHIFT)
+#define UART_BRD_S2_LBKDIF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDIF_SHIFT))
+
+/*! @brief Set the LBKDIF field to a new value. */
+#define UART_WR_S2_LBKDIF(base, value) (UART_RMW_S2(base, (UART_S2_LBKDIF_MASK | UART_S2_RXEDGIF_MASK), UART_S2_LBKDIF(value)))
+#define UART_BWR_S2_LBKDIF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDIF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C3 - UART Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C3 - UART Control Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_C3 register
+ */
+/*@{*/
+#define UART_RD_C3(base)         (UART_C3_REG(base))
+#define UART_WR_C3(base, value)  (UART_C3_REG(base) = (value))
+#define UART_RMW_C3(base, mask, value) (UART_WR_C3(base, (UART_RD_C3(base) & ~(mask)) | (value)))
+#define UART_SET_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) |  (value)))
+#define UART_CLR_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) & ~(value)))
+#define UART_TOG_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C3 bitfields
+ */
+
+/*!
+ * @name Register UART_C3, field PEIE[0] (RW)
+ *
+ * Enables the parity error flag, S1[PF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - PF interrupt requests are disabled.
+ * - 0b1 - PF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_PEIE field. */
+#define UART_RD_C3_PEIE(base) ((UART_C3_REG(base) & UART_C3_PEIE_MASK) >> UART_C3_PEIE_SHIFT)
+#define UART_BRD_C3_PEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT))
+
+/*! @brief Set the PEIE field to a new value. */
+#define UART_WR_C3_PEIE(base, value) (UART_RMW_C3(base, UART_C3_PEIE_MASK, UART_C3_PEIE(value)))
+#define UART_BWR_C3_PEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field FEIE[1] (RW)
+ *
+ * Enables the framing error flag, S1[FE], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - FE interrupt requests are disabled.
+ * - 0b1 - FE interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_FEIE field. */
+#define UART_RD_C3_FEIE(base) ((UART_C3_REG(base) & UART_C3_FEIE_MASK) >> UART_C3_FEIE_SHIFT)
+#define UART_BRD_C3_FEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define UART_WR_C3_FEIE(base, value) (UART_RMW_C3(base, UART_C3_FEIE_MASK, UART_C3_FEIE(value)))
+#define UART_BWR_C3_FEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field NEIE[2] (RW)
+ *
+ * Enables the noise flag, S1[NF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - NF interrupt requests are disabled.
+ * - 0b1 - NF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_NEIE field. */
+#define UART_RD_C3_NEIE(base) ((UART_C3_REG(base) & UART_C3_NEIE_MASK) >> UART_C3_NEIE_SHIFT)
+#define UART_BRD_C3_NEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT))
+
+/*! @brief Set the NEIE field to a new value. */
+#define UART_WR_C3_NEIE(base, value) (UART_RMW_C3(base, UART_C3_NEIE_MASK, UART_C3_NEIE(value)))
+#define UART_BWR_C3_NEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field ORIE[3] (RW)
+ *
+ * Enables the overrun error flag, S1[OR], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - OR interrupts are disabled.
+ * - 0b1 - OR interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_ORIE field. */
+#define UART_RD_C3_ORIE(base) ((UART_C3_REG(base) & UART_C3_ORIE_MASK) >> UART_C3_ORIE_SHIFT)
+#define UART_BRD_C3_ORIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT))
+
+/*! @brief Set the ORIE field to a new value. */
+#define UART_WR_C3_ORIE(base, value) (UART_RMW_C3(base, UART_C3_ORIE_MASK, UART_C3_ORIE(value)))
+#define UART_BWR_C3_ORIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the transmitted data output. In
+ * NRZ format, a one is represented by a mark and a zero is represented by a space
+ * for normal polarity, and the opposite for inverted polarity. In IrDA format,
+ * a zero is represented by short high pulse in the middle of a bit time
+ * remaining idle low for a one for normal polarity, and a zero is represented by short
+ * low pulse in the middle of a bit time remaining idle high for a one for
+ * inverted polarity. This field is automatically set when C7816[INIT] and
+ * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
+ * Setting TXINV inverts all transmitted values, including idle, break, start, and
+ * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
+ * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
+ * the transmitted data bits and parity bit are inverted.
+ *
+ * Values:
+ * - 0b0 - Transmit data is not inverted.
+ * - 0b1 - Transmit data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXINV field. */
+#define UART_RD_C3_TXINV(base) ((UART_C3_REG(base) & UART_C3_TXINV_MASK) >> UART_C3_TXINV_SHIFT)
+#define UART_BRD_C3_TXINV(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT))
+
+/*! @brief Set the TXINV field to a new value. */
+#define UART_WR_C3_TXINV(base, value) (UART_RMW_C3(base, UART_C3_TXINV_MASK, UART_C3_TXINV(value)))
+#define UART_BWR_C3_TXINV(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXDIR[5] (RW)
+ *
+ * Determines whether the TXD pin is used as an input or output in the
+ * single-wire mode of operation. This field is relevant only to the single wire mode.
+ * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
+ * automatically cleared after the requested block is transmitted. This condition is
+ * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
+ * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
+ * being transmitted, the hardware automatically overrides this field as needed. In
+ * this situation, TXDIR does not reflect the temporary state associated with
+ * the NACK.
+ *
+ * Values:
+ * - 0b0 - TXD pin is an input in single wire mode.
+ * - 0b1 - TXD pin is an output in single wire mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXDIR field. */
+#define UART_RD_C3_TXDIR(base) ((UART_C3_REG(base) & UART_C3_TXDIR_MASK) >> UART_C3_TXDIR_SHIFT)
+#define UART_BRD_C3_TXDIR(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT))
+
+/*! @brief Set the TXDIR field to a new value. */
+#define UART_WR_C3_TXDIR(base, value) (UART_RMW_C3(base, UART_C3_TXDIR_MASK, UART_C3_TXDIR(value)))
+#define UART_BWR_C3_TXDIR(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field T8[6] (RW)
+ *
+ * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
+ * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
+ * same as in the previous transmission, T8 does not have to be rewritten. The same
+ * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
+ * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
+ * the remaining data.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_T8 field. */
+#define UART_RD_C3_T8(base)  ((UART_C3_REG(base) & UART_C3_T8_MASK) >> UART_C3_T8_SHIFT)
+#define UART_BRD_C3_T8(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_T8_SHIFT))
+
+/*! @brief Set the T8 field to a new value. */
+#define UART_WR_C3_T8(base, value) (UART_RMW_C3(base, UART_C3_T8_MASK, UART_C3_T8(value)))
+#define UART_BWR_C3_T8(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_T8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field R8[7] (RO)
+ *
+ * R8 is the ninth data bit received when the UART is configured for 9-bit data
+ * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
+ * current data value in the UARTx_D register. To read the 9th bit, read the
+ * value of UARTx_C3[R8], then read the UARTx_D register.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_R8 field. */
+#define UART_RD_C3_R8(base)  ((UART_C3_REG(base) & UART_C3_R8_MASK) >> UART_C3_R8_SHIFT)
+#define UART_BRD_C3_R8(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_R8_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_D - UART Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_D - UART Data Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is actually two separate registers. Reads return the contents
+ * of the read-only receive data register and writes go to the write-only transmit
+ * data register. In 8-bit or 9-bit data format, only UART data register (D)
+ * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
+ * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
+ * register, only if the ninth bit of data needs to be captured. Similarly, the
+ * ED register needs to be read, prior to the D register, only if the additional
+ * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
+ * bit cleared) if the parity is enabled, you get seven data bits and one parity
+ * bit. That one parity bit is loaded into the D register. So, for the data bits,
+ * mask off the parity bit from the value you read out of this register. When
+ * transmitting in 9-bit data format and using 8-bit write instructions, write first
+ * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
+ * C3[T8] stores the data in a temporary register. If D register is written first,
+ * and then the new data on data bus is stored in D, the temporary value written by
+ * the last write to C3[T8] gets stored in the C3[T8] register.
+ */
+/*!
+ * @name Constants and macros for entire UART_D register
+ */
+/*@{*/
+#define UART_RD_D(base)          (UART_D_REG(base))
+#define UART_WR_D(base, value)   (UART_D_REG(base) = (value))
+#define UART_RMW_D(base, mask, value) (UART_WR_D(base, (UART_RD_D(base) & ~(mask)) | (value)))
+#define UART_SET_D(base, value)  (UART_WR_D(base, UART_RD_D(base) |  (value)))
+#define UART_CLR_D(base, value)  (UART_WR_D(base, UART_RD_D(base) & ~(value)))
+#define UART_TOG_D(base, value)  (UART_WR_D(base, UART_RD_D(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA1 - UART Match Address Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA1 - UART Match Address Registers 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MA1 and MA2 registers are compared to input data addresses when the most
+ * significant bit is set and the associated C4[MAEN] field is set. If a match
+ * occurs, the following data is transferred to the data register. If a match
+ * fails, the following data is discarded. These registers can be read and written at
+ * anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA1 register
+ */
+/*@{*/
+#define UART_RD_MA1(base)        (UART_MA1_REG(base))
+#define UART_WR_MA1(base, value) (UART_MA1_REG(base) = (value))
+#define UART_RMW_MA1(base, mask, value) (UART_WR_MA1(base, (UART_RD_MA1(base) & ~(mask)) | (value)))
+#define UART_SET_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) |  (value)))
+#define UART_CLR_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) & ~(value)))
+#define UART_TOG_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA2 - UART Match Address Registers 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA2 - UART Match Address Registers 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * These registers can be read and written at anytime. The MA1 and MA2 registers
+ * are compared to input data addresses when the most significant bit is set and
+ * the associated C4[MAEN] field is set. If a match occurs, the following data
+ * is transferred to the data register. If a match fails, the following data is
+ * discarded.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA2 register
+ */
+/*@{*/
+#define UART_RD_MA2(base)        (UART_MA2_REG(base))
+#define UART_WR_MA2(base, value) (UART_MA2_REG(base) = (value))
+#define UART_RMW_MA2(base, mask, value) (UART_WR_MA2(base, (UART_RD_MA2(base) & ~(mask)) | (value)))
+#define UART_SET_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) |  (value)))
+#define UART_CLR_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) & ~(value)))
+#define UART_TOG_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C4 - UART Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C4 - UART Control Register 4 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C4 register
+ */
+/*@{*/
+#define UART_RD_C4(base)         (UART_C4_REG(base))
+#define UART_WR_C4(base, value)  (UART_C4_REG(base) = (value))
+#define UART_RMW_C4(base, mask, value) (UART_WR_C4(base, (UART_RD_C4(base) & ~(mask)) | (value)))
+#define UART_SET_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) |  (value)))
+#define UART_CLR_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) & ~(value)))
+#define UART_TOG_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C4 bitfields
+ */
+
+/*!
+ * @name Register UART_C4, field BRFA[4:0] (RW)
+ *
+ * This bit field is used to add more timing resolution to the average baud
+ * frequency, in increments of 1/32. See Baud rate generation for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_BRFA field. */
+#define UART_RD_C4_BRFA(base) ((UART_C4_REG(base) & UART_C4_BRFA_MASK) >> UART_C4_BRFA_SHIFT)
+#define UART_BRD_C4_BRFA(base) (UART_RD_C4_BRFA(base))
+
+/*! @brief Set the BRFA field to a new value. */
+#define UART_WR_C4_BRFA(base, value) (UART_RMW_C4(base, UART_C4_BRFA_MASK, UART_C4_BRFA(value)))
+#define UART_BWR_C4_BRFA(base, value) (UART_WR_C4_BRFA(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field M10[5] (RW)
+ *
+ * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
+ * This tenth bit is generated and interpreted as a parity bit. The M10 field
+ * does not affect the LIN send or detect break behavior. If M10 is set, then both
+ * C1[M] and C1[PE] must also be set. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
+ *
+ * Values:
+ * - 0b0 - The parity bit is the ninth bit in the serial transmission.
+ * - 0b1 - The parity bit is the tenth bit in the serial transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_M10 field. */
+#define UART_RD_C4_M10(base) ((UART_C4_REG(base) & UART_C4_M10_MASK) >> UART_C4_M10_SHIFT)
+#define UART_BRD_C4_M10(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_M10_SHIFT))
+
+/*! @brief Set the M10 field to a new value. */
+#define UART_WR_C4_M10(base, value) (UART_RMW_C4(base, UART_C4_M10_MASK, UART_C4_M10(value)))
+#define UART_BWR_C4_M10(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_M10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN2[6] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0b0 - All data received is transferred to the data buffer if MAEN1 is
+ *     cleared.
+ * - 0b1 - All data received with the most significant bit cleared, is
+ *     discarded. All data received with the most significant bit set, is compared with
+ *     contents of MA2 register. If no match occurs, the data is discarded. If a
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN2 field. */
+#define UART_RD_C4_MAEN2(base) ((UART_C4_REG(base) & UART_C4_MAEN2_MASK) >> UART_C4_MAEN2_SHIFT)
+#define UART_BRD_C4_MAEN2(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT))
+
+/*! @brief Set the MAEN2 field to a new value. */
+#define UART_WR_C4_MAEN2(base, value) (UART_RMW_C4(base, UART_C4_MAEN2_MASK, UART_C4_MAEN2(value)))
+#define UART_BWR_C4_MAEN2(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN1[7] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0b0 - All data received is transferred to the data buffer if MAEN2 is
+ *     cleared.
+ * - 0b1 - All data received with the most significant bit cleared, is
+ *     discarded. All data received with the most significant bit set, is compared with
+ *     contents of MA1 register. If no match occurs, the data is discarded. If
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN1 field. */
+#define UART_RD_C4_MAEN1(base) ((UART_C4_REG(base) & UART_C4_MAEN1_MASK) >> UART_C4_MAEN1_SHIFT)
+#define UART_BRD_C4_MAEN1(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT))
+
+/*! @brief Set the MAEN1 field to a new value. */
+#define UART_WR_C4_MAEN1(base, value) (UART_RMW_C4(base, UART_C4_MAEN1_MASK, UART_C4_MAEN1(value)))
+#define UART_BWR_C4_MAEN1(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C5 - UART Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C5 - UART Control Register 5 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C5 register
+ */
+/*@{*/
+#define UART_RD_C5(base)         (UART_C5_REG(base))
+#define UART_WR_C5(base, value)  (UART_C5_REG(base) = (value))
+#define UART_RMW_C5(base, mask, value) (UART_WR_C5(base, (UART_RD_C5(base) & ~(mask)) | (value)))
+#define UART_SET_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) |  (value)))
+#define UART_CLR_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) & ~(value)))
+#define UART_TOG_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C5 bitfields
+ */
+
+/*!
+ * @name Register UART_C5, field LBKDDMAS[3] (RW)
+ *
+ * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
+ * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
+ * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
+ * of the state of LBKDDMAS.
+ *
+ * Values:
+ * - 0b0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
+ *     asserted to request an interrupt service.
+ * - 0b1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal
+ *     is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_LBKDDMAS field. */
+#define UART_RD_C5_LBKDDMAS(base) ((UART_C5_REG(base) & UART_C5_LBKDDMAS_MASK) >> UART_C5_LBKDDMAS_SHIFT)
+#define UART_BRD_C5_LBKDDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_LBKDDMAS_SHIFT))
+
+/*! @brief Set the LBKDDMAS field to a new value. */
+#define UART_WR_C5_LBKDDMAS(base, value) (UART_RMW_C5(base, UART_C5_LBKDDMAS_MASK, UART_C5_LBKDDMAS(value)))
+#define UART_BWR_C5_LBKDDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_LBKDDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field ILDMAS[4] (RW)
+ *
+ * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
+ * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
+ * DMA and IDLE interrupt request signals are not asserted, regardless of the state
+ * of ILDMAS.
+ *
+ * Values:
+ * - 0b0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal
+ *     is asserted to request an interrupt service.
+ * - 0b1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_ILDMAS field. */
+#define UART_RD_C5_ILDMAS(base) ((UART_C5_REG(base) & UART_C5_ILDMAS_MASK) >> UART_C5_ILDMAS_SHIFT)
+#define UART_BRD_C5_ILDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_ILDMAS_SHIFT))
+
+/*! @brief Set the ILDMAS field to a new value. */
+#define UART_WR_C5_ILDMAS(base, value) (UART_RMW_C5(base, UART_C5_ILDMAS_MASK, UART_C5_ILDMAS(value)))
+#define UART_BWR_C5_ILDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_ILDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field RDMAS[5] (RW)
+ *
+ * Configures the receiver data register full flag, S1[RDRF], to generate
+ * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
+ * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
+ * regardless of the state of RDMAS.
+ *
+ * Values:
+ * - 0b0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
+ *     asserted to request an interrupt service.
+ * - 0b1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_RDMAS field. */
+#define UART_RD_C5_RDMAS(base) ((UART_C5_REG(base) & UART_C5_RDMAS_MASK) >> UART_C5_RDMAS_SHIFT)
+#define UART_BRD_C5_RDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT))
+
+/*! @brief Set the RDMAS field to a new value. */
+#define UART_WR_C5_RDMAS(base, value) (UART_RMW_C5(base, UART_C5_RDMAS_MASK, UART_C5_RDMAS(value)))
+#define UART_BWR_C5_RDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TCDMAS[6] (RW)
+ *
+ * Configures the transmission complete flag, S1[TC], to generate interrupt or
+ * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
+ * interrupt request signals are not asserted when the S1[TC] flag is set, regardless
+ * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
+ * must be cleared, and D must not be written unless a DMA request is being serviced.
+ *
+ * Values:
+ * - 0b0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt
+ *     request signal is asserted to request an interrupt service.
+ * - 0b1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TCDMAS field. */
+#define UART_RD_C5_TCDMAS(base) ((UART_C5_REG(base) & UART_C5_TCDMAS_MASK) >> UART_C5_TCDMAS_SHIFT)
+#define UART_BRD_C5_TCDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TCDMAS_SHIFT))
+
+/*! @brief Set the TCDMAS field to a new value. */
+#define UART_WR_C5_TCDMAS(base, value) (UART_RMW_C5(base, UART_C5_TCDMAS_MASK, UART_C5_TCDMAS(value)))
+#define UART_BWR_C5_TCDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TCDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TDMAS[7] (RW)
+ *
+ * Configures the transmit data register empty flag, S1[TDRE], to generate
+ * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
+ * TDRE interrupt request signals are not asserted when the TDRE flag is set,
+ * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
+ * must be cleared, and D must not be written unless a DMA request is being
+ * serviced.
+ *
+ * Values:
+ * - 0b0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
+ *     request signal is asserted to request interrupt service.
+ * - 0b1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TDMAS field. */
+#define UART_RD_C5_TDMAS(base) ((UART_C5_REG(base) & UART_C5_TDMAS_MASK) >> UART_C5_TDMAS_SHIFT)
+#define UART_BRD_C5_TDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT))
+
+/*! @brief Set the TDMAS field to a new value. */
+#define UART_WR_C5_TDMAS(base, value) (UART_RMW_C5(base, UART_C5_TDMAS_MASK, UART_C5_TDMAS(value)))
+#define UART_BWR_C5_TDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ED - UART Extended Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ED - UART Extended Data Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains additional information flags that are stored with a
+ * received dataword. This register may be read at any time but contains valid data
+ * only if there is a dataword in the receive FIFO. The data contained in this
+ * register represents additional information regarding the conditions on which a
+ * dataword was received. The importance of this data varies with the
+ * application, and in some cases maybe completely optional. These fields automatically
+ * update to reflect the conditions of the next dataword whenever D is read. If
+ * S1[NF] and S1[PF] have not been set since the last time the receive buffer was
+ * empty, the NOISY and PARITYE fields will be zero.
+ */
+/*!
+ * @name Constants and macros for entire UART_ED register
+ */
+/*@{*/
+#define UART_RD_ED(base)         (UART_ED_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ED bitfields
+ */
+
+/*!
+ * @name Register UART_ED, field PARITYE[6] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with a
+ * parity error.
+ *
+ * Values:
+ * - 0b0 - The dataword was received without a parity error.
+ * - 0b1 - The dataword was received with a parity error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ED_PARITYE field. */
+#define UART_RD_ED_PARITYE(base) ((UART_ED_REG(base) & UART_ED_PARITYE_MASK) >> UART_ED_PARITYE_SHIFT)
+#define UART_BRD_ED_PARITYE(base) (BITBAND_ACCESS8(&UART_ED_REG(base), UART_ED_PARITYE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_ED, field NOISY[7] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with
+ * noise.
+ *
+ * Values:
+ * - 0b0 - The dataword was received without noise.
+ * - 0b1 - The data was received with noise.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ED_NOISY field. */
+#define UART_RD_ED_NOISY(base) ((UART_ED_REG(base) & UART_ED_NOISY_MASK) >> UART_ED_NOISY_SHIFT)
+#define UART_BRD_ED_NOISY(base) (BITBAND_ACCESS8(&UART_ED_REG(base), UART_ED_NOISY_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MODEM - UART Modem Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MODEM - UART Modem Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MODEM register controls options for setting the modem configuration.
+ * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
+ * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
+ * ISO-7816 protocol does not use the RTS and CTS signals.
+ */
+/*!
+ * @name Constants and macros for entire UART_MODEM register
+ */
+/*@{*/
+#define UART_RD_MODEM(base)      (UART_MODEM_REG(base))
+#define UART_WR_MODEM(base, value) (UART_MODEM_REG(base) = (value))
+#define UART_RMW_MODEM(base, mask, value) (UART_WR_MODEM(base, (UART_RD_MODEM(base) & ~(mask)) | (value)))
+#define UART_SET_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) |  (value)))
+#define UART_CLR_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) & ~(value)))
+#define UART_TOG_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_MODEM bitfields
+ */
+
+/*!
+ * @name Register UART_MODEM, field TXCTSE[0] (RW)
+ *
+ * TXCTSE controls the operation of the transmitter. TXCTSE can be set
+ * independently from the state of TXRTSE and RXRTSE.
+ *
+ * Values:
+ * - 0b0 - CTS has no effect on the transmitter.
+ * - 0b1 - Enables clear-to-send operation. The transmitter checks the state of
+ *     CTS each time it is ready to send a character. If CTS is asserted, the
+ *     character is sent. If CTS is deasserted, the signal TXD remains in the mark
+ *     state and transmission is delayed until CTS is asserted. Changes in CTS as
+ *     a character is being sent do not affect its transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXCTSE field. */
+#define UART_RD_MODEM_TXCTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_TXCTSE_MASK) >> UART_MODEM_TXCTSE_SHIFT)
+#define UART_BRD_MODEM_TXCTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXCTSE_SHIFT))
+
+/*! @brief Set the TXCTSE field to a new value. */
+#define UART_WR_MODEM_TXCTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXCTSE_MASK, UART_MODEM_TXCTSE(value)))
+#define UART_BWR_MODEM_TXCTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXCTSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field TXRTSE[1] (RW)
+ *
+ * Controls RTS before and after a transmission.
+ *
+ * Values:
+ * - 0b0 - The transmitter has no effect on RTS.
+ * - 0b1 - When a character is placed into an empty transmitter data buffer ,
+ *     RTS asserts one bit time before the start bit is transmitted. RTS deasserts
+ *     one bit time after all characters in the transmitter data buffer and shift
+ *     register are completely sent, including the last stop bit. (FIFO) (FIFO)
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXRTSE field. */
+#define UART_RD_MODEM_TXRTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_TXRTSE_MASK) >> UART_MODEM_TXRTSE_SHIFT)
+#define UART_BRD_MODEM_TXRTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSE_SHIFT))
+
+/*! @brief Set the TXRTSE field to a new value. */
+#define UART_WR_MODEM_TXRTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXRTSE_MASK, UART_MODEM_TXRTSE(value)))
+#define UART_BWR_MODEM_TXRTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field TXRTSPOL[2] (RW)
+ *
+ * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
+ * polarity of the receiver RTS. RTS will remain negated in the active low state
+ * unless TXRTSE is set.
+ *
+ * Values:
+ * - 0b0 - Transmitter RTS is active low.
+ * - 0b1 - Transmitter RTS is active high.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXRTSPOL field. */
+#define UART_RD_MODEM_TXRTSPOL(base) ((UART_MODEM_REG(base) & UART_MODEM_TXRTSPOL_MASK) >> UART_MODEM_TXRTSPOL_SHIFT)
+#define UART_BRD_MODEM_TXRTSPOL(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSPOL_SHIFT))
+
+/*! @brief Set the TXRTSPOL field to a new value. */
+#define UART_WR_MODEM_TXRTSPOL(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXRTSPOL_MASK, UART_MODEM_TXRTSPOL(value)))
+#define UART_BWR_MODEM_TXRTSPOL(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field RXRTSE[3] (RW)
+ *
+ * Allows the RTS output to control the CTS input of the transmitting device to
+ * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
+ *
+ * Values:
+ * - 0b0 - The receiver has no effect on RTS.
+ * - 0b1 - RTS is deasserted if the number of characters in the receiver data
+ *     register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
+ *     when the number of characters in the receiver data register (FIFO) is
+ *     less than RWFIFO[RXWATER].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_RXRTSE field. */
+#define UART_RD_MODEM_RXRTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_RXRTSE_MASK) >> UART_MODEM_RXRTSE_SHIFT)
+#define UART_BRD_MODEM_RXRTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_RXRTSE_SHIFT))
+
+/*! @brief Set the RXRTSE field to a new value. */
+#define UART_WR_MODEM_RXRTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_RXRTSE_MASK, UART_MODEM_RXRTSE(value)))
+#define UART_BWR_MODEM_RXRTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_RXRTSE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IR - UART Infrared Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IR - UART Infrared Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IR register controls options for setting the infrared configuration.
+ */
+/*!
+ * @name Constants and macros for entire UART_IR register
+ */
+/*@{*/
+#define UART_RD_IR(base)         (UART_IR_REG(base))
+#define UART_WR_IR(base, value)  (UART_IR_REG(base) = (value))
+#define UART_RMW_IR(base, mask, value) (UART_WR_IR(base, (UART_RD_IR(base) & ~(mask)) | (value)))
+#define UART_SET_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) |  (value)))
+#define UART_CLR_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) & ~(value)))
+#define UART_TOG_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IR bitfields
+ */
+
+/*!
+ * @name Register UART_IR, field TNP[1:0] (RW)
+ *
+ * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
+ *
+ * Values:
+ * - 0b00 - 3/16.
+ * - 0b01 - 1/16.
+ * - 0b10 - 1/32.
+ * - 0b11 - 1/4.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IR_TNP field. */
+#define UART_RD_IR_TNP(base) ((UART_IR_REG(base) & UART_IR_TNP_MASK) >> UART_IR_TNP_SHIFT)
+#define UART_BRD_IR_TNP(base) (UART_RD_IR_TNP(base))
+
+/*! @brief Set the TNP field to a new value. */
+#define UART_WR_IR_TNP(base, value) (UART_RMW_IR(base, UART_IR_TNP_MASK, UART_IR_TNP(value)))
+#define UART_BWR_IR_TNP(base, value) (UART_WR_IR_TNP(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_IR, field IREN[2] (RW)
+ *
+ * Enables/disables the infrared modulation/demodulation.
+ *
+ * Values:
+ * - 0b0 - IR disabled.
+ * - 0b1 - IR enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IR_IREN field. */
+#define UART_RD_IR_IREN(base) ((UART_IR_REG(base) & UART_IR_IREN_MASK) >> UART_IR_IREN_SHIFT)
+#define UART_BRD_IR_IREN(base) (BITBAND_ACCESS8(&UART_IR_REG(base), UART_IR_IREN_SHIFT))
+
+/*! @brief Set the IREN field to a new value. */
+#define UART_WR_IR_IREN(base, value) (UART_RMW_IR(base, UART_IR_IREN_MASK, UART_IR_IREN(value)))
+#define UART_BWR_IR_IREN(base, value) (BITBAND_ACCESS8(&UART_IR_REG(base), UART_IR_IREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_PFIFO - UART FIFO Parameters
+ ******************************************************************************/
+
+/*!
+ * @brief UART_PFIFO - UART FIFO Parameters (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability for the programmer to turn on and off FIFO
+ * functionality. It also provides the size of the FIFO that has been
+ * implemented. This register may be read at any time. This register must be written only
+ * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
+ * empty.
+ */
+/*!
+ * @name Constants and macros for entire UART_PFIFO register
+ */
+/*@{*/
+#define UART_RD_PFIFO(base)      (UART_PFIFO_REG(base))
+#define UART_WR_PFIFO(base, value) (UART_PFIFO_REG(base) = (value))
+#define UART_RMW_PFIFO(base, mask, value) (UART_WR_PFIFO(base, (UART_RD_PFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) |  (value)))
+#define UART_CLR_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) & ~(value)))
+#define UART_TOG_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_PFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
+ *
+ * The maximum number of receive datawords that can be stored in the receive
+ * buffer before an overrun occurs. This field is read only.
+ *
+ * Values:
+ * - 0b000 - Receive FIFO/Buffer depth = 1 dataword.
+ * - 0b001 - Receive FIFO/Buffer depth = 4 datawords.
+ * - 0b010 - Receive FIFO/Buffer depth = 8 datawords.
+ * - 0b011 - Receive FIFO/Buffer depth = 16 datawords.
+ * - 0b100 - Receive FIFO/Buffer depth = 32 datawords.
+ * - 0b101 - Receive FIFO/Buffer depth = 64 datawords.
+ * - 0b110 - Receive FIFO/Buffer depth = 128 datawords.
+ * - 0b111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. */
+#define UART_RD_PFIFO_RXFIFOSIZE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_RXFIFOSIZE_MASK) >> UART_PFIFO_RXFIFOSIZE_SHIFT)
+#define UART_BRD_PFIFO_RXFIFOSIZE(base) (UART_RD_PFIFO_RXFIFOSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field RXFE[3] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the receive buffer is
+ * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
+ * If this field is not set, the receive buffer operates as a FIFO of depth one
+ * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
+ * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
+ * commands must be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0b0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
+ * - 0b1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_RXFE field. */
+#define UART_RD_PFIFO_RXFE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_RXFE_MASK) >> UART_PFIFO_RXFE_SHIFT)
+#define UART_BRD_PFIFO_RXFE(base) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_RXFE_SHIFT))
+
+/*! @brief Set the RXFE field to a new value. */
+#define UART_WR_PFIFO_RXFE(base, value) (UART_RMW_PFIFO(base, UART_PFIFO_RXFE_MASK, UART_PFIFO_RXFE(value)))
+#define UART_BWR_PFIFO_RXFE(base, value) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_RXFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
+ *
+ * The maximum number of transmit datawords that can be stored in the transmit
+ * buffer. This field is read only.
+ *
+ * Values:
+ * - 0b000 - Transmit FIFO/Buffer depth = 1 dataword.
+ * - 0b001 - Transmit FIFO/Buffer depth = 4 datawords.
+ * - 0b010 - Transmit FIFO/Buffer depth = 8 datawords.
+ * - 0b011 - Transmit FIFO/Buffer depth = 16 datawords.
+ * - 0b100 - Transmit FIFO/Buffer depth = 32 datawords.
+ * - 0b101 - Transmit FIFO/Buffer depth = 64 datawords.
+ * - 0b110 - Transmit FIFO/Buffer depth = 128 datawords.
+ * - 0b111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. */
+#define UART_RD_PFIFO_TXFIFOSIZE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_TXFIFOSIZE_MASK) >> UART_PFIFO_TXFIFOSIZE_SHIFT)
+#define UART_BRD_PFIFO_TXFIFOSIZE(base) (UART_RD_PFIFO_TXFIFOSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field TXFE[7] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the transmit buffer
+ * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
+ * field is not set, the transmit buffer operates as a FIFO of depth one dataword
+ * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
+ * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
+ * be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0b0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
+ * - 0b1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_TXFE field. */
+#define UART_RD_PFIFO_TXFE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_TXFE_MASK) >> UART_PFIFO_TXFE_SHIFT)
+#define UART_BRD_PFIFO_TXFE(base) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_TXFE_SHIFT))
+
+/*! @brief Set the TXFE field to a new value. */
+#define UART_WR_PFIFO_TXFE(base, value) (UART_RMW_PFIFO(base, UART_PFIFO_TXFE_MASK, UART_PFIFO_TXFE(value)))
+#define UART_BWR_PFIFO_TXFE(base, value) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_TXFE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_CFIFO - UART FIFO Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_CFIFO - UART FIFO Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to program various control fields for FIFO
+ * operation. This register may be read or written at any time. Note that
+ * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
+ * to prevent unintended/unpredictable behavior. Therefore, it is recommended that
+ * TE and RE be cleared prior to flushing the corresponding FIFO.
+ */
+/*!
+ * @name Constants and macros for entire UART_CFIFO register
+ */
+/*@{*/
+#define UART_RD_CFIFO(base)      (UART_CFIFO_REG(base))
+#define UART_WR_CFIFO(base, value) (UART_CFIFO_REG(base) = (value))
+#define UART_RMW_CFIFO(base, mask, value) (UART_WR_CFIFO(base, (UART_RD_CFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) |  (value)))
+#define UART_CLR_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) & ~(value)))
+#define UART_TOG_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_CFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_CFIFO, field RXUFE[0] (RW)
+ *
+ * When this field is set, the RXUF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - RXUF flag does not generate an interrupt to the host.
+ * - 0b1 - RXUF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_RXUFE field. */
+#define UART_RD_CFIFO_RXUFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_RXUFE_MASK) >> UART_CFIFO_RXUFE_SHIFT)
+#define UART_BRD_CFIFO_RXUFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXUFE_SHIFT))
+
+/*! @brief Set the RXUFE field to a new value. */
+#define UART_WR_CFIFO_RXUFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXUFE_MASK, UART_CFIFO_RXUFE(value)))
+#define UART_BWR_CFIFO_RXUFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXUFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field TXOFE[1] (RW)
+ *
+ * When this field is set, the TXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - TXOF flag does not generate an interrupt to the host.
+ * - 0b1 - TXOF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_TXOFE field. */
+#define UART_RD_CFIFO_TXOFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_TXOFE_MASK) >> UART_CFIFO_TXOFE_SHIFT)
+#define UART_BRD_CFIFO_TXOFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXOFE_SHIFT))
+
+/*! @brief Set the TXOFE field to a new value. */
+#define UART_WR_CFIFO_TXOFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_TXOFE_MASK, UART_CFIFO_TXOFE(value)))
+#define UART_BWR_CFIFO_TXOFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXOFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field RXOFE[2] (RW)
+ *
+ * When this field is set, the RXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - RXOF flag does not generate an interrupt to the host.
+ * - 0b1 - RXOF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_RXOFE field. */
+#define UART_RD_CFIFO_RXOFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_RXOFE_MASK) >> UART_CFIFO_RXOFE_SHIFT)
+#define UART_BRD_CFIFO_RXOFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXOFE_SHIFT))
+
+/*! @brief Set the RXOFE field to a new value. */
+#define UART_WR_CFIFO_RXOFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXOFE_MASK, UART_CFIFO_RXOFE(value)))
+#define UART_BWR_CFIFO_RXOFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXOFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the receive
+ * FIFO/buffer to be flushed. This does not affect data that is in the receive shift
+ * register.
+ *
+ * Values:
+ * - 0b0 - No flush operation occurs.
+ * - 0b1 - All data in the receive FIFO/buffer is cleared out.
+ */
+/*@{*/
+/*! @brief Set the RXFLUSH field to a new value. */
+#define UART_WR_CFIFO_RXFLUSH(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXFLUSH_MASK, UART_CFIFO_RXFLUSH(value)))
+#define UART_BWR_CFIFO_RXFLUSH(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXFLUSH_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the transmit
+ * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
+ * register.
+ *
+ * Values:
+ * - 0b0 - No flush operation occurs.
+ * - 0b1 - All data in the transmit FIFO/Buffer is cleared out.
+ */
+/*@{*/
+/*! @brief Set the TXFLUSH field to a new value. */
+#define UART_WR_CFIFO_TXFLUSH(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_TXFLUSH_MASK, UART_CFIFO_TXFLUSH(value)))
+#define UART_BWR_CFIFO_TXFLUSH(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXFLUSH_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_SFIFO - UART FIFO Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_SFIFO - UART FIFO Status Register (RW)
+ *
+ * Reset value: 0xC0U
+ *
+ * This register provides status information regarding the transmit and receiver
+ * buffers/FIFOs, including interrupt information. This register may be written
+ * to or read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_SFIFO register
+ */
+/*@{*/
+#define UART_RD_SFIFO(base)      (UART_SFIFO_REG(base))
+#define UART_WR_SFIFO(base, value) (UART_SFIFO_REG(base) = (value))
+#define UART_RMW_SFIFO(base, mask, value) (UART_WR_SFIFO(base, (UART_RD_SFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) |  (value)))
+#define UART_CLR_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) & ~(value)))
+#define UART_TOG_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_SFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_SFIFO, field RXUF[0] (W1C)
+ *
+ * Indicates that more data has been read from the receive buffer than was
+ * present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No receive buffer underflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one receive buffer underflow has occurred since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXUF field. */
+#define UART_RD_SFIFO_RXUF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXUF_MASK) >> UART_SFIFO_RXUF_SHIFT)
+#define UART_BRD_SFIFO_RXUF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXUF_SHIFT))
+
+/*! @brief Set the RXUF field to a new value. */
+#define UART_WR_SFIFO_RXUF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_RXUF_MASK | UART_SFIFO_TXOF_MASK | UART_SFIFO_RXOF_MASK), UART_SFIFO_RXUF(value)))
+#define UART_BWR_SFIFO_RXUF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field TXOF[1] (W1C)
+ *
+ * Indicates that more data has been written to the transmit buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
+ * flag is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No transmit buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one transmit buffer overflow has occurred since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_TXOF field. */
+#define UART_RD_SFIFO_TXOF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_TXOF_MASK) >> UART_SFIFO_TXOF_SHIFT)
+#define UART_BRD_SFIFO_TXOF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXOF_SHIFT))
+
+/*! @brief Set the TXOF field to a new value. */
+#define UART_WR_SFIFO_TXOF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_TXOF_MASK | UART_SFIFO_RXUF_MASK | UART_SFIFO_RXOF_MASK), UART_SFIFO_TXOF(value)))
+#define UART_BWR_SFIFO_TXOF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field RXOF[2] (W1C)
+ *
+ * Indicates that more data has been written to the receive buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No receive buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one receive buffer overflow has occurred since the last time
+ *     the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXOF field. */
+#define UART_RD_SFIFO_RXOF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXOF_MASK) >> UART_SFIFO_RXOF_SHIFT)
+#define UART_BRD_SFIFO_RXOF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXOF_SHIFT))
+
+/*! @brief Set the RXOF field to a new value. */
+#define UART_WR_SFIFO_RXOF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_RXOF_MASK | UART_SFIFO_RXUF_MASK | UART_SFIFO_TXOF_MASK), UART_SFIFO_RXOF(value)))
+#define UART_BWR_SFIFO_RXOF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field RXEMPT[6] (RO)
+ *
+ * Asserts when there is no data in the receive FIFO/Buffer. This field does not
+ * take into account data that is in the receive shift register.
+ *
+ * Values:
+ * - 0b0 - Receive buffer is not empty.
+ * - 0b1 - Receive buffer is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXEMPT field. */
+#define UART_RD_SFIFO_RXEMPT(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXEMPT_MASK) >> UART_SFIFO_RXEMPT_SHIFT)
+#define UART_BRD_SFIFO_RXEMPT(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXEMPT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field TXEMPT[7] (RO)
+ *
+ * Asserts when there is no data in the Transmit FIFO/buffer. This field does
+ * not take into account data that is in the transmit shift register.
+ *
+ * Values:
+ * - 0b0 - Transmit buffer is not empty.
+ * - 0b1 - Transmit buffer is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_TXEMPT field. */
+#define UART_RD_SFIFO_TXEMPT(base) ((UART_SFIFO_REG(base) & UART_SFIFO_TXEMPT_MASK) >> UART_SFIFO_TXEMPT_SHIFT)
+#define UART_BRD_SFIFO_TXEMPT(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXEMPT_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TWFIFO - UART FIFO Transmit Watermark
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TWFIFO - UART FIFO Transmit Watermark (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of needing additional transmit data. This register may be read at any
+ * time but must be written only when C2[TE] is not set. Changing the value of the
+ * watermark will not clear the S1[TDRE] flag.
+ */
+/*!
+ * @name Constants and macros for entire UART_TWFIFO register
+ */
+/*@{*/
+#define UART_RD_TWFIFO(base)     (UART_TWFIFO_REG(base))
+#define UART_WR_TWFIFO(base, value) (UART_TWFIFO_REG(base) = (value))
+#define UART_RMW_TWFIFO(base, mask, value) (UART_WR_TWFIFO(base, (UART_RD_TWFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) |  (value)))
+#define UART_CLR_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) & ~(value)))
+#define UART_TOG_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TCFIFO - UART FIFO Transmit Count
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TCFIFO - UART FIFO Transmit Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the transmit buffer/FIFO. It may be read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_TCFIFO register
+ */
+/*@{*/
+#define UART_RD_TCFIFO(base)     (UART_TCFIFO_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * UART_RWFIFO - UART FIFO Receive Watermark
+ ******************************************************************************/
+
+/*!
+ * @brief UART_RWFIFO - UART FIFO Receive Watermark (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of the need to remove data from the receiver FIFO/buffer. This register
+ * may be read at any time but must be written only when C2[RE] is not asserted.
+ * Changing the value in this register will not clear S1[RDRF].
+ */
+/*!
+ * @name Constants and macros for entire UART_RWFIFO register
+ */
+/*@{*/
+#define UART_RD_RWFIFO(base)     (UART_RWFIFO_REG(base))
+#define UART_WR_RWFIFO(base, value) (UART_RWFIFO_REG(base) = (value))
+#define UART_RMW_RWFIFO(base, mask, value) (UART_WR_RWFIFO(base, (UART_RD_RWFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) |  (value)))
+#define UART_CLR_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) & ~(value)))
+#define UART_TOG_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_RCFIFO - UART FIFO Receive Count
+ ******************************************************************************/
+
+/*!
+ * @brief UART_RCFIFO - UART FIFO Receive Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the receive FIFO/buffer. It may be read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_RCFIFO register
+ */
+/*@{*/
+#define UART_RD_RCFIFO(base)     (UART_RCFIFO_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C7816 - UART 7816 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C7816 - UART 7816 Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The C7816 register is the primary control register for ISO-7816 specific
+ * functionality. This register is specific to 7816 functionality and the values in
+ * this register have no effect on UART operation and should be ignored if
+ * ISO_7816E is not set/enabled. This register may be read at any time but values must
+ * be changed only when ISO_7816E is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_C7816 register
+ */
+/*@{*/
+#define UART_RD_C7816(base)      (UART_C7816_REG(base))
+#define UART_WR_C7816(base, value) (UART_C7816_REG(base) = (value))
+#define UART_RMW_C7816(base, mask, value) (UART_WR_C7816(base, (UART_RD_C7816(base) & ~(mask)) | (value)))
+#define UART_SET_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) |  (value)))
+#define UART_CLR_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) & ~(value)))
+#define UART_TOG_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C7816 bitfields
+ */
+
+/*!
+ * @name Register UART_C7816, field ISO_7816E[0] (RW)
+ *
+ * Indicates that the UART is operating according to the ISO-7816 protocol. This
+ * field must be modified only when no transmit or receive is occurring. If this
+ * field is changed during a data transfer, the data being transmitted or
+ * received may be transferred incorrectly.
+ *
+ * Values:
+ * - 0b0 - ISO-7816 functionality is turned off/not enabled.
+ * - 0b1 - ISO-7816 functionality is turned on/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ISO_7816E field. */
+#define UART_RD_C7816_ISO_7816E(base) ((UART_C7816_REG(base) & UART_C7816_ISO_7816E_MASK) >> UART_C7816_ISO_7816E_SHIFT)
+#define UART_BRD_C7816_ISO_7816E(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT))
+
+/*! @brief Set the ISO_7816E field to a new value. */
+#define UART_WR_C7816_ISO_7816E(base, value) (UART_RMW_C7816(base, UART_C7816_ISO_7816E_MASK, UART_C7816_ISO_7816E(value)))
+#define UART_BWR_C7816_ISO_7816E(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field TTYPE[1] (RW)
+ *
+ * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
+ * for more details.
+ *
+ * Values:
+ * - 0b0 - T = 0 per the ISO-7816 specification.
+ * - 0b1 - T = 1 per the ISO-7816 specification.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_TTYPE field. */
+#define UART_RD_C7816_TTYPE(base) ((UART_C7816_REG(base) & UART_C7816_TTYPE_MASK) >> UART_C7816_TTYPE_SHIFT)
+#define UART_BRD_C7816_TTYPE(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT))
+
+/*! @brief Set the TTYPE field to a new value. */
+#define UART_WR_C7816_TTYPE(base, value) (UART_RMW_C7816(base, UART_C7816_TTYPE_MASK, UART_C7816_TTYPE(value)))
+#define UART_BWR_C7816_TTYPE(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field INIT[2] (RW)
+ *
+ * When this field is set, all received characters are searched for a valid
+ * initial character. If an invalid initial character is identified, and ANACK is
+ * set, a NACK is sent. All received data is discarded and error flags blocked
+ * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
+ * until a valid initial character is detected. Upon detecting a valid initial
+ * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
+ * automatically updated to reflect the initial character that was received. The
+ * actual INIT data value is not stored in the receive buffer. Additionally, upon
+ * detection of a valid initial character, IS7816[INITD] is set and an interrupt
+ * issued as programmed by IE7816[INITDE]. When a valid initial character is
+ * detected, INIT is automatically cleared. This Initial Character Detect feature is
+ * supported only in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0b0 - Normal operating mode. Receiver does not seek to identify initial
+ *     character.
+ * - 0b1 - Receiver searches for initial character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_INIT field. */
+#define UART_RD_C7816_INIT(base) ((UART_C7816_REG(base) & UART_C7816_INIT_MASK) >> UART_C7816_INIT_SHIFT)
+#define UART_BRD_C7816_INIT(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT))
+
+/*! @brief Set the INIT field to a new value. */
+#define UART_WR_C7816_INIT(base, value) (UART_RMW_C7816(base, UART_C7816_INIT_MASK, UART_C7816_INIT(value)))
+#define UART_BWR_C7816_INIT(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ANACK[3] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a parity error occurs or if INIT is set and an invalid initial character is
+ * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
+ * attempts to retransmit the data indefinitely. To stop retransmission attempts,
+ * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
+ *
+ * Values:
+ * - 0b0 - No NACK is automatically generated.
+ * - 0b1 - A NACK is automatically generated if a parity error is detected or if
+ *     an invalid initial character is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ANACK field. */
+#define UART_RD_C7816_ANACK(base) ((UART_C7816_REG(base) & UART_C7816_ANACK_MASK) >> UART_C7816_ANACK_SHIFT)
+#define UART_BRD_C7816_ANACK(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT))
+
+/*! @brief Set the ANACK field to a new value. */
+#define UART_WR_C7816_ANACK(base, value) (UART_RMW_C7816(base, UART_C7816_ANACK_MASK, UART_C7816_ANACK(value)))
+#define UART_BWR_C7816_ANACK(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ONACK[4] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
+ * this results in the transmitter resending the packet that overflowed until the
+ * retransmit threshold for that transmitter is reached. A NACK is generated only
+ * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
+ * considerations
+ *
+ * Values:
+ * - 0b0 - The received data does not generate a NACK when the receipt of the
+ *     data results in an overflow event.
+ * - 0b1 - If the receiver buffer overflows, a NACK is automatically sent on a
+ *     received character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ONACK field. */
+#define UART_RD_C7816_ONACK(base) ((UART_C7816_REG(base) & UART_C7816_ONACK_MASK) >> UART_C7816_ONACK_SHIFT)
+#define UART_BRD_C7816_ONACK(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT))
+
+/*! @brief Set the ONACK field to a new value. */
+#define UART_WR_C7816_ONACK(base, value) (UART_RMW_C7816(base, UART_C7816_ONACK_MASK, UART_C7816_ONACK(value)))
+#define UART_BWR_C7816_ONACK(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IE7816 - UART 7816 Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IE7816 register controls which flags result in an interrupt being issued.
+ * This register is specific to 7816 functionality, the corresponding flags that
+ * drive the interrupts are not asserted when 7816E is not set/enabled. However,
+ * these flags may remain set if they are asserted while 7816E was set and not
+ * subsequently cleared. This register may be read or written to at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_IE7816 register
+ */
+/*@{*/
+#define UART_RD_IE7816(base)     (UART_IE7816_REG(base))
+#define UART_WR_IE7816(base, value) (UART_IE7816_REG(base) = (value))
+#define UART_RMW_IE7816(base, mask, value) (UART_WR_IE7816(base, (UART_RD_IE7816(base) & ~(mask)) | (value)))
+#define UART_SET_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) |  (value)))
+#define UART_CLR_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) & ~(value)))
+#define UART_TOG_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IE7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IE7816, field RXTE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[RXT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[RXT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_RXTE field. */
+#define UART_RD_IE7816_RXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_RXTE_MASK) >> UART_IE7816_RXTE_SHIFT)
+#define UART_BRD_IE7816_RXTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT))
+
+/*! @brief Set the RXTE field to a new value. */
+#define UART_WR_IE7816_RXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_RXTE_MASK, UART_IE7816_RXTE(value)))
+#define UART_BWR_IE7816_RXTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field TXTE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[TXT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[TXT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_TXTE field. */
+#define UART_RD_IE7816_TXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_TXTE_MASK) >> UART_IE7816_TXTE_SHIFT)
+#define UART_BRD_IE7816_TXTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT))
+
+/*! @brief Set the TXTE field to a new value. */
+#define UART_WR_IE7816_TXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_TXTE_MASK, UART_IE7816_TXTE(value)))
+#define UART_BWR_IE7816_TXTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field GTVE[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[GTV] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[GTV] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_GTVE field. */
+#define UART_RD_IE7816_GTVE(base) ((UART_IE7816_REG(base) & UART_IE7816_GTVE_MASK) >> UART_IE7816_GTVE_SHIFT)
+#define UART_BRD_IE7816_GTVE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT))
+
+/*! @brief Set the GTVE field to a new value. */
+#define UART_WR_IE7816_GTVE(base, value) (UART_RMW_IE7816(base, UART_IE7816_GTVE_MASK, UART_IE7816_GTVE(value)))
+#define UART_BWR_IE7816_GTVE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field INITDE[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[INITD] does not result in the generation of
+ *     an interrupt.
+ * - 0b1 - The assertion of IS7816[INITD] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_INITDE field. */
+#define UART_RD_IE7816_INITDE(base) ((UART_IE7816_REG(base) & UART_IE7816_INITDE_MASK) >> UART_IE7816_INITDE_SHIFT)
+#define UART_BRD_IE7816_INITDE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT))
+
+/*! @brief Set the INITDE field to a new value. */
+#define UART_WR_IE7816_INITDE(base, value) (UART_RMW_IE7816(base, UART_IE7816_INITDE_MASK, UART_IE7816_INITDE(value)))
+#define UART_BWR_IE7816_INITDE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field BWTE[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[BWT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[BWT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_BWTE field. */
+#define UART_RD_IE7816_BWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_BWTE_MASK) >> UART_IE7816_BWTE_SHIFT)
+#define UART_BRD_IE7816_BWTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT))
+
+/*! @brief Set the BWTE field to a new value. */
+#define UART_WR_IE7816_BWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_BWTE_MASK, UART_IE7816_BWTE(value)))
+#define UART_BWR_IE7816_BWTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field CWTE[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[CWT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[CWT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_CWTE field. */
+#define UART_RD_IE7816_CWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_CWTE_MASK) >> UART_IE7816_CWTE_SHIFT)
+#define UART_BRD_IE7816_CWTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT))
+
+/*! @brief Set the CWTE field to a new value. */
+#define UART_WR_IE7816_CWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_CWTE_MASK, UART_IE7816_CWTE(value)))
+#define UART_BWR_IE7816_CWTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field WTE[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[WT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[WT] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_WTE field. */
+#define UART_RD_IE7816_WTE(base) ((UART_IE7816_REG(base) & UART_IE7816_WTE_MASK) >> UART_IE7816_WTE_SHIFT)
+#define UART_BRD_IE7816_WTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT))
+
+/*! @brief Set the WTE field to a new value. */
+#define UART_WR_IE7816_WTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_WTE_MASK, UART_IE7816_WTE(value)))
+#define UART_BWR_IE7816_WTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IS7816 - UART 7816 Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IS7816 - UART 7816 Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IS7816 register provides a mechanism to read and clear the interrupt
+ * flags. All flags/interrupts are cleared by writing a 1 to the field location.
+ * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
+ * the flag condition that occurred since the last time the bit was cleared, not
+ * that the condition currently exists. The status flags are set regardless of
+ * whether the corresponding field in the IE7816 is set or cleared. The IE7816
+ * controls only if an interrupt is issued to the host processor. This register is
+ * specific to 7816 functionality and the values in this register have no affect on
+ * UART operation and should be ignored if 7816E is not set/enabled. This
+ * register may be read or written at anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_IS7816 register
+ */
+/*@{*/
+#define UART_RD_IS7816(base)     (UART_IS7816_REG(base))
+#define UART_WR_IS7816(base, value) (UART_IS7816_REG(base) = (value))
+#define UART_RMW_IS7816(base, mask, value) (UART_WR_IS7816(base, (UART_RD_IS7816(base) & ~(mask)) | (value)))
+#define UART_SET_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) |  (value)))
+#define UART_CLR_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) & ~(value)))
+#define UART_TOG_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IS7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IS7816, field RXT[0] (W1C)
+ *
+ * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
+ * generated in response to parity errors on received data. This flag requires ANACK
+ * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
+ * Clearing this field also resets the counter keeping track of consecutive NACKS. The
+ * UART will continue to attempt to receive data regardless of whether this flag
+ * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
+ * or packet is received without needing to issue a NACK, the internal NACK
+ * detection counter is cleared and the count restarts from zero on the next
+ * transmitted NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - The number of consecutive NACKS generated as a result of parity
+ *     errors and buffer overruns is less than or equal to the value in
+ *     ET7816[RXTHRESHOLD].
+ * - 0b1 - The number of consecutive NACKS generated as a result of parity
+ *     errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_RXT field. */
+#define UART_RD_IS7816_RXT(base) ((UART_IS7816_REG(base) & UART_IS7816_RXT_MASK) >> UART_IS7816_RXT_SHIFT)
+#define UART_BRD_IS7816_RXT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT))
+
+/*! @brief Set the RXT field to a new value. */
+#define UART_WR_IS7816_RXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_RXT(value)))
+#define UART_BWR_IS7816_RXT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field TXT[1] (W1C)
+ *
+ * Indicates that the transmit NACK threshold has been exceeded as indicated by
+ * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
+ * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
+ * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
+ * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
+ * internal NACK detection counter is cleared and the count restarts from zero on
+ * the next received NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - The number of retries and corresponding NACKS does not exceed the
+ *     value in ET7816[TXTHRESHOLD].
+ * - 0b1 - The number of retries and corresponding NACKS exceeds the value in
+ *     ET7816[TXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_TXT field. */
+#define UART_RD_IS7816_TXT(base) ((UART_IS7816_REG(base) & UART_IS7816_TXT_MASK) >> UART_IS7816_TXT_SHIFT)
+#define UART_BRD_IS7816_TXT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT))
+
+/*! @brief Set the TXT field to a new value. */
+#define UART_WR_IS7816_TXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_TXT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_TXT(value)))
+#define UART_BWR_IS7816_TXT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field GTV[2] (W1C)
+ *
+ * Indicates that one or more of the character guard time, block guard time, or
+ * guard time are violated. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - A guard time (GT, CGT, or BGT) has not been violated.
+ * - 0b1 - A guard time (GT, CGT, or BGT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_GTV field. */
+#define UART_RD_IS7816_GTV(base) ((UART_IS7816_REG(base) & UART_IS7816_GTV_MASK) >> UART_IS7816_GTV_SHIFT)
+#define UART_BRD_IS7816_GTV(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT))
+
+/*! @brief Set the GTV field to a new value. */
+#define UART_WR_IS7816_GTV(base, value) (UART_RMW_IS7816(base, (UART_IS7816_GTV_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_GTV(value)))
+#define UART_BWR_IS7816_GTV(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field INITD[4] (W1C)
+ *
+ * Indicates that a valid initial character is received. This interrupt is
+ * cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - A valid initial character has not been received.
+ * - 0b1 - A valid initial character has been received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_INITD field. */
+#define UART_RD_IS7816_INITD(base) ((UART_IS7816_REG(base) & UART_IS7816_INITD_MASK) >> UART_IS7816_INITD_SHIFT)
+#define UART_BRD_IS7816_INITD(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT))
+
+/*! @brief Set the INITD field to a new value. */
+#define UART_WR_IS7816_INITD(base, value) (UART_RMW_IS7816(base, (UART_IS7816_INITD_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_INITD(value)))
+#define UART_BWR_IS7816_INITD(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field BWT[5] (W1C)
+ *
+ * Indicates that the block wait time, the time between the leading edge of
+ * first received character of a block and the leading edge of the last character the
+ * previously transmitted block, has exceeded the programmed value. This flag
+ * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - Block wait time (BWT) has not been violated.
+ * - 0b1 - Block wait time (BWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_BWT field. */
+#define UART_RD_IS7816_BWT(base) ((UART_IS7816_REG(base) & UART_IS7816_BWT_MASK) >> UART_IS7816_BWT_SHIFT)
+#define UART_BRD_IS7816_BWT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT))
+
+/*! @brief Set the BWT field to a new value. */
+#define UART_WR_IS7816_BWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_BWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_BWT(value)))
+#define UART_BWR_IS7816_BWT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field CWT[6] (W1C)
+ *
+ * Indicates that the character wait time, the time between the leading edges of
+ * two consecutive characters in a block, has exceeded the programmed value.
+ * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
+ * writing 1.
+ *
+ * Values:
+ * - 0b0 - Character wait time (CWT) has not been violated.
+ * - 0b1 - Character wait time (CWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_CWT field. */
+#define UART_RD_IS7816_CWT(base) ((UART_IS7816_REG(base) & UART_IS7816_CWT_MASK) >> UART_IS7816_CWT_SHIFT)
+#define UART_BRD_IS7816_CWT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT))
+
+/*! @brief Set the CWT field to a new value. */
+#define UART_WR_IS7816_CWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_CWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_CWT(value)))
+#define UART_BWR_IS7816_CWT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field WT[7] (W1C)
+ *
+ * Indicates that the wait time, the time between the leading edge of a
+ * character being transmitted and the leading edge of the next response character, has
+ * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
+ * This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - Wait time (WT) has not been violated.
+ * - 0b1 - Wait time (WT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_WT field. */
+#define UART_RD_IS7816_WT(base) ((UART_IS7816_REG(base) & UART_IS7816_WT_MASK) >> UART_IS7816_WT_SHIFT)
+#define UART_BRD_IS7816_WT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT))
+
+/*! @brief Set the WT field to a new value. */
+#define UART_WR_IS7816_WT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_WT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK), UART_IS7816_WT(value)))
+#define UART_BWR_IS7816_WT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816T0 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816T0 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816T0 register
+ */
+/*@{*/
+#define UART_RD_WP7816T0(base)   (UART_WP7816T0_REG(base))
+#define UART_WR_WP7816T0(base, value) (UART_WP7816T0_REG(base) = (value))
+#define UART_RMW_WP7816T0(base, mask, value) (UART_WR_WP7816T0(base, (UART_RD_WP7816T0(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) |  (value)))
+#define UART_CLR_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) & ~(value)))
+#define UART_TOG_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816T1 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816T1 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816T1 register
+ */
+/*@{*/
+#define UART_RD_WP7816T1(base)   (UART_WP7816T1_REG(base))
+#define UART_WR_WP7816T1(base, value) (UART_WP7816T1_REG(base) = (value))
+#define UART_RMW_WP7816T1(base, mask, value) (UART_WR_WP7816T1(base, (UART_RD_WP7816T1(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) |  (value)))
+#define UART_CLR_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) & ~(value)))
+#define UART_TOG_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_WP7816T1 bitfields
+ */
+
+/*!
+ * @name Register UART_WP7816T1, field BWI[3:0] (RW)
+ *
+ * Used to calculate the value used for the BWT counter. It represent a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816T1_BWI field. */
+#define UART_RD_WP7816T1_BWI(base) ((UART_WP7816T1_REG(base) & UART_WP7816T1_BWI_MASK) >> UART_WP7816T1_BWI_SHIFT)
+#define UART_BRD_WP7816T1_BWI(base) (UART_RD_WP7816T1_BWI(base))
+
+/*! @brief Set the BWI field to a new value. */
+#define UART_WR_WP7816T1_BWI(base, value) (UART_RMW_WP7816T1(base, UART_WP7816T1_BWI_MASK, UART_WP7816T1_BWI(value)))
+#define UART_BWR_WP7816T1_BWI(base, value) (UART_WR_WP7816T1_BWI(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_WP7816T1, field CWI[7:4] (RW)
+ *
+ * Used to calculate the value used for the CWT counter. It represents a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816T1_CWI field. */
+#define UART_RD_WP7816T1_CWI(base) ((UART_WP7816T1_REG(base) & UART_WP7816T1_CWI_MASK) >> UART_WP7816T1_CWI_SHIFT)
+#define UART_BRD_WP7816T1_CWI(base) (UART_RD_WP7816T1_CWI(base))
+
+/*! @brief Set the CWI field to a new value. */
+#define UART_WR_WP7816T1_CWI(base, value) (UART_RMW_WP7816T1(base, UART_WP7816T1_CWI_MASK, UART_WP7816T1_CWI(value)))
+#define UART_BWR_WP7816T1_CWI(base, value) (UART_WR_WP7816T1_CWI(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WN7816 - UART 7816 Wait N Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WN7816 - UART 7816 Wait N Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The WN7816 register contains a parameter that is used in the calculation of
+ * the guard time counter. This register may be read at any time. This register
+ * must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WN7816 register
+ */
+/*@{*/
+#define UART_RD_WN7816(base)     (UART_WN7816_REG(base))
+#define UART_WR_WN7816(base, value) (UART_WN7816_REG(base) = (value))
+#define UART_RMW_WN7816(base, mask, value) (UART_WR_WN7816(base, (UART_RD_WN7816(base) & ~(mask)) | (value)))
+#define UART_SET_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) |  (value)))
+#define UART_CLR_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) & ~(value)))
+#define UART_TOG_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WF7816 - UART 7816 Wait FD Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WF7816 - UART 7816 Wait FD Register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * The WF7816 contains parameters that are used in the generation of various
+ * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WF7816 register
+ */
+/*@{*/
+#define UART_RD_WF7816(base)     (UART_WF7816_REG(base))
+#define UART_WR_WF7816(base, value) (UART_WF7816_REG(base) = (value))
+#define UART_RMW_WF7816(base, mask, value) (UART_WR_WF7816(base, (UART_RD_WF7816(base) & ~(mask)) | (value)))
+#define UART_SET_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) |  (value)))
+#define UART_CLR_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) & ~(value)))
+#define UART_TOG_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ET7816 - UART 7816 Error Threshold Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ET7816 - UART 7816 Error Threshold Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The ET7816 register contains fields that determine the number of NACKs that
+ * must be received or transmitted before the host processor is notified. This
+ * register may be read at anytime. This register must be written to only when
+ * C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_ET7816 register
+ */
+/*@{*/
+#define UART_RD_ET7816(base)     (UART_ET7816_REG(base))
+#define UART_WR_ET7816(base, value) (UART_ET7816_REG(base) = (value))
+#define UART_RMW_ET7816(base, mask, value) (UART_WR_ET7816(base, (UART_RD_ET7816(base) & ~(mask)) | (value)))
+#define UART_SET_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) |  (value)))
+#define UART_CLR_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) & ~(value)))
+#define UART_TOG_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ET7816 bitfields
+ */
+
+/*!
+ * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
+ *
+ * The value written to this field indicates the maximum number of consecutive
+ * NACKs generated as a result of a parity error or receiver buffer overruns
+ * before the host processor is notified. After the counter exceeds that value in the
+ * field, the IS7816[RXT] is asserted. This field is meaningful only when
+ * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
+ * NACKs that have been transmitted since the last successful reception. This
+ * counter saturates at 4'hF and does not wrap around. Regardless of the number of
+ * NACKs sent, the UART continues to receive valid packets indefinitely. For
+ * additional information, see IS7816[RXT] field description.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */
+#define UART_RD_ET7816_RXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_RXTHRESHOLD_MASK) >> UART_ET7816_RXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_RXTHRESHOLD(base) (UART_RD_ET7816_RXTHRESHOLD(base))
+
+/*! @brief Set the RXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_RXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_RXTHRESHOLD_MASK, UART_ET7816_RXTHRESHOLD(value)))
+#define UART_BWR_ET7816_RXTHRESHOLD(base, value) (UART_WR_ET7816_RXTHRESHOLD(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
+ *
+ * The value written to this field indicates the maximum number of failed
+ * attempts (NACKs) a transmitted character can have before the host processor is
+ * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
+ * The value read from this field represents the number of consecutive NACKs
+ * that have been received since the last successful transmission. This counter
+ * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
+ * received, the UART continues to retransmit indefinitely. This flag only
+ * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
+ * description.
+ *
+ * Values:
+ * - 0b0000 - TXT asserts on the first NACK that is received.
+ * - 0b0001 - TXT asserts on the second NACK that is received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */
+#define UART_RD_ET7816_TXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_TXTHRESHOLD_MASK) >> UART_ET7816_TXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_TXTHRESHOLD(base) (UART_RD_ET7816_TXTHRESHOLD(base))
+
+/*! @brief Set the TXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_TXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_TXTHRESHOLD_MASK, UART_ET7816_TXTHRESHOLD(value)))
+#define UART_BWR_ET7816_TXTHRESHOLD(base, value) (UART_WR_ET7816_TXTHRESHOLD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TL7816 - UART 7816 Transmit Length Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TL7816 - UART 7816 Transmit Length Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The TL7816 register is used to indicate the number of characters contained in
+ * the block being transmitted. This register is used only when C7816[TTYPE] =
+ * 1. This register may be read at anytime. This register must be written only
+ * when C2[TE] is not enabled.
+ */
+/*!
+ * @name Constants and macros for entire UART_TL7816 register
+ */
+/*@{*/
+#define UART_RD_TL7816(base)     (UART_TL7816_REG(base))
+#define UART_WR_TL7816(base, value) (UART_TL7816_REG(base) = (value))
+#define UART_RMW_TL7816(base, mask, value) (UART_WR_TL7816(base, (UART_RD_TL7816(base) & ~(mask)) | (value)))
+#define UART_SET_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) |  (value)))
+#define UART_CLR_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) & ~(value)))
+#define UART_TOG_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 USB
+ *
+ * Universal Serial Bus, OTG Capable Controller
+ *
+ * Registers defined in this header file:
+ * - USB_PERID - Peripheral ID register
+ * - USB_IDCOMP - Peripheral ID Complement register
+ * - USB_REV - Peripheral Revision register
+ * - USB_ADDINFO - Peripheral Additional Info register
+ * - USB_OTGISTAT - OTG Interrupt Status register
+ * - USB_OTGICR - OTG Interrupt Control register
+ * - USB_OTGSTAT - OTG Status register
+ * - USB_OTGCTL - OTG Control register
+ * - USB_ISTAT - Interrupt Status register
+ * - USB_INTEN - Interrupt Enable register
+ * - USB_ERRSTAT - Error Interrupt Status register
+ * - USB_ERREN - Error Interrupt Enable register
+ * - USB_STAT - Status register
+ * - USB_CTL - Control register
+ * - USB_ADDR - Address register
+ * - USB_BDTPAGE1 - BDT Page register 1
+ * - USB_FRMNUML - Frame Number register Low
+ * - USB_FRMNUMH - Frame Number register High
+ * - USB_TOKEN - Token register
+ * - USB_SOFTHLD - SOF Threshold register
+ * - USB_BDTPAGE2 - BDT Page Register 2
+ * - USB_BDTPAGE3 - BDT Page Register 3
+ * - USB_ENDPT - Endpoint Control register
+ * - USB_USBCTRL - USB Control register
+ * - USB_OBSERVE - USB OTG Observe register
+ * - USB_CONTROL - USB OTG Control register
+ * - USB_USBTRC0 - USB Transceiver Control register 0
+ * - USB_USBFRMADJUST - Frame Adjust Register
+ * - USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ * - USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ * - USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ */
+
+#define USB_INSTANCE_COUNT (1U) /*!< Number of instances of the USB module. */
+#define USB0_IDX (0U) /*!< Instance number for USB0. */
+
+/*******************************************************************************
+ * USB_PERID - Peripheral ID register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_PERID - Peripheral ID register (RO)
+ *
+ * Reset value: 0x04U
+ *
+ * Reads back the value of 0x04. This value is defined for the USB peripheral.
+ */
+/*!
+ * @name Constants and macros for entire USB_PERID register
+ */
+/*@{*/
+#define USB_RD_PERID(base)       (USB_PERID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_PERID bitfields
+ */
+
+/*!
+ * @name Register USB_PERID, field ID[5:0] (RO)
+ *
+ * This field always reads 0x4h.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_PERID_ID field. */
+#define USB_RD_PERID_ID(base) ((USB_PERID_REG(base) & USB_PERID_ID_MASK) >> USB_PERID_ID_SHIFT)
+#define USB_BRD_PERID_ID(base) (USB_RD_PERID_ID(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_IDCOMP - Peripheral ID Complement register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_IDCOMP - Peripheral ID Complement register (RO)
+ *
+ * Reset value: 0xFBU
+ *
+ * Reads back the complement of the Peripheral ID register. For the USB
+ * peripheral, the value is 0xFB.
+ */
+/*!
+ * @name Constants and macros for entire USB_IDCOMP register
+ */
+/*@{*/
+#define USB_RD_IDCOMP(base)      (USB_IDCOMP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_IDCOMP bitfields
+ */
+
+/*!
+ * @name Register USB_IDCOMP, field NID[5:0] (RO)
+ *
+ * Ones' complement of PERID[ID]. bits.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_IDCOMP_NID field. */
+#define USB_RD_IDCOMP_NID(base) ((USB_IDCOMP_REG(base) & USB_IDCOMP_NID_MASK) >> USB_IDCOMP_NID_SHIFT)
+#define USB_BRD_IDCOMP_NID(base) (USB_RD_IDCOMP_NID(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_REV - Peripheral Revision register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_REV - Peripheral Revision register (RO)
+ *
+ * Reset value: 0x33U
+ *
+ * Contains the revision number of the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_REV register
+ */
+/*@{*/
+#define USB_RD_REV(base)         (USB_REV_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDINFO - Peripheral Additional Info register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDINFO - Peripheral Additional Info register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with
+ * the Host Enable bit.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDINFO register
+ */
+/*@{*/
+#define USB_RD_ADDINFO(base)     (USB_ADDINFO_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDINFO bitfields
+ */
+
+/*!
+ * @name Register USB_ADDINFO, field IEHOST[0] (RO)
+ *
+ * This bit is set if host mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IEHOST field. */
+#define USB_RD_ADDINFO_IEHOST(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IEHOST_MASK) >> USB_ADDINFO_IEHOST_SHIFT)
+#define USB_BRD_ADDINFO_IEHOST(base) (BITBAND_ACCESS8(&USB_ADDINFO_REG(base), USB_ADDINFO_IEHOST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_ADDINFO, field IRQNUM[7:3] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IRQNUM field. */
+#define USB_RD_ADDINFO_IRQNUM(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IRQNUM_MASK) >> USB_ADDINFO_IRQNUM_SHIFT)
+#define USB_BRD_ADDINFO_IRQNUM(base) (USB_RD_ADDINFO_IRQNUM(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGISTAT - OTG Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGISTAT - OTG Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Records changes of the ID sense and VBUS signals. Software can read this
+ * register to determine the event that triggers an interrupt. Only bits that have
+ * changed since the last software read are set. Writing a one to a bit clears the
+ * associated interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGISTAT register
+ */
+/*@{*/
+#define USB_RD_OTGISTAT(base)    (USB_OTGISTAT_REG(base))
+#define USB_WR_OTGISTAT(base, value) (USB_OTGISTAT_REG(base) = (value))
+#define USB_RMW_OTGISTAT(base, mask, value) (USB_WR_OTGISTAT(base, (USB_RD_OTGISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) |  (value)))
+#define USB_CLR_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) & ~(value)))
+#define USB_TOG_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on an A device.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field. */
+#define USB_RD_OTGISTAT_AVBUSCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_AVBUSCHG_MASK) >> USB_OTGISTAT_AVBUSCHG_SHIFT)
+#define USB_BRD_OTGISTAT_AVBUSCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_AVBUSCHG_SHIFT))
+
+/*! @brief Set the AVBUSCHG field to a new value. */
+#define USB_WR_OTGISTAT_AVBUSCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_AVBUSCHG_MASK, USB_OTGISTAT_AVBUSCHG(value)))
+#define USB_BWR_OTGISTAT_AVBUSCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_AVBUSCHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on a B device.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field. */
+#define USB_RD_OTGISTAT_B_SESS_CHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_B_SESS_CHG_MASK) >> USB_OTGISTAT_B_SESS_CHG_SHIFT)
+#define USB_BRD_OTGISTAT_B_SESS_CHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_B_SESS_CHG_SHIFT))
+
+/*! @brief Set the B_SESS_CHG field to a new value. */
+#define USB_WR_OTGISTAT_B_SESS_CHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_B_SESS_CHG_MASK, USB_OTGISTAT_B_SESS_CHG(value)))
+#define USB_BWR_OTGISTAT_B_SESS_CHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_B_SESS_CHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW)
+ *
+ * This bit is set when a change in VBUS is detected indicating a session valid
+ * or a session no longer valid.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field. */
+#define USB_RD_OTGISTAT_SESSVLDCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_SESSVLDCHG_MASK) >> USB_OTGISTAT_SESSVLDCHG_SHIFT)
+#define USB_BRD_OTGISTAT_SESSVLDCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_SESSVLDCHG_SHIFT))
+
+/*! @brief Set the SESSVLDCHG field to a new value. */
+#define USB_WR_OTGISTAT_SESSVLDCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_SESSVLDCHG_MASK, USB_OTGISTAT_SESSVLDCHG(value)))
+#define USB_BWR_OTGISTAT_SESSVLDCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_SESSVLDCHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW)
+ *
+ * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits)
+ * are stable without change for 1 millisecond, and the value of the line state
+ * is different from the last time when the line state was stable. It is set on
+ * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
+ * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt
+ * can be used in detecting Reset, Resume, Connect, and Data Line Pulse
+ * signaling.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field. */
+#define USB_RD_OTGISTAT_LINE_STATE_CHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_LINE_STATE_CHG_MASK) >> USB_OTGISTAT_LINE_STATE_CHG_SHIFT)
+#define USB_BRD_OTGISTAT_LINE_STATE_CHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_LINE_STATE_CHG_SHIFT))
+
+/*! @brief Set the LINE_STATE_CHG field to a new value. */
+#define USB_WR_OTGISTAT_LINE_STATE_CHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_LINE_STATE_CHG_MASK, USB_OTGISTAT_LINE_STATE_CHG(value)))
+#define USB_BWR_OTGISTAT_LINE_STATE_CHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_LINE_STATE_CHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW)
+ *
+ * This bit is set when the 1 millisecond timer expires. This bit stays asserted
+ * until cleared by software. The interrupt must be serviced every millisecond
+ * to avoid losing 1msec counts.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_ONEMSEC field. */
+#define USB_RD_OTGISTAT_ONEMSEC(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_ONEMSEC_MASK) >> USB_OTGISTAT_ONEMSEC_SHIFT)
+#define USB_BRD_OTGISTAT_ONEMSEC(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_ONEMSEC_SHIFT))
+
+/*! @brief Set the ONEMSEC field to a new value. */
+#define USB_WR_OTGISTAT_ONEMSEC(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_ONEMSEC_MASK, USB_OTGISTAT_ONEMSEC(value)))
+#define USB_BWR_OTGISTAT_ONEMSEC(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_ONEMSEC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field IDCHG[7] (RW)
+ *
+ * This bit is set when a change in the ID Signal from the USB connector is
+ * sensed.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_IDCHG field. */
+#define USB_RD_OTGISTAT_IDCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_IDCHG_MASK) >> USB_OTGISTAT_IDCHG_SHIFT)
+#define USB_BRD_OTGISTAT_IDCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_IDCHG_SHIFT))
+
+/*! @brief Set the IDCHG field to a new value. */
+#define USB_WR_OTGISTAT_IDCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_IDCHG_MASK, USB_OTGISTAT_IDCHG(value)))
+#define USB_BWR_OTGISTAT_IDCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_IDCHG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGICR - OTG Interrupt Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGICR - OTG Interrupt Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Enables the corresponding interrupt status bits defined in the OTG Interrupt
+ * Status Register.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGICR register
+ */
+/*@{*/
+#define USB_RD_OTGICR(base)      (USB_OTGICR_REG(base))
+#define USB_WR_OTGICR(base, value) (USB_OTGICR_REG(base) = (value))
+#define USB_RMW_OTGICR(base, mask, value) (USB_WR_OTGICR(base, (USB_RD_OTGICR(base) & ~(mask)) | (value)))
+#define USB_SET_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) |  (value)))
+#define USB_CLR_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) & ~(value)))
+#define USB_TOG_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGICR bitfields
+ */
+
+/*!
+ * @name Register USB_OTGICR, field AVBUSEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the AVBUSCHG interrupt.
+ * - 0b1 - Enables the AVBUSCHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_AVBUSEN field. */
+#define USB_RD_OTGICR_AVBUSEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_AVBUSEN_MASK) >> USB_OTGICR_AVBUSEN_SHIFT)
+#define USB_BRD_OTGICR_AVBUSEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_AVBUSEN_SHIFT))
+
+/*! @brief Set the AVBUSEN field to a new value. */
+#define USB_WR_OTGICR_AVBUSEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_AVBUSEN_MASK, USB_OTGICR_AVBUSEN(value)))
+#define USB_BWR_OTGICR_AVBUSEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_AVBUSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field BSESSEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the B_SESS_CHG interrupt.
+ * - 0b1 - Enables the B_SESS_CHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_BSESSEN field. */
+#define USB_RD_OTGICR_BSESSEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_BSESSEN_MASK) >> USB_OTGICR_BSESSEN_SHIFT)
+#define USB_BRD_OTGICR_BSESSEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_BSESSEN_SHIFT))
+
+/*! @brief Set the BSESSEN field to a new value. */
+#define USB_WR_OTGICR_BSESSEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_BSESSEN_MASK, USB_OTGICR_BSESSEN(value)))
+#define USB_BWR_OTGICR_BSESSEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_BSESSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field SESSVLDEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the SESSVLDCHG interrupt.
+ * - 0b1 - Enables the SESSVLDCHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_SESSVLDEN field. */
+#define USB_RD_OTGICR_SESSVLDEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_SESSVLDEN_MASK) >> USB_OTGICR_SESSVLDEN_SHIFT)
+#define USB_BRD_OTGICR_SESSVLDEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_SESSVLDEN_SHIFT))
+
+/*! @brief Set the SESSVLDEN field to a new value. */
+#define USB_WR_OTGICR_SESSVLDEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_SESSVLDEN_MASK, USB_OTGICR_SESSVLDEN(value)))
+#define USB_BWR_OTGICR_SESSVLDEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_SESSVLDEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field LINESTATEEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the LINE_STAT_CHG interrupt.
+ * - 0b1 - Enables the LINE_STAT_CHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_LINESTATEEN field. */
+#define USB_RD_OTGICR_LINESTATEEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_LINESTATEEN_MASK) >> USB_OTGICR_LINESTATEEN_SHIFT)
+#define USB_BRD_OTGICR_LINESTATEEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_LINESTATEEN_SHIFT))
+
+/*! @brief Set the LINESTATEEN field to a new value. */
+#define USB_WR_OTGICR_LINESTATEEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_LINESTATEEN_MASK, USB_OTGICR_LINESTATEEN(value)))
+#define USB_BWR_OTGICR_LINESTATEEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_LINESTATEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field ONEMSECEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Diables the 1ms timer interrupt.
+ * - 0b1 - Enables the 1ms timer interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_ONEMSECEN field. */
+#define USB_RD_OTGICR_ONEMSECEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_ONEMSECEN_MASK) >> USB_OTGICR_ONEMSECEN_SHIFT)
+#define USB_BRD_OTGICR_ONEMSECEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_ONEMSECEN_SHIFT))
+
+/*! @brief Set the ONEMSECEN field to a new value. */
+#define USB_WR_OTGICR_ONEMSECEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_ONEMSECEN_MASK, USB_OTGICR_ONEMSECEN(value)))
+#define USB_BWR_OTGICR_ONEMSECEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_ONEMSECEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field IDEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The ID interrupt is disabled
+ * - 0b1 - The ID interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_IDEN field. */
+#define USB_RD_OTGICR_IDEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_IDEN_MASK) >> USB_OTGICR_IDEN_SHIFT)
+#define USB_BRD_OTGICR_IDEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_IDEN_SHIFT))
+
+/*! @brief Set the IDEN field to a new value. */
+#define USB_WR_OTGICR_IDEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_IDEN_MASK, USB_OTGICR_IDEN(value)))
+#define USB_BWR_OTGICR_IDEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_IDEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGSTAT - OTG Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGSTAT - OTG Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Displays the actual value from the external comparator outputs of the ID pin
+ * and VBUS.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGSTAT register
+ */
+/*@{*/
+#define USB_RD_OTGSTAT(base)     (USB_OTGSTAT_REG(base))
+#define USB_WR_OTGSTAT(base, value) (USB_OTGSTAT_REG(base) = (value))
+#define USB_RMW_OTGSTAT(base, mask, value) (USB_WR_OTGSTAT(base, (USB_RD_OTGSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) |  (value)))
+#define USB_CLR_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) & ~(value)))
+#define USB_TOG_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is below the A VBUS Valid threshold.
+ * - 0b1 - The VBUS voltage is above the A VBUS Valid threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field. */
+#define USB_RD_OTGSTAT_AVBUSVLD(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_AVBUSVLD_MASK) >> USB_OTGSTAT_AVBUSVLD_SHIFT)
+#define USB_BRD_OTGSTAT_AVBUSVLD(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_AVBUSVLD_SHIFT))
+
+/*! @brief Set the AVBUSVLD field to a new value. */
+#define USB_WR_OTGSTAT_AVBUSVLD(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_AVBUSVLD_MASK, USB_OTGSTAT_AVBUSVLD(value)))
+#define USB_BWR_OTGSTAT_AVBUSVLD(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_AVBUSVLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field BSESSEND[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is above the B session end threshold.
+ * - 0b1 - The VBUS voltage is below the B session end threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_BSESSEND field. */
+#define USB_RD_OTGSTAT_BSESSEND(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_BSESSEND_MASK) >> USB_OTGSTAT_BSESSEND_SHIFT)
+#define USB_BRD_OTGSTAT_BSESSEND(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_BSESSEND_SHIFT))
+
+/*! @brief Set the BSESSEND field to a new value. */
+#define USB_WR_OTGSTAT_BSESSEND(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_BSESSEND_MASK, USB_OTGSTAT_BSESSEND(value)))
+#define USB_BWR_OTGSTAT_BSESSEND(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_BSESSEND_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is below the B session valid threshold
+ * - 0b1 - The VBUS voltage is above the B session valid threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_SESS_VLD field. */
+#define USB_RD_OTGSTAT_SESS_VLD(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_SESS_VLD_MASK) >> USB_OTGSTAT_SESS_VLD_SHIFT)
+#define USB_BRD_OTGSTAT_SESS_VLD(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_SESS_VLD_SHIFT))
+
+/*! @brief Set the SESS_VLD field to a new value. */
+#define USB_WR_OTGSTAT_SESS_VLD(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_SESS_VLD_MASK, USB_OTGSTAT_SESS_VLD(value)))
+#define USB_BWR_OTGSTAT_SESS_VLD(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_SESS_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
+ *
+ * Indicates that the internal signals that control the LINE_STATE_CHG field of
+ * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG
+ * field and then read this field. If this field reads as 1, then the value of
+ * LINE_STATE_CHG can be considered stable.
+ *
+ * Values:
+ * - 0b0 - The LINE_STAT_CHG bit is not yet stable.
+ * - 0b1 - The LINE_STAT_CHG bit has been debounced and is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field. */
+#define USB_RD_OTGSTAT_LINESTATESTABLE(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_LINESTATESTABLE_MASK) >> USB_OTGSTAT_LINESTATESTABLE_SHIFT)
+#define USB_BRD_OTGSTAT_LINESTATESTABLE(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_LINESTATESTABLE_SHIFT))
+
+/*! @brief Set the LINESTATESTABLE field to a new value. */
+#define USB_WR_OTGSTAT_LINESTATESTABLE(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_LINESTATESTABLE_MASK, USB_OTGSTAT_LINESTATESTABLE(value)))
+#define USB_BWR_OTGSTAT_LINESTATESTABLE(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_LINESTATESTABLE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW)
+ *
+ * This bit is reserved for the 1ms count, but it is not useful to software.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field. */
+#define USB_RD_OTGSTAT_ONEMSECEN(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_ONEMSECEN_MASK) >> USB_OTGSTAT_ONEMSECEN_SHIFT)
+#define USB_BRD_OTGSTAT_ONEMSECEN(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ONEMSECEN_SHIFT))
+
+/*! @brief Set the ONEMSECEN field to a new value. */
+#define USB_WR_OTGSTAT_ONEMSECEN(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_ONEMSECEN_MASK, USB_OTGSTAT_ONEMSECEN(value)))
+#define USB_BWR_OTGSTAT_ONEMSECEN(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ONEMSECEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field ID[7] (RW)
+ *
+ * Indicates the current state of the ID pin on the USB connector
+ *
+ * Values:
+ * - 0b0 - Indicates a Type A cable is plugged into the USB connector.
+ * - 0b1 - Indicates no cable is attached or a Type B cable is plugged into the
+ *     USB connector.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_ID field. */
+#define USB_RD_OTGSTAT_ID(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_ID_MASK) >> USB_OTGSTAT_ID_SHIFT)
+#define USB_BRD_OTGSTAT_ID(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ID_SHIFT))
+
+/*! @brief Set the ID field to a new value. */
+#define USB_WR_OTGSTAT_ID(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_ID_MASK, USB_OTGSTAT_ID(value)))
+#define USB_BWR_OTGSTAT_ID(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ID_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGCTL - OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGCTL - OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Controls the operation of VBUS and Data Line termination resistors.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGCTL register
+ */
+/*@{*/
+#define USB_RD_OTGCTL(base)      (USB_OTGCTL_REG(base))
+#define USB_WR_OTGCTL(base, value) (USB_OTGCTL_REG(base) = (value))
+#define USB_RMW_OTGCTL(base, mask, value) (USB_WR_OTGCTL(base, (USB_RD_OTGCTL(base) & ~(mask)) | (value)))
+#define USB_SET_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) |  (value)))
+#define USB_CLR_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) & ~(value)))
+#define USB_TOG_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGCTL bitfields
+ */
+
+/*!
+ * @name Register USB_OTGCTL, field OTGEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then
+ *     the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+
+ *     and D- Data Line pull-down resistors are engaged.
+ * - 0b1 - The pull-up and pull-down controls in this register are used.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_OTGEN field. */
+#define USB_RD_OTGCTL_OTGEN(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_OTGEN_MASK) >> USB_OTGCTL_OTGEN_SHIFT)
+#define USB_BRD_OTGCTL_OTGEN(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_OTGEN_SHIFT))
+
+/*! @brief Set the OTGEN field to a new value. */
+#define USB_WR_OTGCTL_OTGEN(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_OTGEN_MASK, USB_OTGCTL_OTGEN(value)))
+#define USB_BWR_OTGCTL_OTGEN(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_OTGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DMLOW[4] (RW)
+ *
+ * Values:
+ * - 0b0 - D- pulldown resistor is not enabled.
+ * - 0b1 - D- pulldown resistor is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DMLOW field. */
+#define USB_RD_OTGCTL_DMLOW(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DMLOW_MASK) >> USB_OTGCTL_DMLOW_SHIFT)
+#define USB_BRD_OTGCTL_DMLOW(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DMLOW_SHIFT))
+
+/*! @brief Set the DMLOW field to a new value. */
+#define USB_WR_OTGCTL_DMLOW(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DMLOW_MASK, USB_OTGCTL_DMLOW(value)))
+#define USB_BWR_OTGCTL_DMLOW(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DMLOW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DPLOW[5] (RW)
+ *
+ * This bit should always be enabled together with bit 4 (DMLOW)
+ *
+ * Values:
+ * - 0b0 - D+ pulldown resistor is not enabled.
+ * - 0b1 - D+ pulldown resistor is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPLOW field. */
+#define USB_RD_OTGCTL_DPLOW(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPLOW_MASK) >> USB_OTGCTL_DPLOW_SHIFT)
+#define USB_BRD_OTGCTL_DPLOW(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPLOW_SHIFT))
+
+/*! @brief Set the DPLOW field to a new value. */
+#define USB_WR_OTGCTL_DPLOW(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPLOW_MASK, USB_OTGCTL_DPLOW(value)))
+#define USB_BWR_OTGCTL_DPLOW(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPLOW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DPHIGH[7] (RW)
+ *
+ * Values:
+ * - 0b0 - D+ pullup resistor is not enabled
+ * - 0b1 - D+ pullup resistor is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPHIGH field. */
+#define USB_RD_OTGCTL_DPHIGH(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPHIGH_MASK) >> USB_OTGCTL_DPHIGH_SHIFT)
+#define USB_BRD_OTGCTL_DPHIGH(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT))
+
+/*! @brief Set the DPHIGH field to a new value. */
+#define USB_WR_OTGCTL_DPHIGH(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPHIGH_MASK, USB_OTGCTL_DPHIGH(value)))
+#define USB_BWR_OTGCTL_DPHIGH(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ISTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ISTAT - Interrupt Status register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains fields for each of the interrupt sources within the USB Module. Each
+ * of these fields are qualified with their respective interrupt enable bits.
+ * All fields of this register are logically OR'd together along with the OTG
+ * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the
+ * processor's interrupt controller. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ISTAT register
+ */
+/*@{*/
+#define USB_RD_ISTAT(base)       (USB_ISTAT_REG(base))
+#define USB_WR_ISTAT(base, value) (USB_ISTAT_REG(base) = (value))
+#define USB_RMW_ISTAT(base, mask, value) (USB_WR_ISTAT(base, (USB_RD_ISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) |  (value)))
+#define USB_CLR_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) & ~(value)))
+#define USB_TOG_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ISTAT, field USBRST[0] (W1C)
+ *
+ * This bit is set when the USB Module has decoded a valid USB reset. This
+ * informs the processor that it should write 0x00 into the address register and
+ * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5
+ * microseconds. It is not asserted again until the USB reset condition has been
+ * removed and then reasserted.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_USBRST field. */
+#define USB_RD_ISTAT_USBRST(base) ((USB_ISTAT_REG(base) & USB_ISTAT_USBRST_MASK) >> USB_ISTAT_USBRST_SHIFT)
+#define USB_BRD_ISTAT_USBRST(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT))
+
+/*! @brief Set the USBRST field to a new value. */
+#define USB_WR_ISTAT_USBRST(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_USBRST(value)))
+#define USB_BWR_ISTAT_USBRST(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ERROR[1] (W1C)
+ *
+ * This bit is set when any of the error conditions within Error Interrupt
+ * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register
+ * to determine the source of the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ERROR field. */
+#define USB_RD_ISTAT_ERROR(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ERROR_MASK) >> USB_ISTAT_ERROR_SHIFT)
+#define USB_BRD_ISTAT_ERROR(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT))
+
+/*! @brief Set the ERROR field to a new value. */
+#define USB_WR_ISTAT_ERROR(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ERROR_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ERROR(value)))
+#define USB_BWR_ISTAT_ERROR(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SOFTOK[2] (W1C)
+ *
+ * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In
+ * Host mode this field is set when the SOF threshold is reached, so that
+ * software can prepare for the next SOF.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SOFTOK field. */
+#define USB_RD_ISTAT_SOFTOK(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SOFTOK_MASK) >> USB_ISTAT_SOFTOK_SHIFT)
+#define USB_BRD_ISTAT_SOFTOK(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT))
+
+/*! @brief Set the SOFTOK field to a new value. */
+#define USB_WR_ISTAT_SOFTOK(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SOFTOK_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SOFTOK(value)))
+#define USB_BWR_ISTAT_SOFTOK(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field TOKDNE[3] (W1C)
+ *
+ * This bit is set when the current token being processed has completed. The
+ * processor must immediately read the STATUS (STAT) register to determine the
+ * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes
+ * STAT to be cleared or the STAT holding register to be loaded into the STAT
+ * register.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_TOKDNE field. */
+#define USB_RD_ISTAT_TOKDNE(base) ((USB_ISTAT_REG(base) & USB_ISTAT_TOKDNE_MASK) >> USB_ISTAT_TOKDNE_SHIFT)
+#define USB_BRD_ISTAT_TOKDNE(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT))
+
+/*! @brief Set the TOKDNE field to a new value. */
+#define USB_WR_ISTAT_TOKDNE(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_TOKDNE_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_TOKDNE(value)))
+#define USB_BWR_ISTAT_TOKDNE(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SLEEP[4] (W1C)
+ *
+ * This bit is set when the USB Module detects a constant idle on the USB bus
+ * for 3 ms. The sleep timer is reset by activity on the USB bus.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SLEEP field. */
+#define USB_RD_ISTAT_SLEEP(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SLEEP_MASK) >> USB_ISTAT_SLEEP_SHIFT)
+#define USB_BRD_ISTAT_SLEEP(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define USB_WR_ISTAT_SLEEP(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SLEEP_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SLEEP(value)))
+#define USB_BWR_ISTAT_SLEEP(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field RESUME[5] (W1C)
+ *
+ * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us.
+ * When not in suspend mode this interrupt must be disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_RESUME field. */
+#define USB_RD_ISTAT_RESUME(base) ((USB_ISTAT_REG(base) & USB_ISTAT_RESUME_MASK) >> USB_ISTAT_RESUME_SHIFT)
+#define USB_BRD_ISTAT_RESUME(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_ISTAT_RESUME(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_RESUME_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_RESUME(value)))
+#define USB_BWR_ISTAT_RESUME(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ATTACH[6] (W1C)
+ *
+ * This bit is set when the USB Module detects an attach of a USB device. This
+ * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a
+ * peripheral is now present and must be configured; it is asserted if there have
+ * been no transitions on the USB for 2.5 us and the current bus state is not SE0."
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ATTACH field. */
+#define USB_RD_ISTAT_ATTACH(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ATTACH_MASK) >> USB_ISTAT_ATTACH_SHIFT)
+#define USB_BRD_ISTAT_ATTACH(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ATTACH_SHIFT))
+
+/*! @brief Set the ATTACH field to a new value. */
+#define USB_WR_ISTAT_ATTACH(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ATTACH_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ATTACH(value)))
+#define USB_BWR_ISTAT_ATTACH(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ATTACH_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field STALL[7] (W1C)
+ *
+ * In Target mode this bit is asserted when a STALL handshake is sent by the
+ * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge
+ * during the handshake phase of a USB transaction.This interrupt can be used to
+ * determine whether the last USB transaction was completed successfully or
+ * stalled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_STALL field. */
+#define USB_RD_ISTAT_STALL(base) ((USB_ISTAT_REG(base) & USB_ISTAT_STALL_MASK) >> USB_ISTAT_STALL_SHIFT)
+#define USB_BRD_ISTAT_STALL(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT))
+
+/*! @brief Set the STALL field to a new value. */
+#define USB_WR_ISTAT_STALL(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_STALL_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK), USB_ISTAT_STALL(value)))
+#define USB_BWR_ISTAT_STALL(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_INTEN - Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_INTEN - Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable fields for each of the interrupt sources within the USB
+ * Module. Setting any of these bits enables the respective interrupt source in the
+ * ISTAT register. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_INTEN register
+ */
+/*@{*/
+#define USB_RD_INTEN(base)       (USB_INTEN_REG(base))
+#define USB_WR_INTEN(base, value) (USB_INTEN_REG(base) = (value))
+#define USB_RMW_INTEN(base, mask, value) (USB_WR_INTEN(base, (USB_RD_INTEN(base) & ~(mask)) | (value)))
+#define USB_SET_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) |  (value)))
+#define USB_CLR_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) & ~(value)))
+#define USB_TOG_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_INTEN bitfields
+ */
+
+/*!
+ * @name Register USB_INTEN, field USBRSTEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the USBRST interrupt.
+ * - 0b1 - Enables the USBRST interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_USBRSTEN field. */
+#define USB_RD_INTEN_USBRSTEN(base) ((USB_INTEN_REG(base) & USB_INTEN_USBRSTEN_MASK) >> USB_INTEN_USBRSTEN_SHIFT)
+#define USB_BRD_INTEN_USBRSTEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT))
+
+/*! @brief Set the USBRSTEN field to a new value. */
+#define USB_WR_INTEN_USBRSTEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_USBRSTEN_MASK, USB_INTEN_USBRSTEN(value)))
+#define USB_BWR_INTEN_USBRSTEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ERROREN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the ERROR interrupt.
+ * - 0b1 - Enables the ERROR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ERROREN field. */
+#define USB_RD_INTEN_ERROREN(base) ((USB_INTEN_REG(base) & USB_INTEN_ERROREN_MASK) >> USB_INTEN_ERROREN_SHIFT)
+#define USB_BRD_INTEN_ERROREN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT))
+
+/*! @brief Set the ERROREN field to a new value. */
+#define USB_WR_INTEN_ERROREN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ERROREN_MASK, USB_INTEN_ERROREN(value)))
+#define USB_BWR_INTEN_ERROREN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SOFTOKEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disbles the SOFTOK interrupt.
+ * - 0b1 - Enables the SOFTOK interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SOFTOKEN field. */
+#define USB_RD_INTEN_SOFTOKEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SOFTOKEN_MASK) >> USB_INTEN_SOFTOKEN_SHIFT)
+#define USB_BRD_INTEN_SOFTOKEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT))
+
+/*! @brief Set the SOFTOKEN field to a new value. */
+#define USB_WR_INTEN_SOFTOKEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SOFTOKEN_MASK, USB_INTEN_SOFTOKEN(value)))
+#define USB_BWR_INTEN_SOFTOKEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field TOKDNEEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the TOKDNE interrupt.
+ * - 0b1 - Enables the TOKDNE interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_TOKDNEEN field. */
+#define USB_RD_INTEN_TOKDNEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_TOKDNEEN_MASK) >> USB_INTEN_TOKDNEEN_SHIFT)
+#define USB_BRD_INTEN_TOKDNEEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT))
+
+/*! @brief Set the TOKDNEEN field to a new value. */
+#define USB_WR_INTEN_TOKDNEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_TOKDNEEN_MASK, USB_INTEN_TOKDNEEN(value)))
+#define USB_BWR_INTEN_TOKDNEEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SLEEPEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the SLEEP interrupt.
+ * - 0b1 - Enables the SLEEP interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SLEEPEN field. */
+#define USB_RD_INTEN_SLEEPEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SLEEPEN_MASK) >> USB_INTEN_SLEEPEN_SHIFT)
+#define USB_BRD_INTEN_SLEEPEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT))
+
+/*! @brief Set the SLEEPEN field to a new value. */
+#define USB_WR_INTEN_SLEEPEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SLEEPEN_MASK, USB_INTEN_SLEEPEN(value)))
+#define USB_BWR_INTEN_SLEEPEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field RESUMEEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the RESUME interrupt.
+ * - 0b1 - Enables the RESUME interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_RESUMEEN field. */
+#define USB_RD_INTEN_RESUMEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_RESUMEEN_MASK) >> USB_INTEN_RESUMEEN_SHIFT)
+#define USB_BRD_INTEN_RESUMEEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT))
+
+/*! @brief Set the RESUMEEN field to a new value. */
+#define USB_WR_INTEN_RESUMEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_RESUMEEN_MASK, USB_INTEN_RESUMEEN(value)))
+#define USB_BWR_INTEN_RESUMEEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ATTACHEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the ATTACH interrupt.
+ * - 0b1 - Enables the ATTACH interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ATTACHEN field. */
+#define USB_RD_INTEN_ATTACHEN(base) ((USB_INTEN_REG(base) & USB_INTEN_ATTACHEN_MASK) >> USB_INTEN_ATTACHEN_SHIFT)
+#define USB_BRD_INTEN_ATTACHEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ATTACHEN_SHIFT))
+
+/*! @brief Set the ATTACHEN field to a new value. */
+#define USB_WR_INTEN_ATTACHEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ATTACHEN_MASK, USB_INTEN_ATTACHEN(value)))
+#define USB_BWR_INTEN_ATTACHEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ATTACHEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field STALLEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Diasbles the STALL interrupt.
+ * - 0b1 - Enables the STALL interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_STALLEN field. */
+#define USB_RD_INTEN_STALLEN(base) ((USB_INTEN_REG(base) & USB_INTEN_STALLEN_MASK) >> USB_INTEN_STALLEN_SHIFT)
+#define USB_BRD_INTEN_STALLEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT))
+
+/*! @brief Set the STALLEN field to a new value. */
+#define USB_WR_INTEN_STALLEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_STALLEN_MASK, USB_INTEN_STALLEN(value)))
+#define USB_BWR_INTEN_STALLEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERRSTAT - Error Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERRSTAT - Error Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error sources within the USB Module.
+ * Each of these bits are qualified with their respective error enable bits. All
+ * bits of this register are logically OR'd together and the result placed in the
+ * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. Each bit is set
+ * as soon as the error condition is detected. Therefore, the interrupt does not
+ * typically correspond with the end of a token being processed. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERRSTAT register
+ */
+/*@{*/
+#define USB_RD_ERRSTAT(base)     (USB_ERRSTAT_REG(base))
+#define USB_WR_ERRSTAT(base, value) (USB_ERRSTAT_REG(base) = (value))
+#define USB_RMW_ERRSTAT(base, mask, value) (USB_WR_ERRSTAT(base, (USB_RD_ERRSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) |  (value)))
+#define USB_CLR_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) & ~(value)))
+#define USB_TOG_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERRSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ERRSTAT, field PIDERR[0] (W1C)
+ *
+ * This bit is set when the PID check field fails.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_PIDERR field. */
+#define USB_RD_ERRSTAT_PIDERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_PIDERR_MASK) >> USB_ERRSTAT_PIDERR_SHIFT)
+#define USB_BRD_ERRSTAT_PIDERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT))
+
+/*! @brief Set the PIDERR field to a new value. */
+#define USB_WR_ERRSTAT_PIDERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_PIDERR(value)))
+#define USB_BWR_ERRSTAT_PIDERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C)
+ *
+ * This error interrupt has two functions. When the USB Module is operating in
+ * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token
+ * packets generated by the host. If set the token packet was rejected due to a
+ * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this
+ * interrupt detects End Of Frame (EOF) error conditions. This occurs when the
+ * USB Module is transmitting or receiving data and the SOF counter reaches zero.
+ * This interrupt is useful when developing USB packet scheduling software to
+ * ensure that no USB transactions cross the start of the next frame.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC5EOF field. */
+#define USB_RD_ERRSTAT_CRC5EOF(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC5EOF_MASK) >> USB_ERRSTAT_CRC5EOF_SHIFT)
+#define USB_BRD_ERRSTAT_CRC5EOF(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5EOF_SHIFT))
+
+/*! @brief Set the CRC5EOF field to a new value. */
+#define USB_WR_ERRSTAT_CRC5EOF(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC5EOF(value)))
+#define USB_BWR_ERRSTAT_CRC5EOF(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5EOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC16[2] (W1C)
+ *
+ * This bit is set when a data packet is rejected due to a CRC16 error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC16 field. */
+#define USB_RD_ERRSTAT_CRC16(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC16_MASK) >> USB_ERRSTAT_CRC16_SHIFT)
+#define USB_BRD_ERRSTAT_CRC16(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT))
+
+/*! @brief Set the CRC16 field to a new value. */
+#define USB_WR_ERRSTAT_CRC16(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC16(value)))
+#define USB_BWR_ERRSTAT_CRC16(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DFN8[3] (W1C)
+ *
+ * This bit is set if the data field received was not 8 bits in length. USB
+ * Specification 1.0 requires that data fields be an integral number of bytes. If the
+ * data field was not an integral number of bytes, this bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DFN8 field. */
+#define USB_RD_ERRSTAT_DFN8(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DFN8_MASK) >> USB_ERRSTAT_DFN8_SHIFT)
+#define USB_BRD_ERRSTAT_DFN8(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT))
+
+/*! @brief Set the DFN8 field to a new value. */
+#define USB_WR_ERRSTAT_DFN8(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DFN8(value)))
+#define USB_BWR_ERRSTAT_DFN8(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTOERR[4] (W1C)
+ *
+ * This bit is set when a bus turnaround timeout error occurs. The USB module
+ * contains a bus turnaround timer that keeps track of the amount of time elapsed
+ * between the token and data phases of a SETUP or OUT TOKEN or the data and
+ * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the
+ * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTOERR field. */
+#define USB_RD_ERRSTAT_BTOERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTOERR_MASK) >> USB_ERRSTAT_BTOERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTOERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT))
+
+/*! @brief Set the BTOERR field to a new value. */
+#define USB_WR_ERRSTAT_BTOERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_BTOERR(value)))
+#define USB_BWR_ERRSTAT_BTOERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DMAERR[5] (W1C)
+ *
+ * This bit is set if the USB Module has requested a DMA access to read a new
+ * BDT but has not been given the bus before it needs to receive or transmit data.
+ * If processing a TX transfer this would cause a transmit data underflow
+ * condition. If processing a RX transfer this would cause a receive data overflow
+ * condition. This interrupt is useful when developing device arbitration hardware for
+ * the microprocessor and the USB module to minimize bus request and bus grant
+ * latency. This bit is also set if a data packet to or from the host is larger
+ * than the buffer size allocated in the BDT. In this case the data packet is
+ * truncated as it is put in buffer memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DMAERR field. */
+#define USB_RD_ERRSTAT_DMAERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DMAERR_MASK) >> USB_ERRSTAT_DMAERR_SHIFT)
+#define USB_BRD_ERRSTAT_DMAERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT))
+
+/*! @brief Set the DMAERR field to a new value. */
+#define USB_WR_ERRSTAT_DMAERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DMAERR(value)))
+#define USB_BWR_ERRSTAT_DMAERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTSERR[7] (W1C)
+ *
+ * This bit is set when a bit stuff error is detected. If set, the corresponding
+ * packet is rejected due to the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTSERR field. */
+#define USB_RD_ERRSTAT_BTSERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTSERR_MASK) >> USB_ERRSTAT_BTSERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTSERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT))
+
+/*! @brief Set the BTSERR field to a new value. */
+#define USB_WR_ERRSTAT_BTSERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTSERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK), USB_ERRSTAT_BTSERR(value)))
+#define USB_BWR_ERRSTAT_BTSERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERREN - Error Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERREN - Error Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error interrupt sources within the USB
+ * module. Setting any of these bits enables the respective interrupt source in
+ * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore,
+ * the interrupt does not typically correspond with the end of a token being
+ * processed. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERREN register
+ */
+/*@{*/
+#define USB_RD_ERREN(base)       (USB_ERREN_REG(base))
+#define USB_WR_ERREN(base, value) (USB_ERREN_REG(base) = (value))
+#define USB_RMW_ERREN(base, mask, value) (USB_WR_ERREN(base, (USB_RD_ERREN(base) & ~(mask)) | (value)))
+#define USB_SET_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) |  (value)))
+#define USB_CLR_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) & ~(value)))
+#define USB_TOG_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERREN bitfields
+ */
+
+/*!
+ * @name Register USB_ERREN, field PIDERREN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the PIDERR interrupt.
+ * - 0b1 - Enters the PIDERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_PIDERREN field. */
+#define USB_RD_ERREN_PIDERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_PIDERREN_MASK) >> USB_ERREN_PIDERREN_SHIFT)
+#define USB_BRD_ERREN_PIDERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT))
+
+/*! @brief Set the PIDERREN field to a new value. */
+#define USB_WR_ERREN_PIDERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_PIDERREN_MASK, USB_ERREN_PIDERREN(value)))
+#define USB_BWR_ERREN_PIDERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC5EOFEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the CRC5/EOF interrupt.
+ * - 0b1 - Enables the CRC5/EOF interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC5EOFEN field. */
+#define USB_RD_ERREN_CRC5EOFEN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC5EOFEN_MASK) >> USB_ERREN_CRC5EOFEN_SHIFT)
+#define USB_BRD_ERREN_CRC5EOFEN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT))
+
+/*! @brief Set the CRC5EOFEN field to a new value. */
+#define USB_WR_ERREN_CRC5EOFEN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC5EOFEN_MASK, USB_ERREN_CRC5EOFEN(value)))
+#define USB_BWR_ERREN_CRC5EOFEN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC16EN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the CRC16 interrupt.
+ * - 0b1 - Enables the CRC16 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC16EN field. */
+#define USB_RD_ERREN_CRC16EN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC16EN_MASK) >> USB_ERREN_CRC16EN_SHIFT)
+#define USB_BRD_ERREN_CRC16EN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT))
+
+/*! @brief Set the CRC16EN field to a new value. */
+#define USB_WR_ERREN_CRC16EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC16EN_MASK, USB_ERREN_CRC16EN(value)))
+#define USB_BWR_ERREN_CRC16EN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DFN8EN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the DFN8 interrupt.
+ * - 0b1 - Enables the DFN8 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DFN8EN field. */
+#define USB_RD_ERREN_DFN8EN(base) ((USB_ERREN_REG(base) & USB_ERREN_DFN8EN_MASK) >> USB_ERREN_DFN8EN_SHIFT)
+#define USB_BRD_ERREN_DFN8EN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT))
+
+/*! @brief Set the DFN8EN field to a new value. */
+#define USB_WR_ERREN_DFN8EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DFN8EN_MASK, USB_ERREN_DFN8EN(value)))
+#define USB_BWR_ERREN_DFN8EN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTOERREN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the BTOERR interrupt.
+ * - 0b1 - Enables the BTOERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTOERREN field. */
+#define USB_RD_ERREN_BTOERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTOERREN_MASK) >> USB_ERREN_BTOERREN_SHIFT)
+#define USB_BRD_ERREN_BTOERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT))
+
+/*! @brief Set the BTOERREN field to a new value. */
+#define USB_WR_ERREN_BTOERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTOERREN_MASK, USB_ERREN_BTOERREN(value)))
+#define USB_BWR_ERREN_BTOERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DMAERREN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the DMAERR interrupt.
+ * - 0b1 - Enables the DMAERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DMAERREN field. */
+#define USB_RD_ERREN_DMAERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_DMAERREN_MASK) >> USB_ERREN_DMAERREN_SHIFT)
+#define USB_BRD_ERREN_DMAERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT))
+
+/*! @brief Set the DMAERREN field to a new value. */
+#define USB_WR_ERREN_DMAERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DMAERREN_MASK, USB_ERREN_DMAERREN(value)))
+#define USB_BWR_ERREN_DMAERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTSERREN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the BTSERR interrupt.
+ * - 0b1 - Enables the BTSERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTSERREN field. */
+#define USB_RD_ERREN_BTSERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTSERREN_MASK) >> USB_ERREN_BTSERREN_SHIFT)
+#define USB_BRD_ERREN_BTSERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT))
+
+/*! @brief Set the BTSERREN field to a new value. */
+#define USB_WR_ERREN_BTSERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTSERREN_MASK, USB_ERREN_BTSERREN(value)))
+#define USB_BWR_ERREN_BTSERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_STAT - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_STAT - Status register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * Reports the transaction status within the USB module. When the processor's
+ * interrupt controller has received a TOKDNE, interrupt the Status Register must
+ * be read to determine the status of the previous endpoint communication. The
+ * data in the status register is valid when TOKDNE interrupt is asserted. The
+ * Status register is actually a read window into a status FIFO maintained by the USB
+ * module. When the USB module uses a BD, it updates the Status register. If
+ * another USB transaction is performed before the TOKDNE interrupt is serviced, the
+ * USB module stores the status of the next transaction in the STAT FIFO. Thus
+ * STAT is actually a four byte FIFO that allows the processor core to process one
+ * transaction while the SIE is processing the next transaction. Clearing the
+ * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents
+ * of the next STAT value. If the data in the STAT holding register is valid, the
+ * SIE immediately reasserts to TOKDNE interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_STAT register
+ */
+/*@{*/
+#define USB_RD_STAT(base)        (USB_STAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_STAT bitfields
+ */
+
+/*!
+ * @name Register USB_STAT, field ODD[2] (RO)
+ *
+ * This bit is set if the last buffer descriptor updated was in the odd bank of
+ * the BDT.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ODD field. */
+#define USB_RD_STAT_ODD(base) ((USB_STAT_REG(base) & USB_STAT_ODD_MASK) >> USB_STAT_ODD_SHIFT)
+#define USB_BRD_STAT_ODD(base) (BITBAND_ACCESS8(&USB_STAT_REG(base), USB_STAT_ODD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field TX[3] (RO)
+ *
+ * Values:
+ * - 0b0 - The most recent transaction was a receive operation.
+ * - 0b1 - The most recent transaction was a transmit operation.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_TX field. */
+#define USB_RD_STAT_TX(base) ((USB_STAT_REG(base) & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT)
+#define USB_BRD_STAT_TX(base) (BITBAND_ACCESS8(&USB_STAT_REG(base), USB_STAT_TX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field ENDP[7:4] (RO)
+ *
+ * This four-bit field encodes the endpoint address that received or transmitted
+ * the previous token. This allows the processor core to determine the BDT entry
+ * that was updated by the last USB transaction.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ENDP field. */
+#define USB_RD_STAT_ENDP(base) ((USB_STAT_REG(base) & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT)
+#define USB_BRD_STAT_ENDP(base) (USB_RD_STAT_ENDP(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CTL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CTL - Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides various control and configuration information for the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_CTL register
+ */
+/*@{*/
+#define USB_RD_CTL(base)         (USB_CTL_REG(base))
+#define USB_WR_CTL(base, value)  (USB_CTL_REG(base) = (value))
+#define USB_RMW_CTL(base, mask, value) (USB_WR_CTL(base, (USB_RD_CTL(base) & ~(mask)) | (value)))
+#define USB_SET_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) |  (value)))
+#define USB_CLR_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) & ~(value)))
+#define USB_TOG_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CTL bitfields
+ */
+
+/*!
+ * @name Register USB_CTL, field USBENSOFEN[0] (RW)
+ *
+ * Setting this bit enables the USB-FS to operate; clearing it disables the
+ * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs.
+ * Therefore, setting this bit resets much of the logic in the SIE. When host mode
+ * is enabled, clearing this bit causes the SIE to stop sending SOF tokens.
+ *
+ * Values:
+ * - 0b0 - Disables the USB Module.
+ * - 0b1 - Enables the USB Module.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_USBENSOFEN field. */
+#define USB_RD_CTL_USBENSOFEN(base) ((USB_CTL_REG(base) & USB_CTL_USBENSOFEN_MASK) >> USB_CTL_USBENSOFEN_SHIFT)
+#define USB_BRD_CTL_USBENSOFEN(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT))
+
+/*! @brief Set the USBENSOFEN field to a new value. */
+#define USB_WR_CTL_USBENSOFEN(base, value) (USB_RMW_CTL(base, USB_CTL_USBENSOFEN_MASK, USB_CTL_USBENSOFEN(value)))
+#define USB_BWR_CTL_USBENSOFEN(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field ODDRST[1] (RW)
+ *
+ * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which
+ * then specifies the EVEN BDT bank.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_ODDRST field. */
+#define USB_RD_CTL_ODDRST(base) ((USB_CTL_REG(base) & USB_CTL_ODDRST_MASK) >> USB_CTL_ODDRST_SHIFT)
+#define USB_BRD_CTL_ODDRST(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT))
+
+/*! @brief Set the ODDRST field to a new value. */
+#define USB_WR_CTL_ODDRST(base, value) (USB_RMW_CTL(base, USB_CTL_ODDRST_MASK, USB_CTL_ODDRST(value)))
+#define USB_BWR_CTL_ODDRST(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field RESUME[2] (RW)
+ *
+ * When set to 1 this bit enables the USB Module to execute resume signaling.
+ * This allows the USB Module to perform remote wake-up. Software must set RESUME
+ * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN
+ * bit is set, the USB module appends a Low Speed End of Packet to the Resume
+ * signaling when the RESUME bit is cleared. For more information on RESUME
+ * signaling see Section 7.1.4.5 of the USB specification version 1.0.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_RESUME field. */
+#define USB_RD_CTL_RESUME(base) ((USB_CTL_REG(base) & USB_CTL_RESUME_MASK) >> USB_CTL_RESUME_SHIFT)
+#define USB_BRD_CTL_RESUME(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESUME_SHIFT))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_CTL_RESUME(base, value) (USB_RMW_CTL(base, USB_CTL_RESUME_MASK, USB_CTL_RESUME(value)))
+#define USB_BWR_CTL_RESUME(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESUME_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field HOSTMODEEN[3] (RW)
+ *
+ * When set to 1, this bit enables the USB Module to operate in Host mode. In
+ * host mode, the USB module performs USB transactions under the programmed control
+ * of the host processor.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_HOSTMODEEN field. */
+#define USB_RD_CTL_HOSTMODEEN(base) ((USB_CTL_REG(base) & USB_CTL_HOSTMODEEN_MASK) >> USB_CTL_HOSTMODEEN_SHIFT)
+#define USB_BRD_CTL_HOSTMODEEN(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_HOSTMODEEN_SHIFT))
+
+/*! @brief Set the HOSTMODEEN field to a new value. */
+#define USB_WR_CTL_HOSTMODEEN(base, value) (USB_RMW_CTL(base, USB_CTL_HOSTMODEEN_MASK, USB_CTL_HOSTMODEEN(value)))
+#define USB_BWR_CTL_HOSTMODEEN(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_HOSTMODEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field RESET[4] (RW)
+ *
+ * Setting this bit enables the USB Module to generate USB reset signaling. This
+ * allows the USB Module to reset USB peripherals. This control signal is only
+ * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the
+ * required amount of time and then clear it to 0 to end reset signaling. For more
+ * information on reset signaling see Section 7.1.4.3 of the USB specification version
+ * 1.0.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_RESET field. */
+#define USB_RD_CTL_RESET(base) ((USB_CTL_REG(base) & USB_CTL_RESET_MASK) >> USB_CTL_RESET_SHIFT)
+#define USB_BRD_CTL_RESET(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESET_SHIFT))
+
+/*! @brief Set the RESET field to a new value. */
+#define USB_WR_CTL_RESET(base, value) (USB_RMW_CTL(base, USB_CTL_RESET_MASK, USB_CTL_RESET(value)))
+#define USB_BWR_CTL_RESET(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW)
+ *
+ * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB
+ * token. Software must not write more token commands to the Token Register when
+ * TOKEN_BUSY is set. Software should check this field before writing any tokens
+ * to the Token Register to ensure that token commands are not lost. In Target
+ * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and
+ * reception. Clearing this bit allows the SIE to continue token processing. This bit
+ * is set by the SIE when a SETUP Token is received allowing software to dequeue
+ * any pending packet transactions in the BDT before resuming token processing.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field. */
+#define USB_RD_CTL_TXSUSPENDTOKENBUSY(base) ((USB_CTL_REG(base) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) >> USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)
+#define USB_BRD_CTL_TXSUSPENDTOKENBUSY(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))
+
+/*! @brief Set the TXSUSPENDTOKENBUSY field to a new value. */
+#define USB_WR_CTL_TXSUSPENDTOKENBUSY(base, value) (USB_RMW_CTL(base, USB_CTL_TXSUSPENDTOKENBUSY_MASK, USB_CTL_TXSUSPENDTOKENBUSY(value)))
+#define USB_BWR_CTL_TXSUSPENDTOKENBUSY(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field SE0[6] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_SE0 field. */
+#define USB_RD_CTL_SE0(base) ((USB_CTL_REG(base) & USB_CTL_SE0_MASK) >> USB_CTL_SE0_SHIFT)
+#define USB_BRD_CTL_SE0(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT))
+
+/*! @brief Set the SE0 field to a new value. */
+#define USB_WR_CTL_SE0(base, value) (USB_RMW_CTL(base, USB_CTL_SE0_MASK, USB_CTL_SE0(value)))
+#define USB_BWR_CTL_SE0(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field JSTATE[7] (RW)
+ *
+ * The polarity of this signal is affected by the current state of LSEN .
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_JSTATE field. */
+#define USB_RD_CTL_JSTATE(base) ((USB_CTL_REG(base) & USB_CTL_JSTATE_MASK) >> USB_CTL_JSTATE_SHIFT)
+#define USB_BRD_CTL_JSTATE(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT))
+
+/*! @brief Set the JSTATE field to a new value. */
+#define USB_WR_CTL_JSTATE(base, value) (USB_RMW_CTL(base, USB_CTL_JSTATE_MASK, USB_CTL_JSTATE(value)))
+#define USB_BWR_CTL_JSTATE(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDR - Address register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDR - Address register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Holds the unique USB address that the USB module decodes when in Peripheral
+ * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module
+ * transmits this address with a TOKEN packet. This enables the USB module to
+ * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1.
+ * The Address register is reset to 0x00 after the reset input becomes active or
+ * the USB module decodes a USB reset signal. This action initializes the Address
+ * register to decode address 0x00 as required by the USB specification.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDR register
+ */
+/*@{*/
+#define USB_RD_ADDR(base)        (USB_ADDR_REG(base))
+#define USB_WR_ADDR(base, value) (USB_ADDR_REG(base) = (value))
+#define USB_RMW_ADDR(base, mask, value) (USB_WR_ADDR(base, (USB_RD_ADDR(base) & ~(mask)) | (value)))
+#define USB_SET_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) |  (value)))
+#define USB_CLR_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) & ~(value)))
+#define USB_TOG_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDR bitfields
+ */
+
+/*!
+ * @name Register USB_ADDR, field ADDR[6:0] (RW)
+ *
+ * Defines the USB address that the USB module decodes in peripheral mode, or
+ * transmits when in host mode.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_ADDR field. */
+#define USB_RD_ADDR_ADDR(base) ((USB_ADDR_REG(base) & USB_ADDR_ADDR_MASK) >> USB_ADDR_ADDR_SHIFT)
+#define USB_BRD_ADDR_ADDR(base) (USB_RD_ADDR_ADDR(base))
+
+/*! @brief Set the ADDR field to a new value. */
+#define USB_WR_ADDR_ADDR(base, value) (USB_RMW_ADDR(base, USB_ADDR_ADDR_MASK, USB_ADDR_ADDR(value)))
+#define USB_BWR_ADDR_ADDR(base, value) (USB_WR_ADDR_ADDR(base, value))
+/*@}*/
+
+/*!
+ * @name Register USB_ADDR, field LSEN[7] (RW)
+ *
+ * Informs the USB module that the next token command written to the token
+ * register must be performed at low speed. This enables the USB module to perform the
+ * necessary preamble required for low-speed data transmissions.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_LSEN field. */
+#define USB_RD_ADDR_LSEN(base) ((USB_ADDR_REG(base) & USB_ADDR_LSEN_MASK) >> USB_ADDR_LSEN_SHIFT)
+#define USB_BRD_ADDR_LSEN(base) (BITBAND_ACCESS8(&USB_ADDR_REG(base), USB_ADDR_LSEN_SHIFT))
+
+/*! @brief Set the LSEN field to a new value. */
+#define USB_WR_ADDR_LSEN(base, value) (USB_RMW_ADDR(base, USB_ADDR_LSEN_MASK, USB_ADDR_LSEN(value)))
+#define USB_BWR_ADDR_LSEN(base, value) (BITBAND_ACCESS8(&USB_ADDR_REG(base), USB_ADDR_LSEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE1 - BDT Page register 1
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE1 - BDT Page register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides address bits 15 through 9 of the base address where the current
+ * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor
+ * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so
+ * bits 8 through 0 of the base address are always zero.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE1 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE1(base)    (USB_BDTPAGE1_REG(base))
+#define USB_WR_BDTPAGE1(base, value) (USB_BDTPAGE1_REG(base) = (value))
+#define USB_RMW_BDTPAGE1(base, mask, value) (USB_WR_BDTPAGE1(base, (USB_RD_BDTPAGE1(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) |  (value)))
+#define USB_CLR_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) & ~(value)))
+#define USB_TOG_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_BDTPAGE1 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW)
+ *
+ * Provides address bits 15 through 9 of the BDT base address.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_BDTPAGE1_BDTBA field. */
+#define USB_RD_BDTPAGE1_BDTBA(base) ((USB_BDTPAGE1_REG(base) & USB_BDTPAGE1_BDTBA_MASK) >> USB_BDTPAGE1_BDTBA_SHIFT)
+#define USB_BRD_BDTPAGE1_BDTBA(base) (USB_RD_BDTPAGE1_BDTBA(base))
+
+/*! @brief Set the BDTBA field to a new value. */
+#define USB_WR_BDTPAGE1_BDTBA(base, value) (USB_RMW_BDTPAGE1(base, USB_BDTPAGE1_BDTBA_MASK, USB_BDTPAGE1_BDTBA(value)))
+#define USB_BWR_BDTPAGE1_BDTBA(base, value) (USB_WR_BDTPAGE1_BDTBA(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUML - Frame Number register Low
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUML - Frame Number register Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUML register
+ */
+/*@{*/
+#define USB_RD_FRMNUML(base)     (USB_FRMNUML_REG(base))
+#define USB_WR_FRMNUML(base, value) (USB_FRMNUML_REG(base) = (value))
+#define USB_RMW_FRMNUML(base, mask, value) (USB_WR_FRMNUML(base, (USB_RD_FRMNUML(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) |  (value)))
+#define USB_CLR_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) & ~(value)))
+#define USB_TOG_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUMH - Frame Number register High
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUMH - Frame Number register High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUMH register
+ */
+/*@{*/
+#define USB_RD_FRMNUMH(base)     (USB_FRMNUMH_REG(base))
+#define USB_WR_FRMNUMH(base, value) (USB_FRMNUMH_REG(base) = (value))
+#define USB_RMW_FRMNUMH(base, mask, value) (USB_WR_FRMNUMH(base, (USB_RD_FRMNUMH(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) |  (value)))
+#define USB_CLR_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) & ~(value)))
+#define USB_TOG_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_FRMNUMH bitfields
+ */
+
+/*!
+ * @name Register USB_FRMNUMH, field FRM[2:0] (RW)
+ *
+ * This 3-bit field and the 8-bit field in the Frame Number Register Low are
+ * used to compute the address where the current Buffer Descriptor Table (BDT)
+ * resides in system memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_FRMNUMH_FRM field. */
+#define USB_RD_FRMNUMH_FRM(base) ((USB_FRMNUMH_REG(base) & USB_FRMNUMH_FRM_MASK) >> USB_FRMNUMH_FRM_SHIFT)
+#define USB_BRD_FRMNUMH_FRM(base) (USB_RD_FRMNUMH_FRM(base))
+
+/*! @brief Set the FRM field to a new value. */
+#define USB_WR_FRMNUMH_FRM(base, value) (USB_RMW_FRMNUMH(base, USB_FRMNUMH_FRM_MASK, USB_FRMNUMH_FRM(value)))
+#define USB_BWR_FRMNUMH_FRM(base, value) (USB_WR_FRMNUMH_FRM(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_TOKEN - Token register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_TOKEN - Token register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the
+ * software needs to execute a USB transaction to a peripheral, it writes the
+ * TOKEN type and endpoint to this register. After this register has been written,
+ * the USB module begins the specified USB transaction to the address contained in
+ * the address register. The processor core must always check that the
+ * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register.
+ * This ensures that the token commands are not overwritten before they can be
+ * executed. The address register and endpoint control register 0 are also used when
+ * performing a token command and therefore must also be written before the
+ * Token Register. The address register is used to select the USB peripheral address
+ * transmitted by the token command. The endpoint control register determines the
+ * handshake and retry policies used during the transfer.
+ */
+/*!
+ * @name Constants and macros for entire USB_TOKEN register
+ */
+/*@{*/
+#define USB_RD_TOKEN(base)       (USB_TOKEN_REG(base))
+#define USB_WR_TOKEN(base, value) (USB_TOKEN_REG(base) = (value))
+#define USB_RMW_TOKEN(base, mask, value) (USB_WR_TOKEN(base, (USB_RD_TOKEN(base) & ~(mask)) | (value)))
+#define USB_SET_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) |  (value)))
+#define USB_CLR_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) & ~(value)))
+#define USB_TOG_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_TOKEN bitfields
+ */
+
+/*!
+ * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW)
+ *
+ * Holds the Endpoint address for the token command. The four bit value written
+ * must be a valid endpoint.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_TOKEN_TOKENENDPT field. */
+#define USB_RD_TOKEN_TOKENENDPT(base) ((USB_TOKEN_REG(base) & USB_TOKEN_TOKENENDPT_MASK) >> USB_TOKEN_TOKENENDPT_SHIFT)
+#define USB_BRD_TOKEN_TOKENENDPT(base) (USB_RD_TOKEN_TOKENENDPT(base))
+
+/*! @brief Set the TOKENENDPT field to a new value. */
+#define USB_WR_TOKEN_TOKENENDPT(base, value) (USB_RMW_TOKEN(base, USB_TOKEN_TOKENENDPT_MASK, USB_TOKEN_TOKENENDPT(value)))
+#define USB_BWR_TOKEN_TOKENENDPT(base, value) (USB_WR_TOKEN_TOKENENDPT(base, value))
+/*@}*/
+
+/*!
+ * @name Register USB_TOKEN, field TOKENPID[7:4] (RW)
+ *
+ * Contains the token type executed by the USB module.
+ *
+ * Values:
+ * - 0b0001 - OUT Token. USB Module performs an OUT (TX) transaction.
+ * - 0b1001 - IN Token. USB Module performs an In (RX) transaction.
+ * - 0b1101 - SETUP Token. USB Module performs a SETUP (TX) transaction
+ */
+/*@{*/
+/*! @brief Read current value of the USB_TOKEN_TOKENPID field. */
+#define USB_RD_TOKEN_TOKENPID(base) ((USB_TOKEN_REG(base) & USB_TOKEN_TOKENPID_MASK) >> USB_TOKEN_TOKENPID_SHIFT)
+#define USB_BRD_TOKEN_TOKENPID(base) (USB_RD_TOKEN_TOKENPID(base))
+
+/*! @brief Set the TOKENPID field to a new value. */
+#define USB_WR_TOKEN_TOKENPID(base, value) (USB_RMW_TOKEN(base, USB_TOKEN_TOKENPID_MASK, USB_TOKEN_TOKENPID(value)))
+#define USB_BWR_TOKEN_TOKENPID(base, value) (USB_WR_TOKEN_TOKENPID(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_SOFTHLD - SOF Threshold register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_SOFTHLD - SOF Threshold register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in
+ * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The
+ * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with
+ * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF)
+ * token is transmitted. The SOF threshold register is used to program the number
+ * of USB byte times before the SOF to stop initiating token packet transactions.
+ * This register must be set to a value that ensures that other packets are not
+ * actively being transmitted when the SOF time counts to zero. When the SOF
+ * counter reaches the threshold value, no more tokens are transmitted until after the
+ * SOF has been transmitted. The value programmed into the threshold register
+ * must reserve enough time to ensure the worst case transaction completes. In
+ * general the worst case transaction is an IN token followed by a data packet from
+ * the target followed by the response from the host. The actual time required is
+ * a function of the maximum packet size on the bus. Typical values for the SOF
+ * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26;
+ * 8-byte packets=18.
+ */
+/*!
+ * @name Constants and macros for entire USB_SOFTHLD register
+ */
+/*@{*/
+#define USB_RD_SOFTHLD(base)     (USB_SOFTHLD_REG(base))
+#define USB_WR_SOFTHLD(base, value) (USB_SOFTHLD_REG(base) = (value))
+#define USB_RMW_SOFTHLD(base, mask, value) (USB_WR_SOFTHLD(base, (USB_RD_SOFTHLD(base) & ~(mask)) | (value)))
+#define USB_SET_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) |  (value)))
+#define USB_CLR_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) & ~(value)))
+#define USB_TOG_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE2 - BDT Page Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE2 - BDT Page Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE2 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE2(base)    (USB_BDTPAGE2_REG(base))
+#define USB_WR_BDTPAGE2(base, value) (USB_BDTPAGE2_REG(base) = (value))
+#define USB_RMW_BDTPAGE2(base, mask, value) (USB_WR_BDTPAGE2(base, (USB_RD_BDTPAGE2(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) |  (value)))
+#define USB_CLR_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) & ~(value)))
+#define USB_TOG_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE3 - BDT Page Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE3 - BDT Page Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE3 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE3(base)    (USB_BDTPAGE3_REG(base))
+#define USB_WR_BDTPAGE3(base, value) (USB_BDTPAGE3_REG(base) = (value))
+#define USB_RMW_BDTPAGE3(base, mask, value) (USB_WR_BDTPAGE3(base, (USB_RD_BDTPAGE3(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) |  (value)))
+#define USB_CLR_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) & ~(value)))
+#define USB_TOG_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ENDPT - Endpoint Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ENDPT - Endpoint Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains the endpoint control bits for each of the 16 endpoints available
+ * within the USB module for a decoded address. The format for these registers is
+ * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control
+ * pipe 0, which is required for all USB functions. Therefore, after a USBRST
+ * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode
+ * ENDPT0 is used to determine the handshake, retry and low speed
+ * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
+ * bit should be 1. For Isochronous transfers it should be 0. Common values to
+ * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
+ * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and
+ * EPTXEN define if an endpoint is enabled and define the direction of the endpoint.
+ * The endpoint enable/direction control is defined in the following table.
+ * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint
+ * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only
+ * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and
+ * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP)
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire USB_ENDPT register
+ */
+/*@{*/
+#define USB_RD_ENDPT(base, index) (USB_ENDPT_REG(base, index))
+#define USB_WR_ENDPT(base, index, value) (USB_ENDPT_REG(base, index) = (value))
+#define USB_RMW_ENDPT(base, index, mask, value) (USB_WR_ENDPT(base, index, (USB_RD_ENDPT(base, index) & ~(mask)) | (value)))
+#define USB_SET_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) |  (value)))
+#define USB_CLR_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) & ~(value)))
+#define USB_TOG_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ENDPT bitfields
+ */
+
+/*!
+ * @name Register USB_ENDPT, field EPHSHK[0] (RW)
+ *
+ * When set this bit enables an endpoint to perform handshaking during a
+ * transaction to this endpoint. This bit is generally 1 unless the endpoint is
+ * Isochronous.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPHSHK field. */
+#define USB_RD_ENDPT_EPHSHK(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPHSHK_MASK) >> USB_ENDPT_EPHSHK_SHIFT)
+#define USB_BRD_ENDPT_EPHSHK(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT))
+
+/*! @brief Set the EPHSHK field to a new value. */
+#define USB_WR_ENDPT_EPHSHK(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPHSHK_MASK, USB_ENDPT_EPHSHK(value)))
+#define USB_BWR_ENDPT_EPHSHK(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPSTALL[1] (RW)
+ *
+ * When set this bit indicates that the endpoint is called. This bit has
+ * priority over all other control bits in the EndPoint Enable Register, but it is only
+ * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB
+ * Module to return a STALL handshake. After an endpoint is stalled it requires
+ * intervention from the Host Controller.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPSTALL field. */
+#define USB_RD_ENDPT_EPSTALL(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPSTALL_MASK) >> USB_ENDPT_EPSTALL_SHIFT)
+#define USB_BRD_ENDPT_EPSTALL(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT))
+
+/*! @brief Set the EPSTALL field to a new value. */
+#define USB_WR_ENDPT_EPSTALL(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPSTALL_MASK, USB_ENDPT_EPSTALL(value)))
+#define USB_BWR_ENDPT_EPSTALL(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPTXEN[2] (RW)
+ *
+ * This bit, when set, enables the endpoint for TX transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPTXEN field. */
+#define USB_RD_ENDPT_EPTXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPTXEN_MASK) >> USB_ENDPT_EPTXEN_SHIFT)
+#define USB_BRD_ENDPT_EPTXEN(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT))
+
+/*! @brief Set the EPTXEN field to a new value. */
+#define USB_WR_ENDPT_EPTXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPTXEN_MASK, USB_ENDPT_EPTXEN(value)))
+#define USB_BWR_ENDPT_EPTXEN(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPRXEN[3] (RW)
+ *
+ * This bit, when set, enables the endpoint for RX transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPRXEN field. */
+#define USB_RD_ENDPT_EPRXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPRXEN_MASK) >> USB_ENDPT_EPRXEN_SHIFT)
+#define USB_BRD_ENDPT_EPRXEN(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT))
+
+/*! @brief Set the EPRXEN field to a new value. */
+#define USB_WR_ENDPT_EPRXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPRXEN_MASK, USB_ENDPT_EPRXEN(value)))
+#define USB_BWR_ENDPT_EPRXEN(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPCTLDIS[4] (RW)
+ *
+ * This bit, when set, disables control (SETUP) transfers. When cleared, control
+ * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
+ * are also set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPCTLDIS field. */
+#define USB_RD_ENDPT_EPCTLDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPCTLDIS_MASK) >> USB_ENDPT_EPCTLDIS_SHIFT)
+#define USB_BRD_ENDPT_EPCTLDIS(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT))
+
+/*! @brief Set the EPCTLDIS field to a new value. */
+#define USB_WR_ENDPT_EPCTLDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPCTLDIS_MASK, USB_ENDPT_EPCTLDIS(value)))
+#define USB_BWR_ENDPT_EPCTLDIS(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field RETRYDIS[6] (RW)
+ *
+ * This is a Host mode only bit and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed
+ * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID
+ * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When
+ * this bit is cleared, NAKed transactions are retried in hardware. This bit must
+ * be set when the host is attempting to poll an interrupt endpoint.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_RETRYDIS field. */
+#define USB_RD_ENDPT_RETRYDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_RETRYDIS_MASK) >> USB_ENDPT_RETRYDIS_SHIFT)
+#define USB_BRD_ENDPT_RETRYDIS(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_RETRYDIS_SHIFT))
+
+/*! @brief Set the RETRYDIS field to a new value. */
+#define USB_WR_ENDPT_RETRYDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_RETRYDIS_MASK, USB_ENDPT_RETRYDIS(value)))
+#define USB_BWR_ENDPT_RETRYDIS(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_RETRYDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field HOSTWOHUB[7] (RW)
+ *
+ * This is a Host mode only field and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a
+ * directly connected low speed device. When cleared, the host produces the
+ * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed
+ * device as required to communicate with a low speed device through a hub.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_HOSTWOHUB field. */
+#define USB_RD_ENDPT_HOSTWOHUB(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_HOSTWOHUB_MASK) >> USB_ENDPT_HOSTWOHUB_SHIFT)
+#define USB_BRD_ENDPT_HOSTWOHUB(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_HOSTWOHUB_SHIFT))
+
+/*! @brief Set the HOSTWOHUB field to a new value. */
+#define USB_WR_ENDPT_HOSTWOHUB(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_HOSTWOHUB_MASK, USB_ENDPT_HOSTWOHUB(value)))
+#define USB_BWR_ENDPT_HOSTWOHUB(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_HOSTWOHUB_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBCTRL - USB Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBCTRL - USB Control register (RW)
+ *
+ * Reset value: 0xC0U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBCTRL register
+ */
+/*@{*/
+#define USB_RD_USBCTRL(base)     (USB_USBCTRL_REG(base))
+#define USB_WR_USBCTRL(base, value) (USB_USBCTRL_REG(base) = (value))
+#define USB_RMW_USBCTRL(base, mask, value) (USB_WR_USBCTRL(base, (USB_RD_USBCTRL(base) & ~(mask)) | (value)))
+#define USB_SET_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) |  (value)))
+#define USB_CLR_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) & ~(value)))
+#define USB_TOG_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBCTRL bitfields
+ */
+
+/*!
+ * @name Register USB_USBCTRL, field PDE[6] (RW)
+ *
+ * Enables the weak pulldowns on the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - Weak pulldowns are disabled on D+ and D-.
+ * - 0b1 - Weak pulldowns are enabled on D+ and D-.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_PDE field. */
+#define USB_RD_USBCTRL_PDE(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_PDE_MASK) >> USB_USBCTRL_PDE_SHIFT)
+#define USB_BRD_USBCTRL_PDE(base) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT))
+
+/*! @brief Set the PDE field to a new value. */
+#define USB_WR_USBCTRL_PDE(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_PDE_MASK, USB_USBCTRL_PDE(value)))
+#define USB_BWR_USBCTRL_PDE(base, value) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_USBCTRL, field SUSP[7] (RW)
+ *
+ * Places the USB transceiver into the suspend state.
+ *
+ * Values:
+ * - 0b0 - USB transceiver is not in suspend state.
+ * - 0b1 - USB transceiver is in suspend state.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_SUSP field. */
+#define USB_RD_USBCTRL_SUSP(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_SUSP_MASK) >> USB_USBCTRL_SUSP_SHIFT)
+#define USB_BRD_USBCTRL_SUSP(base) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT))
+
+/*! @brief Set the SUSP field to a new value. */
+#define USB_WR_USBCTRL_SUSP(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_SUSP_MASK, USB_USBCTRL_SUSP(value)))
+#define USB_BWR_USBCTRL_SUSP(base, value) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OBSERVE - USB OTG Observe register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OBSERVE - USB OTG Observe register (RO)
+ *
+ * Reset value: 0x50U
+ *
+ * Provides visibility on the state of the pull-ups and pull-downs at the
+ * transceiver. Useful when interfacing to an external OTG control module via a serial
+ * interface.
+ */
+/*!
+ * @name Constants and macros for entire USB_OBSERVE register
+ */
+/*@{*/
+#define USB_RD_OBSERVE(base)     (USB_OBSERVE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OBSERVE bitfields
+ */
+
+/*!
+ * @name Register USB_OBSERVE, field DMPD[4] (RO)
+ *
+ * Provides observability of the D- Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D- pulldown disabled.
+ * - 0b1 - D- pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DMPD field. */
+#define USB_RD_OBSERVE_DMPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DMPD_MASK) >> USB_OBSERVE_DMPD_SHIFT)
+#define USB_BRD_OBSERVE_DMPD(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DMPD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPD[6] (RO)
+ *
+ * Provides observability of the D+ Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D+ pulldown disabled.
+ * - 0b1 - D+ pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPD field. */
+#define USB_RD_OBSERVE_DPPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPD_MASK) >> USB_OBSERVE_DPPD_SHIFT)
+#define USB_BRD_OBSERVE_DPPD(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPU[7] (RO)
+ *
+ * Provides observability of the D+ Pullup enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D+ pullup disabled.
+ * - 0b1 - D+ pullup enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPU field. */
+#define USB_RD_OBSERVE_DPPU(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPU_MASK) >> USB_OBSERVE_DPPU_SHIFT)
+#define USB_BRD_OBSERVE_DPPU(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPU_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CONTROL - USB OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CONTROL - USB OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_CONTROL register
+ */
+/*@{*/
+#define USB_RD_CONTROL(base)     (USB_CONTROL_REG(base))
+#define USB_WR_CONTROL(base, value) (USB_CONTROL_REG(base) = (value))
+#define USB_RMW_CONTROL(base, mask, value) (USB_WR_CONTROL(base, (USB_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USB_SET_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) |  (value)))
+#define USB_CLR_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) & ~(value)))
+#define USB_TOG_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW)
+ *
+ * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG
+ * device mode.
+ *
+ * Values:
+ * - 0b0 - DP Pullup in non-OTG device mode is not enabled.
+ * - 0b1 - DP Pullup in non-OTG device mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field. */
+#define USB_RD_CONTROL_DPPULLUPNONOTG(base) ((USB_CONTROL_REG(base) & USB_CONTROL_DPPULLUPNONOTG_MASK) >> USB_CONTROL_DPPULLUPNONOTG_SHIFT)
+#define USB_BRD_CONTROL_DPPULLUPNONOTG(base) (BITBAND_ACCESS8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT))
+
+/*! @brief Set the DPPULLUPNONOTG field to a new value. */
+#define USB_WR_CONTROL_DPPULLUPNONOTG(base, value) (USB_RMW_CONTROL(base, USB_CONTROL_DPPULLUPNONOTG_MASK, USB_CONTROL_DPPULLUPNONOTG(value)))
+#define USB_BWR_CONTROL_DPPULLUPNONOTG(base, value) (BITBAND_ACCESS8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBTRC0 - USB Transceiver Control register 0
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBTRC0 - USB Transceiver Control register 0 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Includes signals for basic operation of the on-chip USB Full Speed
+ * transceiver and configuration of the USB data connection that are not otherwise included
+ * in the USB Full Speed controller registers.
+ */
+/*!
+ * @name Constants and macros for entire USB_USBTRC0 register
+ */
+/*@{*/
+#define USB_RD_USBTRC0(base)     (USB_USBTRC0_REG(base))
+#define USB_WR_USBTRC0(base, value) (USB_USBTRC0_REG(base) = (value))
+#define USB_RMW_USBTRC0(base, mask, value) (USB_WR_USBTRC0(base, (USB_RD_USBTRC0(base) & ~(mask)) | (value)))
+#define USB_SET_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) |  (value)))
+#define USB_CLR_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) & ~(value)))
+#define USB_TOG_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBTRC0 bitfields
+ */
+
+/*!
+ * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No interrupt was generated.
+ * - 0b1 - Interrupt was generated because of the USB asynchronous interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field. */
+#define USB_RD_USBTRC0_USB_RESUME_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_RESUME_INT_MASK) >> USB_USBTRC0_USB_RESUME_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_RESUME_INT(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_RESUME_INT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field SYNC_DET[1] (RO)
+ *
+ * Values:
+ * - 0b0 - Synchronous interrupt has not been detected.
+ * - 0b1 - Synchronous interrupt has been detected.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_SYNC_DET field. */
+#define USB_RD_USBTRC0_SYNC_DET(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_SYNC_DET_MASK) >> USB_USBTRC0_SYNC_DET_SHIFT)
+#define USB_BRD_USBTRC0_SYNC_DET(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_SYNC_DET_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO)
+ *
+ * This read-only field will be set to value high at 1'b1 when any of USB clock
+ * recovery interrupt conditions are detected and those interrupts are unmasked.
+ * For customer use the only unmasked USB clock recovery interrupt condition
+ * results from an overflow of the frequency trim setting values indicating that the
+ * frequency trim calculated is out of the adjustment range of the IRC48M output
+ * clock. To clear this bit after it has been set, Write 0xFF to register
+ * USB_CLK_RECOVER_INT_STATUS.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field. */
+#define USB_RD_USBTRC0_USB_CLK_RECOVERY_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) >> USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_CLK_RECOVERY_INT(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESMEN[5] (RW)
+ *
+ * This bit, when set, allows the USB module to send an asynchronous wakeup
+ * event to the MCU upon detection of resume signaling on the USB bus. The MCU then
+ * re-enables clocks to the USB module. It is used for low-power suspend mode when
+ * USB module clocks are stopped or the USB transceiver is in Suspend mode.
+ * Async wakeup only works in device mode.
+ *
+ * Values:
+ * - 0b0 - USB asynchronous wakeup from suspend mode disabled.
+ * - 0b1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous
+ *     resume interrupt differs from the synchronous resume interrupt in that it
+ *     asynchronously detects K-state using the unfiltered state of the D+ and D-
+ *     pins. This interrupt should only be enabled when the Transceiver is
+ *     suspended.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USBRESMEN field. */
+#define USB_RD_USBTRC0_USBRESMEN(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USBRESMEN_MASK) >> USB_USBTRC0_USBRESMEN_SHIFT)
+#define USB_BRD_USBTRC0_USBRESMEN(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT))
+
+/*! @brief Set the USBRESMEN field to a new value. */
+#define USB_WR_USBTRC0_USBRESMEN(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESMEN_MASK, USB_USBTRC0_USBRESMEN(value)))
+#define USB_BWR_USBTRC0_USBRESMEN(base, value) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESET[7] (WO)
+ *
+ * Generates a hard reset to USBOTG. After this bit is set and the reset occurs,
+ * this bit is automatically cleared. This bit is always read as zero. Wait two
+ * USB clock cycles after setting this bit.
+ *
+ * Values:
+ * - 0b0 - Normal USB module operation.
+ * - 0b1 - Returns the USB module to its reset state.
+ */
+/*@{*/
+/*! @brief Set the USBRESET field to a new value. */
+#define USB_WR_USBTRC0_USBRESET(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESET_MASK, USB_USBTRC0_USBRESET(value)))
+#define USB_BWR_USBTRC0_USBRESET(base, value) (USB_WR_USBTRC0_USBRESET(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBFRMADJUST - Frame Adjust Register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBFRMADJUST - Frame Adjust Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBFRMADJUST register
+ */
+/*@{*/
+#define USB_RD_USBFRMADJUST(base) (USB_USBFRMADJUST_REG(base))
+#define USB_WR_USBFRMADJUST(base, value) (USB_USBFRMADJUST_REG(base) = (value))
+#define USB_RMW_USBFRMADJUST(base, mask, value) (USB_WR_USBFRMADJUST(base, (USB_RD_USBFRMADJUST(base) & ~(mask)) | (value)))
+#define USB_SET_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) |  (value)))
+#define USB_CLR_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) & ~(value)))
+#define USB_TOG_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Signals in this register control the crystal-less USB clock mode in which the
+ * internal IRC48M oscillator is tuned to match the clock extracted from the
+ * incoming USB data stream. The IRC48M internal oscillator module must be enabled
+ * in register USB_CLK_RECOVER_IRC_EN for this mode.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_CTRL(base) (USB_CLK_RECOVER_CTRL_REG(base))
+#define USB_WR_CLK_RECOVER_CTRL(base, value) (USB_CLK_RECOVER_CTRL_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_CTRL(base, mask, value) (USB_WR_CLK_RECOVER_CTRL(base, (USB_RD_CLK_RECOVER_CTRL(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW)
+ *
+ * IRC48 has a default trim fine value whose default value is factory trimmed
+ * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz
+ * and keeps updating the trim fine value accordingly
+ *
+ * Values:
+ * - 0b0 - Trim fine adjustment always works based on the previous updated trim
+ *     fine value (default)
+ * - 0b1 - Trim fine restarts from the IFR trim value whenever
+ *     bus_reset/bus_resume is detected or module enable is desasserted
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))
+
+/*! @brief Set the RESTART_IFRTRIM_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW)
+ *
+ * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock.
+ * It has two phases after user enables clock_recover_en bit, rough phase and
+ * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine
+ * value is different during these two phases. The step in rough phase is larger
+ * than that in tracking phase. Switch back to rough stage whenever USB bus reset
+ * or bus resume occurs.
+ *
+ * Values:
+ * - 0b0 - Always works in tracking phase after the 1st time rough to track
+ *     transition (default)
+ * - 0b1 - Go back to rough stage whenever bus reset or bus resume occurs
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))
+
+/*! @brief Set the RESET_RESUME_ROUGH_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW)
+ *
+ * This bit must be enabled if user wants to use the crystal-less USB mode for
+ * the Full Speed USB controller and transceiver. This bit should not be set for
+ * USB host mode or OTG.
+ *
+ * Values:
+ * - 0b0 - Disable clock recovery block (default)
+ * - 0b1 - Enable clock recovery block
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) >> USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))
+
+/*! @brief Set the CLOCK_RECOVER_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * Controls basic operation of the on-chip IRC48M module used to produce nominal
+ * 48MHz clocks for USB crystal-less operation and other functions. See
+ * additional information about the IRC48M operation in the Clock Distribution chapter.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_IRC_EN(base) (USB_CLK_RECOVER_IRC_EN_REG(base))
+#define USB_WR_CLK_RECOVER_IRC_EN(base, value) (USB_CLK_RECOVER_IRC_EN_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_IRC_EN(base, mask, value) (USB_WR_CLK_RECOVER_IRC_EN(base, (USB_RD_CLK_RECOVER_IRC_EN(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW)
+ *
+ * This bit is used to enable the local analog regulator for IRC48Mhz module.
+ * This bit must be set if user wants to use the crystal-less USB clock
+ * configuration.
+ *
+ * Values:
+ * - 0b0 - IRC48M local regulator is disabled
+ * - 0b1 - IRC48M local regulator is enabled (default)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_REG_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_REG_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))
+
+/*! @brief Set the REG_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_REG_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_REG_EN_MASK, USB_CLK_RECOVER_IRC_EN_REG_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_REG_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
+ *
+ * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
+ * crystal-less USB. It can only be used for FS USB device mode operation. This
+ * bit must be set before using the crystal-less USB clock configuration.
+ *
+ * Values:
+ * - 0b0 - Disable the IRC48M module (default)
+ * - 0b1 - Enable the IRC48M module
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_IRC_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_IRC_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))
+
+/*! @brief Set the IRC_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK, USB_CLK_RECOVER_IRC_EN_IRC_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * A Write operation with value high at 1'b1 on any combination of individual
+ * bits will clear those bits.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_INT_STATUS(base) (USB_CLK_RECOVER_INT_STATUS_REG(base))
+#define USB_WR_CLK_RECOVER_INT_STATUS(base, value) (USB_CLK_RECOVER_INT_STATUS_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_INT_STATUS(base, mask, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, (USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C)
+ *
+ * Indicates that the USB clock recovery algorithm has detected that the
+ * frequency trim adjustment needed for the IRC48M output clock is outside the available
+ * TRIM_FINE adjustment range for the IRC48M module.
+ *
+ * Values:
+ * - 0b0 - No interrupt is reported
+ * - 0b1 - Unmasked interrupt has been generated
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field. */
+#define USB_RD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) ((USB_CLK_RECOVER_INT_STATUS_REG(base) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) >> USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)
+#define USB_BRD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))
+
+/*! @brief Set the OVF_ERROR field to a new value. */
+#define USB_WR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (USB_RMW_CLK_RECOVER_INT_STATUS(base, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(value)))
+#define USB_BWR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 USBDCD
+ *
+ * USB Device Charger Detection module
+ *
+ * Registers defined in this header file:
+ * - USBDCD_CONTROL - Control register
+ * - USBDCD_CLOCK - Clock register
+ * - USBDCD_STATUS - Status register
+ * - USBDCD_TIMER0 - TIMER0 register
+ * - USBDCD_TIMER1 - TIMER1 register
+ * - USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ * - USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ */
+
+#define USBDCD_INSTANCE_COUNT (1U) /*!< Number of instances of the USBDCD module. */
+#define USBDCD_IDX (0U) /*!< Instance number for USBDCD. */
+
+/*******************************************************************************
+ * USBDCD_CONTROL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_CONTROL - Control register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Contains the control and interrupt bit fields.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_CONTROL register
+ */
+/*@{*/
+#define USBDCD_RD_CONTROL(base)  (USBDCD_CONTROL_REG(base))
+#define USBDCD_WR_CONTROL(base, value) (USBDCD_CONTROL_REG(base) = (value))
+#define USBDCD_RMW_CONTROL(base, mask, value) (USBDCD_WR_CONTROL(base, (USBDCD_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USBDCD_SET_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) |  (value)))
+#define USBDCD_CLR_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) & ~(value)))
+#define USBDCD_TOG_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CONTROL, field IACK[0] (WORZ)
+ *
+ * Determines whether the interrupt is cleared.
+ *
+ * Values:
+ * - 0b0 - Do not clear the interrupt.
+ * - 0b1 - Clear the IF bit (interrupt flag).
+ */
+/*@{*/
+/*! @brief Set the IACK field to a new value. */
+#define USBDCD_WR_CONTROL_IACK(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_IACK_MASK, USBDCD_CONTROL_IACK(value)))
+#define USBDCD_BWR_CONTROL_IACK(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field IF[8] (RO)
+ *
+ * Determines whether an interrupt is pending.
+ *
+ * Values:
+ * - 0b0 - No interrupt is pending.
+ * - 0b1 - An interrupt is pending.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_IF field. */
+#define USBDCD_RD_CONTROL_IF(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_IF_MASK) >> USBDCD_CONTROL_IF_SHIFT)
+#define USBDCD_BRD_CONTROL_IF(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field IE[16] (RW)
+ *
+ * Enables/disables interrupts to the system.
+ *
+ * Values:
+ * - 0b0 - Disable interrupts to the system.
+ * - 0b1 - Enable interrupts to the system.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_IE field. */
+#define USBDCD_RD_CONTROL_IE(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_IE_MASK) >> USBDCD_CONTROL_IE_SHIFT)
+#define USBDCD_BRD_CONTROL_IE(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IE_SHIFT))
+
+/*! @brief Set the IE field to a new value. */
+#define USBDCD_WR_CONTROL_IE(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_IE_MASK, USBDCD_CONTROL_IE(value)))
+#define USBDCD_BWR_CONTROL_IE(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field BC12[17] (RW)
+ *
+ * BC1.2 compatibility. This bit cannot be changed after start detection.
+ *
+ * Values:
+ * - 0b0 - Compatible with BC1.1 (default)
+ * - 0b1 - Compatible with BC1.2
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_BC12 field. */
+#define USBDCD_RD_CONTROL_BC12(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_BC12_MASK) >> USBDCD_CONTROL_BC12_SHIFT)
+#define USBDCD_BRD_CONTROL_BC12(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_BC12_SHIFT))
+
+/*! @brief Set the BC12 field to a new value. */
+#define USBDCD_WR_CONTROL_BC12(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_BC12_MASK, USBDCD_CONTROL_BC12(value)))
+#define USBDCD_BWR_CONTROL_BC12(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_BC12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field START[24] (WORZ)
+ *
+ * Determines whether the charger detection sequence is initiated.
+ *
+ * Values:
+ * - 0b0 - Do not start the sequence. Writes of this value have no effect.
+ * - 0b1 - Initiate the charger detection sequence. If the sequence is already
+ *     running, writes of this value have no effect.
+ */
+/*@{*/
+/*! @brief Set the START field to a new value. */
+#define USBDCD_WR_CONTROL_START(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_START_MASK, USBDCD_CONTROL_START(value)))
+#define USBDCD_BWR_CONTROL_START(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_START_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field SR[25] (WORZ)
+ *
+ * Determines whether a software reset is performed.
+ *
+ * Values:
+ * - 0b0 - Do not perform a software reset.
+ * - 0b1 - Perform a software reset.
+ */
+/*@{*/
+/*! @brief Set the SR field to a new value. */
+#define USBDCD_WR_CONTROL_SR(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_SR_MASK, USBDCD_CONTROL_SR(value)))
+#define USBDCD_BWR_CONTROL_SR(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_SR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_CLOCK - Clock register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_CLOCK - Clock register (RW)
+ *
+ * Reset value: 0x000000C1U
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_CLOCK register
+ */
+/*@{*/
+#define USBDCD_RD_CLOCK(base)    (USBDCD_CLOCK_REG(base))
+#define USBDCD_WR_CLOCK(base, value) (USBDCD_CLOCK_REG(base) = (value))
+#define USBDCD_RMW_CLOCK(base, mask, value) (USBDCD_WR_CLOCK(base, (USBDCD_RD_CLOCK(base) & ~(mask)) | (value)))
+#define USBDCD_SET_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) |  (value)))
+#define USBDCD_CLR_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) & ~(value)))
+#define USBDCD_TOG_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_CLOCK bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW)
+ *
+ * Specifies the unit of measure for the clock speed.
+ *
+ * Values:
+ * - 0b0 - kHz Speed (between 1 kHz and 1023 kHz)
+ * - 0b1 - MHz Speed (between 1 MHz and 1023 MHz)
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field. */
+#define USBDCD_RD_CLOCK_CLOCK_UNIT(base) ((USBDCD_CLOCK_REG(base) & USBDCD_CLOCK_CLOCK_UNIT_MASK) >> USBDCD_CLOCK_CLOCK_UNIT_SHIFT)
+#define USBDCD_BRD_CLOCK_CLOCK_UNIT(base) (BITBAND_ACCESS32(&USBDCD_CLOCK_REG(base), USBDCD_CLOCK_CLOCK_UNIT_SHIFT))
+
+/*! @brief Set the CLOCK_UNIT field to a new value. */
+#define USBDCD_WR_CLOCK_CLOCK_UNIT(base, value) (USBDCD_RMW_CLOCK(base, USBDCD_CLOCK_CLOCK_UNIT_MASK, USBDCD_CLOCK_CLOCK_UNIT(value)))
+#define USBDCD_BWR_CLOCK_CLOCK_UNIT(base, value) (BITBAND_ACCESS32(&USBDCD_CLOCK_REG(base), USBDCD_CLOCK_CLOCK_UNIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW)
+ *
+ * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to
+ * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples
+ * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz:
+ * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100)
+ * For 500 kHz: 0b01_1111_0100 (500)
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field. */
+#define USBDCD_RD_CLOCK_CLOCK_SPEED(base) ((USBDCD_CLOCK_REG(base) & USBDCD_CLOCK_CLOCK_SPEED_MASK) >> USBDCD_CLOCK_CLOCK_SPEED_SHIFT)
+#define USBDCD_BRD_CLOCK_CLOCK_SPEED(base) (USBDCD_RD_CLOCK_CLOCK_SPEED(base))
+
+/*! @brief Set the CLOCK_SPEED field to a new value. */
+#define USBDCD_WR_CLOCK_CLOCK_SPEED(base, value) (USBDCD_RMW_CLOCK(base, USBDCD_CLOCK_CLOCK_SPEED_MASK, USBDCD_CLOCK_CLOCK_SPEED(value)))
+#define USBDCD_BWR_CLOCK_CLOCK_SPEED(base, value) (USBDCD_WR_CLOCK_CLOCK_SPEED(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_STATUS - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_STATUS - Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Provides the current state of the module for system software monitoring.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_STATUS register
+ */
+/*@{*/
+#define USBDCD_RD_STATUS(base)   (USBDCD_STATUS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_STATUS bitfields
+ */
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO)
+ *
+ * Reports how the charger detection is attached.
+ *
+ * Values:
+ * - 0b00 - No results to report.
+ * - 0b01 - Attached to a standard host. Must comply with USB 2.0 by drawing
+ *     only 2.5 mA (max) until connected.
+ * - 0b10 - Attached to a charging port. The exact meaning depends on bit 18: 0:
+ *     Attached to either a charging host or a dedicated charger. The charger
+ *     type detection has not completed. 1: Attached to a charging host. The
+ *     charger type detection has completed.
+ * - 0b11 - Attached to a dedicated charger.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_SEQ_RES field. */
+#define USBDCD_RD_STATUS_SEQ_RES(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_SEQ_RES_MASK) >> USBDCD_STATUS_SEQ_RES_SHIFT)
+#define USBDCD_BRD_STATUS_SEQ_RES(base) (USBDCD_RD_STATUS_SEQ_RES(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO)
+ *
+ * Indicates the status of the charger detection sequence.
+ *
+ * Values:
+ * - 0b00 - The module is either not enabled, or the module is enabled but the
+ *     data pins have not yet been detected.
+ * - 0b01 - Data pin contact detection is complete.
+ * - 0b10 - Charging port detection is complete.
+ * - 0b11 - Charger type detection is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field. */
+#define USBDCD_RD_STATUS_SEQ_STAT(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_SEQ_STAT_MASK) >> USBDCD_STATUS_SEQ_STAT_SHIFT)
+#define USBDCD_BRD_STATUS_SEQ_STAT(base) (USBDCD_RD_STATUS_SEQ_STAT(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field ERR[20] (RO)
+ *
+ * Indicates whether there is an error in the detection sequence.
+ *
+ * Values:
+ * - 0b0 - No sequence errors.
+ * - 0b1 - Error in the detection sequence. See the SEQ_STAT field to determine
+ *     the phase in which the error occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_ERR field. */
+#define USBDCD_RD_STATUS_ERR(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_ERR_MASK) >> USBDCD_STATUS_ERR_SHIFT)
+#define USBDCD_BRD_STATUS_ERR(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field TO[21] (RO)
+ *
+ * Indicates whether the detection sequence has passed the timeout threshhold.
+ *
+ * Values:
+ * - 0b0 - The detection sequence has not been running for over 1 s.
+ * - 0b1 - It has been over 1 s since the data pin contact was detected and
+ *     debounced.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_TO field. */
+#define USBDCD_RD_STATUS_TO(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_TO_MASK) >> USBDCD_STATUS_TO_SHIFT)
+#define USBDCD_BRD_STATUS_TO(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_TO_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field ACTIVE[22] (RO)
+ *
+ * Indicates whether the sequence is running.
+ *
+ * Values:
+ * - 0b0 - The sequence is not running.
+ * - 0b1 - The sequence is running.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_ACTIVE field. */
+#define USBDCD_RD_STATUS_ACTIVE(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_ACTIVE_MASK) >> USBDCD_STATUS_ACTIVE_SHIFT)
+#define USBDCD_BRD_STATUS_ACTIVE(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_ACTIVE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER0 - TIMER0 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER0 - TIMER0 register (RW)
+ *
+ * Reset value: 0x00100000U
+ *
+ * TIMER0 has an TSEQ_INIT field that represents the system latency in ms.
+ * Latency is measured from the time when VBUS goes active until the time system
+ * software initiates charger detection sequence in USBDCD module. When software sets
+ * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized
+ * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery
+ * Charging Specification requires the entire sequence, including TSEQ_INIT, to be
+ * completed in 1s or less.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER0 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER0(base)   (USBDCD_TIMER0_REG(base))
+#define USBDCD_WR_TIMER0(base, value) (USBDCD_TIMER0_REG(base) = (value))
+#define USBDCD_RMW_TIMER0(base, mask, value) (USBDCD_WR_TIMER0(base, (USBDCD_RD_TIMER0(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) |  (value)))
+#define USBDCD_CLR_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) & ~(value)))
+#define USBDCD_TOG_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER0 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO)
+ *
+ * Displays the amount of elapsed time since the event of setting the START bit
+ * plus the value of TSEQ_INIT. The timer is automatically initialized with the
+ * value of TSEQ_INIT before starting to count. This timer enables compliance with
+ * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging
+ * Specification. If the timer reaches the one second limit, the module triggers
+ * an interrupt and sets the error flag STATUS[ERR]. The timer continues
+ * counting throughout the charger detection sequence, even when control has been passed
+ * to software. As long as the module is active, the timer continues to count
+ * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not
+ * rollover to zero. A software reset clears the timer.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER0_TUNITCON field. */
+#define USBDCD_RD_TIMER0_TUNITCON(base) ((USBDCD_TIMER0_REG(base) & USBDCD_TIMER0_TUNITCON_MASK) >> USBDCD_TIMER0_TUNITCON_SHIFT)
+#define USBDCD_BRD_TIMER0_TUNITCON(base) (USBDCD_RD_TIMER0_TUNITCON(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW)
+ *
+ * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS
+ * goes active to the time system software initiates the charger detection
+ * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit
+ * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid
+ * values are 0-1023, but the USB Battery Charging Specification requires the
+ * entire sequence, including TSEQ_INIT, to be completed in 1s or less.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field. */
+#define USBDCD_RD_TIMER0_TSEQ_INIT(base) ((USBDCD_TIMER0_REG(base) & USBDCD_TIMER0_TSEQ_INIT_MASK) >> USBDCD_TIMER0_TSEQ_INIT_SHIFT)
+#define USBDCD_BRD_TIMER0_TSEQ_INIT(base) (USBDCD_RD_TIMER0_TSEQ_INIT(base))
+
+/*! @brief Set the TSEQ_INIT field to a new value. */
+#define USBDCD_WR_TIMER0_TSEQ_INIT(base, value) (USBDCD_RMW_TIMER0(base, USBDCD_TIMER0_TSEQ_INIT_MASK, USBDCD_TIMER0_TSEQ_INIT(value)))
+#define USBDCD_BWR_TIMER0_TSEQ_INIT(base, value) (USBDCD_WR_TIMER0_TSEQ_INIT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER1 - TIMER1 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER1 - TIMER1 register (RW)
+ *
+ * Reset value: 0x000A0028U
+ *
+ * TIMER1 contains timing parameters. Note that register values can be written
+ * that are not compliant with the USB Battery Charging Specification, so care
+ * should be taken when overwriting the default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER1 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER1(base)   (USBDCD_TIMER1_REG(base))
+#define USBDCD_WR_TIMER1(base, value) (USBDCD_TIMER1_REG(base) = (value))
+#define USBDCD_RMW_TIMER1(base, mask, value) (USBDCD_WR_TIMER1(base, (USBDCD_RD_TIMER1(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) |  (value)))
+#define USBDCD_CLR_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) & ~(value)))
+#define USBDCD_TOG_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER1 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW)
+ *
+ * This timing parameter is used after detection of the data pin. See "Charging
+ * Port Detection". Valid values are 1-1023, but the USB Battery Charging
+ * Specification requires a minimum value of 40 ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field. */
+#define USBDCD_RD_TIMER1_TVDPSRC_ON(base) ((USBDCD_TIMER1_REG(base) & USBDCD_TIMER1_TVDPSRC_ON_MASK) >> USBDCD_TIMER1_TVDPSRC_ON_SHIFT)
+#define USBDCD_BRD_TIMER1_TVDPSRC_ON(base) (USBDCD_RD_TIMER1_TVDPSRC_ON(base))
+
+/*! @brief Set the TVDPSRC_ON field to a new value. */
+#define USBDCD_WR_TIMER1_TVDPSRC_ON(base, value) (USBDCD_RMW_TIMER1(base, USBDCD_TIMER1_TVDPSRC_ON_MASK, USBDCD_TIMER1_TVDPSRC_ON(value)))
+#define USBDCD_BWR_TIMER1_TVDPSRC_ON(base, value) (USBDCD_WR_TIMER1_TVDPSRC_ON(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW)
+ *
+ * Sets the time period (ms) to debounce the D+ signal during the data pin
+ * contact detection phase. See "Debouncing the data pin contact" Valid values are
+ * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10
+ * ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field. */
+#define USBDCD_RD_TIMER1_TDCD_DBNC(base) ((USBDCD_TIMER1_REG(base) & USBDCD_TIMER1_TDCD_DBNC_MASK) >> USBDCD_TIMER1_TDCD_DBNC_SHIFT)
+#define USBDCD_BRD_TIMER1_TDCD_DBNC(base) (USBDCD_RD_TIMER1_TDCD_DBNC(base))
+
+/*! @brief Set the TDCD_DBNC field to a new value. */
+#define USBDCD_WR_TIMER1_TDCD_DBNC(base, value) (USBDCD_RMW_TIMER1(base, USBDCD_TIMER1_TDCD_DBNC_MASK, USBDCD_TIMER1_TDCD_DBNC(value)))
+#define USBDCD_BWR_TIMER1_TDCD_DBNC(base, value) (USBDCD_WR_TIMER1_TDCD_DBNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW)
+ *
+ * Reset value: 0x00280001U
+ *
+ * TIMER2_BC11 contains timing parameters for USB Battery Charging
+ * Specification, v1.1. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC11 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER2_BC11(base) (USBDCD_TIMER2_BC11_REG(base))
+#define USBDCD_WR_TIMER2_BC11(base, value) (USBDCD_TIMER2_BC11_REG(base) = (value))
+#define USBDCD_RMW_TIMER2_BC11(base, mask, value) (USBDCD_WR_TIMER2_BC11(base, (USBDCD_RD_TIMER2_BC11(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) |  (value)))
+#define USBDCD_CLR_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) & ~(value)))
+#define USBDCD_TOG_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after the device
+ * connects to the USB bus until checking the state of the D- line to determine the
+ * type of charging port. See "Charger Type Detection." Valid values are 1-15ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field. */
+#define USBDCD_RD_TIMER2_BC11_CHECK_DM(base) ((USBDCD_TIMER2_BC11_REG(base) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) >> USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)
+#define USBDCD_BRD_TIMER2_BC11_CHECK_DM(base) (USBDCD_RD_TIMER2_BC11_CHECK_DM(base))
+
+/*! @brief Set the CHECK_DM field to a new value. */
+#define USBDCD_WR_TIMER2_BC11_CHECK_DM(base, value) (USBDCD_RMW_TIMER2_BC11(base, USBDCD_TIMER2_BC11_CHECK_DM_MASK, USBDCD_TIMER2_BC11_CHECK_DM(value)))
+#define USBDCD_BWR_TIMER2_BC11_CHECK_DM(base, value) (USBDCD_WR_TIMER2_BC11_CHECK_DM(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW)
+ *
+ * Sets the time period (ms) that the module waits after charging port detection
+ * before system software must enable the D+ pullup to connect to the USB host.
+ * Valid values are 1-1023, but the USB Battery Charging Specification requires a
+ * minimum value of 40 ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field. */
+#define USBDCD_RD_TIMER2_BC11_TVDPSRC_CON(base) ((USBDCD_TIMER2_BC11_REG(base) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) >> USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)
+#define USBDCD_BRD_TIMER2_BC11_TVDPSRC_CON(base) (USBDCD_RD_TIMER2_BC11_TVDPSRC_CON(base))
+
+/*! @brief Set the TVDPSRC_CON field to a new value. */
+#define USBDCD_WR_TIMER2_BC11_TVDPSRC_CON(base, value) (USBDCD_RMW_TIMER2_BC11(base, USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK, USBDCD_TIMER2_BC11_TVDPSRC_CON(value)))
+#define USBDCD_BWR_TIMER2_BC11_TVDPSRC_CON(base, value) (USBDCD_WR_TIMER2_BC11_TVDPSRC_CON(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW)
+ *
+ * Reset value: 0x00010028U
+ *
+ * TIMER2_BC12 contains timing parameters for USB Battery Charging
+ * Specification, v1.2. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC12 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER2_BC12(base) (USBDCD_TIMER2_BC12_REG(base))
+#define USBDCD_WR_TIMER2_BC12(base, value) (USBDCD_TIMER2_BC12_REG(base) = (value))
+#define USBDCD_RMW_TIMER2_BC12(base, mask, value) (USBDCD_WR_TIMER2_BC12(base, (USBDCD_RD_TIMER2_BC12(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) |  (value)))
+#define USBDCD_CLR_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) & ~(value)))
+#define USBDCD_TOG_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid
+ * values are 0-40ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field. */
+#define USBDCD_RD_TIMER2_BC12_TVDMSRC_ON(base) ((USBDCD_TIMER2_BC12_REG(base) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) >> USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)
+#define USBDCD_BRD_TIMER2_BC12_TVDMSRC_ON(base) (USBDCD_RD_TIMER2_BC12_TVDMSRC_ON(base))
+
+/*! @brief Set the TVDMSRC_ON field to a new value. */
+#define USBDCD_WR_TIMER2_BC12_TVDMSRC_ON(base, value) (USBDCD_RMW_TIMER2_BC12(base, USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK, USBDCD_TIMER2_BC12_TVDMSRC_ON(value)))
+#define USBDCD_BWR_TIMER2_BC12_TVDMSRC_ON(base, value) (USBDCD_WR_TIMER2_BC12_TVDMSRC_ON(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after primary detection
+ * before start to secondary detection. Valid values are 1-1023ms. Default is
+ * 1ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field. */
+#define USBDCD_RD_TIMER2_BC12_TWAIT_AFTER_PRD(base) ((USBDCD_TIMER2_BC12_REG(base) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) >> USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)
+#define USBDCD_BRD_TIMER2_BC12_TWAIT_AFTER_PRD(base) (USBDCD_RD_TIMER2_BC12_TWAIT_AFTER_PRD(base))
+
+/*! @brief Set the TWAIT_AFTER_PRD field to a new value. */
+#define USBDCD_WR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value) (USBDCD_RMW_TIMER2_BC12(base, USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK, USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(value)))
+#define USBDCD_BWR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value) (USBDCD_WR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value))
+/*@}*/
+
+/*
+ * MK64F12 VREF
+ *
+ * Voltage Reference
+ *
+ * Registers defined in this header file:
+ * - VREF_TRM - VREF Trim Register
+ * - VREF_SC - VREF Status and Control Register
+ */
+
+#define VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
+#define VREF_IDX (0U) /*!< Instance number for VREF. */
+
+/*******************************************************************************
+ * VREF_TRM - VREF Trim Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_TRM - VREF Trim Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains bits that contain the trim data for the Voltage
+ * Reference.
+ */
+/*!
+ * @name Constants and macros for entire VREF_TRM register
+ */
+/*@{*/
+#define VREF_RD_TRM(base)        (VREF_TRM_REG(base))
+#define VREF_WR_TRM(base, value) (VREF_TRM_REG(base) = (value))
+#define VREF_RMW_TRM(base, mask, value) (VREF_WR_TRM(base, (VREF_RD_TRM(base) & ~(mask)) | (value)))
+#define VREF_SET_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) |  (value)))
+#define VREF_CLR_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) & ~(value)))
+#define VREF_TOG_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_TRM bitfields
+ */
+
+/*!
+ * @name Register VREF_TRM, field TRIM[5:0] (RW)
+ *
+ * These bits change the resulting VREF by approximately +/- 0.5 mV for each
+ * step. Min = minimum and max = maximum voltage reference output. For minimum and
+ * maximum voltage reference output values, refer to the Data Sheet for this chip.
+ *
+ * Values:
+ * - 0b000000 - Min
+ * - 0b111111 - Max
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_TRIM field. */
+#define VREF_RD_TRM_TRIM(base) ((VREF_TRM_REG(base) & VREF_TRM_TRIM_MASK) >> VREF_TRM_TRIM_SHIFT)
+#define VREF_BRD_TRM_TRIM(base) (VREF_RD_TRM_TRIM(base))
+
+/*! @brief Set the TRIM field to a new value. */
+#define VREF_WR_TRM_TRIM(base, value) (VREF_RMW_TRM(base, VREF_TRM_TRIM_MASK, VREF_TRM_TRIM(value)))
+#define VREF_BWR_TRM_TRIM(base, value) (VREF_WR_TRM_TRIM(base, value))
+/*@}*/
+
+/*!
+ * @name Register VREF_TRM, field CHOPEN[6] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0b0 - Chop oscillator is disabled.
+ * - 0b1 - Chop oscillator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_CHOPEN field. */
+#define VREF_RD_TRM_CHOPEN(base) ((VREF_TRM_REG(base) & VREF_TRM_CHOPEN_MASK) >> VREF_TRM_CHOPEN_SHIFT)
+#define VREF_BRD_TRM_CHOPEN(base) (BITBAND_ACCESS8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT))
+
+/*! @brief Set the CHOPEN field to a new value. */
+#define VREF_WR_TRM_CHOPEN(base, value) (VREF_RMW_TRM(base, VREF_TRM_CHOPEN_MASK, VREF_TRM_CHOPEN(value)))
+#define VREF_BWR_TRM_CHOPEN(base, value) (BITBAND_ACCESS8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * VREF_SC - VREF Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_SC - VREF Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the control bits used to enable the internal voltage
+ * reference and to select the buffer mode to be used.
+ */
+/*!
+ * @name Constants and macros for entire VREF_SC register
+ */
+/*@{*/
+#define VREF_RD_SC(base)         (VREF_SC_REG(base))
+#define VREF_WR_SC(base, value)  (VREF_SC_REG(base) = (value))
+#define VREF_RMW_SC(base, mask, value) (VREF_WR_SC(base, (VREF_RD_SC(base) & ~(mask)) | (value)))
+#define VREF_SET_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) |  (value)))
+#define VREF_CLR_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) & ~(value)))
+#define VREF_TOG_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_SC bitfields
+ */
+
+/*!
+ * @name Register VREF_SC, field MODE_LV[1:0] (RW)
+ *
+ * These bits select the buffer modes for the Voltage Reference module.
+ *
+ * Values:
+ * - 0b00 - Bandgap on only, for stabilization and startup
+ * - 0b01 - High power buffer mode enabled
+ * - 0b10 - Low-power buffer mode enabled
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_MODE_LV field. */
+#define VREF_RD_SC_MODE_LV(base) ((VREF_SC_REG(base) & VREF_SC_MODE_LV_MASK) >> VREF_SC_MODE_LV_SHIFT)
+#define VREF_BRD_SC_MODE_LV(base) (VREF_RD_SC_MODE_LV(base))
+
+/*! @brief Set the MODE_LV field to a new value. */
+#define VREF_WR_SC_MODE_LV(base, value) (VREF_RMW_SC(base, VREF_SC_MODE_LV_MASK, VREF_SC_MODE_LV(value)))
+#define VREF_BWR_SC_MODE_LV(base, value) (VREF_WR_SC_MODE_LV(base, value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFST[2] (RO)
+ *
+ * This bit indicates that the bandgap reference within the Voltage Reference
+ * module has completed its startup and stabilization.
+ *
+ * Values:
+ * - 0b0 - The module is disabled or not stable.
+ * - 0b1 - The module is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFST field. */
+#define VREF_RD_SC_VREFST(base) ((VREF_SC_REG(base) & VREF_SC_VREFST_MASK) >> VREF_SC_VREFST_SHIFT)
+#define VREF_BRD_SC_VREFST(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field ICOMPEN[5] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_ICOMPEN field. */
+#define VREF_RD_SC_ICOMPEN(base) ((VREF_SC_REG(base) & VREF_SC_ICOMPEN_MASK) >> VREF_SC_ICOMPEN_SHIFT)
+#define VREF_BRD_SC_ICOMPEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT))
+
+/*! @brief Set the ICOMPEN field to a new value. */
+#define VREF_WR_SC_ICOMPEN(base, value) (VREF_RMW_SC(base, VREF_SC_ICOMPEN_MASK, VREF_SC_ICOMPEN(value)))
+#define VREF_BWR_SC_ICOMPEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field REGEN[6] (RW)
+ *
+ * This bit is used to enable the internal 1.75 V regulator to produce a
+ * constant internal voltage supply in order to reduce the sensitivity to external
+ * supply noise and variation. If it is desired to keep the regulator enabled in very
+ * low power modes, refer to the Chip Configuration details for a description on
+ * how this can be achieved. This bit is set during factory trimming of the VREF
+ * voltage. This bit should be written to 1 to achieve the performance stated in
+ * the data sheet.
+ *
+ * Values:
+ * - 0b0 - Internal 1.75 V regulator is disabled.
+ * - 0b1 - Internal 1.75 V regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_REGEN field. */
+#define VREF_RD_SC_REGEN(base) ((VREF_SC_REG(base) & VREF_SC_REGEN_MASK) >> VREF_SC_REGEN_SHIFT)
+#define VREF_BRD_SC_REGEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT))
+
+/*! @brief Set the REGEN field to a new value. */
+#define VREF_WR_SC_REGEN(base, value) (VREF_RMW_SC(base, VREF_SC_REGEN_MASK, VREF_SC_REGEN(value)))
+#define VREF_BWR_SC_REGEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFEN[7] (RW)
+ *
+ * This bit is used to enable the bandgap reference within the Voltage Reference
+ * module. After the VREF is enabled, turning off the clock to the VREF module
+ * via the corresponding clock gate register will not disable the VREF. VREF must
+ * be disabled via this VREFEN bit.
+ *
+ * Values:
+ * - 0b0 - The module is disabled.
+ * - 0b1 - The module is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFEN field. */
+#define VREF_RD_SC_VREFEN(base) ((VREF_SC_REG(base) & VREF_SC_VREFEN_MASK) >> VREF_SC_VREFEN_SHIFT)
+#define VREF_BRD_SC_VREFEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT))
+
+/*! @brief Set the VREFEN field to a new value. */
+#define VREF_WR_SC_VREFEN(base, value) (VREF_RMW_SC(base, VREF_SC_VREFEN_MASK, VREF_SC_VREFEN(value)))
+#define VREF_BWR_SC_VREFEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 WDOG
+ *
+ * Generation 2008 Watchdog Timer
+ *
+ * Registers defined in this header file:
+ * - WDOG_STCTRLH - Watchdog Status and Control Register High
+ * - WDOG_STCTRLL - Watchdog Status and Control Register Low
+ * - WDOG_TOVALH - Watchdog Time-out Value Register High
+ * - WDOG_TOVALL - Watchdog Time-out Value Register Low
+ * - WDOG_WINH - Watchdog Window Register High
+ * - WDOG_WINL - Watchdog Window Register Low
+ * - WDOG_REFRESH - Watchdog Refresh register
+ * - WDOG_UNLOCK - Watchdog Unlock register
+ * - WDOG_TMROUTH - Watchdog Timer Output Register High
+ * - WDOG_TMROUTL - Watchdog Timer Output Register Low
+ * - WDOG_RSTCNT - Watchdog Reset Count register
+ * - WDOG_PRESC - Watchdog Prescaler register
+ */
+
+#define WDOG_INSTANCE_COUNT (1U) /*!< Number of instances of the WDOG module. */
+#define WDOG_IDX (0U) /*!< Instance number for WDOG. */
+
+/*******************************************************************************
+ * WDOG_STCTRLH - Watchdog Status and Control Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
+ *
+ * Reset value: 0x01D3U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLH register
+ */
+/*@{*/
+#define WDOG_RD_STCTRLH(base)    (WDOG_STCTRLH_REG(base))
+#define WDOG_WR_STCTRLH(base, value) (WDOG_STCTRLH_REG(base) = (value))
+#define WDOG_RMW_STCTRLH(base, mask, value) (WDOG_WR_STCTRLH(base, (WDOG_RD_STCTRLH(base) & ~(mask)) | (value)))
+#define WDOG_SET_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) |  (value)))
+#define WDOG_CLR_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) & ~(value)))
+#define WDOG_TOG_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_STCTRLH bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
+ *
+ * Enables or disables the WDOG's operation. In the disabled state, the watchdog
+ * timer is kept in the reset state, but the other exception conditions can
+ * still trigger a reset/interrupt. A change in the value of this bit must be held
+ * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled.
+ * - 0b1 - WDOG is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. */
+#define WDOG_RD_STCTRLH_WDOGEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WDOGEN_MASK) >> WDOG_STCTRLH_WDOGEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WDOGEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WDOGEN_SHIFT))
+
+/*! @brief Set the WDOGEN field to a new value. */
+#define WDOG_WR_STCTRLH_WDOGEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WDOGEN_MASK, WDOG_STCTRLH_WDOGEN(value)))
+#define WDOG_BWR_STCTRLH_WDOGEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WDOGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
+ *
+ * Selects clock source for the WDOG timer and other internal timing operations.
+ *
+ * Values:
+ * - 0b0 - WDOG clock sourced from LPO .
+ * - 0b1 - WDOG clock sourced from alternate clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. */
+#define WDOG_RD_STCTRLH_CLKSRC(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_CLKSRC_MASK) >> WDOG_STCTRLH_CLKSRC_SHIFT)
+#define WDOG_BRD_STCTRLH_CLKSRC(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_CLKSRC_SHIFT))
+
+/*! @brief Set the CLKSRC field to a new value. */
+#define WDOG_WR_STCTRLH_CLKSRC(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_CLKSRC_MASK, WDOG_STCTRLH_CLKSRC(value)))
+#define WDOG_BWR_STCTRLH_CLKSRC(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_CLKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
+ *
+ * Used to enable the debug breadcrumbs feature. A change in this bit is updated
+ * immediately, as opposed to updating after WCT.
+ *
+ * Values:
+ * - 0b0 - WDOG time-out generates reset only.
+ * - 0b1 - WDOG time-out initially generates an interrupt. After WCT, it
+ *     generates a reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. */
+#define WDOG_RD_STCTRLH_IRQRSTEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_IRQRSTEN_MASK) >> WDOG_STCTRLH_IRQRSTEN_SHIFT)
+#define WDOG_BRD_STCTRLH_IRQRSTEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_IRQRSTEN_SHIFT))
+
+/*! @brief Set the IRQRSTEN field to a new value. */
+#define WDOG_WR_STCTRLH_IRQRSTEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_IRQRSTEN_MASK, WDOG_STCTRLH_IRQRSTEN(value)))
+#define WDOG_BWR_STCTRLH_IRQRSTEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_IRQRSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
+ *
+ * Enables Windowing mode.
+ *
+ * Values:
+ * - 0b0 - Windowing mode is disabled.
+ * - 0b1 - Windowing mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WINEN field. */
+#define WDOG_RD_STCTRLH_WINEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WINEN_MASK) >> WDOG_STCTRLH_WINEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WINEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WINEN_SHIFT))
+
+/*! @brief Set the WINEN field to a new value. */
+#define WDOG_WR_STCTRLH_WINEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WINEN_MASK, WDOG_STCTRLH_WINEN(value)))
+#define WDOG_BWR_STCTRLH_WINEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WINEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
+ *
+ * Enables updates to watchdog write-once registers, after the reset-triggered
+ * initial configuration window (WCT) closes, through unlock sequence.
+ *
+ * Values:
+ * - 0b0 - No further updates allowed to WDOG write-once registers.
+ * - 0b1 - WDOG write-once registers can be unlocked for updating.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. */
+#define WDOG_RD_STCTRLH_ALLOWUPDATE(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_ALLOWUPDATE_MASK) >> WDOG_STCTRLH_ALLOWUPDATE_SHIFT)
+#define WDOG_BRD_STCTRLH_ALLOWUPDATE(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_ALLOWUPDATE_SHIFT))
+
+/*! @brief Set the ALLOWUPDATE field to a new value. */
+#define WDOG_WR_STCTRLH_ALLOWUPDATE(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_ALLOWUPDATE_MASK, WDOG_STCTRLH_ALLOWUPDATE(value)))
+#define WDOG_BWR_STCTRLH_ALLOWUPDATE(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_ALLOWUPDATE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
+ *
+ * Enables or disables WDOG in Debug mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Debug mode.
+ * - 0b1 - WDOG is enabled in CPU Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_DBGEN field. */
+#define WDOG_RD_STCTRLH_DBGEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_DBGEN_MASK) >> WDOG_STCTRLH_DBGEN_SHIFT)
+#define WDOG_BRD_STCTRLH_DBGEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DBGEN_SHIFT))
+
+/*! @brief Set the DBGEN field to a new value. */
+#define WDOG_WR_STCTRLH_DBGEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_DBGEN_MASK, WDOG_STCTRLH_DBGEN(value)))
+#define WDOG_BWR_STCTRLH_DBGEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DBGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
+ *
+ * Enables or disables WDOG in Stop mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Stop mode.
+ * - 0b1 - WDOG is enabled in CPU Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_STOPEN field. */
+#define WDOG_RD_STCTRLH_STOPEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_STOPEN_MASK) >> WDOG_STCTRLH_STOPEN_SHIFT)
+#define WDOG_BRD_STCTRLH_STOPEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_STOPEN_SHIFT))
+
+/*! @brief Set the STOPEN field to a new value. */
+#define WDOG_WR_STCTRLH_STOPEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_STOPEN_MASK, WDOG_STCTRLH_STOPEN(value)))
+#define WDOG_BWR_STCTRLH_STOPEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_STOPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
+ *
+ * Enables or disables WDOG in Wait mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Wait mode.
+ * - 0b1 - WDOG is enabled in CPU Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WAITEN field. */
+#define WDOG_RD_STCTRLH_WAITEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WAITEN_MASK) >> WDOG_STCTRLH_WAITEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WAITEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WAITEN_SHIFT))
+
+/*! @brief Set the WAITEN field to a new value. */
+#define WDOG_WR_STCTRLH_WAITEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WAITEN_MASK, WDOG_STCTRLH_WAITEN(value)))
+#define WDOG_BWR_STCTRLH_WAITEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WAITEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
+ *
+ * Puts the watchdog in the functional test mode. In this mode, the watchdog
+ * timer and the associated compare and reset generation logic is tested for correct
+ * operation. The clock for the timer is switched from the main watchdog clock
+ * to the fast clock input for watchdog functional test. The TESTSEL bit selects
+ * the test to be run.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. */
+#define WDOG_RD_STCTRLH_TESTWDOG(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_TESTWDOG_MASK) >> WDOG_STCTRLH_TESTWDOG_SHIFT)
+#define WDOG_BRD_STCTRLH_TESTWDOG(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTWDOG_SHIFT))
+
+/*! @brief Set the TESTWDOG field to a new value. */
+#define WDOG_WR_STCTRLH_TESTWDOG(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_TESTWDOG_MASK, WDOG_STCTRLH_TESTWDOG(value)))
+#define WDOG_BWR_STCTRLH_TESTWDOG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTWDOG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
+ *
+ * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
+ * timer.
+ *
+ * Values:
+ * - 0b0 - Quick test. The timer runs in normal operation. You can load a small
+ *     time-out value to do a quick test.
+ * - 0b1 - Byte test. Puts the timer in the byte test mode where individual
+ *     bytes of the timer are enabled for operation and are compared for time-out
+ *     against the corresponding byte of the programmed time-out value. Select the
+ *     byte through BYTESEL[1:0] for testing.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. */
+#define WDOG_RD_STCTRLH_TESTSEL(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_TESTSEL_MASK) >> WDOG_STCTRLH_TESTSEL_SHIFT)
+#define WDOG_BRD_STCTRLH_TESTSEL(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTSEL_SHIFT))
+
+/*! @brief Set the TESTSEL field to a new value. */
+#define WDOG_WR_STCTRLH_TESTSEL(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_TESTSEL_MASK, WDOG_STCTRLH_TESTSEL(value)))
+#define WDOG_BWR_STCTRLH_TESTSEL(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
+ *
+ * This 2-bit field selects the byte to be tested when the watchdog is in the
+ * byte test mode.
+ *
+ * Values:
+ * - 0b00 - Byte 0 selected
+ * - 0b01 - Byte 1 selected
+ * - 0b10 - Byte 2 selected
+ * - 0b11 - Byte 3 selected
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. */
+#define WDOG_RD_STCTRLH_BYTESEL(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_BYTESEL_MASK) >> WDOG_STCTRLH_BYTESEL_SHIFT)
+#define WDOG_BRD_STCTRLH_BYTESEL(base) (WDOG_RD_STCTRLH_BYTESEL(base))
+
+/*! @brief Set the BYTESEL field to a new value. */
+#define WDOG_WR_STCTRLH_BYTESEL(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_BYTESEL_MASK, WDOG_STCTRLH_BYTESEL(value)))
+#define WDOG_BWR_STCTRLH_BYTESEL(base, value) (WDOG_WR_STCTRLH_BYTESEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
+ *
+ * Allows the WDOG's functional test mode to be disabled permanently. After it
+ * is set, it can only be cleared by a reset. It cannot be unlocked for editing
+ * after it is set.
+ *
+ * Values:
+ * - 0b0 - WDOG functional test mode is not disabled.
+ * - 0b1 - WDOG functional test mode is disabled permanently until reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. */
+#define WDOG_RD_STCTRLH_DISTESTWDOG(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_DISTESTWDOG_MASK) >> WDOG_STCTRLH_DISTESTWDOG_SHIFT)
+#define WDOG_BRD_STCTRLH_DISTESTWDOG(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DISTESTWDOG_SHIFT))
+
+/*! @brief Set the DISTESTWDOG field to a new value. */
+#define WDOG_WR_STCTRLH_DISTESTWDOG(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_DISTESTWDOG_MASK, WDOG_STCTRLH_DISTESTWDOG(value)))
+#define WDOG_BWR_STCTRLH_DISTESTWDOG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DISTESTWDOG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_STCTRLL - Watchdog Status and Control Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
+ *
+ * Reset value: 0x0001U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLL register
+ */
+/*@{*/
+#define WDOG_RD_STCTRLL(base)    (WDOG_STCTRLL_REG(base))
+#define WDOG_WR_STCTRLL(base, value) (WDOG_STCTRLL_REG(base) = (value))
+#define WDOG_RMW_STCTRLL(base, mask, value) (WDOG_WR_STCTRLL(base, (WDOG_RD_STCTRLL(base) & ~(mask)) | (value)))
+#define WDOG_SET_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) |  (value)))
+#define WDOG_CLR_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) & ~(value)))
+#define WDOG_TOG_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_STCTRLL bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
+ *
+ * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
+ * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
+ * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
+ * bit. It also gets cleared on a system reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLL_INTFLG field. */
+#define WDOG_RD_STCTRLL_INTFLG(base) ((WDOG_STCTRLL_REG(base) & WDOG_STCTRLL_INTFLG_MASK) >> WDOG_STCTRLL_INTFLG_SHIFT)
+#define WDOG_BRD_STCTRLL_INTFLG(base) (BITBAND_ACCESS16(&WDOG_STCTRLL_REG(base), WDOG_STCTRLL_INTFLG_SHIFT))
+
+/*! @brief Set the INTFLG field to a new value. */
+#define WDOG_WR_STCTRLL_INTFLG(base, value) (WDOG_RMW_STCTRLL(base, WDOG_STCTRLL_INTFLG_MASK, WDOG_STCTRLL_INTFLG(value)))
+#define WDOG_BWR_STCTRLL_INTFLG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLL_REG(base), WDOG_STCTRLL_INTFLG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TOVALH - Watchdog Time-out Value Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
+ *
+ * Reset value: 0x004CU
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TOVALH register
+ */
+/*@{*/
+#define WDOG_RD_TOVALH(base)     (WDOG_TOVALH_REG(base))
+#define WDOG_WR_TOVALH(base, value) (WDOG_TOVALH_REG(base) = (value))
+#define WDOG_RMW_TOVALH(base, mask, value) (WDOG_WR_TOVALH(base, (WDOG_RD_TOVALH(base) & ~(mask)) | (value)))
+#define WDOG_SET_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) |  (value)))
+#define WDOG_CLR_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) & ~(value)))
+#define WDOG_TOG_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TOVALL - Watchdog Time-out Value Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
+ *
+ * Reset value: 0x4B4CU
+ *
+ * The time-out value of the watchdog must be set to a minimum of four watchdog
+ * clock cycles. This is to take into account the delay in new settings taking
+ * effect in the watchdog clock domain.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TOVALL register
+ */
+/*@{*/
+#define WDOG_RD_TOVALL(base)     (WDOG_TOVALL_REG(base))
+#define WDOG_WR_TOVALL(base, value) (WDOG_TOVALL_REG(base) = (value))
+#define WDOG_RMW_TOVALL(base, mask, value) (WDOG_WR_TOVALL(base, (WDOG_RD_TOVALL(base) & ~(mask)) | (value)))
+#define WDOG_SET_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) |  (value)))
+#define WDOG_CLR_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) & ~(value)))
+#define WDOG_TOG_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_WINH - Watchdog Window Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_WINH - Watchdog Window Register High (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_WINH register
+ */
+/*@{*/
+#define WDOG_RD_WINH(base)       (WDOG_WINH_REG(base))
+#define WDOG_WR_WINH(base, value) (WDOG_WINH_REG(base) = (value))
+#define WDOG_RMW_WINH(base, mask, value) (WDOG_WR_WINH(base, (WDOG_RD_WINH(base) & ~(mask)) | (value)))
+#define WDOG_SET_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) |  (value)))
+#define WDOG_CLR_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) & ~(value)))
+#define WDOG_TOG_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_WINL - Watchdog Window Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_WINL - Watchdog Window Register Low (RW)
+ *
+ * Reset value: 0x0010U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_WINL register
+ */
+/*@{*/
+#define WDOG_RD_WINL(base)       (WDOG_WINL_REG(base))
+#define WDOG_WR_WINL(base, value) (WDOG_WINL_REG(base) = (value))
+#define WDOG_RMW_WINL(base, mask, value) (WDOG_WR_WINL(base, (WDOG_RD_WINL(base) & ~(mask)) | (value)))
+#define WDOG_SET_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) |  (value)))
+#define WDOG_CLR_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) & ~(value)))
+#define WDOG_TOG_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_REFRESH - Watchdog Refresh register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_REFRESH - Watchdog Refresh register (RW)
+ *
+ * Reset value: 0xB480U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_REFRESH register
+ */
+/*@{*/
+#define WDOG_RD_REFRESH(base)    (WDOG_REFRESH_REG(base))
+#define WDOG_WR_REFRESH(base, value) (WDOG_REFRESH_REG(base) = (value))
+#define WDOG_RMW_REFRESH(base, mask, value) (WDOG_WR_REFRESH(base, (WDOG_RD_REFRESH(base) & ~(mask)) | (value)))
+#define WDOG_SET_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) |  (value)))
+#define WDOG_CLR_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) & ~(value)))
+#define WDOG_TOG_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_UNLOCK - Watchdog Unlock register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_UNLOCK - Watchdog Unlock register (RW)
+ *
+ * Reset value: 0xD928U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_UNLOCK register
+ */
+/*@{*/
+#define WDOG_RD_UNLOCK(base)     (WDOG_UNLOCK_REG(base))
+#define WDOG_WR_UNLOCK(base, value) (WDOG_UNLOCK_REG(base) = (value))
+#define WDOG_RMW_UNLOCK(base, mask, value) (WDOG_WR_UNLOCK(base, (WDOG_RD_UNLOCK(base) & ~(mask)) | (value)))
+#define WDOG_SET_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) |  (value)))
+#define WDOG_CLR_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) & ~(value)))
+#define WDOG_TOG_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TMROUTH - Watchdog Timer Output Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTH register
+ */
+/*@{*/
+#define WDOG_RD_TMROUTH(base)    (WDOG_TMROUTH_REG(base))
+#define WDOG_WR_TMROUTH(base, value) (WDOG_TMROUTH_REG(base) = (value))
+#define WDOG_RMW_TMROUTH(base, mask, value) (WDOG_WR_TMROUTH(base, (WDOG_RD_TMROUTH(base) & ~(mask)) | (value)))
+#define WDOG_SET_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) |  (value)))
+#define WDOG_CLR_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) & ~(value)))
+#define WDOG_TOG_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TMROUTL - Watchdog Timer Output Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
+ * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
+ * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
+ * the watchdog timer.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTL register
+ */
+/*@{*/
+#define WDOG_RD_TMROUTL(base)    (WDOG_TMROUTL_REG(base))
+#define WDOG_WR_TMROUTL(base, value) (WDOG_TMROUTL_REG(base) = (value))
+#define WDOG_RMW_TMROUTL(base, mask, value) (WDOG_WR_TMROUTL(base, (WDOG_RD_TMROUTL(base) & ~(mask)) | (value)))
+#define WDOG_SET_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) |  (value)))
+#define WDOG_CLR_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) & ~(value)))
+#define WDOG_TOG_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_RSTCNT - Watchdog Reset Count register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_RSTCNT - Watchdog Reset Count register (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_RSTCNT register
+ */
+/*@{*/
+#define WDOG_RD_RSTCNT(base)     (WDOG_RSTCNT_REG(base))
+#define WDOG_WR_RSTCNT(base, value) (WDOG_RSTCNT_REG(base) = (value))
+#define WDOG_RMW_RSTCNT(base, mask, value) (WDOG_WR_RSTCNT(base, (WDOG_RD_RSTCNT(base) & ~(mask)) | (value)))
+#define WDOG_SET_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) |  (value)))
+#define WDOG_CLR_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) & ~(value)))
+#define WDOG_TOG_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_PRESC - Watchdog Prescaler register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_PRESC - Watchdog Prescaler register (RW)
+ *
+ * Reset value: 0x0400U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_PRESC register
+ */
+/*@{*/
+#define WDOG_RD_PRESC(base)      (WDOG_PRESC_REG(base))
+#define WDOG_WR_PRESC(base, value) (WDOG_PRESC_REG(base) = (value))
+#define WDOG_RMW_PRESC(base, mask, value) (WDOG_WR_PRESC(base, (WDOG_RD_PRESC(base) & ~(mask)) | (value)))
+#define WDOG_SET_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) |  (value)))
+#define WDOG_CLR_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) & ~(value)))
+#define WDOG_TOG_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_PRESC bitfields
+ */
+
+/*!
+ * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
+ *
+ * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
+ * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
+ * 1) to provide the prescaled WDOG_CLK.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_PRESC_PRESCVAL field. */
+#define WDOG_RD_PRESC_PRESCVAL(base) ((WDOG_PRESC_REG(base) & WDOG_PRESC_PRESCVAL_MASK) >> WDOG_PRESC_PRESCVAL_SHIFT)
+#define WDOG_BRD_PRESC_PRESCVAL(base) (WDOG_RD_PRESC_PRESCVAL(base))
+
+/*! @brief Set the PRESCVAL field to a new value. */
+#define WDOG_WR_PRESC_PRESCVAL(base, value) (WDOG_RMW_PRESC(base, WDOG_PRESC_PRESCVAL_MASK, WDOG_PRESC_PRESCVAL(value)))
+#define WDOG_BWR_PRESC_PRESCVAL(base, value) (WDOG_WR_PRESC_PRESCVAL(base, value))
+/*@}*/
+
+/* Instance numbers for core modules */
+#define JTAG_IDX (0) /*!< Instance number for JTAG. */
+#define TPIU_IDX (0) /*!< Instance number for TPIU. */
+#define SCB_IDX (0) /*!< Instance number for SCB. */
+#define CoreDebug_IDX (0) /*!< Instance number for CoreDebug. */
+
+#if defined(__IAR_SYSTEMS_ICC__)
+  /* Restore checking of "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)" */
+  #pragma diag_default=pm008
+#endif
+
+#endif /* __MK64F12_EXTENSION_H__ */
+/* EOF */
diff --git a/Workspace/GPIO/SDK/platform/devices/MK64F12/include/MK64F12_features.h b/Workspace/GPIO/SDK/platform/devices/MK64F12/include/MK64F12_features.h
new file mode 100644
index 0000000..9c826df
--- /dev/null
+++ b/Workspace/GPIO/SDK/platform/devices/MK64F12/include/MK64F12_features.h
@@ -0,0 +1,1901 @@
+/*
+** ###################################################################
+**     Version:             rev. 2.14, 2015-06-08
+**     Build:               b150715
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-01-30)
+**         Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.6 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.7 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.8 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.9 (2015-01-21)
+**         Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
+**     - rev. 2.10 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**     - rev. 2.11 (2015-05-19)
+**         FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
+**         Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
+**         Added features for PDB and PORT.
+**     - rev. 2.12 (2015-05-25)
+**         Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
+**     - rev. 2.13 (2015-05-27)
+**         Several USB features added.
+**     - rev. 2.14 (2015-06-08)
+**         FTM features BUS_CLOCK and FAST_CLOCK removed.
+**
+** ###################################################################
+*/
+
+#if !defined(__FSL_MK64F12_FEATURES_H__)
+#define __FSL_MK64F12_FEATURES_H__
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* FLEXCAN module features */
+
+/* @brief Message buffer size */
+#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
+/* @brief Has doze mode support (register bit field MCR[DOZE]). */
+#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
+/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
+#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
+/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
+/* @brief Has extended bit timing register (register CBT). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
+/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
+#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
+/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
+#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
+/* @brief Number of interrupt vectors. */
+#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* SOC module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief ACMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_ACMP_COUNT (0)
+    /* @brief ADC16 availability on the SoC. */
+    #define FSL_FEATURE_SOC_ADC16_COUNT (2)
+    /* @brief AFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_AFE_COUNT (0)
+    /* @brief AIPS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AIPS_COUNT (2)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (0)
+    /* @brief AXBS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AXBS_COUNT (1)
+    /* @brief CADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CADC_COUNT (0)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief MMCAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
+    /* @brief CMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMP_COUNT (3)
+    /* @brief CMT availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMT_COUNT (1)
+    /* @brief CNC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CNC_COUNT (0)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief DAC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DAC_COUNT (2)
+    /* @brief DCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DCDC_COUNT (0)
+    /* @brief DDR availability on the SoC. */
+    #define FSL_FEATURE_SOC_DDR_COUNT (0)
+    /* @brief DMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMA_COUNT (0)
+    /* @brief DMAMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+    /* @brief DRY availability on the SoC. */
+    #define FSL_FEATURE_SOC_DRY_COUNT (0)
+    /* @brief DSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_DSPI_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EMVSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+    /* @brief ENC availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENC_COUNT (0)
+    /* @brief ENET availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENET_COUNT (1)
+    /* @brief EWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EWM_COUNT (1)
+    /* @brief FB availability on the SoC. */
+    #define FSL_FEATURE_SOC_FB_COUNT (1)
+    /* @brief FGPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+    /* @brief FLEXIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FSKDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+    /* @brief FTFA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFA_COUNT (0)
+    /* @brief FTFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFE_COUNT (1)
+    /* @brief FTFL availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFL_COUNT (0)
+    /* @brief FTM availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTM_COUNT (4)
+    /* @brief FTMRA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+    /* @brief FTMRE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+    /* @brief FTMRH availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief HSADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_HSADC_COUNT (0)
+    /* @brief I2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2C_COUNT (3)
+    /* @brief I2S availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2S_COUNT (1)
+    /* @brief ICS availability on the SoC. */
+    #define FSL_FEATURE_SOC_ICS_COUNT (0)
+    /* @brief IRQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_IRQ_COUNT (0)
+    /* @brief KBI availability on the SoC. */
+    #define FSL_FEATURE_SOC_KBI_COUNT (0)
+    /* @brief SLCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_SLCD_COUNT (0)
+    /* @brief LCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LCDC_COUNT (0)
+    /* @brief LDO availability on the SoC. */
+    #define FSL_FEATURE_SOC_LDO_COUNT (0)
+    /* @brief LLWU availability on the SoC. */
+    #define FSL_FEATURE_SOC_LLWU_COUNT (1)
+    /* @brief LMEM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LMEM_COUNT (0)
+    /* @brief LPSCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPTPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (0)
+    /* @brief LTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LTC_COUNT (0)
+    /* @brief MC availability on the SoC. */
+    #define FSL_FEATURE_SOC_MC_COUNT (0)
+    /* @brief MCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCG_COUNT (1)
+    /* @brief MCGLITE availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+    /* @brief MCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCM_COUNT (1)
+    /* @brief MMAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMAU_COUNT (0)
+    /* @brief MMDVSQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+    /* @brief MPU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MPU_COUNT (1)
+    /* @brief MSCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+    /* @brief MTB availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTB_COUNT (0)
+    /* @brief MTBDWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
+    /* @brief NFC availability on the SoC. */
+    #define FSL_FEATURE_SOC_NFC_COUNT (0)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+    /* @brief OSC availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSC_COUNT (1)
+    /* @brief OTFAD availability on the SoC. */
+    #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+    /* @brief PDB availability on the SoC. */
+    #define FSL_FEATURE_SOC_PDB_COUNT (1)
+    /* @brief PGA availability on the SoC. */
+    #define FSL_FEATURE_SOC_PGA_COUNT (0)
+    /* @brief PIT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PIT_COUNT (1)
+    /* @brief PMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_PMC_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (0)
+    /* @brief PWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWT_COUNT (0)
+    /* @brief QuadSPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+    /* @brief RCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RCM_COUNT (1)
+    /* @brief RFSYS availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+    /* @brief RFVBAT availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+    /* @brief RNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNG_COUNT (1)
+    /* @brief RNGB availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNGB_COUNT (0)
+    /* @brief ROM availability on the SoC. */
+    #define FSL_FEATURE_SOC_ROM_COUNT (0)
+    /* @brief RSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RSIM_COUNT (0)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCI_COUNT (0)
+    /* @brief SDHC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDHC_COUNT (1)
+    /* @brief SDRAM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+    /* @brief SIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SIM_COUNT (1)
+    /* @brief SMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMC_COUNT (1)
+    /* @brief SPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPI_COUNT (0)
+    /* @brief TMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_TMR_COUNT (0)
+    /* @brief TPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_TPM_COUNT (0)
+    /* @brief TRIAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+    /* @brief TRNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRNG_COUNT (0)
+    /* @brief TSI availability on the SoC. */
+    #define FSL_FEATURE_SOC_TSI_COUNT (0)
+    /* @brief UART availability on the SoC. */
+    #define FSL_FEATURE_SOC_UART_COUNT (6)
+    /* @brief USB availability on the SoC. */
+    #define FSL_FEATURE_SOC_USB_COUNT (1)
+    /* @brief USBDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+    /* @brief USBHSDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+    /* @brief USBPHY availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+    /* @brief VREF availability on the SoC. */
+    #define FSL_FEATURE_SOC_VREF_COUNT (1)
+    /* @brief WDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_WDOG_COUNT (1)
+    /* @brief XBAR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XBAR_COUNT (0)
+    /* @brief XCVR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XCVR_COUNT (0)
+    /* @brief ZLL availability on the SoC. */
+    #define FSL_FEATURE_SOC_ZLL_COUNT (0)
+#elif defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12)
+    /* @brief ACMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_ACMP_COUNT (0)
+    /* @brief ADC16 availability on the SoC. */
+    #define FSL_FEATURE_SOC_ADC16_COUNT (2)
+    /* @brief AFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_AFE_COUNT (0)
+    /* @brief AIPS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AIPS_COUNT (2)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (0)
+    /* @brief AXBS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AXBS_COUNT (1)
+    /* @brief CADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CADC_COUNT (0)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief MMCAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
+    /* @brief CMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMP_COUNT (3)
+    /* @brief CMT availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMT_COUNT (1)
+    /* @brief CNC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CNC_COUNT (0)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief DAC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DAC_COUNT (1)
+    /* @brief DCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DCDC_COUNT (0)
+    /* @brief DDR availability on the SoC. */
+    #define FSL_FEATURE_SOC_DDR_COUNT (0)
+    /* @brief DMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMA_COUNT (0)
+    /* @brief DMAMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+    /* @brief DRY availability on the SoC. */
+    #define FSL_FEATURE_SOC_DRY_COUNT (0)
+    /* @brief DSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_DSPI_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EMVSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+    /* @brief ENC availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENC_COUNT (0)
+    /* @brief ENET availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENET_COUNT (1)
+    /* @brief EWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EWM_COUNT (1)
+    /* @brief FB availability on the SoC. */
+    #define FSL_FEATURE_SOC_FB_COUNT (1)
+    /* @brief FGPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+    /* @brief FLEXIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FSKDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+    /* @brief FTFA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFA_COUNT (0)
+    /* @brief FTFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFE_COUNT (1)
+    /* @brief FTFL availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFL_COUNT (0)
+    /* @brief FTM availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTM_COUNT (4)
+    /* @brief FTMRA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+    /* @brief FTMRE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+    /* @brief FTMRH availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief HSADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_HSADC_COUNT (0)
+    /* @brief I2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2C_COUNT (3)
+    /* @brief I2S availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2S_COUNT (1)
+    /* @brief ICS availability on the SoC. */
+    #define FSL_FEATURE_SOC_ICS_COUNT (0)
+    /* @brief IRQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_IRQ_COUNT (0)
+    /* @brief KBI availability on the SoC. */
+    #define FSL_FEATURE_SOC_KBI_COUNT (0)
+    /* @brief SLCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_SLCD_COUNT (0)
+    /* @brief LCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LCDC_COUNT (0)
+    /* @brief LDO availability on the SoC. */
+    #define FSL_FEATURE_SOC_LDO_COUNT (0)
+    /* @brief LLWU availability on the SoC. */
+    #define FSL_FEATURE_SOC_LLWU_COUNT (1)
+    /* @brief LMEM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LMEM_COUNT (0)
+    /* @brief LPSCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPTPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (0)
+    /* @brief LTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LTC_COUNT (0)
+    /* @brief MC availability on the SoC. */
+    #define FSL_FEATURE_SOC_MC_COUNT (0)
+    /* @brief MCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCG_COUNT (1)
+    /* @brief MCGLITE availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+    /* @brief MCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCM_COUNT (1)
+    /* @brief MMAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMAU_COUNT (0)
+    /* @brief MMDVSQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+    /* @brief MPU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MPU_COUNT (1)
+    /* @brief MSCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+    /* @brief MTB availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTB_COUNT (0)
+    /* @brief MTBDWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
+    /* @brief NFC availability on the SoC. */
+    #define FSL_FEATURE_SOC_NFC_COUNT (0)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+    /* @brief OSC availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSC_COUNT (1)
+    /* @brief OTFAD availability on the SoC. */
+    #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+    /* @brief PDB availability on the SoC. */
+    #define FSL_FEATURE_SOC_PDB_COUNT (1)
+    /* @brief PGA availability on the SoC. */
+    #define FSL_FEATURE_SOC_PGA_COUNT (0)
+    /* @brief PIT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PIT_COUNT (1)
+    /* @brief PMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_PMC_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (0)
+    /* @brief PWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWT_COUNT (0)
+    /* @brief QuadSPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+    /* @brief RCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RCM_COUNT (1)
+    /* @brief RFSYS availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+    /* @brief RFVBAT availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+    /* @brief RNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNG_COUNT (1)
+    /* @brief RNGB availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNGB_COUNT (0)
+    /* @brief ROM availability on the SoC. */
+    #define FSL_FEATURE_SOC_ROM_COUNT (0)
+    /* @brief RSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RSIM_COUNT (0)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCI_COUNT (0)
+    /* @brief SDHC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDHC_COUNT (1)
+    /* @brief SDRAM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+    /* @brief SIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SIM_COUNT (1)
+    /* @brief SMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMC_COUNT (1)
+    /* @brief SPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPI_COUNT (0)
+    /* @brief TMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_TMR_COUNT (0)
+    /* @brief TPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_TPM_COUNT (0)
+    /* @brief TRIAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+    /* @brief TRNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRNG_COUNT (0)
+    /* @brief TSI availability on the SoC. */
+    #define FSL_FEATURE_SOC_TSI_COUNT (0)
+    /* @brief UART availability on the SoC. */
+    #define FSL_FEATURE_SOC_UART_COUNT (6)
+    /* @brief USB availability on the SoC. */
+    #define FSL_FEATURE_SOC_USB_COUNT (1)
+    /* @brief USBDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+    /* @brief USBHSDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+    /* @brief USBPHY availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+    /* @brief VREF availability on the SoC. */
+    #define FSL_FEATURE_SOC_VREF_COUNT (1)
+    /* @brief WDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_WDOG_COUNT (1)
+    /* @brief XBAR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XBAR_COUNT (0)
+    /* @brief XCVR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XCVR_COUNT (0)
+    /* @brief ZLL availability on the SoC. */
+    #define FSL_FEATURE_SOC_ZLL_COUNT (0)
+#endif
+
+/* CRC module features */
+
+/* @brief Has data register with name CRC */
+#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (DMA_INSTANCE_COUNT * 16)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (DMAMUX_INSTANCE_COUNT * 16)
+/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+
+/* ENET module features */
+
+/* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */
+#define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0)
+/* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */
+#define FSL_FEATURE_ENET_SUPPORT_PTP (1)
+/* @brief Number of associated interrupt vectors. */
+#define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
+/* @brief Errata 2597: No support for IEEE 1588 timestamp timer overflow interrupt. */
+#define FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT_ERRATA_2579 (0)
+/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
+#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
+
+/* EWM module features */
+
+/* @brief Has clock prescaler (register CLKPRESCALER). */
+#define FSL_FEATURE_EWM_HAS_PRESCALER  (0)
+
+/* FLEXBUS module features */
+
+/* No feature definitions */
+
+/* FLASH module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (0)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (1)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (131072)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00020000)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0001C000)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00018000)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00010000)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00000000)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00020000)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+#elif defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (0)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (1)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+#endif
+
+/* FTM module features */
+
+/* @brief Number of channels. */
+#define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
+#define FSL_FEATURE_FTM_CHANNEL_COUNTx { 8, 2, 2, 8 }
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
+
+/* SAI module features */
+
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+#define FSL_FEATURE_SAI_FIFO_COUNT (8)
+/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
+#define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
+#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
+/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
+#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
+/* @brief Ihe interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
+
+/* LLWU module features */
+
+/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+/* @brief Has pins 8-15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+/* @brief Maximum number of internal modules connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+/* @brief Number of digital filters. */
+#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+/* @brief Has MF5 register. */
+#define FSL_FEATURE_LLWU_HAS_MF (0)
+/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1)
+/* @brief Has external pin 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
+/* @brief Has external pin 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
+/* @brief Has external pin 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
+/* @brief Has external pin 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
+/* @brief Has external pin 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
+/* @brief Has external pin 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
+/* @brief Has external pin 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
+/* @brief Has external pin 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
+/* @brief Has external pin 8 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
+/* @brief Has external pin 9 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
+/* @brief Has external pin 10 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
+/* @brief Has external pin 11 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
+/* @brief Has external pin 12 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
+/* @brief Has external pin 13 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
+/* @brief Has external pin 14 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
+/* @brief Has external pin 15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
+/* @brief Has external pin 16 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+/* @brief Has external pin 17 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+/* @brief Has external pin 18 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+/* @brief Has external pin 19 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+/* @brief Has external pin 20 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+/* @brief Has external pin 21 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+/* @brief Has external pin 22 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+/* @brief Has external pin 23 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+/* @brief Has external pin 24 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+/* @brief Has external pin 25 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+/* @brief Has external pin 26 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+/* @brief Has external pin 27 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+/* @brief Has external pin 28 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+/* @brief Has external pin 29 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+/* @brief Has external pin 30 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+/* @brief Has external pin 31 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+/* @brief Has internal module 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+/* @brief Has internal module 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+/* @brief Has internal module 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+/* @brief Has internal module 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+/* @brief Has internal module 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
+/* @brief Has internal module 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+/* @brief Has internal module 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+/* @brief Has internal module 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+
+/* MCG module features */
+
+/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
+/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
+/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
+/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
+/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
+/* @brief The PLL clock is divided by 2 before VCO divider. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
+/* @brief FRDIV supports 1280. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
+/* @brief FRDIV supports 1536. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
+#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
+/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
+#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
+/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_PLL1 (0)
+/* @brief Has 48MHz internal oscillator. */
+#define FSL_FEATURE_MCG_HAS_IRC_48M (1)
+/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_OSC1 (0)
+/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
+#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
+/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
+#define FSL_FEATURE_MCG_HAS_LOLRE (1)
+/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
+#define FSL_FEATURE_MCG_USE_OSCSEL (1)
+/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
+#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
+/* @brief TBD */
+#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL (1)
+/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
+/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
+/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
+#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
+/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
+#define FSL_FEATURE_MCG_HAS_FLL (1)
+/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
+/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
+#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
+/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
+/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
+/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
+#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
+/* @brief Has external clock monitor (register bit C6[CME]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
+/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
+#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
+/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
+#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
+/* @brief Has PEI mode or PBI mode. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
+/* @brief Reset clock mode is BLPI. */
+#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
+
+/* MPU module features */
+
+/* @brief Specifies number of descriptors available. */
+#define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12)
+/* @brief Has process identifier support. */
+#define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1)
+/* @brief Has master 0. */
+#define FSL_FEATURE_MPU_HAS_MASTER0 (1)
+/* @brief Has master 1. */
+#define FSL_FEATURE_MPU_HAS_MASTER1 (1)
+/* @brief Has master 2. */
+#define FSL_FEATURE_MPU_HAS_MASTER2 (1)
+/* @brief Has master 3. */
+#define FSL_FEATURE_MPU_HAS_MASTER3 (1)
+/* @brief Has master 4. */
+#define FSL_FEATURE_MPU_HAS_MASTER4 (1)
+/* @brief Has master 5. */
+#define FSL_FEATURE_MPU_HAS_MASTER5 (1)
+/* @brief Has master 6. */
+#define FSL_FEATURE_MPU_HAS_MASTER6 (0)
+/* @brief Has master 7. */
+#define FSL_FEATURE_MPU_HAS_MASTER7 (0)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
+
+/* OSC module features */
+
+/* @brief Has OSC1 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC1 (0)
+/* @brief Has OSC0 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC0 (0)
+/* @brief Has OSC external oscillator (without index). */
+#define FSL_FEATURE_OSC_HAS_OSC (1)
+/* @brief Number of OSC external oscillators. */
+#define FSL_FEATURE_OSC_OSC_COUNT (1)
+/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
+#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
+
+/* PDB module features */
+
+/* @brief Define the count of supporting ADC pre-trigger for each channel. */
+#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2)
+/* @brief Has DAC support. */
+#define FSL_FEATURE_PDB_HAS_DAC (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (4)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (1)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (1)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (1)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (1)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (1)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (0)
+
+/* RTC module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \
+    defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12)
+    /* @brief Has wakeup pin (bit field CR[WPS]). */
+    #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+    /* @brief Has low power features (registers MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+    /* @brief Has read/write access control (registers WAR and RAR). */
+    #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+    /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_SECURITY (1)
+#elif defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief Has wakeup pin (bit field CR[WPS]). */
+    #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+    /* @brief Has low power features (registers MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+    /* @brief Has read/write access control (registers WAR and RAR). */
+    #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+    /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_SECURITY (0)
+#endif
+
+/* SDHC module features */
+
+/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
+#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1)
+/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
+#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0)
+/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
+#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (1)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
+
+/* DSPI module features */
+
+/* @brief Receive/transmit FIFO size in number of items. */
+#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
+#define FSL_FEATURE_DSPI_FIFO_SIZEx { 4, 1, 1 }
+/* @brief Maximum transfer data width in bits. */
+#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
+/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
+#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
+/* @brief Number of chip select pins. */
+#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
+/* @brief Has chip select strobe capability on the PCS5 pin. */
+#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
+/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+/* @brief Has 16-bit data transfer support. */
+#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (0) : \
+    ((x) == 2 ? (0) : (-1))))
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
+
+/* UART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_HAS_FIFO (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_UART_IS_SCI (0)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_FIFO_SIZE (8)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
+/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
+#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (1) : \
+    ((x) == 2 ? (1) : \
+    ((x) == 3 ? (1) : \
+    ((x) == 4 ? (0) : \
+    ((x) == 5 ? (0) : (-1)))))))
+
+/* USB module features */
+
+/* @brief HOST mode enabled */
+#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
+/* @brief OTG mode enabled */
+#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
+/* @brief Has KEEP_ALIVE_CTRL register */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
+/* @brief Has the Dynamic SOF threshold compare support */
+#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
+/* @brief Has the VBUS detect support */
+#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
+/* @brief Has the IRC48M module clock support */
+#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief Describes the set of SC[MODE_LV] bitfield values */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+
+/* WDOG module features */
+
+/* @brief Watchdog is available. */
+#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
+/* @brief Has Wait mode support. */
+#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
+
+#endif /* __FSL_MK64F12_FEATURES_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/Workspace/GPIO/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h b/Workspace/GPIO/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
new file mode 100644
index 0000000..0044bbf
--- /dev/null
+++ b/Workspace/GPIO/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
@@ -0,0 +1,111 @@
+/*
+** ###################################################################
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Register bit field access macros.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+#ifndef _FSL_BITACCESS_H
+#define _FSL_BITACCESS_H  1
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/**
+ * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+#endif /* _FSL_BITACCESS_H */
+
+/******************************************************************************/
diff --git a/Workspace/GPIO/SDK/platform/devices/fsl_device_registers.h b/Workspace/GPIO/SDK/platform/devices/fsl_device_registers.h
new file mode 100644
index 0000000..abeb4ac
--- /dev/null
+++ b/Workspace/GPIO/SDK/platform/devices/fsl_device_registers.h
@@ -0,0 +1,1083 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2014-05-15
+**     Build:               b141209
+**
+**     Abstract:
+**         Common include file for CMSIS register access layer headers.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-05-15)
+**         Customer release.
+**
+** ###################################################################
+*/
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \
+    defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10))
+
+    #define K02F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK02F12810/include/MK02F12810.h"
+    /* Extension register definitions */
+    #include "MK02F12810/include/MK02F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK02F12810/include/MK02F12810_features.h"
+
+#elif (defined(CPU_MK10DN512VLK10) || defined(CPU_MK10DN512VLL10) || defined(CPU_MK10DX128VLQ10) || \
+    defined(CPU_MK10DX256VLQ10) || defined(CPU_MK10DN512VLQ10) || defined(CPU_MK10DN512VMC10) || \
+    defined(CPU_MK10DX128VMD10) || defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10))
+
+    #define K10D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK10D10/include/MK10D10.h"
+    /* Extension register definitions */
+    #include "MK10D10/include/MK10D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK10D10/include/MK10D10_features.h"
+
+#elif (defined(CPU_MK11DX128AVLK5) || defined(CPU_MK11DX256AVLK5) || defined(CPU_MK11DN512AVLK5) || \
+    defined(CPU_MK11DX128AVMC5) || defined(CPU_MK11DX256AVMC5) || defined(CPU_MK11DN512AVMC5))
+
+    #define K11DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK11DA5/include/MK11DA5.h"
+    /* Extension register definitions */
+    #include "MK11DA5/include/MK11DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK11DA5/include/MK11DA5_features.h"
+
+#elif (defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DX256VLK10) || defined(CPU_MK20DN512VLL10) || \
+    defined(CPU_MK20DX256VLL10) || defined(CPU_MK20DX128VLQ10) || defined(CPU_MK20DX256VLQ10) || \
+    defined(CPU_MK20DN512VLQ10) || defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || \
+    defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || defined(CPU_MK20DN512VMD10))
+
+    #define K20D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D10/include/MK20D10.h"
+    /* Extension register definitions */
+    #include "MK20D10/include/MK20D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D10/include/MK20D10_features.h"
+
+#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \
+    defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
+    defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
+    defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
+    defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \
+    defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
+    defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \
+    defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
+    defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
+    defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5))
+
+    #define K20D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D5/include/MK20D5.h"
+    /* Extension register definitions */
+    #include "MK20D5/include/MK20D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D5/include/MK20D5_features.h"
+
+#elif (defined(CPU_MK21DX128AVLK5) || defined(CPU_MK21DX256AVLK5) || defined(CPU_MK21DN512AVLK5) || \
+    defined(CPU_MK21DX128AVMC5) || defined(CPU_MK21DX256AVMC5) || defined(CPU_MK21DN512AVMC5))
+
+    #define K21DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21DA5/include/MK21DA5.h"
+    /* Extension register definitions */
+    #include "MK21DA5/include/MK21DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21DA5/include/MK21DA5_features.h"
+
+#elif (defined(CPU_MK21FX512AVLQ12) || defined(CPU_MK21FN1M0AVLQ12) || defined(CPU_MK21FX512AVMC12) || \
+    defined(CPU_MK21FN1M0AVMC12) || defined(CPU_MK21FX512AVMD12) || defined(CPU_MK21FN1M0AVMD12))
+
+    #define K21FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21FA12/include/MK21FA12.h"
+    /* Extension register definitions */
+    #include "MK21FA12/include/MK21FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21FA12/include/MK21FA12_features.h"
+
+#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \
+    defined(CPU_MK22FN128VMP10))
+
+    #define K22F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F12810/include/MK22F12810.h"
+    /* Extension register definitions */
+    #include "MK22F12810/include/MK22F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F12810/include/MK22F12810_features.h"
+
+#elif (defined(CPU_MK22FX512AVLH12) || defined(CPU_MK22FN1M0AVLH12) || defined(CPU_MK22FX512AVLK12) || \
+    defined(CPU_MK22FN1M0AVLK12) || defined(CPU_MK22FX512AVLL12) || defined(CPU_MK22FN1M0AVLL12) || \
+    defined(CPU_MK22FX512AVLQ12) || defined(CPU_MK22FN1M0AVLQ12) || defined(CPU_MK22FX512AVMC12) || \
+    defined(CPU_MK22FN1M0AVMC12) || defined(CPU_MK22FX512AVMD12) || defined(CPU_MK22FN1M0AVMD12))
+
+    #define K22FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22FA12/include/MK22FA12.h"
+    /* Extension register definitions */
+    #include "MK22FA12/include/MK22FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22FA12/include/MK22FA12_features.h"
+
+#elif (defined(CPU_MK22FN256CAH12) || defined(CPU_MK22FN128CAH12) || defined(CPU_MK22FN256VDC12) || \
+    defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12))
+
+    #define K22F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F25612/include/MK22F25612.h"
+    /* Extension register definitions */
+    #include "MK22F25612/include/MK22F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F25612/include/MK22F25612_features.h"
+
+#elif (defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
+    defined(CPU_MK22FN512VLL12) || defined(CPU_MK22FN512VMP12))
+
+    #define K22F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F51212/include/MK22F51212.h"
+    /* Extension register definitions */
+    #include "MK22F51212/include/MK22F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F51212/include/MK22F51212_features.h"
+
+#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12))
+
+    #define K24F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F12/include/MK24F12.h"
+    /* Extension register definitions */
+    #include "MK24F12/include/MK24F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F12/include/MK24F12_features.h"
+
+#elif (defined(CPU_MK24FN256VDC12))
+
+    #define K24F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F25612/include/MK24F25612.h"
+    /* Extension register definitions */
+    #include "MK24F25612/include/MK24F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F25612/include/MK24F25612_features.h"
+
+#elif (defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VLQ18) || defined(CPU_MK26FN2M0VMD18) || \
+    defined(CPU_MK26FN2M0VMI18))
+
+    #define K26F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK26F18/include/MK26F18.h"
+    /* Extension register definitions */
+    #include "MK26F18/include/MK26F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK26F18/include/MK26F18_features.h"
+
+#elif (defined(CPU_MK30DN512VLK10) || defined(CPU_MK30DN512VLL10) || defined(CPU_MK30DX128VLQ10) || \
+    defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMC10) || \
+    defined(CPU_MK30DX128VMD10) || defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10))
+
+    #define K30D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK30D10/include/MK30D10.h"
+    /* Extension register definitions */
+    #include "MK30D10/include/MK30D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK30D10/include/MK30D10_features.h"
+
+#elif (defined(CPU_MK40DN512VLK10) || defined(CPU_MK40DN512VLL10) || defined(CPU_MK40DX128VLQ10) || \
+    defined(CPU_MK40DX256VLQ10) || defined(CPU_MK40DN512VLQ10) || defined(CPU_MK40DN512VMC10) || \
+    defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || defined(CPU_MK40DN512VMD10))
+
+    #define K40D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK40D10/include/MK40D10.h"
+    /* Extension register definitions */
+    #include "MK40D10/include/MK40D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK40D10/include/MK40D10_features.h"
+
+#elif (defined(CPU_MK50DX256CLL10) || defined(CPU_MK50DN512CLL10) || defined(CPU_MK50DN512CLQ10) || \
+    defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || defined(CPU_MK50DN512CMD10) || \
+    defined(CPU_MK50DX256CMD10) || defined(CPU_MK50DX256CLK10))
+
+    #define K50D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK50D10/include/MK50D10.h"
+    /* Extension register definitions */
+    #include "MK50D10/include/MK50D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK50D10/include/MK50D10_features.h"
+
+#elif (defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10) || defined(CPU_MK51DN256CLQ10) || \
+    defined(CPU_MK51DN512CLQ10) || defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || \
+    defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10) || defined(CPU_MK51DX256CLK10))
+
+    #define K51D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK51D10/include/MK51D10.h"
+    /* Extension register definitions */
+    #include "MK51D10/include/MK51D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK51D10/include/MK51D10_features.h"
+
+#elif (defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10))
+
+    #define K52D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK52D10/include/MK52D10.h"
+    /* Extension register definitions */
+    #include "MK52D10/include/MK52D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK52D10/include/MK52D10_features.h"
+
+#elif (defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || defined(CPU_MK53DN512CMD10) || \
+    defined(CPU_MK53DX256CMD10))
+
+    #define K53D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK53D10/include/MK53D10.h"
+    /* Extension register definitions */
+    #include "MK53D10/include/MK53D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK53D10/include/MK53D10_features.h"
+
+#elif (defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DN512VLL10) || \
+    defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DN512VLQ10) || \
+    defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || defined(CPU_MK60DN512VMC10) || \
+    defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10))
+
+    #define K60D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK60D10/include/MK60D10.h"
+    /* Extension register definitions */
+    #include "MK60D10/include/MK60D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK60D10/include/MK60D10_features.h"
+
+#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12))
+
+    #define K63F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK63F12/include/MK63F12.h"
+    /* Extension register definitions */
+    #include "MK63F12/include/MK63F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK63F12/include/MK63F12_features.h"
+
+#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
+    defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12))
+
+
+    #define K64F12_SERIES
+    /* CMSIS-style register definitions */
+    #include "MK64F12/include/MK64F12.h"
+    /* Extension register definitions */
+    #include "MK64F12/include/MK64F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK64F12/include/MK64F12_features.h"
+
+#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
+    defined(CPU_MK65FX1M0VMI18))
+
+    #define K65F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK65F18/include/MK65F18.h"
+    /* Extension register definitions */
+    #include "MK65F18/include/MK65F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK65F18/include/MK65F18_features.h"
+
+#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
+    defined(CPU_MK66FX1M0VMD18))
+
+    #define K66F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK66F18/include/MK66F18.h"
+    /* Extension register definitions */
+    #include "MK66F18/include/MK66F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK66F18/include/MK66F18_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12))
+
+    #define K70F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F12/include/MK70F12.h"
+    /* Extension register definitions */
+    #include "MK70F12/include/MK70F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F12/include/MK70F12_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+
+    #define K70F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F15/include/MK70F15.h"
+    /* Extension register definitions */
+    #include "MK70F15/include/MK70F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F15/include/MK70F15_features.h"
+
+#elif (defined(CPU_MK80FN256CAx15) || defined(CPU_MK80FN256VDC15) || defined(CPU_MK80FN256VLL15) || \
+    defined(CPU_MK80FN256VLQ15))
+
+    #define K80F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK80F25615/include/MK80F25615.h"
+    /* Extension register definitions */
+    #include "MK80F25615/include/MK80F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK80F25615/include/MK80F25615_features.h"
+
+#elif (defined(CPU_MK81FN256CAx15) || defined(CPU_MK81FN256VDC15) || defined(CPU_MK81FN256VLL15) || \
+    defined(CPU_MK81FN256VLQ15))
+
+    #define K81F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK81F25615/include/MK81F25615.h"
+    /* Extension register definitions */
+    #include "MK81F25615/include/MK81F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK81F25615/include/MK81F25615_features.h"
+
+#elif (defined(CPU_MK82FN256CAx15) || defined(CPU_MK82FN256VDC15) || defined(CPU_MK82FN256VLL15) || \
+    defined(CPU_MK82FN256VLQ15))
+
+    #define K82F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK82F25615/include/MK82F25615.h"
+    /* Extension register definitions */
+    #include "MK82F25615/include/MK82F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK82F25615/include/MK82F25615_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC2) || defined(CPU_MKE02Z32VLC2) || defined(CPU_MKE02Z16VLC2) || \
+    defined(CPU_MKE02Z64VLD2) || defined(CPU_MKE02Z32VLD2) || defined(CPU_MKE02Z16VLD2) || \
+    defined(CPU_MKE02Z64VLH2) || defined(CPU_MKE02Z64VQH2) || defined(CPU_MKE02Z32VLH2) || \
+    defined(CPU_MKE02Z32VQH2))
+
+    #define KE02Z2_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z2/include/MKE02Z2.h"
+    /* Extension register definitions */
+    #include "MKE02Z2/include/MKE02Z2_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z2/include/MKE02Z2_features.h"
+
+#elif (defined(CPU_SKEAZN64MLC2) || defined(CPU_SKEAZN32MLC2) || defined(CPU_SKEAZN16MLC2) || \
+    defined(CPU_SKEAZN64MLD2) || defined(CPU_SKEAZN32MLD2) || defined(CPU_SKEAZN16MLD2) || \
+    defined(CPU_SKEAZN64MLH2) || defined(CPU_SKEAZN32MLH2))
+
+    #define SKEAZN642_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN642/include/SKEAZN642.h"
+    /* Extension register definitions */
+    #include "SKEAZN642/include/SKEAZN642_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN642/include/SKEAZN642_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC4) || defined(CPU_MKE02Z32VLC4) || defined(CPU_MKE02Z16VLC4) || \
+    defined(CPU_MKE02Z64VLD4) || defined(CPU_MKE02Z32VLD4) || defined(CPU_MKE02Z16VLD4) || \
+    defined(CPU_MKE02Z64VLH4) || defined(CPU_MKE02Z64VQH4) || defined(CPU_MKE02Z32VLH4) || \
+    defined(CPU_MKE02Z32VQH4))
+
+    #define KE02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z4/include/MKE02Z4.h"
+    /* Extension register definitions */
+    #include "MKE02Z4/include/MKE02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z4/include/MKE02Z4_features.h"
+
+#elif (defined(CPU_MKE04Z128VLD4) || defined(CPU_MKE04Z64VLD4) || defined(CPU_MKE04Z128VLK4) || \
+    defined(CPU_MKE04Z64VLK4) || defined(CPU_MKE04Z128VQH4) || defined(CPU_MKE04Z64VQH4) || \
+    defined(CPU_MKE04Z128VLH4) || defined(CPU_MKE04Z64VLH4))
+
+    #define KE04Z1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284.h"
+    /* Extension register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_features.h"
+
+#elif (defined(CPU_MKE04Z8VFK4) || defined(CPU_MKE04Z8VTG4) || defined(CPU_MKE04Z8VWJ4))
+
+    #define KE04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z4/include/MKE04Z4.h"
+    /* Extension register definitions */
+    #include "MKE04Z4/include/MKE04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z4/include/MKE04Z4_features.h"
+
+#elif (defined(CPU_SKEAZN8MFK) || defined(CPU_SKEAZN8MTG))
+
+    #define SKEAZN84_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN84/include/SKEAZN84.h"
+    /* Extension register definitions */
+    #include "SKEAZN84/include/SKEAZN84_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN84/include/SKEAZN84_features.h"
+
+#elif (defined(CPU_MKE06Z128VLD4) || defined(CPU_MKE06Z64VLD4) || defined(CPU_MKE06Z128VLK4) || \
+    defined(CPU_MKE06Z64VLK4) || defined(CPU_MKE06Z128VQH4) || defined(CPU_MKE06Z64VQH4) || \
+    defined(CPU_MKE06Z128VLH4) || defined(CPU_MKE06Z64VLH4))
+
+    #define KE06Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE06Z4/include/MKE06Z4.h"
+    /* Extension register definitions */
+    #include "MKE06Z4/include/MKE06Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE06Z4/include/MKE06Z4_features.h"
+
+#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
+    defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \
+    defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4))
+
+    #define KL02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL02Z4/include/MKL02Z4.h"
+    /* Extension register definitions */
+    #include "MKL02Z4/include/MKL02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL02Z4/include/MKL02Z4_features.h"
+
+#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \
+    defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \
+    defined(CPU_MKL03Z32VFK4))
+
+    #define KL03Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL03Z4/include/MKL03Z4.h"
+    /* Extension register definitions */
+    #include "MKL03Z4/include/MKL03Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL03Z4/include/MKL03Z4_features.h"
+
+#elif (defined(CPU_MKL04Z8VFK4) || defined(CPU_MKL04Z16VFK4) || defined(CPU_MKL04Z32VFK4) || \
+    defined(CPU_MKL04Z8VLC4) || defined(CPU_MKL04Z16VLC4) || defined(CPU_MKL04Z32VLC4) || \
+    defined(CPU_MKL04Z8VFM4) || defined(CPU_MKL04Z16VFM4) || defined(CPU_MKL04Z32VFM4) || \
+    defined(CPU_MKL04Z16VLF4) || defined(CPU_MKL04Z32VLF4))
+
+    #define KL04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL04Z4/include/MKL04Z4.h"
+    /* Extension register definitions */
+    #include "MKL04Z4/include/MKL04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL04Z4/include/MKL04Z4_features.h"
+
+#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \
+    defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
+    defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
+    defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4))
+
+    #define KL05Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL05Z4/include/MKL05Z4.h"
+    /* Extension register definitions */
+    #include "MKL05Z4/include/MKL05Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL05Z4/include/MKL05Z4_features.h"
+
+#elif (defined(CPU_MKL13Z32VFM4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z32VFT4) || \
+    defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z32VLH4) || defined(CPU_MKL13Z64VLH4) || \
+    defined(CPU_MKL13Z32VLK4) || defined(CPU_MKL13Z64VLK4) || defined(CPU_MKL13Z32VMP4) || \
+    defined(CPU_MKL13Z64VMP4))
+
+    #define KL13Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL13Z644/include/MKL13Z644.h"
+    /* Extension register definitions */
+    #include "MKL13Z644/include/MKL13Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL13Z644/include/MKL13Z644_features.h"
+
+#elif (defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || defined(CPU_MKL14Z32VFT4) || \
+    defined(CPU_MKL14Z64VFT4) || defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || \
+    defined(CPU_MKL14Z32VLK4) || defined(CPU_MKL14Z64VLK4))
+
+    #define KL14Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL14Z4/include/MKL14Z4.h"
+    /* Extension register definitions */
+    #include "MKL14Z4/include/MKL14Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL14Z4/include/MKL14Z4_features.h"
+
+#elif (defined(CPU_MKL15Z128CAD4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || \
+    defined(CPU_MKL15Z128VFM4) || defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || \
+    defined(CPU_MKL15Z128VFT4) || defined(CPU_MKL15Z32VLH4) || defined(CPU_MKL15Z64VLH4) || \
+    defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || defined(CPU_MKL15Z64VLK4) || \
+    defined(CPU_MKL15Z128VLK4))
+
+    #define KL15Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL15Z4/include/MKL15Z4.h"
+    /* Extension register definitions */
+    #include "MKL15Z4/include/MKL15Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL15Z4/include/MKL15Z4_features.h"
+
+#elif (defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || \
+    defined(CPU_MKL16Z32VFT4) || defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || \
+    defined(CPU_MKL16Z32VLH4) || defined(CPU_MKL16Z64VLH4) || defined(CPU_MKL16Z128VLH4) || \
+    defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VMP4))
+
+    #define KL16Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL16Z4/include/MKL16Z4.h"
+    /* Extension register definitions */
+    #include "MKL16Z4/include/MKL16Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL16Z4/include/MKL16Z4_features.h"
+
+#elif (defined(CPU_MKL17Z128VFM4) || defined(CPU_MKL17Z256VFM4) || defined(CPU_MKL17Z128VFT4) || \
+    defined(CPU_MKL17Z256VFT4) || defined(CPU_MKL17Z128VLH4) || defined(CPU_MKL17Z256VLH4) || \
+    defined(CPU_MKL17Z128VMP4) || defined(CPU_MKL17Z256VMP4))
+
+    #define KL17Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z4/include/MKL17Z4.h"
+    /* Extension register definitions */
+    #include "MKL17Z4/include/MKL17Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z4/include/MKL17Z4_features.h"
+
+#elif (defined(CPU_MKL17Z32VDA4) || defined(CPU_MKL17Z64VDA4) || defined(CPU_MKL17Z32VFM4) || \
+    defined(CPU_MKL17Z64VFM4) || defined(CPU_MKL17Z32VFT4) || defined(CPU_MKL17Z64VFT4) || \
+    defined(CPU_MKL17Z32VLH4) || defined(CPU_MKL17Z64VLH4) || defined(CPU_MKL17Z32VMP4) || \
+    defined(CPU_MKL17Z64VMP4))
+
+    #define KL17Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z644/include/MKL17Z644.h"
+    /* Extension register definitions */
+    #include "MKL17Z644/include/MKL17Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z644/include/MKL17Z644_features.h"
+
+#elif (defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || defined(CPU_MKL24Z32VFT4) || \
+    defined(CPU_MKL24Z64VFT4) || defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || \
+    defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4))
+
+    #define KL24Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL24Z4/include/MKL24Z4.h"
+    /* Extension register definitions */
+    #include "MKL24Z4/include/MKL24Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL24Z4/include/MKL24Z4_features.h"
+
+#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
+    defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
+    defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
+    defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
+
+    #define KL25Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL25Z4/include/MKL25Z4.h"
+    /* Extension register definitions */
+    #include "MKL25Z4/include/MKL25Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL25Z4/include/MKL25Z4_features.h"
+
+
+#elif (defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || \
+    defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || \
+    defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || \
+    defined(CPU_MKL26Z128VLH4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z128VLL4) || \
+    defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
+    defined(CPU_MKL26Z256VMP4))
+
+    #define KL26Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL26Z4/include/MKL26Z4.h"
+    /* Extension register definitions */
+    #include "MKL26Z4/include/MKL26Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL26Z4/include/MKL26Z4_features.h"
+
+#elif (defined(CPU_MKL27Z128VFM4) || defined(CPU_MKL27Z256VFM4) || defined(CPU_MKL27Z128VFT4) || \
+    defined(CPU_MKL27Z256VFT4) || defined(CPU_MKL27Z128VLH4) || defined(CPU_MKL27Z256VLH4) || \
+    defined(CPU_MKL27Z128VMP4) || defined(CPU_MKL27Z256VMP4))
+
+    #define KL27Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z4/include/MKL27Z4.h"
+    /* Extension register definitions */
+    #include "MKL27Z4/include/MKL27Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z4/include/MKL27Z4_features.h"
+
+#elif (defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z64VDA4) || defined(CPU_MKL27Z32VFM4) || \
+    defined(CPU_MKL27Z64VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z64VFT4) || \
+    defined(CPU_MKL27Z32VLH4) || defined(CPU_MKL27Z64VLH4) || defined(CPU_MKL27Z32VMP4) || \
+    defined(CPU_MKL27Z64VMP4))
+
+    #define KL27Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z644/include/MKL27Z644.h"
+    /* Extension register definitions */
+    #include "MKL27Z644/include/MKL27Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z644/include/MKL27Z644_features.h"
+
+#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \
+    defined(CPU_MKL33Z256VMP4))
+
+    #define KL33Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z4/include/MKL33Z4.h"
+    /* Extension register definitions */
+    #include "MKL33Z4/include/MKL33Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z4/include/MKL33Z4_features.h"
+
+#elif (defined(CPU_MKL33Z32VFT4) || defined(CPU_MKL33Z64VFT4) || defined(CPU_MKL33Z32VLH4) || \
+    defined(CPU_MKL33Z64VLH4) || defined(CPU_MKL33Z32VLK4) || defined(CPU_MKL33Z64VLK4) || \
+    defined(CPU_MKL33Z32VMP4) || defined(CPU_MKL33Z64VMP4))
+
+    #define KL33Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z644/include/MKL33Z644.h"
+    /* Extension register definitions */
+    #include "MKL33Z644/include/MKL33Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z644/include/MKL33Z644_features.h"
+
+#elif (defined(CPU_MKL34Z64VLH4) || defined(CPU_MKL34Z64VLL4))
+
+    #define KL34Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL34Z4/include/MKL34Z4.h"
+    /* Extension register definitions */
+    #include "MKL34Z4/include/MKL34Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL34Z4/include/MKL34Z4_features.h"
+
+#elif (defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || \
+    defined(CPU_MKL36Z64VLL4) || defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || \
+    defined(CPU_MKL36Z128VMC4) || defined(CPU_MKL36Z256VMC4) || defined(CPU_MKL36Z256VMP4))
+
+    #define KL36Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL36Z4/include/MKL36Z4.h"
+    /* Extension register definitions */
+    #include "MKL36Z4/include/MKL36Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL36Z4/include/MKL36Z4_features.h"
+
+#elif (defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z128VMP4) || \
+    defined(CPU_MKL43Z256VMP4))
+
+    #define KL43Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL43Z4/include/MKL43Z4.h"
+    /* Extension register definitions */
+    #include "MKL43Z4/include/MKL43Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL43Z4/include/MKL43Z4_features.h"
+
+#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
+    defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \
+    defined(CPU_MKL46Z256VMP4))
+
+    #define KL46Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL46Z4/include/MKL46Z4.h"
+    /* Extension register definitions */
+    #include "MKL46Z4/include/MKL46Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL46Z4/include/MKL46Z4_features.h"
+
+#elif (defined(CPU_MKM14Z128AHH5) || defined(CPU_MKM14Z64AHH5))
+
+    #define KM14ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5.h"
+    /* Extension register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_features.h"
+
+#elif (defined(CPU_MKM33Z128ALH5) || defined(CPU_MKM33Z64ALH5) || defined(CPU_MKM33Z128ALL5) || \
+    defined(CPU_MKM33Z64ALL5))
+
+    #define KM33ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5.h"
+    /* Extension register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z128ALL5))
+
+    #define KM34ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5.h"
+    /* Extension register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z256VLL7) || defined(CPU_MKM34Z256VLQ7))
+
+    #define KM34Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34Z7/include/MKM34Z7.h"
+    /* Extension register definitions */
+    #include "MKM34Z7/include/MKM34Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34Z7/include/MKM34Z7_features.h"
+
+#elif (defined(CPU_MKV10Z16VFM7) || defined(CPU_MKV10Z16VLC7) || defined(CPU_MKV10Z16VLF7) || \
+    defined(CPU_MKV10Z32VFM7) || defined(CPU_MKV10Z32VLC7) || defined(CPU_MKV10Z32VLF7))
+
+    #define KV10Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z7/include/MKV10Z7.h"
+    /* Extension register definitions */
+    #include "MKV10Z7/include/MKV10Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z7/include/MKV10Z7_features.h"
+
+#elif (defined(CPU_MKV10Z128VFM7) || defined(CPU_MKV10Z128VLC7) || defined(CPU_MKV10Z128VLF7) || \
+    defined(CPU_MKV10Z128VLH7) || defined(CPU_MKV10Z64VFM7) || defined(CPU_MKV10Z64VLC7) || \
+    defined(CPU_MKV10Z64VLF7) || defined(CPU_MKV10Z64VLH7))
+
+    #define KV10Z1287_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z1287/include/MKV10Z1287.h"
+    /* Extension register definitions */
+    #include "MKV10Z1287/include/MKV10Z1287_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z1287/include/MKV10Z1287_features.h"
+
+#elif (defined(CPU_MKV11Z128VFM7) || defined(CPU_MKV11Z128VLC7) || defined(CPU_MKV11Z128VLF7) || \
+    defined(CPU_MKV11Z128VLH7) || defined(CPU_MKV11Z64VFM7) || defined(CPU_MKV11Z64VLC7) || \
+    defined(CPU_MKV11Z64VLF7) || defined(CPU_MKV11Z64VLH7))
+
+    #define KV11Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV11Z7/include/MKV11Z7.h"
+    /* Extension register definitions */
+    #include "MKV11Z7/include/MKV11Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV11Z7/include/MKV11Z7_features.h"
+
+#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
+    defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10))
+
+    #define KV30F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV30F12810/include/MKV30F12810.h"
+    /* Extension register definitions */
+    #include "MKV30F12810/include/MKV30F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV30F12810/include/MKV30F12810_features.h"
+
+#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10))
+
+    #define KV31F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F12810/include/MKV31F12810.h"
+    /* Extension register definitions */
+    #include "MKV31F12810/include/MKV31F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F12810/include/MKV31F12810_features.h"
+
+#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12))
+
+    #define KV31F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F25612/include/MKV31F25612.h"
+    /* Extension register definitions */
+    #include "MKV31F25612/include/MKV31F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F25612/include/MKV31F25612_features.h"
+
+#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12))
+
+    #define KV31F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F51212/include/MKV31F51212.h"
+    /* Extension register definitions */
+    #include "MKV31F51212/include/MKV31F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F51212/include/MKV31F51212_features.h"
+
+#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
+    defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15))
+
+    #define KV40F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV40F15/include/MKV40F15.h"
+    /* Extension register definitions */
+    #include "MKV40F15/include/MKV40F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV40F15/include/MKV40F15_features.h"
+
+#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15))
+
+    #define KV43F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV43F15/include/MKV43F15.h"
+    /* Extension register definitions */
+    #include "MKV43F15/include/MKV43F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV43F15/include/MKV43F15_features.h"
+
+#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15))
+
+    #define KV44F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV44F15/include/MKV44F15.h"
+    /* Extension register definitions */
+    #include "MKV44F15/include/MKV44F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV44F15/include/MKV44F15_features.h"
+
+#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \
+    defined(CPU_MKV45F256VLL15))
+
+    #define KV45F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV45F15/include/MKV45F15.h"
+    /* Extension register definitions */
+    #include "MKV45F15/include/MKV45F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV45F15/include/MKV45F15_features.h"
+
+#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \
+    defined(CPU_MKV46F256VLL15))
+
+    #define KV46F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV46F15/include/MKV46F15.h"
+    /* Extension register definitions */
+    #include "MKV46F15/include/MKV46F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV46F15/include/MKV46F15_features.h"
+
+#elif (defined(CPU_MKW01Z128CHN4))
+
+    #define KW01Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW01Z4/include/MKW01Z4.h"
+    /* Extension register definitions */
+    #include "MKW01Z4/include/MKW01Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW01Z4/include/MKW01Z4_features.h"
+
+#elif (defined(CPU_MKW20Z160VHT4))
+
+    #define KW20Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW20Z4/include/MKW20Z4.h"
+    /* Extension register definitions */
+    #include "MKW20Z4/include/MKW20Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW20Z4/include/MKW20Z4_features.h"
+
+#elif (defined(CPU_MKW21D256VHA5) || defined(CPU_MKW21D512VHA5))
+
+    #define KW21D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW21D5/include/MKW21D5.h"
+    /* Extension register definitions */
+    #include "MKW21D5/include/MKW21D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW21D5/include/MKW21D5_features.h"
+
+#elif (defined(CPU_MKW22D512VHA5))
+
+    #define KW22D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW22D5/include/MKW22D5.h"
+    /* Extension register definitions */
+    #include "MKW22D5/include/MKW22D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW22D5/include/MKW22D5_features.h"
+
+#elif (defined(CPU_MKW24D512VHA5))
+
+    #define KW24D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW24D5/include/MKW24D5.h"
+    /* Extension register definitions */
+    #include "MKW24D5/include/MKW24D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW24D5/include/MKW24D5_features.h"
+
+#elif (defined(CPU_MKW30Z160VHM4))
+
+    #define KW30Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW30Z4/include/MKW30Z4.h"
+    /* Extension register definitions */
+    #include "MKW30Z4/include/MKW30Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW30Z4/include/MKW30Z4_features.h"
+
+#elif (defined(CPU_MKW40Z160VHT4))
+
+    #define KW40Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW40Z4/include/MKW40Z4.h"
+    /* Extension register definitions */
+    #include "MKW40Z4/include/MKW40Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW40Z4/include/MKW40Z4_features.h"
+
+#elif (defined(CPU_SKEAZ128MLH) || defined(CPU_SKEAZ64MLH) || defined(CPU_SKEAZ128MLK) || \
+    defined(CPU_SKEAZ64MLK))
+
+    #define SKEAZ1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284.h"
+    /* Extension register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/Workspace/GPIO/Sources/main.c b/Workspace/GPIO/Sources/main.c
new file mode 100644
index 0000000..2f74731
--- /dev/null
+++ b/Workspace/GPIO/Sources/main.c
@@ -0,0 +1,70 @@
+#include "MK64F12.h"
+
+int main(void)
+{
+
+	SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; /*Enable Port B Clock Gate Control*/
+	SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;/*Enable Port E Clock Gate Control*/
+	SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;/*Enable Port C Clock Gate Control*/
+	SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /*Enable Port A Clock Gate Control*/
+	PORTB_PCR21 = 0x100; /*Blue Led, configured as Alternative 1 (GPIO)*/
+	PORTB_PCR22 = 0x100;/*Red Led, configured as Alternative 1 (GPIO)*/
+	PORTE_PCR26 = 0x100;/*Green Led, configured as Alternative 1 (GPIO)*/
+	PORTC_PCR6 = 0X100;/*Switch 2, configured as Alternative 1 (GPIO)*/
+	PORTA_PCR4 = 0x100;/*Changing the NMI to GPIO*/
+	GPIOB_PDDR |= (1 << 21);/*Setting the bit 21 of the port B as Output*/
+	GPIOB_PDDR |= (1 << 22);/*Setting the bit 22 of the port B as Output*/
+	GPIOE_PDDR |= (1 << 26);/*Setting the bit 26 of the port E as Output*/
+	GPIOC_PDDR |= (0 << 6);/*Setting the bit 6 of the port C as Input*/
+	/*Turn off RGB Leds*/
+	GPIOB_PDOR |= (1 << 22);/*Turn Off Red Led*/
+	GPIOB_PDOR |= (1 << 21);/*Turn Off Blue Led*/
+	GPIOE_PDOR |= (1 << 26);/*Turn Off Green Led*/
+
+	unsigned long Counter = 0x100000;/*Delay Value*/
+
+	for(;;)
+	{
+		if(GPIOC_PDIR == 0)/*If the Switch 2 was press*/
+		{
+			GPIOB_PDOR = (1 << 21);/*Turn On Red Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOB_PDOR = (1 << 22) | ( 1 << 21); /*Turn Off Red Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOE_PDOR = (0 << 26);/*Turn On Green Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOE_PDOR = (1 << 26); /*Turn Off Green Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOB_PDOR = (1 << 22);/*Turn On Blue Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+			GPIOB_PDOR = (1 << 21) | (1 << 22); /*Turn Off Blue Led*/
+			while(Counter != 0)/*Wait Delay Value*/
+			{
+				Counter--;
+			}
+			Counter = 0x100000;/*Recharger the Delay*/
+		}
+	}
+	return 0;
+}
+
diff --git a/Workspace/Interrupt/.cproject b/Workspace/Interrupt/.cproject
new file mode 100644
index 0000000..6b51f26
--- /dev/null
+++ b/Workspace/Interrupt/.cproject
@@ -0,0 +1,128 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<macros>
+					<stringMacro name="PROJECT_KSDK_PATH" type="VALUE_TEXT" value="C:\Freescale\KSDK_1.3.0"/>
+				</macros>
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="GPIO" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.138424891" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
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+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.446926023" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
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+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.1774832244" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1114519651" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.584099008" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder buildPath="${workspace_loc:/GPIO}/Debug" id="ilg.gnuarmeclipse.managedbuild.cross.builder.2018125917" name="Gnu Make Builder.Debug" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
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+									<listOptionValue builtIn="false" value="&quot;../Sources&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../Project_Settings/Startup_Code&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/CMSIS/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices/MK64F12/include&quot;"/>
+								</option>
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+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.2026894627" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="-specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs" valueType="string"/>
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+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
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+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="GPIO.ilg.gnuarmeclipse.managedbuild.cross.target.elf.1672910064" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
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+	<storageModule moduleId="scannerConfiguration">
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+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/Workspace/Interrupt/.cwGeneratedFileSetLog b/Workspace/Interrupt/.cwGeneratedFileSetLog
new file mode 100644
index 0000000..da94cd8
--- /dev/null
+++ b/Workspace/Interrupt/.cwGeneratedFileSetLog
@@ -0,0 +1,19 @@
+Sources/main.c
+Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
+SDK/platform/devices/MK64F12/include/MK64F12_extension.h
+SDK/platform/CMSIS/Include/arm_math.h
+SDK/platform/CMSIS/Include/core_cmSimd.h
+SDK/platform/devices/MK64F12/include/MK64F12.h
+SDK/platform/CMSIS/Include/core_cm4.h
+SDK/platform/CMSIS/Include/arm_common_tables.h
+SDK/platform/devices/MK64F12/include/MK64F12_features.h
+SDK/platform/devices/fsl_device_registers.h
+SDK/platform/CMSIS/Include/arm_const_structs.h
+SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
+SDK/platform/CMSIS/Include/core_cmFunc.h
+SDK/platform/CMSIS/Include/core_cmInstr.h
+Project_Settings/Startup_Code/system_MK64F12.h
+Project_Settings/Startup_Code/startup.c
+Project_Settings/Startup_Code/startup_MK64F12.S
+Project_Settings/Startup_Code/startup.h
+Project_Settings/Startup_Code/system_MK64F12.c
\ No newline at end of file
diff --git a/Workspace/Interrupt/.project b/Workspace/Interrupt/.project
new file mode 100644
index 0000000..7f0cf1b
--- /dev/null
+++ b/Workspace/Interrupt/.project
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>Interrupt</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<variableList>
+		<variable>
+			<name>PROJECT_KSDK_PATH</name>
+			<value>file:/C:/Freescale/KSDK_1.3.0</value>
+		</variable>
+	</variableList>
+</projectDescription>
diff --git a/Workspace/Interrupt/.settings/com.freescale.processorexpert.derivative.prefs b/Workspace/Interrupt/.settings/com.freescale.processorexpert.derivative.prefs
new file mode 100644
index 0000000..60d5016
--- /dev/null
+++ b/Workspace/Interrupt/.settings/com.freescale.processorexpert.derivative.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+versionGenerated/versionGenerated=1.0.0.RT7_b1550-0615
diff --git a/Workspace/Interrupt/.settings/com.processorexpert.sdk.legacy.legacyprojectupdater.prefs b/Workspace/Interrupt/.settings/com.processorexpert.sdk.legacy.legacyprojectupdater.prefs
new file mode 100644
index 0000000..7733bda
--- /dev/null
+++ b/Workspace/Interrupt/.settings/com.processorexpert.sdk.legacy.legacyprojectupdater.prefs
@@ -0,0 +1 @@
+skip=true
\ No newline at end of file
diff --git a/Workspace/Interrupt/.settings/language.settings.xml b/Workspace/Interrupt/.settings/language.settings.xml
new file mode 100644
index 0000000..63c81d5
--- /dev/null
+++ b/Workspace/Interrupt/.settings/language.settings.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="355957199812988073" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings Cross ARM" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/Workspace/Interrupt/Debug/GPIO.elf b/Workspace/Interrupt/Debug/GPIO.elf
new file mode 100644
index 0000000..e6e8593
Binary files /dev/null and b/Workspace/Interrupt/Debug/GPIO.elf differ
diff --git a/Workspace/Interrupt/Debug/GPIO.map b/Workspace/Interrupt/Debug/GPIO.map
new file mode 100644
index 0000000..c9ee082
--- /dev/null
+++ b/Workspace/Interrupt/Debug/GPIO.map
@@ -0,0 +1,617 @@
+Archive member included because of file (symbol)
+
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (exit)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_global_impure_ptr)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (__libc_init_array)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (memset)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_exit)
+
+Discarded input sections
+
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .data          0x00000000        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.extab     0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .text          0x00000000        0x0 ./Sources/main.o
+ .data          0x00000000        0x0 ./Sources/main.o
+ .bss           0x00000000        0x0 ./Sources/main.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
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+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
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+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
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+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
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+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .text          0x00000000        0x0 ./Project_Settings/Startup_Code/startup.o
+ .data          0x00000000        0x0 ./Project_Settings/Startup_Code/startup.o
+ .bss           0x00000000        0x0 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00000000      0x856 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00000000       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00000000       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00000000       0x44 ./Project_Settings/Startup_Code/startup.o
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+ .debug_macro   0x00000000       0x3b ./Project_Settings/Startup_Code/startup.o
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+ .debug_macro   0x00000000      0xd1d ./Project_Settings/Startup_Code/startup.o
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+ .debug_macro   0x00000000    0x1773b ./Project_Settings/Startup_Code/startup.o
+ .data          0x00000000        0x0 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .bss           0x00000000        0x0 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/system_MK64F12.o
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+ .text          0x00000000        0x0 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .data          0x00000000        0x0 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .bss           0x00000000        0x0 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .data.SystemCoreClock
+                0x00000000        0x4 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .text.SystemCoreClockUpdate
+                0x00000000      0x270 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000      0x856 ./Project_Settings/Startup_Code/system_MK64F12.o
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+ .debug_macro   0x00000000       0x11 ./Project_Settings/Startup_Code/system_MK64F12.o
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+ .debug_macro   0x00000000       0x7f ./Project_Settings/Startup_Code/system_MK64F12.o
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+ .debug_macro   0x00000000    0x16273 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00000000     0x1182 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data._impure_ptr
+                0x00000000        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .eh_frame      0x00000000        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+m_interrupts     0x00000000         0x00000400         xr
+m_flash_config   0x00000400         0x00000010         xr
+m_text           0x00000410         0x000ffbf0         xr
+m_data           0x1fff0000         0x00010000         rw
+m_data_2         0x20000000         0x00030000         rw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+LOAD ./Sources/main.o
+LOAD ./Project_Settings/Startup_Code/startup.o
+LOAD ./Project_Settings/Startup_Code/startup_MK64F12.o
+LOAD ./Project_Settings/Startup_Code/system_MK64F12.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libstdc++_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libm.a
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000400                HEAP_SIZE = DEFINED (__heap_size__)?__heap_size__:0x400
+                0x00000400                STACK_SIZE = DEFINED (__stack_size__)?__stack_size__:0x400
+                0x00000000                M_VECTOR_RAM_SIZE = DEFINED (__ram_vector_table__)?0x400:0x0
+
+.interrupts     0x00000000      0x400
+                0x00000000                __VECTOR_TABLE = .
+                0x00000000                . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector    0x00000000      0x400 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000000                __isr_vector
+                0x00000400                . = ALIGN (0x4)
+
+.flash_config   0x00000400       0x10
+                0x00000400                . = ALIGN (0x4)
+ *(.FlashConfig)
+ .FlashConfig   0x00000400       0x10 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000410                . = ALIGN (0x4)
+
+.text           0x00000410      0x40c
+                0x00000410                . = ALIGN (0x4)
+ *(.text)
+ .text          0x00000410       0x54 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .text          0x00000464       0x74 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00000464                _start
+                0x00000464                _mainCRTStartup
+ .text          0x000004d8       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x000004d8                Reset_Handler
+                0x000004e8                DebugMon_Handler
+                0x000004e8                I2C0_IRQHandler
+                0x000004e8                HardFault_Handler
+                0x000004e8                SysTick_Handler
+                0x000004e8                UART3_RX_TX_IRQHandler
+                0x000004e8                PendSV_Handler
+                0x000004e8                NMI_Handler
+                0x000004e8                UART0_RX_TX_IRQHandler
+                0x000004e8                I2C1_IRQHandler
+                0x000004e8                DMA2_IRQHandler
+                0x000004e8                ENET_Error_IRQHandler
+                0x000004e8                CAN0_Tx_Warning_IRQHandler
+                0x000004e8                PIT0_IRQHandler
+                0x000004e8                CAN0_ORed_Message_buffer_IRQHandler
+                0x000004e8                CMP2_IRQHandler
+                0x000004e8                LLWU_IRQHandler
+                0x000004e8                ENET_Receive_IRQHandler
+                0x000004e8                ENET_1588_Timer_IRQHandler
+                0x000004e8                UART2_RX_TX_IRQHandler
+                0x000004e8                SWI_IRQHandler
+                0x000004e8                ADC0_IRQHandler
+                0x000004e8                UsageFault_Handler
+                0x000004e8                I2S0_Tx_IRQHandler
+                0x000004e8                CMT_IRQHandler
+                0x000004e8                UART4_RX_TX_IRQHandler
+                0x000004e8                SPI1_IRQHandler
+                0x000004e8                DefaultISR
+                0x000004e8                DMA9_IRQHandler
+                0x000004e8                DMA14_IRQHandler
+                0x000004e8                CMP1_IRQHandler
+                0x000004e8                Reserved71_IRQHandler
+                0x000004e8                PORTD_IRQHandler
+                0x000004e8                PORTB_IRQHandler
+                0x000004e8                UART4_ERR_IRQHandler
+                0x000004e8                ADC1_IRQHandler
+                0x000004e8                I2C2_IRQHandler
+                0x000004e8                PIT2_IRQHandler
+                0x000004e8                I2S0_Rx_IRQHandler
+                0x000004e8                DMA5_IRQHandler
+                0x000004e8                RTC_IRQHandler
+                0x000004e8                PDB0_IRQHandler
+                0x000004e8                CAN0_Rx_Warning_IRQHandler
+                0x000004e8                FTM1_IRQHandler
+                0x000004e8                UART5_RX_TX_IRQHandler
+                0x000004e8                UART3_ERR_IRQHandler
+                0x000004e8                PIT3_IRQHandler
+                0x000004e8                SDHC_IRQHandler
+                0x000004e8                RTC_Seconds_IRQHandler
+                0x000004e8                MCG_IRQHandler
+                0x000004e8                FTFE_IRQHandler
+                0x000004e8                UART2_ERR_IRQHandler
+                0x000004e8                DMA11_IRQHandler
+                0x000004e8                UART5_ERR_IRQHandler
+                0x000004e8                Read_Collision_IRQHandler
+                0x000004e8                DMA7_IRQHandler
+                0x000004e8                ENET_Transmit_IRQHandler
+                0x000004e8                USBDCD_IRQHandler
+                0x000004e8                USB0_IRQHandler
+                0x000004e8                SPI2_IRQHandler
+                0x000004e8                WDOG_EWM_IRQHandler
+                0x000004e8                MemManage_Handler
+                0x000004e8                SVC_Handler
+                0x000004e8                DMA13_IRQHandler
+                0x000004e8                DMA3_IRQHandler
+                0x000004e8                UART0_LON_IRQHandler
+                0x000004e8                RNG_IRQHandler
+                0x000004e8                DMA0_IRQHandler
+                0x000004e8                DMA15_IRQHandler
+                0x000004e8                DAC0_IRQHandler
+                0x000004e8                CAN0_Error_IRQHandler
+                0x000004e8                DMA4_IRQHandler
+                0x000004e8                PIT1_IRQHandler
+                0x000004e8                UART0_ERR_IRQHandler
+                0x000004e8                DMA_Error_IRQHandler
+                0x000004e8                LVD_LVW_IRQHandler
+                0x000004e8                SPI0_IRQHandler
+                0x000004e8                FTM0_IRQHandler
+                0x000004e8                PORTA_IRQHandler
+                0x000004e8                DAC1_IRQHandler
+                0x000004e8                MCM_IRQHandler
+                0x000004e8                DMA12_IRQHandler
+                0x000004e8                CAN0_Bus_Off_IRQHandler
+                0x000004e8                FTM3_IRQHandler
+                0x000004e8                PORTE_IRQHandler
+                0x000004e8                FTM2_IRQHandler
+                0x000004e8                LPTMR0_IRQHandler
+                0x000004e8                BusFault_Handler
+                0x000004e8                DMA8_IRQHandler
+                0x000004e8                DMA10_IRQHandler
+                0x000004e8                CAN0_Wake_Up_IRQHandler
+                0x000004e8                UART1_ERR_IRQHandler
+                0x000004e8                UART1_RX_TX_IRQHandler
+                0x000004e8                CMP0_IRQHandler
+                0x000004e8                DMA6_IRQHandler
+                0x000004e8                DMA1_IRQHandler
+ *(.text*)
+ .text.NVIC_EnableIRQ
+                0x000004ec       0x30 ./Sources/main.o
+ .text.main     0x0000051c       0xe0 ./Sources/main.o
+                0x0000051c                main
+ .text.PORTC_IRQHandler
+                0x000005fc       0x48 ./Sources/main.o
+                0x000005fc                PORTC_IRQHandler
+ .text.DelayFunction
+                0x00000644       0x28 ./Sources/main.o
+                0x00000644                DelayFunction
+ .text.init_data_bss
+                0x0000066c       0xcc ./Project_Settings/Startup_Code/startup.o
+                0x0000066c                init_data_bss
+ .text.SystemInit
+                0x00000738       0x3c ./Project_Settings/Startup_Code/system_MK64F12.o
+                0x00000738                SystemInit
+ .text.exit     0x00000774       0x28 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+                0x00000774                exit
+ .text.__libc_init_array
+                0x0000079c       0x4c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                0x0000079c                __libc_init_array
+ .text.memset   0x000007e8       0x10 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                0x000007e8                memset
+ .text._exit    0x000007f8        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                0x000007f8                _exit
+ *(.rodata)
+ *(.rodata*)
+ .rodata.str1.1
+                0x000007fc        0x2 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *fill*         0x000007fe        0x2 
+ .rodata._global_impure_ptr
+                0x00000800        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                0x00000800                _global_impure_ptr
+ *(.glue_7)
+ .glue_7        0x00000000        0x0 linker stubs
+ *(.glue_7t)
+ .glue_7t       0x00000000        0x0 linker stubs
+ *(.eh_frame)
+ .eh_frame      0x00000804        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.init)
+ .init          0x00000804        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x00000804                _init
+ .init          0x00000808        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ *(.fini)
+ .fini          0x00000810        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x00000810                _fini
+ .fini          0x00000814        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x0000081c                . = ALIGN (0x4)
+
+.vfp11_veneer   0x0000081c        0x0
+ .vfp11_veneer  0x00000000        0x0 linker stubs
+
+.v4_bx          0x0000081c        0x0
+ .v4_bx         0x00000000        0x0 linker stubs
+
+.iplt           0x0000081c        0x0
+ .iplt          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM            0x0000081c        0x8
+                0x0000081c                __exidx_start = .
+ *(.ARM.exidx*)
+ .ARM.exidx     0x0000081c        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00000824                __exidx_end = .
+
+.rel.dyn        0x00000824        0x0
+ .rel.iplt      0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ctors          0x00000824        0x0
+                0x00000824                __CTOR_LIST__ = .
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+                0x00000824                __CTOR_END__ = .
+
+.dtors          0x00000824        0x0
+                0x00000824                __DTOR_LIST__ = .
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+                0x00000824                __DTOR_END__ = .
+
+.preinit_array  0x00000824        0x0
+                0x00000824                PROVIDE (__preinit_array_start, .)
+ *(.preinit_array*)
+                0x00000824                PROVIDE (__preinit_array_end, .)
+
+.init_array     0x00000824        0x4
+                0x00000824                PROVIDE (__init_array_start, .)
+ *(SORT(.init_array.*))
+ *(.init_array*)
+ .init_array    0x00000824        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x00000828                PROVIDE (__init_array_end, .)
+
+.fini_array     0x00000828        0x4
+                0x00000828                PROVIDE (__fini_array_start, .)
+ *(SORT(.fini_array.*))
+ *(.fini_array*)
+ .fini_array    0x00000828        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x0000082c                PROVIDE (__fini_array_end, .)
+                0x0000082c                __etext = .
+                0x0000082c                __DATA_ROM = .
+
+.interrupts_ram
+                0x1fff0000        0x0
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __VECTOR_RAM__ = .
+                0x1fff0000                __interrupts_ram_start__ = .
+ *(.m_interrupts_ram)
+                0x1fff0000                . = (. + M_VECTOR_RAM_SIZE)
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __interrupts_ram_end__ = .
+                0x00000000                __VECTOR_RAM = DEFINED (__ram_vector_table__)?__VECTOR_RAM__:ORIGIN (m_interrupts)
+                0x00000000                __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED (__ram_vector_table__)?(__interrupts_ram_end__ - __interrupts_ram_start__):0x0
+
+.data           0x1fff0000       0x64 load address 0x0000082c
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __DATA_RAM = .
+                0x1fff0000                __data_start__ = .
+ *(.data)
+ *(.data*)
+ .data.impure_data
+                0x1fff0000       0x60 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *(.jcr*)
+ .jcr           0x1fff0060        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .jcr           0x1fff0060        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __data_end__ = .
+                0x00000890                __DATA_END = (__DATA_ROM + (__data_end__ - __data_start__))
+                0x00100000                text_end = (ORIGIN (m_text) + 0xffbf0)
+                0x00000001                ASSERT ((__DATA_END <= text_end), region m_text overflowed with text and data)
+
+.igot.plt       0x1fff0064        0x0 load address 0x00000890
+ .igot.plt      0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.bss            0x1fff0064       0x1c load address 0x00000890
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __START_BSS = .
+                0x1fff0064                __bss_start__ = .
+ *(.bss)
+ .bss           0x1fff0064       0x1c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.bss*)
+ *(COMMON)
+                0x1fff0080                . = ALIGN (0x4)
+                0x1fff0080                __bss_end__ = .
+                0x1fff0080                __END_BSS = .
+
+.heap           0x20000000      0x400
+                0x20000000                . = ALIGN (0x8)
+                0x20000000                __end__ = .
+                0x20000000                PROVIDE (end, .)
+                0x20000000                __HeapBase = .
+                0x20000400                . = (. + HEAP_SIZE)
+ *fill*         0x20000000      0x400 
+                0x20000400                __HeapLimit = .
+
+.stack          0x20000400      0x400
+                0x20000400                . = ALIGN (0x8)
+                0x20000800                . = (. + STACK_SIZE)
+ *fill*         0x20000400      0x400 
+                0x20030000                __StackTop = (ORIGIN (m_data_2) + 0x30000)
+                0x2002fc00                __StackLimit = (__StackTop - STACK_SIZE)
+                0x20030000                PROVIDE (__stack, __StackTop)
+
+.ARM.attributes
+                0x00000000       0x30
+ *(.ARM.attributes)
+ .ARM.attributes
+                0x00000000       0x22 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .ARM.attributes
+                0x00000022       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .ARM.attributes
+                0x00000056       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.attributes
+                0x00000076       0x39 ./Sources/main.o
+ .ARM.attributes
+                0x000000af       0x39 ./Project_Settings/Startup_Code/startup.o
+ .ARM.attributes
+                0x000000e8       0x1f ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .ARM.attributes
+                0x00000107       0x39 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .ARM.attributes
+                0x00000140       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .ARM.attributes
+                0x00000174       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .ARM.attributes
+                0x000001a8       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .ARM.attributes
+                0x000001dc       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .ARM.attributes
+                0x00000210       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .ARM.attributes
+                0x00000244       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .ARM.attributes
+                0x00000278       0x22 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000001                ASSERT ((__StackLimit >= __HeapLimit), region m_data_2 overflowed with stack and heap)
+OUTPUT(GPIO.elf elf32-littlearm)
+
+.debug_info     0x00000000     0x1206
+ .debug_info    0x00000000      0x7c0 ./Sources/main.o
+ .debug_info    0x000007c0      0x3a7 ./Project_Settings/Startup_Code/startup.o
+ .debug_info    0x00000b67       0x8f ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_info    0x00000bf6      0x610 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_abbrev   0x00000000      0x399
+ .debug_abbrev  0x00000000      0x171 ./Sources/main.o
+ .debug_abbrev  0x00000171       0xfa ./Project_Settings/Startup_Code/startup.o
+ .debug_abbrev  0x0000026b       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_abbrev  0x0000027f      0x11a ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_aranges  0x00000000       0xa0
+ .debug_aranges
+                0x00000000       0x38 ./Sources/main.o
+ .debug_aranges
+                0x00000038       0x20 ./Project_Settings/Startup_Code/startup.o
+ .debug_aranges
+                0x00000058       0x20 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_aranges
+                0x00000078       0x28 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_ranges   0x00000000       0x50
+ .debug_ranges  0x00000000       0x28 ./Sources/main.o
+ .debug_ranges  0x00000028       0x10 ./Project_Settings/Startup_Code/startup.o
+ .debug_ranges  0x00000038       0x18 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_macro    0x00000000    0x30d8e
+ .debug_macro   0x00000000       0x8d ./Sources/main.o
+ .debug_macro   0x0000008d      0x856 ./Sources/main.o
+ .debug_macro   0x000008e3       0x16 ./Sources/main.o
+ .debug_macro   0x000008f9       0x16 ./Sources/main.o
+ .debug_macro   0x0000090f       0x44 ./Sources/main.o
+ .debug_macro   0x00000953      0x209 ./Sources/main.o
+ .debug_macro   0x00000b5c       0x56 ./Sources/main.o
+ .debug_macro   0x00000bb2       0x3b ./Sources/main.o
+ .debug_macro   0x00000bed       0x34 ./Sources/main.o
+ .debug_macro   0x00000c21       0x26 ./Sources/main.o
+ .debug_macro   0x00000c47      0xd1d ./Sources/main.o
+ .debug_macro   0x00001964       0x78 ./Sources/main.o
+ .debug_macro   0x000019dc    0x1773b ./Sources/main.o
+ .debug_macro   0x00019117      0x171 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019288       0x11 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019299       0x58 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000192f1       0x35 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019326       0xa3 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193c9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193df      0x10e ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000194ed       0x7f ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0001956c       0x52 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195be       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195d4       0x43 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019617      0x180 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019797       0x22 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197b9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197cf    0x16273 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0002fa42     0x1182 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00030bc4      0x162 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00030d26       0x68 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_line     0x00000000      0x9e3
+ .debug_line    0x00000000      0x296 ./Sources/main.o
+ .debug_line    0x00000296      0x358 ./Project_Settings/Startup_Code/startup.o
+ .debug_line    0x000005ee       0x6a ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_line    0x00000658      0x38b ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_str      0x00000000   0x19cfec
+ .debug_str     0x00000000    0x90040 ./Sources/main.o
+                              0x901dc (size before relaxing)
+ .debug_str     0x00090040   0x10ceb7 ./Project_Settings/Startup_Code/startup.o
+                             0x19ca7d (size before relaxing)
+ .debug_str     0x0019cef7       0xf5 ./Project_Settings/Startup_Code/system_MK64F12.o
+                             0x19cb38 (size before relaxing)
+
+.comment        0x00000000       0x70
+ .comment       0x00000000       0x70 ./Sources/main.o
+                                 0x71 (size before relaxing)
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/startup.o
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_frame    0x00000000      0x184
+ .debug_frame   0x00000000       0x80 ./Sources/main.o
+ .debug_frame   0x00000080       0x2c ./Project_Settings/Startup_Code/startup.o
+ .debug_frame   0x000000ac       0x44 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_frame   0x000000f0       0x28 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .debug_frame   0x00000118       0x2c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .debug_frame   0x00000144       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .debug_frame   0x00000164       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
diff --git a/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/startup.d b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/startup.d
new file mode 100644
index 0000000..09df623
--- /dev/null
+++ b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/startup.d
@@ -0,0 +1,38 @@
+Project_Settings/Startup_Code/startup.o: \
+ ../Project_Settings/Startup_Code/startup.c \
+ ../Project_Settings/Startup_Code/startup.h \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h
+
+../Project_Settings/Startup_Code/startup.h:
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
diff --git a/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/startup.o b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/startup.o
new file mode 100644
index 0000000..e804d0c
Binary files /dev/null and b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/startup.o differ
diff --git a/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/startup_MK64F12.d b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/startup_MK64F12.d
new file mode 100644
index 0000000..15e90f1
--- /dev/null
+++ b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/startup_MK64F12.d
@@ -0,0 +1,2 @@
+Project_Settings/Startup_Code/startup_MK64F12.o: \
+ ../Project_Settings/Startup_Code/startup_MK64F12.S
diff --git a/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/startup_MK64F12.o b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/startup_MK64F12.o
new file mode 100644
index 0000000..dce1a39
Binary files /dev/null and b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/startup_MK64F12.o differ
diff --git a/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/subdir.mk b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/subdir.mk
new file mode 100644
index 0000000..1e5a1fb
--- /dev/null
+++ b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/subdir.mk
@@ -0,0 +1,41 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Project_Settings/Startup_Code/startup.c \
+../Project_Settings/Startup_Code/system_MK64F12.c 
+
+S_UPPER_SRCS += \
+../Project_Settings/Startup_Code/startup_MK64F12.S 
+
+OBJS += \
+./Project_Settings/Startup_Code/startup.o \
+./Project_Settings/Startup_Code/startup_MK64F12.o \
+./Project_Settings/Startup_Code/system_MK64F12.o 
+
+C_DEPS += \
+./Project_Settings/Startup_Code/startup.d \
+./Project_Settings/Startup_Code/system_MK64F12.d 
+
+S_UPPER_DEPS += \
+./Project_Settings/Startup_Code/startup_MK64F12.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Project_Settings/Startup_Code/%.o: ../Project_Settings/Startup_Code/%.c
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM C Compiler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+Project_Settings/Startup_Code/%.o: ../Project_Settings/Startup_Code/%.S
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM GNU Assembler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+
diff --git a/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/system_MK64F12.d b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/system_MK64F12.d
new file mode 100644
index 0000000..d0e2961
--- /dev/null
+++ b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/system_MK64F12.d
@@ -0,0 +1,35 @@
+Project_Settings/Startup_Code/system_MK64F12.o: \
+ ../Project_Settings/Startup_Code/system_MK64F12.c \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
diff --git a/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/system_MK64F12.o b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/system_MK64F12.o
new file mode 100644
index 0000000..f5478f2
Binary files /dev/null and b/Workspace/Interrupt/Debug/Project_Settings/Startup_Code/system_MK64F12.o differ
diff --git a/Workspace/Interrupt/Debug/Sources/main.d b/Workspace/Interrupt/Debug/Sources/main.d
new file mode 100644
index 0000000..6984a8b
--- /dev/null
+++ b/Workspace/Interrupt/Debug/Sources/main.d
@@ -0,0 +1,19 @@
+Sources/main.o: ../Sources/main.c \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
diff --git a/Workspace/Interrupt/Debug/Sources/main.o b/Workspace/Interrupt/Debug/Sources/main.o
new file mode 100644
index 0000000..eb718d6
Binary files /dev/null and b/Workspace/Interrupt/Debug/Sources/main.o differ
diff --git a/Workspace/Interrupt/Debug/Sources/subdir.mk b/Workspace/Interrupt/Debug/Sources/subdir.mk
new file mode 100644
index 0000000..95aa41f
--- /dev/null
+++ b/Workspace/Interrupt/Debug/Sources/subdir.mk
@@ -0,0 +1,24 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Sources/main.c 
+
+OBJS += \
+./Sources/main.o 
+
+C_DEPS += \
+./Sources/main.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Sources/%.o: ../Sources/%.c
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM C Compiler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+
diff --git a/Workspace/Interrupt/Debug/makefile b/Workspace/Interrupt/Debug/makefile
new file mode 100644
index 0000000..5fc7a90
--- /dev/null
+++ b/Workspace/Interrupt/Debug/makefile
@@ -0,0 +1,77 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include Sources/subdir.mk
+-include Project_Settings/Startup_Code/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C++_DEPS)),)
+-include $(C++_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+ifneq ($(strip $(ASM_DEPS)),)
+-include $(ASM_DEPS)
+endif
+ifneq ($(strip $(CC_DEPS)),)
+-include $(CC_DEPS)
+endif
+ifneq ($(strip $(CPP_DEPS)),)
+-include $(CPP_DEPS)
+endif
+ifneq ($(strip $(CXX_DEPS)),)
+-include $(CXX_DEPS)
+endif
+ifneq ($(strip $(C_UPPER_DEPS)),)
+-include $(C_UPPER_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables 
+SECONDARY_SIZE += \
+GPIO.siz \
+
+
+# All Target
+all: GPIO.elf secondary-outputs
+
+# Tool invocations
+GPIO.elf: $(OBJS) $(USER_OBJS)
+	@echo 'Building target: $@'
+	@echo 'Invoking: Cross ARM C++ Linker'
+	arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -T "MK64FN1M0xxx12_flash.ld" -Xlinker --gc-sections -L"C:/Users/pkalgaon/Desktop/Workspace/Interrupt/Project_Settings/Linker_Files" -Wl,-Map,"GPIO.map" -specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs -o "GPIO.elf" $(OBJS) $(USER_OBJS) $(LIBS)
+	@echo 'Finished building target: $@'
+	@echo ' '
+
+GPIO.siz: GPIO.elf
+	@echo 'Invoking: Cross ARM GNU Print Size'
+	arm-none-eabi-size --format=berkeley "GPIO.elf"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+# Other Targets
+clean:
+	-$(RM) $(SECONDARY_SIZE)$(C++_DEPS)$(OBJS)$(C_DEPS)$(ASM_DEPS)$(CC_DEPS)$(CPP_DEPS)$(CXX_DEPS)$(C_UPPER_DEPS)$(S_UPPER_DEPS) GPIO.elf
+	-@echo ' '
+
+secondary-outputs: $(SECONDARY_SIZE)
+
+.PHONY: all clean dependents
+.SECONDARY:
+
+-include ../makefile.targets
diff --git a/Workspace/Interrupt/Debug/objects.mk b/Workspace/Interrupt/Debug/objects.mk
new file mode 100644
index 0000000..742c2da
--- /dev/null
+++ b/Workspace/Interrupt/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/Workspace/Interrupt/Debug/sources.mk b/Workspace/Interrupt/Debug/sources.mk
new file mode 100644
index 0000000..80f8a41
--- /dev/null
+++ b/Workspace/Interrupt/Debug/sources.mk
@@ -0,0 +1,31 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ELF_SRCS := 
+O_SRCS := 
+CPP_SRCS := 
+C_UPPER_SRCS := 
+C_SRCS := 
+S_UPPER_SRCS := 
+OBJ_SRCS := 
+ASM_SRCS := 
+CXX_SRCS := 
+C++_SRCS := 
+CC_SRCS := 
+SECONDARY_SIZE := 
+C++_DEPS := 
+OBJS := 
+C_DEPS := 
+ASM_DEPS := 
+CC_DEPS := 
+CPP_DEPS := 
+CXX_DEPS := 
+C_UPPER_DEPS := 
+S_UPPER_DEPS := 
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Sources \
+Project_Settings/Startup_Code \
+
diff --git a/Workspace/Interrupt/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch b/Workspace/Interrupt/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch
new file mode 100644
index 0000000..cae21a4
--- /dev/null
+++ b/Workspace/Interrupt/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doConnectToRunning" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f kinetis.cfg"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/GPIO.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="GPIO"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/GPIO"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/Interrupt/Project_Settings/Debugger/GPIO_Debug_Segger.launch b/Workspace/Interrupt/Project_Settings/Debugger/GPIO_Debug_Segger.launch
new file mode 100644
index 0000000..68923d5
--- /dev/null
+++ b/Workspace/Interrupt/Project_Settings/Debugger/GPIO_Debug_Segger.launch
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.jlink.launchConfigurationType">
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="MK64FN1M0xxx12"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="1000"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM J-Link"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/GPIO.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="GPIO"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/GPIO"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/Interrupt/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld b/Workspace/Interrupt/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
new file mode 100644
index 0000000..506082b
--- /dev/null
+++ b/Workspace/Interrupt/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
@@ -0,0 +1,245 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150624
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
+  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0
+  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
+  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+  } > m_data_2
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data_2
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
+}
+
diff --git a/Workspace/Interrupt/Project_Settings/Startup_Code/startup.c b/Workspace/Interrupt/Project_Settings/Startup_Code/startup.c
new file mode 100644
index 0000000..b89e7fc
--- /dev/null
+++ b/Workspace/Interrupt/Project_Settings/Startup_Code/startup.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "startup.h"
+#include "fsl_device_registers.h"
+
+#if (defined(__ICCARM__))
+    #pragma section = ".data"
+    #pragma section = ".data_init"
+    #pragma section = ".bss"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : init_data_bss
+ * Description   : Make necessary initializations for RAM.
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ *
+ * Tool Chians:
+ *   __GNUC__   : GCC
+ *   __CC_ARM   : KEIL
+ *   __ICCARM__ : IAR
+ *
+ *END**************************************************************************/
+void init_data_bss(void)
+{
+    uint32_t n; 
+    
+    /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+    #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base  
+    #define __VECTOR_RAM Image$$VECTOR_RAM$$Base  
+    #define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];  
+    extern uint32_t __VECTOR_RAM[];  
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif
+
+    if (__VECTOR_RAM != __VECTOR_TABLE)
+    {   
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+    else
+    {
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_TABLE;
+    }
+
+#if !defined(__CC_ARM) && !defined(__ICCARM__)
+    
+    /* Declare pointers for various data sections. These pointers
+     * are initialized using values pulled in from the linker file */
+    uint8_t * data_ram, * data_rom, * data_rom_end;
+    uint8_t * bss_start, * bss_end;
+
+    /* Get the addresses for the .data section (initialized data section) */
+#if defined(__GNUC__)
+    extern uint32_t __DATA_ROM[];
+    extern uint32_t __DATA_RAM[];
+    extern char __DATA_END[];
+    data_ram = (uint8_t *)__DATA_RAM;
+    data_rom = (uint8_t *)__DATA_ROM;
+    data_rom_end  = (uint8_t *)__DATA_END;
+    n = data_rom_end - data_rom;
+#endif
+
+    /* Copy initialized data from ROM to RAM */
+    while (n--)
+    {
+        *data_ram++ = *data_rom++;
+    }   
+    
+    /* Get the addresses for the .bss section (zero-initialized data) */
+#if defined(__GNUC__)
+    extern char __START_BSS[];
+    extern char __END_BSS[];
+    bss_start = (uint8_t *)__START_BSS;
+    bss_end = (uint8_t *)__END_BSS;
+#endif
+		
+    /* Clear the zero-initialized data section */
+    n = bss_end - bss_start;
+    while(n--)
+    {
+        *bss_start++ = 0;
+    }
+#endif /* !__CC_ARM && !__ICCARM__*/
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/Workspace/Interrupt/Project_Settings/Startup_Code/startup.h b/Workspace/Interrupt/Project_Settings/Startup_Code/startup.h
new file mode 100644
index 0000000..17ad55f
--- /dev/null
+++ b/Workspace/Interrupt/Project_Settings/Startup_Code/startup.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _STARTUP_H_
+#define _STARTUP_H_
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Make necessary initializations for RAM.
+ *
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ */
+void init_data_bss(void);
+
+#endif /* _STARTUP_H_*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/Workspace/Interrupt/Project_Settings/Startup_Code/startup_MK64F12.S b/Workspace/Interrupt/Project_Settings/Startup_Code/startup_MK64F12.S
new file mode 100644
index 0000000..aebe2e6
--- /dev/null
+++ b/Workspace/Interrupt/Project_Settings/Startup_Code/startup_MK64F12.S
@@ -0,0 +1,457 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK64F12.s                                                           */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK64F12                                                                     */
+/*  @version: 2.8                                                                         */
+/*  @date:    2015-2-19                                                                   */
+/*  @build:   b150225                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_IRQHandler                                 /* DMA Channel 0 Transfer Complete*/
+    .long   DMA1_IRQHandler                                 /* DMA Channel 1 Transfer Complete*/
+    .long   DMA2_IRQHandler                                 /* DMA Channel 2 Transfer Complete*/
+    .long   DMA3_IRQHandler                                 /* DMA Channel 3 Transfer Complete*/
+    .long   DMA4_IRQHandler                                 /* DMA Channel 4 Transfer Complete*/
+    .long   DMA5_IRQHandler                                 /* DMA Channel 5 Transfer Complete*/
+    .long   DMA6_IRQHandler                                 /* DMA Channel 6 Transfer Complete*/
+    .long   DMA7_IRQHandler                                 /* DMA Channel 7 Transfer Complete*/
+    .long   DMA8_IRQHandler                                 /* DMA Channel 8 Transfer Complete*/
+    .long   DMA9_IRQHandler                                 /* DMA Channel 9 Transfer Complete*/
+    .long   DMA10_IRQHandler                                /* DMA Channel 10 Transfer Complete*/
+    .long   DMA11_IRQHandler                                /* DMA Channel 11 Transfer Complete*/
+    .long   DMA12_IRQHandler                                /* DMA Channel 12 Transfer Complete*/
+    .long   DMA13_IRQHandler                                /* DMA Channel 13 Transfer Complete*/
+    .long   DMA14_IRQHandler                                /* DMA Channel 14 Transfer Complete*/
+    .long   DMA15_IRQHandler                                /* DMA Channel 15 Transfer Complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA Error Interrupt*/
+    .long   MCM_IRQHandler                                  /* Normal Interrupt*/
+    .long   FTFE_IRQHandler                                 /* FTFE Command complete interrupt*/
+    .long   Read_Collision_IRQHandler                       /* Read Collision Interrupt*/
+    .long   LVD_LVW_IRQHandler                              /* Low Voltage Detect, Low Voltage Warning*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup Unit*/
+    .long   WDOG_EWM_IRQHandler                             /* WDOG Interrupt*/
+    .long   RNG_IRQHandler                                  /* RNG Interrupt*/
+    .long   I2C0_IRQHandler                                 /* I2C0 interrupt*/
+    .long   I2C1_IRQHandler                                 /* I2C1 interrupt*/
+    .long   SPI0_IRQHandler                                 /* SPI0 Interrupt*/
+    .long   SPI1_IRQHandler                                 /* SPI1 Interrupt*/
+    .long   I2S0_Tx_IRQHandler                              /* I2S0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* I2S0 receive interrupt*/
+    .long   UART0_LON_IRQHandler                            /* UART0 LON interrupt*/
+    .long   UART0_RX_TX_IRQHandler                          /* UART0 Receive/Transmit interrupt*/
+    .long   UART0_ERR_IRQHandler                            /* UART0 Error interrupt*/
+    .long   UART1_RX_TX_IRQHandler                          /* UART1 Receive/Transmit interrupt*/
+    .long   UART1_ERR_IRQHandler                            /* UART1 Error interrupt*/
+    .long   UART2_RX_TX_IRQHandler                          /* UART2 Receive/Transmit interrupt*/
+    .long   UART2_ERR_IRQHandler                            /* UART2 Error interrupt*/
+    .long   UART3_RX_TX_IRQHandler                          /* UART3 Receive/Transmit interrupt*/
+    .long   UART3_ERR_IRQHandler                            /* UART3 Error interrupt*/
+    .long   ADC0_IRQHandler                                 /* ADC0 interrupt*/
+    .long   CMP0_IRQHandler                                 /* CMP0 interrupt*/
+    .long   CMP1_IRQHandler                                 /* CMP1 interrupt*/
+    .long   FTM0_IRQHandler                                 /* FTM0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FTM1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FTM2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* CMT interrupt*/
+    .long   RTC_IRQHandler                                  /* RTC interrupt*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds interrupt*/
+    .long   PIT0_IRQHandler                                 /* PIT timer channel 0 interrupt*/
+    .long   PIT1_IRQHandler                                 /* PIT timer channel 1 interrupt*/
+    .long   PIT2_IRQHandler                                 /* PIT timer channel 2 interrupt*/
+    .long   PIT3_IRQHandler                                 /* PIT timer channel 3 interrupt*/
+    .long   PDB0_IRQHandler                                 /* PDB0 Interrupt*/
+    .long   USB0_IRQHandler                                 /* USB0 interrupt*/
+    .long   USBDCD_IRQHandler                               /* USBDCD Interrupt*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt 71*/
+    .long   DAC0_IRQHandler                                 /* DAC0 interrupt*/
+    .long   MCG_IRQHandler                                  /* MCG Interrupt*/
+    .long   LPTMR0_IRQHandler                               /* LPTimer interrupt*/
+    .long   PORTA_IRQHandler                                /* Port A interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* SPI2 Interrupt*/
+    .long   UART4_RX_TX_IRQHandler                          /* UART4 Receive/Transmit interrupt*/
+    .long   UART4_ERR_IRQHandler                            /* UART4 Error interrupt*/
+    .long   UART5_RX_TX_IRQHandler                          /* UART5 Receive/Transmit interrupt*/
+    .long   UART5_ERR_IRQHandler                            /* UART5 Error interrupt*/
+    .long   CMP2_IRQHandler                                 /* CMP2 interrupt*/
+    .long   FTM3_IRQHandler                                 /* FTM3 fault, overflow and channels interrupt*/
+    .long   DAC1_IRQHandler                                 /* DAC1 interrupt*/
+    .long   ADC1_IRQHandler                                 /* ADC1 interrupt*/
+    .long   I2C2_IRQHandler                                 /* I2C2 interrupt*/
+    .long   CAN0_ORed_Message_buffer_IRQHandler             /* CAN0 OR'd message buffers interrupt*/
+    .long   CAN0_Bus_Off_IRQHandler                         /* CAN0 bus off interrupt*/
+    .long   CAN0_Error_IRQHandler                           /* CAN0 error interrupt*/
+    .long   CAN0_Tx_Warning_IRQHandler                      /* CAN0 Tx warning interrupt*/
+    .long   CAN0_Rx_Warning_IRQHandler                      /* CAN0 Rx warning interrupt*/
+    .long   CAN0_Wake_Up_IRQHandler                         /* CAN0 wake up interrupt*/
+    .long   SDHC_IRQHandler                                 /* SDHC interrupt*/
+    .long   ENET_1588_Timer_IRQHandler                      /* Ethernet MAC IEEE 1588 Timer Interrupt*/
+    .long   ENET_Transmit_IRQHandler                        /* Ethernet MAC Transmit Interrupt*/
+    .long   ENET_Receive_IRQHandler                         /* Ethernet MAC Receive Interrupt*/
+    .long   ENET_Error_IRQHandler                           /* Ethernet MAC Error and miscelaneous Interrupt*/
+    .long   DefaultISR                                      /* 102*/
+    .long   DefaultISR                                      /* 103*/
+    .long   DefaultISR                                      /* 104*/
+    .long   DefaultISR                                      /* 105*/
+    .long   DefaultISR                                      /* 106*/
+    .long   DefaultISR                                      /* 107*/
+    .long   DefaultISR                                      /* 108*/
+    .long   DefaultISR                                      /* 109*/
+    .long   DefaultISR                                      /* 110*/
+    .long   DefaultISR                                      /* 111*/
+    .long   DefaultISR                                      /* 112*/
+    .long   DefaultISR                                      /* 113*/
+    .long   DefaultISR                                      /* 114*/
+    .long   DefaultISR                                      /* 115*/
+    .long   DefaultISR                                      /* 116*/
+    .long   DefaultISR                                      /* 117*/
+    .long   DefaultISR                                      /* 118*/
+    .long   DefaultISR                                      /* 119*/
+    .long   DefaultISR                                      /* 120*/
+    .long   DefaultISR                                      /* 121*/
+    .long   DefaultISR                                      /* 122*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+    .long   DefaultISR                                      /* 240*/
+    .long   DefaultISR                                      /* 241*/
+    .long   DefaultISR                                      /* 242*/
+    .long   DefaultISR                                      /* 243*/
+    .long   DefaultISR                                      /* 244*/
+    .long   DefaultISR                                      /* 245*/
+    .long   DefaultISR                                      /* 246*/
+    .long   DefaultISR                                      /* 247*/
+    .long   DefaultISR                                      /* 248*/
+    .long   DefaultISR                                      /* 249*/
+    .long   DefaultISR                                      /* 250*/
+    .long   DefaultISR                                      /* 251*/
+    .long   DefaultISR                                      /* 252*/
+    .long   DefaultISR                                      /* 253*/
+    .long   DefaultISR                                      /* 254*/
+    .long   0xFFFFFFFF                                      /*  Reserved for user TRIM value*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_IRQHandler
+    def_irq_handler    DMA1_IRQHandler
+    def_irq_handler    DMA2_IRQHandler
+    def_irq_handler    DMA3_IRQHandler
+    def_irq_handler    DMA4_IRQHandler
+    def_irq_handler    DMA5_IRQHandler
+    def_irq_handler    DMA6_IRQHandler
+    def_irq_handler    DMA7_IRQHandler
+    def_irq_handler    DMA8_IRQHandler
+    def_irq_handler    DMA9_IRQHandler
+    def_irq_handler    DMA10_IRQHandler
+    def_irq_handler    DMA11_IRQHandler
+    def_irq_handler    DMA12_IRQHandler
+    def_irq_handler    DMA13_IRQHandler
+    def_irq_handler    DMA14_IRQHandler
+    def_irq_handler    DMA15_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFE_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    RNG_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    UART0_LON_IRQHandler
+    def_irq_handler    UART0_RX_TX_IRQHandler
+    def_irq_handler    UART0_ERR_IRQHandler
+    def_irq_handler    UART1_RX_TX_IRQHandler
+    def_irq_handler    UART1_ERR_IRQHandler
+    def_irq_handler    UART2_RX_TX_IRQHandler
+    def_irq_handler    UART2_ERR_IRQHandler
+    def_irq_handler    UART3_RX_TX_IRQHandler
+    def_irq_handler    UART3_ERR_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    PIT1_IRQHandler
+    def_irq_handler    PIT2_IRQHandler
+    def_irq_handler    PIT3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    UART4_RX_TX_IRQHandler
+    def_irq_handler    UART4_ERR_IRQHandler
+    def_irq_handler    UART5_RX_TX_IRQHandler
+    def_irq_handler    UART5_ERR_IRQHandler
+    def_irq_handler    CMP2_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    DAC1_IRQHandler
+    def_irq_handler    ADC1_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    CAN0_ORed_Message_buffer_IRQHandler
+    def_irq_handler    CAN0_Bus_Off_IRQHandler
+    def_irq_handler    CAN0_Error_IRQHandler
+    def_irq_handler    CAN0_Tx_Warning_IRQHandler
+    def_irq_handler    CAN0_Rx_Warning_IRQHandler
+    def_irq_handler    CAN0_Wake_Up_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    ENET_1588_Timer_IRQHandler
+    def_irq_handler    ENET_Transmit_IRQHandler
+    def_irq_handler    ENET_Receive_IRQHandler
+    def_irq_handler    ENET_Error_IRQHandler
+
+    .end
diff --git a/Workspace/Interrupt/Project_Settings/Startup_Code/system_MK64F12.c b/Workspace/Interrupt/Project_Settings/Startup_Code/system_MK64F12.c
new file mode 100644
index 0000000..e3c1376
--- /dev/null
+++ b/Workspace/Interrupt/Project_Settings/Startup_Code/system_MK64F12.c
@@ -0,0 +1,414 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief Device specific configuration file for MK64F12 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+#if (DISABLE_WDOG)
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+  /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+  WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+                 WDOG_STCTRLH_WAITEN_MASK |
+                 WDOG_STCTRLH_STOPEN_MASK |
+                 WDOG_STCTRLH_ALLOWUPDATE_MASK |
+                 WDOG_STCTRLH_CLKSRC_MASK |
+                 0x0100U;
+#endif /* (DISABLE_WDOG) */
+#ifdef CLOCK_SETUP
+  if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
+  {
+    if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
+    {
+       PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO:  Only has an effect if recovering from VLLSx.*/
+    }
+  } else {
+#ifdef SYSTEM_RTC_CR_VALUE
+    SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
+    if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
+      RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
+      RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
+      RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
+    }
+#endif
+  }
+
+  /* Power mode protection initialization */
+#ifdef SYSTEM_SMC_PMPROT_VALUE
+  SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
+#endif
+
+  /* System clock initialization */
+  /* Internal reference clock trim initialization */
+#if defined(SLOW_TRIM_ADDRESS)
+  if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) {                              /* Skip if non-volatile flash memory is erased */
+    MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
+  #endif /* defined(SLOW_TRIM_ADDRESS) */
+  #if defined(SLOW_FINE_TRIM_ADDRESS)
+    MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
+  #endif
+  #if defined(FAST_TRIM_ADDRESS)
+    MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
+  #endif
+  #if defined(FAST_FINE_TRIM_ADDRESS)
+    MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
+  #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
+#if defined(SLOW_TRIM_ADDRESS)
+  }
+  #endif /* defined(SLOW_TRIM_ADDRESS) */
+
+  /* Set system prescalers and clock sources */
+  SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
+  SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
+  SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+  /* Set MCG and OSC */
+#if  ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+  /* PORTA_PCR19: ISF=0,MUX=0 */
+  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
+  MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+  /* Check that the source of the FLL reference clock is the requested one. */
+  if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+    }
+  } else {
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+    }
+  }
+  MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+  MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+  OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
+  #if (MCG_MODE == MCG_MODE_BLPI)
+  /* BLPI specific */
+  MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
+  #endif
+
+#else /* MCG_MODE */
+  /* Set MCG and OSC */
+#if  (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+  /* PORTA_PCR19: ISF=0,MUX=0 */
+  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
+  MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+  OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
+  #if (MCG_MODE == MCG_MODE_PEE)
+  MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
+  #else
+  MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+  #endif
+  if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
+    while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
+    }
+  }
+  /* Check that the source of the FLL reference clock is the requested one. */
+  if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+    }
+  } else {
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+    }
+  }
+  MCG->C4 = ((SYSTEM_MCG_C4_VALUE)  & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+#endif /* MCG_MODE */
+
+  /* Common for all MCG modes */
+
+  /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
+  MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
+  MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+  if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
+    MCG->C5 |= MCG_C5_PLLCLKEN0_MASK;  /* PLL clock enable in mode other than PEE or PBE */
+  }
+  /* BLPE, PEE and PBE MCG mode specific */
+
+#if (MCG_MODE == MCG_MODE_BLPE)
+  MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
+#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
+  MCG->C6 |= (MCG_C6_PLLS_MASK);       /* Set C6 (PLL select, VCO divider etc.) */
+  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
+  }
+  #if (MCG_MODE == MCG_MODE_PEE)
+  MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
+  #endif
+#endif
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
+  }
+  /* Use LPTMR to wait for 1ms dor FLL clock stabilization */
+  SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;   /* Alow software control of LPMTR */
+  LPTMR0->CMR = LPTMR_CMR_COMPARE(0);  /* Default 1 LPO tick */
+  LPTMR0->CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00));
+  LPTMR0->PSR = (LPTMR_PSR_PCS(0x01) | LPTMR_PSR_PBYP_MASK); /* Clock source: LPO, Prescaler bypass enable */
+  LPTMR0->CSR = LPTMR_CSR_TEN_MASK;    /* LPMTR enable */
+  while((LPTMR0_CSR & LPTMR_CSR_TCF_MASK) == 0u) {
+  }
+  LPTMR0_CSR = 0x00;                   /* Disable LPTMR */
+  SIM_SCGC5 &= (uint32_t)~(uint32_t)SIM_SCGC5_LPTMR_MASK;
+#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
+  }
+#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+  }
+#elif (MCG_MODE == MCG_MODE_PEE)
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
+  }
+#endif
+#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
+  SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
+  while(SMC->PMSTAT != 0x04U) {        /* Wait until the system is in VLPR mode */
+  }
+#endif
+
+#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
+  SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
+#endif
+
+  /* PLL loss of lock interrupt request initialization */
+  if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
+    NVIC_EnableIRQ(MCG_IRQn);          /* Enable PLL loss of lock interrupt request */
+  }
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+  uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
+  uint16_t Divider;
+
+  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
+    /* Output of FLL or PLL is selected */
+    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
+      /* FLL is selected */
+      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+        case 0x00U:
+          MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+          break;
+        case 0x01U:
+          MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+          break;
+        case 0x02U:
+        default:
+          MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+          break;
+        }
+        if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
+          switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
+          case 0x38U:
+            Divider = 1536U;
+            break;
+          case 0x30U:
+            Divider = 1280U;
+            break;
+          default:
+            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+            break;
+          }
+        } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+          Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+        }
+        MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+        MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+      /* Select correct multiplier to calculate the MCG output clock  */
+      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+        case 0x00U:
+          MCGOUTClock *= 640U;
+          break;
+        case 0x20U:
+          MCGOUTClock *= 1280U;
+          break;
+        case 0x40U:
+          MCGOUTClock *= 1920U;
+          break;
+        case 0x60U:
+          MCGOUTClock *= 2560U;
+          break;
+        case 0x80U:
+          MCGOUTClock *= 732U;
+          break;
+        case 0xA0U:
+          MCGOUTClock *= 1464U;
+          break;
+        case 0xC0U:
+          MCGOUTClock *= 2197U;
+          break;
+        case 0xE0U:
+          MCGOUTClock *= 2929U;
+          break;
+        default:
+          break;
+      }
+    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+      /* PLL is selected */
+      Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
+      MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+      Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
+      MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
+    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
+    /* Internal reference clock is selected */
+    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+      Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+      MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
+    /* External reference clock is selected */
+    switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+    case 0x00U:
+      MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
+      break;
+    case 0x01U:
+      MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+      break;
+    case 0x02U:
+    default:
+      MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+      break;
+    }
+  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    /* Reserved value */
+    return;
+  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+  SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/Workspace/Interrupt/Project_Settings/Startup_Code/system_MK64F12.h b/Workspace/Interrupt/Project_Settings/Startup_Code/system_MK64F12.h
new file mode 100644
index 0000000..d6a5f05
--- /dev/null
+++ b/Workspace/Interrupt/Project_Settings/Startup_Code/system_MK64F12.h
@@ -0,0 +1,352 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief Device specific configuration file for MK64F12 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK64F12_H_
+#define SYSTEM_MK64F12_H_                        /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG                 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI                   0U
+#define MCG_MODE_FBI                   1U
+#define MCG_MODE_BLPI                  2U
+#define MCG_MODE_FEE                   3U
+#define MCG_MODE_FBE                   4U
+#define MCG_MODE_BLPE                  5U
+#define MCG_MODE_PBE                   6U
+#define MCG_MODE_PEE                   7U
+
+/* Predefined clock setups
+   0 ... Default  part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock = 20.97152MHz
+         Bus clock  = 20.97152MHz
+   1 ... Maximum achievable clock frequency configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+   2 ... Chip internaly clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   3 ... Chip externally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: RTC oscillator reference clock
+         Core clock = 0.032768MHz
+         Bus clock  = 0.032768MHz
+   4 ... USB clock setup
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+ */
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ                50000000u           /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_XTAL32k_CLK_HZ             32768u              /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+#define CPU_INT_SLOW_CLK_HZ            32768u              /* Value of the slow internal oscillator clock frequency in Hz  */
+#define CPU_INT_FAST_CLK_HZ            4000000u            /* Value of the fast internal oscillator clock frequency in Hz  */
+#define CPU_INT_IRC_CLK_HZ             48000000u           /* Value of the 48M internal oscillator clock frequency in Hz  */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE            0x0300U             /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE        0x2AU               /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */                             /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */                        /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */                             /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */                        /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_FEI /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x06U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00110000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00U               /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 1)
+  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 2)
+  #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_BLPI /* Clock generator mode */
+  /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x46U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00040000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 3)
+  #define DEFAULT_SYSTEM_CLOCK         32768u              /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_BLPE /* Clock generator mode */
+  /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x82U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x02U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=1 */
+  #define SYSTEM_MCG_C7_VALUE          0x01U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00U               /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 4)
+  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
+  #define SYSTEM_SIM_CLKDIV2_VALUE     0x09U               /* SIM_CLKDIV2 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
+#endif
+#else
+  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* #if !defined(SYSTEM_MK64F12_H_) */
diff --git a/Workspace/Interrupt/SDK/platform/CMSIS/Include/arm_common_tables.h b/Workspace/Interrupt/SDK/platform/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000..039cc3d
--- /dev/null
+++ b/Workspace/Interrupt/SDK/platform/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/Workspace/Interrupt/SDK/platform/CMSIS/Include/arm_const_structs.h b/Workspace/Interrupt/SDK/platform/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 0000000..726d06e
--- /dev/null
+++ b/Workspace/Interrupt/SDK/platform/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/Workspace/Interrupt/SDK/platform/CMSIS/Include/arm_math.h b/Workspace/Interrupt/SDK/platform/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000..e4b2f62
--- /dev/null
+++ b/Workspace/Interrupt/SDK/platform/CMSIS/Include/arm_math.h
@@ -0,0 +1,7556 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_math.h
+*
+* Description:	Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   * 
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   * 
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+  #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31	   0x400000
+#define TABLE_SPACING_Q15	   0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+#elif defined __GNUC__
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__			/* Cosmic */
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+#elif defined __TASKING__
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+//#define __CLZ __clz
+//#endif
+
+//note: function can be removed when all toolchain support __CLZ for Cortex-M0
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+      ((q15_t) x * (q15_t) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		 *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15( 
+    const arm_cfft_instance_q15 * S, 
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31( 
+    const arm_cfft_instance_q31 * S, 
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+  
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in >= 0.0f)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+   
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("push")         \
+         _Pragma ("O1")
+    #else
+      #define LOW_OPTIMIZATION_ENTER 
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_EXIT \
+         _Pragma ("pop")
+    #else
+      #define LOW_OPTIMIZATION_EXIT  
+    #endif
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)		// Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)		// TASKING
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/Workspace/Interrupt/SDK/platform/CMSIS/Include/core_cm4.h b/Workspace/Interrupt/SDK/platform/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000..9749c27
--- /dev/null
+++ b/Workspace/Interrupt/SDK/platform/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1858 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)IRQn < 0) {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)IRQn < 0) {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                             /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Workspace/Interrupt/SDK/platform/CMSIS/Include/core_cmFunc.h b/Workspace/Interrupt/SDK/platform/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000..b6ad0a4
--- /dev/null
+++ b/Workspace/Interrupt/SDK/platform/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,664 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+    or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+	or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/Workspace/Interrupt/SDK/platform/CMSIS/Include/core_cmInstr.h b/Workspace/Interrupt/SDK/platform/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000..fca425c
--- /dev/null
+++ b/Workspace/Interrupt/SDK/platform/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,916 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+  return(result);
+}
+#endif
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+#endif
+  return(result);
+}
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/Workspace/Interrupt/SDK/platform/CMSIS/Include/core_cmSimd.h b/Workspace/Interrupt/SDK/platform/CMSIS/Include/core_cmSimd.h
new file mode 100644
index 0000000..7b8e37f
--- /dev/null
+++ b/Workspace/Interrupt/SDK/platform/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/Workspace/Interrupt/SDK/platform/devices/MK64F12/include/MK64F12.h b/Workspace/Interrupt/SDK/platform/devices/MK64F12/include/MK64F12.h
new file mode 100644
index 0000000..3114ad7
--- /dev/null
+++ b/Workspace/Interrupt/SDK/platform/devices/MK64F12/include/MK64F12.h
@@ -0,0 +1,18767 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MK64F12
+**
+**     Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12.h
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief CMSIS Peripheral Access Layer for MK64F12
+ *
+ * CMSIS Peripheral Access Layer for MK64F12
+ */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCU activation
+   ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MK64F12_H_)  /* Check if memory map has not been already included */
+#define MK64F12_H_
+#define MCU_MK64F12
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+  #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0008u
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ *        bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ *        0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return  Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 102                /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_IRQn                    = 0,                /**< DMA Channel 0 Transfer Complete */
+  DMA1_IRQn                    = 1,                /**< DMA Channel 1 Transfer Complete */
+  DMA2_IRQn                    = 2,                /**< DMA Channel 2 Transfer Complete */
+  DMA3_IRQn                    = 3,                /**< DMA Channel 3 Transfer Complete */
+  DMA4_IRQn                    = 4,                /**< DMA Channel 4 Transfer Complete */
+  DMA5_IRQn                    = 5,                /**< DMA Channel 5 Transfer Complete */
+  DMA6_IRQn                    = 6,                /**< DMA Channel 6 Transfer Complete */
+  DMA7_IRQn                    = 7,                /**< DMA Channel 7 Transfer Complete */
+  DMA8_IRQn                    = 8,                /**< DMA Channel 8 Transfer Complete */
+  DMA9_IRQn                    = 9,                /**< DMA Channel 9 Transfer Complete */
+  DMA10_IRQn                   = 10,               /**< DMA Channel 10 Transfer Complete */
+  DMA11_IRQn                   = 11,               /**< DMA Channel 11 Transfer Complete */
+  DMA12_IRQn                   = 12,               /**< DMA Channel 12 Transfer Complete */
+  DMA13_IRQn                   = 13,               /**< DMA Channel 13 Transfer Complete */
+  DMA14_IRQn                   = 14,               /**< DMA Channel 14 Transfer Complete */
+  DMA15_IRQn                   = 15,               /**< DMA Channel 15 Transfer Complete */
+  DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
+  MCM_IRQn                     = 17,               /**< Normal Interrupt */
+  FTFE_IRQn                    = 18,               /**< FTFE Command complete interrupt */
+  Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
+  LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
+  LLWU_IRQn                    = 21,               /**< Low Leakage Wakeup Unit */
+  WDOG_EWM_IRQn                = 22,               /**< WDOG Interrupt */
+  RNG_IRQn                     = 23,               /**< RNG Interrupt */
+  I2C0_IRQn                    = 24,               /**< I2C0 interrupt */
+  I2C1_IRQn                    = 25,               /**< I2C1 interrupt */
+  SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
+  SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
+  I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
+  I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
+  UART0_LON_IRQn               = 30,               /**< UART0 LON interrupt */
+  UART0_RX_TX_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
+  UART0_ERR_IRQn               = 32,               /**< UART0 Error interrupt */
+  UART1_RX_TX_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
+  UART1_ERR_IRQn               = 34,               /**< UART1 Error interrupt */
+  UART2_RX_TX_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
+  UART2_ERR_IRQn               = 36,               /**< UART2 Error interrupt */
+  UART3_RX_TX_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
+  UART3_ERR_IRQn               = 38,               /**< UART3 Error interrupt */
+  ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
+  CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
+  FTM0_IRQn                    = 42,               /**< FTM0 fault, overflow and channels interrupt */
+  FTM1_IRQn                    = 43,               /**< FTM1 fault, overflow and channels interrupt */
+  FTM2_IRQn                    = 44,               /**< FTM2 fault, overflow and channels interrupt */
+  CMT_IRQn                     = 45,               /**< CMT interrupt */
+  RTC_IRQn                     = 46,               /**< RTC interrupt */
+  RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
+  PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
+  PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
+  PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
+  PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
+  PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
+  USB0_IRQn                    = 53,               /**< USB0 interrupt */
+  USBDCD_IRQn                  = 54,               /**< USBDCD Interrupt */
+  Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
+  DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
+  MCG_IRQn                     = 57,               /**< MCG Interrupt */
+  LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
+  PORTA_IRQn                   = 59,               /**< Port A interrupt */
+  PORTB_IRQn                   = 60,               /**< Port B interrupt */
+  PORTC_IRQn                   = 61,               /**< Port C interrupt */
+  PORTD_IRQn                   = 62,               /**< Port D interrupt */
+  PORTE_IRQn                   = 63,               /**< Port E interrupt */
+  SWI_IRQn                     = 64,               /**< Software interrupt */
+  SPI2_IRQn                    = 65,               /**< SPI2 Interrupt */
+  UART4_RX_TX_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
+  UART4_ERR_IRQn               = 67,               /**< UART4 Error interrupt */
+  UART5_RX_TX_IRQn             = 68,               /**< UART5 Receive/Transmit interrupt */
+  UART5_ERR_IRQn               = 69,               /**< UART5 Error interrupt */
+  CMP2_IRQn                    = 70,               /**< CMP2 interrupt */
+  FTM3_IRQn                    = 71,               /**< FTM3 fault, overflow and channels interrupt */
+  DAC1_IRQn                    = 72,               /**< DAC1 interrupt */
+  ADC1_IRQn                    = 73,               /**< ADC1 interrupt */
+  I2C2_IRQn                    = 74,               /**< I2C2 interrupt */
+  CAN0_ORed_Message_buffer_IRQn = 75,              /**< CAN0 OR'd message buffers interrupt */
+  CAN0_Bus_Off_IRQn            = 76,               /**< CAN0 bus off interrupt */
+  CAN0_Error_IRQn              = 77,               /**< CAN0 error interrupt */
+  CAN0_Tx_Warning_IRQn         = 78,               /**< CAN0 Tx warning interrupt */
+  CAN0_Rx_Warning_IRQn         = 79,               /**< CAN0 Rx warning interrupt */
+  CAN0_Wake_Up_IRQn            = 80,               /**< CAN0 wake up interrupt */
+  SDHC_IRQn                    = 81,               /**< SDHC interrupt */
+  ENET_1588_Timer_IRQn         = 82,               /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+  ENET_Transmit_IRQn           = 83,               /**< Ethernet MAC Transmit Interrupt */
+  ENET_Receive_IRQn            = 84,               /**< Ethernet MAC Receive Interrupt */
+  ENET_Error_IRQn              = 85                /**< Ethernet MAC Error and miscelaneous Interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_MK64F12.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index)                  ((base)->SC1[index])
+#define ADC_SC1_COUNT                            2
+#define ADC_CFG1_REG(base)                       ((base)->CFG1)
+#define ADC_CFG2_REG(base)                       ((base)->CFG2)
+#define ADC_R_REG(base,index)                    ((base)->R[index])
+#define ADC_R_COUNT                              2
+#define ADC_CV1_REG(base)                        ((base)->CV1)
+#define ADC_CV2_REG(base)                        ((base)->CV2)
+#define ADC_SC2_REG(base)                        ((base)->SC2)
+#define ADC_SC3_REG(base)                        ((base)->SC3)
+#define ADC_OFS_REG(base)                        ((base)->OFS)
+#define ADC_PG_REG(base)                         ((base)->PG)
+#define ADC_MG_REG(base)                         ((base)->MG)
+#define ADC_CLPD_REG(base)                       ((base)->CLPD)
+#define ADC_CLPS_REG(base)                       ((base)->CLPS)
+#define ADC_CLP4_REG(base)                       ((base)->CLP4)
+#define ADC_CLP3_REG(base)                       ((base)->CLP3)
+#define ADC_CLP2_REG(base)                       ((base)->CLP2)
+#define ADC_CLP1_REG(base)                       ((base)->CLP1)
+#define ADC_CLP0_REG(base)                       ((base)->CLP0)
+#define ADC_CLMD_REG(base)                       ((base)->CLMD)
+#define ADC_CLMS_REG(base)                       ((base)->CLMS)
+#define ADC_CLM4_REG(base)                       ((base)->CLM4)
+#define ADC_CLM3_REG(base)                       ((base)->CLM3)
+#define ADC_CLM2_REG(base)                       ((base)->CLM2)
+#define ADC_CLM1_REG(base)                       ((base)->CLM1)
+#define ADC_CLM0_REG(base)                       ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK                        0x1Fu
+#define ADC_SC1_ADCH_SHIFT                       0
+#define ADC_SC1_ADCH_WIDTH                       5
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        0x20u
+#define ADC_SC1_DIFF_SHIFT                       5
+#define ADC_SC1_DIFF_WIDTH                       1
+#define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK                        0x40u
+#define ADC_SC1_AIEN_SHIFT                       6
+#define ADC_SC1_AIEN_WIDTH                       1
+#define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK                        0x80u
+#define ADC_SC1_COCO_SHIFT                       7
+#define ADC_SC1_COCO_WIDTH                       1
+#define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK                     0x3u
+#define ADC_CFG1_ADICLK_SHIFT                    0
+#define ADC_CFG1_ADICLK_WIDTH                    2
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       0xCu
+#define ADC_CFG1_MODE_SHIFT                      2
+#define ADC_CFG1_MODE_WIDTH                      2
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     0x10u
+#define ADC_CFG1_ADLSMP_SHIFT                    4
+#define ADC_CFG1_ADLSMP_WIDTH                    1
+#define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK                       0x60u
+#define ADC_CFG1_ADIV_SHIFT                      5
+#define ADC_CFG1_ADIV_WIDTH                      2
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      0x80u
+#define ADC_CFG1_ADLPC_SHIFT                     7
+#define ADC_CFG1_ADLPC_WIDTH                     1
+#define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK                     0x3u
+#define ADC_CFG2_ADLSTS_SHIFT                    0
+#define ADC_CFG2_ADLSTS_WIDTH                    2
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      0x4u
+#define ADC_CFG2_ADHSC_SHIFT                     2
+#define ADC_CFG2_ADHSC_WIDTH                     1
+#define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK                    0x8u
+#define ADC_CFG2_ADACKEN_SHIFT                   3
+#define ADC_CFG2_ADACKEN_WIDTH                   1
+#define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK                     0x10u
+#define ADC_CFG2_MUXSEL_SHIFT                    4
+#define ADC_CFG2_MUXSEL_WIDTH                    1
+#define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
+/* R Bit Fields */
+#define ADC_R_D_MASK                             0xFFFFu
+#define ADC_R_D_SHIFT                            0
+#define ADC_R_D_WIDTH                            16
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK                          0xFFFFu
+#define ADC_CV1_CV_SHIFT                         0
+#define ADC_CV1_CV_WIDTH                         16
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK                          0xFFFFu
+#define ADC_CV2_CV_SHIFT                         0
+#define ADC_CV2_CV_WIDTH                         16
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK                      0x3u
+#define ADC_SC2_REFSEL_SHIFT                     0
+#define ADC_SC2_REFSEL_WIDTH                     2
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       0x4u
+#define ADC_SC2_DMAEN_SHIFT                      2
+#define ADC_SC2_DMAEN_WIDTH                      1
+#define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK                       0x8u
+#define ADC_SC2_ACREN_SHIFT                      3
+#define ADC_SC2_ACREN_WIDTH                      1
+#define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK                       0x10u
+#define ADC_SC2_ACFGT_SHIFT                      4
+#define ADC_SC2_ACFGT_WIDTH                      1
+#define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK                        0x20u
+#define ADC_SC2_ACFE_SHIFT                       5
+#define ADC_SC2_ACFE_WIDTH                       1
+#define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK                       0x40u
+#define ADC_SC2_ADTRG_SHIFT                      6
+#define ADC_SC2_ADTRG_WIDTH                      1
+#define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK                       0x80u
+#define ADC_SC2_ADACT_SHIFT                      7
+#define ADC_SC2_ADACT_WIDTH                      1
+#define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK                        0x3u
+#define ADC_SC3_AVGS_SHIFT                       0
+#define ADC_SC3_AVGS_WIDTH                       2
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        0x4u
+#define ADC_SC3_AVGE_SHIFT                       2
+#define ADC_SC3_AVGE_WIDTH                       1
+#define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK                        0x8u
+#define ADC_SC3_ADCO_SHIFT                       3
+#define ADC_SC3_ADCO_WIDTH                       1
+#define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK                        0x40u
+#define ADC_SC3_CALF_SHIFT                       6
+#define ADC_SC3_CALF_WIDTH                       1
+#define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK                         0x80u
+#define ADC_SC3_CAL_SHIFT                        7
+#define ADC_SC3_CAL_WIDTH                        1
+#define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK                         0xFFFFu
+#define ADC_OFS_OFS_SHIFT                        0
+#define ADC_OFS_OFS_WIDTH                        16
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK                           0xFFFFu
+#define ADC_PG_PG_SHIFT                          0
+#define ADC_PG_PG_WIDTH                          16
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK                           0xFFFFu
+#define ADC_MG_MG_SHIFT                          0
+#define ADC_MG_MG_WIDTH                          16
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK                       0x3Fu
+#define ADC_CLPD_CLPD_SHIFT                      0
+#define ADC_CLPD_CLPD_WIDTH                      6
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK                       0x3Fu
+#define ADC_CLPS_CLPS_SHIFT                      0
+#define ADC_CLPS_CLPS_WIDTH                      6
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK                       0x3FFu
+#define ADC_CLP4_CLP4_SHIFT                      0
+#define ADC_CLP4_CLP4_WIDTH                      10
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK                       0x1FFu
+#define ADC_CLP3_CLP3_SHIFT                      0
+#define ADC_CLP3_CLP3_WIDTH                      9
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK                       0xFFu
+#define ADC_CLP2_CLP2_SHIFT                      0
+#define ADC_CLP2_CLP2_WIDTH                      8
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK                       0x7Fu
+#define ADC_CLP1_CLP1_SHIFT                      0
+#define ADC_CLP1_CLP1_WIDTH                      7
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK                       0x3Fu
+#define ADC_CLP0_CLP0_SHIFT                      0
+#define ADC_CLP0_CLP0_WIDTH                      6
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK                       0x3Fu
+#define ADC_CLMD_CLMD_SHIFT                      0
+#define ADC_CLMD_CLMD_WIDTH                      6
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK                       0x3Fu
+#define ADC_CLMS_CLMS_SHIFT                      0
+#define ADC_CLMS_CLMS_WIDTH                      6
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK                       0x3FFu
+#define ADC_CLM4_CLM4_SHIFT                      0
+#define ADC_CLM4_CLM4_WIDTH                      10
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK                       0x1FFu
+#define ADC_CLM3_CLM3_SHIFT                      0
+#define ADC_CLM3_CLM3_WIDTH                      9
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK                       0xFFu
+#define ADC_CLM2_CLM2_SHIFT                      0
+#define ADC_CLM2_CLM2_WIDTH                      8
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK                       0x7Fu
+#define ADC_CLM1_CLM1_SHIFT                      0
+#define ADC_CLM1_CLM1_WIDTH                      7
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK                       0x3Fu
+#define ADC_CLM0_CLM0_SHIFT                      0
+#define ADC_CLM0_CLM0_WIDTH                      6
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR                            (ADC0)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_Type *)ADC1_BASE)
+#define ADC1_BASE_PTR                            (ADC1)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A                                ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B                                ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1                                ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2                                ADC_CFG2_REG(ADC0)
+#define ADC0_RA                                  ADC_R_REG(ADC0,0)
+#define ADC0_RB                                  ADC_R_REG(ADC0,1)
+#define ADC0_CV1                                 ADC_CV1_REG(ADC0)
+#define ADC0_CV2                                 ADC_CV2_REG(ADC0)
+#define ADC0_SC2                                 ADC_SC2_REG(ADC0)
+#define ADC0_SC3                                 ADC_SC3_REG(ADC0)
+#define ADC0_OFS                                 ADC_OFS_REG(ADC0)
+#define ADC0_PG                                  ADC_PG_REG(ADC0)
+#define ADC0_MG                                  ADC_MG_REG(ADC0)
+#define ADC0_CLPD                                ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS                                ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4                                ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3                                ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2                                ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1                                ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0                                ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD                                ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS                                ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4                                ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3                                ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2                                ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1                                ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0                                ADC_CLM0_REG(ADC0)
+/* ADC1 */
+#define ADC1_SC1A                                ADC_SC1_REG(ADC1,0)
+#define ADC1_SC1B                                ADC_SC1_REG(ADC1,1)
+#define ADC1_CFG1                                ADC_CFG1_REG(ADC1)
+#define ADC1_CFG2                                ADC_CFG2_REG(ADC1)
+#define ADC1_RA                                  ADC_R_REG(ADC1,0)
+#define ADC1_RB                                  ADC_R_REG(ADC1,1)
+#define ADC1_CV1                                 ADC_CV1_REG(ADC1)
+#define ADC1_CV2                                 ADC_CV2_REG(ADC1)
+#define ADC1_SC2                                 ADC_SC2_REG(ADC1)
+#define ADC1_SC3                                 ADC_SC3_REG(ADC1)
+#define ADC1_OFS                                 ADC_OFS_REG(ADC1)
+#define ADC1_PG                                  ADC_PG_REG(ADC1)
+#define ADC1_MG                                  ADC_MG_REG(ADC1)
+#define ADC1_CLPD                                ADC_CLPD_REG(ADC1)
+#define ADC1_CLPS                                ADC_CLPS_REG(ADC1)
+#define ADC1_CLP4                                ADC_CLP4_REG(ADC1)
+#define ADC1_CLP3                                ADC_CLP3_REG(ADC1)
+#define ADC1_CLP2                                ADC_CLP2_REG(ADC1)
+#define ADC1_CLP1                                ADC_CLP1_REG(ADC1)
+#define ADC1_CLP0                                ADC_CLP0_REG(ADC1)
+#define ADC1_CLMD                                ADC_CLMD_REG(ADC1)
+#define ADC1_CLMS                                ADC_CLMS_REG(ADC1)
+#define ADC1_CLM4                                ADC_CLM4_REG(ADC1)
+#define ADC1_CLM3                                ADC_CLM3_REG(ADC1)
+#define ADC1_CLM2                                ADC_CLM2_REG(ADC1)
+#define ADC1_CLM1                                ADC_CLM1_REG(ADC1)
+#define ADC1_CLM0                                ADC_CLM0_REG(ADC1)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index)                          ADC_SC1_REG(ADC0,index)
+#define ADC1_SC1(index)                          ADC_SC1_REG(ADC1,index)
+#define ADC0_R(index)                            ADC_R_REG(ADC0,index)
+#define ADC1_R(index)                            ADC_R_REG(ADC1,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPRA;                              /**< Master Privilege Register A, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PACRA;                             /**< Peripheral Access Control Register, offset: 0x20 */
+  __IO uint32_t PACRB;                             /**< Peripheral Access Control Register, offset: 0x24 */
+  __IO uint32_t PACRC;                             /**< Peripheral Access Control Register, offset: 0x28 */
+  __IO uint32_t PACRD;                             /**< Peripheral Access Control Register, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PACRE;                             /**< Peripheral Access Control Register, offset: 0x40 */
+  __IO uint32_t PACRF;                             /**< Peripheral Access Control Register, offset: 0x44 */
+  __IO uint32_t PACRG;                             /**< Peripheral Access Control Register, offset: 0x48 */
+  __IO uint32_t PACRH;                             /**< Peripheral Access Control Register, offset: 0x4C */
+  __IO uint32_t PACRI;                             /**< Peripheral Access Control Register, offset: 0x50 */
+  __IO uint32_t PACRJ;                             /**< Peripheral Access Control Register, offset: 0x54 */
+  __IO uint32_t PACRK;                             /**< Peripheral Access Control Register, offset: 0x58 */
+  __IO uint32_t PACRL;                             /**< Peripheral Access Control Register, offset: 0x5C */
+  __IO uint32_t PACRM;                             /**< Peripheral Access Control Register, offset: 0x60 */
+  __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
+  __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
+  __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t PACRU;                             /**< Peripheral Access Control Register, offset: 0x80 */
+} AIPS_Type, *AIPS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register accessors */
+#define AIPS_MPRA_REG(base)                      ((base)->MPRA)
+#define AIPS_PACRA_REG(base)                     ((base)->PACRA)
+#define AIPS_PACRB_REG(base)                     ((base)->PACRB)
+#define AIPS_PACRC_REG(base)                     ((base)->PACRC)
+#define AIPS_PACRD_REG(base)                     ((base)->PACRD)
+#define AIPS_PACRE_REG(base)                     ((base)->PACRE)
+#define AIPS_PACRF_REG(base)                     ((base)->PACRF)
+#define AIPS_PACRG_REG(base)                     ((base)->PACRG)
+#define AIPS_PACRH_REG(base)                     ((base)->PACRH)
+#define AIPS_PACRI_REG(base)                     ((base)->PACRI)
+#define AIPS_PACRJ_REG(base)                     ((base)->PACRJ)
+#define AIPS_PACRK_REG(base)                     ((base)->PACRK)
+#define AIPS_PACRL_REG(base)                     ((base)->PACRL)
+#define AIPS_PACRM_REG(base)                     ((base)->PACRM)
+#define AIPS_PACRN_REG(base)                     ((base)->PACRN)
+#define AIPS_PACRO_REG(base)                     ((base)->PACRO)
+#define AIPS_PACRP_REG(base)                     ((base)->PACRP)
+#define AIPS_PACRU_REG(base)                     ((base)->PACRU)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/* MPRA Bit Fields */
+#define AIPS_MPRA_MPL5_MASK                      0x100u
+#define AIPS_MPRA_MPL5_SHIFT                     8
+#define AIPS_MPRA_MPL5_WIDTH                     1
+#define AIPS_MPRA_MPL5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL5_SHIFT))&AIPS_MPRA_MPL5_MASK)
+#define AIPS_MPRA_MTW5_MASK                      0x200u
+#define AIPS_MPRA_MTW5_SHIFT                     9
+#define AIPS_MPRA_MTW5_WIDTH                     1
+#define AIPS_MPRA_MTW5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW5_SHIFT))&AIPS_MPRA_MTW5_MASK)
+#define AIPS_MPRA_MTR5_MASK                      0x400u
+#define AIPS_MPRA_MTR5_SHIFT                     10
+#define AIPS_MPRA_MTR5_WIDTH                     1
+#define AIPS_MPRA_MTR5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR5_SHIFT))&AIPS_MPRA_MTR5_MASK)
+#define AIPS_MPRA_MPL4_MASK                      0x1000u
+#define AIPS_MPRA_MPL4_SHIFT                     12
+#define AIPS_MPRA_MPL4_WIDTH                     1
+#define AIPS_MPRA_MPL4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL4_SHIFT))&AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MTW4_MASK                      0x2000u
+#define AIPS_MPRA_MTW4_SHIFT                     13
+#define AIPS_MPRA_MTW4_WIDTH                     1
+#define AIPS_MPRA_MTW4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW4_SHIFT))&AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTR4_MASK                      0x4000u
+#define AIPS_MPRA_MTR4_SHIFT                     14
+#define AIPS_MPRA_MTR4_WIDTH                     1
+#define AIPS_MPRA_MTR4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR4_SHIFT))&AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MPL3_MASK                      0x10000u
+#define AIPS_MPRA_MPL3_SHIFT                     16
+#define AIPS_MPRA_MPL3_WIDTH                     1
+#define AIPS_MPRA_MPL3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL3_SHIFT))&AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MTW3_MASK                      0x20000u
+#define AIPS_MPRA_MTW3_SHIFT                     17
+#define AIPS_MPRA_MTW3_WIDTH                     1
+#define AIPS_MPRA_MTW3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW3_SHIFT))&AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTR3_MASK                      0x40000u
+#define AIPS_MPRA_MTR3_SHIFT                     18
+#define AIPS_MPRA_MTR3_WIDTH                     1
+#define AIPS_MPRA_MTR3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR3_SHIFT))&AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MPL2_MASK                      0x100000u
+#define AIPS_MPRA_MPL2_SHIFT                     20
+#define AIPS_MPRA_MPL2_WIDTH                     1
+#define AIPS_MPRA_MPL2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL2_SHIFT))&AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MTW2_MASK                      0x200000u
+#define AIPS_MPRA_MTW2_SHIFT                     21
+#define AIPS_MPRA_MTW2_WIDTH                     1
+#define AIPS_MPRA_MTW2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW2_SHIFT))&AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTR2_MASK                      0x400000u
+#define AIPS_MPRA_MTR2_SHIFT                     22
+#define AIPS_MPRA_MTR2_WIDTH                     1
+#define AIPS_MPRA_MTR2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR2_SHIFT))&AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MPL1_MASK                      0x1000000u
+#define AIPS_MPRA_MPL1_SHIFT                     24
+#define AIPS_MPRA_MPL1_WIDTH                     1
+#define AIPS_MPRA_MPL1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL1_SHIFT))&AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MTW1_MASK                      0x2000000u
+#define AIPS_MPRA_MTW1_SHIFT                     25
+#define AIPS_MPRA_MTW1_WIDTH                     1
+#define AIPS_MPRA_MTW1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW1_SHIFT))&AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTR1_MASK                      0x4000000u
+#define AIPS_MPRA_MTR1_SHIFT                     26
+#define AIPS_MPRA_MTR1_WIDTH                     1
+#define AIPS_MPRA_MTR1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR1_SHIFT))&AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MPL0_MASK                      0x10000000u
+#define AIPS_MPRA_MPL0_SHIFT                     28
+#define AIPS_MPRA_MPL0_WIDTH                     1
+#define AIPS_MPRA_MPL0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL0_SHIFT))&AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MTW0_MASK                      0x20000000u
+#define AIPS_MPRA_MTW0_SHIFT                     29
+#define AIPS_MPRA_MTW0_WIDTH                     1
+#define AIPS_MPRA_MTW0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW0_SHIFT))&AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTR0_MASK                      0x40000000u
+#define AIPS_MPRA_MTR0_SHIFT                     30
+#define AIPS_MPRA_MTR0_WIDTH                     1
+#define AIPS_MPRA_MTR0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR0_SHIFT))&AIPS_MPRA_MTR0_MASK)
+/* PACRA Bit Fields */
+#define AIPS_PACRA_TP7_MASK                      0x1u
+#define AIPS_PACRA_TP7_SHIFT                     0
+#define AIPS_PACRA_TP7_WIDTH                     1
+#define AIPS_PACRA_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP7_SHIFT))&AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_WP7_MASK                      0x2u
+#define AIPS_PACRA_WP7_SHIFT                     1
+#define AIPS_PACRA_WP7_WIDTH                     1
+#define AIPS_PACRA_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP7_SHIFT))&AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_SP7_MASK                      0x4u
+#define AIPS_PACRA_SP7_SHIFT                     2
+#define AIPS_PACRA_SP7_WIDTH                     1
+#define AIPS_PACRA_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP7_SHIFT))&AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_TP6_MASK                      0x10u
+#define AIPS_PACRA_TP6_SHIFT                     4
+#define AIPS_PACRA_TP6_WIDTH                     1
+#define AIPS_PACRA_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP6_SHIFT))&AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_WP6_MASK                      0x20u
+#define AIPS_PACRA_WP6_SHIFT                     5
+#define AIPS_PACRA_WP6_WIDTH                     1
+#define AIPS_PACRA_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP6_SHIFT))&AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_SP6_MASK                      0x40u
+#define AIPS_PACRA_SP6_SHIFT                     6
+#define AIPS_PACRA_SP6_WIDTH                     1
+#define AIPS_PACRA_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP6_SHIFT))&AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_TP5_MASK                      0x100u
+#define AIPS_PACRA_TP5_SHIFT                     8
+#define AIPS_PACRA_TP5_WIDTH                     1
+#define AIPS_PACRA_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP5_SHIFT))&AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_WP5_MASK                      0x200u
+#define AIPS_PACRA_WP5_SHIFT                     9
+#define AIPS_PACRA_WP5_WIDTH                     1
+#define AIPS_PACRA_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP5_SHIFT))&AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_SP5_MASK                      0x400u
+#define AIPS_PACRA_SP5_SHIFT                     10
+#define AIPS_PACRA_SP5_WIDTH                     1
+#define AIPS_PACRA_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP5_SHIFT))&AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_TP4_MASK                      0x1000u
+#define AIPS_PACRA_TP4_SHIFT                     12
+#define AIPS_PACRA_TP4_WIDTH                     1
+#define AIPS_PACRA_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP4_SHIFT))&AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_WP4_MASK                      0x2000u
+#define AIPS_PACRA_WP4_SHIFT                     13
+#define AIPS_PACRA_WP4_WIDTH                     1
+#define AIPS_PACRA_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP4_SHIFT))&AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_SP4_MASK                      0x4000u
+#define AIPS_PACRA_SP4_SHIFT                     14
+#define AIPS_PACRA_SP4_WIDTH                     1
+#define AIPS_PACRA_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP4_SHIFT))&AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_TP3_MASK                      0x10000u
+#define AIPS_PACRA_TP3_SHIFT                     16
+#define AIPS_PACRA_TP3_WIDTH                     1
+#define AIPS_PACRA_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP3_SHIFT))&AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_WP3_MASK                      0x20000u
+#define AIPS_PACRA_WP3_SHIFT                     17
+#define AIPS_PACRA_WP3_WIDTH                     1
+#define AIPS_PACRA_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP3_SHIFT))&AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_SP3_MASK                      0x40000u
+#define AIPS_PACRA_SP3_SHIFT                     18
+#define AIPS_PACRA_SP3_WIDTH                     1
+#define AIPS_PACRA_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP3_SHIFT))&AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_TP2_MASK                      0x100000u
+#define AIPS_PACRA_TP2_SHIFT                     20
+#define AIPS_PACRA_TP2_WIDTH                     1
+#define AIPS_PACRA_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP2_SHIFT))&AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_WP2_MASK                      0x200000u
+#define AIPS_PACRA_WP2_SHIFT                     21
+#define AIPS_PACRA_WP2_WIDTH                     1
+#define AIPS_PACRA_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP2_SHIFT))&AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_SP2_MASK                      0x400000u
+#define AIPS_PACRA_SP2_SHIFT                     22
+#define AIPS_PACRA_SP2_WIDTH                     1
+#define AIPS_PACRA_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP2_SHIFT))&AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_TP1_MASK                      0x1000000u
+#define AIPS_PACRA_TP1_SHIFT                     24
+#define AIPS_PACRA_TP1_WIDTH                     1
+#define AIPS_PACRA_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP1_SHIFT))&AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_WP1_MASK                      0x2000000u
+#define AIPS_PACRA_WP1_SHIFT                     25
+#define AIPS_PACRA_WP1_WIDTH                     1
+#define AIPS_PACRA_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP1_SHIFT))&AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_SP1_MASK                      0x4000000u
+#define AIPS_PACRA_SP1_SHIFT                     26
+#define AIPS_PACRA_SP1_WIDTH                     1
+#define AIPS_PACRA_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP1_SHIFT))&AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_TP0_MASK                      0x10000000u
+#define AIPS_PACRA_TP0_SHIFT                     28
+#define AIPS_PACRA_TP0_WIDTH                     1
+#define AIPS_PACRA_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP0_SHIFT))&AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_WP0_MASK                      0x20000000u
+#define AIPS_PACRA_WP0_SHIFT                     29
+#define AIPS_PACRA_WP0_WIDTH                     1
+#define AIPS_PACRA_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP0_SHIFT))&AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_SP0_MASK                      0x40000000u
+#define AIPS_PACRA_SP0_SHIFT                     30
+#define AIPS_PACRA_SP0_WIDTH                     1
+#define AIPS_PACRA_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP0_SHIFT))&AIPS_PACRA_SP0_MASK)
+/* PACRB Bit Fields */
+#define AIPS_PACRB_TP7_MASK                      0x1u
+#define AIPS_PACRB_TP7_SHIFT                     0
+#define AIPS_PACRB_TP7_WIDTH                     1
+#define AIPS_PACRB_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP7_SHIFT))&AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_WP7_MASK                      0x2u
+#define AIPS_PACRB_WP7_SHIFT                     1
+#define AIPS_PACRB_WP7_WIDTH                     1
+#define AIPS_PACRB_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP7_SHIFT))&AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_SP7_MASK                      0x4u
+#define AIPS_PACRB_SP7_SHIFT                     2
+#define AIPS_PACRB_SP7_WIDTH                     1
+#define AIPS_PACRB_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP7_SHIFT))&AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_TP6_MASK                      0x10u
+#define AIPS_PACRB_TP6_SHIFT                     4
+#define AIPS_PACRB_TP6_WIDTH                     1
+#define AIPS_PACRB_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP6_SHIFT))&AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_WP6_MASK                      0x20u
+#define AIPS_PACRB_WP6_SHIFT                     5
+#define AIPS_PACRB_WP6_WIDTH                     1
+#define AIPS_PACRB_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP6_SHIFT))&AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_SP6_MASK                      0x40u
+#define AIPS_PACRB_SP6_SHIFT                     6
+#define AIPS_PACRB_SP6_WIDTH                     1
+#define AIPS_PACRB_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP6_SHIFT))&AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_TP5_MASK                      0x100u
+#define AIPS_PACRB_TP5_SHIFT                     8
+#define AIPS_PACRB_TP5_WIDTH                     1
+#define AIPS_PACRB_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP5_SHIFT))&AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_WP5_MASK                      0x200u
+#define AIPS_PACRB_WP5_SHIFT                     9
+#define AIPS_PACRB_WP5_WIDTH                     1
+#define AIPS_PACRB_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP5_SHIFT))&AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_SP5_MASK                      0x400u
+#define AIPS_PACRB_SP5_SHIFT                     10
+#define AIPS_PACRB_SP5_WIDTH                     1
+#define AIPS_PACRB_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP5_SHIFT))&AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_TP4_MASK                      0x1000u
+#define AIPS_PACRB_TP4_SHIFT                     12
+#define AIPS_PACRB_TP4_WIDTH                     1
+#define AIPS_PACRB_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP4_SHIFT))&AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_WP4_MASK                      0x2000u
+#define AIPS_PACRB_WP4_SHIFT                     13
+#define AIPS_PACRB_WP4_WIDTH                     1
+#define AIPS_PACRB_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP4_SHIFT))&AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_SP4_MASK                      0x4000u
+#define AIPS_PACRB_SP4_SHIFT                     14
+#define AIPS_PACRB_SP4_WIDTH                     1
+#define AIPS_PACRB_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP4_SHIFT))&AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_TP3_MASK                      0x10000u
+#define AIPS_PACRB_TP3_SHIFT                     16
+#define AIPS_PACRB_TP3_WIDTH                     1
+#define AIPS_PACRB_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP3_SHIFT))&AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_WP3_MASK                      0x20000u
+#define AIPS_PACRB_WP3_SHIFT                     17
+#define AIPS_PACRB_WP3_WIDTH                     1
+#define AIPS_PACRB_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP3_SHIFT))&AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_SP3_MASK                      0x40000u
+#define AIPS_PACRB_SP3_SHIFT                     18
+#define AIPS_PACRB_SP3_WIDTH                     1
+#define AIPS_PACRB_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP3_SHIFT))&AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_TP2_MASK                      0x100000u
+#define AIPS_PACRB_TP2_SHIFT                     20
+#define AIPS_PACRB_TP2_WIDTH                     1
+#define AIPS_PACRB_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP2_SHIFT))&AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_WP2_MASK                      0x200000u
+#define AIPS_PACRB_WP2_SHIFT                     21
+#define AIPS_PACRB_WP2_WIDTH                     1
+#define AIPS_PACRB_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP2_SHIFT))&AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_SP2_MASK                      0x400000u
+#define AIPS_PACRB_SP2_SHIFT                     22
+#define AIPS_PACRB_SP2_WIDTH                     1
+#define AIPS_PACRB_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP2_SHIFT))&AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_TP1_MASK                      0x1000000u
+#define AIPS_PACRB_TP1_SHIFT                     24
+#define AIPS_PACRB_TP1_WIDTH                     1
+#define AIPS_PACRB_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP1_SHIFT))&AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_WP1_MASK                      0x2000000u
+#define AIPS_PACRB_WP1_SHIFT                     25
+#define AIPS_PACRB_WP1_WIDTH                     1
+#define AIPS_PACRB_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP1_SHIFT))&AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_SP1_MASK                      0x4000000u
+#define AIPS_PACRB_SP1_SHIFT                     26
+#define AIPS_PACRB_SP1_WIDTH                     1
+#define AIPS_PACRB_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP1_SHIFT))&AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_TP0_MASK                      0x10000000u
+#define AIPS_PACRB_TP0_SHIFT                     28
+#define AIPS_PACRB_TP0_WIDTH                     1
+#define AIPS_PACRB_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP0_SHIFT))&AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_WP0_MASK                      0x20000000u
+#define AIPS_PACRB_WP0_SHIFT                     29
+#define AIPS_PACRB_WP0_WIDTH                     1
+#define AIPS_PACRB_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP0_SHIFT))&AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_SP0_MASK                      0x40000000u
+#define AIPS_PACRB_SP0_SHIFT                     30
+#define AIPS_PACRB_SP0_WIDTH                     1
+#define AIPS_PACRB_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP0_SHIFT))&AIPS_PACRB_SP0_MASK)
+/* PACRC Bit Fields */
+#define AIPS_PACRC_TP7_MASK                      0x1u
+#define AIPS_PACRC_TP7_SHIFT                     0
+#define AIPS_PACRC_TP7_WIDTH                     1
+#define AIPS_PACRC_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP7_SHIFT))&AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_WP7_MASK                      0x2u
+#define AIPS_PACRC_WP7_SHIFT                     1
+#define AIPS_PACRC_WP7_WIDTH                     1
+#define AIPS_PACRC_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP7_SHIFT))&AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_SP7_MASK                      0x4u
+#define AIPS_PACRC_SP7_SHIFT                     2
+#define AIPS_PACRC_SP7_WIDTH                     1
+#define AIPS_PACRC_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP7_SHIFT))&AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_TP6_MASK                      0x10u
+#define AIPS_PACRC_TP6_SHIFT                     4
+#define AIPS_PACRC_TP6_WIDTH                     1
+#define AIPS_PACRC_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP6_SHIFT))&AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_WP6_MASK                      0x20u
+#define AIPS_PACRC_WP6_SHIFT                     5
+#define AIPS_PACRC_WP6_WIDTH                     1
+#define AIPS_PACRC_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP6_SHIFT))&AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_SP6_MASK                      0x40u
+#define AIPS_PACRC_SP6_SHIFT                     6
+#define AIPS_PACRC_SP6_WIDTH                     1
+#define AIPS_PACRC_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP6_SHIFT))&AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_TP5_MASK                      0x100u
+#define AIPS_PACRC_TP5_SHIFT                     8
+#define AIPS_PACRC_TP5_WIDTH                     1
+#define AIPS_PACRC_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP5_SHIFT))&AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_WP5_MASK                      0x200u
+#define AIPS_PACRC_WP5_SHIFT                     9
+#define AIPS_PACRC_WP5_WIDTH                     1
+#define AIPS_PACRC_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP5_SHIFT))&AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_SP5_MASK                      0x400u
+#define AIPS_PACRC_SP5_SHIFT                     10
+#define AIPS_PACRC_SP5_WIDTH                     1
+#define AIPS_PACRC_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP5_SHIFT))&AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_TP4_MASK                      0x1000u
+#define AIPS_PACRC_TP4_SHIFT                     12
+#define AIPS_PACRC_TP4_WIDTH                     1
+#define AIPS_PACRC_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP4_SHIFT))&AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_WP4_MASK                      0x2000u
+#define AIPS_PACRC_WP4_SHIFT                     13
+#define AIPS_PACRC_WP4_WIDTH                     1
+#define AIPS_PACRC_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP4_SHIFT))&AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_SP4_MASK                      0x4000u
+#define AIPS_PACRC_SP4_SHIFT                     14
+#define AIPS_PACRC_SP4_WIDTH                     1
+#define AIPS_PACRC_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP4_SHIFT))&AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_TP3_MASK                      0x10000u
+#define AIPS_PACRC_TP3_SHIFT                     16
+#define AIPS_PACRC_TP3_WIDTH                     1
+#define AIPS_PACRC_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP3_SHIFT))&AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_WP3_MASK                      0x20000u
+#define AIPS_PACRC_WP3_SHIFT                     17
+#define AIPS_PACRC_WP3_WIDTH                     1
+#define AIPS_PACRC_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP3_SHIFT))&AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_SP3_MASK                      0x40000u
+#define AIPS_PACRC_SP3_SHIFT                     18
+#define AIPS_PACRC_SP3_WIDTH                     1
+#define AIPS_PACRC_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP3_SHIFT))&AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_TP2_MASK                      0x100000u
+#define AIPS_PACRC_TP2_SHIFT                     20
+#define AIPS_PACRC_TP2_WIDTH                     1
+#define AIPS_PACRC_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP2_SHIFT))&AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_WP2_MASK                      0x200000u
+#define AIPS_PACRC_WP2_SHIFT                     21
+#define AIPS_PACRC_WP2_WIDTH                     1
+#define AIPS_PACRC_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP2_SHIFT))&AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_SP2_MASK                      0x400000u
+#define AIPS_PACRC_SP2_SHIFT                     22
+#define AIPS_PACRC_SP2_WIDTH                     1
+#define AIPS_PACRC_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP2_SHIFT))&AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_TP1_MASK                      0x1000000u
+#define AIPS_PACRC_TP1_SHIFT                     24
+#define AIPS_PACRC_TP1_WIDTH                     1
+#define AIPS_PACRC_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP1_SHIFT))&AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_WP1_MASK                      0x2000000u
+#define AIPS_PACRC_WP1_SHIFT                     25
+#define AIPS_PACRC_WP1_WIDTH                     1
+#define AIPS_PACRC_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP1_SHIFT))&AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_SP1_MASK                      0x4000000u
+#define AIPS_PACRC_SP1_SHIFT                     26
+#define AIPS_PACRC_SP1_WIDTH                     1
+#define AIPS_PACRC_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP1_SHIFT))&AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_TP0_MASK                      0x10000000u
+#define AIPS_PACRC_TP0_SHIFT                     28
+#define AIPS_PACRC_TP0_WIDTH                     1
+#define AIPS_PACRC_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP0_SHIFT))&AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_WP0_MASK                      0x20000000u
+#define AIPS_PACRC_WP0_SHIFT                     29
+#define AIPS_PACRC_WP0_WIDTH                     1
+#define AIPS_PACRC_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP0_SHIFT))&AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_SP0_MASK                      0x40000000u
+#define AIPS_PACRC_SP0_SHIFT                     30
+#define AIPS_PACRC_SP0_WIDTH                     1
+#define AIPS_PACRC_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP0_SHIFT))&AIPS_PACRC_SP0_MASK)
+/* PACRD Bit Fields */
+#define AIPS_PACRD_TP7_MASK                      0x1u
+#define AIPS_PACRD_TP7_SHIFT                     0
+#define AIPS_PACRD_TP7_WIDTH                     1
+#define AIPS_PACRD_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP7_SHIFT))&AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_WP7_MASK                      0x2u
+#define AIPS_PACRD_WP7_SHIFT                     1
+#define AIPS_PACRD_WP7_WIDTH                     1
+#define AIPS_PACRD_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP7_SHIFT))&AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_SP7_MASK                      0x4u
+#define AIPS_PACRD_SP7_SHIFT                     2
+#define AIPS_PACRD_SP7_WIDTH                     1
+#define AIPS_PACRD_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP7_SHIFT))&AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_TP6_MASK                      0x10u
+#define AIPS_PACRD_TP6_SHIFT                     4
+#define AIPS_PACRD_TP6_WIDTH                     1
+#define AIPS_PACRD_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP6_SHIFT))&AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_WP6_MASK                      0x20u
+#define AIPS_PACRD_WP6_SHIFT                     5
+#define AIPS_PACRD_WP6_WIDTH                     1
+#define AIPS_PACRD_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP6_SHIFT))&AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_SP6_MASK                      0x40u
+#define AIPS_PACRD_SP6_SHIFT                     6
+#define AIPS_PACRD_SP6_WIDTH                     1
+#define AIPS_PACRD_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP6_SHIFT))&AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_TP5_MASK                      0x100u
+#define AIPS_PACRD_TP5_SHIFT                     8
+#define AIPS_PACRD_TP5_WIDTH                     1
+#define AIPS_PACRD_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP5_SHIFT))&AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_WP5_MASK                      0x200u
+#define AIPS_PACRD_WP5_SHIFT                     9
+#define AIPS_PACRD_WP5_WIDTH                     1
+#define AIPS_PACRD_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP5_SHIFT))&AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_SP5_MASK                      0x400u
+#define AIPS_PACRD_SP5_SHIFT                     10
+#define AIPS_PACRD_SP5_WIDTH                     1
+#define AIPS_PACRD_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP5_SHIFT))&AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_TP4_MASK                      0x1000u
+#define AIPS_PACRD_TP4_SHIFT                     12
+#define AIPS_PACRD_TP4_WIDTH                     1
+#define AIPS_PACRD_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP4_SHIFT))&AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_WP4_MASK                      0x2000u
+#define AIPS_PACRD_WP4_SHIFT                     13
+#define AIPS_PACRD_WP4_WIDTH                     1
+#define AIPS_PACRD_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP4_SHIFT))&AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_SP4_MASK                      0x4000u
+#define AIPS_PACRD_SP4_SHIFT                     14
+#define AIPS_PACRD_SP4_WIDTH                     1
+#define AIPS_PACRD_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP4_SHIFT))&AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_TP3_MASK                      0x10000u
+#define AIPS_PACRD_TP3_SHIFT                     16
+#define AIPS_PACRD_TP3_WIDTH                     1
+#define AIPS_PACRD_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP3_SHIFT))&AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_WP3_MASK                      0x20000u
+#define AIPS_PACRD_WP3_SHIFT                     17
+#define AIPS_PACRD_WP3_WIDTH                     1
+#define AIPS_PACRD_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP3_SHIFT))&AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_SP3_MASK                      0x40000u
+#define AIPS_PACRD_SP3_SHIFT                     18
+#define AIPS_PACRD_SP3_WIDTH                     1
+#define AIPS_PACRD_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP3_SHIFT))&AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_TP2_MASK                      0x100000u
+#define AIPS_PACRD_TP2_SHIFT                     20
+#define AIPS_PACRD_TP2_WIDTH                     1
+#define AIPS_PACRD_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP2_SHIFT))&AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_WP2_MASK                      0x200000u
+#define AIPS_PACRD_WP2_SHIFT                     21
+#define AIPS_PACRD_WP2_WIDTH                     1
+#define AIPS_PACRD_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP2_SHIFT))&AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_SP2_MASK                      0x400000u
+#define AIPS_PACRD_SP2_SHIFT                     22
+#define AIPS_PACRD_SP2_WIDTH                     1
+#define AIPS_PACRD_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP2_SHIFT))&AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_TP1_MASK                      0x1000000u
+#define AIPS_PACRD_TP1_SHIFT                     24
+#define AIPS_PACRD_TP1_WIDTH                     1
+#define AIPS_PACRD_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP1_SHIFT))&AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_WP1_MASK                      0x2000000u
+#define AIPS_PACRD_WP1_SHIFT                     25
+#define AIPS_PACRD_WP1_WIDTH                     1
+#define AIPS_PACRD_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP1_SHIFT))&AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_SP1_MASK                      0x4000000u
+#define AIPS_PACRD_SP1_SHIFT                     26
+#define AIPS_PACRD_SP1_WIDTH                     1
+#define AIPS_PACRD_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP1_SHIFT))&AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_TP0_MASK                      0x10000000u
+#define AIPS_PACRD_TP0_SHIFT                     28
+#define AIPS_PACRD_TP0_WIDTH                     1
+#define AIPS_PACRD_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP0_SHIFT))&AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_WP0_MASK                      0x20000000u
+#define AIPS_PACRD_WP0_SHIFT                     29
+#define AIPS_PACRD_WP0_WIDTH                     1
+#define AIPS_PACRD_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP0_SHIFT))&AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_SP0_MASK                      0x40000000u
+#define AIPS_PACRD_SP0_SHIFT                     30
+#define AIPS_PACRD_SP0_WIDTH                     1
+#define AIPS_PACRD_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP0_SHIFT))&AIPS_PACRD_SP0_MASK)
+/* PACRE Bit Fields */
+#define AIPS_PACRE_TP7_MASK                      0x1u
+#define AIPS_PACRE_TP7_SHIFT                     0
+#define AIPS_PACRE_TP7_WIDTH                     1
+#define AIPS_PACRE_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP7_SHIFT))&AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_WP7_MASK                      0x2u
+#define AIPS_PACRE_WP7_SHIFT                     1
+#define AIPS_PACRE_WP7_WIDTH                     1
+#define AIPS_PACRE_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP7_SHIFT))&AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_SP7_MASK                      0x4u
+#define AIPS_PACRE_SP7_SHIFT                     2
+#define AIPS_PACRE_SP7_WIDTH                     1
+#define AIPS_PACRE_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP7_SHIFT))&AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_TP6_MASK                      0x10u
+#define AIPS_PACRE_TP6_SHIFT                     4
+#define AIPS_PACRE_TP6_WIDTH                     1
+#define AIPS_PACRE_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP6_SHIFT))&AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_WP6_MASK                      0x20u
+#define AIPS_PACRE_WP6_SHIFT                     5
+#define AIPS_PACRE_WP6_WIDTH                     1
+#define AIPS_PACRE_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP6_SHIFT))&AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_SP6_MASK                      0x40u
+#define AIPS_PACRE_SP6_SHIFT                     6
+#define AIPS_PACRE_SP6_WIDTH                     1
+#define AIPS_PACRE_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP6_SHIFT))&AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_TP5_MASK                      0x100u
+#define AIPS_PACRE_TP5_SHIFT                     8
+#define AIPS_PACRE_TP5_WIDTH                     1
+#define AIPS_PACRE_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP5_SHIFT))&AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_WP5_MASK                      0x200u
+#define AIPS_PACRE_WP5_SHIFT                     9
+#define AIPS_PACRE_WP5_WIDTH                     1
+#define AIPS_PACRE_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP5_SHIFT))&AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_SP5_MASK                      0x400u
+#define AIPS_PACRE_SP5_SHIFT                     10
+#define AIPS_PACRE_SP5_WIDTH                     1
+#define AIPS_PACRE_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP5_SHIFT))&AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_TP4_MASK                      0x1000u
+#define AIPS_PACRE_TP4_SHIFT                     12
+#define AIPS_PACRE_TP4_WIDTH                     1
+#define AIPS_PACRE_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP4_SHIFT))&AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_WP4_MASK                      0x2000u
+#define AIPS_PACRE_WP4_SHIFT                     13
+#define AIPS_PACRE_WP4_WIDTH                     1
+#define AIPS_PACRE_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP4_SHIFT))&AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_SP4_MASK                      0x4000u
+#define AIPS_PACRE_SP4_SHIFT                     14
+#define AIPS_PACRE_SP4_WIDTH                     1
+#define AIPS_PACRE_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP4_SHIFT))&AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_TP3_MASK                      0x10000u
+#define AIPS_PACRE_TP3_SHIFT                     16
+#define AIPS_PACRE_TP3_WIDTH                     1
+#define AIPS_PACRE_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP3_SHIFT))&AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_WP3_MASK                      0x20000u
+#define AIPS_PACRE_WP3_SHIFT                     17
+#define AIPS_PACRE_WP3_WIDTH                     1
+#define AIPS_PACRE_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP3_SHIFT))&AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_SP3_MASK                      0x40000u
+#define AIPS_PACRE_SP3_SHIFT                     18
+#define AIPS_PACRE_SP3_WIDTH                     1
+#define AIPS_PACRE_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP3_SHIFT))&AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_TP2_MASK                      0x100000u
+#define AIPS_PACRE_TP2_SHIFT                     20
+#define AIPS_PACRE_TP2_WIDTH                     1
+#define AIPS_PACRE_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP2_SHIFT))&AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_WP2_MASK                      0x200000u
+#define AIPS_PACRE_WP2_SHIFT                     21
+#define AIPS_PACRE_WP2_WIDTH                     1
+#define AIPS_PACRE_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP2_SHIFT))&AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_SP2_MASK                      0x400000u
+#define AIPS_PACRE_SP2_SHIFT                     22
+#define AIPS_PACRE_SP2_WIDTH                     1
+#define AIPS_PACRE_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP2_SHIFT))&AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_TP1_MASK                      0x1000000u
+#define AIPS_PACRE_TP1_SHIFT                     24
+#define AIPS_PACRE_TP1_WIDTH                     1
+#define AIPS_PACRE_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP1_SHIFT))&AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_WP1_MASK                      0x2000000u
+#define AIPS_PACRE_WP1_SHIFT                     25
+#define AIPS_PACRE_WP1_WIDTH                     1
+#define AIPS_PACRE_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP1_SHIFT))&AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_SP1_MASK                      0x4000000u
+#define AIPS_PACRE_SP1_SHIFT                     26
+#define AIPS_PACRE_SP1_WIDTH                     1
+#define AIPS_PACRE_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP1_SHIFT))&AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_TP0_MASK                      0x10000000u
+#define AIPS_PACRE_TP0_SHIFT                     28
+#define AIPS_PACRE_TP0_WIDTH                     1
+#define AIPS_PACRE_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP0_SHIFT))&AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_WP0_MASK                      0x20000000u
+#define AIPS_PACRE_WP0_SHIFT                     29
+#define AIPS_PACRE_WP0_WIDTH                     1
+#define AIPS_PACRE_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP0_SHIFT))&AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_SP0_MASK                      0x40000000u
+#define AIPS_PACRE_SP0_SHIFT                     30
+#define AIPS_PACRE_SP0_WIDTH                     1
+#define AIPS_PACRE_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP0_SHIFT))&AIPS_PACRE_SP0_MASK)
+/* PACRF Bit Fields */
+#define AIPS_PACRF_TP7_MASK                      0x1u
+#define AIPS_PACRF_TP7_SHIFT                     0
+#define AIPS_PACRF_TP7_WIDTH                     1
+#define AIPS_PACRF_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP7_SHIFT))&AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_WP7_MASK                      0x2u
+#define AIPS_PACRF_WP7_SHIFT                     1
+#define AIPS_PACRF_WP7_WIDTH                     1
+#define AIPS_PACRF_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP7_SHIFT))&AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_SP7_MASK                      0x4u
+#define AIPS_PACRF_SP7_SHIFT                     2
+#define AIPS_PACRF_SP7_WIDTH                     1
+#define AIPS_PACRF_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP7_SHIFT))&AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_TP6_MASK                      0x10u
+#define AIPS_PACRF_TP6_SHIFT                     4
+#define AIPS_PACRF_TP6_WIDTH                     1
+#define AIPS_PACRF_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP6_SHIFT))&AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_WP6_MASK                      0x20u
+#define AIPS_PACRF_WP6_SHIFT                     5
+#define AIPS_PACRF_WP6_WIDTH                     1
+#define AIPS_PACRF_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP6_SHIFT))&AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_SP6_MASK                      0x40u
+#define AIPS_PACRF_SP6_SHIFT                     6
+#define AIPS_PACRF_SP6_WIDTH                     1
+#define AIPS_PACRF_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP6_SHIFT))&AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_TP5_MASK                      0x100u
+#define AIPS_PACRF_TP5_SHIFT                     8
+#define AIPS_PACRF_TP5_WIDTH                     1
+#define AIPS_PACRF_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP5_SHIFT))&AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_WP5_MASK                      0x200u
+#define AIPS_PACRF_WP5_SHIFT                     9
+#define AIPS_PACRF_WP5_WIDTH                     1
+#define AIPS_PACRF_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP5_SHIFT))&AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_SP5_MASK                      0x400u
+#define AIPS_PACRF_SP5_SHIFT                     10
+#define AIPS_PACRF_SP5_WIDTH                     1
+#define AIPS_PACRF_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP5_SHIFT))&AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_TP4_MASK                      0x1000u
+#define AIPS_PACRF_TP4_SHIFT                     12
+#define AIPS_PACRF_TP4_WIDTH                     1
+#define AIPS_PACRF_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP4_SHIFT))&AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_WP4_MASK                      0x2000u
+#define AIPS_PACRF_WP4_SHIFT                     13
+#define AIPS_PACRF_WP4_WIDTH                     1
+#define AIPS_PACRF_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP4_SHIFT))&AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_SP4_MASK                      0x4000u
+#define AIPS_PACRF_SP4_SHIFT                     14
+#define AIPS_PACRF_SP4_WIDTH                     1
+#define AIPS_PACRF_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP4_SHIFT))&AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_TP3_MASK                      0x10000u
+#define AIPS_PACRF_TP3_SHIFT                     16
+#define AIPS_PACRF_TP3_WIDTH                     1
+#define AIPS_PACRF_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP3_SHIFT))&AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_WP3_MASK                      0x20000u
+#define AIPS_PACRF_WP3_SHIFT                     17
+#define AIPS_PACRF_WP3_WIDTH                     1
+#define AIPS_PACRF_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP3_SHIFT))&AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_SP3_MASK                      0x40000u
+#define AIPS_PACRF_SP3_SHIFT                     18
+#define AIPS_PACRF_SP3_WIDTH                     1
+#define AIPS_PACRF_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP3_SHIFT))&AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_TP2_MASK                      0x100000u
+#define AIPS_PACRF_TP2_SHIFT                     20
+#define AIPS_PACRF_TP2_WIDTH                     1
+#define AIPS_PACRF_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP2_SHIFT))&AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_WP2_MASK                      0x200000u
+#define AIPS_PACRF_WP2_SHIFT                     21
+#define AIPS_PACRF_WP2_WIDTH                     1
+#define AIPS_PACRF_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP2_SHIFT))&AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_SP2_MASK                      0x400000u
+#define AIPS_PACRF_SP2_SHIFT                     22
+#define AIPS_PACRF_SP2_WIDTH                     1
+#define AIPS_PACRF_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP2_SHIFT))&AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_TP1_MASK                      0x1000000u
+#define AIPS_PACRF_TP1_SHIFT                     24
+#define AIPS_PACRF_TP1_WIDTH                     1
+#define AIPS_PACRF_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP1_SHIFT))&AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_WP1_MASK                      0x2000000u
+#define AIPS_PACRF_WP1_SHIFT                     25
+#define AIPS_PACRF_WP1_WIDTH                     1
+#define AIPS_PACRF_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP1_SHIFT))&AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_SP1_MASK                      0x4000000u
+#define AIPS_PACRF_SP1_SHIFT                     26
+#define AIPS_PACRF_SP1_WIDTH                     1
+#define AIPS_PACRF_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP1_SHIFT))&AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_TP0_MASK                      0x10000000u
+#define AIPS_PACRF_TP0_SHIFT                     28
+#define AIPS_PACRF_TP0_WIDTH                     1
+#define AIPS_PACRF_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP0_SHIFT))&AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_WP0_MASK                      0x20000000u
+#define AIPS_PACRF_WP0_SHIFT                     29
+#define AIPS_PACRF_WP0_WIDTH                     1
+#define AIPS_PACRF_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP0_SHIFT))&AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_SP0_MASK                      0x40000000u
+#define AIPS_PACRF_SP0_SHIFT                     30
+#define AIPS_PACRF_SP0_WIDTH                     1
+#define AIPS_PACRF_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP0_SHIFT))&AIPS_PACRF_SP0_MASK)
+/* PACRG Bit Fields */
+#define AIPS_PACRG_TP7_MASK                      0x1u
+#define AIPS_PACRG_TP7_SHIFT                     0
+#define AIPS_PACRG_TP7_WIDTH                     1
+#define AIPS_PACRG_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP7_SHIFT))&AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_WP7_MASK                      0x2u
+#define AIPS_PACRG_WP7_SHIFT                     1
+#define AIPS_PACRG_WP7_WIDTH                     1
+#define AIPS_PACRG_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP7_SHIFT))&AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_SP7_MASK                      0x4u
+#define AIPS_PACRG_SP7_SHIFT                     2
+#define AIPS_PACRG_SP7_WIDTH                     1
+#define AIPS_PACRG_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP7_SHIFT))&AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_TP6_MASK                      0x10u
+#define AIPS_PACRG_TP6_SHIFT                     4
+#define AIPS_PACRG_TP6_WIDTH                     1
+#define AIPS_PACRG_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP6_SHIFT))&AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_WP6_MASK                      0x20u
+#define AIPS_PACRG_WP6_SHIFT                     5
+#define AIPS_PACRG_WP6_WIDTH                     1
+#define AIPS_PACRG_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP6_SHIFT))&AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_SP6_MASK                      0x40u
+#define AIPS_PACRG_SP6_SHIFT                     6
+#define AIPS_PACRG_SP6_WIDTH                     1
+#define AIPS_PACRG_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP6_SHIFT))&AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_TP5_MASK                      0x100u
+#define AIPS_PACRG_TP5_SHIFT                     8
+#define AIPS_PACRG_TP5_WIDTH                     1
+#define AIPS_PACRG_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP5_SHIFT))&AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_WP5_MASK                      0x200u
+#define AIPS_PACRG_WP5_SHIFT                     9
+#define AIPS_PACRG_WP5_WIDTH                     1
+#define AIPS_PACRG_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP5_SHIFT))&AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_SP5_MASK                      0x400u
+#define AIPS_PACRG_SP5_SHIFT                     10
+#define AIPS_PACRG_SP5_WIDTH                     1
+#define AIPS_PACRG_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP5_SHIFT))&AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_TP4_MASK                      0x1000u
+#define AIPS_PACRG_TP4_SHIFT                     12
+#define AIPS_PACRG_TP4_WIDTH                     1
+#define AIPS_PACRG_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP4_SHIFT))&AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_WP4_MASK                      0x2000u
+#define AIPS_PACRG_WP4_SHIFT                     13
+#define AIPS_PACRG_WP4_WIDTH                     1
+#define AIPS_PACRG_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP4_SHIFT))&AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_SP4_MASK                      0x4000u
+#define AIPS_PACRG_SP4_SHIFT                     14
+#define AIPS_PACRG_SP4_WIDTH                     1
+#define AIPS_PACRG_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP4_SHIFT))&AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_TP3_MASK                      0x10000u
+#define AIPS_PACRG_TP3_SHIFT                     16
+#define AIPS_PACRG_TP3_WIDTH                     1
+#define AIPS_PACRG_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP3_SHIFT))&AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_WP3_MASK                      0x20000u
+#define AIPS_PACRG_WP3_SHIFT                     17
+#define AIPS_PACRG_WP3_WIDTH                     1
+#define AIPS_PACRG_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP3_SHIFT))&AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_SP3_MASK                      0x40000u
+#define AIPS_PACRG_SP3_SHIFT                     18
+#define AIPS_PACRG_SP3_WIDTH                     1
+#define AIPS_PACRG_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP3_SHIFT))&AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_TP2_MASK                      0x100000u
+#define AIPS_PACRG_TP2_SHIFT                     20
+#define AIPS_PACRG_TP2_WIDTH                     1
+#define AIPS_PACRG_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP2_SHIFT))&AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_WP2_MASK                      0x200000u
+#define AIPS_PACRG_WP2_SHIFT                     21
+#define AIPS_PACRG_WP2_WIDTH                     1
+#define AIPS_PACRG_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP2_SHIFT))&AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_SP2_MASK                      0x400000u
+#define AIPS_PACRG_SP2_SHIFT                     22
+#define AIPS_PACRG_SP2_WIDTH                     1
+#define AIPS_PACRG_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP2_SHIFT))&AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_TP1_MASK                      0x1000000u
+#define AIPS_PACRG_TP1_SHIFT                     24
+#define AIPS_PACRG_TP1_WIDTH                     1
+#define AIPS_PACRG_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP1_SHIFT))&AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_WP1_MASK                      0x2000000u
+#define AIPS_PACRG_WP1_SHIFT                     25
+#define AIPS_PACRG_WP1_WIDTH                     1
+#define AIPS_PACRG_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP1_SHIFT))&AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_SP1_MASK                      0x4000000u
+#define AIPS_PACRG_SP1_SHIFT                     26
+#define AIPS_PACRG_SP1_WIDTH                     1
+#define AIPS_PACRG_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP1_SHIFT))&AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_TP0_MASK                      0x10000000u
+#define AIPS_PACRG_TP0_SHIFT                     28
+#define AIPS_PACRG_TP0_WIDTH                     1
+#define AIPS_PACRG_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP0_SHIFT))&AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_WP0_MASK                      0x20000000u
+#define AIPS_PACRG_WP0_SHIFT                     29
+#define AIPS_PACRG_WP0_WIDTH                     1
+#define AIPS_PACRG_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP0_SHIFT))&AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_SP0_MASK                      0x40000000u
+#define AIPS_PACRG_SP0_SHIFT                     30
+#define AIPS_PACRG_SP0_WIDTH                     1
+#define AIPS_PACRG_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP0_SHIFT))&AIPS_PACRG_SP0_MASK)
+/* PACRH Bit Fields */
+#define AIPS_PACRH_TP7_MASK                      0x1u
+#define AIPS_PACRH_TP7_SHIFT                     0
+#define AIPS_PACRH_TP7_WIDTH                     1
+#define AIPS_PACRH_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP7_SHIFT))&AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_WP7_MASK                      0x2u
+#define AIPS_PACRH_WP7_SHIFT                     1
+#define AIPS_PACRH_WP7_WIDTH                     1
+#define AIPS_PACRH_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP7_SHIFT))&AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_SP7_MASK                      0x4u
+#define AIPS_PACRH_SP7_SHIFT                     2
+#define AIPS_PACRH_SP7_WIDTH                     1
+#define AIPS_PACRH_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP7_SHIFT))&AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_TP6_MASK                      0x10u
+#define AIPS_PACRH_TP6_SHIFT                     4
+#define AIPS_PACRH_TP6_WIDTH                     1
+#define AIPS_PACRH_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP6_SHIFT))&AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_WP6_MASK                      0x20u
+#define AIPS_PACRH_WP6_SHIFT                     5
+#define AIPS_PACRH_WP6_WIDTH                     1
+#define AIPS_PACRH_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP6_SHIFT))&AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_SP6_MASK                      0x40u
+#define AIPS_PACRH_SP6_SHIFT                     6
+#define AIPS_PACRH_SP6_WIDTH                     1
+#define AIPS_PACRH_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP6_SHIFT))&AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_TP5_MASK                      0x100u
+#define AIPS_PACRH_TP5_SHIFT                     8
+#define AIPS_PACRH_TP5_WIDTH                     1
+#define AIPS_PACRH_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP5_SHIFT))&AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_WP5_MASK                      0x200u
+#define AIPS_PACRH_WP5_SHIFT                     9
+#define AIPS_PACRH_WP5_WIDTH                     1
+#define AIPS_PACRH_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP5_SHIFT))&AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_SP5_MASK                      0x400u
+#define AIPS_PACRH_SP5_SHIFT                     10
+#define AIPS_PACRH_SP5_WIDTH                     1
+#define AIPS_PACRH_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP5_SHIFT))&AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_TP4_MASK                      0x1000u
+#define AIPS_PACRH_TP4_SHIFT                     12
+#define AIPS_PACRH_TP4_WIDTH                     1
+#define AIPS_PACRH_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP4_SHIFT))&AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_WP4_MASK                      0x2000u
+#define AIPS_PACRH_WP4_SHIFT                     13
+#define AIPS_PACRH_WP4_WIDTH                     1
+#define AIPS_PACRH_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP4_SHIFT))&AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_SP4_MASK                      0x4000u
+#define AIPS_PACRH_SP4_SHIFT                     14
+#define AIPS_PACRH_SP4_WIDTH                     1
+#define AIPS_PACRH_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP4_SHIFT))&AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_TP3_MASK                      0x10000u
+#define AIPS_PACRH_TP3_SHIFT                     16
+#define AIPS_PACRH_TP3_WIDTH                     1
+#define AIPS_PACRH_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP3_SHIFT))&AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_WP3_MASK                      0x20000u
+#define AIPS_PACRH_WP3_SHIFT                     17
+#define AIPS_PACRH_WP3_WIDTH                     1
+#define AIPS_PACRH_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP3_SHIFT))&AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_SP3_MASK                      0x40000u
+#define AIPS_PACRH_SP3_SHIFT                     18
+#define AIPS_PACRH_SP3_WIDTH                     1
+#define AIPS_PACRH_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP3_SHIFT))&AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_TP2_MASK                      0x100000u
+#define AIPS_PACRH_TP2_SHIFT                     20
+#define AIPS_PACRH_TP2_WIDTH                     1
+#define AIPS_PACRH_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP2_SHIFT))&AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_WP2_MASK                      0x200000u
+#define AIPS_PACRH_WP2_SHIFT                     21
+#define AIPS_PACRH_WP2_WIDTH                     1
+#define AIPS_PACRH_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP2_SHIFT))&AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_SP2_MASK                      0x400000u
+#define AIPS_PACRH_SP2_SHIFT                     22
+#define AIPS_PACRH_SP2_WIDTH                     1
+#define AIPS_PACRH_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP2_SHIFT))&AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_TP1_MASK                      0x1000000u
+#define AIPS_PACRH_TP1_SHIFT                     24
+#define AIPS_PACRH_TP1_WIDTH                     1
+#define AIPS_PACRH_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP1_SHIFT))&AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_WP1_MASK                      0x2000000u
+#define AIPS_PACRH_WP1_SHIFT                     25
+#define AIPS_PACRH_WP1_WIDTH                     1
+#define AIPS_PACRH_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP1_SHIFT))&AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_SP1_MASK                      0x4000000u
+#define AIPS_PACRH_SP1_SHIFT                     26
+#define AIPS_PACRH_SP1_WIDTH                     1
+#define AIPS_PACRH_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP1_SHIFT))&AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_TP0_MASK                      0x10000000u
+#define AIPS_PACRH_TP0_SHIFT                     28
+#define AIPS_PACRH_TP0_WIDTH                     1
+#define AIPS_PACRH_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP0_SHIFT))&AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_WP0_MASK                      0x20000000u
+#define AIPS_PACRH_WP0_SHIFT                     29
+#define AIPS_PACRH_WP0_WIDTH                     1
+#define AIPS_PACRH_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP0_SHIFT))&AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_SP0_MASK                      0x40000000u
+#define AIPS_PACRH_SP0_SHIFT                     30
+#define AIPS_PACRH_SP0_WIDTH                     1
+#define AIPS_PACRH_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP0_SHIFT))&AIPS_PACRH_SP0_MASK)
+/* PACRI Bit Fields */
+#define AIPS_PACRI_TP7_MASK                      0x1u
+#define AIPS_PACRI_TP7_SHIFT                     0
+#define AIPS_PACRI_TP7_WIDTH                     1
+#define AIPS_PACRI_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP7_SHIFT))&AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_WP7_MASK                      0x2u
+#define AIPS_PACRI_WP7_SHIFT                     1
+#define AIPS_PACRI_WP7_WIDTH                     1
+#define AIPS_PACRI_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP7_SHIFT))&AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_SP7_MASK                      0x4u
+#define AIPS_PACRI_SP7_SHIFT                     2
+#define AIPS_PACRI_SP7_WIDTH                     1
+#define AIPS_PACRI_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP7_SHIFT))&AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_TP6_MASK                      0x10u
+#define AIPS_PACRI_TP6_SHIFT                     4
+#define AIPS_PACRI_TP6_WIDTH                     1
+#define AIPS_PACRI_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP6_SHIFT))&AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_WP6_MASK                      0x20u
+#define AIPS_PACRI_WP6_SHIFT                     5
+#define AIPS_PACRI_WP6_WIDTH                     1
+#define AIPS_PACRI_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP6_SHIFT))&AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_SP6_MASK                      0x40u
+#define AIPS_PACRI_SP6_SHIFT                     6
+#define AIPS_PACRI_SP6_WIDTH                     1
+#define AIPS_PACRI_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP6_SHIFT))&AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_TP5_MASK                      0x100u
+#define AIPS_PACRI_TP5_SHIFT                     8
+#define AIPS_PACRI_TP5_WIDTH                     1
+#define AIPS_PACRI_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP5_SHIFT))&AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_WP5_MASK                      0x200u
+#define AIPS_PACRI_WP5_SHIFT                     9
+#define AIPS_PACRI_WP5_WIDTH                     1
+#define AIPS_PACRI_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP5_SHIFT))&AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_SP5_MASK                      0x400u
+#define AIPS_PACRI_SP5_SHIFT                     10
+#define AIPS_PACRI_SP5_WIDTH                     1
+#define AIPS_PACRI_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP5_SHIFT))&AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_TP4_MASK                      0x1000u
+#define AIPS_PACRI_TP4_SHIFT                     12
+#define AIPS_PACRI_TP4_WIDTH                     1
+#define AIPS_PACRI_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP4_SHIFT))&AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_WP4_MASK                      0x2000u
+#define AIPS_PACRI_WP4_SHIFT                     13
+#define AIPS_PACRI_WP4_WIDTH                     1
+#define AIPS_PACRI_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP4_SHIFT))&AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_SP4_MASK                      0x4000u
+#define AIPS_PACRI_SP4_SHIFT                     14
+#define AIPS_PACRI_SP4_WIDTH                     1
+#define AIPS_PACRI_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP4_SHIFT))&AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_TP3_MASK                      0x10000u
+#define AIPS_PACRI_TP3_SHIFT                     16
+#define AIPS_PACRI_TP3_WIDTH                     1
+#define AIPS_PACRI_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP3_SHIFT))&AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_WP3_MASK                      0x20000u
+#define AIPS_PACRI_WP3_SHIFT                     17
+#define AIPS_PACRI_WP3_WIDTH                     1
+#define AIPS_PACRI_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP3_SHIFT))&AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_SP3_MASK                      0x40000u
+#define AIPS_PACRI_SP3_SHIFT                     18
+#define AIPS_PACRI_SP3_WIDTH                     1
+#define AIPS_PACRI_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP3_SHIFT))&AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_TP2_MASK                      0x100000u
+#define AIPS_PACRI_TP2_SHIFT                     20
+#define AIPS_PACRI_TP2_WIDTH                     1
+#define AIPS_PACRI_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP2_SHIFT))&AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_WP2_MASK                      0x200000u
+#define AIPS_PACRI_WP2_SHIFT                     21
+#define AIPS_PACRI_WP2_WIDTH                     1
+#define AIPS_PACRI_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP2_SHIFT))&AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_SP2_MASK                      0x400000u
+#define AIPS_PACRI_SP2_SHIFT                     22
+#define AIPS_PACRI_SP2_WIDTH                     1
+#define AIPS_PACRI_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP2_SHIFT))&AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_TP1_MASK                      0x1000000u
+#define AIPS_PACRI_TP1_SHIFT                     24
+#define AIPS_PACRI_TP1_WIDTH                     1
+#define AIPS_PACRI_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP1_SHIFT))&AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_WP1_MASK                      0x2000000u
+#define AIPS_PACRI_WP1_SHIFT                     25
+#define AIPS_PACRI_WP1_WIDTH                     1
+#define AIPS_PACRI_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP1_SHIFT))&AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_SP1_MASK                      0x4000000u
+#define AIPS_PACRI_SP1_SHIFT                     26
+#define AIPS_PACRI_SP1_WIDTH                     1
+#define AIPS_PACRI_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP1_SHIFT))&AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_TP0_MASK                      0x10000000u
+#define AIPS_PACRI_TP0_SHIFT                     28
+#define AIPS_PACRI_TP0_WIDTH                     1
+#define AIPS_PACRI_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP0_SHIFT))&AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_WP0_MASK                      0x20000000u
+#define AIPS_PACRI_WP0_SHIFT                     29
+#define AIPS_PACRI_WP0_WIDTH                     1
+#define AIPS_PACRI_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP0_SHIFT))&AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_SP0_MASK                      0x40000000u
+#define AIPS_PACRI_SP0_SHIFT                     30
+#define AIPS_PACRI_SP0_WIDTH                     1
+#define AIPS_PACRI_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP0_SHIFT))&AIPS_PACRI_SP0_MASK)
+/* PACRJ Bit Fields */
+#define AIPS_PACRJ_TP7_MASK                      0x1u
+#define AIPS_PACRJ_TP7_SHIFT                     0
+#define AIPS_PACRJ_TP7_WIDTH                     1
+#define AIPS_PACRJ_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP7_SHIFT))&AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_WP7_MASK                      0x2u
+#define AIPS_PACRJ_WP7_SHIFT                     1
+#define AIPS_PACRJ_WP7_WIDTH                     1
+#define AIPS_PACRJ_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP7_SHIFT))&AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_SP7_MASK                      0x4u
+#define AIPS_PACRJ_SP7_SHIFT                     2
+#define AIPS_PACRJ_SP7_WIDTH                     1
+#define AIPS_PACRJ_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP7_SHIFT))&AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_TP6_MASK                      0x10u
+#define AIPS_PACRJ_TP6_SHIFT                     4
+#define AIPS_PACRJ_TP6_WIDTH                     1
+#define AIPS_PACRJ_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP6_SHIFT))&AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_WP6_MASK                      0x20u
+#define AIPS_PACRJ_WP6_SHIFT                     5
+#define AIPS_PACRJ_WP6_WIDTH                     1
+#define AIPS_PACRJ_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP6_SHIFT))&AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_SP6_MASK                      0x40u
+#define AIPS_PACRJ_SP6_SHIFT                     6
+#define AIPS_PACRJ_SP6_WIDTH                     1
+#define AIPS_PACRJ_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP6_SHIFT))&AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_TP5_MASK                      0x100u
+#define AIPS_PACRJ_TP5_SHIFT                     8
+#define AIPS_PACRJ_TP5_WIDTH                     1
+#define AIPS_PACRJ_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP5_SHIFT))&AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_WP5_MASK                      0x200u
+#define AIPS_PACRJ_WP5_SHIFT                     9
+#define AIPS_PACRJ_WP5_WIDTH                     1
+#define AIPS_PACRJ_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP5_SHIFT))&AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_SP5_MASK                      0x400u
+#define AIPS_PACRJ_SP5_SHIFT                     10
+#define AIPS_PACRJ_SP5_WIDTH                     1
+#define AIPS_PACRJ_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP5_SHIFT))&AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_TP4_MASK                      0x1000u
+#define AIPS_PACRJ_TP4_SHIFT                     12
+#define AIPS_PACRJ_TP4_WIDTH                     1
+#define AIPS_PACRJ_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP4_SHIFT))&AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_WP4_MASK                      0x2000u
+#define AIPS_PACRJ_WP4_SHIFT                     13
+#define AIPS_PACRJ_WP4_WIDTH                     1
+#define AIPS_PACRJ_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP4_SHIFT))&AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_SP4_MASK                      0x4000u
+#define AIPS_PACRJ_SP4_SHIFT                     14
+#define AIPS_PACRJ_SP4_WIDTH                     1
+#define AIPS_PACRJ_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP4_SHIFT))&AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_TP3_MASK                      0x10000u
+#define AIPS_PACRJ_TP3_SHIFT                     16
+#define AIPS_PACRJ_TP3_WIDTH                     1
+#define AIPS_PACRJ_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP3_SHIFT))&AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_WP3_MASK                      0x20000u
+#define AIPS_PACRJ_WP3_SHIFT                     17
+#define AIPS_PACRJ_WP3_WIDTH                     1
+#define AIPS_PACRJ_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP3_SHIFT))&AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_SP3_MASK                      0x40000u
+#define AIPS_PACRJ_SP3_SHIFT                     18
+#define AIPS_PACRJ_SP3_WIDTH                     1
+#define AIPS_PACRJ_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP3_SHIFT))&AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_TP2_MASK                      0x100000u
+#define AIPS_PACRJ_TP2_SHIFT                     20
+#define AIPS_PACRJ_TP2_WIDTH                     1
+#define AIPS_PACRJ_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP2_SHIFT))&AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_WP2_MASK                      0x200000u
+#define AIPS_PACRJ_WP2_SHIFT                     21
+#define AIPS_PACRJ_WP2_WIDTH                     1
+#define AIPS_PACRJ_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP2_SHIFT))&AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_SP2_MASK                      0x400000u
+#define AIPS_PACRJ_SP2_SHIFT                     22
+#define AIPS_PACRJ_SP2_WIDTH                     1
+#define AIPS_PACRJ_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP2_SHIFT))&AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_TP1_MASK                      0x1000000u
+#define AIPS_PACRJ_TP1_SHIFT                     24
+#define AIPS_PACRJ_TP1_WIDTH                     1
+#define AIPS_PACRJ_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP1_SHIFT))&AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_WP1_MASK                      0x2000000u
+#define AIPS_PACRJ_WP1_SHIFT                     25
+#define AIPS_PACRJ_WP1_WIDTH                     1
+#define AIPS_PACRJ_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP1_SHIFT))&AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_SP1_MASK                      0x4000000u
+#define AIPS_PACRJ_SP1_SHIFT                     26
+#define AIPS_PACRJ_SP1_WIDTH                     1
+#define AIPS_PACRJ_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP1_SHIFT))&AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_TP0_MASK                      0x10000000u
+#define AIPS_PACRJ_TP0_SHIFT                     28
+#define AIPS_PACRJ_TP0_WIDTH                     1
+#define AIPS_PACRJ_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP0_SHIFT))&AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_WP0_MASK                      0x20000000u
+#define AIPS_PACRJ_WP0_SHIFT                     29
+#define AIPS_PACRJ_WP0_WIDTH                     1
+#define AIPS_PACRJ_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP0_SHIFT))&AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_SP0_MASK                      0x40000000u
+#define AIPS_PACRJ_SP0_SHIFT                     30
+#define AIPS_PACRJ_SP0_WIDTH                     1
+#define AIPS_PACRJ_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP0_SHIFT))&AIPS_PACRJ_SP0_MASK)
+/* PACRK Bit Fields */
+#define AIPS_PACRK_TP7_MASK                      0x1u
+#define AIPS_PACRK_TP7_SHIFT                     0
+#define AIPS_PACRK_TP7_WIDTH                     1
+#define AIPS_PACRK_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP7_SHIFT))&AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_WP7_MASK                      0x2u
+#define AIPS_PACRK_WP7_SHIFT                     1
+#define AIPS_PACRK_WP7_WIDTH                     1
+#define AIPS_PACRK_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP7_SHIFT))&AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_SP7_MASK                      0x4u
+#define AIPS_PACRK_SP7_SHIFT                     2
+#define AIPS_PACRK_SP7_WIDTH                     1
+#define AIPS_PACRK_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP7_SHIFT))&AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_TP6_MASK                      0x10u
+#define AIPS_PACRK_TP6_SHIFT                     4
+#define AIPS_PACRK_TP6_WIDTH                     1
+#define AIPS_PACRK_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP6_SHIFT))&AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_WP6_MASK                      0x20u
+#define AIPS_PACRK_WP6_SHIFT                     5
+#define AIPS_PACRK_WP6_WIDTH                     1
+#define AIPS_PACRK_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP6_SHIFT))&AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_SP6_MASK                      0x40u
+#define AIPS_PACRK_SP6_SHIFT                     6
+#define AIPS_PACRK_SP6_WIDTH                     1
+#define AIPS_PACRK_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP6_SHIFT))&AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_TP5_MASK                      0x100u
+#define AIPS_PACRK_TP5_SHIFT                     8
+#define AIPS_PACRK_TP5_WIDTH                     1
+#define AIPS_PACRK_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP5_SHIFT))&AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_WP5_MASK                      0x200u
+#define AIPS_PACRK_WP5_SHIFT                     9
+#define AIPS_PACRK_WP5_WIDTH                     1
+#define AIPS_PACRK_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP5_SHIFT))&AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_SP5_MASK                      0x400u
+#define AIPS_PACRK_SP5_SHIFT                     10
+#define AIPS_PACRK_SP5_WIDTH                     1
+#define AIPS_PACRK_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP5_SHIFT))&AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_TP4_MASK                      0x1000u
+#define AIPS_PACRK_TP4_SHIFT                     12
+#define AIPS_PACRK_TP4_WIDTH                     1
+#define AIPS_PACRK_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP4_SHIFT))&AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_WP4_MASK                      0x2000u
+#define AIPS_PACRK_WP4_SHIFT                     13
+#define AIPS_PACRK_WP4_WIDTH                     1
+#define AIPS_PACRK_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP4_SHIFT))&AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_SP4_MASK                      0x4000u
+#define AIPS_PACRK_SP4_SHIFT                     14
+#define AIPS_PACRK_SP4_WIDTH                     1
+#define AIPS_PACRK_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP4_SHIFT))&AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_TP3_MASK                      0x10000u
+#define AIPS_PACRK_TP3_SHIFT                     16
+#define AIPS_PACRK_TP3_WIDTH                     1
+#define AIPS_PACRK_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP3_SHIFT))&AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_WP3_MASK                      0x20000u
+#define AIPS_PACRK_WP3_SHIFT                     17
+#define AIPS_PACRK_WP3_WIDTH                     1
+#define AIPS_PACRK_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP3_SHIFT))&AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_SP3_MASK                      0x40000u
+#define AIPS_PACRK_SP3_SHIFT                     18
+#define AIPS_PACRK_SP3_WIDTH                     1
+#define AIPS_PACRK_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP3_SHIFT))&AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_TP2_MASK                      0x100000u
+#define AIPS_PACRK_TP2_SHIFT                     20
+#define AIPS_PACRK_TP2_WIDTH                     1
+#define AIPS_PACRK_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP2_SHIFT))&AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_WP2_MASK                      0x200000u
+#define AIPS_PACRK_WP2_SHIFT                     21
+#define AIPS_PACRK_WP2_WIDTH                     1
+#define AIPS_PACRK_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP2_SHIFT))&AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_SP2_MASK                      0x400000u
+#define AIPS_PACRK_SP2_SHIFT                     22
+#define AIPS_PACRK_SP2_WIDTH                     1
+#define AIPS_PACRK_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP2_SHIFT))&AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_TP1_MASK                      0x1000000u
+#define AIPS_PACRK_TP1_SHIFT                     24
+#define AIPS_PACRK_TP1_WIDTH                     1
+#define AIPS_PACRK_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP1_SHIFT))&AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_WP1_MASK                      0x2000000u
+#define AIPS_PACRK_WP1_SHIFT                     25
+#define AIPS_PACRK_WP1_WIDTH                     1
+#define AIPS_PACRK_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP1_SHIFT))&AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_SP1_MASK                      0x4000000u
+#define AIPS_PACRK_SP1_SHIFT                     26
+#define AIPS_PACRK_SP1_WIDTH                     1
+#define AIPS_PACRK_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP1_SHIFT))&AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_TP0_MASK                      0x10000000u
+#define AIPS_PACRK_TP0_SHIFT                     28
+#define AIPS_PACRK_TP0_WIDTH                     1
+#define AIPS_PACRK_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP0_SHIFT))&AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_WP0_MASK                      0x20000000u
+#define AIPS_PACRK_WP0_SHIFT                     29
+#define AIPS_PACRK_WP0_WIDTH                     1
+#define AIPS_PACRK_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP0_SHIFT))&AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_SP0_MASK                      0x40000000u
+#define AIPS_PACRK_SP0_SHIFT                     30
+#define AIPS_PACRK_SP0_WIDTH                     1
+#define AIPS_PACRK_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP0_SHIFT))&AIPS_PACRK_SP0_MASK)
+/* PACRL Bit Fields */
+#define AIPS_PACRL_TP7_MASK                      0x1u
+#define AIPS_PACRL_TP7_SHIFT                     0
+#define AIPS_PACRL_TP7_WIDTH                     1
+#define AIPS_PACRL_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP7_SHIFT))&AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_WP7_MASK                      0x2u
+#define AIPS_PACRL_WP7_SHIFT                     1
+#define AIPS_PACRL_WP7_WIDTH                     1
+#define AIPS_PACRL_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP7_SHIFT))&AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_SP7_MASK                      0x4u
+#define AIPS_PACRL_SP7_SHIFT                     2
+#define AIPS_PACRL_SP7_WIDTH                     1
+#define AIPS_PACRL_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP7_SHIFT))&AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_TP6_MASK                      0x10u
+#define AIPS_PACRL_TP6_SHIFT                     4
+#define AIPS_PACRL_TP6_WIDTH                     1
+#define AIPS_PACRL_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP6_SHIFT))&AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_WP6_MASK                      0x20u
+#define AIPS_PACRL_WP6_SHIFT                     5
+#define AIPS_PACRL_WP6_WIDTH                     1
+#define AIPS_PACRL_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP6_SHIFT))&AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_SP6_MASK                      0x40u
+#define AIPS_PACRL_SP6_SHIFT                     6
+#define AIPS_PACRL_SP6_WIDTH                     1
+#define AIPS_PACRL_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP6_SHIFT))&AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_TP5_MASK                      0x100u
+#define AIPS_PACRL_TP5_SHIFT                     8
+#define AIPS_PACRL_TP5_WIDTH                     1
+#define AIPS_PACRL_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP5_SHIFT))&AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_WP5_MASK                      0x200u
+#define AIPS_PACRL_WP5_SHIFT                     9
+#define AIPS_PACRL_WP5_WIDTH                     1
+#define AIPS_PACRL_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP5_SHIFT))&AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_SP5_MASK                      0x400u
+#define AIPS_PACRL_SP5_SHIFT                     10
+#define AIPS_PACRL_SP5_WIDTH                     1
+#define AIPS_PACRL_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP5_SHIFT))&AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_TP4_MASK                      0x1000u
+#define AIPS_PACRL_TP4_SHIFT                     12
+#define AIPS_PACRL_TP4_WIDTH                     1
+#define AIPS_PACRL_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP4_SHIFT))&AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_WP4_MASK                      0x2000u
+#define AIPS_PACRL_WP4_SHIFT                     13
+#define AIPS_PACRL_WP4_WIDTH                     1
+#define AIPS_PACRL_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP4_SHIFT))&AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_SP4_MASK                      0x4000u
+#define AIPS_PACRL_SP4_SHIFT                     14
+#define AIPS_PACRL_SP4_WIDTH                     1
+#define AIPS_PACRL_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP4_SHIFT))&AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_TP3_MASK                      0x10000u
+#define AIPS_PACRL_TP3_SHIFT                     16
+#define AIPS_PACRL_TP3_WIDTH                     1
+#define AIPS_PACRL_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP3_SHIFT))&AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_WP3_MASK                      0x20000u
+#define AIPS_PACRL_WP3_SHIFT                     17
+#define AIPS_PACRL_WP3_WIDTH                     1
+#define AIPS_PACRL_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP3_SHIFT))&AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_SP3_MASK                      0x40000u
+#define AIPS_PACRL_SP3_SHIFT                     18
+#define AIPS_PACRL_SP3_WIDTH                     1
+#define AIPS_PACRL_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP3_SHIFT))&AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_TP2_MASK                      0x100000u
+#define AIPS_PACRL_TP2_SHIFT                     20
+#define AIPS_PACRL_TP2_WIDTH                     1
+#define AIPS_PACRL_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP2_SHIFT))&AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_WP2_MASK                      0x200000u
+#define AIPS_PACRL_WP2_SHIFT                     21
+#define AIPS_PACRL_WP2_WIDTH                     1
+#define AIPS_PACRL_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP2_SHIFT))&AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_SP2_MASK                      0x400000u
+#define AIPS_PACRL_SP2_SHIFT                     22
+#define AIPS_PACRL_SP2_WIDTH                     1
+#define AIPS_PACRL_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP2_SHIFT))&AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_TP1_MASK                      0x1000000u
+#define AIPS_PACRL_TP1_SHIFT                     24
+#define AIPS_PACRL_TP1_WIDTH                     1
+#define AIPS_PACRL_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP1_SHIFT))&AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_WP1_MASK                      0x2000000u
+#define AIPS_PACRL_WP1_SHIFT                     25
+#define AIPS_PACRL_WP1_WIDTH                     1
+#define AIPS_PACRL_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP1_SHIFT))&AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_SP1_MASK                      0x4000000u
+#define AIPS_PACRL_SP1_SHIFT                     26
+#define AIPS_PACRL_SP1_WIDTH                     1
+#define AIPS_PACRL_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP1_SHIFT))&AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_TP0_MASK                      0x10000000u
+#define AIPS_PACRL_TP0_SHIFT                     28
+#define AIPS_PACRL_TP0_WIDTH                     1
+#define AIPS_PACRL_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP0_SHIFT))&AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_WP0_MASK                      0x20000000u
+#define AIPS_PACRL_WP0_SHIFT                     29
+#define AIPS_PACRL_WP0_WIDTH                     1
+#define AIPS_PACRL_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP0_SHIFT))&AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_SP0_MASK                      0x40000000u
+#define AIPS_PACRL_SP0_SHIFT                     30
+#define AIPS_PACRL_SP0_WIDTH                     1
+#define AIPS_PACRL_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP0_SHIFT))&AIPS_PACRL_SP0_MASK)
+/* PACRM Bit Fields */
+#define AIPS_PACRM_TP7_MASK                      0x1u
+#define AIPS_PACRM_TP7_SHIFT                     0
+#define AIPS_PACRM_TP7_WIDTH                     1
+#define AIPS_PACRM_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP7_SHIFT))&AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_WP7_MASK                      0x2u
+#define AIPS_PACRM_WP7_SHIFT                     1
+#define AIPS_PACRM_WP7_WIDTH                     1
+#define AIPS_PACRM_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP7_SHIFT))&AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_SP7_MASK                      0x4u
+#define AIPS_PACRM_SP7_SHIFT                     2
+#define AIPS_PACRM_SP7_WIDTH                     1
+#define AIPS_PACRM_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP7_SHIFT))&AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_TP6_MASK                      0x10u
+#define AIPS_PACRM_TP6_SHIFT                     4
+#define AIPS_PACRM_TP6_WIDTH                     1
+#define AIPS_PACRM_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP6_SHIFT))&AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_WP6_MASK                      0x20u
+#define AIPS_PACRM_WP6_SHIFT                     5
+#define AIPS_PACRM_WP6_WIDTH                     1
+#define AIPS_PACRM_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP6_SHIFT))&AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_SP6_MASK                      0x40u
+#define AIPS_PACRM_SP6_SHIFT                     6
+#define AIPS_PACRM_SP6_WIDTH                     1
+#define AIPS_PACRM_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP6_SHIFT))&AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_TP5_MASK                      0x100u
+#define AIPS_PACRM_TP5_SHIFT                     8
+#define AIPS_PACRM_TP5_WIDTH                     1
+#define AIPS_PACRM_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP5_SHIFT))&AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_WP5_MASK                      0x200u
+#define AIPS_PACRM_WP5_SHIFT                     9
+#define AIPS_PACRM_WP5_WIDTH                     1
+#define AIPS_PACRM_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP5_SHIFT))&AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_SP5_MASK                      0x400u
+#define AIPS_PACRM_SP5_SHIFT                     10
+#define AIPS_PACRM_SP5_WIDTH                     1
+#define AIPS_PACRM_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP5_SHIFT))&AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_TP4_MASK                      0x1000u
+#define AIPS_PACRM_TP4_SHIFT                     12
+#define AIPS_PACRM_TP4_WIDTH                     1
+#define AIPS_PACRM_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP4_SHIFT))&AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_WP4_MASK                      0x2000u
+#define AIPS_PACRM_WP4_SHIFT                     13
+#define AIPS_PACRM_WP4_WIDTH                     1
+#define AIPS_PACRM_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP4_SHIFT))&AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_SP4_MASK                      0x4000u
+#define AIPS_PACRM_SP4_SHIFT                     14
+#define AIPS_PACRM_SP4_WIDTH                     1
+#define AIPS_PACRM_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP4_SHIFT))&AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_TP3_MASK                      0x10000u
+#define AIPS_PACRM_TP3_SHIFT                     16
+#define AIPS_PACRM_TP3_WIDTH                     1
+#define AIPS_PACRM_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP3_SHIFT))&AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_WP3_MASK                      0x20000u
+#define AIPS_PACRM_WP3_SHIFT                     17
+#define AIPS_PACRM_WP3_WIDTH                     1
+#define AIPS_PACRM_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP3_SHIFT))&AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_SP3_MASK                      0x40000u
+#define AIPS_PACRM_SP3_SHIFT                     18
+#define AIPS_PACRM_SP3_WIDTH                     1
+#define AIPS_PACRM_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP3_SHIFT))&AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_TP2_MASK                      0x100000u
+#define AIPS_PACRM_TP2_SHIFT                     20
+#define AIPS_PACRM_TP2_WIDTH                     1
+#define AIPS_PACRM_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP2_SHIFT))&AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_WP2_MASK                      0x200000u
+#define AIPS_PACRM_WP2_SHIFT                     21
+#define AIPS_PACRM_WP2_WIDTH                     1
+#define AIPS_PACRM_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP2_SHIFT))&AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_SP2_MASK                      0x400000u
+#define AIPS_PACRM_SP2_SHIFT                     22
+#define AIPS_PACRM_SP2_WIDTH                     1
+#define AIPS_PACRM_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP2_SHIFT))&AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_TP1_MASK                      0x1000000u
+#define AIPS_PACRM_TP1_SHIFT                     24
+#define AIPS_PACRM_TP1_WIDTH                     1
+#define AIPS_PACRM_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP1_SHIFT))&AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_WP1_MASK                      0x2000000u
+#define AIPS_PACRM_WP1_SHIFT                     25
+#define AIPS_PACRM_WP1_WIDTH                     1
+#define AIPS_PACRM_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP1_SHIFT))&AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_SP1_MASK                      0x4000000u
+#define AIPS_PACRM_SP1_SHIFT                     26
+#define AIPS_PACRM_SP1_WIDTH                     1
+#define AIPS_PACRM_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP1_SHIFT))&AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_TP0_MASK                      0x10000000u
+#define AIPS_PACRM_TP0_SHIFT                     28
+#define AIPS_PACRM_TP0_WIDTH                     1
+#define AIPS_PACRM_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP0_SHIFT))&AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_WP0_MASK                      0x20000000u
+#define AIPS_PACRM_WP0_SHIFT                     29
+#define AIPS_PACRM_WP0_WIDTH                     1
+#define AIPS_PACRM_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP0_SHIFT))&AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_SP0_MASK                      0x40000000u
+#define AIPS_PACRM_SP0_SHIFT                     30
+#define AIPS_PACRM_SP0_WIDTH                     1
+#define AIPS_PACRM_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP0_SHIFT))&AIPS_PACRM_SP0_MASK)
+/* PACRN Bit Fields */
+#define AIPS_PACRN_TP7_MASK                      0x1u
+#define AIPS_PACRN_TP7_SHIFT                     0
+#define AIPS_PACRN_TP7_WIDTH                     1
+#define AIPS_PACRN_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP7_SHIFT))&AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_WP7_MASK                      0x2u
+#define AIPS_PACRN_WP7_SHIFT                     1
+#define AIPS_PACRN_WP7_WIDTH                     1
+#define AIPS_PACRN_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP7_SHIFT))&AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_SP7_MASK                      0x4u
+#define AIPS_PACRN_SP7_SHIFT                     2
+#define AIPS_PACRN_SP7_WIDTH                     1
+#define AIPS_PACRN_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP7_SHIFT))&AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_TP6_MASK                      0x10u
+#define AIPS_PACRN_TP6_SHIFT                     4
+#define AIPS_PACRN_TP6_WIDTH                     1
+#define AIPS_PACRN_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP6_SHIFT))&AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_WP6_MASK                      0x20u
+#define AIPS_PACRN_WP6_SHIFT                     5
+#define AIPS_PACRN_WP6_WIDTH                     1
+#define AIPS_PACRN_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP6_SHIFT))&AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_SP6_MASK                      0x40u
+#define AIPS_PACRN_SP6_SHIFT                     6
+#define AIPS_PACRN_SP6_WIDTH                     1
+#define AIPS_PACRN_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP6_SHIFT))&AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_TP5_MASK                      0x100u
+#define AIPS_PACRN_TP5_SHIFT                     8
+#define AIPS_PACRN_TP5_WIDTH                     1
+#define AIPS_PACRN_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP5_SHIFT))&AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_WP5_MASK                      0x200u
+#define AIPS_PACRN_WP5_SHIFT                     9
+#define AIPS_PACRN_WP5_WIDTH                     1
+#define AIPS_PACRN_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP5_SHIFT))&AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_SP5_MASK                      0x400u
+#define AIPS_PACRN_SP5_SHIFT                     10
+#define AIPS_PACRN_SP5_WIDTH                     1
+#define AIPS_PACRN_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP5_SHIFT))&AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_TP4_MASK                      0x1000u
+#define AIPS_PACRN_TP4_SHIFT                     12
+#define AIPS_PACRN_TP4_WIDTH                     1
+#define AIPS_PACRN_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP4_SHIFT))&AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_WP4_MASK                      0x2000u
+#define AIPS_PACRN_WP4_SHIFT                     13
+#define AIPS_PACRN_WP4_WIDTH                     1
+#define AIPS_PACRN_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP4_SHIFT))&AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_SP4_MASK                      0x4000u
+#define AIPS_PACRN_SP4_SHIFT                     14
+#define AIPS_PACRN_SP4_WIDTH                     1
+#define AIPS_PACRN_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP4_SHIFT))&AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_TP3_MASK                      0x10000u
+#define AIPS_PACRN_TP3_SHIFT                     16
+#define AIPS_PACRN_TP3_WIDTH                     1
+#define AIPS_PACRN_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP3_SHIFT))&AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_WP3_MASK                      0x20000u
+#define AIPS_PACRN_WP3_SHIFT                     17
+#define AIPS_PACRN_WP3_WIDTH                     1
+#define AIPS_PACRN_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP3_SHIFT))&AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_SP3_MASK                      0x40000u
+#define AIPS_PACRN_SP3_SHIFT                     18
+#define AIPS_PACRN_SP3_WIDTH                     1
+#define AIPS_PACRN_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP3_SHIFT))&AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_TP2_MASK                      0x100000u
+#define AIPS_PACRN_TP2_SHIFT                     20
+#define AIPS_PACRN_TP2_WIDTH                     1
+#define AIPS_PACRN_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP2_SHIFT))&AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_WP2_MASK                      0x200000u
+#define AIPS_PACRN_WP2_SHIFT                     21
+#define AIPS_PACRN_WP2_WIDTH                     1
+#define AIPS_PACRN_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP2_SHIFT))&AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_SP2_MASK                      0x400000u
+#define AIPS_PACRN_SP2_SHIFT                     22
+#define AIPS_PACRN_SP2_WIDTH                     1
+#define AIPS_PACRN_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP2_SHIFT))&AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_TP1_MASK                      0x1000000u
+#define AIPS_PACRN_TP1_SHIFT                     24
+#define AIPS_PACRN_TP1_WIDTH                     1
+#define AIPS_PACRN_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP1_SHIFT))&AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_WP1_MASK                      0x2000000u
+#define AIPS_PACRN_WP1_SHIFT                     25
+#define AIPS_PACRN_WP1_WIDTH                     1
+#define AIPS_PACRN_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP1_SHIFT))&AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_SP1_MASK                      0x4000000u
+#define AIPS_PACRN_SP1_SHIFT                     26
+#define AIPS_PACRN_SP1_WIDTH                     1
+#define AIPS_PACRN_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP1_SHIFT))&AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_TP0_MASK                      0x10000000u
+#define AIPS_PACRN_TP0_SHIFT                     28
+#define AIPS_PACRN_TP0_WIDTH                     1
+#define AIPS_PACRN_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP0_SHIFT))&AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_WP0_MASK                      0x20000000u
+#define AIPS_PACRN_WP0_SHIFT                     29
+#define AIPS_PACRN_WP0_WIDTH                     1
+#define AIPS_PACRN_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP0_SHIFT))&AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_SP0_MASK                      0x40000000u
+#define AIPS_PACRN_SP0_SHIFT                     30
+#define AIPS_PACRN_SP0_WIDTH                     1
+#define AIPS_PACRN_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP0_SHIFT))&AIPS_PACRN_SP0_MASK)
+/* PACRO Bit Fields */
+#define AIPS_PACRO_TP7_MASK                      0x1u
+#define AIPS_PACRO_TP7_SHIFT                     0
+#define AIPS_PACRO_TP7_WIDTH                     1
+#define AIPS_PACRO_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP7_SHIFT))&AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_WP7_MASK                      0x2u
+#define AIPS_PACRO_WP7_SHIFT                     1
+#define AIPS_PACRO_WP7_WIDTH                     1
+#define AIPS_PACRO_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP7_SHIFT))&AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_SP7_MASK                      0x4u
+#define AIPS_PACRO_SP7_SHIFT                     2
+#define AIPS_PACRO_SP7_WIDTH                     1
+#define AIPS_PACRO_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP7_SHIFT))&AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_TP6_MASK                      0x10u
+#define AIPS_PACRO_TP6_SHIFT                     4
+#define AIPS_PACRO_TP6_WIDTH                     1
+#define AIPS_PACRO_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP6_SHIFT))&AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_WP6_MASK                      0x20u
+#define AIPS_PACRO_WP6_SHIFT                     5
+#define AIPS_PACRO_WP6_WIDTH                     1
+#define AIPS_PACRO_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP6_SHIFT))&AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_SP6_MASK                      0x40u
+#define AIPS_PACRO_SP6_SHIFT                     6
+#define AIPS_PACRO_SP6_WIDTH                     1
+#define AIPS_PACRO_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP6_SHIFT))&AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_TP5_MASK                      0x100u
+#define AIPS_PACRO_TP5_SHIFT                     8
+#define AIPS_PACRO_TP5_WIDTH                     1
+#define AIPS_PACRO_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP5_SHIFT))&AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_WP5_MASK                      0x200u
+#define AIPS_PACRO_WP5_SHIFT                     9
+#define AIPS_PACRO_WP5_WIDTH                     1
+#define AIPS_PACRO_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP5_SHIFT))&AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_SP5_MASK                      0x400u
+#define AIPS_PACRO_SP5_SHIFT                     10
+#define AIPS_PACRO_SP5_WIDTH                     1
+#define AIPS_PACRO_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP5_SHIFT))&AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_TP4_MASK                      0x1000u
+#define AIPS_PACRO_TP4_SHIFT                     12
+#define AIPS_PACRO_TP4_WIDTH                     1
+#define AIPS_PACRO_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP4_SHIFT))&AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_WP4_MASK                      0x2000u
+#define AIPS_PACRO_WP4_SHIFT                     13
+#define AIPS_PACRO_WP4_WIDTH                     1
+#define AIPS_PACRO_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP4_SHIFT))&AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_SP4_MASK                      0x4000u
+#define AIPS_PACRO_SP4_SHIFT                     14
+#define AIPS_PACRO_SP4_WIDTH                     1
+#define AIPS_PACRO_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP4_SHIFT))&AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_TP3_MASK                      0x10000u
+#define AIPS_PACRO_TP3_SHIFT                     16
+#define AIPS_PACRO_TP3_WIDTH                     1
+#define AIPS_PACRO_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP3_SHIFT))&AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_WP3_MASK                      0x20000u
+#define AIPS_PACRO_WP3_SHIFT                     17
+#define AIPS_PACRO_WP3_WIDTH                     1
+#define AIPS_PACRO_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP3_SHIFT))&AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_SP3_MASK                      0x40000u
+#define AIPS_PACRO_SP3_SHIFT                     18
+#define AIPS_PACRO_SP3_WIDTH                     1
+#define AIPS_PACRO_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP3_SHIFT))&AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_TP2_MASK                      0x100000u
+#define AIPS_PACRO_TP2_SHIFT                     20
+#define AIPS_PACRO_TP2_WIDTH                     1
+#define AIPS_PACRO_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP2_SHIFT))&AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_WP2_MASK                      0x200000u
+#define AIPS_PACRO_WP2_SHIFT                     21
+#define AIPS_PACRO_WP2_WIDTH                     1
+#define AIPS_PACRO_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP2_SHIFT))&AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_SP2_MASK                      0x400000u
+#define AIPS_PACRO_SP2_SHIFT                     22
+#define AIPS_PACRO_SP2_WIDTH                     1
+#define AIPS_PACRO_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP2_SHIFT))&AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_TP1_MASK                      0x1000000u
+#define AIPS_PACRO_TP1_SHIFT                     24
+#define AIPS_PACRO_TP1_WIDTH                     1
+#define AIPS_PACRO_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP1_SHIFT))&AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_WP1_MASK                      0x2000000u
+#define AIPS_PACRO_WP1_SHIFT                     25
+#define AIPS_PACRO_WP1_WIDTH                     1
+#define AIPS_PACRO_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP1_SHIFT))&AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_SP1_MASK                      0x4000000u
+#define AIPS_PACRO_SP1_SHIFT                     26
+#define AIPS_PACRO_SP1_WIDTH                     1
+#define AIPS_PACRO_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP1_SHIFT))&AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_TP0_MASK                      0x10000000u
+#define AIPS_PACRO_TP0_SHIFT                     28
+#define AIPS_PACRO_TP0_WIDTH                     1
+#define AIPS_PACRO_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP0_SHIFT))&AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_WP0_MASK                      0x20000000u
+#define AIPS_PACRO_WP0_SHIFT                     29
+#define AIPS_PACRO_WP0_WIDTH                     1
+#define AIPS_PACRO_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP0_SHIFT))&AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_SP0_MASK                      0x40000000u
+#define AIPS_PACRO_SP0_SHIFT                     30
+#define AIPS_PACRO_SP0_WIDTH                     1
+#define AIPS_PACRO_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP0_SHIFT))&AIPS_PACRO_SP0_MASK)
+/* PACRP Bit Fields */
+#define AIPS_PACRP_TP7_MASK                      0x1u
+#define AIPS_PACRP_TP7_SHIFT                     0
+#define AIPS_PACRP_TP7_WIDTH                     1
+#define AIPS_PACRP_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP7_SHIFT))&AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_WP7_MASK                      0x2u
+#define AIPS_PACRP_WP7_SHIFT                     1
+#define AIPS_PACRP_WP7_WIDTH                     1
+#define AIPS_PACRP_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP7_SHIFT))&AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_SP7_MASK                      0x4u
+#define AIPS_PACRP_SP7_SHIFT                     2
+#define AIPS_PACRP_SP7_WIDTH                     1
+#define AIPS_PACRP_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP7_SHIFT))&AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_TP6_MASK                      0x10u
+#define AIPS_PACRP_TP6_SHIFT                     4
+#define AIPS_PACRP_TP6_WIDTH                     1
+#define AIPS_PACRP_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP6_SHIFT))&AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_WP6_MASK                      0x20u
+#define AIPS_PACRP_WP6_SHIFT                     5
+#define AIPS_PACRP_WP6_WIDTH                     1
+#define AIPS_PACRP_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP6_SHIFT))&AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_SP6_MASK                      0x40u
+#define AIPS_PACRP_SP6_SHIFT                     6
+#define AIPS_PACRP_SP6_WIDTH                     1
+#define AIPS_PACRP_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP6_SHIFT))&AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_TP5_MASK                      0x100u
+#define AIPS_PACRP_TP5_SHIFT                     8
+#define AIPS_PACRP_TP5_WIDTH                     1
+#define AIPS_PACRP_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP5_SHIFT))&AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_WP5_MASK                      0x200u
+#define AIPS_PACRP_WP5_SHIFT                     9
+#define AIPS_PACRP_WP5_WIDTH                     1
+#define AIPS_PACRP_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP5_SHIFT))&AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_SP5_MASK                      0x400u
+#define AIPS_PACRP_SP5_SHIFT                     10
+#define AIPS_PACRP_SP5_WIDTH                     1
+#define AIPS_PACRP_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP5_SHIFT))&AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_TP4_MASK                      0x1000u
+#define AIPS_PACRP_TP4_SHIFT                     12
+#define AIPS_PACRP_TP4_WIDTH                     1
+#define AIPS_PACRP_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP4_SHIFT))&AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_WP4_MASK                      0x2000u
+#define AIPS_PACRP_WP4_SHIFT                     13
+#define AIPS_PACRP_WP4_WIDTH                     1
+#define AIPS_PACRP_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP4_SHIFT))&AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_SP4_MASK                      0x4000u
+#define AIPS_PACRP_SP4_SHIFT                     14
+#define AIPS_PACRP_SP4_WIDTH                     1
+#define AIPS_PACRP_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP4_SHIFT))&AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_TP3_MASK                      0x10000u
+#define AIPS_PACRP_TP3_SHIFT                     16
+#define AIPS_PACRP_TP3_WIDTH                     1
+#define AIPS_PACRP_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP3_SHIFT))&AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_WP3_MASK                      0x20000u
+#define AIPS_PACRP_WP3_SHIFT                     17
+#define AIPS_PACRP_WP3_WIDTH                     1
+#define AIPS_PACRP_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP3_SHIFT))&AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_SP3_MASK                      0x40000u
+#define AIPS_PACRP_SP3_SHIFT                     18
+#define AIPS_PACRP_SP3_WIDTH                     1
+#define AIPS_PACRP_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP3_SHIFT))&AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_TP2_MASK                      0x100000u
+#define AIPS_PACRP_TP2_SHIFT                     20
+#define AIPS_PACRP_TP2_WIDTH                     1
+#define AIPS_PACRP_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP2_SHIFT))&AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_WP2_MASK                      0x200000u
+#define AIPS_PACRP_WP2_SHIFT                     21
+#define AIPS_PACRP_WP2_WIDTH                     1
+#define AIPS_PACRP_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP2_SHIFT))&AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_SP2_MASK                      0x400000u
+#define AIPS_PACRP_SP2_SHIFT                     22
+#define AIPS_PACRP_SP2_WIDTH                     1
+#define AIPS_PACRP_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP2_SHIFT))&AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_TP1_MASK                      0x1000000u
+#define AIPS_PACRP_TP1_SHIFT                     24
+#define AIPS_PACRP_TP1_WIDTH                     1
+#define AIPS_PACRP_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP1_SHIFT))&AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_WP1_MASK                      0x2000000u
+#define AIPS_PACRP_WP1_SHIFT                     25
+#define AIPS_PACRP_WP1_WIDTH                     1
+#define AIPS_PACRP_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP1_SHIFT))&AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_SP1_MASK                      0x4000000u
+#define AIPS_PACRP_SP1_SHIFT                     26
+#define AIPS_PACRP_SP1_WIDTH                     1
+#define AIPS_PACRP_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP1_SHIFT))&AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_TP0_MASK                      0x10000000u
+#define AIPS_PACRP_TP0_SHIFT                     28
+#define AIPS_PACRP_TP0_WIDTH                     1
+#define AIPS_PACRP_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP0_SHIFT))&AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_WP0_MASK                      0x20000000u
+#define AIPS_PACRP_WP0_SHIFT                     29
+#define AIPS_PACRP_WP0_WIDTH                     1
+#define AIPS_PACRP_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP0_SHIFT))&AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_SP0_MASK                      0x40000000u
+#define AIPS_PACRP_SP0_SHIFT                     30
+#define AIPS_PACRP_SP0_WIDTH                     1
+#define AIPS_PACRP_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP0_SHIFT))&AIPS_PACRP_SP0_MASK)
+/* PACRU Bit Fields */
+#define AIPS_PACRU_TP1_MASK                      0x1000000u
+#define AIPS_PACRU_TP1_SHIFT                     24
+#define AIPS_PACRU_TP1_WIDTH                     1
+#define AIPS_PACRU_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_TP1_SHIFT))&AIPS_PACRU_TP1_MASK)
+#define AIPS_PACRU_WP1_MASK                      0x2000000u
+#define AIPS_PACRU_WP1_SHIFT                     25
+#define AIPS_PACRU_WP1_WIDTH                     1
+#define AIPS_PACRU_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_WP1_SHIFT))&AIPS_PACRU_WP1_MASK)
+#define AIPS_PACRU_SP1_MASK                      0x4000000u
+#define AIPS_PACRU_SP1_SHIFT                     26
+#define AIPS_PACRU_SP1_WIDTH                     1
+#define AIPS_PACRU_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_SP1_SHIFT))&AIPS_PACRU_SP1_MASK)
+#define AIPS_PACRU_TP0_MASK                      0x10000000u
+#define AIPS_PACRU_TP0_SHIFT                     28
+#define AIPS_PACRU_TP0_WIDTH                     1
+#define AIPS_PACRU_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_TP0_SHIFT))&AIPS_PACRU_TP0_MASK)
+#define AIPS_PACRU_WP0_MASK                      0x20000000u
+#define AIPS_PACRU_WP0_SHIFT                     29
+#define AIPS_PACRU_WP0_WIDTH                     1
+#define AIPS_PACRU_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_WP0_SHIFT))&AIPS_PACRU_WP0_MASK)
+#define AIPS_PACRU_SP0_MASK                      0x40000000u
+#define AIPS_PACRU_SP0_SHIFT                     30
+#define AIPS_PACRU_SP0_WIDTH                     1
+#define AIPS_PACRU_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_SP0_SHIFT))&AIPS_PACRU_SP0_MASK)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base address */
+#define AIPS0_BASE                               (0x40000000u)
+/** Peripheral AIPS0 base pointer */
+#define AIPS0                                    ((AIPS_Type *)AIPS0_BASE)
+#define AIPS0_BASE_PTR                           (AIPS0)
+/** Peripheral AIPS1 base address */
+#define AIPS1_BASE                               (0x40080000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1                                    ((AIPS_Type *)AIPS1_BASE)
+#define AIPS1_BASE_PTR                           (AIPS1)
+/** Array initializer of AIPS peripheral base addresses */
+#define AIPS_BASE_ADDRS                          { AIPS0_BASE, AIPS1_BASE }
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS                           { AIPS0, AIPS1 }
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register instance definitions */
+/* AIPS0 */
+#define AIPS0_MPRA                               AIPS_MPRA_REG(AIPS0)
+#define AIPS0_PACRA                              AIPS_PACRA_REG(AIPS0)
+#define AIPS0_PACRB                              AIPS_PACRB_REG(AIPS0)
+#define AIPS0_PACRC                              AIPS_PACRC_REG(AIPS0)
+#define AIPS0_PACRD                              AIPS_PACRD_REG(AIPS0)
+#define AIPS0_PACRE                              AIPS_PACRE_REG(AIPS0)
+#define AIPS0_PACRF                              AIPS_PACRF_REG(AIPS0)
+#define AIPS0_PACRG                              AIPS_PACRG_REG(AIPS0)
+#define AIPS0_PACRH                              AIPS_PACRH_REG(AIPS0)
+#define AIPS0_PACRI                              AIPS_PACRI_REG(AIPS0)
+#define AIPS0_PACRJ                              AIPS_PACRJ_REG(AIPS0)
+#define AIPS0_PACRK                              AIPS_PACRK_REG(AIPS0)
+#define AIPS0_PACRL                              AIPS_PACRL_REG(AIPS0)
+#define AIPS0_PACRM                              AIPS_PACRM_REG(AIPS0)
+#define AIPS0_PACRN                              AIPS_PACRN_REG(AIPS0)
+#define AIPS0_PACRO                              AIPS_PACRO_REG(AIPS0)
+#define AIPS0_PACRP                              AIPS_PACRP_REG(AIPS0)
+#define AIPS0_PACRU                              AIPS_PACRU_REG(AIPS0)
+/* AIPS1 */
+#define AIPS1_MPRA                               AIPS_MPRA_REG(AIPS1)
+#define AIPS1_PACRA                              AIPS_PACRA_REG(AIPS1)
+#define AIPS1_PACRB                              AIPS_PACRB_REG(AIPS1)
+#define AIPS1_PACRC                              AIPS_PACRC_REG(AIPS1)
+#define AIPS1_PACRD                              AIPS_PACRD_REG(AIPS1)
+#define AIPS1_PACRE                              AIPS_PACRE_REG(AIPS1)
+#define AIPS1_PACRF                              AIPS_PACRF_REG(AIPS1)
+#define AIPS1_PACRG                              AIPS_PACRG_REG(AIPS1)
+#define AIPS1_PACRH                              AIPS_PACRH_REG(AIPS1)
+#define AIPS1_PACRI                              AIPS_PACRI_REG(AIPS1)
+#define AIPS1_PACRJ                              AIPS_PACRJ_REG(AIPS1)
+#define AIPS1_PACRK                              AIPS_PACRK_REG(AIPS1)
+#define AIPS1_PACRL                              AIPS_PACRL_REG(AIPS1)
+#define AIPS1_PACRM                              AIPS_PACRM_REG(AIPS1)
+#define AIPS1_PACRN                              AIPS_PACRN_REG(AIPS1)
+#define AIPS1_PACRO                              AIPS_PACRO_REG(AIPS1)
+#define AIPS1_PACRP                              AIPS_PACRP_REG(AIPS1)
+#define AIPS1_PACRU                              AIPS_PACRU_REG(AIPS1)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t PRS;                               /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CRS;                               /**< Control Register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_1[236];
+  } SLAVE[5];
+       uint8_t RESERVED_0[768];
+  __IO uint32_t MGPCR0;                            /**< Master General Purpose Control Register, offset: 0x800 */
+       uint8_t RESERVED_1[252];
+  __IO uint32_t MGPCR1;                            /**< Master General Purpose Control Register, offset: 0x900 */
+       uint8_t RESERVED_2[252];
+  __IO uint32_t MGPCR2;                            /**< Master General Purpose Control Register, offset: 0xA00 */
+       uint8_t RESERVED_3[252];
+  __IO uint32_t MGPCR3;                            /**< Master General Purpose Control Register, offset: 0xB00 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t MGPCR4;                            /**< Master General Purpose Control Register, offset: 0xC00 */
+       uint8_t RESERVED_5[252];
+  __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
+} AXBS_Type, *AXBS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register accessors */
+#define AXBS_PRS_REG(base,index)                 ((base)->SLAVE[index].PRS)
+#define AXBS_PRS_COUNT                           5
+#define AXBS_CRS_REG(base,index)                 ((base)->SLAVE[index].CRS)
+#define AXBS_CRS_COUNT                           5
+#define AXBS_MGPCR0_REG(base)                    ((base)->MGPCR0)
+#define AXBS_MGPCR1_REG(base)                    ((base)->MGPCR1)
+#define AXBS_MGPCR2_REG(base)                    ((base)->MGPCR2)
+#define AXBS_MGPCR3_REG(base)                    ((base)->MGPCR3)
+#define AXBS_MGPCR4_REG(base)                    ((base)->MGPCR4)
+#define AXBS_MGPCR5_REG(base)                    ((base)->MGPCR5)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/* PRS Bit Fields */
+#define AXBS_PRS_M0_MASK                         0x7u
+#define AXBS_PRS_M0_SHIFT                        0
+#define AXBS_PRS_M0_WIDTH                        3
+#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK                         0x70u
+#define AXBS_PRS_M1_SHIFT                        4
+#define AXBS_PRS_M1_WIDTH                        3
+#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK                         0x700u
+#define AXBS_PRS_M2_SHIFT                        8
+#define AXBS_PRS_M2_WIDTH                        3
+#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK                         0x7000u
+#define AXBS_PRS_M3_SHIFT                        12
+#define AXBS_PRS_M3_WIDTH                        3
+#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK                         0x70000u
+#define AXBS_PRS_M4_SHIFT                        16
+#define AXBS_PRS_M4_WIDTH                        3
+#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK                         0x700000u
+#define AXBS_PRS_M5_SHIFT                        20
+#define AXBS_PRS_M5_WIDTH                        3
+#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
+/* CRS Bit Fields */
+#define AXBS_CRS_PARK_MASK                       0x7u
+#define AXBS_CRS_PARK_SHIFT                      0
+#define AXBS_CRS_PARK_WIDTH                      3
+#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK                       0x30u
+#define AXBS_CRS_PCTL_SHIFT                      4
+#define AXBS_CRS_PCTL_WIDTH                      2
+#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK                        0x300u
+#define AXBS_CRS_ARB_SHIFT                       8
+#define AXBS_CRS_ARB_WIDTH                       2
+#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK                        0x40000000u
+#define AXBS_CRS_HLP_SHIFT                       30
+#define AXBS_CRS_HLP_WIDTH                       1
+#define AXBS_CRS_HLP(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_HLP_SHIFT))&AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_RO_MASK                         0x80000000u
+#define AXBS_CRS_RO_SHIFT                        31
+#define AXBS_CRS_RO_WIDTH                        1
+#define AXBS_CRS_RO(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_RO_SHIFT))&AXBS_CRS_RO_MASK)
+/* MGPCR0 Bit Fields */
+#define AXBS_MGPCR0_AULB_MASK                    0x7u
+#define AXBS_MGPCR0_AULB_SHIFT                   0
+#define AXBS_MGPCR0_AULB_WIDTH                   3
+#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
+/* MGPCR1 Bit Fields */
+#define AXBS_MGPCR1_AULB_MASK                    0x7u
+#define AXBS_MGPCR1_AULB_SHIFT                   0
+#define AXBS_MGPCR1_AULB_WIDTH                   3
+#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
+/* MGPCR2 Bit Fields */
+#define AXBS_MGPCR2_AULB_MASK                    0x7u
+#define AXBS_MGPCR2_AULB_SHIFT                   0
+#define AXBS_MGPCR2_AULB_WIDTH                   3
+#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
+/* MGPCR3 Bit Fields */
+#define AXBS_MGPCR3_AULB_MASK                    0x7u
+#define AXBS_MGPCR3_AULB_SHIFT                   0
+#define AXBS_MGPCR3_AULB_WIDTH                   3
+#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
+/* MGPCR4 Bit Fields */
+#define AXBS_MGPCR4_AULB_MASK                    0x7u
+#define AXBS_MGPCR4_AULB_SHIFT                   0
+#define AXBS_MGPCR4_AULB_WIDTH                   3
+#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
+/* MGPCR5 Bit Fields */
+#define AXBS_MGPCR5_AULB_MASK                    0x7u
+#define AXBS_MGPCR5_AULB_SHIFT                   0
+#define AXBS_MGPCR5_AULB_WIDTH                   3
+#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS base address */
+#define AXBS_BASE                                (0x40004000u)
+/** Peripheral AXBS base pointer */
+#define AXBS                                     ((AXBS_Type *)AXBS_BASE)
+#define AXBS_BASE_PTR                            (AXBS)
+/** Array initializer of AXBS peripheral base addresses */
+#define AXBS_BASE_ADDRS                          { AXBS_BASE }
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASE_PTRS                           { AXBS }
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register instance definitions */
+/* AXBS */
+#define AXBS_PRS0                                AXBS_PRS_REG(AXBS,0)
+#define AXBS_CRS0                                AXBS_CRS_REG(AXBS,0)
+#define AXBS_PRS1                                AXBS_PRS_REG(AXBS,1)
+#define AXBS_CRS1                                AXBS_CRS_REG(AXBS,1)
+#define AXBS_PRS2                                AXBS_PRS_REG(AXBS,2)
+#define AXBS_CRS2                                AXBS_CRS_REG(AXBS,2)
+#define AXBS_PRS3                                AXBS_PRS_REG(AXBS,3)
+#define AXBS_CRS3                                AXBS_CRS_REG(AXBS,3)
+#define AXBS_PRS4                                AXBS_PRS_REG(AXBS,4)
+#define AXBS_CRS4                                AXBS_CRS_REG(AXBS,4)
+#define AXBS_MGPCR0                              AXBS_MGPCR0_REG(AXBS)
+#define AXBS_MGPCR1                              AXBS_MGPCR1_REG(AXBS)
+#define AXBS_MGPCR2                              AXBS_MGPCR2_REG(AXBS)
+#define AXBS_MGPCR3                              AXBS_MGPCR3_REG(AXBS)
+#define AXBS_MGPCR4                              AXBS_MGPCR4_REG(AXBS)
+#define AXBS_MGPCR5                              AXBS_MGPCR5_REG(AXBS)
+
+/* AXBS - Register array accessors */
+#define AXBS_PRS(index)                          AXBS_PRS_REG(AXBS,index)
+#define AXBS_CRS(index)                          AXBS_CRS_REG(AXBS,index)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
+  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
+  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
+  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
+  __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
+  __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
+  __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
+  __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
+  __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
+       uint8_t RESERVED_4[48];
+  struct {                                         /* offset: 0x80, array step: 0x10 */
+    __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+    __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+    __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+    __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+  } MB[16];
+       uint8_t RESERVED_5[1792];
+  __IO uint32_t RXIMR[16];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_Type, *CAN_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register accessors */
+#define CAN_MCR_REG(base)                        ((base)->MCR)
+#define CAN_CTRL1_REG(base)                      ((base)->CTRL1)
+#define CAN_TIMER_REG(base)                      ((base)->TIMER)
+#define CAN_RXMGMASK_REG(base)                   ((base)->RXMGMASK)
+#define CAN_RX14MASK_REG(base)                   ((base)->RX14MASK)
+#define CAN_RX15MASK_REG(base)                   ((base)->RX15MASK)
+#define CAN_ECR_REG(base)                        ((base)->ECR)
+#define CAN_ESR1_REG(base)                       ((base)->ESR1)
+#define CAN_IMASK1_REG(base)                     ((base)->IMASK1)
+#define CAN_IFLAG1_REG(base)                     ((base)->IFLAG1)
+#define CAN_CTRL2_REG(base)                      ((base)->CTRL2)
+#define CAN_ESR2_REG(base)                       ((base)->ESR2)
+#define CAN_CRCR_REG(base)                       ((base)->CRCR)
+#define CAN_RXFGMASK_REG(base)                   ((base)->RXFGMASK)
+#define CAN_RXFIR_REG(base)                      ((base)->RXFIR)
+#define CAN_CS_REG(base,index)                   ((base)->MB[index].CS)
+#define CAN_CS_COUNT                             16
+#define CAN_ID_REG(base,index)                   ((base)->MB[index].ID)
+#define CAN_ID_COUNT                             16
+#define CAN_WORD0_REG(base,index)                ((base)->MB[index].WORD0)
+#define CAN_WORD0_COUNT                          16
+#define CAN_WORD1_REG(base,index)                ((base)->MB[index].WORD1)
+#define CAN_WORD1_COUNT                          16
+#define CAN_RXIMR_REG(base,index)                ((base)->RXIMR[index])
+#define CAN_RXIMR_COUNT                          16
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define CAN_MCR_MAXMB_MASK                       0x7Fu
+#define CAN_MCR_MAXMB_SHIFT                      0
+#define CAN_MCR_MAXMB_WIDTH                      7
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK                        0x300u
+#define CAN_MCR_IDAM_SHIFT                       8
+#define CAN_MCR_IDAM_WIDTH                       2
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK                         0x1000u
+#define CAN_MCR_AEN_SHIFT                        12
+#define CAN_MCR_AEN_WIDTH                        1
+#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK                     0x2000u
+#define CAN_MCR_LPRIOEN_SHIFT                    13
+#define CAN_MCR_LPRIOEN_WIDTH                    1
+#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_IRMQ_MASK                        0x10000u
+#define CAN_MCR_IRMQ_SHIFT                       16
+#define CAN_MCR_IRMQ_WIDTH                       1
+#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK                      0x20000u
+#define CAN_MCR_SRXDIS_SHIFT                     17
+#define CAN_MCR_SRXDIS_WIDTH                     1
+#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_WAKSRC_MASK                      0x80000u
+#define CAN_MCR_WAKSRC_SHIFT                     19
+#define CAN_MCR_WAKSRC_WIDTH                     1
+#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKSRC_SHIFT))&CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_LPMACK_MASK                      0x100000u
+#define CAN_MCR_LPMACK_SHIFT                     20
+#define CAN_MCR_LPMACK_WIDTH                     1
+#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK                       0x200000u
+#define CAN_MCR_WRNEN_SHIFT                      21
+#define CAN_MCR_WRNEN_WIDTH                      1
+#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SLFWAK_MASK                      0x400000u
+#define CAN_MCR_SLFWAK_SHIFT                     22
+#define CAN_MCR_SLFWAK_WIDTH                     1
+#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SLFWAK_SHIFT))&CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SUPV_MASK                        0x800000u
+#define CAN_MCR_SUPV_SHIFT                       23
+#define CAN_MCR_SUPV_WIDTH                       1
+#define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
+#define CAN_MCR_FRZACK_MASK                      0x1000000u
+#define CAN_MCR_FRZACK_SHIFT                     24
+#define CAN_MCR_FRZACK_WIDTH                     1
+#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK                     0x2000000u
+#define CAN_MCR_SOFTRST_SHIFT                    25
+#define CAN_MCR_SOFTRST_WIDTH                    1
+#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_WAKMSK_MASK                      0x4000000u
+#define CAN_MCR_WAKMSK_SHIFT                     26
+#define CAN_MCR_WAKMSK_WIDTH                     1
+#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKMSK_SHIFT))&CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_NOTRDY_MASK                      0x8000000u
+#define CAN_MCR_NOTRDY_SHIFT                     27
+#define CAN_MCR_NOTRDY_WIDTH                     1
+#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK                        0x10000000u
+#define CAN_MCR_HALT_SHIFT                       28
+#define CAN_MCR_HALT_WIDTH                       1
+#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK                        0x20000000u
+#define CAN_MCR_RFEN_SHIFT                       29
+#define CAN_MCR_RFEN_WIDTH                       1
+#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK                         0x40000000u
+#define CAN_MCR_FRZ_SHIFT                        30
+#define CAN_MCR_FRZ_WIDTH                        1
+#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK                        0x80000000u
+#define CAN_MCR_MDIS_SHIFT                       31
+#define CAN_MCR_MDIS_WIDTH                       1
+#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
+/* CTRL1 Bit Fields */
+#define CAN_CTRL1_PROPSEG_MASK                   0x7u
+#define CAN_CTRL1_PROPSEG_SHIFT                  0
+#define CAN_CTRL1_PROPSEG_WIDTH                  3
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK                       0x8u
+#define CAN_CTRL1_LOM_SHIFT                      3
+#define CAN_CTRL1_LOM_WIDTH                      1
+#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK                      0x10u
+#define CAN_CTRL1_LBUF_SHIFT                     4
+#define CAN_CTRL1_LBUF_WIDTH                     1
+#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK                      0x20u
+#define CAN_CTRL1_TSYN_SHIFT                     5
+#define CAN_CTRL1_TSYN_WIDTH                     1
+#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK                   0x40u
+#define CAN_CTRL1_BOFFREC_SHIFT                  6
+#define CAN_CTRL1_BOFFREC_WIDTH                  1
+#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK                       0x80u
+#define CAN_CTRL1_SMP_SHIFT                      7
+#define CAN_CTRL1_SMP_WIDTH                      1
+#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK                   0x400u
+#define CAN_CTRL1_RWRNMSK_SHIFT                  10
+#define CAN_CTRL1_RWRNMSK_WIDTH                  1
+#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK                   0x800u
+#define CAN_CTRL1_TWRNMSK_SHIFT                  11
+#define CAN_CTRL1_TWRNMSK_WIDTH                  1
+#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK                       0x1000u
+#define CAN_CTRL1_LPB_SHIFT                      12
+#define CAN_CTRL1_LPB_WIDTH                      1
+#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_CLKSRC_MASK                    0x2000u
+#define CAN_CTRL1_CLKSRC_SHIFT                   13
+#define CAN_CTRL1_CLKSRC_WIDTH                   1
+#define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_ERRMSK_MASK                    0x4000u
+#define CAN_CTRL1_ERRMSK_SHIFT                   14
+#define CAN_CTRL1_ERRMSK_WIDTH                   1
+#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK                   0x8000u
+#define CAN_CTRL1_BOFFMSK_SHIFT                  15
+#define CAN_CTRL1_BOFFMSK_WIDTH                  1
+#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK                     0x70000u
+#define CAN_CTRL1_PSEG2_SHIFT                    16
+#define CAN_CTRL1_PSEG2_WIDTH                    3
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK                     0x380000u
+#define CAN_CTRL1_PSEG1_SHIFT                    19
+#define CAN_CTRL1_PSEG1_WIDTH                    3
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK                       0xC00000u
+#define CAN_CTRL1_RJW_SHIFT                      22
+#define CAN_CTRL1_RJW_WIDTH                      2
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
+#define CAN_CTRL1_PRESDIV_SHIFT                  24
+#define CAN_CTRL1_PRESDIV_WIDTH                  8
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
+/* TIMER Bit Fields */
+#define CAN_TIMER_TIMER_MASK                     0xFFFFu
+#define CAN_TIMER_TIMER_SHIFT                    0
+#define CAN_TIMER_TIMER_WIDTH                    16
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
+/* RXMGMASK Bit Fields */
+#define CAN_RXMGMASK_MG_MASK                     0xFFFFFFFFu
+#define CAN_RXMGMASK_MG_SHIFT                    0
+#define CAN_RXMGMASK_MG_WIDTH                    32
+#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
+/* RX14MASK Bit Fields */
+#define CAN_RX14MASK_RX14M_MASK                  0xFFFFFFFFu
+#define CAN_RX14MASK_RX14M_SHIFT                 0
+#define CAN_RX14MASK_RX14M_WIDTH                 32
+#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
+/* RX15MASK Bit Fields */
+#define CAN_RX15MASK_RX15M_MASK                  0xFFFFFFFFu
+#define CAN_RX15MASK_RX15M_SHIFT                 0
+#define CAN_RX15MASK_RX15M_WIDTH                 32
+#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
+/* ECR Bit Fields */
+#define CAN_ECR_TXERRCNT_MASK                    0xFFu
+#define CAN_ECR_TXERRCNT_SHIFT                   0
+#define CAN_ECR_TXERRCNT_WIDTH                   8
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK                    0xFF00u
+#define CAN_ECR_RXERRCNT_SHIFT                   8
+#define CAN_ECR_RXERRCNT_WIDTH                   8
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
+/* ESR1 Bit Fields */
+#define CAN_ESR1_WAKINT_MASK                     0x1u
+#define CAN_ESR1_WAKINT_SHIFT                    0
+#define CAN_ESR1_WAKINT_WIDTH                    1
+#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_WAKINT_SHIFT))&CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_ERRINT_MASK                     0x2u
+#define CAN_ESR1_ERRINT_SHIFT                    1
+#define CAN_ESR1_ERRINT_WIDTH                    1
+#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK                    0x4u
+#define CAN_ESR1_BOFFINT_SHIFT                   2
+#define CAN_ESR1_BOFFINT_WIDTH                   1
+#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK                         0x8u
+#define CAN_ESR1_RX_SHIFT                        3
+#define CAN_ESR1_RX_WIDTH                        1
+#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK                    0x30u
+#define CAN_ESR1_FLTCONF_SHIFT                   4
+#define CAN_ESR1_FLTCONF_WIDTH                   2
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK                         0x40u
+#define CAN_ESR1_TX_SHIFT                        6
+#define CAN_ESR1_TX_WIDTH                        1
+#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK                       0x80u
+#define CAN_ESR1_IDLE_SHIFT                      7
+#define CAN_ESR1_IDLE_WIDTH                      1
+#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK                      0x100u
+#define CAN_ESR1_RXWRN_SHIFT                     8
+#define CAN_ESR1_RXWRN_WIDTH                     1
+#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK                      0x200u
+#define CAN_ESR1_TXWRN_SHIFT                     9
+#define CAN_ESR1_TXWRN_WIDTH                     1
+#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK                     0x400u
+#define CAN_ESR1_STFERR_SHIFT                    10
+#define CAN_ESR1_STFERR_WIDTH                    1
+#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK                     0x800u
+#define CAN_ESR1_FRMERR_SHIFT                    11
+#define CAN_ESR1_FRMERR_WIDTH                    1
+#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK                     0x1000u
+#define CAN_ESR1_CRCERR_SHIFT                    12
+#define CAN_ESR1_CRCERR_WIDTH                    1
+#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK                     0x2000u
+#define CAN_ESR1_ACKERR_SHIFT                    13
+#define CAN_ESR1_ACKERR_WIDTH                    1
+#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK                    0x4000u
+#define CAN_ESR1_BIT0ERR_SHIFT                   14
+#define CAN_ESR1_BIT0ERR_WIDTH                   1
+#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK                    0x8000u
+#define CAN_ESR1_BIT1ERR_SHIFT                   15
+#define CAN_ESR1_BIT1ERR_WIDTH                   1
+#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK                    0x10000u
+#define CAN_ESR1_RWRNINT_SHIFT                   16
+#define CAN_ESR1_RWRNINT_WIDTH                   1
+#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK                    0x20000u
+#define CAN_ESR1_TWRNINT_SHIFT                   17
+#define CAN_ESR1_TWRNINT_WIDTH                   1
+#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK                      0x40000u
+#define CAN_ESR1_SYNCH_SHIFT                     18
+#define CAN_ESR1_SYNCH_WIDTH                     1
+#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
+/* IMASK1 Bit Fields */
+#define CAN_IMASK1_BUFLM_MASK                    0xFFFFFFFFu
+#define CAN_IMASK1_BUFLM_SHIFT                   0
+#define CAN_IMASK1_BUFLM_WIDTH                   32
+#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
+/* IFLAG1 Bit Fields */
+#define CAN_IFLAG1_BUF0I_MASK                    0x1u
+#define CAN_IFLAG1_BUF0I_SHIFT                   0
+#define CAN_IFLAG1_BUF0I_WIDTH                   1
+#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF4TO1I_MASK                 0x1Eu
+#define CAN_IFLAG1_BUF4TO1I_SHIFT                1
+#define CAN_IFLAG1_BUF4TO1I_WIDTH                4
+#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK                    0x20u
+#define CAN_IFLAG1_BUF5I_SHIFT                   5
+#define CAN_IFLAG1_BUF5I_WIDTH                   1
+#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK                    0x40u
+#define CAN_IFLAG1_BUF6I_SHIFT                   6
+#define CAN_IFLAG1_BUF6I_WIDTH                   1
+#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK                    0x80u
+#define CAN_IFLAG1_BUF7I_SHIFT                   7
+#define CAN_IFLAG1_BUF7I_WIDTH                   1
+#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK                0xFFFFFF00u
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               8
+#define CAN_IFLAG1_BUF31TO8I_WIDTH               24
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
+/* CTRL2 Bit Fields */
+#define CAN_CTRL2_EACEN_MASK                     0x10000u
+#define CAN_CTRL2_EACEN_SHIFT                    16
+#define CAN_CTRL2_EACEN_WIDTH                    1
+#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK                       0x20000u
+#define CAN_CTRL2_RRS_SHIFT                      17
+#define CAN_CTRL2_RRS_WIDTH                      1
+#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK                       0x40000u
+#define CAN_CTRL2_MRP_SHIFT                      18
+#define CAN_CTRL2_MRP_WIDTH                      1
+#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK                      0xF80000u
+#define CAN_CTRL2_TASD_SHIFT                     19
+#define CAN_CTRL2_TASD_WIDTH                     5
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK                      0xF000000u
+#define CAN_CTRL2_RFFN_SHIFT                     24
+#define CAN_CTRL2_RFFN_WIDTH                     4
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK                    0x10000000u
+#define CAN_CTRL2_WRMFRZ_SHIFT                   28
+#define CAN_CTRL2_WRMFRZ_WIDTH                   1
+#define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_WRMFRZ_SHIFT))&CAN_CTRL2_WRMFRZ_MASK)
+/* ESR2 Bit Fields */
+#define CAN_ESR2_IMB_MASK                        0x2000u
+#define CAN_ESR2_IMB_SHIFT                       13
+#define CAN_ESR2_IMB_WIDTH                       1
+#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK                        0x4000u
+#define CAN_ESR2_VPS_SHIFT                       14
+#define CAN_ESR2_VPS_WIDTH                       1
+#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK                       0x7F0000u
+#define CAN_ESR2_LPTM_SHIFT                      16
+#define CAN_ESR2_LPTM_WIDTH                      7
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
+/* CRCR Bit Fields */
+#define CAN_CRCR_TXCRC_MASK                      0x7FFFu
+#define CAN_CRCR_TXCRC_SHIFT                     0
+#define CAN_CRCR_TXCRC_WIDTH                     15
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK                      0x7F0000u
+#define CAN_CRCR_MBCRC_SHIFT                     16
+#define CAN_CRCR_MBCRC_WIDTH                     7
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
+/* RXFGMASK Bit Fields */
+#define CAN_RXFGMASK_FGM_MASK                    0xFFFFFFFFu
+#define CAN_RXFGMASK_FGM_SHIFT                   0
+#define CAN_RXFGMASK_FGM_WIDTH                   32
+#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
+/* RXFIR Bit Fields */
+#define CAN_RXFIR_IDHIT_MASK                     0x1FFu
+#define CAN_RXFIR_IDHIT_SHIFT                    0
+#define CAN_RXFIR_IDHIT_WIDTH                    9
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
+/* CS Bit Fields */
+#define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
+#define CAN_CS_TIME_STAMP_SHIFT                  0
+#define CAN_CS_TIME_STAMP_WIDTH                  16
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK                          0xF0000u
+#define CAN_CS_DLC_SHIFT                         16
+#define CAN_CS_DLC_WIDTH                         4
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK                          0x100000u
+#define CAN_CS_RTR_SHIFT                         20
+#define CAN_CS_RTR_WIDTH                         1
+#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_RTR_SHIFT))&CAN_CS_RTR_MASK)
+#define CAN_CS_IDE_MASK                          0x200000u
+#define CAN_CS_IDE_SHIFT                         21
+#define CAN_CS_IDE_WIDTH                         1
+#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_IDE_SHIFT))&CAN_CS_IDE_MASK)
+#define CAN_CS_SRR_MASK                          0x400000u
+#define CAN_CS_SRR_SHIFT                         22
+#define CAN_CS_SRR_WIDTH                         1
+#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_SRR_SHIFT))&CAN_CS_SRR_MASK)
+#define CAN_CS_CODE_MASK                         0xF000000u
+#define CAN_CS_CODE_SHIFT                        24
+#define CAN_CS_CODE_WIDTH                        4
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
+/* ID Bit Fields */
+#define CAN_ID_EXT_MASK                          0x3FFFFu
+#define CAN_ID_EXT_SHIFT                         0
+#define CAN_ID_EXT_WIDTH                         18
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK                          0x1FFC0000u
+#define CAN_ID_STD_SHIFT                         18
+#define CAN_ID_STD_WIDTH                         11
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK                         0xE0000000u
+#define CAN_ID_PRIO_SHIFT                        29
+#define CAN_ID_PRIO_WIDTH                        3
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
+/* WORD0 Bit Fields */
+#define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              0
+#define CAN_WORD0_DATA_BYTE_3_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              8
+#define CAN_WORD0_DATA_BYTE_2_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              16
+#define CAN_WORD0_DATA_BYTE_1_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              24
+#define CAN_WORD0_DATA_BYTE_0_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
+/* WORD1 Bit Fields */
+#define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              0
+#define CAN_WORD1_DATA_BYTE_7_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              8
+#define CAN_WORD1_DATA_BYTE_6_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              16
+#define CAN_WORD1_DATA_BYTE_5_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              24
+#define CAN_WORD1_DATA_BYTE_4_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
+/* RXIMR Bit Fields */
+#define CAN_RXIMR_MI_MASK                        0xFFFFFFFFu
+#define CAN_RXIMR_MI_SHIFT                       0
+#define CAN_RXIMR_MI_WIDTH                       32
+#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+#define CAN0_BASE_PTR                            (CAN0)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS                      { CAN0_Rx_Warning_IRQn }
+#define CAN_Tx_Warning_IRQS                      { CAN0_Tx_Warning_IRQn }
+#define CAN_Wake_Up_IRQS                         { CAN0_Wake_Up_IRQn }
+#define CAN_Error_IRQS                           { CAN0_Error_IRQn }
+#define CAN_Bus_Off_IRQS                         { CAN0_Bus_Off_IRQn }
+#define CAN_ORed_Message_buffer_IRQS             { CAN0_ORed_Message_buffer_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register instance definitions */
+/* CAN0 */
+#define CAN0_MCR                                 CAN_MCR_REG(CAN0)
+#define CAN0_CTRL1                               CAN_CTRL1_REG(CAN0)
+#define CAN0_TIMER                               CAN_TIMER_REG(CAN0)
+#define CAN0_RXMGMASK                            CAN_RXMGMASK_REG(CAN0)
+#define CAN0_RX14MASK                            CAN_RX14MASK_REG(CAN0)
+#define CAN0_RX15MASK                            CAN_RX15MASK_REG(CAN0)
+#define CAN0_ECR                                 CAN_ECR_REG(CAN0)
+#define CAN0_ESR1                                CAN_ESR1_REG(CAN0)
+#define CAN0_IMASK1                              CAN_IMASK1_REG(CAN0)
+#define CAN0_IFLAG1                              CAN_IFLAG1_REG(CAN0)
+#define CAN0_CTRL2                               CAN_CTRL2_REG(CAN0)
+#define CAN0_ESR2                                CAN_ESR2_REG(CAN0)
+#define CAN0_CRCR                                CAN_CRCR_REG(CAN0)
+#define CAN0_RXFGMASK                            CAN_RXFGMASK_REG(CAN0)
+#define CAN0_RXFIR                               CAN_RXFIR_REG(CAN0)
+#define CAN0_CS0                                 CAN_CS_REG(CAN0,0)
+#define CAN0_ID0                                 CAN_ID_REG(CAN0,0)
+#define CAN0_WORD00                              CAN_WORD0_REG(CAN0,0)
+#define CAN0_WORD10                              CAN_WORD1_REG(CAN0,0)
+#define CAN0_CS1                                 CAN_CS_REG(CAN0,1)
+#define CAN0_ID1                                 CAN_ID_REG(CAN0,1)
+#define CAN0_WORD01                              CAN_WORD0_REG(CAN0,1)
+#define CAN0_WORD11                              CAN_WORD1_REG(CAN0,1)
+#define CAN0_CS2                                 CAN_CS_REG(CAN0,2)
+#define CAN0_ID2                                 CAN_ID_REG(CAN0,2)
+#define CAN0_WORD02                              CAN_WORD0_REG(CAN0,2)
+#define CAN0_WORD12                              CAN_WORD1_REG(CAN0,2)
+#define CAN0_CS3                                 CAN_CS_REG(CAN0,3)
+#define CAN0_ID3                                 CAN_ID_REG(CAN0,3)
+#define CAN0_WORD03                              CAN_WORD0_REG(CAN0,3)
+#define CAN0_WORD13                              CAN_WORD1_REG(CAN0,3)
+#define CAN0_CS4                                 CAN_CS_REG(CAN0,4)
+#define CAN0_ID4                                 CAN_ID_REG(CAN0,4)
+#define CAN0_WORD04                              CAN_WORD0_REG(CAN0,4)
+#define CAN0_WORD14                              CAN_WORD1_REG(CAN0,4)
+#define CAN0_CS5                                 CAN_CS_REG(CAN0,5)
+#define CAN0_ID5                                 CAN_ID_REG(CAN0,5)
+#define CAN0_WORD05                              CAN_WORD0_REG(CAN0,5)
+#define CAN0_WORD15                              CAN_WORD1_REG(CAN0,5)
+#define CAN0_CS6                                 CAN_CS_REG(CAN0,6)
+#define CAN0_ID6                                 CAN_ID_REG(CAN0,6)
+#define CAN0_WORD06                              CAN_WORD0_REG(CAN0,6)
+#define CAN0_WORD16                              CAN_WORD1_REG(CAN0,6)
+#define CAN0_CS7                                 CAN_CS_REG(CAN0,7)
+#define CAN0_ID7                                 CAN_ID_REG(CAN0,7)
+#define CAN0_WORD07                              CAN_WORD0_REG(CAN0,7)
+#define CAN0_WORD17                              CAN_WORD1_REG(CAN0,7)
+#define CAN0_CS8                                 CAN_CS_REG(CAN0,8)
+#define CAN0_ID8                                 CAN_ID_REG(CAN0,8)
+#define CAN0_WORD08                              CAN_WORD0_REG(CAN0,8)
+#define CAN0_WORD18                              CAN_WORD1_REG(CAN0,8)
+#define CAN0_CS9                                 CAN_CS_REG(CAN0,9)
+#define CAN0_ID9                                 CAN_ID_REG(CAN0,9)
+#define CAN0_WORD09                              CAN_WORD0_REG(CAN0,9)
+#define CAN0_WORD19                              CAN_WORD1_REG(CAN0,9)
+#define CAN0_CS10                                CAN_CS_REG(CAN0,10)
+#define CAN0_ID10                                CAN_ID_REG(CAN0,10)
+#define CAN0_WORD010                             CAN_WORD0_REG(CAN0,10)
+#define CAN0_WORD110                             CAN_WORD1_REG(CAN0,10)
+#define CAN0_CS11                                CAN_CS_REG(CAN0,11)
+#define CAN0_ID11                                CAN_ID_REG(CAN0,11)
+#define CAN0_WORD011                             CAN_WORD0_REG(CAN0,11)
+#define CAN0_WORD111                             CAN_WORD1_REG(CAN0,11)
+#define CAN0_CS12                                CAN_CS_REG(CAN0,12)
+#define CAN0_ID12                                CAN_ID_REG(CAN0,12)
+#define CAN0_WORD012                             CAN_WORD0_REG(CAN0,12)
+#define CAN0_WORD112                             CAN_WORD1_REG(CAN0,12)
+#define CAN0_CS13                                CAN_CS_REG(CAN0,13)
+#define CAN0_ID13                                CAN_ID_REG(CAN0,13)
+#define CAN0_WORD013                             CAN_WORD0_REG(CAN0,13)
+#define CAN0_WORD113                             CAN_WORD1_REG(CAN0,13)
+#define CAN0_CS14                                CAN_CS_REG(CAN0,14)
+#define CAN0_ID14                                CAN_ID_REG(CAN0,14)
+#define CAN0_WORD014                             CAN_WORD0_REG(CAN0,14)
+#define CAN0_WORD114                             CAN_WORD1_REG(CAN0,14)
+#define CAN0_CS15                                CAN_CS_REG(CAN0,15)
+#define CAN0_ID15                                CAN_ID_REG(CAN0,15)
+#define CAN0_WORD015                             CAN_WORD0_REG(CAN0,15)
+#define CAN0_WORD115                             CAN_WORD1_REG(CAN0,15)
+#define CAN0_RXIMR0                              CAN_RXIMR_REG(CAN0,0)
+#define CAN0_RXIMR1                              CAN_RXIMR_REG(CAN0,1)
+#define CAN0_RXIMR2                              CAN_RXIMR_REG(CAN0,2)
+#define CAN0_RXIMR3                              CAN_RXIMR_REG(CAN0,3)
+#define CAN0_RXIMR4                              CAN_RXIMR_REG(CAN0,4)
+#define CAN0_RXIMR5                              CAN_RXIMR_REG(CAN0,5)
+#define CAN0_RXIMR6                              CAN_RXIMR_REG(CAN0,6)
+#define CAN0_RXIMR7                              CAN_RXIMR_REG(CAN0,7)
+#define CAN0_RXIMR8                              CAN_RXIMR_REG(CAN0,8)
+#define CAN0_RXIMR9                              CAN_RXIMR_REG(CAN0,9)
+#define CAN0_RXIMR10                             CAN_RXIMR_REG(CAN0,10)
+#define CAN0_RXIMR11                             CAN_RXIMR_REG(CAN0,11)
+#define CAN0_RXIMR12                             CAN_RXIMR_REG(CAN0,12)
+#define CAN0_RXIMR13                             CAN_RXIMR_REG(CAN0,13)
+#define CAN0_RXIMR14                             CAN_RXIMR_REG(CAN0,14)
+#define CAN0_RXIMR15                             CAN_RXIMR_REG(CAN0,15)
+
+/* CAN - Register array accessors */
+#define CAN0_CS(index)                           CAN_CS_REG(CAN0,index)
+#define CAN0_ID(index)                           CAN_ID_REG(CAN0,index)
+#define CAN0_WORD0(index)                        CAN_WORD0_REG(CAN0,index)
+#define CAN0_WORD1(index)                        CAN_WORD1_REG(CAN0,index)
+#define CAN0_RXIMR(index)                        CAN_RXIMR_REG(CAN0,index)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+  __O  uint32_t DIRECT[16];                        /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[2048];
+  __O  uint32_t LDR_CASR;                          /**< Status register - Load Register command, offset: 0x840 */
+  __O  uint32_t LDR_CAA;                           /**< Accumulator register - Load Register command, offset: 0x844 */
+  __O  uint32_t LDR_CA[9];                         /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
+       uint8_t RESERVED_1[20];
+  __I  uint32_t STR_CASR;                          /**< Status register - Store Register command, offset: 0x880 */
+  __I  uint32_t STR_CAA;                           /**< Accumulator register - Store Register command, offset: 0x884 */
+  __I  uint32_t STR_CA[9];                         /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
+       uint8_t RESERVED_2[20];
+  __O  uint32_t ADR_CASR;                          /**< Status register - Add Register command, offset: 0x8C0 */
+  __O  uint32_t ADR_CAA;                           /**< Accumulator register - Add to register command, offset: 0x8C4 */
+  __O  uint32_t ADR_CA[9];                         /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
+       uint8_t RESERVED_3[20];
+  __O  uint32_t RADR_CASR;                         /**< Status register - Reverse and Add to Register command, offset: 0x900 */
+  __O  uint32_t RADR_CAA;                          /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
+  __O  uint32_t RADR_CA[9];                        /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
+       uint8_t RESERVED_4[84];
+  __O  uint32_t XOR_CASR;                          /**< Status register - Exclusive Or command, offset: 0x980 */
+  __O  uint32_t XOR_CAA;                           /**< Accumulator register - Exclusive Or command, offset: 0x984 */
+  __O  uint32_t XOR_CA[9];                         /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
+       uint8_t RESERVED_5[20];
+  __O  uint32_t ROTL_CASR;                         /**< Status register - Rotate Left command, offset: 0x9C0 */
+  __O  uint32_t ROTL_CAA;                          /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
+  __O  uint32_t ROTL_CA[9];                        /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
+       uint8_t RESERVED_6[276];
+  __O  uint32_t AESC_CASR;                         /**< Status register - AES Column Operation command, offset: 0xB00 */
+  __O  uint32_t AESC_CAA;                          /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
+  __O  uint32_t AESC_CA[9];                        /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
+       uint8_t RESERVED_7[20];
+  __O  uint32_t AESIC_CASR;                        /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
+  __O  uint32_t AESIC_CAA;                         /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
+  __O  uint32_t AESIC_CA[9];                       /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
+} CAU_Type, *CAU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register accessors */
+#define CAU_DIRECT_REG(base,index)               ((base)->DIRECT[index])
+#define CAU_DIRECT_COUNT                         16
+#define CAU_LDR_CASR_REG(base)                   ((base)->LDR_CASR)
+#define CAU_LDR_CAA_REG(base)                    ((base)->LDR_CAA)
+#define CAU_LDR_CA_REG(base,index)               ((base)->LDR_CA[index])
+#define CAU_LDR_CA_COUNT                         9
+#define CAU_STR_CASR_REG(base)                   ((base)->STR_CASR)
+#define CAU_STR_CAA_REG(base)                    ((base)->STR_CAA)
+#define CAU_STR_CA_REG(base,index)               ((base)->STR_CA[index])
+#define CAU_STR_CA_COUNT                         9
+#define CAU_ADR_CASR_REG(base)                   ((base)->ADR_CASR)
+#define CAU_ADR_CAA_REG(base)                    ((base)->ADR_CAA)
+#define CAU_ADR_CA_REG(base,index)               ((base)->ADR_CA[index])
+#define CAU_ADR_CA_COUNT                         9
+#define CAU_RADR_CASR_REG(base)                  ((base)->RADR_CASR)
+#define CAU_RADR_CAA_REG(base)                   ((base)->RADR_CAA)
+#define CAU_RADR_CA_REG(base,index)              ((base)->RADR_CA[index])
+#define CAU_RADR_CA_COUNT                        9
+#define CAU_XOR_CASR_REG(base)                   ((base)->XOR_CASR)
+#define CAU_XOR_CAA_REG(base)                    ((base)->XOR_CAA)
+#define CAU_XOR_CA_REG(base,index)               ((base)->XOR_CA[index])
+#define CAU_XOR_CA_COUNT                         9
+#define CAU_ROTL_CASR_REG(base)                  ((base)->ROTL_CASR)
+#define CAU_ROTL_CAA_REG(base)                   ((base)->ROTL_CAA)
+#define CAU_ROTL_CA_REG(base,index)              ((base)->ROTL_CA[index])
+#define CAU_ROTL_CA_COUNT                        9
+#define CAU_AESC_CASR_REG(base)                  ((base)->AESC_CASR)
+#define CAU_AESC_CAA_REG(base)                   ((base)->AESC_CAA)
+#define CAU_AESC_CA_REG(base,index)              ((base)->AESC_CA[index])
+#define CAU_AESC_CA_COUNT                        9
+#define CAU_AESIC_CASR_REG(base)                 ((base)->AESIC_CASR)
+#define CAU_AESIC_CAA_REG(base)                  ((base)->AESIC_CAA)
+#define CAU_AESIC_CA_REG(base,index)             ((base)->AESIC_CA[index])
+#define CAU_AESIC_CA_COUNT                       9
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/* DIRECT Bit Fields */
+#define CAU_DIRECT_CAU_DIRECT0_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT0_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT0_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT0(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
+#define CAU_DIRECT_CAU_DIRECT1_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT1_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT1_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT1(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
+#define CAU_DIRECT_CAU_DIRECT2_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT2_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT2_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT2(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
+#define CAU_DIRECT_CAU_DIRECT3_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT3_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT3_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT3(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
+#define CAU_DIRECT_CAU_DIRECT4_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT4_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT4_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT4(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
+#define CAU_DIRECT_CAU_DIRECT5_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT5_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT5_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT5(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
+#define CAU_DIRECT_CAU_DIRECT6_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT6_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT6_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT6(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
+#define CAU_DIRECT_CAU_DIRECT7_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT7_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT7_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT7(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
+#define CAU_DIRECT_CAU_DIRECT8_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT8_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT8_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT8(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
+#define CAU_DIRECT_CAU_DIRECT9_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT9_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT9_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT9(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
+#define CAU_DIRECT_CAU_DIRECT10_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT10_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT10_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT10(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
+#define CAU_DIRECT_CAU_DIRECT11_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT11_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT11_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT11(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
+#define CAU_DIRECT_CAU_DIRECT12_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT12_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT12_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT12(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
+#define CAU_DIRECT_CAU_DIRECT13_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT13_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT13_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT13(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
+#define CAU_DIRECT_CAU_DIRECT14_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT14_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT14_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT14(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
+#define CAU_DIRECT_CAU_DIRECT15_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT15_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT15_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT15(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
+/* LDR_CASR Bit Fields */
+#define CAU_LDR_CASR_IC_MASK                     0x1u
+#define CAU_LDR_CASR_IC_SHIFT                    0
+#define CAU_LDR_CASR_IC_WIDTH                    1
+#define CAU_LDR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_IC_SHIFT))&CAU_LDR_CASR_IC_MASK)
+#define CAU_LDR_CASR_DPE_MASK                    0x2u
+#define CAU_LDR_CASR_DPE_SHIFT                   1
+#define CAU_LDR_CASR_DPE_WIDTH                   1
+#define CAU_LDR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_DPE_SHIFT))&CAU_LDR_CASR_DPE_MASK)
+#define CAU_LDR_CASR_VER_MASK                    0xF0000000u
+#define CAU_LDR_CASR_VER_SHIFT                   28
+#define CAU_LDR_CASR_VER_WIDTH                   4
+#define CAU_LDR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
+/* LDR_CAA Bit Fields */
+#define CAU_LDR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_LDR_CAA_ACC_SHIFT                    0
+#define CAU_LDR_CAA_ACC_WIDTH                    32
+#define CAU_LDR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
+/* LDR_CA Bit Fields */
+#define CAU_LDR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA0_SHIFT                     0
+#define CAU_LDR_CA_CA0_WIDTH                     32
+#define CAU_LDR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
+#define CAU_LDR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA1_SHIFT                     0
+#define CAU_LDR_CA_CA1_WIDTH                     32
+#define CAU_LDR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
+#define CAU_LDR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA2_SHIFT                     0
+#define CAU_LDR_CA_CA2_WIDTH                     32
+#define CAU_LDR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
+#define CAU_LDR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA3_SHIFT                     0
+#define CAU_LDR_CA_CA3_WIDTH                     32
+#define CAU_LDR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
+#define CAU_LDR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA4_SHIFT                     0
+#define CAU_LDR_CA_CA4_WIDTH                     32
+#define CAU_LDR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
+#define CAU_LDR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA5_SHIFT                     0
+#define CAU_LDR_CA_CA5_WIDTH                     32
+#define CAU_LDR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
+#define CAU_LDR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA6_SHIFT                     0
+#define CAU_LDR_CA_CA6_WIDTH                     32
+#define CAU_LDR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
+#define CAU_LDR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA7_SHIFT                     0
+#define CAU_LDR_CA_CA7_WIDTH                     32
+#define CAU_LDR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
+#define CAU_LDR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA8_SHIFT                     0
+#define CAU_LDR_CA_CA8_WIDTH                     32
+#define CAU_LDR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
+/* STR_CASR Bit Fields */
+#define CAU_STR_CASR_IC_MASK                     0x1u
+#define CAU_STR_CASR_IC_SHIFT                    0
+#define CAU_STR_CASR_IC_WIDTH                    1
+#define CAU_STR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_IC_SHIFT))&CAU_STR_CASR_IC_MASK)
+#define CAU_STR_CASR_DPE_MASK                    0x2u
+#define CAU_STR_CASR_DPE_SHIFT                   1
+#define CAU_STR_CASR_DPE_WIDTH                   1
+#define CAU_STR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_DPE_SHIFT))&CAU_STR_CASR_DPE_MASK)
+#define CAU_STR_CASR_VER_MASK                    0xF0000000u
+#define CAU_STR_CASR_VER_SHIFT                   28
+#define CAU_STR_CASR_VER_WIDTH                   4
+#define CAU_STR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
+/* STR_CAA Bit Fields */
+#define CAU_STR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_STR_CAA_ACC_SHIFT                    0
+#define CAU_STR_CAA_ACC_WIDTH                    32
+#define CAU_STR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
+/* STR_CA Bit Fields */
+#define CAU_STR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA0_SHIFT                     0
+#define CAU_STR_CA_CA0_WIDTH                     32
+#define CAU_STR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
+#define CAU_STR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA1_SHIFT                     0
+#define CAU_STR_CA_CA1_WIDTH                     32
+#define CAU_STR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
+#define CAU_STR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA2_SHIFT                     0
+#define CAU_STR_CA_CA2_WIDTH                     32
+#define CAU_STR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
+#define CAU_STR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA3_SHIFT                     0
+#define CAU_STR_CA_CA3_WIDTH                     32
+#define CAU_STR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
+#define CAU_STR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA4_SHIFT                     0
+#define CAU_STR_CA_CA4_WIDTH                     32
+#define CAU_STR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
+#define CAU_STR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA5_SHIFT                     0
+#define CAU_STR_CA_CA5_WIDTH                     32
+#define CAU_STR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
+#define CAU_STR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA6_SHIFT                     0
+#define CAU_STR_CA_CA6_WIDTH                     32
+#define CAU_STR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
+#define CAU_STR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA7_SHIFT                     0
+#define CAU_STR_CA_CA7_WIDTH                     32
+#define CAU_STR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
+#define CAU_STR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA8_SHIFT                     0
+#define CAU_STR_CA_CA8_WIDTH                     32
+#define CAU_STR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
+/* ADR_CASR Bit Fields */
+#define CAU_ADR_CASR_IC_MASK                     0x1u
+#define CAU_ADR_CASR_IC_SHIFT                    0
+#define CAU_ADR_CASR_IC_WIDTH                    1
+#define CAU_ADR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_IC_SHIFT))&CAU_ADR_CASR_IC_MASK)
+#define CAU_ADR_CASR_DPE_MASK                    0x2u
+#define CAU_ADR_CASR_DPE_SHIFT                   1
+#define CAU_ADR_CASR_DPE_WIDTH                   1
+#define CAU_ADR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_DPE_SHIFT))&CAU_ADR_CASR_DPE_MASK)
+#define CAU_ADR_CASR_VER_MASK                    0xF0000000u
+#define CAU_ADR_CASR_VER_SHIFT                   28
+#define CAU_ADR_CASR_VER_WIDTH                   4
+#define CAU_ADR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
+/* ADR_CAA Bit Fields */
+#define CAU_ADR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_ADR_CAA_ACC_SHIFT                    0
+#define CAU_ADR_CAA_ACC_WIDTH                    32
+#define CAU_ADR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
+/* ADR_CA Bit Fields */
+#define CAU_ADR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA0_SHIFT                     0
+#define CAU_ADR_CA_CA0_WIDTH                     32
+#define CAU_ADR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
+#define CAU_ADR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA1_SHIFT                     0
+#define CAU_ADR_CA_CA1_WIDTH                     32
+#define CAU_ADR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
+#define CAU_ADR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA2_SHIFT                     0
+#define CAU_ADR_CA_CA2_WIDTH                     32
+#define CAU_ADR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
+#define CAU_ADR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA3_SHIFT                     0
+#define CAU_ADR_CA_CA3_WIDTH                     32
+#define CAU_ADR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
+#define CAU_ADR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA4_SHIFT                     0
+#define CAU_ADR_CA_CA4_WIDTH                     32
+#define CAU_ADR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
+#define CAU_ADR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA5_SHIFT                     0
+#define CAU_ADR_CA_CA5_WIDTH                     32
+#define CAU_ADR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
+#define CAU_ADR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA6_SHIFT                     0
+#define CAU_ADR_CA_CA6_WIDTH                     32
+#define CAU_ADR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
+#define CAU_ADR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA7_SHIFT                     0
+#define CAU_ADR_CA_CA7_WIDTH                     32
+#define CAU_ADR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
+#define CAU_ADR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA8_SHIFT                     0
+#define CAU_ADR_CA_CA8_WIDTH                     32
+#define CAU_ADR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
+/* RADR_CASR Bit Fields */
+#define CAU_RADR_CASR_IC_MASK                    0x1u
+#define CAU_RADR_CASR_IC_SHIFT                   0
+#define CAU_RADR_CASR_IC_WIDTH                   1
+#define CAU_RADR_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_IC_SHIFT))&CAU_RADR_CASR_IC_MASK)
+#define CAU_RADR_CASR_DPE_MASK                   0x2u
+#define CAU_RADR_CASR_DPE_SHIFT                  1
+#define CAU_RADR_CASR_DPE_WIDTH                  1
+#define CAU_RADR_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_DPE_SHIFT))&CAU_RADR_CASR_DPE_MASK)
+#define CAU_RADR_CASR_VER_MASK                   0xF0000000u
+#define CAU_RADR_CASR_VER_SHIFT                  28
+#define CAU_RADR_CASR_VER_WIDTH                  4
+#define CAU_RADR_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
+/* RADR_CAA Bit Fields */
+#define CAU_RADR_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_RADR_CAA_ACC_SHIFT                   0
+#define CAU_RADR_CAA_ACC_WIDTH                   32
+#define CAU_RADR_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
+/* RADR_CA Bit Fields */
+#define CAU_RADR_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA0_SHIFT                    0
+#define CAU_RADR_CA_CA0_WIDTH                    32
+#define CAU_RADR_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
+#define CAU_RADR_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA1_SHIFT                    0
+#define CAU_RADR_CA_CA1_WIDTH                    32
+#define CAU_RADR_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
+#define CAU_RADR_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA2_SHIFT                    0
+#define CAU_RADR_CA_CA2_WIDTH                    32
+#define CAU_RADR_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
+#define CAU_RADR_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA3_SHIFT                    0
+#define CAU_RADR_CA_CA3_WIDTH                    32
+#define CAU_RADR_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
+#define CAU_RADR_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA4_SHIFT                    0
+#define CAU_RADR_CA_CA4_WIDTH                    32
+#define CAU_RADR_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
+#define CAU_RADR_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA5_SHIFT                    0
+#define CAU_RADR_CA_CA5_WIDTH                    32
+#define CAU_RADR_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
+#define CAU_RADR_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA6_SHIFT                    0
+#define CAU_RADR_CA_CA6_WIDTH                    32
+#define CAU_RADR_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
+#define CAU_RADR_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA7_SHIFT                    0
+#define CAU_RADR_CA_CA7_WIDTH                    32
+#define CAU_RADR_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
+#define CAU_RADR_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA8_SHIFT                    0
+#define CAU_RADR_CA_CA8_WIDTH                    32
+#define CAU_RADR_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
+/* XOR_CASR Bit Fields */
+#define CAU_XOR_CASR_IC_MASK                     0x1u
+#define CAU_XOR_CASR_IC_SHIFT                    0
+#define CAU_XOR_CASR_IC_WIDTH                    1
+#define CAU_XOR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_IC_SHIFT))&CAU_XOR_CASR_IC_MASK)
+#define CAU_XOR_CASR_DPE_MASK                    0x2u
+#define CAU_XOR_CASR_DPE_SHIFT                   1
+#define CAU_XOR_CASR_DPE_WIDTH                   1
+#define CAU_XOR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_DPE_SHIFT))&CAU_XOR_CASR_DPE_MASK)
+#define CAU_XOR_CASR_VER_MASK                    0xF0000000u
+#define CAU_XOR_CASR_VER_SHIFT                   28
+#define CAU_XOR_CASR_VER_WIDTH                   4
+#define CAU_XOR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
+/* XOR_CAA Bit Fields */
+#define CAU_XOR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_XOR_CAA_ACC_SHIFT                    0
+#define CAU_XOR_CAA_ACC_WIDTH                    32
+#define CAU_XOR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
+/* XOR_CA Bit Fields */
+#define CAU_XOR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA0_SHIFT                     0
+#define CAU_XOR_CA_CA0_WIDTH                     32
+#define CAU_XOR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
+#define CAU_XOR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA1_SHIFT                     0
+#define CAU_XOR_CA_CA1_WIDTH                     32
+#define CAU_XOR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
+#define CAU_XOR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA2_SHIFT                     0
+#define CAU_XOR_CA_CA2_WIDTH                     32
+#define CAU_XOR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
+#define CAU_XOR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA3_SHIFT                     0
+#define CAU_XOR_CA_CA3_WIDTH                     32
+#define CAU_XOR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
+#define CAU_XOR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA4_SHIFT                     0
+#define CAU_XOR_CA_CA4_WIDTH                     32
+#define CAU_XOR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
+#define CAU_XOR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA5_SHIFT                     0
+#define CAU_XOR_CA_CA5_WIDTH                     32
+#define CAU_XOR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
+#define CAU_XOR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA6_SHIFT                     0
+#define CAU_XOR_CA_CA6_WIDTH                     32
+#define CAU_XOR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
+#define CAU_XOR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA7_SHIFT                     0
+#define CAU_XOR_CA_CA7_WIDTH                     32
+#define CAU_XOR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
+#define CAU_XOR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA8_SHIFT                     0
+#define CAU_XOR_CA_CA8_WIDTH                     32
+#define CAU_XOR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
+/* ROTL_CASR Bit Fields */
+#define CAU_ROTL_CASR_IC_MASK                    0x1u
+#define CAU_ROTL_CASR_IC_SHIFT                   0
+#define CAU_ROTL_CASR_IC_WIDTH                   1
+#define CAU_ROTL_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_IC_SHIFT))&CAU_ROTL_CASR_IC_MASK)
+#define CAU_ROTL_CASR_DPE_MASK                   0x2u
+#define CAU_ROTL_CASR_DPE_SHIFT                  1
+#define CAU_ROTL_CASR_DPE_WIDTH                  1
+#define CAU_ROTL_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_DPE_SHIFT))&CAU_ROTL_CASR_DPE_MASK)
+#define CAU_ROTL_CASR_VER_MASK                   0xF0000000u
+#define CAU_ROTL_CASR_VER_SHIFT                  28
+#define CAU_ROTL_CASR_VER_WIDTH                  4
+#define CAU_ROTL_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
+/* ROTL_CAA Bit Fields */
+#define CAU_ROTL_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_ROTL_CAA_ACC_SHIFT                   0
+#define CAU_ROTL_CAA_ACC_WIDTH                   32
+#define CAU_ROTL_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
+/* ROTL_CA Bit Fields */
+#define CAU_ROTL_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA0_SHIFT                    0
+#define CAU_ROTL_CA_CA0_WIDTH                    32
+#define CAU_ROTL_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
+#define CAU_ROTL_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA1_SHIFT                    0
+#define CAU_ROTL_CA_CA1_WIDTH                    32
+#define CAU_ROTL_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
+#define CAU_ROTL_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA2_SHIFT                    0
+#define CAU_ROTL_CA_CA2_WIDTH                    32
+#define CAU_ROTL_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
+#define CAU_ROTL_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA3_SHIFT                    0
+#define CAU_ROTL_CA_CA3_WIDTH                    32
+#define CAU_ROTL_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
+#define CAU_ROTL_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA4_SHIFT                    0
+#define CAU_ROTL_CA_CA4_WIDTH                    32
+#define CAU_ROTL_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
+#define CAU_ROTL_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA5_SHIFT                    0
+#define CAU_ROTL_CA_CA5_WIDTH                    32
+#define CAU_ROTL_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
+#define CAU_ROTL_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA6_SHIFT                    0
+#define CAU_ROTL_CA_CA6_WIDTH                    32
+#define CAU_ROTL_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
+#define CAU_ROTL_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA7_SHIFT                    0
+#define CAU_ROTL_CA_CA7_WIDTH                    32
+#define CAU_ROTL_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
+#define CAU_ROTL_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA8_SHIFT                    0
+#define CAU_ROTL_CA_CA8_WIDTH                    32
+#define CAU_ROTL_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
+/* AESC_CASR Bit Fields */
+#define CAU_AESC_CASR_IC_MASK                    0x1u
+#define CAU_AESC_CASR_IC_SHIFT                   0
+#define CAU_AESC_CASR_IC_WIDTH                   1
+#define CAU_AESC_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_IC_SHIFT))&CAU_AESC_CASR_IC_MASK)
+#define CAU_AESC_CASR_DPE_MASK                   0x2u
+#define CAU_AESC_CASR_DPE_SHIFT                  1
+#define CAU_AESC_CASR_DPE_WIDTH                  1
+#define CAU_AESC_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_DPE_SHIFT))&CAU_AESC_CASR_DPE_MASK)
+#define CAU_AESC_CASR_VER_MASK                   0xF0000000u
+#define CAU_AESC_CASR_VER_SHIFT                  28
+#define CAU_AESC_CASR_VER_WIDTH                  4
+#define CAU_AESC_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
+/* AESC_CAA Bit Fields */
+#define CAU_AESC_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_AESC_CAA_ACC_SHIFT                   0
+#define CAU_AESC_CAA_ACC_WIDTH                   32
+#define CAU_AESC_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
+/* AESC_CA Bit Fields */
+#define CAU_AESC_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA0_SHIFT                    0
+#define CAU_AESC_CA_CA0_WIDTH                    32
+#define CAU_AESC_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
+#define CAU_AESC_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA1_SHIFT                    0
+#define CAU_AESC_CA_CA1_WIDTH                    32
+#define CAU_AESC_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
+#define CAU_AESC_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA2_SHIFT                    0
+#define CAU_AESC_CA_CA2_WIDTH                    32
+#define CAU_AESC_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
+#define CAU_AESC_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA3_SHIFT                    0
+#define CAU_AESC_CA_CA3_WIDTH                    32
+#define CAU_AESC_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
+#define CAU_AESC_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA4_SHIFT                    0
+#define CAU_AESC_CA_CA4_WIDTH                    32
+#define CAU_AESC_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
+#define CAU_AESC_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA5_SHIFT                    0
+#define CAU_AESC_CA_CA5_WIDTH                    32
+#define CAU_AESC_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
+#define CAU_AESC_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA6_SHIFT                    0
+#define CAU_AESC_CA_CA6_WIDTH                    32
+#define CAU_AESC_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
+#define CAU_AESC_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA7_SHIFT                    0
+#define CAU_AESC_CA_CA7_WIDTH                    32
+#define CAU_AESC_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
+#define CAU_AESC_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA8_SHIFT                    0
+#define CAU_AESC_CA_CA8_WIDTH                    32
+#define CAU_AESC_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
+/* AESIC_CASR Bit Fields */
+#define CAU_AESIC_CASR_IC_MASK                   0x1u
+#define CAU_AESIC_CASR_IC_SHIFT                  0
+#define CAU_AESIC_CASR_IC_WIDTH                  1
+#define CAU_AESIC_CASR_IC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_IC_SHIFT))&CAU_AESIC_CASR_IC_MASK)
+#define CAU_AESIC_CASR_DPE_MASK                  0x2u
+#define CAU_AESIC_CASR_DPE_SHIFT                 1
+#define CAU_AESIC_CASR_DPE_WIDTH                 1
+#define CAU_AESIC_CASR_DPE(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_DPE_SHIFT))&CAU_AESIC_CASR_DPE_MASK)
+#define CAU_AESIC_CASR_VER_MASK                  0xF0000000u
+#define CAU_AESIC_CASR_VER_SHIFT                 28
+#define CAU_AESIC_CASR_VER_WIDTH                 4
+#define CAU_AESIC_CASR_VER(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
+/* AESIC_CAA Bit Fields */
+#define CAU_AESIC_CAA_ACC_MASK                   0xFFFFFFFFu
+#define CAU_AESIC_CAA_ACC_SHIFT                  0
+#define CAU_AESIC_CAA_ACC_WIDTH                  32
+#define CAU_AESIC_CAA_ACC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
+/* AESIC_CA Bit Fields */
+#define CAU_AESIC_CA_CA0_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA0_SHIFT                   0
+#define CAU_AESIC_CA_CA0_WIDTH                   32
+#define CAU_AESIC_CA_CA0(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
+#define CAU_AESIC_CA_CA1_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA1_SHIFT                   0
+#define CAU_AESIC_CA_CA1_WIDTH                   32
+#define CAU_AESIC_CA_CA1(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
+#define CAU_AESIC_CA_CA2_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA2_SHIFT                   0
+#define CAU_AESIC_CA_CA2_WIDTH                   32
+#define CAU_AESIC_CA_CA2(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
+#define CAU_AESIC_CA_CA3_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA3_SHIFT                   0
+#define CAU_AESIC_CA_CA3_WIDTH                   32
+#define CAU_AESIC_CA_CA3(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
+#define CAU_AESIC_CA_CA4_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA4_SHIFT                   0
+#define CAU_AESIC_CA_CA4_WIDTH                   32
+#define CAU_AESIC_CA_CA4(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
+#define CAU_AESIC_CA_CA5_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA5_SHIFT                   0
+#define CAU_AESIC_CA_CA5_WIDTH                   32
+#define CAU_AESIC_CA_CA5(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
+#define CAU_AESIC_CA_CA6_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA6_SHIFT                   0
+#define CAU_AESIC_CA_CA6_WIDTH                   32
+#define CAU_AESIC_CA_CA6(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
+#define CAU_AESIC_CA_CA7_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA7_SHIFT                   0
+#define CAU_AESIC_CA_CA7_WIDTH                   32
+#define CAU_AESIC_CA_CA7(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
+#define CAU_AESIC_CA_CA8_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA8_SHIFT                   0
+#define CAU_AESIC_CA_CA8_WIDTH                   32
+#define CAU_AESIC_CA_CA8(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+/** Peripheral CAU base address */
+#define CAU_BASE                                 (0xE0081000u)
+/** Peripheral CAU base pointer */
+#define CAU                                      ((CAU_Type *)CAU_BASE)
+#define CAU_BASE_PTR                             (CAU)
+/** Array initializer of CAU peripheral base addresses */
+#define CAU_BASE_ADDRS                           { CAU_BASE }
+/** Array initializer of CAU peripheral base pointers */
+#define CAU_BASE_PTRS                            { CAU }
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register instance definitions */
+/* CAU */
+#define CAU_DIRECT0                              CAU_DIRECT_REG(CAU,0)
+#define CAU_DIRECT1                              CAU_DIRECT_REG(CAU,1)
+#define CAU_DIRECT2                              CAU_DIRECT_REG(CAU,2)
+#define CAU_DIRECT3                              CAU_DIRECT_REG(CAU,3)
+#define CAU_DIRECT4                              CAU_DIRECT_REG(CAU,4)
+#define CAU_DIRECT5                              CAU_DIRECT_REG(CAU,5)
+#define CAU_DIRECT6                              CAU_DIRECT_REG(CAU,6)
+#define CAU_DIRECT7                              CAU_DIRECT_REG(CAU,7)
+#define CAU_DIRECT8                              CAU_DIRECT_REG(CAU,8)
+#define CAU_DIRECT9                              CAU_DIRECT_REG(CAU,9)
+#define CAU_DIRECT10                             CAU_DIRECT_REG(CAU,10)
+#define CAU_DIRECT11                             CAU_DIRECT_REG(CAU,11)
+#define CAU_DIRECT12                             CAU_DIRECT_REG(CAU,12)
+#define CAU_DIRECT13                             CAU_DIRECT_REG(CAU,13)
+#define CAU_DIRECT14                             CAU_DIRECT_REG(CAU,14)
+#define CAU_DIRECT15                             CAU_DIRECT_REG(CAU,15)
+#define CAU_LDR_CASR                             CAU_LDR_CASR_REG(CAU)
+#define CAU_LDR_CAA                              CAU_LDR_CAA_REG(CAU)
+#define CAU_LDR_CA0                              CAU_LDR_CA_REG(CAU,0)
+#define CAU_LDR_CA1                              CAU_LDR_CA_REG(CAU,1)
+#define CAU_LDR_CA2                              CAU_LDR_CA_REG(CAU,2)
+#define CAU_LDR_CA3                              CAU_LDR_CA_REG(CAU,3)
+#define CAU_LDR_CA4                              CAU_LDR_CA_REG(CAU,4)
+#define CAU_LDR_CA5                              CAU_LDR_CA_REG(CAU,5)
+#define CAU_LDR_CA6                              CAU_LDR_CA_REG(CAU,6)
+#define CAU_LDR_CA7                              CAU_LDR_CA_REG(CAU,7)
+#define CAU_LDR_CA8                              CAU_LDR_CA_REG(CAU,8)
+#define CAU_STR_CASR                             CAU_STR_CASR_REG(CAU)
+#define CAU_STR_CAA                              CAU_STR_CAA_REG(CAU)
+#define CAU_STR_CA0                              CAU_STR_CA_REG(CAU,0)
+#define CAU_STR_CA1                              CAU_STR_CA_REG(CAU,1)
+#define CAU_STR_CA2                              CAU_STR_CA_REG(CAU,2)
+#define CAU_STR_CA3                              CAU_STR_CA_REG(CAU,3)
+#define CAU_STR_CA4                              CAU_STR_CA_REG(CAU,4)
+#define CAU_STR_CA5                              CAU_STR_CA_REG(CAU,5)
+#define CAU_STR_CA6                              CAU_STR_CA_REG(CAU,6)
+#define CAU_STR_CA7                              CAU_STR_CA_REG(CAU,7)
+#define CAU_STR_CA8                              CAU_STR_CA_REG(CAU,8)
+#define CAU_ADR_CASR                             CAU_ADR_CASR_REG(CAU)
+#define CAU_ADR_CAA                              CAU_ADR_CAA_REG(CAU)
+#define CAU_ADR_CA0                              CAU_ADR_CA_REG(CAU,0)
+#define CAU_ADR_CA1                              CAU_ADR_CA_REG(CAU,1)
+#define CAU_ADR_CA2                              CAU_ADR_CA_REG(CAU,2)
+#define CAU_ADR_CA3                              CAU_ADR_CA_REG(CAU,3)
+#define CAU_ADR_CA4                              CAU_ADR_CA_REG(CAU,4)
+#define CAU_ADR_CA5                              CAU_ADR_CA_REG(CAU,5)
+#define CAU_ADR_CA6                              CAU_ADR_CA_REG(CAU,6)
+#define CAU_ADR_CA7                              CAU_ADR_CA_REG(CAU,7)
+#define CAU_ADR_CA8                              CAU_ADR_CA_REG(CAU,8)
+#define CAU_RADR_CASR                            CAU_RADR_CASR_REG(CAU)
+#define CAU_RADR_CAA                             CAU_RADR_CAA_REG(CAU)
+#define CAU_RADR_CA0                             CAU_RADR_CA_REG(CAU,0)
+#define CAU_RADR_CA1                             CAU_RADR_CA_REG(CAU,1)
+#define CAU_RADR_CA2                             CAU_RADR_CA_REG(CAU,2)
+#define CAU_RADR_CA3                             CAU_RADR_CA_REG(CAU,3)
+#define CAU_RADR_CA4                             CAU_RADR_CA_REG(CAU,4)
+#define CAU_RADR_CA5                             CAU_RADR_CA_REG(CAU,5)
+#define CAU_RADR_CA6                             CAU_RADR_CA_REG(CAU,6)
+#define CAU_RADR_CA7                             CAU_RADR_CA_REG(CAU,7)
+#define CAU_RADR_CA8                             CAU_RADR_CA_REG(CAU,8)
+#define CAU_XOR_CASR                             CAU_XOR_CASR_REG(CAU)
+#define CAU_XOR_CAA                              CAU_XOR_CAA_REG(CAU)
+#define CAU_XOR_CA0                              CAU_XOR_CA_REG(CAU,0)
+#define CAU_XOR_CA1                              CAU_XOR_CA_REG(CAU,1)
+#define CAU_XOR_CA2                              CAU_XOR_CA_REG(CAU,2)
+#define CAU_XOR_CA3                              CAU_XOR_CA_REG(CAU,3)
+#define CAU_XOR_CA4                              CAU_XOR_CA_REG(CAU,4)
+#define CAU_XOR_CA5                              CAU_XOR_CA_REG(CAU,5)
+#define CAU_XOR_CA6                              CAU_XOR_CA_REG(CAU,6)
+#define CAU_XOR_CA7                              CAU_XOR_CA_REG(CAU,7)
+#define CAU_XOR_CA8                              CAU_XOR_CA_REG(CAU,8)
+#define CAU_ROTL_CASR                            CAU_ROTL_CASR_REG(CAU)
+#define CAU_ROTL_CAA                             CAU_ROTL_CAA_REG(CAU)
+#define CAU_ROTL_CA0                             CAU_ROTL_CA_REG(CAU,0)
+#define CAU_ROTL_CA1                             CAU_ROTL_CA_REG(CAU,1)
+#define CAU_ROTL_CA2                             CAU_ROTL_CA_REG(CAU,2)
+#define CAU_ROTL_CA3                             CAU_ROTL_CA_REG(CAU,3)
+#define CAU_ROTL_CA4                             CAU_ROTL_CA_REG(CAU,4)
+#define CAU_ROTL_CA5                             CAU_ROTL_CA_REG(CAU,5)
+#define CAU_ROTL_CA6                             CAU_ROTL_CA_REG(CAU,6)
+#define CAU_ROTL_CA7                             CAU_ROTL_CA_REG(CAU,7)
+#define CAU_ROTL_CA8                             CAU_ROTL_CA_REG(CAU,8)
+#define CAU_AESC_CASR                            CAU_AESC_CASR_REG(CAU)
+#define CAU_AESC_CAA                             CAU_AESC_CAA_REG(CAU)
+#define CAU_AESC_CA0                             CAU_AESC_CA_REG(CAU,0)
+#define CAU_AESC_CA1                             CAU_AESC_CA_REG(CAU,1)
+#define CAU_AESC_CA2                             CAU_AESC_CA_REG(CAU,2)
+#define CAU_AESC_CA3                             CAU_AESC_CA_REG(CAU,3)
+#define CAU_AESC_CA4                             CAU_AESC_CA_REG(CAU,4)
+#define CAU_AESC_CA5                             CAU_AESC_CA_REG(CAU,5)
+#define CAU_AESC_CA6                             CAU_AESC_CA_REG(CAU,6)
+#define CAU_AESC_CA7                             CAU_AESC_CA_REG(CAU,7)
+#define CAU_AESC_CA8                             CAU_AESC_CA_REG(CAU,8)
+#define CAU_AESIC_CASR                           CAU_AESIC_CASR_REG(CAU)
+#define CAU_AESIC_CAA                            CAU_AESIC_CAA_REG(CAU)
+#define CAU_AESIC_CA0                            CAU_AESIC_CA_REG(CAU,0)
+#define CAU_AESIC_CA1                            CAU_AESIC_CA_REG(CAU,1)
+#define CAU_AESIC_CA2                            CAU_AESIC_CA_REG(CAU,2)
+#define CAU_AESIC_CA3                            CAU_AESIC_CA_REG(CAU,3)
+#define CAU_AESIC_CA4                            CAU_AESIC_CA_REG(CAU,4)
+#define CAU_AESIC_CA5                            CAU_AESIC_CA_REG(CAU,5)
+#define CAU_AESIC_CA6                            CAU_AESIC_CA_REG(CAU,6)
+#define CAU_AESIC_CA7                            CAU_AESIC_CA_REG(CAU,7)
+#define CAU_AESIC_CA8                            CAU_AESIC_CA_REG(CAU,8)
+
+/* CAU - Register array accessors */
+#define CAU_DIRECT(index)                        CAU_DIRECT_REG(CAU,index)
+#define CAU_LDR_CA(index)                        CAU_LDR_CA_REG(CAU,index)
+#define CAU_STR_CA(index)                        CAU_STR_CA_REG(CAU,index)
+#define CAU_ADR_CA(index)                        CAU_ADR_CA_REG(CAU,index)
+#define CAU_RADR_CA(index)                       CAU_RADR_CA_REG(CAU,index)
+#define CAU_XOR_CA(index)                        CAU_XOR_CA_REG(CAU,index)
+#define CAU_ROTL_CA(index)                       CAU_ROTL_CA_REG(CAU,index)
+#define CAU_AESC_CA(index)                       CAU_AESC_CA_REG(CAU,index)
+#define CAU_AESIC_CA(index)                      CAU_AESIC_CA_REG(CAU,index)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base)                        ((base)->CR0)
+#define CMP_CR1_REG(base)                        ((base)->CR1)
+#define CMP_FPR_REG(base)                        ((base)->FPR)
+#define CMP_SCR_REG(base)                        ((base)->SCR)
+#define CMP_DACCR_REG(base)                      ((base)->DACCR)
+#define CMP_MUXCR_REG(base)                      ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK                     0x3u
+#define CMP_CR0_HYSTCTR_SHIFT                    0
+#define CMP_CR0_HYSTCTR_WIDTH                    2
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT                 4
+#define CMP_CR0_FILTER_CNT_WIDTH                 3
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK                          0x1u
+#define CMP_CR1_EN_SHIFT                         0
+#define CMP_CR1_EN_WIDTH                         1
+#define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK                         0x2u
+#define CMP_CR1_OPE_SHIFT                        1
+#define CMP_CR1_OPE_WIDTH                        1
+#define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK                         0x4u
+#define CMP_CR1_COS_SHIFT                        2
+#define CMP_CR1_COS_WIDTH                        1
+#define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK                         0x8u
+#define CMP_CR1_INV_SHIFT                        3
+#define CMP_CR1_INV_WIDTH                        1
+#define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK                       0x10u
+#define CMP_CR1_PMODE_SHIFT                      4
+#define CMP_CR1_PMODE_WIDTH                      1
+#define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
+#define CMP_CR1_WE_MASK                          0x40u
+#define CMP_CR1_WE_SHIFT                         6
+#define CMP_CR1_WE_WIDTH                         1
+#define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK                          0x80u
+#define CMP_CR1_SE_SHIFT                         7
+#define CMP_CR1_SE_WIDTH                         1
+#define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK                    0xFFu
+#define CMP_FPR_FILT_PER_SHIFT                   0
+#define CMP_FPR_FILT_PER_WIDTH                   8
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK                        0x1u
+#define CMP_SCR_COUT_SHIFT                       0
+#define CMP_SCR_COUT_WIDTH                       1
+#define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK                         0x2u
+#define CMP_SCR_CFF_SHIFT                        1
+#define CMP_SCR_CFF_WIDTH                        1
+#define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK                         0x4u
+#define CMP_SCR_CFR_SHIFT                        2
+#define CMP_SCR_CFR_WIDTH                        1
+#define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK                         0x8u
+#define CMP_SCR_IEF_SHIFT                        3
+#define CMP_SCR_IEF_WIDTH                        1
+#define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK                         0x10u
+#define CMP_SCR_IER_SHIFT                        4
+#define CMP_SCR_IER_WIDTH                        1
+#define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK                       0x40u
+#define CMP_SCR_DMAEN_SHIFT                      6
+#define CMP_SCR_DMAEN_WIDTH                      1
+#define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK                     0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT                    0
+#define CMP_DACCR_VOSEL_WIDTH                    6
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     0x40u
+#define CMP_DACCR_VRSEL_SHIFT                    6
+#define CMP_DACCR_VRSEL_WIDTH                    1
+#define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK                     0x80u
+#define CMP_DACCR_DACEN_SHIFT                    7
+#define CMP_DACCR_DACEN_WIDTH                    1
+#define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK                      0x7u
+#define CMP_MUXCR_MSEL_SHIFT                     0
+#define CMP_MUXCR_MSEL_WIDTH                     3
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      0x38u
+#define CMP_MUXCR_PSEL_SHIFT                     3
+#define CMP_MUXCR_PSEL_WIDTH                     3
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK                      0x80u
+#define CMP_MUXCR_PSTM_SHIFT                     7
+#define CMP_MUXCR_PSTM_WIDTH                     1
+#define CMP_MUXCR_PSTM(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSTM_SHIFT))&CMP_MUXCR_PSTM_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR                            (CMP0)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE                                (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1                                     ((CMP_Type *)CMP1_BASE)
+#define CMP1_BASE_PTR                            (CMP1)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE                                (0x40073010u)
+/** Peripheral CMP2 base pointer */
+#define CMP2                                     ((CMP_Type *)CMP2_BASE)
+#define CMP2_BASE_PTR                            (CMP2)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS                           { CMP0_BASE, CMP1_BASE, CMP2_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS                            { CMP0, CMP1, CMP2 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0                                 CMP_CR0_REG(CMP0)
+#define CMP0_CR1                                 CMP_CR1_REG(CMP0)
+#define CMP0_FPR                                 CMP_FPR_REG(CMP0)
+#define CMP0_SCR                                 CMP_SCR_REG(CMP0)
+#define CMP0_DACCR                               CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR                               CMP_MUXCR_REG(CMP0)
+/* CMP1 */
+#define CMP1_CR0                                 CMP_CR0_REG(CMP1)
+#define CMP1_CR1                                 CMP_CR1_REG(CMP1)
+#define CMP1_FPR                                 CMP_FPR_REG(CMP1)
+#define CMP1_SCR                                 CMP_SCR_REG(CMP1)
+#define CMP1_DACCR                               CMP_DACCR_REG(CMP1)
+#define CMP1_MUXCR                               CMP_MUXCR_REG(CMP1)
+/* CMP2 */
+#define CMP2_CR0                                 CMP_CR0_REG(CMP2)
+#define CMP2_CR1                                 CMP_CR1_REG(CMP2)
+#define CMP2_FPR                                 CMP_FPR_REG(CMP2)
+#define CMP2_SCR                                 CMP_SCR_REG(CMP2)
+#define CMP2_DACCR                               CMP_DACCR_REG(CMP2)
+#define CMP2_MUXCR                               CMP_MUXCR_REG(CMP2)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CGH1;                               /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+  __IO uint8_t CGL1;                               /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+  __IO uint8_t CGH2;                               /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+  __IO uint8_t CGL2;                               /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+  __IO uint8_t OC;                                 /**< CMT Output Control Register, offset: 0x4 */
+  __IO uint8_t MSC;                                /**< CMT Modulator Status and Control Register, offset: 0x5 */
+  __IO uint8_t CMD1;                               /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+  __IO uint8_t CMD2;                               /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+  __IO uint8_t CMD3;                               /**< CMT Modulator Data Register Space High, offset: 0x8 */
+  __IO uint8_t CMD4;                               /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+  __IO uint8_t PPS;                                /**< CMT Primary Prescaler Register, offset: 0xA */
+  __IO uint8_t DMA;                                /**< CMT Direct Memory Access Register, offset: 0xB */
+} CMT_Type, *CMT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register accessors */
+#define CMT_CGH1_REG(base)                       ((base)->CGH1)
+#define CMT_CGL1_REG(base)                       ((base)->CGL1)
+#define CMT_CGH2_REG(base)                       ((base)->CGH2)
+#define CMT_CGL2_REG(base)                       ((base)->CGL2)
+#define CMT_OC_REG(base)                         ((base)->OC)
+#define CMT_MSC_REG(base)                        ((base)->MSC)
+#define CMT_CMD1_REG(base)                       ((base)->CMD1)
+#define CMT_CMD2_REG(base)                       ((base)->CMD2)
+#define CMT_CMD3_REG(base)                       ((base)->CMD3)
+#define CMT_CMD4_REG(base)                       ((base)->CMD4)
+#define CMT_PPS_REG(base)                        ((base)->PPS)
+#define CMT_DMA_REG(base)                        ((base)->DMA)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK                         0xFFu
+#define CMT_CGH1_PH_SHIFT                        0
+#define CMT_CGH1_PH_WIDTH                        8
+#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK                         0xFFu
+#define CMT_CGL1_PL_SHIFT                        0
+#define CMT_CGL1_PL_WIDTH                        8
+#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK                         0xFFu
+#define CMT_CGH2_SH_SHIFT                        0
+#define CMT_CGH2_SH_WIDTH                        8
+#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK                         0xFFu
+#define CMT_CGL2_SL_SHIFT                        0
+#define CMT_CGL2_SL_WIDTH                        8
+#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK                       0x20u
+#define CMT_OC_IROPEN_SHIFT                      5
+#define CMT_OC_IROPEN_WIDTH                      1
+#define CMT_OC_IROPEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROPEN_SHIFT))&CMT_OC_IROPEN_MASK)
+#define CMT_OC_CMTPOL_MASK                       0x40u
+#define CMT_OC_CMTPOL_SHIFT                      6
+#define CMT_OC_CMTPOL_WIDTH                      1
+#define CMT_OC_CMTPOL(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_OC_CMTPOL_SHIFT))&CMT_OC_CMTPOL_MASK)
+#define CMT_OC_IROL_MASK                         0x80u
+#define CMT_OC_IROL_SHIFT                        7
+#define CMT_OC_IROL_WIDTH                        1
+#define CMT_OC_IROL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROL_SHIFT))&CMT_OC_IROL_MASK)
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK                       0x1u
+#define CMT_MSC_MCGEN_SHIFT                      0
+#define CMT_MSC_MCGEN_WIDTH                      1
+#define CMT_MSC_MCGEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_MCGEN_SHIFT))&CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_EOCIE_MASK                       0x2u
+#define CMT_MSC_EOCIE_SHIFT                      1
+#define CMT_MSC_EOCIE_WIDTH                      1
+#define CMT_MSC_EOCIE(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCIE_SHIFT))&CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_FSK_MASK                         0x4u
+#define CMT_MSC_FSK_SHIFT                        2
+#define CMT_MSC_FSK_WIDTH                        1
+#define CMT_MSC_FSK(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_MSC_FSK_SHIFT))&CMT_MSC_FSK_MASK)
+#define CMT_MSC_BASE_MASK                        0x8u
+#define CMT_MSC_BASE_SHIFT                       3
+#define CMT_MSC_BASE_WIDTH                       1
+#define CMT_MSC_BASE(x)                          (((uint8_t)(((uint8_t)(x))<<CMT_MSC_BASE_SHIFT))&CMT_MSC_BASE_MASK)
+#define CMT_MSC_EXSPC_MASK                       0x10u
+#define CMT_MSC_EXSPC_SHIFT                      4
+#define CMT_MSC_EXSPC_WIDTH                      1
+#define CMT_MSC_EXSPC(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EXSPC_SHIFT))&CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_CMTDIV_MASK                      0x60u
+#define CMT_MSC_CMTDIV_SHIFT                     5
+#define CMT_MSC_CMTDIV_WIDTH                     2
+#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK                        0x80u
+#define CMT_MSC_EOCF_SHIFT                       7
+#define CMT_MSC_EOCF_WIDTH                       1
+#define CMT_MSC_EOCF(x)                          (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCF_SHIFT))&CMT_MSC_EOCF_MASK)
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK                         0xFFu
+#define CMT_CMD1_MB_SHIFT                        0
+#define CMT_CMD1_MB_WIDTH                        8
+#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK                         0xFFu
+#define CMT_CMD2_MB_SHIFT                        0
+#define CMT_CMD2_MB_WIDTH                        8
+#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK                         0xFFu
+#define CMT_CMD3_SB_SHIFT                        0
+#define CMT_CMD3_SB_WIDTH                        8
+#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK                         0xFFu
+#define CMT_CMD4_SB_SHIFT                        0
+#define CMT_CMD4_SB_WIDTH                        8
+#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK                      0xFu
+#define CMT_PPS_PPSDIV_SHIFT                     0
+#define CMT_PPS_PPSDIV_WIDTH                     4
+#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK                         0x1u
+#define CMT_DMA_DMA_SHIFT                        0
+#define CMT_DMA_DMA_WIDTH                        1
+#define CMT_DMA_DMA(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_DMA_DMA_SHIFT))&CMT_DMA_DMA_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE                                 (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT                                      ((CMT_Type *)CMT_BASE)
+#define CMT_BASE_PTR                             (CMT)
+/** Array initializer of CMT peripheral base addresses */
+#define CMT_BASE_ADDRS                           { CMT_BASE }
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASE_PTRS                            { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS                                 { CMT_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register instance definitions */
+/* CMT */
+#define CMT_CGH1                                 CMT_CGH1_REG(CMT)
+#define CMT_CGL1                                 CMT_CGL1_REG(CMT)
+#define CMT_CGH2                                 CMT_CGH2_REG(CMT)
+#define CMT_CGL2                                 CMT_CGL2_REG(CMT)
+#define CMT_OC                                   CMT_OC_REG(CMT)
+#define CMT_MSC                                  CMT_MSC_REG(CMT)
+#define CMT_CMD1                                 CMT_CMD1_REG(CMT)
+#define CMT_CMD2                                 CMT_CMD2_REG(CMT)
+#define CMT_CMD3                                 CMT_CMD3_REG(CMT)
+#define CMT_CMD4                                 CMT_CMD4_REG(CMT)
+#define CMT_PPS                                  CMT_PPS_REG(CMT)
+#define CMT_DMA                                  CMT_DMA_REG(CMT)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type, *CRC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register accessors */
+#define CRC_DATAL_REG(base)                      ((base)->ACCESS16BIT.DATAL)
+#define CRC_DATAH_REG(base)                      ((base)->ACCESS16BIT.DATAH)
+#define CRC_DATA_REG(base)                       ((base)->DATA)
+#define CRC_DATALL_REG(base)                     ((base)->ACCESS8BIT.DATALL)
+#define CRC_DATALU_REG(base)                     ((base)->ACCESS8BIT.DATALU)
+#define CRC_DATAHL_REG(base)                     ((base)->ACCESS8BIT.DATAHL)
+#define CRC_DATAHU_REG(base)                     ((base)->ACCESS8BIT.DATAHU)
+#define CRC_GPOLYL_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYL)
+#define CRC_GPOLYH_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYH)
+#define CRC_GPOLY_REG(base)                      ((base)->GPOLY)
+#define CRC_GPOLYLL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
+#define CRC_GPOLYLU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
+#define CRC_GPOLYHL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
+#define CRC_GPOLYHU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
+#define CRC_CTRL_REG(base)                       ((base)->CTRL)
+#define CRC_CTRLHU_REG(base)                     ((base)->CTRL_ACCESS8BIT.CTRLHU)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK                     0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT                    0
+#define CRC_DATAL_DATAL_WIDTH                    16
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK                     0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT                    0
+#define CRC_DATAH_DATAH_WIDTH                    16
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK                         0xFFu
+#define CRC_DATA_LL_SHIFT                        0
+#define CRC_DATA_LL_WIDTH                        8
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         0xFF00u
+#define CRC_DATA_LU_SHIFT                        8
+#define CRC_DATA_LU_WIDTH                        8
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         0xFF0000u
+#define CRC_DATA_HL_SHIFT                        16
+#define CRC_DATA_HL_WIDTH                        8
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         0xFF000000u
+#define CRC_DATA_HU_SHIFT                        24
+#define CRC_DATA_HU_WIDTH                        8
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK                   0xFFu
+#define CRC_DATALL_DATALL_SHIFT                  0
+#define CRC_DATALL_DATALL_WIDTH                  8
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK                   0xFFu
+#define CRC_DATALU_DATALU_SHIFT                  0
+#define CRC_DATALU_DATALU_WIDTH                  8
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK                   0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT                  0
+#define CRC_DATAHL_DATAHL_WIDTH                  8
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK                   0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT                  0
+#define CRC_DATAHU_DATAHU_WIDTH                  8
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT                  0
+#define CRC_GPOLYL_GPOLYL_WIDTH                  16
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT                  0
+#define CRC_GPOLYH_GPOLYH_WIDTH                  16
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK                       0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT                      0
+#define CRC_GPOLY_LOW_WIDTH                      16
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT                     16
+#define CRC_GPOLY_HIGH_WIDTH                     16
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                0
+#define CRC_GPOLYLL_GPOLYLL_WIDTH                8
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                0
+#define CRC_GPOLYLU_GPOLYLU_WIDTH                8
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                0
+#define CRC_GPOLYHL_GPOLYHL_WIDTH                8
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                0
+#define CRC_GPOLYHU_GPOLYHU_WIDTH                8
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK                       0x1000000u
+#define CRC_CTRL_TCRC_SHIFT                      24
+#define CRC_CTRL_TCRC_WIDTH                      1
+#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK                        0x2000000u
+#define CRC_CTRL_WAS_SHIFT                       25
+#define CRC_CTRL_WAS_WIDTH                       1
+#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK                       0x4000000u
+#define CRC_CTRL_FXOR_SHIFT                      26
+#define CRC_CTRL_FXOR_WIDTH                      1
+#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK                       0x30000000u
+#define CRC_CTRL_TOTR_SHIFT                      28
+#define CRC_CTRL_TOTR_WIDTH                      2
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        0xC0000000u
+#define CRC_CTRL_TOT_SHIFT                       30
+#define CRC_CTRL_TOT_WIDTH                       2
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK                     0x1u
+#define CRC_CTRLHU_TCRC_SHIFT                    0
+#define CRC_CTRLHU_TCRC_WIDTH                    1
+#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TCRC_SHIFT))&CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK                      0x2u
+#define CRC_CTRLHU_WAS_SHIFT                     1
+#define CRC_CTRLHU_WAS_WIDTH                     1
+#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_WAS_SHIFT))&CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK                     0x4u
+#define CRC_CTRLHU_FXOR_SHIFT                    2
+#define CRC_CTRLHU_FXOR_WIDTH                    1
+#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_FXOR_SHIFT))&CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK                     0x30u
+#define CRC_CTRLHU_TOTR_SHIFT                    4
+#define CRC_CTRLHU_TOTR_WIDTH                    2
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      0xC0u
+#define CRC_CTRLHU_TOT_SHIFT                     6
+#define CRC_CTRLHU_TOT_WIDTH                     2
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+#define CRC_BASE_PTR                             (CRC0)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register instance definitions */
+/* CRC */
+#define CRC_DATA                                 CRC_DATA_REG(CRC0)
+#define CRC_DATAL                                CRC_DATAL_REG(CRC0)
+#define CRC_DATALL                               CRC_DATALL_REG(CRC0)
+#define CRC_DATALU                               CRC_DATALU_REG(CRC0)
+#define CRC_DATAH                                CRC_DATAH_REG(CRC0)
+#define CRC_DATAHL                               CRC_DATAHL_REG(CRC0)
+#define CRC_DATAHU                               CRC_DATAHU_REG(CRC0)
+#define CRC_GPOLY                                CRC_GPOLY_REG(CRC0)
+#define CRC_GPOLYL                               CRC_GPOLYL_REG(CRC0)
+#define CRC_GPOLYLL                              CRC_GPOLYLL_REG(CRC0)
+#define CRC_GPOLYLU                              CRC_GPOLYLU_REG(CRC0)
+#define CRC_GPOLYH                               CRC_GPOLYH_REG(CRC0)
+#define CRC_GPOLYHL                              CRC_GPOLYHL_REG(CRC0)
+#define CRC_GPOLYHU                              CRC_GPOLYHU_REG(CRC0)
+#define CRC_CTRL                                 CRC_CTRL_REG(CRC0)
+#define CRC_CTRLHU                               CRC_CTRLHU_REG(CRC0)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[16];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index)                 ((base)->DAT[index].DATL)
+#define DAC_DATL_COUNT                           16
+#define DAC_DATH_REG(base,index)                 ((base)->DAT[index].DATH)
+#define DAC_DATH_COUNT                           16
+#define DAC_SR_REG(base)                         ((base)->SR)
+#define DAC_C0_REG(base)                         ((base)->C0)
+#define DAC_C1_REG(base)                         ((base)->C1)
+#define DAC_C2_REG(base)                         ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK                      0xFFu
+#define DAC_DATL_DATA0_SHIFT                     0
+#define DAC_DATL_DATA0_WIDTH                     8
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK                      0xFu
+#define DAC_DATH_DATA1_SHIFT                     0
+#define DAC_DATH_DATA1_WIDTH                     4
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK                    0x1u
+#define DAC_SR_DACBFRPBF_SHIFT                   0
+#define DAC_SR_DACBFRPBF_WIDTH                   1
+#define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK                    0x2u
+#define DAC_SR_DACBFRPTF_SHIFT                   1
+#define DAC_SR_DACBFRPTF_WIDTH                   1
+#define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK                     0x4u
+#define DAC_SR_DACBFWMF_SHIFT                    2
+#define DAC_SR_DACBFWMF_WIDTH                    1
+#define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFWMF_SHIFT))&DAC_SR_DACBFWMF_MASK)
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK                     0x1u
+#define DAC_C0_DACBBIEN_SHIFT                    0
+#define DAC_C0_DACBBIEN_WIDTH                    1
+#define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK                     0x2u
+#define DAC_C0_DACBTIEN_SHIFT                    1
+#define DAC_C0_DACBTIEN_WIDTH                    1
+#define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK                     0x4u
+#define DAC_C0_DACBWIEN_SHIFT                    2
+#define DAC_C0_DACBWIEN_WIDTH                    1
+#define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBWIEN_SHIFT))&DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK                         0x8u
+#define DAC_C0_LPEN_SHIFT                        3
+#define DAC_C0_LPEN_WIDTH                        1
+#define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK                     0x10u
+#define DAC_C0_DACSWTRG_SHIFT                    4
+#define DAC_C0_DACSWTRG_WIDTH                    1
+#define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK                    0x20u
+#define DAC_C0_DACTRGSEL_SHIFT                   5
+#define DAC_C0_DACTRGSEL_WIDTH                   1
+#define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK                       0x40u
+#define DAC_C0_DACRFS_SHIFT                      6
+#define DAC_C0_DACRFS_WIDTH                      1
+#define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK                        0x80u
+#define DAC_C0_DACEN_SHIFT                       7
+#define DAC_C0_DACEN_WIDTH                       1
+#define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK                      0x1u
+#define DAC_C1_DACBFEN_SHIFT                     0
+#define DAC_C1_DACBFEN_WIDTH                     1
+#define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK                      0x6u
+#define DAC_C1_DACBFMD_SHIFT                     1
+#define DAC_C1_DACBFMD_WIDTH                     2
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK                      0x18u
+#define DAC_C1_DACBFWM_SHIFT                     3
+#define DAC_C1_DACBFWM_WIDTH                     2
+#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK                        0x80u
+#define DAC_C1_DMAEN_SHIFT                       7
+#define DAC_C1_DMAEN_WIDTH                       1
+#define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK                      0xFu
+#define DAC_C2_DACBFUP_SHIFT                     0
+#define DAC_C2_DACBFUP_WIDTH                     4
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      0xF0u
+#define DAC_C2_DACBFRP_SHIFT                     4
+#define DAC_C2_DACBFRP_WIDTH                     4
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR                            (DAC0)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE                                (0x400CD000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1                                     ((DAC_Type *)DAC1_BASE)
+#define DAC1_BASE_PTR                            (DAC1)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS                           { DAC0_BASE, DAC1_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS                            { DAC0, DAC1 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn, DAC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L                               DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H                               DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L                               DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H                               DAC_DATH_REG(DAC0,1)
+#define DAC0_DAT2L                               DAC_DATL_REG(DAC0,2)
+#define DAC0_DAT2H                               DAC_DATH_REG(DAC0,2)
+#define DAC0_DAT3L                               DAC_DATL_REG(DAC0,3)
+#define DAC0_DAT3H                               DAC_DATH_REG(DAC0,3)
+#define DAC0_DAT4L                               DAC_DATL_REG(DAC0,4)
+#define DAC0_DAT4H                               DAC_DATH_REG(DAC0,4)
+#define DAC0_DAT5L                               DAC_DATL_REG(DAC0,5)
+#define DAC0_DAT5H                               DAC_DATH_REG(DAC0,5)
+#define DAC0_DAT6L                               DAC_DATL_REG(DAC0,6)
+#define DAC0_DAT6H                               DAC_DATH_REG(DAC0,6)
+#define DAC0_DAT7L                               DAC_DATL_REG(DAC0,7)
+#define DAC0_DAT7H                               DAC_DATH_REG(DAC0,7)
+#define DAC0_DAT8L                               DAC_DATL_REG(DAC0,8)
+#define DAC0_DAT8H                               DAC_DATH_REG(DAC0,8)
+#define DAC0_DAT9L                               DAC_DATL_REG(DAC0,9)
+#define DAC0_DAT9H                               DAC_DATH_REG(DAC0,9)
+#define DAC0_DAT10L                              DAC_DATL_REG(DAC0,10)
+#define DAC0_DAT10H                              DAC_DATH_REG(DAC0,10)
+#define DAC0_DAT11L                              DAC_DATL_REG(DAC0,11)
+#define DAC0_DAT11H                              DAC_DATH_REG(DAC0,11)
+#define DAC0_DAT12L                              DAC_DATL_REG(DAC0,12)
+#define DAC0_DAT12H                              DAC_DATH_REG(DAC0,12)
+#define DAC0_DAT13L                              DAC_DATL_REG(DAC0,13)
+#define DAC0_DAT13H                              DAC_DATH_REG(DAC0,13)
+#define DAC0_DAT14L                              DAC_DATL_REG(DAC0,14)
+#define DAC0_DAT14H                              DAC_DATH_REG(DAC0,14)
+#define DAC0_DAT15L                              DAC_DATL_REG(DAC0,15)
+#define DAC0_DAT15H                              DAC_DATH_REG(DAC0,15)
+#define DAC0_SR                                  DAC_SR_REG(DAC0)
+#define DAC0_C0                                  DAC_C0_REG(DAC0)
+#define DAC0_C1                                  DAC_C1_REG(DAC0)
+#define DAC0_C2                                  DAC_C2_REG(DAC0)
+/* DAC1 */
+#define DAC1_DAT0L                               DAC_DATL_REG(DAC1,0)
+#define DAC1_DAT0H                               DAC_DATH_REG(DAC1,0)
+#define DAC1_DAT1L                               DAC_DATL_REG(DAC1,1)
+#define DAC1_DAT1H                               DAC_DATH_REG(DAC1,1)
+#define DAC1_DAT2L                               DAC_DATL_REG(DAC1,2)
+#define DAC1_DAT2H                               DAC_DATH_REG(DAC1,2)
+#define DAC1_DAT3L                               DAC_DATL_REG(DAC1,3)
+#define DAC1_DAT3H                               DAC_DATH_REG(DAC1,3)
+#define DAC1_DAT4L                               DAC_DATL_REG(DAC1,4)
+#define DAC1_DAT4H                               DAC_DATH_REG(DAC1,4)
+#define DAC1_DAT5L                               DAC_DATL_REG(DAC1,5)
+#define DAC1_DAT5H                               DAC_DATH_REG(DAC1,5)
+#define DAC1_DAT6L                               DAC_DATL_REG(DAC1,6)
+#define DAC1_DAT6H                               DAC_DATH_REG(DAC1,6)
+#define DAC1_DAT7L                               DAC_DATL_REG(DAC1,7)
+#define DAC1_DAT7H                               DAC_DATH_REG(DAC1,7)
+#define DAC1_DAT8L                               DAC_DATL_REG(DAC1,8)
+#define DAC1_DAT8H                               DAC_DATH_REG(DAC1,8)
+#define DAC1_DAT9L                               DAC_DATL_REG(DAC1,9)
+#define DAC1_DAT9H                               DAC_DATH_REG(DAC1,9)
+#define DAC1_DAT10L                              DAC_DATL_REG(DAC1,10)
+#define DAC1_DAT10H                              DAC_DATH_REG(DAC1,10)
+#define DAC1_DAT11L                              DAC_DATL_REG(DAC1,11)
+#define DAC1_DAT11H                              DAC_DATH_REG(DAC1,11)
+#define DAC1_DAT12L                              DAC_DATL_REG(DAC1,12)
+#define DAC1_DAT12H                              DAC_DATH_REG(DAC1,12)
+#define DAC1_DAT13L                              DAC_DATL_REG(DAC1,13)
+#define DAC1_DAT13H                              DAC_DATH_REG(DAC1,13)
+#define DAC1_DAT14L                              DAC_DATL_REG(DAC1,14)
+#define DAC1_DAT14H                              DAC_DATH_REG(DAC1,14)
+#define DAC1_DAT15L                              DAC_DATL_REG(DAC1,15)
+#define DAC1_DAT15H                              DAC_DATH_REG(DAC1,15)
+#define DAC1_SR                                  DAC_SR_REG(DAC1)
+#define DAC1_C0                                  DAC_C0_REG(DAC1)
+#define DAC1_C1                                  DAC_C1_REG(DAC1)
+#define DAC1_C2                                  DAC_C2_REG(DAC1)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index)                         DAC_DATL_REG(DAC0,index)
+#define DAC1_DATL(index)                         DAC_DATL_REG(DAC1,index)
+#define DAC0_DATH(index)                         DAC_DATH_REG(DAC0,index)
+#define DAC1_DATH(index)                         DAC_DATH_REG(DAC1,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[200];
+  __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /**< Channel n Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /**< Channel n Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /**< Channel n Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /**< Channel n Priority Register, offset: 0x107 */
+  __IO uint8_t DCHPRI11;                           /**< Channel n Priority Register, offset: 0x108 */
+  __IO uint8_t DCHPRI10;                           /**< Channel n Priority Register, offset: 0x109 */
+  __IO uint8_t DCHPRI9;                            /**< Channel n Priority Register, offset: 0x10A */
+  __IO uint8_t DCHPRI8;                            /**< Channel n Priority Register, offset: 0x10B */
+  __IO uint8_t DCHPRI15;                           /**< Channel n Priority Register, offset: 0x10C */
+  __IO uint8_t DCHPRI14;                           /**< Channel n Priority Register, offset: 0x10D */
+  __IO uint8_t DCHPRI13;                           /**< Channel n Priority Register, offset: 0x10E */
+  __IO uint8_t DCHPRI12;                           /**< Channel n Priority Register, offset: 0x10F */
+       uint8_t RESERVED_6[3824];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[16];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_CR_REG(base)                         ((base)->CR)
+#define DMA_ES_REG(base)                         ((base)->ES)
+#define DMA_ERQ_REG(base)                        ((base)->ERQ)
+#define DMA_EEI_REG(base)                        ((base)->EEI)
+#define DMA_CEEI_REG(base)                       ((base)->CEEI)
+#define DMA_SEEI_REG(base)                       ((base)->SEEI)
+#define DMA_CERQ_REG(base)                       ((base)->CERQ)
+#define DMA_SERQ_REG(base)                       ((base)->SERQ)
+#define DMA_CDNE_REG(base)                       ((base)->CDNE)
+#define DMA_SSRT_REG(base)                       ((base)->SSRT)
+#define DMA_CERR_REG(base)                       ((base)->CERR)
+#define DMA_CINT_REG(base)                       ((base)->CINT)
+#define DMA_INT_REG(base)                        ((base)->INT)
+#define DMA_ERR_REG(base)                        ((base)->ERR)
+#define DMA_HRS_REG(base)                        ((base)->HRS)
+#define DMA_DCHPRI3_REG(base)                    ((base)->DCHPRI3)
+#define DMA_DCHPRI2_REG(base)                    ((base)->DCHPRI2)
+#define DMA_DCHPRI1_REG(base)                    ((base)->DCHPRI1)
+#define DMA_DCHPRI0_REG(base)                    ((base)->DCHPRI0)
+#define DMA_DCHPRI7_REG(base)                    ((base)->DCHPRI7)
+#define DMA_DCHPRI6_REG(base)                    ((base)->DCHPRI6)
+#define DMA_DCHPRI5_REG(base)                    ((base)->DCHPRI5)
+#define DMA_DCHPRI4_REG(base)                    ((base)->DCHPRI4)
+#define DMA_DCHPRI11_REG(base)                   ((base)->DCHPRI11)
+#define DMA_DCHPRI10_REG(base)                   ((base)->DCHPRI10)
+#define DMA_DCHPRI9_REG(base)                    ((base)->DCHPRI9)
+#define DMA_DCHPRI8_REG(base)                    ((base)->DCHPRI8)
+#define DMA_DCHPRI15_REG(base)                   ((base)->DCHPRI15)
+#define DMA_DCHPRI14_REG(base)                   ((base)->DCHPRI14)
+#define DMA_DCHPRI13_REG(base)                   ((base)->DCHPRI13)
+#define DMA_DCHPRI12_REG(base)                   ((base)->DCHPRI12)
+#define DMA_SADDR_REG(base,index)                ((base)->TCD[index].SADDR)
+#define DMA_SADDR_COUNT                          16
+#define DMA_SOFF_REG(base,index)                 ((base)->TCD[index].SOFF)
+#define DMA_SOFF_COUNT                           16
+#define DMA_ATTR_REG(base,index)                 ((base)->TCD[index].ATTR)
+#define DMA_ATTR_COUNT                           16
+#define DMA_NBYTES_MLNO_REG(base,index)          ((base)->TCD[index].NBYTES_MLNO)
+#define DMA_NBYTES_MLNO_COUNT                    16
+#define DMA_NBYTES_MLOFFNO_REG(base,index)       ((base)->TCD[index].NBYTES_MLOFFNO)
+#define DMA_NBYTES_MLOFFNO_COUNT                 16
+#define DMA_NBYTES_MLOFFYES_REG(base,index)      ((base)->TCD[index].NBYTES_MLOFFYES)
+#define DMA_NBYTES_MLOFFYES_COUNT                16
+#define DMA_SLAST_REG(base,index)                ((base)->TCD[index].SLAST)
+#define DMA_SLAST_COUNT                          16
+#define DMA_DADDR_REG(base,index)                ((base)->TCD[index].DADDR)
+#define DMA_DADDR_COUNT                          16
+#define DMA_DOFF_REG(base,index)                 ((base)->TCD[index].DOFF)
+#define DMA_DOFF_COUNT                           16
+#define DMA_CITER_ELINKNO_REG(base,index)        ((base)->TCD[index].CITER_ELINKNO)
+#define DMA_CITER_ELINKNO_COUNT                  16
+#define DMA_CITER_ELINKYES_REG(base,index)       ((base)->TCD[index].CITER_ELINKYES)
+#define DMA_CITER_ELINKYES_COUNT                 16
+#define DMA_DLAST_SGA_REG(base,index)            ((base)->TCD[index].DLAST_SGA)
+#define DMA_DLAST_SGA_COUNT                      16
+#define DMA_CSR_REG(base,index)                  ((base)->TCD[index].CSR)
+#define DMA_CSR_COUNT                            16
+#define DMA_BITER_ELINKNO_REG(base,index)        ((base)->TCD[index].BITER_ELINKNO)
+#define DMA_BITER_ELINKNO_COUNT                  16
+#define DMA_BITER_ELINKYES_REG(base,index)       ((base)->TCD[index].BITER_ELINKYES)
+#define DMA_BITER_ELINKYES_COUNT                 16
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK                         0x2u
+#define DMA_CR_EDBG_SHIFT                        1
+#define DMA_CR_EDBG_WIDTH                        1
+#define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK                         0x4u
+#define DMA_CR_ERCA_SHIFT                        2
+#define DMA_CR_ERCA_WIDTH                        1
+#define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK                          0x10u
+#define DMA_CR_HOE_SHIFT                         4
+#define DMA_CR_HOE_WIDTH                         1
+#define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK                         0x20u
+#define DMA_CR_HALT_SHIFT                        5
+#define DMA_CR_HALT_WIDTH                        1
+#define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK                          0x40u
+#define DMA_CR_CLM_SHIFT                         6
+#define DMA_CR_CLM_WIDTH                         1
+#define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK                         0x80u
+#define DMA_CR_EMLM_SHIFT                        7
+#define DMA_CR_EMLM_WIDTH                        1
+#define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK                          0x10000u
+#define DMA_CR_ECX_SHIFT                         16
+#define DMA_CR_ECX_WIDTH                         1
+#define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK                           0x20000u
+#define DMA_CR_CX_SHIFT                          17
+#define DMA_CR_CX_WIDTH                          1
+#define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK                          0x1u
+#define DMA_ES_DBE_SHIFT                         0
+#define DMA_ES_DBE_WIDTH                         1
+#define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK                          0x2u
+#define DMA_ES_SBE_SHIFT                         1
+#define DMA_ES_SBE_WIDTH                         1
+#define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK                          0x4u
+#define DMA_ES_SGE_SHIFT                         2
+#define DMA_ES_SGE_WIDTH                         1
+#define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK                          0x8u
+#define DMA_ES_NCE_SHIFT                         3
+#define DMA_ES_NCE_WIDTH                         1
+#define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK                          0x10u
+#define DMA_ES_DOE_SHIFT                         4
+#define DMA_ES_DOE_WIDTH                         1
+#define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK                          0x20u
+#define DMA_ES_DAE_SHIFT                         5
+#define DMA_ES_DAE_WIDTH                         1
+#define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK                          0x40u
+#define DMA_ES_SOE_SHIFT                         6
+#define DMA_ES_SOE_WIDTH                         1
+#define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK                          0x80u
+#define DMA_ES_SAE_SHIFT                         7
+#define DMA_ES_SAE_WIDTH                         1
+#define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK                       0xF00u
+#define DMA_ES_ERRCHN_SHIFT                      8
+#define DMA_ES_ERRCHN_WIDTH                      4
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          0x4000u
+#define DMA_ES_CPE_SHIFT                         14
+#define DMA_ES_CPE_WIDTH                         1
+#define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK                          0x10000u
+#define DMA_ES_ECX_SHIFT                         16
+#define DMA_ES_ECX_WIDTH                         1
+#define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK                          0x80000000u
+#define DMA_ES_VLD_SHIFT                         31
+#define DMA_ES_VLD_WIDTH                         1
+#define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK                        0x1u
+#define DMA_ERQ_ERQ0_SHIFT                       0
+#define DMA_ERQ_ERQ0_WIDTH                       1
+#define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK                        0x2u
+#define DMA_ERQ_ERQ1_SHIFT                       1
+#define DMA_ERQ_ERQ1_WIDTH                       1
+#define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK                        0x4u
+#define DMA_ERQ_ERQ2_SHIFT                       2
+#define DMA_ERQ_ERQ2_WIDTH                       1
+#define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK                        0x8u
+#define DMA_ERQ_ERQ3_SHIFT                       3
+#define DMA_ERQ_ERQ3_WIDTH                       1
+#define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK                        0x10u
+#define DMA_ERQ_ERQ4_SHIFT                       4
+#define DMA_ERQ_ERQ4_WIDTH                       1
+#define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK                        0x20u
+#define DMA_ERQ_ERQ5_SHIFT                       5
+#define DMA_ERQ_ERQ5_WIDTH                       1
+#define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK                        0x40u
+#define DMA_ERQ_ERQ6_SHIFT                       6
+#define DMA_ERQ_ERQ6_WIDTH                       1
+#define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK                        0x80u
+#define DMA_ERQ_ERQ7_SHIFT                       7
+#define DMA_ERQ_ERQ7_WIDTH                       1
+#define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK                        0x100u
+#define DMA_ERQ_ERQ8_SHIFT                       8
+#define DMA_ERQ_ERQ8_WIDTH                       1
+#define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK                        0x200u
+#define DMA_ERQ_ERQ9_SHIFT                       9
+#define DMA_ERQ_ERQ9_WIDTH                       1
+#define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK                       0x400u
+#define DMA_ERQ_ERQ10_SHIFT                      10
+#define DMA_ERQ_ERQ10_WIDTH                      1
+#define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK                       0x800u
+#define DMA_ERQ_ERQ11_SHIFT                      11
+#define DMA_ERQ_ERQ11_WIDTH                      1
+#define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK                       0x1000u
+#define DMA_ERQ_ERQ12_SHIFT                      12
+#define DMA_ERQ_ERQ12_WIDTH                      1
+#define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK                       0x2000u
+#define DMA_ERQ_ERQ13_SHIFT                      13
+#define DMA_ERQ_ERQ13_WIDTH                      1
+#define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK                       0x4000u
+#define DMA_ERQ_ERQ14_SHIFT                      14
+#define DMA_ERQ_ERQ14_WIDTH                      1
+#define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK                       0x8000u
+#define DMA_ERQ_ERQ15_SHIFT                      15
+#define DMA_ERQ_ERQ15_WIDTH                      1
+#define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK                        0x1u
+#define DMA_EEI_EEI0_SHIFT                       0
+#define DMA_EEI_EEI0_WIDTH                       1
+#define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK                        0x2u
+#define DMA_EEI_EEI1_SHIFT                       1
+#define DMA_EEI_EEI1_WIDTH                       1
+#define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK                        0x4u
+#define DMA_EEI_EEI2_SHIFT                       2
+#define DMA_EEI_EEI2_WIDTH                       1
+#define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK                        0x8u
+#define DMA_EEI_EEI3_SHIFT                       3
+#define DMA_EEI_EEI3_WIDTH                       1
+#define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK                        0x10u
+#define DMA_EEI_EEI4_SHIFT                       4
+#define DMA_EEI_EEI4_WIDTH                       1
+#define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK                        0x20u
+#define DMA_EEI_EEI5_SHIFT                       5
+#define DMA_EEI_EEI5_WIDTH                       1
+#define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK                        0x40u
+#define DMA_EEI_EEI6_SHIFT                       6
+#define DMA_EEI_EEI6_WIDTH                       1
+#define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK                        0x80u
+#define DMA_EEI_EEI7_SHIFT                       7
+#define DMA_EEI_EEI7_WIDTH                       1
+#define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK                        0x100u
+#define DMA_EEI_EEI8_SHIFT                       8
+#define DMA_EEI_EEI8_WIDTH                       1
+#define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK                        0x200u
+#define DMA_EEI_EEI9_SHIFT                       9
+#define DMA_EEI_EEI9_WIDTH                       1
+#define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK                       0x400u
+#define DMA_EEI_EEI10_SHIFT                      10
+#define DMA_EEI_EEI10_WIDTH                      1
+#define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK                       0x800u
+#define DMA_EEI_EEI11_SHIFT                      11
+#define DMA_EEI_EEI11_WIDTH                      1
+#define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK                       0x1000u
+#define DMA_EEI_EEI12_SHIFT                      12
+#define DMA_EEI_EEI12_WIDTH                      1
+#define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK                       0x2000u
+#define DMA_EEI_EEI13_SHIFT                      13
+#define DMA_EEI_EEI13_WIDTH                      1
+#define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK                       0x4000u
+#define DMA_EEI_EEI14_SHIFT                      14
+#define DMA_EEI_EEI14_WIDTH                      1
+#define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK                       0x8000u
+#define DMA_EEI_EEI15_SHIFT                      15
+#define DMA_EEI_EEI15_WIDTH                      1
+#define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK                       0xFu
+#define DMA_CEEI_CEEI_SHIFT                      0
+#define DMA_CEEI_CEEI_WIDTH                      4
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       0x40u
+#define DMA_CEEI_CAEE_SHIFT                      6
+#define DMA_CEEI_CAEE_WIDTH                      1
+#define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK                        0x80u
+#define DMA_CEEI_NOP_SHIFT                       7
+#define DMA_CEEI_NOP_WIDTH                       1
+#define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK                       0xFu
+#define DMA_SEEI_SEEI_SHIFT                      0
+#define DMA_SEEI_SEEI_WIDTH                      4
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       0x40u
+#define DMA_SEEI_SAEE_SHIFT                      6
+#define DMA_SEEI_SAEE_WIDTH                      1
+#define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK                        0x80u
+#define DMA_SEEI_NOP_SHIFT                       7
+#define DMA_SEEI_NOP_WIDTH                       1
+#define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK                       0xFu
+#define DMA_CERQ_CERQ_SHIFT                      0
+#define DMA_CERQ_CERQ_WIDTH                      4
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       0x40u
+#define DMA_CERQ_CAER_SHIFT                      6
+#define DMA_CERQ_CAER_WIDTH                      1
+#define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK                        0x80u
+#define DMA_CERQ_NOP_SHIFT                       7
+#define DMA_CERQ_NOP_WIDTH                       1
+#define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK                       0xFu
+#define DMA_SERQ_SERQ_SHIFT                      0
+#define DMA_SERQ_SERQ_WIDTH                      4
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       0x40u
+#define DMA_SERQ_SAER_SHIFT                      6
+#define DMA_SERQ_SAER_WIDTH                      1
+#define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK                        0x80u
+#define DMA_SERQ_NOP_SHIFT                       7
+#define DMA_SERQ_NOP_WIDTH                       1
+#define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK                       0xFu
+#define DMA_CDNE_CDNE_SHIFT                      0
+#define DMA_CDNE_CDNE_WIDTH                      4
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       0x40u
+#define DMA_CDNE_CADN_SHIFT                      6
+#define DMA_CDNE_CADN_WIDTH                      1
+#define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK                        0x80u
+#define DMA_CDNE_NOP_SHIFT                       7
+#define DMA_CDNE_NOP_WIDTH                       1
+#define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK                       0xFu
+#define DMA_SSRT_SSRT_SHIFT                      0
+#define DMA_SSRT_SSRT_WIDTH                      4
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       0x40u
+#define DMA_SSRT_SAST_SHIFT                      6
+#define DMA_SSRT_SAST_WIDTH                      1
+#define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK                        0x80u
+#define DMA_SSRT_NOP_SHIFT                       7
+#define DMA_SSRT_NOP_WIDTH                       1
+#define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK                       0xFu
+#define DMA_CERR_CERR_SHIFT                      0
+#define DMA_CERR_CERR_WIDTH                      4
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       0x40u
+#define DMA_CERR_CAEI_SHIFT                      6
+#define DMA_CERR_CAEI_WIDTH                      1
+#define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK                        0x80u
+#define DMA_CERR_NOP_SHIFT                       7
+#define DMA_CERR_NOP_WIDTH                       1
+#define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK                       0xFu
+#define DMA_CINT_CINT_SHIFT                      0
+#define DMA_CINT_CINT_WIDTH                      4
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       0x40u
+#define DMA_CINT_CAIR_SHIFT                      6
+#define DMA_CINT_CAIR_WIDTH                      1
+#define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK                        0x80u
+#define DMA_CINT_NOP_SHIFT                       7
+#define DMA_CINT_NOP_WIDTH                       1
+#define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK                        0x1u
+#define DMA_INT_INT0_SHIFT                       0
+#define DMA_INT_INT0_WIDTH                       1
+#define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK                        0x2u
+#define DMA_INT_INT1_SHIFT                       1
+#define DMA_INT_INT1_WIDTH                       1
+#define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK                        0x4u
+#define DMA_INT_INT2_SHIFT                       2
+#define DMA_INT_INT2_WIDTH                       1
+#define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK                        0x8u
+#define DMA_INT_INT3_SHIFT                       3
+#define DMA_INT_INT3_WIDTH                       1
+#define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK                        0x10u
+#define DMA_INT_INT4_SHIFT                       4
+#define DMA_INT_INT4_WIDTH                       1
+#define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK                        0x20u
+#define DMA_INT_INT5_SHIFT                       5
+#define DMA_INT_INT5_WIDTH                       1
+#define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK                        0x40u
+#define DMA_INT_INT6_SHIFT                       6
+#define DMA_INT_INT6_WIDTH                       1
+#define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK                        0x80u
+#define DMA_INT_INT7_SHIFT                       7
+#define DMA_INT_INT7_WIDTH                       1
+#define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK                        0x100u
+#define DMA_INT_INT8_SHIFT                       8
+#define DMA_INT_INT8_WIDTH                       1
+#define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK                        0x200u
+#define DMA_INT_INT9_SHIFT                       9
+#define DMA_INT_INT9_WIDTH                       1
+#define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK                       0x400u
+#define DMA_INT_INT10_SHIFT                      10
+#define DMA_INT_INT10_WIDTH                      1
+#define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK                       0x800u
+#define DMA_INT_INT11_SHIFT                      11
+#define DMA_INT_INT11_WIDTH                      1
+#define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK                       0x1000u
+#define DMA_INT_INT12_SHIFT                      12
+#define DMA_INT_INT12_WIDTH                      1
+#define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK                       0x2000u
+#define DMA_INT_INT13_SHIFT                      13
+#define DMA_INT_INT13_WIDTH                      1
+#define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK                       0x4000u
+#define DMA_INT_INT14_SHIFT                      14
+#define DMA_INT_INT14_WIDTH                      1
+#define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK                       0x8000u
+#define DMA_INT_INT15_SHIFT                      15
+#define DMA_INT_INT15_WIDTH                      1
+#define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK                        0x1u
+#define DMA_ERR_ERR0_SHIFT                       0
+#define DMA_ERR_ERR0_WIDTH                       1
+#define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK                        0x2u
+#define DMA_ERR_ERR1_SHIFT                       1
+#define DMA_ERR_ERR1_WIDTH                       1
+#define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK                        0x4u
+#define DMA_ERR_ERR2_SHIFT                       2
+#define DMA_ERR_ERR2_WIDTH                       1
+#define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK                        0x8u
+#define DMA_ERR_ERR3_SHIFT                       3
+#define DMA_ERR_ERR3_WIDTH                       1
+#define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK                        0x10u
+#define DMA_ERR_ERR4_SHIFT                       4
+#define DMA_ERR_ERR4_WIDTH                       1
+#define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK                        0x20u
+#define DMA_ERR_ERR5_SHIFT                       5
+#define DMA_ERR_ERR5_WIDTH                       1
+#define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK                        0x40u
+#define DMA_ERR_ERR6_SHIFT                       6
+#define DMA_ERR_ERR6_WIDTH                       1
+#define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK                        0x80u
+#define DMA_ERR_ERR7_SHIFT                       7
+#define DMA_ERR_ERR7_WIDTH                       1
+#define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK                        0x100u
+#define DMA_ERR_ERR8_SHIFT                       8
+#define DMA_ERR_ERR8_WIDTH                       1
+#define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK                        0x200u
+#define DMA_ERR_ERR9_SHIFT                       9
+#define DMA_ERR_ERR9_WIDTH                       1
+#define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK                       0x400u
+#define DMA_ERR_ERR10_SHIFT                      10
+#define DMA_ERR_ERR10_WIDTH                      1
+#define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK                       0x800u
+#define DMA_ERR_ERR11_SHIFT                      11
+#define DMA_ERR_ERR11_WIDTH                      1
+#define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK                       0x1000u
+#define DMA_ERR_ERR12_SHIFT                      12
+#define DMA_ERR_ERR12_WIDTH                      1
+#define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK                       0x2000u
+#define DMA_ERR_ERR13_SHIFT                      13
+#define DMA_ERR_ERR13_WIDTH                      1
+#define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK                       0x4000u
+#define DMA_ERR_ERR14_SHIFT                      14
+#define DMA_ERR_ERR14_WIDTH                      1
+#define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK                       0x8000u
+#define DMA_ERR_ERR15_SHIFT                      15
+#define DMA_ERR_ERR15_WIDTH                      1
+#define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK                        0x1u
+#define DMA_HRS_HRS0_SHIFT                       0
+#define DMA_HRS_HRS0_WIDTH                       1
+#define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK                        0x2u
+#define DMA_HRS_HRS1_SHIFT                       1
+#define DMA_HRS_HRS1_WIDTH                       1
+#define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK                        0x4u
+#define DMA_HRS_HRS2_SHIFT                       2
+#define DMA_HRS_HRS2_WIDTH                       1
+#define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK                        0x8u
+#define DMA_HRS_HRS3_SHIFT                       3
+#define DMA_HRS_HRS3_WIDTH                       1
+#define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK                        0x10u
+#define DMA_HRS_HRS4_SHIFT                       4
+#define DMA_HRS_HRS4_WIDTH                       1
+#define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK                        0x20u
+#define DMA_HRS_HRS5_SHIFT                       5
+#define DMA_HRS_HRS5_WIDTH                       1
+#define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK                        0x40u
+#define DMA_HRS_HRS6_SHIFT                       6
+#define DMA_HRS_HRS6_WIDTH                       1
+#define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK                        0x80u
+#define DMA_HRS_HRS7_SHIFT                       7
+#define DMA_HRS_HRS7_WIDTH                       1
+#define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK                        0x100u
+#define DMA_HRS_HRS8_SHIFT                       8
+#define DMA_HRS_HRS8_WIDTH                       1
+#define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK                        0x200u
+#define DMA_HRS_HRS9_SHIFT                       9
+#define DMA_HRS_HRS9_WIDTH                       1
+#define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK                       0x400u
+#define DMA_HRS_HRS10_SHIFT                      10
+#define DMA_HRS_HRS10_WIDTH                      1
+#define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK                       0x800u
+#define DMA_HRS_HRS11_SHIFT                      11
+#define DMA_HRS_HRS11_WIDTH                      1
+#define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK                       0x1000u
+#define DMA_HRS_HRS12_SHIFT                      12
+#define DMA_HRS_HRS12_WIDTH                      1
+#define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK                       0x2000u
+#define DMA_HRS_HRS13_SHIFT                      13
+#define DMA_HRS_HRS13_WIDTH                      1
+#define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK                       0x4000u
+#define DMA_HRS_HRS14_SHIFT                      14
+#define DMA_HRS_HRS14_WIDTH                      1
+#define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK                       0x8000u
+#define DMA_HRS_HRS15_SHIFT                      15
+#define DMA_HRS_HRS15_WIDTH                      1
+#define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT                  0
+#define DMA_DCHPRI3_CHPRI_WIDTH                  4
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     0x40u
+#define DMA_DCHPRI3_DPA_SHIFT                    6
+#define DMA_DCHPRI3_DPA_WIDTH                    1
+#define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_DPA_SHIFT))&DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK                     0x80u
+#define DMA_DCHPRI3_ECP_SHIFT                    7
+#define DMA_DCHPRI3_ECP_WIDTH                    1
+#define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_ECP_SHIFT))&DMA_DCHPRI3_ECP_MASK)
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT                  0
+#define DMA_DCHPRI2_CHPRI_WIDTH                  4
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     0x40u
+#define DMA_DCHPRI2_DPA_SHIFT                    6
+#define DMA_DCHPRI2_DPA_WIDTH                    1
+#define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_DPA_SHIFT))&DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK                     0x80u
+#define DMA_DCHPRI2_ECP_SHIFT                    7
+#define DMA_DCHPRI2_ECP_WIDTH                    1
+#define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_ECP_SHIFT))&DMA_DCHPRI2_ECP_MASK)
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT                  0
+#define DMA_DCHPRI1_CHPRI_WIDTH                  4
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     0x40u
+#define DMA_DCHPRI1_DPA_SHIFT                    6
+#define DMA_DCHPRI1_DPA_WIDTH                    1
+#define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_DPA_SHIFT))&DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK                     0x80u
+#define DMA_DCHPRI1_ECP_SHIFT                    7
+#define DMA_DCHPRI1_ECP_WIDTH                    1
+#define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_ECP_SHIFT))&DMA_DCHPRI1_ECP_MASK)
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT                  0
+#define DMA_DCHPRI0_CHPRI_WIDTH                  4
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     0x40u
+#define DMA_DCHPRI0_DPA_SHIFT                    6
+#define DMA_DCHPRI0_DPA_WIDTH                    1
+#define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_DPA_SHIFT))&DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK                     0x80u
+#define DMA_DCHPRI0_ECP_SHIFT                    7
+#define DMA_DCHPRI0_ECP_WIDTH                    1
+#define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_ECP_SHIFT))&DMA_DCHPRI0_ECP_MASK)
+/* DCHPRI7 Bit Fields */
+#define DMA_DCHPRI7_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI7_CHPRI_SHIFT                  0
+#define DMA_DCHPRI7_CHPRI_WIDTH                  4
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     0x40u
+#define DMA_DCHPRI7_DPA_SHIFT                    6
+#define DMA_DCHPRI7_DPA_WIDTH                    1
+#define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_DPA_SHIFT))&DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK                     0x80u
+#define DMA_DCHPRI7_ECP_SHIFT                    7
+#define DMA_DCHPRI7_ECP_WIDTH                    1
+#define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_ECP_SHIFT))&DMA_DCHPRI7_ECP_MASK)
+/* DCHPRI6 Bit Fields */
+#define DMA_DCHPRI6_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI6_CHPRI_SHIFT                  0
+#define DMA_DCHPRI6_CHPRI_WIDTH                  4
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     0x40u
+#define DMA_DCHPRI6_DPA_SHIFT                    6
+#define DMA_DCHPRI6_DPA_WIDTH                    1
+#define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_DPA_SHIFT))&DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK                     0x80u
+#define DMA_DCHPRI6_ECP_SHIFT                    7
+#define DMA_DCHPRI6_ECP_WIDTH                    1
+#define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_ECP_SHIFT))&DMA_DCHPRI6_ECP_MASK)
+/* DCHPRI5 Bit Fields */
+#define DMA_DCHPRI5_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI5_CHPRI_SHIFT                  0
+#define DMA_DCHPRI5_CHPRI_WIDTH                  4
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     0x40u
+#define DMA_DCHPRI5_DPA_SHIFT                    6
+#define DMA_DCHPRI5_DPA_WIDTH                    1
+#define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_DPA_SHIFT))&DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK                     0x80u
+#define DMA_DCHPRI5_ECP_SHIFT                    7
+#define DMA_DCHPRI5_ECP_WIDTH                    1
+#define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_ECP_SHIFT))&DMA_DCHPRI5_ECP_MASK)
+/* DCHPRI4 Bit Fields */
+#define DMA_DCHPRI4_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI4_CHPRI_SHIFT                  0
+#define DMA_DCHPRI4_CHPRI_WIDTH                  4
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     0x40u
+#define DMA_DCHPRI4_DPA_SHIFT                    6
+#define DMA_DCHPRI4_DPA_WIDTH                    1
+#define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_DPA_SHIFT))&DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK                     0x80u
+#define DMA_DCHPRI4_ECP_SHIFT                    7
+#define DMA_DCHPRI4_ECP_WIDTH                    1
+#define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_ECP_SHIFT))&DMA_DCHPRI4_ECP_MASK)
+/* DCHPRI11 Bit Fields */
+#define DMA_DCHPRI11_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI11_CHPRI_SHIFT                 0
+#define DMA_DCHPRI11_CHPRI_WIDTH                 4
+#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK                    0x40u
+#define DMA_DCHPRI11_DPA_SHIFT                   6
+#define DMA_DCHPRI11_DPA_WIDTH                   1
+#define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_DPA_SHIFT))&DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_ECP_MASK                    0x80u
+#define DMA_DCHPRI11_ECP_SHIFT                   7
+#define DMA_DCHPRI11_ECP_WIDTH                   1
+#define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_ECP_SHIFT))&DMA_DCHPRI11_ECP_MASK)
+/* DCHPRI10 Bit Fields */
+#define DMA_DCHPRI10_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI10_CHPRI_SHIFT                 0
+#define DMA_DCHPRI10_CHPRI_WIDTH                 4
+#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK                    0x40u
+#define DMA_DCHPRI10_DPA_SHIFT                   6
+#define DMA_DCHPRI10_DPA_WIDTH                   1
+#define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_DPA_SHIFT))&DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_ECP_MASK                    0x80u
+#define DMA_DCHPRI10_ECP_SHIFT                   7
+#define DMA_DCHPRI10_ECP_WIDTH                   1
+#define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_ECP_SHIFT))&DMA_DCHPRI10_ECP_MASK)
+/* DCHPRI9 Bit Fields */
+#define DMA_DCHPRI9_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI9_CHPRI_SHIFT                  0
+#define DMA_DCHPRI9_CHPRI_WIDTH                  4
+#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK                     0x40u
+#define DMA_DCHPRI9_DPA_SHIFT                    6
+#define DMA_DCHPRI9_DPA_WIDTH                    1
+#define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_DPA_SHIFT))&DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_ECP_MASK                     0x80u
+#define DMA_DCHPRI9_ECP_SHIFT                    7
+#define DMA_DCHPRI9_ECP_WIDTH                    1
+#define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_ECP_SHIFT))&DMA_DCHPRI9_ECP_MASK)
+/* DCHPRI8 Bit Fields */
+#define DMA_DCHPRI8_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI8_CHPRI_SHIFT                  0
+#define DMA_DCHPRI8_CHPRI_WIDTH                  4
+#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK                     0x40u
+#define DMA_DCHPRI8_DPA_SHIFT                    6
+#define DMA_DCHPRI8_DPA_WIDTH                    1
+#define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_DPA_SHIFT))&DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_ECP_MASK                     0x80u
+#define DMA_DCHPRI8_ECP_SHIFT                    7
+#define DMA_DCHPRI8_ECP_WIDTH                    1
+#define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_ECP_SHIFT))&DMA_DCHPRI8_ECP_MASK)
+/* DCHPRI15 Bit Fields */
+#define DMA_DCHPRI15_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI15_CHPRI_SHIFT                 0
+#define DMA_DCHPRI15_CHPRI_WIDTH                 4
+#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK                    0x40u
+#define DMA_DCHPRI15_DPA_SHIFT                   6
+#define DMA_DCHPRI15_DPA_WIDTH                   1
+#define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_DPA_SHIFT))&DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_ECP_MASK                    0x80u
+#define DMA_DCHPRI15_ECP_SHIFT                   7
+#define DMA_DCHPRI15_ECP_WIDTH                   1
+#define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_ECP_SHIFT))&DMA_DCHPRI15_ECP_MASK)
+/* DCHPRI14 Bit Fields */
+#define DMA_DCHPRI14_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI14_CHPRI_SHIFT                 0
+#define DMA_DCHPRI14_CHPRI_WIDTH                 4
+#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK                    0x40u
+#define DMA_DCHPRI14_DPA_SHIFT                   6
+#define DMA_DCHPRI14_DPA_WIDTH                   1
+#define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_DPA_SHIFT))&DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_ECP_MASK                    0x80u
+#define DMA_DCHPRI14_ECP_SHIFT                   7
+#define DMA_DCHPRI14_ECP_WIDTH                   1
+#define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_ECP_SHIFT))&DMA_DCHPRI14_ECP_MASK)
+/* DCHPRI13 Bit Fields */
+#define DMA_DCHPRI13_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI13_CHPRI_SHIFT                 0
+#define DMA_DCHPRI13_CHPRI_WIDTH                 4
+#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK                    0x40u
+#define DMA_DCHPRI13_DPA_SHIFT                   6
+#define DMA_DCHPRI13_DPA_WIDTH                   1
+#define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_DPA_SHIFT))&DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_ECP_MASK                    0x80u
+#define DMA_DCHPRI13_ECP_SHIFT                   7
+#define DMA_DCHPRI13_ECP_WIDTH                   1
+#define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_ECP_SHIFT))&DMA_DCHPRI13_ECP_MASK)
+/* DCHPRI12 Bit Fields */
+#define DMA_DCHPRI12_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI12_CHPRI_SHIFT                 0
+#define DMA_DCHPRI12_CHPRI_WIDTH                 4
+#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK                    0x40u
+#define DMA_DCHPRI12_DPA_SHIFT                   6
+#define DMA_DCHPRI12_DPA_WIDTH                   1
+#define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_DPA_SHIFT))&DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_ECP_MASK                    0x80u
+#define DMA_DCHPRI12_ECP_SHIFT                   7
+#define DMA_DCHPRI12_ECP_WIDTH                   1
+#define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_ECP_SHIFT))&DMA_DCHPRI12_ECP_MASK)
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK                     0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT                    0
+#define DMA_SADDR_SADDR_WIDTH                    32
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK                       0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT                      0
+#define DMA_SOFF_SOFF_WIDTH                      16
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK                      0x7u
+#define DMA_ATTR_DSIZE_SHIFT                     0
+#define DMA_ATTR_DSIZE_WIDTH                     3
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       0xF8u
+#define DMA_ATTR_DMOD_SHIFT                      3
+#define DMA_ATTR_DMOD_WIDTH                      5
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      0x700u
+#define DMA_ATTR_SSIZE_SHIFT                     8
+#define DMA_ATTR_SSIZE_WIDTH                     3
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       0xF800u
+#define DMA_ATTR_SMOD_SHIFT                      11
+#define DMA_ATTR_SMOD_WIDTH                      5
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             0
+#define DMA_NBYTES_MLNO_NBYTES_WIDTH             32
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          0
+#define DMA_NBYTES_MLOFFNO_NBYTES_WIDTH          30
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           30
+#define DMA_NBYTES_MLOFFNO_DMLOE_WIDTH           1
+#define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           31
+#define DMA_NBYTES_MLOFFNO_SMLOE_WIDTH           1
+#define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         0
+#define DMA_NBYTES_MLOFFYES_NBYTES_WIDTH         10
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          10
+#define DMA_NBYTES_MLOFFYES_MLOFF_WIDTH          20
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          30
+#define DMA_NBYTES_MLOFFYES_DMLOE_WIDTH          1
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          31
+#define DMA_NBYTES_MLOFFYES_SMLOE_WIDTH          1
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK                     0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT                    0
+#define DMA_SLAST_SLAST_WIDTH                    32
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK                     0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT                    0
+#define DMA_DADDR_DADDR_WIDTH                    32
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK                       0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT                      0
+#define DMA_DOFF_DOFF_WIDTH                      16
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK             0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT            0
+#define DMA_CITER_ELINKNO_CITER_WIDTH            15
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            15
+#define DMA_CITER_ELINKNO_ELINK_WIDTH            1
+#define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_ELINK_SHIFT))&DMA_CITER_ELINKNO_ELINK_MASK)
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK            0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT           0
+#define DMA_CITER_ELINKYES_CITER_WIDTH           9
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_CITER_ELINKYES_LINKCH_WIDTH          4
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           15
+#define DMA_CITER_ELINKYES_ELINK_WIDTH           1
+#define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_ELINK_SHIFT))&DMA_CITER_ELINKYES_ELINK_MASK)
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             0
+#define DMA_DLAST_SGA_DLASTSGA_WIDTH             32
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK                       0x1u
+#define DMA_CSR_START_SHIFT                      0
+#define DMA_CSR_START_WIDTH                      1
+#define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_CSR_START_SHIFT))&DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK                    0x2u
+#define DMA_CSR_INTMAJOR_SHIFT                   1
+#define DMA_CSR_INTMAJOR_WIDTH                   1
+#define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTMAJOR_SHIFT))&DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK                     0x4u
+#define DMA_CSR_INTHALF_SHIFT                    2
+#define DMA_CSR_INTHALF_WIDTH                    1
+#define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTHALF_SHIFT))&DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK                        0x8u
+#define DMA_CSR_DREQ_SHIFT                       3
+#define DMA_CSR_DREQ_WIDTH                       1
+#define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DREQ_SHIFT))&DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK                         0x10u
+#define DMA_CSR_ESG_SHIFT                        4
+#define DMA_CSR_ESG_WIDTH                        1
+#define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ESG_SHIFT))&DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK                  0x20u
+#define DMA_CSR_MAJORELINK_SHIFT                 5
+#define DMA_CSR_MAJORELINK_WIDTH                 1
+#define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORELINK_SHIFT))&DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK                      0x40u
+#define DMA_CSR_ACTIVE_SHIFT                     6
+#define DMA_CSR_ACTIVE_WIDTH                     1
+#define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ACTIVE_SHIFT))&DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK                        0x80u
+#define DMA_CSR_DONE_SHIFT                       7
+#define DMA_CSR_DONE_WIDTH                       1
+#define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DONE_SHIFT))&DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK                 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT                8
+#define DMA_CSR_MAJORLINKCH_WIDTH                4
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         0xC000u
+#define DMA_CSR_BWC_SHIFT                        14
+#define DMA_CSR_BWC_WIDTH                        2
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK             0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT            0
+#define DMA_BITER_ELINKNO_BITER_WIDTH            15
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            15
+#define DMA_BITER_ELINKNO_ELINK_WIDTH            1
+#define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_ELINK_SHIFT))&DMA_BITER_ELINKNO_ELINK_MASK)
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK            0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT           0
+#define DMA_BITER_ELINKYES_BITER_WIDTH           9
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_BITER_ELINKYES_LINKCH_WIDTH          4
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           15
+#define DMA_BITER_ELINKYES_ELINK_WIDTH           1
+#define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_ELINK_SHIFT))&DMA_BITER_ELINKYES_ELINK_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR                             (DMA0)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_CR                                   DMA_CR_REG(DMA0)
+#define DMA_ES                                   DMA_ES_REG(DMA0)
+#define DMA_ERQ                                  DMA_ERQ_REG(DMA0)
+#define DMA_EEI                                  DMA_EEI_REG(DMA0)
+#define DMA_CEEI                                 DMA_CEEI_REG(DMA0)
+#define DMA_SEEI                                 DMA_SEEI_REG(DMA0)
+#define DMA_CERQ                                 DMA_CERQ_REG(DMA0)
+#define DMA_SERQ                                 DMA_SERQ_REG(DMA0)
+#define DMA_CDNE                                 DMA_CDNE_REG(DMA0)
+#define DMA_SSRT                                 DMA_SSRT_REG(DMA0)
+#define DMA_CERR                                 DMA_CERR_REG(DMA0)
+#define DMA_CINT                                 DMA_CINT_REG(DMA0)
+#define DMA_INT                                  DMA_INT_REG(DMA0)
+#define DMA_ERR                                  DMA_ERR_REG(DMA0)
+#define DMA_HRS                                  DMA_HRS_REG(DMA0)
+#define DMA_DCHPRI3                              DMA_DCHPRI3_REG(DMA0)
+#define DMA_DCHPRI2                              DMA_DCHPRI2_REG(DMA0)
+#define DMA_DCHPRI1                              DMA_DCHPRI1_REG(DMA0)
+#define DMA_DCHPRI0                              DMA_DCHPRI0_REG(DMA0)
+#define DMA_DCHPRI7                              DMA_DCHPRI7_REG(DMA0)
+#define DMA_DCHPRI6                              DMA_DCHPRI6_REG(DMA0)
+#define DMA_DCHPRI5                              DMA_DCHPRI5_REG(DMA0)
+#define DMA_DCHPRI4                              DMA_DCHPRI4_REG(DMA0)
+#define DMA_DCHPRI11                             DMA_DCHPRI11_REG(DMA0)
+#define DMA_DCHPRI10                             DMA_DCHPRI10_REG(DMA0)
+#define DMA_DCHPRI9                              DMA_DCHPRI9_REG(DMA0)
+#define DMA_DCHPRI8                              DMA_DCHPRI8_REG(DMA0)
+#define DMA_DCHPRI15                             DMA_DCHPRI15_REG(DMA0)
+#define DMA_DCHPRI14                             DMA_DCHPRI14_REG(DMA0)
+#define DMA_DCHPRI13                             DMA_DCHPRI13_REG(DMA0)
+#define DMA_DCHPRI12                             DMA_DCHPRI12_REG(DMA0)
+#define DMA_TCD0_SADDR                           DMA_SADDR_REG(DMA0,0)
+#define DMA_TCD0_SOFF                            DMA_SOFF_REG(DMA0,0)
+#define DMA_TCD0_ATTR                            DMA_ATTR_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,0)
+#define DMA_TCD0_SLAST                           DMA_SLAST_REG(DMA0,0)
+#define DMA_TCD0_DADDR                           DMA_DADDR_REG(DMA0,0)
+#define DMA_TCD0_DOFF                            DMA_DOFF_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD0_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,0)
+#define DMA_TCD0_CSR                             DMA_CSR_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD1_SADDR                           DMA_SADDR_REG(DMA0,1)
+#define DMA_TCD1_SOFF                            DMA_SOFF_REG(DMA0,1)
+#define DMA_TCD1_ATTR                            DMA_ATTR_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,1)
+#define DMA_TCD1_SLAST                           DMA_SLAST_REG(DMA0,1)
+#define DMA_TCD1_DADDR                           DMA_DADDR_REG(DMA0,1)
+#define DMA_TCD1_DOFF                            DMA_DOFF_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD1_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,1)
+#define DMA_TCD1_CSR                             DMA_CSR_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD2_SADDR                           DMA_SADDR_REG(DMA0,2)
+#define DMA_TCD2_SOFF                            DMA_SOFF_REG(DMA0,2)
+#define DMA_TCD2_ATTR                            DMA_ATTR_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,2)
+#define DMA_TCD2_SLAST                           DMA_SLAST_REG(DMA0,2)
+#define DMA_TCD2_DADDR                           DMA_DADDR_REG(DMA0,2)
+#define DMA_TCD2_DOFF                            DMA_DOFF_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD2_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,2)
+#define DMA_TCD2_CSR                             DMA_CSR_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD3_SADDR                           DMA_SADDR_REG(DMA0,3)
+#define DMA_TCD3_SOFF                            DMA_SOFF_REG(DMA0,3)
+#define DMA_TCD3_ATTR                            DMA_ATTR_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,3)
+#define DMA_TCD3_SLAST                           DMA_SLAST_REG(DMA0,3)
+#define DMA_TCD3_DADDR                           DMA_DADDR_REG(DMA0,3)
+#define DMA_TCD3_DOFF                            DMA_DOFF_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD3_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,3)
+#define DMA_TCD3_CSR                             DMA_CSR_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD4_SADDR                           DMA_SADDR_REG(DMA0,4)
+#define DMA_TCD4_SOFF                            DMA_SOFF_REG(DMA0,4)
+#define DMA_TCD4_ATTR                            DMA_ATTR_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,4)
+#define DMA_TCD4_SLAST                           DMA_SLAST_REG(DMA0,4)
+#define DMA_TCD4_DADDR                           DMA_DADDR_REG(DMA0,4)
+#define DMA_TCD4_DOFF                            DMA_DOFF_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD4_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,4)
+#define DMA_TCD4_CSR                             DMA_CSR_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD5_SADDR                           DMA_SADDR_REG(DMA0,5)
+#define DMA_TCD5_SOFF                            DMA_SOFF_REG(DMA0,5)
+#define DMA_TCD5_ATTR                            DMA_ATTR_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,5)
+#define DMA_TCD5_SLAST                           DMA_SLAST_REG(DMA0,5)
+#define DMA_TCD5_DADDR                           DMA_DADDR_REG(DMA0,5)
+#define DMA_TCD5_DOFF                            DMA_DOFF_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD5_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,5)
+#define DMA_TCD5_CSR                             DMA_CSR_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD6_SADDR                           DMA_SADDR_REG(DMA0,6)
+#define DMA_TCD6_SOFF                            DMA_SOFF_REG(DMA0,6)
+#define DMA_TCD6_ATTR                            DMA_ATTR_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,6)
+#define DMA_TCD6_SLAST                           DMA_SLAST_REG(DMA0,6)
+#define DMA_TCD6_DADDR                           DMA_DADDR_REG(DMA0,6)
+#define DMA_TCD6_DOFF                            DMA_DOFF_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD6_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,6)
+#define DMA_TCD6_CSR                             DMA_CSR_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD7_SADDR                           DMA_SADDR_REG(DMA0,7)
+#define DMA_TCD7_SOFF                            DMA_SOFF_REG(DMA0,7)
+#define DMA_TCD7_ATTR                            DMA_ATTR_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,7)
+#define DMA_TCD7_SLAST                           DMA_SLAST_REG(DMA0,7)
+#define DMA_TCD7_DADDR                           DMA_DADDR_REG(DMA0,7)
+#define DMA_TCD7_DOFF                            DMA_DOFF_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD7_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,7)
+#define DMA_TCD7_CSR                             DMA_CSR_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD8_SADDR                           DMA_SADDR_REG(DMA0,8)
+#define DMA_TCD8_SOFF                            DMA_SOFF_REG(DMA0,8)
+#define DMA_TCD8_ATTR                            DMA_ATTR_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,8)
+#define DMA_TCD8_SLAST                           DMA_SLAST_REG(DMA0,8)
+#define DMA_TCD8_DADDR                           DMA_DADDR_REG(DMA0,8)
+#define DMA_TCD8_DOFF                            DMA_DOFF_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD8_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,8)
+#define DMA_TCD8_CSR                             DMA_CSR_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD9_SADDR                           DMA_SADDR_REG(DMA0,9)
+#define DMA_TCD9_SOFF                            DMA_SOFF_REG(DMA0,9)
+#define DMA_TCD9_ATTR                            DMA_ATTR_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,9)
+#define DMA_TCD9_SLAST                           DMA_SLAST_REG(DMA0,9)
+#define DMA_TCD9_DADDR                           DMA_DADDR_REG(DMA0,9)
+#define DMA_TCD9_DOFF                            DMA_DOFF_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD9_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,9)
+#define DMA_TCD9_CSR                             DMA_CSR_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD10_SADDR                          DMA_SADDR_REG(DMA0,10)
+#define DMA_TCD10_SOFF                           DMA_SOFF_REG(DMA0,10)
+#define DMA_TCD10_ATTR                           DMA_ATTR_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,10)
+#define DMA_TCD10_SLAST                          DMA_SLAST_REG(DMA0,10)
+#define DMA_TCD10_DADDR                          DMA_DADDR_REG(DMA0,10)
+#define DMA_TCD10_DOFF                           DMA_DOFF_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD10_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,10)
+#define DMA_TCD10_CSR                            DMA_CSR_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD11_SADDR                          DMA_SADDR_REG(DMA0,11)
+#define DMA_TCD11_SOFF                           DMA_SOFF_REG(DMA0,11)
+#define DMA_TCD11_ATTR                           DMA_ATTR_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,11)
+#define DMA_TCD11_SLAST                          DMA_SLAST_REG(DMA0,11)
+#define DMA_TCD11_DADDR                          DMA_DADDR_REG(DMA0,11)
+#define DMA_TCD11_DOFF                           DMA_DOFF_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD11_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,11)
+#define DMA_TCD11_CSR                            DMA_CSR_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD12_SADDR                          DMA_SADDR_REG(DMA0,12)
+#define DMA_TCD12_SOFF                           DMA_SOFF_REG(DMA0,12)
+#define DMA_TCD12_ATTR                           DMA_ATTR_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,12)
+#define DMA_TCD12_SLAST                          DMA_SLAST_REG(DMA0,12)
+#define DMA_TCD12_DADDR                          DMA_DADDR_REG(DMA0,12)
+#define DMA_TCD12_DOFF                           DMA_DOFF_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD12_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,12)
+#define DMA_TCD12_CSR                            DMA_CSR_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD13_SADDR                          DMA_SADDR_REG(DMA0,13)
+#define DMA_TCD13_SOFF                           DMA_SOFF_REG(DMA0,13)
+#define DMA_TCD13_ATTR                           DMA_ATTR_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,13)
+#define DMA_TCD13_SLAST                          DMA_SLAST_REG(DMA0,13)
+#define DMA_TCD13_DADDR                          DMA_DADDR_REG(DMA0,13)
+#define DMA_TCD13_DOFF                           DMA_DOFF_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD13_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,13)
+#define DMA_TCD13_CSR                            DMA_CSR_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD14_SADDR                          DMA_SADDR_REG(DMA0,14)
+#define DMA_TCD14_SOFF                           DMA_SOFF_REG(DMA0,14)
+#define DMA_TCD14_ATTR                           DMA_ATTR_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,14)
+#define DMA_TCD14_SLAST                          DMA_SLAST_REG(DMA0,14)
+#define DMA_TCD14_DADDR                          DMA_DADDR_REG(DMA0,14)
+#define DMA_TCD14_DOFF                           DMA_DOFF_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD14_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,14)
+#define DMA_TCD14_CSR                            DMA_CSR_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD15_SADDR                          DMA_SADDR_REG(DMA0,15)
+#define DMA_TCD15_SOFF                           DMA_SOFF_REG(DMA0,15)
+#define DMA_TCD15_ATTR                           DMA_ATTR_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,15)
+#define DMA_TCD15_SLAST                          DMA_SLAST_REG(DMA0,15)
+#define DMA_TCD15_DADDR                          DMA_DADDR_REG(DMA0,15)
+#define DMA_TCD15_DOFF                           DMA_DOFF_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,15)
+#define DMA_TCD15_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,15)
+#define DMA_TCD15_CSR                            DMA_CSR_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,15)
+
+/* DMA - Register array accessors */
+#define DMA_SADDR(index)                         DMA_SADDR_REG(DMA0,index)
+#define DMA_SOFF(index)                          DMA_SOFF_REG(DMA0,index)
+#define DMA_ATTR(index)                          DMA_ATTR_REG(DMA0,index)
+#define DMA_NBYTES_MLNO(index)                   DMA_NBYTES_MLNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFNO(index)                DMA_NBYTES_MLOFFNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFYES(index)               DMA_NBYTES_MLOFFYES_REG(DMA0,index)
+#define DMA_SLAST(index)                         DMA_SLAST_REG(DMA0,index)
+#define DMA_DADDR(index)                         DMA_DADDR_REG(DMA0,index)
+#define DMA_DOFF(index)                          DMA_DOFF_REG(DMA0,index)
+#define DMA_CITER_ELINKNO(index)                 DMA_CITER_ELINKNO_REG(DMA0,index)
+#define DMA_CITER_ELINKYES(index)                DMA_CITER_ELINKYES_REG(DMA0,index)
+#define DMA_DLAST_SGA(index)                     DMA_DLAST_SGA_REG(DMA0,index)
+#define DMA_CSR(index)                           DMA_CSR_REG(DMA0,index)
+#define DMA_BITER_ELINKNO(index)                 DMA_BITER_ELINKNO_REG(DMA0,index)
+#define DMA_BITER_ELINKYES(index)                DMA_BITER_ELINKYES_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[16];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index)             ((base)->CHCFG[index])
+#define DMAMUX_CHCFG_COUNT                       16
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT                0
+#define DMAMUX_CHCFG_SOURCE_WIDTH                6
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT                  6
+#define DMAMUX_CHCFG_TRIG_WIDTH                  1
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT                  7
+#define DMAMUX_CHCFG_ENBL_WIDTH                  1
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE                              (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
+#define DMAMUX_BASE_PTR                          (DMAMUX)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { DMAMUX }
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX */
+#define DMAMUX_CHCFG0                            DMAMUX_CHCFG_REG(DMAMUX,0)
+#define DMAMUX_CHCFG1                            DMAMUX_CHCFG_REG(DMAMUX,1)
+#define DMAMUX_CHCFG2                            DMAMUX_CHCFG_REG(DMAMUX,2)
+#define DMAMUX_CHCFG3                            DMAMUX_CHCFG_REG(DMAMUX,3)
+#define DMAMUX_CHCFG4                            DMAMUX_CHCFG_REG(DMAMUX,4)
+#define DMAMUX_CHCFG5                            DMAMUX_CHCFG_REG(DMAMUX,5)
+#define DMAMUX_CHCFG6                            DMAMUX_CHCFG_REG(DMAMUX,6)
+#define DMAMUX_CHCFG7                            DMAMUX_CHCFG_REG(DMAMUX,7)
+#define DMAMUX_CHCFG8                            DMAMUX_CHCFG_REG(DMAMUX,8)
+#define DMAMUX_CHCFG9                            DMAMUX_CHCFG_REG(DMAMUX,9)
+#define DMAMUX_CHCFG10                           DMAMUX_CHCFG_REG(DMAMUX,10)
+#define DMAMUX_CHCFG11                           DMAMUX_CHCFG_REG(DMAMUX,11)
+#define DMAMUX_CHCFG12                           DMAMUX_CHCFG_REG(DMAMUX,12)
+#define DMAMUX_CHCFG13                           DMAMUX_CHCFG_REG(DMAMUX,13)
+#define DMAMUX_CHCFG14                           DMAMUX_CHCFG_REG(DMAMUX,14)
+#define DMAMUX_CHCFG15                           DMAMUX_CHCFG_REG(DMAMUX,15)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX_CHCFG(index)                      DMAMUX_CHCFG_REG(DMAMUX,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4];
+  __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
+  __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register, offset: 0x10 */
+  __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register, offset: 0x14 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
+  __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
+       uint8_t RESERVED_4[28];
+  __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
+       uint8_t RESERVED_5[28];
+  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
+  __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
+  __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
+       uint8_t RESERVED_8[40];
+  __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+  __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+  __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
+  __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
+       uint8_t RESERVED_9[28];
+  __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
+       uint8_t RESERVED_10[56];
+  __IO uint32_t RDSR;                              /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+  __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+  __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+  __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+  __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+  __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+  __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+  __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+  __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+  __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+  __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
+       uint8_t RESERVED_12[12];
+  __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+  __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+       uint8_t RESERVED_13[60];
+  __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
+  __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
+  __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
+  __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
+  __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
+  __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
+  __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
+  __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
+  __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
+  __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
+  __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
+  __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
+  __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
+  __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
+  __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
+  __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
+  __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
+       uint8_t RESERVED_14[4];
+  __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
+  __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
+  __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
+  __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
+  __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
+  __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
+  __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
+  __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
+       uint8_t RESERVED_15[4];
+  __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
+  __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
+       uint8_t RESERVED_16[12];
+  __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
+  __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
+  __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
+  __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
+  __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
+  __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
+  __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
+  __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
+       uint8_t RESERVED_17[4];
+  __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
+  __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
+  __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
+  __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
+  __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
+  __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
+  __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
+  __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
+  __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
+  __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
+  __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
+  __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
+  __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
+  __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
+  __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
+       uint8_t RESERVED_18[284];
+  __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
+  __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
+  __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
+  __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
+  __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
+  __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
+  __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+       uint8_t RESERVED_19[488];
+  __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
+  struct {                                         /* offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+  } CHANNEL[4];
+} ENET_Type, *ENET_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register accessors */
+#define ENET_EIR_REG(base)                       ((base)->EIR)
+#define ENET_EIMR_REG(base)                      ((base)->EIMR)
+#define ENET_RDAR_REG(base)                      ((base)->RDAR)
+#define ENET_TDAR_REG(base)                      ((base)->TDAR)
+#define ENET_ECR_REG(base)                       ((base)->ECR)
+#define ENET_MMFR_REG(base)                      ((base)->MMFR)
+#define ENET_MSCR_REG(base)                      ((base)->MSCR)
+#define ENET_MIBC_REG(base)                      ((base)->MIBC)
+#define ENET_RCR_REG(base)                       ((base)->RCR)
+#define ENET_TCR_REG(base)                       ((base)->TCR)
+#define ENET_PALR_REG(base)                      ((base)->PALR)
+#define ENET_PAUR_REG(base)                      ((base)->PAUR)
+#define ENET_OPD_REG(base)                       ((base)->OPD)
+#define ENET_IAUR_REG(base)                      ((base)->IAUR)
+#define ENET_IALR_REG(base)                      ((base)->IALR)
+#define ENET_GAUR_REG(base)                      ((base)->GAUR)
+#define ENET_GALR_REG(base)                      ((base)->GALR)
+#define ENET_TFWR_REG(base)                      ((base)->TFWR)
+#define ENET_RDSR_REG(base)                      ((base)->RDSR)
+#define ENET_TDSR_REG(base)                      ((base)->TDSR)
+#define ENET_MRBR_REG(base)                      ((base)->MRBR)
+#define ENET_RSFL_REG(base)                      ((base)->RSFL)
+#define ENET_RSEM_REG(base)                      ((base)->RSEM)
+#define ENET_RAEM_REG(base)                      ((base)->RAEM)
+#define ENET_RAFL_REG(base)                      ((base)->RAFL)
+#define ENET_TSEM_REG(base)                      ((base)->TSEM)
+#define ENET_TAEM_REG(base)                      ((base)->TAEM)
+#define ENET_TAFL_REG(base)                      ((base)->TAFL)
+#define ENET_TIPG_REG(base)                      ((base)->TIPG)
+#define ENET_FTRL_REG(base)                      ((base)->FTRL)
+#define ENET_TACC_REG(base)                      ((base)->TACC)
+#define ENET_RACC_REG(base)                      ((base)->RACC)
+#define ENET_RMON_T_PACKETS_REG(base)            ((base)->RMON_T_PACKETS)
+#define ENET_RMON_T_BC_PKT_REG(base)             ((base)->RMON_T_BC_PKT)
+#define ENET_RMON_T_MC_PKT_REG(base)             ((base)->RMON_T_MC_PKT)
+#define ENET_RMON_T_CRC_ALIGN_REG(base)          ((base)->RMON_T_CRC_ALIGN)
+#define ENET_RMON_T_UNDERSIZE_REG(base)          ((base)->RMON_T_UNDERSIZE)
+#define ENET_RMON_T_OVERSIZE_REG(base)           ((base)->RMON_T_OVERSIZE)
+#define ENET_RMON_T_FRAG_REG(base)               ((base)->RMON_T_FRAG)
+#define ENET_RMON_T_JAB_REG(base)                ((base)->RMON_T_JAB)
+#define ENET_RMON_T_COL_REG(base)                ((base)->RMON_T_COL)
+#define ENET_RMON_T_P64_REG(base)                ((base)->RMON_T_P64)
+#define ENET_RMON_T_P65TO127_REG(base)           ((base)->RMON_T_P65TO127)
+#define ENET_RMON_T_P128TO255_REG(base)          ((base)->RMON_T_P128TO255)
+#define ENET_RMON_T_P256TO511_REG(base)          ((base)->RMON_T_P256TO511)
+#define ENET_RMON_T_P512TO1023_REG(base)         ((base)->RMON_T_P512TO1023)
+#define ENET_RMON_T_P1024TO2047_REG(base)        ((base)->RMON_T_P1024TO2047)
+#define ENET_RMON_T_P_GTE2048_REG(base)          ((base)->RMON_T_P_GTE2048)
+#define ENET_RMON_T_OCTETS_REG(base)             ((base)->RMON_T_OCTETS)
+#define ENET_IEEE_T_FRAME_OK_REG(base)           ((base)->IEEE_T_FRAME_OK)
+#define ENET_IEEE_T_1COL_REG(base)               ((base)->IEEE_T_1COL)
+#define ENET_IEEE_T_MCOL_REG(base)               ((base)->IEEE_T_MCOL)
+#define ENET_IEEE_T_DEF_REG(base)                ((base)->IEEE_T_DEF)
+#define ENET_IEEE_T_LCOL_REG(base)               ((base)->IEEE_T_LCOL)
+#define ENET_IEEE_T_EXCOL_REG(base)              ((base)->IEEE_T_EXCOL)
+#define ENET_IEEE_T_MACERR_REG(base)             ((base)->IEEE_T_MACERR)
+#define ENET_IEEE_T_CSERR_REG(base)              ((base)->IEEE_T_CSERR)
+#define ENET_IEEE_T_FDXFC_REG(base)              ((base)->IEEE_T_FDXFC)
+#define ENET_IEEE_T_OCTETS_OK_REG(base)          ((base)->IEEE_T_OCTETS_OK)
+#define ENET_RMON_R_PACKETS_REG(base)            ((base)->RMON_R_PACKETS)
+#define ENET_RMON_R_BC_PKT_REG(base)             ((base)->RMON_R_BC_PKT)
+#define ENET_RMON_R_MC_PKT_REG(base)             ((base)->RMON_R_MC_PKT)
+#define ENET_RMON_R_CRC_ALIGN_REG(base)          ((base)->RMON_R_CRC_ALIGN)
+#define ENET_RMON_R_UNDERSIZE_REG(base)          ((base)->RMON_R_UNDERSIZE)
+#define ENET_RMON_R_OVERSIZE_REG(base)           ((base)->RMON_R_OVERSIZE)
+#define ENET_RMON_R_FRAG_REG(base)               ((base)->RMON_R_FRAG)
+#define ENET_RMON_R_JAB_REG(base)                ((base)->RMON_R_JAB)
+#define ENET_RMON_R_P64_REG(base)                ((base)->RMON_R_P64)
+#define ENET_RMON_R_P65TO127_REG(base)           ((base)->RMON_R_P65TO127)
+#define ENET_RMON_R_P128TO255_REG(base)          ((base)->RMON_R_P128TO255)
+#define ENET_RMON_R_P256TO511_REG(base)          ((base)->RMON_R_P256TO511)
+#define ENET_RMON_R_P512TO1023_REG(base)         ((base)->RMON_R_P512TO1023)
+#define ENET_RMON_R_P1024TO2047_REG(base)        ((base)->RMON_R_P1024TO2047)
+#define ENET_RMON_R_P_GTE2048_REG(base)          ((base)->RMON_R_P_GTE2048)
+#define ENET_RMON_R_OCTETS_REG(base)             ((base)->RMON_R_OCTETS)
+#define ENET_IEEE_R_DROP_REG(base)               ((base)->IEEE_R_DROP)
+#define ENET_IEEE_R_FRAME_OK_REG(base)           ((base)->IEEE_R_FRAME_OK)
+#define ENET_IEEE_R_CRC_REG(base)                ((base)->IEEE_R_CRC)
+#define ENET_IEEE_R_ALIGN_REG(base)              ((base)->IEEE_R_ALIGN)
+#define ENET_IEEE_R_MACERR_REG(base)             ((base)->IEEE_R_MACERR)
+#define ENET_IEEE_R_FDXFC_REG(base)              ((base)->IEEE_R_FDXFC)
+#define ENET_IEEE_R_OCTETS_OK_REG(base)          ((base)->IEEE_R_OCTETS_OK)
+#define ENET_ATCR_REG(base)                      ((base)->ATCR)
+#define ENET_ATVR_REG(base)                      ((base)->ATVR)
+#define ENET_ATOFF_REG(base)                     ((base)->ATOFF)
+#define ENET_ATPER_REG(base)                     ((base)->ATPER)
+#define ENET_ATCOR_REG(base)                     ((base)->ATCOR)
+#define ENET_ATINC_REG(base)                     ((base)->ATINC)
+#define ENET_ATSTMP_REG(base)                    ((base)->ATSTMP)
+#define ENET_TGSR_REG(base)                      ((base)->TGSR)
+#define ENET_TCSR_REG(base,index)                ((base)->CHANNEL[index].TCSR)
+#define ENET_TCSR_COUNT                          4
+#define ENET_TCCR_REG(base,index)                ((base)->CHANNEL[index].TCCR)
+#define ENET_TCCR_COUNT                          4
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/* EIR Bit Fields */
+#define ENET_EIR_TS_TIMER_MASK                   0x8000u
+#define ENET_EIR_TS_TIMER_SHIFT                  15
+#define ENET_EIR_TS_TIMER_WIDTH                  1
+#define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_TIMER_SHIFT))&ENET_EIR_TS_TIMER_MASK)
+#define ENET_EIR_TS_AVAIL_MASK                   0x10000u
+#define ENET_EIR_TS_AVAIL_SHIFT                  16
+#define ENET_EIR_TS_AVAIL_WIDTH                  1
+#define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_AVAIL_SHIFT))&ENET_EIR_TS_AVAIL_MASK)
+#define ENET_EIR_WAKEUP_MASK                     0x20000u
+#define ENET_EIR_WAKEUP_SHIFT                    17
+#define ENET_EIR_WAKEUP_WIDTH                    1
+#define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_EIR_WAKEUP_SHIFT))&ENET_EIR_WAKEUP_MASK)
+#define ENET_EIR_PLR_MASK                        0x40000u
+#define ENET_EIR_PLR_SHIFT                       18
+#define ENET_EIR_PLR_WIDTH                       1
+#define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_PLR_SHIFT))&ENET_EIR_PLR_MASK)
+#define ENET_EIR_UN_MASK                         0x80000u
+#define ENET_EIR_UN_SHIFT                        19
+#define ENET_EIR_UN_WIDTH                        1
+#define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_UN_SHIFT))&ENET_EIR_UN_MASK)
+#define ENET_EIR_RL_MASK                         0x100000u
+#define ENET_EIR_RL_SHIFT                        20
+#define ENET_EIR_RL_WIDTH                        1
+#define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RL_SHIFT))&ENET_EIR_RL_MASK)
+#define ENET_EIR_LC_MASK                         0x200000u
+#define ENET_EIR_LC_SHIFT                        21
+#define ENET_EIR_LC_WIDTH                        1
+#define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_LC_SHIFT))&ENET_EIR_LC_MASK)
+#define ENET_EIR_EBERR_MASK                      0x400000u
+#define ENET_EIR_EBERR_SHIFT                     22
+#define ENET_EIR_EBERR_WIDTH                     1
+#define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIR_EBERR_SHIFT))&ENET_EIR_EBERR_MASK)
+#define ENET_EIR_MII_MASK                        0x800000u
+#define ENET_EIR_MII_SHIFT                       23
+#define ENET_EIR_MII_WIDTH                       1
+#define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_MII_SHIFT))&ENET_EIR_MII_MASK)
+#define ENET_EIR_RXB_MASK                        0x1000000u
+#define ENET_EIR_RXB_SHIFT                       24
+#define ENET_EIR_RXB_WIDTH                       1
+#define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXB_SHIFT))&ENET_EIR_RXB_MASK)
+#define ENET_EIR_RXF_MASK                        0x2000000u
+#define ENET_EIR_RXF_SHIFT                       25
+#define ENET_EIR_RXF_WIDTH                       1
+#define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXF_SHIFT))&ENET_EIR_RXF_MASK)
+#define ENET_EIR_TXB_MASK                        0x4000000u
+#define ENET_EIR_TXB_SHIFT                       26
+#define ENET_EIR_TXB_WIDTH                       1
+#define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXB_SHIFT))&ENET_EIR_TXB_MASK)
+#define ENET_EIR_TXF_MASK                        0x8000000u
+#define ENET_EIR_TXF_SHIFT                       27
+#define ENET_EIR_TXF_WIDTH                       1
+#define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXF_SHIFT))&ENET_EIR_TXF_MASK)
+#define ENET_EIR_GRA_MASK                        0x10000000u
+#define ENET_EIR_GRA_SHIFT                       28
+#define ENET_EIR_GRA_WIDTH                       1
+#define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_GRA_SHIFT))&ENET_EIR_GRA_MASK)
+#define ENET_EIR_BABT_MASK                       0x20000000u
+#define ENET_EIR_BABT_SHIFT                      29
+#define ENET_EIR_BABT_WIDTH                      1
+#define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABT_SHIFT))&ENET_EIR_BABT_MASK)
+#define ENET_EIR_BABR_MASK                       0x40000000u
+#define ENET_EIR_BABR_SHIFT                      30
+#define ENET_EIR_BABR_WIDTH                      1
+#define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABR_SHIFT))&ENET_EIR_BABR_MASK)
+/* EIMR Bit Fields */
+#define ENET_EIMR_TS_TIMER_MASK                  0x8000u
+#define ENET_EIMR_TS_TIMER_SHIFT                 15
+#define ENET_EIMR_TS_TIMER_WIDTH                 1
+#define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_TIMER_SHIFT))&ENET_EIMR_TS_TIMER_MASK)
+#define ENET_EIMR_TS_AVAIL_MASK                  0x10000u
+#define ENET_EIMR_TS_AVAIL_SHIFT                 16
+#define ENET_EIMR_TS_AVAIL_WIDTH                 1
+#define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_AVAIL_SHIFT))&ENET_EIMR_TS_AVAIL_MASK)
+#define ENET_EIMR_WAKEUP_MASK                    0x20000u
+#define ENET_EIMR_WAKEUP_SHIFT                   17
+#define ENET_EIMR_WAKEUP_WIDTH                   1
+#define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_WAKEUP_SHIFT))&ENET_EIMR_WAKEUP_MASK)
+#define ENET_EIMR_PLR_MASK                       0x40000u
+#define ENET_EIMR_PLR_SHIFT                      18
+#define ENET_EIMR_PLR_WIDTH                      1
+#define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_PLR_SHIFT))&ENET_EIMR_PLR_MASK)
+#define ENET_EIMR_UN_MASK                        0x80000u
+#define ENET_EIMR_UN_SHIFT                       19
+#define ENET_EIMR_UN_WIDTH                       1
+#define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_UN_SHIFT))&ENET_EIMR_UN_MASK)
+#define ENET_EIMR_RL_MASK                        0x100000u
+#define ENET_EIMR_RL_SHIFT                       20
+#define ENET_EIMR_RL_WIDTH                       1
+#define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RL_SHIFT))&ENET_EIMR_RL_MASK)
+#define ENET_EIMR_LC_MASK                        0x200000u
+#define ENET_EIMR_LC_SHIFT                       21
+#define ENET_EIMR_LC_WIDTH                       1
+#define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_LC_SHIFT))&ENET_EIMR_LC_MASK)
+#define ENET_EIMR_EBERR_MASK                     0x400000u
+#define ENET_EIMR_EBERR_SHIFT                    22
+#define ENET_EIMR_EBERR_WIDTH                    1
+#define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_EBERR_SHIFT))&ENET_EIMR_EBERR_MASK)
+#define ENET_EIMR_MII_MASK                       0x800000u
+#define ENET_EIMR_MII_SHIFT                      23
+#define ENET_EIMR_MII_WIDTH                      1
+#define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_MII_SHIFT))&ENET_EIMR_MII_MASK)
+#define ENET_EIMR_RXB_MASK                       0x1000000u
+#define ENET_EIMR_RXB_SHIFT                      24
+#define ENET_EIMR_RXB_WIDTH                      1
+#define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXB_SHIFT))&ENET_EIMR_RXB_MASK)
+#define ENET_EIMR_RXF_MASK                       0x2000000u
+#define ENET_EIMR_RXF_SHIFT                      25
+#define ENET_EIMR_RXF_WIDTH                      1
+#define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXF_SHIFT))&ENET_EIMR_RXF_MASK)
+#define ENET_EIMR_TXB_MASK                       0x4000000u
+#define ENET_EIMR_TXB_SHIFT                      26
+#define ENET_EIMR_TXB_WIDTH                      1
+#define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXB_SHIFT))&ENET_EIMR_TXB_MASK)
+#define ENET_EIMR_TXF_MASK                       0x8000000u
+#define ENET_EIMR_TXF_SHIFT                      27
+#define ENET_EIMR_TXF_WIDTH                      1
+#define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXF_SHIFT))&ENET_EIMR_TXF_MASK)
+#define ENET_EIMR_GRA_MASK                       0x10000000u
+#define ENET_EIMR_GRA_SHIFT                      28
+#define ENET_EIMR_GRA_WIDTH                      1
+#define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_GRA_SHIFT))&ENET_EIMR_GRA_MASK)
+#define ENET_EIMR_BABT_MASK                      0x20000000u
+#define ENET_EIMR_BABT_SHIFT                     29
+#define ENET_EIMR_BABT_WIDTH                     1
+#define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABT_SHIFT))&ENET_EIMR_BABT_MASK)
+#define ENET_EIMR_BABR_MASK                      0x40000000u
+#define ENET_EIMR_BABR_SHIFT                     30
+#define ENET_EIMR_BABR_WIDTH                     1
+#define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABR_SHIFT))&ENET_EIMR_BABR_MASK)
+/* RDAR Bit Fields */
+#define ENET_RDAR_RDAR_MASK                      0x1000000u
+#define ENET_RDAR_RDAR_SHIFT                     24
+#define ENET_RDAR_RDAR_WIDTH                     1
+#define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RDAR_RDAR_SHIFT))&ENET_RDAR_RDAR_MASK)
+/* TDAR Bit Fields */
+#define ENET_TDAR_TDAR_MASK                      0x1000000u
+#define ENET_TDAR_TDAR_SHIFT                     24
+#define ENET_TDAR_TDAR_WIDTH                     1
+#define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TDAR_TDAR_SHIFT))&ENET_TDAR_TDAR_MASK)
+/* ECR Bit Fields */
+#define ENET_ECR_RESET_MASK                      0x1u
+#define ENET_ECR_RESET_SHIFT                     0
+#define ENET_ECR_RESET_WIDTH                     1
+#define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_RESET_SHIFT))&ENET_ECR_RESET_MASK)
+#define ENET_ECR_ETHEREN_MASK                    0x2u
+#define ENET_ECR_ETHEREN_SHIFT                   1
+#define ENET_ECR_ETHEREN_WIDTH                   1
+#define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ECR_ETHEREN_SHIFT))&ENET_ECR_ETHEREN_MASK)
+#define ENET_ECR_MAGICEN_MASK                    0x4u
+#define ENET_ECR_MAGICEN_SHIFT                   2
+#define ENET_ECR_MAGICEN_WIDTH                   1
+#define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ECR_MAGICEN_SHIFT))&ENET_ECR_MAGICEN_MASK)
+#define ENET_ECR_SLEEP_MASK                      0x8u
+#define ENET_ECR_SLEEP_SHIFT                     3
+#define ENET_ECR_SLEEP_WIDTH                     1
+#define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_SLEEP_SHIFT))&ENET_ECR_SLEEP_MASK)
+#define ENET_ECR_EN1588_MASK                     0x10u
+#define ENET_ECR_EN1588_SHIFT                    4
+#define ENET_ECR_EN1588_WIDTH                    1
+#define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ECR_EN1588_SHIFT))&ENET_ECR_EN1588_MASK)
+#define ENET_ECR_DBGEN_MASK                      0x40u
+#define ENET_ECR_DBGEN_SHIFT                     6
+#define ENET_ECR_DBGEN_WIDTH                     1
+#define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBGEN_SHIFT))&ENET_ECR_DBGEN_MASK)
+#define ENET_ECR_STOPEN_MASK                     0x80u
+#define ENET_ECR_STOPEN_SHIFT                    7
+#define ENET_ECR_STOPEN_WIDTH                    1
+#define ENET_ECR_STOPEN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ECR_STOPEN_SHIFT))&ENET_ECR_STOPEN_MASK)
+#define ENET_ECR_DBSWP_MASK                      0x100u
+#define ENET_ECR_DBSWP_SHIFT                     8
+#define ENET_ECR_DBSWP_WIDTH                     1
+#define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBSWP_SHIFT))&ENET_ECR_DBSWP_MASK)
+/* MMFR Bit Fields */
+#define ENET_MMFR_DATA_MASK                      0xFFFFu
+#define ENET_MMFR_DATA_SHIFT                     0
+#define ENET_MMFR_DATA_WIDTH                     16
+#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK                        0x30000u
+#define ENET_MMFR_TA_SHIFT                       16
+#define ENET_MMFR_TA_WIDTH                       2
+#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK                        0x7C0000u
+#define ENET_MMFR_RA_SHIFT                       18
+#define ENET_MMFR_RA_WIDTH                       5
+#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK                        0xF800000u
+#define ENET_MMFR_PA_SHIFT                       23
+#define ENET_MMFR_PA_WIDTH                       5
+#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK                        0x30000000u
+#define ENET_MMFR_OP_SHIFT                       28
+#define ENET_MMFR_OP_WIDTH                       2
+#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK                        0xC0000000u
+#define ENET_MMFR_ST_SHIFT                       30
+#define ENET_MMFR_ST_WIDTH                       2
+#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
+/* MSCR Bit Fields */
+#define ENET_MSCR_MII_SPEED_MASK                 0x7Eu
+#define ENET_MSCR_MII_SPEED_SHIFT                1
+#define ENET_MSCR_MII_SPEED_WIDTH                6
+#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE_MASK                   0x80u
+#define ENET_MSCR_DIS_PRE_SHIFT                  7
+#define ENET_MSCR_DIS_PRE_WIDTH                  1
+#define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_DIS_PRE_SHIFT))&ENET_MSCR_DIS_PRE_MASK)
+#define ENET_MSCR_HOLDTIME_MASK                  0x700u
+#define ENET_MSCR_HOLDTIME_SHIFT                 8
+#define ENET_MSCR_HOLDTIME_WIDTH                 3
+#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
+/* MIBC Bit Fields */
+#define ENET_MIBC_MIB_CLEAR_MASK                 0x20000000u
+#define ENET_MIBC_MIB_CLEAR_SHIFT                29
+#define ENET_MIBC_MIB_CLEAR_WIDTH                1
+#define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_CLEAR_SHIFT))&ENET_MIBC_MIB_CLEAR_MASK)
+#define ENET_MIBC_MIB_IDLE_MASK                  0x40000000u
+#define ENET_MIBC_MIB_IDLE_SHIFT                 30
+#define ENET_MIBC_MIB_IDLE_WIDTH                 1
+#define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_IDLE_SHIFT))&ENET_MIBC_MIB_IDLE_MASK)
+#define ENET_MIBC_MIB_DIS_MASK                   0x80000000u
+#define ENET_MIBC_MIB_DIS_SHIFT                  31
+#define ENET_MIBC_MIB_DIS_WIDTH                  1
+#define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_DIS_SHIFT))&ENET_MIBC_MIB_DIS_MASK)
+/* RCR Bit Fields */
+#define ENET_RCR_LOOP_MASK                       0x1u
+#define ENET_RCR_LOOP_SHIFT                      0
+#define ENET_RCR_LOOP_WIDTH                      1
+#define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_LOOP_SHIFT))&ENET_RCR_LOOP_MASK)
+#define ENET_RCR_DRT_MASK                        0x2u
+#define ENET_RCR_DRT_SHIFT                       1
+#define ENET_RCR_DRT_WIDTH                       1
+#define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_DRT_SHIFT))&ENET_RCR_DRT_MASK)
+#define ENET_RCR_MII_MODE_MASK                   0x4u
+#define ENET_RCR_MII_MODE_SHIFT                  2
+#define ENET_RCR_MII_MODE_WIDTH                  1
+#define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MII_MODE_SHIFT))&ENET_RCR_MII_MODE_MASK)
+#define ENET_RCR_PROM_MASK                       0x8u
+#define ENET_RCR_PROM_SHIFT                      3
+#define ENET_RCR_PROM_WIDTH                      1
+#define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PROM_SHIFT))&ENET_RCR_PROM_MASK)
+#define ENET_RCR_BC_REJ_MASK                     0x10u
+#define ENET_RCR_BC_REJ_SHIFT                    4
+#define ENET_RCR_BC_REJ_WIDTH                    1
+#define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_BC_REJ_SHIFT))&ENET_RCR_BC_REJ_MASK)
+#define ENET_RCR_FCE_MASK                        0x20u
+#define ENET_RCR_FCE_SHIFT                       5
+#define ENET_RCR_FCE_WIDTH                       1
+#define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_FCE_SHIFT))&ENET_RCR_FCE_MASK)
+#define ENET_RCR_RMII_MODE_MASK                  0x100u
+#define ENET_RCR_RMII_MODE_SHIFT                 8
+#define ENET_RCR_RMII_MODE_WIDTH                 1
+#define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_MODE_SHIFT))&ENET_RCR_RMII_MODE_MASK)
+#define ENET_RCR_RMII_10T_MASK                   0x200u
+#define ENET_RCR_RMII_10T_SHIFT                  9
+#define ENET_RCR_RMII_10T_WIDTH                  1
+#define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_10T_SHIFT))&ENET_RCR_RMII_10T_MASK)
+#define ENET_RCR_PADEN_MASK                      0x1000u
+#define ENET_RCR_PADEN_SHIFT                     12
+#define ENET_RCR_PADEN_WIDTH                     1
+#define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PADEN_SHIFT))&ENET_RCR_PADEN_MASK)
+#define ENET_RCR_PAUFWD_MASK                     0x2000u
+#define ENET_RCR_PAUFWD_SHIFT                    13
+#define ENET_RCR_PAUFWD_WIDTH                    1
+#define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PAUFWD_SHIFT))&ENET_RCR_PAUFWD_MASK)
+#define ENET_RCR_CRCFWD_MASK                     0x4000u
+#define ENET_RCR_CRCFWD_SHIFT                    14
+#define ENET_RCR_CRCFWD_WIDTH                    1
+#define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CRCFWD_SHIFT))&ENET_RCR_CRCFWD_MASK)
+#define ENET_RCR_CFEN_MASK                       0x8000u
+#define ENET_RCR_CFEN_SHIFT                      15
+#define ENET_RCR_CFEN_WIDTH                      1
+#define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CFEN_SHIFT))&ENET_RCR_CFEN_MASK)
+#define ENET_RCR_MAX_FL_MASK                     0x3FFF0000u
+#define ENET_RCR_MAX_FL_SHIFT                    16
+#define ENET_RCR_MAX_FL_WIDTH                    14
+#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC_MASK                        0x40000000u
+#define ENET_RCR_NLC_SHIFT                       30
+#define ENET_RCR_NLC_WIDTH                       1
+#define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_NLC_SHIFT))&ENET_RCR_NLC_MASK)
+#define ENET_RCR_GRS_MASK                        0x80000000u
+#define ENET_RCR_GRS_SHIFT                       31
+#define ENET_RCR_GRS_WIDTH                       1
+#define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_GRS_SHIFT))&ENET_RCR_GRS_MASK)
+/* TCR Bit Fields */
+#define ENET_TCR_GTS_MASK                        0x1u
+#define ENET_TCR_GTS_SHIFT                       0
+#define ENET_TCR_GTS_WIDTH                       1
+#define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_TCR_GTS_SHIFT))&ENET_TCR_GTS_MASK)
+#define ENET_TCR_FDEN_MASK                       0x4u
+#define ENET_TCR_FDEN_SHIFT                      2
+#define ENET_TCR_FDEN_WIDTH                      1
+#define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCR_FDEN_SHIFT))&ENET_TCR_FDEN_MASK)
+#define ENET_TCR_TFC_PAUSE_MASK                  0x8u
+#define ENET_TCR_TFC_PAUSE_SHIFT                 3
+#define ENET_TCR_TFC_PAUSE_WIDTH                 1
+#define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_TCR_TFC_PAUSE_SHIFT))&ENET_TCR_TFC_PAUSE_MASK)
+#define ENET_TCR_RFC_PAUSE_MASK                  0x10u
+#define ENET_TCR_RFC_PAUSE_SHIFT                 4
+#define ENET_TCR_RFC_PAUSE_WIDTH                 1
+#define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_TCR_RFC_PAUSE_SHIFT))&ENET_TCR_RFC_PAUSE_MASK)
+#define ENET_TCR_ADDSEL_MASK                     0xE0u
+#define ENET_TCR_ADDSEL_SHIFT                    5
+#define ENET_TCR_ADDSEL_WIDTH                    3
+#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS_MASK                     0x100u
+#define ENET_TCR_ADDINS_SHIFT                    8
+#define ENET_TCR_ADDINS_WIDTH                    1
+#define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDINS_SHIFT))&ENET_TCR_ADDINS_MASK)
+#define ENET_TCR_CRCFWD_MASK                     0x200u
+#define ENET_TCR_CRCFWD_SHIFT                    9
+#define ENET_TCR_CRCFWD_WIDTH                    1
+#define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_CRCFWD_SHIFT))&ENET_TCR_CRCFWD_MASK)
+/* PALR Bit Fields */
+#define ENET_PALR_PADDR1_MASK                    0xFFFFFFFFu
+#define ENET_PALR_PADDR1_SHIFT                   0
+#define ENET_PALR_PADDR1_WIDTH                   32
+#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
+/* PAUR Bit Fields */
+#define ENET_PAUR_TYPE_MASK                      0xFFFFu
+#define ENET_PAUR_TYPE_SHIFT                     0
+#define ENET_PAUR_TYPE_WIDTH                     16
+#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK                    0xFFFF0000u
+#define ENET_PAUR_PADDR2_SHIFT                   16
+#define ENET_PAUR_PADDR2_WIDTH                   16
+#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
+/* OPD Bit Fields */
+#define ENET_OPD_PAUSE_DUR_MASK                  0xFFFFu
+#define ENET_OPD_PAUSE_DUR_SHIFT                 0
+#define ENET_OPD_PAUSE_DUR_WIDTH                 16
+#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK                     0xFFFF0000u
+#define ENET_OPD_OPCODE_SHIFT                    16
+#define ENET_OPD_OPCODE_WIDTH                    16
+#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
+/* IAUR Bit Fields */
+#define ENET_IAUR_IADDR1_MASK                    0xFFFFFFFFu
+#define ENET_IAUR_IADDR1_SHIFT                   0
+#define ENET_IAUR_IADDR1_WIDTH                   32
+#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
+/* IALR Bit Fields */
+#define ENET_IALR_IADDR2_MASK                    0xFFFFFFFFu
+#define ENET_IALR_IADDR2_SHIFT                   0
+#define ENET_IALR_IADDR2_WIDTH                   32
+#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
+/* GAUR Bit Fields */
+#define ENET_GAUR_GADDR1_MASK                    0xFFFFFFFFu
+#define ENET_GAUR_GADDR1_SHIFT                   0
+#define ENET_GAUR_GADDR1_WIDTH                   32
+#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
+/* GALR Bit Fields */
+#define ENET_GALR_GADDR2_MASK                    0xFFFFFFFFu
+#define ENET_GALR_GADDR2_SHIFT                   0
+#define ENET_GALR_GADDR2_WIDTH                   32
+#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
+/* TFWR Bit Fields */
+#define ENET_TFWR_TFWR_MASK                      0x3Fu
+#define ENET_TFWR_TFWR_SHIFT                     0
+#define ENET_TFWR_TFWR_WIDTH                     6
+#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD_MASK                    0x100u
+#define ENET_TFWR_STRFWD_SHIFT                   8
+#define ENET_TFWR_STRFWD_WIDTH                   1
+#define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_STRFWD_SHIFT))&ENET_TFWR_STRFWD_MASK)
+/* RDSR Bit Fields */
+#define ENET_RDSR_R_DES_START_MASK               0xFFFFFFF8u
+#define ENET_RDSR_R_DES_START_SHIFT              3
+#define ENET_RDSR_R_DES_START_WIDTH              29
+#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
+/* TDSR Bit Fields */
+#define ENET_TDSR_X_DES_START_MASK               0xFFFFFFF8u
+#define ENET_TDSR_X_DES_START_SHIFT              3
+#define ENET_TDSR_X_DES_START_WIDTH              29
+#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
+/* MRBR Bit Fields */
+#define ENET_MRBR_R_BUF_SIZE_MASK                0x3FF0u
+#define ENET_MRBR_R_BUF_SIZE_SHIFT               4
+#define ENET_MRBR_R_BUF_SIZE_WIDTH               10
+#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
+/* RSFL Bit Fields */
+#define ENET_RSFL_RX_SECTION_FULL_MASK           0xFFu
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT          0
+#define ENET_RSFL_RX_SECTION_FULL_WIDTH          8
+#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
+/* RSEM Bit Fields */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         0
+#define ENET_RSEM_RX_SECTION_EMPTY_WIDTH         8
+#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK        0x1F0000u
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       16
+#define ENET_RSEM_STAT_SECTION_EMPTY_WIDTH       5
+#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+/* RAEM Bit Fields */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          0
+#define ENET_RAEM_RX_ALMOST_EMPTY_WIDTH          8
+#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+/* RAFL Bit Fields */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK            0xFFu
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           0
+#define ENET_RAFL_RX_ALMOST_FULL_WIDTH           8
+#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
+/* TSEM Bit Fields */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         0
+#define ENET_TSEM_TX_SECTION_EMPTY_WIDTH         8
+#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
+/* TAEM Bit Fields */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          0
+#define ENET_TAEM_TX_ALMOST_EMPTY_WIDTH          8
+#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+/* TAFL Bit Fields */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK            0xFFu
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           0
+#define ENET_TAFL_TX_ALMOST_FULL_WIDTH           8
+#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
+/* TIPG Bit Fields */
+#define ENET_TIPG_IPG_MASK                       0x1Fu
+#define ENET_TIPG_IPG_SHIFT                      0
+#define ENET_TIPG_IPG_WIDTH                      5
+#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
+/* FTRL Bit Fields */
+#define ENET_FTRL_TRUNC_FL_MASK                  0x3FFFu
+#define ENET_FTRL_TRUNC_FL_SHIFT                 0
+#define ENET_FTRL_TRUNC_FL_WIDTH                 14
+#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
+/* TACC Bit Fields */
+#define ENET_TACC_SHIFT16_MASK                   0x1u
+#define ENET_TACC_SHIFT16_SHIFT                  0
+#define ENET_TACC_SHIFT16_WIDTH                  1
+#define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_TACC_SHIFT16_SHIFT))&ENET_TACC_SHIFT16_MASK)
+#define ENET_TACC_IPCHK_MASK                     0x8u
+#define ENET_TACC_IPCHK_SHIFT                    3
+#define ENET_TACC_IPCHK_WIDTH                    1
+#define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TACC_IPCHK_SHIFT))&ENET_TACC_IPCHK_MASK)
+#define ENET_TACC_PROCHK_MASK                    0x10u
+#define ENET_TACC_PROCHK_SHIFT                   4
+#define ENET_TACC_PROCHK_WIDTH                   1
+#define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_TACC_PROCHK_SHIFT))&ENET_TACC_PROCHK_MASK)
+/* RACC Bit Fields */
+#define ENET_RACC_PADREM_MASK                    0x1u
+#define ENET_RACC_PADREM_SHIFT                   0
+#define ENET_RACC_PADREM_WIDTH                   1
+#define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PADREM_SHIFT))&ENET_RACC_PADREM_MASK)
+#define ENET_RACC_IPDIS_MASK                     0x2u
+#define ENET_RACC_IPDIS_SHIFT                    1
+#define ENET_RACC_IPDIS_WIDTH                    1
+#define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RACC_IPDIS_SHIFT))&ENET_RACC_IPDIS_MASK)
+#define ENET_RACC_PRODIS_MASK                    0x4u
+#define ENET_RACC_PRODIS_SHIFT                   2
+#define ENET_RACC_PRODIS_WIDTH                   1
+#define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PRODIS_SHIFT))&ENET_RACC_PRODIS_MASK)
+#define ENET_RACC_LINEDIS_MASK                   0x40u
+#define ENET_RACC_LINEDIS_SHIFT                  6
+#define ENET_RACC_LINEDIS_WIDTH                  1
+#define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RACC_LINEDIS_SHIFT))&ENET_RACC_LINEDIS_MASK)
+#define ENET_RACC_SHIFT16_MASK                   0x80u
+#define ENET_RACC_SHIFT16_SHIFT                  7
+#define ENET_RACC_SHIFT16_WIDTH                  1
+#define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RACC_SHIFT16_SHIFT))&ENET_RACC_SHIFT16_MASK)
+/* RMON_T_PACKETS Bit Fields */
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK          0xFFFFu
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         0
+#define ENET_RMON_T_PACKETS_TXPKTS_WIDTH         16
+#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
+/* RMON_T_BC_PKT Bit Fields */
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           0xFFFFu
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          0
+#define ENET_RMON_T_BC_PKT_TXPKTS_WIDTH          16
+#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+/* RMON_T_MC_PKT Bit Fields */
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           0xFFFFu
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          0
+#define ENET_RMON_T_MC_PKT_TXPKTS_WIDTH          16
+#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+/* RMON_T_CRC_ALIGN Bit Fields */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       0
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_WIDTH       16
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+/* RMON_T_UNDERSIZE Bit Fields */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       0
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_WIDTH       16
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+/* RMON_T_OVERSIZE Bit Fields */
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         0xFFFFu
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        0
+#define ENET_RMON_T_OVERSIZE_TXPKTS_WIDTH        16
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+/* RMON_T_FRAG Bit Fields */
+#define ENET_RMON_T_FRAG_TXPKTS_MASK             0xFFFFu
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            0
+#define ENET_RMON_T_FRAG_TXPKTS_WIDTH            16
+#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
+/* RMON_T_JAB Bit Fields */
+#define ENET_RMON_T_JAB_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT             0
+#define ENET_RMON_T_JAB_TXPKTS_WIDTH             16
+#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
+/* RMON_T_COL Bit Fields */
+#define ENET_RMON_T_COL_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_COL_TXPKTS_SHIFT             0
+#define ENET_RMON_T_COL_TXPKTS_WIDTH             16
+#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
+/* RMON_T_P64 Bit Fields */
+#define ENET_RMON_T_P64_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_P64_TXPKTS_SHIFT             0
+#define ENET_RMON_T_P64_TXPKTS_WIDTH             16
+#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
+/* RMON_T_P65TO127 Bit Fields */
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK         0xFFFFu
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        0
+#define ENET_RMON_T_P65TO127_TXPKTS_WIDTH        16
+#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
+/* RMON_T_P128TO255 Bit Fields */
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P128TO255_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
+/* RMON_T_P256TO511 Bit Fields */
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P256TO511_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
+/* RMON_T_P512TO1023 Bit Fields */
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       0xFFFFu
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      0
+#define ENET_RMON_T_P512TO1023_TXPKTS_WIDTH      16
+#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+/* RMON_T_P1024TO2047 Bit Fields */
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      0xFFFFu
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     0
+#define ENET_RMON_T_P1024TO2047_TXPKTS_WIDTH     16
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+/* RMON_T_P_GTE2048 Bit Fields */
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P_GTE2048_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+/* RMON_T_OCTETS Bit Fields */
+#define ENET_RMON_T_OCTETS_TXOCTS_MASK           0xFFFFFFFFu
+#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          0
+#define ENET_RMON_T_OCTETS_TXOCTS_WIDTH          32
+#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
+/* IEEE_T_FRAME_OK Bit Fields */
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          0xFFFFu
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         0
+#define ENET_IEEE_T_FRAME_OK_COUNT_WIDTH         16
+#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+/* IEEE_T_1COL Bit Fields */
+#define ENET_IEEE_T_1COL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_1COL_COUNT_SHIFT             0
+#define ENET_IEEE_T_1COL_COUNT_WIDTH             16
+#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
+/* IEEE_T_MCOL Bit Fields */
+#define ENET_IEEE_T_MCOL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT             0
+#define ENET_IEEE_T_MCOL_COUNT_WIDTH             16
+#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
+/* IEEE_T_DEF Bit Fields */
+#define ENET_IEEE_T_DEF_COUNT_MASK               0xFFFFu
+#define ENET_IEEE_T_DEF_COUNT_SHIFT              0
+#define ENET_IEEE_T_DEF_COUNT_WIDTH              16
+#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
+/* IEEE_T_LCOL Bit Fields */
+#define ENET_IEEE_T_LCOL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT             0
+#define ENET_IEEE_T_LCOL_COUNT_WIDTH             16
+#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
+/* IEEE_T_EXCOL Bit Fields */
+#define ENET_IEEE_T_EXCOL_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            0
+#define ENET_IEEE_T_EXCOL_COUNT_WIDTH            16
+#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
+/* IEEE_T_MACERR Bit Fields */
+#define ENET_IEEE_T_MACERR_COUNT_MASK            0xFFFFu
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT           0
+#define ENET_IEEE_T_MACERR_COUNT_WIDTH           16
+#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
+/* IEEE_T_CSERR Bit Fields */
+#define ENET_IEEE_T_CSERR_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT            0
+#define ENET_IEEE_T_CSERR_COUNT_WIDTH            16
+#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
+/* IEEE_T_FDXFC Bit Fields */
+#define ENET_IEEE_T_FDXFC_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            0
+#define ENET_IEEE_T_FDXFC_COUNT_WIDTH            16
+#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
+/* IEEE_T_OCTETS_OK Bit Fields */
+#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        0
+#define ENET_IEEE_T_OCTETS_OK_COUNT_WIDTH        32
+#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+/* RMON_R_PACKETS Bit Fields */
+#define ENET_RMON_R_PACKETS_COUNT_MASK           0xFFFFu
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT          0
+#define ENET_RMON_R_PACKETS_COUNT_WIDTH          16
+#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
+/* RMON_R_BC_PKT Bit Fields */
+#define ENET_RMON_R_BC_PKT_COUNT_MASK            0xFFFFu
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           0
+#define ENET_RMON_R_BC_PKT_COUNT_WIDTH           16
+#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
+/* RMON_R_MC_PKT Bit Fields */
+#define ENET_RMON_R_MC_PKT_COUNT_MASK            0xFFFFu
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           0
+#define ENET_RMON_R_MC_PKT_COUNT_WIDTH           16
+#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
+/* RMON_R_CRC_ALIGN Bit Fields */
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        0
+#define ENET_RMON_R_CRC_ALIGN_COUNT_WIDTH        16
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+/* RMON_R_UNDERSIZE Bit Fields */
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        0
+#define ENET_RMON_R_UNDERSIZE_COUNT_WIDTH        16
+#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+/* RMON_R_OVERSIZE Bit Fields */
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK          0xFFFFu
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         0
+#define ENET_RMON_R_OVERSIZE_COUNT_WIDTH         16
+#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
+/* RMON_R_FRAG Bit Fields */
+#define ENET_RMON_R_FRAG_COUNT_MASK              0xFFFFu
+#define ENET_RMON_R_FRAG_COUNT_SHIFT             0
+#define ENET_RMON_R_FRAG_COUNT_WIDTH             16
+#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
+/* RMON_R_JAB Bit Fields */
+#define ENET_RMON_R_JAB_COUNT_MASK               0xFFFFu
+#define ENET_RMON_R_JAB_COUNT_SHIFT              0
+#define ENET_RMON_R_JAB_COUNT_WIDTH              16
+#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
+/* RMON_R_P64 Bit Fields */
+#define ENET_RMON_R_P64_COUNT_MASK               0xFFFFu
+#define ENET_RMON_R_P64_COUNT_SHIFT              0
+#define ENET_RMON_R_P64_COUNT_WIDTH              16
+#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
+/* RMON_R_P65TO127 Bit Fields */
+#define ENET_RMON_R_P65TO127_COUNT_MASK          0xFFFFu
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT         0
+#define ENET_RMON_R_P65TO127_COUNT_WIDTH         16
+#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
+/* RMON_R_P128TO255 Bit Fields */
+#define ENET_RMON_R_P128TO255_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT        0
+#define ENET_RMON_R_P128TO255_COUNT_WIDTH        16
+#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
+/* RMON_R_P256TO511 Bit Fields */
+#define ENET_RMON_R_P256TO511_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT        0
+#define ENET_RMON_R_P256TO511_COUNT_WIDTH        16
+#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
+/* RMON_R_P512TO1023 Bit Fields */
+#define ENET_RMON_R_P512TO1023_COUNT_MASK        0xFFFFu
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       0
+#define ENET_RMON_R_P512TO1023_COUNT_WIDTH       16
+#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
+/* RMON_R_P1024TO2047 Bit Fields */
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK       0xFFFFu
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      0
+#define ENET_RMON_R_P1024TO2047_COUNT_WIDTH      16
+#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
+/* RMON_R_P_GTE2048 Bit Fields */
+#define ENET_RMON_R_P_GTE2048_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        0
+#define ENET_RMON_R_P_GTE2048_COUNT_WIDTH        16
+#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
+/* RMON_R_OCTETS Bit Fields */
+#define ENET_RMON_R_OCTETS_COUNT_MASK            0xFFFFFFFFu
+#define ENET_RMON_R_OCTETS_COUNT_SHIFT           0
+#define ENET_RMON_R_OCTETS_COUNT_WIDTH           32
+#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
+/* IEEE_R_DROP Bit Fields */
+#define ENET_IEEE_R_DROP_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_R_DROP_COUNT_SHIFT             0
+#define ENET_IEEE_R_DROP_COUNT_WIDTH             16
+#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
+/* IEEE_R_FRAME_OK Bit Fields */
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          0xFFFFu
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         0
+#define ENET_IEEE_R_FRAME_OK_COUNT_WIDTH         16
+#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+/* IEEE_R_CRC Bit Fields */
+#define ENET_IEEE_R_CRC_COUNT_MASK               0xFFFFu
+#define ENET_IEEE_R_CRC_COUNT_SHIFT              0
+#define ENET_IEEE_R_CRC_COUNT_WIDTH              16
+#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
+/* IEEE_R_ALIGN Bit Fields */
+#define ENET_IEEE_R_ALIGN_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            0
+#define ENET_IEEE_R_ALIGN_COUNT_WIDTH            16
+#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
+/* IEEE_R_MACERR Bit Fields */
+#define ENET_IEEE_R_MACERR_COUNT_MASK            0xFFFFu
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT           0
+#define ENET_IEEE_R_MACERR_COUNT_WIDTH           16
+#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
+/* IEEE_R_FDXFC Bit Fields */
+#define ENET_IEEE_R_FDXFC_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            0
+#define ENET_IEEE_R_FDXFC_COUNT_WIDTH            16
+#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
+/* IEEE_R_OCTETS_OK Bit Fields */
+#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        0
+#define ENET_IEEE_R_OCTETS_OK_COUNT_WIDTH        32
+#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+/* ATCR Bit Fields */
+#define ENET_ATCR_EN_MASK                        0x1u
+#define ENET_ATCR_EN_SHIFT                       0
+#define ENET_ATCR_EN_WIDTH                       1
+#define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_EN_SHIFT))&ENET_ATCR_EN_MASK)
+#define ENET_ATCR_OFFEN_MASK                     0x4u
+#define ENET_ATCR_OFFEN_SHIFT                    2
+#define ENET_ATCR_OFFEN_WIDTH                    1
+#define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFEN_SHIFT))&ENET_ATCR_OFFEN_MASK)
+#define ENET_ATCR_OFFRST_MASK                    0x8u
+#define ENET_ATCR_OFFRST_SHIFT                   3
+#define ENET_ATCR_OFFRST_WIDTH                   1
+#define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFRST_SHIFT))&ENET_ATCR_OFFRST_MASK)
+#define ENET_ATCR_PEREN_MASK                     0x10u
+#define ENET_ATCR_PEREN_SHIFT                    4
+#define ENET_ATCR_PEREN_WIDTH                    1
+#define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PEREN_SHIFT))&ENET_ATCR_PEREN_MASK)
+#define ENET_ATCR_PINPER_MASK                    0x80u
+#define ENET_ATCR_PINPER_SHIFT                   7
+#define ENET_ATCR_PINPER_WIDTH                   1
+#define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PINPER_SHIFT))&ENET_ATCR_PINPER_MASK)
+#define ENET_ATCR_RESTART_MASK                   0x200u
+#define ENET_ATCR_RESTART_SHIFT                  9
+#define ENET_ATCR_RESTART_WIDTH                  1
+#define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_RESTART_SHIFT))&ENET_ATCR_RESTART_MASK)
+#define ENET_ATCR_CAPTURE_MASK                   0x800u
+#define ENET_ATCR_CAPTURE_SHIFT                  11
+#define ENET_ATCR_CAPTURE_WIDTH                  1
+#define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_CAPTURE_SHIFT))&ENET_ATCR_CAPTURE_MASK)
+#define ENET_ATCR_SLAVE_MASK                     0x2000u
+#define ENET_ATCR_SLAVE_SHIFT                    13
+#define ENET_ATCR_SLAVE_WIDTH                    1
+#define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_SLAVE_SHIFT))&ENET_ATCR_SLAVE_MASK)
+/* ATVR Bit Fields */
+#define ENET_ATVR_ATIME_MASK                     0xFFFFFFFFu
+#define ENET_ATVR_ATIME_SHIFT                    0
+#define ENET_ATVR_ATIME_WIDTH                    32
+#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
+/* ATOFF Bit Fields */
+#define ENET_ATOFF_OFFSET_MASK                   0xFFFFFFFFu
+#define ENET_ATOFF_OFFSET_SHIFT                  0
+#define ENET_ATOFF_OFFSET_WIDTH                  32
+#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
+/* ATPER Bit Fields */
+#define ENET_ATPER_PERIOD_MASK                   0xFFFFFFFFu
+#define ENET_ATPER_PERIOD_SHIFT                  0
+#define ENET_ATPER_PERIOD_WIDTH                  32
+#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
+/* ATCOR Bit Fields */
+#define ENET_ATCOR_COR_MASK                      0x7FFFFFFFu
+#define ENET_ATCOR_COR_SHIFT                     0
+#define ENET_ATCOR_COR_WIDTH                     31
+#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
+/* ATINC Bit Fields */
+#define ENET_ATINC_INC_MASK                      0x7Fu
+#define ENET_ATINC_INC_SHIFT                     0
+#define ENET_ATINC_INC_WIDTH                     7
+#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK                 0x7F00u
+#define ENET_ATINC_INC_CORR_SHIFT                8
+#define ENET_ATINC_INC_CORR_WIDTH                7
+#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
+/* ATSTMP Bit Fields */
+#define ENET_ATSTMP_TIMESTAMP_MASK               0xFFFFFFFFu
+#define ENET_ATSTMP_TIMESTAMP_SHIFT              0
+#define ENET_ATSTMP_TIMESTAMP_WIDTH              32
+#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
+/* TGSR Bit Fields */
+#define ENET_TGSR_TF0_MASK                       0x1u
+#define ENET_TGSR_TF0_SHIFT                      0
+#define ENET_TGSR_TF0_WIDTH                      1
+#define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF0_SHIFT))&ENET_TGSR_TF0_MASK)
+#define ENET_TGSR_TF1_MASK                       0x2u
+#define ENET_TGSR_TF1_SHIFT                      1
+#define ENET_TGSR_TF1_WIDTH                      1
+#define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF1_SHIFT))&ENET_TGSR_TF1_MASK)
+#define ENET_TGSR_TF2_MASK                       0x4u
+#define ENET_TGSR_TF2_SHIFT                      2
+#define ENET_TGSR_TF2_WIDTH                      1
+#define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF2_SHIFT))&ENET_TGSR_TF2_MASK)
+#define ENET_TGSR_TF3_MASK                       0x8u
+#define ENET_TGSR_TF3_SHIFT                      3
+#define ENET_TGSR_TF3_WIDTH                      1
+#define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF3_SHIFT))&ENET_TGSR_TF3_MASK)
+/* TCSR Bit Fields */
+#define ENET_TCSR_TDRE_MASK                      0x1u
+#define ENET_TCSR_TDRE_SHIFT                     0
+#define ENET_TCSR_TDRE_WIDTH                     1
+#define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TDRE_SHIFT))&ENET_TCSR_TDRE_MASK)
+#define ENET_TCSR_TMODE_MASK                     0x3Cu
+#define ENET_TCSR_TMODE_SHIFT                    2
+#define ENET_TCSR_TMODE_WIDTH                    4
+#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE_MASK                       0x40u
+#define ENET_TCSR_TIE_SHIFT                      6
+#define ENET_TCSR_TIE_WIDTH                      1
+#define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TIE_SHIFT))&ENET_TCSR_TIE_MASK)
+#define ENET_TCSR_TF_MASK                        0x80u
+#define ENET_TCSR_TF_SHIFT                       7
+#define ENET_TCSR_TF_WIDTH                       1
+#define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TF_SHIFT))&ENET_TCSR_TF_MASK)
+/* TCCR Bit Fields */
+#define ENET_TCCR_TCC_MASK                       0xFFFFFFFFu
+#define ENET_TCCR_TCC_SHIFT                      0
+#define ENET_TCCR_TCC_WIDTH                      32
+#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE                                (0x400C0000u)
+/** Peripheral ENET base pointer */
+#define ENET                                     ((ENET_Type *)ENET_BASE)
+#define ENET_BASE_PTR                            (ENET)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS                          { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS                           { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_Transmit_IRQS                       { ENET_Transmit_IRQn }
+#define ENET_Receive_IRQS                        { ENET_Receive_IRQn }
+#define ENET_Error_IRQS                          { ENET_Error_IRQn }
+#define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register instance definitions */
+/* ENET */
+#define ENET_EIR                                 ENET_EIR_REG(ENET)
+#define ENET_EIMR                                ENET_EIMR_REG(ENET)
+#define ENET_RDAR                                ENET_RDAR_REG(ENET)
+#define ENET_TDAR                                ENET_TDAR_REG(ENET)
+#define ENET_ECR                                 ENET_ECR_REG(ENET)
+#define ENET_MMFR                                ENET_MMFR_REG(ENET)
+#define ENET_MSCR                                ENET_MSCR_REG(ENET)
+#define ENET_MIBC                                ENET_MIBC_REG(ENET)
+#define ENET_RCR                                 ENET_RCR_REG(ENET)
+#define ENET_TCR                                 ENET_TCR_REG(ENET)
+#define ENET_PALR                                ENET_PALR_REG(ENET)
+#define ENET_PAUR                                ENET_PAUR_REG(ENET)
+#define ENET_OPD                                 ENET_OPD_REG(ENET)
+#define ENET_IAUR                                ENET_IAUR_REG(ENET)
+#define ENET_IALR                                ENET_IALR_REG(ENET)
+#define ENET_GAUR                                ENET_GAUR_REG(ENET)
+#define ENET_GALR                                ENET_GALR_REG(ENET)
+#define ENET_TFWR                                ENET_TFWR_REG(ENET)
+#define ENET_RDSR                                ENET_RDSR_REG(ENET)
+#define ENET_TDSR                                ENET_TDSR_REG(ENET)
+#define ENET_MRBR                                ENET_MRBR_REG(ENET)
+#define ENET_RSFL                                ENET_RSFL_REG(ENET)
+#define ENET_RSEM                                ENET_RSEM_REG(ENET)
+#define ENET_RAEM                                ENET_RAEM_REG(ENET)
+#define ENET_RAFL                                ENET_RAFL_REG(ENET)
+#define ENET_TSEM                                ENET_TSEM_REG(ENET)
+#define ENET_TAEM                                ENET_TAEM_REG(ENET)
+#define ENET_TAFL                                ENET_TAFL_REG(ENET)
+#define ENET_TIPG                                ENET_TIPG_REG(ENET)
+#define ENET_FTRL                                ENET_FTRL_REG(ENET)
+#define ENET_TACC                                ENET_TACC_REG(ENET)
+#define ENET_RACC                                ENET_RACC_REG(ENET)
+#define ENET_RMON_T_PACKETS                      ENET_RMON_T_PACKETS_REG(ENET)
+#define ENET_RMON_T_BC_PKT                       ENET_RMON_T_BC_PKT_REG(ENET)
+#define ENET_RMON_T_MC_PKT                       ENET_RMON_T_MC_PKT_REG(ENET)
+#define ENET_RMON_T_CRC_ALIGN                    ENET_RMON_T_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_T_UNDERSIZE                    ENET_RMON_T_UNDERSIZE_REG(ENET)
+#define ENET_RMON_T_OVERSIZE                     ENET_RMON_T_OVERSIZE_REG(ENET)
+#define ENET_RMON_T_FRAG                         ENET_RMON_T_FRAG_REG(ENET)
+#define ENET_RMON_T_JAB                          ENET_RMON_T_JAB_REG(ENET)
+#define ENET_RMON_T_COL                          ENET_RMON_T_COL_REG(ENET)
+#define ENET_RMON_T_P64                          ENET_RMON_T_P64_REG(ENET)
+#define ENET_RMON_T_P65TO127                     ENET_RMON_T_P65TO127_REG(ENET)
+#define ENET_RMON_T_P128TO255                    ENET_RMON_T_P128TO255_REG(ENET)
+#define ENET_RMON_T_P256TO511                    ENET_RMON_T_P256TO511_REG(ENET)
+#define ENET_RMON_T_P512TO1023                   ENET_RMON_T_P512TO1023_REG(ENET)
+#define ENET_RMON_T_P1024TO2047                  ENET_RMON_T_P1024TO2047_REG(ENET)
+#define ENET_RMON_T_P_GTE2048                    ENET_RMON_T_P_GTE2048_REG(ENET)
+#define ENET_RMON_T_OCTETS                       ENET_RMON_T_OCTETS_REG(ENET)
+#define ENET_IEEE_T_FRAME_OK                     ENET_IEEE_T_FRAME_OK_REG(ENET)
+#define ENET_IEEE_T_1COL                         ENET_IEEE_T_1COL_REG(ENET)
+#define ENET_IEEE_T_MCOL                         ENET_IEEE_T_MCOL_REG(ENET)
+#define ENET_IEEE_T_DEF                          ENET_IEEE_T_DEF_REG(ENET)
+#define ENET_IEEE_T_LCOL                         ENET_IEEE_T_LCOL_REG(ENET)
+#define ENET_IEEE_T_EXCOL                        ENET_IEEE_T_EXCOL_REG(ENET)
+#define ENET_IEEE_T_MACERR                       ENET_IEEE_T_MACERR_REG(ENET)
+#define ENET_IEEE_T_CSERR                        ENET_IEEE_T_CSERR_REG(ENET)
+#define ENET_IEEE_T_FDXFC                        ENET_IEEE_T_FDXFC_REG(ENET)
+#define ENET_IEEE_T_OCTETS_OK                    ENET_IEEE_T_OCTETS_OK_REG(ENET)
+#define ENET_RMON_R_PACKETS                      ENET_RMON_R_PACKETS_REG(ENET)
+#define ENET_RMON_R_BC_PKT                       ENET_RMON_R_BC_PKT_REG(ENET)
+#define ENET_RMON_R_MC_PKT                       ENET_RMON_R_MC_PKT_REG(ENET)
+#define ENET_RMON_R_CRC_ALIGN                    ENET_RMON_R_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_R_UNDERSIZE                    ENET_RMON_R_UNDERSIZE_REG(ENET)
+#define ENET_RMON_R_OVERSIZE                     ENET_RMON_R_OVERSIZE_REG(ENET)
+#define ENET_RMON_R_FRAG                         ENET_RMON_R_FRAG_REG(ENET)
+#define ENET_RMON_R_JAB                          ENET_RMON_R_JAB_REG(ENET)
+#define ENET_RMON_R_P64                          ENET_RMON_R_P64_REG(ENET)
+#define ENET_RMON_R_P65TO127                     ENET_RMON_R_P65TO127_REG(ENET)
+#define ENET_RMON_R_P128TO255                    ENET_RMON_R_P128TO255_REG(ENET)
+#define ENET_RMON_R_P256TO511                    ENET_RMON_R_P256TO511_REG(ENET)
+#define ENET_RMON_R_P512TO1023                   ENET_RMON_R_P512TO1023_REG(ENET)
+#define ENET_RMON_R_P1024TO2047                  ENET_RMON_R_P1024TO2047_REG(ENET)
+#define ENET_RMON_R_P_GTE2048                    ENET_RMON_R_P_GTE2048_REG(ENET)
+#define ENET_RMON_R_OCTETS                       ENET_RMON_R_OCTETS_REG(ENET)
+#define ENET_IEEE_R_DROP                         ENET_IEEE_R_DROP_REG(ENET)
+#define ENET_IEEE_R_FRAME_OK                     ENET_IEEE_R_FRAME_OK_REG(ENET)
+#define ENET_IEEE_R_CRC                          ENET_IEEE_R_CRC_REG(ENET)
+#define ENET_IEEE_R_ALIGN                        ENET_IEEE_R_ALIGN_REG(ENET)
+#define ENET_IEEE_R_MACERR                       ENET_IEEE_R_MACERR_REG(ENET)
+#define ENET_IEEE_R_FDXFC                        ENET_IEEE_R_FDXFC_REG(ENET)
+#define ENET_IEEE_R_OCTETS_OK                    ENET_IEEE_R_OCTETS_OK_REG(ENET)
+#define ENET_ATCR                                ENET_ATCR_REG(ENET)
+#define ENET_ATVR                                ENET_ATVR_REG(ENET)
+#define ENET_ATOFF                               ENET_ATOFF_REG(ENET)
+#define ENET_ATPER                               ENET_ATPER_REG(ENET)
+#define ENET_ATCOR                               ENET_ATCOR_REG(ENET)
+#define ENET_ATINC                               ENET_ATINC_REG(ENET)
+#define ENET_ATSTMP                              ENET_ATSTMP_REG(ENET)
+#define ENET_TGSR                                ENET_TGSR_REG(ENET)
+#define ENET_TCSR0                               ENET_TCSR_REG(ENET,0)
+#define ENET_TCCR0                               ENET_TCCR_REG(ENET,0)
+#define ENET_TCSR1                               ENET_TCSR_REG(ENET,1)
+#define ENET_TCCR1                               ENET_TCCR_REG(ENET,1)
+#define ENET_TCSR2                               ENET_TCSR_REG(ENET,2)
+#define ENET_TCCR2                               ENET_TCCR_REG(ENET,2)
+#define ENET_TCSR3                               ENET_TCSR_REG(ENET,3)
+#define ENET_TCCR3                               ENET_TCCR_REG(ENET,3)
+
+/* ENET - Register array accessors */
+#define ENET_TCSR(index)                         ENET_TCSR_REG(ENET,index)
+#define ENET_TCCR(index)                         ENET_TCCR_REG(ENET,index)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
+} EWM_Type, *EWM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register accessors */
+#define EWM_CTRL_REG(base)                       ((base)->CTRL)
+#define EWM_SERV_REG(base)                       ((base)->SERV)
+#define EWM_CMPL_REG(base)                       ((base)->CMPL)
+#define EWM_CMPH_REG(base)                       ((base)->CMPH)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK                      0x1u
+#define EWM_CTRL_EWMEN_SHIFT                     0
+#define EWM_CTRL_EWMEN_WIDTH                     1
+#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK                      0x2u
+#define EWM_CTRL_ASSIN_SHIFT                     1
+#define EWM_CTRL_ASSIN_WIDTH                     1
+#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK                       0x4u
+#define EWM_CTRL_INEN_SHIFT                      2
+#define EWM_CTRL_INEN_WIDTH                      1
+#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK                      0x8u
+#define EWM_CTRL_INTEN_SHIFT                     3
+#define EWM_CTRL_INTEN_WIDTH                     1
+#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK                    0xFFu
+#define EWM_SERV_SERVICE_SHIFT                   0
+#define EWM_SERV_SERVICE_WIDTH                   8
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK                   0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT                  0
+#define EWM_CMPL_COMPAREL_WIDTH                  8
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK                   0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT                  0
+#define EWM_CMPH_COMPAREH_WIDTH                  8
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE                                 (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM                                      ((EWM_Type *)EWM_BASE)
+#define EWM_BASE_PTR                             (EWM)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS                           { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS                            { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS                                 { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register instance definitions */
+/* EWM */
+#define EWM_CTRL                                 EWM_CTRL_REG(EWM)
+#define EWM_SERV                                 EWM_SERV_REG(EWM)
+#define EWM_CMPL                                 EWM_CMPL_REG(EWM)
+#define EWM_CMPH                                 EWM_CMPH_REG(EWM)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0xC */
+    __IO uint32_t CSAR;                              /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+    __IO uint32_t CSMR;                              /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+    __IO uint32_t CSCR;                              /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+  } CS[6];
+       uint8_t RESERVED_0[24];
+  __IO uint32_t CSPMCR;                            /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type, *FB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register accessors */
+#define FB_CSAR_REG(base,index)                  ((base)->CS[index].CSAR)
+#define FB_CSAR_COUNT                            6
+#define FB_CSMR_REG(base,index)                  ((base)->CS[index].CSMR)
+#define FB_CSMR_COUNT                            6
+#define FB_CSCR_REG(base,index)                  ((base)->CS[index].CSCR)
+#define FB_CSCR_COUNT                            6
+#define FB_CSPMCR_REG(base)                      ((base)->CSPMCR)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK                          0xFFFF0000u
+#define FB_CSAR_BA_SHIFT                         16
+#define FB_CSAR_BA_WIDTH                         16
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
+/* CSMR Bit Fields */
+#define FB_CSMR_V_MASK                           0x1u
+#define FB_CSMR_V_SHIFT                          0
+#define FB_CSMR_V_WIDTH                          1
+#define FB_CSMR_V(x)                             (((uint32_t)(((uint32_t)(x))<<FB_CSMR_V_SHIFT))&FB_CSMR_V_MASK)
+#define FB_CSMR_WP_MASK                          0x100u
+#define FB_CSMR_WP_SHIFT                         8
+#define FB_CSMR_WP_WIDTH                         1
+#define FB_CSMR_WP(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSMR_WP_SHIFT))&FB_CSMR_WP_MASK)
+#define FB_CSMR_BAM_MASK                         0xFFFF0000u
+#define FB_CSMR_BAM_SHIFT                        16
+#define FB_CSMR_BAM_WIDTH                        16
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
+/* CSCR Bit Fields */
+#define FB_CSCR_BSTW_MASK                        0x8u
+#define FB_CSCR_BSTW_SHIFT                       3
+#define FB_CSCR_BSTW_WIDTH                       1
+#define FB_CSCR_BSTW(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTW_SHIFT))&FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTR_MASK                        0x10u
+#define FB_CSCR_BSTR_SHIFT                       4
+#define FB_CSCR_BSTR_WIDTH                       1
+#define FB_CSCR_BSTR(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTR_SHIFT))&FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BEM_MASK                         0x20u
+#define FB_CSCR_BEM_SHIFT                        5
+#define FB_CSCR_BEM_WIDTH                        1
+#define FB_CSCR_BEM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BEM_SHIFT))&FB_CSCR_BEM_MASK)
+#define FB_CSCR_PS_MASK                          0xC0u
+#define FB_CSCR_PS_SHIFT                         6
+#define FB_CSCR_PS_WIDTH                         2
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK                          0x100u
+#define FB_CSCR_AA_SHIFT                         8
+#define FB_CSCR_AA_WIDTH                         1
+#define FB_CSCR_AA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_AA_SHIFT))&FB_CSCR_AA_MASK)
+#define FB_CSCR_BLS_MASK                         0x200u
+#define FB_CSCR_BLS_SHIFT                        9
+#define FB_CSCR_BLS_WIDTH                        1
+#define FB_CSCR_BLS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BLS_SHIFT))&FB_CSCR_BLS_MASK)
+#define FB_CSCR_WS_MASK                          0xFC00u
+#define FB_CSCR_WS_SHIFT                         10
+#define FB_CSCR_WS_WIDTH                         6
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        0x30000u
+#define FB_CSCR_WRAH_SHIFT                       16
+#define FB_CSCR_WRAH_WIDTH                       2
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        0xC0000u
+#define FB_CSCR_RDAH_SHIFT                       18
+#define FB_CSCR_RDAH_WIDTH                       2
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        0x300000u
+#define FB_CSCR_ASET_SHIFT                       20
+#define FB_CSCR_ASET_WIDTH                       2
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK                        0x400000u
+#define FB_CSCR_EXTS_SHIFT                       22
+#define FB_CSCR_EXTS_WIDTH                       1
+#define FB_CSCR_EXTS(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_EXTS_SHIFT))&FB_CSCR_EXTS_MASK)
+#define FB_CSCR_SWSEN_MASK                       0x800000u
+#define FB_CSCR_SWSEN_SHIFT                      23
+#define FB_CSCR_SWSEN_WIDTH                      1
+#define FB_CSCR_SWSEN(x)                         (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWSEN_SHIFT))&FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWS_MASK                         0xFC000000u
+#define FB_CSCR_SWS_SHIFT                        26
+#define FB_CSCR_SWS_WIDTH                        6
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
+/* CSPMCR Bit Fields */
+#define FB_CSPMCR_GROUP5_MASK                    0xF000u
+#define FB_CSPMCR_GROUP5_SHIFT                   12
+#define FB_CSPMCR_GROUP5_WIDTH                   4
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    0xF0000u
+#define FB_CSPMCR_GROUP4_SHIFT                   16
+#define FB_CSPMCR_GROUP4_WIDTH                   4
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    0xF00000u
+#define FB_CSPMCR_GROUP3_SHIFT                   20
+#define FB_CSPMCR_GROUP3_WIDTH                   4
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    0xF000000u
+#define FB_CSPMCR_GROUP2_SHIFT                   24
+#define FB_CSPMCR_GROUP2_WIDTH                   4
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    0xF0000000u
+#define FB_CSPMCR_GROUP1_SHIFT                   28
+#define FB_CSPMCR_GROUP1_WIDTH                   4
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE                                  (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB                                       ((FB_Type *)FB_BASE)
+#define FB_BASE_PTR                              (FB)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS                            { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS                             { FB }
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register instance definitions */
+/* FB */
+#define FB_CSAR0                                 FB_CSAR_REG(FB,0)
+#define FB_CSMR0                                 FB_CSMR_REG(FB,0)
+#define FB_CSCR0                                 FB_CSCR_REG(FB,0)
+#define FB_CSAR1                                 FB_CSAR_REG(FB,1)
+#define FB_CSMR1                                 FB_CSMR_REG(FB,1)
+#define FB_CSCR1                                 FB_CSCR_REG(FB,1)
+#define FB_CSAR2                                 FB_CSAR_REG(FB,2)
+#define FB_CSMR2                                 FB_CSMR_REG(FB,2)
+#define FB_CSCR2                                 FB_CSCR_REG(FB,2)
+#define FB_CSAR3                                 FB_CSAR_REG(FB,3)
+#define FB_CSMR3                                 FB_CSMR_REG(FB,3)
+#define FB_CSCR3                                 FB_CSCR_REG(FB,3)
+#define FB_CSAR4                                 FB_CSAR_REG(FB,4)
+#define FB_CSMR4                                 FB_CSMR_REG(FB,4)
+#define FB_CSCR4                                 FB_CSCR_REG(FB,4)
+#define FB_CSAR5                                 FB_CSAR_REG(FB,5)
+#define FB_CSMR5                                 FB_CSMR_REG(FB,5)
+#define FB_CSCR5                                 FB_CSCR_REG(FB,5)
+#define FB_CSPMCR                                FB_CSPMCR_REG(FB)
+
+/* FB - Register array accessors */
+#define FB_CSAR(index)                           FB_CSAR_REG(FB,index)
+#define FB_CSMR(index)                           FB_CSMR_REG(FB,index)
+#define FB_CSCR(index)                           FB_CSCR_REG(FB,index)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PFAPR;                             /**< Flash Access Protection Register, offset: 0x0 */
+  __IO uint32_t PFB0CR;                            /**< Flash Bank 0 Control Register, offset: 0x4 */
+  __IO uint32_t PFB1CR;                            /**< Flash Bank 1 Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[244];
+  __IO uint32_t TAGVDW0S[4];                       /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+  __IO uint32_t TAGVDW1S[4];                       /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
+  __IO uint32_t TAGVDW2S[4];                       /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+  __IO uint32_t TAGVDW3S[4];                       /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
+       uint8_t RESERVED_1[192];
+  struct {                                         /* offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_U;                            /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_L;                            /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
+  } SET[4][4];
+} FMC_Type, *FMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register accessors */
+#define FMC_PFAPR_REG(base)                      ((base)->PFAPR)
+#define FMC_PFB0CR_REG(base)                     ((base)->PFB0CR)
+#define FMC_PFB1CR_REG(base)                     ((base)->PFB1CR)
+#define FMC_TAGVDW0S_REG(base,index)             ((base)->TAGVDW0S[index])
+#define FMC_TAGVDW0S_COUNT                       4
+#define FMC_TAGVDW1S_REG(base,index)             ((base)->TAGVDW1S[index])
+#define FMC_TAGVDW1S_COUNT                       4
+#define FMC_TAGVDW2S_REG(base,index)             ((base)->TAGVDW2S[index])
+#define FMC_TAGVDW2S_COUNT                       4
+#define FMC_TAGVDW3S_REG(base,index)             ((base)->TAGVDW3S[index])
+#define FMC_TAGVDW3S_COUNT                       4
+#define FMC_DATA_U_REG(base,index,index2)        ((base)->SET[index][index2].DATA_U)
+#define FMC_DATA_U_COUNT                         4
+#define FMC_DATA_U_COUNT2                        4
+#define FMC_DATA_L_REG(base,index,index2)        ((base)->SET[index][index2].DATA_L)
+#define FMC_DATA_L_COUNT                         4
+#define FMC_DATA_L_COUNT2                        4
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK                      0x3u
+#define FMC_PFAPR_M0AP_SHIFT                     0
+#define FMC_PFAPR_M0AP_WIDTH                     2
+#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK                      0xCu
+#define FMC_PFAPR_M1AP_SHIFT                     2
+#define FMC_PFAPR_M1AP_WIDTH                     2
+#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK                      0x30u
+#define FMC_PFAPR_M2AP_SHIFT                     4
+#define FMC_PFAPR_M2AP_WIDTH                     2
+#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK                      0xC0u
+#define FMC_PFAPR_M3AP_SHIFT                     6
+#define FMC_PFAPR_M3AP_WIDTH                     2
+#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK                      0x300u
+#define FMC_PFAPR_M4AP_SHIFT                     8
+#define FMC_PFAPR_M4AP_WIDTH                     2
+#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK                      0xC00u
+#define FMC_PFAPR_M5AP_SHIFT                     10
+#define FMC_PFAPR_M5AP_WIDTH                     2
+#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK                      0x3000u
+#define FMC_PFAPR_M6AP_SHIFT                     12
+#define FMC_PFAPR_M6AP_WIDTH                     2
+#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK                      0xC000u
+#define FMC_PFAPR_M7AP_SHIFT                     14
+#define FMC_PFAPR_M7AP_WIDTH                     2
+#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK                     0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT                    16
+#define FMC_PFAPR_M0PFD_WIDTH                    1
+#define FMC_PFAPR_M0PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0PFD_SHIFT))&FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK                     0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT                    17
+#define FMC_PFAPR_M1PFD_WIDTH                    1
+#define FMC_PFAPR_M1PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1PFD_SHIFT))&FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK                     0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT                    18
+#define FMC_PFAPR_M2PFD_WIDTH                    1
+#define FMC_PFAPR_M2PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2PFD_SHIFT))&FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK                     0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT                    19
+#define FMC_PFAPR_M3PFD_WIDTH                    1
+#define FMC_PFAPR_M3PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3PFD_SHIFT))&FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M4PFD_MASK                     0x100000u
+#define FMC_PFAPR_M4PFD_SHIFT                    20
+#define FMC_PFAPR_M4PFD_WIDTH                    1
+#define FMC_PFAPR_M4PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4PFD_SHIFT))&FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M5PFD_MASK                     0x200000u
+#define FMC_PFAPR_M5PFD_SHIFT                    21
+#define FMC_PFAPR_M5PFD_WIDTH                    1
+#define FMC_PFAPR_M5PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5PFD_SHIFT))&FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M6PFD_MASK                     0x400000u
+#define FMC_PFAPR_M6PFD_SHIFT                    22
+#define FMC_PFAPR_M6PFD_WIDTH                    1
+#define FMC_PFAPR_M6PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6PFD_SHIFT))&FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M7PFD_MASK                     0x800000u
+#define FMC_PFAPR_M7PFD_SHIFT                    23
+#define FMC_PFAPR_M7PFD_WIDTH                    1
+#define FMC_PFAPR_M7PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7PFD_SHIFT))&FMC_PFAPR_M7PFD_MASK)
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK                   0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT                  0
+#define FMC_PFB0CR_B0SEBE_WIDTH                  1
+#define FMC_PFB0CR_B0SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0SEBE_SHIFT))&FMC_PFB0CR_B0SEBE_MASK)
+#define FMC_PFB0CR_B0IPE_MASK                    0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT                   1
+#define FMC_PFB0CR_B0IPE_WIDTH                   1
+#define FMC_PFB0CR_B0IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0IPE_SHIFT))&FMC_PFB0CR_B0IPE_MASK)
+#define FMC_PFB0CR_B0DPE_MASK                    0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT                   2
+#define FMC_PFB0CR_B0DPE_WIDTH                   1
+#define FMC_PFB0CR_B0DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DPE_SHIFT))&FMC_PFB0CR_B0DPE_MASK)
+#define FMC_PFB0CR_B0ICE_MASK                    0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT                   3
+#define FMC_PFB0CR_B0ICE_WIDTH                   1
+#define FMC_PFB0CR_B0ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0ICE_SHIFT))&FMC_PFB0CR_B0ICE_MASK)
+#define FMC_PFB0CR_B0DCE_MASK                    0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT                   4
+#define FMC_PFB0CR_B0DCE_WIDTH                   1
+#define FMC_PFB0CR_B0DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DCE_SHIFT))&FMC_PFB0CR_B0DCE_MASK)
+#define FMC_PFB0CR_CRC_MASK                      0xE0u
+#define FMC_PFB0CR_CRC_SHIFT                     5
+#define FMC_PFB0CR_CRC_WIDTH                     3
+#define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK                     0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT                    17
+#define FMC_PFB0CR_B0MW_WIDTH                    2
+#define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK                  0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT                 19
+#define FMC_PFB0CR_S_B_INV_WIDTH                 1
+#define FMC_PFB0CR_S_B_INV(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_S_B_INV_SHIFT))&FMC_PFB0CR_S_B_INV_MASK)
+#define FMC_PFB0CR_CINV_WAY_MASK                 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT                20
+#define FMC_PFB0CR_CINV_WAY_WIDTH                4
+#define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK                 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT                24
+#define FMC_PFB0CR_CLCK_WAY_WIDTH                4
+#define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK                   0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT                  28
+#define FMC_PFB0CR_B0RWSC_WIDTH                  4
+#define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* PFB1CR Bit Fields */
+#define FMC_PFB1CR_B1SEBE_MASK                   0x1u
+#define FMC_PFB1CR_B1SEBE_SHIFT                  0
+#define FMC_PFB1CR_B1SEBE_WIDTH                  1
+#define FMC_PFB1CR_B1SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1SEBE_SHIFT))&FMC_PFB1CR_B1SEBE_MASK)
+#define FMC_PFB1CR_B1IPE_MASK                    0x2u
+#define FMC_PFB1CR_B1IPE_SHIFT                   1
+#define FMC_PFB1CR_B1IPE_WIDTH                   1
+#define FMC_PFB1CR_B1IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1IPE_SHIFT))&FMC_PFB1CR_B1IPE_MASK)
+#define FMC_PFB1CR_B1DPE_MASK                    0x4u
+#define FMC_PFB1CR_B1DPE_SHIFT                   2
+#define FMC_PFB1CR_B1DPE_WIDTH                   1
+#define FMC_PFB1CR_B1DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DPE_SHIFT))&FMC_PFB1CR_B1DPE_MASK)
+#define FMC_PFB1CR_B1ICE_MASK                    0x8u
+#define FMC_PFB1CR_B1ICE_SHIFT                   3
+#define FMC_PFB1CR_B1ICE_WIDTH                   1
+#define FMC_PFB1CR_B1ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1ICE_SHIFT))&FMC_PFB1CR_B1ICE_MASK)
+#define FMC_PFB1CR_B1DCE_MASK                    0x10u
+#define FMC_PFB1CR_B1DCE_SHIFT                   4
+#define FMC_PFB1CR_B1DCE_WIDTH                   1
+#define FMC_PFB1CR_B1DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DCE_SHIFT))&FMC_PFB1CR_B1DCE_MASK)
+#define FMC_PFB1CR_B1MW_MASK                     0x60000u
+#define FMC_PFB1CR_B1MW_SHIFT                    17
+#define FMC_PFB1CR_B1MW_WIDTH                    2
+#define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK                   0xF0000000u
+#define FMC_PFB1CR_B1RWSC_SHIFT                  28
+#define FMC_PFB1CR_B1RWSC_WIDTH                  4
+#define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
+/* TAGVDW0S Bit Fields */
+#define FMC_TAGVDW0S_valid_MASK                  0x1u
+#define FMC_TAGVDW0S_valid_SHIFT                 0
+#define FMC_TAGVDW0S_valid_WIDTH                 1
+#define FMC_TAGVDW0S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_valid_SHIFT))&FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW0S_tag_SHIFT                   5
+#define FMC_TAGVDW0S_tag_WIDTH                   14
+#define FMC_TAGVDW0S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
+/* TAGVDW1S Bit Fields */
+#define FMC_TAGVDW1S_valid_MASK                  0x1u
+#define FMC_TAGVDW1S_valid_SHIFT                 0
+#define FMC_TAGVDW1S_valid_WIDTH                 1
+#define FMC_TAGVDW1S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_valid_SHIFT))&FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW1S_tag_SHIFT                   5
+#define FMC_TAGVDW1S_tag_WIDTH                   14
+#define FMC_TAGVDW1S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
+/* TAGVDW2S Bit Fields */
+#define FMC_TAGVDW2S_valid_MASK                  0x1u
+#define FMC_TAGVDW2S_valid_SHIFT                 0
+#define FMC_TAGVDW2S_valid_WIDTH                 1
+#define FMC_TAGVDW2S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_valid_SHIFT))&FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW2S_tag_SHIFT                   5
+#define FMC_TAGVDW2S_tag_WIDTH                   14
+#define FMC_TAGVDW2S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
+/* TAGVDW3S Bit Fields */
+#define FMC_TAGVDW3S_valid_MASK                  0x1u
+#define FMC_TAGVDW3S_valid_SHIFT                 0
+#define FMC_TAGVDW3S_valid_WIDTH                 1
+#define FMC_TAGVDW3S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_valid_SHIFT))&FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW3S_tag_SHIFT                   5
+#define FMC_TAGVDW3S_tag_WIDTH                   14
+#define FMC_TAGVDW3S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
+/* DATA_U Bit Fields */
+#define FMC_DATA_U_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_U_data_SHIFT                    0
+#define FMC_DATA_U_data_WIDTH                    32
+#define FMC_DATA_U_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
+/* DATA_L Bit Fields */
+#define FMC_DATA_L_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_L_data_SHIFT                    0
+#define FMC_DATA_L_data_WIDTH                    32
+#define FMC_DATA_L_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE                                 (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC                                      ((FMC_Type *)FMC_BASE)
+#define FMC_BASE_PTR                             (FMC)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS                           { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS                            { FMC }
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register instance definitions */
+/* FMC */
+#define FMC_PFAPR                                FMC_PFAPR_REG(FMC)
+#define FMC_PFB0CR                               FMC_PFB0CR_REG(FMC)
+#define FMC_PFB1CR                               FMC_PFB1CR_REG(FMC)
+#define FMC_TAGVDW0S0                            FMC_TAGVDW0S_REG(FMC,0)
+#define FMC_TAGVDW0S1                            FMC_TAGVDW0S_REG(FMC,1)
+#define FMC_TAGVDW0S2                            FMC_TAGVDW0S_REG(FMC,2)
+#define FMC_TAGVDW0S3                            FMC_TAGVDW0S_REG(FMC,3)
+#define FMC_TAGVDW1S0                            FMC_TAGVDW1S_REG(FMC,0)
+#define FMC_TAGVDW1S1                            FMC_TAGVDW1S_REG(FMC,1)
+#define FMC_TAGVDW1S2                            FMC_TAGVDW1S_REG(FMC,2)
+#define FMC_TAGVDW1S3                            FMC_TAGVDW1S_REG(FMC,3)
+#define FMC_TAGVDW2S0                            FMC_TAGVDW2S_REG(FMC,0)
+#define FMC_TAGVDW2S1                            FMC_TAGVDW2S_REG(FMC,1)
+#define FMC_TAGVDW2S2                            FMC_TAGVDW2S_REG(FMC,2)
+#define FMC_TAGVDW2S3                            FMC_TAGVDW2S_REG(FMC,3)
+#define FMC_TAGVDW3S0                            FMC_TAGVDW3S_REG(FMC,0)
+#define FMC_TAGVDW3S1                            FMC_TAGVDW3S_REG(FMC,1)
+#define FMC_TAGVDW3S2                            FMC_TAGVDW3S_REG(FMC,2)
+#define FMC_TAGVDW3S3                            FMC_TAGVDW3S_REG(FMC,3)
+#define FMC_DATAW0S0U                            FMC_DATA_U_REG(FMC,0,0)
+#define FMC_DATAW0S0L                            FMC_DATA_L_REG(FMC,0,0)
+#define FMC_DATAW0S1U                            FMC_DATA_U_REG(FMC,0,1)
+#define FMC_DATAW0S1L                            FMC_DATA_L_REG(FMC,0,1)
+#define FMC_DATAW0S2U                            FMC_DATA_U_REG(FMC,0,2)
+#define FMC_DATAW0S2L                            FMC_DATA_L_REG(FMC,0,2)
+#define FMC_DATAW0S3U                            FMC_DATA_U_REG(FMC,0,3)
+#define FMC_DATAW0S3L                            FMC_DATA_L_REG(FMC,0,3)
+#define FMC_DATAW1S0U                            FMC_DATA_U_REG(FMC,1,0)
+#define FMC_DATAW1S0L                            FMC_DATA_L_REG(FMC,1,0)
+#define FMC_DATAW1S1U                            FMC_DATA_U_REG(FMC,1,1)
+#define FMC_DATAW1S1L                            FMC_DATA_L_REG(FMC,1,1)
+#define FMC_DATAW1S2U                            FMC_DATA_U_REG(FMC,1,2)
+#define FMC_DATAW1S2L                            FMC_DATA_L_REG(FMC,1,2)
+#define FMC_DATAW1S3U                            FMC_DATA_U_REG(FMC,1,3)
+#define FMC_DATAW1S3L                            FMC_DATA_L_REG(FMC,1,3)
+#define FMC_DATAW2S0U                            FMC_DATA_U_REG(FMC,2,0)
+#define FMC_DATAW2S0L                            FMC_DATA_L_REG(FMC,2,0)
+#define FMC_DATAW2S1U                            FMC_DATA_U_REG(FMC,2,1)
+#define FMC_DATAW2S1L                            FMC_DATA_L_REG(FMC,2,1)
+#define FMC_DATAW2S2U                            FMC_DATA_U_REG(FMC,2,2)
+#define FMC_DATAW2S2L                            FMC_DATA_L_REG(FMC,2,2)
+#define FMC_DATAW2S3U                            FMC_DATA_U_REG(FMC,2,3)
+#define FMC_DATAW2S3L                            FMC_DATA_L_REG(FMC,2,3)
+#define FMC_DATAW3S0U                            FMC_DATA_U_REG(FMC,3,0)
+#define FMC_DATAW3S0L                            FMC_DATA_L_REG(FMC,3,0)
+#define FMC_DATAW3S1U                            FMC_DATA_U_REG(FMC,3,1)
+#define FMC_DATAW3S1L                            FMC_DATA_L_REG(FMC,3,1)
+#define FMC_DATAW3S2U                            FMC_DATA_U_REG(FMC,3,2)
+#define FMC_DATAW3S2L                            FMC_DATA_L_REG(FMC,3,2)
+#define FMC_DATAW3S3U                            FMC_DATA_U_REG(FMC,3,3)
+#define FMC_DATAW3S3L                            FMC_DATA_L_REG(FMC,3,3)
+
+/* FMC - Register array accessors */
+#define FMC_TAGVDW0S(index)                      FMC_TAGVDW0S_REG(FMC,index)
+#define FMC_TAGVDW1S(index)                      FMC_TAGVDW1S_REG(FMC,index)
+#define FMC_TAGVDW2S(index)                      FMC_TAGVDW2S_REG(FMC,index)
+#define FMC_TAGVDW3S(index)                      FMC_TAGVDW3S_REG(FMC,index)
+#define FMC_DATA_U(index,index2)                 FMC_DATA_U_REG(FMC,index,index2)
+#define FMC_DATA_L(index,index2)                 FMC_DATA_L_REG(FMC,index,index2)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t FEPROT;                             /**< EEPROM Protection Register, offset: 0x16 */
+  __IO uint8_t FDPROT;                             /**< Data Flash Protection Register, offset: 0x17 */
+} FTFE_Type, *FTFE_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register accessors */
+#define FTFE_FSTAT_REG(base)                     ((base)->FSTAT)
+#define FTFE_FCNFG_REG(base)                     ((base)->FCNFG)
+#define FTFE_FSEC_REG(base)                      ((base)->FSEC)
+#define FTFE_FOPT_REG(base)                      ((base)->FOPT)
+#define FTFE_FCCOB3_REG(base)                    ((base)->FCCOB3)
+#define FTFE_FCCOB2_REG(base)                    ((base)->FCCOB2)
+#define FTFE_FCCOB1_REG(base)                    ((base)->FCCOB1)
+#define FTFE_FCCOB0_REG(base)                    ((base)->FCCOB0)
+#define FTFE_FCCOB7_REG(base)                    ((base)->FCCOB7)
+#define FTFE_FCCOB6_REG(base)                    ((base)->FCCOB6)
+#define FTFE_FCCOB5_REG(base)                    ((base)->FCCOB5)
+#define FTFE_FCCOB4_REG(base)                    ((base)->FCCOB4)
+#define FTFE_FCCOBB_REG(base)                    ((base)->FCCOBB)
+#define FTFE_FCCOBA_REG(base)                    ((base)->FCCOBA)
+#define FTFE_FCCOB9_REG(base)                    ((base)->FCCOB9)
+#define FTFE_FCCOB8_REG(base)                    ((base)->FCCOB8)
+#define FTFE_FPROT3_REG(base)                    ((base)->FPROT3)
+#define FTFE_FPROT2_REG(base)                    ((base)->FPROT2)
+#define FTFE_FPROT1_REG(base)                    ((base)->FPROT1)
+#define FTFE_FPROT0_REG(base)                    ((base)->FPROT0)
+#define FTFE_FEPROT_REG(base)                    ((base)->FEPROT)
+#define FTFE_FDPROT_REG(base)                    ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFE_FSTAT_MGSTAT0_MASK                  0x1u
+#define FTFE_FSTAT_MGSTAT0_SHIFT                 0
+#define FTFE_FSTAT_MGSTAT0_WIDTH                 1
+#define FTFE_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_MGSTAT0_SHIFT))&FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_FPVIOL_MASK                   0x10u
+#define FTFE_FSTAT_FPVIOL_SHIFT                  4
+#define FTFE_FSTAT_FPVIOL_WIDTH                  1
+#define FTFE_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_FPVIOL_SHIFT))&FTFE_FSTAT_FPVIOL_MASK)
+#define FTFE_FSTAT_ACCERR_MASK                   0x20u
+#define FTFE_FSTAT_ACCERR_SHIFT                  5
+#define FTFE_FSTAT_ACCERR_WIDTH                  1
+#define FTFE_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_ACCERR_SHIFT))&FTFE_FSTAT_ACCERR_MASK)
+#define FTFE_FSTAT_RDCOLERR_MASK                 0x40u
+#define FTFE_FSTAT_RDCOLERR_SHIFT                6
+#define FTFE_FSTAT_RDCOLERR_WIDTH                1
+#define FTFE_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_RDCOLERR_SHIFT))&FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFE_FSTAT_CCIF_MASK                     0x80u
+#define FTFE_FSTAT_CCIF_SHIFT                    7
+#define FTFE_FSTAT_CCIF_WIDTH                    1
+#define FTFE_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_CCIF_SHIFT))&FTFE_FSTAT_CCIF_MASK)
+/* FCNFG Bit Fields */
+#define FTFE_FCNFG_EEERDY_MASK                   0x1u
+#define FTFE_FCNFG_EEERDY_SHIFT                  0
+#define FTFE_FCNFG_EEERDY_WIDTH                  1
+#define FTFE_FCNFG_EEERDY(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_EEERDY_SHIFT))&FTFE_FCNFG_EEERDY_MASK)
+#define FTFE_FCNFG_RAMRDY_MASK                   0x2u
+#define FTFE_FCNFG_RAMRDY_SHIFT                  1
+#define FTFE_FCNFG_RAMRDY_WIDTH                  1
+#define FTFE_FCNFG_RAMRDY(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RAMRDY_SHIFT))&FTFE_FCNFG_RAMRDY_MASK)
+#define FTFE_FCNFG_PFLSH_MASK                    0x4u
+#define FTFE_FCNFG_PFLSH_SHIFT                   2
+#define FTFE_FCNFG_PFLSH_WIDTH                   1
+#define FTFE_FCNFG_PFLSH(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_PFLSH_SHIFT))&FTFE_FCNFG_PFLSH_MASK)
+#define FTFE_FCNFG_SWAP_MASK                     0x8u
+#define FTFE_FCNFG_SWAP_SHIFT                    3
+#define FTFE_FCNFG_SWAP_WIDTH                    1
+#define FTFE_FCNFG_SWAP(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_SWAP_SHIFT))&FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_ERSSUSP_MASK                  0x10u
+#define FTFE_FCNFG_ERSSUSP_SHIFT                 4
+#define FTFE_FCNFG_ERSSUSP_WIDTH                 1
+#define FTFE_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSSUSP_SHIFT))&FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSAREQ_MASK                  0x20u
+#define FTFE_FCNFG_ERSAREQ_SHIFT                 5
+#define FTFE_FCNFG_ERSAREQ_WIDTH                 1
+#define FTFE_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSAREQ_SHIFT))&FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_RDCOLLIE_MASK                 0x40u
+#define FTFE_FCNFG_RDCOLLIE_SHIFT                6
+#define FTFE_FCNFG_RDCOLLIE_WIDTH                1
+#define FTFE_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RDCOLLIE_SHIFT))&FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_CCIE_MASK                     0x80u
+#define FTFE_FCNFG_CCIE_SHIFT                    7
+#define FTFE_FCNFG_CCIE_WIDTH                    1
+#define FTFE_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_CCIE_SHIFT))&FTFE_FCNFG_CCIE_MASK)
+/* FSEC Bit Fields */
+#define FTFE_FSEC_SEC_MASK                       0x3u
+#define FTFE_FSEC_SEC_SHIFT                      0
+#define FTFE_FSEC_SEC_WIDTH                      2
+#define FTFE_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK                    0xCu
+#define FTFE_FSEC_FSLACC_SHIFT                   2
+#define FTFE_FSEC_FSLACC_WIDTH                   2
+#define FTFE_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK                      0x30u
+#define FTFE_FSEC_MEEN_SHIFT                     4
+#define FTFE_FSEC_MEEN_WIDTH                     2
+#define FTFE_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK                     0xC0u
+#define FTFE_FSEC_KEYEN_SHIFT                    6
+#define FTFE_FSEC_KEYEN_WIDTH                    2
+#define FTFE_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFE_FOPT_OPT_MASK                       0xFFu
+#define FTFE_FOPT_OPT_SHIFT                      0
+#define FTFE_FOPT_OPT_WIDTH                      8
+#define FTFE_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFE_FCCOB3_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB3_CCOBn_SHIFT                  0
+#define FTFE_FCCOB3_CCOBn_WIDTH                  8
+#define FTFE_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFE_FCCOB2_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB2_CCOBn_SHIFT                  0
+#define FTFE_FCCOB2_CCOBn_WIDTH                  8
+#define FTFE_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFE_FCCOB1_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB1_CCOBn_SHIFT                  0
+#define FTFE_FCCOB1_CCOBn_WIDTH                  8
+#define FTFE_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFE_FCCOB0_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB0_CCOBn_SHIFT                  0
+#define FTFE_FCCOB0_CCOBn_WIDTH                  8
+#define FTFE_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFE_FCCOB7_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB7_CCOBn_SHIFT                  0
+#define FTFE_FCCOB7_CCOBn_WIDTH                  8
+#define FTFE_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFE_FCCOB6_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB6_CCOBn_SHIFT                  0
+#define FTFE_FCCOB6_CCOBn_WIDTH                  8
+#define FTFE_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFE_FCCOB5_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB5_CCOBn_SHIFT                  0
+#define FTFE_FCCOB5_CCOBn_WIDTH                  8
+#define FTFE_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFE_FCCOB4_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB4_CCOBn_SHIFT                  0
+#define FTFE_FCCOB4_CCOBn_WIDTH                  8
+#define FTFE_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFE_FCCOBB_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBB_CCOBn_SHIFT                  0
+#define FTFE_FCCOBB_CCOBn_WIDTH                  8
+#define FTFE_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFE_FCCOBA_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBA_CCOBn_SHIFT                  0
+#define FTFE_FCCOBA_CCOBn_WIDTH                  8
+#define FTFE_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFE_FCCOB9_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB9_CCOBn_SHIFT                  0
+#define FTFE_FCCOB9_CCOBn_WIDTH                  8
+#define FTFE_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFE_FCCOB8_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB8_CCOBn_SHIFT                  0
+#define FTFE_FCCOB8_CCOBn_WIDTH                  8
+#define FTFE_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFE_FPROT3_PROT_MASK                    0xFFu
+#define FTFE_FPROT3_PROT_SHIFT                   0
+#define FTFE_FPROT3_PROT_WIDTH                   8
+#define FTFE_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFE_FPROT2_PROT_MASK                    0xFFu
+#define FTFE_FPROT2_PROT_SHIFT                   0
+#define FTFE_FPROT2_PROT_WIDTH                   8
+#define FTFE_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFE_FPROT1_PROT_MASK                    0xFFu
+#define FTFE_FPROT1_PROT_SHIFT                   0
+#define FTFE_FPROT1_PROT_WIDTH                   8
+#define FTFE_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFE_FPROT0_PROT_MASK                    0xFFu
+#define FTFE_FPROT0_PROT_SHIFT                   0
+#define FTFE_FPROT0_PROT_WIDTH                   8
+#define FTFE_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFE_FEPROT_EPROT_MASK                   0xFFu
+#define FTFE_FEPROT_EPROT_SHIFT                  0
+#define FTFE_FEPROT_EPROT_WIDTH                  8
+#define FTFE_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFE_FDPROT_DPROT_MASK                   0xFFu
+#define FTFE_FDPROT_DPROT_SHIFT                  0
+#define FTFE_FDPROT_DPROT_WIDTH                  8
+#define FTFE_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE                                (0x40020000u)
+/** Peripheral FTFE base pointer */
+#define FTFE                                     ((FTFE_Type *)FTFE_BASE)
+#define FTFE_BASE_PTR                            (FTFE)
+/** Array initializer of FTFE peripheral base addresses */
+#define FTFE_BASE_ADDRS                          { FTFE_BASE }
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASE_PTRS                           { FTFE }
+/** Interrupt vectors for the FTFE peripheral type */
+#define FTFE_COMMAND_COMPLETE_IRQS               { FTFE_IRQn }
+#define FTFE_READ_COLLISION_IRQS                 { Read_Collision_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register instance definitions */
+/* FTFE */
+#define FTFE_FSTAT                               FTFE_FSTAT_REG(FTFE)
+#define FTFE_FCNFG                               FTFE_FCNFG_REG(FTFE)
+#define FTFE_FSEC                                FTFE_FSEC_REG(FTFE)
+#define FTFE_FOPT                                FTFE_FOPT_REG(FTFE)
+#define FTFE_FCCOB3                              FTFE_FCCOB3_REG(FTFE)
+#define FTFE_FCCOB2                              FTFE_FCCOB2_REG(FTFE)
+#define FTFE_FCCOB1                              FTFE_FCCOB1_REG(FTFE)
+#define FTFE_FCCOB0                              FTFE_FCCOB0_REG(FTFE)
+#define FTFE_FCCOB7                              FTFE_FCCOB7_REG(FTFE)
+#define FTFE_FCCOB6                              FTFE_FCCOB6_REG(FTFE)
+#define FTFE_FCCOB5                              FTFE_FCCOB5_REG(FTFE)
+#define FTFE_FCCOB4                              FTFE_FCCOB4_REG(FTFE)
+#define FTFE_FCCOBB                              FTFE_FCCOBB_REG(FTFE)
+#define FTFE_FCCOBA                              FTFE_FCCOBA_REG(FTFE)
+#define FTFE_FCCOB9                              FTFE_FCCOB9_REG(FTFE)
+#define FTFE_FCCOB8                              FTFE_FCCOB8_REG(FTFE)
+#define FTFE_FPROT3                              FTFE_FPROT3_REG(FTFE)
+#define FTFE_FPROT2                              FTFE_FPROT2_REG(FTFE)
+#define FTFE_FPROT1                              FTFE_FPROT1_REG(FTFE)
+#define FTFE_FPROT0                              FTFE_FPROT0_REG(FTFE)
+#define FTFE_FEPROT                              FTFE_FEPROT_REG(FTFE)
+#define FTFE_FDPROT                              FTFE_FDPROT_REG(FTFE)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[8];
+  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
+  __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
+  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
+  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
+  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
+  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
+  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
+  __IO uint32_t DEADTIME;                          /**< Deadtime Insertion Control, offset: 0x68 */
+  __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
+  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
+  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
+  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
+  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+  __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
+  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
+  __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
+  __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
+  __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type, *FTM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register accessors */
+#define FTM_SC_REG(base)                         ((base)->SC)
+#define FTM_CNT_REG(base)                        ((base)->CNT)
+#define FTM_MOD_REG(base)                        ((base)->MOD)
+#define FTM_CnSC_REG(base,index)                 ((base)->CONTROLS[index].CnSC)
+#define FTM_CnSC_COUNT                           8
+#define FTM_CnV_REG(base,index)                  ((base)->CONTROLS[index].CnV)
+#define FTM_CnV_COUNT                            8
+#define FTM_CNTIN_REG(base)                      ((base)->CNTIN)
+#define FTM_STATUS_REG(base)                     ((base)->STATUS)
+#define FTM_MODE_REG(base)                       ((base)->MODE)
+#define FTM_SYNC_REG(base)                       ((base)->SYNC)
+#define FTM_OUTINIT_REG(base)                    ((base)->OUTINIT)
+#define FTM_OUTMASK_REG(base)                    ((base)->OUTMASK)
+#define FTM_COMBINE_REG(base)                    ((base)->COMBINE)
+#define FTM_DEADTIME_REG(base)                   ((base)->DEADTIME)
+#define FTM_EXTTRIG_REG(base)                    ((base)->EXTTRIG)
+#define FTM_POL_REG(base)                        ((base)->POL)
+#define FTM_FMS_REG(base)                        ((base)->FMS)
+#define FTM_FILTER_REG(base)                     ((base)->FILTER)
+#define FTM_FLTCTRL_REG(base)                    ((base)->FLTCTRL)
+#define FTM_QDCTRL_REG(base)                     ((base)->QDCTRL)
+#define FTM_CONF_REG(base)                       ((base)->CONF)
+#define FTM_FLTPOL_REG(base)                     ((base)->FLTPOL)
+#define FTM_SYNCONF_REG(base)                    ((base)->SYNCONF)
+#define FTM_INVCTRL_REG(base)                    ((base)->INVCTRL)
+#define FTM_SWOCTRL_REG(base)                    ((base)->SWOCTRL)
+#define FTM_PWMLOAD_REG(base)                    ((base)->PWMLOAD)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK                           0x7u
+#define FTM_SC_PS_SHIFT                          0
+#define FTM_SC_PS_WIDTH                          3
+#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK                         0x18u
+#define FTM_SC_CLKS_SHIFT                        3
+#define FTM_SC_CLKS_WIDTH                        2
+#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK                        0x20u
+#define FTM_SC_CPWMS_SHIFT                       5
+#define FTM_SC_CPWMS_WIDTH                       1
+#define FTM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK                         0x40u
+#define FTM_SC_TOIE_SHIFT                        6
+#define FTM_SC_TOIE_WIDTH                        1
+#define FTM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK                          0x80u
+#define FTM_SC_TOF_SHIFT                         7
+#define FTM_SC_TOF_WIDTH                         1
+#define FTM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK                       0xFFFFu
+#define FTM_CNT_COUNT_SHIFT                      0
+#define FTM_CNT_COUNT_WIDTH                      16
+#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK                         0xFFFFu
+#define FTM_MOD_MOD_SHIFT                        0
+#define FTM_MOD_MOD_WIDTH                        16
+#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK                        0x1u
+#define FTM_CnSC_DMA_SHIFT                       0
+#define FTM_CnSC_DMA_WIDTH                       1
+#define FTM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ELSA_MASK                       0x4u
+#define FTM_CnSC_ELSA_SHIFT                      2
+#define FTM_CnSC_ELSA_WIDTH                      1
+#define FTM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK                       0x8u
+#define FTM_CnSC_ELSB_SHIFT                      3
+#define FTM_CnSC_ELSB_WIDTH                      1
+#define FTM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK                        0x10u
+#define FTM_CnSC_MSA_SHIFT                       4
+#define FTM_CnSC_MSA_WIDTH                       1
+#define FTM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK                        0x20u
+#define FTM_CnSC_MSB_SHIFT                       5
+#define FTM_CnSC_MSB_WIDTH                       1
+#define FTM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK                       0x40u
+#define FTM_CnSC_CHIE_SHIFT                      6
+#define FTM_CnSC_CHIE_WIDTH                      1
+#define FTM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK                        0x80u
+#define FTM_CnSC_CHF_SHIFT                       7
+#define FTM_CnSC_CHF_WIDTH                       1
+#define FTM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK                         0xFFFFu
+#define FTM_CnV_VAL_SHIFT                        0
+#define FTM_CnV_VAL_WIDTH                        16
+#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK                      0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT                     0
+#define FTM_CNTIN_INIT_WIDTH                     16
+#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK                     0x1u
+#define FTM_STATUS_CH0F_SHIFT                    0
+#define FTM_STATUS_CH0F_WIDTH                    1
+#define FTM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK                     0x2u
+#define FTM_STATUS_CH1F_SHIFT                    1
+#define FTM_STATUS_CH1F_WIDTH                    1
+#define FTM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK                     0x4u
+#define FTM_STATUS_CH2F_SHIFT                    2
+#define FTM_STATUS_CH2F_WIDTH                    1
+#define FTM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK                     0x8u
+#define FTM_STATUS_CH3F_SHIFT                    3
+#define FTM_STATUS_CH3F_WIDTH                    1
+#define FTM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK                     0x10u
+#define FTM_STATUS_CH4F_SHIFT                    4
+#define FTM_STATUS_CH4F_WIDTH                    1
+#define FTM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK                     0x20u
+#define FTM_STATUS_CH5F_SHIFT                    5
+#define FTM_STATUS_CH5F_WIDTH                    1
+#define FTM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK                     0x40u
+#define FTM_STATUS_CH6F_SHIFT                    6
+#define FTM_STATUS_CH6F_WIDTH                    1
+#define FTM_STATUS_CH6F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK                     0x80u
+#define FTM_STATUS_CH7F_SHIFT                    7
+#define FTM_STATUS_CH7F_WIDTH                    1
+#define FTM_STATUS_CH7F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK                      0x1u
+#define FTM_MODE_FTMEN_SHIFT                     0
+#define FTM_MODE_FTMEN_WIDTH                     1
+#define FTM_MODE_FTMEN(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK                       0x2u
+#define FTM_MODE_INIT_SHIFT                      1
+#define FTM_MODE_INIT_WIDTH                      1
+#define FTM_MODE_INIT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK                      0x4u
+#define FTM_MODE_WPDIS_SHIFT                     2
+#define FTM_MODE_WPDIS_WIDTH                     1
+#define FTM_MODE_WPDIS(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK                    0x8u
+#define FTM_MODE_PWMSYNC_SHIFT                   3
+#define FTM_MODE_PWMSYNC_WIDTH                   1
+#define FTM_MODE_PWMSYNC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK                    0x10u
+#define FTM_MODE_CAPTEST_SHIFT                   4
+#define FTM_MODE_CAPTEST_WIDTH                   1
+#define FTM_MODE_CAPTEST(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK                     0x60u
+#define FTM_MODE_FAULTM_SHIFT                    5
+#define FTM_MODE_FAULTM_WIDTH                    2
+#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK                    0x80u
+#define FTM_MODE_FAULTIE_SHIFT                   7
+#define FTM_MODE_FAULTIE_WIDTH                   1
+#define FTM_MODE_FAULTIE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK                     0x1u
+#define FTM_SYNC_CNTMIN_SHIFT                    0
+#define FTM_SYNC_CNTMIN_WIDTH                    1
+#define FTM_SYNC_CNTMIN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK                     0x2u
+#define FTM_SYNC_CNTMAX_SHIFT                    1
+#define FTM_SYNC_CNTMAX_WIDTH                    1
+#define FTM_SYNC_CNTMAX(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK                     0x4u
+#define FTM_SYNC_REINIT_SHIFT                    2
+#define FTM_SYNC_REINIT_WIDTH                    1
+#define FTM_SYNC_REINIT(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK                    0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT                   3
+#define FTM_SYNC_SYNCHOM_WIDTH                   1
+#define FTM_SYNC_SYNCHOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK                      0x10u
+#define FTM_SYNC_TRIG0_SHIFT                     4
+#define FTM_SYNC_TRIG0_WIDTH                     1
+#define FTM_SYNC_TRIG0(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK                      0x20u
+#define FTM_SYNC_TRIG1_SHIFT                     5
+#define FTM_SYNC_TRIG1_WIDTH                     1
+#define FTM_SYNC_TRIG1(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK                      0x40u
+#define FTM_SYNC_TRIG2_SHIFT                     6
+#define FTM_SYNC_TRIG2_WIDTH                     1
+#define FTM_SYNC_TRIG2(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK                     0x80u
+#define FTM_SYNC_SWSYNC_SHIFT                    7
+#define FTM_SYNC_SWSYNC_WIDTH                    1
+#define FTM_SYNC_SWSYNC(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK                   0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT                  0
+#define FTM_OUTINIT_CH0OI_WIDTH                  1
+#define FTM_OUTINIT_CH0OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK                   0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT                  1
+#define FTM_OUTINIT_CH1OI_WIDTH                  1
+#define FTM_OUTINIT_CH1OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK                   0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT                  2
+#define FTM_OUTINIT_CH2OI_WIDTH                  1
+#define FTM_OUTINIT_CH2OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK                   0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT                  3
+#define FTM_OUTINIT_CH3OI_WIDTH                  1
+#define FTM_OUTINIT_CH3OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK                   0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT                  4
+#define FTM_OUTINIT_CH4OI_WIDTH                  1
+#define FTM_OUTINIT_CH4OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK                   0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT                  5
+#define FTM_OUTINIT_CH5OI_WIDTH                  1
+#define FTM_OUTINIT_CH5OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK                   0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT                  6
+#define FTM_OUTINIT_CH6OI_WIDTH                  1
+#define FTM_OUTINIT_CH6OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK                   0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT                  7
+#define FTM_OUTINIT_CH7OI_WIDTH                  1
+#define FTM_OUTINIT_CH7OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK                   0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT                  0
+#define FTM_OUTMASK_CH0OM_WIDTH                  1
+#define FTM_OUTMASK_CH0OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK                   0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT                  1
+#define FTM_OUTMASK_CH1OM_WIDTH                  1
+#define FTM_OUTMASK_CH1OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK                   0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT                  2
+#define FTM_OUTMASK_CH2OM_WIDTH                  1
+#define FTM_OUTMASK_CH2OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK                   0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT                  3
+#define FTM_OUTMASK_CH3OM_WIDTH                  1
+#define FTM_OUTMASK_CH3OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK                   0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT                  4
+#define FTM_OUTMASK_CH4OM_WIDTH                  1
+#define FTM_OUTMASK_CH4OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK                   0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT                  5
+#define FTM_OUTMASK_CH5OM_WIDTH                  1
+#define FTM_OUTMASK_CH5OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK                   0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT                  6
+#define FTM_OUTMASK_CH6OM_WIDTH                  1
+#define FTM_OUTMASK_CH6OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK                   0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT                  7
+#define FTM_OUTMASK_CH7OM_WIDTH                  1
+#define FTM_OUTMASK_CH7OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK                0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT               0
+#define FTM_COMBINE_COMBINE0_WIDTH               1
+#define FTM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK                   0x2u
+#define FTM_COMBINE_COMP0_SHIFT                  1
+#define FTM_COMBINE_COMP0_WIDTH                  1
+#define FTM_COMBINE_COMP0(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK                0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT               2
+#define FTM_COMBINE_DECAPEN0_WIDTH               1
+#define FTM_COMBINE_DECAPEN0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK                  0x8u
+#define FTM_COMBINE_DECAP0_SHIFT                 3
+#define FTM_COMBINE_DECAP0_WIDTH                 1
+#define FTM_COMBINE_DECAP0(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK                   0x10u
+#define FTM_COMBINE_DTEN0_SHIFT                  4
+#define FTM_COMBINE_DTEN0_WIDTH                  1
+#define FTM_COMBINE_DTEN0(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK                 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT                5
+#define FTM_COMBINE_SYNCEN0_WIDTH                1
+#define FTM_COMBINE_SYNCEN0(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK                0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT               6
+#define FTM_COMBINE_FAULTEN0_WIDTH               1
+#define FTM_COMBINE_FAULTEN0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK                0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT               8
+#define FTM_COMBINE_COMBINE1_WIDTH               1
+#define FTM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK                   0x200u
+#define FTM_COMBINE_COMP1_SHIFT                  9
+#define FTM_COMBINE_COMP1_WIDTH                  1
+#define FTM_COMBINE_COMP1(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK                0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT               10
+#define FTM_COMBINE_DECAPEN1_WIDTH               1
+#define FTM_COMBINE_DECAPEN1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK                  0x800u
+#define FTM_COMBINE_DECAP1_SHIFT                 11
+#define FTM_COMBINE_DECAP1_WIDTH                 1
+#define FTM_COMBINE_DECAP1(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK                   0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT                  12
+#define FTM_COMBINE_DTEN1_WIDTH                  1
+#define FTM_COMBINE_DTEN1(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK                 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT                13
+#define FTM_COMBINE_SYNCEN1_WIDTH                1
+#define FTM_COMBINE_SYNCEN1(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK                0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT               14
+#define FTM_COMBINE_FAULTEN1_WIDTH               1
+#define FTM_COMBINE_FAULTEN1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK                0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT               16
+#define FTM_COMBINE_COMBINE2_WIDTH               1
+#define FTM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK                   0x20000u
+#define FTM_COMBINE_COMP2_SHIFT                  17
+#define FTM_COMBINE_COMP2_WIDTH                  1
+#define FTM_COMBINE_COMP2(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK                0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT               18
+#define FTM_COMBINE_DECAPEN2_WIDTH               1
+#define FTM_COMBINE_DECAPEN2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK                  0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT                 19
+#define FTM_COMBINE_DECAP2_WIDTH                 1
+#define FTM_COMBINE_DECAP2(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK                   0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT                  20
+#define FTM_COMBINE_DTEN2_WIDTH                  1
+#define FTM_COMBINE_DTEN2(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK                 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT                21
+#define FTM_COMBINE_SYNCEN2_WIDTH                1
+#define FTM_COMBINE_SYNCEN2(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK                0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT               22
+#define FTM_COMBINE_FAULTEN2_WIDTH               1
+#define FTM_COMBINE_FAULTEN2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK                0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT               24
+#define FTM_COMBINE_COMBINE3_WIDTH               1
+#define FTM_COMBINE_COMBINE3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK                   0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT                  25
+#define FTM_COMBINE_COMP3_WIDTH                  1
+#define FTM_COMBINE_COMP3(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK                0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT               26
+#define FTM_COMBINE_DECAPEN3_WIDTH               1
+#define FTM_COMBINE_DECAPEN3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK                  0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT                 27
+#define FTM_COMBINE_DECAP3_WIDTH                 1
+#define FTM_COMBINE_DECAP3(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK                   0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT                  28
+#define FTM_COMBINE_DTEN3_WIDTH                  1
+#define FTM_COMBINE_DTEN3(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK                 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT                29
+#define FTM_COMBINE_SYNCEN3_WIDTH                1
+#define FTM_COMBINE_SYNCEN3(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK                0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT               30
+#define FTM_COMBINE_FAULTEN3_WIDTH               1
+#define FTM_COMBINE_FAULTEN3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK                  0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT                 0
+#define FTM_DEADTIME_DTVAL_WIDTH                 6
+#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK                   0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT                  6
+#define FTM_DEADTIME_DTPS_WIDTH                  2
+#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK                 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT                0
+#define FTM_EXTTRIG_CH2TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH2TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK                 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT                1
+#define FTM_EXTTRIG_CH3TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH3TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK                 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT                2
+#define FTM_EXTTRIG_CH4TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH4TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK                 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT                3
+#define FTM_EXTTRIG_CH5TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH5TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK                 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT                4
+#define FTM_EXTTRIG_CH0TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH0TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK                 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT                5
+#define FTM_EXTTRIG_CH1TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH1TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK              0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT             6
+#define FTM_EXTTRIG_INITTRIGEN_WIDTH             1
+#define FTM_EXTTRIG_INITTRIGEN(x)                (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK                   0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT                  7
+#define FTM_EXTTRIG_TRIGF_WIDTH                  1
+#define FTM_EXTTRIG_TRIGF(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK                        0x1u
+#define FTM_POL_POL0_SHIFT                       0
+#define FTM_POL_POL0_WIDTH                       1
+#define FTM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK                        0x2u
+#define FTM_POL_POL1_SHIFT                       1
+#define FTM_POL_POL1_WIDTH                       1
+#define FTM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK                        0x4u
+#define FTM_POL_POL2_SHIFT                       2
+#define FTM_POL_POL2_WIDTH                       1
+#define FTM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK                        0x8u
+#define FTM_POL_POL3_SHIFT                       3
+#define FTM_POL_POL3_WIDTH                       1
+#define FTM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK                        0x10u
+#define FTM_POL_POL4_SHIFT                       4
+#define FTM_POL_POL4_WIDTH                       1
+#define FTM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK                        0x20u
+#define FTM_POL_POL5_SHIFT                       5
+#define FTM_POL_POL5_WIDTH                       1
+#define FTM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK                        0x40u
+#define FTM_POL_POL6_SHIFT                       6
+#define FTM_POL_POL6_WIDTH                       1
+#define FTM_POL_POL6(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK                        0x80u
+#define FTM_POL_POL7_SHIFT                       7
+#define FTM_POL_POL7_WIDTH                       1
+#define FTM_POL_POL7(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK                     0x1u
+#define FTM_FMS_FAULTF0_SHIFT                    0
+#define FTM_FMS_FAULTF0_WIDTH                    1
+#define FTM_FMS_FAULTF0(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK                     0x2u
+#define FTM_FMS_FAULTF1_SHIFT                    1
+#define FTM_FMS_FAULTF1_WIDTH                    1
+#define FTM_FMS_FAULTF1(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK                     0x4u
+#define FTM_FMS_FAULTF2_SHIFT                    2
+#define FTM_FMS_FAULTF2_WIDTH                    1
+#define FTM_FMS_FAULTF2(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK                     0x8u
+#define FTM_FMS_FAULTF3_SHIFT                    3
+#define FTM_FMS_FAULTF3_WIDTH                    1
+#define FTM_FMS_FAULTF3(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK                     0x20u
+#define FTM_FMS_FAULTIN_SHIFT                    5
+#define FTM_FMS_FAULTIN_WIDTH                    1
+#define FTM_FMS_FAULTIN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK                        0x40u
+#define FTM_FMS_WPEN_SHIFT                       6
+#define FTM_FMS_WPEN_WIDTH                       1
+#define FTM_FMS_WPEN(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK                      0x80u
+#define FTM_FMS_FAULTF_SHIFT                     7
+#define FTM_FMS_FAULTF_WIDTH                     1
+#define FTM_FMS_FAULTF(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK                  0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT                 0
+#define FTM_FILTER_CH0FVAL_WIDTH                 4
+#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK                  0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT                 4
+#define FTM_FILTER_CH1FVAL_WIDTH                 4
+#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK                  0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT                 8
+#define FTM_FILTER_CH2FVAL_WIDTH                 4
+#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK                  0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT                 12
+#define FTM_FILTER_CH3FVAL_WIDTH                 4
+#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK                0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT               0
+#define FTM_FLTCTRL_FAULT0EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT0EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK                0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT               1
+#define FTM_FLTCTRL_FAULT1EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT1EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK                0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT               2
+#define FTM_FLTCTRL_FAULT2EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT2EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK                0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT               3
+#define FTM_FLTCTRL_FAULT3EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT3EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK                0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT               4
+#define FTM_FLTCTRL_FFLTR0EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR0EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK                0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT               5
+#define FTM_FLTCTRL_FFLTR1EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR1EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK                0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT               6
+#define FTM_FLTCTRL_FFLTR2EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR2EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK                0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT               7
+#define FTM_FLTCTRL_FFLTR3EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR3EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK                   0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT                  8
+#define FTM_FLTCTRL_FFVAL_WIDTH                  4
+#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK                   0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT                  0
+#define FTM_QDCTRL_QUADEN_WIDTH                  1
+#define FTM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK                   0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT                  1
+#define FTM_QDCTRL_TOFDIR_WIDTH                  1
+#define FTM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK                   0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT                  2
+#define FTM_QDCTRL_QUADIR_WIDTH                  1
+#define FTM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK                 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT                3
+#define FTM_QDCTRL_QUADMODE_WIDTH                1
+#define FTM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK                   0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT                  4
+#define FTM_QDCTRL_PHBPOL_WIDTH                  1
+#define FTM_QDCTRL_PHBPOL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK                   0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT                  5
+#define FTM_QDCTRL_PHAPOL_WIDTH                  1
+#define FTM_QDCTRL_PHAPOL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK                0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT               6
+#define FTM_QDCTRL_PHBFLTREN_WIDTH               1
+#define FTM_QDCTRL_PHBFLTREN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK                0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT               7
+#define FTM_QDCTRL_PHAFLTREN_WIDTH               1
+#define FTM_QDCTRL_PHAFLTREN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK                     0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT                    0
+#define FTM_CONF_NUMTOF_WIDTH                    5
+#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK                    0xC0u
+#define FTM_CONF_BDMMODE_SHIFT                   6
+#define FTM_CONF_BDMMODE_WIDTH                   2
+#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK                     0x200u
+#define FTM_CONF_GTBEEN_SHIFT                    9
+#define FTM_CONF_GTBEEN_WIDTH                    1
+#define FTM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK                    0x400u
+#define FTM_CONF_GTBEOUT_SHIFT                   10
+#define FTM_CONF_GTBEOUT_WIDTH                   1
+#define FTM_CONF_GTBEOUT(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK                  0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT                 0
+#define FTM_FLTPOL_FLT0POL_WIDTH                 1
+#define FTM_FLTPOL_FLT0POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK                  0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT                 1
+#define FTM_FLTPOL_FLT1POL_WIDTH                 1
+#define FTM_FLTPOL_FLT1POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK                  0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT                 2
+#define FTM_FLTPOL_FLT2POL_WIDTH                 1
+#define FTM_FLTPOL_FLT2POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK                  0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT                 3
+#define FTM_FLTPOL_FLT3POL_WIDTH                 1
+#define FTM_FLTPOL_FLT3POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK              0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT             0
+#define FTM_SYNCONF_HWTRIGMODE_WIDTH             1
+#define FTM_SYNCONF_HWTRIGMODE(x)                (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK                  0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT                 2
+#define FTM_SYNCONF_CNTINC_WIDTH                 1
+#define FTM_SYNCONF_CNTINC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK                    0x10u
+#define FTM_SYNCONF_INVC_SHIFT                   4
+#define FTM_SYNCONF_INVC_WIDTH                   1
+#define FTM_SYNCONF_INVC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK                    0x20u
+#define FTM_SYNCONF_SWOC_SHIFT                   5
+#define FTM_SYNCONF_SWOC_WIDTH                   1
+#define FTM_SYNCONF_SWOC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK                0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT               7
+#define FTM_SYNCONF_SYNCMODE_WIDTH               1
+#define FTM_SYNCONF_SYNCMODE(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK                0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT               8
+#define FTM_SYNCONF_SWRSTCNT_WIDTH               1
+#define FTM_SYNCONF_SWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK                 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT                9
+#define FTM_SYNCONF_SWWRBUF_WIDTH                1
+#define FTM_SYNCONF_SWWRBUF(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK                    0x400u
+#define FTM_SYNCONF_SWOM_SHIFT                   10
+#define FTM_SYNCONF_SWOM_WIDTH                   1
+#define FTM_SYNCONF_SWOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK                  0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT                 11
+#define FTM_SYNCONF_SWINVC_WIDTH                 1
+#define FTM_SYNCONF_SWINVC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK                   0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT                  12
+#define FTM_SYNCONF_SWSOC_WIDTH                  1
+#define FTM_SYNCONF_SWSOC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK                0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT               16
+#define FTM_SYNCONF_HWRSTCNT_WIDTH               1
+#define FTM_SYNCONF_HWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK                 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT                17
+#define FTM_SYNCONF_HWWRBUF_WIDTH                1
+#define FTM_SYNCONF_HWWRBUF(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK                    0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT                   18
+#define FTM_SYNCONF_HWOM_WIDTH                   1
+#define FTM_SYNCONF_HWOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK                  0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT                 19
+#define FTM_SYNCONF_HWINVC_WIDTH                 1
+#define FTM_SYNCONF_HWINVC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK                   0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT                  20
+#define FTM_SYNCONF_HWSOC_WIDTH                  1
+#define FTM_SYNCONF_HWSOC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK                  0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT                 0
+#define FTM_INVCTRL_INV0EN_WIDTH                 1
+#define FTM_INVCTRL_INV0EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK                  0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT                 1
+#define FTM_INVCTRL_INV1EN_WIDTH                 1
+#define FTM_INVCTRL_INV1EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK                  0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT                 2
+#define FTM_INVCTRL_INV2EN_WIDTH                 1
+#define FTM_INVCTRL_INV2EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK                  0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT                 3
+#define FTM_INVCTRL_INV3EN_WIDTH                 1
+#define FTM_INVCTRL_INV3EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK                   0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT                  0
+#define FTM_SWOCTRL_CH0OC_WIDTH                  1
+#define FTM_SWOCTRL_CH0OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK                   0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT                  1
+#define FTM_SWOCTRL_CH1OC_WIDTH                  1
+#define FTM_SWOCTRL_CH1OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK                   0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT                  2
+#define FTM_SWOCTRL_CH2OC_WIDTH                  1
+#define FTM_SWOCTRL_CH2OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK                   0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT                  3
+#define FTM_SWOCTRL_CH3OC_WIDTH                  1
+#define FTM_SWOCTRL_CH3OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK                   0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT                  4
+#define FTM_SWOCTRL_CH4OC_WIDTH                  1
+#define FTM_SWOCTRL_CH4OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK                   0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT                  5
+#define FTM_SWOCTRL_CH5OC_WIDTH                  1
+#define FTM_SWOCTRL_CH5OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK                   0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT                  6
+#define FTM_SWOCTRL_CH6OC_WIDTH                  1
+#define FTM_SWOCTRL_CH6OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK                   0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT                  7
+#define FTM_SWOCTRL_CH7OC_WIDTH                  1
+#define FTM_SWOCTRL_CH7OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK                  0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT                 8
+#define FTM_SWOCTRL_CH0OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH0OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK                  0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT                 9
+#define FTM_SWOCTRL_CH1OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH1OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK                  0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT                 10
+#define FTM_SWOCTRL_CH2OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH2OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK                  0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT                 11
+#define FTM_SWOCTRL_CH3OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH3OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK                  0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT                 12
+#define FTM_SWOCTRL_CH4OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH4OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK                  0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT                 13
+#define FTM_SWOCTRL_CH5OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH5OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK                  0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT                 14
+#define FTM_SWOCTRL_CH6OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH6OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK                  0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT                 15
+#define FTM_SWOCTRL_CH7OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH7OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK                  0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT                 0
+#define FTM_PWMLOAD_CH0SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH0SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK                  0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT                 1
+#define FTM_PWMLOAD_CH1SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH1SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK                  0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT                 2
+#define FTM_PWMLOAD_CH2SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH2SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK                  0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT                 3
+#define FTM_PWMLOAD_CH3SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH3SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK                  0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT                 4
+#define FTM_PWMLOAD_CH4SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH4SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK                  0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT                 5
+#define FTM_PWMLOAD_CH5SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH5SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK                  0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT                 6
+#define FTM_PWMLOAD_CH6SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH6SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK                  0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT                 7
+#define FTM_PWMLOAD_CH7SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH7SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK                    0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT                   9
+#define FTM_PWMLOAD_LDOK_WIDTH                   1
+#define FTM_PWMLOAD_LDOK(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE                                (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0                                     ((FTM_Type *)FTM0_BASE)
+#define FTM0_BASE_PTR                            (FTM0)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE                                (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1                                     ((FTM_Type *)FTM1_BASE)
+#define FTM1_BASE_PTR                            (FTM1)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE                                (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2                                     ((FTM_Type *)FTM2_BASE)
+#define FTM2_BASE_PTR                            (FTM2)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE                                (0x400B9000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3                                     ((FTM_Type *)FTM3_BASE)
+#define FTM3_BASE_PTR                            (FTM3)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS                           { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS                            { FTM0, FTM1, FTM2, FTM3 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS                                 { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register instance definitions */
+/* FTM0 */
+#define FTM0_SC                                  FTM_SC_REG(FTM0)
+#define FTM0_CNT                                 FTM_CNT_REG(FTM0)
+#define FTM0_MOD                                 FTM_MOD_REG(FTM0)
+#define FTM0_C0SC                                FTM_CnSC_REG(FTM0,0)
+#define FTM0_C0V                                 FTM_CnV_REG(FTM0,0)
+#define FTM0_C1SC                                FTM_CnSC_REG(FTM0,1)
+#define FTM0_C1V                                 FTM_CnV_REG(FTM0,1)
+#define FTM0_C2SC                                FTM_CnSC_REG(FTM0,2)
+#define FTM0_C2V                                 FTM_CnV_REG(FTM0,2)
+#define FTM0_C3SC                                FTM_CnSC_REG(FTM0,3)
+#define FTM0_C3V                                 FTM_CnV_REG(FTM0,3)
+#define FTM0_C4SC                                FTM_CnSC_REG(FTM0,4)
+#define FTM0_C4V                                 FTM_CnV_REG(FTM0,4)
+#define FTM0_C5SC                                FTM_CnSC_REG(FTM0,5)
+#define FTM0_C5V                                 FTM_CnV_REG(FTM0,5)
+#define FTM0_C6SC                                FTM_CnSC_REG(FTM0,6)
+#define FTM0_C6V                                 FTM_CnV_REG(FTM0,6)
+#define FTM0_C7SC                                FTM_CnSC_REG(FTM0,7)
+#define FTM0_C7V                                 FTM_CnV_REG(FTM0,7)
+#define FTM0_CNTIN                               FTM_CNTIN_REG(FTM0)
+#define FTM0_STATUS                              FTM_STATUS_REG(FTM0)
+#define FTM0_MODE                                FTM_MODE_REG(FTM0)
+#define FTM0_SYNC                                FTM_SYNC_REG(FTM0)
+#define FTM0_OUTINIT                             FTM_OUTINIT_REG(FTM0)
+#define FTM0_OUTMASK                             FTM_OUTMASK_REG(FTM0)
+#define FTM0_COMBINE                             FTM_COMBINE_REG(FTM0)
+#define FTM0_DEADTIME                            FTM_DEADTIME_REG(FTM0)
+#define FTM0_EXTTRIG                             FTM_EXTTRIG_REG(FTM0)
+#define FTM0_POL                                 FTM_POL_REG(FTM0)
+#define FTM0_FMS                                 FTM_FMS_REG(FTM0)
+#define FTM0_FILTER                              FTM_FILTER_REG(FTM0)
+#define FTM0_FLTCTRL                             FTM_FLTCTRL_REG(FTM0)
+#define FTM0_QDCTRL                              FTM_QDCTRL_REG(FTM0)
+#define FTM0_CONF                                FTM_CONF_REG(FTM0)
+#define FTM0_FLTPOL                              FTM_FLTPOL_REG(FTM0)
+#define FTM0_SYNCONF                             FTM_SYNCONF_REG(FTM0)
+#define FTM0_INVCTRL                             FTM_INVCTRL_REG(FTM0)
+#define FTM0_SWOCTRL                             FTM_SWOCTRL_REG(FTM0)
+#define FTM0_PWMLOAD                             FTM_PWMLOAD_REG(FTM0)
+/* FTM1 */
+#define FTM1_SC                                  FTM_SC_REG(FTM1)
+#define FTM1_CNT                                 FTM_CNT_REG(FTM1)
+#define FTM1_MOD                                 FTM_MOD_REG(FTM1)
+#define FTM1_C0SC                                FTM_CnSC_REG(FTM1,0)
+#define FTM1_C0V                                 FTM_CnV_REG(FTM1,0)
+#define FTM1_C1SC                                FTM_CnSC_REG(FTM1,1)
+#define FTM1_C1V                                 FTM_CnV_REG(FTM1,1)
+#define FTM1_CNTIN                               FTM_CNTIN_REG(FTM1)
+#define FTM1_STATUS                              FTM_STATUS_REG(FTM1)
+#define FTM1_MODE                                FTM_MODE_REG(FTM1)
+#define FTM1_SYNC                                FTM_SYNC_REG(FTM1)
+#define FTM1_OUTINIT                             FTM_OUTINIT_REG(FTM1)
+#define FTM1_OUTMASK                             FTM_OUTMASK_REG(FTM1)
+#define FTM1_COMBINE                             FTM_COMBINE_REG(FTM1)
+#define FTM1_DEADTIME                            FTM_DEADTIME_REG(FTM1)
+#define FTM1_EXTTRIG                             FTM_EXTTRIG_REG(FTM1)
+#define FTM1_POL                                 FTM_POL_REG(FTM1)
+#define FTM1_FMS                                 FTM_FMS_REG(FTM1)
+#define FTM1_FILTER                              FTM_FILTER_REG(FTM1)
+#define FTM1_FLTCTRL                             FTM_FLTCTRL_REG(FTM1)
+#define FTM1_QDCTRL                              FTM_QDCTRL_REG(FTM1)
+#define FTM1_CONF                                FTM_CONF_REG(FTM1)
+#define FTM1_FLTPOL                              FTM_FLTPOL_REG(FTM1)
+#define FTM1_SYNCONF                             FTM_SYNCONF_REG(FTM1)
+#define FTM1_INVCTRL                             FTM_INVCTRL_REG(FTM1)
+#define FTM1_SWOCTRL                             FTM_SWOCTRL_REG(FTM1)
+#define FTM1_PWMLOAD                             FTM_PWMLOAD_REG(FTM1)
+/* FTM2 */
+#define FTM2_SC                                  FTM_SC_REG(FTM2)
+#define FTM2_CNT                                 FTM_CNT_REG(FTM2)
+#define FTM2_MOD                                 FTM_MOD_REG(FTM2)
+#define FTM2_C0SC                                FTM_CnSC_REG(FTM2,0)
+#define FTM2_C0V                                 FTM_CnV_REG(FTM2,0)
+#define FTM2_C1SC                                FTM_CnSC_REG(FTM2,1)
+#define FTM2_C1V                                 FTM_CnV_REG(FTM2,1)
+#define FTM2_CNTIN                               FTM_CNTIN_REG(FTM2)
+#define FTM2_STATUS                              FTM_STATUS_REG(FTM2)
+#define FTM2_MODE                                FTM_MODE_REG(FTM2)
+#define FTM2_SYNC                                FTM_SYNC_REG(FTM2)
+#define FTM2_OUTINIT                             FTM_OUTINIT_REG(FTM2)
+#define FTM2_OUTMASK                             FTM_OUTMASK_REG(FTM2)
+#define FTM2_COMBINE                             FTM_COMBINE_REG(FTM2)
+#define FTM2_DEADTIME                            FTM_DEADTIME_REG(FTM2)
+#define FTM2_EXTTRIG                             FTM_EXTTRIG_REG(FTM2)
+#define FTM2_POL                                 FTM_POL_REG(FTM2)
+#define FTM2_FMS                                 FTM_FMS_REG(FTM2)
+#define FTM2_FILTER                              FTM_FILTER_REG(FTM2)
+#define FTM2_FLTCTRL                             FTM_FLTCTRL_REG(FTM2)
+#define FTM2_QDCTRL                              FTM_QDCTRL_REG(FTM2)
+#define FTM2_CONF                                FTM_CONF_REG(FTM2)
+#define FTM2_FLTPOL                              FTM_FLTPOL_REG(FTM2)
+#define FTM2_SYNCONF                             FTM_SYNCONF_REG(FTM2)
+#define FTM2_INVCTRL                             FTM_INVCTRL_REG(FTM2)
+#define FTM2_SWOCTRL                             FTM_SWOCTRL_REG(FTM2)
+#define FTM2_PWMLOAD                             FTM_PWMLOAD_REG(FTM2)
+/* FTM3 */
+#define FTM3_SC                                  FTM_SC_REG(FTM3)
+#define FTM3_CNT                                 FTM_CNT_REG(FTM3)
+#define FTM3_MOD                                 FTM_MOD_REG(FTM3)
+#define FTM3_C0SC                                FTM_CnSC_REG(FTM3,0)
+#define FTM3_C0V                                 FTM_CnV_REG(FTM3,0)
+#define FTM3_C1SC                                FTM_CnSC_REG(FTM3,1)
+#define FTM3_C1V                                 FTM_CnV_REG(FTM3,1)
+#define FTM3_C2SC                                FTM_CnSC_REG(FTM3,2)
+#define FTM3_C2V                                 FTM_CnV_REG(FTM3,2)
+#define FTM3_C3SC                                FTM_CnSC_REG(FTM3,3)
+#define FTM3_C3V                                 FTM_CnV_REG(FTM3,3)
+#define FTM3_C4SC                                FTM_CnSC_REG(FTM3,4)
+#define FTM3_C4V                                 FTM_CnV_REG(FTM3,4)
+#define FTM3_C5SC                                FTM_CnSC_REG(FTM3,5)
+#define FTM3_C5V                                 FTM_CnV_REG(FTM3,5)
+#define FTM3_C6SC                                FTM_CnSC_REG(FTM3,6)
+#define FTM3_C6V                                 FTM_CnV_REG(FTM3,6)
+#define FTM3_C7SC                                FTM_CnSC_REG(FTM3,7)
+#define FTM3_C7V                                 FTM_CnV_REG(FTM3,7)
+#define FTM3_CNTIN                               FTM_CNTIN_REG(FTM3)
+#define FTM3_STATUS                              FTM_STATUS_REG(FTM3)
+#define FTM3_MODE                                FTM_MODE_REG(FTM3)
+#define FTM3_SYNC                                FTM_SYNC_REG(FTM3)
+#define FTM3_OUTINIT                             FTM_OUTINIT_REG(FTM3)
+#define FTM3_OUTMASK                             FTM_OUTMASK_REG(FTM3)
+#define FTM3_COMBINE                             FTM_COMBINE_REG(FTM3)
+#define FTM3_DEADTIME                            FTM_DEADTIME_REG(FTM3)
+#define FTM3_EXTTRIG                             FTM_EXTTRIG_REG(FTM3)
+#define FTM3_POL                                 FTM_POL_REG(FTM3)
+#define FTM3_FMS                                 FTM_FMS_REG(FTM3)
+#define FTM3_FILTER                              FTM_FILTER_REG(FTM3)
+#define FTM3_FLTCTRL                             FTM_FLTCTRL_REG(FTM3)
+#define FTM3_QDCTRL                              FTM_QDCTRL_REG(FTM3)
+#define FTM3_CONF                                FTM_CONF_REG(FTM3)
+#define FTM3_FLTPOL                              FTM_FLTPOL_REG(FTM3)
+#define FTM3_SYNCONF                             FTM_SYNCONF_REG(FTM3)
+#define FTM3_INVCTRL                             FTM_INVCTRL_REG(FTM3)
+#define FTM3_SWOCTRL                             FTM_SWOCTRL_REG(FTM3)
+#define FTM3_PWMLOAD                             FTM_PWMLOAD_REG(FTM3)
+
+/* FTM - Register array accessors */
+#define FTM0_CnSC(index)                         FTM_CnSC_REG(FTM0,index)
+#define FTM1_CnSC(index)                         FTM_CnSC_REG(FTM1,index)
+#define FTM2_CnSC(index)                         FTM_CnSC_REG(FTM2,index)
+#define FTM3_CnSC(index)                         FTM_CnSC_REG(FTM3,index)
+#define FTM0_CnV(index)                          FTM_CnV_REG(FTM0,index)
+#define FTM1_CnV(index)                          FTM_CnV_REG(FTM1,index)
+#define FTM2_CnV(index)                          FTM_CnV_REG(FTM2,index)
+#define FTM3_CnV(index)                          FTM_CnV_REG(FTM3,index)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base)                      ((base)->PDOR)
+#define GPIO_PSOR_REG(base)                      ((base)->PSOR)
+#define GPIO_PCOR_REG(base)                      ((base)->PCOR)
+#define GPIO_PTOR_REG(base)                      ((base)->PTOR)
+#define GPIO_PDIR_REG(base)                      ((base)->PDIR)
+#define GPIO_PDDR_REG(base)                      ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT                      0
+#define GPIO_PDOR_PDO_WIDTH                      32
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT                     0
+#define GPIO_PSOR_PTSO_WIDTH                     32
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT                     0
+#define GPIO_PCOR_PTCO_WIDTH                     32
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT                     0
+#define GPIO_PTOR_PTTO_WIDTH                     32
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT                      0
+#define GPIO_PDIR_PDI_WIDTH                      32
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT                      0
+#define GPIO_PDDR_PDD_WIDTH                      32
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE                                 (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA                                      ((GPIO_Type *)PTA_BASE)
+#define PTA_BASE_PTR                             (PTA)
+/** Peripheral PTB base address */
+#define PTB_BASE                                 (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB                                      ((GPIO_Type *)PTB_BASE)
+#define PTB_BASE_PTR                             (PTB)
+/** Peripheral PTC base address */
+#define PTC_BASE                                 (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC                                      ((GPIO_Type *)PTC_BASE)
+#define PTC_BASE_PTR                             (PTC)
+/** Peripheral PTD base address */
+#define PTD_BASE                                 (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD                                      ((GPIO_Type *)PTD_BASE)
+#define PTD_BASE_PTR                             (PTD)
+/** Peripheral PTE base address */
+#define PTE_BASE                                 (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE                                      ((GPIO_Type *)PTE_BASE)
+#define PTE_BASE_PTR                             (PTE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { PTA, PTB, PTC, PTD, PTE }
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* PTA */
+#define GPIOA_PDOR                               GPIO_PDOR_REG(PTA)
+#define GPIOA_PSOR                               GPIO_PSOR_REG(PTA)
+#define GPIOA_PCOR                               GPIO_PCOR_REG(PTA)
+#define GPIOA_PTOR                               GPIO_PTOR_REG(PTA)
+#define GPIOA_PDIR                               GPIO_PDIR_REG(PTA)
+#define GPIOA_PDDR                               GPIO_PDDR_REG(PTA)
+/* PTB */
+#define GPIOB_PDOR                               GPIO_PDOR_REG(PTB)
+#define GPIOB_PSOR                               GPIO_PSOR_REG(PTB)
+#define GPIOB_PCOR                               GPIO_PCOR_REG(PTB)
+#define GPIOB_PTOR                               GPIO_PTOR_REG(PTB)
+#define GPIOB_PDIR                               GPIO_PDIR_REG(PTB)
+#define GPIOB_PDDR                               GPIO_PDDR_REG(PTB)
+/* PTC */
+#define GPIOC_PDOR                               GPIO_PDOR_REG(PTC)
+#define GPIOC_PSOR                               GPIO_PSOR_REG(PTC)
+#define GPIOC_PCOR                               GPIO_PCOR_REG(PTC)
+#define GPIOC_PTOR                               GPIO_PTOR_REG(PTC)
+#define GPIOC_PDIR                               GPIO_PDIR_REG(PTC)
+#define GPIOC_PDDR                               GPIO_PDDR_REG(PTC)
+/* PTD */
+#define GPIOD_PDOR                               GPIO_PDOR_REG(PTD)
+#define GPIOD_PSOR                               GPIO_PSOR_REG(PTD)
+#define GPIOD_PCOR                               GPIO_PCOR_REG(PTD)
+#define GPIOD_PTOR                               GPIO_PTOR_REG(PTD)
+#define GPIOD_PDIR                               GPIO_PDIR_REG(PTD)
+#define GPIOD_PDDR                               GPIO_PDDR_REG(PTD)
+/* PTE */
+#define GPIOE_PDOR                               GPIO_PDOR_REG(PTE)
+#define GPIOE_PSOR                               GPIO_PSOR_REG(PTE)
+#define GPIOE_PCOR                               GPIO_PCOR_REG(PTE)
+#define GPIOE_PTOR                               GPIO_PTOR_REG(PTE)
+#define GPIOE_PDIR                               GPIO_PDIR_REG(PTE)
+#define GPIOE_PDDR                               GPIO_PDDR_REG(PTE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base)                         ((base)->A1)
+#define I2C_F_REG(base)                          ((base)->F)
+#define I2C_C1_REG(base)                         ((base)->C1)
+#define I2C_S_REG(base)                          ((base)->S)
+#define I2C_D_REG(base)                          ((base)->D)
+#define I2C_C2_REG(base)                         ((base)->C2)
+#define I2C_FLT_REG(base)                        ((base)->FLT)
+#define I2C_RA_REG(base)                         ((base)->RA)
+#define I2C_SMB_REG(base)                        ((base)->SMB)
+#define I2C_A2_REG(base)                         ((base)->A2)
+#define I2C_SLTH_REG(base)                       ((base)->SLTH)
+#define I2C_SLTL_REG(base)                       ((base)->SLTL)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK                           0xFEu
+#define I2C_A1_AD_SHIFT                          1
+#define I2C_A1_AD_WIDTH                          7
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK                           0x3Fu
+#define I2C_F_ICR_SHIFT                          0
+#define I2C_F_ICR_WIDTH                          6
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          0xC0u
+#define I2C_F_MULT_SHIFT                         6
+#define I2C_F_MULT_WIDTH                         2
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK                        0x1u
+#define I2C_C1_DMAEN_SHIFT                       0
+#define I2C_C1_DMAEN_WIDTH                       1
+#define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_DMAEN_SHIFT))&I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK                         0x2u
+#define I2C_C1_WUEN_SHIFT                        1
+#define I2C_C1_WUEN_WIDTH                        1
+#define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_WUEN_SHIFT))&I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK                         0x4u
+#define I2C_C1_RSTA_SHIFT                        2
+#define I2C_C1_RSTA_WIDTH                        1
+#define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_RSTA_SHIFT))&I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK                         0x8u
+#define I2C_C1_TXAK_SHIFT                        3
+#define I2C_C1_TXAK_WIDTH                        1
+#define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_TXAK_SHIFT))&I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK                           0x10u
+#define I2C_C1_TX_SHIFT                          4
+#define I2C_C1_TX_WIDTH                          1
+#define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C1_TX_SHIFT))&I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK                          0x20u
+#define I2C_C1_MST_SHIFT                         5
+#define I2C_C1_MST_WIDTH                         1
+#define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_C1_MST_SHIFT))&I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK                        0x40u
+#define I2C_C1_IICIE_SHIFT                       6
+#define I2C_C1_IICIE_WIDTH                       1
+#define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICIE_SHIFT))&I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK                        0x80u
+#define I2C_C1_IICEN_SHIFT                       7
+#define I2C_C1_IICEN_WIDTH                       1
+#define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICEN_SHIFT))&I2C_C1_IICEN_MASK)
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK                          0x1u
+#define I2C_S_RXAK_SHIFT                         0
+#define I2C_S_RXAK_WIDTH                         1
+#define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_RXAK_SHIFT))&I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK                         0x2u
+#define I2C_S_IICIF_SHIFT                        1
+#define I2C_S_IICIF_WIDTH                        1
+#define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_S_IICIF_SHIFT))&I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK                           0x4u
+#define I2C_S_SRW_SHIFT                          2
+#define I2C_S_SRW_WIDTH                          1
+#define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_SRW_SHIFT))&I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK                           0x8u
+#define I2C_S_RAM_SHIFT                          3
+#define I2C_S_RAM_WIDTH                          1
+#define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_RAM_SHIFT))&I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK                          0x10u
+#define I2C_S_ARBL_SHIFT                         4
+#define I2C_S_ARBL_WIDTH                         1
+#define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_ARBL_SHIFT))&I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK                          0x20u
+#define I2C_S_BUSY_SHIFT                         5
+#define I2C_S_BUSY_WIDTH                         1
+#define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_BUSY_SHIFT))&I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK                          0x40u
+#define I2C_S_IAAS_SHIFT                         6
+#define I2C_S_IAAS_WIDTH                         1
+#define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_IAAS_SHIFT))&I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK                           0x80u
+#define I2C_S_TCF_SHIFT                          7
+#define I2C_S_TCF_WIDTH                          1
+#define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_TCF_SHIFT))&I2C_S_TCF_MASK)
+/* D Bit Fields */
+#define I2C_D_DATA_MASK                          0xFFu
+#define I2C_D_DATA_SHIFT                         0
+#define I2C_D_DATA_WIDTH                         8
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK                           0x7u
+#define I2C_C2_AD_SHIFT                          0
+#define I2C_C2_AD_WIDTH                          3
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         0x8u
+#define I2C_C2_RMEN_SHIFT                        3
+#define I2C_C2_RMEN_WIDTH                        1
+#define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_RMEN_SHIFT))&I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK                         0x10u
+#define I2C_C2_SBRC_SHIFT                        4
+#define I2C_C2_SBRC_WIDTH                        1
+#define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_SBRC_SHIFT))&I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK                         0x20u
+#define I2C_C2_HDRS_SHIFT                        5
+#define I2C_C2_HDRS_WIDTH                        1
+#define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_HDRS_SHIFT))&I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK                        0x40u
+#define I2C_C2_ADEXT_SHIFT                       6
+#define I2C_C2_ADEXT_WIDTH                       1
+#define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_ADEXT_SHIFT))&I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK                        0x80u
+#define I2C_C2_GCAEN_SHIFT                       7
+#define I2C_C2_GCAEN_WIDTH                       1
+#define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_GCAEN_SHIFT))&I2C_C2_GCAEN_MASK)
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK                         0xFu
+#define I2C_FLT_FLT_SHIFT                        0
+#define I2C_FLT_FLT_WIDTH                        4
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK                      0x10u
+#define I2C_FLT_STARTF_SHIFT                     4
+#define I2C_FLT_STARTF_WIDTH                     1
+#define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STARTF_SHIFT))&I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK                        0x20u
+#define I2C_FLT_SSIE_SHIFT                       5
+#define I2C_FLT_SSIE_WIDTH                       1
+#define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SSIE_SHIFT))&I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK                       0x40u
+#define I2C_FLT_STOPF_SHIFT                      6
+#define I2C_FLT_STOPF_WIDTH                      1
+#define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STOPF_SHIFT))&I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK                        0x80u
+#define I2C_FLT_SHEN_SHIFT                       7
+#define I2C_FLT_SHEN_WIDTH                       1
+#define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SHEN_SHIFT))&I2C_FLT_SHEN_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK                          0xFEu
+#define I2C_RA_RAD_SHIFT                         1
+#define I2C_RA_RAD_WIDTH                         7
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK                     0x1u
+#define I2C_SMB_SHTF2IE_SHIFT                    0
+#define I2C_SMB_SHTF2IE_WIDTH                    1
+#define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2IE_SHIFT))&I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK                       0x2u
+#define I2C_SMB_SHTF2_SHIFT                      1
+#define I2C_SMB_SHTF2_WIDTH                      1
+#define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2_SHIFT))&I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK                       0x4u
+#define I2C_SMB_SHTF1_SHIFT                      2
+#define I2C_SMB_SHTF1_WIDTH                      1
+#define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF1_SHIFT))&I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK                        0x8u
+#define I2C_SMB_SLTF_SHIFT                       3
+#define I2C_SMB_SLTF_WIDTH                       1
+#define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SLTF_SHIFT))&I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK                      0x10u
+#define I2C_SMB_TCKSEL_SHIFT                     4
+#define I2C_SMB_TCKSEL_WIDTH                     1
+#define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_SMB_TCKSEL_SHIFT))&I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK                     0x20u
+#define I2C_SMB_SIICAEN_SHIFT                    5
+#define I2C_SMB_SIICAEN_WIDTH                    1
+#define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SIICAEN_SHIFT))&I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK                     0x40u
+#define I2C_SMB_ALERTEN_SHIFT                    6
+#define I2C_SMB_ALERTEN_WIDTH                    1
+#define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_ALERTEN_SHIFT))&I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK                        0x80u
+#define I2C_SMB_FACK_SHIFT                       7
+#define I2C_SMB_FACK_WIDTH                       1
+#define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_FACK_SHIFT))&I2C_SMB_FACK_MASK)
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK                          0xFEu
+#define I2C_A2_SAD_SHIFT                         1
+#define I2C_A2_SAD_WIDTH                         7
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK                       0xFFu
+#define I2C_SLTH_SSLT_SHIFT                      0
+#define I2C_SLTH_SSLT_WIDTH                      8
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK                       0xFFu
+#define I2C_SLTL_SSLT_SHIFT                      0
+#define I2C_SLTL_SSLT_WIDTH                      8
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR                            (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR                            (I2C1)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x400E6000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+#define I2C2_BASE_PTR                            (I2C2)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1                                  I2C_A1_REG(I2C0)
+#define I2C0_F                                   I2C_F_REG(I2C0)
+#define I2C0_C1                                  I2C_C1_REG(I2C0)
+#define I2C0_S                                   I2C_S_REG(I2C0)
+#define I2C0_D                                   I2C_D_REG(I2C0)
+#define I2C0_C2                                  I2C_C2_REG(I2C0)
+#define I2C0_FLT                                 I2C_FLT_REG(I2C0)
+#define I2C0_RA                                  I2C_RA_REG(I2C0)
+#define I2C0_SMB                                 I2C_SMB_REG(I2C0)
+#define I2C0_A2                                  I2C_A2_REG(I2C0)
+#define I2C0_SLTH                                I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL                                I2C_SLTL_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1                                  I2C_A1_REG(I2C1)
+#define I2C1_F                                   I2C_F_REG(I2C1)
+#define I2C1_C1                                  I2C_C1_REG(I2C1)
+#define I2C1_S                                   I2C_S_REG(I2C1)
+#define I2C1_D                                   I2C_D_REG(I2C1)
+#define I2C1_C2                                  I2C_C2_REG(I2C1)
+#define I2C1_FLT                                 I2C_FLT_REG(I2C1)
+#define I2C1_RA                                  I2C_RA_REG(I2C1)
+#define I2C1_SMB                                 I2C_SMB_REG(I2C1)
+#define I2C1_A2                                  I2C_A2_REG(I2C1)
+#define I2C1_SLTH                                I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL                                I2C_SLTL_REG(I2C1)
+/* I2C2 */
+#define I2C2_A1                                  I2C_A1_REG(I2C2)
+#define I2C2_F                                   I2C_F_REG(I2C2)
+#define I2C2_C1                                  I2C_C1_REG(I2C2)
+#define I2C2_S                                   I2C_S_REG(I2C2)
+#define I2C2_D                                   I2C_D_REG(I2C2)
+#define I2C2_C2                                  I2C_C2_REG(I2C2)
+#define I2C2_FLT                                 I2C_FLT_REG(I2C2)
+#define I2C2_RA                                  I2C_RA_REG(I2C2)
+#define I2C2_SMB                                 I2C_SMB_REG(I2C2)
+#define I2C2_A2                                  I2C_A2_REG(I2C2)
+#define I2C2_SLTH                                I2C_SLTH_REG(I2C2)
+#define I2C2_SLTL                                I2C_SLTL_REG(I2C2)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
+  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t TDR[2];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __I  uint32_t TFR[2];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_3[28];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
+  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t RDR[2];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[24];
+  __I  uint32_t RFR[2];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_6[24];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
+  __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base)                       ((base)->TCSR)
+#define I2S_TCR1_REG(base)                       ((base)->TCR1)
+#define I2S_TCR2_REG(base)                       ((base)->TCR2)
+#define I2S_TCR3_REG(base)                       ((base)->TCR3)
+#define I2S_TCR4_REG(base)                       ((base)->TCR4)
+#define I2S_TCR5_REG(base)                       ((base)->TCR5)
+#define I2S_TDR_REG(base,index)                  ((base)->TDR[index])
+#define I2S_TDR_COUNT                            2
+#define I2S_TFR_REG(base,index)                  ((base)->TFR[index])
+#define I2S_TFR_COUNT                            2
+#define I2S_TMR_REG(base)                        ((base)->TMR)
+#define I2S_RCSR_REG(base)                       ((base)->RCSR)
+#define I2S_RCR1_REG(base)                       ((base)->RCR1)
+#define I2S_RCR2_REG(base)                       ((base)->RCR2)
+#define I2S_RCR3_REG(base)                       ((base)->RCR3)
+#define I2S_RCR4_REG(base)                       ((base)->RCR4)
+#define I2S_RCR5_REG(base)                       ((base)->RCR5)
+#define I2S_RDR_REG(base,index)                  ((base)->RDR[index])
+#define I2S_RDR_COUNT                            2
+#define I2S_RFR_REG(base,index)                  ((base)->RFR[index])
+#define I2S_RFR_COUNT                            2
+#define I2S_RMR_REG(base)                        ((base)->RMR)
+#define I2S_MCR_REG(base)                        ((base)->MCR)
+#define I2S_MDR_REG(base)                        ((base)->MDR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK                       0x1u
+#define I2S_TCSR_FRDE_SHIFT                      0
+#define I2S_TCSR_FRDE_WIDTH                      1
+#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRDE_SHIFT))&I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK                       0x2u
+#define I2S_TCSR_FWDE_SHIFT                      1
+#define I2S_TCSR_FWDE_WIDTH                      1
+#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK                       0x100u
+#define I2S_TCSR_FRIE_SHIFT                      8
+#define I2S_TCSR_FRIE_WIDTH                      1
+#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRIE_SHIFT))&I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK                       0x200u
+#define I2S_TCSR_FWIE_SHIFT                      9
+#define I2S_TCSR_FWIE_WIDTH                      1
+#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK                       0x400u
+#define I2S_TCSR_FEIE_SHIFT                      10
+#define I2S_TCSR_FEIE_WIDTH                      1
+#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK                       0x800u
+#define I2S_TCSR_SEIE_SHIFT                      11
+#define I2S_TCSR_SEIE_WIDTH                      1
+#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK                       0x1000u
+#define I2S_TCSR_WSIE_SHIFT                      12
+#define I2S_TCSR_WSIE_WIDTH                      1
+#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK                        0x10000u
+#define I2S_TCSR_FRF_SHIFT                       16
+#define I2S_TCSR_FRF_WIDTH                       1
+#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRF_SHIFT))&I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK                        0x20000u
+#define I2S_TCSR_FWF_SHIFT                       17
+#define I2S_TCSR_FWF_WIDTH                       1
+#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK                        0x40000u
+#define I2S_TCSR_FEF_SHIFT                       18
+#define I2S_TCSR_FEF_WIDTH                       1
+#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK                        0x80000u
+#define I2S_TCSR_SEF_SHIFT                       19
+#define I2S_TCSR_SEF_WIDTH                       1
+#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK                        0x100000u
+#define I2S_TCSR_WSF_SHIFT                       20
+#define I2S_TCSR_WSF_WIDTH                       1
+#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK                         0x1000000u
+#define I2S_TCSR_SR_SHIFT                        24
+#define I2S_TCSR_SR_WIDTH                        1
+#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK                         0x2000000u
+#define I2S_TCSR_FR_SHIFT                        25
+#define I2S_TCSR_FR_WIDTH                        1
+#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK                        0x10000000u
+#define I2S_TCSR_BCE_SHIFT                       28
+#define I2S_TCSR_BCE_WIDTH                       1
+#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK                       0x20000000u
+#define I2S_TCSR_DBGE_SHIFT                      29
+#define I2S_TCSR_DBGE_WIDTH                      1
+#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK                      0x40000000u
+#define I2S_TCSR_STOPE_SHIFT                     30
+#define I2S_TCSR_STOPE_WIDTH                     1
+#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK                         0x80000000u
+#define I2S_TCSR_TE_SHIFT                        31
+#define I2S_TCSR_TE_WIDTH                        1
+#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK                        0x7u
+#define I2S_TCR1_TFW_SHIFT                       0
+#define I2S_TCR1_TFW_WIDTH                       3
+#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK                        0xFFu
+#define I2S_TCR2_DIV_SHIFT                       0
+#define I2S_TCR2_DIV_WIDTH                       8
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        0x1000000u
+#define I2S_TCR2_BCD_SHIFT                       24
+#define I2S_TCR2_BCD_WIDTH                       1
+#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK                        0x2000000u
+#define I2S_TCR2_BCP_SHIFT                       25
+#define I2S_TCR2_BCP_WIDTH                       1
+#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK                       0xC000000u
+#define I2S_TCR2_MSEL_SHIFT                      26
+#define I2S_TCR2_MSEL_WIDTH                      2
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK                        0x10000000u
+#define I2S_TCR2_BCI_SHIFT                       28
+#define I2S_TCR2_BCI_WIDTH                       1
+#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK                        0x20000000u
+#define I2S_TCR2_BCS_SHIFT                       29
+#define I2S_TCR2_BCS_WIDTH                       1
+#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK                       0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT                      30
+#define I2S_TCR2_SYNC_WIDTH                      2
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK                       0x1Fu
+#define I2S_TCR3_WDFL_SHIFT                      0
+#define I2S_TCR3_WDFL_WIDTH                      5
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        0x30000u
+#define I2S_TCR3_TCE_SHIFT                       16
+#define I2S_TCR3_TCE_WIDTH                       2
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK                        0x1u
+#define I2S_TCR4_FSD_SHIFT                       0
+#define I2S_TCR4_FSD_WIDTH                       1
+#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK                        0x2u
+#define I2S_TCR4_FSP_SHIFT                       1
+#define I2S_TCR4_FSP_WIDTH                       1
+#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSE_MASK                        0x8u
+#define I2S_TCR4_FSE_SHIFT                       3
+#define I2S_TCR4_FSE_WIDTH                       1
+#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK                         0x10u
+#define I2S_TCR4_MF_SHIFT                        4
+#define I2S_TCR4_MF_WIDTH                        1
+#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK                       0x1F00u
+#define I2S_TCR4_SYWD_SHIFT                      8
+#define I2S_TCR4_SYWD_WIDTH                      5
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT                      16
+#define I2S_TCR4_FRSZ_WIDTH                      5
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK                        0x1F00u
+#define I2S_TCR5_FBT_SHIFT                       8
+#define I2S_TCR5_FBT_WIDTH                       5
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        0x1F0000u
+#define I2S_TCR5_W0W_SHIFT                       16
+#define I2S_TCR5_W0W_WIDTH                       5
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        0x1F000000u
+#define I2S_TCR5_WNW_SHIFT                       24
+#define I2S_TCR5_WNW_WIDTH                       5
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT                        0
+#define I2S_TDR_TDR_WIDTH                        32
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK                         0xFu
+#define I2S_TFR_RFP_SHIFT                        0
+#define I2S_TFR_RFP_WIDTH                        4
+#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK                         0xF0000u
+#define I2S_TFR_WFP_SHIFT                        16
+#define I2S_TFR_WFP_WIDTH                        4
+#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK                         0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT                        0
+#define I2S_TMR_TWM_WIDTH                        32
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK                       0x1u
+#define I2S_RCSR_FRDE_SHIFT                      0
+#define I2S_RCSR_FRDE_WIDTH                      1
+#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRDE_SHIFT))&I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK                       0x2u
+#define I2S_RCSR_FWDE_SHIFT                      1
+#define I2S_RCSR_FWDE_WIDTH                      1
+#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK                       0x100u
+#define I2S_RCSR_FRIE_SHIFT                      8
+#define I2S_RCSR_FRIE_WIDTH                      1
+#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRIE_SHIFT))&I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK                       0x200u
+#define I2S_RCSR_FWIE_SHIFT                      9
+#define I2S_RCSR_FWIE_WIDTH                      1
+#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK                       0x400u
+#define I2S_RCSR_FEIE_SHIFT                      10
+#define I2S_RCSR_FEIE_WIDTH                      1
+#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK                       0x800u
+#define I2S_RCSR_SEIE_SHIFT                      11
+#define I2S_RCSR_SEIE_WIDTH                      1
+#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK                       0x1000u
+#define I2S_RCSR_WSIE_SHIFT                      12
+#define I2S_RCSR_WSIE_WIDTH                      1
+#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK                        0x10000u
+#define I2S_RCSR_FRF_SHIFT                       16
+#define I2S_RCSR_FRF_WIDTH                       1
+#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRF_SHIFT))&I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK                        0x20000u
+#define I2S_RCSR_FWF_SHIFT                       17
+#define I2S_RCSR_FWF_WIDTH                       1
+#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK                        0x40000u
+#define I2S_RCSR_FEF_SHIFT                       18
+#define I2S_RCSR_FEF_WIDTH                       1
+#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK                        0x80000u
+#define I2S_RCSR_SEF_SHIFT                       19
+#define I2S_RCSR_SEF_WIDTH                       1
+#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK                        0x100000u
+#define I2S_RCSR_WSF_SHIFT                       20
+#define I2S_RCSR_WSF_WIDTH                       1
+#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK                         0x1000000u
+#define I2S_RCSR_SR_SHIFT                        24
+#define I2S_RCSR_SR_WIDTH                        1
+#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK                         0x2000000u
+#define I2S_RCSR_FR_SHIFT                        25
+#define I2S_RCSR_FR_WIDTH                        1
+#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK                        0x10000000u
+#define I2S_RCSR_BCE_SHIFT                       28
+#define I2S_RCSR_BCE_WIDTH                       1
+#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK                       0x20000000u
+#define I2S_RCSR_DBGE_SHIFT                      29
+#define I2S_RCSR_DBGE_WIDTH                      1
+#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK                      0x40000000u
+#define I2S_RCSR_STOPE_SHIFT                     30
+#define I2S_RCSR_STOPE_WIDTH                     1
+#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK                         0x80000000u
+#define I2S_RCSR_RE_SHIFT                        31
+#define I2S_RCSR_RE_WIDTH                        1
+#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK                        0x7u
+#define I2S_RCR1_RFW_SHIFT                       0
+#define I2S_RCR1_RFW_WIDTH                       3
+#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK                        0xFFu
+#define I2S_RCR2_DIV_SHIFT                       0
+#define I2S_RCR2_DIV_WIDTH                       8
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        0x1000000u
+#define I2S_RCR2_BCD_SHIFT                       24
+#define I2S_RCR2_BCD_WIDTH                       1
+#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK                        0x2000000u
+#define I2S_RCR2_BCP_SHIFT                       25
+#define I2S_RCR2_BCP_WIDTH                       1
+#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK                       0xC000000u
+#define I2S_RCR2_MSEL_SHIFT                      26
+#define I2S_RCR2_MSEL_WIDTH                      2
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK                        0x10000000u
+#define I2S_RCR2_BCI_SHIFT                       28
+#define I2S_RCR2_BCI_WIDTH                       1
+#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK                        0x20000000u
+#define I2S_RCR2_BCS_SHIFT                       29
+#define I2S_RCR2_BCS_WIDTH                       1
+#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK                       0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT                      30
+#define I2S_RCR2_SYNC_WIDTH                      2
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK                       0x1Fu
+#define I2S_RCR3_WDFL_SHIFT                      0
+#define I2S_RCR3_WDFL_WIDTH                      5
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        0x30000u
+#define I2S_RCR3_RCE_SHIFT                       16
+#define I2S_RCR3_RCE_WIDTH                       2
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK                        0x1u
+#define I2S_RCR4_FSD_SHIFT                       0
+#define I2S_RCR4_FSD_WIDTH                       1
+#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK                        0x2u
+#define I2S_RCR4_FSP_SHIFT                       1
+#define I2S_RCR4_FSP_WIDTH                       1
+#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSE_MASK                        0x8u
+#define I2S_RCR4_FSE_SHIFT                       3
+#define I2S_RCR4_FSE_WIDTH                       1
+#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK                         0x10u
+#define I2S_RCR4_MF_SHIFT                        4
+#define I2S_RCR4_MF_WIDTH                        1
+#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK                       0x1F00u
+#define I2S_RCR4_SYWD_SHIFT                      8
+#define I2S_RCR4_SYWD_WIDTH                      5
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT                      16
+#define I2S_RCR4_FRSZ_WIDTH                      5
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK                        0x1F00u
+#define I2S_RCR5_FBT_SHIFT                       8
+#define I2S_RCR5_FBT_WIDTH                       5
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        0x1F0000u
+#define I2S_RCR5_W0W_SHIFT                       16
+#define I2S_RCR5_W0W_WIDTH                       5
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        0x1F000000u
+#define I2S_RCR5_WNW_SHIFT                       24
+#define I2S_RCR5_WNW_WIDTH                       5
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT                        0
+#define I2S_RDR_RDR_WIDTH                        32
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK                         0xFu
+#define I2S_RFR_RFP_SHIFT                        0
+#define I2S_RFR_RFP_WIDTH                        4
+#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK                         0xF0000u
+#define I2S_RFR_WFP_SHIFT                        16
+#define I2S_RFR_WFP_WIDTH                        4
+#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK                         0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT                        0
+#define I2S_RMR_RWM_WIDTH                        32
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK                        0x3000000u
+#define I2S_MCR_MICS_SHIFT                       24
+#define I2S_MCR_MICS_WIDTH                       2
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK                         0x40000000u
+#define I2S_MCR_MOE_SHIFT                        30
+#define I2S_MCR_MOE_WIDTH                        1
+#define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MOE_SHIFT))&I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK                         0x80000000u
+#define I2S_MCR_DUF_SHIFT                        31
+#define I2S_MCR_DUF_WIDTH                        1
+#define I2S_MCR_DUF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_DUF_SHIFT))&I2S_MCR_DUF_MASK)
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK                      0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT                     0
+#define I2S_MDR_DIVIDE_WIDTH                     12
+#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK                       0xFF000u
+#define I2S_MDR_FRACT_SHIFT                      12
+#define I2S_MDR_FRACT_WIDTH                      8
+#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR                            (I2S0)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS                              { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS                              { I2S0_Tx_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR                                I2S_TCSR_REG(I2S0)
+#define I2S0_TCR1                                I2S_TCR1_REG(I2S0)
+#define I2S0_TCR2                                I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3                                I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4                                I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5                                I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0                                I2S_TDR_REG(I2S0,0)
+#define I2S0_TDR1                                I2S_TDR_REG(I2S0,1)
+#define I2S0_TFR0                                I2S_TFR_REG(I2S0,0)
+#define I2S0_TFR1                                I2S_TFR_REG(I2S0,1)
+#define I2S0_TMR                                 I2S_TMR_REG(I2S0)
+#define I2S0_RCSR                                I2S_RCSR_REG(I2S0)
+#define I2S0_RCR1                                I2S_RCR1_REG(I2S0)
+#define I2S0_RCR2                                I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3                                I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4                                I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5                                I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0                                I2S_RDR_REG(I2S0,0)
+#define I2S0_RDR1                                I2S_RDR_REG(I2S0,1)
+#define I2S0_RFR0                                I2S_RFR_REG(I2S0,0)
+#define I2S0_RFR1                                I2S_RFR_REG(I2S0,1)
+#define I2S0_RMR                                 I2S_RMR_REG(I2S0)
+#define I2S0_MCR                                 I2S_MCR_REG(I2S0)
+#define I2S0_MDR                                 I2S_MDR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index)                          I2S_TDR_REG(I2S0,index)
+#define I2S0_TFR(index)                          I2S_TFR_REG(I2S0,index)
+#define I2S0_RDR(index)                          I2S_RDR_REG(I2S0,index)
+#define I2S0_RFR(index)                          I2S_RFR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
+  __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
+  __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
+  __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
+  __IO uint8_t RST;                                /**< LLWU Reset Enable register, offset: 0xA */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base)                       ((base)->PE1)
+#define LLWU_PE2_REG(base)                       ((base)->PE2)
+#define LLWU_PE3_REG(base)                       ((base)->PE3)
+#define LLWU_PE4_REG(base)                       ((base)->PE4)
+#define LLWU_ME_REG(base)                        ((base)->ME)
+#define LLWU_F1_REG(base)                        ((base)->F1)
+#define LLWU_F2_REG(base)                        ((base)->F2)
+#define LLWU_F3_REG(base)                        ((base)->F3)
+#define LLWU_FILT1_REG(base)                     ((base)->FILT1)
+#define LLWU_FILT2_REG(base)                     ((base)->FILT2)
+#define LLWU_RST_REG(base)                       ((base)->RST)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK                      0x3u
+#define LLWU_PE1_WUPE0_SHIFT                     0
+#define LLWU_PE1_WUPE0_WIDTH                     2
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      0xCu
+#define LLWU_PE1_WUPE1_SHIFT                     2
+#define LLWU_PE1_WUPE1_WIDTH                     2
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      0x30u
+#define LLWU_PE1_WUPE2_SHIFT                     4
+#define LLWU_PE1_WUPE2_WIDTH                     2
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      0xC0u
+#define LLWU_PE1_WUPE3_SHIFT                     6
+#define LLWU_PE1_WUPE3_WIDTH                     2
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK                      0x3u
+#define LLWU_PE2_WUPE4_SHIFT                     0
+#define LLWU_PE2_WUPE4_WIDTH                     2
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      0xCu
+#define LLWU_PE2_WUPE5_SHIFT                     2
+#define LLWU_PE2_WUPE5_WIDTH                     2
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      0x30u
+#define LLWU_PE2_WUPE6_SHIFT                     4
+#define LLWU_PE2_WUPE6_WIDTH                     2
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      0xC0u
+#define LLWU_PE2_WUPE7_SHIFT                     6
+#define LLWU_PE2_WUPE7_WIDTH                     2
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK                      0x3u
+#define LLWU_PE3_WUPE8_SHIFT                     0
+#define LLWU_PE3_WUPE8_WIDTH                     2
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      0xCu
+#define LLWU_PE3_WUPE9_SHIFT                     2
+#define LLWU_PE3_WUPE9_WIDTH                     2
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     0x30u
+#define LLWU_PE3_WUPE10_SHIFT                    4
+#define LLWU_PE3_WUPE10_WIDTH                    2
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     0xC0u
+#define LLWU_PE3_WUPE11_SHIFT                    6
+#define LLWU_PE3_WUPE11_WIDTH                    2
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK                     0x3u
+#define LLWU_PE4_WUPE12_SHIFT                    0
+#define LLWU_PE4_WUPE12_WIDTH                    2
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     0xCu
+#define LLWU_PE4_WUPE13_SHIFT                    2
+#define LLWU_PE4_WUPE13_WIDTH                    2
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     0x30u
+#define LLWU_PE4_WUPE14_SHIFT                    4
+#define LLWU_PE4_WUPE14_WIDTH                    2
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     0xC0u
+#define LLWU_PE4_WUPE15_SHIFT                    6
+#define LLWU_PE4_WUPE15_WIDTH                    2
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK                       0x1u
+#define LLWU_ME_WUME0_SHIFT                      0
+#define LLWU_ME_WUME0_WIDTH                      1
+#define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK                       0x2u
+#define LLWU_ME_WUME1_SHIFT                      1
+#define LLWU_ME_WUME1_WIDTH                      1
+#define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK                       0x4u
+#define LLWU_ME_WUME2_SHIFT                      2
+#define LLWU_ME_WUME2_WIDTH                      1
+#define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK                       0x8u
+#define LLWU_ME_WUME3_SHIFT                      3
+#define LLWU_ME_WUME3_WIDTH                      1
+#define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK                       0x10u
+#define LLWU_ME_WUME4_SHIFT                      4
+#define LLWU_ME_WUME4_WIDTH                      1
+#define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK                       0x20u
+#define LLWU_ME_WUME5_SHIFT                      5
+#define LLWU_ME_WUME5_WIDTH                      1
+#define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK                       0x40u
+#define LLWU_ME_WUME6_SHIFT                      6
+#define LLWU_ME_WUME6_WIDTH                      1
+#define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK                       0x80u
+#define LLWU_ME_WUME7_SHIFT                      7
+#define LLWU_ME_WUME7_WIDTH                      1
+#define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK                        0x1u
+#define LLWU_F1_WUF0_SHIFT                       0
+#define LLWU_F1_WUF0_WIDTH                       1
+#define LLWU_F1_WUF0(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF0_SHIFT))&LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK                        0x2u
+#define LLWU_F1_WUF1_SHIFT                       1
+#define LLWU_F1_WUF1_WIDTH                       1
+#define LLWU_F1_WUF1(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF1_SHIFT))&LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK                        0x4u
+#define LLWU_F1_WUF2_SHIFT                       2
+#define LLWU_F1_WUF2_WIDTH                       1
+#define LLWU_F1_WUF2(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF2_SHIFT))&LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK                        0x8u
+#define LLWU_F1_WUF3_SHIFT                       3
+#define LLWU_F1_WUF3_WIDTH                       1
+#define LLWU_F1_WUF3(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF3_SHIFT))&LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK                        0x10u
+#define LLWU_F1_WUF4_SHIFT                       4
+#define LLWU_F1_WUF4_WIDTH                       1
+#define LLWU_F1_WUF4(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF4_SHIFT))&LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK                        0x20u
+#define LLWU_F1_WUF5_SHIFT                       5
+#define LLWU_F1_WUF5_WIDTH                       1
+#define LLWU_F1_WUF5(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF5_SHIFT))&LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK                        0x40u
+#define LLWU_F1_WUF6_SHIFT                       6
+#define LLWU_F1_WUF6_WIDTH                       1
+#define LLWU_F1_WUF6(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF6_SHIFT))&LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK                        0x80u
+#define LLWU_F1_WUF7_SHIFT                       7
+#define LLWU_F1_WUF7_WIDTH                       1
+#define LLWU_F1_WUF7(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF7_SHIFT))&LLWU_F1_WUF7_MASK)
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK                        0x1u
+#define LLWU_F2_WUF8_SHIFT                       0
+#define LLWU_F2_WUF8_WIDTH                       1
+#define LLWU_F2_WUF8(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF8_SHIFT))&LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK                        0x2u
+#define LLWU_F2_WUF9_SHIFT                       1
+#define LLWU_F2_WUF9_WIDTH                       1
+#define LLWU_F2_WUF9(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF9_SHIFT))&LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK                       0x4u
+#define LLWU_F2_WUF10_SHIFT                      2
+#define LLWU_F2_WUF10_WIDTH                      1
+#define LLWU_F2_WUF10(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF10_SHIFT))&LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK                       0x8u
+#define LLWU_F2_WUF11_SHIFT                      3
+#define LLWU_F2_WUF11_WIDTH                      1
+#define LLWU_F2_WUF11(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF11_SHIFT))&LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK                       0x10u
+#define LLWU_F2_WUF12_SHIFT                      4
+#define LLWU_F2_WUF12_WIDTH                      1
+#define LLWU_F2_WUF12(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF12_SHIFT))&LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK                       0x20u
+#define LLWU_F2_WUF13_SHIFT                      5
+#define LLWU_F2_WUF13_WIDTH                      1
+#define LLWU_F2_WUF13(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF13_SHIFT))&LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK                       0x40u
+#define LLWU_F2_WUF14_SHIFT                      6
+#define LLWU_F2_WUF14_WIDTH                      1
+#define LLWU_F2_WUF14(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF14_SHIFT))&LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK                       0x80u
+#define LLWU_F2_WUF15_SHIFT                      7
+#define LLWU_F2_WUF15_WIDTH                      1
+#define LLWU_F2_WUF15(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF15_SHIFT))&LLWU_F2_WUF15_MASK)
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK                       0x1u
+#define LLWU_F3_MWUF0_SHIFT                      0
+#define LLWU_F3_MWUF0_WIDTH                      1
+#define LLWU_F3_MWUF0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF0_SHIFT))&LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK                       0x2u
+#define LLWU_F3_MWUF1_SHIFT                      1
+#define LLWU_F3_MWUF1_WIDTH                      1
+#define LLWU_F3_MWUF1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF1_SHIFT))&LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK                       0x4u
+#define LLWU_F3_MWUF2_SHIFT                      2
+#define LLWU_F3_MWUF2_WIDTH                      1
+#define LLWU_F3_MWUF2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF2_SHIFT))&LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK                       0x8u
+#define LLWU_F3_MWUF3_SHIFT                      3
+#define LLWU_F3_MWUF3_WIDTH                      1
+#define LLWU_F3_MWUF3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF3_SHIFT))&LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK                       0x10u
+#define LLWU_F3_MWUF4_SHIFT                      4
+#define LLWU_F3_MWUF4_WIDTH                      1
+#define LLWU_F3_MWUF4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF4_SHIFT))&LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK                       0x20u
+#define LLWU_F3_MWUF5_SHIFT                      5
+#define LLWU_F3_MWUF5_WIDTH                      1
+#define LLWU_F3_MWUF5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF5_SHIFT))&LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK                       0x40u
+#define LLWU_F3_MWUF6_SHIFT                      6
+#define LLWU_F3_MWUF6_WIDTH                      1
+#define LLWU_F3_MWUF6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF6_SHIFT))&LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK                       0x80u
+#define LLWU_F3_MWUF7_SHIFT                      7
+#define LLWU_F3_MWUF7_WIDTH                      1
+#define LLWU_F3_MWUF7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF7_SHIFT))&LLWU_F3_MWUF7_MASK)
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK                  0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT                 0
+#define LLWU_FILT1_FILTSEL_WIDTH                 4
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    0x60u
+#define LLWU_FILT1_FILTE_SHIFT                   5
+#define LLWU_FILT1_FILTE_WIDTH                   2
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK                    0x80u
+#define LLWU_FILT1_FILTF_SHIFT                   7
+#define LLWU_FILT1_FILTF_WIDTH                   1
+#define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK                  0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT                 0
+#define LLWU_FILT2_FILTSEL_WIDTH                 4
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    0x60u
+#define LLWU_FILT2_FILTE_SHIFT                   5
+#define LLWU_FILT2_FILTE_WIDTH                   2
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK                    0x80u
+#define LLWU_FILT2_FILTF_SHIFT                   7
+#define LLWU_FILT2_FILTF_WIDTH                   1
+#define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK                    0x1u
+#define LLWU_RST_RSTFILT_SHIFT                   0
+#define LLWU_RST_RSTFILT_WIDTH                   1
+#define LLWU_RST_RSTFILT(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_RST_RSTFILT_SHIFT))&LLWU_RST_RSTFILT_MASK)
+#define LLWU_RST_LLRSTE_MASK                     0x2u
+#define LLWU_RST_LLRSTE_SHIFT                    1
+#define LLWU_RST_LLRSTE_WIDTH                    1
+#define LLWU_RST_LLRSTE(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_RST_LLRSTE_SHIFT))&LLWU_RST_LLRSTE_MASK)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR                            (LLWU)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1                                 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2                                 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3                                 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4                                 LLWU_PE4_REG(LLWU)
+#define LLWU_ME                                  LLWU_ME_REG(LLWU)
+#define LLWU_F1                                  LLWU_F1_REG(LLWU)
+#define LLWU_F2                                  LLWU_F2_REG(LLWU)
+#define LLWU_F3                                  LLWU_F3_REG(LLWU)
+#define LLWU_FILT1                               LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2                               LLWU_FILT2_REG(LLWU)
+#define LLWU_RST                                 LLWU_RST_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base)                      ((base)->CSR)
+#define LPTMR_PSR_REG(base)                      ((base)->PSR)
+#define LPTMR_CMR_REG(base)                      ((base)->CMR)
+#define LPTMR_CNR_REG(base)                      ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK                       0x1u
+#define LPTMR_CSR_TEN_SHIFT                      0
+#define LPTMR_CSR_TEN_WIDTH                      1
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK                       0x2u
+#define LPTMR_CSR_TMS_SHIFT                      1
+#define LPTMR_CSR_TMS_WIDTH                      1
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK                       0x4u
+#define LPTMR_CSR_TFC_SHIFT                      2
+#define LPTMR_CSR_TFC_WIDTH                      1
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK                       0x8u
+#define LPTMR_CSR_TPP_SHIFT                      3
+#define LPTMR_CSR_TPP_WIDTH                      1
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK                       0x30u
+#define LPTMR_CSR_TPS_SHIFT                      4
+#define LPTMR_CSR_TPS_WIDTH                      2
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       0x40u
+#define LPTMR_CSR_TIE_SHIFT                      6
+#define LPTMR_CSR_TIE_WIDTH                      1
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK                       0x80u
+#define LPTMR_CSR_TCF_SHIFT                      7
+#define LPTMR_CSR_TCF_WIDTH                      1
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK                       0x3u
+#define LPTMR_PSR_PCS_SHIFT                      0
+#define LPTMR_PSR_PCS_WIDTH                      2
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      0x4u
+#define LPTMR_PSR_PBYP_SHIFT                     2
+#define LPTMR_PSR_PBYP_WIDTH                     1
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK                  0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT                 3
+#define LPTMR_PSR_PRESCALE_WIDTH                 4
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT                  0
+#define LPTMR_CMR_COMPARE_WIDTH                  16
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT                  0
+#define LPTMR_CNR_COUNTER_WIDTH                  16
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR                          (LPTMR0)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR                               LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR                               LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR                               LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR                               LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
+  __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
+  __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
+  __IO uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+  __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+  __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
+  __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base)                         ((base)->C1)
+#define MCG_C2_REG(base)                         ((base)->C2)
+#define MCG_C3_REG(base)                         ((base)->C3)
+#define MCG_C4_REG(base)                         ((base)->C4)
+#define MCG_C5_REG(base)                         ((base)->C5)
+#define MCG_C6_REG(base)                         ((base)->C6)
+#define MCG_S_REG(base)                          ((base)->S)
+#define MCG_SC_REG(base)                         ((base)->SC)
+#define MCG_ATCVH_REG(base)                      ((base)->ATCVH)
+#define MCG_ATCVL_REG(base)                      ((base)->ATCVL)
+#define MCG_C7_REG(base)                         ((base)->C7)
+#define MCG_C8_REG(base)                         ((base)->C8)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK                     0x1u
+#define MCG_C1_IREFSTEN_SHIFT                    0
+#define MCG_C1_IREFSTEN_WIDTH                    1
+#define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK                      0x2u
+#define MCG_C1_IRCLKEN_SHIFT                     1
+#define MCG_C1_IRCLKEN_WIDTH                     1
+#define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK                        0x4u
+#define MCG_C1_IREFS_SHIFT                       2
+#define MCG_C1_IREFS_WIDTH                       1
+#define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFS_SHIFT))&MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK                        0x38u
+#define MCG_C1_FRDIV_SHIFT                       3
+#define MCG_C1_FRDIV_WIDTH                       3
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         0xC0u
+#define MCG_C1_CLKS_SHIFT                        6
+#define MCG_C1_CLKS_WIDTH                        2
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK                         0x1u
+#define MCG_C2_IRCS_SHIFT                        0
+#define MCG_C2_IRCS_WIDTH                        1
+#define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK                           0x2u
+#define MCG_C2_LP_SHIFT                          1
+#define MCG_C2_LP_WIDTH                          1
+#define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x))<<MCG_C2_LP_SHIFT))&MCG_C2_LP_MASK)
+#define MCG_C2_EREFS_MASK                        0x4u
+#define MCG_C2_EREFS_SHIFT                       2
+#define MCG_C2_EREFS_WIDTH                       1
+#define MCG_C2_EREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS_SHIFT))&MCG_C2_EREFS_MASK)
+#define MCG_C2_HGO_MASK                          0x8u
+#define MCG_C2_HGO_SHIFT                         3
+#define MCG_C2_HGO_WIDTH                         1
+#define MCG_C2_HGO(x)                            (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO_SHIFT))&MCG_C2_HGO_MASK)
+#define MCG_C2_RANGE_MASK                        0x30u
+#define MCG_C2_RANGE_SHIFT                       4
+#define MCG_C2_RANGE_WIDTH                       2
+#define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK                      0x40u
+#define MCG_C2_FCFTRIM_SHIFT                     6
+#define MCG_C2_FCFTRIM_WIDTH                     1
+#define MCG_C2_FCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C2_FCFTRIM_SHIFT))&MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK                       0x80u
+#define MCG_C2_LOCRE0_SHIFT                      7
+#define MCG_C2_LOCRE0_WIDTH                      1
+#define MCG_C2_LOCRE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_LOCRE0_SHIFT))&MCG_C2_LOCRE0_MASK)
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK                       0xFFu
+#define MCG_C3_SCTRIM_SHIFT                      0
+#define MCG_C3_SCTRIM_WIDTH                      8
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK                      0x1u
+#define MCG_C4_SCFTRIM_SHIFT                     0
+#define MCG_C4_SCFTRIM_WIDTH                     1
+#define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C4_SCFTRIM_SHIFT))&MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK                       0x1Eu
+#define MCG_C4_FCTRIM_SHIFT                      1
+#define MCG_C4_FCTRIM_WIDTH                      4
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     0x60u
+#define MCG_C4_DRST_DRS_SHIFT                    5
+#define MCG_C4_DRST_DRS_WIDTH                    2
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK                        0x80u
+#define MCG_C4_DMX32_SHIFT                       7
+#define MCG_C4_DMX32_WIDTH                       1
+#define MCG_C4_DMX32(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C4_DMX32_SHIFT))&MCG_C4_DMX32_MASK)
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK                       0x1Fu
+#define MCG_C5_PRDIV0_SHIFT                      0
+#define MCG_C5_PRDIV0_WIDTH                      5
+#define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK                     0x20u
+#define MCG_C5_PLLSTEN0_SHIFT                    5
+#define MCG_C5_PLLSTEN0_WIDTH                    1
+#define MCG_C5_PLLSTEN0(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLSTEN0_SHIFT))&MCG_C5_PLLSTEN0_MASK)
+#define MCG_C5_PLLCLKEN0_MASK                    0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT                   6
+#define MCG_C5_PLLCLKEN0_WIDTH                   1
+#define MCG_C5_PLLCLKEN0(x)                      (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLCLKEN0_SHIFT))&MCG_C5_PLLCLKEN0_MASK)
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK                        0x1Fu
+#define MCG_C6_VDIV0_SHIFT                       0
+#define MCG_C6_VDIV0_WIDTH                       5
+#define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK                         0x20u
+#define MCG_C6_CME0_SHIFT                        5
+#define MCG_C6_CME0_WIDTH                        1
+#define MCG_C6_CME0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_CME0_SHIFT))&MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK                         0x40u
+#define MCG_C6_PLLS_SHIFT                        6
+#define MCG_C6_PLLS_WIDTH                        1
+#define MCG_C6_PLLS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_PLLS_SHIFT))&MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK                       0x80u
+#define MCG_C6_LOLIE0_SHIFT                      7
+#define MCG_C6_LOLIE0_WIDTH                      1
+#define MCG_C6_LOLIE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C6_LOLIE0_SHIFT))&MCG_C6_LOLIE0_MASK)
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK                         0x1u
+#define MCG_S_IRCST_SHIFT                        0
+#define MCG_S_IRCST_WIDTH                        1
+#define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_IRCST_SHIFT))&MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK                      0x2u
+#define MCG_S_OSCINIT0_SHIFT                     1
+#define MCG_S_OSCINIT0_WIDTH                     1
+#define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK                         0xCu
+#define MCG_S_CLKST_SHIFT                        2
+#define MCG_S_CLKST_WIDTH                        2
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK                        0x10u
+#define MCG_S_IREFST_SHIFT                       4
+#define MCG_S_IREFST_WIDTH                       1
+#define MCG_S_IREFST(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_S_IREFST_SHIFT))&MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK                         0x20u
+#define MCG_S_PLLST_SHIFT                        5
+#define MCG_S_PLLST_WIDTH                        1
+#define MCG_S_PLLST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_PLLST_SHIFT))&MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK                         0x40u
+#define MCG_S_LOCK0_SHIFT                        6
+#define MCG_S_LOCK0_WIDTH                        1
+#define MCG_S_LOCK0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOCK0_SHIFT))&MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK                         0x80u
+#define MCG_S_LOLS0_SHIFT                        7
+#define MCG_S_LOLS0_WIDTH                        1
+#define MCG_S_LOLS0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOLS0_SHIFT))&MCG_S_LOLS0_MASK)
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK                        0x1u
+#define MCG_SC_LOCS0_SHIFT                       0
+#define MCG_SC_LOCS0_WIDTH                       1
+#define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_SC_LOCS0_SHIFT))&MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK                       0xEu
+#define MCG_SC_FCRDIV_SHIFT                      1
+#define MCG_SC_FCRDIV_WIDTH                      3
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK                     0x10u
+#define MCG_SC_FLTPRSRV_SHIFT                    4
+#define MCG_SC_FLTPRSRV_WIDTH                    1
+#define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_SC_FLTPRSRV_SHIFT))&MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK                         0x20u
+#define MCG_SC_ATMF_SHIFT                        5
+#define MCG_SC_ATMF_WIDTH                        1
+#define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMF_SHIFT))&MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK                         0x40u
+#define MCG_SC_ATMS_SHIFT                        6
+#define MCG_SC_ATMS_WIDTH                        1
+#define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMS_SHIFT))&MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK                         0x80u
+#define MCG_SC_ATME_SHIFT                        7
+#define MCG_SC_ATME_WIDTH                        1
+#define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATME_SHIFT))&MCG_SC_ATME_MASK)
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK                     0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT                    0
+#define MCG_ATCVH_ATCVH_WIDTH                    8
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK                     0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT                    0
+#define MCG_ATCVL_ATCVL_WIDTH                    8
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK                       0x3u
+#define MCG_C7_OSCSEL_SHIFT                      0
+#define MCG_C7_OSCSEL_WIDTH                      2
+#define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK                        0x1u
+#define MCG_C8_LOCS1_SHIFT                       0
+#define MCG_C8_LOCS1_WIDTH                       1
+#define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCS1_SHIFT))&MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK                         0x20u
+#define MCG_C8_CME1_SHIFT                        5
+#define MCG_C8_CME1_WIDTH                        1
+#define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C8_CME1_SHIFT))&MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK                        0x40u
+#define MCG_C8_LOLRE_SHIFT                       6
+#define MCG_C8_LOLRE_WIDTH                       1
+#define MCG_C8_LOLRE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOLRE_SHIFT))&MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK                       0x80u
+#define MCG_C8_LOCRE1_SHIFT                      7
+#define MCG_C8_LOCRE1_WIDTH                      1
+#define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCRE1_SHIFT))&MCG_C8_LOCRE1_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR                             (MCG)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS                           { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS                            { MCG }
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1                                   MCG_C1_REG(MCG)
+#define MCG_C2                                   MCG_C2_REG(MCG)
+#define MCG_C3                                   MCG_C3_REG(MCG)
+#define MCG_C4                                   MCG_C4_REG(MCG)
+#define MCG_C5                                   MCG_C5_REG(MCG)
+#define MCG_C6                                   MCG_C6_REG(MCG)
+#define MCG_S                                    MCG_S_REG(MCG)
+#define MCG_SC                                   MCG_SC_REG(MCG)
+#define MCG_ATCVH                                MCG_ATCVH_REG(MCG)
+#define MCG_ATCVL                                MCG_ATCVL_REG(MCG)
+#define MCG_C7                                   MCG_C7_REG(MCG)
+#define MCG_C8                                   MCG_C8_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t CR;                                /**< Control Register, offset: 0xC */
+  __IO uint32_t ISCR;                              /**< Interrupt Status Register, offset: 0x10 */
+  __IO uint32_t ETBCC;                             /**< ETB Counter Control register, offset: 0x14 */
+  __IO uint32_t ETBRL;                             /**< ETB Reload register, offset: 0x18 */
+  __I  uint32_t ETBCNT;                            /**< ETB Counter Value register, offset: 0x1C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PID;                               /**< Process ID register, offset: 0x30 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base)                      ((base)->PLASC)
+#define MCM_PLAMC_REG(base)                      ((base)->PLAMC)
+#define MCM_CR_REG(base)                         ((base)->CR)
+#define MCM_ISCR_REG(base)                       ((base)->ISCR)
+#define MCM_ETBCC_REG(base)                      ((base)->ETBCC)
+#define MCM_ETBRL_REG(base)                      ((base)->ETBRL)
+#define MCM_ETBCNT_REG(base)                     ((base)->ETBCNT)
+#define MCM_PID_REG(base)                        ((base)->PID)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK                       0xFFu
+#define MCM_PLASC_ASC_SHIFT                      0
+#define MCM_PLASC_ASC_WIDTH                      8
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK                       0xFFu
+#define MCM_PLAMC_AMC_SHIFT                      0
+#define MCM_PLAMC_AMC_WIDTH                      8
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* CR Bit Fields */
+#define MCM_CR_SRAMUAP_MASK                      0x3000000u
+#define MCM_CR_SRAMUAP_SHIFT                     24
+#define MCM_CR_SRAMUAP_WIDTH                     2
+#define MCM_CR_SRAMUAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP_MASK                      0x4000000u
+#define MCM_CR_SRAMUWP_SHIFT                     26
+#define MCM_CR_SRAMUWP_WIDTH                     1
+#define MCM_CR_SRAMUWP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUWP_SHIFT))&MCM_CR_SRAMUWP_MASK)
+#define MCM_CR_SRAMLAP_MASK                      0x30000000u
+#define MCM_CR_SRAMLAP_SHIFT                     28
+#define MCM_CR_SRAMLAP_WIDTH                     2
+#define MCM_CR_SRAMLAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP_MASK                      0x40000000u
+#define MCM_CR_SRAMLWP_SHIFT                     30
+#define MCM_CR_SRAMLWP_WIDTH                     1
+#define MCM_CR_SRAMLWP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLWP_SHIFT))&MCM_CR_SRAMLWP_MASK)
+/* ISCR Bit Fields */
+#define MCM_ISCR_IRQ_MASK                        0x2u
+#define MCM_ISCR_IRQ_SHIFT                       1
+#define MCM_ISCR_IRQ_WIDTH                       1
+#define MCM_ISCR_IRQ(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_IRQ_SHIFT))&MCM_ISCR_IRQ_MASK)
+#define MCM_ISCR_NMI_MASK                        0x4u
+#define MCM_ISCR_NMI_SHIFT                       2
+#define MCM_ISCR_NMI_WIDTH                       1
+#define MCM_ISCR_NMI(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_NMI_SHIFT))&MCM_ISCR_NMI_MASK)
+#define MCM_ISCR_DHREQ_MASK                      0x8u
+#define MCM_ISCR_DHREQ_SHIFT                     3
+#define MCM_ISCR_DHREQ_WIDTH                     1
+#define MCM_ISCR_DHREQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_DHREQ_SHIFT))&MCM_ISCR_DHREQ_MASK)
+#define MCM_ISCR_FIOC_MASK                       0x100u
+#define MCM_ISCR_FIOC_SHIFT                      8
+#define MCM_ISCR_FIOC_WIDTH                      1
+#define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FDZC_MASK                       0x200u
+#define MCM_ISCR_FDZC_SHIFT                      9
+#define MCM_ISCR_FDZC_WIDTH                      1
+#define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FOFC_MASK                       0x400u
+#define MCM_ISCR_FOFC_SHIFT                      10
+#define MCM_ISCR_FOFC_WIDTH                      1
+#define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FUFC_MASK                       0x800u
+#define MCM_ISCR_FUFC_SHIFT                      11
+#define MCM_ISCR_FUFC_WIDTH                      1
+#define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FIXC_MASK                       0x1000u
+#define MCM_ISCR_FIXC_SHIFT                      12
+#define MCM_ISCR_FIXC_WIDTH                      1
+#define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIDC_MASK                       0x8000u
+#define MCM_ISCR_FIDC_SHIFT                      15
+#define MCM_ISCR_FIDC_WIDTH                      1
+#define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIOCE_MASK                      0x1000000u
+#define MCM_ISCR_FIOCE_SHIFT                     24
+#define MCM_ISCR_FIOCE_WIDTH                     1
+#define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FDZCE_MASK                      0x2000000u
+#define MCM_ISCR_FDZCE_SHIFT                     25
+#define MCM_ISCR_FDZCE_WIDTH                     1
+#define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FOFCE_MASK                      0x4000000u
+#define MCM_ISCR_FOFCE_SHIFT                     26
+#define MCM_ISCR_FOFCE_WIDTH                     1
+#define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FUFCE_MASK                      0x8000000u
+#define MCM_ISCR_FUFCE_SHIFT                     27
+#define MCM_ISCR_FUFCE_WIDTH                     1
+#define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FIXCE_MASK                      0x10000000u
+#define MCM_ISCR_FIXCE_SHIFT                     28
+#define MCM_ISCR_FIXCE_WIDTH                     1
+#define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIDCE_MASK                      0x80000000u
+#define MCM_ISCR_FIDCE_SHIFT                     31
+#define MCM_ISCR_FIDCE_WIDTH                     1
+#define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
+/* ETBCC Bit Fields */
+#define MCM_ETBCC_CNTEN_MASK                     0x1u
+#define MCM_ETBCC_CNTEN_SHIFT                    0
+#define MCM_ETBCC_CNTEN_WIDTH                    1
+#define MCM_ETBCC_CNTEN(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_CNTEN_SHIFT))&MCM_ETBCC_CNTEN_MASK)
+#define MCM_ETBCC_RSPT_MASK                      0x6u
+#define MCM_ETBCC_RSPT_SHIFT                     1
+#define MCM_ETBCC_RSPT_WIDTH                     2
+#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK                      0x8u
+#define MCM_ETBCC_RLRQ_SHIFT                     3
+#define MCM_ETBCC_RLRQ_WIDTH                     1
+#define MCM_ETBCC_RLRQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RLRQ_SHIFT))&MCM_ETBCC_RLRQ_MASK)
+#define MCM_ETBCC_ETDIS_MASK                     0x10u
+#define MCM_ETBCC_ETDIS_SHIFT                    4
+#define MCM_ETBCC_ETDIS_WIDTH                    1
+#define MCM_ETBCC_ETDIS(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ETDIS_SHIFT))&MCM_ETBCC_ETDIS_MASK)
+#define MCM_ETBCC_ITDIS_MASK                     0x20u
+#define MCM_ETBCC_ITDIS_SHIFT                    5
+#define MCM_ETBCC_ITDIS_WIDTH                    1
+#define MCM_ETBCC_ITDIS(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ITDIS_SHIFT))&MCM_ETBCC_ITDIS_MASK)
+/* ETBRL Bit Fields */
+#define MCM_ETBRL_RELOAD_MASK                    0x7FFu
+#define MCM_ETBRL_RELOAD_SHIFT                   0
+#define MCM_ETBRL_RELOAD_WIDTH                   11
+#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
+/* ETBCNT Bit Fields */
+#define MCM_ETBCNT_COUNTER_MASK                  0x7FFu
+#define MCM_ETBCNT_COUNTER_SHIFT                 0
+#define MCM_ETBCNT_COUNTER_WIDTH                 11
+#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
+/* PID Bit Fields */
+#define MCM_PID_PID_MASK                         0xFFu
+#define MCM_PID_PID_SHIFT                        0
+#define MCM_PID_PID_WIDTH                        8
+#define MCM_PID_PID(x)                           (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR                             (MCM)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { MCM }
+/** Interrupt vectors for the MCM peripheral type */
+#define MCM_IRQS                                 { MCM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC                                MCM_PLASC_REG(MCM)
+#define MCM_PLAMC                                MCM_PLAMC_REG(MCM)
+#define MCM_CR                                   MCM_CR_REG(MCM)
+#define MCM_ISCR                                 MCM_ISCR_REG(MCM)
+#define MCM_ETBCC                                MCM_ETBCC_REG(MCM)
+#define MCM_ETBRL                                MCM_ETBRL_REG(MCM)
+#define MCM_ETBCNT                               MCM_ETBCNT_REG(MCM)
+#define MCM_PID                                  MCM_PID_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
+ * @{
+ */
+
+/** MPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} MPU_Type, *MPU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register accessors */
+#define MPU_CESR_REG(base)                       ((base)->CESR)
+#define MPU_EAR_REG(base,index)                  ((base)->SP[index].EAR)
+#define MPU_EAR_COUNT                            5
+#define MPU_EDR_REG(base,index)                  ((base)->SP[index].EDR)
+#define MPU_EDR_COUNT                            5
+#define MPU_WORD_REG(base,index,index2)          ((base)->WORD[index][index2])
+#define MPU_WORD_COUNT                           12
+#define MPU_WORD_COUNT2                          4
+#define MPU_RGDAAC_REG(base,index)               ((base)->RGDAAC[index])
+#define MPU_RGDAAC_COUNT                         12
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Masks MPU Register Masks
+ * @{
+ */
+
+/* CESR Bit Fields */
+#define MPU_CESR_VLD_MASK                        0x1u
+#define MPU_CESR_VLD_SHIFT                       0
+#define MPU_CESR_VLD_WIDTH                       1
+#define MPU_CESR_VLD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_VLD_SHIFT))&MPU_CESR_VLD_MASK)
+#define MPU_CESR_NRGD_MASK                       0xF00u
+#define MPU_CESR_NRGD_SHIFT                      8
+#define MPU_CESR_NRGD_WIDTH                      4
+#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
+#define MPU_CESR_NSP_MASK                        0xF000u
+#define MPU_CESR_NSP_SHIFT                       12
+#define MPU_CESR_NSP_WIDTH                       4
+#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
+#define MPU_CESR_HRL_MASK                        0xF0000u
+#define MPU_CESR_HRL_SHIFT                       16
+#define MPU_CESR_HRL_WIDTH                       4
+#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
+#define MPU_CESR_SPERR_MASK                      0xF8000000u
+#define MPU_CESR_SPERR_SHIFT                     27
+#define MPU_CESR_SPERR_WIDTH                     5
+#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
+/* EAR Bit Fields */
+#define MPU_EAR_EADDR_MASK                       0xFFFFFFFFu
+#define MPU_EAR_EADDR_SHIFT                      0
+#define MPU_EAR_EADDR_WIDTH                      32
+#define MPU_EAR_EADDR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
+/* EDR Bit Fields */
+#define MPU_EDR_ERW_MASK                         0x1u
+#define MPU_EDR_ERW_SHIFT                        0
+#define MPU_EDR_ERW_WIDTH                        1
+#define MPU_EDR_ERW(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_ERW_SHIFT))&MPU_EDR_ERW_MASK)
+#define MPU_EDR_EATTR_MASK                       0xEu
+#define MPU_EDR_EATTR_SHIFT                      1
+#define MPU_EDR_EATTR_WIDTH                      3
+#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
+#define MPU_EDR_EMN_MASK                         0xF0u
+#define MPU_EDR_EMN_SHIFT                        4
+#define MPU_EDR_EMN_WIDTH                        4
+#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
+#define MPU_EDR_EPID_MASK                        0xFF00u
+#define MPU_EDR_EPID_SHIFT                       8
+#define MPU_EDR_EPID_WIDTH                       8
+#define MPU_EDR_EPID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
+#define MPU_EDR_EACD_MASK                        0xFFFF0000u
+#define MPU_EDR_EACD_SHIFT                       16
+#define MPU_EDR_EACD_WIDTH                       16
+#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
+/* WORD Bit Fields */
+#define MPU_WORD_VLD_MASK                        0x1u
+#define MPU_WORD_VLD_SHIFT                       0
+#define MPU_WORD_VLD_WIDTH                       1
+#define MPU_WORD_VLD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_VLD_SHIFT))&MPU_WORD_VLD_MASK)
+#define MPU_WORD_M0UM_MASK                       0x7u
+#define MPU_WORD_M0UM_SHIFT                      0
+#define MPU_WORD_M0UM_WIDTH                      3
+#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
+#define MPU_WORD_M0SM_MASK                       0x18u
+#define MPU_WORD_M0SM_SHIFT                      3
+#define MPU_WORD_M0SM_WIDTH                      2
+#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
+#define MPU_WORD_M0PE_MASK                       0x20u
+#define MPU_WORD_M0PE_SHIFT                      5
+#define MPU_WORD_M0PE_WIDTH                      1
+#define MPU_WORD_M0PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0PE_SHIFT))&MPU_WORD_M0PE_MASK)
+#define MPU_WORD_ENDADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_ENDADDR_SHIFT                   5
+#define MPU_WORD_ENDADDR_WIDTH                   27
+#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
+#define MPU_WORD_SRTADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_SRTADDR_SHIFT                   5
+#define MPU_WORD_SRTADDR_WIDTH                   27
+#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
+#define MPU_WORD_M1UM_MASK                       0x1C0u
+#define MPU_WORD_M1UM_SHIFT                      6
+#define MPU_WORD_M1UM_WIDTH                      3
+#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
+#define MPU_WORD_M1SM_MASK                       0x600u
+#define MPU_WORD_M1SM_SHIFT                      9
+#define MPU_WORD_M1SM_WIDTH                      2
+#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
+#define MPU_WORD_M1PE_MASK                       0x800u
+#define MPU_WORD_M1PE_SHIFT                      11
+#define MPU_WORD_M1PE_WIDTH                      1
+#define MPU_WORD_M1PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1PE_SHIFT))&MPU_WORD_M1PE_MASK)
+#define MPU_WORD_M2UM_MASK                       0x7000u
+#define MPU_WORD_M2UM_SHIFT                      12
+#define MPU_WORD_M2UM_WIDTH                      3
+#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
+#define MPU_WORD_M2SM_MASK                       0x18000u
+#define MPU_WORD_M2SM_SHIFT                      15
+#define MPU_WORD_M2SM_WIDTH                      2
+#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
+#define MPU_WORD_PIDMASK_MASK                    0xFF0000u
+#define MPU_WORD_PIDMASK_SHIFT                   16
+#define MPU_WORD_PIDMASK_WIDTH                   8
+#define MPU_WORD_PIDMASK(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
+#define MPU_WORD_M2PE_MASK                       0x20000u
+#define MPU_WORD_M2PE_SHIFT                      17
+#define MPU_WORD_M2PE_WIDTH                      1
+#define MPU_WORD_M2PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2PE_SHIFT))&MPU_WORD_M2PE_MASK)
+#define MPU_WORD_M3UM_MASK                       0x1C0000u
+#define MPU_WORD_M3UM_SHIFT                      18
+#define MPU_WORD_M3UM_WIDTH                      3
+#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
+#define MPU_WORD_M3SM_MASK                       0x600000u
+#define MPU_WORD_M3SM_SHIFT                      21
+#define MPU_WORD_M3SM_WIDTH                      2
+#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
+#define MPU_WORD_M3PE_MASK                       0x800000u
+#define MPU_WORD_M3PE_SHIFT                      23
+#define MPU_WORD_M3PE_WIDTH                      1
+#define MPU_WORD_M3PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3PE_SHIFT))&MPU_WORD_M3PE_MASK)
+#define MPU_WORD_PID_MASK                        0xFF000000u
+#define MPU_WORD_PID_SHIFT                       24
+#define MPU_WORD_PID_WIDTH                       8
+#define MPU_WORD_PID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
+#define MPU_WORD_M4WE_MASK                       0x1000000u
+#define MPU_WORD_M4WE_SHIFT                      24
+#define MPU_WORD_M4WE_WIDTH                      1
+#define MPU_WORD_M4WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4WE_SHIFT))&MPU_WORD_M4WE_MASK)
+#define MPU_WORD_M4RE_MASK                       0x2000000u
+#define MPU_WORD_M4RE_SHIFT                      25
+#define MPU_WORD_M4RE_WIDTH                      1
+#define MPU_WORD_M4RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4RE_SHIFT))&MPU_WORD_M4RE_MASK)
+#define MPU_WORD_M5WE_MASK                       0x4000000u
+#define MPU_WORD_M5WE_SHIFT                      26
+#define MPU_WORD_M5WE_WIDTH                      1
+#define MPU_WORD_M5WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5WE_SHIFT))&MPU_WORD_M5WE_MASK)
+#define MPU_WORD_M5RE_MASK                       0x8000000u
+#define MPU_WORD_M5RE_SHIFT                      27
+#define MPU_WORD_M5RE_WIDTH                      1
+#define MPU_WORD_M5RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5RE_SHIFT))&MPU_WORD_M5RE_MASK)
+#define MPU_WORD_M6WE_MASK                       0x10000000u
+#define MPU_WORD_M6WE_SHIFT                      28
+#define MPU_WORD_M6WE_WIDTH                      1
+#define MPU_WORD_M6WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6WE_SHIFT))&MPU_WORD_M6WE_MASK)
+#define MPU_WORD_M6RE_MASK                       0x20000000u
+#define MPU_WORD_M6RE_SHIFT                      29
+#define MPU_WORD_M6RE_WIDTH                      1
+#define MPU_WORD_M6RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6RE_SHIFT))&MPU_WORD_M6RE_MASK)
+#define MPU_WORD_M7WE_MASK                       0x40000000u
+#define MPU_WORD_M7WE_SHIFT                      30
+#define MPU_WORD_M7WE_WIDTH                      1
+#define MPU_WORD_M7WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7WE_SHIFT))&MPU_WORD_M7WE_MASK)
+#define MPU_WORD_M7RE_MASK                       0x80000000u
+#define MPU_WORD_M7RE_SHIFT                      31
+#define MPU_WORD_M7RE_WIDTH                      1
+#define MPU_WORD_M7RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7RE_SHIFT))&MPU_WORD_M7RE_MASK)
+/* RGDAAC Bit Fields */
+#define MPU_RGDAAC_M0UM_MASK                     0x7u
+#define MPU_RGDAAC_M0UM_SHIFT                    0
+#define MPU_RGDAAC_M0UM_WIDTH                    3
+#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
+#define MPU_RGDAAC_M0SM_MASK                     0x18u
+#define MPU_RGDAAC_M0SM_SHIFT                    3
+#define MPU_RGDAAC_M0SM_WIDTH                    2
+#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
+#define MPU_RGDAAC_M0PE_MASK                     0x20u
+#define MPU_RGDAAC_M0PE_SHIFT                    5
+#define MPU_RGDAAC_M0PE_WIDTH                    1
+#define MPU_RGDAAC_M0PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0PE_SHIFT))&MPU_RGDAAC_M0PE_MASK)
+#define MPU_RGDAAC_M1UM_MASK                     0x1C0u
+#define MPU_RGDAAC_M1UM_SHIFT                    6
+#define MPU_RGDAAC_M1UM_WIDTH                    3
+#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
+#define MPU_RGDAAC_M1SM_MASK                     0x600u
+#define MPU_RGDAAC_M1SM_SHIFT                    9
+#define MPU_RGDAAC_M1SM_WIDTH                    2
+#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
+#define MPU_RGDAAC_M1PE_MASK                     0x800u
+#define MPU_RGDAAC_M1PE_SHIFT                    11
+#define MPU_RGDAAC_M1PE_WIDTH                    1
+#define MPU_RGDAAC_M1PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1PE_SHIFT))&MPU_RGDAAC_M1PE_MASK)
+#define MPU_RGDAAC_M2UM_MASK                     0x7000u
+#define MPU_RGDAAC_M2UM_SHIFT                    12
+#define MPU_RGDAAC_M2UM_WIDTH                    3
+#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
+#define MPU_RGDAAC_M2SM_MASK                     0x18000u
+#define MPU_RGDAAC_M2SM_SHIFT                    15
+#define MPU_RGDAAC_M2SM_WIDTH                    2
+#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
+#define MPU_RGDAAC_M2PE_MASK                     0x20000u
+#define MPU_RGDAAC_M2PE_SHIFT                    17
+#define MPU_RGDAAC_M2PE_WIDTH                    1
+#define MPU_RGDAAC_M2PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2PE_SHIFT))&MPU_RGDAAC_M2PE_MASK)
+#define MPU_RGDAAC_M3UM_MASK                     0x1C0000u
+#define MPU_RGDAAC_M3UM_SHIFT                    18
+#define MPU_RGDAAC_M3UM_WIDTH                    3
+#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
+#define MPU_RGDAAC_M3SM_MASK                     0x600000u
+#define MPU_RGDAAC_M3SM_SHIFT                    21
+#define MPU_RGDAAC_M3SM_WIDTH                    2
+#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
+#define MPU_RGDAAC_M3PE_MASK                     0x800000u
+#define MPU_RGDAAC_M3PE_SHIFT                    23
+#define MPU_RGDAAC_M3PE_WIDTH                    1
+#define MPU_RGDAAC_M3PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3PE_SHIFT))&MPU_RGDAAC_M3PE_MASK)
+#define MPU_RGDAAC_M4WE_MASK                     0x1000000u
+#define MPU_RGDAAC_M4WE_SHIFT                    24
+#define MPU_RGDAAC_M4WE_WIDTH                    1
+#define MPU_RGDAAC_M4WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4WE_SHIFT))&MPU_RGDAAC_M4WE_MASK)
+#define MPU_RGDAAC_M4RE_MASK                     0x2000000u
+#define MPU_RGDAAC_M4RE_SHIFT                    25
+#define MPU_RGDAAC_M4RE_WIDTH                    1
+#define MPU_RGDAAC_M4RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4RE_SHIFT))&MPU_RGDAAC_M4RE_MASK)
+#define MPU_RGDAAC_M5WE_MASK                     0x4000000u
+#define MPU_RGDAAC_M5WE_SHIFT                    26
+#define MPU_RGDAAC_M5WE_WIDTH                    1
+#define MPU_RGDAAC_M5WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5WE_SHIFT))&MPU_RGDAAC_M5WE_MASK)
+#define MPU_RGDAAC_M5RE_MASK                     0x8000000u
+#define MPU_RGDAAC_M5RE_SHIFT                    27
+#define MPU_RGDAAC_M5RE_WIDTH                    1
+#define MPU_RGDAAC_M5RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5RE_SHIFT))&MPU_RGDAAC_M5RE_MASK)
+#define MPU_RGDAAC_M6WE_MASK                     0x10000000u
+#define MPU_RGDAAC_M6WE_SHIFT                    28
+#define MPU_RGDAAC_M6WE_WIDTH                    1
+#define MPU_RGDAAC_M6WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6WE_SHIFT))&MPU_RGDAAC_M6WE_MASK)
+#define MPU_RGDAAC_M6RE_MASK                     0x20000000u
+#define MPU_RGDAAC_M6RE_SHIFT                    29
+#define MPU_RGDAAC_M6RE_WIDTH                    1
+#define MPU_RGDAAC_M6RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6RE_SHIFT))&MPU_RGDAAC_M6RE_MASK)
+#define MPU_RGDAAC_M7WE_MASK                     0x40000000u
+#define MPU_RGDAAC_M7WE_SHIFT                    30
+#define MPU_RGDAAC_M7WE_WIDTH                    1
+#define MPU_RGDAAC_M7WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7WE_SHIFT))&MPU_RGDAAC_M7WE_MASK)
+#define MPU_RGDAAC_M7RE_MASK                     0x80000000u
+#define MPU_RGDAAC_M7RE_SHIFT                    31
+#define MPU_RGDAAC_M7RE_WIDTH                    1
+#define MPU_RGDAAC_M7RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7RE_SHIFT))&MPU_RGDAAC_M7RE_MASK)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Masks */
+
+
+/* MPU - Peripheral instance base addresses */
+/** Peripheral MPU base address */
+#define MPU_BASE                                 (0x4000D000u)
+/** Peripheral MPU base pointer */
+#define MPU                                      ((MPU_Type *)MPU_BASE)
+#define MPU_BASE_PTR                             (MPU)
+/** Array initializer of MPU peripheral base addresses */
+#define MPU_BASE_ADDRS                           { MPU_BASE }
+/** Array initializer of MPU peripheral base pointers */
+#define MPU_BASE_PTRS                            { MPU }
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register instance definitions */
+/* MPU */
+#define MPU_CESR                                 MPU_CESR_REG(MPU)
+#define MPU_EAR0                                 MPU_EAR_REG(MPU,0)
+#define MPU_EDR0                                 MPU_EDR_REG(MPU,0)
+#define MPU_EAR1                                 MPU_EAR_REG(MPU,1)
+#define MPU_EDR1                                 MPU_EDR_REG(MPU,1)
+#define MPU_EAR2                                 MPU_EAR_REG(MPU,2)
+#define MPU_EDR2                                 MPU_EDR_REG(MPU,2)
+#define MPU_EAR3                                 MPU_EAR_REG(MPU,3)
+#define MPU_EDR3                                 MPU_EDR_REG(MPU,3)
+#define MPU_EAR4                                 MPU_EAR_REG(MPU,4)
+#define MPU_EDR4                                 MPU_EDR_REG(MPU,4)
+#define MPU_RGD0_WORD0                           MPU_WORD_REG(MPU,0,0)
+#define MPU_RGD0_WORD1                           MPU_WORD_REG(MPU,0,1)
+#define MPU_RGD0_WORD2                           MPU_WORD_REG(MPU,0,2)
+#define MPU_RGD0_WORD3                           MPU_WORD_REG(MPU,0,3)
+#define MPU_RGD1_WORD0                           MPU_WORD_REG(MPU,1,0)
+#define MPU_RGD1_WORD1                           MPU_WORD_REG(MPU,1,1)
+#define MPU_RGD1_WORD2                           MPU_WORD_REG(MPU,1,2)
+#define MPU_RGD1_WORD3                           MPU_WORD_REG(MPU,1,3)
+#define MPU_RGD2_WORD0                           MPU_WORD_REG(MPU,2,0)
+#define MPU_RGD2_WORD1                           MPU_WORD_REG(MPU,2,1)
+#define MPU_RGD2_WORD2                           MPU_WORD_REG(MPU,2,2)
+#define MPU_RGD2_WORD3                           MPU_WORD_REG(MPU,2,3)
+#define MPU_RGD3_WORD0                           MPU_WORD_REG(MPU,3,0)
+#define MPU_RGD3_WORD1                           MPU_WORD_REG(MPU,3,1)
+#define MPU_RGD3_WORD2                           MPU_WORD_REG(MPU,3,2)
+#define MPU_RGD3_WORD3                           MPU_WORD_REG(MPU,3,3)
+#define MPU_RGD4_WORD0                           MPU_WORD_REG(MPU,4,0)
+#define MPU_RGD4_WORD1                           MPU_WORD_REG(MPU,4,1)
+#define MPU_RGD4_WORD2                           MPU_WORD_REG(MPU,4,2)
+#define MPU_RGD4_WORD3                           MPU_WORD_REG(MPU,4,3)
+#define MPU_RGD5_WORD0                           MPU_WORD_REG(MPU,5,0)
+#define MPU_RGD5_WORD1                           MPU_WORD_REG(MPU,5,1)
+#define MPU_RGD5_WORD2                           MPU_WORD_REG(MPU,5,2)
+#define MPU_RGD5_WORD3                           MPU_WORD_REG(MPU,5,3)
+#define MPU_RGD6_WORD0                           MPU_WORD_REG(MPU,6,0)
+#define MPU_RGD6_WORD1                           MPU_WORD_REG(MPU,6,1)
+#define MPU_RGD6_WORD2                           MPU_WORD_REG(MPU,6,2)
+#define MPU_RGD6_WORD3                           MPU_WORD_REG(MPU,6,3)
+#define MPU_RGD7_WORD0                           MPU_WORD_REG(MPU,7,0)
+#define MPU_RGD7_WORD1                           MPU_WORD_REG(MPU,7,1)
+#define MPU_RGD7_WORD2                           MPU_WORD_REG(MPU,7,2)
+#define MPU_RGD7_WORD3                           MPU_WORD_REG(MPU,7,3)
+#define MPU_RGD8_WORD0                           MPU_WORD_REG(MPU,8,0)
+#define MPU_RGD8_WORD1                           MPU_WORD_REG(MPU,8,1)
+#define MPU_RGD8_WORD2                           MPU_WORD_REG(MPU,8,2)
+#define MPU_RGD8_WORD3                           MPU_WORD_REG(MPU,8,3)
+#define MPU_RGD9_WORD0                           MPU_WORD_REG(MPU,9,0)
+#define MPU_RGD9_WORD1                           MPU_WORD_REG(MPU,9,1)
+#define MPU_RGD9_WORD2                           MPU_WORD_REG(MPU,9,2)
+#define MPU_RGD9_WORD3                           MPU_WORD_REG(MPU,9,3)
+#define MPU_RGD10_WORD0                          MPU_WORD_REG(MPU,10,0)
+#define MPU_RGD10_WORD1                          MPU_WORD_REG(MPU,10,1)
+#define MPU_RGD10_WORD2                          MPU_WORD_REG(MPU,10,2)
+#define MPU_RGD10_WORD3                          MPU_WORD_REG(MPU,10,3)
+#define MPU_RGD11_WORD0                          MPU_WORD_REG(MPU,11,0)
+#define MPU_RGD11_WORD1                          MPU_WORD_REG(MPU,11,1)
+#define MPU_RGD11_WORD2                          MPU_WORD_REG(MPU,11,2)
+#define MPU_RGD11_WORD3                          MPU_WORD_REG(MPU,11,3)
+#define MPU_RGDAAC0                              MPU_RGDAAC_REG(MPU,0)
+#define MPU_RGDAAC1                              MPU_RGDAAC_REG(MPU,1)
+#define MPU_RGDAAC2                              MPU_RGDAAC_REG(MPU,2)
+#define MPU_RGDAAC3                              MPU_RGDAAC_REG(MPU,3)
+#define MPU_RGDAAC4                              MPU_RGDAAC_REG(MPU,4)
+#define MPU_RGDAAC5                              MPU_RGDAAC_REG(MPU,5)
+#define MPU_RGDAAC6                              MPU_RGDAAC_REG(MPU,6)
+#define MPU_RGDAAC7                              MPU_RGDAAC_REG(MPU,7)
+#define MPU_RGDAAC8                              MPU_RGDAAC_REG(MPU,8)
+#define MPU_RGDAAC9                              MPU_RGDAAC_REG(MPU,9)
+#define MPU_RGDAAC10                             MPU_RGDAAC_REG(MPU,10)
+#define MPU_RGDAAC11                             MPU_RGDAAC_REG(MPU,11)
+
+/* MPU - Register array accessors */
+#define MPU_EAR(index)                           MPU_EAR_REG(MPU,index)
+#define MPU_EDR(index)                           MPU_EDR_REG(MPU,index)
+#define MPU_WORD(index,index2)                   MPU_WORD_REG(MPU,index,index2)
+#define MPU_RGDAAC(index)                        MPU_RGDAAC_REG(MPU,index)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+  __I  uint8_t FEPROT;                             /**< Non-volatile EERAM Protection Register, offset: 0xE */
+  __I  uint8_t FDPROT;                             /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base)                    ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base)                    ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base)                    ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base)                    ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base)                    ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base)                    ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base)                    ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base)                    ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base)                      ((base)->FPROT3)
+#define NV_FPROT2_REG(base)                      ((base)->FPROT2)
+#define NV_FPROT1_REG(base)                      ((base)->FPROT1)
+#define NV_FPROT0_REG(base)                      ((base)->FPROT0)
+#define NV_FSEC_REG(base)                        ((base)->FSEC)
+#define NV_FOPT_REG(base)                        ((base)->FOPT)
+#define NV_FEPROT_REG(base)                      ((base)->FEPROT)
+#define NV_FDPROT_REG(base)                      ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK                     0xFFu
+#define NV_BACKKEY3_KEY_SHIFT                    0
+#define NV_BACKKEY3_KEY_WIDTH                    8
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK                     0xFFu
+#define NV_BACKKEY2_KEY_SHIFT                    0
+#define NV_BACKKEY2_KEY_WIDTH                    8
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK                     0xFFu
+#define NV_BACKKEY1_KEY_SHIFT                    0
+#define NV_BACKKEY1_KEY_WIDTH                    8
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK                     0xFFu
+#define NV_BACKKEY0_KEY_SHIFT                    0
+#define NV_BACKKEY0_KEY_WIDTH                    8
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK                     0xFFu
+#define NV_BACKKEY7_KEY_SHIFT                    0
+#define NV_BACKKEY7_KEY_WIDTH                    8
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK                     0xFFu
+#define NV_BACKKEY6_KEY_SHIFT                    0
+#define NV_BACKKEY6_KEY_WIDTH                    8
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK                     0xFFu
+#define NV_BACKKEY5_KEY_SHIFT                    0
+#define NV_BACKKEY5_KEY_WIDTH                    8
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK                     0xFFu
+#define NV_BACKKEY4_KEY_SHIFT                    0
+#define NV_BACKKEY4_KEY_WIDTH                    8
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK                      0xFFu
+#define NV_FPROT3_PROT_SHIFT                     0
+#define NV_FPROT3_PROT_WIDTH                     8
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK                      0xFFu
+#define NV_FPROT2_PROT_SHIFT                     0
+#define NV_FPROT2_PROT_WIDTH                     8
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK                      0xFFu
+#define NV_FPROT1_PROT_SHIFT                     0
+#define NV_FPROT1_PROT_WIDTH                     8
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK                      0xFFu
+#define NV_FPROT0_PROT_SHIFT                     0
+#define NV_FPROT0_PROT_WIDTH                     8
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK                         0x3u
+#define NV_FSEC_SEC_SHIFT                        0
+#define NV_FSEC_SEC_WIDTH                        2
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      0xCu
+#define NV_FSEC_FSLACC_SHIFT                     2
+#define NV_FSEC_FSLACC_WIDTH                     2
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        0x30u
+#define NV_FSEC_MEEN_SHIFT                       4
+#define NV_FSEC_MEEN_WIDTH                       2
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       0xC0u
+#define NV_FSEC_KEYEN_SHIFT                      6
+#define NV_FSEC_KEYEN_WIDTH                      2
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK                      0x1u
+#define NV_FOPT_LPBOOT_SHIFT                     0
+#define NV_FOPT_LPBOOT_WIDTH                     1
+#define NV_FOPT_LPBOOT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT_SHIFT))&NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK                  0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT                 1
+#define NV_FOPT_EZPORT_DIS_WIDTH                 1
+#define NV_FOPT_EZPORT_DIS(x)                    (((uint8_t)(((uint8_t)(x))<<NV_FOPT_EZPORT_DIS_SHIFT))&NV_FOPT_EZPORT_DIS_MASK)
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK                     0xFFu
+#define NV_FEPROT_EPROT_SHIFT                    0
+#define NV_FEPROT_EPROT_WIDTH                    8
+#define NV_FEPROT_EPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK                     0xFFu
+#define NV_FDPROT_DPROT_SHIFT                    0
+#define NV_FDPROT_DPROT_WIDTH                    8
+#define NV_FDPROT_DPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFE_FlashConfig base address */
+#define FTFE_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFE_FlashConfig base pointer */
+#define FTFE_FlashConfig                         ((NV_Type *)FTFE_FlashConfig_BASE)
+#define FTFE_FlashConfig_BASE_PTR                (FTFE_FlashConfig)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS                            { FTFE_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS                             { FTFE_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFE_FlashConfig */
+#define NV_BACKKEY3                              NV_BACKKEY3_REG(FTFE_FlashConfig)
+#define NV_BACKKEY2                              NV_BACKKEY2_REG(FTFE_FlashConfig)
+#define NV_BACKKEY1                              NV_BACKKEY1_REG(FTFE_FlashConfig)
+#define NV_BACKKEY0                              NV_BACKKEY0_REG(FTFE_FlashConfig)
+#define NV_BACKKEY7                              NV_BACKKEY7_REG(FTFE_FlashConfig)
+#define NV_BACKKEY6                              NV_BACKKEY6_REG(FTFE_FlashConfig)
+#define NV_BACKKEY5                              NV_BACKKEY5_REG(FTFE_FlashConfig)
+#define NV_BACKKEY4                              NV_BACKKEY4_REG(FTFE_FlashConfig)
+#define NV_FPROT3                                NV_FPROT3_REG(FTFE_FlashConfig)
+#define NV_FPROT2                                NV_FPROT2_REG(FTFE_FlashConfig)
+#define NV_FPROT1                                NV_FPROT1_REG(FTFE_FlashConfig)
+#define NV_FPROT0                                NV_FPROT0_REG(FTFE_FlashConfig)
+#define NV_FSEC                                  NV_FSEC_REG(FTFE_FlashConfig)
+#define NV_FOPT                                  NV_FOPT_REG(FTFE_FlashConfig)
+#define NV_FEPROT                                NV_FEPROT_REG(FTFE_FlashConfig)
+#define NV_FDPROT                                NV_FDPROT_REG(FTFE_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base)                         ((base)->CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK                        0x1u
+#define OSC_CR_SC16P_SHIFT                       0
+#define OSC_CR_SC16P_WIDTH                       1
+#define OSC_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK                         0x2u
+#define OSC_CR_SC8P_SHIFT                        1
+#define OSC_CR_SC8P_WIDTH                        1
+#define OSC_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK                         0x4u
+#define OSC_CR_SC4P_SHIFT                        2
+#define OSC_CR_SC4P_WIDTH                        1
+#define OSC_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK                         0x8u
+#define OSC_CR_SC2P_SHIFT                        3
+#define OSC_CR_SC2P_WIDTH                        1
+#define OSC_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK                     0x20u
+#define OSC_CR_EREFSTEN_SHIFT                    5
+#define OSC_CR_EREFSTEN_WIDTH                    1
+#define OSC_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK                      0x80u
+#define OSC_CR_ERCLKEN_SHIFT                     7
+#define OSC_CR_ERCLKEN_WIDTH                     1
+#define OSC_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE                                 (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC                                      ((OSC_Type *)OSC_BASE)
+#define OSC_BASE_PTR                             (OSC)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS                           { OSC_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS                            { OSC }
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC */
+#define OSC_CR                                   OSC_CR_REG(OSC)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control register, offset: 0x0 */
+  __IO uint32_t MOD;                               /**< Modulus register, offset: 0x4 */
+  __I  uint32_t CNT;                               /**< Counter register, offset: 0x8 */
+  __IO uint32_t IDLY;                              /**< Interrupt Delay register, offset: 0xC */
+  struct {                                         /* offset: 0x10, array step: 0x28 */
+    __IO uint32_t C1;                                /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+    __IO uint32_t S;                                 /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+    __IO uint32_t DLY[2];                            /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+         uint8_t RESERVED_0[24];
+  } CH[2];
+       uint8_t RESERVED_0[240];
+  struct {                                         /* offset: 0x150, array step: 0x8 */
+    __IO uint32_t INTC;                              /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+    __IO uint32_t INT;                               /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+  } DAC[2];
+       uint8_t RESERVED_1[48];
+  __IO uint32_t POEN;                              /**< Pulse-Out n Enable register, offset: 0x190 */
+  __IO uint32_t PODLY[3];                          /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type, *PDB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register accessors */
+#define PDB_SC_REG(base)                         ((base)->SC)
+#define PDB_MOD_REG(base)                        ((base)->MOD)
+#define PDB_CNT_REG(base)                        ((base)->CNT)
+#define PDB_IDLY_REG(base)                       ((base)->IDLY)
+#define PDB_C1_REG(base,index)                   ((base)->CH[index].C1)
+#define PDB_C1_COUNT                             2
+#define PDB_S_REG(base,index)                    ((base)->CH[index].S)
+#define PDB_S_COUNT                              2
+#define PDB_DLY_REG(base,index,index2)           ((base)->CH[index].DLY[index2])
+#define PDB_DLY_COUNT                            2
+#define PDB_DLY_COUNT2                           2
+#define PDB_INTC_REG(base,index)                 ((base)->DAC[index].INTC)
+#define PDB_INTC_COUNT                           2
+#define PDB_INT_REG(base,index)                  ((base)->DAC[index].INT)
+#define PDB_INT_COUNT                            2
+#define PDB_POEN_REG(base)                       ((base)->POEN)
+#define PDB_PODLY_REG(base,index)                ((base)->PODLY[index])
+#define PDB_PODLY_COUNT                          3
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK                         0x1u
+#define PDB_SC_LDOK_SHIFT                        0
+#define PDB_SC_LDOK_WIDTH                        1
+#define PDB_SC_LDOK(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK                         0x2u
+#define PDB_SC_CONT_SHIFT                        1
+#define PDB_SC_CONT_WIDTH                        1
+#define PDB_SC_CONT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK                         0xCu
+#define PDB_SC_MULT_SHIFT                        2
+#define PDB_SC_MULT_WIDTH                        2
+#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK                        0x20u
+#define PDB_SC_PDBIE_SHIFT                       5
+#define PDB_SC_PDBIE_WIDTH                       1
+#define PDB_SC_PDBIE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK                        0x40u
+#define PDB_SC_PDBIF_SHIFT                       6
+#define PDB_SC_PDBIF_WIDTH                       1
+#define PDB_SC_PDBIF(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK                        0x80u
+#define PDB_SC_PDBEN_SHIFT                       7
+#define PDB_SC_PDBEN_WIDTH                       1
+#define PDB_SC_PDBEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK                       0xF00u
+#define PDB_SC_TRGSEL_SHIFT                      8
+#define PDB_SC_TRGSEL_WIDTH                      4
+#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK                    0x7000u
+#define PDB_SC_PRESCALER_SHIFT                   12
+#define PDB_SC_PRESCALER_WIDTH                   3
+#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK                        0x8000u
+#define PDB_SC_DMAEN_SHIFT                       15
+#define PDB_SC_DMAEN_WIDTH                       1
+#define PDB_SC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK                       0x10000u
+#define PDB_SC_SWTRIG_SHIFT                      16
+#define PDB_SC_SWTRIG_WIDTH                      1
+#define PDB_SC_SWTRIG(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK                       0x20000u
+#define PDB_SC_PDBEIE_SHIFT                      17
+#define PDB_SC_PDBEIE_WIDTH                      1
+#define PDB_SC_PDBEIE(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK                        0xC0000u
+#define PDB_SC_LDMOD_SHIFT                       18
+#define PDB_SC_LDMOD_WIDTH                       2
+#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK                         0xFFFFu
+#define PDB_MOD_MOD_SHIFT                        0
+#define PDB_MOD_MOD_WIDTH                        16
+#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK                         0xFFFFu
+#define PDB_CNT_CNT_SHIFT                        0
+#define PDB_CNT_CNT_WIDTH                        16
+#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK                       0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT                      0
+#define PDB_IDLY_IDLY_WIDTH                      16
+#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK                           0xFFu
+#define PDB_C1_EN_SHIFT                          0
+#define PDB_C1_EN_WIDTH                          8
+#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK                          0xFF00u
+#define PDB_C1_TOS_SHIFT                         8
+#define PDB_C1_TOS_WIDTH                         8
+#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK                           0xFF0000u
+#define PDB_C1_BB_SHIFT                          16
+#define PDB_C1_BB_WIDTH                          8
+#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK                           0xFFu
+#define PDB_S_ERR_SHIFT                          0
+#define PDB_S_ERR_WIDTH                          8
+#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK                            0xFF0000u
+#define PDB_S_CF_SHIFT                           16
+#define PDB_S_CF_WIDTH                           8
+#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK                         0xFFFFu
+#define PDB_DLY_DLY_SHIFT                        0
+#define PDB_DLY_DLY_WIDTH                        16
+#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* INTC Bit Fields */
+#define PDB_INTC_TOE_MASK                        0x1u
+#define PDB_INTC_TOE_SHIFT                       0
+#define PDB_INTC_TOE_WIDTH                       1
+#define PDB_INTC_TOE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_TOE_SHIFT))&PDB_INTC_TOE_MASK)
+#define PDB_INTC_EXT_MASK                        0x2u
+#define PDB_INTC_EXT_SHIFT                       1
+#define PDB_INTC_EXT_WIDTH                       1
+#define PDB_INTC_EXT(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_EXT_SHIFT))&PDB_INTC_EXT_MASK)
+/* INT Bit Fields */
+#define PDB_INT_INT_MASK                         0xFFFFu
+#define PDB_INT_INT_SHIFT                        0
+#define PDB_INT_INT_WIDTH                        16
+#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK                       0xFFu
+#define PDB_POEN_POEN_SHIFT                      0
+#define PDB_POEN_POEN_WIDTH                      8
+#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK                      0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT                     0
+#define PDB_PODLY_DLY2_WIDTH                     16
+#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK                      0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT                     16
+#define PDB_PODLY_DLY1_WIDTH                     16
+#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE                                (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0                                     ((PDB_Type *)PDB0_BASE)
+#define PDB0_BASE_PTR                            (PDB0)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS                           { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS                            { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS                                 { PDB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register instance definitions */
+/* PDB0 */
+#define PDB0_SC                                  PDB_SC_REG(PDB0)
+#define PDB0_MOD                                 PDB_MOD_REG(PDB0)
+#define PDB0_CNT                                 PDB_CNT_REG(PDB0)
+#define PDB0_IDLY                                PDB_IDLY_REG(PDB0)
+#define PDB0_CH0C1                               PDB_C1_REG(PDB0,0)
+#define PDB0_CH0S                                PDB_S_REG(PDB0,0)
+#define PDB0_CH0DLY0                             PDB_DLY_REG(PDB0,0,0)
+#define PDB0_CH0DLY1                             PDB_DLY_REG(PDB0,0,1)
+#define PDB0_CH1C1                               PDB_C1_REG(PDB0,1)
+#define PDB0_CH1S                                PDB_S_REG(PDB0,1)
+#define PDB0_CH1DLY0                             PDB_DLY_REG(PDB0,1,0)
+#define PDB0_CH1DLY1                             PDB_DLY_REG(PDB0,1,1)
+#define PDB0_DACINTC0                            PDB_INTC_REG(PDB0,0)
+#define PDB0_DACINT0                             PDB_INT_REG(PDB0,0)
+#define PDB0_DACINTC1                            PDB_INTC_REG(PDB0,1)
+#define PDB0_DACINT1                             PDB_INT_REG(PDB0,1)
+#define PDB0_POEN                                PDB_POEN_REG(PDB0)
+#define PDB0_PO0DLY                              PDB_PODLY_REG(PDB0,0)
+#define PDB0_PO1DLY                              PDB_PODLY_REG(PDB0,1)
+#define PDB0_PO2DLY                              PDB_PODLY_REG(PDB0,2)
+
+/* PDB - Register array accessors */
+#define PDB0_C1(index)                           PDB_C1_REG(PDB0,index)
+#define PDB0_S(index)                            PDB_S_REG(PDB0,index)
+#define PDB0_DLY(index,index2)                   PDB_DLY_REG(PDB0,index,index2)
+#define PDB0_INTC(index)                         PDB_INTC_REG(PDB0,index)
+#define PDB0_INT(index)                          PDB_INT_REG(PDB0,index)
+#define PDB0_PODLY(index)                        PDB_PODLY_REG(PDB0,index)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[252];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[4];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base)                        ((base)->MCR)
+#define PIT_LDVAL_REG(base,index)                ((base)->CHANNEL[index].LDVAL)
+#define PIT_LDVAL_COUNT                          4
+#define PIT_CVAL_REG(base,index)                 ((base)->CHANNEL[index].CVAL)
+#define PIT_CVAL_COUNT                           4
+#define PIT_TCTRL_REG(base,index)                ((base)->CHANNEL[index].TCTRL)
+#define PIT_TCTRL_COUNT                          4
+#define PIT_TFLG_REG(base,index)                 ((base)->CHANNEL[index].TFLG)
+#define PIT_TFLG_COUNT                           4
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK                         0x1u
+#define PIT_MCR_FRZ_SHIFT                        0
+#define PIT_MCR_FRZ_WIDTH                        1
+#define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK                        0x2u
+#define PIT_MCR_MDIS_SHIFT                       1
+#define PIT_MCR_MDIS_WIDTH                       1
+#define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT                      0
+#define PIT_LDVAL_TSV_WIDTH                      32
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT                       0
+#define PIT_CVAL_TVL_WIDTH                       32
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK                       0x1u
+#define PIT_TCTRL_TEN_SHIFT                      0
+#define PIT_TCTRL_TEN_WIDTH                      1
+#define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK                       0x2u
+#define PIT_TCTRL_TIE_SHIFT                      1
+#define PIT_TCTRL_TIE_WIDTH                      1
+#define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK                       0x4u
+#define PIT_TCTRL_CHN_SHIFT                      2
+#define PIT_TCTRL_CHN_WIDTH                      1
+#define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK                        0x1u
+#define PIT_TFLG_TIF_SHIFT                       0
+#define PIT_TFLG_TIF_WIDTH                       1
+#define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR                             (PIT)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS                           { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR                                  PIT_MCR_REG(PIT)
+#define PIT_LDVAL0                               PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0                                PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0                               PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0                                PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1                               PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1                                PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1                               PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1                                PIT_TFLG_REG(PIT,1)
+#define PIT_LDVAL2                               PIT_LDVAL_REG(PIT,2)
+#define PIT_CVAL2                                PIT_CVAL_REG(PIT,2)
+#define PIT_TCTRL2                               PIT_TCTRL_REG(PIT,2)
+#define PIT_TFLG2                                PIT_TFLG_REG(PIT,2)
+#define PIT_LDVAL3                               PIT_LDVAL_REG(PIT,3)
+#define PIT_CVAL3                                PIT_CVAL_REG(PIT,3)
+#define PIT_TCTRL3                               PIT_TCTRL_REG(PIT,3)
+#define PIT_TFLG3                                PIT_TFLG_REG(PIT,3)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index)                         PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index)                          PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index)                         PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index)                          PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base)                     ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base)                     ((base)->LVDSC2)
+#define PMC_REGSC_REG(base)                      ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK                     0x3u
+#define PMC_LVDSC1_LVDV_SHIFT                    0
+#define PMC_LVDSC1_LVDV_WIDTH                    2
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT                   4
+#define PMC_LVDSC1_LVDRE_WIDTH                   1
+#define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK                    0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT                   5
+#define PMC_LVDSC1_LVDIE_WIDTH                   1
+#define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK                   0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT                  6
+#define PMC_LVDSC1_LVDACK_WIDTH                  1
+#define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK                     0x80u
+#define PMC_LVDSC1_LVDF_SHIFT                    7
+#define PMC_LVDSC1_LVDF_WIDTH                    1
+#define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK                     0x3u
+#define PMC_LVDSC2_LVWV_SHIFT                    0
+#define PMC_LVDSC2_LVWV_WIDTH                    2
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT                   5
+#define PMC_LVDSC2_LVWIE_WIDTH                   1
+#define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK                   0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT                  6
+#define PMC_LVDSC2_LVWACK_WIDTH                  1
+#define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK                     0x80u
+#define PMC_LVDSC2_LVWF_SHIFT                    7
+#define PMC_LVDSC2_LVWF_WIDTH                    1
+#define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK                      0x1u
+#define PMC_REGSC_BGBE_SHIFT                     0
+#define PMC_REGSC_BGBE_WIDTH                     1
+#define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK                    0x4u
+#define PMC_REGSC_REGONS_SHIFT                   2
+#define PMC_REGSC_REGONS_WIDTH                   1
+#define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK                    0x8u
+#define PMC_REGSC_ACKISO_SHIFT                   3
+#define PMC_REGSC_ACKISO_WIDTH                   1
+#define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK                      0x10u
+#define PMC_REGSC_BGEN_SHIFT                     4
+#define PMC_REGSC_BGEN_WIDTH                     1
+#define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR                             (PMC)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS                           { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { LVD_LVW_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1                               PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2                               PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC                                PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
+  __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
+  __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index)                 ((base)->PCR[index])
+#define PORT_PCR_COUNT                           32
+#define PORT_GPCLR_REG(base)                     ((base)->GPCLR)
+#define PORT_GPCHR_REG(base)                     ((base)->GPCHR)
+#define PORT_ISFR_REG(base)                      ((base)->ISFR)
+#define PORT_DFER_REG(base)                      ((base)->DFER)
+#define PORT_DFCR_REG(base)                      ((base)->DFCR)
+#define PORT_DFWR_REG(base)                      ((base)->DFWR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK                         0x1u
+#define PORT_PCR_PS_SHIFT                        0
+#define PORT_PCR_PS_WIDTH                        1
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK                         0x2u
+#define PORT_PCR_PE_SHIFT                        1
+#define PORT_PCR_PE_WIDTH                        1
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK                        0x4u
+#define PORT_PCR_SRE_SHIFT                       2
+#define PORT_PCR_SRE_WIDTH                       1
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK                        0x10u
+#define PORT_PCR_PFE_SHIFT                       4
+#define PORT_PCR_PFE_WIDTH                       1
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK                        0x20u
+#define PORT_PCR_ODE_SHIFT                       5
+#define PORT_PCR_ODE_WIDTH                       1
+#define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK                        0x40u
+#define PORT_PCR_DSE_SHIFT                       6
+#define PORT_PCR_DSE_WIDTH                       1
+#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK                        0x700u
+#define PORT_PCR_MUX_SHIFT                       8
+#define PORT_PCR_MUX_WIDTH                       3
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK                         0x8000u
+#define PORT_PCR_LK_SHIFT                        15
+#define PORT_PCR_LK_WIDTH                        1
+#define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK                       0xF0000u
+#define PORT_PCR_IRQC_SHIFT                      16
+#define PORT_PCR_IRQC_WIDTH                      4
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        0x1000000u
+#define PORT_PCR_ISF_SHIFT                       24
+#define PORT_PCR_ISF_WIDTH                       1
+#define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT                    0
+#define PORT_GPCLR_GPWD_WIDTH                    16
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT                    16
+#define PORT_GPCLR_GPWE_WIDTH                    16
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT                    0
+#define PORT_GPCHR_GPWD_WIDTH                    16
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT                    16
+#define PORT_GPCHR_GPWE_WIDTH                    16
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT                      0
+#define PORT_ISFR_ISF_WIDTH                      32
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK                       0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT                      0
+#define PORT_DFER_DFE_WIDTH                      32
+#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK                        0x1u
+#define PORT_DFCR_CS_SHIFT                       0
+#define PORT_DFCR_CS_WIDTH                       1
+#define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK                      0x1Fu
+#define PORT_DFWR_FILT_SHIFT                     0
+#define PORT_DFWR_FILT_WIDTH                     5
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR                           (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR                           (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR                           (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR                           (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR                           (PORTE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0                               PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1                               PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2                               PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3                               PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4                               PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5                               PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6                               PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7                               PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8                               PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9                               PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10                              PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11                              PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12                              PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13                              PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14                              PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15                              PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16                              PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17                              PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18                              PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19                              PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20                              PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21                              PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22                              PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23                              PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24                              PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25                              PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26                              PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27                              PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28                              PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29                              PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30                              PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31                              PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR                              PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR                              PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR                               PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0                               PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1                               PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2                               PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3                               PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4                               PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5                               PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6                               PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7                               PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8                               PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9                               PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10                              PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11                              PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12                              PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13                              PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14                              PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15                              PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16                              PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17                              PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18                              PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19                              PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20                              PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21                              PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22                              PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23                              PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24                              PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25                              PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26                              PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27                              PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28                              PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29                              PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30                              PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31                              PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR                              PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR                              PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR                               PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0                               PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1                               PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2                               PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3                               PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4                               PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5                               PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6                               PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7                               PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8                               PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9                               PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10                              PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11                              PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12                              PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13                              PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14                              PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15                              PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16                              PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17                              PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18                              PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19                              PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20                              PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21                              PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22                              PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23                              PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24                              PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25                              PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26                              PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27                              PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28                              PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29                              PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30                              PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31                              PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR                              PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR                              PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR                               PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0                               PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1                               PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2                               PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3                               PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4                               PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5                               PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6                               PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7                               PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8                               PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9                               PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10                              PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11                              PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12                              PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13                              PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14                              PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15                              PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16                              PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17                              PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18                              PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19                              PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20                              PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21                              PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22                              PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23                              PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24                              PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25                              PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26                              PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27                              PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28                              PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29                              PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30                              PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31                              PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR                              PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR                              PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR                               PORT_ISFR_REG(PORTD)
+#define PORTD_DFER                               PORT_DFER_REG(PORTD)
+#define PORTD_DFCR                               PORT_DFCR_REG(PORTD)
+#define PORTD_DFWR                               PORT_DFWR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0                               PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1                               PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2                               PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3                               PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4                               PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5                               PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6                               PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7                               PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8                               PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9                               PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10                              PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11                              PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12                              PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13                              PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14                              PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15                              PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16                              PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17                              PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18                              PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19                              PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20                              PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21                              PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22                              PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23                              PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24                              PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25                              PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26                              PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27                              PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28                              PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29                              PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30                              PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31                              PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR                              PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR                              PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR                               PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index)                         PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index)                         PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index)                         PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index)                         PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index)                         PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+       uint8_t RESERVED_1[1];
+  __I  uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base)                       ((base)->SRS0)
+#define RCM_SRS1_REG(base)                       ((base)->SRS1)
+#define RCM_RPFC_REG(base)                       ((base)->RPFC)
+#define RCM_RPFW_REG(base)                       ((base)->RPFW)
+#define RCM_MR_REG(base)                         ((base)->MR)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK                     0x1u
+#define RCM_SRS0_WAKEUP_SHIFT                    0
+#define RCM_SRS0_WAKEUP_WIDTH                    1
+#define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK                        0x2u
+#define RCM_SRS0_LVD_SHIFT                       1
+#define RCM_SRS0_LVD_WIDTH                       1
+#define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK                        0x4u
+#define RCM_SRS0_LOC_SHIFT                       2
+#define RCM_SRS0_LOC_WIDTH                       1
+#define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOC_SHIFT))&RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK                        0x8u
+#define RCM_SRS0_LOL_SHIFT                       3
+#define RCM_SRS0_LOL_WIDTH                       1
+#define RCM_SRS0_LOL(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOL_SHIFT))&RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK                       0x20u
+#define RCM_SRS0_WDOG_SHIFT                      5
+#define RCM_SRS0_WDOG_WIDTH                      1
+#define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK                        0x40u
+#define RCM_SRS0_PIN_SHIFT                       6
+#define RCM_SRS0_PIN_WIDTH                       1
+#define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK                        0x80u
+#define RCM_SRS0_POR_SHIFT                       7
+#define RCM_SRS0_POR_WIDTH                       1
+#define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK                       0x1u
+#define RCM_SRS1_JTAG_SHIFT                      0
+#define RCM_SRS1_JTAG_WIDTH                      1
+#define RCM_SRS1_JTAG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_JTAG_SHIFT))&RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK                     0x2u
+#define RCM_SRS1_LOCKUP_SHIFT                    1
+#define RCM_SRS1_LOCKUP_WIDTH                    1
+#define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK                         0x4u
+#define RCM_SRS1_SW_SHIFT                        2
+#define RCM_SRS1_SW_WIDTH                        1
+#define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK                     0x8u
+#define RCM_SRS1_MDM_AP_SHIFT                    3
+#define RCM_SRS1_MDM_AP_WIDTH                    1
+#define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK                       0x10u
+#define RCM_SRS1_EZPT_SHIFT                      4
+#define RCM_SRS1_EZPT_WIDTH                      1
+#define RCM_SRS1_EZPT(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_EZPT_SHIFT))&RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK                    0x20u
+#define RCM_SRS1_SACKERR_SHIFT                   5
+#define RCM_SRS1_SACKERR_WIDTH                   1
+#define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 0
+#define RCM_RPFC_RSTFLTSRW_WIDTH                 2
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK                   0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT                  2
+#define RCM_RPFC_RSTFLTSS_WIDTH                  1
+#define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 0
+#define RCM_RPFW_RSTFLTSEL_WIDTH                 5
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK                       0x2u
+#define RCM_MR_EZP_MS_SHIFT                      1
+#define RCM_MR_EZP_MS_WIDTH                      1
+#define RCM_MR_EZP_MS(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_MR_EZP_MS_SHIFT))&RCM_MR_EZP_MS_MASK)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR                             (RCM)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS                           { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS                            { RCM }
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0                                 RCM_SRS0_REG(RCM)
+#define RCM_SRS1                                 RCM_SRS1_REG(RCM)
+#define RCM_RPFC                                 RCM_RPFC_REG(RCM)
+#define RCM_RPFW                                 RCM_RPFW_REG(RCM)
+#define RCM_MR                                   RCM_MR_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index)                ((base)->REG[index])
+#define RFSYS_REG_COUNT                          8
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK                        0xFFu
+#define RFSYS_REG_LL_SHIFT                       0
+#define RFSYS_REG_LL_WIDTH                       8
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        0xFF00u
+#define RFSYS_REG_LH_SHIFT                       8
+#define RFSYS_REG_LH_WIDTH                       8
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        0xFF0000u
+#define RFSYS_REG_HL_SHIFT                       16
+#define RFSYS_REG_HL_WIDTH                       8
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        0xFF000000u
+#define RFSYS_REG_HH_SHIFT                       24
+#define RFSYS_REG_HH_WIDTH                       8
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR                           (RFSYS)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS                          { RFSYS }
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0                               RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1                               RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2                               RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3                               RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4                               RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5                               RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6                               RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7                               RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index)                         RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type, *RFVBAT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register accessors */
+#define RFVBAT_REG_REG(base,index)               ((base)->REG[index])
+#define RFVBAT_REG_COUNT                         8
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK                       0xFFu
+#define RFVBAT_REG_LL_SHIFT                      0
+#define RFVBAT_REG_LL_WIDTH                      8
+#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK                       0xFF00u
+#define RFVBAT_REG_LH_SHIFT                      8
+#define RFVBAT_REG_LH_WIDTH                      8
+#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK                       0xFF0000u
+#define RFVBAT_REG_HL_SHIFT                      16
+#define RFVBAT_REG_HL_WIDTH                      8
+#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK                       0xFF000000u
+#define RFVBAT_REG_HH_SHIFT                      24
+#define RFVBAT_REG_HH_WIDTH                      8
+#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE                              (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
+#define RFVBAT_BASE_PTR                          (RFVBAT)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS                        { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS                         { RFVBAT }
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register instance definitions */
+/* RFVBAT */
+#define RFVBAT_REG0                              RFVBAT_REG_REG(RFVBAT,0)
+#define RFVBAT_REG1                              RFVBAT_REG_REG(RFVBAT,1)
+#define RFVBAT_REG2                              RFVBAT_REG_REG(RFVBAT,2)
+#define RFVBAT_REG3                              RFVBAT_REG_REG(RFVBAT,3)
+#define RFVBAT_REG4                              RFVBAT_REG_REG(RFVBAT,4)
+#define RFVBAT_REG5                              RFVBAT_REG_REG(RFVBAT,5)
+#define RFVBAT_REG6                              RFVBAT_REG_REG(RFVBAT,6)
+#define RFVBAT_REG7                              RFVBAT_REG_REG(RFVBAT,7)
+
+/* RFVBAT - Register array accessors */
+#define RFVBAT_REG(index)                        RFVBAT_REG_REG(RFVBAT,index)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< RNGA Control Register, offset: 0x0 */
+  __I  uint32_t SR;                                /**< RNGA Status Register, offset: 0x4 */
+  __O  uint32_t ER;                                /**< RNGA Entropy Register, offset: 0x8 */
+  __I  uint32_t OR;                                /**< RNGA Output Register, offset: 0xC */
+} RNG_Type, *RNG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register accessors */
+#define RNG_CR_REG(base)                         ((base)->CR)
+#define RNG_SR_REG(base)                         ((base)->SR)
+#define RNG_ER_REG(base)                         ((base)->ER)
+#define RNG_OR_REG(base)                         ((base)->OR)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define RNG_CR_GO_MASK                           0x1u
+#define RNG_CR_GO_SHIFT                          0
+#define RNG_CR_GO_WIDTH                          1
+#define RNG_CR_GO(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_GO_SHIFT))&RNG_CR_GO_MASK)
+#define RNG_CR_HA_MASK                           0x2u
+#define RNG_CR_HA_SHIFT                          1
+#define RNG_CR_HA_WIDTH                          1
+#define RNG_CR_HA(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_HA_SHIFT))&RNG_CR_HA_MASK)
+#define RNG_CR_INTM_MASK                         0x4u
+#define RNG_CR_INTM_SHIFT                        2
+#define RNG_CR_INTM_WIDTH                        1
+#define RNG_CR_INTM(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_INTM_SHIFT))&RNG_CR_INTM_MASK)
+#define RNG_CR_CLRI_MASK                         0x8u
+#define RNG_CR_CLRI_SHIFT                        3
+#define RNG_CR_CLRI_WIDTH                        1
+#define RNG_CR_CLRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_CLRI_SHIFT))&RNG_CR_CLRI_MASK)
+#define RNG_CR_SLP_MASK                          0x10u
+#define RNG_CR_SLP_SHIFT                         4
+#define RNG_CR_SLP_WIDTH                         1
+#define RNG_CR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_CR_SLP_SHIFT))&RNG_CR_SLP_MASK)
+/* SR Bit Fields */
+#define RNG_SR_SECV_MASK                         0x1u
+#define RNG_SR_SECV_SHIFT                        0
+#define RNG_SR_SECV_WIDTH                        1
+#define RNG_SR_SECV(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_SECV_SHIFT))&RNG_SR_SECV_MASK)
+#define RNG_SR_LRS_MASK                          0x2u
+#define RNG_SR_LRS_SHIFT                         1
+#define RNG_SR_LRS_WIDTH                         1
+#define RNG_SR_LRS(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_LRS_SHIFT))&RNG_SR_LRS_MASK)
+#define RNG_SR_ORU_MASK                          0x4u
+#define RNG_SR_ORU_SHIFT                         2
+#define RNG_SR_ORU_WIDTH                         1
+#define RNG_SR_ORU(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_ORU_SHIFT))&RNG_SR_ORU_MASK)
+#define RNG_SR_ERRI_MASK                         0x8u
+#define RNG_SR_ERRI_SHIFT                        3
+#define RNG_SR_ERRI_WIDTH                        1
+#define RNG_SR_ERRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_ERRI_SHIFT))&RNG_SR_ERRI_MASK)
+#define RNG_SR_SLP_MASK                          0x10u
+#define RNG_SR_SLP_SHIFT                         4
+#define RNG_SR_SLP_WIDTH                         1
+#define RNG_SR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_SLP_SHIFT))&RNG_SR_SLP_MASK)
+#define RNG_SR_OREG_LVL_MASK                     0xFF00u
+#define RNG_SR_OREG_LVL_SHIFT                    8
+#define RNG_SR_OREG_LVL_WIDTH                    8
+#define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK                    0xFF0000u
+#define RNG_SR_OREG_SIZE_SHIFT                   16
+#define RNG_SR_OREG_SIZE_WIDTH                   8
+#define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
+/* ER Bit Fields */
+#define RNG_ER_EXT_ENT_MASK                      0xFFFFFFFFu
+#define RNG_ER_EXT_ENT_SHIFT                     0
+#define RNG_ER_EXT_ENT_WIDTH                     32
+#define RNG_ER_EXT_ENT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
+/* OR Bit Fields */
+#define RNG_OR_RANDOUT_MASK                      0xFFFFFFFFu
+#define RNG_OR_RANDOUT_SHIFT                     0
+#define RNG_OR_RANDOUT_WIDTH                     32
+#define RNG_OR_RANDOUT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE                                 (0x40029000u)
+/** Peripheral RNG base pointer */
+#define RNG                                      ((RNG_Type *)RNG_BASE)
+#define RNG_BASE_PTR                             (RNG)
+/** Array initializer of RNG peripheral base addresses */
+#define RNG_BASE_ADDRS                           { RNG_BASE }
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASE_PTRS                            { RNG }
+/** Interrupt vectors for the RNG peripheral type */
+#define RNG_IRQS                                 { RNG_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register instance definitions */
+/* RNG */
+#define RNG_CR                                   RNG_CR_REG(RNG)
+#define RNG_SR                                   RNG_SR_REG(RNG)
+#define RNG_ER                                   RNG_ER_REG(RNG)
+#define RNG_OR                                   RNG_OR_REG(RNG)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+       uint8_t RESERVED_0[2016];
+  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base)                        ((base)->TSR)
+#define RTC_TPR_REG(base)                        ((base)->TPR)
+#define RTC_TAR_REG(base)                        ((base)->TAR)
+#define RTC_TCR_REG(base)                        ((base)->TCR)
+#define RTC_CR_REG(base)                         ((base)->CR)
+#define RTC_SR_REG(base)                         ((base)->SR)
+#define RTC_LR_REG(base)                         ((base)->LR)
+#define RTC_IER_REG(base)                        ((base)->IER)
+#define RTC_WAR_REG(base)                        ((base)->WAR)
+#define RTC_RAR_REG(base)                        ((base)->RAR)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT                        0
+#define RTC_TSR_TSR_WIDTH                        32
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK                         0xFFFFu
+#define RTC_TPR_TPR_SHIFT                        0
+#define RTC_TPR_TPR_WIDTH                        16
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT                        0
+#define RTC_TAR_TAR_WIDTH                        32
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK                         0xFFu
+#define RTC_TCR_TCR_SHIFT                        0
+#define RTC_TCR_TCR_WIDTH                        8
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         0xFF00u
+#define RTC_TCR_CIR_SHIFT                        8
+#define RTC_TCR_CIR_WIDTH                        8
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         0xFF0000u
+#define RTC_TCR_TCV_SHIFT                        16
+#define RTC_TCR_TCV_WIDTH                        8
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         0xFF000000u
+#define RTC_TCR_CIC_SHIFT                        24
+#define RTC_TCR_CIC_WIDTH                        8
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK                          0x1u
+#define RTC_CR_SWR_SHIFT                         0
+#define RTC_CR_SWR_WIDTH                         1
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK                          0x2u
+#define RTC_CR_WPE_SHIFT                         1
+#define RTC_CR_WPE_WIDTH                         1
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK                          0x4u
+#define RTC_CR_SUP_SHIFT                         2
+#define RTC_CR_SUP_WIDTH                         1
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK                           0x8u
+#define RTC_CR_UM_SHIFT                          3
+#define RTC_CR_UM_WIDTH                          1
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK                          0x10u
+#define RTC_CR_WPS_SHIFT                         4
+#define RTC_CR_WPS_WIDTH                         1
+#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK                         0x100u
+#define RTC_CR_OSCE_SHIFT                        8
+#define RTC_CR_OSCE_WIDTH                        1
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK                         0x200u
+#define RTC_CR_CLKO_SHIFT                        9
+#define RTC_CR_CLKO_WIDTH                        1
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK                        0x400u
+#define RTC_CR_SC16P_SHIFT                       10
+#define RTC_CR_SC16P_WIDTH                       1
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK                         0x800u
+#define RTC_CR_SC8P_SHIFT                        11
+#define RTC_CR_SC8P_WIDTH                        1
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK                         0x1000u
+#define RTC_CR_SC4P_SHIFT                        12
+#define RTC_CR_SC4P_WIDTH                        1
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK                         0x2000u
+#define RTC_CR_SC2P_SHIFT                        13
+#define RTC_CR_SC2P_WIDTH                        1
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK                          0x1u
+#define RTC_SR_TIF_SHIFT                         0
+#define RTC_SR_TIF_WIDTH                         1
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK                          0x2u
+#define RTC_SR_TOF_SHIFT                         1
+#define RTC_SR_TOF_WIDTH                         1
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK                          0x4u
+#define RTC_SR_TAF_SHIFT                         2
+#define RTC_SR_TAF_WIDTH                         1
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK                          0x10u
+#define RTC_SR_TCE_SHIFT                         4
+#define RTC_SR_TCE_WIDTH                         1
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK                          0x8u
+#define RTC_LR_TCL_SHIFT                         3
+#define RTC_LR_TCL_WIDTH                         1
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK                          0x10u
+#define RTC_LR_CRL_SHIFT                         4
+#define RTC_LR_CRL_WIDTH                         1
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK                          0x20u
+#define RTC_LR_SRL_SHIFT                         5
+#define RTC_LR_SRL_WIDTH                         1
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK                          0x40u
+#define RTC_LR_LRL_SHIFT                         6
+#define RTC_LR_LRL_WIDTH                         1
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK                        0x1u
+#define RTC_IER_TIIE_SHIFT                       0
+#define RTC_IER_TIIE_WIDTH                       1
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK                        0x2u
+#define RTC_IER_TOIE_SHIFT                       1
+#define RTC_IER_TOIE_WIDTH                       1
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK                        0x4u
+#define RTC_IER_TAIE_SHIFT                       2
+#define RTC_IER_TAIE_WIDTH                       1
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK                        0x10u
+#define RTC_IER_TSIE_SHIFT                       4
+#define RTC_IER_TSIE_WIDTH                       1
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK                        0x80u
+#define RTC_IER_WPON_SHIFT                       7
+#define RTC_IER_WPON_WIDTH                       1
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK                        0x1u
+#define RTC_WAR_TSRW_SHIFT                       0
+#define RTC_WAR_TSRW_WIDTH                       1
+#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TSRW_SHIFT))&RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK                        0x2u
+#define RTC_WAR_TPRW_SHIFT                       1
+#define RTC_WAR_TPRW_WIDTH                       1
+#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TPRW_SHIFT))&RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK                        0x4u
+#define RTC_WAR_TARW_SHIFT                       2
+#define RTC_WAR_TARW_WIDTH                       1
+#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TARW_SHIFT))&RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK                        0x8u
+#define RTC_WAR_TCRW_SHIFT                       3
+#define RTC_WAR_TCRW_WIDTH                       1
+#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TCRW_SHIFT))&RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK                         0x10u
+#define RTC_WAR_CRW_SHIFT                        4
+#define RTC_WAR_CRW_WIDTH                        1
+#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_CRW_SHIFT))&RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK                         0x20u
+#define RTC_WAR_SRW_SHIFT                        5
+#define RTC_WAR_SRW_WIDTH                        1
+#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_SRW_SHIFT))&RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK                         0x40u
+#define RTC_WAR_LRW_SHIFT                        6
+#define RTC_WAR_LRW_WIDTH                        1
+#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_LRW_SHIFT))&RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK                        0x80u
+#define RTC_WAR_IERW_SHIFT                       7
+#define RTC_WAR_IERW_WIDTH                       1
+#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_IERW_SHIFT))&RTC_WAR_IERW_MASK)
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK                        0x1u
+#define RTC_RAR_TSRR_SHIFT                       0
+#define RTC_RAR_TSRR_WIDTH                       1
+#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TSRR_SHIFT))&RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK                        0x2u
+#define RTC_RAR_TPRR_SHIFT                       1
+#define RTC_RAR_TPRR_WIDTH                       1
+#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TPRR_SHIFT))&RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK                        0x4u
+#define RTC_RAR_TARR_SHIFT                       2
+#define RTC_RAR_TARR_WIDTH                       1
+#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TARR_SHIFT))&RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK                        0x8u
+#define RTC_RAR_TCRR_SHIFT                       3
+#define RTC_RAR_TCRR_WIDTH                       1
+#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TCRR_SHIFT))&RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK                         0x10u
+#define RTC_RAR_CRR_SHIFT                        4
+#define RTC_RAR_CRR_WIDTH                        1
+#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_CRR_SHIFT))&RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK                         0x20u
+#define RTC_RAR_SRR_SHIFT                        5
+#define RTC_RAR_SRR_WIDTH                        1
+#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_SRR_SHIFT))&RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK                         0x40u
+#define RTC_RAR_LRR_SHIFT                        6
+#define RTC_RAR_LRR_WIDTH                        1
+#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_LRR_SHIFT))&RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK                        0x80u
+#define RTC_RAR_IERR_SHIFT                       7
+#define RTC_RAR_IERR_WIDTH                       1
+#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_IERR_SHIFT))&RTC_RAR_IERR_MASK)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR                             (RTC)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR                                  RTC_TSR_REG(RTC)
+#define RTC_TPR                                  RTC_TPR_REG(RTC)
+#define RTC_TAR                                  RTC_TAR_REG(RTC)
+#define RTC_TCR                                  RTC_TCR_REG(RTC)
+#define RTC_CR                                   RTC_CR_REG(RTC)
+#define RTC_SR                                   RTC_SR_REG(RTC)
+#define RTC_LR                                   RTC_LR_REG(RTC)
+#define RTC_IER                                  RTC_IER_REG(RTC)
+#define RTC_WAR                                  RTC_WAR_REG(RTC)
+#define RTC_RAR                                  RTC_RAR_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
+ * @{
+ */
+
+/** SDHC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DSADDR;                            /**< DMA System Address register, offset: 0x0 */
+  __IO uint32_t BLKATTR;                           /**< Block Attributes register, offset: 0x4 */
+  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x8 */
+  __IO uint32_t XFERTYP;                           /**< Transfer Type register, offset: 0xC */
+  __I  uint32_t CMDRSP[4];                         /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t DATPORT;                           /**< Buffer Data Port register, offset: 0x20 */
+  __I  uint32_t PRSSTAT;                           /**< Present State register, offset: 0x24 */
+  __IO uint32_t PROCTL;                            /**< Protocol Control register, offset: 0x28 */
+  __IO uint32_t SYSCTL;                            /**< System Control register, offset: 0x2C */
+  __IO uint32_t IRQSTAT;                           /**< Interrupt Status register, offset: 0x30 */
+  __IO uint32_t IRQSTATEN;                         /**< Interrupt Status Enable register, offset: 0x34 */
+  __IO uint32_t IRQSIGEN;                          /**< Interrupt Signal Enable register, offset: 0x38 */
+  __I  uint32_t AC12ERR;                           /**< Auto CMD12 Error Status Register, offset: 0x3C */
+  __I  uint32_t HTCAPBLT;                          /**< Host Controller Capabilities, offset: 0x40 */
+  __IO uint32_t WML;                               /**< Watermark Level Register, offset: 0x44 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t FEVT;                              /**< Force Event register, offset: 0x50 */
+  __I  uint32_t ADMAES;                            /**< ADMA Error Status register, offset: 0x54 */
+  __IO uint32_t ADSADDR;                           /**< ADMA System Addressregister, offset: 0x58 */
+       uint8_t RESERVED_1[100];
+  __IO uint32_t VENDOR;                            /**< Vendor Specific register, offset: 0xC0 */
+  __IO uint32_t MMCBOOT;                           /**< MMC Boot register, offset: 0xC4 */
+       uint8_t RESERVED_2[52];
+  __I  uint32_t HOSTVER;                           /**< Host Controller Version, offset: 0xFC */
+} SDHC_Type, *SDHC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register accessors */
+#define SDHC_DSADDR_REG(base)                    ((base)->DSADDR)
+#define SDHC_BLKATTR_REG(base)                   ((base)->BLKATTR)
+#define SDHC_CMDARG_REG(base)                    ((base)->CMDARG)
+#define SDHC_XFERTYP_REG(base)                   ((base)->XFERTYP)
+#define SDHC_CMDRSP_REG(base,index)              ((base)->CMDRSP[index])
+#define SDHC_CMDRSP_COUNT                        4
+#define SDHC_DATPORT_REG(base)                   ((base)->DATPORT)
+#define SDHC_PRSSTAT_REG(base)                   ((base)->PRSSTAT)
+#define SDHC_PROCTL_REG(base)                    ((base)->PROCTL)
+#define SDHC_SYSCTL_REG(base)                    ((base)->SYSCTL)
+#define SDHC_IRQSTAT_REG(base)                   ((base)->IRQSTAT)
+#define SDHC_IRQSTATEN_REG(base)                 ((base)->IRQSTATEN)
+#define SDHC_IRQSIGEN_REG(base)                  ((base)->IRQSIGEN)
+#define SDHC_AC12ERR_REG(base)                   ((base)->AC12ERR)
+#define SDHC_HTCAPBLT_REG(base)                  ((base)->HTCAPBLT)
+#define SDHC_WML_REG(base)                       ((base)->WML)
+#define SDHC_FEVT_REG(base)                      ((base)->FEVT)
+#define SDHC_ADMAES_REG(base)                    ((base)->ADMAES)
+#define SDHC_ADSADDR_REG(base)                   ((base)->ADSADDR)
+#define SDHC_VENDOR_REG(base)                    ((base)->VENDOR)
+#define SDHC_MMCBOOT_REG(base)                   ((base)->MMCBOOT)
+#define SDHC_HOSTVER_REG(base)                   ((base)->HOSTVER)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/* DSADDR Bit Fields */
+#define SDHC_DSADDR_DSADDR_MASK                  0xFFFFFFFCu
+#define SDHC_DSADDR_DSADDR_SHIFT                 2
+#define SDHC_DSADDR_DSADDR_WIDTH                 30
+#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
+/* BLKATTR Bit Fields */
+#define SDHC_BLKATTR_BLKSIZE_MASK                0x1FFFu
+#define SDHC_BLKATTR_BLKSIZE_SHIFT               0
+#define SDHC_BLKATTR_BLKSIZE_WIDTH               13
+#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK                 0xFFFF0000u
+#define SDHC_BLKATTR_BLKCNT_SHIFT                16
+#define SDHC_BLKATTR_BLKCNT_WIDTH                16
+#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
+/* CMDARG Bit Fields */
+#define SDHC_CMDARG_CMDARG_MASK                  0xFFFFFFFFu
+#define SDHC_CMDARG_CMDARG_SHIFT                 0
+#define SDHC_CMDARG_CMDARG_WIDTH                 32
+#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
+/* XFERTYP Bit Fields */
+#define SDHC_XFERTYP_DMAEN_MASK                  0x1u
+#define SDHC_XFERTYP_DMAEN_SHIFT                 0
+#define SDHC_XFERTYP_DMAEN_WIDTH                 1
+#define SDHC_XFERTYP_DMAEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DMAEN_SHIFT))&SDHC_XFERTYP_DMAEN_MASK)
+#define SDHC_XFERTYP_BCEN_MASK                   0x2u
+#define SDHC_XFERTYP_BCEN_SHIFT                  1
+#define SDHC_XFERTYP_BCEN_WIDTH                  1
+#define SDHC_XFERTYP_BCEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_BCEN_SHIFT))&SDHC_XFERTYP_BCEN_MASK)
+#define SDHC_XFERTYP_AC12EN_MASK                 0x4u
+#define SDHC_XFERTYP_AC12EN_SHIFT                2
+#define SDHC_XFERTYP_AC12EN_WIDTH                1
+#define SDHC_XFERTYP_AC12EN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_AC12EN_SHIFT))&SDHC_XFERTYP_AC12EN_MASK)
+#define SDHC_XFERTYP_DTDSEL_MASK                 0x10u
+#define SDHC_XFERTYP_DTDSEL_SHIFT                4
+#define SDHC_XFERTYP_DTDSEL_WIDTH                1
+#define SDHC_XFERTYP_DTDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DTDSEL_SHIFT))&SDHC_XFERTYP_DTDSEL_MASK)
+#define SDHC_XFERTYP_MSBSEL_MASK                 0x20u
+#define SDHC_XFERTYP_MSBSEL_SHIFT                5
+#define SDHC_XFERTYP_MSBSEL_WIDTH                1
+#define SDHC_XFERTYP_MSBSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_MSBSEL_SHIFT))&SDHC_XFERTYP_MSBSEL_MASK)
+#define SDHC_XFERTYP_RSPTYP_MASK                 0x30000u
+#define SDHC_XFERTYP_RSPTYP_SHIFT                16
+#define SDHC_XFERTYP_RSPTYP_WIDTH                2
+#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK                  0x80000u
+#define SDHC_XFERTYP_CCCEN_SHIFT                 19
+#define SDHC_XFERTYP_CCCEN_WIDTH                 1
+#define SDHC_XFERTYP_CCCEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CCCEN_SHIFT))&SDHC_XFERTYP_CCCEN_MASK)
+#define SDHC_XFERTYP_CICEN_MASK                  0x100000u
+#define SDHC_XFERTYP_CICEN_SHIFT                 20
+#define SDHC_XFERTYP_CICEN_WIDTH                 1
+#define SDHC_XFERTYP_CICEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CICEN_SHIFT))&SDHC_XFERTYP_CICEN_MASK)
+#define SDHC_XFERTYP_DPSEL_MASK                  0x200000u
+#define SDHC_XFERTYP_DPSEL_SHIFT                 21
+#define SDHC_XFERTYP_DPSEL_WIDTH                 1
+#define SDHC_XFERTYP_DPSEL(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DPSEL_SHIFT))&SDHC_XFERTYP_DPSEL_MASK)
+#define SDHC_XFERTYP_CMDTYP_MASK                 0xC00000u
+#define SDHC_XFERTYP_CMDTYP_SHIFT                22
+#define SDHC_XFERTYP_CMDTYP_WIDTH                2
+#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK                 0x3F000000u
+#define SDHC_XFERTYP_CMDINX_SHIFT                24
+#define SDHC_XFERTYP_CMDINX_WIDTH                6
+#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
+/* CMDRSP Bit Fields */
+#define SDHC_CMDRSP_CMDRSP0_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP0_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP0_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP1_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP1_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP2_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP2_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP3_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP3_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
+/* DATPORT Bit Fields */
+#define SDHC_DATPORT_DATCONT_MASK                0xFFFFFFFFu
+#define SDHC_DATPORT_DATCONT_SHIFT               0
+#define SDHC_DATPORT_DATCONT_WIDTH               32
+#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
+/* PRSSTAT Bit Fields */
+#define SDHC_PRSSTAT_CIHB_MASK                   0x1u
+#define SDHC_PRSSTAT_CIHB_SHIFT                  0
+#define SDHC_PRSSTAT_CIHB_WIDTH                  1
+#define SDHC_PRSSTAT_CIHB(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CIHB_SHIFT))&SDHC_PRSSTAT_CIHB_MASK)
+#define SDHC_PRSSTAT_CDIHB_MASK                  0x2u
+#define SDHC_PRSSTAT_CDIHB_SHIFT                 1
+#define SDHC_PRSSTAT_CDIHB_WIDTH                 1
+#define SDHC_PRSSTAT_CDIHB(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CDIHB_SHIFT))&SDHC_PRSSTAT_CDIHB_MASK)
+#define SDHC_PRSSTAT_DLA_MASK                    0x4u
+#define SDHC_PRSSTAT_DLA_SHIFT                   2
+#define SDHC_PRSSTAT_DLA_WIDTH                   1
+#define SDHC_PRSSTAT_DLA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLA_SHIFT))&SDHC_PRSSTAT_DLA_MASK)
+#define SDHC_PRSSTAT_SDSTB_MASK                  0x8u
+#define SDHC_PRSSTAT_SDSTB_SHIFT                 3
+#define SDHC_PRSSTAT_SDSTB_WIDTH                 1
+#define SDHC_PRSSTAT_SDSTB(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDSTB_SHIFT))&SDHC_PRSSTAT_SDSTB_MASK)
+#define SDHC_PRSSTAT_IPGOFF_MASK                 0x10u
+#define SDHC_PRSSTAT_IPGOFF_SHIFT                4
+#define SDHC_PRSSTAT_IPGOFF_WIDTH                1
+#define SDHC_PRSSTAT_IPGOFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_IPGOFF_SHIFT))&SDHC_PRSSTAT_IPGOFF_MASK)
+#define SDHC_PRSSTAT_HCKOFF_MASK                 0x20u
+#define SDHC_PRSSTAT_HCKOFF_SHIFT                5
+#define SDHC_PRSSTAT_HCKOFF_WIDTH                1
+#define SDHC_PRSSTAT_HCKOFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_HCKOFF_SHIFT))&SDHC_PRSSTAT_HCKOFF_MASK)
+#define SDHC_PRSSTAT_PEROFF_MASK                 0x40u
+#define SDHC_PRSSTAT_PEROFF_SHIFT                6
+#define SDHC_PRSSTAT_PEROFF_WIDTH                1
+#define SDHC_PRSSTAT_PEROFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_PEROFF_SHIFT))&SDHC_PRSSTAT_PEROFF_MASK)
+#define SDHC_PRSSTAT_SDOFF_MASK                  0x80u
+#define SDHC_PRSSTAT_SDOFF_SHIFT                 7
+#define SDHC_PRSSTAT_SDOFF_WIDTH                 1
+#define SDHC_PRSSTAT_SDOFF(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDOFF_SHIFT))&SDHC_PRSSTAT_SDOFF_MASK)
+#define SDHC_PRSSTAT_WTA_MASK                    0x100u
+#define SDHC_PRSSTAT_WTA_SHIFT                   8
+#define SDHC_PRSSTAT_WTA_WIDTH                   1
+#define SDHC_PRSSTAT_WTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_WTA_SHIFT))&SDHC_PRSSTAT_WTA_MASK)
+#define SDHC_PRSSTAT_RTA_MASK                    0x200u
+#define SDHC_PRSSTAT_RTA_SHIFT                   9
+#define SDHC_PRSSTAT_RTA_WIDTH                   1
+#define SDHC_PRSSTAT_RTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_RTA_SHIFT))&SDHC_PRSSTAT_RTA_MASK)
+#define SDHC_PRSSTAT_BWEN_MASK                   0x400u
+#define SDHC_PRSSTAT_BWEN_SHIFT                  10
+#define SDHC_PRSSTAT_BWEN_WIDTH                  1
+#define SDHC_PRSSTAT_BWEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BWEN_SHIFT))&SDHC_PRSSTAT_BWEN_MASK)
+#define SDHC_PRSSTAT_BREN_MASK                   0x800u
+#define SDHC_PRSSTAT_BREN_SHIFT                  11
+#define SDHC_PRSSTAT_BREN_WIDTH                  1
+#define SDHC_PRSSTAT_BREN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BREN_SHIFT))&SDHC_PRSSTAT_BREN_MASK)
+#define SDHC_PRSSTAT_CINS_MASK                   0x10000u
+#define SDHC_PRSSTAT_CINS_SHIFT                  16
+#define SDHC_PRSSTAT_CINS_WIDTH                  1
+#define SDHC_PRSSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CINS_SHIFT))&SDHC_PRSSTAT_CINS_MASK)
+#define SDHC_PRSSTAT_CLSL_MASK                   0x800000u
+#define SDHC_PRSSTAT_CLSL_SHIFT                  23
+#define SDHC_PRSSTAT_CLSL_WIDTH                  1
+#define SDHC_PRSSTAT_CLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CLSL_SHIFT))&SDHC_PRSSTAT_CLSL_MASK)
+#define SDHC_PRSSTAT_DLSL_MASK                   0xFF000000u
+#define SDHC_PRSSTAT_DLSL_SHIFT                  24
+#define SDHC_PRSSTAT_DLSL_WIDTH                  8
+#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
+/* PROCTL Bit Fields */
+#define SDHC_PROCTL_LCTL_MASK                    0x1u
+#define SDHC_PROCTL_LCTL_SHIFT                   0
+#define SDHC_PROCTL_LCTL_WIDTH                   1
+#define SDHC_PROCTL_LCTL(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_LCTL_SHIFT))&SDHC_PROCTL_LCTL_MASK)
+#define SDHC_PROCTL_DTW_MASK                     0x6u
+#define SDHC_PROCTL_DTW_SHIFT                    1
+#define SDHC_PROCTL_DTW_WIDTH                    2
+#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK                    0x8u
+#define SDHC_PROCTL_D3CD_SHIFT                   3
+#define SDHC_PROCTL_D3CD_WIDTH                   1
+#define SDHC_PROCTL_D3CD(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_D3CD_SHIFT))&SDHC_PROCTL_D3CD_MASK)
+#define SDHC_PROCTL_EMODE_MASK                   0x30u
+#define SDHC_PROCTL_EMODE_SHIFT                  4
+#define SDHC_PROCTL_EMODE_WIDTH                  2
+#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK                    0x40u
+#define SDHC_PROCTL_CDTL_SHIFT                   6
+#define SDHC_PROCTL_CDTL_WIDTH                   1
+#define SDHC_PROCTL_CDTL(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDTL_SHIFT))&SDHC_PROCTL_CDTL_MASK)
+#define SDHC_PROCTL_CDSS_MASK                    0x80u
+#define SDHC_PROCTL_CDSS_SHIFT                   7
+#define SDHC_PROCTL_CDSS_WIDTH                   1
+#define SDHC_PROCTL_CDSS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDSS_SHIFT))&SDHC_PROCTL_CDSS_MASK)
+#define SDHC_PROCTL_DMAS_MASK                    0x300u
+#define SDHC_PROCTL_DMAS_SHIFT                   8
+#define SDHC_PROCTL_DMAS_WIDTH                   2
+#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK                 0x10000u
+#define SDHC_PROCTL_SABGREQ_SHIFT                16
+#define SDHC_PROCTL_SABGREQ_WIDTH                1
+#define SDHC_PROCTL_SABGREQ(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_SABGREQ_SHIFT))&SDHC_PROCTL_SABGREQ_MASK)
+#define SDHC_PROCTL_CREQ_MASK                    0x20000u
+#define SDHC_PROCTL_CREQ_SHIFT                   17
+#define SDHC_PROCTL_CREQ_WIDTH                   1
+#define SDHC_PROCTL_CREQ(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CREQ_SHIFT))&SDHC_PROCTL_CREQ_MASK)
+#define SDHC_PROCTL_RWCTL_MASK                   0x40000u
+#define SDHC_PROCTL_RWCTL_SHIFT                  18
+#define SDHC_PROCTL_RWCTL_WIDTH                  1
+#define SDHC_PROCTL_RWCTL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_RWCTL_SHIFT))&SDHC_PROCTL_RWCTL_MASK)
+#define SDHC_PROCTL_IABG_MASK                    0x80000u
+#define SDHC_PROCTL_IABG_SHIFT                   19
+#define SDHC_PROCTL_IABG_WIDTH                   1
+#define SDHC_PROCTL_IABG(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_IABG_SHIFT))&SDHC_PROCTL_IABG_MASK)
+#define SDHC_PROCTL_WECINT_MASK                  0x1000000u
+#define SDHC_PROCTL_WECINT_SHIFT                 24
+#define SDHC_PROCTL_WECINT_WIDTH                 1
+#define SDHC_PROCTL_WECINT(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINT_SHIFT))&SDHC_PROCTL_WECINT_MASK)
+#define SDHC_PROCTL_WECINS_MASK                  0x2000000u
+#define SDHC_PROCTL_WECINS_SHIFT                 25
+#define SDHC_PROCTL_WECINS_WIDTH                 1
+#define SDHC_PROCTL_WECINS(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINS_SHIFT))&SDHC_PROCTL_WECINS_MASK)
+#define SDHC_PROCTL_WECRM_MASK                   0x4000000u
+#define SDHC_PROCTL_WECRM_SHIFT                  26
+#define SDHC_PROCTL_WECRM_WIDTH                  1
+#define SDHC_PROCTL_WECRM(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECRM_SHIFT))&SDHC_PROCTL_WECRM_MASK)
+/* SYSCTL Bit Fields */
+#define SDHC_SYSCTL_IPGEN_MASK                   0x1u
+#define SDHC_SYSCTL_IPGEN_SHIFT                  0
+#define SDHC_SYSCTL_IPGEN_WIDTH                  1
+#define SDHC_SYSCTL_IPGEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_IPGEN_SHIFT))&SDHC_SYSCTL_IPGEN_MASK)
+#define SDHC_SYSCTL_HCKEN_MASK                   0x2u
+#define SDHC_SYSCTL_HCKEN_SHIFT                  1
+#define SDHC_SYSCTL_HCKEN_WIDTH                  1
+#define SDHC_SYSCTL_HCKEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_HCKEN_SHIFT))&SDHC_SYSCTL_HCKEN_MASK)
+#define SDHC_SYSCTL_PEREN_MASK                   0x4u
+#define SDHC_SYSCTL_PEREN_SHIFT                  2
+#define SDHC_SYSCTL_PEREN_WIDTH                  1
+#define SDHC_SYSCTL_PEREN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_PEREN_SHIFT))&SDHC_SYSCTL_PEREN_MASK)
+#define SDHC_SYSCTL_SDCLKEN_MASK                 0x8u
+#define SDHC_SYSCTL_SDCLKEN_SHIFT                3
+#define SDHC_SYSCTL_SDCLKEN_WIDTH                1
+#define SDHC_SYSCTL_SDCLKEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKEN_SHIFT))&SDHC_SYSCTL_SDCLKEN_MASK)
+#define SDHC_SYSCTL_DVS_MASK                     0xF0u
+#define SDHC_SYSCTL_DVS_SHIFT                    4
+#define SDHC_SYSCTL_DVS_WIDTH                    4
+#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK                 0xFF00u
+#define SDHC_SYSCTL_SDCLKFS_SHIFT                8
+#define SDHC_SYSCTL_SDCLKFS_WIDTH                8
+#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK                   0xF0000u
+#define SDHC_SYSCTL_DTOCV_SHIFT                  16
+#define SDHC_SYSCTL_DTOCV_WIDTH                  4
+#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK                    0x1000000u
+#define SDHC_SYSCTL_RSTA_SHIFT                   24
+#define SDHC_SYSCTL_RSTA_WIDTH                   1
+#define SDHC_SYSCTL_RSTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTA_SHIFT))&SDHC_SYSCTL_RSTA_MASK)
+#define SDHC_SYSCTL_RSTC_MASK                    0x2000000u
+#define SDHC_SYSCTL_RSTC_SHIFT                   25
+#define SDHC_SYSCTL_RSTC_WIDTH                   1
+#define SDHC_SYSCTL_RSTC(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTC_SHIFT))&SDHC_SYSCTL_RSTC_MASK)
+#define SDHC_SYSCTL_RSTD_MASK                    0x4000000u
+#define SDHC_SYSCTL_RSTD_SHIFT                   26
+#define SDHC_SYSCTL_RSTD_WIDTH                   1
+#define SDHC_SYSCTL_RSTD(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTD_SHIFT))&SDHC_SYSCTL_RSTD_MASK)
+#define SDHC_SYSCTL_INITA_MASK                   0x8000000u
+#define SDHC_SYSCTL_INITA_SHIFT                  27
+#define SDHC_SYSCTL_INITA_WIDTH                  1
+#define SDHC_SYSCTL_INITA(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_INITA_SHIFT))&SDHC_SYSCTL_INITA_MASK)
+/* IRQSTAT Bit Fields */
+#define SDHC_IRQSTAT_CC_MASK                     0x1u
+#define SDHC_IRQSTAT_CC_SHIFT                    0
+#define SDHC_IRQSTAT_CC_WIDTH                    1
+#define SDHC_IRQSTAT_CC(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CC_SHIFT))&SDHC_IRQSTAT_CC_MASK)
+#define SDHC_IRQSTAT_TC_MASK                     0x2u
+#define SDHC_IRQSTAT_TC_SHIFT                    1
+#define SDHC_IRQSTAT_TC_WIDTH                    1
+#define SDHC_IRQSTAT_TC(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_TC_SHIFT))&SDHC_IRQSTAT_TC_MASK)
+#define SDHC_IRQSTAT_BGE_MASK                    0x4u
+#define SDHC_IRQSTAT_BGE_SHIFT                   2
+#define SDHC_IRQSTAT_BGE_WIDTH                   1
+#define SDHC_IRQSTAT_BGE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BGE_SHIFT))&SDHC_IRQSTAT_BGE_MASK)
+#define SDHC_IRQSTAT_DINT_MASK                   0x8u
+#define SDHC_IRQSTAT_DINT_SHIFT                  3
+#define SDHC_IRQSTAT_DINT_WIDTH                  1
+#define SDHC_IRQSTAT_DINT(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DINT_SHIFT))&SDHC_IRQSTAT_DINT_MASK)
+#define SDHC_IRQSTAT_BWR_MASK                    0x10u
+#define SDHC_IRQSTAT_BWR_SHIFT                   4
+#define SDHC_IRQSTAT_BWR_WIDTH                   1
+#define SDHC_IRQSTAT_BWR(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BWR_SHIFT))&SDHC_IRQSTAT_BWR_MASK)
+#define SDHC_IRQSTAT_BRR_MASK                    0x20u
+#define SDHC_IRQSTAT_BRR_SHIFT                   5
+#define SDHC_IRQSTAT_BRR_WIDTH                   1
+#define SDHC_IRQSTAT_BRR(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BRR_SHIFT))&SDHC_IRQSTAT_BRR_MASK)
+#define SDHC_IRQSTAT_CINS_MASK                   0x40u
+#define SDHC_IRQSTAT_CINS_SHIFT                  6
+#define SDHC_IRQSTAT_CINS_WIDTH                  1
+#define SDHC_IRQSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINS_SHIFT))&SDHC_IRQSTAT_CINS_MASK)
+#define SDHC_IRQSTAT_CRM_MASK                    0x80u
+#define SDHC_IRQSTAT_CRM_SHIFT                   7
+#define SDHC_IRQSTAT_CRM_WIDTH                   1
+#define SDHC_IRQSTAT_CRM(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CRM_SHIFT))&SDHC_IRQSTAT_CRM_MASK)
+#define SDHC_IRQSTAT_CINT_MASK                   0x100u
+#define SDHC_IRQSTAT_CINT_SHIFT                  8
+#define SDHC_IRQSTAT_CINT_WIDTH                  1
+#define SDHC_IRQSTAT_CINT(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINT_SHIFT))&SDHC_IRQSTAT_CINT_MASK)
+#define SDHC_IRQSTAT_CTOE_MASK                   0x10000u
+#define SDHC_IRQSTAT_CTOE_SHIFT                  16
+#define SDHC_IRQSTAT_CTOE_WIDTH                  1
+#define SDHC_IRQSTAT_CTOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CTOE_SHIFT))&SDHC_IRQSTAT_CTOE_MASK)
+#define SDHC_IRQSTAT_CCE_MASK                    0x20000u
+#define SDHC_IRQSTAT_CCE_SHIFT                   17
+#define SDHC_IRQSTAT_CCE_WIDTH                   1
+#define SDHC_IRQSTAT_CCE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CCE_SHIFT))&SDHC_IRQSTAT_CCE_MASK)
+#define SDHC_IRQSTAT_CEBE_MASK                   0x40000u
+#define SDHC_IRQSTAT_CEBE_SHIFT                  18
+#define SDHC_IRQSTAT_CEBE_WIDTH                  1
+#define SDHC_IRQSTAT_CEBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CEBE_SHIFT))&SDHC_IRQSTAT_CEBE_MASK)
+#define SDHC_IRQSTAT_CIE_MASK                    0x80000u
+#define SDHC_IRQSTAT_CIE_SHIFT                   19
+#define SDHC_IRQSTAT_CIE_WIDTH                   1
+#define SDHC_IRQSTAT_CIE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CIE_SHIFT))&SDHC_IRQSTAT_CIE_MASK)
+#define SDHC_IRQSTAT_DTOE_MASK                   0x100000u
+#define SDHC_IRQSTAT_DTOE_SHIFT                  20
+#define SDHC_IRQSTAT_DTOE_WIDTH                  1
+#define SDHC_IRQSTAT_DTOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DTOE_SHIFT))&SDHC_IRQSTAT_DTOE_MASK)
+#define SDHC_IRQSTAT_DCE_MASK                    0x200000u
+#define SDHC_IRQSTAT_DCE_SHIFT                   21
+#define SDHC_IRQSTAT_DCE_WIDTH                   1
+#define SDHC_IRQSTAT_DCE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DCE_SHIFT))&SDHC_IRQSTAT_DCE_MASK)
+#define SDHC_IRQSTAT_DEBE_MASK                   0x400000u
+#define SDHC_IRQSTAT_DEBE_SHIFT                  22
+#define SDHC_IRQSTAT_DEBE_WIDTH                  1
+#define SDHC_IRQSTAT_DEBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DEBE_SHIFT))&SDHC_IRQSTAT_DEBE_MASK)
+#define SDHC_IRQSTAT_AC12E_MASK                  0x1000000u
+#define SDHC_IRQSTAT_AC12E_SHIFT                 24
+#define SDHC_IRQSTAT_AC12E_WIDTH                 1
+#define SDHC_IRQSTAT_AC12E(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_AC12E_SHIFT))&SDHC_IRQSTAT_AC12E_MASK)
+#define SDHC_IRQSTAT_DMAE_MASK                   0x10000000u
+#define SDHC_IRQSTAT_DMAE_SHIFT                  28
+#define SDHC_IRQSTAT_DMAE_WIDTH                  1
+#define SDHC_IRQSTAT_DMAE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DMAE_SHIFT))&SDHC_IRQSTAT_DMAE_MASK)
+/* IRQSTATEN Bit Fields */
+#define SDHC_IRQSTATEN_CCSEN_MASK                0x1u
+#define SDHC_IRQSTATEN_CCSEN_SHIFT               0
+#define SDHC_IRQSTATEN_CCSEN_WIDTH               1
+#define SDHC_IRQSTATEN_CCSEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCSEN_SHIFT))&SDHC_IRQSTATEN_CCSEN_MASK)
+#define SDHC_IRQSTATEN_TCSEN_MASK                0x2u
+#define SDHC_IRQSTATEN_TCSEN_SHIFT               1
+#define SDHC_IRQSTATEN_TCSEN_WIDTH               1
+#define SDHC_IRQSTATEN_TCSEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_TCSEN_SHIFT))&SDHC_IRQSTATEN_TCSEN_MASK)
+#define SDHC_IRQSTATEN_BGESEN_MASK               0x4u
+#define SDHC_IRQSTATEN_BGESEN_SHIFT              2
+#define SDHC_IRQSTATEN_BGESEN_WIDTH              1
+#define SDHC_IRQSTATEN_BGESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BGESEN_SHIFT))&SDHC_IRQSTATEN_BGESEN_MASK)
+#define SDHC_IRQSTATEN_DINTSEN_MASK              0x8u
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT             3
+#define SDHC_IRQSTATEN_DINTSEN_WIDTH             1
+#define SDHC_IRQSTATEN_DINTSEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DINTSEN_SHIFT))&SDHC_IRQSTATEN_DINTSEN_MASK)
+#define SDHC_IRQSTATEN_BWRSEN_MASK               0x10u
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT              4
+#define SDHC_IRQSTATEN_BWRSEN_WIDTH              1
+#define SDHC_IRQSTATEN_BWRSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BWRSEN_SHIFT))&SDHC_IRQSTATEN_BWRSEN_MASK)
+#define SDHC_IRQSTATEN_BRRSEN_MASK               0x20u
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT              5
+#define SDHC_IRQSTATEN_BRRSEN_WIDTH              1
+#define SDHC_IRQSTATEN_BRRSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BRRSEN_SHIFT))&SDHC_IRQSTATEN_BRRSEN_MASK)
+#define SDHC_IRQSTATEN_CINSEN_MASK               0x40u
+#define SDHC_IRQSTATEN_CINSEN_SHIFT              6
+#define SDHC_IRQSTATEN_CINSEN_WIDTH              1
+#define SDHC_IRQSTATEN_CINSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINSEN_SHIFT))&SDHC_IRQSTATEN_CINSEN_MASK)
+#define SDHC_IRQSTATEN_CRMSEN_MASK               0x80u
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT              7
+#define SDHC_IRQSTATEN_CRMSEN_WIDTH              1
+#define SDHC_IRQSTATEN_CRMSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CRMSEN_SHIFT))&SDHC_IRQSTATEN_CRMSEN_MASK)
+#define SDHC_IRQSTATEN_CINTSEN_MASK              0x100u
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT             8
+#define SDHC_IRQSTATEN_CINTSEN_WIDTH             1
+#define SDHC_IRQSTATEN_CINTSEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINTSEN_SHIFT))&SDHC_IRQSTATEN_CINTSEN_MASK)
+#define SDHC_IRQSTATEN_CTOESEN_MASK              0x10000u
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT             16
+#define SDHC_IRQSTATEN_CTOESEN_WIDTH             1
+#define SDHC_IRQSTATEN_CTOESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CTOESEN_SHIFT))&SDHC_IRQSTATEN_CTOESEN_MASK)
+#define SDHC_IRQSTATEN_CCESEN_MASK               0x20000u
+#define SDHC_IRQSTATEN_CCESEN_SHIFT              17
+#define SDHC_IRQSTATEN_CCESEN_WIDTH              1
+#define SDHC_IRQSTATEN_CCESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCESEN_SHIFT))&SDHC_IRQSTATEN_CCESEN_MASK)
+#define SDHC_IRQSTATEN_CEBESEN_MASK              0x40000u
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT             18
+#define SDHC_IRQSTATEN_CEBESEN_WIDTH             1
+#define SDHC_IRQSTATEN_CEBESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CEBESEN_SHIFT))&SDHC_IRQSTATEN_CEBESEN_MASK)
+#define SDHC_IRQSTATEN_CIESEN_MASK               0x80000u
+#define SDHC_IRQSTATEN_CIESEN_SHIFT              19
+#define SDHC_IRQSTATEN_CIESEN_WIDTH              1
+#define SDHC_IRQSTATEN_CIESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CIESEN_SHIFT))&SDHC_IRQSTATEN_CIESEN_MASK)
+#define SDHC_IRQSTATEN_DTOESEN_MASK              0x100000u
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT             20
+#define SDHC_IRQSTATEN_DTOESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DTOESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DTOESEN_SHIFT))&SDHC_IRQSTATEN_DTOESEN_MASK)
+#define SDHC_IRQSTATEN_DCESEN_MASK               0x200000u
+#define SDHC_IRQSTATEN_DCESEN_SHIFT              21
+#define SDHC_IRQSTATEN_DCESEN_WIDTH              1
+#define SDHC_IRQSTATEN_DCESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DCESEN_SHIFT))&SDHC_IRQSTATEN_DCESEN_MASK)
+#define SDHC_IRQSTATEN_DEBESEN_MASK              0x400000u
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT             22
+#define SDHC_IRQSTATEN_DEBESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DEBESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DEBESEN_SHIFT))&SDHC_IRQSTATEN_DEBESEN_MASK)
+#define SDHC_IRQSTATEN_AC12ESEN_MASK             0x1000000u
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT            24
+#define SDHC_IRQSTATEN_AC12ESEN_WIDTH            1
+#define SDHC_IRQSTATEN_AC12ESEN(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_AC12ESEN_SHIFT))&SDHC_IRQSTATEN_AC12ESEN_MASK)
+#define SDHC_IRQSTATEN_DMAESEN_MASK              0x10000000u
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT             28
+#define SDHC_IRQSTATEN_DMAESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DMAESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DMAESEN_SHIFT))&SDHC_IRQSTATEN_DMAESEN_MASK)
+/* IRQSIGEN Bit Fields */
+#define SDHC_IRQSIGEN_CCIEN_MASK                 0x1u
+#define SDHC_IRQSIGEN_CCIEN_SHIFT                0
+#define SDHC_IRQSIGEN_CCIEN_WIDTH                1
+#define SDHC_IRQSIGEN_CCIEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCIEN_SHIFT))&SDHC_IRQSIGEN_CCIEN_MASK)
+#define SDHC_IRQSIGEN_TCIEN_MASK                 0x2u
+#define SDHC_IRQSIGEN_TCIEN_SHIFT                1
+#define SDHC_IRQSIGEN_TCIEN_WIDTH                1
+#define SDHC_IRQSIGEN_TCIEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_TCIEN_SHIFT))&SDHC_IRQSIGEN_TCIEN_MASK)
+#define SDHC_IRQSIGEN_BGEIEN_MASK                0x4u
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT               2
+#define SDHC_IRQSIGEN_BGEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BGEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BGEIEN_SHIFT))&SDHC_IRQSIGEN_BGEIEN_MASK)
+#define SDHC_IRQSIGEN_DINTIEN_MASK               0x8u
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT              3
+#define SDHC_IRQSIGEN_DINTIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DINTIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DINTIEN_SHIFT))&SDHC_IRQSIGEN_DINTIEN_MASK)
+#define SDHC_IRQSIGEN_BWRIEN_MASK                0x10u
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT               4
+#define SDHC_IRQSIGEN_BWRIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BWRIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BWRIEN_SHIFT))&SDHC_IRQSIGEN_BWRIEN_MASK)
+#define SDHC_IRQSIGEN_BRRIEN_MASK                0x20u
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT               5
+#define SDHC_IRQSIGEN_BRRIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BRRIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BRRIEN_SHIFT))&SDHC_IRQSIGEN_BRRIEN_MASK)
+#define SDHC_IRQSIGEN_CINSIEN_MASK               0x40u
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT              6
+#define SDHC_IRQSIGEN_CINSIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CINSIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINSIEN_SHIFT))&SDHC_IRQSIGEN_CINSIEN_MASK)
+#define SDHC_IRQSIGEN_CRMIEN_MASK                0x80u
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT               7
+#define SDHC_IRQSIGEN_CRMIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CRMIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CRMIEN_SHIFT))&SDHC_IRQSIGEN_CRMIEN_MASK)
+#define SDHC_IRQSIGEN_CINTIEN_MASK               0x100u
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT              8
+#define SDHC_IRQSIGEN_CINTIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CINTIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINTIEN_SHIFT))&SDHC_IRQSIGEN_CINTIEN_MASK)
+#define SDHC_IRQSIGEN_CTOEIEN_MASK               0x10000u
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT              16
+#define SDHC_IRQSIGEN_CTOEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CTOEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CTOEIEN_SHIFT))&SDHC_IRQSIGEN_CTOEIEN_MASK)
+#define SDHC_IRQSIGEN_CCEIEN_MASK                0x20000u
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT               17
+#define SDHC_IRQSIGEN_CCEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CCEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCEIEN_SHIFT))&SDHC_IRQSIGEN_CCEIEN_MASK)
+#define SDHC_IRQSIGEN_CEBEIEN_MASK               0x40000u
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT              18
+#define SDHC_IRQSIGEN_CEBEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CEBEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CEBEIEN_SHIFT))&SDHC_IRQSIGEN_CEBEIEN_MASK)
+#define SDHC_IRQSIGEN_CIEIEN_MASK                0x80000u
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT               19
+#define SDHC_IRQSIGEN_CIEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CIEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CIEIEN_SHIFT))&SDHC_IRQSIGEN_CIEIEN_MASK)
+#define SDHC_IRQSIGEN_DTOEIEN_MASK               0x100000u
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT              20
+#define SDHC_IRQSIGEN_DTOEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DTOEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DTOEIEN_SHIFT))&SDHC_IRQSIGEN_DTOEIEN_MASK)
+#define SDHC_IRQSIGEN_DCEIEN_MASK                0x200000u
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT               21
+#define SDHC_IRQSIGEN_DCEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_DCEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DCEIEN_SHIFT))&SDHC_IRQSIGEN_DCEIEN_MASK)
+#define SDHC_IRQSIGEN_DEBEIEN_MASK               0x400000u
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT              22
+#define SDHC_IRQSIGEN_DEBEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DEBEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DEBEIEN_SHIFT))&SDHC_IRQSIGEN_DEBEIEN_MASK)
+#define SDHC_IRQSIGEN_AC12EIEN_MASK              0x1000000u
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT             24
+#define SDHC_IRQSIGEN_AC12EIEN_WIDTH             1
+#define SDHC_IRQSIGEN_AC12EIEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_AC12EIEN_SHIFT))&SDHC_IRQSIGEN_AC12EIEN_MASK)
+#define SDHC_IRQSIGEN_DMAEIEN_MASK               0x10000000u
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT              28
+#define SDHC_IRQSIGEN_DMAEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DMAEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DMAEIEN_SHIFT))&SDHC_IRQSIGEN_DMAEIEN_MASK)
+/* AC12ERR Bit Fields */
+#define SDHC_AC12ERR_AC12NE_MASK                 0x1u
+#define SDHC_AC12ERR_AC12NE_SHIFT                0
+#define SDHC_AC12ERR_AC12NE_WIDTH                1
+#define SDHC_AC12ERR_AC12NE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12NE_SHIFT))&SDHC_AC12ERR_AC12NE_MASK)
+#define SDHC_AC12ERR_AC12TOE_MASK                0x2u
+#define SDHC_AC12ERR_AC12TOE_SHIFT               1
+#define SDHC_AC12ERR_AC12TOE_WIDTH               1
+#define SDHC_AC12ERR_AC12TOE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12TOE_SHIFT))&SDHC_AC12ERR_AC12TOE_MASK)
+#define SDHC_AC12ERR_AC12EBE_MASK                0x4u
+#define SDHC_AC12ERR_AC12EBE_SHIFT               2
+#define SDHC_AC12ERR_AC12EBE_WIDTH               1
+#define SDHC_AC12ERR_AC12EBE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12EBE_SHIFT))&SDHC_AC12ERR_AC12EBE_MASK)
+#define SDHC_AC12ERR_AC12CE_MASK                 0x8u
+#define SDHC_AC12ERR_AC12CE_SHIFT                3
+#define SDHC_AC12ERR_AC12CE_WIDTH                1
+#define SDHC_AC12ERR_AC12CE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12CE_SHIFT))&SDHC_AC12ERR_AC12CE_MASK)
+#define SDHC_AC12ERR_AC12IE_MASK                 0x10u
+#define SDHC_AC12ERR_AC12IE_SHIFT                4
+#define SDHC_AC12ERR_AC12IE_WIDTH                1
+#define SDHC_AC12ERR_AC12IE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12IE_SHIFT))&SDHC_AC12ERR_AC12IE_MASK)
+#define SDHC_AC12ERR_CNIBAC12E_MASK              0x80u
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT             7
+#define SDHC_AC12ERR_CNIBAC12E_WIDTH             1
+#define SDHC_AC12ERR_CNIBAC12E(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_CNIBAC12E_SHIFT))&SDHC_AC12ERR_CNIBAC12E_MASK)
+/* HTCAPBLT Bit Fields */
+#define SDHC_HTCAPBLT_MBL_MASK                   0x70000u
+#define SDHC_HTCAPBLT_MBL_SHIFT                  16
+#define SDHC_HTCAPBLT_MBL_WIDTH                  3
+#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK                 0x100000u
+#define SDHC_HTCAPBLT_ADMAS_SHIFT                20
+#define SDHC_HTCAPBLT_ADMAS_WIDTH                1
+#define SDHC_HTCAPBLT_ADMAS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_ADMAS_SHIFT))&SDHC_HTCAPBLT_ADMAS_MASK)
+#define SDHC_HTCAPBLT_HSS_MASK                   0x200000u
+#define SDHC_HTCAPBLT_HSS_SHIFT                  21
+#define SDHC_HTCAPBLT_HSS_WIDTH                  1
+#define SDHC_HTCAPBLT_HSS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_HSS_SHIFT))&SDHC_HTCAPBLT_HSS_MASK)
+#define SDHC_HTCAPBLT_DMAS_MASK                  0x400000u
+#define SDHC_HTCAPBLT_DMAS_SHIFT                 22
+#define SDHC_HTCAPBLT_DMAS_WIDTH                 1
+#define SDHC_HTCAPBLT_DMAS(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_DMAS_SHIFT))&SDHC_HTCAPBLT_DMAS_MASK)
+#define SDHC_HTCAPBLT_SRS_MASK                   0x800000u
+#define SDHC_HTCAPBLT_SRS_SHIFT                  23
+#define SDHC_HTCAPBLT_SRS_WIDTH                  1
+#define SDHC_HTCAPBLT_SRS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_SRS_SHIFT))&SDHC_HTCAPBLT_SRS_MASK)
+#define SDHC_HTCAPBLT_VS33_MASK                  0x1000000u
+#define SDHC_HTCAPBLT_VS33_SHIFT                 24
+#define SDHC_HTCAPBLT_VS33_WIDTH                 1
+#define SDHC_HTCAPBLT_VS33(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_VS33_SHIFT))&SDHC_HTCAPBLT_VS33_MASK)
+/* WML Bit Fields */
+#define SDHC_WML_RDWML_MASK                      0xFFu
+#define SDHC_WML_RDWML_SHIFT                     0
+#define SDHC_WML_RDWML_WIDTH                     8
+#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK                      0xFF0000u
+#define SDHC_WML_WRWML_SHIFT                     16
+#define SDHC_WML_WRWML_WIDTH                     8
+#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
+/* FEVT Bit Fields */
+#define SDHC_FEVT_AC12NE_MASK                    0x1u
+#define SDHC_FEVT_AC12NE_SHIFT                   0
+#define SDHC_FEVT_AC12NE_WIDTH                   1
+#define SDHC_FEVT_AC12NE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12NE_SHIFT))&SDHC_FEVT_AC12NE_MASK)
+#define SDHC_FEVT_AC12TOE_MASK                   0x2u
+#define SDHC_FEVT_AC12TOE_SHIFT                  1
+#define SDHC_FEVT_AC12TOE_WIDTH                  1
+#define SDHC_FEVT_AC12TOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12TOE_SHIFT))&SDHC_FEVT_AC12TOE_MASK)
+#define SDHC_FEVT_AC12CE_MASK                    0x4u
+#define SDHC_FEVT_AC12CE_SHIFT                   2
+#define SDHC_FEVT_AC12CE_WIDTH                   1
+#define SDHC_FEVT_AC12CE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12CE_SHIFT))&SDHC_FEVT_AC12CE_MASK)
+#define SDHC_FEVT_AC12EBE_MASK                   0x8u
+#define SDHC_FEVT_AC12EBE_SHIFT                  3
+#define SDHC_FEVT_AC12EBE_WIDTH                  1
+#define SDHC_FEVT_AC12EBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12EBE_SHIFT))&SDHC_FEVT_AC12EBE_MASK)
+#define SDHC_FEVT_AC12IE_MASK                    0x10u
+#define SDHC_FEVT_AC12IE_SHIFT                   4
+#define SDHC_FEVT_AC12IE_WIDTH                   1
+#define SDHC_FEVT_AC12IE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12IE_SHIFT))&SDHC_FEVT_AC12IE_MASK)
+#define SDHC_FEVT_CNIBAC12E_MASK                 0x80u
+#define SDHC_FEVT_CNIBAC12E_SHIFT                7
+#define SDHC_FEVT_CNIBAC12E_WIDTH                1
+#define SDHC_FEVT_CNIBAC12E(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CNIBAC12E_SHIFT))&SDHC_FEVT_CNIBAC12E_MASK)
+#define SDHC_FEVT_CTOE_MASK                      0x10000u
+#define SDHC_FEVT_CTOE_SHIFT                     16
+#define SDHC_FEVT_CTOE_WIDTH                     1
+#define SDHC_FEVT_CTOE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CTOE_SHIFT))&SDHC_FEVT_CTOE_MASK)
+#define SDHC_FEVT_CCE_MASK                       0x20000u
+#define SDHC_FEVT_CCE_SHIFT                      17
+#define SDHC_FEVT_CCE_WIDTH                      1
+#define SDHC_FEVT_CCE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CCE_SHIFT))&SDHC_FEVT_CCE_MASK)
+#define SDHC_FEVT_CEBE_MASK                      0x40000u
+#define SDHC_FEVT_CEBE_SHIFT                     18
+#define SDHC_FEVT_CEBE_WIDTH                     1
+#define SDHC_FEVT_CEBE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CEBE_SHIFT))&SDHC_FEVT_CEBE_MASK)
+#define SDHC_FEVT_CIE_MASK                       0x80000u
+#define SDHC_FEVT_CIE_SHIFT                      19
+#define SDHC_FEVT_CIE_WIDTH                      1
+#define SDHC_FEVT_CIE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CIE_SHIFT))&SDHC_FEVT_CIE_MASK)
+#define SDHC_FEVT_DTOE_MASK                      0x100000u
+#define SDHC_FEVT_DTOE_SHIFT                     20
+#define SDHC_FEVT_DTOE_WIDTH                     1
+#define SDHC_FEVT_DTOE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DTOE_SHIFT))&SDHC_FEVT_DTOE_MASK)
+#define SDHC_FEVT_DCE_MASK                       0x200000u
+#define SDHC_FEVT_DCE_SHIFT                      21
+#define SDHC_FEVT_DCE_WIDTH                      1
+#define SDHC_FEVT_DCE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DCE_SHIFT))&SDHC_FEVT_DCE_MASK)
+#define SDHC_FEVT_DEBE_MASK                      0x400000u
+#define SDHC_FEVT_DEBE_SHIFT                     22
+#define SDHC_FEVT_DEBE_WIDTH                     1
+#define SDHC_FEVT_DEBE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DEBE_SHIFT))&SDHC_FEVT_DEBE_MASK)
+#define SDHC_FEVT_AC12E_MASK                     0x1000000u
+#define SDHC_FEVT_AC12E_SHIFT                    24
+#define SDHC_FEVT_AC12E_WIDTH                    1
+#define SDHC_FEVT_AC12E(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12E_SHIFT))&SDHC_FEVT_AC12E_MASK)
+#define SDHC_FEVT_DMAE_MASK                      0x10000000u
+#define SDHC_FEVT_DMAE_SHIFT                     28
+#define SDHC_FEVT_DMAE_WIDTH                     1
+#define SDHC_FEVT_DMAE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DMAE_SHIFT))&SDHC_FEVT_DMAE_MASK)
+#define SDHC_FEVT_CINT_MASK                      0x80000000u
+#define SDHC_FEVT_CINT_SHIFT                     31
+#define SDHC_FEVT_CINT_WIDTH                     1
+#define SDHC_FEVT_CINT(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CINT_SHIFT))&SDHC_FEVT_CINT_MASK)
+/* ADMAES Bit Fields */
+#define SDHC_ADMAES_ADMAES_MASK                  0x3u
+#define SDHC_ADMAES_ADMAES_SHIFT                 0
+#define SDHC_ADMAES_ADMAES_WIDTH                 2
+#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK                 0x4u
+#define SDHC_ADMAES_ADMALME_SHIFT                2
+#define SDHC_ADMAES_ADMALME_WIDTH                1
+#define SDHC_ADMAES_ADMALME(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMALME_SHIFT))&SDHC_ADMAES_ADMALME_MASK)
+#define SDHC_ADMAES_ADMADCE_MASK                 0x8u
+#define SDHC_ADMAES_ADMADCE_SHIFT                3
+#define SDHC_ADMAES_ADMADCE_WIDTH                1
+#define SDHC_ADMAES_ADMADCE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMADCE_SHIFT))&SDHC_ADMAES_ADMADCE_MASK)
+/* ADSADDR Bit Fields */
+#define SDHC_ADSADDR_ADSADDR_MASK                0xFFFFFFFCu
+#define SDHC_ADSADDR_ADSADDR_SHIFT               2
+#define SDHC_ADSADDR_ADSADDR_WIDTH               30
+#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
+/* VENDOR Bit Fields */
+#define SDHC_VENDOR_EXTDMAEN_MASK                0x1u
+#define SDHC_VENDOR_EXTDMAEN_SHIFT               0
+#define SDHC_VENDOR_EXTDMAEN_WIDTH               1
+#define SDHC_VENDOR_EXTDMAEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXTDMAEN_SHIFT))&SDHC_VENDOR_EXTDMAEN_MASK)
+#define SDHC_VENDOR_EXBLKNU_MASK                 0x2u
+#define SDHC_VENDOR_EXBLKNU_SHIFT                1
+#define SDHC_VENDOR_EXBLKNU_WIDTH                1
+#define SDHC_VENDOR_EXBLKNU(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXBLKNU_SHIFT))&SDHC_VENDOR_EXBLKNU_MASK)
+#define SDHC_VENDOR_INTSTVAL_MASK                0xFF0000u
+#define SDHC_VENDOR_INTSTVAL_SHIFT               16
+#define SDHC_VENDOR_INTSTVAL_WIDTH               8
+#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
+/* MMCBOOT Bit Fields */
+#define SDHC_MMCBOOT_DTOCVACK_MASK               0xFu
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT              0
+#define SDHC_MMCBOOT_DTOCVACK_WIDTH              4
+#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK                0x10u
+#define SDHC_MMCBOOT_BOOTACK_SHIFT               4
+#define SDHC_MMCBOOT_BOOTACK_WIDTH               1
+#define SDHC_MMCBOOT_BOOTACK(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTACK_SHIFT))&SDHC_MMCBOOT_BOOTACK_MASK)
+#define SDHC_MMCBOOT_BOOTMODE_MASK               0x20u
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT              5
+#define SDHC_MMCBOOT_BOOTMODE_WIDTH              1
+#define SDHC_MMCBOOT_BOOTMODE(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTMODE_SHIFT))&SDHC_MMCBOOT_BOOTMODE_MASK)
+#define SDHC_MMCBOOT_BOOTEN_MASK                 0x40u
+#define SDHC_MMCBOOT_BOOTEN_SHIFT                6
+#define SDHC_MMCBOOT_BOOTEN_WIDTH                1
+#define SDHC_MMCBOOT_BOOTEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTEN_SHIFT))&SDHC_MMCBOOT_BOOTEN_MASK)
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK             0x80u
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            7
+#define SDHC_MMCBOOT_AUTOSABGEN_WIDTH            1
+#define SDHC_MMCBOOT_AUTOSABGEN(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_AUTOSABGEN_SHIFT))&SDHC_MMCBOOT_AUTOSABGEN_MASK)
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             0xFFFF0000u
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            16
+#define SDHC_MMCBOOT_BOOTBLKCNT_WIDTH            16
+#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+/* HOSTVER Bit Fields */
+#define SDHC_HOSTVER_SVN_MASK                    0xFFu
+#define SDHC_HOSTVER_SVN_SHIFT                   0
+#define SDHC_HOSTVER_SVN_WIDTH                   8
+#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK                    0xFF00u
+#define SDHC_HOSTVER_VVN_SHIFT                   8
+#define SDHC_HOSTVER_VVN_WIDTH                   8
+#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/** Peripheral SDHC base address */
+#define SDHC_BASE                                (0x400B1000u)
+/** Peripheral SDHC base pointer */
+#define SDHC                                     ((SDHC_Type *)SDHC_BASE)
+#define SDHC_BASE_PTR                            (SDHC)
+/** Array initializer of SDHC peripheral base addresses */
+#define SDHC_BASE_ADDRS                          { SDHC_BASE }
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASE_PTRS                           { SDHC }
+/** Interrupt vectors for the SDHC peripheral type */
+#define SDHC_IRQS                                { SDHC_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register instance definitions */
+/* SDHC */
+#define SDHC_DSADDR                              SDHC_DSADDR_REG(SDHC)
+#define SDHC_BLKATTR                             SDHC_BLKATTR_REG(SDHC)
+#define SDHC_CMDARG                              SDHC_CMDARG_REG(SDHC)
+#define SDHC_XFERTYP                             SDHC_XFERTYP_REG(SDHC)
+#define SDHC_CMDRSP0                             SDHC_CMDRSP_REG(SDHC,0)
+#define SDHC_CMDRSP1                             SDHC_CMDRSP_REG(SDHC,1)
+#define SDHC_CMDRSP2                             SDHC_CMDRSP_REG(SDHC,2)
+#define SDHC_CMDRSP3                             SDHC_CMDRSP_REG(SDHC,3)
+#define SDHC_DATPORT                             SDHC_DATPORT_REG(SDHC)
+#define SDHC_PRSSTAT                             SDHC_PRSSTAT_REG(SDHC)
+#define SDHC_PROCTL                              SDHC_PROCTL_REG(SDHC)
+#define SDHC_SYSCTL                              SDHC_SYSCTL_REG(SDHC)
+#define SDHC_IRQSTAT                             SDHC_IRQSTAT_REG(SDHC)
+#define SDHC_IRQSTATEN                           SDHC_IRQSTATEN_REG(SDHC)
+#define SDHC_IRQSIGEN                            SDHC_IRQSIGEN_REG(SDHC)
+#define SDHC_AC12ERR                             SDHC_AC12ERR_REG(SDHC)
+#define SDHC_HTCAPBLT                            SDHC_HTCAPBLT_REG(SDHC)
+#define SDHC_WML                                 SDHC_WML_REG(SDHC)
+#define SDHC_FEVT                                SDHC_FEVT_REG(SDHC)
+#define SDHC_ADMAES                              SDHC_ADMAES_REG(SDHC)
+#define SDHC_ADSADDR                             SDHC_ADSADDR_REG(SDHC)
+#define SDHC_VENDOR                              SDHC_VENDOR_REG(SDHC)
+#define SDHC_MMCBOOT                             SDHC_MMCBOOT_REG(SDHC)
+#define SDHC_HOSTVER                             SDHC_HOSTVER_REG(SDHC)
+
+/* SDHC - Register array accessors */
+#define SDHC_CMDRSP(index)                       SDHC_CMDRSP_REG(SDHC,index)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
+       uint8_t RESERVED_0[4092];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+  __IO uint32_t SCGC1;                             /**< System Clock Gating Control Register 1, offset: 0x1028 */
+  __IO uint32_t SCGC2;                             /**< System Clock Gating Control Register 2, offset: 0x102C */
+  __IO uint32_t SCGC3;                             /**< System Clock Gating Control Register 3, offset: 0x1030 */
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+  __IO uint32_t CLKDIV2;                           /**< System Clock Divider Register 2, offset: 0x1048 */
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+  __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base)                      ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base)                   ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base)                      ((base)->SOPT2)
+#define SIM_SOPT4_REG(base)                      ((base)->SOPT4)
+#define SIM_SOPT5_REG(base)                      ((base)->SOPT5)
+#define SIM_SOPT7_REG(base)                      ((base)->SOPT7)
+#define SIM_SDID_REG(base)                       ((base)->SDID)
+#define SIM_SCGC1_REG(base)                      ((base)->SCGC1)
+#define SIM_SCGC2_REG(base)                      ((base)->SCGC2)
+#define SIM_SCGC3_REG(base)                      ((base)->SCGC3)
+#define SIM_SCGC4_REG(base)                      ((base)->SCGC4)
+#define SIM_SCGC5_REG(base)                      ((base)->SCGC5)
+#define SIM_SCGC6_REG(base)                      ((base)->SCGC6)
+#define SIM_SCGC7_REG(base)                      ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base)                    ((base)->CLKDIV1)
+#define SIM_CLKDIV2_REG(base)                    ((base)->CLKDIV2)
+#define SIM_FCFG1_REG(base)                      ((base)->FCFG1)
+#define SIM_FCFG2_REG(base)                      ((base)->FCFG2)
+#define SIM_UIDH_REG(base)                       ((base)->UIDH)
+#define SIM_UIDMH_REG(base)                      ((base)->UIDMH)
+#define SIM_UIDML_REG(base)                      ((base)->UIDML)
+#define SIM_UIDL_REG(base)                       ((base)->UIDL)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK                   0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT                  12
+#define SIM_SOPT1_RAMSIZE_WIDTH                  4
+#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT                18
+#define SIM_SOPT1_OSC32KSEL_WIDTH                2
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK                  0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT                 29
+#define SIM_SOPT1_USBVSTBY_WIDTH                 1
+#define SIM_SOPT1_USBVSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBVSTBY_SHIFT))&SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK                  0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT                 30
+#define SIM_SOPT1_USBSSTBY_WIDTH                 1
+#define SIM_SOPT1_USBSSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBSSTBY_SHIFT))&SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK                  0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT                 31
+#define SIM_SOPT1_USBREGEN_WIDTH                 1
+#define SIM_SOPT1_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBREGEN_SHIFT))&SIM_SOPT1_USBREGEN_MASK)
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK                   0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT                  24
+#define SIM_SOPT1CFG_URWE_WIDTH                  1
+#define SIM_SOPT1CFG_URWE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_URWE_SHIFT))&SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK                  0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT                 25
+#define SIM_SOPT1CFG_UVSWE_WIDTH                 1
+#define SIM_SOPT1CFG_UVSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_UVSWE_SHIFT))&SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK                  0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT                 26
+#define SIM_SOPT1CFG_USSWE_WIDTH                 1
+#define SIM_SOPT1CFG_USSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_USSWE_SHIFT))&SIM_SOPT1CFG_USSWE_MASK)
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
+#define SIM_SOPT2_RTCCLKOUTSEL_WIDTH             1
+#define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                5
+#define SIM_SOPT2_CLKOUTSEL_WIDTH                3
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK                      0x300u
+#define SIM_SOPT2_FBSL_SHIFT                     8
+#define SIM_SOPT2_FBSL_WIDTH                     2
+#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK                   0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT                  11
+#define SIM_SOPT2_PTD7PAD_WIDTH                  1
+#define SIM_SOPT2_PTD7PAD(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PTD7PAD_SHIFT))&SIM_SOPT2_PTD7PAD_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK               0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT              12
+#define SIM_SOPT2_TRACECLKSEL_WIDTH              1
+#define SIM_SOPT2_TRACECLKSEL(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TRACECLKSEL_SHIFT))&SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK                 0x30000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                16
+#define SIM_SOPT2_PLLFLLSEL_WIDTH                2
+#define SIM_SOPT2_PLLFLLSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK                    0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT                   18
+#define SIM_SOPT2_USBSRC_WIDTH                   1
+#define SIM_SOPT2_USBSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_RMIISRC_MASK                   0x80000u
+#define SIM_SOPT2_RMIISRC_SHIFT                  19
+#define SIM_SOPT2_RMIISRC_WIDTH                  1
+#define SIM_SOPT2_RMIISRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RMIISRC_SHIFT))&SIM_SOPT2_RMIISRC_MASK)
+#define SIM_SOPT2_TIMESRC_MASK                   0x300000u
+#define SIM_SOPT2_TIMESRC_SHIFT                  20
+#define SIM_SOPT2_TIMESRC_WIDTH                  2
+#define SIM_SOPT2_TIMESRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK                   0x30000000u
+#define SIM_SOPT2_SDHCSRC_SHIFT                  28
+#define SIM_SOPT2_SDHCSRC_WIDTH                  2
+#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK                  0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT                 0
+#define SIM_SOPT4_FTM0FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT0_SHIFT))&SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK                  0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT                 1
+#define SIM_SOPT4_FTM0FLT1_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT1_SHIFT))&SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM0FLT2_MASK                  0x4u
+#define SIM_SOPT4_FTM0FLT2_SHIFT                 2
+#define SIM_SOPT4_FTM0FLT2_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT2(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT2_SHIFT))&SIM_SOPT4_FTM0FLT2_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK                  0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT                 4
+#define SIM_SOPT4_FTM1FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM1FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1FLT0_SHIFT))&SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_MASK                  0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT                 8
+#define SIM_SOPT4_FTM2FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM2FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2FLT0_SHIFT))&SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM3FLT0_MASK                  0x1000u
+#define SIM_SOPT4_FTM3FLT0_SHIFT                 12
+#define SIM_SOPT4_FTM3FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM3FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3FLT0_SHIFT))&SIM_SOPT4_FTM3FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK                0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT               18
+#define SIM_SOPT4_FTM1CH0SRC_WIDTH               2
+#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK                0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT               20
+#define SIM_SOPT4_FTM2CH0SRC_WIDTH               2
+#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK                0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT               24
+#define SIM_SOPT4_FTM0CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0CLKSEL_SHIFT))&SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK                0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT               25
+#define SIM_SOPT4_FTM1CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CLKSEL_SHIFT))&SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_MASK                0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT               26
+#define SIM_SOPT4_FTM2CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CLKSEL_SHIFT))&SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM3CLKSEL_MASK                0x8000000u
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT               27
+#define SIM_SOPT4_FTM3CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM3CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3CLKSEL_SHIFT))&SIM_SOPT4_FTM3CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK               0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT              28
+#define SIM_SOPT4_FTM0TRG0SRC_WIDTH              1
+#define SIM_SOPT4_FTM0TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG0SRC_SHIFT))&SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_MASK               0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT              29
+#define SIM_SOPT4_FTM0TRG1SRC_WIDTH              1
+#define SIM_SOPT4_FTM0TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG1SRC_SHIFT))&SIM_SOPT4_FTM0TRG1SRC_MASK)
+#define SIM_SOPT4_FTM3TRG0SRC_MASK               0x40000000u
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT              30
+#define SIM_SOPT4_FTM3TRG0SRC_WIDTH              1
+#define SIM_SOPT4_FTM3TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG0SRC_SHIFT))&SIM_SOPT4_FTM3TRG0SRC_MASK)
+#define SIM_SOPT4_FTM3TRG1SRC_MASK               0x80000000u
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT              31
+#define SIM_SOPT4_FTM3TRG1SRC_WIDTH              1
+#define SIM_SOPT4_FTM3TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG1SRC_SHIFT))&SIM_SOPT4_FTM3TRG1SRC_MASK)
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK                0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT               0
+#define SIM_SOPT5_UART0TXSRC_WIDTH               2
+#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK                0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT               2
+#define SIM_SOPT5_UART0RXSRC_WIDTH               2
+#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK                0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT               4
+#define SIM_SOPT5_UART1TXSRC_WIDTH               2
+#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK                0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT               6
+#define SIM_SOPT5_UART1RXSRC_WIDTH               2
+#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
+#define SIM_SOPT7_ADC0TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
+#define SIM_SOPT7_ADC0PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
+#define SIM_SOPT7_ADC0ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_MASK                0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT               8
+#define SIM_SOPT7_ADC1TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK             0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            12
+#define SIM_SOPT7_ADC1PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC1PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1PRETRGSEL_SHIFT))&SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK              0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             15
+#define SIM_SOPT7_ADC1ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC1ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1ALTTRGEN_SHIFT))&SIM_SOPT7_ADC1ALTTRGEN_MASK)
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK                      0xFu
+#define SIM_SDID_PINID_SHIFT                     0
+#define SIM_SDID_PINID_WIDTH                     4
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK                      0x70u
+#define SIM_SDID_FAMID_SHIFT                     4
+#define SIM_SDID_FAMID_WIDTH                     3
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK                      0xF80u
+#define SIM_SDID_DIEID_SHIFT                     7
+#define SIM_SDID_DIEID_WIDTH                     5
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      0xF000u
+#define SIM_SDID_REVID_SHIFT                     12
+#define SIM_SDID_REVID_WIDTH                     4
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK                   0xF00000u
+#define SIM_SDID_SERIESID_SHIFT                  20
+#define SIM_SDID_SERIESID_WIDTH                  4
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT                  24
+#define SIM_SDID_SUBFAMID_WIDTH                  4
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK                   0xF0000000u
+#define SIM_SDID_FAMILYID_SHIFT                  28
+#define SIM_SDID_FAMILYID_WIDTH                  4
+#define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
+/* SCGC1 Bit Fields */
+#define SIM_SCGC1_I2C2_MASK                      0x40u
+#define SIM_SCGC1_I2C2_SHIFT                     6
+#define SIM_SCGC1_I2C2_WIDTH                     1
+#define SIM_SCGC1_I2C2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_I2C2_SHIFT))&SIM_SCGC1_I2C2_MASK)
+#define SIM_SCGC1_UART4_MASK                     0x400u
+#define SIM_SCGC1_UART4_SHIFT                    10
+#define SIM_SCGC1_UART4_WIDTH                    1
+#define SIM_SCGC1_UART4(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART4_SHIFT))&SIM_SCGC1_UART4_MASK)
+#define SIM_SCGC1_UART5_MASK                     0x800u
+#define SIM_SCGC1_UART5_SHIFT                    11
+#define SIM_SCGC1_UART5_WIDTH                    1
+#define SIM_SCGC1_UART5(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART5_SHIFT))&SIM_SCGC1_UART5_MASK)
+/* SCGC2 Bit Fields */
+#define SIM_SCGC2_ENET_MASK                      0x1u
+#define SIM_SCGC2_ENET_SHIFT                     0
+#define SIM_SCGC2_ENET_WIDTH                     1
+#define SIM_SCGC2_ENET(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_ENET_SHIFT))&SIM_SCGC2_ENET_MASK)
+#define SIM_SCGC2_DAC0_MASK                      0x1000u
+#define SIM_SCGC2_DAC0_SHIFT                     12
+#define SIM_SCGC2_DAC0_WIDTH                     1
+#define SIM_SCGC2_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC0_SHIFT))&SIM_SCGC2_DAC0_MASK)
+#define SIM_SCGC2_DAC1_MASK                      0x2000u
+#define SIM_SCGC2_DAC1_SHIFT                     13
+#define SIM_SCGC2_DAC1_WIDTH                     1
+#define SIM_SCGC2_DAC1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC1_SHIFT))&SIM_SCGC2_DAC1_MASK)
+/* SCGC3 Bit Fields */
+#define SIM_SCGC3_RNGA_MASK                      0x1u
+#define SIM_SCGC3_RNGA_SHIFT                     0
+#define SIM_SCGC3_RNGA_WIDTH                     1
+#define SIM_SCGC3_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_RNGA_SHIFT))&SIM_SCGC3_RNGA_MASK)
+#define SIM_SCGC3_SPI2_MASK                      0x1000u
+#define SIM_SCGC3_SPI2_SHIFT                     12
+#define SIM_SCGC3_SPI2_WIDTH                     1
+#define SIM_SCGC3_SPI2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SPI2_SHIFT))&SIM_SCGC3_SPI2_MASK)
+#define SIM_SCGC3_SDHC_MASK                      0x20000u
+#define SIM_SCGC3_SDHC_SHIFT                     17
+#define SIM_SCGC3_SDHC_WIDTH                     1
+#define SIM_SCGC3_SDHC(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SDHC_SHIFT))&SIM_SCGC3_SDHC_MASK)
+#define SIM_SCGC3_FTM2_MASK                      0x1000000u
+#define SIM_SCGC3_FTM2_SHIFT                     24
+#define SIM_SCGC3_FTM2_WIDTH                     1
+#define SIM_SCGC3_FTM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM2_SHIFT))&SIM_SCGC3_FTM2_MASK)
+#define SIM_SCGC3_FTM3_MASK                      0x2000000u
+#define SIM_SCGC3_FTM3_SHIFT                     25
+#define SIM_SCGC3_FTM3_WIDTH                     1
+#define SIM_SCGC3_FTM3(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM3_SHIFT))&SIM_SCGC3_FTM3_MASK)
+#define SIM_SCGC3_ADC1_MASK                      0x8000000u
+#define SIM_SCGC3_ADC1_SHIFT                     27
+#define SIM_SCGC3_ADC1_WIDTH                     1
+#define SIM_SCGC3_ADC1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_ADC1_SHIFT))&SIM_SCGC3_ADC1_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK                       0x2u
+#define SIM_SCGC4_EWM_SHIFT                      1
+#define SIM_SCGC4_EWM_WIDTH                      1
+#define SIM_SCGC4_EWM(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_EWM_SHIFT))&SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_CMT_MASK                       0x4u
+#define SIM_SCGC4_CMT_SHIFT                      2
+#define SIM_SCGC4_CMT_WIDTH                      1
+#define SIM_SCGC4_CMT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMT_SHIFT))&SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_I2C0_MASK                      0x40u
+#define SIM_SCGC4_I2C0_SHIFT                     6
+#define SIM_SCGC4_I2C0_WIDTH                     1
+#define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C0_SHIFT))&SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK                      0x80u
+#define SIM_SCGC4_I2C1_SHIFT                     7
+#define SIM_SCGC4_I2C1_WIDTH                     1
+#define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C1_SHIFT))&SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK                     0x400u
+#define SIM_SCGC4_UART0_SHIFT                    10
+#define SIM_SCGC4_UART0_WIDTH                    1
+#define SIM_SCGC4_UART0(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART0_SHIFT))&SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK                     0x800u
+#define SIM_SCGC4_UART1_SHIFT                    11
+#define SIM_SCGC4_UART1_WIDTH                    1
+#define SIM_SCGC4_UART1(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART1_SHIFT))&SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK                     0x1000u
+#define SIM_SCGC4_UART2_SHIFT                    12
+#define SIM_SCGC4_UART2_WIDTH                    1
+#define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_UART3_MASK                     0x2000u
+#define SIM_SCGC4_UART3_SHIFT                    13
+#define SIM_SCGC4_UART3_WIDTH                    1
+#define SIM_SCGC4_UART3(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART3_SHIFT))&SIM_SCGC4_UART3_MASK)
+#define SIM_SCGC4_USBOTG_MASK                    0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT                   18
+#define SIM_SCGC4_USBOTG_WIDTH                   1
+#define SIM_SCGC4_USBOTG(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBOTG_SHIFT))&SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK                       0x80000u
+#define SIM_SCGC4_CMP_SHIFT                      19
+#define SIM_SCGC4_CMP_WIDTH                      1
+#define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK                      0x100000u
+#define SIM_SCGC4_VREF_SHIFT                     20
+#define SIM_SCGC4_VREF_WIDTH                     1
+#define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_VREF_SHIFT))&SIM_SCGC4_VREF_MASK)
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK                     0x1u
+#define SIM_SCGC5_LPTMR_SHIFT                    0
+#define SIM_SCGC5_LPTMR_WIDTH                    1
+#define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_PORTA_MASK                     0x200u
+#define SIM_SCGC5_PORTA_SHIFT                    9
+#define SIM_SCGC5_PORTA_WIDTH                    1
+#define SIM_SCGC5_PORTA(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK                     0x400u
+#define SIM_SCGC5_PORTB_SHIFT                    10
+#define SIM_SCGC5_PORTB_WIDTH                    1
+#define SIM_SCGC5_PORTB(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK                     0x800u
+#define SIM_SCGC5_PORTC_SHIFT                    11
+#define SIM_SCGC5_PORTC_WIDTH                    1
+#define SIM_SCGC5_PORTC(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK                     0x1000u
+#define SIM_SCGC5_PORTD_SHIFT                    12
+#define SIM_SCGC5_PORTD_WIDTH                    1
+#define SIM_SCGC5_PORTD(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK                     0x2000u
+#define SIM_SCGC5_PORTE_SHIFT                    13
+#define SIM_SCGC5_PORTE_WIDTH                    1
+#define SIM_SCGC5_PORTE(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK                       0x1u
+#define SIM_SCGC6_FTF_SHIFT                      0
+#define SIM_SCGC6_FTF_WIDTH                      1
+#define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK                    0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT                   1
+#define SIM_SCGC6_DMAMUX_WIDTH                   1
+#define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_FLEXCAN0_MASK                  0x10u
+#define SIM_SCGC6_FLEXCAN0_SHIFT                 4
+#define SIM_SCGC6_FLEXCAN0_WIDTH                 1
+#define SIM_SCGC6_FLEXCAN0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FLEXCAN0_SHIFT))&SIM_SCGC6_FLEXCAN0_MASK)
+#define SIM_SCGC6_RNGA_MASK                      0x200u
+#define SIM_SCGC6_RNGA_SHIFT                     9
+#define SIM_SCGC6_RNGA_WIDTH                     1
+#define SIM_SCGC6_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RNGA_SHIFT))&SIM_SCGC6_RNGA_MASK)
+#define SIM_SCGC6_SPI0_MASK                      0x1000u
+#define SIM_SCGC6_SPI0_SHIFT                     12
+#define SIM_SCGC6_SPI0_WIDTH                     1
+#define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI0_SHIFT))&SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK                      0x2000u
+#define SIM_SCGC6_SPI1_SHIFT                     13
+#define SIM_SCGC6_SPI1_WIDTH                     1
+#define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI1_SHIFT))&SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_I2S_MASK                       0x8000u
+#define SIM_SCGC6_I2S_SHIFT                      15
+#define SIM_SCGC6_I2S_WIDTH                      1
+#define SIM_SCGC6_I2S(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S_SHIFT))&SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK                       0x40000u
+#define SIM_SCGC6_CRC_SHIFT                      18
+#define SIM_SCGC6_CRC_WIDTH                      1
+#define SIM_SCGC6_CRC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_CRC_SHIFT))&SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_USBDCD_MASK                    0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT                   21
+#define SIM_SCGC6_USBDCD_WIDTH                   1
+#define SIM_SCGC6_USBDCD(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_USBDCD_SHIFT))&SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_PDB_MASK                       0x400000u
+#define SIM_SCGC6_PDB_SHIFT                      22
+#define SIM_SCGC6_PDB_WIDTH                      1
+#define SIM_SCGC6_PDB(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PDB_SHIFT))&SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK                       0x800000u
+#define SIM_SCGC6_PIT_SHIFT                      23
+#define SIM_SCGC6_PIT_WIDTH                      1
+#define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK                      0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT                     24
+#define SIM_SCGC6_FTM0_WIDTH                     1
+#define SIM_SCGC6_FTM0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM0_SHIFT))&SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK                      0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT                     25
+#define SIM_SCGC6_FTM1_WIDTH                     1
+#define SIM_SCGC6_FTM1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM1_SHIFT))&SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM2_MASK                      0x4000000u
+#define SIM_SCGC6_FTM2_SHIFT                     26
+#define SIM_SCGC6_FTM2_WIDTH                     1
+#define SIM_SCGC6_FTM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM2_SHIFT))&SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_ADC0_MASK                      0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT                     27
+#define SIM_SCGC6_ADC0_WIDTH                     1
+#define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK                       0x20000000u
+#define SIM_SCGC6_RTC_SHIFT                      29
+#define SIM_SCGC6_RTC_WIDTH                      1
+#define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK                      0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT                     31
+#define SIM_SCGC6_DAC0_WIDTH                     1
+#define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_FLEXBUS_MASK                   0x1u
+#define SIM_SCGC7_FLEXBUS_SHIFT                  0
+#define SIM_SCGC7_FLEXBUS_WIDTH                  1
+#define SIM_SCGC7_FLEXBUS(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_FLEXBUS_SHIFT))&SIM_SCGC7_FLEXBUS_MASK)
+#define SIM_SCGC7_DMA_MASK                       0x2u
+#define SIM_SCGC7_DMA_SHIFT                      1
+#define SIM_SCGC7_DMA_WIDTH                      1
+#define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_MPU_MASK                       0x4u
+#define SIM_SCGC7_MPU_SHIFT                      2
+#define SIM_SCGC7_MPU_WIDTH                      1
+#define SIM_SCGC7_MPU(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_MPU_SHIFT))&SIM_SCGC7_MPU_MASK)
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
+#define SIM_CLKDIV1_OUTDIV4_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK                 0xF00000u
+#define SIM_CLKDIV1_OUTDIV3_SHIFT                20
+#define SIM_CLKDIV1_OUTDIV3_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV3(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK                 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT                24
+#define SIM_CLKDIV1_OUTDIV2_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
+#define SIM_CLKDIV1_OUTDIV1_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK                 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT                0
+#define SIM_CLKDIV2_USBFRAC_WIDTH                1
+#define SIM_CLKDIV2_USBFRAC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBFRAC_SHIFT))&SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK                  0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT                 1
+#define SIM_CLKDIV2_USBDIV_WIDTH                 3
+#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK                  0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT                 0
+#define SIM_FCFG1_FLASHDIS_WIDTH                 1
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT                1
+#define SIM_FCFG1_FLASHDOZE_WIDTH                1
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_DEPART_MASK                    0xF00u
+#define SIM_FCFG1_DEPART_SHIFT                   8
+#define SIM_FCFG1_DEPART_WIDTH                   4
+#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK                    0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT                   16
+#define SIM_FCFG1_EESIZE_WIDTH                   4
+#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT                   24
+#define SIM_FCFG1_PFSIZE_WIDTH                   4
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK                   0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT                  28
+#define SIM_FCFG1_NVMSIZE_WIDTH                  4
+#define SIM_FCFG1_NVMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK                  0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT                 16
+#define SIM_FCFG2_MAXADDR1_WIDTH                 7
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK                     0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT                    23
+#define SIM_FCFG2_PFLSH_WIDTH                    1
+#define SIM_FCFG2_PFLSH(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_PFLSH_SHIFT))&SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK                  0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT                 24
+#define SIM_FCFG2_MAXADDR0_WIDTH                 7
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT                       0
+#define SIM_UIDH_UID_WIDTH                       32
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT                      0
+#define SIM_UIDMH_UID_WIDTH                      32
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT                      0
+#define SIM_UIDML_UID_WIDTH                      32
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT                       0
+#define SIM_UIDL_UID_WIDTH                       32
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR                             (SIM)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1                                SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG                             SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2                                SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4                                SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5                                SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7                                SIM_SOPT7_REG(SIM)
+#define SIM_SDID                                 SIM_SDID_REG(SIM)
+#define SIM_SCGC1                                SIM_SCGC1_REG(SIM)
+#define SIM_SCGC2                                SIM_SCGC2_REG(SIM)
+#define SIM_SCGC3                                SIM_SCGC3_REG(SIM)
+#define SIM_SCGC4                                SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5                                SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6                                SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7                                SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1                              SIM_CLKDIV1_REG(SIM)
+#define SIM_CLKDIV2                              SIM_CLKDIV2_REG(SIM)
+#define SIM_FCFG1                                SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2                                SIM_FCFG2_REG(SIM)
+#define SIM_UIDH                                 SIM_UIDH_REG(SIM)
+#define SIM_UIDMH                                SIM_UIDMH_REG(SIM)
+#define SIM_UIDML                                SIM_UIDML_REG(SIM)
+#define SIM_UIDL                                 SIM_UIDL_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t VLLSCTRL;                           /**< VLLS Control register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base)                     ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base)                     ((base)->PMCTRL)
+#define SMC_VLLSCTRL_REG(base)                   ((base)->VLLSCTRL)
+#define SMC_PMSTAT_REG(base)                     ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK                    0x2u
+#define SMC_PMPROT_AVLLS_SHIFT                   1
+#define SMC_PMPROT_AVLLS_WIDTH                   1
+#define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK                     0x8u
+#define SMC_PMPROT_ALLS_SHIFT                    3
+#define SMC_PMPROT_ALLS_WIDTH                    1
+#define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK                     0x20u
+#define SMC_PMPROT_AVLP_SHIFT                    5
+#define SMC_PMPROT_AVLP_WIDTH                    1
+#define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK                    0x7u
+#define SMC_PMCTRL_STOPM_SHIFT                   0
+#define SMC_PMCTRL_STOPM_WIDTH                   3
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK                    0x8u
+#define SMC_PMCTRL_STOPA_SHIFT                   3
+#define SMC_PMCTRL_STOPA_WIDTH                   1
+#define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK                     0x60u
+#define SMC_PMCTRL_RUNM_SHIFT                    5
+#define SMC_PMCTRL_RUNM_WIDTH                    2
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK                    0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT                   7
+#define SMC_PMCTRL_LPWUI_WIDTH                   1
+#define SMC_PMCTRL_LPWUI(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_LPWUI_SHIFT))&SMC_PMCTRL_LPWUI_MASK)
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK                  0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT                 0
+#define SMC_VLLSCTRL_VLLSM_WIDTH                 3
+#define SMC_VLLSCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK                  0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT                 5
+#define SMC_VLLSCTRL_PORPO_WIDTH                 1
+#define SMC_VLLSCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_PORPO_SHIFT))&SMC_VLLSCTRL_PORPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK                   0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT                  0
+#define SMC_PMSTAT_PMSTAT_WIDTH                  7
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR                             (SMC)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC }
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT                               SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL                               SMC_PMCTRL_REG(SMC)
+#define SMC_VLLSCTRL                             SMC_VLLSCTRL_REG(SMC)
+#define SMC_PMSTAT                               SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+    __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+  };
+       uint8_t RESERVED_1[24];
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
+  __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+  union {                                          /* offset: 0x34 */
+    __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+    __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+  };
+  __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
+  __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
+  __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
+  __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
+  __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
+       uint8_t RESERVED_2[48];
+  __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
+  __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
+  __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
+  __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_MCR_REG(base)                        ((base)->MCR)
+#define SPI_TCR_REG(base)                        ((base)->TCR)
+#define SPI_CTAR_REG(base,index2)                ((base)->CTAR[index2])
+#define SPI_CTAR_COUNT                           2
+#define SPI_CTAR_SLAVE_REG(base,index2)          ((base)->CTAR_SLAVE[index2])
+#define SPI_CTAR_SLAVE_COUNT                     1
+#define SPI_SR_REG(base)                         ((base)->SR)
+#define SPI_RSER_REG(base)                       ((base)->RSER)
+#define SPI_PUSHR_REG(base)                      ((base)->PUSHR)
+#define SPI_PUSHR_SLAVE_REG(base)                ((base)->PUSHR_SLAVE)
+#define SPI_POPR_REG(base)                       ((base)->POPR)
+#define SPI_TXFR0_REG(base)                      ((base)->TXFR0)
+#define SPI_TXFR1_REG(base)                      ((base)->TXFR1)
+#define SPI_TXFR2_REG(base)                      ((base)->TXFR2)
+#define SPI_TXFR3_REG(base)                      ((base)->TXFR3)
+#define SPI_RXFR0_REG(base)                      ((base)->RXFR0)
+#define SPI_RXFR1_REG(base)                      ((base)->RXFR1)
+#define SPI_RXFR2_REG(base)                      ((base)->RXFR2)
+#define SPI_RXFR3_REG(base)                      ((base)->RXFR3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK                        0x1u
+#define SPI_MCR_HALT_SHIFT                       0
+#define SPI_MCR_HALT_WIDTH                       1
+#define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_HALT_SHIFT))&SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK                     0x300u
+#define SPI_MCR_SMPL_PT_SHIFT                    8
+#define SPI_MCR_SMPL_PT_WIDTH                    2
+#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK                     0x400u
+#define SPI_MCR_CLR_RXF_SHIFT                    10
+#define SPI_MCR_CLR_RXF_WIDTH                    1
+#define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_RXF_SHIFT))&SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK                     0x800u
+#define SPI_MCR_CLR_TXF_SHIFT                    11
+#define SPI_MCR_CLR_TXF_WIDTH                    1
+#define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_TXF_SHIFT))&SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK                     0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT                    12
+#define SPI_MCR_DIS_RXF_WIDTH                    1
+#define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_RXF_SHIFT))&SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK                     0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT                    13
+#define SPI_MCR_DIS_TXF_WIDTH                    1
+#define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_TXF_SHIFT))&SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK                        0x4000u
+#define SPI_MCR_MDIS_SHIFT                       14
+#define SPI_MCR_MDIS_WIDTH                       1
+#define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MDIS_SHIFT))&SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK                        0x8000u
+#define SPI_MCR_DOZE_SHIFT                       15
+#define SPI_MCR_DOZE_WIDTH                       1
+#define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DOZE_SHIFT))&SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK                       0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT                      16
+#define SPI_MCR_PCSIS_WIDTH                      6
+#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK                        0x1000000u
+#define SPI_MCR_ROOE_SHIFT                       24
+#define SPI_MCR_ROOE_WIDTH                       1
+#define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_ROOE_SHIFT))&SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK                       0x2000000u
+#define SPI_MCR_PCSSE_SHIFT                      25
+#define SPI_MCR_PCSSE_WIDTH                      1
+#define SPI_MCR_PCSSE(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSSE_SHIFT))&SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK                        0x4000000u
+#define SPI_MCR_MTFE_SHIFT                       26
+#define SPI_MCR_MTFE_WIDTH                       1
+#define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MTFE_SHIFT))&SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK                         0x8000000u
+#define SPI_MCR_FRZ_SHIFT                        27
+#define SPI_MCR_FRZ_WIDTH                        1
+#define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_MCR_FRZ_SHIFT))&SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK                       0x30000000u
+#define SPI_MCR_DCONF_SHIFT                      28
+#define SPI_MCR_DCONF_WIDTH                      2
+#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK                   0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT                  30
+#define SPI_MCR_CONT_SCKE_WIDTH                  1
+#define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CONT_SCKE_SHIFT))&SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK                        0x80000000u
+#define SPI_MCR_MSTR_SHIFT                       31
+#define SPI_MCR_MSTR_WIDTH                       1
+#define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MSTR_SHIFT))&SPI_MCR_MSTR_MASK)
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK                    0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT                   16
+#define SPI_TCR_SPI_TCNT_WIDTH                   16
+#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK                         0xFu
+#define SPI_CTAR_BR_SHIFT                        0
+#define SPI_CTAR_BR_WIDTH                        4
+#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK                         0xF0u
+#define SPI_CTAR_DT_SHIFT                        4
+#define SPI_CTAR_DT_WIDTH                        4
+#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK                        0xF00u
+#define SPI_CTAR_ASC_SHIFT                       8
+#define SPI_CTAR_ASC_WIDTH                       4
+#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK                      0xF000u
+#define SPI_CTAR_CSSCK_SHIFT                     12
+#define SPI_CTAR_CSSCK_WIDTH                     4
+#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK                        0x30000u
+#define SPI_CTAR_PBR_SHIFT                       16
+#define SPI_CTAR_PBR_WIDTH                       2
+#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK                        0xC0000u
+#define SPI_CTAR_PDT_SHIFT                       18
+#define SPI_CTAR_PDT_WIDTH                       2
+#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK                       0x300000u
+#define SPI_CTAR_PASC_SHIFT                      20
+#define SPI_CTAR_PASC_WIDTH                      2
+#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK                     0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT                    22
+#define SPI_CTAR_PCSSCK_WIDTH                    2
+#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK                      0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT                     24
+#define SPI_CTAR_LSBFE_WIDTH                     1
+#define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_LSBFE_SHIFT))&SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK                       0x2000000u
+#define SPI_CTAR_CPHA_SHIFT                      25
+#define SPI_CTAR_CPHA_WIDTH                      1
+#define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPHA_SHIFT))&SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK                       0x4000000u
+#define SPI_CTAR_CPOL_SHIFT                      26
+#define SPI_CTAR_CPOL_WIDTH                      1
+#define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPOL_SHIFT))&SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK                       0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT                      27
+#define SPI_CTAR_FMSZ_WIDTH                      4
+#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK                        0x80000000u
+#define SPI_CTAR_DBR_SHIFT                       31
+#define SPI_CTAR_DBR_WIDTH                       1
+#define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DBR_SHIFT))&SPI_CTAR_DBR_MASK)
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK                 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT                25
+#define SPI_CTAR_SLAVE_CPHA_WIDTH                1
+#define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPHA_SHIFT))&SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK                 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT                26
+#define SPI_CTAR_SLAVE_CPOL_WIDTH                1
+#define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPOL_SHIFT))&SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK                 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT                27
+#define SPI_CTAR_SLAVE_FMSZ_WIDTH                5
+#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK                    0xFu
+#define SPI_SR_POPNXTPTR_SHIFT                   0
+#define SPI_SR_POPNXTPTR_WIDTH                   4
+#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK                        0xF0u
+#define SPI_SR_RXCTR_SHIFT                       4
+#define SPI_SR_RXCTR_WIDTH                       4
+#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK                     0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT                    8
+#define SPI_SR_TXNXTPTR_WIDTH                    4
+#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK                        0xF000u
+#define SPI_SR_TXCTR_SHIFT                       12
+#define SPI_SR_TXCTR_WIDTH                       4
+#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK                         0x20000u
+#define SPI_SR_RFDF_SHIFT                        17
+#define SPI_SR_RFDF_WIDTH                        1
+#define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFDF_SHIFT))&SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK                         0x80000u
+#define SPI_SR_RFOF_SHIFT                        19
+#define SPI_SR_RFOF_WIDTH                        1
+#define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFOF_SHIFT))&SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK                         0x2000000u
+#define SPI_SR_TFFF_SHIFT                        25
+#define SPI_SR_TFFF_WIDTH                        1
+#define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK                         0x8000000u
+#define SPI_SR_TFUF_SHIFT                        27
+#define SPI_SR_TFUF_WIDTH                        1
+#define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFUF_SHIFT))&SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK                         0x10000000u
+#define SPI_SR_EOQF_SHIFT                        28
+#define SPI_SR_EOQF_WIDTH                        1
+#define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_EOQF_SHIFT))&SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK                        0x40000000u
+#define SPI_SR_TXRXS_SHIFT                       30
+#define SPI_SR_TXRXS_WIDTH                       1
+#define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXRXS_SHIFT))&SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK                          0x80000000u
+#define SPI_SR_TCF_SHIFT                         31
+#define SPI_SR_TCF_WIDTH                         1
+#define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x))<<SPI_SR_TCF_SHIFT))&SPI_SR_TCF_MASK)
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK                  0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT                 16
+#define SPI_RSER_RFDF_DIRS_WIDTH                 1
+#define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_DIRS_SHIFT))&SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK                    0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT                   17
+#define SPI_RSER_RFDF_RE_WIDTH                   1
+#define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_RE_SHIFT))&SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK                    0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT                   19
+#define SPI_RSER_RFOF_RE_WIDTH                   1
+#define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFOF_RE_SHIFT))&SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK                  0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT                 24
+#define SPI_RSER_TFFF_DIRS_WIDTH                 1
+#define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_DIRS_SHIFT))&SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK                    0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT                   25
+#define SPI_RSER_TFFF_RE_WIDTH                   1
+#define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK                    0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT                   27
+#define SPI_RSER_TFUF_RE_WIDTH                   1
+#define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFUF_RE_SHIFT))&SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK                    0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT                   28
+#define SPI_RSER_EOQF_RE_WIDTH                   1
+#define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_EOQF_RE_SHIFT))&SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK                     0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT                    31
+#define SPI_RSER_TCF_RE_WIDTH                    1
+#define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TCF_RE_SHIFT))&SPI_RSER_TCF_RE_MASK)
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK                    0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT                   0
+#define SPI_PUSHR_TXDATA_WIDTH                   16
+#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK                       0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT                      16
+#define SPI_PUSHR_PCS_WIDTH                      6
+#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK                     0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT                    26
+#define SPI_PUSHR_CTCNT_WIDTH                    1
+#define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTCNT_SHIFT))&SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK                       0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT                      27
+#define SPI_PUSHR_EOQ_WIDTH                      1
+#define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_EOQ_SHIFT))&SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK                      0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT                     28
+#define SPI_PUSHR_CTAS_WIDTH                     3
+#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK                      0x80000000u
+#define SPI_PUSHR_CONT_SHIFT                     31
+#define SPI_PUSHR_CONT_WIDTH                     1
+#define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CONT_SHIFT))&SPI_PUSHR_CONT_MASK)
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK              0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             0
+#define SPI_PUSHR_SLAVE_TXDATA_WIDTH             32
+#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK                     0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT                    0
+#define SPI_POPR_RXDATA_WIDTH                    32
+#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT                   0
+#define SPI_TXFR0_TXDATA_WIDTH                   16
+#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR0_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT                   0
+#define SPI_TXFR1_TXDATA_WIDTH                   16
+#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR1_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT                   0
+#define SPI_TXFR2_TXDATA_WIDTH                   16
+#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR2_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT                   0
+#define SPI_TXFR3_TXDATA_WIDTH                   16
+#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR3_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT                   0
+#define SPI_RXFR0_RXDATA_WIDTH                   32
+#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT                   0
+#define SPI_RXFR1_RXDATA_WIDTH                   32
+#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT                   0
+#define SPI_RXFR2_RXDATA_WIDTH                   32
+#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT                   0
+#define SPI_RXFR3_RXDATA_WIDTH                   32
+#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR                            (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR                            (SPI1)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x400AC000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+#define SPI2_BASE_PTR                            (SPI2)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_MCR                                 SPI_MCR_REG(SPI0)
+#define SPI0_TCR                                 SPI_TCR_REG(SPI0)
+#define SPI0_CTAR0                               SPI_CTAR_REG(SPI0,0)
+#define SPI0_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI0,0)
+#define SPI0_CTAR1                               SPI_CTAR_REG(SPI0,1)
+#define SPI0_SR                                  SPI_SR_REG(SPI0)
+#define SPI0_RSER                                SPI_RSER_REG(SPI0)
+#define SPI0_PUSHR                               SPI_PUSHR_REG(SPI0)
+#define SPI0_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI0)
+#define SPI0_POPR                                SPI_POPR_REG(SPI0)
+#define SPI0_TXFR0                               SPI_TXFR0_REG(SPI0)
+#define SPI0_TXFR1                               SPI_TXFR1_REG(SPI0)
+#define SPI0_TXFR2                               SPI_TXFR2_REG(SPI0)
+#define SPI0_TXFR3                               SPI_TXFR3_REG(SPI0)
+#define SPI0_RXFR0                               SPI_RXFR0_REG(SPI0)
+#define SPI0_RXFR1                               SPI_RXFR1_REG(SPI0)
+#define SPI0_RXFR2                               SPI_RXFR2_REG(SPI0)
+#define SPI0_RXFR3                               SPI_RXFR3_REG(SPI0)
+/* SPI1 */
+#define SPI1_MCR                                 SPI_MCR_REG(SPI1)
+#define SPI1_TCR                                 SPI_TCR_REG(SPI1)
+#define SPI1_CTAR0                               SPI_CTAR_REG(SPI1,0)
+#define SPI1_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI1,0)
+#define SPI1_CTAR1                               SPI_CTAR_REG(SPI1,1)
+#define SPI1_SR                                  SPI_SR_REG(SPI1)
+#define SPI1_RSER                                SPI_RSER_REG(SPI1)
+#define SPI1_PUSHR                               SPI_PUSHR_REG(SPI1)
+#define SPI1_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI1)
+#define SPI1_POPR                                SPI_POPR_REG(SPI1)
+#define SPI1_TXFR0                               SPI_TXFR0_REG(SPI1)
+#define SPI1_TXFR1                               SPI_TXFR1_REG(SPI1)
+#define SPI1_TXFR2                               SPI_TXFR2_REG(SPI1)
+#define SPI1_TXFR3                               SPI_TXFR3_REG(SPI1)
+#define SPI1_RXFR0                               SPI_RXFR0_REG(SPI1)
+#define SPI1_RXFR1                               SPI_RXFR1_REG(SPI1)
+#define SPI1_RXFR2                               SPI_RXFR2_REG(SPI1)
+#define SPI1_RXFR3                               SPI_RXFR3_REG(SPI1)
+/* SPI2 */
+#define SPI2_MCR                                 SPI_MCR_REG(SPI2)
+#define SPI2_TCR                                 SPI_TCR_REG(SPI2)
+#define SPI2_CTAR0                               SPI_CTAR_REG(SPI2,0)
+#define SPI2_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI2,0)
+#define SPI2_CTAR1                               SPI_CTAR_REG(SPI2,1)
+#define SPI2_SR                                  SPI_SR_REG(SPI2)
+#define SPI2_RSER                                SPI_RSER_REG(SPI2)
+#define SPI2_PUSHR                               SPI_PUSHR_REG(SPI2)
+#define SPI2_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI2)
+#define SPI2_POPR                                SPI_POPR_REG(SPI2)
+#define SPI2_TXFR0                               SPI_TXFR0_REG(SPI2)
+#define SPI2_TXFR1                               SPI_TXFR1_REG(SPI2)
+#define SPI2_TXFR2                               SPI_TXFR2_REG(SPI2)
+#define SPI2_TXFR3                               SPI_TXFR3_REG(SPI2)
+#define SPI2_RXFR0                               SPI_RXFR0_REG(SPI2)
+#define SPI2_RXFR1                               SPI_RXFR1_REG(SPI2)
+#define SPI2_RXFR2                               SPI_RXFR2_REG(SPI2)
+#define SPI2_RXFR3                               SPI_RXFR3_REG(SPI2)
+
+/* SPI - Register array accessors */
+#define SPI0_CTAR(index2)                        SPI_CTAR_REG(SPI0,index2)
+#define SPI1_CTAR(index2)                        SPI_CTAR_REG(SPI1,index2)
+#define SPI2_CTAR(index2)                        SPI_CTAR_REG(SPI2,index2)
+#define SPI0_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI0,index2)
+#define SPI1_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI1,index2)
+#define SPI2_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI2,index2)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
+  __I  uint8_t ED;                                 /**< UART Extended Data Register, offset: 0xC */
+  __IO uint8_t MODEM;                              /**< UART Modem Register, offset: 0xD */
+  __IO uint8_t IR;                                 /**< UART Infrared Register, offset: 0xE */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t PFIFO;                              /**< UART FIFO Parameters, offset: 0x10 */
+  __IO uint8_t CFIFO;                              /**< UART FIFO Control Register, offset: 0x11 */
+  __IO uint8_t SFIFO;                              /**< UART FIFO Status Register, offset: 0x12 */
+  __IO uint8_t TWFIFO;                             /**< UART FIFO Transmit Watermark, offset: 0x13 */
+  __I  uint8_t TCFIFO;                             /**< UART FIFO Transmit Count, offset: 0x14 */
+  __IO uint8_t RWFIFO;                             /**< UART FIFO Receive Watermark, offset: 0x15 */
+  __I  uint8_t RCFIFO;                             /**< UART FIFO Receive Count, offset: 0x16 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
+  __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+  __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+  union {                                          /* offset: 0x1B */
+    __IO uint8_t WP7816T0;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+    __IO uint8_t WP7816T1;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+  };
+  __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
+  __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
+  __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
+  __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base)                       ((base)->BDH)
+#define UART_BDL_REG(base)                       ((base)->BDL)
+#define UART_C1_REG(base)                        ((base)->C1)
+#define UART_C2_REG(base)                        ((base)->C2)
+#define UART_S1_REG(base)                        ((base)->S1)
+#define UART_S2_REG(base)                        ((base)->S2)
+#define UART_C3_REG(base)                        ((base)->C3)
+#define UART_D_REG(base)                         ((base)->D)
+#define UART_MA1_REG(base)                       ((base)->MA1)
+#define UART_MA2_REG(base)                       ((base)->MA2)
+#define UART_C4_REG(base)                        ((base)->C4)
+#define UART_C5_REG(base)                        ((base)->C5)
+#define UART_ED_REG(base)                        ((base)->ED)
+#define UART_MODEM_REG(base)                     ((base)->MODEM)
+#define UART_IR_REG(base)                        ((base)->IR)
+#define UART_PFIFO_REG(base)                     ((base)->PFIFO)
+#define UART_CFIFO_REG(base)                     ((base)->CFIFO)
+#define UART_SFIFO_REG(base)                     ((base)->SFIFO)
+#define UART_TWFIFO_REG(base)                    ((base)->TWFIFO)
+#define UART_TCFIFO_REG(base)                    ((base)->TCFIFO)
+#define UART_RWFIFO_REG(base)                    ((base)->RWFIFO)
+#define UART_RCFIFO_REG(base)                    ((base)->RCFIFO)
+#define UART_C7816_REG(base)                     ((base)->C7816)
+#define UART_IE7816_REG(base)                    ((base)->IE7816)
+#define UART_IS7816_REG(base)                    ((base)->IS7816)
+#define UART_WP7816T0_REG(base)                  ((base)->WP7816T0)
+#define UART_WP7816T1_REG(base)                  ((base)->WP7816T1)
+#define UART_WN7816_REG(base)                    ((base)->WN7816)
+#define UART_WF7816_REG(base)                    ((base)->WF7816)
+#define UART_ET7816_REG(base)                    ((base)->ET7816)
+#define UART_TL7816_REG(base)                    ((base)->TL7816)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK                        0x1Fu
+#define UART_BDH_SBR_SHIFT                       0
+#define UART_BDH_SBR_WIDTH                       5
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK                       0x20u
+#define UART_BDH_SBNS_SHIFT                      5
+#define UART_BDH_SBNS_WIDTH                      1
+#define UART_BDH_SBNS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBNS_SHIFT))&UART_BDH_SBNS_MASK)
+#define UART_BDH_RXEDGIE_MASK                    0x40u
+#define UART_BDH_RXEDGIE_SHIFT                   6
+#define UART_BDH_RXEDGIE_WIDTH                   1
+#define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK                     0x80u
+#define UART_BDH_LBKDIE_SHIFT                    7
+#define UART_BDH_LBKDIE_WIDTH                    1
+#define UART_BDH_LBKDIE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_BDH_LBKDIE_SHIFT))&UART_BDH_LBKDIE_MASK)
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK                        0xFFu
+#define UART_BDL_SBR_SHIFT                       0
+#define UART_BDL_SBR_WIDTH                       8
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK                          0x1u
+#define UART_C1_PT_SHIFT                         0
+#define UART_C1_PT_WIDTH                         1
+#define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
+#define UART_C1_PE_MASK                          0x2u
+#define UART_C1_PE_SHIFT                         1
+#define UART_C1_PE_WIDTH                         1
+#define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK                         0x4u
+#define UART_C1_ILT_SHIFT                        2
+#define UART_C1_ILT_WIDTH                        1
+#define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK                        0x8u
+#define UART_C1_WAKE_SHIFT                       3
+#define UART_C1_WAKE_WIDTH                       1
+#define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK                           0x10u
+#define UART_C1_M_SHIFT                          4
+#define UART_C1_M_WIDTH                          1
+#define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK                        0x20u
+#define UART_C1_RSRC_SHIFT                       5
+#define UART_C1_RSRC_WIDTH                       1
+#define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK                    0x40u
+#define UART_C1_UARTSWAI_SHIFT                   6
+#define UART_C1_UARTSWAI_WIDTH                   1
+#define UART_C1_UARTSWAI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C1_UARTSWAI_SHIFT))&UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK                       0x80u
+#define UART_C1_LOOPS_SHIFT                      7
+#define UART_C1_LOOPS_WIDTH                      1
+#define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK                         0x1u
+#define UART_C2_SBK_SHIFT                        0
+#define UART_C2_SBK_WIDTH                        1
+#define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK                         0x2u
+#define UART_C2_RWU_SHIFT                        1
+#define UART_C2_RWU_WIDTH                        1
+#define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK                          0x4u
+#define UART_C2_RE_SHIFT                         2
+#define UART_C2_RE_WIDTH                         1
+#define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
+#define UART_C2_TE_MASK                          0x8u
+#define UART_C2_TE_SHIFT                         3
+#define UART_C2_TE_WIDTH                         1
+#define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK                        0x10u
+#define UART_C2_ILIE_SHIFT                       4
+#define UART_C2_ILIE_WIDTH                       1
+#define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK                         0x20u
+#define UART_C2_RIE_SHIFT                        5
+#define UART_C2_RIE_WIDTH                        1
+#define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK                        0x40u
+#define UART_C2_TCIE_SHIFT                       6
+#define UART_C2_TCIE_WIDTH                       1
+#define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK                         0x80u
+#define UART_C2_TIE_SHIFT                        7
+#define UART_C2_TIE_WIDTH                        1
+#define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK                          0x1u
+#define UART_S1_PF_SHIFT                         0
+#define UART_S1_PF_WIDTH                         1
+#define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
+#define UART_S1_FE_MASK                          0x2u
+#define UART_S1_FE_SHIFT                         1
+#define UART_S1_FE_WIDTH                         1
+#define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
+#define UART_S1_NF_MASK                          0x4u
+#define UART_S1_NF_SHIFT                         2
+#define UART_S1_NF_WIDTH                         1
+#define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
+#define UART_S1_OR_MASK                          0x8u
+#define UART_S1_OR_SHIFT                         3
+#define UART_S1_OR_WIDTH                         1
+#define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK                        0x10u
+#define UART_S1_IDLE_SHIFT                       4
+#define UART_S1_IDLE_WIDTH                       1
+#define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK                        0x20u
+#define UART_S1_RDRF_SHIFT                       5
+#define UART_S1_RDRF_WIDTH                       1
+#define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK                          0x40u
+#define UART_S1_TC_SHIFT                         6
+#define UART_S1_TC_WIDTH                         1
+#define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK                        0x80u
+#define UART_S1_TDRE_SHIFT                       7
+#define UART_S1_TDRE_WIDTH                       1
+#define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK                         0x1u
+#define UART_S2_RAF_SHIFT                        0
+#define UART_S2_RAF_WIDTH                        1
+#define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK                       0x2u
+#define UART_S2_LBKDE_SHIFT                      1
+#define UART_S2_LBKDE_WIDTH                      1
+#define UART_S2_LBKDE(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDE_SHIFT))&UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK                       0x4u
+#define UART_S2_BRK13_SHIFT                      2
+#define UART_S2_BRK13_WIDTH                      1
+#define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK                       0x8u
+#define UART_S2_RWUID_SHIFT                      3
+#define UART_S2_RWUID_WIDTH                      1
+#define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK                       0x10u
+#define UART_S2_RXINV_SHIFT                      4
+#define UART_S2_RXINV_WIDTH                      1
+#define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK                        0x20u
+#define UART_S2_MSBF_SHIFT                       5
+#define UART_S2_MSBF_WIDTH                       1
+#define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S2_MSBF_SHIFT))&UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK                     0x40u
+#define UART_S2_RXEDGIF_SHIFT                    6
+#define UART_S2_RXEDGIF_WIDTH                    1
+#define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK                      0x80u
+#define UART_S2_LBKDIF_SHIFT                     7
+#define UART_S2_LBKDIF_WIDTH                     1
+#define UART_S2_LBKDIF(x)                        (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDIF_SHIFT))&UART_S2_LBKDIF_MASK)
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK                        0x1u
+#define UART_C3_PEIE_SHIFT                       0
+#define UART_C3_PEIE_WIDTH                       1
+#define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK                        0x2u
+#define UART_C3_FEIE_SHIFT                       1
+#define UART_C3_FEIE_WIDTH                       1
+#define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK                        0x4u
+#define UART_C3_NEIE_SHIFT                       2
+#define UART_C3_NEIE_WIDTH                       1
+#define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK                        0x8u
+#define UART_C3_ORIE_SHIFT                       3
+#define UART_C3_ORIE_WIDTH                       1
+#define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK                       0x10u
+#define UART_C3_TXINV_SHIFT                      4
+#define UART_C3_TXINV_WIDTH                      1
+#define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK                       0x20u
+#define UART_C3_TXDIR_SHIFT                      5
+#define UART_C3_TXDIR_WIDTH                      1
+#define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK                          0x40u
+#define UART_C3_T8_SHIFT                         6
+#define UART_C3_T8_WIDTH                         1
+#define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
+#define UART_C3_R8_MASK                          0x80u
+#define UART_C3_R8_SHIFT                         7
+#define UART_C3_R8_WIDTH                         1
+#define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
+/* D Bit Fields */
+#define UART_D_RT_MASK                           0xFFu
+#define UART_D_RT_SHIFT                          0
+#define UART_D_RT_WIDTH                          8
+#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK                         0xFFu
+#define UART_MA1_MA_SHIFT                        0
+#define UART_MA1_MA_WIDTH                        8
+#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK                         0xFFu
+#define UART_MA2_MA_SHIFT                        0
+#define UART_MA2_MA_WIDTH                        8
+#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK                        0x1Fu
+#define UART_C4_BRFA_SHIFT                       0
+#define UART_C4_BRFA_WIDTH                       5
+#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK                         0x20u
+#define UART_C4_M10_SHIFT                        5
+#define UART_C4_M10_WIDTH                        1
+#define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C4_M10_SHIFT))&UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK                       0x40u
+#define UART_C4_MAEN2_SHIFT                      6
+#define UART_C4_MAEN2_WIDTH                      1
+#define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN2_SHIFT))&UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK                       0x80u
+#define UART_C4_MAEN1_SHIFT                      7
+#define UART_C4_MAEN1_WIDTH                      1
+#define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN1_SHIFT))&UART_C4_MAEN1_MASK)
+/* C5 Bit Fields */
+#define UART_C5_LBKDDMAS_MASK                    0x8u
+#define UART_C5_LBKDDMAS_SHIFT                   3
+#define UART_C5_LBKDDMAS_WIDTH                   1
+#define UART_C5_LBKDDMAS(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C5_LBKDDMAS_SHIFT))&UART_C5_LBKDDMAS_MASK)
+#define UART_C5_ILDMAS_MASK                      0x10u
+#define UART_C5_ILDMAS_SHIFT                     4
+#define UART_C5_ILDMAS_WIDTH                     1
+#define UART_C5_ILDMAS(x)                        (((uint8_t)(((uint8_t)(x))<<UART_C5_ILDMAS_SHIFT))&UART_C5_ILDMAS_MASK)
+#define UART_C5_RDMAS_MASK                       0x20u
+#define UART_C5_RDMAS_SHIFT                      5
+#define UART_C5_RDMAS_WIDTH                      1
+#define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_RDMAS_SHIFT))&UART_C5_RDMAS_MASK)
+#define UART_C5_TCDMAS_MASK                      0x40u
+#define UART_C5_TCDMAS_SHIFT                     6
+#define UART_C5_TCDMAS_WIDTH                     1
+#define UART_C5_TCDMAS(x)                        (((uint8_t)(((uint8_t)(x))<<UART_C5_TCDMAS_SHIFT))&UART_C5_TCDMAS_MASK)
+#define UART_C5_TDMAS_MASK                       0x80u
+#define UART_C5_TDMAS_SHIFT                      7
+#define UART_C5_TDMAS_WIDTH                      1
+#define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_TDMAS_SHIFT))&UART_C5_TDMAS_MASK)
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK                     0x40u
+#define UART_ED_PARITYE_SHIFT                    6
+#define UART_ED_PARITYE_WIDTH                    1
+#define UART_ED_PARITYE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_ED_PARITYE_SHIFT))&UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK                       0x80u
+#define UART_ED_NOISY_SHIFT                      7
+#define UART_ED_NOISY_WIDTH                      1
+#define UART_ED_NOISY(x)                         (((uint8_t)(((uint8_t)(x))<<UART_ED_NOISY_SHIFT))&UART_ED_NOISY_MASK)
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK                   0x1u
+#define UART_MODEM_TXCTSE_SHIFT                  0
+#define UART_MODEM_TXCTSE_WIDTH                  1
+#define UART_MODEM_TXCTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXCTSE_SHIFT))&UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK                   0x2u
+#define UART_MODEM_TXRTSE_SHIFT                  1
+#define UART_MODEM_TXRTSE_WIDTH                  1
+#define UART_MODEM_TXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSE_SHIFT))&UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK                 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT                2
+#define UART_MODEM_TXRTSPOL_WIDTH                1
+#define UART_MODEM_TXRTSPOL(x)                   (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSPOL_SHIFT))&UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK                   0x8u
+#define UART_MODEM_RXRTSE_SHIFT                  3
+#define UART_MODEM_RXRTSE_WIDTH                  1
+#define UART_MODEM_RXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_RXRTSE_SHIFT))&UART_MODEM_RXRTSE_MASK)
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK                         0x3u
+#define UART_IR_TNP_SHIFT                        0
+#define UART_IR_TNP_WIDTH                        2
+#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK                        0x4u
+#define UART_IR_IREN_SHIFT                       2
+#define UART_IR_IREN_WIDTH                       1
+#define UART_IR_IREN(x)                          (((uint8_t)(((uint8_t)(x))<<UART_IR_IREN_SHIFT))&UART_IR_IREN_MASK)
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK               0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT              0
+#define UART_PFIFO_RXFIFOSIZE_WIDTH              3
+#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK                     0x8u
+#define UART_PFIFO_RXFE_SHIFT                    3
+#define UART_PFIFO_RXFE_WIDTH                    1
+#define UART_PFIFO_RXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFE_SHIFT))&UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK               0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT              4
+#define UART_PFIFO_TXFIFOSIZE_WIDTH              3
+#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK                     0x80u
+#define UART_PFIFO_TXFE_SHIFT                    7
+#define UART_PFIFO_TXFE_WIDTH                    1
+#define UART_PFIFO_TXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFE_SHIFT))&UART_PFIFO_TXFE_MASK)
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK                    0x1u
+#define UART_CFIFO_RXUFE_SHIFT                   0
+#define UART_CFIFO_RXUFE_WIDTH                   1
+#define UART_CFIFO_RXUFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXUFE_SHIFT))&UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK                    0x2u
+#define UART_CFIFO_TXOFE_SHIFT                   1
+#define UART_CFIFO_TXOFE_WIDTH                   1
+#define UART_CFIFO_TXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXOFE_SHIFT))&UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXOFE_MASK                    0x4u
+#define UART_CFIFO_RXOFE_SHIFT                   2
+#define UART_CFIFO_RXOFE_WIDTH                   1
+#define UART_CFIFO_RXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXOFE_SHIFT))&UART_CFIFO_RXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK                  0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT                 6
+#define UART_CFIFO_RXFLUSH_WIDTH                 1
+#define UART_CFIFO_RXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXFLUSH_SHIFT))&UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK                  0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT                 7
+#define UART_CFIFO_TXFLUSH_WIDTH                 1
+#define UART_CFIFO_TXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXFLUSH_SHIFT))&UART_CFIFO_TXFLUSH_MASK)
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK                     0x1u
+#define UART_SFIFO_RXUF_SHIFT                    0
+#define UART_SFIFO_RXUF_WIDTH                    1
+#define UART_SFIFO_RXUF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXUF_SHIFT))&UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK                     0x2u
+#define UART_SFIFO_TXOF_SHIFT                    1
+#define UART_SFIFO_TXOF_WIDTH                    1
+#define UART_SFIFO_TXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXOF_SHIFT))&UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXOF_MASK                     0x4u
+#define UART_SFIFO_RXOF_SHIFT                    2
+#define UART_SFIFO_RXOF_WIDTH                    1
+#define UART_SFIFO_RXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXOF_SHIFT))&UART_SFIFO_RXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK                   0x40u
+#define UART_SFIFO_RXEMPT_SHIFT                  6
+#define UART_SFIFO_RXEMPT_WIDTH                  1
+#define UART_SFIFO_RXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXEMPT_SHIFT))&UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK                   0x80u
+#define UART_SFIFO_TXEMPT_SHIFT                  7
+#define UART_SFIFO_TXEMPT_WIDTH                  1
+#define UART_SFIFO_TXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXEMPT_SHIFT))&UART_SFIFO_TXEMPT_MASK)
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK                 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT                0
+#define UART_TWFIFO_TXWATER_WIDTH                8
+#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK                 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT                0
+#define UART_TCFIFO_TXCOUNT_WIDTH                8
+#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK                 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT                0
+#define UART_RWFIFO_RXWATER_WIDTH                8
+#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK                 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT                0
+#define UART_RCFIFO_RXCOUNT_WIDTH                8
+#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK                0x1u
+#define UART_C7816_ISO_7816E_SHIFT               0
+#define UART_C7816_ISO_7816E_WIDTH               1
+#define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x))<<UART_C7816_ISO_7816E_SHIFT))&UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK                    0x2u
+#define UART_C7816_TTYPE_SHIFT                   1
+#define UART_C7816_TTYPE_WIDTH                   1
+#define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_TTYPE_SHIFT))&UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK                     0x4u
+#define UART_C7816_INIT_SHIFT                    2
+#define UART_C7816_INIT_WIDTH                    1
+#define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_C7816_INIT_SHIFT))&UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK                    0x8u
+#define UART_C7816_ANACK_SHIFT                   3
+#define UART_C7816_ANACK_WIDTH                   1
+#define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ANACK_SHIFT))&UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK                    0x10u
+#define UART_C7816_ONACK_SHIFT                   4
+#define UART_C7816_ONACK_WIDTH                   1
+#define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ONACK_SHIFT))&UART_C7816_ONACK_MASK)
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK                    0x1u
+#define UART_IE7816_RXTE_SHIFT                   0
+#define UART_IE7816_RXTE_WIDTH                   1
+#define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_RXTE_SHIFT))&UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK                    0x2u
+#define UART_IE7816_TXTE_SHIFT                   1
+#define UART_IE7816_TXTE_WIDTH                   1
+#define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_TXTE_SHIFT))&UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK                    0x4u
+#define UART_IE7816_GTVE_SHIFT                   2
+#define UART_IE7816_GTVE_WIDTH                   1
+#define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_GTVE_SHIFT))&UART_IE7816_GTVE_MASK)
+#define UART_IE7816_INITDE_MASK                  0x10u
+#define UART_IE7816_INITDE_SHIFT                 4
+#define UART_IE7816_INITDE_WIDTH                 1
+#define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x))<<UART_IE7816_INITDE_SHIFT))&UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK                    0x20u
+#define UART_IE7816_BWTE_SHIFT                   5
+#define UART_IE7816_BWTE_WIDTH                   1
+#define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_BWTE_SHIFT))&UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK                    0x40u
+#define UART_IE7816_CWTE_SHIFT                   6
+#define UART_IE7816_CWTE_WIDTH                   1
+#define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_CWTE_SHIFT))&UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK                     0x80u
+#define UART_IE7816_WTE_SHIFT                    7
+#define UART_IE7816_WTE_WIDTH                    1
+#define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IE7816_WTE_SHIFT))&UART_IE7816_WTE_MASK)
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK                     0x1u
+#define UART_IS7816_RXT_SHIFT                    0
+#define UART_IS7816_RXT_WIDTH                    1
+#define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_RXT_SHIFT))&UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK                     0x2u
+#define UART_IS7816_TXT_SHIFT                    1
+#define UART_IS7816_TXT_WIDTH                    1
+#define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_TXT_SHIFT))&UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK                     0x4u
+#define UART_IS7816_GTV_SHIFT                    2
+#define UART_IS7816_GTV_WIDTH                    1
+#define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_GTV_SHIFT))&UART_IS7816_GTV_MASK)
+#define UART_IS7816_INITD_MASK                   0x10u
+#define UART_IS7816_INITD_SHIFT                  4
+#define UART_IS7816_INITD_WIDTH                  1
+#define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x))<<UART_IS7816_INITD_SHIFT))&UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK                     0x20u
+#define UART_IS7816_BWT_SHIFT                    5
+#define UART_IS7816_BWT_WIDTH                    1
+#define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_BWT_SHIFT))&UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK                     0x40u
+#define UART_IS7816_CWT_SHIFT                    6
+#define UART_IS7816_CWT_WIDTH                    1
+#define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_CWT_SHIFT))&UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK                      0x80u
+#define UART_IS7816_WT_SHIFT                     7
+#define UART_IS7816_WT_WIDTH                     1
+#define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x))<<UART_IS7816_WT_SHIFT))&UART_IS7816_WT_MASK)
+/* WP7816T0 Bit Fields */
+#define UART_WP7816T0_WI_MASK                    0xFFu
+#define UART_WP7816T0_WI_SHIFT                   0
+#define UART_WP7816T0_WI_WIDTH                   8
+#define UART_WP7816T0_WI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
+/* WP7816T1 Bit Fields */
+#define UART_WP7816T1_BWI_MASK                   0xFu
+#define UART_WP7816T1_BWI_SHIFT                  0
+#define UART_WP7816T1_BWI_WIDTH                  4
+#define UART_WP7816T1_BWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
+#define UART_WP7816T1_CWI_MASK                   0xF0u
+#define UART_WP7816T1_CWI_SHIFT                  4
+#define UART_WP7816T1_CWI_WIDTH                  4
+#define UART_WP7816T1_CWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK                     0xFFu
+#define UART_WN7816_GTN_SHIFT                    0
+#define UART_WN7816_GTN_WIDTH                    8
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK                    0xFFu
+#define UART_WF7816_GTFD_SHIFT                   0
+#define UART_WF7816_GTFD_WIDTH                   8
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK             0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT            0
+#define UART_ET7816_RXTHRESHOLD_WIDTH            4
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK             0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT            4
+#define UART_ET7816_TXTHRESHOLD_WIDTH            4
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK                    0xFFu
+#define UART_TL7816_TLEN_SHIFT                   0
+#define UART_TL7816_TLEN_WIDTH                   8
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0                                    ((UART_Type *)UART0_BASE)
+#define UART0_BASE_PTR                           (UART0)
+/** Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1                                    ((UART_Type *)UART1_BASE)
+#define UART1_BASE_PTR                           (UART1)
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR                           (UART2)
+/** Peripheral UART3 base address */
+#define UART3_BASE                               (0x4006D000u)
+/** Peripheral UART3 base pointer */
+#define UART3                                    ((UART_Type *)UART3_BASE)
+#define UART3_BASE_PTR                           (UART3)
+/** Peripheral UART4 base address */
+#define UART4_BASE                               (0x400EA000u)
+/** Peripheral UART4 base pointer */
+#define UART4                                    ((UART_Type *)UART4_BASE)
+#define UART4_BASE_PTR                           (UART4)
+/** Peripheral UART5 base address */
+#define UART5_BASE                               (0x400EB000u)
+/** Peripheral UART5 base pointer */
+#define UART5                                    ((UART_Type *)UART5_BASE)
+#define UART5_BASE_PTR                           (UART5)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS                           { UART0, UART1, UART2, UART3, UART4, UART5 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS                          { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
+#define UART_ERR_IRQS                            { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
+#define UART_LON_IRQS                            { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART0 */
+#define UART0_BDH                                UART_BDH_REG(UART0)
+#define UART0_BDL                                UART_BDL_REG(UART0)
+#define UART0_C1                                 UART_C1_REG(UART0)
+#define UART0_C2                                 UART_C2_REG(UART0)
+#define UART0_S1                                 UART_S1_REG(UART0)
+#define UART0_S2                                 UART_S2_REG(UART0)
+#define UART0_C3                                 UART_C3_REG(UART0)
+#define UART0_D                                  UART_D_REG(UART0)
+#define UART0_MA1                                UART_MA1_REG(UART0)
+#define UART0_MA2                                UART_MA2_REG(UART0)
+#define UART0_C4                                 UART_C4_REG(UART0)
+#define UART0_C5                                 UART_C5_REG(UART0)
+#define UART0_ED                                 UART_ED_REG(UART0)
+#define UART0_MODEM                              UART_MODEM_REG(UART0)
+#define UART0_IR                                 UART_IR_REG(UART0)
+#define UART0_PFIFO                              UART_PFIFO_REG(UART0)
+#define UART0_CFIFO                              UART_CFIFO_REG(UART0)
+#define UART0_SFIFO                              UART_SFIFO_REG(UART0)
+#define UART0_TWFIFO                             UART_TWFIFO_REG(UART0)
+#define UART0_TCFIFO                             UART_TCFIFO_REG(UART0)
+#define UART0_RWFIFO                             UART_RWFIFO_REG(UART0)
+#define UART0_RCFIFO                             UART_RCFIFO_REG(UART0)
+#define UART0_C7816                              UART_C7816_REG(UART0)
+#define UART0_IE7816                             UART_IE7816_REG(UART0)
+#define UART0_IS7816                             UART_IS7816_REG(UART0)
+#define UART0_WP7816T0                           UART_WP7816T0_REG(UART0)
+#define UART0_WP7816T1                           UART_WP7816T1_REG(UART0)
+#define UART0_WN7816                             UART_WN7816_REG(UART0)
+#define UART0_WF7816                             UART_WF7816_REG(UART0)
+#define UART0_ET7816                             UART_ET7816_REG(UART0)
+#define UART0_TL7816                             UART_TL7816_REG(UART0)
+/* UART1 */
+#define UART1_BDH                                UART_BDH_REG(UART1)
+#define UART1_BDL                                UART_BDL_REG(UART1)
+#define UART1_C1                                 UART_C1_REG(UART1)
+#define UART1_C2                                 UART_C2_REG(UART1)
+#define UART1_S1                                 UART_S1_REG(UART1)
+#define UART1_S2                                 UART_S2_REG(UART1)
+#define UART1_C3                                 UART_C3_REG(UART1)
+#define UART1_D                                  UART_D_REG(UART1)
+#define UART1_MA1                                UART_MA1_REG(UART1)
+#define UART1_MA2                                UART_MA2_REG(UART1)
+#define UART1_C4                                 UART_C4_REG(UART1)
+#define UART1_C5                                 UART_C5_REG(UART1)
+#define UART1_ED                                 UART_ED_REG(UART1)
+#define UART1_MODEM                              UART_MODEM_REG(UART1)
+#define UART1_IR                                 UART_IR_REG(UART1)
+#define UART1_PFIFO                              UART_PFIFO_REG(UART1)
+#define UART1_CFIFO                              UART_CFIFO_REG(UART1)
+#define UART1_SFIFO                              UART_SFIFO_REG(UART1)
+#define UART1_TWFIFO                             UART_TWFIFO_REG(UART1)
+#define UART1_TCFIFO                             UART_TCFIFO_REG(UART1)
+#define UART1_RWFIFO                             UART_RWFIFO_REG(UART1)
+#define UART1_RCFIFO                             UART_RCFIFO_REG(UART1)
+/* UART2 */
+#define UART2_BDH                                UART_BDH_REG(UART2)
+#define UART2_BDL                                UART_BDL_REG(UART2)
+#define UART2_C1                                 UART_C1_REG(UART2)
+#define UART2_C2                                 UART_C2_REG(UART2)
+#define UART2_S1                                 UART_S1_REG(UART2)
+#define UART2_S2                                 UART_S2_REG(UART2)
+#define UART2_C3                                 UART_C3_REG(UART2)
+#define UART2_D                                  UART_D_REG(UART2)
+#define UART2_MA1                                UART_MA1_REG(UART2)
+#define UART2_MA2                                UART_MA2_REG(UART2)
+#define UART2_C4                                 UART_C4_REG(UART2)
+#define UART2_C5                                 UART_C5_REG(UART2)
+#define UART2_ED                                 UART_ED_REG(UART2)
+#define UART2_MODEM                              UART_MODEM_REG(UART2)
+#define UART2_IR                                 UART_IR_REG(UART2)
+#define UART2_PFIFO                              UART_PFIFO_REG(UART2)
+#define UART2_CFIFO                              UART_CFIFO_REG(UART2)
+#define UART2_SFIFO                              UART_SFIFO_REG(UART2)
+#define UART2_TWFIFO                             UART_TWFIFO_REG(UART2)
+#define UART2_TCFIFO                             UART_TCFIFO_REG(UART2)
+#define UART2_RWFIFO                             UART_RWFIFO_REG(UART2)
+#define UART2_RCFIFO                             UART_RCFIFO_REG(UART2)
+/* UART3 */
+#define UART3_BDH                                UART_BDH_REG(UART3)
+#define UART3_BDL                                UART_BDL_REG(UART3)
+#define UART3_C1                                 UART_C1_REG(UART3)
+#define UART3_C2                                 UART_C2_REG(UART3)
+#define UART3_S1                                 UART_S1_REG(UART3)
+#define UART3_S2                                 UART_S2_REG(UART3)
+#define UART3_C3                                 UART_C3_REG(UART3)
+#define UART3_D                                  UART_D_REG(UART3)
+#define UART3_MA1                                UART_MA1_REG(UART3)
+#define UART3_MA2                                UART_MA2_REG(UART3)
+#define UART3_C4                                 UART_C4_REG(UART3)
+#define UART3_C5                                 UART_C5_REG(UART3)
+#define UART3_ED                                 UART_ED_REG(UART3)
+#define UART3_MODEM                              UART_MODEM_REG(UART3)
+#define UART3_IR                                 UART_IR_REG(UART3)
+#define UART3_PFIFO                              UART_PFIFO_REG(UART3)
+#define UART3_CFIFO                              UART_CFIFO_REG(UART3)
+#define UART3_SFIFO                              UART_SFIFO_REG(UART3)
+#define UART3_TWFIFO                             UART_TWFIFO_REG(UART3)
+#define UART3_TCFIFO                             UART_TCFIFO_REG(UART3)
+#define UART3_RWFIFO                             UART_RWFIFO_REG(UART3)
+#define UART3_RCFIFO                             UART_RCFIFO_REG(UART3)
+/* UART4 */
+#define UART4_BDH                                UART_BDH_REG(UART4)
+#define UART4_BDL                                UART_BDL_REG(UART4)
+#define UART4_C1                                 UART_C1_REG(UART4)
+#define UART4_C2                                 UART_C2_REG(UART4)
+#define UART4_S1                                 UART_S1_REG(UART4)
+#define UART4_S2                                 UART_S2_REG(UART4)
+#define UART4_C3                                 UART_C3_REG(UART4)
+#define UART4_D                                  UART_D_REG(UART4)
+#define UART4_MA1                                UART_MA1_REG(UART4)
+#define UART4_MA2                                UART_MA2_REG(UART4)
+#define UART4_C4                                 UART_C4_REG(UART4)
+#define UART4_C5                                 UART_C5_REG(UART4)
+#define UART4_ED                                 UART_ED_REG(UART4)
+#define UART4_MODEM                              UART_MODEM_REG(UART4)
+#define UART4_IR                                 UART_IR_REG(UART4)
+#define UART4_PFIFO                              UART_PFIFO_REG(UART4)
+#define UART4_CFIFO                              UART_CFIFO_REG(UART4)
+#define UART4_SFIFO                              UART_SFIFO_REG(UART4)
+#define UART4_TWFIFO                             UART_TWFIFO_REG(UART4)
+#define UART4_TCFIFO                             UART_TCFIFO_REG(UART4)
+#define UART4_RWFIFO                             UART_RWFIFO_REG(UART4)
+#define UART4_RCFIFO                             UART_RCFIFO_REG(UART4)
+/* UART5 */
+#define UART5_BDH                                UART_BDH_REG(UART5)
+#define UART5_BDL                                UART_BDL_REG(UART5)
+#define UART5_C1                                 UART_C1_REG(UART5)
+#define UART5_C2                                 UART_C2_REG(UART5)
+#define UART5_S1                                 UART_S1_REG(UART5)
+#define UART5_S2                                 UART_S2_REG(UART5)
+#define UART5_C3                                 UART_C3_REG(UART5)
+#define UART5_D                                  UART_D_REG(UART5)
+#define UART5_MA1                                UART_MA1_REG(UART5)
+#define UART5_MA2                                UART_MA2_REG(UART5)
+#define UART5_C4                                 UART_C4_REG(UART5)
+#define UART5_C5                                 UART_C5_REG(UART5)
+#define UART5_ED                                 UART_ED_REG(UART5)
+#define UART5_MODEM                              UART_MODEM_REG(UART5)
+#define UART5_IR                                 UART_IR_REG(UART5)
+#define UART5_PFIFO                              UART_PFIFO_REG(UART5)
+#define UART5_CFIFO                              UART_CFIFO_REG(UART5)
+#define UART5_SFIFO                              UART_SFIFO_REG(UART5)
+#define UART5_TWFIFO                             UART_TWFIFO_REG(UART5)
+#define UART5_TCFIFO                             UART_TCFIFO_REG(UART5)
+#define UART5_RWFIFO                             UART_RWFIFO_REG(UART5)
+#define UART5_RCFIFO                             UART_RCFIFO_REG(UART5)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[3];
+  __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t OTGICR;                             /**< OTG Interrupt Control register, offset: 0x14 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_7[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_11[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_16[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t SOFTHLD;                            /**< SOF Threshold register, offset: 0xAC */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_20[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_21[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_22[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_25[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
+       uint8_t RESERVED_26[43];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_27[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48M oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_28[23];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base)                      ((base)->PERID)
+#define USB_IDCOMP_REG(base)                     ((base)->IDCOMP)
+#define USB_REV_REG(base)                        ((base)->REV)
+#define USB_ADDINFO_REG(base)                    ((base)->ADDINFO)
+#define USB_OTGISTAT_REG(base)                   ((base)->OTGISTAT)
+#define USB_OTGICR_REG(base)                     ((base)->OTGICR)
+#define USB_OTGSTAT_REG(base)                    ((base)->OTGSTAT)
+#define USB_OTGCTL_REG(base)                     ((base)->OTGCTL)
+#define USB_ISTAT_REG(base)                      ((base)->ISTAT)
+#define USB_INTEN_REG(base)                      ((base)->INTEN)
+#define USB_ERRSTAT_REG(base)                    ((base)->ERRSTAT)
+#define USB_ERREN_REG(base)                      ((base)->ERREN)
+#define USB_STAT_REG(base)                       ((base)->STAT)
+#define USB_CTL_REG(base)                        ((base)->CTL)
+#define USB_ADDR_REG(base)                       ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base)                   ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base)                    ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base)                    ((base)->FRMNUMH)
+#define USB_TOKEN_REG(base)                      ((base)->TOKEN)
+#define USB_SOFTHLD_REG(base)                    ((base)->SOFTHLD)
+#define USB_BDTPAGE2_REG(base)                   ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base)                   ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index)                ((base)->ENDPOINT[index].ENDPT)
+#define USB_ENDPT_COUNT                          16
+#define USB_USBCTRL_REG(base)                    ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base)                    ((base)->OBSERVE)
+#define USB_CONTROL_REG(base)                    ((base)->CONTROL)
+#define USB_USBTRC0_REG(base)                    ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base)               ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base)           ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base)         ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base)     ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK                        0x3Fu
+#define USB_PERID_ID_SHIFT                       0
+#define USB_PERID_ID_WIDTH                       6
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK                      0x3Fu
+#define USB_IDCOMP_NID_SHIFT                     0
+#define USB_IDCOMP_NID_WIDTH                     6
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK                         0xFFu
+#define USB_REV_REV_SHIFT                        0
+#define USB_REV_REV_WIDTH                        8
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK                  0x1u
+#define USB_ADDINFO_IEHOST_SHIFT                 0
+#define USB_ADDINFO_IEHOST_WIDTH                 1
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
+#define USB_ADDINFO_IRQNUM_MASK                  0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT                 3
+#define USB_ADDINFO_IRQNUM_WIDTH                 5
+#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK               0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT              0
+#define USB_OTGISTAT_AVBUSCHG_WIDTH              1
+#define USB_OTGISTAT_AVBUSCHG(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_AVBUSCHG_SHIFT))&USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK             0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT            2
+#define USB_OTGISTAT_B_SESS_CHG_WIDTH            1
+#define USB_OTGISTAT_B_SESS_CHG(x)               (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_B_SESS_CHG_SHIFT))&USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK             0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT            3
+#define USB_OTGISTAT_SESSVLDCHG_WIDTH            1
+#define USB_OTGISTAT_SESSVLDCHG(x)               (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_SESSVLDCHG_SHIFT))&USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK         0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        5
+#define USB_OTGISTAT_LINE_STATE_CHG_WIDTH        1
+#define USB_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK                0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT               6
+#define USB_OTGISTAT_ONEMSEC_WIDTH               1
+#define USB_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK                  0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT                 7
+#define USB_OTGISTAT_IDCHG_WIDTH                 1
+#define USB_OTGISTAT_IDCHG(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_IDCHG_SHIFT))&USB_OTGISTAT_IDCHG_MASK)
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK                  0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT                 0
+#define USB_OTGICR_AVBUSEN_WIDTH                 1
+#define USB_OTGICR_AVBUSEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_AVBUSEN_SHIFT))&USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK                  0x4u
+#define USB_OTGICR_BSESSEN_SHIFT                 2
+#define USB_OTGICR_BSESSEN_WIDTH                 1
+#define USB_OTGICR_BSESSEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_BSESSEN_SHIFT))&USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK                0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT               3
+#define USB_OTGICR_SESSVLDEN_WIDTH               1
+#define USB_OTGICR_SESSVLDEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_SESSVLDEN_SHIFT))&USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK              0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT             5
+#define USB_OTGICR_LINESTATEEN_WIDTH             1
+#define USB_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK                0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT               6
+#define USB_OTGICR_ONEMSECEN_WIDTH               1
+#define USB_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK                     0x80u
+#define USB_OTGICR_IDEN_SHIFT                    7
+#define USB_OTGICR_IDEN_WIDTH                    1
+#define USB_OTGICR_IDEN(x)                       (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_IDEN_SHIFT))&USB_OTGICR_IDEN_MASK)
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK                0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT               0
+#define USB_OTGSTAT_AVBUSVLD_WIDTH               1
+#define USB_OTGSTAT_AVBUSVLD(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_AVBUSVLD_SHIFT))&USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK                0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT               2
+#define USB_OTGSTAT_BSESSEND_WIDTH               1
+#define USB_OTGSTAT_BSESSEND(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_BSESSEND_SHIFT))&USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK                0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT               3
+#define USB_OTGSTAT_SESS_VLD_WIDTH               1
+#define USB_OTGSTAT_SESS_VLD(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_SESS_VLD_SHIFT))&USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK         0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        5
+#define USB_OTGSTAT_LINESTATESTABLE_WIDTH        1
+#define USB_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK               0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT              6
+#define USB_OTGSTAT_ONEMSECEN_WIDTH              1
+#define USB_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK                      0x80u
+#define USB_OTGSTAT_ID_SHIFT                     7
+#define USB_OTGSTAT_ID_WIDTH                     1
+#define USB_OTGSTAT_ID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ID_SHIFT))&USB_OTGSTAT_ID_MASK)
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK                    0x4u
+#define USB_OTGCTL_OTGEN_SHIFT                   2
+#define USB_OTGCTL_OTGEN_WIDTH                   1
+#define USB_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK                    0x10u
+#define USB_OTGCTL_DMLOW_SHIFT                   4
+#define USB_OTGCTL_DMLOW_WIDTH                   1
+#define USB_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK                    0x20u
+#define USB_OTGCTL_DPLOW_SHIFT                   5
+#define USB_OTGCTL_DPLOW_WIDTH                   1
+#define USB_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK                   0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT                  7
+#define USB_OTGCTL_DPHIGH_WIDTH                  1
+#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK                    0x1u
+#define USB_ISTAT_USBRST_SHIFT                   0
+#define USB_ISTAT_USBRST_WIDTH                   1
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK                     0x2u
+#define USB_ISTAT_ERROR_SHIFT                    1
+#define USB_ISTAT_ERROR_WIDTH                    1
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK                    0x4u
+#define USB_ISTAT_SOFTOK_SHIFT                   2
+#define USB_ISTAT_SOFTOK_WIDTH                   1
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK                    0x8u
+#define USB_ISTAT_TOKDNE_SHIFT                   3
+#define USB_ISTAT_TOKDNE_WIDTH                   1
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK                     0x10u
+#define USB_ISTAT_SLEEP_SHIFT                    4
+#define USB_ISTAT_SLEEP_WIDTH                    1
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK                    0x20u
+#define USB_ISTAT_RESUME_SHIFT                   5
+#define USB_ISTAT_RESUME_WIDTH                   1
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK                    0x40u
+#define USB_ISTAT_ATTACH_SHIFT                   6
+#define USB_ISTAT_ATTACH_WIDTH                   1
+#define USB_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK                     0x80u
+#define USB_ISTAT_STALL_SHIFT                    7
+#define USB_ISTAT_STALL_WIDTH                    1
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK                  0x1u
+#define USB_INTEN_USBRSTEN_SHIFT                 0
+#define USB_INTEN_USBRSTEN_WIDTH                 1
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK                   0x2u
+#define USB_INTEN_ERROREN_SHIFT                  1
+#define USB_INTEN_ERROREN_WIDTH                  1
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK                  0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT                 2
+#define USB_INTEN_SOFTOKEN_WIDTH                 1
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK                  0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT                 3
+#define USB_INTEN_TOKDNEEN_WIDTH                 1
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK                   0x10u
+#define USB_INTEN_SLEEPEN_SHIFT                  4
+#define USB_INTEN_SLEEPEN_WIDTH                  1
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK                  0x20u
+#define USB_INTEN_RESUMEEN_SHIFT                 5
+#define USB_INTEN_RESUMEEN_WIDTH                 1
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK                  0x40u
+#define USB_INTEN_ATTACHEN_SHIFT                 6
+#define USB_INTEN_ATTACHEN_WIDTH                 1
+#define USB_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK                   0x80u
+#define USB_INTEN_STALLEN_SHIFT                  7
+#define USB_INTEN_STALLEN_WIDTH                  1
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK                  0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT                 0
+#define USB_ERRSTAT_PIDERR_WIDTH                 1
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK                 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT                1
+#define USB_ERRSTAT_CRC5EOF_WIDTH                1
+#define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK                   0x4u
+#define USB_ERRSTAT_CRC16_SHIFT                  2
+#define USB_ERRSTAT_CRC16_WIDTH                  1
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK                    0x8u
+#define USB_ERRSTAT_DFN8_SHIFT                   3
+#define USB_ERRSTAT_DFN8_WIDTH                   1
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK                  0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT                 4
+#define USB_ERRSTAT_BTOERR_WIDTH                 1
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK                  0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT                 5
+#define USB_ERRSTAT_DMAERR_WIDTH                 1
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK                  0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT                 7
+#define USB_ERRSTAT_BTSERR_WIDTH                 1
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK                  0x1u
+#define USB_ERREN_PIDERREN_SHIFT                 0
+#define USB_ERREN_PIDERREN_WIDTH                 1
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK                 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT                1
+#define USB_ERREN_CRC5EOFEN_WIDTH                1
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK                   0x4u
+#define USB_ERREN_CRC16EN_SHIFT                  2
+#define USB_ERREN_CRC16EN_WIDTH                  1
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK                    0x8u
+#define USB_ERREN_DFN8EN_SHIFT                   3
+#define USB_ERREN_DFN8EN_WIDTH                   1
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK                  0x10u
+#define USB_ERREN_BTOERREN_SHIFT                 4
+#define USB_ERREN_BTOERREN_WIDTH                 1
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK                  0x20u
+#define USB_ERREN_DMAERREN_SHIFT                 5
+#define USB_ERREN_DMAERREN_WIDTH                 1
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK                  0x80u
+#define USB_ERREN_BTSERREN_SHIFT                 7
+#define USB_ERREN_BTSERREN_WIDTH                 1
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK                        0x4u
+#define USB_STAT_ODD_SHIFT                       2
+#define USB_STAT_ODD_WIDTH                       1
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK                         0x8u
+#define USB_STAT_TX_SHIFT                        3
+#define USB_STAT_TX_WIDTH                        1
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK                       0xF0u
+#define USB_STAT_ENDP_SHIFT                      4
+#define USB_STAT_ENDP_WIDTH                      4
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK                  0x1u
+#define USB_CTL_USBENSOFEN_SHIFT                 0
+#define USB_CTL_USBENSOFEN_WIDTH                 1
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK                      0x2u
+#define USB_CTL_ODDRST_SHIFT                     1
+#define USB_CTL_ODDRST_WIDTH                     1
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK                      0x4u
+#define USB_CTL_RESUME_SHIFT                     2
+#define USB_CTL_RESUME_WIDTH                     1
+#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK                  0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT                 3
+#define USB_CTL_HOSTMODEEN_WIDTH                 1
+#define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK                       0x10u
+#define USB_CTL_RESET_SHIFT                      4
+#define USB_CTL_RESET_WIDTH                      1
+#define USB_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
+#define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH         1
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK                         0x40u
+#define USB_CTL_SE0_SHIFT                        6
+#define USB_CTL_SE0_WIDTH                        1
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK                      0x80u
+#define USB_CTL_JSTATE_SHIFT                     7
+#define USB_CTL_JSTATE_WIDTH                     1
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK                       0x7Fu
+#define USB_ADDR_ADDR_SHIFT                      0
+#define USB_ADDR_ADDR_WIDTH                      7
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK                       0x80u
+#define USB_ADDR_LSEN_SHIFT                      7
+#define USB_ADDR_LSEN_WIDTH                      1
+#define USB_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT                 1
+#define USB_BDTPAGE1_BDTBA_WIDTH                 7
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK                     0xFFu
+#define USB_FRMNUML_FRM_SHIFT                    0
+#define USB_FRMNUML_FRM_WIDTH                    8
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK                     0x7u
+#define USB_FRMNUMH_FRM_SHIFT                    0
+#define USB_FRMNUMH_FRM_WIDTH                    3
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK                0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT               0
+#define USB_TOKEN_TOKENENDPT_WIDTH               4
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT                 4
+#define USB_TOKEN_TOKENPID_WIDTH                 4
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK                     0xFFu
+#define USB_SOFTHLD_CNT_SHIFT                    0
+#define USB_SOFTHLD_CNT_WIDTH                    8
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT                 0
+#define USB_BDTPAGE2_BDTBA_WIDTH                 8
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT                 0
+#define USB_BDTPAGE3_BDTBA_WIDTH                 8
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK                    0x1u
+#define USB_ENDPT_EPHSHK_SHIFT                   0
+#define USB_ENDPT_EPHSHK_WIDTH                   1
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK                   0x2u
+#define USB_ENDPT_EPSTALL_SHIFT                  1
+#define USB_ENDPT_EPSTALL_WIDTH                  1
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK                    0x4u
+#define USB_ENDPT_EPTXEN_SHIFT                   2
+#define USB_ENDPT_EPTXEN_WIDTH                   1
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK                    0x8u
+#define USB_ENDPT_EPRXEN_SHIFT                   3
+#define USB_ENDPT_EPRXEN_WIDTH                   1
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK                  0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT                 4
+#define USB_ENDPT_EPCTLDIS_WIDTH                 1
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK                  0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT                 6
+#define USB_ENDPT_RETRYDIS_WIDTH                 1
+#define USB_ENDPT_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK                 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT                7
+#define USB_ENDPT_HOSTWOHUB_WIDTH                1
+#define USB_ENDPT_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK                     0x40u
+#define USB_USBCTRL_PDE_SHIFT                    6
+#define USB_USBCTRL_PDE_WIDTH                    1
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK                    0x80u
+#define USB_USBCTRL_SUSP_SHIFT                   7
+#define USB_USBCTRL_SUSP_WIDTH                   1
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK                    0x10u
+#define USB_OBSERVE_DMPD_SHIFT                   4
+#define USB_OBSERVE_DMPD_WIDTH                   1
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK                    0x40u
+#define USB_OBSERVE_DPPD_SHIFT                   6
+#define USB_OBSERVE_DPPD_WIDTH                   1
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK                    0x80u
+#define USB_OBSERVE_DPPU_SHIFT                   7
+#define USB_OBSERVE_DPPU_WIDTH                   1
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
+#define USB_CONTROL_DPPULLUPNONOTG_WIDTH         1
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
+#define USB_USBTRC0_USB_RESUME_INT_WIDTH         1
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK                0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT               1
+#define USB_USBTRC0_SYNC_DET_WIDTH               1
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   2
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH   1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))&USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK               0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT              5
+#define USB_USBTRC0_USBRESMEN_WIDTH              1
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK                0x80u
+#define USB_USBTRC0_USBRESET_SHIFT               7
+#define USB_USBTRC0_USBRESET_WIDTH               1
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK                0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT               0
+#define USB_USBFRMADJUST_ADJ_WIDTH               8
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))&USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK       0x1u
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      0
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH 1
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))&USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR                            (USB0)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID                               USB_PERID_REG(USB0)
+#define USB0_IDCOMP                              USB_IDCOMP_REG(USB0)
+#define USB0_REV                                 USB_REV_REG(USB0)
+#define USB0_ADDINFO                             USB_ADDINFO_REG(USB0)
+#define USB0_OTGISTAT                            USB_OTGISTAT_REG(USB0)
+#define USB0_OTGICR                              USB_OTGICR_REG(USB0)
+#define USB0_OTGSTAT                             USB_OTGSTAT_REG(USB0)
+#define USB0_OTGCTL                              USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT                               USB_ISTAT_REG(USB0)
+#define USB0_INTEN                               USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT                             USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN                               USB_ERREN_REG(USB0)
+#define USB0_STAT                                USB_STAT_REG(USB0)
+#define USB0_CTL                                 USB_CTL_REG(USB0)
+#define USB0_ADDR                                USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1                            USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML                             USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH                             USB_FRMNUMH_REG(USB0)
+#define USB0_TOKEN                               USB_TOKEN_REG(USB0)
+#define USB0_SOFTHLD                             USB_SOFTHLD_REG(USB0)
+#define USB0_BDTPAGE2                            USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3                            USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0                              USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1                              USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2                              USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3                              USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4                              USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5                              USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6                              USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7                              USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8                              USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9                              USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10                             USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11                             USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12                             USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13                             USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14                             USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15                             USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL                             USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE                             USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL                             USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0                             USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST                        USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL                    USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN                  USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS              USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index)                        USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
+  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
+  __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
+  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
+  union {                                          /* offset: 0x18 */
+    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
+    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
+  };
+} USBDCD_Type, *USBDCD_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register accessors */
+#define USBDCD_CONTROL_REG(base)                 ((base)->CONTROL)
+#define USBDCD_CLOCK_REG(base)                   ((base)->CLOCK)
+#define USBDCD_STATUS_REG(base)                  ((base)->STATUS)
+#define USBDCD_TIMER0_REG(base)                  ((base)->TIMER0)
+#define USBDCD_TIMER1_REG(base)                  ((base)->TIMER1)
+#define USBDCD_TIMER2_BC11_REG(base)             ((base)->TIMER2_BC11)
+#define USBDCD_TIMER2_BC12_REG(base)             ((base)->TIMER2_BC12)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK                 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT                0
+#define USBDCD_CONTROL_IACK_WIDTH                1
+#define USBDCD_CONTROL_IACK(x)                   (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IACK_SHIFT))&USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IF_MASK                   0x100u
+#define USBDCD_CONTROL_IF_SHIFT                  8
+#define USBDCD_CONTROL_IF_WIDTH                  1
+#define USBDCD_CONTROL_IF(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IF_SHIFT))&USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IE_MASK                   0x10000u
+#define USBDCD_CONTROL_IE_SHIFT                  16
+#define USBDCD_CONTROL_IE_WIDTH                  1
+#define USBDCD_CONTROL_IE(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IE_SHIFT))&USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_BC12_MASK                 0x20000u
+#define USBDCD_CONTROL_BC12_SHIFT                17
+#define USBDCD_CONTROL_BC12_WIDTH                1
+#define USBDCD_CONTROL_BC12(x)                   (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_BC12_SHIFT))&USBDCD_CONTROL_BC12_MASK)
+#define USBDCD_CONTROL_START_MASK                0x1000000u
+#define USBDCD_CONTROL_START_SHIFT               24
+#define USBDCD_CONTROL_START_WIDTH               1
+#define USBDCD_CONTROL_START(x)                  (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_START_SHIFT))&USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_SR_MASK                   0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT                  25
+#define USBDCD_CONTROL_SR_WIDTH                  1
+#define USBDCD_CONTROL_SR(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_SR_SHIFT))&USBDCD_CONTROL_SR_MASK)
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK             0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            0
+#define USBDCD_CLOCK_CLOCK_UNIT_WIDTH            1
+#define USBDCD_CLOCK_CLOCK_UNIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_UNIT_SHIFT))&USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK            0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           2
+#define USBDCD_CLOCK_CLOCK_SPEED_WIDTH           10
+#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK               0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT              16
+#define USBDCD_STATUS_SEQ_RES_WIDTH              2
+#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK              0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT             18
+#define USBDCD_STATUS_SEQ_STAT_WIDTH             2
+#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK                   0x100000u
+#define USBDCD_STATUS_ERR_SHIFT                  20
+#define USBDCD_STATUS_ERR_WIDTH                  1
+#define USBDCD_STATUS_ERR(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ERR_SHIFT))&USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_TO_MASK                    0x200000u
+#define USBDCD_STATUS_TO_SHIFT                   21
+#define USBDCD_STATUS_TO_WIDTH                   1
+#define USBDCD_STATUS_TO(x)                      (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_TO_SHIFT))&USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_ACTIVE_MASK                0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT               22
+#define USBDCD_STATUS_ACTIVE_WIDTH               1
+#define USBDCD_STATUS_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ACTIVE_SHIFT))&USBDCD_STATUS_ACTIVE_MASK)
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK              0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT             0
+#define USBDCD_TIMER0_TUNITCON_WIDTH             12
+#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK             0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            16
+#define USBDCD_TIMER0_TSEQ_INIT_WIDTH            10
+#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK            0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           0
+#define USBDCD_TIMER1_TVDPSRC_ON_WIDTH           10
+#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK             0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            16
+#define USBDCD_TIMER1_TDCD_DBNC_WIDTH            10
+#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2_BC11 Bit Fields */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK         0xFu
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        0
+#define USBDCD_TIMER2_BC11_CHECK_DM_WIDTH        4
+#define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      0x3FF0000u
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     16
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_WIDTH     10
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+/* TIMER2_BC12 Bit Fields */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       0x3FFu
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      0
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_WIDTH      10
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  0x3FF0000u
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_WIDTH 10
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE                              (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD                                   ((USBDCD_Type *)USBDCD_BASE)
+#define USBDCD_BASE_PTR                          (USBDCD)
+/** Array initializer of USBDCD peripheral base addresses */
+#define USBDCD_BASE_ADDRS                        { USBDCD_BASE }
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASE_PTRS                         { USBDCD }
+/** Interrupt vectors for the USBDCD peripheral type */
+#define USBDCD_IRQS                              { USBDCD_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register instance definitions */
+/* USBDCD */
+#define USBDCD_CONTROL                           USBDCD_CONTROL_REG(USBDCD)
+#define USBDCD_CLOCK                             USBDCD_CLOCK_REG(USBDCD)
+#define USBDCD_STATUS                            USBDCD_STATUS_REG(USBDCD)
+#define USBDCD_TIMER0                            USBDCD_TIMER0_REG(USBDCD)
+#define USBDCD_TIMER1                            USBDCD_TIMER1_REG(USBDCD)
+#define USBDCD_TIMER2_BC11                       USBDCD_TIMER2_BC11_REG(USBDCD)
+#define USBDCD_TIMER2_BC12                       USBDCD_TIMER2_BC12_REG(USBDCD)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base)                       ((base)->TRM)
+#define VREF_SC_REG(base)                        ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK                       0x3Fu
+#define VREF_TRM_TRIM_SHIFT                      0
+#define VREF_TRM_TRIM_WIDTH                      6
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     0x40u
+#define VREF_TRM_CHOPEN_SHIFT                    6
+#define VREF_TRM_CHOPEN_WIDTH                    1
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_TRM_CHOPEN_SHIFT))&VREF_TRM_CHOPEN_MASK)
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK                     0x3u
+#define VREF_SC_MODE_LV_SHIFT                    0
+#define VREF_SC_MODE_LV_WIDTH                    2
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      0x4u
+#define VREF_SC_VREFST_SHIFT                     2
+#define VREF_SC_VREFST_WIDTH                     1
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFST_SHIFT))&VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK                     0x20u
+#define VREF_SC_ICOMPEN_SHIFT                    5
+#define VREF_SC_ICOMPEN_WIDTH                    1
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_ICOMPEN_SHIFT))&VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK                       0x40u
+#define VREF_SC_REGEN_SHIFT                      6
+#define VREF_SC_REGEN_WIDTH                      1
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_SC_REGEN_SHIFT))&VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK                      0x80u
+#define VREF_SC_VREFEN_SHIFT                     7
+#define VREF_SC_VREFEN_WIDTH                     1
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFEN_SHIFT))&VREF_SC_VREFEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR                            (VREF)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM                                 VREF_TRM_REG(VREF)
+#define VREF_SC                                  VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t STCTRLH;                           /**< Watchdog Status and Control Register High, offset: 0x0 */
+  __IO uint16_t STCTRLL;                           /**< Watchdog Status and Control Register Low, offset: 0x2 */
+  __IO uint16_t TOVALH;                            /**< Watchdog Time-out Value Register High, offset: 0x4 */
+  __IO uint16_t TOVALL;                            /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+  __IO uint16_t WINH;                              /**< Watchdog Window Register High, offset: 0x8 */
+  __IO uint16_t WINL;                              /**< Watchdog Window Register Low, offset: 0xA */
+  __IO uint16_t REFRESH;                           /**< Watchdog Refresh register, offset: 0xC */
+  __IO uint16_t UNLOCK;                            /**< Watchdog Unlock register, offset: 0xE */
+  __IO uint16_t TMROUTH;                           /**< Watchdog Timer Output Register High, offset: 0x10 */
+  __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
+  __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
+  __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type, *WDOG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register accessors */
+#define WDOG_STCTRLH_REG(base)                   ((base)->STCTRLH)
+#define WDOG_STCTRLL_REG(base)                   ((base)->STCTRLL)
+#define WDOG_TOVALH_REG(base)                    ((base)->TOVALH)
+#define WDOG_TOVALL_REG(base)                    ((base)->TOVALL)
+#define WDOG_WINH_REG(base)                      ((base)->WINH)
+#define WDOG_WINL_REG(base)                      ((base)->WINL)
+#define WDOG_REFRESH_REG(base)                   ((base)->REFRESH)
+#define WDOG_UNLOCK_REG(base)                    ((base)->UNLOCK)
+#define WDOG_TMROUTH_REG(base)                   ((base)->TMROUTH)
+#define WDOG_TMROUTL_REG(base)                   ((base)->TMROUTL)
+#define WDOG_RSTCNT_REG(base)                    ((base)->RSTCNT)
+#define WDOG_PRESC_REG(base)                     ((base)->PRESC)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK                 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT                0
+#define WDOG_STCTRLH_WDOGEN_WIDTH                1
+#define WDOG_STCTRLH_WDOGEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WDOGEN_SHIFT))&WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK                 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT                1
+#define WDOG_STCTRLH_CLKSRC_WIDTH                1
+#define WDOG_STCTRLH_CLKSRC(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_CLKSRC_SHIFT))&WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK               0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT              2
+#define WDOG_STCTRLH_IRQRSTEN_WIDTH              1
+#define WDOG_STCTRLH_IRQRSTEN(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_IRQRSTEN_SHIFT))&WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK                  0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT                 3
+#define WDOG_STCTRLH_WINEN_WIDTH                 1
+#define WDOG_STCTRLH_WINEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WINEN_SHIFT))&WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK            0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           4
+#define WDOG_STCTRLH_ALLOWUPDATE_WIDTH           1
+#define WDOG_STCTRLH_ALLOWUPDATE(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_ALLOWUPDATE_SHIFT))&WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK                  0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT                 5
+#define WDOG_STCTRLH_DBGEN_WIDTH                 1
+#define WDOG_STCTRLH_DBGEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DBGEN_SHIFT))&WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK                 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT                6
+#define WDOG_STCTRLH_STOPEN_WIDTH                1
+#define WDOG_STCTRLH_STOPEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_STOPEN_SHIFT))&WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK                 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT                7
+#define WDOG_STCTRLH_WAITEN_WIDTH                1
+#define WDOG_STCTRLH_WAITEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WAITEN_SHIFT))&WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK               0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT              10
+#define WDOG_STCTRLH_TESTWDOG_WIDTH              1
+#define WDOG_STCTRLH_TESTWDOG(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTWDOG_SHIFT))&WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK                0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT               11
+#define WDOG_STCTRLH_TESTSEL_WIDTH               1
+#define WDOG_STCTRLH_TESTSEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTSEL_SHIFT))&WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK                0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT               12
+#define WDOG_STCTRLH_BYTESEL_WIDTH               2
+#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK            0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT           14
+#define WDOG_STCTRLH_DISTESTWDOG_WIDTH           1
+#define WDOG_STCTRLH_DISTESTWDOG(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DISTESTWDOG_SHIFT))&WDOG_STCTRLH_DISTESTWDOG_MASK)
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK                 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT                15
+#define WDOG_STCTRLL_INTFLG_WIDTH                1
+#define WDOG_STCTRLL_INTFLG(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLL_INTFLG_SHIFT))&WDOG_STCTRLL_INTFLG_MASK)
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK               0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              0
+#define WDOG_TOVALH_TOVALHIGH_WIDTH              16
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK                0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT               0
+#define WDOG_TOVALL_TOVALLOW_WIDTH               16
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK                   0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT                  0
+#define WDOG_WINH_WINHIGH_WIDTH                  16
+#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK                    0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT                   0
+#define WDOG_WINL_WINLOW_WIDTH                   16
+#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK            0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT           0
+#define WDOG_REFRESH_WDOGREFRESH_WIDTH           16
+#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK              0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             0
+#define WDOG_UNLOCK_WDOGUNLOCK_WIDTH             16
+#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK           0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          0
+#define WDOG_TMROUTH_TIMEROUTHIGH_WIDTH          16
+#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK            0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           0
+#define WDOG_TMROUTL_TIMEROUTLOW_WIDTH           16
+#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK                  0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT                 0
+#define WDOG_RSTCNT_RSTCNT_WIDTH                 16
+#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK                 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT                8
+#define WDOG_PRESC_PRESCVAL_WIDTH                3
+#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+#define WDOG_BASE_PTR                            (WDOG)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS                          { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS                           { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS                                { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register instance definitions */
+/* WDOG */
+#define WDOG_STCTRLH                             WDOG_STCTRLH_REG(WDOG)
+#define WDOG_STCTRLL                             WDOG_STCTRLL_REG(WDOG)
+#define WDOG_TOVALH                              WDOG_TOVALH_REG(WDOG)
+#define WDOG_TOVALL                              WDOG_TOVALL_REG(WDOG)
+#define WDOG_WINH                                WDOG_WINH_REG(WDOG)
+#define WDOG_WINL                                WDOG_WINL_REG(WDOG)
+#define WDOG_REFRESH                             WDOG_REFRESH_REG(WDOG)
+#define WDOG_UNLOCK                              WDOG_UNLOCK_REG(WDOG)
+#define WDOG_TMROUTH                             WDOG_TMROUTH_REG(WDOG)
+#define WDOG_TMROUTL                             WDOG_TMROUTL_REG(WDOG)
+#define WDOG_RSTCNT                              WDOG_RSTCNT_REG(WDOG)
+#define WDOG_PRESC                               WDOG_PRESC_REG(WDOG)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Backward Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define DMA_EARS_REG(base)                       This_symbol_has_been_deprecated
+#define DMA_EARS                                 This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_SHIFT                  This_symbol_has_been_deprecated
+#define ENET_RMON_T_DROP_REG(base)               This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP_REG(base)               This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE_REG(base)                This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0_REG(base)            This_symbol_has_been_deprecated
+#define ENET_RMON_R_DROP_REG(base)               ENET_IEEE_R_DROP_REG(base)
+#define ENET_RMON_R_FRAME_OK_REG(base)           ENET_IEEE_R_FRAME_OK_REG(base)
+#define ENET_RMON_T_DROP                         This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP                         This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE                          This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0                      This_symbol_has_been_deprecated
+#define MCG_C9_REG(base)                         This_symbol_has_been_deprecated
+#define MCG_C2_EREFS0_MASK                       MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT                      MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK                         MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT                        MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK                       MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT                      MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x)                         MCG_C2_RANGE(x)
+#define MCG_C9                                   This_symbol_has_been_deprecated
+#define MCM_PLACR_REG(base)                      This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_MASK                       This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_SHIFT                      This_symbol_has_been_deprecated
+#define MCM_PLACR                                This_symbol_has_been_deprecated
+#define ADC_BASES                    ADC_BASE_PTRS
+#define AIPS_BASES                   AIPS_BASE_PTRS
+#define AXBS_BASES                   AXBS_BASE_PTRS
+#define CAN_BASES                    CAN_BASE_PTRS
+#define CAU_BASES                    CAU_BASE_PTRS
+#define CMP_BASES                    CMP_BASE_PTRS
+#define CMT_BASES                    CMT_BASE_PTRS
+#define CRC_BASES                    CRC_BASE_PTRS
+#define DAC_BASES                    DAC_BASE_PTRS
+#define DMA_BASES                    DMA_BASE_PTRS
+#define DMAMUX_BASES                 DMAMUX_BASE_PTRS
+#define ENET_BASES                   ENET_BASE_PTRS
+#define EWM_BASES                    EWM_BASE_PTRS
+#define FB_BASES                     FB_BASE_PTRS
+#define FMC_BASES                    FMC_BASE_PTRS
+#define FTFE_BASES                   FTFE_BASE_PTRS
+#define FTM_BASES                    FTM_BASE_PTRS
+#define GPIO_BASES                   GPIO_BASE_PTRS
+#define I2C_BASES                    I2C_BASE_PTRS
+#define I2S_BASES                    I2S_BASE_PTRS
+#define LLWU_BASES                   LLWU_BASE_PTRS
+#define LPTMR_BASES                  LPTMR_BASE_PTRS
+#define MCG_BASES                    MCG_BASE_PTRS
+#define MCM_ISR_REG(base)            MCM_ISCR_REG(base)
+#define MCM_ISR_FIOC_MASK            MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT           MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK            MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT           MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK            MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT           MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK            MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT           MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK            MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT           MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK            MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT           MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK           MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT          MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK           MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT          MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK           MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT          MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK           MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT          MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK           MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT          MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK           MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT          MCM_ISCR_FIDCE_SHIFT
+#define MCM_BASES                    MCM_BASE_PTRS
+#define MPU_BASES                    MPU_BASE_PTRS
+#define NV_BASES                     NV_BASE_PTRS
+#define OSC_BASES                    OSC_BASE_PTRS
+#define PDB_BASES                    PDB_BASE_PTRS
+#define PIT_BASES                    PIT_BASE_PTRS
+#define PMC_BASES                    PMC_BASE_PTRS
+#define PORT_BASES                   PORT_BASE_PTRS
+#define RCM_BASES                    RCM_BASE_PTRS
+#define RFSYS_BASES                  RFSYS_BASE_PTRS
+#define RFVBAT_BASES                 RFVBAT_BASE_PTRS
+#define RNG_BASES                    RNG_BASE_PTRS
+#define RTC_BASES                    RTC_BASE_PTRS
+#define SDHC_BASES                   SDHC_BASE_PTRS
+#define SIM_BASES                    SIM_BASE_PTRS
+#define SMC_BASES                    SMC_BASE_PTRS
+#define SPI_BASES                    SPI_BASE_PTRS
+#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
+#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
+#define UART_WP7816_T_TYPE0_WI_MASK  UART_WP7816T0_WI_MASK
+#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
+#define UART_WP7816_T_TYPE0_WI(x)    UART_WP7816T0_WI(x)
+#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
+#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
+#define UART_WP7816_T_TYPE1_BWI(x)   UART_WP7816T1_BWI(x)
+#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
+#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
+#define UART_WP7816_T_TYPE1_CWI(x)   UART_WP7816T1_CWI(x)
+#define UART_BASES                   UART_BASE_PTRS
+#define USB_BASES                    USB_BASE_PTRS
+#define USBDCD_BASES                 USBDCD_BASE_PTRS
+#define VREF_BASES                   VREF_BASE_PTRS
+#define WDOG_BASES                   WDOG_BASE_PTRS
+#define Watchdog_IRQn                WDOG_EWM_IRQn
+#define Watchdog_IRQHandler          WDOG_EWM_IRQHandler
+#define LPTimer_IRQn                 LPTMR0_IRQn
+#define LPTimer_IRQHandler           LPTMR0_IRQHandler
+#define LLW_IRQn                     LLWU_IRQn
+#define LLW_IRQHandler               LLWU_IRQHandler
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MK64F12_H_) */
+  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+  #if (MCU_MEM_MAP_VERSION != 0x0200u)
+    #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+      #warning There are included two not compatible versions of memory maps. Please check possible differences.
+    #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+  #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
+#endif  /* #if !defined(MK64F12_H_) */
+
+/* MK64F12.h, eof. */
diff --git a/Workspace/Interrupt/SDK/platform/devices/MK64F12/include/MK64F12_extension.h b/Workspace/Interrupt/SDK/platform/devices/MK64F12/include/MK64F12_extension.h
new file mode 100644
index 0000000..c47b6c4
--- /dev/null
+++ b/Workspace/Interrupt/SDK/platform/devices/MK64F12/include/MK64F12_extension.h
@@ -0,0 +1,63846 @@
+/*
+** ###################################################################
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150612
+**
+**     Abstract:
+**         Extension to the CMSIS register access layer header.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __MK64F12_EXTENSION_H__
+#define __MK64F12_EXTENSION_H__
+
+#include "MK64F12.h"
+#include "fsl_bitaccess.h"
+
+#if defined(__IAR_SYSTEMS_ICC__)
+  /*
+   * Suppress "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)"
+   * as some register descriptions contain code examples
+   */
+  #pragma diag_suppress=pm008
+#endif
+
+/*
+ * MK64F12 ADC
+ *
+ * Analog-to-Digital Converter
+ *
+ * Registers defined in this header file:
+ * - ADC_SC1 - ADC Status and Control Registers 1
+ * - ADC_CFG1 - ADC Configuration Register 1
+ * - ADC_CFG2 - ADC Configuration Register 2
+ * - ADC_R - ADC Data Result Register
+ * - ADC_CV1 - Compare Value Registers
+ * - ADC_CV2 - Compare Value Registers
+ * - ADC_SC2 - Status and Control Register 2
+ * - ADC_SC3 - Status and Control Register 3
+ * - ADC_OFS - ADC Offset Correction Register
+ * - ADC_PG - ADC Plus-Side Gain Register
+ * - ADC_MG - ADC Minus-Side Gain Register
+ * - ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ */
+
+#define ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
+#define ADC0_IDX (0U) /*!< Instance number for ADC0. */
+#define ADC1_IDX (1U) /*!< Instance number for ADC1. */
+
+/*******************************************************************************
+ * ADC_SC1 - ADC Status and Control Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC1 - ADC Status and Control Registers 1 (RW)
+ *
+ * Reset value: 0x0000001FU
+ *
+ * SC1A is used for both software and hardware trigger modes of operation. To
+ * allow sequential conversions of the ADC to be triggered by internal peripherals,
+ * the ADC can have more than one status and control register: one for each
+ * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
+ * for use only in hardware trigger mode. See the chip configuration information
+ * about the number of SC1n registers specific to this device. The SC1n registers
+ * have identical fields, and are used in a "ping-pong" approach to control ADC
+ * operation. At any one point in time, only one of the SC1n registers is actively
+ * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
+ * a conversion is allowed, and vice-versa for any of the SC1n registers specific
+ * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
+ * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
+ * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
+ * value other than all 1s. Writing any of the SC1n registers while that specific
+ * SC1n register is actively controlling a conversion aborts the current conversion.
+ * None of the SC1B-SC1n registers are used for software trigger operation and
+ * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC1 register
+ */
+/*@{*/
+#define ADC_RD_SC1(base, index)  (ADC_SC1_REG(base, index))
+#define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value))
+#define ADC_RMW_SC1(base, index, mask, value) (ADC_WR_SC1(base, index, (ADC_RD_SC1(base, index) & ~(mask)) | (value)))
+#define ADC_SET_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) |  (value)))
+#define ADC_CLR_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) & ~(value)))
+#define ADC_TOG_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC1 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC1, field ADCH[4:0] (RW)
+ *
+ * Selects one of the input channels. The input channel decode depends on the
+ * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
+ * DADMx. Some of the input channel options in the bitfield-setting descriptions might
+ * not be available for your device. For the actual ADC channel assignments for
+ * your device, see the Chip Configuration details. The successive approximation
+ * converter subsystem is turned off when the channel select bits are all set,
+ * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
+ * isolation of the input channel from all sources. Terminating continuous
+ * conversions this way prevents an additional single conversion from being performed. It
+ * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
+ * when continuous conversions are not enabled because the module automatically
+ * enters a low-power state when a conversion completes.
+ *
+ * Values:
+ * - 0b00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
+ *     selected as input.
+ * - 0b00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
+ *     selected as input.
+ * - 0b00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
+ *     selected as input.
+ * - 0b00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
+ *     selected as input.
+ * - 0b00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b11000 - Reserved.
+ * - 0b11001 - Reserved.
+ * - 0b11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input;
+ *     when DIFF=1, Temp Sensor (differential) is selected as input.
+ * - 0b11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
+ *     DIFF=1, Bandgap (differential) is selected as input.
+ * - 0b11100 - Reserved.
+ * - 0b11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
+ *     (differential) is selected as input. Voltage reference selected is determined
+ *     by SC2[REFSEL].
+ * - 0b11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
+ *     reserved. Voltage reference selected is determined by SC2[REFSEL].
+ * - 0b11111 - Module is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_ADCH field. */
+#define ADC_RD_SC1_ADCH(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_ADCH_MASK) >> ADC_SC1_ADCH_SHIFT)
+#define ADC_BRD_SC1_ADCH(base, index) (ADC_RD_SC1_ADCH(base, index))
+
+/*! @brief Set the ADCH field to a new value. */
+#define ADC_WR_SC1_ADCH(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_ADCH_MASK, ADC_SC1_ADCH(value)))
+#define ADC_BWR_SC1_ADCH(base, index, value) (ADC_WR_SC1_ADCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field DIFF[5] (RW)
+ *
+ * Configures the ADC to operate in differential mode. When enabled, this mode
+ * automatically selects from the differential channels, and changes the
+ * conversion algorithm and the number of cycles to complete a conversion.
+ *
+ * Values:
+ * - 0b0 - Single-ended conversions and input channels are selected.
+ * - 0b1 - Differential conversions and input channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_DIFF field. */
+#define ADC_RD_SC1_DIFF(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_DIFF_MASK) >> ADC_SC1_DIFF_SHIFT)
+#define ADC_BRD_SC1_DIFF(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT))
+
+/*! @brief Set the DIFF field to a new value. */
+#define ADC_WR_SC1_DIFF(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_DIFF_MASK, ADC_SC1_DIFF(value)))
+#define ADC_BWR_SC1_DIFF(base, index, value) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field AIEN[6] (RW)
+ *
+ * Enables conversion complete interrupts. When COCO becomes set while the
+ * respective AIEN is high, an interrupt is asserted.
+ *
+ * Values:
+ * - 0b0 - Conversion complete interrupt is disabled.
+ * - 0b1 - Conversion complete interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_AIEN field. */
+#define ADC_RD_SC1_AIEN(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIEN_SHIFT)
+#define ADC_BRD_SC1_AIEN(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT))
+
+/*! @brief Set the AIEN field to a new value. */
+#define ADC_WR_SC1_AIEN(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_AIEN_MASK, ADC_SC1_AIEN(value)))
+#define ADC_BWR_SC1_AIEN(base, index, value) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field COCO[7] (RO)
+ *
+ * This is a read-only field that is set each time a conversion is completed
+ * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
+ * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
+ * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
+ * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
+ * COCO is set upon completion of the selected number of conversions (determined
+ * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
+ * COCO is cleared when the respective SC1n register is written or when the
+ * respective Rn register is read.
+ *
+ * Values:
+ * - 0b0 - Conversion is not completed.
+ * - 0b1 - Conversion is completed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_COCO field. */
+#define ADC_RD_SC1_COCO(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_COCO_MASK) >> ADC_SC1_COCO_SHIFT)
+#define ADC_BRD_SC1_COCO(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG1 - ADC Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG1 - ADC Configuration Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The configuration Register 1 (CFG1) selects the mode of operation, clock
+ * source, clock divide, and configuration for low power or long sample time.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG1 register
+ */
+/*@{*/
+#define ADC_RD_CFG1(base)        (ADC_CFG1_REG(base))
+#define ADC_WR_CFG1(base, value) (ADC_CFG1_REG(base) = (value))
+#define ADC_RMW_CFG1(base, mask, value) (ADC_WR_CFG1(base, (ADC_RD_CFG1(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) |  (value)))
+#define ADC_CLR_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) & ~(value)))
+#define ADC_TOG_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
+ *
+ * Selects the input clock source to generate the internal clock, ADCK. Note
+ * that when the ADACK clock source is selected, it is not required to be active
+ * prior to conversion start. When it is selected and it is not active prior to a
+ * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
+ * the start of a conversion and deactivated when conversions are terminated. In
+ * this case, there is an associated clock startup delay each time the clock
+ * source is re-activated.
+ *
+ * Values:
+ * - 0b00 - Bus clock
+ * - 0b01 - Alternate clock 2 (ALTCLK2)
+ * - 0b10 - Alternate clock (ALTCLK)
+ * - 0b11 - Asynchronous clock (ADACK)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADICLK field. */
+#define ADC_RD_CFG1_ADICLK(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADICLK_MASK) >> ADC_CFG1_ADICLK_SHIFT)
+#define ADC_BRD_CFG1_ADICLK(base) (ADC_RD_CFG1_ADICLK(base))
+
+/*! @brief Set the ADICLK field to a new value. */
+#define ADC_WR_CFG1_ADICLK(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADICLK_MASK, ADC_CFG1_ADICLK(value)))
+#define ADC_BWR_CFG1_ADICLK(base, value) (ADC_WR_CFG1_ADICLK(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field MODE[3:2] (RW)
+ *
+ * Selects the ADC resolution mode.
+ *
+ * Values:
+ * - 0b00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
+ *     differential 9-bit conversion with 2's complement output.
+ * - 0b01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it
+ *     is differential 13-bit conversion with 2's complement output.
+ * - 0b10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it
+ *     is differential 11-bit conversion with 2's complement output
+ * - 0b11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it
+ *     is differential 16-bit conversion with 2's complement output
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_MODE field. */
+#define ADC_RD_CFG1_MODE(base) ((ADC_CFG1_REG(base) & ADC_CFG1_MODE_MASK) >> ADC_CFG1_MODE_SHIFT)
+#define ADC_BRD_CFG1_MODE(base) (ADC_RD_CFG1_MODE(base))
+
+/*! @brief Set the MODE field to a new value. */
+#define ADC_WR_CFG1_MODE(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_MODE_MASK, ADC_CFG1_MODE(value)))
+#define ADC_BWR_CFG1_MODE(base, value) (ADC_WR_CFG1_MODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLSMP[4] (RW)
+ *
+ * Selects between different sample times based on the conversion mode selected.
+ * This field adjusts the sample period to allow higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption if
+ * continuous conversions are enabled and high conversion rates are not required.
+ * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
+ * extent of the long sample time.
+ *
+ * Values:
+ * - 0b0 - Short sample time.
+ * - 0b1 - Long sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
+#define ADC_RD_CFG1_ADLSMP(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLSMP_MASK) >> ADC_CFG1_ADLSMP_SHIFT)
+#define ADC_BRD_CFG1_ADLSMP(base) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT))
+
+/*! @brief Set the ADLSMP field to a new value. */
+#define ADC_WR_CFG1_ADLSMP(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLSMP_MASK, ADC_CFG1_ADLSMP(value)))
+#define ADC_BWR_CFG1_ADLSMP(base, value) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADIV[6:5] (RW)
+ *
+ * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
+ *
+ * Values:
+ * - 0b00 - The divide ratio is 1 and the clock rate is input clock.
+ * - 0b01 - The divide ratio is 2 and the clock rate is (input clock)/2.
+ * - 0b10 - The divide ratio is 4 and the clock rate is (input clock)/4.
+ * - 0b11 - The divide ratio is 8 and the clock rate is (input clock)/8.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADIV field. */
+#define ADC_RD_CFG1_ADIV(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT)
+#define ADC_BRD_CFG1_ADIV(base) (ADC_RD_CFG1_ADIV(base))
+
+/*! @brief Set the ADIV field to a new value. */
+#define ADC_WR_CFG1_ADIV(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADIV_MASK, ADC_CFG1_ADIV(value)))
+#define ADC_BWR_CFG1_ADIV(base, value) (ADC_WR_CFG1_ADIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLPC[7] (RW)
+ *
+ * Controls the power configuration of the successive approximation converter.
+ * This optimizes power consumption when higher sample rates are not required.
+ *
+ * Values:
+ * - 0b0 - Normal power configuration.
+ * - 0b1 - Low-power configuration. The power is reduced at the expense of
+ *     maximum clock speed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLPC field. */
+#define ADC_RD_CFG1_ADLPC(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLPC_MASK) >> ADC_CFG1_ADLPC_SHIFT)
+#define ADC_BRD_CFG1_ADLPC(base) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT))
+
+/*! @brief Set the ADLPC field to a new value. */
+#define ADC_WR_CFG1_ADLPC(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLPC_MASK, ADC_CFG1_ADLPC(value)))
+#define ADC_BWR_CFG1_ADLPC(base, value) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG2 - ADC Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG2 - ADC Configuration Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Configuration Register 2 (CFG2) selects the special high-speed configuration
+ * for very high speed conversions and selects the long sample time duration
+ * during long sample mode.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG2 register
+ */
+/*@{*/
+#define ADC_RD_CFG2(base)        (ADC_CFG2_REG(base))
+#define ADC_WR_CFG2(base, value) (ADC_CFG2_REG(base) = (value))
+#define ADC_RMW_CFG2(base, mask, value) (ADC_WR_CFG2(base, (ADC_RD_CFG2(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) |  (value)))
+#define ADC_CLR_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) & ~(value)))
+#define ADC_TOG_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
+ *
+ * Selects between the extended sample times when long sample time is selected,
+ * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption when
+ * continuous conversions are enabled if high conversion rates are not required.
+ *
+ * Values:
+ * - 0b00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
+ *     total.
+ * - 0b01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
+ * - 0b10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
+ * - 0b11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
+#define ADC_RD_CFG2_ADLSTS(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADLSTS_MASK) >> ADC_CFG2_ADLSTS_SHIFT)
+#define ADC_BRD_CFG2_ADLSTS(base) (ADC_RD_CFG2_ADLSTS(base))
+
+/*! @brief Set the ADLSTS field to a new value. */
+#define ADC_WR_CFG2_ADLSTS(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADLSTS_MASK, ADC_CFG2_ADLSTS(value)))
+#define ADC_BWR_CFG2_ADLSTS(base, value) (ADC_WR_CFG2_ADLSTS(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADHSC[2] (RW)
+ *
+ * Configures the ADC for very high-speed operation. The conversion sequence is
+ * altered with 2 ADCK cycles added to the conversion time to allow higher speed
+ * conversion clocks.
+ *
+ * Values:
+ * - 0b0 - Normal conversion sequence selected.
+ * - 0b1 - High-speed conversion sequence selected with 2 additional ADCK cycles
+ *     to total conversion time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADHSC field. */
+#define ADC_RD_CFG2_ADHSC(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADHSC_MASK) >> ADC_CFG2_ADHSC_SHIFT)
+#define ADC_BRD_CFG2_ADHSC(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT))
+
+/*! @brief Set the ADHSC field to a new value. */
+#define ADC_WR_CFG2_ADHSC(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADHSC_MASK, ADC_CFG2_ADHSC(value)))
+#define ADC_BWR_CFG2_ADHSC(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADACKEN[3] (RW)
+ *
+ * Enables the asynchronous clock source and the clock source output regardless
+ * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
+ * asynchronous clock may be used by other modules. See chip configuration
+ * information. Setting this field allows the clock to be used even while the ADC is
+ * idle or operating from a different clock source. Also, latency of initiating a
+ * single or first-continuous conversion with the asynchronous clock selected is
+ * reduced because the ADACK clock is already operational.
+ *
+ * Values:
+ * - 0b0 - Asynchronous clock output disabled; Asynchronous clock is enabled
+ *     only if selected by ADICLK and a conversion is active.
+ * - 0b1 - Asynchronous clock and clock output is enabled regardless of the
+ *     state of the ADC.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
+#define ADC_RD_CFG2_ADACKEN(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADACKEN_MASK) >> ADC_CFG2_ADACKEN_SHIFT)
+#define ADC_BRD_CFG2_ADACKEN(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT))
+
+/*! @brief Set the ADACKEN field to a new value. */
+#define ADC_WR_CFG2_ADACKEN(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADACKEN_MASK, ADC_CFG2_ADACKEN(value)))
+#define ADC_BWR_CFG2_ADACKEN(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field MUXSEL[4] (RW)
+ *
+ * Changes the ADC mux setting to select between alternate sets of ADC channels.
+ *
+ * Values:
+ * - 0b0 - ADxxa channels are selected.
+ * - 0b1 - ADxxb channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
+#define ADC_RD_CFG2_MUXSEL(base) ((ADC_CFG2_REG(base) & ADC_CFG2_MUXSEL_MASK) >> ADC_CFG2_MUXSEL_SHIFT)
+#define ADC_BRD_CFG2_MUXSEL(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT))
+
+/*! @brief Set the MUXSEL field to a new value. */
+#define ADC_WR_CFG2_MUXSEL(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_MUXSEL_MASK, ADC_CFG2_MUXSEL(value)))
+#define ADC_BWR_CFG2_MUXSEL(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_R - ADC Data Result Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_R - ADC Data Result Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The data result registers (Rn) contain the result of an ADC conversion of the
+ * channel selected by the corresponding status and channel control register
+ * (SC1A:SC1n). For every status and channel control register, there is a
+ * corresponding data result register. Unused bits in R n are cleared in unsigned
+ * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
+ * For example, when configured for 10-bit single-ended mode, D[15:10] are
+ * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
+ * that is, bit 10 extended through bit 15. The following table describes the
+ * behavior of the data result registers in the different modes of operation. Data
+ * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
+ * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
+ * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
+ * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
+ * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
+ * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
+ * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
+ * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
+ * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
+ * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
+ * 2's complement data if indicated
+ */
+/*!
+ * @name Constants and macros for entire ADC_R register
+ */
+/*@{*/
+#define ADC_RD_R(base, index)    (ADC_R_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_R bitfields
+ */
+
+/*!
+ * @name Register ADC_R, field D[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_R_D field. */
+#define ADC_RD_R_D(base, index) ((ADC_R_REG(base, index) & ADC_R_D_MASK) >> ADC_R_D_SHIFT)
+#define ADC_BRD_R_D(base, index) (ADC_RD_R_D(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV1 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV1 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV1 register
+ */
+/*@{*/
+#define ADC_RD_CV1(base)         (ADC_CV1_REG(base))
+#define ADC_WR_CV1(base, value)  (ADC_CV1_REG(base) = (value))
+#define ADC_RMW_CV1(base, mask, value) (ADC_WR_CV1(base, (ADC_RD_CV1(base) & ~(mask)) | (value)))
+#define ADC_SET_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) |  (value)))
+#define ADC_CLR_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) & ~(value)))
+#define ADC_TOG_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV1, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV1_CV field. */
+#define ADC_RD_CV1_CV(base)  ((ADC_CV1_REG(base) & ADC_CV1_CV_MASK) >> ADC_CV1_CV_SHIFT)
+#define ADC_BRD_CV1_CV(base) (ADC_RD_CV1_CV(base))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV1_CV(base, value) (ADC_RMW_CV1(base, ADC_CV1_CV_MASK, ADC_CV1_CV(value)))
+#define ADC_BWR_CV1_CV(base, value) (ADC_WR_CV1_CV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV2 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV2 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV2 register
+ */
+/*@{*/
+#define ADC_RD_CV2(base)         (ADC_CV2_REG(base))
+#define ADC_WR_CV2(base, value)  (ADC_CV2_REG(base) = (value))
+#define ADC_RMW_CV2(base, mask, value) (ADC_WR_CV2(base, (ADC_RD_CV2(base) & ~(mask)) | (value)))
+#define ADC_SET_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) |  (value)))
+#define ADC_CLR_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) & ~(value)))
+#define ADC_TOG_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV2, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV2_CV field. */
+#define ADC_RD_CV2_CV(base)  ((ADC_CV2_REG(base) & ADC_CV2_CV_MASK) >> ADC_CV2_CV_SHIFT)
+#define ADC_BRD_CV2_CV(base) (ADC_RD_CV2_CV(base))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV2_CV(base, value) (ADC_RMW_CV2(base, ADC_CV2_CV_MASK, ADC_CV2_CV(value)))
+#define ADC_BWR_CV2_CV(base, value) (ADC_WR_CV2_CV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC2 - Status and Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC2 - Status and Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The status and control register 2 (SC2) contains the conversion active,
+ * hardware/software trigger select, compare function, and voltage reference select of
+ * the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC2 register
+ */
+/*@{*/
+#define ADC_RD_SC2(base)         (ADC_SC2_REG(base))
+#define ADC_WR_SC2(base, value)  (ADC_SC2_REG(base) = (value))
+#define ADC_RMW_SC2(base, mask, value) (ADC_WR_SC2(base, (ADC_RD_SC2(base) & ~(mask)) | (value)))
+#define ADC_SET_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) |  (value)))
+#define ADC_CLR_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) & ~(value)))
+#define ADC_TOG_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC2 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC2, field REFSEL[1:0] (RW)
+ *
+ * Selects the voltage reference source used for conversions.
+ *
+ * Values:
+ * - 0b00 - Default voltage reference pin pair, that is, external pins VREFH and
+ *     VREFL
+ * - 0b01 - Alternate reference pair, that is, VALTH and VALTL . This pair may
+ *     be additional external pins or internal sources depending on the MCU
+ *     configuration. See the chip configuration information for details specific to
+ *     this MCU
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_REFSEL field. */
+#define ADC_RD_SC2_REFSEL(base) ((ADC_SC2_REG(base) & ADC_SC2_REFSEL_MASK) >> ADC_SC2_REFSEL_SHIFT)
+#define ADC_BRD_SC2_REFSEL(base) (ADC_RD_SC2_REFSEL(base))
+
+/*! @brief Set the REFSEL field to a new value. */
+#define ADC_WR_SC2_REFSEL(base, value) (ADC_RMW_SC2(base, ADC_SC2_REFSEL_MASK, ADC_SC2_REFSEL(value)))
+#define ADC_BWR_SC2_REFSEL(base, value) (ADC_WR_SC2_REFSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field DMAEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled and will assert the ADC DMA request during an ADC
+ *     conversion complete event noted when any of the SC1n[COCO] flags is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_DMAEN field. */
+#define ADC_RD_SC2_DMAEN(base) ((ADC_SC2_REG(base) & ADC_SC2_DMAEN_MASK) >> ADC_SC2_DMAEN_SHIFT)
+#define ADC_BRD_SC2_DMAEN(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define ADC_WR_SC2_DMAEN(base, value) (ADC_RMW_SC2(base, ADC_SC2_DMAEN_MASK, ADC_SC2_DMAEN(value)))
+#define ADC_BWR_SC2_DMAEN(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACREN[3] (RW)
+ *
+ * Configures the compare function to check if the conversion result of the
+ * input being monitored is either between or outside the range formed by CV1 and CV2
+ * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
+ * effect.
+ *
+ * Values:
+ * - 0b0 - Range function disabled. Only CV1 is compared.
+ * - 0b1 - Range function enabled. Both CV1 and CV2 are compared.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACREN field. */
+#define ADC_RD_SC2_ACREN(base) ((ADC_SC2_REG(base) & ADC_SC2_ACREN_MASK) >> ADC_SC2_ACREN_SHIFT)
+#define ADC_BRD_SC2_ACREN(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT))
+
+/*! @brief Set the ACREN field to a new value. */
+#define ADC_WR_SC2_ACREN(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACREN_MASK, ADC_SC2_ACREN(value)))
+#define ADC_BWR_SC2_ACREN(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFGT[4] (RW)
+ *
+ * Configures the compare function to check the conversion result relative to
+ * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
+ * have any effect.
+ *
+ * Values:
+ * - 0b0 - Configures less than threshold, outside range not inclusive and
+ *     inside range not inclusive; functionality based on the values placed in CV1 and
+ *     CV2.
+ * - 0b1 - Configures greater than or equal to threshold, outside and inside
+ *     ranges inclusive; functionality based on the values placed in CV1 and CV2.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFGT field. */
+#define ADC_RD_SC2_ACFGT(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFGT_MASK) >> ADC_SC2_ACFGT_SHIFT)
+#define ADC_BRD_SC2_ACFGT(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT))
+
+/*! @brief Set the ACFGT field to a new value. */
+#define ADC_WR_SC2_ACFGT(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFGT_MASK, ADC_SC2_ACFGT(value)))
+#define ADC_BWR_SC2_ACFGT(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFE[5] (RW)
+ *
+ * Enables the compare function.
+ *
+ * Values:
+ * - 0b0 - Compare function disabled.
+ * - 0b1 - Compare function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFE field. */
+#define ADC_RD_SC2_ACFE(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFE_MASK) >> ADC_SC2_ACFE_SHIFT)
+#define ADC_BRD_SC2_ACFE(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT))
+
+/*! @brief Set the ACFE field to a new value. */
+#define ADC_WR_SC2_ACFE(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFE_MASK, ADC_SC2_ACFE(value)))
+#define ADC_BWR_SC2_ACFE(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADTRG[6] (RW)
+ *
+ * Selects the type of trigger used for initiating a conversion. Two types of
+ * trigger are selectable: Software trigger: When software trigger is selected, a
+ * conversion is initiated following a write to SC1A. Hardware trigger: When
+ * hardware trigger is selected, a conversion is initiated following the assertion of
+ * the ADHWT input after a pulse of the ADHWTSn input.
+ *
+ * Values:
+ * - 0b0 - Software trigger selected.
+ * - 0b1 - Hardware trigger selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADTRG field. */
+#define ADC_RD_SC2_ADTRG(base) ((ADC_SC2_REG(base) & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT)
+#define ADC_BRD_SC2_ADTRG(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT))
+
+/*! @brief Set the ADTRG field to a new value. */
+#define ADC_WR_SC2_ADTRG(base, value) (ADC_RMW_SC2(base, ADC_SC2_ADTRG_MASK, ADC_SC2_ADTRG(value)))
+#define ADC_BWR_SC2_ADTRG(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADACT[7] (RO)
+ *
+ * Indicates that a conversion or hardware averaging is in progress. ADACT is
+ * set when a conversion is initiated and cleared when a conversion is completed or
+ * aborted.
+ *
+ * Values:
+ * - 0b0 - Conversion not in progress.
+ * - 0b1 - Conversion in progress.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADACT field. */
+#define ADC_RD_SC2_ADACT(base) ((ADC_SC2_REG(base) & ADC_SC2_ADACT_MASK) >> ADC_SC2_ADACT_SHIFT)
+#define ADC_BRD_SC2_ADACT(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADACT_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC3 - Status and Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC3 - Status and Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Status and Control Register 3 (SC3) controls the calibration, continuous
+ * convert, and hardware averaging functions of the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC3 register
+ */
+/*@{*/
+#define ADC_RD_SC3(base)         (ADC_SC3_REG(base))
+#define ADC_WR_SC3(base, value)  (ADC_SC3_REG(base) = (value))
+#define ADC_RMW_SC3(base, mask, value) (ADC_WR_SC3(base, (ADC_RD_SC3(base) & ~(mask)) | (value)))
+#define ADC_SET_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) |  (value)))
+#define ADC_CLR_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) & ~(value)))
+#define ADC_TOG_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC3 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC3, field AVGS[1:0] (RW)
+ *
+ * Determines how many ADC conversions will be averaged to create the ADC
+ * average result.
+ *
+ * Values:
+ * - 0b00 - 4 samples averaged.
+ * - 0b01 - 8 samples averaged.
+ * - 0b10 - 16 samples averaged.
+ * - 0b11 - 32 samples averaged.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGS field. */
+#define ADC_RD_SC3_AVGS(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGS_MASK) >> ADC_SC3_AVGS_SHIFT)
+#define ADC_BRD_SC3_AVGS(base) (ADC_RD_SC3_AVGS(base))
+
+/*! @brief Set the AVGS field to a new value. */
+#define ADC_WR_SC3_AVGS(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGS_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGS(value)))
+#define ADC_BWR_SC3_AVGS(base, value) (ADC_WR_SC3_AVGS(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field AVGE[2] (RW)
+ *
+ * Enables the hardware average function of the ADC.
+ *
+ * Values:
+ * - 0b0 - Hardware average function disabled.
+ * - 0b1 - Hardware average function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGE field. */
+#define ADC_RD_SC3_AVGE(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGE_MASK) >> ADC_SC3_AVGE_SHIFT)
+#define ADC_BRD_SC3_AVGE(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT))
+
+/*! @brief Set the AVGE field to a new value. */
+#define ADC_WR_SC3_AVGE(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGE_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGE(value)))
+#define ADC_BWR_SC3_AVGE(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field ADCO[3] (RW)
+ *
+ * Enables continuous conversions.
+ *
+ * Values:
+ * - 0b0 - One conversion or one set of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ * - 0b1 - Continuous conversions or sets of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_ADCO field. */
+#define ADC_RD_SC3_ADCO(base) ((ADC_SC3_REG(base) & ADC_SC3_ADCO_MASK) >> ADC_SC3_ADCO_SHIFT)
+#define ADC_BRD_SC3_ADCO(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT))
+
+/*! @brief Set the ADCO field to a new value. */
+#define ADC_WR_SC3_ADCO(base, value) (ADC_RMW_SC3(base, (ADC_SC3_ADCO_MASK | ADC_SC3_CALF_MASK), ADC_SC3_ADCO(value)))
+#define ADC_BWR_SC3_ADCO(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CALF[6] (W1C)
+ *
+ * Displays the result of the calibration sequence. The calibration sequence
+ * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
+ * entered before the calibration sequence completes. Writing 1 to CALF clears it.
+ *
+ * Values:
+ * - 0b0 - Calibration completed normally.
+ * - 0b1 - Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CALF field. */
+#define ADC_RD_SC3_CALF(base) ((ADC_SC3_REG(base) & ADC_SC3_CALF_MASK) >> ADC_SC3_CALF_SHIFT)
+#define ADC_BRD_SC3_CALF(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT))
+
+/*! @brief Set the CALF field to a new value. */
+#define ADC_WR_SC3_CALF(base, value) (ADC_RMW_SC3(base, ADC_SC3_CALF_MASK, ADC_SC3_CALF(value)))
+#define ADC_BWR_SC3_CALF(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CAL[7] (RW)
+ *
+ * Begins the calibration sequence when set. This field stays set while the
+ * calibration is in progress and is cleared when the calibration sequence is
+ * completed. CALF must be checked to determine the result of the calibration sequence.
+ * Once started, the calibration routine cannot be interrupted by writes to the
+ * ADC registers or the results will be invalid and CALF will set. Setting CAL
+ * will abort any current conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CAL field. */
+#define ADC_RD_SC3_CAL(base) ((ADC_SC3_REG(base) & ADC_SC3_CAL_MASK) >> ADC_SC3_CAL_SHIFT)
+#define ADC_BRD_SC3_CAL(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT))
+
+/*! @brief Set the CAL field to a new value. */
+#define ADC_WR_SC3_CAL(base, value) (ADC_RMW_SC3(base, (ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK), ADC_SC3_CAL(value)))
+#define ADC_BWR_SC3_CAL(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_OFS - ADC Offset Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_OFS - ADC Offset Correction Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * The ADC Offset Correction Register (OFS) contains the user-selected or
+ * calibration-generated offset error correction value. This register is a 2's
+ * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
+ * conversion and the result is transferred into the result registers, Rn. If the
+ * result is greater than the maximum or less than the minimum result value, it is
+ * forced to the appropriate limit for the current mode of operation.
+ */
+/*!
+ * @name Constants and macros for entire ADC_OFS register
+ */
+/*@{*/
+#define ADC_RD_OFS(base)         (ADC_OFS_REG(base))
+#define ADC_WR_OFS(base, value)  (ADC_OFS_REG(base) = (value))
+#define ADC_RMW_OFS(base, mask, value) (ADC_WR_OFS(base, (ADC_RD_OFS(base) & ~(mask)) | (value)))
+#define ADC_SET_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) |  (value)))
+#define ADC_CLR_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) & ~(value)))
+#define ADC_TOG_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_OFS bitfields
+ */
+
+/*!
+ * @name Register ADC_OFS, field OFS[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_OFS_OFS field. */
+#define ADC_RD_OFS_OFS(base) ((ADC_OFS_REG(base) & ADC_OFS_OFS_MASK) >> ADC_OFS_OFS_SHIFT)
+#define ADC_BRD_OFS_OFS(base) (ADC_RD_OFS_OFS(base))
+
+/*! @brief Set the OFS field to a new value. */
+#define ADC_WR_OFS_OFS(base, value) (ADC_RMW_OFS(base, ADC_OFS_OFS_MASK, ADC_OFS_OFS(value)))
+#define ADC_BWR_OFS_OFS(base, value) (ADC_WR_OFS_OFS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_PG - ADC Plus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_PG - ADC Plus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Plus-Side Gain Register (PG) contains the gain error correction for the
+ * plus-side input in differential mode or the overall conversion in single-ended
+ * mode. PG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
+ * written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_PG register
+ */
+/*@{*/
+#define ADC_RD_PG(base)          (ADC_PG_REG(base))
+#define ADC_WR_PG(base, value)   (ADC_PG_REG(base) = (value))
+#define ADC_RMW_PG(base, mask, value) (ADC_WR_PG(base, (ADC_RD_PG(base) & ~(mask)) | (value)))
+#define ADC_SET_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) |  (value)))
+#define ADC_CLR_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) & ~(value)))
+#define ADC_TOG_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_PG bitfields
+ */
+
+/*!
+ * @name Register ADC_PG, field PG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_PG_PG field. */
+#define ADC_RD_PG_PG(base)   ((ADC_PG_REG(base) & ADC_PG_PG_MASK) >> ADC_PG_PG_SHIFT)
+#define ADC_BRD_PG_PG(base)  (ADC_RD_PG_PG(base))
+
+/*! @brief Set the PG field to a new value. */
+#define ADC_WR_PG_PG(base, value) (ADC_RMW_PG(base, ADC_PG_PG_MASK, ADC_PG_PG(value)))
+#define ADC_BWR_PG_PG(base, value) (ADC_WR_PG_PG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_MG - ADC Minus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_MG - ADC Minus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Minus-Side Gain Register (MG) contains the gain error correction for the
+ * minus-side input in differential mode. This register is ignored in
+ * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
+ * be written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_MG register
+ */
+/*@{*/
+#define ADC_RD_MG(base)          (ADC_MG_REG(base))
+#define ADC_WR_MG(base, value)   (ADC_MG_REG(base) = (value))
+#define ADC_RMW_MG(base, mask, value) (ADC_WR_MG(base, (ADC_RD_MG(base) & ~(mask)) | (value)))
+#define ADC_SET_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) |  (value)))
+#define ADC_CLR_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) & ~(value)))
+#define ADC_TOG_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_MG bitfields
+ */
+
+/*!
+ * @name Register ADC_MG, field MG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_MG_MG field. */
+#define ADC_RD_MG_MG(base)   ((ADC_MG_REG(base) & ADC_MG_MG_MASK) >> ADC_MG_MG_SHIFT)
+#define ADC_BRD_MG_MG(base)  (ADC_RD_MG_MG(base))
+
+/*! @brief Set the MG field to a new value. */
+#define ADC_WR_MG_MG(base, value) (ADC_RMW_MG(base, ADC_MG_MG_MASK, ADC_MG_MG(value)))
+#define ADC_BWR_MG_MG(base, value) (ADC_WR_MG_MG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
+ * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
+ * when the self-calibration sequence is done, that is, CAL is cleared. If these
+ * registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPD register
+ */
+/*@{*/
+#define ADC_RD_CLPD(base)        (ADC_CLPD_REG(base))
+#define ADC_WR_CLPD(base, value) (ADC_CLPD_REG(base) = (value))
+#define ADC_RMW_CLPD(base, mask, value) (ADC_WR_CLPD(base, (ADC_RD_CLPD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) |  (value)))
+#define ADC_CLR_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) & ~(value)))
+#define ADC_TOG_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPD, field CLPD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPD_CLPD field. */
+#define ADC_RD_CLPD_CLPD(base) ((ADC_CLPD_REG(base) & ADC_CLPD_CLPD_MASK) >> ADC_CLPD_CLPD_SHIFT)
+#define ADC_BRD_CLPD_CLPD(base) (ADC_RD_CLPD_CLPD(base))
+
+/*! @brief Set the CLPD field to a new value. */
+#define ADC_WR_CLPD_CLPD(base, value) (ADC_RMW_CLPD(base, ADC_CLPD_CLPD_MASK, ADC_CLPD_CLPD(value)))
+#define ADC_BWR_CLPD_CLPD(base, value) (ADC_WR_CLPD_CLPD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPS register
+ */
+/*@{*/
+#define ADC_RD_CLPS(base)        (ADC_CLPS_REG(base))
+#define ADC_WR_CLPS(base, value) (ADC_CLPS_REG(base) = (value))
+#define ADC_RMW_CLPS(base, mask, value) (ADC_WR_CLPS(base, (ADC_RD_CLPS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) |  (value)))
+#define ADC_CLR_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) & ~(value)))
+#define ADC_TOG_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPS, field CLPS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPS_CLPS field. */
+#define ADC_RD_CLPS_CLPS(base) ((ADC_CLPS_REG(base) & ADC_CLPS_CLPS_MASK) >> ADC_CLPS_CLPS_SHIFT)
+#define ADC_BRD_CLPS_CLPS(base) (ADC_RD_CLPS_CLPS(base))
+
+/*! @brief Set the CLPS field to a new value. */
+#define ADC_WR_CLPS_CLPS(base, value) (ADC_RMW_CLPS(base, ADC_CLPS_CLPS_MASK, ADC_CLPS_CLPS(value)))
+#define ADC_BWR_CLPS_CLPS(base, value) (ADC_WR_CLPS_CLPS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP4 register
+ */
+/*@{*/
+#define ADC_RD_CLP4(base)        (ADC_CLP4_REG(base))
+#define ADC_WR_CLP4(base, value) (ADC_CLP4_REG(base) = (value))
+#define ADC_RMW_CLP4(base, mask, value) (ADC_WR_CLP4(base, (ADC_RD_CLP4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) |  (value)))
+#define ADC_CLR_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) & ~(value)))
+#define ADC_TOG_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP4, field CLP4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP4_CLP4 field. */
+#define ADC_RD_CLP4_CLP4(base) ((ADC_CLP4_REG(base) & ADC_CLP4_CLP4_MASK) >> ADC_CLP4_CLP4_SHIFT)
+#define ADC_BRD_CLP4_CLP4(base) (ADC_RD_CLP4_CLP4(base))
+
+/*! @brief Set the CLP4 field to a new value. */
+#define ADC_WR_CLP4_CLP4(base, value) (ADC_RMW_CLP4(base, ADC_CLP4_CLP4_MASK, ADC_CLP4_CLP4(value)))
+#define ADC_BWR_CLP4_CLP4(base, value) (ADC_WR_CLP4_CLP4(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP3 register
+ */
+/*@{*/
+#define ADC_RD_CLP3(base)        (ADC_CLP3_REG(base))
+#define ADC_WR_CLP3(base, value) (ADC_CLP3_REG(base) = (value))
+#define ADC_RMW_CLP3(base, mask, value) (ADC_WR_CLP3(base, (ADC_RD_CLP3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) |  (value)))
+#define ADC_CLR_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) & ~(value)))
+#define ADC_TOG_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP3, field CLP3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP3_CLP3 field. */
+#define ADC_RD_CLP3_CLP3(base) ((ADC_CLP3_REG(base) & ADC_CLP3_CLP3_MASK) >> ADC_CLP3_CLP3_SHIFT)
+#define ADC_BRD_CLP3_CLP3(base) (ADC_RD_CLP3_CLP3(base))
+
+/*! @brief Set the CLP3 field to a new value. */
+#define ADC_WR_CLP3_CLP3(base, value) (ADC_RMW_CLP3(base, ADC_CLP3_CLP3_MASK, ADC_CLP3_CLP3(value)))
+#define ADC_BWR_CLP3_CLP3(base, value) (ADC_WR_CLP3_CLP3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP2 register
+ */
+/*@{*/
+#define ADC_RD_CLP2(base)        (ADC_CLP2_REG(base))
+#define ADC_WR_CLP2(base, value) (ADC_CLP2_REG(base) = (value))
+#define ADC_RMW_CLP2(base, mask, value) (ADC_WR_CLP2(base, (ADC_RD_CLP2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) |  (value)))
+#define ADC_CLR_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) & ~(value)))
+#define ADC_TOG_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP2, field CLP2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP2_CLP2 field. */
+#define ADC_RD_CLP2_CLP2(base) ((ADC_CLP2_REG(base) & ADC_CLP2_CLP2_MASK) >> ADC_CLP2_CLP2_SHIFT)
+#define ADC_BRD_CLP2_CLP2(base) (ADC_RD_CLP2_CLP2(base))
+
+/*! @brief Set the CLP2 field to a new value. */
+#define ADC_WR_CLP2_CLP2(base, value) (ADC_RMW_CLP2(base, ADC_CLP2_CLP2_MASK, ADC_CLP2_CLP2(value)))
+#define ADC_BWR_CLP2_CLP2(base, value) (ADC_WR_CLP2_CLP2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP1 register
+ */
+/*@{*/
+#define ADC_RD_CLP1(base)        (ADC_CLP1_REG(base))
+#define ADC_WR_CLP1(base, value) (ADC_CLP1_REG(base) = (value))
+#define ADC_RMW_CLP1(base, mask, value) (ADC_WR_CLP1(base, (ADC_RD_CLP1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) |  (value)))
+#define ADC_CLR_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) & ~(value)))
+#define ADC_TOG_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP1, field CLP1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP1_CLP1 field. */
+#define ADC_RD_CLP1_CLP1(base) ((ADC_CLP1_REG(base) & ADC_CLP1_CLP1_MASK) >> ADC_CLP1_CLP1_SHIFT)
+#define ADC_BRD_CLP1_CLP1(base) (ADC_RD_CLP1_CLP1(base))
+
+/*! @brief Set the CLP1 field to a new value. */
+#define ADC_WR_CLP1_CLP1(base, value) (ADC_RMW_CLP1(base, ADC_CLP1_CLP1_MASK, ADC_CLP1_CLP1(value)))
+#define ADC_BWR_CLP1_CLP1(base, value) (ADC_WR_CLP1_CLP1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP0 register
+ */
+/*@{*/
+#define ADC_RD_CLP0(base)        (ADC_CLP0_REG(base))
+#define ADC_WR_CLP0(base, value) (ADC_CLP0_REG(base) = (value))
+#define ADC_RMW_CLP0(base, mask, value) (ADC_WR_CLP0(base, (ADC_RD_CLP0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) |  (value)))
+#define ADC_CLR_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) & ~(value)))
+#define ADC_TOG_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP0, field CLP0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP0_CLP0 field. */
+#define ADC_RD_CLP0_CLP0(base) ((ADC_CLP0_REG(base) & ADC_CLP0_CLP0_MASK) >> ADC_CLP0_CLP0_SHIFT)
+#define ADC_BRD_CLP0_CLP0(base) (ADC_RD_CLP0_CLP0(base))
+
+/*! @brief Set the CLP0 field to a new value. */
+#define ADC_WR_CLP0_CLP0(base, value) (ADC_RMW_CLP0(base, ADC_CLP0_CLP0_MASK, ADC_CLP0_CLP0(value)))
+#define ADC_BWR_CLP0_CLP0(base, value) (ADC_WR_CLP0_CLP0(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Minus-Side General Calibration Value (CLMx) registers contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
+ * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
+ * set when the self-calibration sequence is done, that is, CAL is cleared. If
+ * these registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMD register
+ */
+/*@{*/
+#define ADC_RD_CLMD(base)        (ADC_CLMD_REG(base))
+#define ADC_WR_CLMD(base, value) (ADC_CLMD_REG(base) = (value))
+#define ADC_RMW_CLMD(base, mask, value) (ADC_WR_CLMD(base, (ADC_RD_CLMD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) |  (value)))
+#define ADC_CLR_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) & ~(value)))
+#define ADC_TOG_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMD, field CLMD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMD_CLMD field. */
+#define ADC_RD_CLMD_CLMD(base) ((ADC_CLMD_REG(base) & ADC_CLMD_CLMD_MASK) >> ADC_CLMD_CLMD_SHIFT)
+#define ADC_BRD_CLMD_CLMD(base) (ADC_RD_CLMD_CLMD(base))
+
+/*! @brief Set the CLMD field to a new value. */
+#define ADC_WR_CLMD_CLMD(base, value) (ADC_RMW_CLMD(base, ADC_CLMD_CLMD_MASK, ADC_CLMD_CLMD(value)))
+#define ADC_BWR_CLMD_CLMD(base, value) (ADC_WR_CLMD_CLMD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMS register
+ */
+/*@{*/
+#define ADC_RD_CLMS(base)        (ADC_CLMS_REG(base))
+#define ADC_WR_CLMS(base, value) (ADC_CLMS_REG(base) = (value))
+#define ADC_RMW_CLMS(base, mask, value) (ADC_WR_CLMS(base, (ADC_RD_CLMS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) |  (value)))
+#define ADC_CLR_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) & ~(value)))
+#define ADC_TOG_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMS, field CLMS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMS_CLMS field. */
+#define ADC_RD_CLMS_CLMS(base) ((ADC_CLMS_REG(base) & ADC_CLMS_CLMS_MASK) >> ADC_CLMS_CLMS_SHIFT)
+#define ADC_BRD_CLMS_CLMS(base) (ADC_RD_CLMS_CLMS(base))
+
+/*! @brief Set the CLMS field to a new value. */
+#define ADC_WR_CLMS_CLMS(base, value) (ADC_RMW_CLMS(base, ADC_CLMS_CLMS_MASK, ADC_CLMS_CLMS(value)))
+#define ADC_BWR_CLMS_CLMS(base, value) (ADC_WR_CLMS_CLMS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM4 register
+ */
+/*@{*/
+#define ADC_RD_CLM4(base)        (ADC_CLM4_REG(base))
+#define ADC_WR_CLM4(base, value) (ADC_CLM4_REG(base) = (value))
+#define ADC_RMW_CLM4(base, mask, value) (ADC_WR_CLM4(base, (ADC_RD_CLM4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) |  (value)))
+#define ADC_CLR_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) & ~(value)))
+#define ADC_TOG_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM4, field CLM4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM4_CLM4 field. */
+#define ADC_RD_CLM4_CLM4(base) ((ADC_CLM4_REG(base) & ADC_CLM4_CLM4_MASK) >> ADC_CLM4_CLM4_SHIFT)
+#define ADC_BRD_CLM4_CLM4(base) (ADC_RD_CLM4_CLM4(base))
+
+/*! @brief Set the CLM4 field to a new value. */
+#define ADC_WR_CLM4_CLM4(base, value) (ADC_RMW_CLM4(base, ADC_CLM4_CLM4_MASK, ADC_CLM4_CLM4(value)))
+#define ADC_BWR_CLM4_CLM4(base, value) (ADC_WR_CLM4_CLM4(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM3 register
+ */
+/*@{*/
+#define ADC_RD_CLM3(base)        (ADC_CLM3_REG(base))
+#define ADC_WR_CLM3(base, value) (ADC_CLM3_REG(base) = (value))
+#define ADC_RMW_CLM3(base, mask, value) (ADC_WR_CLM3(base, (ADC_RD_CLM3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) |  (value)))
+#define ADC_CLR_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) & ~(value)))
+#define ADC_TOG_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM3, field CLM3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM3_CLM3 field. */
+#define ADC_RD_CLM3_CLM3(base) ((ADC_CLM3_REG(base) & ADC_CLM3_CLM3_MASK) >> ADC_CLM3_CLM3_SHIFT)
+#define ADC_BRD_CLM3_CLM3(base) (ADC_RD_CLM3_CLM3(base))
+
+/*! @brief Set the CLM3 field to a new value. */
+#define ADC_WR_CLM3_CLM3(base, value) (ADC_RMW_CLM3(base, ADC_CLM3_CLM3_MASK, ADC_CLM3_CLM3(value)))
+#define ADC_BWR_CLM3_CLM3(base, value) (ADC_WR_CLM3_CLM3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM2 register
+ */
+/*@{*/
+#define ADC_RD_CLM2(base)        (ADC_CLM2_REG(base))
+#define ADC_WR_CLM2(base, value) (ADC_CLM2_REG(base) = (value))
+#define ADC_RMW_CLM2(base, mask, value) (ADC_WR_CLM2(base, (ADC_RD_CLM2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) |  (value)))
+#define ADC_CLR_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) & ~(value)))
+#define ADC_TOG_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM2, field CLM2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM2_CLM2 field. */
+#define ADC_RD_CLM2_CLM2(base) ((ADC_CLM2_REG(base) & ADC_CLM2_CLM2_MASK) >> ADC_CLM2_CLM2_SHIFT)
+#define ADC_BRD_CLM2_CLM2(base) (ADC_RD_CLM2_CLM2(base))
+
+/*! @brief Set the CLM2 field to a new value. */
+#define ADC_WR_CLM2_CLM2(base, value) (ADC_RMW_CLM2(base, ADC_CLM2_CLM2_MASK, ADC_CLM2_CLM2(value)))
+#define ADC_BWR_CLM2_CLM2(base, value) (ADC_WR_CLM2_CLM2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM1 register
+ */
+/*@{*/
+#define ADC_RD_CLM1(base)        (ADC_CLM1_REG(base))
+#define ADC_WR_CLM1(base, value) (ADC_CLM1_REG(base) = (value))
+#define ADC_RMW_CLM1(base, mask, value) (ADC_WR_CLM1(base, (ADC_RD_CLM1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) |  (value)))
+#define ADC_CLR_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) & ~(value)))
+#define ADC_TOG_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM1, field CLM1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM1_CLM1 field. */
+#define ADC_RD_CLM1_CLM1(base) ((ADC_CLM1_REG(base) & ADC_CLM1_CLM1_MASK) >> ADC_CLM1_CLM1_SHIFT)
+#define ADC_BRD_CLM1_CLM1(base) (ADC_RD_CLM1_CLM1(base))
+
+/*! @brief Set the CLM1 field to a new value. */
+#define ADC_WR_CLM1_CLM1(base, value) (ADC_RMW_CLM1(base, ADC_CLM1_CLM1_MASK, ADC_CLM1_CLM1(value)))
+#define ADC_BWR_CLM1_CLM1(base, value) (ADC_WR_CLM1_CLM1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM0 register
+ */
+/*@{*/
+#define ADC_RD_CLM0(base)        (ADC_CLM0_REG(base))
+#define ADC_WR_CLM0(base, value) (ADC_CLM0_REG(base) = (value))
+#define ADC_RMW_CLM0(base, mask, value) (ADC_WR_CLM0(base, (ADC_RD_CLM0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) |  (value)))
+#define ADC_CLR_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) & ~(value)))
+#define ADC_TOG_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM0, field CLM0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM0_CLM0 field. */
+#define ADC_RD_CLM0_CLM0(base) ((ADC_CLM0_REG(base) & ADC_CLM0_CLM0_MASK) >> ADC_CLM0_CLM0_SHIFT)
+#define ADC_BRD_CLM0_CLM0(base) (ADC_RD_CLM0_CLM0(base))
+
+/*! @brief Set the CLM0 field to a new value. */
+#define ADC_WR_CLM0_CLM0(base, value) (ADC_RMW_CLM0(base, ADC_CLM0_CLM0_MASK, ADC_CLM0_CLM0(value)))
+#define ADC_BWR_CLM0_CLM0(base, value) (ADC_WR_CLM0_CLM0(base, value))
+/*@}*/
+
+/*
+ * MK64F12 AIPS
+ *
+ * AIPS-Lite Bridge
+ *
+ * Registers defined in this header file:
+ * - AIPS_MPRA - Master Privilege Register A
+ * - AIPS_PACRA - Peripheral Access Control Register
+ * - AIPS_PACRB - Peripheral Access Control Register
+ * - AIPS_PACRC - Peripheral Access Control Register
+ * - AIPS_PACRD - Peripheral Access Control Register
+ * - AIPS_PACRE - Peripheral Access Control Register
+ * - AIPS_PACRF - Peripheral Access Control Register
+ * - AIPS_PACRG - Peripheral Access Control Register
+ * - AIPS_PACRH - Peripheral Access Control Register
+ * - AIPS_PACRI - Peripheral Access Control Register
+ * - AIPS_PACRJ - Peripheral Access Control Register
+ * - AIPS_PACRK - Peripheral Access Control Register
+ * - AIPS_PACRL - Peripheral Access Control Register
+ * - AIPS_PACRM - Peripheral Access Control Register
+ * - AIPS_PACRN - Peripheral Access Control Register
+ * - AIPS_PACRO - Peripheral Access Control Register
+ * - AIPS_PACRP - Peripheral Access Control Register
+ * - AIPS_PACRU - Peripheral Access Control Register
+ */
+
+#define AIPS_INSTANCE_COUNT (2U) /*!< Number of instances of the AIPS module. */
+#define AIPS0_IDX (0U) /*!< Instance number for AIPS0. */
+#define AIPS1_IDX (1U) /*!< Instance number for AIPS1. */
+
+/*******************************************************************************
+ * AIPS_MPRA - Master Privilege Register A
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_MPRA - Master Privilege Register A (RW)
+ *
+ * Reset value: 0x77700000U
+ *
+ * The MPRA specifies identical 4-bit fields defining the access-privilege level
+ * associated with a bus master to various peripherals on the chip. The register
+ * provides one field per bus master. At reset, the default value loaded into
+ * the MPRA fields is chip-specific. See the chip configuration details for the
+ * value of a particular device. A register field that maps to an unimplemented
+ * master or peripheral behaves as read-only-zero. Each master is assigned a logical
+ * ID from 0 to 15. See the master logical ID assignment table in the
+ * chip-specific AIPS information.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_MPRA register
+ */
+/*@{*/
+#define AIPS_RD_MPRA(base)       (AIPS_MPRA_REG(base))
+#define AIPS_WR_MPRA(base, value) (AIPS_MPRA_REG(base) = (value))
+#define AIPS_RMW_MPRA(base, mask, value) (AIPS_WR_MPRA(base, (AIPS_RD_MPRA(base) & ~(mask)) | (value)))
+#define AIPS_SET_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) |  (value)))
+#define AIPS_CLR_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) & ~(value)))
+#define AIPS_TOG_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_MPRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_MPRA, field MPL5[8] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL5 field. */
+#define AIPS_RD_MPRA_MPL5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL5_MASK) >> AIPS_MPRA_MPL5_SHIFT)
+#define AIPS_BRD_MPRA_MPL5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL5_SHIFT))
+
+/*! @brief Set the MPL5 field to a new value. */
+#define AIPS_WR_MPRA_MPL5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL5_MASK, AIPS_MPRA_MPL5(value)))
+#define AIPS_BWR_MPRA_MPL5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW5[9] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW5 field. */
+#define AIPS_RD_MPRA_MTW5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW5_MASK) >> AIPS_MPRA_MTW5_SHIFT)
+#define AIPS_BRD_MPRA_MTW5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW5_SHIFT))
+
+/*! @brief Set the MTW5 field to a new value. */
+#define AIPS_WR_MPRA_MTW5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW5_MASK, AIPS_MPRA_MTW5(value)))
+#define AIPS_BWR_MPRA_MTW5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR5[10] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR5 field. */
+#define AIPS_RD_MPRA_MTR5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR5_MASK) >> AIPS_MPRA_MTR5_SHIFT)
+#define AIPS_BRD_MPRA_MTR5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR5_SHIFT))
+
+/*! @brief Set the MTR5 field to a new value. */
+#define AIPS_WR_MPRA_MTR5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR5_MASK, AIPS_MPRA_MTR5(value)))
+#define AIPS_BWR_MPRA_MTR5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL4[12] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL4 field. */
+#define AIPS_RD_MPRA_MPL4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL4_MASK) >> AIPS_MPRA_MPL4_SHIFT)
+#define AIPS_BRD_MPRA_MPL4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL4_SHIFT))
+
+/*! @brief Set the MPL4 field to a new value. */
+#define AIPS_WR_MPRA_MPL4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL4_MASK, AIPS_MPRA_MPL4(value)))
+#define AIPS_BWR_MPRA_MPL4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW4[13] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW4 field. */
+#define AIPS_RD_MPRA_MTW4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW4_MASK) >> AIPS_MPRA_MTW4_SHIFT)
+#define AIPS_BRD_MPRA_MTW4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW4_SHIFT))
+
+/*! @brief Set the MTW4 field to a new value. */
+#define AIPS_WR_MPRA_MTW4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW4_MASK, AIPS_MPRA_MTW4(value)))
+#define AIPS_BWR_MPRA_MTW4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR4[14] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR4 field. */
+#define AIPS_RD_MPRA_MTR4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR4_MASK) >> AIPS_MPRA_MTR4_SHIFT)
+#define AIPS_BRD_MPRA_MTR4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR4_SHIFT))
+
+/*! @brief Set the MTR4 field to a new value. */
+#define AIPS_WR_MPRA_MTR4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR4_MASK, AIPS_MPRA_MTR4(value)))
+#define AIPS_BWR_MPRA_MTR4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL3[16] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL3 field. */
+#define AIPS_RD_MPRA_MPL3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL3_MASK) >> AIPS_MPRA_MPL3_SHIFT)
+#define AIPS_BRD_MPRA_MPL3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL3_SHIFT))
+
+/*! @brief Set the MPL3 field to a new value. */
+#define AIPS_WR_MPRA_MPL3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL3_MASK, AIPS_MPRA_MPL3(value)))
+#define AIPS_BWR_MPRA_MPL3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW3[17] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW3 field. */
+#define AIPS_RD_MPRA_MTW3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW3_MASK) >> AIPS_MPRA_MTW3_SHIFT)
+#define AIPS_BRD_MPRA_MTW3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW3_SHIFT))
+
+/*! @brief Set the MTW3 field to a new value. */
+#define AIPS_WR_MPRA_MTW3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW3_MASK, AIPS_MPRA_MTW3(value)))
+#define AIPS_BWR_MPRA_MTW3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR3[18] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR3 field. */
+#define AIPS_RD_MPRA_MTR3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR3_MASK) >> AIPS_MPRA_MTR3_SHIFT)
+#define AIPS_BRD_MPRA_MTR3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR3_SHIFT))
+
+/*! @brief Set the MTR3 field to a new value. */
+#define AIPS_WR_MPRA_MTR3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR3_MASK, AIPS_MPRA_MTR3(value)))
+#define AIPS_BWR_MPRA_MTR3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL2[20] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL2 field. */
+#define AIPS_RD_MPRA_MPL2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL2_MASK) >> AIPS_MPRA_MPL2_SHIFT)
+#define AIPS_BRD_MPRA_MPL2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL2_SHIFT))
+
+/*! @brief Set the MPL2 field to a new value. */
+#define AIPS_WR_MPRA_MPL2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL2_MASK, AIPS_MPRA_MPL2(value)))
+#define AIPS_BWR_MPRA_MPL2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW2[21] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW2 field. */
+#define AIPS_RD_MPRA_MTW2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW2_MASK) >> AIPS_MPRA_MTW2_SHIFT)
+#define AIPS_BRD_MPRA_MTW2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW2_SHIFT))
+
+/*! @brief Set the MTW2 field to a new value. */
+#define AIPS_WR_MPRA_MTW2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW2_MASK, AIPS_MPRA_MTW2(value)))
+#define AIPS_BWR_MPRA_MTW2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR2[22] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR2 field. */
+#define AIPS_RD_MPRA_MTR2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR2_MASK) >> AIPS_MPRA_MTR2_SHIFT)
+#define AIPS_BRD_MPRA_MTR2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR2_SHIFT))
+
+/*! @brief Set the MTR2 field to a new value. */
+#define AIPS_WR_MPRA_MTR2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR2_MASK, AIPS_MPRA_MTR2(value)))
+#define AIPS_BWR_MPRA_MTR2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL1[24] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL1 field. */
+#define AIPS_RD_MPRA_MPL1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL1_MASK) >> AIPS_MPRA_MPL1_SHIFT)
+#define AIPS_BRD_MPRA_MPL1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL1_SHIFT))
+
+/*! @brief Set the MPL1 field to a new value. */
+#define AIPS_WR_MPRA_MPL1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL1_MASK, AIPS_MPRA_MPL1(value)))
+#define AIPS_BWR_MPRA_MPL1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW1[25] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW1 field. */
+#define AIPS_RD_MPRA_MTW1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW1_MASK) >> AIPS_MPRA_MTW1_SHIFT)
+#define AIPS_BRD_MPRA_MTW1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW1_SHIFT))
+
+/*! @brief Set the MTW1 field to a new value. */
+#define AIPS_WR_MPRA_MTW1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW1_MASK, AIPS_MPRA_MTW1(value)))
+#define AIPS_BWR_MPRA_MTW1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR1[26] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR1 field. */
+#define AIPS_RD_MPRA_MTR1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR1_MASK) >> AIPS_MPRA_MTR1_SHIFT)
+#define AIPS_BRD_MPRA_MTR1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR1_SHIFT))
+
+/*! @brief Set the MTR1 field to a new value. */
+#define AIPS_WR_MPRA_MTR1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR1_MASK, AIPS_MPRA_MTR1(value)))
+#define AIPS_BWR_MPRA_MTR1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL0[28] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL0 field. */
+#define AIPS_RD_MPRA_MPL0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL0_MASK) >> AIPS_MPRA_MPL0_SHIFT)
+#define AIPS_BRD_MPRA_MPL0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL0_SHIFT))
+
+/*! @brief Set the MPL0 field to a new value. */
+#define AIPS_WR_MPRA_MPL0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL0_MASK, AIPS_MPRA_MPL0(value)))
+#define AIPS_BWR_MPRA_MPL0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW0[29] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW0 field. */
+#define AIPS_RD_MPRA_MTW0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW0_MASK) >> AIPS_MPRA_MTW0_SHIFT)
+#define AIPS_BRD_MPRA_MTW0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW0_SHIFT))
+
+/*! @brief Set the MTW0 field to a new value. */
+#define AIPS_WR_MPRA_MTW0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW0_MASK, AIPS_MPRA_MTW0(value)))
+#define AIPS_BWR_MPRA_MTW0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR0[30] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR0 field. */
+#define AIPS_RD_MPRA_MTR0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR0_MASK) >> AIPS_MPRA_MTR0_SHIFT)
+#define AIPS_BRD_MPRA_MTR0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR0_SHIFT))
+
+/*! @brief Set the MTR0 field to a new value. */
+#define AIPS_WR_MPRA_MTR0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR0_MASK, AIPS_MPRA_MTR0(value)))
+#define AIPS_BWR_MPRA_MTR0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRA - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRA - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x50004000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRA register
+ */
+/*@{*/
+#define AIPS_RD_PACRA(base)      (AIPS_PACRA_REG(base))
+#define AIPS_WR_PACRA(base, value) (AIPS_PACRA_REG(base) = (value))
+#define AIPS_RMW_PACRA(base, mask, value) (AIPS_WR_PACRA(base, (AIPS_RD_PACRA(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) |  (value)))
+#define AIPS_CLR_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) & ~(value)))
+#define AIPS_TOG_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRA, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP7 field. */
+#define AIPS_RD_PACRA_TP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP7_MASK) >> AIPS_PACRA_TP7_SHIFT)
+#define AIPS_BRD_PACRA_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRA_TP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP7_MASK, AIPS_PACRA_TP7(value)))
+#define AIPS_BWR_PACRA_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP7 field. */
+#define AIPS_RD_PACRA_WP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP7_MASK) >> AIPS_PACRA_WP7_SHIFT)
+#define AIPS_BRD_PACRA_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRA_WP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP7_MASK, AIPS_PACRA_WP7(value)))
+#define AIPS_BWR_PACRA_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP7 field. */
+#define AIPS_RD_PACRA_SP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP7_MASK) >> AIPS_PACRA_SP7_SHIFT)
+#define AIPS_BRD_PACRA_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRA_SP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP7_MASK, AIPS_PACRA_SP7(value)))
+#define AIPS_BWR_PACRA_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP6 field. */
+#define AIPS_RD_PACRA_TP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP6_MASK) >> AIPS_PACRA_TP6_SHIFT)
+#define AIPS_BRD_PACRA_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRA_TP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP6_MASK, AIPS_PACRA_TP6(value)))
+#define AIPS_BWR_PACRA_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP6 field. */
+#define AIPS_RD_PACRA_WP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP6_MASK) >> AIPS_PACRA_WP6_SHIFT)
+#define AIPS_BRD_PACRA_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRA_WP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP6_MASK, AIPS_PACRA_WP6(value)))
+#define AIPS_BWR_PACRA_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP6 field. */
+#define AIPS_RD_PACRA_SP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP6_MASK) >> AIPS_PACRA_SP6_SHIFT)
+#define AIPS_BRD_PACRA_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRA_SP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP6_MASK, AIPS_PACRA_SP6(value)))
+#define AIPS_BWR_PACRA_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP5 field. */
+#define AIPS_RD_PACRA_TP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP5_MASK) >> AIPS_PACRA_TP5_SHIFT)
+#define AIPS_BRD_PACRA_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRA_TP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP5_MASK, AIPS_PACRA_TP5(value)))
+#define AIPS_BWR_PACRA_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP5 field. */
+#define AIPS_RD_PACRA_WP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP5_MASK) >> AIPS_PACRA_WP5_SHIFT)
+#define AIPS_BRD_PACRA_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRA_WP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP5_MASK, AIPS_PACRA_WP5(value)))
+#define AIPS_BWR_PACRA_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP5 field. */
+#define AIPS_RD_PACRA_SP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP5_MASK) >> AIPS_PACRA_SP5_SHIFT)
+#define AIPS_BRD_PACRA_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRA_SP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP5_MASK, AIPS_PACRA_SP5(value)))
+#define AIPS_BWR_PACRA_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP4 field. */
+#define AIPS_RD_PACRA_TP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP4_MASK) >> AIPS_PACRA_TP4_SHIFT)
+#define AIPS_BRD_PACRA_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRA_TP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP4_MASK, AIPS_PACRA_TP4(value)))
+#define AIPS_BWR_PACRA_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP4 field. */
+#define AIPS_RD_PACRA_WP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP4_MASK) >> AIPS_PACRA_WP4_SHIFT)
+#define AIPS_BRD_PACRA_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRA_WP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP4_MASK, AIPS_PACRA_WP4(value)))
+#define AIPS_BWR_PACRA_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP4 field. */
+#define AIPS_RD_PACRA_SP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP4_MASK) >> AIPS_PACRA_SP4_SHIFT)
+#define AIPS_BRD_PACRA_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRA_SP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP4_MASK, AIPS_PACRA_SP4(value)))
+#define AIPS_BWR_PACRA_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP3 field. */
+#define AIPS_RD_PACRA_TP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP3_MASK) >> AIPS_PACRA_TP3_SHIFT)
+#define AIPS_BRD_PACRA_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRA_TP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP3_MASK, AIPS_PACRA_TP3(value)))
+#define AIPS_BWR_PACRA_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP3 field. */
+#define AIPS_RD_PACRA_WP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP3_MASK) >> AIPS_PACRA_WP3_SHIFT)
+#define AIPS_BRD_PACRA_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRA_WP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP3_MASK, AIPS_PACRA_WP3(value)))
+#define AIPS_BWR_PACRA_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP3 field. */
+#define AIPS_RD_PACRA_SP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP3_MASK) >> AIPS_PACRA_SP3_SHIFT)
+#define AIPS_BRD_PACRA_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRA_SP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP3_MASK, AIPS_PACRA_SP3(value)))
+#define AIPS_BWR_PACRA_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP2 field. */
+#define AIPS_RD_PACRA_TP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP2_MASK) >> AIPS_PACRA_TP2_SHIFT)
+#define AIPS_BRD_PACRA_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRA_TP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP2_MASK, AIPS_PACRA_TP2(value)))
+#define AIPS_BWR_PACRA_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP2 field. */
+#define AIPS_RD_PACRA_WP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP2_MASK) >> AIPS_PACRA_WP2_SHIFT)
+#define AIPS_BRD_PACRA_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRA_WP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP2_MASK, AIPS_PACRA_WP2(value)))
+#define AIPS_BWR_PACRA_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP2 field. */
+#define AIPS_RD_PACRA_SP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP2_MASK) >> AIPS_PACRA_SP2_SHIFT)
+#define AIPS_BRD_PACRA_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRA_SP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP2_MASK, AIPS_PACRA_SP2(value)))
+#define AIPS_BWR_PACRA_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP1 field. */
+#define AIPS_RD_PACRA_TP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP1_MASK) >> AIPS_PACRA_TP1_SHIFT)
+#define AIPS_BRD_PACRA_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRA_TP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP1_MASK, AIPS_PACRA_TP1(value)))
+#define AIPS_BWR_PACRA_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP1 field. */
+#define AIPS_RD_PACRA_WP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP1_MASK) >> AIPS_PACRA_WP1_SHIFT)
+#define AIPS_BRD_PACRA_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRA_WP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP1_MASK, AIPS_PACRA_WP1(value)))
+#define AIPS_BWR_PACRA_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP1 field. */
+#define AIPS_RD_PACRA_SP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP1_MASK) >> AIPS_PACRA_SP1_SHIFT)
+#define AIPS_BRD_PACRA_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRA_SP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP1_MASK, AIPS_PACRA_SP1(value)))
+#define AIPS_BWR_PACRA_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP0 field. */
+#define AIPS_RD_PACRA_TP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP0_MASK) >> AIPS_PACRA_TP0_SHIFT)
+#define AIPS_BRD_PACRA_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRA_TP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP0_MASK, AIPS_PACRA_TP0(value)))
+#define AIPS_BWR_PACRA_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP0 field. */
+#define AIPS_RD_PACRA_WP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP0_MASK) >> AIPS_PACRA_WP0_SHIFT)
+#define AIPS_BRD_PACRA_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRA_WP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP0_MASK, AIPS_PACRA_WP0(value)))
+#define AIPS_BWR_PACRA_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP0 field. */
+#define AIPS_RD_PACRA_SP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP0_MASK) >> AIPS_PACRA_SP0_SHIFT)
+#define AIPS_BRD_PACRA_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRA_SP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP0_MASK, AIPS_PACRA_SP0(value)))
+#define AIPS_BWR_PACRA_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRB - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRB - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44004400U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRB register
+ */
+/*@{*/
+#define AIPS_RD_PACRB(base)      (AIPS_PACRB_REG(base))
+#define AIPS_WR_PACRB(base, value) (AIPS_PACRB_REG(base) = (value))
+#define AIPS_RMW_PACRB(base, mask, value) (AIPS_WR_PACRB(base, (AIPS_RD_PACRB(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) |  (value)))
+#define AIPS_CLR_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) & ~(value)))
+#define AIPS_TOG_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRB bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRB, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP7 field. */
+#define AIPS_RD_PACRB_TP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP7_MASK) >> AIPS_PACRB_TP7_SHIFT)
+#define AIPS_BRD_PACRB_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRB_TP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP7_MASK, AIPS_PACRB_TP7(value)))
+#define AIPS_BWR_PACRB_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP7 field. */
+#define AIPS_RD_PACRB_WP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP7_MASK) >> AIPS_PACRB_WP7_SHIFT)
+#define AIPS_BRD_PACRB_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRB_WP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP7_MASK, AIPS_PACRB_WP7(value)))
+#define AIPS_BWR_PACRB_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP7 field. */
+#define AIPS_RD_PACRB_SP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP7_MASK) >> AIPS_PACRB_SP7_SHIFT)
+#define AIPS_BRD_PACRB_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRB_SP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP7_MASK, AIPS_PACRB_SP7(value)))
+#define AIPS_BWR_PACRB_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP6 field. */
+#define AIPS_RD_PACRB_TP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP6_MASK) >> AIPS_PACRB_TP6_SHIFT)
+#define AIPS_BRD_PACRB_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRB_TP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP6_MASK, AIPS_PACRB_TP6(value)))
+#define AIPS_BWR_PACRB_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP6 field. */
+#define AIPS_RD_PACRB_WP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP6_MASK) >> AIPS_PACRB_WP6_SHIFT)
+#define AIPS_BRD_PACRB_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRB_WP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP6_MASK, AIPS_PACRB_WP6(value)))
+#define AIPS_BWR_PACRB_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP6 field. */
+#define AIPS_RD_PACRB_SP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP6_MASK) >> AIPS_PACRB_SP6_SHIFT)
+#define AIPS_BRD_PACRB_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRB_SP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP6_MASK, AIPS_PACRB_SP6(value)))
+#define AIPS_BWR_PACRB_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP5 field. */
+#define AIPS_RD_PACRB_TP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP5_MASK) >> AIPS_PACRB_TP5_SHIFT)
+#define AIPS_BRD_PACRB_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRB_TP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP5_MASK, AIPS_PACRB_TP5(value)))
+#define AIPS_BWR_PACRB_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP5 field. */
+#define AIPS_RD_PACRB_WP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP5_MASK) >> AIPS_PACRB_WP5_SHIFT)
+#define AIPS_BRD_PACRB_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRB_WP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP5_MASK, AIPS_PACRB_WP5(value)))
+#define AIPS_BWR_PACRB_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP5 field. */
+#define AIPS_RD_PACRB_SP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP5_MASK) >> AIPS_PACRB_SP5_SHIFT)
+#define AIPS_BRD_PACRB_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRB_SP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP5_MASK, AIPS_PACRB_SP5(value)))
+#define AIPS_BWR_PACRB_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP4 field. */
+#define AIPS_RD_PACRB_TP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP4_MASK) >> AIPS_PACRB_TP4_SHIFT)
+#define AIPS_BRD_PACRB_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRB_TP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP4_MASK, AIPS_PACRB_TP4(value)))
+#define AIPS_BWR_PACRB_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP4 field. */
+#define AIPS_RD_PACRB_WP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP4_MASK) >> AIPS_PACRB_WP4_SHIFT)
+#define AIPS_BRD_PACRB_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRB_WP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP4_MASK, AIPS_PACRB_WP4(value)))
+#define AIPS_BWR_PACRB_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP4 field. */
+#define AIPS_RD_PACRB_SP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP4_MASK) >> AIPS_PACRB_SP4_SHIFT)
+#define AIPS_BRD_PACRB_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRB_SP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP4_MASK, AIPS_PACRB_SP4(value)))
+#define AIPS_BWR_PACRB_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP3 field. */
+#define AIPS_RD_PACRB_TP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP3_MASK) >> AIPS_PACRB_TP3_SHIFT)
+#define AIPS_BRD_PACRB_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRB_TP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP3_MASK, AIPS_PACRB_TP3(value)))
+#define AIPS_BWR_PACRB_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP3 field. */
+#define AIPS_RD_PACRB_WP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP3_MASK) >> AIPS_PACRB_WP3_SHIFT)
+#define AIPS_BRD_PACRB_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRB_WP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP3_MASK, AIPS_PACRB_WP3(value)))
+#define AIPS_BWR_PACRB_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP3 field. */
+#define AIPS_RD_PACRB_SP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP3_MASK) >> AIPS_PACRB_SP3_SHIFT)
+#define AIPS_BRD_PACRB_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRB_SP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP3_MASK, AIPS_PACRB_SP3(value)))
+#define AIPS_BWR_PACRB_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP2 field. */
+#define AIPS_RD_PACRB_TP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP2_MASK) >> AIPS_PACRB_TP2_SHIFT)
+#define AIPS_BRD_PACRB_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRB_TP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP2_MASK, AIPS_PACRB_TP2(value)))
+#define AIPS_BWR_PACRB_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP2 field. */
+#define AIPS_RD_PACRB_WP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP2_MASK) >> AIPS_PACRB_WP2_SHIFT)
+#define AIPS_BRD_PACRB_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRB_WP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP2_MASK, AIPS_PACRB_WP2(value)))
+#define AIPS_BWR_PACRB_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP2 field. */
+#define AIPS_RD_PACRB_SP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP2_MASK) >> AIPS_PACRB_SP2_SHIFT)
+#define AIPS_BRD_PACRB_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRB_SP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP2_MASK, AIPS_PACRB_SP2(value)))
+#define AIPS_BWR_PACRB_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP1 field. */
+#define AIPS_RD_PACRB_TP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP1_MASK) >> AIPS_PACRB_TP1_SHIFT)
+#define AIPS_BRD_PACRB_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRB_TP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP1_MASK, AIPS_PACRB_TP1(value)))
+#define AIPS_BWR_PACRB_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP1 field. */
+#define AIPS_RD_PACRB_WP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP1_MASK) >> AIPS_PACRB_WP1_SHIFT)
+#define AIPS_BRD_PACRB_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRB_WP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP1_MASK, AIPS_PACRB_WP1(value)))
+#define AIPS_BWR_PACRB_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP1 field. */
+#define AIPS_RD_PACRB_SP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP1_MASK) >> AIPS_PACRB_SP1_SHIFT)
+#define AIPS_BRD_PACRB_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRB_SP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP1_MASK, AIPS_PACRB_SP1(value)))
+#define AIPS_BWR_PACRB_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP0 field. */
+#define AIPS_RD_PACRB_TP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP0_MASK) >> AIPS_PACRB_TP0_SHIFT)
+#define AIPS_BRD_PACRB_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRB_TP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP0_MASK, AIPS_PACRB_TP0(value)))
+#define AIPS_BWR_PACRB_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP0 field. */
+#define AIPS_RD_PACRB_WP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP0_MASK) >> AIPS_PACRB_WP0_SHIFT)
+#define AIPS_BRD_PACRB_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRB_WP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP0_MASK, AIPS_PACRB_WP0(value)))
+#define AIPS_BWR_PACRB_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP0 field. */
+#define AIPS_RD_PACRB_SP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP0_MASK) >> AIPS_PACRB_SP0_SHIFT)
+#define AIPS_BRD_PACRB_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRB_SP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP0_MASK, AIPS_PACRB_SP0(value)))
+#define AIPS_BWR_PACRB_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRC - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRC - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRC register
+ */
+/*@{*/
+#define AIPS_RD_PACRC(base)      (AIPS_PACRC_REG(base))
+#define AIPS_WR_PACRC(base, value) (AIPS_PACRC_REG(base) = (value))
+#define AIPS_RMW_PACRC(base, mask, value) (AIPS_WR_PACRC(base, (AIPS_RD_PACRC(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) |  (value)))
+#define AIPS_CLR_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) & ~(value)))
+#define AIPS_TOG_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRC bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRC, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP7 field. */
+#define AIPS_RD_PACRC_TP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP7_MASK) >> AIPS_PACRC_TP7_SHIFT)
+#define AIPS_BRD_PACRC_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRC_TP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP7_MASK, AIPS_PACRC_TP7(value)))
+#define AIPS_BWR_PACRC_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP7 field. */
+#define AIPS_RD_PACRC_WP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP7_MASK) >> AIPS_PACRC_WP7_SHIFT)
+#define AIPS_BRD_PACRC_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRC_WP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP7_MASK, AIPS_PACRC_WP7(value)))
+#define AIPS_BWR_PACRC_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP7 field. */
+#define AIPS_RD_PACRC_SP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP7_MASK) >> AIPS_PACRC_SP7_SHIFT)
+#define AIPS_BRD_PACRC_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRC_SP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP7_MASK, AIPS_PACRC_SP7(value)))
+#define AIPS_BWR_PACRC_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP6 field. */
+#define AIPS_RD_PACRC_TP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP6_MASK) >> AIPS_PACRC_TP6_SHIFT)
+#define AIPS_BRD_PACRC_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRC_TP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP6_MASK, AIPS_PACRC_TP6(value)))
+#define AIPS_BWR_PACRC_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP6 field. */
+#define AIPS_RD_PACRC_WP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP6_MASK) >> AIPS_PACRC_WP6_SHIFT)
+#define AIPS_BRD_PACRC_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRC_WP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP6_MASK, AIPS_PACRC_WP6(value)))
+#define AIPS_BWR_PACRC_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP6 field. */
+#define AIPS_RD_PACRC_SP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP6_MASK) >> AIPS_PACRC_SP6_SHIFT)
+#define AIPS_BRD_PACRC_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRC_SP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP6_MASK, AIPS_PACRC_SP6(value)))
+#define AIPS_BWR_PACRC_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP5 field. */
+#define AIPS_RD_PACRC_TP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP5_MASK) >> AIPS_PACRC_TP5_SHIFT)
+#define AIPS_BRD_PACRC_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRC_TP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP5_MASK, AIPS_PACRC_TP5(value)))
+#define AIPS_BWR_PACRC_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP5 field. */
+#define AIPS_RD_PACRC_WP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP5_MASK) >> AIPS_PACRC_WP5_SHIFT)
+#define AIPS_BRD_PACRC_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRC_WP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP5_MASK, AIPS_PACRC_WP5(value)))
+#define AIPS_BWR_PACRC_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP5 field. */
+#define AIPS_RD_PACRC_SP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP5_MASK) >> AIPS_PACRC_SP5_SHIFT)
+#define AIPS_BRD_PACRC_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRC_SP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP5_MASK, AIPS_PACRC_SP5(value)))
+#define AIPS_BWR_PACRC_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP4 field. */
+#define AIPS_RD_PACRC_TP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP4_MASK) >> AIPS_PACRC_TP4_SHIFT)
+#define AIPS_BRD_PACRC_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRC_TP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP4_MASK, AIPS_PACRC_TP4(value)))
+#define AIPS_BWR_PACRC_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP4 field. */
+#define AIPS_RD_PACRC_WP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP4_MASK) >> AIPS_PACRC_WP4_SHIFT)
+#define AIPS_BRD_PACRC_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRC_WP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP4_MASK, AIPS_PACRC_WP4(value)))
+#define AIPS_BWR_PACRC_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP4 field. */
+#define AIPS_RD_PACRC_SP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP4_MASK) >> AIPS_PACRC_SP4_SHIFT)
+#define AIPS_BRD_PACRC_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRC_SP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP4_MASK, AIPS_PACRC_SP4(value)))
+#define AIPS_BWR_PACRC_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP3 field. */
+#define AIPS_RD_PACRC_TP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP3_MASK) >> AIPS_PACRC_TP3_SHIFT)
+#define AIPS_BRD_PACRC_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRC_TP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP3_MASK, AIPS_PACRC_TP3(value)))
+#define AIPS_BWR_PACRC_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP3 field. */
+#define AIPS_RD_PACRC_WP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP3_MASK) >> AIPS_PACRC_WP3_SHIFT)
+#define AIPS_BRD_PACRC_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRC_WP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP3_MASK, AIPS_PACRC_WP3(value)))
+#define AIPS_BWR_PACRC_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP3 field. */
+#define AIPS_RD_PACRC_SP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP3_MASK) >> AIPS_PACRC_SP3_SHIFT)
+#define AIPS_BRD_PACRC_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRC_SP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP3_MASK, AIPS_PACRC_SP3(value)))
+#define AIPS_BWR_PACRC_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP2 field. */
+#define AIPS_RD_PACRC_TP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP2_MASK) >> AIPS_PACRC_TP2_SHIFT)
+#define AIPS_BRD_PACRC_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRC_TP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP2_MASK, AIPS_PACRC_TP2(value)))
+#define AIPS_BWR_PACRC_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP2 field. */
+#define AIPS_RD_PACRC_WP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP2_MASK) >> AIPS_PACRC_WP2_SHIFT)
+#define AIPS_BRD_PACRC_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRC_WP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP2_MASK, AIPS_PACRC_WP2(value)))
+#define AIPS_BWR_PACRC_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP2 field. */
+#define AIPS_RD_PACRC_SP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP2_MASK) >> AIPS_PACRC_SP2_SHIFT)
+#define AIPS_BRD_PACRC_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRC_SP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP2_MASK, AIPS_PACRC_SP2(value)))
+#define AIPS_BWR_PACRC_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP1 field. */
+#define AIPS_RD_PACRC_TP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP1_MASK) >> AIPS_PACRC_TP1_SHIFT)
+#define AIPS_BRD_PACRC_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRC_TP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP1_MASK, AIPS_PACRC_TP1(value)))
+#define AIPS_BWR_PACRC_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP1 field. */
+#define AIPS_RD_PACRC_WP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP1_MASK) >> AIPS_PACRC_WP1_SHIFT)
+#define AIPS_BRD_PACRC_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRC_WP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP1_MASK, AIPS_PACRC_WP1(value)))
+#define AIPS_BWR_PACRC_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP1 field. */
+#define AIPS_RD_PACRC_SP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP1_MASK) >> AIPS_PACRC_SP1_SHIFT)
+#define AIPS_BRD_PACRC_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRC_SP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP1_MASK, AIPS_PACRC_SP1(value)))
+#define AIPS_BWR_PACRC_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP0 field. */
+#define AIPS_RD_PACRC_TP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP0_MASK) >> AIPS_PACRC_TP0_SHIFT)
+#define AIPS_BRD_PACRC_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRC_TP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP0_MASK, AIPS_PACRC_TP0(value)))
+#define AIPS_BWR_PACRC_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP0 field. */
+#define AIPS_RD_PACRC_WP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP0_MASK) >> AIPS_PACRC_WP0_SHIFT)
+#define AIPS_BRD_PACRC_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRC_WP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP0_MASK, AIPS_PACRC_WP0(value)))
+#define AIPS_BWR_PACRC_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP0 field. */
+#define AIPS_RD_PACRC_SP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP0_MASK) >> AIPS_PACRC_SP0_SHIFT)
+#define AIPS_BRD_PACRC_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRC_SP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP0_MASK, AIPS_PACRC_SP0(value)))
+#define AIPS_BWR_PACRC_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRD - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRD - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRD register
+ */
+/*@{*/
+#define AIPS_RD_PACRD(base)      (AIPS_PACRD_REG(base))
+#define AIPS_WR_PACRD(base, value) (AIPS_PACRD_REG(base) = (value))
+#define AIPS_RMW_PACRD(base, mask, value) (AIPS_WR_PACRD(base, (AIPS_RD_PACRD(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) |  (value)))
+#define AIPS_CLR_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) & ~(value)))
+#define AIPS_TOG_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRD bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRD, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP7 field. */
+#define AIPS_RD_PACRD_TP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP7_MASK) >> AIPS_PACRD_TP7_SHIFT)
+#define AIPS_BRD_PACRD_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRD_TP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP7_MASK, AIPS_PACRD_TP7(value)))
+#define AIPS_BWR_PACRD_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP7 field. */
+#define AIPS_RD_PACRD_WP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP7_MASK) >> AIPS_PACRD_WP7_SHIFT)
+#define AIPS_BRD_PACRD_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRD_WP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP7_MASK, AIPS_PACRD_WP7(value)))
+#define AIPS_BWR_PACRD_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP7 field. */
+#define AIPS_RD_PACRD_SP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP7_MASK) >> AIPS_PACRD_SP7_SHIFT)
+#define AIPS_BRD_PACRD_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRD_SP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP7_MASK, AIPS_PACRD_SP7(value)))
+#define AIPS_BWR_PACRD_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP6 field. */
+#define AIPS_RD_PACRD_TP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP6_MASK) >> AIPS_PACRD_TP6_SHIFT)
+#define AIPS_BRD_PACRD_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRD_TP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP6_MASK, AIPS_PACRD_TP6(value)))
+#define AIPS_BWR_PACRD_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP6 field. */
+#define AIPS_RD_PACRD_WP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP6_MASK) >> AIPS_PACRD_WP6_SHIFT)
+#define AIPS_BRD_PACRD_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRD_WP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP6_MASK, AIPS_PACRD_WP6(value)))
+#define AIPS_BWR_PACRD_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP6 field. */
+#define AIPS_RD_PACRD_SP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP6_MASK) >> AIPS_PACRD_SP6_SHIFT)
+#define AIPS_BRD_PACRD_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRD_SP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP6_MASK, AIPS_PACRD_SP6(value)))
+#define AIPS_BWR_PACRD_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP5 field. */
+#define AIPS_RD_PACRD_TP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP5_MASK) >> AIPS_PACRD_TP5_SHIFT)
+#define AIPS_BRD_PACRD_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRD_TP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP5_MASK, AIPS_PACRD_TP5(value)))
+#define AIPS_BWR_PACRD_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP5 field. */
+#define AIPS_RD_PACRD_WP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP5_MASK) >> AIPS_PACRD_WP5_SHIFT)
+#define AIPS_BRD_PACRD_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRD_WP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP5_MASK, AIPS_PACRD_WP5(value)))
+#define AIPS_BWR_PACRD_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP5 field. */
+#define AIPS_RD_PACRD_SP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP5_MASK) >> AIPS_PACRD_SP5_SHIFT)
+#define AIPS_BRD_PACRD_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRD_SP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP5_MASK, AIPS_PACRD_SP5(value)))
+#define AIPS_BWR_PACRD_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP4 field. */
+#define AIPS_RD_PACRD_TP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP4_MASK) >> AIPS_PACRD_TP4_SHIFT)
+#define AIPS_BRD_PACRD_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRD_TP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP4_MASK, AIPS_PACRD_TP4(value)))
+#define AIPS_BWR_PACRD_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP4 field. */
+#define AIPS_RD_PACRD_WP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP4_MASK) >> AIPS_PACRD_WP4_SHIFT)
+#define AIPS_BRD_PACRD_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRD_WP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP4_MASK, AIPS_PACRD_WP4(value)))
+#define AIPS_BWR_PACRD_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP4 field. */
+#define AIPS_RD_PACRD_SP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP4_MASK) >> AIPS_PACRD_SP4_SHIFT)
+#define AIPS_BRD_PACRD_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRD_SP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP4_MASK, AIPS_PACRD_SP4(value)))
+#define AIPS_BWR_PACRD_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP3 field. */
+#define AIPS_RD_PACRD_TP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP3_MASK) >> AIPS_PACRD_TP3_SHIFT)
+#define AIPS_BRD_PACRD_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRD_TP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP3_MASK, AIPS_PACRD_TP3(value)))
+#define AIPS_BWR_PACRD_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP3 field. */
+#define AIPS_RD_PACRD_WP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP3_MASK) >> AIPS_PACRD_WP3_SHIFT)
+#define AIPS_BRD_PACRD_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRD_WP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP3_MASK, AIPS_PACRD_WP3(value)))
+#define AIPS_BWR_PACRD_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP3 field. */
+#define AIPS_RD_PACRD_SP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP3_MASK) >> AIPS_PACRD_SP3_SHIFT)
+#define AIPS_BRD_PACRD_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRD_SP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP3_MASK, AIPS_PACRD_SP3(value)))
+#define AIPS_BWR_PACRD_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP2 field. */
+#define AIPS_RD_PACRD_TP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP2_MASK) >> AIPS_PACRD_TP2_SHIFT)
+#define AIPS_BRD_PACRD_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRD_TP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP2_MASK, AIPS_PACRD_TP2(value)))
+#define AIPS_BWR_PACRD_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP2 field. */
+#define AIPS_RD_PACRD_WP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP2_MASK) >> AIPS_PACRD_WP2_SHIFT)
+#define AIPS_BRD_PACRD_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRD_WP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP2_MASK, AIPS_PACRD_WP2(value)))
+#define AIPS_BWR_PACRD_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP2 field. */
+#define AIPS_RD_PACRD_SP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP2_MASK) >> AIPS_PACRD_SP2_SHIFT)
+#define AIPS_BRD_PACRD_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRD_SP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP2_MASK, AIPS_PACRD_SP2(value)))
+#define AIPS_BWR_PACRD_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP1 field. */
+#define AIPS_RD_PACRD_TP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP1_MASK) >> AIPS_PACRD_TP1_SHIFT)
+#define AIPS_BRD_PACRD_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRD_TP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP1_MASK, AIPS_PACRD_TP1(value)))
+#define AIPS_BWR_PACRD_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP1 field. */
+#define AIPS_RD_PACRD_WP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP1_MASK) >> AIPS_PACRD_WP1_SHIFT)
+#define AIPS_BRD_PACRD_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRD_WP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP1_MASK, AIPS_PACRD_WP1(value)))
+#define AIPS_BWR_PACRD_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP1 field. */
+#define AIPS_RD_PACRD_SP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP1_MASK) >> AIPS_PACRD_SP1_SHIFT)
+#define AIPS_BRD_PACRD_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRD_SP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP1_MASK, AIPS_PACRD_SP1(value)))
+#define AIPS_BWR_PACRD_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP0 field. */
+#define AIPS_RD_PACRD_TP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP0_MASK) >> AIPS_PACRD_TP0_SHIFT)
+#define AIPS_BRD_PACRD_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRD_TP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP0_MASK, AIPS_PACRD_TP0(value)))
+#define AIPS_BWR_PACRD_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP0 field. */
+#define AIPS_RD_PACRD_WP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP0_MASK) >> AIPS_PACRD_WP0_SHIFT)
+#define AIPS_BRD_PACRD_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRD_WP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP0_MASK, AIPS_PACRD_WP0(value)))
+#define AIPS_BWR_PACRD_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP0 field. */
+#define AIPS_RD_PACRD_SP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP0_MASK) >> AIPS_PACRD_SP0_SHIFT)
+#define AIPS_BRD_PACRD_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRD_SP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP0_MASK, AIPS_PACRD_SP0(value)))
+#define AIPS_BWR_PACRD_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRE - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRE - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRE register
+ */
+/*@{*/
+#define AIPS_RD_PACRE(base)      (AIPS_PACRE_REG(base))
+#define AIPS_WR_PACRE(base, value) (AIPS_PACRE_REG(base) = (value))
+#define AIPS_RMW_PACRE(base, mask, value) (AIPS_WR_PACRE(base, (AIPS_RD_PACRE(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) |  (value)))
+#define AIPS_CLR_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) & ~(value)))
+#define AIPS_TOG_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRE bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRE, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP7 field. */
+#define AIPS_RD_PACRE_TP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP7_MASK) >> AIPS_PACRE_TP7_SHIFT)
+#define AIPS_BRD_PACRE_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRE_TP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP7_MASK, AIPS_PACRE_TP7(value)))
+#define AIPS_BWR_PACRE_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP7 field. */
+#define AIPS_RD_PACRE_WP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP7_MASK) >> AIPS_PACRE_WP7_SHIFT)
+#define AIPS_BRD_PACRE_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRE_WP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP7_MASK, AIPS_PACRE_WP7(value)))
+#define AIPS_BWR_PACRE_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP7 field. */
+#define AIPS_RD_PACRE_SP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP7_MASK) >> AIPS_PACRE_SP7_SHIFT)
+#define AIPS_BRD_PACRE_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRE_SP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP7_MASK, AIPS_PACRE_SP7(value)))
+#define AIPS_BWR_PACRE_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP6 field. */
+#define AIPS_RD_PACRE_TP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP6_MASK) >> AIPS_PACRE_TP6_SHIFT)
+#define AIPS_BRD_PACRE_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRE_TP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP6_MASK, AIPS_PACRE_TP6(value)))
+#define AIPS_BWR_PACRE_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP6 field. */
+#define AIPS_RD_PACRE_WP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP6_MASK) >> AIPS_PACRE_WP6_SHIFT)
+#define AIPS_BRD_PACRE_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRE_WP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP6_MASK, AIPS_PACRE_WP6(value)))
+#define AIPS_BWR_PACRE_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP6 field. */
+#define AIPS_RD_PACRE_SP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP6_MASK) >> AIPS_PACRE_SP6_SHIFT)
+#define AIPS_BRD_PACRE_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRE_SP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP6_MASK, AIPS_PACRE_SP6(value)))
+#define AIPS_BWR_PACRE_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP5 field. */
+#define AIPS_RD_PACRE_TP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP5_MASK) >> AIPS_PACRE_TP5_SHIFT)
+#define AIPS_BRD_PACRE_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRE_TP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP5_MASK, AIPS_PACRE_TP5(value)))
+#define AIPS_BWR_PACRE_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP5 field. */
+#define AIPS_RD_PACRE_WP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP5_MASK) >> AIPS_PACRE_WP5_SHIFT)
+#define AIPS_BRD_PACRE_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRE_WP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP5_MASK, AIPS_PACRE_WP5(value)))
+#define AIPS_BWR_PACRE_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP5 field. */
+#define AIPS_RD_PACRE_SP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP5_MASK) >> AIPS_PACRE_SP5_SHIFT)
+#define AIPS_BRD_PACRE_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRE_SP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP5_MASK, AIPS_PACRE_SP5(value)))
+#define AIPS_BWR_PACRE_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP4 field. */
+#define AIPS_RD_PACRE_TP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP4_MASK) >> AIPS_PACRE_TP4_SHIFT)
+#define AIPS_BRD_PACRE_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRE_TP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP4_MASK, AIPS_PACRE_TP4(value)))
+#define AIPS_BWR_PACRE_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP4 field. */
+#define AIPS_RD_PACRE_WP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP4_MASK) >> AIPS_PACRE_WP4_SHIFT)
+#define AIPS_BRD_PACRE_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRE_WP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP4_MASK, AIPS_PACRE_WP4(value)))
+#define AIPS_BWR_PACRE_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP4 field. */
+#define AIPS_RD_PACRE_SP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP4_MASK) >> AIPS_PACRE_SP4_SHIFT)
+#define AIPS_BRD_PACRE_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRE_SP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP4_MASK, AIPS_PACRE_SP4(value)))
+#define AIPS_BWR_PACRE_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP3 field. */
+#define AIPS_RD_PACRE_TP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP3_MASK) >> AIPS_PACRE_TP3_SHIFT)
+#define AIPS_BRD_PACRE_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRE_TP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP3_MASK, AIPS_PACRE_TP3(value)))
+#define AIPS_BWR_PACRE_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP3 field. */
+#define AIPS_RD_PACRE_WP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP3_MASK) >> AIPS_PACRE_WP3_SHIFT)
+#define AIPS_BRD_PACRE_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRE_WP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP3_MASK, AIPS_PACRE_WP3(value)))
+#define AIPS_BWR_PACRE_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP3 field. */
+#define AIPS_RD_PACRE_SP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP3_MASK) >> AIPS_PACRE_SP3_SHIFT)
+#define AIPS_BRD_PACRE_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRE_SP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP3_MASK, AIPS_PACRE_SP3(value)))
+#define AIPS_BWR_PACRE_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP2 field. */
+#define AIPS_RD_PACRE_TP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP2_MASK) >> AIPS_PACRE_TP2_SHIFT)
+#define AIPS_BRD_PACRE_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRE_TP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP2_MASK, AIPS_PACRE_TP2(value)))
+#define AIPS_BWR_PACRE_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP2 field. */
+#define AIPS_RD_PACRE_WP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP2_MASK) >> AIPS_PACRE_WP2_SHIFT)
+#define AIPS_BRD_PACRE_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRE_WP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP2_MASK, AIPS_PACRE_WP2(value)))
+#define AIPS_BWR_PACRE_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP2 field. */
+#define AIPS_RD_PACRE_SP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP2_MASK) >> AIPS_PACRE_SP2_SHIFT)
+#define AIPS_BRD_PACRE_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRE_SP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP2_MASK, AIPS_PACRE_SP2(value)))
+#define AIPS_BWR_PACRE_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP1 field. */
+#define AIPS_RD_PACRE_TP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP1_MASK) >> AIPS_PACRE_TP1_SHIFT)
+#define AIPS_BRD_PACRE_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRE_TP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP1_MASK, AIPS_PACRE_TP1(value)))
+#define AIPS_BWR_PACRE_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP1 field. */
+#define AIPS_RD_PACRE_WP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP1_MASK) >> AIPS_PACRE_WP1_SHIFT)
+#define AIPS_BRD_PACRE_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRE_WP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP1_MASK, AIPS_PACRE_WP1(value)))
+#define AIPS_BWR_PACRE_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP1 field. */
+#define AIPS_RD_PACRE_SP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP1_MASK) >> AIPS_PACRE_SP1_SHIFT)
+#define AIPS_BRD_PACRE_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRE_SP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP1_MASK, AIPS_PACRE_SP1(value)))
+#define AIPS_BWR_PACRE_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP0 field. */
+#define AIPS_RD_PACRE_TP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP0_MASK) >> AIPS_PACRE_TP0_SHIFT)
+#define AIPS_BRD_PACRE_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRE_TP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP0_MASK, AIPS_PACRE_TP0(value)))
+#define AIPS_BWR_PACRE_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP0 field. */
+#define AIPS_RD_PACRE_WP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP0_MASK) >> AIPS_PACRE_WP0_SHIFT)
+#define AIPS_BRD_PACRE_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRE_WP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP0_MASK, AIPS_PACRE_WP0(value)))
+#define AIPS_BWR_PACRE_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP0 field. */
+#define AIPS_RD_PACRE_SP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP0_MASK) >> AIPS_PACRE_SP0_SHIFT)
+#define AIPS_BRD_PACRE_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRE_SP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP0_MASK, AIPS_PACRE_SP0(value)))
+#define AIPS_BWR_PACRE_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRF - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRF - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRF register
+ */
+/*@{*/
+#define AIPS_RD_PACRF(base)      (AIPS_PACRF_REG(base))
+#define AIPS_WR_PACRF(base, value) (AIPS_PACRF_REG(base) = (value))
+#define AIPS_RMW_PACRF(base, mask, value) (AIPS_WR_PACRF(base, (AIPS_RD_PACRF(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) |  (value)))
+#define AIPS_CLR_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) & ~(value)))
+#define AIPS_TOG_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRF bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRF, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP7 field. */
+#define AIPS_RD_PACRF_TP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP7_MASK) >> AIPS_PACRF_TP7_SHIFT)
+#define AIPS_BRD_PACRF_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRF_TP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP7_MASK, AIPS_PACRF_TP7(value)))
+#define AIPS_BWR_PACRF_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP7 field. */
+#define AIPS_RD_PACRF_WP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP7_MASK) >> AIPS_PACRF_WP7_SHIFT)
+#define AIPS_BRD_PACRF_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRF_WP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP7_MASK, AIPS_PACRF_WP7(value)))
+#define AIPS_BWR_PACRF_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP7 field. */
+#define AIPS_RD_PACRF_SP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP7_MASK) >> AIPS_PACRF_SP7_SHIFT)
+#define AIPS_BRD_PACRF_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRF_SP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP7_MASK, AIPS_PACRF_SP7(value)))
+#define AIPS_BWR_PACRF_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP6 field. */
+#define AIPS_RD_PACRF_TP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP6_MASK) >> AIPS_PACRF_TP6_SHIFT)
+#define AIPS_BRD_PACRF_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRF_TP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP6_MASK, AIPS_PACRF_TP6(value)))
+#define AIPS_BWR_PACRF_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP6 field. */
+#define AIPS_RD_PACRF_WP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP6_MASK) >> AIPS_PACRF_WP6_SHIFT)
+#define AIPS_BRD_PACRF_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRF_WP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP6_MASK, AIPS_PACRF_WP6(value)))
+#define AIPS_BWR_PACRF_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP6 field. */
+#define AIPS_RD_PACRF_SP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP6_MASK) >> AIPS_PACRF_SP6_SHIFT)
+#define AIPS_BRD_PACRF_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRF_SP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP6_MASK, AIPS_PACRF_SP6(value)))
+#define AIPS_BWR_PACRF_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP5 field. */
+#define AIPS_RD_PACRF_TP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP5_MASK) >> AIPS_PACRF_TP5_SHIFT)
+#define AIPS_BRD_PACRF_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRF_TP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP5_MASK, AIPS_PACRF_TP5(value)))
+#define AIPS_BWR_PACRF_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP5 field. */
+#define AIPS_RD_PACRF_WP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP5_MASK) >> AIPS_PACRF_WP5_SHIFT)
+#define AIPS_BRD_PACRF_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRF_WP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP5_MASK, AIPS_PACRF_WP5(value)))
+#define AIPS_BWR_PACRF_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP5 field. */
+#define AIPS_RD_PACRF_SP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP5_MASK) >> AIPS_PACRF_SP5_SHIFT)
+#define AIPS_BRD_PACRF_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRF_SP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP5_MASK, AIPS_PACRF_SP5(value)))
+#define AIPS_BWR_PACRF_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP4 field. */
+#define AIPS_RD_PACRF_TP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP4_MASK) >> AIPS_PACRF_TP4_SHIFT)
+#define AIPS_BRD_PACRF_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRF_TP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP4_MASK, AIPS_PACRF_TP4(value)))
+#define AIPS_BWR_PACRF_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP4 field. */
+#define AIPS_RD_PACRF_WP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP4_MASK) >> AIPS_PACRF_WP4_SHIFT)
+#define AIPS_BRD_PACRF_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRF_WP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP4_MASK, AIPS_PACRF_WP4(value)))
+#define AIPS_BWR_PACRF_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP4 field. */
+#define AIPS_RD_PACRF_SP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP4_MASK) >> AIPS_PACRF_SP4_SHIFT)
+#define AIPS_BRD_PACRF_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRF_SP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP4_MASK, AIPS_PACRF_SP4(value)))
+#define AIPS_BWR_PACRF_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP3 field. */
+#define AIPS_RD_PACRF_TP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP3_MASK) >> AIPS_PACRF_TP3_SHIFT)
+#define AIPS_BRD_PACRF_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRF_TP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP3_MASK, AIPS_PACRF_TP3(value)))
+#define AIPS_BWR_PACRF_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP3 field. */
+#define AIPS_RD_PACRF_WP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP3_MASK) >> AIPS_PACRF_WP3_SHIFT)
+#define AIPS_BRD_PACRF_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRF_WP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP3_MASK, AIPS_PACRF_WP3(value)))
+#define AIPS_BWR_PACRF_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP3 field. */
+#define AIPS_RD_PACRF_SP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP3_MASK) >> AIPS_PACRF_SP3_SHIFT)
+#define AIPS_BRD_PACRF_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRF_SP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP3_MASK, AIPS_PACRF_SP3(value)))
+#define AIPS_BWR_PACRF_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP2 field. */
+#define AIPS_RD_PACRF_TP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP2_MASK) >> AIPS_PACRF_TP2_SHIFT)
+#define AIPS_BRD_PACRF_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRF_TP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP2_MASK, AIPS_PACRF_TP2(value)))
+#define AIPS_BWR_PACRF_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP2 field. */
+#define AIPS_RD_PACRF_WP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP2_MASK) >> AIPS_PACRF_WP2_SHIFT)
+#define AIPS_BRD_PACRF_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRF_WP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP2_MASK, AIPS_PACRF_WP2(value)))
+#define AIPS_BWR_PACRF_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP2 field. */
+#define AIPS_RD_PACRF_SP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP2_MASK) >> AIPS_PACRF_SP2_SHIFT)
+#define AIPS_BRD_PACRF_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRF_SP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP2_MASK, AIPS_PACRF_SP2(value)))
+#define AIPS_BWR_PACRF_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP1 field. */
+#define AIPS_RD_PACRF_TP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP1_MASK) >> AIPS_PACRF_TP1_SHIFT)
+#define AIPS_BRD_PACRF_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRF_TP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP1_MASK, AIPS_PACRF_TP1(value)))
+#define AIPS_BWR_PACRF_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP1 field. */
+#define AIPS_RD_PACRF_WP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP1_MASK) >> AIPS_PACRF_WP1_SHIFT)
+#define AIPS_BRD_PACRF_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRF_WP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP1_MASK, AIPS_PACRF_WP1(value)))
+#define AIPS_BWR_PACRF_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP1 field. */
+#define AIPS_RD_PACRF_SP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP1_MASK) >> AIPS_PACRF_SP1_SHIFT)
+#define AIPS_BRD_PACRF_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRF_SP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP1_MASK, AIPS_PACRF_SP1(value)))
+#define AIPS_BWR_PACRF_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP0 field. */
+#define AIPS_RD_PACRF_TP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP0_MASK) >> AIPS_PACRF_TP0_SHIFT)
+#define AIPS_BRD_PACRF_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRF_TP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP0_MASK, AIPS_PACRF_TP0(value)))
+#define AIPS_BWR_PACRF_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP0 field. */
+#define AIPS_RD_PACRF_WP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP0_MASK) >> AIPS_PACRF_WP0_SHIFT)
+#define AIPS_BRD_PACRF_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRF_WP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP0_MASK, AIPS_PACRF_WP0(value)))
+#define AIPS_BWR_PACRF_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP0 field. */
+#define AIPS_RD_PACRF_SP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP0_MASK) >> AIPS_PACRF_SP0_SHIFT)
+#define AIPS_BRD_PACRF_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRF_SP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP0_MASK, AIPS_PACRF_SP0(value)))
+#define AIPS_BWR_PACRF_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRG - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRG - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRG register
+ */
+/*@{*/
+#define AIPS_RD_PACRG(base)      (AIPS_PACRG_REG(base))
+#define AIPS_WR_PACRG(base, value) (AIPS_PACRG_REG(base) = (value))
+#define AIPS_RMW_PACRG(base, mask, value) (AIPS_WR_PACRG(base, (AIPS_RD_PACRG(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) |  (value)))
+#define AIPS_CLR_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) & ~(value)))
+#define AIPS_TOG_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRG bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRG, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP7 field. */
+#define AIPS_RD_PACRG_TP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP7_MASK) >> AIPS_PACRG_TP7_SHIFT)
+#define AIPS_BRD_PACRG_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRG_TP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP7_MASK, AIPS_PACRG_TP7(value)))
+#define AIPS_BWR_PACRG_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP7 field. */
+#define AIPS_RD_PACRG_WP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP7_MASK) >> AIPS_PACRG_WP7_SHIFT)
+#define AIPS_BRD_PACRG_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRG_WP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP7_MASK, AIPS_PACRG_WP7(value)))
+#define AIPS_BWR_PACRG_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP7 field. */
+#define AIPS_RD_PACRG_SP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP7_MASK) >> AIPS_PACRG_SP7_SHIFT)
+#define AIPS_BRD_PACRG_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRG_SP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP7_MASK, AIPS_PACRG_SP7(value)))
+#define AIPS_BWR_PACRG_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP6 field. */
+#define AIPS_RD_PACRG_TP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP6_MASK) >> AIPS_PACRG_TP6_SHIFT)
+#define AIPS_BRD_PACRG_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRG_TP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP6_MASK, AIPS_PACRG_TP6(value)))
+#define AIPS_BWR_PACRG_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP6 field. */
+#define AIPS_RD_PACRG_WP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP6_MASK) >> AIPS_PACRG_WP6_SHIFT)
+#define AIPS_BRD_PACRG_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRG_WP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP6_MASK, AIPS_PACRG_WP6(value)))
+#define AIPS_BWR_PACRG_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP6 field. */
+#define AIPS_RD_PACRG_SP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP6_MASK) >> AIPS_PACRG_SP6_SHIFT)
+#define AIPS_BRD_PACRG_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRG_SP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP6_MASK, AIPS_PACRG_SP6(value)))
+#define AIPS_BWR_PACRG_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP5 field. */
+#define AIPS_RD_PACRG_TP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP5_MASK) >> AIPS_PACRG_TP5_SHIFT)
+#define AIPS_BRD_PACRG_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRG_TP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP5_MASK, AIPS_PACRG_TP5(value)))
+#define AIPS_BWR_PACRG_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP5 field. */
+#define AIPS_RD_PACRG_WP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP5_MASK) >> AIPS_PACRG_WP5_SHIFT)
+#define AIPS_BRD_PACRG_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRG_WP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP5_MASK, AIPS_PACRG_WP5(value)))
+#define AIPS_BWR_PACRG_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP5 field. */
+#define AIPS_RD_PACRG_SP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP5_MASK) >> AIPS_PACRG_SP5_SHIFT)
+#define AIPS_BRD_PACRG_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRG_SP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP5_MASK, AIPS_PACRG_SP5(value)))
+#define AIPS_BWR_PACRG_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP4 field. */
+#define AIPS_RD_PACRG_TP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP4_MASK) >> AIPS_PACRG_TP4_SHIFT)
+#define AIPS_BRD_PACRG_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRG_TP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP4_MASK, AIPS_PACRG_TP4(value)))
+#define AIPS_BWR_PACRG_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP4 field. */
+#define AIPS_RD_PACRG_WP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP4_MASK) >> AIPS_PACRG_WP4_SHIFT)
+#define AIPS_BRD_PACRG_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRG_WP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP4_MASK, AIPS_PACRG_WP4(value)))
+#define AIPS_BWR_PACRG_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP4 field. */
+#define AIPS_RD_PACRG_SP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP4_MASK) >> AIPS_PACRG_SP4_SHIFT)
+#define AIPS_BRD_PACRG_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRG_SP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP4_MASK, AIPS_PACRG_SP4(value)))
+#define AIPS_BWR_PACRG_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP3 field. */
+#define AIPS_RD_PACRG_TP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP3_MASK) >> AIPS_PACRG_TP3_SHIFT)
+#define AIPS_BRD_PACRG_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRG_TP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP3_MASK, AIPS_PACRG_TP3(value)))
+#define AIPS_BWR_PACRG_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP3 field. */
+#define AIPS_RD_PACRG_WP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP3_MASK) >> AIPS_PACRG_WP3_SHIFT)
+#define AIPS_BRD_PACRG_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRG_WP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP3_MASK, AIPS_PACRG_WP3(value)))
+#define AIPS_BWR_PACRG_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP3 field. */
+#define AIPS_RD_PACRG_SP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP3_MASK) >> AIPS_PACRG_SP3_SHIFT)
+#define AIPS_BRD_PACRG_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRG_SP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP3_MASK, AIPS_PACRG_SP3(value)))
+#define AIPS_BWR_PACRG_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP2 field. */
+#define AIPS_RD_PACRG_TP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP2_MASK) >> AIPS_PACRG_TP2_SHIFT)
+#define AIPS_BRD_PACRG_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRG_TP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP2_MASK, AIPS_PACRG_TP2(value)))
+#define AIPS_BWR_PACRG_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP2 field. */
+#define AIPS_RD_PACRG_WP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP2_MASK) >> AIPS_PACRG_WP2_SHIFT)
+#define AIPS_BRD_PACRG_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRG_WP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP2_MASK, AIPS_PACRG_WP2(value)))
+#define AIPS_BWR_PACRG_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP2 field. */
+#define AIPS_RD_PACRG_SP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP2_MASK) >> AIPS_PACRG_SP2_SHIFT)
+#define AIPS_BRD_PACRG_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRG_SP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP2_MASK, AIPS_PACRG_SP2(value)))
+#define AIPS_BWR_PACRG_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP1 field. */
+#define AIPS_RD_PACRG_TP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP1_MASK) >> AIPS_PACRG_TP1_SHIFT)
+#define AIPS_BRD_PACRG_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRG_TP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP1_MASK, AIPS_PACRG_TP1(value)))
+#define AIPS_BWR_PACRG_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP1 field. */
+#define AIPS_RD_PACRG_WP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP1_MASK) >> AIPS_PACRG_WP1_SHIFT)
+#define AIPS_BRD_PACRG_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRG_WP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP1_MASK, AIPS_PACRG_WP1(value)))
+#define AIPS_BWR_PACRG_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP1 field. */
+#define AIPS_RD_PACRG_SP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP1_MASK) >> AIPS_PACRG_SP1_SHIFT)
+#define AIPS_BRD_PACRG_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRG_SP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP1_MASK, AIPS_PACRG_SP1(value)))
+#define AIPS_BWR_PACRG_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP0 field. */
+#define AIPS_RD_PACRG_TP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP0_MASK) >> AIPS_PACRG_TP0_SHIFT)
+#define AIPS_BRD_PACRG_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRG_TP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP0_MASK, AIPS_PACRG_TP0(value)))
+#define AIPS_BWR_PACRG_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP0 field. */
+#define AIPS_RD_PACRG_WP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP0_MASK) >> AIPS_PACRG_WP0_SHIFT)
+#define AIPS_BRD_PACRG_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRG_WP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP0_MASK, AIPS_PACRG_WP0(value)))
+#define AIPS_BWR_PACRG_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP0 field. */
+#define AIPS_RD_PACRG_SP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP0_MASK) >> AIPS_PACRG_SP0_SHIFT)
+#define AIPS_BRD_PACRG_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRG_SP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP0_MASK, AIPS_PACRG_SP0(value)))
+#define AIPS_BWR_PACRG_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRH - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRH - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRH register
+ */
+/*@{*/
+#define AIPS_RD_PACRH(base)      (AIPS_PACRH_REG(base))
+#define AIPS_WR_PACRH(base, value) (AIPS_PACRH_REG(base) = (value))
+#define AIPS_RMW_PACRH(base, mask, value) (AIPS_WR_PACRH(base, (AIPS_RD_PACRH(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) |  (value)))
+#define AIPS_CLR_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) & ~(value)))
+#define AIPS_TOG_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRH bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRH, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP7 field. */
+#define AIPS_RD_PACRH_TP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP7_MASK) >> AIPS_PACRH_TP7_SHIFT)
+#define AIPS_BRD_PACRH_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRH_TP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP7_MASK, AIPS_PACRH_TP7(value)))
+#define AIPS_BWR_PACRH_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP7 field. */
+#define AIPS_RD_PACRH_WP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP7_MASK) >> AIPS_PACRH_WP7_SHIFT)
+#define AIPS_BRD_PACRH_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRH_WP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP7_MASK, AIPS_PACRH_WP7(value)))
+#define AIPS_BWR_PACRH_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP7 field. */
+#define AIPS_RD_PACRH_SP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP7_MASK) >> AIPS_PACRH_SP7_SHIFT)
+#define AIPS_BRD_PACRH_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRH_SP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP7_MASK, AIPS_PACRH_SP7(value)))
+#define AIPS_BWR_PACRH_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP6 field. */
+#define AIPS_RD_PACRH_TP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP6_MASK) >> AIPS_PACRH_TP6_SHIFT)
+#define AIPS_BRD_PACRH_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRH_TP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP6_MASK, AIPS_PACRH_TP6(value)))
+#define AIPS_BWR_PACRH_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP6 field. */
+#define AIPS_RD_PACRH_WP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP6_MASK) >> AIPS_PACRH_WP6_SHIFT)
+#define AIPS_BRD_PACRH_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRH_WP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP6_MASK, AIPS_PACRH_WP6(value)))
+#define AIPS_BWR_PACRH_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP6 field. */
+#define AIPS_RD_PACRH_SP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP6_MASK) >> AIPS_PACRH_SP6_SHIFT)
+#define AIPS_BRD_PACRH_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRH_SP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP6_MASK, AIPS_PACRH_SP6(value)))
+#define AIPS_BWR_PACRH_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP5 field. */
+#define AIPS_RD_PACRH_TP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP5_MASK) >> AIPS_PACRH_TP5_SHIFT)
+#define AIPS_BRD_PACRH_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRH_TP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP5_MASK, AIPS_PACRH_TP5(value)))
+#define AIPS_BWR_PACRH_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP5 field. */
+#define AIPS_RD_PACRH_WP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP5_MASK) >> AIPS_PACRH_WP5_SHIFT)
+#define AIPS_BRD_PACRH_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRH_WP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP5_MASK, AIPS_PACRH_WP5(value)))
+#define AIPS_BWR_PACRH_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP5 field. */
+#define AIPS_RD_PACRH_SP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP5_MASK) >> AIPS_PACRH_SP5_SHIFT)
+#define AIPS_BRD_PACRH_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRH_SP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP5_MASK, AIPS_PACRH_SP5(value)))
+#define AIPS_BWR_PACRH_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP4 field. */
+#define AIPS_RD_PACRH_TP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP4_MASK) >> AIPS_PACRH_TP4_SHIFT)
+#define AIPS_BRD_PACRH_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRH_TP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP4_MASK, AIPS_PACRH_TP4(value)))
+#define AIPS_BWR_PACRH_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP4 field. */
+#define AIPS_RD_PACRH_WP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP4_MASK) >> AIPS_PACRH_WP4_SHIFT)
+#define AIPS_BRD_PACRH_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRH_WP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP4_MASK, AIPS_PACRH_WP4(value)))
+#define AIPS_BWR_PACRH_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP4 field. */
+#define AIPS_RD_PACRH_SP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP4_MASK) >> AIPS_PACRH_SP4_SHIFT)
+#define AIPS_BRD_PACRH_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRH_SP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP4_MASK, AIPS_PACRH_SP4(value)))
+#define AIPS_BWR_PACRH_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP3 field. */
+#define AIPS_RD_PACRH_TP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP3_MASK) >> AIPS_PACRH_TP3_SHIFT)
+#define AIPS_BRD_PACRH_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRH_TP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP3_MASK, AIPS_PACRH_TP3(value)))
+#define AIPS_BWR_PACRH_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP3 field. */
+#define AIPS_RD_PACRH_WP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP3_MASK) >> AIPS_PACRH_WP3_SHIFT)
+#define AIPS_BRD_PACRH_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRH_WP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP3_MASK, AIPS_PACRH_WP3(value)))
+#define AIPS_BWR_PACRH_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP3 field. */
+#define AIPS_RD_PACRH_SP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP3_MASK) >> AIPS_PACRH_SP3_SHIFT)
+#define AIPS_BRD_PACRH_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRH_SP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP3_MASK, AIPS_PACRH_SP3(value)))
+#define AIPS_BWR_PACRH_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP2 field. */
+#define AIPS_RD_PACRH_TP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP2_MASK) >> AIPS_PACRH_TP2_SHIFT)
+#define AIPS_BRD_PACRH_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRH_TP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP2_MASK, AIPS_PACRH_TP2(value)))
+#define AIPS_BWR_PACRH_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP2 field. */
+#define AIPS_RD_PACRH_WP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP2_MASK) >> AIPS_PACRH_WP2_SHIFT)
+#define AIPS_BRD_PACRH_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRH_WP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP2_MASK, AIPS_PACRH_WP2(value)))
+#define AIPS_BWR_PACRH_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP2 field. */
+#define AIPS_RD_PACRH_SP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP2_MASK) >> AIPS_PACRH_SP2_SHIFT)
+#define AIPS_BRD_PACRH_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRH_SP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP2_MASK, AIPS_PACRH_SP2(value)))
+#define AIPS_BWR_PACRH_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP1 field. */
+#define AIPS_RD_PACRH_TP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP1_MASK) >> AIPS_PACRH_TP1_SHIFT)
+#define AIPS_BRD_PACRH_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRH_TP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP1_MASK, AIPS_PACRH_TP1(value)))
+#define AIPS_BWR_PACRH_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP1 field. */
+#define AIPS_RD_PACRH_WP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP1_MASK) >> AIPS_PACRH_WP1_SHIFT)
+#define AIPS_BRD_PACRH_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRH_WP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP1_MASK, AIPS_PACRH_WP1(value)))
+#define AIPS_BWR_PACRH_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP1 field. */
+#define AIPS_RD_PACRH_SP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP1_MASK) >> AIPS_PACRH_SP1_SHIFT)
+#define AIPS_BRD_PACRH_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRH_SP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP1_MASK, AIPS_PACRH_SP1(value)))
+#define AIPS_BWR_PACRH_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP0 field. */
+#define AIPS_RD_PACRH_TP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP0_MASK) >> AIPS_PACRH_TP0_SHIFT)
+#define AIPS_BRD_PACRH_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRH_TP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP0_MASK, AIPS_PACRH_TP0(value)))
+#define AIPS_BWR_PACRH_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP0 field. */
+#define AIPS_RD_PACRH_WP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP0_MASK) >> AIPS_PACRH_WP0_SHIFT)
+#define AIPS_BRD_PACRH_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRH_WP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP0_MASK, AIPS_PACRH_WP0(value)))
+#define AIPS_BWR_PACRH_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP0 field. */
+#define AIPS_RD_PACRH_SP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP0_MASK) >> AIPS_PACRH_SP0_SHIFT)
+#define AIPS_BRD_PACRH_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRH_SP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP0_MASK, AIPS_PACRH_SP0(value)))
+#define AIPS_BWR_PACRH_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRI - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRI - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRI register
+ */
+/*@{*/
+#define AIPS_RD_PACRI(base)      (AIPS_PACRI_REG(base))
+#define AIPS_WR_PACRI(base, value) (AIPS_PACRI_REG(base) = (value))
+#define AIPS_RMW_PACRI(base, mask, value) (AIPS_WR_PACRI(base, (AIPS_RD_PACRI(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) |  (value)))
+#define AIPS_CLR_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) & ~(value)))
+#define AIPS_TOG_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRI bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRI, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP7 field. */
+#define AIPS_RD_PACRI_TP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP7_MASK) >> AIPS_PACRI_TP7_SHIFT)
+#define AIPS_BRD_PACRI_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRI_TP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP7_MASK, AIPS_PACRI_TP7(value)))
+#define AIPS_BWR_PACRI_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP7 field. */
+#define AIPS_RD_PACRI_WP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP7_MASK) >> AIPS_PACRI_WP7_SHIFT)
+#define AIPS_BRD_PACRI_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRI_WP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP7_MASK, AIPS_PACRI_WP7(value)))
+#define AIPS_BWR_PACRI_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP7 field. */
+#define AIPS_RD_PACRI_SP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP7_MASK) >> AIPS_PACRI_SP7_SHIFT)
+#define AIPS_BRD_PACRI_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRI_SP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP7_MASK, AIPS_PACRI_SP7(value)))
+#define AIPS_BWR_PACRI_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP6 field. */
+#define AIPS_RD_PACRI_TP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP6_MASK) >> AIPS_PACRI_TP6_SHIFT)
+#define AIPS_BRD_PACRI_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRI_TP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP6_MASK, AIPS_PACRI_TP6(value)))
+#define AIPS_BWR_PACRI_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP6 field. */
+#define AIPS_RD_PACRI_WP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP6_MASK) >> AIPS_PACRI_WP6_SHIFT)
+#define AIPS_BRD_PACRI_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRI_WP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP6_MASK, AIPS_PACRI_WP6(value)))
+#define AIPS_BWR_PACRI_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP6 field. */
+#define AIPS_RD_PACRI_SP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP6_MASK) >> AIPS_PACRI_SP6_SHIFT)
+#define AIPS_BRD_PACRI_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRI_SP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP6_MASK, AIPS_PACRI_SP6(value)))
+#define AIPS_BWR_PACRI_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP5 field. */
+#define AIPS_RD_PACRI_TP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP5_MASK) >> AIPS_PACRI_TP5_SHIFT)
+#define AIPS_BRD_PACRI_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRI_TP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP5_MASK, AIPS_PACRI_TP5(value)))
+#define AIPS_BWR_PACRI_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP5 field. */
+#define AIPS_RD_PACRI_WP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP5_MASK) >> AIPS_PACRI_WP5_SHIFT)
+#define AIPS_BRD_PACRI_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRI_WP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP5_MASK, AIPS_PACRI_WP5(value)))
+#define AIPS_BWR_PACRI_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP5 field. */
+#define AIPS_RD_PACRI_SP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP5_MASK) >> AIPS_PACRI_SP5_SHIFT)
+#define AIPS_BRD_PACRI_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRI_SP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP5_MASK, AIPS_PACRI_SP5(value)))
+#define AIPS_BWR_PACRI_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP4 field. */
+#define AIPS_RD_PACRI_TP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP4_MASK) >> AIPS_PACRI_TP4_SHIFT)
+#define AIPS_BRD_PACRI_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRI_TP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP4_MASK, AIPS_PACRI_TP4(value)))
+#define AIPS_BWR_PACRI_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP4 field. */
+#define AIPS_RD_PACRI_WP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP4_MASK) >> AIPS_PACRI_WP4_SHIFT)
+#define AIPS_BRD_PACRI_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRI_WP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP4_MASK, AIPS_PACRI_WP4(value)))
+#define AIPS_BWR_PACRI_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP4 field. */
+#define AIPS_RD_PACRI_SP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP4_MASK) >> AIPS_PACRI_SP4_SHIFT)
+#define AIPS_BRD_PACRI_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRI_SP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP4_MASK, AIPS_PACRI_SP4(value)))
+#define AIPS_BWR_PACRI_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP3 field. */
+#define AIPS_RD_PACRI_TP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP3_MASK) >> AIPS_PACRI_TP3_SHIFT)
+#define AIPS_BRD_PACRI_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRI_TP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP3_MASK, AIPS_PACRI_TP3(value)))
+#define AIPS_BWR_PACRI_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP3 field. */
+#define AIPS_RD_PACRI_WP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP3_MASK) >> AIPS_PACRI_WP3_SHIFT)
+#define AIPS_BRD_PACRI_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRI_WP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP3_MASK, AIPS_PACRI_WP3(value)))
+#define AIPS_BWR_PACRI_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP3 field. */
+#define AIPS_RD_PACRI_SP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP3_MASK) >> AIPS_PACRI_SP3_SHIFT)
+#define AIPS_BRD_PACRI_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRI_SP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP3_MASK, AIPS_PACRI_SP3(value)))
+#define AIPS_BWR_PACRI_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP2 field. */
+#define AIPS_RD_PACRI_TP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP2_MASK) >> AIPS_PACRI_TP2_SHIFT)
+#define AIPS_BRD_PACRI_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRI_TP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP2_MASK, AIPS_PACRI_TP2(value)))
+#define AIPS_BWR_PACRI_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP2 field. */
+#define AIPS_RD_PACRI_WP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP2_MASK) >> AIPS_PACRI_WP2_SHIFT)
+#define AIPS_BRD_PACRI_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRI_WP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP2_MASK, AIPS_PACRI_WP2(value)))
+#define AIPS_BWR_PACRI_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP2 field. */
+#define AIPS_RD_PACRI_SP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP2_MASK) >> AIPS_PACRI_SP2_SHIFT)
+#define AIPS_BRD_PACRI_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRI_SP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP2_MASK, AIPS_PACRI_SP2(value)))
+#define AIPS_BWR_PACRI_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP1 field. */
+#define AIPS_RD_PACRI_TP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP1_MASK) >> AIPS_PACRI_TP1_SHIFT)
+#define AIPS_BRD_PACRI_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRI_TP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP1_MASK, AIPS_PACRI_TP1(value)))
+#define AIPS_BWR_PACRI_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP1 field. */
+#define AIPS_RD_PACRI_WP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP1_MASK) >> AIPS_PACRI_WP1_SHIFT)
+#define AIPS_BRD_PACRI_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRI_WP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP1_MASK, AIPS_PACRI_WP1(value)))
+#define AIPS_BWR_PACRI_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP1 field. */
+#define AIPS_RD_PACRI_SP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP1_MASK) >> AIPS_PACRI_SP1_SHIFT)
+#define AIPS_BRD_PACRI_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRI_SP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP1_MASK, AIPS_PACRI_SP1(value)))
+#define AIPS_BWR_PACRI_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP0 field. */
+#define AIPS_RD_PACRI_TP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP0_MASK) >> AIPS_PACRI_TP0_SHIFT)
+#define AIPS_BRD_PACRI_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRI_TP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP0_MASK, AIPS_PACRI_TP0(value)))
+#define AIPS_BWR_PACRI_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP0 field. */
+#define AIPS_RD_PACRI_WP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP0_MASK) >> AIPS_PACRI_WP0_SHIFT)
+#define AIPS_BRD_PACRI_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRI_WP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP0_MASK, AIPS_PACRI_WP0(value)))
+#define AIPS_BWR_PACRI_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP0 field. */
+#define AIPS_RD_PACRI_SP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP0_MASK) >> AIPS_PACRI_SP0_SHIFT)
+#define AIPS_BRD_PACRI_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRI_SP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP0_MASK, AIPS_PACRI_SP0(value)))
+#define AIPS_BWR_PACRI_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRJ - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRJ - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRJ register
+ */
+/*@{*/
+#define AIPS_RD_PACRJ(base)      (AIPS_PACRJ_REG(base))
+#define AIPS_WR_PACRJ(base, value) (AIPS_PACRJ_REG(base) = (value))
+#define AIPS_RMW_PACRJ(base, mask, value) (AIPS_WR_PACRJ(base, (AIPS_RD_PACRJ(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) |  (value)))
+#define AIPS_CLR_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) & ~(value)))
+#define AIPS_TOG_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRJ bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRJ, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP7 field. */
+#define AIPS_RD_PACRJ_TP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP7_MASK) >> AIPS_PACRJ_TP7_SHIFT)
+#define AIPS_BRD_PACRJ_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRJ_TP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP7_MASK, AIPS_PACRJ_TP7(value)))
+#define AIPS_BWR_PACRJ_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP7 field. */
+#define AIPS_RD_PACRJ_WP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP7_MASK) >> AIPS_PACRJ_WP7_SHIFT)
+#define AIPS_BRD_PACRJ_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRJ_WP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP7_MASK, AIPS_PACRJ_WP7(value)))
+#define AIPS_BWR_PACRJ_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP7 field. */
+#define AIPS_RD_PACRJ_SP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP7_MASK) >> AIPS_PACRJ_SP7_SHIFT)
+#define AIPS_BRD_PACRJ_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRJ_SP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP7_MASK, AIPS_PACRJ_SP7(value)))
+#define AIPS_BWR_PACRJ_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP6 field. */
+#define AIPS_RD_PACRJ_TP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP6_MASK) >> AIPS_PACRJ_TP6_SHIFT)
+#define AIPS_BRD_PACRJ_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRJ_TP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP6_MASK, AIPS_PACRJ_TP6(value)))
+#define AIPS_BWR_PACRJ_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP6 field. */
+#define AIPS_RD_PACRJ_WP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP6_MASK) >> AIPS_PACRJ_WP6_SHIFT)
+#define AIPS_BRD_PACRJ_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRJ_WP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP6_MASK, AIPS_PACRJ_WP6(value)))
+#define AIPS_BWR_PACRJ_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP6 field. */
+#define AIPS_RD_PACRJ_SP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP6_MASK) >> AIPS_PACRJ_SP6_SHIFT)
+#define AIPS_BRD_PACRJ_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRJ_SP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP6_MASK, AIPS_PACRJ_SP6(value)))
+#define AIPS_BWR_PACRJ_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP5 field. */
+#define AIPS_RD_PACRJ_TP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP5_MASK) >> AIPS_PACRJ_TP5_SHIFT)
+#define AIPS_BRD_PACRJ_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRJ_TP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP5_MASK, AIPS_PACRJ_TP5(value)))
+#define AIPS_BWR_PACRJ_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP5 field. */
+#define AIPS_RD_PACRJ_WP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP5_MASK) >> AIPS_PACRJ_WP5_SHIFT)
+#define AIPS_BRD_PACRJ_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRJ_WP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP5_MASK, AIPS_PACRJ_WP5(value)))
+#define AIPS_BWR_PACRJ_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP5 field. */
+#define AIPS_RD_PACRJ_SP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP5_MASK) >> AIPS_PACRJ_SP5_SHIFT)
+#define AIPS_BRD_PACRJ_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRJ_SP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP5_MASK, AIPS_PACRJ_SP5(value)))
+#define AIPS_BWR_PACRJ_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP4 field. */
+#define AIPS_RD_PACRJ_TP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP4_MASK) >> AIPS_PACRJ_TP4_SHIFT)
+#define AIPS_BRD_PACRJ_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRJ_TP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP4_MASK, AIPS_PACRJ_TP4(value)))
+#define AIPS_BWR_PACRJ_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP4 field. */
+#define AIPS_RD_PACRJ_WP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP4_MASK) >> AIPS_PACRJ_WP4_SHIFT)
+#define AIPS_BRD_PACRJ_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRJ_WP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP4_MASK, AIPS_PACRJ_WP4(value)))
+#define AIPS_BWR_PACRJ_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP4 field. */
+#define AIPS_RD_PACRJ_SP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP4_MASK) >> AIPS_PACRJ_SP4_SHIFT)
+#define AIPS_BRD_PACRJ_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRJ_SP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP4_MASK, AIPS_PACRJ_SP4(value)))
+#define AIPS_BWR_PACRJ_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP3 field. */
+#define AIPS_RD_PACRJ_TP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP3_MASK) >> AIPS_PACRJ_TP3_SHIFT)
+#define AIPS_BRD_PACRJ_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRJ_TP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP3_MASK, AIPS_PACRJ_TP3(value)))
+#define AIPS_BWR_PACRJ_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP3 field. */
+#define AIPS_RD_PACRJ_WP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP3_MASK) >> AIPS_PACRJ_WP3_SHIFT)
+#define AIPS_BRD_PACRJ_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRJ_WP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP3_MASK, AIPS_PACRJ_WP3(value)))
+#define AIPS_BWR_PACRJ_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP3 field. */
+#define AIPS_RD_PACRJ_SP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP3_MASK) >> AIPS_PACRJ_SP3_SHIFT)
+#define AIPS_BRD_PACRJ_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRJ_SP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP3_MASK, AIPS_PACRJ_SP3(value)))
+#define AIPS_BWR_PACRJ_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP2 field. */
+#define AIPS_RD_PACRJ_TP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP2_MASK) >> AIPS_PACRJ_TP2_SHIFT)
+#define AIPS_BRD_PACRJ_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRJ_TP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP2_MASK, AIPS_PACRJ_TP2(value)))
+#define AIPS_BWR_PACRJ_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP2 field. */
+#define AIPS_RD_PACRJ_WP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP2_MASK) >> AIPS_PACRJ_WP2_SHIFT)
+#define AIPS_BRD_PACRJ_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRJ_WP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP2_MASK, AIPS_PACRJ_WP2(value)))
+#define AIPS_BWR_PACRJ_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP2 field. */
+#define AIPS_RD_PACRJ_SP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP2_MASK) >> AIPS_PACRJ_SP2_SHIFT)
+#define AIPS_BRD_PACRJ_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRJ_SP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP2_MASK, AIPS_PACRJ_SP2(value)))
+#define AIPS_BWR_PACRJ_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP1 field. */
+#define AIPS_RD_PACRJ_TP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP1_MASK) >> AIPS_PACRJ_TP1_SHIFT)
+#define AIPS_BRD_PACRJ_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRJ_TP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP1_MASK, AIPS_PACRJ_TP1(value)))
+#define AIPS_BWR_PACRJ_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP1 field. */
+#define AIPS_RD_PACRJ_WP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP1_MASK) >> AIPS_PACRJ_WP1_SHIFT)
+#define AIPS_BRD_PACRJ_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRJ_WP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP1_MASK, AIPS_PACRJ_WP1(value)))
+#define AIPS_BWR_PACRJ_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP1 field. */
+#define AIPS_RD_PACRJ_SP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP1_MASK) >> AIPS_PACRJ_SP1_SHIFT)
+#define AIPS_BRD_PACRJ_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRJ_SP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP1_MASK, AIPS_PACRJ_SP1(value)))
+#define AIPS_BWR_PACRJ_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP0 field. */
+#define AIPS_RD_PACRJ_TP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP0_MASK) >> AIPS_PACRJ_TP0_SHIFT)
+#define AIPS_BRD_PACRJ_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRJ_TP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP0_MASK, AIPS_PACRJ_TP0(value)))
+#define AIPS_BWR_PACRJ_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP0 field. */
+#define AIPS_RD_PACRJ_WP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP0_MASK) >> AIPS_PACRJ_WP0_SHIFT)
+#define AIPS_BRD_PACRJ_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRJ_WP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP0_MASK, AIPS_PACRJ_WP0(value)))
+#define AIPS_BWR_PACRJ_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP0 field. */
+#define AIPS_RD_PACRJ_SP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP0_MASK) >> AIPS_PACRJ_SP0_SHIFT)
+#define AIPS_BRD_PACRJ_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRJ_SP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP0_MASK, AIPS_PACRJ_SP0(value)))
+#define AIPS_BWR_PACRJ_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRK - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRK - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRK register
+ */
+/*@{*/
+#define AIPS_RD_PACRK(base)      (AIPS_PACRK_REG(base))
+#define AIPS_WR_PACRK(base, value) (AIPS_PACRK_REG(base) = (value))
+#define AIPS_RMW_PACRK(base, mask, value) (AIPS_WR_PACRK(base, (AIPS_RD_PACRK(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) |  (value)))
+#define AIPS_CLR_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) & ~(value)))
+#define AIPS_TOG_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRK bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRK, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP7 field. */
+#define AIPS_RD_PACRK_TP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP7_MASK) >> AIPS_PACRK_TP7_SHIFT)
+#define AIPS_BRD_PACRK_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRK_TP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP7_MASK, AIPS_PACRK_TP7(value)))
+#define AIPS_BWR_PACRK_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP7 field. */
+#define AIPS_RD_PACRK_WP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP7_MASK) >> AIPS_PACRK_WP7_SHIFT)
+#define AIPS_BRD_PACRK_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRK_WP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP7_MASK, AIPS_PACRK_WP7(value)))
+#define AIPS_BWR_PACRK_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP7 field. */
+#define AIPS_RD_PACRK_SP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP7_MASK) >> AIPS_PACRK_SP7_SHIFT)
+#define AIPS_BRD_PACRK_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRK_SP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP7_MASK, AIPS_PACRK_SP7(value)))
+#define AIPS_BWR_PACRK_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP6 field. */
+#define AIPS_RD_PACRK_TP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP6_MASK) >> AIPS_PACRK_TP6_SHIFT)
+#define AIPS_BRD_PACRK_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRK_TP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP6_MASK, AIPS_PACRK_TP6(value)))
+#define AIPS_BWR_PACRK_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP6 field. */
+#define AIPS_RD_PACRK_WP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP6_MASK) >> AIPS_PACRK_WP6_SHIFT)
+#define AIPS_BRD_PACRK_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRK_WP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP6_MASK, AIPS_PACRK_WP6(value)))
+#define AIPS_BWR_PACRK_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP6 field. */
+#define AIPS_RD_PACRK_SP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP6_MASK) >> AIPS_PACRK_SP6_SHIFT)
+#define AIPS_BRD_PACRK_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRK_SP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP6_MASK, AIPS_PACRK_SP6(value)))
+#define AIPS_BWR_PACRK_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP5 field. */
+#define AIPS_RD_PACRK_TP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP5_MASK) >> AIPS_PACRK_TP5_SHIFT)
+#define AIPS_BRD_PACRK_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRK_TP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP5_MASK, AIPS_PACRK_TP5(value)))
+#define AIPS_BWR_PACRK_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP5 field. */
+#define AIPS_RD_PACRK_WP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP5_MASK) >> AIPS_PACRK_WP5_SHIFT)
+#define AIPS_BRD_PACRK_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRK_WP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP5_MASK, AIPS_PACRK_WP5(value)))
+#define AIPS_BWR_PACRK_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP5 field. */
+#define AIPS_RD_PACRK_SP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP5_MASK) >> AIPS_PACRK_SP5_SHIFT)
+#define AIPS_BRD_PACRK_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRK_SP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP5_MASK, AIPS_PACRK_SP5(value)))
+#define AIPS_BWR_PACRK_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP4 field. */
+#define AIPS_RD_PACRK_TP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP4_MASK) >> AIPS_PACRK_TP4_SHIFT)
+#define AIPS_BRD_PACRK_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRK_TP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP4_MASK, AIPS_PACRK_TP4(value)))
+#define AIPS_BWR_PACRK_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP4 field. */
+#define AIPS_RD_PACRK_WP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP4_MASK) >> AIPS_PACRK_WP4_SHIFT)
+#define AIPS_BRD_PACRK_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRK_WP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP4_MASK, AIPS_PACRK_WP4(value)))
+#define AIPS_BWR_PACRK_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP4 field. */
+#define AIPS_RD_PACRK_SP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP4_MASK) >> AIPS_PACRK_SP4_SHIFT)
+#define AIPS_BRD_PACRK_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRK_SP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP4_MASK, AIPS_PACRK_SP4(value)))
+#define AIPS_BWR_PACRK_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP3 field. */
+#define AIPS_RD_PACRK_TP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP3_MASK) >> AIPS_PACRK_TP3_SHIFT)
+#define AIPS_BRD_PACRK_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRK_TP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP3_MASK, AIPS_PACRK_TP3(value)))
+#define AIPS_BWR_PACRK_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP3 field. */
+#define AIPS_RD_PACRK_WP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP3_MASK) >> AIPS_PACRK_WP3_SHIFT)
+#define AIPS_BRD_PACRK_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRK_WP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP3_MASK, AIPS_PACRK_WP3(value)))
+#define AIPS_BWR_PACRK_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP3 field. */
+#define AIPS_RD_PACRK_SP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP3_MASK) >> AIPS_PACRK_SP3_SHIFT)
+#define AIPS_BRD_PACRK_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRK_SP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP3_MASK, AIPS_PACRK_SP3(value)))
+#define AIPS_BWR_PACRK_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP2 field. */
+#define AIPS_RD_PACRK_TP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP2_MASK) >> AIPS_PACRK_TP2_SHIFT)
+#define AIPS_BRD_PACRK_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRK_TP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP2_MASK, AIPS_PACRK_TP2(value)))
+#define AIPS_BWR_PACRK_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP2 field. */
+#define AIPS_RD_PACRK_WP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP2_MASK) >> AIPS_PACRK_WP2_SHIFT)
+#define AIPS_BRD_PACRK_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRK_WP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP2_MASK, AIPS_PACRK_WP2(value)))
+#define AIPS_BWR_PACRK_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP2 field. */
+#define AIPS_RD_PACRK_SP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP2_MASK) >> AIPS_PACRK_SP2_SHIFT)
+#define AIPS_BRD_PACRK_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRK_SP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP2_MASK, AIPS_PACRK_SP2(value)))
+#define AIPS_BWR_PACRK_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP1 field. */
+#define AIPS_RD_PACRK_TP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP1_MASK) >> AIPS_PACRK_TP1_SHIFT)
+#define AIPS_BRD_PACRK_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRK_TP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP1_MASK, AIPS_PACRK_TP1(value)))
+#define AIPS_BWR_PACRK_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP1 field. */
+#define AIPS_RD_PACRK_WP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP1_MASK) >> AIPS_PACRK_WP1_SHIFT)
+#define AIPS_BRD_PACRK_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRK_WP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP1_MASK, AIPS_PACRK_WP1(value)))
+#define AIPS_BWR_PACRK_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP1 field. */
+#define AIPS_RD_PACRK_SP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP1_MASK) >> AIPS_PACRK_SP1_SHIFT)
+#define AIPS_BRD_PACRK_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRK_SP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP1_MASK, AIPS_PACRK_SP1(value)))
+#define AIPS_BWR_PACRK_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP0 field. */
+#define AIPS_RD_PACRK_TP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP0_MASK) >> AIPS_PACRK_TP0_SHIFT)
+#define AIPS_BRD_PACRK_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRK_TP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP0_MASK, AIPS_PACRK_TP0(value)))
+#define AIPS_BWR_PACRK_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP0 field. */
+#define AIPS_RD_PACRK_WP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP0_MASK) >> AIPS_PACRK_WP0_SHIFT)
+#define AIPS_BRD_PACRK_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRK_WP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP0_MASK, AIPS_PACRK_WP0(value)))
+#define AIPS_BWR_PACRK_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP0 field. */
+#define AIPS_RD_PACRK_SP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP0_MASK) >> AIPS_PACRK_SP0_SHIFT)
+#define AIPS_BRD_PACRK_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRK_SP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP0_MASK, AIPS_PACRK_SP0(value)))
+#define AIPS_BWR_PACRK_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRL - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRL - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRL register
+ */
+/*@{*/
+#define AIPS_RD_PACRL(base)      (AIPS_PACRL_REG(base))
+#define AIPS_WR_PACRL(base, value) (AIPS_PACRL_REG(base) = (value))
+#define AIPS_RMW_PACRL(base, mask, value) (AIPS_WR_PACRL(base, (AIPS_RD_PACRL(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) |  (value)))
+#define AIPS_CLR_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) & ~(value)))
+#define AIPS_TOG_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRL bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRL, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP7 field. */
+#define AIPS_RD_PACRL_TP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP7_MASK) >> AIPS_PACRL_TP7_SHIFT)
+#define AIPS_BRD_PACRL_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRL_TP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP7_MASK, AIPS_PACRL_TP7(value)))
+#define AIPS_BWR_PACRL_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP7 field. */
+#define AIPS_RD_PACRL_WP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP7_MASK) >> AIPS_PACRL_WP7_SHIFT)
+#define AIPS_BRD_PACRL_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRL_WP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP7_MASK, AIPS_PACRL_WP7(value)))
+#define AIPS_BWR_PACRL_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP7 field. */
+#define AIPS_RD_PACRL_SP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP7_MASK) >> AIPS_PACRL_SP7_SHIFT)
+#define AIPS_BRD_PACRL_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRL_SP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP7_MASK, AIPS_PACRL_SP7(value)))
+#define AIPS_BWR_PACRL_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP6 field. */
+#define AIPS_RD_PACRL_TP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP6_MASK) >> AIPS_PACRL_TP6_SHIFT)
+#define AIPS_BRD_PACRL_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRL_TP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP6_MASK, AIPS_PACRL_TP6(value)))
+#define AIPS_BWR_PACRL_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP6 field. */
+#define AIPS_RD_PACRL_WP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP6_MASK) >> AIPS_PACRL_WP6_SHIFT)
+#define AIPS_BRD_PACRL_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRL_WP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP6_MASK, AIPS_PACRL_WP6(value)))
+#define AIPS_BWR_PACRL_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP6 field. */
+#define AIPS_RD_PACRL_SP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP6_MASK) >> AIPS_PACRL_SP6_SHIFT)
+#define AIPS_BRD_PACRL_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRL_SP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP6_MASK, AIPS_PACRL_SP6(value)))
+#define AIPS_BWR_PACRL_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP5 field. */
+#define AIPS_RD_PACRL_TP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP5_MASK) >> AIPS_PACRL_TP5_SHIFT)
+#define AIPS_BRD_PACRL_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRL_TP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP5_MASK, AIPS_PACRL_TP5(value)))
+#define AIPS_BWR_PACRL_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP5 field. */
+#define AIPS_RD_PACRL_WP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP5_MASK) >> AIPS_PACRL_WP5_SHIFT)
+#define AIPS_BRD_PACRL_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRL_WP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP5_MASK, AIPS_PACRL_WP5(value)))
+#define AIPS_BWR_PACRL_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP5 field. */
+#define AIPS_RD_PACRL_SP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP5_MASK) >> AIPS_PACRL_SP5_SHIFT)
+#define AIPS_BRD_PACRL_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRL_SP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP5_MASK, AIPS_PACRL_SP5(value)))
+#define AIPS_BWR_PACRL_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP4 field. */
+#define AIPS_RD_PACRL_TP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP4_MASK) >> AIPS_PACRL_TP4_SHIFT)
+#define AIPS_BRD_PACRL_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRL_TP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP4_MASK, AIPS_PACRL_TP4(value)))
+#define AIPS_BWR_PACRL_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP4 field. */
+#define AIPS_RD_PACRL_WP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP4_MASK) >> AIPS_PACRL_WP4_SHIFT)
+#define AIPS_BRD_PACRL_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRL_WP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP4_MASK, AIPS_PACRL_WP4(value)))
+#define AIPS_BWR_PACRL_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP4 field. */
+#define AIPS_RD_PACRL_SP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP4_MASK) >> AIPS_PACRL_SP4_SHIFT)
+#define AIPS_BRD_PACRL_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRL_SP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP4_MASK, AIPS_PACRL_SP4(value)))
+#define AIPS_BWR_PACRL_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP3 field. */
+#define AIPS_RD_PACRL_TP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP3_MASK) >> AIPS_PACRL_TP3_SHIFT)
+#define AIPS_BRD_PACRL_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRL_TP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP3_MASK, AIPS_PACRL_TP3(value)))
+#define AIPS_BWR_PACRL_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP3 field. */
+#define AIPS_RD_PACRL_WP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP3_MASK) >> AIPS_PACRL_WP3_SHIFT)
+#define AIPS_BRD_PACRL_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRL_WP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP3_MASK, AIPS_PACRL_WP3(value)))
+#define AIPS_BWR_PACRL_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP3 field. */
+#define AIPS_RD_PACRL_SP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP3_MASK) >> AIPS_PACRL_SP3_SHIFT)
+#define AIPS_BRD_PACRL_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRL_SP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP3_MASK, AIPS_PACRL_SP3(value)))
+#define AIPS_BWR_PACRL_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP2 field. */
+#define AIPS_RD_PACRL_TP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP2_MASK) >> AIPS_PACRL_TP2_SHIFT)
+#define AIPS_BRD_PACRL_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRL_TP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP2_MASK, AIPS_PACRL_TP2(value)))
+#define AIPS_BWR_PACRL_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP2 field. */
+#define AIPS_RD_PACRL_WP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP2_MASK) >> AIPS_PACRL_WP2_SHIFT)
+#define AIPS_BRD_PACRL_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRL_WP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP2_MASK, AIPS_PACRL_WP2(value)))
+#define AIPS_BWR_PACRL_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP2 field. */
+#define AIPS_RD_PACRL_SP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP2_MASK) >> AIPS_PACRL_SP2_SHIFT)
+#define AIPS_BRD_PACRL_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRL_SP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP2_MASK, AIPS_PACRL_SP2(value)))
+#define AIPS_BWR_PACRL_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP1 field. */
+#define AIPS_RD_PACRL_TP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP1_MASK) >> AIPS_PACRL_TP1_SHIFT)
+#define AIPS_BRD_PACRL_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRL_TP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP1_MASK, AIPS_PACRL_TP1(value)))
+#define AIPS_BWR_PACRL_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP1 field. */
+#define AIPS_RD_PACRL_WP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP1_MASK) >> AIPS_PACRL_WP1_SHIFT)
+#define AIPS_BRD_PACRL_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRL_WP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP1_MASK, AIPS_PACRL_WP1(value)))
+#define AIPS_BWR_PACRL_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP1 field. */
+#define AIPS_RD_PACRL_SP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP1_MASK) >> AIPS_PACRL_SP1_SHIFT)
+#define AIPS_BRD_PACRL_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRL_SP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP1_MASK, AIPS_PACRL_SP1(value)))
+#define AIPS_BWR_PACRL_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP0 field. */
+#define AIPS_RD_PACRL_TP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP0_MASK) >> AIPS_PACRL_TP0_SHIFT)
+#define AIPS_BRD_PACRL_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRL_TP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP0_MASK, AIPS_PACRL_TP0(value)))
+#define AIPS_BWR_PACRL_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP0 field. */
+#define AIPS_RD_PACRL_WP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP0_MASK) >> AIPS_PACRL_WP0_SHIFT)
+#define AIPS_BRD_PACRL_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRL_WP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP0_MASK, AIPS_PACRL_WP0(value)))
+#define AIPS_BWR_PACRL_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP0 field. */
+#define AIPS_RD_PACRL_SP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP0_MASK) >> AIPS_PACRL_SP0_SHIFT)
+#define AIPS_BRD_PACRL_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRL_SP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP0_MASK, AIPS_PACRL_SP0(value)))
+#define AIPS_BWR_PACRL_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRM - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRM - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRM register
+ */
+/*@{*/
+#define AIPS_RD_PACRM(base)      (AIPS_PACRM_REG(base))
+#define AIPS_WR_PACRM(base, value) (AIPS_PACRM_REG(base) = (value))
+#define AIPS_RMW_PACRM(base, mask, value) (AIPS_WR_PACRM(base, (AIPS_RD_PACRM(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) |  (value)))
+#define AIPS_CLR_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) & ~(value)))
+#define AIPS_TOG_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRM bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRM, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP7 field. */
+#define AIPS_RD_PACRM_TP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP7_MASK) >> AIPS_PACRM_TP7_SHIFT)
+#define AIPS_BRD_PACRM_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRM_TP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP7_MASK, AIPS_PACRM_TP7(value)))
+#define AIPS_BWR_PACRM_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP7 field. */
+#define AIPS_RD_PACRM_WP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP7_MASK) >> AIPS_PACRM_WP7_SHIFT)
+#define AIPS_BRD_PACRM_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRM_WP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP7_MASK, AIPS_PACRM_WP7(value)))
+#define AIPS_BWR_PACRM_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP7 field. */
+#define AIPS_RD_PACRM_SP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP7_MASK) >> AIPS_PACRM_SP7_SHIFT)
+#define AIPS_BRD_PACRM_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRM_SP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP7_MASK, AIPS_PACRM_SP7(value)))
+#define AIPS_BWR_PACRM_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP6 field. */
+#define AIPS_RD_PACRM_TP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP6_MASK) >> AIPS_PACRM_TP6_SHIFT)
+#define AIPS_BRD_PACRM_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRM_TP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP6_MASK, AIPS_PACRM_TP6(value)))
+#define AIPS_BWR_PACRM_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP6 field. */
+#define AIPS_RD_PACRM_WP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP6_MASK) >> AIPS_PACRM_WP6_SHIFT)
+#define AIPS_BRD_PACRM_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRM_WP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP6_MASK, AIPS_PACRM_WP6(value)))
+#define AIPS_BWR_PACRM_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP6 field. */
+#define AIPS_RD_PACRM_SP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP6_MASK) >> AIPS_PACRM_SP6_SHIFT)
+#define AIPS_BRD_PACRM_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRM_SP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP6_MASK, AIPS_PACRM_SP6(value)))
+#define AIPS_BWR_PACRM_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP5 field. */
+#define AIPS_RD_PACRM_TP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP5_MASK) >> AIPS_PACRM_TP5_SHIFT)
+#define AIPS_BRD_PACRM_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRM_TP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP5_MASK, AIPS_PACRM_TP5(value)))
+#define AIPS_BWR_PACRM_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP5 field. */
+#define AIPS_RD_PACRM_WP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP5_MASK) >> AIPS_PACRM_WP5_SHIFT)
+#define AIPS_BRD_PACRM_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRM_WP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP5_MASK, AIPS_PACRM_WP5(value)))
+#define AIPS_BWR_PACRM_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP5 field. */
+#define AIPS_RD_PACRM_SP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP5_MASK) >> AIPS_PACRM_SP5_SHIFT)
+#define AIPS_BRD_PACRM_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRM_SP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP5_MASK, AIPS_PACRM_SP5(value)))
+#define AIPS_BWR_PACRM_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP4 field. */
+#define AIPS_RD_PACRM_TP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP4_MASK) >> AIPS_PACRM_TP4_SHIFT)
+#define AIPS_BRD_PACRM_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRM_TP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP4_MASK, AIPS_PACRM_TP4(value)))
+#define AIPS_BWR_PACRM_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP4 field. */
+#define AIPS_RD_PACRM_WP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP4_MASK) >> AIPS_PACRM_WP4_SHIFT)
+#define AIPS_BRD_PACRM_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRM_WP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP4_MASK, AIPS_PACRM_WP4(value)))
+#define AIPS_BWR_PACRM_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP4 field. */
+#define AIPS_RD_PACRM_SP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP4_MASK) >> AIPS_PACRM_SP4_SHIFT)
+#define AIPS_BRD_PACRM_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRM_SP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP4_MASK, AIPS_PACRM_SP4(value)))
+#define AIPS_BWR_PACRM_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP3 field. */
+#define AIPS_RD_PACRM_TP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP3_MASK) >> AIPS_PACRM_TP3_SHIFT)
+#define AIPS_BRD_PACRM_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRM_TP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP3_MASK, AIPS_PACRM_TP3(value)))
+#define AIPS_BWR_PACRM_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP3 field. */
+#define AIPS_RD_PACRM_WP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP3_MASK) >> AIPS_PACRM_WP3_SHIFT)
+#define AIPS_BRD_PACRM_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRM_WP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP3_MASK, AIPS_PACRM_WP3(value)))
+#define AIPS_BWR_PACRM_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP3 field. */
+#define AIPS_RD_PACRM_SP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP3_MASK) >> AIPS_PACRM_SP3_SHIFT)
+#define AIPS_BRD_PACRM_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRM_SP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP3_MASK, AIPS_PACRM_SP3(value)))
+#define AIPS_BWR_PACRM_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP2 field. */
+#define AIPS_RD_PACRM_TP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP2_MASK) >> AIPS_PACRM_TP2_SHIFT)
+#define AIPS_BRD_PACRM_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRM_TP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP2_MASK, AIPS_PACRM_TP2(value)))
+#define AIPS_BWR_PACRM_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP2 field. */
+#define AIPS_RD_PACRM_WP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP2_MASK) >> AIPS_PACRM_WP2_SHIFT)
+#define AIPS_BRD_PACRM_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRM_WP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP2_MASK, AIPS_PACRM_WP2(value)))
+#define AIPS_BWR_PACRM_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP2 field. */
+#define AIPS_RD_PACRM_SP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP2_MASK) >> AIPS_PACRM_SP2_SHIFT)
+#define AIPS_BRD_PACRM_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRM_SP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP2_MASK, AIPS_PACRM_SP2(value)))
+#define AIPS_BWR_PACRM_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP1 field. */
+#define AIPS_RD_PACRM_TP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP1_MASK) >> AIPS_PACRM_TP1_SHIFT)
+#define AIPS_BRD_PACRM_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRM_TP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP1_MASK, AIPS_PACRM_TP1(value)))
+#define AIPS_BWR_PACRM_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP1 field. */
+#define AIPS_RD_PACRM_WP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP1_MASK) >> AIPS_PACRM_WP1_SHIFT)
+#define AIPS_BRD_PACRM_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRM_WP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP1_MASK, AIPS_PACRM_WP1(value)))
+#define AIPS_BWR_PACRM_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP1 field. */
+#define AIPS_RD_PACRM_SP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP1_MASK) >> AIPS_PACRM_SP1_SHIFT)
+#define AIPS_BRD_PACRM_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRM_SP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP1_MASK, AIPS_PACRM_SP1(value)))
+#define AIPS_BWR_PACRM_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP0 field. */
+#define AIPS_RD_PACRM_TP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP0_MASK) >> AIPS_PACRM_TP0_SHIFT)
+#define AIPS_BRD_PACRM_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRM_TP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP0_MASK, AIPS_PACRM_TP0(value)))
+#define AIPS_BWR_PACRM_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP0 field. */
+#define AIPS_RD_PACRM_WP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP0_MASK) >> AIPS_PACRM_WP0_SHIFT)
+#define AIPS_BRD_PACRM_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRM_WP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP0_MASK, AIPS_PACRM_WP0(value)))
+#define AIPS_BWR_PACRM_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP0 field. */
+#define AIPS_RD_PACRM_SP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP0_MASK) >> AIPS_PACRM_SP0_SHIFT)
+#define AIPS_BRD_PACRM_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRM_SP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP0_MASK, AIPS_PACRM_SP0(value)))
+#define AIPS_BWR_PACRM_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRN - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRN - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRN register
+ */
+/*@{*/
+#define AIPS_RD_PACRN(base)      (AIPS_PACRN_REG(base))
+#define AIPS_WR_PACRN(base, value) (AIPS_PACRN_REG(base) = (value))
+#define AIPS_RMW_PACRN(base, mask, value) (AIPS_WR_PACRN(base, (AIPS_RD_PACRN(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) |  (value)))
+#define AIPS_CLR_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) & ~(value)))
+#define AIPS_TOG_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRN bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRN, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP7 field. */
+#define AIPS_RD_PACRN_TP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP7_MASK) >> AIPS_PACRN_TP7_SHIFT)
+#define AIPS_BRD_PACRN_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRN_TP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP7_MASK, AIPS_PACRN_TP7(value)))
+#define AIPS_BWR_PACRN_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP7 field. */
+#define AIPS_RD_PACRN_WP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP7_MASK) >> AIPS_PACRN_WP7_SHIFT)
+#define AIPS_BRD_PACRN_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRN_WP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP7_MASK, AIPS_PACRN_WP7(value)))
+#define AIPS_BWR_PACRN_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP7 field. */
+#define AIPS_RD_PACRN_SP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP7_MASK) >> AIPS_PACRN_SP7_SHIFT)
+#define AIPS_BRD_PACRN_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRN_SP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP7_MASK, AIPS_PACRN_SP7(value)))
+#define AIPS_BWR_PACRN_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP6 field. */
+#define AIPS_RD_PACRN_TP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP6_MASK) >> AIPS_PACRN_TP6_SHIFT)
+#define AIPS_BRD_PACRN_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRN_TP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP6_MASK, AIPS_PACRN_TP6(value)))
+#define AIPS_BWR_PACRN_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP6 field. */
+#define AIPS_RD_PACRN_WP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP6_MASK) >> AIPS_PACRN_WP6_SHIFT)
+#define AIPS_BRD_PACRN_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRN_WP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP6_MASK, AIPS_PACRN_WP6(value)))
+#define AIPS_BWR_PACRN_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP6 field. */
+#define AIPS_RD_PACRN_SP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP6_MASK) >> AIPS_PACRN_SP6_SHIFT)
+#define AIPS_BRD_PACRN_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRN_SP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP6_MASK, AIPS_PACRN_SP6(value)))
+#define AIPS_BWR_PACRN_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP5 field. */
+#define AIPS_RD_PACRN_TP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP5_MASK) >> AIPS_PACRN_TP5_SHIFT)
+#define AIPS_BRD_PACRN_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRN_TP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP5_MASK, AIPS_PACRN_TP5(value)))
+#define AIPS_BWR_PACRN_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP5 field. */
+#define AIPS_RD_PACRN_WP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP5_MASK) >> AIPS_PACRN_WP5_SHIFT)
+#define AIPS_BRD_PACRN_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRN_WP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP5_MASK, AIPS_PACRN_WP5(value)))
+#define AIPS_BWR_PACRN_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP5 field. */
+#define AIPS_RD_PACRN_SP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP5_MASK) >> AIPS_PACRN_SP5_SHIFT)
+#define AIPS_BRD_PACRN_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRN_SP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP5_MASK, AIPS_PACRN_SP5(value)))
+#define AIPS_BWR_PACRN_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP4 field. */
+#define AIPS_RD_PACRN_TP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP4_MASK) >> AIPS_PACRN_TP4_SHIFT)
+#define AIPS_BRD_PACRN_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRN_TP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP4_MASK, AIPS_PACRN_TP4(value)))
+#define AIPS_BWR_PACRN_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP4 field. */
+#define AIPS_RD_PACRN_WP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP4_MASK) >> AIPS_PACRN_WP4_SHIFT)
+#define AIPS_BRD_PACRN_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRN_WP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP4_MASK, AIPS_PACRN_WP4(value)))
+#define AIPS_BWR_PACRN_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP4 field. */
+#define AIPS_RD_PACRN_SP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP4_MASK) >> AIPS_PACRN_SP4_SHIFT)
+#define AIPS_BRD_PACRN_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRN_SP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP4_MASK, AIPS_PACRN_SP4(value)))
+#define AIPS_BWR_PACRN_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP3 field. */
+#define AIPS_RD_PACRN_TP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP3_MASK) >> AIPS_PACRN_TP3_SHIFT)
+#define AIPS_BRD_PACRN_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRN_TP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP3_MASK, AIPS_PACRN_TP3(value)))
+#define AIPS_BWR_PACRN_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP3 field. */
+#define AIPS_RD_PACRN_WP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP3_MASK) >> AIPS_PACRN_WP3_SHIFT)
+#define AIPS_BRD_PACRN_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRN_WP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP3_MASK, AIPS_PACRN_WP3(value)))
+#define AIPS_BWR_PACRN_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP3 field. */
+#define AIPS_RD_PACRN_SP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP3_MASK) >> AIPS_PACRN_SP3_SHIFT)
+#define AIPS_BRD_PACRN_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRN_SP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP3_MASK, AIPS_PACRN_SP3(value)))
+#define AIPS_BWR_PACRN_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP2 field. */
+#define AIPS_RD_PACRN_TP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP2_MASK) >> AIPS_PACRN_TP2_SHIFT)
+#define AIPS_BRD_PACRN_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRN_TP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP2_MASK, AIPS_PACRN_TP2(value)))
+#define AIPS_BWR_PACRN_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP2 field. */
+#define AIPS_RD_PACRN_WP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP2_MASK) >> AIPS_PACRN_WP2_SHIFT)
+#define AIPS_BRD_PACRN_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRN_WP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP2_MASK, AIPS_PACRN_WP2(value)))
+#define AIPS_BWR_PACRN_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP2 field. */
+#define AIPS_RD_PACRN_SP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP2_MASK) >> AIPS_PACRN_SP2_SHIFT)
+#define AIPS_BRD_PACRN_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRN_SP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP2_MASK, AIPS_PACRN_SP2(value)))
+#define AIPS_BWR_PACRN_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP1 field. */
+#define AIPS_RD_PACRN_TP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP1_MASK) >> AIPS_PACRN_TP1_SHIFT)
+#define AIPS_BRD_PACRN_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRN_TP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP1_MASK, AIPS_PACRN_TP1(value)))
+#define AIPS_BWR_PACRN_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP1 field. */
+#define AIPS_RD_PACRN_WP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP1_MASK) >> AIPS_PACRN_WP1_SHIFT)
+#define AIPS_BRD_PACRN_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRN_WP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP1_MASK, AIPS_PACRN_WP1(value)))
+#define AIPS_BWR_PACRN_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP1 field. */
+#define AIPS_RD_PACRN_SP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP1_MASK) >> AIPS_PACRN_SP1_SHIFT)
+#define AIPS_BRD_PACRN_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRN_SP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP1_MASK, AIPS_PACRN_SP1(value)))
+#define AIPS_BWR_PACRN_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP0 field. */
+#define AIPS_RD_PACRN_TP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP0_MASK) >> AIPS_PACRN_TP0_SHIFT)
+#define AIPS_BRD_PACRN_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRN_TP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP0_MASK, AIPS_PACRN_TP0(value)))
+#define AIPS_BWR_PACRN_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP0 field. */
+#define AIPS_RD_PACRN_WP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP0_MASK) >> AIPS_PACRN_WP0_SHIFT)
+#define AIPS_BRD_PACRN_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRN_WP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP0_MASK, AIPS_PACRN_WP0(value)))
+#define AIPS_BWR_PACRN_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP0 field. */
+#define AIPS_RD_PACRN_SP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP0_MASK) >> AIPS_PACRN_SP0_SHIFT)
+#define AIPS_BRD_PACRN_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRN_SP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP0_MASK, AIPS_PACRN_SP0(value)))
+#define AIPS_BWR_PACRN_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRO - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRO - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRO register
+ */
+/*@{*/
+#define AIPS_RD_PACRO(base)      (AIPS_PACRO_REG(base))
+#define AIPS_WR_PACRO(base, value) (AIPS_PACRO_REG(base) = (value))
+#define AIPS_RMW_PACRO(base, mask, value) (AIPS_WR_PACRO(base, (AIPS_RD_PACRO(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) |  (value)))
+#define AIPS_CLR_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) & ~(value)))
+#define AIPS_TOG_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRO bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRO, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP7 field. */
+#define AIPS_RD_PACRO_TP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP7_MASK) >> AIPS_PACRO_TP7_SHIFT)
+#define AIPS_BRD_PACRO_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRO_TP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP7_MASK, AIPS_PACRO_TP7(value)))
+#define AIPS_BWR_PACRO_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP7 field. */
+#define AIPS_RD_PACRO_WP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP7_MASK) >> AIPS_PACRO_WP7_SHIFT)
+#define AIPS_BRD_PACRO_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRO_WP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP7_MASK, AIPS_PACRO_WP7(value)))
+#define AIPS_BWR_PACRO_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP7 field. */
+#define AIPS_RD_PACRO_SP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP7_MASK) >> AIPS_PACRO_SP7_SHIFT)
+#define AIPS_BRD_PACRO_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRO_SP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP7_MASK, AIPS_PACRO_SP7(value)))
+#define AIPS_BWR_PACRO_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP6 field. */
+#define AIPS_RD_PACRO_TP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP6_MASK) >> AIPS_PACRO_TP6_SHIFT)
+#define AIPS_BRD_PACRO_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRO_TP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP6_MASK, AIPS_PACRO_TP6(value)))
+#define AIPS_BWR_PACRO_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP6 field. */
+#define AIPS_RD_PACRO_WP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP6_MASK) >> AIPS_PACRO_WP6_SHIFT)
+#define AIPS_BRD_PACRO_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRO_WP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP6_MASK, AIPS_PACRO_WP6(value)))
+#define AIPS_BWR_PACRO_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP6 field. */
+#define AIPS_RD_PACRO_SP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP6_MASK) >> AIPS_PACRO_SP6_SHIFT)
+#define AIPS_BRD_PACRO_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRO_SP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP6_MASK, AIPS_PACRO_SP6(value)))
+#define AIPS_BWR_PACRO_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP5 field. */
+#define AIPS_RD_PACRO_TP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP5_MASK) >> AIPS_PACRO_TP5_SHIFT)
+#define AIPS_BRD_PACRO_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRO_TP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP5_MASK, AIPS_PACRO_TP5(value)))
+#define AIPS_BWR_PACRO_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP5 field. */
+#define AIPS_RD_PACRO_WP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP5_MASK) >> AIPS_PACRO_WP5_SHIFT)
+#define AIPS_BRD_PACRO_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRO_WP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP5_MASK, AIPS_PACRO_WP5(value)))
+#define AIPS_BWR_PACRO_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP5 field. */
+#define AIPS_RD_PACRO_SP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP5_MASK) >> AIPS_PACRO_SP5_SHIFT)
+#define AIPS_BRD_PACRO_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRO_SP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP5_MASK, AIPS_PACRO_SP5(value)))
+#define AIPS_BWR_PACRO_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP4 field. */
+#define AIPS_RD_PACRO_TP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP4_MASK) >> AIPS_PACRO_TP4_SHIFT)
+#define AIPS_BRD_PACRO_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRO_TP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP4_MASK, AIPS_PACRO_TP4(value)))
+#define AIPS_BWR_PACRO_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP4 field. */
+#define AIPS_RD_PACRO_WP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP4_MASK) >> AIPS_PACRO_WP4_SHIFT)
+#define AIPS_BRD_PACRO_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRO_WP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP4_MASK, AIPS_PACRO_WP4(value)))
+#define AIPS_BWR_PACRO_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP4 field. */
+#define AIPS_RD_PACRO_SP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP4_MASK) >> AIPS_PACRO_SP4_SHIFT)
+#define AIPS_BRD_PACRO_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRO_SP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP4_MASK, AIPS_PACRO_SP4(value)))
+#define AIPS_BWR_PACRO_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP3 field. */
+#define AIPS_RD_PACRO_TP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP3_MASK) >> AIPS_PACRO_TP3_SHIFT)
+#define AIPS_BRD_PACRO_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRO_TP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP3_MASK, AIPS_PACRO_TP3(value)))
+#define AIPS_BWR_PACRO_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP3 field. */
+#define AIPS_RD_PACRO_WP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP3_MASK) >> AIPS_PACRO_WP3_SHIFT)
+#define AIPS_BRD_PACRO_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRO_WP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP3_MASK, AIPS_PACRO_WP3(value)))
+#define AIPS_BWR_PACRO_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP3 field. */
+#define AIPS_RD_PACRO_SP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP3_MASK) >> AIPS_PACRO_SP3_SHIFT)
+#define AIPS_BRD_PACRO_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRO_SP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP3_MASK, AIPS_PACRO_SP3(value)))
+#define AIPS_BWR_PACRO_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP2 field. */
+#define AIPS_RD_PACRO_TP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP2_MASK) >> AIPS_PACRO_TP2_SHIFT)
+#define AIPS_BRD_PACRO_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRO_TP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP2_MASK, AIPS_PACRO_TP2(value)))
+#define AIPS_BWR_PACRO_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP2 field. */
+#define AIPS_RD_PACRO_WP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP2_MASK) >> AIPS_PACRO_WP2_SHIFT)
+#define AIPS_BRD_PACRO_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRO_WP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP2_MASK, AIPS_PACRO_WP2(value)))
+#define AIPS_BWR_PACRO_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP2 field. */
+#define AIPS_RD_PACRO_SP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP2_MASK) >> AIPS_PACRO_SP2_SHIFT)
+#define AIPS_BRD_PACRO_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRO_SP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP2_MASK, AIPS_PACRO_SP2(value)))
+#define AIPS_BWR_PACRO_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP1 field. */
+#define AIPS_RD_PACRO_TP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP1_MASK) >> AIPS_PACRO_TP1_SHIFT)
+#define AIPS_BRD_PACRO_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRO_TP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP1_MASK, AIPS_PACRO_TP1(value)))
+#define AIPS_BWR_PACRO_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP1 field. */
+#define AIPS_RD_PACRO_WP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP1_MASK) >> AIPS_PACRO_WP1_SHIFT)
+#define AIPS_BRD_PACRO_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRO_WP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP1_MASK, AIPS_PACRO_WP1(value)))
+#define AIPS_BWR_PACRO_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP1 field. */
+#define AIPS_RD_PACRO_SP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP1_MASK) >> AIPS_PACRO_SP1_SHIFT)
+#define AIPS_BRD_PACRO_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRO_SP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP1_MASK, AIPS_PACRO_SP1(value)))
+#define AIPS_BWR_PACRO_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP0 field. */
+#define AIPS_RD_PACRO_TP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP0_MASK) >> AIPS_PACRO_TP0_SHIFT)
+#define AIPS_BRD_PACRO_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRO_TP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP0_MASK, AIPS_PACRO_TP0(value)))
+#define AIPS_BWR_PACRO_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP0 field. */
+#define AIPS_RD_PACRO_WP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP0_MASK) >> AIPS_PACRO_WP0_SHIFT)
+#define AIPS_BRD_PACRO_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRO_WP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP0_MASK, AIPS_PACRO_WP0(value)))
+#define AIPS_BWR_PACRO_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP0 field. */
+#define AIPS_RD_PACRO_SP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP0_MASK) >> AIPS_PACRO_SP0_SHIFT)
+#define AIPS_BRD_PACRO_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRO_SP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP0_MASK, AIPS_PACRO_SP0(value)))
+#define AIPS_BWR_PACRO_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRP - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRP - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRP register
+ */
+/*@{*/
+#define AIPS_RD_PACRP(base)      (AIPS_PACRP_REG(base))
+#define AIPS_WR_PACRP(base, value) (AIPS_PACRP_REG(base) = (value))
+#define AIPS_RMW_PACRP(base, mask, value) (AIPS_WR_PACRP(base, (AIPS_RD_PACRP(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) |  (value)))
+#define AIPS_CLR_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) & ~(value)))
+#define AIPS_TOG_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRP bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRP, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP7 field. */
+#define AIPS_RD_PACRP_TP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP7_MASK) >> AIPS_PACRP_TP7_SHIFT)
+#define AIPS_BRD_PACRP_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRP_TP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP7_MASK, AIPS_PACRP_TP7(value)))
+#define AIPS_BWR_PACRP_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP7 field. */
+#define AIPS_RD_PACRP_WP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP7_MASK) >> AIPS_PACRP_WP7_SHIFT)
+#define AIPS_BRD_PACRP_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRP_WP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP7_MASK, AIPS_PACRP_WP7(value)))
+#define AIPS_BWR_PACRP_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP7 field. */
+#define AIPS_RD_PACRP_SP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP7_MASK) >> AIPS_PACRP_SP7_SHIFT)
+#define AIPS_BRD_PACRP_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRP_SP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP7_MASK, AIPS_PACRP_SP7(value)))
+#define AIPS_BWR_PACRP_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP6 field. */
+#define AIPS_RD_PACRP_TP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP6_MASK) >> AIPS_PACRP_TP6_SHIFT)
+#define AIPS_BRD_PACRP_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRP_TP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP6_MASK, AIPS_PACRP_TP6(value)))
+#define AIPS_BWR_PACRP_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP6 field. */
+#define AIPS_RD_PACRP_WP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP6_MASK) >> AIPS_PACRP_WP6_SHIFT)
+#define AIPS_BRD_PACRP_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRP_WP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP6_MASK, AIPS_PACRP_WP6(value)))
+#define AIPS_BWR_PACRP_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP6 field. */
+#define AIPS_RD_PACRP_SP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP6_MASK) >> AIPS_PACRP_SP6_SHIFT)
+#define AIPS_BRD_PACRP_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRP_SP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP6_MASK, AIPS_PACRP_SP6(value)))
+#define AIPS_BWR_PACRP_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP5 field. */
+#define AIPS_RD_PACRP_TP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP5_MASK) >> AIPS_PACRP_TP5_SHIFT)
+#define AIPS_BRD_PACRP_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRP_TP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP5_MASK, AIPS_PACRP_TP5(value)))
+#define AIPS_BWR_PACRP_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP5 field. */
+#define AIPS_RD_PACRP_WP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP5_MASK) >> AIPS_PACRP_WP5_SHIFT)
+#define AIPS_BRD_PACRP_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRP_WP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP5_MASK, AIPS_PACRP_WP5(value)))
+#define AIPS_BWR_PACRP_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP5 field. */
+#define AIPS_RD_PACRP_SP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP5_MASK) >> AIPS_PACRP_SP5_SHIFT)
+#define AIPS_BRD_PACRP_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRP_SP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP5_MASK, AIPS_PACRP_SP5(value)))
+#define AIPS_BWR_PACRP_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP4 field. */
+#define AIPS_RD_PACRP_TP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP4_MASK) >> AIPS_PACRP_TP4_SHIFT)
+#define AIPS_BRD_PACRP_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRP_TP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP4_MASK, AIPS_PACRP_TP4(value)))
+#define AIPS_BWR_PACRP_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP4 field. */
+#define AIPS_RD_PACRP_WP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP4_MASK) >> AIPS_PACRP_WP4_SHIFT)
+#define AIPS_BRD_PACRP_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRP_WP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP4_MASK, AIPS_PACRP_WP4(value)))
+#define AIPS_BWR_PACRP_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP4 field. */
+#define AIPS_RD_PACRP_SP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP4_MASK) >> AIPS_PACRP_SP4_SHIFT)
+#define AIPS_BRD_PACRP_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRP_SP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP4_MASK, AIPS_PACRP_SP4(value)))
+#define AIPS_BWR_PACRP_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP3 field. */
+#define AIPS_RD_PACRP_TP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP3_MASK) >> AIPS_PACRP_TP3_SHIFT)
+#define AIPS_BRD_PACRP_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRP_TP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP3_MASK, AIPS_PACRP_TP3(value)))
+#define AIPS_BWR_PACRP_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP3 field. */
+#define AIPS_RD_PACRP_WP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP3_MASK) >> AIPS_PACRP_WP3_SHIFT)
+#define AIPS_BRD_PACRP_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRP_WP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP3_MASK, AIPS_PACRP_WP3(value)))
+#define AIPS_BWR_PACRP_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP3 field. */
+#define AIPS_RD_PACRP_SP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP3_MASK) >> AIPS_PACRP_SP3_SHIFT)
+#define AIPS_BRD_PACRP_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRP_SP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP3_MASK, AIPS_PACRP_SP3(value)))
+#define AIPS_BWR_PACRP_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP2 field. */
+#define AIPS_RD_PACRP_TP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP2_MASK) >> AIPS_PACRP_TP2_SHIFT)
+#define AIPS_BRD_PACRP_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRP_TP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP2_MASK, AIPS_PACRP_TP2(value)))
+#define AIPS_BWR_PACRP_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP2 field. */
+#define AIPS_RD_PACRP_WP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP2_MASK) >> AIPS_PACRP_WP2_SHIFT)
+#define AIPS_BRD_PACRP_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRP_WP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP2_MASK, AIPS_PACRP_WP2(value)))
+#define AIPS_BWR_PACRP_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP2 field. */
+#define AIPS_RD_PACRP_SP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP2_MASK) >> AIPS_PACRP_SP2_SHIFT)
+#define AIPS_BRD_PACRP_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRP_SP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP2_MASK, AIPS_PACRP_SP2(value)))
+#define AIPS_BWR_PACRP_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP1 field. */
+#define AIPS_RD_PACRP_TP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP1_MASK) >> AIPS_PACRP_TP1_SHIFT)
+#define AIPS_BRD_PACRP_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRP_TP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP1_MASK, AIPS_PACRP_TP1(value)))
+#define AIPS_BWR_PACRP_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP1 field. */
+#define AIPS_RD_PACRP_WP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP1_MASK) >> AIPS_PACRP_WP1_SHIFT)
+#define AIPS_BRD_PACRP_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRP_WP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP1_MASK, AIPS_PACRP_WP1(value)))
+#define AIPS_BWR_PACRP_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP1 field. */
+#define AIPS_RD_PACRP_SP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP1_MASK) >> AIPS_PACRP_SP1_SHIFT)
+#define AIPS_BRD_PACRP_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRP_SP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP1_MASK, AIPS_PACRP_SP1(value)))
+#define AIPS_BWR_PACRP_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP0 field. */
+#define AIPS_RD_PACRP_TP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP0_MASK) >> AIPS_PACRP_TP0_SHIFT)
+#define AIPS_BRD_PACRP_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRP_TP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP0_MASK, AIPS_PACRP_TP0(value)))
+#define AIPS_BWR_PACRP_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP0 field. */
+#define AIPS_RD_PACRP_WP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP0_MASK) >> AIPS_PACRP_WP0_SHIFT)
+#define AIPS_BRD_PACRP_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRP_WP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP0_MASK, AIPS_PACRP_WP0(value)))
+#define AIPS_BWR_PACRP_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP0 field. */
+#define AIPS_RD_PACRP_SP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP0_MASK) >> AIPS_PACRP_SP0_SHIFT)
+#define AIPS_BRD_PACRP_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRP_SP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP0_MASK, AIPS_PACRP_SP0(value)))
+#define AIPS_BWR_PACRP_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRU - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRU - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44000000U
+ *
+ * PACRU defines the access levels for the two global spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRU register
+ */
+/*@{*/
+#define AIPS_RD_PACRU(base)      (AIPS_PACRU_REG(base))
+#define AIPS_WR_PACRU(base, value) (AIPS_PACRU_REG(base) = (value))
+#define AIPS_RMW_PACRU(base, mask, value) (AIPS_WR_PACRU(base, (AIPS_RD_PACRU(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) |  (value)))
+#define AIPS_CLR_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) & ~(value)))
+#define AIPS_TOG_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRU bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRU, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_TP1 field. */
+#define AIPS_RD_PACRU_TP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_TP1_MASK) >> AIPS_PACRU_TP1_SHIFT)
+#define AIPS_BRD_PACRU_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRU_TP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_TP1_MASK, AIPS_PACRU_TP1(value)))
+#define AIPS_BWR_PACRU_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_WP1 field. */
+#define AIPS_RD_PACRU_WP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_WP1_MASK) >> AIPS_PACRU_WP1_SHIFT)
+#define AIPS_BRD_PACRU_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRU_WP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_WP1_MASK, AIPS_PACRU_WP1(value)))
+#define AIPS_BWR_PACRU_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_SP1 field. */
+#define AIPS_RD_PACRU_SP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_SP1_MASK) >> AIPS_PACRU_SP1_SHIFT)
+#define AIPS_BRD_PACRU_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRU_SP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_SP1_MASK, AIPS_PACRU_SP1(value)))
+#define AIPS_BWR_PACRU_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_TP0 field. */
+#define AIPS_RD_PACRU_TP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_TP0_MASK) >> AIPS_PACRU_TP0_SHIFT)
+#define AIPS_BRD_PACRU_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRU_TP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_TP0_MASK, AIPS_PACRU_TP0(value)))
+#define AIPS_BWR_PACRU_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_WP0 field. */
+#define AIPS_RD_PACRU_WP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_WP0_MASK) >> AIPS_PACRU_WP0_SHIFT)
+#define AIPS_BRD_PACRU_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRU_WP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_WP0_MASK, AIPS_PACRU_WP0(value)))
+#define AIPS_BWR_PACRU_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_SP0 field. */
+#define AIPS_RD_PACRU_SP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_SP0_MASK) >> AIPS_PACRU_SP0_SHIFT)
+#define AIPS_BRD_PACRU_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRU_SP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_SP0_MASK, AIPS_PACRU_SP0(value)))
+#define AIPS_BWR_PACRU_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP0_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 AXBS
+ *
+ * Crossbar switch
+ *
+ * Registers defined in this header file:
+ * - AXBS_PRS - Priority Registers Slave
+ * - AXBS_CRS - Control Register
+ * - AXBS_MGPCR0 - Master General Purpose Control Register
+ * - AXBS_MGPCR1 - Master General Purpose Control Register
+ * - AXBS_MGPCR2 - Master General Purpose Control Register
+ * - AXBS_MGPCR3 - Master General Purpose Control Register
+ * - AXBS_MGPCR4 - Master General Purpose Control Register
+ * - AXBS_MGPCR5 - Master General Purpose Control Register
+ */
+
+#define AXBS_INSTANCE_COUNT (1U) /*!< Number of instances of the AXBS module. */
+#define AXBS_IDX (0U) /*!< Instance number for AXBS. */
+
+/*******************************************************************************
+ * AXBS_PRS - Priority Registers Slave
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_PRS - Priority Registers Slave (RW)
+ *
+ * Reset value: 0x00543210U
+ *
+ * The priority registers (PRSn) set the priority of each master port on a per
+ * slave port basis and reside in each slave port. The priority register can be
+ * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
+ * register can only be read; attempts to write to it have no effect on PRSn and
+ * result in a bus-error response to the master initiating the write. Two available
+ * masters must not be programmed with the same priority level. Attempts to
+ * program two or more masters with the same priority level result in a bus-error
+ * response and the PRSn is not updated. Valid values for the Mn priority fields
+ * depend on which masters are available on the chip. This information can be found in
+ * the chip-specific information for the crossbar. If the chip contains less
+ * than five masters, values 0 to 3 are valid. Writing other values will result in
+ * an error. If the chip contains five or more masters, valid values are 0 to n-1,
+ * where n is the number of masters attached to the AXBS module. Other values
+ * will result in an error.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_PRS register
+ */
+/*@{*/
+#define AXBS_RD_PRS(base, index) (AXBS_PRS_REG(base, index))
+#define AXBS_WR_PRS(base, index, value) (AXBS_PRS_REG(base, index) = (value))
+#define AXBS_RMW_PRS(base, index, mask, value) (AXBS_WR_PRS(base, index, (AXBS_RD_PRS(base, index) & ~(mask)) | (value)))
+#define AXBS_SET_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) |  (value)))
+#define AXBS_CLR_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) & ~(value)))
+#define AXBS_TOG_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_PRS bitfields
+ */
+
+/*!
+ * @name Register AXBS_PRS, field M0[2:0] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M0 field. */
+#define AXBS_RD_PRS_M0(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M0_MASK) >> AXBS_PRS_M0_SHIFT)
+#define AXBS_BRD_PRS_M0(base, index) (AXBS_RD_PRS_M0(base, index))
+
+/*! @brief Set the M0 field to a new value. */
+#define AXBS_WR_PRS_M0(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M0_MASK, AXBS_PRS_M0(value)))
+#define AXBS_BWR_PRS_M0(base, index, value) (AXBS_WR_PRS_M0(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M1[6:4] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M1 field. */
+#define AXBS_RD_PRS_M1(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M1_MASK) >> AXBS_PRS_M1_SHIFT)
+#define AXBS_BRD_PRS_M1(base, index) (AXBS_RD_PRS_M1(base, index))
+
+/*! @brief Set the M1 field to a new value. */
+#define AXBS_WR_PRS_M1(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M1_MASK, AXBS_PRS_M1(value)))
+#define AXBS_BWR_PRS_M1(base, index, value) (AXBS_WR_PRS_M1(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M2[10:8] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M2 field. */
+#define AXBS_RD_PRS_M2(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M2_MASK) >> AXBS_PRS_M2_SHIFT)
+#define AXBS_BRD_PRS_M2(base, index) (AXBS_RD_PRS_M2(base, index))
+
+/*! @brief Set the M2 field to a new value. */
+#define AXBS_WR_PRS_M2(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M2_MASK, AXBS_PRS_M2(value)))
+#define AXBS_BWR_PRS_M2(base, index, value) (AXBS_WR_PRS_M2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M3[14:12] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M3 field. */
+#define AXBS_RD_PRS_M3(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M3_MASK) >> AXBS_PRS_M3_SHIFT)
+#define AXBS_BRD_PRS_M3(base, index) (AXBS_RD_PRS_M3(base, index))
+
+/*! @brief Set the M3 field to a new value. */
+#define AXBS_WR_PRS_M3(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M3_MASK, AXBS_PRS_M3(value)))
+#define AXBS_BWR_PRS_M3(base, index, value) (AXBS_WR_PRS_M3(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M4[18:16] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M4 field. */
+#define AXBS_RD_PRS_M4(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M4_MASK) >> AXBS_PRS_M4_SHIFT)
+#define AXBS_BRD_PRS_M4(base, index) (AXBS_RD_PRS_M4(base, index))
+
+/*! @brief Set the M4 field to a new value. */
+#define AXBS_WR_PRS_M4(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M4_MASK, AXBS_PRS_M4(value)))
+#define AXBS_BWR_PRS_M4(base, index, value) (AXBS_WR_PRS_M4(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M5[22:20] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M5 field. */
+#define AXBS_RD_PRS_M5(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M5_MASK) >> AXBS_PRS_M5_SHIFT)
+#define AXBS_BRD_PRS_M5(base, index) (AXBS_RD_PRS_M5(base, index))
+
+/*! @brief Set the M5 field to a new value. */
+#define AXBS_WR_PRS_M5(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M5_MASK, AXBS_PRS_M5(value)))
+#define AXBS_BWR_PRS_M5(base, index, value) (AXBS_WR_PRS_M5(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_CRS - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_CRS - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers control several features of each slave port and must be
+ * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
+ * attempts to write to it have no effect and result in an error response.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_CRS register
+ */
+/*@{*/
+#define AXBS_RD_CRS(base, index) (AXBS_CRS_REG(base, index))
+#define AXBS_WR_CRS(base, index, value) (AXBS_CRS_REG(base, index) = (value))
+#define AXBS_RMW_CRS(base, index, mask, value) (AXBS_WR_CRS(base, index, (AXBS_RD_CRS(base, index) & ~(mask)) | (value)))
+#define AXBS_SET_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) |  (value)))
+#define AXBS_CLR_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) & ~(value)))
+#define AXBS_TOG_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_CRS bitfields
+ */
+
+/*!
+ * @name Register AXBS_CRS, field PARK[2:0] (RW)
+ *
+ * Determines which master port the current slave port parks on when no masters
+ * are actively making requests and the PCTL bits are cleared. Select only master
+ * ports that are present on the chip. Otherwise, undefined behavior might occur.
+ *
+ * Values:
+ * - 0b000 - Park on master port M0
+ * - 0b001 - Park on master port M1
+ * - 0b010 - Park on master port M2
+ * - 0b011 - Park on master port M3
+ * - 0b100 - Park on master port M4
+ * - 0b101 - Park on master port M5
+ * - 0b110 - Park on master port M6
+ * - 0b111 - Park on master port M7
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_PARK field. */
+#define AXBS_RD_CRS_PARK(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_PARK_MASK) >> AXBS_CRS_PARK_SHIFT)
+#define AXBS_BRD_CRS_PARK(base, index) (AXBS_RD_CRS_PARK(base, index))
+
+/*! @brief Set the PARK field to a new value. */
+#define AXBS_WR_CRS_PARK(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_PARK_MASK, AXBS_CRS_PARK(value)))
+#define AXBS_BWR_CRS_PARK(base, index, value) (AXBS_WR_CRS_PARK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field PCTL[5:4] (RW)
+ *
+ * Determines the slave port's parking control. The low-power park feature
+ * results in an overall power savings if the slave port is not saturated. However,
+ * this forces an extra latency clock when any master tries to access the slave
+ * port while not in use because it is not parked on any master.
+ *
+ * Values:
+ * - 0b00 - When no master makes a request, the arbiter parks the slave port on
+ *     the master port defined by the PARK field
+ * - 0b01 - When no master makes a request, the arbiter parks the slave port on
+ *     the last master to be in control of the slave port
+ * - 0b10 - When no master makes a request, the slave port is not parked on a
+ *     master and the arbiter drives all outputs to a constant safe state
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_PCTL field. */
+#define AXBS_RD_CRS_PCTL(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_PCTL_MASK) >> AXBS_CRS_PCTL_SHIFT)
+#define AXBS_BRD_CRS_PCTL(base, index) (AXBS_RD_CRS_PCTL(base, index))
+
+/*! @brief Set the PCTL field to a new value. */
+#define AXBS_WR_CRS_PCTL(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_PCTL_MASK, AXBS_CRS_PCTL(value)))
+#define AXBS_BWR_CRS_PCTL(base, index, value) (AXBS_WR_CRS_PCTL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field ARB[9:8] (RW)
+ *
+ * Selects the arbitration policy for the slave port.
+ *
+ * Values:
+ * - 0b00 - Fixed priority
+ * - 0b01 - Round-robin, or rotating, priority
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_ARB field. */
+#define AXBS_RD_CRS_ARB(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_ARB_MASK) >> AXBS_CRS_ARB_SHIFT)
+#define AXBS_BRD_CRS_ARB(base, index) (AXBS_RD_CRS_ARB(base, index))
+
+/*! @brief Set the ARB field to a new value. */
+#define AXBS_WR_CRS_ARB(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_ARB_MASK, AXBS_CRS_ARB(value)))
+#define AXBS_BWR_CRS_ARB(base, index, value) (AXBS_WR_CRS_ARB(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field HLP[30] (RW)
+ *
+ * Sets the initial arbitration priority for low power mode requests . Setting
+ * this bit will not affect the request for low power mode from attaining highest
+ * priority once it has control of the slave ports.
+ *
+ * Values:
+ * - 0b0 - The low power mode request has the highest priority for arbitration
+ *     on this slave port
+ * - 0b1 - The low power mode request has the lowest initial priority for
+ *     arbitration on this slave port
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_HLP field. */
+#define AXBS_RD_CRS_HLP(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_HLP_MASK) >> AXBS_CRS_HLP_SHIFT)
+#define AXBS_BRD_CRS_HLP(base, index) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_HLP_SHIFT))
+
+/*! @brief Set the HLP field to a new value. */
+#define AXBS_WR_CRS_HLP(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_HLP_MASK, AXBS_CRS_HLP(value)))
+#define AXBS_BWR_CRS_HLP(base, index, value) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_HLP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field RO[31] (RW)
+ *
+ * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
+ * only a hardware reset clears it.
+ *
+ * Values:
+ * - 0b0 - The slave port's registers are writeable
+ * - 0b1 - The slave port's registers are read-only and cannot be written.
+ *     Attempted writes have no effect on the registers and result in a bus error
+ *     response.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_RO field. */
+#define AXBS_RD_CRS_RO(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_RO_MASK) >> AXBS_CRS_RO_SHIFT)
+#define AXBS_BRD_CRS_RO(base, index) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_RO_SHIFT))
+
+/*! @brief Set the RO field to a new value. */
+#define AXBS_WR_CRS_RO(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_RO_MASK, AXBS_CRS_RO(value)))
+#define AXBS_BWR_CRS_RO(base, index, value) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_RO_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR0 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR0 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR0 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR0(base)     (AXBS_MGPCR0_REG(base))
+#define AXBS_WR_MGPCR0(base, value) (AXBS_MGPCR0_REG(base) = (value))
+#define AXBS_RMW_MGPCR0(base, mask, value) (AXBS_WR_MGPCR0(base, (AXBS_RD_MGPCR0(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) |  (value)))
+#define AXBS_CLR_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) & ~(value)))
+#define AXBS_TOG_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR0 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR0_AULB field. */
+#define AXBS_RD_MGPCR0_AULB(base) ((AXBS_MGPCR0_REG(base) & AXBS_MGPCR0_AULB_MASK) >> AXBS_MGPCR0_AULB_SHIFT)
+#define AXBS_BRD_MGPCR0_AULB(base) (AXBS_RD_MGPCR0_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR0_AULB(base, value) (AXBS_RMW_MGPCR0(base, AXBS_MGPCR0_AULB_MASK, AXBS_MGPCR0_AULB(value)))
+#define AXBS_BWR_MGPCR0_AULB(base, value) (AXBS_WR_MGPCR0_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR1 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR1 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR1 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR1(base)     (AXBS_MGPCR1_REG(base))
+#define AXBS_WR_MGPCR1(base, value) (AXBS_MGPCR1_REG(base) = (value))
+#define AXBS_RMW_MGPCR1(base, mask, value) (AXBS_WR_MGPCR1(base, (AXBS_RD_MGPCR1(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) |  (value)))
+#define AXBS_CLR_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) & ~(value)))
+#define AXBS_TOG_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR1 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR1_AULB field. */
+#define AXBS_RD_MGPCR1_AULB(base) ((AXBS_MGPCR1_REG(base) & AXBS_MGPCR1_AULB_MASK) >> AXBS_MGPCR1_AULB_SHIFT)
+#define AXBS_BRD_MGPCR1_AULB(base) (AXBS_RD_MGPCR1_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR1_AULB(base, value) (AXBS_RMW_MGPCR1(base, AXBS_MGPCR1_AULB_MASK, AXBS_MGPCR1_AULB(value)))
+#define AXBS_BWR_MGPCR1_AULB(base, value) (AXBS_WR_MGPCR1_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR2 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR2 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR2 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR2(base)     (AXBS_MGPCR2_REG(base))
+#define AXBS_WR_MGPCR2(base, value) (AXBS_MGPCR2_REG(base) = (value))
+#define AXBS_RMW_MGPCR2(base, mask, value) (AXBS_WR_MGPCR2(base, (AXBS_RD_MGPCR2(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) |  (value)))
+#define AXBS_CLR_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) & ~(value)))
+#define AXBS_TOG_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR2 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR2_AULB field. */
+#define AXBS_RD_MGPCR2_AULB(base) ((AXBS_MGPCR2_REG(base) & AXBS_MGPCR2_AULB_MASK) >> AXBS_MGPCR2_AULB_SHIFT)
+#define AXBS_BRD_MGPCR2_AULB(base) (AXBS_RD_MGPCR2_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR2_AULB(base, value) (AXBS_RMW_MGPCR2(base, AXBS_MGPCR2_AULB_MASK, AXBS_MGPCR2_AULB(value)))
+#define AXBS_BWR_MGPCR2_AULB(base, value) (AXBS_WR_MGPCR2_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR3 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR3 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR3 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR3(base)     (AXBS_MGPCR3_REG(base))
+#define AXBS_WR_MGPCR3(base, value) (AXBS_MGPCR3_REG(base) = (value))
+#define AXBS_RMW_MGPCR3(base, mask, value) (AXBS_WR_MGPCR3(base, (AXBS_RD_MGPCR3(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) |  (value)))
+#define AXBS_CLR_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) & ~(value)))
+#define AXBS_TOG_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR3 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR3_AULB field. */
+#define AXBS_RD_MGPCR3_AULB(base) ((AXBS_MGPCR3_REG(base) & AXBS_MGPCR3_AULB_MASK) >> AXBS_MGPCR3_AULB_SHIFT)
+#define AXBS_BRD_MGPCR3_AULB(base) (AXBS_RD_MGPCR3_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR3_AULB(base, value) (AXBS_RMW_MGPCR3(base, AXBS_MGPCR3_AULB_MASK, AXBS_MGPCR3_AULB(value)))
+#define AXBS_BWR_MGPCR3_AULB(base, value) (AXBS_WR_MGPCR3_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR4 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR4 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR4 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR4(base)     (AXBS_MGPCR4_REG(base))
+#define AXBS_WR_MGPCR4(base, value) (AXBS_MGPCR4_REG(base) = (value))
+#define AXBS_RMW_MGPCR4(base, mask, value) (AXBS_WR_MGPCR4(base, (AXBS_RD_MGPCR4(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) |  (value)))
+#define AXBS_CLR_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) & ~(value)))
+#define AXBS_TOG_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR4 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR4_AULB field. */
+#define AXBS_RD_MGPCR4_AULB(base) ((AXBS_MGPCR4_REG(base) & AXBS_MGPCR4_AULB_MASK) >> AXBS_MGPCR4_AULB_SHIFT)
+#define AXBS_BRD_MGPCR4_AULB(base) (AXBS_RD_MGPCR4_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR4_AULB(base, value) (AXBS_RMW_MGPCR4(base, AXBS_MGPCR4_AULB_MASK, AXBS_MGPCR4_AULB(value)))
+#define AXBS_BWR_MGPCR4_AULB(base, value) (AXBS_WR_MGPCR4_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR5 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR5 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR5 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR5(base)     (AXBS_MGPCR5_REG(base))
+#define AXBS_WR_MGPCR5(base, value) (AXBS_MGPCR5_REG(base) = (value))
+#define AXBS_RMW_MGPCR5(base, mask, value) (AXBS_WR_MGPCR5(base, (AXBS_RD_MGPCR5(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) |  (value)))
+#define AXBS_CLR_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) & ~(value)))
+#define AXBS_TOG_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR5 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR5_AULB field. */
+#define AXBS_RD_MGPCR5_AULB(base) ((AXBS_MGPCR5_REG(base) & AXBS_MGPCR5_AULB_MASK) >> AXBS_MGPCR5_AULB_SHIFT)
+#define AXBS_BRD_MGPCR5_AULB(base) (AXBS_RD_MGPCR5_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR5_AULB(base, value) (AXBS_RMW_MGPCR5(base, AXBS_MGPCR5_AULB_MASK, AXBS_MGPCR5_AULB(value)))
+#define AXBS_BWR_MGPCR5_AULB(base, value) (AXBS_WR_MGPCR5_AULB(base, value))
+/*@}*/
+
+/*
+ * MK64F12 CAN
+ *
+ * Flex Controller Area Network module
+ *
+ * Registers defined in this header file:
+ * - CAN_MCR - Module Configuration Register
+ * - CAN_CTRL1 - Control 1 register
+ * - CAN_TIMER - Free Running Timer
+ * - CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ * - CAN_RX14MASK - Rx 14 Mask register
+ * - CAN_RX15MASK - Rx 15 Mask register
+ * - CAN_ECR - Error Counter
+ * - CAN_ESR1 - Error and Status 1 register
+ * - CAN_IMASK1 - Interrupt Masks 1 register
+ * - CAN_IFLAG1 - Interrupt Flags 1 register
+ * - CAN_CTRL2 - Control 2 register
+ * - CAN_ESR2 - Error and Status 2 register
+ * - CAN_CRCR - CRC Register
+ * - CAN_RXFGMASK - Rx FIFO Global Mask register
+ * - CAN_RXFIR - Rx FIFO Information Register
+ * - CAN_CS - Message Buffer 0 CS Register
+ * - CAN_ID - Message Buffer 0 ID Register
+ * - CAN_WORD0 - Message Buffer 0 WORD0 Register
+ * - CAN_WORD1 - Message Buffer 0 WORD1 Register
+ * - CAN_RXIMR - Rx Individual Mask Registers
+ */
+
+#define CAN_INSTANCE_COUNT (1U) /*!< Number of instances of the CAN module. */
+#define CAN0_IDX (0U) /*!< Instance number for CAN0. */
+
+/*******************************************************************************
+ * CAN_MCR - Module Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0xD890000FU
+ *
+ * This register defines global system configurations, such as the module
+ * operation modes and the maximum message buffer configuration.
+ */
+/*!
+ * @name Constants and macros for entire CAN_MCR register
+ */
+/*@{*/
+#define CAN_RD_MCR(base)         (CAN_MCR_REG(base))
+#define CAN_WR_MCR(base, value)  (CAN_MCR_REG(base) = (value))
+#define CAN_RMW_MCR(base, mask, value) (CAN_WR_MCR(base, (CAN_RD_MCR(base) & ~(mask)) | (value)))
+#define CAN_SET_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) |  (value)))
+#define CAN_CLR_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) & ~(value)))
+#define CAN_TOG_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_MCR bitfields
+ */
+
+/*!
+ * @name Register CAN_MCR, field MAXMB[6:0] (RW)
+ *
+ * This 7-bit field defines the number of the last Message Buffers that will
+ * take part in the matching and arbitration processes. The reset value (0x0F) is
+ * equivalent to a 16 MB configuration. This field can be written only in Freeze
+ * mode because it is blocked by hardware in other modes. Number of the last MB =
+ * MAXMB MAXMB must be programmed with a value smaller than the parameter
+ * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
+ * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
+ * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
+ * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
+ * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
+ * Matching Timing").
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_MAXMB field. */
+#define CAN_RD_MCR_MAXMB(base) ((CAN_MCR_REG(base) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT)
+#define CAN_BRD_MCR_MAXMB(base) (CAN_RD_MCR_MAXMB(base))
+
+/*! @brief Set the MAXMB field to a new value. */
+#define CAN_WR_MCR_MAXMB(base, value) (CAN_RMW_MCR(base, CAN_MCR_MAXMB_MASK, CAN_MCR_MAXMB(value)))
+#define CAN_BWR_MCR_MAXMB(base, value) (CAN_WR_MCR_MAXMB(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field IDAM[9:8] (RW)
+ *
+ * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
+ * elements. Note that all elements of the table are configured at the same time by this
+ * field (they are all the same format). See Section "Rx FIFO Structure". This
+ * field can be written only in Freeze mode because it is blocked by hardware in
+ * other modes.
+ *
+ * Values:
+ * - 0b00 - Format A: One full ID (standard and extended) per ID Filter Table
+ *     element.
+ * - 0b01 - Format B: Two full standard IDs or two partial 14-bit (standard and
+ *     extended) IDs per ID Filter Table element.
+ * - 0b10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table
+ *     element.
+ * - 0b11 - Format D: All frames rejected.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_IDAM field. */
+#define CAN_RD_MCR_IDAM(base) ((CAN_MCR_REG(base) & CAN_MCR_IDAM_MASK) >> CAN_MCR_IDAM_SHIFT)
+#define CAN_BRD_MCR_IDAM(base) (CAN_RD_MCR_IDAM(base))
+
+/*! @brief Set the IDAM field to a new value. */
+#define CAN_WR_MCR_IDAM(base, value) (CAN_RMW_MCR(base, CAN_MCR_IDAM_MASK, CAN_MCR_IDAM(value)))
+#define CAN_BWR_MCR_IDAM(base, value) (CAN_WR_MCR_IDAM(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field AEN[12] (RW)
+ *
+ * This bit is supplied for backwards compatibility with legacy applications.
+ * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
+ * safe procedure for aborting a pending transmission, so that no frame is sent in
+ * the CAN bus without notification. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
+ * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
+ * used for updating Mailboxes configured for transmission. Writing the Abort code
+ * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Abort disabled.
+ * - 0b1 - Abort enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_AEN field. */
+#define CAN_RD_MCR_AEN(base) ((CAN_MCR_REG(base) & CAN_MCR_AEN_MASK) >> CAN_MCR_AEN_SHIFT)
+#define CAN_BRD_MCR_AEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_AEN_SHIFT))
+
+/*! @brief Set the AEN field to a new value. */
+#define CAN_WR_MCR_AEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_AEN_MASK, CAN_MCR_AEN(value)))
+#define CAN_BWR_MCR_AEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_AEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field LPRIOEN[13] (RW)
+ *
+ * This bit is provided for backwards compatibility with legacy applications. It
+ * controls whether the local priority feature is enabled or not. It is used to
+ * expand the ID used during the arbitration process. With this expanded ID
+ * concept, the arbitration process is done based on the full 32-bit word, but the
+ * actual transmitted ID still has 11-bit for standard frames and 29-bit for
+ * extended frames. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Local Priority disabled.
+ * - 0b1 - Local Priority enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_LPRIOEN field. */
+#define CAN_RD_MCR_LPRIOEN(base) ((CAN_MCR_REG(base) & CAN_MCR_LPRIOEN_MASK) >> CAN_MCR_LPRIOEN_SHIFT)
+#define CAN_BRD_MCR_LPRIOEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPRIOEN_SHIFT))
+
+/*! @brief Set the LPRIOEN field to a new value. */
+#define CAN_WR_MCR_LPRIOEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_LPRIOEN_MASK, CAN_MCR_LPRIOEN(value)))
+#define CAN_BWR_MCR_LPRIOEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPRIOEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field IRMQ[16] (RW)
+ *
+ * This bit indicates whether Rx matching process will be based either on
+ * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
+ * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Individual Rx masking and queue feature are disabled. For backward
+ *     compatibility with legacy applications, the reading of C/S word locks the MB
+ *     even if it is EMPTY.
+ * - 0b1 - Individual Rx masking and queue feature are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_IRMQ field. */
+#define CAN_RD_MCR_IRMQ(base) ((CAN_MCR_REG(base) & CAN_MCR_IRMQ_MASK) >> CAN_MCR_IRMQ_SHIFT)
+#define CAN_BRD_MCR_IRMQ(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_IRMQ_SHIFT))
+
+/*! @brief Set the IRMQ field to a new value. */
+#define CAN_WR_MCR_IRMQ(base, value) (CAN_RMW_MCR(base, CAN_MCR_IRMQ_MASK, CAN_MCR_IRMQ(value)))
+#define CAN_BWR_MCR_IRMQ(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_IRMQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SRXDIS[17] (RW)
+ *
+ * This bit defines whether FlexCAN is allowed to receive frames transmitted by
+ * itself. If this bit is asserted, frames transmitted by the module will not be
+ * stored in any MB, regardless if the MB is programmed with an ID that matches
+ * the transmitted frame, and no interrupt flag or interrupt signal will be
+ * generated due to the frame reception. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Self reception enabled.
+ * - 0b1 - Self reception disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SRXDIS field. */
+#define CAN_RD_MCR_SRXDIS(base) ((CAN_MCR_REG(base) & CAN_MCR_SRXDIS_MASK) >> CAN_MCR_SRXDIS_SHIFT)
+#define CAN_BRD_MCR_SRXDIS(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SRXDIS_SHIFT))
+
+/*! @brief Set the SRXDIS field to a new value. */
+#define CAN_WR_MCR_SRXDIS(base, value) (CAN_RMW_MCR(base, CAN_MCR_SRXDIS_MASK, CAN_MCR_SRXDIS(value)))
+#define CAN_BWR_MCR_SRXDIS(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SRXDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WAKSRC[19] (RW)
+ *
+ * This bit defines whether the integrated low-pass filter is applied to protect
+ * the Rx CAN input from spurious wake up. This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ * - 0b1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WAKSRC field. */
+#define CAN_RD_MCR_WAKSRC(base) ((CAN_MCR_REG(base) & CAN_MCR_WAKSRC_MASK) >> CAN_MCR_WAKSRC_SHIFT)
+#define CAN_BRD_MCR_WAKSRC(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKSRC_SHIFT))
+
+/*! @brief Set the WAKSRC field to a new value. */
+#define CAN_WR_MCR_WAKSRC(base, value) (CAN_RMW_MCR(base, CAN_MCR_WAKSRC_MASK, CAN_MCR_WAKSRC(value)))
+#define CAN_BWR_MCR_WAKSRC(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field LPMACK[20] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
+ * mode , Stop mode ). A low-power mode cannot be entered until all current
+ * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
+ * to know when FlexCAN has actually entered low power mode. LPMACK will be
+ * asserted within 180 CAN bits from the low-power mode request by the CPU, and
+ * negated within 2 CAN bits after the low-power mode request removal (see Section
+ * "Protocol Timing").
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not in a low-power mode.
+ * - 0b1 - FlexCAN is in a low-power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_LPMACK field. */
+#define CAN_RD_MCR_LPMACK(base) ((CAN_MCR_REG(base) & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT)
+#define CAN_BRD_MCR_LPMACK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPMACK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WRNEN[21] (RW)
+ *
+ * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
+ * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
+ * RWRNINT flags will always be zero, independent of the values of the error
+ * counters, and no warning interrupt will ever be generated. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
+ *     error counters.
+ * - 0b1 - TWRNINT and RWRNINT bits are set when the respective error counter
+ *     transitions from less than 96 to greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WRNEN field. */
+#define CAN_RD_MCR_WRNEN(base) ((CAN_MCR_REG(base) & CAN_MCR_WRNEN_MASK) >> CAN_MCR_WRNEN_SHIFT)
+#define CAN_BRD_MCR_WRNEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WRNEN_SHIFT))
+
+/*! @brief Set the WRNEN field to a new value. */
+#define CAN_WR_MCR_WRNEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_WRNEN_MASK, CAN_MCR_WRNEN(value)))
+#define CAN_BWR_MCR_WRNEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WRNEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SLFWAK[22] (RW)
+ *
+ * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
+ * other than Disable mode. When this feature is enabled, the FlexCAN module
+ * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
+ * If a wake up event is detected during Stop mode, then FlexCAN generates, if
+ * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
+ * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
+ * low-power mode other than Disable mode, this bit cannot be written as it is
+ * blocked by hardware.
+ *
+ * Values:
+ * - 0b0 - FlexCAN Self Wake Up feature is disabled.
+ * - 0b1 - FlexCAN Self Wake Up feature is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SLFWAK field. */
+#define CAN_RD_MCR_SLFWAK(base) ((CAN_MCR_REG(base) & CAN_MCR_SLFWAK_MASK) >> CAN_MCR_SLFWAK_SHIFT)
+#define CAN_BRD_MCR_SLFWAK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SLFWAK_SHIFT))
+
+/*! @brief Set the SLFWAK field to a new value. */
+#define CAN_WR_MCR_SLFWAK(base, value) (CAN_RMW_MCR(base, CAN_MCR_SLFWAK_MASK, CAN_MCR_SLFWAK(value)))
+#define CAN_BWR_MCR_SLFWAK(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SLFWAK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SUPV[23] (RW)
+ *
+ * This bit configures the FlexCAN to be either in Supervisor or User mode. The
+ * registers affected by this bit are marked as S/U in the Access Type column of
+ * the module memory map. Reset value of this bit is 1, so the affected registers
+ * start with Supervisor access allowance only . This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
+ *     Unrestricted accesses .
+ * - 0b1 - FlexCAN is in Supervisor mode. Affected registers allow only
+ *     Supervisor access. Unrestricted access behaves as though the access was done to an
+ *     unimplemented register location .
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SUPV field. */
+#define CAN_RD_MCR_SUPV(base) ((CAN_MCR_REG(base) & CAN_MCR_SUPV_MASK) >> CAN_MCR_SUPV_SHIFT)
+#define CAN_BRD_MCR_SUPV(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SUPV_SHIFT))
+
+/*! @brief Set the SUPV field to a new value. */
+#define CAN_WR_MCR_SUPV(base, value) (CAN_RMW_MCR(base, CAN_MCR_SUPV_MASK, CAN_MCR_SUPV(value)))
+#define CAN_BWR_MCR_SUPV(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SUPV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field FRZACK[24] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
+ * is stopped. The Freeze mode request cannot be granted until current
+ * transmission or reception processes have finished. Therefore the software can poll the
+ * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
+ * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
+ * running again. If Freeze mode is requested while FlexCAN is in a low power
+ * mode, then the FRZACK bit will be set only when the low-power mode is exited.
+ * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
+ * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
+ * mode request removal (see Section "Protocol Timing").
+ *
+ * Values:
+ * - 0b0 - FlexCAN not in Freeze mode, prescaler running.
+ * - 0b1 - FlexCAN in Freeze mode, prescaler stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_FRZACK field. */
+#define CAN_RD_MCR_FRZACK(base) ((CAN_MCR_REG(base) & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)
+#define CAN_BRD_MCR_FRZACK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZACK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SOFTRST[25] (RW)
+ *
+ * When this bit is asserted, FlexCAN resets its internal state machines and
+ * some of the memory mapped registers. The following registers are reset: MCR
+ * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
+ * CRCR. Configuration registers that control the interface to the CAN bus are
+ * not affected by soft reset. The following registers are unaffected: CTRL1,
+ * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
+ * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
+ * writes to the MCR Register, but it is also asserted when global soft reset is
+ * requested at MCU level . Because soft reset is synchronous and has to follow a
+ * request/acknowledge procedure across clock domains, it may take some time to
+ * fully propagate its effect. The SOFTRST bit remains asserted while reset is
+ * pending, and is automatically negated when reset completes. Therefore, software can
+ * poll this bit to know when the soft reset has completed. Soft reset cannot be
+ * applied while clocks are shut down in a low power mode. The module should be
+ * first removed from low power mode, and then soft reset can be applied.
+ *
+ * Values:
+ * - 0b0 - No reset request.
+ * - 0b1 - Resets the registers affected by soft reset.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SOFTRST field. */
+#define CAN_RD_MCR_SOFTRST(base) ((CAN_MCR_REG(base) & CAN_MCR_SOFTRST_MASK) >> CAN_MCR_SOFTRST_SHIFT)
+#define CAN_BRD_MCR_SOFTRST(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SOFTRST_SHIFT))
+
+/*! @brief Set the SOFTRST field to a new value. */
+#define CAN_WR_MCR_SOFTRST(base, value) (CAN_RMW_MCR(base, CAN_MCR_SOFTRST_MASK, CAN_MCR_SOFTRST(value)))
+#define CAN_BWR_MCR_SOFTRST(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SOFTRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WAKMSK[26] (RW)
+ *
+ * This bit enables the Wake Up Interrupt generation under Self Wake Up
+ * mechanism.
+ *
+ * Values:
+ * - 0b0 - Wake Up Interrupt is disabled.
+ * - 0b1 - Wake Up Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WAKMSK field. */
+#define CAN_RD_MCR_WAKMSK(base) ((CAN_MCR_REG(base) & CAN_MCR_WAKMSK_MASK) >> CAN_MCR_WAKMSK_SHIFT)
+#define CAN_BRD_MCR_WAKMSK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKMSK_SHIFT))
+
+/*! @brief Set the WAKMSK field to a new value. */
+#define CAN_WR_MCR_WAKMSK(base, value) (CAN_RMW_MCR(base, CAN_MCR_WAKMSK_MASK, CAN_MCR_WAKMSK(value)))
+#define CAN_BWR_MCR_WAKMSK(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field NOTRDY[27] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
+ * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN module is either in Normal mode, Listen-Only mode or
+ *     Loop-Back mode.
+ * - 0b1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_NOTRDY field. */
+#define CAN_RD_MCR_NOTRDY(base) ((CAN_MCR_REG(base) & CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT)
+#define CAN_BRD_MCR_NOTRDY(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_NOTRDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field HALT[28] (RW)
+ *
+ * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
+ * should clear it after initializing the Message Buffers and Control Register. No
+ * reception or transmission is performed by FlexCAN before this bit is cleared.
+ * Freeze mode cannot be entered while FlexCAN is in a low power mode.
+ *
+ * Values:
+ * - 0b0 - No Freeze mode request.
+ * - 0b1 - Enters Freeze mode if the FRZ bit is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_HALT field. */
+#define CAN_RD_MCR_HALT(base) ((CAN_MCR_REG(base) & CAN_MCR_HALT_MASK) >> CAN_MCR_HALT_SHIFT)
+#define CAN_BRD_MCR_HALT(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define CAN_WR_MCR_HALT(base, value) (CAN_RMW_MCR(base, CAN_MCR_HALT_MASK, CAN_MCR_HALT(value)))
+#define CAN_BWR_MCR_HALT(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field RFEN[29] (RW)
+ *
+ * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
+ * set, MBs 0 to 5 cannot be used for normal reception and transmission because
+ * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
+ * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
+ * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
+ * minimum number of peripheral clocks per CAN bit as described in the table
+ * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
+ * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Rx FIFO not enabled.
+ * - 0b1 - Rx FIFO enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_RFEN field. */
+#define CAN_RD_MCR_RFEN(base) ((CAN_MCR_REG(base) & CAN_MCR_RFEN_MASK) >> CAN_MCR_RFEN_SHIFT)
+#define CAN_BRD_MCR_RFEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_RFEN_SHIFT))
+
+/*! @brief Set the RFEN field to a new value. */
+#define CAN_WR_MCR_RFEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_RFEN_MASK, CAN_MCR_RFEN(value)))
+#define CAN_BWR_MCR_RFEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_RFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field FRZ[30] (RW)
+ *
+ * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
+ * Register is set or when Debug mode is requested at MCU level . When FRZ is
+ * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
+ * FlexCAN to exit from Freeze mode.
+ *
+ * Values:
+ * - 0b0 - Not enabled to enter Freeze mode.
+ * - 0b1 - Enabled to enter Freeze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_FRZ field. */
+#define CAN_RD_MCR_FRZ(base) ((CAN_MCR_REG(base) & CAN_MCR_FRZ_MASK) >> CAN_MCR_FRZ_SHIFT)
+#define CAN_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define CAN_WR_MCR_FRZ(base, value) (CAN_RMW_MCR(base, CAN_MCR_FRZ_MASK, CAN_MCR_FRZ(value)))
+#define CAN_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field MDIS[31] (RW)
+ *
+ * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
+ * disables the clocks to the CAN Protocol Engine and Controller Host Interface
+ * sub-modules. This is the only bit within this register not affected by soft
+ * reset.
+ *
+ * Values:
+ * - 0b0 - Enable the FlexCAN module.
+ * - 0b1 - Disable the FlexCAN module.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_MDIS field. */
+#define CAN_RD_MCR_MDIS(base) ((CAN_MCR_REG(base) & CAN_MCR_MDIS_MASK) >> CAN_MCR_MDIS_SHIFT)
+#define CAN_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define CAN_WR_MCR_MDIS(base, value) (CAN_RMW_MCR(base, CAN_MCR_MDIS_MASK, CAN_MCR_MDIS(value)))
+#define CAN_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CTRL1 - Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CTRL1 - Control 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is defined for specific FlexCAN control features related to the
+ * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
+ * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
+ * (Bus-Off, Error, Warning). It also determines the Division Factor for the
+ * clock prescaler.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CTRL1 register
+ */
+/*@{*/
+#define CAN_RD_CTRL1(base)       (CAN_CTRL1_REG(base))
+#define CAN_WR_CTRL1(base, value) (CAN_CTRL1_REG(base) = (value))
+#define CAN_RMW_CTRL1(base, mask, value) (CAN_WR_CTRL1(base, (CAN_RD_CTRL1(base) & ~(mask)) | (value)))
+#define CAN_SET_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) |  (value)))
+#define CAN_CLR_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) & ~(value)))
+#define CAN_TOG_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CTRL1 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
+ *
+ * This 3-bit field defines the length of the Propagation Segment in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Propagation
+ * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PROPSEG field. */
+#define CAN_RD_CTRL1_PROPSEG(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PROPSEG_MASK) >> CAN_CTRL1_PROPSEG_SHIFT)
+#define CAN_BRD_CTRL1_PROPSEG(base) (CAN_RD_CTRL1_PROPSEG(base))
+
+/*! @brief Set the PROPSEG field to a new value. */
+#define CAN_WR_CTRL1_PROPSEG(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PROPSEG_MASK, CAN_CTRL1_PROPSEG(value)))
+#define CAN_BWR_CTRL1_PROPSEG(base, value) (CAN_WR_CTRL1_PROPSEG(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LOM[3] (RW)
+ *
+ * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
+ * transmission is disabled, all error counters are frozen and the module operates
+ * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
+ * will be received. If FlexCAN detects a message that has not been acknowledged,
+ * it will flag a BIT0 error without changing the REC, as if it was trying to
+ * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
+ * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
+ * entered. There can be some delay between the Listen-Only mode request and
+ * acknowledge. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Listen-Only mode is deactivated.
+ * - 0b1 - FlexCAN module operates in Listen-Only mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LOM field. */
+#define CAN_RD_CTRL1_LOM(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LOM_MASK) >> CAN_CTRL1_LOM_SHIFT)
+#define CAN_BRD_CTRL1_LOM(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LOM_SHIFT))
+
+/*! @brief Set the LOM field to a new value. */
+#define CAN_WR_CTRL1_LOM(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LOM_MASK, CAN_CTRL1_LOM(value)))
+#define CAN_BWR_CTRL1_LOM(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LBUF[4] (RW)
+ *
+ * This bit defines the ordering mechanism for Message Buffer transmission. When
+ * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0b0 - Buffer with highest priority is transmitted first.
+ * - 0b1 - Lowest number buffer is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LBUF field. */
+#define CAN_RD_CTRL1_LBUF(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LBUF_MASK) >> CAN_CTRL1_LBUF_SHIFT)
+#define CAN_BRD_CTRL1_LBUF(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LBUF_SHIFT))
+
+/*! @brief Set the LBUF field to a new value. */
+#define CAN_WR_CTRL1_LBUF(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LBUF_MASK, CAN_CTRL1_LBUF(value)))
+#define CAN_BWR_CTRL1_LBUF(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field TSYN[5] (RW)
+ *
+ * This bit enables a mechanism that resets the free-running timer each time a
+ * message is received in Message Buffer 0. This feature provides means to
+ * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
+ * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
+ * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
+ * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Timer Sync feature disabled
+ * - 0b1 - Timer Sync feature enabled
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_TSYN field. */
+#define CAN_RD_CTRL1_TSYN(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_TSYN_MASK) >> CAN_CTRL1_TSYN_SHIFT)
+#define CAN_BRD_CTRL1_TSYN(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TSYN_SHIFT))
+
+/*! @brief Set the TSYN field to a new value. */
+#define CAN_WR_CTRL1_TSYN(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_TSYN_MASK, CAN_CTRL1_TSYN(value)))
+#define CAN_BWR_CTRL1_TSYN(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TSYN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
+ *
+ * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
+ * negated, automatic recovering from Bus Off state occurs according to the CAN
+ * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
+ * disabled and the module remains in Bus Off state until the bit is negated by the
+ * user. If the negation occurs before 128 sequences of 11 recessive bits are
+ * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
+ * never been asserted. If the negation occurs after 128 sequences of 11
+ * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
+ * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
+ * be re-asserted again during Bus Off, but it will be effective only the next
+ * time the module enters Bus Off. If BOFFREC was negated when the module entered
+ * Bus Off, asserting it during Bus Off will not be effective for the current Bus
+ * Off recovery.
+ *
+ * Values:
+ * - 0b0 - Automatic recovering from Bus Off state enabled, according to CAN
+ *     Spec 2.0 part B.
+ * - 0b1 - Automatic recovering from Bus Off state disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_BOFFREC field. */
+#define CAN_RD_CTRL1_BOFFREC(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_BOFFREC_MASK) >> CAN_CTRL1_BOFFREC_SHIFT)
+#define CAN_BRD_CTRL1_BOFFREC(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFREC_SHIFT))
+
+/*! @brief Set the BOFFREC field to a new value. */
+#define CAN_WR_CTRL1_BOFFREC(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_BOFFREC_MASK, CAN_CTRL1_BOFFREC(value)))
+#define CAN_BWR_CTRL1_BOFFREC(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFREC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field SMP[7] (RW)
+ *
+ * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
+ * be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0b0 - Just one sample is used to determine the bit value.
+ * - 0b1 - Three samples are used to determine the value of the received bit:
+ *     the regular one (sample point) and 2 preceding samples; a majority rule is
+ *     used.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_SMP field. */
+#define CAN_RD_CTRL1_SMP(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_SMP_MASK) >> CAN_CTRL1_SMP_SHIFT)
+#define CAN_BRD_CTRL1_SMP(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_SMP_SHIFT))
+
+/*! @brief Set the SMP field to a new value. */
+#define CAN_WR_CTRL1_SMP(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_SMP_MASK, CAN_CTRL1_SMP(value)))
+#define CAN_BWR_CTRL1_SMP(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_SMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
+ *
+ * This bit provides a mask for the Rx Warning Interrupt associated with the
+ * RWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Rx Warning Interrupt disabled.
+ * - 0b1 - Rx Warning Interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_RWRNMSK field. */
+#define CAN_RD_CTRL1_RWRNMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_RWRNMSK_MASK) >> CAN_CTRL1_RWRNMSK_SHIFT)
+#define CAN_BRD_CTRL1_RWRNMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_RWRNMSK_SHIFT))
+
+/*! @brief Set the RWRNMSK field to a new value. */
+#define CAN_WR_CTRL1_RWRNMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_RWRNMSK_MASK, CAN_CTRL1_RWRNMSK(value)))
+#define CAN_BWR_CTRL1_RWRNMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_RWRNMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
+ *
+ * This bit provides a mask for the Tx Warning Interrupt associated with the
+ * TWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Tx Warning Interrupt disabled.
+ * - 0b1 - Tx Warning Interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_TWRNMSK field. */
+#define CAN_RD_CTRL1_TWRNMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_TWRNMSK_MASK) >> CAN_CTRL1_TWRNMSK_SHIFT)
+#define CAN_BRD_CTRL1_TWRNMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TWRNMSK_SHIFT))
+
+/*! @brief Set the TWRNMSK field to a new value. */
+#define CAN_WR_CTRL1_TWRNMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_TWRNMSK_MASK, CAN_CTRL1_TWRNMSK(value)))
+#define CAN_BWR_CTRL1_TWRNMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TWRNMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LPB[12] (RW)
+ *
+ * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
+ * FlexCAN performs an internal loop back that can be used for self test operation.
+ * The bit stream output of the transmitter is fed back internally to the receiver
+ * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
+ * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
+ * and treats its own transmitted message as a message received from a remote
+ * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
+ * frame acknowledge field, generating an internal acknowledge bit to ensure proper
+ * reception of its own message. Both transmit and receive interrupts are
+ * generated. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
+ * this will impede the self reception of a transmitted message.
+ *
+ * Values:
+ * - 0b0 - Loop Back disabled.
+ * - 0b1 - Loop Back enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LPB field. */
+#define CAN_RD_CTRL1_LPB(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LPB_MASK) >> CAN_CTRL1_LPB_SHIFT)
+#define CAN_BRD_CTRL1_LPB(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LPB_SHIFT))
+
+/*! @brief Set the LPB field to a new value. */
+#define CAN_WR_CTRL1_LPB(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LPB_MASK, CAN_CTRL1_LPB(value)))
+#define CAN_BWR_CTRL1_LPB(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LPB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
+ *
+ * This bit selects the clock source to the CAN Protocol Engine (PE) to be
+ * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
+ * The selected clock is the one fed to the prescaler to generate the Serial Clock
+ * (Sclock). In order to guarantee reliable operation, this bit can be written
+ * only in Disable mode because it is blocked by hardware in other modes. See
+ * Section "Protocol Timing".
+ *
+ * Values:
+ * - 0b0 - The CAN engine clock source is the oscillator clock. Under this
+ *     condition, the oscillator clock frequency must be lower than the bus clock.
+ * - 0b1 - The CAN engine clock source is the peripheral clock.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_CLKSRC field. */
+#define CAN_RD_CTRL1_CLKSRC(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_CLKSRC_MASK) >> CAN_CTRL1_CLKSRC_SHIFT)
+#define CAN_BRD_CTRL1_CLKSRC(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_CLKSRC_SHIFT))
+
+/*! @brief Set the CLKSRC field to a new value. */
+#define CAN_WR_CTRL1_CLKSRC(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_CLKSRC_MASK, CAN_CTRL1_CLKSRC(value)))
+#define CAN_BWR_CTRL1_CLKSRC(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_CLKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
+ *
+ * This bit provides a mask for the Error Interrupt.
+ *
+ * Values:
+ * - 0b0 - Error interrupt disabled.
+ * - 0b1 - Error interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_ERRMSK field. */
+#define CAN_RD_CTRL1_ERRMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_ERRMSK_MASK) >> CAN_CTRL1_ERRMSK_SHIFT)
+#define CAN_BRD_CTRL1_ERRMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_ERRMSK_SHIFT))
+
+/*! @brief Set the ERRMSK field to a new value. */
+#define CAN_WR_CTRL1_ERRMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_ERRMSK_MASK, CAN_CTRL1_ERRMSK(value)))
+#define CAN_BWR_CTRL1_ERRMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_ERRMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
+ *
+ * This bit provides a mask for the Bus Off Interrupt.
+ *
+ * Values:
+ * - 0b0 - Bus Off interrupt disabled.
+ * - 0b1 - Bus Off interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_BOFFMSK field. */
+#define CAN_RD_CTRL1_BOFFMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_BOFFMSK_MASK) >> CAN_CTRL1_BOFFMSK_SHIFT)
+#define CAN_BRD_CTRL1_BOFFMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFMSK_SHIFT))
+
+/*! @brief Set the BOFFMSK field to a new value. */
+#define CAN_WR_CTRL1_BOFFMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_BOFFMSK_MASK, CAN_CTRL1_BOFFMSK(value)))
+#define CAN_BWR_CTRL1_BOFFMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
+ * time. The valid programmable values are 1-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 2 = (PSEG2 + 1) * Time-Quanta.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PSEG2 field. */
+#define CAN_RD_CTRL1_PSEG2(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PSEG2_MASK) >> CAN_CTRL1_PSEG2_SHIFT)
+#define CAN_BRD_CTRL1_PSEG2(base) (CAN_RD_CTRL1_PSEG2(base))
+
+/*! @brief Set the PSEG2 field to a new value. */
+#define CAN_WR_CTRL1_PSEG2(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PSEG2_MASK, CAN_CTRL1_PSEG2(value)))
+#define CAN_BWR_CTRL1_PSEG2(base, value) (CAN_WR_CTRL1_PSEG2(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 1 = (PSEG1 + 1) * Time-Quanta.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PSEG1 field. */
+#define CAN_RD_CTRL1_PSEG1(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PSEG1_MASK) >> CAN_CTRL1_PSEG1_SHIFT)
+#define CAN_BRD_CTRL1_PSEG1(base) (CAN_RD_CTRL1_PSEG1(base))
+
+/*! @brief Set the PSEG1 field to a new value. */
+#define CAN_WR_CTRL1_PSEG1(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PSEG1_MASK, CAN_CTRL1_PSEG1(value)))
+#define CAN_BWR_CTRL1_PSEG1(base, value) (CAN_WR_CTRL1_PSEG1(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field RJW[23:22] (RW)
+ *
+ * This 2-bit field defines the maximum number of time quanta that a bit time
+ * can be changed by one re-synchronization. One time quantum is equal to the
+ * Sclock period. The valid programmable values are 0-3. This field can be written
+ * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
+ * Width = RJW + 1.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_RJW field. */
+#define CAN_RD_CTRL1_RJW(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_RJW_MASK) >> CAN_CTRL1_RJW_SHIFT)
+#define CAN_BRD_CTRL1_RJW(base) (CAN_RD_CTRL1_RJW(base))
+
+/*! @brief Set the RJW field to a new value. */
+#define CAN_WR_CTRL1_RJW(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_RJW_MASK, CAN_CTRL1_RJW(value)))
+#define CAN_BWR_CTRL1_RJW(base, value) (CAN_WR_CTRL1_RJW(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
+ *
+ * This 8-bit field defines the ratio between the PE clock frequency and the
+ * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
+ * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
+ * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
+ * Sclock frequency equal to the PE clock frequency divided by 256. See Section
+ * "Protocol Timing". This field can be written only in Freeze mode because it is
+ * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
+ * (PRESDIV + 1)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PRESDIV field. */
+#define CAN_RD_CTRL1_PRESDIV(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PRESDIV_MASK) >> CAN_CTRL1_PRESDIV_SHIFT)
+#define CAN_BRD_CTRL1_PRESDIV(base) (CAN_RD_CTRL1_PRESDIV(base))
+
+/*! @brief Set the PRESDIV field to a new value. */
+#define CAN_WR_CTRL1_PRESDIV(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PRESDIV_MASK, CAN_CTRL1_PRESDIV(value)))
+#define CAN_BWR_CTRL1_PRESDIV(base, value) (CAN_WR_CTRL1_PRESDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_TIMER - Free Running Timer
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_TIMER - Free Running Timer (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register represents a 16-bit free running counter that can be read and
+ * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
+ * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
+ * defines the baud rate on the CAN bus. During a message transmission/reception,
+ * it increments by one for each bit that is received or transmitted. When there
+ * is no message on the bus, it counts using the previously programmed baud
+ * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
+ * timer value is captured when the second bit of the identifier field of any frame
+ * is on the CAN bus. This captured value is written into the Time Stamp entry
+ * in a message buffer after a successful reception or transmission of a message.
+ * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
+ * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
+ * can write to this register anytime. However, if the write occurs at the same
+ * time that the Timer is being reset by a reception in the first Mailbox, then
+ * the write value is discarded. Reading this register affects the Mailbox
+ * Unlocking procedure; see Section "Mailbox Lock Mechanism".
+ */
+/*!
+ * @name Constants and macros for entire CAN_TIMER register
+ */
+/*@{*/
+#define CAN_RD_TIMER(base)       (CAN_TIMER_REG(base))
+#define CAN_WR_TIMER(base, value) (CAN_TIMER_REG(base) = (value))
+#define CAN_RMW_TIMER(base, mask, value) (CAN_WR_TIMER(base, (CAN_RD_TIMER(base) & ~(mask)) | (value)))
+#define CAN_SET_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) |  (value)))
+#define CAN_CLR_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) & ~(value)))
+#define CAN_TOG_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_TIMER bitfields
+ */
+
+/*!
+ * @name Register CAN_TIMER, field TIMER[15:0] (RW)
+ *
+ * Contains the free-running counter value.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_TIMER_TIMER field. */
+#define CAN_RD_TIMER_TIMER(base) ((CAN_TIMER_REG(base) & CAN_TIMER_TIMER_MASK) >> CAN_TIMER_TIMER_SHIFT)
+#define CAN_BRD_TIMER_TIMER(base) (CAN_RD_TIMER_TIMER(base))
+
+/*! @brief Set the TIMER field to a new value. */
+#define CAN_WR_TIMER_TIMER(base, value) (CAN_RMW_TIMER(base, CAN_TIMER_TIMER_MASK, CAN_TIMER_TIMER(value)))
+#define CAN_BWR_TIMER_TIMER(base, value) (CAN_WR_TIMER_TIMER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RXMGMASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
+ * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
+ * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
+ * mask registers. This register can only be written in Freeze mode as it is
+ * blocked by hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXMGMASK register
+ */
+/*@{*/
+#define CAN_RD_RXMGMASK(base)    (CAN_RXMGMASK_REG(base))
+#define CAN_WR_RXMGMASK(base, value) (CAN_RXMGMASK_REG(base) = (value))
+#define CAN_RMW_RXMGMASK(base, mask, value) (CAN_WR_RXMGMASK(base, (CAN_RD_RXMGMASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) |  (value)))
+#define CAN_CLR_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) & ~(value)))
+#define CAN_TOG_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RX14MASK - Rx 14 Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RX14MASK - Rx 14 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX14MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
+ * is used to mask the filter fields of Message Buffer 14. This register can only
+ * be programmed while the module is in Freeze mode as it is blocked by hardware
+ * in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RX14MASK register
+ */
+/*@{*/
+#define CAN_RD_RX14MASK(base)    (CAN_RX14MASK_REG(base))
+#define CAN_WR_RX14MASK(base, value) (CAN_RX14MASK_REG(base) = (value))
+#define CAN_RMW_RX14MASK(base, mask, value) (CAN_WR_RX14MASK(base, (CAN_RD_RX14MASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) |  (value)))
+#define CAN_CLR_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) & ~(value)))
+#define CAN_TOG_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RX15MASK - Rx 15 Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RX15MASK - Rx 15 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX15MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
+ * is used to mask the filter fields of Message Buffer 15. This register can be
+ * programmed only while the module is in Freeze mode because it is blocked by
+ * hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RX15MASK register
+ */
+/*@{*/
+#define CAN_RD_RX15MASK(base)    (CAN_RX15MASK_REG(base))
+#define CAN_WR_RX15MASK(base, value) (CAN_RX15MASK_REG(base) = (value))
+#define CAN_RMW_RX15MASK(base, mask, value) (CAN_WR_RX15MASK(base, (CAN_RD_RX15MASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) |  (value)))
+#define CAN_CLR_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) & ~(value)))
+#define CAN_TOG_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ECR - Error Counter
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ECR - Error Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has two 8-bit fields reflecting the value of two FlexCAN error
+ * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
+ * (RXERRCNT field). The rules for increasing and decreasing these counters are
+ * described in the CAN protocol and are completely implemented in the FlexCAN
+ * module. Both counters are read-only except in Freeze mode, where they can be
+ * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
+ * for example, transmit Error Active or Error Passive flag, delay its
+ * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
+ * Off state. The following are the basic rules for FlexCAN bus state transitions:
+ * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
+ * 128, the FLTCONF field in the Error and Status Register is updated to reflect
+ * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
+ * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
+ * other already satisfies this condition, the FLTCONF field in the Error and
+ * Status Register is updated to reflect 'Error Active' state. If the value of
+ * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
+ * Register is updated to reflect 'Bus Off' state, and an interrupt may be
+ * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
+ * state, then TXERRCNT is cascaded together with another internal counter to count
+ * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
+ * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
+ * 11 such bits and then wraps around while incrementing the TXERRCNT. When
+ * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
+ * Register is updated to be 'Error Active' and both error counters are reset to zero.
+ * At any instance of dominant bit following a stream of less than 11
+ * consecutive recessive bits, the internal counter resets itself to zero without affecting
+ * the TXERRCNT value. If during system start-up, only one node is operating,
+ * then its TXERRCNT increases in each message it is trying to transmit, as a
+ * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
+ * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
+ * increment anymore by acknowledge errors. Therefore the device never goes to
+ * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
+ * is not incremented further, even if more errors are detected while being a
+ * receiver. At the next successful message reception, the counter is set to a value
+ * between 119 and 127 to resume to 'Error Active' state.
+ */
+/*!
+ * @name Constants and macros for entire CAN_ECR register
+ */
+/*@{*/
+#define CAN_RD_ECR(base)         (CAN_ECR_REG(base))
+#define CAN_WR_ECR(base, value)  (CAN_ECR_REG(base) = (value))
+#define CAN_RMW_ECR(base, mask, value) (CAN_WR_ECR(base, (CAN_RD_ECR(base) & ~(mask)) | (value)))
+#define CAN_SET_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) |  (value)))
+#define CAN_CLR_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) & ~(value)))
+#define CAN_TOG_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ECR bitfields
+ */
+
+/*!
+ * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ECR_TXERRCNT field. */
+#define CAN_RD_ECR_TXERRCNT(base) ((CAN_ECR_REG(base) & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT)
+#define CAN_BRD_ECR_TXERRCNT(base) (CAN_RD_ECR_TXERRCNT(base))
+
+/*! @brief Set the TXERRCNT field to a new value. */
+#define CAN_WR_ECR_TXERRCNT(base, value) (CAN_RMW_ECR(base, CAN_ECR_TXERRCNT_MASK, CAN_ECR_TXERRCNT(value)))
+#define CAN_BWR_ECR_TXERRCNT(base, value) (CAN_WR_ECR_TXERRCNT(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ECR_RXERRCNT field. */
+#define CAN_RD_ECR_RXERRCNT(base) ((CAN_ECR_REG(base) & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT)
+#define CAN_BRD_ECR_RXERRCNT(base) (CAN_RD_ECR_RXERRCNT(base))
+
+/*! @brief Set the RXERRCNT field to a new value. */
+#define CAN_WR_ECR_RXERRCNT(base, value) (CAN_RMW_ECR(base, CAN_ECR_RXERRCNT_MASK, CAN_ECR_RXERRCNT(value)))
+#define CAN_BWR_ECR_RXERRCNT(base, value) (CAN_WR_ECR_RXERRCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ESR1 - Error and Status 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ESR1 - Error and Status 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various error conditions, some general status of the
+ * device and it is the source of interrupts to the CPU. The CPU read action
+ * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
+ * that occurred since the last time the CPU read this register. Bits 9-3 are
+ * status bits. The following table shows the FlexCAN state variables and their
+ * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
+ * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
+ * Transmitting 1 0 0 1 Receiving
+ */
+/*!
+ * @name Constants and macros for entire CAN_ESR1 register
+ */
+/*@{*/
+#define CAN_RD_ESR1(base)        (CAN_ESR1_REG(base))
+#define CAN_WR_ESR1(base, value) (CAN_ESR1_REG(base) = (value))
+#define CAN_RMW_ESR1(base, mask, value) (CAN_WR_ESR1(base, (CAN_RD_ESR1(base) & ~(mask)) | (value)))
+#define CAN_SET_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) |  (value)))
+#define CAN_CLR_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) & ~(value)))
+#define CAN_TOG_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ESR1 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR1, field WAKINT[0] (W1C)
+ *
+ * This field applies when FlexCAN is in low-power mode under Self Wake Up
+ * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
+ * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
+ * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
+ * is masked. The CPU must clear this flag before disabling the bit. Otherwise
+ * it will be set when the SLFWAK is set again. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - Indicates a recessive to dominant transition was received on the CAN
+ *     bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_WAKINT field. */
+#define CAN_RD_ESR1_WAKINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_WAKINT_MASK) >> CAN_ESR1_WAKINT_SHIFT)
+#define CAN_BRD_ESR1_WAKINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_WAKINT_SHIFT))
+
+/*! @brief Set the WAKINT field to a new value. */
+#define CAN_WR_ESR1_WAKINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_WAKINT(value)))
+#define CAN_BWR_ESR1_WAKINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_WAKINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field ERRINT[1] (W1C)
+ *
+ * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
+ * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
+ * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - Indicates setting of any Error Bit in the Error and Status Register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_ERRINT field. */
+#define CAN_RD_ESR1_ERRINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_ERRINT_MASK) >> CAN_ESR1_ERRINT_SHIFT)
+#define CAN_BRD_ESR1_ERRINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ERRINT_SHIFT))
+
+/*! @brief Set the ERRINT field to a new value. */
+#define CAN_WR_ESR1_ERRINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_ERRINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_ERRINT(value)))
+#define CAN_BWR_ESR1_ERRINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ERRINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
+ *
+ * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
+ * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
+ * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - FlexCAN module entered Bus Off state.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BOFFINT field. */
+#define CAN_RD_ESR1_BOFFINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BOFFINT_MASK) >> CAN_ESR1_BOFFINT_SHIFT)
+#define CAN_BRD_ESR1_BOFFINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BOFFINT_SHIFT))
+
+/*! @brief Set the BOFFINT field to a new value. */
+#define CAN_WR_ESR1_BOFFINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_BOFFINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_BOFFINT(value)))
+#define CAN_BWR_ESR1_BOFFINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BOFFINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RX[3] (RO)
+ *
+ * This bit indicates if FlexCAN is receiving a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not receiving a message.
+ * - 0b1 - FlexCAN is receiving a message.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RX field. */
+#define CAN_RD_ESR1_RX(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RX_MASK) >> CAN_ESR1_RX_SHIFT)
+#define CAN_BRD_ESR1_RX(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
+ *
+ * This 2-bit field indicates the Confinement State of the FlexCAN module. If
+ * the LOM bit in the Control Register is asserted, after some delay that depends
+ * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
+ * same delay affects the way how FLTCONF reflects an update to ECR register by
+ * the CPU. It may be necessary up to one CAN bit time to get them coherent
+ * again. Because the Control Register is not affected by soft reset, the FLTCONF
+ * field will not be affected by soft reset if the LOM bit is asserted.
+ *
+ * Values:
+ * - 0b00 - Error Active
+ * - 0b01 - Error Passive
+ * - 0b1x - Bus Off
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_FLTCONF field. */
+#define CAN_RD_ESR1_FLTCONF(base) ((CAN_ESR1_REG(base) & CAN_ESR1_FLTCONF_MASK) >> CAN_ESR1_FLTCONF_SHIFT)
+#define CAN_BRD_ESR1_FLTCONF(base) (CAN_RD_ESR1_FLTCONF(base))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TX[6] (RO)
+ *
+ * This bit indicates if FlexCAN is transmitting a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not transmitting a message.
+ * - 0b1 - FlexCAN is transmitting a message.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TX field. */
+#define CAN_RD_ESR1_TX(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TX_MASK) >> CAN_ESR1_TX_SHIFT)
+#define CAN_BRD_ESR1_TX(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field IDLE[7] (RO)
+ *
+ * This bit indicates when CAN bus is in IDLE state. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - CAN bus is now IDLE.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_IDLE field. */
+#define CAN_RD_ESR1_IDLE(base) ((CAN_ESR1_REG(base) & CAN_ESR1_IDLE_MASK) >> CAN_ESR1_IDLE_SHIFT)
+#define CAN_BRD_ESR1_IDLE(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RXWRN[8] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * reception. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - RXERRCNT is greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RXWRN field. */
+#define CAN_RD_ESR1_RXWRN(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RXWRN_MASK) >> CAN_ESR1_RXWRN_SHIFT)
+#define CAN_BRD_ESR1_RXWRN(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RXWRN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TXWRN[9] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * transmission. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - TXERRCNT is greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TXWRN field. */
+#define CAN_RD_ESR1_TXWRN(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TXWRN_MASK) >> CAN_ESR1_TXWRN_SHIFT)
+#define CAN_BRD_ESR1_TXWRN(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TXWRN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field STFERR[10] (RO)
+ *
+ * This bit indicates that a Stuffing Error has been etected.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A Stuffing Error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_STFERR field. */
+#define CAN_RD_ESR1_STFERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_STFERR_MASK) >> CAN_ESR1_STFERR_SHIFT)
+#define CAN_BRD_ESR1_STFERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_STFERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field FRMERR[11] (RO)
+ *
+ * This bit indicates that a Form Error has been detected by the receiver node,
+ * that is, a fixed-form bit field contains at least one illegal bit.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A Form Error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_FRMERR field. */
+#define CAN_RD_ESR1_FRMERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_FRMERR_MASK) >> CAN_ESR1_FRMERR_SHIFT)
+#define CAN_BRD_ESR1_FRMERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_FRMERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field CRCERR[12] (RO)
+ *
+ * This bit indicates that a CRC Error has been detected by the receiver node,
+ * that is, the calculated CRC is different from the received.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A CRC error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_CRCERR field. */
+#define CAN_RD_ESR1_CRCERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_CRCERR_MASK) >> CAN_ESR1_CRCERR_SHIFT)
+#define CAN_BRD_ESR1_CRCERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_CRCERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field ACKERR[13] (RO)
+ *
+ * This bit indicates that an Acknowledge Error has been detected by the
+ * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - An ACK error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_ACKERR field. */
+#define CAN_RD_ESR1_ACKERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_ACKERR_MASK) >> CAN_ESR1_ACKERR_SHIFT)
+#define CAN_BRD_ESR1_ACKERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ACKERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - At least one bit sent as dominant is received as recessive.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BIT0ERR field. */
+#define CAN_RD_ESR1_BIT0ERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BIT0ERR_MASK) >> CAN_ESR1_BIT0ERR_SHIFT)
+#define CAN_BRD_ESR1_BIT0ERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BIT0ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message. This bit is not set by a transmitter in case of
+ * arbitration field or ACK slot, or in case of a node sending a passive error
+ * flag that detects dominant bits.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - At least one bit sent as recessive is received as dominant.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BIT1ERR field. */
+#define CAN_RD_ESR1_BIT1ERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BIT1ERR_MASK) >> CAN_ESR1_BIT1ERR_SHIFT)
+#define CAN_BRD_ESR1_BIT1ERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BIT1ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
+ * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
+ * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
+ * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - The Rx error counter transitioned from less than 96 to greater than
+ *     or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RWRNINT field. */
+#define CAN_RD_ESR1_RWRNINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RWRNINT_MASK) >> CAN_ESR1_RWRNINT_SHIFT)
+#define CAN_BRD_ESR1_RWRNINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RWRNINT_SHIFT))
+
+/*! @brief Set the RWRNINT field to a new value. */
+#define CAN_WR_ESR1_RWRNINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_RWRNINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_RWRNINT(value)))
+#define CAN_BWR_ESR1_RWRNINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RWRNINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
+ * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
+ * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
+ * is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This flag is not generated during Bus Off state. This bit is not
+ * updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - The Tx error counter transitioned from less than 96 to greater than
+ *     or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TWRNINT field. */
+#define CAN_RD_ESR1_TWRNINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TWRNINT_MASK) >> CAN_ESR1_TWRNINT_SHIFT)
+#define CAN_BRD_ESR1_TWRNINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TWRNINT_SHIFT))
+
+/*! @brief Set the TWRNINT field to a new value. */
+#define CAN_WR_ESR1_TWRNINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_TWRNINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK), CAN_ESR1_TWRNINT(value)))
+#define CAN_BWR_ESR1_TWRNINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TWRNINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field SYNCH[18] (RO)
+ *
+ * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
+ * bus and able to participate in the communication process. It is set and
+ * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not synchronized to the CAN bus.
+ * - 0b1 - FlexCAN is synchronized to the CAN bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_SYNCH field. */
+#define CAN_RD_ESR1_SYNCH(base) ((CAN_ESR1_REG(base) & CAN_ESR1_SYNCH_MASK) >> CAN_ESR1_SYNCH_SHIFT)
+#define CAN_BRD_ESR1_SYNCH(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_SYNCH_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_IMASK1 - Interrupt Masks 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_IMASK1 - Interrupt Masks 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register allows any number of a range of the 32 Message Buffer
+ * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
+ * bit per buffer, enabling the CPU to determine which buffer generates an
+ * interrupt after a successful transmission or reception, that is, when the
+ * corresponding IFLAG1 bit is set.
+ */
+/*!
+ * @name Constants and macros for entire CAN_IMASK1 register
+ */
+/*@{*/
+#define CAN_RD_IMASK1(base)      (CAN_IMASK1_REG(base))
+#define CAN_WR_IMASK1(base, value) (CAN_IMASK1_REG(base) = (value))
+#define CAN_RMW_IMASK1(base, mask, value) (CAN_WR_IMASK1(base, (CAN_RD_IMASK1(base) & ~(mask)) | (value)))
+#define CAN_SET_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) |  (value)))
+#define CAN_CLR_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) & ~(value)))
+#define CAN_TOG_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_IFLAG1 - Interrupt Flags 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the flags for the 32 Message Buffer interrupts for MB31
+ * to MB0. It contains one interrupt flag bit per buffer. Each successful
+ * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
+ * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
+ * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
+ * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
+ * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
+ * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
+ * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
+ * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
+ * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
+ * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
+ * the FIFO flags must be cleared. The same care must be taken when an RFFN
+ * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
+ * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
+ * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
+ * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
+ * they will remain set and be inconsistent with the number of MBs available.
+ */
+/*!
+ * @name Constants and macros for entire CAN_IFLAG1 register
+ */
+/*@{*/
+#define CAN_RD_IFLAG1(base)      (CAN_IFLAG1_REG(base))
+#define CAN_WR_IFLAG1(base, value) (CAN_IFLAG1_REG(base) = (value))
+#define CAN_RMW_IFLAG1(base, mask, value) (CAN_WR_IFLAG1(base, (CAN_RD_IFLAG1(base) & ~(mask)) | (value)))
+#define CAN_SET_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) |  (value)))
+#define CAN_CLR_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) & ~(value)))
+#define CAN_TOG_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_IFLAG1 bitfields
+ */
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
+ * set.
+ *
+ * Values:
+ * - 0b0 - The corresponding buffer has no occurrence of successfully completed
+ *     transmission or reception when MCR[RFEN]=0.
+ * - 0b1 - The corresponding buffer has successfully completed transmission or
+ *     reception when MCR[RFEN]=0.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF0I field. */
+#define CAN_RD_IFLAG1_BUF0I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF0I_MASK) >> CAN_IFLAG1_BUF0I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF0I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF0I_SHIFT))
+
+/*! @brief Set the BUF0I field to a new value. */
+#define CAN_WR_IFLAG1_BUF0I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF0I(value)))
+#define CAN_BWR_IFLAG1_BUF0I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF0I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
+ * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
+ * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
+ * when MCR[RFEN] is set.
+ *
+ * Values:
+ * - 0b0000 - The corresponding buffer has no occurrence of successfully
+ *     completed transmission or reception when MCR[RFEN]=0.
+ * - 0b0001 - The corresponding buffer has successfully completed transmission
+ *     or reception when MCR[RFEN]=0.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field. */
+#define CAN_RD_IFLAG1_BUF4TO1I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF4TO1I_MASK) >> CAN_IFLAG1_BUF4TO1I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF4TO1I(base) (CAN_RD_IFLAG1_BUF4TO1I(base))
+
+/*! @brief Set the BUF4TO1I field to a new value. */
+#define CAN_WR_IFLAG1_BUF4TO1I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF4TO1I(value)))
+#define CAN_BWR_IFLAG1_BUF4TO1I(base, value) (CAN_WR_IFLAG1_BUF4TO1I(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
+ * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
+ * least one frame is available to be read from the Rx FIFO.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB5 completing transmission/reception when
+ *     MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
+ * - 0b1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
+ *     available in the Rx FIFO when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF5I field. */
+#define CAN_RD_IFLAG1_BUF5I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF5I_MASK) >> CAN_IFLAG1_BUF5I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF5I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF5I_SHIFT))
+
+/*! @brief Set the BUF5I field to a new value. */
+#define CAN_WR_IFLAG1_BUF5I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF5I(value)))
+#define CAN_BWR_IFLAG1_BUF5I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF5I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
+ * when MCR[RFEN] is set. In this case, the flag indicates when the number of
+ * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
+ * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
+ * cleared while the number of unread messages is greater than 4, it does not
+ * assert again until the number of unread messages within the Rx FIFO is decreased
+ * to be equal to or less than 4.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB6 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
+ * - 0b1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     almost full when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF6I field. */
+#define CAN_RD_IFLAG1_BUF6I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF6I_MASK) >> CAN_IFLAG1_BUF6I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF6I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF6I_SHIFT))
+
+/*! @brief Set the BUF6I field to a new value. */
+#define CAN_WR_IFLAG1_BUF6I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF6I(value)))
+#define CAN_BWR_IFLAG1_BUF6I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF6I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
+ * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
+ * because the Rx FIFO is full. Note that the flag will not be asserted when the
+ * Rx FIFO is full and the message was captured by a Mailbox.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB7 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
+ * - 0b1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     overflow when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF7I field. */
+#define CAN_RD_IFLAG1_BUF7I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF7I_MASK) >> CAN_IFLAG1_BUF7I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF7I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF7I_SHIFT))
+
+/*! @brief Set the BUF7I field to a new value. */
+#define CAN_WR_IFLAG1_BUF7I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF7I(value)))
+#define CAN_BWR_IFLAG1_BUF7I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF7I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
+ *
+ * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
+ * MB8.
+ *
+ * Values:
+ * - 0b000000000000000000000000 - The corresponding buffer has no occurrence of
+ *     successfully completed transmission or reception.
+ * - 0b000000000000000000000001 - The corresponding buffer has successfully
+ *     completed transmission or reception.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field. */
+#define CAN_RD_IFLAG1_BUF31TO8I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF31TO8I_MASK) >> CAN_IFLAG1_BUF31TO8I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF31TO8I(base) (CAN_RD_IFLAG1_BUF31TO8I(base))
+
+/*! @brief Set the BUF31TO8I field to a new value. */
+#define CAN_WR_IFLAG1_BUF31TO8I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF31TO8I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK), CAN_IFLAG1_BUF31TO8I(value)))
+#define CAN_BWR_IFLAG1_BUF31TO8I(base, value) (CAN_WR_IFLAG1_BUF31TO8I(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CTRL2 - Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CTRL2 - Control 2 register (RW)
+ *
+ * Reset value: 0x00B00000U
+ *
+ * This register contains control bits for CAN errors, FIFO features, and mode
+ * selection.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CTRL2 register
+ */
+/*@{*/
+#define CAN_RD_CTRL2(base)       (CAN_CTRL2_REG(base))
+#define CAN_WR_CTRL2(base, value) (CAN_CTRL2_REG(base) = (value))
+#define CAN_RMW_CTRL2(base, mask, value) (CAN_WR_CTRL2(base, (CAN_RD_CTRL2(base) & ~(mask)) | (value)))
+#define CAN_SET_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) |  (value)))
+#define CAN_CLR_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) & ~(value)))
+#define CAN_TOG_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CTRL2 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL2, field EACEN[16] (RW)
+ *
+ * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
+ * filters with their corresponding bits in the incoming frame by the matching
+ * process. This bit does not affect matching for Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
+ *     compared despite mask bits.
+ * - 0b1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit
+ *     with their corresponding bits within the incoming frame. Mask bits do apply.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_EACEN field. */
+#define CAN_RD_CTRL2_EACEN(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_EACEN_MASK) >> CAN_CTRL2_EACEN_SHIFT)
+#define CAN_BRD_CTRL2_EACEN(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_EACEN_SHIFT))
+
+/*! @brief Set the EACEN field to a new value. */
+#define CAN_WR_CTRL2_EACEN(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_EACEN_MASK, CAN_CTRL2_EACEN(value)))
+#define CAN_BWR_CTRL2_EACEN(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_EACEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field RRS[17] (RW)
+ *
+ * If this bit is asserted Remote Request Frame is submitted to a matching
+ * process and stored in the corresponding Message Buffer in the same fashion of a
+ * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
+ * negated the Remote Request Frame is submitted to a matching process and an
+ * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
+ * is found with the same ID. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Remote Response Frame is generated.
+ * - 0b1 - Remote Request Frame is stored.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_RRS field. */
+#define CAN_RD_CTRL2_RRS(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_RRS_MASK) >> CAN_CTRL2_RRS_SHIFT)
+#define CAN_BRD_CTRL2_RRS(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_RRS_SHIFT))
+
+/*! @brief Set the RRS field to a new value. */
+#define CAN_WR_CTRL2_RRS(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_RRS_MASK, CAN_CTRL2_RRS(value)))
+#define CAN_BWR_CTRL2_RRS(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_RRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field MRP[18] (RW)
+ *
+ * If this bit is set the matching process starts from the Mailboxes and if no
+ * match occurs the matching continues on the Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Matching starts from Rx FIFO and continues on Mailboxes.
+ * - 0b1 - Matching starts from Mailboxes and continues on Rx FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_MRP field. */
+#define CAN_RD_CTRL2_MRP(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_MRP_MASK) >> CAN_CTRL2_MRP_SHIFT)
+#define CAN_BRD_CTRL2_MRP(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_MRP_SHIFT))
+
+/*! @brief Set the MRP field to a new value. */
+#define CAN_WR_CTRL2_MRP(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_MRP_MASK, CAN_CTRL2_MRP(value)))
+#define CAN_BWR_CTRL2_MRP(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_MRP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field TASD[23:19] (RW)
+ *
+ * This 5-bit field indicates how many CAN bits the Tx arbitration process start
+ * point can be delayed from the first bit of CRC field on CAN bus. This field
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes. This field is useful to optimize the transmit performance based on
+ * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
+ * The duration of an arbitration process, in terms of CAN bits, is directly
+ * proportional to the number of available MBs and CAN baud rate and inversely
+ * proportional to the peripheral clock frequency. The optimal arbitration timing is
+ * that in which the last MB is scanned right before the first bit of the
+ * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
+ * clock ratio is high and the CAN baud rate is low then the arbitration can be
+ * delayed and vice-versa. If TASD is 0 then the arbitration start is not
+ * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
+ * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
+ * the CPU can configure a Tx MB later and less time is reserved for
+ * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
+ * to find winner MBs in time to compete with other nodes for the CAN bus. If the
+ * arbitration ends too much time before the first bit of Intermission field then
+ * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
+ * not the best to be transmitted. The optimal configuration for TASD can be
+ * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
+ * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
+ * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
+ * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
+ * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
+ * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
+ * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
+ * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
+ * Timing" for more details.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_TASD field. */
+#define CAN_RD_CTRL2_TASD(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_TASD_MASK) >> CAN_CTRL2_TASD_SHIFT)
+#define CAN_BRD_CTRL2_TASD(base) (CAN_RD_CTRL2_TASD(base))
+
+/*! @brief Set the TASD field to a new value. */
+#define CAN_WR_CTRL2_TASD(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_TASD_MASK, CAN_CTRL2_TASD(value)))
+#define CAN_BWR_CTRL2_TASD(base, value) (CAN_WR_CTRL2_TASD(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
+ *
+ * This 4-bit field defines the number of Rx FIFO filters, as shown in the
+ * following table. The maximum selectable number of filters is determined by the MCU.
+ * This field can only be written in Freeze mode as it is blocked by hardware in
+ * other modes. This field must not be programmed with values that make the
+ * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
+ * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
+ * a memory space equivalent to two Message Buffers which means that the more
+ * filters are implemented the less Mailboxes will be available. Considering that
+ * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
+ * be programmed with a value correponding to a number of filters not greater
+ * than the number of available memory words which can be calculated as follows:
+ * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
+ * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
+ * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
+ * SETUP_MB value (memory space available) the exceeding ones will not be functional.
+ * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
+ * Filter Table Remaining Available MailboxesThe number of the last remaining
+ * available mailboxes is defined by the least value between the parameter
+ * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
+ * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
+ * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
+ * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
+ * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
+ * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
+ * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
+ * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
+ * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
+ * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
+ * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
+ * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
+ * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
+ * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
+ * 0-37 MB 38-63 Elements 0-31 Elements 32-127
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_RFFN field. */
+#define CAN_RD_CTRL2_RFFN(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT)
+#define CAN_BRD_CTRL2_RFFN(base) (CAN_RD_CTRL2_RFFN(base))
+
+/*! @brief Set the RFFN field to a new value. */
+#define CAN_WR_CTRL2_RFFN(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_RFFN_MASK, CAN_CTRL2_RFFN(value)))
+#define CAN_BWR_CTRL2_RFFN(base, value) (CAN_WR_CTRL2_RFFN(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
+ *
+ * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
+ * can only be written in Freeze mode and has no effect out of Freeze mode.
+ *
+ * Values:
+ * - 0b0 - Maintain the write access restrictions.
+ * - 0b1 - Enable unrestricted write access to FlexCAN memory.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_WRMFRZ field. */
+#define CAN_RD_CTRL2_WRMFRZ(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_WRMFRZ_MASK) >> CAN_CTRL2_WRMFRZ_SHIFT)
+#define CAN_BRD_CTRL2_WRMFRZ(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_WRMFRZ_SHIFT))
+
+/*! @brief Set the WRMFRZ field to a new value. */
+#define CAN_WR_CTRL2_WRMFRZ(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_WRMFRZ_MASK, CAN_CTRL2_WRMFRZ(value)))
+#define CAN_BWR_CTRL2_WRMFRZ(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_WRMFRZ_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ESR2 - Error and Status 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ESR2 - Error and Status 2 register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various interrupt flags and some general status.
+ */
+/*!
+ * @name Constants and macros for entire CAN_ESR2 register
+ */
+/*@{*/
+#define CAN_RD_ESR2(base)        (CAN_ESR2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ESR2 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR2, field IMB[13] (RO)
+ *
+ * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
+ * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
+ * following cases: During arbitration, if an LPTM is found and it is inactive. If
+ * IMB is not asserted and a frame is transmitted successfully. This bit is
+ * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
+ * mechanism have the following behavior: if an MB is successfully transmitted and
+ * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
+ * the index related to the MB just transmitted is loaded into ESR2[LPTM].
+ *
+ * Values:
+ * - 0b0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
+ * - 0b1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox.
+ *     LPTM content is the number of the first one.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_IMB field. */
+#define CAN_RD_ESR2_IMB(base) ((CAN_ESR2_REG(base) & CAN_ESR2_IMB_MASK) >> CAN_ESR2_IMB_SHIFT)
+#define CAN_BRD_ESR2_IMB(base) (BITBAND_ACCESS32(&CAN_ESR2_REG(base), CAN_ESR2_IMB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR2, field VPS[14] (RO)
+ *
+ * This bit indicates whether IMB and LPTM contents are currently valid or not.
+ * VPS is asserted upon every complete Tx arbitration process unless the CPU
+ * writes to Control and Status word of a Mailbox that has already been scanned, that
+ * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
+ * If there is no inactive Mailbox and only one Tx Mailbox that is being
+ * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
+ * arbitration process or upon a write to Control and Status word of any Mailbox.
+ * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
+ * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
+ * in C/S of a MB that is being transmitted (pending abort), or any write attempt
+ * into a Tx MB with IFLAG set is blocked.
+ *
+ * Values:
+ * - 0b0 - Contents of IMB and LPTM are invalid.
+ * - 0b1 - Contents of IMB and LPTM are valid.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_VPS field. */
+#define CAN_RD_ESR2_VPS(base) ((CAN_ESR2_REG(base) & CAN_ESR2_VPS_MASK) >> CAN_ESR2_VPS_SHIFT)
+#define CAN_BRD_ESR2_VPS(base) (BITBAND_ACCESS32(&CAN_ESR2_REG(base), CAN_ESR2_VPS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR2, field LPTM[22:16] (RO)
+ *
+ * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
+ * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
+ * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
+ * negated then the Mailbox indicated is the one that has the greatest arbitration
+ * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
+ * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
+ * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
+ * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
+ * updated with its Mailbox number.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_LPTM field. */
+#define CAN_RD_ESR2_LPTM(base) ((CAN_ESR2_REG(base) & CAN_ESR2_LPTM_MASK) >> CAN_ESR2_LPTM_SHIFT)
+#define CAN_BRD_ESR2_LPTM(base) (CAN_RD_ESR2_LPTM(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CRCR - CRC Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CRCR - CRC Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides information about the CRC of transmitted messages.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CRCR register
+ */
+/*@{*/
+#define CAN_RD_CRCR(base)        (CAN_CRCR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CRCR bitfields
+ */
+
+/*!
+ * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
+ *
+ * This field indicates the CRC value of the last message transmitted. This
+ * field is updated at the same time the Tx Interrupt Flag is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CRCR_TXCRC field. */
+#define CAN_RD_CRCR_TXCRC(base) ((CAN_CRCR_REG(base) & CAN_CRCR_TXCRC_MASK) >> CAN_CRCR_TXCRC_SHIFT)
+#define CAN_BRD_CRCR_TXCRC(base) (CAN_RD_CRCR_TXCRC(base))
+/*@}*/
+
+/*!
+ * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
+ *
+ * This field indicates the number of the Mailbox corresponding to the value in
+ * TXCRC field.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CRCR_MBCRC field. */
+#define CAN_RD_CRCR_MBCRC(base) ((CAN_CRCR_REG(base) & CAN_CRCR_MBCRC_MASK) >> CAN_CRCR_MBCRC_SHIFT)
+#define CAN_BRD_CRCR_MBCRC(base) (CAN_RD_CRCR_MBCRC(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXFGMASK - Rx FIFO Global Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
+ * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
+ * according to CTRL2[RFFN] field setting. This register can only be written in
+ * Freeze mode as it is blocked by hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXFGMASK register
+ */
+/*@{*/
+#define CAN_RD_RXFGMASK(base)    (CAN_RXFGMASK_REG(base))
+#define CAN_WR_RXFGMASK(base, value) (CAN_RXFGMASK_REG(base) = (value))
+#define CAN_RMW_RXFGMASK(base, mask, value) (CAN_WR_RXFGMASK(base, (CAN_RD_RXFGMASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) |  (value)))
+#define CAN_CLR_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) & ~(value)))
+#define CAN_TOG_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXFIR - Rx FIFO Information Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXFIR - Rx FIFO Information Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFIR provides information on Rx FIFO. This register is the port through
+ * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
+ * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
+ * well as its output is updated whenever the output of the Rx FIFO is updated
+ * with the next message. See Section "Rx FIFO" for instructions on reading this
+ * register.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXFIR register
+ */
+/*@{*/
+#define CAN_RD_RXFIR(base)       (CAN_RXFIR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_RXFIR bitfields
+ */
+
+/*!
+ * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
+ *
+ * This field indicates which Identifier Acceptance Filter was hit by the
+ * received message that is in the output of the Rx FIFO. If multiple filters match the
+ * incoming message ID then the first matching IDAF found (lowest number) by the
+ * matching process is indicated. This field is valid only while the
+ * IFLAG[BUF5I] is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_RXFIR_IDHIT field. */
+#define CAN_RD_RXFIR_IDHIT(base) ((CAN_RXFIR_REG(base) & CAN_RXFIR_IDHIT_MASK) >> CAN_RXFIR_IDHIT_SHIFT)
+#define CAN_BRD_RXFIR_IDHIT(base) (CAN_RD_RXFIR_IDHIT(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CS - Message Buffer 0 CS Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CS - Message Buffer 0 CS Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_CS register
+ */
+/*@{*/
+#define CAN_RD_CS(base, index)   (CAN_CS_REG(base, index))
+#define CAN_WR_CS(base, index, value) (CAN_CS_REG(base, index) = (value))
+#define CAN_RMW_CS(base, index, mask, value) (CAN_WR_CS(base, index, (CAN_RD_CS(base, index) & ~(mask)) | (value)))
+#define CAN_SET_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) |  (value)))
+#define CAN_CLR_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) & ~(value)))
+#define CAN_TOG_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CS bitfields
+ */
+
+/*!
+ * @name Register CAN_CS, field TIME_STAMP[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_TIME_STAMP field. */
+#define CAN_RD_CS_TIME_STAMP(base, index) ((CAN_CS_REG(base, index) & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT)
+#define CAN_BRD_CS_TIME_STAMP(base, index) (CAN_RD_CS_TIME_STAMP(base, index))
+
+/*! @brief Set the TIME_STAMP field to a new value. */
+#define CAN_WR_CS_TIME_STAMP(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_TIME_STAMP_MASK, CAN_CS_TIME_STAMP(value)))
+#define CAN_BWR_CS_TIME_STAMP(base, index, value) (CAN_WR_CS_TIME_STAMP(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field DLC[19:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_DLC field. */
+#define CAN_RD_CS_DLC(base, index) ((CAN_CS_REG(base, index) & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT)
+#define CAN_BRD_CS_DLC(base, index) (CAN_RD_CS_DLC(base, index))
+
+/*! @brief Set the DLC field to a new value. */
+#define CAN_WR_CS_DLC(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_DLC_MASK, CAN_CS_DLC(value)))
+#define CAN_BWR_CS_DLC(base, index, value) (CAN_WR_CS_DLC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field RTR[20] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_RTR field. */
+#define CAN_RD_CS_RTR(base, index) ((CAN_CS_REG(base, index) & CAN_CS_RTR_MASK) >> CAN_CS_RTR_SHIFT)
+#define CAN_BRD_CS_RTR(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_RTR_SHIFT))
+
+/*! @brief Set the RTR field to a new value. */
+#define CAN_WR_CS_RTR(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_RTR_MASK, CAN_CS_RTR(value)))
+#define CAN_BWR_CS_RTR(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_RTR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field IDE[21] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_IDE field. */
+#define CAN_RD_CS_IDE(base, index) ((CAN_CS_REG(base, index) & CAN_CS_IDE_MASK) >> CAN_CS_IDE_SHIFT)
+#define CAN_BRD_CS_IDE(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_IDE_SHIFT))
+
+/*! @brief Set the IDE field to a new value. */
+#define CAN_WR_CS_IDE(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_IDE_MASK, CAN_CS_IDE(value)))
+#define CAN_BWR_CS_IDE(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_IDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field SRR[22] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_SRR field. */
+#define CAN_RD_CS_SRR(base, index) ((CAN_CS_REG(base, index) & CAN_CS_SRR_MASK) >> CAN_CS_SRR_SHIFT)
+#define CAN_BRD_CS_SRR(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_SRR_SHIFT))
+
+/*! @brief Set the SRR field to a new value. */
+#define CAN_WR_CS_SRR(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_SRR_MASK, CAN_CS_SRR(value)))
+#define CAN_BWR_CS_SRR(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_SRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field CODE[27:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_CODE field. */
+#define CAN_RD_CS_CODE(base, index) ((CAN_CS_REG(base, index) & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT)
+#define CAN_BRD_CS_CODE(base, index) (CAN_RD_CS_CODE(base, index))
+
+/*! @brief Set the CODE field to a new value. */
+#define CAN_WR_CS_CODE(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_CODE_MASK, CAN_CS_CODE(value)))
+#define CAN_BWR_CS_CODE(base, index, value) (CAN_WR_CS_CODE(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ID - Message Buffer 0 ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ID - Message Buffer 0 ID Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_ID register
+ */
+/*@{*/
+#define CAN_RD_ID(base, index)   (CAN_ID_REG(base, index))
+#define CAN_WR_ID(base, index, value) (CAN_ID_REG(base, index) = (value))
+#define CAN_RMW_ID(base, index, mask, value) (CAN_WR_ID(base, index, (CAN_RD_ID(base, index) & ~(mask)) | (value)))
+#define CAN_SET_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) |  (value)))
+#define CAN_CLR_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) & ~(value)))
+#define CAN_TOG_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ID bitfields
+ */
+
+/*!
+ * @name Register CAN_ID, field EXT[17:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_EXT field. */
+#define CAN_RD_ID_EXT(base, index) ((CAN_ID_REG(base, index) & CAN_ID_EXT_MASK) >> CAN_ID_EXT_SHIFT)
+#define CAN_BRD_ID_EXT(base, index) (CAN_RD_ID_EXT(base, index))
+
+/*! @brief Set the EXT field to a new value. */
+#define CAN_WR_ID_EXT(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_EXT_MASK, CAN_ID_EXT(value)))
+#define CAN_BWR_ID_EXT(base, index, value) (CAN_WR_ID_EXT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ID, field STD[28:18] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_STD field. */
+#define CAN_RD_ID_STD(base, index) ((CAN_ID_REG(base, index) & CAN_ID_STD_MASK) >> CAN_ID_STD_SHIFT)
+#define CAN_BRD_ID_STD(base, index) (CAN_RD_ID_STD(base, index))
+
+/*! @brief Set the STD field to a new value. */
+#define CAN_WR_ID_STD(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_STD_MASK, CAN_ID_STD(value)))
+#define CAN_BWR_ID_STD(base, index, value) (CAN_WR_ID_STD(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ID, field PRIO[31:29] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_PRIO field. */
+#define CAN_RD_ID_PRIO(base, index) ((CAN_ID_REG(base, index) & CAN_ID_PRIO_MASK) >> CAN_ID_PRIO_SHIFT)
+#define CAN_BRD_ID_PRIO(base, index) (CAN_RD_ID_PRIO(base, index))
+
+/*! @brief Set the PRIO field to a new value. */
+#define CAN_WR_ID_PRIO(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_PRIO_MASK, CAN_ID_PRIO(value)))
+#define CAN_BWR_ID_PRIO(base, index, value) (CAN_WR_ID_PRIO(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_WORD0 - Message Buffer 0 WORD0 Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_WORD0 - Message Buffer 0 WORD0 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_WORD0 register
+ */
+/*@{*/
+#define CAN_RD_WORD0(base, index) (CAN_WORD0_REG(base, index))
+#define CAN_WR_WORD0(base, index, value) (CAN_WORD0_REG(base, index) = (value))
+#define CAN_RMW_WORD0(base, index, mask, value) (CAN_WR_WORD0(base, index, (CAN_RD_WORD0(base, index) & ~(mask)) | (value)))
+#define CAN_SET_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) |  (value)))
+#define CAN_CLR_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) & ~(value)))
+#define CAN_TOG_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_WORD0 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_3[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_3 field. */
+#define CAN_RD_WORD0_DATA_BYTE_3(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_3_MASK) >> CAN_WORD0_DATA_BYTE_3_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_3(base, index) (CAN_RD_WORD0_DATA_BYTE_3(base, index))
+
+/*! @brief Set the DATA_BYTE_3 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_3(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_3_MASK, CAN_WORD0_DATA_BYTE_3(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_3(base, index, value) (CAN_WR_WORD0_DATA_BYTE_3(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_2[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_2 field. */
+#define CAN_RD_WORD0_DATA_BYTE_2(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_2_MASK) >> CAN_WORD0_DATA_BYTE_2_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_2(base, index) (CAN_RD_WORD0_DATA_BYTE_2(base, index))
+
+/*! @brief Set the DATA_BYTE_2 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_2(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_2_MASK, CAN_WORD0_DATA_BYTE_2(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_2(base, index, value) (CAN_WR_WORD0_DATA_BYTE_2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_1[23:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_1 field. */
+#define CAN_RD_WORD0_DATA_BYTE_1(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_1_MASK) >> CAN_WORD0_DATA_BYTE_1_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_1(base, index) (CAN_RD_WORD0_DATA_BYTE_1(base, index))
+
+/*! @brief Set the DATA_BYTE_1 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_1(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_1_MASK, CAN_WORD0_DATA_BYTE_1(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_1(base, index, value) (CAN_WR_WORD0_DATA_BYTE_1(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_0[31:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_0 field. */
+#define CAN_RD_WORD0_DATA_BYTE_0(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_0_MASK) >> CAN_WORD0_DATA_BYTE_0_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_0(base, index) (CAN_RD_WORD0_DATA_BYTE_0(base, index))
+
+/*! @brief Set the DATA_BYTE_0 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_0(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_0_MASK, CAN_WORD0_DATA_BYTE_0(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_0(base, index, value) (CAN_WR_WORD0_DATA_BYTE_0(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_WORD1 - Message Buffer 0 WORD1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_WORD1 - Message Buffer 0 WORD1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_WORD1 register
+ */
+/*@{*/
+#define CAN_RD_WORD1(base, index) (CAN_WORD1_REG(base, index))
+#define CAN_WR_WORD1(base, index, value) (CAN_WORD1_REG(base, index) = (value))
+#define CAN_RMW_WORD1(base, index, mask, value) (CAN_WR_WORD1(base, index, (CAN_RD_WORD1(base, index) & ~(mask)) | (value)))
+#define CAN_SET_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) |  (value)))
+#define CAN_CLR_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) & ~(value)))
+#define CAN_TOG_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_WORD1 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_7[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_7 field. */
+#define CAN_RD_WORD1_DATA_BYTE_7(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_7_MASK) >> CAN_WORD1_DATA_BYTE_7_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_7(base, index) (CAN_RD_WORD1_DATA_BYTE_7(base, index))
+
+/*! @brief Set the DATA_BYTE_7 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_7(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_7_MASK, CAN_WORD1_DATA_BYTE_7(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_7(base, index, value) (CAN_WR_WORD1_DATA_BYTE_7(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_6[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_6 field. */
+#define CAN_RD_WORD1_DATA_BYTE_6(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_6_MASK) >> CAN_WORD1_DATA_BYTE_6_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_6(base, index) (CAN_RD_WORD1_DATA_BYTE_6(base, index))
+
+/*! @brief Set the DATA_BYTE_6 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_6(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_6_MASK, CAN_WORD1_DATA_BYTE_6(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_6(base, index, value) (CAN_WR_WORD1_DATA_BYTE_6(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_5[23:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_5 field. */
+#define CAN_RD_WORD1_DATA_BYTE_5(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_5_MASK) >> CAN_WORD1_DATA_BYTE_5_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_5(base, index) (CAN_RD_WORD1_DATA_BYTE_5(base, index))
+
+/*! @brief Set the DATA_BYTE_5 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_5(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_5_MASK, CAN_WORD1_DATA_BYTE_5(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_5(base, index, value) (CAN_WR_WORD1_DATA_BYTE_5(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_4[31:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_4 field. */
+#define CAN_RD_WORD1_DATA_BYTE_4(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_4_MASK) >> CAN_WORD1_DATA_BYTE_4_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_4(base, index) (CAN_RD_WORD1_DATA_BYTE_4(base, index))
+
+/*! @brief Set the DATA_BYTE_4 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_4(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_4_MASK, CAN_WORD1_DATA_BYTE_4(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_4(base, index, value) (CAN_WR_WORD1_DATA_BYTE_4(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXIMR - Rx Individual Mask Registers
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXIMR - Rx Individual Mask Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers are located in RAM. RXIMR are used as acceptance masks for ID
+ * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
+ * register is provided for each available Mailbox, providing ID masking
+ * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
+ * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
+ * Table elements on a one-to-one correspondence depending on the setting of
+ * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
+ * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
+ * are not affected by reset and must be explicitly initialized prior to any
+ * reception.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXIMR register
+ */
+/*@{*/
+#define CAN_RD_RXIMR(base, index) (CAN_RXIMR_REG(base, index))
+#define CAN_WR_RXIMR(base, index, value) (CAN_RXIMR_REG(base, index) = (value))
+#define CAN_RMW_RXIMR(base, index, mask, value) (CAN_WR_RXIMR(base, index, (CAN_RD_RXIMR(base, index) & ~(mask)) | (value)))
+#define CAN_SET_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) |  (value)))
+#define CAN_CLR_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) & ~(value)))
+#define CAN_TOG_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 CAU
+ *
+ * Memory Mapped Cryptographic Acceleration Unit (MMCAU)
+ *
+ * Registers defined in this header file:
+ * - CAU_DIRECT - Direct access register 0
+ * - CAU_LDR_CASR - Status register - Load Register command
+ * - CAU_LDR_CAA - Accumulator register - Load Register command
+ * - CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ * - CAU_STR_CASR - Status register - Store Register command
+ * - CAU_STR_CAA - Accumulator register - Store Register command
+ * - CAU_STR_CA - General Purpose Register 0 - Store Register command
+ * - CAU_ADR_CASR - Status register - Add Register command
+ * - CAU_ADR_CAA - Accumulator register - Add to register command
+ * - CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ * - CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ * - CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ * - CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ * - CAU_XOR_CASR - Status register - Exclusive Or command
+ * - CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ * - CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ * - CAU_ROTL_CASR - Status register - Rotate Left command
+ * - CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ * - CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ * - CAU_AESC_CASR - Status register - AES Column Operation command
+ * - CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ * - CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ * - CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ * - CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ * - CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ */
+
+#define CAU_INSTANCE_COUNT (1U) /*!< Number of instances of the CAU module. */
+#define CAU_IDX (0U) /*!< Instance number for CAU. */
+
+/*******************************************************************************
+ * CAU_DIRECT - Direct access register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_DIRECT - Direct access register 0 (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_DIRECT register
+ */
+/*@{*/
+#define CAU_WR_DIRECT(base, index, value) (CAU_DIRECT_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CASR - Status register - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CASR - Status register - Load Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CASR register
+ */
+/*@{*/
+#define CAU_WR_LDR_CASR(base, value) (CAU_LDR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_LDR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_LDR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_LDR_CASR_IC(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_IC(value)))
+#define CAU_BWR_LDR_CASR_IC(base, value) (CAU_WR_LDR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_LDR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_LDR_CASR_DPE(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_DPE(value)))
+#define CAU_BWR_LDR_CASR_DPE(base, value) (CAU_WR_LDR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_LDR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_LDR_CASR_VER(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_VER(value)))
+#define CAU_BWR_LDR_CASR_VER(base, value) (CAU_WR_LDR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CAA - Accumulator register - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CAA - Accumulator register - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CAA register
+ */
+/*@{*/
+#define CAU_WR_LDR_CAA(base, value) (CAU_LDR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CA - General Purpose Register 0 - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CA register
+ */
+/*@{*/
+#define CAU_WR_LDR_CA(base, index, value) (CAU_LDR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CASR - Status register - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CASR - Status register - Store Register command (RO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CASR register
+ */
+/*@{*/
+#define CAU_RD_STR_CASR(base)    (CAU_STR_CASR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_STR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_STR_CASR, field IC[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_IC field. */
+#define CAU_RD_STR_CASR_IC(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_IC_MASK) >> CAU_STR_CASR_IC_SHIFT)
+#define CAU_BRD_STR_CASR_IC(base) (CAU_RD_STR_CASR_IC(base))
+/*@}*/
+
+/*!
+ * @name Register CAU_STR_CASR, field DPE[1] (RO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_DPE field. */
+#define CAU_RD_STR_CASR_DPE(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_DPE_MASK) >> CAU_STR_CASR_DPE_SHIFT)
+#define CAU_BRD_STR_CASR_DPE(base) (CAU_RD_STR_CASR_DPE(base))
+/*@}*/
+
+/*!
+ * @name Register CAU_STR_CASR, field VER[31:28] (RO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_VER field. */
+#define CAU_RD_STR_CASR_VER(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_VER_MASK) >> CAU_STR_CASR_VER_SHIFT)
+#define CAU_BRD_STR_CASR_VER(base) (CAU_RD_STR_CASR_VER(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CAA - Accumulator register - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CAA - Accumulator register - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CAA register
+ */
+/*@{*/
+#define CAU_RD_STR_CAA(base)     (CAU_STR_CAA_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CA - General Purpose Register 0 - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CA - General Purpose Register 0 - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CA register
+ */
+/*@{*/
+#define CAU_RD_STR_CA(base, index) (CAU_STR_CA_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CASR - Status register - Add Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CASR - Status register - Add Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CASR register
+ */
+/*@{*/
+#define CAU_WR_ADR_CASR(base, value) (CAU_ADR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_ADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_ADR_CASR_IC(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_IC(value)))
+#define CAU_BWR_ADR_CASR_IC(base, value) (CAU_WR_ADR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_ADR_CASR_DPE(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_DPE(value)))
+#define CAU_BWR_ADR_CASR_DPE(base, value) (CAU_WR_ADR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_ADR_CASR_VER(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_VER(value)))
+#define CAU_BWR_ADR_CASR_VER(base, value) (CAU_WR_ADR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CAA - Accumulator register - Add to register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CAA - Accumulator register - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CAA register
+ */
+/*@{*/
+#define CAU_WR_ADR_CAA(base, value) (CAU_ADR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CA - General Purpose Register 0 - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CA register
+ */
+/*@{*/
+#define CAU_WR_ADR_CA(base, index, value) (CAU_ADR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CASR - Status register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CASR register
+ */
+/*@{*/
+#define CAU_WR_RADR_CASR(base, value) (CAU_RADR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_RADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_RADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_RADR_CASR_IC(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_IC(value)))
+#define CAU_BWR_RADR_CASR_IC(base, value) (CAU_WR_RADR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_RADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_RADR_CASR_DPE(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_DPE(value)))
+#define CAU_BWR_RADR_CASR_DPE(base, value) (CAU_WR_RADR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_RADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_RADR_CASR_VER(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_VER(value)))
+#define CAU_BWR_RADR_CASR_VER(base, value) (CAU_WR_RADR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CAA register
+ */
+/*@{*/
+#define CAU_WR_RADR_CAA(base, value) (CAU_RADR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CA register
+ */
+/*@{*/
+#define CAU_WR_RADR_CA(base, index, value) (CAU_RADR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CASR - Status register - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CASR - Status register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CASR register
+ */
+/*@{*/
+#define CAU_WR_XOR_CASR(base, value) (CAU_XOR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_XOR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_XOR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_XOR_CASR_IC(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_IC(value)))
+#define CAU_BWR_XOR_CASR_IC(base, value) (CAU_WR_XOR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_XOR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_XOR_CASR_DPE(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_DPE(value)))
+#define CAU_BWR_XOR_CASR_DPE(base, value) (CAU_WR_XOR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_XOR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_XOR_CASR_VER(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_VER(value)))
+#define CAU_BWR_XOR_CASR_VER(base, value) (CAU_WR_XOR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CAA register
+ */
+/*@{*/
+#define CAU_WR_XOR_CAA(base, value) (CAU_XOR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CA register
+ */
+/*@{*/
+#define CAU_WR_XOR_CA(base, index, value) (CAU_XOR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CASR - Status register - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CASR - Status register - Rotate Left command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CASR register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CASR(base, value) (CAU_ROTL_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_ROTL_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ROTL_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_ROTL_CASR_IC(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_IC(value)))
+#define CAU_BWR_ROTL_CASR_IC(base, value) (CAU_WR_ROTL_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ROTL_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_ROTL_CASR_DPE(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_DPE(value)))
+#define CAU_BWR_ROTL_CASR_DPE(base, value) (CAU_WR_ROTL_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_ROTL_CASR_VER(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_VER(value)))
+#define CAU_BWR_ROTL_CASR_VER(base, value) (CAU_WR_ROTL_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CAA register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CAA(base, value) (CAU_ROTL_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CA register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CA(base, index, value) (CAU_ROTL_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CASR - Status register - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CASR - Status register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CASR register
+ */
+/*@{*/
+#define CAU_WR_AESC_CASR(base, value) (CAU_AESC_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_AESC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_AESC_CASR_IC(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_IC(value)))
+#define CAU_BWR_AESC_CASR_IC(base, value) (CAU_WR_AESC_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_AESC_CASR_DPE(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_DPE(value)))
+#define CAU_BWR_AESC_CASR_DPE(base, value) (CAU_WR_AESC_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_AESC_CASR_VER(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_VER(value)))
+#define CAU_BWR_AESC_CASR_VER(base, value) (CAU_WR_AESC_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CAA register
+ */
+/*@{*/
+#define CAU_WR_AESC_CAA(base, value) (CAU_AESC_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CA register
+ */
+/*@{*/
+#define CAU_WR_AESC_CA(base, index, value) (CAU_AESC_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CASR - Status register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CASR register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CASR(base, value) (CAU_AESIC_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_AESIC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESIC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_AESIC_CASR_IC(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_IC(value)))
+#define CAU_BWR_AESIC_CASR_IC(base, value) (CAU_WR_AESIC_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESIC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_AESIC_CASR_DPE(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_DPE(value)))
+#define CAU_BWR_AESIC_CASR_DPE(base, value) (CAU_WR_AESIC_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_AESIC_CASR_VER(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_VER(value)))
+#define CAU_BWR_AESIC_CASR_VER(base, value) (CAU_WR_AESIC_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CAA register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CAA(base, value) (CAU_AESIC_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CA register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CA(base, index, value) (CAU_AESIC_CA_REG(base, index) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CMP
+ *
+ * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
+ *
+ * Registers defined in this header file:
+ * - CMP_CR0 - CMP Control Register 0
+ * - CMP_CR1 - CMP Control Register 1
+ * - CMP_FPR - CMP Filter Period Register
+ * - CMP_SCR - CMP Status and Control Register
+ * - CMP_DACCR - DAC Control Register
+ * - CMP_MUXCR - MUX Control Register
+ */
+
+#define CMP_INSTANCE_COUNT (3U) /*!< Number of instances of the CMP module. */
+#define CMP0_IDX (0U) /*!< Instance number for CMP0. */
+#define CMP1_IDX (1U) /*!< Instance number for CMP1. */
+#define CMP2_IDX (2U) /*!< Instance number for CMP2. */
+
+/*******************************************************************************
+ * CMP_CR0 - CMP Control Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR0 - CMP Control Register 0 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR0 register
+ */
+/*@{*/
+#define CMP_RD_CR0(base)         (CMP_CR0_REG(base))
+#define CMP_WR_CR0(base, value)  (CMP_CR0_REG(base) = (value))
+#define CMP_RMW_CR0(base, mask, value) (CMP_WR_CR0(base, (CMP_RD_CR0(base) & ~(mask)) | (value)))
+#define CMP_SET_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) |  (value)))
+#define CMP_CLR_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) & ~(value)))
+#define CMP_TOG_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR0 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
+ *
+ * Defines the programmable hysteresis level. The hysteresis values associated
+ * with each level are device-specific. See the Data Sheet of the device for the
+ * exact values.
+ *
+ * Values:
+ * - 0b00 - Level 0
+ * - 0b01 - Level 1
+ * - 0b10 - Level 2
+ * - 0b11 - Level 3
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
+#define CMP_RD_CR0_HYSTCTR(base) ((CMP_CR0_REG(base) & CMP_CR0_HYSTCTR_MASK) >> CMP_CR0_HYSTCTR_SHIFT)
+#define CMP_BRD_CR0_HYSTCTR(base) (CMP_RD_CR0_HYSTCTR(base))
+
+/*! @brief Set the HYSTCTR field to a new value. */
+#define CMP_WR_CR0_HYSTCTR(base, value) (CMP_RMW_CR0(base, CMP_CR0_HYSTCTR_MASK, CMP_CR0_HYSTCTR(value)))
+#define CMP_BWR_CR0_HYSTCTR(base, value) (CMP_WR_CR0_HYSTCTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
+ *
+ * Represents the number of consecutive samples that must agree prior to the
+ * comparator ouput filter accepting a new output state. For information regarding
+ * filter programming and latency, see the Functional descriptionThe CMP module
+ * can be used to compare two analog input voltages applied to INP and INM. .
+ *
+ * Values:
+ * - 0b000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not
+ *     a legal state, and is not recommended. If SE = 0, COUT = COUTA.
+ * - 0b001 - One sample must agree. The comparator output is simply sampled.
+ * - 0b010 - 2 consecutive samples must agree.
+ * - 0b011 - 3 consecutive samples must agree.
+ * - 0b100 - 4 consecutive samples must agree.
+ * - 0b101 - 5 consecutive samples must agree.
+ * - 0b110 - 6 consecutive samples must agree.
+ * - 0b111 - 7 consecutive samples must agree.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
+#define CMP_RD_CR0_FILTER_CNT(base) ((CMP_CR0_REG(base) & CMP_CR0_FILTER_CNT_MASK) >> CMP_CR0_FILTER_CNT_SHIFT)
+#define CMP_BRD_CR0_FILTER_CNT(base) (CMP_RD_CR0_FILTER_CNT(base))
+
+/*! @brief Set the FILTER_CNT field to a new value. */
+#define CMP_WR_CR0_FILTER_CNT(base, value) (CMP_RMW_CR0(base, CMP_CR0_FILTER_CNT_MASK, CMP_CR0_FILTER_CNT(value)))
+#define CMP_BWR_CR0_FILTER_CNT(base, value) (CMP_WR_CR0_FILTER_CNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_CR1 - CMP Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR1 - CMP Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR1 register
+ */
+/*@{*/
+#define CMP_RD_CR1(base)         (CMP_CR1_REG(base))
+#define CMP_WR_CR1(base, value)  (CMP_CR1_REG(base) = (value))
+#define CMP_RMW_CR1(base, mask, value) (CMP_WR_CR1(base, (CMP_RD_CR1(base) & ~(mask)) | (value)))
+#define CMP_SET_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) |  (value)))
+#define CMP_CLR_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) & ~(value)))
+#define CMP_TOG_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR1 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR1, field EN[0] (RW)
+ *
+ * Enables the Analog Comparator module. When the module is not enabled, it
+ * remains in the off state, and consumes no power. When the user selects the same
+ * input from analog mux to the positive and negative port, the comparator is
+ * disabled automatically.
+ *
+ * Values:
+ * - 0b0 - Analog Comparator is disabled.
+ * - 0b1 - Analog Comparator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_EN field. */
+#define CMP_RD_CR1_EN(base)  ((CMP_CR1_REG(base) & CMP_CR1_EN_MASK) >> CMP_CR1_EN_SHIFT)
+#define CMP_BRD_CR1_EN(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT))
+
+/*! @brief Set the EN field to a new value. */
+#define CMP_WR_CR1_EN(base, value) (CMP_RMW_CR1(base, CMP_CR1_EN_MASK, CMP_CR1_EN(value)))
+#define CMP_BWR_CR1_EN(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field OPE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - CMPO is not available on the associated CMPO output pin. If the
+ *     comparator does not own the pin, this field has no effect.
+ * - 0b1 - CMPO is available on the associated CMPO output pin. The comparator
+ *     output (CMPO) is driven out on the associated CMPO output pin if the
+ *     comparator owns the pin. If the comparator does not own the field, this bit has
+ *     no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_OPE field. */
+#define CMP_RD_CR1_OPE(base) ((CMP_CR1_REG(base) & CMP_CR1_OPE_MASK) >> CMP_CR1_OPE_SHIFT)
+#define CMP_BRD_CR1_OPE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT))
+
+/*! @brief Set the OPE field to a new value. */
+#define CMP_WR_CR1_OPE(base, value) (CMP_RMW_CR1(base, CMP_CR1_OPE_MASK, CMP_CR1_OPE(value)))
+#define CMP_BWR_CR1_OPE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field COS[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Set the filtered comparator output (CMPO) to equal COUT.
+ * - 0b1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_COS field. */
+#define CMP_RD_CR1_COS(base) ((CMP_CR1_REG(base) & CMP_CR1_COS_MASK) >> CMP_CR1_COS_SHIFT)
+#define CMP_BRD_CR1_COS(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT))
+
+/*! @brief Set the COS field to a new value. */
+#define CMP_WR_CR1_COS(base, value) (CMP_RMW_CR1(base, CMP_CR1_COS_MASK, CMP_CR1_COS(value)))
+#define CMP_BWR_CR1_COS(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field INV[3] (RW)
+ *
+ * Allows selection of the polarity of the analog comparator function. It is
+ * also driven to the COUT output, on both the device pin and as SCR[COUT], when
+ * OPE=0.
+ *
+ * Values:
+ * - 0b0 - Does not invert the comparator output.
+ * - 0b1 - Inverts the comparator output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_INV field. */
+#define CMP_RD_CR1_INV(base) ((CMP_CR1_REG(base) & CMP_CR1_INV_MASK) >> CMP_CR1_INV_SHIFT)
+#define CMP_BRD_CR1_INV(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT))
+
+/*! @brief Set the INV field to a new value. */
+#define CMP_WR_CR1_INV(base, value) (CMP_RMW_CR1(base, CMP_CR1_INV_MASK, CMP_CR1_INV(value)))
+#define CMP_BWR_CR1_INV(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field PMODE[4] (RW)
+ *
+ * See the electrical specifications table in the device Data Sheet for details.
+ *
+ * Values:
+ * - 0b0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
+ *     output propagation delay and lower current consumption.
+ * - 0b1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has
+ *     faster output propagation delay and higher current consumption.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_PMODE field. */
+#define CMP_RD_CR1_PMODE(base) ((CMP_CR1_REG(base) & CMP_CR1_PMODE_MASK) >> CMP_CR1_PMODE_SHIFT)
+#define CMP_BRD_CR1_PMODE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT))
+
+/*! @brief Set the PMODE field to a new value. */
+#define CMP_WR_CR1_PMODE(base, value) (CMP_RMW_CR1(base, CMP_CR1_PMODE_MASK, CMP_CR1_PMODE(value)))
+#define CMP_BWR_CR1_PMODE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field WE[6] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0b0 - Windowing mode is not selected.
+ * - 0b1 - Windowing mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_WE field. */
+#define CMP_RD_CR1_WE(base)  ((CMP_CR1_REG(base) & CMP_CR1_WE_MASK) >> CMP_CR1_WE_SHIFT)
+#define CMP_BRD_CR1_WE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT))
+
+/*! @brief Set the WE field to a new value. */
+#define CMP_WR_CR1_WE(base, value) (CMP_RMW_CR1(base, CMP_CR1_WE_MASK, CMP_CR1_WE(value)))
+#define CMP_BWR_CR1_WE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field SE[7] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0b0 - Sampling mode is not selected.
+ * - 0b1 - Sampling mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_SE field. */
+#define CMP_RD_CR1_SE(base)  ((CMP_CR1_REG(base) & CMP_CR1_SE_MASK) >> CMP_CR1_SE_SHIFT)
+#define CMP_BRD_CR1_SE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT))
+
+/*! @brief Set the SE field to a new value. */
+#define CMP_WR_CR1_SE(base, value) (CMP_RMW_CR1(base, CMP_CR1_SE_MASK, CMP_CR1_SE(value)))
+#define CMP_BWR_CR1_SE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_FPR - CMP Filter Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_FPR - CMP Filter Period Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_FPR register
+ */
+/*@{*/
+#define CMP_RD_FPR(base)         (CMP_FPR_REG(base))
+#define CMP_WR_FPR(base, value)  (CMP_FPR_REG(base) = (value))
+#define CMP_RMW_FPR(base, mask, value) (CMP_WR_FPR(base, (CMP_RD_FPR(base) & ~(mask)) | (value)))
+#define CMP_SET_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) |  (value)))
+#define CMP_CLR_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) & ~(value)))
+#define CMP_TOG_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_SCR - CMP Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_SCR - CMP Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_SCR register
+ */
+/*@{*/
+#define CMP_RD_SCR(base)         (CMP_SCR_REG(base))
+#define CMP_WR_SCR(base, value)  (CMP_SCR_REG(base) = (value))
+#define CMP_RMW_SCR(base, mask, value) (CMP_WR_SCR(base, (CMP_RD_SCR(base) & ~(mask)) | (value)))
+#define CMP_SET_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) |  (value)))
+#define CMP_CLR_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) & ~(value)))
+#define CMP_TOG_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_SCR bitfields
+ */
+
+/*!
+ * @name Register CMP_SCR, field COUT[0] (RO)
+ *
+ * Returns the current value of the Analog Comparator output, when read. The
+ * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
+ * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_COUT field. */
+#define CMP_RD_SCR_COUT(base) ((CMP_SCR_REG(base) & CMP_SCR_COUT_MASK) >> CMP_SCR_COUT_SHIFT)
+#define CMP_BRD_SCR_COUT(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_COUT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFF[1] (W1C)
+ *
+ * Detects a falling-edge on COUT, when set, during normal operation. CFF is
+ * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0b0 - Falling-edge on COUT has not been detected.
+ * - 0b1 - Falling-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFF field. */
+#define CMP_RD_SCR_CFF(base) ((CMP_SCR_REG(base) & CMP_SCR_CFF_MASK) >> CMP_SCR_CFF_SHIFT)
+#define CMP_BRD_SCR_CFF(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT))
+
+/*! @brief Set the CFF field to a new value. */
+#define CMP_WR_SCR_CFF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_CFF(value)))
+#define CMP_BWR_SCR_CFF(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFR[2] (W1C)
+ *
+ * Detects a rising-edge on COUT, when set, during normal operation. CFR is
+ * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0b0 - Rising-edge on COUT has not been detected.
+ * - 0b1 - Rising-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFR field. */
+#define CMP_RD_SCR_CFR(base) ((CMP_SCR_REG(base) & CMP_SCR_CFR_MASK) >> CMP_SCR_CFR_SHIFT)
+#define CMP_BRD_SCR_CFR(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT))
+
+/*! @brief Set the CFR field to a new value. */
+#define CMP_WR_SCR_CFR(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK), CMP_SCR_CFR(value)))
+#define CMP_BWR_SCR_CFR(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IEF[3] (RW)
+ *
+ * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFF is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled.
+ * - 0b1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IEF field. */
+#define CMP_RD_SCR_IEF(base) ((CMP_SCR_REG(base) & CMP_SCR_IEF_MASK) >> CMP_SCR_IEF_SHIFT)
+#define CMP_BRD_SCR_IEF(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT))
+
+/*! @brief Set the IEF field to a new value. */
+#define CMP_WR_SCR_IEF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IEF_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IEF(value)))
+#define CMP_BWR_SCR_IEF(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IER[4] (RW)
+ *
+ * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFR is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled.
+ * - 0b1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IER field. */
+#define CMP_RD_SCR_IER(base) ((CMP_SCR_REG(base) & CMP_SCR_IER_MASK) >> CMP_SCR_IER_SHIFT)
+#define CMP_BRD_SCR_IER(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT))
+
+/*! @brief Set the IER field to a new value. */
+#define CMP_WR_SCR_IER(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IER_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IER(value)))
+#define CMP_BWR_SCR_IER(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field DMAEN[6] (RW)
+ *
+ * Enables the DMA transfer triggered from the CMP module. When this field is
+ * set, a DMA request is asserted when CFR or CFF is set.
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_DMAEN field. */
+#define CMP_RD_SCR_DMAEN(base) ((CMP_SCR_REG(base) & CMP_SCR_DMAEN_MASK) >> CMP_SCR_DMAEN_SHIFT)
+#define CMP_BRD_SCR_DMAEN(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define CMP_WR_SCR_DMAEN(base, value) (CMP_RMW_SCR(base, (CMP_SCR_DMAEN_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_DMAEN(value)))
+#define CMP_BWR_SCR_DMAEN(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_DACCR - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_DACCR - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_DACCR register
+ */
+/*@{*/
+#define CMP_RD_DACCR(base)       (CMP_DACCR_REG(base))
+#define CMP_WR_DACCR(base, value) (CMP_DACCR_REG(base) = (value))
+#define CMP_RMW_DACCR(base, mask, value) (CMP_WR_DACCR(base, (CMP_RD_DACCR(base) & ~(mask)) | (value)))
+#define CMP_SET_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) |  (value)))
+#define CMP_CLR_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) & ~(value)))
+#define CMP_TOG_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_DACCR bitfields
+ */
+
+/*!
+ * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
+ *
+ * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
+ * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VOSEL field. */
+#define CMP_RD_DACCR_VOSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VOSEL_MASK) >> CMP_DACCR_VOSEL_SHIFT)
+#define CMP_BRD_DACCR_VOSEL(base) (CMP_RD_DACCR_VOSEL(base))
+
+/*! @brief Set the VOSEL field to a new value. */
+#define CMP_WR_DACCR_VOSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VOSEL_MASK, CMP_DACCR_VOSEL(value)))
+#define CMP_BWR_DACCR_VOSEL(base, value) (CMP_WR_DACCR_VOSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field VRSEL[6] (RW)
+ *
+ * Values:
+ * - 0b0 - V is selected as resistor ladder network supply reference V. in1 in
+ * - 0b1 - V is selected as resistor ladder network supply reference V. in2 in
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VRSEL field. */
+#define CMP_RD_DACCR_VRSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VRSEL_MASK) >> CMP_DACCR_VRSEL_SHIFT)
+#define CMP_BRD_DACCR_VRSEL(base) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT))
+
+/*! @brief Set the VRSEL field to a new value. */
+#define CMP_WR_DACCR_VRSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VRSEL_MASK, CMP_DACCR_VRSEL(value)))
+#define CMP_BWR_DACCR_VRSEL(base, value) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field DACEN[7] (RW)
+ *
+ * Enables the DAC. When the DAC is disabled, it is powered down to conserve
+ * power.
+ *
+ * Values:
+ * - 0b0 - DAC is disabled.
+ * - 0b1 - DAC is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_DACEN field. */
+#define CMP_RD_DACCR_DACEN(base) ((CMP_DACCR_REG(base) & CMP_DACCR_DACEN_MASK) >> CMP_DACCR_DACEN_SHIFT)
+#define CMP_BRD_DACCR_DACEN(base) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT))
+
+/*! @brief Set the DACEN field to a new value. */
+#define CMP_WR_DACCR_DACEN(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_DACEN_MASK, CMP_DACCR_DACEN(value)))
+#define CMP_BWR_DACCR_DACEN(base, value) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_MUXCR - MUX Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_MUXCR - MUX Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_MUXCR register
+ */
+/*@{*/
+#define CMP_RD_MUXCR(base)       (CMP_MUXCR_REG(base))
+#define CMP_WR_MUXCR(base, value) (CMP_MUXCR_REG(base) = (value))
+#define CMP_RMW_MUXCR(base, mask, value) (CMP_WR_MUXCR(base, (CMP_RD_MUXCR(base) & ~(mask)) | (value)))
+#define CMP_SET_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) |  (value)))
+#define CMP_CLR_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) & ~(value)))
+#define CMP_TOG_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_MUXCR bitfields
+ */
+
+/*!
+ * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
+ *
+ * Determines which input is selected for the minus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 0b000 - IN0
+ * - 0b001 - IN1
+ * - 0b010 - IN2
+ * - 0b011 - IN3
+ * - 0b100 - IN4
+ * - 0b101 - IN5
+ * - 0b110 - IN6
+ * - 0b111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_MSEL field. */
+#define CMP_RD_MUXCR_MSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_MSEL_MASK) >> CMP_MUXCR_MSEL_SHIFT)
+#define CMP_BRD_MUXCR_MSEL(base) (CMP_RD_MUXCR_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define CMP_WR_MUXCR_MSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_MSEL_MASK, CMP_MUXCR_MSEL(value)))
+#define CMP_BWR_MUXCR_MSEL(base, value) (CMP_WR_MUXCR_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
+ *
+ * Determines which input is selected for the plus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 0b000 - IN0
+ * - 0b001 - IN1
+ * - 0b010 - IN2
+ * - 0b011 - IN3
+ * - 0b100 - IN4
+ * - 0b101 - IN5
+ * - 0b110 - IN6
+ * - 0b111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSEL field. */
+#define CMP_RD_MUXCR_PSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSEL_MASK) >> CMP_MUXCR_PSEL_SHIFT)
+#define CMP_BRD_MUXCR_PSEL(base) (CMP_RD_MUXCR_PSEL(base))
+
+/*! @brief Set the PSEL field to a new value. */
+#define CMP_WR_MUXCR_PSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSEL_MASK, CMP_MUXCR_PSEL(value)))
+#define CMP_BWR_MUXCR_PSEL(base, value) (CMP_WR_MUXCR_PSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSTM[7] (RW)
+ *
+ * This bit is used to enable to MUX pass through mode. Pass through mode is
+ * always available but for some devices this feature must be always disabled due to
+ * the lack of package pins.
+ *
+ * Values:
+ * - 0b0 - Pass Through Mode is disabled.
+ * - 0b1 - Pass Through Mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSTM field. */
+#define CMP_RD_MUXCR_PSTM(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSTM_MASK) >> CMP_MUXCR_PSTM_SHIFT)
+#define CMP_BRD_MUXCR_PSTM(base) (BITBAND_ACCESS8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT))
+
+/*! @brief Set the PSTM field to a new value. */
+#define CMP_WR_MUXCR_PSTM(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSTM_MASK, CMP_MUXCR_PSTM(value)))
+#define CMP_BWR_MUXCR_PSTM(base, value) (BITBAND_ACCESS8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CMT
+ *
+ * Carrier Modulator Transmitter
+ *
+ * Registers defined in this header file:
+ * - CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ * - CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ * - CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ * - CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ * - CMT_OC - CMT Output Control Register
+ * - CMT_MSC - CMT Modulator Status and Control Register
+ * - CMT_CMD1 - CMT Modulator Data Register Mark High
+ * - CMT_CMD2 - CMT Modulator Data Register Mark Low
+ * - CMT_CMD3 - CMT Modulator Data Register Space High
+ * - CMT_CMD4 - CMT Modulator Data Register Space Low
+ * - CMT_PPS - CMT Primary Prescaler Register
+ * - CMT_DMA - CMT Direct Memory Access Register
+ */
+
+#define CMT_INSTANCE_COUNT (1U) /*!< Number of instances of the CMT module. */
+#define CMT_IDX (0U) /*!< Instance number for CMT. */
+
+/*******************************************************************************
+ * CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary high value for generating the carrier
+ * output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGH1 register
+ */
+/*@{*/
+#define CMT_RD_CGH1(base)        (CMT_CGH1_REG(base))
+#define CMT_WR_CGH1(base, value) (CMT_CGH1_REG(base) = (value))
+#define CMT_RMW_CGH1(base, mask, value) (CMT_WR_CGH1(base, (CMT_RD_CGH1(base) & ~(mask)) | (value)))
+#define CMT_SET_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) |  (value)))
+#define CMT_CLR_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) & ~(value)))
+#define CMT_TOG_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary low value for generating the carrier
+ * output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGL1 register
+ */
+/*@{*/
+#define CMT_RD_CGL1(base)        (CMT_CGL1_REG(base))
+#define CMT_WR_CGL1(base, value) (CMT_CGL1_REG(base) = (value))
+#define CMT_RMW_CGL1(base, mask, value) (CMT_WR_CGL1(base, (CMT_RD_CGL1(base) & ~(mask)) | (value)))
+#define CMT_SET_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) |  (value)))
+#define CMT_CLR_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) & ~(value)))
+#define CMT_TOG_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary high value for generating the
+ * carrier output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGH2 register
+ */
+/*@{*/
+#define CMT_RD_CGH2(base)        (CMT_CGH2_REG(base))
+#define CMT_WR_CGH2(base, value) (CMT_CGH2_REG(base) = (value))
+#define CMT_RMW_CGH2(base, mask, value) (CMT_WR_CGH2(base, (CMT_RD_CGH2(base) & ~(mask)) | (value)))
+#define CMT_SET_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) |  (value)))
+#define CMT_CLR_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) & ~(value)))
+#define CMT_TOG_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary low value for generating the
+ * carrier output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGL2 register
+ */
+/*@{*/
+#define CMT_RD_CGL2(base)        (CMT_CGL2_REG(base))
+#define CMT_WR_CGL2(base, value) (CMT_CGL2_REG(base) = (value))
+#define CMT_RMW_CGL2(base, mask, value) (CMT_WR_CGL2(base, (CMT_RD_CGL2(base) & ~(mask)) | (value)))
+#define CMT_SET_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) |  (value)))
+#define CMT_CLR_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) & ~(value)))
+#define CMT_TOG_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_OC - CMT Output Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_OC - CMT Output Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to control the IRO signal of the CMT module.
+ */
+/*!
+ * @name Constants and macros for entire CMT_OC register
+ */
+/*@{*/
+#define CMT_RD_OC(base)          (CMT_OC_REG(base))
+#define CMT_WR_OC(base, value)   (CMT_OC_REG(base) = (value))
+#define CMT_RMW_OC(base, mask, value) (CMT_WR_OC(base, (CMT_RD_OC(base) & ~(mask)) | (value)))
+#define CMT_SET_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) |  (value)))
+#define CMT_CLR_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) & ~(value)))
+#define CMT_TOG_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_OC bitfields
+ */
+
+/*!
+ * @name Register CMT_OC, field IROPEN[5] (RW)
+ *
+ * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
+ * output that drives out either the CMT transmitter output or the state of IROL
+ * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
+ * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
+ * signal is disabled, it is in a high-impedance state and is unable to draw any
+ * current. This signal is disabled during reset.
+ *
+ * Values:
+ * - 0b0 - The IRO signal is disabled.
+ * - 0b1 - The IRO signal is enabled as output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_IROPEN field. */
+#define CMT_RD_OC_IROPEN(base) ((CMT_OC_REG(base) & CMT_OC_IROPEN_MASK) >> CMT_OC_IROPEN_SHIFT)
+#define CMT_BRD_OC_IROPEN(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT))
+
+/*! @brief Set the IROPEN field to a new value. */
+#define CMT_WR_OC_IROPEN(base, value) (CMT_RMW_OC(base, CMT_OC_IROPEN_MASK, CMT_OC_IROPEN(value)))
+#define CMT_BWR_OC_IROPEN(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_OC, field CMTPOL[6] (RW)
+ *
+ * Controls the polarity of the IRO signal.
+ *
+ * Values:
+ * - 0b0 - The IRO signal is active-low.
+ * - 0b1 - The IRO signal is active-high.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_CMTPOL field. */
+#define CMT_RD_OC_CMTPOL(base) ((CMT_OC_REG(base) & CMT_OC_CMTPOL_MASK) >> CMT_OC_CMTPOL_SHIFT)
+#define CMT_BRD_OC_CMTPOL(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT))
+
+/*! @brief Set the CMTPOL field to a new value. */
+#define CMT_WR_OC_CMTPOL(base, value) (CMT_RMW_OC(base, CMT_OC_CMTPOL_MASK, CMT_OC_CMTPOL(value)))
+#define CMT_BWR_OC_CMTPOL(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_OC, field IROL[7] (RW)
+ *
+ * Reads the state of the IRO latch. Writing to IROL changes the state of the
+ * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_IROL field. */
+#define CMT_RD_OC_IROL(base) ((CMT_OC_REG(base) & CMT_OC_IROL_MASK) >> CMT_OC_IROL_SHIFT)
+#define CMT_BRD_OC_IROL(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT))
+
+/*! @brief Set the IROL field to a new value. */
+#define CMT_WR_OC_IROL(base, value) (CMT_RMW_OC(base, CMT_OC_IROL_MASK, CMT_OC_IROL(value)))
+#define CMT_BWR_OC_IROL(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_MSC - CMT Modulator Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_MSC - CMT Modulator Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the modulator and carrier generator enable (MCGEN),
+ * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
+ * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
+ * (EOCF) status bit.
+ */
+/*!
+ * @name Constants and macros for entire CMT_MSC register
+ */
+/*@{*/
+#define CMT_RD_MSC(base)         (CMT_MSC_REG(base))
+#define CMT_WR_MSC(base, value)  (CMT_MSC_REG(base) = (value))
+#define CMT_RMW_MSC(base, mask, value) (CMT_WR_MSC(base, (CMT_RD_MSC(base) & ~(mask)) | (value)))
+#define CMT_SET_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) |  (value)))
+#define CMT_CLR_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) & ~(value)))
+#define CMT_TOG_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_MSC bitfields
+ */
+
+/*!
+ * @name Register CMT_MSC, field MCGEN[0] (RW)
+ *
+ * Setting MCGEN will initialize the carrier generator and modulator and will
+ * enable all clocks. When enabled, the carrier generator and modulator will
+ * function continuously. When MCGEN is cleared, the current modulator cycle will be
+ * allowed to expire before all carrier and modulator clocks are disabled to save
+ * power and the modulator output is forced low. To prevent spurious operation,
+ * the user should initialize all data and control registers before enabling the
+ * system.
+ *
+ * Values:
+ * - 0b0 - Modulator and carrier generator disabled
+ * - 0b1 - Modulator and carrier generator enabled
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_MCGEN field. */
+#define CMT_RD_MSC_MCGEN(base) ((CMT_MSC_REG(base) & CMT_MSC_MCGEN_MASK) >> CMT_MSC_MCGEN_SHIFT)
+#define CMT_BRD_MSC_MCGEN(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT))
+
+/*! @brief Set the MCGEN field to a new value. */
+#define CMT_WR_MSC_MCGEN(base, value) (CMT_RMW_MSC(base, CMT_MSC_MCGEN_MASK, CMT_MSC_MCGEN(value)))
+#define CMT_BWR_MSC_MCGEN(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EOCIE[1] (RW)
+ *
+ * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
+ *
+ * Values:
+ * - 0b0 - CPU interrupt is disabled.
+ * - 0b1 - CPU interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EOCIE field. */
+#define CMT_RD_MSC_EOCIE(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCIE_MASK) >> CMT_MSC_EOCIE_SHIFT)
+#define CMT_BRD_MSC_EOCIE(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT))
+
+/*! @brief Set the EOCIE field to a new value. */
+#define CMT_WR_MSC_EOCIE(base, value) (CMT_RMW_MSC(base, CMT_MSC_EOCIE_MASK, CMT_MSC_EOCIE(value)))
+#define CMT_BWR_MSC_EOCIE(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field FSK[2] (RW)
+ *
+ * Enables FSK operation.
+ *
+ * Values:
+ * - 0b0 - The CMT operates in Time or Baseband mode.
+ * - 0b1 - The CMT operates in FSK mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_FSK field. */
+#define CMT_RD_MSC_FSK(base) ((CMT_MSC_REG(base) & CMT_MSC_FSK_MASK) >> CMT_MSC_FSK_SHIFT)
+#define CMT_BRD_MSC_FSK(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT))
+
+/*! @brief Set the FSK field to a new value. */
+#define CMT_WR_MSC_FSK(base, value) (CMT_RMW_MSC(base, CMT_MSC_FSK_MASK, CMT_MSC_FSK(value)))
+#define CMT_BWR_MSC_FSK(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field BASE[3] (RW)
+ *
+ * When set, BASE disables the carrier generator and forces the carrier output
+ * high for generation of baseband protocols. When BASE is cleared, the carrier
+ * generator is enabled and the carrier output toggles at the frequency determined
+ * by values stored in the carrier data registers. This field is cleared by
+ * reset. This field is not double-buffered and must not be written to during a
+ * transmission.
+ *
+ * Values:
+ * - 0b0 - Baseband mode is disabled.
+ * - 0b1 - Baseband mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_BASE field. */
+#define CMT_RD_MSC_BASE(base) ((CMT_MSC_REG(base) & CMT_MSC_BASE_MASK) >> CMT_MSC_BASE_SHIFT)
+#define CMT_BRD_MSC_BASE(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT))
+
+/*! @brief Set the BASE field to a new value. */
+#define CMT_WR_MSC_BASE(base, value) (CMT_RMW_MSC(base, CMT_MSC_BASE_MASK, CMT_MSC_BASE(value)))
+#define CMT_BWR_MSC_BASE(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EXSPC[4] (RW)
+ *
+ * Enables the extended space operation.
+ *
+ * Values:
+ * - 0b0 - Extended space is disabled.
+ * - 0b1 - Extended space is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EXSPC field. */
+#define CMT_RD_MSC_EXSPC(base) ((CMT_MSC_REG(base) & CMT_MSC_EXSPC_MASK) >> CMT_MSC_EXSPC_SHIFT)
+#define CMT_BRD_MSC_EXSPC(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT))
+
+/*! @brief Set the EXSPC field to a new value. */
+#define CMT_WR_MSC_EXSPC(base, value) (CMT_RMW_MSC(base, CMT_MSC_EXSPC_MASK, CMT_MSC_EXSPC(value)))
+#define CMT_BWR_MSC_EXSPC(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
+ *
+ * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
+ * divided by 2 ,4, or 8 . This field must not be changed during a transmission
+ * because it is not double-buffered.
+ *
+ * Values:
+ * - 0b00 - IF * 1
+ * - 0b01 - IF * 2
+ * - 0b10 - IF * 4
+ * - 0b11 - IF * 8
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_CMTDIV field. */
+#define CMT_RD_MSC_CMTDIV(base) ((CMT_MSC_REG(base) & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT)
+#define CMT_BRD_MSC_CMTDIV(base) (CMT_RD_MSC_CMTDIV(base))
+
+/*! @brief Set the CMTDIV field to a new value. */
+#define CMT_WR_MSC_CMTDIV(base, value) (CMT_RMW_MSC(base, CMT_MSC_CMTDIV_MASK, CMT_MSC_CMTDIV(value)))
+#define CMT_BWR_MSC_CMTDIV(base, value) (CMT_WR_MSC_CMTDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EOCF[7] (RO)
+ *
+ * Sets when: The modulator is not currently active and MCGEN is set to begin
+ * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
+ * set. This is recognized when a match occurs between the contents of the space
+ * period register and the down counter. At this time, the counter is
+ * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
+ * the space period register is loaded with, possibly new contents of the space
+ * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
+ * access of CMD2 or CMD4, or by the DMA transfer.
+ *
+ * Values:
+ * - 0b0 - End of modulation cycle has not occured since the flag last cleared.
+ * - 0b1 - End of modulator cycle has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EOCF field. */
+#define CMT_RD_MSC_EOCF(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCF_MASK) >> CMT_MSC_EOCF_SHIFT)
+#define CMT_BRD_MSC_EOCF(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD1 - CMT Modulator Data Register Mark High
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD1 register
+ */
+/*@{*/
+#define CMT_RD_CMD1(base)        (CMT_CMD1_REG(base))
+#define CMT_WR_CMD1(base, value) (CMT_CMD1_REG(base) = (value))
+#define CMT_RMW_CMD1(base, mask, value) (CMT_WR_CMD1(base, (CMT_RD_CMD1(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) |  (value)))
+#define CMT_CLR_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) & ~(value)))
+#define CMT_TOG_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD2 - CMT Modulator Data Register Mark Low
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD2 register
+ */
+/*@{*/
+#define CMT_RD_CMD2(base)        (CMT_CMD2_REG(base))
+#define CMT_WR_CMD2(base, value) (CMT_CMD2_REG(base) = (value))
+#define CMT_RMW_CMD2(base, mask, value) (CMT_WR_CMD2(base, (CMT_RD_CMD2(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) |  (value)))
+#define CMT_CLR_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) & ~(value)))
+#define CMT_TOG_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD3 - CMT Modulator Data Register Space High
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD3 - CMT Modulator Data Register Space High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD3 register
+ */
+/*@{*/
+#define CMT_RD_CMD3(base)        (CMT_CMD3_REG(base))
+#define CMT_WR_CMD3(base, value) (CMT_CMD3_REG(base) = (value))
+#define CMT_RMW_CMD3(base, mask, value) (CMT_WR_CMD3(base, (CMT_RD_CMD3(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) |  (value)))
+#define CMT_CLR_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) & ~(value)))
+#define CMT_TOG_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD4 - CMT Modulator Data Register Space Low
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD4 register
+ */
+/*@{*/
+#define CMT_RD_CMD4(base)        (CMT_CMD4_REG(base))
+#define CMT_WR_CMD4(base, value) (CMT_CMD4_REG(base) = (value))
+#define CMT_RMW_CMD4(base, mask, value) (CMT_WR_CMD4(base, (CMT_RD_CMD4(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) |  (value)))
+#define CMT_CLR_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) & ~(value)))
+#define CMT_TOG_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_PPS - CMT Primary Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_PPS - CMT Primary Prescaler Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to set the Primary Prescaler Divider field (PPSDIV).
+ */
+/*!
+ * @name Constants and macros for entire CMT_PPS register
+ */
+/*@{*/
+#define CMT_RD_PPS(base)         (CMT_PPS_REG(base))
+#define CMT_WR_PPS(base, value)  (CMT_PPS_REG(base) = (value))
+#define CMT_RMW_PPS(base, mask, value) (CMT_WR_PPS(base, (CMT_RD_PPS(base) & ~(mask)) | (value)))
+#define CMT_SET_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) |  (value)))
+#define CMT_CLR_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) & ~(value)))
+#define CMT_TOG_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_PPS bitfields
+ */
+
+/*!
+ * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
+ *
+ * Divides the CMT clock to generate the Intermediate Frequency clock enable to
+ * the secondary prescaler.
+ *
+ * Values:
+ * - 0b0000 - Bus clock * 1
+ * - 0b0001 - Bus clock * 2
+ * - 0b0010 - Bus clock * 3
+ * - 0b0011 - Bus clock * 4
+ * - 0b0100 - Bus clock * 5
+ * - 0b0101 - Bus clock * 6
+ * - 0b0110 - Bus clock * 7
+ * - 0b0111 - Bus clock * 8
+ * - 0b1000 - Bus clock * 9
+ * - 0b1001 - Bus clock * 10
+ * - 0b1010 - Bus clock * 11
+ * - 0b1011 - Bus clock * 12
+ * - 0b1100 - Bus clock * 13
+ * - 0b1101 - Bus clock * 14
+ * - 0b1110 - Bus clock * 15
+ * - 0b1111 - Bus clock * 16
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_PPS_PPSDIV field. */
+#define CMT_RD_PPS_PPSDIV(base) ((CMT_PPS_REG(base) & CMT_PPS_PPSDIV_MASK) >> CMT_PPS_PPSDIV_SHIFT)
+#define CMT_BRD_PPS_PPSDIV(base) (CMT_RD_PPS_PPSDIV(base))
+
+/*! @brief Set the PPSDIV field to a new value. */
+#define CMT_WR_PPS_PPSDIV(base, value) (CMT_RMW_PPS(base, CMT_PPS_PPSDIV_MASK, CMT_PPS_PPSDIV(value)))
+#define CMT_BWR_PPS_PPSDIV(base, value) (CMT_WR_PPS_PPSDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_DMA - CMT Direct Memory Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_DMA - CMT Direct Memory Access Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to enable/disable direct memory access (DMA).
+ */
+/*!
+ * @name Constants and macros for entire CMT_DMA register
+ */
+/*@{*/
+#define CMT_RD_DMA(base)         (CMT_DMA_REG(base))
+#define CMT_WR_DMA(base, value)  (CMT_DMA_REG(base) = (value))
+#define CMT_RMW_DMA(base, mask, value) (CMT_WR_DMA(base, (CMT_RD_DMA(base) & ~(mask)) | (value)))
+#define CMT_SET_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) |  (value)))
+#define CMT_CLR_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) & ~(value)))
+#define CMT_TOG_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_DMA bitfields
+ */
+
+/*!
+ * @name Register CMT_DMA, field DMA[0] (RW)
+ *
+ * Enables the DMA protocol.
+ *
+ * Values:
+ * - 0b0 - DMA transfer request and done are disabled.
+ * - 0b1 - DMA transfer request and done are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_DMA_DMA field. */
+#define CMT_RD_DMA_DMA(base) ((CMT_DMA_REG(base) & CMT_DMA_DMA_MASK) >> CMT_DMA_DMA_SHIFT)
+#define CMT_BRD_DMA_DMA(base) (BITBAND_ACCESS8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define CMT_WR_DMA_DMA(base, value) (CMT_RMW_DMA(base, CMT_DMA_DMA_MASK, CMT_DMA_DMA(value)))
+#define CMT_BWR_DMA_DMA(base, value) (BITBAND_ACCESS8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CRC
+ *
+ * Cyclic Redundancy Check
+ *
+ * Registers defined in this header file:
+ * - CRC_DATAL - CRC_DATAL register.
+ * - CRC_DATAH - CRC_DATAH register.
+ * - CRC_DATALL - CRC_DATALL register.
+ * - CRC_DATALU - CRC_DATALU register.
+ * - CRC_DATAHL - CRC_DATAHL register.
+ * - CRC_DATAHU - CRC_DATAHU register.
+ * - CRC_DATA - CRC Data register
+ * - CRC_GPOLY - CRC Polynomial register
+ * - CRC_GPOLYL - CRC_GPOLYL register.
+ * - CRC_GPOLYH - CRC_GPOLYH register.
+ * - CRC_GPOLYLL - CRC_GPOLYLL register.
+ * - CRC_GPOLYLU - CRC_GPOLYLU register.
+ * - CRC_GPOLYHL - CRC_GPOLYHL register.
+ * - CRC_GPOLYHU - CRC_GPOLYHU register.
+ * - CRC_CTRL - CRC Control register
+ * - CRC_CTRLHU - CRC_CTRLHU register.
+ */
+
+#define CRC_INSTANCE_COUNT (1U) /*!< Number of instances of the CRC module. */
+#define CRC_IDX (0U) /*!< Instance number for CRC. */
+
+/*******************************************************************************
+ * CRC_DATALL - CRC_DATALL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATALL - CRC_DATALL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATALL register
+ */
+/*@{*/
+#define CRC_RD_DATALL(base)      (CRC_DATALL_REG(base))
+#define CRC_WR_DATALL(base, value) (CRC_DATALL_REG(base) = (value))
+#define CRC_RMW_DATALL(base, mask, value) (CRC_WR_DATALL(base, (CRC_RD_DATALL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) |  (value)))
+#define CRC_CLR_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) & ~(value)))
+#define CRC_TOG_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAL - CRC_DATAL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAL - CRC_DATAL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAL register
+ */
+/*@{*/
+#define CRC_RD_DATAL(base)       (CRC_DATAL_REG(base))
+#define CRC_WR_DATAL(base, value) (CRC_DATAL_REG(base) = (value))
+#define CRC_RMW_DATAL(base, mask, value) (CRC_WR_DATAL(base, (CRC_RD_DATAL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) |  (value)))
+#define CRC_CLR_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) & ~(value)))
+#define CRC_TOG_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATA - CRC Data register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATA - CRC Data register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * The CRC Data register contains the value of the seed, data, and checksum.
+ * When CTRL[WAS] is set, any write to the data register is regarded as the seed
+ * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
+ * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
+ * not used for programming the seed value, and reads of these fields return an
+ * indeterminate value. In 32-bit CRC mode, all fields are used for programming
+ * the seed value. When programming data values, the values can be written 8 bits,
+ * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
+ * data value written first. After all data values are written, the CRC result
+ * can be read from this data register. In 16-bit CRC mode, the CRC result is
+ * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
+ * result. Reads of this register at any time return the intermediate CRC value,
+ * provided the CRC module is configured.
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATA register
+ */
+/*@{*/
+#define CRC_RD_DATA(base)        (CRC_DATA_REG(base))
+#define CRC_WR_DATA(base, value) (CRC_DATA_REG(base) = (value))
+#define CRC_RMW_DATA(base, mask, value) (CRC_WR_DATA(base, (CRC_RD_DATA(base) & ~(mask)) | (value)))
+#define CRC_SET_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) |  (value)))
+#define CRC_CLR_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) & ~(value)))
+#define CRC_TOG_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_DATA bitfields
+ */
+
+/*!
+ * @name Register CRC_DATA, field LL[7:0] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_LL field. */
+#define CRC_RD_DATA_LL(base) ((CRC_DATA_REG(base) & CRC_DATA_LL_MASK) >> CRC_DATA_LL_SHIFT)
+#define CRC_BRD_DATA_LL(base) (CRC_RD_DATA_LL(base))
+
+/*! @brief Set the LL field to a new value. */
+#define CRC_WR_DATA_LL(base, value) (CRC_RMW_DATA(base, CRC_DATA_LL_MASK, CRC_DATA_LL(value)))
+#define CRC_BWR_DATA_LL(base, value) (CRC_WR_DATA_LL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field LU[15:8] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_LU field. */
+#define CRC_RD_DATA_LU(base) ((CRC_DATA_REG(base) & CRC_DATA_LU_MASK) >> CRC_DATA_LU_SHIFT)
+#define CRC_BRD_DATA_LU(base) (CRC_RD_DATA_LU(base))
+
+/*! @brief Set the LU field to a new value. */
+#define CRC_WR_DATA_LU(base, value) (CRC_RMW_DATA(base, CRC_DATA_LU_MASK, CRC_DATA_LU(value)))
+#define CRC_BWR_DATA_LU(base, value) (CRC_WR_DATA_LU(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field HL[23:16] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_HL field. */
+#define CRC_RD_DATA_HL(base) ((CRC_DATA_REG(base) & CRC_DATA_HL_MASK) >> CRC_DATA_HL_SHIFT)
+#define CRC_BRD_DATA_HL(base) (CRC_RD_DATA_HL(base))
+
+/*! @brief Set the HL field to a new value. */
+#define CRC_WR_DATA_HL(base, value) (CRC_RMW_DATA(base, CRC_DATA_HL_MASK, CRC_DATA_HL(value)))
+#define CRC_BWR_DATA_HL(base, value) (CRC_WR_DATA_HL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field HU[31:24] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_HU field. */
+#define CRC_RD_DATA_HU(base) ((CRC_DATA_REG(base) & CRC_DATA_HU_MASK) >> CRC_DATA_HU_SHIFT)
+#define CRC_BRD_DATA_HU(base) (CRC_RD_DATA_HU(base))
+
+/*! @brief Set the HU field to a new value. */
+#define CRC_WR_DATA_HU(base, value) (CRC_RMW_DATA(base, CRC_DATA_HU_MASK, CRC_DATA_HU(value)))
+#define CRC_BWR_DATA_HU(base, value) (CRC_WR_DATA_HU(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATALU - CRC_DATALU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATALU - CRC_DATALU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATALU register
+ */
+/*@{*/
+#define CRC_RD_DATALU(base)      (CRC_DATALU_REG(base))
+#define CRC_WR_DATALU(base, value) (CRC_DATALU_REG(base) = (value))
+#define CRC_RMW_DATALU(base, mask, value) (CRC_WR_DATALU(base, (CRC_RD_DATALU(base) & ~(mask)) | (value)))
+#define CRC_SET_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) |  (value)))
+#define CRC_CLR_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) & ~(value)))
+#define CRC_TOG_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAHL - CRC_DATAHL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAHL - CRC_DATAHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAHL register
+ */
+/*@{*/
+#define CRC_RD_DATAHL(base)      (CRC_DATAHL_REG(base))
+#define CRC_WR_DATAHL(base, value) (CRC_DATAHL_REG(base) = (value))
+#define CRC_RMW_DATAHL(base, mask, value) (CRC_WR_DATAHL(base, (CRC_RD_DATAHL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) |  (value)))
+#define CRC_CLR_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) & ~(value)))
+#define CRC_TOG_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAH - CRC_DATAH register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAH - CRC_DATAH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAH register
+ */
+/*@{*/
+#define CRC_RD_DATAH(base)       (CRC_DATAH_REG(base))
+#define CRC_WR_DATAH(base, value) (CRC_DATAH_REG(base) = (value))
+#define CRC_RMW_DATAH(base, mask, value) (CRC_WR_DATAH(base, (CRC_RD_DATAH(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) |  (value)))
+#define CRC_CLR_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) & ~(value)))
+#define CRC_TOG_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAHU - CRC_DATAHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAHU - CRC_DATAHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAHU register
+ */
+/*@{*/
+#define CRC_RD_DATAHU(base)      (CRC_DATAHU_REG(base))
+#define CRC_WR_DATAHU(base, value) (CRC_DATAHU_REG(base) = (value))
+#define CRC_RMW_DATAHU(base, mask, value) (CRC_WR_DATAHU(base, (CRC_RD_DATAHU(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) |  (value)))
+#define CRC_CLR_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) & ~(value)))
+#define CRC_TOG_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYLL - CRC_GPOLYLL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYLL(base)     (CRC_GPOLYLL_REG(base))
+#define CRC_WR_GPOLYLL(base, value) (CRC_GPOLYLL_REG(base) = (value))
+#define CRC_RMW_GPOLYLL(base, mask, value) (CRC_WR_GPOLYLL(base, (CRC_RD_GPOLYLL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) |  (value)))
+#define CRC_CLR_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) & ~(value)))
+#define CRC_TOG_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLY - CRC Polynomial register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLY - CRC Polynomial register (RW)
+ *
+ * Reset value: 0x00001021U
+ *
+ * This register contains the value of the polynomial for the CRC calculation.
+ * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
+ * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
+ * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
+ * used in both 16- and 32-bit CRC modes.
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLY register
+ */
+/*@{*/
+#define CRC_RD_GPOLY(base)       (CRC_GPOLY_REG(base))
+#define CRC_WR_GPOLY(base, value) (CRC_GPOLY_REG(base) = (value))
+#define CRC_RMW_GPOLY(base, mask, value) (CRC_WR_GPOLY(base, (CRC_RD_GPOLY(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) |  (value)))
+#define CRC_CLR_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) & ~(value)))
+#define CRC_TOG_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_GPOLY bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLY, field LOW[15:0] (RW)
+ *
+ * Writable and readable in both 32-bit and 16-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_GPOLY_LOW field. */
+#define CRC_RD_GPOLY_LOW(base) ((CRC_GPOLY_REG(base) & CRC_GPOLY_LOW_MASK) >> CRC_GPOLY_LOW_SHIFT)
+#define CRC_BRD_GPOLY_LOW(base) (CRC_RD_GPOLY_LOW(base))
+
+/*! @brief Set the LOW field to a new value. */
+#define CRC_WR_GPOLY_LOW(base, value) (CRC_RMW_GPOLY(base, CRC_GPOLY_LOW_MASK, CRC_GPOLY_LOW(value)))
+#define CRC_BWR_GPOLY_LOW(base, value) (CRC_WR_GPOLY_LOW(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
+ *
+ * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
+ * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_GPOLY_HIGH field. */
+#define CRC_RD_GPOLY_HIGH(base) ((CRC_GPOLY_REG(base) & CRC_GPOLY_HIGH_MASK) >> CRC_GPOLY_HIGH_SHIFT)
+#define CRC_BRD_GPOLY_HIGH(base) (CRC_RD_GPOLY_HIGH(base))
+
+/*! @brief Set the HIGH field to a new value. */
+#define CRC_WR_GPOLY_HIGH(base, value) (CRC_RMW_GPOLY(base, CRC_GPOLY_HIGH_MASK, CRC_GPOLY_HIGH(value)))
+#define CRC_BWR_GPOLY_HIGH(base, value) (CRC_WR_GPOLY_HIGH(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYL - CRC_GPOLYL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYL - CRC_GPOLYL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYL(base)      (CRC_GPOLYL_REG(base))
+#define CRC_WR_GPOLYL(base, value) (CRC_GPOLYL_REG(base) = (value))
+#define CRC_RMW_GPOLYL(base, mask, value) (CRC_WR_GPOLYL(base, (CRC_RD_GPOLYL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) |  (value)))
+#define CRC_CLR_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) & ~(value)))
+#define CRC_TOG_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYLU - CRC_GPOLYLU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLU register
+ */
+/*@{*/
+#define CRC_RD_GPOLYLU(base)     (CRC_GPOLYLU_REG(base))
+#define CRC_WR_GPOLYLU(base, value) (CRC_GPOLYLU_REG(base) = (value))
+#define CRC_RMW_GPOLYLU(base, mask, value) (CRC_WR_GPOLYLU(base, (CRC_RD_GPOLYLU(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) |  (value)))
+#define CRC_CLR_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) & ~(value)))
+#define CRC_TOG_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYH - CRC_GPOLYH register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYH - CRC_GPOLYH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYH register
+ */
+/*@{*/
+#define CRC_RD_GPOLYH(base)      (CRC_GPOLYH_REG(base))
+#define CRC_WR_GPOLYH(base, value) (CRC_GPOLYH_REG(base) = (value))
+#define CRC_RMW_GPOLYH(base, mask, value) (CRC_WR_GPOLYH(base, (CRC_RD_GPOLYH(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) |  (value)))
+#define CRC_CLR_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) & ~(value)))
+#define CRC_TOG_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYHL - CRC_GPOLYHL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYHL(base)     (CRC_GPOLYHL_REG(base))
+#define CRC_WR_GPOLYHL(base, value) (CRC_GPOLYHL_REG(base) = (value))
+#define CRC_RMW_GPOLYHL(base, mask, value) (CRC_WR_GPOLYHL(base, (CRC_RD_GPOLYHL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) |  (value)))
+#define CRC_CLR_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) & ~(value)))
+#define CRC_TOG_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYHU - CRC_GPOLYHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHU register
+ */
+/*@{*/
+#define CRC_RD_GPOLYHU(base)     (CRC_GPOLYHU_REG(base))
+#define CRC_WR_GPOLYHU(base, value) (CRC_GPOLYHU_REG(base) = (value))
+#define CRC_RMW_GPOLYHU(base, mask, value) (CRC_WR_GPOLYHU(base, (CRC_RD_GPOLYHU(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) |  (value)))
+#define CRC_CLR_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) & ~(value)))
+#define CRC_TOG_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_CTRL - CRC Control register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_CTRL - CRC Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls the configuration and working of the CRC module.
+ * Appropriate bits must be set before starting a new CRC calculation. A new CRC
+ * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
+ * the CRC data register.
+ */
+/*!
+ * @name Constants and macros for entire CRC_CTRL register
+ */
+/*@{*/
+#define CRC_RD_CTRL(base)        (CRC_CTRL_REG(base))
+#define CRC_WR_CTRL(base, value) (CRC_CTRL_REG(base) = (value))
+#define CRC_RMW_CTRL(base, mask, value) (CRC_WR_CTRL(base, (CRC_RD_CTRL(base) & ~(mask)) | (value)))
+#define CRC_SET_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) |  (value)))
+#define CRC_CLR_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) & ~(value)))
+#define CRC_TOG_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_CTRL bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRL, field TCRC[24] (RW)
+ *
+ * Width of CRC protocol.
+ *
+ * Values:
+ * - 0b0 - 16-bit CRC protocol.
+ * - 0b1 - 32-bit CRC protocol.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TCRC field. */
+#define CRC_RD_CTRL_TCRC(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TCRC_MASK) >> CRC_CTRL_TCRC_SHIFT)
+#define CRC_BRD_CTRL_TCRC(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_TCRC_SHIFT))
+
+/*! @brief Set the TCRC field to a new value. */
+#define CRC_WR_CTRL_TCRC(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TCRC_MASK, CRC_CTRL_TCRC(value)))
+#define CRC_BWR_CTRL_TCRC(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_TCRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field WAS[25] (RW)
+ *
+ * When asserted, a value written to the CRC data register is considered a seed
+ * value. When deasserted, a value written to the CRC data register is taken as
+ * data for CRC computation.
+ *
+ * Values:
+ * - 0b0 - Writes to the CRC data register are data values.
+ * - 0b1 - Writes to the CRC data register are seed values.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_WAS field. */
+#define CRC_RD_CTRL_WAS(base) ((CRC_CTRL_REG(base) & CRC_CTRL_WAS_MASK) >> CRC_CTRL_WAS_SHIFT)
+#define CRC_BRD_CTRL_WAS(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_WAS_SHIFT))
+
+/*! @brief Set the WAS field to a new value. */
+#define CRC_WR_CTRL_WAS(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_WAS_MASK, CRC_CTRL_WAS(value)))
+#define CRC_BWR_CTRL_WAS(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_WAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field FXOR[26] (RW)
+ *
+ * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
+ * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
+ *
+ * Values:
+ * - 0b0 - No XOR on reading.
+ * - 0b1 - Invert or complement the read value of the CRC Data register.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_FXOR field. */
+#define CRC_RD_CTRL_FXOR(base) ((CRC_CTRL_REG(base) & CRC_CTRL_FXOR_MASK) >> CRC_CTRL_FXOR_SHIFT)
+#define CRC_BRD_CTRL_FXOR(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_FXOR_SHIFT))
+
+/*! @brief Set the FXOR field to a new value. */
+#define CRC_WR_CTRL_FXOR(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_FXOR_MASK, CRC_CTRL_FXOR(value)))
+#define CRC_BWR_CTRL_FXOR(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_FXOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field TOTR[29:28] (RW)
+ *
+ * Identifies the transpose configuration of the value read from the CRC Data
+ * register. See the description of the transpose feature for the available
+ * transpose options.
+ *
+ * Values:
+ * - 0b00 - No transposition.
+ * - 0b01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TOTR field. */
+#define CRC_RD_CTRL_TOTR(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT)
+#define CRC_BRD_CTRL_TOTR(base) (CRC_RD_CTRL_TOTR(base))
+
+/*! @brief Set the TOTR field to a new value. */
+#define CRC_WR_CTRL_TOTR(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TOTR_MASK, CRC_CTRL_TOTR(value)))
+#define CRC_BWR_CTRL_TOTR(base, value) (CRC_WR_CTRL_TOTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field TOT[31:30] (RW)
+ *
+ * Defines the transpose configuration of the data written to the CRC data
+ * register. See the description of the transpose feature for the available transpose
+ * options.
+ *
+ * Values:
+ * - 0b00 - No transposition.
+ * - 0b01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TOT field. */
+#define CRC_RD_CTRL_TOT(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TOT_MASK) >> CRC_CTRL_TOT_SHIFT)
+#define CRC_BRD_CTRL_TOT(base) (CRC_RD_CTRL_TOT(base))
+
+/*! @brief Set the TOT field to a new value. */
+#define CRC_WR_CTRL_TOT(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TOT_MASK, CRC_CTRL_TOT(value)))
+#define CRC_BWR_CTRL_TOT(base, value) (CRC_WR_CTRL_TOT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_CTRLHU - CRC_CTRLHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_CTRLHU - CRC_CTRLHU register. (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CRC_CTRLHU register
+ */
+/*@{*/
+#define CRC_RD_CTRLHU(base)      (CRC_CTRLHU_REG(base))
+#define CRC_WR_CTRLHU(base, value) (CRC_CTRLHU_REG(base) = (value))
+#define CRC_RMW_CTRLHU(base, mask, value) (CRC_WR_CTRLHU(base, (CRC_RD_CTRLHU(base) & ~(mask)) | (value)))
+#define CRC_SET_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) |  (value)))
+#define CRC_CLR_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) & ~(value)))
+#define CRC_TOG_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_CTRLHU bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRLHU, field TCRC[0] (RW)
+ *
+ * Values:
+ * - 0b0 - 16-bit CRC protocol.
+ * - 0b1 - 32-bit CRC protocol.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TCRC field. */
+#define CRC_RD_CTRLHU_TCRC(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TCRC_MASK) >> CRC_CTRLHU_TCRC_SHIFT)
+#define CRC_BRD_CTRLHU_TCRC(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_TCRC_SHIFT))
+
+/*! @brief Set the TCRC field to a new value. */
+#define CRC_WR_CTRLHU_TCRC(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TCRC_MASK, CRC_CTRLHU_TCRC(value)))
+#define CRC_BWR_CTRLHU_TCRC(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_TCRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field WAS[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Writes to CRC data register are data values.
+ * - 0b1 - Writes to CRC data reguster are seed values.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_WAS field. */
+#define CRC_RD_CTRLHU_WAS(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_WAS_MASK) >> CRC_CTRLHU_WAS_SHIFT)
+#define CRC_BRD_CTRLHU_WAS(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_WAS_SHIFT))
+
+/*! @brief Set the WAS field to a new value. */
+#define CRC_WR_CTRLHU_WAS(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_WAS_MASK, CRC_CTRLHU_WAS(value)))
+#define CRC_BWR_CTRLHU_WAS(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_WAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field FXOR[2] (RW)
+ *
+ * Values:
+ * - 0b0 - No XOR on reading.
+ * - 0b1 - Invert or complement the read value of CRC data register.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_FXOR field. */
+#define CRC_RD_CTRLHU_FXOR(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_FXOR_MASK) >> CRC_CTRLHU_FXOR_SHIFT)
+#define CRC_BRD_CTRLHU_FXOR(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_FXOR_SHIFT))
+
+/*! @brief Set the FXOR field to a new value. */
+#define CRC_WR_CTRLHU_FXOR(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_FXOR_MASK, CRC_CTRLHU_FXOR(value)))
+#define CRC_BWR_CTRLHU_FXOR(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_FXOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
+ *
+ * Values:
+ * - 0b00 - No Transposition.
+ * - 0b01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TOTR field. */
+#define CRC_RD_CTRLHU_TOTR(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TOTR_MASK) >> CRC_CTRLHU_TOTR_SHIFT)
+#define CRC_BRD_CTRLHU_TOTR(base) (CRC_RD_CTRLHU_TOTR(base))
+
+/*! @brief Set the TOTR field to a new value. */
+#define CRC_WR_CTRLHU_TOTR(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TOTR_MASK, CRC_CTRLHU_TOTR(value)))
+#define CRC_BWR_CTRLHU_TOTR(base, value) (CRC_WR_CTRLHU_TOTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
+ *
+ * Values:
+ * - 0b00 - No Transposition.
+ * - 0b01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TOT field. */
+#define CRC_RD_CTRLHU_TOT(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TOT_MASK) >> CRC_CTRLHU_TOT_SHIFT)
+#define CRC_BRD_CTRLHU_TOT(base) (CRC_RD_CTRLHU_TOT(base))
+
+/*! @brief Set the TOT field to a new value. */
+#define CRC_WR_CTRLHU_TOT(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TOT_MASK, CRC_CTRLHU_TOT(value)))
+#define CRC_BWR_CTRLHU_TOT(base, value) (CRC_WR_CTRLHU_TOT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 DAC
+ *
+ * 12-Bit Digital-to-Analog Converter
+ *
+ * Registers defined in this header file:
+ * - DAC_DATL - DAC Data Low Register
+ * - DAC_DATH - DAC Data High Register
+ * - DAC_SR - DAC Status Register
+ * - DAC_C0 - DAC Control Register
+ * - DAC_C1 - DAC Control Register 1
+ * - DAC_C2 - DAC Control Register 2
+ */
+
+#define DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
+#define DAC0_IDX (0U) /*!< Instance number for DAC0. */
+#define DAC1_IDX (1U) /*!< Instance number for DAC1. */
+
+/*******************************************************************************
+ * DAC_DATL - DAC Data Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATL - DAC Data Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATL register
+ */
+/*@{*/
+#define DAC_RD_DATL(base, index) (DAC_DATL_REG(base, index))
+#define DAC_WR_DATL(base, index, value) (DAC_DATL_REG(base, index) = (value))
+#define DAC_RMW_DATL(base, index, mask, value) (DAC_WR_DATL(base, index, (DAC_RD_DATL(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) |  (value)))
+#define DAC_CLR_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) & ~(value)))
+#define DAC_TOG_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_DATH - DAC Data High Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATH - DAC Data High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATH register
+ */
+/*@{*/
+#define DAC_RD_DATH(base, index) (DAC_DATH_REG(base, index))
+#define DAC_WR_DATH(base, index, value) (DAC_DATH_REG(base, index) = (value))
+#define DAC_RMW_DATH(base, index, mask, value) (DAC_WR_DATH(base, index, (DAC_RD_DATH(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) |  (value)))
+#define DAC_CLR_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) & ~(value)))
+#define DAC_TOG_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_DATH bitfields
+ */
+
+/*!
+ * @name Register DAC_DATH, field DATA1[3:0] (RW)
+ *
+ * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
+ * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
+ * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_DATH_DATA1 field. */
+#define DAC_RD_DATH_DATA1(base, index) ((DAC_DATH_REG(base, index) & DAC_DATH_DATA1_MASK) >> DAC_DATH_DATA1_SHIFT)
+#define DAC_BRD_DATH_DATA1(base, index) (DAC_RD_DATH_DATA1(base, index))
+
+/*! @brief Set the DATA1 field to a new value. */
+#define DAC_WR_DATH_DATA1(base, index, value) (DAC_RMW_DATH(base, index, DAC_DATH_DATA1_MASK, DAC_DATH_DATA1(value)))
+#define DAC_BWR_DATH_DATA1(base, index, value) (DAC_WR_DATH_DATA1(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_SR - DAC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_SR - DAC Status Register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
+ * request is done. Writing 0 to a field clears it whereas writing 1 has no
+ * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
+ * The flags are set only when the data buffer status is changed. Do not use
+ * 32/16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_SR register
+ */
+/*@{*/
+#define DAC_RD_SR(base)          (DAC_SR_REG(base))
+#define DAC_WR_SR(base, value)   (DAC_SR_REG(base) = (value))
+#define DAC_RMW_SR(base, mask, value) (DAC_WR_SR(base, (DAC_RD_SR(base) & ~(mask)) | (value)))
+#define DAC_SET_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) |  (value)))
+#define DAC_CLR_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) & ~(value)))
+#define DAC_TOG_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_SR bitfields
+ */
+
+/*!
+ * @name Register DAC_SR, field DACBFRPBF[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
+ * - 0b1 - The DAC buffer read pointer is equal to C2[DACBFUP].
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
+#define DAC_RD_SR_DACBFRPBF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPBF_MASK) >> DAC_SR_DACBFRPBF_SHIFT)
+#define DAC_BRD_SR_DACBFRPBF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT))
+
+/*! @brief Set the DACBFRPBF field to a new value. */
+#define DAC_WR_SR_DACBFRPBF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPBF_MASK, DAC_SR_DACBFRPBF(value)))
+#define DAC_BWR_SR_DACBFRPBF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFRPTF[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer is not zero.
+ * - 0b1 - The DAC buffer read pointer is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
+#define DAC_RD_SR_DACBFRPTF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPTF_MASK) >> DAC_SR_DACBFRPTF_SHIFT)
+#define DAC_BRD_SR_DACBFRPTF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT))
+
+/*! @brief Set the DACBFRPTF field to a new value. */
+#define DAC_WR_SR_DACBFRPTF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPTF_MASK, DAC_SR_DACBFRPTF(value)))
+#define DAC_BWR_SR_DACBFRPTF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFWMF[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer has not reached the watermark level.
+ * - 0b1 - The DAC buffer read pointer has reached the watermark level.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFWMF field. */
+#define DAC_RD_SR_DACBFWMF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFWMF_MASK) >> DAC_SR_DACBFWMF_SHIFT)
+#define DAC_BRD_SR_DACBFWMF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFWMF_SHIFT))
+
+/*! @brief Set the DACBFWMF field to a new value. */
+#define DAC_WR_SR_DACBFWMF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFWMF_MASK, DAC_SR_DACBFWMF(value)))
+#define DAC_BWR_SR_DACBFWMF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFWMF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C0 - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C0 - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_C0 register
+ */
+/*@{*/
+#define DAC_RD_C0(base)          (DAC_C0_REG(base))
+#define DAC_WR_C0(base, value)   (DAC_C0_REG(base) = (value))
+#define DAC_RMW_C0(base, mask, value) (DAC_WR_C0(base, (DAC_RD_C0(base) & ~(mask)) | (value)))
+#define DAC_SET_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) |  (value)))
+#define DAC_CLR_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) & ~(value)))
+#define DAC_TOG_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C0 bitfields
+ */
+
+/*!
+ * @name Register DAC_C0, field DACBBIEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer bottom flag interrupt is disabled.
+ * - 0b1 - The DAC buffer read pointer bottom flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBBIEN field. */
+#define DAC_RD_C0_DACBBIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBBIEN_MASK) >> DAC_C0_DACBBIEN_SHIFT)
+#define DAC_BRD_C0_DACBBIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT))
+
+/*! @brief Set the DACBBIEN field to a new value. */
+#define DAC_WR_C0_DACBBIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBBIEN_MASK, DAC_C0_DACBBIEN(value)))
+#define DAC_BWR_C0_DACBBIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBTIEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer top flag interrupt is disabled.
+ * - 0b1 - The DAC buffer read pointer top flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBTIEN field. */
+#define DAC_RD_C0_DACBTIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBTIEN_MASK) >> DAC_C0_DACBTIEN_SHIFT)
+#define DAC_BRD_C0_DACBTIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT))
+
+/*! @brief Set the DACBTIEN field to a new value. */
+#define DAC_WR_C0_DACBTIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBTIEN_MASK, DAC_C0_DACBTIEN(value)))
+#define DAC_BWR_C0_DACBTIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBWIEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer watermark interrupt is disabled.
+ * - 0b1 - The DAC buffer watermark interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBWIEN field. */
+#define DAC_RD_C0_DACBWIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBWIEN_MASK) >> DAC_C0_DACBWIEN_SHIFT)
+#define DAC_BRD_C0_DACBWIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBWIEN_SHIFT))
+
+/*! @brief Set the DACBWIEN field to a new value. */
+#define DAC_WR_C0_DACBWIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBWIEN_MASK, DAC_C0_DACBWIEN(value)))
+#define DAC_BWR_C0_DACBWIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBWIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field LPEN[3] (RW)
+ *
+ * See the 12-bit DAC electrical characteristics of the device data sheet for
+ * details on the impact of the modes below.
+ *
+ * Values:
+ * - 0b0 - High-Power mode
+ * - 0b1 - Low-Power mode
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_LPEN field. */
+#define DAC_RD_C0_LPEN(base) ((DAC_C0_REG(base) & DAC_C0_LPEN_MASK) >> DAC_C0_LPEN_SHIFT)
+#define DAC_BRD_C0_LPEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT))
+
+/*! @brief Set the LPEN field to a new value. */
+#define DAC_WR_C0_LPEN(base, value) (DAC_RMW_C0(base, DAC_C0_LPEN_MASK, DAC_C0_LPEN(value)))
+#define DAC_BWR_C0_LPEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
+ *
+ * Active high. This is a write-only field, which always reads 0. If DAC
+ * software trigger is selected and buffer is enabled, writing 1 to this field will
+ * advance the buffer read pointer once.
+ *
+ * Values:
+ * - 0b0 - The DAC soft trigger is not valid.
+ * - 0b1 - The DAC soft trigger is valid.
+ */
+/*@{*/
+/*! @brief Set the DACSWTRG field to a new value. */
+#define DAC_WR_C0_DACSWTRG(base, value) (DAC_RMW_C0(base, DAC_C0_DACSWTRG_MASK, DAC_C0_DACSWTRG(value)))
+#define DAC_BWR_C0_DACSWTRG(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACSWTRG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACTRGSEL[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC hardware trigger is selected.
+ * - 0b1 - The DAC software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
+#define DAC_RD_C0_DACTRGSEL(base) ((DAC_C0_REG(base) & DAC_C0_DACTRGSEL_MASK) >> DAC_C0_DACTRGSEL_SHIFT)
+#define DAC_BRD_C0_DACTRGSEL(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT))
+
+/*! @brief Set the DACTRGSEL field to a new value. */
+#define DAC_WR_C0_DACTRGSEL(base, value) (DAC_RMW_C0(base, DAC_C0_DACTRGSEL_MASK, DAC_C0_DACTRGSEL(value)))
+#define DAC_BWR_C0_DACTRGSEL(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACRFS[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC selects DACREF_1 as the reference voltage.
+ * - 0b1 - The DAC selects DACREF_2 as the reference voltage.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACRFS field. */
+#define DAC_RD_C0_DACRFS(base) ((DAC_C0_REG(base) & DAC_C0_DACRFS_MASK) >> DAC_C0_DACRFS_SHIFT)
+#define DAC_BRD_C0_DACRFS(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT))
+
+/*! @brief Set the DACRFS field to a new value. */
+#define DAC_WR_C0_DACRFS(base, value) (DAC_RMW_C0(base, DAC_C0_DACRFS_MASK, DAC_C0_DACRFS(value)))
+#define DAC_BWR_C0_DACRFS(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACEN[7] (RW)
+ *
+ * Starts the Programmable Reference Generator operation.
+ *
+ * Values:
+ * - 0b0 - The DAC system is disabled.
+ * - 0b1 - The DAC system is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACEN field. */
+#define DAC_RD_C0_DACEN(base) ((DAC_C0_REG(base) & DAC_C0_DACEN_MASK) >> DAC_C0_DACEN_SHIFT)
+#define DAC_BRD_C0_DACEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT))
+
+/*! @brief Set the DACEN field to a new value. */
+#define DAC_WR_C0_DACEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACEN_MASK, DAC_C0_DACEN(value)))
+#define DAC_BWR_C0_DACEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C1 - DAC Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C1 - DAC Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_C1 register
+ */
+/*@{*/
+#define DAC_RD_C1(base)          (DAC_C1_REG(base))
+#define DAC_WR_C1(base, value)   (DAC_C1_REG(base) = (value))
+#define DAC_RMW_C1(base, mask, value) (DAC_WR_C1(base, (DAC_RD_C1(base) & ~(mask)) | (value)))
+#define DAC_SET_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) |  (value)))
+#define DAC_CLR_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) & ~(value)))
+#define DAC_TOG_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C1 bitfields
+ */
+
+/*!
+ * @name Register DAC_C1, field DACBFEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Buffer read pointer is disabled. The converted data is always the
+ *     first word of the buffer.
+ * - 0b1 - Buffer read pointer is enabled. The converted data is the word that
+ *     the read pointer points to. It means converted data can be from any word of
+ *     the buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFEN field. */
+#define DAC_RD_C1_DACBFEN(base) ((DAC_C1_REG(base) & DAC_C1_DACBFEN_MASK) >> DAC_C1_DACBFEN_SHIFT)
+#define DAC_BRD_C1_DACBFEN(base) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT))
+
+/*! @brief Set the DACBFEN field to a new value. */
+#define DAC_WR_C1_DACBFEN(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFEN_MASK, DAC_C1_DACBFEN(value)))
+#define DAC_BWR_C1_DACBFEN(base, value) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFMD[2:1] (RW)
+ *
+ * Values:
+ * - 0b00 - Normal mode
+ * - 0b01 - Swing mode
+ * - 0b10 - One-Time Scan mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFMD field. */
+#define DAC_RD_C1_DACBFMD(base) ((DAC_C1_REG(base) & DAC_C1_DACBFMD_MASK) >> DAC_C1_DACBFMD_SHIFT)
+#define DAC_BRD_C1_DACBFMD(base) (DAC_RD_C1_DACBFMD(base))
+
+/*! @brief Set the DACBFMD field to a new value. */
+#define DAC_WR_C1_DACBFMD(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFMD_MASK, DAC_C1_DACBFMD(value)))
+#define DAC_BWR_C1_DACBFMD(base, value) (DAC_WR_C1_DACBFMD(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFWM[4:3] (RW)
+ *
+ * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
+ * the word defined by this field, which is 1-4 words away from the upper limit
+ * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
+ * watermark interrupt.
+ *
+ * Values:
+ * - 0b00 - 1 word
+ * - 0b01 - 2 words
+ * - 0b10 - 3 words
+ * - 0b11 - 4 words
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFWM field. */
+#define DAC_RD_C1_DACBFWM(base) ((DAC_C1_REG(base) & DAC_C1_DACBFWM_MASK) >> DAC_C1_DACBFWM_SHIFT)
+#define DAC_BRD_C1_DACBFWM(base) (DAC_RD_C1_DACBFWM(base))
+
+/*! @brief Set the DACBFWM field to a new value. */
+#define DAC_WR_C1_DACBFWM(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFWM_MASK, DAC_C1_DACBFWM(value)))
+#define DAC_BWR_C1_DACBFWM(base, value) (DAC_WR_C1_DACBFWM(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DMAEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled. When DMA is enabled, the DMA request will be
+ *     generated by original interrupts. The interrupts will not be presented on this
+ *     module at the same time.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DMAEN field. */
+#define DAC_RD_C1_DMAEN(base) ((DAC_C1_REG(base) & DAC_C1_DMAEN_MASK) >> DAC_C1_DMAEN_SHIFT)
+#define DAC_BRD_C1_DMAEN(base) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define DAC_WR_C1_DMAEN(base, value) (DAC_RMW_C1(base, DAC_C1_DMAEN_MASK, DAC_C1_DMAEN(value)))
+#define DAC_BWR_C1_DMAEN(base, value) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C2 - DAC Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C2 - DAC Control Register 2 (RW)
+ *
+ * Reset value: 0x0FU
+ */
+/*!
+ * @name Constants and macros for entire DAC_C2 register
+ */
+/*@{*/
+#define DAC_RD_C2(base)          (DAC_C2_REG(base))
+#define DAC_WR_C2(base, value)   (DAC_C2_REG(base) = (value))
+#define DAC_RMW_C2(base, mask, value) (DAC_WR_C2(base, (DAC_RD_C2(base) & ~(mask)) | (value)))
+#define DAC_SET_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) |  (value)))
+#define DAC_CLR_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) & ~(value)))
+#define DAC_TOG_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C2 bitfields
+ */
+
+/*!
+ * @name Register DAC_C2, field DACBFUP[3:0] (RW)
+ *
+ * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
+ * exceed it.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFUP field. */
+#define DAC_RD_C2_DACBFUP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFUP_MASK) >> DAC_C2_DACBFUP_SHIFT)
+#define DAC_BRD_C2_DACBFUP(base) (DAC_RD_C2_DACBFUP(base))
+
+/*! @brief Set the DACBFUP field to a new value. */
+#define DAC_WR_C2_DACBFUP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFUP_MASK, DAC_C2_DACBFUP(value)))
+#define DAC_BWR_C2_DACBFUP(base, value) (DAC_WR_C2_DACBFUP(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C2, field DACBFRP[7:4] (RW)
+ *
+ * Keeps the current value of the buffer read pointer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFRP field. */
+#define DAC_RD_C2_DACBFRP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT)
+#define DAC_BRD_C2_DACBFRP(base) (DAC_RD_C2_DACBFRP(base))
+
+/*! @brief Set the DACBFRP field to a new value. */
+#define DAC_WR_C2_DACBFRP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFRP_MASK, DAC_C2_DACBFRP(value)))
+#define DAC_BWR_C2_DACBFRP(base, value) (DAC_WR_C2_DACBFRP(base, value))
+/*@}*/
+
+/*
+ * MK64F12 DMA
+ *
+ * Enhanced direct memory access controller
+ *
+ * Registers defined in this header file:
+ * - DMA_CR - Control Register
+ * - DMA_ES - Error Status Register
+ * - DMA_ERQ - Enable Request Register
+ * - DMA_EEI - Enable Error Interrupt Register
+ * - DMA_CEEI - Clear Enable Error Interrupt Register
+ * - DMA_SEEI - Set Enable Error Interrupt Register
+ * - DMA_CERQ - Clear Enable Request Register
+ * - DMA_SERQ - Set Enable Request Register
+ * - DMA_CDNE - Clear DONE Status Bit Register
+ * - DMA_SSRT - Set START Bit Register
+ * - DMA_CERR - Clear Error Register
+ * - DMA_CINT - Clear Interrupt Request Register
+ * - DMA_INT - Interrupt Request Register
+ * - DMA_ERR - Error Register
+ * - DMA_HRS - Hardware Request Status Register
+ * - DMA_DCHPRI3 - Channel n Priority Register
+ * - DMA_DCHPRI2 - Channel n Priority Register
+ * - DMA_DCHPRI1 - Channel n Priority Register
+ * - DMA_DCHPRI0 - Channel n Priority Register
+ * - DMA_DCHPRI7 - Channel n Priority Register
+ * - DMA_DCHPRI6 - Channel n Priority Register
+ * - DMA_DCHPRI5 - Channel n Priority Register
+ * - DMA_DCHPRI4 - Channel n Priority Register
+ * - DMA_DCHPRI11 - Channel n Priority Register
+ * - DMA_DCHPRI10 - Channel n Priority Register
+ * - DMA_DCHPRI9 - Channel n Priority Register
+ * - DMA_DCHPRI8 - Channel n Priority Register
+ * - DMA_DCHPRI15 - Channel n Priority Register
+ * - DMA_DCHPRI14 - Channel n Priority Register
+ * - DMA_DCHPRI13 - Channel n Priority Register
+ * - DMA_DCHPRI12 - Channel n Priority Register
+ * - DMA_SADDR - TCD Source Address
+ * - DMA_SOFF - TCD Signed Source Address Offset
+ * - DMA_ATTR - TCD Transfer Attributes
+ * - DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ * - DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ * - DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ * - DMA_SLAST - TCD Last Source Address Adjustment
+ * - DMA_DADDR - TCD Destination Address
+ * - DMA_DOFF - TCD Signed Destination Address Offset
+ * - DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ * - DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ * - DMA_CSR - TCD Control and Status
+ * - DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ */
+
+#define DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
+#define DMA_IDX (0U) /*!< Instance number for DMA. */
+
+/*******************************************************************************
+ * DMA_CR - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CR defines the basic operating configuration of the DMA. Arbitration can
+ * be configured to use either a fixed-priority or a round-robin scheme. For
+ * fixed-priority arbitration, the highest priority channel requesting service is
+ * selected to execute. The channel priority registers assign the priorities; see
+ * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
+ * ignored and channels are cycled through (from high to low channel number)
+ * without regard to priority. For correct operation, writes to the CR register must
+ * be performed only when the DMA channels are inactive; that is, when
+ * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
+ * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
+ * minor loop completion. When minor loop offsets are enabled, the minor loop
+ * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
+ * destination address (TCDn_DADDR), or to both prior to the addresses being
+ * written back into the TCD. If the major loop is complete, the minor loop offset is
+ * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
+ * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
+ * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
+ * is used to specify multiple fields: a source enable bit (SMLOE) to specify
+ * the minor loop offset should be applied to the source address (TCDn_SADDR) upon
+ * minor loop completion, a destination enable bit (DMLOE) to specify the minor
+ * loop offset should be applied to the destination address (TCDn_DADDR) upon
+ * minor loop completion, and the sign extended minor loop offset value (MLOFF). The
+ * same offset value (MLOFF) is used for both source and destination minor loop
+ * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
+ * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
+ * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
+ * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
+ * assigned to the NBYTES field.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CR register
+ */
+/*@{*/
+#define DMA_RD_CR(base)          (DMA_CR_REG(base))
+#define DMA_WR_CR(base, value)   (DMA_CR_REG(base) = (value))
+#define DMA_RMW_CR(base, mask, value) (DMA_WR_CR(base, (DMA_RD_CR(base) & ~(mask)) | (value)))
+#define DMA_SET_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) |  (value)))
+#define DMA_CLR_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) & ~(value)))
+#define DMA_TOG_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CR bitfields
+ */
+
+/*!
+ * @name Register DMA_CR, field EDBG[1] (RW)
+ *
+ * Values:
+ * - 0b0 - When in debug mode, the DMA continues to operate.
+ * - 0b1 - When in debug mode, the DMA stalls the start of a new channel.
+ *     Executing channels are allowed to complete. Channel execution resumes when the
+ *     system exits debug mode or the EDBG bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_EDBG field. */
+#define DMA_RD_CR_EDBG(base) ((DMA_CR_REG(base) & DMA_CR_EDBG_MASK) >> DMA_CR_EDBG_SHIFT)
+#define DMA_BRD_CR_EDBG(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EDBG_SHIFT))
+
+/*! @brief Set the EDBG field to a new value. */
+#define DMA_WR_CR_EDBG(base, value) (DMA_RMW_CR(base, DMA_CR_EDBG_MASK, DMA_CR_EDBG(value)))
+#define DMA_BWR_CR_EDBG(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EDBG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field ERCA[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Fixed priority arbitration is used for channel selection .
+ * - 0b1 - Round robin arbitration is used for channel selection .
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_ERCA field. */
+#define DMA_RD_CR_ERCA(base) ((DMA_CR_REG(base) & DMA_CR_ERCA_MASK) >> DMA_CR_ERCA_SHIFT)
+#define DMA_BRD_CR_ERCA(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ERCA_SHIFT))
+
+/*! @brief Set the ERCA field to a new value. */
+#define DMA_WR_CR_ERCA(base, value) (DMA_RMW_CR(base, DMA_CR_ERCA_MASK, DMA_CR_ERCA(value)))
+#define DMA_BWR_CR_ERCA(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ERCA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field HOE[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Any error causes the HALT bit to set. Subsequently, all service
+ *     requests are ignored until the HALT bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_HOE field. */
+#define DMA_RD_CR_HOE(base)  ((DMA_CR_REG(base) & DMA_CR_HOE_MASK) >> DMA_CR_HOE_SHIFT)
+#define DMA_BRD_CR_HOE(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HOE_SHIFT))
+
+/*! @brief Set the HOE field to a new value. */
+#define DMA_WR_CR_HOE(base, value) (DMA_RMW_CR(base, DMA_CR_HOE_MASK, DMA_CR_HOE(value)))
+#define DMA_BWR_CR_HOE(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field HALT[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Stall the start of any new channels. Executing channels are allowed
+ *     to complete. Channel execution resumes when this bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_HALT field. */
+#define DMA_RD_CR_HALT(base) ((DMA_CR_REG(base) & DMA_CR_HALT_MASK) >> DMA_CR_HALT_SHIFT)
+#define DMA_BRD_CR_HALT(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define DMA_WR_CR_HALT(base, value) (DMA_RMW_CR(base, DMA_CR_HALT_MASK, DMA_CR_HALT(value)))
+#define DMA_BWR_CR_HALT(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field CLM[6] (RW)
+ *
+ * Values:
+ * - 0b0 - A minor loop channel link made to itself goes through channel
+ *     arbitration before being activated again.
+ * - 0b1 - A minor loop channel link made to itself does not go through channel
+ *     arbitration before being activated again. Upon minor loop completion, the
+ *     channel activates again if that channel has a minor loop channel link
+ *     enabled and the link channel is itself. This effectively applies the minor
+ *     loop offsets and restarts the next minor loop.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_CLM field. */
+#define DMA_RD_CR_CLM(base)  ((DMA_CR_REG(base) & DMA_CR_CLM_MASK) >> DMA_CR_CLM_SHIFT)
+#define DMA_BRD_CR_CLM(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CLM_SHIFT))
+
+/*! @brief Set the CLM field to a new value. */
+#define DMA_WR_CR_CLM(base, value) (DMA_RMW_CR(base, DMA_CR_CLM_MASK, DMA_CR_CLM(value)))
+#define DMA_BWR_CR_CLM(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CLM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field EMLM[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
+ * - 0b1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
+ *     an offset field, and the NBYTES field. The individual enable fields allow
+ *     the minor loop offset to be applied to the source address, the
+ *     destination address, or both. The NBYTES field is reduced when either offset is
+ *     enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_EMLM field. */
+#define DMA_RD_CR_EMLM(base) ((DMA_CR_REG(base) & DMA_CR_EMLM_MASK) >> DMA_CR_EMLM_SHIFT)
+#define DMA_BRD_CR_EMLM(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EMLM_SHIFT))
+
+/*! @brief Set the EMLM field to a new value. */
+#define DMA_WR_CR_EMLM(base, value) (DMA_RMW_CR(base, DMA_CR_EMLM_MASK, DMA_CR_EMLM(value)))
+#define DMA_BWR_CR_EMLM(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EMLM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field ECX[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Cancel the remaining data transfer in the same fashion as the CX bit.
+ *     Stop the executing channel and force the minor loop to finish. The cancel
+ *     takes effect after the last write of the current read/write sequence. The
+ *     ECX bit clears itself after the cancel is honored. In addition to
+ *     cancelling the transfer, ECX treats the cancel as an error condition, thus
+ *     updating the Error Status register (DMAx_ES) and generating an optional error
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_ECX field. */
+#define DMA_RD_CR_ECX(base)  ((DMA_CR_REG(base) & DMA_CR_ECX_MASK) >> DMA_CR_ECX_SHIFT)
+#define DMA_BRD_CR_ECX(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ECX_SHIFT))
+
+/*! @brief Set the ECX field to a new value. */
+#define DMA_WR_CR_ECX(base, value) (DMA_RMW_CR(base, DMA_CR_ECX_MASK, DMA_CR_ECX(value)))
+#define DMA_BWR_CR_ECX(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ECX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field CX[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Cancel the remaining data transfer. Stop the executing channel and
+ *     force the minor loop to finish. The cancel takes effect after the last write
+ *     of the current read/write sequence. The CX bit clears itself after the
+ *     cancel has been honored. This cancel retires the channel normally as if the
+ *     minor loop was completed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_CX field. */
+#define DMA_RD_CR_CX(base)   ((DMA_CR_REG(base) & DMA_CR_CX_MASK) >> DMA_CR_CX_SHIFT)
+#define DMA_BRD_CR_CX(base)  (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CX_SHIFT))
+
+/*! @brief Set the CX field to a new value. */
+#define DMA_WR_CR_CX(base, value) (DMA_RMW_CR(base, DMA_CR_CX_MASK, DMA_CR_CX(value)))
+#define DMA_BWR_CR_CX(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CX_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ES - Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ES - Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ES provides information concerning the last recorded channel error.
+ * Channel errors can be caused by: A configuration error, that is: An illegal setting
+ * in the transfer-control descriptor, or An illegal priority register setting
+ * in fixed-arbitration An error termination to a bus master read or write cycle
+ * See the Error Reporting and Handling section for more details.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ES register
+ */
+/*@{*/
+#define DMA_RD_ES(base)          (DMA_ES_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ES bitfields
+ */
+
+/*!
+ * @name Register DMA_ES, field DBE[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination bus error
+ * - 0b1 - The last recorded error was a bus error on a destination write
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DBE field. */
+#define DMA_RD_ES_DBE(base)  ((DMA_ES_REG(base) & DMA_ES_DBE_MASK) >> DMA_ES_DBE_SHIFT)
+#define DMA_BRD_ES_DBE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SBE[1] (RO)
+ *
+ * Values:
+ * - 0b0 - No source bus error
+ * - 0b1 - The last recorded error was a bus error on a source read
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SBE field. */
+#define DMA_RD_ES_SBE(base)  ((DMA_ES_REG(base) & DMA_ES_SBE_MASK) >> DMA_ES_SBE_SHIFT)
+#define DMA_BRD_ES_SBE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SGE[2] (RO)
+ *
+ * Values:
+ * - 0b0 - No scatter/gather configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DLASTSGA field. This field is checked at the beginning of a
+ *     scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled.
+ *     TCDn_DLASTSGA is not on a 32 byte boundary.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SGE field. */
+#define DMA_RD_ES_SGE(base)  ((DMA_ES_REG(base) & DMA_ES_SGE_MASK) >> DMA_ES_SGE_SHIFT)
+#define DMA_BRD_ES_SGE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SGE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field NCE[3] (RO)
+ *
+ * Values:
+ * - 0b0 - No NBYTES/CITER configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
+ *     TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
+ *     TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_NCE field. */
+#define DMA_RD_ES_NCE(base)  ((DMA_ES_REG(base) & DMA_ES_NCE_MASK) >> DMA_ES_NCE_SHIFT)
+#define DMA_BRD_ES_NCE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_NCE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field DOE[4] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination offset configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DOE field. */
+#define DMA_RD_ES_DOE(base)  ((DMA_ES_REG(base) & DMA_ES_DOE_MASK) >> DMA_ES_DOE_SHIFT)
+#define DMA_BRD_ES_DOE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field DAE[5] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination address configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DAE field. */
+#define DMA_RD_ES_DAE(base)  ((DMA_ES_REG(base) & DMA_ES_DAE_MASK) >> DMA_ES_DAE_SHIFT)
+#define DMA_BRD_ES_DAE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DAE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SOE[6] (RO)
+ *
+ * Values:
+ * - 0b0 - No source offset configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SOE field. */
+#define DMA_RD_ES_SOE(base)  ((DMA_ES_REG(base) & DMA_ES_SOE_MASK) >> DMA_ES_SOE_SHIFT)
+#define DMA_BRD_ES_SOE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SAE[7] (RO)
+ *
+ * Values:
+ * - 0b0 - No source address configuration error.
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SAE field. */
+#define DMA_RD_ES_SAE(base)  ((DMA_ES_REG(base) & DMA_ES_SAE_MASK) >> DMA_ES_SAE_SHIFT)
+#define DMA_BRD_ES_SAE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SAE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field ERRCHN[11:8] (RO)
+ *
+ * The channel number of the last recorded error (excluding CPE errors) or last
+ * recorded error canceled transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_ERRCHN field. */
+#define DMA_RD_ES_ERRCHN(base) ((DMA_ES_REG(base) & DMA_ES_ERRCHN_MASK) >> DMA_ES_ERRCHN_SHIFT)
+#define DMA_BRD_ES_ERRCHN(base) (DMA_RD_ES_ERRCHN(base))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field CPE[14] (RO)
+ *
+ * Values:
+ * - 0b0 - No channel priority error
+ * - 0b1 - The last recorded error was a configuration error in the channel
+ *     priorities . Channel priorities are not unique.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_CPE field. */
+#define DMA_RD_ES_CPE(base)  ((DMA_ES_REG(base) & DMA_ES_CPE_MASK) >> DMA_ES_CPE_SHIFT)
+#define DMA_BRD_ES_CPE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_CPE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field ECX[16] (RO)
+ *
+ * Values:
+ * - 0b0 - No canceled transfers
+ * - 0b1 - The last recorded entry was a canceled transfer by the error cancel
+ *     transfer input
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_ECX field. */
+#define DMA_RD_ES_ECX(base)  ((DMA_ES_REG(base) & DMA_ES_ECX_MASK) >> DMA_ES_ECX_SHIFT)
+#define DMA_BRD_ES_ECX(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_ECX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field VLD[31] (RO)
+ *
+ * Logical OR of all ERR status bits
+ *
+ * Values:
+ * - 0b0 - No ERR bits are set
+ * - 0b1 - At least one ERR bit is set indicating a valid error exists that has
+ *     not been cleared
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_VLD field. */
+#define DMA_RD_ES_VLD(base)  ((DMA_ES_REG(base) & DMA_ES_VLD_MASK) >> DMA_ES_VLD_SHIFT)
+#define DMA_BRD_ES_VLD(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_VLD_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ERQ - Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ERQ - Enable Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERQ register provides a bit map for the 16 implemented channels to enable
+ * the request signal for each channel. The state of any given channel enable is
+ * directly affected by writes to this register; it is also affected by writes
+ * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
+ * for a single channel can easily be modified without needing to perform a
+ * read-modify-write sequence to the ERQ. DMA request input signals and this enable
+ * request flag must be asserted before a channel's hardware service request is
+ * accepted. The state of the DMA enable request flag does not affect a channel
+ * service request made explicitly through software or a linked channel request.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ERQ register
+ */
+/*@{*/
+#define DMA_RD_ERQ(base)         (DMA_ERQ_REG(base))
+#define DMA_WR_ERQ(base, value)  (DMA_ERQ_REG(base) = (value))
+#define DMA_RMW_ERQ(base, mask, value) (DMA_WR_ERQ(base, (DMA_RD_ERQ(base) & ~(mask)) | (value)))
+#define DMA_SET_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) |  (value)))
+#define DMA_CLR_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) & ~(value)))
+#define DMA_TOG_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_ERQ, field ERQ0[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ0 field. */
+#define DMA_RD_ERQ_ERQ0(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ0_MASK) >> DMA_ERQ_ERQ0_SHIFT)
+#define DMA_BRD_ERQ_ERQ0(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ0_SHIFT))
+
+/*! @brief Set the ERQ0 field to a new value. */
+#define DMA_WR_ERQ_ERQ0(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ0_MASK, DMA_ERQ_ERQ0(value)))
+#define DMA_BWR_ERQ_ERQ0(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ1[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ1 field. */
+#define DMA_RD_ERQ_ERQ1(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ1_MASK) >> DMA_ERQ_ERQ1_SHIFT)
+#define DMA_BRD_ERQ_ERQ1(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ1_SHIFT))
+
+/*! @brief Set the ERQ1 field to a new value. */
+#define DMA_WR_ERQ_ERQ1(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ1_MASK, DMA_ERQ_ERQ1(value)))
+#define DMA_BWR_ERQ_ERQ1(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ2[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ2 field. */
+#define DMA_RD_ERQ_ERQ2(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ2_MASK) >> DMA_ERQ_ERQ2_SHIFT)
+#define DMA_BRD_ERQ_ERQ2(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ2_SHIFT))
+
+/*! @brief Set the ERQ2 field to a new value. */
+#define DMA_WR_ERQ_ERQ2(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ2_MASK, DMA_ERQ_ERQ2(value)))
+#define DMA_BWR_ERQ_ERQ2(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ3[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ3 field. */
+#define DMA_RD_ERQ_ERQ3(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ3_MASK) >> DMA_ERQ_ERQ3_SHIFT)
+#define DMA_BRD_ERQ_ERQ3(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ3_SHIFT))
+
+/*! @brief Set the ERQ3 field to a new value. */
+#define DMA_WR_ERQ_ERQ3(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ3_MASK, DMA_ERQ_ERQ3(value)))
+#define DMA_BWR_ERQ_ERQ3(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ4[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ4 field. */
+#define DMA_RD_ERQ_ERQ4(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ4_MASK) >> DMA_ERQ_ERQ4_SHIFT)
+#define DMA_BRD_ERQ_ERQ4(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ4_SHIFT))
+
+/*! @brief Set the ERQ4 field to a new value. */
+#define DMA_WR_ERQ_ERQ4(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ4_MASK, DMA_ERQ_ERQ4(value)))
+#define DMA_BWR_ERQ_ERQ4(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ5[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ5 field. */
+#define DMA_RD_ERQ_ERQ5(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ5_MASK) >> DMA_ERQ_ERQ5_SHIFT)
+#define DMA_BRD_ERQ_ERQ5(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ5_SHIFT))
+
+/*! @brief Set the ERQ5 field to a new value. */
+#define DMA_WR_ERQ_ERQ5(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ5_MASK, DMA_ERQ_ERQ5(value)))
+#define DMA_BWR_ERQ_ERQ5(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ6[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ6 field. */
+#define DMA_RD_ERQ_ERQ6(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ6_MASK) >> DMA_ERQ_ERQ6_SHIFT)
+#define DMA_BRD_ERQ_ERQ6(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ6_SHIFT))
+
+/*! @brief Set the ERQ6 field to a new value. */
+#define DMA_WR_ERQ_ERQ6(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ6_MASK, DMA_ERQ_ERQ6(value)))
+#define DMA_BWR_ERQ_ERQ6(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ7[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ7 field. */
+#define DMA_RD_ERQ_ERQ7(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ7_MASK) >> DMA_ERQ_ERQ7_SHIFT)
+#define DMA_BRD_ERQ_ERQ7(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ7_SHIFT))
+
+/*! @brief Set the ERQ7 field to a new value. */
+#define DMA_WR_ERQ_ERQ7(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ7_MASK, DMA_ERQ_ERQ7(value)))
+#define DMA_BWR_ERQ_ERQ7(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ8[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ8 field. */
+#define DMA_RD_ERQ_ERQ8(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ8_MASK) >> DMA_ERQ_ERQ8_SHIFT)
+#define DMA_BRD_ERQ_ERQ8(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ8_SHIFT))
+
+/*! @brief Set the ERQ8 field to a new value. */
+#define DMA_WR_ERQ_ERQ8(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ8_MASK, DMA_ERQ_ERQ8(value)))
+#define DMA_BWR_ERQ_ERQ8(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ9[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ9 field. */
+#define DMA_RD_ERQ_ERQ9(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ9_MASK) >> DMA_ERQ_ERQ9_SHIFT)
+#define DMA_BRD_ERQ_ERQ9(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ9_SHIFT))
+
+/*! @brief Set the ERQ9 field to a new value. */
+#define DMA_WR_ERQ_ERQ9(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ9_MASK, DMA_ERQ_ERQ9(value)))
+#define DMA_BWR_ERQ_ERQ9(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ10[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ10 field. */
+#define DMA_RD_ERQ_ERQ10(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ10_MASK) >> DMA_ERQ_ERQ10_SHIFT)
+#define DMA_BRD_ERQ_ERQ10(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ10_SHIFT))
+
+/*! @brief Set the ERQ10 field to a new value. */
+#define DMA_WR_ERQ_ERQ10(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ10_MASK, DMA_ERQ_ERQ10(value)))
+#define DMA_BWR_ERQ_ERQ10(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ11[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ11 field. */
+#define DMA_RD_ERQ_ERQ11(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ11_MASK) >> DMA_ERQ_ERQ11_SHIFT)
+#define DMA_BRD_ERQ_ERQ11(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ11_SHIFT))
+
+/*! @brief Set the ERQ11 field to a new value. */
+#define DMA_WR_ERQ_ERQ11(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ11_MASK, DMA_ERQ_ERQ11(value)))
+#define DMA_BWR_ERQ_ERQ11(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ12[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ12 field. */
+#define DMA_RD_ERQ_ERQ12(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ12_MASK) >> DMA_ERQ_ERQ12_SHIFT)
+#define DMA_BRD_ERQ_ERQ12(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ12_SHIFT))
+
+/*! @brief Set the ERQ12 field to a new value. */
+#define DMA_WR_ERQ_ERQ12(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ12_MASK, DMA_ERQ_ERQ12(value)))
+#define DMA_BWR_ERQ_ERQ12(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ13[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ13 field. */
+#define DMA_RD_ERQ_ERQ13(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ13_MASK) >> DMA_ERQ_ERQ13_SHIFT)
+#define DMA_BRD_ERQ_ERQ13(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ13_SHIFT))
+
+/*! @brief Set the ERQ13 field to a new value. */
+#define DMA_WR_ERQ_ERQ13(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ13_MASK, DMA_ERQ_ERQ13(value)))
+#define DMA_BWR_ERQ_ERQ13(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ14[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ14 field. */
+#define DMA_RD_ERQ_ERQ14(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ14_MASK) >> DMA_ERQ_ERQ14_SHIFT)
+#define DMA_BRD_ERQ_ERQ14(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ14_SHIFT))
+
+/*! @brief Set the ERQ14 field to a new value. */
+#define DMA_WR_ERQ_ERQ14(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ14_MASK, DMA_ERQ_ERQ14(value)))
+#define DMA_BWR_ERQ_ERQ14(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ15[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ15 field. */
+#define DMA_RD_ERQ_ERQ15(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ15_MASK) >> DMA_ERQ_ERQ15_SHIFT)
+#define DMA_BRD_ERQ_ERQ15(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ15_SHIFT))
+
+/*! @brief Set the ERQ15 field to a new value. */
+#define DMA_WR_ERQ_ERQ15(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ15_MASK, DMA_ERQ_ERQ15(value)))
+#define DMA_BWR_ERQ_ERQ15(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_EEI - Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_EEI - Enable Error Interrupt Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The EEI register provides a bit map for the 16 channels to enable the error
+ * interrupt signal for each channel. The state of any given channel's error
+ * interrupt enable is directly affected by writes to this register; it is also
+ * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
+ * interrupt enable for a single channel can easily be modified without the need to
+ * perform a read-modify-write sequence to the EEI register. The DMA error
+ * indicator and the error interrupt enable flag must be asserted before an error
+ * interrupt request for a given channel is asserted to the interrupt controller.
+ */
+/*!
+ * @name Constants and macros for entire DMA_EEI register
+ */
+/*@{*/
+#define DMA_RD_EEI(base)         (DMA_EEI_REG(base))
+#define DMA_WR_EEI(base, value)  (DMA_EEI_REG(base) = (value))
+#define DMA_RMW_EEI(base, mask, value) (DMA_WR_EEI(base, (DMA_RD_EEI(base) & ~(mask)) | (value)))
+#define DMA_SET_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) |  (value)))
+#define DMA_CLR_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) & ~(value)))
+#define DMA_TOG_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_EEI bitfields
+ */
+
+/*!
+ * @name Register DMA_EEI, field EEI0[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI0 field. */
+#define DMA_RD_EEI_EEI0(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI0_MASK) >> DMA_EEI_EEI0_SHIFT)
+#define DMA_BRD_EEI_EEI0(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI0_SHIFT))
+
+/*! @brief Set the EEI0 field to a new value. */
+#define DMA_WR_EEI_EEI0(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI0_MASK, DMA_EEI_EEI0(value)))
+#define DMA_BWR_EEI_EEI0(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI1[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI1 field. */
+#define DMA_RD_EEI_EEI1(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI1_MASK) >> DMA_EEI_EEI1_SHIFT)
+#define DMA_BRD_EEI_EEI1(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI1_SHIFT))
+
+/*! @brief Set the EEI1 field to a new value. */
+#define DMA_WR_EEI_EEI1(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI1_MASK, DMA_EEI_EEI1(value)))
+#define DMA_BWR_EEI_EEI1(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI2[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI2 field. */
+#define DMA_RD_EEI_EEI2(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI2_MASK) >> DMA_EEI_EEI2_SHIFT)
+#define DMA_BRD_EEI_EEI2(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI2_SHIFT))
+
+/*! @brief Set the EEI2 field to a new value. */
+#define DMA_WR_EEI_EEI2(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI2_MASK, DMA_EEI_EEI2(value)))
+#define DMA_BWR_EEI_EEI2(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI3[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI3 field. */
+#define DMA_RD_EEI_EEI3(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI3_MASK) >> DMA_EEI_EEI3_SHIFT)
+#define DMA_BRD_EEI_EEI3(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI3_SHIFT))
+
+/*! @brief Set the EEI3 field to a new value. */
+#define DMA_WR_EEI_EEI3(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI3_MASK, DMA_EEI_EEI3(value)))
+#define DMA_BWR_EEI_EEI3(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI4[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI4 field. */
+#define DMA_RD_EEI_EEI4(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI4_MASK) >> DMA_EEI_EEI4_SHIFT)
+#define DMA_BRD_EEI_EEI4(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI4_SHIFT))
+
+/*! @brief Set the EEI4 field to a new value. */
+#define DMA_WR_EEI_EEI4(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI4_MASK, DMA_EEI_EEI4(value)))
+#define DMA_BWR_EEI_EEI4(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI5[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI5 field. */
+#define DMA_RD_EEI_EEI5(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI5_MASK) >> DMA_EEI_EEI5_SHIFT)
+#define DMA_BRD_EEI_EEI5(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI5_SHIFT))
+
+/*! @brief Set the EEI5 field to a new value. */
+#define DMA_WR_EEI_EEI5(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI5_MASK, DMA_EEI_EEI5(value)))
+#define DMA_BWR_EEI_EEI5(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI6[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI6 field. */
+#define DMA_RD_EEI_EEI6(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI6_MASK) >> DMA_EEI_EEI6_SHIFT)
+#define DMA_BRD_EEI_EEI6(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI6_SHIFT))
+
+/*! @brief Set the EEI6 field to a new value. */
+#define DMA_WR_EEI_EEI6(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI6_MASK, DMA_EEI_EEI6(value)))
+#define DMA_BWR_EEI_EEI6(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI7[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI7 field. */
+#define DMA_RD_EEI_EEI7(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI7_MASK) >> DMA_EEI_EEI7_SHIFT)
+#define DMA_BRD_EEI_EEI7(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI7_SHIFT))
+
+/*! @brief Set the EEI7 field to a new value. */
+#define DMA_WR_EEI_EEI7(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI7_MASK, DMA_EEI_EEI7(value)))
+#define DMA_BWR_EEI_EEI7(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI8[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI8 field. */
+#define DMA_RD_EEI_EEI8(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI8_MASK) >> DMA_EEI_EEI8_SHIFT)
+#define DMA_BRD_EEI_EEI8(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI8_SHIFT))
+
+/*! @brief Set the EEI8 field to a new value. */
+#define DMA_WR_EEI_EEI8(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI8_MASK, DMA_EEI_EEI8(value)))
+#define DMA_BWR_EEI_EEI8(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI9[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI9 field. */
+#define DMA_RD_EEI_EEI9(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI9_MASK) >> DMA_EEI_EEI9_SHIFT)
+#define DMA_BRD_EEI_EEI9(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI9_SHIFT))
+
+/*! @brief Set the EEI9 field to a new value. */
+#define DMA_WR_EEI_EEI9(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI9_MASK, DMA_EEI_EEI9(value)))
+#define DMA_BWR_EEI_EEI9(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI10[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI10 field. */
+#define DMA_RD_EEI_EEI10(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI10_MASK) >> DMA_EEI_EEI10_SHIFT)
+#define DMA_BRD_EEI_EEI10(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI10_SHIFT))
+
+/*! @brief Set the EEI10 field to a new value. */
+#define DMA_WR_EEI_EEI10(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI10_MASK, DMA_EEI_EEI10(value)))
+#define DMA_BWR_EEI_EEI10(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI11[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI11 field. */
+#define DMA_RD_EEI_EEI11(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI11_MASK) >> DMA_EEI_EEI11_SHIFT)
+#define DMA_BRD_EEI_EEI11(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI11_SHIFT))
+
+/*! @brief Set the EEI11 field to a new value. */
+#define DMA_WR_EEI_EEI11(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI11_MASK, DMA_EEI_EEI11(value)))
+#define DMA_BWR_EEI_EEI11(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI12[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI12 field. */
+#define DMA_RD_EEI_EEI12(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI12_MASK) >> DMA_EEI_EEI12_SHIFT)
+#define DMA_BRD_EEI_EEI12(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI12_SHIFT))
+
+/*! @brief Set the EEI12 field to a new value. */
+#define DMA_WR_EEI_EEI12(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI12_MASK, DMA_EEI_EEI12(value)))
+#define DMA_BWR_EEI_EEI12(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI13[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI13 field. */
+#define DMA_RD_EEI_EEI13(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI13_MASK) >> DMA_EEI_EEI13_SHIFT)
+#define DMA_BRD_EEI_EEI13(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI13_SHIFT))
+
+/*! @brief Set the EEI13 field to a new value. */
+#define DMA_WR_EEI_EEI13(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI13_MASK, DMA_EEI_EEI13(value)))
+#define DMA_BWR_EEI_EEI13(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI14[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI14 field. */
+#define DMA_RD_EEI_EEI14(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI14_MASK) >> DMA_EEI_EEI14_SHIFT)
+#define DMA_BRD_EEI_EEI14(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI14_SHIFT))
+
+/*! @brief Set the EEI14 field to a new value. */
+#define DMA_WR_EEI_EEI14(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI14_MASK, DMA_EEI_EEI14(value)))
+#define DMA_BWR_EEI_EEI14(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI15[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI15 field. */
+#define DMA_RD_EEI_EEI15(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI15_MASK) >> DMA_EEI_EEI15_SHIFT)
+#define DMA_BRD_EEI_EEI15(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI15_SHIFT))
+
+/*! @brief Set the EEI15 field to a new value. */
+#define DMA_WR_EEI_EEI15(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI15_MASK, DMA_EEI_EEI15(value)))
+#define DMA_BWR_EEI_EEI15(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CEEI - Clear Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CEEI - Clear Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
+ * the EEI to disable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be cleared. Setting
+ * the CAEE bit provides a global clear function, forcing the EEI contents to be
+ * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
+ * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
+ * Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CEEI register
+ */
+/*@{*/
+#define DMA_RD_CEEI(base)        (DMA_CEEI_REG(base))
+#define DMA_WR_CEEI(base, value) (DMA_CEEI_REG(base) = (value))
+#define DMA_RMW_CEEI(base, mask, value) (DMA_WR_CEEI(base, (DMA_RD_CEEI(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in EEI
+ */
+/*@{*/
+/*! @brief Set the CEEI field to a new value. */
+#define DMA_WR_CEEI_CEEI(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_CEEI_MASK, DMA_CEEI_CEEI(value)))
+#define DMA_BWR_CEEI_CEEI(base, value) (DMA_WR_CEEI_CEEI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CEEI, field CAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the EEI bit specified in the CEEI field
+ * - 0b1 - Clear all bits in EEI
+ */
+/*@{*/
+/*! @brief Set the CAEE field to a new value. */
+#define DMA_WR_CEEI_CAEE(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_CAEE_MASK, DMA_CEEI_CAEE(value)))
+#define DMA_BWR_CEEI_CAEE(base, value) (BITBAND_ACCESS8(&DMA_CEEI_REG(base), DMA_CEEI_CAEE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CEEI_NOP(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_NOP_MASK, DMA_CEEI_NOP(value)))
+#define DMA_BWR_CEEI_NOP(base, value) (BITBAND_ACCESS8(&DMA_CEEI_REG(base), DMA_CEEI_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SEEI - Set Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SEEI - Set Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
+ * EEI to enable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be set. Setting the
+ * SAEE bit provides a global set function, forcing the entire EEI contents to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SEEI register
+ */
+/*@{*/
+#define DMA_RD_SEEI(base)        (DMA_SEEI_REG(base))
+#define DMA_WR_SEEI(base, value) (DMA_SEEI_REG(base) = (value))
+#define DMA_RMW_SEEI(base, mask, value) (DMA_WR_SEEI(base, (DMA_RD_SEEI(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in EEI
+ */
+/*@{*/
+/*! @brief Set the SEEI field to a new value. */
+#define DMA_WR_SEEI_SEEI(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_SEEI_MASK, DMA_SEEI_SEEI(value)))
+#define DMA_BWR_SEEI_SEEI(base, value) (DMA_WR_SEEI_SEEI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SEEI, field SAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the EEI bit specified in the SEEI field.
+ * - 0b1 - Sets all bits in EEI
+ */
+/*@{*/
+/*! @brief Set the SAEE field to a new value. */
+#define DMA_WR_SEEI_SAEE(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_SAEE_MASK, DMA_SEEI_SAEE(value)))
+#define DMA_BWR_SEEI_SAEE(base, value) (BITBAND_ACCESS8(&DMA_SEEI_REG(base), DMA_SEEI_SAEE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SEEI_NOP(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_NOP_MASK, DMA_SEEI_NOP(value)))
+#define DMA_BWR_SEEI_NOP(base, value) (BITBAND_ACCESS8(&DMA_SEEI_REG(base), DMA_SEEI_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CERQ - Clear Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CERQ - Clear Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERQ to disable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be cleared. Setting the
+ * CAER bit provides a global clear function, forcing the entire contents of the
+ * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
+ * command is ignored. This allows you to write multiple-byte registers as a 32-bit
+ * word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CERQ register
+ */
+/*@{*/
+#define DMA_RD_CERQ(base)        (DMA_CERQ_REG(base))
+#define DMA_WR_CERQ(base, value) (DMA_CERQ_REG(base) = (value))
+#define DMA_RMW_CERQ(base, mask, value) (DMA_WR_CERQ(base, (DMA_RD_CERQ(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERQ
+ */
+/*@{*/
+/*! @brief Set the CERQ field to a new value. */
+#define DMA_WR_CERQ_CERQ(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_CERQ_MASK, DMA_CERQ_CERQ(value)))
+#define DMA_BWR_CERQ_CERQ(base, value) (DMA_WR_CERQ_CERQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERQ, field CAER[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the ERQ bit specified in the CERQ field
+ * - 0b1 - Clear all bits in ERQ
+ */
+/*@{*/
+/*! @brief Set the CAER field to a new value. */
+#define DMA_WR_CERQ_CAER(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_CAER_MASK, DMA_CERQ_CAER(value)))
+#define DMA_BWR_CERQ_CAER(base, value) (BITBAND_ACCESS8(&DMA_CERQ_REG(base), DMA_CERQ_CAER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CERQ_NOP(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_NOP_MASK, DMA_CERQ_NOP(value)))
+#define DMA_BWR_CERQ_NOP(base, value) (BITBAND_ACCESS8(&DMA_CERQ_REG(base), DMA_CERQ_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SERQ - Set Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SERQ - Set Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
+ * ERQ to enable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
+ * bit provides a global set function, forcing the entire contents of ERQ to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SERQ register
+ */
+/*@{*/
+#define DMA_RD_SERQ(base)        (DMA_SERQ_REG(base))
+#define DMA_WR_SERQ(base, value) (DMA_SERQ_REG(base) = (value))
+#define DMA_RMW_SERQ(base, mask, value) (DMA_WR_SERQ(base, (DMA_RD_SERQ(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in ERQ
+ */
+/*@{*/
+/*! @brief Set the SERQ field to a new value. */
+#define DMA_WR_SERQ_SERQ(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_SERQ_MASK, DMA_SERQ_SERQ(value)))
+#define DMA_BWR_SERQ_SERQ(base, value) (DMA_WR_SERQ_SERQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SERQ, field SAER[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the ERQ bit specified in the SERQ field
+ * - 0b1 - Set all bits in ERQ
+ */
+/*@{*/
+/*! @brief Set the SAER field to a new value. */
+#define DMA_WR_SERQ_SAER(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_SAER_MASK, DMA_SERQ_SAER(value)))
+#define DMA_BWR_SERQ_SAER(base, value) (BITBAND_ACCESS8(&DMA_SERQ_REG(base), DMA_SERQ_SAER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SERQ_NOP(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_NOP_MASK, DMA_SERQ_NOP(value)))
+#define DMA_BWR_SERQ_NOP(base, value) (BITBAND_ACCESS8(&DMA_SERQ_REG(base), DMA_SERQ_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CDNE - Clear DONE Status Bit Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CDNE - Clear DONE Status Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
+ * the CADN bit provides a global clear function, forcing all DONE bits to be
+ * cleared. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CDNE register
+ */
+/*@{*/
+#define DMA_RD_CDNE(base)        (DMA_CDNE_REG(base))
+#define DMA_WR_CDNE(base, value) (DMA_CDNE_REG(base) = (value))
+#define DMA_RMW_CDNE(base, mask, value) (DMA_WR_CDNE(base, (DMA_RD_CDNE(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CDNE bitfields
+ */
+
+/*!
+ * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in TCDn_CSR[DONE]
+ */
+/*@{*/
+/*! @brief Set the CDNE field to a new value. */
+#define DMA_WR_CDNE_CDNE(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_CDNE_MASK, DMA_CDNE_CDNE(value)))
+#define DMA_BWR_CDNE_CDNE(base, value) (DMA_WR_CDNE_CDNE(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CDNE, field CADN[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
+ * - 0b1 - Clears all bits in TCDn_CSR[DONE]
+ */
+/*@{*/
+/*! @brief Set the CADN field to a new value. */
+#define DMA_WR_CDNE_CADN(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_CADN_MASK, DMA_CDNE_CADN(value)))
+#define DMA_BWR_CDNE_CADN(base, value) (BITBAND_ACCESS8(&DMA_CDNE_REG(base), DMA_CDNE_CADN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CDNE, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CDNE_NOP(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_NOP_MASK, DMA_CDNE_NOP(value)))
+#define DMA_BWR_CDNE_NOP(base, value) (BITBAND_ACCESS8(&DMA_CDNE_REG(base), DMA_CDNE_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SSRT - Set START Bit Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SSRT - Set START Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SSRT provides a simple memory-mapped mechanism to set the START bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * START bit in the corresponding transfer control descriptor to be set. Setting the
+ * SAST bit provides a global set function, forcing all START bits to be set. If
+ * the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SSRT register
+ */
+/*@{*/
+#define DMA_RD_SSRT(base)        (DMA_SSRT_REG(base))
+#define DMA_WR_SSRT(base, value) (DMA_SSRT_REG(base) = (value))
+#define DMA_RMW_SSRT(base, mask, value) (DMA_WR_SSRT(base, (DMA_RD_SSRT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SSRT bitfields
+ */
+
+/*!
+ * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in TCDn_CSR[START]
+ */
+/*@{*/
+/*! @brief Set the SSRT field to a new value. */
+#define DMA_WR_SSRT_SSRT(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_SSRT_MASK, DMA_SSRT_SSRT(value)))
+#define DMA_BWR_SSRT_SSRT(base, value) (DMA_WR_SSRT_SSRT(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SSRT, field SAST[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
+ * - 0b1 - Set all bits in TCDn_CSR[START]
+ */
+/*@{*/
+/*! @brief Set the SAST field to a new value. */
+#define DMA_WR_SSRT_SAST(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_SAST_MASK, DMA_SSRT_SAST(value)))
+#define DMA_BWR_SSRT_SAST(base, value) (BITBAND_ACCESS8(&DMA_SSRT_REG(base), DMA_SSRT_SAST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SSRT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SSRT_NOP(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_NOP_MASK, DMA_SSRT_NOP(value)))
+#define DMA_BWR_SSRT_NOP(base, value) (BITBAND_ACCESS8(&DMA_SSRT_REG(base), DMA_SSRT_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CERR - Clear Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CERR - Clear Error Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERR provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERR to disable the error condition flag for a given channel. The given value
+ * on a register write causes the corresponding bit in the ERR to be cleared.
+ * Setting the CAEI bit provides a global clear function, forcing the ERR contents
+ * to be cleared, clearing all channel error indicators. If the NOP bit is set,
+ * the command is ignored. This allows you to write multiple-byte registers as a
+ * 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CERR register
+ */
+/*@{*/
+#define DMA_RD_CERR(base)        (DMA_CERR_REG(base))
+#define DMA_WR_CERR(base, value) (DMA_CERR_REG(base) = (value))
+#define DMA_RMW_CERR(base, mask, value) (DMA_WR_CERR(base, (DMA_RD_CERR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CERR bitfields
+ */
+
+/*!
+ * @name Register DMA_CERR, field CERR[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERR
+ */
+/*@{*/
+/*! @brief Set the CERR field to a new value. */
+#define DMA_WR_CERR_CERR(base, value) (DMA_RMW_CERR(base, DMA_CERR_CERR_MASK, DMA_CERR_CERR(value)))
+#define DMA_BWR_CERR_CERR(base, value) (DMA_WR_CERR_CERR(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERR, field CAEI[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the ERR bit specified in the CERR field
+ * - 0b1 - Clear all bits in ERR
+ */
+/*@{*/
+/*! @brief Set the CAEI field to a new value. */
+#define DMA_WR_CERR_CAEI(base, value) (DMA_RMW_CERR(base, DMA_CERR_CAEI_MASK, DMA_CERR_CAEI(value)))
+#define DMA_BWR_CERR_CAEI(base, value) (BITBAND_ACCESS8(&DMA_CERR_REG(base), DMA_CERR_CAEI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERR, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CERR_NOP(base, value) (DMA_RMW_CERR(base, DMA_CERR_NOP_MASK, DMA_CERR_NOP(value)))
+#define DMA_BWR_CERR_NOP(base, value) (BITBAND_ACCESS8(&DMA_CERR_REG(base), DMA_CERR_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CINT - Clear Interrupt Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CINT - Clear Interrupt Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
+ * the INT to disable the interrupt request for a given channel. The given value
+ * on a register write causes the corresponding bit in the INT to be cleared.
+ * Setting the CAIR bit provides a global clear function, forcing the entire contents
+ * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
+ * bit is set, the command is ignored. This allows you to write multiple-byte
+ * registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CINT register
+ */
+/*@{*/
+#define DMA_RD_CINT(base)        (DMA_CINT_REG(base))
+#define DMA_WR_CINT(base, value) (DMA_CINT_REG(base) = (value))
+#define DMA_RMW_CINT(base, mask, value) (DMA_WR_CINT(base, (DMA_RD_CINT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CINT bitfields
+ */
+
+/*!
+ * @name Register DMA_CINT, field CINT[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in INT
+ */
+/*@{*/
+/*! @brief Set the CINT field to a new value. */
+#define DMA_WR_CINT_CINT(base, value) (DMA_RMW_CINT(base, DMA_CINT_CINT_MASK, DMA_CINT_CINT(value)))
+#define DMA_BWR_CINT_CINT(base, value) (DMA_WR_CINT_CINT(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CINT, field CAIR[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the INT bit specified in the CINT field
+ * - 0b1 - Clear all bits in INT
+ */
+/*@{*/
+/*! @brief Set the CAIR field to a new value. */
+#define DMA_WR_CINT_CAIR(base, value) (DMA_RMW_CINT(base, DMA_CINT_CAIR_MASK, DMA_CINT_CAIR(value)))
+#define DMA_BWR_CINT_CAIR(base, value) (BITBAND_ACCESS8(&DMA_CINT_REG(base), DMA_CINT_CAIR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CINT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CINT_NOP(base, value) (DMA_RMW_CINT(base, DMA_CINT_NOP_MASK, DMA_CINT_NOP(value)))
+#define DMA_BWR_CINT_NOP(base, value) (BITBAND_ACCESS8(&DMA_CINT_REG(base), DMA_CINT_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_INT - Interrupt Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_INT - Interrupt Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The INT register provides a bit map for the 16 channels signaling the
+ * presence of an interrupt request for each channel. Depending on the appropriate bit
+ * setting in the transfer-control descriptors, the eDMA engine generates an
+ * interrupt on data transfer completion. The outputs of this register are directly
+ * routed to the interrupt controller (INTC). During the interrupt-service routine
+ * associated with any given channel, it is the software's responsibility to
+ * clear the appropriate bit, negating the interrupt request. Typically, a write to
+ * the CINT register in the interrupt service routine is used for this purpose.
+ * The state of any given channel's interrupt request is directly affected by
+ * writes to this register; it is also affected by writes to the CINT register. On
+ * writes to INT, a 1 in any bit position clears the corresponding channel's
+ * interrupt request. A zero in any bit position has no affect on the corresponding
+ * channel's current interrupt status. The CINT register is provided so the interrupt
+ * request for a single channel can easily be cleared without the need to
+ * perform a read-modify-write sequence to the INT register.
+ */
+/*!
+ * @name Constants and macros for entire DMA_INT register
+ */
+/*@{*/
+#define DMA_RD_INT(base)         (DMA_INT_REG(base))
+#define DMA_WR_INT(base, value)  (DMA_INT_REG(base) = (value))
+#define DMA_RMW_INT(base, mask, value) (DMA_WR_INT(base, (DMA_RD_INT(base) & ~(mask)) | (value)))
+#define DMA_SET_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) |  (value)))
+#define DMA_CLR_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) & ~(value)))
+#define DMA_TOG_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_INT bitfields
+ */
+
+/*!
+ * @name Register DMA_INT, field INT0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT0 field. */
+#define DMA_RD_INT_INT0(base) ((DMA_INT_REG(base) & DMA_INT_INT0_MASK) >> DMA_INT_INT0_SHIFT)
+#define DMA_BRD_INT_INT0(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT0_SHIFT))
+
+/*! @brief Set the INT0 field to a new value. */
+#define DMA_WR_INT_INT0(base, value) (DMA_RMW_INT(base, (DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT0(value)))
+#define DMA_BWR_INT_INT0(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT1 field. */
+#define DMA_RD_INT_INT1(base) ((DMA_INT_REG(base) & DMA_INT_INT1_MASK) >> DMA_INT_INT1_SHIFT)
+#define DMA_BRD_INT_INT1(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT1_SHIFT))
+
+/*! @brief Set the INT1 field to a new value. */
+#define DMA_WR_INT_INT1(base, value) (DMA_RMW_INT(base, (DMA_INT_INT1_MASK | DMA_INT_INT0_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT1(value)))
+#define DMA_BWR_INT_INT1(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT2 field. */
+#define DMA_RD_INT_INT2(base) ((DMA_INT_REG(base) & DMA_INT_INT2_MASK) >> DMA_INT_INT2_SHIFT)
+#define DMA_BRD_INT_INT2(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT2_SHIFT))
+
+/*! @brief Set the INT2 field to a new value. */
+#define DMA_WR_INT_INT2(base, value) (DMA_RMW_INT(base, (DMA_INT_INT2_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT2(value)))
+#define DMA_BWR_INT_INT2(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT3 field. */
+#define DMA_RD_INT_INT3(base) ((DMA_INT_REG(base) & DMA_INT_INT3_MASK) >> DMA_INT_INT3_SHIFT)
+#define DMA_BRD_INT_INT3(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT3_SHIFT))
+
+/*! @brief Set the INT3 field to a new value. */
+#define DMA_WR_INT_INT3(base, value) (DMA_RMW_INT(base, (DMA_INT_INT3_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT3(value)))
+#define DMA_BWR_INT_INT3(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT4[4] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT4 field. */
+#define DMA_RD_INT_INT4(base) ((DMA_INT_REG(base) & DMA_INT_INT4_MASK) >> DMA_INT_INT4_SHIFT)
+#define DMA_BRD_INT_INT4(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT4_SHIFT))
+
+/*! @brief Set the INT4 field to a new value. */
+#define DMA_WR_INT_INT4(base, value) (DMA_RMW_INT(base, (DMA_INT_INT4_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT4(value)))
+#define DMA_BWR_INT_INT4(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT5[5] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT5 field. */
+#define DMA_RD_INT_INT5(base) ((DMA_INT_REG(base) & DMA_INT_INT5_MASK) >> DMA_INT_INT5_SHIFT)
+#define DMA_BRD_INT_INT5(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT5_SHIFT))
+
+/*! @brief Set the INT5 field to a new value. */
+#define DMA_WR_INT_INT5(base, value) (DMA_RMW_INT(base, (DMA_INT_INT5_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT5(value)))
+#define DMA_BWR_INT_INT5(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT6[6] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT6 field. */
+#define DMA_RD_INT_INT6(base) ((DMA_INT_REG(base) & DMA_INT_INT6_MASK) >> DMA_INT_INT6_SHIFT)
+#define DMA_BRD_INT_INT6(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT6_SHIFT))
+
+/*! @brief Set the INT6 field to a new value. */
+#define DMA_WR_INT_INT6(base, value) (DMA_RMW_INT(base, (DMA_INT_INT6_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT6(value)))
+#define DMA_BWR_INT_INT6(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT7[7] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT7 field. */
+#define DMA_RD_INT_INT7(base) ((DMA_INT_REG(base) & DMA_INT_INT7_MASK) >> DMA_INT_INT7_SHIFT)
+#define DMA_BRD_INT_INT7(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT7_SHIFT))
+
+/*! @brief Set the INT7 field to a new value. */
+#define DMA_WR_INT_INT7(base, value) (DMA_RMW_INT(base, (DMA_INT_INT7_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT7(value)))
+#define DMA_BWR_INT_INT7(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT8[8] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT8 field. */
+#define DMA_RD_INT_INT8(base) ((DMA_INT_REG(base) & DMA_INT_INT8_MASK) >> DMA_INT_INT8_SHIFT)
+#define DMA_BRD_INT_INT8(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT8_SHIFT))
+
+/*! @brief Set the INT8 field to a new value. */
+#define DMA_WR_INT_INT8(base, value) (DMA_RMW_INT(base, (DMA_INT_INT8_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT8(value)))
+#define DMA_BWR_INT_INT8(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT9[9] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT9 field. */
+#define DMA_RD_INT_INT9(base) ((DMA_INT_REG(base) & DMA_INT_INT9_MASK) >> DMA_INT_INT9_SHIFT)
+#define DMA_BRD_INT_INT9(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT9_SHIFT))
+
+/*! @brief Set the INT9 field to a new value. */
+#define DMA_WR_INT_INT9(base, value) (DMA_RMW_INT(base, (DMA_INT_INT9_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT9(value)))
+#define DMA_BWR_INT_INT9(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT10[10] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT10 field. */
+#define DMA_RD_INT_INT10(base) ((DMA_INT_REG(base) & DMA_INT_INT10_MASK) >> DMA_INT_INT10_SHIFT)
+#define DMA_BRD_INT_INT10(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT10_SHIFT))
+
+/*! @brief Set the INT10 field to a new value. */
+#define DMA_WR_INT_INT10(base, value) (DMA_RMW_INT(base, (DMA_INT_INT10_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT10(value)))
+#define DMA_BWR_INT_INT10(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT11[11] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT11 field. */
+#define DMA_RD_INT_INT11(base) ((DMA_INT_REG(base) & DMA_INT_INT11_MASK) >> DMA_INT_INT11_SHIFT)
+#define DMA_BRD_INT_INT11(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT11_SHIFT))
+
+/*! @brief Set the INT11 field to a new value. */
+#define DMA_WR_INT_INT11(base, value) (DMA_RMW_INT(base, (DMA_INT_INT11_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT11(value)))
+#define DMA_BWR_INT_INT11(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT12[12] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT12 field. */
+#define DMA_RD_INT_INT12(base) ((DMA_INT_REG(base) & DMA_INT_INT12_MASK) >> DMA_INT_INT12_SHIFT)
+#define DMA_BRD_INT_INT12(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT12_SHIFT))
+
+/*! @brief Set the INT12 field to a new value. */
+#define DMA_WR_INT_INT12(base, value) (DMA_RMW_INT(base, (DMA_INT_INT12_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT12(value)))
+#define DMA_BWR_INT_INT12(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT13[13] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT13 field. */
+#define DMA_RD_INT_INT13(base) ((DMA_INT_REG(base) & DMA_INT_INT13_MASK) >> DMA_INT_INT13_SHIFT)
+#define DMA_BRD_INT_INT13(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT13_SHIFT))
+
+/*! @brief Set the INT13 field to a new value. */
+#define DMA_WR_INT_INT13(base, value) (DMA_RMW_INT(base, (DMA_INT_INT13_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT13(value)))
+#define DMA_BWR_INT_INT13(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT14[14] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT14 field. */
+#define DMA_RD_INT_INT14(base) ((DMA_INT_REG(base) & DMA_INT_INT14_MASK) >> DMA_INT_INT14_SHIFT)
+#define DMA_BRD_INT_INT14(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT14_SHIFT))
+
+/*! @brief Set the INT14 field to a new value. */
+#define DMA_WR_INT_INT14(base, value) (DMA_RMW_INT(base, (DMA_INT_INT14_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT15_MASK), DMA_INT_INT14(value)))
+#define DMA_BWR_INT_INT14(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT15[15] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT15 field. */
+#define DMA_RD_INT_INT15(base) ((DMA_INT_REG(base) & DMA_INT_INT15_MASK) >> DMA_INT_INT15_SHIFT)
+#define DMA_BRD_INT_INT15(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT15_SHIFT))
+
+/*! @brief Set the INT15 field to a new value. */
+#define DMA_WR_INT_INT15(base, value) (DMA_RMW_INT(base, (DMA_INT_INT15_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK), DMA_INT_INT15(value)))
+#define DMA_BWR_INT_INT15(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ERR - Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ERR - Error Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERR provides a bit map for the 16 channels, signaling the presence of an
+ * error for each channel. The eDMA engine signals the occurrence of an error
+ * condition by setting the appropriate bit in this register. The outputs of this
+ * register are enabled by the contents of the EEI, and then routed to the
+ * interrupt controller. During the execution of the interrupt-service routine associated
+ * with any DMA errors, it is software's responsibility to clear the appropriate
+ * bit, negating the error-interrupt request. Typically, a write to the CERR in
+ * the interrupt-service routine is used for this purpose. The normal DMA channel
+ * completion indicators (setting the transfer control descriptor DONE flag and
+ * the possible assertion of an interrupt request) are not affected when an error
+ * is detected. The contents of this register can also be polled because a
+ * non-zero value indicates the presence of a channel error regardless of the state of
+ * the EEI. The state of any given channel's error indicators is affected by
+ * writes to this register; it is also affected by writes to the CERR. On writes to
+ * the ERR, a one in any bit position clears the corresponding channel's error
+ * status. A zero in any bit position has no affect on the corresponding channel's
+ * current error status. The CERR is provided so the error indicator for a single
+ * channel can easily be cleared.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ERR register
+ */
+/*@{*/
+#define DMA_RD_ERR(base)         (DMA_ERR_REG(base))
+#define DMA_WR_ERR(base, value)  (DMA_ERR_REG(base) = (value))
+#define DMA_RMW_ERR(base, mask, value) (DMA_WR_ERR(base, (DMA_RD_ERR(base) & ~(mask)) | (value)))
+#define DMA_SET_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) |  (value)))
+#define DMA_CLR_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) & ~(value)))
+#define DMA_TOG_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ERR bitfields
+ */
+
+/*!
+ * @name Register DMA_ERR, field ERR0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR0 field. */
+#define DMA_RD_ERR_ERR0(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR0_MASK) >> DMA_ERR_ERR0_SHIFT)
+#define DMA_BRD_ERR_ERR0(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR0_SHIFT))
+
+/*! @brief Set the ERR0 field to a new value. */
+#define DMA_WR_ERR_ERR0(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR0(value)))
+#define DMA_BWR_ERR_ERR0(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR1 field. */
+#define DMA_RD_ERR_ERR1(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR1_MASK) >> DMA_ERR_ERR1_SHIFT)
+#define DMA_BRD_ERR_ERR1(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR1_SHIFT))
+
+/*! @brief Set the ERR1 field to a new value. */
+#define DMA_WR_ERR_ERR1(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR1_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR1(value)))
+#define DMA_BWR_ERR_ERR1(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR2 field. */
+#define DMA_RD_ERR_ERR2(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR2_MASK) >> DMA_ERR_ERR2_SHIFT)
+#define DMA_BRD_ERR_ERR2(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR2_SHIFT))
+
+/*! @brief Set the ERR2 field to a new value. */
+#define DMA_WR_ERR_ERR2(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR2_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR2(value)))
+#define DMA_BWR_ERR_ERR2(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR3 field. */
+#define DMA_RD_ERR_ERR3(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR3_MASK) >> DMA_ERR_ERR3_SHIFT)
+#define DMA_BRD_ERR_ERR3(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR3_SHIFT))
+
+/*! @brief Set the ERR3 field to a new value. */
+#define DMA_WR_ERR_ERR3(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR3_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR3(value)))
+#define DMA_BWR_ERR_ERR3(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR4[4] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR4 field. */
+#define DMA_RD_ERR_ERR4(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR4_MASK) >> DMA_ERR_ERR4_SHIFT)
+#define DMA_BRD_ERR_ERR4(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR4_SHIFT))
+
+/*! @brief Set the ERR4 field to a new value. */
+#define DMA_WR_ERR_ERR4(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR4_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR4(value)))
+#define DMA_BWR_ERR_ERR4(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR5[5] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR5 field. */
+#define DMA_RD_ERR_ERR5(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR5_MASK) >> DMA_ERR_ERR5_SHIFT)
+#define DMA_BRD_ERR_ERR5(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR5_SHIFT))
+
+/*! @brief Set the ERR5 field to a new value. */
+#define DMA_WR_ERR_ERR5(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR5_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR5(value)))
+#define DMA_BWR_ERR_ERR5(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR6[6] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR6 field. */
+#define DMA_RD_ERR_ERR6(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR6_MASK) >> DMA_ERR_ERR6_SHIFT)
+#define DMA_BRD_ERR_ERR6(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR6_SHIFT))
+
+/*! @brief Set the ERR6 field to a new value. */
+#define DMA_WR_ERR_ERR6(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR6_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR6(value)))
+#define DMA_BWR_ERR_ERR6(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR7[7] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR7 field. */
+#define DMA_RD_ERR_ERR7(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR7_MASK) >> DMA_ERR_ERR7_SHIFT)
+#define DMA_BRD_ERR_ERR7(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR7_SHIFT))
+
+/*! @brief Set the ERR7 field to a new value. */
+#define DMA_WR_ERR_ERR7(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR7_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR7(value)))
+#define DMA_BWR_ERR_ERR7(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR8[8] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR8 field. */
+#define DMA_RD_ERR_ERR8(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR8_MASK) >> DMA_ERR_ERR8_SHIFT)
+#define DMA_BRD_ERR_ERR8(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR8_SHIFT))
+
+/*! @brief Set the ERR8 field to a new value. */
+#define DMA_WR_ERR_ERR8(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR8_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR8(value)))
+#define DMA_BWR_ERR_ERR8(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR9[9] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR9 field. */
+#define DMA_RD_ERR_ERR9(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR9_MASK) >> DMA_ERR_ERR9_SHIFT)
+#define DMA_BRD_ERR_ERR9(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR9_SHIFT))
+
+/*! @brief Set the ERR9 field to a new value. */
+#define DMA_WR_ERR_ERR9(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR9_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR9(value)))
+#define DMA_BWR_ERR_ERR9(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR10[10] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR10 field. */
+#define DMA_RD_ERR_ERR10(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR10_MASK) >> DMA_ERR_ERR10_SHIFT)
+#define DMA_BRD_ERR_ERR10(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR10_SHIFT))
+
+/*! @brief Set the ERR10 field to a new value. */
+#define DMA_WR_ERR_ERR10(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR10_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR10(value)))
+#define DMA_BWR_ERR_ERR10(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR11[11] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR11 field. */
+#define DMA_RD_ERR_ERR11(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR11_MASK) >> DMA_ERR_ERR11_SHIFT)
+#define DMA_BRD_ERR_ERR11(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR11_SHIFT))
+
+/*! @brief Set the ERR11 field to a new value. */
+#define DMA_WR_ERR_ERR11(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR11_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR11(value)))
+#define DMA_BWR_ERR_ERR11(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR12[12] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR12 field. */
+#define DMA_RD_ERR_ERR12(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR12_MASK) >> DMA_ERR_ERR12_SHIFT)
+#define DMA_BRD_ERR_ERR12(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR12_SHIFT))
+
+/*! @brief Set the ERR12 field to a new value. */
+#define DMA_WR_ERR_ERR12(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR12_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR12(value)))
+#define DMA_BWR_ERR_ERR12(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR13[13] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR13 field. */
+#define DMA_RD_ERR_ERR13(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR13_MASK) >> DMA_ERR_ERR13_SHIFT)
+#define DMA_BRD_ERR_ERR13(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR13_SHIFT))
+
+/*! @brief Set the ERR13 field to a new value. */
+#define DMA_WR_ERR_ERR13(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR13_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR13(value)))
+#define DMA_BWR_ERR_ERR13(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR14[14] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR14 field. */
+#define DMA_RD_ERR_ERR14(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR14_MASK) >> DMA_ERR_ERR14_SHIFT)
+#define DMA_BRD_ERR_ERR14(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR14_SHIFT))
+
+/*! @brief Set the ERR14 field to a new value. */
+#define DMA_WR_ERR_ERR14(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR14_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR14(value)))
+#define DMA_BWR_ERR_ERR14(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR15[15] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR15 field. */
+#define DMA_RD_ERR_ERR15(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR15_MASK) >> DMA_ERR_ERR15_SHIFT)
+#define DMA_BRD_ERR_ERR15(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR15_SHIFT))
+
+/*! @brief Set the ERR15 field to a new value. */
+#define DMA_WR_ERR_ERR15(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR15_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK), DMA_ERR_ERR15(value)))
+#define DMA_BWR_ERR_ERR15(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_HRS - Hardware Request Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_HRS - Hardware Request Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The HRS register provides a bit map for the DMA channels, signaling the
+ * presence of a hardware request for each channel. The hardware request status bits
+ * reflect the current state of the register and qualified (via the ERQ fields)
+ * DMA request signals as seen by the DMA's arbitration logic. This view into the
+ * hardware request signals may be used for debug purposes. These bits reflect the
+ * state of the request as seen by the arbitration logic. Therefore, this status
+ * is affected by the ERQ bits.
+ */
+/*!
+ * @name Constants and macros for entire DMA_HRS register
+ */
+/*@{*/
+#define DMA_RD_HRS(base)         (DMA_HRS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_HRS bitfields
+ */
+
+/*!
+ * @name Register DMA_HRS, field HRS0[0] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 0 is not present
+ * - 0b1 - A hardware service request for channel 0 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS0 field. */
+#define DMA_RD_HRS_HRS0(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS0_MASK) >> DMA_HRS_HRS0_SHIFT)
+#define DMA_BRD_HRS_HRS0(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS1[1] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 1 is not present
+ * - 0b1 - A hardware service request for channel 1 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS1 field. */
+#define DMA_RD_HRS_HRS1(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS1_MASK) >> DMA_HRS_HRS1_SHIFT)
+#define DMA_BRD_HRS_HRS1(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS2[2] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 2 is not present
+ * - 0b1 - A hardware service request for channel 2 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS2 field. */
+#define DMA_RD_HRS_HRS2(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS2_MASK) >> DMA_HRS_HRS2_SHIFT)
+#define DMA_BRD_HRS_HRS2(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS2_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS3[3] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 3 is not present
+ * - 0b1 - A hardware service request for channel 3 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS3 field. */
+#define DMA_RD_HRS_HRS3(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS3_MASK) >> DMA_HRS_HRS3_SHIFT)
+#define DMA_BRD_HRS_HRS3(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS3_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS4[4] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 4 is not present
+ * - 0b1 - A hardware service request for channel 4 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS4 field. */
+#define DMA_RD_HRS_HRS4(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS4_MASK) >> DMA_HRS_HRS4_SHIFT)
+#define DMA_BRD_HRS_HRS4(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS4_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS5[5] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 5 is not present
+ * - 0b1 - A hardware service request for channel 5 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS5 field. */
+#define DMA_RD_HRS_HRS5(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS5_MASK) >> DMA_HRS_HRS5_SHIFT)
+#define DMA_BRD_HRS_HRS5(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS5_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS6[6] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 6 is not present
+ * - 0b1 - A hardware service request for channel 6 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS6 field. */
+#define DMA_RD_HRS_HRS6(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS6_MASK) >> DMA_HRS_HRS6_SHIFT)
+#define DMA_BRD_HRS_HRS6(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS6_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS7[7] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 7 is not present
+ * - 0b1 - A hardware service request for channel 7 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS7 field. */
+#define DMA_RD_HRS_HRS7(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS7_MASK) >> DMA_HRS_HRS7_SHIFT)
+#define DMA_BRD_HRS_HRS7(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS7_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS8[8] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 8 is not present
+ * - 0b1 - A hardware service request for channel 8 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS8 field. */
+#define DMA_RD_HRS_HRS8(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS8_MASK) >> DMA_HRS_HRS8_SHIFT)
+#define DMA_BRD_HRS_HRS8(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS8_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS9[9] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 9 is not present
+ * - 0b1 - A hardware service request for channel 9 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS9 field. */
+#define DMA_RD_HRS_HRS9(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS9_MASK) >> DMA_HRS_HRS9_SHIFT)
+#define DMA_BRD_HRS_HRS9(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS9_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS10[10] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 10 is not present
+ * - 0b1 - A hardware service request for channel 10 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS10 field. */
+#define DMA_RD_HRS_HRS10(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS10_MASK) >> DMA_HRS_HRS10_SHIFT)
+#define DMA_BRD_HRS_HRS10(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS10_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS11[11] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 11 is not present
+ * - 0b1 - A hardware service request for channel 11 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS11 field. */
+#define DMA_RD_HRS_HRS11(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS11_MASK) >> DMA_HRS_HRS11_SHIFT)
+#define DMA_BRD_HRS_HRS11(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS11_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS12[12] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 12 is not present
+ * - 0b1 - A hardware service request for channel 12 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS12 field. */
+#define DMA_RD_HRS_HRS12(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS12_MASK) >> DMA_HRS_HRS12_SHIFT)
+#define DMA_BRD_HRS_HRS12(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS12_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS13[13] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 13 is not present
+ * - 0b1 - A hardware service request for channel 13 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS13 field. */
+#define DMA_RD_HRS_HRS13(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS13_MASK) >> DMA_HRS_HRS13_SHIFT)
+#define DMA_BRD_HRS_HRS13(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS13_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS14[14] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 14 is not present
+ * - 0b1 - A hardware service request for channel 14 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS14 field. */
+#define DMA_RD_HRS_HRS14(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS14_MASK) >> DMA_HRS_HRS14_SHIFT)
+#define DMA_BRD_HRS_HRS14(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS14_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS15[15] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 15 is not present
+ * - 0b1 - A hardware service request for channel 15 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS15 field. */
+#define DMA_RD_HRS_HRS15(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS15_MASK) >> DMA_HRS_HRS15_SHIFT)
+#define DMA_BRD_HRS_HRS15(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS15_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI3 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI3 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI3 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI3(base)     (DMA_DCHPRI3_REG(base))
+#define DMA_WR_DCHPRI3(base, value) (DMA_DCHPRI3_REG(base) = (value))
+#define DMA_RMW_DCHPRI3(base, mask, value) (DMA_WR_DCHPRI3(base, (DMA_RD_DCHPRI3(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) |  (value)))
+#define DMA_CLR_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) & ~(value)))
+#define DMA_TOG_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI3 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI3, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_CHPRI field. */
+#define DMA_RD_DCHPRI3_CHPRI(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_CHPRI_MASK) >> DMA_DCHPRI3_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI3_CHPRI(base) (DMA_RD_DCHPRI3_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI3_CHPRI(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_CHPRI_MASK, DMA_DCHPRI3_CHPRI(value)))
+#define DMA_BWR_DCHPRI3_CHPRI(base, value) (DMA_WR_DCHPRI3_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI3, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_DPA field. */
+#define DMA_RD_DCHPRI3_DPA(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_DPA_MASK) >> DMA_DCHPRI3_DPA_SHIFT)
+#define DMA_BRD_DCHPRI3_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI3_DPA(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_DPA_MASK, DMA_DCHPRI3_DPA(value)))
+#define DMA_BWR_DCHPRI3_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI3, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_ECP field. */
+#define DMA_RD_DCHPRI3_ECP(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_ECP_MASK) >> DMA_DCHPRI3_ECP_SHIFT)
+#define DMA_BRD_DCHPRI3_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI3_ECP(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_ECP_MASK, DMA_DCHPRI3_ECP(value)))
+#define DMA_BWR_DCHPRI3_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI2 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI2 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI2 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI2(base)     (DMA_DCHPRI2_REG(base))
+#define DMA_WR_DCHPRI2(base, value) (DMA_DCHPRI2_REG(base) = (value))
+#define DMA_RMW_DCHPRI2(base, mask, value) (DMA_WR_DCHPRI2(base, (DMA_RD_DCHPRI2(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) |  (value)))
+#define DMA_CLR_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) & ~(value)))
+#define DMA_TOG_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI2 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI2, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_CHPRI field. */
+#define DMA_RD_DCHPRI2_CHPRI(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_CHPRI_MASK) >> DMA_DCHPRI2_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI2_CHPRI(base) (DMA_RD_DCHPRI2_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI2_CHPRI(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_CHPRI_MASK, DMA_DCHPRI2_CHPRI(value)))
+#define DMA_BWR_DCHPRI2_CHPRI(base, value) (DMA_WR_DCHPRI2_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI2, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_DPA field. */
+#define DMA_RD_DCHPRI2_DPA(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_DPA_MASK) >> DMA_DCHPRI2_DPA_SHIFT)
+#define DMA_BRD_DCHPRI2_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI2_DPA(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_DPA_MASK, DMA_DCHPRI2_DPA(value)))
+#define DMA_BWR_DCHPRI2_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI2, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_ECP field. */
+#define DMA_RD_DCHPRI2_ECP(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_ECP_MASK) >> DMA_DCHPRI2_ECP_SHIFT)
+#define DMA_BRD_DCHPRI2_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI2_ECP(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_ECP_MASK, DMA_DCHPRI2_ECP(value)))
+#define DMA_BWR_DCHPRI2_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI1 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI1 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI1 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI1(base)     (DMA_DCHPRI1_REG(base))
+#define DMA_WR_DCHPRI1(base, value) (DMA_DCHPRI1_REG(base) = (value))
+#define DMA_RMW_DCHPRI1(base, mask, value) (DMA_WR_DCHPRI1(base, (DMA_RD_DCHPRI1(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) |  (value)))
+#define DMA_CLR_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) & ~(value)))
+#define DMA_TOG_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI1 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI1, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_CHPRI field. */
+#define DMA_RD_DCHPRI1_CHPRI(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_CHPRI_MASK) >> DMA_DCHPRI1_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI1_CHPRI(base) (DMA_RD_DCHPRI1_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI1_CHPRI(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_CHPRI_MASK, DMA_DCHPRI1_CHPRI(value)))
+#define DMA_BWR_DCHPRI1_CHPRI(base, value) (DMA_WR_DCHPRI1_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI1, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_DPA field. */
+#define DMA_RD_DCHPRI1_DPA(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_DPA_MASK) >> DMA_DCHPRI1_DPA_SHIFT)
+#define DMA_BRD_DCHPRI1_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI1_DPA(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_DPA_MASK, DMA_DCHPRI1_DPA(value)))
+#define DMA_BWR_DCHPRI1_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI1, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_ECP field. */
+#define DMA_RD_DCHPRI1_ECP(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_ECP_MASK) >> DMA_DCHPRI1_ECP_SHIFT)
+#define DMA_BRD_DCHPRI1_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI1_ECP(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_ECP_MASK, DMA_DCHPRI1_ECP(value)))
+#define DMA_BWR_DCHPRI1_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI0 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI0 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI0 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI0(base)     (DMA_DCHPRI0_REG(base))
+#define DMA_WR_DCHPRI0(base, value) (DMA_DCHPRI0_REG(base) = (value))
+#define DMA_RMW_DCHPRI0(base, mask, value) (DMA_WR_DCHPRI0(base, (DMA_RD_DCHPRI0(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) |  (value)))
+#define DMA_CLR_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) & ~(value)))
+#define DMA_TOG_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI0 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI0, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_CHPRI field. */
+#define DMA_RD_DCHPRI0_CHPRI(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_CHPRI_MASK) >> DMA_DCHPRI0_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI0_CHPRI(base) (DMA_RD_DCHPRI0_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI0_CHPRI(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_CHPRI_MASK, DMA_DCHPRI0_CHPRI(value)))
+#define DMA_BWR_DCHPRI0_CHPRI(base, value) (DMA_WR_DCHPRI0_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI0, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_DPA field. */
+#define DMA_RD_DCHPRI0_DPA(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_DPA_MASK) >> DMA_DCHPRI0_DPA_SHIFT)
+#define DMA_BRD_DCHPRI0_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI0_DPA(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_DPA_MASK, DMA_DCHPRI0_DPA(value)))
+#define DMA_BWR_DCHPRI0_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI0, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_ECP field. */
+#define DMA_RD_DCHPRI0_ECP(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_ECP_MASK) >> DMA_DCHPRI0_ECP_SHIFT)
+#define DMA_BRD_DCHPRI0_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI0_ECP(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_ECP_MASK, DMA_DCHPRI0_ECP(value)))
+#define DMA_BWR_DCHPRI0_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI7 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI7 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI7 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI7(base)     (DMA_DCHPRI7_REG(base))
+#define DMA_WR_DCHPRI7(base, value) (DMA_DCHPRI7_REG(base) = (value))
+#define DMA_RMW_DCHPRI7(base, mask, value) (DMA_WR_DCHPRI7(base, (DMA_RD_DCHPRI7(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) |  (value)))
+#define DMA_CLR_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) & ~(value)))
+#define DMA_TOG_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI7 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI7, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_CHPRI field. */
+#define DMA_RD_DCHPRI7_CHPRI(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_CHPRI_MASK) >> DMA_DCHPRI7_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI7_CHPRI(base) (DMA_RD_DCHPRI7_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI7_CHPRI(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_CHPRI_MASK, DMA_DCHPRI7_CHPRI(value)))
+#define DMA_BWR_DCHPRI7_CHPRI(base, value) (DMA_WR_DCHPRI7_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI7, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_DPA field. */
+#define DMA_RD_DCHPRI7_DPA(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_DPA_MASK) >> DMA_DCHPRI7_DPA_SHIFT)
+#define DMA_BRD_DCHPRI7_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI7_DPA(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_DPA_MASK, DMA_DCHPRI7_DPA(value)))
+#define DMA_BWR_DCHPRI7_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI7, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_ECP field. */
+#define DMA_RD_DCHPRI7_ECP(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_ECP_MASK) >> DMA_DCHPRI7_ECP_SHIFT)
+#define DMA_BRD_DCHPRI7_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI7_ECP(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_ECP_MASK, DMA_DCHPRI7_ECP(value)))
+#define DMA_BWR_DCHPRI7_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI6 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI6 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI6 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI6(base)     (DMA_DCHPRI6_REG(base))
+#define DMA_WR_DCHPRI6(base, value) (DMA_DCHPRI6_REG(base) = (value))
+#define DMA_RMW_DCHPRI6(base, mask, value) (DMA_WR_DCHPRI6(base, (DMA_RD_DCHPRI6(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) |  (value)))
+#define DMA_CLR_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) & ~(value)))
+#define DMA_TOG_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI6 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI6, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_CHPRI field. */
+#define DMA_RD_DCHPRI6_CHPRI(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_CHPRI_MASK) >> DMA_DCHPRI6_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI6_CHPRI(base) (DMA_RD_DCHPRI6_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI6_CHPRI(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_CHPRI_MASK, DMA_DCHPRI6_CHPRI(value)))
+#define DMA_BWR_DCHPRI6_CHPRI(base, value) (DMA_WR_DCHPRI6_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI6, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_DPA field. */
+#define DMA_RD_DCHPRI6_DPA(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_DPA_MASK) >> DMA_DCHPRI6_DPA_SHIFT)
+#define DMA_BRD_DCHPRI6_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI6_DPA(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_DPA_MASK, DMA_DCHPRI6_DPA(value)))
+#define DMA_BWR_DCHPRI6_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI6, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_ECP field. */
+#define DMA_RD_DCHPRI6_ECP(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_ECP_MASK) >> DMA_DCHPRI6_ECP_SHIFT)
+#define DMA_BRD_DCHPRI6_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI6_ECP(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_ECP_MASK, DMA_DCHPRI6_ECP(value)))
+#define DMA_BWR_DCHPRI6_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI5 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI5 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI5 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI5(base)     (DMA_DCHPRI5_REG(base))
+#define DMA_WR_DCHPRI5(base, value) (DMA_DCHPRI5_REG(base) = (value))
+#define DMA_RMW_DCHPRI5(base, mask, value) (DMA_WR_DCHPRI5(base, (DMA_RD_DCHPRI5(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) |  (value)))
+#define DMA_CLR_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) & ~(value)))
+#define DMA_TOG_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI5 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI5, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_CHPRI field. */
+#define DMA_RD_DCHPRI5_CHPRI(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_CHPRI_MASK) >> DMA_DCHPRI5_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI5_CHPRI(base) (DMA_RD_DCHPRI5_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI5_CHPRI(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_CHPRI_MASK, DMA_DCHPRI5_CHPRI(value)))
+#define DMA_BWR_DCHPRI5_CHPRI(base, value) (DMA_WR_DCHPRI5_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI5, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_DPA field. */
+#define DMA_RD_DCHPRI5_DPA(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_DPA_MASK) >> DMA_DCHPRI5_DPA_SHIFT)
+#define DMA_BRD_DCHPRI5_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI5_DPA(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_DPA_MASK, DMA_DCHPRI5_DPA(value)))
+#define DMA_BWR_DCHPRI5_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI5, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_ECP field. */
+#define DMA_RD_DCHPRI5_ECP(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_ECP_MASK) >> DMA_DCHPRI5_ECP_SHIFT)
+#define DMA_BRD_DCHPRI5_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI5_ECP(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_ECP_MASK, DMA_DCHPRI5_ECP(value)))
+#define DMA_BWR_DCHPRI5_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI4 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI4 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI4 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI4(base)     (DMA_DCHPRI4_REG(base))
+#define DMA_WR_DCHPRI4(base, value) (DMA_DCHPRI4_REG(base) = (value))
+#define DMA_RMW_DCHPRI4(base, mask, value) (DMA_WR_DCHPRI4(base, (DMA_RD_DCHPRI4(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) |  (value)))
+#define DMA_CLR_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) & ~(value)))
+#define DMA_TOG_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI4 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI4, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_CHPRI field. */
+#define DMA_RD_DCHPRI4_CHPRI(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_CHPRI_MASK) >> DMA_DCHPRI4_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI4_CHPRI(base) (DMA_RD_DCHPRI4_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI4_CHPRI(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_CHPRI_MASK, DMA_DCHPRI4_CHPRI(value)))
+#define DMA_BWR_DCHPRI4_CHPRI(base, value) (DMA_WR_DCHPRI4_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI4, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_DPA field. */
+#define DMA_RD_DCHPRI4_DPA(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_DPA_MASK) >> DMA_DCHPRI4_DPA_SHIFT)
+#define DMA_BRD_DCHPRI4_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI4_DPA(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_DPA_MASK, DMA_DCHPRI4_DPA(value)))
+#define DMA_BWR_DCHPRI4_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI4, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_ECP field. */
+#define DMA_RD_DCHPRI4_ECP(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_ECP_MASK) >> DMA_DCHPRI4_ECP_SHIFT)
+#define DMA_BRD_DCHPRI4_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI4_ECP(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_ECP_MASK, DMA_DCHPRI4_ECP(value)))
+#define DMA_BWR_DCHPRI4_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI11 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI11 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI11 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI11(base)    (DMA_DCHPRI11_REG(base))
+#define DMA_WR_DCHPRI11(base, value) (DMA_DCHPRI11_REG(base) = (value))
+#define DMA_RMW_DCHPRI11(base, mask, value) (DMA_WR_DCHPRI11(base, (DMA_RD_DCHPRI11(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) |  (value)))
+#define DMA_CLR_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) & ~(value)))
+#define DMA_TOG_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI11 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI11, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_CHPRI field. */
+#define DMA_RD_DCHPRI11_CHPRI(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_CHPRI_MASK) >> DMA_DCHPRI11_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI11_CHPRI(base) (DMA_RD_DCHPRI11_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI11_CHPRI(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_CHPRI_MASK, DMA_DCHPRI11_CHPRI(value)))
+#define DMA_BWR_DCHPRI11_CHPRI(base, value) (DMA_WR_DCHPRI11_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI11, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_DPA field. */
+#define DMA_RD_DCHPRI11_DPA(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_DPA_MASK) >> DMA_DCHPRI11_DPA_SHIFT)
+#define DMA_BRD_DCHPRI11_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI11_DPA(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_DPA_MASK, DMA_DCHPRI11_DPA(value)))
+#define DMA_BWR_DCHPRI11_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI11, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_ECP field. */
+#define DMA_RD_DCHPRI11_ECP(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_ECP_MASK) >> DMA_DCHPRI11_ECP_SHIFT)
+#define DMA_BRD_DCHPRI11_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI11_ECP(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_ECP_MASK, DMA_DCHPRI11_ECP(value)))
+#define DMA_BWR_DCHPRI11_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI10 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI10 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI10 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI10(base)    (DMA_DCHPRI10_REG(base))
+#define DMA_WR_DCHPRI10(base, value) (DMA_DCHPRI10_REG(base) = (value))
+#define DMA_RMW_DCHPRI10(base, mask, value) (DMA_WR_DCHPRI10(base, (DMA_RD_DCHPRI10(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) |  (value)))
+#define DMA_CLR_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) & ~(value)))
+#define DMA_TOG_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI10 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI10, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_CHPRI field. */
+#define DMA_RD_DCHPRI10_CHPRI(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_CHPRI_MASK) >> DMA_DCHPRI10_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI10_CHPRI(base) (DMA_RD_DCHPRI10_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI10_CHPRI(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_CHPRI_MASK, DMA_DCHPRI10_CHPRI(value)))
+#define DMA_BWR_DCHPRI10_CHPRI(base, value) (DMA_WR_DCHPRI10_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI10, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_DPA field. */
+#define DMA_RD_DCHPRI10_DPA(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_DPA_MASK) >> DMA_DCHPRI10_DPA_SHIFT)
+#define DMA_BRD_DCHPRI10_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI10_DPA(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_DPA_MASK, DMA_DCHPRI10_DPA(value)))
+#define DMA_BWR_DCHPRI10_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI10, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_ECP field. */
+#define DMA_RD_DCHPRI10_ECP(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_ECP_MASK) >> DMA_DCHPRI10_ECP_SHIFT)
+#define DMA_BRD_DCHPRI10_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI10_ECP(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_ECP_MASK, DMA_DCHPRI10_ECP(value)))
+#define DMA_BWR_DCHPRI10_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI9 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI9 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI9 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI9(base)     (DMA_DCHPRI9_REG(base))
+#define DMA_WR_DCHPRI9(base, value) (DMA_DCHPRI9_REG(base) = (value))
+#define DMA_RMW_DCHPRI9(base, mask, value) (DMA_WR_DCHPRI9(base, (DMA_RD_DCHPRI9(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) |  (value)))
+#define DMA_CLR_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) & ~(value)))
+#define DMA_TOG_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI9 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI9, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_CHPRI field. */
+#define DMA_RD_DCHPRI9_CHPRI(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_CHPRI_MASK) >> DMA_DCHPRI9_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI9_CHPRI(base) (DMA_RD_DCHPRI9_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI9_CHPRI(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_CHPRI_MASK, DMA_DCHPRI9_CHPRI(value)))
+#define DMA_BWR_DCHPRI9_CHPRI(base, value) (DMA_WR_DCHPRI9_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI9, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_DPA field. */
+#define DMA_RD_DCHPRI9_DPA(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_DPA_MASK) >> DMA_DCHPRI9_DPA_SHIFT)
+#define DMA_BRD_DCHPRI9_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI9_DPA(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_DPA_MASK, DMA_DCHPRI9_DPA(value)))
+#define DMA_BWR_DCHPRI9_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI9, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_ECP field. */
+#define DMA_RD_DCHPRI9_ECP(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_ECP_MASK) >> DMA_DCHPRI9_ECP_SHIFT)
+#define DMA_BRD_DCHPRI9_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI9_ECP(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_ECP_MASK, DMA_DCHPRI9_ECP(value)))
+#define DMA_BWR_DCHPRI9_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI8 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI8 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI8 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI8(base)     (DMA_DCHPRI8_REG(base))
+#define DMA_WR_DCHPRI8(base, value) (DMA_DCHPRI8_REG(base) = (value))
+#define DMA_RMW_DCHPRI8(base, mask, value) (DMA_WR_DCHPRI8(base, (DMA_RD_DCHPRI8(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) |  (value)))
+#define DMA_CLR_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) & ~(value)))
+#define DMA_TOG_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI8 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI8, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_CHPRI field. */
+#define DMA_RD_DCHPRI8_CHPRI(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_CHPRI_MASK) >> DMA_DCHPRI8_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI8_CHPRI(base) (DMA_RD_DCHPRI8_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI8_CHPRI(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_CHPRI_MASK, DMA_DCHPRI8_CHPRI(value)))
+#define DMA_BWR_DCHPRI8_CHPRI(base, value) (DMA_WR_DCHPRI8_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI8, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_DPA field. */
+#define DMA_RD_DCHPRI8_DPA(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_DPA_MASK) >> DMA_DCHPRI8_DPA_SHIFT)
+#define DMA_BRD_DCHPRI8_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI8_DPA(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_DPA_MASK, DMA_DCHPRI8_DPA(value)))
+#define DMA_BWR_DCHPRI8_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI8, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_ECP field. */
+#define DMA_RD_DCHPRI8_ECP(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_ECP_MASK) >> DMA_DCHPRI8_ECP_SHIFT)
+#define DMA_BRD_DCHPRI8_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI8_ECP(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_ECP_MASK, DMA_DCHPRI8_ECP(value)))
+#define DMA_BWR_DCHPRI8_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI15 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI15 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI15 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI15(base)    (DMA_DCHPRI15_REG(base))
+#define DMA_WR_DCHPRI15(base, value) (DMA_DCHPRI15_REG(base) = (value))
+#define DMA_RMW_DCHPRI15(base, mask, value) (DMA_WR_DCHPRI15(base, (DMA_RD_DCHPRI15(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) |  (value)))
+#define DMA_CLR_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) & ~(value)))
+#define DMA_TOG_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI15 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI15, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_CHPRI field. */
+#define DMA_RD_DCHPRI15_CHPRI(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_CHPRI_MASK) >> DMA_DCHPRI15_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI15_CHPRI(base) (DMA_RD_DCHPRI15_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI15_CHPRI(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_CHPRI_MASK, DMA_DCHPRI15_CHPRI(value)))
+#define DMA_BWR_DCHPRI15_CHPRI(base, value) (DMA_WR_DCHPRI15_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI15, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_DPA field. */
+#define DMA_RD_DCHPRI15_DPA(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_DPA_MASK) >> DMA_DCHPRI15_DPA_SHIFT)
+#define DMA_BRD_DCHPRI15_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI15_DPA(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_DPA_MASK, DMA_DCHPRI15_DPA(value)))
+#define DMA_BWR_DCHPRI15_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI15, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_ECP field. */
+#define DMA_RD_DCHPRI15_ECP(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_ECP_MASK) >> DMA_DCHPRI15_ECP_SHIFT)
+#define DMA_BRD_DCHPRI15_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI15_ECP(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_ECP_MASK, DMA_DCHPRI15_ECP(value)))
+#define DMA_BWR_DCHPRI15_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI14 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI14 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI14 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI14(base)    (DMA_DCHPRI14_REG(base))
+#define DMA_WR_DCHPRI14(base, value) (DMA_DCHPRI14_REG(base) = (value))
+#define DMA_RMW_DCHPRI14(base, mask, value) (DMA_WR_DCHPRI14(base, (DMA_RD_DCHPRI14(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) |  (value)))
+#define DMA_CLR_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) & ~(value)))
+#define DMA_TOG_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI14 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI14, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_CHPRI field. */
+#define DMA_RD_DCHPRI14_CHPRI(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_CHPRI_MASK) >> DMA_DCHPRI14_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI14_CHPRI(base) (DMA_RD_DCHPRI14_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI14_CHPRI(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_CHPRI_MASK, DMA_DCHPRI14_CHPRI(value)))
+#define DMA_BWR_DCHPRI14_CHPRI(base, value) (DMA_WR_DCHPRI14_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI14, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_DPA field. */
+#define DMA_RD_DCHPRI14_DPA(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_DPA_MASK) >> DMA_DCHPRI14_DPA_SHIFT)
+#define DMA_BRD_DCHPRI14_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI14_DPA(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_DPA_MASK, DMA_DCHPRI14_DPA(value)))
+#define DMA_BWR_DCHPRI14_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI14, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_ECP field. */
+#define DMA_RD_DCHPRI14_ECP(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_ECP_MASK) >> DMA_DCHPRI14_ECP_SHIFT)
+#define DMA_BRD_DCHPRI14_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI14_ECP(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_ECP_MASK, DMA_DCHPRI14_ECP(value)))
+#define DMA_BWR_DCHPRI14_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI13 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI13 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI13 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI13(base)    (DMA_DCHPRI13_REG(base))
+#define DMA_WR_DCHPRI13(base, value) (DMA_DCHPRI13_REG(base) = (value))
+#define DMA_RMW_DCHPRI13(base, mask, value) (DMA_WR_DCHPRI13(base, (DMA_RD_DCHPRI13(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) |  (value)))
+#define DMA_CLR_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) & ~(value)))
+#define DMA_TOG_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI13 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI13, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_CHPRI field. */
+#define DMA_RD_DCHPRI13_CHPRI(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_CHPRI_MASK) >> DMA_DCHPRI13_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI13_CHPRI(base) (DMA_RD_DCHPRI13_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI13_CHPRI(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_CHPRI_MASK, DMA_DCHPRI13_CHPRI(value)))
+#define DMA_BWR_DCHPRI13_CHPRI(base, value) (DMA_WR_DCHPRI13_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI13, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_DPA field. */
+#define DMA_RD_DCHPRI13_DPA(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_DPA_MASK) >> DMA_DCHPRI13_DPA_SHIFT)
+#define DMA_BRD_DCHPRI13_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI13_DPA(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_DPA_MASK, DMA_DCHPRI13_DPA(value)))
+#define DMA_BWR_DCHPRI13_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI13, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_ECP field. */
+#define DMA_RD_DCHPRI13_ECP(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_ECP_MASK) >> DMA_DCHPRI13_ECP_SHIFT)
+#define DMA_BRD_DCHPRI13_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI13_ECP(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_ECP_MASK, DMA_DCHPRI13_ECP(value)))
+#define DMA_BWR_DCHPRI13_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI12 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI12 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI12 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI12(base)    (DMA_DCHPRI12_REG(base))
+#define DMA_WR_DCHPRI12(base, value) (DMA_DCHPRI12_REG(base) = (value))
+#define DMA_RMW_DCHPRI12(base, mask, value) (DMA_WR_DCHPRI12(base, (DMA_RD_DCHPRI12(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) |  (value)))
+#define DMA_CLR_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) & ~(value)))
+#define DMA_TOG_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI12 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI12, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_CHPRI field. */
+#define DMA_RD_DCHPRI12_CHPRI(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_CHPRI_MASK) >> DMA_DCHPRI12_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI12_CHPRI(base) (DMA_RD_DCHPRI12_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI12_CHPRI(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_CHPRI_MASK, DMA_DCHPRI12_CHPRI(value)))
+#define DMA_BWR_DCHPRI12_CHPRI(base, value) (DMA_WR_DCHPRI12_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI12, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_DPA field. */
+#define DMA_RD_DCHPRI12_DPA(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_DPA_MASK) >> DMA_DCHPRI12_DPA_SHIFT)
+#define DMA_BRD_DCHPRI12_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI12_DPA(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_DPA_MASK, DMA_DCHPRI12_DPA(value)))
+#define DMA_BWR_DCHPRI12_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI12, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_ECP field. */
+#define DMA_RD_DCHPRI12_ECP(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_ECP_MASK) >> DMA_DCHPRI12_ECP_SHIFT)
+#define DMA_BRD_DCHPRI12_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI12_ECP(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_ECP_MASK, DMA_DCHPRI12_ECP(value)))
+#define DMA_BWR_DCHPRI12_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SADDR - TCD Source Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SADDR - TCD Source Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SADDR register
+ */
+/*@{*/
+#define DMA_RD_SADDR(base, index) (DMA_SADDR_REG(base, index))
+#define DMA_WR_SADDR(base, index, value) (DMA_SADDR_REG(base, index) = (value))
+#define DMA_RMW_SADDR(base, index, mask, value) (DMA_WR_SADDR(base, index, (DMA_RD_SADDR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) |  (value)))
+#define DMA_CLR_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) & ~(value)))
+#define DMA_TOG_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SOFF - TCD Signed Source Address Offset
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SOFF - TCD Signed Source Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SOFF register
+ */
+/*@{*/
+#define DMA_RD_SOFF(base, index) (DMA_SOFF_REG(base, index))
+#define DMA_WR_SOFF(base, index, value) (DMA_SOFF_REG(base, index) = (value))
+#define DMA_RMW_SOFF(base, index, mask, value) (DMA_WR_SOFF(base, index, (DMA_RD_SOFF(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) |  (value)))
+#define DMA_CLR_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) & ~(value)))
+#define DMA_TOG_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ATTR - TCD Transfer Attributes
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ATTR - TCD Transfer Attributes (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_ATTR register
+ */
+/*@{*/
+#define DMA_RD_ATTR(base, index) (DMA_ATTR_REG(base, index))
+#define DMA_WR_ATTR(base, index, value) (DMA_ATTR_REG(base, index) = (value))
+#define DMA_RMW_ATTR(base, index, mask, value) (DMA_WR_ATTR(base, index, (DMA_RD_ATTR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) |  (value)))
+#define DMA_CLR_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) & ~(value)))
+#define DMA_TOG_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ATTR bitfields
+ */
+
+/*!
+ * @name Register DMA_ATTR, field DSIZE[2:0] (RW)
+ *
+ * See the SSIZE definition
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_DSIZE field. */
+#define DMA_RD_ATTR_DSIZE(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_DSIZE_MASK) >> DMA_ATTR_DSIZE_SHIFT)
+#define DMA_BRD_ATTR_DSIZE(base, index) (DMA_RD_ATTR_DSIZE(base, index))
+
+/*! @brief Set the DSIZE field to a new value. */
+#define DMA_WR_ATTR_DSIZE(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_DSIZE_MASK, DMA_ATTR_DSIZE(value)))
+#define DMA_BWR_ATTR_DSIZE(base, index, value) (DMA_WR_ATTR_DSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field DMOD[7:3] (RW)
+ *
+ * See the SMOD definition
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_DMOD field. */
+#define DMA_RD_ATTR_DMOD(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_DMOD_MASK) >> DMA_ATTR_DMOD_SHIFT)
+#define DMA_BRD_ATTR_DMOD(base, index) (DMA_RD_ATTR_DMOD(base, index))
+
+/*! @brief Set the DMOD field to a new value. */
+#define DMA_WR_ATTR_DMOD(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_DMOD_MASK, DMA_ATTR_DMOD(value)))
+#define DMA_BWR_ATTR_DMOD(base, index, value) (DMA_WR_ATTR_DMOD(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field SSIZE[10:8] (RW)
+ *
+ * The attempted use of a Reserved encoding causes a configuration error.
+ *
+ * Values:
+ * - 0b000 - 8-bit
+ * - 0b001 - 16-bit
+ * - 0b010 - 32-bit
+ * - 0b011 - Reserved
+ * - 0b100 - 16-byte
+ * - 0b101 - 32-byte
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_SSIZE field. */
+#define DMA_RD_ATTR_SSIZE(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_SSIZE_MASK) >> DMA_ATTR_SSIZE_SHIFT)
+#define DMA_BRD_ATTR_SSIZE(base, index) (DMA_RD_ATTR_SSIZE(base, index))
+
+/*! @brief Set the SSIZE field to a new value. */
+#define DMA_WR_ATTR_SSIZE(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_SSIZE_MASK, DMA_ATTR_SSIZE(value)))
+#define DMA_BWR_ATTR_SSIZE(base, index, value) (DMA_WR_ATTR_SSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field SMOD[15:11] (RW)
+ *
+ * Values:
+ * - 0b00000 - Source address modulo feature is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_SMOD field. */
+#define DMA_RD_ATTR_SMOD(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_SMOD_MASK) >> DMA_ATTR_SMOD_SHIFT)
+#define DMA_BRD_ATTR_SMOD(base, index) (DMA_RD_ATTR_SMOD(base, index))
+
+/*! @brief Set the SMOD field to a new value. */
+#define DMA_WR_ATTR_SMOD(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_SMOD_MASK, DMA_ATTR_SMOD(value)))
+#define DMA_BWR_ATTR_SMOD(base, index, value) (DMA_WR_ATTR_SMOD(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
+ * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
+ * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
+ * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLOFFYES register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLOFFYES(base, index) (DMA_NBYTES_MLOFFYES_REG(base, index))
+#define DMA_WR_NBYTES_MLOFFYES(base, index, value) (DMA_NBYTES_MLOFFYES_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLOFFYES(base, index, mask, value) (DMA_WR_NBYTES_MLOFFYES(base, index, (DMA_RD_NBYTES_MLOFFYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_NBYTES_MLOFFYES bitfields
+ */
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted.
+ * (Although, it may be stalled by using the bandwidth control field, or via
+ * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
+ * written back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_NBYTES field. */
+#define DMA_RD_NBYTES_MLOFFYES_NBYTES(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) >> DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_NBYTES(base, index) (DMA_RD_NBYTES_MLOFFYES_NBYTES(base, index))
+
+/*! @brief Set the NBYTES field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_NBYTES(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_NBYTES_MASK, DMA_NBYTES_MLOFFYES_NBYTES(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_NBYTES(base, index, value) (DMA_WR_NBYTES_MLOFFYES_NBYTES(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_MLOFF field. */
+#define DMA_RD_NBYTES_MLOFFYES_MLOFF(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) >> DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_MLOFF(base, index) (DMA_RD_NBYTES_MLOFFYES_MLOFF(base, index))
+
+/*! @brief Set the MLOFF field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_MLOFF(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_MLOFF_MASK, DMA_NBYTES_MLOFFYES_MLOFF(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_MLOFF(base, index, value) (DMA_WR_NBYTES_MLOFFYES_MLOFF(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the DADDR
+ * - 0b1 - The minor loop offset is applied to the DADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_DMLOE field. */
+#define DMA_RD_NBYTES_MLOFFYES_DMLOE(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) >> DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_DMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))
+
+/*! @brief Set the DMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_DMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_DMLOE_MASK, DMA_NBYTES_MLOFFYES_DMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_DMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_DMLOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the SADDR
+ * - 0b1 - The minor loop offset is applied to the SADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_SMLOE field. */
+#define DMA_RD_NBYTES_MLOFFYES_SMLOE(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) >> DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_SMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))
+
+/*! @brief Set the SMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_SMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_SMLOE_MASK, DMA_NBYTES_MLOFFYES_SMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_SMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_SMLOE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
+ * register to use depends on whether minor loop mapping is disabled, enabled but not
+ * used for this channel, or enabled and used. TCD word 2 is defined as follows
+ * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
+ * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
+ * for TCD word 2's definition.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLNO register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLNO(base, index) (DMA_NBYTES_MLNO_REG(base, index))
+#define DMA_WR_NBYTES_MLNO(base, index, value) (DMA_NBYTES_MLNO_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLNO(base, index, mask, value) (DMA_WR_NBYTES_MLNO(base, index, (DMA_RD_NBYTES_MLNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
+ * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
+ * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
+ * the TCD_NBYTES_MLNO register description.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLOFFNO register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLOFFNO(base, index) (DMA_NBYTES_MLOFFNO_REG(base, index))
+#define DMA_WR_NBYTES_MLOFFNO(base, index, value) (DMA_NBYTES_MLOFFNO_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLOFFNO(base, index, mask, value) (DMA_WR_NBYTES_MLOFFNO(base, index, (DMA_RD_NBYTES_MLOFFNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_NBYTES_MLOFFNO bitfields
+ */
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted;
+ * although, it may be stalled by using the bandwidth control field, or via
+ * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
+ * back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_NBYTES field. */
+#define DMA_RD_NBYTES_MLOFFNO_NBYTES(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) >> DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_NBYTES(base, index) (DMA_RD_NBYTES_MLOFFNO_NBYTES(base, index))
+
+/*! @brief Set the NBYTES field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_NBYTES(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_NBYTES_MASK, DMA_NBYTES_MLOFFNO_NBYTES(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_NBYTES(base, index, value) (DMA_WR_NBYTES_MLOFFNO_NBYTES(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the DADDR
+ * - 0b1 - The minor loop offset is applied to the DADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_DMLOE field. */
+#define DMA_RD_NBYTES_MLOFFNO_DMLOE(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) >> DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_DMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))
+
+/*! @brief Set the DMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_DMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_DMLOE_MASK, DMA_NBYTES_MLOFFNO_DMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_DMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_DMLOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the SADDR
+ * - 0b1 - The minor loop offset is applied to the SADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_SMLOE field. */
+#define DMA_RD_NBYTES_MLOFFNO_SMLOE(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) >> DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_SMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))
+
+/*! @brief Set the SMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_SMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_SMLOE_MASK, DMA_NBYTES_MLOFFNO_SMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_SMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_SMLOE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SLAST - TCD Last Source Address Adjustment
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SLAST - TCD Last Source Address Adjustment (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SLAST register
+ */
+/*@{*/
+#define DMA_RD_SLAST(base, index) (DMA_SLAST_REG(base, index))
+#define DMA_WR_SLAST(base, index, value) (DMA_SLAST_REG(base, index) = (value))
+#define DMA_RMW_SLAST(base, index, mask, value) (DMA_WR_SLAST(base, index, (DMA_RD_SLAST(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) |  (value)))
+#define DMA_CLR_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) & ~(value)))
+#define DMA_TOG_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DADDR - TCD Destination Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DADDR - TCD Destination Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DADDR register
+ */
+/*@{*/
+#define DMA_RD_DADDR(base, index) (DMA_DADDR_REG(base, index))
+#define DMA_WR_DADDR(base, index, value) (DMA_DADDR_REG(base, index) = (value))
+#define DMA_RMW_DADDR(base, index, mask, value) (DMA_WR_DADDR(base, index, (DMA_RD_DADDR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) |  (value)))
+#define DMA_CLR_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) & ~(value)))
+#define DMA_TOG_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DOFF - TCD Signed Destination Address Offset
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DOFF - TCD Signed Destination Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DOFF register
+ */
+/*@{*/
+#define DMA_RD_DOFF(base, index) (DMA_DOFF_REG(base, index))
+#define DMA_WR_DOFF(base, index, value) (DMA_DOFF_REG(base, index) = (value))
+#define DMA_RMW_DOFF(base, index, mask, value) (DMA_WR_DOFF(base, index, (DMA_RD_DOFF(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) |  (value)))
+#define DMA_CLR_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) & ~(value)))
+#define DMA_TOG_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
+ * follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CITER_ELINKNO register
+ */
+/*@{*/
+#define DMA_RD_CITER_ELINKNO(base, index) (DMA_CITER_ELINKNO_REG(base, index))
+#define DMA_WR_CITER_ELINKNO(base, index, value) (DMA_CITER_ELINKNO_REG(base, index) = (value))
+#define DMA_RMW_CITER_ELINKNO(base, index, mask, value) (DMA_WR_CITER_ELINKNO(base, index, (DMA_RD_CITER_ELINKNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) |  (value)))
+#define DMA_CLR_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) & ~(value)))
+#define DMA_TOG_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_CITER_ELINKNO, field CITER[14:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKNO_CITER field. */
+#define DMA_RD_CITER_ELINKNO_CITER(base, index) ((DMA_CITER_ELINKNO_REG(base, index) & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT)
+#define DMA_BRD_CITER_ELINKNO_CITER(base, index) (DMA_RD_CITER_ELINKNO_CITER(base, index))
+
+/*! @brief Set the CITER field to a new value. */
+#define DMA_WR_CITER_ELINKNO_CITER(base, index, value) (DMA_RMW_CITER_ELINKNO(base, index, DMA_CITER_ELINKNO_CITER_MASK, DMA_CITER_ELINKNO_CITER(value)))
+#define DMA_BWR_CITER_ELINKNO_CITER(base, index, value) (DMA_WR_CITER_ELINKNO_CITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKNO_ELINK field. */
+#define DMA_RD_CITER_ELINKNO_ELINK(base, index) ((DMA_CITER_ELINKNO_REG(base, index) & DMA_CITER_ELINKNO_ELINK_MASK) >> DMA_CITER_ELINKNO_ELINK_SHIFT)
+#define DMA_BRD_CITER_ELINKNO_ELINK(base, index) (BITBAND_ACCESS16(&DMA_CITER_ELINKNO_REG(base, index), DMA_CITER_ELINKNO_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_CITER_ELINKNO_ELINK(base, index, value) (DMA_RMW_CITER_ELINKNO(base, index, DMA_CITER_ELINKNO_ELINK_MASK, DMA_CITER_ELINKNO_ELINK(value)))
+#define DMA_BWR_CITER_ELINKNO_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CITER_ELINKNO_REG(base, index), DMA_CITER_ELINKNO_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CITER_ELINKYES register
+ */
+/*@{*/
+#define DMA_RD_CITER_ELINKYES(base, index) (DMA_CITER_ELINKYES_REG(base, index))
+#define DMA_WR_CITER_ELINKYES(base, index, value) (DMA_CITER_ELINKYES_REG(base, index) = (value))
+#define DMA_RMW_CITER_ELINKYES(base, index, mask, value) (DMA_WR_CITER_ELINKYES(base, index, (DMA_RD_CITER_ELINKYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) |  (value)))
+#define DMA_CLR_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) & ~(value)))
+#define DMA_TOG_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field CITER[8:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_CITER field. */
+#define DMA_RD_CITER_ELINKYES_CITER(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_CITER(base, index) (DMA_RD_CITER_ELINKYES_CITER(base, index))
+
+/*! @brief Set the CITER field to a new value. */
+#define DMA_WR_CITER_ELINKYES_CITER(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_CITER_MASK, DMA_CITER_ELINKYES_CITER(value)))
+#define DMA_BWR_CITER_ELINKYES_CITER(base, index, value) (DMA_WR_CITER_ELINKYES_CITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request to the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_LINKCH field. */
+#define DMA_RD_CITER_ELINKYES_LINKCH(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_LINKCH_MASK) >> DMA_CITER_ELINKYES_LINKCH_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_LINKCH(base, index) (DMA_RD_CITER_ELINKYES_LINKCH(base, index))
+
+/*! @brief Set the LINKCH field to a new value. */
+#define DMA_WR_CITER_ELINKYES_LINKCH(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_LINKCH_MASK, DMA_CITER_ELINKYES_LINKCH(value)))
+#define DMA_BWR_CITER_ELINKYES_LINKCH(base, index, value) (DMA_WR_CITER_ELINKYES_LINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_ELINK field. */
+#define DMA_RD_CITER_ELINKYES_ELINK(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_ELINK_MASK) >> DMA_CITER_ELINKYES_ELINK_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_ELINK(base, index) (BITBAND_ACCESS16(&DMA_CITER_ELINKYES_REG(base, index), DMA_CITER_ELINKYES_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_CITER_ELINKYES_ELINK(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_ELINK_MASK, DMA_CITER_ELINKYES_ELINK(value)))
+#define DMA_BWR_CITER_ELINKYES_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CITER_ELINKYES_REG(base, index), DMA_CITER_ELINKYES_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DLAST_SGA register
+ */
+/*@{*/
+#define DMA_RD_DLAST_SGA(base, index) (DMA_DLAST_SGA_REG(base, index))
+#define DMA_WR_DLAST_SGA(base, index, value) (DMA_DLAST_SGA_REG(base, index) = (value))
+#define DMA_RMW_DLAST_SGA(base, index, mask, value) (DMA_WR_DLAST_SGA(base, index, (DMA_RD_DLAST_SGA(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) |  (value)))
+#define DMA_CLR_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) & ~(value)))
+#define DMA_TOG_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CSR - TCD Control and Status
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CSR - TCD Control and Status (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_CSR register
+ */
+/*@{*/
+#define DMA_RD_CSR(base, index)  (DMA_CSR_REG(base, index))
+#define DMA_WR_CSR(base, index, value) (DMA_CSR_REG(base, index) = (value))
+#define DMA_RMW_CSR(base, index, mask, value) (DMA_WR_CSR(base, index, (DMA_RD_CSR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) |  (value)))
+#define DMA_CLR_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) & ~(value)))
+#define DMA_TOG_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CSR bitfields
+ */
+
+/*!
+ * @name Register DMA_CSR, field START[0] (RW)
+ *
+ * If this flag is set, the channel is requesting service. The eDMA hardware
+ * automatically clears this flag after the channel begins execution.
+ *
+ * Values:
+ * - 0b0 - The channel is not explicitly started
+ * - 0b1 - The channel is explicitly started via a software initiated service
+ *     request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_START field. */
+#define DMA_RD_CSR_START(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_START_MASK) >> DMA_CSR_START_SHIFT)
+#define DMA_BRD_CSR_START(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_START_SHIFT))
+
+/*! @brief Set the START field to a new value. */
+#define DMA_WR_CSR_START(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_START_MASK, DMA_CSR_START(value)))
+#define DMA_BWR_CSR_START(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_START_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field INTMAJOR[1] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT when the current major iteration count reaches
+ * zero.
+ *
+ * Values:
+ * - 0b0 - The end-of-major loop interrupt is disabled
+ * - 0b1 - The end-of-major loop interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_INTMAJOR field. */
+#define DMA_RD_CSR_INTMAJOR(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_INTMAJOR_MASK) >> DMA_CSR_INTMAJOR_SHIFT)
+#define DMA_BRD_CSR_INTMAJOR(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTMAJOR_SHIFT))
+
+/*! @brief Set the INTMAJOR field to a new value. */
+#define DMA_WR_CSR_INTMAJOR(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_INTMAJOR_MASK, DMA_CSR_INTMAJOR(value)))
+#define DMA_BWR_CSR_INTMAJOR(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTMAJOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field INTHALF[2] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT register when the current major iteration count
+ * reaches the halfway point. Specifically, the comparison performed by the eDMA
+ * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
+ * provided to support double-buffered (aka ping-pong) schemes or other types of data
+ * movement where the processor needs an early indication of the transfer's
+ * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
+ *
+ * Values:
+ * - 0b0 - The half-point interrupt is disabled
+ * - 0b1 - The half-point interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_INTHALF field. */
+#define DMA_RD_CSR_INTHALF(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_INTHALF_MASK) >> DMA_CSR_INTHALF_SHIFT)
+#define DMA_BRD_CSR_INTHALF(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTHALF_SHIFT))
+
+/*! @brief Set the INTHALF field to a new value. */
+#define DMA_WR_CSR_INTHALF(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_INTHALF_MASK, DMA_CSR_INTHALF(value)))
+#define DMA_BWR_CSR_INTHALF(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTHALF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field DREQ[3] (RW)
+ *
+ * If this flag is set, the eDMA hardware automatically clears the corresponding
+ * ERQ bit when the current major iteration count reaches zero.
+ *
+ * Values:
+ * - 0b0 - The channel's ERQ bit is not affected
+ * - 0b1 - The channel's ERQ bit is cleared when the major loop is complete
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_DREQ field. */
+#define DMA_RD_CSR_DREQ(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_DREQ_MASK) >> DMA_CSR_DREQ_SHIFT)
+#define DMA_BRD_CSR_DREQ(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DREQ_SHIFT))
+
+/*! @brief Set the DREQ field to a new value. */
+#define DMA_WR_CSR_DREQ(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_DREQ_MASK, DMA_CSR_DREQ(value)))
+#define DMA_BWR_CSR_DREQ(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field ESG[4] (RW)
+ *
+ * As the channel completes the major loop, this flag enables scatter/gather
+ * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
+ * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
+ * loaded as the transfer control descriptor into the local memory. To support the
+ * dynamic scatter/gather coherency model, this field is forced to zero when
+ * written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0b0 - The current channel's TCD is normal format.
+ * - 0b1 - The current channel's TCD specifies a scatter gather format. The
+ *     DLASTSGA field provides a memory pointer to the next TCD to be loaded into
+ *     this channel after the major loop completes its execution.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_ESG field. */
+#define DMA_RD_CSR_ESG(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_ESG_MASK) >> DMA_CSR_ESG_SHIFT)
+#define DMA_BRD_CSR_ESG(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ESG_SHIFT))
+
+/*! @brief Set the ESG field to a new value. */
+#define DMA_WR_CSR_ESG(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_ESG_MASK, DMA_CSR_ESG(value)))
+#define DMA_BWR_CSR_ESG(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ESG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field MAJORELINK[5] (RW)
+ *
+ * As the channel completes the major loop, this flag enables the linking to
+ * another channel, defined by MAJORLINKCH. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. To support the dynamic linking coherency model,
+ * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_MAJORELINK field. */
+#define DMA_RD_CSR_MAJORELINK(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_MAJORELINK_MASK) >> DMA_CSR_MAJORELINK_SHIFT)
+#define DMA_BRD_CSR_MAJORELINK(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_MAJORELINK_SHIFT))
+
+/*! @brief Set the MAJORELINK field to a new value. */
+#define DMA_WR_CSR_MAJORELINK(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_MAJORELINK_MASK, DMA_CSR_MAJORELINK(value)))
+#define DMA_BWR_CSR_MAJORELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_MAJORELINK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field ACTIVE[6] (RW)
+ *
+ * This flag signals the channel is currently in execution. It is set when
+ * channel service begins, and the eDMA clears it as the minor loop completes or if
+ * any error condition is detected. This bit resets to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_ACTIVE field. */
+#define DMA_RD_CSR_ACTIVE(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_ACTIVE_MASK) >> DMA_CSR_ACTIVE_SHIFT)
+#define DMA_BRD_CSR_ACTIVE(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ACTIVE_SHIFT))
+
+/*! @brief Set the ACTIVE field to a new value. */
+#define DMA_WR_CSR_ACTIVE(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_ACTIVE_MASK, DMA_CSR_ACTIVE(value)))
+#define DMA_BWR_CSR_ACTIVE(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ACTIVE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field DONE[7] (RW)
+ *
+ * This flag indicates the eDMA has completed the major loop. The eDMA engine
+ * sets it as the CITER count reaches zero; The software clears it, or the hardware
+ * when the channel is activated. This bit must be cleared to write the
+ * MAJORELINK or ESG bits.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_DONE field. */
+#define DMA_RD_CSR_DONE(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT)
+#define DMA_BRD_CSR_DONE(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DONE_SHIFT))
+
+/*! @brief Set the DONE field to a new value. */
+#define DMA_WR_CSR_DONE(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_DONE_MASK, DMA_CSR_DONE(value)))
+#define DMA_BWR_CSR_DONE(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DONE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field MAJORLINKCH[11:8] (RW)
+ *
+ * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
+ * performed after the major loop counter is exhausted. else After the major loop
+ * counter is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_MAJORLINKCH field. */
+#define DMA_RD_CSR_MAJORLINKCH(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_MAJORLINKCH_MASK) >> DMA_CSR_MAJORLINKCH_SHIFT)
+#define DMA_BRD_CSR_MAJORLINKCH(base, index) (DMA_RD_CSR_MAJORLINKCH(base, index))
+
+/*! @brief Set the MAJORLINKCH field to a new value. */
+#define DMA_WR_CSR_MAJORLINKCH(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_MAJORLINKCH_MASK, DMA_CSR_MAJORLINKCH(value)))
+#define DMA_BWR_CSR_MAJORLINKCH(base, index, value) (DMA_WR_CSR_MAJORLINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field BWC[15:14] (RW)
+ *
+ * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
+ * the eDMA processes the minor loop, it continuously generates read/write
+ * sequences until the minor count is exhausted. This field forces the eDMA to stall
+ * after the completion of each read/write access to control the bus request
+ * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
+ * this field is ignored between the first and second transfers and after the
+ * last write of each minor loop. This behavior is a side effect of reducing
+ * start-up latency.
+ *
+ * Values:
+ * - 0b00 - No eDMA engine stalls
+ * - 0b01 - Reserved
+ * - 0b10 - eDMA engine stalls for 4 cycles after each r/w
+ * - 0b11 - eDMA engine stalls for 8 cycles after each r/w
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_BWC field. */
+#define DMA_RD_CSR_BWC(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_BWC_MASK) >> DMA_CSR_BWC_SHIFT)
+#define DMA_BRD_CSR_BWC(base, index) (DMA_RD_CSR_BWC(base, index))
+
+/*! @brief Set the BWC field to a new value. */
+#define DMA_WR_CSR_BWC(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_BWC_MASK, DMA_CSR_BWC(value)))
+#define DMA_BWR_CSR_BWC(base, index, value) (DMA_WR_CSR_BWC(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
+ * follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_BITER_ELINKYES register
+ */
+/*@{*/
+#define DMA_RD_BITER_ELINKYES(base, index) (DMA_BITER_ELINKYES_REG(base, index))
+#define DMA_WR_BITER_ELINKYES(base, index, value) (DMA_BITER_ELINKYES_REG(base, index) = (value))
+#define DMA_RMW_BITER_ELINKYES(base, index, mask, value) (DMA_WR_BITER_ELINKYES(base, index, (DMA_RD_BITER_ELINKYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) |  (value)))
+#define DMA_CLR_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) & ~(value)))
+#define DMA_TOG_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_BITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field BITER[8:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_BITER field. */
+#define DMA_RD_BITER_ELINKYES_BITER(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_BITER_MASK) >> DMA_BITER_ELINKYES_BITER_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_BITER(base, index) (DMA_RD_BITER_ELINKYES_BITER(base, index))
+
+/*! @brief Set the BITER field to a new value. */
+#define DMA_WR_BITER_ELINKYES_BITER(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_BITER_MASK, DMA_BITER_ELINKYES_BITER(value)))
+#define DMA_BWR_BITER_ELINKYES_BITER(base, index, value) (DMA_WR_BITER_ELINKYES_BITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START]
+ * bit. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the major
+ * iteration count is exhausted, the contents of this field is reloaded into the
+ * CITER field.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_LINKCH field. */
+#define DMA_RD_BITER_ELINKYES_LINKCH(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_LINKCH_MASK) >> DMA_BITER_ELINKYES_LINKCH_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_LINKCH(base, index) (DMA_RD_BITER_ELINKYES_LINKCH(base, index))
+
+/*! @brief Set the LINKCH field to a new value. */
+#define DMA_WR_BITER_ELINKYES_LINKCH(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_LINKCH_MASK, DMA_BITER_ELINKYES_LINKCH(value)))
+#define DMA_BWR_BITER_ELINKYES_LINKCH(base, index, value) (DMA_WR_BITER_ELINKYES_LINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking disables, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded into
+ * the CITER field.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_ELINK field. */
+#define DMA_RD_BITER_ELINKYES_ELINK(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_ELINK_MASK) >> DMA_BITER_ELINKYES_ELINK_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_ELINK(base, index) (BITBAND_ACCESS16(&DMA_BITER_ELINKYES_REG(base, index), DMA_BITER_ELINKYES_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_BITER_ELINKYES_ELINK(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_ELINK_MASK, DMA_BITER_ELINKYES_ELINK(value)))
+#define DMA_BWR_BITER_ELINKYES_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_BITER_ELINKYES_REG(base, index), DMA_BITER_ELINKYES_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
+ * as follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_BITER_ELINKNO register
+ */
+/*@{*/
+#define DMA_RD_BITER_ELINKNO(base, index) (DMA_BITER_ELINKNO_REG(base, index))
+#define DMA_WR_BITER_ELINKNO(base, index, value) (DMA_BITER_ELINKNO_REG(base, index) = (value))
+#define DMA_RMW_BITER_ELINKNO(base, index, mask, value) (DMA_WR_BITER_ELINKNO(base, index, (DMA_RD_BITER_ELINKNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) |  (value)))
+#define DMA_CLR_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) & ~(value)))
+#define DMA_TOG_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_BITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_BITER_ELINKNO, field BITER[14:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKNO_BITER field. */
+#define DMA_RD_BITER_ELINKNO_BITER(base, index) ((DMA_BITER_ELINKNO_REG(base, index) & DMA_BITER_ELINKNO_BITER_MASK) >> DMA_BITER_ELINKNO_BITER_SHIFT)
+#define DMA_BRD_BITER_ELINKNO_BITER(base, index) (DMA_RD_BITER_ELINKNO_BITER(base, index))
+
+/*! @brief Set the BITER field to a new value. */
+#define DMA_WR_BITER_ELINKNO_BITER(base, index, value) (DMA_RMW_BITER_ELINKNO(base, index, DMA_BITER_ELINKNO_BITER_MASK, DMA_BITER_ELINKNO_BITER(value)))
+#define DMA_BWR_BITER_ELINKNO_BITER(base, index, value) (DMA_WR_BITER_ELINKNO_BITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded
+ * into the CITER field.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKNO_ELINK field. */
+#define DMA_RD_BITER_ELINKNO_ELINK(base, index) ((DMA_BITER_ELINKNO_REG(base, index) & DMA_BITER_ELINKNO_ELINK_MASK) >> DMA_BITER_ELINKNO_ELINK_SHIFT)
+#define DMA_BRD_BITER_ELINKNO_ELINK(base, index) (BITBAND_ACCESS16(&DMA_BITER_ELINKNO_REG(base, index), DMA_BITER_ELINKNO_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_BITER_ELINKNO_ELINK(base, index, value) (DMA_RMW_BITER_ELINKNO(base, index, DMA_BITER_ELINKNO_ELINK_MASK, DMA_BITER_ELINKNO_ELINK(value)))
+#define DMA_BWR_BITER_ELINKNO_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_BITER_ELINKNO_REG(base, index), DMA_BITER_ELINKNO_ELINK_SHIFT) = (value))
+/*@}*/
+
+/* Register macros for indexed access to DMA channel priority registers */
+/*
+ * Constants and macros for entire DMA_DCHPRIn register
+ */
+#define DMA_DCHPRIn_INDEX(channel)          (((channel) & ~0x03U) | (3 - ((channel) & 0x03U)))
+#define DMA_DCHPRIn_REG(base, index)        (((volatile uint8_t *)&DMA_DCHPRI3_REG(base))[DMA_DCHPRIn_INDEX(index)])
+#define DMA_RD_DCHPRIn(base, index)         (DMA_DCHPRIn_REG((base), (index)))
+#define DMA_WR_DCHPRIn(base, index, value)  (DMA_DCHPRIn_REG((base), (index)) = (value))
+#define DMA_SET_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) |  (value)))
+#define DMA_CLR_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) & ~(value)))
+#define DMA_TOG_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) ^  (value)))
+
+/*
+ * Register DMA_DCHPRIn, bit field CHPRI
+ */
+/* Read current value of the CHPRI bit field. */
+#define DMA_RD_DCHPRIn_CHPRI(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_CHPRI_MASK) >> DMA_DCHPRI0_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRIn_CHPRI(base, index) (DMA_RD_DCHPRIn_CHPRI((base), (index)))
+
+/* Set the CHPRI bit field to a new value. */
+#define DMA_WR_DCHPRIn_CHPRI(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_CHPRI_MASK) | DMA_DCHPRI0_CHPRI(value)))
+#define DMA_BWR_DCHPRIn_CHPRI(base, index, value) (DMA_WR_DCHPRIn_CHPRI((base), (index), (value)))
+
+/*
+ * Register DMA_DCHPRIn, bit field DPA
+ */
+/* Read current value of the DPA bit field. */
+#define DMA_RD_DCHPRIn_DPA(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_DPA_MASK) >> DMA_DCHPRI0_DPA_SHIFT)
+#define DMA_BRD_DCHPRIn_DPA(base, index) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_DPA_SHIFT))
+
+/* Set the DPA bit field to a new value. */
+#define DMA_WR_DCHPRIn_DPA(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_DPA_MASK) | DMA_DCHPRI0_DPA(value)))
+#define DMA_BWR_DCHPRIn_DPA(base, index, value) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_DPA_SHIFT) = (value))
+
+/*
+ * Register DMA_DCHPRIn, bit field ECP
+ */
+/* Read current value of the ECP bit field. */
+#define DMA_RD_DCHPRIn_ECP(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_ECP_MASK) >> DMA_DCHPRI0_ECP_SHIFT)
+#define DMA_BRD_DCHPRIn_ECP(base, index) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_ECP_SHIFT))
+
+/* Set the ECP bit field to a new value. */
+#define DMA_WR_DCHPRIn_ECP(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_ECP_MASK) | DMA_DCHPRI0_ECP(value)))
+#define DMA_BWR_DCHPRIn_ECP(base, index, value) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_ECP_SHIFT) = (value))
+
+/*
+ * MK64F12 DMAMUX
+ *
+ * DMA channel multiplexor
+ *
+ * Registers defined in this header file:
+ * - DMAMUX_CHCFG - Channel Configuration register
+ */
+
+#define DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
+#define DMAMUX_IDX (0U) /*!< Instance number for DMAMUX. */
+
+/*******************************************************************************
+ * DMAMUX_CHCFG - Channel Configuration register
+ ******************************************************************************/
+
+/*!
+ * @brief DMAMUX_CHCFG - Channel Configuration register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Each of the DMA channels can be independently enabled/disabled and associated
+ * with one of the DMA slots (peripheral slots or always-on slots) in the
+ * system. Setting multiple CHCFG registers with the same source value will result in
+ * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
+ * Before changing the trigger or source settings, a DMA channel must be disabled
+ * via CHCFGn[ENBL].
+ */
+/*!
+ * @name Constants and macros for entire DMAMUX_CHCFG register
+ */
+/*@{*/
+#define DMAMUX_RD_CHCFG(base, index) (DMAMUX_CHCFG_REG(base, index))
+#define DMAMUX_WR_CHCFG(base, index, value) (DMAMUX_CHCFG_REG(base, index) = (value))
+#define DMAMUX_RMW_CHCFG(base, index, mask, value) (DMAMUX_WR_CHCFG(base, index, (DMAMUX_RD_CHCFG(base, index) & ~(mask)) | (value)))
+#define DMAMUX_SET_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) |  (value)))
+#define DMAMUX_CLR_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) & ~(value)))
+#define DMAMUX_TOG_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMAMUX_CHCFG bitfields
+ */
+
+/*!
+ * @name Register DMAMUX_CHCFG, field SOURCE[5:0] (RW)
+ *
+ * Specifies which DMA source, if any, is routed to a particular DMA channel.
+ * See your device's chip configuration details for information about the
+ * peripherals and their slot numbers.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_SOURCE field. */
+#define DMAMUX_RD_CHCFG_SOURCE(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT)
+#define DMAMUX_BRD_CHCFG_SOURCE(base, index) (DMAMUX_RD_CHCFG_SOURCE(base, index))
+
+/*! @brief Set the SOURCE field to a new value. */
+#define DMAMUX_WR_CHCFG_SOURCE(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_SOURCE_MASK, DMAMUX_CHCFG_SOURCE(value)))
+#define DMAMUX_BWR_CHCFG_SOURCE(base, index, value) (DMAMUX_WR_CHCFG_SOURCE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field TRIG[6] (RW)
+ *
+ * Enables the periodic trigger capability for the triggered DMA channel.
+ *
+ * Values:
+ * - 0b0 - Triggering is disabled. If triggering is disabled and ENBL is set,
+ *     the DMA Channel will simply route the specified source to the DMA channel.
+ *     (Normal mode)
+ * - 0b1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
+ *     DMAMUX is in Periodic Trigger mode.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_TRIG field. */
+#define DMAMUX_RD_CHCFG_TRIG(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_TRIG_MASK) >> DMAMUX_CHCFG_TRIG_SHIFT)
+#define DMAMUX_BRD_CHCFG_TRIG(base, index) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT))
+
+/*! @brief Set the TRIG field to a new value. */
+#define DMAMUX_WR_CHCFG_TRIG(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_TRIG_MASK, DMAMUX_CHCFG_TRIG(value)))
+#define DMAMUX_BWR_CHCFG_TRIG(base, index, value) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field ENBL[7] (RW)
+ *
+ * Enables the DMA channel.
+ *
+ * Values:
+ * - 0b0 - DMA channel is disabled. This mode is primarily used during
+ *     configuration of the DMAMux. The DMA has separate channel enables/disables, which
+ *     should be used to disable or reconfigure a DMA channel.
+ * - 0b1 - DMA channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_ENBL field. */
+#define DMAMUX_RD_CHCFG_ENBL(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT)
+#define DMAMUX_BRD_CHCFG_ENBL(base, index) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT))
+
+/*! @brief Set the ENBL field to a new value. */
+#define DMAMUX_WR_CHCFG_ENBL(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_ENBL_MASK, DMAMUX_CHCFG_ENBL(value)))
+#define DMAMUX_BWR_CHCFG_ENBL(base, index, value) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 ENET
+ *
+ * Ethernet MAC-NET Core
+ *
+ * Registers defined in this header file:
+ * - ENET_EIR - Interrupt Event Register
+ * - ENET_EIMR - Interrupt Mask Register
+ * - ENET_RDAR - Receive Descriptor Active Register
+ * - ENET_TDAR - Transmit Descriptor Active Register
+ * - ENET_ECR - Ethernet Control Register
+ * - ENET_MMFR - MII Management Frame Register
+ * - ENET_MSCR - MII Speed Control Register
+ * - ENET_MIBC - MIB Control Register
+ * - ENET_RCR - Receive Control Register
+ * - ENET_TCR - Transmit Control Register
+ * - ENET_PALR - Physical Address Lower Register
+ * - ENET_PAUR - Physical Address Upper Register
+ * - ENET_OPD - Opcode/Pause Duration Register
+ * - ENET_IAUR - Descriptor Individual Upper Address Register
+ * - ENET_IALR - Descriptor Individual Lower Address Register
+ * - ENET_GAUR - Descriptor Group Upper Address Register
+ * - ENET_GALR - Descriptor Group Lower Address Register
+ * - ENET_TFWR - Transmit FIFO Watermark Register
+ * - ENET_RDSR - Receive Descriptor Ring Start Register
+ * - ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ * - ENET_MRBR - Maximum Receive Buffer Size Register
+ * - ENET_RSFL - Receive FIFO Section Full Threshold
+ * - ENET_RSEM - Receive FIFO Section Empty Threshold
+ * - ENET_RAEM - Receive FIFO Almost Empty Threshold
+ * - ENET_RAFL - Receive FIFO Almost Full Threshold
+ * - ENET_TSEM - Transmit FIFO Section Empty Threshold
+ * - ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ * - ENET_TAFL - Transmit FIFO Almost Full Threshold
+ * - ENET_TIPG - Transmit Inter-Packet Gap
+ * - ENET_FTRL - Frame Truncation Length
+ * - ENET_TACC - Transmit Accelerator Function Configuration
+ * - ENET_RACC - Receive Accelerator Function Configuration
+ * - ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ * - ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ * - ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ * - ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ * - ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ * - ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ * - ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ * - ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ * - ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ * - ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ * - ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ * - ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ * - ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ * - ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ * - ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ * - ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ * - ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ * - ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ * - ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ * - ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ * - ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ * - ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ * - ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ * - ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ * - ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ * - ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ * - ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ * - ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ * - ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ * - ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ * - ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ * - ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ * - ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ * - ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ * - ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ * - ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ * - ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ * - ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ * - ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ * - ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ * - ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ * - ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ * - ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ * - ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ * - ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ * - ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ * - ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ * - ENET_ATCR - Adjustable Timer Control Register
+ * - ENET_ATVR - Timer Value Register
+ * - ENET_ATOFF - Timer Offset Register
+ * - ENET_ATPER - Timer Period Register
+ * - ENET_ATCOR - Timer Correction Register
+ * - ENET_ATINC - Time-Stamping Clock Period Register
+ * - ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ * - ENET_TGSR - Timer Global Status Register
+ * - ENET_TCSR - Timer Control Status Register
+ * - ENET_TCCR - Timer Compare Capture Register
+ */
+
+#define ENET_INSTANCE_COUNT (1U) /*!< Number of instances of the ENET module. */
+#define ENET_IDX (0U) /*!< Instance number for ENET. */
+
+/*******************************************************************************
+ * ENET_EIR - Interrupt Event Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_EIR - Interrupt Event Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an event occurs that sets a bit in EIR, an interrupt occurs if the
+ * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
+ * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
+ * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
+ * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
+ * Legacy mode does not require these flags to be enabled.
+ */
+/*!
+ * @name Constants and macros for entire ENET_EIR register
+ */
+/*@{*/
+#define ENET_RD_EIR(base)        (ENET_EIR_REG(base))
+#define ENET_WR_EIR(base, value) (ENET_EIR_REG(base) = (value))
+#define ENET_RMW_EIR(base, mask, value) (ENET_WR_EIR(base, (ENET_RD_EIR(base) & ~(mask)) | (value)))
+#define ENET_SET_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) |  (value)))
+#define ENET_CLR_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) & ~(value)))
+#define ENET_TOG_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_EIR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
+ *
+ * The adjustable timer reached the period event. A period event interrupt can
+ * be generated if ATCR[PEREN] is set and the timer wraps according to the
+ * periodic setting in the ATPER register. Set the timer period value before setting
+ * ATCR[PEREN].
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TS_TIMER field. */
+#define ENET_RD_EIR_TS_TIMER(base) ((ENET_EIR_REG(base) & ENET_EIR_TS_TIMER_MASK) >> ENET_EIR_TS_TIMER_SHIFT)
+#define ENET_BRD_EIR_TS_TIMER(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_TIMER_SHIFT))
+
+/*! @brief Set the TS_TIMER field to a new value. */
+#define ENET_WR_EIR_TS_TIMER(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TS_TIMER(value)))
+#define ENET_BWR_EIR_TS_TIMER(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_TIMER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
+ *
+ * Indicates that the timestamp of the last transmitted timing frame is
+ * available in the ATSTMP register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TS_AVAIL field. */
+#define ENET_RD_EIR_TS_AVAIL(base) ((ENET_EIR_REG(base) & ENET_EIR_TS_AVAIL_MASK) >> ENET_EIR_TS_AVAIL_SHIFT)
+#define ENET_BRD_EIR_TS_AVAIL(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_AVAIL_SHIFT))
+
+/*! @brief Set the TS_AVAIL field to a new value. */
+#define ENET_WR_EIR_TS_AVAIL(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TS_AVAIL_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TS_AVAIL(value)))
+#define ENET_BWR_EIR_TS_AVAIL(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_AVAIL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field WAKEUP[17] (W1C)
+ *
+ * Read-only status bit to indicate that a magic packet has been detected. Will
+ * act only if ECR[MAGICEN] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_WAKEUP field. */
+#define ENET_RD_EIR_WAKEUP(base) ((ENET_EIR_REG(base) & ENET_EIR_WAKEUP_MASK) >> ENET_EIR_WAKEUP_SHIFT)
+#define ENET_BRD_EIR_WAKEUP(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_WAKEUP_SHIFT))
+
+/*! @brief Set the WAKEUP field to a new value. */
+#define ENET_WR_EIR_WAKEUP(base, value) (ENET_RMW_EIR(base, (ENET_EIR_WAKEUP_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_WAKEUP(value)))
+#define ENET_BWR_EIR_WAKEUP(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_WAKEUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field PLR[18] (W1C)
+ *
+ * Indicates a frame was received with a payload length error. See Frame
+ * Length/Type Verification: Payload Length Check for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_PLR field. */
+#define ENET_RD_EIR_PLR(base) ((ENET_EIR_REG(base) & ENET_EIR_PLR_MASK) >> ENET_EIR_PLR_SHIFT)
+#define ENET_BRD_EIR_PLR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_PLR_SHIFT))
+
+/*! @brief Set the PLR field to a new value. */
+#define ENET_WR_EIR_PLR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_PLR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_PLR(value)))
+#define ENET_BWR_EIR_PLR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_PLR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field UN[19] (W1C)
+ *
+ * Indicates the transmit FIFO became empty before the complete frame was
+ * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
+ * frame is discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_UN field. */
+#define ENET_RD_EIR_UN(base) ((ENET_EIR_REG(base) & ENET_EIR_UN_MASK) >> ENET_EIR_UN_SHIFT)
+#define ENET_BRD_EIR_UN(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_UN_SHIFT))
+
+/*! @brief Set the UN field to a new value. */
+#define ENET_WR_EIR_UN(base, value) (ENET_RMW_EIR(base, (ENET_EIR_UN_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_UN(value)))
+#define ENET_BWR_EIR_UN(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_UN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RL[20] (W1C)
+ *
+ * Indicates a collision occurred on each of 16 successive attempts to transmit
+ * the frame. The frame is discarded without being transmitted and transmission
+ * of the next frame commences. This error can only occur in half-duplex mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RL field. */
+#define ENET_RD_EIR_RL(base) ((ENET_EIR_REG(base) & ENET_EIR_RL_MASK) >> ENET_EIR_RL_SHIFT)
+#define ENET_BRD_EIR_RL(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RL_SHIFT))
+
+/*! @brief Set the RL field to a new value. */
+#define ENET_WR_EIR_RL(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RL_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RL(value)))
+#define ENET_BWR_EIR_RL(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field LC[21] (W1C)
+ *
+ * Indicates a collision occurred beyond the collision window (slot time) in
+ * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
+ * frame is discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_LC field. */
+#define ENET_RD_EIR_LC(base) ((ENET_EIR_REG(base) & ENET_EIR_LC_MASK) >> ENET_EIR_LC_SHIFT)
+#define ENET_BRD_EIR_LC(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_LC_SHIFT))
+
+/*! @brief Set the LC field to a new value. */
+#define ENET_WR_EIR_LC(base, value) (ENET_RMW_EIR(base, (ENET_EIR_LC_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_LC(value)))
+#define ENET_BWR_EIR_LC(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_LC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field EBERR[22] (W1C)
+ *
+ * Indicates a system bus error occurred when a uDMA transaction is underway.
+ * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
+ * MAC. When this occurs, software must ensure proper actions, possibly resetting
+ * the system, to resume normal operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_EBERR field. */
+#define ENET_RD_EIR_EBERR(base) ((ENET_EIR_REG(base) & ENET_EIR_EBERR_MASK) >> ENET_EIR_EBERR_SHIFT)
+#define ENET_BRD_EIR_EBERR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_EBERR_SHIFT))
+
+/*! @brief Set the EBERR field to a new value. */
+#define ENET_WR_EIR_EBERR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_EBERR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_EBERR(value)))
+#define ENET_BWR_EIR_EBERR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_EBERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field MII[23] (W1C)
+ *
+ * Indicates that the MII has completed the data transfer requested.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_MII field. */
+#define ENET_RD_EIR_MII(base) ((ENET_EIR_REG(base) & ENET_EIR_MII_MASK) >> ENET_EIR_MII_SHIFT)
+#define ENET_BRD_EIR_MII(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_MII_SHIFT))
+
+/*! @brief Set the MII field to a new value. */
+#define ENET_WR_EIR_MII(base, value) (ENET_RMW_EIR(base, (ENET_EIR_MII_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_MII(value)))
+#define ENET_BWR_EIR_MII(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_MII_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RXB[24] (W1C)
+ *
+ * Indicates a receive buffer descriptor is not the last in the frame has been
+ * updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RXB field. */
+#define ENET_RD_EIR_RXB(base) ((ENET_EIR_REG(base) & ENET_EIR_RXB_MASK) >> ENET_EIR_RXB_SHIFT)
+#define ENET_BRD_EIR_RXB(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXB_SHIFT))
+
+/*! @brief Set the RXB field to a new value. */
+#define ENET_WR_EIR_RXB(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RXB_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RXB(value)))
+#define ENET_BWR_EIR_RXB(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RXF[25] (W1C)
+ *
+ * Indicates a frame has been received and the last corresponding buffer
+ * descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RXF field. */
+#define ENET_RD_EIR_RXF(base) ((ENET_EIR_REG(base) & ENET_EIR_RXF_MASK) >> ENET_EIR_RXF_SHIFT)
+#define ENET_BRD_EIR_RXF(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXF_SHIFT))
+
+/*! @brief Set the RXF field to a new value. */
+#define ENET_WR_EIR_RXF(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RXF_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RXF(value)))
+#define ENET_BWR_EIR_RXF(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TXB[26] (W1C)
+ *
+ * Indicates a transmit buffer descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TXB field. */
+#define ENET_RD_EIR_TXB(base) ((ENET_EIR_REG(base) & ENET_EIR_TXB_MASK) >> ENET_EIR_TXB_SHIFT)
+#define ENET_BRD_EIR_TXB(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXB_SHIFT))
+
+/*! @brief Set the TXB field to a new value. */
+#define ENET_WR_EIR_TXB(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TXB_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TXB(value)))
+#define ENET_BWR_EIR_TXB(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TXF[27] (W1C)
+ *
+ * Indicates a frame has been transmitted and the last corresponding buffer
+ * descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TXF field. */
+#define ENET_RD_EIR_TXF(base) ((ENET_EIR_REG(base) & ENET_EIR_TXF_MASK) >> ENET_EIR_TXF_SHIFT)
+#define ENET_BRD_EIR_TXF(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXF_SHIFT))
+
+/*! @brief Set the TXF field to a new value. */
+#define ENET_WR_EIR_TXF(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TXF_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TXF(value)))
+#define ENET_BWR_EIR_TXF(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field GRA[28] (W1C)
+ *
+ * This interrupt is asserted after the transmitter is put into a pause state
+ * after completion of the frame currently being transmitted. See Graceful Transmit
+ * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
+ * asserted only when the TX transitions into the stopped state. If this bit is
+ * cleared by writing 1 and the TX is still stopped, the bit is not set again.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_GRA field. */
+#define ENET_RD_EIR_GRA(base) ((ENET_EIR_REG(base) & ENET_EIR_GRA_MASK) >> ENET_EIR_GRA_SHIFT)
+#define ENET_BRD_EIR_GRA(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_GRA_SHIFT))
+
+/*! @brief Set the GRA field to a new value. */
+#define ENET_WR_EIR_GRA(base, value) (ENET_RMW_EIR(base, (ENET_EIR_GRA_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_GRA(value)))
+#define ENET_BWR_EIR_GRA(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_GRA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field BABT[29] (W1C)
+ *
+ * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
+ * this condition is caused when a frame that is too long is placed into the
+ * transmit data buffer(s). Truncation does not occur.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_BABT field. */
+#define ENET_RD_EIR_BABT(base) ((ENET_EIR_REG(base) & ENET_EIR_BABT_MASK) >> ENET_EIR_BABT_SHIFT)
+#define ENET_BRD_EIR_BABT(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABT_SHIFT))
+
+/*! @brief Set the BABT field to a new value. */
+#define ENET_WR_EIR_BABT(base, value) (ENET_RMW_EIR(base, (ENET_EIR_BABT_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABR_MASK), ENET_EIR_BABT(value)))
+#define ENET_BWR_EIR_BABT(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field BABR[30] (W1C)
+ *
+ * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_BABR field. */
+#define ENET_RD_EIR_BABR(base) ((ENET_EIR_REG(base) & ENET_EIR_BABR_MASK) >> ENET_EIR_BABR_SHIFT)
+#define ENET_BRD_EIR_BABR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABR_SHIFT))
+
+/*! @brief Set the BABR field to a new value. */
+#define ENET_WR_EIR_BABR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_BABR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK), ENET_EIR_BABR(value)))
+#define ENET_BWR_EIR_BABR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_EIMR - Interrupt Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_EIMR - Interrupt Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * EIMR controls which interrupt events are allowed to generate actual
+ * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
+ * and EIMR registers are set, an interrupt is generated. The interrupt signal
+ * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
+ * 0 is written to the EIMR field.
+ */
+/*!
+ * @name Constants and macros for entire ENET_EIMR register
+ */
+/*@{*/
+#define ENET_RD_EIMR(base)       (ENET_EIMR_REG(base))
+#define ENET_WR_EIMR(base, value) (ENET_EIMR_REG(base) = (value))
+#define ENET_RMW_EIMR(base, mask, value) (ENET_WR_EIMR(base, (ENET_RD_EIMR(base) & ~(mask)) | (value)))
+#define ENET_SET_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) |  (value)))
+#define ENET_CLR_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) & ~(value)))
+#define ENET_TOG_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_EIMR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_TIMER field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TS_TIMER field. */
+#define ENET_RD_EIMR_TS_TIMER(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TS_TIMER_MASK) >> ENET_EIMR_TS_TIMER_SHIFT)
+#define ENET_BRD_EIMR_TS_TIMER(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_TIMER_SHIFT))
+
+/*! @brief Set the TS_TIMER field to a new value. */
+#define ENET_WR_EIMR_TS_TIMER(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TS_TIMER_MASK, ENET_EIMR_TS_TIMER(value)))
+#define ENET_BWR_EIMR_TS_TIMER(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_TIMER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TS_AVAIL field. */
+#define ENET_RD_EIMR_TS_AVAIL(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TS_AVAIL_MASK) >> ENET_EIMR_TS_AVAIL_SHIFT)
+#define ENET_BRD_EIMR_TS_AVAIL(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_AVAIL_SHIFT))
+
+/*! @brief Set the TS_AVAIL field to a new value. */
+#define ENET_WR_EIMR_TS_AVAIL(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TS_AVAIL_MASK, ENET_EIMR_TS_AVAIL(value)))
+#define ENET_BWR_EIMR_TS_AVAIL(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_AVAIL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field WAKEUP[17] (RW)
+ *
+ * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR WAKEUP field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_WAKEUP field. */
+#define ENET_RD_EIMR_WAKEUP(base) ((ENET_EIMR_REG(base) & ENET_EIMR_WAKEUP_MASK) >> ENET_EIMR_WAKEUP_SHIFT)
+#define ENET_BRD_EIMR_WAKEUP(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_WAKEUP_SHIFT))
+
+/*! @brief Set the WAKEUP field to a new value. */
+#define ENET_WR_EIMR_WAKEUP(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_WAKEUP_MASK, ENET_EIMR_WAKEUP(value)))
+#define ENET_BWR_EIMR_WAKEUP(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_WAKEUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field PLR[18] (RW)
+ *
+ * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR PLR field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_PLR field. */
+#define ENET_RD_EIMR_PLR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_PLR_MASK) >> ENET_EIMR_PLR_SHIFT)
+#define ENET_BRD_EIMR_PLR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_PLR_SHIFT))
+
+/*! @brief Set the PLR field to a new value. */
+#define ENET_WR_EIMR_PLR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_PLR_MASK, ENET_EIMR_PLR(value)))
+#define ENET_BWR_EIMR_PLR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_PLR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field UN[19] (RW)
+ *
+ * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR UN field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_UN field. */
+#define ENET_RD_EIMR_UN(base) ((ENET_EIMR_REG(base) & ENET_EIMR_UN_MASK) >> ENET_EIMR_UN_SHIFT)
+#define ENET_BRD_EIMR_UN(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_UN_SHIFT))
+
+/*! @brief Set the UN field to a new value. */
+#define ENET_WR_EIMR_UN(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_UN_MASK, ENET_EIMR_UN(value)))
+#define ENET_BWR_EIMR_UN(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_UN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RL[20] (RW)
+ *
+ * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR RL field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RL field. */
+#define ENET_RD_EIMR_RL(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RL_MASK) >> ENET_EIMR_RL_SHIFT)
+#define ENET_BRD_EIMR_RL(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RL_SHIFT))
+
+/*! @brief Set the RL field to a new value. */
+#define ENET_WR_EIMR_RL(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RL_MASK, ENET_EIMR_RL(value)))
+#define ENET_BWR_EIMR_RL(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field LC[21] (RW)
+ *
+ * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR LC field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_LC field. */
+#define ENET_RD_EIMR_LC(base) ((ENET_EIMR_REG(base) & ENET_EIMR_LC_MASK) >> ENET_EIMR_LC_SHIFT)
+#define ENET_BRD_EIMR_LC(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_LC_SHIFT))
+
+/*! @brief Set the LC field to a new value. */
+#define ENET_WR_EIMR_LC(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_LC_MASK, ENET_EIMR_LC(value)))
+#define ENET_BWR_EIMR_LC(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_LC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field EBERR[22] (RW)
+ *
+ * Corresponds to interrupt source EIR[EBERR] and determines whether an
+ * interrupt condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR EBERR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_EBERR field. */
+#define ENET_RD_EIMR_EBERR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_EBERR_MASK) >> ENET_EIMR_EBERR_SHIFT)
+#define ENET_BRD_EIMR_EBERR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_EBERR_SHIFT))
+
+/*! @brief Set the EBERR field to a new value. */
+#define ENET_WR_EIMR_EBERR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_EBERR_MASK, ENET_EIMR_EBERR(value)))
+#define ENET_BWR_EIMR_EBERR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_EBERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field MII[23] (RW)
+ *
+ * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR MII field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_MII field. */
+#define ENET_RD_EIMR_MII(base) ((ENET_EIMR_REG(base) & ENET_EIMR_MII_MASK) >> ENET_EIMR_MII_SHIFT)
+#define ENET_BRD_EIMR_MII(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_MII_SHIFT))
+
+/*! @brief Set the MII field to a new value. */
+#define ENET_WR_EIMR_MII(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_MII_MASK, ENET_EIMR_MII(value)))
+#define ENET_BWR_EIMR_MII(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_MII_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RXB[24] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXB field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RXB field. */
+#define ENET_RD_EIMR_RXB(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RXB_MASK) >> ENET_EIMR_RXB_SHIFT)
+#define ENET_BRD_EIMR_RXB(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXB_SHIFT))
+
+/*! @brief Set the RXB field to a new value. */
+#define ENET_WR_EIMR_RXB(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RXB_MASK, ENET_EIMR_RXB(value)))
+#define ENET_BWR_EIMR_RXB(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RXF[25] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RXF field. */
+#define ENET_RD_EIMR_RXF(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RXF_MASK) >> ENET_EIMR_RXF_SHIFT)
+#define ENET_BRD_EIMR_RXF(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXF_SHIFT))
+
+/*! @brief Set the RXF field to a new value. */
+#define ENET_WR_EIMR_RXF(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RXF_MASK, ENET_EIMR_RXF(value)))
+#define ENET_BWR_EIMR_RXF(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TXB[26] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TXB field. */
+#define ENET_RD_EIMR_TXB(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TXB_MASK) >> ENET_EIMR_TXB_SHIFT)
+#define ENET_BRD_EIMR_TXB(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXB_SHIFT))
+
+/*! @brief Set the TXB field to a new value. */
+#define ENET_WR_EIMR_TXB(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TXB_MASK, ENET_EIMR_TXB(value)))
+#define ENET_BWR_EIMR_TXB(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TXF[27] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TXF field. */
+#define ENET_RD_EIMR_TXF(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TXF_MASK) >> ENET_EIMR_TXF_SHIFT)
+#define ENET_BRD_EIMR_TXF(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXF_SHIFT))
+
+/*! @brief Set the TXF field to a new value. */
+#define ENET_WR_EIMR_TXF(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TXF_MASK, ENET_EIMR_TXF(value)))
+#define ENET_BWR_EIMR_TXF(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field GRA[28] (RW)
+ *
+ * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR GRA field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_GRA field. */
+#define ENET_RD_EIMR_GRA(base) ((ENET_EIMR_REG(base) & ENET_EIMR_GRA_MASK) >> ENET_EIMR_GRA_SHIFT)
+#define ENET_BRD_EIMR_GRA(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_GRA_SHIFT))
+
+/*! @brief Set the GRA field to a new value. */
+#define ENET_WR_EIMR_GRA(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_GRA_MASK, ENET_EIMR_GRA(value)))
+#define ENET_BWR_EIMR_GRA(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_GRA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field BABT[29] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABT
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_BABT field. */
+#define ENET_RD_EIMR_BABT(base) ((ENET_EIMR_REG(base) & ENET_EIMR_BABT_MASK) >> ENET_EIMR_BABT_SHIFT)
+#define ENET_BRD_EIMR_BABT(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABT_SHIFT))
+
+/*! @brief Set the BABT field to a new value. */
+#define ENET_WR_EIMR_BABT(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_BABT_MASK, ENET_EIMR_BABT(value)))
+#define ENET_BWR_EIMR_BABT(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field BABR[30] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_BABR field. */
+#define ENET_RD_EIMR_BABR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_BABR_MASK) >> ENET_EIMR_BABR_SHIFT)
+#define ENET_BRD_EIMR_BABR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABR_SHIFT))
+
+/*! @brief Set the BABR field to a new value. */
+#define ENET_WR_EIMR_BABR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_BABR_MASK, ENET_EIMR_BABR(value)))
+#define ENET_BWR_EIMR_BABR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RDAR - Receive Descriptor Active Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RDAR - Receive Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDAR is a command register, written by the user, to indicate that the receive
+ * descriptor ring has been updated, that is, that the driver produced empty
+ * receive buffers with the empty bit set.
+ */
+/*!
+ * @name Constants and macros for entire ENET_RDAR register
+ */
+/*@{*/
+#define ENET_RD_RDAR(base)       (ENET_RDAR_REG(base))
+#define ENET_WR_RDAR(base, value) (ENET_RDAR_REG(base) = (value))
+#define ENET_RMW_RDAR(base, mask, value) (ENET_WR_RDAR(base, (ENET_RD_RDAR(base) & ~(mask)) | (value)))
+#define ENET_SET_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) |  (value)))
+#define ENET_CLR_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) & ~(value)))
+#define ENET_TOG_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDAR, field RDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This field is cleared by the MAC device when no additional empty
+ * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
+ * from set to cleared or when ECR[RESET] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RDAR_RDAR field. */
+#define ENET_RD_RDAR_RDAR(base) ((ENET_RDAR_REG(base) & ENET_RDAR_RDAR_MASK) >> ENET_RDAR_RDAR_SHIFT)
+#define ENET_BRD_RDAR_RDAR(base) (BITBAND_ACCESS32(&ENET_RDAR_REG(base), ENET_RDAR_RDAR_SHIFT))
+
+/*! @brief Set the RDAR field to a new value. */
+#define ENET_WR_RDAR_RDAR(base, value) (ENET_RMW_RDAR(base, ENET_RDAR_RDAR_MASK, ENET_RDAR_RDAR(value)))
+#define ENET_BWR_RDAR_RDAR(base, value) (BITBAND_ACCESS32(&ENET_RDAR_REG(base), ENET_RDAR_RDAR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TDAR - Transmit Descriptor Active Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TDAR - Transmit Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The TDAR is a command register that the user writes to indicate that the
+ * transmit descriptor ring has been updated, that is, that transmit buffers have
+ * been produced by the driver with the ready bit set in the buffer descriptor. The
+ * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
+ * cleared, or when ECR[RESET] is set.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TDAR register
+ */
+/*@{*/
+#define ENET_RD_TDAR(base)       (ENET_TDAR_REG(base))
+#define ENET_WR_TDAR(base, value) (ENET_TDAR_REG(base) = (value))
+#define ENET_RMW_TDAR(base, mask, value) (ENET_WR_TDAR(base, (ENET_RD_TDAR(base) & ~(mask)) | (value)))
+#define ENET_SET_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) |  (value)))
+#define ENET_CLR_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) & ~(value)))
+#define ENET_TOG_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDAR, field TDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This bit is cleared by the MAC device when no additional ready descriptors
+ * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
+ * set to cleared or when ECR[RESET] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TDAR_TDAR field. */
+#define ENET_RD_TDAR_TDAR(base) ((ENET_TDAR_REG(base) & ENET_TDAR_TDAR_MASK) >> ENET_TDAR_TDAR_SHIFT)
+#define ENET_BRD_TDAR_TDAR(base) (BITBAND_ACCESS32(&ENET_TDAR_REG(base), ENET_TDAR_TDAR_SHIFT))
+
+/*! @brief Set the TDAR field to a new value. */
+#define ENET_WR_TDAR_TDAR(base, value) (ENET_RMW_TDAR(base, ENET_TDAR_TDAR_MASK, ENET_TDAR_TDAR(value)))
+#define ENET_BWR_TDAR_TDAR(base, value) (BITBAND_ACCESS32(&ENET_TDAR_REG(base), ENET_TDAR_TDAR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ECR - Ethernet Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ECR - Ethernet Control Register (RW)
+ *
+ * Reset value: 0xF0000000U
+ *
+ * ECR is a read/write user register, though hardware may also alter fields in
+ * this register. It controls many of the high level features of the Ethernet MAC,
+ * including legacy FEC support through the EN1588 field.
+ */
+/*!
+ * @name Constants and macros for entire ENET_ECR register
+ */
+/*@{*/
+#define ENET_RD_ECR(base)        (ENET_ECR_REG(base))
+#define ENET_WR_ECR(base, value) (ENET_ECR_REG(base) = (value))
+#define ENET_RMW_ECR(base, mask, value) (ENET_WR_ECR(base, (ENET_RD_ECR(base) & ~(mask)) | (value)))
+#define ENET_SET_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) |  (value)))
+#define ENET_CLR_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) & ~(value)))
+#define ENET_TOG_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ECR bitfields
+ */
+
+/*!
+ * @name Register ENET_ECR, field RESET[0] (RW)
+ *
+ * When this field is set, it clears the ETHEREN field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_RESET field. */
+#define ENET_RD_ECR_RESET(base) ((ENET_ECR_REG(base) & ENET_ECR_RESET_MASK) >> ENET_ECR_RESET_SHIFT)
+#define ENET_BRD_ECR_RESET(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_RESET_SHIFT))
+
+/*! @brief Set the RESET field to a new value. */
+#define ENET_WR_ECR_RESET(base, value) (ENET_RMW_ECR(base, ENET_ECR_RESET_MASK, ENET_ECR_RESET(value)))
+#define ENET_BWR_ECR_RESET(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_RESET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field ETHEREN[1] (RW)
+ *
+ * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
+ * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
+ * descriptor, and FIFO control logic are reset, including the buffer descriptor and
+ * FIFO pointers. Hardware clears this field under the following conditions: RESET
+ * is set by software An error condition causes the EBERR field to set. ETHEREN
+ * must be set at the very last step during ENET
+ * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
+ * is cleared to 0 by software then then next time ETHEREN is set, the EIR
+ * interrupts must cleared to 0 due to previous pending interrupts.
+ *
+ * Values:
+ * - 0b0 - Reception immediately stops and transmission stops after a bad CRC is
+ *     appended to any currently transmitted frame.
+ * - 0b1 - MAC is enabled, and reception and transmission are possible.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_ETHEREN field. */
+#define ENET_RD_ECR_ETHEREN(base) ((ENET_ECR_REG(base) & ENET_ECR_ETHEREN_MASK) >> ENET_ECR_ETHEREN_SHIFT)
+#define ENET_BRD_ECR_ETHEREN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_ETHEREN_SHIFT))
+
+/*! @brief Set the ETHEREN field to a new value. */
+#define ENET_WR_ECR_ETHEREN(base, value) (ENET_RMW_ECR(base, ENET_ECR_ETHEREN_MASK, ENET_ECR_ETHEREN(value)))
+#define ENET_BWR_ECR_ETHEREN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_ETHEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field MAGICEN[2] (RW)
+ *
+ * Enables/disables magic packet detection. MAGICEN is relevant only if the
+ * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
+ * sleep mode and magic packet detection.
+ *
+ * Values:
+ * - 0b0 - Magic detection logic disabled.
+ * - 0b1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a
+ *     frame is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_MAGICEN field. */
+#define ENET_RD_ECR_MAGICEN(base) ((ENET_ECR_REG(base) & ENET_ECR_MAGICEN_MASK) >> ENET_ECR_MAGICEN_SHIFT)
+#define ENET_BRD_ECR_MAGICEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_MAGICEN_SHIFT))
+
+/*! @brief Set the MAGICEN field to a new value. */
+#define ENET_WR_ECR_MAGICEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_MAGICEN_MASK, ENET_ECR_MAGICEN(value)))
+#define ENET_BWR_ECR_MAGICEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_MAGICEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field SLEEP[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operating mode.
+ * - 0b1 - Sleep mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_SLEEP field. */
+#define ENET_RD_ECR_SLEEP(base) ((ENET_ECR_REG(base) & ENET_ECR_SLEEP_MASK) >> ENET_ECR_SLEEP_SHIFT)
+#define ENET_BRD_ECR_SLEEP(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_SLEEP_SHIFT))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define ENET_WR_ECR_SLEEP(base, value) (ENET_RMW_ECR(base, ENET_ECR_SLEEP_MASK, ENET_ECR_SLEEP(value)))
+#define ENET_BWR_ECR_SLEEP(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_SLEEP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field EN1588[4] (RW)
+ *
+ * Enables enhanced functionality of the MAC.
+ *
+ * Values:
+ * - 0b0 - Legacy FEC buffer descriptors and functions enabled.
+ * - 0b1 - Enhanced frame time-stamping functions enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_EN1588 field. */
+#define ENET_RD_ECR_EN1588(base) ((ENET_ECR_REG(base) & ENET_ECR_EN1588_MASK) >> ENET_ECR_EN1588_SHIFT)
+#define ENET_BRD_ECR_EN1588(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_EN1588_SHIFT))
+
+/*! @brief Set the EN1588 field to a new value. */
+#define ENET_WR_ECR_EN1588(base, value) (ENET_RMW_ECR(base, ENET_ECR_EN1588_MASK, ENET_ECR_EN1588(value)))
+#define ENET_BWR_ECR_EN1588(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_EN1588_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field DBGEN[6] (RW)
+ *
+ * Enables the MAC to enter hardware freeze mode when the device enters debug
+ * mode.
+ *
+ * Values:
+ * - 0b0 - MAC continues operation in debug mode.
+ * - 0b1 - MAC enters hardware freeze mode when the processor is in debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_DBGEN field. */
+#define ENET_RD_ECR_DBGEN(base) ((ENET_ECR_REG(base) & ENET_ECR_DBGEN_MASK) >> ENET_ECR_DBGEN_SHIFT)
+#define ENET_BRD_ECR_DBGEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBGEN_SHIFT))
+
+/*! @brief Set the DBGEN field to a new value. */
+#define ENET_WR_ECR_DBGEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_DBGEN_MASK, ENET_ECR_DBGEN(value)))
+#define ENET_BWR_ECR_DBGEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field STOPEN[7] (RW)
+ *
+ * Controls device behavior in doze mode. In doze mode, if this field is set
+ * then all the clocks of the ENET assembly are disabled, except the RMII /MII
+ * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
+ * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
+ * can still wake the system after receiving a magic packet in stop mode. MAGICEN
+ * must be set prior to entering sleep/stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_STOPEN field. */
+#define ENET_RD_ECR_STOPEN(base) ((ENET_ECR_REG(base) & ENET_ECR_STOPEN_MASK) >> ENET_ECR_STOPEN_SHIFT)
+#define ENET_BRD_ECR_STOPEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_STOPEN_SHIFT))
+
+/*! @brief Set the STOPEN field to a new value. */
+#define ENET_WR_ECR_STOPEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_STOPEN_MASK, ENET_ECR_STOPEN(value)))
+#define ENET_BWR_ECR_STOPEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_STOPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field DBSWP[8] (RW)
+ *
+ * Swaps the byte locations of the buffer descriptors. This field must be
+ * written to 1 after reset.
+ *
+ * Values:
+ * - 0b0 - The buffer descriptor bytes are not swapped to support big-endian
+ *     devices.
+ * - 0b1 - The buffer descriptor bytes are swapped to support little-endian
+ *     devices.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_DBSWP field. */
+#define ENET_RD_ECR_DBSWP(base) ((ENET_ECR_REG(base) & ENET_ECR_DBSWP_MASK) >> ENET_ECR_DBSWP_SHIFT)
+#define ENET_BRD_ECR_DBSWP(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBSWP_SHIFT))
+
+/*! @brief Set the DBSWP field to a new value. */
+#define ENET_WR_ECR_DBSWP(base, value) (ENET_RMW_ECR(base, ENET_ECR_DBSWP_MASK, ENET_ECR_DBSWP(value)))
+#define ENET_BWR_ECR_DBSWP(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBSWP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MMFR - MII Management Frame Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MMFR - MII Management Frame Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Writing to MMFR triggers a management frame transaction to the PHY device
+ * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
+ * during a write to MMFR, an MII frame is generated with the data previously written
+ * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
+ * MSCR is currently zero. If the MMFR register is written while frame generation is
+ * in progress, the frame contents are altered. Software must use the EIR[MII]
+ * interrupt indication to avoid writing to the MMFR register while frame
+ * generation is in progress.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MMFR register
+ */
+/*@{*/
+#define ENET_RD_MMFR(base)       (ENET_MMFR_REG(base))
+#define ENET_WR_MMFR(base, value) (ENET_MMFR_REG(base) = (value))
+#define ENET_RMW_MMFR(base, mask, value) (ENET_WR_MMFR(base, (ENET_RD_MMFR(base) & ~(mask)) | (value)))
+#define ENET_SET_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) |  (value)))
+#define ENET_CLR_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) & ~(value)))
+#define ENET_TOG_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MMFR bitfields
+ */
+
+/*!
+ * @name Register ENET_MMFR, field DATA[15:0] (RW)
+ *
+ * This is the field for data to be written to or read from the PHY register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_DATA field. */
+#define ENET_RD_MMFR_DATA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT)
+#define ENET_BRD_MMFR_DATA(base) (ENET_RD_MMFR_DATA(base))
+
+/*! @brief Set the DATA field to a new value. */
+#define ENET_WR_MMFR_DATA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_DATA_MASK, ENET_MMFR_DATA(value)))
+#define ENET_BWR_MMFR_DATA(base, value) (ENET_WR_MMFR_DATA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field TA[17:16] (RW)
+ *
+ * This field must be programmed to 10 to generate a valid MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_TA field. */
+#define ENET_RD_MMFR_TA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_TA_MASK) >> ENET_MMFR_TA_SHIFT)
+#define ENET_BRD_MMFR_TA(base) (ENET_RD_MMFR_TA(base))
+
+/*! @brief Set the TA field to a new value. */
+#define ENET_WR_MMFR_TA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_TA_MASK, ENET_MMFR_TA(value)))
+#define ENET_BWR_MMFR_TA(base, value) (ENET_WR_MMFR_TA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field RA[22:18] (RW)
+ *
+ * Specifies one of up to 32 registers within the specified PHY device.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_RA field. */
+#define ENET_RD_MMFR_RA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_RA_MASK) >> ENET_MMFR_RA_SHIFT)
+#define ENET_BRD_MMFR_RA(base) (ENET_RD_MMFR_RA(base))
+
+/*! @brief Set the RA field to a new value. */
+#define ENET_WR_MMFR_RA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_RA_MASK, ENET_MMFR_RA(value)))
+#define ENET_BWR_MMFR_RA(base, value) (ENET_WR_MMFR_RA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field PA[27:23] (RW)
+ *
+ * Specifies one of up to 32 attached PHY devices.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_PA field. */
+#define ENET_RD_MMFR_PA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_PA_MASK) >> ENET_MMFR_PA_SHIFT)
+#define ENET_BRD_MMFR_PA(base) (ENET_RD_MMFR_PA(base))
+
+/*! @brief Set the PA field to a new value. */
+#define ENET_WR_MMFR_PA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_PA_MASK, ENET_MMFR_PA(value)))
+#define ENET_BWR_MMFR_PA(base, value) (ENET_WR_MMFR_PA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field OP[29:28] (RW)
+ *
+ * Determines the frame operation.
+ *
+ * Values:
+ * - 0b00 - Write frame operation, but not MII compliant.
+ * - 0b01 - Write frame operation for a valid MII management frame.
+ * - 0b10 - Read frame operation for a valid MII management frame.
+ * - 0b11 - Read frame operation, but not MII compliant.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_OP field. */
+#define ENET_RD_MMFR_OP(base) ((ENET_MMFR_REG(base) & ENET_MMFR_OP_MASK) >> ENET_MMFR_OP_SHIFT)
+#define ENET_BRD_MMFR_OP(base) (ENET_RD_MMFR_OP(base))
+
+/*! @brief Set the OP field to a new value. */
+#define ENET_WR_MMFR_OP(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_OP_MASK, ENET_MMFR_OP(value)))
+#define ENET_BWR_MMFR_OP(base, value) (ENET_WR_MMFR_OP(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field ST[31:30] (RW)
+ *
+ * These fields must be programmed to 01 for a valid MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_ST field. */
+#define ENET_RD_MMFR_ST(base) ((ENET_MMFR_REG(base) & ENET_MMFR_ST_MASK) >> ENET_MMFR_ST_SHIFT)
+#define ENET_BRD_MMFR_ST(base) (ENET_RD_MMFR_ST(base))
+
+/*! @brief Set the ST field to a new value. */
+#define ENET_WR_MMFR_ST(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_ST_MASK, ENET_MMFR_ST(value)))
+#define ENET_BWR_MMFR_ST(base, value) (ENET_WR_MMFR_ST(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MSCR - MII Speed Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MSCR - MII Speed Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * MSCR provides control of the MII clock (MDC pin) frequency and allows a
+ * preamble drop on the MII management frame. The MII_SPEED field must be programmed
+ * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
+ * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
+ * a non-zero value to source a read or write management frame. After the
+ * management frame is complete, the MSCR register may optionally be cleared to turn
+ * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
+ * changes during operation. This change takes effect following a rising or falling
+ * edge of MDC. If the internal module clock is 25 MHz, programming this register
+ * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
+ * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
+ * MII_SPEED as a function of internal module clock frequency. Programming Examples
+ * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
+ * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
+ * 0xD 2.36 MHz
+ */
+/*!
+ * @name Constants and macros for entire ENET_MSCR register
+ */
+/*@{*/
+#define ENET_RD_MSCR(base)       (ENET_MSCR_REG(base))
+#define ENET_WR_MSCR(base, value) (ENET_MSCR_REG(base) = (value))
+#define ENET_RMW_MSCR(base, mask, value) (ENET_WR_MSCR(base, (ENET_RD_MSCR(base) & ~(mask)) | (value)))
+#define ENET_SET_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) |  (value)))
+#define ENET_CLR_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) & ~(value)))
+#define ENET_TOG_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MSCR bitfields
+ */
+
+/*!
+ * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
+ *
+ * Controls the frequency of the MII management interface clock (MDC) relative
+ * to the internal module clock. A value of 0 in this field turns off MDC and
+ * leaves it in low voltage state. Any non-zero value results in the MDC frequency
+ * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_MII_SPEED field. */
+#define ENET_RD_MSCR_MII_SPEED(base) ((ENET_MSCR_REG(base) & ENET_MSCR_MII_SPEED_MASK) >> ENET_MSCR_MII_SPEED_SHIFT)
+#define ENET_BRD_MSCR_MII_SPEED(base) (ENET_RD_MSCR_MII_SPEED(base))
+
+/*! @brief Set the MII_SPEED field to a new value. */
+#define ENET_WR_MSCR_MII_SPEED(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_MII_SPEED_MASK, ENET_MSCR_MII_SPEED(value)))
+#define ENET_BWR_MSCR_MII_SPEED(base, value) (ENET_WR_MSCR_MII_SPEED(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
+ *
+ * Enables/disables prepending a preamble to the MII management frame. The MII
+ * standard allows the preamble to be dropped if the attached PHY devices do not
+ * require it.
+ *
+ * Values:
+ * - 0b0 - Preamble enabled.
+ * - 0b1 - Preamble (32 ones) is not prepended to the MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_DIS_PRE field. */
+#define ENET_RD_MSCR_DIS_PRE(base) ((ENET_MSCR_REG(base) & ENET_MSCR_DIS_PRE_MASK) >> ENET_MSCR_DIS_PRE_SHIFT)
+#define ENET_BRD_MSCR_DIS_PRE(base) (BITBAND_ACCESS32(&ENET_MSCR_REG(base), ENET_MSCR_DIS_PRE_SHIFT))
+
+/*! @brief Set the DIS_PRE field to a new value. */
+#define ENET_WR_MSCR_DIS_PRE(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_DIS_PRE_MASK, ENET_MSCR_DIS_PRE(value)))
+#define ENET_BWR_MSCR_DIS_PRE(base, value) (BITBAND_ACCESS32(&ENET_MSCR_REG(base), ENET_MSCR_DIS_PRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
+ *
+ * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
+ * output. Depending on the host bus frequency, the setting may need to be
+ * increased.
+ *
+ * Values:
+ * - 0b000 - 1 internal module clock cycle
+ * - 0b001 - 2 internal module clock cycles
+ * - 0b010 - 3 internal module clock cycles
+ * - 0b111 - 8 internal module clock cycles
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_HOLDTIME field. */
+#define ENET_RD_MSCR_HOLDTIME(base) ((ENET_MSCR_REG(base) & ENET_MSCR_HOLDTIME_MASK) >> ENET_MSCR_HOLDTIME_SHIFT)
+#define ENET_BRD_MSCR_HOLDTIME(base) (ENET_RD_MSCR_HOLDTIME(base))
+
+/*! @brief Set the HOLDTIME field to a new value. */
+#define ENET_WR_MSCR_HOLDTIME(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_HOLDTIME_MASK, ENET_MSCR_HOLDTIME(value)))
+#define ENET_BWR_MSCR_HOLDTIME(base, value) (ENET_WR_MSCR_HOLDTIME(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MIBC - MIB Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MIBC - MIB Control Register (RW)
+ *
+ * Reset value: 0xC0000000U
+ *
+ * MIBC is a read/write register controlling and observing the state of the MIB
+ * block. Access this register to disable the MIB block operation or clear the
+ * MIB counters. The MIB_DIS field resets to 1.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MIBC register
+ */
+/*@{*/
+#define ENET_RD_MIBC(base)       (ENET_MIBC_REG(base))
+#define ENET_WR_MIBC(base, value) (ENET_MIBC_REG(base) = (value))
+#define ENET_RMW_MIBC(base, mask, value) (ENET_WR_MIBC(base, (ENET_RD_MIBC(base) & ~(mask)) | (value)))
+#define ENET_SET_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) |  (value)))
+#define ENET_CLR_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) & ~(value)))
+#define ENET_TOG_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MIBC bitfields
+ */
+
+/*!
+ * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
+ *
+ * If set, all statistics counters are reset to 0. This field is not
+ * self-clearing. To clear the MIB counters set and then clear the field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_CLEAR field. */
+#define ENET_RD_MIBC_MIB_CLEAR(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_CLEAR_MASK) >> ENET_MIBC_MIB_CLEAR_SHIFT)
+#define ENET_BRD_MIBC_MIB_CLEAR(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_CLEAR_SHIFT))
+
+/*! @brief Set the MIB_CLEAR field to a new value. */
+#define ENET_WR_MIBC_MIB_CLEAR(base, value) (ENET_RMW_MIBC(base, ENET_MIBC_MIB_CLEAR_MASK, ENET_MIBC_MIB_CLEAR(value)))
+#define ENET_BWR_MIBC_MIB_CLEAR(base, value) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_CLEAR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
+ *
+ * If this status field is set, the MIB block is not currently updating any MIB
+ * counters.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_IDLE field. */
+#define ENET_RD_MIBC_MIB_IDLE(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_IDLE_MASK) >> ENET_MIBC_MIB_IDLE_SHIFT)
+#define ENET_BRD_MIBC_MIB_IDLE(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
+ *
+ * If this control field is set, the MIB logic halts and does not update any MIB
+ * counters.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_DIS field. */
+#define ENET_RD_MIBC_MIB_DIS(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_DIS_MASK) >> ENET_MIBC_MIB_DIS_SHIFT)
+#define ENET_BRD_MIBC_MIB_DIS(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_DIS_SHIFT))
+
+/*! @brief Set the MIB_DIS field to a new value. */
+#define ENET_WR_MIBC_MIB_DIS(base, value) (ENET_RMW_MIBC(base, ENET_MIBC_MIB_DIS_MASK, ENET_MIBC_MIB_DIS(value)))
+#define ENET_BWR_MIBC_MIB_DIS(base, value) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_DIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RCR - Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RCR - Receive Control Register (RW)
+ *
+ * Reset value: 0x05EE0001U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RCR register
+ */
+/*@{*/
+#define ENET_RD_RCR(base)        (ENET_RCR_REG(base))
+#define ENET_WR_RCR(base, value) (ENET_RCR_REG(base) = (value))
+#define ENET_RMW_RCR(base, mask, value) (ENET_WR_RCR(base, (ENET_RD_RCR(base) & ~(mask)) | (value)))
+#define ENET_SET_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) |  (value)))
+#define ENET_CLR_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) & ~(value)))
+#define ENET_TOG_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RCR bitfields
+ */
+
+/*!
+ * @name Register ENET_RCR, field LOOP[0] (RW)
+ *
+ * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
+ * RMII_MODE must be written to 0.
+ *
+ * Values:
+ * - 0b0 - Loopback disabled.
+ * - 0b1 - Transmitted frames are looped back internal to the device and
+ *     transmit MII output signals are not asserted. DRT must be cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_LOOP field. */
+#define ENET_RD_RCR_LOOP(base) ((ENET_RCR_REG(base) & ENET_RCR_LOOP_MASK) >> ENET_RCR_LOOP_SHIFT)
+#define ENET_BRD_RCR_LOOP(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_LOOP_SHIFT))
+
+/*! @brief Set the LOOP field to a new value. */
+#define ENET_WR_RCR_LOOP(base, value) (ENET_RMW_RCR(base, ENET_RCR_LOOP_MASK, ENET_RCR_LOOP(value)))
+#define ENET_BWR_RCR_LOOP(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_LOOP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field DRT[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Receive path operates independently of transmit. Used for full-duplex
+ *     or to monitor transmit activity in half-duplex mode.
+ * - 0b1 - Disable reception of frames while transmitting. Normally used for
+ *     half-duplex mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_DRT field. */
+#define ENET_RD_RCR_DRT(base) ((ENET_RCR_REG(base) & ENET_RCR_DRT_MASK) >> ENET_RCR_DRT_SHIFT)
+#define ENET_BRD_RCR_DRT(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_DRT_SHIFT))
+
+/*! @brief Set the DRT field to a new value. */
+#define ENET_WR_RCR_DRT(base, value) (ENET_RMW_RCR(base, ENET_RCR_DRT_MASK, ENET_RCR_DRT(value)))
+#define ENET_BWR_RCR_DRT(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_DRT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field MII_MODE[2] (RW)
+ *
+ * This field must always be set.
+ *
+ * Values:
+ * - 0b0 - Reserved.
+ * - 0b1 - MII or RMII mode, as indicated by the RMII_MODE field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_MII_MODE field. */
+#define ENET_RD_RCR_MII_MODE(base) ((ENET_RCR_REG(base) & ENET_RCR_MII_MODE_MASK) >> ENET_RCR_MII_MODE_SHIFT)
+#define ENET_BRD_RCR_MII_MODE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_MII_MODE_SHIFT))
+
+/*! @brief Set the MII_MODE field to a new value. */
+#define ENET_WR_RCR_MII_MODE(base, value) (ENET_RMW_RCR(base, ENET_RCR_MII_MODE_MASK, ENET_RCR_MII_MODE(value)))
+#define ENET_BWR_RCR_MII_MODE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_MII_MODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PROM[3] (RW)
+ *
+ * All frames are accepted regardless of address matching.
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PROM field. */
+#define ENET_RD_RCR_PROM(base) ((ENET_RCR_REG(base) & ENET_RCR_PROM_MASK) >> ENET_RCR_PROM_SHIFT)
+#define ENET_BRD_RCR_PROM(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PROM_SHIFT))
+
+/*! @brief Set the PROM field to a new value. */
+#define ENET_WR_RCR_PROM(base, value) (ENET_RMW_RCR(base, ENET_RCR_PROM_MASK, ENET_RCR_PROM(value)))
+#define ENET_BWR_RCR_PROM(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PROM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field BC_REJ[4] (RW)
+ *
+ * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
+ * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
+ * broadcast DA are accepted and the MISS (M) is set in the receive buffer
+ * descriptor.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_BC_REJ field. */
+#define ENET_RD_RCR_BC_REJ(base) ((ENET_RCR_REG(base) & ENET_RCR_BC_REJ_MASK) >> ENET_RCR_BC_REJ_SHIFT)
+#define ENET_BRD_RCR_BC_REJ(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_BC_REJ_SHIFT))
+
+/*! @brief Set the BC_REJ field to a new value. */
+#define ENET_WR_RCR_BC_REJ(base, value) (ENET_RMW_RCR(base, ENET_RCR_BC_REJ_MASK, ENET_RCR_BC_REJ(value)))
+#define ENET_BWR_RCR_BC_REJ(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_BC_REJ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field FCE[5] (RW)
+ *
+ * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
+ * transmitter stops transmitting data frames for a given duration.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_FCE field. */
+#define ENET_RD_RCR_FCE(base) ((ENET_RCR_REG(base) & ENET_RCR_FCE_MASK) >> ENET_RCR_FCE_SHIFT)
+#define ENET_BRD_RCR_FCE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_FCE_SHIFT))
+
+/*! @brief Set the FCE field to a new value. */
+#define ENET_WR_RCR_FCE(base, value) (ENET_RMW_RCR(base, ENET_RCR_FCE_MASK, ENET_RCR_FCE(value)))
+#define ENET_BWR_RCR_FCE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_FCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field RMII_MODE[8] (RW)
+ *
+ * Specifies whether the MAC is configured for MII mode or RMII operation .
+ *
+ * Values:
+ * - 0b0 - MAC configured for MII mode.
+ * - 0b1 - MAC configured for RMII operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_RMII_MODE field. */
+#define ENET_RD_RCR_RMII_MODE(base) ((ENET_RCR_REG(base) & ENET_RCR_RMII_MODE_MASK) >> ENET_RCR_RMII_MODE_SHIFT)
+#define ENET_BRD_RCR_RMII_MODE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_MODE_SHIFT))
+
+/*! @brief Set the RMII_MODE field to a new value. */
+#define ENET_WR_RCR_RMII_MODE(base, value) (ENET_RMW_RCR(base, ENET_RCR_RMII_MODE_MASK, ENET_RCR_RMII_MODE(value)))
+#define ENET_BWR_RCR_RMII_MODE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_MODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field RMII_10T[9] (RW)
+ *
+ * Enables 10-Mbps mode of the RMII .
+ *
+ * Values:
+ * - 0b0 - 100 Mbps operation.
+ * - 0b1 - 10 Mbps operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_RMII_10T field. */
+#define ENET_RD_RCR_RMII_10T(base) ((ENET_RCR_REG(base) & ENET_RCR_RMII_10T_MASK) >> ENET_RCR_RMII_10T_SHIFT)
+#define ENET_BRD_RCR_RMII_10T(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_10T_SHIFT))
+
+/*! @brief Set the RMII_10T field to a new value. */
+#define ENET_WR_RCR_RMII_10T(base, value) (ENET_RMW_RCR(base, ENET_RCR_RMII_10T_MASK, ENET_RCR_RMII_10T(value)))
+#define ENET_BWR_RCR_RMII_10T(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_10T_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PADEN[12] (RW)
+ *
+ * Specifies whether the MAC removes padding from received frames.
+ *
+ * Values:
+ * - 0b0 - No padding is removed on receive by the MAC.
+ * - 0b1 - Padding is removed from received frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PADEN field. */
+#define ENET_RD_RCR_PADEN(base) ((ENET_RCR_REG(base) & ENET_RCR_PADEN_MASK) >> ENET_RCR_PADEN_SHIFT)
+#define ENET_BRD_RCR_PADEN(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PADEN_SHIFT))
+
+/*! @brief Set the PADEN field to a new value. */
+#define ENET_WR_RCR_PADEN(base, value) (ENET_RMW_RCR(base, ENET_RCR_PADEN_MASK, ENET_RCR_PADEN(value)))
+#define ENET_BWR_RCR_PADEN(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PADEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PAUFWD[13] (RW)
+ *
+ * Specifies whether pause frames are terminated or forwarded.
+ *
+ * Values:
+ * - 0b0 - Pause frames are terminated and discarded in the MAC.
+ * - 0b1 - Pause frames are forwarded to the user application.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PAUFWD field. */
+#define ENET_RD_RCR_PAUFWD(base) ((ENET_RCR_REG(base) & ENET_RCR_PAUFWD_MASK) >> ENET_RCR_PAUFWD_SHIFT)
+#define ENET_BRD_RCR_PAUFWD(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PAUFWD_SHIFT))
+
+/*! @brief Set the PAUFWD field to a new value. */
+#define ENET_WR_RCR_PAUFWD(base, value) (ENET_RMW_RCR(base, ENET_RCR_PAUFWD_MASK, ENET_RCR_PAUFWD(value)))
+#define ENET_BWR_RCR_PAUFWD(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PAUFWD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field CRCFWD[14] (RW)
+ *
+ * Specifies whether the CRC field of received frames is transmitted or
+ * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
+ * field is checked and always terminated and removed.
+ *
+ * Values:
+ * - 0b0 - The CRC field of received frames is transmitted to the user
+ *     application.
+ * - 0b1 - The CRC field is stripped from the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_CRCFWD field. */
+#define ENET_RD_RCR_CRCFWD(base) ((ENET_RCR_REG(base) & ENET_RCR_CRCFWD_MASK) >> ENET_RCR_CRCFWD_SHIFT)
+#define ENET_BRD_RCR_CRCFWD(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CRCFWD_SHIFT))
+
+/*! @brief Set the CRCFWD field to a new value. */
+#define ENET_WR_RCR_CRCFWD(base, value) (ENET_RMW_RCR(base, ENET_RCR_CRCFWD_MASK, ENET_RCR_CRCFWD(value)))
+#define ENET_BWR_RCR_CRCFWD(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CRCFWD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field CFEN[15] (RW)
+ *
+ * Enables/disables the MAC control frame.
+ *
+ * Values:
+ * - 0b0 - MAC control frames with any opcode other than 0x0001 (pause frame)
+ *     are accepted and forwarded to the client interface.
+ * - 0b1 - MAC control frames with any opcode other than 0x0001 (pause frame)
+ *     are silently discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_CFEN field. */
+#define ENET_RD_RCR_CFEN(base) ((ENET_RCR_REG(base) & ENET_RCR_CFEN_MASK) >> ENET_RCR_CFEN_SHIFT)
+#define ENET_BRD_RCR_CFEN(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CFEN_SHIFT))
+
+/*! @brief Set the CFEN field to a new value. */
+#define ENET_WR_RCR_CFEN(base, value) (ENET_RMW_RCR(base, ENET_RCR_CFEN_MASK, ENET_RCR_CFEN(value)))
+#define ENET_BWR_RCR_CFEN(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
+ *
+ * Resets to decimal 1518. Length is measured starting at DA and includes the
+ * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
+ * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
+ * to occur and set the LG field in the end of frame receive buffer descriptor.
+ * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
+ * supported.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_MAX_FL field. */
+#define ENET_RD_RCR_MAX_FL(base) ((ENET_RCR_REG(base) & ENET_RCR_MAX_FL_MASK) >> ENET_RCR_MAX_FL_SHIFT)
+#define ENET_BRD_RCR_MAX_FL(base) (ENET_RD_RCR_MAX_FL(base))
+
+/*! @brief Set the MAX_FL field to a new value. */
+#define ENET_WR_RCR_MAX_FL(base, value) (ENET_RMW_RCR(base, ENET_RCR_MAX_FL_MASK, ENET_RCR_MAX_FL(value)))
+#define ENET_BWR_RCR_MAX_FL(base, value) (ENET_WR_RCR_MAX_FL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field NLC[30] (RW)
+ *
+ * Enables/disables a payload length check.
+ *
+ * Values:
+ * - 0b0 - The payload length check is disabled.
+ * - 0b1 - The core checks the frame's payload length with the frame length/type
+ *     field. Errors are indicated in the EIR[PLC] field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_NLC field. */
+#define ENET_RD_RCR_NLC(base) ((ENET_RCR_REG(base) & ENET_RCR_NLC_MASK) >> ENET_RCR_NLC_SHIFT)
+#define ENET_BRD_RCR_NLC(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_NLC_SHIFT))
+
+/*! @brief Set the NLC field to a new value. */
+#define ENET_WR_RCR_NLC(base, value) (ENET_RMW_RCR(base, ENET_RCR_NLC_MASK, ENET_RCR_NLC(value)))
+#define ENET_BWR_RCR_NLC(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_NLC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field GRS[31] (RO)
+ *
+ * Read-only status indicating that the MAC receive datapath is stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_GRS field. */
+#define ENET_RD_RCR_GRS(base) ((ENET_RCR_REG(base) & ENET_RCR_GRS_MASK) >> ENET_RCR_GRS_SHIFT)
+#define ENET_BRD_RCR_GRS(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_GRS_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCR - Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCR - Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR is read/write and configures the transmit block. This register is cleared
+ * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCR register
+ */
+/*@{*/
+#define ENET_RD_TCR(base)        (ENET_TCR_REG(base))
+#define ENET_WR_TCR(base, value) (ENET_TCR_REG(base) = (value))
+#define ENET_RMW_TCR(base, mask, value) (ENET_WR_TCR(base, (ENET_RD_TCR(base) & ~(mask)) | (value)))
+#define ENET_SET_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) |  (value)))
+#define ENET_CLR_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) & ~(value)))
+#define ENET_TOG_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TCR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCR, field GTS[0] (RW)
+ *
+ * When this field is set, MAC stops transmission after any frame currently
+ * transmitted is complete and EIR[GRA] is set. If frame transmission is not
+ * currently underway, the GRA interrupt is asserted immediately. After transmission
+ * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
+ * transmitted. If an early collision occurs during transmission when GTS is set,
+ * transmission stops after the collision. The frame is transmitted again after GTS is
+ * cleared. There may be old frames in the transmit FIFO that transmit when GTS
+ * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_GTS field. */
+#define ENET_RD_TCR_GTS(base) ((ENET_TCR_REG(base) & ENET_TCR_GTS_MASK) >> ENET_TCR_GTS_SHIFT)
+#define ENET_BRD_TCR_GTS(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_GTS_SHIFT))
+
+/*! @brief Set the GTS field to a new value. */
+#define ENET_WR_TCR_GTS(base, value) (ENET_RMW_TCR(base, ENET_TCR_GTS_MASK, ENET_TCR_GTS(value)))
+#define ENET_BWR_TCR_GTS(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_GTS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field FDEN[2] (RW)
+ *
+ * If this field is set, frames transmit independent of carrier sense and
+ * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_FDEN field. */
+#define ENET_RD_TCR_FDEN(base) ((ENET_TCR_REG(base) & ENET_TCR_FDEN_MASK) >> ENET_TCR_FDEN_SHIFT)
+#define ENET_BRD_TCR_FDEN(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_FDEN_SHIFT))
+
+/*! @brief Set the FDEN field to a new value. */
+#define ENET_WR_TCR_FDEN(base, value) (ENET_RMW_TCR(base, ENET_TCR_FDEN_MASK, ENET_TCR_FDEN(value)))
+#define ENET_BWR_TCR_FDEN(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_FDEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
+ *
+ * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
+ * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
+ * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
+ * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
+ * the MAC may continue transmitting a MAC control PAUSE frame.
+ *
+ * Values:
+ * - 0b0 - No PAUSE frame transmitted.
+ * - 0b1 - The MAC stops transmission of data frames after the current
+ *     transmission is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_TFC_PAUSE field. */
+#define ENET_RD_TCR_TFC_PAUSE(base) ((ENET_TCR_REG(base) & ENET_TCR_TFC_PAUSE_MASK) >> ENET_TCR_TFC_PAUSE_SHIFT)
+#define ENET_BRD_TCR_TFC_PAUSE(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_TFC_PAUSE_SHIFT))
+
+/*! @brief Set the TFC_PAUSE field to a new value. */
+#define ENET_WR_TCR_TFC_PAUSE(base, value) (ENET_RMW_TCR(base, ENET_TCR_TFC_PAUSE_MASK, ENET_TCR_TFC_PAUSE(value)))
+#define ENET_BWR_TCR_TFC_PAUSE(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_TFC_PAUSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
+ *
+ * This status field is set when a full-duplex flow control pause frame is
+ * received and the transmitter pauses for the duration defined in this pause frame.
+ * This field automatically clears when the pause duration is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_RFC_PAUSE field. */
+#define ENET_RD_TCR_RFC_PAUSE(base) ((ENET_TCR_REG(base) & ENET_TCR_RFC_PAUSE_MASK) >> ENET_TCR_RFC_PAUSE_SHIFT)
+#define ENET_BRD_TCR_RFC_PAUSE(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_RFC_PAUSE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
+ *
+ * If ADDINS is set, indicates the MAC address that overwrites the source MAC
+ * address.
+ *
+ * Values:
+ * - 0b000 - Node MAC address programmed on PADDR1/2 registers.
+ * - 0b100 - Reserved.
+ * - 0b101 - Reserved.
+ * - 0b110 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_ADDSEL field. */
+#define ENET_RD_TCR_ADDSEL(base) ((ENET_TCR_REG(base) & ENET_TCR_ADDSEL_MASK) >> ENET_TCR_ADDSEL_SHIFT)
+#define ENET_BRD_TCR_ADDSEL(base) (ENET_RD_TCR_ADDSEL(base))
+
+/*! @brief Set the ADDSEL field to a new value. */
+#define ENET_WR_TCR_ADDSEL(base, value) (ENET_RMW_TCR(base, ENET_TCR_ADDSEL_MASK, ENET_TCR_ADDSEL(value)))
+#define ENET_BWR_TCR_ADDSEL(base, value) (ENET_WR_TCR_ADDSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field ADDINS[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The source MAC address is not modified by the MAC.
+ * - 0b1 - The MAC overwrites the source MAC address with the programmed MAC
+ *     address according to ADDSEL.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_ADDINS field. */
+#define ENET_RD_TCR_ADDINS(base) ((ENET_TCR_REG(base) & ENET_TCR_ADDINS_MASK) >> ENET_TCR_ADDINS_SHIFT)
+#define ENET_BRD_TCR_ADDINS(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_ADDINS_SHIFT))
+
+/*! @brief Set the ADDINS field to a new value. */
+#define ENET_WR_TCR_ADDINS(base, value) (ENET_RMW_TCR(base, ENET_TCR_ADDINS_MASK, ENET_TCR_ADDINS(value)))
+#define ENET_BWR_TCR_ADDINS(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_ADDINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field CRCFWD[9] (RW)
+ *
+ * Values:
+ * - 0b0 - TxBD[TC] controls whether the frame has a CRC from the application.
+ * - 0b1 - The transmitter does not append any CRC to transmitted frames, as it
+ *     is expecting a frame with CRC from the application.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_CRCFWD field. */
+#define ENET_RD_TCR_CRCFWD(base) ((ENET_TCR_REG(base) & ENET_TCR_CRCFWD_MASK) >> ENET_TCR_CRCFWD_SHIFT)
+#define ENET_BRD_TCR_CRCFWD(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_CRCFWD_SHIFT))
+
+/*! @brief Set the CRCFWD field to a new value. */
+#define ENET_WR_TCR_CRCFWD(base, value) (ENET_RMW_TCR(base, ENET_TCR_CRCFWD_MASK, ENET_TCR_CRCFWD(value)))
+#define ENET_BWR_TCR_CRCFWD(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_CRCFWD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_PALR - Physical Address Lower Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_PALR - Physical Address Lower Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
+ * in the address recognition process to compare with the destination address
+ * (DA) field of receive frames with an individual DA. In addition, this register
+ * is used in bytes 0 through 3 of the six-byte source address field when
+ * transmitting PAUSE frames. This register is not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_PALR register
+ */
+/*@{*/
+#define ENET_RD_PALR(base)       (ENET_PALR_REG(base))
+#define ENET_WR_PALR(base, value) (ENET_PALR_REG(base) = (value))
+#define ENET_RMW_PALR(base, mask, value) (ENET_WR_PALR(base, (ENET_RD_PALR(base) & ~(mask)) | (value)))
+#define ENET_SET_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) |  (value)))
+#define ENET_CLR_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) & ~(value)))
+#define ENET_TOG_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_PAUR - Physical Address Upper Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_PAUR - Physical Address Upper Register (RW)
+ *
+ * Reset value: 0x00008808U
+ *
+ * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
+ * the address recognition process to compare with the destination address (DA)
+ * field of receive frames with an individual DA. In addition, this register is
+ * used in bytes 4 and 5 of the six-byte source address field when transmitting
+ * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
+ * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
+ * you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_PAUR register
+ */
+/*@{*/
+#define ENET_RD_PAUR(base)       (ENET_PAUR_REG(base))
+#define ENET_WR_PAUR(base, value) (ENET_PAUR_REG(base) = (value))
+#define ENET_RMW_PAUR(base, mask, value) (ENET_WR_PAUR(base, (ENET_RD_PAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) |  (value)))
+#define ENET_CLR_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) & ~(value)))
+#define ENET_TOG_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_PAUR bitfields
+ */
+
+/*!
+ * @name Register ENET_PAUR, field TYPE[15:0] (RO)
+ *
+ * These fields have a constant value of 0x8808.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_PAUR_TYPE field. */
+#define ENET_RD_PAUR_TYPE(base) ((ENET_PAUR_REG(base) & ENET_PAUR_TYPE_MASK) >> ENET_PAUR_TYPE_SHIFT)
+#define ENET_BRD_PAUR_TYPE(base) (ENET_RD_PAUR_TYPE(base))
+/*@}*/
+
+/*!
+ * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
+ *
+ * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
+ * for exact match, and the source address field in PAUSE frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_PAUR_PADDR2 field. */
+#define ENET_RD_PAUR_PADDR2(base) ((ENET_PAUR_REG(base) & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT)
+#define ENET_BRD_PAUR_PADDR2(base) (ENET_RD_PAUR_PADDR2(base))
+
+/*! @brief Set the PADDR2 field to a new value. */
+#define ENET_WR_PAUR_PADDR2(base, value) (ENET_RMW_PAUR(base, ENET_PAUR_PADDR2_MASK, ENET_PAUR_PADDR2(value)))
+#define ENET_BWR_PAUR_PADDR2(base, value) (ENET_WR_PAUR_PADDR2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_OPD - Opcode/Pause Duration Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_OPD - Opcode/Pause Duration Register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * OPD is read/write accessible. This register contains the 16-bit opcode and
+ * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
+ * field is a constant value, 0x0001. When another node detects a PAUSE frame,
+ * that node pauses transmission for the duration specified in the pause duration
+ * field. The lower 16 bits of this register are not reset and you must initialize
+ * it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_OPD register
+ */
+/*@{*/
+#define ENET_RD_OPD(base)        (ENET_OPD_REG(base))
+#define ENET_WR_OPD(base, value) (ENET_OPD_REG(base) = (value))
+#define ENET_RMW_OPD(base, mask, value) (ENET_WR_OPD(base, (ENET_RD_OPD(base) & ~(mask)) | (value)))
+#define ENET_SET_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) |  (value)))
+#define ENET_CLR_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) & ~(value)))
+#define ENET_TOG_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_OPD bitfields
+ */
+
+/*!
+ * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
+ *
+ * Pause duration field used in PAUSE frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_OPD_PAUSE_DUR field. */
+#define ENET_RD_OPD_PAUSE_DUR(base) ((ENET_OPD_REG(base) & ENET_OPD_PAUSE_DUR_MASK) >> ENET_OPD_PAUSE_DUR_SHIFT)
+#define ENET_BRD_OPD_PAUSE_DUR(base) (ENET_RD_OPD_PAUSE_DUR(base))
+
+/*! @brief Set the PAUSE_DUR field to a new value. */
+#define ENET_WR_OPD_PAUSE_DUR(base, value) (ENET_RMW_OPD(base, ENET_OPD_PAUSE_DUR_MASK, ENET_OPD_PAUSE_DUR(value)))
+#define ENET_BWR_OPD_PAUSE_DUR(base, value) (ENET_WR_OPD_PAUSE_DUR(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_OPD, field OPCODE[31:16] (RO)
+ *
+ * These fields have a constant value of 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_OPD_OPCODE field. */
+#define ENET_RD_OPD_OPCODE(base) ((ENET_OPD_REG(base) & ENET_OPD_OPCODE_MASK) >> ENET_OPD_OPCODE_SHIFT)
+#define ENET_BRD_OPD_OPCODE(base) (ENET_RD_OPD_OPCODE(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IAUR - Descriptor Individual Upper Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IAUR - Descriptor Individual Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the destination address (DA) field of receive frames with an individual
+ * DA. This register is not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IAUR register
+ */
+/*@{*/
+#define ENET_RD_IAUR(base)       (ENET_IAUR_REG(base))
+#define ENET_WR_IAUR(base, value) (ENET_IAUR_REG(base) = (value))
+#define ENET_RMW_IAUR(base, mask, value) (ENET_WR_IAUR(base, (ENET_RD_IAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) |  (value)))
+#define ENET_CLR_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) & ~(value)))
+#define ENET_TOG_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IALR - Descriptor Individual Lower Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IALR - Descriptor Individual Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IALR contains the lower 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the DA field of receive frames with an individual DA. This register is
+ * not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IALR register
+ */
+/*@{*/
+#define ENET_RD_IALR(base)       (ENET_IALR_REG(base))
+#define ENET_WR_IALR(base, value) (ENET_IALR_REG(base) = (value))
+#define ENET_RMW_IALR(base, mask, value) (ENET_WR_IALR(base, (ENET_RD_IALR(base) & ~(mask)) | (value)))
+#define ENET_SET_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) |  (value)))
+#define ENET_CLR_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) & ~(value)))
+#define ENET_TOG_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_GAUR - Descriptor Group Upper Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_GAUR - Descriptor Group Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+/*!
+ * @name Constants and macros for entire ENET_GAUR register
+ */
+/*@{*/
+#define ENET_RD_GAUR(base)       (ENET_GAUR_REG(base))
+#define ENET_WR_GAUR(base, value) (ENET_GAUR_REG(base) = (value))
+#define ENET_RMW_GAUR(base, mask, value) (ENET_WR_GAUR(base, (ENET_RD_GAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) |  (value)))
+#define ENET_CLR_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) & ~(value)))
+#define ENET_TOG_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_GALR - Descriptor Group Lower Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_GALR - Descriptor Group Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GALR contains the lower 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+/*!
+ * @name Constants and macros for entire ENET_GALR register
+ */
+/*@{*/
+#define ENET_RD_GALR(base)       (ENET_GALR_REG(base))
+#define ENET_WR_GALR(base, value) (ENET_GALR_REG(base) = (value))
+#define ENET_RMW_GALR(base, mask, value) (ENET_WR_GALR(base, (ENET_RD_GALR(base) & ~(mask)) | (value)))
+#define ENET_SET_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) |  (value)))
+#define ENET_CLR_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) & ~(value)))
+#define ENET_TOG_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TFWR - Transmit FIFO Watermark Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TFWR - Transmit FIFO Watermark Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
+ * in the transmit FIFO before transmission of a frame can begin. This allows you
+ * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
+ * latency (TFWR = 11) due to contention for the system bus. Setting the
+ * watermark to a high value minimizes the risk of transmit FIFO underrun due to
+ * contention for the system bus. The byte counts associated with the TFWR field may need
+ * to be modified to match a given system requirement. For example, worst case
+ * bus access latency by the transmit data DMA channel. When the FIFO level
+ * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
+ * transmit control logic starts frame transmission even before the end-of-frame is
+ * available in the FIFO (cut-through operation). If a complete frame has a size
+ * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
+ * to the line. To enable store and forward on the Transmit path, set STR_FWD to
+ * '1'. In this case, the MAC starts to transmit data only when a complete frame
+ * is stored in the Transmit FIFO.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TFWR register
+ */
+/*@{*/
+#define ENET_RD_TFWR(base)       (ENET_TFWR_REG(base))
+#define ENET_WR_TFWR(base, value) (ENET_TFWR_REG(base) = (value))
+#define ENET_RMW_TFWR(base, mask, value) (ENET_WR_TFWR(base, (ENET_RD_TFWR(base) & ~(mask)) | (value)))
+#define ENET_SET_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) |  (value)))
+#define ENET_CLR_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) & ~(value)))
+#define ENET_TOG_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TFWR bitfields
+ */
+
+/*!
+ * @name Register ENET_TFWR, field TFWR[5:0] (RW)
+ *
+ * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
+ * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
+ * begins. If a frame with less than the threshold is written, it is still sent
+ * independently of this threshold setting. The threshold is relevant only if the
+ * frame is larger than the threshold given. This chip may not support the maximum
+ * number of bytes written shown below. See the chip-specific information for the
+ * ENET module for this value.
+ *
+ * Values:
+ * - 0b000000 - 64 bytes written.
+ * - 0b000001 - 64 bytes written.
+ * - 0b000010 - 128 bytes written.
+ * - 0b000011 - 192 bytes written.
+ * - 0b111110 - 3968 bytes written.
+ * - 0b111111 - 4032 bytes written.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TFWR_TFWR field. */
+#define ENET_RD_TFWR_TFWR(base) ((ENET_TFWR_REG(base) & ENET_TFWR_TFWR_MASK) >> ENET_TFWR_TFWR_SHIFT)
+#define ENET_BRD_TFWR_TFWR(base) (ENET_RD_TFWR_TFWR(base))
+
+/*! @brief Set the TFWR field to a new value. */
+#define ENET_WR_TFWR_TFWR(base, value) (ENET_RMW_TFWR(base, ENET_TFWR_TFWR_MASK, ENET_TFWR_TFWR(value)))
+#define ENET_BWR_TFWR_TFWR(base, value) (ENET_WR_TFWR_TFWR(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TFWR, field STRFWD[8] (RW)
+ *
+ * Values:
+ * - 0b0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
+ * - 0b1 - Enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TFWR_STRFWD field. */
+#define ENET_RD_TFWR_STRFWD(base) ((ENET_TFWR_REG(base) & ENET_TFWR_STRFWD_MASK) >> ENET_TFWR_STRFWD_SHIFT)
+#define ENET_BRD_TFWR_STRFWD(base) (BITBAND_ACCESS32(&ENET_TFWR_REG(base), ENET_TFWR_STRFWD_SHIFT))
+
+/*! @brief Set the STRFWD field to a new value. */
+#define ENET_WR_TFWR_STRFWD(base, value) (ENET_RMW_TFWR(base, ENET_TFWR_STRFWD_MASK, ENET_TFWR_STRFWD(value)))
+#define ENET_BWR_TFWR_STRFWD(base, value) (BITBAND_ACCESS32(&ENET_TFWR_REG(base), ENET_TFWR_STRFWD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RDSR - Receive Descriptor Ring Start Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RDSR - Receive Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDSR points to the beginning of the circular receive buffer descriptor queue
+ * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
+ * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
+ * by 16. This register must be initialized prior to operation
+ */
+/*!
+ * @name Constants and macros for entire ENET_RDSR register
+ */
+/*@{*/
+#define ENET_RD_RDSR(base)       (ENET_RDSR_REG(base))
+#define ENET_WR_RDSR(base, value) (ENET_RDSR_REG(base) = (value))
+#define ENET_RMW_RDSR(base, mask, value) (ENET_WR_RDSR(base, (ENET_RD_RDSR(base) & ~(mask)) | (value)))
+#define ENET_SET_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) |  (value)))
+#define ENET_CLR_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) & ~(value)))
+#define ENET_TOG_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the receive buffer descriptor queue.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RDSR_R_DES_START field. */
+#define ENET_RD_RDSR_R_DES_START(base) ((ENET_RDSR_REG(base) & ENET_RDSR_R_DES_START_MASK) >> ENET_RDSR_R_DES_START_SHIFT)
+#define ENET_BRD_RDSR_R_DES_START(base) (ENET_RD_RDSR_R_DES_START(base))
+
+/*! @brief Set the R_DES_START field to a new value. */
+#define ENET_WR_RDSR_R_DES_START(base, value) (ENET_RMW_RDSR(base, ENET_RDSR_R_DES_START_MASK, ENET_RDSR_R_DES_START(value)))
+#define ENET_BWR_RDSR_R_DES_START(base, value) (ENET_WR_RDSR_R_DES_START(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TDSR provides a pointer to the beginning of the circular transmit buffer
+ * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
+ * must be zero); however, it is recommended to be 128-bit aligned, that is,
+ * evenly divisible by 16. This register must be initialized prior to operation.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TDSR register
+ */
+/*@{*/
+#define ENET_RD_TDSR(base)       (ENET_TDSR_REG(base))
+#define ENET_WR_TDSR(base, value) (ENET_TDSR_REG(base) = (value))
+#define ENET_RMW_TDSR(base, mask, value) (ENET_WR_TDSR(base, (ENET_RD_TDSR(base) & ~(mask)) | (value)))
+#define ENET_SET_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) |  (value)))
+#define ENET_CLR_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) & ~(value)))
+#define ENET_TOG_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the transmit buffer descriptor queue.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TDSR_X_DES_START field. */
+#define ENET_RD_TDSR_X_DES_START(base) ((ENET_TDSR_REG(base) & ENET_TDSR_X_DES_START_MASK) >> ENET_TDSR_X_DES_START_SHIFT)
+#define ENET_BRD_TDSR_X_DES_START(base) (ENET_RD_TDSR_X_DES_START(base))
+
+/*! @brief Set the X_DES_START field to a new value. */
+#define ENET_WR_TDSR_X_DES_START(base, value) (ENET_RMW_TDSR(base, ENET_TDSR_X_DES_START_MASK, ENET_TDSR_X_DES_START(value)))
+#define ENET_BWR_TDSR_X_DES_START(base, value) (ENET_WR_TDSR_X_DES_START(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MRBR - Maximum Receive Buffer Size Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MRBR - Maximum Receive Buffer Size Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MRBR is a user-programmable register that dictates the maximum size of
+ * all receive buffers. This value should take into consideration that the receive
+ * CRC is always written into the last receive buffer. To allow one maximum size
+ * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
+ * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
+ * set to zero by the device. To minimize bus usage (descriptor fetches), set
+ * MRBR greater than or equal to 256 bytes. This register must be initialized
+ * before operation.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MRBR register
+ */
+/*@{*/
+#define ENET_RD_MRBR(base)       (ENET_MRBR_REG(base))
+#define ENET_WR_MRBR(base, value) (ENET_MRBR_REG(base) = (value))
+#define ENET_RMW_MRBR(base, mask, value) (ENET_WR_MRBR(base, (ENET_RD_MRBR(base) & ~(mask)) | (value)))
+#define ENET_SET_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) |  (value)))
+#define ENET_CLR_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) & ~(value)))
+#define ENET_TOG_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MRBR bitfields
+ */
+
+/*!
+ * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
+ *
+ * Receive buffer size in bytes.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field. */
+#define ENET_RD_MRBR_R_BUF_SIZE(base) ((ENET_MRBR_REG(base) & ENET_MRBR_R_BUF_SIZE_MASK) >> ENET_MRBR_R_BUF_SIZE_SHIFT)
+#define ENET_BRD_MRBR_R_BUF_SIZE(base) (ENET_RD_MRBR_R_BUF_SIZE(base))
+
+/*! @brief Set the R_BUF_SIZE field to a new value. */
+#define ENET_WR_MRBR_R_BUF_SIZE(base, value) (ENET_RMW_MRBR(base, ENET_MRBR_R_BUF_SIZE_MASK, ENET_MRBR_R_BUF_SIZE(value)))
+#define ENET_BWR_MRBR_R_BUF_SIZE(base, value) (ENET_WR_MRBR_R_BUF_SIZE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RSFL - Receive FIFO Section Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RSFL - Receive FIFO Section Full Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RSFL register
+ */
+/*@{*/
+#define ENET_RD_RSFL(base)       (ENET_RSFL_REG(base))
+#define ENET_WR_RSFL(base, value) (ENET_RSFL_REG(base) = (value))
+#define ENET_RMW_RSFL(base, mask, value) (ENET_WR_RSFL(base, (ENET_RD_RSFL(base) & ~(mask)) | (value)))
+#define ENET_SET_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) |  (value)))
+#define ENET_CLR_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) & ~(value)))
+#define ENET_TOG_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RSFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
+ * this field to enable store and forward on the RX FIFO. When programming a value
+ * greater than 0 (cut-through operation), it must be greater than
+ * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
+ * in the Receive FIFO (cut-through operation).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field. */
+#define ENET_RD_RSFL_RX_SECTION_FULL(base) ((ENET_RSFL_REG(base) & ENET_RSFL_RX_SECTION_FULL_MASK) >> ENET_RSFL_RX_SECTION_FULL_SHIFT)
+#define ENET_BRD_RSFL_RX_SECTION_FULL(base) (ENET_RD_RSFL_RX_SECTION_FULL(base))
+
+/*! @brief Set the RX_SECTION_FULL field to a new value. */
+#define ENET_WR_RSFL_RX_SECTION_FULL(base, value) (ENET_RMW_RSFL(base, ENET_RSFL_RX_SECTION_FULL_MASK, ENET_RSFL_RX_SECTION_FULL(value)))
+#define ENET_BWR_RSFL_RX_SECTION_FULL(base, value) (ENET_WR_RSFL_RX_SECTION_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RSEM - Receive FIFO Section Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RSEM register
+ */
+/*@{*/
+#define ENET_RD_RSEM(base)       (ENET_RSEM_REG(base))
+#define ENET_WR_RSEM(base, value) (ENET_RSEM_REG(base) = (value))
+#define ENET_RMW_RSEM(base, mask, value) (ENET_WR_RSEM(base, (ENET_RD_RSEM(base) & ~(mask)) | (value)))
+#define ENET_SET_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) |  (value)))
+#define ENET_CLR_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) & ~(value)))
+#define ENET_TOG_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
+ * FIFO has reached this level, a pause frame will be issued. A value of 0
+ * disables automatic pause frame generation. When the FIFO level goes below the value
+ * programmed in this field, an XON pause frame is issued to indicate the FIFO
+ * congestion is cleared to the remote Ethernet client. The section-empty
+ * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field. */
+#define ENET_RD_RSEM_RX_SECTION_EMPTY(base) ((ENET_RSEM_REG(base) & ENET_RSEM_RX_SECTION_EMPTY_MASK) >> ENET_RSEM_RX_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_RSEM_RX_SECTION_EMPTY(base) (ENET_RD_RSEM_RX_SECTION_EMPTY(base))
+
+/*! @brief Set the RX_SECTION_EMPTY field to a new value. */
+#define ENET_WR_RSEM_RX_SECTION_EMPTY(base, value) (ENET_RMW_RSEM(base, ENET_RSEM_RX_SECTION_EMPTY_MASK, ENET_RSEM_RX_SECTION_EMPTY(value)))
+#define ENET_BWR_RSEM_RX_SECTION_EMPTY(base, value) (ENET_WR_RSEM_RX_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
+ *
+ * Defines number of frames in the receive FIFO, independent of its size, that
+ * can be accepted. If the limit is reached, reception will continue normally,
+ * however a pause frame will be triggered to indicate a possible congestion to the
+ * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
+ * frame generation
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field. */
+#define ENET_RD_RSEM_STAT_SECTION_EMPTY(base) ((ENET_RSEM_REG(base) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) >> ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_RSEM_STAT_SECTION_EMPTY(base) (ENET_RD_RSEM_STAT_SECTION_EMPTY(base))
+
+/*! @brief Set the STAT_SECTION_EMPTY field to a new value. */
+#define ENET_WR_RSEM_STAT_SECTION_EMPTY(base, value) (ENET_RMW_RSEM(base, ENET_RSEM_STAT_SECTION_EMPTY_MASK, ENET_RSEM_STAT_SECTION_EMPTY(value)))
+#define ENET_BWR_RSEM_STAT_SECTION_EMPTY(base, value) (ENET_WR_RSEM_STAT_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RAEM - Receive FIFO Almost Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RAEM register
+ */
+/*@{*/
+#define ENET_RD_RAEM(base)       (ENET_RAEM_REG(base))
+#define ENET_WR_RAEM(base, value) (ENET_RAEM_REG(base) = (value))
+#define ENET_RMW_RAEM(base, mask, value) (ENET_WR_RAEM(base, (ENET_RD_RAEM(base) & ~(mask)) | (value)))
+#define ENET_SET_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) |  (value)))
+#define ENET_CLR_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) & ~(value)))
+#define ENET_TOG_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field and the end-of-frame has
+ * not been received for the frame yet, the core receive read control stops FIFO
+ * read (and subsequently stops transferring data to the MAC client
+ * application). It continues to deliver the frame, if again more data than the threshold or
+ * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field. */
+#define ENET_RD_RAEM_RX_ALMOST_EMPTY(base) ((ENET_RAEM_REG(base) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) >> ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)
+#define ENET_BRD_RAEM_RX_ALMOST_EMPTY(base) (ENET_RD_RAEM_RX_ALMOST_EMPTY(base))
+
+/*! @brief Set the RX_ALMOST_EMPTY field to a new value. */
+#define ENET_WR_RAEM_RX_ALMOST_EMPTY(base, value) (ENET_RMW_RAEM(base, ENET_RAEM_RX_ALMOST_EMPTY_MASK, ENET_RAEM_RX_ALMOST_EMPTY(value)))
+#define ENET_BWR_RAEM_RX_ALMOST_EMPTY(base, value) (ENET_WR_RAEM_RX_ALMOST_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RAFL - Receive FIFO Almost Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RAFL register
+ */
+/*@{*/
+#define ENET_RD_RAFL(base)       (ENET_RAFL_REG(base))
+#define ENET_WR_RAFL(base, value) (ENET_RAFL_REG(base) = (value))
+#define ENET_RMW_RAFL(base, mask, value) (ENET_WR_RAFL(base, (ENET_RD_RAFL(base) & ~(mask)) | (value)))
+#define ENET_SET_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) |  (value)))
+#define ENET_CLR_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) & ~(value)))
+#define ENET_TOG_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
+ * truncates the received frame to avoid FIFO overflow. The corresponding error
+ * status will be set when the frame is delivered to the application. A minimum
+ * value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field. */
+#define ENET_RD_RAFL_RX_ALMOST_FULL(base) ((ENET_RAFL_REG(base) & ENET_RAFL_RX_ALMOST_FULL_MASK) >> ENET_RAFL_RX_ALMOST_FULL_SHIFT)
+#define ENET_BRD_RAFL_RX_ALMOST_FULL(base) (ENET_RD_RAFL_RX_ALMOST_FULL(base))
+
+/*! @brief Set the RX_ALMOST_FULL field to a new value. */
+#define ENET_WR_RAFL_RX_ALMOST_FULL(base, value) (ENET_RMW_RAFL(base, ENET_RAFL_RX_ALMOST_FULL_MASK, ENET_RAFL_RX_ALMOST_FULL(value)))
+#define ENET_BWR_RAFL_RX_ALMOST_FULL(base, value) (ENET_WR_RAFL_RX_ALMOST_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TSEM - Transmit FIFO Section Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TSEM register
+ */
+/*@{*/
+#define ENET_RD_TSEM(base)       (ENET_TSEM_REG(base))
+#define ENET_WR_TSEM(base, value) (ENET_TSEM_REG(base) = (value))
+#define ENET_RMW_TSEM(base, mask, value) (ENET_WR_TSEM(base, (ENET_RD_TSEM(base) & ~(mask)) | (value)))
+#define ENET_SET_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) |  (value)))
+#define ENET_CLR_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) & ~(value)))
+#define ENET_TOG_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field. */
+#define ENET_RD_TSEM_TX_SECTION_EMPTY(base) ((ENET_TSEM_REG(base) & ENET_TSEM_TX_SECTION_EMPTY_MASK) >> ENET_TSEM_TX_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_TSEM_TX_SECTION_EMPTY(base) (ENET_RD_TSEM_TX_SECTION_EMPTY(base))
+
+/*! @brief Set the TX_SECTION_EMPTY field to a new value. */
+#define ENET_WR_TSEM_TX_SECTION_EMPTY(base, value) (ENET_RMW_TSEM(base, ENET_TSEM_TX_SECTION_EMPTY_MASK, ENET_TSEM_TX_SECTION_EMPTY(value)))
+#define ENET_BWR_TSEM_TX_SECTION_EMPTY(base, value) (ENET_WR_TSEM_TX_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TAEM register
+ */
+/*@{*/
+#define ENET_RD_TAEM(base)       (ENET_TAEM_REG(base))
+#define ENET_WR_TAEM(base, value) (ENET_TAEM_REG(base) = (value))
+#define ENET_RMW_TAEM(base, mask, value) (ENET_WR_TAEM(base, (ENET_RD_TAEM(base) & ~(mask)) | (value)))
+#define ENET_SET_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) |  (value)))
+#define ENET_CLR_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) & ~(value)))
+#define ENET_TOG_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field, and no end-of-frame is
+ * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
+ * stops reading the FIFO and transmits a frame with an MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A minimum value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field. */
+#define ENET_RD_TAEM_TX_ALMOST_EMPTY(base) ((ENET_TAEM_REG(base) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) >> ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)
+#define ENET_BRD_TAEM_TX_ALMOST_EMPTY(base) (ENET_RD_TAEM_TX_ALMOST_EMPTY(base))
+
+/*! @brief Set the TX_ALMOST_EMPTY field to a new value. */
+#define ENET_WR_TAEM_TX_ALMOST_EMPTY(base, value) (ENET_RMW_TAEM(base, ENET_TAEM_TX_ALMOST_EMPTY_MASK, ENET_TAEM_TX_ALMOST_EMPTY(value)))
+#define ENET_BWR_TAEM_TX_ALMOST_EMPTY(base, value) (ENET_WR_TAEM_TX_ALMOST_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TAFL - Transmit FIFO Almost Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000008U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TAFL register
+ */
+/*@{*/
+#define ENET_RD_TAFL(base)       (ENET_TAFL_REG(base))
+#define ENET_WR_TAFL(base, value) (ENET_TAFL_REG(base) = (value))
+#define ENET_RMW_TAFL(base, mask, value) (ENET_WR_TAFL(base, (ENET_RD_TAFL(base) & ~(mask)) | (value)))
+#define ENET_SET_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) |  (value)))
+#define ENET_CLR_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) & ~(value)))
+#define ENET_TOG_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
+ * value of six is required . A recommended value of at least 8 should be set
+ * allowing a latency of two clock cycles to the application. If more latency is
+ * required the value can be increased as necessary (latency = TAFL - 5). When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
+ * application does not react on this signal, the FIFO write control logic, to
+ * avoid FIFO overflow, truncates the current frame and sets the error status. As a
+ * result, the frame will be transmitted with an GMII/MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A FIFO overflow is a fatal error and requires
+ * a global reset on the transmit datapath or at least deassertion of ETHEREN.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field. */
+#define ENET_RD_TAFL_TX_ALMOST_FULL(base) ((ENET_TAFL_REG(base) & ENET_TAFL_TX_ALMOST_FULL_MASK) >> ENET_TAFL_TX_ALMOST_FULL_SHIFT)
+#define ENET_BRD_TAFL_TX_ALMOST_FULL(base) (ENET_RD_TAFL_TX_ALMOST_FULL(base))
+
+/*! @brief Set the TX_ALMOST_FULL field to a new value. */
+#define ENET_WR_TAFL_TX_ALMOST_FULL(base, value) (ENET_RMW_TAFL(base, ENET_TAFL_TX_ALMOST_FULL_MASK, ENET_TAFL_TX_ALMOST_FULL(value)))
+#define ENET_BWR_TAFL_TX_ALMOST_FULL(base, value) (ENET_WR_TAFL_TX_ALMOST_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TIPG - Transmit Inter-Packet Gap
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TIPG - Transmit Inter-Packet Gap (RW)
+ *
+ * Reset value: 0x0000000CU
+ */
+/*!
+ * @name Constants and macros for entire ENET_TIPG register
+ */
+/*@{*/
+#define ENET_RD_TIPG(base)       (ENET_TIPG_REG(base))
+#define ENET_WR_TIPG(base, value) (ENET_TIPG_REG(base) = (value))
+#define ENET_RMW_TIPG(base, mask, value) (ENET_WR_TIPG(base, (ENET_RD_TIPG(base) & ~(mask)) | (value)))
+#define ENET_SET_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) |  (value)))
+#define ENET_CLR_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) & ~(value)))
+#define ENET_TOG_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TIPG bitfields
+ */
+
+/*!
+ * @name Register ENET_TIPG, field IPG[4:0] (RW)
+ *
+ * Indicates the IPG, in bytes, between transmitted frames. Valid values range
+ * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
+ * 27, the IPG is 27.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TIPG_IPG field. */
+#define ENET_RD_TIPG_IPG(base) ((ENET_TIPG_REG(base) & ENET_TIPG_IPG_MASK) >> ENET_TIPG_IPG_SHIFT)
+#define ENET_BRD_TIPG_IPG(base) (ENET_RD_TIPG_IPG(base))
+
+/*! @brief Set the IPG field to a new value. */
+#define ENET_WR_TIPG_IPG(base, value) (ENET_RMW_TIPG(base, ENET_TIPG_IPG_MASK, ENET_TIPG_IPG(value)))
+#define ENET_BWR_TIPG_IPG(base, value) (ENET_WR_TIPG_IPG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_FTRL - Frame Truncation Length
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_FTRL - Frame Truncation Length (RW)
+ *
+ * Reset value: 0x000007FFU
+ */
+/*!
+ * @name Constants and macros for entire ENET_FTRL register
+ */
+/*@{*/
+#define ENET_RD_FTRL(base)       (ENET_FTRL_REG(base))
+#define ENET_WR_FTRL(base, value) (ENET_FTRL_REG(base) = (value))
+#define ENET_RMW_FTRL(base, mask, value) (ENET_WR_FTRL(base, (ENET_RD_FTRL(base) & ~(mask)) | (value)))
+#define ENET_SET_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) |  (value)))
+#define ENET_CLR_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) & ~(value)))
+#define ENET_TOG_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_FTRL bitfields
+ */
+
+/*!
+ * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
+ *
+ * Indicates the value a receive frame is truncated, if it is greater than this
+ * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
+ * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
+ * less data, guaranteeing that it never receives more than the set limit.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_FTRL_TRUNC_FL field. */
+#define ENET_RD_FTRL_TRUNC_FL(base) ((ENET_FTRL_REG(base) & ENET_FTRL_TRUNC_FL_MASK) >> ENET_FTRL_TRUNC_FL_SHIFT)
+#define ENET_BRD_FTRL_TRUNC_FL(base) (ENET_RD_FTRL_TRUNC_FL(base))
+
+/*! @brief Set the TRUNC_FL field to a new value. */
+#define ENET_WR_FTRL_TRUNC_FL(base, value) (ENET_RMW_FTRL(base, ENET_FTRL_TRUNC_FL_MASK, ENET_FTRL_TRUNC_FL(value)))
+#define ENET_BWR_FTRL_TRUNC_FL(base, value) (ENET_WR_FTRL_TRUNC_FL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TACC - Transmit Accelerator Function Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TACC - Transmit Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TACC controls accelerator actions when sending frames. The register can be
+ * changed before or after each frame, but it must remain unmodified during frame
+ * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
+ * checksum feature.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TACC register
+ */
+/*@{*/
+#define ENET_RD_TACC(base)       (ENET_TACC_REG(base))
+#define ENET_WR_TACC(base, value) (ENET_TACC_REG(base) = (value))
+#define ENET_RMW_TACC(base, mask, value) (ENET_WR_TACC(base, (ENET_RD_TACC(base) & ~(mask)) | (value)))
+#define ENET_SET_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) |  (value)))
+#define ENET_CLR_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) & ~(value)))
+#define ENET_TOG_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TACC bitfields
+ */
+
+/*!
+ * @name Register ENET_TACC, field SHIFT16[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Indicates to the transmit data FIFO that the written frames contain
+ *     two additional octets before the frame data. This means the actual frame
+ *     begins at bit 16 of the first word written into the FIFO. This function
+ *     allows putting the frame payload on a 32-bit boundary in memory, as the
+ *     14-byte Ethernet header is extended to a 16-byte header.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_SHIFT16 field. */
+#define ENET_RD_TACC_SHIFT16(base) ((ENET_TACC_REG(base) & ENET_TACC_SHIFT16_MASK) >> ENET_TACC_SHIFT16_SHIFT)
+#define ENET_BRD_TACC_SHIFT16(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_SHIFT16_SHIFT))
+
+/*! @brief Set the SHIFT16 field to a new value. */
+#define ENET_WR_TACC_SHIFT16(base, value) (ENET_RMW_TACC(base, ENET_TACC_SHIFT16_MASK, ENET_TACC_SHIFT16(value)))
+#define ENET_BWR_TACC_SHIFT16(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_SHIFT16_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TACC, field IPCHK[3] (RW)
+ *
+ * Enables insertion of IP header checksum.
+ *
+ * Values:
+ * - 0b0 - Checksum is not inserted.
+ * - 0b1 - If an IP frame is transmitted, the checksum is inserted
+ *     automatically. The IP header checksum field must be cleared. If a non-IP frame is
+ *     transmitted the frame is not modified.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_IPCHK field. */
+#define ENET_RD_TACC_IPCHK(base) ((ENET_TACC_REG(base) & ENET_TACC_IPCHK_MASK) >> ENET_TACC_IPCHK_SHIFT)
+#define ENET_BRD_TACC_IPCHK(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_IPCHK_SHIFT))
+
+/*! @brief Set the IPCHK field to a new value. */
+#define ENET_WR_TACC_IPCHK(base, value) (ENET_RMW_TACC(base, ENET_TACC_IPCHK_MASK, ENET_TACC_IPCHK(value)))
+#define ENET_BWR_TACC_IPCHK(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_IPCHK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TACC, field PROCHK[4] (RW)
+ *
+ * Enables insertion of protocol checksum.
+ *
+ * Values:
+ * - 0b0 - Checksum not inserted.
+ * - 0b1 - If an IP frame with a known protocol is transmitted, the checksum is
+ *     inserted automatically into the frame. The checksum field must be cleared.
+ *     The other frames are not modified.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_PROCHK field. */
+#define ENET_RD_TACC_PROCHK(base) ((ENET_TACC_REG(base) & ENET_TACC_PROCHK_MASK) >> ENET_TACC_PROCHK_SHIFT)
+#define ENET_BRD_TACC_PROCHK(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_PROCHK_SHIFT))
+
+/*! @brief Set the PROCHK field to a new value. */
+#define ENET_WR_TACC_PROCHK(base, value) (ENET_RMW_TACC(base, ENET_TACC_PROCHK_MASK, ENET_TACC_PROCHK(value)))
+#define ENET_BWR_TACC_PROCHK(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_PROCHK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RACC - Receive Accelerator Function Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RACC - Receive Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RACC register
+ */
+/*@{*/
+#define ENET_RD_RACC(base)       (ENET_RACC_REG(base))
+#define ENET_WR_RACC(base, value) (ENET_RACC_REG(base) = (value))
+#define ENET_RMW_RACC(base, mask, value) (ENET_WR_RACC(base, (ENET_RD_RACC(base) & ~(mask)) | (value)))
+#define ENET_SET_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) |  (value)))
+#define ENET_CLR_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) & ~(value)))
+#define ENET_TOG_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RACC bitfields
+ */
+
+/*!
+ * @name Register ENET_RACC, field PADREM[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Padding not removed.
+ * - 0b1 - Any bytes following the IP payload section of the frame are removed
+ *     from the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_PADREM field. */
+#define ENET_RD_RACC_PADREM(base) ((ENET_RACC_REG(base) & ENET_RACC_PADREM_MASK) >> ENET_RACC_PADREM_SHIFT)
+#define ENET_BRD_RACC_PADREM(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PADREM_SHIFT))
+
+/*! @brief Set the PADREM field to a new value. */
+#define ENET_WR_RACC_PADREM(base, value) (ENET_RMW_RACC(base, ENET_RACC_PADREM_MASK, ENET_RACC_PADREM(value)))
+#define ENET_BWR_RACC_PADREM(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PADREM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field IPDIS[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with wrong IPv4 header checksum are not discarded.
+ * - 0b1 - If an IPv4 frame is received with a mismatching header checksum, the
+ *     frame is discarded. IPv6 has no header checksum and is not affected by
+ *     this setting. Discarding is only available when the RX FIFO operates in store
+ *     and forward mode (RSFL cleared).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_IPDIS field. */
+#define ENET_RD_RACC_IPDIS(base) ((ENET_RACC_REG(base) & ENET_RACC_IPDIS_MASK) >> ENET_RACC_IPDIS_SHIFT)
+#define ENET_BRD_RACC_IPDIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_IPDIS_SHIFT))
+
+/*! @brief Set the IPDIS field to a new value. */
+#define ENET_WR_RACC_IPDIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_IPDIS_MASK, ENET_RACC_IPDIS(value)))
+#define ENET_BWR_RACC_IPDIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_IPDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field PRODIS[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with wrong checksum are not discarded.
+ * - 0b1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong
+ *     TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only
+ *     available when the RX FIFO operates in store and forward mode (RSFL cleared).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_PRODIS field. */
+#define ENET_RD_RACC_PRODIS(base) ((ENET_RACC_REG(base) & ENET_RACC_PRODIS_MASK) >> ENET_RACC_PRODIS_SHIFT)
+#define ENET_BRD_RACC_PRODIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PRODIS_SHIFT))
+
+/*! @brief Set the PRODIS field to a new value. */
+#define ENET_WR_RACC_PRODIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_PRODIS_MASK, ENET_RACC_PRODIS(value)))
+#define ENET_BWR_RACC_PRODIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PRODIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field LINEDIS[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with errors are not discarded.
+ * - 0b1 - Any frame received with a CRC, length, or PHY error is automatically
+ *     discarded and not forwarded to the user application interface.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_LINEDIS field. */
+#define ENET_RD_RACC_LINEDIS(base) ((ENET_RACC_REG(base) & ENET_RACC_LINEDIS_MASK) >> ENET_RACC_LINEDIS_SHIFT)
+#define ENET_BRD_RACC_LINEDIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_LINEDIS_SHIFT))
+
+/*! @brief Set the LINEDIS field to a new value. */
+#define ENET_WR_RACC_LINEDIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_LINEDIS_MASK, ENET_RACC_LINEDIS(value)))
+#define ENET_BWR_RACC_LINEDIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_LINEDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field SHIFT16[7] (RW)
+ *
+ * When this field is set, the actual frame data starts at bit 16 of the first
+ * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
+ * This function only affects the FIFO storage and has no influence on the
+ * statistics, which use the actual length of the frame received.
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Instructs the MAC to write two additional bytes in front of each
+ *     frame received into the RX FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_SHIFT16 field. */
+#define ENET_RD_RACC_SHIFT16(base) ((ENET_RACC_REG(base) & ENET_RACC_SHIFT16_MASK) >> ENET_RACC_SHIFT16_SHIFT)
+#define ENET_BRD_RACC_SHIFT16(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_SHIFT16_SHIFT))
+
+/*! @brief Set the SHIFT16 field to a new value. */
+#define ENET_WR_RACC_SHIFT16(base, value) (ENET_RMW_RACC(base, ENET_RACC_SHIFT16_MASK, ENET_RACC_SHIFT16(value)))
+#define ENET_BWR_RACC_SHIFT16(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_SHIFT16_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_PACKETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_PACKETS(base) (ENET_RMON_T_PACKETS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field. */
+#define ENET_RD_RMON_T_PACKETS_TXPKTS(base) ((ENET_RMON_T_PACKETS_REG(base) & ENET_RMON_T_PACKETS_TXPKTS_MASK) >> ENET_RMON_T_PACKETS_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_PACKETS_TXPKTS(base) (ENET_RD_RMON_T_PACKETS_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RMON Tx Broadcast Packets
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_BC_PKT(base) (ENET_RMON_T_BC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field. */
+#define ENET_RD_RMON_T_BC_PKT_TXPKTS(base) ((ENET_RMON_T_BC_PKT_REG(base) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) >> ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_BC_PKT_TXPKTS(base) (ENET_RD_RMON_T_BC_PKT_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_MC_PKT(base) (ENET_RMON_T_MC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field. */
+#define ENET_RD_RMON_T_MC_PKT_TXPKTS(base) ((ENET_RMON_T_MC_PKT_REG(base) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) >> ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_MC_PKT_TXPKTS(base) (ENET_RD_RMON_T_MC_PKT_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_CRC_ALIGN(base) (ENET_RMON_T_CRC_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field. */
+#define ENET_RD_RMON_T_CRC_ALIGN_TXPKTS(base) ((ENET_RMON_T_CRC_ALIGN_REG(base) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) >> ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_CRC_ALIGN_TXPKTS(base) (ENET_RD_RMON_T_CRC_ALIGN_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_UNDERSIZE(base) (ENET_RMON_T_UNDERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field. */
+#define ENET_RD_RMON_T_UNDERSIZE_TXPKTS(base) ((ENET_RMON_T_UNDERSIZE_REG(base) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) >> ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_UNDERSIZE_TXPKTS(base) (ENET_RD_RMON_T_UNDERSIZE_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_OVERSIZE(base) (ENET_RMON_T_OVERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field. */
+#define ENET_RD_RMON_T_OVERSIZE_TXPKTS(base) ((ENET_RMON_T_OVERSIZE_REG(base) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) >> ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_OVERSIZE_TXPKTS(base) (ENET_RD_RMON_T_OVERSIZE_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_FRAG register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_FRAG(base) (ENET_RMON_T_FRAG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field. */
+#define ENET_RD_RMON_T_FRAG_TXPKTS(base) ((ENET_RMON_T_FRAG_REG(base) & ENET_RMON_T_FRAG_TXPKTS_MASK) >> ENET_RMON_T_FRAG_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_FRAG_TXPKTS(base) (ENET_RD_RMON_T_FRAG_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_JAB register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_JAB(base) (ENET_RMON_T_JAB_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field. */
+#define ENET_RD_RMON_T_JAB_TXPKTS(base) ((ENET_RMON_T_JAB_REG(base) & ENET_RMON_T_JAB_TXPKTS_MASK) >> ENET_RMON_T_JAB_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_JAB_TXPKTS(base) (ENET_RD_RMON_T_JAB_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_COL register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_COL(base) (ENET_RMON_T_COL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_COL bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field. */
+#define ENET_RD_RMON_T_COL_TXPKTS(base) ((ENET_RMON_T_COL_REG(base) & ENET_RMON_T_COL_TXPKTS_MASK) >> ENET_RMON_T_COL_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_COL_TXPKTS(base) (ENET_RD_RMON_T_COL_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P64 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P64(base) (ENET_RMON_T_P64_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field. */
+#define ENET_RD_RMON_T_P64_TXPKTS(base) ((ENET_RMON_T_P64_REG(base) & ENET_RMON_T_P64_TXPKTS_MASK) >> ENET_RMON_T_P64_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P64_TXPKTS(base) (ENET_RD_RMON_T_P64_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P65TO127(base) (ENET_RMON_T_P65TO127_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field. */
+#define ENET_RD_RMON_T_P65TO127_TXPKTS(base) ((ENET_RMON_T_P65TO127_REG(base) & ENET_RMON_T_P65TO127_TXPKTS_MASK) >> ENET_RMON_T_P65TO127_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P65TO127_TXPKTS(base) (ENET_RD_RMON_T_P65TO127_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P128TO255(base) (ENET_RMON_T_P128TO255_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field. */
+#define ENET_RD_RMON_T_P128TO255_TXPKTS(base) ((ENET_RMON_T_P128TO255_REG(base) & ENET_RMON_T_P128TO255_TXPKTS_MASK) >> ENET_RMON_T_P128TO255_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P128TO255_TXPKTS(base) (ENET_RD_RMON_T_P128TO255_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P256TO511(base) (ENET_RMON_T_P256TO511_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field. */
+#define ENET_RD_RMON_T_P256TO511_TXPKTS(base) ((ENET_RMON_T_P256TO511_REG(base) & ENET_RMON_T_P256TO511_TXPKTS_MASK) >> ENET_RMON_T_P256TO511_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P256TO511_TXPKTS(base) (ENET_RD_RMON_T_P256TO511_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P512TO1023(base) (ENET_RMON_T_P512TO1023_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field. */
+#define ENET_RD_RMON_T_P512TO1023_TXPKTS(base) ((ENET_RMON_T_P512TO1023_REG(base) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) >> ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P512TO1023_TXPKTS(base) (ENET_RD_RMON_T_P512TO1023_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P1024TO2047(base) (ENET_RMON_T_P1024TO2047_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field. */
+#define ENET_RD_RMON_T_P1024TO2047_TXPKTS(base) ((ENET_RMON_T_P1024TO2047_REG(base) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) >> ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P1024TO2047_TXPKTS(base) (ENET_RD_RMON_T_P1024TO2047_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P_GTE2048(base) (ENET_RMON_T_P_GTE2048_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field. */
+#define ENET_RD_RMON_T_P_GTE2048_TXPKTS(base) ((ENET_RMON_T_P_GTE2048_REG(base) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) >> ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P_GTE2048_TXPKTS(base) (ENET_RD_RMON_T_P_GTE2048_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OCTETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_OCTETS(base) (ENET_RMON_T_OCTETS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_FRAME_OK(base) (ENET_IEEE_T_FRAME_OK_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field. */
+#define ENET_RD_IEEE_T_FRAME_OK_COUNT(base) ((ENET_IEEE_T_FRAME_OK_REG(base) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) >> ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_FRAME_OK_COUNT(base) (ENET_RD_IEEE_T_FRAME_OK_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_1COL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_1COL(base) (ENET_IEEE_T_1COL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_1COL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field. */
+#define ENET_RD_IEEE_T_1COL_COUNT(base) ((ENET_IEEE_T_1COL_REG(base) & ENET_IEEE_T_1COL_COUNT_MASK) >> ENET_IEEE_T_1COL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_1COL_COUNT(base) (ENET_RD_IEEE_T_1COL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_MCOL(base) (ENET_IEEE_T_MCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field. */
+#define ENET_RD_IEEE_T_MCOL_COUNT(base) ((ENET_IEEE_T_MCOL_REG(base) & ENET_IEEE_T_MCOL_COUNT_MASK) >> ENET_IEEE_T_MCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_MCOL_COUNT(base) (ENET_RD_IEEE_T_MCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_DEF register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_DEF(base) (ENET_IEEE_T_DEF_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_DEF bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field. */
+#define ENET_RD_IEEE_T_DEF_COUNT(base) ((ENET_IEEE_T_DEF_REG(base) & ENET_IEEE_T_DEF_COUNT_MASK) >> ENET_IEEE_T_DEF_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_DEF_COUNT(base) (ENET_RD_IEEE_T_DEF_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_LCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_LCOL(base) (ENET_IEEE_T_LCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field. */
+#define ENET_RD_IEEE_T_LCOL_COUNT(base) ((ENET_IEEE_T_LCOL_REG(base) & ENET_IEEE_T_LCOL_COUNT_MASK) >> ENET_IEEE_T_LCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_LCOL_COUNT(base) (ENET_RD_IEEE_T_LCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_EXCOL(base) (ENET_IEEE_T_EXCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field. */
+#define ENET_RD_IEEE_T_EXCOL_COUNT(base) ((ENET_IEEE_T_EXCOL_REG(base) & ENET_IEEE_T_EXCOL_COUNT_MASK) >> ENET_IEEE_T_EXCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_EXCOL_COUNT(base) (ENET_RD_IEEE_T_EXCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MACERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_MACERR(base) (ENET_IEEE_T_MACERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field. */
+#define ENET_RD_IEEE_T_MACERR_COUNT(base) ((ENET_IEEE_T_MACERR_REG(base) & ENET_IEEE_T_MACERR_COUNT_MASK) >> ENET_IEEE_T_MACERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_MACERR_COUNT(base) (ENET_RD_IEEE_T_MACERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_CSERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_CSERR(base) (ENET_IEEE_T_CSERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field. */
+#define ENET_RD_IEEE_T_CSERR_COUNT(base) ((ENET_IEEE_T_CSERR_REG(base) & ENET_IEEE_T_CSERR_COUNT_MASK) >> ENET_IEEE_T_CSERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_CSERR_COUNT(base) (ENET_RD_IEEE_T_CSERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_FDXFC(base) (ENET_IEEE_T_FDXFC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field. */
+#define ENET_RD_IEEE_T_FDXFC_COUNT(base) ((ENET_IEEE_T_FDXFC_REG(base) & ENET_IEEE_T_FDXFC_COUNT_MASK) >> ENET_IEEE_T_FDXFC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_FDXFC_COUNT(base) (ENET_RD_IEEE_T_FDXFC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counts total octets (includes header and FCS fields).
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_OCTETS_OK(base) (ENET_IEEE_T_OCTETS_OK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_PACKETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_PACKETS(base) (ENET_RMON_R_PACKETS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field. */
+#define ENET_RD_RMON_R_PACKETS_COUNT(base) ((ENET_RMON_R_PACKETS_REG(base) & ENET_RMON_R_PACKETS_COUNT_MASK) >> ENET_RMON_R_PACKETS_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_PACKETS_COUNT(base) (ENET_RD_RMON_R_PACKETS_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_BC_PKT(base) (ENET_RMON_R_BC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field. */
+#define ENET_RD_RMON_R_BC_PKT_COUNT(base) ((ENET_RMON_R_BC_PKT_REG(base) & ENET_RMON_R_BC_PKT_COUNT_MASK) >> ENET_RMON_R_BC_PKT_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_BC_PKT_COUNT(base) (ENET_RD_RMON_R_BC_PKT_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_MC_PKT(base) (ENET_RMON_R_MC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field. */
+#define ENET_RD_RMON_R_MC_PKT_COUNT(base) ((ENET_RMON_R_MC_PKT_REG(base) & ENET_RMON_R_MC_PKT_COUNT_MASK) >> ENET_RMON_R_MC_PKT_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_MC_PKT_COUNT(base) (ENET_RD_RMON_R_MC_PKT_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_CRC_ALIGN(base) (ENET_RMON_R_CRC_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field. */
+#define ENET_RD_RMON_R_CRC_ALIGN_COUNT(base) ((ENET_RMON_R_CRC_ALIGN_REG(base) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) >> ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_CRC_ALIGN_COUNT(base) (ENET_RD_RMON_R_CRC_ALIGN_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_UNDERSIZE(base) (ENET_RMON_R_UNDERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field. */
+#define ENET_RD_RMON_R_UNDERSIZE_COUNT(base) ((ENET_RMON_R_UNDERSIZE_REG(base) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) >> ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_UNDERSIZE_COUNT(base) (ENET_RD_RMON_R_UNDERSIZE_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_OVERSIZE(base) (ENET_RMON_R_OVERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field. */
+#define ENET_RD_RMON_R_OVERSIZE_COUNT(base) ((ENET_RMON_R_OVERSIZE_REG(base) & ENET_RMON_R_OVERSIZE_COUNT_MASK) >> ENET_RMON_R_OVERSIZE_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_OVERSIZE_COUNT(base) (ENET_RD_RMON_R_OVERSIZE_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_FRAG register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_FRAG(base) (ENET_RMON_R_FRAG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field. */
+#define ENET_RD_RMON_R_FRAG_COUNT(base) ((ENET_RMON_R_FRAG_REG(base) & ENET_RMON_R_FRAG_COUNT_MASK) >> ENET_RMON_R_FRAG_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_FRAG_COUNT(base) (ENET_RD_RMON_R_FRAG_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_JAB register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_JAB(base) (ENET_RMON_R_JAB_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_JAB_COUNT field. */
+#define ENET_RD_RMON_R_JAB_COUNT(base) ((ENET_RMON_R_JAB_REG(base) & ENET_RMON_R_JAB_COUNT_MASK) >> ENET_RMON_R_JAB_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_JAB_COUNT(base) (ENET_RD_RMON_R_JAB_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P64 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P64(base) (ENET_RMON_R_P64_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P64_COUNT field. */
+#define ENET_RD_RMON_R_P64_COUNT(base) ((ENET_RMON_R_P64_REG(base) & ENET_RMON_R_P64_COUNT_MASK) >> ENET_RMON_R_P64_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P64_COUNT(base) (ENET_RD_RMON_R_P64_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P65TO127(base) (ENET_RMON_R_P65TO127_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field. */
+#define ENET_RD_RMON_R_P65TO127_COUNT(base) ((ENET_RMON_R_P65TO127_REG(base) & ENET_RMON_R_P65TO127_COUNT_MASK) >> ENET_RMON_R_P65TO127_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P65TO127_COUNT(base) (ENET_RD_RMON_R_P65TO127_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P128TO255(base) (ENET_RMON_R_P128TO255_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field. */
+#define ENET_RD_RMON_R_P128TO255_COUNT(base) ((ENET_RMON_R_P128TO255_REG(base) & ENET_RMON_R_P128TO255_COUNT_MASK) >> ENET_RMON_R_P128TO255_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P128TO255_COUNT(base) (ENET_RD_RMON_R_P128TO255_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P256TO511(base) (ENET_RMON_R_P256TO511_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field. */
+#define ENET_RD_RMON_R_P256TO511_COUNT(base) ((ENET_RMON_R_P256TO511_REG(base) & ENET_RMON_R_P256TO511_COUNT_MASK) >> ENET_RMON_R_P256TO511_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P256TO511_COUNT(base) (ENET_RD_RMON_R_P256TO511_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P512TO1023(base) (ENET_RMON_R_P512TO1023_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field. */
+#define ENET_RD_RMON_R_P512TO1023_COUNT(base) ((ENET_RMON_R_P512TO1023_REG(base) & ENET_RMON_R_P512TO1023_COUNT_MASK) >> ENET_RMON_R_P512TO1023_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P512TO1023_COUNT(base) (ENET_RD_RMON_R_P512TO1023_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P1024TO2047(base) (ENET_RMON_R_P1024TO2047_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field. */
+#define ENET_RD_RMON_R_P1024TO2047_COUNT(base) ((ENET_RMON_R_P1024TO2047_REG(base) & ENET_RMON_R_P1024TO2047_COUNT_MASK) >> ENET_RMON_R_P1024TO2047_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P1024TO2047_COUNT(base) (ENET_RD_RMON_R_P1024TO2047_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P_GTE2048 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P_GTE2048(base) (ENET_RMON_R_P_GTE2048_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P_GTE2048, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P_GTE2048_COUNT field. */
+#define ENET_RD_RMON_R_P_GTE2048_COUNT(base) ((ENET_RMON_R_P_GTE2048_REG(base) & ENET_RMON_R_P_GTE2048_COUNT_MASK) >> ENET_RMON_R_P_GTE2048_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P_GTE2048_COUNT(base) (ENET_RD_RMON_R_P_GTE2048_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OCTETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_OCTETS(base) (ENET_RMON_R_OCTETS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counter increments if a frame with invalid or missing SFD character is
+ * detected and has been dropped. None of the other counters increments if this counter
+ * increments.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_DROP register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_DROP(base) (ENET_IEEE_R_DROP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_DROP bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field. */
+#define ENET_RD_IEEE_R_DROP_COUNT(base) ((ENET_IEEE_R_DROP_REG(base) & ENET_IEEE_R_DROP_COUNT_MASK) >> ENET_IEEE_R_DROP_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_DROP_COUNT(base) (ENET_RD_IEEE_R_DROP_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_FRAME_OK(base) (ENET_IEEE_R_FRAME_OK_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field. */
+#define ENET_RD_IEEE_R_FRAME_OK_COUNT(base) ((ENET_IEEE_R_FRAME_OK_REG(base) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) >> ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_FRAME_OK_COUNT(base) (ENET_RD_IEEE_R_FRAME_OK_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_CRC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_CRC(base) (ENET_IEEE_R_CRC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_CRC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field. */
+#define ENET_RD_IEEE_R_CRC_COUNT(base) ((ENET_IEEE_R_CRC_REG(base) & ENET_IEEE_R_CRC_COUNT_MASK) >> ENET_IEEE_R_CRC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_CRC_COUNT(base) (ENET_RD_IEEE_R_CRC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_ALIGN(base) (ENET_IEEE_R_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field. */
+#define ENET_RD_IEEE_R_ALIGN_COUNT(base) ((ENET_IEEE_R_ALIGN_REG(base) & ENET_IEEE_R_ALIGN_COUNT_MASK) >> ENET_IEEE_R_ALIGN_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_ALIGN_COUNT(base) (ENET_RD_IEEE_R_ALIGN_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_MACERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_MACERR(base) (ENET_IEEE_R_MACERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field. */
+#define ENET_RD_IEEE_R_MACERR_COUNT(base) ((ENET_IEEE_R_MACERR_REG(base) & ENET_IEEE_R_MACERR_COUNT_MASK) >> ENET_IEEE_R_MACERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_MACERR_COUNT(base) (ENET_RD_IEEE_R_MACERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_FDXFC(base) (ENET_IEEE_R_FDXFC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field. */
+#define ENET_RD_IEEE_R_FDXFC_COUNT(base) ((ENET_IEEE_R_FDXFC_REG(base) & ENET_IEEE_R_FDXFC_COUNT_MASK) >> ENET_IEEE_R_FDXFC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_FDXFC_COUNT(base) (ENET_RD_IEEE_R_FDXFC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_OCTETS_OK(base) (ENET_IEEE_R_OCTETS_OK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATCR - Adjustable Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATCR - Adjustable Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * ATCR command fields can trigger the corresponding events directly. It is not
+ * necessary to preserve any of the configuration fields when a command field is
+ * set in the register, that is, no read-modify-write is required. The fields are
+ * automatically cleared after the command completes.
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATCR register
+ */
+/*@{*/
+#define ENET_RD_ATCR(base)       (ENET_ATCR_REG(base))
+#define ENET_WR_ATCR(base, value) (ENET_ATCR_REG(base) = (value))
+#define ENET_RMW_ATCR(base, mask, value) (ENET_WR_ATCR(base, (ENET_RD_ATCR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) |  (value)))
+#define ENET_CLR_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) & ~(value)))
+#define ENET_TOG_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATCR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCR, field EN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer stops at the current value.
+ * - 0b1 - The timer starts incrementing.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_EN field. */
+#define ENET_RD_ATCR_EN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_EN_MASK) >> ENET_ATCR_EN_SHIFT)
+#define ENET_BRD_ATCR_EN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_EN_SHIFT))
+
+/*! @brief Set the EN field to a new value. */
+#define ENET_WR_ATCR_EN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_EN_MASK, ENET_ATCR_EN(value)))
+#define ENET_BWR_ATCR_EN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field OFFEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - The timer can be reset to zero when the given offset time is reached
+ *     (offset event). The field is cleared when the offset event is reached, so
+ *     no further event occurs until the field is set again. The timer offset
+ *     value must be set before setting this field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_OFFEN field. */
+#define ENET_RD_ATCR_OFFEN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_OFFEN_MASK) >> ENET_ATCR_OFFEN_SHIFT)
+#define ENET_BRD_ATCR_OFFEN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFEN_SHIFT))
+
+/*! @brief Set the OFFEN field to a new value. */
+#define ENET_WR_ATCR_OFFEN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_OFFEN_MASK, ENET_ATCR_OFFEN(value)))
+#define ENET_BWR_ATCR_OFFEN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field OFFRST[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer is not affected and no action occurs, besides clearing
+ *     OFFEN, when the offset is reached.
+ * - 0b1 - If OFFEN is set, the timer resets to zero when the offset setting is
+ *     reached. The offset event does not cause a timer interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_OFFRST field. */
+#define ENET_RD_ATCR_OFFRST(base) ((ENET_ATCR_REG(base) & ENET_ATCR_OFFRST_MASK) >> ENET_ATCR_OFFRST_SHIFT)
+#define ENET_BRD_ATCR_OFFRST(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFRST_SHIFT))
+
+/*! @brief Set the OFFRST field to a new value. */
+#define ENET_WR_ATCR_OFFRST(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_OFFRST_MASK, ENET_ATCR_OFFRST(value)))
+#define ENET_BWR_ATCR_OFFRST(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field PEREN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the
+ *     event signal output is asserted when the timer wraps around according to the
+ *     periodic setting ATPER. The timer period value must be set before setting
+ *     this bit. Not all devices contain the event signal output. See the chip
+ *     configuration details.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_PEREN field. */
+#define ENET_RD_ATCR_PEREN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_PEREN_MASK) >> ENET_ATCR_PEREN_SHIFT)
+#define ENET_BRD_ATCR_PEREN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PEREN_SHIFT))
+
+/*! @brief Set the PEREN field to a new value. */
+#define ENET_WR_ATCR_PEREN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_PEREN_MASK, ENET_ATCR_PEREN(value)))
+#define ENET_BWR_ATCR_PEREN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field PINPER[7] (RW)
+ *
+ * Enables event signal output assertion on period event. Not all devices
+ * contain the event signal output. See the chip configuration details.
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - Enable.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_PINPER field. */
+#define ENET_RD_ATCR_PINPER(base) ((ENET_ATCR_REG(base) & ENET_ATCR_PINPER_MASK) >> ENET_ATCR_PINPER_SHIFT)
+#define ENET_BRD_ATCR_PINPER(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PINPER_SHIFT))
+
+/*! @brief Set the PINPER field to a new value. */
+#define ENET_WR_ATCR_PINPER(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_PINPER_MASK, ENET_ATCR_PINPER(value)))
+#define ENET_BWR_ATCR_PINPER(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PINPER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field RESTART[9] (RW)
+ *
+ * Resets the timer to zero. This has no effect on the counter enable. If the
+ * counter is enabled when this field is set, the timer is reset to zero and starts
+ * counting from there. When set, all other fields are ignored during a write.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_RESTART field. */
+#define ENET_RD_ATCR_RESTART(base) ((ENET_ATCR_REG(base) & ENET_ATCR_RESTART_MASK) >> ENET_ATCR_RESTART_SHIFT)
+#define ENET_BRD_ATCR_RESTART(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_RESTART_SHIFT))
+
+/*! @brief Set the RESTART field to a new value. */
+#define ENET_WR_ATCR_RESTART(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_RESTART_MASK, ENET_ATCR_RESTART(value)))
+#define ENET_BWR_ATCR_RESTART(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_RESTART_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field CAPTURE[11] (RW)
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - The current time is captured and can be read from the ATVR register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_CAPTURE field. */
+#define ENET_RD_ATCR_CAPTURE(base) ((ENET_ATCR_REG(base) & ENET_ATCR_CAPTURE_MASK) >> ENET_ATCR_CAPTURE_SHIFT)
+#define ENET_BRD_ATCR_CAPTURE(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_CAPTURE_SHIFT))
+
+/*! @brief Set the CAPTURE field to a new value. */
+#define ENET_WR_ATCR_CAPTURE(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_CAPTURE_MASK, ENET_ATCR_CAPTURE(value)))
+#define ENET_BWR_ATCR_CAPTURE(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_CAPTURE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field SLAVE[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer is active and all configuration fields in this register are
+ *     relevant.
+ * - 0b1 - The internal timer is disabled and the externally provided timer
+ *     value is used. All other fields, except CAPTURE, in this register have no
+ *     effect. CAPTURE can still be used to capture the current timer value.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_SLAVE field. */
+#define ENET_RD_ATCR_SLAVE(base) ((ENET_ATCR_REG(base) & ENET_ATCR_SLAVE_MASK) >> ENET_ATCR_SLAVE_SHIFT)
+#define ENET_BRD_ATCR_SLAVE(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_SLAVE_SHIFT))
+
+/*! @brief Set the SLAVE field to a new value. */
+#define ENET_WR_ATCR_SLAVE(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_SLAVE_MASK, ENET_ATCR_SLAVE(value)))
+#define ENET_BWR_ATCR_SLAVE(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_SLAVE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATVR - Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATVR - Timer Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATVR register
+ */
+/*@{*/
+#define ENET_RD_ATVR(base)       (ENET_ATVR_REG(base))
+#define ENET_WR_ATVR(base, value) (ENET_ATVR_REG(base) = (value))
+#define ENET_RMW_ATVR(base, mask, value) (ENET_WR_ATVR(base, (ENET_RD_ATVR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) |  (value)))
+#define ENET_CLR_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) & ~(value)))
+#define ENET_TOG_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATOFF - Timer Offset Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATOFF - Timer Offset Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATOFF register
+ */
+/*@{*/
+#define ENET_RD_ATOFF(base)      (ENET_ATOFF_REG(base))
+#define ENET_WR_ATOFF(base, value) (ENET_ATOFF_REG(base) = (value))
+#define ENET_RMW_ATOFF(base, mask, value) (ENET_WR_ATOFF(base, (ENET_RD_ATOFF(base) & ~(mask)) | (value)))
+#define ENET_SET_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) |  (value)))
+#define ENET_CLR_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) & ~(value)))
+#define ENET_TOG_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATPER - Timer Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATPER - Timer Period Register (RW)
+ *
+ * Reset value: 0x3B9ACA00U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATPER register
+ */
+/*@{*/
+#define ENET_RD_ATPER(base)      (ENET_ATPER_REG(base))
+#define ENET_WR_ATPER(base, value) (ENET_ATPER_REG(base) = (value))
+#define ENET_RMW_ATPER(base, mask, value) (ENET_WR_ATPER(base, (ENET_RD_ATPER(base) & ~(mask)) | (value)))
+#define ENET_SET_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) |  (value)))
+#define ENET_CLR_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) & ~(value)))
+#define ENET_TOG_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATCOR - Timer Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATCOR - Timer Correction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATCOR register
+ */
+/*@{*/
+#define ENET_RD_ATCOR(base)      (ENET_ATCOR_REG(base))
+#define ENET_WR_ATCOR(base, value) (ENET_ATCOR_REG(base) = (value))
+#define ENET_RMW_ATCOR(base, mask, value) (ENET_WR_ATCOR(base, (ENET_RD_ATCOR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) |  (value)))
+#define ENET_CLR_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) & ~(value)))
+#define ENET_TOG_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATCOR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCOR, field COR[30:0] (RW)
+ *
+ * Defines after how many timer clock cycles (ts_clk) the correction counter
+ * should be reset and trigger a correction increment on the timer. The amount of
+ * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
+ * counter and no corrections occur. This value is given in clock cycles, not in
+ * nanoseconds as all other values.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCOR_COR field. */
+#define ENET_RD_ATCOR_COR(base) ((ENET_ATCOR_REG(base) & ENET_ATCOR_COR_MASK) >> ENET_ATCOR_COR_SHIFT)
+#define ENET_BRD_ATCOR_COR(base) (ENET_RD_ATCOR_COR(base))
+
+/*! @brief Set the COR field to a new value. */
+#define ENET_WR_ATCOR_COR(base, value) (ENET_RMW_ATCOR(base, ENET_ATCOR_COR_MASK, ENET_ATCOR_COR(value)))
+#define ENET_BWR_ATCOR_COR(base, value) (ENET_WR_ATCOR_COR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATINC - Time-Stamping Clock Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATINC - Time-Stamping Clock Period Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATINC register
+ */
+/*@{*/
+#define ENET_RD_ATINC(base)      (ENET_ATINC_REG(base))
+#define ENET_WR_ATINC(base, value) (ENET_ATINC_REG(base) = (value))
+#define ENET_RMW_ATINC(base, mask, value) (ENET_WR_ATINC(base, (ENET_RD_ATINC(base) & ~(mask)) | (value)))
+#define ENET_SET_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) |  (value)))
+#define ENET_CLR_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) & ~(value)))
+#define ENET_TOG_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATINC bitfields
+ */
+
+/*!
+ * @name Register ENET_ATINC, field INC[6:0] (RW)
+ *
+ * The timer increments by this amount each clock cycle. For example, set to 10
+ * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
+ * that is an integer fraction of the period set in ATPER.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATINC_INC field. */
+#define ENET_RD_ATINC_INC(base) ((ENET_ATINC_REG(base) & ENET_ATINC_INC_MASK) >> ENET_ATINC_INC_SHIFT)
+#define ENET_BRD_ATINC_INC(base) (ENET_RD_ATINC_INC(base))
+
+/*! @brief Set the INC field to a new value. */
+#define ENET_WR_ATINC_INC(base, value) (ENET_RMW_ATINC(base, ENET_ATINC_INC_MASK, ENET_ATINC_INC(value)))
+#define ENET_BWR_ATINC_INC(base, value) (ENET_WR_ATINC_INC(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
+ *
+ * This value is added every time the correction timer expires (every clock
+ * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
+ * than INC speeds up the timer.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATINC_INC_CORR field. */
+#define ENET_RD_ATINC_INC_CORR(base) ((ENET_ATINC_REG(base) & ENET_ATINC_INC_CORR_MASK) >> ENET_ATINC_INC_CORR_SHIFT)
+#define ENET_BRD_ATINC_INC_CORR(base) (ENET_RD_ATINC_INC_CORR(base))
+
+/*! @brief Set the INC_CORR field to a new value. */
+#define ENET_WR_ATINC_INC_CORR(base, value) (ENET_RMW_ATINC(base, ENET_ATINC_INC_CORR_MASK, ENET_ATINC_INC_CORR(value)))
+#define ENET_BWR_ATINC_INC_CORR(base, value) (ENET_WR_ATINC_INC_CORR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATSTMP register
+ */
+/*@{*/
+#define ENET_RD_ATSTMP(base)     (ENET_ATSTMP_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TGSR - Timer Global Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TGSR - Timer Global Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TGSR register
+ */
+/*@{*/
+#define ENET_RD_TGSR(base)       (ENET_TGSR_REG(base))
+#define ENET_WR_TGSR(base, value) (ENET_TGSR_REG(base) = (value))
+#define ENET_RMW_TGSR(base, mask, value) (ENET_WR_TGSR(base, (ENET_RD_TGSR(base) & ~(mask)) | (value)))
+#define ENET_SET_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) |  (value)))
+#define ENET_CLR_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) & ~(value)))
+#define ENET_TOG_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TGSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TGSR, field TF0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 0 is clear
+ * - 0b1 - Timer Flag for Channel 0 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF0 field. */
+#define ENET_RD_TGSR_TF0(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF0_MASK) >> ENET_TGSR_TF0_SHIFT)
+#define ENET_BRD_TGSR_TF0(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF0_SHIFT))
+
+/*! @brief Set the TF0 field to a new value. */
+#define ENET_WR_TGSR_TF0(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF2_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF0(value)))
+#define ENET_BWR_TGSR_TF0(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 1 is clear
+ * - 0b1 - Timer Flag for Channel 1 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF1 field. */
+#define ENET_RD_TGSR_TF1(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF1_MASK) >> ENET_TGSR_TF1_SHIFT)
+#define ENET_BRD_TGSR_TF1(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF1_SHIFT))
+
+/*! @brief Set the TF1 field to a new value. */
+#define ENET_WR_TGSR_TF1(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF1_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF2_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF1(value)))
+#define ENET_BWR_TGSR_TF1(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 2 is clear
+ * - 0b1 - Timer Flag for Channel 2 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF2 field. */
+#define ENET_RD_TGSR_TF2(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF2_MASK) >> ENET_TGSR_TF2_SHIFT)
+#define ENET_BRD_TGSR_TF2(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF2_SHIFT))
+
+/*! @brief Set the TF2 field to a new value. */
+#define ENET_WR_TGSR_TF2(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF2_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF2(value)))
+#define ENET_BWR_TGSR_TF2(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 3 is clear
+ * - 0b1 - Timer Flag for Channel 3 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF3 field. */
+#define ENET_RD_TGSR_TF3(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF3_MASK) >> ENET_TGSR_TF3_SHIFT)
+#define ENET_BRD_TGSR_TF3(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF3_SHIFT))
+
+/*! @brief Set the TF3 field to a new value. */
+#define ENET_WR_TGSR_TF3(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF3_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF2_MASK), ENET_TGSR_TF3(value)))
+#define ENET_BWR_TGSR_TF3(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF3_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCSR - Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCSR - Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCSR register
+ */
+/*@{*/
+#define ENET_RD_TCSR(base, index) (ENET_TCSR_REG(base, index))
+#define ENET_WR_TCSR(base, index, value) (ENET_TCSR_REG(base, index) = (value))
+#define ENET_RMW_TCSR(base, index, mask, value) (ENET_WR_TCSR(base, index, (ENET_RD_TCSR(base, index) & ~(mask)) | (value)))
+#define ENET_SET_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) |  (value)))
+#define ENET_CLR_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) & ~(value)))
+#define ENET_TOG_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TCSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCSR, field TDRE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA request is disabled
+ * - 0b1 - DMA request is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TDRE field. */
+#define ENET_RD_TCSR_TDRE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TDRE_MASK) >> ENET_TCSR_TDRE_SHIFT)
+#define ENET_BRD_TCSR_TDRE(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TDRE_SHIFT))
+
+/*! @brief Set the TDRE field to a new value. */
+#define ENET_WR_TCSR_TDRE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TDRE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TDRE(value)))
+#define ENET_BWR_TCSR_TDRE(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TDRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TMODE[5:2] (RW)
+ *
+ * Updating the Timer Mode field takes a few cycles to register because it is
+ * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
+ * from the 1588 clock domain. When changing Timer Mode, always disable the
+ * channel and read this register to verify the channel is disabled first.
+ *
+ * Values:
+ * - 0b0000 - Timer Channel is disabled.
+ * - 0b0001 - Timer Channel is configured for Input Capture on rising edge
+ * - 0b0010 - Timer Channel is configured for Input Capture on falling edge
+ * - 0b0011 - Timer Channel is configured for Input Capture on both edges
+ * - 0b0100 - Timer Channel is configured for Output Compare - software only
+ * - 0b0101 - Timer Channel is configured for Output Compare - toggle output on
+ *     compare
+ * - 0b0110 - Timer Channel is configured for Output Compare - clear output on
+ *     compare
+ * - 0b0111 - Timer Channel is configured for Output Compare - set output on
+ *     compare
+ * - 0b1000 - Reserved
+ * - 0b1010 - Timer Channel is configured for Output Compare - clear output on
+ *     compare, set output on overflow
+ * - 0b10x1 - Timer Channel is configured for Output Compare - set output on
+ *     compare, clear output on overflow
+ * - 0b1100 - Reserved
+ * - 0b1110 - Timer Channel is configured for Output Compare - pulse output low
+ *     on compare for one 1588 clock cycle
+ * - 0b1111 - Timer Channel is configured for Output Compare - pulse output high
+ *     on compare for one 1588 clock cycle
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TMODE field. */
+#define ENET_RD_TCSR_TMODE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TMODE_MASK) >> ENET_TCSR_TMODE_SHIFT)
+#define ENET_BRD_TCSR_TMODE(base, index) (ENET_RD_TCSR_TMODE(base, index))
+
+/*! @brief Set the TMODE field to a new value. */
+#define ENET_WR_TCSR_TMODE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TMODE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TMODE(value)))
+#define ENET_BWR_TCSR_TMODE(base, index, value) (ENET_WR_TCSR_TMODE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TIE[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled
+ * - 0b1 - Interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TIE field. */
+#define ENET_RD_TCSR_TIE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TIE_MASK) >> ENET_TCSR_TIE_SHIFT)
+#define ENET_BRD_TCSR_TIE(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define ENET_WR_TCSR_TIE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TIE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TIE(value)))
+#define ENET_BWR_TCSR_TIE(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TF[7] (W1C)
+ *
+ * Sets when input capture or output compare occurs. This flag is double
+ * buffered between the module clock and 1588 clock domains. When this field is 1, it
+ * can be cleared to 0 by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - Input Capture or Output Compare has not occurred
+ * - 0b1 - Input Capture or Output Compare has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TF field. */
+#define ENET_RD_TCSR_TF(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TF_MASK) >> ENET_TCSR_TF_SHIFT)
+#define ENET_BRD_TCSR_TF(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TF_SHIFT))
+
+/*! @brief Set the TF field to a new value. */
+#define ENET_WR_TCSR_TF(base, index, value) (ENET_RMW_TCSR(base, index, ENET_TCSR_TF_MASK, ENET_TCSR_TF(value)))
+#define ENET_BWR_TCSR_TF(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCCR - Timer Compare Capture Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCCR - Timer Compare Capture Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCCR register
+ */
+/*@{*/
+#define ENET_RD_TCCR(base, index) (ENET_TCCR_REG(base, index))
+#define ENET_WR_TCCR(base, index, value) (ENET_TCCR_REG(base, index) = (value))
+#define ENET_RMW_TCCR(base, index, mask, value) (ENET_WR_TCCR(base, index, (ENET_RD_TCCR(base, index) & ~(mask)) | (value)))
+#define ENET_SET_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) |  (value)))
+#define ENET_CLR_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) & ~(value)))
+#define ENET_TOG_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 EWM
+ *
+ * External Watchdog Monitor
+ *
+ * Registers defined in this header file:
+ * - EWM_CTRL - Control Register
+ * - EWM_SERV - Service Register
+ * - EWM_CMPL - Compare Low Register
+ * - EWM_CMPH - Compare High Register
+ */
+
+#define EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
+#define EWM_IDX (0U) /*!< Instance number for EWM. */
+
+/*******************************************************************************
+ * EWM_CTRL - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CTRL - Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
+ * written once after a CPU reset. Modifying these bits more than once, generates
+ * a bus transfer error.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CTRL register
+ */
+/*@{*/
+#define EWM_RD_CTRL(base)        (EWM_CTRL_REG(base))
+#define EWM_WR_CTRL(base, value) (EWM_CTRL_REG(base) = (value))
+#define EWM_RMW_CTRL(base, mask, value) (EWM_WR_CTRL(base, (EWM_RD_CTRL(base) & ~(mask)) | (value)))
+#define EWM_SET_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) |  (value)))
+#define EWM_CLR_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) & ~(value)))
+#define EWM_TOG_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual EWM_CTRL bitfields
+ */
+
+/*!
+ * @name Register EWM_CTRL, field EWMEN[0] (RW)
+ *
+ * This bit when set, enables the EWM module. This resets the EWM counter to
+ * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
+ * therefore it cannot be enabled until a reset occurs, due to the write-once
+ * nature of this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_EWMEN field. */
+#define EWM_RD_CTRL_EWMEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_EWMEN_MASK) >> EWM_CTRL_EWMEN_SHIFT)
+#define EWM_BRD_CTRL_EWMEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_EWMEN_SHIFT))
+
+/*! @brief Set the EWMEN field to a new value. */
+#define EWM_WR_CTRL_EWMEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_EWMEN_MASK, EWM_CTRL_EWMEN(value)))
+#define EWM_BWR_CTRL_EWMEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_EWMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field ASSIN[1] (RW)
+ *
+ * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
+ * inverts the assert state to a logic one.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_ASSIN field. */
+#define EWM_RD_CTRL_ASSIN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_ASSIN_MASK) >> EWM_CTRL_ASSIN_SHIFT)
+#define EWM_BRD_CTRL_ASSIN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_ASSIN_SHIFT))
+
+/*! @brief Set the ASSIN field to a new value. */
+#define EWM_WR_CTRL_ASSIN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_ASSIN_MASK, EWM_CTRL_ASSIN(value)))
+#define EWM_BWR_CTRL_ASSIN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_ASSIN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field INEN[2] (RW)
+ *
+ * This bit when set, enables the EWM_in port.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_INEN field. */
+#define EWM_RD_CTRL_INEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_INEN_MASK) >> EWM_CTRL_INEN_SHIFT)
+#define EWM_BRD_CTRL_INEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INEN_SHIFT))
+
+/*! @brief Set the INEN field to a new value. */
+#define EWM_WR_CTRL_INEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_INEN_MASK, EWM_CTRL_INEN(value)))
+#define EWM_BWR_CTRL_INEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field INTEN[3] (RW)
+ *
+ * This bit when set and EWM_out is asserted, an interrupt request is generated.
+ * To de-assert interrupt request, user should clear this bit by writing 0.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_INTEN field. */
+#define EWM_RD_CTRL_INTEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_INTEN_MASK) >> EWM_CTRL_INTEN_SHIFT)
+#define EWM_BRD_CTRL_INTEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INTEN_SHIFT))
+
+/*! @brief Set the INTEN field to a new value. */
+#define EWM_WR_CTRL_INTEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_INTEN_MASK, EWM_CTRL_INTEN(value)))
+#define EWM_BWR_CTRL_INTEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INTEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_SERV - Service Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_SERV - Service Register (WORZ)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERV register provides the interface from the CPU to the EWM module. It
+ * is write-only and reads of this register return zero.
+ */
+/*!
+ * @name Constants and macros for entire EWM_SERV register
+ */
+/*@{*/
+#define EWM_RD_SERV(base)        (EWM_SERV_REG(base))
+#define EWM_WR_SERV(base, value) (EWM_SERV_REG(base) = (value))
+#define EWM_RMW_SERV(base, mask, value) (EWM_WR_SERV(base, (EWM_RD_SERV(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_CMPL - Compare Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CMPL - Compare Low Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CMPL register is reset to zero after a CPU reset. This provides no
+ * minimum time for the CPU to service the EWM counter. This register can be written
+ * only once after a CPU reset. Writing this register more than once generates a
+ * bus transfer error.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CMPL register
+ */
+/*@{*/
+#define EWM_RD_CMPL(base)        (EWM_CMPL_REG(base))
+#define EWM_WR_CMPL(base, value) (EWM_CMPL_REG(base) = (value))
+#define EWM_RMW_CMPL(base, mask, value) (EWM_WR_CMPL(base, (EWM_RD_CMPL(base) & ~(mask)) | (value)))
+#define EWM_SET_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) |  (value)))
+#define EWM_CLR_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) & ~(value)))
+#define EWM_TOG_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_CMPH - Compare High Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CMPH - Compare High Register (RW)
+ *
+ * Reset value: 0xFFU
+ *
+ * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
+ * of 256 clocks time, for the CPU to service the EWM counter. This register can
+ * be written only once after a CPU reset. Writing this register more than once
+ * generates a bus transfer error. The valid values for CMPH are up to 0xFE
+ * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
+ * if EWM counter is greater than CMPH.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CMPH register
+ */
+/*@{*/
+#define EWM_RD_CMPH(base)        (EWM_CMPH_REG(base))
+#define EWM_WR_CMPH(base, value) (EWM_CMPH_REG(base) = (value))
+#define EWM_RMW_CMPH(base, mask, value) (EWM_WR_CMPH(base, (EWM_RD_CMPH(base) & ~(mask)) | (value)))
+#define EWM_SET_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) |  (value)))
+#define EWM_CLR_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) & ~(value)))
+#define EWM_TOG_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FB
+ *
+ * FlexBus external bus interface
+ *
+ * Registers defined in this header file:
+ * - FB_CSAR - Chip Select Address Register
+ * - FB_CSMR - Chip Select Mask Register
+ * - FB_CSCR - Chip Select Control Register
+ * - FB_CSPMCR - Chip Select port Multiplexing Control Register
+ */
+
+#define FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
+#define FB_IDX (0U) /*!< Instance number for FB. */
+
+/*******************************************************************************
+ * FB_CSAR - Chip Select Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSAR - Chip Select Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the associated chip-select's base address.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSAR register
+ */
+/*@{*/
+#define FB_RD_CSAR(base, index)  (FB_CSAR_REG(base, index))
+#define FB_WR_CSAR(base, index, value) (FB_CSAR_REG(base, index) = (value))
+#define FB_RMW_CSAR(base, index, mask, value) (FB_WR_CSAR(base, index, (FB_RD_CSAR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) |  (value)))
+#define FB_CLR_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) & ~(value)))
+#define FB_TOG_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSAR bitfields
+ */
+
+/*!
+ * @name Register FB_CSAR, field BA[31:16] (RW)
+ *
+ * Defines the base address for memory dedicated to the associated chip-select.
+ * BA is compared to bits 31-16 on the internal address bus to determine if the
+ * associated chip-select's memory is being accessed. Because the FlexBus module
+ * is one of the slaves connected to the crossbar switch, it is only accessible
+ * within a certain memory range. See the chip memory map for the applicable
+ * FlexBus "expansion" address range for which the chip-selects can be active. Set the
+ * CSARn and CSMRn registers appropriately before accessing this region.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSAR_BA field. */
+#define FB_RD_CSAR_BA(base, index) ((FB_CSAR_REG(base, index) & FB_CSAR_BA_MASK) >> FB_CSAR_BA_SHIFT)
+#define FB_BRD_CSAR_BA(base, index) (FB_RD_CSAR_BA(base, index))
+
+/*! @brief Set the BA field to a new value. */
+#define FB_WR_CSAR_BA(base, index, value) (FB_RMW_CSAR(base, index, FB_CSAR_BA_MASK, FB_CSAR_BA(value)))
+#define FB_BWR_CSAR_BA(base, index, value) (FB_WR_CSAR_BA(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSMR - Chip Select Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSMR - Chip Select Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the address mask and allowable access types for the associated
+ * chip-select.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSMR register
+ */
+/*@{*/
+#define FB_RD_CSMR(base, index)  (FB_CSMR_REG(base, index))
+#define FB_WR_CSMR(base, index, value) (FB_CSMR_REG(base, index) = (value))
+#define FB_RMW_CSMR(base, index, mask, value) (FB_WR_CSMR(base, index, (FB_RD_CSMR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) |  (value)))
+#define FB_CLR_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) & ~(value)))
+#define FB_TOG_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSMR bitfields
+ */
+
+/*!
+ * @name Register FB_CSMR, field V[0] (RW)
+ *
+ * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
+ * Programmed chip-selects do not assert until the V bit is 1b (except for
+ * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
+ * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
+ * select initialization sequence to allow other chip selects to function as
+ * programmed.
+ *
+ * Values:
+ * - 0b0 - Chip-select is invalid.
+ * - 0b1 - Chip-select is valid.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_V field. */
+#define FB_RD_CSMR_V(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_V_MASK) >> FB_CSMR_V_SHIFT)
+#define FB_BRD_CSMR_V(base, index) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_V_SHIFT))
+
+/*! @brief Set the V field to a new value. */
+#define FB_WR_CSMR_V(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_V_MASK, FB_CSMR_V(value)))
+#define FB_BWR_CSMR_V(base, index, value) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_V_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSMR, field WP[8] (RW)
+ *
+ * Controls write accesses to the address range in the corresponding CSAR.
+ *
+ * Values:
+ * - 0b0 - Write accesses are allowed.
+ * - 0b1 - Write accesses are not allowed. Attempting to write to the range of
+ *     addresses for which the WP bit is set results in a bus error termination of
+ *     the internal cycle and no external cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_WP field. */
+#define FB_RD_CSMR_WP(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_WP_MASK) >> FB_CSMR_WP_SHIFT)
+#define FB_BRD_CSMR_WP(base, index) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_WP_SHIFT))
+
+/*! @brief Set the WP field to a new value. */
+#define FB_WR_CSMR_WP(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_WP_MASK, FB_CSMR_WP(value)))
+#define FB_BWR_CSMR_WP(base, index, value) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_WP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSMR, field BAM[31:16] (RW)
+ *
+ * Defines the associated chip-select's block size by masking address bits.
+ *
+ * Values:
+ * - 0b0000000000000000 - The corresponding address bit in CSAR is used in the
+ *     chip-select decode.
+ * - 0b0000000000000001 - The corresponding address bit in CSAR is a don't care
+ *     in the chip-select decode.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_BAM field. */
+#define FB_RD_CSMR_BAM(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_BAM_MASK) >> FB_CSMR_BAM_SHIFT)
+#define FB_BRD_CSMR_BAM(base, index) (FB_RD_CSMR_BAM(base, index))
+
+/*! @brief Set the BAM field to a new value. */
+#define FB_WR_CSMR_BAM(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_BAM_MASK, FB_CSMR_BAM(value)))
+#define FB_BWR_CSMR_BAM(base, index, value) (FB_WR_CSMR_BAM(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSCR - Chip Select Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSCR - Chip Select Control Register (RW)
+ *
+ * Reset value: 0x003FFC00U
+ *
+ * Controls the auto-acknowledge, address setup and hold times, port size, burst
+ * capability, and number of wait states for the associated chip select. To
+ * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
+ * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
+ * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
+ * particular chip for information on the exact CSCR0 reset value.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSCR register
+ */
+/*@{*/
+#define FB_RD_CSCR(base, index)  (FB_CSCR_REG(base, index))
+#define FB_WR_CSCR(base, index, value) (FB_CSCR_REG(base, index) = (value))
+#define FB_RMW_CSCR(base, index, mask, value) (FB_WR_CSCR(base, index, (FB_RD_CSCR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) |  (value)))
+#define FB_CLR_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) & ~(value)))
+#define FB_TOG_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSCR, field BSTW[3] (RW)
+ *
+ * Specifies whether burst writes are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0b0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst writes. For example, a 32-bit write to an
+ *     8-bit port takes four byte writes.
+ * - 0b1 - Enabled. Enables burst write of data larger than the specified port
+ *     size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to
+ *     8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BSTW field. */
+#define FB_RD_CSCR_BSTW(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BSTW_MASK) >> FB_CSCR_BSTW_SHIFT)
+#define FB_BRD_CSCR_BSTW(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTW_SHIFT))
+
+/*! @brief Set the BSTW field to a new value. */
+#define FB_WR_CSCR_BSTW(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BSTW_MASK, FB_CSCR_BSTW(value)))
+#define FB_BWR_CSCR_BSTW(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BSTR[4] (RW)
+ *
+ * Specifies whether burst reads are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0b0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst reads. For example, a 32-bit read from an
+ *     8-bit port is broken into four 8-bit reads.
+ * - 0b1 - Enabled. Enables data burst reads larger than the specified port
+ *     size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
+ *     ports, and line reads from 8-, 16-, and 32-bit ports.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BSTR field. */
+#define FB_RD_CSCR_BSTR(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BSTR_MASK) >> FB_CSCR_BSTR_SHIFT)
+#define FB_BRD_CSCR_BSTR(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTR_SHIFT))
+
+/*! @brief Set the BSTR field to a new value. */
+#define FB_WR_CSCR_BSTR(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BSTR_MASK, FB_CSCR_BSTR(value)))
+#define FB_BWR_CSCR_BSTR(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BEM[5] (RW)
+ *
+ * Specifies whether the corresponding FB_BE is asserted for read accesses.
+ * Certain memories have byte enables that must be asserted during reads and writes.
+ * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
+ * of byte enable support for these SRAMs.
+ *
+ * Values:
+ * - 0b0 - FB_BE is asserted for data write only.
+ * - 0b1 - FB_BE is asserted for data read and write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BEM field. */
+#define FB_RD_CSCR_BEM(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BEM_MASK) >> FB_CSCR_BEM_SHIFT)
+#define FB_BRD_CSCR_BEM(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BEM_SHIFT))
+
+/*! @brief Set the BEM field to a new value. */
+#define FB_WR_CSCR_BEM(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BEM_MASK, FB_CSCR_BEM(value)))
+#define FB_BWR_CSCR_BEM(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BEM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field PS[7:6] (RW)
+ *
+ * Specifies the data port width of the associated chip-select, and determines
+ * where data is driven during write cycles and where data is sampled during read
+ * cycles.
+ *
+ * Values:
+ * - 0b00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
+ * - 0b01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24]
+ *     when BLS is 0b, or FB_D[7:0] when BLS is 1b.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_PS field. */
+#define FB_RD_CSCR_PS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_PS_MASK) >> FB_CSCR_PS_SHIFT)
+#define FB_BRD_CSCR_PS(base, index) (FB_RD_CSCR_PS(base, index))
+
+/*! @brief Set the PS field to a new value. */
+#define FB_WR_CSCR_PS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_PS_MASK, FB_CSCR_PS(value)))
+#define FB_BWR_CSCR_PS(base, index, value) (FB_WR_CSCR_PS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field AA[8] (RW)
+ *
+ * Asserts the internal transfer acknowledge for accesses specified by the
+ * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
+ * asserts an external FB_TA before the wait-state countdown asserts the
+ * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
+ * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
+ *
+ * Values:
+ * - 0b0 - Disabled. No internal transfer acknowledge is asserted and the cycle
+ *     is terminated externally.
+ * - 0b1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_AA field. */
+#define FB_RD_CSCR_AA(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_AA_MASK) >> FB_CSCR_AA_SHIFT)
+#define FB_BRD_CSCR_AA(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_AA_SHIFT))
+
+/*! @brief Set the AA field to a new value. */
+#define FB_WR_CSCR_AA(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_AA_MASK, FB_CSCR_AA(value)))
+#define FB_BWR_CSCR_AA(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_AA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BLS[9] (RW)
+ *
+ * Specifies if data on FB_AD appears left-aligned or right-aligned during the
+ * data phase of a FlexBus access.
+ *
+ * Values:
+ * - 0b0 - Not shifted. Data is left-aligned on FB_AD.
+ * - 0b1 - Shifted. Data is right-aligned on FB_AD.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BLS field. */
+#define FB_RD_CSCR_BLS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BLS_MASK) >> FB_CSCR_BLS_SHIFT)
+#define FB_BRD_CSCR_BLS(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BLS_SHIFT))
+
+/*! @brief Set the BLS field to a new value. */
+#define FB_WR_CSCR_BLS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BLS_MASK, FB_CSCR_BLS(value)))
+#define FB_BWR_CSCR_BLS(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field WS[15:10] (RW)
+ *
+ * Specifies the number of wait states inserted after FlexBus asserts the
+ * associated chip-select and before an internal transfer acknowledge is generated (WS
+ * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_WS field. */
+#define FB_RD_CSCR_WS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_WS_MASK) >> FB_CSCR_WS_SHIFT)
+#define FB_BRD_CSCR_WS(base, index) (FB_RD_CSCR_WS(base, index))
+
+/*! @brief Set the WS field to a new value. */
+#define FB_WR_CSCR_WS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_WS_MASK, FB_CSCR_WS(value)))
+#define FB_BWR_CSCR_WS(base, index, value) (FB_WR_CSCR_WS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field WRAH[17:16] (RW)
+ *
+ * Controls the address, data, and attribute hold time after the termination of
+ * a write cycle that hits in the associated chip-select's address space. The
+ * hold time applies only at the end of a transfer. Therefore, during a burst
+ * transfer or a transfer to a port size smaller than the transfer size, the hold time
+ * is only added after the last bus cycle.
+ *
+ * Values:
+ * - 0b00 - 1 cycle (default for all but FB_CS0 )
+ * - 0b01 - 2 cycles
+ * - 0b10 - 3 cycles
+ * - 0b11 - 4 cycles (default for FB_CS0 )
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_WRAH field. */
+#define FB_RD_CSCR_WRAH(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_WRAH_MASK) >> FB_CSCR_WRAH_SHIFT)
+#define FB_BRD_CSCR_WRAH(base, index) (FB_RD_CSCR_WRAH(base, index))
+
+/*! @brief Set the WRAH field to a new value. */
+#define FB_WR_CSCR_WRAH(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_WRAH_MASK, FB_CSCR_WRAH(value)))
+#define FB_BWR_CSCR_WRAH(base, index, value) (FB_WR_CSCR_WRAH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field RDAH[19:18] (RW)
+ *
+ * Controls the address and attribute hold time after the termination during a
+ * read cycle that hits in the associated chip-select's address space. The hold
+ * time applies only at the end of a transfer. Therefore, during a burst transfer
+ * or a transfer to a port size smaller than the transfer size, the hold time is
+ * only added after the last bus cycle. The number of cycles the address and
+ * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
+ *
+ * Values:
+ * - 0b00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
+ * - 0b01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
+ * - 0b10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
+ * - 0b11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_RDAH field. */
+#define FB_RD_CSCR_RDAH(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_RDAH_MASK) >> FB_CSCR_RDAH_SHIFT)
+#define FB_BRD_CSCR_RDAH(base, index) (FB_RD_CSCR_RDAH(base, index))
+
+/*! @brief Set the RDAH field to a new value. */
+#define FB_WR_CSCR_RDAH(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_RDAH_MASK, FB_CSCR_RDAH(value)))
+#define FB_BWR_CSCR_RDAH(base, index, value) (FB_WR_CSCR_RDAH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field ASET[21:20] (RW)
+ *
+ * Controls when the chip-select is asserted with respect to assertion of a
+ * valid address and attributes.
+ *
+ * Values:
+ * - 0b00 - Assert FB_CSn on the first rising clock edge after the address is
+ *     asserted (default for all but FB_CS0 ).
+ * - 0b01 - Assert FB_CSn on the second rising clock edge after the address is
+ *     asserted.
+ * - 0b10 - Assert FB_CSn on the third rising clock edge after the address is
+ *     asserted.
+ * - 0b11 - Assert FB_CSn on the fourth rising clock edge after the address is
+ *     asserted (default for FB_CS0 ).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_ASET field. */
+#define FB_RD_CSCR_ASET(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_ASET_MASK) >> FB_CSCR_ASET_SHIFT)
+#define FB_BRD_CSCR_ASET(base, index) (FB_RD_CSCR_ASET(base, index))
+
+/*! @brief Set the ASET field to a new value. */
+#define FB_WR_CSCR_ASET(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_ASET_MASK, FB_CSCR_ASET(value)))
+#define FB_BWR_CSCR_ASET(base, index, value) (FB_WR_CSCR_ASET(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field EXTS[22] (RW)
+ *
+ * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
+ * /FB_ALE is asserted.
+ *
+ * Values:
+ * - 0b0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
+ * - 0b1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive
+ *     clock edge after FB_CSn asserts.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_EXTS field. */
+#define FB_RD_CSCR_EXTS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_EXTS_MASK) >> FB_CSCR_EXTS_SHIFT)
+#define FB_BRD_CSCR_EXTS(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_EXTS_SHIFT))
+
+/*! @brief Set the EXTS field to a new value. */
+#define FB_WR_CSCR_EXTS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_EXTS_MASK, FB_CSCR_EXTS(value)))
+#define FB_BWR_CSCR_EXTS(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_EXTS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field SWSEN[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled. A number of wait states (specified by WS) are inserted
+ *     before an internal transfer acknowledge is generated for all transfers.
+ * - 0b1 - Enabled. A number of wait states (specified by SWS) are inserted
+ *     before an internal transfer acknowledge is generated for burst transfer
+ *     secondary terminations.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_SWSEN field. */
+#define FB_RD_CSCR_SWSEN(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_SWSEN_MASK) >> FB_CSCR_SWSEN_SHIFT)
+#define FB_BRD_CSCR_SWSEN(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_SWSEN_SHIFT))
+
+/*! @brief Set the SWSEN field to a new value. */
+#define FB_WR_CSCR_SWSEN(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_SWSEN_MASK, FB_CSCR_SWSEN(value)))
+#define FB_BWR_CSCR_SWSEN(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_SWSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field SWS[31:26] (RW)
+ *
+ * Used only when the SWSEN bit is 1b. Specifies the number of wait states
+ * inserted before an internal transfer acknowledge is generated for a burst transfer
+ * (except for the first termination, which is controlled by WS).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_SWS field. */
+#define FB_RD_CSCR_SWS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_SWS_MASK) >> FB_CSCR_SWS_SHIFT)
+#define FB_BRD_CSCR_SWS(base, index) (FB_RD_CSCR_SWS(base, index))
+
+/*! @brief Set the SWS field to a new value. */
+#define FB_WR_CSCR_SWS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_SWS_MASK, FB_CSCR_SWS(value)))
+#define FB_BWR_CSCR_SWS(base, index, value) (FB_WR_CSCR_SWS(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSPMCR - Chip Select port Multiplexing Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
+ * do any of the following: Write to a reserved address Write to a reserved
+ * field in this register, or Access this register using a size other than 32 bits.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSPMCR register
+ */
+/*@{*/
+#define FB_RD_CSPMCR(base)       (FB_CSPMCR_REG(base))
+#define FB_WR_CSPMCR(base, value) (FB_CSPMCR_REG(base) = (value))
+#define FB_RMW_CSPMCR(base, mask, value) (FB_WR_CSPMCR(base, (FB_RD_CSPMCR(base) & ~(mask)) | (value)))
+#define FB_SET_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) |  (value)))
+#define FB_CLR_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) & ~(value)))
+#define FB_TOG_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSPMCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
+ *
+ * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
+ * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
+ * bus hangs during a transfer.
+ *
+ * Values:
+ * - 0b0000 - FB_TA
+ * - 0b0001 - FB_CS3 . You must also write 1b to CSCR[AA].
+ * - 0b0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
+#define FB_RD_CSPMCR_GROUP5(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP5_MASK) >> FB_CSPMCR_GROUP5_SHIFT)
+#define FB_BRD_CSPMCR_GROUP5(base) (FB_RD_CSPMCR_GROUP5(base))
+
+/*! @brief Set the GROUP5 field to a new value. */
+#define FB_WR_CSPMCR_GROUP5(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP5_MASK, FB_CSPMCR_GROUP5(value)))
+#define FB_BWR_CSPMCR_GROUP5(base, value) (FB_WR_CSPMCR_GROUP5(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
+ *
+ * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_TBST
+ * - 0b0001 - FB_CS2
+ * - 0b0010 - FB_BE_15_8
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
+#define FB_RD_CSPMCR_GROUP4(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP4_MASK) >> FB_CSPMCR_GROUP4_SHIFT)
+#define FB_BRD_CSPMCR_GROUP4(base) (FB_RD_CSPMCR_GROUP4(base))
+
+/*! @brief Set the GROUP4 field to a new value. */
+#define FB_WR_CSPMCR_GROUP4(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP4_MASK, FB_CSPMCR_GROUP4(value)))
+#define FB_BWR_CSPMCR_GROUP4(base, value) (FB_WR_CSPMCR_GROUP4(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
+ *
+ * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_CS5
+ * - 0b0001 - FB_TSIZ1
+ * - 0b0010 - FB_BE_23_16
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
+#define FB_RD_CSPMCR_GROUP3(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP3_MASK) >> FB_CSPMCR_GROUP3_SHIFT)
+#define FB_BRD_CSPMCR_GROUP3(base) (FB_RD_CSPMCR_GROUP3(base))
+
+/*! @brief Set the GROUP3 field to a new value. */
+#define FB_WR_CSPMCR_GROUP3(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP3_MASK, FB_CSPMCR_GROUP3(value)))
+#define FB_BWR_CSPMCR_GROUP3(base, value) (FB_WR_CSPMCR_GROUP3(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
+ *
+ * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_CS4
+ * - 0b0001 - FB_TSIZ0
+ * - 0b0010 - FB_BE_31_24
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
+#define FB_RD_CSPMCR_GROUP2(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP2_MASK) >> FB_CSPMCR_GROUP2_SHIFT)
+#define FB_BRD_CSPMCR_GROUP2(base) (FB_RD_CSPMCR_GROUP2(base))
+
+/*! @brief Set the GROUP2 field to a new value. */
+#define FB_WR_CSPMCR_GROUP2(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP2_MASK, FB_CSPMCR_GROUP2(value)))
+#define FB_BWR_CSPMCR_GROUP2(base, value) (FB_WR_CSPMCR_GROUP2(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
+ *
+ * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
+ *
+ * Values:
+ * - 0b0000 - FB_ALE
+ * - 0b0001 - FB_CS1
+ * - 0b0010 - FB_TS
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
+#define FB_RD_CSPMCR_GROUP1(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP1_MASK) >> FB_CSPMCR_GROUP1_SHIFT)
+#define FB_BRD_CSPMCR_GROUP1(base) (FB_RD_CSPMCR_GROUP1(base))
+
+/*! @brief Set the GROUP1 field to a new value. */
+#define FB_WR_CSPMCR_GROUP1(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP1_MASK, FB_CSPMCR_GROUP1(value)))
+#define FB_BWR_CSPMCR_GROUP1(base, value) (FB_WR_CSPMCR_GROUP1(base, value))
+/*@}*/
+
+/*
+ * MK64F12 FMC
+ *
+ * Flash Memory Controller
+ *
+ * Registers defined in this header file:
+ * - FMC_PFAPR - Flash Access Protection Register
+ * - FMC_PFB0CR - Flash Bank 0 Control Register
+ * - FMC_PFB1CR - Flash Bank 1 Control Register
+ * - FMC_TAGVDW0S - Cache Tag Storage
+ * - FMC_TAGVDW1S - Cache Tag Storage
+ * - FMC_TAGVDW2S - Cache Tag Storage
+ * - FMC_TAGVDW3S - Cache Tag Storage
+ * - FMC_DATA_U - Cache Data Storage (upper word)
+ * - FMC_DATA_L - Cache Data Storage (lower word)
+ */
+
+#define FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */
+#define FMC_IDX (0U) /*!< Instance number for FMC. */
+
+/*******************************************************************************
+ * FMC_PFAPR - Flash Access Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFAPR - Flash Access Protection Register (RW)
+ *
+ * Reset value: 0x00F8003FU
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFAPR register
+ */
+/*@{*/
+#define FMC_RD_PFAPR(base)       (FMC_PFAPR_REG(base))
+#define FMC_WR_PFAPR(base, value) (FMC_PFAPR_REG(base) = (value))
+#define FMC_RMW_PFAPR(base, mask, value) (FMC_WR_PFAPR(base, (FMC_RD_PFAPR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) |  (value)))
+#define FMC_CLR_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) & ~(value)))
+#define FMC_TOG_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFAPR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M0AP field. */
+#define FMC_RD_PFAPR_M0AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M0AP_MASK) >> FMC_PFAPR_M0AP_SHIFT)
+#define FMC_BRD_PFAPR_M0AP(base) (FMC_RD_PFAPR_M0AP(base))
+
+/*! @brief Set the M0AP field to a new value. */
+#define FMC_WR_PFAPR_M0AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M0AP_MASK, FMC_PFAPR_M0AP(value)))
+#define FMC_BWR_PFAPR_M0AP(base, value) (FMC_WR_PFAPR_M0AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M1AP field. */
+#define FMC_RD_PFAPR_M1AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M1AP_MASK) >> FMC_PFAPR_M1AP_SHIFT)
+#define FMC_BRD_PFAPR_M1AP(base) (FMC_RD_PFAPR_M1AP(base))
+
+/*! @brief Set the M1AP field to a new value. */
+#define FMC_WR_PFAPR_M1AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M1AP_MASK, FMC_PFAPR_M1AP(value)))
+#define FMC_BWR_PFAPR_M1AP(base, value) (FMC_WR_PFAPR_M1AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M2AP field. */
+#define FMC_RD_PFAPR_M2AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M2AP_MASK) >> FMC_PFAPR_M2AP_SHIFT)
+#define FMC_BRD_PFAPR_M2AP(base) (FMC_RD_PFAPR_M2AP(base))
+
+/*! @brief Set the M2AP field to a new value. */
+#define FMC_WR_PFAPR_M2AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M2AP_MASK, FMC_PFAPR_M2AP(value)))
+#define FMC_BWR_PFAPR_M2AP(base, value) (FMC_WR_PFAPR_M2AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M3AP field. */
+#define FMC_RD_PFAPR_M3AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M3AP_MASK) >> FMC_PFAPR_M3AP_SHIFT)
+#define FMC_BRD_PFAPR_M3AP(base) (FMC_RD_PFAPR_M3AP(base))
+
+/*! @brief Set the M3AP field to a new value. */
+#define FMC_WR_PFAPR_M3AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M3AP_MASK, FMC_PFAPR_M3AP(value)))
+#define FMC_BWR_PFAPR_M3AP(base, value) (FMC_WR_PFAPR_M3AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M4AP field. */
+#define FMC_RD_PFAPR_M4AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M4AP_MASK) >> FMC_PFAPR_M4AP_SHIFT)
+#define FMC_BRD_PFAPR_M4AP(base) (FMC_RD_PFAPR_M4AP(base))
+
+/*! @brief Set the M4AP field to a new value. */
+#define FMC_WR_PFAPR_M4AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M4AP_MASK, FMC_PFAPR_M4AP(value)))
+#define FMC_BWR_PFAPR_M4AP(base, value) (FMC_WR_PFAPR_M4AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M5AP field. */
+#define FMC_RD_PFAPR_M5AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M5AP_MASK) >> FMC_PFAPR_M5AP_SHIFT)
+#define FMC_BRD_PFAPR_M5AP(base) (FMC_RD_PFAPR_M5AP(base))
+
+/*! @brief Set the M5AP field to a new value. */
+#define FMC_WR_PFAPR_M5AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M5AP_MASK, FMC_PFAPR_M5AP(value)))
+#define FMC_BWR_PFAPR_M5AP(base, value) (FMC_WR_PFAPR_M5AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M6AP field. */
+#define FMC_RD_PFAPR_M6AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M6AP_MASK) >> FMC_PFAPR_M6AP_SHIFT)
+#define FMC_BRD_PFAPR_M6AP(base) (FMC_RD_PFAPR_M6AP(base))
+
+/*! @brief Set the M6AP field to a new value. */
+#define FMC_WR_PFAPR_M6AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M6AP_MASK, FMC_PFAPR_M6AP(value)))
+#define FMC_BWR_PFAPR_M6AP(base, value) (FMC_WR_PFAPR_M6AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master.
+ * - 0b01 - Only read accesses may be performed by this master.
+ * - 0b10 - Only write accesses may be performed by this master.
+ * - 0b11 - Both read and write accesses may be performed by this master.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M7AP field. */
+#define FMC_RD_PFAPR_M7AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M7AP_MASK) >> FMC_PFAPR_M7AP_SHIFT)
+#define FMC_BRD_PFAPR_M7AP(base) (FMC_RD_PFAPR_M7AP(base))
+
+/*! @brief Set the M7AP field to a new value. */
+#define FMC_WR_PFAPR_M7AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M7AP_MASK, FMC_PFAPR_M7AP(value)))
+#define FMC_BWR_PFAPR_M7AP(base, value) (FMC_WR_PFAPR_M7AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M0PFD[16] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M0PFD field. */
+#define FMC_RD_PFAPR_M0PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M0PFD_MASK) >> FMC_PFAPR_M0PFD_SHIFT)
+#define FMC_BRD_PFAPR_M0PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M0PFD_SHIFT))
+
+/*! @brief Set the M0PFD field to a new value. */
+#define FMC_WR_PFAPR_M0PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M0PFD_MASK, FMC_PFAPR_M0PFD(value)))
+#define FMC_BWR_PFAPR_M0PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M0PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M1PFD[17] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M1PFD field. */
+#define FMC_RD_PFAPR_M1PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M1PFD_MASK) >> FMC_PFAPR_M1PFD_SHIFT)
+#define FMC_BRD_PFAPR_M1PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M1PFD_SHIFT))
+
+/*! @brief Set the M1PFD field to a new value. */
+#define FMC_WR_PFAPR_M1PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M1PFD_MASK, FMC_PFAPR_M1PFD(value)))
+#define FMC_BWR_PFAPR_M1PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M1PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M2PFD[18] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M2PFD field. */
+#define FMC_RD_PFAPR_M2PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M2PFD_MASK) >> FMC_PFAPR_M2PFD_SHIFT)
+#define FMC_BRD_PFAPR_M2PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M2PFD_SHIFT))
+
+/*! @brief Set the M2PFD field to a new value. */
+#define FMC_WR_PFAPR_M2PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M2PFD_MASK, FMC_PFAPR_M2PFD(value)))
+#define FMC_BWR_PFAPR_M2PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M2PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M3PFD[19] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M3PFD field. */
+#define FMC_RD_PFAPR_M3PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M3PFD_MASK) >> FMC_PFAPR_M3PFD_SHIFT)
+#define FMC_BRD_PFAPR_M3PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M3PFD_SHIFT))
+
+/*! @brief Set the M3PFD field to a new value. */
+#define FMC_WR_PFAPR_M3PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M3PFD_MASK, FMC_PFAPR_M3PFD(value)))
+#define FMC_BWR_PFAPR_M3PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M3PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M4PFD[20] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M4PFD field. */
+#define FMC_RD_PFAPR_M4PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M4PFD_MASK) >> FMC_PFAPR_M4PFD_SHIFT)
+#define FMC_BRD_PFAPR_M4PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M4PFD_SHIFT))
+
+/*! @brief Set the M4PFD field to a new value. */
+#define FMC_WR_PFAPR_M4PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M4PFD_MASK, FMC_PFAPR_M4PFD(value)))
+#define FMC_BWR_PFAPR_M4PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M4PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M5PFD[21] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M5PFD field. */
+#define FMC_RD_PFAPR_M5PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M5PFD_MASK) >> FMC_PFAPR_M5PFD_SHIFT)
+#define FMC_BRD_PFAPR_M5PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M5PFD_SHIFT))
+
+/*! @brief Set the M5PFD field to a new value. */
+#define FMC_WR_PFAPR_M5PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M5PFD_MASK, FMC_PFAPR_M5PFD(value)))
+#define FMC_BWR_PFAPR_M5PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M5PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M6PFD[22] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M6PFD field. */
+#define FMC_RD_PFAPR_M6PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M6PFD_MASK) >> FMC_PFAPR_M6PFD_SHIFT)
+#define FMC_BRD_PFAPR_M6PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M6PFD_SHIFT))
+
+/*! @brief Set the M6PFD field to a new value. */
+#define FMC_WR_PFAPR_M6PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M6PFD_MASK, FMC_PFAPR_M6PFD(value)))
+#define FMC_BWR_PFAPR_M6PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M6PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M7PFD[23] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M7PFD field. */
+#define FMC_RD_PFAPR_M7PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M7PFD_MASK) >> FMC_PFAPR_M7PFD_SHIFT)
+#define FMC_BRD_PFAPR_M7PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M7PFD_SHIFT))
+
+/*! @brief Set the M7PFD field to a new value. */
+#define FMC_WR_PFAPR_M7PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M7PFD_MASK, FMC_PFAPR_M7PFD(value)))
+#define FMC_BWR_PFAPR_M7PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M7PFD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_PFB0CR - Flash Bank 0 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFB0CR - Flash Bank 0 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFB0CR register
+ */
+/*@{*/
+#define FMC_RD_PFB0CR(base)      (FMC_PFB0CR_REG(base))
+#define FMC_WR_PFB0CR(base, value) (FMC_PFB0CR_REG(base) = (value))
+#define FMC_RMW_PFB0CR(base, mask, value) (FMC_WR_PFB0CR(base, (FMC_RD_PFB0CR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) |  (value)))
+#define FMC_CLR_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) & ~(value)))
+#define FMC_TOG_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFB0CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry page buffer is enabled in response
+ * to flash read accesses. Its operation is independent from bank 1's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0b0 - Single entry buffer is disabled.
+ * - 0b1 - Single entry buffer is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */
+#define FMC_RD_PFB0CR_B0SEBE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0SEBE_MASK) >> FMC_PFB0CR_B0SEBE_SHIFT)
+#define FMC_BRD_PFB0CR_B0SEBE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0SEBE_SHIFT))
+
+/*! @brief Set the B0SEBE field to a new value. */
+#define FMC_WR_PFB0CR_B0SEBE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0SEBE_MASK, FMC_PFB0CR_B0SEBE(value)))
+#define FMC_BWR_PFB0CR_B0SEBE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0SEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to instruction fetches.
+ * - 0b1 - Enable prefetches in response to instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */
+#define FMC_RD_PFB0CR_B0IPE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0IPE_MASK) >> FMC_PFB0CR_B0IPE_SHIFT)
+#define FMC_BRD_PFB0CR_B0IPE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0IPE_SHIFT))
+
+/*! @brief Set the B0IPE field to a new value. */
+#define FMC_WR_PFB0CR_B0IPE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0IPE_MASK, FMC_PFB0CR_B0IPE(value)))
+#define FMC_BWR_PFB0CR_B0IPE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0IPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to data references.
+ * - 0b1 - Enable prefetches in response to data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */
+#define FMC_RD_PFB0CR_B0DPE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0DPE_MASK) >> FMC_PFB0CR_B0DPE_SHIFT)
+#define FMC_BRD_PFB0CR_B0DPE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DPE_SHIFT))
+
+/*! @brief Set the B0DPE field to a new value. */
+#define FMC_WR_PFB0CR_B0DPE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0DPE_MASK, FMC_PFB0CR_B0DPE(value)))
+#define FMC_BWR_PFB0CR_B0DPE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache instruction fetches.
+ * - 0b1 - Cache instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */
+#define FMC_RD_PFB0CR_B0ICE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0ICE_MASK) >> FMC_PFB0CR_B0ICE_SHIFT)
+#define FMC_BRD_PFB0CR_B0ICE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0ICE_SHIFT))
+
+/*! @brief Set the B0ICE field to a new value. */
+#define FMC_WR_PFB0CR_B0ICE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0ICE_MASK, FMC_PFB0CR_B0ICE(value)))
+#define FMC_BWR_PFB0CR_B0ICE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0ICE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache data references.
+ * - 0b1 - Cache data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */
+#define FMC_RD_PFB0CR_B0DCE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0DCE_MASK) >> FMC_PFB0CR_B0DCE_SHIFT)
+#define FMC_BRD_PFB0CR_B0DCE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DCE_SHIFT))
+
+/*! @brief Set the B0DCE field to a new value. */
+#define FMC_WR_PFB0CR_B0DCE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0DCE_MASK, FMC_PFB0CR_B0DCE(value)))
+#define FMC_BWR_PFB0CR_B0DCE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
+ *
+ * This 3-bit field defines the replacement algorithm for accesses that are
+ * cached.
+ *
+ * Values:
+ * - 0b000 - LRU replacement algorithm per set across all four ways
+ * - 0b001 - Reserved
+ * - 0b010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
+ * - 0b011 - Independent LRU with ways [0-2] for ifetches, [3] for data
+ * - 0b1xx - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_CRC field. */
+#define FMC_RD_PFB0CR_CRC(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_CRC_MASK) >> FMC_PFB0CR_CRC_SHIFT)
+#define FMC_BRD_PFB0CR_CRC(base) (FMC_RD_PFB0CR_CRC(base))
+
+/*! @brief Set the CRC field to a new value. */
+#define FMC_WR_PFB0CR_CRC(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CRC_MASK, FMC_PFB0CR_CRC(value)))
+#define FMC_BWR_PFB0CR_CRC(base, value) (FMC_WR_PFB0CR_CRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 0 memory.
+ *
+ * Values:
+ * - 0b00 - 32 bits
+ * - 0b01 - 64 bits
+ * - 0b10 - 128 bits
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0MW field. */
+#define FMC_RD_PFB0CR_B0MW(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0MW_MASK) >> FMC_PFB0CR_B0MW_SHIFT)
+#define FMC_BRD_PFB0CR_B0MW(base) (FMC_RD_PFB0CR_B0MW(base))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
+ *
+ * This bit determines if the FMC's prefetch speculation buffer and the single
+ * entry page buffer are to be invalidated (cleared). When this bit is written,
+ * the speculation buffer and single entry buffer are immediately cleared. This bit
+ * always reads as zero.
+ *
+ * Values:
+ * - 0b0 - Speculation buffer and single entry buffer are not affected.
+ * - 0b1 - Invalidate (clear) speculation buffer and single entry buffer.
+ */
+/*@{*/
+/*! @brief Set the S_B_INV field to a new value. */
+#define FMC_WR_PFB0CR_S_B_INV(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_S_B_INV_MASK, FMC_PFB0CR_S_B_INV(value)))
+#define FMC_BWR_PFB0CR_S_B_INV(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_S_B_INV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
+ *
+ * These bits determine if the given cache way is to be invalidated (cleared).
+ * When a bit within this field is written, the corresponding cache way is
+ * immediately invalidated: the way's tag, data, and valid contents are cleared. This
+ * field always reads as zero. Cache invalidation takes precedence over locking.
+ * The cache is invalidated by system reset. System software is required to
+ * maintain memory coherency when any segment of the flash memory is programmed or
+ * erased. Accordingly, cache invalidations must occur after a programming or erase
+ * event is completed and before the new memory image is accessed. The bit setting
+ * definitions are for each bit in the field.
+ *
+ * Values:
+ * - 0b0000 - No cache way invalidation for the corresponding cache
+ * - 0b0001 - Invalidate cache way for the corresponding cache: clear the tag,
+ *     data, and vld bits of ways selected
+ */
+/*@{*/
+/*! @brief Set the CINV_WAY field to a new value. */
+#define FMC_WR_PFB0CR_CINV_WAY(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY(value)))
+#define FMC_BWR_PFB0CR_CINV_WAY(base, value) (FMC_WR_PFB0CR_CINV_WAY(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
+ *
+ * These bits determine if the given cache way is locked such that its contents
+ * will not be displaced by future misses. The bit setting definitions are for
+ * each bit in the field.
+ *
+ * Values:
+ * - 0b0000 - Cache way is unlocked and may be displaced
+ * - 0b0001 - Cache way is locked and its contents are not displaced
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */
+#define FMC_RD_PFB0CR_CLCK_WAY(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_CLCK_WAY_MASK) >> FMC_PFB0CR_CLCK_WAY_SHIFT)
+#define FMC_BRD_PFB0CR_CLCK_WAY(base) (FMC_RD_PFB0CR_CLCK_WAY(base))
+
+/*! @brief Set the CLCK_WAY field to a new value. */
+#define FMC_WR_PFB0CR_CLCK_WAY(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CLCK_WAY_MASK, FMC_PFB0CR_CLCK_WAY(value)))
+#define FMC_BWR_PFB0CR_CLCK_WAY(base, value) (FMC_WR_PFB0CR_CLCK_WAY(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 0 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */
+#define FMC_RD_PFB0CR_B0RWSC(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0RWSC_MASK) >> FMC_PFB0CR_B0RWSC_SHIFT)
+#define FMC_BRD_PFB0CR_B0RWSC(base) (FMC_RD_PFB0CR_B0RWSC(base))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_PFB1CR - Flash Bank 1 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFB1CR - Flash Bank 1 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ *
+ * This register has a format similar to that for PFB0CR, except it controls the
+ * operation of flash bank 1, and the "global" cache control fields are empty.
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFB1CR register
+ */
+/*@{*/
+#define FMC_RD_PFB1CR(base)      (FMC_PFB1CR_REG(base))
+#define FMC_WR_PFB1CR(base, value) (FMC_PFB1CR_REG(base) = (value))
+#define FMC_RMW_PFB1CR(base, mask, value) (FMC_WR_PFB1CR(base, (FMC_RD_PFB1CR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) |  (value)))
+#define FMC_CLR_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) & ~(value)))
+#define FMC_TOG_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFB1CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry buffer is enabled in response to
+ * flash read accesses. Its operation is independent from bank 0's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0b0 - Single entry buffer is disabled.
+ * - 0b1 - Single entry buffer is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */
+#define FMC_RD_PFB1CR_B1SEBE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1SEBE_MASK) >> FMC_PFB1CR_B1SEBE_SHIFT)
+#define FMC_BRD_PFB1CR_B1SEBE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1SEBE_SHIFT))
+
+/*! @brief Set the B1SEBE field to a new value. */
+#define FMC_WR_PFB1CR_B1SEBE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1SEBE_MASK, FMC_PFB1CR_B1SEBE(value)))
+#define FMC_BWR_PFB1CR_B1SEBE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1SEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to instruction fetches.
+ * - 0b1 - Enable prefetches in response to instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */
+#define FMC_RD_PFB1CR_B1IPE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1IPE_MASK) >> FMC_PFB1CR_B1IPE_SHIFT)
+#define FMC_BRD_PFB1CR_B1IPE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1IPE_SHIFT))
+
+/*! @brief Set the B1IPE field to a new value. */
+#define FMC_WR_PFB1CR_B1IPE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1IPE_MASK, FMC_PFB1CR_B1IPE(value)))
+#define FMC_BWR_PFB1CR_B1IPE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1IPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to data references.
+ * - 0b1 - Enable prefetches in response to data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */
+#define FMC_RD_PFB1CR_B1DPE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1DPE_MASK) >> FMC_PFB1CR_B1DPE_SHIFT)
+#define FMC_BRD_PFB1CR_B1DPE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DPE_SHIFT))
+
+/*! @brief Set the B1DPE field to a new value. */
+#define FMC_WR_PFB1CR_B1DPE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1DPE_MASK, FMC_PFB1CR_B1DPE(value)))
+#define FMC_BWR_PFB1CR_B1DPE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache instruction fetches.
+ * - 0b1 - Cache instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */
+#define FMC_RD_PFB1CR_B1ICE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1ICE_MASK) >> FMC_PFB1CR_B1ICE_SHIFT)
+#define FMC_BRD_PFB1CR_B1ICE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1ICE_SHIFT))
+
+/*! @brief Set the B1ICE field to a new value. */
+#define FMC_WR_PFB1CR_B1ICE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1ICE_MASK, FMC_PFB1CR_B1ICE(value)))
+#define FMC_BWR_PFB1CR_B1ICE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1ICE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache data references.
+ * - 0b1 - Cache data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */
+#define FMC_RD_PFB1CR_B1DCE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1DCE_MASK) >> FMC_PFB1CR_B1DCE_SHIFT)
+#define FMC_BRD_PFB1CR_B1DCE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DCE_SHIFT))
+
+/*! @brief Set the B1DCE field to a new value. */
+#define FMC_WR_PFB1CR_B1DCE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1DCE_MASK, FMC_PFB1CR_B1DCE(value)))
+#define FMC_BWR_PFB1CR_B1DCE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 1 memory.
+ *
+ * Values:
+ * - 0b00 - 32 bits
+ * - 0b01 - 64 bits
+ * - 0b10 - 128 bits
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1MW field. */
+#define FMC_RD_PFB1CR_B1MW(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1MW_MASK) >> FMC_PFB1CR_B1MW_SHIFT)
+#define FMC_BRD_PFB1CR_B1MW(base) (FMC_RD_PFB1CR_B1MW(base))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 1 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */
+#define FMC_RD_PFB1CR_B1RWSC(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1RWSC_MASK) >> FMC_PFB1CR_B1RWSC_SHIFT)
+#define FMC_BRD_PFB1CR_B1RWSC(base) (FMC_RD_PFB1CR_B1RWSC(base))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW0S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW0S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW0S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW0S(base, index) (FMC_TAGVDW0S_REG(base, index))
+#define FMC_WR_TAGVDW0S(base, index, value) (FMC_TAGVDW0S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW0S(base, index, mask, value) (FMC_WR_TAGVDW0S(base, index, (FMC_RD_TAGVDW0S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW0S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW0S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW0S_valid field. */
+#define FMC_RD_TAGVDW0S_valid(base, index) ((FMC_TAGVDW0S_REG(base, index) & FMC_TAGVDW0S_valid_MASK) >> FMC_TAGVDW0S_valid_SHIFT)
+#define FMC_BRD_TAGVDW0S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW0S_REG(base, index), FMC_TAGVDW0S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW0S_valid(base, index, value) (FMC_RMW_TAGVDW0S(base, index, FMC_TAGVDW0S_valid_MASK, FMC_TAGVDW0S_valid(value)))
+#define FMC_BWR_TAGVDW0S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW0S_REG(base, index), FMC_TAGVDW0S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW0S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW0S_tag field. */
+#define FMC_RD_TAGVDW0S_tag(base, index) ((FMC_TAGVDW0S_REG(base, index) & FMC_TAGVDW0S_tag_MASK) >> FMC_TAGVDW0S_tag_SHIFT)
+#define FMC_BRD_TAGVDW0S_tag(base, index) (FMC_RD_TAGVDW0S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW0S_tag(base, index, value) (FMC_RMW_TAGVDW0S(base, index, FMC_TAGVDW0S_tag_MASK, FMC_TAGVDW0S_tag(value)))
+#define FMC_BWR_TAGVDW0S_tag(base, index, value) (FMC_WR_TAGVDW0S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW1S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW1S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW1S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW1S(base, index) (FMC_TAGVDW1S_REG(base, index))
+#define FMC_WR_TAGVDW1S(base, index, value) (FMC_TAGVDW1S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW1S(base, index, mask, value) (FMC_WR_TAGVDW1S(base, index, (FMC_RD_TAGVDW1S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW1S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW1S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW1S_valid field. */
+#define FMC_RD_TAGVDW1S_valid(base, index) ((FMC_TAGVDW1S_REG(base, index) & FMC_TAGVDW1S_valid_MASK) >> FMC_TAGVDW1S_valid_SHIFT)
+#define FMC_BRD_TAGVDW1S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW1S_REG(base, index), FMC_TAGVDW1S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW1S_valid(base, index, value) (FMC_RMW_TAGVDW1S(base, index, FMC_TAGVDW1S_valid_MASK, FMC_TAGVDW1S_valid(value)))
+#define FMC_BWR_TAGVDW1S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW1S_REG(base, index), FMC_TAGVDW1S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW1S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW1S_tag field. */
+#define FMC_RD_TAGVDW1S_tag(base, index) ((FMC_TAGVDW1S_REG(base, index) & FMC_TAGVDW1S_tag_MASK) >> FMC_TAGVDW1S_tag_SHIFT)
+#define FMC_BRD_TAGVDW1S_tag(base, index) (FMC_RD_TAGVDW1S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW1S_tag(base, index, value) (FMC_RMW_TAGVDW1S(base, index, FMC_TAGVDW1S_tag_MASK, FMC_TAGVDW1S_tag(value)))
+#define FMC_BWR_TAGVDW1S_tag(base, index, value) (FMC_WR_TAGVDW1S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW2S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW2S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW2S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW2S(base, index) (FMC_TAGVDW2S_REG(base, index))
+#define FMC_WR_TAGVDW2S(base, index, value) (FMC_TAGVDW2S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW2S(base, index, mask, value) (FMC_WR_TAGVDW2S(base, index, (FMC_RD_TAGVDW2S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW2S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW2S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW2S_valid field. */
+#define FMC_RD_TAGVDW2S_valid(base, index) ((FMC_TAGVDW2S_REG(base, index) & FMC_TAGVDW2S_valid_MASK) >> FMC_TAGVDW2S_valid_SHIFT)
+#define FMC_BRD_TAGVDW2S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW2S_REG(base, index), FMC_TAGVDW2S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW2S_valid(base, index, value) (FMC_RMW_TAGVDW2S(base, index, FMC_TAGVDW2S_valid_MASK, FMC_TAGVDW2S_valid(value)))
+#define FMC_BWR_TAGVDW2S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW2S_REG(base, index), FMC_TAGVDW2S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW2S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW2S_tag field. */
+#define FMC_RD_TAGVDW2S_tag(base, index) ((FMC_TAGVDW2S_REG(base, index) & FMC_TAGVDW2S_tag_MASK) >> FMC_TAGVDW2S_tag_SHIFT)
+#define FMC_BRD_TAGVDW2S_tag(base, index) (FMC_RD_TAGVDW2S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW2S_tag(base, index, value) (FMC_RMW_TAGVDW2S(base, index, FMC_TAGVDW2S_tag_MASK, FMC_TAGVDW2S_tag(value)))
+#define FMC_BWR_TAGVDW2S_tag(base, index, value) (FMC_WR_TAGVDW2S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW3S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW3S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW3S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW3S(base, index) (FMC_TAGVDW3S_REG(base, index))
+#define FMC_WR_TAGVDW3S(base, index, value) (FMC_TAGVDW3S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW3S(base, index, mask, value) (FMC_WR_TAGVDW3S(base, index, (FMC_RD_TAGVDW3S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW3S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW3S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW3S_valid field. */
+#define FMC_RD_TAGVDW3S_valid(base, index) ((FMC_TAGVDW3S_REG(base, index) & FMC_TAGVDW3S_valid_MASK) >> FMC_TAGVDW3S_valid_SHIFT)
+#define FMC_BRD_TAGVDW3S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW3S_REG(base, index), FMC_TAGVDW3S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW3S_valid(base, index, value) (FMC_RMW_TAGVDW3S(base, index, FMC_TAGVDW3S_valid_MASK, FMC_TAGVDW3S_valid(value)))
+#define FMC_BWR_TAGVDW3S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW3S_REG(base, index), FMC_TAGVDW3S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW3S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW3S_tag field. */
+#define FMC_RD_TAGVDW3S_tag(base, index) ((FMC_TAGVDW3S_REG(base, index) & FMC_TAGVDW3S_tag_MASK) >> FMC_TAGVDW3S_tag_SHIFT)
+#define FMC_BRD_TAGVDW3S_tag(base, index) (FMC_RD_TAGVDW3S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW3S_tag(base, index, value) (FMC_RMW_TAGVDW3S(base, index, FMC_TAGVDW3S_tag_MASK, FMC_TAGVDW3S_tag(value)))
+#define FMC_BWR_TAGVDW3S_tag(base, index, value) (FMC_WR_TAGVDW3S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_DATA_U - Cache Data Storage (upper word)
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_DATA_U - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_DATA_U register
+ */
+/*@{*/
+#define FMC_RD_DATA_U(base, index, index2) (FMC_DATA_U_REG(base, index, index2))
+#define FMC_WR_DATA_U(base, index, index2, value) (FMC_DATA_U_REG(base, index, index2) = (value))
+#define FMC_RMW_DATA_U(base, index, index2, mask, value) (FMC_WR_DATA_U(base, index, index2, (FMC_RD_DATA_U(base, index, index2) & ~(mask)) | (value)))
+#define FMC_SET_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) |  (value)))
+#define FMC_CLR_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) & ~(value)))
+#define FMC_TOG_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_DATA_L - Cache Data Storage (lower word)
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_DATA_L - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_DATA_L register
+ */
+/*@{*/
+#define FMC_RD_DATA_L(base, index, index2) (FMC_DATA_L_REG(base, index, index2))
+#define FMC_WR_DATA_L(base, index, index2, value) (FMC_DATA_L_REG(base, index, index2) = (value))
+#define FMC_RMW_DATA_L(base, index, index2, mask, value) (FMC_WR_DATA_L(base, index, index2, (FMC_RD_DATA_L(base, index, index2) & ~(mask)) | (value)))
+#define FMC_SET_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) |  (value)))
+#define FMC_CLR_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) & ~(value)))
+#define FMC_TOG_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FTFE
+ *
+ * Flash Memory Interface
+ *
+ * Registers defined in this header file:
+ * - FTFE_FSTAT - Flash Status Register
+ * - FTFE_FCNFG - Flash Configuration Register
+ * - FTFE_FSEC - Flash Security Register
+ * - FTFE_FOPT - Flash Option Register
+ * - FTFE_FCCOB3 - Flash Common Command Object Registers
+ * - FTFE_FCCOB2 - Flash Common Command Object Registers
+ * - FTFE_FCCOB1 - Flash Common Command Object Registers
+ * - FTFE_FCCOB0 - Flash Common Command Object Registers
+ * - FTFE_FCCOB7 - Flash Common Command Object Registers
+ * - FTFE_FCCOB6 - Flash Common Command Object Registers
+ * - FTFE_FCCOB5 - Flash Common Command Object Registers
+ * - FTFE_FCCOB4 - Flash Common Command Object Registers
+ * - FTFE_FCCOBB - Flash Common Command Object Registers
+ * - FTFE_FCCOBA - Flash Common Command Object Registers
+ * - FTFE_FCCOB9 - Flash Common Command Object Registers
+ * - FTFE_FCCOB8 - Flash Common Command Object Registers
+ * - FTFE_FPROT3 - Program Flash Protection Registers
+ * - FTFE_FPROT2 - Program Flash Protection Registers
+ * - FTFE_FPROT1 - Program Flash Protection Registers
+ * - FTFE_FPROT0 - Program Flash Protection Registers
+ * - FTFE_FEPROT - EEPROM Protection Register
+ * - FTFE_FDPROT - Data Flash Protection Register
+ */
+
+#define FTFE_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFE module. */
+#define FTFE_IDX (0U) /*!< Instance number for FTFE. */
+
+/*******************************************************************************
+ * FTFE_FSTAT - Flash Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FSTAT - Flash Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FSTAT register reports the operational status of the FTFE module. The
+ * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0
+ * bit is read only. The unassigned bits read 0 and are not writable. When set, the
+ * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this
+ * register prevent the launch of any more commands or writes to the FlexRAM (when
+ * EEERDY is set) until the flag is cleared (by writing a one to it).
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FSTAT register
+ */
+/*@{*/
+#define FTFE_RD_FSTAT(base)      (FTFE_FSTAT_REG(base))
+#define FTFE_WR_FSTAT(base, value) (FTFE_FSTAT_REG(base) = (value))
+#define FTFE_RMW_FSTAT(base, mask, value) (FTFE_WR_FSTAT(base, (FTFE_RD_FSTAT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) |  (value)))
+#define FTFE_CLR_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) & ~(value)))
+#define FTFE_TOG_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FSTAT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO)
+ *
+ * The MGSTAT0 status flag is set if an error is detected during execution of an
+ * FTFE command or during the flash reset sequence. As a status flag, this bit
+ * cannot (and need not) be cleared by the user like the other error flags in this
+ * register. The value of the MGSTAT0 bit for "command-N" is valid only at the
+ * end of the "command-N" execution when CCIF=1 and before the next command has
+ * been launched. At some point during the execution of "command-N+1," the previous
+ * result is discarded and any previous error is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field. */
+#define FTFE_RD_FSTAT_MGSTAT0(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_MGSTAT0_MASK) >> FTFE_FSTAT_MGSTAT0_SHIFT)
+#define FTFE_BRD_FSTAT_MGSTAT0(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_MGSTAT0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C)
+ *
+ * The FPVIOL error bit indicates an attempt was made to program or erase an
+ * address in a protected area of program flash or data flash memory during a
+ * command write sequence or a write was attempted to a protected area of the FlexRAM
+ * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared
+ * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a
+ * 0 to the FPVIOL bit has no effect.
+ *
+ * Values:
+ * - 0b0 - No protection violation detected
+ * - 0b1 - Protection violation detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_FPVIOL field. */
+#define FTFE_RD_FSTAT_FPVIOL(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_FPVIOL_MASK) >> FTFE_FSTAT_FPVIOL_SHIFT)
+#define FTFE_BRD_FSTAT_FPVIOL(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_FPVIOL_SHIFT))
+
+/*! @brief Set the FPVIOL field to a new value. */
+#define FTFE_WR_FSTAT_FPVIOL(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_FPVIOL(value)))
+#define FTFE_BWR_FSTAT_FPVIOL(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_FPVIOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field ACCERR[5] (W1C)
+ *
+ * The ACCERR error bit indicates an illegal access has occurred to an FTFE
+ * resource caused by a violation of the command write sequence or issuing an illegal
+ * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch
+ * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
+ * ACCERR bit has no effect.
+ *
+ * Values:
+ * - 0b0 - No access error detected
+ * - 0b1 - Access error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_ACCERR field. */
+#define FTFE_RD_FSTAT_ACCERR(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_ACCERR_MASK) >> FTFE_FSTAT_ACCERR_SHIFT)
+#define FTFE_BRD_FSTAT_ACCERR(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_ACCERR_SHIFT))
+
+/*! @brief Set the ACCERR field to a new value. */
+#define FTFE_WR_FSTAT_ACCERR(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_ACCERR(value)))
+#define FTFE_BWR_FSTAT_ACCERR(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_ACCERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C)
+ *
+ * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE
+ * resource that was being manipulated by an FTFE command (CCIF=0). Any
+ * simultaneous access is detected as a collision error by the block arbitration logic. The
+ * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by
+ * writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
+ *
+ * Values:
+ * - 0b0 - No collision error detected
+ * - 0b1 - Collision error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_RDCOLERR field. */
+#define FTFE_RD_FSTAT_RDCOLERR(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_RDCOLERR_MASK) >> FTFE_FSTAT_RDCOLERR_SHIFT)
+#define FTFE_BRD_FSTAT_RDCOLERR(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_RDCOLERR_SHIFT))
+
+/*! @brief Set the RDCOLERR field to a new value. */
+#define FTFE_WR_FSTAT_RDCOLERR(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_RDCOLERR(value)))
+#define FTFE_BWR_FSTAT_RDCOLERR(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_RDCOLERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field CCIF[7] (W1C)
+ *
+ * The CCIF flag indicates that a FTFE command or EEPROM file system operation
+ * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a
+ * command, and CCIF stays low until command completion or command violation. The
+ * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE,
+ * and CCIF stays low until the EEPROM file system has created the associated
+ * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory
+ * controller at the end of the reset initialization sequence. Depending on how
+ * quickly the read occurs after reset release, the user may or may not see the 0
+ * hardware reset value.
+ *
+ * Values:
+ * - 0b0 - FTFE command or EEPROM file system operation in progress
+ * - 0b1 - FTFE command or EEPROM file system operation has completed
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_CCIF field. */
+#define FTFE_RD_FSTAT_CCIF(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_CCIF_MASK) >> FTFE_FSTAT_CCIF_SHIFT)
+#define FTFE_BRD_FSTAT_CCIF(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_CCIF_SHIFT))
+
+/*! @brief Set the CCIF field to a new value. */
+#define FTFE_WR_FSTAT_CCIF(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_CCIF_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_RDCOLERR_MASK), FTFE_FSTAT_CCIF(value)))
+#define FTFE_BWR_FSTAT_CCIF(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_CCIF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCNFG - Flash Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCNFG - Flash Configuration Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides information on the current functional state of the
+ * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write
+ * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned
+ * bits read as noted and are not writable. The reset values for the SWAP, PFLSH,
+ * RAMRDY, and EEERDY bits are determined during the reset sequence.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCNFG register
+ */
+/*@{*/
+#define FTFE_RD_FCNFG(base)      (FTFE_FCNFG_REG(base))
+#define FTFE_WR_FCNFG(base, value) (FTFE_FCNFG_REG(base) = (value))
+#define FTFE_RMW_FCNFG(base, mask, value) (FTFE_WR_FCNFG(base, (FTFE_RD_FCNFG(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) |  (value)))
+#define FTFE_CLR_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) & ~(value)))
+#define FTFE_TOG_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FCNFG bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCNFG, field EEERDY[0] (RO)
+ *
+ * For devices with FlexNVM: This flag indicates if the EEPROM backup data has
+ * been copied to the FlexRAM and is therefore available for read access. During
+ * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if
+ * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM:
+ * This bit is reserved.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FlexRAM is not available for EEPROM
+ *     operation.
+ * - 0b1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations
+ *     where: reads from the FlexRAM return data previously written to the
+ *     FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the
+ *     written data in the FlexRAM and EEPROM backup.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_EEERDY field. */
+#define FTFE_RD_FCNFG_EEERDY(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_EEERDY_MASK) >> FTFE_FCNFG_EEERDY_SHIFT)
+#define FTFE_BRD_FCNFG_EEERDY(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_EEERDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field RAMRDY[1] (RO)
+ *
+ * This flag indicates the current status of the FlexRAM/ programming
+ * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally
+ * controlled by the Set FlexRAM Function command. During the reset sequence, the
+ * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will
+ * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is
+ * cleared if the Program Partition command is run to partition the FlexNVM block
+ * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks
+ * command or execution of the erase-all operation triggered external to the FTFE.
+ * For devices without FlexNVM: This bit should always be set.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FlexRAM is not available for traditional
+ *     RAM access. For devices without FlexNVM: Programming acceleration RAM is not
+ *     available.
+ * - 0b1 - For devices with FlexNVM: FlexRAM is available as traditional RAM
+ *     only; writes to the FlexRAM do not trigger EEPROM operations. For devices
+ *     without FlexNVM: Programming acceleration RAM is available.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_RAMRDY field. */
+#define FTFE_RD_FCNFG_RAMRDY(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_RAMRDY_MASK) >> FTFE_FCNFG_RAMRDY_SHIFT)
+#define FTFE_BRD_FCNFG_RAMRDY(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RAMRDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field PFLSH[2] (RO)
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FTFE configuration supports two program
+ *     flash blocks and two FlexNVM blocks For devices with program flash only:
+ *     Reserved
+ * - 0b1 - For devices with FlexNVM: Reserved For devices with program flash
+ *     only: FTFE configuration supports four program flash blocks
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_PFLSH field. */
+#define FTFE_RD_FCNFG_PFLSH(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_PFLSH_MASK) >> FTFE_FCNFG_PFLSH_SHIFT)
+#define FTFE_BRD_FCNFG_PFLSH(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_PFLSH_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field SWAP[3] (RO)
+ *
+ * The SWAP flag indicates which half of the program flash space is located at
+ * relative address 0x0000. The state of the SWAP flag is set by the FTFE during
+ * the reset sequence. See for information on swap management.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: Program flash 0 block is located at
+ *     relative address 0x0000 For devices with program flash only: Program flash 0
+ *     block is located at relative address 0x0000
+ * - 0b1 - For devices with FlexNVM: Reserved For devices with program flash
+ *     only: Program flash 1 block is located at relative address 0x0000
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_SWAP field. */
+#define FTFE_RD_FCNFG_SWAP(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_SWAP_MASK) >> FTFE_FCNFG_SWAP_SHIFT)
+#define FTFE_BRD_FCNFG_SWAP(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_SWAP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW)
+ *
+ * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector
+ * command while it is executing.
+ *
+ * Values:
+ * - 0b0 - No suspend requested
+ * - 0b1 - Suspend the current Erase Flash Sector command execution.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_ERSSUSP field. */
+#define FTFE_RD_FCNFG_ERSSUSP(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_ERSSUSP_MASK) >> FTFE_FCNFG_ERSSUSP_SHIFT)
+#define FTFE_BRD_FCNFG_ERSSUSP(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSSUSP_SHIFT))
+
+/*! @brief Set the ERSSUSP field to a new value. */
+#define FTFE_WR_FCNFG_ERSSUSP(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_ERSSUSP_MASK, FTFE_FCNFG_ERSSUSP(value)))
+#define FTFE_BWR_FCNFG_ERSSUSP(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSSUSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO)
+ *
+ * This bit issues a request to the memory controller to execute the Erase All
+ * Blocks command and release security. ERSAREQ is not directly writable but is
+ * under indirect user control. Refer to the device's Chip Configuration details on
+ * how to request this command. The ERSAREQ bit sets when an erase all request
+ * is triggered external to the FTFE and CCIF is set (no command is currently
+ * being executed). ERSAREQ is cleared by the FTFE when the operation completes.
+ *
+ * Values:
+ * - 0b0 - No request or request complete
+ * - 0b1 - Request to: run the Erase All Blocks command, verify the erased
+ *     state, program the security byte in the Flash Configuration Field to the
+ *     unsecure state, and release MCU security by setting the FSEC[SEC] field to the
+ *     unsecure state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_ERSAREQ field. */
+#define FTFE_RD_FCNFG_ERSAREQ(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_ERSAREQ_MASK) >> FTFE_FCNFG_ERSAREQ_SHIFT)
+#define FTFE_BRD_FCNFG_ERSAREQ(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSAREQ_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW)
+ *
+ * The RDCOLLIE bit controls interrupt generation when an FTFE read collision
+ * error occurs.
+ *
+ * Values:
+ * - 0b0 - Read collision error interrupt disabled
+ * - 0b1 - Read collision error interrupt enabled. An interrupt request is
+ *     generated whenever an FTFE read collision error is detected (see the
+ *     description of FSTAT[RDCOLERR]).
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field. */
+#define FTFE_RD_FCNFG_RDCOLLIE(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_RDCOLLIE_MASK) >> FTFE_FCNFG_RDCOLLIE_SHIFT)
+#define FTFE_BRD_FCNFG_RDCOLLIE(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RDCOLLIE_SHIFT))
+
+/*! @brief Set the RDCOLLIE field to a new value. */
+#define FTFE_WR_FCNFG_RDCOLLIE(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_RDCOLLIE_MASK, FTFE_FCNFG_RDCOLLIE(value)))
+#define FTFE_BWR_FCNFG_RDCOLLIE(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RDCOLLIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field CCIE[7] (RW)
+ *
+ * The CCIE bit controls interrupt generation when an FTFE command completes.
+ *
+ * Values:
+ * - 0b0 - Command complete interrupt disabled
+ * - 0b1 - Command complete interrupt enabled. An interrupt request is generated
+ *     whenever the FSTAT[CCIF] flag is set.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_CCIE field. */
+#define FTFE_RD_FCNFG_CCIE(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_CCIE_MASK) >> FTFE_FCNFG_CCIE_SHIFT)
+#define FTFE_BRD_FCNFG_CCIE(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_CCIE_SHIFT))
+
+/*! @brief Set the CCIE field to a new value. */
+#define FTFE_WR_FCNFG_CCIE(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_CCIE_MASK, FTFE_FCNFG_CCIE(value)))
+#define FTFE_BWR_FCNFG_CCIE(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_CCIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FSEC - Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FSEC - Flash Security Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This read-only register holds all bits associated with the security of the
+ * MCU and FTFE module. During the reset sequence, the register is loaded with the
+ * contents of the flash security byte in the Flash Configuration Field located
+ * in program flash memory. The Flash basis for the values is signified by X in
+ * the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FSEC register
+ */
+/*@{*/
+#define FTFE_RD_FSEC(base)       (FTFE_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FSEC bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSEC, field SEC[1:0] (RO)
+ *
+ * These bits define the security state of the MCU. In the secure state, the MCU
+ * limits access to FTFE module resources. The limitations are defined per
+ * device and are detailed in the Chip Configuration details. If the FTFE module is
+ * unsecured using backdoor key access, the SEC bits are forced to 10b.
+ *
+ * Values:
+ * - 0b00 - MCU security status is secure
+ * - 0b01 - MCU security status is secure
+ * - 0b10 - MCU security status is unsecure (The standard shipping condition of
+ *     the FTFE is unsecure.)
+ * - 0b11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_SEC field. */
+#define FTFE_RD_FSEC_SEC(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_SEC_MASK) >> FTFE_FSEC_SEC_SHIFT)
+#define FTFE_BRD_FSEC_SEC(base) (FTFE_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field FSLACC[3:2] (RO)
+ *
+ * These bits enable or disable access to the flash memory contents during
+ * returned part failure analysis at Freescale. When SEC is secure and FSLACC is
+ * denied, access to the program flash contents is denied and any failure analysis
+ * performed by Freescale factory test must begin with a full erase to unsecure the
+ * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is
+ * granted), Freescale factory testing has visibility of the current flash
+ * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to
+ * secure. When the SEC field is set to unsecure, the FSLACC setting does not
+ * matter.
+ *
+ * Values:
+ * - 0b00 - Freescale factory access granted
+ * - 0b01 - Freescale factory access denied
+ * - 0b10 - Freescale factory access denied
+ * - 0b11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_FSLACC field. */
+#define FTFE_RD_FSEC_FSLACC(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_FSLACC_MASK) >> FTFE_FSEC_FSLACC_SHIFT)
+#define FTFE_BRD_FSEC_FSLACC(base) (FTFE_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field MEEN[5:4] (RO)
+ *
+ * Enables and disables mass erase capability of the FTFE module. The state of
+ * the MEEN bits is only relevant when the SEC bits are set to secure outside of
+ * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does
+ * not matter.
+ *
+ * Values:
+ * - 0b00 - Mass erase is enabled
+ * - 0b01 - Mass erase is enabled
+ * - 0b10 - Mass erase is disabled
+ * - 0b11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_MEEN field. */
+#define FTFE_RD_FSEC_MEEN(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_MEEN_MASK) >> FTFE_FSEC_MEEN_SHIFT)
+#define FTFE_BRD_FSEC_MEEN(base) (FTFE_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field KEYEN[7:6] (RO)
+ *
+ * These bits enable and disable backdoor key access to the FTFE module.
+ *
+ * Values:
+ * - 0b00 - Backdoor key access disabled
+ * - 0b01 - Backdoor key access disabled (preferred KEYEN state to disable
+ *     backdoor key access)
+ * - 0b10 - Backdoor key access enabled
+ * - 0b11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_KEYEN field. */
+#define FTFE_RD_FSEC_KEYEN(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_KEYEN_MASK) >> FTFE_FSEC_KEYEN_SHIFT)
+#define FTFE_BRD_FSEC_KEYEN(base) (FTFE_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FOPT - Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FOPT - Flash Option Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * The flash option register allows the MCU to customize its operations by
+ * examining the state of these read-only bits, which are loaded from NVM at reset.
+ * The function of the bits is defined in the device's Chip Configuration details.
+ * All bits in the register are read-only. During the reset sequence, the
+ * register is loaded from the flash nonvolatile option byte in the Flash Configuration
+ * Field located in program flash memory. The flash basis for the values is
+ * signified by X in the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FOPT register
+ */
+/*@{*/
+#define FTFE_RD_FOPT(base)       (FTFE_FOPT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB3 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB3 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB3 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB3(base)     (FTFE_FCCOB3_REG(base))
+#define FTFE_WR_FCCOB3(base, value) (FTFE_FCCOB3_REG(base) = (value))
+#define FTFE_RMW_FCCOB3(base, mask, value) (FTFE_WR_FCCOB3(base, (FTFE_RD_FCCOB3(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) |  (value)))
+#define FTFE_CLR_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) & ~(value)))
+#define FTFE_TOG_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB2 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB2 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB2 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB2(base)     (FTFE_FCCOB2_REG(base))
+#define FTFE_WR_FCCOB2(base, value) (FTFE_FCCOB2_REG(base) = (value))
+#define FTFE_RMW_FCCOB2(base, mask, value) (FTFE_WR_FCCOB2(base, (FTFE_RD_FCCOB2(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) |  (value)))
+#define FTFE_CLR_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) & ~(value)))
+#define FTFE_TOG_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB1 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB1 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB1 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB1(base)     (FTFE_FCCOB1_REG(base))
+#define FTFE_WR_FCCOB1(base, value) (FTFE_FCCOB1_REG(base) = (value))
+#define FTFE_RMW_FCCOB1(base, mask, value) (FTFE_WR_FCCOB1(base, (FTFE_RD_FCCOB1(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) |  (value)))
+#define FTFE_CLR_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) & ~(value)))
+#define FTFE_TOG_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB0 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB0 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB0 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB0(base)     (FTFE_FCCOB0_REG(base))
+#define FTFE_WR_FCCOB0(base, value) (FTFE_FCCOB0_REG(base) = (value))
+#define FTFE_RMW_FCCOB0(base, mask, value) (FTFE_WR_FCCOB0(base, (FTFE_RD_FCCOB0(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) |  (value)))
+#define FTFE_CLR_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) & ~(value)))
+#define FTFE_TOG_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB7 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB7 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB7 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB7(base)     (FTFE_FCCOB7_REG(base))
+#define FTFE_WR_FCCOB7(base, value) (FTFE_FCCOB7_REG(base) = (value))
+#define FTFE_RMW_FCCOB7(base, mask, value) (FTFE_WR_FCCOB7(base, (FTFE_RD_FCCOB7(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) |  (value)))
+#define FTFE_CLR_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) & ~(value)))
+#define FTFE_TOG_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB6 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB6 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB6 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB6(base)     (FTFE_FCCOB6_REG(base))
+#define FTFE_WR_FCCOB6(base, value) (FTFE_FCCOB6_REG(base) = (value))
+#define FTFE_RMW_FCCOB6(base, mask, value) (FTFE_WR_FCCOB6(base, (FTFE_RD_FCCOB6(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) |  (value)))
+#define FTFE_CLR_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) & ~(value)))
+#define FTFE_TOG_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB5 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB5 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB5 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB5(base)     (FTFE_FCCOB5_REG(base))
+#define FTFE_WR_FCCOB5(base, value) (FTFE_FCCOB5_REG(base) = (value))
+#define FTFE_RMW_FCCOB5(base, mask, value) (FTFE_WR_FCCOB5(base, (FTFE_RD_FCCOB5(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) |  (value)))
+#define FTFE_CLR_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) & ~(value)))
+#define FTFE_TOG_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB4 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB4 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB4 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB4(base)     (FTFE_FCCOB4_REG(base))
+#define FTFE_WR_FCCOB4(base, value) (FTFE_FCCOB4_REG(base) = (value))
+#define FTFE_RMW_FCCOB4(base, mask, value) (FTFE_WR_FCCOB4(base, (FTFE_RD_FCCOB4(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) |  (value)))
+#define FTFE_CLR_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) & ~(value)))
+#define FTFE_TOG_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOBB - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOBB - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBB register
+ */
+/*@{*/
+#define FTFE_RD_FCCOBB(base)     (FTFE_FCCOBB_REG(base))
+#define FTFE_WR_FCCOBB(base, value) (FTFE_FCCOBB_REG(base) = (value))
+#define FTFE_RMW_FCCOBB(base, mask, value) (FTFE_WR_FCCOBB(base, (FTFE_RD_FCCOBB(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) |  (value)))
+#define FTFE_CLR_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) & ~(value)))
+#define FTFE_TOG_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOBA - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOBA - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBA register
+ */
+/*@{*/
+#define FTFE_RD_FCCOBA(base)     (FTFE_FCCOBA_REG(base))
+#define FTFE_WR_FCCOBA(base, value) (FTFE_FCCOBA_REG(base) = (value))
+#define FTFE_RMW_FCCOBA(base, mask, value) (FTFE_WR_FCCOBA(base, (FTFE_RD_FCCOBA(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) |  (value)))
+#define FTFE_CLR_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) & ~(value)))
+#define FTFE_TOG_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB9 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB9 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB9 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB9(base)     (FTFE_FCCOB9_REG(base))
+#define FTFE_WR_FCCOB9(base, value) (FTFE_FCCOB9_REG(base) = (value))
+#define FTFE_RMW_FCCOB9(base, mask, value) (FTFE_WR_FCCOB9(base, (FTFE_RD_FCCOB9(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) |  (value)))
+#define FTFE_CLR_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) & ~(value)))
+#define FTFE_TOG_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB8 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB8 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB8 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB8(base)     (FTFE_FCCOB8_REG(base))
+#define FTFE_WR_FCCOB8(base, value) (FTFE_FCCOB8_REG(base) = (value))
+#define FTFE_RMW_FCCOB8(base, mask, value) (FTFE_WR_FCCOB8(base, (FTFE_RD_FCCOB8(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) |  (value)))
+#define FTFE_CLR_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) & ~(value)))
+#define FTFE_TOG_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT3 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT3 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT3 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT3(base)     (FTFE_FPROT3_REG(base))
+#define FTFE_WR_FPROT3(base, value) (FTFE_FPROT3_REG(base) = (value))
+#define FTFE_RMW_FPROT3(base, mask, value) (FTFE_WR_FPROT3(base, (FTFE_RD_FPROT3(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) |  (value)))
+#define FTFE_CLR_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) & ~(value)))
+#define FTFE_TOG_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT2 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT2 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT2 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT2(base)     (FTFE_FPROT2_REG(base))
+#define FTFE_WR_FPROT2(base, value) (FTFE_FPROT2_REG(base) = (value))
+#define FTFE_RMW_FPROT2(base, mask, value) (FTFE_WR_FPROT2(base, (FTFE_RD_FPROT2(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) |  (value)))
+#define FTFE_CLR_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) & ~(value)))
+#define FTFE_TOG_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT1 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT1 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT1 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT1(base)     (FTFE_FPROT1_REG(base))
+#define FTFE_WR_FPROT1(base, value) (FTFE_FPROT1_REG(base) = (value))
+#define FTFE_RMW_FPROT1(base, mask, value) (FTFE_WR_FPROT1(base, (FTFE_RD_FPROT1(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) |  (value)))
+#define FTFE_CLR_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) & ~(value)))
+#define FTFE_TOG_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT0 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT0 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT0 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT0(base)     (FTFE_FPROT0_REG(base))
+#define FTFE_WR_FPROT0(base, value) (FTFE_FPROT0_REG(base) = (value))
+#define FTFE_RMW_FPROT0(base, mask, value) (FTFE_WR_FPROT0(base, (FTFE_RD_FPROT0(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) |  (value)))
+#define FTFE_CLR_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) & ~(value)))
+#define FTFE_TOG_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FEPROT - EEPROM Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FEPROT - EEPROM Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of
+ * the FlexRAM are protected against program and erase operations. Protected
+ * EEPROM regions cannot have their content changed by writing to it. Unprotected
+ * regions can be changed by writing to the FlexRAM. For devices with program flash
+ * only: This register is reserved and not used.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FEPROT register
+ */
+/*@{*/
+#define FTFE_RD_FEPROT(base)     (FTFE_FEPROT_REG(base))
+#define FTFE_WR_FEPROT(base, value) (FTFE_FEPROT_REG(base) = (value))
+#define FTFE_RMW_FEPROT(base, mask, value) (FTFE_WR_FEPROT(base, (FTFE_RD_FEPROT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) |  (value)))
+#define FTFE_CLR_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) & ~(value)))
+#define FTFE_TOG_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FDPROT - Data Flash Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FDPROT - Data Flash Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FDPROT register defines which data flash regions are protected against
+ * program and erase operations. Protected Flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by both program and erase
+ * operations.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FDPROT register
+ */
+/*@{*/
+#define FTFE_RD_FDPROT(base)     (FTFE_FDPROT_REG(base))
+#define FTFE_WR_FDPROT(base, value) (FTFE_FDPROT_REG(base) = (value))
+#define FTFE_RMW_FDPROT(base, mask, value) (FTFE_WR_FDPROT(base, (FTFE_RD_FDPROT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) |  (value)))
+#define FTFE_CLR_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) & ~(value)))
+#define FTFE_TOG_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FTM
+ *
+ * FlexTimer Module
+ *
+ * Registers defined in this header file:
+ * - FTM_SC - Status And Control
+ * - FTM_CNT - Counter
+ * - FTM_MOD - Modulo
+ * - FTM_CnSC - Channel (n) Status And Control
+ * - FTM_CnV - Channel (n) Value
+ * - FTM_CNTIN - Counter Initial Value
+ * - FTM_STATUS - Capture And Compare Status
+ * - FTM_MODE - Features Mode Selection
+ * - FTM_SYNC - Synchronization
+ * - FTM_OUTINIT - Initial State For Channels Output
+ * - FTM_OUTMASK - Output Mask
+ * - FTM_COMBINE - Function For Linked Channels
+ * - FTM_DEADTIME - Deadtime Insertion Control
+ * - FTM_EXTTRIG - FTM External Trigger
+ * - FTM_POL - Channels Polarity
+ * - FTM_FMS - Fault Mode Status
+ * - FTM_FILTER - Input Capture Filter Control
+ * - FTM_FLTCTRL - Fault Control
+ * - FTM_QDCTRL - Quadrature Decoder Control And Status
+ * - FTM_CONF - Configuration
+ * - FTM_FLTPOL - FTM Fault Input Polarity
+ * - FTM_SYNCONF - Synchronization Configuration
+ * - FTM_INVCTRL - FTM Inverting Control
+ * - FTM_SWOCTRL - FTM Software Output Control
+ * - FTM_PWMLOAD - FTM PWM Load
+ */
+
+#define FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
+#define FTM0_IDX (0U) /*!< Instance number for FTM0. */
+#define FTM1_IDX (1U) /*!< Instance number for FTM1. */
+#define FTM2_IDX (2U) /*!< Instance number for FTM2. */
+#define FTM3_IDX (3U) /*!< Instance number for FTM3. */
+
+/*******************************************************************************
+ * FTM_SC - Status And Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SC - Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * SC contains the overflow status flag and control bits used to configure the
+ * interrupt enable, FTM configuration, clock source, and prescaler factor. These
+ * controls relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SC register
+ */
+/*@{*/
+#define FTM_RD_SC(base)          (FTM_SC_REG(base))
+#define FTM_WR_SC(base, value)   (FTM_SC_REG(base) = (value))
+#define FTM_RMW_SC(base, mask, value) (FTM_WR_SC(base, (FTM_RD_SC(base) & ~(mask)) | (value)))
+#define FTM_SET_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) |  (value)))
+#define FTM_CLR_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) & ~(value)))
+#define FTM_TOG_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SC bitfields
+ */
+
+/*!
+ * @name Register FTM_SC, field PS[2:0] (RW)
+ *
+ * Selects one of 8 division factors for the clock source selected by CLKS. The
+ * new prescaler factor affects the clock source on the next system clock cycle
+ * after the new value is updated into the register bits. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b000 - Divide by 1
+ * - 0b001 - Divide by 2
+ * - 0b010 - Divide by 4
+ * - 0b011 - Divide by 8
+ * - 0b100 - Divide by 16
+ * - 0b101 - Divide by 32
+ * - 0b110 - Divide by 64
+ * - 0b111 - Divide by 128
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_PS field. */
+#define FTM_RD_SC_PS(base)   ((FTM_SC_REG(base) & FTM_SC_PS_MASK) >> FTM_SC_PS_SHIFT)
+#define FTM_BRD_SC_PS(base)  (FTM_RD_SC_PS(base))
+
+/*! @brief Set the PS field to a new value. */
+#define FTM_WR_SC_PS(base, value) (FTM_RMW_SC(base, FTM_SC_PS_MASK, FTM_SC_PS(value)))
+#define FTM_BWR_SC_PS(base, value) (FTM_WR_SC_PS(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field CLKS[4:3] (RW)
+ *
+ * Selects one of the three FTM counter clock sources. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b00 - No clock selected. This in effect disables the FTM counter.
+ * - 0b01 - System clock
+ * - 0b10 - Fixed frequency clock
+ * - 0b11 - External clock
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_CLKS field. */
+#define FTM_RD_SC_CLKS(base) ((FTM_SC_REG(base) & FTM_SC_CLKS_MASK) >> FTM_SC_CLKS_SHIFT)
+#define FTM_BRD_SC_CLKS(base) (FTM_RD_SC_CLKS(base))
+
+/*! @brief Set the CLKS field to a new value. */
+#define FTM_WR_SC_CLKS(base, value) (FTM_RMW_SC(base, FTM_SC_CLKS_MASK, FTM_SC_CLKS(value)))
+#define FTM_BWR_SC_CLKS(base, value) (FTM_WR_SC_CLKS(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field CPWMS[5] (RW)
+ *
+ * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
+ * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ *
+ * Values:
+ * - 0b0 - FTM counter operates in Up Counting mode.
+ * - 0b1 - FTM counter operates in Up-Down Counting mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_CPWMS field. */
+#define FTM_RD_SC_CPWMS(base) ((FTM_SC_REG(base) & FTM_SC_CPWMS_MASK) >> FTM_SC_CPWMS_SHIFT)
+#define FTM_BRD_SC_CPWMS(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_CPWMS_SHIFT))
+
+/*! @brief Set the CPWMS field to a new value. */
+#define FTM_WR_SC_CPWMS(base, value) (FTM_RMW_SC(base, FTM_SC_CPWMS_MASK, FTM_SC_CPWMS(value)))
+#define FTM_BWR_SC_CPWMS(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_CPWMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field TOIE[6] (RW)
+ *
+ * Enables FTM overflow interrupts.
+ *
+ * Values:
+ * - 0b0 - Disable TOF interrupts. Use software polling.
+ * - 0b1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_TOIE field. */
+#define FTM_RD_SC_TOIE(base) ((FTM_SC_REG(base) & FTM_SC_TOIE_MASK) >> FTM_SC_TOIE_SHIFT)
+#define FTM_BRD_SC_TOIE(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOIE_SHIFT))
+
+/*! @brief Set the TOIE field to a new value. */
+#define FTM_WR_SC_TOIE(base, value) (FTM_RMW_SC(base, FTM_SC_TOIE_MASK, FTM_SC_TOIE(value)))
+#define FTM_BWR_SC_TOIE(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field TOF[7] (ROWZ)
+ *
+ * Set by hardware when the FTM counter passes the value in the MOD register.
+ * The TOF bit is cleared by reading the SC register while TOF is set and then
+ * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
+ * occurs between the read and write operations, the write operation has no
+ * effect; therefore, TOF remains set indicating an overflow has occurred. In this
+ * case, a TOF interrupt request is not lost due to the clearing sequence for a
+ * previous TOF.
+ *
+ * Values:
+ * - 0b0 - FTM counter has not overflowed.
+ * - 0b1 - FTM counter has overflowed.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_TOF field. */
+#define FTM_RD_SC_TOF(base)  ((FTM_SC_REG(base) & FTM_SC_TOF_MASK) >> FTM_SC_TOF_SHIFT)
+#define FTM_BRD_SC_TOF(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOF_SHIFT))
+
+/*! @brief Set the TOF field to a new value. */
+#define FTM_WR_SC_TOF(base, value) (FTM_RMW_SC(base, FTM_SC_TOF_MASK, FTM_SC_TOF(value)))
+#define FTM_BWR_SC_TOF(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CNT - Counter
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CNT - Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CNT register contains the FTM counter value. Reset clears the CNT
+ * register. Writing any value to COUNT updates the counter with its initial value,
+ * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
+ * may read.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CNT register
+ */
+/*@{*/
+#define FTM_RD_CNT(base)         (FTM_CNT_REG(base))
+#define FTM_WR_CNT(base, value)  (FTM_CNT_REG(base) = (value))
+#define FTM_RMW_CNT(base, mask, value) (FTM_WR_CNT(base, (FTM_RD_CNT(base) & ~(mask)) | (value)))
+#define FTM_SET_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) |  (value)))
+#define FTM_CLR_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) & ~(value)))
+#define FTM_TOG_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CNT bitfields
+ */
+
+/*!
+ * @name Register FTM_CNT, field COUNT[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CNT_COUNT field. */
+#define FTM_RD_CNT_COUNT(base) ((FTM_CNT_REG(base) & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT)
+#define FTM_BRD_CNT_COUNT(base) (FTM_RD_CNT_COUNT(base))
+
+/*! @brief Set the COUNT field to a new value. */
+#define FTM_WR_CNT_COUNT(base, value) (FTM_RMW_CNT(base, FTM_CNT_COUNT_MASK, FTM_CNT_COUNT(value)))
+#define FTM_BWR_CNT_COUNT(base, value) (FTM_WR_CNT_COUNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_MOD - Modulo
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_MOD - Modulo (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Modulo register contains the modulo value for the FTM counter. After the
+ * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
+ * the next clock, and the next value of FTM counter depends on the selected
+ * counting method; see Counter. Writing to the MOD register latches the value into a
+ * buffer. The MOD register is updated with the value of its write buffer
+ * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
+ * mechanism may be manually reset by writing to the SC register whether BDM is
+ * active or not. Initialize the FTM counter, by writing to CNT, before writing
+ * to the MOD register to avoid confusion about when the first counter overflow
+ * will occur.
+ */
+/*!
+ * @name Constants and macros for entire FTM_MOD register
+ */
+/*@{*/
+#define FTM_RD_MOD(base)         (FTM_MOD_REG(base))
+#define FTM_WR_MOD(base, value)  (FTM_MOD_REG(base) = (value))
+#define FTM_RMW_MOD(base, mask, value) (FTM_WR_MOD(base, (FTM_RD_MOD(base) & ~(mask)) | (value)))
+#define FTM_SET_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) |  (value)))
+#define FTM_CLR_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) & ~(value)))
+#define FTM_TOG_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_MOD bitfields
+ */
+
+/*!
+ * @name Register FTM_MOD, field MOD[15:0] (RW)
+ *
+ * Modulo Value
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MOD_MOD field. */
+#define FTM_RD_MOD_MOD(base) ((FTM_MOD_REG(base) & FTM_MOD_MOD_MASK) >> FTM_MOD_MOD_SHIFT)
+#define FTM_BRD_MOD_MOD(base) (FTM_RD_MOD_MOD(base))
+
+/*! @brief Set the MOD field to a new value. */
+#define FTM_WR_MOD_MOD(base, value) (FTM_RMW_MOD(base, FTM_MOD_MOD_MASK, FTM_MOD_MOD(value)))
+#define FTM_BWR_MOD_MOD(base, value) (FTM_WR_MOD_MOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CnSC - Channel (n) Status And Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CnSC - Channel (n) Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CnSC contains the channel-interrupt-status flag and control bits used to
+ * configure the interrupt enable, channel configuration, and pin function. Mode,
+ * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
+ * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
+ * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
+ * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
+ * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
+ * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
+ * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
+ * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
+ * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
+ * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
+ * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
+ * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
+ * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
+ * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
+ * Enabled Rising and falling edges
+ */
+/*!
+ * @name Constants and macros for entire FTM_CnSC register
+ */
+/*@{*/
+#define FTM_RD_CnSC(base, index) (FTM_CnSC_REG(base, index))
+#define FTM_WR_CnSC(base, index, value) (FTM_CnSC_REG(base, index) = (value))
+#define FTM_RMW_CnSC(base, index, mask, value) (FTM_WR_CnSC(base, index, (FTM_RD_CnSC(base, index) & ~(mask)) | (value)))
+#define FTM_SET_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) |  (value)))
+#define FTM_CLR_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) & ~(value)))
+#define FTM_TOG_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CnSC bitfields
+ */
+
+/*!
+ * @name Register FTM_CnSC, field DMA[0] (RW)
+ *
+ * Enables DMA transfers for the channel.
+ *
+ * Values:
+ * - 0b0 - Disable DMA transfers.
+ * - 0b1 - Enable DMA transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_DMA field. */
+#define FTM_RD_CnSC_DMA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_DMA_MASK) >> FTM_CnSC_DMA_SHIFT)
+#define FTM_BRD_CnSC_DMA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define FTM_WR_CnSC_DMA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_DMA_MASK, FTM_CnSC_DMA(value)))
+#define FTM_BWR_CnSC_DMA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_DMA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field ELSA[2] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_ELSA field. */
+#define FTM_RD_CnSC_ELSA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_ELSA_MASK) >> FTM_CnSC_ELSA_SHIFT)
+#define FTM_BRD_CnSC_ELSA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSA_SHIFT))
+
+/*! @brief Set the ELSA field to a new value. */
+#define FTM_WR_CnSC_ELSA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_ELSA_MASK, FTM_CnSC_ELSA(value)))
+#define FTM_BWR_CnSC_ELSA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field ELSB[3] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_ELSB field. */
+#define FTM_RD_CnSC_ELSB(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_ELSB_MASK) >> FTM_CnSC_ELSB_SHIFT)
+#define FTM_BRD_CnSC_ELSB(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSB_SHIFT))
+
+/*! @brief Set the ELSB field to a new value. */
+#define FTM_WR_CnSC_ELSB(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_ELSB_MASK, FTM_CnSC_ELSB(value)))
+#define FTM_BWR_CnSC_ELSB(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field MSA[4] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_MSA field. */
+#define FTM_RD_CnSC_MSA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_MSA_MASK) >> FTM_CnSC_MSA_SHIFT)
+#define FTM_BRD_CnSC_MSA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSA_SHIFT))
+
+/*! @brief Set the MSA field to a new value. */
+#define FTM_WR_CnSC_MSA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_MSA_MASK, FTM_CnSC_MSA(value)))
+#define FTM_BWR_CnSC_MSA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field MSB[5] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_MSB field. */
+#define FTM_RD_CnSC_MSB(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_MSB_MASK) >> FTM_CnSC_MSB_SHIFT)
+#define FTM_BRD_CnSC_MSB(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSB_SHIFT))
+
+/*! @brief Set the MSB field to a new value. */
+#define FTM_WR_CnSC_MSB(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_MSB_MASK, FTM_CnSC_MSB(value)))
+#define FTM_BWR_CnSC_MSB(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field CHIE[6] (RW)
+ *
+ * Enables channel interrupts.
+ *
+ * Values:
+ * - 0b0 - Disable channel interrupts. Use software polling.
+ * - 0b1 - Enable channel interrupts.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_CHIE field. */
+#define FTM_RD_CnSC_CHIE(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_CHIE_MASK) >> FTM_CnSC_CHIE_SHIFT)
+#define FTM_BRD_CnSC_CHIE(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHIE_SHIFT))
+
+/*! @brief Set the CHIE field to a new value. */
+#define FTM_WR_CnSC_CHIE(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_CHIE_MASK, FTM_CnSC_CHIE(value)))
+#define FTM_BWR_CnSC_CHIE(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field CHF[7] (ROWZ)
+ *
+ * Set by hardware when an event occurs on the channel. CHF is cleared by
+ * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
+ * Writing a 1 to CHF has no effect. If another event occurs between the read and
+ * write operations, the write operation has no effect; therefore, CHF remains set
+ * indicating an event has occurred. In this case a CHF interrupt request is not
+ * lost due to the clearing sequence for a previous CHF.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_CHF field. */
+#define FTM_RD_CnSC_CHF(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_CHF_MASK) >> FTM_CnSC_CHF_SHIFT)
+#define FTM_BRD_CnSC_CHF(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHF_SHIFT))
+
+/*! @brief Set the CHF field to a new value. */
+#define FTM_WR_CnSC_CHF(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_CHF_MASK, FTM_CnSC_CHF(value)))
+#define FTM_BWR_CnSC_CHF(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CnV - Channel (n) Value
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CnV - Channel (n) Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the captured FTM counter value for the input modes or
+ * the match value for the output modes. In Input Capture, Capture Test, and
+ * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
+ * writing to a CnV register latches the value into a buffer. A CnV register is
+ * updated with the value of its write buffer according to Registers updated from
+ * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
+ * reset by writing to the CnSC register whether BDM mode is active or not.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CnV register
+ */
+/*@{*/
+#define FTM_RD_CnV(base, index)  (FTM_CnV_REG(base, index))
+#define FTM_WR_CnV(base, index, value) (FTM_CnV_REG(base, index) = (value))
+#define FTM_RMW_CnV(base, index, mask, value) (FTM_WR_CnV(base, index, (FTM_RD_CnV(base, index) & ~(mask)) | (value)))
+#define FTM_SET_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) |  (value)))
+#define FTM_CLR_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) & ~(value)))
+#define FTM_TOG_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CnV bitfields
+ */
+
+/*!
+ * @name Register FTM_CnV, field VAL[15:0] (RW)
+ *
+ * Captured FTM counter value of the input modes or the match value for the
+ * output modes
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnV_VAL field. */
+#define FTM_RD_CnV_VAL(base, index) ((FTM_CnV_REG(base, index) & FTM_CnV_VAL_MASK) >> FTM_CnV_VAL_SHIFT)
+#define FTM_BRD_CnV_VAL(base, index) (FTM_RD_CnV_VAL(base, index))
+
+/*! @brief Set the VAL field to a new value. */
+#define FTM_WR_CnV_VAL(base, index, value) (FTM_RMW_CnV(base, index, FTM_CnV_VAL_MASK, FTM_CnV_VAL(value)))
+#define FTM_BWR_CnV_VAL(base, index, value) (FTM_WR_CnV_VAL(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CNTIN - Counter Initial Value
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CNTIN - Counter Initial Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Counter Initial Value register contains the initial value for the FTM
+ * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
+ * register is updated with the value of its write buffer according to Registers
+ * updated from write buffers. When the FTM clock is initially selected, by
+ * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
+ * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
+ * write the new value to the the CNTIN register and then initialize the FTM
+ * counter by writing any value to the CNT register.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CNTIN register
+ */
+/*@{*/
+#define FTM_RD_CNTIN(base)       (FTM_CNTIN_REG(base))
+#define FTM_WR_CNTIN(base, value) (FTM_CNTIN_REG(base) = (value))
+#define FTM_RMW_CNTIN(base, mask, value) (FTM_WR_CNTIN(base, (FTM_RD_CNTIN(base) & ~(mask)) | (value)))
+#define FTM_SET_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) |  (value)))
+#define FTM_CLR_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) & ~(value)))
+#define FTM_TOG_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CNTIN bitfields
+ */
+
+/*!
+ * @name Register FTM_CNTIN, field INIT[15:0] (RW)
+ *
+ * Initial Value Of The FTM Counter
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CNTIN_INIT field. */
+#define FTM_RD_CNTIN_INIT(base) ((FTM_CNTIN_REG(base) & FTM_CNTIN_INIT_MASK) >> FTM_CNTIN_INIT_SHIFT)
+#define FTM_BRD_CNTIN_INIT(base) (FTM_RD_CNTIN_INIT(base))
+
+/*! @brief Set the INIT field to a new value. */
+#define FTM_WR_CNTIN_INIT(base, value) (FTM_RMW_CNTIN(base, FTM_CNTIN_INIT_MASK, FTM_CNTIN_INIT(value)))
+#define FTM_BWR_CNTIN_INIT(base, value) (FTM_WR_CNTIN_INIT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_STATUS - Capture And Compare Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_STATUS - Capture And Compare Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
+ * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
+ * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
+ * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
+ * STATUS. Hardware sets the individual channel flags when an event occurs on the
+ * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
+ * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
+ * occurs between the read and write operations, the write operation has no effect;
+ * therefore, CHnF remains set indicating an event has occurred. In this case, a
+ * CHnF interrupt request is not lost due to the clearing sequence for a previous
+ * CHnF. The STATUS register should be used only in Combine mode.
+ */
+/*!
+ * @name Constants and macros for entire FTM_STATUS register
+ */
+/*@{*/
+#define FTM_RD_STATUS(base)      (FTM_STATUS_REG(base))
+#define FTM_WR_STATUS(base, value) (FTM_STATUS_REG(base) = (value))
+#define FTM_RMW_STATUS(base, mask, value) (FTM_WR_STATUS(base, (FTM_RD_STATUS(base) & ~(mask)) | (value)))
+#define FTM_SET_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) |  (value)))
+#define FTM_CLR_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) & ~(value)))
+#define FTM_TOG_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_STATUS bitfields
+ */
+
+/*!
+ * @name Register FTM_STATUS, field CH0F[0] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH0F field. */
+#define FTM_RD_STATUS_CH0F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH0F_MASK) >> FTM_STATUS_CH0F_SHIFT)
+#define FTM_BRD_STATUS_CH0F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH0F_SHIFT))
+
+/*! @brief Set the CH0F field to a new value. */
+#define FTM_WR_STATUS_CH0F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH0F(value)))
+#define FTM_BWR_STATUS_CH0F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH0F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH1F[1] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH1F field. */
+#define FTM_RD_STATUS_CH1F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH1F_MASK) >> FTM_STATUS_CH1F_SHIFT)
+#define FTM_BRD_STATUS_CH1F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH1F_SHIFT))
+
+/*! @brief Set the CH1F field to a new value. */
+#define FTM_WR_STATUS_CH1F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH1F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH1F(value)))
+#define FTM_BWR_STATUS_CH1F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH1F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH2F[2] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH2F field. */
+#define FTM_RD_STATUS_CH2F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH2F_MASK) >> FTM_STATUS_CH2F_SHIFT)
+#define FTM_BRD_STATUS_CH2F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH2F_SHIFT))
+
+/*! @brief Set the CH2F field to a new value. */
+#define FTM_WR_STATUS_CH2F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH2F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH2F(value)))
+#define FTM_BWR_STATUS_CH2F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH2F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH3F[3] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH3F field. */
+#define FTM_RD_STATUS_CH3F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH3F_MASK) >> FTM_STATUS_CH3F_SHIFT)
+#define FTM_BRD_STATUS_CH3F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH3F_SHIFT))
+
+/*! @brief Set the CH3F field to a new value. */
+#define FTM_WR_STATUS_CH3F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH3F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH3F(value)))
+#define FTM_BWR_STATUS_CH3F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH3F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH4F[4] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH4F field. */
+#define FTM_RD_STATUS_CH4F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH4F_MASK) >> FTM_STATUS_CH4F_SHIFT)
+#define FTM_BRD_STATUS_CH4F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH4F_SHIFT))
+
+/*! @brief Set the CH4F field to a new value. */
+#define FTM_WR_STATUS_CH4F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH4F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH4F(value)))
+#define FTM_BWR_STATUS_CH4F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH4F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH5F[5] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH5F field. */
+#define FTM_RD_STATUS_CH5F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH5F_MASK) >> FTM_STATUS_CH5F_SHIFT)
+#define FTM_BRD_STATUS_CH5F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH5F_SHIFT))
+
+/*! @brief Set the CH5F field to a new value. */
+#define FTM_WR_STATUS_CH5F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH5F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH5F(value)))
+#define FTM_BWR_STATUS_CH5F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH5F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH6F[6] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH6F field. */
+#define FTM_RD_STATUS_CH6F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH6F_MASK) >> FTM_STATUS_CH6F_SHIFT)
+#define FTM_BRD_STATUS_CH6F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH6F_SHIFT))
+
+/*! @brief Set the CH6F field to a new value. */
+#define FTM_WR_STATUS_CH6F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH6F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH6F(value)))
+#define FTM_BWR_STATUS_CH6F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH6F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH7F[7] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH7F field. */
+#define FTM_RD_STATUS_CH7F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH7F_MASK) >> FTM_STATUS_CH7F_SHIFT)
+#define FTM_BRD_STATUS_CH7F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH7F_SHIFT))
+
+/*! @brief Set the CH7F field to a new value. */
+#define FTM_WR_STATUS_CH7F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH7F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK), FTM_STATUS_CH7F(value)))
+#define FTM_BWR_STATUS_CH7F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH7F_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_MODE - Features Mode Selection
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_MODE - Features Mode Selection (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * This register contains the global enable bit for FTM-specific features and
+ * the control bits used to configure: Fault control mode and interrupt Capture
+ * Test mode PWM synchronization Write protection Channel output initialization
+ * These controls relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire FTM_MODE register
+ */
+/*@{*/
+#define FTM_RD_MODE(base)        (FTM_MODE_REG(base))
+#define FTM_WR_MODE(base, value) (FTM_MODE_REG(base) = (value))
+#define FTM_RMW_MODE(base, mask, value) (FTM_WR_MODE(base, (FTM_RD_MODE(base) & ~(mask)) | (value)))
+#define FTM_SET_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) |  (value)))
+#define FTM_CLR_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) & ~(value)))
+#define FTM_TOG_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_MODE bitfields
+ */
+
+/*!
+ * @name Register FTM_MODE, field FTMEN[0] (RW)
+ *
+ * This field is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Only the TPM-compatible registers (first set of registers) can be
+ *     used without any restriction. Do not use the FTM-specific registers.
+ * - 0b1 - All registers including the FTM-specific registers (second set of
+ *     registers) are available for use with no restrictions.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FTMEN field. */
+#define FTM_RD_MODE_FTMEN(base) ((FTM_MODE_REG(base) & FTM_MODE_FTMEN_MASK) >> FTM_MODE_FTMEN_SHIFT)
+#define FTM_BRD_MODE_FTMEN(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FTMEN_SHIFT))
+
+/*! @brief Set the FTMEN field to a new value. */
+#define FTM_WR_MODE_FTMEN(base, value) (FTM_RMW_MODE(base, FTM_MODE_FTMEN_MASK, FTM_MODE_FTMEN(value)))
+#define FTM_BWR_MODE_FTMEN(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FTMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field INIT[1] (RW)
+ *
+ * When a 1 is written to INIT bit the channels output is initialized according
+ * to the state of their corresponding bit in the OUTINIT register. Writing a 0
+ * to INIT bit has no effect. The INIT bit is always read as 0.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_INIT field. */
+#define FTM_RD_MODE_INIT(base) ((FTM_MODE_REG(base) & FTM_MODE_INIT_MASK) >> FTM_MODE_INIT_SHIFT)
+#define FTM_BRD_MODE_INIT(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_INIT_SHIFT))
+
+/*! @brief Set the INIT field to a new value. */
+#define FTM_WR_MODE_INIT(base, value) (FTM_RMW_MODE(base, FTM_MODE_INIT_MASK, FTM_MODE_INIT(value)))
+#define FTM_BWR_MODE_INIT(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_INIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field WPDIS[2] (RW)
+ *
+ * When write protection is enabled (WPDIS = 0), write protected bits cannot be
+ * written. When write protection is disabled (WPDIS = 1), write protected bits
+ * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
+ * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
+ * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
+ *
+ * Values:
+ * - 0b0 - Write protection is enabled.
+ * - 0b1 - Write protection is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_WPDIS field. */
+#define FTM_RD_MODE_WPDIS(base) ((FTM_MODE_REG(base) & FTM_MODE_WPDIS_MASK) >> FTM_MODE_WPDIS_SHIFT)
+#define FTM_BRD_MODE_WPDIS(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_WPDIS_SHIFT))
+
+/*! @brief Set the WPDIS field to a new value. */
+#define FTM_WR_MODE_WPDIS(base, value) (FTM_RMW_MODE(base, FTM_MODE_WPDIS_MASK, FTM_MODE_WPDIS(value)))
+#define FTM_BWR_MODE_WPDIS(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_WPDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field PWMSYNC[3] (RW)
+ *
+ * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
+ * synchronization. See PWM synchronization. The PWMSYNC bit configures the
+ * synchronization when SYNCMODE is 0.
+ *
+ * Values:
+ * - 0b0 - No restrictions. Software and hardware triggers can be used by MOD,
+ *     CnV, OUTMASK, and FTM counter synchronization.
+ * - 0b1 - Software trigger can only be used by MOD and CnV synchronization, and
+ *     hardware triggers can only be used by OUTMASK and FTM counter
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_PWMSYNC field. */
+#define FTM_RD_MODE_PWMSYNC(base) ((FTM_MODE_REG(base) & FTM_MODE_PWMSYNC_MASK) >> FTM_MODE_PWMSYNC_SHIFT)
+#define FTM_BRD_MODE_PWMSYNC(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_PWMSYNC_SHIFT))
+
+/*! @brief Set the PWMSYNC field to a new value. */
+#define FTM_WR_MODE_PWMSYNC(base, value) (FTM_RMW_MODE(base, FTM_MODE_PWMSYNC_MASK, FTM_MODE_PWMSYNC(value)))
+#define FTM_BWR_MODE_PWMSYNC(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_PWMSYNC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field CAPTEST[4] (RW)
+ *
+ * Enables the capture test mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Capture test mode is disabled.
+ * - 0b1 - Capture test mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_CAPTEST field. */
+#define FTM_RD_MODE_CAPTEST(base) ((FTM_MODE_REG(base) & FTM_MODE_CAPTEST_MASK) >> FTM_MODE_CAPTEST_SHIFT)
+#define FTM_BRD_MODE_CAPTEST(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_CAPTEST_SHIFT))
+
+/*! @brief Set the CAPTEST field to a new value. */
+#define FTM_WR_MODE_CAPTEST(base, value) (FTM_RMW_MODE(base, FTM_MODE_CAPTEST_MASK, FTM_MODE_CAPTEST(value)))
+#define FTM_BWR_MODE_CAPTEST(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_CAPTEST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field FAULTM[6:5] (RW)
+ *
+ * Defines the FTM fault control mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b00 - Fault control is disabled for all channels.
+ * - 0b01 - Fault control is enabled for even channels only (channels 0, 2, 4,
+ *     and 6), and the selected mode is the manual fault clearing.
+ * - 0b10 - Fault control is enabled for all channels, and the selected mode is
+ *     the manual fault clearing.
+ * - 0b11 - Fault control is enabled for all channels, and the selected mode is
+ *     the automatic fault clearing.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FAULTM field. */
+#define FTM_RD_MODE_FAULTM(base) ((FTM_MODE_REG(base) & FTM_MODE_FAULTM_MASK) >> FTM_MODE_FAULTM_SHIFT)
+#define FTM_BRD_MODE_FAULTM(base) (FTM_RD_MODE_FAULTM(base))
+
+/*! @brief Set the FAULTM field to a new value. */
+#define FTM_WR_MODE_FAULTM(base, value) (FTM_RMW_MODE(base, FTM_MODE_FAULTM_MASK, FTM_MODE_FAULTM(value)))
+#define FTM_BWR_MODE_FAULTM(base, value) (FTM_WR_MODE_FAULTM(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field FAULTIE[7] (RW)
+ *
+ * Enables the generation of an interrupt when a fault is detected by FTM and
+ * the FTM fault control is enabled.
+ *
+ * Values:
+ * - 0b0 - Fault control interrupt is disabled.
+ * - 0b1 - Fault control interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FAULTIE field. */
+#define FTM_RD_MODE_FAULTIE(base) ((FTM_MODE_REG(base) & FTM_MODE_FAULTIE_MASK) >> FTM_MODE_FAULTIE_SHIFT)
+#define FTM_BRD_MODE_FAULTIE(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FAULTIE_SHIFT))
+
+/*! @brief Set the FAULTIE field to a new value. */
+#define FTM_WR_MODE_FAULTIE(base, value) (FTM_RMW_MODE(base, FTM_MODE_FAULTIE_MASK, FTM_MODE_FAULTIE(value)))
+#define FTM_BWR_MODE_FAULTIE(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FAULTIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SYNC - Synchronization
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SYNC - Synchronization (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the PWM synchronization. A synchronization event can
+ * perform the synchronized update of MOD, CV, and OUTMASK registers with the
+ * value of their write buffer and the FTM counter initialization. The software
+ * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
+ * potential conflict if used together when SYNCMODE = 0. Use only hardware or
+ * software triggers but not both at the same time, otherwise unpredictable behavior
+ * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
+ * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
+ * all enabled channels simultaneously. The use of the loading point selection
+ * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
+ * bits, is likely to result in unpredictable behavior. The synchronization
+ * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
+ * register) bits. See PWM synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SYNC register
+ */
+/*@{*/
+#define FTM_RD_SYNC(base)        (FTM_SYNC_REG(base))
+#define FTM_WR_SYNC(base, value) (FTM_SYNC_REG(base) = (value))
+#define FTM_RMW_SYNC(base, mask, value) (FTM_WR_SYNC(base, (FTM_RD_SYNC(base) & ~(mask)) | (value)))
+#define FTM_SET_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) |  (value)))
+#define FTM_CLR_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) & ~(value)))
+#define FTM_TOG_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SYNC bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNC, field CNTMIN[0] (RW)
+ *
+ * Selects the minimum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMIN is one, the selected loading point is when the
+ * FTM counter reaches its minimum value (CNTIN register).
+ *
+ * Values:
+ * - 0b0 - The minimum loading point is disabled.
+ * - 0b1 - The minimum loading point is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_CNTMIN field. */
+#define FTM_RD_SYNC_CNTMIN(base) ((FTM_SYNC_REG(base) & FTM_SYNC_CNTMIN_MASK) >> FTM_SYNC_CNTMIN_SHIFT)
+#define FTM_BRD_SYNC_CNTMIN(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMIN_SHIFT))
+
+/*! @brief Set the CNTMIN field to a new value. */
+#define FTM_WR_SYNC_CNTMIN(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_CNTMIN_MASK, FTM_SYNC_CNTMIN(value)))
+#define FTM_BWR_SYNC_CNTMIN(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMIN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field CNTMAX[1] (RW)
+ *
+ * Selects the maximum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
+ * counter reaches its maximum value (MOD register).
+ *
+ * Values:
+ * - 0b0 - The maximum loading point is disabled.
+ * - 0b1 - The maximum loading point is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_CNTMAX field. */
+#define FTM_RD_SYNC_CNTMAX(base) ((FTM_SYNC_REG(base) & FTM_SYNC_CNTMAX_MASK) >> FTM_SYNC_CNTMAX_SHIFT)
+#define FTM_BRD_SYNC_CNTMAX(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMAX_SHIFT))
+
+/*! @brief Set the CNTMAX field to a new value. */
+#define FTM_WR_SYNC_CNTMAX(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_CNTMAX_MASK, FTM_SYNC_CNTMAX(value)))
+#define FTM_BWR_SYNC_CNTMAX(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMAX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field REINIT[2] (RW)
+ *
+ * Determines if the FTM counter is reinitialized when the selected trigger for
+ * the synchronization is detected. The REINIT bit configures the synchronization
+ * when SYNCMODE is zero.
+ *
+ * Values:
+ * - 0b0 - FTM counter continues to count normally.
+ * - 0b1 - FTM counter is updated with its initial value when the selected
+ *     trigger is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_REINIT field. */
+#define FTM_RD_SYNC_REINIT(base) ((FTM_SYNC_REG(base) & FTM_SYNC_REINIT_MASK) >> FTM_SYNC_REINIT_SHIFT)
+#define FTM_BRD_SYNC_REINIT(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_REINIT_SHIFT))
+
+/*! @brief Set the REINIT field to a new value. */
+#define FTM_WR_SYNC_REINIT(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_REINIT_MASK, FTM_SYNC_REINIT(value)))
+#define FTM_BWR_SYNC_REINIT(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_REINIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
+ *
+ * Selects when the OUTMASK register is updated with the value of its buffer.
+ *
+ * Values:
+ * - 0b0 - OUTMASK register is updated with the value of its buffer in all
+ *     rising edges of the system clock.
+ * - 0b1 - OUTMASK register is updated with the value of its buffer only by the
+ *     PWM synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */
+#define FTM_RD_SYNC_SYNCHOM(base) ((FTM_SYNC_REG(base) & FTM_SYNC_SYNCHOM_MASK) >> FTM_SYNC_SYNCHOM_SHIFT)
+#define FTM_BRD_SYNC_SYNCHOM(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SYNCHOM_SHIFT))
+
+/*! @brief Set the SYNCHOM field to a new value. */
+#define FTM_WR_SYNC_SYNCHOM(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_SYNCHOM_MASK, FTM_SYNC_SYNCHOM(value)))
+#define FTM_BWR_SYNC_SYNCHOM(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SYNCHOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG0[4] (RW)
+ *
+ * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
+ * occurs when a rising edge is detected at the trigger 0 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG0 field. */
+#define FTM_RD_SYNC_TRIG0(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG0_MASK) >> FTM_SYNC_TRIG0_SHIFT)
+#define FTM_BRD_SYNC_TRIG0(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG0_SHIFT))
+
+/*! @brief Set the TRIG0 field to a new value. */
+#define FTM_WR_SYNC_TRIG0(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG0_MASK, FTM_SYNC_TRIG0(value)))
+#define FTM_BWR_SYNC_TRIG0(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG1[5] (RW)
+ *
+ * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
+ * happens when a rising edge is detected at the trigger 1 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG1 field. */
+#define FTM_RD_SYNC_TRIG1(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG1_MASK) >> FTM_SYNC_TRIG1_SHIFT)
+#define FTM_BRD_SYNC_TRIG1(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG1_SHIFT))
+
+/*! @brief Set the TRIG1 field to a new value. */
+#define FTM_WR_SYNC_TRIG1(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG1_MASK, FTM_SYNC_TRIG1(value)))
+#define FTM_BWR_SYNC_TRIG1(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG2[6] (RW)
+ *
+ * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
+ * happens when a rising edge is detected at the trigger 2 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG2 field. */
+#define FTM_RD_SYNC_TRIG2(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG2_MASK) >> FTM_SYNC_TRIG2_SHIFT)
+#define FTM_BRD_SYNC_TRIG2(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG2_SHIFT))
+
+/*! @brief Set the TRIG2 field to a new value. */
+#define FTM_WR_SYNC_TRIG2(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG2_MASK, FTM_SYNC_TRIG2(value)))
+#define FTM_BWR_SYNC_TRIG2(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field SWSYNC[7] (RW)
+ *
+ * Selects the software trigger as the PWM synchronization trigger. The software
+ * trigger happens when a 1 is written to SWSYNC bit.
+ *
+ * Values:
+ * - 0b0 - Software trigger is not selected.
+ * - 0b1 - Software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_SWSYNC field. */
+#define FTM_RD_SYNC_SWSYNC(base) ((FTM_SYNC_REG(base) & FTM_SYNC_SWSYNC_MASK) >> FTM_SYNC_SWSYNC_SHIFT)
+#define FTM_BRD_SYNC_SWSYNC(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SWSYNC_SHIFT))
+
+/*! @brief Set the SWSYNC field to a new value. */
+#define FTM_WR_SYNC_SWSYNC(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_SWSYNC_MASK, FTM_SYNC_SWSYNC(value)))
+#define FTM_BWR_SYNC_SWSYNC(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SWSYNC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_OUTINIT - Initial State For Channels Output
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_OUTINIT - Initial State For Channels Output (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire FTM_OUTINIT register
+ */
+/*@{*/
+#define FTM_RD_OUTINIT(base)     (FTM_OUTINIT_REG(base))
+#define FTM_WR_OUTINIT(base, value) (FTM_OUTINIT_REG(base) = (value))
+#define FTM_RMW_OUTINIT(base, mask, value) (FTM_WR_OUTINIT(base, (FTM_RD_OUTINIT(base) & ~(mask)) | (value)))
+#define FTM_SET_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) |  (value)))
+#define FTM_CLR_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) & ~(value)))
+#define FTM_TOG_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_OUTINIT bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */
+#define FTM_RD_OUTINIT_CH0OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH0OI_MASK) >> FTM_OUTINIT_CH0OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH0OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH0OI_SHIFT))
+
+/*! @brief Set the CH0OI field to a new value. */
+#define FTM_WR_OUTINIT_CH0OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH0OI_MASK, FTM_OUTINIT_CH0OI(value)))
+#define FTM_BWR_OUTINIT_CH0OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH0OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */
+#define FTM_RD_OUTINIT_CH1OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH1OI_MASK) >> FTM_OUTINIT_CH1OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH1OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH1OI_SHIFT))
+
+/*! @brief Set the CH1OI field to a new value. */
+#define FTM_WR_OUTINIT_CH1OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH1OI_MASK, FTM_OUTINIT_CH1OI(value)))
+#define FTM_BWR_OUTINIT_CH1OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH1OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */
+#define FTM_RD_OUTINIT_CH2OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH2OI_MASK) >> FTM_OUTINIT_CH2OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH2OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH2OI_SHIFT))
+
+/*! @brief Set the CH2OI field to a new value. */
+#define FTM_WR_OUTINIT_CH2OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH2OI_MASK, FTM_OUTINIT_CH2OI(value)))
+#define FTM_BWR_OUTINIT_CH2OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH2OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */
+#define FTM_RD_OUTINIT_CH3OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH3OI_MASK) >> FTM_OUTINIT_CH3OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH3OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH3OI_SHIFT))
+
+/*! @brief Set the CH3OI field to a new value. */
+#define FTM_WR_OUTINIT_CH3OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH3OI_MASK, FTM_OUTINIT_CH3OI(value)))
+#define FTM_BWR_OUTINIT_CH3OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH3OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */
+#define FTM_RD_OUTINIT_CH4OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH4OI_MASK) >> FTM_OUTINIT_CH4OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH4OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH4OI_SHIFT))
+
+/*! @brief Set the CH4OI field to a new value. */
+#define FTM_WR_OUTINIT_CH4OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH4OI_MASK, FTM_OUTINIT_CH4OI(value)))
+#define FTM_BWR_OUTINIT_CH4OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH4OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */
+#define FTM_RD_OUTINIT_CH5OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH5OI_MASK) >> FTM_OUTINIT_CH5OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH5OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH5OI_SHIFT))
+
+/*! @brief Set the CH5OI field to a new value. */
+#define FTM_WR_OUTINIT_CH5OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH5OI_MASK, FTM_OUTINIT_CH5OI(value)))
+#define FTM_BWR_OUTINIT_CH5OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH5OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */
+#define FTM_RD_OUTINIT_CH6OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH6OI_MASK) >> FTM_OUTINIT_CH6OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH6OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH6OI_SHIFT))
+
+/*! @brief Set the CH6OI field to a new value. */
+#define FTM_WR_OUTINIT_CH6OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH6OI_MASK, FTM_OUTINIT_CH6OI(value)))
+#define FTM_BWR_OUTINIT_CH6OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH6OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */
+#define FTM_RD_OUTINIT_CH7OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH7OI_MASK) >> FTM_OUTINIT_CH7OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH7OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH7OI_SHIFT))
+
+/*! @brief Set the CH7OI field to a new value. */
+#define FTM_WR_OUTINIT_CH7OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH7OI_MASK, FTM_OUTINIT_CH7OI(value)))
+#define FTM_BWR_OUTINIT_CH7OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH7OI_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_OUTMASK - Output Mask
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_OUTMASK - Output Mask (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides a mask for each FTM channel. The mask of a channel
+ * determines if its output responds, that is, it is masked or not, when a match
+ * occurs. This feature is used for BLDC control where the PWM signal is presented
+ * to an electric motor at specific times to provide electronic commutation. Any
+ * write to the OUTMASK register, stores the value in its write buffer. The
+ * register is updated with the value of its write buffer according to PWM
+ * synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_OUTMASK register
+ */
+/*@{*/
+#define FTM_RD_OUTMASK(base)     (FTM_OUTMASK_REG(base))
+#define FTM_WR_OUTMASK(base, value) (FTM_OUTMASK_REG(base) = (value))
+#define FTM_RMW_OUTMASK(base, mask, value) (FTM_WR_OUTMASK(base, (FTM_RD_OUTMASK(base) & ~(mask)) | (value)))
+#define FTM_SET_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) |  (value)))
+#define FTM_CLR_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) & ~(value)))
+#define FTM_TOG_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_OUTMASK bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */
+#define FTM_RD_OUTMASK_CH0OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH0OM_MASK) >> FTM_OUTMASK_CH0OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH0OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH0OM_SHIFT))
+
+/*! @brief Set the CH0OM field to a new value. */
+#define FTM_WR_OUTMASK_CH0OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH0OM_MASK, FTM_OUTMASK_CH0OM(value)))
+#define FTM_BWR_OUTMASK_CH0OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH0OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */
+#define FTM_RD_OUTMASK_CH1OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH1OM_MASK) >> FTM_OUTMASK_CH1OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH1OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH1OM_SHIFT))
+
+/*! @brief Set the CH1OM field to a new value. */
+#define FTM_WR_OUTMASK_CH1OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH1OM_MASK, FTM_OUTMASK_CH1OM(value)))
+#define FTM_BWR_OUTMASK_CH1OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH1OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */
+#define FTM_RD_OUTMASK_CH2OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH2OM_MASK) >> FTM_OUTMASK_CH2OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH2OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH2OM_SHIFT))
+
+/*! @brief Set the CH2OM field to a new value. */
+#define FTM_WR_OUTMASK_CH2OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH2OM_MASK, FTM_OUTMASK_CH2OM(value)))
+#define FTM_BWR_OUTMASK_CH2OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH2OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */
+#define FTM_RD_OUTMASK_CH3OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH3OM_MASK) >> FTM_OUTMASK_CH3OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH3OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH3OM_SHIFT))
+
+/*! @brief Set the CH3OM field to a new value. */
+#define FTM_WR_OUTMASK_CH3OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH3OM_MASK, FTM_OUTMASK_CH3OM(value)))
+#define FTM_BWR_OUTMASK_CH3OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH3OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */
+#define FTM_RD_OUTMASK_CH4OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH4OM_MASK) >> FTM_OUTMASK_CH4OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH4OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH4OM_SHIFT))
+
+/*! @brief Set the CH4OM field to a new value. */
+#define FTM_WR_OUTMASK_CH4OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH4OM_MASK, FTM_OUTMASK_CH4OM(value)))
+#define FTM_BWR_OUTMASK_CH4OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH4OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */
+#define FTM_RD_OUTMASK_CH5OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH5OM_MASK) >> FTM_OUTMASK_CH5OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH5OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH5OM_SHIFT))
+
+/*! @brief Set the CH5OM field to a new value. */
+#define FTM_WR_OUTMASK_CH5OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH5OM_MASK, FTM_OUTMASK_CH5OM(value)))
+#define FTM_BWR_OUTMASK_CH5OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH5OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */
+#define FTM_RD_OUTMASK_CH6OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH6OM_MASK) >> FTM_OUTMASK_CH6OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH6OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH6OM_SHIFT))
+
+/*! @brief Set the CH6OM field to a new value. */
+#define FTM_WR_OUTMASK_CH6OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH6OM_MASK, FTM_OUTMASK_CH6OM(value)))
+#define FTM_BWR_OUTMASK_CH6OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH6OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */
+#define FTM_RD_OUTMASK_CH7OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH7OM_MASK) >> FTM_OUTMASK_CH7OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH7OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH7OM_SHIFT))
+
+/*! @brief Set the CH7OM field to a new value. */
+#define FTM_WR_OUTMASK_CH7OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH7OM_MASK, FTM_OUTMASK_CH7OM(value)))
+#define FTM_BWR_OUTMASK_CH7OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH7OM_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_COMBINE - Function For Linked Channels
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_COMBINE - Function For Linked Channels (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the control bits used to configure the fault control,
+ * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
+ * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
+ * 4, and 6.
+ */
+/*!
+ * @name Constants and macros for entire FTM_COMBINE register
+ */
+/*@{*/
+#define FTM_RD_COMBINE(base)     (FTM_COMBINE_REG(base))
+#define FTM_WR_COMBINE(base, value) (FTM_COMBINE_REG(base) = (value))
+#define FTM_RMW_COMBINE(base, mask, value) (FTM_WR_COMBINE(base, (FTM_RD_COMBINE(base) & ~(mask)) | (value)))
+#define FTM_SET_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) |  (value)))
+#define FTM_CLR_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) & ~(value)))
+#define FTM_TOG_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_COMBINE bitfields
+ */
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */
+#define FTM_RD_COMBINE_COMBINE0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE0_MASK) >> FTM_COMBINE_COMBINE0_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE0_SHIFT))
+
+/*! @brief Set the COMBINE0 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE0_MASK, FTM_COMBINE_COMBINE0(value)))
+#define FTM_BWR_COMBINE_COMBINE0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP0[1] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP0 field. */
+#define FTM_RD_COMBINE_COMP0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP0_MASK) >> FTM_COMBINE_COMP0_SHIFT)
+#define FTM_BRD_COMBINE_COMP0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP0_SHIFT))
+
+/*! @brief Set the COMP0 field to a new value. */
+#define FTM_WR_COMBINE_COMP0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP0_MASK, FTM_COMBINE_COMP0(value)))
+#define FTM_BWR_COMBINE_COMP0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */
+#define FTM_RD_COMBINE_DECAPEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN0_MASK) >> FTM_COMBINE_DECAPEN0_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN0_SHIFT))
+
+/*! @brief Set the DECAPEN0 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN0_MASK, FTM_COMBINE_DECAPEN0(value)))
+#define FTM_BWR_COMBINE_DECAPEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP0[3] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */
+#define FTM_RD_COMBINE_DECAP0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP0_MASK) >> FTM_COMBINE_DECAP0_SHIFT)
+#define FTM_BRD_COMBINE_DECAP0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP0_SHIFT))
+
+/*! @brief Set the DECAP0 field to a new value. */
+#define FTM_WR_COMBINE_DECAP0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP0_MASK, FTM_COMBINE_DECAP0(value)))
+#define FTM_BWR_COMBINE_DECAP0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN0[4] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */
+#define FTM_RD_COMBINE_DTEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN0_MASK) >> FTM_COMBINE_DTEN0_SHIFT)
+#define FTM_BRD_COMBINE_DTEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN0_SHIFT))
+
+/*! @brief Set the DTEN0 field to a new value. */
+#define FTM_WR_COMBINE_DTEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN0_MASK, FTM_COMBINE_DTEN0(value)))
+#define FTM_BWR_COMBINE_DTEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */
+#define FTM_RD_COMBINE_SYNCEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN0_MASK) >> FTM_COMBINE_SYNCEN0_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN0_SHIFT))
+
+/*! @brief Set the SYNCEN0 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN0_MASK, FTM_COMBINE_SYNCEN0(value)))
+#define FTM_BWR_COMBINE_SYNCEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */
+#define FTM_RD_COMBINE_FAULTEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN0_MASK) >> FTM_COMBINE_FAULTEN0_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN0_SHIFT))
+
+/*! @brief Set the FAULTEN0 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN0_MASK, FTM_COMBINE_FAULTEN0(value)))
+#define FTM_BWR_COMBINE_FAULTEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */
+#define FTM_RD_COMBINE_COMBINE1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE1_MASK) >> FTM_COMBINE_COMBINE1_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE1_SHIFT))
+
+/*! @brief Set the COMBINE1 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE1_MASK, FTM_COMBINE_COMBINE1(value)))
+#define FTM_BWR_COMBINE_COMBINE1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP1[9] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP1 field. */
+#define FTM_RD_COMBINE_COMP1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP1_MASK) >> FTM_COMBINE_COMP1_SHIFT)
+#define FTM_BRD_COMBINE_COMP1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP1_SHIFT))
+
+/*! @brief Set the COMP1 field to a new value. */
+#define FTM_WR_COMBINE_COMP1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP1_MASK, FTM_COMBINE_COMP1(value)))
+#define FTM_BWR_COMBINE_COMP1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */
+#define FTM_RD_COMBINE_DECAPEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN1_MASK) >> FTM_COMBINE_DECAPEN1_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN1_SHIFT))
+
+/*! @brief Set the DECAPEN1 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN1_MASK, FTM_COMBINE_DECAPEN1(value)))
+#define FTM_BWR_COMBINE_DECAPEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP1[11] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */
+#define FTM_RD_COMBINE_DECAP1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP1_MASK) >> FTM_COMBINE_DECAP1_SHIFT)
+#define FTM_BRD_COMBINE_DECAP1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP1_SHIFT))
+
+/*! @brief Set the DECAP1 field to a new value. */
+#define FTM_WR_COMBINE_DECAP1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP1_MASK, FTM_COMBINE_DECAP1(value)))
+#define FTM_BWR_COMBINE_DECAP1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN1[12] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */
+#define FTM_RD_COMBINE_DTEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN1_MASK) >> FTM_COMBINE_DTEN1_SHIFT)
+#define FTM_BRD_COMBINE_DTEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN1_SHIFT))
+
+/*! @brief Set the DTEN1 field to a new value. */
+#define FTM_WR_COMBINE_DTEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN1_MASK, FTM_COMBINE_DTEN1(value)))
+#define FTM_BWR_COMBINE_DTEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */
+#define FTM_RD_COMBINE_SYNCEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN1_MASK) >> FTM_COMBINE_SYNCEN1_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN1_SHIFT))
+
+/*! @brief Set the SYNCEN1 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN1_MASK, FTM_COMBINE_SYNCEN1(value)))
+#define FTM_BWR_COMBINE_SYNCEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */
+#define FTM_RD_COMBINE_FAULTEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN1_MASK) >> FTM_COMBINE_FAULTEN1_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN1_SHIFT))
+
+/*! @brief Set the FAULTEN1 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN1_MASK, FTM_COMBINE_FAULTEN1(value)))
+#define FTM_BWR_COMBINE_FAULTEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */
+#define FTM_RD_COMBINE_COMBINE2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE2_MASK) >> FTM_COMBINE_COMBINE2_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE2_SHIFT))
+
+/*! @brief Set the COMBINE2 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE2_MASK, FTM_COMBINE_COMBINE2(value)))
+#define FTM_BWR_COMBINE_COMBINE2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP2[17] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP2 field. */
+#define FTM_RD_COMBINE_COMP2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP2_MASK) >> FTM_COMBINE_COMP2_SHIFT)
+#define FTM_BRD_COMBINE_COMP2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP2_SHIFT))
+
+/*! @brief Set the COMP2 field to a new value. */
+#define FTM_WR_COMBINE_COMP2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP2_MASK, FTM_COMBINE_COMP2(value)))
+#define FTM_BWR_COMBINE_COMP2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */
+#define FTM_RD_COMBINE_DECAPEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN2_MASK) >> FTM_COMBINE_DECAPEN2_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN2_SHIFT))
+
+/*! @brief Set the DECAPEN2 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN2_MASK, FTM_COMBINE_DECAPEN2(value)))
+#define FTM_BWR_COMBINE_DECAPEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP2[19] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */
+#define FTM_RD_COMBINE_DECAP2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP2_MASK) >> FTM_COMBINE_DECAP2_SHIFT)
+#define FTM_BRD_COMBINE_DECAP2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP2_SHIFT))
+
+/*! @brief Set the DECAP2 field to a new value. */
+#define FTM_WR_COMBINE_DECAP2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP2_MASK, FTM_COMBINE_DECAP2(value)))
+#define FTM_BWR_COMBINE_DECAP2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN2[20] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */
+#define FTM_RD_COMBINE_DTEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN2_MASK) >> FTM_COMBINE_DTEN2_SHIFT)
+#define FTM_BRD_COMBINE_DTEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN2_SHIFT))
+
+/*! @brief Set the DTEN2 field to a new value. */
+#define FTM_WR_COMBINE_DTEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN2_MASK, FTM_COMBINE_DTEN2(value)))
+#define FTM_BWR_COMBINE_DTEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */
+#define FTM_RD_COMBINE_SYNCEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN2_MASK) >> FTM_COMBINE_SYNCEN2_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN2_SHIFT))
+
+/*! @brief Set the SYNCEN2 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN2_MASK, FTM_COMBINE_SYNCEN2(value)))
+#define FTM_BWR_COMBINE_SYNCEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */
+#define FTM_RD_COMBINE_FAULTEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN2_MASK) >> FTM_COMBINE_FAULTEN2_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN2_SHIFT))
+
+/*! @brief Set the FAULTEN2 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN2_MASK, FTM_COMBINE_FAULTEN2(value)))
+#define FTM_BWR_COMBINE_FAULTEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */
+#define FTM_RD_COMBINE_COMBINE3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE3_MASK) >> FTM_COMBINE_COMBINE3_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE3_SHIFT))
+
+/*! @brief Set the COMBINE3 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE3_MASK, FTM_COMBINE_COMBINE3(value)))
+#define FTM_BWR_COMBINE_COMBINE3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP3[25] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP3 field. */
+#define FTM_RD_COMBINE_COMP3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP3_MASK) >> FTM_COMBINE_COMP3_SHIFT)
+#define FTM_BRD_COMBINE_COMP3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP3_SHIFT))
+
+/*! @brief Set the COMP3 field to a new value. */
+#define FTM_WR_COMBINE_COMP3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP3_MASK, FTM_COMBINE_COMP3(value)))
+#define FTM_BWR_COMBINE_COMP3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */
+#define FTM_RD_COMBINE_DECAPEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN3_MASK) >> FTM_COMBINE_DECAPEN3_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN3_SHIFT))
+
+/*! @brief Set the DECAPEN3 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN3_MASK, FTM_COMBINE_DECAPEN3(value)))
+#define FTM_BWR_COMBINE_DECAPEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP3[27] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */
+#define FTM_RD_COMBINE_DECAP3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP3_MASK) >> FTM_COMBINE_DECAP3_SHIFT)
+#define FTM_BRD_COMBINE_DECAP3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP3_SHIFT))
+
+/*! @brief Set the DECAP3 field to a new value. */
+#define FTM_WR_COMBINE_DECAP3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP3_MASK, FTM_COMBINE_DECAP3(value)))
+#define FTM_BWR_COMBINE_DECAP3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN3[28] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */
+#define FTM_RD_COMBINE_DTEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN3_MASK) >> FTM_COMBINE_DTEN3_SHIFT)
+#define FTM_BRD_COMBINE_DTEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN3_SHIFT))
+
+/*! @brief Set the DTEN3 field to a new value. */
+#define FTM_WR_COMBINE_DTEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN3_MASK, FTM_COMBINE_DTEN3(value)))
+#define FTM_BWR_COMBINE_DTEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */
+#define FTM_RD_COMBINE_SYNCEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN3_MASK) >> FTM_COMBINE_SYNCEN3_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN3_SHIFT))
+
+/*! @brief Set the SYNCEN3 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN3_MASK, FTM_COMBINE_SYNCEN3(value)))
+#define FTM_BWR_COMBINE_SYNCEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */
+#define FTM_RD_COMBINE_FAULTEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN3_MASK) >> FTM_COMBINE_FAULTEN3_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN3_SHIFT))
+
+/*! @brief Set the FAULTEN3 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN3_MASK, FTM_COMBINE_FAULTEN3(value)))
+#define FTM_BWR_COMBINE_FAULTEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN3_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_DEADTIME - Deadtime Insertion Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_DEADTIME - Deadtime Insertion Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the deadtime prescaler factor and deadtime value. All
+ * FTM channels use this clock prescaler and this deadtime value for the deadtime
+ * insertion.
+ */
+/*!
+ * @name Constants and macros for entire FTM_DEADTIME register
+ */
+/*@{*/
+#define FTM_RD_DEADTIME(base)    (FTM_DEADTIME_REG(base))
+#define FTM_WR_DEADTIME(base, value) (FTM_DEADTIME_REG(base) = (value))
+#define FTM_RMW_DEADTIME(base, mask, value) (FTM_WR_DEADTIME(base, (FTM_RD_DEADTIME(base) & ~(mask)) | (value)))
+#define FTM_SET_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) |  (value)))
+#define FTM_CLR_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) & ~(value)))
+#define FTM_TOG_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_DEADTIME bitfields
+ */
+
+/*!
+ * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
+ *
+ * Selects the deadtime insertion value for the deadtime counter. The deadtime
+ * counter is clocked by a scaled version of the system clock. See the description
+ * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
+ * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
+ * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
+ * This pattern continues up to a possible 63 counts. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */
+#define FTM_RD_DEADTIME_DTVAL(base) ((FTM_DEADTIME_REG(base) & FTM_DEADTIME_DTVAL_MASK) >> FTM_DEADTIME_DTVAL_SHIFT)
+#define FTM_BRD_DEADTIME_DTVAL(base) (FTM_RD_DEADTIME_DTVAL(base))
+
+/*! @brief Set the DTVAL field to a new value. */
+#define FTM_WR_DEADTIME_DTVAL(base, value) (FTM_RMW_DEADTIME(base, FTM_DEADTIME_DTVAL_MASK, FTM_DEADTIME_DTVAL(value)))
+#define FTM_BWR_DEADTIME_DTVAL(base, value) (FTM_WR_DEADTIME_DTVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
+ *
+ * Selects the division factor of the system clock. This prescaled clock is used
+ * by the deadtime counter. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0x - Divide the system clock by 1.
+ * - 0b10 - Divide the system clock by 4.
+ * - 0b11 - Divide the system clock by 16.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_DEADTIME_DTPS field. */
+#define FTM_RD_DEADTIME_DTPS(base) ((FTM_DEADTIME_REG(base) & FTM_DEADTIME_DTPS_MASK) >> FTM_DEADTIME_DTPS_SHIFT)
+#define FTM_BRD_DEADTIME_DTPS(base) (FTM_RD_DEADTIME_DTPS(base))
+
+/*! @brief Set the DTPS field to a new value. */
+#define FTM_WR_DEADTIME_DTPS(base, value) (FTM_RMW_DEADTIME(base, FTM_DEADTIME_DTPS_MASK, FTM_DEADTIME_DTPS(value)))
+#define FTM_BWR_DEADTIME_DTPS(base, value) (FTM_WR_DEADTIME_DTPS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_EXTTRIG - FTM External Trigger
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_EXTTRIG - FTM External Trigger (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register: Indicates when a channel trigger was generated Enables the
+ * generation of a trigger when the FTM counter is equal to its initial value
+ * Selects which channels are used in the generation of the channel triggers Several
+ * channels can be selected to generate multiple triggers in one PWM period.
+ * Channels 6 and 7 are not used to generate channel triggers.
+ */
+/*!
+ * @name Constants and macros for entire FTM_EXTTRIG register
+ */
+/*@{*/
+#define FTM_RD_EXTTRIG(base)     (FTM_EXTTRIG_REG(base))
+#define FTM_WR_EXTTRIG(base, value) (FTM_EXTTRIG_REG(base) = (value))
+#define FTM_RMW_EXTTRIG(base, mask, value) (FTM_WR_EXTTRIG(base, (FTM_RD_EXTTRIG(base) & ~(mask)) | (value)))
+#define FTM_SET_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) |  (value)))
+#define FTM_CLR_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) & ~(value)))
+#define FTM_TOG_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_EXTTRIG bitfields
+ */
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */
+#define FTM_RD_EXTTRIG_CH2TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH2TRIG_MASK) >> FTM_EXTTRIG_CH2TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH2TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH2TRIG_SHIFT))
+
+/*! @brief Set the CH2TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH2TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH2TRIG_MASK, FTM_EXTTRIG_CH2TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH2TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH2TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */
+#define FTM_RD_EXTTRIG_CH3TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH3TRIG_MASK) >> FTM_EXTTRIG_CH3TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH3TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH3TRIG_SHIFT))
+
+/*! @brief Set the CH3TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH3TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH3TRIG_MASK, FTM_EXTTRIG_CH3TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH3TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH3TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */
+#define FTM_RD_EXTTRIG_CH4TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH4TRIG_MASK) >> FTM_EXTTRIG_CH4TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH4TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH4TRIG_SHIFT))
+
+/*! @brief Set the CH4TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH4TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH4TRIG_MASK, FTM_EXTTRIG_CH4TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH4TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH4TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */
+#define FTM_RD_EXTTRIG_CH5TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH5TRIG_MASK) >> FTM_EXTTRIG_CH5TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH5TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH5TRIG_SHIFT))
+
+/*! @brief Set the CH5TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH5TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH5TRIG_MASK, FTM_EXTTRIG_CH5TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH5TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH5TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */
+#define FTM_RD_EXTTRIG_CH0TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH0TRIG_MASK) >> FTM_EXTTRIG_CH0TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH0TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH0TRIG_SHIFT))
+
+/*! @brief Set the CH0TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH0TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH0TRIG_MASK, FTM_EXTTRIG_CH0TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH0TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH0TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */
+#define FTM_RD_EXTTRIG_CH1TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH1TRIG_MASK) >> FTM_EXTTRIG_CH1TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH1TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH1TRIG_SHIFT))
+
+/*! @brief Set the CH1TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH1TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH1TRIG_MASK, FTM_EXTTRIG_CH1TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH1TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH1TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
+ *
+ * Enables the generation of the trigger when the FTM counter is equal to the
+ * CNTIN register.
+ *
+ * Values:
+ * - 0b0 - The generation of initialization trigger is disabled.
+ * - 0b1 - The generation of initialization trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */
+#define FTM_RD_EXTTRIG_INITTRIGEN(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_INITTRIGEN_MASK) >> FTM_EXTTRIG_INITTRIGEN_SHIFT)
+#define FTM_BRD_EXTTRIG_INITTRIGEN(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_INITTRIGEN_SHIFT))
+
+/*! @brief Set the INITTRIGEN field to a new value. */
+#define FTM_WR_EXTTRIG_INITTRIGEN(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_INITTRIGEN_MASK, FTM_EXTTRIG_INITTRIGEN(value)))
+#define FTM_BWR_EXTTRIG_INITTRIGEN(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_INITTRIGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
+ *
+ * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
+ * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
+ * has no effect. If another channel trigger is generated before the clearing
+ * sequence is completed, the sequence is reset so TRIGF remains set after the clear
+ * sequence is completed for the earlier TRIGF.
+ *
+ * Values:
+ * - 0b0 - No channel trigger was generated.
+ * - 0b1 - A channel trigger was generated.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */
+#define FTM_RD_EXTTRIG_TRIGF(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_TRIGF_MASK) >> FTM_EXTTRIG_TRIGF_SHIFT)
+#define FTM_BRD_EXTTRIG_TRIGF(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_TRIGF_SHIFT))
+
+/*! @brief Set the TRIGF field to a new value. */
+#define FTM_WR_EXTTRIG_TRIGF(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_TRIGF_MASK, FTM_EXTTRIG_TRIGF(value)))
+#define FTM_BWR_EXTTRIG_TRIGF(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_TRIGF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_POL - Channels Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_POL - Channels Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the output polarity of the FTM channels. The safe value
+ * that is driven in a channel output when the fault control is enabled and a
+ * fault condition is detected is the inactive state of the channel. That is, the
+ * safe value of a channel is the value of its POL bit.
+ */
+/*!
+ * @name Constants and macros for entire FTM_POL register
+ */
+/*@{*/
+#define FTM_RD_POL(base)         (FTM_POL_REG(base))
+#define FTM_WR_POL(base, value)  (FTM_POL_REG(base) = (value))
+#define FTM_RMW_POL(base, mask, value) (FTM_WR_POL(base, (FTM_RD_POL(base) & ~(mask)) | (value)))
+#define FTM_SET_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) |  (value)))
+#define FTM_CLR_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) & ~(value)))
+#define FTM_TOG_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_POL bitfields
+ */
+
+/*!
+ * @name Register FTM_POL, field POL0[0] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL0 field. */
+#define FTM_RD_POL_POL0(base) ((FTM_POL_REG(base) & FTM_POL_POL0_MASK) >> FTM_POL_POL0_SHIFT)
+#define FTM_BRD_POL_POL0(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL0_SHIFT))
+
+/*! @brief Set the POL0 field to a new value. */
+#define FTM_WR_POL_POL0(base, value) (FTM_RMW_POL(base, FTM_POL_POL0_MASK, FTM_POL_POL0(value)))
+#define FTM_BWR_POL_POL0(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL1[1] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL1 field. */
+#define FTM_RD_POL_POL1(base) ((FTM_POL_REG(base) & FTM_POL_POL1_MASK) >> FTM_POL_POL1_SHIFT)
+#define FTM_BRD_POL_POL1(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL1_SHIFT))
+
+/*! @brief Set the POL1 field to a new value. */
+#define FTM_WR_POL_POL1(base, value) (FTM_RMW_POL(base, FTM_POL_POL1_MASK, FTM_POL_POL1(value)))
+#define FTM_BWR_POL_POL1(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL2[2] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL2 field. */
+#define FTM_RD_POL_POL2(base) ((FTM_POL_REG(base) & FTM_POL_POL2_MASK) >> FTM_POL_POL2_SHIFT)
+#define FTM_BRD_POL_POL2(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL2_SHIFT))
+
+/*! @brief Set the POL2 field to a new value. */
+#define FTM_WR_POL_POL2(base, value) (FTM_RMW_POL(base, FTM_POL_POL2_MASK, FTM_POL_POL2(value)))
+#define FTM_BWR_POL_POL2(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL3[3] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL3 field. */
+#define FTM_RD_POL_POL3(base) ((FTM_POL_REG(base) & FTM_POL_POL3_MASK) >> FTM_POL_POL3_SHIFT)
+#define FTM_BRD_POL_POL3(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL3_SHIFT))
+
+/*! @brief Set the POL3 field to a new value. */
+#define FTM_WR_POL_POL3(base, value) (FTM_RMW_POL(base, FTM_POL_POL3_MASK, FTM_POL_POL3(value)))
+#define FTM_BWR_POL_POL3(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL4[4] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL4 field. */
+#define FTM_RD_POL_POL4(base) ((FTM_POL_REG(base) & FTM_POL_POL4_MASK) >> FTM_POL_POL4_SHIFT)
+#define FTM_BRD_POL_POL4(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL4_SHIFT))
+
+/*! @brief Set the POL4 field to a new value. */
+#define FTM_WR_POL_POL4(base, value) (FTM_RMW_POL(base, FTM_POL_POL4_MASK, FTM_POL_POL4(value)))
+#define FTM_BWR_POL_POL4(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL5[5] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL5 field. */
+#define FTM_RD_POL_POL5(base) ((FTM_POL_REG(base) & FTM_POL_POL5_MASK) >> FTM_POL_POL5_SHIFT)
+#define FTM_BRD_POL_POL5(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL5_SHIFT))
+
+/*! @brief Set the POL5 field to a new value. */
+#define FTM_WR_POL_POL5(base, value) (FTM_RMW_POL(base, FTM_POL_POL5_MASK, FTM_POL_POL5(value)))
+#define FTM_BWR_POL_POL5(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL6[6] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL6 field. */
+#define FTM_RD_POL_POL6(base) ((FTM_POL_REG(base) & FTM_POL_POL6_MASK) >> FTM_POL_POL6_SHIFT)
+#define FTM_BRD_POL_POL6(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL6_SHIFT))
+
+/*! @brief Set the POL6 field to a new value. */
+#define FTM_WR_POL_POL6(base, value) (FTM_RMW_POL(base, FTM_POL_POL6_MASK, FTM_POL_POL6(value)))
+#define FTM_BWR_POL_POL6(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL7[7] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL7 field. */
+#define FTM_RD_POL_POL7(base) ((FTM_POL_REG(base) & FTM_POL_POL7_MASK) >> FTM_POL_POL7_SHIFT)
+#define FTM_BRD_POL_POL7(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL7_SHIFT))
+
+/*! @brief Set the POL7 field to a new value. */
+#define FTM_WR_POL_POL7(base, value) (FTM_RMW_POL(base, FTM_POL_POL7_MASK, FTM_POL_POL7(value)))
+#define FTM_BWR_POL_POL7(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FMS - Fault Mode Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FMS - Fault Mode Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the fault detection flags, write protection enable
+ * bit, and the logic OR of the enabled fault inputs.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FMS register
+ */
+/*@{*/
+#define FTM_RD_FMS(base)         (FTM_FMS_REG(base))
+#define FTM_WR_FMS(base, value)  (FTM_FMS_REG(base) = (value))
+#define FTM_RMW_FMS(base, mask, value) (FTM_WR_FMS(base, (FTM_RD_FMS(base) & ~(mask)) | (value)))
+#define FTM_SET_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) |  (value)))
+#define FTM_CLR_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) & ~(value)))
+#define FTM_TOG_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FMS bitfields
+ */
+
+/*!
+ * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
+ * by reading the FMS register while FAULTF0 is set and then writing a 0 to
+ * FAULTF0 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF0 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF0 field. */
+#define FTM_RD_FMS_FAULTF0(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF0_MASK) >> FTM_FMS_FAULTF0_SHIFT)
+#define FTM_BRD_FMS_FAULTF0(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF0_SHIFT))
+
+/*! @brief Set the FAULTF0 field to a new value. */
+#define FTM_WR_FMS_FAULTF0(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF0_MASK, FTM_FMS_FAULTF0(value)))
+#define FTM_BWR_FMS_FAULTF0(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
+ * by reading the FMS register while FAULTF1 is set and then writing a 0 to
+ * FAULTF1 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF1 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF1 field. */
+#define FTM_RD_FMS_FAULTF1(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF1_MASK) >> FTM_FMS_FAULTF1_SHIFT)
+#define FTM_BRD_FMS_FAULTF1(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF1_SHIFT))
+
+/*! @brief Set the FAULTF1 field to a new value. */
+#define FTM_WR_FMS_FAULTF1(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF1_MASK, FTM_FMS_FAULTF1(value)))
+#define FTM_BWR_FMS_FAULTF1(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
+ * by reading the FMS register while FAULTF2 is set and then writing a 0 to
+ * FAULTF2 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF2 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF2 field. */
+#define FTM_RD_FMS_FAULTF2(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF2_MASK) >> FTM_FMS_FAULTF2_SHIFT)
+#define FTM_BRD_FMS_FAULTF2(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF2_SHIFT))
+
+/*! @brief Set the FAULTF2 field to a new value. */
+#define FTM_WR_FMS_FAULTF2(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF2_MASK, FTM_FMS_FAULTF2(value)))
+#define FTM_BWR_FMS_FAULTF2(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
+ * by reading the FMS register while FAULTF3 is set and then writing a 0 to
+ * FAULTF3 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF3 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF3 field. */
+#define FTM_RD_FMS_FAULTF3(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF3_MASK) >> FTM_FMS_FAULTF3_SHIFT)
+#define FTM_BRD_FMS_FAULTF3(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF3_SHIFT))
+
+/*! @brief Set the FAULTF3 field to a new value. */
+#define FTM_WR_FMS_FAULTF3(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF3_MASK, FTM_FMS_FAULTF3(value)))
+#define FTM_BWR_FMS_FAULTF3(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTIN[5] (RO)
+ *
+ * Represents the logic OR of the enabled fault inputs after their filter (if
+ * their filter is enabled) when fault control is enabled.
+ *
+ * Values:
+ * - 0b0 - The logic OR of the enabled fault inputs is 0.
+ * - 0b1 - The logic OR of the enabled fault inputs is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTIN field. */
+#define FTM_RD_FMS_FAULTIN(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTIN_MASK) >> FTM_FMS_FAULTIN_SHIFT)
+#define FTM_BRD_FMS_FAULTIN(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTIN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field WPEN[6] (RW)
+ *
+ * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
+ * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
+ * WPDIS. Writing 0 to WPEN has no effect.
+ *
+ * Values:
+ * - 0b0 - Write protection is disabled. Write protected bits can be written.
+ * - 0b1 - Write protection is enabled. Write protected bits cannot be written.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_WPEN field. */
+#define FTM_RD_FMS_WPEN(base) ((FTM_FMS_REG(base) & FTM_FMS_WPEN_MASK) >> FTM_FMS_WPEN_SHIFT)
+#define FTM_BRD_FMS_WPEN(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_WPEN_SHIFT))
+
+/*! @brief Set the WPEN field to a new value. */
+#define FTM_WR_FMS_WPEN(base, value) (FTM_RMW_FMS(base, FTM_FMS_WPEN_MASK, FTM_FMS_WPEN(value)))
+#define FTM_BWR_FMS_WPEN(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_WPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
+ *
+ * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
+ * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
+ * a 0 to FAULTF while there is no existing fault condition at the enabled fault
+ * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
+ * detected in an enabled fault input before the clearing sequence is completed, the
+ * sequence is reset so FAULTF remains set after the clearing sequence is
+ * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
+ * are cleared individually.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected.
+ * - 0b1 - A fault condition was detected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF field. */
+#define FTM_RD_FMS_FAULTF(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF_MASK) >> FTM_FMS_FAULTF_SHIFT)
+#define FTM_BRD_FMS_FAULTF(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF_SHIFT))
+
+/*! @brief Set the FAULTF field to a new value. */
+#define FTM_WR_FMS_FAULTF(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF_MASK, FTM_FMS_FAULTF(value)))
+#define FTM_BWR_FMS_FAULTF(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FILTER - Input Capture Filter Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FILTER - Input Capture Filter Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the inputs of channels. Channels
+ * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
+ * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
+ * in input modes. Failure to do this could result in a missing valid signal.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FILTER register
+ */
+/*@{*/
+#define FTM_RD_FILTER(base)      (FTM_FILTER_REG(base))
+#define FTM_WR_FILTER(base, value) (FTM_FILTER_REG(base) = (value))
+#define FTM_RMW_FILTER(base, mask, value) (FTM_WR_FILTER(base, (FTM_RD_FILTER(base) & ~(mask)) | (value)))
+#define FTM_SET_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) |  (value)))
+#define FTM_CLR_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) & ~(value)))
+#define FTM_TOG_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FILTER bitfields
+ */
+
+/*!
+ * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */
+#define FTM_RD_FILTER_CH0FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH0FVAL_MASK) >> FTM_FILTER_CH0FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH0FVAL(base) (FTM_RD_FILTER_CH0FVAL(base))
+
+/*! @brief Set the CH0FVAL field to a new value. */
+#define FTM_WR_FILTER_CH0FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH0FVAL_MASK, FTM_FILTER_CH0FVAL(value)))
+#define FTM_BWR_FILTER_CH0FVAL(base, value) (FTM_WR_FILTER_CH0FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */
+#define FTM_RD_FILTER_CH1FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH1FVAL_MASK) >> FTM_FILTER_CH1FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH1FVAL(base) (FTM_RD_FILTER_CH1FVAL(base))
+
+/*! @brief Set the CH1FVAL field to a new value. */
+#define FTM_WR_FILTER_CH1FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH1FVAL_MASK, FTM_FILTER_CH1FVAL(value)))
+#define FTM_BWR_FILTER_CH1FVAL(base, value) (FTM_WR_FILTER_CH1FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */
+#define FTM_RD_FILTER_CH2FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH2FVAL_MASK) >> FTM_FILTER_CH2FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH2FVAL(base) (FTM_RD_FILTER_CH2FVAL(base))
+
+/*! @brief Set the CH2FVAL field to a new value. */
+#define FTM_WR_FILTER_CH2FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH2FVAL_MASK, FTM_FILTER_CH2FVAL(value)))
+#define FTM_BWR_FILTER_CH2FVAL(base, value) (FTM_WR_FILTER_CH2FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */
+#define FTM_RD_FILTER_CH3FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH3FVAL_MASK) >> FTM_FILTER_CH3FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH3FVAL(base) (FTM_RD_FILTER_CH3FVAL(base))
+
+/*! @brief Set the CH3FVAL field to a new value. */
+#define FTM_WR_FILTER_CH3FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH3FVAL_MASK, FTM_FILTER_CH3FVAL(value)))
+#define FTM_BWR_FILTER_CH3FVAL(base, value) (FTM_WR_FILTER_CH3FVAL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FLTCTRL - Fault Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FLTCTRL - Fault Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the fault inputs, enables the
+ * fault inputs and the fault inputs filter.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FLTCTRL register
+ */
+/*@{*/
+#define FTM_RD_FLTCTRL(base)     (FTM_FLTCTRL_REG(base))
+#define FTM_WR_FLTCTRL(base, value) (FTM_FLTCTRL_REG(base) = (value))
+#define FTM_RMW_FLTCTRL(base, mask, value) (FTM_WR_FLTCTRL(base, (FTM_RD_FLTCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) |  (value)))
+#define FTM_CLR_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) & ~(value)))
+#define FTM_TOG_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FLTCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */
+#define FTM_RD_FLTCTRL_FAULT0EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT0EN_MASK) >> FTM_FLTCTRL_FAULT0EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT0EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT0EN_SHIFT))
+
+/*! @brief Set the FAULT0EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT0EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT0EN_MASK, FTM_FLTCTRL_FAULT0EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT0EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */
+#define FTM_RD_FLTCTRL_FAULT1EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT1EN_MASK) >> FTM_FLTCTRL_FAULT1EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT1EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT1EN_SHIFT))
+
+/*! @brief Set the FAULT1EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT1EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT1EN_MASK, FTM_FLTCTRL_FAULT1EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT1EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */
+#define FTM_RD_FLTCTRL_FAULT2EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT2EN_MASK) >> FTM_FLTCTRL_FAULT2EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT2EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT2EN_SHIFT))
+
+/*! @brief Set the FAULT2EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT2EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT2EN_MASK, FTM_FLTCTRL_FAULT2EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT2EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */
+#define FTM_RD_FLTCTRL_FAULT3EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT3EN_MASK) >> FTM_FLTCTRL_FAULT3EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT3EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT3EN_SHIFT))
+
+/*! @brief Set the FAULT3EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT3EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT3EN_MASK, FTM_FLTCTRL_FAULT3EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT3EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT3EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */
+#define FTM_RD_FLTCTRL_FFLTR0EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR0EN_MASK) >> FTM_FLTCTRL_FFLTR0EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR0EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR0EN_SHIFT))
+
+/*! @brief Set the FFLTR0EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR0EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR0EN_MASK, FTM_FLTCTRL_FFLTR0EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR0EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */
+#define FTM_RD_FLTCTRL_FFLTR1EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR1EN_MASK) >> FTM_FLTCTRL_FFLTR1EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR1EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR1EN_SHIFT))
+
+/*! @brief Set the FFLTR1EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR1EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR1EN_MASK, FTM_FLTCTRL_FFLTR1EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR1EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */
+#define FTM_RD_FLTCTRL_FFLTR2EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR2EN_MASK) >> FTM_FLTCTRL_FFLTR2EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR2EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR2EN_SHIFT))
+
+/*! @brief Set the FFLTR2EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR2EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR2EN_MASK, FTM_FLTCTRL_FFLTR2EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR2EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */
+#define FTM_RD_FLTCTRL_FFLTR3EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR3EN_MASK) >> FTM_FLTCTRL_FFLTR3EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR3EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR3EN_SHIFT))
+
+/*! @brief Set the FFLTR3EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR3EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR3EN_MASK, FTM_FLTCTRL_FFLTR3EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR3EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR3EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
+ *
+ * Selects the filter value for the fault inputs. The fault filter is disabled
+ * when the value is zero. Writing to this field has immediate effect and must be
+ * done only when the fault control or all fault inputs are disabled. Failure to
+ * do this could result in a missing fault detection.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */
+#define FTM_RD_FLTCTRL_FFVAL(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFVAL_MASK) >> FTM_FLTCTRL_FFVAL_SHIFT)
+#define FTM_BRD_FLTCTRL_FFVAL(base) (FTM_RD_FLTCTRL_FFVAL(base))
+
+/*! @brief Set the FFVAL field to a new value. */
+#define FTM_WR_FLTCTRL_FFVAL(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFVAL_MASK, FTM_FLTCTRL_FFVAL(value)))
+#define FTM_BWR_FLTCTRL_FFVAL(base, value) (FTM_WR_FLTCTRL_FFVAL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_QDCTRL - Quadrature Decoder Control And Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has the control and status bits for the Quadrature Decoder mode.
+ */
+/*!
+ * @name Constants and macros for entire FTM_QDCTRL register
+ */
+/*@{*/
+#define FTM_RD_QDCTRL(base)      (FTM_QDCTRL_REG(base))
+#define FTM_WR_QDCTRL(base, value) (FTM_QDCTRL_REG(base) = (value))
+#define FTM_RMW_QDCTRL(base, mask, value) (FTM_WR_QDCTRL(base, (FTM_RD_QDCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) |  (value)))
+#define FTM_CLR_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) & ~(value)))
+#define FTM_TOG_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_QDCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
+ *
+ * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
+ * signals control the FTM counter direction. The Quadrature Decoder mode has
+ * precedence over the other modes. See #ModeSel1Table. This field is write protected.
+ * It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Quadrature Decoder mode is disabled.
+ * - 0b1 - Quadrature Decoder mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */
+#define FTM_RD_QDCTRL_QUADEN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADEN_MASK) >> FTM_QDCTRL_QUADEN_SHIFT)
+#define FTM_BRD_QDCTRL_QUADEN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADEN_SHIFT))
+
+/*! @brief Set the QUADEN field to a new value. */
+#define FTM_WR_QDCTRL_QUADEN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_QUADEN_MASK, FTM_QDCTRL_QUADEN(value)))
+#define FTM_BWR_QDCTRL_QUADEN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
+ *
+ * Indicates if the TOF bit was set on the top or the bottom of counting.
+ *
+ * Values:
+ * - 0b0 - TOF bit was set on the bottom of counting. There was an FTM counter
+ *     decrement and FTM counter changes from its minimum value (CNTIN register)
+ *     to its maximum value (MOD register).
+ * - 0b1 - TOF bit was set on the top of counting. There was an FTM counter
+ *     increment and FTM counter changes from its maximum value (MOD register) to its
+ *     minimum value (CNTIN register).
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */
+#define FTM_RD_QDCTRL_TOFDIR(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_TOFDIR_MASK) >> FTM_QDCTRL_TOFDIR_SHIFT)
+#define FTM_BRD_QDCTRL_TOFDIR(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_TOFDIR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
+ *
+ * Indicates the counting direction.
+ *
+ * Values:
+ * - 0b0 - Counting direction is decreasing (FTM counter decrement).
+ * - 0b1 - Counting direction is increasing (FTM counter increment).
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */
+#define FTM_RD_QDCTRL_QUADIR(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADIR_MASK) >> FTM_QDCTRL_QUADIR_SHIFT)
+#define FTM_BRD_QDCTRL_QUADIR(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADIR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
+ *
+ * Selects the encoding mode used in the Quadrature Decoder mode.
+ *
+ * Values:
+ * - 0b0 - Phase A and phase B encoding mode.
+ * - 0b1 - Count and direction encoding mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */
+#define FTM_RD_QDCTRL_QUADMODE(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADMODE_MASK) >> FTM_QDCTRL_QUADMODE_SHIFT)
+#define FTM_BRD_QDCTRL_QUADMODE(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADMODE_SHIFT))
+
+/*! @brief Set the QUADMODE field to a new value. */
+#define FTM_WR_QDCTRL_QUADMODE(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_QUADMODE_MASK, FTM_QDCTRL_QUADMODE(value)))
+#define FTM_BWR_QDCTRL_QUADMODE(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase B input.
+ *
+ * Values:
+ * - 0b0 - Normal polarity. Phase B input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 0b1 - Inverted polarity. Phase B input signal is inverted before
+ *     identifying the rising and falling edges of this signal.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */
+#define FTM_RD_QDCTRL_PHBPOL(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHBPOL_MASK) >> FTM_QDCTRL_PHBPOL_SHIFT)
+#define FTM_BRD_QDCTRL_PHBPOL(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBPOL_SHIFT))
+
+/*! @brief Set the PHBPOL field to a new value. */
+#define FTM_WR_QDCTRL_PHBPOL(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHBPOL_MASK, FTM_QDCTRL_PHBPOL(value)))
+#define FTM_BWR_QDCTRL_PHBPOL(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase A input.
+ *
+ * Values:
+ * - 0b0 - Normal polarity. Phase A input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 0b1 - Inverted polarity. Phase A input signal is inverted before
+ *     identifying the rising and falling edges of this signal.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */
+#define FTM_RD_QDCTRL_PHAPOL(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHAPOL_MASK) >> FTM_QDCTRL_PHAPOL_SHIFT)
+#define FTM_BRD_QDCTRL_PHAPOL(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAPOL_SHIFT))
+
+/*! @brief Set the PHAPOL field to a new value. */
+#define FTM_WR_QDCTRL_PHAPOL(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHAPOL_MASK, FTM_QDCTRL_PHAPOL(value)))
+#define FTM_BWR_QDCTRL_PHAPOL(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase B input. The filter value
+ * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
+ * filter is also disabled when CH1FVAL is zero.
+ *
+ * Values:
+ * - 0b0 - Phase B input filter is disabled.
+ * - 0b1 - Phase B input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */
+#define FTM_RD_QDCTRL_PHBFLTREN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHBFLTREN_MASK) >> FTM_QDCTRL_PHBFLTREN_SHIFT)
+#define FTM_BRD_QDCTRL_PHBFLTREN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBFLTREN_SHIFT))
+
+/*! @brief Set the PHBFLTREN field to a new value. */
+#define FTM_WR_QDCTRL_PHBFLTREN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHBFLTREN_MASK, FTM_QDCTRL_PHBFLTREN(value)))
+#define FTM_BWR_QDCTRL_PHBFLTREN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBFLTREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase A input. The filter value
+ * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
+ * filter is also disabled when CH0FVAL is zero.
+ *
+ * Values:
+ * - 0b0 - Phase A input filter is disabled.
+ * - 0b1 - Phase A input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */
+#define FTM_RD_QDCTRL_PHAFLTREN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHAFLTREN_MASK) >> FTM_QDCTRL_PHAFLTREN_SHIFT)
+#define FTM_BRD_QDCTRL_PHAFLTREN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAFLTREN_SHIFT))
+
+/*! @brief Set the PHAFLTREN field to a new value. */
+#define FTM_WR_QDCTRL_PHAFLTREN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHAFLTREN_MASK, FTM_QDCTRL_PHAFLTREN(value)))
+#define FTM_BWR_QDCTRL_PHAFLTREN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAFLTREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CONF - Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CONF - Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the number of times that the FTM counter overflow
+ * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
+ * of an external global time base, and the global time base signal generation.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CONF register
+ */
+/*@{*/
+#define FTM_RD_CONF(base)        (FTM_CONF_REG(base))
+#define FTM_WR_CONF(base, value) (FTM_CONF_REG(base) = (value))
+#define FTM_RMW_CONF(base, mask, value) (FTM_WR_CONF(base, (FTM_RD_CONF(base) & ~(mask)) | (value)))
+#define FTM_SET_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) |  (value)))
+#define FTM_CLR_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) & ~(value)))
+#define FTM_TOG_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CONF bitfields
+ */
+
+/*!
+ * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
+ *
+ * Selects the ratio between the number of counter overflows to the number of
+ * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
+ * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
+ * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
+ * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
+ * first counter overflow but not for the next 3 overflows. This pattern continues
+ * up to a maximum of 31.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_NUMTOF field. */
+#define FTM_RD_CONF_NUMTOF(base) ((FTM_CONF_REG(base) & FTM_CONF_NUMTOF_MASK) >> FTM_CONF_NUMTOF_SHIFT)
+#define FTM_BRD_CONF_NUMTOF(base) (FTM_RD_CONF_NUMTOF(base))
+
+/*! @brief Set the NUMTOF field to a new value. */
+#define FTM_WR_CONF_NUMTOF(base, value) (FTM_RMW_CONF(base, FTM_CONF_NUMTOF_MASK, FTM_CONF_NUMTOF(value)))
+#define FTM_BWR_CONF_NUMTOF(base, value) (FTM_WR_CONF_NUMTOF(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
+ *
+ * Selects the FTM behavior in BDM mode. See BDM mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_BDMMODE field. */
+#define FTM_RD_CONF_BDMMODE(base) ((FTM_CONF_REG(base) & FTM_CONF_BDMMODE_MASK) >> FTM_CONF_BDMMODE_SHIFT)
+#define FTM_BRD_CONF_BDMMODE(base) (FTM_RD_CONF_BDMMODE(base))
+
+/*! @brief Set the BDMMODE field to a new value. */
+#define FTM_WR_CONF_BDMMODE(base, value) (FTM_RMW_CONF(base, FTM_CONF_BDMMODE_MASK, FTM_CONF_BDMMODE(value)))
+#define FTM_BWR_CONF_BDMMODE(base, value) (FTM_WR_CONF_BDMMODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field GTBEEN[9] (RW)
+ *
+ * Configures the FTM to use an external global time base signal that is
+ * generated by another FTM.
+ *
+ * Values:
+ * - 0b0 - Use of an external global time base is disabled.
+ * - 0b1 - Use of an external global time base is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_GTBEEN field. */
+#define FTM_RD_CONF_GTBEEN(base) ((FTM_CONF_REG(base) & FTM_CONF_GTBEEN_MASK) >> FTM_CONF_GTBEEN_SHIFT)
+#define FTM_BRD_CONF_GTBEEN(base) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEEN_SHIFT))
+
+/*! @brief Set the GTBEEN field to a new value. */
+#define FTM_WR_CONF_GTBEEN(base, value) (FTM_RMW_CONF(base, FTM_CONF_GTBEEN_MASK, FTM_CONF_GTBEEN(value)))
+#define FTM_BWR_CONF_GTBEEN(base, value) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field GTBEOUT[10] (RW)
+ *
+ * Enables the global time base signal generation to other FTMs.
+ *
+ * Values:
+ * - 0b0 - A global time base signal generation is disabled.
+ * - 0b1 - A global time base signal generation is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_GTBEOUT field. */
+#define FTM_RD_CONF_GTBEOUT(base) ((FTM_CONF_REG(base) & FTM_CONF_GTBEOUT_MASK) >> FTM_CONF_GTBEOUT_SHIFT)
+#define FTM_BRD_CONF_GTBEOUT(base) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEOUT_SHIFT))
+
+/*! @brief Set the GTBEOUT field to a new value. */
+#define FTM_WR_CONF_GTBEOUT(base, value) (FTM_RMW_CONF(base, FTM_CONF_GTBEOUT_MASK, FTM_CONF_GTBEOUT(value)))
+#define FTM_BWR_CONF_GTBEOUT(base, value) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEOUT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FLTPOL - FTM Fault Input Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FLTPOL - FTM Fault Input Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the fault inputs polarity.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FLTPOL register
+ */
+/*@{*/
+#define FTM_RD_FLTPOL(base)      (FTM_FLTPOL_REG(base))
+#define FTM_WR_FLTPOL(base, value) (FTM_FLTPOL_REG(base) = (value))
+#define FTM_RMW_FLTPOL(base, mask, value) (FTM_WR_FLTPOL(base, (FTM_RD_FLTPOL(base) & ~(mask)) | (value)))
+#define FTM_SET_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) |  (value)))
+#define FTM_CLR_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) & ~(value)))
+#define FTM_TOG_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FLTPOL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */
+#define FTM_RD_FLTPOL_FLT0POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT0POL_MASK) >> FTM_FLTPOL_FLT0POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT0POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT0POL_SHIFT))
+
+/*! @brief Set the FLT0POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT0POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT0POL_MASK, FTM_FLTPOL_FLT0POL(value)))
+#define FTM_BWR_FLTPOL_FLT0POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT0POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */
+#define FTM_RD_FLTPOL_FLT1POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT1POL_MASK) >> FTM_FLTPOL_FLT1POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT1POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT1POL_SHIFT))
+
+/*! @brief Set the FLT1POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT1POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT1POL_MASK, FTM_FLTPOL_FLT1POL(value)))
+#define FTM_BWR_FLTPOL_FLT1POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT1POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */
+#define FTM_RD_FLTPOL_FLT2POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT2POL_MASK) >> FTM_FLTPOL_FLT2POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT2POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT2POL_SHIFT))
+
+/*! @brief Set the FLT2POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT2POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT2POL_MASK, FTM_FLTPOL_FLT2POL(value)))
+#define FTM_BWR_FLTPOL_FLT2POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT2POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */
+#define FTM_RD_FLTPOL_FLT3POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT3POL_MASK) >> FTM_FLTPOL_FLT3POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT3POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT3POL_SHIFT))
+
+/*! @brief Set the FLT3POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT3POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT3POL_MASK, FTM_FLTPOL_FLT3POL(value)))
+#define FTM_BWR_FLTPOL_FLT3POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT3POL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SYNCONF - Synchronization Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SYNCONF - Synchronization Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
+ * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
+ * 0, 1, 2, when the hardware trigger j is detected.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SYNCONF register
+ */
+/*@{*/
+#define FTM_RD_SYNCONF(base)     (FTM_SYNCONF_REG(base))
+#define FTM_WR_SYNCONF(base, value) (FTM_SYNCONF_REG(base) = (value))
+#define FTM_RMW_SYNCONF(base, mask, value) (FTM_WR_SYNCONF(base, (FTM_RD_SYNCONF(base) & ~(mask)) | (value)))
+#define FTM_SET_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) |  (value)))
+#define FTM_CLR_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) & ~(value)))
+#define FTM_TOG_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SYNCONF bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - FTM clears the TRIGj bit when the hardware trigger j is detected,
+ *     where j = 0, 1,2.
+ * - 0b1 - FTM does not clear the TRIGj bit when the hardware trigger j is
+ *     detected, where j = 0, 1,2.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */
+#define FTM_RD_SYNCONF_HWTRIGMODE(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWTRIGMODE_MASK) >> FTM_SYNCONF_HWTRIGMODE_SHIFT)
+#define FTM_BRD_SYNCONF_HWTRIGMODE(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWTRIGMODE_SHIFT))
+
+/*! @brief Set the HWTRIGMODE field to a new value. */
+#define FTM_WR_SYNCONF_HWTRIGMODE(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWTRIGMODE_MASK, FTM_SYNCONF_HWTRIGMODE(value)))
+#define FTM_BWR_SYNCONF_HWTRIGMODE(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWTRIGMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
+ *
+ * Values:
+ * - 0b0 - CNTIN register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - CNTIN register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */
+#define FTM_RD_SYNCONF_CNTINC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_CNTINC_MASK) >> FTM_SYNCONF_CNTINC_SHIFT)
+#define FTM_BRD_SYNCONF_CNTINC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_CNTINC_SHIFT))
+
+/*! @brief Set the CNTINC field to a new value. */
+#define FTM_WR_SYNCONF_CNTINC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_CNTINC_MASK, FTM_SYNCONF_CNTINC(value)))
+#define FTM_BWR_SYNCONF_CNTINC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_CNTINC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field INVC[4] (RW)
+ *
+ * Values:
+ * - 0b0 - INVCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - INVCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_INVC field. */
+#define FTM_RD_SYNCONF_INVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_INVC_MASK) >> FTM_SYNCONF_INVC_SHIFT)
+#define FTM_BRD_SYNCONF_INVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_INVC_SHIFT))
+
+/*! @brief Set the INVC field to a new value. */
+#define FTM_WR_SYNCONF_INVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_INVC_MASK, FTM_SYNCONF_INVC(value)))
+#define FTM_BWR_SYNCONF_INVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_INVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOC[5] (RW)
+ *
+ * Values:
+ * - 0b0 - SWOCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - SWOCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWOC field. */
+#define FTM_RD_SYNCONF_SWOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWOC_MASK) >> FTM_SYNCONF_SWOC_SHIFT)
+#define FTM_BRD_SYNCONF_SWOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOC_SHIFT))
+
+/*! @brief Set the SWOC field to a new value. */
+#define FTM_WR_SYNCONF_SWOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWOC_MASK, FTM_SYNCONF_SWOC(value)))
+#define FTM_BWR_SYNCONF_SWOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
+ *
+ * Selects the PWM Synchronization mode.
+ *
+ * Values:
+ * - 0b0 - Legacy PWM synchronization is selected.
+ * - 0b1 - Enhanced PWM synchronization is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */
+#define FTM_RD_SYNCONF_SYNCMODE(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SYNCMODE_MASK) >> FTM_SYNCONF_SYNCMODE_SHIFT)
+#define FTM_BRD_SYNCONF_SYNCMODE(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SYNCMODE_SHIFT))
+
+/*! @brief Set the SYNCMODE field to a new value. */
+#define FTM_WR_SYNCONF_SYNCMODE(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SYNCMODE_MASK, FTM_SYNCONF_SYNCMODE(value)))
+#define FTM_BWR_SYNCONF_SYNCMODE(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SYNCMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
+ *
+ * FTM counter synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the FTM counter
+ *     synchronization.
+ * - 0b1 - The software trigger activates the FTM counter synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */
+#define FTM_RD_SYNCONF_SWRSTCNT(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWRSTCNT_MASK) >> FTM_SYNCONF_SWRSTCNT_SHIFT)
+#define FTM_BRD_SYNCONF_SWRSTCNT(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWRSTCNT_SHIFT))
+
+/*! @brief Set the SWRSTCNT field to a new value. */
+#define FTM_WR_SYNCONF_SWRSTCNT(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWRSTCNT_MASK, FTM_SYNCONF_SWRSTCNT(value)))
+#define FTM_BWR_SYNCONF_SWRSTCNT(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWRSTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by the software
+ * trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 0b1 - The software trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */
+#define FTM_RD_SYNCONF_SWWRBUF(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWWRBUF_MASK) >> FTM_SYNCONF_SWWRBUF_SHIFT)
+#define FTM_BRD_SYNCONF_SWWRBUF(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWWRBUF_SHIFT))
+
+/*! @brief Set the SWWRBUF field to a new value. */
+#define FTM_WR_SYNCONF_SWWRBUF(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWWRBUF_MASK, FTM_SYNCONF_SWWRBUF(value)))
+#define FTM_BWR_SYNCONF_SWWRBUF(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWWRBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOM[10] (RW)
+ *
+ * Output mask synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the OUTMASK register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWOM field. */
+#define FTM_RD_SYNCONF_SWOM(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWOM_MASK) >> FTM_SYNCONF_SWOM_SHIFT)
+#define FTM_BRD_SYNCONF_SWOM(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOM_SHIFT))
+
+/*! @brief Set the SWOM field to a new value. */
+#define FTM_WR_SYNCONF_SWOM(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWOM_MASK, FTM_SYNCONF_SWOM(value)))
+#define FTM_BWR_SYNCONF_SWOM(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
+ *
+ * Inverting control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the INVCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */
+#define FTM_RD_SYNCONF_SWINVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWINVC_MASK) >> FTM_SYNCONF_SWINVC_SHIFT)
+#define FTM_BRD_SYNCONF_SWINVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWINVC_SHIFT))
+
+/*! @brief Set the SWINVC field to a new value. */
+#define FTM_WR_SYNCONF_SWINVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWINVC_MASK, FTM_SYNCONF_SWINVC(value)))
+#define FTM_BWR_SYNCONF_SWINVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWINVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
+ *
+ * Software output control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the SWOCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */
+#define FTM_RD_SYNCONF_SWSOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWSOC_MASK) >> FTM_SYNCONF_SWSOC_SHIFT)
+#define FTM_BRD_SYNCONF_SWSOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWSOC_SHIFT))
+
+/*! @brief Set the SWSOC field to a new value. */
+#define FTM_WR_SYNCONF_SWSOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWSOC_MASK, FTM_SYNCONF_SWSOC(value)))
+#define FTM_BWR_SYNCONF_SWSOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWSOC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
+ *
+ * FTM counter synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the FTM counter synchronization.
+ * - 0b1 - A hardware trigger activates the FTM counter synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */
+#define FTM_RD_SYNCONF_HWRSTCNT(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWRSTCNT_MASK) >> FTM_SYNCONF_HWRSTCNT_SHIFT)
+#define FTM_BRD_SYNCONF_HWRSTCNT(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWRSTCNT_SHIFT))
+
+/*! @brief Set the HWRSTCNT field to a new value. */
+#define FTM_WR_SYNCONF_HWRSTCNT(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWRSTCNT_MASK, FTM_SYNCONF_HWRSTCNT(value)))
+#define FTM_BWR_SYNCONF_HWRSTCNT(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWRSTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by a hardware
+ * trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */
+#define FTM_RD_SYNCONF_HWWRBUF(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWWRBUF_MASK) >> FTM_SYNCONF_HWWRBUF_SHIFT)
+#define FTM_BRD_SYNCONF_HWWRBUF(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWWRBUF_SHIFT))
+
+/*! @brief Set the HWWRBUF field to a new value. */
+#define FTM_WR_SYNCONF_HWWRBUF(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWWRBUF_MASK, FTM_SYNCONF_HWWRBUF(value)))
+#define FTM_BWR_SYNCONF_HWWRBUF(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWWRBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWOM[18] (RW)
+ *
+ * Output mask synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the OUTMASK register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWOM field. */
+#define FTM_RD_SYNCONF_HWOM(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWOM_MASK) >> FTM_SYNCONF_HWOM_SHIFT)
+#define FTM_BRD_SYNCONF_HWOM(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWOM_SHIFT))
+
+/*! @brief Set the HWOM field to a new value. */
+#define FTM_WR_SYNCONF_HWOM(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWOM_MASK, FTM_SYNCONF_HWOM(value)))
+#define FTM_BWR_SYNCONF_HWOM(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
+ *
+ * Inverting control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the INVCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */
+#define FTM_RD_SYNCONF_HWINVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWINVC_MASK) >> FTM_SYNCONF_HWINVC_SHIFT)
+#define FTM_BRD_SYNCONF_HWINVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWINVC_SHIFT))
+
+/*! @brief Set the HWINVC field to a new value. */
+#define FTM_WR_SYNCONF_HWINVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWINVC_MASK, FTM_SYNCONF_HWINVC(value)))
+#define FTM_BWR_SYNCONF_HWINVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWINVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
+ *
+ * Software output control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the SWOCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */
+#define FTM_RD_SYNCONF_HWSOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWSOC_MASK) >> FTM_SYNCONF_HWSOC_SHIFT)
+#define FTM_BRD_SYNCONF_HWSOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWSOC_SHIFT))
+
+/*! @brief Set the HWSOC field to a new value. */
+#define FTM_WR_SYNCONF_HWSOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWSOC_MASK, FTM_SYNCONF_HWSOC(value)))
+#define FTM_BWR_SYNCONF_HWSOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWSOC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_INVCTRL - FTM Inverting Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_INVCTRL - FTM Inverting Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls when the channel (n) output becomes the channel (n+1)
+ * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
+ * bit enables the inverting operation for the corresponding pair channels m. This
+ * register has a write buffer. The INVmEN bit is updated by the INVCTRL
+ * register synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_INVCTRL register
+ */
+/*@{*/
+#define FTM_RD_INVCTRL(base)     (FTM_INVCTRL_REG(base))
+#define FTM_WR_INVCTRL(base, value) (FTM_INVCTRL_REG(base) = (value))
+#define FTM_RMW_INVCTRL(base, mask, value) (FTM_WR_INVCTRL(base, (FTM_RD_INVCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) |  (value)))
+#define FTM_CLR_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) & ~(value)))
+#define FTM_TOG_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_INVCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */
+#define FTM_RD_INVCTRL_INV0EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV0EN_MASK) >> FTM_INVCTRL_INV0EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV0EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV0EN_SHIFT))
+
+/*! @brief Set the INV0EN field to a new value. */
+#define FTM_WR_INVCTRL_INV0EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV0EN_MASK, FTM_INVCTRL_INV0EN(value)))
+#define FTM_BWR_INVCTRL_INV0EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */
+#define FTM_RD_INVCTRL_INV1EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV1EN_MASK) >> FTM_INVCTRL_INV1EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV1EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV1EN_SHIFT))
+
+/*! @brief Set the INV1EN field to a new value. */
+#define FTM_WR_INVCTRL_INV1EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV1EN_MASK, FTM_INVCTRL_INV1EN(value)))
+#define FTM_BWR_INVCTRL_INV1EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */
+#define FTM_RD_INVCTRL_INV2EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV2EN_MASK) >> FTM_INVCTRL_INV2EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV2EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV2EN_SHIFT))
+
+/*! @brief Set the INV2EN field to a new value. */
+#define FTM_WR_INVCTRL_INV2EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV2EN_MASK, FTM_INVCTRL_INV2EN(value)))
+#define FTM_BWR_INVCTRL_INV2EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */
+#define FTM_RD_INVCTRL_INV3EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV3EN_MASK) >> FTM_INVCTRL_INV3EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV3EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV3EN_SHIFT))
+
+/*! @brief Set the INV3EN field to a new value. */
+#define FTM_WR_INVCTRL_INV3EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV3EN_MASK, FTM_INVCTRL_INV3EN(value)))
+#define FTM_BWR_INVCTRL_INV3EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV3EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SWOCTRL - FTM Software Output Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SWOCTRL - FTM Software Output Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register enables software control of channel (n) output and defines the
+ * value forced to the channel (n) output: The CHnOC bits enable the control of
+ * the corresponding channel (n) output by software. The CHnOCV bits select the
+ * value that is forced at the corresponding channel (n) output. This register has
+ * a write buffer. The fields are updated by the SWOCTRL register synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SWOCTRL register
+ */
+/*@{*/
+#define FTM_RD_SWOCTRL(base)     (FTM_SWOCTRL_REG(base))
+#define FTM_WR_SWOCTRL(base, value) (FTM_SWOCTRL_REG(base) = (value))
+#define FTM_RMW_SWOCTRL(base, mask, value) (FTM_WR_SWOCTRL(base, (FTM_RD_SWOCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) |  (value)))
+#define FTM_CLR_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) & ~(value)))
+#define FTM_TOG_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SWOCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */
+#define FTM_RD_SWOCTRL_CH0OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH0OC_MASK) >> FTM_SWOCTRL_CH0OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH0OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OC_SHIFT))
+
+/*! @brief Set the CH0OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH0OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH0OC_MASK, FTM_SWOCTRL_CH0OC(value)))
+#define FTM_BWR_SWOCTRL_CH0OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */
+#define FTM_RD_SWOCTRL_CH1OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH1OC_MASK) >> FTM_SWOCTRL_CH1OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH1OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OC_SHIFT))
+
+/*! @brief Set the CH1OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH1OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH1OC_MASK, FTM_SWOCTRL_CH1OC(value)))
+#define FTM_BWR_SWOCTRL_CH1OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */
+#define FTM_RD_SWOCTRL_CH2OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH2OC_MASK) >> FTM_SWOCTRL_CH2OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH2OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OC_SHIFT))
+
+/*! @brief Set the CH2OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH2OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH2OC_MASK, FTM_SWOCTRL_CH2OC(value)))
+#define FTM_BWR_SWOCTRL_CH2OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */
+#define FTM_RD_SWOCTRL_CH3OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH3OC_MASK) >> FTM_SWOCTRL_CH3OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH3OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OC_SHIFT))
+
+/*! @brief Set the CH3OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH3OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH3OC_MASK, FTM_SWOCTRL_CH3OC(value)))
+#define FTM_BWR_SWOCTRL_CH3OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */
+#define FTM_RD_SWOCTRL_CH4OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH4OC_MASK) >> FTM_SWOCTRL_CH4OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH4OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OC_SHIFT))
+
+/*! @brief Set the CH4OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH4OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH4OC_MASK, FTM_SWOCTRL_CH4OC(value)))
+#define FTM_BWR_SWOCTRL_CH4OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */
+#define FTM_RD_SWOCTRL_CH5OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH5OC_MASK) >> FTM_SWOCTRL_CH5OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH5OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OC_SHIFT))
+
+/*! @brief Set the CH5OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH5OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH5OC_MASK, FTM_SWOCTRL_CH5OC(value)))
+#define FTM_BWR_SWOCTRL_CH5OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */
+#define FTM_RD_SWOCTRL_CH6OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH6OC_MASK) >> FTM_SWOCTRL_CH6OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH6OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OC_SHIFT))
+
+/*! @brief Set the CH6OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH6OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH6OC_MASK, FTM_SWOCTRL_CH6OC(value)))
+#define FTM_BWR_SWOCTRL_CH6OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */
+#define FTM_RD_SWOCTRL_CH7OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH7OC_MASK) >> FTM_SWOCTRL_CH7OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH7OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OC_SHIFT))
+
+/*! @brief Set the CH7OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH7OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH7OC_MASK, FTM_SWOCTRL_CH7OC(value)))
+#define FTM_BWR_SWOCTRL_CH7OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */
+#define FTM_RD_SWOCTRL_CH0OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH0OCV_MASK) >> FTM_SWOCTRL_CH0OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH0OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OCV_SHIFT))
+
+/*! @brief Set the CH0OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH0OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH0OCV_MASK, FTM_SWOCTRL_CH0OCV(value)))
+#define FTM_BWR_SWOCTRL_CH0OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */
+#define FTM_RD_SWOCTRL_CH1OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH1OCV_MASK) >> FTM_SWOCTRL_CH1OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH1OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OCV_SHIFT))
+
+/*! @brief Set the CH1OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH1OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH1OCV_MASK, FTM_SWOCTRL_CH1OCV(value)))
+#define FTM_BWR_SWOCTRL_CH1OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */
+#define FTM_RD_SWOCTRL_CH2OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH2OCV_MASK) >> FTM_SWOCTRL_CH2OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH2OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OCV_SHIFT))
+
+/*! @brief Set the CH2OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH2OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH2OCV_MASK, FTM_SWOCTRL_CH2OCV(value)))
+#define FTM_BWR_SWOCTRL_CH2OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */
+#define FTM_RD_SWOCTRL_CH3OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH3OCV_MASK) >> FTM_SWOCTRL_CH3OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH3OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OCV_SHIFT))
+
+/*! @brief Set the CH3OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH3OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH3OCV_MASK, FTM_SWOCTRL_CH3OCV(value)))
+#define FTM_BWR_SWOCTRL_CH3OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */
+#define FTM_RD_SWOCTRL_CH4OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH4OCV_MASK) >> FTM_SWOCTRL_CH4OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH4OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OCV_SHIFT))
+
+/*! @brief Set the CH4OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH4OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH4OCV_MASK, FTM_SWOCTRL_CH4OCV(value)))
+#define FTM_BWR_SWOCTRL_CH4OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */
+#define FTM_RD_SWOCTRL_CH5OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH5OCV_MASK) >> FTM_SWOCTRL_CH5OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH5OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OCV_SHIFT))
+
+/*! @brief Set the CH5OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH5OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH5OCV_MASK, FTM_SWOCTRL_CH5OCV(value)))
+#define FTM_BWR_SWOCTRL_CH5OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */
+#define FTM_RD_SWOCTRL_CH6OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH6OCV_MASK) >> FTM_SWOCTRL_CH6OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH6OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OCV_SHIFT))
+
+/*! @brief Set the CH6OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH6OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH6OCV_MASK, FTM_SWOCTRL_CH6OCV(value)))
+#define FTM_BWR_SWOCTRL_CH6OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */
+#define FTM_RD_SWOCTRL_CH7OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH7OCV_MASK) >> FTM_SWOCTRL_CH7OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH7OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OCV_SHIFT))
+
+/*! @brief Set the CH7OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH7OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH7OCV_MASK, FTM_SWOCTRL_CH7OCV(value)))
+#define FTM_BWR_SWOCTRL_CH7OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OCV_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_PWMLOAD - FTM PWM Load
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_PWMLOAD - FTM PWM Load (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
+ * values of their write buffers when the FTM counter changes from the MOD
+ * register value to its next value or when a channel (j) match occurs. A match occurs
+ * for the channel (j) when FTM counter = C(j)V.
+ */
+/*!
+ * @name Constants and macros for entire FTM_PWMLOAD register
+ */
+/*@{*/
+#define FTM_RD_PWMLOAD(base)     (FTM_PWMLOAD_REG(base))
+#define FTM_WR_PWMLOAD(base, value) (FTM_PWMLOAD_REG(base) = (value))
+#define FTM_RMW_PWMLOAD(base, mask, value) (FTM_WR_PWMLOAD(base, (FTM_RD_PWMLOAD(base) & ~(mask)) | (value)))
+#define FTM_SET_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) |  (value)))
+#define FTM_CLR_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) & ~(value)))
+#define FTM_TOG_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_PWMLOAD bitfields
+ */
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */
+#define FTM_RD_PWMLOAD_CH0SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH0SEL_MASK) >> FTM_PWMLOAD_CH0SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH0SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH0SEL_SHIFT))
+
+/*! @brief Set the CH0SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH0SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH0SEL_MASK, FTM_PWMLOAD_CH0SEL(value)))
+#define FTM_BWR_PWMLOAD_CH0SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH0SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */
+#define FTM_RD_PWMLOAD_CH1SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH1SEL_MASK) >> FTM_PWMLOAD_CH1SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH1SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH1SEL_SHIFT))
+
+/*! @brief Set the CH1SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH1SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH1SEL_MASK, FTM_PWMLOAD_CH1SEL(value)))
+#define FTM_BWR_PWMLOAD_CH1SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH1SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */
+#define FTM_RD_PWMLOAD_CH2SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH2SEL_MASK) >> FTM_PWMLOAD_CH2SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH2SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH2SEL_SHIFT))
+
+/*! @brief Set the CH2SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH2SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH2SEL_MASK, FTM_PWMLOAD_CH2SEL(value)))
+#define FTM_BWR_PWMLOAD_CH2SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH2SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */
+#define FTM_RD_PWMLOAD_CH3SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH3SEL_MASK) >> FTM_PWMLOAD_CH3SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH3SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH3SEL_SHIFT))
+
+/*! @brief Set the CH3SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH3SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH3SEL_MASK, FTM_PWMLOAD_CH3SEL(value)))
+#define FTM_BWR_PWMLOAD_CH3SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH3SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */
+#define FTM_RD_PWMLOAD_CH4SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH4SEL_MASK) >> FTM_PWMLOAD_CH4SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH4SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH4SEL_SHIFT))
+
+/*! @brief Set the CH4SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH4SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH4SEL_MASK, FTM_PWMLOAD_CH4SEL(value)))
+#define FTM_BWR_PWMLOAD_CH4SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH4SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */
+#define FTM_RD_PWMLOAD_CH5SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH5SEL_MASK) >> FTM_PWMLOAD_CH5SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH5SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH5SEL_SHIFT))
+
+/*! @brief Set the CH5SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH5SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH5SEL_MASK, FTM_PWMLOAD_CH5SEL(value)))
+#define FTM_BWR_PWMLOAD_CH5SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH5SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */
+#define FTM_RD_PWMLOAD_CH6SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH6SEL_MASK) >> FTM_PWMLOAD_CH6SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH6SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH6SEL_SHIFT))
+
+/*! @brief Set the CH6SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH6SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH6SEL_MASK, FTM_PWMLOAD_CH6SEL(value)))
+#define FTM_BWR_PWMLOAD_CH6SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH6SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */
+#define FTM_RD_PWMLOAD_CH7SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH7SEL_MASK) >> FTM_PWMLOAD_CH7SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH7SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH7SEL_SHIFT))
+
+/*! @brief Set the CH7SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH7SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH7SEL_MASK, FTM_PWMLOAD_CH7SEL(value)))
+#define FTM_BWR_PWMLOAD_CH7SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH7SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
+ *
+ * Enables the loading of the MOD, CNTIN, and CV registers with the values of
+ * their write buffers.
+ *
+ * Values:
+ * - 0b0 - Loading updated values is disabled.
+ * - 0b1 - Loading updated values is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */
+#define FTM_RD_PWMLOAD_LDOK(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_LDOK_MASK) >> FTM_PWMLOAD_LDOK_SHIFT)
+#define FTM_BRD_PWMLOAD_LDOK(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_LDOK_SHIFT))
+
+/*! @brief Set the LDOK field to a new value. */
+#define FTM_WR_PWMLOAD_LDOK(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_LDOK_MASK, FTM_PWMLOAD_LDOK(value)))
+#define FTM_BWR_PWMLOAD_LDOK(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_LDOK_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 GPIO
+ *
+ * General Purpose Input/Output
+ *
+ * Registers defined in this header file:
+ * - GPIO_PDOR - Port Data Output Register
+ * - GPIO_PSOR - Port Set Output Register
+ * - GPIO_PCOR - Port Clear Output Register
+ * - GPIO_PTOR - Port Toggle Output Register
+ * - GPIO_PDIR - Port Data Input Register
+ * - GPIO_PDDR - Port Data Direction Register
+ */
+
+#define GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
+#define GPIOA_IDX (0U) /*!< Instance number for GPIOA. */
+#define GPIOB_IDX (1U) /*!< Instance number for GPIOB. */
+#define GPIOC_IDX (2U) /*!< Instance number for GPIOC. */
+#define GPIOD_IDX (3U) /*!< Instance number for GPIOD. */
+#define GPIOE_IDX (4U) /*!< Instance number for GPIOE. */
+
+/*******************************************************************************
+ * GPIO_PDOR - Port Data Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDOR - Port Data Output Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the logic levels that are driven on each
+ * general-purpose output pins. Do not modify pin configuration registers associated with
+ * pins not available in your selected package. All unbonded pins not available in
+ * your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDOR register
+ */
+/*@{*/
+#define GPIO_RD_PDOR(base)       (GPIO_PDOR_REG(base))
+#define GPIO_WR_PDOR(base, value) (GPIO_PDOR_REG(base) = (value))
+#define GPIO_RMW_PDOR(base, mask, value) (GPIO_WR_PDOR(base, (GPIO_RD_PDOR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) |  (value)))
+#define GPIO_CLR_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) & ~(value)))
+#define GPIO_TOG_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PSOR - Port Set Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PSOR - Port Set Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to set the fields of the PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PSOR register
+ */
+/*@{*/
+#define GPIO_RD_PSOR(base)       (GPIO_PSOR_REG(base))
+#define GPIO_WR_PSOR(base, value) (GPIO_PSOR_REG(base) = (value))
+#define GPIO_RMW_PSOR(base, mask, value) (GPIO_WR_PSOR(base, (GPIO_RD_PSOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PCOR - Port Clear Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PCOR - Port Clear Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to clear the fields of PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PCOR register
+ */
+/*@{*/
+#define GPIO_RD_PCOR(base)       (GPIO_PCOR_REG(base))
+#define GPIO_WR_PCOR(base, value) (GPIO_PCOR_REG(base) = (value))
+#define GPIO_RMW_PCOR(base, mask, value) (GPIO_WR_PCOR(base, (GPIO_RD_PCOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PTOR - Port Toggle Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PTOR - Port Toggle Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PTOR register
+ */
+/*@{*/
+#define GPIO_RD_PTOR(base)       (GPIO_PTOR_REG(base))
+#define GPIO_WR_PTOR(base, value) (GPIO_PTOR_REG(base) = (value))
+#define GPIO_RMW_PTOR(base, mask, value) (GPIO_WR_PTOR(base, (GPIO_RD_PTOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDIR - Port Data Input Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDIR - Port Data Input Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Do not modify pin configuration registers associated with pins not available
+ * in your selected package. All unbonded pins not available in your package will
+ * default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDIR register
+ */
+/*@{*/
+#define GPIO_RD_PDIR(base)       (GPIO_PDIR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDDR - Port Data Direction Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDDR - Port Data Direction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The PDDR configures the individual port pins for input or output.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDDR register
+ */
+/*@{*/
+#define GPIO_RD_PDDR(base)       (GPIO_PDDR_REG(base))
+#define GPIO_WR_PDDR(base, value) (GPIO_PDDR_REG(base) = (value))
+#define GPIO_RMW_PDDR(base, mask, value) (GPIO_WR_PDDR(base, (GPIO_RD_PDDR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) |  (value)))
+#define GPIO_CLR_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) & ~(value)))
+#define GPIO_TOG_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 I2C
+ *
+ * Inter-Integrated Circuit
+ *
+ * Registers defined in this header file:
+ * - I2C_A1 - I2C Address Register 1
+ * - I2C_F - I2C Frequency Divider register
+ * - I2C_C1 - I2C Control Register 1
+ * - I2C_S - I2C Status register
+ * - I2C_D - I2C Data I/O register
+ * - I2C_C2 - I2C Control Register 2
+ * - I2C_FLT - I2C Programmable Input Glitch Filter register
+ * - I2C_RA - I2C Range Address register
+ * - I2C_SMB - I2C SMBus Control and Status register
+ * - I2C_A2 - I2C Address Register 2
+ * - I2C_SLTH - I2C SCL Low Timeout Register High
+ * - I2C_SLTL - I2C SCL Low Timeout Register Low
+ */
+
+#define I2C_INSTANCE_COUNT (3U) /*!< Number of instances of the I2C module. */
+#define I2C0_IDX (0U) /*!< Instance number for I2C0. */
+#define I2C1_IDX (1U) /*!< Instance number for I2C1. */
+#define I2C2_IDX (2U) /*!< Instance number for I2C2. */
+
+/*******************************************************************************
+ * I2C_A1 - I2C Address Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A1 - I2C Address Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the slave address to be used by the I2C module.
+ */
+/*!
+ * @name Constants and macros for entire I2C_A1 register
+ */
+/*@{*/
+#define I2C_RD_A1(base)          (I2C_A1_REG(base))
+#define I2C_WR_A1(base, value)   (I2C_A1_REG(base) = (value))
+#define I2C_RMW_A1(base, mask, value) (I2C_WR_A1(base, (I2C_RD_A1(base) & ~(mask)) | (value)))
+#define I2C_SET_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) |  (value)))
+#define I2C_CLR_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) & ~(value)))
+#define I2C_TOG_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A1 bitfields
+ */
+
+/*!
+ * @name Register I2C_A1, field AD[7:1] (RW)
+ *
+ * Contains the primary slave address used by the I2C module when it is
+ * addressed as a slave. This field is used in the 7-bit address scheme and the lower
+ * seven bits in the 10-bit address scheme.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A1_AD field. */
+#define I2C_RD_A1_AD(base)   ((I2C_A1_REG(base) & I2C_A1_AD_MASK) >> I2C_A1_AD_SHIFT)
+#define I2C_BRD_A1_AD(base)  (I2C_RD_A1_AD(base))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_A1_AD(base, value) (I2C_RMW_A1(base, I2C_A1_AD_MASK, I2C_A1_AD(value)))
+#define I2C_BWR_A1_AD(base, value) (I2C_WR_A1_AD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_F - I2C Frequency Divider register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_F - I2C Frequency Divider register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_F register
+ */
+/*@{*/
+#define I2C_RD_F(base)           (I2C_F_REG(base))
+#define I2C_WR_F(base, value)    (I2C_F_REG(base) = (value))
+#define I2C_RMW_F(base, mask, value) (I2C_WR_F(base, (I2C_RD_F(base) & ~(mask)) | (value)))
+#define I2C_SET_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) |  (value)))
+#define I2C_CLR_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) & ~(value)))
+#define I2C_TOG_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_F bitfields
+ */
+
+/*!
+ * @name Register I2C_F, field ICR[5:0] (RW)
+ *
+ * Prescales the I2C module clock for bit rate selection. This field and the
+ * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
+ * time, and the SCL stop hold time. For a list of values corresponding to each ICR
+ * setting, see I2C divider and hold values. The SCL divider multiplied by
+ * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
+ * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
+ * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
+ * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
+ * the delay from the falling edge of SDA (I2C data) while SCL is high (start
+ * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
+ * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
+ * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
+ * data) while SCL is high (stop condition). SCL stop hold time = I2C module
+ * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
+ * speed is 8 MHz, the following table shows the possible hold time values with
+ * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
+ * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h
+ * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
+ * 1.125 4.750 5.125
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_ICR field. */
+#define I2C_RD_F_ICR(base)   ((I2C_F_REG(base) & I2C_F_ICR_MASK) >> I2C_F_ICR_SHIFT)
+#define I2C_BRD_F_ICR(base)  (I2C_RD_F_ICR(base))
+
+/*! @brief Set the ICR field to a new value. */
+#define I2C_WR_F_ICR(base, value) (I2C_RMW_F(base, I2C_F_ICR_MASK, I2C_F_ICR(value)))
+#define I2C_BWR_F_ICR(base, value) (I2C_WR_F_ICR(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_F, field MULT[7:6] (RW)
+ *
+ * Defines the multiplier factor (mul). This factor is used along with the SCL
+ * divider to generate the I2C baud rate.
+ *
+ * Values:
+ * - 0b00 - mul = 1
+ * - 0b01 - mul = 2
+ * - 0b10 - mul = 4
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_MULT field. */
+#define I2C_RD_F_MULT(base)  ((I2C_F_REG(base) & I2C_F_MULT_MASK) >> I2C_F_MULT_SHIFT)
+#define I2C_BRD_F_MULT(base) (I2C_RD_F_MULT(base))
+
+/*! @brief Set the MULT field to a new value. */
+#define I2C_WR_F_MULT(base, value) (I2C_RMW_F(base, I2C_F_MULT_MASK, I2C_F_MULT(value)))
+#define I2C_BWR_F_MULT(base, value) (I2C_WR_F_MULT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C1 - I2C Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C1 - I2C Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C1 register
+ */
+/*@{*/
+#define I2C_RD_C1(base)          (I2C_C1_REG(base))
+#define I2C_WR_C1(base, value)   (I2C_C1_REG(base) = (value))
+#define I2C_RMW_C1(base, mask, value) (I2C_WR_C1(base, (I2C_RD_C1(base) & ~(mask)) | (value)))
+#define I2C_SET_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) |  (value)))
+#define I2C_CLR_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) & ~(value)))
+#define I2C_TOG_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C1 bitfields
+ */
+
+/*!
+ * @name Register I2C_C1, field DMAEN[0] (RW)
+ *
+ * Enables or disables the DMA function.
+ *
+ * Values:
+ * - 0b0 - All DMA signalling disabled.
+ * - 0b1 - DMA transfer is enabled. While SMB[FACK] = 0, the following
+ *     conditions trigger the DMA request: a data byte is received, and either address or
+ *     data is transmitted. (ACK/NACK is automatic) the first byte received
+ *     matches the A1 register or is a general call address. If any address matching
+ *     occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
+ *     from master to slave, then it is not required to check S[SRW]. With this
+ *     assumption, DMA can also be used in this case. In other cases, if the master
+ *     reads data from the slave, then it is required to rewrite the C1 register
+ *     operation. With this assumption, DMA cannot be used. When FACK = 1, an
+ *     address or a data byte is transmitted.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_DMAEN field. */
+#define I2C_RD_C1_DMAEN(base) ((I2C_C1_REG(base) & I2C_C1_DMAEN_MASK) >> I2C_C1_DMAEN_SHIFT)
+#define I2C_BRD_C1_DMAEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define I2C_WR_C1_DMAEN(base, value) (I2C_RMW_C1(base, I2C_C1_DMAEN_MASK, I2C_C1_DMAEN(value)))
+#define I2C_BWR_C1_DMAEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field WUEN[1] (RW)
+ *
+ * The I2C module can wake the MCU from low power mode with no peripheral bus
+ * running when slave address matching occurs.
+ *
+ * Values:
+ * - 0b0 - Normal operation. No interrupt generated when address matching in low
+ *     power mode.
+ * - 0b1 - Enables the wakeup function in low power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_WUEN field. */
+#define I2C_RD_C1_WUEN(base) ((I2C_C1_REG(base) & I2C_C1_WUEN_MASK) >> I2C_C1_WUEN_SHIFT)
+#define I2C_BRD_C1_WUEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT))
+
+/*! @brief Set the WUEN field to a new value. */
+#define I2C_WR_C1_WUEN(base, value) (I2C_RMW_C1(base, I2C_C1_WUEN_MASK, I2C_C1_WUEN(value)))
+#define I2C_BWR_C1_WUEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field RSTA[2] (WORZ)
+ *
+ * Writing 1 to this bit generates a repeated START condition provided it is the
+ * current master. This bit will always be read as 0. Attempting a repeat at the
+ * wrong time results in loss of arbitration.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define I2C_WR_C1_RSTA(base, value) (I2C_RMW_C1(base, I2C_C1_RSTA_MASK, I2C_C1_RSTA(value)))
+#define I2C_BWR_C1_RSTA(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_RSTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TXAK[3] (RW)
+ *
+ * Specifies the value driven onto the SDA during data acknowledge cycles for
+ * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
+ * generation. SCL is held low until TXAK is written.
+ *
+ * Values:
+ * - 0b0 - An acknowledge signal is sent to the bus on the following receiving
+ *     byte (if FACK is cleared) or the current receiving byte (if FACK is set).
+ * - 0b1 - No acknowledge signal is sent to the bus on the following receiving
+ *     data byte (if FACK is cleared) or the current receiving data byte (if FACK
+ *     is set).
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TXAK field. */
+#define I2C_RD_C1_TXAK(base) ((I2C_C1_REG(base) & I2C_C1_TXAK_MASK) >> I2C_C1_TXAK_SHIFT)
+#define I2C_BRD_C1_TXAK(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT))
+
+/*! @brief Set the TXAK field to a new value. */
+#define I2C_WR_C1_TXAK(base, value) (I2C_RMW_C1(base, I2C_C1_TXAK_MASK, I2C_C1_TXAK(value)))
+#define I2C_BWR_C1_TXAK(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TX[4] (RW)
+ *
+ * Selects the direction of master and slave transfers. In master mode this bit
+ * must be set according to the type of transfer required. Therefore, for address
+ * cycles, this bit is always set. When addressed as a slave this bit must be
+ * set by software according to the SRW bit in the status register.
+ *
+ * Values:
+ * - 0b0 - Receive
+ * - 0b1 - Transmit
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TX field. */
+#define I2C_RD_C1_TX(base)   ((I2C_C1_REG(base) & I2C_C1_TX_MASK) >> I2C_C1_TX_SHIFT)
+#define I2C_BRD_C1_TX(base)  (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT))
+
+/*! @brief Set the TX field to a new value. */
+#define I2C_WR_C1_TX(base, value) (I2C_RMW_C1(base, I2C_C1_TX_MASK, I2C_C1_TX(value)))
+#define I2C_BWR_C1_TX(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field MST[5] (RW)
+ *
+ * When MST is changed from 0 to 1, a START signal is generated on the bus and
+ * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
+ * generated and the mode of operation changes from master to slave.
+ *
+ * Values:
+ * - 0b0 - Slave mode
+ * - 0b1 - Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_MST field. */
+#define I2C_RD_C1_MST(base)  ((I2C_C1_REG(base) & I2C_C1_MST_MASK) >> I2C_C1_MST_SHIFT)
+#define I2C_BRD_C1_MST(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT))
+
+/*! @brief Set the MST field to a new value. */
+#define I2C_WR_C1_MST(base, value) (I2C_RMW_C1(base, I2C_C1_MST_MASK, I2C_C1_MST(value)))
+#define I2C_BWR_C1_MST(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICIE[6] (RW)
+ *
+ * Enables I2C interrupt requests.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICIE field. */
+#define I2C_RD_C1_IICIE(base) ((I2C_C1_REG(base) & I2C_C1_IICIE_MASK) >> I2C_C1_IICIE_SHIFT)
+#define I2C_BRD_C1_IICIE(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT))
+
+/*! @brief Set the IICIE field to a new value. */
+#define I2C_WR_C1_IICIE(base, value) (I2C_RMW_C1(base, I2C_C1_IICIE_MASK, I2C_C1_IICIE(value)))
+#define I2C_BWR_C1_IICIE(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICEN[7] (RW)
+ *
+ * Enables I2C module operation.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICEN field. */
+#define I2C_RD_C1_IICEN(base) ((I2C_C1_REG(base) & I2C_C1_IICEN_MASK) >> I2C_C1_IICEN_SHIFT)
+#define I2C_BRD_C1_IICEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT))
+
+/*! @brief Set the IICEN field to a new value. */
+#define I2C_WR_C1_IICEN(base, value) (I2C_RMW_C1(base, I2C_C1_IICEN_MASK, I2C_C1_IICEN(value)))
+#define I2C_BWR_C1_IICEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_S - I2C Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_S - I2C Status register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire I2C_S register
+ */
+/*@{*/
+#define I2C_RD_S(base)           (I2C_S_REG(base))
+#define I2C_WR_S(base, value)    (I2C_S_REG(base) = (value))
+#define I2C_RMW_S(base, mask, value) (I2C_WR_S(base, (I2C_RD_S(base) & ~(mask)) | (value)))
+#define I2C_SET_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) |  (value)))
+#define I2C_CLR_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) & ~(value)))
+#define I2C_TOG_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_S bitfields
+ */
+
+/*!
+ * @name Register I2C_S, field RXAK[0] (RO)
+ *
+ * Values:
+ * - 0b0 - Acknowledge signal was received after the completion of one byte of
+ *     data transmission on the bus
+ * - 0b1 - No acknowledge signal detected
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RXAK field. */
+#define I2C_RD_S_RXAK(base)  ((I2C_S_REG(base) & I2C_S_RXAK_MASK) >> I2C_S_RXAK_SHIFT)
+#define I2C_BRD_S_RXAK(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RXAK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IICIF[1] (W1C)
+ *
+ * This bit sets when an interrupt is pending. This bit must be cleared by
+ * software by writing 1 to it, such as in the interrupt routine. One of the following
+ * events can set this bit: One byte transfer, including ACK/NACK bit, completes
+ * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
+ * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
+ * completes if FACK is 1. Match of slave address to calling address including
+ * primary slave address, range slave address , alert response address, second
+ * slave address, or general call address. Arbitration lost In SMBus mode, any
+ * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
+ * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
+ * start detection interrupt: In the interrupt service routine, first clear the
+ * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
+ * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
+ * asserted again.
+ *
+ * Values:
+ * - 0b0 - No interrupt pending
+ * - 0b1 - Interrupt pending
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IICIF field. */
+#define I2C_RD_S_IICIF(base) ((I2C_S_REG(base) & I2C_S_IICIF_MASK) >> I2C_S_IICIF_SHIFT)
+#define I2C_BRD_S_IICIF(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT))
+
+/*! @brief Set the IICIF field to a new value. */
+#define I2C_WR_S_IICIF(base, value) (I2C_RMW_S(base, (I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IICIF(value)))
+#define I2C_BWR_S_IICIF(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field SRW[2] (RO)
+ *
+ * When addressed as a slave, SRW indicates the value of the R/W command bit of
+ * the calling address sent to the master.
+ *
+ * Values:
+ * - 0b0 - Slave receive, master writing to slave
+ * - 0b1 - Slave transmit, master reading from slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_SRW field. */
+#define I2C_RD_S_SRW(base)   ((I2C_S_REG(base) & I2C_S_SRW_MASK) >> I2C_S_SRW_SHIFT)
+#define I2C_BRD_S_SRW(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_SRW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field RAM[3] (RW)
+ *
+ * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
+ * Any nonzero calling address is received that matches the address in the RA
+ * register. The calling address is within the range of values of the A1 and RA
+ * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
+ * Writing the C1 register with any value clears this bit to 0.
+ *
+ * Values:
+ * - 0b0 - Not addressed
+ * - 0b1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RAM field. */
+#define I2C_RD_S_RAM(base)   ((I2C_S_REG(base) & I2C_S_RAM_MASK) >> I2C_S_RAM_SHIFT)
+#define I2C_BRD_S_RAM(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RAM_SHIFT))
+
+/*! @brief Set the RAM field to a new value. */
+#define I2C_WR_S_RAM(base, value) (I2C_RMW_S(base, (I2C_S_RAM_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_RAM(value)))
+#define I2C_BWR_S_RAM(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RAM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field ARBL[4] (W1C)
+ *
+ * This bit is set by hardware when the arbitration procedure is lost. The ARBL
+ * bit must be cleared by software, by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - Standard bus operation.
+ * - 0b1 - Loss of arbitration.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_ARBL field. */
+#define I2C_RD_S_ARBL(base)  ((I2C_S_REG(base) & I2C_S_ARBL_MASK) >> I2C_S_ARBL_SHIFT)
+#define I2C_BRD_S_ARBL(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT))
+
+/*! @brief Set the ARBL field to a new value. */
+#define I2C_WR_S_ARBL(base, value) (I2C_RMW_S(base, (I2C_S_ARBL_MASK | I2C_S_IICIF_MASK), I2C_S_ARBL(value)))
+#define I2C_BWR_S_ARBL(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field BUSY[5] (RO)
+ *
+ * Indicates the status of the bus regardless of slave or master mode. This bit
+ * is set when a START signal is detected and cleared when a STOP signal is
+ * detected.
+ *
+ * Values:
+ * - 0b0 - Bus is idle
+ * - 0b1 - Bus is busy
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_BUSY field. */
+#define I2C_RD_S_BUSY(base)  ((I2C_S_REG(base) & I2C_S_BUSY_MASK) >> I2C_S_BUSY_SHIFT)
+#define I2C_BRD_S_BUSY(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_BUSY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IAAS[6] (RW)
+ *
+ * This bit is set by one of the following conditions: The calling address
+ * matches the programmed primary slave address in the A1 register, or matches the
+ * range address in the RA register (which must be set to a nonzero value and under
+ * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
+ * received. SMB[SIICAEN] is set and the calling address matches the second programmed
+ * slave address. ALERTEN is set and an SMBus alert response address is received
+ * RMEN is set and an address is received that is within the range between the
+ * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
+ * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
+ * value clears this bit.
+ *
+ * Values:
+ * - 0b0 - Not addressed
+ * - 0b1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IAAS field. */
+#define I2C_RD_S_IAAS(base)  ((I2C_S_REG(base) & I2C_S_IAAS_MASK) >> I2C_S_IAAS_SHIFT)
+#define I2C_BRD_S_IAAS(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT))
+
+/*! @brief Set the IAAS field to a new value. */
+#define I2C_WR_S_IAAS(base, value) (I2C_RMW_S(base, (I2C_S_IAAS_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IAAS(value)))
+#define I2C_BWR_S_IAAS(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field TCF[7] (RO)
+ *
+ * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
+ * This bit is valid only during or immediately following a transfer to or from
+ * the I2C module. TCF is cleared by reading the I2C data register in receive mode
+ * or by writing to the I2C data register in transmit mode.
+ *
+ * Values:
+ * - 0b0 - Transfer in progress
+ * - 0b1 - Transfer complete
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_TCF field. */
+#define I2C_RD_S_TCF(base)   ((I2C_S_REG(base) & I2C_S_TCF_MASK) >> I2C_S_TCF_SHIFT)
+#define I2C_BRD_S_TCF(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_TCF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_D - I2C Data I/O register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_D - I2C Data I/O register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_D register
+ */
+/*@{*/
+#define I2C_RD_D(base)           (I2C_D_REG(base))
+#define I2C_WR_D(base, value)    (I2C_D_REG(base) = (value))
+#define I2C_RMW_D(base, mask, value) (I2C_WR_D(base, (I2C_RD_D(base) & ~(mask)) | (value)))
+#define I2C_SET_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) |  (value)))
+#define I2C_CLR_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) & ~(value)))
+#define I2C_TOG_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C2 - I2C Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C2 - I2C Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C2 register
+ */
+/*@{*/
+#define I2C_RD_C2(base)          (I2C_C2_REG(base))
+#define I2C_WR_C2(base, value)   (I2C_C2_REG(base) = (value))
+#define I2C_RMW_C2(base, mask, value) (I2C_WR_C2(base, (I2C_RD_C2(base) & ~(mask)) | (value)))
+#define I2C_SET_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) |  (value)))
+#define I2C_CLR_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) & ~(value)))
+#define I2C_TOG_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C2 bitfields
+ */
+
+/*!
+ * @name Register I2C_C2, field AD[2:0] (RW)
+ *
+ * Contains the upper three bits of the slave address in the 10-bit address
+ * scheme. This field is valid only while the ADEXT bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_AD field. */
+#define I2C_RD_C2_AD(base)   ((I2C_C2_REG(base) & I2C_C2_AD_MASK) >> I2C_C2_AD_SHIFT)
+#define I2C_BRD_C2_AD(base)  (I2C_RD_C2_AD(base))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_C2_AD(base, value) (I2C_RMW_C2(base, I2C_C2_AD_MASK, I2C_C2_AD(value)))
+#define I2C_BWR_C2_AD(base, value) (I2C_WR_C2_AD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field RMEN[3] (RW)
+ *
+ * This bit controls the slave address matching for addresses between the values
+ * of the A1 and RA registers. When this bit is set, a slave address matching
+ * occurs for any address greater than the value of the A1 register and less than
+ * or equal to the value of the RA register.
+ *
+ * Values:
+ * - 0b0 - Range mode disabled. No address matching occurs for an address within
+ *     the range of values of the A1 and RA registers.
+ * - 0b1 - Range mode enabled. Address matching occurs when a slave receives an
+ *     address within the range of values of the A1 and RA registers.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_RMEN field. */
+#define I2C_RD_C2_RMEN(base) ((I2C_C2_REG(base) & I2C_C2_RMEN_MASK) >> I2C_C2_RMEN_SHIFT)
+#define I2C_BRD_C2_RMEN(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT))
+
+/*! @brief Set the RMEN field to a new value. */
+#define I2C_WR_C2_RMEN(base, value) (I2C_RMW_C2(base, I2C_C2_RMEN_MASK, I2C_C2_RMEN(value)))
+#define I2C_BWR_C2_RMEN(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field SBRC[4] (RW)
+ *
+ * Enables independent slave mode baud rate at maximum frequency, which forces
+ * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
+ * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
+ * capture the master's data at only 10 kbit/s.
+ *
+ * Values:
+ * - 0b0 - The slave baud rate follows the master baud rate and clock stretching
+ *     may occur
+ * - 0b1 - Slave baud rate is independent of the master baud rate
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_SBRC field. */
+#define I2C_RD_C2_SBRC(base) ((I2C_C2_REG(base) & I2C_C2_SBRC_MASK) >> I2C_C2_SBRC_SHIFT)
+#define I2C_BRD_C2_SBRC(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT))
+
+/*! @brief Set the SBRC field to a new value. */
+#define I2C_WR_C2_SBRC(base, value) (I2C_RMW_C2(base, I2C_C2_SBRC_MASK, I2C_C2_SBRC(value)))
+#define I2C_BWR_C2_SBRC(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field HDRS[5] (RW)
+ *
+ * Controls the drive capability of the I2C pads.
+ *
+ * Values:
+ * - 0b0 - Normal drive mode
+ * - 0b1 - High drive mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_HDRS field. */
+#define I2C_RD_C2_HDRS(base) ((I2C_C2_REG(base) & I2C_C2_HDRS_MASK) >> I2C_C2_HDRS_SHIFT)
+#define I2C_BRD_C2_HDRS(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT))
+
+/*! @brief Set the HDRS field to a new value. */
+#define I2C_WR_C2_HDRS(base, value) (I2C_RMW_C2(base, I2C_C2_HDRS_MASK, I2C_C2_HDRS(value)))
+#define I2C_BWR_C2_HDRS(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field ADEXT[6] (RW)
+ *
+ * Controls the number of bits used for the slave address.
+ *
+ * Values:
+ * - 0b0 - 7-bit address scheme
+ * - 0b1 - 10-bit address scheme
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_ADEXT field. */
+#define I2C_RD_C2_ADEXT(base) ((I2C_C2_REG(base) & I2C_C2_ADEXT_MASK) >> I2C_C2_ADEXT_SHIFT)
+#define I2C_BRD_C2_ADEXT(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT))
+
+/*! @brief Set the ADEXT field to a new value. */
+#define I2C_WR_C2_ADEXT(base, value) (I2C_RMW_C2(base, I2C_C2_ADEXT_MASK, I2C_C2_ADEXT(value)))
+#define I2C_BWR_C2_ADEXT(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field GCAEN[7] (RW)
+ *
+ * Enables general call address.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_GCAEN field. */
+#define I2C_RD_C2_GCAEN(base) ((I2C_C2_REG(base) & I2C_C2_GCAEN_MASK) >> I2C_C2_GCAEN_SHIFT)
+#define I2C_BRD_C2_GCAEN(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT))
+
+/*! @brief Set the GCAEN field to a new value. */
+#define I2C_WR_C2_GCAEN(base, value) (I2C_RMW_C2(base, I2C_C2_GCAEN_MASK, I2C_C2_GCAEN(value)))
+#define I2C_BWR_C2_GCAEN(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_FLT - I2C Programmable Input Glitch Filter register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_FLT register
+ */
+/*@{*/
+#define I2C_RD_FLT(base)         (I2C_FLT_REG(base))
+#define I2C_WR_FLT(base, value)  (I2C_FLT_REG(base) = (value))
+#define I2C_RMW_FLT(base, mask, value) (I2C_WR_FLT(base, (I2C_RD_FLT(base) & ~(mask)) | (value)))
+#define I2C_SET_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) |  (value)))
+#define I2C_CLR_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) & ~(value)))
+#define I2C_TOG_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_FLT bitfields
+ */
+
+/*!
+ * @name Register I2C_FLT, field FLT[3:0] (RW)
+ *
+ * Controls the width of the glitch, in terms of I2C module clock cycles, that
+ * the filter must absorb. For any glitch whose size is less than or equal to this
+ * width setting, the filter does not allow the glitch to pass.
+ *
+ * Values:
+ * - 0b0000 - No filter/bypass
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_FLT field. */
+#define I2C_RD_FLT_FLT(base) ((I2C_FLT_REG(base) & I2C_FLT_FLT_MASK) >> I2C_FLT_FLT_SHIFT)
+#define I2C_BRD_FLT_FLT(base) (I2C_RD_FLT_FLT(base))
+
+/*! @brief Set the FLT field to a new value. */
+#define I2C_WR_FLT_FLT(base, value) (I2C_RMW_FLT(base, (I2C_FLT_FLT_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_FLT(value)))
+#define I2C_BWR_FLT_FLT(base, value) (I2C_WR_FLT_FLT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STARTF[4] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's start status is detected. The
+ * STARTF bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No start happens on I2C bus
+ * - 0b1 - Start detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STARTF field. */
+#define I2C_RD_FLT_STARTF(base) ((I2C_FLT_REG(base) & I2C_FLT_STARTF_MASK) >> I2C_FLT_STARTF_SHIFT)
+#define I2C_BRD_FLT_STARTF(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT))
+
+/*! @brief Set the STARTF field to a new value. */
+#define I2C_WR_FLT_STARTF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_STARTF(value)))
+#define I2C_BWR_FLT_STARTF(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SSIE[5] (RW)
+ *
+ * This bit enables the interrupt for I2C bus stop or start detection. To clear
+ * the I2C bus stop or start detection interrupt: In the interrupt service
+ * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
+ * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
+ * is asserted again.
+ *
+ * Values:
+ * - 0b0 - Stop or start detection interrupt is disabled
+ * - 0b1 - Stop or start detection interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SSIE field. */
+#define I2C_RD_FLT_SSIE(base) ((I2C_FLT_REG(base) & I2C_FLT_SSIE_MASK) >> I2C_FLT_SSIE_SHIFT)
+#define I2C_BRD_FLT_SSIE(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT))
+
+/*! @brief Set the SSIE field to a new value. */
+#define I2C_WR_FLT_SSIE(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SSIE_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SSIE(value)))
+#define I2C_BWR_FLT_SSIE(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STOPF[6] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
+ * bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No stop happens on I2C bus
+ * - 0b1 - Stop detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STOPF field. */
+#define I2C_RD_FLT_STOPF(base) ((I2C_FLT_REG(base) & I2C_FLT_STOPF_MASK) >> I2C_FLT_STOPF_SHIFT)
+#define I2C_BRD_FLT_STOPF(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT))
+
+/*! @brief Set the STOPF field to a new value. */
+#define I2C_WR_FLT_STOPF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK), I2C_FLT_STOPF(value)))
+#define I2C_BWR_FLT_STOPF(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SHEN[7] (RW)
+ *
+ * Set this bit to hold off entry to stop mode when any data transmission or
+ * reception is occurring. The following scenario explains the holdoff
+ * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
+ * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
+ * byte currently being transferred, including both address and data, completes
+ * its transfer. The I2C slave or master acknowledges that the in-transfer byte
+ * completed its transfer and acknowledges the request to enter stop mode. After
+ * receiving the I2C module's acknowledgment of the request to enter stop mode,
+ * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
+ * is set to 1 and the I2C module is in an idle or disabled state when the MCU
+ * signals to enter stop mode, the module immediately acknowledges the request to
+ * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
+ * reception that was suspended by stop mode entry was incomplete: To resume the
+ * overall transmission or reception after the MCU exits stop mode, software must
+ * reinitialize the transfer by resending the address of the slave. If the I2C
+ * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
+ * system software will receive the interrupt triggered by the I2C Status Register's
+ * TCF bit after the MCU wakes from the stop mode.
+ *
+ * Values:
+ * - 0b0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
+ * - 0b1 - Stop holdoff is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SHEN field. */
+#define I2C_RD_FLT_SHEN(base) ((I2C_FLT_REG(base) & I2C_FLT_SHEN_MASK) >> I2C_FLT_SHEN_SHIFT)
+#define I2C_BRD_FLT_SHEN(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT))
+
+/*! @brief Set the SHEN field to a new value. */
+#define I2C_WR_FLT_SHEN(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SHEN_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SHEN(value)))
+#define I2C_BWR_FLT_SHEN(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_RA - I2C Range Address register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_RA - I2C Range Address register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_RA register
+ */
+/*@{*/
+#define I2C_RD_RA(base)          (I2C_RA_REG(base))
+#define I2C_WR_RA(base, value)   (I2C_RA_REG(base) = (value))
+#define I2C_RMW_RA(base, mask, value) (I2C_WR_RA(base, (I2C_RD_RA(base) & ~(mask)) | (value)))
+#define I2C_SET_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) |  (value)))
+#define I2C_CLR_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) & ~(value)))
+#define I2C_TOG_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_RA bitfields
+ */
+
+/*!
+ * @name Register I2C_RA, field RAD[7:1] (RW)
+ *
+ * This field contains the slave address to be used by the I2C module. The field
+ * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
+ * value write enables this register. This register value can be considered as a
+ * maximum boundary in the range matching mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_RA_RAD field. */
+#define I2C_RD_RA_RAD(base)  ((I2C_RA_REG(base) & I2C_RA_RAD_MASK) >> I2C_RA_RAD_SHIFT)
+#define I2C_BRD_RA_RAD(base) (I2C_RD_RA_RAD(base))
+
+/*! @brief Set the RAD field to a new value. */
+#define I2C_WR_RA_RAD(base, value) (I2C_RMW_RA(base, I2C_RA_RAD_MASK, I2C_RA_RAD(value)))
+#define I2C_BWR_RA_RAD(base, value) (I2C_WR_RA_RAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SMB - I2C SMBus Control and Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SMB - I2C SMBus Control and Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When the SCL and SDA signals are held high for a length of time greater than
+ * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
+ * while the system is detecting how long these signals are being held high, a
+ * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
+ * bus transmission process with the idle bus state. When the TCKSEL bit is set,
+ * there is no need to monitor the SHTF1 bit because the bus speed is too high to
+ * match the protocol of SMBus.
+ */
+/*!
+ * @name Constants and macros for entire I2C_SMB register
+ */
+/*@{*/
+#define I2C_RD_SMB(base)         (I2C_SMB_REG(base))
+#define I2C_WR_SMB(base, value)  (I2C_SMB_REG(base) = (value))
+#define I2C_RMW_SMB(base, mask, value) (I2C_WR_SMB(base, (I2C_RD_SMB(base) & ~(mask)) | (value)))
+#define I2C_SET_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) |  (value)))
+#define I2C_CLR_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) & ~(value)))
+#define I2C_TOG_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_SMB bitfields
+ */
+
+/*!
+ * @name Register I2C_SMB, field SHTF2IE[0] (RW)
+ *
+ * Enables SCL high and SDA low timeout interrupt.
+ *
+ * Values:
+ * - 0b0 - SHTF2 interrupt is disabled
+ * - 0b1 - SHTF2 interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2IE field. */
+#define I2C_RD_SMB_SHTF2IE(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2IE_MASK) >> I2C_SMB_SHTF2IE_SHIFT)
+#define I2C_BRD_SMB_SHTF2IE(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT))
+
+/*! @brief Set the SHTF2IE field to a new value. */
+#define I2C_WR_SMB_SHTF2IE(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2IE_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2IE(value)))
+#define I2C_BWR_SMB_SHTF2IE(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF2[1] (W1C)
+ *
+ * This bit sets when SCL is held high and SDA is held low more than clock *
+ * LoValue / 512. Software clears this bit by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No SCL high and SDA low timeout occurs
+ * - 0b1 - SCL high and SDA low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2 field. */
+#define I2C_RD_SMB_SHTF2(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2_MASK) >> I2C_SMB_SHTF2_SHIFT)
+#define I2C_BRD_SMB_SHTF2(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT))
+
+/*! @brief Set the SHTF2 field to a new value. */
+#define I2C_WR_SMB_SHTF2(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2(value)))
+#define I2C_BWR_SMB_SHTF2(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF1[2] (RO)
+ *
+ * This read-only bit sets when SCL and SDA are held high more than clock *
+ * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
+ *
+ * Values:
+ * - 0b0 - No SCL high and SDA high timeout occurs
+ * - 0b1 - SCL high and SDA high timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF1 field. */
+#define I2C_RD_SMB_SHTF1(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF1_MASK) >> I2C_SMB_SHTF1_SHIFT)
+#define I2C_BRD_SMB_SHTF1(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SLTF[3] (W1C)
+ *
+ * This bit is set when the SLT register (consisting of the SLTH and SLTL
+ * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
+ * Software clears this bit by writing a logic 1 to it. The low timeout function
+ * is disabled when the SLT register's value is 0.
+ *
+ * Values:
+ * - 0b0 - No low timeout occurs
+ * - 0b1 - Low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SLTF field. */
+#define I2C_RD_SMB_SLTF(base) ((I2C_SMB_REG(base) & I2C_SMB_SLTF_MASK) >> I2C_SMB_SLTF_SHIFT)
+#define I2C_BRD_SMB_SLTF(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT))
+
+/*! @brief Set the SLTF field to a new value. */
+#define I2C_WR_SMB_SLTF(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SLTF_MASK | I2C_SMB_SHTF2_MASK), I2C_SMB_SLTF(value)))
+#define I2C_BWR_SMB_SLTF(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field TCKSEL[4] (RW)
+ *
+ * Selects the clock source of the timeout counter.
+ *
+ * Values:
+ * - 0b0 - Timeout counter counts at the frequency of the I2C module clock / 64
+ * - 0b1 - Timeout counter counts at the frequency of the I2C module clock
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_TCKSEL field. */
+#define I2C_RD_SMB_TCKSEL(base) ((I2C_SMB_REG(base) & I2C_SMB_TCKSEL_MASK) >> I2C_SMB_TCKSEL_SHIFT)
+#define I2C_BRD_SMB_TCKSEL(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT))
+
+/*! @brief Set the TCKSEL field to a new value. */
+#define I2C_WR_SMB_TCKSEL(base, value) (I2C_RMW_SMB(base, (I2C_SMB_TCKSEL_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_TCKSEL(value)))
+#define I2C_BWR_SMB_TCKSEL(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SIICAEN[5] (RW)
+ *
+ * Enables or disables SMBus device default address.
+ *
+ * Values:
+ * - 0b0 - I2C address register 2 matching is disabled
+ * - 0b1 - I2C address register 2 matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SIICAEN field. */
+#define I2C_RD_SMB_SIICAEN(base) ((I2C_SMB_REG(base) & I2C_SMB_SIICAEN_MASK) >> I2C_SMB_SIICAEN_SHIFT)
+#define I2C_BRD_SMB_SIICAEN(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT))
+
+/*! @brief Set the SIICAEN field to a new value. */
+#define I2C_WR_SMB_SIICAEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SIICAEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SIICAEN(value)))
+#define I2C_BWR_SMB_SIICAEN(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field ALERTEN[6] (RW)
+ *
+ * Enables or disables SMBus alert response address matching. After the host
+ * responds to a device that used the alert response address, you must use software
+ * to put the device's address on the bus. The alert protocol is described in the
+ * SMBus specification.
+ *
+ * Values:
+ * - 0b0 - SMBus alert response address matching is disabled
+ * - 0b1 - SMBus alert response address matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_ALERTEN field. */
+#define I2C_RD_SMB_ALERTEN(base) ((I2C_SMB_REG(base) & I2C_SMB_ALERTEN_MASK) >> I2C_SMB_ALERTEN_SHIFT)
+#define I2C_BRD_SMB_ALERTEN(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT))
+
+/*! @brief Set the ALERTEN field to a new value. */
+#define I2C_WR_SMB_ALERTEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_ALERTEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_ALERTEN(value)))
+#define I2C_BWR_SMB_ALERTEN(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field FACK[7] (RW)
+ *
+ * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
+ * according to the result of receiving data byte.
+ *
+ * Values:
+ * - 0b0 - An ACK or NACK is sent on the following receiving data byte
+ * - 0b1 - Writing 0 to TXAK after receiving a data byte generates an ACK.
+ *     Writing 1 to TXAK after receiving a data byte generates a NACK.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_FACK field. */
+#define I2C_RD_SMB_FACK(base) ((I2C_SMB_REG(base) & I2C_SMB_FACK_MASK) >> I2C_SMB_FACK_SHIFT)
+#define I2C_BRD_SMB_FACK(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT))
+
+/*! @brief Set the FACK field to a new value. */
+#define I2C_WR_SMB_FACK(base, value) (I2C_RMW_SMB(base, (I2C_SMB_FACK_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_FACK(value)))
+#define I2C_BWR_SMB_FACK(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_A2 - I2C Address Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A2 - I2C Address Register 2 (RW)
+ *
+ * Reset value: 0xC2U
+ */
+/*!
+ * @name Constants and macros for entire I2C_A2 register
+ */
+/*@{*/
+#define I2C_RD_A2(base)          (I2C_A2_REG(base))
+#define I2C_WR_A2(base, value)   (I2C_A2_REG(base) = (value))
+#define I2C_RMW_A2(base, mask, value) (I2C_WR_A2(base, (I2C_RD_A2(base) & ~(mask)) | (value)))
+#define I2C_SET_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) |  (value)))
+#define I2C_CLR_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) & ~(value)))
+#define I2C_TOG_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A2 bitfields
+ */
+
+/*!
+ * @name Register I2C_A2, field SAD[7:1] (RW)
+ *
+ * Contains the slave address used by the SMBus. This field is used on the
+ * device default address or other related addresses.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A2_SAD field. */
+#define I2C_RD_A2_SAD(base)  ((I2C_A2_REG(base) & I2C_A2_SAD_MASK) >> I2C_A2_SAD_SHIFT)
+#define I2C_BRD_A2_SAD(base) (I2C_RD_A2_SAD(base))
+
+/*! @brief Set the SAD field to a new value. */
+#define I2C_WR_A2_SAD(base, value) (I2C_RMW_A2(base, I2C_A2_SAD_MASK, I2C_A2_SAD(value)))
+#define I2C_BWR_A2_SAD(base, value) (I2C_WR_A2_SAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTH - I2C SCL Low Timeout Register High
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTH - I2C SCL Low Timeout Register High (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTH register
+ */
+/*@{*/
+#define I2C_RD_SLTH(base)        (I2C_SLTH_REG(base))
+#define I2C_WR_SLTH(base, value) (I2C_SLTH_REG(base) = (value))
+#define I2C_RMW_SLTH(base, mask, value) (I2C_WR_SLTH(base, (I2C_RD_SLTH(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) |  (value)))
+#define I2C_CLR_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) & ~(value)))
+#define I2C_TOG_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTL - I2C SCL Low Timeout Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTL register
+ */
+/*@{*/
+#define I2C_RD_SLTL(base)        (I2C_SLTL_REG(base))
+#define I2C_WR_SLTL(base, value) (I2C_SLTL_REG(base) = (value))
+#define I2C_RMW_SLTL(base, mask, value) (I2C_WR_SLTL(base, (I2C_RD_SLTL(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) |  (value)))
+#define I2C_CLR_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) & ~(value)))
+#define I2C_TOG_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 I2S
+ *
+ * Inter-IC Sound / Synchronous Audio Interface
+ *
+ * Registers defined in this header file:
+ * - I2S_TCSR - SAI Transmit Control Register
+ * - I2S_TCR1 - SAI Transmit Configuration 1 Register
+ * - I2S_TCR2 - SAI Transmit Configuration 2 Register
+ * - I2S_TCR3 - SAI Transmit Configuration 3 Register
+ * - I2S_TCR4 - SAI Transmit Configuration 4 Register
+ * - I2S_TCR5 - SAI Transmit Configuration 5 Register
+ * - I2S_TDR - SAI Transmit Data Register
+ * - I2S_TFR - SAI Transmit FIFO Register
+ * - I2S_TMR - SAI Transmit Mask Register
+ * - I2S_RCSR - SAI Receive Control Register
+ * - I2S_RCR1 - SAI Receive Configuration 1 Register
+ * - I2S_RCR2 - SAI Receive Configuration 2 Register
+ * - I2S_RCR3 - SAI Receive Configuration 3 Register
+ * - I2S_RCR4 - SAI Receive Configuration 4 Register
+ * - I2S_RCR5 - SAI Receive Configuration 5 Register
+ * - I2S_RDR - SAI Receive Data Register
+ * - I2S_RFR - SAI Receive FIFO Register
+ * - I2S_RMR - SAI Receive Mask Register
+ * - I2S_MCR - SAI MCLK Control Register
+ * - I2S_MDR - SAI MCLK Divide Register
+ */
+
+#define I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */
+#define I2S0_IDX (0U) /*!< Instance number for I2S0. */
+
+/*******************************************************************************
+ * I2S_TCSR - SAI Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCSR - SAI Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCSR register
+ */
+/*@{*/
+#define I2S_RD_TCSR(base)        (I2S_TCSR_REG(base))
+#define I2S_WR_TCSR(base, value) (I2S_TCSR_REG(base) = (value))
+#define I2S_RMW_TCSR(base, mask, value) (I2S_WR_TCSR(base, (I2S_RD_TCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) |  (value)))
+#define I2S_CLR_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) & ~(value)))
+#define I2S_TOG_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_TCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRDE field. */
+#define I2S_RD_TCSR_FRDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRDE_MASK) >> I2S_TCSR_FRDE_SHIFT)
+#define I2S_BRD_TCSR_FRDE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRDE_SHIFT))
+
+/*! @brief Set the FRDE field to a new value. */
+#define I2S_WR_TCSR_FRDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FRDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FRDE(value)))
+#define I2S_BWR_TCSR_FRDE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWDE field. */
+#define I2S_RD_TCSR_FWDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWDE_MASK) >> I2S_TCSR_FWDE_SHIFT)
+#define I2S_BRD_TCSR_FWDE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_TCSR_FWDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWDE(value)))
+#define I2S_BWR_TCSR_FWDE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRIE field. */
+#define I2S_RD_TCSR_FRIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRIE_MASK) >> I2S_TCSR_FRIE_SHIFT)
+#define I2S_BRD_TCSR_FRIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRIE_SHIFT))
+
+/*! @brief Set the FRIE field to a new value. */
+#define I2S_WR_TCSR_FRIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FRIE(value)))
+#define I2S_BWR_TCSR_FRIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWIE field. */
+#define I2S_RD_TCSR_FWIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWIE_MASK) >> I2S_TCSR_FWIE_SHIFT)
+#define I2S_BRD_TCSR_FWIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_TCSR_FWIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWIE(value)))
+#define I2S_BWR_TCSR_FWIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEIE field. */
+#define I2S_RD_TCSR_FEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEIE_MASK) >> I2S_TCSR_FEIE_SHIFT)
+#define I2S_BRD_TCSR_FEIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_TCSR_FEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEIE(value)))
+#define I2S_BWR_TCSR_FEIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEIE field. */
+#define I2S_RD_TCSR_SEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEIE_MASK) >> I2S_TCSR_SEIE_SHIFT)
+#define I2S_BRD_TCSR_SEIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_TCSR_SEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEIE(value)))
+#define I2S_BWR_TCSR_SEIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSIE field. */
+#define I2S_RD_TCSR_WSIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSIE_MASK) >> I2S_TCSR_WSIE_SHIFT)
+#define I2S_BRD_TCSR_WSIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_TCSR_WSIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_WSIE(value)))
+#define I2S_BWR_TCSR_WSIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled transmit channel FIFO is
+ * less than or equal to the transmit FIFO watermark.
+ *
+ * Values:
+ * - 0b0 - Transmit FIFO watermark has not been reached.
+ * - 0b1 - Transmit FIFO watermark has been reached.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRF field. */
+#define I2S_RD_TCSR_FRF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRF_MASK) >> I2S_TCSR_FRF_SHIFT)
+#define I2S_BRD_TCSR_FRF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled transmit FIFO is empty.
+ *
+ * Values:
+ * - 0b0 - No enabled transmit FIFO is empty.
+ * - 0b1 - Enabled transmit FIFO is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWF field. */
+#define I2S_RD_TCSR_FWF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWF_MASK) >> I2S_TCSR_FWF_SHIFT)
+#define I2S_BRD_TCSR_FWF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
+ * field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Transmit underrun not detected.
+ * - 0b1 - Transmit underrun detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEF field. */
+#define I2S_RD_TCSR_FEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEF_MASK) >> I2S_TCSR_FEF_SHIFT)
+#define I2S_BRD_TCSR_FEF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_TCSR_FEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEF(value)))
+#define I2S_BWR_TCSR_FEF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Sync error not detected.
+ * - 0b1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEF field. */
+#define I2S_RD_TCSR_SEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEF_MASK) >> I2S_TCSR_SEF_SHIFT)
+#define I2S_BRD_TCSR_SEF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_TCSR_SEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEF(value)))
+#define I2S_BWR_TCSR_SEF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Start of word not detected.
+ * - 0b1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSF field. */
+#define I2S_RD_TCSR_WSF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSF_MASK) >> I2S_TCSR_WSF_SHIFT)
+#define I2S_BRD_TCSR_WSF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_TCSR_WSF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK), I2S_TCSR_WSF(value)))
+#define I2S_BWR_TCSR_WSF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SR[24] (RW)
+ *
+ * When set, resets the internal transmitter logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SR field. */
+#define I2S_RD_TCSR_SR(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SR_MASK) >> I2S_TCSR_SR_SHIFT)
+#define I2S_BRD_TCSR_SR(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_TCSR_SR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SR(value)))
+#define I2S_BWR_TCSR_SR(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the transmitter is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_TCSR_FR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FR(value)))
+#define I2S_BWR_TCSR_FR(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field BCE[28] (RW)
+ *
+ * Enables the transmit bit clock, separately from the TE. This field is
+ * automatically set whenever TE is set. When software clears this field, the transmit
+ * bit clock remains enabled, and this bit remains set, until the end of the
+ * current frame.
+ *
+ * Values:
+ * - 0b0 - Transmit bit clock is disabled.
+ * - 0b1 - Transmit bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_BCE field. */
+#define I2S_RD_TCSR_BCE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_BCE_MASK) >> I2S_TCSR_BCE_SHIFT)
+#define I2S_BRD_TCSR_BCE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_TCSR_BCE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_BCE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_BCE(value)))
+#define I2S_BWR_TCSR_BCE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables transmitter operation in Debug mode. The transmit bit clock
+ * is not affected by debug mode.
+ *
+ * Values:
+ * - 0b0 - Transmitter is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 0b1 - Transmitter is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_DBGE field. */
+#define I2S_RD_TCSR_DBGE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_DBGE_MASK) >> I2S_TCSR_DBGE_SHIFT)
+#define I2S_BRD_TCSR_DBGE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_TCSR_DBGE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_DBGE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_DBGE(value)))
+#define I2S_BWR_TCSR_DBGE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field STOPE[30] (RW)
+ *
+ * Configures transmitter operation in Stop mode. This field is ignored and the
+ * transmitter is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0b0 - Transmitter disabled in Stop mode.
+ * - 0b1 - Transmitter enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_STOPE field. */
+#define I2S_RD_TCSR_STOPE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_STOPE_MASK) >> I2S_TCSR_STOPE_SHIFT)
+#define I2S_BRD_TCSR_STOPE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_TCSR_STOPE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_STOPE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_STOPE(value)))
+#define I2S_BWR_TCSR_STOPE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field TE[31] (RW)
+ *
+ * Enables/disables the transmitter. When software clears this field, the
+ * transmitter remains enabled, and this bit remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0b0 - Transmitter is disabled.
+ * - 0b1 - Transmitter is enabled, or transmitter has been disabled and has not
+ *     yet reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_TE field. */
+#define I2S_RD_TCSR_TE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_TE_MASK) >> I2S_TCSR_TE_SHIFT)
+#define I2S_BRD_TCSR_TE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT))
+
+/*! @brief Set the TE field to a new value. */
+#define I2S_WR_TCSR_TE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_TE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_TE(value)))
+#define I2S_BWR_TCSR_TE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR1 - SAI Transmit Configuration 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR1 register
+ */
+/*@{*/
+#define I2S_RD_TCR1(base)        (I2S_TCR1_REG(base))
+#define I2S_WR_TCR1(base, value) (I2S_TCR1_REG(base) = (value))
+#define I2S_RMW_TCR1(base, mask, value) (I2S_WR_TCR1(base, (I2S_RD_TCR1(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) |  (value)))
+#define I2S_CLR_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) & ~(value)))
+#define I2S_TOG_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR1, field TFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled transmit channels.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR1_TFW field. */
+#define I2S_RD_TCR1_TFW(base) ((I2S_TCR1_REG(base) & I2S_TCR1_TFW_MASK) >> I2S_TCR1_TFW_SHIFT)
+#define I2S_BRD_TCR1_TFW(base) (I2S_RD_TCR1_TFW(base))
+
+/*! @brief Set the TFW field to a new value. */
+#define I2S_WR_TCR1_TFW(base, value) (I2S_RMW_TCR1(base, I2S_TCR1_TFW_MASK, I2S_TCR1_TFW(value)))
+#define I2S_BWR_TCR1_TFW(base, value) (I2S_WR_TCR1_TFW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR2 - SAI Transmit Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR2 register
+ */
+/*@{*/
+#define I2S_RD_TCR2(base)        (I2S_TCR2_REG(base))
+#define I2S_WR_TCR2(base, value) (I2S_TCR2_REG(base) = (value))
+#define I2S_RMW_TCR2(base, mask, value) (I2S_WR_TCR2(base, (I2S_RD_TCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) |  (value)))
+#define I2S_CLR_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) & ~(value)))
+#define I2S_TOG_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_DIV field. */
+#define I2S_RD_TCR2_DIV(base) ((I2S_TCR2_REG(base) & I2S_TCR2_DIV_MASK) >> I2S_TCR2_DIV_SHIFT)
+#define I2S_BRD_TCR2_DIV(base) (I2S_RD_TCR2_DIV(base))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_TCR2_DIV(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_DIV_MASK, I2S_TCR2_DIV(value)))
+#define I2S_BWR_TCR2_DIV(base, value) (I2S_WR_TCR2_DIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is generated externally in Slave mode.
+ * - 0b1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCD field. */
+#define I2S_RD_TCR2_BCD(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCD_MASK) >> I2S_TCR2_BCD_SHIFT)
+#define I2S_BRD_TCR2_BCD(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_TCR2_BCD(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCD_MASK, I2S_TCR2_BCD(value)))
+#define I2S_BWR_TCR2_BCD(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 0b1 - Bit clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCP field. */
+#define I2S_RD_TCR2_BCP(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCP_MASK) >> I2S_TCR2_BCP_SHIFT)
+#define I2S_BRD_TCR2_BCP(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_TCR2_BCP(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCP_MASK, I2S_TCR2_BCP(value)))
+#define I2S_BWR_TCR2_BCP(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 0b00 - Bus Clock selected.
+ * - 0b01 - Master Clock (MCLK) 1 option selected.
+ * - 0b10 - Master Clock (MCLK) 2 option selected.
+ * - 0b11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_MSEL field. */
+#define I2S_RD_TCR2_MSEL(base) ((I2S_TCR2_REG(base) & I2S_TCR2_MSEL_MASK) >> I2S_TCR2_MSEL_SHIFT)
+#define I2S_BRD_TCR2_MSEL(base) (I2S_RD_TCR2_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_TCR2_MSEL(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_MSEL_MASK, I2S_TCR2_MSEL(value)))
+#define I2S_BWR_TCR2_MSEL(base, value) (I2S_WR_TCR2_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the
+ * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
+ * input as if the clock was externally generated). This has the effect of
+ * decreasing the data input setup time, but increasing the data output valid time. The
+ * slave mode timing from the datasheet should be used for the transmitter when
+ * this bit is set. In synchronous mode, this bit allows the transmitter to use
+ * the slave mode timing from the datasheet, while the receiver uses the master
+ * mode timing. This field has no effect when configured for an externally generated
+ * bit clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCI field. */
+#define I2S_RD_TCR2_BCI(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCI_MASK) >> I2S_TCR2_BCI_SHIFT)
+#define I2S_BRD_TCR2_BCI(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_TCR2_BCI(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCI_MASK, I2S_TCR2_BCI(value)))
+#define I2S_BWR_TCR2_BCI(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the transmitter. When the transmitter
+ * is configured in asynchronous mode and this bit is set, the transmitter is
+ * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the transmitter continues to use the
+ * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
+ * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
+ * the same value. When both are set, the transmitter and receiver are both
+ * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
+ * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
+ * peripheral.
+ *
+ * Values:
+ * - 0b0 - Use the normal bit clock source.
+ * - 0b1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCS field. */
+#define I2S_RD_TCR2_BCS(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCS_MASK) >> I2S_TCR2_BCS_SHIFT)
+#define I2S_BRD_TCR2_BCS(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_TCR2_BCS(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCS_MASK, I2S_TCR2_BCS(value)))
+#define I2S_BWR_TCR2_BCS(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the receiver or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 0b00 - Asynchronous mode.
+ * - 0b01 - Synchronous with receiver.
+ * - 0b10 - Synchronous with another SAI transmitter.
+ * - 0b11 - Synchronous with another SAI receiver.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_SYNC field. */
+#define I2S_RD_TCR2_SYNC(base) ((I2S_TCR2_REG(base) & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT)
+#define I2S_BRD_TCR2_SYNC(base) (I2S_RD_TCR2_SYNC(base))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_TCR2_SYNC(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_SYNC_MASK, I2S_TCR2_SYNC(value)))
+#define I2S_BWR_TCR2_SYNC(base, value) (I2S_WR_TCR2_SYNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR3 - SAI Transmit Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR3 register
+ */
+/*@{*/
+#define I2S_RD_TCR3(base)        (I2S_TCR3_REG(base))
+#define I2S_WR_TCR3(base, value) (I2S_TCR3_REG(base) = (value))
+#define I2S_RMW_TCR3(base, mask, value) (I2S_WR_TCR3(base, (I2S_RD_TCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) |  (value)))
+#define I2S_CLR_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) & ~(value)))
+#define I2S_TOG_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word sets the start of word flag. The value written must be
+ * one less than the word number. For example, writing 0 configures the first
+ * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
+ * start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_WDFL field. */
+#define I2S_RD_TCR3_WDFL(base) ((I2S_TCR3_REG(base) & I2S_TCR3_WDFL_MASK) >> I2S_TCR3_WDFL_SHIFT)
+#define I2S_BRD_TCR3_WDFL(base) (I2S_RD_TCR3_WDFL(base))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_TCR3_WDFL(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_WDFL_MASK, I2S_TCR3_WDFL(value)))
+#define I2S_BWR_TCR3_WDFL(base, value) (I2S_WR_TCR3_WDFL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR3, field TCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for transmit operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0b00 - Transmit data channel N is disabled.
+ * - 0b01 - Transmit data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_TCE field. */
+#define I2S_RD_TCR3_TCE(base) ((I2S_TCR3_REG(base) & I2S_TCR3_TCE_MASK) >> I2S_TCR3_TCE_SHIFT)
+#define I2S_BRD_TCR3_TCE(base) (I2S_RD_TCR3_TCE(base))
+
+/*! @brief Set the TCE field to a new value. */
+#define I2S_WR_TCR3_TCE(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_TCE_MASK, I2S_TCR3_TCE(value)))
+#define I2S_BWR_TCR3_TCE(base, value) (I2S_WR_TCR3_TCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR4 - SAI Transmit Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR4 register
+ */
+/*@{*/
+#define I2S_RD_TCR4(base)        (I2S_TCR4_REG(base))
+#define I2S_WR_TCR4(base, value) (I2S_TCR4_REG(base) = (value))
+#define I2S_RMW_TCR4(base, mask, value) (I2S_WR_TCR4(base, (I2S_RD_TCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) |  (value)))
+#define I2S_CLR_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) & ~(value)))
+#define I2S_TOG_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is generated externally in Slave mode.
+ * - 0b1 - Frame sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSD field. */
+#define I2S_RD_TCR4_FSD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSD_MASK) >> I2S_TCR4_FSD_SHIFT)
+#define I2S_BRD_TCR4_FSD(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_TCR4_FSD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSD_MASK, I2S_TCR4_FSD(value)))
+#define I2S_BWR_TCR4_FSD(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is active high.
+ * - 0b1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSP field. */
+#define I2S_RD_TCR4_FSP(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSP_MASK) >> I2S_TCR4_FSP_SHIFT)
+#define I2S_BRD_TCR4_FSP(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_TCR4_FSP(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSP_MASK, I2S_TCR4_FSP(value)))
+#define I2S_BWR_TCR4_FSP(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Frame sync asserts with the first bit of the frame.
+ * - 0b1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSE field. */
+#define I2S_RD_TCR4_FSE(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSE_MASK) >> I2S_TCR4_FSE_SHIFT)
+#define I2S_BRD_TCR4_FSE(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_TCR4_FSE(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSE_MASK, I2S_TCR4_FSE(value)))
+#define I2S_BWR_TCR4_FSE(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is transmitted first.
+ *
+ * Values:
+ * - 0b0 - LSB is transmitted first.
+ * - 0b1 - MSB is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_MF field. */
+#define I2S_RD_TCR4_MF(base) ((I2S_TCR4_REG(base) & I2S_TCR4_MF_MASK) >> I2S_TCR4_MF_SHIFT)
+#define I2S_BRD_TCR4_MF(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_TCR4_MF(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_MF_MASK, I2S_TCR4_MF(value)))
+#define I2S_BWR_TCR4_MF(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_SYWD field. */
+#define I2S_RD_TCR4_SYWD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_SYWD_MASK) >> I2S_TCR4_SYWD_SHIFT)
+#define I2S_BRD_TCR4_SYWD(base) (I2S_RD_TCR4_SYWD(base))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_TCR4_SYWD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_SYWD_MASK, I2S_TCR4_SYWD(value)))
+#define I2S_BWR_TCR4_SYWD(base, value) (I2S_WR_TCR4_SYWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FRSZ field. */
+#define I2S_RD_TCR4_FRSZ(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FRSZ_MASK) >> I2S_TCR4_FRSZ_SHIFT)
+#define I2S_BRD_TCR4_FRSZ(base) (I2S_RD_TCR4_FRSZ(base))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_TCR4_FRSZ(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FRSZ_MASK, I2S_TCR4_FRSZ(value)))
+#define I2S_BWR_TCR4_FRSZ(base, value) (I2S_WR_TCR4_FRSZ(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR5 - SAI Transmit Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR5 register
+ */
+/*@{*/
+#define I2S_RD_TCR5(base)        (I2S_TCR5_REG(base))
+#define I2S_WR_TCR5(base, value) (I2S_TCR5_REG(base) = (value))
+#define I2S_RMW_TCR5(base, mask, value) (I2S_WR_TCR5(base, (I2S_RD_TCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) |  (value)))
+#define I2S_CLR_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) & ~(value)))
+#define I2S_TOG_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit transmitted for each word in the
+ * frame. If configured for MSB First, the index of the next bit transmitted is
+ * one less than the current bit transmitted. If configured for LSB First, the
+ * index of the next bit transmitted is one more than the current bit transmitted.
+ * The value written must be greater than or equal to the word width when
+ * configured for MSB First. The value written must be less than or equal to 31-word width
+ * when configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_FBT field. */
+#define I2S_RD_TCR5_FBT(base) ((I2S_TCR5_REG(base) & I2S_TCR5_FBT_MASK) >> I2S_TCR5_FBT_SHIFT)
+#define I2S_BRD_TCR5_FBT(base) (I2S_RD_TCR5_FBT(base))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_TCR5_FBT(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_FBT_MASK, I2S_TCR5_FBT(value)))
+#define I2S_BWR_TCR5_FBT(base, value) (I2S_WR_TCR5_FBT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_W0W field. */
+#define I2S_RD_TCR5_W0W(base) ((I2S_TCR5_REG(base) & I2S_TCR5_W0W_MASK) >> I2S_TCR5_W0W_SHIFT)
+#define I2S_BRD_TCR5_W0W(base) (I2S_RD_TCR5_W0W(base))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_TCR5_W0W(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_W0W_MASK, I2S_TCR5_W0W(value)))
+#define I2S_BWR_TCR5_W0W(base, value) (I2S_WR_TCR5_W0W(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_WNW field. */
+#define I2S_RD_TCR5_WNW(base) ((I2S_TCR5_REG(base) & I2S_TCR5_WNW_MASK) >> I2S_TCR5_WNW_SHIFT)
+#define I2S_BRD_TCR5_WNW(base) (I2S_RD_TCR5_WNW(base))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_TCR5_WNW(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_WNW_MASK, I2S_TCR5_WNW(value)))
+#define I2S_BWR_TCR5_WNW(base, value) (I2S_WR_TCR5_WNW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TDR - SAI Transmit Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TDR - SAI Transmit Data Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TDR register
+ */
+/*@{*/
+#define I2S_RD_TDR(base, index)  (I2S_TDR_REG(base, index))
+#define I2S_WR_TDR(base, index, value) (I2S_TDR_REG(base, index) = (value))
+#define I2S_RMW_TDR(base, index, mask, value) (I2S_WR_TDR(base, index, (I2S_RD_TDR(base, index) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TFR - SAI Transmit FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TFR - SAI Transmit FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TFR register
+ */
+/*@{*/
+#define I2S_RD_TFR(base, index)  (I2S_TFR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TFR bitfields
+ */
+
+/*!
+ * @name Register I2S_TFR, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for transmit data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TFR_RFP field. */
+#define I2S_RD_TFR_RFP(base, index) ((I2S_TFR_REG(base, index) & I2S_TFR_RFP_MASK) >> I2S_TFR_RFP_SHIFT)
+#define I2S_BRD_TFR_RFP(base, index) (I2S_RD_TFR_RFP(base, index))
+/*@}*/
+
+/*!
+ * @name Register I2S_TFR, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for transmit data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TFR_WFP field. */
+#define I2S_RD_TFR_WFP(base, index) ((I2S_TFR_REG(base, index) & I2S_TFR_WFP_MASK) >> I2S_TFR_WFP_SHIFT)
+#define I2S_BRD_TFR_WFP(base, index) (I2S_RD_TFR_WFP(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TMR - SAI Transmit Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TMR - SAI Transmit Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When TCSR[TE] is first set At
+ * the end of each frame. This allows the masked words in each frame to change
+ * from frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TMR register
+ */
+/*@{*/
+#define I2S_RD_TMR(base)         (I2S_TMR_REG(base))
+#define I2S_WR_TMR(base, value)  (I2S_TMR_REG(base) = (value))
+#define I2S_RMW_TMR(base, mask, value) (I2S_WR_TMR(base, (I2S_RD_TMR(base) & ~(mask)) | (value)))
+#define I2S_SET_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) |  (value)))
+#define I2S_CLR_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) & ~(value)))
+#define I2S_TOG_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCSR - SAI Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCSR - SAI Receive Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCSR register
+ */
+/*@{*/
+#define I2S_RD_RCSR(base)        (I2S_RCSR_REG(base))
+#define I2S_WR_RCSR(base, value) (I2S_RCSR_REG(base) = (value))
+#define I2S_RMW_RCSR(base, mask, value) (I2S_WR_RCSR(base, (I2S_RD_RCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) |  (value)))
+#define I2S_CLR_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) & ~(value)))
+#define I2S_TOG_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_RCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRDE field. */
+#define I2S_RD_RCSR_FRDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRDE_MASK) >> I2S_RCSR_FRDE_SHIFT)
+#define I2S_BRD_RCSR_FRDE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRDE_SHIFT))
+
+/*! @brief Set the FRDE field to a new value. */
+#define I2S_WR_RCSR_FRDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FRDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FRDE(value)))
+#define I2S_BWR_RCSR_FRDE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWDE field. */
+#define I2S_RD_RCSR_FWDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWDE_MASK) >> I2S_RCSR_FWDE_SHIFT)
+#define I2S_BRD_RCSR_FWDE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_RCSR_FWDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWDE(value)))
+#define I2S_BWR_RCSR_FWDE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRIE field. */
+#define I2S_RD_RCSR_FRIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRIE_MASK) >> I2S_RCSR_FRIE_SHIFT)
+#define I2S_BRD_RCSR_FRIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRIE_SHIFT))
+
+/*! @brief Set the FRIE field to a new value. */
+#define I2S_WR_RCSR_FRIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FRIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FRIE(value)))
+#define I2S_BWR_RCSR_FRIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWIE field. */
+#define I2S_RD_RCSR_FWIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWIE_MASK) >> I2S_RCSR_FWIE_SHIFT)
+#define I2S_BRD_RCSR_FWIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_RCSR_FWIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWIE(value)))
+#define I2S_BWR_RCSR_FWIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEIE field. */
+#define I2S_RD_RCSR_FEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEIE_MASK) >> I2S_RCSR_FEIE_SHIFT)
+#define I2S_BRD_RCSR_FEIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_RCSR_FEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEIE(value)))
+#define I2S_BWR_RCSR_FEIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEIE field. */
+#define I2S_RD_RCSR_SEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEIE_MASK) >> I2S_RCSR_SEIE_SHIFT)
+#define I2S_BRD_RCSR_SEIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_RCSR_SEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEIE(value)))
+#define I2S_BWR_RCSR_SEIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSIE field. */
+#define I2S_RD_RCSR_WSIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSIE_MASK) >> I2S_RCSR_WSIE_SHIFT)
+#define I2S_BRD_RCSR_WSIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_RCSR_WSIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_WSIE(value)))
+#define I2S_BWR_RCSR_WSIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled receive channel FIFO is
+ * greater than the receive FIFO watermark.
+ *
+ * Values:
+ * - 0b0 - Receive FIFO watermark not reached.
+ * - 0b1 - Receive FIFO watermark has been reached.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRF field. */
+#define I2S_RD_RCSR_FRF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRF_MASK) >> I2S_RCSR_FRF_SHIFT)
+#define I2S_BRD_RCSR_FRF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled receive FIFO is full.
+ *
+ * Values:
+ * - 0b0 - No enabled receive FIFO is full.
+ * - 0b1 - Enabled receive FIFO is full.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWF field. */
+#define I2S_RD_RCSR_FWF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWF_MASK) >> I2S_RCSR_FWF_SHIFT)
+#define I2S_BRD_RCSR_FWF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
+ * this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Receive overflow not detected.
+ * - 0b1 - Receive overflow detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEF field. */
+#define I2S_RD_RCSR_FEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEF_MASK) >> I2S_RCSR_FEF_SHIFT)
+#define I2S_BRD_RCSR_FEF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_RCSR_FEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEF(value)))
+#define I2S_BWR_RCSR_FEF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Sync error not detected.
+ * - 0b1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEF field. */
+#define I2S_RD_RCSR_SEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEF_MASK) >> I2S_RCSR_SEF_SHIFT)
+#define I2S_BRD_RCSR_SEF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_RCSR_SEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEF(value)))
+#define I2S_BWR_RCSR_SEF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Start of word not detected.
+ * - 0b1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSF field. */
+#define I2S_RD_RCSR_WSF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSF_MASK) >> I2S_RCSR_WSF_SHIFT)
+#define I2S_BRD_RCSR_WSF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_RCSR_WSF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK), I2S_RCSR_WSF(value)))
+#define I2S_BWR_RCSR_WSF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SR[24] (RW)
+ *
+ * Resets the internal receiver logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SR field. */
+#define I2S_RD_RCSR_SR(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SR_MASK) >> I2S_RCSR_SR_SHIFT)
+#define I2S_BRD_RCSR_SR(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_RCSR_SR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SR(value)))
+#define I2S_BWR_RCSR_SR(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the receiver is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_RCSR_FR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FR(value)))
+#define I2S_BWR_RCSR_FR(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field BCE[28] (RW)
+ *
+ * Enables the receive bit clock, separately from RE. This field is
+ * automatically set whenever RE is set. When software clears this field, the receive bit
+ * clock remains enabled, and this field remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0b0 - Receive bit clock is disabled.
+ * - 0b1 - Receive bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_BCE field. */
+#define I2S_RD_RCSR_BCE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_BCE_MASK) >> I2S_RCSR_BCE_SHIFT)
+#define I2S_BRD_RCSR_BCE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_RCSR_BCE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_BCE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_BCE(value)))
+#define I2S_BWR_RCSR_BCE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables receiver operation in Debug mode. The receive bit clock is
+ * not affected by Debug mode.
+ *
+ * Values:
+ * - 0b0 - Receiver is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 0b1 - Receiver is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_DBGE field. */
+#define I2S_RD_RCSR_DBGE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_DBGE_MASK) >> I2S_RCSR_DBGE_SHIFT)
+#define I2S_BRD_RCSR_DBGE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_RCSR_DBGE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_DBGE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_DBGE(value)))
+#define I2S_BWR_RCSR_DBGE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field STOPE[30] (RW)
+ *
+ * Configures receiver operation in Stop mode. This bit is ignored and the
+ * receiver is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0b0 - Receiver disabled in Stop mode.
+ * - 0b1 - Receiver enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_STOPE field. */
+#define I2S_RD_RCSR_STOPE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_STOPE_MASK) >> I2S_RCSR_STOPE_SHIFT)
+#define I2S_BRD_RCSR_STOPE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_RCSR_STOPE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_STOPE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_STOPE(value)))
+#define I2S_BWR_RCSR_STOPE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field RE[31] (RW)
+ *
+ * Enables/disables the receiver. When software clears this field, the receiver
+ * remains enabled, and this bit remains set, until the end of the current frame.
+ *
+ * Values:
+ * - 0b0 - Receiver is disabled.
+ * - 0b1 - Receiver is enabled, or receiver has been disabled and has not yet
+ *     reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_RE field. */
+#define I2S_RD_RCSR_RE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_RE_MASK) >> I2S_RCSR_RE_SHIFT)
+#define I2S_BRD_RCSR_RE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT))
+
+/*! @brief Set the RE field to a new value. */
+#define I2S_WR_RCSR_RE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_RE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_RE(value)))
+#define I2S_BWR_RCSR_RE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR1 - SAI Receive Configuration 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR1 register
+ */
+/*@{*/
+#define I2S_RD_RCR1(base)        (I2S_RCR1_REG(base))
+#define I2S_WR_RCR1(base, value) (I2S_RCR1_REG(base) = (value))
+#define I2S_RMW_RCR1(base, mask, value) (I2S_WR_RCR1(base, (I2S_RD_RCR1(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) |  (value)))
+#define I2S_CLR_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) & ~(value)))
+#define I2S_TOG_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR1, field RFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled receiver channels.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR1_RFW field. */
+#define I2S_RD_RCR1_RFW(base) ((I2S_RCR1_REG(base) & I2S_RCR1_RFW_MASK) >> I2S_RCR1_RFW_SHIFT)
+#define I2S_BRD_RCR1_RFW(base) (I2S_RD_RCR1_RFW(base))
+
+/*! @brief Set the RFW field to a new value. */
+#define I2S_WR_RCR1_RFW(base, value) (I2S_RMW_RCR1(base, I2S_RCR1_RFW_MASK, I2S_RCR1_RFW(value)))
+#define I2S_BWR_RCR1_RFW(base, value) (I2S_WR_RCR1_RFW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR2 - SAI Receive Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR2 register
+ */
+/*@{*/
+#define I2S_RD_RCR2(base)        (I2S_RCR2_REG(base))
+#define I2S_WR_RCR2(base, value) (I2S_RCR2_REG(base) = (value))
+#define I2S_RMW_RCR2(base, mask, value) (I2S_WR_RCR2(base, (I2S_RD_RCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) |  (value)))
+#define I2S_CLR_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) & ~(value)))
+#define I2S_TOG_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_DIV field. */
+#define I2S_RD_RCR2_DIV(base) ((I2S_RCR2_REG(base) & I2S_RCR2_DIV_MASK) >> I2S_RCR2_DIV_SHIFT)
+#define I2S_BRD_RCR2_DIV(base) (I2S_RD_RCR2_DIV(base))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_RCR2_DIV(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_DIV_MASK, I2S_RCR2_DIV(value)))
+#define I2S_BWR_RCR2_DIV(base, value) (I2S_WR_RCR2_DIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is generated externally in Slave mode.
+ * - 0b1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCD field. */
+#define I2S_RD_RCR2_BCD(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCD_MASK) >> I2S_RCR2_BCD_SHIFT)
+#define I2S_BRD_RCR2_BCD(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_RCR2_BCD(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCD_MASK, I2S_RCR2_BCD(value)))
+#define I2S_BWR_RCR2_BCD(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit Clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 0b1 - Bit Clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCP field. */
+#define I2S_RD_RCR2_BCP(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCP_MASK) >> I2S_RCR2_BCP_SHIFT)
+#define I2S_BRD_RCR2_BCP(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_RCR2_BCP(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCP_MASK, I2S_RCR2_BCP(value)))
+#define I2S_BWR_RCR2_BCP(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 0b00 - Bus Clock selected.
+ * - 0b01 - Master Clock (MCLK) 1 option selected.
+ * - 0b10 - Master Clock (MCLK) 2 option selected.
+ * - 0b11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_MSEL field. */
+#define I2S_RD_RCR2_MSEL(base) ((I2S_RCR2_REG(base) & I2S_RCR2_MSEL_MASK) >> I2S_RCR2_MSEL_SHIFT)
+#define I2S_BRD_RCR2_MSEL(base) (I2S_RD_RCR2_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_RCR2_MSEL(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_MSEL_MASK, I2S_RCR2_MSEL(value)))
+#define I2S_BWR_RCR2_MSEL(base, value) (I2S_WR_RCR2_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the receiver
+ * is delayed by the pad output delay (the receiver is clocked by the pad input
+ * as if the clock was externally generated). This has the effect of decreasing
+ * the data input setup time, but increasing the data output valid time. The slave
+ * mode timing from the datasheet should be used for the receiver when this bit
+ * is set. In synchronous mode, this bit allows the receiver to use the slave mode
+ * timing from the datasheet, while the transmitter uses the master mode timing.
+ * This field has no effect when configured for an externally generated bit
+ * clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCI field. */
+#define I2S_RD_RCR2_BCI(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCI_MASK) >> I2S_RCR2_BCI_SHIFT)
+#define I2S_BRD_RCR2_BCI(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_RCR2_BCI(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCI_MASK, I2S_RCR2_BCI(value)))
+#define I2S_BWR_RCR2_BCI(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the receiver. When the receiver is
+ * configured in asynchronous mode and this bit is set, the receiver is clocked by
+ * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the receiver continues to use the receiver
+ * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
+ * mode, the transmitter BCS field and receiver BCS field must be set to the same
+ * value. When both are set, the transmitter and receiver are both clocked by the
+ * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
+ * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
+ *
+ * Values:
+ * - 0b0 - Use the normal bit clock source.
+ * - 0b1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCS field. */
+#define I2S_RD_RCR2_BCS(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCS_MASK) >> I2S_RCR2_BCS_SHIFT)
+#define I2S_BRD_RCR2_BCS(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_RCR2_BCS(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCS_MASK, I2S_RCR2_BCS(value)))
+#define I2S_BWR_RCR2_BCS(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the transmitter or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 0b00 - Asynchronous mode.
+ * - 0b01 - Synchronous with transmitter.
+ * - 0b10 - Synchronous with another SAI receiver.
+ * - 0b11 - Synchronous with another SAI transmitter.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_SYNC field. */
+#define I2S_RD_RCR2_SYNC(base) ((I2S_RCR2_REG(base) & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT)
+#define I2S_BRD_RCR2_SYNC(base) (I2S_RD_RCR2_SYNC(base))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_RCR2_SYNC(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_SYNC_MASK, I2S_RCR2_SYNC(value)))
+#define I2S_BWR_RCR2_SYNC(base, value) (I2S_WR_RCR2_SYNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR3 - SAI Receive Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR3 register
+ */
+/*@{*/
+#define I2S_RD_RCR3(base)        (I2S_RCR3_REG(base))
+#define I2S_WR_RCR3(base, value) (I2S_RCR3_REG(base) = (value))
+#define I2S_RMW_RCR3(base, mask, value) (I2S_WR_RCR3(base, (I2S_RD_RCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) |  (value)))
+#define I2S_CLR_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) & ~(value)))
+#define I2S_TOG_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word the start of word flag is set. The value written should
+ * be one less than the word number (for example, write zero to configure for
+ * the first word in the frame). When configured to a value greater than the Frame
+ * Size field, then the start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_WDFL field. */
+#define I2S_RD_RCR3_WDFL(base) ((I2S_RCR3_REG(base) & I2S_RCR3_WDFL_MASK) >> I2S_RCR3_WDFL_SHIFT)
+#define I2S_BRD_RCR3_WDFL(base) (I2S_RD_RCR3_WDFL(base))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_RCR3_WDFL(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_WDFL_MASK, I2S_RCR3_WDFL(value)))
+#define I2S_BWR_RCR3_WDFL(base, value) (I2S_WR_RCR3_WDFL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR3, field RCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for receive operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0b00 - Receive data channel N is disabled.
+ * - 0b01 - Receive data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_RCE field. */
+#define I2S_RD_RCR3_RCE(base) ((I2S_RCR3_REG(base) & I2S_RCR3_RCE_MASK) >> I2S_RCR3_RCE_SHIFT)
+#define I2S_BRD_RCR3_RCE(base) (I2S_RD_RCR3_RCE(base))
+
+/*! @brief Set the RCE field to a new value. */
+#define I2S_WR_RCR3_RCE(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_RCE_MASK, I2S_RCR3_RCE(value)))
+#define I2S_BWR_RCR3_RCE(base, value) (I2S_WR_RCR3_RCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR4 - SAI Receive Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR4 register
+ */
+/*@{*/
+#define I2S_RD_RCR4(base)        (I2S_RCR4_REG(base))
+#define I2S_WR_RCR4(base, value) (I2S_RCR4_REG(base) = (value))
+#define I2S_RMW_RCR4(base, mask, value) (I2S_WR_RCR4(base, (I2S_RD_RCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) |  (value)))
+#define I2S_CLR_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) & ~(value)))
+#define I2S_TOG_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame Sync is generated externally in Slave mode.
+ * - 0b1 - Frame Sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSD field. */
+#define I2S_RD_RCR4_FSD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSD_MASK) >> I2S_RCR4_FSD_SHIFT)
+#define I2S_BRD_RCR4_FSD(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_RCR4_FSD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSD_MASK, I2S_RCR4_FSD(value)))
+#define I2S_BWR_RCR4_FSD(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is active high.
+ * - 0b1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSP field. */
+#define I2S_RD_RCR4_FSP(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSP_MASK) >> I2S_RCR4_FSP_SHIFT)
+#define I2S_BRD_RCR4_FSP(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_RCR4_FSP(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSP_MASK, I2S_RCR4_FSP(value)))
+#define I2S_BWR_RCR4_FSP(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Frame sync asserts with the first bit of the frame.
+ * - 0b1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSE field. */
+#define I2S_RD_RCR4_FSE(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSE_MASK) >> I2S_RCR4_FSE_SHIFT)
+#define I2S_BRD_RCR4_FSE(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_RCR4_FSE(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSE_MASK, I2S_RCR4_FSE(value)))
+#define I2S_BWR_RCR4_FSE(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is received first.
+ *
+ * Values:
+ * - 0b0 - LSB is received first.
+ * - 0b1 - MSB is received first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_MF field. */
+#define I2S_RD_RCR4_MF(base) ((I2S_RCR4_REG(base) & I2S_RCR4_MF_MASK) >> I2S_RCR4_MF_SHIFT)
+#define I2S_BRD_RCR4_MF(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_RCR4_MF(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_MF_MASK, I2S_RCR4_MF(value)))
+#define I2S_BWR_RCR4_MF(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_SYWD field. */
+#define I2S_RD_RCR4_SYWD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_SYWD_MASK) >> I2S_RCR4_SYWD_SHIFT)
+#define I2S_BRD_RCR4_SYWD(base) (I2S_RD_RCR4_SYWD(base))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_RCR4_SYWD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_SYWD_MASK, I2S_RCR4_SYWD(value)))
+#define I2S_BWR_RCR4_SYWD(base, value) (I2S_WR_RCR4_SYWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FRSZ field. */
+#define I2S_RD_RCR4_FRSZ(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FRSZ_MASK) >> I2S_RCR4_FRSZ_SHIFT)
+#define I2S_BRD_RCR4_FRSZ(base) (I2S_RD_RCR4_FRSZ(base))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_RCR4_FRSZ(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FRSZ_MASK, I2S_RCR4_FRSZ(value)))
+#define I2S_BWR_RCR4_FRSZ(base, value) (I2S_WR_RCR4_FRSZ(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR5 - SAI Receive Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR5 register
+ */
+/*@{*/
+#define I2S_RD_RCR5(base)        (I2S_RCR5_REG(base))
+#define I2S_WR_RCR5(base, value) (I2S_RCR5_REG(base) = (value))
+#define I2S_RMW_RCR5(base, mask, value) (I2S_WR_RCR5(base, (I2S_RD_RCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) |  (value)))
+#define I2S_CLR_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) & ~(value)))
+#define I2S_TOG_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit received for each word in the
+ * frame. If configured for MSB First, the index of the next bit received is one less
+ * than the current bit received. If configured for LSB First, the index of the
+ * next bit received is one more than the current bit received. The value written
+ * must be greater than or equal to the word width when configured for MSB
+ * First. The value written must be less than or equal to 31-word width when
+ * configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_FBT field. */
+#define I2S_RD_RCR5_FBT(base) ((I2S_RCR5_REG(base) & I2S_RCR5_FBT_MASK) >> I2S_RCR5_FBT_SHIFT)
+#define I2S_BRD_RCR5_FBT(base) (I2S_RD_RCR5_FBT(base))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_RCR5_FBT(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_FBT_MASK, I2S_RCR5_FBT(value)))
+#define I2S_BWR_RCR5_FBT(base, value) (I2S_WR_RCR5_FBT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_W0W field. */
+#define I2S_RD_RCR5_W0W(base) ((I2S_RCR5_REG(base) & I2S_RCR5_W0W_MASK) >> I2S_RCR5_W0W_SHIFT)
+#define I2S_BRD_RCR5_W0W(base) (I2S_RD_RCR5_W0W(base))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_RCR5_W0W(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_W0W_MASK, I2S_RCR5_W0W(value)))
+#define I2S_BWR_RCR5_W0W(base, value) (I2S_WR_RCR5_W0W(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_WNW field. */
+#define I2S_RD_RCR5_WNW(base) ((I2S_RCR5_REG(base) & I2S_RCR5_WNW_MASK) >> I2S_RCR5_WNW_SHIFT)
+#define I2S_BRD_RCR5_WNW(base) (I2S_RD_RCR5_WNW(base))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_RCR5_WNW(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_WNW_MASK, I2S_RCR5_WNW(value)))
+#define I2S_BWR_RCR5_WNW(base, value) (I2S_WR_RCR5_WNW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RDR - SAI Receive Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RDR - SAI Receive Data Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Reading this register introduces one additional peripheral clock wait state
+ * on each read.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RDR register
+ */
+/*@{*/
+#define I2S_RD_RDR(base, index)  (I2S_RDR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RFR - SAI Receive FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RFR - SAI Receive FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RFR register
+ */
+/*@{*/
+#define I2S_RD_RFR(base, index)  (I2S_RFR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RFR bitfields
+ */
+
+/*!
+ * @name Register I2S_RFR, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for receive data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RFR_RFP field. */
+#define I2S_RD_RFR_RFP(base, index) ((I2S_RFR_REG(base, index) & I2S_RFR_RFP_MASK) >> I2S_RFR_RFP_SHIFT)
+#define I2S_BRD_RFR_RFP(base, index) (I2S_RD_RFR_RFP(base, index))
+/*@}*/
+
+/*!
+ * @name Register I2S_RFR, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for receive data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RFR_WFP field. */
+#define I2S_RD_RFR_WFP(base, index) ((I2S_RFR_REG(base, index) & I2S_RFR_WFP_MASK) >> I2S_RFR_WFP_SHIFT)
+#define I2S_BRD_RFR_WFP(base, index) (I2S_RD_RFR_WFP(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RMR - SAI Receive Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RMR - SAI Receive Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When RCSR[RE] is first set At
+ * the end of each frame This allows the masked words in each frame to change from
+ * frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RMR register
+ */
+/*@{*/
+#define I2S_RD_RMR(base)         (I2S_RMR_REG(base))
+#define I2S_WR_RMR(base, value)  (I2S_RMR_REG(base) = (value))
+#define I2S_RMW_RMR(base, mask, value) (I2S_WR_RMR(base, (I2S_RD_RMR(base) & ~(mask)) | (value)))
+#define I2S_SET_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) |  (value)))
+#define I2S_CLR_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) & ~(value)))
+#define I2S_TOG_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MCR - SAI MCLK Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MCR - SAI MCLK Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Control Register (MCR) controls the clock source and direction of
+ * the audio master clock.
+ */
+/*!
+ * @name Constants and macros for entire I2S_MCR register
+ */
+/*@{*/
+#define I2S_RD_MCR(base)         (I2S_MCR_REG(base))
+#define I2S_WR_MCR(base, value)  (I2S_MCR_REG(base) = (value))
+#define I2S_RMW_MCR(base, mask, value) (I2S_WR_MCR(base, (I2S_RD_MCR(base) & ~(mask)) | (value)))
+#define I2S_SET_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) |  (value)))
+#define I2S_CLR_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) & ~(value)))
+#define I2S_TOG_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MCR bitfields
+ */
+
+/*!
+ * @name Register I2S_MCR, field MICS[25:24] (RW)
+ *
+ * Selects the clock input to the MCLK divider. This field cannot be changed
+ * while the MCLK divider is enabled. See the chip configuration details for
+ * information about the connections to these inputs.
+ *
+ * Values:
+ * - 0b00 - MCLK divider input clock 0 selected.
+ * - 0b01 - MCLK divider input clock 1 selected.
+ * - 0b10 - MCLK divider input clock 2 selected.
+ * - 0b11 - MCLK divider input clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MICS field. */
+#define I2S_RD_MCR_MICS(base) ((I2S_MCR_REG(base) & I2S_MCR_MICS_MASK) >> I2S_MCR_MICS_SHIFT)
+#define I2S_BRD_MCR_MICS(base) (I2S_RD_MCR_MICS(base))
+
+/*! @brief Set the MICS field to a new value. */
+#define I2S_WR_MCR_MICS(base, value) (I2S_RMW_MCR(base, I2S_MCR_MICS_MASK, I2S_MCR_MICS(value)))
+#define I2S_BWR_MCR_MICS(base, value) (I2S_WR_MCR_MICS(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field MOE[30] (RW)
+ *
+ * Enables the MCLK divider and configures the MCLK signal pin as an output.
+ * When software clears this field, it remains set until the MCLK divider is fully
+ * disabled.
+ *
+ * Values:
+ * - 0b0 - MCLK signal pin is configured as an input that bypasses the MCLK
+ *     divider.
+ * - 0b1 - MCLK signal pin is configured as an output from the MCLK divider and
+ *     the MCLK divider is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MOE field. */
+#define I2S_RD_MCR_MOE(base) ((I2S_MCR_REG(base) & I2S_MCR_MOE_MASK) >> I2S_MCR_MOE_SHIFT)
+#define I2S_BRD_MCR_MOE(base) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT))
+
+/*! @brief Set the MOE field to a new value. */
+#define I2S_WR_MCR_MOE(base, value) (I2S_RMW_MCR(base, I2S_MCR_MOE_MASK, I2S_MCR_MOE(value)))
+#define I2S_BWR_MCR_MOE(base, value) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field DUF[31] (RO)
+ *
+ * Provides the status of on-the-fly updates to the MCLK divider ratio.
+ *
+ * Values:
+ * - 0b0 - MCLK divider ratio is not being updated currently.
+ * - 0b1 - MCLK divider ratio is updating on-the-fly. Further updates to the
+ *     MCLK divider ratio are blocked while this flag remains set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_DUF field. */
+#define I2S_RD_MCR_DUF(base) ((I2S_MCR_REG(base) & I2S_MCR_DUF_MASK) >> I2S_MCR_DUF_SHIFT)
+#define I2S_BRD_MCR_DUF(base) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_DUF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MDR - SAI MCLK Divide Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MDR - SAI MCLK Divide Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
+ * MDR can be changed when the MCLK divider clock is enabled, additional writes
+ * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
+ * divided clock is disabled do not set MCR[DUF].
+ */
+/*!
+ * @name Constants and macros for entire I2S_MDR register
+ */
+/*@{*/
+#define I2S_RD_MDR(base)         (I2S_MDR_REG(base))
+#define I2S_WR_MDR(base, value)  (I2S_MDR_REG(base) = (value))
+#define I2S_RMW_MDR(base, mask, value) (I2S_WR_MDR(base, (I2S_RD_MDR(base) & ~(mask)) | (value)))
+#define I2S_SET_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) |  (value)))
+#define I2S_CLR_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) & ~(value)))
+#define I2S_TOG_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MDR bitfields
+ */
+
+/*!
+ * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MDR_DIVIDE field. */
+#define I2S_RD_MDR_DIVIDE(base) ((I2S_MDR_REG(base) & I2S_MDR_DIVIDE_MASK) >> I2S_MDR_DIVIDE_SHIFT)
+#define I2S_BRD_MDR_DIVIDE(base) (I2S_RD_MDR_DIVIDE(base))
+
+/*! @brief Set the DIVIDE field to a new value. */
+#define I2S_WR_MDR_DIVIDE(base, value) (I2S_RMW_MDR(base, I2S_MDR_DIVIDE_MASK, I2S_MDR_DIVIDE(value)))
+#define I2S_BWR_MDR_DIVIDE(base, value) (I2S_WR_MDR_DIVIDE(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MDR, field FRACT[19:12] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MDR_FRACT field. */
+#define I2S_RD_MDR_FRACT(base) ((I2S_MDR_REG(base) & I2S_MDR_FRACT_MASK) >> I2S_MDR_FRACT_SHIFT)
+#define I2S_BRD_MDR_FRACT(base) (I2S_RD_MDR_FRACT(base))
+
+/*! @brief Set the FRACT field to a new value. */
+#define I2S_WR_MDR_FRACT(base, value) (I2S_RMW_MDR(base, I2S_MDR_FRACT_MASK, I2S_MDR_FRACT(value)))
+#define I2S_BWR_MDR_FRACT(base, value) (I2S_WR_MDR_FRACT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 LLWU
+ *
+ * Low leakage wakeup unit
+ *
+ * Registers defined in this header file:
+ * - LLWU_PE1 - LLWU Pin Enable 1 register
+ * - LLWU_PE2 - LLWU Pin Enable 2 register
+ * - LLWU_PE3 - LLWU Pin Enable 3 register
+ * - LLWU_PE4 - LLWU Pin Enable 4 register
+ * - LLWU_ME - LLWU Module Enable register
+ * - LLWU_F1 - LLWU Flag 1 register
+ * - LLWU_F2 - LLWU Flag 2 register
+ * - LLWU_F3 - LLWU Flag 3 register
+ * - LLWU_FILT1 - LLWU Pin Filter 1 register
+ * - LLWU_FILT2 - LLWU Pin Filter 2 register
+ * - LLWU_RST - LLWU Reset Enable register
+ */
+
+#define LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
+#define LLWU_IDX (0U) /*!< Instance number for LLWU. */
+
+/*******************************************************************************
+ * LLWU_PE1 - LLWU Pin Enable 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE1 - LLWU Pin Enable 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE1 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE1 register
+ */
+/*@{*/
+#define LLWU_RD_PE1(base)        (LLWU_PE1_REG(base))
+#define LLWU_WR_PE1(base, value) (LLWU_PE1_REG(base) = (value))
+#define LLWU_RMW_PE1(base, mask, value) (LLWU_WR_PE1(base, (LLWU_RD_PE1(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) |  (value)))
+#define LLWU_CLR_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) & ~(value)))
+#define LLWU_TOG_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
+#define LLWU_RD_PE1_WUPE0(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE0_MASK) >> LLWU_PE1_WUPE0_SHIFT)
+#define LLWU_BRD_PE1_WUPE0(base) (LLWU_RD_PE1_WUPE0(base))
+
+/*! @brief Set the WUPE0 field to a new value. */
+#define LLWU_WR_PE1_WUPE0(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE0_MASK, LLWU_PE1_WUPE0(value)))
+#define LLWU_BWR_PE1_WUPE0(base, value) (LLWU_WR_PE1_WUPE0(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
+#define LLWU_RD_PE1_WUPE1(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE1_MASK) >> LLWU_PE1_WUPE1_SHIFT)
+#define LLWU_BRD_PE1_WUPE1(base) (LLWU_RD_PE1_WUPE1(base))
+
+/*! @brief Set the WUPE1 field to a new value. */
+#define LLWU_WR_PE1_WUPE1(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE1_MASK, LLWU_PE1_WUPE1(value)))
+#define LLWU_BWR_PE1_WUPE1(base, value) (LLWU_WR_PE1_WUPE1(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
+#define LLWU_RD_PE1_WUPE2(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE2_MASK) >> LLWU_PE1_WUPE2_SHIFT)
+#define LLWU_BRD_PE1_WUPE2(base) (LLWU_RD_PE1_WUPE2(base))
+
+/*! @brief Set the WUPE2 field to a new value. */
+#define LLWU_WR_PE1_WUPE2(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE2_MASK, LLWU_PE1_WUPE2(value)))
+#define LLWU_BWR_PE1_WUPE2(base, value) (LLWU_WR_PE1_WUPE2(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
+#define LLWU_RD_PE1_WUPE3(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE3_MASK) >> LLWU_PE1_WUPE3_SHIFT)
+#define LLWU_BRD_PE1_WUPE3(base) (LLWU_RD_PE1_WUPE3(base))
+
+/*! @brief Set the WUPE3 field to a new value. */
+#define LLWU_WR_PE1_WUPE3(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE3_MASK, LLWU_PE1_WUPE3(value)))
+#define LLWU_BWR_PE1_WUPE3(base, value) (LLWU_WR_PE1_WUPE3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE2 - LLWU Pin Enable 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE2 - LLWU Pin Enable 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE2 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE2 register
+ */
+/*@{*/
+#define LLWU_RD_PE2(base)        (LLWU_PE2_REG(base))
+#define LLWU_WR_PE2(base, value) (LLWU_PE2_REG(base) = (value))
+#define LLWU_RMW_PE2(base, mask, value) (LLWU_WR_PE2(base, (LLWU_RD_PE2(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) |  (value)))
+#define LLWU_CLR_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) & ~(value)))
+#define LLWU_TOG_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
+#define LLWU_RD_PE2_WUPE4(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE4_MASK) >> LLWU_PE2_WUPE4_SHIFT)
+#define LLWU_BRD_PE2_WUPE4(base) (LLWU_RD_PE2_WUPE4(base))
+
+/*! @brief Set the WUPE4 field to a new value. */
+#define LLWU_WR_PE2_WUPE4(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE4_MASK, LLWU_PE2_WUPE4(value)))
+#define LLWU_BWR_PE2_WUPE4(base, value) (LLWU_WR_PE2_WUPE4(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
+#define LLWU_RD_PE2_WUPE5(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE5_MASK) >> LLWU_PE2_WUPE5_SHIFT)
+#define LLWU_BRD_PE2_WUPE5(base) (LLWU_RD_PE2_WUPE5(base))
+
+/*! @brief Set the WUPE5 field to a new value. */
+#define LLWU_WR_PE2_WUPE5(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE5_MASK, LLWU_PE2_WUPE5(value)))
+#define LLWU_BWR_PE2_WUPE5(base, value) (LLWU_WR_PE2_WUPE5(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
+#define LLWU_RD_PE2_WUPE6(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE6_MASK) >> LLWU_PE2_WUPE6_SHIFT)
+#define LLWU_BRD_PE2_WUPE6(base) (LLWU_RD_PE2_WUPE6(base))
+
+/*! @brief Set the WUPE6 field to a new value. */
+#define LLWU_WR_PE2_WUPE6(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE6_MASK, LLWU_PE2_WUPE6(value)))
+#define LLWU_BWR_PE2_WUPE6(base, value) (LLWU_WR_PE2_WUPE6(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
+#define LLWU_RD_PE2_WUPE7(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE7_MASK) >> LLWU_PE2_WUPE7_SHIFT)
+#define LLWU_BRD_PE2_WUPE7(base) (LLWU_RD_PE2_WUPE7(base))
+
+/*! @brief Set the WUPE7 field to a new value. */
+#define LLWU_WR_PE2_WUPE7(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE7_MASK, LLWU_PE2_WUPE7(value)))
+#define LLWU_BWR_PE2_WUPE7(base, value) (LLWU_WR_PE2_WUPE7(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE3 - LLWU Pin Enable 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE3 - LLWU Pin Enable 3 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE3 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE3 register
+ */
+/*@{*/
+#define LLWU_RD_PE3(base)        (LLWU_PE3_REG(base))
+#define LLWU_WR_PE3(base, value) (LLWU_PE3_REG(base) = (value))
+#define LLWU_RMW_PE3(base, mask, value) (LLWU_WR_PE3(base, (LLWU_RD_PE3(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) |  (value)))
+#define LLWU_CLR_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) & ~(value)))
+#define LLWU_TOG_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
+#define LLWU_RD_PE3_WUPE8(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE8_MASK) >> LLWU_PE3_WUPE8_SHIFT)
+#define LLWU_BRD_PE3_WUPE8(base) (LLWU_RD_PE3_WUPE8(base))
+
+/*! @brief Set the WUPE8 field to a new value. */
+#define LLWU_WR_PE3_WUPE8(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE8_MASK, LLWU_PE3_WUPE8(value)))
+#define LLWU_BWR_PE3_WUPE8(base, value) (LLWU_WR_PE3_WUPE8(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
+#define LLWU_RD_PE3_WUPE9(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE9_MASK) >> LLWU_PE3_WUPE9_SHIFT)
+#define LLWU_BRD_PE3_WUPE9(base) (LLWU_RD_PE3_WUPE9(base))
+
+/*! @brief Set the WUPE9 field to a new value. */
+#define LLWU_WR_PE3_WUPE9(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE9_MASK, LLWU_PE3_WUPE9(value)))
+#define LLWU_BWR_PE3_WUPE9(base, value) (LLWU_WR_PE3_WUPE9(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
+#define LLWU_RD_PE3_WUPE10(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE10_MASK) >> LLWU_PE3_WUPE10_SHIFT)
+#define LLWU_BRD_PE3_WUPE10(base) (LLWU_RD_PE3_WUPE10(base))
+
+/*! @brief Set the WUPE10 field to a new value. */
+#define LLWU_WR_PE3_WUPE10(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE10_MASK, LLWU_PE3_WUPE10(value)))
+#define LLWU_BWR_PE3_WUPE10(base, value) (LLWU_WR_PE3_WUPE10(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
+#define LLWU_RD_PE3_WUPE11(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE11_MASK) >> LLWU_PE3_WUPE11_SHIFT)
+#define LLWU_BRD_PE3_WUPE11(base) (LLWU_RD_PE3_WUPE11(base))
+
+/*! @brief Set the WUPE11 field to a new value. */
+#define LLWU_WR_PE3_WUPE11(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE11_MASK, LLWU_PE3_WUPE11(value)))
+#define LLWU_BWR_PE3_WUPE11(base, value) (LLWU_WR_PE3_WUPE11(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE4 - LLWU Pin Enable 4 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE4 - LLWU Pin Enable 4 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE4 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE4 register
+ */
+/*@{*/
+#define LLWU_RD_PE4(base)        (LLWU_PE4_REG(base))
+#define LLWU_WR_PE4(base, value) (LLWU_PE4_REG(base) = (value))
+#define LLWU_RMW_PE4(base, mask, value) (LLWU_WR_PE4(base, (LLWU_RD_PE4(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) |  (value)))
+#define LLWU_CLR_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) & ~(value)))
+#define LLWU_TOG_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE4 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
+#define LLWU_RD_PE4_WUPE12(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE12_MASK) >> LLWU_PE4_WUPE12_SHIFT)
+#define LLWU_BRD_PE4_WUPE12(base) (LLWU_RD_PE4_WUPE12(base))
+
+/*! @brief Set the WUPE12 field to a new value. */
+#define LLWU_WR_PE4_WUPE12(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE12_MASK, LLWU_PE4_WUPE12(value)))
+#define LLWU_BWR_PE4_WUPE12(base, value) (LLWU_WR_PE4_WUPE12(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
+#define LLWU_RD_PE4_WUPE13(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE13_MASK) >> LLWU_PE4_WUPE13_SHIFT)
+#define LLWU_BRD_PE4_WUPE13(base) (LLWU_RD_PE4_WUPE13(base))
+
+/*! @brief Set the WUPE13 field to a new value. */
+#define LLWU_WR_PE4_WUPE13(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE13_MASK, LLWU_PE4_WUPE13(value)))
+#define LLWU_BWR_PE4_WUPE13(base, value) (LLWU_WR_PE4_WUPE13(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
+#define LLWU_RD_PE4_WUPE14(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE14_MASK) >> LLWU_PE4_WUPE14_SHIFT)
+#define LLWU_BRD_PE4_WUPE14(base) (LLWU_RD_PE4_WUPE14(base))
+
+/*! @brief Set the WUPE14 field to a new value. */
+#define LLWU_WR_PE4_WUPE14(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE14_MASK, LLWU_PE4_WUPE14(value)))
+#define LLWU_BWR_PE4_WUPE14(base, value) (LLWU_WR_PE4_WUPE14(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
+#define LLWU_RD_PE4_WUPE15(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE15_MASK) >> LLWU_PE4_WUPE15_SHIFT)
+#define LLWU_BRD_PE4_WUPE15(base) (LLWU_RD_PE4_WUPE15(base))
+
+/*! @brief Set the WUPE15 field to a new value. */
+#define LLWU_WR_PE4_WUPE15(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE15_MASK, LLWU_PE4_WUPE15(value)))
+#define LLWU_BWR_PE4_WUPE15(base, value) (LLWU_WR_PE4_WUPE15(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_ME - LLWU Module Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_ME - LLWU Module Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_ME contains the bits to enable the internal module flag as a wakeup
+ * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
+ * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
+ * reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
+ * RCM implements many of the reset functions for the chip. See the chip's reset
+ * chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_ME register
+ */
+/*@{*/
+#define LLWU_RD_ME(base)         (LLWU_ME_REG(base))
+#define LLWU_WR_ME(base, value)  (LLWU_ME_REG(base) = (value))
+#define LLWU_RMW_ME(base, mask, value) (LLWU_WR_ME(base, (LLWU_RD_ME(base) & ~(mask)) | (value)))
+#define LLWU_SET_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) |  (value)))
+#define LLWU_CLR_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) & ~(value)))
+#define LLWU_TOG_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_ME bitfields
+ */
+
+/*!
+ * @name Register LLWU_ME, field WUME0[0] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME0 field. */
+#define LLWU_RD_ME_WUME0(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME0_MASK) >> LLWU_ME_WUME0_SHIFT)
+#define LLWU_BRD_ME_WUME0(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT))
+
+/*! @brief Set the WUME0 field to a new value. */
+#define LLWU_WR_ME_WUME0(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME0_MASK, LLWU_ME_WUME0(value)))
+#define LLWU_BWR_ME_WUME0(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME1[1] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME1 field. */
+#define LLWU_RD_ME_WUME1(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME1_MASK) >> LLWU_ME_WUME1_SHIFT)
+#define LLWU_BRD_ME_WUME1(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT))
+
+/*! @brief Set the WUME1 field to a new value. */
+#define LLWU_WR_ME_WUME1(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME1_MASK, LLWU_ME_WUME1(value)))
+#define LLWU_BWR_ME_WUME1(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME2[2] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME2 field. */
+#define LLWU_RD_ME_WUME2(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME2_MASK) >> LLWU_ME_WUME2_SHIFT)
+#define LLWU_BRD_ME_WUME2(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT))
+
+/*! @brief Set the WUME2 field to a new value. */
+#define LLWU_WR_ME_WUME2(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME2_MASK, LLWU_ME_WUME2(value)))
+#define LLWU_BWR_ME_WUME2(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME3[3] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME3 field. */
+#define LLWU_RD_ME_WUME3(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME3_MASK) >> LLWU_ME_WUME3_SHIFT)
+#define LLWU_BRD_ME_WUME3(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT))
+
+/*! @brief Set the WUME3 field to a new value. */
+#define LLWU_WR_ME_WUME3(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME3_MASK, LLWU_ME_WUME3(value)))
+#define LLWU_BWR_ME_WUME3(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME4[4] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME4 field. */
+#define LLWU_RD_ME_WUME4(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME4_MASK) >> LLWU_ME_WUME4_SHIFT)
+#define LLWU_BRD_ME_WUME4(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT))
+
+/*! @brief Set the WUME4 field to a new value. */
+#define LLWU_WR_ME_WUME4(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME4_MASK, LLWU_ME_WUME4(value)))
+#define LLWU_BWR_ME_WUME4(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME5[5] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME5 field. */
+#define LLWU_RD_ME_WUME5(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME5_MASK) >> LLWU_ME_WUME5_SHIFT)
+#define LLWU_BRD_ME_WUME5(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT))
+
+/*! @brief Set the WUME5 field to a new value. */
+#define LLWU_WR_ME_WUME5(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME5_MASK, LLWU_ME_WUME5(value)))
+#define LLWU_BWR_ME_WUME5(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME6[6] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME6 field. */
+#define LLWU_RD_ME_WUME6(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME6_MASK) >> LLWU_ME_WUME6_SHIFT)
+#define LLWU_BRD_ME_WUME6(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT))
+
+/*! @brief Set the WUME6 field to a new value. */
+#define LLWU_WR_ME_WUME6(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME6_MASK, LLWU_ME_WUME6(value)))
+#define LLWU_BWR_ME_WUME6(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME7[7] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME7 field. */
+#define LLWU_RD_ME_WUME7(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME7_MASK) >> LLWU_ME_WUME7_SHIFT)
+#define LLWU_BRD_ME_WUME7(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT))
+
+/*! @brief Set the WUME7 field to a new value. */
+#define LLWU_WR_ME_WUME7(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME7_MASK, LLWU_ME_WUME7(value)))
+#define LLWU_BWR_ME_WUME7(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F1 - LLWU Flag 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F1 - LLWU Flag 1 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F1 register
+ */
+/*@{*/
+#define LLWU_RD_F1(base)         (LLWU_F1_REG(base))
+#define LLWU_WR_F1(base, value)  (LLWU_F1_REG(base) = (value))
+#define LLWU_RMW_F1(base, mask, value) (LLWU_WR_F1(base, (LLWU_RD_F1(base) & ~(mask)) | (value)))
+#define LLWU_SET_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) |  (value)))
+#define LLWU_CLR_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) & ~(value)))
+#define LLWU_TOG_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F1, field WUF0[0] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF0.
+ *
+ * Values:
+ * - 0b0 - LLWU_P0 input was not a wakeup source
+ * - 0b1 - LLWU_P0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF0 field. */
+#define LLWU_RD_F1_WUF0(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF0_MASK) >> LLWU_F1_WUF0_SHIFT)
+#define LLWU_BRD_F1_WUF0(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT))
+
+/*! @brief Set the WUF0 field to a new value. */
+#define LLWU_WR_F1_WUF0(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF0(value)))
+#define LLWU_BWR_F1_WUF0(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF1[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF1.
+ *
+ * Values:
+ * - 0b0 - LLWU_P1 input was not a wakeup source
+ * - 0b1 - LLWU_P1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF1 field. */
+#define LLWU_RD_F1_WUF1(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF1_MASK) >> LLWU_F1_WUF1_SHIFT)
+#define LLWU_BRD_F1_WUF1(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT))
+
+/*! @brief Set the WUF1 field to a new value. */
+#define LLWU_WR_F1_WUF1(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF1_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF1(value)))
+#define LLWU_BWR_F1_WUF1(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF2[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF2.
+ *
+ * Values:
+ * - 0b0 - LLWU_P2 input was not a wakeup source
+ * - 0b1 - LLWU_P2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF2 field. */
+#define LLWU_RD_F1_WUF2(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF2_MASK) >> LLWU_F1_WUF2_SHIFT)
+#define LLWU_BRD_F1_WUF2(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT))
+
+/*! @brief Set the WUF2 field to a new value. */
+#define LLWU_WR_F1_WUF2(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF2_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF2(value)))
+#define LLWU_BWR_F1_WUF2(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF3[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF3.
+ *
+ * Values:
+ * - 0b0 - LLWU_P3 input was not a wake-up source
+ * - 0b1 - LLWU_P3 input was a wake-up source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF3 field. */
+#define LLWU_RD_F1_WUF3(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF3_MASK) >> LLWU_F1_WUF3_SHIFT)
+#define LLWU_BRD_F1_WUF3(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT))
+
+/*! @brief Set the WUF3 field to a new value. */
+#define LLWU_WR_F1_WUF3(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF3_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF3(value)))
+#define LLWU_BWR_F1_WUF3(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF4[4] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF4.
+ *
+ * Values:
+ * - 0b0 - LLWU_P4 input was not a wakeup source
+ * - 0b1 - LLWU_P4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF4 field. */
+#define LLWU_RD_F1_WUF4(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF4_MASK) >> LLWU_F1_WUF4_SHIFT)
+#define LLWU_BRD_F1_WUF4(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT))
+
+/*! @brief Set the WUF4 field to a new value. */
+#define LLWU_WR_F1_WUF4(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF4_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF4(value)))
+#define LLWU_BWR_F1_WUF4(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF5[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF5.
+ *
+ * Values:
+ * - 0b0 - LLWU_P5 input was not a wakeup source
+ * - 0b1 - LLWU_P5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF5 field. */
+#define LLWU_RD_F1_WUF5(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF5_MASK) >> LLWU_F1_WUF5_SHIFT)
+#define LLWU_BRD_F1_WUF5(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT))
+
+/*! @brief Set the WUF5 field to a new value. */
+#define LLWU_WR_F1_WUF5(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF5_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF5(value)))
+#define LLWU_BWR_F1_WUF5(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF6[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF6.
+ *
+ * Values:
+ * - 0b0 - LLWU_P6 input was not a wakeup source
+ * - 0b1 - LLWU_P6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF6 field. */
+#define LLWU_RD_F1_WUF6(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF6_MASK) >> LLWU_F1_WUF6_SHIFT)
+#define LLWU_BRD_F1_WUF6(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT))
+
+/*! @brief Set the WUF6 field to a new value. */
+#define LLWU_WR_F1_WUF6(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF6_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF6(value)))
+#define LLWU_BWR_F1_WUF6(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF7[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF7.
+ *
+ * Values:
+ * - 0b0 - LLWU_P7 input was not a wakeup source
+ * - 0b1 - LLWU_P7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF7 field. */
+#define LLWU_RD_F1_WUF7(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF7_MASK) >> LLWU_F1_WUF7_SHIFT)
+#define LLWU_BRD_F1_WUF7(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT))
+
+/*! @brief Set the WUF7 field to a new value. */
+#define LLWU_WR_F1_WUF7(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF7_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK), LLWU_F1_WUF7(value)))
+#define LLWU_BWR_F1_WUF7(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F2 - LLWU Flag 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F2 - LLWU Flag 2 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F2 register
+ */
+/*@{*/
+#define LLWU_RD_F2(base)         (LLWU_F2_REG(base))
+#define LLWU_WR_F2(base, value)  (LLWU_F2_REG(base) = (value))
+#define LLWU_RMW_F2(base, mask, value) (LLWU_WR_F2(base, (LLWU_RD_F2(base) & ~(mask)) | (value)))
+#define LLWU_SET_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) |  (value)))
+#define LLWU_CLR_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) & ~(value)))
+#define LLWU_TOG_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F2, field WUF8[0] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF8.
+ *
+ * Values:
+ * - 0b0 - LLWU_P8 input was not a wakeup source
+ * - 0b1 - LLWU_P8 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF8 field. */
+#define LLWU_RD_F2_WUF8(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF8_MASK) >> LLWU_F2_WUF8_SHIFT)
+#define LLWU_BRD_F2_WUF8(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT))
+
+/*! @brief Set the WUF8 field to a new value. */
+#define LLWU_WR_F2_WUF8(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF8(value)))
+#define LLWU_BWR_F2_WUF8(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF9[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF9.
+ *
+ * Values:
+ * - 0b0 - LLWU_P9 input was not a wakeup source
+ * - 0b1 - LLWU_P9 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF9 field. */
+#define LLWU_RD_F2_WUF9(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF9_MASK) >> LLWU_F2_WUF9_SHIFT)
+#define LLWU_BRD_F2_WUF9(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT))
+
+/*! @brief Set the WUF9 field to a new value. */
+#define LLWU_WR_F2_WUF9(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF9_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF9(value)))
+#define LLWU_BWR_F2_WUF9(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF10[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF10.
+ *
+ * Values:
+ * - 0b0 - LLWU_P10 input was not a wakeup source
+ * - 0b1 - LLWU_P10 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF10 field. */
+#define LLWU_RD_F2_WUF10(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF10_MASK) >> LLWU_F2_WUF10_SHIFT)
+#define LLWU_BRD_F2_WUF10(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT))
+
+/*! @brief Set the WUF10 field to a new value. */
+#define LLWU_WR_F2_WUF10(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF10_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF10(value)))
+#define LLWU_BWR_F2_WUF10(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF11[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF11.
+ *
+ * Values:
+ * - 0b0 - LLWU_P11 input was not a wakeup source
+ * - 0b1 - LLWU_P11 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF11 field. */
+#define LLWU_RD_F2_WUF11(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF11_MASK) >> LLWU_F2_WUF11_SHIFT)
+#define LLWU_BRD_F2_WUF11(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT))
+
+/*! @brief Set the WUF11 field to a new value. */
+#define LLWU_WR_F2_WUF11(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF11_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF11(value)))
+#define LLWU_BWR_F2_WUF11(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF12[4] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF12.
+ *
+ * Values:
+ * - 0b0 - LLWU_P12 input was not a wakeup source
+ * - 0b1 - LLWU_P12 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF12 field. */
+#define LLWU_RD_F2_WUF12(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF12_MASK) >> LLWU_F2_WUF12_SHIFT)
+#define LLWU_BRD_F2_WUF12(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT))
+
+/*! @brief Set the WUF12 field to a new value. */
+#define LLWU_WR_F2_WUF12(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF12_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF12(value)))
+#define LLWU_BWR_F2_WUF12(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF13[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF13.
+ *
+ * Values:
+ * - 0b0 - LLWU_P13 input was not a wakeup source
+ * - 0b1 - LLWU_P13 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF13 field. */
+#define LLWU_RD_F2_WUF13(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF13_MASK) >> LLWU_F2_WUF13_SHIFT)
+#define LLWU_BRD_F2_WUF13(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT))
+
+/*! @brief Set the WUF13 field to a new value. */
+#define LLWU_WR_F2_WUF13(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF13_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF13(value)))
+#define LLWU_BWR_F2_WUF13(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF14[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF14.
+ *
+ * Values:
+ * - 0b0 - LLWU_P14 input was not a wakeup source
+ * - 0b1 - LLWU_P14 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF14 field. */
+#define LLWU_RD_F2_WUF14(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF14_MASK) >> LLWU_F2_WUF14_SHIFT)
+#define LLWU_BRD_F2_WUF14(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT))
+
+/*! @brief Set the WUF14 field to a new value. */
+#define LLWU_WR_F2_WUF14(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF14_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF14(value)))
+#define LLWU_BWR_F2_WUF14(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF15[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF15.
+ *
+ * Values:
+ * - 0b0 - LLWU_P15 input was not a wakeup source
+ * - 0b1 - LLWU_P15 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF15 field. */
+#define LLWU_RD_F2_WUF15(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF15_MASK) >> LLWU_F2_WUF15_SHIFT)
+#define LLWU_BRD_F2_WUF15(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT))
+
+/*! @brief Set the WUF15 field to a new value. */
+#define LLWU_WR_F2_WUF15(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF15_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK), LLWU_F2_WUF15(value)))
+#define LLWU_BWR_F2_WUF15(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F3 - LLWU Flag 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F3 - LLWU Flag 3 register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
+ * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
+ * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
+ * For internal peripherals that are capable of running in a low-leakage power
+ * mode, such as a real time clock module or CMP module, the flag from the
+ * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
+ * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
+ * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
+ * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
+ * the IntroductionInformation found here describes the registers of the Reset
+ * Control Module (RCM). The RCM implements many of the reset functions for the
+ * chip. See the chip's reset chapter for more information. details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F3 register
+ */
+/*@{*/
+#define LLWU_RD_F3(base)         (LLWU_F3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F3, field MWUF0[0] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 0 input was not a wakeup source
+ * - 0b1 - Module 0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF0 field. */
+#define LLWU_RD_F3_MWUF0(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF0_MASK) >> LLWU_F3_MWUF0_SHIFT)
+#define LLWU_BRD_F3_MWUF0(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF1[1] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 1 input was not a wakeup source
+ * - 0b1 - Module 1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF1 field. */
+#define LLWU_RD_F3_MWUF1(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF1_MASK) >> LLWU_F3_MWUF1_SHIFT)
+#define LLWU_BRD_F3_MWUF1(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF2[2] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 2 input was not a wakeup source
+ * - 0b1 - Module 2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF2 field. */
+#define LLWU_RD_F3_MWUF2(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF2_MASK) >> LLWU_F3_MWUF2_SHIFT)
+#define LLWU_BRD_F3_MWUF2(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF2_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF3[3] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 3 input was not a wakeup source
+ * - 0b1 - Module 3 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF3 field. */
+#define LLWU_RD_F3_MWUF3(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF3_MASK) >> LLWU_F3_MWUF3_SHIFT)
+#define LLWU_BRD_F3_MWUF3(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF3_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF4[4] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 4 input was not a wakeup source
+ * - 0b1 - Module 4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF4 field. */
+#define LLWU_RD_F3_MWUF4(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF4_MASK) >> LLWU_F3_MWUF4_SHIFT)
+#define LLWU_BRD_F3_MWUF4(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF4_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF5[5] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 5 input was not a wakeup source
+ * - 0b1 - Module 5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF5 field. */
+#define LLWU_RD_F3_MWUF5(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF5_MASK) >> LLWU_F3_MWUF5_SHIFT)
+#define LLWU_BRD_F3_MWUF5(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF5_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF6[6] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 6 input was not a wakeup source
+ * - 0b1 - Module 6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF6 field. */
+#define LLWU_RD_F3_MWUF6(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF6_MASK) >> LLWU_F3_MWUF6_SHIFT)
+#define LLWU_BRD_F3_MWUF6(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF6_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF7[7] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 7 input was not a wakeup source
+ * - 0b1 - Module 7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF7 field. */
+#define LLWU_RD_F3_MWUF7(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF7_MASK) >> LLWU_F3_MWUF7_SHIFT)
+#define LLWU_BRD_F3_MWUF7(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF7_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT1 - LLWU Pin Filter 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT1 is a control and status register that is used to enable/disable
+ * the digital filter 1 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT1 register
+ */
+/*@{*/
+#define LLWU_RD_FILT1(base)      (LLWU_FILT1_REG(base))
+#define LLWU_WR_FILT1(base, value) (LLWU_FILT1_REG(base) = (value))
+#define LLWU_RMW_FILT1(base, mask, value) (LLWU_WR_FILT1(base, (LLWU_RD_FILT1(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) |  (value)))
+#define LLWU_CLR_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) & ~(value)))
+#define LLWU_TOG_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0b0000 - Select LLWU_P0 for filter
+ * - 0b1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
+#define LLWU_RD_FILT1_FILTSEL(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTSEL_MASK) >> LLWU_FILT1_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT1_FILTSEL(base) (LLWU_RD_FILT1_FILTSEL(base))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT1_FILTSEL(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTSEL(value)))
+#define LLWU_BWR_FILT1_FILTSEL(base, value) (LLWU_WR_FILT1_FILTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 0b00 - Filter disabled
+ * - 0b01 - Filter posedge detect enabled
+ * - 0b10 - Filter negedge detect enabled
+ * - 0b11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTE field. */
+#define LLWU_RD_FILT1_FILTE(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTE_MASK) >> LLWU_FILT1_FILTE_SHIFT)
+#define LLWU_BRD_FILT1_FILTE(base) (LLWU_RD_FILT1_FILTE(base))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT1_FILTE(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTE_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTE(value)))
+#define LLWU_BWR_FILT1_FILTE(base, value) (LLWU_WR_FILT1_FILTE(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0b0 - Pin Filter 1 was not a wakeup source
+ * - 0b1 - Pin Filter 1 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTF field. */
+#define LLWU_RD_FILT1_FILTF(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTF_MASK) >> LLWU_FILT1_FILTF_SHIFT)
+#define LLWU_BRD_FILT1_FILTF(base) (BITBAND_ACCESS8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT1_FILTF(base, value) (LLWU_RMW_FILT1(base, LLWU_FILT1_FILTF_MASK, LLWU_FILT1_FILTF(value)))
+#define LLWU_BWR_FILT1_FILTF(base, value) (BITBAND_ACCESS8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT2 - LLWU Pin Filter 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT2 is a control and status register that is used to enable/disable
+ * the digital filter 2 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT2 register
+ */
+/*@{*/
+#define LLWU_RD_FILT2(base)      (LLWU_FILT2_REG(base))
+#define LLWU_WR_FILT2(base, value) (LLWU_FILT2_REG(base) = (value))
+#define LLWU_RMW_FILT2(base, mask, value) (LLWU_WR_FILT2(base, (LLWU_RD_FILT2(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) |  (value)))
+#define LLWU_CLR_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) & ~(value)))
+#define LLWU_TOG_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0b0000 - Select LLWU_P0 for filter
+ * - 0b1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
+#define LLWU_RD_FILT2_FILTSEL(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTSEL_MASK) >> LLWU_FILT2_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT2_FILTSEL(base) (LLWU_RD_FILT2_FILTSEL(base))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT2_FILTSEL(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTSEL_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTSEL(value)))
+#define LLWU_BWR_FILT2_FILTSEL(base, value) (LLWU_WR_FILT2_FILTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 0b00 - Filter disabled
+ * - 0b01 - Filter posedge detect enabled
+ * - 0b10 - Filter negedge detect enabled
+ * - 0b11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTE field. */
+#define LLWU_RD_FILT2_FILTE(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTE_MASK) >> LLWU_FILT2_FILTE_SHIFT)
+#define LLWU_BRD_FILT2_FILTE(base) (LLWU_RD_FILT2_FILTE(base))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT2_FILTE(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTE_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTE(value)))
+#define LLWU_BWR_FILT2_FILTE(base, value) (LLWU_WR_FILT2_FILTE(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0b0 - Pin Filter 2 was not a wakeup source
+ * - 0b1 - Pin Filter 2 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTF field. */
+#define LLWU_RD_FILT2_FILTF(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTF_MASK) >> LLWU_FILT2_FILTF_SHIFT)
+#define LLWU_BRD_FILT2_FILTF(base) (BITBAND_ACCESS8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT2_FILTF(base, value) (LLWU_RMW_FILT2(base, LLWU_FILT2_FILTF_MASK, LLWU_FILT2_FILTF(value)))
+#define LLWU_BWR_FILT2_FILTF(base, value) (BITBAND_ACCESS8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_RST - LLWU Reset Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_RST - LLWU Reset Enable register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * LLWU_RST is a control register that is used to enable/disable the digital
+ * filter for the external pin detect and RESET pin. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_RST register
+ */
+/*@{*/
+#define LLWU_RD_RST(base)        (LLWU_RST_REG(base))
+#define LLWU_WR_RST(base, value) (LLWU_RST_REG(base) = (value))
+#define LLWU_RMW_RST(base, mask, value) (LLWU_WR_RST(base, (LLWU_RD_RST(base) & ~(mask)) | (value)))
+#define LLWU_SET_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) |  (value)))
+#define LLWU_CLR_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) & ~(value)))
+#define LLWU_TOG_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_RST bitfields
+ */
+
+/*!
+ * @name Register LLWU_RST, field RSTFILT[0] (RW)
+ *
+ * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
+ * VLLS1 modes.
+ *
+ * Values:
+ * - 0b0 - Filter not enabled
+ * - 0b1 - Filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_RST_RSTFILT field. */
+#define LLWU_RD_RST_RSTFILT(base) ((LLWU_RST_REG(base) & LLWU_RST_RSTFILT_MASK) >> LLWU_RST_RSTFILT_SHIFT)
+#define LLWU_BRD_RST_RSTFILT(base) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_RSTFILT_SHIFT))
+
+/*! @brief Set the RSTFILT field to a new value. */
+#define LLWU_WR_RST_RSTFILT(base, value) (LLWU_RMW_RST(base, LLWU_RST_RSTFILT_MASK, LLWU_RST_RSTFILT(value)))
+#define LLWU_BWR_RST_RSTFILT(base, value) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_RSTFILT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_RST, field LLRSTE[1] (RW)
+ *
+ * This bit must be set to allow the device to be reset while in a low-leakage
+ * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
+ * also be enabled in the explicit port mux control.
+ *
+ * Values:
+ * - 0b0 - RESET pin not enabled as a leakage mode exit source
+ * - 0b1 - RESET pin enabled as a low leakage mode exit source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_RST_LLRSTE field. */
+#define LLWU_RD_RST_LLRSTE(base) ((LLWU_RST_REG(base) & LLWU_RST_LLRSTE_MASK) >> LLWU_RST_LLRSTE_SHIFT)
+#define LLWU_BRD_RST_LLRSTE(base) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_LLRSTE_SHIFT))
+
+/*! @brief Set the LLRSTE field to a new value. */
+#define LLWU_WR_RST_LLRSTE(base, value) (LLWU_RMW_RST(base, LLWU_RST_LLRSTE_MASK, LLWU_RST_LLRSTE(value)))
+#define LLWU_BWR_RST_LLRSTE(base, value) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_LLRSTE_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 LPTMR
+ *
+ * Low Power Timer
+ *
+ * Registers defined in this header file:
+ * - LPTMR_CSR - Low Power Timer Control Status Register
+ * - LPTMR_PSR - Low Power Timer Prescale Register
+ * - LPTMR_CMR - Low Power Timer Compare Register
+ * - LPTMR_CNR - Low Power Timer Counter Register
+ */
+
+#define LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
+#define LPTMR0_IDX (0U) /*!< Instance number for LPTMR0. */
+
+/*******************************************************************************
+ * LPTMR_CSR - Low Power Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CSR - Low Power Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CSR register
+ */
+/*@{*/
+#define LPTMR_RD_CSR(base)       (LPTMR_CSR_REG(base))
+#define LPTMR_WR_CSR(base, value) (LPTMR_CSR_REG(base) = (value))
+#define LPTMR_RMW_CSR(base, mask, value) (LPTMR_WR_CSR(base, (LPTMR_RD_CSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) |  (value)))
+#define LPTMR_CLR_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) & ~(value)))
+#define LPTMR_TOG_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CSR, field TEN[0] (RW)
+ *
+ * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
+ * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
+ * CSR[5:1] must not be altered.
+ *
+ * Values:
+ * - 0b0 - LPTMR is disabled and internal logic is reset.
+ * - 0b1 - LPTMR is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TEN field. */
+#define LPTMR_RD_CSR_TEN(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TEN_MASK) >> LPTMR_CSR_TEN_SHIFT)
+#define LPTMR_BRD_CSR_TEN(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT))
+
+/*! @brief Set the TEN field to a new value. */
+#define LPTMR_WR_CSR_TEN(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TEN_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TEN(value)))
+#define LPTMR_BWR_CSR_TEN(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TMS[1] (RW)
+ *
+ * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
+ * disabled.
+ *
+ * Values:
+ * - 0b0 - Time Counter mode.
+ * - 0b1 - Pulse Counter mode.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TMS field. */
+#define LPTMR_RD_CSR_TMS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TMS_MASK) >> LPTMR_CSR_TMS_SHIFT)
+#define LPTMR_BRD_CSR_TMS(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT))
+
+/*! @brief Set the TMS field to a new value. */
+#define LPTMR_WR_CSR_TMS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TMS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TMS(value)))
+#define LPTMR_BWR_CSR_TMS(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TFC[2] (RW)
+ *
+ * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
+ * TFC configures the CNR to reset on overflow. TFC must be altered only when the
+ * LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - CNR is reset whenever TCF is set.
+ * - 0b1 - CNR is reset on overflow.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TFC field. */
+#define LPTMR_RD_CSR_TFC(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TFC_MASK) >> LPTMR_CSR_TFC_SHIFT)
+#define LPTMR_BRD_CSR_TFC(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT))
+
+/*! @brief Set the TFC field to a new value. */
+#define LPTMR_WR_CSR_TFC(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TFC_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TFC(value)))
+#define LPTMR_BWR_CSR_TFC(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPP[3] (RW)
+ *
+ * Configures the polarity of the input source in Pulse Counter mode. TPP must
+ * be changed only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - Pulse Counter input source is active-high, and the CNR will increment
+ *     on the rising-edge.
+ * - 0b1 - Pulse Counter input source is active-low, and the CNR will increment
+ *     on the falling-edge.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPP field. */
+#define LPTMR_RD_CSR_TPP(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPP_MASK) >> LPTMR_CSR_TPP_SHIFT)
+#define LPTMR_BRD_CSR_TPP(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT))
+
+/*! @brief Set the TPP field to a new value. */
+#define LPTMR_WR_CSR_TPP(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPP_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPP(value)))
+#define LPTMR_BWR_CSR_TPP(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPS[5:4] (RW)
+ *
+ * Configures the input source to be used in Pulse Counter mode. TPS must be
+ * altered only when the LPTMR is disabled. The input connections vary by device.
+ * See the chip configuration details for information on the connections to these
+ * inputs.
+ *
+ * Values:
+ * - 0b00 - Pulse counter input 0 is selected.
+ * - 0b01 - Pulse counter input 1 is selected.
+ * - 0b10 - Pulse counter input 2 is selected.
+ * - 0b11 - Pulse counter input 3 is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPS field. */
+#define LPTMR_RD_CSR_TPS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPS_MASK) >> LPTMR_CSR_TPS_SHIFT)
+#define LPTMR_BRD_CSR_TPS(base) (LPTMR_RD_CSR_TPS(base))
+
+/*! @brief Set the TPS field to a new value. */
+#define LPTMR_WR_CSR_TPS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPS(value)))
+#define LPTMR_BWR_CSR_TPS(base, value) (LPTMR_WR_CSR_TPS(base, value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TIE[6] (RW)
+ *
+ * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
+ *
+ * Values:
+ * - 0b0 - Timer interrupt disabled.
+ * - 0b1 - Timer interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TIE field. */
+#define LPTMR_RD_CSR_TIE(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TIE_MASK) >> LPTMR_CSR_TIE_SHIFT)
+#define LPTMR_BRD_CSR_TIE(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define LPTMR_WR_CSR_TIE(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TIE_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TIE(value)))
+#define LPTMR_BWR_CSR_TIE(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TCF[7] (W1C)
+ *
+ * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
+ * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
+ *
+ * Values:
+ * - 0b0 - The value of CNR is not equal to CMR and increments.
+ * - 0b1 - The value of CNR is equal to CMR and increments.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TCF field. */
+#define LPTMR_RD_CSR_TCF(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TCF_MASK) >> LPTMR_CSR_TCF_SHIFT)
+#define LPTMR_BRD_CSR_TCF(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT))
+
+/*! @brief Set the TCF field to a new value. */
+#define LPTMR_WR_CSR_TCF(base, value) (LPTMR_RMW_CSR(base, LPTMR_CSR_TCF_MASK, LPTMR_CSR_TCF(value)))
+#define LPTMR_BWR_CSR_TCF(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_PSR - Low Power Timer Prescale Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_PSR - Low Power Timer Prescale Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_PSR register
+ */
+/*@{*/
+#define LPTMR_RD_PSR(base)       (LPTMR_PSR_REG(base))
+#define LPTMR_WR_PSR(base, value) (LPTMR_PSR_REG(base) = (value))
+#define LPTMR_RMW_PSR(base, mask, value) (LPTMR_WR_PSR(base, (LPTMR_RD_PSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) |  (value)))
+#define LPTMR_CLR_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) & ~(value)))
+#define LPTMR_TOG_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_PSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_PSR, field PCS[1:0] (RW)
+ *
+ * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
+ * be altered only when the LPTMR is disabled. The clock connections vary by
+ * device. See the chip configuration details for information on the connections to
+ * these inputs.
+ *
+ * Values:
+ * - 0b00 - Prescaler/glitch filter clock 0 selected.
+ * - 0b01 - Prescaler/glitch filter clock 1 selected.
+ * - 0b10 - Prescaler/glitch filter clock 2 selected.
+ * - 0b11 - Prescaler/glitch filter clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PCS field. */
+#define LPTMR_RD_PSR_PCS(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PCS_MASK) >> LPTMR_PSR_PCS_SHIFT)
+#define LPTMR_BRD_PSR_PCS(base) (LPTMR_RD_PSR_PCS(base))
+
+/*! @brief Set the PCS field to a new value. */
+#define LPTMR_WR_PSR_PCS(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PCS_MASK, LPTMR_PSR_PCS(value)))
+#define LPTMR_BWR_PSR_PCS(base, value) (LPTMR_WR_PSR_PCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PBYP[2] (RW)
+ *
+ * When PBYP is set, the selected prescaler clock in Time Counter mode or
+ * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
+ * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
+ * must be altered only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - Prescaler/glitch filter is enabled.
+ * - 0b1 - Prescaler/glitch filter is bypassed.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PBYP field. */
+#define LPTMR_RD_PSR_PBYP(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PBYP_MASK) >> LPTMR_PSR_PBYP_SHIFT)
+#define LPTMR_BRD_PSR_PBYP(base) (BITBAND_ACCESS32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT))
+
+/*! @brief Set the PBYP field to a new value. */
+#define LPTMR_WR_PSR_PBYP(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PBYP_MASK, LPTMR_PSR_PBYP(value)))
+#define LPTMR_BWR_PSR_PBYP(base, value) (BITBAND_ACCESS32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
+ *
+ * Configures the size of the Prescaler in Time Counter mode or width of the
+ * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
+ * is disabled.
+ *
+ * Values:
+ * - 0b0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
+ *     support this configuration.
+ * - 0b0001 - Prescaler divides the prescaler clock by 4; glitch filter
+ *     recognizes change on input pin after 2 rising clock edges.
+ * - 0b0010 - Prescaler divides the prescaler clock by 8; glitch filter
+ *     recognizes change on input pin after 4 rising clock edges.
+ * - 0b0011 - Prescaler divides the prescaler clock by 16; glitch filter
+ *     recognizes change on input pin after 8 rising clock edges.
+ * - 0b0100 - Prescaler divides the prescaler clock by 32; glitch filter
+ *     recognizes change on input pin after 16 rising clock edges.
+ * - 0b0101 - Prescaler divides the prescaler clock by 64; glitch filter
+ *     recognizes change on input pin after 32 rising clock edges.
+ * - 0b0110 - Prescaler divides the prescaler clock by 128; glitch filter
+ *     recognizes change on input pin after 64 rising clock edges.
+ * - 0b0111 - Prescaler divides the prescaler clock by 256; glitch filter
+ *     recognizes change on input pin after 128 rising clock edges.
+ * - 0b1000 - Prescaler divides the prescaler clock by 512; glitch filter
+ *     recognizes change on input pin after 256 rising clock edges.
+ * - 0b1001 - Prescaler divides the prescaler clock by 1024; glitch filter
+ *     recognizes change on input pin after 512 rising clock edges.
+ * - 0b1010 - Prescaler divides the prescaler clock by 2048; glitch filter
+ *     recognizes change on input pin after 1024 rising clock edges.
+ * - 0b1011 - Prescaler divides the prescaler clock by 4096; glitch filter
+ *     recognizes change on input pin after 2048 rising clock edges.
+ * - 0b1100 - Prescaler divides the prescaler clock by 8192; glitch filter
+ *     recognizes change on input pin after 4096 rising clock edges.
+ * - 0b1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
+ *     recognizes change on input pin after 8192 rising clock edges.
+ * - 0b1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
+ *     recognizes change on input pin after 16,384 rising clock edges.
+ * - 0b1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
+ *     recognizes change on input pin after 32,768 rising clock edges.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
+#define LPTMR_RD_PSR_PRESCALE(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PRESCALE_MASK) >> LPTMR_PSR_PRESCALE_SHIFT)
+#define LPTMR_BRD_PSR_PRESCALE(base) (LPTMR_RD_PSR_PRESCALE(base))
+
+/*! @brief Set the PRESCALE field to a new value. */
+#define LPTMR_WR_PSR_PRESCALE(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PRESCALE_MASK, LPTMR_PSR_PRESCALE(value)))
+#define LPTMR_BWR_PSR_PRESCALE(base, value) (LPTMR_WR_PSR_PRESCALE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CMR - Low Power Timer Compare Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CMR - Low Power Timer Compare Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CMR register
+ */
+/*@{*/
+#define LPTMR_RD_CMR(base)       (LPTMR_CMR_REG(base))
+#define LPTMR_WR_CMR(base, value) (LPTMR_CMR_REG(base) = (value))
+#define LPTMR_RMW_CMR(base, mask, value) (LPTMR_WR_CMR(base, (LPTMR_RD_CMR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) |  (value)))
+#define LPTMR_CLR_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) & ~(value)))
+#define LPTMR_TOG_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CMR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
+ *
+ * When the LPTMR is enabled and the CNR equals the value in the CMR and
+ * increments, TCF is set and the hardware trigger asserts until the next time the CNR
+ * increments. If the CMR is 0, the hardware trigger will remain asserted until
+ * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
+ * when TCF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
+#define LPTMR_RD_CMR_COMPARE(base) ((LPTMR_CMR_REG(base) & LPTMR_CMR_COMPARE_MASK) >> LPTMR_CMR_COMPARE_SHIFT)
+#define LPTMR_BRD_CMR_COMPARE(base) (LPTMR_RD_CMR_COMPARE(base))
+
+/*! @brief Set the COMPARE field to a new value. */
+#define LPTMR_WR_CMR_COMPARE(base, value) (LPTMR_RMW_CMR(base, LPTMR_CMR_COMPARE_MASK, LPTMR_CMR_COMPARE(value)))
+#define LPTMR_BWR_CMR_COMPARE(base, value) (LPTMR_WR_CMR_COMPARE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CNR - Low Power Timer Counter Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CNR - Low Power Timer Counter Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CNR register
+ */
+/*@{*/
+#define LPTMR_RD_CNR(base)       (LPTMR_CNR_REG(base))
+#define LPTMR_WR_CNR(base, value) (LPTMR_CNR_REG(base) = (value))
+#define LPTMR_RMW_CNR(base, mask, value) (LPTMR_WR_CNR(base, (LPTMR_RD_CNR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) |  (value)))
+#define LPTMR_CLR_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) & ~(value)))
+#define LPTMR_TOG_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CNR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
+#define LPTMR_RD_CNR_COUNTER(base) ((LPTMR_CNR_REG(base) & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT)
+#define LPTMR_BRD_CNR_COUNTER(base) (LPTMR_RD_CNR_COUNTER(base))
+
+/*! @brief Set the COUNTER field to a new value. */
+#define LPTMR_WR_CNR_COUNTER(base, value) (LPTMR_RMW_CNR(base, LPTMR_CNR_COUNTER_MASK, LPTMR_CNR_COUNTER(value)))
+#define LPTMR_BWR_CNR_COUNTER(base, value) (LPTMR_WR_CNR_COUNTER(base, value))
+/*@}*/
+
+/*
+ * MK64F12 MCG
+ *
+ * Multipurpose Clock Generator module
+ *
+ * Registers defined in this header file:
+ * - MCG_C1 - MCG Control 1 Register
+ * - MCG_C2 - MCG Control 2 Register
+ * - MCG_C3 - MCG Control 3 Register
+ * - MCG_C4 - MCG Control 4 Register
+ * - MCG_C5 - MCG Control 5 Register
+ * - MCG_C6 - MCG Control 6 Register
+ * - MCG_S - MCG Status Register
+ * - MCG_SC - MCG Status and Control Register
+ * - MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ * - MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ * - MCG_C7 - MCG Control 7 Register
+ * - MCG_C8 - MCG Control 8 Register
+ */
+
+#define MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */
+#define MCG_IDX (0U) /*!< Instance number for MCG. */
+
+/*******************************************************************************
+ * MCG_C1 - MCG Control 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C1 - MCG Control 1 Register (RW)
+ *
+ * Reset value: 0x04U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C1 register
+ */
+/*@{*/
+#define MCG_RD_C1(base)          (MCG_C1_REG(base))
+#define MCG_WR_C1(base, value)   (MCG_C1_REG(base) = (value))
+#define MCG_RMW_C1(base, mask, value) (MCG_WR_C1(base, (MCG_RD_C1(base) & ~(mask)) | (value)))
+#define MCG_SET_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) |  (value)))
+#define MCG_CLR_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) & ~(value)))
+#define MCG_TOG_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C1 bitfields
+ */
+
+/*!
+ * @name Register MCG_C1, field IREFSTEN[0] (RW)
+ *
+ * Controls whether or not the internal reference clock remains enabled when the
+ * MCG enters Stop mode.
+ *
+ * Values:
+ * - 0b0 - Internal reference clock is disabled in Stop mode.
+ * - 0b1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
+ *     if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFSTEN field. */
+#define MCG_RD_C1_IREFSTEN(base) ((MCG_C1_REG(base) & MCG_C1_IREFSTEN_MASK) >> MCG_C1_IREFSTEN_SHIFT)
+#define MCG_BRD_C1_IREFSTEN(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT))
+
+/*! @brief Set the IREFSTEN field to a new value. */
+#define MCG_WR_C1_IREFSTEN(base, value) (MCG_RMW_C1(base, MCG_C1_IREFSTEN_MASK, MCG_C1_IREFSTEN(value)))
+#define MCG_BWR_C1_IREFSTEN(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IRCLKEN[1] (RW)
+ *
+ * Enables the internal reference clock for use as MCGIRCLK.
+ *
+ * Values:
+ * - 0b0 - MCGIRCLK inactive.
+ * - 0b1 - MCGIRCLK active.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IRCLKEN field. */
+#define MCG_RD_C1_IRCLKEN(base) ((MCG_C1_REG(base) & MCG_C1_IRCLKEN_MASK) >> MCG_C1_IRCLKEN_SHIFT)
+#define MCG_BRD_C1_IRCLKEN(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT))
+
+/*! @brief Set the IRCLKEN field to a new value. */
+#define MCG_WR_C1_IRCLKEN(base, value) (MCG_RMW_C1(base, MCG_C1_IRCLKEN_MASK, MCG_C1_IRCLKEN(value)))
+#define MCG_BWR_C1_IRCLKEN(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IREFS[2] (RW)
+ *
+ * Selects the reference clock source for the FLL.
+ *
+ * Values:
+ * - 0b0 - External reference clock is selected.
+ * - 0b1 - The slow internal reference clock is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFS field. */
+#define MCG_RD_C1_IREFS(base) ((MCG_C1_REG(base) & MCG_C1_IREFS_MASK) >> MCG_C1_IREFS_SHIFT)
+#define MCG_BRD_C1_IREFS(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT))
+
+/*! @brief Set the IREFS field to a new value. */
+#define MCG_WR_C1_IREFS(base, value) (MCG_RMW_C1(base, MCG_C1_IREFS_MASK, MCG_C1_IREFS(value)))
+#define MCG_BWR_C1_IREFS(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field FRDIV[5:3] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the FLL.
+ * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
+ * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
+ * not required to meet this range, but it is recommended in the cases when trying
+ * to enter a FLL mode from FBE).
+ *
+ * Values:
+ * - 0b000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
+ *     values, Divide Factor is 32.
+ * - 0b001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
+ *     values, Divide Factor is 64.
+ * - 0b010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
+ *     values, Divide Factor is 128.
+ * - 0b011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
+ *     values, Divide Factor is 256.
+ * - 0b100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
+ *     values, Divide Factor is 512.
+ * - 0b101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
+ *     values, Divide Factor is 1024.
+ * - 0b110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
+ *     values, Divide Factor is 1280 .
+ * - 0b111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other
+ *     RANGE values, Divide Factor is 1536 .
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_FRDIV field. */
+#define MCG_RD_C1_FRDIV(base) ((MCG_C1_REG(base) & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
+#define MCG_BRD_C1_FRDIV(base) (MCG_RD_C1_FRDIV(base))
+
+/*! @brief Set the FRDIV field to a new value. */
+#define MCG_WR_C1_FRDIV(base, value) (MCG_RMW_C1(base, MCG_C1_FRDIV_MASK, MCG_C1_FRDIV(value)))
+#define MCG_BWR_C1_FRDIV(base, value) (MCG_WR_C1_FRDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field CLKS[7:6] (RW)
+ *
+ * Selects the clock source for MCGOUTCLK .
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS
+ *     control bit).
+ * - 0b01 - Encoding 1 - Internal reference clock is selected.
+ * - 0b10 - Encoding 2 - External reference clock is selected.
+ * - 0b11 - Encoding 3 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_CLKS field. */
+#define MCG_RD_C1_CLKS(base) ((MCG_C1_REG(base) & MCG_C1_CLKS_MASK) >> MCG_C1_CLKS_SHIFT)
+#define MCG_BRD_C1_CLKS(base) (MCG_RD_C1_CLKS(base))
+
+/*! @brief Set the CLKS field to a new value. */
+#define MCG_WR_C1_CLKS(base, value) (MCG_RMW_C1(base, MCG_C1_CLKS_MASK, MCG_C1_CLKS(value)))
+#define MCG_BWR_C1_CLKS(base, value) (MCG_WR_C1_CLKS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C2 - MCG Control 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C2 - MCG Control 2 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C2 register
+ */
+/*@{*/
+#define MCG_RD_C2(base)          (MCG_C2_REG(base))
+#define MCG_WR_C2(base, value)   (MCG_C2_REG(base) = (value))
+#define MCG_RMW_C2(base, mask, value) (MCG_WR_C2(base, (MCG_RD_C2(base) & ~(mask)) | (value)))
+#define MCG_SET_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) |  (value)))
+#define MCG_CLR_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) & ~(value)))
+#define MCG_TOG_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C2 bitfields
+ */
+
+/*!
+ * @name Register MCG_C2, field IRCS[0] (RW)
+ *
+ * Selects between the fast or slow internal reference clock source.
+ *
+ * Values:
+ * - 0b0 - Slow internal reference clock selected.
+ * - 0b1 - Fast internal reference clock selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_IRCS field. */
+#define MCG_RD_C2_IRCS(base) ((MCG_C2_REG(base) & MCG_C2_IRCS_MASK) >> MCG_C2_IRCS_SHIFT)
+#define MCG_BRD_C2_IRCS(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT))
+
+/*! @brief Set the IRCS field to a new value. */
+#define MCG_WR_C2_IRCS(base, value) (MCG_RMW_C2(base, MCG_C2_IRCS_MASK, MCG_C2_IRCS(value)))
+#define MCG_BWR_C2_IRCS(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field LP[1] (RW)
+ *
+ * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
+ * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
+ * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
+ * other MCG mode, LP bit has no affect.
+ *
+ * Values:
+ * - 0b0 - FLL or PLL is not disabled in bypass modes.
+ * - 0b1 - FLL or PLL is disabled in bypass modes (lower power)
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_LP field. */
+#define MCG_RD_C2_LP(base)   ((MCG_C2_REG(base) & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
+#define MCG_BRD_C2_LP(base)  (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT))
+
+/*! @brief Set the LP field to a new value. */
+#define MCG_WR_C2_LP(base, value) (MCG_RMW_C2(base, MCG_C2_LP_MASK, MCG_C2_LP(value)))
+#define MCG_BWR_C2_LP(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field EREFS[2] (RW)
+ *
+ * Selects the source for the external reference clock. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0b0 - External reference clock requested.
+ * - 0b1 - Oscillator requested.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_EREFS field. */
+#define MCG_RD_C2_EREFS(base) ((MCG_C2_REG(base) & MCG_C2_EREFS_MASK) >> MCG_C2_EREFS_SHIFT)
+#define MCG_BRD_C2_EREFS(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT))
+
+/*! @brief Set the EREFS field to a new value. */
+#define MCG_WR_C2_EREFS(base, value) (MCG_RMW_C2(base, MCG_C2_EREFS_MASK, MCG_C2_EREFS(value)))
+#define MCG_BWR_C2_EREFS(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field HGO[3] (RW)
+ *
+ * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0b0 - Configure crystal oscillator for low-power operation.
+ * - 0b1 - Configure crystal oscillator for high-gain operation.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_HGO field. */
+#define MCG_RD_C2_HGO(base)  ((MCG_C2_REG(base) & MCG_C2_HGO_MASK) >> MCG_C2_HGO_SHIFT)
+#define MCG_BRD_C2_HGO(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT))
+
+/*! @brief Set the HGO field to a new value. */
+#define MCG_WR_C2_HGO(base, value) (MCG_RMW_C2(base, MCG_C2_HGO_MASK, MCG_C2_HGO(value)))
+#define MCG_BWR_C2_HGO(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field RANGE[5:4] (RW)
+ *
+ * Selects the frequency range for the crystal oscillator or external clock
+ * source. See the Oscillator (OSC) chapter for more details and the device data
+ * sheet for the frequency ranges used.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Low frequency range selected for the crystal oscillator
+ *     .
+ * - 0b01 - Encoding 1 - High frequency range selected for the crystal
+ *     oscillator .
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_RANGE field. */
+#define MCG_RD_C2_RANGE(base) ((MCG_C2_REG(base) & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
+#define MCG_BRD_C2_RANGE(base) (MCG_RD_C2_RANGE(base))
+
+/*! @brief Set the RANGE field to a new value. */
+#define MCG_WR_C2_RANGE(base, value) (MCG_RMW_C2(base, MCG_C2_RANGE_MASK, MCG_C2_RANGE(value)))
+#define MCG_BWR_C2_RANGE(base, value) (MCG_WR_C2_RANGE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field FCFTRIM[6] (RW)
+ *
+ * FCFTRIM controls the smallest adjustment of the fast internal reference clock
+ * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
+ * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_FCFTRIM field. */
+#define MCG_RD_C2_FCFTRIM(base) ((MCG_C2_REG(base) & MCG_C2_FCFTRIM_MASK) >> MCG_C2_FCFTRIM_SHIFT)
+#define MCG_BRD_C2_FCFTRIM(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT))
+
+/*! @brief Set the FCFTRIM field to a new value. */
+#define MCG_WR_C2_FCFTRIM(base, value) (MCG_RMW_C2(base, MCG_C2_FCFTRIM_MASK, MCG_C2_FCFTRIM(value)))
+#define MCG_BWR_C2_FCFTRIM(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field LOCRE0[7] (RW)
+ *
+ * Determines whether an interrupt or a reset request is made following a loss
+ * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
+ * set.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a loss of OSC0 external reference
+ *     clock.
+ * - 0b1 - Generate a reset request on a loss of OSC0 external reference clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_LOCRE0 field. */
+#define MCG_RD_C2_LOCRE0(base) ((MCG_C2_REG(base) & MCG_C2_LOCRE0_MASK) >> MCG_C2_LOCRE0_SHIFT)
+#define MCG_BRD_C2_LOCRE0(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT))
+
+/*! @brief Set the LOCRE0 field to a new value. */
+#define MCG_WR_C2_LOCRE0(base, value) (MCG_RMW_C2(base, MCG_C2_LOCRE0_MASK, MCG_C2_LOCRE0(value)))
+#define MCG_BWR_C2_LOCRE0(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C3 - MCG Control 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C3 - MCG Control 3 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C3 register
+ */
+/*@{*/
+#define MCG_RD_C3(base)          (MCG_C3_REG(base))
+#define MCG_WR_C3(base, value)   (MCG_C3_REG(base) = (value))
+#define MCG_RMW_C3(base, mask, value) (MCG_WR_C3(base, (MCG_RD_C3(base) & ~(mask)) | (value)))
+#define MCG_SET_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) |  (value)))
+#define MCG_CLR_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) & ~(value)))
+#define MCG_TOG_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C4 - MCG Control 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C4 - MCG Control 4 Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Reset values for DRST and DMX32 bits are 0.
+ */
+/*!
+ * @name Constants and macros for entire MCG_C4 register
+ */
+/*@{*/
+#define MCG_RD_C4(base)          (MCG_C4_REG(base))
+#define MCG_WR_C4(base, value)   (MCG_C4_REG(base) = (value))
+#define MCG_RMW_C4(base, mask, value) (MCG_WR_C4(base, (MCG_RD_C4(base) & ~(mask)) | (value)))
+#define MCG_SET_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) |  (value)))
+#define MCG_CLR_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) & ~(value)))
+#define MCG_TOG_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C4 bitfields
+ */
+
+/*!
+ * @name Register MCG_C4, field SCFTRIM[0] (RW)
+ *
+ * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
+ * location . controls the smallest adjustment of the slow internal reference
+ * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
+ * decreases the period by the smallest amount possible. If an SCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_SCFTRIM field. */
+#define MCG_RD_C4_SCFTRIM(base) ((MCG_C4_REG(base) & MCG_C4_SCFTRIM_MASK) >> MCG_C4_SCFTRIM_SHIFT)
+#define MCG_BRD_C4_SCFTRIM(base) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT))
+
+/*! @brief Set the SCFTRIM field to a new value. */
+#define MCG_WR_C4_SCFTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_SCFTRIM_MASK, MCG_C4_SCFTRIM(value)))
+#define MCG_BWR_C4_SCFTRIM(base, value) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field FCTRIM[4:1] (RW)
+ *
+ * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
+ * location. controls the fast internal reference clock frequency by controlling
+ * the fast internal reference clock period. The FCTRIM bits are binary weighted,
+ * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
+ * increases the period, and decreasing the value decreases the period. If an
+ * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
+ * responsibility to copy that value from the nonvolatile memory location to this register.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_FCTRIM field. */
+#define MCG_RD_C4_FCTRIM(base) ((MCG_C4_REG(base) & MCG_C4_FCTRIM_MASK) >> MCG_C4_FCTRIM_SHIFT)
+#define MCG_BRD_C4_FCTRIM(base) (MCG_RD_C4_FCTRIM(base))
+
+/*! @brief Set the FCTRIM field to a new value. */
+#define MCG_WR_C4_FCTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_FCTRIM_MASK, MCG_C4_FCTRIM(value)))
+#define MCG_BWR_C4_FCTRIM(base, value) (MCG_WR_C4_FCTRIM(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
+ *
+ * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
+ * LP bit is set, writes to the DRS bits are ignored. The DRST read field
+ * indicates the current frequency range for DCOOUT. The DRST field does not update
+ * immediately after a write to the DRS field due to internal synchronization between
+ * clock domains. See the DCO Frequency Range table for more details.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Low range (reset default).
+ * - 0b01 - Encoding 1 - Mid range.
+ * - 0b10 - Encoding 2 - Mid-high range.
+ * - 0b11 - Encoding 3 - High range.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_DRST_DRS field. */
+#define MCG_RD_C4_DRST_DRS(base) ((MCG_C4_REG(base) & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
+#define MCG_BRD_C4_DRST_DRS(base) (MCG_RD_C4_DRST_DRS(base))
+
+/*! @brief Set the DRST_DRS field to a new value. */
+#define MCG_WR_C4_DRST_DRS(base, value) (MCG_RMW_C4(base, MCG_C4_DRST_DRS_MASK, MCG_C4_DRST_DRS(value)))
+#define MCG_BWR_C4_DRST_DRS(base, value) (MCG_WR_C4_DRST_DRS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field DMX32[7] (RW)
+ *
+ * The DMX32 bit controls whether the DCO frequency range is narrowed to its
+ * maximum frequency with a 32.768 kHz reference. The following table identifies
+ * settings for the DCO frequency range. The system clocks derived from this source
+ * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
+ * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
+ * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
+ * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
+ * 80-100 MHz 1 32.768 kHz 2929 96 MHz
+ *
+ * Values:
+ * - 0b0 - DCO has a default range of 25%.
+ * - 0b1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_DMX32 field. */
+#define MCG_RD_C4_DMX32(base) ((MCG_C4_REG(base) & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
+#define MCG_BRD_C4_DMX32(base) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT))
+
+/*! @brief Set the DMX32 field to a new value. */
+#define MCG_WR_C4_DMX32(base, value) (MCG_RMW_C4(base, MCG_C4_DMX32_MASK, MCG_C4_DMX32(value)))
+#define MCG_BWR_C4_DMX32(base, value) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C5 - MCG Control 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C5 - MCG Control 5 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C5 register
+ */
+/*@{*/
+#define MCG_RD_C5(base)          (MCG_C5_REG(base))
+#define MCG_WR_C5(base, value)   (MCG_C5_REG(base) = (value))
+#define MCG_RMW_C5(base, mask, value) (MCG_WR_C5(base, (MCG_RD_C5(base) & ~(mask)) | (value)))
+#define MCG_SET_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) |  (value)))
+#define MCG_CLR_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) & ~(value)))
+#define MCG_TOG_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C5 bitfields
+ */
+
+/*!
+ * @name Register MCG_C5, field PRDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the PLL.
+ * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
+ * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
+ * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
+ * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
+ * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
+ * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
+ * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
+ * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
+ * Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PRDIV0 field. */
+#define MCG_RD_C5_PRDIV0(base) ((MCG_C5_REG(base) & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
+#define MCG_BRD_C5_PRDIV0(base) (MCG_RD_C5_PRDIV0(base))
+
+/*! @brief Set the PRDIV0 field to a new value. */
+#define MCG_WR_C5_PRDIV0(base, value) (MCG_RMW_C5(base, MCG_C5_PRDIV0_MASK, MCG_C5_PRDIV0(value)))
+#define MCG_BWR_C5_PRDIV0(base, value) (MCG_WR_C5_PRDIV0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C5, field PLLSTEN0[5] (RW)
+ *
+ * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
+ * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
+ * has no affect and does not enable the PLL Clock to run if it is written to 1.
+ *
+ * Values:
+ * - 0b0 - MCGPLLCLK is disabled in any of the Stop modes.
+ * - 0b1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */
+#define MCG_RD_C5_PLLSTEN0(base) ((MCG_C5_REG(base) & MCG_C5_PLLSTEN0_MASK) >> MCG_C5_PLLSTEN0_SHIFT)
+#define MCG_BRD_C5_PLLSTEN0(base) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLSTEN0_SHIFT))
+
+/*! @brief Set the PLLSTEN0 field to a new value. */
+#define MCG_WR_C5_PLLSTEN0(base, value) (MCG_RMW_C5(base, MCG_C5_PLLSTEN0_MASK, MCG_C5_PLLSTEN0(value)))
+#define MCG_BWR_C5_PLLSTEN0(base, value) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLSTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C5, field PLLCLKEN0[6] (RW)
+ *
+ * Enables the PLL independent of PLLS and enables the PLL clock for use as
+ * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
+ * PLL reference clock in the range of 2 - 4 MHz range prior to setting the
+ * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
+ * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
+ * and the external oscillator is being used as the reference clock, the OSCINIT 0
+ * bit should be checked to make sure it is set.
+ *
+ * Values:
+ * - 0b0 - MCGPLLCLK is inactive.
+ * - 0b1 - MCGPLLCLK is active.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */
+#define MCG_RD_C5_PLLCLKEN0(base) ((MCG_C5_REG(base) & MCG_C5_PLLCLKEN0_MASK) >> MCG_C5_PLLCLKEN0_SHIFT)
+#define MCG_BRD_C5_PLLCLKEN0(base) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLCLKEN0_SHIFT))
+
+/*! @brief Set the PLLCLKEN0 field to a new value. */
+#define MCG_WR_C5_PLLCLKEN0(base, value) (MCG_RMW_C5(base, MCG_C5_PLLCLKEN0_MASK, MCG_C5_PLLCLKEN0(value)))
+#define MCG_BWR_C5_PLLCLKEN0(base, value) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLCLKEN0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C6 - MCG Control 6 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C6 - MCG Control 6 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C6 register
+ */
+/*@{*/
+#define MCG_RD_C6(base)          (MCG_C6_REG(base))
+#define MCG_WR_C6(base, value)   (MCG_C6_REG(base) = (value))
+#define MCG_RMW_C6(base, mask, value) (MCG_WR_C6(base, (MCG_RD_C6(base) & ~(mask)) | (value)))
+#define MCG_SET_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) |  (value)))
+#define MCG_CLR_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) & ~(value)))
+#define MCG_TOG_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C6 bitfields
+ */
+
+/*!
+ * @name Register MCG_C6, field VDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
+ * establish the multiplication factor (M) applied to the reference clock frequency.
+ * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
+ * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
+ * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
+ * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
+ * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
+ * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
+ * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_VDIV0 field. */
+#define MCG_RD_C6_VDIV0(base) ((MCG_C6_REG(base) & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
+#define MCG_BRD_C6_VDIV0(base) (MCG_RD_C6_VDIV0(base))
+
+/*! @brief Set the VDIV0 field to a new value. */
+#define MCG_WR_C6_VDIV0(base, value) (MCG_RMW_C6(base, MCG_C6_VDIV0_MASK, MCG_C6_VDIV0(value)))
+#define MCG_BWR_C6_VDIV0(base, value) (MCG_WR_C6_VDIV0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field CME0[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the OSC0 external reference
+ * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
+ * generated following a loss of OSC0 indication. The CME0 bit must only be set
+ * to a logic 1 when the MCG is in an operational mode that uses the external
+ * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
+ * the value of the RANGE0 bits in the C2 register should not be changed. CME0
+ * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur while in Stop mode. CME0 should also be set to a
+ * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
+ *
+ * Values:
+ * - 0b0 - External clock monitor is disabled for OSC0.
+ * - 0b1 - External clock monitor is enabled for OSC0.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_CME0 field. */
+#define MCG_RD_C6_CME0(base) ((MCG_C6_REG(base) & MCG_C6_CME0_MASK) >> MCG_C6_CME0_SHIFT)
+#define MCG_BRD_C6_CME0(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_CME0_SHIFT))
+
+/*! @brief Set the CME0 field to a new value. */
+#define MCG_WR_C6_CME0(base, value) (MCG_RMW_C6(base, MCG_C6_CME0_MASK, MCG_C6_CME0(value)))
+#define MCG_BWR_C6_CME0(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_CME0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field PLLS[6] (RW)
+ *
+ * Controls whether the PLL or FLL output is selected as the MCG source when
+ * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
+ * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
+ *
+ * Values:
+ * - 0b0 - FLL is selected.
+ * - 0b1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
+ *     to generate a PLL reference clock in the range of 2-4 MHz prior to
+ *     setting the PLLS bit).
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_PLLS field. */
+#define MCG_RD_C6_PLLS(base) ((MCG_C6_REG(base) & MCG_C6_PLLS_MASK) >> MCG_C6_PLLS_SHIFT)
+#define MCG_BRD_C6_PLLS(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_PLLS_SHIFT))
+
+/*! @brief Set the PLLS field to a new value. */
+#define MCG_WR_C6_PLLS(base, value) (MCG_RMW_C6(base, MCG_C6_PLLS_MASK, MCG_C6_PLLS(value)))
+#define MCG_BWR_C6_PLLS(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_PLLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field LOLIE0[7] (RW)
+ *
+ * Determines if an interrupt request is made following a loss of lock
+ * indication. This bit only has an effect when LOLS 0 is set.
+ *
+ * Values:
+ * - 0b0 - No interrupt request is generated on loss of lock.
+ * - 0b1 - Generate an interrupt request on loss of lock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_LOLIE0 field. */
+#define MCG_RD_C6_LOLIE0(base) ((MCG_C6_REG(base) & MCG_C6_LOLIE0_MASK) >> MCG_C6_LOLIE0_SHIFT)
+#define MCG_BRD_C6_LOLIE0(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_LOLIE0_SHIFT))
+
+/*! @brief Set the LOLIE0 field to a new value. */
+#define MCG_WR_C6_LOLIE0(base, value) (MCG_RMW_C6(base, MCG_C6_LOLIE0_MASK, MCG_C6_LOLIE0(value)))
+#define MCG_BWR_C6_LOLIE0(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_LOLIE0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_S - MCG Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_S - MCG Status Register (RW)
+ *
+ * Reset value: 0x10U
+ */
+/*!
+ * @name Constants and macros for entire MCG_S register
+ */
+/*@{*/
+#define MCG_RD_S(base)           (MCG_S_REG(base))
+#define MCG_WR_S(base, value)    (MCG_S_REG(base) = (value))
+#define MCG_RMW_S(base, mask, value) (MCG_WR_S(base, (MCG_RD_S(base) & ~(mask)) | (value)))
+#define MCG_SET_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) |  (value)))
+#define MCG_CLR_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) & ~(value)))
+#define MCG_TOG_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_S bitfields
+ */
+
+/*!
+ * @name Register MCG_S, field IRCST[0] (RO)
+ *
+ * The IRCST bit indicates the current source for the internal reference clock
+ * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
+ * to the IRCS bit due to internal synchronization between clock domains. The
+ * IRCST bit will only be updated if the internal reference clock is enabled,
+ * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
+ * bit .
+ *
+ * Values:
+ * - 0b0 - Source of internal reference clock is the slow clock (32 kHz IRC).
+ * - 0b1 - Source of internal reference clock is the fast clock (4 MHz IRC).
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_IRCST field. */
+#define MCG_RD_S_IRCST(base) ((MCG_S_REG(base) & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT)
+#define MCG_BRD_S_IRCST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_IRCST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field OSCINIT0[1] (RO)
+ *
+ * This bit, which resets to 0, is set to 1 after the initialization cycles of
+ * the crystal oscillator clock have completed. After being set, the bit is
+ * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
+ * description for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_OSCINIT0 field. */
+#define MCG_RD_S_OSCINIT0(base) ((MCG_S_REG(base) & MCG_S_OSCINIT0_MASK) >> MCG_S_OSCINIT0_SHIFT)
+#define MCG_BRD_S_OSCINIT0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_OSCINIT0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field CLKST[3:2] (RO)
+ *
+ * These bits indicate the current clock mode. The CLKST bits do not update
+ * immediately after a write to the CLKS bits due to internal synchronization between
+ * clock domains.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Output of the FLL is selected (reset default).
+ * - 0b01 - Encoding 1 - Internal reference clock is selected.
+ * - 0b10 - Encoding 2 - External reference clock is selected.
+ * - 0b11 - Encoding 3 - Output of the PLL is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_CLKST field. */
+#define MCG_RD_S_CLKST(base) ((MCG_S_REG(base) & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
+#define MCG_BRD_S_CLKST(base) (MCG_RD_S_CLKST(base))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field IREFST[4] (RO)
+ *
+ * This bit indicates the current source for the FLL reference clock. The IREFST
+ * bit does not update immediately after a write to the IREFS bit due to
+ * internal synchronization between clock domains.
+ *
+ * Values:
+ * - 0b0 - Source of FLL reference clock is the external reference clock.
+ * - 0b1 - Source of FLL reference clock is the internal reference clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_IREFST field. */
+#define MCG_RD_S_IREFST(base) ((MCG_S_REG(base) & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
+#define MCG_BRD_S_IREFST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_IREFST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field PLLST[5] (RO)
+ *
+ * This bit indicates the clock source selected by PLLS . The PLLST bit does not
+ * update immediately after a write to the PLLS bit due to internal
+ * synchronization between clock domains.
+ *
+ * Values:
+ * - 0b0 - Source of PLLS clock is FLL clock.
+ * - 0b1 - Source of PLLS clock is PLL output clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_PLLST field. */
+#define MCG_RD_S_PLLST(base) ((MCG_S_REG(base) & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT)
+#define MCG_BRD_S_PLLST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_PLLST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field LOCK0[6] (RO)
+ *
+ * This bit indicates whether the PLL has acquired lock. Lock detection is only
+ * enabled when the PLL is enabled (either through clock mode selection or
+ * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
+ * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
+ * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
+ * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
+ * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
+ * reference clock will also cause the LOCK0 bit to clear until the PLL has
+ * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
+ * the lock status bit to clear and stay cleared until the Stop mode is exited
+ * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
+ * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
+ * again.
+ *
+ * Values:
+ * - 0b0 - PLL is currently unlocked.
+ * - 0b1 - PLL is currently locked.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_LOCK0 field. */
+#define MCG_RD_S_LOCK0(base) ((MCG_S_REG(base) & MCG_S_LOCK0_MASK) >> MCG_S_LOCK0_SHIFT)
+#define MCG_BRD_S_LOCK0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOCK0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field LOLS0[7] (W1C)
+ *
+ * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
+ * if after acquiring lock, the PLL output frequency has fallen outside the lock
+ * exit frequency tolerance, D unl . LOLIE determines whether an interrupt
+ * request is made when LOLS is set. LOLRE determines whether a reset request is made
+ * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
+ * when set. Writing a logic 0 to this bit has no effect.
+ *
+ * Values:
+ * - 0b0 - PLL has not lost lock since LOLS 0 was last cleared.
+ * - 0b1 - PLL has lost lock since LOLS 0 was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_LOLS0 field. */
+#define MCG_RD_S_LOLS0(base) ((MCG_S_REG(base) & MCG_S_LOLS0_MASK) >> MCG_S_LOLS0_SHIFT)
+#define MCG_BRD_S_LOLS0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOLS0_SHIFT))
+
+/*! @brief Set the LOLS0 field to a new value. */
+#define MCG_WR_S_LOLS0(base, value) (MCG_RMW_S(base, MCG_S_LOLS0_MASK, MCG_S_LOLS0(value)))
+#define MCG_BWR_S_LOLS0(base, value) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOLS0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_SC - MCG Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_SC - MCG Status and Control Register (RW)
+ *
+ * Reset value: 0x02U
+ */
+/*!
+ * @name Constants and macros for entire MCG_SC register
+ */
+/*@{*/
+#define MCG_RD_SC(base)          (MCG_SC_REG(base))
+#define MCG_WR_SC(base, value)   (MCG_SC_REG(base) = (value))
+#define MCG_RMW_SC(base, mask, value) (MCG_WR_SC(base, (MCG_RD_SC(base) & ~(mask)) | (value)))
+#define MCG_SET_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) |  (value)))
+#define MCG_CLR_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) & ~(value)))
+#define MCG_TOG_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_SC bitfields
+ */
+
+/*!
+ * @name Register MCG_SC, field LOCS0[0] (W1C)
+ *
+ * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
+ * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
+ * logic 1 to it when set.
+ *
+ * Values:
+ * - 0b0 - Loss of OSC0 has not occurred.
+ * - 0b1 - Loss of OSC0 has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_LOCS0 field. */
+#define MCG_RD_SC_LOCS0(base) ((MCG_SC_REG(base) & MCG_SC_LOCS0_MASK) >> MCG_SC_LOCS0_SHIFT)
+#define MCG_BRD_SC_LOCS0(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT))
+
+/*! @brief Set the LOCS0 field to a new value. */
+#define MCG_WR_SC_LOCS0(base, value) (MCG_RMW_SC(base, MCG_SC_LOCS0_MASK, MCG_SC_LOCS0(value)))
+#define MCG_BWR_SC_LOCS0(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field FCRDIV[3:1] (RW)
+ *
+ * Selects the amount to divide down the fast internal reference clock. The
+ * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
+ * divider when the Fast IRC is enabled is not supported).
+ *
+ * Values:
+ * - 0b000 - Divide Factor is 1
+ * - 0b001 - Divide Factor is 2.
+ * - 0b010 - Divide Factor is 4.
+ * - 0b011 - Divide Factor is 8.
+ * - 0b100 - Divide Factor is 16
+ * - 0b101 - Divide Factor is 32
+ * - 0b110 - Divide Factor is 64
+ * - 0b111 - Divide Factor is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FCRDIV field. */
+#define MCG_RD_SC_FCRDIV(base) ((MCG_SC_REG(base) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
+#define MCG_BRD_SC_FCRDIV(base) (MCG_RD_SC_FCRDIV(base))
+
+/*! @brief Set the FCRDIV field to a new value. */
+#define MCG_WR_SC_FCRDIV(base, value) (MCG_RMW_SC(base, (MCG_SC_FCRDIV_MASK | MCG_SC_LOCS0_MASK), MCG_SC_FCRDIV(value)))
+#define MCG_BWR_SC_FCRDIV(base, value) (MCG_WR_SC_FCRDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field FLTPRSRV[4] (RW)
+ *
+ * This bit will prevent the FLL filter values from resetting allowing the FLL
+ * output frequency to remain the same during clock mode changes where the FLL/DCO
+ * output is still valid. (Note: This requires that the FLL reference frequency
+ * to remain the same as what it was prior to the new clock mode switch.
+ * Otherwise FLL filter and frequency values will change.)
+ *
+ * Values:
+ * - 0b0 - FLL filter and FLL frequency will reset on changes to currect clock
+ *     mode.
+ * - 0b1 - Fll filter and FLL frequency retain their previous values during new
+ *     clock mode change.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FLTPRSRV field. */
+#define MCG_RD_SC_FLTPRSRV(base) ((MCG_SC_REG(base) & MCG_SC_FLTPRSRV_MASK) >> MCG_SC_FLTPRSRV_SHIFT)
+#define MCG_BRD_SC_FLTPRSRV(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT))
+
+/*! @brief Set the FLTPRSRV field to a new value. */
+#define MCG_WR_SC_FLTPRSRV(base, value) (MCG_RMW_SC(base, (MCG_SC_FLTPRSRV_MASK | MCG_SC_LOCS0_MASK), MCG_SC_FLTPRSRV(value)))
+#define MCG_BWR_SC_FLTPRSRV(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATMF[5] (RW)
+ *
+ * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
+ * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
+ * registers is detected or the MCG enters into any Stop mode. A write to ATMF
+ * clears the flag.
+ *
+ * Values:
+ * - 0b0 - Automatic Trim Machine completed normally.
+ * - 0b1 - Automatic Trim Machine failed.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATMF field. */
+#define MCG_RD_SC_ATMF(base) ((MCG_SC_REG(base) & MCG_SC_ATMF_MASK) >> MCG_SC_ATMF_SHIFT)
+#define MCG_BRD_SC_ATMF(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT))
+
+/*! @brief Set the ATMF field to a new value. */
+#define MCG_WR_SC_ATMF(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMF(value)))
+#define MCG_BWR_SC_ATMF(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATMS[6] (RW)
+ *
+ * Selects the IRCS clock for Auto Trim Test.
+ *
+ * Values:
+ * - 0b0 - 32 kHz Internal Reference Clock selected.
+ * - 0b1 - 4 MHz Internal Reference Clock selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATMS field. */
+#define MCG_RD_SC_ATMS(base) ((MCG_SC_REG(base) & MCG_SC_ATMS_MASK) >> MCG_SC_ATMS_SHIFT)
+#define MCG_BRD_SC_ATMS(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT))
+
+/*! @brief Set the ATMS field to a new value. */
+#define MCG_WR_SC_ATMS(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMS(value)))
+#define MCG_BWR_SC_ATMS(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATME[7] (RW)
+ *
+ * Enables the Auto Trim Machine to start automatically trimming the selected
+ * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
+ * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
+ * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
+ * operation and clears this bit.
+ *
+ * Values:
+ * - 0b0 - Auto Trim Machine disabled.
+ * - 0b1 - Auto Trim Machine enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATME field. */
+#define MCG_RD_SC_ATME(base) ((MCG_SC_REG(base) & MCG_SC_ATME_MASK) >> MCG_SC_ATME_SHIFT)
+#define MCG_BRD_SC_ATME(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT))
+
+/*! @brief Set the ATME field to a new value. */
+#define MCG_WR_SC_ATME(base, value) (MCG_RMW_SC(base, (MCG_SC_ATME_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATME(value)))
+#define MCG_BWR_SC_ATME(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_ATCVH register
+ */
+/*@{*/
+#define MCG_RD_ATCVH(base)       (MCG_ATCVH_REG(base))
+#define MCG_WR_ATCVH(base, value) (MCG_ATCVH_REG(base) = (value))
+#define MCG_RMW_ATCVH(base, mask, value) (MCG_WR_ATCVH(base, (MCG_RD_ATCVH(base) & ~(mask)) | (value)))
+#define MCG_SET_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) |  (value)))
+#define MCG_CLR_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) & ~(value)))
+#define MCG_TOG_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_ATCVL register
+ */
+/*@{*/
+#define MCG_RD_ATCVL(base)       (MCG_ATCVL_REG(base))
+#define MCG_WR_ATCVL(base, value) (MCG_ATCVL_REG(base) = (value))
+#define MCG_RMW_ATCVL(base, mask, value) (MCG_WR_ATCVL(base, (MCG_RD_ATCVL(base) & ~(mask)) | (value)))
+#define MCG_SET_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) |  (value)))
+#define MCG_CLR_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) & ~(value)))
+#define MCG_TOG_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C7 - MCG Control 7 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C7 - MCG Control 7 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C7 register
+ */
+/*@{*/
+#define MCG_RD_C7(base)          (MCG_C7_REG(base))
+#define MCG_WR_C7(base, value)   (MCG_C7_REG(base) = (value))
+#define MCG_RMW_C7(base, mask, value) (MCG_WR_C7(base, (MCG_RD_C7(base) & ~(mask)) | (value)))
+#define MCG_SET_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) |  (value)))
+#define MCG_CLR_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) & ~(value)))
+#define MCG_TOG_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C7 bitfields
+ */
+
+/*!
+ * @name Register MCG_C7, field OSCSEL[1:0] (RW)
+ *
+ * Selects the MCG FLL external reference clock
+ *
+ * Values:
+ * - 0b00 - Selects Oscillator (OSCCLK0).
+ * - 0b01 - Selects 32 kHz RTC Oscillator.
+ * - 0b10 - Selects Oscillator (OSCCLK1).
+ * - 0b11 - RESERVED
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C7_OSCSEL field. */
+#define MCG_RD_C7_OSCSEL(base) ((MCG_C7_REG(base) & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
+#define MCG_BRD_C7_OSCSEL(base) (MCG_RD_C7_OSCSEL(base))
+
+/*! @brief Set the OSCSEL field to a new value. */
+#define MCG_WR_C7_OSCSEL(base, value) (MCG_RMW_C7(base, MCG_C7_OSCSEL_MASK, MCG_C7_OSCSEL(value)))
+#define MCG_BWR_C7_OSCSEL(base, value) (MCG_WR_C7_OSCSEL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C8 - MCG Control 8 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C8 - MCG Control 8 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C8 register
+ */
+/*@{*/
+#define MCG_RD_C8(base)          (MCG_C8_REG(base))
+#define MCG_WR_C8(base, value)   (MCG_C8_REG(base) = (value))
+#define MCG_RMW_C8(base, mask, value) (MCG_WR_C8(base, (MCG_RD_C8(base) & ~(mask)) | (value)))
+#define MCG_SET_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) |  (value)))
+#define MCG_CLR_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) & ~(value)))
+#define MCG_TOG_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C8 bitfields
+ */
+
+/*!
+ * @name Register MCG_C8, field LOCS1[0] (W1C)
+ *
+ * This bit indicates when a loss of clock has occurred. This bit is cleared by
+ * writing a logic 1 to it when set.
+ *
+ * Values:
+ * - 0b0 - Loss of RTC has not occur.
+ * - 0b1 - Loss of RTC has occur
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOCS1 field. */
+#define MCG_RD_C8_LOCS1(base) ((MCG_C8_REG(base) & MCG_C8_LOCS1_MASK) >> MCG_C8_LOCS1_SHIFT)
+#define MCG_BRD_C8_LOCS1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT))
+
+/*! @brief Set the LOCS1 field to a new value. */
+#define MCG_WR_C8_LOCS1(base, value) (MCG_RMW_C8(base, MCG_C8_LOCS1_MASK, MCG_C8_LOCS1(value)))
+#define MCG_BWR_C8_LOCS1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field CME1[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the output of the RTC
+ * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
+ * reset request is generated following a loss of RTC clock indication. The CME1
+ * bit should be set to a logic 1 when the MCG is in an operational mode that uses
+ * the RTC as its external reference clock or if the RTC is operational. CME1 bit
+ * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
+ * before entering VLPR or VLPW power modes.
+ *
+ * Values:
+ * - 0b0 - External clock monitor is disabled for RTC clock.
+ * - 0b1 - External clock monitor is enabled for RTC clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_CME1 field. */
+#define MCG_RD_C8_CME1(base) ((MCG_C8_REG(base) & MCG_C8_CME1_MASK) >> MCG_C8_CME1_SHIFT)
+#define MCG_BRD_C8_CME1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT))
+
+/*! @brief Set the CME1 field to a new value. */
+#define MCG_WR_C8_CME1(base, value) (MCG_RMW_C8(base, (MCG_C8_CME1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_CME1(value)))
+#define MCG_BWR_C8_CME1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field LOLRE[6] (RW)
+ *
+ * Determines if an interrupt or a reset request is made following a PLL loss of
+ * lock.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a PLL loss of lock indication. The
+ *     PLL loss of lock interrupt enable bit must also be set to generate the
+ *     interrupt request.
+ * - 0b1 - Generate a reset request on a PLL loss of lock indication.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOLRE field. */
+#define MCG_RD_C8_LOLRE(base) ((MCG_C8_REG(base) & MCG_C8_LOLRE_MASK) >> MCG_C8_LOLRE_SHIFT)
+#define MCG_BRD_C8_LOLRE(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOLRE_SHIFT))
+
+/*! @brief Set the LOLRE field to a new value. */
+#define MCG_WR_C8_LOLRE(base, value) (MCG_RMW_C8(base, (MCG_C8_LOLRE_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOLRE(value)))
+#define MCG_BWR_C8_LOLRE(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOLRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field LOCRE1[7] (RW)
+ *
+ * Determines if a interrupt or a reset request is made following a loss of RTC
+ * external reference clock. The LOCRE1 only has an affect when CME1 is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a loss of RTC external reference
+ *     clock.
+ * - 0b1 - Generate a reset request on a loss of RTC external reference clock
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOCRE1 field. */
+#define MCG_RD_C8_LOCRE1(base) ((MCG_C8_REG(base) & MCG_C8_LOCRE1_MASK) >> MCG_C8_LOCRE1_SHIFT)
+#define MCG_BRD_C8_LOCRE1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT))
+
+/*! @brief Set the LOCRE1 field to a new value. */
+#define MCG_WR_C8_LOCRE1(base, value) (MCG_RMW_C8(base, (MCG_C8_LOCRE1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOCRE1(value)))
+#define MCG_BWR_C8_LOCRE1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 MCM
+ *
+ * Core Platform Miscellaneous Control Module
+ *
+ * Registers defined in this header file:
+ * - MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ * - MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ * - MCM_CR - Control Register
+ * - MCM_ISCR - Interrupt Status Register
+ * - MCM_ETBCC - ETB Counter Control register
+ * - MCM_ETBRL - ETB Reload register
+ * - MCM_ETBCNT - ETB Counter Value register
+ * - MCM_PID - Process ID register
+ */
+
+#define MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
+#define MCM_IDX (0U) /*!< Instance number for MCM. */
+
+/*******************************************************************************
+ * MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
+ *
+ * Reset value: 0x001FU
+ *
+ * PLASC is a 16-bit read-only register identifying the presence/absence of bus
+ * slave connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLASC register
+ */
+/*@{*/
+#define MCM_RD_PLASC(base)       (MCM_PLASC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLASC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLASC, field ASC[7:0] (RO)
+ *
+ * Values:
+ * - 0b00000000 - A bus slave connection to AXBS input port n is absent
+ * - 0b00000001 - A bus slave connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLASC_ASC field. */
+#define MCM_RD_PLASC_ASC(base) ((MCM_PLASC_REG(base) & MCM_PLASC_ASC_MASK) >> MCM_PLASC_ASC_SHIFT)
+#define MCM_BRD_PLASC_ASC(base) (MCM_RD_PLASC_ASC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
+ *
+ * Reset value: 0x0037U
+ *
+ * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
+ * master connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLAMC register
+ */
+/*@{*/
+#define MCM_RD_PLAMC(base)       (MCM_PLAMC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLAMC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLAMC, field AMC[7:0] (RO)
+ *
+ * Values:
+ * - 0b00000000 - A bus master connection to AXBS input port n is absent
+ * - 0b00000001 - A bus master connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLAMC_AMC field. */
+#define MCM_RD_PLAMC_AMC(base) ((MCM_PLAMC_REG(base) & MCM_PLAMC_AMC_MASK) >> MCM_PLAMC_AMC_SHIFT)
+#define MCM_BRD_PLAMC_AMC(base) (MCM_RD_PLAMC_AMC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_CR - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CR defines the arbitration and protection schemes for the two system RAM
+ * arrays.
+ */
+/*!
+ * @name Constants and macros for entire MCM_CR register
+ */
+/*@{*/
+#define MCM_RD_CR(base)          (MCM_CR_REG(base))
+#define MCM_WR_CR(base, value)   (MCM_CR_REG(base) = (value))
+#define MCM_RMW_CR(base, mask, value) (MCM_WR_CR(base, (MCM_RD_CR(base) & ~(mask)) | (value)))
+#define MCM_SET_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) |  (value)))
+#define MCM_CLR_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) & ~(value)))
+#define MCM_TOG_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_CR bitfields
+ */
+
+/*!
+ * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_U array.
+ *
+ * Values:
+ * - 0b00 - Round robin
+ * - 0b01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 0b10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 0b11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMUAP field. */
+#define MCM_RD_CR_SRAMUAP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMUAP_MASK) >> MCM_CR_SRAMUAP_SHIFT)
+#define MCM_BRD_CR_SRAMUAP(base) (MCM_RD_CR_SRAMUAP(base))
+
+/*! @brief Set the SRAMUAP field to a new value. */
+#define MCM_WR_CR_SRAMUAP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMUAP_MASK, MCM_CR_SRAMUAP(value)))
+#define MCM_BWR_CR_SRAMUAP(base, value) (MCM_WR_CR_SRAMUAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMUWP[26] (RW)
+ *
+ * When this bit is set, writes to SRAM_U array generates a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMUWP field. */
+#define MCM_RD_CR_SRAMUWP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMUWP_MASK) >> MCM_CR_SRAMUWP_SHIFT)
+#define MCM_BRD_CR_SRAMUWP(base) (MCM_RD_CR_SRAMUWP(base))
+
+/*! @brief Set the SRAMUWP field to a new value. */
+#define MCM_WR_CR_SRAMUWP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMUWP_MASK, MCM_CR_SRAMUWP(value)))
+#define MCM_BWR_CR_SRAMUWP(base, value) (MCM_WR_CR_SRAMUWP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_L array.
+ *
+ * Values:
+ * - 0b00 - Round robin
+ * - 0b01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 0b10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 0b11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMLAP field. */
+#define MCM_RD_CR_SRAMLAP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMLAP_MASK) >> MCM_CR_SRAMLAP_SHIFT)
+#define MCM_BRD_CR_SRAMLAP(base) (MCM_RD_CR_SRAMLAP(base))
+
+/*! @brief Set the SRAMLAP field to a new value. */
+#define MCM_WR_CR_SRAMLAP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMLAP_MASK, MCM_CR_SRAMLAP(value)))
+#define MCM_BWR_CR_SRAMLAP(base, value) (MCM_WR_CR_SRAMLAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMLWP[30] (RW)
+ *
+ * When this bit is set, writes to SRAM_L array generates a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMLWP field. */
+#define MCM_RD_CR_SRAMLWP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMLWP_MASK) >> MCM_CR_SRAMLWP_SHIFT)
+#define MCM_BRD_CR_SRAMLWP(base) (MCM_RD_CR_SRAMLWP(base))
+
+/*! @brief Set the SRAMLWP field to a new value. */
+#define MCM_WR_CR_SRAMLWP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMLWP_MASK, MCM_CR_SRAMLWP(value)))
+#define MCM_BWR_CR_SRAMLWP(base, value) (MCM_WR_CR_SRAMLWP(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ISCR - Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ISCR - Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ISCR register
+ */
+/*@{*/
+#define MCM_RD_ISCR(base)        (MCM_ISCR_REG(base))
+#define MCM_WR_ISCR(base, value) (MCM_ISCR_REG(base) = (value))
+#define MCM_RMW_ISCR(base, mask, value) (MCM_WR_ISCR(base, (MCM_RD_ISCR(base) & ~(mask)) | (value)))
+#define MCM_SET_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) |  (value)))
+#define MCM_CLR_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) & ~(value)))
+#define MCM_TOG_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ISCR bitfields
+ */
+
+/*!
+ * @name Register MCM_ISCR, field IRQ[1] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0b0 - No pending interrupt
+ * - 0b1 - Due to the ETB counter expiring, a normal interrupt is pending
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_IRQ field. */
+#define MCM_RD_ISCR_IRQ(base) ((MCM_ISCR_REG(base) & MCM_ISCR_IRQ_MASK) >> MCM_ISCR_IRQ_SHIFT)
+#define MCM_BRD_ISCR_IRQ(base) (MCM_RD_ISCR_IRQ(base))
+
+/*! @brief Set the IRQ field to a new value. */
+#define MCM_WR_ISCR_IRQ(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_IRQ(value)))
+#define MCM_BWR_ISCR_IRQ(base, value) (MCM_WR_ISCR_IRQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field NMI[2] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0b0 - No pending NMI
+ * - 0b1 - Due to the ETB counter expiring, an NMI is pending
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_NMI field. */
+#define MCM_RD_ISCR_NMI(base) ((MCM_ISCR_REG(base) & MCM_ISCR_NMI_MASK) >> MCM_ISCR_NMI_SHIFT)
+#define MCM_BRD_ISCR_NMI(base) (MCM_RD_ISCR_NMI(base))
+
+/*! @brief Set the NMI field to a new value. */
+#define MCM_WR_ISCR_NMI(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_NMI_MASK | MCM_ISCR_IRQ_MASK), MCM_ISCR_NMI(value)))
+#define MCM_BWR_ISCR_NMI(base, value) (MCM_WR_ISCR_NMI(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field DHREQ[3] (RO)
+ *
+ * Indicates that a debug halt request is initiated due to a ETB counter
+ * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
+ * counter is disabled or when the ETB counter is reloaded.
+ *
+ * Values:
+ * - 0b0 - No debug halt request
+ * - 0b1 - Debug halt request initiated
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_DHREQ field. */
+#define MCM_RD_ISCR_DHREQ(base) ((MCM_ISCR_REG(base) & MCM_ISCR_DHREQ_MASK) >> MCM_ISCR_DHREQ_SHIFT)
+#define MCM_BRD_ISCR_DHREQ(base) (MCM_RD_ISCR_DHREQ(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIOC[8] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
+ * illegal operation has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IOC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIOC field. */
+#define MCM_RD_ISCR_FIOC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIOC_MASK) >> MCM_ISCR_FIOC_SHIFT)
+#define MCM_BRD_ISCR_FIOC(base) (MCM_RD_ISCR_FIOC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FDZC[9] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
+ * divide by zero has been detected in the processor's FPU. Once set, this bit remains
+ * set until software clears the FPSCR[DZC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FDZC field. */
+#define MCM_RD_ISCR_FDZC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FDZC_MASK) >> MCM_ISCR_FDZC_SHIFT)
+#define MCM_BRD_ISCR_FDZC(base) (MCM_RD_ISCR_FDZC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FOFC[10] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
+ * overflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[OFC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FOFC field. */
+#define MCM_RD_ISCR_FOFC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FOFC_MASK) >> MCM_ISCR_FOFC_SHIFT)
+#define MCM_BRD_ISCR_FOFC(base) (MCM_RD_ISCR_FOFC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FUFC[11] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
+ * underflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[UFC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FUFC field. */
+#define MCM_RD_ISCR_FUFC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FUFC_MASK) >> MCM_ISCR_FUFC_SHIFT)
+#define MCM_BRD_ISCR_FUFC(base) (MCM_RD_ISCR_FUFC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIXC[12] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
+ * inexact number has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IXC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIXC field. */
+#define MCM_RD_ISCR_FIXC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIXC_MASK) >> MCM_ISCR_FIXC_SHIFT)
+#define MCM_BRD_ISCR_FIXC(base) (MCM_RD_ISCR_FIXC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIDC[15] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
+ * denormalized number has been detected in the processor's FPU. Once set, this
+ * bit remains set until software clears the FPSCR[IDC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIDC field. */
+#define MCM_RD_ISCR_FIDC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIDC_MASK) >> MCM_ISCR_FIDC_SHIFT)
+#define MCM_BRD_ISCR_FIDC(base) (MCM_RD_ISCR_FIDC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIOCE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIOCE field. */
+#define MCM_RD_ISCR_FIOCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIOCE_MASK) >> MCM_ISCR_FIOCE_SHIFT)
+#define MCM_BRD_ISCR_FIOCE(base) (MCM_RD_ISCR_FIOCE(base))
+
+/*! @brief Set the FIOCE field to a new value. */
+#define MCM_WR_ISCR_FIOCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIOCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIOCE(value)))
+#define MCM_BWR_ISCR_FIOCE(base, value) (MCM_WR_ISCR_FIOCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FDZCE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FDZCE field. */
+#define MCM_RD_ISCR_FDZCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FDZCE_MASK) >> MCM_ISCR_FDZCE_SHIFT)
+#define MCM_BRD_ISCR_FDZCE(base) (MCM_RD_ISCR_FDZCE(base))
+
+/*! @brief Set the FDZCE field to a new value. */
+#define MCM_WR_ISCR_FDZCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FDZCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FDZCE(value)))
+#define MCM_BWR_ISCR_FDZCE(base, value) (MCM_WR_ISCR_FDZCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FOFCE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FOFCE field. */
+#define MCM_RD_ISCR_FOFCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FOFCE_MASK) >> MCM_ISCR_FOFCE_SHIFT)
+#define MCM_BRD_ISCR_FOFCE(base) (MCM_RD_ISCR_FOFCE(base))
+
+/*! @brief Set the FOFCE field to a new value. */
+#define MCM_WR_ISCR_FOFCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FOFCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FOFCE(value)))
+#define MCM_BWR_ISCR_FOFCE(base, value) (MCM_WR_ISCR_FOFCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FUFCE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FUFCE field. */
+#define MCM_RD_ISCR_FUFCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FUFCE_MASK) >> MCM_ISCR_FUFCE_SHIFT)
+#define MCM_BRD_ISCR_FUFCE(base) (MCM_RD_ISCR_FUFCE(base))
+
+/*! @brief Set the FUFCE field to a new value. */
+#define MCM_WR_ISCR_FUFCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FUFCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FUFCE(value)))
+#define MCM_BWR_ISCR_FUFCE(base, value) (MCM_WR_ISCR_FUFCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIXCE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIXCE field. */
+#define MCM_RD_ISCR_FIXCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIXCE_MASK) >> MCM_ISCR_FIXCE_SHIFT)
+#define MCM_BRD_ISCR_FIXCE(base) (MCM_RD_ISCR_FIXCE(base))
+
+/*! @brief Set the FIXCE field to a new value. */
+#define MCM_WR_ISCR_FIXCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIXCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIXCE(value)))
+#define MCM_BWR_ISCR_FIXCE(base, value) (MCM_WR_ISCR_FIXCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIDCE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIDCE field. */
+#define MCM_RD_ISCR_FIDCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIDCE_MASK) >> MCM_ISCR_FIDCE_SHIFT)
+#define MCM_BRD_ISCR_FIDCE(base) (MCM_RD_ISCR_FIDCE(base))
+
+/*! @brief Set the FIDCE field to a new value. */
+#define MCM_WR_ISCR_FIDCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIDCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIDCE(value)))
+#define MCM_BWR_ISCR_FIDCE(base, value) (MCM_WR_ISCR_FIDCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBCC - ETB Counter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBCC - ETB Counter Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBCC register
+ */
+/*@{*/
+#define MCM_RD_ETBCC(base)       (MCM_ETBCC_REG(base))
+#define MCM_WR_ETBCC(base, value) (MCM_ETBCC_REG(base) = (value))
+#define MCM_RMW_ETBCC(base, mask, value) (MCM_WR_ETBCC(base, (MCM_RD_ETBCC(base) & ~(mask)) | (value)))
+#define MCM_SET_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) |  (value)))
+#define MCM_CLR_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) & ~(value)))
+#define MCM_TOG_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBCC bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCC, field CNTEN[0] (RW)
+ *
+ * Enables the ETB counter.
+ *
+ * Values:
+ * - 0b0 - ETB counter disabled
+ * - 0b1 - ETB counter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_CNTEN field. */
+#define MCM_RD_ETBCC_CNTEN(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_CNTEN_MASK) >> MCM_ETBCC_CNTEN_SHIFT)
+#define MCM_BRD_ETBCC_CNTEN(base) (MCM_RD_ETBCC_CNTEN(base))
+
+/*! @brief Set the CNTEN field to a new value. */
+#define MCM_WR_ETBCC_CNTEN(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_CNTEN_MASK, MCM_ETBCC_CNTEN(value)))
+#define MCM_BWR_ETBCC_CNTEN(base, value) (MCM_WR_ETBCC_CNTEN(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
+ *
+ * Values:
+ * - 0b00 - No response when the ETB count expires
+ * - 0b01 - Generate a normal interrupt when the ETB count expires
+ * - 0b10 - Generate an NMI when the ETB count expires
+ * - 0b11 - Generate a debug halt when the ETB count expires
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_RSPT field. */
+#define MCM_RD_ETBCC_RSPT(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_RSPT_MASK) >> MCM_ETBCC_RSPT_SHIFT)
+#define MCM_BRD_ETBCC_RSPT(base) (MCM_RD_ETBCC_RSPT(base))
+
+/*! @brief Set the RSPT field to a new value. */
+#define MCM_WR_ETBCC_RSPT(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_RSPT_MASK, MCM_ETBCC_RSPT(value)))
+#define MCM_BWR_ETBCC_RSPT(base, value) (MCM_WR_ETBCC_RSPT(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field RLRQ[3] (RW)
+ *
+ * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
+ * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
+ * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
+ * If debug halt was enabled and a debug halt request was asserted on counter
+ * expiration, setting this bit clears the debug halt request.
+ *
+ * Values:
+ * - 0b0 - No effect
+ * - 0b1 - Clears pending debug halt, NMI, or IRQ interrupt requests
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_RLRQ field. */
+#define MCM_RD_ETBCC_RLRQ(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_RLRQ_MASK) >> MCM_ETBCC_RLRQ_SHIFT)
+#define MCM_BRD_ETBCC_RLRQ(base) (MCM_RD_ETBCC_RLRQ(base))
+
+/*! @brief Set the RLRQ field to a new value. */
+#define MCM_WR_ETBCC_RLRQ(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_RLRQ_MASK, MCM_ETBCC_RLRQ(value)))
+#define MCM_BWR_ETBCC_RLRQ(base, value) (MCM_WR_ETBCC_RLRQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field ETDIS[4] (RW)
+ *
+ * Disables the trace path from ETM to TPIU.
+ *
+ * Values:
+ * - 0b0 - ETM-to-TPIU trace path enabled
+ * - 0b1 - ETM-to-TPIU trace path disabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_ETDIS field. */
+#define MCM_RD_ETBCC_ETDIS(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_ETDIS_MASK) >> MCM_ETBCC_ETDIS_SHIFT)
+#define MCM_BRD_ETBCC_ETDIS(base) (MCM_RD_ETBCC_ETDIS(base))
+
+/*! @brief Set the ETDIS field to a new value. */
+#define MCM_WR_ETBCC_ETDIS(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_ETDIS_MASK, MCM_ETBCC_ETDIS(value)))
+#define MCM_BWR_ETBCC_ETDIS(base, value) (MCM_WR_ETBCC_ETDIS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field ITDIS[5] (RW)
+ *
+ * Disables the trace path from ITM to TPIU.
+ *
+ * Values:
+ * - 0b0 - ITM-to-TPIU trace path enabled
+ * - 0b1 - ITM-to-TPIU trace path disabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_ITDIS field. */
+#define MCM_RD_ETBCC_ITDIS(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_ITDIS_MASK) >> MCM_ETBCC_ITDIS_SHIFT)
+#define MCM_BRD_ETBCC_ITDIS(base) (MCM_RD_ETBCC_ITDIS(base))
+
+/*! @brief Set the ITDIS field to a new value. */
+#define MCM_WR_ETBCC_ITDIS(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_ITDIS_MASK, MCM_ETBCC_ITDIS(value)))
+#define MCM_BWR_ETBCC_ITDIS(base, value) (MCM_WR_ETBCC_ITDIS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBRL - ETB Reload register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBRL - ETB Reload register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBRL register
+ */
+/*@{*/
+#define MCM_RD_ETBRL(base)       (MCM_ETBRL_REG(base))
+#define MCM_WR_ETBRL(base, value) (MCM_ETBRL_REG(base) = (value))
+#define MCM_RMW_ETBRL(base, mask, value) (MCM_WR_ETBRL(base, (MCM_RD_ETBRL(base) & ~(mask)) | (value)))
+#define MCM_SET_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) |  (value)))
+#define MCM_CLR_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) & ~(value)))
+#define MCM_TOG_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBRL bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
+ *
+ * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
+ * value to this field results in a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBRL_RELOAD field. */
+#define MCM_RD_ETBRL_RELOAD(base) ((MCM_ETBRL_REG(base) & MCM_ETBRL_RELOAD_MASK) >> MCM_ETBRL_RELOAD_SHIFT)
+#define MCM_BRD_ETBRL_RELOAD(base) (MCM_RD_ETBRL_RELOAD(base))
+
+/*! @brief Set the RELOAD field to a new value. */
+#define MCM_WR_ETBRL_RELOAD(base, value) (MCM_RMW_ETBRL(base, MCM_ETBRL_RELOAD_MASK, MCM_ETBRL_RELOAD(value)))
+#define MCM_BWR_ETBRL_RELOAD(base, value) (MCM_WR_ETBRL_RELOAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBCNT - ETB Counter Value register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBCNT - ETB Counter Value register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBCNT register
+ */
+/*@{*/
+#define MCM_RD_ETBCNT(base)      (MCM_ETBCNT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBCNT bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
+ *
+ * Indicates the current 0-mod-4 value of the counter.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCNT_COUNTER field. */
+#define MCM_RD_ETBCNT_COUNTER(base) ((MCM_ETBCNT_REG(base) & MCM_ETBCNT_COUNTER_MASK) >> MCM_ETBCNT_COUNTER_SHIFT)
+#define MCM_BRD_ETBCNT_COUNTER(base) (MCM_RD_ETBCNT_COUNTER(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PID - Process ID register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PID - Process ID register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register drives the M0_PID and M1_PID values in the Memory Protection
+ * Unit(MPU). System software loads this register before passing control to a given
+ * user mode process. If the PID of the process does not match the value in this
+ * register, a bus error occurs. See the MPU chapter for more details.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PID register
+ */
+/*@{*/
+#define MCM_RD_PID(base)         (MCM_PID_REG(base))
+#define MCM_WR_PID(base, value)  (MCM_PID_REG(base) = (value))
+#define MCM_RMW_PID(base, mask, value) (MCM_WR_PID(base, (MCM_RD_PID(base) & ~(mask)) | (value)))
+#define MCM_SET_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) |  (value)))
+#define MCM_CLR_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) & ~(value)))
+#define MCM_TOG_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PID bitfields
+ */
+
+/*!
+ * @name Register MCM_PID, field PID[7:0] (RW)
+ *
+ * Drives the M0_PID and M1_PID values in the MPU.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PID_PID field. */
+#define MCM_RD_PID_PID(base) ((MCM_PID_REG(base) & MCM_PID_PID_MASK) >> MCM_PID_PID_SHIFT)
+#define MCM_BRD_PID_PID(base) (MCM_RD_PID_PID(base))
+
+/*! @brief Set the PID field to a new value. */
+#define MCM_WR_PID_PID(base, value) (MCM_RMW_PID(base, MCM_PID_PID_MASK, MCM_PID_PID(value)))
+#define MCM_BWR_PID_PID(base, value) (MCM_WR_PID_PID(base, value))
+/*@}*/
+
+/*
+ * MK64F12 MPU
+ *
+ * Memory protection unit
+ *
+ * Registers defined in this header file:
+ * - MPU_CESR - Control/Error Status Register
+ * - MPU_EAR - Error Address Register, slave port n
+ * - MPU_EDR - Error Detail Register, slave port n
+ * - MPU_WORD - Region Descriptor n, Word 0
+ * - MPU_RGDAAC - Region Descriptor Alternate Access Control n
+ */
+
+#define MPU_INSTANCE_COUNT (1U) /*!< Number of instances of the MPU module. */
+#define MPU_IDX (0U) /*!< Instance number for MPU. */
+
+/*******************************************************************************
+ * MPU_CESR - Control/Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_CESR - Control/Error Status Register (RW)
+ *
+ * Reset value: 0x00815101U
+ */
+/*!
+ * @name Constants and macros for entire MPU_CESR register
+ */
+/*@{*/
+#define MPU_RD_CESR(base)        (MPU_CESR_REG(base))
+#define MPU_WR_CESR(base, value) (MPU_CESR_REG(base) = (value))
+#define MPU_RMW_CESR(base, mask, value) (MPU_WR_CESR(base, (MPU_RD_CESR(base) & ~(mask)) | (value)))
+#define MPU_SET_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) |  (value)))
+#define MPU_CLR_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) & ~(value)))
+#define MPU_TOG_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_CESR bitfields
+ */
+
+/*!
+ * @name Register MPU_CESR, field VLD[0] (RW)
+ *
+ * Global enable/disable for the MPU.
+ *
+ * Values:
+ * - 0b0 - MPU is disabled. All accesses from all bus masters are allowed.
+ * - 0b1 - MPU is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_VLD field. */
+#define MPU_RD_CESR_VLD(base) ((MPU_CESR_REG(base) & MPU_CESR_VLD_MASK) >> MPU_CESR_VLD_SHIFT)
+#define MPU_BRD_CESR_VLD(base) (BITBAND_ACCESS32(&MPU_CESR_REG(base), MPU_CESR_VLD_SHIFT))
+
+/*! @brief Set the VLD field to a new value. */
+#define MPU_WR_CESR_VLD(base, value) (MPU_RMW_CESR(base, (MPU_CESR_VLD_MASK | MPU_CESR_SPERR_MASK), MPU_CESR_VLD(value)))
+#define MPU_BWR_CESR_VLD(base, value) (BITBAND_ACCESS32(&MPU_CESR_REG(base), MPU_CESR_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field NRGD[11:8] (RO)
+ *
+ * Indicates the number of region descriptors implemented in the MPU.
+ *
+ * Values:
+ * - 0b0000 - 8 region descriptors
+ * - 0b0001 - 12 region descriptors
+ * - 0b0010 - 16 region descriptors
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_NRGD field. */
+#define MPU_RD_CESR_NRGD(base) ((MPU_CESR_REG(base) & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT)
+#define MPU_BRD_CESR_NRGD(base) (MPU_RD_CESR_NRGD(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field NSP[15:12] (RO)
+ *
+ * Specifies the number of slave ports connected to the MPU.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_NSP field. */
+#define MPU_RD_CESR_NSP(base) ((MPU_CESR_REG(base) & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT)
+#define MPU_BRD_CESR_NSP(base) (MPU_RD_CESR_NSP(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field HRL[19:16] (RO)
+ *
+ * Specifies the MPU's hardware and definition revision level. It can be read by
+ * software to determine the functional definition of the module.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_HRL field. */
+#define MPU_RD_CESR_HRL(base) ((MPU_CESR_REG(base) & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT)
+#define MPU_BRD_CESR_HRL(base) (MPU_RD_CESR_HRL(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field SPERR[31:27] (W1C)
+ *
+ * Indicates a captured error in EARn and EDRn. This bit is set when the
+ * hardware detects an error and records the faulting address and attributes. It is
+ * cleared by writing one to it. If another error is captured at the exact same cycle
+ * as the write, the flag remains set. A find-first-one instruction or
+ * equivalent can detect the presence of a captured error. The following shows the
+ * correspondence between the bit number and slave port number: Bit 31 corresponds to
+ * slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
+ * port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
+ *
+ * Values:
+ * - 0b00000 - No error has occurred for slave port n.
+ * - 0b00001 - An error has occurred for slave port n.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_SPERR field. */
+#define MPU_RD_CESR_SPERR(base) ((MPU_CESR_REG(base) & MPU_CESR_SPERR_MASK) >> MPU_CESR_SPERR_SHIFT)
+#define MPU_BRD_CESR_SPERR(base) (MPU_RD_CESR_SPERR(base))
+
+/*! @brief Set the SPERR field to a new value. */
+#define MPU_WR_CESR_SPERR(base, value) (MPU_RMW_CESR(base, MPU_CESR_SPERR_MASK, MPU_CESR_SPERR(value)))
+#define MPU_BWR_CESR_SPERR(base, value) (MPU_WR_CESR_SPERR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_EAR - Error Address Register, slave port n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_EAR - Error Address Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, the 32-bit reference
+ * address is captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] set. Additional information about the faulting access is captured in
+ * the corresponding EDRn at the same time. This register and the corresponding
+ * EDRn contain the most recent access error; there are no hardware interlocks with
+ * CESR[SPERR], as the error registers are always loaded upon the occurrence of
+ * each protection violation.
+ */
+/*!
+ * @name Constants and macros for entire MPU_EAR register
+ */
+/*@{*/
+#define MPU_RD_EAR(base, index)  (MPU_EAR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_EDR - Error Detail Register, slave port n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_EDR - Error Detail Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, 32 bits of error detail
+ * are captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] is set. Information on the faulting address is captured in the
+ * corresponding EARn register at the same time. This register and the corresponding EARn
+ * register contain the most recent access error; there are no hardware interlocks
+ * with CESR[SPERR] as the error registers are always loaded upon the occurrence
+ * of each protection violation.
+ */
+/*!
+ * @name Constants and macros for entire MPU_EDR register
+ */
+/*@{*/
+#define MPU_RD_EDR(base, index)  (MPU_EDR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_EDR bitfields
+ */
+
+/*!
+ * @name Register MPU_EDR, field ERW[0] (RO)
+ *
+ * Indicates the access type of the faulting reference.
+ *
+ * Values:
+ * - 0b0 - Read
+ * - 0b1 - Write
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_ERW field. */
+#define MPU_RD_EDR_ERW(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT)
+#define MPU_BRD_EDR_ERW(base, index) (BITBAND_ACCESS32(&MPU_EDR_REG(base, index), MPU_EDR_ERW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EATTR[3:1] (RO)
+ *
+ * Indicates attribute information about the faulting reference. All other
+ * encodings are reserved.
+ *
+ * Values:
+ * - 0b000 - User mode, instruction access
+ * - 0b001 - User mode, data access
+ * - 0b010 - Supervisor mode, instruction access
+ * - 0b011 - Supervisor mode, data access
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EATTR field. */
+#define MPU_RD_EDR_EATTR(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT)
+#define MPU_BRD_EDR_EATTR(base, index) (MPU_RD_EDR_EATTR(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EMN[7:4] (RO)
+ *
+ * Indicates the bus master that generated the access error.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EMN field. */
+#define MPU_RD_EDR_EMN(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT)
+#define MPU_BRD_EDR_EMN(base, index) (MPU_RD_EDR_EMN(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EPID[15:8] (RO)
+ *
+ * Records the process identifier of the faulting reference. The process
+ * identifier is typically driven only by processor cores; for other bus masters, this
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EPID field. */
+#define MPU_RD_EDR_EPID(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT)
+#define MPU_BRD_EDR_EPID(base, index) (MPU_RD_EDR_EPID(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EACD[31:16] (RO)
+ *
+ * Indicates the region descriptor with the access error. If EDRn contains a
+ * captured error and EACD is cleared, an access did not hit in any region
+ * descriptor. If only a single EACD bit is set, the protection error was caused by a
+ * single non-overlapping region descriptor. If two or more EACD bits are set, the
+ * protection error was caused by an overlapping set of region descriptors.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EACD field. */
+#define MPU_RD_EDR_EACD(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EACD_MASK) >> MPU_EDR_EACD_SHIFT)
+#define MPU_BRD_EDR_EACD(base, index) (MPU_RD_EDR_EACD(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_WORD - Region Descriptor n, Word 0
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_WORD - Region Descriptor n, Word 0 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The first word of the region descriptor defines the 0-modulo-32 byte start
+ * address of the memory region. Writes to this register clear the region
+ * descriptor's valid bit (RGDn_WORD3[VLD]).
+ */
+/*!
+ * @name Constants and macros for entire MPU_WORD register
+ */
+/*@{*/
+#define MPU_RD_WORD(base, index, index2) (MPU_WORD_REG(base, index, index2))
+#define MPU_WR_WORD(base, index, index2, value) (MPU_WORD_REG(base, index, index2) = (value))
+#define MPU_RMW_WORD(base, index, index2, mask, value) (MPU_WR_WORD(base, index, index2, (MPU_RD_WORD(base, index, index2) & ~(mask)) | (value)))
+#define MPU_SET_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) |  (value)))
+#define MPU_CLR_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) & ~(value)))
+#define MPU_TOG_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_WORD bitfields
+ */
+
+/*!
+ * @name Register MPU_WORD, field VLD[0] (RW)
+ *
+ * Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
+ * bit.
+ *
+ * Values:
+ * - 0b0 - Region descriptor is invalid
+ * - 0b1 - Region descriptor is valid
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_VLD field. */
+#define MPU_RD_WORD_VLD(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_VLD_MASK) >> MPU_WORD_VLD_SHIFT)
+#define MPU_BRD_WORD_VLD(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_VLD_SHIFT))
+
+/*! @brief Set the VLD field to a new value. */
+#define MPU_WR_WORD_VLD(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_VLD_MASK, MPU_WORD_VLD(value)))
+#define MPU_BWR_WORD_VLD(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0UM field. */
+#define MPU_RD_WORD_M0UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0UM_MASK) >> MPU_WORD_M0UM_SHIFT)
+#define MPU_BRD_WORD_M0UM(base, index, index2) (MPU_RD_WORD_M0UM(base, index, index2))
+
+/*! @brief Set the M0UM field to a new value. */
+#define MPU_WR_WORD_M0UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0UM_MASK, MPU_WORD_M0UM(value)))
+#define MPU_BWR_WORD_M0UM(base, index, index2, value) (MPU_WR_WORD_M0UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0SM field. */
+#define MPU_RD_WORD_M0SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0SM_MASK) >> MPU_WORD_M0SM_SHIFT)
+#define MPU_BRD_WORD_M0SM(base, index, index2) (MPU_RD_WORD_M0SM(base, index, index2))
+
+/*! @brief Set the M0SM field to a new value. */
+#define MPU_WR_WORD_M0SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0SM_MASK, MPU_WORD_M0SM(value)))
+#define MPU_BWR_WORD_M0SM(base, index, index2, value) (MPU_WR_WORD_M0SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0PE[5] (RW)
+ *
+ * See M0PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0PE field. */
+#define MPU_RD_WORD_M0PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0PE_MASK) >> MPU_WORD_M0PE_SHIFT)
+#define MPU_BRD_WORD_M0PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M0PE_SHIFT))
+
+/*! @brief Set the M0PE field to a new value. */
+#define MPU_WR_WORD_M0PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0PE_MASK, MPU_WORD_M0PE(value)))
+#define MPU_BWR_WORD_M0PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M0PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field ENDADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 31-modulo-32 byte end address of the
+ * memory region. The MPU does not verify that ENDADDR >= SRTADDR.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_ENDADDR field. */
+#define MPU_RD_WORD_ENDADDR(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_ENDADDR_MASK) >> MPU_WORD_ENDADDR_SHIFT)
+#define MPU_BRD_WORD_ENDADDR(base, index, index2) (MPU_RD_WORD_ENDADDR(base, index, index2))
+
+/*! @brief Set the ENDADDR field to a new value. */
+#define MPU_WR_WORD_ENDADDR(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_ENDADDR_MASK, MPU_WORD_ENDADDR(value)))
+#define MPU_BWR_WORD_ENDADDR(base, index, index2, value) (MPU_WR_WORD_ENDADDR(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field SRTADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 0-modulo-32 byte start address of
+ * the memory region.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_SRTADDR field. */
+#define MPU_RD_WORD_SRTADDR(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_SRTADDR_MASK) >> MPU_WORD_SRTADDR_SHIFT)
+#define MPU_BRD_WORD_SRTADDR(base, index, index2) (MPU_RD_WORD_SRTADDR(base, index, index2))
+
+/*! @brief Set the SRTADDR field to a new value. */
+#define MPU_WR_WORD_SRTADDR(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_SRTADDR_MASK, MPU_WORD_SRTADDR(value)))
+#define MPU_BWR_WORD_SRTADDR(base, index, index2, value) (MPU_WR_WORD_SRTADDR(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1UM field. */
+#define MPU_RD_WORD_M1UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1UM_MASK) >> MPU_WORD_M1UM_SHIFT)
+#define MPU_BRD_WORD_M1UM(base, index, index2) (MPU_RD_WORD_M1UM(base, index, index2))
+
+/*! @brief Set the M1UM field to a new value. */
+#define MPU_WR_WORD_M1UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1UM_MASK, MPU_WORD_M1UM(value)))
+#define MPU_BWR_WORD_M1UM(base, index, index2, value) (MPU_WR_WORD_M1UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1SM field. */
+#define MPU_RD_WORD_M1SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1SM_MASK) >> MPU_WORD_M1SM_SHIFT)
+#define MPU_BRD_WORD_M1SM(base, index, index2) (MPU_RD_WORD_M1SM(base, index, index2))
+
+/*! @brief Set the M1SM field to a new value. */
+#define MPU_WR_WORD_M1SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1SM_MASK, MPU_WORD_M1SM(value)))
+#define MPU_BWR_WORD_M1SM(base, index, index2, value) (MPU_WR_WORD_M1SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1PE field. */
+#define MPU_RD_WORD_M1PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1PE_MASK) >> MPU_WORD_M1PE_SHIFT)
+#define MPU_BRD_WORD_M1PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M1PE_SHIFT))
+
+/*! @brief Set the M1PE field to a new value. */
+#define MPU_WR_WORD_M1PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1PE_MASK, MPU_WORD_M1PE(value)))
+#define MPU_BWR_WORD_M1PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M1PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2UM field. */
+#define MPU_RD_WORD_M2UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2UM_MASK) >> MPU_WORD_M2UM_SHIFT)
+#define MPU_BRD_WORD_M2UM(base, index, index2) (MPU_RD_WORD_M2UM(base, index, index2))
+
+/*! @brief Set the M2UM field to a new value. */
+#define MPU_WR_WORD_M2UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2UM_MASK, MPU_WORD_M2UM(value)))
+#define MPU_BWR_WORD_M2UM(base, index, index2, value) (MPU_WR_WORD_M2UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2SM field. */
+#define MPU_RD_WORD_M2SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2SM_MASK) >> MPU_WORD_M2SM_SHIFT)
+#define MPU_BRD_WORD_M2SM(base, index, index2) (MPU_RD_WORD_M2SM(base, index, index2))
+
+/*! @brief Set the M2SM field to a new value. */
+#define MPU_WR_WORD_M2SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2SM_MASK, MPU_WORD_M2SM(value)))
+#define MPU_BWR_WORD_M2SM(base, index, index2, value) (MPU_WR_WORD_M2SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field PIDMASK[23:16] (RW)
+ *
+ * Provides a masking capability so that multiple process identifiers can be
+ * included as part of the region hit determination. If a bit in PIDMASK is set,
+ * then the corresponding PID bit is ignored in the comparison. This field and PID
+ * are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
+ * more information on the handling of the PID and PIDMASK, see "Access Evaluation
+ * - Hit Determination."
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_PIDMASK field. */
+#define MPU_RD_WORD_PIDMASK(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_PIDMASK_MASK) >> MPU_WORD_PIDMASK_SHIFT)
+#define MPU_BRD_WORD_PIDMASK(base, index, index2) (MPU_RD_WORD_PIDMASK(base, index, index2))
+
+/*! @brief Set the PIDMASK field to a new value. */
+#define MPU_WR_WORD_PIDMASK(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_PIDMASK_MASK, MPU_WORD_PIDMASK(value)))
+#define MPU_BWR_WORD_PIDMASK(base, index, index2, value) (MPU_WR_WORD_PIDMASK(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2PE field. */
+#define MPU_RD_WORD_M2PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2PE_MASK) >> MPU_WORD_M2PE_SHIFT)
+#define MPU_BRD_WORD_M2PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M2PE_SHIFT))
+
+/*! @brief Set the M2PE field to a new value. */
+#define MPU_WR_WORD_M2PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2PE_MASK, MPU_WORD_M2PE(value)))
+#define MPU_BWR_WORD_M2PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M2PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in User mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0b000 - An attempted access of that mode may be terminated with an access
+ *     error (if not allowed by another descriptor) and the access not performed.
+ * - 0b001 - Allows the given access type to occur
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3UM field. */
+#define MPU_RD_WORD_M3UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3UM_MASK) >> MPU_WORD_M3UM_SHIFT)
+#define MPU_BRD_WORD_M3UM(base, index, index2) (MPU_RD_WORD_M3UM(base, index, index2))
+
+/*! @brief Set the M3UM field to a new value. */
+#define MPU_WR_WORD_M3UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3UM_MASK, MPU_WORD_M3UM(value)))
+#define MPU_BWR_WORD_M3UM(base, index, index2, value) (MPU_WR_WORD_M3UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 0b00 - r/w/x; read, write and execute allowed
+ * - 0b01 - r/x; read and execute allowed, but no write
+ * - 0b10 - r/w; read and write allowed, but no execute
+ * - 0b11 - Same as User mode defined in M3UM
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3SM field. */
+#define MPU_RD_WORD_M3SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3SM_MASK) >> MPU_WORD_M3SM_SHIFT)
+#define MPU_BRD_WORD_M3SM(base, index, index2) (MPU_RD_WORD_M3SM(base, index, index2))
+
+/*! @brief Set the M3SM field to a new value. */
+#define MPU_WR_WORD_M3SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3SM_MASK, MPU_WORD_M3SM(value)))
+#define MPU_BWR_WORD_M3SM(base, index, index2, value) (MPU_WR_WORD_M3SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the process identifier in the evaluation
+ * - 0b1 - Include the process identifier and mask (RGDn_WORD3) in the region
+ *     hit evaluation
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3PE field. */
+#define MPU_RD_WORD_M3PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3PE_MASK) >> MPU_WORD_M3PE_SHIFT)
+#define MPU_BRD_WORD_M3PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M3PE_SHIFT))
+
+/*! @brief Set the M3PE field to a new value. */
+#define MPU_WR_WORD_M3PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3PE_MASK, MPU_WORD_M3PE(value)))
+#define MPU_BWR_WORD_M3PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M3PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field PID[31:24] (RW)
+ *
+ * Specifies the process identifier that is included in the region hit
+ * determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
+ * field.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_PID field. */
+#define MPU_RD_WORD_PID(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_PID_MASK) >> MPU_WORD_PID_SHIFT)
+#define MPU_BRD_WORD_PID(base, index, index2) (MPU_RD_WORD_PID(base, index, index2))
+
+/*! @brief Set the PID field to a new value. */
+#define MPU_WR_WORD_PID(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_PID_MASK, MPU_WORD_PID(value)))
+#define MPU_BWR_WORD_PID(base, index, index2, value) (MPU_WR_WORD_PID(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 4 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M4WE field. */
+#define MPU_RD_WORD_M4WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M4WE_MASK) >> MPU_WORD_M4WE_SHIFT)
+#define MPU_BRD_WORD_M4WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4WE_SHIFT))
+
+/*! @brief Set the M4WE field to a new value. */
+#define MPU_WR_WORD_M4WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M4WE_MASK, MPU_WORD_M4WE(value)))
+#define MPU_BWR_WORD_M4WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 4 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M4RE field. */
+#define MPU_RD_WORD_M4RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M4RE_MASK) >> MPU_WORD_M4RE_SHIFT)
+#define MPU_BRD_WORD_M4RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4RE_SHIFT))
+
+/*! @brief Set the M4RE field to a new value. */
+#define MPU_WR_WORD_M4RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M4RE_MASK, MPU_WORD_M4RE(value)))
+#define MPU_BWR_WORD_M4RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 5 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M5WE field. */
+#define MPU_RD_WORD_M5WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M5WE_MASK) >> MPU_WORD_M5WE_SHIFT)
+#define MPU_BRD_WORD_M5WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5WE_SHIFT))
+
+/*! @brief Set the M5WE field to a new value. */
+#define MPU_WR_WORD_M5WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M5WE_MASK, MPU_WORD_M5WE(value)))
+#define MPU_BWR_WORD_M5WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 5 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M5RE field. */
+#define MPU_RD_WORD_M5RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M5RE_MASK) >> MPU_WORD_M5RE_SHIFT)
+#define MPU_BRD_WORD_M5RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5RE_SHIFT))
+
+/*! @brief Set the M5RE field to a new value. */
+#define MPU_WR_WORD_M5RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M5RE_MASK, MPU_WORD_M5RE(value)))
+#define MPU_BWR_WORD_M5RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 6 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M6WE field. */
+#define MPU_RD_WORD_M6WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M6WE_MASK) >> MPU_WORD_M6WE_SHIFT)
+#define MPU_BRD_WORD_M6WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6WE_SHIFT))
+
+/*! @brief Set the M6WE field to a new value. */
+#define MPU_WR_WORD_M6WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M6WE_MASK, MPU_WORD_M6WE(value)))
+#define MPU_BWR_WORD_M6WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 6 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M6RE field. */
+#define MPU_RD_WORD_M6RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M6RE_MASK) >> MPU_WORD_M6RE_SHIFT)
+#define MPU_BRD_WORD_M6RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6RE_SHIFT))
+
+/*! @brief Set the M6RE field to a new value. */
+#define MPU_WR_WORD_M6RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M6RE_MASK, MPU_WORD_M6RE(value)))
+#define MPU_BWR_WORD_M6RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 7 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M7WE field. */
+#define MPU_RD_WORD_M7WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M7WE_MASK) >> MPU_WORD_M7WE_SHIFT)
+#define MPU_BRD_WORD_M7WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7WE_SHIFT))
+
+/*! @brief Set the M7WE field to a new value. */
+#define MPU_WR_WORD_M7WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M7WE_MASK, MPU_WORD_M7WE(value)))
+#define MPU_BWR_WORD_M7WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 7 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M7RE field. */
+#define MPU_RD_WORD_M7RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M7RE_MASK) >> MPU_WORD_M7RE_SHIFT)
+#define MPU_BRD_WORD_M7RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7RE_SHIFT))
+
+/*! @brief Set the M7RE field to a new value. */
+#define MPU_WR_WORD_M7RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M7RE_MASK, MPU_WORD_M7RE(value)))
+#define MPU_BWR_WORD_M7RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_RGDAAC - Region Descriptor Alternate Access Control n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_RGDAAC - Region Descriptor Alternate Access Control n (RW)
+ *
+ * Reset value: 0x0061F7DFU
+ *
+ * Because software may adjust only the access controls within a region
+ * descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
+ * this 32-bit entity is available. Writing to this register does not affect the
+ * descriptor's valid bit.
+ */
+/*!
+ * @name Constants and macros for entire MPU_RGDAAC register
+ */
+/*@{*/
+#define MPU_RD_RGDAAC(base, index) (MPU_RGDAAC_REG(base, index))
+#define MPU_WR_RGDAAC(base, index, value) (MPU_RGDAAC_REG(base, index) = (value))
+#define MPU_RMW_RGDAAC(base, index, mask, value) (MPU_WR_RGDAAC(base, index, (MPU_RD_RGDAAC(base, index) & ~(mask)) | (value)))
+#define MPU_SET_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) |  (value)))
+#define MPU_CLR_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) & ~(value)))
+#define MPU_TOG_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_RGDAAC bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDAAC, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0UM field. */
+#define MPU_RD_RGDAAC_M0UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0UM_MASK) >> MPU_RGDAAC_M0UM_SHIFT)
+#define MPU_BRD_RGDAAC_M0UM(base, index) (MPU_RD_RGDAAC_M0UM(base, index))
+
+/*! @brief Set the M0UM field to a new value. */
+#define MPU_WR_RGDAAC_M0UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0UM_MASK, MPU_RGDAAC_M0UM(value)))
+#define MPU_BWR_RGDAAC_M0UM(base, index, value) (MPU_WR_RGDAAC_M0UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0SM field. */
+#define MPU_RD_RGDAAC_M0SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0SM_MASK) >> MPU_RGDAAC_M0SM_SHIFT)
+#define MPU_BRD_RGDAAC_M0SM(base, index) (MPU_RD_RGDAAC_M0SM(base, index))
+
+/*! @brief Set the M0SM field to a new value. */
+#define MPU_WR_RGDAAC_M0SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0SM_MASK, MPU_RGDAAC_M0SM(value)))
+#define MPU_BWR_RGDAAC_M0SM(base, index, value) (MPU_WR_RGDAAC_M0SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M0PE[5] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0PE field. */
+#define MPU_RD_RGDAAC_M0PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0PE_MASK) >> MPU_RGDAAC_M0PE_SHIFT)
+#define MPU_BRD_RGDAAC_M0PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M0PE_SHIFT))
+
+/*! @brief Set the M0PE field to a new value. */
+#define MPU_WR_RGDAAC_M0PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0PE_MASK, MPU_RGDAAC_M0PE(value)))
+#define MPU_BWR_RGDAAC_M0PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M0PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1UM field. */
+#define MPU_RD_RGDAAC_M1UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1UM_MASK) >> MPU_RGDAAC_M1UM_SHIFT)
+#define MPU_BRD_RGDAAC_M1UM(base, index) (MPU_RD_RGDAAC_M1UM(base, index))
+
+/*! @brief Set the M1UM field to a new value. */
+#define MPU_WR_RGDAAC_M1UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1UM_MASK, MPU_RGDAAC_M1UM(value)))
+#define MPU_BWR_RGDAAC_M1UM(base, index, value) (MPU_WR_RGDAAC_M1UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1SM field. */
+#define MPU_RD_RGDAAC_M1SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1SM_MASK) >> MPU_RGDAAC_M1SM_SHIFT)
+#define MPU_BRD_RGDAAC_M1SM(base, index) (MPU_RD_RGDAAC_M1SM(base, index))
+
+/*! @brief Set the M1SM field to a new value. */
+#define MPU_WR_RGDAAC_M1SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1SM_MASK, MPU_RGDAAC_M1SM(value)))
+#define MPU_BWR_RGDAAC_M1SM(base, index, value) (MPU_WR_RGDAAC_M1SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1PE field. */
+#define MPU_RD_RGDAAC_M1PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1PE_MASK) >> MPU_RGDAAC_M1PE_SHIFT)
+#define MPU_BRD_RGDAAC_M1PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M1PE_SHIFT))
+
+/*! @brief Set the M1PE field to a new value. */
+#define MPU_WR_RGDAAC_M1PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1PE_MASK, MPU_RGDAAC_M1PE(value)))
+#define MPU_BWR_RGDAAC_M1PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M1PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2UM field. */
+#define MPU_RD_RGDAAC_M2UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2UM_MASK) >> MPU_RGDAAC_M2UM_SHIFT)
+#define MPU_BRD_RGDAAC_M2UM(base, index) (MPU_RD_RGDAAC_M2UM(base, index))
+
+/*! @brief Set the M2UM field to a new value. */
+#define MPU_WR_RGDAAC_M2UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2UM_MASK, MPU_RGDAAC_M2UM(value)))
+#define MPU_BWR_RGDAAC_M2UM(base, index, value) (MPU_WR_RGDAAC_M2UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2SM field. */
+#define MPU_RD_RGDAAC_M2SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2SM_MASK) >> MPU_RGDAAC_M2SM_SHIFT)
+#define MPU_BRD_RGDAAC_M2SM(base, index) (MPU_RD_RGDAAC_M2SM(base, index))
+
+/*! @brief Set the M2SM field to a new value. */
+#define MPU_WR_RGDAAC_M2SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2SM_MASK, MPU_RGDAAC_M2SM(value)))
+#define MPU_BWR_RGDAAC_M2SM(base, index, value) (MPU_WR_RGDAAC_M2SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2PE field. */
+#define MPU_RD_RGDAAC_M2PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2PE_MASK) >> MPU_RGDAAC_M2PE_SHIFT)
+#define MPU_BRD_RGDAAC_M2PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M2PE_SHIFT))
+
+/*! @brief Set the M2PE field to a new value. */
+#define MPU_WR_RGDAAC_M2PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2PE_MASK, MPU_RGDAAC_M2PE(value)))
+#define MPU_BWR_RGDAAC_M2PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M2PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in user mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0b000 - An attempted access of that mode may be terminated with an access
+ *     error (if not allowed by another descriptor) and the access not performed.
+ * - 0b001 - Allows the given access type to occur
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3UM field. */
+#define MPU_RD_RGDAAC_M3UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3UM_MASK) >> MPU_RGDAAC_M3UM_SHIFT)
+#define MPU_BRD_RGDAAC_M3UM(base, index) (MPU_RD_RGDAAC_M3UM(base, index))
+
+/*! @brief Set the M3UM field to a new value. */
+#define MPU_WR_RGDAAC_M3UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3UM_MASK, MPU_RGDAAC_M3UM(value)))
+#define MPU_BWR_RGDAAC_M3UM(base, index, value) (MPU_WR_RGDAAC_M3UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 0b00 - r/w/x; read, write and execute allowed
+ * - 0b01 - r/x; read and execute allowed, but no write
+ * - 0b10 - r/w; read and write allowed, but no execute
+ * - 0b11 - Same as User mode defined in M3UM
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3SM field. */
+#define MPU_RD_RGDAAC_M3SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3SM_MASK) >> MPU_RGDAAC_M3SM_SHIFT)
+#define MPU_BRD_RGDAAC_M3SM(base, index) (MPU_RD_RGDAAC_M3SM(base, index))
+
+/*! @brief Set the M3SM field to a new value. */
+#define MPU_WR_RGDAAC_M3SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3SM_MASK, MPU_RGDAAC_M3SM(value)))
+#define MPU_BWR_RGDAAC_M3SM(base, index, value) (MPU_WR_RGDAAC_M3SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the process identifier in the evaluation
+ * - 0b1 - Include the process identifier and mask (RGDn.RGDAAC) in the region
+ *     hit evaluation
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3PE field. */
+#define MPU_RD_RGDAAC_M3PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3PE_MASK) >> MPU_RGDAAC_M3PE_SHIFT)
+#define MPU_BRD_RGDAAC_M3PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M3PE_SHIFT))
+
+/*! @brief Set the M3PE field to a new value. */
+#define MPU_WR_RGDAAC_M3PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3PE_MASK, MPU_RGDAAC_M3PE(value)))
+#define MPU_BWR_RGDAAC_M3PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M3PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 4 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M4WE field. */
+#define MPU_RD_RGDAAC_M4WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M4WE_MASK) >> MPU_RGDAAC_M4WE_SHIFT)
+#define MPU_BRD_RGDAAC_M4WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4WE_SHIFT))
+
+/*! @brief Set the M4WE field to a new value. */
+#define MPU_WR_RGDAAC_M4WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M4WE_MASK, MPU_RGDAAC_M4WE(value)))
+#define MPU_BWR_RGDAAC_M4WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 4 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M4RE field. */
+#define MPU_RD_RGDAAC_M4RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M4RE_MASK) >> MPU_RGDAAC_M4RE_SHIFT)
+#define MPU_BRD_RGDAAC_M4RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4RE_SHIFT))
+
+/*! @brief Set the M4RE field to a new value. */
+#define MPU_WR_RGDAAC_M4RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M4RE_MASK, MPU_RGDAAC_M4RE(value)))
+#define MPU_BWR_RGDAAC_M4RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 5 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M5WE field. */
+#define MPU_RD_RGDAAC_M5WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M5WE_MASK) >> MPU_RGDAAC_M5WE_SHIFT)
+#define MPU_BRD_RGDAAC_M5WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5WE_SHIFT))
+
+/*! @brief Set the M5WE field to a new value. */
+#define MPU_WR_RGDAAC_M5WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M5WE_MASK, MPU_RGDAAC_M5WE(value)))
+#define MPU_BWR_RGDAAC_M5WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 5 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M5RE field. */
+#define MPU_RD_RGDAAC_M5RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M5RE_MASK) >> MPU_RGDAAC_M5RE_SHIFT)
+#define MPU_BRD_RGDAAC_M5RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5RE_SHIFT))
+
+/*! @brief Set the M5RE field to a new value. */
+#define MPU_WR_RGDAAC_M5RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M5RE_MASK, MPU_RGDAAC_M5RE(value)))
+#define MPU_BWR_RGDAAC_M5RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 6 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M6WE field. */
+#define MPU_RD_RGDAAC_M6WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M6WE_MASK) >> MPU_RGDAAC_M6WE_SHIFT)
+#define MPU_BRD_RGDAAC_M6WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6WE_SHIFT))
+
+/*! @brief Set the M6WE field to a new value. */
+#define MPU_WR_RGDAAC_M6WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M6WE_MASK, MPU_RGDAAC_M6WE(value)))
+#define MPU_BWR_RGDAAC_M6WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 6 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M6RE field. */
+#define MPU_RD_RGDAAC_M6RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M6RE_MASK) >> MPU_RGDAAC_M6RE_SHIFT)
+#define MPU_BRD_RGDAAC_M6RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6RE_SHIFT))
+
+/*! @brief Set the M6RE field to a new value. */
+#define MPU_WR_RGDAAC_M6RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M6RE_MASK, MPU_RGDAAC_M6RE(value)))
+#define MPU_BWR_RGDAAC_M6RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 7 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M7WE field. */
+#define MPU_RD_RGDAAC_M7WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M7WE_MASK) >> MPU_RGDAAC_M7WE_SHIFT)
+#define MPU_BRD_RGDAAC_M7WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7WE_SHIFT))
+
+/*! @brief Set the M7WE field to a new value. */
+#define MPU_WR_RGDAAC_M7WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M7WE_MASK, MPU_RGDAAC_M7WE(value)))
+#define MPU_BWR_RGDAAC_M7WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 7 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M7RE field. */
+#define MPU_RD_RGDAAC_M7RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M7RE_MASK) >> MPU_RGDAAC_M7RE_SHIFT)
+#define MPU_BRD_RGDAAC_M7RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7RE_SHIFT))
+
+/*! @brief Set the M7RE field to a new value. */
+#define MPU_WR_RGDAAC_M7RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M7RE_MASK, MPU_RGDAAC_M7RE(value)))
+#define MPU_BWR_RGDAAC_M7RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7RE_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 NV
+ *
+ * Flash configuration field
+ *
+ * Registers defined in this header file:
+ * - NV_BACKKEY3 - Backdoor Comparison Key 3.
+ * - NV_BACKKEY2 - Backdoor Comparison Key 2.
+ * - NV_BACKKEY1 - Backdoor Comparison Key 1.
+ * - NV_BACKKEY0 - Backdoor Comparison Key 0.
+ * - NV_BACKKEY7 - Backdoor Comparison Key 7.
+ * - NV_BACKKEY6 - Backdoor Comparison Key 6.
+ * - NV_BACKKEY5 - Backdoor Comparison Key 5.
+ * - NV_BACKKEY4 - Backdoor Comparison Key 4.
+ * - NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ * - NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ * - NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ * - NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ * - NV_FSEC - Non-volatile Flash Security Register
+ * - NV_FOPT - Non-volatile Flash Option Register
+ * - NV_FEPROT - Non-volatile EERAM Protection Register
+ * - NV_FDPROT - Non-volatile D-Flash Protection Register
+ */
+
+#define NV_INSTANCE_COUNT (1U) /*!< Number of instances of the NV module. */
+#define FTFE_FlashConfig_IDX (0U) /*!< Instance number for FTFE_FlashConfig. */
+
+/*******************************************************************************
+ * NV_BACKKEY3 - Backdoor Comparison Key 3.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY3 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY3(base)     (NV_BACKKEY3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY2 - Backdoor Comparison Key 2.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY2 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY2(base)     (NV_BACKKEY2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY1 - Backdoor Comparison Key 1.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY1 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY1(base)     (NV_BACKKEY1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY0 - Backdoor Comparison Key 0.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY0 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY0(base)     (NV_BACKKEY0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY7 - Backdoor Comparison Key 7.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY7 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY7(base)     (NV_BACKKEY7_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY6 - Backdoor Comparison Key 6.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY6 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY6(base)     (NV_BACKKEY6_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY5 - Backdoor Comparison Key 5.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY5 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY5(base)     (NV_BACKKEY5_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY4 - Backdoor Comparison Key 4.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY4 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY4(base)     (NV_BACKKEY4_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT3 register
+ */
+/*@{*/
+#define NV_RD_FPROT3(base)       (NV_FPROT3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT2 register
+ */
+/*@{*/
+#define NV_RD_FPROT2(base)       (NV_FPROT2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT1 register
+ */
+/*@{*/
+#define NV_RD_FPROT1(base)       (NV_FPROT1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT0 register
+ */
+/*@{*/
+#define NV_RD_FPROT0(base)       (NV_FPROT0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FSEC - Non-volatile Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FSEC - Non-volatile Flash Security Register (RO)
+ *
+ * Reset value: 0xFFU
+ *
+ * Allows the user to customize the operation of the MCU at boot time
+ */
+/*!
+ * @name Constants and macros for entire NV_FSEC register
+ */
+/*@{*/
+#define NV_RD_FSEC(base)         (NV_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FSEC bitfields
+ */
+
+/*!
+ * @name Register NV_FSEC, field SEC[1:0] (RO)
+ *
+ * Values:
+ * - 0b10 - MCU security status is unsecure
+ * - 0b11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_SEC field. */
+#define NV_RD_FSEC_SEC(base) ((NV_FSEC_REG(base) & NV_FSEC_SEC_MASK) >> NV_FSEC_SEC_SHIFT)
+#define NV_BRD_FSEC_SEC(base) (NV_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field FSLACC[3:2] (RO)
+ *
+ * Values:
+ * - 0b10 - Freescale factory access denied
+ * - 0b11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_FSLACC field. */
+#define NV_RD_FSEC_FSLACC(base) ((NV_FSEC_REG(base) & NV_FSEC_FSLACC_MASK) >> NV_FSEC_FSLACC_SHIFT)
+#define NV_BRD_FSEC_FSLACC(base) (NV_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field MEEN[5:4] (RO)
+ *
+ * Values:
+ * - 0b10 - Mass erase is disabled
+ * - 0b11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_MEEN field. */
+#define NV_RD_FSEC_MEEN(base) ((NV_FSEC_REG(base) & NV_FSEC_MEEN_MASK) >> NV_FSEC_MEEN_SHIFT)
+#define NV_BRD_FSEC_MEEN(base) (NV_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field KEYEN[7:6] (RO)
+ *
+ * Values:
+ * - 0b10 - Backdoor key access enabled
+ * - 0b11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_KEYEN field. */
+#define NV_RD_FSEC_KEYEN(base) ((NV_FSEC_REG(base) & NV_FSEC_KEYEN_MASK) >> NV_FSEC_KEYEN_SHIFT)
+#define NV_BRD_FSEC_KEYEN(base) (NV_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FOPT - Non-volatile Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FOPT - Non-volatile Flash Option Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FOPT register
+ */
+/*@{*/
+#define NV_RD_FOPT(base)         (NV_FOPT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FOPT bitfields
+ */
+
+/*!
+ * @name Register NV_FOPT, field LPBOOT[0] (RO)
+ *
+ * Values:
+ * - 0b0 - Low-power boot
+ * - 0b1 - Normal boot
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_LPBOOT field. */
+#define NV_RD_FOPT_LPBOOT(base) ((NV_FOPT_REG(base) & NV_FOPT_LPBOOT_MASK) >> NV_FOPT_LPBOOT_SHIFT)
+#define NV_BRD_FOPT_LPBOOT(base) (BITBAND_ACCESS8(&NV_FOPT_REG(base), NV_FOPT_LPBOOT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register NV_FOPT, field EZPORT_DIS[1] (RO)
+ *
+ * Values:
+ * - 0b0 - EzPort operation is disabled
+ * - 0b1 - EzPort operation is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_EZPORT_DIS field. */
+#define NV_RD_FOPT_EZPORT_DIS(base) ((NV_FOPT_REG(base) & NV_FOPT_EZPORT_DIS_MASK) >> NV_FOPT_EZPORT_DIS_SHIFT)
+#define NV_BRD_FOPT_EZPORT_DIS(base) (BITBAND_ACCESS8(&NV_FOPT_REG(base), NV_FOPT_EZPORT_DIS_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FEPROT - Non-volatile EERAM Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FEPROT - Non-volatile EERAM Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FEPROT register
+ */
+/*@{*/
+#define NV_RD_FEPROT(base)       (NV_FEPROT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FDPROT - Non-volatile D-Flash Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FDPROT - Non-volatile D-Flash Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FDPROT register
+ */
+/*@{*/
+#define NV_RD_FDPROT(base)       (NV_FDPROT_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 OSC
+ *
+ * Oscillator
+ *
+ * Registers defined in this header file:
+ * - OSC_CR - OSC Control Register
+ */
+
+#define OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */
+#define OSC_IDX (0U) /*!< Instance number for OSC. */
+
+/*******************************************************************************
+ * OSC_CR - OSC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief OSC_CR - OSC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * After OSC is enabled and starts generating the clocks, the configurations
+ * such as low power and frequency range, must not be changed.
+ */
+/*!
+ * @name Constants and macros for entire OSC_CR register
+ */
+/*@{*/
+#define OSC_RD_CR(base)          (OSC_CR_REG(base))
+#define OSC_WR_CR(base, value)   (OSC_CR_REG(base) = (value))
+#define OSC_RMW_CR(base, mask, value) (OSC_WR_CR(base, (OSC_RD_CR(base) & ~(mask)) | (value)))
+#define OSC_SET_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) |  (value)))
+#define OSC_CLR_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) & ~(value)))
+#define OSC_TOG_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual OSC_CR bitfields
+ */
+
+/*!
+ * @name Register OSC_CR, field SC16P[0] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 16 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC16P field. */
+#define OSC_RD_CR_SC16P(base) ((OSC_CR_REG(base) & OSC_CR_SC16P_MASK) >> OSC_CR_SC16P_SHIFT)
+#define OSC_BRD_CR_SC16P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT))
+
+/*! @brief Set the SC16P field to a new value. */
+#define OSC_WR_CR_SC16P(base, value) (OSC_RMW_CR(base, OSC_CR_SC16P_MASK, OSC_CR_SC16P(value)))
+#define OSC_BWR_CR_SC16P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC8P[1] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 8 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC8P field. */
+#define OSC_RD_CR_SC8P(base) ((OSC_CR_REG(base) & OSC_CR_SC8P_MASK) >> OSC_CR_SC8P_SHIFT)
+#define OSC_BRD_CR_SC8P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT))
+
+/*! @brief Set the SC8P field to a new value. */
+#define OSC_WR_CR_SC8P(base, value) (OSC_RMW_CR(base, OSC_CR_SC8P_MASK, OSC_CR_SC8P(value)))
+#define OSC_BWR_CR_SC8P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC4P[2] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 4 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC4P field. */
+#define OSC_RD_CR_SC4P(base) ((OSC_CR_REG(base) & OSC_CR_SC4P_MASK) >> OSC_CR_SC4P_SHIFT)
+#define OSC_BRD_CR_SC4P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT))
+
+/*! @brief Set the SC4P field to a new value. */
+#define OSC_WR_CR_SC4P(base, value) (OSC_RMW_CR(base, OSC_CR_SC4P_MASK, OSC_CR_SC4P(value)))
+#define OSC_BWR_CR_SC4P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC2P[3] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 2 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC2P field. */
+#define OSC_RD_CR_SC2P(base) ((OSC_CR_REG(base) & OSC_CR_SC2P_MASK) >> OSC_CR_SC2P_SHIFT)
+#define OSC_BRD_CR_SC2P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT))
+
+/*! @brief Set the SC2P field to a new value. */
+#define OSC_WR_CR_SC2P(base, value) (OSC_RMW_CR(base, OSC_CR_SC2P_MASK, OSC_CR_SC2P(value)))
+#define OSC_BWR_CR_SC2P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field EREFSTEN[5] (RW)
+ *
+ * Controls whether or not the external reference clock (OSCERCLK) remains
+ * enabled when MCU enters Stop mode.
+ *
+ * Values:
+ * - 0b0 - External reference clock is disabled in Stop mode.
+ * - 0b1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
+ *     before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_EREFSTEN field. */
+#define OSC_RD_CR_EREFSTEN(base) ((OSC_CR_REG(base) & OSC_CR_EREFSTEN_MASK) >> OSC_CR_EREFSTEN_SHIFT)
+#define OSC_BRD_CR_EREFSTEN(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT))
+
+/*! @brief Set the EREFSTEN field to a new value. */
+#define OSC_WR_CR_EREFSTEN(base, value) (OSC_RMW_CR(base, OSC_CR_EREFSTEN_MASK, OSC_CR_EREFSTEN(value)))
+#define OSC_BWR_CR_EREFSTEN(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field ERCLKEN[7] (RW)
+ *
+ * Enables external reference clock (OSCERCLK).
+ *
+ * Values:
+ * - 0b0 - External reference clock is inactive.
+ * - 0b1 - External reference clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_ERCLKEN field. */
+#define OSC_RD_CR_ERCLKEN(base) ((OSC_CR_REG(base) & OSC_CR_ERCLKEN_MASK) >> OSC_CR_ERCLKEN_SHIFT)
+#define OSC_BRD_CR_ERCLKEN(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT))
+
+/*! @brief Set the ERCLKEN field to a new value. */
+#define OSC_WR_CR_ERCLKEN(base, value) (OSC_RMW_CR(base, OSC_CR_ERCLKEN_MASK, OSC_CR_ERCLKEN(value)))
+#define OSC_BWR_CR_ERCLKEN(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PDB
+ *
+ * Programmable Delay Block
+ *
+ * Registers defined in this header file:
+ * - PDB_SC - Status and Control register
+ * - PDB_MOD - Modulus register
+ * - PDB_CNT - Counter register
+ * - PDB_IDLY - Interrupt Delay register
+ * - PDB_C1 - Channel n Control register 1
+ * - PDB_S - Channel n Status register
+ * - PDB_DLY - Channel n Delay 0 register
+ * - PDB_INTC - DAC Interval Trigger n Control register
+ * - PDB_INT - DAC Interval n register
+ * - PDB_POEN - Pulse-Out n Enable register
+ * - PDB_PODLY - Pulse-Out n Delay register
+ */
+
+#define PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */
+#define PDB0_IDX (0U) /*!< Instance number for PDB0. */
+
+/*******************************************************************************
+ * PDB_SC - Status and Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_SC - Status and Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_SC register
+ */
+/*@{*/
+#define PDB_RD_SC(base)          (PDB_SC_REG(base))
+#define PDB_WR_SC(base, value)   (PDB_SC_REG(base) = (value))
+#define PDB_RMW_SC(base, mask, value) (PDB_WR_SC(base, (PDB_RD_SC(base) & ~(mask)) | (value)))
+#define PDB_SET_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) |  (value)))
+#define PDB_CLR_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) & ~(value)))
+#define PDB_TOG_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_SC bitfields
+ */
+
+/*!
+ * @name Register PDB_SC, field LDOK[0] (RW)
+ *
+ * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
+ * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
+ * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
+ * written to the LDOK field, the values in the buffers of above registers are
+ * not effective and the buffers cannot be written until the values in buffers are
+ * loaded into their internal registers. LDOK can be written only when PDBEN is
+ * set or it can be written at the same time with PDBEN being written to 1. It is
+ * automatically cleared when the values in buffers are loaded into the internal
+ * registers or the PDBEN is cleared. Writing 0 to it has no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_LDOK field. */
+#define PDB_RD_SC_LDOK(base) ((PDB_SC_REG(base) & PDB_SC_LDOK_MASK) >> PDB_SC_LDOK_SHIFT)
+#define PDB_BRD_SC_LDOK(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_LDOK_SHIFT))
+
+/*! @brief Set the LDOK field to a new value. */
+#define PDB_WR_SC_LDOK(base, value) (PDB_RMW_SC(base, PDB_SC_LDOK_MASK, PDB_SC_LDOK(value)))
+#define PDB_BWR_SC_LDOK(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_LDOK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field CONT[1] (RW)
+ *
+ * Enables the PDB operation in Continuous mode.
+ *
+ * Values:
+ * - 0b0 - PDB operation in One-Shot mode
+ * - 0b1 - PDB operation in Continuous mode
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_CONT field. */
+#define PDB_RD_SC_CONT(base) ((PDB_SC_REG(base) & PDB_SC_CONT_MASK) >> PDB_SC_CONT_SHIFT)
+#define PDB_BRD_SC_CONT(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_CONT_SHIFT))
+
+/*! @brief Set the CONT field to a new value. */
+#define PDB_WR_SC_CONT(base, value) (PDB_RMW_SC(base, PDB_SC_CONT_MASK, PDB_SC_CONT(value)))
+#define PDB_BWR_SC_CONT(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_CONT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field MULT[3:2] (RW)
+ *
+ * Selects the multiplication factor of the prescaler divider for the counter
+ * clock.
+ *
+ * Values:
+ * - 0b00 - Multiplication factor is 1.
+ * - 0b01 - Multiplication factor is 10.
+ * - 0b10 - Multiplication factor is 20.
+ * - 0b11 - Multiplication factor is 40.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_MULT field. */
+#define PDB_RD_SC_MULT(base) ((PDB_SC_REG(base) & PDB_SC_MULT_MASK) >> PDB_SC_MULT_SHIFT)
+#define PDB_BRD_SC_MULT(base) (PDB_RD_SC_MULT(base))
+
+/*! @brief Set the MULT field to a new value. */
+#define PDB_WR_SC_MULT(base, value) (PDB_RMW_SC(base, PDB_SC_MULT_MASK, PDB_SC_MULT(value)))
+#define PDB_BWR_SC_MULT(base, value) (PDB_WR_SC_MULT(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBIE[5] (RW)
+ *
+ * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
+ * generates a PDB interrupt.
+ *
+ * Values:
+ * - 0b0 - PDB interrupt disabled.
+ * - 0b1 - PDB interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBIE field. */
+#define PDB_RD_SC_PDBIE(base) ((PDB_SC_REG(base) & PDB_SC_PDBIE_MASK) >> PDB_SC_PDBIE_SHIFT)
+#define PDB_BRD_SC_PDBIE(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIE_SHIFT))
+
+/*! @brief Set the PDBIE field to a new value. */
+#define PDB_WR_SC_PDBIE(base, value) (PDB_RMW_SC(base, PDB_SC_PDBIE_MASK, PDB_SC_PDBIE(value)))
+#define PDB_BWR_SC_PDBIE(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBIF[6] (RW)
+ *
+ * This field is set when the counter value is equal to the IDLY register.
+ * Writing zero clears this field.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBIF field. */
+#define PDB_RD_SC_PDBIF(base) ((PDB_SC_REG(base) & PDB_SC_PDBIF_MASK) >> PDB_SC_PDBIF_SHIFT)
+#define PDB_BRD_SC_PDBIF(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIF_SHIFT))
+
+/*! @brief Set the PDBIF field to a new value. */
+#define PDB_WR_SC_PDBIF(base, value) (PDB_RMW_SC(base, PDB_SC_PDBIF_MASK, PDB_SC_PDBIF(value)))
+#define PDB_BWR_SC_PDBIF(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - PDB disabled. Counter is off.
+ * - 0b1 - PDB enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBEN field. */
+#define PDB_RD_SC_PDBEN(base) ((PDB_SC_REG(base) & PDB_SC_PDBEN_MASK) >> PDB_SC_PDBEN_SHIFT)
+#define PDB_BRD_SC_PDBEN(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEN_SHIFT))
+
+/*! @brief Set the PDBEN field to a new value. */
+#define PDB_WR_SC_PDBEN(base, value) (PDB_RMW_SC(base, PDB_SC_PDBEN_MASK, PDB_SC_PDBEN(value)))
+#define PDB_BWR_SC_PDBEN(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field TRGSEL[11:8] (RW)
+ *
+ * Selects the trigger input source for the PDB. The trigger input source can be
+ * internal or external (EXTRG pin), or the software trigger. Refer to chip
+ * configuration details for the actual PDB input trigger connections.
+ *
+ * Values:
+ * - 0b0000 - Trigger-In 0 is selected.
+ * - 0b0001 - Trigger-In 1 is selected.
+ * - 0b0010 - Trigger-In 2 is selected.
+ * - 0b0011 - Trigger-In 3 is selected.
+ * - 0b0100 - Trigger-In 4 is selected.
+ * - 0b0101 - Trigger-In 5 is selected.
+ * - 0b0110 - Trigger-In 6 is selected.
+ * - 0b0111 - Trigger-In 7 is selected.
+ * - 0b1000 - Trigger-In 8 is selected.
+ * - 0b1001 - Trigger-In 9 is selected.
+ * - 0b1010 - Trigger-In 10 is selected.
+ * - 0b1011 - Trigger-In 11 is selected.
+ * - 0b1100 - Trigger-In 12 is selected.
+ * - 0b1101 - Trigger-In 13 is selected.
+ * - 0b1110 - Trigger-In 14 is selected.
+ * - 0b1111 - Software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_TRGSEL field. */
+#define PDB_RD_SC_TRGSEL(base) ((PDB_SC_REG(base) & PDB_SC_TRGSEL_MASK) >> PDB_SC_TRGSEL_SHIFT)
+#define PDB_BRD_SC_TRGSEL(base) (PDB_RD_SC_TRGSEL(base))
+
+/*! @brief Set the TRGSEL field to a new value. */
+#define PDB_WR_SC_TRGSEL(base, value) (PDB_RMW_SC(base, PDB_SC_TRGSEL_MASK, PDB_SC_TRGSEL(value)))
+#define PDB_BWR_SC_TRGSEL(base, value) (PDB_WR_SC_TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PRESCALER[14:12] (RW)
+ *
+ * Values:
+ * - 0b000 - Counting uses the peripheral clock divided by multiplication factor
+ *     selected by MULT.
+ * - 0b001 - Counting uses the peripheral clock divided by twice of the
+ *     multiplication factor selected by MULT.
+ * - 0b010 - Counting uses the peripheral clock divided by four times of the
+ *     multiplication factor selected by MULT.
+ * - 0b011 - Counting uses the peripheral clock divided by eight times of the
+ *     multiplication factor selected by MULT.
+ * - 0b100 - Counting uses the peripheral clock divided by 16 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b101 - Counting uses the peripheral clock divided by 32 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b110 - Counting uses the peripheral clock divided by 64 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b111 - Counting uses the peripheral clock divided by 128 times of the
+ *     multiplication factor selected by MULT.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PRESCALER field. */
+#define PDB_RD_SC_PRESCALER(base) ((PDB_SC_REG(base) & PDB_SC_PRESCALER_MASK) >> PDB_SC_PRESCALER_SHIFT)
+#define PDB_BRD_SC_PRESCALER(base) (PDB_RD_SC_PRESCALER(base))
+
+/*! @brief Set the PRESCALER field to a new value. */
+#define PDB_WR_SC_PRESCALER(base, value) (PDB_RMW_SC(base, PDB_SC_PRESCALER_MASK, PDB_SC_PRESCALER(value)))
+#define PDB_BWR_SC_PRESCALER(base, value) (PDB_WR_SC_PRESCALER(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field DMAEN[15] (RW)
+ *
+ * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
+ * interrupt.
+ *
+ * Values:
+ * - 0b0 - DMA disabled.
+ * - 0b1 - DMA enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_DMAEN field. */
+#define PDB_RD_SC_DMAEN(base) ((PDB_SC_REG(base) & PDB_SC_DMAEN_MASK) >> PDB_SC_DMAEN_SHIFT)
+#define PDB_BRD_SC_DMAEN(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define PDB_WR_SC_DMAEN(base, value) (PDB_RMW_SC(base, PDB_SC_DMAEN_MASK, PDB_SC_DMAEN(value)))
+#define PDB_BWR_SC_DMAEN(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field SWTRIG[16] (WORZ)
+ *
+ * When PDB is enabled and the software trigger is selected as the trigger input
+ * source, writing 1 to this field resets and restarts the counter. Writing 0 to
+ * this field has no effect. Reading this field results 0.
+ */
+/*@{*/
+/*! @brief Set the SWTRIG field to a new value. */
+#define PDB_WR_SC_SWTRIG(base, value) (PDB_RMW_SC(base, PDB_SC_SWTRIG_MASK, PDB_SC_SWTRIG(value)))
+#define PDB_BWR_SC_SWTRIG(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_SWTRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBEIE[17] (RW)
+ *
+ * Enables the PDB sequence error interrupt. When this field is set, any of the
+ * PDB channel sequence error flags generates a PDB sequence error interrupt.
+ *
+ * Values:
+ * - 0b0 - PDB sequence error interrupt disabled.
+ * - 0b1 - PDB sequence error interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBEIE field. */
+#define PDB_RD_SC_PDBEIE(base) ((PDB_SC_REG(base) & PDB_SC_PDBEIE_MASK) >> PDB_SC_PDBEIE_SHIFT)
+#define PDB_BRD_SC_PDBEIE(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEIE_SHIFT))
+
+/*! @brief Set the PDBEIE field to a new value. */
+#define PDB_WR_SC_PDBEIE(base, value) (PDB_RMW_SC(base, PDB_SC_PDBEIE_MASK, PDB_SC_PDBEIE(value)))
+#define PDB_BWR_SC_PDBEIE(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field LDMOD[19:18] (RW)
+ *
+ * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
+ * after 1 is written to LDOK.
+ *
+ * Values:
+ * - 0b00 - The internal registers are loaded with the values from their buffers
+ *     immediately after 1 is written to LDOK.
+ * - 0b01 - The internal registers are loaded with the values from their buffers
+ *     when the PDB counter reaches the MOD register value after 1 is written to
+ *     LDOK.
+ * - 0b10 - The internal registers are loaded with the values from their buffers
+ *     when a trigger input event is detected after 1 is written to LDOK.
+ * - 0b11 - The internal registers are loaded with the values from their buffers
+ *     when either the PDB counter reaches the MOD register value or a trigger
+ *     input event is detected, after 1 is written to LDOK.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_LDMOD field. */
+#define PDB_RD_SC_LDMOD(base) ((PDB_SC_REG(base) & PDB_SC_LDMOD_MASK) >> PDB_SC_LDMOD_SHIFT)
+#define PDB_BRD_SC_LDMOD(base) (PDB_RD_SC_LDMOD(base))
+
+/*! @brief Set the LDMOD field to a new value. */
+#define PDB_WR_SC_LDMOD(base, value) (PDB_RMW_SC(base, PDB_SC_LDMOD_MASK, PDB_SC_LDMOD(value)))
+#define PDB_BWR_SC_LDMOD(base, value) (PDB_WR_SC_LDMOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_MOD - Modulus register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_MOD - Modulus register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+/*!
+ * @name Constants and macros for entire PDB_MOD register
+ */
+/*@{*/
+#define PDB_RD_MOD(base)         (PDB_MOD_REG(base))
+#define PDB_WR_MOD(base, value)  (PDB_MOD_REG(base) = (value))
+#define PDB_RMW_MOD(base, mask, value) (PDB_WR_MOD(base, (PDB_RD_MOD(base) & ~(mask)) | (value)))
+#define PDB_SET_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) |  (value)))
+#define PDB_CLR_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) & ~(value)))
+#define PDB_TOG_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_MOD bitfields
+ */
+
+/*!
+ * @name Register PDB_MOD, field MOD[15:0] (RW)
+ *
+ * Specifies the period of the counter. When the counter reaches this value, it
+ * will be reset back to zero. If the PDB is in Continuous mode, the count begins
+ * anew. Reading this field returns the value of the internal register that is
+ * effective for the current cycle of PDB.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_MOD_MOD field. */
+#define PDB_RD_MOD_MOD(base) ((PDB_MOD_REG(base) & PDB_MOD_MOD_MASK) >> PDB_MOD_MOD_SHIFT)
+#define PDB_BRD_MOD_MOD(base) (PDB_RD_MOD_MOD(base))
+
+/*! @brief Set the MOD field to a new value. */
+#define PDB_WR_MOD_MOD(base, value) (PDB_RMW_MOD(base, PDB_MOD_MOD_MASK, PDB_MOD_MOD(value)))
+#define PDB_BWR_MOD_MOD(base, value) (PDB_WR_MOD_MOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_CNT - Counter register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_CNT - Counter register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_CNT register
+ */
+/*@{*/
+#define PDB_RD_CNT(base)         (PDB_CNT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_CNT bitfields
+ */
+
+/*!
+ * @name Register PDB_CNT, field CNT[15:0] (RO)
+ *
+ * Contains the current value of the counter.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_CNT_CNT field. */
+#define PDB_RD_CNT_CNT(base) ((PDB_CNT_REG(base) & PDB_CNT_CNT_MASK) >> PDB_CNT_CNT_SHIFT)
+#define PDB_BRD_CNT_CNT(base) (PDB_RD_CNT_CNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_IDLY - Interrupt Delay register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_IDLY - Interrupt Delay register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+/*!
+ * @name Constants and macros for entire PDB_IDLY register
+ */
+/*@{*/
+#define PDB_RD_IDLY(base)        (PDB_IDLY_REG(base))
+#define PDB_WR_IDLY(base, value) (PDB_IDLY_REG(base) = (value))
+#define PDB_RMW_IDLY(base, mask, value) (PDB_WR_IDLY(base, (PDB_RD_IDLY(base) & ~(mask)) | (value)))
+#define PDB_SET_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) |  (value)))
+#define PDB_CLR_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) & ~(value)))
+#define PDB_TOG_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_IDLY bitfields
+ */
+
+/*!
+ * @name Register PDB_IDLY, field IDLY[15:0] (RW)
+ *
+ * Specifies the delay value to schedule the PDB interrupt. It can be used to
+ * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
+ * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
+ * this field returns the value of internal register that is effective for the
+ * current cycle of the PDB.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_IDLY_IDLY field. */
+#define PDB_RD_IDLY_IDLY(base) ((PDB_IDLY_REG(base) & PDB_IDLY_IDLY_MASK) >> PDB_IDLY_IDLY_SHIFT)
+#define PDB_BRD_IDLY_IDLY(base) (PDB_RD_IDLY_IDLY(base))
+
+/*! @brief Set the IDLY field to a new value. */
+#define PDB_WR_IDLY_IDLY(base, value) (PDB_RMW_IDLY(base, PDB_IDLY_IDLY_MASK, PDB_IDLY_IDLY(value)))
+#define PDB_BWR_IDLY_IDLY(base, value) (PDB_WR_IDLY_IDLY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_C1 - Channel n Control register 1
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_C1 - Channel n Control register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PDB channel has one control register, CHnC1. The bits in this register
+ * control the functionality of each PDB channel operation.
+ */
+/*!
+ * @name Constants and macros for entire PDB_C1 register
+ */
+/*@{*/
+#define PDB_RD_C1(base, index)   (PDB_C1_REG(base, index))
+#define PDB_WR_C1(base, index, value) (PDB_C1_REG(base, index) = (value))
+#define PDB_RMW_C1(base, index, mask, value) (PDB_WR_C1(base, index, (PDB_RD_C1(base, index) & ~(mask)) | (value)))
+#define PDB_SET_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) |  (value)))
+#define PDB_CLR_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) & ~(value)))
+#define PDB_TOG_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_C1 bitfields
+ */
+
+/*!
+ * @name Register PDB_C1, field EN[7:0] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
+ * bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger disabled.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_EN field. */
+#define PDB_RD_C1_EN(base, index) ((PDB_C1_REG(base, index) & PDB_C1_EN_MASK) >> PDB_C1_EN_SHIFT)
+#define PDB_BRD_C1_EN(base, index) (PDB_RD_C1_EN(base, index))
+
+/*! @brief Set the EN field to a new value. */
+#define PDB_WR_C1_EN(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_EN_MASK, PDB_C1_EN(value)))
+#define PDB_BWR_C1_EN(base, index, value) (PDB_WR_C1_EN(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_C1, field TOS[15:8] (RW)
+ *
+ * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
+ * implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger is in bypassed mode.
+ *     The pre-trigger asserts one peripheral clock cycle after a rising edge is
+ *     detected on selected trigger input source or software trigger is selected
+ *     and SWTRIG is written with 1.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger asserts when the
+ *     counter reaches the channel delay register and one peripheral clock cycle after
+ *     a rising edge is detected on selected trigger input source or software
+ *     trigger is selected and SETRIG is written with 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_TOS field. */
+#define PDB_RD_C1_TOS(base, index) ((PDB_C1_REG(base, index) & PDB_C1_TOS_MASK) >> PDB_C1_TOS_SHIFT)
+#define PDB_BRD_C1_TOS(base, index) (PDB_RD_C1_TOS(base, index))
+
+/*! @brief Set the TOS field to a new value. */
+#define PDB_WR_C1_TOS(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_TOS_MASK, PDB_C1_TOS(value)))
+#define PDB_BWR_C1_TOS(base, index, value) (PDB_WR_C1_TOS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_C1, field BB[23:16] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
+ * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
+ * enables the ADC conversions complete to trigger the next PDB channel
+ * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
+ * set of configuration and results registers. Application code must only enable
+ * the back-to-back operation of the PDB pre-triggers at the leading of the
+ * back-to-back connection chain.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger back-to-back operation
+ *     disabled.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger back-to-back operation
+ *     enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_BB field. */
+#define PDB_RD_C1_BB(base, index) ((PDB_C1_REG(base, index) & PDB_C1_BB_MASK) >> PDB_C1_BB_SHIFT)
+#define PDB_BRD_C1_BB(base, index) (PDB_RD_C1_BB(base, index))
+
+/*! @brief Set the BB field to a new value. */
+#define PDB_WR_C1_BB(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_BB_MASK, PDB_C1_BB(value)))
+#define PDB_BWR_C1_BB(base, index, value) (PDB_WR_C1_BB(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_S - Channel n Status register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_S - Channel n Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_S register
+ */
+/*@{*/
+#define PDB_RD_S(base, index)    (PDB_S_REG(base, index))
+#define PDB_WR_S(base, index, value) (PDB_S_REG(base, index) = (value))
+#define PDB_RMW_S(base, index, mask, value) (PDB_WR_S(base, index, (PDB_RD_S(base, index) & ~(mask)) | (value)))
+#define PDB_SET_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) |  (value)))
+#define PDB_CLR_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) & ~(value)))
+#define PDB_TOG_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_S bitfields
+ */
+
+/*!
+ * @name Register PDB_S, field ERR[7:0] (RW)
+ *
+ * Only the lower M bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - Sequence error not detected on PDB channel's corresponding
+ *     pre-trigger.
+ * - 0b00000001 - Sequence error detected on PDB channel's corresponding
+ *     pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from
+ *     PDB channel n. When one conversion, which is triggered by one of the
+ *     pre-triggers from PDB channel n, is in progress, new trigger from PDB
+ *     channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is
+ *     set. Writing 0's to clear the sequence error flags.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_S_ERR field. */
+#define PDB_RD_S_ERR(base, index) ((PDB_S_REG(base, index) & PDB_S_ERR_MASK) >> PDB_S_ERR_SHIFT)
+#define PDB_BRD_S_ERR(base, index) (PDB_RD_S_ERR(base, index))
+
+/*! @brief Set the ERR field to a new value. */
+#define PDB_WR_S_ERR(base, index, value) (PDB_RMW_S(base, index, PDB_S_ERR_MASK, PDB_S_ERR(value)))
+#define PDB_BWR_S_ERR(base, index, value) (PDB_WR_S_ERR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_S, field CF[23:16] (RW)
+ *
+ * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
+ * clear these bits.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_S_CF field. */
+#define PDB_RD_S_CF(base, index) ((PDB_S_REG(base, index) & PDB_S_CF_MASK) >> PDB_S_CF_SHIFT)
+#define PDB_BRD_S_CF(base, index) (PDB_RD_S_CF(base, index))
+
+/*! @brief Set the CF field to a new value. */
+#define PDB_WR_S_CF(base, index, value) (PDB_RMW_S(base, index, PDB_S_CF_MASK, PDB_S_CF(value)))
+#define PDB_BWR_S_CF(base, index, value) (PDB_WR_S_CF(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_DLY - Channel n Delay 0 register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_DLY - Channel n Delay 0 register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_DLY register
+ */
+/*@{*/
+#define PDB_RD_DLY(base, index, index2) (PDB_DLY_REG(base, index, index2))
+#define PDB_WR_DLY(base, index, index2, value) (PDB_DLY_REG(base, index, index2) = (value))
+#define PDB_RMW_DLY(base, index, index2, mask, value) (PDB_WR_DLY(base, index, index2, (PDB_RD_DLY(base, index, index2) & ~(mask)) | (value)))
+#define PDB_SET_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) |  (value)))
+#define PDB_CLR_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) & ~(value)))
+#define PDB_TOG_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_DLY bitfields
+ */
+
+/*!
+ * @name Register PDB_DLY, field DLY[15:0] (RW)
+ *
+ * Specifies the delay value for the channel's corresponding pre-trigger. The
+ * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
+ * the value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_DLY_DLY field. */
+#define PDB_RD_DLY_DLY(base, index, index2) ((PDB_DLY_REG(base, index, index2) & PDB_DLY_DLY_MASK) >> PDB_DLY_DLY_SHIFT)
+#define PDB_BRD_DLY_DLY(base, index, index2) (PDB_RD_DLY_DLY(base, index, index2))
+
+/*! @brief Set the DLY field to a new value. */
+#define PDB_WR_DLY_DLY(base, index, index2, value) (PDB_RMW_DLY(base, index, index2, PDB_DLY_DLY_MASK, PDB_DLY_DLY(value)))
+#define PDB_BWR_DLY_DLY(base, index, index2, value) (PDB_WR_DLY_DLY(base, index, index2, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_INTC - DAC Interval Trigger n Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_INTC - DAC Interval Trigger n Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_INTC register
+ */
+/*@{*/
+#define PDB_RD_INTC(base, index) (PDB_INTC_REG(base, index))
+#define PDB_WR_INTC(base, index, value) (PDB_INTC_REG(base, index) = (value))
+#define PDB_RMW_INTC(base, index, mask, value) (PDB_WR_INTC(base, index, (PDB_RD_INTC(base, index) & ~(mask)) | (value)))
+#define PDB_SET_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) |  (value)))
+#define PDB_CLR_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) & ~(value)))
+#define PDB_TOG_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_INTC bitfields
+ */
+
+/*!
+ * @name Register PDB_INTC, field TOE[0] (RW)
+ *
+ * This bit enables the DAC interval trigger.
+ *
+ * Values:
+ * - 0b0 - DAC interval trigger disabled.
+ * - 0b1 - DAC interval trigger enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INTC_TOE field. */
+#define PDB_RD_INTC_TOE(base, index) ((PDB_INTC_REG(base, index) & PDB_INTC_TOE_MASK) >> PDB_INTC_TOE_SHIFT)
+#define PDB_BRD_INTC_TOE(base, index) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_TOE_SHIFT))
+
+/*! @brief Set the TOE field to a new value. */
+#define PDB_WR_INTC_TOE(base, index, value) (PDB_RMW_INTC(base, index, PDB_INTC_TOE_MASK, PDB_INTC_TOE(value)))
+#define PDB_BWR_INTC_TOE(base, index, value) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_TOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_INTC, field EXT[1] (RW)
+ *
+ * Enables the external trigger for DAC interval counter.
+ *
+ * Values:
+ * - 0b0 - DAC external trigger input disabled. DAC interval counter is reset
+ *     and counting starts when a rising edge is detected on selected trigger input
+ *     source or software trigger is selected and SWTRIG is written with 1.
+ * - 0b1 - DAC external trigger input enabled. DAC interval counter is bypassed
+ *     and DAC external trigger input triggers the DAC interval trigger.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INTC_EXT field. */
+#define PDB_RD_INTC_EXT(base, index) ((PDB_INTC_REG(base, index) & PDB_INTC_EXT_MASK) >> PDB_INTC_EXT_SHIFT)
+#define PDB_BRD_INTC_EXT(base, index) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_EXT_SHIFT))
+
+/*! @brief Set the EXT field to a new value. */
+#define PDB_WR_INTC_EXT(base, index, value) (PDB_RMW_INTC(base, index, PDB_INTC_EXT_MASK, PDB_INTC_EXT(value)))
+#define PDB_BWR_INTC_EXT(base, index, value) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_EXT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_INT - DAC Interval n register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_INT - DAC Interval n register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_INT register
+ */
+/*@{*/
+#define PDB_RD_INT(base, index)  (PDB_INT_REG(base, index))
+#define PDB_WR_INT(base, index, value) (PDB_INT_REG(base, index) = (value))
+#define PDB_RMW_INT(base, index, mask, value) (PDB_WR_INT(base, index, (PDB_RD_INT(base, index) & ~(mask)) | (value)))
+#define PDB_SET_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) |  (value)))
+#define PDB_CLR_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) & ~(value)))
+#define PDB_TOG_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_INT bitfields
+ */
+
+/*!
+ * @name Register PDB_INT, field INT[15:0] (RW)
+ *
+ * Specifies the interval value for DAC interval trigger. DAC interval trigger
+ * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
+ * Reading this field returns the value of internal register that is effective
+ * for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INT_INT field. */
+#define PDB_RD_INT_INT(base, index) ((PDB_INT_REG(base, index) & PDB_INT_INT_MASK) >> PDB_INT_INT_SHIFT)
+#define PDB_BRD_INT_INT(base, index) (PDB_RD_INT_INT(base, index))
+
+/*! @brief Set the INT field to a new value. */
+#define PDB_WR_INT_INT(base, index, value) (PDB_RMW_INT(base, index, PDB_INT_INT_MASK, PDB_INT_INT(value)))
+#define PDB_BWR_INT_INT(base, index, value) (PDB_WR_INT_INT(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_POEN - Pulse-Out n Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_POEN - Pulse-Out n Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_POEN register
+ */
+/*@{*/
+#define PDB_RD_POEN(base)        (PDB_POEN_REG(base))
+#define PDB_WR_POEN(base, value) (PDB_POEN_REG(base) = (value))
+#define PDB_RMW_POEN(base, mask, value) (PDB_WR_POEN(base, (PDB_RD_POEN(base) & ~(mask)) | (value)))
+#define PDB_SET_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) |  (value)))
+#define PDB_CLR_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) & ~(value)))
+#define PDB_TOG_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_POEN bitfields
+ */
+
+/*!
+ * @name Register PDB_POEN, field POEN[7:0] (RW)
+ *
+ * Enables the pulse output. Only lower Y bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB Pulse-Out disabled
+ * - 0b00000001 - PDB Pulse-Out enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_POEN_POEN field. */
+#define PDB_RD_POEN_POEN(base) ((PDB_POEN_REG(base) & PDB_POEN_POEN_MASK) >> PDB_POEN_POEN_SHIFT)
+#define PDB_BRD_POEN_POEN(base) (PDB_RD_POEN_POEN(base))
+
+/*! @brief Set the POEN field to a new value. */
+#define PDB_WR_POEN_POEN(base, value) (PDB_RMW_POEN(base, PDB_POEN_POEN_MASK, PDB_POEN_POEN(value)))
+#define PDB_BWR_POEN_POEN(base, value) (PDB_WR_POEN_POEN(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_PODLY - Pulse-Out n Delay register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_PODLY - Pulse-Out n Delay register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_PODLY register
+ */
+/*@{*/
+#define PDB_RD_PODLY(base, index) (PDB_PODLY_REG(base, index))
+#define PDB_WR_PODLY(base, index, value) (PDB_PODLY_REG(base, index) = (value))
+#define PDB_RMW_PODLY(base, index, mask, value) (PDB_WR_PODLY(base, index, (PDB_RD_PODLY(base, index) & ~(mask)) | (value)))
+#define PDB_SET_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) |  (value)))
+#define PDB_CLR_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) & ~(value)))
+#define PDB_TOG_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_PODLY bitfields
+ */
+
+/*!
+ * @name Register PDB_PODLY, field DLY2[15:0] (RW)
+ *
+ * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
+ * low when the PDB counter is equal to the DLY2. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_PODLY_DLY2 field. */
+#define PDB_RD_PODLY_DLY2(base, index) ((PDB_PODLY_REG(base, index) & PDB_PODLY_DLY2_MASK) >> PDB_PODLY_DLY2_SHIFT)
+#define PDB_BRD_PODLY_DLY2(base, index) (PDB_RD_PODLY_DLY2(base, index))
+
+/*! @brief Set the DLY2 field to a new value. */
+#define PDB_WR_PODLY_DLY2(base, index, value) (PDB_RMW_PODLY(base, index, PDB_PODLY_DLY2_MASK, PDB_PODLY_DLY2(value)))
+#define PDB_BWR_PODLY_DLY2(base, index, value) (PDB_WR_PODLY_DLY2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_PODLY, field DLY1[31:16] (RW)
+ *
+ * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
+ * high when the PDB counter is equal to the DLY1. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_PODLY_DLY1 field. */
+#define PDB_RD_PODLY_DLY1(base, index) ((PDB_PODLY_REG(base, index) & PDB_PODLY_DLY1_MASK) >> PDB_PODLY_DLY1_SHIFT)
+#define PDB_BRD_PODLY_DLY1(base, index) (PDB_RD_PODLY_DLY1(base, index))
+
+/*! @brief Set the DLY1 field to a new value. */
+#define PDB_WR_PODLY_DLY1(base, index, value) (PDB_RMW_PODLY(base, index, PDB_PODLY_DLY1_MASK, PDB_PODLY_DLY1(value)))
+#define PDB_BWR_PODLY_DLY1(base, index, value) (PDB_WR_PODLY_DLY1(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 PIT
+ *
+ * Periodic Interrupt Timer
+ *
+ * Registers defined in this header file:
+ * - PIT_MCR - PIT Module Control Register
+ * - PIT_LDVAL - Timer Load Value Register
+ * - PIT_CVAL - Current Timer Value Register
+ * - PIT_TCTRL - Timer Control Register
+ * - PIT_TFLG - Timer Flag Register
+ */
+
+#define PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
+#define PIT_IDX (0U) /*!< Instance number for PIT. */
+
+/*******************************************************************************
+ * PIT_MCR - PIT Module Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_MCR - PIT Module Control Register (RW)
+ *
+ * Reset value: 0x00000006U
+ *
+ * This register enables or disables the PIT timer clocks and controls the
+ * timers when the PIT enters the Debug mode.
+ */
+/*!
+ * @name Constants and macros for entire PIT_MCR register
+ */
+/*@{*/
+#define PIT_RD_MCR(base)         (PIT_MCR_REG(base))
+#define PIT_WR_MCR(base, value)  (PIT_MCR_REG(base) = (value))
+#define PIT_RMW_MCR(base, mask, value) (PIT_WR_MCR(base, (PIT_RD_MCR(base) & ~(mask)) | (value)))
+#define PIT_SET_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) |  (value)))
+#define PIT_CLR_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) & ~(value)))
+#define PIT_TOG_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_MCR bitfields
+ */
+
+/*!
+ * @name Register PIT_MCR, field FRZ[0] (RW)
+ *
+ * Allows the timers to be stopped when the device enters the Debug mode.
+ *
+ * Values:
+ * - 0b0 - Timers continue to run in Debug mode.
+ * - 0b1 - Timers are stopped in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_FRZ field. */
+#define PIT_RD_MCR_FRZ(base) ((PIT_MCR_REG(base) & PIT_MCR_FRZ_MASK) >> PIT_MCR_FRZ_SHIFT)
+#define PIT_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define PIT_WR_MCR_FRZ(base, value) (PIT_RMW_MCR(base, PIT_MCR_FRZ_MASK, PIT_MCR_FRZ(value)))
+#define PIT_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_MCR, field MDIS[1] (RW)
+ *
+ * Disables the standard timers. This field must be enabled before any other
+ * setup is done.
+ *
+ * Values:
+ * - 0b0 - Clock for standard PIT timers is enabled.
+ * - 0b1 - Clock for standard PIT timers is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_MDIS field. */
+#define PIT_RD_MCR_MDIS(base) ((PIT_MCR_REG(base) & PIT_MCR_MDIS_MASK) >> PIT_MCR_MDIS_SHIFT)
+#define PIT_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define PIT_WR_MCR_MDIS(base, value) (PIT_RMW_MCR(base, PIT_MCR_MDIS_MASK, PIT_MCR_MDIS(value)))
+#define PIT_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_LDVAL - Timer Load Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_LDVAL - Timer Load Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers select the timeout period for the timer interrupts.
+ */
+/*!
+ * @name Constants and macros for entire PIT_LDVAL register
+ */
+/*@{*/
+#define PIT_RD_LDVAL(base, index) (PIT_LDVAL_REG(base, index))
+#define PIT_WR_LDVAL(base, index, value) (PIT_LDVAL_REG(base, index) = (value))
+#define PIT_RMW_LDVAL(base, index, mask, value) (PIT_WR_LDVAL(base, index, (PIT_RD_LDVAL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) |  (value)))
+#define PIT_CLR_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) & ~(value)))
+#define PIT_TOG_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_CVAL - Current Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_CVAL - Current Timer Value Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the current timer position.
+ */
+/*!
+ * @name Constants and macros for entire PIT_CVAL register
+ */
+/*@{*/
+#define PIT_RD_CVAL(base, index) (PIT_CVAL_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TCTRL - Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TCTRL - Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the control bits for each timer.
+ */
+/*!
+ * @name Constants and macros for entire PIT_TCTRL register
+ */
+/*@{*/
+#define PIT_RD_TCTRL(base, index) (PIT_TCTRL_REG(base, index))
+#define PIT_WR_TCTRL(base, index, value) (PIT_TCTRL_REG(base, index) = (value))
+#define PIT_RMW_TCTRL(base, index, mask, value) (PIT_WR_TCTRL(base, index, (PIT_RD_TCTRL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) |  (value)))
+#define PIT_CLR_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) & ~(value)))
+#define PIT_TOG_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TCTRL bitfields
+ */
+
+/*!
+ * @name Register PIT_TCTRL, field TEN[0] (RW)
+ *
+ * Enables or disables the timer.
+ *
+ * Values:
+ * - 0b0 - Timer n is disabled.
+ * - 0b1 - Timer n is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TEN field. */
+#define PIT_RD_TCTRL_TEN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TEN_MASK) >> PIT_TCTRL_TEN_SHIFT)
+#define PIT_BRD_TCTRL_TEN(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT))
+
+/*! @brief Set the TEN field to a new value. */
+#define PIT_WR_TCTRL_TEN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TEN_MASK, PIT_TCTRL_TEN(value)))
+#define PIT_BWR_TCTRL_TEN(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field TIE[1] (RW)
+ *
+ * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
+ * will immediately cause an interrupt event. To avoid this, the associated
+ * TFLGn[TIF] must be cleared first.
+ *
+ * Values:
+ * - 0b0 - Interrupt requests from Timer n are disabled.
+ * - 0b1 - Interrupt will be requested whenever TIF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TIE field. */
+#define PIT_RD_TCTRL_TIE(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TIE_MASK) >> PIT_TCTRL_TIE_SHIFT)
+#define PIT_BRD_TCTRL_TIE(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define PIT_WR_TCTRL_TIE(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TIE_MASK, PIT_TCTRL_TIE(value)))
+#define PIT_BWR_TCTRL_TIE(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field CHN[2] (RW)
+ *
+ * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
+ * Timer 0 cannot be chained.
+ *
+ * Values:
+ * - 0b0 - Timer is not chained.
+ * - 0b1 - Timer is chained to previous timer. For example, for Channel 2, if
+ *     this field is set, Timer 2 is chained to Timer 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_CHN field. */
+#define PIT_RD_TCTRL_CHN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_CHN_MASK) >> PIT_TCTRL_CHN_SHIFT)
+#define PIT_BRD_TCTRL_CHN(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT))
+
+/*! @brief Set the CHN field to a new value. */
+#define PIT_WR_TCTRL_CHN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_CHN_MASK, PIT_TCTRL_CHN(value)))
+#define PIT_BWR_TCTRL_CHN(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TFLG - Timer Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TFLG - Timer Flag Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers hold the PIT interrupt flags.
+ */
+/*!
+ * @name Constants and macros for entire PIT_TFLG register
+ */
+/*@{*/
+#define PIT_RD_TFLG(base, index) (PIT_TFLG_REG(base, index))
+#define PIT_WR_TFLG(base, index, value) (PIT_TFLG_REG(base, index) = (value))
+#define PIT_RMW_TFLG(base, index, mask, value) (PIT_WR_TFLG(base, index, (PIT_RD_TFLG(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) |  (value)))
+#define PIT_CLR_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) & ~(value)))
+#define PIT_TOG_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TFLG bitfields
+ */
+
+/*!
+ * @name Register PIT_TFLG, field TIF[0] (W1C)
+ *
+ * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
+ * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
+ * interrupt request.
+ *
+ * Values:
+ * - 0b0 - Timeout has not yet occurred.
+ * - 0b1 - Timeout has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TFLG_TIF field. */
+#define PIT_RD_TFLG_TIF(base, index) ((PIT_TFLG_REG(base, index) & PIT_TFLG_TIF_MASK) >> PIT_TFLG_TIF_SHIFT)
+#define PIT_BRD_TFLG_TIF(base, index) (BITBAND_ACCESS32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT))
+
+/*! @brief Set the TIF field to a new value. */
+#define PIT_WR_TFLG_TIF(base, index, value) (PIT_RMW_TFLG(base, index, PIT_TFLG_TIF_MASK, PIT_TFLG_TIF(value)))
+#define PIT_BWR_TFLG_TIF(base, index, value) (BITBAND_ACCESS32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PMC
+ *
+ * Power Management Controller
+ *
+ * Registers defined in this header file:
+ * - PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ * - PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ * - PMC_REGSC - Regulator Status And Control register
+ */
+
+#define PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
+#define PMC_IDX (0U) /*!< Instance number for PMC. */
+
+/*******************************************************************************
+ * PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
+ *
+ * Reset value: 0x10U
+ *
+ * This register contains status and control bits to support the low voltage
+ * detect function. This register should be written during the reset initialization
+ * program to set the desired controls even if the desired settings are the same
+ * as the reset settings. While the device is in the very low power or low
+ * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
+ * systems that must have LVD always on, configure the Power Mode Protection
+ * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
+ * low leakage modes from being enabled. See the device's data sheet for the
+ * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
+ * register's other bits are reset on Chip Reset Not VLLS. For more information
+ * about these reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC1 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC1(base)      (PMC_LVDSC1_REG(base))
+#define PMC_WR_LVDSC1(base, value) (PMC_LVDSC1_REG(base) = (value))
+#define PMC_RMW_LVDSC1(base, mask, value) (PMC_WR_LVDSC1(base, (PMC_RD_LVDSC1(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) |  (value)))
+#define PMC_CLR_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) & ~(value)))
+#define PMC_TOG_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC1 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
+ *
+ * Selects the LVD trip point voltage (V LVD ).
+ *
+ * Values:
+ * - 0b00 - Low trip point selected (V LVD = V LVDL )
+ * - 0b01 - High trip point selected (V LVD = V LVDH )
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
+#define PMC_RD_LVDSC1_LVDV(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDV_MASK) >> PMC_LVDSC1_LVDV_SHIFT)
+#define PMC_BRD_LVDSC1_LVDV(base) (PMC_RD_LVDSC1_LVDV(base))
+
+/*! @brief Set the LVDV field to a new value. */
+#define PMC_WR_LVDSC1_LVDV(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDV_MASK, PMC_LVDSC1_LVDV(value)))
+#define PMC_BWR_LVDSC1_LVDV(base, value) (PMC_WR_LVDSC1_LVDV(base, value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
+ *
+ * This write-once bit enables LVDF events to generate a hardware reset.
+ * Additional writes are ignored.
+ *
+ * Values:
+ * - 0b0 - LVDF does not generate hardware resets
+ * - 0b1 - Force an MCU reset when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
+#define PMC_RD_LVDSC1_LVDRE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDRE_MASK) >> PMC_LVDSC1_LVDRE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDRE(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT))
+
+/*! @brief Set the LVDRE field to a new value. */
+#define PMC_WR_LVDSC1_LVDRE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDRE_MASK, PMC_LVDSC1_LVDRE(value)))
+#define PMC_BWR_LVDSC1_LVDRE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVDF.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupt disabled (use polling)
+ * - 0b1 - Request a hardware interrupt when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
+#define PMC_RD_LVDSC1_LVDIE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDIE_MASK) >> PMC_LVDSC1_LVDIE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDIE(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT))
+
+/*! @brief Set the LVDIE field to a new value. */
+#define PMC_WR_LVDSC1_LVDIE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDIE_MASK, PMC_LVDSC1_LVDIE(value)))
+#define PMC_BWR_LVDSC1_LVDIE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage detection errors.
+ * Write 1 to clear LVDF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVDACK field to a new value. */
+#define PMC_WR_LVDSC1_LVDACK(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDACK_MASK, PMC_LVDSC1_LVDACK(value)))
+#define PMC_BWR_LVDSC1_LVDACK(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage detect event.
+ *
+ * Values:
+ * - 0b0 - Low-voltage event not detected
+ * - 0b1 - Low-voltage event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
+#define PMC_RD_LVDSC1_LVDF(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDF_MASK) >> PMC_LVDSC1_LVDF_SHIFT)
+#define PMC_BRD_LVDSC1_LVDF(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains status and control bits to support the low voltage
+ * warning function. While the device is in the very low power or low leakage modes,
+ * the LVD system is disabled regardless of LVDSC2 settings. See the device's
+ * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
+ * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
+ * register are reset on Chip Reset Not VLLS. For more information about these
+ * reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC2 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC2(base)      (PMC_LVDSC2_REG(base))
+#define PMC_WR_LVDSC2(base, value) (PMC_LVDSC2_REG(base) = (value))
+#define PMC_RMW_LVDSC2(base, mask, value) (PMC_WR_LVDSC2(base, (PMC_RD_LVDSC2(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) |  (value)))
+#define PMC_CLR_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) & ~(value)))
+#define PMC_TOG_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC2 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
+ *
+ * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
+ * depends on LVDSC1[LVDV].
+ *
+ * Values:
+ * - 0b00 - Low trip point selected (VLVW = VLVW1)
+ * - 0b01 - Mid 1 trip point selected (VLVW = VLVW2)
+ * - 0b10 - Mid 2 trip point selected (VLVW = VLVW3)
+ * - 0b11 - High trip point selected (VLVW = VLVW4)
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
+#define PMC_RD_LVDSC2_LVWV(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWV_MASK) >> PMC_LVDSC2_LVWV_SHIFT)
+#define PMC_BRD_LVDSC2_LVWV(base) (PMC_RD_LVDSC2_LVWV(base))
+
+/*! @brief Set the LVWV field to a new value. */
+#define PMC_WR_LVDSC2_LVWV(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWV_MASK, PMC_LVDSC2_LVWV(value)))
+#define PMC_BWR_LVDSC2_LVWV(base, value) (PMC_WR_LVDSC2_LVWV(base, value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVWF.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupt disabled (use polling)
+ * - 0b1 - Request a hardware interrupt when LVWF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
+#define PMC_RD_LVDSC2_LVWIE(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWIE_MASK) >> PMC_LVDSC2_LVWIE_SHIFT)
+#define PMC_BRD_LVDSC2_LVWIE(base) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT))
+
+/*! @brief Set the LVWIE field to a new value. */
+#define PMC_WR_LVDSC2_LVWIE(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWIE_MASK, PMC_LVDSC2_LVWIE(value)))
+#define PMC_BWR_LVDSC2_LVWIE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage warning errors.
+ * Write 1 to clear LVWF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVWACK field to a new value. */
+#define PMC_WR_LVDSC2_LVWACK(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWACK_MASK, PMC_LVDSC2_LVWACK(value)))
+#define PMC_BWR_LVDSC2_LVWACK(base, value) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage warning event. LVWF is
+ * set when VSupply transitions below the trip point, or after reset and VSupply is
+ * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
+ * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
+ * LVWACK first.
+ *
+ * Values:
+ * - 0b0 - Low-voltage warning event not detected
+ * - 0b1 - Low-voltage warning event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
+#define PMC_RD_LVDSC2_LVWF(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWF_MASK) >> PMC_LVDSC2_LVWF_SHIFT)
+#define PMC_BRD_LVDSC2_LVWF(base) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_REGSC - Regulator Status And Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_REGSC - Regulator Status And Control register (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * The PMC contains an internal voltage regulator. The voltage regulator design
+ * uses a bandgap reference that is also available through a buffer as input to
+ * certain internal peripherals, such as the CMP and ADC. The internal regulator
+ * provides a status bit (REGONS) indicating the regulator is in run regulation.
+ * This register is reset on Chip Reset Not VLLS and by reset types that trigger
+ * Chip Reset not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire PMC_REGSC register
+ */
+/*@{*/
+#define PMC_RD_REGSC(base)       (PMC_REGSC_REG(base))
+#define PMC_WR_REGSC(base, value) (PMC_REGSC_REG(base) = (value))
+#define PMC_RMW_REGSC(base, mask, value) (PMC_WR_REGSC(base, (PMC_RD_REGSC(base) & ~(mask)) | (value)))
+#define PMC_SET_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) |  (value)))
+#define PMC_CLR_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) & ~(value)))
+#define PMC_TOG_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_REGSC bitfields
+ */
+
+/*!
+ * @name Register PMC_REGSC, field BGBE[0] (RW)
+ *
+ * Enables the bandgap buffer.
+ *
+ * Values:
+ * - 0b0 - Bandgap buffer not enabled
+ * - 0b1 - Bandgap buffer enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGBE field. */
+#define PMC_RD_REGSC_BGBE(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGBE_MASK) >> PMC_REGSC_BGBE_SHIFT)
+#define PMC_BRD_REGSC_BGBE(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT))
+
+/*! @brief Set the BGBE field to a new value. */
+#define PMC_WR_REGSC_BGBE(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGBE_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGBE(value)))
+#define PMC_BWR_REGSC_BGBE(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field REGONS[2] (RO)
+ *
+ * This read-only field provides the current status of the internal voltage
+ * regulator.
+ *
+ * Values:
+ * - 0b0 - Regulator is in stop regulation or in transition to/from it
+ * - 0b1 - Regulator is in run regulation
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_REGONS field. */
+#define PMC_RD_REGSC_REGONS(base) ((PMC_REGSC_REG(base) & PMC_REGSC_REGONS_MASK) >> PMC_REGSC_REGONS_SHIFT)
+#define PMC_BRD_REGSC_REGONS(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_REGONS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field ACKISO[3] (W1C)
+ *
+ * Reading this field indicates whether certain peripherals and the I/O pads are
+ * in a latched state as a result of having been in a VLLS mode. Writing 1 to
+ * this field when it is set releases the I/O pads and certain peripherals to their
+ * normal run mode state. After recovering from a VLLS mode, user should restore
+ * chip configuration before clearing ACKISO. In particular, pin configuration
+ * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
+ * being falsely set when ACKISO is cleared.
+ *
+ * Values:
+ * - 0b0 - Peripherals and I/O pads are in normal run state.
+ * - 0b1 - Certain peripherals and I/O pads are in an isolated and latched state.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_ACKISO field. */
+#define PMC_RD_REGSC_ACKISO(base) ((PMC_REGSC_REG(base) & PMC_REGSC_ACKISO_MASK) >> PMC_REGSC_ACKISO_SHIFT)
+#define PMC_BRD_REGSC_ACKISO(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT))
+
+/*! @brief Set the ACKISO field to a new value. */
+#define PMC_WR_REGSC_ACKISO(base, value) (PMC_RMW_REGSC(base, PMC_REGSC_ACKISO_MASK, PMC_REGSC_ACKISO(value)))
+#define PMC_BWR_REGSC_ACKISO(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field BGEN[4] (RW)
+ *
+ * BGEN controls whether the bandgap is enabled in lower power modes of
+ * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
+ * reference in low power modes of operation, set BGEN to continue to enable the
+ * bandgap operation. When the bandgap voltage reference is not needed in low
+ * power modes, clear BGEN to avoid excess power consumption.
+ *
+ * Values:
+ * - 0b0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
+ * - 0b1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGEN field. */
+#define PMC_RD_REGSC_BGEN(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGEN_MASK) >> PMC_REGSC_BGEN_SHIFT)
+#define PMC_BRD_REGSC_BGEN(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT))
+
+/*! @brief Set the BGEN field to a new value. */
+#define PMC_WR_REGSC_BGEN(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGEN_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGEN(value)))
+#define PMC_BWR_REGSC_BGEN(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PORT
+ *
+ * Pin Control and Interrupts
+ *
+ * Registers defined in this header file:
+ * - PORT_PCR - Pin Control Register n
+ * - PORT_GPCLR - Global Pin Control Low Register
+ * - PORT_GPCHR - Global Pin Control High Register
+ * - PORT_ISFR - Interrupt Status Flag Register
+ * - PORT_DFER - Digital Filter Enable Register
+ * - PORT_DFCR - Digital Filter Clock Register
+ * - PORT_DFWR - Digital Filter Width Register
+ */
+
+#define PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
+#define PORTA_IDX (0U) /*!< Instance number for PORTA. */
+#define PORTB_IDX (1U) /*!< Instance number for PORTB. */
+#define PORTC_IDX (2U) /*!< Instance number for PORTC. */
+#define PORTD_IDX (3U) /*!< Instance number for PORTD. */
+#define PORTE_IDX (4U) /*!< Instance number for PORTE. */
+
+/*******************************************************************************
+ * PORT_PCR - Pin Control Register n
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_PCR - Pin Control Register n (RW)
+ *
+ * Reset value: 0x00000746U
+ *
+ * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
+ * this device. See the GPIO Configuration section for details on the available
+ * functions for each pin. Do not modify pin configuration registers associated
+ * with pins not available in your selected package. All unbonded pins not
+ * available in your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire PORT_PCR register
+ */
+/*@{*/
+#define PORT_RD_PCR(base, index) (PORT_PCR_REG(base, index))
+#define PORT_WR_PCR(base, index, value) (PORT_PCR_REG(base, index) = (value))
+#define PORT_RMW_PCR(base, index, mask, value) (PORT_WR_PCR(base, index, (PORT_RD_PCR(base, index) & ~(mask)) | (value)))
+#define PORT_SET_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) |  (value)))
+#define PORT_CLR_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) & ~(value)))
+#define PORT_TOG_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_PCR bitfields
+ */
+
+/*!
+ * @name Register PORT_PCR, field PS[0] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Internal pulldown resistor is enabled on the corresponding pin, if
+ *     the corresponding PE field is set.
+ * - 0b1 - Internal pullup resistor is enabled on the corresponding pin, if the
+ *     corresponding PE field is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PS field. */
+#define PORT_RD_PCR_PS(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PS_MASK) >> PORT_PCR_PS_SHIFT)
+#define PORT_BRD_PCR_PS(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT))
+
+/*! @brief Set the PS field to a new value. */
+#define PORT_WR_PCR_PS(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PS_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PS(value)))
+#define PORT_BWR_PCR_PS(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PE[1] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Internal pullup or pulldown resistor is not enabled on the
+ *     corresponding pin.
+ * - 0b1 - Internal pullup or pulldown resistor is enabled on the corresponding
+ *     pin, if the pin is configured as a digital input.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PE field. */
+#define PORT_RD_PCR_PE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PE_MASK) >> PORT_PCR_PE_SHIFT)
+#define PORT_BRD_PCR_PE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT))
+
+/*! @brief Set the PE field to a new value. */
+#define PORT_WR_PCR_PE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PE(value)))
+#define PORT_BWR_PCR_PE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field SRE[2] (RW)
+ *
+ * Slew rate configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Fast slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ * - 0b1 - Slow slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_SRE field. */
+#define PORT_RD_PCR_SRE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_SRE_MASK) >> PORT_PCR_SRE_SHIFT)
+#define PORT_BRD_PCR_SRE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT))
+
+/*! @brief Set the SRE field to a new value. */
+#define PORT_WR_PCR_SRE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_SRE(value)))
+#define PORT_BWR_PCR_SRE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PFE[4] (RW)
+ *
+ * Passive filter configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Passive input filter is disabled on the corresponding pin.
+ * - 0b1 - Passive input filter is enabled on the corresponding pin, if the pin
+ *     is configured as a digital input. Refer to the device data sheet for
+ *     filter characteristics.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PFE field. */
+#define PORT_RD_PCR_PFE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PFE_MASK) >> PORT_PCR_PFE_SHIFT)
+#define PORT_BRD_PCR_PFE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT))
+
+/*! @brief Set the PFE field to a new value. */
+#define PORT_WR_PCR_PFE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PFE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PFE(value)))
+#define PORT_BWR_PCR_PFE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ODE[5] (RW)
+ *
+ * Open drain configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Open drain output is disabled on the corresponding pin.
+ * - 0b1 - Open drain output is enabled on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ODE field. */
+#define PORT_RD_PCR_ODE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ODE_MASK) >> PORT_PCR_ODE_SHIFT)
+#define PORT_BRD_PCR_ODE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ODE_SHIFT))
+
+/*! @brief Set the ODE field to a new value. */
+#define PORT_WR_PCR_ODE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_ODE(value)))
+#define PORT_BWR_PCR_ODE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field DSE[6] (RW)
+ *
+ * Drive strength configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Low drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ * - 0b1 - High drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_DSE field. */
+#define PORT_RD_PCR_DSE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_DSE_MASK) >> PORT_PCR_DSE_SHIFT)
+#define PORT_BRD_PCR_DSE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT))
+
+/*! @brief Set the DSE field to a new value. */
+#define PORT_WR_PCR_DSE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_DSE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_DSE(value)))
+#define PORT_BWR_PCR_DSE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field MUX[10:8] (RW)
+ *
+ * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
+ * reserved and may result in configuring the pin for a different pin muxing
+ * slot. The corresponding pin is configured in the following pin muxing slot as
+ * follows:
+ *
+ * Values:
+ * - 0b000 - Pin disabled (analog).
+ * - 0b001 - Alternative 1 (GPIO).
+ * - 0b010 - Alternative 2 (chip-specific).
+ * - 0b011 - Alternative 3 (chip-specific).
+ * - 0b100 - Alternative 4 (chip-specific).
+ * - 0b101 - Alternative 5 (chip-specific).
+ * - 0b110 - Alternative 6 (chip-specific).
+ * - 0b111 - Alternative 7 (chip-specific).
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_MUX field. */
+#define PORT_RD_PCR_MUX(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_MUX_MASK) >> PORT_PCR_MUX_SHIFT)
+#define PORT_BRD_PCR_MUX(base, index) (PORT_RD_PCR_MUX(base, index))
+
+/*! @brief Set the MUX field to a new value. */
+#define PORT_WR_PCR_MUX(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_MUX_MASK | PORT_PCR_ISF_MASK), PORT_PCR_MUX(value)))
+#define PORT_BWR_PCR_MUX(base, index, value) (PORT_WR_PCR_MUX(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field LK[15] (RW)
+ *
+ * Values:
+ * - 0b0 - Pin Control Register fields [15:0] are not locked.
+ * - 0b1 - Pin Control Register fields [15:0] are locked and cannot be updated
+ *     until the next system reset.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_LK field. */
+#define PORT_RD_PCR_LK(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_LK_MASK) >> PORT_PCR_LK_SHIFT)
+#define PORT_BRD_PCR_LK(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_LK_SHIFT))
+
+/*! @brief Set the LK field to a new value. */
+#define PORT_WR_PCR_LK(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_LK_MASK | PORT_PCR_ISF_MASK), PORT_PCR_LK(value)))
+#define PORT_BWR_PCR_LK(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_LK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field IRQC[19:16] (RW)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * corresponding pin is configured to generate interrupt/DMA request as follows:
+ *
+ * Values:
+ * - 0b0000 - Interrupt/DMA request disabled.
+ * - 0b0001 - DMA request on rising edge.
+ * - 0b0010 - DMA request on falling edge.
+ * - 0b0011 - DMA request on either edge.
+ * - 0b1000 - Interrupt when logic 0.
+ * - 0b1001 - Interrupt on rising-edge.
+ * - 0b1010 - Interrupt on falling-edge.
+ * - 0b1011 - Interrupt on either edge.
+ * - 0b1100 - Interrupt when logic 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_IRQC field. */
+#define PORT_RD_PCR_IRQC(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_IRQC_MASK) >> PORT_PCR_IRQC_SHIFT)
+#define PORT_BRD_PCR_IRQC(base, index) (PORT_RD_PCR_IRQC(base, index))
+
+/*! @brief Set the IRQC field to a new value. */
+#define PORT_WR_PCR_IRQC(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_IRQC_MASK | PORT_PCR_ISF_MASK), PORT_PCR_IRQC(value)))
+#define PORT_BWR_PCR_IRQC(base, index, value) (PORT_WR_PCR_IRQC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ISF[24] (W1C)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Configured interrupt is not detected.
+ * - 0b1 - Configured interrupt is detected. If the pin is configured to
+ *     generate a DMA request, then the corresponding flag will be cleared automatically
+ *     at the completion of the requested DMA transfer. Otherwise, the flag
+ *     remains set until a logic 1 is written to the flag. If the pin is configured
+ *     for a level sensitive interrupt and the pin remains asserted, then the flag
+ *     is set again immediately after it is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ISF field. */
+#define PORT_RD_PCR_ISF(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ISF_MASK) >> PORT_PCR_ISF_SHIFT)
+#define PORT_BRD_PCR_ISF(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT))
+
+/*! @brief Set the ISF field to a new value. */
+#define PORT_WR_PCR_ISF(base, index, value) (PORT_RMW_PCR(base, index, PORT_PCR_ISF_MASK, PORT_PCR_ISF(value)))
+#define PORT_BWR_PCR_ISF(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCLR - Global Pin Control Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCLR - Global Pin Control Low Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCLR register
+ */
+/*@{*/
+#define PORT_RD_GPCLR(base)      (PORT_GPCLR_REG(base))
+#define PORT_WR_GPCLR(base, value) (PORT_GPCLR_REG(base) = (value))
+#define PORT_RMW_GPCLR(base, mask, value) (PORT_WR_GPCLR(base, (PORT_RD_GPCLR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCLR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCLR_GPWD(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWD_MASK, PORT_GPCLR_GPWD(value)))
+#define PORT_BWR_GPCLR_GPWD(base, value) (PORT_WR_GPCLR_GPWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
+ *     the value in GPWD.
+ * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
+ *     value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCLR_GPWE(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWE_MASK, PORT_GPCLR_GPWE(value)))
+#define PORT_BWR_GPCLR_GPWE(base, value) (PORT_WR_GPCLR_GPWE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCHR - Global Pin Control High Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCHR - Global Pin Control High Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCHR register
+ */
+/*@{*/
+#define PORT_RD_GPCHR(base)      (PORT_GPCHR_REG(base))
+#define PORT_WR_GPCHR(base, value) (PORT_GPCHR_REG(base) = (value))
+#define PORT_RMW_GPCHR(base, mask, value) (PORT_WR_GPCHR(base, (PORT_RD_GPCHR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCHR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCHR_GPWD(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWD_MASK, PORT_GPCHR_GPWD(value)))
+#define PORT_BWR_GPCHR_GPWD(base, value) (PORT_WR_GPCHR_GPWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
+ *     the value in GPWD.
+ * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
+ *     value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCHR_GPWE(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWE_MASK, PORT_GPCHR_GPWE(value)))
+#define PORT_BWR_GPCHR_GPWE(base, value) (PORT_WR_GPCHR_GPWE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_ISFR - Interrupt Status Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_ISFR - Interrupt Status Flag Register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * Interrupt Status Flag for each pin is also visible in the corresponding Pin
+ * Control Register, and each flag can be cleared in either location.
+ */
+/*!
+ * @name Constants and macros for entire PORT_ISFR register
+ */
+/*@{*/
+#define PORT_RD_ISFR(base)       (PORT_ISFR_REG(base))
+#define PORT_WR_ISFR(base, value) (PORT_ISFR_REG(base) = (value))
+#define PORT_RMW_ISFR(base, mask, value) (PORT_WR_ISFR(base, (PORT_RD_ISFR(base) & ~(mask)) | (value)))
+#define PORT_SET_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) |  (value)))
+#define PORT_CLR_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) & ~(value)))
+#define PORT_TOG_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFER - Digital Filter Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFER - Digital Filter Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The corresponding bit is read only for pins that do not support a digital
+ * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
+ * the pins that support digital filter. The digital filter configuration is valid
+ * in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFER register
+ */
+/*@{*/
+#define PORT_RD_DFER(base)       (PORT_DFER_REG(base))
+#define PORT_WR_DFER(base, value) (PORT_DFER_REG(base) = (value))
+#define PORT_RMW_DFER(base, mask, value) (PORT_WR_DFER(base, (PORT_RD_DFER(base) & ~(mask)) | (value)))
+#define PORT_SET_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) |  (value)))
+#define PORT_CLR_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) & ~(value)))
+#define PORT_TOG_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFCR - Digital Filter Clock Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFCR - Digital Filter Clock Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFCR register
+ */
+/*@{*/
+#define PORT_RD_DFCR(base)       (PORT_DFCR_REG(base))
+#define PORT_WR_DFCR(base, value) (PORT_DFCR_REG(base) = (value))
+#define PORT_RMW_DFCR(base, mask, value) (PORT_WR_DFCR(base, (PORT_RD_DFCR(base) & ~(mask)) | (value)))
+#define PORT_SET_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) |  (value)))
+#define PORT_CLR_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) & ~(value)))
+#define PORT_TOG_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_DFCR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFCR, field CS[0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the clock source for the digital input filters. Changing the filter
+ * clock source must be done only when all digital filters are disabled.
+ *
+ * Values:
+ * - 0b0 - Digital filters are clocked by the bus clock.
+ * - 0b1 - Digital filters are clocked by the 1 kHz LPO clock.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_DFCR_CS field. */
+#define PORT_RD_DFCR_CS(base) ((PORT_DFCR_REG(base) & PORT_DFCR_CS_MASK) >> PORT_DFCR_CS_SHIFT)
+#define PORT_BRD_DFCR_CS(base) (BITBAND_ACCESS32(&PORT_DFCR_REG(base), PORT_DFCR_CS_SHIFT))
+
+/*! @brief Set the CS field to a new value. */
+#define PORT_WR_DFCR_CS(base, value) (PORT_RMW_DFCR(base, PORT_DFCR_CS_MASK, PORT_DFCR_CS(value)))
+#define PORT_BWR_DFCR_CS(base, value) (BITBAND_ACCESS32(&PORT_DFCR_REG(base), PORT_DFCR_CS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFWR - Digital Filter Width Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFWR - Digital Filter Width Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFWR register
+ */
+/*@{*/
+#define PORT_RD_DFWR(base)       (PORT_DFWR_REG(base))
+#define PORT_WR_DFWR(base, value) (PORT_DFWR_REG(base) = (value))
+#define PORT_RMW_DFWR(base, mask, value) (PORT_WR_DFWR(base, (PORT_RD_DFWR(base) & ~(mask)) | (value)))
+#define PORT_SET_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) |  (value)))
+#define PORT_CLR_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) & ~(value)))
+#define PORT_TOG_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_DFWR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFWR, field FILT[4:0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the maximum size of the glitches, in clock cycles, that the digital
+ * filter absorbs for the enabled digital filters. Glitches that are longer than
+ * this register setting will pass through the digital filter, and glitches that
+ * are equal to or less than this register setting are filtered. Changing the
+ * filter length must be done only after all filters are disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_DFWR_FILT field. */
+#define PORT_RD_DFWR_FILT(base) ((PORT_DFWR_REG(base) & PORT_DFWR_FILT_MASK) >> PORT_DFWR_FILT_SHIFT)
+#define PORT_BRD_DFWR_FILT(base) (PORT_RD_DFWR_FILT(base))
+
+/*! @brief Set the FILT field to a new value. */
+#define PORT_WR_DFWR_FILT(base, value) (PORT_RMW_DFWR(base, PORT_DFWR_FILT_MASK, PORT_DFWR_FILT(value)))
+#define PORT_BWR_DFWR_FILT(base, value) (PORT_WR_DFWR_FILT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 RCM
+ *
+ * Reset Control Module
+ *
+ * Registers defined in this header file:
+ * - RCM_SRS0 - System Reset Status Register 0
+ * - RCM_SRS1 - System Reset Status Register 1
+ * - RCM_RPFC - Reset Pin Filter Control register
+ * - RCM_RPFW - Reset Pin Filter Width register
+ * - RCM_MR - Mode Register
+ */
+
+#define RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */
+#define RCM_IDX (0U) /*!< Instance number for RCM. */
+
+/*******************************************************************************
+ * RCM_SRS0 - System Reset Status Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS0 - System Reset Status Register 0 (RO)
+ *
+ * Reset value: 0x82U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
+ * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS0 register
+ */
+/*@{*/
+#define RCM_RD_SRS0(base)        (RCM_SRS0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS0 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS0, field WAKEUP[0] (RO)
+ *
+ * Indicates a reset has been caused by an enabled LLWU module wakeup source
+ * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
+ * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
+ * mode causes a reset. This bit is cleared by any reset except WAKEUP.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by LLWU module wakeup source
+ * - 0b1 - Reset caused by LLWU module wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WAKEUP field. */
+#define RCM_RD_SRS0_WAKEUP(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WAKEUP_MASK) >> RCM_SRS0_WAKEUP_SHIFT)
+#define RCM_BRD_SRS0_WAKEUP(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_WAKEUP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LVD[1] (RO)
+ *
+ * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
+ * an LVD reset occurs. This field is also set by POR.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by LVD trip or POR
+ * - 0b1 - Reset caused by LVD trip or POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LVD field. */
+#define RCM_RD_SRS0_LVD(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LVD_MASK) >> RCM_SRS0_LVD_SHIFT)
+#define RCM_BRD_SRS0_LVD(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LVD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LOC[2] (RO)
+ *
+ * Indicates a reset has been caused by a loss of external clock. The MCG clock
+ * monitor must be enabled for a loss of clock to be detected. Refer to the
+ * detailed MCG description for information on enabling the clock monitor.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by a loss of external clock.
+ * - 0b1 - Reset caused by a loss of external clock.
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LOC field. */
+#define RCM_RD_SRS0_LOC(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOC_MASK) >> RCM_SRS0_LOC_SHIFT)
+#define RCM_BRD_SRS0_LOC(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LOC_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LOL[3] (RO)
+ *
+ * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
+ * MCG description for information on the loss-of-clock event.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by a loss of lock in the PLL
+ * - 0b1 - Reset caused by a loss of lock in the PLL
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LOL field. */
+#define RCM_RD_SRS0_LOL(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOL_MASK) >> RCM_SRS0_LOL_SHIFT)
+#define RCM_BRD_SRS0_LOL(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LOL_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field WDOG[5] (RO)
+ *
+ * Indicates a reset has been caused by the watchdog timer Computer Operating
+ * Properly (COP) timing out. This reset source can be blocked by disabling the COP
+ * watchdog: write 00 to SIM_COPCTRL[COPT].
+ *
+ * Values:
+ * - 0b0 - Reset not caused by watchdog timeout
+ * - 0b1 - Reset caused by watchdog timeout
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WDOG field. */
+#define RCM_RD_SRS0_WDOG(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WDOG_MASK) >> RCM_SRS0_WDOG_SHIFT)
+#define RCM_BRD_SRS0_WDOG(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_WDOG_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field PIN[6] (RO)
+ *
+ * Indicates a reset has been caused by an active-low level on the external
+ * RESET pin.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by external reset pin
+ * - 0b1 - Reset caused by external reset pin
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_PIN field. */
+#define RCM_RD_SRS0_PIN(base) ((RCM_SRS0_REG(base) & RCM_SRS0_PIN_MASK) >> RCM_SRS0_PIN_SHIFT)
+#define RCM_BRD_SRS0_PIN(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_PIN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field POR[7] (RO)
+ *
+ * Indicates a reset has been caused by the power-on detection logic. Because
+ * the internal supply voltage was ramping up at the time, the low-voltage reset
+ * (LVD) status bit is also set to indicate that the reset occurred while the
+ * internal supply was below the LVD threshold.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by POR
+ * - 0b1 - Reset caused by POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_POR field. */
+#define RCM_RD_SRS0_POR(base) ((RCM_SRS0_REG(base) & RCM_SRS0_POR_MASK) >> RCM_SRS0_POR_SHIFT)
+#define RCM_BRD_SRS0_POR(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_POR_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_SRS1 - System Reset Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS1 - System Reset Status Register 1 (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS1 register
+ */
+/*@{*/
+#define RCM_RD_SRS1(base)        (RCM_SRS1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS1 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS1, field JTAG[0] (RO)
+ *
+ * Indicates a reset has been caused by JTAG selection of certain IR codes:
+ * EZPORT, EXTEST, HIGHZ, and CLAMP.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by JTAG
+ * - 0b1 - Reset caused by JTAG
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_JTAG field. */
+#define RCM_RD_SRS1_JTAG(base) ((RCM_SRS1_REG(base) & RCM_SRS1_JTAG_MASK) >> RCM_SRS1_JTAG_SHIFT)
+#define RCM_BRD_SRS1_JTAG(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_JTAG_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field LOCKUP[1] (RO)
+ *
+ * Indicates a reset has been caused by the ARM core indication of a LOCKUP
+ * event.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by core LOCKUP event
+ * - 0b1 - Reset caused by core LOCKUP event
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_LOCKUP field. */
+#define RCM_RD_SRS1_LOCKUP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_LOCKUP_MASK) >> RCM_SRS1_LOCKUP_SHIFT)
+#define RCM_BRD_SRS1_LOCKUP(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_LOCKUP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SW[2] (RO)
+ *
+ * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
+ * Application Interrupt and Reset Control Register in the ARM core.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by software setting of SYSRESETREQ bit
+ * - 0b1 - Reset caused by software setting of SYSRESETREQ bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SW field. */
+#define RCM_RD_SRS1_SW(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SW_MASK) >> RCM_SRS1_SW_SHIFT)
+#define RCM_BRD_SRS1_SW(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_SW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field MDM_AP[3] (RO)
+ *
+ * Indicates a reset has been caused by the host debugger system setting of the
+ * System Reset Request bit in the MDM-AP Control Register.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by host debugger system setting of the System Reset
+ *     Request bit
+ * - 0b1 - Reset caused by host debugger system setting of the System Reset
+ *     Request bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_MDM_AP field. */
+#define RCM_RD_SRS1_MDM_AP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_MDM_AP_MASK) >> RCM_SRS1_MDM_AP_SHIFT)
+#define RCM_BRD_SRS1_MDM_AP(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_MDM_AP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field EZPT[4] (RO)
+ *
+ * Indicates a reset has been caused by EzPort receiving the RESET command while
+ * the device is in EzPort mode.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by EzPort receiving the RESET command while the
+ *     device is in EzPort mode
+ * - 0b1 - Reset caused by EzPort receiving the RESET command while the device
+ *     is in EzPort mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_EZPT field. */
+#define RCM_RD_SRS1_EZPT(base) ((RCM_SRS1_REG(base) & RCM_SRS1_EZPT_MASK) >> RCM_SRS1_EZPT_SHIFT)
+#define RCM_BRD_SRS1_EZPT(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_EZPT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SACKERR[5] (RO)
+ *
+ * Indicates that after an attempt to enter Stop mode, a reset has been caused
+ * by a failure of one or more peripherals to acknowledge within approximately one
+ * second to enter stop mode.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by peripheral failure to acknowledge attempt to
+ *     enter stop mode
+ * - 0b1 - Reset caused by peripheral failure to acknowledge attempt to enter
+ *     stop mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SACKERR field. */
+#define RCM_RD_SRS1_SACKERR(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SACKERR_MASK) >> RCM_SRS1_SACKERR_SHIFT)
+#define RCM_BRD_SRS1_SACKERR(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_SACKERR_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFC - Reset Pin Filter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFC - Reset Pin Filter Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
+ * other reset types. The bus clock filter is reset when disabled or when entering
+ * stop mode. The LPO filter is reset when disabled or when entering any low
+ * leakage stop mode .
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFC register
+ */
+/*@{*/
+#define RCM_RD_RPFC(base)        (RCM_RPFC_REG(base))
+#define RCM_WR_RPFC(base, value) (RCM_RPFC_REG(base) = (value))
+#define RCM_RMW_RPFC(base, mask, value) (RCM_WR_RPFC(base, (RCM_RD_RPFC(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) |  (value)))
+#define RCM_CLR_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) & ~(value)))
+#define RCM_TOG_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFC bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
+ *
+ * Selects how the reset pin filter is enabled in run and wait modes.
+ *
+ * Values:
+ * - 0b00 - All filtering disabled
+ * - 0b01 - Bus clock filter enabled for normal operation
+ * - 0b10 - LPO clock filter enabled for normal operation
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */
+#define RCM_RD_RPFC_RSTFLTSRW(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSRW_MASK) >> RCM_RPFC_RSTFLTSRW_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSRW(base) (RCM_RD_RPFC_RSTFLTSRW(base))
+
+/*! @brief Set the RSTFLTSRW field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSRW(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSRW_MASK, RCM_RPFC_RSTFLTSRW(value)))
+#define RCM_BWR_RPFC_RSTFLTSRW(base, value) (RCM_WR_RPFC_RSTFLTSRW(base, value))
+/*@}*/
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
+ *
+ * Selects how the reset pin filter is enabled in Stop and VLPS modes
+ *
+ * Values:
+ * - 0b0 - All filtering disabled
+ * - 0b1 - LPO clock filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */
+#define RCM_RD_RPFC_RSTFLTSS(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSS_MASK) >> RCM_RPFC_RSTFLTSS_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSS(base) (BITBAND_ACCESS8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT))
+
+/*! @brief Set the RSTFLTSS field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSS(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSS_MASK, RCM_RPFC_RSTFLTSS(value)))
+#define RCM_BWR_RPFC_RSTFLTSS(base, value) (BITBAND_ACCESS8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFW - Reset Pin Filter Width register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFW - Reset Pin Filter Width register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
+ * They are unaffected by other reset types.
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFW register
+ */
+/*@{*/
+#define RCM_RD_RPFW(base)        (RCM_RPFW_REG(base))
+#define RCM_WR_RPFW(base, value) (RCM_RPFW_REG(base) = (value))
+#define RCM_RMW_RPFW(base, mask, value) (RCM_WR_RPFW(base, (RCM_RD_RPFW(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) |  (value)))
+#define RCM_CLR_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) & ~(value)))
+#define RCM_TOG_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFW bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
+ *
+ * Selects the reset pin bus clock filter width.
+ *
+ * Values:
+ * - 0b00000 - Bus clock filter count is 1
+ * - 0b00001 - Bus clock filter count is 2
+ * - 0b00010 - Bus clock filter count is 3
+ * - 0b00011 - Bus clock filter count is 4
+ * - 0b00100 - Bus clock filter count is 5
+ * - 0b00101 - Bus clock filter count is 6
+ * - 0b00110 - Bus clock filter count is 7
+ * - 0b00111 - Bus clock filter count is 8
+ * - 0b01000 - Bus clock filter count is 9
+ * - 0b01001 - Bus clock filter count is 10
+ * - 0b01010 - Bus clock filter count is 11
+ * - 0b01011 - Bus clock filter count is 12
+ * - 0b01100 - Bus clock filter count is 13
+ * - 0b01101 - Bus clock filter count is 14
+ * - 0b01110 - Bus clock filter count is 15
+ * - 0b01111 - Bus clock filter count is 16
+ * - 0b10000 - Bus clock filter count is 17
+ * - 0b10001 - Bus clock filter count is 18
+ * - 0b10010 - Bus clock filter count is 19
+ * - 0b10011 - Bus clock filter count is 20
+ * - 0b10100 - Bus clock filter count is 21
+ * - 0b10101 - Bus clock filter count is 22
+ * - 0b10110 - Bus clock filter count is 23
+ * - 0b10111 - Bus clock filter count is 24
+ * - 0b11000 - Bus clock filter count is 25
+ * - 0b11001 - Bus clock filter count is 26
+ * - 0b11010 - Bus clock filter count is 27
+ * - 0b11011 - Bus clock filter count is 28
+ * - 0b11100 - Bus clock filter count is 29
+ * - 0b11101 - Bus clock filter count is 30
+ * - 0b11110 - Bus clock filter count is 31
+ * - 0b11111 - Bus clock filter count is 32
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */
+#define RCM_RD_RPFW_RSTFLTSEL(base) ((RCM_RPFW_REG(base) & RCM_RPFW_RSTFLTSEL_MASK) >> RCM_RPFW_RSTFLTSEL_SHIFT)
+#define RCM_BRD_RPFW_RSTFLTSEL(base) (RCM_RD_RPFW_RSTFLTSEL(base))
+
+/*! @brief Set the RSTFLTSEL field to a new value. */
+#define RCM_WR_RPFW_RSTFLTSEL(base, value) (RCM_RMW_RPFW(base, RCM_RPFW_RSTFLTSEL_MASK, RCM_RPFW_RSTFLTSEL(value)))
+#define RCM_BWR_RPFW_RSTFLTSEL(base, value) (RCM_WR_RPFW_RSTFLTSEL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_MR - Mode Register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_MR - Mode Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the state of the
+ * mode pins during the last Chip Reset.
+ */
+/*!
+ * @name Constants and macros for entire RCM_MR register
+ */
+/*@{*/
+#define RCM_RD_MR(base)          (RCM_MR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_MR bitfields
+ */
+
+/*!
+ * @name Register RCM_MR, field EZP_MS[1] (RO)
+ *
+ * Reflects the state of the EZP_MS pin during the last Chip Reset
+ *
+ * Values:
+ * - 0b0 - Pin deasserted (logic 1)
+ * - 0b1 - Pin asserted (logic 0)
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_MR_EZP_MS field. */
+#define RCM_RD_MR_EZP_MS(base) ((RCM_MR_REG(base) & RCM_MR_EZP_MS_MASK) >> RCM_MR_EZP_MS_SHIFT)
+#define RCM_BRD_MR_EZP_MS(base) (BITBAND_ACCESS8(&RCM_MR_REG(base), RCM_MR_EZP_MS_SHIFT))
+/*@}*/
+
+/*
+ * MK64F12 RFSYS
+ *
+ * System register file
+ *
+ * Registers defined in this header file:
+ * - RFSYS_REG - Register file register
+ */
+
+#define RFSYS_INSTANCE_COUNT (1U) /*!< Number of instances of the RFSYS module. */
+#define RFSYS_IDX (0U) /*!< Instance number for RFSYS. */
+
+/*******************************************************************************
+ * RFSYS_REG - Register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFSYS_REG - Register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFSYS_REG register
+ */
+/*@{*/
+#define RFSYS_RD_REG(base, index) (RFSYS_REG_REG(base, index))
+#define RFSYS_WR_REG(base, index, value) (RFSYS_REG_REG(base, index) = (value))
+#define RFSYS_RMW_REG(base, index, mask, value) (RFSYS_WR_REG(base, index, (RFSYS_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFSYS_SET_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) |  (value)))
+#define RFSYS_CLR_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) & ~(value)))
+#define RFSYS_TOG_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFSYS_REG bitfields
+ */
+
+/*!
+ * @name Register RFSYS_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LL field. */
+#define RFSYS_RD_REG_LL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LL_MASK) >> RFSYS_REG_LL_SHIFT)
+#define RFSYS_BRD_REG_LL(base, index) (RFSYS_RD_REG_LL(base, index))
+
+/*! @brief Set the LL field to a new value. */
+#define RFSYS_WR_REG_LL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LL_MASK, RFSYS_REG_LL(value)))
+#define RFSYS_BWR_REG_LL(base, index, value) (RFSYS_WR_REG_LL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LH field. */
+#define RFSYS_RD_REG_LH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LH_MASK) >> RFSYS_REG_LH_SHIFT)
+#define RFSYS_BRD_REG_LH(base, index) (RFSYS_RD_REG_LH(base, index))
+
+/*! @brief Set the LH field to a new value. */
+#define RFSYS_WR_REG_LH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LH_MASK, RFSYS_REG_LH(value)))
+#define RFSYS_BWR_REG_LH(base, index, value) (RFSYS_WR_REG_LH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HL field. */
+#define RFSYS_RD_REG_HL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HL_MASK) >> RFSYS_REG_HL_SHIFT)
+#define RFSYS_BRD_REG_HL(base, index) (RFSYS_RD_REG_HL(base, index))
+
+/*! @brief Set the HL field to a new value. */
+#define RFSYS_WR_REG_HL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HL_MASK, RFSYS_REG_HL(value)))
+#define RFSYS_BWR_REG_HL(base, index, value) (RFSYS_WR_REG_HL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HH field. */
+#define RFSYS_RD_REG_HH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HH_MASK) >> RFSYS_REG_HH_SHIFT)
+#define RFSYS_BRD_REG_HH(base, index) (RFSYS_RD_REG_HH(base, index))
+
+/*! @brief Set the HH field to a new value. */
+#define RFSYS_WR_REG_HH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HH_MASK, RFSYS_REG_HH(value)))
+#define RFSYS_BWR_REG_HH(base, index, value) (RFSYS_WR_REG_HH(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 RFVBAT
+ *
+ * VBAT register file
+ *
+ * Registers defined in this header file:
+ * - RFVBAT_REG - VBAT register file register
+ */
+
+#define RFVBAT_INSTANCE_COUNT (1U) /*!< Number of instances of the RFVBAT module. */
+#define RFVBAT_IDX (0U) /*!< Instance number for RFVBAT. */
+
+/*******************************************************************************
+ * RFVBAT_REG - VBAT register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFVBAT_REG - VBAT register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFVBAT_REG register
+ */
+/*@{*/
+#define RFVBAT_RD_REG(base, index) (RFVBAT_REG_REG(base, index))
+#define RFVBAT_WR_REG(base, index, value) (RFVBAT_REG_REG(base, index) = (value))
+#define RFVBAT_RMW_REG(base, index, mask, value) (RFVBAT_WR_REG(base, index, (RFVBAT_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFVBAT_SET_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) |  (value)))
+#define RFVBAT_CLR_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) & ~(value)))
+#define RFVBAT_TOG_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFVBAT_REG bitfields
+ */
+
+/*!
+ * @name Register RFVBAT_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_LL field. */
+#define RFVBAT_RD_REG_LL(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_LL_MASK) >> RFVBAT_REG_LL_SHIFT)
+#define RFVBAT_BRD_REG_LL(base, index) (RFVBAT_RD_REG_LL(base, index))
+
+/*! @brief Set the LL field to a new value. */
+#define RFVBAT_WR_REG_LL(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_LL_MASK, RFVBAT_REG_LL(value)))
+#define RFVBAT_BWR_REG_LL(base, index, value) (RFVBAT_WR_REG_LL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_LH field. */
+#define RFVBAT_RD_REG_LH(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_LH_MASK) >> RFVBAT_REG_LH_SHIFT)
+#define RFVBAT_BRD_REG_LH(base, index) (RFVBAT_RD_REG_LH(base, index))
+
+/*! @brief Set the LH field to a new value. */
+#define RFVBAT_WR_REG_LH(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_LH_MASK, RFVBAT_REG_LH(value)))
+#define RFVBAT_BWR_REG_LH(base, index, value) (RFVBAT_WR_REG_LH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_HL field. */
+#define RFVBAT_RD_REG_HL(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_HL_MASK) >> RFVBAT_REG_HL_SHIFT)
+#define RFVBAT_BRD_REG_HL(base, index) (RFVBAT_RD_REG_HL(base, index))
+
+/*! @brief Set the HL field to a new value. */
+#define RFVBAT_WR_REG_HL(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_HL_MASK, RFVBAT_REG_HL(value)))
+#define RFVBAT_BWR_REG_HL(base, index, value) (RFVBAT_WR_REG_HL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_HH field. */
+#define RFVBAT_RD_REG_HH(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_HH_MASK) >> RFVBAT_REG_HH_SHIFT)
+#define RFVBAT_BRD_REG_HH(base, index) (RFVBAT_RD_REG_HH(base, index))
+
+/*! @brief Set the HH field to a new value. */
+#define RFVBAT_WR_REG_HH(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_HH_MASK, RFVBAT_REG_HH(value)))
+#define RFVBAT_BWR_REG_HH(base, index, value) (RFVBAT_WR_REG_HH(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 RNG
+ *
+ * Random Number Generator Accelerator
+ *
+ * Registers defined in this header file:
+ * - RNG_CR - RNGA Control Register
+ * - RNG_SR - RNGA Status Register
+ * - RNG_ER - RNGA Entropy Register
+ * - RNG_OR - RNGA Output Register
+ */
+
+#define RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
+#define RNG_IDX (0U) /*!< Instance number for RNG. */
+
+/*******************************************************************************
+ * RNG_CR - RNGA Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_CR - RNGA Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the operation of RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_CR register
+ */
+/*@{*/
+#define RNG_RD_CR(base)          (RNG_CR_REG(base))
+#define RNG_WR_CR(base, value)   (RNG_CR_REG(base) = (value))
+#define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value)))
+#define RNG_SET_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) |  (value)))
+#define RNG_CLR_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) & ~(value)))
+#define RNG_TOG_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RNG_CR bitfields
+ */
+
+/*!
+ * @name Register RNG_CR, field GO[0] (RW)
+ *
+ * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
+ * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
+ * OR[RANDOUT] with data.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_GO field. */
+#define RNG_RD_CR_GO(base)   ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT)
+#define RNG_BRD_CR_GO(base)  (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_GO_SHIFT))
+
+/*! @brief Set the GO field to a new value. */
+#define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value)))
+#define RNG_BWR_CR_GO(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_GO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field HA[1] (RW)
+ *
+ * Enables notification of security violations (via SR[SECV]). A security
+ * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
+ * After enabling notification of security violations, you must reset RNGA to
+ * disable them again.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_HA field. */
+#define RNG_RD_CR_HA(base)   ((RNG_CR_REG(base) & RNG_CR_HA_MASK) >> RNG_CR_HA_SHIFT)
+#define RNG_BRD_CR_HA(base)  (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_HA_SHIFT))
+
+/*! @brief Set the HA field to a new value. */
+#define RNG_WR_CR_HA(base, value) (RNG_RMW_CR(base, RNG_CR_HA_MASK, RNG_CR_HA(value)))
+#define RNG_BWR_CR_HA(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_HA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field INTM[2] (RW)
+ *
+ * Masks the triggering of an error interrupt to the interrupt controller when
+ * an OR underflow condition occurs. An OR underflow condition occurs when you
+ * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
+ *
+ * Values:
+ * - 0b0 - Not masked
+ * - 0b1 - Masked
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_INTM field. */
+#define RNG_RD_CR_INTM(base) ((RNG_CR_REG(base) & RNG_CR_INTM_MASK) >> RNG_CR_INTM_SHIFT)
+#define RNG_BRD_CR_INTM(base) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_INTM_SHIFT))
+
+/*! @brief Set the INTM field to a new value. */
+#define RNG_WR_CR_INTM(base, value) (RNG_RMW_CR(base, RNG_CR_INTM_MASK, RNG_CR_INTM(value)))
+#define RNG_BWR_CR_INTM(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_INTM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field CLRI[3] (WORZ)
+ *
+ * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
+ *
+ * Values:
+ * - 0b0 - Do not clear the interrupt.
+ * - 0b1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
+ *     the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
+ */
+/*@{*/
+/*! @brief Set the CLRI field to a new value. */
+#define RNG_WR_CR_CLRI(base, value) (RNG_RMW_CR(base, RNG_CR_CLRI_MASK, RNG_CR_CLRI(value)))
+#define RNG_BWR_CR_CLRI(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_CLRI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field SLP[4] (RW)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_SLP field. */
+#define RNG_RD_CR_SLP(base)  ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT)
+#define RNG_BRD_CR_SLP(base) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_SLP_SHIFT))
+
+/*! @brief Set the SLP field to a new value. */
+#define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value)))
+#define RNG_BWR_CR_SLP(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_SLP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_SR - RNGA Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_SR - RNGA Status Register (RO)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Indicates the status of RNGA. This register is read-only.
+ */
+/*!
+ * @name Constants and macros for entire RNG_SR register
+ */
+/*@{*/
+#define RNG_RD_SR(base)          (RNG_SR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RNG_SR bitfields
+ */
+
+/*!
+ * @name Register RNG_SR, field SECV[0] (RO)
+ *
+ * Used only when high assurance is enabled (CR[HA]). Indicates that a security
+ * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
+ * RNGA.
+ *
+ * Values:
+ * - 0b0 - No security violation
+ * - 0b1 - Security violation
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SECV field. */
+#define RNG_RD_SR_SECV(base) ((RNG_SR_REG(base) & RNG_SR_SECV_MASK) >> RNG_SR_SECV_SHIFT)
+#define RNG_BRD_SR_SECV(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_SECV_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field LRS[1] (RO)
+ *
+ * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
+ * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
+ * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
+ * After you read this register, RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_LRS field. */
+#define RNG_RD_SR_LRS(base)  ((RNG_SR_REG(base) & RNG_SR_LRS_MASK) >> RNG_SR_LRS_SHIFT)
+#define RNG_BRD_SR_LRS(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_LRS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field ORU[2] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last read
+ * this register (SR) or RNGA was reset, regardless of whether the error
+ * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
+ * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
+ * field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_ORU field. */
+#define RNG_RD_SR_ORU(base)  ((RNG_SR_REG(base) & RNG_SR_ORU_MASK) >> RNG_SR_ORU_SHIFT)
+#define RNG_BRD_SR_ORU(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_ORU_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field ERRI[3] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last
+ * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
+ * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
+ * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
+ * indicator (via CR[CLRI]), RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_ERRI field. */
+#define RNG_RD_SR_ERRI(base) ((RNG_SR_REG(base) & RNG_SR_ERRI_MASK) >> RNG_SR_ERRI_SHIFT)
+#define RNG_BRD_SR_ERRI(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_ERRI_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field SLP[4] (RO)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SLP field. */
+#define RNG_RD_SR_SLP(base)  ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT)
+#define RNG_BRD_SR_SLP(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_SLP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
+ *
+ * Indicates the number of random-data words that are in OR[RANDOUT], which
+ * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
+ * is not 0, then the contents of a random number contained in OR[RANDOUT] are
+ * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
+ *
+ * Values:
+ * - 0b00000000 - No words (empty)
+ * - 0b00000001 - One word (valid)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_LVL field. */
+#define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT)
+#define RNG_BRD_SR_OREG_LVL(base) (RNG_RD_SR_OREG_LVL(base))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
+ *
+ * Indicates the size of the Output (OR) register in terms of the number of
+ * 32-bit random-data words it can hold.
+ *
+ * Values:
+ * - 0b00000001 - One word (this value is fixed)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
+#define RNG_RD_SR_OREG_SIZE(base) ((RNG_SR_REG(base) & RNG_SR_OREG_SIZE_MASK) >> RNG_SR_OREG_SIZE_SHIFT)
+#define RNG_BRD_SR_OREG_SIZE(base) (RNG_RD_SR_OREG_SIZE(base))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_ER - RNGA Entropy Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_ER - RNGA Entropy Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies an entropy value that RNGA uses in addition to its ring oscillators
+ * to seed its pseudorandom algorithm. This is a write-only register; reads
+ * return all zeros.
+ */
+/*!
+ * @name Constants and macros for entire RNG_ER register
+ */
+/*@{*/
+#define RNG_RD_ER(base)          (RNG_ER_REG(base))
+#define RNG_WR_ER(base, value)   (RNG_ER_REG(base) = (value))
+#define RNG_RMW_ER(base, mask, value) (RNG_WR_ER(base, (RNG_RD_ER(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_OR - RNGA Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_OR - RNGA Output Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Stores a random-data word generated by RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_OR register
+ */
+/*@{*/
+#define RNG_RD_OR(base)          (RNG_OR_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 RTC
+ *
+ * Secure Real Time Clock
+ *
+ * Registers defined in this header file:
+ * - RTC_TSR - RTC Time Seconds Register
+ * - RTC_TPR - RTC Time Prescaler Register
+ * - RTC_TAR - RTC Time Alarm Register
+ * - RTC_TCR - RTC Time Compensation Register
+ * - RTC_CR - RTC Control Register
+ * - RTC_SR - RTC Status Register
+ * - RTC_LR - RTC Lock Register
+ * - RTC_IER - RTC Interrupt Enable Register
+ * - RTC_WAR - RTC Write Access Register
+ * - RTC_RAR - RTC Read Access Register
+ */
+
+#define RTC_INSTANCE_COUNT (1U) /*!< Number of instances of the RTC module. */
+#define RTC_IDX (0U) /*!< Instance number for RTC. */
+
+/*******************************************************************************
+ * RTC_TSR - RTC Time Seconds Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TSR - RTC Time Seconds Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TSR register
+ */
+/*@{*/
+#define RTC_RD_TSR(base)         (RTC_TSR_REG(base))
+#define RTC_WR_TSR(base, value)  (RTC_TSR_REG(base) = (value))
+#define RTC_RMW_TSR(base, mask, value) (RTC_WR_TSR(base, (RTC_RD_TSR(base) & ~(mask)) | (value)))
+#define RTC_SET_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) |  (value)))
+#define RTC_CLR_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) & ~(value)))
+#define RTC_TOG_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TPR - RTC Time Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TPR - RTC Time Prescaler Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TPR register
+ */
+/*@{*/
+#define RTC_RD_TPR(base)         (RTC_TPR_REG(base))
+#define RTC_WR_TPR(base, value)  (RTC_TPR_REG(base) = (value))
+#define RTC_RMW_TPR(base, mask, value) (RTC_WR_TPR(base, (RTC_RD_TPR(base) & ~(mask)) | (value)))
+#define RTC_SET_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) |  (value)))
+#define RTC_CLR_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) & ~(value)))
+#define RTC_TOG_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TPR bitfields
+ */
+
+/*!
+ * @name Register RTC_TPR, field TPR[15:0] (RW)
+ *
+ * When the time counter is enabled, the TPR is read only and increments every
+ * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
+ * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
+ * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
+ * to a logic zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TPR_TPR field. */
+#define RTC_RD_TPR_TPR(base) ((RTC_TPR_REG(base) & RTC_TPR_TPR_MASK) >> RTC_TPR_TPR_SHIFT)
+#define RTC_BRD_TPR_TPR(base) (RTC_RD_TPR_TPR(base))
+
+/*! @brief Set the TPR field to a new value. */
+#define RTC_WR_TPR_TPR(base, value) (RTC_RMW_TPR(base, RTC_TPR_TPR_MASK, RTC_TPR_TPR(value)))
+#define RTC_BWR_TPR_TPR(base, value) (RTC_WR_TPR_TPR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TAR - RTC Time Alarm Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TAR - RTC Time Alarm Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TAR register
+ */
+/*@{*/
+#define RTC_RD_TAR(base)         (RTC_TAR_REG(base))
+#define RTC_WR_TAR(base, value)  (RTC_TAR_REG(base) = (value))
+#define RTC_RMW_TAR(base, mask, value) (RTC_WR_TAR(base, (RTC_RD_TAR(base) & ~(mask)) | (value)))
+#define RTC_SET_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) |  (value)))
+#define RTC_CLR_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) & ~(value)))
+#define RTC_TOG_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TCR - RTC Time Compensation Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TCR - RTC Time Compensation Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TCR register
+ */
+/*@{*/
+#define RTC_RD_TCR(base)         (RTC_TCR_REG(base))
+#define RTC_WR_TCR(base, value)  (RTC_TCR_REG(base) = (value))
+#define RTC_RMW_TCR(base, mask, value) (RTC_WR_TCR(base, (RTC_RD_TCR(base) & ~(mask)) | (value)))
+#define RTC_SET_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) |  (value)))
+#define RTC_CLR_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) & ~(value)))
+#define RTC_TOG_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TCR bitfields
+ */
+
+/*!
+ * @name Register RTC_TCR, field TCR[7:0] (RW)
+ *
+ * Configures the number of 32.768 kHz clock cycles in each second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ *
+ * Values:
+ * - 0b10000000 - Time Prescaler Register overflows every 32896 clock cycles.
+ * - 0b11111111 - Time Prescaler Register overflows every 32769 clock cycles.
+ * - 0b00000000 - Time Prescaler Register overflows every 32768 clock cycles.
+ * - 0b00000001 - Time Prescaler Register overflows every 32767 clock cycles.
+ * - 0b01111111 - Time Prescaler Register overflows every 32641 clock cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCR field. */
+#define RTC_RD_TCR_TCR(base) ((RTC_TCR_REG(base) & RTC_TCR_TCR_MASK) >> RTC_TCR_TCR_SHIFT)
+#define RTC_BRD_TCR_TCR(base) (RTC_RD_TCR_TCR(base))
+
+/*! @brief Set the TCR field to a new value. */
+#define RTC_WR_TCR_TCR(base, value) (RTC_RMW_TCR(base, RTC_TCR_TCR_MASK, RTC_TCR_TCR(value)))
+#define RTC_BWR_TCR_TCR(base, value) (RTC_WR_TCR_TCR(base, value))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIR[15:8] (RW)
+ *
+ * Configures the compensation interval in seconds from 1 to 256 to control how
+ * frequently the TCR should adjust the number of 32.768 kHz cycles in each
+ * second. The value written should be one less than the number of seconds. For
+ * example, write zero to configure for a compensation interval of one second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIR field. */
+#define RTC_RD_TCR_CIR(base) ((RTC_TCR_REG(base) & RTC_TCR_CIR_MASK) >> RTC_TCR_CIR_SHIFT)
+#define RTC_BRD_TCR_CIR(base) (RTC_RD_TCR_CIR(base))
+
+/*! @brief Set the CIR field to a new value. */
+#define RTC_WR_TCR_CIR(base, value) (RTC_RMW_TCR(base, RTC_TCR_CIR_MASK, RTC_TCR_CIR(value)))
+#define RTC_BWR_TCR_CIR(base, value) (RTC_WR_TCR_CIR(base, value))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field TCV[23:16] (RO)
+ *
+ * Current value used by the compensation logic for the present second interval.
+ * Updated once a second if the CIC equals 0 with the contents of the TCR field.
+ * If the CIC does not equal zero then it is loaded with zero (compensation is
+ * not enabled for that second increment).
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCV field. */
+#define RTC_RD_TCR_TCV(base) ((RTC_TCR_REG(base) & RTC_TCR_TCV_MASK) >> RTC_TCR_TCV_SHIFT)
+#define RTC_BRD_TCR_TCV(base) (RTC_RD_TCR_TCV(base))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIC[31:24] (RO)
+ *
+ * Current value of the compensation interval counter. If the compensation
+ * interval counter equals zero then it is loaded with the contents of the CIR. If the
+ * CIC does not equal zero then it is decremented once a second.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIC field. */
+#define RTC_RD_TCR_CIC(base) ((RTC_TCR_REG(base) & RTC_TCR_CIC_MASK) >> RTC_TCR_CIC_SHIFT)
+#define RTC_BRD_TCR_CIC(base) (RTC_RD_TCR_CIC(base))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_CR - RTC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_CR - RTC Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_CR register
+ */
+/*@{*/
+#define RTC_RD_CR(base)          (RTC_CR_REG(base))
+#define RTC_WR_CR(base, value)   (RTC_CR_REG(base) = (value))
+#define RTC_RMW_CR(base, mask, value) (RTC_WR_CR(base, (RTC_RD_CR(base) & ~(mask)) | (value)))
+#define RTC_SET_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) |  (value)))
+#define RTC_CLR_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) & ~(value)))
+#define RTC_TOG_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_CR bitfields
+ */
+
+/*!
+ * @name Register RTC_CR, field SWR[0] (RW)
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
+ *     RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
+ *     explicitly clearing it.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SWR field. */
+#define RTC_RD_CR_SWR(base)  ((RTC_CR_REG(base) & RTC_CR_SWR_MASK) >> RTC_CR_SWR_SHIFT)
+#define RTC_BRD_CR_SWR(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT))
+
+/*! @brief Set the SWR field to a new value. */
+#define RTC_WR_CR_SWR(base, value) (RTC_RMW_CR(base, RTC_CR_SWR_MASK, RTC_CR_SWR(value)))
+#define RTC_BWR_CR_SWR(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPE[1] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0b0 - Wakeup pin is disabled.
+ * - 0b1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPE field. */
+#define RTC_RD_CR_WPE(base)  ((RTC_CR_REG(base) & RTC_CR_WPE_MASK) >> RTC_CR_WPE_SHIFT)
+#define RTC_BRD_CR_WPE(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT))
+
+/*! @brief Set the WPE field to a new value. */
+#define RTC_WR_CR_WPE(base, value) (RTC_RMW_CR(base, RTC_CR_WPE_MASK, RTC_CR_WPE(value)))
+#define RTC_BWR_CR_WPE(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SUP[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Non-supervisor mode write accesses are not supported and generate a
+ *     bus error.
+ * - 0b1 - Non-supervisor mode write accesses are supported.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SUP field. */
+#define RTC_RD_CR_SUP(base)  ((RTC_CR_REG(base) & RTC_CR_SUP_MASK) >> RTC_CR_SUP_SHIFT)
+#define RTC_BRD_CR_SUP(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT))
+
+/*! @brief Set the SUP field to a new value. */
+#define RTC_WR_CR_SUP(base, value) (RTC_RMW_CR(base, RTC_CR_SUP_MASK, RTC_CR_SUP(value)))
+#define RTC_BWR_CR_SUP(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field UM[3] (RW)
+ *
+ * Allows SR[TCE] to be written even when the Status Register is locked. When
+ * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
+ * the SR[TCE] is clear.
+ *
+ * Values:
+ * - 0b0 - Registers cannot be written when locked.
+ * - 0b1 - Registers can be written when locked under limited conditions.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_UM field. */
+#define RTC_RD_CR_UM(base)   ((RTC_CR_REG(base) & RTC_CR_UM_MASK) >> RTC_CR_UM_SHIFT)
+#define RTC_BRD_CR_UM(base)  (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT))
+
+/*! @brief Set the UM field to a new value. */
+#define RTC_WR_CR_UM(base, value) (RTC_RMW_CR(base, RTC_CR_UM_MASK, RTC_CR_UM(value)))
+#define RTC_BWR_CR_UM(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPS[4] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0b0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ * - 0b1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup
+ *     pin is turned on and the 32kHz clock is output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPS field. */
+#define RTC_RD_CR_WPS(base)  ((RTC_CR_REG(base) & RTC_CR_WPS_MASK) >> RTC_CR_WPS_SHIFT)
+#define RTC_BRD_CR_WPS(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT))
+
+/*! @brief Set the WPS field to a new value. */
+#define RTC_WR_CR_WPS(base, value) (RTC_RMW_CR(base, RTC_CR_WPS_MASK, RTC_CR_WPS(value)))
+#define RTC_BWR_CR_WPS(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field OSCE[8] (RW)
+ *
+ * Values:
+ * - 0b0 - 32.768 kHz oscillator is disabled.
+ * - 0b1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
+ *     oscillator startup time before enabling the time counter to allow the 32.768
+ *     kHz clock time to stabilize.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_OSCE field. */
+#define RTC_RD_CR_OSCE(base) ((RTC_CR_REG(base) & RTC_CR_OSCE_MASK) >> RTC_CR_OSCE_SHIFT)
+#define RTC_BRD_CR_OSCE(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT))
+
+/*! @brief Set the OSCE field to a new value. */
+#define RTC_WR_CR_OSCE(base, value) (RTC_RMW_CR(base, RTC_CR_OSCE_MASK, RTC_CR_OSCE(value)))
+#define RTC_BWR_CR_OSCE(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field CLKO[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The 32 kHz clock is output to other peripherals.
+ * - 0b1 - The 32 kHz clock is not output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_CLKO field. */
+#define RTC_RD_CR_CLKO(base) ((RTC_CR_REG(base) & RTC_CR_CLKO_MASK) >> RTC_CR_CLKO_SHIFT)
+#define RTC_BRD_CR_CLKO(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT))
+
+/*! @brief Set the CLKO field to a new value. */
+#define RTC_WR_CR_CLKO(base, value) (RTC_RMW_CR(base, RTC_CR_CLKO_MASK, RTC_CR_CLKO(value)))
+#define RTC_BWR_CR_CLKO(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC16P[10] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC16P field. */
+#define RTC_RD_CR_SC16P(base) ((RTC_CR_REG(base) & RTC_CR_SC16P_MASK) >> RTC_CR_SC16P_SHIFT)
+#define RTC_BRD_CR_SC16P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT))
+
+/*! @brief Set the SC16P field to a new value. */
+#define RTC_WR_CR_SC16P(base, value) (RTC_RMW_CR(base, RTC_CR_SC16P_MASK, RTC_CR_SC16P(value)))
+#define RTC_BWR_CR_SC16P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC8P[11] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC8P field. */
+#define RTC_RD_CR_SC8P(base) ((RTC_CR_REG(base) & RTC_CR_SC8P_MASK) >> RTC_CR_SC8P_SHIFT)
+#define RTC_BRD_CR_SC8P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT))
+
+/*! @brief Set the SC8P field to a new value. */
+#define RTC_WR_CR_SC8P(base, value) (RTC_RMW_CR(base, RTC_CR_SC8P_MASK, RTC_CR_SC8P(value)))
+#define RTC_BWR_CR_SC8P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC4P[12] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC4P field. */
+#define RTC_RD_CR_SC4P(base) ((RTC_CR_REG(base) & RTC_CR_SC4P_MASK) >> RTC_CR_SC4P_SHIFT)
+#define RTC_BRD_CR_SC4P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT))
+
+/*! @brief Set the SC4P field to a new value. */
+#define RTC_WR_CR_SC4P(base, value) (RTC_RMW_CR(base, RTC_CR_SC4P_MASK, RTC_CR_SC4P(value)))
+#define RTC_BWR_CR_SC4P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC2P[13] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC2P field. */
+#define RTC_RD_CR_SC2P(base) ((RTC_CR_REG(base) & RTC_CR_SC2P_MASK) >> RTC_CR_SC2P_SHIFT)
+#define RTC_BRD_CR_SC2P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT))
+
+/*! @brief Set the SC2P field to a new value. */
+#define RTC_WR_CR_SC2P(base, value) (RTC_RMW_CR(base, RTC_CR_SC2P_MASK, RTC_CR_SC2P(value)))
+#define RTC_BWR_CR_SC2P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_SR - RTC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_SR - RTC Status Register (RW)
+ *
+ * Reset value: 0x00000001U
+ */
+/*!
+ * @name Constants and macros for entire RTC_SR register
+ */
+/*@{*/
+#define RTC_RD_SR(base)          (RTC_SR_REG(base))
+#define RTC_WR_SR(base, value)   (RTC_SR_REG(base) = (value))
+#define RTC_RMW_SR(base, mask, value) (RTC_WR_SR(base, (RTC_RD_SR(base) & ~(mask)) | (value)))
+#define RTC_SET_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) |  (value)))
+#define RTC_CLR_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) & ~(value)))
+#define RTC_TOG_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_SR bitfields
+ */
+
+/*!
+ * @name Register RTC_SR, field TIF[0] (RO)
+ *
+ * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
+ * do not increment and read as zero when this bit is set. This bit is cleared by
+ * writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0b0 - Time is valid.
+ * - 0b1 - Time is invalid and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TIF field. */
+#define RTC_RD_SR_TIF(base)  ((RTC_SR_REG(base) & RTC_SR_TIF_MASK) >> RTC_SR_TIF_SHIFT)
+#define RTC_BRD_SR_TIF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TIF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TOF[1] (RO)
+ *
+ * Time overflow flag is set when the time counter is enabled and overflows. The
+ * TSR and TPR do not increment and read as zero when this bit is set. This bit
+ * is cleared by writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0b0 - Time overflow has not occurred.
+ * - 0b1 - Time overflow has occurred and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TOF field. */
+#define RTC_RD_SR_TOF(base)  ((RTC_SR_REG(base) & RTC_SR_TOF_MASK) >> RTC_SR_TOF_SHIFT)
+#define RTC_BRD_SR_TOF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TOF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TAF[2] (RO)
+ *
+ * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
+ * increments. This bit is cleared by writing the TAR register.
+ *
+ * Values:
+ * - 0b0 - Time alarm has not occurred.
+ * - 0b1 - Time alarm has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TAF field. */
+#define RTC_RD_SR_TAF(base)  ((RTC_SR_REG(base) & RTC_SR_TAF_MASK) >> RTC_SR_TAF_SHIFT)
+#define RTC_BRD_SR_TAF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TAF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TCE[4] (RW)
+ *
+ * When time counter is disabled the TSR register and TPR register are
+ * writeable, but do not increment. When time counter is enabled the TSR register and TPR
+ * register are not writeable, but increment.
+ *
+ * Values:
+ * - 0b0 - Time counter is disabled.
+ * - 0b1 - Time counter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TCE field. */
+#define RTC_RD_SR_TCE(base)  ((RTC_SR_REG(base) & RTC_SR_TCE_MASK) >> RTC_SR_TCE_SHIFT)
+#define RTC_BRD_SR_TCE(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT))
+
+/*! @brief Set the TCE field to a new value. */
+#define RTC_WR_SR_TCE(base, value) (RTC_RMW_SR(base, RTC_SR_TCE_MASK, RTC_SR_TCE(value)))
+#define RTC_BWR_SR_TCE(base, value) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_LR - RTC Lock Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_LR - RTC Lock Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_LR register
+ */
+/*@{*/
+#define RTC_RD_LR(base)          (RTC_LR_REG(base))
+#define RTC_WR_LR(base, value)   (RTC_LR_REG(base) = (value))
+#define RTC_RMW_LR(base, mask, value) (RTC_WR_LR(base, (RTC_RD_LR(base) & ~(mask)) | (value)))
+#define RTC_SET_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) |  (value)))
+#define RTC_CLR_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) & ~(value)))
+#define RTC_TOG_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_LR bitfields
+ */
+
+/*!
+ * @name Register RTC_LR, field TCL[3] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Time Compensation Register is locked and writes are ignored.
+ * - 0b1 - Time Compensation Register is not locked and writes complete as
+ *     normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_TCL field. */
+#define RTC_RD_LR_TCL(base)  ((RTC_LR_REG(base) & RTC_LR_TCL_MASK) >> RTC_LR_TCL_SHIFT)
+#define RTC_BRD_LR_TCL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT))
+
+/*! @brief Set the TCL field to a new value. */
+#define RTC_WR_LR_TCL(base, value) (RTC_RMW_LR(base, RTC_LR_TCL_MASK, RTC_LR_TCL(value)))
+#define RTC_BWR_LR_TCL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field CRL[4] (RW)
+ *
+ * After being cleared, this bit can only be set by VBAT POR.
+ *
+ * Values:
+ * - 0b0 - Control Register is locked and writes are ignored.
+ * - 0b1 - Control Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_CRL field. */
+#define RTC_RD_LR_CRL(base)  ((RTC_LR_REG(base) & RTC_LR_CRL_MASK) >> RTC_LR_CRL_SHIFT)
+#define RTC_BRD_LR_CRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT))
+
+/*! @brief Set the CRL field to a new value. */
+#define RTC_WR_LR_CRL(base, value) (RTC_RMW_LR(base, RTC_LR_CRL_MASK, RTC_LR_CRL(value)))
+#define RTC_BWR_LR_CRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field SRL[5] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Status Register is locked and writes are ignored.
+ * - 0b1 - Status Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_SRL field. */
+#define RTC_RD_LR_SRL(base)  ((RTC_LR_REG(base) & RTC_LR_SRL_MASK) >> RTC_LR_SRL_SHIFT)
+#define RTC_BRD_LR_SRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT))
+
+/*! @brief Set the SRL field to a new value. */
+#define RTC_WR_LR_SRL(base, value) (RTC_RMW_LR(base, RTC_LR_SRL_MASK, RTC_LR_SRL(value)))
+#define RTC_BWR_LR_SRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field LRL[6] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Lock Register is locked and writes are ignored.
+ * - 0b1 - Lock Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_LRL field. */
+#define RTC_RD_LR_LRL(base)  ((RTC_LR_REG(base) & RTC_LR_LRL_MASK) >> RTC_LR_LRL_SHIFT)
+#define RTC_BRD_LR_LRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT))
+
+/*! @brief Set the LRL field to a new value. */
+#define RTC_WR_LR_LRL(base, value) (RTC_RMW_LR(base, RTC_LR_LRL_MASK, RTC_LR_LRL(value)))
+#define RTC_BWR_LR_LRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_IER - RTC Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_IER - RTC Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00000007U
+ */
+/*!
+ * @name Constants and macros for entire RTC_IER register
+ */
+/*@{*/
+#define RTC_RD_IER(base)         (RTC_IER_REG(base))
+#define RTC_WR_IER(base, value)  (RTC_IER_REG(base) = (value))
+#define RTC_RMW_IER(base, mask, value) (RTC_WR_IER(base, (RTC_RD_IER(base) & ~(mask)) | (value)))
+#define RTC_SET_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) |  (value)))
+#define RTC_CLR_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) & ~(value)))
+#define RTC_TOG_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_IER bitfields
+ */
+
+/*!
+ * @name Register RTC_IER, field TIIE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Time invalid flag does not generate an interrupt.
+ * - 0b1 - Time invalid flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TIIE field. */
+#define RTC_RD_IER_TIIE(base) ((RTC_IER_REG(base) & RTC_IER_TIIE_MASK) >> RTC_IER_TIIE_SHIFT)
+#define RTC_BRD_IER_TIIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT))
+
+/*! @brief Set the TIIE field to a new value. */
+#define RTC_WR_IER_TIIE(base, value) (RTC_RMW_IER(base, RTC_IER_TIIE_MASK, RTC_IER_TIIE(value)))
+#define RTC_BWR_IER_TIIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TOIE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Time overflow flag does not generate an interrupt.
+ * - 0b1 - Time overflow flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TOIE field. */
+#define RTC_RD_IER_TOIE(base) ((RTC_IER_REG(base) & RTC_IER_TOIE_MASK) >> RTC_IER_TOIE_SHIFT)
+#define RTC_BRD_IER_TOIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT))
+
+/*! @brief Set the TOIE field to a new value. */
+#define RTC_WR_IER_TOIE(base, value) (RTC_RMW_IER(base, RTC_IER_TOIE_MASK, RTC_IER_TOIE(value)))
+#define RTC_BWR_IER_TOIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TAIE[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Time alarm flag does not generate an interrupt.
+ * - 0b1 - Time alarm flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TAIE field. */
+#define RTC_RD_IER_TAIE(base) ((RTC_IER_REG(base) & RTC_IER_TAIE_MASK) >> RTC_IER_TAIE_SHIFT)
+#define RTC_BRD_IER_TAIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT))
+
+/*! @brief Set the TAIE field to a new value. */
+#define RTC_WR_IER_TAIE(base, value) (RTC_RMW_IER(base, RTC_IER_TAIE_MASK, RTC_IER_TAIE(value)))
+#define RTC_BWR_IER_TAIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TSIE[4] (RW)
+ *
+ * The seconds interrupt is an edge-sensitive interrupt with a dedicated
+ * interrupt vector. It is generated once a second and requires no software overhead
+ * (there is no corresponding status flag to clear).
+ *
+ * Values:
+ * - 0b0 - Seconds interrupt is disabled.
+ * - 0b1 - Seconds interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TSIE field. */
+#define RTC_RD_IER_TSIE(base) ((RTC_IER_REG(base) & RTC_IER_TSIE_MASK) >> RTC_IER_TSIE_SHIFT)
+#define RTC_BRD_IER_TSIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT))
+
+/*! @brief Set the TSIE field to a new value. */
+#define RTC_WR_IER_TSIE(base, value) (RTC_RMW_IER(base, RTC_IER_TSIE_MASK, RTC_IER_TSIE(value)))
+#define RTC_BWR_IER_TSIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field WPON[7] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices. Whenever the
+ * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - If the wakeup pin is enabled, then the wakeup pin will assert.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_WPON field. */
+#define RTC_RD_IER_WPON(base) ((RTC_IER_REG(base) & RTC_IER_WPON_MASK) >> RTC_IER_WPON_SHIFT)
+#define RTC_BRD_IER_WPON(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT))
+
+/*! @brief Set the WPON field to a new value. */
+#define RTC_WR_IER_WPON(base, value) (RTC_RMW_IER(base, RTC_IER_WPON_MASK, RTC_IER_WPON(value)))
+#define RTC_BWR_IER_WPON(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_WAR - RTC Write Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_WAR - RTC Write Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_WAR register
+ */
+/*@{*/
+#define RTC_RD_WAR(base)         (RTC_WAR_REG(base))
+#define RTC_WR_WAR(base, value)  (RTC_WAR_REG(base) = (value))
+#define RTC_RMW_WAR(base, mask, value) (RTC_WR_WAR(base, (RTC_RD_WAR(base) & ~(mask)) | (value)))
+#define RTC_SET_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) |  (value)))
+#define RTC_CLR_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) & ~(value)))
+#define RTC_TOG_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_WAR bitfields
+ */
+
+/*!
+ * @name Register RTC_WAR, field TSRW[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Seconds Register are ignored.
+ * - 0b1 - Writes to the Time Seconds Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TSRW field. */
+#define RTC_RD_WAR_TSRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TSRW_MASK) >> RTC_WAR_TSRW_SHIFT)
+#define RTC_BRD_WAR_TSRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TSRW_SHIFT))
+
+/*! @brief Set the TSRW field to a new value. */
+#define RTC_WR_WAR_TSRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TSRW_MASK, RTC_WAR_TSRW(value)))
+#define RTC_BWR_WAR_TSRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TSRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TPRW[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Prescaler Register are ignored.
+ * - 0b1 - Writes to the Time Prescaler Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TPRW field. */
+#define RTC_RD_WAR_TPRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TPRW_MASK) >> RTC_WAR_TPRW_SHIFT)
+#define RTC_BRD_WAR_TPRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TPRW_SHIFT))
+
+/*! @brief Set the TPRW field to a new value. */
+#define RTC_WR_WAR_TPRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TPRW_MASK, RTC_WAR_TPRW(value)))
+#define RTC_BWR_WAR_TPRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TPRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TARW[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Alarm Register are ignored.
+ * - 0b1 - Writes to the Time Alarm Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TARW field. */
+#define RTC_RD_WAR_TARW(base) ((RTC_WAR_REG(base) & RTC_WAR_TARW_MASK) >> RTC_WAR_TARW_SHIFT)
+#define RTC_BRD_WAR_TARW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TARW_SHIFT))
+
+/*! @brief Set the TARW field to a new value. */
+#define RTC_WR_WAR_TARW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TARW_MASK, RTC_WAR_TARW(value)))
+#define RTC_BWR_WAR_TARW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TARW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TCRW[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Compensation Register are ignored.
+ * - 0b1 - Writes to the Time Compensation Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TCRW field. */
+#define RTC_RD_WAR_TCRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TCRW_MASK) >> RTC_WAR_TCRW_SHIFT)
+#define RTC_BRD_WAR_TCRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TCRW_SHIFT))
+
+/*! @brief Set the TCRW field to a new value. */
+#define RTC_WR_WAR_TCRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TCRW_MASK, RTC_WAR_TCRW(value)))
+#define RTC_BWR_WAR_TCRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TCRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field CRW[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Control Register are ignored.
+ * - 0b1 - Writes to the Control Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_CRW field. */
+#define RTC_RD_WAR_CRW(base) ((RTC_WAR_REG(base) & RTC_WAR_CRW_MASK) >> RTC_WAR_CRW_SHIFT)
+#define RTC_BRD_WAR_CRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_CRW_SHIFT))
+
+/*! @brief Set the CRW field to a new value. */
+#define RTC_WR_WAR_CRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_CRW_MASK, RTC_WAR_CRW(value)))
+#define RTC_BWR_WAR_CRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_CRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field SRW[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Status Register are ignored.
+ * - 0b1 - Writes to the Status Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_SRW field. */
+#define RTC_RD_WAR_SRW(base) ((RTC_WAR_REG(base) & RTC_WAR_SRW_MASK) >> RTC_WAR_SRW_SHIFT)
+#define RTC_BRD_WAR_SRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_SRW_SHIFT))
+
+/*! @brief Set the SRW field to a new value. */
+#define RTC_WR_WAR_SRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_SRW_MASK, RTC_WAR_SRW(value)))
+#define RTC_BWR_WAR_SRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_SRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field LRW[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Lock Register are ignored.
+ * - 0b1 - Writes to the Lock Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_LRW field. */
+#define RTC_RD_WAR_LRW(base) ((RTC_WAR_REG(base) & RTC_WAR_LRW_MASK) >> RTC_WAR_LRW_SHIFT)
+#define RTC_BRD_WAR_LRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_LRW_SHIFT))
+
+/*! @brief Set the LRW field to a new value. */
+#define RTC_WR_WAR_LRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_LRW_MASK, RTC_WAR_LRW(value)))
+#define RTC_BWR_WAR_LRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_LRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field IERW[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Interupt Enable Register are ignored.
+ * - 0b1 - Writes to the Interrupt Enable Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_IERW field. */
+#define RTC_RD_WAR_IERW(base) ((RTC_WAR_REG(base) & RTC_WAR_IERW_MASK) >> RTC_WAR_IERW_SHIFT)
+#define RTC_BRD_WAR_IERW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_IERW_SHIFT))
+
+/*! @brief Set the IERW field to a new value. */
+#define RTC_WR_WAR_IERW(base, value) (RTC_RMW_WAR(base, RTC_WAR_IERW_MASK, RTC_WAR_IERW(value)))
+#define RTC_BWR_WAR_IERW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_IERW_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_RAR - RTC Read Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_RAR - RTC Read Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_RAR register
+ */
+/*@{*/
+#define RTC_RD_RAR(base)         (RTC_RAR_REG(base))
+#define RTC_WR_RAR(base, value)  (RTC_RAR_REG(base) = (value))
+#define RTC_RMW_RAR(base, mask, value) (RTC_WR_RAR(base, (RTC_RD_RAR(base) & ~(mask)) | (value)))
+#define RTC_SET_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) |  (value)))
+#define RTC_CLR_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) & ~(value)))
+#define RTC_TOG_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_RAR bitfields
+ */
+
+/*!
+ * @name Register RTC_RAR, field TSRR[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Seconds Register are ignored.
+ * - 0b1 - Reads to the Time Seconds Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TSRR field. */
+#define RTC_RD_RAR_TSRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TSRR_MASK) >> RTC_RAR_TSRR_SHIFT)
+#define RTC_BRD_RAR_TSRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TSRR_SHIFT))
+
+/*! @brief Set the TSRR field to a new value. */
+#define RTC_WR_RAR_TSRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TSRR_MASK, RTC_RAR_TSRR(value)))
+#define RTC_BWR_RAR_TSRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TSRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TPRR[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Pprescaler Register are ignored.
+ * - 0b1 - Reads to the Time Prescaler Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TPRR field. */
+#define RTC_RD_RAR_TPRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TPRR_MASK) >> RTC_RAR_TPRR_SHIFT)
+#define RTC_BRD_RAR_TPRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TPRR_SHIFT))
+
+/*! @brief Set the TPRR field to a new value. */
+#define RTC_WR_RAR_TPRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TPRR_MASK, RTC_RAR_TPRR(value)))
+#define RTC_BWR_RAR_TPRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TPRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TARR[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Alarm Register are ignored.
+ * - 0b1 - Reads to the Time Alarm Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TARR field. */
+#define RTC_RD_RAR_TARR(base) ((RTC_RAR_REG(base) & RTC_RAR_TARR_MASK) >> RTC_RAR_TARR_SHIFT)
+#define RTC_BRD_RAR_TARR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TARR_SHIFT))
+
+/*! @brief Set the TARR field to a new value. */
+#define RTC_WR_RAR_TARR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TARR_MASK, RTC_RAR_TARR(value)))
+#define RTC_BWR_RAR_TARR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TARR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TCRR[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Compensation Register are ignored.
+ * - 0b1 - Reads to the Time Compensation Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TCRR field. */
+#define RTC_RD_RAR_TCRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TCRR_MASK) >> RTC_RAR_TCRR_SHIFT)
+#define RTC_BRD_RAR_TCRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TCRR_SHIFT))
+
+/*! @brief Set the TCRR field to a new value. */
+#define RTC_WR_RAR_TCRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TCRR_MASK, RTC_RAR_TCRR(value)))
+#define RTC_BWR_RAR_TCRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TCRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field CRR[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Control Register are ignored.
+ * - 0b1 - Reads to the Control Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_CRR field. */
+#define RTC_RD_RAR_CRR(base) ((RTC_RAR_REG(base) & RTC_RAR_CRR_MASK) >> RTC_RAR_CRR_SHIFT)
+#define RTC_BRD_RAR_CRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_CRR_SHIFT))
+
+/*! @brief Set the CRR field to a new value. */
+#define RTC_WR_RAR_CRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_CRR_MASK, RTC_RAR_CRR(value)))
+#define RTC_BWR_RAR_CRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_CRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field SRR[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Status Register are ignored.
+ * - 0b1 - Reads to the Status Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_SRR field. */
+#define RTC_RD_RAR_SRR(base) ((RTC_RAR_REG(base) & RTC_RAR_SRR_MASK) >> RTC_RAR_SRR_SHIFT)
+#define RTC_BRD_RAR_SRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_SRR_SHIFT))
+
+/*! @brief Set the SRR field to a new value. */
+#define RTC_WR_RAR_SRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_SRR_MASK, RTC_RAR_SRR(value)))
+#define RTC_BWR_RAR_SRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_SRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field LRR[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Lock Register are ignored.
+ * - 0b1 - Reads to the Lock Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_LRR field. */
+#define RTC_RD_RAR_LRR(base) ((RTC_RAR_REG(base) & RTC_RAR_LRR_MASK) >> RTC_RAR_LRR_SHIFT)
+#define RTC_BRD_RAR_LRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_LRR_SHIFT))
+
+/*! @brief Set the LRR field to a new value. */
+#define RTC_WR_RAR_LRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_LRR_MASK, RTC_RAR_LRR(value)))
+#define RTC_BWR_RAR_LRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_LRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field IERR[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Interrupt Enable Register are ignored.
+ * - 0b1 - Reads to the Interrupt Enable Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_IERR field. */
+#define RTC_RD_RAR_IERR(base) ((RTC_RAR_REG(base) & RTC_RAR_IERR_MASK) >> RTC_RAR_IERR_SHIFT)
+#define RTC_BRD_RAR_IERR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_IERR_SHIFT))
+
+/*! @brief Set the IERR field to a new value. */
+#define RTC_WR_RAR_IERR(base, value) (RTC_RMW_RAR(base, RTC_RAR_IERR_MASK, RTC_RAR_IERR(value)))
+#define RTC_BWR_RAR_IERR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_IERR_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 SDHC
+ *
+ * Secured Digital Host Controller
+ *
+ * Registers defined in this header file:
+ * - SDHC_DSADDR - DMA System Address register
+ * - SDHC_BLKATTR - Block Attributes register
+ * - SDHC_CMDARG - Command Argument register
+ * - SDHC_XFERTYP - Transfer Type register
+ * - SDHC_CMDRSP - Command Response 0
+ * - SDHC_DATPORT - Buffer Data Port register
+ * - SDHC_PRSSTAT - Present State register
+ * - SDHC_PROCTL - Protocol Control register
+ * - SDHC_SYSCTL - System Control register
+ * - SDHC_IRQSTAT - Interrupt Status register
+ * - SDHC_IRQSTATEN - Interrupt Status Enable register
+ * - SDHC_IRQSIGEN - Interrupt Signal Enable register
+ * - SDHC_AC12ERR - Auto CMD12 Error Status Register
+ * - SDHC_HTCAPBLT - Host Controller Capabilities
+ * - SDHC_WML - Watermark Level Register
+ * - SDHC_FEVT - Force Event register
+ * - SDHC_ADMAES - ADMA Error Status register
+ * - SDHC_ADSADDR - ADMA System Addressregister
+ * - SDHC_VENDOR - Vendor Specific register
+ * - SDHC_MMCBOOT - MMC Boot register
+ * - SDHC_HOSTVER - Host Controller Version
+ */
+
+#define SDHC_INSTANCE_COUNT (1U) /*!< Number of instances of the SDHC module. */
+#define SDHC_IDX (0U) /*!< Instance number for SDHC. */
+
+/*******************************************************************************
+ * SDHC_DSADDR - DMA System Address register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_DSADDR - DMA System Address register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for DMA
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_DSADDR register
+ */
+/*@{*/
+#define SDHC_RD_DSADDR(base)     (SDHC_DSADDR_REG(base))
+#define SDHC_WR_DSADDR(base, value) (SDHC_DSADDR_REG(base) = (value))
+#define SDHC_RMW_DSADDR(base, mask, value) (SDHC_WR_DSADDR(base, (SDHC_RD_DSADDR(base) & ~(mask)) | (value)))
+#define SDHC_SET_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) |  (value)))
+#define SDHC_CLR_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) & ~(value)))
+#define SDHC_TOG_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_DSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
+ *
+ * Contains the 32-bit system memory address for a DMA transfer. Because the
+ * address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
+ * When the SDHC stops a DMA transfer, this register points to the system address
+ * of the next contiguous data position. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read operation
+ * during transfers may return an invalid value. The host driver shall initialize
+ * this register before starting a DMA transaction. After DMA has stopped, the
+ * system address of the next contiguous data position can be read from this register.
+ * This register is protected during a data transfer. When data lines are
+ * active, write to this register is ignored. The host driver shall wait, until
+ * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
+ * not support a virtual memory system. It supports only continuous physical
+ * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
+ * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
+ * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
+ * automatically alters the value of internal address counter, so SW cannot
+ * change this register when IRQSTAT[TC] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_DSADDR_DSADDR field. */
+#define SDHC_RD_DSADDR_DSADDR(base) ((SDHC_DSADDR_REG(base) & SDHC_DSADDR_DSADDR_MASK) >> SDHC_DSADDR_DSADDR_SHIFT)
+#define SDHC_BRD_DSADDR_DSADDR(base) (SDHC_RD_DSADDR_DSADDR(base))
+
+/*! @brief Set the DSADDR field to a new value. */
+#define SDHC_WR_DSADDR_DSADDR(base, value) (SDHC_RMW_DSADDR(base, SDHC_DSADDR_DSADDR_MASK, SDHC_DSADDR_DSADDR(value)))
+#define SDHC_BWR_DSADDR_DSADDR(base, value) (SDHC_WR_DSADDR_DSADDR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_BLKATTR - Block Attributes register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_BLKATTR - Block Attributes register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to configure the number of data blocks and the number
+ * of bytes in each block.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_BLKATTR register
+ */
+/*@{*/
+#define SDHC_RD_BLKATTR(base)    (SDHC_BLKATTR_REG(base))
+#define SDHC_WR_BLKATTR(base, value) (SDHC_BLKATTR_REG(base) = (value))
+#define SDHC_RMW_BLKATTR(base, mask, value) (SDHC_WR_BLKATTR(base, (SDHC_RD_BLKATTR(base) & ~(mask)) | (value)))
+#define SDHC_SET_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) |  (value)))
+#define SDHC_CLR_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) & ~(value)))
+#define SDHC_TOG_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_BLKATTR bitfields
+ */
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
+ *
+ * Specifies the block size for block data transfers. Values ranging from 1 byte
+ * up to the maximum buffer size can be set. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read
+ * operations during transfers may return an invalid value, and write operations will be
+ * ignored.
+ *
+ * Values:
+ * - 0b0000000000000 - No data transfer.
+ * - 0b0000000000001 - 1 Byte
+ * - 0b0000000000010 - 2 Bytes
+ * - 0b0000000000011 - 3 Bytes
+ * - 0b0000000000100 - 4 Bytes
+ * - 0b0000111111111 - 511 Bytes
+ * - 0b0001000000000 - 512 Bytes
+ * - 0b0100000000000 - 2048 Bytes
+ * - 0b1000000000000 - 4096 Bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field. */
+#define SDHC_RD_BLKATTR_BLKSIZE(base) ((SDHC_BLKATTR_REG(base) & SDHC_BLKATTR_BLKSIZE_MASK) >> SDHC_BLKATTR_BLKSIZE_SHIFT)
+#define SDHC_BRD_BLKATTR_BLKSIZE(base) (SDHC_RD_BLKATTR_BLKSIZE(base))
+
+/*! @brief Set the BLKSIZE field to a new value. */
+#define SDHC_WR_BLKATTR_BLKSIZE(base, value) (SDHC_RMW_BLKATTR(base, SDHC_BLKATTR_BLKSIZE_MASK, SDHC_BLKATTR_BLKSIZE(value)))
+#define SDHC_BWR_BLKATTR_BLKSIZE(base, value) (SDHC_WR_BLKATTR_BLKSIZE(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
+ *
+ * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
+ * multiple block transfers. For single block transfer, this register will
+ * always read as 1. The host driver shall set this register to a value between 1 and
+ * the maximum block count. The SDHC decrements the block count after each block
+ * transfer and stops when the count reaches zero. Setting the block count to 0
+ * results in no data blocks being transferred. This register must be accessed
+ * only when no transaction is executing, that is, after transactions are stopped.
+ * During data transfer, read operations on this register may return an invalid
+ * value and write operations are ignored. When saving transfer content as a result
+ * of a suspend command, the number of blocks yet to be transferred can be
+ * determined by reading this register. The reading of this register must be applied
+ * after transfer is paused by stop at block gap operation and before sending the
+ * command marked as suspend. This is because when suspend command is sent out,
+ * SDHC will regard the current transfer as aborted and change BLKCNT back to its
+ * original value instead of keeping the dynamical indicator of remained block
+ * count. When restoring transfer content prior to issuing a resume command, the
+ * host driver shall restore the previously saved block count. Although the BLKCNT
+ * field is 0 after reset, the read of reset value is 0x1. This is because when
+ * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
+ * BLKCNT is always 1.
+ *
+ * Values:
+ * - 0b0000000000000000 - Stop count.
+ * - 0b0000000000000001 - 1 block
+ * - 0b0000000000000010 - 2 blocks
+ * - 0b1111111111111111 - 65535 blocks
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_BLKATTR_BLKCNT field. */
+#define SDHC_RD_BLKATTR_BLKCNT(base) ((SDHC_BLKATTR_REG(base) & SDHC_BLKATTR_BLKCNT_MASK) >> SDHC_BLKATTR_BLKCNT_SHIFT)
+#define SDHC_BRD_BLKATTR_BLKCNT(base) (SDHC_RD_BLKATTR_BLKCNT(base))
+
+/*! @brief Set the BLKCNT field to a new value. */
+#define SDHC_WR_BLKATTR_BLKCNT(base, value) (SDHC_RMW_BLKATTR(base, SDHC_BLKATTR_BLKCNT_MASK, SDHC_BLKATTR_BLKCNT(value)))
+#define SDHC_BWR_BLKATTR_BLKCNT(base, value) (SDHC_WR_BLKATTR_BLKCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_CMDARG - Command Argument register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_CMDARG - Command Argument register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the SD/MMC command argument.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_CMDARG register
+ */
+/*@{*/
+#define SDHC_RD_CMDARG(base)     (SDHC_CMDARG_REG(base))
+#define SDHC_WR_CMDARG(base, value) (SDHC_CMDARG_REG(base) = (value))
+#define SDHC_RMW_CMDARG(base, mask, value) (SDHC_WR_CMDARG(base, (SDHC_RD_CMDARG(base) & ~(mask)) | (value)))
+#define SDHC_SET_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) |  (value)))
+#define SDHC_CLR_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) & ~(value)))
+#define SDHC_TOG_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_XFERTYP - Transfer Type register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_XFERTYP - Transfer Type register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to control the operation of data transfers. The host
+ * driver shall set this register before issuing a command followed by a data
+ * transfer, or before issuing a resume command. To prevent data loss, the SDHC
+ * prevents writing to the bits that are involved in the data transfer of this
+ * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
+ * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
+ * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
+ * send a command with data by writing to this register is ignored; when
+ * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
+ * data transfer involved, it is mandatory that the block size is nonzero.
+ * Besides, block count must also be nonzero, or indicated as single block transfer
+ * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
+ * this register is 0 when written), otherwise SDHC will ignore the sending of
+ * this command and do nothing. For write command, with all above restrictions, it
+ * is also mandatory that the write protect switch is not active (WPSPL bit of
+ * Present State Register is 1), otherwise SDHC will also ignore the command. If
+ * the commands with data transfer does not receive the response in 64 clock
+ * cycles, that is, response time-out, SDHC will regard the external device does not
+ * accept the command and abort the data transfer. In this scenario, the driver
+ * must issue the command again to retry the transfer. It is also possible that,
+ * for some reason, the card responds to the command but SDHC does not receive the
+ * response, and if it is internal DMA (either simple DMA or ADMA) read
+ * operation, the external system memory is over-written by the internal DMA with data
+ * sent back from the card. The following table shows the summary of how register
+ * settings determine the type of data transfer. Transfer Type register setting for
+ * various transfer types Multi/Single block select Block count enable Block
+ * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
+ * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
+ * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
+ * in regards to XFERTYP[RSPTYP] as well as the name of the response type.
+ * Relationship between parameters and the name of the response type Response type
+ * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
+ * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
+ * the SDIO specification, response type notation for R5b is not defined. R5
+ * includes R5b in the SDIO specification. But R5b is defined in this specification
+ * to specify that the SDHC will check the busy status after receiving a
+ * response. For example, usually CMD52 is used with R5, but the I/O abort command shall
+ * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
+ * The CRC check shall be disabled for these response types.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_XFERTYP register
+ */
+/*@{*/
+#define SDHC_RD_XFERTYP(base)    (SDHC_XFERTYP_REG(base))
+#define SDHC_WR_XFERTYP(base, value) (SDHC_XFERTYP_REG(base) = (value))
+#define SDHC_RMW_XFERTYP(base, mask, value) (SDHC_WR_XFERTYP(base, (SDHC_RD_XFERTYP(base) & ~(mask)) | (value)))
+#define SDHC_SET_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) |  (value)))
+#define SDHC_CLR_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) & ~(value)))
+#define SDHC_TOG_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_XFERTYP bitfields
+ */
+
+/*!
+ * @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
+ *
+ * Enables DMA functionality. If this bit is set to 1, a DMA operation shall
+ * begin when the host driver sets the DPSEL bit of this register. Whether the
+ * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DMAEN field. */
+#define SDHC_RD_XFERTYP_DMAEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DMAEN_MASK) >> SDHC_XFERTYP_DMAEN_SHIFT)
+#define SDHC_BRD_XFERTYP_DMAEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define SDHC_WR_XFERTYP_DMAEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DMAEN_MASK, SDHC_XFERTYP_DMAEN(value)))
+#define SDHC_BWR_XFERTYP_DMAEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field BCEN[1] (RW)
+ *
+ * Used to enable the Block Count register, which is only relevant for multiple
+ * block transfers. When this bit is 0, the internal counter for block is
+ * disabled, which is useful in executing an infinite transfer.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_BCEN field. */
+#define SDHC_RD_XFERTYP_BCEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_BCEN_MASK) >> SDHC_XFERTYP_BCEN_SHIFT)
+#define SDHC_BRD_XFERTYP_BCEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_BCEN_SHIFT))
+
+/*! @brief Set the BCEN field to a new value. */
+#define SDHC_WR_XFERTYP_BCEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_BCEN_MASK, SDHC_XFERTYP_BCEN(value)))
+#define SDHC_BWR_XFERTYP_BCEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_BCEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
+ *
+ * Multiple block transfers for memory require a CMD12 to stop the transaction.
+ * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
+ * last block transfer has completed. The host driver shall not set this bit to
+ * issue commands that do not require CMD12 to stop a multiple block data
+ * transfer. In particular, secure commands defined in File Security Specification (see
+ * reference list) do not require CMD12. In single block transfer, the SDHC will
+ * ignore this bit whether it is set or not.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_AC12EN field. */
+#define SDHC_RD_XFERTYP_AC12EN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_AC12EN_MASK) >> SDHC_XFERTYP_AC12EN_SHIFT)
+#define SDHC_BRD_XFERTYP_AC12EN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_AC12EN_SHIFT))
+
+/*! @brief Set the AC12EN field to a new value. */
+#define SDHC_WR_XFERTYP_AC12EN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_AC12EN_MASK, SDHC_XFERTYP_AC12EN(value)))
+#define SDHC_BWR_XFERTYP_AC12EN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_AC12EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
+ *
+ * Defines the direction of DAT line data transfers. The bit is set to 1 by the
+ * host driver to transfer data from the SD card to the SDHC and is set to 0 for
+ * all other commands.
+ *
+ * Values:
+ * - 0b0 - Write host to card.
+ * - 0b1 - Read card to host.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DTDSEL field. */
+#define SDHC_RD_XFERTYP_DTDSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DTDSEL_MASK) >> SDHC_XFERTYP_DTDSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_DTDSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DTDSEL_SHIFT))
+
+/*! @brief Set the DTDSEL field to a new value. */
+#define SDHC_WR_XFERTYP_DTDSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DTDSEL_MASK, SDHC_XFERTYP_DTDSEL(value)))
+#define SDHC_BWR_XFERTYP_DTDSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DTDSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
+ *
+ * Enables multiple block DAT line data transfers. For any other commands, this
+ * bit shall be set to 0. If this bit is 0, it is not necessary to set the block
+ * count register.
+ *
+ * Values:
+ * - 0b0 - Single block.
+ * - 0b1 - Multiple blocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_MSBSEL field. */
+#define SDHC_RD_XFERTYP_MSBSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_MSBSEL_MASK) >> SDHC_XFERTYP_MSBSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_MSBSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_MSBSEL_SHIFT))
+
+/*! @brief Set the MSBSEL field to a new value. */
+#define SDHC_WR_XFERTYP_MSBSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_MSBSEL_MASK, SDHC_XFERTYP_MSBSEL(value)))
+#define SDHC_BWR_XFERTYP_MSBSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_MSBSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
+ *
+ * Values:
+ * - 0b00 - No response.
+ * - 0b01 - Response length 136.
+ * - 0b10 - Response length 48.
+ * - 0b11 - Response length 48, check busy after response.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_RSPTYP field. */
+#define SDHC_RD_XFERTYP_RSPTYP(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_RSPTYP_MASK) >> SDHC_XFERTYP_RSPTYP_SHIFT)
+#define SDHC_BRD_XFERTYP_RSPTYP(base) (SDHC_RD_XFERTYP_RSPTYP(base))
+
+/*! @brief Set the RSPTYP field to a new value. */
+#define SDHC_WR_XFERTYP_RSPTYP(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_RSPTYP_MASK, SDHC_XFERTYP_RSPTYP(value)))
+#define SDHC_BWR_XFERTYP_RSPTYP(base, value) (SDHC_WR_XFERTYP_RSPTYP(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
+ *
+ * If this bit is set to 1, the SDHC shall check the CRC field in the response.
+ * If an error is detected, it is reported as a Command CRC Error. If this bit is
+ * set to 0, the CRC field is not checked. The number of bits checked by the CRC
+ * field value changes according to the length of the response.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CCCEN field. */
+#define SDHC_RD_XFERTYP_CCCEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CCCEN_MASK) >> SDHC_XFERTYP_CCCEN_SHIFT)
+#define SDHC_BRD_XFERTYP_CCCEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CCCEN_SHIFT))
+
+/*! @brief Set the CCCEN field to a new value. */
+#define SDHC_WR_XFERTYP_CCCEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CCCEN_MASK, SDHC_XFERTYP_CCCEN(value)))
+#define SDHC_BWR_XFERTYP_CCCEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CCCEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CICEN[20] (RW)
+ *
+ * If this bit is set to 1, the SDHC will check the index field in the response
+ * to see if it has the same value as the command index. If it is not, it is
+ * reported as a command index error. If this bit is set to 0, the index field is not
+ * checked.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CICEN field. */
+#define SDHC_RD_XFERTYP_CICEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CICEN_MASK) >> SDHC_XFERTYP_CICEN_SHIFT)
+#define SDHC_BRD_XFERTYP_CICEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CICEN_SHIFT))
+
+/*! @brief Set the CICEN field to a new value. */
+#define SDHC_WR_XFERTYP_CICEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CICEN_MASK, SDHC_XFERTYP_CICEN(value)))
+#define SDHC_BWR_XFERTYP_CICEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CICEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
+ *
+ * This bit is set to 1 to indicate that data is present and shall be
+ * transferred using the DAT line. It is set to 0 for the following: Commands using only
+ * the CMD line, for example: CMD52. Commands with no data transfer, but using the
+ * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
+ * this bit shall be set, and other bits in this register shall be set the same
+ * as when the transfer was initially launched. When the Write Protect switch is
+ * on, that is, the WPSPL bit is active as 0, any command with a write operation
+ * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
+ * 0, writes to the register Transfer Type are ignored.
+ *
+ * Values:
+ * - 0b0 - No data present.
+ * - 0b1 - Data present.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DPSEL field. */
+#define SDHC_RD_XFERTYP_DPSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DPSEL_MASK) >> SDHC_XFERTYP_DPSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_DPSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DPSEL_SHIFT))
+
+/*! @brief Set the DPSEL field to a new value. */
+#define SDHC_WR_XFERTYP_DPSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DPSEL_MASK, SDHC_XFERTYP_DPSEL(value)))
+#define SDHC_BWR_XFERTYP_DPSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DPSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
+ *
+ * There are three types of special commands: suspend, resume, and abort. These
+ * bits shall be set to 00b for all other commands. Suspend command: If the
+ * suspend command succeeds, the SDHC shall assume that the card bus has been released
+ * and that it is possible to issue the next command which uses the DAT line.
+ * Because the SDHC does not monitor the content of command response, it does not
+ * know if the suspend command succeeded or not. It is the host driver's
+ * responsibility to check the status of the suspend command and send another command
+ * marked as suspend to inform the SDHC that a suspend command was successfully
+ * issued. After the end bit of command is sent, the SDHC deasserts read wait for read
+ * transactions and stops checking busy for write transactions. In 4-bit mode,
+ * the interrupt cycle starts. If the suspend command fails, the SDHC will
+ * maintain its current state, and the host driver shall restart the transfer by setting
+ * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
+ * restoring the registers saved before sending the suspend command and then sends
+ * the resume command. The SDHC will check for a pending busy state before
+ * starting write transfers. Abort command: If this command is set when executing a
+ * read transfer, the SDHC will stop reads to the buffer. If this command is set
+ * when executing a write transfer, the SDHC will stop driving the DAT line. After
+ * issuing the abort command, the host driver must issue a software reset (abort
+ * transaction).
+ *
+ * Values:
+ * - 0b00 - Normal other commands.
+ * - 0b01 - Suspend CMD52 for writing bus suspend in CCCR.
+ * - 0b10 - Resume CMD52 for writing function select in CCCR.
+ * - 0b11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CMDTYP field. */
+#define SDHC_RD_XFERTYP_CMDTYP(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CMDTYP_MASK) >> SDHC_XFERTYP_CMDTYP_SHIFT)
+#define SDHC_BRD_XFERTYP_CMDTYP(base) (SDHC_RD_XFERTYP_CMDTYP(base))
+
+/*! @brief Set the CMDTYP field to a new value. */
+#define SDHC_WR_XFERTYP_CMDTYP(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CMDTYP_MASK, SDHC_XFERTYP_CMDTYP(value)))
+#define SDHC_BWR_XFERTYP_CMDTYP(base, value) (SDHC_WR_XFERTYP_CMDTYP(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
+ *
+ * These bits shall be set to the command number that is specified in bits 45-40
+ * of the command-format in the SD Memory Card Physical Layer Specification and
+ * SDIO Card Specification.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CMDINX field. */
+#define SDHC_RD_XFERTYP_CMDINX(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CMDINX_MASK) >> SDHC_XFERTYP_CMDINX_SHIFT)
+#define SDHC_BRD_XFERTYP_CMDINX(base) (SDHC_RD_XFERTYP_CMDINX(base))
+
+/*! @brief Set the CMDINX field to a new value. */
+#define SDHC_WR_XFERTYP_CMDINX(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CMDINX_MASK, SDHC_XFERTYP_CMDINX(value)))
+#define SDHC_BWR_XFERTYP_CMDINX(base, value) (SDHC_WR_XFERTYP_CMDINX(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_CMDRSP - Command Response 0
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_CMDRSP - Command Response 0 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 0 of the response bits from the card.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP register
+ */
+/*@{*/
+#define SDHC_RD_CMDRSP(base, index) (SDHC_CMDRSP_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_DATPORT - Buffer Data Port register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_DATPORT - Buffer Data Port register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This is a 32-bit data port register used to access the internal buffer and it
+ * cannot be updated in Idle mode.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_DATPORT register
+ */
+/*@{*/
+#define SDHC_RD_DATPORT(base)    (SDHC_DATPORT_REG(base))
+#define SDHC_WR_DATPORT(base, value) (SDHC_DATPORT_REG(base) = (value))
+#define SDHC_RMW_DATPORT(base, mask, value) (SDHC_WR_DATPORT(base, (SDHC_RD_DATPORT(base) & ~(mask)) | (value)))
+#define SDHC_SET_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) |  (value)))
+#define SDHC_CLR_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) & ~(value)))
+#define SDHC_TOG_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_PRSSTAT - Present State register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_PRSSTAT - Present State register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The host driver can get status of the SDHC from this 32-bit read-only
+ * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
+ * SDIO) when the DAT lines are busy during a data transfer. These commands can be
+ * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
+ * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
+ * Physical Specification may add other commands to this list in the future.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_PRSSTAT register
+ */
+/*@{*/
+#define SDHC_RD_PRSSTAT(base)    (SDHC_PRSSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_PRSSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
+ *
+ * If this status bit is 0, it indicates that the CMD line is not in use and the
+ * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
+ * immediately after the Transfer Type register is written. This bit is cleared when
+ * the command response is received. Even if the CDIHB bit is set to 1, Commands
+ * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
+ * generates a command complete interrupt in the interrupt status register. If the
+ * SDHC cannot issue the command because of a command conflict error (see
+ * command CRC error) or because of a command not issued by auto CMD12 error, this bit
+ * will remain 1 and the command complete is not set. The status of issuing an
+ * auto CMD12 does not show on this bit.
+ *
+ * Values:
+ * - 0b0 - Can issue command using only CMD line.
+ * - 0b1 - Cannot issue command.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CIHB field. */
+#define SDHC_RD_PRSSTAT_CIHB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CIHB_MASK) >> SDHC_PRSSTAT_CIHB_SHIFT)
+#define SDHC_BRD_PRSSTAT_CIHB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CIHB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
+ *
+ * This status bit is generated if either the DLA or the RTA is set to 1. If
+ * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
+ * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
+ * the case when the command busy is finished, changing from 1 to 0 generates a
+ * transfer complete interrupt in the Interrupt Status register. The SD host
+ * driver can save registers for a suspend transaction after this bit has changed
+ * from 1 to 0.
+ *
+ * Values:
+ * - 0b0 - Can issue command which uses the DAT line.
+ * - 0b1 - Cannot issue command which uses the DAT line.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CDIHB field. */
+#define SDHC_RD_PRSSTAT_CDIHB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CDIHB_MASK) >> SDHC_PRSSTAT_CDIHB_SHIFT)
+#define SDHC_BRD_PRSSTAT_CDIHB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CDIHB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLA[2] (RO)
+ *
+ * Indicates whether one of the DAT lines on the SD bus is in use. In the case
+ * of read transactions: This status indicates whether a read transfer is
+ * executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
+ * generates a block gap event interrupt in the Interrupt Status register. This bit
+ * will be set in either of the following cases: After the end bit of the read
+ * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
+ * will be cleared in either of the following cases: When the end bit of the last
+ * data block is sent from the SD bus to the SDHC. When the read wait state is
+ * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
+ * the next block gap by driving read wait at the start of the interrupt cycle.
+ * If the read wait signal is already driven (data buffer cannot receive data),
+ * the SDHC can wait for a current block gap by continuing to drive the read wait
+ * signal. It is necessary to support read wait to use the suspend / resume
+ * function. This bit will remain 1 during read wait. In the case of write
+ * transactions: This status indicates that a write transfer is executing on the SD bus.
+ * Changes in this value from 1 to 0 generate a transfer complete interrupt in the
+ * interrupt status register. This bit will be set in either of the following
+ * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
+ * continue a write transfer. This bit will be cleared in either of the
+ * following cases: When the SD card releases write busy of the last data block, the SDHC
+ * will also detect if the output is not busy. If the SD card does not drive the
+ * busy signal after the CRC status is received, the SDHC shall assume the card
+ * drive "Not busy". When the SD card releases write busy, prior to waiting for
+ * write transfer, and as a result of a stop at block gap request. In the case of
+ * command with busy pending: This status indicates that a busy state follows the
+ * command and the data line is in use. This bit will be cleared when the DAT0
+ * line is released.
+ *
+ * Values:
+ * - 0b0 - DAT line inactive.
+ * - 0b1 - DAT line active.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_DLA field. */
+#define SDHC_RD_PRSSTAT_DLA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_DLA_MASK) >> SDHC_PRSSTAT_DLA_SHIFT)
+#define SDHC_BRD_PRSSTAT_DLA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_DLA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
+ *
+ * Indicates that the internal card clock is stable. This bit is for the host
+ * driver to poll clock status when changing the clock frequency. It is recommended
+ * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
+ * frequency is changing.
+ *
+ * Values:
+ * - 0b0 - Clock is changing frequency and not stable.
+ * - 0b1 - Clock is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_SDSTB field. */
+#define SDHC_RD_PRSSTAT_SDSTB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_SDSTB_MASK) >> SDHC_PRSSTAT_SDSTB_SHIFT)
+#define SDHC_BRD_PRSSTAT_SDSTB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_SDSTB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
+ *
+ * Indicates that the bus clock is internally gated off. This bit is for the
+ * host driver to debug.
+ *
+ * Values:
+ * - 0b0 - Bus clock is active.
+ * - 0b1 - Bus clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field. */
+#define SDHC_RD_PRSSTAT_IPGOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_IPGOFF_MASK) >> SDHC_PRSSTAT_IPGOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_IPGOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_IPGOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
+ *
+ * Indicates that the system clock is internally gated off. This bit is for the
+ * host driver to debug during a data transfer.
+ *
+ * Values:
+ * - 0b0 - System clock is active.
+ * - 0b1 - System clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field. */
+#define SDHC_RD_PRSSTAT_HCKOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_HCKOFF_MASK) >> SDHC_PRSSTAT_HCKOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_HCKOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_HCKOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
+ *
+ * Indicates that the is internally gated off. This bit is for the host driver
+ * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
+ * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
+ * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
+ * clock SDHC clock bus clock
+ *
+ * Values:
+ * - 0b0 - SDHC clock is active.
+ * - 0b1 - SDHC clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_PEROFF field. */
+#define SDHC_RD_PRSSTAT_PEROFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_PEROFF_MASK) >> SDHC_PRSSTAT_PEROFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_PEROFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_PEROFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
+ *
+ * Indicates that the SD clock is internally gated off, because of buffer
+ * over/under-run or read pause without read wait assertion, or the driver has cleared
+ * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
+ * data transaction on the SD bus.
+ *
+ * Values:
+ * - 0b0 - SD clock is active.
+ * - 0b1 - SD clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_SDOFF field. */
+#define SDHC_RD_PRSSTAT_SDOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_SDOFF_MASK) >> SDHC_PRSSTAT_SDOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_SDOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_SDOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field WTA[8] (RO)
+ *
+ * Indicates that a write transfer is active. If this bit is 0, it means no
+ * valid write data exists in the SDHC. This bit is set in either of the following
+ * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
+ * restart a write transfer. This bit is cleared in either of the following
+ * cases: After getting the CRC status of the last data block as specified by the
+ * transfer count (single and multiple). After getting the CRC status of any block
+ * where data transmission is about to be stopped by a stop at block gap request.
+ * During a write transaction, a block gap event interrupt is generated when this
+ * bit is changed to 0, as result of the stop at block gap request being set.
+ * This status is useful for the host driver in determining when to issue commands
+ * during write busy state.
+ *
+ * Values:
+ * - 0b0 - No valid data.
+ * - 0b1 - Transferring data.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_WTA field. */
+#define SDHC_RD_PRSSTAT_WTA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_WTA_MASK) >> SDHC_PRSSTAT_WTA_SHIFT)
+#define SDHC_BRD_PRSSTAT_WTA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_WTA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field RTA[9] (RO)
+ *
+ * Used for detecting completion of a read transfer. This bit is set for either
+ * of the following conditions: After the end bit of the read command. When
+ * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
+ * interrupt is generated when this bit changes to 0. This bit is cleared for either of
+ * the following conditions: When the last data block as specified by block
+ * length is transferred to the system, that is, all data are read away from SDHC
+ * internal buffer. When all valid data blocks have been transferred from SDHC
+ * internal buffer to the system and no current block transfers are being sent as a
+ * result of the stop at block gap request being set to 1.
+ *
+ * Values:
+ * - 0b0 - No valid data.
+ * - 0b1 - Transferring data.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_RTA field. */
+#define SDHC_RD_PRSSTAT_RTA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_RTA_MASK) >> SDHC_PRSSTAT_RTA_SHIFT)
+#define SDHC_BRD_PRSSTAT_RTA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_RTA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
+ *
+ * Used for non-DMA write transfers. The SDHC can implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates whether space is
+ * available for write data. If this bit is 1, valid data greater than the watermark
+ * level can be written to the buffer. This read-only flag indicates whether
+ * space is available for write data.
+ *
+ * Values:
+ * - 0b0 - Write disable, the buffer can hold valid data less than the write
+ *     watermark level.
+ * - 0b1 - Write enable, the buffer can hold valid data greater than the write
+ *     watermark level.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_BWEN field. */
+#define SDHC_RD_PRSSTAT_BWEN(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_BWEN_MASK) >> SDHC_PRSSTAT_BWEN_SHIFT)
+#define SDHC_BRD_PRSSTAT_BWEN(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_BWEN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BREN[11] (RO)
+ *
+ * Used for non-DMA read transfers. The SDHC may implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates that valid data exists
+ * in the host side buffer. If this bit is high, valid data greater than the
+ * watermark level exist in the buffer. This read-only flag indicates that valid
+ * data exists in the host side buffer.
+ *
+ * Values:
+ * - 0b0 - Read disable, valid data less than the watermark level exist in the
+ *     buffer.
+ * - 0b1 - Read enable, valid data greater than the watermark level exist in the
+ *     buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_BREN field. */
+#define SDHC_RD_PRSSTAT_BREN(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_BREN_MASK) >> SDHC_PRSSTAT_BREN_SHIFT)
+#define SDHC_BRD_PRSSTAT_BREN(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_BREN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CINS[16] (RO)
+ *
+ * Indicates whether a card has been inserted. The SDHC debounces this signal so
+ * that the host driver will not need to wait for it to stabilize. Changing from
+ * a 0 to 1 generates a card insertion interrupt in the Interrupt Status
+ * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
+ * Status register. A write to the force event register does not effect this bit.
+ * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
+ * bit.
+ *
+ * Values:
+ * - 0b0 - Power on reset or no card.
+ * - 0b1 - Card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CINS field. */
+#define SDHC_RD_PRSSTAT_CINS(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CINS_MASK) >> SDHC_PRSSTAT_CINS_SHIFT)
+#define SDHC_BRD_PRSSTAT_CINS(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CINS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
+ *
+ * Used to check the CMD line level to recover from errors, and for debugging.
+ * The reset value is effected by the external pullup/pulldown resistor, by
+ * default, the read value of this bit after reset is 1b, when the command line is
+ * pulled up.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CLSL field. */
+#define SDHC_RD_PRSSTAT_CLSL(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CLSL_MASK) >> SDHC_PRSSTAT_CLSL_SHIFT)
+#define SDHC_BRD_PRSSTAT_CLSL(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CLSL_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
+ *
+ * Used to check the DAT line level to recover from errors, and for debugging.
+ * This is especially useful in detecting the busy signal level from DAT[0]. The
+ * reset value is effected by the external pullup/pulldown resistors. By default,
+ * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
+ * down and the other lines are pulled up.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_DLSL field. */
+#define SDHC_RD_PRSSTAT_DLSL(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_DLSL_MASK) >> SDHC_PRSSTAT_DLSL_SHIFT)
+#define SDHC_BRD_PRSSTAT_DLSL(base) (SDHC_RD_PRSSTAT_DLSL(base))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_PROCTL - Protocol Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_PROCTL - Protocol Control register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * There are three cases to restart the transfer after stop at the block gap.
+ * Which case is appropriate depends on whether the SDHC issues a suspend command
+ * or the SD card accepts the suspend command: If the host driver does not issue a
+ * suspend command, the continue request shall be used to restart the transfer.
+ * If the host driver issues a suspend command and the SD card accepts it, a
+ * resume command shall be used to restart the transfer. If the host driver issues a
+ * suspend command and the SD card does not accept it, the continue request shall
+ * be used to restart the transfer. Any time stop at block gap request stops the
+ * data transfer, the host driver shall wait for a transfer complete (in the
+ * interrupt status register), before attempting to restart the transfer. When
+ * restarting the data transfer by continue request, the host driver shall clear the
+ * stop at block gap request before or simultaneously.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_PROCTL register
+ */
+/*@{*/
+#define SDHC_RD_PROCTL(base)     (SDHC_PROCTL_REG(base))
+#define SDHC_WR_PROCTL(base, value) (SDHC_PROCTL_REG(base) = (value))
+#define SDHC_RMW_PROCTL(base, mask, value) (SDHC_WR_PROCTL(base, (SDHC_RD_PROCTL(base) & ~(mask)) | (value)))
+#define SDHC_SET_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) |  (value)))
+#define SDHC_CLR_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) & ~(value)))
+#define SDHC_TOG_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_PROCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_PROCTL, field LCTL[0] (RW)
+ *
+ * This bit, fully controlled by the host driver, is used to caution the user
+ * not to remove the card while the card is being accessed. If the software is
+ * going to issue multiple SD commands, this bit can be set during all these
+ * transactions. It is not necessary to change for each transaction. When the software
+ * issues multiple SD commands, setting the bit once before the first command is
+ * sufficient: it is not necessary to reset the bit between commands.
+ *
+ * Values:
+ * - 0b0 - LED off.
+ * - 0b1 - LED on.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_LCTL field. */
+#define SDHC_RD_PROCTL_LCTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_LCTL_MASK) >> SDHC_PROCTL_LCTL_SHIFT)
+#define SDHC_BRD_PROCTL_LCTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_LCTL_SHIFT))
+
+/*! @brief Set the LCTL field to a new value. */
+#define SDHC_WR_PROCTL_LCTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_LCTL_MASK, SDHC_PROCTL_LCTL(value)))
+#define SDHC_BWR_PROCTL_LCTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_LCTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field DTW[2:1] (RW)
+ *
+ * Selects the data width of the SD bus for a data transfer. The host driver
+ * shall set it to match the data width of the card. Possible data transfer width is
+ * 1-bit, 4-bits or 8-bits.
+ *
+ * Values:
+ * - 0b00 - 1-bit mode
+ * - 0b01 - 4-bit mode
+ * - 0b10 - 8-bit mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_DTW field. */
+#define SDHC_RD_PROCTL_DTW(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_DTW_MASK) >> SDHC_PROCTL_DTW_SHIFT)
+#define SDHC_BRD_PROCTL_DTW(base) (SDHC_RD_PROCTL_DTW(base))
+
+/*! @brief Set the DTW field to a new value. */
+#define SDHC_WR_PROCTL_DTW(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_DTW_MASK, SDHC_PROCTL_DTW(value)))
+#define SDHC_BWR_PROCTL_DTW(base, value) (SDHC_WR_PROCTL_DTW(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field D3CD[3] (RW)
+ *
+ * If this bit is set, DAT3 should be pulled down to act as a card detection
+ * pin. Be cautious when using this feature, because DAT3 is also a chip-select for
+ * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
+ * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
+ * is used.
+ *
+ * Values:
+ * - 0b0 - DAT3 does not monitor card Insertion.
+ * - 0b1 - DAT3 as card detection pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_D3CD field. */
+#define SDHC_RD_PROCTL_D3CD(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_D3CD_MASK) >> SDHC_PROCTL_D3CD_SHIFT)
+#define SDHC_BRD_PROCTL_D3CD(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_D3CD_SHIFT))
+
+/*! @brief Set the D3CD field to a new value. */
+#define SDHC_WR_PROCTL_D3CD(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_D3CD_MASK, SDHC_PROCTL_D3CD(value)))
+#define SDHC_BWR_PROCTL_D3CD(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_D3CD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
+ *
+ * The SDHC supports all four endian modes in data transfer.
+ *
+ * Values:
+ * - 0b00 - Big endian mode
+ * - 0b01 - Half word big endian mode
+ * - 0b10 - Little endian mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_EMODE field. */
+#define SDHC_RD_PROCTL_EMODE(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_EMODE_MASK) >> SDHC_PROCTL_EMODE_SHIFT)
+#define SDHC_BRD_PROCTL_EMODE(base) (SDHC_RD_PROCTL_EMODE(base))
+
+/*! @brief Set the EMODE field to a new value. */
+#define SDHC_WR_PROCTL_EMODE(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_EMODE_MASK, SDHC_PROCTL_EMODE(value)))
+#define SDHC_BWR_PROCTL_EMODE(base, value) (SDHC_WR_PROCTL_EMODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CDTL[6] (RW)
+ *
+ * Enabled while the CDSS is set to 1 and it indicates card insertion.
+ *
+ * Values:
+ * - 0b0 - Card detect test level is 0, no card inserted.
+ * - 0b1 - Card detect test level is 1, card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CDTL field. */
+#define SDHC_RD_PROCTL_CDTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CDTL_MASK) >> SDHC_PROCTL_CDTL_SHIFT)
+#define SDHC_BRD_PROCTL_CDTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDTL_SHIFT))
+
+/*! @brief Set the CDTL field to a new value. */
+#define SDHC_WR_PROCTL_CDTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CDTL_MASK, SDHC_PROCTL_CDTL(value)))
+#define SDHC_BWR_PROCTL_CDTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CDSS[7] (RW)
+ *
+ * Selects the source for the card detection.
+ *
+ * Values:
+ * - 0b0 - Card detection level is selected for normal purpose.
+ * - 0b1 - Card detection test level is selected for test purpose.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CDSS field. */
+#define SDHC_RD_PROCTL_CDSS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CDSS_MASK) >> SDHC_PROCTL_CDSS_SHIFT)
+#define SDHC_BRD_PROCTL_CDSS(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDSS_SHIFT))
+
+/*! @brief Set the CDSS field to a new value. */
+#define SDHC_WR_PROCTL_CDSS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CDSS_MASK, SDHC_PROCTL_CDSS(value)))
+#define SDHC_BWR_PROCTL_CDSS(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDSS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
+ *
+ * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
+ * operation.
+ *
+ * Values:
+ * - 0b00 - No DMA or simple DMA is selected.
+ * - 0b01 - ADMA1 is selected.
+ * - 0b10 - ADMA2 is selected.
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_DMAS field. */
+#define SDHC_RD_PROCTL_DMAS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT)
+#define SDHC_BRD_PROCTL_DMAS(base) (SDHC_RD_PROCTL_DMAS(base))
+
+/*! @brief Set the DMAS field to a new value. */
+#define SDHC_WR_PROCTL_DMAS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_DMAS_MASK, SDHC_PROCTL_DMAS(value)))
+#define SDHC_BWR_PROCTL_DMAS(base, value) (SDHC_WR_PROCTL_DMAS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
+ *
+ * Used to stop executing a transaction at the next block gap for both DMA and
+ * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
+ * transfer completion, the host driver shall leave this bit set to 1. Clearing both
+ * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
+ * Wait is used to stop the read transaction at the block gap. The SDHC will
+ * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
+ * that SDIO card support read wait. Therefore, the host driver shall not set
+ * this bit during read transfers unless the SDIO card supports read wait and has
+ * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
+ * the read operation during block gap. In the case of write transfers in which
+ * the host driver writes data to the data port register, the host driver shall set
+ * this bit after all block data is written. If this bit is set to 1, the host
+ * driver shall not write data to the Data Port register after a block is sent.
+ * Once this bit is set, the host driver shall not clear this bit before
+ * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
+ * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
+ *
+ * Values:
+ * - 0b0 - Transfer
+ * - 0b1 - Stop
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_SABGREQ field. */
+#define SDHC_RD_PROCTL_SABGREQ(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_SABGREQ_MASK) >> SDHC_PROCTL_SABGREQ_SHIFT)
+#define SDHC_BRD_PROCTL_SABGREQ(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_SABGREQ_SHIFT))
+
+/*! @brief Set the SABGREQ field to a new value. */
+#define SDHC_WR_PROCTL_SABGREQ(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_SABGREQ_MASK, SDHC_PROCTL_SABGREQ(value)))
+#define SDHC_BWR_PROCTL_SABGREQ(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_SABGREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CREQ[17] (RW)
+ *
+ * Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
+ * When a suspend operation is not accepted by the card, it is also by setting this
+ * bit to restart the paused transfer. To cancel stop at the block gap, set
+ * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
+ * automatically clears this bit, therefore it is not necessary for the host driver to
+ * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
+ * request is ignored.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Restart
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CREQ field. */
+#define SDHC_RD_PROCTL_CREQ(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CREQ_MASK) >> SDHC_PROCTL_CREQ_SHIFT)
+#define SDHC_BRD_PROCTL_CREQ(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CREQ_SHIFT))
+
+/*! @brief Set the CREQ field to a new value. */
+#define SDHC_WR_PROCTL_CREQ(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CREQ_MASK, SDHC_PROCTL_CREQ(value)))
+#define SDHC_BWR_PROCTL_CREQ(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field RWCTL[18] (RW)
+ *
+ * The read wait function is optional for SDIO cards. If the card supports read
+ * wait, set this bit to enable use of the read wait protocol to stop read data
+ * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
+ * read data, which restricts commands generation. When the host driver detects an
+ * SDIO card insertion, it shall set this bit according to the CCCR of the card.
+ * If the card does not support read wait, this bit shall never be set to 1,
+ * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
+ * during read operation is also supported, but the SDHC will stop the SD Clock
+ * to pause reading operation.
+ *
+ * Values:
+ * - 0b0 - Disable read wait control, and stop SD clock at block gap when
+ *     SABGREQ is set.
+ * - 0b1 - Enable read wait control, and assert read wait without stopping SD
+ *     clock at block gap when SABGREQ bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_RWCTL field. */
+#define SDHC_RD_PROCTL_RWCTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_RWCTL_MASK) >> SDHC_PROCTL_RWCTL_SHIFT)
+#define SDHC_BRD_PROCTL_RWCTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_RWCTL_SHIFT))
+
+/*! @brief Set the RWCTL field to a new value. */
+#define SDHC_WR_PROCTL_RWCTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_RWCTL_MASK, SDHC_PROCTL_RWCTL(value)))
+#define SDHC_BWR_PROCTL_RWCTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_RWCTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field IABG[19] (RW)
+ *
+ * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
+ * interrupt cycle. Setting to 1 enables interrupt detection at the block gap
+ * for a multiple block transfer. Setting to 0 disables interrupt detection during
+ * a multiple block transfer. If the SDIO card can't signal an interrupt during a
+ * multiple block transfer, this bit must be set to 0 to avoid an inadvertent
+ * interrupt. When the host driver detects an SDIO card insertion, it shall set
+ * this bit according to the CCCR of the card.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_IABG field. */
+#define SDHC_RD_PROCTL_IABG(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_IABG_MASK) >> SDHC_PROCTL_IABG_SHIFT)
+#define SDHC_BRD_PROCTL_IABG(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_IABG_SHIFT))
+
+/*! @brief Set the IABG field to a new value. */
+#define SDHC_WR_PROCTL_IABG(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_IABG_MASK, SDHC_PROCTL_IABG(value)))
+#define SDHC_BWR_PROCTL_IABG(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_IABG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINT[24] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
+ * (Wake Up Support) in CIS is set to 1. When this bit is set, the card
+ * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
+ * the wakeup feature is not enabled, the SD_CLK must be active to assert the
+ * card interrupt status and the SDHC interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECINT field. */
+#define SDHC_RD_PROCTL_WECINT(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECINT_MASK) >> SDHC_PROCTL_WECINT_SHIFT)
+#define SDHC_BRD_PROCTL_WECINT(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINT_SHIFT))
+
+/*! @brief Set the WECINT field to a new value. */
+#define SDHC_WR_PROCTL_WECINT(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECINT_MASK, SDHC_PROCTL_WECINT(value)))
+#define SDHC_BWR_PROCTL_WECINT(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINS[25] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
+ * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
+ * interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECINS field. */
+#define SDHC_RD_PROCTL_WECINS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECINS_MASK) >> SDHC_PROCTL_WECINS_SHIFT)
+#define SDHC_BRD_PROCTL_WECINS(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINS_SHIFT))
+
+/*! @brief Set the WECINS field to a new value. */
+#define SDHC_WR_PROCTL_WECINS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECINS_MASK, SDHC_PROCTL_WECINS(value)))
+#define SDHC_BWR_PROCTL_WECINS(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECRM[26] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
+ * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECRM field. */
+#define SDHC_RD_PROCTL_WECRM(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECRM_MASK) >> SDHC_PROCTL_WECRM_SHIFT)
+#define SDHC_BRD_PROCTL_WECRM(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECRM_SHIFT))
+
+/*! @brief Set the WECRM field to a new value. */
+#define SDHC_WR_PROCTL_WECRM(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECRM_MASK, SDHC_PROCTL_WECRM(value)))
+#define SDHC_BWR_PROCTL_WECRM(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECRM_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_SYSCTL - System Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_SYSCTL - System Control register (RW)
+ *
+ * Reset value: 0x00008008U
+ */
+/*!
+ * @name Constants and macros for entire SDHC_SYSCTL register
+ */
+/*@{*/
+#define SDHC_RD_SYSCTL(base)     (SDHC_SYSCTL_REG(base))
+#define SDHC_WR_SYSCTL(base, value) (SDHC_SYSCTL_REG(base) = (value))
+#define SDHC_RMW_SYSCTL(base, mask, value) (SDHC_WR_SYSCTL(base, (SDHC_RD_SYSCTL(base) & ~(mask)) | (value)))
+#define SDHC_SET_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) |  (value)))
+#define SDHC_CLR_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) & ~(value)))
+#define SDHC_TOG_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_SYSCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
+ *
+ * If this bit is set, bus clock will always be active and no automatic gating
+ * is applied. The bus clock will be internally gated off, if none of the
+ * following factors are met: The cmd part is reset, or Data part is reset, or Soft
+ * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
+ * request is just set, or This bit is set, or Card insertion is detected, or Card
+ * removal is detected, or Card external interrupt is detected, or The SDHC
+ * clock is not gated off The bus clock will not be auto gated off if the SDHC clock
+ * is not gated off. So clearing only this bit has no effect unless the PEREN bit
+ * is also cleared.
+ *
+ * Values:
+ * - 0b0 - Bus clock will be internally gated off.
+ * - 0b1 - Bus clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_IPGEN field. */
+#define SDHC_RD_SYSCTL_IPGEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_IPGEN_MASK) >> SDHC_SYSCTL_IPGEN_SHIFT)
+#define SDHC_BRD_SYSCTL_IPGEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_IPGEN_SHIFT))
+
+/*! @brief Set the IPGEN field to a new value. */
+#define SDHC_WR_SYSCTL_IPGEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_IPGEN_MASK, SDHC_SYSCTL_IPGEN(value)))
+#define SDHC_BWR_SYSCTL_IPGEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_IPGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
+ *
+ * If this bit is set, system clock will always be active and no automatic
+ * gating is applied. When this bit is cleared, system clock will be automatically off
+ * when no data transfer is on the SD bus.
+ *
+ * Values:
+ * - 0b0 - System clock will be internally gated off.
+ * - 0b1 - System clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_HCKEN field. */
+#define SDHC_RD_SYSCTL_HCKEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_HCKEN_MASK) >> SDHC_SYSCTL_HCKEN_SHIFT)
+#define SDHC_BRD_SYSCTL_HCKEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_HCKEN_SHIFT))
+
+/*! @brief Set the HCKEN field to a new value. */
+#define SDHC_WR_SYSCTL_HCKEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_HCKEN_MASK, SDHC_SYSCTL_HCKEN(value)))
+#define SDHC_BWR_SYSCTL_HCKEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_HCKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field PEREN[2] (RW)
+ *
+ * If this bit is set, SDHC clock will always be active and no automatic gating
+ * is applied. Thus the SDCLK is active except for when auto gating-off during
+ * buffer danger (buffer about to over-run or under-run). When this bit is cleared,
+ * the SDHC clock will be automatically off whenever there is no transaction on
+ * the SD bus. Because this bit is only a feature enabling bit, clearing this bit
+ * does not stop SDCLK immediately. The SDHC clock will be internally gated off,
+ * if none of the following factors are met: The cmd part is reset, or Data part
+ * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
+ * just updated, or Continue request is just set, or This bit is set, or Card
+ * insertion is detected, or Card removal is detected, or Card external interrupt is
+ * detected, or 80 clocks for initialization phase is ongoing
+ *
+ * Values:
+ * - 0b0 - SDHC clock will be internally gated off.
+ * - 0b1 - SDHC clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_PEREN field. */
+#define SDHC_RD_SYSCTL_PEREN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_PEREN_MASK) >> SDHC_SYSCTL_PEREN_SHIFT)
+#define SDHC_BRD_SYSCTL_PEREN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_PEREN_SHIFT))
+
+/*! @brief Set the PEREN field to a new value. */
+#define SDHC_WR_SYSCTL_PEREN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_PEREN_MASK, SDHC_SYSCTL_PEREN(value)))
+#define SDHC_BWR_SYSCTL_PEREN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_PEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
+ *
+ * The host controller shall stop SDCLK when writing this bit to 0. SDCLK
+ * frequency can be changed when this bit is 0. Then, the host controller shall
+ * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
+ * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
+ * power.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field. */
+#define SDHC_RD_SYSCTL_SDCLKEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_SDCLKEN_MASK) >> SDHC_SYSCTL_SDCLKEN_SHIFT)
+#define SDHC_BRD_SYSCTL_SDCLKEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_SDCLKEN_SHIFT))
+
+/*! @brief Set the SDCLKEN field to a new value. */
+#define SDHC_WR_SYSCTL_SDCLKEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_SDCLKEN_MASK, SDHC_SYSCTL_SDCLKEN(value)))
+#define SDHC_BWR_SYSCTL_SDCLKEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_SDCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
+ *
+ * Used to provide a more exact divisor to generate the desired SD clock
+ * frequency. Note the divider can even support odd divisor without deterioration of
+ * duty cycle. The setting are as following:
+ *
+ * Values:
+ * - 0b0000 - Divisor by 1.
+ * - 0b0001 - Divisor by 2.
+ * - 0b1110 - Divisor by 15.
+ * - 0b1111 - Divisor by 16.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_DVS field. */
+#define SDHC_RD_SYSCTL_DVS(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_DVS_MASK) >> SDHC_SYSCTL_DVS_SHIFT)
+#define SDHC_BRD_SYSCTL_DVS(base) (SDHC_RD_SYSCTL_DVS(base))
+
+/*! @brief Set the DVS field to a new value. */
+#define SDHC_WR_SYSCTL_DVS(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_DVS_MASK, SDHC_SYSCTL_DVS(value)))
+#define SDHC_BWR_SYSCTL_DVS(base, value) (SDHC_WR_SYSCTL_DVS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
+ *
+ * Used to select the frequency of the SDCLK pin. The frequency is not
+ * programmed directly. Rather this register holds the prescaler (this register) and
+ * divisor (next register) of the base clock frequency register. Setting 00h bypasses
+ * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
+ * behavior of this prescaler is undefined. The two default divider values can
+ * be calculated by the frequency of SDHC clock and the following divisor bits.
+ * The frequency of SDCLK is set by the following formula: Clock frequency = (Base
+ * clock) / (prescaler x divisor) For example, if the base clock frequency is 96
+ * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
+ * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
+ * less than or equal to the target. Similarly, to approach a clock value of 400
+ * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
+ * value of 400 kHz. The reset value of this field is 80h, so if the input base
+ * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
+ * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
+ * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
+ * never exceed this limit. Only the following settings are allowed:
+ *
+ * Values:
+ * - 0b00000001 - Base clock divided by 2.
+ * - 0b00000010 - Base clock divided by 4.
+ * - 0b00000100 - Base clock divided by 8.
+ * - 0b00001000 - Base clock divided by 16.
+ * - 0b00010000 - Base clock divided by 32.
+ * - 0b00100000 - Base clock divided by 64.
+ * - 0b01000000 - Base clock divided by 128.
+ * - 0b10000000 - Base clock divided by 256.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field. */
+#define SDHC_RD_SYSCTL_SDCLKFS(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_SDCLKFS_MASK) >> SDHC_SYSCTL_SDCLKFS_SHIFT)
+#define SDHC_BRD_SYSCTL_SDCLKFS(base) (SDHC_RD_SYSCTL_SDCLKFS(base))
+
+/*! @brief Set the SDCLKFS field to a new value. */
+#define SDHC_WR_SYSCTL_SDCLKFS(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_SDCLKFS_MASK, SDHC_SYSCTL_SDCLKFS(value)))
+#define SDHC_BWR_SYSCTL_SDCLKFS(base, value) (SDHC_WR_SYSCTL_SDCLKFS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
+ *
+ * Determines the interval by which DAT line timeouts are detected. See
+ * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
+ * clock frequency will be generated by dividing the base clock SDCLK value by this
+ * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
+ * time-out events.
+ *
+ * Values:
+ * - 0b0000 - SDCLK x 2 13
+ * - 0b0001 - SDCLK x 2 14
+ * - 0b1110 - SDCLK x 2 27
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_DTOCV field. */
+#define SDHC_RD_SYSCTL_DTOCV(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_DTOCV_MASK) >> SDHC_SYSCTL_DTOCV_SHIFT)
+#define SDHC_BRD_SYSCTL_DTOCV(base) (SDHC_RD_SYSCTL_DTOCV(base))
+
+/*! @brief Set the DTOCV field to a new value. */
+#define SDHC_WR_SYSCTL_DTOCV(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_DTOCV_MASK, SDHC_SYSCTL_DTOCV(value)))
+#define SDHC_BWR_SYSCTL_DTOCV(base, value) (SDHC_WR_SYSCTL_DTOCV(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
+ *
+ * Effects the entire host controller except for the card detection circuit.
+ * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
+ * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
+ * reset this bit to 0 when the capabilities registers are valid and the host driver
+ * can read them. Additional use of software reset for all does not affect the
+ * value of the capabilities registers. After this bit is set, it is recommended
+ * that the host driver reset the external card and reinitialize it.
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define SDHC_WR_SYSCTL_RSTA(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTA_MASK, SDHC_SYSCTL_RSTA(value)))
+#define SDHC_BWR_SYSCTL_RSTA(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
+ *
+ * Only part of the command circuit is reset. The following registers and bits
+ * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTC field to a new value. */
+#define SDHC_WR_SYSCTL_RSTC(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTC_MASK, SDHC_SYSCTL_RSTC(value)))
+#define SDHC_BWR_SYSCTL_RSTC(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
+ *
+ * Only part of the data circuit is reset. DMA circuit is also reset. The
+ * following registers and bits are cleared by this bit: Data Port register Buffer Is
+ * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
+ * Enable Read Transfer Active Write Transfer Active DAT Line Active Command
+ * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
+ * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
+ * Block Gap Event Transfer Complete
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTD field to a new value. */
+#define SDHC_WR_SYSCTL_RSTD(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTD_MASK, SDHC_SYSCTL_RSTD(value)))
+#define SDHC_BWR_SYSCTL_RSTD(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field INITA[27] (RW)
+ *
+ * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
+ * are sent, this bit is self-cleared. This bit is very useful during the card
+ * power-up period when 74 SD-clocks are needed and the clock auto gating feature
+ * is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
+ * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
+ * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
+ * when command line or data lines are active, write to this bit is not allowed.
+ * On the otherhand, when this bit is set, that is, during intialization active
+ * period, it is allowed to issue command, and the command bit stream will appear
+ * on the CMD pad after all 80 clock cycles are done. So when this command ends,
+ * the driver can make sure the 80 clock cycles are sent out. This is very useful
+ * when the driver needs send 80 cycles to the card and does not want to wait
+ * till this bit is self-cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_INITA field. */
+#define SDHC_RD_SYSCTL_INITA(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_INITA_MASK) >> SDHC_SYSCTL_INITA_SHIFT)
+#define SDHC_BRD_SYSCTL_INITA(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_INITA_SHIFT))
+
+/*! @brief Set the INITA field to a new value. */
+#define SDHC_WR_SYSCTL_INITA(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_INITA_MASK, SDHC_SYSCTL_INITA(value)))
+#define SDHC_BWR_SYSCTL_INITA(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_INITA_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSTAT - Interrupt Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * An interrupt is generated when the Normal Interrupt Signal Enable is enabled
+ * and at least one of the status bits is set to 1. For all bits, writing 1 to a
+ * bit clears it; writing to 0 keeps the bit unchanged. More than one status can
+ * be cleared with a single register write. For Card Interrupt, before writing 1
+ * to clear, it is required that the card stops asserting the interrupt, meaning
+ * that when the Card Driver services the interrupt condition, otherwise the CINT
+ * bit will be asserted again. The table below shows the relationship between
+ * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
+ * complete Command timeout error Meaning of the status 0 0 X X 1 Response not
+ * received within 64 SDCLK cycles 1 0 Response received The table below shows the
+ * relationship between the Transfer Complete and the Data Timeout Error. SDHC status
+ * for data timeout error/transfer complete bit combinations Transfer complete
+ * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
+ * transfer 1 X Data transfer complete The table below shows the relationship between
+ * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
+ * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
+ * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
+ * CMD line conflict
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTAT register
+ */
+/*@{*/
+#define SDHC_RD_IRQSTAT(base)    (SDHC_IRQSTAT_REG(base))
+#define SDHC_WR_IRQSTAT(base, value) (SDHC_IRQSTAT_REG(base) = (value))
+#define SDHC_RMW_IRQSTAT(base, mask, value) (SDHC_WR_IRQSTAT(base, (SDHC_RD_IRQSTAT(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) |  (value)))
+#define SDHC_CLR_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) & ~(value)))
+#define SDHC_TOG_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CC[0] (W1C)
+ *
+ * This bit is set when you receive the end bit of the command response, except
+ * Auto CMD12. See PRSSTAT[CIHB].
+ *
+ * Values:
+ * - 0b0 - Command not complete.
+ * - 0b1 - Command complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CC field. */
+#define SDHC_RD_IRQSTAT_CC(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CC_MASK) >> SDHC_IRQSTAT_CC_SHIFT)
+#define SDHC_BRD_IRQSTAT_CC(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CC_SHIFT))
+
+/*! @brief Set the CC field to a new value. */
+#define SDHC_WR_IRQSTAT_CC(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CC(value)))
+#define SDHC_BWR_IRQSTAT_CC(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field TC[1] (W1C)
+ *
+ * This bit is set when a read or write transfer is completed. In the case of a
+ * read transaction: This bit is set at the falling edge of the read transfer
+ * active status. There are two cases in which this interrupt is generated. The
+ * first is when a data transfer is completed as specified by the data length, after
+ * the last data has been read to the host system. The second is when data has
+ * stopped at the block gap and completed the data transfer by setting
+ * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
+ * transaction: This bit is set at the falling edge of the DAT line active
+ * status. There are two cases in which this interrupt is generated. The first is when
+ * the last data is written to the SD card as specified by the data length and
+ * the busy signal is released. The second is when data transfers are stopped at
+ * the block gap, by setting PROCTL[SABGREQ], and the data transfers are
+ * completed,after valid data is written to the SD card and the busy signal released.
+ *
+ * Values:
+ * - 0b0 - Transfer not complete.
+ * - 0b1 - Transfer complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_TC field. */
+#define SDHC_RD_IRQSTAT_TC(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_TC_MASK) >> SDHC_IRQSTAT_TC_SHIFT)
+#define SDHC_BRD_IRQSTAT_TC(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_TC_SHIFT))
+
+/*! @brief Set the TC field to a new value. */
+#define SDHC_WR_IRQSTAT_TC(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_TC(value)))
+#define SDHC_BWR_IRQSTAT_TC(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_TC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
+ *
+ * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
+ * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
+ * set to 1. In the case of a read transaction: This bit is set at the falling
+ * edge of the DAT line active status, when the transaction is stopped at SD Bus
+ * timing. The read wait must be supported in order to use this function. In the
+ * case of write transaction: This bit is set at the falling edge of write transfer
+ * active status, after getting CRC status at SD bus timing.
+ *
+ * Values:
+ * - 0b0 - No block gap event.
+ * - 0b1 - Transaction stopped at block gap.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BGE field. */
+#define SDHC_RD_IRQSTAT_BGE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BGE_MASK) >> SDHC_IRQSTAT_BGE_SHIFT)
+#define SDHC_BRD_IRQSTAT_BGE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BGE_SHIFT))
+
+/*! @brief Set the BGE field to a new value. */
+#define SDHC_WR_IRQSTAT_BGE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BGE(value)))
+#define SDHC_BWR_IRQSTAT_BGE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
+ *
+ * Occurs only when the internal DMA finishes the data transfer successfully.
+ * Whenever errors occur during data transfer, this bit will not be set. Instead,
+ * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
+ * this bit will be set.
+ *
+ * Values:
+ * - 0b0 - No DMA Interrupt.
+ * - 0b1 - DMA Interrupt is generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DINT field. */
+#define SDHC_RD_IRQSTAT_DINT(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DINT_MASK) >> SDHC_IRQSTAT_DINT_SHIFT)
+#define SDHC_BRD_IRQSTAT_DINT(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DINT_SHIFT))
+
+/*! @brief Set the DINT field to a new value. */
+#define SDHC_WR_IRQSTAT_DINT(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DINT(value)))
+#define SDHC_BWR_IRQSTAT_DINT(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
+ *
+ * This status bit is set if the Buffer Write Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0b0 - Not ready to write buffer.
+ * - 0b1 - Ready to write buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BWR field. */
+#define SDHC_RD_IRQSTAT_BWR(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BWR_MASK) >> SDHC_IRQSTAT_BWR_SHIFT)
+#define SDHC_BRD_IRQSTAT_BWR(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BWR_SHIFT))
+
+/*! @brief Set the BWR field to a new value. */
+#define SDHC_WR_IRQSTAT_BWR(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BWR(value)))
+#define SDHC_BWR_IRQSTAT_BWR(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BWR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
+ *
+ * This status bit is set if the Buffer Read Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0b0 - Not ready to read buffer.
+ * - 0b1 - Ready to read buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BRR field. */
+#define SDHC_RD_IRQSTAT_BRR(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BRR_MASK) >> SDHC_IRQSTAT_BRR_SHIFT)
+#define SDHC_BRD_IRQSTAT_BRR(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BRR_SHIFT))
+
+/*! @brief Set the BRR field to a new value. */
+#define SDHC_WR_IRQSTAT_BRR(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BRR(value)))
+#define SDHC_BWR_IRQSTAT_BRR(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 0 to 1. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if a card is inserted. To leave it cleared,
+ * clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0b0 - Card state unstable or removed.
+ * - 0b1 - Card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CINS field. */
+#define SDHC_RD_IRQSTAT_CINS(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CINS_MASK) >> SDHC_IRQSTAT_CINS_SHIFT)
+#define SDHC_BRD_IRQSTAT_CINS(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINS_SHIFT))
+
+/*! @brief Set the CINS field to a new value. */
+#define SDHC_WR_IRQSTAT_CINS(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CINS(value)))
+#define SDHC_BWR_IRQSTAT_CINS(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 1 to 0. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if no card is inserted. To leave it cleared,
+ * clear the Card Removal Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0b0 - Card state unstable or inserted.
+ * - 0b1 - Card removed.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CRM field. */
+#define SDHC_RD_IRQSTAT_CRM(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CRM_MASK) >> SDHC_IRQSTAT_CRM_SHIFT)
+#define SDHC_BRD_IRQSTAT_CRM(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CRM_SHIFT))
+
+/*! @brief Set the CRM field to a new value. */
+#define SDHC_WR_IRQSTAT_CRM(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CRM(value)))
+#define SDHC_BWR_IRQSTAT_CRM(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CRM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
+ *
+ * This status bit is set when an interrupt signal is detected from the external
+ * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
+ * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
+ * during the interrupt cycle, so the interrupt from card can only be sampled
+ * during interrupt cycle, introducing some delay between the interrupt signal from
+ * the SDIO card and the interrupt to the host system. Writing this bit to 1 can
+ * clear this bit, but as the interrupt factor from the SDIO card does not clear,
+ * this bit is set again. To clear this bit, it is required to reset the interrupt
+ * factor from the external card followed by a writing 1 to this bit. When this
+ * status has been set, and the host driver needs to service this interrupt, the
+ * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
+ * 0 to stop driving the interrupt signal to the host system. After completion
+ * of the card interrupt service (it must reset the interrupt factors in the SDIO
+ * card and the interrupt signal may not be asserted), write 1 to clear this bit,
+ * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
+ * signal again.
+ *
+ * Values:
+ * - 0b0 - No Card Interrupt.
+ * - 0b1 - Generate Card Interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CINT field. */
+#define SDHC_RD_IRQSTAT_CINT(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CINT_MASK) >> SDHC_IRQSTAT_CINT_SHIFT)
+#define SDHC_BRD_IRQSTAT_CINT(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINT_SHIFT))
+
+/*! @brief Set the CINT field to a new value. */
+#define SDHC_WR_IRQSTAT_CINT(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CINT(value)))
+#define SDHC_BWR_IRQSTAT_CINT(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
+ *
+ * Occurs only if no response is returned within 64 SDCLK cycles from the end
+ * bit of the command. If the SDHC detects a CMD line conflict, in which case a
+ * Command CRC Error shall also be set, this bit shall be set without waiting for 64
+ * SDCLK cycles. This is because the command will be aborted by the SDHC.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CTOE field. */
+#define SDHC_RD_IRQSTAT_CTOE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CTOE_MASK) >> SDHC_IRQSTAT_CTOE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CTOE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CTOE_SHIFT))
+
+/*! @brief Set the CTOE field to a new value. */
+#define SDHC_WR_IRQSTAT_CTOE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CTOE(value)))
+#define SDHC_BWR_IRQSTAT_CTOE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
+ *
+ * Command CRC Error is generated in two cases. If a response is returned and
+ * the Command Timeout Error is set to 0, indicating no time-out, this bit is set
+ * when detecting a CRC error in the command response. The SDHC detects a CMD line
+ * conflict by monitoring the CMD line when a command is issued. If the SDHC
+ * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
+ * then the SDHC shall abort the command (Stop driving CMD line) and set this bit
+ * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
+ * conflict.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - CRC Error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CCE field. */
+#define SDHC_RD_IRQSTAT_CCE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CCE_MASK) >> SDHC_IRQSTAT_CCE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CCE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CCE_SHIFT))
+
+/*! @brief Set the CCE field to a new value. */
+#define SDHC_WR_IRQSTAT_CCE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CCE(value)))
+#define SDHC_BWR_IRQSTAT_CCE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
+ *
+ * Occurs when detecting that the end bit of a command response is 0.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - End Bit Error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CEBE field. */
+#define SDHC_RD_IRQSTAT_CEBE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CEBE_MASK) >> SDHC_IRQSTAT_CEBE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CEBE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CEBE_SHIFT))
+
+/*! @brief Set the CEBE field to a new value. */
+#define SDHC_WR_IRQSTAT_CEBE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CEBE(value)))
+#define SDHC_BWR_IRQSTAT_CEBE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
+ *
+ * Occurs if a Command Index error occurs in the command response.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CIE field. */
+#define SDHC_RD_IRQSTAT_CIE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CIE_MASK) >> SDHC_IRQSTAT_CIE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CIE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CIE_SHIFT))
+
+/*! @brief Set the CIE field to a new value. */
+#define SDHC_WR_IRQSTAT_CIE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CIE(value)))
+#define SDHC_BWR_IRQSTAT_CIE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
+ *
+ * Occurs when detecting one of following time-out conditions. Busy time-out for
+ * R1b,R5b type Busy time-out after Write CRC status Read Data time-out
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DTOE field. */
+#define SDHC_RD_IRQSTAT_DTOE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DTOE_MASK) >> SDHC_IRQSTAT_DTOE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DTOE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DTOE_SHIFT))
+
+/*! @brief Set the DTOE field to a new value. */
+#define SDHC_WR_IRQSTAT_DTOE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DTOE(value)))
+#define SDHC_BWR_IRQSTAT_DTOE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
+ *
+ * Occurs when detecting a CRC error when transferring read data, which uses the
+ * DAT line, or when detecting the Write CRC status having a value other than
+ * 010.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DCE field. */
+#define SDHC_RD_IRQSTAT_DCE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DCE_MASK) >> SDHC_IRQSTAT_DCE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DCE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DCE_SHIFT))
+
+/*! @brief Set the DCE field to a new value. */
+#define SDHC_WR_IRQSTAT_DCE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DCE(value)))
+#define SDHC_BWR_IRQSTAT_DCE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
+ *
+ * Occurs either when detecting 0 at the end bit position of read data, which
+ * uses the DAT line, or at the end bit position of the CRC.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DEBE field. */
+#define SDHC_RD_IRQSTAT_DEBE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DEBE_MASK) >> SDHC_IRQSTAT_DEBE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DEBE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DEBE_SHIFT))
+
+/*! @brief Set the DEBE field to a new value. */
+#define SDHC_WR_IRQSTAT_DEBE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DEBE(value)))
+#define SDHC_BWR_IRQSTAT_DEBE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
+ *
+ * Occurs when detecting that one of the bits in the Auto CMD12 Error Status
+ * register has changed from 0 to 1. This bit is set to 1, not only when the errors
+ * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
+ * previous command error.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_AC12E field. */
+#define SDHC_RD_IRQSTAT_AC12E(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_AC12E_MASK) >> SDHC_IRQSTAT_AC12E_SHIFT)
+#define SDHC_BRD_IRQSTAT_AC12E(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_AC12E_SHIFT))
+
+/*! @brief Set the AC12E field to a new value. */
+#define SDHC_WR_IRQSTAT_AC12E(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_AC12E(value)))
+#define SDHC_BWR_IRQSTAT_AC12E(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_AC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
+ *
+ * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
+ * some error occurs in the data transfer. This error can be caused by either
+ * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
+ * Address register is the next fetch address where the error occurs. Because any
+ * error corrupts the whole data block, the host driver shall restart the transfer
+ * from the corrupted block boundary. The address of the block boundary can be
+ * calculated either from the current DSADDR value or from the remaining number of
+ * blocks and the block size.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DMAE field. */
+#define SDHC_RD_IRQSTAT_DMAE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DMAE_MASK) >> SDHC_IRQSTAT_DMAE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DMAE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DMAE_SHIFT))
+
+/*! @brief Set the DMAE field to a new value. */
+#define SDHC_WR_IRQSTAT_DMAE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DMAE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK), SDHC_IRQSTAT_DMAE(value)))
+#define SDHC_BWR_IRQSTAT_DMAE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DMAE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSTATEN - Interrupt Status Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
+ *
+ * Reset value: 0x117F013FU
+ *
+ * Setting the bits in this register to 1 enables the corresponding interrupt
+ * status to be set by the specified event. If any bit is cleared, the
+ * corresponding interrupt status bit is also cleared, that is, when the bit in this register
+ * is cleared, the corresponding bit in interrupt status register is always 0.
+ * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
+ * card interrupt signal during the interrupt period and hold its value in the
+ * flip-flop. There will be some delays on the card interrupt, asserted from the card,
+ * to the time the host system is informed. To detect a CMD line conflict, the
+ * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTATEN register
+ */
+/*@{*/
+#define SDHC_RD_IRQSTATEN(base)  (SDHC_IRQSTATEN_REG(base))
+#define SDHC_WR_IRQSTATEN(base, value) (SDHC_IRQSTATEN_REG(base) = (value))
+#define SDHC_RMW_IRQSTATEN(base, mask, value) (SDHC_WR_IRQSTATEN(base, (SDHC_RD_IRQSTATEN(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) |  (value)))
+#define SDHC_CLR_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) & ~(value)))
+#define SDHC_TOG_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSTATEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field. */
+#define SDHC_RD_IRQSTATEN_CCSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CCSEN_MASK) >> SDHC_IRQSTATEN_CCSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CCSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCSEN_SHIFT))
+
+/*! @brief Set the CCSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CCSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CCSEN_MASK, SDHC_IRQSTATEN_CCSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CCSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field. */
+#define SDHC_RD_IRQSTATEN_TCSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_TCSEN_MASK) >> SDHC_IRQSTATEN_TCSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_TCSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_TCSEN_SHIFT))
+
+/*! @brief Set the TCSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_TCSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_TCSEN_MASK, SDHC_IRQSTATEN_TCSEN(value)))
+#define SDHC_BWR_IRQSTATEN_TCSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_TCSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field. */
+#define SDHC_RD_IRQSTATEN_BGESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BGESEN_MASK) >> SDHC_IRQSTATEN_BGESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BGESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BGESEN_SHIFT))
+
+/*! @brief Set the BGESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BGESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BGESEN_MASK, SDHC_IRQSTATEN_BGESEN(value)))
+#define SDHC_BWR_IRQSTATEN_BGESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BGESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field. */
+#define SDHC_RD_IRQSTATEN_DINTSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DINTSEN_MASK) >> SDHC_IRQSTATEN_DINTSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DINTSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DINTSEN_SHIFT))
+
+/*! @brief Set the DINTSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DINTSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DINTSEN_MASK, SDHC_IRQSTATEN_DINTSEN(value)))
+#define SDHC_BWR_IRQSTATEN_DINTSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DINTSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field. */
+#define SDHC_RD_IRQSTATEN_BWRSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BWRSEN_MASK) >> SDHC_IRQSTATEN_BWRSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BWRSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BWRSEN_SHIFT))
+
+/*! @brief Set the BWRSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BWRSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BWRSEN_MASK, SDHC_IRQSTATEN_BWRSEN(value)))
+#define SDHC_BWR_IRQSTATEN_BWRSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BWRSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field. */
+#define SDHC_RD_IRQSTATEN_BRRSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BRRSEN_MASK) >> SDHC_IRQSTATEN_BRRSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BRRSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BRRSEN_SHIFT))
+
+/*! @brief Set the BRRSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BRRSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BRRSEN_MASK, SDHC_IRQSTATEN_BRRSEN(value)))
+#define SDHC_BWR_IRQSTATEN_BRRSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BRRSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field. */
+#define SDHC_RD_IRQSTATEN_CINSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CINSEN_MASK) >> SDHC_IRQSTATEN_CINSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CINSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINSEN_SHIFT))
+
+/*! @brief Set the CINSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CINSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CINSEN_MASK, SDHC_IRQSTATEN_CINSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CINSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field. */
+#define SDHC_RD_IRQSTATEN_CRMSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CRMSEN_MASK) >> SDHC_IRQSTATEN_CRMSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CRMSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CRMSEN_SHIFT))
+
+/*! @brief Set the CRMSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CRMSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CRMSEN_MASK, SDHC_IRQSTATEN_CRMSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CRMSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CRMSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
+ *
+ * If this bit is set to 0, the SDHC will clear the interrupt request to the
+ * system. The card interrupt detection is stopped when this bit is cleared and
+ * restarted when this bit is set to 1. The host driver must clear the this bit
+ * before servicing the card interrupt and must set this bit again after all interrupt
+ * requests from the card are cleared to prevent inadvertent interrupts.
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field. */
+#define SDHC_RD_IRQSTATEN_CINTSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CINTSEN_MASK) >> SDHC_IRQSTATEN_CINTSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CINTSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINTSEN_SHIFT))
+
+/*! @brief Set the CINTSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CINTSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CINTSEN_MASK, SDHC_IRQSTATEN_CINTSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CINTSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINTSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field. */
+#define SDHC_RD_IRQSTATEN_CTOESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CTOESEN_MASK) >> SDHC_IRQSTATEN_CTOESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CTOESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CTOESEN_SHIFT))
+
+/*! @brief Set the CTOESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CTOESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CTOESEN_MASK, SDHC_IRQSTATEN_CTOESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CTOESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CTOESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field. */
+#define SDHC_RD_IRQSTATEN_CCESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CCESEN_MASK) >> SDHC_IRQSTATEN_CCESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CCESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCESEN_SHIFT))
+
+/*! @brief Set the CCESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CCESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CCESEN_MASK, SDHC_IRQSTATEN_CCESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CCESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field. */
+#define SDHC_RD_IRQSTATEN_CEBESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CEBESEN_MASK) >> SDHC_IRQSTATEN_CEBESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CEBESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CEBESEN_SHIFT))
+
+/*! @brief Set the CEBESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CEBESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CEBESEN_MASK, SDHC_IRQSTATEN_CEBESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CEBESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CEBESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field. */
+#define SDHC_RD_IRQSTATEN_CIESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CIESEN_MASK) >> SDHC_IRQSTATEN_CIESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CIESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CIESEN_SHIFT))
+
+/*! @brief Set the CIESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CIESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CIESEN_MASK, SDHC_IRQSTATEN_CIESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CIESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CIESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field. */
+#define SDHC_RD_IRQSTATEN_DTOESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DTOESEN_MASK) >> SDHC_IRQSTATEN_DTOESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DTOESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DTOESEN_SHIFT))
+
+/*! @brief Set the DTOESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DTOESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DTOESEN_MASK, SDHC_IRQSTATEN_DTOESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DTOESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DTOESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field. */
+#define SDHC_RD_IRQSTATEN_DCESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DCESEN_MASK) >> SDHC_IRQSTATEN_DCESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DCESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DCESEN_SHIFT))
+
+/*! @brief Set the DCESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DCESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DCESEN_MASK, SDHC_IRQSTATEN_DCESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DCESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DCESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field. */
+#define SDHC_RD_IRQSTATEN_DEBESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DEBESEN_MASK) >> SDHC_IRQSTATEN_DEBESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DEBESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DEBESEN_SHIFT))
+
+/*! @brief Set the DEBESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DEBESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DEBESEN_MASK, SDHC_IRQSTATEN_DEBESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DEBESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DEBESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field. */
+#define SDHC_RD_IRQSTATEN_AC12ESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_AC12ESEN_MASK) >> SDHC_IRQSTATEN_AC12ESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_AC12ESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_AC12ESEN_SHIFT))
+
+/*! @brief Set the AC12ESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_AC12ESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_AC12ESEN_MASK, SDHC_IRQSTATEN_AC12ESEN(value)))
+#define SDHC_BWR_IRQSTATEN_AC12ESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_AC12ESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field. */
+#define SDHC_RD_IRQSTATEN_DMAESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DMAESEN_MASK) >> SDHC_IRQSTATEN_DMAESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DMAESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DMAESEN_SHIFT))
+
+/*! @brief Set the DMAESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DMAESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DMAESEN_MASK, SDHC_IRQSTATEN_DMAESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DMAESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DMAESEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSIGEN - Interrupt Signal Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to select which interrupt status is indicated to the
+ * host system as the interrupt. All of these status bits share the same interrupt
+ * line. Setting any of these bits to 1 enables interrupt generation. The
+ * corresponding status register bit will generate an interrupt when the corresponding
+ * interrupt signal enable bit is set.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSIGEN register
+ */
+/*@{*/
+#define SDHC_RD_IRQSIGEN(base)   (SDHC_IRQSIGEN_REG(base))
+#define SDHC_WR_IRQSIGEN(base, value) (SDHC_IRQSIGEN_REG(base) = (value))
+#define SDHC_RMW_IRQSIGEN(base, mask, value) (SDHC_WR_IRQSIGEN(base, (SDHC_RD_IRQSIGEN(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) |  (value)))
+#define SDHC_CLR_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) & ~(value)))
+#define SDHC_TOG_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSIGEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field. */
+#define SDHC_RD_IRQSIGEN_CCIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CCIEN_MASK) >> SDHC_IRQSIGEN_CCIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CCIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCIEN_SHIFT))
+
+/*! @brief Set the CCIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CCIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CCIEN_MASK, SDHC_IRQSIGEN_CCIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CCIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field. */
+#define SDHC_RD_IRQSIGEN_TCIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_TCIEN_MASK) >> SDHC_IRQSIGEN_TCIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_TCIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_TCIEN_SHIFT))
+
+/*! @brief Set the TCIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_TCIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_TCIEN_MASK, SDHC_IRQSIGEN_TCIEN(value)))
+#define SDHC_BWR_IRQSIGEN_TCIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_TCIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field. */
+#define SDHC_RD_IRQSIGEN_BGEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BGEIEN_MASK) >> SDHC_IRQSIGEN_BGEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BGEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BGEIEN_SHIFT))
+
+/*! @brief Set the BGEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BGEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BGEIEN_MASK, SDHC_IRQSIGEN_BGEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BGEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BGEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field. */
+#define SDHC_RD_IRQSIGEN_DINTIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DINTIEN_MASK) >> SDHC_IRQSIGEN_DINTIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DINTIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DINTIEN_SHIFT))
+
+/*! @brief Set the DINTIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DINTIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DINTIEN_MASK, SDHC_IRQSIGEN_DINTIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DINTIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DINTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field. */
+#define SDHC_RD_IRQSIGEN_BWRIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BWRIEN_MASK) >> SDHC_IRQSIGEN_BWRIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BWRIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BWRIEN_SHIFT))
+
+/*! @brief Set the BWRIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BWRIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BWRIEN_MASK, SDHC_IRQSIGEN_BWRIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BWRIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BWRIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field. */
+#define SDHC_RD_IRQSIGEN_BRRIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BRRIEN_MASK) >> SDHC_IRQSIGEN_BRRIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BRRIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BRRIEN_SHIFT))
+
+/*! @brief Set the BRRIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BRRIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BRRIEN_MASK, SDHC_IRQSIGEN_BRRIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BRRIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BRRIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field. */
+#define SDHC_RD_IRQSIGEN_CINSIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CINSIEN_MASK) >> SDHC_IRQSIGEN_CINSIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CINSIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINSIEN_SHIFT))
+
+/*! @brief Set the CINSIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CINSIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CINSIEN_MASK, SDHC_IRQSIGEN_CINSIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CINSIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINSIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field. */
+#define SDHC_RD_IRQSIGEN_CRMIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CRMIEN_MASK) >> SDHC_IRQSIGEN_CRMIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CRMIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CRMIEN_SHIFT))
+
+/*! @brief Set the CRMIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CRMIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CRMIEN_MASK, SDHC_IRQSIGEN_CRMIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CRMIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CRMIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field. */
+#define SDHC_RD_IRQSIGEN_CINTIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CINTIEN_MASK) >> SDHC_IRQSIGEN_CINTIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CINTIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINTIEN_SHIFT))
+
+/*! @brief Set the CINTIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CINTIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CINTIEN_MASK, SDHC_IRQSIGEN_CINTIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CINTIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field. */
+#define SDHC_RD_IRQSIGEN_CTOEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CTOEIEN_MASK) >> SDHC_IRQSIGEN_CTOEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CTOEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CTOEIEN_SHIFT))
+
+/*! @brief Set the CTOEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CTOEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CTOEIEN_MASK, SDHC_IRQSIGEN_CTOEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CTOEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CTOEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field. */
+#define SDHC_RD_IRQSIGEN_CCEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CCEIEN_MASK) >> SDHC_IRQSIGEN_CCEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CCEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCEIEN_SHIFT))
+
+/*! @brief Set the CCEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CCEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CCEIEN_MASK, SDHC_IRQSIGEN_CCEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CCEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field. */
+#define SDHC_RD_IRQSIGEN_CEBEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CEBEIEN_MASK) >> SDHC_IRQSIGEN_CEBEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CEBEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CEBEIEN_SHIFT))
+
+/*! @brief Set the CEBEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CEBEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CEBEIEN_MASK, SDHC_IRQSIGEN_CEBEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CEBEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CEBEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field. */
+#define SDHC_RD_IRQSIGEN_CIEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CIEIEN_MASK) >> SDHC_IRQSIGEN_CIEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CIEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CIEIEN_SHIFT))
+
+/*! @brief Set the CIEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CIEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CIEIEN_MASK, SDHC_IRQSIGEN_CIEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CIEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CIEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field. */
+#define SDHC_RD_IRQSIGEN_DTOEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DTOEIEN_MASK) >> SDHC_IRQSIGEN_DTOEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DTOEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DTOEIEN_SHIFT))
+
+/*! @brief Set the DTOEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DTOEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DTOEIEN_MASK, SDHC_IRQSIGEN_DTOEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DTOEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DTOEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field. */
+#define SDHC_RD_IRQSIGEN_DCEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DCEIEN_MASK) >> SDHC_IRQSIGEN_DCEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DCEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DCEIEN_SHIFT))
+
+/*! @brief Set the DCEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DCEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DCEIEN_MASK, SDHC_IRQSIGEN_DCEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DCEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DCEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field. */
+#define SDHC_RD_IRQSIGEN_DEBEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DEBEIEN_MASK) >> SDHC_IRQSIGEN_DEBEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DEBEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DEBEIEN_SHIFT))
+
+/*! @brief Set the DEBEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DEBEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DEBEIEN_MASK, SDHC_IRQSIGEN_DEBEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DEBEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DEBEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field. */
+#define SDHC_RD_IRQSIGEN_AC12EIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_AC12EIEN_MASK) >> SDHC_IRQSIGEN_AC12EIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_AC12EIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_AC12EIEN_SHIFT))
+
+/*! @brief Set the AC12EIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_AC12EIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_AC12EIEN_MASK, SDHC_IRQSIGEN_AC12EIEN(value)))
+#define SDHC_BWR_IRQSIGEN_AC12EIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_AC12EIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field. */
+#define SDHC_RD_IRQSIGEN_DMAEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DMAEIEN_MASK) >> SDHC_IRQSIGEN_DMAEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DMAEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DMAEIEN_SHIFT))
+
+/*! @brief Set the DMAEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DMAEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DMAEIEN_MASK, SDHC_IRQSIGEN_DMAEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DMAEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DMAEIEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_AC12ERR - Auto CMD12 Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the AC12ESEN bit in the Status register is set, the host driver shall
+ * check this register to identify what kind of error the Auto CMD12 indicated.
+ * This register is valid only when the Auto CMD12 Error status bit is set. The
+ * following table shows the relationship between the Auto CMGD12 CRC error and the
+ * Auto CMD12 command timeout error. Relationship between Command CRC Error and
+ * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
+ * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
+ * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
+ * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
+ * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
+ * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
+ * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
+ * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
+ * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
+ * command that can't be issued. Clear bit 7 if there is no command to issue. The
+ * timing for generating the auto CMD12 error and writing to the command register
+ * are asynchronous. After that, bit 7 shall be sampled when the driver is not
+ * writing to the command register. So it is suggested to read this register only
+ * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
+ * of the error bits (0-4) is set to 1. The command not issued by auto CMD12
+ * error does not generate an interrupt.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_AC12ERR register
+ */
+/*@{*/
+#define SDHC_RD_AC12ERR(base)    (SDHC_AC12ERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_AC12ERR bitfields
+ */
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
+ *
+ * If memory multiple block data transfer is not started, due to a command
+ * error, this bit is not set because it is not necessary to issue an auto CMD12.
+ * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
+ * multiple block data transfer due to some error. If this bit is set to 1, other
+ * error status bits (1-4) have no meaning.
+ *
+ * Values:
+ * - 0b0 - Executed.
+ * - 0b1 - Not executed.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12NE field. */
+#define SDHC_RD_AC12ERR_AC12NE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12NE_MASK) >> SDHC_AC12ERR_AC12NE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12NE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12NE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
+ *
+ * Occurs if no response is returned within 64 SDCLK cycles from the end bit of
+ * the command. If this bit is set to 1, the other error status bits (2-4) have
+ * no meaning.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12TOE field. */
+#define SDHC_RD_AC12ERR_AC12TOE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12TOE_MASK) >> SDHC_AC12ERR_AC12TOE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12TOE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12TOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
+ *
+ * Occurs when detecting that the end bit of command response is 0 which must be
+ * 1.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - End bit error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12EBE field. */
+#define SDHC_RD_AC12ERR_AC12EBE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12EBE_MASK) >> SDHC_AC12ERR_AC12EBE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12EBE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12EBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
+ *
+ * Occurs when detecting a CRC error in the command response.
+ *
+ * Values:
+ * - 0b0 - No CRC error.
+ * - 0b1 - CRC error met in Auto CMD12 response.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12CE field. */
+#define SDHC_RD_AC12ERR_AC12CE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12CE_MASK) >> SDHC_AC12ERR_AC12CE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12CE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12CE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
+ *
+ * Occurs if the command index error occurs in response to a command.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error, the CMD index in response is not CMD12.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12IE field. */
+#define SDHC_RD_AC12ERR_AC12IE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12IE_MASK) >> SDHC_AC12ERR_AC12IE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12IE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12IE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
+ *
+ * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
+ * error (D04-D01) in this register.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Not issued.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field. */
+#define SDHC_RD_AC12ERR_CNIBAC12E(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_CNIBAC12E_MASK) >> SDHC_AC12ERR_CNIBAC12E_SHIFT)
+#define SDHC_BRD_AC12ERR_CNIBAC12E(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_CNIBAC12E_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_HTCAPBLT - Host Controller Capabilities
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_HTCAPBLT - Host Controller Capabilities (RO)
+ *
+ * Reset value: 0x07F30000U
+ *
+ * This register provides the host driver with information specific to the SDHC
+ * implementation. The value in this register is the power-on-reset value, and
+ * does not change with a software reset. Any write to this register is ignored.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_HTCAPBLT register
+ */
+/*@{*/
+#define SDHC_RD_HTCAPBLT(base)   (SDHC_HTCAPBLT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_HTCAPBLT bitfields
+ */
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
+ *
+ * This value indicates the maximum block size that the host driver can read and
+ * write to the buffer in the SDHC. The buffer shall transfer block size without
+ * wait cycles.
+ *
+ * Values:
+ * - 0b000 - 512 bytes
+ * - 0b001 - 1024 bytes
+ * - 0b010 - 2048 bytes
+ * - 0b011 - 4096 bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_MBL field. */
+#define SDHC_RD_HTCAPBLT_MBL(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_MBL_MASK) >> SDHC_HTCAPBLT_MBL_SHIFT)
+#define SDHC_BRD_HTCAPBLT_MBL(base) (SDHC_RD_HTCAPBLT_MBL(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
+ *
+ * This bit indicates whether the SDHC supports the ADMA feature.
+ *
+ * Values:
+ * - 0b0 - Advanced DMA not supported.
+ * - 0b1 - Advanced DMA supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field. */
+#define SDHC_RD_HTCAPBLT_ADMAS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_ADMAS_MASK) >> SDHC_HTCAPBLT_ADMAS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_ADMAS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_ADMAS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
+ *
+ * This bit indicates whether the SDHC supports high speed mode and the host
+ * system can supply a SD Clock frequency from 25 MHz to 50 MHz.
+ *
+ * Values:
+ * - 0b0 - High speed not supported.
+ * - 0b1 - High speed supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_HSS field. */
+#define SDHC_RD_HTCAPBLT_HSS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_HSS_MASK) >> SDHC_HTCAPBLT_HSS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_HSS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_HSS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
+ *
+ * This bit indicates whether the SDHC is capable of using the internal DMA to
+ * transfer data between system memory and the data buffer directly.
+ *
+ * Values:
+ * - 0b0 - DMA not supported.
+ * - 0b1 - DMA supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_DMAS field. */
+#define SDHC_RD_HTCAPBLT_DMAS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_DMAS_MASK) >> SDHC_HTCAPBLT_DMAS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_DMAS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_DMAS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
+ *
+ * This bit indicates whether the SDHC supports suspend / resume functionality.
+ * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
+ * are not supported, and the host driver shall not issue either suspend or
+ * resume commands.
+ *
+ * Values:
+ * - 0b0 - Not supported.
+ * - 0b1 - Supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_SRS field. */
+#define SDHC_RD_HTCAPBLT_SRS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_SRS_MASK) >> SDHC_HTCAPBLT_SRS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_SRS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_SRS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
+ *
+ * This bit shall depend on the host system ability.
+ *
+ * Values:
+ * - 0b0 - 3.3 V not supported.
+ * - 0b1 - 3.3 V supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_VS33 field. */
+#define SDHC_RD_HTCAPBLT_VS33(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_VS33_MASK) >> SDHC_HTCAPBLT_VS33_SHIFT)
+#define SDHC_BRD_HTCAPBLT_VS33(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_VS33_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_WML - Watermark Level Register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_WML - Watermark Level Register (RW)
+ *
+ * Reset value: 0x00100010U
+ *
+ * Both write and read watermark levels (FIFO threshold) are configurable. There
+ * value can range from 1 to 128 words. Both write and read burst lengths are
+ * also configurable. There value can range from 1 to 31 words.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_WML register
+ */
+/*@{*/
+#define SDHC_RD_WML(base)        (SDHC_WML_REG(base))
+#define SDHC_WR_WML(base, value) (SDHC_WML_REG(base) = (value))
+#define SDHC_RMW_WML(base, mask, value) (SDHC_WR_WML(base, (SDHC_RD_WML(base) & ~(mask)) | (value)))
+#define SDHC_SET_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) |  (value)))
+#define SDHC_CLR_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) & ~(value)))
+#define SDHC_TOG_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_WML bitfields
+ */
+
+/*!
+ * @name Register SDHC_WML, field RDWML[7:0] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * read operation. Also the number of words as a sequence of read bursts in
+ * back-to-back mode. The maximum legal value for the read water mark level is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_WML_RDWML field. */
+#define SDHC_RD_WML_RDWML(base) ((SDHC_WML_REG(base) & SDHC_WML_RDWML_MASK) >> SDHC_WML_RDWML_SHIFT)
+#define SDHC_BRD_WML_RDWML(base) (SDHC_RD_WML_RDWML(base))
+
+/*! @brief Set the RDWML field to a new value. */
+#define SDHC_WR_WML_RDWML(base, value) (SDHC_RMW_WML(base, SDHC_WML_RDWML_MASK, SDHC_WML_RDWML(value)))
+#define SDHC_BWR_WML_RDWML(base, value) (SDHC_WR_WML_RDWML(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_WML, field WRWML[23:16] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * write operation. Also the number of words as a sequence of write bursts in
+ * back-to-back mode. The maximum legal value for the write watermark level is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_WML_WRWML field. */
+#define SDHC_RD_WML_WRWML(base) ((SDHC_WML_REG(base) & SDHC_WML_WRWML_MASK) >> SDHC_WML_WRWML_SHIFT)
+#define SDHC_BRD_WML_WRWML(base) (SDHC_RD_WML_WRWML(base))
+
+/*! @brief Set the WRWML field to a new value. */
+#define SDHC_WR_WML_WRWML(base, value) (SDHC_RMW_WML(base, SDHC_WML_WRWML_MASK, SDHC_WML_WRWML(value)))
+#define SDHC_BWR_WML_WRWML(base, value) (SDHC_WR_WML_WRWML(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_FEVT - Force Event register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_FEVT - Force Event register (WO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Force Event (FEVT) register is not a physically implemented register.
+ * Rather, it is an address at which the Interrupt Status register can be written if
+ * the corresponding bit of the Interrupt Status Enable register is set. This
+ * register is a write only register and writing 0 to it has no effect. Writing 1
+ * to this register actually sets the corresponding bit of Interrupt Status
+ * register. A read from this register always results in 0's. To change the
+ * corresponding status bits in the interrupt status register, make sure to set
+ * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
+ * short pulse on the DAT[1] line, and the driver may treat this interrupt as a
+ * normal interrupt. The interrupt service routine may skip polling the card
+ * interrupt factor as the interrupt is selfcleared.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_FEVT register
+ */
+/*@{*/
+#define SDHC_RD_FEVT(base)       (SDHC_FEVT_REG(base))
+#define SDHC_WR_FEVT(base, value) (SDHC_FEVT_REG(base) = (value))
+#define SDHC_RMW_FEVT(base, mask, value) (SDHC_WR_FEVT(base, (SDHC_RD_FEVT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_FEVT bitfields
+ */
+
+/*!
+ * @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
+ *
+ * Forces AC12ERR[AC12NE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12NE field to a new value. */
+#define SDHC_WR_FEVT_AC12NE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12NE_MASK, SDHC_FEVT_AC12NE(value)))
+#define SDHC_BWR_FEVT_AC12NE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12NE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
+ *
+ * Forces AC12ERR[AC12TOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12TOE field to a new value. */
+#define SDHC_WR_FEVT_AC12TOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12TOE_MASK, SDHC_FEVT_AC12TOE(value)))
+#define SDHC_BWR_FEVT_AC12TOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12TOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
+ *
+ * Forces AC12ERR[AC12CE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12CE field to a new value. */
+#define SDHC_WR_FEVT_AC12CE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12CE_MASK, SDHC_FEVT_AC12CE(value)))
+#define SDHC_BWR_FEVT_AC12CE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12CE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
+ *
+ * Forces AC12ERR[AC12EBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12EBE field to a new value. */
+#define SDHC_WR_FEVT_AC12EBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12EBE_MASK, SDHC_FEVT_AC12EBE(value)))
+#define SDHC_BWR_FEVT_AC12EBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12EBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
+ *
+ * Forces AC12ERR[AC12IE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12IE field to a new value. */
+#define SDHC_WR_FEVT_AC12IE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12IE_MASK, SDHC_FEVT_AC12IE(value)))
+#define SDHC_BWR_FEVT_AC12IE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
+ *
+ * Forces AC12ERR[CNIBAC12E] to be set.
+ */
+/*@{*/
+/*! @brief Set the CNIBAC12E field to a new value. */
+#define SDHC_WR_FEVT_CNIBAC12E(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CNIBAC12E_MASK, SDHC_FEVT_CNIBAC12E(value)))
+#define SDHC_BWR_FEVT_CNIBAC12E(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CNIBAC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CTOE[16] (WORZ)
+ *
+ * Forces IRQSTAT[CTOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CTOE field to a new value. */
+#define SDHC_WR_FEVT_CTOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CTOE_MASK, SDHC_FEVT_CTOE(value)))
+#define SDHC_BWR_FEVT_CTOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CCE[17] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CCE field to a new value. */
+#define SDHC_WR_FEVT_CCE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CCE_MASK, SDHC_FEVT_CCE(value)))
+#define SDHC_BWR_FEVT_CCE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CEBE[18] (WORZ)
+ *
+ * Forces IRQSTAT[CEBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CEBE field to a new value. */
+#define SDHC_WR_FEVT_CEBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CEBE_MASK, SDHC_FEVT_CEBE(value)))
+#define SDHC_BWR_FEVT_CEBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CIE[19] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CIE field to a new value. */
+#define SDHC_WR_FEVT_CIE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CIE_MASK, SDHC_FEVT_CIE(value)))
+#define SDHC_BWR_FEVT_CIE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DTOE[20] (WORZ)
+ *
+ * Forces IRQSTAT[DTOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DTOE field to a new value. */
+#define SDHC_WR_FEVT_DTOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DTOE_MASK, SDHC_FEVT_DTOE(value)))
+#define SDHC_BWR_FEVT_DTOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DCE[21] (WORZ)
+ *
+ * Forces IRQSTAT[DCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DCE field to a new value. */
+#define SDHC_WR_FEVT_DCE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DCE_MASK, SDHC_FEVT_DCE(value)))
+#define SDHC_BWR_FEVT_DCE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DEBE[22] (WORZ)
+ *
+ * Forces IRQSTAT[DEBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DEBE field to a new value. */
+#define SDHC_WR_FEVT_DEBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DEBE_MASK, SDHC_FEVT_DEBE(value)))
+#define SDHC_BWR_FEVT_DEBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12E[24] (WORZ)
+ *
+ * Forces IRQSTAT[AC12E] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12E field to a new value. */
+#define SDHC_WR_FEVT_AC12E(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12E_MASK, SDHC_FEVT_AC12E(value)))
+#define SDHC_BWR_FEVT_AC12E(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DMAE[28] (WORZ)
+ *
+ * Forces the DMAE bit of Interrupt Status Register to be set.
+ */
+/*@{*/
+/*! @brief Set the DMAE field to a new value. */
+#define SDHC_WR_FEVT_DMAE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DMAE_MASK, SDHC_FEVT_DMAE(value)))
+#define SDHC_BWR_FEVT_DMAE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DMAE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CINT[31] (WORZ)
+ *
+ * Writing 1 to this bit generates a short low-level pulse on the internal
+ * DAT[1] line, as if a self-clearing interrupt was received from the external card.
+ * If enabled, the CINT bit will be set and the interrupt service routine may
+ * treat this interrupt as a normal interrupt from the external card.
+ */
+/*@{*/
+/*! @brief Set the CINT field to a new value. */
+#define SDHC_WR_FEVT_CINT(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CINT_MASK, SDHC_FEVT_CINT(value)))
+#define SDHC_BWR_FEVT_CINT(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CINT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_ADMAES - ADMA Error Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_ADMAES - ADMA Error Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an ADMA error interrupt has occurred, the ADMA Error States field in
+ * this register holds the ADMA state and the ADMA System Address register holds the
+ * address around the error descriptor. For recovering from this error, the host
+ * driver requires the ADMA state to identify the error descriptor address as
+ * follows: ST_STOP: Previous location set in the ADMA System Address register is
+ * the error descriptor address. ST_FDS: Current location set in the ADMA System
+ * Address register is the error descriptor address. ST_CADR: This state is never
+ * set because it only increments the descriptor pointer and doesn't generate an
+ * ADMA error. ST_TFR: Previous location set in the ADMA System Address register
+ * is the error descriptor address. In case of a write operation, the host driver
+ * must use the ACMD22 to get the number of the written block, rather than using
+ * this information, because unwritten data may exist in the host controller.
+ * The host controller generates the ADMA error interrupt when it detects invalid
+ * descriptor data (valid = 0) in the ST_FDS state. The host driver can
+ * distinguish this error by reading the valid bit of the error descriptor. ADMA Error
+ * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
+ * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
+ * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
+ * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
+ * (Transfer Data) Holds the address of the next executable descriptor command
+ */
+/*!
+ * @name Constants and macros for entire SDHC_ADMAES register
+ */
+/*@{*/
+#define SDHC_RD_ADMAES(base)     (SDHC_ADMAES_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_ADMAES bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
+ *
+ * Indicates the state of the ADMA when an error has occurred during an ADMA
+ * data transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMAES field. */
+#define SDHC_RD_ADMAES_ADMAES(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMAES_MASK) >> SDHC_ADMAES_ADMAES_SHIFT)
+#define SDHC_BRD_ADMAES_ADMAES(base) (SDHC_RD_ADMAES_ADMAES(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMALME[2] (RO)
+ *
+ * This error occurs in the following 2 cases: While the block count enable is
+ * being set, the total data length specified by the descriptor table is different
+ * from that specified by the block count and block length. Total data length
+ * can not be divided by the block length.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMALME field. */
+#define SDHC_RD_ADMAES_ADMALME(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMALME_MASK) >> SDHC_ADMAES_ADMALME_SHIFT)
+#define SDHC_BRD_ADMAES_ADMALME(base) (BITBAND_ACCESS32(&SDHC_ADMAES_REG(base), SDHC_ADMAES_ADMALME_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
+ *
+ * This error occurs when an invalid descriptor is fetched by ADMA.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMADCE field. */
+#define SDHC_RD_ADMAES_ADMADCE(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMADCE_MASK) >> SDHC_ADMAES_ADMADCE_SHIFT)
+#define SDHC_BRD_ADMAES_ADMADCE(base) (BITBAND_ACCESS32(&SDHC_ADMAES_REG(base), SDHC_ADMAES_ADMADCE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_ADSADDR - ADMA System Addressregister
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_ADSADDR - ADMA System Addressregister (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for ADMA
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_ADSADDR register
+ */
+/*@{*/
+#define SDHC_RD_ADSADDR(base)    (SDHC_ADSADDR_REG(base))
+#define SDHC_WR_ADSADDR(base, value) (SDHC_ADSADDR_REG(base) = (value))
+#define SDHC_RMW_ADSADDR(base, mask, value) (SDHC_WR_ADSADDR(base, (SDHC_RD_ADSADDR(base) & ~(mask)) | (value)))
+#define SDHC_SET_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) |  (value)))
+#define SDHC_CLR_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) & ~(value)))
+#define SDHC_TOG_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_ADSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
+ *
+ * Holds the word address of the executing command in the descriptor table. At
+ * the start of ADMA, the host driver shall set the start address of the
+ * Descriptor table. The ADMA engine increments this register address whenever fetching a
+ * descriptor command. When the ADMA is stopped at the block gap, this register
+ * indicates the address of the next executable descriptor command. When the ADMA
+ * error interrupt is generated, this register shall hold the valid descriptor
+ * address depending on the ADMA state. The lower 2 bits of this register is tied
+ * to '0' so the ADMA address is always word-aligned. Because this register
+ * supports dynamic address reflecting, when TC bit is set, it automatically alters the
+ * value of internal address counter, so SW cannot change this register when TC
+ * bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADSADDR_ADSADDR field. */
+#define SDHC_RD_ADSADDR_ADSADDR(base) ((SDHC_ADSADDR_REG(base) & SDHC_ADSADDR_ADSADDR_MASK) >> SDHC_ADSADDR_ADSADDR_SHIFT)
+#define SDHC_BRD_ADSADDR_ADSADDR(base) (SDHC_RD_ADSADDR_ADSADDR(base))
+
+/*! @brief Set the ADSADDR field to a new value. */
+#define SDHC_WR_ADSADDR_ADSADDR(base, value) (SDHC_RMW_ADSADDR(base, SDHC_ADSADDR_ADSADDR_MASK, SDHC_ADSADDR_ADSADDR(value)))
+#define SDHC_BWR_ADSADDR_ADSADDR(base, value) (SDHC_WR_ADSADDR_ADSADDR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_VENDOR - Vendor Specific register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_VENDOR - Vendor Specific register (RW)
+ *
+ * Reset value: 0x00000001U
+ *
+ * This register contains the vendor-specific control/status register.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_VENDOR register
+ */
+/*@{*/
+#define SDHC_RD_VENDOR(base)     (SDHC_VENDOR_REG(base))
+#define SDHC_WR_VENDOR(base, value) (SDHC_VENDOR_REG(base) = (value))
+#define SDHC_RMW_VENDOR(base, mask, value) (SDHC_WR_VENDOR(base, (SDHC_RD_VENDOR(base) & ~(mask)) | (value)))
+#define SDHC_SET_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) |  (value)))
+#define SDHC_CLR_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) & ~(value)))
+#define SDHC_TOG_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_VENDOR bitfields
+ */
+
+/*!
+ * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
+ *
+ * Enables the request to external DMA. When the internal DMA (either simple DMA
+ * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
+ * request when the internal buffer is ready. This bit is particularly useful when
+ * transferring data by CPU polling mode, and it is not allowed to send out the
+ * external DMA request. By default, this bit is set.
+ *
+ * Values:
+ * - 0b0 - In any scenario, SDHC does not send out the external DMA request.
+ * - 0b1 - When internal DMA is not active, the external DMA request will be
+ *     sent out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field. */
+#define SDHC_RD_VENDOR_EXTDMAEN(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_EXTDMAEN_MASK) >> SDHC_VENDOR_EXTDMAEN_SHIFT)
+#define SDHC_BRD_VENDOR_EXTDMAEN(base) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXTDMAEN_SHIFT))
+
+/*! @brief Set the EXTDMAEN field to a new value. */
+#define SDHC_WR_VENDOR_EXTDMAEN(base, value) (SDHC_RMW_VENDOR(base, SDHC_VENDOR_EXTDMAEN_MASK, SDHC_VENDOR_EXTDMAEN(value)))
+#define SDHC_BWR_VENDOR_EXTDMAEN(base, value) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXTDMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
+ *
+ * This bit must be set before S/W issues CMD53 multi-block read with exact
+ * block number. This bit must not be set if the CMD53 multi-block read is not exact
+ * block number.
+ *
+ * Values:
+ * - 0b0 - None exact block read.
+ * - 0b1 - Exact block read for SDIO CMD53.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_EXBLKNU field. */
+#define SDHC_RD_VENDOR_EXBLKNU(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_EXBLKNU_MASK) >> SDHC_VENDOR_EXBLKNU_SHIFT)
+#define SDHC_BRD_VENDOR_EXBLKNU(base) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXBLKNU_SHIFT))
+
+/*! @brief Set the EXBLKNU field to a new value. */
+#define SDHC_WR_VENDOR_EXBLKNU(base, value) (SDHC_RMW_VENDOR(base, SDHC_VENDOR_EXBLKNU_MASK, SDHC_VENDOR_EXBLKNU(value)))
+#define SDHC_BWR_VENDOR_EXBLKNU(base, value) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXBLKNU_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
+ *
+ * Internal state value, reflecting the corresponding state value selected by
+ * Debug Select field. This field is read-only and write to this field does not
+ * have effect.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_INTSTVAL field. */
+#define SDHC_RD_VENDOR_INTSTVAL(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_INTSTVAL_MASK) >> SDHC_VENDOR_INTSTVAL_SHIFT)
+#define SDHC_BRD_VENDOR_INTSTVAL(base) (SDHC_RD_VENDOR_INTSTVAL(base))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_MMCBOOT - MMC Boot register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_MMCBOOT - MMC Boot register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the MMC fast boot control register.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_MMCBOOT register
+ */
+/*@{*/
+#define SDHC_RD_MMCBOOT(base)    (SDHC_MMCBOOT_REG(base))
+#define SDHC_WR_MMCBOOT(base, value) (SDHC_MMCBOOT_REG(base) = (value))
+#define SDHC_RMW_MMCBOOT(base, mask, value) (SDHC_WR_MMCBOOT(base, (SDHC_RD_MMCBOOT(base) & ~(mask)) | (value)))
+#define SDHC_SET_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) |  (value)))
+#define SDHC_CLR_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) & ~(value)))
+#define SDHC_TOG_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_MMCBOOT bitfields
+ */
+
+/*!
+ * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
+ *
+ * Values:
+ * - 0b0000 - SDCLK x 2^8
+ * - 0b0001 - SDCLK x 2^9
+ * - 0b0010 - SDCLK x 2^10
+ * - 0b0011 - SDCLK x 2^11
+ * - 0b0100 - SDCLK x 2^12
+ * - 0b0101 - SDCLK x 2^13
+ * - 0b0110 - SDCLK x 2^14
+ * - 0b0111 - SDCLK x 2^15
+ * - 0b1110 - SDCLK x 2^22
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field. */
+#define SDHC_RD_MMCBOOT_DTOCVACK(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_DTOCVACK_MASK) >> SDHC_MMCBOOT_DTOCVACK_SHIFT)
+#define SDHC_BRD_MMCBOOT_DTOCVACK(base) (SDHC_RD_MMCBOOT_DTOCVACK(base))
+
+/*! @brief Set the DTOCVACK field to a new value. */
+#define SDHC_WR_MMCBOOT_DTOCVACK(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_DTOCVACK_MASK, SDHC_MMCBOOT_DTOCVACK(value)))
+#define SDHC_BWR_MMCBOOT_DTOCVACK(base, value) (SDHC_WR_MMCBOOT_DTOCVACK(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
+ *
+ * Values:
+ * - 0b0 - No ack.
+ * - 0b1 - Ack.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field. */
+#define SDHC_RD_MMCBOOT_BOOTACK(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTACK_MASK) >> SDHC_MMCBOOT_BOOTACK_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTACK(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTACK_SHIFT))
+
+/*! @brief Set the BOOTACK field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTACK(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTACK_MASK, SDHC_MMCBOOT_BOOTACK(value)))
+#define SDHC_BWR_MMCBOOT_BOOTACK(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal boot.
+ * - 0b1 - Alternative boot.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field. */
+#define SDHC_RD_MMCBOOT_BOOTMODE(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTMODE_MASK) >> SDHC_MMCBOOT_BOOTMODE_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTMODE(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTMODE_SHIFT))
+
+/*! @brief Set the BOOTMODE field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTMODE(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTMODE_MASK, SDHC_MMCBOOT_BOOTMODE(value)))
+#define SDHC_BWR_MMCBOOT_BOOTMODE(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Fast boot disable.
+ * - 0b1 - Fast boot enable.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field. */
+#define SDHC_RD_MMCBOOT_BOOTEN(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTEN_MASK) >> SDHC_MMCBOOT_BOOTEN_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTEN(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTEN_SHIFT))
+
+/*! @brief Set the BOOTEN field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTEN(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTEN_MASK, SDHC_MMCBOOT_BOOTEN(value)))
+#define SDHC_BWR_MMCBOOT_BOOTEN(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
+ *
+ * When boot, enable auto stop at block gap function. This function will be
+ * triggered, and host will stop at block gap when received card block cnt is equal
+ * to BOOTBLKCNT.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field. */
+#define SDHC_RD_MMCBOOT_AUTOSABGEN(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_AUTOSABGEN_MASK) >> SDHC_MMCBOOT_AUTOSABGEN_SHIFT)
+#define SDHC_BRD_MMCBOOT_AUTOSABGEN(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_AUTOSABGEN_SHIFT))
+
+/*! @brief Set the AUTOSABGEN field to a new value. */
+#define SDHC_WR_MMCBOOT_AUTOSABGEN(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_AUTOSABGEN_MASK, SDHC_MMCBOOT_AUTOSABGEN(value)))
+#define SDHC_BWR_MMCBOOT_AUTOSABGEN(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_AUTOSABGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
+ *
+ * Defines the stop at block gap value of automatic mode. When received card
+ * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field. */
+#define SDHC_RD_MMCBOOT_BOOTBLKCNT(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTBLKCNT_MASK) >> SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTBLKCNT(base) (SDHC_RD_MMCBOOT_BOOTBLKCNT(base))
+
+/*! @brief Set the BOOTBLKCNT field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTBLKCNT(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTBLKCNT_MASK, SDHC_MMCBOOT_BOOTBLKCNT(value)))
+#define SDHC_BWR_MMCBOOT_BOOTBLKCNT(base, value) (SDHC_WR_MMCBOOT_BOOTBLKCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_HOSTVER - Host Controller Version
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_HOSTVER - Host Controller Version (RO)
+ *
+ * Reset value: 0x00001201U
+ *
+ * This register contains the vendor host controller version information. All
+ * bits are read only and will read the same as the power-reset value.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_HOSTVER register
+ */
+/*@{*/
+#define SDHC_RD_HOSTVER(base)    (SDHC_HOSTVER_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_HOSTVER bitfields
+ */
+
+/*!
+ * @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
+ *
+ * These status bits indicate the host controller specification version.
+ *
+ * Values:
+ * - 0b00000001 - SD host specification version 2.0, supports test event
+ *     register and ADMA.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HOSTVER_SVN field. */
+#define SDHC_RD_HOSTVER_SVN(base) ((SDHC_HOSTVER_REG(base) & SDHC_HOSTVER_SVN_MASK) >> SDHC_HOSTVER_SVN_SHIFT)
+#define SDHC_BRD_HOSTVER_SVN(base) (SDHC_RD_HOSTVER_SVN(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
+ *
+ * These status bits are reserved for the vendor version number. The host driver
+ * shall not use this status.
+ *
+ * Values:
+ * - 0b00000000 - Freescale SDHC version 1.0
+ * - 0b00010000 - Freescale SDHC version 2.0
+ * - 0b00010001 - Freescale SDHC version 2.1
+ * - 0b00010010 - Freescale SDHC version 2.2
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HOSTVER_VVN field. */
+#define SDHC_RD_HOSTVER_VVN(base) ((SDHC_HOSTVER_REG(base) & SDHC_HOSTVER_VVN_MASK) >> SDHC_HOSTVER_VVN_SHIFT)
+#define SDHC_BRD_HOSTVER_VVN(base) (SDHC_RD_HOSTVER_VVN(base))
+/*@}*/
+
+/*
+ * MK64F12 SIM
+ *
+ * System Integration Module
+ *
+ * Registers defined in this header file:
+ * - SIM_SOPT1 - System Options Register 1
+ * - SIM_SOPT1CFG - SOPT1 Configuration Register
+ * - SIM_SOPT2 - System Options Register 2
+ * - SIM_SOPT4 - System Options Register 4
+ * - SIM_SOPT5 - System Options Register 5
+ * - SIM_SOPT7 - System Options Register 7
+ * - SIM_SDID - System Device Identification Register
+ * - SIM_SCGC1 - System Clock Gating Control Register 1
+ * - SIM_SCGC2 - System Clock Gating Control Register 2
+ * - SIM_SCGC3 - System Clock Gating Control Register 3
+ * - SIM_SCGC4 - System Clock Gating Control Register 4
+ * - SIM_SCGC5 - System Clock Gating Control Register 5
+ * - SIM_SCGC6 - System Clock Gating Control Register 6
+ * - SIM_SCGC7 - System Clock Gating Control Register 7
+ * - SIM_CLKDIV1 - System Clock Divider Register 1
+ * - SIM_CLKDIV2 - System Clock Divider Register 2
+ * - SIM_FCFG1 - Flash Configuration Register 1
+ * - SIM_FCFG2 - Flash Configuration Register 2
+ * - SIM_UIDH - Unique Identification Register High
+ * - SIM_UIDMH - Unique Identification Register Mid-High
+ * - SIM_UIDML - Unique Identification Register Mid Low
+ * - SIM_UIDL - Unique Identification Register Low
+ */
+
+#define SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */
+#define SIM_IDX (0U) /*!< Instance number for SIM. */
+
+/*******************************************************************************
+ * SIM_SOPT1 - System Options Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1 - System Options Register 1 (RW)
+ *
+ * Reset value: 0x80000000U
+ *
+ * The SOPT1 register is only reset on POR or LVD.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1 register
+ */
+/*@{*/
+#define SIM_RD_SOPT1(base)       (SIM_SOPT1_REG(base))
+#define SIM_WR_SOPT1(base, value) (SIM_SOPT1_REG(base) = (value))
+#define SIM_RMW_SOPT1(base, mask, value) (SIM_WR_SOPT1(base, (SIM_RD_SOPT1(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) |  (value)))
+#define SIM_CLR_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) & ~(value)))
+#define SIM_TOG_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
+ *
+ * This field specifies the amount of system RAM available on the device.
+ *
+ * Values:
+ * - 0b0001 - 8 KB
+ * - 0b0011 - 16 KB
+ * - 0b0100 - 24 KB
+ * - 0b0101 - 32 KB
+ * - 0b0110 - 48 KB
+ * - 0b0111 - 64 KB
+ * - 0b1000 - 96 KB
+ * - 0b1001 - 128 KB
+ * - 0b1011 - 256 KB
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */
+#define SIM_RD_SOPT1_RAMSIZE(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_RAMSIZE_MASK) >> SIM_SOPT1_RAMSIZE_SHIFT)
+#define SIM_BRD_SOPT1_RAMSIZE(base) (SIM_RD_SOPT1_RAMSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
+ *
+ * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
+ * only on POR/LVD.
+ *
+ * Values:
+ * - 0b00 - System oscillator (OSC32KCLK)
+ * - 0b01 - Reserved
+ * - 0b10 - RTC 32.768kHz oscillator
+ * - 0b11 - LPO 1 kHz
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */
+#define SIM_RD_SOPT1_OSC32KSEL(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
+#define SIM_BRD_SOPT1_OSC32KSEL(base) (SIM_RD_SOPT1_OSC32KSEL(base))
+
+/*! @brief Set the OSC32KSEL field to a new value. */
+#define SIM_WR_SOPT1_OSC32KSEL(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_OSC32KSEL_MASK, SIM_SOPT1_OSC32KSEL(value)))
+#define SIM_BWR_SOPT1_OSC32KSEL(base, value) (SIM_WR_SOPT1_OSC32KSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * VLPR and VLPW modes.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator not in standby during VLPR and VLPW modes.
+ * - 0b1 - USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */
+#define SIM_RD_SOPT1_USBVSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBVSTBY_MASK) >> SIM_SOPT1_USBVSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBVSTBY(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT))
+
+/*! @brief Set the USBVSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBVSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBVSTBY_MASK, SIM_SOPT1_USBVSTBY(value)))
+#define SIM_BWR_SOPT1_USBVSTBY(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * Stop, VLPS, LLS and VLLS modes.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ * - 0b1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */
+#define SIM_RD_SOPT1_USBSSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBSSTBY_MASK) >> SIM_SOPT1_USBSSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBSSTBY(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT))
+
+/*! @brief Set the USBSSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBSSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBSSTBY_MASK, SIM_SOPT1_USBSSTBY(value)))
+#define SIM_BWR_SOPT1_USBSSTBY(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
+ *
+ * Controls whether the USB voltage regulator is enabled.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator is disabled.
+ * - 0b1 - USB voltage regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */
+#define SIM_RD_SOPT1_USBREGEN(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBREGEN_MASK) >> SIM_SOPT1_USBREGEN_SHIFT)
+#define SIM_BRD_SOPT1_USBREGEN(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT))
+
+/*! @brief Set the USBREGEN field to a new value. */
+#define SIM_WR_SOPT1_USBREGEN(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBREGEN_MASK, SIM_SOPT1_USBREGEN(value)))
+#define SIM_BWR_SOPT1_USBREGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT1CFG - SOPT1 Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The SOPT1CFG register is reset on System Reset not VLLS.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1CFG register
+ */
+/*@{*/
+#define SIM_RD_SOPT1CFG(base)    (SIM_SOPT1CFG_REG(base))
+#define SIM_WR_SOPT1CFG(base, value) (SIM_SOPT1CFG_REG(base) = (value))
+#define SIM_RMW_SOPT1CFG(base, mask, value) (SIM_WR_SOPT1CFG(base, (SIM_RD_SOPT1CFG(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) |  (value)))
+#define SIM_CLR_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) & ~(value)))
+#define SIM_TOG_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1CFG bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
+ *
+ * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
+ * register bit clears after a write to USBREGEN.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBREGEN cannot be written.
+ * - 0b1 - SOPT1 USBREGEN can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */
+#define SIM_RD_SOPT1CFG_URWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_URWE_MASK) >> SIM_SOPT1CFG_URWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_URWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT))
+
+/*! @brief Set the URWE field to a new value. */
+#define SIM_WR_SOPT1CFG_URWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_URWE_MASK, SIM_SOPT1CFG_URWE(value)))
+#define SIM_BWR_SOPT1CFG_URWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
+ *
+ * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
+ * This register bit clears after a write to USBVSTBY.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBVSTBY cannot be written.
+ * - 0b1 - SOPT1 USBVSTBY can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */
+#define SIM_RD_SOPT1CFG_UVSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_UVSWE_MASK) >> SIM_SOPT1CFG_UVSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_UVSWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT))
+
+/*! @brief Set the UVSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_UVSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_UVSWE_MASK, SIM_SOPT1CFG_UVSWE(value)))
+#define SIM_BWR_SOPT1CFG_UVSWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
+ *
+ * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
+ * This register bit clears after a write to USBSSTBY.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBSSTBY cannot be written.
+ * - 0b1 - SOPT1 USBSSTBY can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */
+#define SIM_RD_SOPT1CFG_USSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_USSWE_MASK) >> SIM_SOPT1CFG_USSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_USSWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT))
+
+/*! @brief Set the USSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_USSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_USSWE_MASK, SIM_SOPT1CFG_USSWE(value)))
+#define SIM_BWR_SOPT1CFG_USSWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT2 - System Options Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT2 - System Options Register 2 (RW)
+ *
+ * Reset value: 0x00001000U
+ *
+ * SOPT2 contains the controls for selecting many of the module clock source
+ * options on this device. See the Clock Distribution chapter for more information
+ * including clocking diagrams and definitions of device clocks.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT2 register
+ */
+/*@{*/
+#define SIM_RD_SOPT2(base)       (SIM_SOPT2_REG(base))
+#define SIM_WR_SOPT2(base, value) (SIM_SOPT2_REG(base) = (value))
+#define SIM_RMW_SOPT2(base, mask, value) (SIM_WR_SOPT2(base, (SIM_RD_SOPT2(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) |  (value)))
+#define SIM_CLR_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) & ~(value)))
+#define SIM_TOG_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
+ *
+ * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
+ * RTC_CLKOUT pin.
+ *
+ * Values:
+ * - 0b0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
+ * - 0b1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */
+#define SIM_RD_SOPT2_RTCCLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RTCCLKOUTSEL_MASK) >> SIM_SOPT2_RTCCLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_RTCCLKOUTSEL(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT))
+
+/*! @brief Set the RTCCLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_RTCCLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RTCCLKOUTSEL_MASK, SIM_SOPT2_RTCCLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_RTCCLKOUTSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
+ *
+ * Selects the clock to output on the CLKOUT pin.
+ *
+ * Values:
+ * - 0b000 - FlexBus CLKOUT
+ * - 0b001 - Reserved
+ * - 0b010 - Flash clock
+ * - 0b011 - LPO clock (1 kHz)
+ * - 0b100 - MCGIRCLK
+ * - 0b101 - RTC 32.768kHz clock
+ * - 0b110 - OSCERCLK0
+ * - 0b111 - IRC 48 MHz clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */
+#define SIM_RD_SOPT2_CLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_CLKOUTSEL_MASK) >> SIM_SOPT2_CLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_CLKOUTSEL(base) (SIM_RD_SOPT2_CLKOUTSEL(base))
+
+/*! @brief Set the CLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_CLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_CLKOUTSEL_MASK, SIM_SOPT2_CLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_CLKOUTSEL(base, value) (SIM_WR_SOPT2_CLKOUTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
+ *
+ * If flash security is enabled, then this field affects what CPU operations can
+ * access off-chip via the FlexBus interface. This field has no effect if flash
+ * security is not enabled.
+ *
+ * Values:
+ * - 0b00 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 0b01 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 0b10 - Off-chip instruction accesses are disallowed. Data accesses are
+ *     allowed.
+ * - 0b11 - Off-chip instruction accesses and data accesses are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_FBSL field. */
+#define SIM_RD_SOPT2_FBSL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_FBSL_MASK) >> SIM_SOPT2_FBSL_SHIFT)
+#define SIM_BRD_SOPT2_FBSL(base) (SIM_RD_SOPT2_FBSL(base))
+
+/*! @brief Set the FBSL field to a new value. */
+#define SIM_WR_SOPT2_FBSL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_FBSL_MASK, SIM_SOPT2_FBSL(value)))
+#define SIM_BWR_SOPT2_FBSL(base, value) (SIM_WR_SOPT2_FBSL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
+ *
+ * Controls the output drive strength of the PTD7 pin by selecting either one or
+ * two pads to drive it.
+ *
+ * Values:
+ * - 0b0 - Single-pad drive strength for PTD7.
+ * - 0b1 - Double pad drive strength for PTD7.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_PTD7PAD field. */
+#define SIM_RD_SOPT2_PTD7PAD(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_PTD7PAD_MASK) >> SIM_SOPT2_PTD7PAD_SHIFT)
+#define SIM_BRD_SOPT2_PTD7PAD(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_PTD7PAD_SHIFT))
+
+/*! @brief Set the PTD7PAD field to a new value. */
+#define SIM_WR_SOPT2_PTD7PAD(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_PTD7PAD_MASK, SIM_SOPT2_PTD7PAD(value)))
+#define SIM_BWR_SOPT2_PTD7PAD(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_PTD7PAD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
+ *
+ * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
+ * clock source.
+ *
+ * Values:
+ * - 0b0 - MCGOUTCLK
+ * - 0b1 - Core/system clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */
+#define SIM_RD_SOPT2_TRACECLKSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TRACECLKSEL_MASK) >> SIM_SOPT2_TRACECLKSEL_SHIFT)
+#define SIM_BRD_SOPT2_TRACECLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_TRACECLKSEL_SHIFT))
+
+/*! @brief Set the TRACECLKSEL field to a new value. */
+#define SIM_WR_SOPT2_TRACECLKSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TRACECLKSEL_MASK, SIM_SOPT2_TRACECLKSEL(value)))
+#define SIM_BWR_SOPT2_TRACECLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_TRACECLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
+ *
+ * Selects the high frequency clock for various peripheral clocking options.
+ *
+ * Values:
+ * - 0b00 - MCGFLLCLK clock
+ * - 0b01 - MCGPLLCLK clock
+ * - 0b10 - Reserved
+ * - 0b11 - IRC48 MHz clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */
+#define SIM_RD_SOPT2_PLLFLLSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
+#define SIM_BRD_SOPT2_PLLFLLSEL(base) (SIM_RD_SOPT2_PLLFLLSEL(base))
+
+/*! @brief Set the PLLFLLSEL field to a new value. */
+#define SIM_WR_SOPT2_PLLFLLSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_PLLFLLSEL_MASK, SIM_SOPT2_PLLFLLSEL(value)))
+#define SIM_BWR_SOPT2_PLLFLLSEL(base, value) (SIM_WR_SOPT2_PLLFLLSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field USBSRC[18] (RW)
+ *
+ * Selects the clock source for the USB 48 MHz clock.
+ *
+ * Values:
+ * - 0b0 - External bypass clock (USB_CLKIN).
+ * - 0b1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
+ *     SIM_CLKDIV2[USBFRAC, USBDIV].
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_USBSRC field. */
+#define SIM_RD_SOPT2_USBSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_USBSRC_MASK) >> SIM_SOPT2_USBSRC_SHIFT)
+#define SIM_BRD_SOPT2_USBSRC(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT))
+
+/*! @brief Set the USBSRC field to a new value. */
+#define SIM_WR_SOPT2_USBSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_USBSRC_MASK, SIM_SOPT2_USBSRC(value)))
+#define SIM_BWR_SOPT2_USBSRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field RMIISRC[19] (RW)
+ *
+ * Selects the clock source for the Ethernet RMII interface
+ *
+ * Values:
+ * - 0b0 - EXTAL clock
+ * - 0b1 - External bypass clock (ENET_1588_CLKIN).
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RMIISRC field. */
+#define SIM_RD_SOPT2_RMIISRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RMIISRC_MASK) >> SIM_SOPT2_RMIISRC_SHIFT)
+#define SIM_BRD_SOPT2_RMIISRC(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RMIISRC_SHIFT))
+
+/*! @brief Set the RMIISRC field to a new value. */
+#define SIM_WR_SOPT2_RMIISRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RMIISRC_MASK, SIM_SOPT2_RMIISRC(value)))
+#define SIM_BWR_SOPT2_RMIISRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RMIISRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
+ *
+ * Selects the clock source for the Ethernet timestamp clock.
+ *
+ * Values:
+ * - 0b00 - Core/system clock.
+ * - 0b01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 0b10 - OSCERCLK clock
+ * - 0b11 - External bypass clock (ENET_1588_CLKIN).
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TIMESRC field. */
+#define SIM_RD_SOPT2_TIMESRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TIMESRC_MASK) >> SIM_SOPT2_TIMESRC_SHIFT)
+#define SIM_BRD_SOPT2_TIMESRC(base) (SIM_RD_SOPT2_TIMESRC(base))
+
+/*! @brief Set the TIMESRC field to a new value. */
+#define SIM_WR_SOPT2_TIMESRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TIMESRC_MASK, SIM_SOPT2_TIMESRC(value)))
+#define SIM_BWR_SOPT2_TIMESRC(base, value) (SIM_WR_SOPT2_TIMESRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
+ *
+ * Selects the clock source for the SDHC clock .
+ *
+ * Values:
+ * - 0b00 - Core/system clock.
+ * - 0b01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 0b10 - OSCERCLK clock
+ * - 0b11 - External bypass clock (SDHC0_CLKIN)
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_SDHCSRC field. */
+#define SIM_RD_SOPT2_SDHCSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_SDHCSRC_MASK) >> SIM_SOPT2_SDHCSRC_SHIFT)
+#define SIM_BRD_SOPT2_SDHCSRC(base) (SIM_RD_SOPT2_SDHCSRC(base))
+
+/*! @brief Set the SDHCSRC field to a new value. */
+#define SIM_WR_SOPT2_SDHCSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_SDHCSRC_MASK, SIM_SOPT2_SDHCSRC(value)))
+#define SIM_BWR_SOPT2_SDHCSRC(base, value) (SIM_WR_SOPT2_SDHCSRC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT4 - System Options Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT4 - System Options Register 4 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT4 register
+ */
+/*@{*/
+#define SIM_RD_SOPT4(base)       (SIM_SOPT4_REG(base))
+#define SIM_WR_SOPT4(base, value) (SIM_SOPT4_REG(base) = (value))
+#define SIM_RMW_SOPT4(base, mask, value) (SIM_WR_SOPT4(base, (SIM_RD_SOPT4(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) |  (value)))
+#define SIM_CLR_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) & ~(value)))
+#define SIM_TOG_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
+ *
+ * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */
+#define SIM_RD_SOPT4_FTM0FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT0_MASK) >> SIM_SOPT4_FTM0FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT0_SHIFT))
+
+/*! @brief Set the FTM0FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT0_MASK, SIM_SOPT4_FTM0FLT0(value)))
+#define SIM_BWR_SOPT4_FTM0FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
+ *
+ * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT1 pin
+ * - 0b1 - CMP1 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */
+#define SIM_RD_SOPT4_FTM0FLT1(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT1_MASK) >> SIM_SOPT4_FTM0FLT1_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT1(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT1_SHIFT))
+
+/*! @brief Set the FTM0FLT1 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT1(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT1_MASK, SIM_SOPT4_FTM0FLT1(value)))
+#define SIM_BWR_SOPT4_FTM0FLT1(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
+ *
+ * Selects the source of FTM0 fault 2. The pin source for fault 2 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT2 pin
+ * - 0b1 - CMP2 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. */
+#define SIM_RD_SOPT4_FTM0FLT2(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT2_MASK) >> SIM_SOPT4_FTM0FLT2_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT2(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT2_SHIFT))
+
+/*! @brief Set the FTM0FLT2 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT2(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT2_MASK, SIM_SOPT4_FTM0FLT2(value)))
+#define SIM_BWR_SOPT4_FTM0FLT2(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
+ *
+ * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM1_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */
+#define SIM_RD_SOPT4_FTM1FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1FLT0_MASK) >> SIM_SOPT4_FTM1FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM1FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1FLT0_SHIFT))
+
+/*! @brief Set the FTM1FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM1FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1FLT0_MASK, SIM_SOPT4_FTM1FLT0(value)))
+#define SIM_BWR_SOPT4_FTM1FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
+ *
+ * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0b0 - FTM2_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */
+#define SIM_RD_SOPT4_FTM2FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2FLT0_MASK) >> SIM_SOPT4_FTM2FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM2FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2FLT0_SHIFT))
+
+/*! @brief Set the FTM2FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM2FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2FLT0_MASK, SIM_SOPT4_FTM2FLT0(value)))
+#define SIM_BWR_SOPT4_FTM2FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
+ *
+ * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0b0 - FTM3_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */
+#define SIM_RD_SOPT4_FTM3FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3FLT0_MASK) >> SIM_SOPT4_FTM3FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM3FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3FLT0_SHIFT))
+
+/*! @brief Set the FTM3FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM3FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3FLT0_MASK, SIM_SOPT4_FTM3FLT0(value)))
+#define SIM_BWR_SOPT4_FTM3FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
+ *
+ * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0b00 - FTM1_CH0 signal
+ * - 0b01 - CMP0 output
+ * - 0b10 - CMP1 output
+ * - 0b11 - USB start of frame pulse
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */
+#define SIM_RD_SOPT4_FTM1CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1CH0SRC_MASK) >> SIM_SOPT4_FTM1CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM1CH0SRC(base) (SIM_RD_SOPT4_FTM1CH0SRC(base))
+
+/*! @brief Set the FTM1CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM1CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1CH0SRC_MASK, SIM_SOPT4_FTM1CH0SRC(value)))
+#define SIM_BWR_SOPT4_FTM1CH0SRC(base, value) (SIM_WR_SOPT4_FTM1CH0SRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
+ *
+ * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0b00 - FTM2_CH0 signal
+ * - 0b01 - CMP0 output
+ * - 0b10 - CMP1 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */
+#define SIM_RD_SOPT4_FTM2CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2CH0SRC_MASK) >> SIM_SOPT4_FTM2CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM2CH0SRC(base) (SIM_RD_SOPT4_FTM2CH0SRC(base))
+
+/*! @brief Set the FTM2CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM2CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2CH0SRC_MASK, SIM_SOPT4_FTM2CH0SRC(value)))
+#define SIM_BWR_SOPT4_FTM2CH0SRC(base, value) (SIM_WR_SOPT4_FTM2CH0SRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM0 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM_CLK0 pin
+ * - 0b1 - FTM_CLK1 pin
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */
+#define SIM_RD_SOPT4_FTM0CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0CLKSEL_MASK) >> SIM_SOPT4_FTM0CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM0CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0CLKSEL_SHIFT))
+
+/*! @brief Set the FTM0CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM0CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0CLKSEL_MASK, SIM_SOPT4_FTM0CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM0CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM1 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM_CLK0 pin
+ * - 0b1 - FTM_CLK1 pin
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */
+#define SIM_RD_SOPT4_FTM1CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1CLKSEL_MASK) >> SIM_SOPT4_FTM1CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM1CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1CLKSEL_SHIFT))
+
+/*! @brief Set the FTM1CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM1CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1CLKSEL_MASK, SIM_SOPT4_FTM1CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM1CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM2 module. The
+ * selected pin must also be configured for the FTM2 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM2 external clock driven by FTM_CLK0 pin.
+ * - 0b1 - FTM2 external clock driven by FTM_CLK1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */
+#define SIM_RD_SOPT4_FTM2CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2CLKSEL_MASK) >> SIM_SOPT4_FTM2CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM2CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2CLKSEL_SHIFT))
+
+/*! @brief Set the FTM2CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM2CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2CLKSEL_MASK, SIM_SOPT4_FTM2CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM2CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM3 module. The
+ * selected pin must also be configured for the FTM3 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM3 external clock driven by FTM_CLK0 pin.
+ * - 0b1 - FTM3 external clock driven by FTM_CLK1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */
+#define SIM_RD_SOPT4_FTM3CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3CLKSEL_MASK) >> SIM_SOPT4_FTM3CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM3CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3CLKSEL_SHIFT))
+
+/*! @brief Set the FTM3CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM3CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3CLKSEL_MASK, SIM_SOPT4_FTM3CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM3CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 0.
+ *
+ * Values:
+ * - 0b0 - HSCMP0 output drives FTM0 hardware trigger 0
+ * - 0b1 - FTM1 channel match drives FTM0 hardware trigger 0
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */
+#define SIM_RD_SOPT4_FTM0TRG0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0TRG0SRC_MASK) >> SIM_SOPT4_FTM0TRG0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM0TRG0SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG0SRC_SHIFT))
+
+/*! @brief Set the FTM0TRG0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM0TRG0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0TRG0SRC_MASK, SIM_SOPT4_FTM0TRG0SRC(value)))
+#define SIM_BWR_SOPT4_FTM0TRG0SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG0SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 1.
+ *
+ * Values:
+ * - 0b0 - PDB output trigger 1 drives FTM0 hardware trigger 1
+ * - 0b1 - FTM2 channel match drives FTM0 hardware trigger 1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */
+#define SIM_RD_SOPT4_FTM0TRG1SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0TRG1SRC_MASK) >> SIM_SOPT4_FTM0TRG1SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM0TRG1SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG1SRC_SHIFT))
+
+/*! @brief Set the FTM0TRG1SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM0TRG1SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0TRG1SRC_MASK, SIM_SOPT4_FTM0TRG1SRC(value)))
+#define SIM_BWR_SOPT4_FTM0TRG1SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG1SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 0.
+ *
+ * Values:
+ * - 0b0 - Reserved
+ * - 0b1 - FTM1 channel match drives FTM3 hardware trigger 0
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */
+#define SIM_RD_SOPT4_FTM3TRG0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3TRG0SRC_MASK) >> SIM_SOPT4_FTM3TRG0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM3TRG0SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG0SRC_SHIFT))
+
+/*! @brief Set the FTM3TRG0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM3TRG0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3TRG0SRC_MASK, SIM_SOPT4_FTM3TRG0SRC(value)))
+#define SIM_BWR_SOPT4_FTM3TRG0SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG0SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 1.
+ *
+ * Values:
+ * - 0b0 - Reserved
+ * - 0b1 - FTM2 channel match drives FTM3 hardware trigger 1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */
+#define SIM_RD_SOPT4_FTM3TRG1SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3TRG1SRC_MASK) >> SIM_SOPT4_FTM3TRG1SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM3TRG1SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG1SRC_SHIFT))
+
+/*! @brief Set the FTM3TRG1SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM3TRG1SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3TRG1SRC_MASK, SIM_SOPT4_FTM3TRG1SRC(value)))
+#define SIM_BWR_SOPT4_FTM3TRG1SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG1SRC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT5 - System Options Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT5 - System Options Register 5 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT5 register
+ */
+/*@{*/
+#define SIM_RD_SOPT5(base)       (SIM_SOPT5_REG(base))
+#define SIM_WR_SOPT5(base, value) (SIM_SOPT5_REG(base) = (value))
+#define SIM_RMW_SOPT5(base, mask, value) (SIM_WR_SOPT5(base, (SIM_RD_SOPT5(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) |  (value)))
+#define SIM_CLR_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) & ~(value)))
+#define SIM_TOG_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
+ *
+ * Selects the source for the UART 0 transmit data.
+ *
+ * Values:
+ * - 0b00 - UART0_TX pin
+ * - 0b01 - UART0_TX pin modulated with FTM1 channel 0 output
+ * - 0b10 - UART0_TX pin modulated with FTM2 channel 0 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */
+#define SIM_RD_SOPT5_UART0TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART0TXSRC_MASK) >> SIM_SOPT5_UART0TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART0TXSRC(base) (SIM_RD_SOPT5_UART0TXSRC(base))
+
+/*! @brief Set the UART0TXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART0TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART0TXSRC_MASK, SIM_SOPT5_UART0TXSRC(value)))
+#define SIM_BWR_SOPT5_UART0TXSRC(base, value) (SIM_WR_SOPT5_UART0TXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
+ *
+ * Selects the source for the UART 0 receive data.
+ *
+ * Values:
+ * - 0b00 - UART0_RX pin
+ * - 0b01 - CMP0
+ * - 0b10 - CMP1
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */
+#define SIM_RD_SOPT5_UART0RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART0RXSRC_MASK) >> SIM_SOPT5_UART0RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART0RXSRC(base) (SIM_RD_SOPT5_UART0RXSRC(base))
+
+/*! @brief Set the UART0RXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART0RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART0RXSRC_MASK, SIM_SOPT5_UART0RXSRC(value)))
+#define SIM_BWR_SOPT5_UART0RXSRC(base, value) (SIM_WR_SOPT5_UART0RXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
+ *
+ * Selects the source for the UART 1 transmit data.
+ *
+ * Values:
+ * - 0b00 - UART1_TX pin
+ * - 0b01 - UART1_TX pin modulated with FTM1 channel 0 output
+ * - 0b10 - UART1_TX pin modulated with FTM2 channel 0 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */
+#define SIM_RD_SOPT5_UART1TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART1TXSRC_MASK) >> SIM_SOPT5_UART1TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART1TXSRC(base) (SIM_RD_SOPT5_UART1TXSRC(base))
+
+/*! @brief Set the UART1TXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART1TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART1TXSRC_MASK, SIM_SOPT5_UART1TXSRC(value)))
+#define SIM_BWR_SOPT5_UART1TXSRC(base, value) (SIM_WR_SOPT5_UART1TXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
+ *
+ * Selects the source for the UART 1 receive data.
+ *
+ * Values:
+ * - 0b00 - UART1_RX pin
+ * - 0b01 - CMP0
+ * - 0b10 - CMP1
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */
+#define SIM_RD_SOPT5_UART1RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART1RXSRC_MASK) >> SIM_SOPT5_UART1RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART1RXSRC(base) (SIM_RD_SOPT5_UART1RXSRC(base))
+
+/*! @brief Set the UART1RXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART1RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART1RXSRC_MASK, SIM_SOPT5_UART1RXSRC(value)))
+#define SIM_BWR_SOPT5_UART1RXSRC(base, value) (SIM_WR_SOPT5_UART1RXSRC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT7 - System Options Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT7 - System Options Register 7 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT7 register
+ */
+/*@{*/
+#define SIM_RD_SOPT7(base)       (SIM_SOPT7_REG(base))
+#define SIM_WR_SOPT7(base, value) (SIM_SOPT7_REG(base) = (value))
+#define SIM_RMW_SOPT7(base, mask, value) (SIM_WR_SOPT7(base, (SIM_RD_SOPT7(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) |  (value)))
+#define SIM_CLR_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) & ~(value)))
+#define SIM_TOG_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
+ *
+ * Selects the ADC0 trigger source when alternative triggers are functional in
+ * stop and VLPS modes. .
+ *
+ * Values:
+ * - 0b0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0b0001 - High speed comparator 0 output
+ * - 0b0010 - High speed comparator 1 output
+ * - 0b0011 - High speed comparator 2 output
+ * - 0b0100 - PIT trigger 0
+ * - 0b0101 - PIT trigger 1
+ * - 0b0110 - PIT trigger 2
+ * - 0b0111 - PIT trigger 3
+ * - 0b1000 - FTM0 trigger
+ * - 0b1001 - FTM1 trigger
+ * - 0b1010 - FTM2 trigger
+ * - 0b1011 - FTM3 trigger
+ * - 0b1100 - RTC alarm
+ * - 0b1101 - RTC seconds
+ * - 0b1110 - Low-power timer (LPTMR) trigger
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */
+#define SIM_RD_SOPT7_ADC0TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0TRGSEL_MASK) >> SIM_SOPT7_ADC0TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0TRGSEL(base) (SIM_RD_SOPT7_ADC0TRGSEL(base))
+
+/*! @brief Set the ADC0TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0TRGSEL_MASK, SIM_SOPT7_ADC0TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0TRGSEL(base, value) (SIM_WR_SOPT7_ADC0TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
+ *
+ * Selects the ADC0 pre-trigger source when alternative triggers are enabled
+ * through ADC0ALTTRGEN.
+ *
+ * Values:
+ * - 0b0 - Pre-trigger A
+ * - 0b1 - Pre-trigger B
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC0PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0PRETRGSEL_MASK) >> SIM_SOPT7_ADC0PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0PRETRGSEL(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT))
+
+/*! @brief Set the ADC0PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0PRETRGSEL_MASK, SIM_SOPT7_ADC0PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0PRETRGSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
+ *
+ * Enable alternative conversion triggers for ADC0.
+ *
+ * Values:
+ * - 0b0 - PDB trigger selected for ADC0.
+ * - 0b1 - Alternate trigger selected for ADC0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC0ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0ALTTRGEN_MASK) >> SIM_SOPT7_ADC0ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC0ALTTRGEN(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT))
+
+/*! @brief Set the ADC0ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC0ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0ALTTRGEN_MASK, SIM_SOPT7_ADC0ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC0ALTTRGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
+ *
+ * Selects the ADC1 trigger source when alternative triggers are functional in
+ * stop and VLPS modes.
+ *
+ * Values:
+ * - 0b0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0b0001 - High speed comparator 0 output
+ * - 0b0010 - High speed comparator 1 output
+ * - 0b0011 - High speed comparator 2 output
+ * - 0b0100 - PIT trigger 0
+ * - 0b0101 - PIT trigger 1
+ * - 0b0110 - PIT trigger 2
+ * - 0b0111 - PIT trigger 3
+ * - 0b1000 - FTM0 trigger
+ * - 0b1001 - FTM1 trigger
+ * - 0b1010 - FTM2 trigger
+ * - 0b1011 - FTM3 trigger
+ * - 0b1100 - RTC alarm
+ * - 0b1101 - RTC seconds
+ * - 0b1110 - Low-power timer (LPTMR) trigger
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */
+#define SIM_RD_SOPT7_ADC1TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1TRGSEL_MASK) >> SIM_SOPT7_ADC1TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC1TRGSEL(base) (SIM_RD_SOPT7_ADC1TRGSEL(base))
+
+/*! @brief Set the ADC1TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC1TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1TRGSEL_MASK, SIM_SOPT7_ADC1TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC1TRGSEL(base, value) (SIM_WR_SOPT7_ADC1TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
+ *
+ * Selects the ADC1 pre-trigger source when alternative triggers are enabled
+ * through ADC1ALTTRGEN.
+ *
+ * Values:
+ * - 0b0 - Pre-trigger A selected for ADC1.
+ * - 0b1 - Pre-trigger B selected for ADC1.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC1PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1PRETRGSEL_MASK) >> SIM_SOPT7_ADC1PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC1PRETRGSEL(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1PRETRGSEL_SHIFT))
+
+/*! @brief Set the ADC1PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC1PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1PRETRGSEL_MASK, SIM_SOPT7_ADC1PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC1PRETRGSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1PRETRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
+ *
+ * Enable alternative conversion triggers for ADC1.
+ *
+ * Values:
+ * - 0b0 - PDB trigger selected for ADC1
+ * - 0b1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC1ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1ALTTRGEN_MASK) >> SIM_SOPT7_ADC1ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC1ALTTRGEN(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1ALTTRGEN_SHIFT))
+
+/*! @brief Set the ADC1ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC1ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1ALTTRGEN_MASK, SIM_SOPT7_ADC1ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC1ALTTRGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1ALTTRGEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SDID - System Device Identification Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SDID - System Device Identification Register (RO)
+ *
+ * Reset value: 0x00000380U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SDID register
+ */
+/*@{*/
+#define SIM_RD_SDID(base)        (SIM_SDID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SDID bitfields
+ */
+
+/*!
+ * @name Register SIM_SDID, field PINID[3:0] (RO)
+ *
+ * Specifies the pincount of the device.
+ *
+ * Values:
+ * - 0b0000 - Reserved
+ * - 0b0001 - Reserved
+ * - 0b0010 - 32-pin
+ * - 0b0011 - Reserved
+ * - 0b0100 - 48-pin
+ * - 0b0101 - 64-pin
+ * - 0b0110 - 80-pin
+ * - 0b0111 - 81-pin or 121-pin
+ * - 0b1000 - 100-pin
+ * - 0b1001 - 121-pin
+ * - 0b1010 - 144-pin
+ * - 0b1011 - Custom pinout (WLCSP)
+ * - 0b1100 - 169-pin
+ * - 0b1101 - Reserved
+ * - 0b1110 - 256-pin
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_PINID field. */
+#define SIM_RD_SDID_PINID(base) ((SIM_SDID_REG(base) & SIM_SDID_PINID_MASK) >> SIM_SDID_PINID_SHIFT)
+#define SIM_BRD_SDID_PINID(base) (SIM_RD_SDID_PINID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMID[6:4] (RO)
+ *
+ * This field is maintained for compatibility only, but has been superceded by
+ * the SERIESID, FAMILYID and SUBFAMID fields in this register.
+ *
+ * Values:
+ * - 0b000 - K1x Family (without tamper)
+ * - 0b001 - K2x Family (without tamper)
+ * - 0b010 - K3x Family or K1x/K6x Family (with tamper)
+ * - 0b011 - K4x Family or K2x Family (with tamper)
+ * - 0b100 - K6x Family (without tamper)
+ * - 0b101 - K7x Family
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMID field. */
+#define SIM_RD_SDID_FAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMID_MASK) >> SIM_SDID_FAMID_SHIFT)
+#define SIM_BRD_SDID_FAMID(base) (SIM_RD_SDID_FAMID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field DIEID[11:7] (RO)
+ *
+ * Specifies the silicon feature set identication number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_DIEID field. */
+#define SIM_RD_SDID_DIEID(base) ((SIM_SDID_REG(base) & SIM_SDID_DIEID_MASK) >> SIM_SDID_DIEID_SHIFT)
+#define SIM_BRD_SDID_DIEID(base) (SIM_RD_SDID_DIEID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field REVID[15:12] (RO)
+ *
+ * Specifies the silicon implementation number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_REVID field. */
+#define SIM_RD_SDID_REVID(base) ((SIM_SDID_REG(base) & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT)
+#define SIM_BRD_SDID_REVID(base) (SIM_RD_SDID_REVID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SERIESID[23:20] (RO)
+ *
+ * Specifies the Kinetis series of the device.
+ *
+ * Values:
+ * - 0b0000 - Kinetis K series
+ * - 0b0001 - Kinetis L series
+ * - 0b0101 - Kinetis W series
+ * - 0b0110 - Kinetis V series
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SERIESID field. */
+#define SIM_RD_SDID_SERIESID(base) ((SIM_SDID_REG(base) & SIM_SDID_SERIESID_MASK) >> SIM_SDID_SERIESID_SHIFT)
+#define SIM_BRD_SDID_SERIESID(base) (SIM_RD_SDID_SERIESID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
+ *
+ * Specifies the Kinetis sub-family of the device.
+ *
+ * Values:
+ * - 0b0000 - Kx0 Subfamily
+ * - 0b0001 - Kx1 Subfamily (tamper detect)
+ * - 0b0010 - Kx2 Subfamily
+ * - 0b0011 - Kx3 Subfamily (tamper detect)
+ * - 0b0100 - Kx4 Subfamily
+ * - 0b0101 - Kx5 Subfamily (tamper detect)
+ * - 0b0110 - Kx6 Subfamily
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SUBFAMID field. */
+#define SIM_RD_SDID_SUBFAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_SUBFAMID_MASK) >> SIM_SDID_SUBFAMID_SHIFT)
+#define SIM_BRD_SDID_SUBFAMID(base) (SIM_RD_SDID_SUBFAMID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
+ *
+ * Specifies the Kinetis family of the device.
+ *
+ * Values:
+ * - 0b0001 - K1x Family
+ * - 0b0010 - K2x Family
+ * - 0b0011 - K3x Family
+ * - 0b0100 - K4x Family
+ * - 0b0110 - K6x Family
+ * - 0b0111 - K7x Family
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMILYID field. */
+#define SIM_RD_SDID_FAMILYID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMILYID_MASK) >> SIM_SDID_FAMILYID_SHIFT)
+#define SIM_BRD_SDID_FAMILYID(base) (SIM_RD_SDID_FAMILYID(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC1 - System Clock Gating Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC1 register
+ */
+/*@{*/
+#define SIM_RD_SCGC1(base)       (SIM_SCGC1_REG(base))
+#define SIM_WR_SCGC1(base, value) (SIM_SCGC1_REG(base) = (value))
+#define SIM_RMW_SCGC1(base, mask, value) (SIM_WR_SCGC1(base, (SIM_RD_SCGC1(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) |  (value)))
+#define SIM_CLR_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) & ~(value)))
+#define SIM_TOG_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) ^  (value)))
+/*@}*/
+
+/* Unified clock gate bit access macros */
+#define SIM_SCGC_BIT_REG(base, index)        (*((volatile uint32_t *)&SIM_SCGC1_REG(base) + (((uint32_t)(index) >> 5) - 0U)))
+#define SIM_SCGC_BIT_SHIFT(index)            ((uint32_t)(index) & ((1U << 5) - 1U))
+#define SIM_RD_SCGC_BIT(base, index)         (SIM_SCGC_BIT_REG((base), (index)) & (1U << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BRD_SCGC_BIT(base, index)        (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_WR_SCGC_BIT(base, index, value)  (SIM_SCGC_BIT_REG((base), (index)) = (SIM_SCGC_BIT_REG((base), (index)) & ~(1U << SIM_SCGC_BIT_SHIFT(index))) | ((uint32_t)(value) << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BWR_SCGC_BIT(base, index, value) (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)) = (uint32_t)(value))
+
+/*
+ * Constants & macros for individual SIM_SCGC1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC1, field I2C2[6] (RW)
+ *
+ * This bit controls the clock gate to the I2C2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_I2C2 field. */
+#define SIM_RD_SCGC1_I2C2(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_I2C2_MASK) >> SIM_SCGC1_I2C2_SHIFT)
+#define SIM_BRD_SCGC1_I2C2(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_I2C2_SHIFT))
+
+/*! @brief Set the I2C2 field to a new value. */
+#define SIM_WR_SCGC1_I2C2(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_I2C2_MASK, SIM_SCGC1_I2C2(value)))
+#define SIM_BWR_SCGC1_I2C2(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_I2C2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC1, field UART4[10] (RW)
+ *
+ * This bit controls the clock gate to the UART4 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_UART4 field. */
+#define SIM_RD_SCGC1_UART4(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_UART4_MASK) >> SIM_SCGC1_UART4_SHIFT)
+#define SIM_BRD_SCGC1_UART4(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART4_SHIFT))
+
+/*! @brief Set the UART4 field to a new value. */
+#define SIM_WR_SCGC1_UART4(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_UART4_MASK, SIM_SCGC1_UART4(value)))
+#define SIM_BWR_SCGC1_UART4(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC1, field UART5[11] (RW)
+ *
+ * This bit controls the clock gate to the UART5 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_UART5 field. */
+#define SIM_RD_SCGC1_UART5(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_UART5_MASK) >> SIM_SCGC1_UART5_SHIFT)
+#define SIM_BRD_SCGC1_UART5(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART5_SHIFT))
+
+/*! @brief Set the UART5 field to a new value. */
+#define SIM_WR_SCGC1_UART5(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_UART5_MASK, SIM_SCGC1_UART5(value)))
+#define SIM_BWR_SCGC1_UART5(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART5_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC2 - System Clock Gating Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
+ * AIPS1, define the clock gate control bits in the SCGC2. When accessing through
+ * AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC2 register
+ */
+/*@{*/
+#define SIM_RD_SCGC2(base)       (SIM_SCGC2_REG(base))
+#define SIM_WR_SCGC2(base, value) (SIM_SCGC2_REG(base) = (value))
+#define SIM_RMW_SCGC2(base, mask, value) (SIM_WR_SCGC2(base, (SIM_RD_SCGC2(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) |  (value)))
+#define SIM_CLR_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) & ~(value)))
+#define SIM_TOG_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC2, field ENET[0] (RW)
+ *
+ * This bit controls the clock gate to the ENET module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_ENET field. */
+#define SIM_RD_SCGC2_ENET(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_ENET_MASK) >> SIM_SCGC2_ENET_SHIFT)
+#define SIM_BRD_SCGC2_ENET(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_ENET_SHIFT))
+
+/*! @brief Set the ENET field to a new value. */
+#define SIM_WR_SCGC2_ENET(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_ENET_MASK, SIM_SCGC2_ENET(value)))
+#define SIM_BWR_SCGC2_ENET(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_ENET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC2, field DAC0[12] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_DAC0 field. */
+#define SIM_RD_SCGC2_DAC0(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_DAC0_MASK) >> SIM_SCGC2_DAC0_SHIFT)
+#define SIM_BRD_SCGC2_DAC0(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC0_SHIFT))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC2_DAC0(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_DAC0_MASK, SIM_SCGC2_DAC0(value)))
+#define SIM_BWR_SCGC2_DAC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC2, field DAC1[13] (RW)
+ *
+ * This bit controls the clock gate to the DAC1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_DAC1 field. */
+#define SIM_RD_SCGC2_DAC1(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_DAC1_MASK) >> SIM_SCGC2_DAC1_SHIFT)
+#define SIM_BRD_SCGC2_DAC1(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC1_SHIFT))
+
+/*! @brief Set the DAC1 field to a new value. */
+#define SIM_WR_SCGC2_DAC1(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_DAC1_MASK, SIM_SCGC2_DAC1(value)))
+#define SIM_BWR_SCGC2_DAC1(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC3 - System Clock Gating Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
+ * through AIPS1, define the clock gate control bits in the SCGC3. When accessing
+ * through AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC3 register
+ */
+/*@{*/
+#define SIM_RD_SCGC3(base)       (SIM_SCGC3_REG(base))
+#define SIM_WR_SCGC3(base, value) (SIM_SCGC3_REG(base) = (value))
+#define SIM_RMW_SCGC3(base, mask, value) (SIM_WR_SCGC3(base, (SIM_RD_SCGC3(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) |  (value)))
+#define SIM_CLR_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) & ~(value)))
+#define SIM_TOG_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC3 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC3, field RNGA[0] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_RNGA field. */
+#define SIM_RD_SCGC3_RNGA(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_RNGA_MASK) >> SIM_SCGC3_RNGA_SHIFT)
+#define SIM_BRD_SCGC3_RNGA(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_RNGA_SHIFT))
+
+/*! @brief Set the RNGA field to a new value. */
+#define SIM_WR_SCGC3_RNGA(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_RNGA_MASK, SIM_SCGC3_RNGA(value)))
+#define SIM_BWR_SCGC3_RNGA(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_RNGA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field SPI2[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_SPI2 field. */
+#define SIM_RD_SCGC3_SPI2(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_SPI2_MASK) >> SIM_SCGC3_SPI2_SHIFT)
+#define SIM_BRD_SCGC3_SPI2(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SPI2_SHIFT))
+
+/*! @brief Set the SPI2 field to a new value. */
+#define SIM_WR_SCGC3_SPI2(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_SPI2_MASK, SIM_SCGC3_SPI2(value)))
+#define SIM_BWR_SCGC3_SPI2(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SPI2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field SDHC[17] (RW)
+ *
+ * This bit controls the clock gate to the SDHC module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_SDHC field. */
+#define SIM_RD_SCGC3_SDHC(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_SDHC_MASK) >> SIM_SCGC3_SDHC_SHIFT)
+#define SIM_BRD_SCGC3_SDHC(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SDHC_SHIFT))
+
+/*! @brief Set the SDHC field to a new value. */
+#define SIM_WR_SCGC3_SDHC(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_SDHC_MASK, SIM_SCGC3_SDHC(value)))
+#define SIM_BWR_SCGC3_SDHC(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SDHC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field FTM2[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_FTM2 field. */
+#define SIM_RD_SCGC3_FTM2(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_FTM2_MASK) >> SIM_SCGC3_FTM2_SHIFT)
+#define SIM_BRD_SCGC3_FTM2(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM2_SHIFT))
+
+/*! @brief Set the FTM2 field to a new value. */
+#define SIM_WR_SCGC3_FTM2(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_FTM2_MASK, SIM_SCGC3_FTM2(value)))
+#define SIM_BWR_SCGC3_FTM2(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field FTM3[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM3 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_FTM3 field. */
+#define SIM_RD_SCGC3_FTM3(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_FTM3_MASK) >> SIM_SCGC3_FTM3_SHIFT)
+#define SIM_BRD_SCGC3_FTM3(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM3_SHIFT))
+
+/*! @brief Set the FTM3 field to a new value. */
+#define SIM_WR_SCGC3_FTM3(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_FTM3_MASK, SIM_SCGC3_FTM3(value)))
+#define SIM_BWR_SCGC3_FTM3(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field ADC1[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_ADC1 field. */
+#define SIM_RD_SCGC3_ADC1(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_ADC1_MASK) >> SIM_SCGC3_ADC1_SHIFT)
+#define SIM_BRD_SCGC3_ADC1(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_ADC1_SHIFT))
+
+/*! @brief Set the ADC1 field to a new value. */
+#define SIM_WR_SCGC3_ADC1(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_ADC1_MASK, SIM_SCGC3_ADC1(value)))
+#define SIM_BWR_SCGC3_ADC1(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_ADC1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC4 - System Clock Gating Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
+ *
+ * Reset value: 0xF0100030U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC4 register
+ */
+/*@{*/
+#define SIM_RD_SCGC4(base)       (SIM_SCGC4_REG(base))
+#define SIM_WR_SCGC4(base, value) (SIM_SCGC4_REG(base) = (value))
+#define SIM_RMW_SCGC4(base, mask, value) (SIM_WR_SCGC4(base, (SIM_RD_SCGC4(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) |  (value)))
+#define SIM_CLR_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) & ~(value)))
+#define SIM_TOG_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC4, field EWM[1] (RW)
+ *
+ * This bit controls the clock gate to the EWM module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_EWM field. */
+#define SIM_RD_SCGC4_EWM(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_EWM_MASK) >> SIM_SCGC4_EWM_SHIFT)
+#define SIM_BRD_SCGC4_EWM(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_EWM_SHIFT))
+
+/*! @brief Set the EWM field to a new value. */
+#define SIM_WR_SCGC4_EWM(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_EWM_MASK, SIM_SCGC4_EWM(value)))
+#define SIM_BWR_SCGC4_EWM(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_EWM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMT[2] (RW)
+ *
+ * This bit controls the clock gate to the CMT module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMT field. */
+#define SIM_RD_SCGC4_CMT(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMT_MASK) >> SIM_SCGC4_CMT_SHIFT)
+#define SIM_BRD_SCGC4_CMT(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT))
+
+/*! @brief Set the CMT field to a new value. */
+#define SIM_WR_SCGC4_CMT(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMT_MASK, SIM_SCGC4_CMT(value)))
+#define SIM_BWR_SCGC4_CMT(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C0[6] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C0 field. */
+#define SIM_RD_SCGC4_I2C0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C0_MASK) >> SIM_SCGC4_I2C0_SHIFT)
+#define SIM_BRD_SCGC4_I2C0(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT))
+
+/*! @brief Set the I2C0 field to a new value. */
+#define SIM_WR_SCGC4_I2C0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C0_MASK, SIM_SCGC4_I2C0(value)))
+#define SIM_BWR_SCGC4_I2C0(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C1[7] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C1 field. */
+#define SIM_RD_SCGC4_I2C1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C1_MASK) >> SIM_SCGC4_I2C1_SHIFT)
+#define SIM_BRD_SCGC4_I2C1(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT))
+
+/*! @brief Set the I2C1 field to a new value. */
+#define SIM_WR_SCGC4_I2C1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C1_MASK, SIM_SCGC4_I2C1(value)))
+#define SIM_BWR_SCGC4_I2C1(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART0[10] (RW)
+ *
+ * This bit controls the clock gate to the UART0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART0 field. */
+#define SIM_RD_SCGC4_UART0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT)
+#define SIM_BRD_SCGC4_UART0(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART0_SHIFT))
+
+/*! @brief Set the UART0 field to a new value. */
+#define SIM_WR_SCGC4_UART0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART0_MASK, SIM_SCGC4_UART0(value)))
+#define SIM_BWR_SCGC4_UART0(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART1[11] (RW)
+ *
+ * This bit controls the clock gate to the UART1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART1 field. */
+#define SIM_RD_SCGC4_UART1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT)
+#define SIM_BRD_SCGC4_UART1(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART1_SHIFT))
+
+/*! @brief Set the UART1 field to a new value. */
+#define SIM_WR_SCGC4_UART1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART1_MASK, SIM_SCGC4_UART1(value)))
+#define SIM_BWR_SCGC4_UART1(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART2[12] (RW)
+ *
+ * This bit controls the clock gate to the UART2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART2 field. */
+#define SIM_RD_SCGC4_UART2(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT)
+#define SIM_BRD_SCGC4_UART2(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT))
+
+/*! @brief Set the UART2 field to a new value. */
+#define SIM_WR_SCGC4_UART2(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART2_MASK, SIM_SCGC4_UART2(value)))
+#define SIM_BWR_SCGC4_UART2(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART3[13] (RW)
+ *
+ * This bit controls the clock gate to the UART3 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART3 field. */
+#define SIM_RD_SCGC4_UART3(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART3_MASK) >> SIM_SCGC4_UART3_SHIFT)
+#define SIM_BRD_SCGC4_UART3(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART3_SHIFT))
+
+/*! @brief Set the UART3 field to a new value. */
+#define SIM_WR_SCGC4_UART3(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART3_MASK, SIM_SCGC4_UART3(value)))
+#define SIM_BWR_SCGC4_UART3(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field USBOTG[18] (RW)
+ *
+ * This bit controls the clock gate to the USB module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_USBOTG field. */
+#define SIM_RD_SCGC4_USBOTG(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_USBOTG_MASK) >> SIM_SCGC4_USBOTG_SHIFT)
+#define SIM_BRD_SCGC4_USBOTG(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBOTG_SHIFT))
+
+/*! @brief Set the USBOTG field to a new value. */
+#define SIM_WR_SCGC4_USBOTG(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_USBOTG_MASK, SIM_SCGC4_USBOTG(value)))
+#define SIM_BWR_SCGC4_USBOTG(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBOTG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMP[19] (RW)
+ *
+ * This bit controls the clock gate to the comparator module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMP field. */
+#define SIM_RD_SCGC4_CMP(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMP_MASK) >> SIM_SCGC4_CMP_SHIFT)
+#define SIM_BRD_SCGC4_CMP(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT))
+
+/*! @brief Set the CMP field to a new value. */
+#define SIM_WR_SCGC4_CMP(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMP_MASK, SIM_SCGC4_CMP(value)))
+#define SIM_BWR_SCGC4_CMP(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field VREF[20] (RW)
+ *
+ * This bit controls the clock gate to the VREF module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_VREF field. */
+#define SIM_RD_SCGC4_VREF(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_VREF_MASK) >> SIM_SCGC4_VREF_SHIFT)
+#define SIM_BRD_SCGC4_VREF(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT))
+
+/*! @brief Set the VREF field to a new value. */
+#define SIM_WR_SCGC4_VREF(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_VREF_MASK, SIM_SCGC4_VREF(value)))
+#define SIM_BWR_SCGC4_VREF(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC5 - System Clock Gating Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
+ *
+ * Reset value: 0x00040182U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC5 register
+ */
+/*@{*/
+#define SIM_RD_SCGC5(base)       (SIM_SCGC5_REG(base))
+#define SIM_WR_SCGC5(base, value) (SIM_SCGC5_REG(base) = (value))
+#define SIM_RMW_SCGC5(base, mask, value) (SIM_WR_SCGC5(base, (SIM_RD_SCGC5(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) |  (value)))
+#define SIM_CLR_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) & ~(value)))
+#define SIM_TOG_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC5, field LPTMR[0] (RW)
+ *
+ * This bit controls software access to the Low Power Timer module.
+ *
+ * Values:
+ * - 0b0 - Access disabled
+ * - 0b1 - Access enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_LPTMR field. */
+#define SIM_RD_SCGC5_LPTMR(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPTMR_MASK) >> SIM_SCGC5_LPTMR_SHIFT)
+#define SIM_BRD_SCGC5_LPTMR(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT))
+
+/*! @brief Set the LPTMR field to a new value. */
+#define SIM_WR_SCGC5_LPTMR(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPTMR_MASK, SIM_SCGC5_LPTMR(value)))
+#define SIM_BWR_SCGC5_LPTMR(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTA[9] (RW)
+ *
+ * This bit controls the clock gate to the Port A module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTA field. */
+#define SIM_RD_SCGC5_PORTA(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTA_MASK) >> SIM_SCGC5_PORTA_SHIFT)
+#define SIM_BRD_SCGC5_PORTA(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT))
+
+/*! @brief Set the PORTA field to a new value. */
+#define SIM_WR_SCGC5_PORTA(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTA_MASK, SIM_SCGC5_PORTA(value)))
+#define SIM_BWR_SCGC5_PORTA(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTB[10] (RW)
+ *
+ * This bit controls the clock gate to the Port B module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTB field. */
+#define SIM_RD_SCGC5_PORTB(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTB_MASK) >> SIM_SCGC5_PORTB_SHIFT)
+#define SIM_BRD_SCGC5_PORTB(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT))
+
+/*! @brief Set the PORTB field to a new value. */
+#define SIM_WR_SCGC5_PORTB(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTB_MASK, SIM_SCGC5_PORTB(value)))
+#define SIM_BWR_SCGC5_PORTB(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTC[11] (RW)
+ *
+ * This bit controls the clock gate to the Port C module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTC field. */
+#define SIM_RD_SCGC5_PORTC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTC_MASK) >> SIM_SCGC5_PORTC_SHIFT)
+#define SIM_BRD_SCGC5_PORTC(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT))
+
+/*! @brief Set the PORTC field to a new value. */
+#define SIM_WR_SCGC5_PORTC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTC_MASK, SIM_SCGC5_PORTC(value)))
+#define SIM_BWR_SCGC5_PORTC(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTD[12] (RW)
+ *
+ * This bit controls the clock gate to the Port D module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTD field. */
+#define SIM_RD_SCGC5_PORTD(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTD_MASK) >> SIM_SCGC5_PORTD_SHIFT)
+#define SIM_BRD_SCGC5_PORTD(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT))
+
+/*! @brief Set the PORTD field to a new value. */
+#define SIM_WR_SCGC5_PORTD(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTD_MASK, SIM_SCGC5_PORTD(value)))
+#define SIM_BWR_SCGC5_PORTD(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTE[13] (RW)
+ *
+ * This bit controls the clock gate to the Port E module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTE field. */
+#define SIM_RD_SCGC5_PORTE(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTE_MASK) >> SIM_SCGC5_PORTE_SHIFT)
+#define SIM_BRD_SCGC5_PORTE(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT))
+
+/*! @brief Set the PORTE field to a new value. */
+#define SIM_WR_SCGC5_PORTE(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTE_MASK, SIM_SCGC5_PORTE(value)))
+#define SIM_BWR_SCGC5_PORTE(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC6 - System Clock Gating Control Register 6
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
+ *
+ * Reset value: 0x40000001U
+ *
+ * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
+ * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
+ * When accessing through AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC6 register
+ */
+/*@{*/
+#define SIM_RD_SCGC6(base)       (SIM_SCGC6_REG(base))
+#define SIM_WR_SCGC6(base, value) (SIM_SCGC6_REG(base) = (value))
+#define SIM_RMW_SCGC6(base, mask, value) (SIM_WR_SCGC6(base, (SIM_RD_SCGC6(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) |  (value)))
+#define SIM_CLR_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) & ~(value)))
+#define SIM_TOG_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC6 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC6, field FTF[0] (RW)
+ *
+ * This bit controls the clock gate to the flash memory. Flash reads are still
+ * supported while the flash memory is clock gated, but entry into low power modes
+ * is blocked.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTF field. */
+#define SIM_RD_SCGC6_FTF(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTF_MASK) >> SIM_SCGC6_FTF_SHIFT)
+#define SIM_BRD_SCGC6_FTF(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT))
+
+/*! @brief Set the FTF field to a new value. */
+#define SIM_WR_SCGC6_FTF(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTF_MASK, SIM_SCGC6_FTF(value)))
+#define SIM_BWR_SCGC6_FTF(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA Mux module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */
+#define SIM_RD_SCGC6_DMAMUX(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DMAMUX_MASK) >> SIM_SCGC6_DMAMUX_SHIFT)
+#define SIM_BRD_SCGC6_DMAMUX(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT))
+
+/*! @brief Set the DMAMUX field to a new value. */
+#define SIM_WR_SCGC6_DMAMUX(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DMAMUX_MASK, SIM_SCGC6_DMAMUX(value)))
+#define SIM_BWR_SCGC6_DMAMUX(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
+ *
+ * This bit controls the clock gate to the FlexCAN0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. */
+#define SIM_RD_SCGC6_FLEXCAN0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FLEXCAN0_MASK) >> SIM_SCGC6_FLEXCAN0_SHIFT)
+#define SIM_BRD_SCGC6_FLEXCAN0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FLEXCAN0_SHIFT))
+
+/*! @brief Set the FLEXCAN0 field to a new value. */
+#define SIM_WR_SCGC6_FLEXCAN0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FLEXCAN0_MASK, SIM_SCGC6_FLEXCAN0(value)))
+#define SIM_BWR_SCGC6_FLEXCAN0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FLEXCAN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RNGA[9] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RNGA field. */
+#define SIM_RD_SCGC6_RNGA(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RNGA_MASK) >> SIM_SCGC6_RNGA_SHIFT)
+#define SIM_BRD_SCGC6_RNGA(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RNGA_SHIFT))
+
+/*! @brief Set the RNGA field to a new value. */
+#define SIM_WR_SCGC6_RNGA(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RNGA_MASK, SIM_SCGC6_RNGA(value)))
+#define SIM_BWR_SCGC6_RNGA(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RNGA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field SPI0[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_SPI0 field. */
+#define SIM_RD_SCGC6_SPI0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI0_MASK) >> SIM_SCGC6_SPI0_SHIFT)
+#define SIM_BRD_SCGC6_SPI0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT))
+
+/*! @brief Set the SPI0 field to a new value. */
+#define SIM_WR_SCGC6_SPI0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI0_MASK, SIM_SCGC6_SPI0(value)))
+#define SIM_BWR_SCGC6_SPI0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field SPI1[13] (RW)
+ *
+ * This bit controls the clock gate to the SPI1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_SPI1 field. */
+#define SIM_RD_SCGC6_SPI1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI1_MASK) >> SIM_SCGC6_SPI1_SHIFT)
+#define SIM_BRD_SCGC6_SPI1(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT))
+
+/*! @brief Set the SPI1 field to a new value. */
+#define SIM_WR_SCGC6_SPI1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI1_MASK, SIM_SCGC6_SPI1(value)))
+#define SIM_BWR_SCGC6_SPI1(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field I2S[15] (RW)
+ *
+ * This bit controls the clock gate to the I 2 S module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_I2S field. */
+#define SIM_RD_SCGC6_I2S(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_I2S_MASK) >> SIM_SCGC6_I2S_SHIFT)
+#define SIM_BRD_SCGC6_I2S(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT))
+
+/*! @brief Set the I2S field to a new value. */
+#define SIM_WR_SCGC6_I2S(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_I2S_MASK, SIM_SCGC6_I2S(value)))
+#define SIM_BWR_SCGC6_I2S(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field CRC[18] (RW)
+ *
+ * This bit controls the clock gate to the CRC module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_CRC field. */
+#define SIM_RD_SCGC6_CRC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_CRC_MASK) >> SIM_SCGC6_CRC_SHIFT)
+#define SIM_BRD_SCGC6_CRC(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_CRC_SHIFT))
+
+/*! @brief Set the CRC field to a new value. */
+#define SIM_WR_SCGC6_CRC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_CRC_MASK, SIM_SCGC6_CRC(value)))
+#define SIM_BWR_SCGC6_CRC(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_CRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field USBDCD[21] (RW)
+ *
+ * This bit controls the clock gate to the USB DCD module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_USBDCD field. */
+#define SIM_RD_SCGC6_USBDCD(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_USBDCD_MASK) >> SIM_SCGC6_USBDCD_SHIFT)
+#define SIM_BRD_SCGC6_USBDCD(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_USBDCD_SHIFT))
+
+/*! @brief Set the USBDCD field to a new value. */
+#define SIM_WR_SCGC6_USBDCD(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_USBDCD_MASK, SIM_SCGC6_USBDCD(value)))
+#define SIM_BWR_SCGC6_USBDCD(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_USBDCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PDB[22] (RW)
+ *
+ * This bit controls the clock gate to the PDB module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PDB field. */
+#define SIM_RD_SCGC6_PDB(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PDB_MASK) >> SIM_SCGC6_PDB_SHIFT)
+#define SIM_BRD_SCGC6_PDB(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PDB_SHIFT))
+
+/*! @brief Set the PDB field to a new value. */
+#define SIM_WR_SCGC6_PDB(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PDB_MASK, SIM_SCGC6_PDB(value)))
+#define SIM_BWR_SCGC6_PDB(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PDB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PIT[23] (RW)
+ *
+ * This bit controls the clock gate to the PIT module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PIT field. */
+#define SIM_RD_SCGC6_PIT(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PIT_MASK) >> SIM_SCGC6_PIT_SHIFT)
+#define SIM_BRD_SCGC6_PIT(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT))
+
+/*! @brief Set the PIT field to a new value. */
+#define SIM_WR_SCGC6_PIT(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PIT_MASK, SIM_SCGC6_PIT(value)))
+#define SIM_BWR_SCGC6_PIT(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM0[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM0 field. */
+#define SIM_RD_SCGC6_FTM0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM0_MASK) >> SIM_SCGC6_FTM0_SHIFT)
+#define SIM_BRD_SCGC6_FTM0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM0_SHIFT))
+
+/*! @brief Set the FTM0 field to a new value. */
+#define SIM_WR_SCGC6_FTM0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM0_MASK, SIM_SCGC6_FTM0(value)))
+#define SIM_BWR_SCGC6_FTM0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM1[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM1 field. */
+#define SIM_RD_SCGC6_FTM1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM1_MASK) >> SIM_SCGC6_FTM1_SHIFT)
+#define SIM_BRD_SCGC6_FTM1(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM1_SHIFT))
+
+/*! @brief Set the FTM1 field to a new value. */
+#define SIM_WR_SCGC6_FTM1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM1_MASK, SIM_SCGC6_FTM1(value)))
+#define SIM_BWR_SCGC6_FTM1(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM2[26] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM2 field. */
+#define SIM_RD_SCGC6_FTM2(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM2_MASK) >> SIM_SCGC6_FTM2_SHIFT)
+#define SIM_BRD_SCGC6_FTM2(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM2_SHIFT))
+
+/*! @brief Set the FTM2 field to a new value. */
+#define SIM_WR_SCGC6_FTM2(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM2_MASK, SIM_SCGC6_FTM2(value)))
+#define SIM_BWR_SCGC6_FTM2(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field ADC0[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_ADC0 field. */
+#define SIM_RD_SCGC6_ADC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_ADC0_MASK) >> SIM_SCGC6_ADC0_SHIFT)
+#define SIM_BRD_SCGC6_ADC0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT))
+
+/*! @brief Set the ADC0 field to a new value. */
+#define SIM_WR_SCGC6_ADC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_ADC0_MASK, SIM_SCGC6_ADC0(value)))
+#define SIM_BWR_SCGC6_ADC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RTC[29] (RW)
+ *
+ * This bit controls software access and interrupts to the RTC module.
+ *
+ * Values:
+ * - 0b0 - Access and interrupts disabled
+ * - 0b1 - Access and interrupts enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RTC field. */
+#define SIM_RD_SCGC6_RTC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RTC_MASK) >> SIM_SCGC6_RTC_SHIFT)
+#define SIM_BRD_SCGC6_RTC(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT))
+
+/*! @brief Set the RTC field to a new value. */
+#define SIM_WR_SCGC6_RTC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RTC_MASK, SIM_SCGC6_RTC(value)))
+#define SIM_BWR_SCGC6_RTC(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DAC0[31] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DAC0 field. */
+#define SIM_RD_SCGC6_DAC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DAC0_MASK) >> SIM_SCGC6_DAC0_SHIFT)
+#define SIM_BRD_SCGC6_DAC0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC6_DAC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DAC0_MASK, SIM_SCGC6_DAC0(value)))
+#define SIM_BWR_SCGC6_DAC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC7 - System Clock Gating Control Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
+ *
+ * Reset value: 0x00000006U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC7 register
+ */
+/*@{*/
+#define SIM_RD_SCGC7(base)       (SIM_SCGC7_REG(base))
+#define SIM_WR_SCGC7(base, value) (SIM_SCGC7_REG(base) = (value))
+#define SIM_RMW_SCGC7(base, mask, value) (SIM_WR_SCGC7(base, (SIM_RD_SCGC7(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) |  (value)))
+#define SIM_CLR_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) & ~(value)))
+#define SIM_TOG_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
+ *
+ * This bit controls the clock gate to the FlexBus module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */
+#define SIM_RD_SCGC7_FLEXBUS(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_FLEXBUS_MASK) >> SIM_SCGC7_FLEXBUS_SHIFT)
+#define SIM_BRD_SCGC7_FLEXBUS(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_FLEXBUS_SHIFT))
+
+/*! @brief Set the FLEXBUS field to a new value. */
+#define SIM_WR_SCGC7_FLEXBUS(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_FLEXBUS_MASK, SIM_SCGC7_FLEXBUS(value)))
+#define SIM_BWR_SCGC7_FLEXBUS(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_FLEXBUS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC7, field DMA[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_DMA field. */
+#define SIM_RD_SCGC7_DMA(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_DMA_MASK) >> SIM_SCGC7_DMA_SHIFT)
+#define SIM_BRD_SCGC7_DMA(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define SIM_WR_SCGC7_DMA(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_DMA_MASK, SIM_SCGC7_DMA(value)))
+#define SIM_BWR_SCGC7_DMA(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC7, field MPU[2] (RW)
+ *
+ * This bit controls the clock gate to the MPU module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_MPU field. */
+#define SIM_RD_SCGC7_MPU(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_MPU_MASK) >> SIM_SCGC7_MPU_SHIFT)
+#define SIM_BRD_SCGC7_MPU(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_MPU_SHIFT))
+
+/*! @brief Set the MPU field to a new value. */
+#define SIM_WR_SCGC7_MPU(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_MPU_MASK, SIM_SCGC7_MPU(value)))
+#define SIM_BWR_SCGC7_MPU(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_MPU_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV1 - System Clock Divider Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * When updating CLKDIV1, update all fields using the one write command.
+ * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
+ * write to be ignored. The maximum divide ratio that can be programmed between
+ * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
+ * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
+ * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
+ * mode.
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV1 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV1(base)     (SIM_CLKDIV1_REG(base))
+#define SIM_WR_CLKDIV1(base, value) (SIM_CLKDIV1_REG(base) = (value))
+#define SIM_RMW_CLKDIV1(base, mask, value) (SIM_WR_CLKDIV1(base, (SIM_RD_CLKDIV1(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) |  (value)))
+#define SIM_CLR_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) & ~(value)))
+#define SIM_TOG_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV1 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
+ *
+ * This field sets the divide value for the flash clock from MCGOUTCLK. At the
+ * end of reset, it is loaded with either 0001 or 1111 depending on
+ * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
+ * frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */
+#define SIM_RD_CLKDIV1_OUTDIV4(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV4(base) (SIM_RD_CLKDIV1_OUTDIV4(base))
+
+/*! @brief Set the OUTDIV4 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV4(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV4_MASK, SIM_CLKDIV1_OUTDIV4(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV4(base, value) (SIM_WR_CLKDIV1_OUTDIV4(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
+ *
+ * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
+ * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
+ * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
+ * divide of the system clock frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */
+#define SIM_RD_CLKDIV1_OUTDIV3(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV3(base) (SIM_RD_CLKDIV1_OUTDIV3(base))
+
+/*! @brief Set the OUTDIV3 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV3(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV3_MASK, SIM_CLKDIV1_OUTDIV3(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV3(base, value) (SIM_WR_CLKDIV1_OUTDIV3(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
+ *
+ * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
+ * of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
+ * frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */
+#define SIM_RD_CLKDIV1_OUTDIV2(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV2(base) (SIM_RD_CLKDIV1_OUTDIV2(base))
+
+/*! @brief Set the OUTDIV2 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV2(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV2_MASK, SIM_CLKDIV1_OUTDIV2(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV2(base, value) (SIM_WR_CLKDIV1_OUTDIV2(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
+ *
+ * This field sets the divide value for the core/system clock from MCGOUTCLK. At
+ * the end of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT].
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */
+#define SIM_RD_CLKDIV1_OUTDIV1(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV1(base) (SIM_RD_CLKDIV1_OUTDIV1(base))
+
+/*! @brief Set the OUTDIV1 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV1(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV1_MASK, SIM_CLKDIV1_OUTDIV1(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV1(base, value) (SIM_WR_CLKDIV1_OUTDIV1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV2 - System Clock Divider Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV2 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV2(base)     (SIM_CLKDIV2_REG(base))
+#define SIM_WR_CLKDIV2(base, value) (SIM_CLKDIV2_REG(base) = (value))
+#define SIM_RMW_CLKDIV2(base, mask, value) (SIM_WR_CLKDIV2(base, (SIM_RD_CLKDIV2(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) |  (value)))
+#define SIM_CLR_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) & ~(value)))
+#define SIM_TOG_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV2 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
+ *
+ * This field sets the fraction multiply value for the fractional clock divider
+ * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
+ * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. */
+#define SIM_RD_CLKDIV2_USBFRAC(base) ((SIM_CLKDIV2_REG(base) & SIM_CLKDIV2_USBFRAC_MASK) >> SIM_CLKDIV2_USBFRAC_SHIFT)
+#define SIM_BRD_CLKDIV2_USBFRAC(base) (BITBAND_ACCESS32(&SIM_CLKDIV2_REG(base), SIM_CLKDIV2_USBFRAC_SHIFT))
+
+/*! @brief Set the USBFRAC field to a new value. */
+#define SIM_WR_CLKDIV2_USBFRAC(base, value) (SIM_RMW_CLKDIV2(base, SIM_CLKDIV2_USBFRAC_MASK, SIM_CLKDIV2_USBFRAC(value)))
+#define SIM_BWR_CLKDIV2_USBFRAC(base, value) (BITBAND_ACCESS32(&SIM_CLKDIV2_REG(base), SIM_CLKDIV2_USBFRAC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
+ *
+ * This field sets the divide value for the fractional clock divider when the
+ * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
+ * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV2_USBDIV field. */
+#define SIM_RD_CLKDIV2_USBDIV(base) ((SIM_CLKDIV2_REG(base) & SIM_CLKDIV2_USBDIV_MASK) >> SIM_CLKDIV2_USBDIV_SHIFT)
+#define SIM_BRD_CLKDIV2_USBDIV(base) (SIM_RD_CLKDIV2_USBDIV(base))
+
+/*! @brief Set the USBDIV field to a new value. */
+#define SIM_WR_CLKDIV2_USBDIV(base, value) (SIM_RMW_CLKDIV2(base, SIM_CLKDIV2_USBDIV_MASK, SIM_CLKDIV2_USBDIV(value)))
+#define SIM_BWR_CLKDIV2_USBDIV(base, value) (SIM_WR_CLKDIV2_USBDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG1 - Flash Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG1 - Flash Configuration Register 1 (RW)
+ *
+ * Reset value: 0xFF0F0F00U
+ *
+ * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
+ * user programming in user IFR via the PGMPART flash command. For devices with
+ * program flash only:
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG1 register
+ */
+/*@{*/
+#define SIM_RD_FCFG1(base)       (SIM_FCFG1_REG(base))
+#define SIM_WR_FCFG1(base, value) (SIM_FCFG1_REG(base) = (value))
+#define SIM_RMW_FCFG1(base, mask, value) (SIM_WR_FCFG1(base, (SIM_RD_FCFG1(base) & ~(mask)) | (value)))
+#define SIM_SET_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) |  (value)))
+#define SIM_CLR_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) & ~(value)))
+#define SIM_TOG_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG1 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
+ *
+ * Flash accesses are disabled (and generate a bus error) and the Flash memory
+ * is placed in a low power state. This bit should not be changed during VLP
+ * modes. Relocate the interrupt vectors out of Flash memory before disabling the
+ * Flash.
+ *
+ * Values:
+ * - 0b0 - Flash is enabled
+ * - 0b1 - Flash is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */
+#define SIM_RD_FCFG1_FLASHDIS(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDIS_MASK) >> SIM_FCFG1_FLASHDIS_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDIS(base) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT))
+
+/*! @brief Set the FLASHDIS field to a new value. */
+#define SIM_WR_FCFG1_FLASHDIS(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDIS_MASK, SIM_FCFG1_FLASHDIS(value)))
+#define SIM_BWR_FCFG1_FLASHDIS(base, value) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
+ *
+ * When set, Flash memory is disabled for the duration of Wait mode. An attempt
+ * by the DMA or other bus master to access the Flash when the Flash is disabled
+ * will result in a bus error. This bit should be clear during VLP modes. The
+ * Flash will be automatically enabled again at the end of Wait mode so interrupt
+ * vectors do not need to be relocated out of Flash memory. The wakeup time from
+ * Wait mode is extended when this bit is set.
+ *
+ * Values:
+ * - 0b0 - Flash remains enabled during Wait mode
+ * - 0b1 - Flash is disabled for the duration of Wait mode
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */
+#define SIM_RD_FCFG1_FLASHDOZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDOZE_MASK) >> SIM_FCFG1_FLASHDOZE_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDOZE(base) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT))
+
+/*! @brief Set the FLASHDOZE field to a new value. */
+#define SIM_WR_FCFG1_FLASHDOZE(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDOZE_MASK, SIM_FCFG1_FLASHDOZE(value)))
+#define SIM_BWR_FCFG1_FLASHDOZE(base, value) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
+ *
+ * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
+ * description in FTFE chapter. For devices without FlexNVM: Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_DEPART field. */
+#define SIM_RD_FCFG1_DEPART(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT)
+#define SIM_BRD_FCFG1_DEPART(base) (SIM_RD_FCFG1_DEPART(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
+ *
+ * EEPROM data size .
+ *
+ * Values:
+ * - 0b0000 - 16 KB
+ * - 0b0001 - 8 KB
+ * - 0b0010 - 4 KB
+ * - 0b0011 - 2 KB
+ * - 0b0100 - 1 KB
+ * - 0b0101 - 512 Bytes
+ * - 0b0110 - 256 Bytes
+ * - 0b0111 - 128 Bytes
+ * - 0b1000 - 64 Bytes
+ * - 0b1001 - 32 Bytes
+ * - 0b1111 - 0 Bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_EESIZE field. */
+#define SIM_RD_FCFG1_EESIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_EESIZE_MASK) >> SIM_FCFG1_EESIZE_SHIFT)
+#define SIM_BRD_FCFG1_EESIZE(base) (SIM_RD_FCFG1_EESIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
+ *
+ * This field specifies the amount of program flash memory available on the
+ * device . Undefined values are reserved.
+ *
+ * Values:
+ * - 0b0011 - 32 KB of program flash memory
+ * - 0b0101 - 64 KB of program flash memory
+ * - 0b0111 - 128 KB of program flash memory
+ * - 0b1001 - 256 KB of program flash memory
+ * - 0b1011 - 512 KB of program flash memory
+ * - 0b1101 - 1024 KB of program flash memory
+ * - 0b1111 - 1024 KB of program flash memory
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */
+#define SIM_RD_FCFG1_PFSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT)
+#define SIM_BRD_FCFG1_PFSIZE(base) (SIM_RD_FCFG1_PFSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
+ *
+ * This field specifies the amount of FlexNVM memory available on the device .
+ * Undefined values are reserved.
+ *
+ * Values:
+ * - 0b0000 - 0 KB of FlexNVM
+ * - 0b0011 - 32 KB of FlexNVM
+ * - 0b0101 - 64 KB of FlexNVM
+ * - 0b0111 - 128 KB of FlexNVM
+ * - 0b1001 - 256 KB of FlexNVM
+ * - 0b1011 - 512 KB of FlexNVM
+ * - 0b1111 - 512 KB of FlexNVM
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_NVMSIZE field. */
+#define SIM_RD_FCFG1_NVMSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_NVMSIZE_MASK) >> SIM_FCFG1_NVMSIZE_SHIFT)
+#define SIM_BRD_FCFG1_NVMSIZE(base) (SIM_RD_FCFG1_NVMSIZE(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG2 - Flash Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG2 - Flash Configuration Register 2 (RO)
+ *
+ * Reset value: 0x7F7F0000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG2 register
+ */
+/*@{*/
+#define SIM_RD_FCFG2(base)       (SIM_FCFG2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG2 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
+ *
+ * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
+ * the FlexNVM base address indicates the first invalid address of the FlexNVM
+ * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
+ * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
+ * for a device with 256 KB FlexNVM. For devices with program flash only: This
+ * field equals zero if there is only one program flash block, otherwise it equals
+ * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
+ * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
+ * the MAXADDR1 value for a device with 512 KB program flash memory across two
+ * flash blocks and no FlexNVM.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */
+#define SIM_RD_FCFG2_MAXADDR1(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR1_MASK) >> SIM_FCFG2_MAXADDR1_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR1(base) (SIM_RD_FCFG2_MAXADDR1(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field PFLSH[23] (RO)
+ *
+ * For devices with FlexNVM, this bit is always clear. For devices without
+ * FlexNVM, this bit is always set.
+ *
+ * Values:
+ * - 0b0 - Device supports FlexNVM
+ * - 0b1 - Program Flash only, device does not support FlexNVM
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_PFLSH field. */
+#define SIM_RD_FCFG2_PFLSH(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_PFLSH_MASK) >> SIM_FCFG2_PFLSH_SHIFT)
+#define SIM_BRD_FCFG2_PFLSH(base) (BITBAND_ACCESS32(&SIM_FCFG2_REG(base), SIM_FCFG2_PFLSH_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
+ *
+ * This field concatenated with 13 trailing zeros indicates the first invalid
+ * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
+ * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
+ * value for a device with 256 KB program flash in flash block 0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */
+#define SIM_RD_FCFG2_MAXADDR0(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR0_MASK) >> SIM_FCFG2_MAXADDR0_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR0(base) (SIM_RD_FCFG2_MAXADDR0(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDH - Unique Identification Register High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDH - Unique Identification Register High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDH register
+ */
+/*@{*/
+#define SIM_RD_UIDH(base)        (SIM_UIDH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDMH - Unique Identification Register Mid-High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDMH - Unique Identification Register Mid-High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDMH register
+ */
+/*@{*/
+#define SIM_RD_UIDMH(base)       (SIM_UIDMH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDML - Unique Identification Register Mid Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDML - Unique Identification Register Mid Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDML register
+ */
+/*@{*/
+#define SIM_RD_UIDML(base)       (SIM_UIDML_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDL - Unique Identification Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDL - Unique Identification Register Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDL register
+ */
+/*@{*/
+#define SIM_RD_UIDL(base)        (SIM_UIDL_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 SMC
+ *
+ * System Mode Controller
+ *
+ * Registers defined in this header file:
+ * - SMC_PMPROT - Power Mode Protection register
+ * - SMC_PMCTRL - Power Mode Control register
+ * - SMC_VLLSCTRL - VLLS Control register
+ * - SMC_PMSTAT - Power Mode Status register
+ */
+
+#define SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
+#define SMC_IDX (0U) /*!< Instance number for SMC. */
+
+/*******************************************************************************
+ * SMC_PMPROT - Power Mode Protection register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMPROT - Power Mode Protection register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides protection for entry into any low-power run or stop
+ * mode. The enabling of the low-power run or stop mode occurs by configuring the
+ * Power Mode Control register (PMCTRL). The PMPROT register can be written only
+ * once after any system reset. If the MCU is configured for a disallowed or
+ * reserved power mode, the MCU remains in its current power mode. For example, if the
+ * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
+ * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
+ * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
+ * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
+ * that do not trigger Chip Reset not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMPROT register
+ */
+/*@{*/
+#define SMC_RD_PMPROT(base)      (SMC_PMPROT_REG(base))
+#define SMC_WR_PMPROT(base, value) (SMC_PMPROT_REG(base) = (value))
+#define SMC_RMW_PMPROT(base, mask, value) (SMC_WR_PMPROT(base, (SMC_RD_PMPROT(base) & ~(mask)) | (value)))
+#define SMC_SET_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) |  (value)))
+#define SMC_CLR_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) & ~(value)))
+#define SMC_TOG_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMPROT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMPROT, field AVLLS[1] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write once
+ * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
+ *
+ * Values:
+ * - 0b0 - Any VLLSx mode is not allowed
+ * - 0b1 - Any VLLSx mode is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
+#define SMC_RD_PMPROT_AVLLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLLS_MASK) >> SMC_PMPROT_AVLLS_SHIFT)
+#define SMC_BRD_PMPROT_AVLLS(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT))
+
+/*! @brief Set the AVLLS field to a new value. */
+#define SMC_WR_PMPROT_AVLLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLLS_MASK, SMC_PMPROT_AVLLS(value)))
+#define SMC_BWR_PMPROT_AVLLS(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field ALLS[3] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any low-leakage stop mode (LLS).
+ *
+ * Values:
+ * - 0b0 - LLS is not allowed
+ * - 0b1 - LLS is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_ALLS field. */
+#define SMC_RD_PMPROT_ALLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_ALLS_MASK) >> SMC_PMPROT_ALLS_SHIFT)
+#define SMC_BRD_PMPROT_ALLS(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT))
+
+/*! @brief Set the ALLS field to a new value. */
+#define SMC_WR_PMPROT_ALLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_ALLS_MASK, SMC_PMPROT_ALLS(value)))
+#define SMC_BWR_PMPROT_ALLS(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field AVLP[5] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
+ *
+ * Values:
+ * - 0b0 - VLPR, VLPW, and VLPS are not allowed.
+ * - 0b1 - VLPR, VLPW, and VLPS are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLP field. */
+#define SMC_RD_PMPROT_AVLP(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLP_MASK) >> SMC_PMPROT_AVLP_SHIFT)
+#define SMC_BRD_PMPROT_AVLP(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT))
+
+/*! @brief Set the AVLP field to a new value. */
+#define SMC_WR_PMPROT_AVLP(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLP_MASK, SMC_PMPROT_AVLP(value)))
+#define SMC_BWR_PMPROT_AVLP(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMCTRL - Power Mode Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMCTRL - Power Mode Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The PMCTRL register controls entry into low-power Run and Stop modes,
+ * provided that the selected power mode is allowed via an appropriate setting of the
+ * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
+ * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
+ * that do not trigger Chip POR not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMCTRL register
+ */
+/*@{*/
+#define SMC_RD_PMCTRL(base)      (SMC_PMCTRL_REG(base))
+#define SMC_WR_PMCTRL(base, value) (SMC_PMCTRL_REG(base) = (value))
+#define SMC_RMW_PMCTRL(base, mask, value) (SMC_WR_PMCTRL(base, (SMC_RD_PMCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) |  (value)))
+#define SMC_CLR_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) & ~(value)))
+#define SMC_TOG_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
+ *
+ * When written, controls entry into the selected stop mode when Sleep-Now or
+ * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
+ * blocked if the protection level has not been enabled using the PMPROT register.
+ * After any system reset, this field is cleared by hardware on any successful write
+ * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
+ * register is used to further select the particular VLLS submode which will be
+ * entered.
+ *
+ * Values:
+ * - 0b000 - Normal Stop (STOP)
+ * - 0b001 - Reserved
+ * - 0b010 - Very-Low-Power Stop (VLPS)
+ * - 0b011 - Low-Leakage Stop (LLS)
+ * - 0b100 - Very-Low-Leakage Stop (VLLSx)
+ * - 0b101 - Reserved
+ * - 0b110 - Reseved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
+#define SMC_RD_PMCTRL_STOPM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPM_MASK) >> SMC_PMCTRL_STOPM_SHIFT)
+#define SMC_BRD_PMCTRL_STOPM(base) (SMC_RD_PMCTRL_STOPM(base))
+
+/*! @brief Set the STOPM field to a new value. */
+#define SMC_WR_PMCTRL_STOPM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_STOPM_MASK, SMC_PMCTRL_STOPM(value)))
+#define SMC_BWR_PMCTRL_STOPM(base, value) (SMC_WR_PMCTRL_STOPM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPA[3] (RO)
+ *
+ * When set, this read-only status bit indicates an interrupt or reset occured
+ * during the previous stop mode entry sequence, preventing the system from
+ * entering that mode. This field is cleared by hardware at the beginning of any stop
+ * mode entry sequence and is set if the sequence was aborted.
+ *
+ * Values:
+ * - 0b0 - The previous stop mode entry was successsful.
+ * - 0b1 - The previous stop mode entry was aborted.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
+#define SMC_RD_PMCTRL_STOPA(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPA_MASK) >> SMC_PMCTRL_STOPA_SHIFT)
+#define SMC_BRD_PMCTRL_STOPA(base) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_STOPA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
+ *
+ * When written, causes entry into the selected run mode. Writes to this field
+ * are blocked if the protection level has not been enabled using the PMPROT
+ * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
+ * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
+ *
+ * Values:
+ * - 0b00 - Normal Run mode (RUN)
+ * - 0b01 - Reserved
+ * - 0b10 - Very-Low-Power Run mode (VLPR)
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
+#define SMC_RD_PMCTRL_RUNM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_RUNM_MASK) >> SMC_PMCTRL_RUNM_SHIFT)
+#define SMC_BRD_PMCTRL_RUNM(base) (SMC_RD_PMCTRL_RUNM(base))
+
+/*! @brief Set the RUNM field to a new value. */
+#define SMC_WR_PMCTRL_RUNM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_RUNM_MASK, SMC_PMCTRL_RUNM(value)))
+#define SMC_BWR_PMCTRL_RUNM(base, value) (SMC_WR_PMCTRL_RUNM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
+ *
+ * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
+ * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
+ * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
+ * the LPWUI setting. LPWUI must be modified only while the system is in RUN
+ * mode, that is, when PMSTAT=RUN.
+ *
+ * Values:
+ * - 0b0 - The system remains in a VLP mode on an interrupt
+ * - 0b1 - The system exits to Normal RUN mode on an interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_LPWUI field. */
+#define SMC_RD_PMCTRL_LPWUI(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_LPWUI_MASK) >> SMC_PMCTRL_LPWUI_SHIFT)
+#define SMC_BRD_PMCTRL_LPWUI(base) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_LPWUI_SHIFT))
+
+/*! @brief Set the LPWUI field to a new value. */
+#define SMC_WR_PMCTRL_LPWUI(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_LPWUI_MASK, SMC_PMCTRL_LPWUI(value)))
+#define SMC_BWR_PMCTRL_LPWUI(base, value) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_LPWUI_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_VLLSCTRL - VLLS Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_VLLSCTRL - VLLS Control register (RW)
+ *
+ * Reset value: 0x03U
+ *
+ * The VLLSCTRL register controls features related to VLLS modes. This register
+ * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
+ * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
+ * the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_VLLSCTRL register
+ */
+/*@{*/
+#define SMC_RD_VLLSCTRL(base)    (SMC_VLLSCTRL_REG(base))
+#define SMC_WR_VLLSCTRL(base, value) (SMC_VLLSCTRL_REG(base) = (value))
+#define SMC_RMW_VLLSCTRL(base, mask, value) (SMC_WR_VLLSCTRL(base, (SMC_RD_VLLSCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) |  (value)))
+#define SMC_CLR_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) & ~(value)))
+#define SMC_TOG_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_VLLSCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
+ *
+ * Controls which VLLS sub-mode to enter if STOPM=VLLS.
+ *
+ * Values:
+ * - 0b000 - VLLS0
+ * - 0b001 - VLLS1
+ * - 0b010 - VLLS2
+ * - 0b011 - VLLS3
+ * - 0b100 - Reserved
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_VLLSCTRL_VLLSM field. */
+#define SMC_RD_VLLSCTRL_VLLSM(base) ((SMC_VLLSCTRL_REG(base) & SMC_VLLSCTRL_VLLSM_MASK) >> SMC_VLLSCTRL_VLLSM_SHIFT)
+#define SMC_BRD_VLLSCTRL_VLLSM(base) (SMC_RD_VLLSCTRL_VLLSM(base))
+
+/*! @brief Set the VLLSM field to a new value. */
+#define SMC_WR_VLLSCTRL_VLLSM(base, value) (SMC_RMW_VLLSCTRL(base, SMC_VLLSCTRL_VLLSM_MASK, SMC_VLLSCTRL_VLLSM(value)))
+#define SMC_BWR_VLLSCTRL_VLLSM(base, value) (SMC_WR_VLLSCTRL_VLLSM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
+ *
+ * Controls whether the POR detect circuit (for brown-out detection) is enabled
+ * in VLLS0 mode.
+ *
+ * Values:
+ * - 0b0 - POR detect circuit is enabled in VLLS0.
+ * - 0b1 - POR detect circuit is disabled in VLLS0.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_VLLSCTRL_PORPO field. */
+#define SMC_RD_VLLSCTRL_PORPO(base) ((SMC_VLLSCTRL_REG(base) & SMC_VLLSCTRL_PORPO_MASK) >> SMC_VLLSCTRL_PORPO_SHIFT)
+#define SMC_BRD_VLLSCTRL_PORPO(base) (BITBAND_ACCESS8(&SMC_VLLSCTRL_REG(base), SMC_VLLSCTRL_PORPO_SHIFT))
+
+/*! @brief Set the PORPO field to a new value. */
+#define SMC_WR_VLLSCTRL_PORPO(base, value) (SMC_RMW_VLLSCTRL(base, SMC_VLLSCTRL_PORPO_MASK, SMC_VLLSCTRL_PORPO(value)))
+#define SMC_BWR_VLLSCTRL_PORPO(base, value) (BITBAND_ACCESS8(&SMC_VLLSCTRL_REG(base), SMC_VLLSCTRL_PORPO_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMSTAT - Power Mode Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMSTAT - Power Mode Status register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * PMSTAT is a read-only, one-hot register which indicates the current power
+ * mode of the system. This register is reset on Chip POR not VLLS and by reset
+ * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
+ * trigger Chip POR not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMSTAT register
+ */
+/*@{*/
+#define SMC_RD_PMSTAT(base)      (SMC_PMSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMSTAT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
+ *
+ * When debug is enabled, the PMSTAT will not update to STOP or VLPS
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */
+#define SMC_RD_PMSTAT_PMSTAT(base) ((SMC_PMSTAT_REG(base) & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT)
+#define SMC_BRD_PMSTAT_PMSTAT(base) (SMC_RD_PMSTAT_PMSTAT(base))
+/*@}*/
+
+/*
+ * MK64F12 SPI
+ *
+ * Serial Peripheral Interface
+ *
+ * Registers defined in this header file:
+ * - SPI_MCR - Module Configuration Register
+ * - SPI_TCR - Transfer Count Register
+ * - SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
+ * - SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ * - SPI_SR - Status Register
+ * - SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ * - SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ * - SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ * - SPI_POPR - POP RX FIFO Register
+ * - SPI_TXFR0 - Transmit FIFO Registers
+ * - SPI_TXFR1 - Transmit FIFO Registers
+ * - SPI_TXFR2 - Transmit FIFO Registers
+ * - SPI_TXFR3 - Transmit FIFO Registers
+ * - SPI_RXFR0 - Receive FIFO Registers
+ * - SPI_RXFR1 - Receive FIFO Registers
+ * - SPI_RXFR2 - Receive FIFO Registers
+ * - SPI_RXFR3 - Receive FIFO Registers
+ */
+
+#define SPI_INSTANCE_COUNT (3U) /*!< Number of instances of the SPI module. */
+#define SPI0_IDX (0U) /*!< Instance number for SPI0. */
+#define SPI1_IDX (1U) /*!< Instance number for SPI1. */
+#define SPI2_IDX (2U) /*!< Instance number for SPI2. */
+
+/*******************************************************************************
+ * SPI_MCR - Module Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0x00004001U
+ *
+ * Contains bits to configure various attributes associated with the module
+ * operations. The HALT and MDIS bits can be changed at any time, but the effect
+ * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
+ * MCR can be changed, while the module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_MCR register
+ */
+/*@{*/
+#define SPI_RD_MCR(base)         (SPI_MCR_REG(base))
+#define SPI_WR_MCR(base, value)  (SPI_MCR_REG(base) = (value))
+#define SPI_RMW_MCR(base, mask, value) (SPI_WR_MCR(base, (SPI_RD_MCR(base) & ~(mask)) | (value)))
+#define SPI_SET_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) |  (value)))
+#define SPI_CLR_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) & ~(value)))
+#define SPI_TOG_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_MCR bitfields
+ */
+
+/*!
+ * @name Register SPI_MCR, field HALT[0] (RW)
+ *
+ * The HALT bit starts and stops frame transfers. See Start and Stop of Module
+ * transfers
+ *
+ * Values:
+ * - 0b0 - Start transfers.
+ * - 0b1 - Stop transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_HALT field. */
+#define SPI_RD_MCR_HALT(base) ((SPI_MCR_REG(base) & SPI_MCR_HALT_MASK) >> SPI_MCR_HALT_SHIFT)
+#define SPI_BRD_MCR_HALT(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define SPI_WR_MCR_HALT(base, value) (SPI_RMW_MCR(base, SPI_MCR_HALT_MASK, SPI_MCR_HALT(value)))
+#define SPI_BWR_MCR_HALT(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
+ *
+ * Controls when the module master samples SIN in Modified Transfer Format. This
+ * field is valid only when CPHA bit in CTARn[CPHA] is 0.
+ *
+ * Values:
+ * - 0b00 - 0 protocol clock cycles between SCK edge and SIN sample
+ * - 0b01 - 1 protocol clock cycle between SCK edge and SIN sample
+ * - 0b10 - 2 protocol clock cycles between SCK edge and SIN sample
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_SMPL_PT field. */
+#define SPI_RD_MCR_SMPL_PT(base) ((SPI_MCR_REG(base) & SPI_MCR_SMPL_PT_MASK) >> SPI_MCR_SMPL_PT_SHIFT)
+#define SPI_BRD_MCR_SMPL_PT(base) (SPI_RD_MCR_SMPL_PT(base))
+
+/*! @brief Set the SMPL_PT field to a new value. */
+#define SPI_WR_MCR_SMPL_PT(base, value) (SPI_RMW_MCR(base, SPI_MCR_SMPL_PT_MASK, SPI_MCR_SMPL_PT(value)))
+#define SPI_BWR_MCR_SMPL_PT(base, value) (SPI_WR_MCR_SMPL_PT(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
+ *
+ * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
+ * CLR_RXF bit is always read as zero.
+ *
+ * Values:
+ * - 0b0 - Do not clear the RX FIFO counter.
+ * - 0b1 - Clear the RX FIFO counter.
+ */
+/*@{*/
+/*! @brief Set the CLR_RXF field to a new value. */
+#define SPI_WR_MCR_CLR_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_RXF_MASK, SPI_MCR_CLR_RXF(value)))
+#define SPI_BWR_MCR_CLR_RXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CLR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
+ *
+ * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
+ * CLR_TXF bit is always read as zero.
+ *
+ * Values:
+ * - 0b0 - Do not clear the TX FIFO counter.
+ * - 0b1 - Clear the TX FIFO counter.
+ */
+/*@{*/
+/*! @brief Set the CLR_TXF field to a new value. */
+#define SPI_WR_MCR_CLR_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_TXF_MASK, SPI_MCR_CLR_TXF(value)))
+#define SPI_BWR_MCR_CLR_TXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CLR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DIS_RXF[12] (RW)
+ *
+ * When the RX FIFO is disabled, the receive part of the module operates as a
+ * simplified double-buffered SPI. This bit can only be written when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0b0 - RX FIFO is enabled.
+ * - 0b1 - RX FIFO is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DIS_RXF field. */
+#define SPI_RD_MCR_DIS_RXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_RXF_MASK) >> SPI_MCR_DIS_RXF_SHIFT)
+#define SPI_BRD_MCR_DIS_RXF(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT))
+
+/*! @brief Set the DIS_RXF field to a new value. */
+#define SPI_WR_MCR_DIS_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_RXF_MASK, SPI_MCR_DIS_RXF(value)))
+#define SPI_BWR_MCR_DIS_RXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DIS_TXF[13] (RW)
+ *
+ * When the TX FIFO is disabled, the transmit part of the module operates as a
+ * simplified double-buffered SPI. This bit can be written only when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0b0 - TX FIFO is enabled.
+ * - 0b1 - TX FIFO is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DIS_TXF field. */
+#define SPI_RD_MCR_DIS_TXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_TXF_MASK) >> SPI_MCR_DIS_TXF_SHIFT)
+#define SPI_BRD_MCR_DIS_TXF(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT))
+
+/*! @brief Set the DIS_TXF field to a new value. */
+#define SPI_WR_MCR_DIS_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_TXF_MASK, SPI_MCR_DIS_TXF(value)))
+#define SPI_BWR_MCR_DIS_TXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MDIS[14] (RW)
+ *
+ * Allows the clock to be stopped to the non-memory mapped logic in the module
+ * effectively putting it in a software-controlled power-saving state. The reset
+ * value of the MDIS bit is parameterized, with a default reset value of 0. When
+ * the module is used in Slave Mode, we recommend leaving this bit 0, because a
+ * slave doesn't have control over master transactions.
+ *
+ * Values:
+ * - 0b0 - Enables the module clocks.
+ * - 0b1 - Allows external logic to disable the module clocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MDIS field. */
+#define SPI_RD_MCR_MDIS(base) ((SPI_MCR_REG(base) & SPI_MCR_MDIS_MASK) >> SPI_MCR_MDIS_SHIFT)
+#define SPI_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define SPI_WR_MCR_MDIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_MDIS_MASK, SPI_MCR_MDIS(value)))
+#define SPI_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DOZE[15] (RW)
+ *
+ * Provides support for an externally controlled Doze mode power-saving
+ * mechanism.
+ *
+ * Values:
+ * - 0b0 - Doze mode has no effect on the module.
+ * - 0b1 - Doze mode disables the module.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DOZE field. */
+#define SPI_RD_MCR_DOZE(base) ((SPI_MCR_REG(base) & SPI_MCR_DOZE_MASK) >> SPI_MCR_DOZE_SHIFT)
+#define SPI_BRD_MCR_DOZE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT))
+
+/*! @brief Set the DOZE field to a new value. */
+#define SPI_WR_MCR_DOZE(base, value) (SPI_RMW_MCR(base, SPI_MCR_DOZE_MASK, SPI_MCR_DOZE(value)))
+#define SPI_BWR_MCR_DOZE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field PCSIS[21:16] (RW)
+ *
+ * Determines the inactive state of PCSx.
+ *
+ * Values:
+ * - 0b000000 - The inactive state of PCSx is low.
+ * - 0b000001 - The inactive state of PCSx is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_PCSIS field. */
+#define SPI_RD_MCR_PCSIS(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSIS_MASK) >> SPI_MCR_PCSIS_SHIFT)
+#define SPI_BRD_MCR_PCSIS(base) (SPI_RD_MCR_PCSIS(base))
+
+/*! @brief Set the PCSIS field to a new value. */
+#define SPI_WR_MCR_PCSIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSIS_MASK, SPI_MCR_PCSIS(value)))
+#define SPI_BWR_MCR_PCSIS(base, value) (SPI_WR_MCR_PCSIS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field ROOE[24] (RW)
+ *
+ * In the RX FIFO overflow condition, configures the module to ignore the
+ * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
+ * is received, the data from the transfer, generating the overflow, is ignored
+ * or shifted into the shift register.
+ *
+ * Values:
+ * - 0b0 - Incoming data is ignored.
+ * - 0b1 - Incoming data is shifted into the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_ROOE field. */
+#define SPI_RD_MCR_ROOE(base) ((SPI_MCR_REG(base) & SPI_MCR_ROOE_MASK) >> SPI_MCR_ROOE_SHIFT)
+#define SPI_BRD_MCR_ROOE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT))
+
+/*! @brief Set the ROOE field to a new value. */
+#define SPI_WR_MCR_ROOE(base, value) (SPI_RMW_MCR(base, SPI_MCR_ROOE_MASK, SPI_MCR_ROOE(value)))
+#define SPI_BWR_MCR_ROOE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field PCSSE[25] (RW)
+ *
+ * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
+ *
+ * Values:
+ * - 0b0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
+ * - 0b1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_PCSSE field. */
+#define SPI_RD_MCR_PCSSE(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSSE_MASK) >> SPI_MCR_PCSSE_SHIFT)
+#define SPI_BRD_MCR_PCSSE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_PCSSE_SHIFT))
+
+/*! @brief Set the PCSSE field to a new value. */
+#define SPI_WR_MCR_PCSSE(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSSE_MASK, SPI_MCR_PCSSE(value)))
+#define SPI_BWR_MCR_PCSSE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_PCSSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MTFE[26] (RW)
+ *
+ * Enables a modified transfer format to be used.
+ *
+ * Values:
+ * - 0b0 - Modified SPI transfer format disabled.
+ * - 0b1 - Modified SPI transfer format enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MTFE field. */
+#define SPI_RD_MCR_MTFE(base) ((SPI_MCR_REG(base) & SPI_MCR_MTFE_MASK) >> SPI_MCR_MTFE_SHIFT)
+#define SPI_BRD_MCR_MTFE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT))
+
+/*! @brief Set the MTFE field to a new value. */
+#define SPI_WR_MCR_MTFE(base, value) (SPI_RMW_MCR(base, SPI_MCR_MTFE_MASK, SPI_MCR_MTFE(value)))
+#define SPI_BWR_MCR_MTFE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field FRZ[27] (RW)
+ *
+ * Enables transfers to be stopped on the next frame boundary when the device
+ * enters Debug mode.
+ *
+ * Values:
+ * - 0b0 - Do not halt serial transfers in Debug mode.
+ * - 0b1 - Halt serial transfers in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_FRZ field. */
+#define SPI_RD_MCR_FRZ(base) ((SPI_MCR_REG(base) & SPI_MCR_FRZ_MASK) >> SPI_MCR_FRZ_SHIFT)
+#define SPI_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define SPI_WR_MCR_FRZ(base, value) (SPI_RMW_MCR(base, SPI_MCR_FRZ_MASK, SPI_MCR_FRZ(value)))
+#define SPI_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DCONF[29:28] (RO)
+ *
+ * Selects among the different configurations of the module.
+ *
+ * Values:
+ * - 0b00 - SPI
+ * - 0b01 - Reserved
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DCONF field. */
+#define SPI_RD_MCR_DCONF(base) ((SPI_MCR_REG(base) & SPI_MCR_DCONF_MASK) >> SPI_MCR_DCONF_SHIFT)
+#define SPI_BRD_MCR_DCONF(base) (SPI_RD_MCR_DCONF(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
+ *
+ * Enables the Serial Communication Clock (SCK) to run continuously.
+ *
+ * Values:
+ * - 0b0 - Continuous SCK disabled.
+ * - 0b1 - Continuous SCK enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */
+#define SPI_RD_MCR_CONT_SCKE(base) ((SPI_MCR_REG(base) & SPI_MCR_CONT_SCKE_MASK) >> SPI_MCR_CONT_SCKE_SHIFT)
+#define SPI_BRD_MCR_CONT_SCKE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT))
+
+/*! @brief Set the CONT_SCKE field to a new value. */
+#define SPI_WR_MCR_CONT_SCKE(base, value) (SPI_RMW_MCR(base, SPI_MCR_CONT_SCKE_MASK, SPI_MCR_CONT_SCKE(value)))
+#define SPI_BWR_MCR_CONT_SCKE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MSTR[31] (RW)
+ *
+ * Enables either Master mode (if supported) or Slave mode (if supported)
+ * operation.
+ *
+ * Values:
+ * - 0b0 - Enables Slave mode
+ * - 0b1 - Enables Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MSTR field. */
+#define SPI_RD_MCR_MSTR(base) ((SPI_MCR_REG(base) & SPI_MCR_MSTR_MASK) >> SPI_MCR_MSTR_SHIFT)
+#define SPI_BRD_MCR_MSTR(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT))
+
+/*! @brief Set the MSTR field to a new value. */
+#define SPI_WR_MCR_MSTR(base, value) (SPI_RMW_MCR(base, SPI_MCR_MSTR_MASK, SPI_MCR_MSTR(value)))
+#define SPI_BWR_MCR_MSTR(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TCR - Transfer Count Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TCR - Transfer Count Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR contains a counter that indicates the number of SPI transfers made. The
+ * transfer counter is intended to assist in queue management. Do not write the
+ * TCR when the module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TCR register
+ */
+/*@{*/
+#define SPI_RD_TCR(base)         (SPI_TCR_REG(base))
+#define SPI_WR_TCR(base, value)  (SPI_TCR_REG(base) = (value))
+#define SPI_RMW_TCR(base, mask, value) (SPI_WR_TCR(base, (SPI_RD_TCR(base) & ~(mask)) | (value)))
+#define SPI_SET_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) |  (value)))
+#define SPI_CLR_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) & ~(value)))
+#define SPI_TOG_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TCR bitfields
+ */
+
+/*!
+ * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
+ *
+ * Counts the number of SPI transfers the module makes. The SPI_TCNT field
+ * increments every time the last bit of an SPI frame is transmitted. A value written
+ * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
+ * the beginning of the frame when the CTCNT field is set in the executing SPI
+ * command. The Transfer Counter wraps around; incrementing the counter past 65535
+ * resets the counter to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */
+#define SPI_RD_TCR_SPI_TCNT(base) ((SPI_TCR_REG(base) & SPI_TCR_SPI_TCNT_MASK) >> SPI_TCR_SPI_TCNT_SHIFT)
+#define SPI_BRD_TCR_SPI_TCNT(base) (SPI_RD_TCR_SPI_TCNT(base))
+
+/*! @brief Set the SPI_TCNT field to a new value. */
+#define SPI_WR_TCR_SPI_TCNT(base, value) (SPI_RMW_TCR(base, SPI_TCR_SPI_TCNT_MASK, SPI_TCR_SPI_TCNT(value)))
+#define SPI_BWR_TCR_SPI_TCNT(base, value) (SPI_WR_TCR_SPI_TCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * When the module is configured as an SPI bus slave, the CTAR0 register is used.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CTAR_SLAVE register
+ */
+/*@{*/
+#define SPI_RD_CTAR_SLAVE(base, index) (SPI_CTAR_SLAVE_REG(base, index))
+#define SPI_WR_CTAR_SLAVE(base, index, value) (SPI_CTAR_SLAVE_REG(base, index) = (value))
+#define SPI_RMW_CTAR_SLAVE(base, index, mask, value) (SPI_WR_CTAR_SLAVE(base, index, (SPI_RD_CTAR_SLAVE(base, index) & ~(mask)) | (value)))
+#define SPI_SET_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) |  (value)))
+#define SPI_CLR_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) & ~(value)))
+#define SPI_TOG_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CTAR_SLAVE bitfields
+ */
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0b0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 0b1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_CPHA field. */
+#define SPI_RD_CTAR_SLAVE_CPHA(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPHA_MASK) >> SPI_CTAR_SLAVE_CPHA_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_CPHA(base, index) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_CTAR_SLAVE_CPHA(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPHA_MASK, SPI_CTAR_SLAVE_CPHA(value)))
+#define SPI_BWR_CTAR_SLAVE_CPHA(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0b0 - The inactive state value of SCK is low.
+ * - 0b1 - The inactive state value of SCK is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_CPOL field. */
+#define SPI_RD_CTAR_SLAVE_CPOL(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPOL_MASK) >> SPI_CTAR_SLAVE_CPOL_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_CPOL(base, index) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_CTAR_SLAVE_CPOL(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPOL_MASK, SPI_CTAR_SLAVE_CPOL(value)))
+#define SPI_BWR_CTAR_SLAVE_CPOL(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field FMSZ[31:27] (RW)
+ *
+ * The number of bits transfered per frame is equal to the FMSZ field value plus
+ * 1. Note that the minimum valid value of frame size is 4.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_FMSZ field. */
+#define SPI_RD_CTAR_SLAVE_FMSZ(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_FMSZ(base, index) (SPI_RD_CTAR_SLAVE_FMSZ(base, index))
+
+/*! @brief Set the FMSZ field to a new value. */
+#define SPI_WR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_FMSZ_MASK, SPI_CTAR_SLAVE_FMSZ(value)))
+#define SPI_BWR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_WR_CTAR_SLAVE_FMSZ(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * CTAR registers are used to define different transfer attributes. Do not write
+ * to the CTAR registers while the module is in the Running state. In Master
+ * mode, the CTAR registers define combinations of transfer attributes such as frame
+ * size, clock phase and polarity, data bit ordering, baud rate, and various
+ * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
+ * slave transfer attributes. When the module is configured as an SPI master, the
+ * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
+ * registers is used. When the module is configured as an SPI bus slave, it uses
+ * the CTAR0 register.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CTAR register
+ */
+/*@{*/
+#define SPI_RD_CTAR(base, index) (SPI_CTAR_REG(base, index))
+#define SPI_WR_CTAR(base, index, value) (SPI_CTAR_REG(base, index) = (value))
+#define SPI_RMW_CTAR(base, index, mask, value) (SPI_WR_CTAR(base, index, (SPI_RD_CTAR(base, index) & ~(mask)) | (value)))
+#define SPI_SET_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) |  (value)))
+#define SPI_CLR_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) & ~(value)))
+#define SPI_TOG_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CTAR bitfields
+ */
+
+/*!
+ * @name Register SPI_CTAR, field BR[3:0] (RW)
+ *
+ * Selects the scaler value for the baud rate. This field is used only in master
+ * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
+ * generate the frequency of the SCK. The baud rate is computed according to the
+ * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
+ * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
+ * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
+ * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_BR field. */
+#define SPI_RD_CTAR_BR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_BR_MASK) >> SPI_CTAR_BR_SHIFT)
+#define SPI_BRD_CTAR_BR(base, index) (SPI_RD_CTAR_BR(base, index))
+
+/*! @brief Set the BR field to a new value. */
+#define SPI_WR_CTAR_BR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_BR_MASK, SPI_CTAR_BR(value)))
+#define SPI_BWR_CTAR_BR(base, index, value) (SPI_WR_CTAR_BR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field DT[7:4] (RW)
+ *
+ * Selects the Delay after Transfer Scaler. This field is used only in master
+ * mode. The Delay after Transfer is the time between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the next
+ * frame. In the Continuous Serial Communications Clock operation, the DT value
+ * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
+ * protocol clock period, and it is computed according to the following
+ * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
+ * field description for scaler values.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_DT field. */
+#define SPI_RD_CTAR_DT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DT_MASK) >> SPI_CTAR_DT_SHIFT)
+#define SPI_BRD_CTAR_DT(base, index) (SPI_RD_CTAR_DT(base, index))
+
+/*! @brief Set the DT field to a new value. */
+#define SPI_WR_CTAR_DT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DT_MASK, SPI_CTAR_DT(value)))
+#define SPI_BWR_CTAR_DT(base, index, value) (SPI_WR_CTAR_DT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field ASC[11:8] (RW)
+ *
+ * Selects the scaler value for the After SCK Delay. This field is used only in
+ * master mode. The After SCK Delay is the delay between the last edge of SCK and
+ * the negation of PCS. The delay is a multiple of the protocol clock period,
+ * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
+ * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
+ * scaler values. Refer After SCK Delay (tASC ) for more details.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_ASC field. */
+#define SPI_RD_CTAR_ASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_ASC_MASK) >> SPI_CTAR_ASC_SHIFT)
+#define SPI_BRD_CTAR_ASC(base, index) (SPI_RD_CTAR_ASC(base, index))
+
+/*! @brief Set the ASC field to a new value. */
+#define SPI_WR_CTAR_ASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_ASC_MASK, SPI_CTAR_ASC(value)))
+#define SPI_BWR_CTAR_ASC(base, index, value) (SPI_WR_CTAR_ASC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CSSCK[15:12] (RW)
+ *
+ * Selects the scaler value for the PCS to SCK delay. This field is used only in
+ * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
+ * and the first edge of the SCK. The delay is a multiple of the protocol clock
+ * period, and it is computed according to the following equation: t CSC = (1/fP )
+ * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
+ * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
+ * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
+ * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
+ * details.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CSSCK field. */
+#define SPI_RD_CTAR_CSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CSSCK_MASK) >> SPI_CTAR_CSSCK_SHIFT)
+#define SPI_BRD_CTAR_CSSCK(base, index) (SPI_RD_CTAR_CSSCK(base, index))
+
+/*! @brief Set the CSSCK field to a new value. */
+#define SPI_WR_CTAR_CSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CSSCK_MASK, SPI_CTAR_CSSCK(value)))
+#define SPI_BWR_CTAR_CSSCK(base, index, value) (SPI_WR_CTAR_CSSCK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PBR[17:16] (RW)
+ *
+ * Selects the prescaler value for the baud rate. This field is used only in
+ * master mode. The baud rate is the frequency of the SCK. The protocol clock is
+ * divided by the prescaler value before the baud rate selection takes place. See
+ * the BR field description for details on how to compute the baud rate.
+ *
+ * Values:
+ * - 0b00 - Baud Rate Prescaler value is 2.
+ * - 0b01 - Baud Rate Prescaler value is 3.
+ * - 0b10 - Baud Rate Prescaler value is 5.
+ * - 0b11 - Baud Rate Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PBR field. */
+#define SPI_RD_CTAR_PBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PBR_MASK) >> SPI_CTAR_PBR_SHIFT)
+#define SPI_BRD_CTAR_PBR(base, index) (SPI_RD_CTAR_PBR(base, index))
+
+/*! @brief Set the PBR field to a new value. */
+#define SPI_WR_CTAR_PBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PBR_MASK, SPI_CTAR_PBR(value)))
+#define SPI_BWR_CTAR_PBR(base, index, value) (SPI_WR_CTAR_PBR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PDT[19:18] (RW)
+ *
+ * Selects the prescaler value for the delay between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the
+ * next frame. The PDT field is only used in master mode. See the DT field
+ * description for details on how to compute the Delay after Transfer. Refer Delay after
+ * Transfer (tDT ) for more details.
+ *
+ * Values:
+ * - 0b00 - Delay after Transfer Prescaler value is 1.
+ * - 0b01 - Delay after Transfer Prescaler value is 3.
+ * - 0b10 - Delay after Transfer Prescaler value is 5.
+ * - 0b11 - Delay after Transfer Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PDT field. */
+#define SPI_RD_CTAR_PDT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PDT_MASK) >> SPI_CTAR_PDT_SHIFT)
+#define SPI_BRD_CTAR_PDT(base, index) (SPI_RD_CTAR_PDT(base, index))
+
+/*! @brief Set the PDT field to a new value. */
+#define SPI_WR_CTAR_PDT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PDT_MASK, SPI_CTAR_PDT(value)))
+#define SPI_BWR_CTAR_PDT(base, index, value) (SPI_WR_CTAR_PDT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PASC[21:20] (RW)
+ *
+ * Selects the prescaler value for the delay between the last edge of SCK and
+ * the negation of PCS. See the ASC field description for information on how to
+ * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
+ *
+ * Values:
+ * - 0b00 - Delay after Transfer Prescaler value is 1.
+ * - 0b01 - Delay after Transfer Prescaler value is 3.
+ * - 0b10 - Delay after Transfer Prescaler value is 5.
+ * - 0b11 - Delay after Transfer Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PASC field. */
+#define SPI_RD_CTAR_PASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PASC_MASK) >> SPI_CTAR_PASC_SHIFT)
+#define SPI_BRD_CTAR_PASC(base, index) (SPI_RD_CTAR_PASC(base, index))
+
+/*! @brief Set the PASC field to a new value. */
+#define SPI_WR_CTAR_PASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PASC_MASK, SPI_CTAR_PASC(value)))
+#define SPI_BWR_CTAR_PASC(base, index, value) (SPI_WR_CTAR_PASC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PCSSCK[23:22] (RW)
+ *
+ * Selects the prescaler value for the delay between assertion of PCS and the
+ * first edge of the SCK. See the CSSCK field description for information on how to
+ * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
+ *
+ * Values:
+ * - 0b00 - PCS to SCK Prescaler value is 1.
+ * - 0b01 - PCS to SCK Prescaler value is 3.
+ * - 0b10 - PCS to SCK Prescaler value is 5.
+ * - 0b11 - PCS to SCK Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PCSSCK field. */
+#define SPI_RD_CTAR_PCSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PCSSCK_MASK) >> SPI_CTAR_PCSSCK_SHIFT)
+#define SPI_BRD_CTAR_PCSSCK(base, index) (SPI_RD_CTAR_PCSSCK(base, index))
+
+/*! @brief Set the PCSSCK field to a new value. */
+#define SPI_WR_CTAR_PCSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PCSSCK_MASK, SPI_CTAR_PCSSCK(value)))
+#define SPI_BWR_CTAR_PCSSCK(base, index, value) (SPI_WR_CTAR_PCSSCK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field LSBFE[24] (RW)
+ *
+ * Specifies whether the LSB or MSB of the frame is transferred first.
+ *
+ * Values:
+ * - 0b0 - Data is transferred MSB first.
+ * - 0b1 - Data is transferred LSB first.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_LSBFE field. */
+#define SPI_RD_CTAR_LSBFE(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_LSBFE_MASK) >> SPI_CTAR_LSBFE_SHIFT)
+#define SPI_BRD_CTAR_LSBFE(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT))
+
+/*! @brief Set the LSBFE field to a new value. */
+#define SPI_WR_CTAR_LSBFE(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_LSBFE_MASK, SPI_CTAR_LSBFE(value)))
+#define SPI_BWR_CTAR_LSBFE(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0b0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 0b1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CPHA field. */
+#define SPI_RD_CTAR_CPHA(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPHA_MASK) >> SPI_CTAR_CPHA_SHIFT)
+#define SPI_BRD_CTAR_CPHA(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_CTAR_CPHA(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPHA_MASK, SPI_CTAR_CPHA(value)))
+#define SPI_BWR_CTAR_CPHA(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). This bit
+ * is used in both master and slave mode. For successful communication between
+ * serial devices, the devices must have identical clock polarities. When the
+ * Continuous Selection Format is selected, switching between clock polarities
+ * without stopping the module can cause errors in the transfer due to the peripheral
+ * device interpreting the switch of clock polarity as a valid clock edge. In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0b0 - The inactive state value of SCK is low.
+ * - 0b1 - The inactive state value of SCK is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CPOL field. */
+#define SPI_RD_CTAR_CPOL(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPOL_MASK) >> SPI_CTAR_CPOL_SHIFT)
+#define SPI_BRD_CTAR_CPOL(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_CTAR_CPOL(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPOL_MASK, SPI_CTAR_CPOL(value)))
+#define SPI_BWR_CTAR_CPOL(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field FMSZ[30:27] (RW)
+ *
+ * The number of bits transferred per frame is equal to the FMSZ value plus 1.
+ * Regardless of the transmission mode, the minimum valid frame size value is 4.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_FMSZ field. */
+#define SPI_RD_CTAR_FMSZ(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT)
+#define SPI_BRD_CTAR_FMSZ(base, index) (SPI_RD_CTAR_FMSZ(base, index))
+
+/*! @brief Set the FMSZ field to a new value. */
+#define SPI_WR_CTAR_FMSZ(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_FMSZ_MASK, SPI_CTAR_FMSZ(value)))
+#define SPI_BWR_CTAR_FMSZ(base, index, value) (SPI_WR_CTAR_FMSZ(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field DBR[31] (RW)
+ *
+ * Doubles the effective baud rate of the Serial Communications Clock (SCK).
+ * This field is used only in master mode. It effectively halves the Baud Rate
+ * division ratio, supporting faster frequencies, and odd division ratios for the
+ * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
+ * Serial Communications Clock (SCK) depends on the value in the Baud Rate
+ * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
+ * description for details on how to compute the baud rate. SPI SCK Duty Cycle
+ * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
+ * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
+ *
+ * Values:
+ * - 0b0 - The baud rate is computed normally with a 50/50 duty cycle.
+ * - 0b1 - The baud rate is doubled with the duty cycle depending on the Baud
+ *     Rate Prescaler.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_DBR field. */
+#define SPI_RD_CTAR_DBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DBR_MASK) >> SPI_CTAR_DBR_SHIFT)
+#define SPI_BRD_CTAR_DBR(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT))
+
+/*! @brief Set the DBR field to a new value. */
+#define SPI_WR_CTAR_DBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DBR_MASK, SPI_CTAR_DBR(value)))
+#define SPI_BWR_CTAR_DBR(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_SR - Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_SR - Status Register (RW)
+ *
+ * Reset value: 0x02000000U
+ *
+ * SR contains status and flag bits. The bits reflect the status of the module
+ * and indicate the occurrence of events that can generate interrupt or DMA
+ * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
+ * to a flag bit has no effect. This register may not be writable in Module
+ * Disable mode due to the use of power saving mechanisms.
+ */
+/*!
+ * @name Constants and macros for entire SPI_SR register
+ */
+/*@{*/
+#define SPI_RD_SR(base)          (SPI_SR_REG(base))
+#define SPI_WR_SR(base, value)   (SPI_SR_REG(base) = (value))
+#define SPI_RMW_SR(base, mask, value) (SPI_WR_SR(base, (SPI_RD_SR(base) & ~(mask)) | (value)))
+#define SPI_SET_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) |  (value)))
+#define SPI_CLR_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) & ~(value)))
+#define SPI_TOG_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_SR bitfields
+ */
+
+/*!
+ * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
+ *
+ * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
+ * The POPNXTPTR is updated when the POPR is read.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_POPNXTPTR field. */
+#define SPI_RD_SR_POPNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_POPNXTPTR_MASK) >> SPI_SR_POPNXTPTR_SHIFT)
+#define SPI_BRD_SR_POPNXTPTR(base) (SPI_RD_SR_POPNXTPTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RXCTR[7:4] (RO)
+ *
+ * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
+ * every time the POPR is read. The RXCTR is incremented every time data is
+ * transferred from the shift register to the RX FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RXCTR field. */
+#define SPI_RD_SR_RXCTR(base) ((SPI_SR_REG(base) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT)
+#define SPI_BRD_SR_RXCTR(base) (SPI_RD_SR_RXCTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
+ *
+ * Indicates which TX FIFO entry is transmitted during the next transfer. The
+ * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
+ * the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXNXTPTR field. */
+#define SPI_RD_SR_TXNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_TXNXTPTR_MASK) >> SPI_SR_TXNXTPTR_SHIFT)
+#define SPI_BRD_SR_TXNXTPTR(base) (SPI_RD_SR_TXNXTPTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXCTR[15:12] (RO)
+ *
+ * Indicates the number of valid entries in the TX FIFO. The TXCTR is
+ * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
+ * command is executed and the SPI data is transferred to the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXCTR field. */
+#define SPI_RD_SR_TXCTR(base) ((SPI_SR_REG(base) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT)
+#define SPI_BRD_SR_TXCTR(base) (SPI_RD_SR_TXCTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RFDF[17] (W1C)
+ *
+ * Provides a method for the module to request that entries be removed from the
+ * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller when
+ * the RX FIFO is empty.
+ *
+ * Values:
+ * - 0b0 - RX FIFO is empty.
+ * - 0b1 - RX FIFO is not empty.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RFDF field. */
+#define SPI_RD_SR_RFDF(base) ((SPI_SR_REG(base) & SPI_SR_RFDF_MASK) >> SPI_SR_RFDF_SHIFT)
+#define SPI_BRD_SR_RFDF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT))
+
+/*! @brief Set the RFDF field to a new value. */
+#define SPI_WR_SR_RFDF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFDF(value)))
+#define SPI_BWR_SR_RFDF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RFOF[19] (W1C)
+ *
+ * Indicates an overflow condition in the RX FIFO. The field is set when the RX
+ * FIFO and shift register are full and a transfer is initiated. The bit remains
+ * set until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - No Rx FIFO overflow.
+ * - 0b1 - Rx FIFO overflow has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RFOF field. */
+#define SPI_RD_SR_RFOF(base) ((SPI_SR_REG(base) & SPI_SR_RFOF_MASK) >> SPI_SR_RFOF_SHIFT)
+#define SPI_BRD_SR_RFOF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT))
+
+/*! @brief Set the RFOF field to a new value. */
+#define SPI_WR_SR_RFOF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFOF(value)))
+#define SPI_BWR_SR_RFOF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TFFF[25] (W1C)
+ *
+ * Provides a method for the module to request more entries to be added to the
+ * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller to
+ * the TX FIFO full request.
+ *
+ * Values:
+ * - 0b0 - TX FIFO is full.
+ * - 0b1 - TX FIFO is not full.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TFFF field. */
+#define SPI_RD_SR_TFFF(base) ((SPI_SR_REG(base) & SPI_SR_TFFF_MASK) >> SPI_SR_TFFF_SHIFT)
+#define SPI_BRD_SR_TFFF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT))
+
+/*! @brief Set the TFFF field to a new value. */
+#define SPI_WR_SR_TFFF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFFF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFFF(value)))
+#define SPI_BWR_SR_TFFF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TFUF[27] (W1C)
+ *
+ * Indicates an underflow condition in the TX FIFO. The transmit underflow
+ * condition is detected only for SPI blocks operating in Slave mode and SPI
+ * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
+ * is empty and an external SPI master initiates a transfer. The TFUF bit remains
+ * set until cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No TX FIFO underflow.
+ * - 0b1 - TX FIFO underflow has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TFUF field. */
+#define SPI_RD_SR_TFUF(base) ((SPI_SR_REG(base) & SPI_SR_TFUF_MASK) >> SPI_SR_TFUF_SHIFT)
+#define SPI_BRD_SR_TFUF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT))
+
+/*! @brief Set the TFUF field to a new value. */
+#define SPI_WR_SR_TFUF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFUF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFUF(value)))
+#define SPI_BWR_SR_TFUF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field EOQF[28] (W1C)
+ *
+ * Indicates that the last entry in a queue has been transmitted when the module
+ * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
+ * set in the command halfword and the end of the transfer is reached. The EOQF
+ * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
+ * the TXRXS bit is automatically cleared.
+ *
+ * Values:
+ * - 0b0 - EOQ is not set in the executing command.
+ * - 0b1 - EOQ is set in the executing SPI command.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_EOQF field. */
+#define SPI_RD_SR_EOQF(base) ((SPI_SR_REG(base) & SPI_SR_EOQF_MASK) >> SPI_SR_EOQF_SHIFT)
+#define SPI_BRD_SR_EOQF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT))
+
+/*! @brief Set the EOQF field to a new value. */
+#define SPI_WR_SR_EOQF(base, value) (SPI_RMW_SR(base, (SPI_SR_EOQF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_EOQF(value)))
+#define SPI_BWR_SR_EOQF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXRXS[30] (W1C)
+ *
+ * Reflects the run status of the module.
+ *
+ * Values:
+ * - 0b0 - Transmit and receive operations are disabled (The module is in
+ *     Stopped state).
+ * - 0b1 - Transmit and receive operations are enabled (The module is in Running
+ *     state).
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXRXS field. */
+#define SPI_RD_SR_TXRXS(base) ((SPI_SR_REG(base) & SPI_SR_TXRXS_MASK) >> SPI_SR_TXRXS_SHIFT)
+#define SPI_BRD_SR_TXRXS(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT))
+
+/*! @brief Set the TXRXS field to a new value. */
+#define SPI_WR_SR_TXRXS(base, value) (SPI_RMW_SR(base, (SPI_SR_TXRXS_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TCF_MASK), SPI_SR_TXRXS(value)))
+#define SPI_BWR_SR_TXRXS(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TCF[31] (W1C)
+ *
+ * Indicates that all bits in a frame have been shifted out. TCF remains set
+ * until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - Transfer not complete.
+ * - 0b1 - Transfer complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TCF field. */
+#define SPI_RD_SR_TCF(base)  ((SPI_SR_REG(base) & SPI_SR_TCF_MASK) >> SPI_SR_TCF_SHIFT)
+#define SPI_BRD_SR_TCF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT))
+
+/*! @brief Set the TCF field to a new value. */
+#define SPI_WR_SR_TCF(base, value) (SPI_RMW_SR(base, (SPI_SR_TCF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK), SPI_SR_TCF(value)))
+#define SPI_BWR_SR_TCF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RSER controls DMA and interrupt requests. Do not write to the RSER while the
+ * module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RSER register
+ */
+/*@{*/
+#define SPI_RD_RSER(base)        (SPI_RSER_REG(base))
+#define SPI_WR_RSER(base, value) (SPI_RSER_REG(base) = (value))
+#define SPI_RMW_RSER(base, mask, value) (SPI_WR_RSER(base, (SPI_RD_RSER(base) & ~(mask)) | (value)))
+#define SPI_SET_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) |  (value)))
+#define SPI_CLR_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) & ~(value)))
+#define SPI_TOG_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_RSER bitfields
+ */
+
+/*!
+ * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When the
+ * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
+ * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - Interrupt request.
+ * - 0b1 - DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */
+#define SPI_RD_RSER_RFDF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_DIRS_MASK) >> SPI_RSER_RFDF_DIRS_SHIFT)
+#define SPI_BRD_RSER_RFDF_DIRS(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT))
+
+/*! @brief Set the RFDF_DIRS field to a new value. */
+#define SPI_WR_RSER_RFDF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_DIRS_MASK, SPI_RSER_RFDF_DIRS(value)))
+#define SPI_BWR_RSER_RFDF_DIRS(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field RFDF_RE[17] (RW)
+ *
+ * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - RFDF interrupt or DMA requests are disabled.
+ * - 0b1 - RFDF interrupt or DMA requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFDF_RE field. */
+#define SPI_RD_RSER_RFDF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_RE_MASK) >> SPI_RSER_RFDF_RE_SHIFT)
+#define SPI_BRD_RSER_RFDF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT))
+
+/*! @brief Set the RFDF_RE field to a new value. */
+#define SPI_WR_RSER_RFDF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_RE_MASK, SPI_RSER_RFDF_RE(value)))
+#define SPI_BWR_RSER_RFDF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field RFOF_RE[19] (RW)
+ *
+ * Enables the RFOF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - RFOF interrupt requests are disabled.
+ * - 0b1 - RFOF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFOF_RE field. */
+#define SPI_RD_RSER_RFOF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFOF_RE_MASK) >> SPI_RSER_RFOF_RE_SHIFT)
+#define SPI_BRD_RSER_RFOF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT))
+
+/*! @brief Set the RFOF_RE field to a new value. */
+#define SPI_WR_RSER_RFOF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFOF_RE_MASK, SPI_RSER_RFOF_RE(value)))
+#define SPI_BWR_RSER_RFOF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When
+ * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
+ * interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - TFFF flag generates interrupt requests.
+ * - 0b1 - TFFF flag generates DMA requests.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */
+#define SPI_RD_RSER_TFFF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_DIRS_MASK) >> SPI_RSER_TFFF_DIRS_SHIFT)
+#define SPI_BRD_RSER_TFFF_DIRS(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT))
+
+/*! @brief Set the TFFF_DIRS field to a new value. */
+#define SPI_WR_RSER_TFFF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_DIRS_MASK, SPI_RSER_TFFF_DIRS(value)))
+#define SPI_BWR_RSER_TFFF_DIRS(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFFF_RE[25] (RW)
+ *
+ * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - TFFF interrupts or DMA requests are disabled.
+ * - 0b1 - TFFF interrupts or DMA requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFFF_RE field. */
+#define SPI_RD_RSER_TFFF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_RE_MASK) >> SPI_RSER_TFFF_RE_SHIFT)
+#define SPI_BRD_RSER_TFFF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT))
+
+/*! @brief Set the TFFF_RE field to a new value. */
+#define SPI_WR_RSER_TFFF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_RE_MASK, SPI_RSER_TFFF_RE(value)))
+#define SPI_BWR_RSER_TFFF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFUF_RE[27] (RW)
+ *
+ * Enables the TFUF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - TFUF interrupt requests are disabled.
+ * - 0b1 - TFUF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFUF_RE field. */
+#define SPI_RD_RSER_TFUF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFUF_RE_MASK) >> SPI_RSER_TFUF_RE_SHIFT)
+#define SPI_BRD_RSER_TFUF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT))
+
+/*! @brief Set the TFUF_RE field to a new value. */
+#define SPI_WR_RSER_TFUF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFUF_RE_MASK, SPI_RSER_TFUF_RE(value)))
+#define SPI_BWR_RSER_TFUF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field EOQF_RE[28] (RW)
+ *
+ * Enables the EOQF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - EOQF interrupt requests are disabled.
+ * - 0b1 - EOQF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_EOQF_RE field. */
+#define SPI_RD_RSER_EOQF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_EOQF_RE_MASK) >> SPI_RSER_EOQF_RE_SHIFT)
+#define SPI_BRD_RSER_EOQF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT))
+
+/*! @brief Set the EOQF_RE field to a new value. */
+#define SPI_WR_RSER_EOQF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_EOQF_RE_MASK, SPI_RSER_EOQF_RE(value)))
+#define SPI_BWR_RSER_EOQF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TCF_RE[31] (RW)
+ *
+ * Enables TCF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - TCF interrupt requests are disabled.
+ * - 0b1 - TCF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TCF_RE field. */
+#define SPI_RD_RSER_TCF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TCF_RE_MASK) >> SPI_RSER_TCF_RE_SHIFT)
+#define SPI_BRD_RSER_TCF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT))
+
+/*! @brief Set the TCF_RE field to a new value. */
+#define SPI_WR_RSER_TCF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TCF_RE_MASK, SPI_RSER_TCF_RE(value)))
+#define SPI_BWR_RSER_TCF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
+ * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
+ * can be used as data, supporting up to 32-bit frame operation. A read access
+ * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
+ * writing to this register does not update the FIFO. Therefore, any reads performed
+ * while the module is disabled return the last PUSHR write performed while the
+ * module was still enabled.
+ */
+/*!
+ * @name Constants and macros for entire SPI_PUSHR register
+ */
+/*@{*/
+#define SPI_RD_PUSHR(base)       (SPI_PUSHR_REG(base))
+#define SPI_WR_PUSHR(base, value) (SPI_PUSHR_REG(base) = (value))
+#define SPI_RMW_PUSHR(base, mask, value) (SPI_WR_PUSHR(base, (SPI_RD_PUSHR(base) & ~(mask)) | (value)))
+#define SPI_SET_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) |  (value)))
+#define SPI_CLR_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) & ~(value)))
+#define SPI_TOG_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_PUSHR bitfields
+ */
+
+/*!
+ * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
+ *
+ * Holds SPI data to be transferred according to the associated SPI command.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_TXDATA field. */
+#define SPI_RD_PUSHR_TXDATA(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_TXDATA_MASK) >> SPI_PUSHR_TXDATA_SHIFT)
+#define SPI_BRD_PUSHR_TXDATA(base) (SPI_RD_PUSHR_TXDATA(base))
+
+/*! @brief Set the TXDATA field to a new value. */
+#define SPI_WR_PUSHR_TXDATA(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_TXDATA_MASK, SPI_PUSHR_TXDATA(value)))
+#define SPI_BWR_PUSHR_TXDATA(base, value) (SPI_WR_PUSHR_TXDATA(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field PCS[21:16] (RW)
+ *
+ * Select which PCS signals are to be asserted for the transfer. Refer to the
+ * chip configuration details for the number of PCS signals used in this MCU.
+ *
+ * Values:
+ * - 0b000000 - Negate the PCS[x] signal.
+ * - 0b000001 - Assert the PCS[x] signal.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_PCS field. */
+#define SPI_RD_PUSHR_PCS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_PCS_MASK) >> SPI_PUSHR_PCS_SHIFT)
+#define SPI_BRD_PUSHR_PCS(base) (SPI_RD_PUSHR_PCS(base))
+
+/*! @brief Set the PCS field to a new value. */
+#define SPI_WR_PUSHR_PCS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_PCS_MASK, SPI_PUSHR_PCS(value)))
+#define SPI_BWR_PUSHR_PCS(base, value) (SPI_WR_PUSHR_PCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CTCNT[26] (RW)
+ *
+ * Clears the TCNT field in the TCR register. The TCNT field is cleared before
+ * the module starts transmitting the current SPI frame.
+ *
+ * Values:
+ * - 0b0 - Do not clear the TCR[TCNT] field.
+ * - 0b1 - Clear the TCR[TCNT] field.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CTCNT field. */
+#define SPI_RD_PUSHR_CTCNT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTCNT_MASK) >> SPI_PUSHR_CTCNT_SHIFT)
+#define SPI_BRD_PUSHR_CTCNT(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT))
+
+/*! @brief Set the CTCNT field to a new value. */
+#define SPI_WR_PUSHR_CTCNT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTCNT_MASK, SPI_PUSHR_CTCNT(value)))
+#define SPI_BWR_PUSHR_CTCNT(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field EOQ[27] (RW)
+ *
+ * Host software uses this bit to signal to the module that the current SPI
+ * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
+ * SR is set.
+ *
+ * Values:
+ * - 0b0 - The SPI data is not the last data to transfer.
+ * - 0b1 - The SPI data is the last data to transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_EOQ field. */
+#define SPI_RD_PUSHR_EOQ(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_EOQ_MASK) >> SPI_PUSHR_EOQ_SHIFT)
+#define SPI_BRD_PUSHR_EOQ(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT))
+
+/*! @brief Set the EOQ field to a new value. */
+#define SPI_WR_PUSHR_EOQ(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_EOQ_MASK, SPI_PUSHR_EOQ(value)))
+#define SPI_BWR_PUSHR_EOQ(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
+ *
+ * Selects which CTAR to use in master mode to specify the transfer attributes
+ * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
+ * configuration details to determine how many CTARs this device has. You should
+ * not program a value in this field for a register that is not present.
+ *
+ * Values:
+ * - 0b000 - CTAR0
+ * - 0b001 - CTAR1
+ * - 0b010 - Reserved
+ * - 0b011 - Reserved
+ * - 0b100 - Reserved
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CTAS field. */
+#define SPI_RD_PUSHR_CTAS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTAS_MASK) >> SPI_PUSHR_CTAS_SHIFT)
+#define SPI_BRD_PUSHR_CTAS(base) (SPI_RD_PUSHR_CTAS(base))
+
+/*! @brief Set the CTAS field to a new value. */
+#define SPI_WR_PUSHR_CTAS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTAS_MASK, SPI_PUSHR_CTAS(value)))
+#define SPI_BWR_PUSHR_CTAS(base, value) (SPI_WR_PUSHR_CTAS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CONT[31] (RW)
+ *
+ * Selects a continuous selection format. The bit is used in SPI Master mode.
+ * The bit enables the selected PCS signals to remain asserted between transfers.
+ *
+ * Values:
+ * - 0b0 - Return PCSn signals to their inactive state between transfers.
+ * - 0b1 - Keep PCSn signals asserted between transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CONT field. */
+#define SPI_RD_PUSHR_CONT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CONT_MASK) >> SPI_PUSHR_CONT_SHIFT)
+#define SPI_BRD_PUSHR_CONT(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT))
+
+/*! @brief Set the CONT field to a new value. */
+#define SPI_WR_PUSHR_CONT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CONT_MASK, SPI_PUSHR_CONT(value)))
+#define SPI_BWR_PUSHR_CONT(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
+ * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
+ * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
+ * SPI Frame operation.
+ */
+/*!
+ * @name Constants and macros for entire SPI_PUSHR_SLAVE register
+ */
+/*@{*/
+#define SPI_RD_PUSHR_SLAVE(base) (SPI_PUSHR_SLAVE_REG(base))
+#define SPI_WR_PUSHR_SLAVE(base, value) (SPI_PUSHR_SLAVE_REG(base) = (value))
+#define SPI_RMW_PUSHR_SLAVE(base, mask, value) (SPI_WR_PUSHR_SLAVE(base, (SPI_RD_PUSHR_SLAVE(base) & ~(mask)) | (value)))
+#define SPI_SET_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) |  (value)))
+#define SPI_CLR_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) & ~(value)))
+#define SPI_TOG_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_POPR - POP RX FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_POPR - POP RX FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
+ * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
+ * this register will generate a Transfer Error.
+ */
+/*!
+ * @name Constants and macros for entire SPI_POPR register
+ */
+/*@{*/
+#define SPI_RD_POPR(base)        (SPI_POPR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR0 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR0 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR0 register
+ */
+/*@{*/
+#define SPI_RD_TXFR0(base)       (SPI_TXFR0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR0 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR0, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR0_TXDATA field. */
+#define SPI_RD_TXFR0_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXDATA_MASK) >> SPI_TXFR0_TXDATA_SHIFT)
+#define SPI_BRD_TXFR0_TXDATA(base) (SPI_RD_TXFR0_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR0, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR0_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR0_TXCMD_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXCMD_TXDATA_MASK) >> SPI_TXFR0_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR0_TXCMD_TXDATA(base) (SPI_RD_TXFR0_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR1 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR1 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR1 register
+ */
+/*@{*/
+#define SPI_RD_TXFR1(base)       (SPI_TXFR1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR1 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR1, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR1_TXDATA field. */
+#define SPI_RD_TXFR1_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXDATA_MASK) >> SPI_TXFR1_TXDATA_SHIFT)
+#define SPI_BRD_TXFR1_TXDATA(base) (SPI_RD_TXFR1_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR1, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR1_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR1_TXCMD_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXCMD_TXDATA_MASK) >> SPI_TXFR1_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR1_TXCMD_TXDATA(base) (SPI_RD_TXFR1_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR2 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR2 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR2 register
+ */
+/*@{*/
+#define SPI_RD_TXFR2(base)       (SPI_TXFR2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR2 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR2, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR2_TXDATA field. */
+#define SPI_RD_TXFR2_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXDATA_MASK) >> SPI_TXFR2_TXDATA_SHIFT)
+#define SPI_BRD_TXFR2_TXDATA(base) (SPI_RD_TXFR2_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR2, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR2_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR2_TXCMD_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXCMD_TXDATA_MASK) >> SPI_TXFR2_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR2_TXCMD_TXDATA(base) (SPI_RD_TXFR2_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR3 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR3 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR3 register
+ */
+/*@{*/
+#define SPI_RD_TXFR3(base)       (SPI_TXFR3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR3 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR3, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR3_TXDATA field. */
+#define SPI_RD_TXFR3_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXDATA_MASK) >> SPI_TXFR3_TXDATA_SHIFT)
+#define SPI_BRD_TXFR3_TXDATA(base) (SPI_RD_TXFR3_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR3, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR3_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR3_TXCMD_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXCMD_TXDATA_MASK) >> SPI_TXFR3_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR3_TXCMD_TXDATA(base) (SPI_RD_TXFR3_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR0 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR0 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR0 register
+ */
+/*@{*/
+#define SPI_RD_RXFR0(base)       (SPI_RXFR0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR1 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR1 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR1 register
+ */
+/*@{*/
+#define SPI_RD_RXFR1(base)       (SPI_RXFR1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR2 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR2 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR2 register
+ */
+/*@{*/
+#define SPI_RD_RXFR2(base)       (SPI_RXFR2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR3 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR3 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR3 register
+ */
+/*@{*/
+#define SPI_RD_RXFR3(base)       (SPI_RXFR3_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 UART
+ *
+ * Serial Communication Interface
+ *
+ * Registers defined in this header file:
+ * - UART_BDH - UART Baud Rate Registers: High
+ * - UART_BDL - UART Baud Rate Registers: Low
+ * - UART_C1 - UART Control Register 1
+ * - UART_C2 - UART Control Register 2
+ * - UART_S1 - UART Status Register 1
+ * - UART_S2 - UART Status Register 2
+ * - UART_C3 - UART Control Register 3
+ * - UART_D - UART Data Register
+ * - UART_MA1 - UART Match Address Registers 1
+ * - UART_MA2 - UART Match Address Registers 2
+ * - UART_C4 - UART Control Register 4
+ * - UART_C5 - UART Control Register 5
+ * - UART_ED - UART Extended Data Register
+ * - UART_MODEM - UART Modem Register
+ * - UART_IR - UART Infrared Register
+ * - UART_PFIFO - UART FIFO Parameters
+ * - UART_CFIFO - UART FIFO Control Register
+ * - UART_SFIFO - UART FIFO Status Register
+ * - UART_TWFIFO - UART FIFO Transmit Watermark
+ * - UART_TCFIFO - UART FIFO Transmit Count
+ * - UART_RWFIFO - UART FIFO Receive Watermark
+ * - UART_RCFIFO - UART FIFO Receive Count
+ * - UART_C7816 - UART 7816 Control Register
+ * - UART_IE7816 - UART 7816 Interrupt Enable Register
+ * - UART_IS7816 - UART 7816 Interrupt Status Register
+ * - UART_WP7816T0 - UART 7816 Wait Parameter Register
+ * - UART_WP7816T1 - UART 7816 Wait Parameter Register
+ * - UART_WN7816 - UART 7816 Wait N Register
+ * - UART_WF7816 - UART 7816 Wait FD Register
+ * - UART_ET7816 - UART 7816 Error Threshold Register
+ * - UART_TL7816 - UART 7816 Transmit Length Register
+ */
+
+#define UART_INSTANCE_COUNT (6U) /*!< Number of instances of the UART module. */
+#define UART0_IDX (0U) /*!< Instance number for UART0. */
+#define UART1_IDX (1U) /*!< Instance number for UART1. */
+#define UART2_IDX (2U) /*!< Instance number for UART2. */
+#define UART3_IDX (3U) /*!< Instance number for UART3. */
+#define UART4_IDX (4U) /*!< Instance number for UART4. */
+#define UART5_IDX (5U) /*!< Instance number for UART5. */
+
+/*******************************************************************************
+ * UART_BDH - UART Baud Rate Registers: High
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDH - UART Baud Rate Registers: High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register, along with the BDL register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting
+ * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
+ * to BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is,
+ * when C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDH register
+ */
+/*@{*/
+#define UART_RD_BDH(base)        (UART_BDH_REG(base))
+#define UART_WR_BDH(base, value) (UART_BDH_REG(base) = (value))
+#define UART_RMW_BDH(base, mask, value) (UART_WR_BDH(base, (UART_RD_BDH(base) & ~(mask)) | (value)))
+#define UART_SET_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) |  (value)))
+#define UART_CLR_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) & ~(value)))
+#define UART_TOG_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_BDH bitfields
+ */
+
+/*!
+ * @name Register UART_BDH, field SBR[4:0] (RW)
+ *
+ * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
+ * generation for details. The baud rate generator is disabled until C2[TE] or
+ * C2[RE] is set for the first time after reset.The baud rate generator is disabled
+ * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
+ * writing to BDH puts the data in a temporary location until BDL is written.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBR field. */
+#define UART_RD_BDH_SBR(base) ((UART_BDH_REG(base) & UART_BDH_SBR_MASK) >> UART_BDH_SBR_SHIFT)
+#define UART_BRD_BDH_SBR(base) (UART_RD_BDH_SBR(base))
+
+/*! @brief Set the SBR field to a new value. */
+#define UART_WR_BDH_SBR(base, value) (UART_RMW_BDH(base, UART_BDH_SBR_MASK, UART_BDH_SBR(value)))
+#define UART_BWR_BDH_SBR(base, value) (UART_WR_BDH_SBR(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field SBNS[5] (RW)
+ *
+ * SBNS selects the number of stop bits present in a data frame. This field
+ * valid for all 8, 9 and 10 bit data formats available. This field is not valid when
+ * C7816[ISO7816E] is enabled.
+ *
+ * Values:
+ * - 0b0 - Data frame consists of a single stop bit.
+ * - 0b1 - Data frame consists of two stop bits.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBNS field. */
+#define UART_RD_BDH_SBNS(base) ((UART_BDH_REG(base) & UART_BDH_SBNS_MASK) >> UART_BDH_SBNS_SHIFT)
+#define UART_BRD_BDH_SBNS(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_SBNS_SHIFT))
+
+/*! @brief Set the SBNS field to a new value. */
+#define UART_WR_BDH_SBNS(base, value) (UART_RMW_BDH(base, UART_BDH_SBNS_MASK, UART_BDH_SBNS(value)))
+#define UART_BWR_BDH_SBNS(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_SBNS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field RXEDGIE[6] (RW)
+ *
+ * Enables the receive input active edge, RXEDGIF, to generate interrupt
+ * requests.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupts from RXEDGIF disabled using polling.
+ * - 0b1 - RXEDGIF interrupt request enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_RXEDGIE field. */
+#define UART_RD_BDH_RXEDGIE(base) ((UART_BDH_REG(base) & UART_BDH_RXEDGIE_MASK) >> UART_BDH_RXEDGIE_SHIFT)
+#define UART_BRD_BDH_RXEDGIE(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT))
+
+/*! @brief Set the RXEDGIE field to a new value. */
+#define UART_WR_BDH_RXEDGIE(base, value) (UART_RMW_BDH(base, UART_BDH_RXEDGIE_MASK, UART_BDH_RXEDGIE(value)))
+#define UART_BWR_BDH_RXEDGIE(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field LBKDIE[7] (RW)
+ *
+ * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
+ * based on the state of LBKDDMAS. or DMA transfer requests,
+ *
+ * Values:
+ * - 0b0 - LBKDIF interrupt and DMA transfer requests disabled.
+ * - 0b1 - LBKDIF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_LBKDIE field. */
+#define UART_RD_BDH_LBKDIE(base) ((UART_BDH_REG(base) & UART_BDH_LBKDIE_MASK) >> UART_BDH_LBKDIE_SHIFT)
+#define UART_BRD_BDH_LBKDIE(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_LBKDIE_SHIFT))
+
+/*! @brief Set the LBKDIE field to a new value. */
+#define UART_WR_BDH_LBKDIE(base, value) (UART_RMW_BDH(base, UART_BDH_LBKDIE_MASK, UART_BDH_LBKDIE(value)))
+#define UART_BWR_BDH_LBKDIE(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_LBKDIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_BDL - UART Baud Rate Registers: Low
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDL - UART Baud Rate Registers: Low (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * This register, along with the BDH register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
+ * first write to BDH to buffer the high half of the new value and then write to
+ * BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is, when
+ * C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDL register
+ */
+/*@{*/
+#define UART_RD_BDL(base)        (UART_BDL_REG(base))
+#define UART_WR_BDL(base, value) (UART_BDL_REG(base) = (value))
+#define UART_RMW_BDL(base, mask, value) (UART_WR_BDL(base, (UART_RD_BDL(base) & ~(mask)) | (value)))
+#define UART_SET_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) |  (value)))
+#define UART_CLR_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) & ~(value)))
+#define UART_TOG_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C1 - UART Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C1 - UART Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This read/write register controls various optional features of the UART
+ * system.
+ */
+/*!
+ * @name Constants and macros for entire UART_C1 register
+ */
+/*@{*/
+#define UART_RD_C1(base)         (UART_C1_REG(base))
+#define UART_WR_C1(base, value)  (UART_C1_REG(base) = (value))
+#define UART_RMW_C1(base, mask, value) (UART_WR_C1(base, (UART_RD_C1(base) & ~(mask)) | (value)))
+#define UART_SET_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) |  (value)))
+#define UART_CLR_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) & ~(value)))
+#define UART_TOG_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C1 bitfields
+ */
+
+/*!
+ * @name Register UART_C1, field PT[0] (RW)
+ *
+ * Determines whether the UART generates and checks for even parity or odd
+ * parity. With even parity, an even number of 1s clears the parity bit and an odd
+ * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
+ * parity bit and an even number of 1s sets the parity bit. This field must be
+ * cleared when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Even parity.
+ * - 0b1 - Odd parity.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PT field. */
+#define UART_RD_C1_PT(base)  ((UART_C1_REG(base) & UART_C1_PT_MASK) >> UART_C1_PT_SHIFT)
+#define UART_BRD_C1_PT(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PT_SHIFT))
+
+/*! @brief Set the PT field to a new value. */
+#define UART_WR_C1_PT(base, value) (UART_RMW_C1(base, UART_C1_PT_MASK, UART_C1_PT(value)))
+#define UART_BWR_C1_PT(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field PE[1] (RW)
+ *
+ * Enables the parity function. When parity is enabled, parity function inserts
+ * a parity bit in the bit position immediately preceding the stop bit. This
+ * field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Parity function disabled.
+ * - 0b1 - Parity function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PE field. */
+#define UART_RD_C1_PE(base)  ((UART_C1_REG(base) & UART_C1_PE_MASK) >> UART_C1_PE_SHIFT)
+#define UART_BRD_C1_PE(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PE_SHIFT))
+
+/*! @brief Set the PE field to a new value. */
+#define UART_WR_C1_PE(base, value) (UART_RMW_C1(base, UART_C1_PE_MASK, UART_C1_PE(value)))
+#define UART_BWR_C1_PE(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field ILT[2] (RW)
+ *
+ * Determines when the receiver starts counting logic 1s as idle character bits.
+ * The count begins either after a valid start bit or after the stop bit. If the
+ * count begins after the start bit, then a string of logic 1s preceding the
+ * stop bit can cause false recognition of an idle character. Beginning the count
+ * after the stop bit avoids false idle character recognition, but requires
+ * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
+ * logic of 1'b0 is automatically shifted after a received stop bit, therefore
+ * resetting the idle count. In case the UART is programmed for IDLE line wakeup
+ * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
+ * logic 1s as idle character bits. In idle line wakeup, an idle character is
+ * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
+ * and C4[M10] fields.
+ *
+ * Values:
+ * - 0b0 - Idle character bit count starts after start bit.
+ * - 0b1 - Idle character bit count starts after stop bit.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_ILT field. */
+#define UART_RD_C1_ILT(base) ((UART_C1_REG(base) & UART_C1_ILT_MASK) >> UART_C1_ILT_SHIFT)
+#define UART_BRD_C1_ILT(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_ILT_SHIFT))
+
+/*! @brief Set the ILT field to a new value. */
+#define UART_WR_C1_ILT(base, value) (UART_RMW_C1(base, UART_C1_ILT_MASK, UART_C1_ILT(value)))
+#define UART_BWR_C1_ILT(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_ILT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field WAKE[3] (RW)
+ *
+ * Determines which condition wakes the UART: Address mark in the most
+ * significant bit position of a received data character, or An idle condition on the
+ * receive pin input signal.
+ *
+ * Values:
+ * - 0b0 - Idle line wakeup.
+ * - 0b1 - Address mark wakeup.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_WAKE field. */
+#define UART_RD_C1_WAKE(base) ((UART_C1_REG(base) & UART_C1_WAKE_MASK) >> UART_C1_WAKE_SHIFT)
+#define UART_BRD_C1_WAKE(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT))
+
+/*! @brief Set the WAKE field to a new value. */
+#define UART_WR_C1_WAKE(base, value) (UART_RMW_C1(base, UART_C1_WAKE_MASK, UART_C1_WAKE(value)))
+#define UART_BWR_C1_WAKE(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field M[4] (RW)
+ *
+ * This field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) +
+ *     stop.
+ * - 0b1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_M field. */
+#define UART_RD_C1_M(base)   ((UART_C1_REG(base) & UART_C1_M_MASK) >> UART_C1_M_SHIFT)
+#define UART_BRD_C1_M(base)  (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_M_SHIFT))
+
+/*! @brief Set the M field to a new value. */
+#define UART_WR_C1_M(base, value) (UART_RMW_C1(base, UART_C1_M_MASK, UART_C1_M(value)))
+#define UART_BWR_C1_M(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_M_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field RSRC[5] (RW)
+ *
+ * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
+ * is set, the RSRC field determines the source for the receiver shift register
+ * input.
+ *
+ * Values:
+ * - 0b0 - Selects internal loop back mode. The receiver input is internally
+ *     connected to transmitter output.
+ * - 0b1 - Single wire UART mode where the receiver input is connected to the
+ *     transmit pin input signal.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_RSRC field. */
+#define UART_RD_C1_RSRC(base) ((UART_C1_REG(base) & UART_C1_RSRC_MASK) >> UART_C1_RSRC_SHIFT)
+#define UART_BRD_C1_RSRC(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT))
+
+/*! @brief Set the RSRC field to a new value. */
+#define UART_WR_C1_RSRC(base, value) (UART_RMW_C1(base, UART_C1_RSRC_MASK, UART_C1_RSRC(value)))
+#define UART_BWR_C1_RSRC(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field UARTSWAI[6] (RW)
+ *
+ * Values:
+ * - 0b0 - UART clock continues to run in Wait mode.
+ * - 0b1 - UART clock freezes while CPU is in Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_UARTSWAI field. */
+#define UART_RD_C1_UARTSWAI(base) ((UART_C1_REG(base) & UART_C1_UARTSWAI_MASK) >> UART_C1_UARTSWAI_SHIFT)
+#define UART_BRD_C1_UARTSWAI(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_UARTSWAI_SHIFT))
+
+/*! @brief Set the UARTSWAI field to a new value. */
+#define UART_WR_C1_UARTSWAI(base, value) (UART_RMW_C1(base, UART_C1_UARTSWAI_MASK, UART_C1_UARTSWAI(value)))
+#define UART_BWR_C1_UARTSWAI(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_UARTSWAI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field LOOPS[7] (RW)
+ *
+ * When LOOPS is set, the RxD pin is disconnected from the UART and the
+ * transmitter output is internally connected to the receiver input. The transmitter and
+ * the receiver must be enabled to use the loop function.
+ *
+ * Values:
+ * - 0b0 - Normal operation.
+ * - 0b1 - Loop mode where transmitter output is internally connected to
+ *     receiver input. The receiver input is determined by RSRC.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_LOOPS field. */
+#define UART_RD_C1_LOOPS(base) ((UART_C1_REG(base) & UART_C1_LOOPS_MASK) >> UART_C1_LOOPS_SHIFT)
+#define UART_BRD_C1_LOOPS(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT))
+
+/*! @brief Set the LOOPS field to a new value. */
+#define UART_WR_C1_LOOPS(base, value) (UART_RMW_C1(base, UART_C1_LOOPS_MASK, UART_C1_LOOPS(value)))
+#define UART_BWR_C1_LOOPS(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C2 - UART Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C2 - UART Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register can be read or written at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_C2 register
+ */
+/*@{*/
+#define UART_RD_C2(base)         (UART_C2_REG(base))
+#define UART_WR_C2(base, value)  (UART_C2_REG(base) = (value))
+#define UART_RMW_C2(base, mask, value) (UART_WR_C2(base, (UART_RD_C2(base) & ~(mask)) | (value)))
+#define UART_SET_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) |  (value)))
+#define UART_CLR_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) & ~(value)))
+#define UART_TOG_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C2 bitfields
+ */
+
+/*!
+ * @name Register UART_C2, field SBK[0] (RW)
+ *
+ * Toggling SBK sends one break character from the following: See Transmitting
+ * break characters for the number of logic 0s for the different configurations.
+ * Toggling implies clearing the SBK field before the break character has finished
+ * transmitting. As long as SBK is set, the transmitter continues to send
+ * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
+ * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
+ * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
+ * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
+ * C7816[ISO_7816E] is set.
+ *
+ * Values:
+ * - 0b0 - Normal transmitter operation.
+ * - 0b1 - Queue break characters to be sent.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_SBK field. */
+#define UART_RD_C2_SBK(base) ((UART_C2_REG(base) & UART_C2_SBK_MASK) >> UART_C2_SBK_SHIFT)
+#define UART_BRD_C2_SBK(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_SBK_SHIFT))
+
+/*! @brief Set the SBK field to a new value. */
+#define UART_WR_C2_SBK(base, value) (UART_RMW_C2(base, UART_C2_SBK_MASK, UART_C2_SBK(value)))
+#define UART_BWR_C2_SBK(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_SBK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RWU[1] (RW)
+ *
+ * This field can be set to place the UART receiver in a standby state. RWU
+ * automatically clears when an RWU event occurs, that is, an IDLE event when
+ * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
+ * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
+ * on idle) if the channel is currently not idle. This can be determined by
+ * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
+ * idle, it is possible that the UART will discard data. This is because the data
+ * must be received or a LIN break detected after an IDLE is detected before IDLE
+ * is allowed to reasserted.
+ *
+ * Values:
+ * - 0b0 - Normal operation.
+ * - 0b1 - RWU enables the wakeup function and inhibits further receiver
+ *     interrupt requests. Normally, hardware wakes the receiver by automatically
+ *     clearing RWU.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RWU field. */
+#define UART_RD_C2_RWU(base) ((UART_C2_REG(base) & UART_C2_RWU_MASK) >> UART_C2_RWU_SHIFT)
+#define UART_BRD_C2_RWU(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RWU_SHIFT))
+
+/*! @brief Set the RWU field to a new value. */
+#define UART_WR_C2_RWU(base, value) (UART_RMW_C2(base, UART_C2_RWU_MASK, UART_C2_RWU(value)))
+#define UART_BWR_C2_RWU(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RWU_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RE[2] (RW)
+ *
+ * Enables the UART receiver.
+ *
+ * Values:
+ * - 0b0 - Receiver off.
+ * - 0b1 - Receiver on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RE field. */
+#define UART_RD_C2_RE(base)  ((UART_C2_REG(base) & UART_C2_RE_MASK) >> UART_C2_RE_SHIFT)
+#define UART_BRD_C2_RE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RE_SHIFT))
+
+/*! @brief Set the RE field to a new value. */
+#define UART_WR_C2_RE(base, value) (UART_RMW_C2(base, UART_C2_RE_MASK, UART_C2_RE(value)))
+#define UART_BWR_C2_RE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TE[3] (RW)
+ *
+ * Enables the UART transmitter. TE can be used to queue an idle preamble by
+ * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
+ * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
+ * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
+ * additional characters are transmitted.
+ *
+ * Values:
+ * - 0b0 - Transmitter off.
+ * - 0b1 - Transmitter on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TE field. */
+#define UART_RD_C2_TE(base)  ((UART_C2_REG(base) & UART_C2_TE_MASK) >> UART_C2_TE_SHIFT)
+#define UART_BRD_C2_TE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TE_SHIFT))
+
+/*! @brief Set the TE field to a new value. */
+#define UART_WR_C2_TE(base, value) (UART_RMW_C2(base, UART_C2_TE_MASK, UART_C2_TE(value)))
+#define UART_BWR_C2_TE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field ILIE[4] (RW)
+ *
+ * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
+ * transfer requests based on the state of C5[ILDMAS].
+ *
+ * Values:
+ * - 0b0 - IDLE interrupt requests disabled. and DMA transfer
+ * - 0b1 - IDLE interrupt requests enabled. or DMA transfer
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_ILIE field. */
+#define UART_RD_C2_ILIE(base) ((UART_C2_REG(base) & UART_C2_ILIE_MASK) >> UART_C2_ILIE_SHIFT)
+#define UART_BRD_C2_ILIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT))
+
+/*! @brief Set the ILIE field to a new value. */
+#define UART_WR_C2_ILIE(base, value) (UART_RMW_C2(base, UART_C2_ILIE_MASK, UART_C2_ILIE(value)))
+#define UART_BWR_C2_ILIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RIE[5] (RW)
+ *
+ * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[RDMAS].
+ *
+ * Values:
+ * - 0b0 - RDRF interrupt and DMA transfer requests disabled.
+ * - 0b1 - RDRF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RIE field. */
+#define UART_RD_C2_RIE(base) ((UART_C2_REG(base) & UART_C2_RIE_MASK) >> UART_C2_RIE_SHIFT)
+#define UART_BRD_C2_RIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RIE_SHIFT))
+
+/*! @brief Set the RIE field to a new value. */
+#define UART_WR_C2_RIE(base, value) (UART_RMW_C2(base, UART_C2_RIE_MASK, UART_C2_RIE(value)))
+#define UART_BWR_C2_RIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TCIE[6] (RW)
+ *
+ * Enables the transmission complete flag, S1[TC], to generate interrupt
+ * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
+ * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
+ * written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0b0 - TC interrupt and DMA transfer requests disabled.
+ * - 0b1 - TC interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TCIE field. */
+#define UART_RD_C2_TCIE(base) ((UART_C2_REG(base) & UART_C2_TCIE_MASK) >> UART_C2_TCIE_SHIFT)
+#define UART_BRD_C2_TCIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT))
+
+/*! @brief Set the TCIE field to a new value. */
+#define UART_WR_C2_TCIE(base, value) (UART_RMW_C2(base, UART_C2_TCIE_MASK, UART_C2_TCIE(value)))
+#define UART_BWR_C2_TCIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TIE[7] (RW)
+ *
+ * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
+ * must be cleared, and D[D] must not be written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0b0 - TDRE interrupt and DMA transfer requests disabled.
+ * - 0b1 - TDRE interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TIE field. */
+#define UART_RD_C2_TIE(base) ((UART_C2_REG(base) & UART_C2_TIE_MASK) >> UART_C2_TIE_SHIFT)
+#define UART_BRD_C2_TIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define UART_WR_C2_TIE(base, value) (UART_RMW_C2(base, UART_C2_TIE_MASK, UART_C2_TIE(value)))
+#define UART_BWR_C2_TIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S1 - UART Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S1 - UART Status Register 1 (RO)
+ *
+ * Reset value: 0xC0U
+ *
+ * The S1 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. This register can also be polled by the MCU to check the
+ * status of its fields. To clear a flag, the status register should be read followed
+ * by a read or write to D register, depending on the interrupt flag type. Other
+ * instructions can be executed between the two steps as long the handling of
+ * I/O is not compromised, but the order of operations is important for flag
+ * clearing. When a flag is configured to trigger a DMA request, assertion of the
+ * associated DMA done signal from the DMA controller clears the flag. If the
+ * condition that results in the assertion of the flag, interrupt, or DMA request is not
+ * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
+ * reasserts. For example, if the DMA or interrupt service routine fails to write
+ * sufficient data to the transmit buffer to raise it above the watermark level, the
+ * flag reasserts and generates another interrupt or DMA request. Reading an
+ * empty data register to clear one of the flags of the S1 register causes the FIFO
+ * pointers to become misaligned. A receive FIFO flush reinitializes the
+ * pointers. A better way to prevent this situation is to always leave one byte in FIFO
+ * and this byte will be read eventually in clearing the flag bit.
+ */
+/*!
+ * @name Constants and macros for entire UART_S1 register
+ */
+/*@{*/
+#define UART_RD_S1(base)         (UART_S1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S1 bitfields
+ */
+
+/*!
+ * @name Register UART_S1, field PF[0] (RO)
+ *
+ * PF is set when PE is set and the parity of the received data does not match
+ * its parity bit. The PF is not set in the case of an overrun condition. When PF
+ * is set, it indicates only that a dataword was received with parity error since
+ * the last time it was cleared. There is no guarantee that the first dataword
+ * read from the receive buffer has a parity error or that there is only one
+ * dataword in the buffer that was received with a parity error, unless the receive
+ * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
+ * disabled, Within the receive buffer structure the received dataword is tagged
+ * if it is received with a parity error. This information is available by reading
+ * the ED register prior to reading the D register.
+ *
+ * Values:
+ * - 0b0 - No parity error detected since the last time this flag was cleared.
+ *     If the receive buffer has a depth greater than 1, then there may be data in
+ *     the receive buffer what was received with a parity error.
+ * - 0b1 - At least one dataword was received with a parity error since the last
+ *     time this flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_PF field. */
+#define UART_RD_S1_PF(base)  ((UART_S1_REG(base) & UART_S1_PF_MASK) >> UART_S1_PF_SHIFT)
+#define UART_BRD_S1_PF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_PF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field FE[1] (RO)
+ *
+ * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
+ * then FE will set when a logic 0 is accepted for either of the two stop bits.
+ * FE does not set in the case of an overrun or while the LIN break detect feature
+ * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
+ * cleared. To clear FE, read S1 with FE set and then read D. The last data in the
+ * receive buffer represents the data that was received with the frame error
+ * enabled. Framing errors are not supported when 7816E is set/enabled. However, if
+ * this flag is set, data is still not received in 7816 mode.
+ *
+ * Values:
+ * - 0b0 - No framing error detected.
+ * - 0b1 - Framing error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_FE field. */
+#define UART_RD_S1_FE(base)  ((UART_S1_REG(base) & UART_S1_FE_MASK) >> UART_S1_FE_SHIFT)
+#define UART_BRD_S1_FE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_FE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field NF[2] (RO)
+ *
+ * NF is set when the UART detects noise on the receiver input. NF does not
+ * become set in the case of an overrun or while the LIN break detect feature is
+ * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
+ * been received with noise since the last time it was cleared. There is no
+ * guarantee that the first dataword read from the receive buffer has noise or that there
+ * is only one dataword in the buffer that was received with noise unless the
+ * receive buffer has a depth of one. To clear NF, read S1 and then read D.
+ *
+ * Values:
+ * - 0b0 - No noise detected since the last time this flag was cleared. If the
+ *     receive buffer has a depth greater than 1 then there may be data in the
+ *     receiver buffer that was received with noise.
+ * - 0b1 - At least one dataword was received with noise detected since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_NF field. */
+#define UART_RD_S1_NF(base)  ((UART_S1_REG(base) & UART_S1_NF_MASK) >> UART_S1_NF_SHIFT)
+#define UART_BRD_S1_NF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_NF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field OR[3] (RO)
+ *
+ * OR is set when software fails to prevent the receive data register from
+ * overflowing with data. The OR bit is set immediately after the stop bit has been
+ * completely received for the dataword that overflows the buffer and all the other
+ * error flags (FE, NF, and PF) are prevented from setting. The data in the
+ * shift register is lost, but the data already in the UART data registers is not
+ * affected. If the OR flag is set, no data is stored in the data buffer even if
+ * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
+ * flags are blocked from asserting, that is, transition from an inactive to an
+ * active state. To clear OR, read S1 when OR is set and then read D. See
+ * functional description for more details regarding the operation of the OR bit.If
+ * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
+ * is not cleared before the next data character is received. In 7816 mode, it is
+ * possible to configure a NACK to be returned by programing C7816[ONACK].
+ *
+ * Values:
+ * - 0b0 - No overrun has occurred since the last time the flag was cleared.
+ * - 0b1 - Overrun has occurred or the overrun flag has not been cleared since
+ *     the last overrun occured.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_OR field. */
+#define UART_RD_S1_OR(base)  ((UART_S1_REG(base) & UART_S1_OR_MASK) >> UART_S1_OR_SHIFT)
+#define UART_BRD_S1_OR(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_OR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field IDLE[4] (RO)
+ *
+ * After the IDLE flag is cleared, a frame must be received (although not
+ * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
+ * break character must set the S2[LBKDIF] flag before an idle condition can set the
+ * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
+ * IDLE is set when either of the following appear on the receiver input: 10
+ * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
+ * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
+ * detection is not supported when 7816E is set/enabled and hence this flag is
+ * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
+ * flag if RWUID is set, else the IDLE flag does not become set.
+ *
+ * Values:
+ * - 0b0 - Receiver input is either active now or has never become active since
+ *     the IDLE flag was last cleared.
+ * - 0b1 - Receiver input has become idle or the flag has not been cleared since
+ *     it last asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_IDLE field. */
+#define UART_RD_S1_IDLE(base) ((UART_S1_REG(base) & UART_S1_IDLE_MASK) >> UART_S1_IDLE_SHIFT)
+#define UART_BRD_S1_IDLE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field RDRF[5] (RO)
+ *
+ * RDRF is set when the number of datawords in the receive buffer is equal to or
+ * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
+ * process of being received is not included in the count. To clear RDRF, read S1
+ * when RDRF is set and then read D. For more efficient interrupt and DMA
+ * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
+ * Then read S1 and the final data value, resulting in the clearing of the RDRF
+ * flag. Even if RDRF is set, data will continue to be received until an overrun
+ * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
+ * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
+ * buffer but over-write each other.
+ *
+ * Values:
+ * - 0b0 - The number of datawords in the receive buffer is less than the number
+ *     indicated by RXWATER.
+ * - 0b1 - The number of datawords in the receive buffer is equal to or greater
+ *     than the number indicated by RXWATER at some point in time since this flag
+ *     was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_RDRF field. */
+#define UART_RD_S1_RDRF(base) ((UART_S1_REG(base) & UART_S1_RDRF_MASK) >> UART_S1_RDRF_SHIFT)
+#define UART_BRD_S1_RDRF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_RDRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TC[6] (RO)
+ *
+ * TC is set when the transmit buffer is empty and no data, preamble, or break
+ * character is being transmitted. When TC is set, the transmit data output signal
+ * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
+ * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
+ * set after any NACK signal has been received, but prior to any corresponding
+ * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
+ * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
+ * in C2.
+ *
+ * Values:
+ * - 0b0 - Transmitter active (sending data, a preamble, or a break).
+ * - 0b1 - Transmitter idle (transmission activity complete).
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TC field. */
+#define UART_RD_S1_TC(base)  ((UART_S1_REG(base) & UART_S1_TC_MASK) >> UART_S1_TC_SHIFT)
+#define UART_BRD_S1_TC(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_TC_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TDRE[7] (RO)
+ *
+ * TDRE will set when the number of datawords in the transmit buffer (D and
+ * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
+ * character that is in the process of being transmitted is not included in the count.
+ * To clear TDRE, read S1 when TDRE is set and then write to the UART data
+ * register (D). For more efficient interrupt servicing, all data except the final value
+ * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
+ * before writing the final data value, resulting in the clearing of the TRDE
+ * flag. This is more efficient because the TDRE reasserts until the watermark has
+ * been exceeded. So, attempting to clear the TDRE with every write will be
+ * ineffective until sufficient data has been written.
+ *
+ * Values:
+ * - 0b0 - The amount of data in the transmit buffer is greater than the value
+ *     indicated by TWFIFO[TXWATER].
+ * - 0b1 - The amount of data in the transmit buffer is less than or equal to
+ *     the value indicated by TWFIFO[TXWATER] at some point in time since the flag
+ *     has been cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TDRE field. */
+#define UART_RD_S1_TDRE(base) ((UART_S1_REG(base) & UART_S1_TDRE_MASK) >> UART_S1_TDRE_SHIFT)
+#define UART_BRD_S1_TDRE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_TDRE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S2 - UART Status Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S2 - UART Status Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The S2 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. Also, this register can be polled by the MCU to check the
+ * status of these bits. This register can be read or written at any time, with the
+ * exception of the MSBF and RXINV bits, which should be changed by the user only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_S2 register
+ */
+/*@{*/
+#define UART_RD_S2(base)         (UART_S2_REG(base))
+#define UART_WR_S2(base, value)  (UART_S2_REG(base) = (value))
+#define UART_RMW_S2(base, mask, value) (UART_WR_S2(base, (UART_RD_S2(base) & ~(mask)) | (value)))
+#define UART_SET_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) |  (value)))
+#define UART_CLR_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) & ~(value)))
+#define UART_TOG_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S2 bitfields
+ */
+
+/*!
+ * @name Register UART_S2, field RAF[0] (RO)
+ *
+ * RAF is set when the UART receiver detects a logic 0 during the RT1 time
+ * period of the start bit search. RAF is cleared when the receiver detects an idle
+ * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
+ * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
+ * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
+ * to configure the guard time to 12. However, if a NACK is required to be
+ * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
+ * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
+ * prior to actually being inactive.
+ *
+ * Values:
+ * - 0b0 - UART receiver idle/inactive waiting for a start bit.
+ * - 0b1 - UART receiver active, RxD input not idle.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RAF field. */
+#define UART_RD_S2_RAF(base) ((UART_S2_REG(base) & UART_S2_RAF_MASK) >> UART_S2_RAF_SHIFT)
+#define UART_BRD_S2_RAF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RAF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field LBKDE[1] (RW)
+ *
+ * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
+ * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
+ * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
+ *
+ * Values:
+ * - 0b0 - Break character detection is disabled.
+ * - 0b1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
+ *     12 bits time if C1[M] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_LBKDE field. */
+#define UART_RD_S2_LBKDE(base) ((UART_S2_REG(base) & UART_S2_LBKDE_MASK) >> UART_S2_LBKDE_SHIFT)
+#define UART_BRD_S2_LBKDE(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDE_SHIFT))
+
+/*! @brief Set the LBKDE field to a new value. */
+#define UART_WR_S2_LBKDE(base, value) (UART_RMW_S2(base, (UART_S2_LBKDE_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_LBKDE(value)))
+#define UART_BWR_S2_LBKDE(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field BRK13[2] (RW)
+ *
+ * Determines whether the transmit break character is 10, 11, or 12 bits long,
+ * or 13 or 14 bits long. See for the length of the break character for the
+ * different configurations. The detection of a framing error is not affected by this
+ * field. Transmitting break characters
+ *
+ * Values:
+ * - 0b0 - Break character is 10, 11, or 12 bits long.
+ * - 0b1 - Break character is 13 or 14 bits long.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_BRK13 field. */
+#define UART_RD_S2_BRK13(base) ((UART_S2_REG(base) & UART_S2_BRK13_MASK) >> UART_S2_BRK13_SHIFT)
+#define UART_BRD_S2_BRK13(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT))
+
+/*! @brief Set the BRK13 field to a new value. */
+#define UART_WR_S2_BRK13(base, value) (UART_RMW_S2(base, (UART_S2_BRK13_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_BRK13(value)))
+#define UART_BWR_S2_BRK13(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RWUID[3] (RW)
+ *
+ * When RWU is set and WAKE is cleared, this field controls whether the idle
+ * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - S1[IDLE] is not set upon detection of an idle character.
+ * - 0b1 - S1[IDLE] is set upon detection of an idle character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RWUID field. */
+#define UART_RD_S2_RWUID(base) ((UART_S2_REG(base) & UART_S2_RWUID_MASK) >> UART_S2_RWUID_SHIFT)
+#define UART_BRD_S2_RWUID(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT))
+
+/*! @brief Set the RWUID field to a new value. */
+#define UART_WR_S2_RWUID(base, value) (UART_RMW_S2(base, (UART_S2_RWUID_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RWUID(value)))
+#define UART_BWR_S2_RWUID(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the received data input. In NRZ
+ * format, a one is represented by a mark and a zero is represented by a space for
+ * normal polarity, and the opposite for inverted polarity. In IrDA format, a
+ * zero is represented by short high pulse in the middle of a bit time remaining
+ * idle low for a one for normal polarity. A zero is represented by a short low
+ * pulse in the middle of a bit time remaining idle high for a one for inverted
+ * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
+ * enabled and an initial character is detected in T = 0 protocol mode. Setting
+ * RXINV inverts the RxD input for data bits, start and stop bits, break, and
+ * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
+ * are inverted.
+ *
+ * Values:
+ * - 0b0 - Receive data is not inverted.
+ * - 0b1 - Receive data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXINV field. */
+#define UART_RD_S2_RXINV(base) ((UART_S2_REG(base) & UART_S2_RXINV_MASK) >> UART_S2_RXINV_SHIFT)
+#define UART_BRD_S2_RXINV(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT))
+
+/*! @brief Set the RXINV field to a new value. */
+#define UART_WR_S2_RXINV(base, value) (UART_RMW_S2(base, (UART_S2_RXINV_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RXINV(value)))
+#define UART_BWR_S2_RXINV(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field MSBF[5] (RW)
+ *
+ * Setting this field reverses the order of the bits that are transmitted and
+ * received on the wire. This field does not affect the polarity of the bits, the
+ * location of the parity bit, or the location of the start or stop bits. This
+ * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
+ * an initial character is detected in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0b0 - LSB (bit0) is the first bit that is transmitted following the start
+ *     bit. Further, the first bit received after the start bit is identified as
+ *     bit0.
+ * - 0b1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted
+ *     following the start bit, depending on the setting of C1[M] and C1[PE]. Further,
+ *     the first bit received after the start bit is identified as bit8, bit7, or
+ *     bit6, depending on the setting of C1[M] and C1[PE].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_MSBF field. */
+#define UART_RD_S2_MSBF(base) ((UART_S2_REG(base) & UART_S2_MSBF_MASK) >> UART_S2_MSBF_SHIFT)
+#define UART_BRD_S2_MSBF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT))
+
+/*! @brief Set the MSBF field to a new value. */
+#define UART_WR_S2_MSBF(base, value) (UART_RMW_S2(base, (UART_S2_MSBF_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_MSBF(value)))
+#define UART_BWR_S2_MSBF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXEDGIF[6] (W1C)
+ *
+ * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
+ * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
+ * to it. See for additional details. RXEDGIF description The active edge is
+ * detected only in two wire mode and on receiving data coming from the RxD pin.
+ *
+ * Values:
+ * - 0b0 - No active edge on the receive pin has occurred.
+ * - 0b1 - An active edge on the receive pin has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXEDGIF field. */
+#define UART_RD_S2_RXEDGIF(base) ((UART_S2_REG(base) & UART_S2_RXEDGIF_MASK) >> UART_S2_RXEDGIF_SHIFT)
+#define UART_BRD_S2_RXEDGIF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT))
+
+/*! @brief Set the RXEDGIF field to a new value. */
+#define UART_WR_S2_RXEDGIF(base, value) (UART_RMW_S2(base, (UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RXEDGIF(value)))
+#define UART_BWR_S2_RXEDGIF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field LBKDIF[7] (W1C)
+ *
+ * LBKDIF is set when LBKDE is set and a LIN break character is detected on the
+ * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
+ * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
+ * last LIN break character. LBKDIF is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - No LIN break character detected.
+ * - 0b1 - LIN break character detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_LBKDIF field. */
+#define UART_RD_S2_LBKDIF(base) ((UART_S2_REG(base) & UART_S2_LBKDIF_MASK) >> UART_S2_LBKDIF_SHIFT)
+#define UART_BRD_S2_LBKDIF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDIF_SHIFT))
+
+/*! @brief Set the LBKDIF field to a new value. */
+#define UART_WR_S2_LBKDIF(base, value) (UART_RMW_S2(base, (UART_S2_LBKDIF_MASK | UART_S2_RXEDGIF_MASK), UART_S2_LBKDIF(value)))
+#define UART_BWR_S2_LBKDIF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDIF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C3 - UART Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C3 - UART Control Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_C3 register
+ */
+/*@{*/
+#define UART_RD_C3(base)         (UART_C3_REG(base))
+#define UART_WR_C3(base, value)  (UART_C3_REG(base) = (value))
+#define UART_RMW_C3(base, mask, value) (UART_WR_C3(base, (UART_RD_C3(base) & ~(mask)) | (value)))
+#define UART_SET_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) |  (value)))
+#define UART_CLR_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) & ~(value)))
+#define UART_TOG_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C3 bitfields
+ */
+
+/*!
+ * @name Register UART_C3, field PEIE[0] (RW)
+ *
+ * Enables the parity error flag, S1[PF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - PF interrupt requests are disabled.
+ * - 0b1 - PF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_PEIE field. */
+#define UART_RD_C3_PEIE(base) ((UART_C3_REG(base) & UART_C3_PEIE_MASK) >> UART_C3_PEIE_SHIFT)
+#define UART_BRD_C3_PEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT))
+
+/*! @brief Set the PEIE field to a new value. */
+#define UART_WR_C3_PEIE(base, value) (UART_RMW_C3(base, UART_C3_PEIE_MASK, UART_C3_PEIE(value)))
+#define UART_BWR_C3_PEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field FEIE[1] (RW)
+ *
+ * Enables the framing error flag, S1[FE], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - FE interrupt requests are disabled.
+ * - 0b1 - FE interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_FEIE field. */
+#define UART_RD_C3_FEIE(base) ((UART_C3_REG(base) & UART_C3_FEIE_MASK) >> UART_C3_FEIE_SHIFT)
+#define UART_BRD_C3_FEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define UART_WR_C3_FEIE(base, value) (UART_RMW_C3(base, UART_C3_FEIE_MASK, UART_C3_FEIE(value)))
+#define UART_BWR_C3_FEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field NEIE[2] (RW)
+ *
+ * Enables the noise flag, S1[NF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - NF interrupt requests are disabled.
+ * - 0b1 - NF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_NEIE field. */
+#define UART_RD_C3_NEIE(base) ((UART_C3_REG(base) & UART_C3_NEIE_MASK) >> UART_C3_NEIE_SHIFT)
+#define UART_BRD_C3_NEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT))
+
+/*! @brief Set the NEIE field to a new value. */
+#define UART_WR_C3_NEIE(base, value) (UART_RMW_C3(base, UART_C3_NEIE_MASK, UART_C3_NEIE(value)))
+#define UART_BWR_C3_NEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field ORIE[3] (RW)
+ *
+ * Enables the overrun error flag, S1[OR], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - OR interrupts are disabled.
+ * - 0b1 - OR interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_ORIE field. */
+#define UART_RD_C3_ORIE(base) ((UART_C3_REG(base) & UART_C3_ORIE_MASK) >> UART_C3_ORIE_SHIFT)
+#define UART_BRD_C3_ORIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT))
+
+/*! @brief Set the ORIE field to a new value. */
+#define UART_WR_C3_ORIE(base, value) (UART_RMW_C3(base, UART_C3_ORIE_MASK, UART_C3_ORIE(value)))
+#define UART_BWR_C3_ORIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the transmitted data output. In
+ * NRZ format, a one is represented by a mark and a zero is represented by a space
+ * for normal polarity, and the opposite for inverted polarity. In IrDA format,
+ * a zero is represented by short high pulse in the middle of a bit time
+ * remaining idle low for a one for normal polarity, and a zero is represented by short
+ * low pulse in the middle of a bit time remaining idle high for a one for
+ * inverted polarity. This field is automatically set when C7816[INIT] and
+ * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
+ * Setting TXINV inverts all transmitted values, including idle, break, start, and
+ * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
+ * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
+ * the transmitted data bits and parity bit are inverted.
+ *
+ * Values:
+ * - 0b0 - Transmit data is not inverted.
+ * - 0b1 - Transmit data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXINV field. */
+#define UART_RD_C3_TXINV(base) ((UART_C3_REG(base) & UART_C3_TXINV_MASK) >> UART_C3_TXINV_SHIFT)
+#define UART_BRD_C3_TXINV(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT))
+
+/*! @brief Set the TXINV field to a new value. */
+#define UART_WR_C3_TXINV(base, value) (UART_RMW_C3(base, UART_C3_TXINV_MASK, UART_C3_TXINV(value)))
+#define UART_BWR_C3_TXINV(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXDIR[5] (RW)
+ *
+ * Determines whether the TXD pin is used as an input or output in the
+ * single-wire mode of operation. This field is relevant only to the single wire mode.
+ * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
+ * automatically cleared after the requested block is transmitted. This condition is
+ * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
+ * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
+ * being transmitted, the hardware automatically overrides this field as needed. In
+ * this situation, TXDIR does not reflect the temporary state associated with
+ * the NACK.
+ *
+ * Values:
+ * - 0b0 - TXD pin is an input in single wire mode.
+ * - 0b1 - TXD pin is an output in single wire mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXDIR field. */
+#define UART_RD_C3_TXDIR(base) ((UART_C3_REG(base) & UART_C3_TXDIR_MASK) >> UART_C3_TXDIR_SHIFT)
+#define UART_BRD_C3_TXDIR(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT))
+
+/*! @brief Set the TXDIR field to a new value. */
+#define UART_WR_C3_TXDIR(base, value) (UART_RMW_C3(base, UART_C3_TXDIR_MASK, UART_C3_TXDIR(value)))
+#define UART_BWR_C3_TXDIR(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field T8[6] (RW)
+ *
+ * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
+ * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
+ * same as in the previous transmission, T8 does not have to be rewritten. The same
+ * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
+ * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
+ * the remaining data.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_T8 field. */
+#define UART_RD_C3_T8(base)  ((UART_C3_REG(base) & UART_C3_T8_MASK) >> UART_C3_T8_SHIFT)
+#define UART_BRD_C3_T8(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_T8_SHIFT))
+
+/*! @brief Set the T8 field to a new value. */
+#define UART_WR_C3_T8(base, value) (UART_RMW_C3(base, UART_C3_T8_MASK, UART_C3_T8(value)))
+#define UART_BWR_C3_T8(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_T8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field R8[7] (RO)
+ *
+ * R8 is the ninth data bit received when the UART is configured for 9-bit data
+ * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
+ * current data value in the UARTx_D register. To read the 9th bit, read the
+ * value of UARTx_C3[R8], then read the UARTx_D register.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_R8 field. */
+#define UART_RD_C3_R8(base)  ((UART_C3_REG(base) & UART_C3_R8_MASK) >> UART_C3_R8_SHIFT)
+#define UART_BRD_C3_R8(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_R8_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_D - UART Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_D - UART Data Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is actually two separate registers. Reads return the contents
+ * of the read-only receive data register and writes go to the write-only transmit
+ * data register. In 8-bit or 9-bit data format, only UART data register (D)
+ * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
+ * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
+ * register, only if the ninth bit of data needs to be captured. Similarly, the
+ * ED register needs to be read, prior to the D register, only if the additional
+ * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
+ * bit cleared) if the parity is enabled, you get seven data bits and one parity
+ * bit. That one parity bit is loaded into the D register. So, for the data bits,
+ * mask off the parity bit from the value you read out of this register. When
+ * transmitting in 9-bit data format and using 8-bit write instructions, write first
+ * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
+ * C3[T8] stores the data in a temporary register. If D register is written first,
+ * and then the new data on data bus is stored in D, the temporary value written by
+ * the last write to C3[T8] gets stored in the C3[T8] register.
+ */
+/*!
+ * @name Constants and macros for entire UART_D register
+ */
+/*@{*/
+#define UART_RD_D(base)          (UART_D_REG(base))
+#define UART_WR_D(base, value)   (UART_D_REG(base) = (value))
+#define UART_RMW_D(base, mask, value) (UART_WR_D(base, (UART_RD_D(base) & ~(mask)) | (value)))
+#define UART_SET_D(base, value)  (UART_WR_D(base, UART_RD_D(base) |  (value)))
+#define UART_CLR_D(base, value)  (UART_WR_D(base, UART_RD_D(base) & ~(value)))
+#define UART_TOG_D(base, value)  (UART_WR_D(base, UART_RD_D(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA1 - UART Match Address Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA1 - UART Match Address Registers 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MA1 and MA2 registers are compared to input data addresses when the most
+ * significant bit is set and the associated C4[MAEN] field is set. If a match
+ * occurs, the following data is transferred to the data register. If a match
+ * fails, the following data is discarded. These registers can be read and written at
+ * anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA1 register
+ */
+/*@{*/
+#define UART_RD_MA1(base)        (UART_MA1_REG(base))
+#define UART_WR_MA1(base, value) (UART_MA1_REG(base) = (value))
+#define UART_RMW_MA1(base, mask, value) (UART_WR_MA1(base, (UART_RD_MA1(base) & ~(mask)) | (value)))
+#define UART_SET_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) |  (value)))
+#define UART_CLR_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) & ~(value)))
+#define UART_TOG_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA2 - UART Match Address Registers 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA2 - UART Match Address Registers 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * These registers can be read and written at anytime. The MA1 and MA2 registers
+ * are compared to input data addresses when the most significant bit is set and
+ * the associated C4[MAEN] field is set. If a match occurs, the following data
+ * is transferred to the data register. If a match fails, the following data is
+ * discarded.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA2 register
+ */
+/*@{*/
+#define UART_RD_MA2(base)        (UART_MA2_REG(base))
+#define UART_WR_MA2(base, value) (UART_MA2_REG(base) = (value))
+#define UART_RMW_MA2(base, mask, value) (UART_WR_MA2(base, (UART_RD_MA2(base) & ~(mask)) | (value)))
+#define UART_SET_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) |  (value)))
+#define UART_CLR_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) & ~(value)))
+#define UART_TOG_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C4 - UART Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C4 - UART Control Register 4 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C4 register
+ */
+/*@{*/
+#define UART_RD_C4(base)         (UART_C4_REG(base))
+#define UART_WR_C4(base, value)  (UART_C4_REG(base) = (value))
+#define UART_RMW_C4(base, mask, value) (UART_WR_C4(base, (UART_RD_C4(base) & ~(mask)) | (value)))
+#define UART_SET_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) |  (value)))
+#define UART_CLR_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) & ~(value)))
+#define UART_TOG_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C4 bitfields
+ */
+
+/*!
+ * @name Register UART_C4, field BRFA[4:0] (RW)
+ *
+ * This bit field is used to add more timing resolution to the average baud
+ * frequency, in increments of 1/32. See Baud rate generation for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_BRFA field. */
+#define UART_RD_C4_BRFA(base) ((UART_C4_REG(base) & UART_C4_BRFA_MASK) >> UART_C4_BRFA_SHIFT)
+#define UART_BRD_C4_BRFA(base) (UART_RD_C4_BRFA(base))
+
+/*! @brief Set the BRFA field to a new value. */
+#define UART_WR_C4_BRFA(base, value) (UART_RMW_C4(base, UART_C4_BRFA_MASK, UART_C4_BRFA(value)))
+#define UART_BWR_C4_BRFA(base, value) (UART_WR_C4_BRFA(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field M10[5] (RW)
+ *
+ * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
+ * This tenth bit is generated and interpreted as a parity bit. The M10 field
+ * does not affect the LIN send or detect break behavior. If M10 is set, then both
+ * C1[M] and C1[PE] must also be set. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
+ *
+ * Values:
+ * - 0b0 - The parity bit is the ninth bit in the serial transmission.
+ * - 0b1 - The parity bit is the tenth bit in the serial transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_M10 field. */
+#define UART_RD_C4_M10(base) ((UART_C4_REG(base) & UART_C4_M10_MASK) >> UART_C4_M10_SHIFT)
+#define UART_BRD_C4_M10(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_M10_SHIFT))
+
+/*! @brief Set the M10 field to a new value. */
+#define UART_WR_C4_M10(base, value) (UART_RMW_C4(base, UART_C4_M10_MASK, UART_C4_M10(value)))
+#define UART_BWR_C4_M10(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_M10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN2[6] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0b0 - All data received is transferred to the data buffer if MAEN1 is
+ *     cleared.
+ * - 0b1 - All data received with the most significant bit cleared, is
+ *     discarded. All data received with the most significant bit set, is compared with
+ *     contents of MA2 register. If no match occurs, the data is discarded. If a
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN2 field. */
+#define UART_RD_C4_MAEN2(base) ((UART_C4_REG(base) & UART_C4_MAEN2_MASK) >> UART_C4_MAEN2_SHIFT)
+#define UART_BRD_C4_MAEN2(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT))
+
+/*! @brief Set the MAEN2 field to a new value. */
+#define UART_WR_C4_MAEN2(base, value) (UART_RMW_C4(base, UART_C4_MAEN2_MASK, UART_C4_MAEN2(value)))
+#define UART_BWR_C4_MAEN2(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN1[7] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0b0 - All data received is transferred to the data buffer if MAEN2 is
+ *     cleared.
+ * - 0b1 - All data received with the most significant bit cleared, is
+ *     discarded. All data received with the most significant bit set, is compared with
+ *     contents of MA1 register. If no match occurs, the data is discarded. If
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN1 field. */
+#define UART_RD_C4_MAEN1(base) ((UART_C4_REG(base) & UART_C4_MAEN1_MASK) >> UART_C4_MAEN1_SHIFT)
+#define UART_BRD_C4_MAEN1(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT))
+
+/*! @brief Set the MAEN1 field to a new value. */
+#define UART_WR_C4_MAEN1(base, value) (UART_RMW_C4(base, UART_C4_MAEN1_MASK, UART_C4_MAEN1(value)))
+#define UART_BWR_C4_MAEN1(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C5 - UART Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C5 - UART Control Register 5 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C5 register
+ */
+/*@{*/
+#define UART_RD_C5(base)         (UART_C5_REG(base))
+#define UART_WR_C5(base, value)  (UART_C5_REG(base) = (value))
+#define UART_RMW_C5(base, mask, value) (UART_WR_C5(base, (UART_RD_C5(base) & ~(mask)) | (value)))
+#define UART_SET_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) |  (value)))
+#define UART_CLR_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) & ~(value)))
+#define UART_TOG_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C5 bitfields
+ */
+
+/*!
+ * @name Register UART_C5, field LBKDDMAS[3] (RW)
+ *
+ * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
+ * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
+ * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
+ * of the state of LBKDDMAS.
+ *
+ * Values:
+ * - 0b0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
+ *     asserted to request an interrupt service.
+ * - 0b1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal
+ *     is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_LBKDDMAS field. */
+#define UART_RD_C5_LBKDDMAS(base) ((UART_C5_REG(base) & UART_C5_LBKDDMAS_MASK) >> UART_C5_LBKDDMAS_SHIFT)
+#define UART_BRD_C5_LBKDDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_LBKDDMAS_SHIFT))
+
+/*! @brief Set the LBKDDMAS field to a new value. */
+#define UART_WR_C5_LBKDDMAS(base, value) (UART_RMW_C5(base, UART_C5_LBKDDMAS_MASK, UART_C5_LBKDDMAS(value)))
+#define UART_BWR_C5_LBKDDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_LBKDDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field ILDMAS[4] (RW)
+ *
+ * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
+ * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
+ * DMA and IDLE interrupt request signals are not asserted, regardless of the state
+ * of ILDMAS.
+ *
+ * Values:
+ * - 0b0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal
+ *     is asserted to request an interrupt service.
+ * - 0b1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_ILDMAS field. */
+#define UART_RD_C5_ILDMAS(base) ((UART_C5_REG(base) & UART_C5_ILDMAS_MASK) >> UART_C5_ILDMAS_SHIFT)
+#define UART_BRD_C5_ILDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_ILDMAS_SHIFT))
+
+/*! @brief Set the ILDMAS field to a new value. */
+#define UART_WR_C5_ILDMAS(base, value) (UART_RMW_C5(base, UART_C5_ILDMAS_MASK, UART_C5_ILDMAS(value)))
+#define UART_BWR_C5_ILDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_ILDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field RDMAS[5] (RW)
+ *
+ * Configures the receiver data register full flag, S1[RDRF], to generate
+ * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
+ * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
+ * regardless of the state of RDMAS.
+ *
+ * Values:
+ * - 0b0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
+ *     asserted to request an interrupt service.
+ * - 0b1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_RDMAS field. */
+#define UART_RD_C5_RDMAS(base) ((UART_C5_REG(base) & UART_C5_RDMAS_MASK) >> UART_C5_RDMAS_SHIFT)
+#define UART_BRD_C5_RDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT))
+
+/*! @brief Set the RDMAS field to a new value. */
+#define UART_WR_C5_RDMAS(base, value) (UART_RMW_C5(base, UART_C5_RDMAS_MASK, UART_C5_RDMAS(value)))
+#define UART_BWR_C5_RDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TCDMAS[6] (RW)
+ *
+ * Configures the transmission complete flag, S1[TC], to generate interrupt or
+ * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
+ * interrupt request signals are not asserted when the S1[TC] flag is set, regardless
+ * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
+ * must be cleared, and D must not be written unless a DMA request is being serviced.
+ *
+ * Values:
+ * - 0b0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt
+ *     request signal is asserted to request an interrupt service.
+ * - 0b1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TCDMAS field. */
+#define UART_RD_C5_TCDMAS(base) ((UART_C5_REG(base) & UART_C5_TCDMAS_MASK) >> UART_C5_TCDMAS_SHIFT)
+#define UART_BRD_C5_TCDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TCDMAS_SHIFT))
+
+/*! @brief Set the TCDMAS field to a new value. */
+#define UART_WR_C5_TCDMAS(base, value) (UART_RMW_C5(base, UART_C5_TCDMAS_MASK, UART_C5_TCDMAS(value)))
+#define UART_BWR_C5_TCDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TCDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TDMAS[7] (RW)
+ *
+ * Configures the transmit data register empty flag, S1[TDRE], to generate
+ * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
+ * TDRE interrupt request signals are not asserted when the TDRE flag is set,
+ * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
+ * must be cleared, and D must not be written unless a DMA request is being
+ * serviced.
+ *
+ * Values:
+ * - 0b0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
+ *     request signal is asserted to request interrupt service.
+ * - 0b1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TDMAS field. */
+#define UART_RD_C5_TDMAS(base) ((UART_C5_REG(base) & UART_C5_TDMAS_MASK) >> UART_C5_TDMAS_SHIFT)
+#define UART_BRD_C5_TDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT))
+
+/*! @brief Set the TDMAS field to a new value. */
+#define UART_WR_C5_TDMAS(base, value) (UART_RMW_C5(base, UART_C5_TDMAS_MASK, UART_C5_TDMAS(value)))
+#define UART_BWR_C5_TDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ED - UART Extended Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ED - UART Extended Data Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains additional information flags that are stored with a
+ * received dataword. This register may be read at any time but contains valid data
+ * only if there is a dataword in the receive FIFO. The data contained in this
+ * register represents additional information regarding the conditions on which a
+ * dataword was received. The importance of this data varies with the
+ * application, and in some cases maybe completely optional. These fields automatically
+ * update to reflect the conditions of the next dataword whenever D is read. If
+ * S1[NF] and S1[PF] have not been set since the last time the receive buffer was
+ * empty, the NOISY and PARITYE fields will be zero.
+ */
+/*!
+ * @name Constants and macros for entire UART_ED register
+ */
+/*@{*/
+#define UART_RD_ED(base)         (UART_ED_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ED bitfields
+ */
+
+/*!
+ * @name Register UART_ED, field PARITYE[6] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with a
+ * parity error.
+ *
+ * Values:
+ * - 0b0 - The dataword was received without a parity error.
+ * - 0b1 - The dataword was received with a parity error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ED_PARITYE field. */
+#define UART_RD_ED_PARITYE(base) ((UART_ED_REG(base) & UART_ED_PARITYE_MASK) >> UART_ED_PARITYE_SHIFT)
+#define UART_BRD_ED_PARITYE(base) (BITBAND_ACCESS8(&UART_ED_REG(base), UART_ED_PARITYE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_ED, field NOISY[7] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with
+ * noise.
+ *
+ * Values:
+ * - 0b0 - The dataword was received without noise.
+ * - 0b1 - The data was received with noise.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ED_NOISY field. */
+#define UART_RD_ED_NOISY(base) ((UART_ED_REG(base) & UART_ED_NOISY_MASK) >> UART_ED_NOISY_SHIFT)
+#define UART_BRD_ED_NOISY(base) (BITBAND_ACCESS8(&UART_ED_REG(base), UART_ED_NOISY_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MODEM - UART Modem Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MODEM - UART Modem Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MODEM register controls options for setting the modem configuration.
+ * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
+ * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
+ * ISO-7816 protocol does not use the RTS and CTS signals.
+ */
+/*!
+ * @name Constants and macros for entire UART_MODEM register
+ */
+/*@{*/
+#define UART_RD_MODEM(base)      (UART_MODEM_REG(base))
+#define UART_WR_MODEM(base, value) (UART_MODEM_REG(base) = (value))
+#define UART_RMW_MODEM(base, mask, value) (UART_WR_MODEM(base, (UART_RD_MODEM(base) & ~(mask)) | (value)))
+#define UART_SET_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) |  (value)))
+#define UART_CLR_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) & ~(value)))
+#define UART_TOG_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_MODEM bitfields
+ */
+
+/*!
+ * @name Register UART_MODEM, field TXCTSE[0] (RW)
+ *
+ * TXCTSE controls the operation of the transmitter. TXCTSE can be set
+ * independently from the state of TXRTSE and RXRTSE.
+ *
+ * Values:
+ * - 0b0 - CTS has no effect on the transmitter.
+ * - 0b1 - Enables clear-to-send operation. The transmitter checks the state of
+ *     CTS each time it is ready to send a character. If CTS is asserted, the
+ *     character is sent. If CTS is deasserted, the signal TXD remains in the mark
+ *     state and transmission is delayed until CTS is asserted. Changes in CTS as
+ *     a character is being sent do not affect its transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXCTSE field. */
+#define UART_RD_MODEM_TXCTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_TXCTSE_MASK) >> UART_MODEM_TXCTSE_SHIFT)
+#define UART_BRD_MODEM_TXCTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXCTSE_SHIFT))
+
+/*! @brief Set the TXCTSE field to a new value. */
+#define UART_WR_MODEM_TXCTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXCTSE_MASK, UART_MODEM_TXCTSE(value)))
+#define UART_BWR_MODEM_TXCTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXCTSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field TXRTSE[1] (RW)
+ *
+ * Controls RTS before and after a transmission.
+ *
+ * Values:
+ * - 0b0 - The transmitter has no effect on RTS.
+ * - 0b1 - When a character is placed into an empty transmitter data buffer ,
+ *     RTS asserts one bit time before the start bit is transmitted. RTS deasserts
+ *     one bit time after all characters in the transmitter data buffer and shift
+ *     register are completely sent, including the last stop bit. (FIFO) (FIFO)
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXRTSE field. */
+#define UART_RD_MODEM_TXRTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_TXRTSE_MASK) >> UART_MODEM_TXRTSE_SHIFT)
+#define UART_BRD_MODEM_TXRTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSE_SHIFT))
+
+/*! @brief Set the TXRTSE field to a new value. */
+#define UART_WR_MODEM_TXRTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXRTSE_MASK, UART_MODEM_TXRTSE(value)))
+#define UART_BWR_MODEM_TXRTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field TXRTSPOL[2] (RW)
+ *
+ * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
+ * polarity of the receiver RTS. RTS will remain negated in the active low state
+ * unless TXRTSE is set.
+ *
+ * Values:
+ * - 0b0 - Transmitter RTS is active low.
+ * - 0b1 - Transmitter RTS is active high.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXRTSPOL field. */
+#define UART_RD_MODEM_TXRTSPOL(base) ((UART_MODEM_REG(base) & UART_MODEM_TXRTSPOL_MASK) >> UART_MODEM_TXRTSPOL_SHIFT)
+#define UART_BRD_MODEM_TXRTSPOL(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSPOL_SHIFT))
+
+/*! @brief Set the TXRTSPOL field to a new value. */
+#define UART_WR_MODEM_TXRTSPOL(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXRTSPOL_MASK, UART_MODEM_TXRTSPOL(value)))
+#define UART_BWR_MODEM_TXRTSPOL(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field RXRTSE[3] (RW)
+ *
+ * Allows the RTS output to control the CTS input of the transmitting device to
+ * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
+ *
+ * Values:
+ * - 0b0 - The receiver has no effect on RTS.
+ * - 0b1 - RTS is deasserted if the number of characters in the receiver data
+ *     register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
+ *     when the number of characters in the receiver data register (FIFO) is
+ *     less than RWFIFO[RXWATER].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_RXRTSE field. */
+#define UART_RD_MODEM_RXRTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_RXRTSE_MASK) >> UART_MODEM_RXRTSE_SHIFT)
+#define UART_BRD_MODEM_RXRTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_RXRTSE_SHIFT))
+
+/*! @brief Set the RXRTSE field to a new value. */
+#define UART_WR_MODEM_RXRTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_RXRTSE_MASK, UART_MODEM_RXRTSE(value)))
+#define UART_BWR_MODEM_RXRTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_RXRTSE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IR - UART Infrared Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IR - UART Infrared Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IR register controls options for setting the infrared configuration.
+ */
+/*!
+ * @name Constants and macros for entire UART_IR register
+ */
+/*@{*/
+#define UART_RD_IR(base)         (UART_IR_REG(base))
+#define UART_WR_IR(base, value)  (UART_IR_REG(base) = (value))
+#define UART_RMW_IR(base, mask, value) (UART_WR_IR(base, (UART_RD_IR(base) & ~(mask)) | (value)))
+#define UART_SET_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) |  (value)))
+#define UART_CLR_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) & ~(value)))
+#define UART_TOG_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IR bitfields
+ */
+
+/*!
+ * @name Register UART_IR, field TNP[1:0] (RW)
+ *
+ * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
+ *
+ * Values:
+ * - 0b00 - 3/16.
+ * - 0b01 - 1/16.
+ * - 0b10 - 1/32.
+ * - 0b11 - 1/4.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IR_TNP field. */
+#define UART_RD_IR_TNP(base) ((UART_IR_REG(base) & UART_IR_TNP_MASK) >> UART_IR_TNP_SHIFT)
+#define UART_BRD_IR_TNP(base) (UART_RD_IR_TNP(base))
+
+/*! @brief Set the TNP field to a new value. */
+#define UART_WR_IR_TNP(base, value) (UART_RMW_IR(base, UART_IR_TNP_MASK, UART_IR_TNP(value)))
+#define UART_BWR_IR_TNP(base, value) (UART_WR_IR_TNP(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_IR, field IREN[2] (RW)
+ *
+ * Enables/disables the infrared modulation/demodulation.
+ *
+ * Values:
+ * - 0b0 - IR disabled.
+ * - 0b1 - IR enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IR_IREN field. */
+#define UART_RD_IR_IREN(base) ((UART_IR_REG(base) & UART_IR_IREN_MASK) >> UART_IR_IREN_SHIFT)
+#define UART_BRD_IR_IREN(base) (BITBAND_ACCESS8(&UART_IR_REG(base), UART_IR_IREN_SHIFT))
+
+/*! @brief Set the IREN field to a new value. */
+#define UART_WR_IR_IREN(base, value) (UART_RMW_IR(base, UART_IR_IREN_MASK, UART_IR_IREN(value)))
+#define UART_BWR_IR_IREN(base, value) (BITBAND_ACCESS8(&UART_IR_REG(base), UART_IR_IREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_PFIFO - UART FIFO Parameters
+ ******************************************************************************/
+
+/*!
+ * @brief UART_PFIFO - UART FIFO Parameters (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability for the programmer to turn on and off FIFO
+ * functionality. It also provides the size of the FIFO that has been
+ * implemented. This register may be read at any time. This register must be written only
+ * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
+ * empty.
+ */
+/*!
+ * @name Constants and macros for entire UART_PFIFO register
+ */
+/*@{*/
+#define UART_RD_PFIFO(base)      (UART_PFIFO_REG(base))
+#define UART_WR_PFIFO(base, value) (UART_PFIFO_REG(base) = (value))
+#define UART_RMW_PFIFO(base, mask, value) (UART_WR_PFIFO(base, (UART_RD_PFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) |  (value)))
+#define UART_CLR_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) & ~(value)))
+#define UART_TOG_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_PFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
+ *
+ * The maximum number of receive datawords that can be stored in the receive
+ * buffer before an overrun occurs. This field is read only.
+ *
+ * Values:
+ * - 0b000 - Receive FIFO/Buffer depth = 1 dataword.
+ * - 0b001 - Receive FIFO/Buffer depth = 4 datawords.
+ * - 0b010 - Receive FIFO/Buffer depth = 8 datawords.
+ * - 0b011 - Receive FIFO/Buffer depth = 16 datawords.
+ * - 0b100 - Receive FIFO/Buffer depth = 32 datawords.
+ * - 0b101 - Receive FIFO/Buffer depth = 64 datawords.
+ * - 0b110 - Receive FIFO/Buffer depth = 128 datawords.
+ * - 0b111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. */
+#define UART_RD_PFIFO_RXFIFOSIZE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_RXFIFOSIZE_MASK) >> UART_PFIFO_RXFIFOSIZE_SHIFT)
+#define UART_BRD_PFIFO_RXFIFOSIZE(base) (UART_RD_PFIFO_RXFIFOSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field RXFE[3] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the receive buffer is
+ * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
+ * If this field is not set, the receive buffer operates as a FIFO of depth one
+ * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
+ * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
+ * commands must be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0b0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
+ * - 0b1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_RXFE field. */
+#define UART_RD_PFIFO_RXFE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_RXFE_MASK) >> UART_PFIFO_RXFE_SHIFT)
+#define UART_BRD_PFIFO_RXFE(base) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_RXFE_SHIFT))
+
+/*! @brief Set the RXFE field to a new value. */
+#define UART_WR_PFIFO_RXFE(base, value) (UART_RMW_PFIFO(base, UART_PFIFO_RXFE_MASK, UART_PFIFO_RXFE(value)))
+#define UART_BWR_PFIFO_RXFE(base, value) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_RXFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
+ *
+ * The maximum number of transmit datawords that can be stored in the transmit
+ * buffer. This field is read only.
+ *
+ * Values:
+ * - 0b000 - Transmit FIFO/Buffer depth = 1 dataword.
+ * - 0b001 - Transmit FIFO/Buffer depth = 4 datawords.
+ * - 0b010 - Transmit FIFO/Buffer depth = 8 datawords.
+ * - 0b011 - Transmit FIFO/Buffer depth = 16 datawords.
+ * - 0b100 - Transmit FIFO/Buffer depth = 32 datawords.
+ * - 0b101 - Transmit FIFO/Buffer depth = 64 datawords.
+ * - 0b110 - Transmit FIFO/Buffer depth = 128 datawords.
+ * - 0b111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. */
+#define UART_RD_PFIFO_TXFIFOSIZE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_TXFIFOSIZE_MASK) >> UART_PFIFO_TXFIFOSIZE_SHIFT)
+#define UART_BRD_PFIFO_TXFIFOSIZE(base) (UART_RD_PFIFO_TXFIFOSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field TXFE[7] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the transmit buffer
+ * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
+ * field is not set, the transmit buffer operates as a FIFO of depth one dataword
+ * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
+ * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
+ * be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0b0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
+ * - 0b1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_TXFE field. */
+#define UART_RD_PFIFO_TXFE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_TXFE_MASK) >> UART_PFIFO_TXFE_SHIFT)
+#define UART_BRD_PFIFO_TXFE(base) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_TXFE_SHIFT))
+
+/*! @brief Set the TXFE field to a new value. */
+#define UART_WR_PFIFO_TXFE(base, value) (UART_RMW_PFIFO(base, UART_PFIFO_TXFE_MASK, UART_PFIFO_TXFE(value)))
+#define UART_BWR_PFIFO_TXFE(base, value) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_TXFE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_CFIFO - UART FIFO Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_CFIFO - UART FIFO Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to program various control fields for FIFO
+ * operation. This register may be read or written at any time. Note that
+ * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
+ * to prevent unintended/unpredictable behavior. Therefore, it is recommended that
+ * TE and RE be cleared prior to flushing the corresponding FIFO.
+ */
+/*!
+ * @name Constants and macros for entire UART_CFIFO register
+ */
+/*@{*/
+#define UART_RD_CFIFO(base)      (UART_CFIFO_REG(base))
+#define UART_WR_CFIFO(base, value) (UART_CFIFO_REG(base) = (value))
+#define UART_RMW_CFIFO(base, mask, value) (UART_WR_CFIFO(base, (UART_RD_CFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) |  (value)))
+#define UART_CLR_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) & ~(value)))
+#define UART_TOG_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_CFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_CFIFO, field RXUFE[0] (RW)
+ *
+ * When this field is set, the RXUF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - RXUF flag does not generate an interrupt to the host.
+ * - 0b1 - RXUF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_RXUFE field. */
+#define UART_RD_CFIFO_RXUFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_RXUFE_MASK) >> UART_CFIFO_RXUFE_SHIFT)
+#define UART_BRD_CFIFO_RXUFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXUFE_SHIFT))
+
+/*! @brief Set the RXUFE field to a new value. */
+#define UART_WR_CFIFO_RXUFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXUFE_MASK, UART_CFIFO_RXUFE(value)))
+#define UART_BWR_CFIFO_RXUFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXUFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field TXOFE[1] (RW)
+ *
+ * When this field is set, the TXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - TXOF flag does not generate an interrupt to the host.
+ * - 0b1 - TXOF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_TXOFE field. */
+#define UART_RD_CFIFO_TXOFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_TXOFE_MASK) >> UART_CFIFO_TXOFE_SHIFT)
+#define UART_BRD_CFIFO_TXOFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXOFE_SHIFT))
+
+/*! @brief Set the TXOFE field to a new value. */
+#define UART_WR_CFIFO_TXOFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_TXOFE_MASK, UART_CFIFO_TXOFE(value)))
+#define UART_BWR_CFIFO_TXOFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXOFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field RXOFE[2] (RW)
+ *
+ * When this field is set, the RXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - RXOF flag does not generate an interrupt to the host.
+ * - 0b1 - RXOF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_RXOFE field. */
+#define UART_RD_CFIFO_RXOFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_RXOFE_MASK) >> UART_CFIFO_RXOFE_SHIFT)
+#define UART_BRD_CFIFO_RXOFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXOFE_SHIFT))
+
+/*! @brief Set the RXOFE field to a new value. */
+#define UART_WR_CFIFO_RXOFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXOFE_MASK, UART_CFIFO_RXOFE(value)))
+#define UART_BWR_CFIFO_RXOFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXOFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the receive
+ * FIFO/buffer to be flushed. This does not affect data that is in the receive shift
+ * register.
+ *
+ * Values:
+ * - 0b0 - No flush operation occurs.
+ * - 0b1 - All data in the receive FIFO/buffer is cleared out.
+ */
+/*@{*/
+/*! @brief Set the RXFLUSH field to a new value. */
+#define UART_WR_CFIFO_RXFLUSH(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXFLUSH_MASK, UART_CFIFO_RXFLUSH(value)))
+#define UART_BWR_CFIFO_RXFLUSH(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXFLUSH_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the transmit
+ * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
+ * register.
+ *
+ * Values:
+ * - 0b0 - No flush operation occurs.
+ * - 0b1 - All data in the transmit FIFO/Buffer is cleared out.
+ */
+/*@{*/
+/*! @brief Set the TXFLUSH field to a new value. */
+#define UART_WR_CFIFO_TXFLUSH(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_TXFLUSH_MASK, UART_CFIFO_TXFLUSH(value)))
+#define UART_BWR_CFIFO_TXFLUSH(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXFLUSH_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_SFIFO - UART FIFO Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_SFIFO - UART FIFO Status Register (RW)
+ *
+ * Reset value: 0xC0U
+ *
+ * This register provides status information regarding the transmit and receiver
+ * buffers/FIFOs, including interrupt information. This register may be written
+ * to or read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_SFIFO register
+ */
+/*@{*/
+#define UART_RD_SFIFO(base)      (UART_SFIFO_REG(base))
+#define UART_WR_SFIFO(base, value) (UART_SFIFO_REG(base) = (value))
+#define UART_RMW_SFIFO(base, mask, value) (UART_WR_SFIFO(base, (UART_RD_SFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) |  (value)))
+#define UART_CLR_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) & ~(value)))
+#define UART_TOG_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_SFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_SFIFO, field RXUF[0] (W1C)
+ *
+ * Indicates that more data has been read from the receive buffer than was
+ * present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No receive buffer underflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one receive buffer underflow has occurred since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXUF field. */
+#define UART_RD_SFIFO_RXUF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXUF_MASK) >> UART_SFIFO_RXUF_SHIFT)
+#define UART_BRD_SFIFO_RXUF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXUF_SHIFT))
+
+/*! @brief Set the RXUF field to a new value. */
+#define UART_WR_SFIFO_RXUF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_RXUF_MASK | UART_SFIFO_TXOF_MASK | UART_SFIFO_RXOF_MASK), UART_SFIFO_RXUF(value)))
+#define UART_BWR_SFIFO_RXUF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field TXOF[1] (W1C)
+ *
+ * Indicates that more data has been written to the transmit buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
+ * flag is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No transmit buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one transmit buffer overflow has occurred since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_TXOF field. */
+#define UART_RD_SFIFO_TXOF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_TXOF_MASK) >> UART_SFIFO_TXOF_SHIFT)
+#define UART_BRD_SFIFO_TXOF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXOF_SHIFT))
+
+/*! @brief Set the TXOF field to a new value. */
+#define UART_WR_SFIFO_TXOF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_TXOF_MASK | UART_SFIFO_RXUF_MASK | UART_SFIFO_RXOF_MASK), UART_SFIFO_TXOF(value)))
+#define UART_BWR_SFIFO_TXOF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field RXOF[2] (W1C)
+ *
+ * Indicates that more data has been written to the receive buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No receive buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one receive buffer overflow has occurred since the last time
+ *     the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXOF field. */
+#define UART_RD_SFIFO_RXOF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXOF_MASK) >> UART_SFIFO_RXOF_SHIFT)
+#define UART_BRD_SFIFO_RXOF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXOF_SHIFT))
+
+/*! @brief Set the RXOF field to a new value. */
+#define UART_WR_SFIFO_RXOF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_RXOF_MASK | UART_SFIFO_RXUF_MASK | UART_SFIFO_TXOF_MASK), UART_SFIFO_RXOF(value)))
+#define UART_BWR_SFIFO_RXOF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field RXEMPT[6] (RO)
+ *
+ * Asserts when there is no data in the receive FIFO/Buffer. This field does not
+ * take into account data that is in the receive shift register.
+ *
+ * Values:
+ * - 0b0 - Receive buffer is not empty.
+ * - 0b1 - Receive buffer is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXEMPT field. */
+#define UART_RD_SFIFO_RXEMPT(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXEMPT_MASK) >> UART_SFIFO_RXEMPT_SHIFT)
+#define UART_BRD_SFIFO_RXEMPT(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXEMPT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field TXEMPT[7] (RO)
+ *
+ * Asserts when there is no data in the Transmit FIFO/buffer. This field does
+ * not take into account data that is in the transmit shift register.
+ *
+ * Values:
+ * - 0b0 - Transmit buffer is not empty.
+ * - 0b1 - Transmit buffer is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_TXEMPT field. */
+#define UART_RD_SFIFO_TXEMPT(base) ((UART_SFIFO_REG(base) & UART_SFIFO_TXEMPT_MASK) >> UART_SFIFO_TXEMPT_SHIFT)
+#define UART_BRD_SFIFO_TXEMPT(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXEMPT_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TWFIFO - UART FIFO Transmit Watermark
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TWFIFO - UART FIFO Transmit Watermark (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of needing additional transmit data. This register may be read at any
+ * time but must be written only when C2[TE] is not set. Changing the value of the
+ * watermark will not clear the S1[TDRE] flag.
+ */
+/*!
+ * @name Constants and macros for entire UART_TWFIFO register
+ */
+/*@{*/
+#define UART_RD_TWFIFO(base)     (UART_TWFIFO_REG(base))
+#define UART_WR_TWFIFO(base, value) (UART_TWFIFO_REG(base) = (value))
+#define UART_RMW_TWFIFO(base, mask, value) (UART_WR_TWFIFO(base, (UART_RD_TWFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) |  (value)))
+#define UART_CLR_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) & ~(value)))
+#define UART_TOG_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TCFIFO - UART FIFO Transmit Count
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TCFIFO - UART FIFO Transmit Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the transmit buffer/FIFO. It may be read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_TCFIFO register
+ */
+/*@{*/
+#define UART_RD_TCFIFO(base)     (UART_TCFIFO_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * UART_RWFIFO - UART FIFO Receive Watermark
+ ******************************************************************************/
+
+/*!
+ * @brief UART_RWFIFO - UART FIFO Receive Watermark (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of the need to remove data from the receiver FIFO/buffer. This register
+ * may be read at any time but must be written only when C2[RE] is not asserted.
+ * Changing the value in this register will not clear S1[RDRF].
+ */
+/*!
+ * @name Constants and macros for entire UART_RWFIFO register
+ */
+/*@{*/
+#define UART_RD_RWFIFO(base)     (UART_RWFIFO_REG(base))
+#define UART_WR_RWFIFO(base, value) (UART_RWFIFO_REG(base) = (value))
+#define UART_RMW_RWFIFO(base, mask, value) (UART_WR_RWFIFO(base, (UART_RD_RWFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) |  (value)))
+#define UART_CLR_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) & ~(value)))
+#define UART_TOG_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_RCFIFO - UART FIFO Receive Count
+ ******************************************************************************/
+
+/*!
+ * @brief UART_RCFIFO - UART FIFO Receive Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the receive FIFO/buffer. It may be read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_RCFIFO register
+ */
+/*@{*/
+#define UART_RD_RCFIFO(base)     (UART_RCFIFO_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C7816 - UART 7816 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C7816 - UART 7816 Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The C7816 register is the primary control register for ISO-7816 specific
+ * functionality. This register is specific to 7816 functionality and the values in
+ * this register have no effect on UART operation and should be ignored if
+ * ISO_7816E is not set/enabled. This register may be read at any time but values must
+ * be changed only when ISO_7816E is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_C7816 register
+ */
+/*@{*/
+#define UART_RD_C7816(base)      (UART_C7816_REG(base))
+#define UART_WR_C7816(base, value) (UART_C7816_REG(base) = (value))
+#define UART_RMW_C7816(base, mask, value) (UART_WR_C7816(base, (UART_RD_C7816(base) & ~(mask)) | (value)))
+#define UART_SET_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) |  (value)))
+#define UART_CLR_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) & ~(value)))
+#define UART_TOG_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C7816 bitfields
+ */
+
+/*!
+ * @name Register UART_C7816, field ISO_7816E[0] (RW)
+ *
+ * Indicates that the UART is operating according to the ISO-7816 protocol. This
+ * field must be modified only when no transmit or receive is occurring. If this
+ * field is changed during a data transfer, the data being transmitted or
+ * received may be transferred incorrectly.
+ *
+ * Values:
+ * - 0b0 - ISO-7816 functionality is turned off/not enabled.
+ * - 0b1 - ISO-7816 functionality is turned on/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ISO_7816E field. */
+#define UART_RD_C7816_ISO_7816E(base) ((UART_C7816_REG(base) & UART_C7816_ISO_7816E_MASK) >> UART_C7816_ISO_7816E_SHIFT)
+#define UART_BRD_C7816_ISO_7816E(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT))
+
+/*! @brief Set the ISO_7816E field to a new value. */
+#define UART_WR_C7816_ISO_7816E(base, value) (UART_RMW_C7816(base, UART_C7816_ISO_7816E_MASK, UART_C7816_ISO_7816E(value)))
+#define UART_BWR_C7816_ISO_7816E(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field TTYPE[1] (RW)
+ *
+ * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
+ * for more details.
+ *
+ * Values:
+ * - 0b0 - T = 0 per the ISO-7816 specification.
+ * - 0b1 - T = 1 per the ISO-7816 specification.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_TTYPE field. */
+#define UART_RD_C7816_TTYPE(base) ((UART_C7816_REG(base) & UART_C7816_TTYPE_MASK) >> UART_C7816_TTYPE_SHIFT)
+#define UART_BRD_C7816_TTYPE(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT))
+
+/*! @brief Set the TTYPE field to a new value. */
+#define UART_WR_C7816_TTYPE(base, value) (UART_RMW_C7816(base, UART_C7816_TTYPE_MASK, UART_C7816_TTYPE(value)))
+#define UART_BWR_C7816_TTYPE(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field INIT[2] (RW)
+ *
+ * When this field is set, all received characters are searched for a valid
+ * initial character. If an invalid initial character is identified, and ANACK is
+ * set, a NACK is sent. All received data is discarded and error flags blocked
+ * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
+ * until a valid initial character is detected. Upon detecting a valid initial
+ * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
+ * automatically updated to reflect the initial character that was received. The
+ * actual INIT data value is not stored in the receive buffer. Additionally, upon
+ * detection of a valid initial character, IS7816[INITD] is set and an interrupt
+ * issued as programmed by IE7816[INITDE]. When a valid initial character is
+ * detected, INIT is automatically cleared. This Initial Character Detect feature is
+ * supported only in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0b0 - Normal operating mode. Receiver does not seek to identify initial
+ *     character.
+ * - 0b1 - Receiver searches for initial character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_INIT field. */
+#define UART_RD_C7816_INIT(base) ((UART_C7816_REG(base) & UART_C7816_INIT_MASK) >> UART_C7816_INIT_SHIFT)
+#define UART_BRD_C7816_INIT(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT))
+
+/*! @brief Set the INIT field to a new value. */
+#define UART_WR_C7816_INIT(base, value) (UART_RMW_C7816(base, UART_C7816_INIT_MASK, UART_C7816_INIT(value)))
+#define UART_BWR_C7816_INIT(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ANACK[3] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a parity error occurs or if INIT is set and an invalid initial character is
+ * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
+ * attempts to retransmit the data indefinitely. To stop retransmission attempts,
+ * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
+ *
+ * Values:
+ * - 0b0 - No NACK is automatically generated.
+ * - 0b1 - A NACK is automatically generated if a parity error is detected or if
+ *     an invalid initial character is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ANACK field. */
+#define UART_RD_C7816_ANACK(base) ((UART_C7816_REG(base) & UART_C7816_ANACK_MASK) >> UART_C7816_ANACK_SHIFT)
+#define UART_BRD_C7816_ANACK(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT))
+
+/*! @brief Set the ANACK field to a new value. */
+#define UART_WR_C7816_ANACK(base, value) (UART_RMW_C7816(base, UART_C7816_ANACK_MASK, UART_C7816_ANACK(value)))
+#define UART_BWR_C7816_ANACK(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ONACK[4] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
+ * this results in the transmitter resending the packet that overflowed until the
+ * retransmit threshold for that transmitter is reached. A NACK is generated only
+ * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
+ * considerations
+ *
+ * Values:
+ * - 0b0 - The received data does not generate a NACK when the receipt of the
+ *     data results in an overflow event.
+ * - 0b1 - If the receiver buffer overflows, a NACK is automatically sent on a
+ *     received character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ONACK field. */
+#define UART_RD_C7816_ONACK(base) ((UART_C7816_REG(base) & UART_C7816_ONACK_MASK) >> UART_C7816_ONACK_SHIFT)
+#define UART_BRD_C7816_ONACK(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT))
+
+/*! @brief Set the ONACK field to a new value. */
+#define UART_WR_C7816_ONACK(base, value) (UART_RMW_C7816(base, UART_C7816_ONACK_MASK, UART_C7816_ONACK(value)))
+#define UART_BWR_C7816_ONACK(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IE7816 - UART 7816 Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IE7816 register controls which flags result in an interrupt being issued.
+ * This register is specific to 7816 functionality, the corresponding flags that
+ * drive the interrupts are not asserted when 7816E is not set/enabled. However,
+ * these flags may remain set if they are asserted while 7816E was set and not
+ * subsequently cleared. This register may be read or written to at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_IE7816 register
+ */
+/*@{*/
+#define UART_RD_IE7816(base)     (UART_IE7816_REG(base))
+#define UART_WR_IE7816(base, value) (UART_IE7816_REG(base) = (value))
+#define UART_RMW_IE7816(base, mask, value) (UART_WR_IE7816(base, (UART_RD_IE7816(base) & ~(mask)) | (value)))
+#define UART_SET_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) |  (value)))
+#define UART_CLR_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) & ~(value)))
+#define UART_TOG_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IE7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IE7816, field RXTE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[RXT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[RXT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_RXTE field. */
+#define UART_RD_IE7816_RXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_RXTE_MASK) >> UART_IE7816_RXTE_SHIFT)
+#define UART_BRD_IE7816_RXTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT))
+
+/*! @brief Set the RXTE field to a new value. */
+#define UART_WR_IE7816_RXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_RXTE_MASK, UART_IE7816_RXTE(value)))
+#define UART_BWR_IE7816_RXTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field TXTE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[TXT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[TXT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_TXTE field. */
+#define UART_RD_IE7816_TXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_TXTE_MASK) >> UART_IE7816_TXTE_SHIFT)
+#define UART_BRD_IE7816_TXTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT))
+
+/*! @brief Set the TXTE field to a new value. */
+#define UART_WR_IE7816_TXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_TXTE_MASK, UART_IE7816_TXTE(value)))
+#define UART_BWR_IE7816_TXTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field GTVE[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[GTV] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[GTV] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_GTVE field. */
+#define UART_RD_IE7816_GTVE(base) ((UART_IE7816_REG(base) & UART_IE7816_GTVE_MASK) >> UART_IE7816_GTVE_SHIFT)
+#define UART_BRD_IE7816_GTVE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT))
+
+/*! @brief Set the GTVE field to a new value. */
+#define UART_WR_IE7816_GTVE(base, value) (UART_RMW_IE7816(base, UART_IE7816_GTVE_MASK, UART_IE7816_GTVE(value)))
+#define UART_BWR_IE7816_GTVE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field INITDE[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[INITD] does not result in the generation of
+ *     an interrupt.
+ * - 0b1 - The assertion of IS7816[INITD] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_INITDE field. */
+#define UART_RD_IE7816_INITDE(base) ((UART_IE7816_REG(base) & UART_IE7816_INITDE_MASK) >> UART_IE7816_INITDE_SHIFT)
+#define UART_BRD_IE7816_INITDE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT))
+
+/*! @brief Set the INITDE field to a new value. */
+#define UART_WR_IE7816_INITDE(base, value) (UART_RMW_IE7816(base, UART_IE7816_INITDE_MASK, UART_IE7816_INITDE(value)))
+#define UART_BWR_IE7816_INITDE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field BWTE[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[BWT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[BWT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_BWTE field. */
+#define UART_RD_IE7816_BWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_BWTE_MASK) >> UART_IE7816_BWTE_SHIFT)
+#define UART_BRD_IE7816_BWTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT))
+
+/*! @brief Set the BWTE field to a new value. */
+#define UART_WR_IE7816_BWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_BWTE_MASK, UART_IE7816_BWTE(value)))
+#define UART_BWR_IE7816_BWTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field CWTE[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[CWT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[CWT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_CWTE field. */
+#define UART_RD_IE7816_CWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_CWTE_MASK) >> UART_IE7816_CWTE_SHIFT)
+#define UART_BRD_IE7816_CWTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT))
+
+/*! @brief Set the CWTE field to a new value. */
+#define UART_WR_IE7816_CWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_CWTE_MASK, UART_IE7816_CWTE(value)))
+#define UART_BWR_IE7816_CWTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field WTE[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[WT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[WT] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_WTE field. */
+#define UART_RD_IE7816_WTE(base) ((UART_IE7816_REG(base) & UART_IE7816_WTE_MASK) >> UART_IE7816_WTE_SHIFT)
+#define UART_BRD_IE7816_WTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT))
+
+/*! @brief Set the WTE field to a new value. */
+#define UART_WR_IE7816_WTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_WTE_MASK, UART_IE7816_WTE(value)))
+#define UART_BWR_IE7816_WTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IS7816 - UART 7816 Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IS7816 - UART 7816 Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IS7816 register provides a mechanism to read and clear the interrupt
+ * flags. All flags/interrupts are cleared by writing a 1 to the field location.
+ * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
+ * the flag condition that occurred since the last time the bit was cleared, not
+ * that the condition currently exists. The status flags are set regardless of
+ * whether the corresponding field in the IE7816 is set or cleared. The IE7816
+ * controls only if an interrupt is issued to the host processor. This register is
+ * specific to 7816 functionality and the values in this register have no affect on
+ * UART operation and should be ignored if 7816E is not set/enabled. This
+ * register may be read or written at anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_IS7816 register
+ */
+/*@{*/
+#define UART_RD_IS7816(base)     (UART_IS7816_REG(base))
+#define UART_WR_IS7816(base, value) (UART_IS7816_REG(base) = (value))
+#define UART_RMW_IS7816(base, mask, value) (UART_WR_IS7816(base, (UART_RD_IS7816(base) & ~(mask)) | (value)))
+#define UART_SET_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) |  (value)))
+#define UART_CLR_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) & ~(value)))
+#define UART_TOG_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IS7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IS7816, field RXT[0] (W1C)
+ *
+ * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
+ * generated in response to parity errors on received data. This flag requires ANACK
+ * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
+ * Clearing this field also resets the counter keeping track of consecutive NACKS. The
+ * UART will continue to attempt to receive data regardless of whether this flag
+ * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
+ * or packet is received without needing to issue a NACK, the internal NACK
+ * detection counter is cleared and the count restarts from zero on the next
+ * transmitted NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - The number of consecutive NACKS generated as a result of parity
+ *     errors and buffer overruns is less than or equal to the value in
+ *     ET7816[RXTHRESHOLD].
+ * - 0b1 - The number of consecutive NACKS generated as a result of parity
+ *     errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_RXT field. */
+#define UART_RD_IS7816_RXT(base) ((UART_IS7816_REG(base) & UART_IS7816_RXT_MASK) >> UART_IS7816_RXT_SHIFT)
+#define UART_BRD_IS7816_RXT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT))
+
+/*! @brief Set the RXT field to a new value. */
+#define UART_WR_IS7816_RXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_RXT(value)))
+#define UART_BWR_IS7816_RXT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field TXT[1] (W1C)
+ *
+ * Indicates that the transmit NACK threshold has been exceeded as indicated by
+ * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
+ * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
+ * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
+ * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
+ * internal NACK detection counter is cleared and the count restarts from zero on
+ * the next received NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - The number of retries and corresponding NACKS does not exceed the
+ *     value in ET7816[TXTHRESHOLD].
+ * - 0b1 - The number of retries and corresponding NACKS exceeds the value in
+ *     ET7816[TXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_TXT field. */
+#define UART_RD_IS7816_TXT(base) ((UART_IS7816_REG(base) & UART_IS7816_TXT_MASK) >> UART_IS7816_TXT_SHIFT)
+#define UART_BRD_IS7816_TXT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT))
+
+/*! @brief Set the TXT field to a new value. */
+#define UART_WR_IS7816_TXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_TXT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_TXT(value)))
+#define UART_BWR_IS7816_TXT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field GTV[2] (W1C)
+ *
+ * Indicates that one or more of the character guard time, block guard time, or
+ * guard time are violated. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - A guard time (GT, CGT, or BGT) has not been violated.
+ * - 0b1 - A guard time (GT, CGT, or BGT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_GTV field. */
+#define UART_RD_IS7816_GTV(base) ((UART_IS7816_REG(base) & UART_IS7816_GTV_MASK) >> UART_IS7816_GTV_SHIFT)
+#define UART_BRD_IS7816_GTV(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT))
+
+/*! @brief Set the GTV field to a new value. */
+#define UART_WR_IS7816_GTV(base, value) (UART_RMW_IS7816(base, (UART_IS7816_GTV_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_GTV(value)))
+#define UART_BWR_IS7816_GTV(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field INITD[4] (W1C)
+ *
+ * Indicates that a valid initial character is received. This interrupt is
+ * cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - A valid initial character has not been received.
+ * - 0b1 - A valid initial character has been received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_INITD field. */
+#define UART_RD_IS7816_INITD(base) ((UART_IS7816_REG(base) & UART_IS7816_INITD_MASK) >> UART_IS7816_INITD_SHIFT)
+#define UART_BRD_IS7816_INITD(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT))
+
+/*! @brief Set the INITD field to a new value. */
+#define UART_WR_IS7816_INITD(base, value) (UART_RMW_IS7816(base, (UART_IS7816_INITD_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_INITD(value)))
+#define UART_BWR_IS7816_INITD(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field BWT[5] (W1C)
+ *
+ * Indicates that the block wait time, the time between the leading edge of
+ * first received character of a block and the leading edge of the last character the
+ * previously transmitted block, has exceeded the programmed value. This flag
+ * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - Block wait time (BWT) has not been violated.
+ * - 0b1 - Block wait time (BWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_BWT field. */
+#define UART_RD_IS7816_BWT(base) ((UART_IS7816_REG(base) & UART_IS7816_BWT_MASK) >> UART_IS7816_BWT_SHIFT)
+#define UART_BRD_IS7816_BWT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT))
+
+/*! @brief Set the BWT field to a new value. */
+#define UART_WR_IS7816_BWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_BWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_BWT(value)))
+#define UART_BWR_IS7816_BWT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field CWT[6] (W1C)
+ *
+ * Indicates that the character wait time, the time between the leading edges of
+ * two consecutive characters in a block, has exceeded the programmed value.
+ * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
+ * writing 1.
+ *
+ * Values:
+ * - 0b0 - Character wait time (CWT) has not been violated.
+ * - 0b1 - Character wait time (CWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_CWT field. */
+#define UART_RD_IS7816_CWT(base) ((UART_IS7816_REG(base) & UART_IS7816_CWT_MASK) >> UART_IS7816_CWT_SHIFT)
+#define UART_BRD_IS7816_CWT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT))
+
+/*! @brief Set the CWT field to a new value. */
+#define UART_WR_IS7816_CWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_CWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_CWT(value)))
+#define UART_BWR_IS7816_CWT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field WT[7] (W1C)
+ *
+ * Indicates that the wait time, the time between the leading edge of a
+ * character being transmitted and the leading edge of the next response character, has
+ * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
+ * This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - Wait time (WT) has not been violated.
+ * - 0b1 - Wait time (WT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_WT field. */
+#define UART_RD_IS7816_WT(base) ((UART_IS7816_REG(base) & UART_IS7816_WT_MASK) >> UART_IS7816_WT_SHIFT)
+#define UART_BRD_IS7816_WT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT))
+
+/*! @brief Set the WT field to a new value. */
+#define UART_WR_IS7816_WT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_WT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK), UART_IS7816_WT(value)))
+#define UART_BWR_IS7816_WT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816T0 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816T0 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816T0 register
+ */
+/*@{*/
+#define UART_RD_WP7816T0(base)   (UART_WP7816T0_REG(base))
+#define UART_WR_WP7816T0(base, value) (UART_WP7816T0_REG(base) = (value))
+#define UART_RMW_WP7816T0(base, mask, value) (UART_WR_WP7816T0(base, (UART_RD_WP7816T0(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) |  (value)))
+#define UART_CLR_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) & ~(value)))
+#define UART_TOG_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816T1 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816T1 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816T1 register
+ */
+/*@{*/
+#define UART_RD_WP7816T1(base)   (UART_WP7816T1_REG(base))
+#define UART_WR_WP7816T1(base, value) (UART_WP7816T1_REG(base) = (value))
+#define UART_RMW_WP7816T1(base, mask, value) (UART_WR_WP7816T1(base, (UART_RD_WP7816T1(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) |  (value)))
+#define UART_CLR_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) & ~(value)))
+#define UART_TOG_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_WP7816T1 bitfields
+ */
+
+/*!
+ * @name Register UART_WP7816T1, field BWI[3:0] (RW)
+ *
+ * Used to calculate the value used for the BWT counter. It represent a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816T1_BWI field. */
+#define UART_RD_WP7816T1_BWI(base) ((UART_WP7816T1_REG(base) & UART_WP7816T1_BWI_MASK) >> UART_WP7816T1_BWI_SHIFT)
+#define UART_BRD_WP7816T1_BWI(base) (UART_RD_WP7816T1_BWI(base))
+
+/*! @brief Set the BWI field to a new value. */
+#define UART_WR_WP7816T1_BWI(base, value) (UART_RMW_WP7816T1(base, UART_WP7816T1_BWI_MASK, UART_WP7816T1_BWI(value)))
+#define UART_BWR_WP7816T1_BWI(base, value) (UART_WR_WP7816T1_BWI(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_WP7816T1, field CWI[7:4] (RW)
+ *
+ * Used to calculate the value used for the CWT counter. It represents a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816T1_CWI field. */
+#define UART_RD_WP7816T1_CWI(base) ((UART_WP7816T1_REG(base) & UART_WP7816T1_CWI_MASK) >> UART_WP7816T1_CWI_SHIFT)
+#define UART_BRD_WP7816T1_CWI(base) (UART_RD_WP7816T1_CWI(base))
+
+/*! @brief Set the CWI field to a new value. */
+#define UART_WR_WP7816T1_CWI(base, value) (UART_RMW_WP7816T1(base, UART_WP7816T1_CWI_MASK, UART_WP7816T1_CWI(value)))
+#define UART_BWR_WP7816T1_CWI(base, value) (UART_WR_WP7816T1_CWI(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WN7816 - UART 7816 Wait N Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WN7816 - UART 7816 Wait N Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The WN7816 register contains a parameter that is used in the calculation of
+ * the guard time counter. This register may be read at any time. This register
+ * must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WN7816 register
+ */
+/*@{*/
+#define UART_RD_WN7816(base)     (UART_WN7816_REG(base))
+#define UART_WR_WN7816(base, value) (UART_WN7816_REG(base) = (value))
+#define UART_RMW_WN7816(base, mask, value) (UART_WR_WN7816(base, (UART_RD_WN7816(base) & ~(mask)) | (value)))
+#define UART_SET_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) |  (value)))
+#define UART_CLR_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) & ~(value)))
+#define UART_TOG_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WF7816 - UART 7816 Wait FD Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WF7816 - UART 7816 Wait FD Register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * The WF7816 contains parameters that are used in the generation of various
+ * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WF7816 register
+ */
+/*@{*/
+#define UART_RD_WF7816(base)     (UART_WF7816_REG(base))
+#define UART_WR_WF7816(base, value) (UART_WF7816_REG(base) = (value))
+#define UART_RMW_WF7816(base, mask, value) (UART_WR_WF7816(base, (UART_RD_WF7816(base) & ~(mask)) | (value)))
+#define UART_SET_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) |  (value)))
+#define UART_CLR_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) & ~(value)))
+#define UART_TOG_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ET7816 - UART 7816 Error Threshold Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ET7816 - UART 7816 Error Threshold Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The ET7816 register contains fields that determine the number of NACKs that
+ * must be received or transmitted before the host processor is notified. This
+ * register may be read at anytime. This register must be written to only when
+ * C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_ET7816 register
+ */
+/*@{*/
+#define UART_RD_ET7816(base)     (UART_ET7816_REG(base))
+#define UART_WR_ET7816(base, value) (UART_ET7816_REG(base) = (value))
+#define UART_RMW_ET7816(base, mask, value) (UART_WR_ET7816(base, (UART_RD_ET7816(base) & ~(mask)) | (value)))
+#define UART_SET_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) |  (value)))
+#define UART_CLR_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) & ~(value)))
+#define UART_TOG_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ET7816 bitfields
+ */
+
+/*!
+ * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
+ *
+ * The value written to this field indicates the maximum number of consecutive
+ * NACKs generated as a result of a parity error or receiver buffer overruns
+ * before the host processor is notified. After the counter exceeds that value in the
+ * field, the IS7816[RXT] is asserted. This field is meaningful only when
+ * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
+ * NACKs that have been transmitted since the last successful reception. This
+ * counter saturates at 4'hF and does not wrap around. Regardless of the number of
+ * NACKs sent, the UART continues to receive valid packets indefinitely. For
+ * additional information, see IS7816[RXT] field description.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */
+#define UART_RD_ET7816_RXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_RXTHRESHOLD_MASK) >> UART_ET7816_RXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_RXTHRESHOLD(base) (UART_RD_ET7816_RXTHRESHOLD(base))
+
+/*! @brief Set the RXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_RXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_RXTHRESHOLD_MASK, UART_ET7816_RXTHRESHOLD(value)))
+#define UART_BWR_ET7816_RXTHRESHOLD(base, value) (UART_WR_ET7816_RXTHRESHOLD(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
+ *
+ * The value written to this field indicates the maximum number of failed
+ * attempts (NACKs) a transmitted character can have before the host processor is
+ * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
+ * The value read from this field represents the number of consecutive NACKs
+ * that have been received since the last successful transmission. This counter
+ * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
+ * received, the UART continues to retransmit indefinitely. This flag only
+ * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
+ * description.
+ *
+ * Values:
+ * - 0b0000 - TXT asserts on the first NACK that is received.
+ * - 0b0001 - TXT asserts on the second NACK that is received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */
+#define UART_RD_ET7816_TXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_TXTHRESHOLD_MASK) >> UART_ET7816_TXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_TXTHRESHOLD(base) (UART_RD_ET7816_TXTHRESHOLD(base))
+
+/*! @brief Set the TXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_TXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_TXTHRESHOLD_MASK, UART_ET7816_TXTHRESHOLD(value)))
+#define UART_BWR_ET7816_TXTHRESHOLD(base, value) (UART_WR_ET7816_TXTHRESHOLD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TL7816 - UART 7816 Transmit Length Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TL7816 - UART 7816 Transmit Length Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The TL7816 register is used to indicate the number of characters contained in
+ * the block being transmitted. This register is used only when C7816[TTYPE] =
+ * 1. This register may be read at anytime. This register must be written only
+ * when C2[TE] is not enabled.
+ */
+/*!
+ * @name Constants and macros for entire UART_TL7816 register
+ */
+/*@{*/
+#define UART_RD_TL7816(base)     (UART_TL7816_REG(base))
+#define UART_WR_TL7816(base, value) (UART_TL7816_REG(base) = (value))
+#define UART_RMW_TL7816(base, mask, value) (UART_WR_TL7816(base, (UART_RD_TL7816(base) & ~(mask)) | (value)))
+#define UART_SET_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) |  (value)))
+#define UART_CLR_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) & ~(value)))
+#define UART_TOG_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 USB
+ *
+ * Universal Serial Bus, OTG Capable Controller
+ *
+ * Registers defined in this header file:
+ * - USB_PERID - Peripheral ID register
+ * - USB_IDCOMP - Peripheral ID Complement register
+ * - USB_REV - Peripheral Revision register
+ * - USB_ADDINFO - Peripheral Additional Info register
+ * - USB_OTGISTAT - OTG Interrupt Status register
+ * - USB_OTGICR - OTG Interrupt Control register
+ * - USB_OTGSTAT - OTG Status register
+ * - USB_OTGCTL - OTG Control register
+ * - USB_ISTAT - Interrupt Status register
+ * - USB_INTEN - Interrupt Enable register
+ * - USB_ERRSTAT - Error Interrupt Status register
+ * - USB_ERREN - Error Interrupt Enable register
+ * - USB_STAT - Status register
+ * - USB_CTL - Control register
+ * - USB_ADDR - Address register
+ * - USB_BDTPAGE1 - BDT Page register 1
+ * - USB_FRMNUML - Frame Number register Low
+ * - USB_FRMNUMH - Frame Number register High
+ * - USB_TOKEN - Token register
+ * - USB_SOFTHLD - SOF Threshold register
+ * - USB_BDTPAGE2 - BDT Page Register 2
+ * - USB_BDTPAGE3 - BDT Page Register 3
+ * - USB_ENDPT - Endpoint Control register
+ * - USB_USBCTRL - USB Control register
+ * - USB_OBSERVE - USB OTG Observe register
+ * - USB_CONTROL - USB OTG Control register
+ * - USB_USBTRC0 - USB Transceiver Control register 0
+ * - USB_USBFRMADJUST - Frame Adjust Register
+ * - USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ * - USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ * - USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ */
+
+#define USB_INSTANCE_COUNT (1U) /*!< Number of instances of the USB module. */
+#define USB0_IDX (0U) /*!< Instance number for USB0. */
+
+/*******************************************************************************
+ * USB_PERID - Peripheral ID register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_PERID - Peripheral ID register (RO)
+ *
+ * Reset value: 0x04U
+ *
+ * Reads back the value of 0x04. This value is defined for the USB peripheral.
+ */
+/*!
+ * @name Constants and macros for entire USB_PERID register
+ */
+/*@{*/
+#define USB_RD_PERID(base)       (USB_PERID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_PERID bitfields
+ */
+
+/*!
+ * @name Register USB_PERID, field ID[5:0] (RO)
+ *
+ * This field always reads 0x4h.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_PERID_ID field. */
+#define USB_RD_PERID_ID(base) ((USB_PERID_REG(base) & USB_PERID_ID_MASK) >> USB_PERID_ID_SHIFT)
+#define USB_BRD_PERID_ID(base) (USB_RD_PERID_ID(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_IDCOMP - Peripheral ID Complement register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_IDCOMP - Peripheral ID Complement register (RO)
+ *
+ * Reset value: 0xFBU
+ *
+ * Reads back the complement of the Peripheral ID register. For the USB
+ * peripheral, the value is 0xFB.
+ */
+/*!
+ * @name Constants and macros for entire USB_IDCOMP register
+ */
+/*@{*/
+#define USB_RD_IDCOMP(base)      (USB_IDCOMP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_IDCOMP bitfields
+ */
+
+/*!
+ * @name Register USB_IDCOMP, field NID[5:0] (RO)
+ *
+ * Ones' complement of PERID[ID]. bits.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_IDCOMP_NID field. */
+#define USB_RD_IDCOMP_NID(base) ((USB_IDCOMP_REG(base) & USB_IDCOMP_NID_MASK) >> USB_IDCOMP_NID_SHIFT)
+#define USB_BRD_IDCOMP_NID(base) (USB_RD_IDCOMP_NID(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_REV - Peripheral Revision register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_REV - Peripheral Revision register (RO)
+ *
+ * Reset value: 0x33U
+ *
+ * Contains the revision number of the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_REV register
+ */
+/*@{*/
+#define USB_RD_REV(base)         (USB_REV_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDINFO - Peripheral Additional Info register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDINFO - Peripheral Additional Info register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with
+ * the Host Enable bit.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDINFO register
+ */
+/*@{*/
+#define USB_RD_ADDINFO(base)     (USB_ADDINFO_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDINFO bitfields
+ */
+
+/*!
+ * @name Register USB_ADDINFO, field IEHOST[0] (RO)
+ *
+ * This bit is set if host mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IEHOST field. */
+#define USB_RD_ADDINFO_IEHOST(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IEHOST_MASK) >> USB_ADDINFO_IEHOST_SHIFT)
+#define USB_BRD_ADDINFO_IEHOST(base) (BITBAND_ACCESS8(&USB_ADDINFO_REG(base), USB_ADDINFO_IEHOST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_ADDINFO, field IRQNUM[7:3] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IRQNUM field. */
+#define USB_RD_ADDINFO_IRQNUM(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IRQNUM_MASK) >> USB_ADDINFO_IRQNUM_SHIFT)
+#define USB_BRD_ADDINFO_IRQNUM(base) (USB_RD_ADDINFO_IRQNUM(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGISTAT - OTG Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGISTAT - OTG Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Records changes of the ID sense and VBUS signals. Software can read this
+ * register to determine the event that triggers an interrupt. Only bits that have
+ * changed since the last software read are set. Writing a one to a bit clears the
+ * associated interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGISTAT register
+ */
+/*@{*/
+#define USB_RD_OTGISTAT(base)    (USB_OTGISTAT_REG(base))
+#define USB_WR_OTGISTAT(base, value) (USB_OTGISTAT_REG(base) = (value))
+#define USB_RMW_OTGISTAT(base, mask, value) (USB_WR_OTGISTAT(base, (USB_RD_OTGISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) |  (value)))
+#define USB_CLR_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) & ~(value)))
+#define USB_TOG_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on an A device.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field. */
+#define USB_RD_OTGISTAT_AVBUSCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_AVBUSCHG_MASK) >> USB_OTGISTAT_AVBUSCHG_SHIFT)
+#define USB_BRD_OTGISTAT_AVBUSCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_AVBUSCHG_SHIFT))
+
+/*! @brief Set the AVBUSCHG field to a new value. */
+#define USB_WR_OTGISTAT_AVBUSCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_AVBUSCHG_MASK, USB_OTGISTAT_AVBUSCHG(value)))
+#define USB_BWR_OTGISTAT_AVBUSCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_AVBUSCHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on a B device.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field. */
+#define USB_RD_OTGISTAT_B_SESS_CHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_B_SESS_CHG_MASK) >> USB_OTGISTAT_B_SESS_CHG_SHIFT)
+#define USB_BRD_OTGISTAT_B_SESS_CHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_B_SESS_CHG_SHIFT))
+
+/*! @brief Set the B_SESS_CHG field to a new value. */
+#define USB_WR_OTGISTAT_B_SESS_CHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_B_SESS_CHG_MASK, USB_OTGISTAT_B_SESS_CHG(value)))
+#define USB_BWR_OTGISTAT_B_SESS_CHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_B_SESS_CHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW)
+ *
+ * This bit is set when a change in VBUS is detected indicating a session valid
+ * or a session no longer valid.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field. */
+#define USB_RD_OTGISTAT_SESSVLDCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_SESSVLDCHG_MASK) >> USB_OTGISTAT_SESSVLDCHG_SHIFT)
+#define USB_BRD_OTGISTAT_SESSVLDCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_SESSVLDCHG_SHIFT))
+
+/*! @brief Set the SESSVLDCHG field to a new value. */
+#define USB_WR_OTGISTAT_SESSVLDCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_SESSVLDCHG_MASK, USB_OTGISTAT_SESSVLDCHG(value)))
+#define USB_BWR_OTGISTAT_SESSVLDCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_SESSVLDCHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW)
+ *
+ * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits)
+ * are stable without change for 1 millisecond, and the value of the line state
+ * is different from the last time when the line state was stable. It is set on
+ * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
+ * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt
+ * can be used in detecting Reset, Resume, Connect, and Data Line Pulse
+ * signaling.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field. */
+#define USB_RD_OTGISTAT_LINE_STATE_CHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_LINE_STATE_CHG_MASK) >> USB_OTGISTAT_LINE_STATE_CHG_SHIFT)
+#define USB_BRD_OTGISTAT_LINE_STATE_CHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_LINE_STATE_CHG_SHIFT))
+
+/*! @brief Set the LINE_STATE_CHG field to a new value. */
+#define USB_WR_OTGISTAT_LINE_STATE_CHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_LINE_STATE_CHG_MASK, USB_OTGISTAT_LINE_STATE_CHG(value)))
+#define USB_BWR_OTGISTAT_LINE_STATE_CHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_LINE_STATE_CHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW)
+ *
+ * This bit is set when the 1 millisecond timer expires. This bit stays asserted
+ * until cleared by software. The interrupt must be serviced every millisecond
+ * to avoid losing 1msec counts.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_ONEMSEC field. */
+#define USB_RD_OTGISTAT_ONEMSEC(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_ONEMSEC_MASK) >> USB_OTGISTAT_ONEMSEC_SHIFT)
+#define USB_BRD_OTGISTAT_ONEMSEC(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_ONEMSEC_SHIFT))
+
+/*! @brief Set the ONEMSEC field to a new value. */
+#define USB_WR_OTGISTAT_ONEMSEC(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_ONEMSEC_MASK, USB_OTGISTAT_ONEMSEC(value)))
+#define USB_BWR_OTGISTAT_ONEMSEC(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_ONEMSEC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field IDCHG[7] (RW)
+ *
+ * This bit is set when a change in the ID Signal from the USB connector is
+ * sensed.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_IDCHG field. */
+#define USB_RD_OTGISTAT_IDCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_IDCHG_MASK) >> USB_OTGISTAT_IDCHG_SHIFT)
+#define USB_BRD_OTGISTAT_IDCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_IDCHG_SHIFT))
+
+/*! @brief Set the IDCHG field to a new value. */
+#define USB_WR_OTGISTAT_IDCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_IDCHG_MASK, USB_OTGISTAT_IDCHG(value)))
+#define USB_BWR_OTGISTAT_IDCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_IDCHG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGICR - OTG Interrupt Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGICR - OTG Interrupt Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Enables the corresponding interrupt status bits defined in the OTG Interrupt
+ * Status Register.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGICR register
+ */
+/*@{*/
+#define USB_RD_OTGICR(base)      (USB_OTGICR_REG(base))
+#define USB_WR_OTGICR(base, value) (USB_OTGICR_REG(base) = (value))
+#define USB_RMW_OTGICR(base, mask, value) (USB_WR_OTGICR(base, (USB_RD_OTGICR(base) & ~(mask)) | (value)))
+#define USB_SET_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) |  (value)))
+#define USB_CLR_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) & ~(value)))
+#define USB_TOG_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGICR bitfields
+ */
+
+/*!
+ * @name Register USB_OTGICR, field AVBUSEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the AVBUSCHG interrupt.
+ * - 0b1 - Enables the AVBUSCHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_AVBUSEN field. */
+#define USB_RD_OTGICR_AVBUSEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_AVBUSEN_MASK) >> USB_OTGICR_AVBUSEN_SHIFT)
+#define USB_BRD_OTGICR_AVBUSEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_AVBUSEN_SHIFT))
+
+/*! @brief Set the AVBUSEN field to a new value. */
+#define USB_WR_OTGICR_AVBUSEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_AVBUSEN_MASK, USB_OTGICR_AVBUSEN(value)))
+#define USB_BWR_OTGICR_AVBUSEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_AVBUSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field BSESSEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the B_SESS_CHG interrupt.
+ * - 0b1 - Enables the B_SESS_CHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_BSESSEN field. */
+#define USB_RD_OTGICR_BSESSEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_BSESSEN_MASK) >> USB_OTGICR_BSESSEN_SHIFT)
+#define USB_BRD_OTGICR_BSESSEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_BSESSEN_SHIFT))
+
+/*! @brief Set the BSESSEN field to a new value. */
+#define USB_WR_OTGICR_BSESSEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_BSESSEN_MASK, USB_OTGICR_BSESSEN(value)))
+#define USB_BWR_OTGICR_BSESSEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_BSESSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field SESSVLDEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the SESSVLDCHG interrupt.
+ * - 0b1 - Enables the SESSVLDCHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_SESSVLDEN field. */
+#define USB_RD_OTGICR_SESSVLDEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_SESSVLDEN_MASK) >> USB_OTGICR_SESSVLDEN_SHIFT)
+#define USB_BRD_OTGICR_SESSVLDEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_SESSVLDEN_SHIFT))
+
+/*! @brief Set the SESSVLDEN field to a new value. */
+#define USB_WR_OTGICR_SESSVLDEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_SESSVLDEN_MASK, USB_OTGICR_SESSVLDEN(value)))
+#define USB_BWR_OTGICR_SESSVLDEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_SESSVLDEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field LINESTATEEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the LINE_STAT_CHG interrupt.
+ * - 0b1 - Enables the LINE_STAT_CHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_LINESTATEEN field. */
+#define USB_RD_OTGICR_LINESTATEEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_LINESTATEEN_MASK) >> USB_OTGICR_LINESTATEEN_SHIFT)
+#define USB_BRD_OTGICR_LINESTATEEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_LINESTATEEN_SHIFT))
+
+/*! @brief Set the LINESTATEEN field to a new value. */
+#define USB_WR_OTGICR_LINESTATEEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_LINESTATEEN_MASK, USB_OTGICR_LINESTATEEN(value)))
+#define USB_BWR_OTGICR_LINESTATEEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_LINESTATEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field ONEMSECEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Diables the 1ms timer interrupt.
+ * - 0b1 - Enables the 1ms timer interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_ONEMSECEN field. */
+#define USB_RD_OTGICR_ONEMSECEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_ONEMSECEN_MASK) >> USB_OTGICR_ONEMSECEN_SHIFT)
+#define USB_BRD_OTGICR_ONEMSECEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_ONEMSECEN_SHIFT))
+
+/*! @brief Set the ONEMSECEN field to a new value. */
+#define USB_WR_OTGICR_ONEMSECEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_ONEMSECEN_MASK, USB_OTGICR_ONEMSECEN(value)))
+#define USB_BWR_OTGICR_ONEMSECEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_ONEMSECEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field IDEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The ID interrupt is disabled
+ * - 0b1 - The ID interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_IDEN field. */
+#define USB_RD_OTGICR_IDEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_IDEN_MASK) >> USB_OTGICR_IDEN_SHIFT)
+#define USB_BRD_OTGICR_IDEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_IDEN_SHIFT))
+
+/*! @brief Set the IDEN field to a new value. */
+#define USB_WR_OTGICR_IDEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_IDEN_MASK, USB_OTGICR_IDEN(value)))
+#define USB_BWR_OTGICR_IDEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_IDEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGSTAT - OTG Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGSTAT - OTG Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Displays the actual value from the external comparator outputs of the ID pin
+ * and VBUS.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGSTAT register
+ */
+/*@{*/
+#define USB_RD_OTGSTAT(base)     (USB_OTGSTAT_REG(base))
+#define USB_WR_OTGSTAT(base, value) (USB_OTGSTAT_REG(base) = (value))
+#define USB_RMW_OTGSTAT(base, mask, value) (USB_WR_OTGSTAT(base, (USB_RD_OTGSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) |  (value)))
+#define USB_CLR_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) & ~(value)))
+#define USB_TOG_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is below the A VBUS Valid threshold.
+ * - 0b1 - The VBUS voltage is above the A VBUS Valid threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field. */
+#define USB_RD_OTGSTAT_AVBUSVLD(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_AVBUSVLD_MASK) >> USB_OTGSTAT_AVBUSVLD_SHIFT)
+#define USB_BRD_OTGSTAT_AVBUSVLD(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_AVBUSVLD_SHIFT))
+
+/*! @brief Set the AVBUSVLD field to a new value. */
+#define USB_WR_OTGSTAT_AVBUSVLD(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_AVBUSVLD_MASK, USB_OTGSTAT_AVBUSVLD(value)))
+#define USB_BWR_OTGSTAT_AVBUSVLD(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_AVBUSVLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field BSESSEND[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is above the B session end threshold.
+ * - 0b1 - The VBUS voltage is below the B session end threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_BSESSEND field. */
+#define USB_RD_OTGSTAT_BSESSEND(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_BSESSEND_MASK) >> USB_OTGSTAT_BSESSEND_SHIFT)
+#define USB_BRD_OTGSTAT_BSESSEND(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_BSESSEND_SHIFT))
+
+/*! @brief Set the BSESSEND field to a new value. */
+#define USB_WR_OTGSTAT_BSESSEND(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_BSESSEND_MASK, USB_OTGSTAT_BSESSEND(value)))
+#define USB_BWR_OTGSTAT_BSESSEND(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_BSESSEND_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is below the B session valid threshold
+ * - 0b1 - The VBUS voltage is above the B session valid threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_SESS_VLD field. */
+#define USB_RD_OTGSTAT_SESS_VLD(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_SESS_VLD_MASK) >> USB_OTGSTAT_SESS_VLD_SHIFT)
+#define USB_BRD_OTGSTAT_SESS_VLD(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_SESS_VLD_SHIFT))
+
+/*! @brief Set the SESS_VLD field to a new value. */
+#define USB_WR_OTGSTAT_SESS_VLD(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_SESS_VLD_MASK, USB_OTGSTAT_SESS_VLD(value)))
+#define USB_BWR_OTGSTAT_SESS_VLD(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_SESS_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
+ *
+ * Indicates that the internal signals that control the LINE_STATE_CHG field of
+ * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG
+ * field and then read this field. If this field reads as 1, then the value of
+ * LINE_STATE_CHG can be considered stable.
+ *
+ * Values:
+ * - 0b0 - The LINE_STAT_CHG bit is not yet stable.
+ * - 0b1 - The LINE_STAT_CHG bit has been debounced and is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field. */
+#define USB_RD_OTGSTAT_LINESTATESTABLE(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_LINESTATESTABLE_MASK) >> USB_OTGSTAT_LINESTATESTABLE_SHIFT)
+#define USB_BRD_OTGSTAT_LINESTATESTABLE(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_LINESTATESTABLE_SHIFT))
+
+/*! @brief Set the LINESTATESTABLE field to a new value. */
+#define USB_WR_OTGSTAT_LINESTATESTABLE(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_LINESTATESTABLE_MASK, USB_OTGSTAT_LINESTATESTABLE(value)))
+#define USB_BWR_OTGSTAT_LINESTATESTABLE(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_LINESTATESTABLE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW)
+ *
+ * This bit is reserved for the 1ms count, but it is not useful to software.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field. */
+#define USB_RD_OTGSTAT_ONEMSECEN(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_ONEMSECEN_MASK) >> USB_OTGSTAT_ONEMSECEN_SHIFT)
+#define USB_BRD_OTGSTAT_ONEMSECEN(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ONEMSECEN_SHIFT))
+
+/*! @brief Set the ONEMSECEN field to a new value. */
+#define USB_WR_OTGSTAT_ONEMSECEN(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_ONEMSECEN_MASK, USB_OTGSTAT_ONEMSECEN(value)))
+#define USB_BWR_OTGSTAT_ONEMSECEN(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ONEMSECEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field ID[7] (RW)
+ *
+ * Indicates the current state of the ID pin on the USB connector
+ *
+ * Values:
+ * - 0b0 - Indicates a Type A cable is plugged into the USB connector.
+ * - 0b1 - Indicates no cable is attached or a Type B cable is plugged into the
+ *     USB connector.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_ID field. */
+#define USB_RD_OTGSTAT_ID(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_ID_MASK) >> USB_OTGSTAT_ID_SHIFT)
+#define USB_BRD_OTGSTAT_ID(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ID_SHIFT))
+
+/*! @brief Set the ID field to a new value. */
+#define USB_WR_OTGSTAT_ID(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_ID_MASK, USB_OTGSTAT_ID(value)))
+#define USB_BWR_OTGSTAT_ID(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ID_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGCTL - OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGCTL - OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Controls the operation of VBUS and Data Line termination resistors.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGCTL register
+ */
+/*@{*/
+#define USB_RD_OTGCTL(base)      (USB_OTGCTL_REG(base))
+#define USB_WR_OTGCTL(base, value) (USB_OTGCTL_REG(base) = (value))
+#define USB_RMW_OTGCTL(base, mask, value) (USB_WR_OTGCTL(base, (USB_RD_OTGCTL(base) & ~(mask)) | (value)))
+#define USB_SET_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) |  (value)))
+#define USB_CLR_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) & ~(value)))
+#define USB_TOG_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGCTL bitfields
+ */
+
+/*!
+ * @name Register USB_OTGCTL, field OTGEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then
+ *     the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+
+ *     and D- Data Line pull-down resistors are engaged.
+ * - 0b1 - The pull-up and pull-down controls in this register are used.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_OTGEN field. */
+#define USB_RD_OTGCTL_OTGEN(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_OTGEN_MASK) >> USB_OTGCTL_OTGEN_SHIFT)
+#define USB_BRD_OTGCTL_OTGEN(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_OTGEN_SHIFT))
+
+/*! @brief Set the OTGEN field to a new value. */
+#define USB_WR_OTGCTL_OTGEN(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_OTGEN_MASK, USB_OTGCTL_OTGEN(value)))
+#define USB_BWR_OTGCTL_OTGEN(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_OTGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DMLOW[4] (RW)
+ *
+ * Values:
+ * - 0b0 - D- pulldown resistor is not enabled.
+ * - 0b1 - D- pulldown resistor is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DMLOW field. */
+#define USB_RD_OTGCTL_DMLOW(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DMLOW_MASK) >> USB_OTGCTL_DMLOW_SHIFT)
+#define USB_BRD_OTGCTL_DMLOW(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DMLOW_SHIFT))
+
+/*! @brief Set the DMLOW field to a new value. */
+#define USB_WR_OTGCTL_DMLOW(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DMLOW_MASK, USB_OTGCTL_DMLOW(value)))
+#define USB_BWR_OTGCTL_DMLOW(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DMLOW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DPLOW[5] (RW)
+ *
+ * This bit should always be enabled together with bit 4 (DMLOW)
+ *
+ * Values:
+ * - 0b0 - D+ pulldown resistor is not enabled.
+ * - 0b1 - D+ pulldown resistor is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPLOW field. */
+#define USB_RD_OTGCTL_DPLOW(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPLOW_MASK) >> USB_OTGCTL_DPLOW_SHIFT)
+#define USB_BRD_OTGCTL_DPLOW(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPLOW_SHIFT))
+
+/*! @brief Set the DPLOW field to a new value. */
+#define USB_WR_OTGCTL_DPLOW(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPLOW_MASK, USB_OTGCTL_DPLOW(value)))
+#define USB_BWR_OTGCTL_DPLOW(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPLOW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DPHIGH[7] (RW)
+ *
+ * Values:
+ * - 0b0 - D+ pullup resistor is not enabled
+ * - 0b1 - D+ pullup resistor is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPHIGH field. */
+#define USB_RD_OTGCTL_DPHIGH(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPHIGH_MASK) >> USB_OTGCTL_DPHIGH_SHIFT)
+#define USB_BRD_OTGCTL_DPHIGH(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT))
+
+/*! @brief Set the DPHIGH field to a new value. */
+#define USB_WR_OTGCTL_DPHIGH(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPHIGH_MASK, USB_OTGCTL_DPHIGH(value)))
+#define USB_BWR_OTGCTL_DPHIGH(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ISTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ISTAT - Interrupt Status register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains fields for each of the interrupt sources within the USB Module. Each
+ * of these fields are qualified with their respective interrupt enable bits.
+ * All fields of this register are logically OR'd together along with the OTG
+ * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the
+ * processor's interrupt controller. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ISTAT register
+ */
+/*@{*/
+#define USB_RD_ISTAT(base)       (USB_ISTAT_REG(base))
+#define USB_WR_ISTAT(base, value) (USB_ISTAT_REG(base) = (value))
+#define USB_RMW_ISTAT(base, mask, value) (USB_WR_ISTAT(base, (USB_RD_ISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) |  (value)))
+#define USB_CLR_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) & ~(value)))
+#define USB_TOG_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ISTAT, field USBRST[0] (W1C)
+ *
+ * This bit is set when the USB Module has decoded a valid USB reset. This
+ * informs the processor that it should write 0x00 into the address register and
+ * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5
+ * microseconds. It is not asserted again until the USB reset condition has been
+ * removed and then reasserted.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_USBRST field. */
+#define USB_RD_ISTAT_USBRST(base) ((USB_ISTAT_REG(base) & USB_ISTAT_USBRST_MASK) >> USB_ISTAT_USBRST_SHIFT)
+#define USB_BRD_ISTAT_USBRST(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT))
+
+/*! @brief Set the USBRST field to a new value. */
+#define USB_WR_ISTAT_USBRST(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_USBRST(value)))
+#define USB_BWR_ISTAT_USBRST(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ERROR[1] (W1C)
+ *
+ * This bit is set when any of the error conditions within Error Interrupt
+ * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register
+ * to determine the source of the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ERROR field. */
+#define USB_RD_ISTAT_ERROR(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ERROR_MASK) >> USB_ISTAT_ERROR_SHIFT)
+#define USB_BRD_ISTAT_ERROR(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT))
+
+/*! @brief Set the ERROR field to a new value. */
+#define USB_WR_ISTAT_ERROR(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ERROR_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ERROR(value)))
+#define USB_BWR_ISTAT_ERROR(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SOFTOK[2] (W1C)
+ *
+ * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In
+ * Host mode this field is set when the SOF threshold is reached, so that
+ * software can prepare for the next SOF.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SOFTOK field. */
+#define USB_RD_ISTAT_SOFTOK(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SOFTOK_MASK) >> USB_ISTAT_SOFTOK_SHIFT)
+#define USB_BRD_ISTAT_SOFTOK(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT))
+
+/*! @brief Set the SOFTOK field to a new value. */
+#define USB_WR_ISTAT_SOFTOK(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SOFTOK_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SOFTOK(value)))
+#define USB_BWR_ISTAT_SOFTOK(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field TOKDNE[3] (W1C)
+ *
+ * This bit is set when the current token being processed has completed. The
+ * processor must immediately read the STATUS (STAT) register to determine the
+ * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes
+ * STAT to be cleared or the STAT holding register to be loaded into the STAT
+ * register.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_TOKDNE field. */
+#define USB_RD_ISTAT_TOKDNE(base) ((USB_ISTAT_REG(base) & USB_ISTAT_TOKDNE_MASK) >> USB_ISTAT_TOKDNE_SHIFT)
+#define USB_BRD_ISTAT_TOKDNE(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT))
+
+/*! @brief Set the TOKDNE field to a new value. */
+#define USB_WR_ISTAT_TOKDNE(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_TOKDNE_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_TOKDNE(value)))
+#define USB_BWR_ISTAT_TOKDNE(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SLEEP[4] (W1C)
+ *
+ * This bit is set when the USB Module detects a constant idle on the USB bus
+ * for 3 ms. The sleep timer is reset by activity on the USB bus.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SLEEP field. */
+#define USB_RD_ISTAT_SLEEP(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SLEEP_MASK) >> USB_ISTAT_SLEEP_SHIFT)
+#define USB_BRD_ISTAT_SLEEP(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define USB_WR_ISTAT_SLEEP(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SLEEP_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SLEEP(value)))
+#define USB_BWR_ISTAT_SLEEP(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field RESUME[5] (W1C)
+ *
+ * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us.
+ * When not in suspend mode this interrupt must be disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_RESUME field. */
+#define USB_RD_ISTAT_RESUME(base) ((USB_ISTAT_REG(base) & USB_ISTAT_RESUME_MASK) >> USB_ISTAT_RESUME_SHIFT)
+#define USB_BRD_ISTAT_RESUME(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_ISTAT_RESUME(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_RESUME_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_RESUME(value)))
+#define USB_BWR_ISTAT_RESUME(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ATTACH[6] (W1C)
+ *
+ * This bit is set when the USB Module detects an attach of a USB device. This
+ * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a
+ * peripheral is now present and must be configured; it is asserted if there have
+ * been no transitions on the USB for 2.5 us and the current bus state is not SE0."
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ATTACH field. */
+#define USB_RD_ISTAT_ATTACH(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ATTACH_MASK) >> USB_ISTAT_ATTACH_SHIFT)
+#define USB_BRD_ISTAT_ATTACH(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ATTACH_SHIFT))
+
+/*! @brief Set the ATTACH field to a new value. */
+#define USB_WR_ISTAT_ATTACH(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ATTACH_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ATTACH(value)))
+#define USB_BWR_ISTAT_ATTACH(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ATTACH_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field STALL[7] (W1C)
+ *
+ * In Target mode this bit is asserted when a STALL handshake is sent by the
+ * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge
+ * during the handshake phase of a USB transaction.This interrupt can be used to
+ * determine whether the last USB transaction was completed successfully or
+ * stalled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_STALL field. */
+#define USB_RD_ISTAT_STALL(base) ((USB_ISTAT_REG(base) & USB_ISTAT_STALL_MASK) >> USB_ISTAT_STALL_SHIFT)
+#define USB_BRD_ISTAT_STALL(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT))
+
+/*! @brief Set the STALL field to a new value. */
+#define USB_WR_ISTAT_STALL(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_STALL_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK), USB_ISTAT_STALL(value)))
+#define USB_BWR_ISTAT_STALL(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_INTEN - Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_INTEN - Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable fields for each of the interrupt sources within the USB
+ * Module. Setting any of these bits enables the respective interrupt source in the
+ * ISTAT register. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_INTEN register
+ */
+/*@{*/
+#define USB_RD_INTEN(base)       (USB_INTEN_REG(base))
+#define USB_WR_INTEN(base, value) (USB_INTEN_REG(base) = (value))
+#define USB_RMW_INTEN(base, mask, value) (USB_WR_INTEN(base, (USB_RD_INTEN(base) & ~(mask)) | (value)))
+#define USB_SET_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) |  (value)))
+#define USB_CLR_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) & ~(value)))
+#define USB_TOG_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_INTEN bitfields
+ */
+
+/*!
+ * @name Register USB_INTEN, field USBRSTEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the USBRST interrupt.
+ * - 0b1 - Enables the USBRST interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_USBRSTEN field. */
+#define USB_RD_INTEN_USBRSTEN(base) ((USB_INTEN_REG(base) & USB_INTEN_USBRSTEN_MASK) >> USB_INTEN_USBRSTEN_SHIFT)
+#define USB_BRD_INTEN_USBRSTEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT))
+
+/*! @brief Set the USBRSTEN field to a new value. */
+#define USB_WR_INTEN_USBRSTEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_USBRSTEN_MASK, USB_INTEN_USBRSTEN(value)))
+#define USB_BWR_INTEN_USBRSTEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ERROREN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the ERROR interrupt.
+ * - 0b1 - Enables the ERROR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ERROREN field. */
+#define USB_RD_INTEN_ERROREN(base) ((USB_INTEN_REG(base) & USB_INTEN_ERROREN_MASK) >> USB_INTEN_ERROREN_SHIFT)
+#define USB_BRD_INTEN_ERROREN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT))
+
+/*! @brief Set the ERROREN field to a new value. */
+#define USB_WR_INTEN_ERROREN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ERROREN_MASK, USB_INTEN_ERROREN(value)))
+#define USB_BWR_INTEN_ERROREN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SOFTOKEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disbles the SOFTOK interrupt.
+ * - 0b1 - Enables the SOFTOK interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SOFTOKEN field. */
+#define USB_RD_INTEN_SOFTOKEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SOFTOKEN_MASK) >> USB_INTEN_SOFTOKEN_SHIFT)
+#define USB_BRD_INTEN_SOFTOKEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT))
+
+/*! @brief Set the SOFTOKEN field to a new value. */
+#define USB_WR_INTEN_SOFTOKEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SOFTOKEN_MASK, USB_INTEN_SOFTOKEN(value)))
+#define USB_BWR_INTEN_SOFTOKEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field TOKDNEEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the TOKDNE interrupt.
+ * - 0b1 - Enables the TOKDNE interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_TOKDNEEN field. */
+#define USB_RD_INTEN_TOKDNEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_TOKDNEEN_MASK) >> USB_INTEN_TOKDNEEN_SHIFT)
+#define USB_BRD_INTEN_TOKDNEEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT))
+
+/*! @brief Set the TOKDNEEN field to a new value. */
+#define USB_WR_INTEN_TOKDNEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_TOKDNEEN_MASK, USB_INTEN_TOKDNEEN(value)))
+#define USB_BWR_INTEN_TOKDNEEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SLEEPEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the SLEEP interrupt.
+ * - 0b1 - Enables the SLEEP interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SLEEPEN field. */
+#define USB_RD_INTEN_SLEEPEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SLEEPEN_MASK) >> USB_INTEN_SLEEPEN_SHIFT)
+#define USB_BRD_INTEN_SLEEPEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT))
+
+/*! @brief Set the SLEEPEN field to a new value. */
+#define USB_WR_INTEN_SLEEPEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SLEEPEN_MASK, USB_INTEN_SLEEPEN(value)))
+#define USB_BWR_INTEN_SLEEPEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field RESUMEEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the RESUME interrupt.
+ * - 0b1 - Enables the RESUME interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_RESUMEEN field. */
+#define USB_RD_INTEN_RESUMEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_RESUMEEN_MASK) >> USB_INTEN_RESUMEEN_SHIFT)
+#define USB_BRD_INTEN_RESUMEEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT))
+
+/*! @brief Set the RESUMEEN field to a new value. */
+#define USB_WR_INTEN_RESUMEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_RESUMEEN_MASK, USB_INTEN_RESUMEEN(value)))
+#define USB_BWR_INTEN_RESUMEEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ATTACHEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the ATTACH interrupt.
+ * - 0b1 - Enables the ATTACH interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ATTACHEN field. */
+#define USB_RD_INTEN_ATTACHEN(base) ((USB_INTEN_REG(base) & USB_INTEN_ATTACHEN_MASK) >> USB_INTEN_ATTACHEN_SHIFT)
+#define USB_BRD_INTEN_ATTACHEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ATTACHEN_SHIFT))
+
+/*! @brief Set the ATTACHEN field to a new value. */
+#define USB_WR_INTEN_ATTACHEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ATTACHEN_MASK, USB_INTEN_ATTACHEN(value)))
+#define USB_BWR_INTEN_ATTACHEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ATTACHEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field STALLEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Diasbles the STALL interrupt.
+ * - 0b1 - Enables the STALL interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_STALLEN field. */
+#define USB_RD_INTEN_STALLEN(base) ((USB_INTEN_REG(base) & USB_INTEN_STALLEN_MASK) >> USB_INTEN_STALLEN_SHIFT)
+#define USB_BRD_INTEN_STALLEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT))
+
+/*! @brief Set the STALLEN field to a new value. */
+#define USB_WR_INTEN_STALLEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_STALLEN_MASK, USB_INTEN_STALLEN(value)))
+#define USB_BWR_INTEN_STALLEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERRSTAT - Error Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERRSTAT - Error Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error sources within the USB Module.
+ * Each of these bits are qualified with their respective error enable bits. All
+ * bits of this register are logically OR'd together and the result placed in the
+ * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. Each bit is set
+ * as soon as the error condition is detected. Therefore, the interrupt does not
+ * typically correspond with the end of a token being processed. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERRSTAT register
+ */
+/*@{*/
+#define USB_RD_ERRSTAT(base)     (USB_ERRSTAT_REG(base))
+#define USB_WR_ERRSTAT(base, value) (USB_ERRSTAT_REG(base) = (value))
+#define USB_RMW_ERRSTAT(base, mask, value) (USB_WR_ERRSTAT(base, (USB_RD_ERRSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) |  (value)))
+#define USB_CLR_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) & ~(value)))
+#define USB_TOG_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERRSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ERRSTAT, field PIDERR[0] (W1C)
+ *
+ * This bit is set when the PID check field fails.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_PIDERR field. */
+#define USB_RD_ERRSTAT_PIDERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_PIDERR_MASK) >> USB_ERRSTAT_PIDERR_SHIFT)
+#define USB_BRD_ERRSTAT_PIDERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT))
+
+/*! @brief Set the PIDERR field to a new value. */
+#define USB_WR_ERRSTAT_PIDERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_PIDERR(value)))
+#define USB_BWR_ERRSTAT_PIDERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C)
+ *
+ * This error interrupt has two functions. When the USB Module is operating in
+ * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token
+ * packets generated by the host. If set the token packet was rejected due to a
+ * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this
+ * interrupt detects End Of Frame (EOF) error conditions. This occurs when the
+ * USB Module is transmitting or receiving data and the SOF counter reaches zero.
+ * This interrupt is useful when developing USB packet scheduling software to
+ * ensure that no USB transactions cross the start of the next frame.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC5EOF field. */
+#define USB_RD_ERRSTAT_CRC5EOF(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC5EOF_MASK) >> USB_ERRSTAT_CRC5EOF_SHIFT)
+#define USB_BRD_ERRSTAT_CRC5EOF(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5EOF_SHIFT))
+
+/*! @brief Set the CRC5EOF field to a new value. */
+#define USB_WR_ERRSTAT_CRC5EOF(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC5EOF(value)))
+#define USB_BWR_ERRSTAT_CRC5EOF(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5EOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC16[2] (W1C)
+ *
+ * This bit is set when a data packet is rejected due to a CRC16 error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC16 field. */
+#define USB_RD_ERRSTAT_CRC16(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC16_MASK) >> USB_ERRSTAT_CRC16_SHIFT)
+#define USB_BRD_ERRSTAT_CRC16(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT))
+
+/*! @brief Set the CRC16 field to a new value. */
+#define USB_WR_ERRSTAT_CRC16(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC16(value)))
+#define USB_BWR_ERRSTAT_CRC16(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DFN8[3] (W1C)
+ *
+ * This bit is set if the data field received was not 8 bits in length. USB
+ * Specification 1.0 requires that data fields be an integral number of bytes. If the
+ * data field was not an integral number of bytes, this bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DFN8 field. */
+#define USB_RD_ERRSTAT_DFN8(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DFN8_MASK) >> USB_ERRSTAT_DFN8_SHIFT)
+#define USB_BRD_ERRSTAT_DFN8(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT))
+
+/*! @brief Set the DFN8 field to a new value. */
+#define USB_WR_ERRSTAT_DFN8(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DFN8(value)))
+#define USB_BWR_ERRSTAT_DFN8(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTOERR[4] (W1C)
+ *
+ * This bit is set when a bus turnaround timeout error occurs. The USB module
+ * contains a bus turnaround timer that keeps track of the amount of time elapsed
+ * between the token and data phases of a SETUP or OUT TOKEN or the data and
+ * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the
+ * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTOERR field. */
+#define USB_RD_ERRSTAT_BTOERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTOERR_MASK) >> USB_ERRSTAT_BTOERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTOERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT))
+
+/*! @brief Set the BTOERR field to a new value. */
+#define USB_WR_ERRSTAT_BTOERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_BTOERR(value)))
+#define USB_BWR_ERRSTAT_BTOERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DMAERR[5] (W1C)
+ *
+ * This bit is set if the USB Module has requested a DMA access to read a new
+ * BDT but has not been given the bus before it needs to receive or transmit data.
+ * If processing a TX transfer this would cause a transmit data underflow
+ * condition. If processing a RX transfer this would cause a receive data overflow
+ * condition. This interrupt is useful when developing device arbitration hardware for
+ * the microprocessor and the USB module to minimize bus request and bus grant
+ * latency. This bit is also set if a data packet to or from the host is larger
+ * than the buffer size allocated in the BDT. In this case the data packet is
+ * truncated as it is put in buffer memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DMAERR field. */
+#define USB_RD_ERRSTAT_DMAERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DMAERR_MASK) >> USB_ERRSTAT_DMAERR_SHIFT)
+#define USB_BRD_ERRSTAT_DMAERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT))
+
+/*! @brief Set the DMAERR field to a new value. */
+#define USB_WR_ERRSTAT_DMAERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DMAERR(value)))
+#define USB_BWR_ERRSTAT_DMAERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTSERR[7] (W1C)
+ *
+ * This bit is set when a bit stuff error is detected. If set, the corresponding
+ * packet is rejected due to the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTSERR field. */
+#define USB_RD_ERRSTAT_BTSERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTSERR_MASK) >> USB_ERRSTAT_BTSERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTSERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT))
+
+/*! @brief Set the BTSERR field to a new value. */
+#define USB_WR_ERRSTAT_BTSERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTSERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK), USB_ERRSTAT_BTSERR(value)))
+#define USB_BWR_ERRSTAT_BTSERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERREN - Error Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERREN - Error Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error interrupt sources within the USB
+ * module. Setting any of these bits enables the respective interrupt source in
+ * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore,
+ * the interrupt does not typically correspond with the end of a token being
+ * processed. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERREN register
+ */
+/*@{*/
+#define USB_RD_ERREN(base)       (USB_ERREN_REG(base))
+#define USB_WR_ERREN(base, value) (USB_ERREN_REG(base) = (value))
+#define USB_RMW_ERREN(base, mask, value) (USB_WR_ERREN(base, (USB_RD_ERREN(base) & ~(mask)) | (value)))
+#define USB_SET_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) |  (value)))
+#define USB_CLR_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) & ~(value)))
+#define USB_TOG_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERREN bitfields
+ */
+
+/*!
+ * @name Register USB_ERREN, field PIDERREN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the PIDERR interrupt.
+ * - 0b1 - Enters the PIDERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_PIDERREN field. */
+#define USB_RD_ERREN_PIDERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_PIDERREN_MASK) >> USB_ERREN_PIDERREN_SHIFT)
+#define USB_BRD_ERREN_PIDERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT))
+
+/*! @brief Set the PIDERREN field to a new value. */
+#define USB_WR_ERREN_PIDERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_PIDERREN_MASK, USB_ERREN_PIDERREN(value)))
+#define USB_BWR_ERREN_PIDERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC5EOFEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the CRC5/EOF interrupt.
+ * - 0b1 - Enables the CRC5/EOF interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC5EOFEN field. */
+#define USB_RD_ERREN_CRC5EOFEN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC5EOFEN_MASK) >> USB_ERREN_CRC5EOFEN_SHIFT)
+#define USB_BRD_ERREN_CRC5EOFEN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT))
+
+/*! @brief Set the CRC5EOFEN field to a new value. */
+#define USB_WR_ERREN_CRC5EOFEN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC5EOFEN_MASK, USB_ERREN_CRC5EOFEN(value)))
+#define USB_BWR_ERREN_CRC5EOFEN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC16EN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the CRC16 interrupt.
+ * - 0b1 - Enables the CRC16 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC16EN field. */
+#define USB_RD_ERREN_CRC16EN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC16EN_MASK) >> USB_ERREN_CRC16EN_SHIFT)
+#define USB_BRD_ERREN_CRC16EN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT))
+
+/*! @brief Set the CRC16EN field to a new value. */
+#define USB_WR_ERREN_CRC16EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC16EN_MASK, USB_ERREN_CRC16EN(value)))
+#define USB_BWR_ERREN_CRC16EN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DFN8EN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the DFN8 interrupt.
+ * - 0b1 - Enables the DFN8 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DFN8EN field. */
+#define USB_RD_ERREN_DFN8EN(base) ((USB_ERREN_REG(base) & USB_ERREN_DFN8EN_MASK) >> USB_ERREN_DFN8EN_SHIFT)
+#define USB_BRD_ERREN_DFN8EN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT))
+
+/*! @brief Set the DFN8EN field to a new value. */
+#define USB_WR_ERREN_DFN8EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DFN8EN_MASK, USB_ERREN_DFN8EN(value)))
+#define USB_BWR_ERREN_DFN8EN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTOERREN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the BTOERR interrupt.
+ * - 0b1 - Enables the BTOERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTOERREN field. */
+#define USB_RD_ERREN_BTOERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTOERREN_MASK) >> USB_ERREN_BTOERREN_SHIFT)
+#define USB_BRD_ERREN_BTOERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT))
+
+/*! @brief Set the BTOERREN field to a new value. */
+#define USB_WR_ERREN_BTOERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTOERREN_MASK, USB_ERREN_BTOERREN(value)))
+#define USB_BWR_ERREN_BTOERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DMAERREN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the DMAERR interrupt.
+ * - 0b1 - Enables the DMAERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DMAERREN field. */
+#define USB_RD_ERREN_DMAERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_DMAERREN_MASK) >> USB_ERREN_DMAERREN_SHIFT)
+#define USB_BRD_ERREN_DMAERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT))
+
+/*! @brief Set the DMAERREN field to a new value. */
+#define USB_WR_ERREN_DMAERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DMAERREN_MASK, USB_ERREN_DMAERREN(value)))
+#define USB_BWR_ERREN_DMAERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTSERREN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the BTSERR interrupt.
+ * - 0b1 - Enables the BTSERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTSERREN field. */
+#define USB_RD_ERREN_BTSERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTSERREN_MASK) >> USB_ERREN_BTSERREN_SHIFT)
+#define USB_BRD_ERREN_BTSERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT))
+
+/*! @brief Set the BTSERREN field to a new value. */
+#define USB_WR_ERREN_BTSERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTSERREN_MASK, USB_ERREN_BTSERREN(value)))
+#define USB_BWR_ERREN_BTSERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_STAT - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_STAT - Status register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * Reports the transaction status within the USB module. When the processor's
+ * interrupt controller has received a TOKDNE, interrupt the Status Register must
+ * be read to determine the status of the previous endpoint communication. The
+ * data in the status register is valid when TOKDNE interrupt is asserted. The
+ * Status register is actually a read window into a status FIFO maintained by the USB
+ * module. When the USB module uses a BD, it updates the Status register. If
+ * another USB transaction is performed before the TOKDNE interrupt is serviced, the
+ * USB module stores the status of the next transaction in the STAT FIFO. Thus
+ * STAT is actually a four byte FIFO that allows the processor core to process one
+ * transaction while the SIE is processing the next transaction. Clearing the
+ * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents
+ * of the next STAT value. If the data in the STAT holding register is valid, the
+ * SIE immediately reasserts to TOKDNE interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_STAT register
+ */
+/*@{*/
+#define USB_RD_STAT(base)        (USB_STAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_STAT bitfields
+ */
+
+/*!
+ * @name Register USB_STAT, field ODD[2] (RO)
+ *
+ * This bit is set if the last buffer descriptor updated was in the odd bank of
+ * the BDT.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ODD field. */
+#define USB_RD_STAT_ODD(base) ((USB_STAT_REG(base) & USB_STAT_ODD_MASK) >> USB_STAT_ODD_SHIFT)
+#define USB_BRD_STAT_ODD(base) (BITBAND_ACCESS8(&USB_STAT_REG(base), USB_STAT_ODD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field TX[3] (RO)
+ *
+ * Values:
+ * - 0b0 - The most recent transaction was a receive operation.
+ * - 0b1 - The most recent transaction was a transmit operation.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_TX field. */
+#define USB_RD_STAT_TX(base) ((USB_STAT_REG(base) & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT)
+#define USB_BRD_STAT_TX(base) (BITBAND_ACCESS8(&USB_STAT_REG(base), USB_STAT_TX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field ENDP[7:4] (RO)
+ *
+ * This four-bit field encodes the endpoint address that received or transmitted
+ * the previous token. This allows the processor core to determine the BDT entry
+ * that was updated by the last USB transaction.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ENDP field. */
+#define USB_RD_STAT_ENDP(base) ((USB_STAT_REG(base) & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT)
+#define USB_BRD_STAT_ENDP(base) (USB_RD_STAT_ENDP(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CTL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CTL - Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides various control and configuration information for the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_CTL register
+ */
+/*@{*/
+#define USB_RD_CTL(base)         (USB_CTL_REG(base))
+#define USB_WR_CTL(base, value)  (USB_CTL_REG(base) = (value))
+#define USB_RMW_CTL(base, mask, value) (USB_WR_CTL(base, (USB_RD_CTL(base) & ~(mask)) | (value)))
+#define USB_SET_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) |  (value)))
+#define USB_CLR_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) & ~(value)))
+#define USB_TOG_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CTL bitfields
+ */
+
+/*!
+ * @name Register USB_CTL, field USBENSOFEN[0] (RW)
+ *
+ * Setting this bit enables the USB-FS to operate; clearing it disables the
+ * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs.
+ * Therefore, setting this bit resets much of the logic in the SIE. When host mode
+ * is enabled, clearing this bit causes the SIE to stop sending SOF tokens.
+ *
+ * Values:
+ * - 0b0 - Disables the USB Module.
+ * - 0b1 - Enables the USB Module.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_USBENSOFEN field. */
+#define USB_RD_CTL_USBENSOFEN(base) ((USB_CTL_REG(base) & USB_CTL_USBENSOFEN_MASK) >> USB_CTL_USBENSOFEN_SHIFT)
+#define USB_BRD_CTL_USBENSOFEN(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT))
+
+/*! @brief Set the USBENSOFEN field to a new value. */
+#define USB_WR_CTL_USBENSOFEN(base, value) (USB_RMW_CTL(base, USB_CTL_USBENSOFEN_MASK, USB_CTL_USBENSOFEN(value)))
+#define USB_BWR_CTL_USBENSOFEN(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field ODDRST[1] (RW)
+ *
+ * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which
+ * then specifies the EVEN BDT bank.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_ODDRST field. */
+#define USB_RD_CTL_ODDRST(base) ((USB_CTL_REG(base) & USB_CTL_ODDRST_MASK) >> USB_CTL_ODDRST_SHIFT)
+#define USB_BRD_CTL_ODDRST(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT))
+
+/*! @brief Set the ODDRST field to a new value. */
+#define USB_WR_CTL_ODDRST(base, value) (USB_RMW_CTL(base, USB_CTL_ODDRST_MASK, USB_CTL_ODDRST(value)))
+#define USB_BWR_CTL_ODDRST(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field RESUME[2] (RW)
+ *
+ * When set to 1 this bit enables the USB Module to execute resume signaling.
+ * This allows the USB Module to perform remote wake-up. Software must set RESUME
+ * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN
+ * bit is set, the USB module appends a Low Speed End of Packet to the Resume
+ * signaling when the RESUME bit is cleared. For more information on RESUME
+ * signaling see Section 7.1.4.5 of the USB specification version 1.0.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_RESUME field. */
+#define USB_RD_CTL_RESUME(base) ((USB_CTL_REG(base) & USB_CTL_RESUME_MASK) >> USB_CTL_RESUME_SHIFT)
+#define USB_BRD_CTL_RESUME(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESUME_SHIFT))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_CTL_RESUME(base, value) (USB_RMW_CTL(base, USB_CTL_RESUME_MASK, USB_CTL_RESUME(value)))
+#define USB_BWR_CTL_RESUME(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESUME_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field HOSTMODEEN[3] (RW)
+ *
+ * When set to 1, this bit enables the USB Module to operate in Host mode. In
+ * host mode, the USB module performs USB transactions under the programmed control
+ * of the host processor.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_HOSTMODEEN field. */
+#define USB_RD_CTL_HOSTMODEEN(base) ((USB_CTL_REG(base) & USB_CTL_HOSTMODEEN_MASK) >> USB_CTL_HOSTMODEEN_SHIFT)
+#define USB_BRD_CTL_HOSTMODEEN(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_HOSTMODEEN_SHIFT))
+
+/*! @brief Set the HOSTMODEEN field to a new value. */
+#define USB_WR_CTL_HOSTMODEEN(base, value) (USB_RMW_CTL(base, USB_CTL_HOSTMODEEN_MASK, USB_CTL_HOSTMODEEN(value)))
+#define USB_BWR_CTL_HOSTMODEEN(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_HOSTMODEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field RESET[4] (RW)
+ *
+ * Setting this bit enables the USB Module to generate USB reset signaling. This
+ * allows the USB Module to reset USB peripherals. This control signal is only
+ * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the
+ * required amount of time and then clear it to 0 to end reset signaling. For more
+ * information on reset signaling see Section 7.1.4.3 of the USB specification version
+ * 1.0.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_RESET field. */
+#define USB_RD_CTL_RESET(base) ((USB_CTL_REG(base) & USB_CTL_RESET_MASK) >> USB_CTL_RESET_SHIFT)
+#define USB_BRD_CTL_RESET(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESET_SHIFT))
+
+/*! @brief Set the RESET field to a new value. */
+#define USB_WR_CTL_RESET(base, value) (USB_RMW_CTL(base, USB_CTL_RESET_MASK, USB_CTL_RESET(value)))
+#define USB_BWR_CTL_RESET(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW)
+ *
+ * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB
+ * token. Software must not write more token commands to the Token Register when
+ * TOKEN_BUSY is set. Software should check this field before writing any tokens
+ * to the Token Register to ensure that token commands are not lost. In Target
+ * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and
+ * reception. Clearing this bit allows the SIE to continue token processing. This bit
+ * is set by the SIE when a SETUP Token is received allowing software to dequeue
+ * any pending packet transactions in the BDT before resuming token processing.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field. */
+#define USB_RD_CTL_TXSUSPENDTOKENBUSY(base) ((USB_CTL_REG(base) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) >> USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)
+#define USB_BRD_CTL_TXSUSPENDTOKENBUSY(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))
+
+/*! @brief Set the TXSUSPENDTOKENBUSY field to a new value. */
+#define USB_WR_CTL_TXSUSPENDTOKENBUSY(base, value) (USB_RMW_CTL(base, USB_CTL_TXSUSPENDTOKENBUSY_MASK, USB_CTL_TXSUSPENDTOKENBUSY(value)))
+#define USB_BWR_CTL_TXSUSPENDTOKENBUSY(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field SE0[6] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_SE0 field. */
+#define USB_RD_CTL_SE0(base) ((USB_CTL_REG(base) & USB_CTL_SE0_MASK) >> USB_CTL_SE0_SHIFT)
+#define USB_BRD_CTL_SE0(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT))
+
+/*! @brief Set the SE0 field to a new value. */
+#define USB_WR_CTL_SE0(base, value) (USB_RMW_CTL(base, USB_CTL_SE0_MASK, USB_CTL_SE0(value)))
+#define USB_BWR_CTL_SE0(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field JSTATE[7] (RW)
+ *
+ * The polarity of this signal is affected by the current state of LSEN .
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_JSTATE field. */
+#define USB_RD_CTL_JSTATE(base) ((USB_CTL_REG(base) & USB_CTL_JSTATE_MASK) >> USB_CTL_JSTATE_SHIFT)
+#define USB_BRD_CTL_JSTATE(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT))
+
+/*! @brief Set the JSTATE field to a new value. */
+#define USB_WR_CTL_JSTATE(base, value) (USB_RMW_CTL(base, USB_CTL_JSTATE_MASK, USB_CTL_JSTATE(value)))
+#define USB_BWR_CTL_JSTATE(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDR - Address register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDR - Address register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Holds the unique USB address that the USB module decodes when in Peripheral
+ * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module
+ * transmits this address with a TOKEN packet. This enables the USB module to
+ * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1.
+ * The Address register is reset to 0x00 after the reset input becomes active or
+ * the USB module decodes a USB reset signal. This action initializes the Address
+ * register to decode address 0x00 as required by the USB specification.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDR register
+ */
+/*@{*/
+#define USB_RD_ADDR(base)        (USB_ADDR_REG(base))
+#define USB_WR_ADDR(base, value) (USB_ADDR_REG(base) = (value))
+#define USB_RMW_ADDR(base, mask, value) (USB_WR_ADDR(base, (USB_RD_ADDR(base) & ~(mask)) | (value)))
+#define USB_SET_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) |  (value)))
+#define USB_CLR_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) & ~(value)))
+#define USB_TOG_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDR bitfields
+ */
+
+/*!
+ * @name Register USB_ADDR, field ADDR[6:0] (RW)
+ *
+ * Defines the USB address that the USB module decodes in peripheral mode, or
+ * transmits when in host mode.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_ADDR field. */
+#define USB_RD_ADDR_ADDR(base) ((USB_ADDR_REG(base) & USB_ADDR_ADDR_MASK) >> USB_ADDR_ADDR_SHIFT)
+#define USB_BRD_ADDR_ADDR(base) (USB_RD_ADDR_ADDR(base))
+
+/*! @brief Set the ADDR field to a new value. */
+#define USB_WR_ADDR_ADDR(base, value) (USB_RMW_ADDR(base, USB_ADDR_ADDR_MASK, USB_ADDR_ADDR(value)))
+#define USB_BWR_ADDR_ADDR(base, value) (USB_WR_ADDR_ADDR(base, value))
+/*@}*/
+
+/*!
+ * @name Register USB_ADDR, field LSEN[7] (RW)
+ *
+ * Informs the USB module that the next token command written to the token
+ * register must be performed at low speed. This enables the USB module to perform the
+ * necessary preamble required for low-speed data transmissions.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_LSEN field. */
+#define USB_RD_ADDR_LSEN(base) ((USB_ADDR_REG(base) & USB_ADDR_LSEN_MASK) >> USB_ADDR_LSEN_SHIFT)
+#define USB_BRD_ADDR_LSEN(base) (BITBAND_ACCESS8(&USB_ADDR_REG(base), USB_ADDR_LSEN_SHIFT))
+
+/*! @brief Set the LSEN field to a new value. */
+#define USB_WR_ADDR_LSEN(base, value) (USB_RMW_ADDR(base, USB_ADDR_LSEN_MASK, USB_ADDR_LSEN(value)))
+#define USB_BWR_ADDR_LSEN(base, value) (BITBAND_ACCESS8(&USB_ADDR_REG(base), USB_ADDR_LSEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE1 - BDT Page register 1
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE1 - BDT Page register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides address bits 15 through 9 of the base address where the current
+ * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor
+ * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so
+ * bits 8 through 0 of the base address are always zero.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE1 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE1(base)    (USB_BDTPAGE1_REG(base))
+#define USB_WR_BDTPAGE1(base, value) (USB_BDTPAGE1_REG(base) = (value))
+#define USB_RMW_BDTPAGE1(base, mask, value) (USB_WR_BDTPAGE1(base, (USB_RD_BDTPAGE1(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) |  (value)))
+#define USB_CLR_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) & ~(value)))
+#define USB_TOG_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_BDTPAGE1 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW)
+ *
+ * Provides address bits 15 through 9 of the BDT base address.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_BDTPAGE1_BDTBA field. */
+#define USB_RD_BDTPAGE1_BDTBA(base) ((USB_BDTPAGE1_REG(base) & USB_BDTPAGE1_BDTBA_MASK) >> USB_BDTPAGE1_BDTBA_SHIFT)
+#define USB_BRD_BDTPAGE1_BDTBA(base) (USB_RD_BDTPAGE1_BDTBA(base))
+
+/*! @brief Set the BDTBA field to a new value. */
+#define USB_WR_BDTPAGE1_BDTBA(base, value) (USB_RMW_BDTPAGE1(base, USB_BDTPAGE1_BDTBA_MASK, USB_BDTPAGE1_BDTBA(value)))
+#define USB_BWR_BDTPAGE1_BDTBA(base, value) (USB_WR_BDTPAGE1_BDTBA(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUML - Frame Number register Low
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUML - Frame Number register Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUML register
+ */
+/*@{*/
+#define USB_RD_FRMNUML(base)     (USB_FRMNUML_REG(base))
+#define USB_WR_FRMNUML(base, value) (USB_FRMNUML_REG(base) = (value))
+#define USB_RMW_FRMNUML(base, mask, value) (USB_WR_FRMNUML(base, (USB_RD_FRMNUML(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) |  (value)))
+#define USB_CLR_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) & ~(value)))
+#define USB_TOG_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUMH - Frame Number register High
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUMH - Frame Number register High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUMH register
+ */
+/*@{*/
+#define USB_RD_FRMNUMH(base)     (USB_FRMNUMH_REG(base))
+#define USB_WR_FRMNUMH(base, value) (USB_FRMNUMH_REG(base) = (value))
+#define USB_RMW_FRMNUMH(base, mask, value) (USB_WR_FRMNUMH(base, (USB_RD_FRMNUMH(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) |  (value)))
+#define USB_CLR_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) & ~(value)))
+#define USB_TOG_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_FRMNUMH bitfields
+ */
+
+/*!
+ * @name Register USB_FRMNUMH, field FRM[2:0] (RW)
+ *
+ * This 3-bit field and the 8-bit field in the Frame Number Register Low are
+ * used to compute the address where the current Buffer Descriptor Table (BDT)
+ * resides in system memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_FRMNUMH_FRM field. */
+#define USB_RD_FRMNUMH_FRM(base) ((USB_FRMNUMH_REG(base) & USB_FRMNUMH_FRM_MASK) >> USB_FRMNUMH_FRM_SHIFT)
+#define USB_BRD_FRMNUMH_FRM(base) (USB_RD_FRMNUMH_FRM(base))
+
+/*! @brief Set the FRM field to a new value. */
+#define USB_WR_FRMNUMH_FRM(base, value) (USB_RMW_FRMNUMH(base, USB_FRMNUMH_FRM_MASK, USB_FRMNUMH_FRM(value)))
+#define USB_BWR_FRMNUMH_FRM(base, value) (USB_WR_FRMNUMH_FRM(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_TOKEN - Token register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_TOKEN - Token register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the
+ * software needs to execute a USB transaction to a peripheral, it writes the
+ * TOKEN type and endpoint to this register. After this register has been written,
+ * the USB module begins the specified USB transaction to the address contained in
+ * the address register. The processor core must always check that the
+ * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register.
+ * This ensures that the token commands are not overwritten before they can be
+ * executed. The address register and endpoint control register 0 are also used when
+ * performing a token command and therefore must also be written before the
+ * Token Register. The address register is used to select the USB peripheral address
+ * transmitted by the token command. The endpoint control register determines the
+ * handshake and retry policies used during the transfer.
+ */
+/*!
+ * @name Constants and macros for entire USB_TOKEN register
+ */
+/*@{*/
+#define USB_RD_TOKEN(base)       (USB_TOKEN_REG(base))
+#define USB_WR_TOKEN(base, value) (USB_TOKEN_REG(base) = (value))
+#define USB_RMW_TOKEN(base, mask, value) (USB_WR_TOKEN(base, (USB_RD_TOKEN(base) & ~(mask)) | (value)))
+#define USB_SET_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) |  (value)))
+#define USB_CLR_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) & ~(value)))
+#define USB_TOG_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_TOKEN bitfields
+ */
+
+/*!
+ * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW)
+ *
+ * Holds the Endpoint address for the token command. The four bit value written
+ * must be a valid endpoint.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_TOKEN_TOKENENDPT field. */
+#define USB_RD_TOKEN_TOKENENDPT(base) ((USB_TOKEN_REG(base) & USB_TOKEN_TOKENENDPT_MASK) >> USB_TOKEN_TOKENENDPT_SHIFT)
+#define USB_BRD_TOKEN_TOKENENDPT(base) (USB_RD_TOKEN_TOKENENDPT(base))
+
+/*! @brief Set the TOKENENDPT field to a new value. */
+#define USB_WR_TOKEN_TOKENENDPT(base, value) (USB_RMW_TOKEN(base, USB_TOKEN_TOKENENDPT_MASK, USB_TOKEN_TOKENENDPT(value)))
+#define USB_BWR_TOKEN_TOKENENDPT(base, value) (USB_WR_TOKEN_TOKENENDPT(base, value))
+/*@}*/
+
+/*!
+ * @name Register USB_TOKEN, field TOKENPID[7:4] (RW)
+ *
+ * Contains the token type executed by the USB module.
+ *
+ * Values:
+ * - 0b0001 - OUT Token. USB Module performs an OUT (TX) transaction.
+ * - 0b1001 - IN Token. USB Module performs an In (RX) transaction.
+ * - 0b1101 - SETUP Token. USB Module performs a SETUP (TX) transaction
+ */
+/*@{*/
+/*! @brief Read current value of the USB_TOKEN_TOKENPID field. */
+#define USB_RD_TOKEN_TOKENPID(base) ((USB_TOKEN_REG(base) & USB_TOKEN_TOKENPID_MASK) >> USB_TOKEN_TOKENPID_SHIFT)
+#define USB_BRD_TOKEN_TOKENPID(base) (USB_RD_TOKEN_TOKENPID(base))
+
+/*! @brief Set the TOKENPID field to a new value. */
+#define USB_WR_TOKEN_TOKENPID(base, value) (USB_RMW_TOKEN(base, USB_TOKEN_TOKENPID_MASK, USB_TOKEN_TOKENPID(value)))
+#define USB_BWR_TOKEN_TOKENPID(base, value) (USB_WR_TOKEN_TOKENPID(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_SOFTHLD - SOF Threshold register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_SOFTHLD - SOF Threshold register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in
+ * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The
+ * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with
+ * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF)
+ * token is transmitted. The SOF threshold register is used to program the number
+ * of USB byte times before the SOF to stop initiating token packet transactions.
+ * This register must be set to a value that ensures that other packets are not
+ * actively being transmitted when the SOF time counts to zero. When the SOF
+ * counter reaches the threshold value, no more tokens are transmitted until after the
+ * SOF has been transmitted. The value programmed into the threshold register
+ * must reserve enough time to ensure the worst case transaction completes. In
+ * general the worst case transaction is an IN token followed by a data packet from
+ * the target followed by the response from the host. The actual time required is
+ * a function of the maximum packet size on the bus. Typical values for the SOF
+ * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26;
+ * 8-byte packets=18.
+ */
+/*!
+ * @name Constants and macros for entire USB_SOFTHLD register
+ */
+/*@{*/
+#define USB_RD_SOFTHLD(base)     (USB_SOFTHLD_REG(base))
+#define USB_WR_SOFTHLD(base, value) (USB_SOFTHLD_REG(base) = (value))
+#define USB_RMW_SOFTHLD(base, mask, value) (USB_WR_SOFTHLD(base, (USB_RD_SOFTHLD(base) & ~(mask)) | (value)))
+#define USB_SET_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) |  (value)))
+#define USB_CLR_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) & ~(value)))
+#define USB_TOG_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE2 - BDT Page Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE2 - BDT Page Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE2 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE2(base)    (USB_BDTPAGE2_REG(base))
+#define USB_WR_BDTPAGE2(base, value) (USB_BDTPAGE2_REG(base) = (value))
+#define USB_RMW_BDTPAGE2(base, mask, value) (USB_WR_BDTPAGE2(base, (USB_RD_BDTPAGE2(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) |  (value)))
+#define USB_CLR_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) & ~(value)))
+#define USB_TOG_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE3 - BDT Page Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE3 - BDT Page Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE3 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE3(base)    (USB_BDTPAGE3_REG(base))
+#define USB_WR_BDTPAGE3(base, value) (USB_BDTPAGE3_REG(base) = (value))
+#define USB_RMW_BDTPAGE3(base, mask, value) (USB_WR_BDTPAGE3(base, (USB_RD_BDTPAGE3(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) |  (value)))
+#define USB_CLR_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) & ~(value)))
+#define USB_TOG_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ENDPT - Endpoint Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ENDPT - Endpoint Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains the endpoint control bits for each of the 16 endpoints available
+ * within the USB module for a decoded address. The format for these registers is
+ * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control
+ * pipe 0, which is required for all USB functions. Therefore, after a USBRST
+ * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode
+ * ENDPT0 is used to determine the handshake, retry and low speed
+ * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
+ * bit should be 1. For Isochronous transfers it should be 0. Common values to
+ * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
+ * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and
+ * EPTXEN define if an endpoint is enabled and define the direction of the endpoint.
+ * The endpoint enable/direction control is defined in the following table.
+ * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint
+ * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only
+ * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and
+ * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP)
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire USB_ENDPT register
+ */
+/*@{*/
+#define USB_RD_ENDPT(base, index) (USB_ENDPT_REG(base, index))
+#define USB_WR_ENDPT(base, index, value) (USB_ENDPT_REG(base, index) = (value))
+#define USB_RMW_ENDPT(base, index, mask, value) (USB_WR_ENDPT(base, index, (USB_RD_ENDPT(base, index) & ~(mask)) | (value)))
+#define USB_SET_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) |  (value)))
+#define USB_CLR_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) & ~(value)))
+#define USB_TOG_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ENDPT bitfields
+ */
+
+/*!
+ * @name Register USB_ENDPT, field EPHSHK[0] (RW)
+ *
+ * When set this bit enables an endpoint to perform handshaking during a
+ * transaction to this endpoint. This bit is generally 1 unless the endpoint is
+ * Isochronous.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPHSHK field. */
+#define USB_RD_ENDPT_EPHSHK(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPHSHK_MASK) >> USB_ENDPT_EPHSHK_SHIFT)
+#define USB_BRD_ENDPT_EPHSHK(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT))
+
+/*! @brief Set the EPHSHK field to a new value. */
+#define USB_WR_ENDPT_EPHSHK(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPHSHK_MASK, USB_ENDPT_EPHSHK(value)))
+#define USB_BWR_ENDPT_EPHSHK(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPSTALL[1] (RW)
+ *
+ * When set this bit indicates that the endpoint is called. This bit has
+ * priority over all other control bits in the EndPoint Enable Register, but it is only
+ * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB
+ * Module to return a STALL handshake. After an endpoint is stalled it requires
+ * intervention from the Host Controller.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPSTALL field. */
+#define USB_RD_ENDPT_EPSTALL(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPSTALL_MASK) >> USB_ENDPT_EPSTALL_SHIFT)
+#define USB_BRD_ENDPT_EPSTALL(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT))
+
+/*! @brief Set the EPSTALL field to a new value. */
+#define USB_WR_ENDPT_EPSTALL(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPSTALL_MASK, USB_ENDPT_EPSTALL(value)))
+#define USB_BWR_ENDPT_EPSTALL(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPTXEN[2] (RW)
+ *
+ * This bit, when set, enables the endpoint for TX transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPTXEN field. */
+#define USB_RD_ENDPT_EPTXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPTXEN_MASK) >> USB_ENDPT_EPTXEN_SHIFT)
+#define USB_BRD_ENDPT_EPTXEN(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT))
+
+/*! @brief Set the EPTXEN field to a new value. */
+#define USB_WR_ENDPT_EPTXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPTXEN_MASK, USB_ENDPT_EPTXEN(value)))
+#define USB_BWR_ENDPT_EPTXEN(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPRXEN[3] (RW)
+ *
+ * This bit, when set, enables the endpoint for RX transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPRXEN field. */
+#define USB_RD_ENDPT_EPRXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPRXEN_MASK) >> USB_ENDPT_EPRXEN_SHIFT)
+#define USB_BRD_ENDPT_EPRXEN(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT))
+
+/*! @brief Set the EPRXEN field to a new value. */
+#define USB_WR_ENDPT_EPRXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPRXEN_MASK, USB_ENDPT_EPRXEN(value)))
+#define USB_BWR_ENDPT_EPRXEN(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPCTLDIS[4] (RW)
+ *
+ * This bit, when set, disables control (SETUP) transfers. When cleared, control
+ * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
+ * are also set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPCTLDIS field. */
+#define USB_RD_ENDPT_EPCTLDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPCTLDIS_MASK) >> USB_ENDPT_EPCTLDIS_SHIFT)
+#define USB_BRD_ENDPT_EPCTLDIS(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT))
+
+/*! @brief Set the EPCTLDIS field to a new value. */
+#define USB_WR_ENDPT_EPCTLDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPCTLDIS_MASK, USB_ENDPT_EPCTLDIS(value)))
+#define USB_BWR_ENDPT_EPCTLDIS(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field RETRYDIS[6] (RW)
+ *
+ * This is a Host mode only bit and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed
+ * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID
+ * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When
+ * this bit is cleared, NAKed transactions are retried in hardware. This bit must
+ * be set when the host is attempting to poll an interrupt endpoint.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_RETRYDIS field. */
+#define USB_RD_ENDPT_RETRYDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_RETRYDIS_MASK) >> USB_ENDPT_RETRYDIS_SHIFT)
+#define USB_BRD_ENDPT_RETRYDIS(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_RETRYDIS_SHIFT))
+
+/*! @brief Set the RETRYDIS field to a new value. */
+#define USB_WR_ENDPT_RETRYDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_RETRYDIS_MASK, USB_ENDPT_RETRYDIS(value)))
+#define USB_BWR_ENDPT_RETRYDIS(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_RETRYDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field HOSTWOHUB[7] (RW)
+ *
+ * This is a Host mode only field and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a
+ * directly connected low speed device. When cleared, the host produces the
+ * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed
+ * device as required to communicate with a low speed device through a hub.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_HOSTWOHUB field. */
+#define USB_RD_ENDPT_HOSTWOHUB(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_HOSTWOHUB_MASK) >> USB_ENDPT_HOSTWOHUB_SHIFT)
+#define USB_BRD_ENDPT_HOSTWOHUB(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_HOSTWOHUB_SHIFT))
+
+/*! @brief Set the HOSTWOHUB field to a new value. */
+#define USB_WR_ENDPT_HOSTWOHUB(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_HOSTWOHUB_MASK, USB_ENDPT_HOSTWOHUB(value)))
+#define USB_BWR_ENDPT_HOSTWOHUB(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_HOSTWOHUB_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBCTRL - USB Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBCTRL - USB Control register (RW)
+ *
+ * Reset value: 0xC0U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBCTRL register
+ */
+/*@{*/
+#define USB_RD_USBCTRL(base)     (USB_USBCTRL_REG(base))
+#define USB_WR_USBCTRL(base, value) (USB_USBCTRL_REG(base) = (value))
+#define USB_RMW_USBCTRL(base, mask, value) (USB_WR_USBCTRL(base, (USB_RD_USBCTRL(base) & ~(mask)) | (value)))
+#define USB_SET_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) |  (value)))
+#define USB_CLR_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) & ~(value)))
+#define USB_TOG_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBCTRL bitfields
+ */
+
+/*!
+ * @name Register USB_USBCTRL, field PDE[6] (RW)
+ *
+ * Enables the weak pulldowns on the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - Weak pulldowns are disabled on D+ and D-.
+ * - 0b1 - Weak pulldowns are enabled on D+ and D-.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_PDE field. */
+#define USB_RD_USBCTRL_PDE(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_PDE_MASK) >> USB_USBCTRL_PDE_SHIFT)
+#define USB_BRD_USBCTRL_PDE(base) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT))
+
+/*! @brief Set the PDE field to a new value. */
+#define USB_WR_USBCTRL_PDE(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_PDE_MASK, USB_USBCTRL_PDE(value)))
+#define USB_BWR_USBCTRL_PDE(base, value) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_USBCTRL, field SUSP[7] (RW)
+ *
+ * Places the USB transceiver into the suspend state.
+ *
+ * Values:
+ * - 0b0 - USB transceiver is not in suspend state.
+ * - 0b1 - USB transceiver is in suspend state.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_SUSP field. */
+#define USB_RD_USBCTRL_SUSP(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_SUSP_MASK) >> USB_USBCTRL_SUSP_SHIFT)
+#define USB_BRD_USBCTRL_SUSP(base) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT))
+
+/*! @brief Set the SUSP field to a new value. */
+#define USB_WR_USBCTRL_SUSP(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_SUSP_MASK, USB_USBCTRL_SUSP(value)))
+#define USB_BWR_USBCTRL_SUSP(base, value) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OBSERVE - USB OTG Observe register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OBSERVE - USB OTG Observe register (RO)
+ *
+ * Reset value: 0x50U
+ *
+ * Provides visibility on the state of the pull-ups and pull-downs at the
+ * transceiver. Useful when interfacing to an external OTG control module via a serial
+ * interface.
+ */
+/*!
+ * @name Constants and macros for entire USB_OBSERVE register
+ */
+/*@{*/
+#define USB_RD_OBSERVE(base)     (USB_OBSERVE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OBSERVE bitfields
+ */
+
+/*!
+ * @name Register USB_OBSERVE, field DMPD[4] (RO)
+ *
+ * Provides observability of the D- Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D- pulldown disabled.
+ * - 0b1 - D- pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DMPD field. */
+#define USB_RD_OBSERVE_DMPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DMPD_MASK) >> USB_OBSERVE_DMPD_SHIFT)
+#define USB_BRD_OBSERVE_DMPD(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DMPD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPD[6] (RO)
+ *
+ * Provides observability of the D+ Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D+ pulldown disabled.
+ * - 0b1 - D+ pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPD field. */
+#define USB_RD_OBSERVE_DPPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPD_MASK) >> USB_OBSERVE_DPPD_SHIFT)
+#define USB_BRD_OBSERVE_DPPD(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPU[7] (RO)
+ *
+ * Provides observability of the D+ Pullup enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D+ pullup disabled.
+ * - 0b1 - D+ pullup enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPU field. */
+#define USB_RD_OBSERVE_DPPU(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPU_MASK) >> USB_OBSERVE_DPPU_SHIFT)
+#define USB_BRD_OBSERVE_DPPU(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPU_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CONTROL - USB OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CONTROL - USB OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_CONTROL register
+ */
+/*@{*/
+#define USB_RD_CONTROL(base)     (USB_CONTROL_REG(base))
+#define USB_WR_CONTROL(base, value) (USB_CONTROL_REG(base) = (value))
+#define USB_RMW_CONTROL(base, mask, value) (USB_WR_CONTROL(base, (USB_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USB_SET_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) |  (value)))
+#define USB_CLR_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) & ~(value)))
+#define USB_TOG_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW)
+ *
+ * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG
+ * device mode.
+ *
+ * Values:
+ * - 0b0 - DP Pullup in non-OTG device mode is not enabled.
+ * - 0b1 - DP Pullup in non-OTG device mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field. */
+#define USB_RD_CONTROL_DPPULLUPNONOTG(base) ((USB_CONTROL_REG(base) & USB_CONTROL_DPPULLUPNONOTG_MASK) >> USB_CONTROL_DPPULLUPNONOTG_SHIFT)
+#define USB_BRD_CONTROL_DPPULLUPNONOTG(base) (BITBAND_ACCESS8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT))
+
+/*! @brief Set the DPPULLUPNONOTG field to a new value. */
+#define USB_WR_CONTROL_DPPULLUPNONOTG(base, value) (USB_RMW_CONTROL(base, USB_CONTROL_DPPULLUPNONOTG_MASK, USB_CONTROL_DPPULLUPNONOTG(value)))
+#define USB_BWR_CONTROL_DPPULLUPNONOTG(base, value) (BITBAND_ACCESS8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBTRC0 - USB Transceiver Control register 0
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBTRC0 - USB Transceiver Control register 0 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Includes signals for basic operation of the on-chip USB Full Speed
+ * transceiver and configuration of the USB data connection that are not otherwise included
+ * in the USB Full Speed controller registers.
+ */
+/*!
+ * @name Constants and macros for entire USB_USBTRC0 register
+ */
+/*@{*/
+#define USB_RD_USBTRC0(base)     (USB_USBTRC0_REG(base))
+#define USB_WR_USBTRC0(base, value) (USB_USBTRC0_REG(base) = (value))
+#define USB_RMW_USBTRC0(base, mask, value) (USB_WR_USBTRC0(base, (USB_RD_USBTRC0(base) & ~(mask)) | (value)))
+#define USB_SET_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) |  (value)))
+#define USB_CLR_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) & ~(value)))
+#define USB_TOG_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBTRC0 bitfields
+ */
+
+/*!
+ * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No interrupt was generated.
+ * - 0b1 - Interrupt was generated because of the USB asynchronous interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field. */
+#define USB_RD_USBTRC0_USB_RESUME_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_RESUME_INT_MASK) >> USB_USBTRC0_USB_RESUME_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_RESUME_INT(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_RESUME_INT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field SYNC_DET[1] (RO)
+ *
+ * Values:
+ * - 0b0 - Synchronous interrupt has not been detected.
+ * - 0b1 - Synchronous interrupt has been detected.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_SYNC_DET field. */
+#define USB_RD_USBTRC0_SYNC_DET(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_SYNC_DET_MASK) >> USB_USBTRC0_SYNC_DET_SHIFT)
+#define USB_BRD_USBTRC0_SYNC_DET(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_SYNC_DET_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO)
+ *
+ * This read-only field will be set to value high at 1'b1 when any of USB clock
+ * recovery interrupt conditions are detected and those interrupts are unmasked.
+ * For customer use the only unmasked USB clock recovery interrupt condition
+ * results from an overflow of the frequency trim setting values indicating that the
+ * frequency trim calculated is out of the adjustment range of the IRC48M output
+ * clock. To clear this bit after it has been set, Write 0xFF to register
+ * USB_CLK_RECOVER_INT_STATUS.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field. */
+#define USB_RD_USBTRC0_USB_CLK_RECOVERY_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) >> USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_CLK_RECOVERY_INT(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESMEN[5] (RW)
+ *
+ * This bit, when set, allows the USB module to send an asynchronous wakeup
+ * event to the MCU upon detection of resume signaling on the USB bus. The MCU then
+ * re-enables clocks to the USB module. It is used for low-power suspend mode when
+ * USB module clocks are stopped or the USB transceiver is in Suspend mode.
+ * Async wakeup only works in device mode.
+ *
+ * Values:
+ * - 0b0 - USB asynchronous wakeup from suspend mode disabled.
+ * - 0b1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous
+ *     resume interrupt differs from the synchronous resume interrupt in that it
+ *     asynchronously detects K-state using the unfiltered state of the D+ and D-
+ *     pins. This interrupt should only be enabled when the Transceiver is
+ *     suspended.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USBRESMEN field. */
+#define USB_RD_USBTRC0_USBRESMEN(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USBRESMEN_MASK) >> USB_USBTRC0_USBRESMEN_SHIFT)
+#define USB_BRD_USBTRC0_USBRESMEN(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT))
+
+/*! @brief Set the USBRESMEN field to a new value. */
+#define USB_WR_USBTRC0_USBRESMEN(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESMEN_MASK, USB_USBTRC0_USBRESMEN(value)))
+#define USB_BWR_USBTRC0_USBRESMEN(base, value) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESET[7] (WO)
+ *
+ * Generates a hard reset to USBOTG. After this bit is set and the reset occurs,
+ * this bit is automatically cleared. This bit is always read as zero. Wait two
+ * USB clock cycles after setting this bit.
+ *
+ * Values:
+ * - 0b0 - Normal USB module operation.
+ * - 0b1 - Returns the USB module to its reset state.
+ */
+/*@{*/
+/*! @brief Set the USBRESET field to a new value. */
+#define USB_WR_USBTRC0_USBRESET(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESET_MASK, USB_USBTRC0_USBRESET(value)))
+#define USB_BWR_USBTRC0_USBRESET(base, value) (USB_WR_USBTRC0_USBRESET(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBFRMADJUST - Frame Adjust Register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBFRMADJUST - Frame Adjust Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBFRMADJUST register
+ */
+/*@{*/
+#define USB_RD_USBFRMADJUST(base) (USB_USBFRMADJUST_REG(base))
+#define USB_WR_USBFRMADJUST(base, value) (USB_USBFRMADJUST_REG(base) = (value))
+#define USB_RMW_USBFRMADJUST(base, mask, value) (USB_WR_USBFRMADJUST(base, (USB_RD_USBFRMADJUST(base) & ~(mask)) | (value)))
+#define USB_SET_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) |  (value)))
+#define USB_CLR_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) & ~(value)))
+#define USB_TOG_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Signals in this register control the crystal-less USB clock mode in which the
+ * internal IRC48M oscillator is tuned to match the clock extracted from the
+ * incoming USB data stream. The IRC48M internal oscillator module must be enabled
+ * in register USB_CLK_RECOVER_IRC_EN for this mode.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_CTRL(base) (USB_CLK_RECOVER_CTRL_REG(base))
+#define USB_WR_CLK_RECOVER_CTRL(base, value) (USB_CLK_RECOVER_CTRL_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_CTRL(base, mask, value) (USB_WR_CLK_RECOVER_CTRL(base, (USB_RD_CLK_RECOVER_CTRL(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW)
+ *
+ * IRC48 has a default trim fine value whose default value is factory trimmed
+ * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz
+ * and keeps updating the trim fine value accordingly
+ *
+ * Values:
+ * - 0b0 - Trim fine adjustment always works based on the previous updated trim
+ *     fine value (default)
+ * - 0b1 - Trim fine restarts from the IFR trim value whenever
+ *     bus_reset/bus_resume is detected or module enable is desasserted
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))
+
+/*! @brief Set the RESTART_IFRTRIM_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW)
+ *
+ * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock.
+ * It has two phases after user enables clock_recover_en bit, rough phase and
+ * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine
+ * value is different during these two phases. The step in rough phase is larger
+ * than that in tracking phase. Switch back to rough stage whenever USB bus reset
+ * or bus resume occurs.
+ *
+ * Values:
+ * - 0b0 - Always works in tracking phase after the 1st time rough to track
+ *     transition (default)
+ * - 0b1 - Go back to rough stage whenever bus reset or bus resume occurs
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))
+
+/*! @brief Set the RESET_RESUME_ROUGH_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW)
+ *
+ * This bit must be enabled if user wants to use the crystal-less USB mode for
+ * the Full Speed USB controller and transceiver. This bit should not be set for
+ * USB host mode or OTG.
+ *
+ * Values:
+ * - 0b0 - Disable clock recovery block (default)
+ * - 0b1 - Enable clock recovery block
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) >> USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))
+
+/*! @brief Set the CLOCK_RECOVER_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * Controls basic operation of the on-chip IRC48M module used to produce nominal
+ * 48MHz clocks for USB crystal-less operation and other functions. See
+ * additional information about the IRC48M operation in the Clock Distribution chapter.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_IRC_EN(base) (USB_CLK_RECOVER_IRC_EN_REG(base))
+#define USB_WR_CLK_RECOVER_IRC_EN(base, value) (USB_CLK_RECOVER_IRC_EN_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_IRC_EN(base, mask, value) (USB_WR_CLK_RECOVER_IRC_EN(base, (USB_RD_CLK_RECOVER_IRC_EN(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW)
+ *
+ * This bit is used to enable the local analog regulator for IRC48Mhz module.
+ * This bit must be set if user wants to use the crystal-less USB clock
+ * configuration.
+ *
+ * Values:
+ * - 0b0 - IRC48M local regulator is disabled
+ * - 0b1 - IRC48M local regulator is enabled (default)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_REG_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_REG_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))
+
+/*! @brief Set the REG_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_REG_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_REG_EN_MASK, USB_CLK_RECOVER_IRC_EN_REG_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_REG_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
+ *
+ * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
+ * crystal-less USB. It can only be used for FS USB device mode operation. This
+ * bit must be set before using the crystal-less USB clock configuration.
+ *
+ * Values:
+ * - 0b0 - Disable the IRC48M module (default)
+ * - 0b1 - Enable the IRC48M module
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_IRC_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_IRC_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))
+
+/*! @brief Set the IRC_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK, USB_CLK_RECOVER_IRC_EN_IRC_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * A Write operation with value high at 1'b1 on any combination of individual
+ * bits will clear those bits.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_INT_STATUS(base) (USB_CLK_RECOVER_INT_STATUS_REG(base))
+#define USB_WR_CLK_RECOVER_INT_STATUS(base, value) (USB_CLK_RECOVER_INT_STATUS_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_INT_STATUS(base, mask, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, (USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C)
+ *
+ * Indicates that the USB clock recovery algorithm has detected that the
+ * frequency trim adjustment needed for the IRC48M output clock is outside the available
+ * TRIM_FINE adjustment range for the IRC48M module.
+ *
+ * Values:
+ * - 0b0 - No interrupt is reported
+ * - 0b1 - Unmasked interrupt has been generated
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field. */
+#define USB_RD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) ((USB_CLK_RECOVER_INT_STATUS_REG(base) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) >> USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)
+#define USB_BRD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))
+
+/*! @brief Set the OVF_ERROR field to a new value. */
+#define USB_WR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (USB_RMW_CLK_RECOVER_INT_STATUS(base, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(value)))
+#define USB_BWR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 USBDCD
+ *
+ * USB Device Charger Detection module
+ *
+ * Registers defined in this header file:
+ * - USBDCD_CONTROL - Control register
+ * - USBDCD_CLOCK - Clock register
+ * - USBDCD_STATUS - Status register
+ * - USBDCD_TIMER0 - TIMER0 register
+ * - USBDCD_TIMER1 - TIMER1 register
+ * - USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ * - USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ */
+
+#define USBDCD_INSTANCE_COUNT (1U) /*!< Number of instances of the USBDCD module. */
+#define USBDCD_IDX (0U) /*!< Instance number for USBDCD. */
+
+/*******************************************************************************
+ * USBDCD_CONTROL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_CONTROL - Control register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Contains the control and interrupt bit fields.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_CONTROL register
+ */
+/*@{*/
+#define USBDCD_RD_CONTROL(base)  (USBDCD_CONTROL_REG(base))
+#define USBDCD_WR_CONTROL(base, value) (USBDCD_CONTROL_REG(base) = (value))
+#define USBDCD_RMW_CONTROL(base, mask, value) (USBDCD_WR_CONTROL(base, (USBDCD_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USBDCD_SET_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) |  (value)))
+#define USBDCD_CLR_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) & ~(value)))
+#define USBDCD_TOG_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CONTROL, field IACK[0] (WORZ)
+ *
+ * Determines whether the interrupt is cleared.
+ *
+ * Values:
+ * - 0b0 - Do not clear the interrupt.
+ * - 0b1 - Clear the IF bit (interrupt flag).
+ */
+/*@{*/
+/*! @brief Set the IACK field to a new value. */
+#define USBDCD_WR_CONTROL_IACK(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_IACK_MASK, USBDCD_CONTROL_IACK(value)))
+#define USBDCD_BWR_CONTROL_IACK(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field IF[8] (RO)
+ *
+ * Determines whether an interrupt is pending.
+ *
+ * Values:
+ * - 0b0 - No interrupt is pending.
+ * - 0b1 - An interrupt is pending.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_IF field. */
+#define USBDCD_RD_CONTROL_IF(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_IF_MASK) >> USBDCD_CONTROL_IF_SHIFT)
+#define USBDCD_BRD_CONTROL_IF(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field IE[16] (RW)
+ *
+ * Enables/disables interrupts to the system.
+ *
+ * Values:
+ * - 0b0 - Disable interrupts to the system.
+ * - 0b1 - Enable interrupts to the system.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_IE field. */
+#define USBDCD_RD_CONTROL_IE(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_IE_MASK) >> USBDCD_CONTROL_IE_SHIFT)
+#define USBDCD_BRD_CONTROL_IE(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IE_SHIFT))
+
+/*! @brief Set the IE field to a new value. */
+#define USBDCD_WR_CONTROL_IE(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_IE_MASK, USBDCD_CONTROL_IE(value)))
+#define USBDCD_BWR_CONTROL_IE(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field BC12[17] (RW)
+ *
+ * BC1.2 compatibility. This bit cannot be changed after start detection.
+ *
+ * Values:
+ * - 0b0 - Compatible with BC1.1 (default)
+ * - 0b1 - Compatible with BC1.2
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_BC12 field. */
+#define USBDCD_RD_CONTROL_BC12(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_BC12_MASK) >> USBDCD_CONTROL_BC12_SHIFT)
+#define USBDCD_BRD_CONTROL_BC12(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_BC12_SHIFT))
+
+/*! @brief Set the BC12 field to a new value. */
+#define USBDCD_WR_CONTROL_BC12(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_BC12_MASK, USBDCD_CONTROL_BC12(value)))
+#define USBDCD_BWR_CONTROL_BC12(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_BC12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field START[24] (WORZ)
+ *
+ * Determines whether the charger detection sequence is initiated.
+ *
+ * Values:
+ * - 0b0 - Do not start the sequence. Writes of this value have no effect.
+ * - 0b1 - Initiate the charger detection sequence. If the sequence is already
+ *     running, writes of this value have no effect.
+ */
+/*@{*/
+/*! @brief Set the START field to a new value. */
+#define USBDCD_WR_CONTROL_START(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_START_MASK, USBDCD_CONTROL_START(value)))
+#define USBDCD_BWR_CONTROL_START(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_START_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field SR[25] (WORZ)
+ *
+ * Determines whether a software reset is performed.
+ *
+ * Values:
+ * - 0b0 - Do not perform a software reset.
+ * - 0b1 - Perform a software reset.
+ */
+/*@{*/
+/*! @brief Set the SR field to a new value. */
+#define USBDCD_WR_CONTROL_SR(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_SR_MASK, USBDCD_CONTROL_SR(value)))
+#define USBDCD_BWR_CONTROL_SR(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_SR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_CLOCK - Clock register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_CLOCK - Clock register (RW)
+ *
+ * Reset value: 0x000000C1U
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_CLOCK register
+ */
+/*@{*/
+#define USBDCD_RD_CLOCK(base)    (USBDCD_CLOCK_REG(base))
+#define USBDCD_WR_CLOCK(base, value) (USBDCD_CLOCK_REG(base) = (value))
+#define USBDCD_RMW_CLOCK(base, mask, value) (USBDCD_WR_CLOCK(base, (USBDCD_RD_CLOCK(base) & ~(mask)) | (value)))
+#define USBDCD_SET_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) |  (value)))
+#define USBDCD_CLR_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) & ~(value)))
+#define USBDCD_TOG_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_CLOCK bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW)
+ *
+ * Specifies the unit of measure for the clock speed.
+ *
+ * Values:
+ * - 0b0 - kHz Speed (between 1 kHz and 1023 kHz)
+ * - 0b1 - MHz Speed (between 1 MHz and 1023 MHz)
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field. */
+#define USBDCD_RD_CLOCK_CLOCK_UNIT(base) ((USBDCD_CLOCK_REG(base) & USBDCD_CLOCK_CLOCK_UNIT_MASK) >> USBDCD_CLOCK_CLOCK_UNIT_SHIFT)
+#define USBDCD_BRD_CLOCK_CLOCK_UNIT(base) (BITBAND_ACCESS32(&USBDCD_CLOCK_REG(base), USBDCD_CLOCK_CLOCK_UNIT_SHIFT))
+
+/*! @brief Set the CLOCK_UNIT field to a new value. */
+#define USBDCD_WR_CLOCK_CLOCK_UNIT(base, value) (USBDCD_RMW_CLOCK(base, USBDCD_CLOCK_CLOCK_UNIT_MASK, USBDCD_CLOCK_CLOCK_UNIT(value)))
+#define USBDCD_BWR_CLOCK_CLOCK_UNIT(base, value) (BITBAND_ACCESS32(&USBDCD_CLOCK_REG(base), USBDCD_CLOCK_CLOCK_UNIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW)
+ *
+ * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to
+ * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples
+ * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz:
+ * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100)
+ * For 500 kHz: 0b01_1111_0100 (500)
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field. */
+#define USBDCD_RD_CLOCK_CLOCK_SPEED(base) ((USBDCD_CLOCK_REG(base) & USBDCD_CLOCK_CLOCK_SPEED_MASK) >> USBDCD_CLOCK_CLOCK_SPEED_SHIFT)
+#define USBDCD_BRD_CLOCK_CLOCK_SPEED(base) (USBDCD_RD_CLOCK_CLOCK_SPEED(base))
+
+/*! @brief Set the CLOCK_SPEED field to a new value. */
+#define USBDCD_WR_CLOCK_CLOCK_SPEED(base, value) (USBDCD_RMW_CLOCK(base, USBDCD_CLOCK_CLOCK_SPEED_MASK, USBDCD_CLOCK_CLOCK_SPEED(value)))
+#define USBDCD_BWR_CLOCK_CLOCK_SPEED(base, value) (USBDCD_WR_CLOCK_CLOCK_SPEED(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_STATUS - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_STATUS - Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Provides the current state of the module for system software monitoring.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_STATUS register
+ */
+/*@{*/
+#define USBDCD_RD_STATUS(base)   (USBDCD_STATUS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_STATUS bitfields
+ */
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO)
+ *
+ * Reports how the charger detection is attached.
+ *
+ * Values:
+ * - 0b00 - No results to report.
+ * - 0b01 - Attached to a standard host. Must comply with USB 2.0 by drawing
+ *     only 2.5 mA (max) until connected.
+ * - 0b10 - Attached to a charging port. The exact meaning depends on bit 18: 0:
+ *     Attached to either a charging host or a dedicated charger. The charger
+ *     type detection has not completed. 1: Attached to a charging host. The
+ *     charger type detection has completed.
+ * - 0b11 - Attached to a dedicated charger.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_SEQ_RES field. */
+#define USBDCD_RD_STATUS_SEQ_RES(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_SEQ_RES_MASK) >> USBDCD_STATUS_SEQ_RES_SHIFT)
+#define USBDCD_BRD_STATUS_SEQ_RES(base) (USBDCD_RD_STATUS_SEQ_RES(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO)
+ *
+ * Indicates the status of the charger detection sequence.
+ *
+ * Values:
+ * - 0b00 - The module is either not enabled, or the module is enabled but the
+ *     data pins have not yet been detected.
+ * - 0b01 - Data pin contact detection is complete.
+ * - 0b10 - Charging port detection is complete.
+ * - 0b11 - Charger type detection is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field. */
+#define USBDCD_RD_STATUS_SEQ_STAT(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_SEQ_STAT_MASK) >> USBDCD_STATUS_SEQ_STAT_SHIFT)
+#define USBDCD_BRD_STATUS_SEQ_STAT(base) (USBDCD_RD_STATUS_SEQ_STAT(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field ERR[20] (RO)
+ *
+ * Indicates whether there is an error in the detection sequence.
+ *
+ * Values:
+ * - 0b0 - No sequence errors.
+ * - 0b1 - Error in the detection sequence. See the SEQ_STAT field to determine
+ *     the phase in which the error occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_ERR field. */
+#define USBDCD_RD_STATUS_ERR(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_ERR_MASK) >> USBDCD_STATUS_ERR_SHIFT)
+#define USBDCD_BRD_STATUS_ERR(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field TO[21] (RO)
+ *
+ * Indicates whether the detection sequence has passed the timeout threshhold.
+ *
+ * Values:
+ * - 0b0 - The detection sequence has not been running for over 1 s.
+ * - 0b1 - It has been over 1 s since the data pin contact was detected and
+ *     debounced.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_TO field. */
+#define USBDCD_RD_STATUS_TO(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_TO_MASK) >> USBDCD_STATUS_TO_SHIFT)
+#define USBDCD_BRD_STATUS_TO(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_TO_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field ACTIVE[22] (RO)
+ *
+ * Indicates whether the sequence is running.
+ *
+ * Values:
+ * - 0b0 - The sequence is not running.
+ * - 0b1 - The sequence is running.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_ACTIVE field. */
+#define USBDCD_RD_STATUS_ACTIVE(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_ACTIVE_MASK) >> USBDCD_STATUS_ACTIVE_SHIFT)
+#define USBDCD_BRD_STATUS_ACTIVE(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_ACTIVE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER0 - TIMER0 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER0 - TIMER0 register (RW)
+ *
+ * Reset value: 0x00100000U
+ *
+ * TIMER0 has an TSEQ_INIT field that represents the system latency in ms.
+ * Latency is measured from the time when VBUS goes active until the time system
+ * software initiates charger detection sequence in USBDCD module. When software sets
+ * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized
+ * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery
+ * Charging Specification requires the entire sequence, including TSEQ_INIT, to be
+ * completed in 1s or less.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER0 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER0(base)   (USBDCD_TIMER0_REG(base))
+#define USBDCD_WR_TIMER0(base, value) (USBDCD_TIMER0_REG(base) = (value))
+#define USBDCD_RMW_TIMER0(base, mask, value) (USBDCD_WR_TIMER0(base, (USBDCD_RD_TIMER0(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) |  (value)))
+#define USBDCD_CLR_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) & ~(value)))
+#define USBDCD_TOG_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER0 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO)
+ *
+ * Displays the amount of elapsed time since the event of setting the START bit
+ * plus the value of TSEQ_INIT. The timer is automatically initialized with the
+ * value of TSEQ_INIT before starting to count. This timer enables compliance with
+ * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging
+ * Specification. If the timer reaches the one second limit, the module triggers
+ * an interrupt and sets the error flag STATUS[ERR]. The timer continues
+ * counting throughout the charger detection sequence, even when control has been passed
+ * to software. As long as the module is active, the timer continues to count
+ * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not
+ * rollover to zero. A software reset clears the timer.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER0_TUNITCON field. */
+#define USBDCD_RD_TIMER0_TUNITCON(base) ((USBDCD_TIMER0_REG(base) & USBDCD_TIMER0_TUNITCON_MASK) >> USBDCD_TIMER0_TUNITCON_SHIFT)
+#define USBDCD_BRD_TIMER0_TUNITCON(base) (USBDCD_RD_TIMER0_TUNITCON(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW)
+ *
+ * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS
+ * goes active to the time system software initiates the charger detection
+ * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit
+ * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid
+ * values are 0-1023, but the USB Battery Charging Specification requires the
+ * entire sequence, including TSEQ_INIT, to be completed in 1s or less.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field. */
+#define USBDCD_RD_TIMER0_TSEQ_INIT(base) ((USBDCD_TIMER0_REG(base) & USBDCD_TIMER0_TSEQ_INIT_MASK) >> USBDCD_TIMER0_TSEQ_INIT_SHIFT)
+#define USBDCD_BRD_TIMER0_TSEQ_INIT(base) (USBDCD_RD_TIMER0_TSEQ_INIT(base))
+
+/*! @brief Set the TSEQ_INIT field to a new value. */
+#define USBDCD_WR_TIMER0_TSEQ_INIT(base, value) (USBDCD_RMW_TIMER0(base, USBDCD_TIMER0_TSEQ_INIT_MASK, USBDCD_TIMER0_TSEQ_INIT(value)))
+#define USBDCD_BWR_TIMER0_TSEQ_INIT(base, value) (USBDCD_WR_TIMER0_TSEQ_INIT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER1 - TIMER1 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER1 - TIMER1 register (RW)
+ *
+ * Reset value: 0x000A0028U
+ *
+ * TIMER1 contains timing parameters. Note that register values can be written
+ * that are not compliant with the USB Battery Charging Specification, so care
+ * should be taken when overwriting the default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER1 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER1(base)   (USBDCD_TIMER1_REG(base))
+#define USBDCD_WR_TIMER1(base, value) (USBDCD_TIMER1_REG(base) = (value))
+#define USBDCD_RMW_TIMER1(base, mask, value) (USBDCD_WR_TIMER1(base, (USBDCD_RD_TIMER1(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) |  (value)))
+#define USBDCD_CLR_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) & ~(value)))
+#define USBDCD_TOG_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER1 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW)
+ *
+ * This timing parameter is used after detection of the data pin. See "Charging
+ * Port Detection". Valid values are 1-1023, but the USB Battery Charging
+ * Specification requires a minimum value of 40 ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field. */
+#define USBDCD_RD_TIMER1_TVDPSRC_ON(base) ((USBDCD_TIMER1_REG(base) & USBDCD_TIMER1_TVDPSRC_ON_MASK) >> USBDCD_TIMER1_TVDPSRC_ON_SHIFT)
+#define USBDCD_BRD_TIMER1_TVDPSRC_ON(base) (USBDCD_RD_TIMER1_TVDPSRC_ON(base))
+
+/*! @brief Set the TVDPSRC_ON field to a new value. */
+#define USBDCD_WR_TIMER1_TVDPSRC_ON(base, value) (USBDCD_RMW_TIMER1(base, USBDCD_TIMER1_TVDPSRC_ON_MASK, USBDCD_TIMER1_TVDPSRC_ON(value)))
+#define USBDCD_BWR_TIMER1_TVDPSRC_ON(base, value) (USBDCD_WR_TIMER1_TVDPSRC_ON(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW)
+ *
+ * Sets the time period (ms) to debounce the D+ signal during the data pin
+ * contact detection phase. See "Debouncing the data pin contact" Valid values are
+ * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10
+ * ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field. */
+#define USBDCD_RD_TIMER1_TDCD_DBNC(base) ((USBDCD_TIMER1_REG(base) & USBDCD_TIMER1_TDCD_DBNC_MASK) >> USBDCD_TIMER1_TDCD_DBNC_SHIFT)
+#define USBDCD_BRD_TIMER1_TDCD_DBNC(base) (USBDCD_RD_TIMER1_TDCD_DBNC(base))
+
+/*! @brief Set the TDCD_DBNC field to a new value. */
+#define USBDCD_WR_TIMER1_TDCD_DBNC(base, value) (USBDCD_RMW_TIMER1(base, USBDCD_TIMER1_TDCD_DBNC_MASK, USBDCD_TIMER1_TDCD_DBNC(value)))
+#define USBDCD_BWR_TIMER1_TDCD_DBNC(base, value) (USBDCD_WR_TIMER1_TDCD_DBNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW)
+ *
+ * Reset value: 0x00280001U
+ *
+ * TIMER2_BC11 contains timing parameters for USB Battery Charging
+ * Specification, v1.1. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC11 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER2_BC11(base) (USBDCD_TIMER2_BC11_REG(base))
+#define USBDCD_WR_TIMER2_BC11(base, value) (USBDCD_TIMER2_BC11_REG(base) = (value))
+#define USBDCD_RMW_TIMER2_BC11(base, mask, value) (USBDCD_WR_TIMER2_BC11(base, (USBDCD_RD_TIMER2_BC11(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) |  (value)))
+#define USBDCD_CLR_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) & ~(value)))
+#define USBDCD_TOG_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after the device
+ * connects to the USB bus until checking the state of the D- line to determine the
+ * type of charging port. See "Charger Type Detection." Valid values are 1-15ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field. */
+#define USBDCD_RD_TIMER2_BC11_CHECK_DM(base) ((USBDCD_TIMER2_BC11_REG(base) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) >> USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)
+#define USBDCD_BRD_TIMER2_BC11_CHECK_DM(base) (USBDCD_RD_TIMER2_BC11_CHECK_DM(base))
+
+/*! @brief Set the CHECK_DM field to a new value. */
+#define USBDCD_WR_TIMER2_BC11_CHECK_DM(base, value) (USBDCD_RMW_TIMER2_BC11(base, USBDCD_TIMER2_BC11_CHECK_DM_MASK, USBDCD_TIMER2_BC11_CHECK_DM(value)))
+#define USBDCD_BWR_TIMER2_BC11_CHECK_DM(base, value) (USBDCD_WR_TIMER2_BC11_CHECK_DM(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW)
+ *
+ * Sets the time period (ms) that the module waits after charging port detection
+ * before system software must enable the D+ pullup to connect to the USB host.
+ * Valid values are 1-1023, but the USB Battery Charging Specification requires a
+ * minimum value of 40 ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field. */
+#define USBDCD_RD_TIMER2_BC11_TVDPSRC_CON(base) ((USBDCD_TIMER2_BC11_REG(base) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) >> USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)
+#define USBDCD_BRD_TIMER2_BC11_TVDPSRC_CON(base) (USBDCD_RD_TIMER2_BC11_TVDPSRC_CON(base))
+
+/*! @brief Set the TVDPSRC_CON field to a new value. */
+#define USBDCD_WR_TIMER2_BC11_TVDPSRC_CON(base, value) (USBDCD_RMW_TIMER2_BC11(base, USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK, USBDCD_TIMER2_BC11_TVDPSRC_CON(value)))
+#define USBDCD_BWR_TIMER2_BC11_TVDPSRC_CON(base, value) (USBDCD_WR_TIMER2_BC11_TVDPSRC_CON(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW)
+ *
+ * Reset value: 0x00010028U
+ *
+ * TIMER2_BC12 contains timing parameters for USB Battery Charging
+ * Specification, v1.2. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC12 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER2_BC12(base) (USBDCD_TIMER2_BC12_REG(base))
+#define USBDCD_WR_TIMER2_BC12(base, value) (USBDCD_TIMER2_BC12_REG(base) = (value))
+#define USBDCD_RMW_TIMER2_BC12(base, mask, value) (USBDCD_WR_TIMER2_BC12(base, (USBDCD_RD_TIMER2_BC12(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) |  (value)))
+#define USBDCD_CLR_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) & ~(value)))
+#define USBDCD_TOG_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid
+ * values are 0-40ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field. */
+#define USBDCD_RD_TIMER2_BC12_TVDMSRC_ON(base) ((USBDCD_TIMER2_BC12_REG(base) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) >> USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)
+#define USBDCD_BRD_TIMER2_BC12_TVDMSRC_ON(base) (USBDCD_RD_TIMER2_BC12_TVDMSRC_ON(base))
+
+/*! @brief Set the TVDMSRC_ON field to a new value. */
+#define USBDCD_WR_TIMER2_BC12_TVDMSRC_ON(base, value) (USBDCD_RMW_TIMER2_BC12(base, USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK, USBDCD_TIMER2_BC12_TVDMSRC_ON(value)))
+#define USBDCD_BWR_TIMER2_BC12_TVDMSRC_ON(base, value) (USBDCD_WR_TIMER2_BC12_TVDMSRC_ON(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after primary detection
+ * before start to secondary detection. Valid values are 1-1023ms. Default is
+ * 1ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field. */
+#define USBDCD_RD_TIMER2_BC12_TWAIT_AFTER_PRD(base) ((USBDCD_TIMER2_BC12_REG(base) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) >> USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)
+#define USBDCD_BRD_TIMER2_BC12_TWAIT_AFTER_PRD(base) (USBDCD_RD_TIMER2_BC12_TWAIT_AFTER_PRD(base))
+
+/*! @brief Set the TWAIT_AFTER_PRD field to a new value. */
+#define USBDCD_WR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value) (USBDCD_RMW_TIMER2_BC12(base, USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK, USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(value)))
+#define USBDCD_BWR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value) (USBDCD_WR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value))
+/*@}*/
+
+/*
+ * MK64F12 VREF
+ *
+ * Voltage Reference
+ *
+ * Registers defined in this header file:
+ * - VREF_TRM - VREF Trim Register
+ * - VREF_SC - VREF Status and Control Register
+ */
+
+#define VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
+#define VREF_IDX (0U) /*!< Instance number for VREF. */
+
+/*******************************************************************************
+ * VREF_TRM - VREF Trim Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_TRM - VREF Trim Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains bits that contain the trim data for the Voltage
+ * Reference.
+ */
+/*!
+ * @name Constants and macros for entire VREF_TRM register
+ */
+/*@{*/
+#define VREF_RD_TRM(base)        (VREF_TRM_REG(base))
+#define VREF_WR_TRM(base, value) (VREF_TRM_REG(base) = (value))
+#define VREF_RMW_TRM(base, mask, value) (VREF_WR_TRM(base, (VREF_RD_TRM(base) & ~(mask)) | (value)))
+#define VREF_SET_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) |  (value)))
+#define VREF_CLR_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) & ~(value)))
+#define VREF_TOG_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_TRM bitfields
+ */
+
+/*!
+ * @name Register VREF_TRM, field TRIM[5:0] (RW)
+ *
+ * These bits change the resulting VREF by approximately +/- 0.5 mV for each
+ * step. Min = minimum and max = maximum voltage reference output. For minimum and
+ * maximum voltage reference output values, refer to the Data Sheet for this chip.
+ *
+ * Values:
+ * - 0b000000 - Min
+ * - 0b111111 - Max
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_TRIM field. */
+#define VREF_RD_TRM_TRIM(base) ((VREF_TRM_REG(base) & VREF_TRM_TRIM_MASK) >> VREF_TRM_TRIM_SHIFT)
+#define VREF_BRD_TRM_TRIM(base) (VREF_RD_TRM_TRIM(base))
+
+/*! @brief Set the TRIM field to a new value. */
+#define VREF_WR_TRM_TRIM(base, value) (VREF_RMW_TRM(base, VREF_TRM_TRIM_MASK, VREF_TRM_TRIM(value)))
+#define VREF_BWR_TRM_TRIM(base, value) (VREF_WR_TRM_TRIM(base, value))
+/*@}*/
+
+/*!
+ * @name Register VREF_TRM, field CHOPEN[6] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0b0 - Chop oscillator is disabled.
+ * - 0b1 - Chop oscillator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_CHOPEN field. */
+#define VREF_RD_TRM_CHOPEN(base) ((VREF_TRM_REG(base) & VREF_TRM_CHOPEN_MASK) >> VREF_TRM_CHOPEN_SHIFT)
+#define VREF_BRD_TRM_CHOPEN(base) (BITBAND_ACCESS8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT))
+
+/*! @brief Set the CHOPEN field to a new value. */
+#define VREF_WR_TRM_CHOPEN(base, value) (VREF_RMW_TRM(base, VREF_TRM_CHOPEN_MASK, VREF_TRM_CHOPEN(value)))
+#define VREF_BWR_TRM_CHOPEN(base, value) (BITBAND_ACCESS8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * VREF_SC - VREF Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_SC - VREF Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the control bits used to enable the internal voltage
+ * reference and to select the buffer mode to be used.
+ */
+/*!
+ * @name Constants and macros for entire VREF_SC register
+ */
+/*@{*/
+#define VREF_RD_SC(base)         (VREF_SC_REG(base))
+#define VREF_WR_SC(base, value)  (VREF_SC_REG(base) = (value))
+#define VREF_RMW_SC(base, mask, value) (VREF_WR_SC(base, (VREF_RD_SC(base) & ~(mask)) | (value)))
+#define VREF_SET_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) |  (value)))
+#define VREF_CLR_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) & ~(value)))
+#define VREF_TOG_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_SC bitfields
+ */
+
+/*!
+ * @name Register VREF_SC, field MODE_LV[1:0] (RW)
+ *
+ * These bits select the buffer modes for the Voltage Reference module.
+ *
+ * Values:
+ * - 0b00 - Bandgap on only, for stabilization and startup
+ * - 0b01 - High power buffer mode enabled
+ * - 0b10 - Low-power buffer mode enabled
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_MODE_LV field. */
+#define VREF_RD_SC_MODE_LV(base) ((VREF_SC_REG(base) & VREF_SC_MODE_LV_MASK) >> VREF_SC_MODE_LV_SHIFT)
+#define VREF_BRD_SC_MODE_LV(base) (VREF_RD_SC_MODE_LV(base))
+
+/*! @brief Set the MODE_LV field to a new value. */
+#define VREF_WR_SC_MODE_LV(base, value) (VREF_RMW_SC(base, VREF_SC_MODE_LV_MASK, VREF_SC_MODE_LV(value)))
+#define VREF_BWR_SC_MODE_LV(base, value) (VREF_WR_SC_MODE_LV(base, value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFST[2] (RO)
+ *
+ * This bit indicates that the bandgap reference within the Voltage Reference
+ * module has completed its startup and stabilization.
+ *
+ * Values:
+ * - 0b0 - The module is disabled or not stable.
+ * - 0b1 - The module is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFST field. */
+#define VREF_RD_SC_VREFST(base) ((VREF_SC_REG(base) & VREF_SC_VREFST_MASK) >> VREF_SC_VREFST_SHIFT)
+#define VREF_BRD_SC_VREFST(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field ICOMPEN[5] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_ICOMPEN field. */
+#define VREF_RD_SC_ICOMPEN(base) ((VREF_SC_REG(base) & VREF_SC_ICOMPEN_MASK) >> VREF_SC_ICOMPEN_SHIFT)
+#define VREF_BRD_SC_ICOMPEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT))
+
+/*! @brief Set the ICOMPEN field to a new value. */
+#define VREF_WR_SC_ICOMPEN(base, value) (VREF_RMW_SC(base, VREF_SC_ICOMPEN_MASK, VREF_SC_ICOMPEN(value)))
+#define VREF_BWR_SC_ICOMPEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field REGEN[6] (RW)
+ *
+ * This bit is used to enable the internal 1.75 V regulator to produce a
+ * constant internal voltage supply in order to reduce the sensitivity to external
+ * supply noise and variation. If it is desired to keep the regulator enabled in very
+ * low power modes, refer to the Chip Configuration details for a description on
+ * how this can be achieved. This bit is set during factory trimming of the VREF
+ * voltage. This bit should be written to 1 to achieve the performance stated in
+ * the data sheet.
+ *
+ * Values:
+ * - 0b0 - Internal 1.75 V regulator is disabled.
+ * - 0b1 - Internal 1.75 V regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_REGEN field. */
+#define VREF_RD_SC_REGEN(base) ((VREF_SC_REG(base) & VREF_SC_REGEN_MASK) >> VREF_SC_REGEN_SHIFT)
+#define VREF_BRD_SC_REGEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT))
+
+/*! @brief Set the REGEN field to a new value. */
+#define VREF_WR_SC_REGEN(base, value) (VREF_RMW_SC(base, VREF_SC_REGEN_MASK, VREF_SC_REGEN(value)))
+#define VREF_BWR_SC_REGEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFEN[7] (RW)
+ *
+ * This bit is used to enable the bandgap reference within the Voltage Reference
+ * module. After the VREF is enabled, turning off the clock to the VREF module
+ * via the corresponding clock gate register will not disable the VREF. VREF must
+ * be disabled via this VREFEN bit.
+ *
+ * Values:
+ * - 0b0 - The module is disabled.
+ * - 0b1 - The module is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFEN field. */
+#define VREF_RD_SC_VREFEN(base) ((VREF_SC_REG(base) & VREF_SC_VREFEN_MASK) >> VREF_SC_VREFEN_SHIFT)
+#define VREF_BRD_SC_VREFEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT))
+
+/*! @brief Set the VREFEN field to a new value. */
+#define VREF_WR_SC_VREFEN(base, value) (VREF_RMW_SC(base, VREF_SC_VREFEN_MASK, VREF_SC_VREFEN(value)))
+#define VREF_BWR_SC_VREFEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 WDOG
+ *
+ * Generation 2008 Watchdog Timer
+ *
+ * Registers defined in this header file:
+ * - WDOG_STCTRLH - Watchdog Status and Control Register High
+ * - WDOG_STCTRLL - Watchdog Status and Control Register Low
+ * - WDOG_TOVALH - Watchdog Time-out Value Register High
+ * - WDOG_TOVALL - Watchdog Time-out Value Register Low
+ * - WDOG_WINH - Watchdog Window Register High
+ * - WDOG_WINL - Watchdog Window Register Low
+ * - WDOG_REFRESH - Watchdog Refresh register
+ * - WDOG_UNLOCK - Watchdog Unlock register
+ * - WDOG_TMROUTH - Watchdog Timer Output Register High
+ * - WDOG_TMROUTL - Watchdog Timer Output Register Low
+ * - WDOG_RSTCNT - Watchdog Reset Count register
+ * - WDOG_PRESC - Watchdog Prescaler register
+ */
+
+#define WDOG_INSTANCE_COUNT (1U) /*!< Number of instances of the WDOG module. */
+#define WDOG_IDX (0U) /*!< Instance number for WDOG. */
+
+/*******************************************************************************
+ * WDOG_STCTRLH - Watchdog Status and Control Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
+ *
+ * Reset value: 0x01D3U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLH register
+ */
+/*@{*/
+#define WDOG_RD_STCTRLH(base)    (WDOG_STCTRLH_REG(base))
+#define WDOG_WR_STCTRLH(base, value) (WDOG_STCTRLH_REG(base) = (value))
+#define WDOG_RMW_STCTRLH(base, mask, value) (WDOG_WR_STCTRLH(base, (WDOG_RD_STCTRLH(base) & ~(mask)) | (value)))
+#define WDOG_SET_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) |  (value)))
+#define WDOG_CLR_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) & ~(value)))
+#define WDOG_TOG_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_STCTRLH bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
+ *
+ * Enables or disables the WDOG's operation. In the disabled state, the watchdog
+ * timer is kept in the reset state, but the other exception conditions can
+ * still trigger a reset/interrupt. A change in the value of this bit must be held
+ * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled.
+ * - 0b1 - WDOG is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. */
+#define WDOG_RD_STCTRLH_WDOGEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WDOGEN_MASK) >> WDOG_STCTRLH_WDOGEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WDOGEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WDOGEN_SHIFT))
+
+/*! @brief Set the WDOGEN field to a new value. */
+#define WDOG_WR_STCTRLH_WDOGEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WDOGEN_MASK, WDOG_STCTRLH_WDOGEN(value)))
+#define WDOG_BWR_STCTRLH_WDOGEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WDOGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
+ *
+ * Selects clock source for the WDOG timer and other internal timing operations.
+ *
+ * Values:
+ * - 0b0 - WDOG clock sourced from LPO .
+ * - 0b1 - WDOG clock sourced from alternate clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. */
+#define WDOG_RD_STCTRLH_CLKSRC(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_CLKSRC_MASK) >> WDOG_STCTRLH_CLKSRC_SHIFT)
+#define WDOG_BRD_STCTRLH_CLKSRC(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_CLKSRC_SHIFT))
+
+/*! @brief Set the CLKSRC field to a new value. */
+#define WDOG_WR_STCTRLH_CLKSRC(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_CLKSRC_MASK, WDOG_STCTRLH_CLKSRC(value)))
+#define WDOG_BWR_STCTRLH_CLKSRC(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_CLKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
+ *
+ * Used to enable the debug breadcrumbs feature. A change in this bit is updated
+ * immediately, as opposed to updating after WCT.
+ *
+ * Values:
+ * - 0b0 - WDOG time-out generates reset only.
+ * - 0b1 - WDOG time-out initially generates an interrupt. After WCT, it
+ *     generates a reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. */
+#define WDOG_RD_STCTRLH_IRQRSTEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_IRQRSTEN_MASK) >> WDOG_STCTRLH_IRQRSTEN_SHIFT)
+#define WDOG_BRD_STCTRLH_IRQRSTEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_IRQRSTEN_SHIFT))
+
+/*! @brief Set the IRQRSTEN field to a new value. */
+#define WDOG_WR_STCTRLH_IRQRSTEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_IRQRSTEN_MASK, WDOG_STCTRLH_IRQRSTEN(value)))
+#define WDOG_BWR_STCTRLH_IRQRSTEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_IRQRSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
+ *
+ * Enables Windowing mode.
+ *
+ * Values:
+ * - 0b0 - Windowing mode is disabled.
+ * - 0b1 - Windowing mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WINEN field. */
+#define WDOG_RD_STCTRLH_WINEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WINEN_MASK) >> WDOG_STCTRLH_WINEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WINEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WINEN_SHIFT))
+
+/*! @brief Set the WINEN field to a new value. */
+#define WDOG_WR_STCTRLH_WINEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WINEN_MASK, WDOG_STCTRLH_WINEN(value)))
+#define WDOG_BWR_STCTRLH_WINEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WINEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
+ *
+ * Enables updates to watchdog write-once registers, after the reset-triggered
+ * initial configuration window (WCT) closes, through unlock sequence.
+ *
+ * Values:
+ * - 0b0 - No further updates allowed to WDOG write-once registers.
+ * - 0b1 - WDOG write-once registers can be unlocked for updating.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. */
+#define WDOG_RD_STCTRLH_ALLOWUPDATE(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_ALLOWUPDATE_MASK) >> WDOG_STCTRLH_ALLOWUPDATE_SHIFT)
+#define WDOG_BRD_STCTRLH_ALLOWUPDATE(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_ALLOWUPDATE_SHIFT))
+
+/*! @brief Set the ALLOWUPDATE field to a new value. */
+#define WDOG_WR_STCTRLH_ALLOWUPDATE(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_ALLOWUPDATE_MASK, WDOG_STCTRLH_ALLOWUPDATE(value)))
+#define WDOG_BWR_STCTRLH_ALLOWUPDATE(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_ALLOWUPDATE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
+ *
+ * Enables or disables WDOG in Debug mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Debug mode.
+ * - 0b1 - WDOG is enabled in CPU Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_DBGEN field. */
+#define WDOG_RD_STCTRLH_DBGEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_DBGEN_MASK) >> WDOG_STCTRLH_DBGEN_SHIFT)
+#define WDOG_BRD_STCTRLH_DBGEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DBGEN_SHIFT))
+
+/*! @brief Set the DBGEN field to a new value. */
+#define WDOG_WR_STCTRLH_DBGEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_DBGEN_MASK, WDOG_STCTRLH_DBGEN(value)))
+#define WDOG_BWR_STCTRLH_DBGEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DBGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
+ *
+ * Enables or disables WDOG in Stop mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Stop mode.
+ * - 0b1 - WDOG is enabled in CPU Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_STOPEN field. */
+#define WDOG_RD_STCTRLH_STOPEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_STOPEN_MASK) >> WDOG_STCTRLH_STOPEN_SHIFT)
+#define WDOG_BRD_STCTRLH_STOPEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_STOPEN_SHIFT))
+
+/*! @brief Set the STOPEN field to a new value. */
+#define WDOG_WR_STCTRLH_STOPEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_STOPEN_MASK, WDOG_STCTRLH_STOPEN(value)))
+#define WDOG_BWR_STCTRLH_STOPEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_STOPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
+ *
+ * Enables or disables WDOG in Wait mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Wait mode.
+ * - 0b1 - WDOG is enabled in CPU Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WAITEN field. */
+#define WDOG_RD_STCTRLH_WAITEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WAITEN_MASK) >> WDOG_STCTRLH_WAITEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WAITEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WAITEN_SHIFT))
+
+/*! @brief Set the WAITEN field to a new value. */
+#define WDOG_WR_STCTRLH_WAITEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WAITEN_MASK, WDOG_STCTRLH_WAITEN(value)))
+#define WDOG_BWR_STCTRLH_WAITEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WAITEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
+ *
+ * Puts the watchdog in the functional test mode. In this mode, the watchdog
+ * timer and the associated compare and reset generation logic is tested for correct
+ * operation. The clock for the timer is switched from the main watchdog clock
+ * to the fast clock input for watchdog functional test. The TESTSEL bit selects
+ * the test to be run.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. */
+#define WDOG_RD_STCTRLH_TESTWDOG(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_TESTWDOG_MASK) >> WDOG_STCTRLH_TESTWDOG_SHIFT)
+#define WDOG_BRD_STCTRLH_TESTWDOG(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTWDOG_SHIFT))
+
+/*! @brief Set the TESTWDOG field to a new value. */
+#define WDOG_WR_STCTRLH_TESTWDOG(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_TESTWDOG_MASK, WDOG_STCTRLH_TESTWDOG(value)))
+#define WDOG_BWR_STCTRLH_TESTWDOG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTWDOG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
+ *
+ * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
+ * timer.
+ *
+ * Values:
+ * - 0b0 - Quick test. The timer runs in normal operation. You can load a small
+ *     time-out value to do a quick test.
+ * - 0b1 - Byte test. Puts the timer in the byte test mode where individual
+ *     bytes of the timer are enabled for operation and are compared for time-out
+ *     against the corresponding byte of the programmed time-out value. Select the
+ *     byte through BYTESEL[1:0] for testing.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. */
+#define WDOG_RD_STCTRLH_TESTSEL(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_TESTSEL_MASK) >> WDOG_STCTRLH_TESTSEL_SHIFT)
+#define WDOG_BRD_STCTRLH_TESTSEL(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTSEL_SHIFT))
+
+/*! @brief Set the TESTSEL field to a new value. */
+#define WDOG_WR_STCTRLH_TESTSEL(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_TESTSEL_MASK, WDOG_STCTRLH_TESTSEL(value)))
+#define WDOG_BWR_STCTRLH_TESTSEL(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
+ *
+ * This 2-bit field selects the byte to be tested when the watchdog is in the
+ * byte test mode.
+ *
+ * Values:
+ * - 0b00 - Byte 0 selected
+ * - 0b01 - Byte 1 selected
+ * - 0b10 - Byte 2 selected
+ * - 0b11 - Byte 3 selected
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. */
+#define WDOG_RD_STCTRLH_BYTESEL(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_BYTESEL_MASK) >> WDOG_STCTRLH_BYTESEL_SHIFT)
+#define WDOG_BRD_STCTRLH_BYTESEL(base) (WDOG_RD_STCTRLH_BYTESEL(base))
+
+/*! @brief Set the BYTESEL field to a new value. */
+#define WDOG_WR_STCTRLH_BYTESEL(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_BYTESEL_MASK, WDOG_STCTRLH_BYTESEL(value)))
+#define WDOG_BWR_STCTRLH_BYTESEL(base, value) (WDOG_WR_STCTRLH_BYTESEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
+ *
+ * Allows the WDOG's functional test mode to be disabled permanently. After it
+ * is set, it can only be cleared by a reset. It cannot be unlocked for editing
+ * after it is set.
+ *
+ * Values:
+ * - 0b0 - WDOG functional test mode is not disabled.
+ * - 0b1 - WDOG functional test mode is disabled permanently until reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. */
+#define WDOG_RD_STCTRLH_DISTESTWDOG(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_DISTESTWDOG_MASK) >> WDOG_STCTRLH_DISTESTWDOG_SHIFT)
+#define WDOG_BRD_STCTRLH_DISTESTWDOG(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DISTESTWDOG_SHIFT))
+
+/*! @brief Set the DISTESTWDOG field to a new value. */
+#define WDOG_WR_STCTRLH_DISTESTWDOG(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_DISTESTWDOG_MASK, WDOG_STCTRLH_DISTESTWDOG(value)))
+#define WDOG_BWR_STCTRLH_DISTESTWDOG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DISTESTWDOG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_STCTRLL - Watchdog Status and Control Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
+ *
+ * Reset value: 0x0001U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLL register
+ */
+/*@{*/
+#define WDOG_RD_STCTRLL(base)    (WDOG_STCTRLL_REG(base))
+#define WDOG_WR_STCTRLL(base, value) (WDOG_STCTRLL_REG(base) = (value))
+#define WDOG_RMW_STCTRLL(base, mask, value) (WDOG_WR_STCTRLL(base, (WDOG_RD_STCTRLL(base) & ~(mask)) | (value)))
+#define WDOG_SET_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) |  (value)))
+#define WDOG_CLR_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) & ~(value)))
+#define WDOG_TOG_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_STCTRLL bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
+ *
+ * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
+ * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
+ * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
+ * bit. It also gets cleared on a system reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLL_INTFLG field. */
+#define WDOG_RD_STCTRLL_INTFLG(base) ((WDOG_STCTRLL_REG(base) & WDOG_STCTRLL_INTFLG_MASK) >> WDOG_STCTRLL_INTFLG_SHIFT)
+#define WDOG_BRD_STCTRLL_INTFLG(base) (BITBAND_ACCESS16(&WDOG_STCTRLL_REG(base), WDOG_STCTRLL_INTFLG_SHIFT))
+
+/*! @brief Set the INTFLG field to a new value. */
+#define WDOG_WR_STCTRLL_INTFLG(base, value) (WDOG_RMW_STCTRLL(base, WDOG_STCTRLL_INTFLG_MASK, WDOG_STCTRLL_INTFLG(value)))
+#define WDOG_BWR_STCTRLL_INTFLG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLL_REG(base), WDOG_STCTRLL_INTFLG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TOVALH - Watchdog Time-out Value Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
+ *
+ * Reset value: 0x004CU
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TOVALH register
+ */
+/*@{*/
+#define WDOG_RD_TOVALH(base)     (WDOG_TOVALH_REG(base))
+#define WDOG_WR_TOVALH(base, value) (WDOG_TOVALH_REG(base) = (value))
+#define WDOG_RMW_TOVALH(base, mask, value) (WDOG_WR_TOVALH(base, (WDOG_RD_TOVALH(base) & ~(mask)) | (value)))
+#define WDOG_SET_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) |  (value)))
+#define WDOG_CLR_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) & ~(value)))
+#define WDOG_TOG_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TOVALL - Watchdog Time-out Value Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
+ *
+ * Reset value: 0x4B4CU
+ *
+ * The time-out value of the watchdog must be set to a minimum of four watchdog
+ * clock cycles. This is to take into account the delay in new settings taking
+ * effect in the watchdog clock domain.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TOVALL register
+ */
+/*@{*/
+#define WDOG_RD_TOVALL(base)     (WDOG_TOVALL_REG(base))
+#define WDOG_WR_TOVALL(base, value) (WDOG_TOVALL_REG(base) = (value))
+#define WDOG_RMW_TOVALL(base, mask, value) (WDOG_WR_TOVALL(base, (WDOG_RD_TOVALL(base) & ~(mask)) | (value)))
+#define WDOG_SET_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) |  (value)))
+#define WDOG_CLR_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) & ~(value)))
+#define WDOG_TOG_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_WINH - Watchdog Window Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_WINH - Watchdog Window Register High (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_WINH register
+ */
+/*@{*/
+#define WDOG_RD_WINH(base)       (WDOG_WINH_REG(base))
+#define WDOG_WR_WINH(base, value) (WDOG_WINH_REG(base) = (value))
+#define WDOG_RMW_WINH(base, mask, value) (WDOG_WR_WINH(base, (WDOG_RD_WINH(base) & ~(mask)) | (value)))
+#define WDOG_SET_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) |  (value)))
+#define WDOG_CLR_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) & ~(value)))
+#define WDOG_TOG_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_WINL - Watchdog Window Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_WINL - Watchdog Window Register Low (RW)
+ *
+ * Reset value: 0x0010U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_WINL register
+ */
+/*@{*/
+#define WDOG_RD_WINL(base)       (WDOG_WINL_REG(base))
+#define WDOG_WR_WINL(base, value) (WDOG_WINL_REG(base) = (value))
+#define WDOG_RMW_WINL(base, mask, value) (WDOG_WR_WINL(base, (WDOG_RD_WINL(base) & ~(mask)) | (value)))
+#define WDOG_SET_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) |  (value)))
+#define WDOG_CLR_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) & ~(value)))
+#define WDOG_TOG_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_REFRESH - Watchdog Refresh register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_REFRESH - Watchdog Refresh register (RW)
+ *
+ * Reset value: 0xB480U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_REFRESH register
+ */
+/*@{*/
+#define WDOG_RD_REFRESH(base)    (WDOG_REFRESH_REG(base))
+#define WDOG_WR_REFRESH(base, value) (WDOG_REFRESH_REG(base) = (value))
+#define WDOG_RMW_REFRESH(base, mask, value) (WDOG_WR_REFRESH(base, (WDOG_RD_REFRESH(base) & ~(mask)) | (value)))
+#define WDOG_SET_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) |  (value)))
+#define WDOG_CLR_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) & ~(value)))
+#define WDOG_TOG_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_UNLOCK - Watchdog Unlock register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_UNLOCK - Watchdog Unlock register (RW)
+ *
+ * Reset value: 0xD928U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_UNLOCK register
+ */
+/*@{*/
+#define WDOG_RD_UNLOCK(base)     (WDOG_UNLOCK_REG(base))
+#define WDOG_WR_UNLOCK(base, value) (WDOG_UNLOCK_REG(base) = (value))
+#define WDOG_RMW_UNLOCK(base, mask, value) (WDOG_WR_UNLOCK(base, (WDOG_RD_UNLOCK(base) & ~(mask)) | (value)))
+#define WDOG_SET_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) |  (value)))
+#define WDOG_CLR_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) & ~(value)))
+#define WDOG_TOG_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TMROUTH - Watchdog Timer Output Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTH register
+ */
+/*@{*/
+#define WDOG_RD_TMROUTH(base)    (WDOG_TMROUTH_REG(base))
+#define WDOG_WR_TMROUTH(base, value) (WDOG_TMROUTH_REG(base) = (value))
+#define WDOG_RMW_TMROUTH(base, mask, value) (WDOG_WR_TMROUTH(base, (WDOG_RD_TMROUTH(base) & ~(mask)) | (value)))
+#define WDOG_SET_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) |  (value)))
+#define WDOG_CLR_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) & ~(value)))
+#define WDOG_TOG_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TMROUTL - Watchdog Timer Output Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
+ * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
+ * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
+ * the watchdog timer.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTL register
+ */
+/*@{*/
+#define WDOG_RD_TMROUTL(base)    (WDOG_TMROUTL_REG(base))
+#define WDOG_WR_TMROUTL(base, value) (WDOG_TMROUTL_REG(base) = (value))
+#define WDOG_RMW_TMROUTL(base, mask, value) (WDOG_WR_TMROUTL(base, (WDOG_RD_TMROUTL(base) & ~(mask)) | (value)))
+#define WDOG_SET_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) |  (value)))
+#define WDOG_CLR_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) & ~(value)))
+#define WDOG_TOG_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_RSTCNT - Watchdog Reset Count register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_RSTCNT - Watchdog Reset Count register (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_RSTCNT register
+ */
+/*@{*/
+#define WDOG_RD_RSTCNT(base)     (WDOG_RSTCNT_REG(base))
+#define WDOG_WR_RSTCNT(base, value) (WDOG_RSTCNT_REG(base) = (value))
+#define WDOG_RMW_RSTCNT(base, mask, value) (WDOG_WR_RSTCNT(base, (WDOG_RD_RSTCNT(base) & ~(mask)) | (value)))
+#define WDOG_SET_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) |  (value)))
+#define WDOG_CLR_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) & ~(value)))
+#define WDOG_TOG_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_PRESC - Watchdog Prescaler register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_PRESC - Watchdog Prescaler register (RW)
+ *
+ * Reset value: 0x0400U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_PRESC register
+ */
+/*@{*/
+#define WDOG_RD_PRESC(base)      (WDOG_PRESC_REG(base))
+#define WDOG_WR_PRESC(base, value) (WDOG_PRESC_REG(base) = (value))
+#define WDOG_RMW_PRESC(base, mask, value) (WDOG_WR_PRESC(base, (WDOG_RD_PRESC(base) & ~(mask)) | (value)))
+#define WDOG_SET_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) |  (value)))
+#define WDOG_CLR_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) & ~(value)))
+#define WDOG_TOG_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_PRESC bitfields
+ */
+
+/*!
+ * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
+ *
+ * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
+ * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
+ * 1) to provide the prescaled WDOG_CLK.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_PRESC_PRESCVAL field. */
+#define WDOG_RD_PRESC_PRESCVAL(base) ((WDOG_PRESC_REG(base) & WDOG_PRESC_PRESCVAL_MASK) >> WDOG_PRESC_PRESCVAL_SHIFT)
+#define WDOG_BRD_PRESC_PRESCVAL(base) (WDOG_RD_PRESC_PRESCVAL(base))
+
+/*! @brief Set the PRESCVAL field to a new value. */
+#define WDOG_WR_PRESC_PRESCVAL(base, value) (WDOG_RMW_PRESC(base, WDOG_PRESC_PRESCVAL_MASK, WDOG_PRESC_PRESCVAL(value)))
+#define WDOG_BWR_PRESC_PRESCVAL(base, value) (WDOG_WR_PRESC_PRESCVAL(base, value))
+/*@}*/
+
+/* Instance numbers for core modules */
+#define JTAG_IDX (0) /*!< Instance number for JTAG. */
+#define TPIU_IDX (0) /*!< Instance number for TPIU. */
+#define SCB_IDX (0) /*!< Instance number for SCB. */
+#define CoreDebug_IDX (0) /*!< Instance number for CoreDebug. */
+
+#if defined(__IAR_SYSTEMS_ICC__)
+  /* Restore checking of "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)" */
+  #pragma diag_default=pm008
+#endif
+
+#endif /* __MK64F12_EXTENSION_H__ */
+/* EOF */
diff --git a/Workspace/Interrupt/SDK/platform/devices/MK64F12/include/MK64F12_features.h b/Workspace/Interrupt/SDK/platform/devices/MK64F12/include/MK64F12_features.h
new file mode 100644
index 0000000..9c826df
--- /dev/null
+++ b/Workspace/Interrupt/SDK/platform/devices/MK64F12/include/MK64F12_features.h
@@ -0,0 +1,1901 @@
+/*
+** ###################################################################
+**     Version:             rev. 2.14, 2015-06-08
+**     Build:               b150715
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-01-30)
+**         Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.6 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.7 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.8 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.9 (2015-01-21)
+**         Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
+**     - rev. 2.10 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**     - rev. 2.11 (2015-05-19)
+**         FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
+**         Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
+**         Added features for PDB and PORT.
+**     - rev. 2.12 (2015-05-25)
+**         Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
+**     - rev. 2.13 (2015-05-27)
+**         Several USB features added.
+**     - rev. 2.14 (2015-06-08)
+**         FTM features BUS_CLOCK and FAST_CLOCK removed.
+**
+** ###################################################################
+*/
+
+#if !defined(__FSL_MK64F12_FEATURES_H__)
+#define __FSL_MK64F12_FEATURES_H__
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* FLEXCAN module features */
+
+/* @brief Message buffer size */
+#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
+/* @brief Has doze mode support (register bit field MCR[DOZE]). */
+#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
+/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
+#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
+/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
+/* @brief Has extended bit timing register (register CBT). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
+/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
+#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
+/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
+#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
+/* @brief Number of interrupt vectors. */
+#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* SOC module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief ACMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_ACMP_COUNT (0)
+    /* @brief ADC16 availability on the SoC. */
+    #define FSL_FEATURE_SOC_ADC16_COUNT (2)
+    /* @brief AFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_AFE_COUNT (0)
+    /* @brief AIPS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AIPS_COUNT (2)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (0)
+    /* @brief AXBS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AXBS_COUNT (1)
+    /* @brief CADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CADC_COUNT (0)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief MMCAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
+    /* @brief CMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMP_COUNT (3)
+    /* @brief CMT availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMT_COUNT (1)
+    /* @brief CNC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CNC_COUNT (0)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief DAC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DAC_COUNT (2)
+    /* @brief DCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DCDC_COUNT (0)
+    /* @brief DDR availability on the SoC. */
+    #define FSL_FEATURE_SOC_DDR_COUNT (0)
+    /* @brief DMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMA_COUNT (0)
+    /* @brief DMAMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+    /* @brief DRY availability on the SoC. */
+    #define FSL_FEATURE_SOC_DRY_COUNT (0)
+    /* @brief DSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_DSPI_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EMVSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+    /* @brief ENC availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENC_COUNT (0)
+    /* @brief ENET availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENET_COUNT (1)
+    /* @brief EWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EWM_COUNT (1)
+    /* @brief FB availability on the SoC. */
+    #define FSL_FEATURE_SOC_FB_COUNT (1)
+    /* @brief FGPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+    /* @brief FLEXIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FSKDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+    /* @brief FTFA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFA_COUNT (0)
+    /* @brief FTFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFE_COUNT (1)
+    /* @brief FTFL availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFL_COUNT (0)
+    /* @brief FTM availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTM_COUNT (4)
+    /* @brief FTMRA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+    /* @brief FTMRE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+    /* @brief FTMRH availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief HSADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_HSADC_COUNT (0)
+    /* @brief I2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2C_COUNT (3)
+    /* @brief I2S availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2S_COUNT (1)
+    /* @brief ICS availability on the SoC. */
+    #define FSL_FEATURE_SOC_ICS_COUNT (0)
+    /* @brief IRQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_IRQ_COUNT (0)
+    /* @brief KBI availability on the SoC. */
+    #define FSL_FEATURE_SOC_KBI_COUNT (0)
+    /* @brief SLCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_SLCD_COUNT (0)
+    /* @brief LCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LCDC_COUNT (0)
+    /* @brief LDO availability on the SoC. */
+    #define FSL_FEATURE_SOC_LDO_COUNT (0)
+    /* @brief LLWU availability on the SoC. */
+    #define FSL_FEATURE_SOC_LLWU_COUNT (1)
+    /* @brief LMEM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LMEM_COUNT (0)
+    /* @brief LPSCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPTPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (0)
+    /* @brief LTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LTC_COUNT (0)
+    /* @brief MC availability on the SoC. */
+    #define FSL_FEATURE_SOC_MC_COUNT (0)
+    /* @brief MCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCG_COUNT (1)
+    /* @brief MCGLITE availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+    /* @brief MCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCM_COUNT (1)
+    /* @brief MMAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMAU_COUNT (0)
+    /* @brief MMDVSQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+    /* @brief MPU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MPU_COUNT (1)
+    /* @brief MSCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+    /* @brief MTB availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTB_COUNT (0)
+    /* @brief MTBDWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
+    /* @brief NFC availability on the SoC. */
+    #define FSL_FEATURE_SOC_NFC_COUNT (0)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+    /* @brief OSC availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSC_COUNT (1)
+    /* @brief OTFAD availability on the SoC. */
+    #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+    /* @brief PDB availability on the SoC. */
+    #define FSL_FEATURE_SOC_PDB_COUNT (1)
+    /* @brief PGA availability on the SoC. */
+    #define FSL_FEATURE_SOC_PGA_COUNT (0)
+    /* @brief PIT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PIT_COUNT (1)
+    /* @brief PMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_PMC_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (0)
+    /* @brief PWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWT_COUNT (0)
+    /* @brief QuadSPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+    /* @brief RCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RCM_COUNT (1)
+    /* @brief RFSYS availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+    /* @brief RFVBAT availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+    /* @brief RNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNG_COUNT (1)
+    /* @brief RNGB availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNGB_COUNT (0)
+    /* @brief ROM availability on the SoC. */
+    #define FSL_FEATURE_SOC_ROM_COUNT (0)
+    /* @brief RSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RSIM_COUNT (0)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCI_COUNT (0)
+    /* @brief SDHC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDHC_COUNT (1)
+    /* @brief SDRAM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+    /* @brief SIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SIM_COUNT (1)
+    /* @brief SMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMC_COUNT (1)
+    /* @brief SPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPI_COUNT (0)
+    /* @brief TMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_TMR_COUNT (0)
+    /* @brief TPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_TPM_COUNT (0)
+    /* @brief TRIAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+    /* @brief TRNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRNG_COUNT (0)
+    /* @brief TSI availability on the SoC. */
+    #define FSL_FEATURE_SOC_TSI_COUNT (0)
+    /* @brief UART availability on the SoC. */
+    #define FSL_FEATURE_SOC_UART_COUNT (6)
+    /* @brief USB availability on the SoC. */
+    #define FSL_FEATURE_SOC_USB_COUNT (1)
+    /* @brief USBDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+    /* @brief USBHSDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+    /* @brief USBPHY availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+    /* @brief VREF availability on the SoC. */
+    #define FSL_FEATURE_SOC_VREF_COUNT (1)
+    /* @brief WDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_WDOG_COUNT (1)
+    /* @brief XBAR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XBAR_COUNT (0)
+    /* @brief XCVR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XCVR_COUNT (0)
+    /* @brief ZLL availability on the SoC. */
+    #define FSL_FEATURE_SOC_ZLL_COUNT (0)
+#elif defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12)
+    /* @brief ACMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_ACMP_COUNT (0)
+    /* @brief ADC16 availability on the SoC. */
+    #define FSL_FEATURE_SOC_ADC16_COUNT (2)
+    /* @brief AFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_AFE_COUNT (0)
+    /* @brief AIPS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AIPS_COUNT (2)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (0)
+    /* @brief AXBS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AXBS_COUNT (1)
+    /* @brief CADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CADC_COUNT (0)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief MMCAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
+    /* @brief CMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMP_COUNT (3)
+    /* @brief CMT availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMT_COUNT (1)
+    /* @brief CNC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CNC_COUNT (0)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief DAC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DAC_COUNT (1)
+    /* @brief DCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DCDC_COUNT (0)
+    /* @brief DDR availability on the SoC. */
+    #define FSL_FEATURE_SOC_DDR_COUNT (0)
+    /* @brief DMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMA_COUNT (0)
+    /* @brief DMAMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+    /* @brief DRY availability on the SoC. */
+    #define FSL_FEATURE_SOC_DRY_COUNT (0)
+    /* @brief DSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_DSPI_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EMVSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+    /* @brief ENC availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENC_COUNT (0)
+    /* @brief ENET availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENET_COUNT (1)
+    /* @brief EWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EWM_COUNT (1)
+    /* @brief FB availability on the SoC. */
+    #define FSL_FEATURE_SOC_FB_COUNT (1)
+    /* @brief FGPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+    /* @brief FLEXIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FSKDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+    /* @brief FTFA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFA_COUNT (0)
+    /* @brief FTFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFE_COUNT (1)
+    /* @brief FTFL availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFL_COUNT (0)
+    /* @brief FTM availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTM_COUNT (4)
+    /* @brief FTMRA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+    /* @brief FTMRE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+    /* @brief FTMRH availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief HSADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_HSADC_COUNT (0)
+    /* @brief I2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2C_COUNT (3)
+    /* @brief I2S availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2S_COUNT (1)
+    /* @brief ICS availability on the SoC. */
+    #define FSL_FEATURE_SOC_ICS_COUNT (0)
+    /* @brief IRQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_IRQ_COUNT (0)
+    /* @brief KBI availability on the SoC. */
+    #define FSL_FEATURE_SOC_KBI_COUNT (0)
+    /* @brief SLCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_SLCD_COUNT (0)
+    /* @brief LCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LCDC_COUNT (0)
+    /* @brief LDO availability on the SoC. */
+    #define FSL_FEATURE_SOC_LDO_COUNT (0)
+    /* @brief LLWU availability on the SoC. */
+    #define FSL_FEATURE_SOC_LLWU_COUNT (1)
+    /* @brief LMEM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LMEM_COUNT (0)
+    /* @brief LPSCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPTPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (0)
+    /* @brief LTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LTC_COUNT (0)
+    /* @brief MC availability on the SoC. */
+    #define FSL_FEATURE_SOC_MC_COUNT (0)
+    /* @brief MCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCG_COUNT (1)
+    /* @brief MCGLITE availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+    /* @brief MCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCM_COUNT (1)
+    /* @brief MMAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMAU_COUNT (0)
+    /* @brief MMDVSQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+    /* @brief MPU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MPU_COUNT (1)
+    /* @brief MSCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+    /* @brief MTB availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTB_COUNT (0)
+    /* @brief MTBDWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
+    /* @brief NFC availability on the SoC. */
+    #define FSL_FEATURE_SOC_NFC_COUNT (0)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+    /* @brief OSC availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSC_COUNT (1)
+    /* @brief OTFAD availability on the SoC. */
+    #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+    /* @brief PDB availability on the SoC. */
+    #define FSL_FEATURE_SOC_PDB_COUNT (1)
+    /* @brief PGA availability on the SoC. */
+    #define FSL_FEATURE_SOC_PGA_COUNT (0)
+    /* @brief PIT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PIT_COUNT (1)
+    /* @brief PMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_PMC_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (0)
+    /* @brief PWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWT_COUNT (0)
+    /* @brief QuadSPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+    /* @brief RCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RCM_COUNT (1)
+    /* @brief RFSYS availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+    /* @brief RFVBAT availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+    /* @brief RNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNG_COUNT (1)
+    /* @brief RNGB availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNGB_COUNT (0)
+    /* @brief ROM availability on the SoC. */
+    #define FSL_FEATURE_SOC_ROM_COUNT (0)
+    /* @brief RSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RSIM_COUNT (0)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCI_COUNT (0)
+    /* @brief SDHC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDHC_COUNT (1)
+    /* @brief SDRAM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+    /* @brief SIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SIM_COUNT (1)
+    /* @brief SMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMC_COUNT (1)
+    /* @brief SPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPI_COUNT (0)
+    /* @brief TMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_TMR_COUNT (0)
+    /* @brief TPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_TPM_COUNT (0)
+    /* @brief TRIAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+    /* @brief TRNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRNG_COUNT (0)
+    /* @brief TSI availability on the SoC. */
+    #define FSL_FEATURE_SOC_TSI_COUNT (0)
+    /* @brief UART availability on the SoC. */
+    #define FSL_FEATURE_SOC_UART_COUNT (6)
+    /* @brief USB availability on the SoC. */
+    #define FSL_FEATURE_SOC_USB_COUNT (1)
+    /* @brief USBDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+    /* @brief USBHSDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+    /* @brief USBPHY availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+    /* @brief VREF availability on the SoC. */
+    #define FSL_FEATURE_SOC_VREF_COUNT (1)
+    /* @brief WDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_WDOG_COUNT (1)
+    /* @brief XBAR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XBAR_COUNT (0)
+    /* @brief XCVR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XCVR_COUNT (0)
+    /* @brief ZLL availability on the SoC. */
+    #define FSL_FEATURE_SOC_ZLL_COUNT (0)
+#endif
+
+/* CRC module features */
+
+/* @brief Has data register with name CRC */
+#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (DMA_INSTANCE_COUNT * 16)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (DMAMUX_INSTANCE_COUNT * 16)
+/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+
+/* ENET module features */
+
+/* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */
+#define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0)
+/* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */
+#define FSL_FEATURE_ENET_SUPPORT_PTP (1)
+/* @brief Number of associated interrupt vectors. */
+#define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
+/* @brief Errata 2597: No support for IEEE 1588 timestamp timer overflow interrupt. */
+#define FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT_ERRATA_2579 (0)
+/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
+#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
+
+/* EWM module features */
+
+/* @brief Has clock prescaler (register CLKPRESCALER). */
+#define FSL_FEATURE_EWM_HAS_PRESCALER  (0)
+
+/* FLEXBUS module features */
+
+/* No feature definitions */
+
+/* FLASH module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (0)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (1)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (131072)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00020000)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0001C000)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00018000)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00010000)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00000000)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00020000)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+#elif defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (0)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (1)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+#endif
+
+/* FTM module features */
+
+/* @brief Number of channels. */
+#define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
+#define FSL_FEATURE_FTM_CHANNEL_COUNTx { 8, 2, 2, 8 }
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
+
+/* SAI module features */
+
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+#define FSL_FEATURE_SAI_FIFO_COUNT (8)
+/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
+#define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
+#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
+/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
+#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
+/* @brief Ihe interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
+
+/* LLWU module features */
+
+/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+/* @brief Has pins 8-15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+/* @brief Maximum number of internal modules connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+/* @brief Number of digital filters. */
+#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+/* @brief Has MF5 register. */
+#define FSL_FEATURE_LLWU_HAS_MF (0)
+/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1)
+/* @brief Has external pin 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
+/* @brief Has external pin 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
+/* @brief Has external pin 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
+/* @brief Has external pin 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
+/* @brief Has external pin 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
+/* @brief Has external pin 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
+/* @brief Has external pin 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
+/* @brief Has external pin 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
+/* @brief Has external pin 8 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
+/* @brief Has external pin 9 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
+/* @brief Has external pin 10 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
+/* @brief Has external pin 11 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
+/* @brief Has external pin 12 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
+/* @brief Has external pin 13 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
+/* @brief Has external pin 14 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
+/* @brief Has external pin 15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
+/* @brief Has external pin 16 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+/* @brief Has external pin 17 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+/* @brief Has external pin 18 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+/* @brief Has external pin 19 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+/* @brief Has external pin 20 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+/* @brief Has external pin 21 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+/* @brief Has external pin 22 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+/* @brief Has external pin 23 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+/* @brief Has external pin 24 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+/* @brief Has external pin 25 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+/* @brief Has external pin 26 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+/* @brief Has external pin 27 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+/* @brief Has external pin 28 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+/* @brief Has external pin 29 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+/* @brief Has external pin 30 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+/* @brief Has external pin 31 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+/* @brief Has internal module 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+/* @brief Has internal module 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+/* @brief Has internal module 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+/* @brief Has internal module 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+/* @brief Has internal module 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
+/* @brief Has internal module 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+/* @brief Has internal module 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+/* @brief Has internal module 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+
+/* MCG module features */
+
+/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
+/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
+/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
+/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
+/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
+/* @brief The PLL clock is divided by 2 before VCO divider. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
+/* @brief FRDIV supports 1280. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
+/* @brief FRDIV supports 1536. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
+#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
+/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
+#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
+/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_PLL1 (0)
+/* @brief Has 48MHz internal oscillator. */
+#define FSL_FEATURE_MCG_HAS_IRC_48M (1)
+/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_OSC1 (0)
+/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
+#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
+/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
+#define FSL_FEATURE_MCG_HAS_LOLRE (1)
+/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
+#define FSL_FEATURE_MCG_USE_OSCSEL (1)
+/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
+#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
+/* @brief TBD */
+#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL (1)
+/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
+/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
+/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
+#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
+/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
+#define FSL_FEATURE_MCG_HAS_FLL (1)
+/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
+/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
+#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
+/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
+/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
+/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
+#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
+/* @brief Has external clock monitor (register bit C6[CME]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
+/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
+#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
+/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
+#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
+/* @brief Has PEI mode or PBI mode. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
+/* @brief Reset clock mode is BLPI. */
+#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
+
+/* MPU module features */
+
+/* @brief Specifies number of descriptors available. */
+#define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12)
+/* @brief Has process identifier support. */
+#define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1)
+/* @brief Has master 0. */
+#define FSL_FEATURE_MPU_HAS_MASTER0 (1)
+/* @brief Has master 1. */
+#define FSL_FEATURE_MPU_HAS_MASTER1 (1)
+/* @brief Has master 2. */
+#define FSL_FEATURE_MPU_HAS_MASTER2 (1)
+/* @brief Has master 3. */
+#define FSL_FEATURE_MPU_HAS_MASTER3 (1)
+/* @brief Has master 4. */
+#define FSL_FEATURE_MPU_HAS_MASTER4 (1)
+/* @brief Has master 5. */
+#define FSL_FEATURE_MPU_HAS_MASTER5 (1)
+/* @brief Has master 6. */
+#define FSL_FEATURE_MPU_HAS_MASTER6 (0)
+/* @brief Has master 7. */
+#define FSL_FEATURE_MPU_HAS_MASTER7 (0)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
+
+/* OSC module features */
+
+/* @brief Has OSC1 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC1 (0)
+/* @brief Has OSC0 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC0 (0)
+/* @brief Has OSC external oscillator (without index). */
+#define FSL_FEATURE_OSC_HAS_OSC (1)
+/* @brief Number of OSC external oscillators. */
+#define FSL_FEATURE_OSC_OSC_COUNT (1)
+/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
+#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
+
+/* PDB module features */
+
+/* @brief Define the count of supporting ADC pre-trigger for each channel. */
+#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2)
+/* @brief Has DAC support. */
+#define FSL_FEATURE_PDB_HAS_DAC (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (4)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (1)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (1)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (1)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (1)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (1)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (0)
+
+/* RTC module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \
+    defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12)
+    /* @brief Has wakeup pin (bit field CR[WPS]). */
+    #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+    /* @brief Has low power features (registers MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+    /* @brief Has read/write access control (registers WAR and RAR). */
+    #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+    /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_SECURITY (1)
+#elif defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief Has wakeup pin (bit field CR[WPS]). */
+    #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+    /* @brief Has low power features (registers MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+    /* @brief Has read/write access control (registers WAR and RAR). */
+    #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+    /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_SECURITY (0)
+#endif
+
+/* SDHC module features */
+
+/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
+#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1)
+/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
+#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0)
+/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
+#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (1)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
+
+/* DSPI module features */
+
+/* @brief Receive/transmit FIFO size in number of items. */
+#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
+#define FSL_FEATURE_DSPI_FIFO_SIZEx { 4, 1, 1 }
+/* @brief Maximum transfer data width in bits. */
+#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
+/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
+#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
+/* @brief Number of chip select pins. */
+#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
+/* @brief Has chip select strobe capability on the PCS5 pin. */
+#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
+/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+/* @brief Has 16-bit data transfer support. */
+#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (0) : \
+    ((x) == 2 ? (0) : (-1))))
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
+
+/* UART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_HAS_FIFO (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_UART_IS_SCI (0)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_FIFO_SIZE (8)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
+/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
+#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (1) : \
+    ((x) == 2 ? (1) : \
+    ((x) == 3 ? (1) : \
+    ((x) == 4 ? (0) : \
+    ((x) == 5 ? (0) : (-1)))))))
+
+/* USB module features */
+
+/* @brief HOST mode enabled */
+#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
+/* @brief OTG mode enabled */
+#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
+/* @brief Has KEEP_ALIVE_CTRL register */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
+/* @brief Has the Dynamic SOF threshold compare support */
+#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
+/* @brief Has the VBUS detect support */
+#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
+/* @brief Has the IRC48M module clock support */
+#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief Describes the set of SC[MODE_LV] bitfield values */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+
+/* WDOG module features */
+
+/* @brief Watchdog is available. */
+#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
+/* @brief Has Wait mode support. */
+#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
+
+#endif /* __FSL_MK64F12_FEATURES_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/Workspace/Interrupt/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h b/Workspace/Interrupt/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
new file mode 100644
index 0000000..0044bbf
--- /dev/null
+++ b/Workspace/Interrupt/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
@@ -0,0 +1,111 @@
+/*
+** ###################################################################
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Register bit field access macros.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+#ifndef _FSL_BITACCESS_H
+#define _FSL_BITACCESS_H  1
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/**
+ * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+#endif /* _FSL_BITACCESS_H */
+
+/******************************************************************************/
diff --git a/Workspace/Interrupt/SDK/platform/devices/fsl_device_registers.h b/Workspace/Interrupt/SDK/platform/devices/fsl_device_registers.h
new file mode 100644
index 0000000..abeb4ac
--- /dev/null
+++ b/Workspace/Interrupt/SDK/platform/devices/fsl_device_registers.h
@@ -0,0 +1,1083 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2014-05-15
+**     Build:               b141209
+**
+**     Abstract:
+**         Common include file for CMSIS register access layer headers.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-05-15)
+**         Customer release.
+**
+** ###################################################################
+*/
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \
+    defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10))
+
+    #define K02F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK02F12810/include/MK02F12810.h"
+    /* Extension register definitions */
+    #include "MK02F12810/include/MK02F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK02F12810/include/MK02F12810_features.h"
+
+#elif (defined(CPU_MK10DN512VLK10) || defined(CPU_MK10DN512VLL10) || defined(CPU_MK10DX128VLQ10) || \
+    defined(CPU_MK10DX256VLQ10) || defined(CPU_MK10DN512VLQ10) || defined(CPU_MK10DN512VMC10) || \
+    defined(CPU_MK10DX128VMD10) || defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10))
+
+    #define K10D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK10D10/include/MK10D10.h"
+    /* Extension register definitions */
+    #include "MK10D10/include/MK10D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK10D10/include/MK10D10_features.h"
+
+#elif (defined(CPU_MK11DX128AVLK5) || defined(CPU_MK11DX256AVLK5) || defined(CPU_MK11DN512AVLK5) || \
+    defined(CPU_MK11DX128AVMC5) || defined(CPU_MK11DX256AVMC5) || defined(CPU_MK11DN512AVMC5))
+
+    #define K11DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK11DA5/include/MK11DA5.h"
+    /* Extension register definitions */
+    #include "MK11DA5/include/MK11DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK11DA5/include/MK11DA5_features.h"
+
+#elif (defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DX256VLK10) || defined(CPU_MK20DN512VLL10) || \
+    defined(CPU_MK20DX256VLL10) || defined(CPU_MK20DX128VLQ10) || defined(CPU_MK20DX256VLQ10) || \
+    defined(CPU_MK20DN512VLQ10) || defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || \
+    defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || defined(CPU_MK20DN512VMD10))
+
+    #define K20D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D10/include/MK20D10.h"
+    /* Extension register definitions */
+    #include "MK20D10/include/MK20D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D10/include/MK20D10_features.h"
+
+#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \
+    defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
+    defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
+    defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
+    defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \
+    defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
+    defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \
+    defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
+    defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
+    defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5))
+
+    #define K20D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D5/include/MK20D5.h"
+    /* Extension register definitions */
+    #include "MK20D5/include/MK20D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D5/include/MK20D5_features.h"
+
+#elif (defined(CPU_MK21DX128AVLK5) || defined(CPU_MK21DX256AVLK5) || defined(CPU_MK21DN512AVLK5) || \
+    defined(CPU_MK21DX128AVMC5) || defined(CPU_MK21DX256AVMC5) || defined(CPU_MK21DN512AVMC5))
+
+    #define K21DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21DA5/include/MK21DA5.h"
+    /* Extension register definitions */
+    #include "MK21DA5/include/MK21DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21DA5/include/MK21DA5_features.h"
+
+#elif (defined(CPU_MK21FX512AVLQ12) || defined(CPU_MK21FN1M0AVLQ12) || defined(CPU_MK21FX512AVMC12) || \
+    defined(CPU_MK21FN1M0AVMC12) || defined(CPU_MK21FX512AVMD12) || defined(CPU_MK21FN1M0AVMD12))
+
+    #define K21FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21FA12/include/MK21FA12.h"
+    /* Extension register definitions */
+    #include "MK21FA12/include/MK21FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21FA12/include/MK21FA12_features.h"
+
+#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \
+    defined(CPU_MK22FN128VMP10))
+
+    #define K22F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F12810/include/MK22F12810.h"
+    /* Extension register definitions */
+    #include "MK22F12810/include/MK22F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F12810/include/MK22F12810_features.h"
+
+#elif (defined(CPU_MK22FX512AVLH12) || defined(CPU_MK22FN1M0AVLH12) || defined(CPU_MK22FX512AVLK12) || \
+    defined(CPU_MK22FN1M0AVLK12) || defined(CPU_MK22FX512AVLL12) || defined(CPU_MK22FN1M0AVLL12) || \
+    defined(CPU_MK22FX512AVLQ12) || defined(CPU_MK22FN1M0AVLQ12) || defined(CPU_MK22FX512AVMC12) || \
+    defined(CPU_MK22FN1M0AVMC12) || defined(CPU_MK22FX512AVMD12) || defined(CPU_MK22FN1M0AVMD12))
+
+    #define K22FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22FA12/include/MK22FA12.h"
+    /* Extension register definitions */
+    #include "MK22FA12/include/MK22FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22FA12/include/MK22FA12_features.h"
+
+#elif (defined(CPU_MK22FN256CAH12) || defined(CPU_MK22FN128CAH12) || defined(CPU_MK22FN256VDC12) || \
+    defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12))
+
+    #define K22F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F25612/include/MK22F25612.h"
+    /* Extension register definitions */
+    #include "MK22F25612/include/MK22F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F25612/include/MK22F25612_features.h"
+
+#elif (defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
+    defined(CPU_MK22FN512VLL12) || defined(CPU_MK22FN512VMP12))
+
+    #define K22F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F51212/include/MK22F51212.h"
+    /* Extension register definitions */
+    #include "MK22F51212/include/MK22F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F51212/include/MK22F51212_features.h"
+
+#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12))
+
+    #define K24F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F12/include/MK24F12.h"
+    /* Extension register definitions */
+    #include "MK24F12/include/MK24F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F12/include/MK24F12_features.h"
+
+#elif (defined(CPU_MK24FN256VDC12))
+
+    #define K24F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F25612/include/MK24F25612.h"
+    /* Extension register definitions */
+    #include "MK24F25612/include/MK24F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F25612/include/MK24F25612_features.h"
+
+#elif (defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VLQ18) || defined(CPU_MK26FN2M0VMD18) || \
+    defined(CPU_MK26FN2M0VMI18))
+
+    #define K26F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK26F18/include/MK26F18.h"
+    /* Extension register definitions */
+    #include "MK26F18/include/MK26F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK26F18/include/MK26F18_features.h"
+
+#elif (defined(CPU_MK30DN512VLK10) || defined(CPU_MK30DN512VLL10) || defined(CPU_MK30DX128VLQ10) || \
+    defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMC10) || \
+    defined(CPU_MK30DX128VMD10) || defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10))
+
+    #define K30D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK30D10/include/MK30D10.h"
+    /* Extension register definitions */
+    #include "MK30D10/include/MK30D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK30D10/include/MK30D10_features.h"
+
+#elif (defined(CPU_MK40DN512VLK10) || defined(CPU_MK40DN512VLL10) || defined(CPU_MK40DX128VLQ10) || \
+    defined(CPU_MK40DX256VLQ10) || defined(CPU_MK40DN512VLQ10) || defined(CPU_MK40DN512VMC10) || \
+    defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || defined(CPU_MK40DN512VMD10))
+
+    #define K40D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK40D10/include/MK40D10.h"
+    /* Extension register definitions */
+    #include "MK40D10/include/MK40D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK40D10/include/MK40D10_features.h"
+
+#elif (defined(CPU_MK50DX256CLL10) || defined(CPU_MK50DN512CLL10) || defined(CPU_MK50DN512CLQ10) || \
+    defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || defined(CPU_MK50DN512CMD10) || \
+    defined(CPU_MK50DX256CMD10) || defined(CPU_MK50DX256CLK10))
+
+    #define K50D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK50D10/include/MK50D10.h"
+    /* Extension register definitions */
+    #include "MK50D10/include/MK50D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK50D10/include/MK50D10_features.h"
+
+#elif (defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10) || defined(CPU_MK51DN256CLQ10) || \
+    defined(CPU_MK51DN512CLQ10) || defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || \
+    defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10) || defined(CPU_MK51DX256CLK10))
+
+    #define K51D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK51D10/include/MK51D10.h"
+    /* Extension register definitions */
+    #include "MK51D10/include/MK51D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK51D10/include/MK51D10_features.h"
+
+#elif (defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10))
+
+    #define K52D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK52D10/include/MK52D10.h"
+    /* Extension register definitions */
+    #include "MK52D10/include/MK52D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK52D10/include/MK52D10_features.h"
+
+#elif (defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || defined(CPU_MK53DN512CMD10) || \
+    defined(CPU_MK53DX256CMD10))
+
+    #define K53D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK53D10/include/MK53D10.h"
+    /* Extension register definitions */
+    #include "MK53D10/include/MK53D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK53D10/include/MK53D10_features.h"
+
+#elif (defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DN512VLL10) || \
+    defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DN512VLQ10) || \
+    defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || defined(CPU_MK60DN512VMC10) || \
+    defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10))
+
+    #define K60D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK60D10/include/MK60D10.h"
+    /* Extension register definitions */
+    #include "MK60D10/include/MK60D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK60D10/include/MK60D10_features.h"
+
+#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12))
+
+    #define K63F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK63F12/include/MK63F12.h"
+    /* Extension register definitions */
+    #include "MK63F12/include/MK63F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK63F12/include/MK63F12_features.h"
+
+#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
+    defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12))
+
+
+    #define K64F12_SERIES
+    /* CMSIS-style register definitions */
+    #include "MK64F12/include/MK64F12.h"
+    /* Extension register definitions */
+    #include "MK64F12/include/MK64F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK64F12/include/MK64F12_features.h"
+
+#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
+    defined(CPU_MK65FX1M0VMI18))
+
+    #define K65F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK65F18/include/MK65F18.h"
+    /* Extension register definitions */
+    #include "MK65F18/include/MK65F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK65F18/include/MK65F18_features.h"
+
+#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
+    defined(CPU_MK66FX1M0VMD18))
+
+    #define K66F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK66F18/include/MK66F18.h"
+    /* Extension register definitions */
+    #include "MK66F18/include/MK66F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK66F18/include/MK66F18_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12))
+
+    #define K70F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F12/include/MK70F12.h"
+    /* Extension register definitions */
+    #include "MK70F12/include/MK70F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F12/include/MK70F12_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+
+    #define K70F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F15/include/MK70F15.h"
+    /* Extension register definitions */
+    #include "MK70F15/include/MK70F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F15/include/MK70F15_features.h"
+
+#elif (defined(CPU_MK80FN256CAx15) || defined(CPU_MK80FN256VDC15) || defined(CPU_MK80FN256VLL15) || \
+    defined(CPU_MK80FN256VLQ15))
+
+    #define K80F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK80F25615/include/MK80F25615.h"
+    /* Extension register definitions */
+    #include "MK80F25615/include/MK80F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK80F25615/include/MK80F25615_features.h"
+
+#elif (defined(CPU_MK81FN256CAx15) || defined(CPU_MK81FN256VDC15) || defined(CPU_MK81FN256VLL15) || \
+    defined(CPU_MK81FN256VLQ15))
+
+    #define K81F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK81F25615/include/MK81F25615.h"
+    /* Extension register definitions */
+    #include "MK81F25615/include/MK81F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK81F25615/include/MK81F25615_features.h"
+
+#elif (defined(CPU_MK82FN256CAx15) || defined(CPU_MK82FN256VDC15) || defined(CPU_MK82FN256VLL15) || \
+    defined(CPU_MK82FN256VLQ15))
+
+    #define K82F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK82F25615/include/MK82F25615.h"
+    /* Extension register definitions */
+    #include "MK82F25615/include/MK82F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK82F25615/include/MK82F25615_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC2) || defined(CPU_MKE02Z32VLC2) || defined(CPU_MKE02Z16VLC2) || \
+    defined(CPU_MKE02Z64VLD2) || defined(CPU_MKE02Z32VLD2) || defined(CPU_MKE02Z16VLD2) || \
+    defined(CPU_MKE02Z64VLH2) || defined(CPU_MKE02Z64VQH2) || defined(CPU_MKE02Z32VLH2) || \
+    defined(CPU_MKE02Z32VQH2))
+
+    #define KE02Z2_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z2/include/MKE02Z2.h"
+    /* Extension register definitions */
+    #include "MKE02Z2/include/MKE02Z2_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z2/include/MKE02Z2_features.h"
+
+#elif (defined(CPU_SKEAZN64MLC2) || defined(CPU_SKEAZN32MLC2) || defined(CPU_SKEAZN16MLC2) || \
+    defined(CPU_SKEAZN64MLD2) || defined(CPU_SKEAZN32MLD2) || defined(CPU_SKEAZN16MLD2) || \
+    defined(CPU_SKEAZN64MLH2) || defined(CPU_SKEAZN32MLH2))
+
+    #define SKEAZN642_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN642/include/SKEAZN642.h"
+    /* Extension register definitions */
+    #include "SKEAZN642/include/SKEAZN642_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN642/include/SKEAZN642_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC4) || defined(CPU_MKE02Z32VLC4) || defined(CPU_MKE02Z16VLC4) || \
+    defined(CPU_MKE02Z64VLD4) || defined(CPU_MKE02Z32VLD4) || defined(CPU_MKE02Z16VLD4) || \
+    defined(CPU_MKE02Z64VLH4) || defined(CPU_MKE02Z64VQH4) || defined(CPU_MKE02Z32VLH4) || \
+    defined(CPU_MKE02Z32VQH4))
+
+    #define KE02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z4/include/MKE02Z4.h"
+    /* Extension register definitions */
+    #include "MKE02Z4/include/MKE02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z4/include/MKE02Z4_features.h"
+
+#elif (defined(CPU_MKE04Z128VLD4) || defined(CPU_MKE04Z64VLD4) || defined(CPU_MKE04Z128VLK4) || \
+    defined(CPU_MKE04Z64VLK4) || defined(CPU_MKE04Z128VQH4) || defined(CPU_MKE04Z64VQH4) || \
+    defined(CPU_MKE04Z128VLH4) || defined(CPU_MKE04Z64VLH4))
+
+    #define KE04Z1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284.h"
+    /* Extension register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_features.h"
+
+#elif (defined(CPU_MKE04Z8VFK4) || defined(CPU_MKE04Z8VTG4) || defined(CPU_MKE04Z8VWJ4))
+
+    #define KE04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z4/include/MKE04Z4.h"
+    /* Extension register definitions */
+    #include "MKE04Z4/include/MKE04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z4/include/MKE04Z4_features.h"
+
+#elif (defined(CPU_SKEAZN8MFK) || defined(CPU_SKEAZN8MTG))
+
+    #define SKEAZN84_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN84/include/SKEAZN84.h"
+    /* Extension register definitions */
+    #include "SKEAZN84/include/SKEAZN84_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN84/include/SKEAZN84_features.h"
+
+#elif (defined(CPU_MKE06Z128VLD4) || defined(CPU_MKE06Z64VLD4) || defined(CPU_MKE06Z128VLK4) || \
+    defined(CPU_MKE06Z64VLK4) || defined(CPU_MKE06Z128VQH4) || defined(CPU_MKE06Z64VQH4) || \
+    defined(CPU_MKE06Z128VLH4) || defined(CPU_MKE06Z64VLH4))
+
+    #define KE06Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE06Z4/include/MKE06Z4.h"
+    /* Extension register definitions */
+    #include "MKE06Z4/include/MKE06Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE06Z4/include/MKE06Z4_features.h"
+
+#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
+    defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \
+    defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4))
+
+    #define KL02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL02Z4/include/MKL02Z4.h"
+    /* Extension register definitions */
+    #include "MKL02Z4/include/MKL02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL02Z4/include/MKL02Z4_features.h"
+
+#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \
+    defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \
+    defined(CPU_MKL03Z32VFK4))
+
+    #define KL03Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL03Z4/include/MKL03Z4.h"
+    /* Extension register definitions */
+    #include "MKL03Z4/include/MKL03Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL03Z4/include/MKL03Z4_features.h"
+
+#elif (defined(CPU_MKL04Z8VFK4) || defined(CPU_MKL04Z16VFK4) || defined(CPU_MKL04Z32VFK4) || \
+    defined(CPU_MKL04Z8VLC4) || defined(CPU_MKL04Z16VLC4) || defined(CPU_MKL04Z32VLC4) || \
+    defined(CPU_MKL04Z8VFM4) || defined(CPU_MKL04Z16VFM4) || defined(CPU_MKL04Z32VFM4) || \
+    defined(CPU_MKL04Z16VLF4) || defined(CPU_MKL04Z32VLF4))
+
+    #define KL04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL04Z4/include/MKL04Z4.h"
+    /* Extension register definitions */
+    #include "MKL04Z4/include/MKL04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL04Z4/include/MKL04Z4_features.h"
+
+#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \
+    defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
+    defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
+    defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4))
+
+    #define KL05Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL05Z4/include/MKL05Z4.h"
+    /* Extension register definitions */
+    #include "MKL05Z4/include/MKL05Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL05Z4/include/MKL05Z4_features.h"
+
+#elif (defined(CPU_MKL13Z32VFM4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z32VFT4) || \
+    defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z32VLH4) || defined(CPU_MKL13Z64VLH4) || \
+    defined(CPU_MKL13Z32VLK4) || defined(CPU_MKL13Z64VLK4) || defined(CPU_MKL13Z32VMP4) || \
+    defined(CPU_MKL13Z64VMP4))
+
+    #define KL13Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL13Z644/include/MKL13Z644.h"
+    /* Extension register definitions */
+    #include "MKL13Z644/include/MKL13Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL13Z644/include/MKL13Z644_features.h"
+
+#elif (defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || defined(CPU_MKL14Z32VFT4) || \
+    defined(CPU_MKL14Z64VFT4) || defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || \
+    defined(CPU_MKL14Z32VLK4) || defined(CPU_MKL14Z64VLK4))
+
+    #define KL14Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL14Z4/include/MKL14Z4.h"
+    /* Extension register definitions */
+    #include "MKL14Z4/include/MKL14Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL14Z4/include/MKL14Z4_features.h"
+
+#elif (defined(CPU_MKL15Z128CAD4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || \
+    defined(CPU_MKL15Z128VFM4) || defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || \
+    defined(CPU_MKL15Z128VFT4) || defined(CPU_MKL15Z32VLH4) || defined(CPU_MKL15Z64VLH4) || \
+    defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || defined(CPU_MKL15Z64VLK4) || \
+    defined(CPU_MKL15Z128VLK4))
+
+    #define KL15Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL15Z4/include/MKL15Z4.h"
+    /* Extension register definitions */
+    #include "MKL15Z4/include/MKL15Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL15Z4/include/MKL15Z4_features.h"
+
+#elif (defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || \
+    defined(CPU_MKL16Z32VFT4) || defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || \
+    defined(CPU_MKL16Z32VLH4) || defined(CPU_MKL16Z64VLH4) || defined(CPU_MKL16Z128VLH4) || \
+    defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VMP4))
+
+    #define KL16Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL16Z4/include/MKL16Z4.h"
+    /* Extension register definitions */
+    #include "MKL16Z4/include/MKL16Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL16Z4/include/MKL16Z4_features.h"
+
+#elif (defined(CPU_MKL17Z128VFM4) || defined(CPU_MKL17Z256VFM4) || defined(CPU_MKL17Z128VFT4) || \
+    defined(CPU_MKL17Z256VFT4) || defined(CPU_MKL17Z128VLH4) || defined(CPU_MKL17Z256VLH4) || \
+    defined(CPU_MKL17Z128VMP4) || defined(CPU_MKL17Z256VMP4))
+
+    #define KL17Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z4/include/MKL17Z4.h"
+    /* Extension register definitions */
+    #include "MKL17Z4/include/MKL17Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z4/include/MKL17Z4_features.h"
+
+#elif (defined(CPU_MKL17Z32VDA4) || defined(CPU_MKL17Z64VDA4) || defined(CPU_MKL17Z32VFM4) || \
+    defined(CPU_MKL17Z64VFM4) || defined(CPU_MKL17Z32VFT4) || defined(CPU_MKL17Z64VFT4) || \
+    defined(CPU_MKL17Z32VLH4) || defined(CPU_MKL17Z64VLH4) || defined(CPU_MKL17Z32VMP4) || \
+    defined(CPU_MKL17Z64VMP4))
+
+    #define KL17Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z644/include/MKL17Z644.h"
+    /* Extension register definitions */
+    #include "MKL17Z644/include/MKL17Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z644/include/MKL17Z644_features.h"
+
+#elif (defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || defined(CPU_MKL24Z32VFT4) || \
+    defined(CPU_MKL24Z64VFT4) || defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || \
+    defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4))
+
+    #define KL24Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL24Z4/include/MKL24Z4.h"
+    /* Extension register definitions */
+    #include "MKL24Z4/include/MKL24Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL24Z4/include/MKL24Z4_features.h"
+
+#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
+    defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
+    defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
+    defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
+
+    #define KL25Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL25Z4/include/MKL25Z4.h"
+    /* Extension register definitions */
+    #include "MKL25Z4/include/MKL25Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL25Z4/include/MKL25Z4_features.h"
+
+
+#elif (defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || \
+    defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || \
+    defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || \
+    defined(CPU_MKL26Z128VLH4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z128VLL4) || \
+    defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
+    defined(CPU_MKL26Z256VMP4))
+
+    #define KL26Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL26Z4/include/MKL26Z4.h"
+    /* Extension register definitions */
+    #include "MKL26Z4/include/MKL26Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL26Z4/include/MKL26Z4_features.h"
+
+#elif (defined(CPU_MKL27Z128VFM4) || defined(CPU_MKL27Z256VFM4) || defined(CPU_MKL27Z128VFT4) || \
+    defined(CPU_MKL27Z256VFT4) || defined(CPU_MKL27Z128VLH4) || defined(CPU_MKL27Z256VLH4) || \
+    defined(CPU_MKL27Z128VMP4) || defined(CPU_MKL27Z256VMP4))
+
+    #define KL27Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z4/include/MKL27Z4.h"
+    /* Extension register definitions */
+    #include "MKL27Z4/include/MKL27Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z4/include/MKL27Z4_features.h"
+
+#elif (defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z64VDA4) || defined(CPU_MKL27Z32VFM4) || \
+    defined(CPU_MKL27Z64VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z64VFT4) || \
+    defined(CPU_MKL27Z32VLH4) || defined(CPU_MKL27Z64VLH4) || defined(CPU_MKL27Z32VMP4) || \
+    defined(CPU_MKL27Z64VMP4))
+
+    #define KL27Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z644/include/MKL27Z644.h"
+    /* Extension register definitions */
+    #include "MKL27Z644/include/MKL27Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z644/include/MKL27Z644_features.h"
+
+#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \
+    defined(CPU_MKL33Z256VMP4))
+
+    #define KL33Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z4/include/MKL33Z4.h"
+    /* Extension register definitions */
+    #include "MKL33Z4/include/MKL33Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z4/include/MKL33Z4_features.h"
+
+#elif (defined(CPU_MKL33Z32VFT4) || defined(CPU_MKL33Z64VFT4) || defined(CPU_MKL33Z32VLH4) || \
+    defined(CPU_MKL33Z64VLH4) || defined(CPU_MKL33Z32VLK4) || defined(CPU_MKL33Z64VLK4) || \
+    defined(CPU_MKL33Z32VMP4) || defined(CPU_MKL33Z64VMP4))
+
+    #define KL33Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z644/include/MKL33Z644.h"
+    /* Extension register definitions */
+    #include "MKL33Z644/include/MKL33Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z644/include/MKL33Z644_features.h"
+
+#elif (defined(CPU_MKL34Z64VLH4) || defined(CPU_MKL34Z64VLL4))
+
+    #define KL34Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL34Z4/include/MKL34Z4.h"
+    /* Extension register definitions */
+    #include "MKL34Z4/include/MKL34Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL34Z4/include/MKL34Z4_features.h"
+
+#elif (defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || \
+    defined(CPU_MKL36Z64VLL4) || defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || \
+    defined(CPU_MKL36Z128VMC4) || defined(CPU_MKL36Z256VMC4) || defined(CPU_MKL36Z256VMP4))
+
+    #define KL36Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL36Z4/include/MKL36Z4.h"
+    /* Extension register definitions */
+    #include "MKL36Z4/include/MKL36Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL36Z4/include/MKL36Z4_features.h"
+
+#elif (defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z128VMP4) || \
+    defined(CPU_MKL43Z256VMP4))
+
+    #define KL43Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL43Z4/include/MKL43Z4.h"
+    /* Extension register definitions */
+    #include "MKL43Z4/include/MKL43Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL43Z4/include/MKL43Z4_features.h"
+
+#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
+    defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \
+    defined(CPU_MKL46Z256VMP4))
+
+    #define KL46Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL46Z4/include/MKL46Z4.h"
+    /* Extension register definitions */
+    #include "MKL46Z4/include/MKL46Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL46Z4/include/MKL46Z4_features.h"
+
+#elif (defined(CPU_MKM14Z128AHH5) || defined(CPU_MKM14Z64AHH5))
+
+    #define KM14ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5.h"
+    /* Extension register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_features.h"
+
+#elif (defined(CPU_MKM33Z128ALH5) || defined(CPU_MKM33Z64ALH5) || defined(CPU_MKM33Z128ALL5) || \
+    defined(CPU_MKM33Z64ALL5))
+
+    #define KM33ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5.h"
+    /* Extension register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z128ALL5))
+
+    #define KM34ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5.h"
+    /* Extension register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z256VLL7) || defined(CPU_MKM34Z256VLQ7))
+
+    #define KM34Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34Z7/include/MKM34Z7.h"
+    /* Extension register definitions */
+    #include "MKM34Z7/include/MKM34Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34Z7/include/MKM34Z7_features.h"
+
+#elif (defined(CPU_MKV10Z16VFM7) || defined(CPU_MKV10Z16VLC7) || defined(CPU_MKV10Z16VLF7) || \
+    defined(CPU_MKV10Z32VFM7) || defined(CPU_MKV10Z32VLC7) || defined(CPU_MKV10Z32VLF7))
+
+    #define KV10Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z7/include/MKV10Z7.h"
+    /* Extension register definitions */
+    #include "MKV10Z7/include/MKV10Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z7/include/MKV10Z7_features.h"
+
+#elif (defined(CPU_MKV10Z128VFM7) || defined(CPU_MKV10Z128VLC7) || defined(CPU_MKV10Z128VLF7) || \
+    defined(CPU_MKV10Z128VLH7) || defined(CPU_MKV10Z64VFM7) || defined(CPU_MKV10Z64VLC7) || \
+    defined(CPU_MKV10Z64VLF7) || defined(CPU_MKV10Z64VLH7))
+
+    #define KV10Z1287_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z1287/include/MKV10Z1287.h"
+    /* Extension register definitions */
+    #include "MKV10Z1287/include/MKV10Z1287_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z1287/include/MKV10Z1287_features.h"
+
+#elif (defined(CPU_MKV11Z128VFM7) || defined(CPU_MKV11Z128VLC7) || defined(CPU_MKV11Z128VLF7) || \
+    defined(CPU_MKV11Z128VLH7) || defined(CPU_MKV11Z64VFM7) || defined(CPU_MKV11Z64VLC7) || \
+    defined(CPU_MKV11Z64VLF7) || defined(CPU_MKV11Z64VLH7))
+
+    #define KV11Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV11Z7/include/MKV11Z7.h"
+    /* Extension register definitions */
+    #include "MKV11Z7/include/MKV11Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV11Z7/include/MKV11Z7_features.h"
+
+#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
+    defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10))
+
+    #define KV30F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV30F12810/include/MKV30F12810.h"
+    /* Extension register definitions */
+    #include "MKV30F12810/include/MKV30F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV30F12810/include/MKV30F12810_features.h"
+
+#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10))
+
+    #define KV31F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F12810/include/MKV31F12810.h"
+    /* Extension register definitions */
+    #include "MKV31F12810/include/MKV31F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F12810/include/MKV31F12810_features.h"
+
+#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12))
+
+    #define KV31F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F25612/include/MKV31F25612.h"
+    /* Extension register definitions */
+    #include "MKV31F25612/include/MKV31F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F25612/include/MKV31F25612_features.h"
+
+#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12))
+
+    #define KV31F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F51212/include/MKV31F51212.h"
+    /* Extension register definitions */
+    #include "MKV31F51212/include/MKV31F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F51212/include/MKV31F51212_features.h"
+
+#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
+    defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15))
+
+    #define KV40F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV40F15/include/MKV40F15.h"
+    /* Extension register definitions */
+    #include "MKV40F15/include/MKV40F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV40F15/include/MKV40F15_features.h"
+
+#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15))
+
+    #define KV43F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV43F15/include/MKV43F15.h"
+    /* Extension register definitions */
+    #include "MKV43F15/include/MKV43F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV43F15/include/MKV43F15_features.h"
+
+#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15))
+
+    #define KV44F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV44F15/include/MKV44F15.h"
+    /* Extension register definitions */
+    #include "MKV44F15/include/MKV44F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV44F15/include/MKV44F15_features.h"
+
+#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \
+    defined(CPU_MKV45F256VLL15))
+
+    #define KV45F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV45F15/include/MKV45F15.h"
+    /* Extension register definitions */
+    #include "MKV45F15/include/MKV45F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV45F15/include/MKV45F15_features.h"
+
+#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \
+    defined(CPU_MKV46F256VLL15))
+
+    #define KV46F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV46F15/include/MKV46F15.h"
+    /* Extension register definitions */
+    #include "MKV46F15/include/MKV46F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV46F15/include/MKV46F15_features.h"
+
+#elif (defined(CPU_MKW01Z128CHN4))
+
+    #define KW01Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW01Z4/include/MKW01Z4.h"
+    /* Extension register definitions */
+    #include "MKW01Z4/include/MKW01Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW01Z4/include/MKW01Z4_features.h"
+
+#elif (defined(CPU_MKW20Z160VHT4))
+
+    #define KW20Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW20Z4/include/MKW20Z4.h"
+    /* Extension register definitions */
+    #include "MKW20Z4/include/MKW20Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW20Z4/include/MKW20Z4_features.h"
+
+#elif (defined(CPU_MKW21D256VHA5) || defined(CPU_MKW21D512VHA5))
+
+    #define KW21D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW21D5/include/MKW21D5.h"
+    /* Extension register definitions */
+    #include "MKW21D5/include/MKW21D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW21D5/include/MKW21D5_features.h"
+
+#elif (defined(CPU_MKW22D512VHA5))
+
+    #define KW22D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW22D5/include/MKW22D5.h"
+    /* Extension register definitions */
+    #include "MKW22D5/include/MKW22D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW22D5/include/MKW22D5_features.h"
+
+#elif (defined(CPU_MKW24D512VHA5))
+
+    #define KW24D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW24D5/include/MKW24D5.h"
+    /* Extension register definitions */
+    #include "MKW24D5/include/MKW24D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW24D5/include/MKW24D5_features.h"
+
+#elif (defined(CPU_MKW30Z160VHM4))
+
+    #define KW30Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW30Z4/include/MKW30Z4.h"
+    /* Extension register definitions */
+    #include "MKW30Z4/include/MKW30Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW30Z4/include/MKW30Z4_features.h"
+
+#elif (defined(CPU_MKW40Z160VHT4))
+
+    #define KW40Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW40Z4/include/MKW40Z4.h"
+    /* Extension register definitions */
+    #include "MKW40Z4/include/MKW40Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW40Z4/include/MKW40Z4_features.h"
+
+#elif (defined(CPU_SKEAZ128MLH) || defined(CPU_SKEAZ64MLH) || defined(CPU_SKEAZ128MLK) || \
+    defined(CPU_SKEAZ64MLK))
+
+    #define SKEAZ1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284.h"
+    /* Extension register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/Workspace/Interrupt/Sources/main.c b/Workspace/Interrupt/Sources/main.c
new file mode 100644
index 0000000..fe10301
--- /dev/null
+++ b/Workspace/Interrupt/Sources/main.c
@@ -0,0 +1,51 @@
+#include "MK64F12.h"
+
+void DelayFunction(void);
+
+int main(void)
+{
+
+	SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; /*Enable Port B Clock Gate Control*/
+	SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;/*Enable Port C Clock Gate Control*/
+	SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /*Enable Port A Clock Gate Control*/
+	PORTB_PCR21 = 0x100; /*Blue Led, configured as Alternative 1 (GPIO)*/
+	PORTB_PCR22 = 0x100;/*Red Led, configured as Alternative 1 (GPIO)*/
+	PORTC_PCR6 = 0x90100; /*PORTC_PCR6: ISF=0,IRQC=9,MUX=1 */
+	PORTA_PCR4 = 0x100;/*Changing the NMI to GPIO*/
+	GPIOB_PDDR |= (1 << 21);/*Setting the bit 21 of the port B as Output*/
+	GPIOB_PDDR |= (1 << 22);/*Setting the bit 22 of the port B as Output*/
+	GPIOC_PDDR |= (0 << 6);/*Setting the bit 6 of the port C as Input*/
+	/*Turn off Red and Blue Leds*/
+	GPIOB_PDOR |= (1 << 22);/*Turn Off Red Led*/
+	GPIOB_PDOR |= (1 << 21);/*Turn Off Blue Led*/
+
+	PORTC_ISFR = PORT_ISFR_ISF(0x40); /* Clear interrupt status flag */
+	NVIC_EnableIRQ(PORTC_IRQn);/*Enable the PORTC interrupt*/
+
+	for(;;)
+	{
+		GPIOB_PTOR |= (1 << 22); /*Red LED blinking*/
+		DelayFunction();
+	}
+	return 0;
+}
+
+void PORTC_IRQHandler(void)
+{
+	DelayFunction();
+	GPIOB_PSOR |= (1 << 22);/*Turn Off Red Led*/
+	GPIOB_PCOR |= (1 << 21);/*Turn On Blue Led*/
+	DelayFunction();
+	GPIOB_PSOR |= (1 << 21);/*Turn Off Blue Led*/
+	DelayFunction();
+	PORTC_ISFR = PORT_ISFR_ISF(0x40);/* Clear interrupt status flag */
+}
+
+void DelayFunction(void)
+{
+	int cnt;
+	for(cnt=0; cnt<1000000; cnt++)
+	{
+
+	}
+}
diff --git a/Workspace/RemoteSystemsTempFiles/.project b/Workspace/RemoteSystemsTempFiles/.project
new file mode 100644
index 0000000..5447a64
--- /dev/null
+++ b/Workspace/RemoteSystemsTempFiles/.project
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>RemoteSystemsTempFiles</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.rse.ui.remoteSystemsTempNature</nature>
+	</natures>
+</projectDescription>
diff --git a/Workspace/UART/.cproject b/Workspace/UART/.cproject
new file mode 100644
index 0000000..6b51f26
--- /dev/null
+++ b/Workspace/UART/.cproject
@@ -0,0 +1,128 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<macros>
+					<stringMacro name="PROJECT_KSDK_PATH" type="VALUE_TEXT" value="C:\Freescale\KSDK_1.3.0"/>
+				</macros>
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="GPIO" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934." name="/" resourcePath="">
+						<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.138424891" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.671934056" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1175035411" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1895319972" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.983170211" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.161883849" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1925652539" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.max" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.11219160" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.67316860" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.12133355" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.hard" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.295274606" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.fpv4spd16" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.473892561" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="GNU Tools for ARM Embedded Processors" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.1644050763" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.1421551701" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.446926023" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.611553597" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.1316335364" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.178354009" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.996371827" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.312855577" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.790468637" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" value="ar" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.1774832244" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1114519651" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.584099008" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder buildPath="${workspace_loc:/GPIO}/Debug" id="ilg.gnuarmeclipse.managedbuild.cross.builder.2018125917" name="Gnu Make Builder.Debug" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.2120002892" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.538999987" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.1145931798" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1102412416" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.154764793" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.c99" valueType="enumerated"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.100594230" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;../Sources&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../Project_Settings/Startup_Code&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/CMSIS/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices/MK64F12/include&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.831650274" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="&quot;CPU_MK64FN1M0VMD12&quot;"/>
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.13072522" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1648336251" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.1971374264" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;../Sources&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../Project_Settings/Startup_Code&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/CMSIS/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;../SDK/platform/devices/MK64F12/include&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.1311446966" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="&quot;CPU_MK64FN1M0VMD12&quot;"/>
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.1060554805" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.536657092" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.613993163" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.462759647" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.1291283292" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.416132893" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.2026894627" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="-specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs" valueType="string"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.1394898970" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="&quot;MK64FN1M0xxx12_flash.ld&quot;"/>
+								</option>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.672556956" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1276352763" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.830299569" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.282145612" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.2110003551" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.1898028372" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.338169926" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1783546987" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1190073944" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.805423770" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.1404268138" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="GPIO.ilg.gnuarmeclipse.managedbuild.cross.target.elf.1672910064" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1102412416;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.13072522">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1648336251;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.1060554805">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>
diff --git a/Workspace/UART/.cwGeneratedFileSetLog b/Workspace/UART/.cwGeneratedFileSetLog
new file mode 100644
index 0000000..da94cd8
--- /dev/null
+++ b/Workspace/UART/.cwGeneratedFileSetLog
@@ -0,0 +1,19 @@
+Sources/main.c
+Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
+SDK/platform/devices/MK64F12/include/MK64F12_extension.h
+SDK/platform/CMSIS/Include/arm_math.h
+SDK/platform/CMSIS/Include/core_cmSimd.h
+SDK/platform/devices/MK64F12/include/MK64F12.h
+SDK/platform/CMSIS/Include/core_cm4.h
+SDK/platform/CMSIS/Include/arm_common_tables.h
+SDK/platform/devices/MK64F12/include/MK64F12_features.h
+SDK/platform/devices/fsl_device_registers.h
+SDK/platform/CMSIS/Include/arm_const_structs.h
+SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
+SDK/platform/CMSIS/Include/core_cmFunc.h
+SDK/platform/CMSIS/Include/core_cmInstr.h
+Project_Settings/Startup_Code/system_MK64F12.h
+Project_Settings/Startup_Code/startup.c
+Project_Settings/Startup_Code/startup_MK64F12.S
+Project_Settings/Startup_Code/startup.h
+Project_Settings/Startup_Code/system_MK64F12.c
\ No newline at end of file
diff --git a/Workspace/UART/.project b/Workspace/UART/.project
new file mode 100644
index 0000000..9e9fe49
--- /dev/null
+++ b/Workspace/UART/.project
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>UART</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<variableList>
+		<variable>
+			<name>PROJECT_KSDK_PATH</name>
+			<value>file:/C:/Freescale/KSDK_1.3.0</value>
+		</variable>
+	</variableList>
+</projectDescription>
diff --git a/Workspace/UART/.settings/com.freescale.processorexpert.derivative.prefs b/Workspace/UART/.settings/com.freescale.processorexpert.derivative.prefs
new file mode 100644
index 0000000..60d5016
--- /dev/null
+++ b/Workspace/UART/.settings/com.freescale.processorexpert.derivative.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+versionGenerated/versionGenerated=1.0.0.RT7_b1550-0615
diff --git a/Workspace/UART/.settings/com.processorexpert.sdk.legacy.legacyprojectupdater.prefs b/Workspace/UART/.settings/com.processorexpert.sdk.legacy.legacyprojectupdater.prefs
new file mode 100644
index 0000000..7733bda
--- /dev/null
+++ b/Workspace/UART/.settings/com.processorexpert.sdk.legacy.legacyprojectupdater.prefs
@@ -0,0 +1 @@
+skip=true
\ No newline at end of file
diff --git a/Workspace/UART/.settings/language.settings.xml b/Workspace/UART/.settings/language.settings.xml
new file mode 100644
index 0000000..63c81d5
--- /dev/null
+++ b/Workspace/UART/.settings/language.settings.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.81132934" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="355957199812988073" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings Cross ARM" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>
diff --git a/Workspace/UART/Debug/GPIO.elf b/Workspace/UART/Debug/GPIO.elf
new file mode 100644
index 0000000..c62ab6e
Binary files /dev/null and b/Workspace/UART/Debug/GPIO.elf differ
diff --git a/Workspace/UART/Debug/GPIO.map b/Workspace/UART/Debug/GPIO.map
new file mode 100644
index 0000000..2f6ffee
--- /dev/null
+++ b/Workspace/UART/Debug/GPIO.map
@@ -0,0 +1,619 @@
+Archive member included because of file (symbol)
+
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (exit)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_global_impure_ptr)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (__libc_init_array)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o (memset)
+c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                              c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o) (_exit)
+
+Discarded input sections
+
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .data          0x00000000        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.extab     0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .group         0x00000000        0x8 ./Sources/main.o
+ .text          0x00000000        0x0 ./Sources/main.o
+ .data          0x00000000        0x0 ./Sources/main.o
+ .bss           0x00000000        0x0 ./Sources/main.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/startup.o
+ .text          0x00000000        0x0 ./Project_Settings/Startup_Code/startup.o
+ .data          0x00000000        0x0 ./Project_Settings/Startup_Code/startup.o
+ .bss           0x00000000        0x0 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00000000      0x856 ./Project_Settings/Startup_Code/startup.o
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+ .debug_macro   0x00000000       0x16 ./Project_Settings/Startup_Code/startup.o
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+ .debug_macro   0x00000000    0x1773b ./Project_Settings/Startup_Code/startup.o
+ .data          0x00000000        0x0 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .bss           0x00000000        0x0 ./Project_Settings/Startup_Code/startup_MK64F12.o
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+ .group         0x00000000        0x8 ./Project_Settings/Startup_Code/system_MK64F12.o
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+ .bss           0x00000000        0x0 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .data.SystemCoreClock
+                0x00000000        0x4 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .text.SystemCoreClockUpdate
+                0x00000000      0x270 ./Project_Settings/Startup_Code/system_MK64F12.o
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+ .debug_macro   0x00000000     0x1182 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .data._impure_ptr
+                0x00000000        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .eh_frame      0x00000000        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .text          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .data          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ .bss           0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+m_interrupts     0x00000000         0x00000400         xr
+m_flash_config   0x00000400         0x00000010         xr
+m_text           0x00000410         0x000ffbf0         xr
+m_data           0x1fff0000         0x00010000         rw
+m_data_2         0x20000000         0x00030000         rw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+LOAD ./Sources/main.o
+LOAD ./Project_Settings/Startup_Code/startup.o
+LOAD ./Project_Settings/Startup_Code/startup_MK64F12.o
+LOAD ./Project_Settings/Startup_Code/system_MK64F12.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libstdc++_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libm.a
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+START GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu\libgcc.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libc_s.a
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a
+END GROUP
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+LOAD c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000400                HEAP_SIZE = DEFINED (__heap_size__)?__heap_size__:0x400
+                0x00000400                STACK_SIZE = DEFINED (__stack_size__)?__stack_size__:0x400
+                0x00000000                M_VECTOR_RAM_SIZE = DEFINED (__ram_vector_table__)?0x400:0x0
+
+.interrupts     0x00000000      0x400
+                0x00000000                __VECTOR_TABLE = .
+                0x00000000                . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector    0x00000000      0x400 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000000                __isr_vector
+                0x00000400                . = ALIGN (0x4)
+
+.flash_config   0x00000400       0x10
+                0x00000400                . = ALIGN (0x4)
+ *(.FlashConfig)
+ .FlashConfig   0x00000400       0x10 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x00000410                . = ALIGN (0x4)
+
+.text           0x00000410      0x3f0
+                0x00000410                . = ALIGN (0x4)
+ *(.text)
+ .text          0x00000410       0x54 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .text          0x00000464       0x74 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00000464                _start
+                0x00000464                _mainCRTStartup
+ .text          0x000004d8       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+                0x000004d8                Reset_Handler
+                0x000004e8                DebugMon_Handler
+                0x000004e8                I2C0_IRQHandler
+                0x000004e8                HardFault_Handler
+                0x000004e8                SysTick_Handler
+                0x000004e8                UART3_RX_TX_IRQHandler
+                0x000004e8                PendSV_Handler
+                0x000004e8                NMI_Handler
+                0x000004e8                UART0_RX_TX_IRQHandler
+                0x000004e8                I2C1_IRQHandler
+                0x000004e8                DMA2_IRQHandler
+                0x000004e8                ENET_Error_IRQHandler
+                0x000004e8                CAN0_Tx_Warning_IRQHandler
+                0x000004e8                PIT0_IRQHandler
+                0x000004e8                CAN0_ORed_Message_buffer_IRQHandler
+                0x000004e8                CMP2_IRQHandler
+                0x000004e8                LLWU_IRQHandler
+                0x000004e8                ENET_Receive_IRQHandler
+                0x000004e8                ENET_1588_Timer_IRQHandler
+                0x000004e8                UART2_RX_TX_IRQHandler
+                0x000004e8                SWI_IRQHandler
+                0x000004e8                ADC0_IRQHandler
+                0x000004e8                UsageFault_Handler
+                0x000004e8                I2S0_Tx_IRQHandler
+                0x000004e8                CMT_IRQHandler
+                0x000004e8                UART4_RX_TX_IRQHandler
+                0x000004e8                SPI1_IRQHandler
+                0x000004e8                DefaultISR
+                0x000004e8                DMA9_IRQHandler
+                0x000004e8                DMA14_IRQHandler
+                0x000004e8                CMP1_IRQHandler
+                0x000004e8                Reserved71_IRQHandler
+                0x000004e8                PORTD_IRQHandler
+                0x000004e8                PORTB_IRQHandler
+                0x000004e8                UART4_ERR_IRQHandler
+                0x000004e8                ADC1_IRQHandler
+                0x000004e8                I2C2_IRQHandler
+                0x000004e8                PIT2_IRQHandler
+                0x000004e8                I2S0_Rx_IRQHandler
+                0x000004e8                DMA5_IRQHandler
+                0x000004e8                RTC_IRQHandler
+                0x000004e8                PDB0_IRQHandler
+                0x000004e8                CAN0_Rx_Warning_IRQHandler
+                0x000004e8                FTM1_IRQHandler
+                0x000004e8                UART5_RX_TX_IRQHandler
+                0x000004e8                UART3_ERR_IRQHandler
+                0x000004e8                PIT3_IRQHandler
+                0x000004e8                SDHC_IRQHandler
+                0x000004e8                RTC_Seconds_IRQHandler
+                0x000004e8                MCG_IRQHandler
+                0x000004e8                FTFE_IRQHandler
+                0x000004e8                UART2_ERR_IRQHandler
+                0x000004e8                DMA11_IRQHandler
+                0x000004e8                UART5_ERR_IRQHandler
+                0x000004e8                Read_Collision_IRQHandler
+                0x000004e8                DMA7_IRQHandler
+                0x000004e8                ENET_Transmit_IRQHandler
+                0x000004e8                USBDCD_IRQHandler
+                0x000004e8                USB0_IRQHandler
+                0x000004e8                SPI2_IRQHandler
+                0x000004e8                WDOG_EWM_IRQHandler
+                0x000004e8                MemManage_Handler
+                0x000004e8                SVC_Handler
+                0x000004e8                DMA13_IRQHandler
+                0x000004e8                DMA3_IRQHandler
+                0x000004e8                UART0_LON_IRQHandler
+                0x000004e8                RNG_IRQHandler
+                0x000004e8                DMA0_IRQHandler
+                0x000004e8                DMA15_IRQHandler
+                0x000004e8                DAC0_IRQHandler
+                0x000004e8                CAN0_Error_IRQHandler
+                0x000004e8                DMA4_IRQHandler
+                0x000004e8                PIT1_IRQHandler
+                0x000004e8                UART0_ERR_IRQHandler
+                0x000004e8                DMA_Error_IRQHandler
+                0x000004e8                LVD_LVW_IRQHandler
+                0x000004e8                SPI0_IRQHandler
+                0x000004e8                FTM0_IRQHandler
+                0x000004e8                PORTA_IRQHandler
+                0x000004e8                DAC1_IRQHandler
+                0x000004e8                MCM_IRQHandler
+                0x000004e8                DMA12_IRQHandler
+                0x000004e8                CAN0_Bus_Off_IRQHandler
+                0x000004e8                FTM3_IRQHandler
+                0x000004e8                PORTE_IRQHandler
+                0x000004e8                FTM2_IRQHandler
+                0x000004e8                LPTMR0_IRQHandler
+                0x000004e8                BusFault_Handler
+                0x000004e8                DMA8_IRQHandler
+                0x000004e8                DMA10_IRQHandler
+                0x000004e8                CAN0_Wake_Up_IRQHandler
+                0x000004e8                UART1_ERR_IRQHandler
+                0x000004e8                UART1_RX_TX_IRQHandler
+                0x000004e8                CMP0_IRQHandler
+                0x000004e8                PORTC_IRQHandler
+                0x000004e8                DMA6_IRQHandler
+                0x000004e8                DMA1_IRQHandler
+ *(.text*)
+ .text.main     0x000004ec       0xcc ./Sources/main.o
+                0x000004ec                main
+ .text.uart_getchar
+                0x000005b8       0x28 ./Sources/main.o
+                0x000005b8                uart_getchar
+ .text.uart_putchar
+                0x000005e0       0x30 ./Sources/main.o
+                0x000005e0                uart_putchar
+ .text.put      0x00000610       0x28 ./Sources/main.o
+                0x00000610                put
+ .text.init_data_bss
+                0x00000638       0xcc ./Project_Settings/Startup_Code/startup.o
+                0x00000638                init_data_bss
+ .text.SystemInit
+                0x00000704       0x3c ./Project_Settings/Startup_Code/system_MK64F12.o
+                0x00000704                SystemInit
+ .text.exit     0x00000740       0x28 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+                0x00000740                exit
+ .text.__libc_init_array
+                0x00000768       0x4c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+                0x00000768                __libc_init_array
+ .text.memset   0x000007b4       0x10 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+                0x000007b4                memset
+ .text._exit    0x000007c4        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+                0x000007c4                _exit
+ *(.rodata)
+ .rodata        0x000007c8       0x18 ./Sources/main.o
+ *(.rodata*)
+ .rodata.str1.1
+                0x000007e0        0x2 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *fill*         0x000007e2        0x2 
+ .rodata._global_impure_ptr
+                0x000007e4        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+                0x000007e4                _global_impure_ptr
+ *(.glue_7)
+ .glue_7        0x00000000        0x0 linker stubs
+ *(.glue_7t)
+ .glue_7t       0x00000000        0x0 linker stubs
+ *(.eh_frame)
+ .eh_frame      0x000007e8        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.init)
+ .init          0x000007e8        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x000007e8                _init
+ .init          0x000007ec        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+ *(.fini)
+ .fini          0x000007f4        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+                0x000007f4                _fini
+ .fini          0x000007f8        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000800                . = ALIGN (0x4)
+
+.vfp11_veneer   0x00000800        0x0
+ .vfp11_veneer  0x00000000        0x0 linker stubs
+
+.v4_bx          0x00000800        0x0
+ .v4_bx         0x00000000        0x0 linker stubs
+
+.iplt           0x00000800        0x0
+ .iplt          0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+.ARM            0x00000800        0x8
+                0x00000800                __exidx_start = .
+ *(.ARM.exidx*)
+ .ARM.exidx     0x00000800        0x8 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+                0x00000808                __exidx_end = .
+
+.rel.dyn        0x00000808        0x0
+ .rel.iplt      0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.ctors          0x00000808        0x0
+                0x00000808                __CTOR_LIST__ = .
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+                0x00000808                __CTOR_END__ = .
+
+.dtors          0x00000808        0x0
+                0x00000808                __DTOR_LIST__ = .
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+                0x00000808                __DTOR_END__ = .
+
+.preinit_array  0x00000808        0x0
+                0x00000808                PROVIDE (__preinit_array_start, .)
+ *(.preinit_array*)
+                0x00000808                PROVIDE (__preinit_array_end, .)
+
+.init_array     0x00000808        0x4
+                0x00000808                PROVIDE (__init_array_start, .)
+ *(SORT(.init_array.*))
+ *(.init_array*)
+ .init_array    0x00000808        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x0000080c                PROVIDE (__init_array_end, .)
+
+.fini_array     0x0000080c        0x4
+                0x0000080c                PROVIDE (__fini_array_start, .)
+ *(SORT(.fini_array.*))
+ *(.fini_array*)
+ .fini_array    0x0000080c        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+                0x00000810                PROVIDE (__fini_array_end, .)
+                0x00000810                __etext = .
+                0x00000810                __DATA_ROM = .
+
+.interrupts_ram
+                0x1fff0000        0x0
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __VECTOR_RAM__ = .
+                0x1fff0000                __interrupts_ram_start__ = .
+ *(.m_interrupts_ram)
+                0x1fff0000                . = (. + M_VECTOR_RAM_SIZE)
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __interrupts_ram_end__ = .
+                0x00000000                __VECTOR_RAM = DEFINED (__ram_vector_table__)?__VECTOR_RAM__:ORIGIN (m_interrupts)
+                0x00000000                __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED (__ram_vector_table__)?(__interrupts_ram_end__ - __interrupts_ram_start__):0x0
+
+.data           0x1fff0000       0x64 load address 0x00000810
+                0x1fff0000                . = ALIGN (0x4)
+                0x1fff0000                __DATA_RAM = .
+                0x1fff0000                __data_start__ = .
+ *(.data)
+ *(.data*)
+ .data.impure_data
+                0x1fff0000       0x60 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ *(.jcr*)
+ .jcr           0x1fff0060        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .jcr           0x1fff0060        0x4 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __data_end__ = .
+                0x00000874                __DATA_END = (__DATA_ROM + (__data_end__ - __data_start__))
+                0x00100000                text_end = (ORIGIN (m_text) + 0xffbf0)
+                0x00000001                ASSERT ((__DATA_END <= text_end), region m_text overflowed with text and data)
+
+.igot.plt       0x1fff0064        0x0 load address 0x00000874
+ .igot.plt      0x00000000        0x0 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+
+.bss            0x1fff0064       0x1c load address 0x00000874
+                0x1fff0064                . = ALIGN (0x4)
+                0x1fff0064                __START_BSS = .
+                0x1fff0064                __bss_start__ = .
+ *(.bss)
+ .bss           0x1fff0064       0x1c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ *(.bss*)
+ *(COMMON)
+                0x1fff0080                . = ALIGN (0x4)
+                0x1fff0080                __bss_end__ = .
+                0x1fff0080                __END_BSS = .
+
+.heap           0x20000000      0x400
+                0x20000000                . = ALIGN (0x8)
+                0x20000000                __end__ = .
+                0x20000000                PROVIDE (end, .)
+                0x20000000                __HeapBase = .
+                0x20000400                . = (. + HEAP_SIZE)
+ *fill*         0x20000000      0x400 
+                0x20000400                __HeapLimit = .
+
+.stack          0x20000400      0x400
+                0x20000400                . = ALIGN (0x8)
+                0x20000800                . = (. + STACK_SIZE)
+ *fill*         0x20000400      0x400 
+                0x20030000                __StackTop = (ORIGIN (m_data_2) + 0x30000)
+                0x2002fc00                __StackLimit = (__StackTop - STACK_SIZE)
+                0x20030000                PROVIDE (__stack, __StackTop)
+
+.ARM.attributes
+                0x00000000       0x30
+ *(.ARM.attributes)
+ .ARM.attributes
+                0x00000000       0x22 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crti.o
+ .ARM.attributes
+                0x00000022       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtbegin.o
+ .ARM.attributes
+                0x00000056       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu/crt0.o
+ .ARM.attributes
+                0x00000076       0x39 ./Sources/main.o
+ .ARM.attributes
+                0x000000af       0x39 ./Project_Settings/Startup_Code/startup.o
+ .ARM.attributes
+                0x000000e8       0x1f ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .ARM.attributes
+                0x00000107       0x39 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .ARM.attributes
+                0x00000140       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .ARM.attributes
+                0x00000174       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-impure.o)
+ .ARM.attributes
+                0x000001a8       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .ARM.attributes
+                0x000001dc       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .ARM.attributes
+                0x00000210       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
+ .ARM.attributes
+                0x00000244       0x34 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtend.o
+ .ARM.attributes
+                0x00000278       0x22 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7e-m/fpu/crtn.o
+                0x00000001                ASSERT ((__StackLimit >= __HeapLimit), region m_data_2 overflowed with stack and heap)
+OUTPUT(GPIO.elf elf32-littlearm)
+
+.debug_info     0x00000000     0x1028
+ .debug_info    0x00000000      0x5e7 ./Sources/main.o
+ .debug_info    0x000005e7      0x3a7 ./Project_Settings/Startup_Code/startup.o
+ .debug_info    0x0000098e       0x8a ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_info    0x00000a18      0x610 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_abbrev   0x00000000      0x3c0
+ .debug_abbrev  0x00000000      0x198 ./Sources/main.o
+ .debug_abbrev  0x00000198       0xfa ./Project_Settings/Startup_Code/startup.o
+ .debug_abbrev  0x00000292       0x14 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_abbrev  0x000002a6      0x11a ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_aranges  0x00000000       0xa0
+ .debug_aranges
+                0x00000000       0x38 ./Sources/main.o
+ .debug_aranges
+                0x00000038       0x20 ./Project_Settings/Startup_Code/startup.o
+ .debug_aranges
+                0x00000058       0x20 ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_aranges
+                0x00000078       0x28 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_ranges   0x00000000       0x50
+ .debug_ranges  0x00000000       0x28 ./Sources/main.o
+ .debug_ranges  0x00000028       0x10 ./Project_Settings/Startup_Code/startup.o
+ .debug_ranges  0x00000038       0x18 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_macro    0x00000000    0x30d8e
+ .debug_macro   0x00000000       0x8d ./Sources/main.o
+ .debug_macro   0x0000008d      0x856 ./Sources/main.o
+ .debug_macro   0x000008e3       0x16 ./Sources/main.o
+ .debug_macro   0x000008f9       0x16 ./Sources/main.o
+ .debug_macro   0x0000090f       0x44 ./Sources/main.o
+ .debug_macro   0x00000953      0x209 ./Sources/main.o
+ .debug_macro   0x00000b5c       0x56 ./Sources/main.o
+ .debug_macro   0x00000bb2       0x3b ./Sources/main.o
+ .debug_macro   0x00000bed       0x34 ./Sources/main.o
+ .debug_macro   0x00000c21       0x26 ./Sources/main.o
+ .debug_macro   0x00000c47      0xd1d ./Sources/main.o
+ .debug_macro   0x00001964       0x78 ./Sources/main.o
+ .debug_macro   0x000019dc    0x1773b ./Sources/main.o
+ .debug_macro   0x00019117      0x171 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019288       0x11 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019299       0x58 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000192f1       0x35 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019326       0xa3 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193c9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000193df      0x10e ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000194ed       0x7f ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0001956c       0x52 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195be       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000195d4       0x43 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019617      0x180 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00019797       0x22 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197b9       0x16 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x000197cf    0x16273 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x0002fa42     0x1182 ./Project_Settings/Startup_Code/startup.o
+ .debug_macro   0x00030bc4      0x162 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_macro   0x00030d26       0x68 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_line     0x00000000      0x9de
+ .debug_line    0x00000000      0x291 ./Sources/main.o
+ .debug_line    0x00000291      0x358 ./Project_Settings/Startup_Code/startup.o
+ .debug_line    0x000005e9       0x6a ./Project_Settings/Startup_Code/startup_MK64F12.o
+ .debug_line    0x00000653      0x38b ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_str      0x00000000   0x19cb52
+ .debug_str     0x00000000    0x8fb78 ./Sources/main.o
+                              0x8fcf6 (size before relaxing)
+ .debug_str     0x0008fb78   0x10cef0 ./Project_Settings/Startup_Code/startup.o
+                             0x19ca78 (size before relaxing)
+ .debug_str     0x0019ca68       0xea ./Project_Settings/Startup_Code/system_MK64F12.o
+                             0x19cb33 (size before relaxing)
+
+.comment        0x00000000       0x70
+ .comment       0x00000000       0x70 ./Sources/main.o
+                                 0x71 (size before relaxing)
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/startup.o
+ .comment       0x00000000       0x71 ./Project_Settings/Startup_Code/system_MK64F12.o
+
+.debug_frame    0x00000000      0x188
+ .debug_frame   0x00000000       0x84 ./Sources/main.o
+ .debug_frame   0x00000084       0x2c ./Project_Settings/Startup_Code/startup.o
+ .debug_frame   0x000000b0       0x44 ./Project_Settings/Startup_Code/system_MK64F12.o
+ .debug_frame   0x000000f4       0x28 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-exit.o)
+ .debug_frame   0x0000011c       0x2c c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-init.o)
+ .debug_frame   0x00000148       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libg_s.a(lib_a-memset.o)
+ .debug_frame   0x00000168       0x20 c:/freescale/kds_v3/toolchain/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7e-m/fpu\libnosys.a(_exit.o)
diff --git a/Workspace/UART/Debug/Project_Settings/Startup_Code/startup.d b/Workspace/UART/Debug/Project_Settings/Startup_Code/startup.d
new file mode 100644
index 0000000..09df623
--- /dev/null
+++ b/Workspace/UART/Debug/Project_Settings/Startup_Code/startup.d
@@ -0,0 +1,38 @@
+Project_Settings/Startup_Code/startup.o: \
+ ../Project_Settings/Startup_Code/startup.c \
+ ../Project_Settings/Startup_Code/startup.h \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h
+
+../Project_Settings/Startup_Code/startup.h:
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
diff --git a/Workspace/UART/Debug/Project_Settings/Startup_Code/startup.o b/Workspace/UART/Debug/Project_Settings/Startup_Code/startup.o
new file mode 100644
index 0000000..83add89
Binary files /dev/null and b/Workspace/UART/Debug/Project_Settings/Startup_Code/startup.o differ
diff --git a/Workspace/UART/Debug/Project_Settings/Startup_Code/startup_MK64F12.d b/Workspace/UART/Debug/Project_Settings/Startup_Code/startup_MK64F12.d
new file mode 100644
index 0000000..15e90f1
--- /dev/null
+++ b/Workspace/UART/Debug/Project_Settings/Startup_Code/startup_MK64F12.d
@@ -0,0 +1,2 @@
+Project_Settings/Startup_Code/startup_MK64F12.o: \
+ ../Project_Settings/Startup_Code/startup_MK64F12.S
diff --git a/Workspace/UART/Debug/Project_Settings/Startup_Code/startup_MK64F12.o b/Workspace/UART/Debug/Project_Settings/Startup_Code/startup_MK64F12.o
new file mode 100644
index 0000000..abfb149
Binary files /dev/null and b/Workspace/UART/Debug/Project_Settings/Startup_Code/startup_MK64F12.o differ
diff --git a/Workspace/UART/Debug/Project_Settings/Startup_Code/subdir.mk b/Workspace/UART/Debug/Project_Settings/Startup_Code/subdir.mk
new file mode 100644
index 0000000..1e5a1fb
--- /dev/null
+++ b/Workspace/UART/Debug/Project_Settings/Startup_Code/subdir.mk
@@ -0,0 +1,41 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Project_Settings/Startup_Code/startup.c \
+../Project_Settings/Startup_Code/system_MK64F12.c 
+
+S_UPPER_SRCS += \
+../Project_Settings/Startup_Code/startup_MK64F12.S 
+
+OBJS += \
+./Project_Settings/Startup_Code/startup.o \
+./Project_Settings/Startup_Code/startup_MK64F12.o \
+./Project_Settings/Startup_Code/system_MK64F12.o 
+
+C_DEPS += \
+./Project_Settings/Startup_Code/startup.d \
+./Project_Settings/Startup_Code/system_MK64F12.d 
+
+S_UPPER_DEPS += \
+./Project_Settings/Startup_Code/startup_MK64F12.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Project_Settings/Startup_Code/%.o: ../Project_Settings/Startup_Code/%.c
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM C Compiler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+Project_Settings/Startup_Code/%.o: ../Project_Settings/Startup_Code/%.S
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM GNU Assembler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+
diff --git a/Workspace/UART/Debug/Project_Settings/Startup_Code/system_MK64F12.d b/Workspace/UART/Debug/Project_Settings/Startup_Code/system_MK64F12.d
new file mode 100644
index 0000000..d0e2961
--- /dev/null
+++ b/Workspace/UART/Debug/Project_Settings/Startup_Code/system_MK64F12.d
@@ -0,0 +1,35 @@
+Project_Settings/Startup_Code/system_MK64F12.o: \
+ ../Project_Settings/Startup_Code/system_MK64F12.c \
+ ../SDK/platform/devices/fsl_device_registers.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_extension.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h \
+ ../SDK/platform/devices/MK64F12/include/MK64F12_features.h
+
+../SDK/platform/devices/fsl_device_registers.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_extension.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/devices/MK64F12/include/fsl_bitaccess.h:
+
+../SDK/platform/devices/MK64F12/include/MK64F12_features.h:
diff --git a/Workspace/UART/Debug/Project_Settings/Startup_Code/system_MK64F12.o b/Workspace/UART/Debug/Project_Settings/Startup_Code/system_MK64F12.o
new file mode 100644
index 0000000..0dd820e
Binary files /dev/null and b/Workspace/UART/Debug/Project_Settings/Startup_Code/system_MK64F12.o differ
diff --git a/Workspace/UART/Debug/Sources/main.d b/Workspace/UART/Debug/Sources/main.d
new file mode 100644
index 0000000..6984a8b
--- /dev/null
+++ b/Workspace/UART/Debug/Sources/main.d
@@ -0,0 +1,19 @@
+Sources/main.o: ../Sources/main.c \
+ ../SDK/platform/devices/MK64F12/include/MK64F12.h \
+ ../SDK/platform/CMSIS/Include/core_cm4.h \
+ ../SDK/platform/CMSIS/Include/core_cmInstr.h \
+ ../SDK/platform/CMSIS/Include/core_cmFunc.h \
+ ../SDK/platform/CMSIS/Include/core_cmSimd.h \
+ ../Project_Settings/Startup_Code/system_MK64F12.h
+
+../SDK/platform/devices/MK64F12/include/MK64F12.h:
+
+../SDK/platform/CMSIS/Include/core_cm4.h:
+
+../SDK/platform/CMSIS/Include/core_cmInstr.h:
+
+../SDK/platform/CMSIS/Include/core_cmFunc.h:
+
+../SDK/platform/CMSIS/Include/core_cmSimd.h:
+
+../Project_Settings/Startup_Code/system_MK64F12.h:
diff --git a/Workspace/UART/Debug/Sources/main.o b/Workspace/UART/Debug/Sources/main.o
new file mode 100644
index 0000000..dd8b2f1
Binary files /dev/null and b/Workspace/UART/Debug/Sources/main.o differ
diff --git a/Workspace/UART/Debug/Sources/subdir.mk b/Workspace/UART/Debug/Sources/subdir.mk
new file mode 100644
index 0000000..95aa41f
--- /dev/null
+++ b/Workspace/UART/Debug/Sources/subdir.mk
@@ -0,0 +1,24 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Sources/main.c 
+
+OBJS += \
+./Sources/main.o 
+
+C_DEPS += \
+./Sources/main.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Sources/%.o: ../Sources/%.c
+	@echo 'Building file: $<'
+	@echo 'Invoking: Cross ARM C Compiler'
+	arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -D"CPU_MK64FN1M0VMD12" -I"../Sources" -I"../Project_Settings/Startup_Code" -I"../SDK/platform/CMSIS/Include" -I"../SDK/platform/devices" -I"../SDK/platform/devices/MK64F12/include" -std=c99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" -c -o "$@" "$<"
+	@echo 'Finished building: $<'
+	@echo ' '
+
+
diff --git a/Workspace/UART/Debug/makefile b/Workspace/UART/Debug/makefile
new file mode 100644
index 0000000..d264e0e
--- /dev/null
+++ b/Workspace/UART/Debug/makefile
@@ -0,0 +1,77 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include Sources/subdir.mk
+-include Project_Settings/Startup_Code/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C++_DEPS)),)
+-include $(C++_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+ifneq ($(strip $(ASM_DEPS)),)
+-include $(ASM_DEPS)
+endif
+ifneq ($(strip $(CC_DEPS)),)
+-include $(CC_DEPS)
+endif
+ifneq ($(strip $(CPP_DEPS)),)
+-include $(CPP_DEPS)
+endif
+ifneq ($(strip $(CXX_DEPS)),)
+-include $(CXX_DEPS)
+endif
+ifneq ($(strip $(C_UPPER_DEPS)),)
+-include $(C_UPPER_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables 
+SECONDARY_SIZE += \
+GPIO.siz \
+
+
+# All Target
+all: GPIO.elf secondary-outputs
+
+# Tool invocations
+GPIO.elf: $(OBJS) $(USER_OBJS)
+	@echo 'Building target: $@'
+	@echo 'Invoking: Cross ARM C++ Linker'
+	arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -Wall  -g3 -T "MK64FN1M0xxx12_flash.ld" -Xlinker --gc-sections -L"C:/Users/pkalgaon/Desktop/Workspace/UART/Project_Settings/Linker_Files" -Wl,-Map,"GPIO.map" -specs=nosys.specs -specs=nano.specs -Xlinker -z -Xlinker muldefs -o "GPIO.elf" $(OBJS) $(USER_OBJS) $(LIBS)
+	@echo 'Finished building target: $@'
+	@echo ' '
+
+GPIO.siz: GPIO.elf
+	@echo 'Invoking: Cross ARM GNU Print Size'
+	arm-none-eabi-size --format=berkeley "GPIO.elf"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+# Other Targets
+clean:
+	-$(RM) $(SECONDARY_SIZE)$(C++_DEPS)$(OBJS)$(C_DEPS)$(ASM_DEPS)$(CC_DEPS)$(CPP_DEPS)$(CXX_DEPS)$(C_UPPER_DEPS)$(S_UPPER_DEPS) GPIO.elf
+	-@echo ' '
+
+secondary-outputs: $(SECONDARY_SIZE)
+
+.PHONY: all clean dependents
+.SECONDARY:
+
+-include ../makefile.targets
diff --git a/Workspace/UART/Debug/objects.mk b/Workspace/UART/Debug/objects.mk
new file mode 100644
index 0000000..742c2da
--- /dev/null
+++ b/Workspace/UART/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/Workspace/UART/Debug/sources.mk b/Workspace/UART/Debug/sources.mk
new file mode 100644
index 0000000..80f8a41
--- /dev/null
+++ b/Workspace/UART/Debug/sources.mk
@@ -0,0 +1,31 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ELF_SRCS := 
+O_SRCS := 
+CPP_SRCS := 
+C_UPPER_SRCS := 
+C_SRCS := 
+S_UPPER_SRCS := 
+OBJ_SRCS := 
+ASM_SRCS := 
+CXX_SRCS := 
+C++_SRCS := 
+CC_SRCS := 
+SECONDARY_SIZE := 
+C++_DEPS := 
+OBJS := 
+C_DEPS := 
+ASM_DEPS := 
+CC_DEPS := 
+CPP_DEPS := 
+CXX_DEPS := 
+C_UPPER_DEPS := 
+S_UPPER_DEPS := 
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Sources \
+Project_Settings/Startup_Code \
+
diff --git a/Workspace/UART/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch b/Workspace/UART/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch
new file mode 100644
index 0000000..cae21a4
--- /dev/null
+++ b/Workspace/UART/Project_Settings/Debugger/GPIO_Debug_OpenOCD.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doConnectToRunning" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f kinetis.cfg"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/GPIO.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="GPIO"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/GPIO"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/UART/Project_Settings/Debugger/GPIO_Debug_Segger.launch b/Workspace/UART/Project_Settings/Debugger/GPIO_Debug_Segger.launch
new file mode 100644
index 0000000..68923d5
--- /dev/null
+++ b/Workspace/UART/Project_Settings/Debugger/GPIO_Debug_Segger.launch
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.jlink.launchConfigurationType">
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="MK64FN1M0xxx12"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="1000"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
+<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
+<intAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM J-Link"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/GPIO.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="GPIO"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/GPIO"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/Workspace/UART/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld b/Workspace/UART/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
new file mode 100644
index 0000000..506082b
--- /dev/null
+++ b/Workspace/UART/Project_Settings/Linker_Files/MK64FN1M0xxx12_flash.ld
@@ -0,0 +1,245 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150624
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
+  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0
+  m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
+  m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+  } > m_data_2
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data_2
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
+}
+
diff --git a/Workspace/UART/Project_Settings/Startup_Code/startup.c b/Workspace/UART/Project_Settings/Startup_Code/startup.c
new file mode 100644
index 0000000..b89e7fc
--- /dev/null
+++ b/Workspace/UART/Project_Settings/Startup_Code/startup.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "startup.h"
+#include "fsl_device_registers.h"
+
+#if (defined(__ICCARM__))
+    #pragma section = ".data"
+    #pragma section = ".data_init"
+    #pragma section = ".bss"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : init_data_bss
+ * Description   : Make necessary initializations for RAM.
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ *
+ * Tool Chians:
+ *   __GNUC__   : GCC
+ *   __CC_ARM   : KEIL
+ *   __ICCARM__ : IAR
+ *
+ *END**************************************************************************/
+void init_data_bss(void)
+{
+    uint32_t n; 
+    
+    /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+    #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base  
+    #define __VECTOR_RAM Image$$VECTOR_RAM$$Base  
+    #define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];  
+    extern uint32_t __VECTOR_RAM[];  
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif
+
+    if (__VECTOR_RAM != __VECTOR_TABLE)
+    {   
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+    else
+    {
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_TABLE;
+    }
+
+#if !defined(__CC_ARM) && !defined(__ICCARM__)
+    
+    /* Declare pointers for various data sections. These pointers
+     * are initialized using values pulled in from the linker file */
+    uint8_t * data_ram, * data_rom, * data_rom_end;
+    uint8_t * bss_start, * bss_end;
+
+    /* Get the addresses for the .data section (initialized data section) */
+#if defined(__GNUC__)
+    extern uint32_t __DATA_ROM[];
+    extern uint32_t __DATA_RAM[];
+    extern char __DATA_END[];
+    data_ram = (uint8_t *)__DATA_RAM;
+    data_rom = (uint8_t *)__DATA_ROM;
+    data_rom_end  = (uint8_t *)__DATA_END;
+    n = data_rom_end - data_rom;
+#endif
+
+    /* Copy initialized data from ROM to RAM */
+    while (n--)
+    {
+        *data_ram++ = *data_rom++;
+    }   
+    
+    /* Get the addresses for the .bss section (zero-initialized data) */
+#if defined(__GNUC__)
+    extern char __START_BSS[];
+    extern char __END_BSS[];
+    bss_start = (uint8_t *)__START_BSS;
+    bss_end = (uint8_t *)__END_BSS;
+#endif
+		
+    /* Clear the zero-initialized data section */
+    n = bss_end - bss_start;
+    while(n--)
+    {
+        *bss_start++ = 0;
+    }
+#endif /* !__CC_ARM && !__ICCARM__*/
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/Workspace/UART/Project_Settings/Startup_Code/startup.h b/Workspace/UART/Project_Settings/Startup_Code/startup.h
new file mode 100644
index 0000000..17ad55f
--- /dev/null
+++ b/Workspace/UART/Project_Settings/Startup_Code/startup.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _STARTUP_H_
+#define _STARTUP_H_
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+/*!
+ * @brief Make necessary initializations for RAM.
+ *
+ * - Copy initialized data from ROM to RAM.
+ * - Clear the zero-initialized data section.
+ * - Copy the vector table from ROM to RAM. This could be an option.  
+ */
+void init_data_bss(void);
+
+#endif /* _STARTUP_H_*/
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
+
diff --git a/Workspace/UART/Project_Settings/Startup_Code/startup_MK64F12.S b/Workspace/UART/Project_Settings/Startup_Code/startup_MK64F12.S
new file mode 100644
index 0000000..aebe2e6
--- /dev/null
+++ b/Workspace/UART/Project_Settings/Startup_Code/startup_MK64F12.S
@@ -0,0 +1,457 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MK64F12.s                                                           */
+/*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
+/*            MK64F12                                                                     */
+/*  @version: 2.8                                                                         */
+/*  @date:    2015-2-19                                                                   */
+/*  @build:   b150225                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
+/* All rights reserved.                                                                   */
+/*                                                                                        */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv7-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   MemManage_Handler                               /* MPU Fault Handler*/
+    .long   BusFault_Handler                                /* Bus Fault Handler*/
+    .long   UsageFault_Handler                              /* Usage Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_IRQHandler                                 /* DMA Channel 0 Transfer Complete*/
+    .long   DMA1_IRQHandler                                 /* DMA Channel 1 Transfer Complete*/
+    .long   DMA2_IRQHandler                                 /* DMA Channel 2 Transfer Complete*/
+    .long   DMA3_IRQHandler                                 /* DMA Channel 3 Transfer Complete*/
+    .long   DMA4_IRQHandler                                 /* DMA Channel 4 Transfer Complete*/
+    .long   DMA5_IRQHandler                                 /* DMA Channel 5 Transfer Complete*/
+    .long   DMA6_IRQHandler                                 /* DMA Channel 6 Transfer Complete*/
+    .long   DMA7_IRQHandler                                 /* DMA Channel 7 Transfer Complete*/
+    .long   DMA8_IRQHandler                                 /* DMA Channel 8 Transfer Complete*/
+    .long   DMA9_IRQHandler                                 /* DMA Channel 9 Transfer Complete*/
+    .long   DMA10_IRQHandler                                /* DMA Channel 10 Transfer Complete*/
+    .long   DMA11_IRQHandler                                /* DMA Channel 11 Transfer Complete*/
+    .long   DMA12_IRQHandler                                /* DMA Channel 12 Transfer Complete*/
+    .long   DMA13_IRQHandler                                /* DMA Channel 13 Transfer Complete*/
+    .long   DMA14_IRQHandler                                /* DMA Channel 14 Transfer Complete*/
+    .long   DMA15_IRQHandler                                /* DMA Channel 15 Transfer Complete*/
+    .long   DMA_Error_IRQHandler                            /* DMA Error Interrupt*/
+    .long   MCM_IRQHandler                                  /* Normal Interrupt*/
+    .long   FTFE_IRQHandler                                 /* FTFE Command complete interrupt*/
+    .long   Read_Collision_IRQHandler                       /* Read Collision Interrupt*/
+    .long   LVD_LVW_IRQHandler                              /* Low Voltage Detect, Low Voltage Warning*/
+    .long   LLWU_IRQHandler                                 /* Low Leakage Wakeup Unit*/
+    .long   WDOG_EWM_IRQHandler                             /* WDOG Interrupt*/
+    .long   RNG_IRQHandler                                  /* RNG Interrupt*/
+    .long   I2C0_IRQHandler                                 /* I2C0 interrupt*/
+    .long   I2C1_IRQHandler                                 /* I2C1 interrupt*/
+    .long   SPI0_IRQHandler                                 /* SPI0 Interrupt*/
+    .long   SPI1_IRQHandler                                 /* SPI1 Interrupt*/
+    .long   I2S0_Tx_IRQHandler                              /* I2S0 transmit interrupt*/
+    .long   I2S0_Rx_IRQHandler                              /* I2S0 receive interrupt*/
+    .long   UART0_LON_IRQHandler                            /* UART0 LON interrupt*/
+    .long   UART0_RX_TX_IRQHandler                          /* UART0 Receive/Transmit interrupt*/
+    .long   UART0_ERR_IRQHandler                            /* UART0 Error interrupt*/
+    .long   UART1_RX_TX_IRQHandler                          /* UART1 Receive/Transmit interrupt*/
+    .long   UART1_ERR_IRQHandler                            /* UART1 Error interrupt*/
+    .long   UART2_RX_TX_IRQHandler                          /* UART2 Receive/Transmit interrupt*/
+    .long   UART2_ERR_IRQHandler                            /* UART2 Error interrupt*/
+    .long   UART3_RX_TX_IRQHandler                          /* UART3 Receive/Transmit interrupt*/
+    .long   UART3_ERR_IRQHandler                            /* UART3 Error interrupt*/
+    .long   ADC0_IRQHandler                                 /* ADC0 interrupt*/
+    .long   CMP0_IRQHandler                                 /* CMP0 interrupt*/
+    .long   CMP1_IRQHandler                                 /* CMP1 interrupt*/
+    .long   FTM0_IRQHandler                                 /* FTM0 fault, overflow and channels interrupt*/
+    .long   FTM1_IRQHandler                                 /* FTM1 fault, overflow and channels interrupt*/
+    .long   FTM2_IRQHandler                                 /* FTM2 fault, overflow and channels interrupt*/
+    .long   CMT_IRQHandler                                  /* CMT interrupt*/
+    .long   RTC_IRQHandler                                  /* RTC interrupt*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds interrupt*/
+    .long   PIT0_IRQHandler                                 /* PIT timer channel 0 interrupt*/
+    .long   PIT1_IRQHandler                                 /* PIT timer channel 1 interrupt*/
+    .long   PIT2_IRQHandler                                 /* PIT timer channel 2 interrupt*/
+    .long   PIT3_IRQHandler                                 /* PIT timer channel 3 interrupt*/
+    .long   PDB0_IRQHandler                                 /* PDB0 Interrupt*/
+    .long   USB0_IRQHandler                                 /* USB0 interrupt*/
+    .long   USBDCD_IRQHandler                               /* USBDCD Interrupt*/
+    .long   Reserved71_IRQHandler                           /* Reserved interrupt 71*/
+    .long   DAC0_IRQHandler                                 /* DAC0 interrupt*/
+    .long   MCG_IRQHandler                                  /* MCG Interrupt*/
+    .long   LPTMR0_IRQHandler                               /* LPTimer interrupt*/
+    .long   PORTA_IRQHandler                                /* Port A interrupt*/
+    .long   PORTB_IRQHandler                                /* Port B interrupt*/
+    .long   PORTC_IRQHandler                                /* Port C interrupt*/
+    .long   PORTD_IRQHandler                                /* Port D interrupt*/
+    .long   PORTE_IRQHandler                                /* Port E interrupt*/
+    .long   SWI_IRQHandler                                  /* Software interrupt*/
+    .long   SPI2_IRQHandler                                 /* SPI2 Interrupt*/
+    .long   UART4_RX_TX_IRQHandler                          /* UART4 Receive/Transmit interrupt*/
+    .long   UART4_ERR_IRQHandler                            /* UART4 Error interrupt*/
+    .long   UART5_RX_TX_IRQHandler                          /* UART5 Receive/Transmit interrupt*/
+    .long   UART5_ERR_IRQHandler                            /* UART5 Error interrupt*/
+    .long   CMP2_IRQHandler                                 /* CMP2 interrupt*/
+    .long   FTM3_IRQHandler                                 /* FTM3 fault, overflow and channels interrupt*/
+    .long   DAC1_IRQHandler                                 /* DAC1 interrupt*/
+    .long   ADC1_IRQHandler                                 /* ADC1 interrupt*/
+    .long   I2C2_IRQHandler                                 /* I2C2 interrupt*/
+    .long   CAN0_ORed_Message_buffer_IRQHandler             /* CAN0 OR'd message buffers interrupt*/
+    .long   CAN0_Bus_Off_IRQHandler                         /* CAN0 bus off interrupt*/
+    .long   CAN0_Error_IRQHandler                           /* CAN0 error interrupt*/
+    .long   CAN0_Tx_Warning_IRQHandler                      /* CAN0 Tx warning interrupt*/
+    .long   CAN0_Rx_Warning_IRQHandler                      /* CAN0 Rx warning interrupt*/
+    .long   CAN0_Wake_Up_IRQHandler                         /* CAN0 wake up interrupt*/
+    .long   SDHC_IRQHandler                                 /* SDHC interrupt*/
+    .long   ENET_1588_Timer_IRQHandler                      /* Ethernet MAC IEEE 1588 Timer Interrupt*/
+    .long   ENET_Transmit_IRQHandler                        /* Ethernet MAC Transmit Interrupt*/
+    .long   ENET_Receive_IRQHandler                         /* Ethernet MAC Receive Interrupt*/
+    .long   ENET_Error_IRQHandler                           /* Ethernet MAC Error and miscelaneous Interrupt*/
+    .long   DefaultISR                                      /* 102*/
+    .long   DefaultISR                                      /* 103*/
+    .long   DefaultISR                                      /* 104*/
+    .long   DefaultISR                                      /* 105*/
+    .long   DefaultISR                                      /* 106*/
+    .long   DefaultISR                                      /* 107*/
+    .long   DefaultISR                                      /* 108*/
+    .long   DefaultISR                                      /* 109*/
+    .long   DefaultISR                                      /* 110*/
+    .long   DefaultISR                                      /* 111*/
+    .long   DefaultISR                                      /* 112*/
+    .long   DefaultISR                                      /* 113*/
+    .long   DefaultISR                                      /* 114*/
+    .long   DefaultISR                                      /* 115*/
+    .long   DefaultISR                                      /* 116*/
+    .long   DefaultISR                                      /* 117*/
+    .long   DefaultISR                                      /* 118*/
+    .long   DefaultISR                                      /* 119*/
+    .long   DefaultISR                                      /* 120*/
+    .long   DefaultISR                                      /* 121*/
+    .long   DefaultISR                                      /* 122*/
+    .long   DefaultISR                                      /* 123*/
+    .long   DefaultISR                                      /* 124*/
+    .long   DefaultISR                                      /* 125*/
+    .long   DefaultISR                                      /* 126*/
+    .long   DefaultISR                                      /* 127*/
+    .long   DefaultISR                                      /* 128*/
+    .long   DefaultISR                                      /* 129*/
+    .long   DefaultISR                                      /* 130*/
+    .long   DefaultISR                                      /* 131*/
+    .long   DefaultISR                                      /* 132*/
+    .long   DefaultISR                                      /* 133*/
+    .long   DefaultISR                                      /* 134*/
+    .long   DefaultISR                                      /* 135*/
+    .long   DefaultISR                                      /* 136*/
+    .long   DefaultISR                                      /* 137*/
+    .long   DefaultISR                                      /* 138*/
+    .long   DefaultISR                                      /* 139*/
+    .long   DefaultISR                                      /* 140*/
+    .long   DefaultISR                                      /* 141*/
+    .long   DefaultISR                                      /* 142*/
+    .long   DefaultISR                                      /* 143*/
+    .long   DefaultISR                                      /* 144*/
+    .long   DefaultISR                                      /* 145*/
+    .long   DefaultISR                                      /* 146*/
+    .long   DefaultISR                                      /* 147*/
+    .long   DefaultISR                                      /* 148*/
+    .long   DefaultISR                                      /* 149*/
+    .long   DefaultISR                                      /* 150*/
+    .long   DefaultISR                                      /* 151*/
+    .long   DefaultISR                                      /* 152*/
+    .long   DefaultISR                                      /* 153*/
+    .long   DefaultISR                                      /* 154*/
+    .long   DefaultISR                                      /* 155*/
+    .long   DefaultISR                                      /* 156*/
+    .long   DefaultISR                                      /* 157*/
+    .long   DefaultISR                                      /* 158*/
+    .long   DefaultISR                                      /* 159*/
+    .long   DefaultISR                                      /* 160*/
+    .long   DefaultISR                                      /* 161*/
+    .long   DefaultISR                                      /* 162*/
+    .long   DefaultISR                                      /* 163*/
+    .long   DefaultISR                                      /* 164*/
+    .long   DefaultISR                                      /* 165*/
+    .long   DefaultISR                                      /* 166*/
+    .long   DefaultISR                                      /* 167*/
+    .long   DefaultISR                                      /* 168*/
+    .long   DefaultISR                                      /* 169*/
+    .long   DefaultISR                                      /* 170*/
+    .long   DefaultISR                                      /* 171*/
+    .long   DefaultISR                                      /* 172*/
+    .long   DefaultISR                                      /* 173*/
+    .long   DefaultISR                                      /* 174*/
+    .long   DefaultISR                                      /* 175*/
+    .long   DefaultISR                                      /* 176*/
+    .long   DefaultISR                                      /* 177*/
+    .long   DefaultISR                                      /* 178*/
+    .long   DefaultISR                                      /* 179*/
+    .long   DefaultISR                                      /* 180*/
+    .long   DefaultISR                                      /* 181*/
+    .long   DefaultISR                                      /* 182*/
+    .long   DefaultISR                                      /* 183*/
+    .long   DefaultISR                                      /* 184*/
+    .long   DefaultISR                                      /* 185*/
+    .long   DefaultISR                                      /* 186*/
+    .long   DefaultISR                                      /* 187*/
+    .long   DefaultISR                                      /* 188*/
+    .long   DefaultISR                                      /* 189*/
+    .long   DefaultISR                                      /* 190*/
+    .long   DefaultISR                                      /* 191*/
+    .long   DefaultISR                                      /* 192*/
+    .long   DefaultISR                                      /* 193*/
+    .long   DefaultISR                                      /* 194*/
+    .long   DefaultISR                                      /* 195*/
+    .long   DefaultISR                                      /* 196*/
+    .long   DefaultISR                                      /* 197*/
+    .long   DefaultISR                                      /* 198*/
+    .long   DefaultISR                                      /* 199*/
+    .long   DefaultISR                                      /* 200*/
+    .long   DefaultISR                                      /* 201*/
+    .long   DefaultISR                                      /* 202*/
+    .long   DefaultISR                                      /* 203*/
+    .long   DefaultISR                                      /* 204*/
+    .long   DefaultISR                                      /* 205*/
+    .long   DefaultISR                                      /* 206*/
+    .long   DefaultISR                                      /* 207*/
+    .long   DefaultISR                                      /* 208*/
+    .long   DefaultISR                                      /* 209*/
+    .long   DefaultISR                                      /* 210*/
+    .long   DefaultISR                                      /* 211*/
+    .long   DefaultISR                                      /* 212*/
+    .long   DefaultISR                                      /* 213*/
+    .long   DefaultISR                                      /* 214*/
+    .long   DefaultISR                                      /* 215*/
+    .long   DefaultISR                                      /* 216*/
+    .long   DefaultISR                                      /* 217*/
+    .long   DefaultISR                                      /* 218*/
+    .long   DefaultISR                                      /* 219*/
+    .long   DefaultISR                                      /* 220*/
+    .long   DefaultISR                                      /* 221*/
+    .long   DefaultISR                                      /* 222*/
+    .long   DefaultISR                                      /* 223*/
+    .long   DefaultISR                                      /* 224*/
+    .long   DefaultISR                                      /* 225*/
+    .long   DefaultISR                                      /* 226*/
+    .long   DefaultISR                                      /* 227*/
+    .long   DefaultISR                                      /* 228*/
+    .long   DefaultISR                                      /* 229*/
+    .long   DefaultISR                                      /* 230*/
+    .long   DefaultISR                                      /* 231*/
+    .long   DefaultISR                                      /* 232*/
+    .long   DefaultISR                                      /* 233*/
+    .long   DefaultISR                                      /* 234*/
+    .long   DefaultISR                                      /* 235*/
+    .long   DefaultISR                                      /* 236*/
+    .long   DefaultISR                                      /* 237*/
+    .long   DefaultISR                                      /* 238*/
+    .long   DefaultISR                                      /* 239*/
+    .long   DefaultISR                                      /* 240*/
+    .long   DefaultISR                                      /* 241*/
+    .long   DefaultISR                                      /* 242*/
+    .long   DefaultISR                                      /* 243*/
+    .long   DefaultISR                                      /* 244*/
+    .long   DefaultISR                                      /* 245*/
+    .long   DefaultISR                                      /* 246*/
+    .long   DefaultISR                                      /* 247*/
+    .long   DefaultISR                                      /* 248*/
+    .long   DefaultISR                                      /* 249*/
+    .long   DefaultISR                                      /* 250*/
+    .long   DefaultISR                                      /* 251*/
+    .long   DefaultISR                                      /* 252*/
+    .long   DefaultISR                                      /* 253*/
+    .long   DefaultISR                                      /* 254*/
+    .long   0xFFFFFFFF                                      /*  Reserved for user TRIM value*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+#ifndef __NO_SYSTEM_INIT
+    bl SystemInit
+#endif
+    bl init_data_bss
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    bl    __START
+#else
+    bl    __libc_init_array
+    bl    main
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align	1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b	DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler	handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    NMI_Handler
+    def_irq_handler    HardFault_Handler
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SVC_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+    def_irq_handler    DMA0_IRQHandler
+    def_irq_handler    DMA1_IRQHandler
+    def_irq_handler    DMA2_IRQHandler
+    def_irq_handler    DMA3_IRQHandler
+    def_irq_handler    DMA4_IRQHandler
+    def_irq_handler    DMA5_IRQHandler
+    def_irq_handler    DMA6_IRQHandler
+    def_irq_handler    DMA7_IRQHandler
+    def_irq_handler    DMA8_IRQHandler
+    def_irq_handler    DMA9_IRQHandler
+    def_irq_handler    DMA10_IRQHandler
+    def_irq_handler    DMA11_IRQHandler
+    def_irq_handler    DMA12_IRQHandler
+    def_irq_handler    DMA13_IRQHandler
+    def_irq_handler    DMA14_IRQHandler
+    def_irq_handler    DMA15_IRQHandler
+    def_irq_handler    DMA_Error_IRQHandler
+    def_irq_handler    MCM_IRQHandler
+    def_irq_handler    FTFE_IRQHandler
+    def_irq_handler    Read_Collision_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    WDOG_EWM_IRQHandler
+    def_irq_handler    RNG_IRQHandler
+    def_irq_handler    I2C0_IRQHandler
+    def_irq_handler    I2C1_IRQHandler
+    def_irq_handler    SPI0_IRQHandler
+    def_irq_handler    SPI1_IRQHandler
+    def_irq_handler    I2S0_Tx_IRQHandler
+    def_irq_handler    I2S0_Rx_IRQHandler
+    def_irq_handler    UART0_LON_IRQHandler
+    def_irq_handler    UART0_RX_TX_IRQHandler
+    def_irq_handler    UART0_ERR_IRQHandler
+    def_irq_handler    UART1_RX_TX_IRQHandler
+    def_irq_handler    UART1_ERR_IRQHandler
+    def_irq_handler    UART2_RX_TX_IRQHandler
+    def_irq_handler    UART2_ERR_IRQHandler
+    def_irq_handler    UART3_RX_TX_IRQHandler
+    def_irq_handler    UART3_ERR_IRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    CMP1_IRQHandler
+    def_irq_handler    FTM0_IRQHandler
+    def_irq_handler    FTM1_IRQHandler
+    def_irq_handler    FTM2_IRQHandler
+    def_irq_handler    CMT_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT0_IRQHandler
+    def_irq_handler    PIT1_IRQHandler
+    def_irq_handler    PIT2_IRQHandler
+    def_irq_handler    PIT3_IRQHandler
+    def_irq_handler    PDB0_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    USBDCD_IRQHandler
+    def_irq_handler    Reserved71_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTB_IRQHandler
+    def_irq_handler    PORTC_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+    def_irq_handler    PORTE_IRQHandler
+    def_irq_handler    SWI_IRQHandler
+    def_irq_handler    SPI2_IRQHandler
+    def_irq_handler    UART4_RX_TX_IRQHandler
+    def_irq_handler    UART4_ERR_IRQHandler
+    def_irq_handler    UART5_RX_TX_IRQHandler
+    def_irq_handler    UART5_ERR_IRQHandler
+    def_irq_handler    CMP2_IRQHandler
+    def_irq_handler    FTM3_IRQHandler
+    def_irq_handler    DAC1_IRQHandler
+    def_irq_handler    ADC1_IRQHandler
+    def_irq_handler    I2C2_IRQHandler
+    def_irq_handler    CAN0_ORed_Message_buffer_IRQHandler
+    def_irq_handler    CAN0_Bus_Off_IRQHandler
+    def_irq_handler    CAN0_Error_IRQHandler
+    def_irq_handler    CAN0_Tx_Warning_IRQHandler
+    def_irq_handler    CAN0_Rx_Warning_IRQHandler
+    def_irq_handler    CAN0_Wake_Up_IRQHandler
+    def_irq_handler    SDHC_IRQHandler
+    def_irq_handler    ENET_1588_Timer_IRQHandler
+    def_irq_handler    ENET_Transmit_IRQHandler
+    def_irq_handler    ENET_Receive_IRQHandler
+    def_irq_handler    ENET_Error_IRQHandler
+
+    .end
diff --git a/Workspace/UART/Project_Settings/Startup_Code/system_MK64F12.c b/Workspace/UART/Project_Settings/Startup_Code/system_MK64F12.c
new file mode 100644
index 0000000..e3c1376
--- /dev/null
+++ b/Workspace/UART/Project_Settings/Startup_Code/system_MK64F12.c
@@ -0,0 +1,414 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief Device specific configuration file for MK64F12 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+#if (DISABLE_WDOG)
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+  /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+  WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+  /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+  WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+                 WDOG_STCTRLH_WAITEN_MASK |
+                 WDOG_STCTRLH_STOPEN_MASK |
+                 WDOG_STCTRLH_ALLOWUPDATE_MASK |
+                 WDOG_STCTRLH_CLKSRC_MASK |
+                 0x0100U;
+#endif /* (DISABLE_WDOG) */
+#ifdef CLOCK_SETUP
+  if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
+  {
+    if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
+    {
+       PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO:  Only has an effect if recovering from VLLSx.*/
+    }
+  } else {
+#ifdef SYSTEM_RTC_CR_VALUE
+    SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
+    if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
+      RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
+      RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
+      RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
+    }
+#endif
+  }
+
+  /* Power mode protection initialization */
+#ifdef SYSTEM_SMC_PMPROT_VALUE
+  SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
+#endif
+
+  /* System clock initialization */
+  /* Internal reference clock trim initialization */
+#if defined(SLOW_TRIM_ADDRESS)
+  if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) {                              /* Skip if non-volatile flash memory is erased */
+    MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
+  #endif /* defined(SLOW_TRIM_ADDRESS) */
+  #if defined(SLOW_FINE_TRIM_ADDRESS)
+    MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
+  #endif
+  #if defined(FAST_TRIM_ADDRESS)
+    MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
+  #endif
+  #if defined(FAST_FINE_TRIM_ADDRESS)
+    MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
+  #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
+#if defined(SLOW_TRIM_ADDRESS)
+  }
+  #endif /* defined(SLOW_TRIM_ADDRESS) */
+
+  /* Set system prescalers and clock sources */
+  SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
+  SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
+  SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+  /* Set MCG and OSC */
+#if  ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+  /* PORTA_PCR19: ISF=0,MUX=0 */
+  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
+  MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+  /* Check that the source of the FLL reference clock is the requested one. */
+  if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+    }
+  } else {
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+    }
+  }
+  MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+  MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+  OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
+  #if (MCG_MODE == MCG_MODE_BLPI)
+  /* BLPI specific */
+  MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
+  #endif
+
+#else /* MCG_MODE */
+  /* Set MCG and OSC */
+#if  (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
+  /* SIM_SCGC5: PORTA=1 */
+  SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+  /* PORTA_PCR19: ISF=0,MUX=0 */
+  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+  }
+#endif
+  MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
+  MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+  OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+  MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
+  #if (MCG_MODE == MCG_MODE_PEE)
+  MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
+  #else
+  MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+  #endif
+  if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
+    while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
+    }
+  }
+  /* Check that the source of the FLL reference clock is the requested one. */
+  if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+    }
+  } else {
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+    }
+  }
+  MCG->C4 = ((SYSTEM_MCG_C4_VALUE)  & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+#endif /* MCG_MODE */
+
+  /* Common for all MCG modes */
+
+  /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
+  MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
+  MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+  if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
+    MCG->C5 |= MCG_C5_PLLCLKEN0_MASK;  /* PLL clock enable in mode other than PEE or PBE */
+  }
+  /* BLPE, PEE and PBE MCG mode specific */
+
+#if (MCG_MODE == MCG_MODE_BLPE)
+  MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
+#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
+  MCG->C6 |= (MCG_C6_PLLS_MASK);       /* Set C6 (PLL select, VCO divider etc.) */
+  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
+  }
+  #if (MCG_MODE == MCG_MODE_PEE)
+  MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
+  #endif
+#endif
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
+  }
+  /* Use LPTMR to wait for 1ms dor FLL clock stabilization */
+  SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK;   /* Alow software control of LPMTR */
+  LPTMR0->CMR = LPTMR_CMR_COMPARE(0);  /* Default 1 LPO tick */
+  LPTMR0->CSR = (LPTMR_CSR_TCF_MASK | LPTMR_CSR_TPS(0x00));
+  LPTMR0->PSR = (LPTMR_PSR_PCS(0x01) | LPTMR_PSR_PBYP_MASK); /* Clock source: LPO, Prescaler bypass enable */
+  LPTMR0->CSR = LPTMR_CSR_TEN_MASK;    /* LPMTR enable */
+  while((LPTMR0_CSR & LPTMR_CSR_TCF_MASK) == 0u) {
+  }
+  LPTMR0_CSR = 0x00;                   /* Disable LPTMR */
+  SIM_SCGC5 &= (uint32_t)~(uint32_t)SIM_SCGC5_LPTMR_MASK;
+#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
+  }
+#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+  }
+#elif (MCG_MODE == MCG_MODE_PEE)
+  while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
+  }
+#endif
+#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
+  SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
+  while(SMC->PMSTAT != 0x04U) {        /* Wait until the system is in VLPR mode */
+  }
+#endif
+
+#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
+  SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
+#endif
+
+  /* PLL loss of lock interrupt request initialization */
+  if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
+    NVIC_EnableIRQ(MCG_IRQn);          /* Enable PLL loss of lock interrupt request */
+  }
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+  uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
+  uint16_t Divider;
+
+  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
+    /* Output of FLL or PLL is selected */
+    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
+      /* FLL is selected */
+      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
+        /* External reference clock is selected */
+        switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+        case 0x00U:
+          MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+          break;
+        case 0x01U:
+          MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+          break;
+        case 0x02U:
+        default:
+          MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+          break;
+        }
+        if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
+          switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
+          case 0x38U:
+            Divider = 1536U;
+            break;
+          case 0x30U:
+            Divider = 1280U;
+            break;
+          default:
+            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+            break;
+          }
+        } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+          Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+        }
+        MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+        MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+      /* Select correct multiplier to calculate the MCG output clock  */
+      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+        case 0x00U:
+          MCGOUTClock *= 640U;
+          break;
+        case 0x20U:
+          MCGOUTClock *= 1280U;
+          break;
+        case 0x40U:
+          MCGOUTClock *= 1920U;
+          break;
+        case 0x60U:
+          MCGOUTClock *= 2560U;
+          break;
+        case 0x80U:
+          MCGOUTClock *= 732U;
+          break;
+        case 0xA0U:
+          MCGOUTClock *= 1464U;
+          break;
+        case 0xC0U:
+          MCGOUTClock *= 2197U;
+          break;
+        case 0xE0U:
+          MCGOUTClock *= 2929U;
+          break;
+        default:
+          break;
+      }
+    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+      /* PLL is selected */
+      Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
+      MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+      Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
+      MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
+    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
+    /* Internal reference clock is selected */
+    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+      Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+      MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
+    /* External reference clock is selected */
+    switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+    case 0x00U:
+      MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
+      break;
+    case 0x01U:
+      MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+      break;
+    case 0x02U:
+    default:
+      MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+      break;
+    }
+  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+    /* Reserved value */
+    return;
+  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+  SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/Workspace/UART/Project_Settings/Startup_Code/system_MK64F12.h b/Workspace/UART/Project_Settings/Startup_Code/system_MK64F12.h
new file mode 100644
index 0000000..d6a5f05
--- /dev/null
+++ b/Workspace/UART/Project_Settings/Startup_Code/system_MK64F12.h
@@ -0,0 +1,352 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief Device specific configuration file for MK64F12 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK64F12_H_
+#define SYSTEM_MK64F12_H_                        /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG                 1
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI                   0U
+#define MCG_MODE_FBI                   1U
+#define MCG_MODE_BLPI                  2U
+#define MCG_MODE_FEE                   3U
+#define MCG_MODE_FBE                   4U
+#define MCG_MODE_BLPE                  5U
+#define MCG_MODE_PBE                   6U
+#define MCG_MODE_PEE                   7U
+
+/* Predefined clock setups
+   0 ... Default  part configuration
+         Multipurpose Clock Generator (MCG) in FEI mode.
+         Reference clock source for MCG module: Slow internal reference clock
+         Core clock = 20.97152MHz
+         Bus clock  = 20.97152MHz
+   1 ... Maximum achievable clock frequency configuration
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+   2 ... Chip internaly clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPI mode.
+         Reference clock source for MCG module: Fast internal reference clock
+         Core clock = 4MHz
+         Bus clock  = 4MHz
+   3 ... Chip externally clocked, ready for Very Low Power Run mode.
+         Multipurpose Clock Generator (MCG) in BLPE mode.
+         Reference clock source for MCG module: RTC oscillator reference clock
+         Core clock = 0.032768MHz
+         Bus clock  = 0.032768MHz
+   4 ... USB clock setup
+         Multipurpose Clock Generator (MCG) in PEE mode.
+         Reference clock source for MCG module: System oscillator 0 reference clock
+         Core clock = 120MHz
+         Bus clock  = 60MHz
+ */
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ                50000000u           /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_XTAL32k_CLK_HZ             32768u              /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+#define CPU_INT_SLOW_CLK_HZ            32768u              /* Value of the slow internal oscillator clock frequency in Hz  */
+#define CPU_INT_FAST_CLK_HZ            4000000u            /* Value of the fast internal oscillator clock frequency in Hz  */
+#define CPU_INT_IRC_CLK_HZ             48000000u           /* Value of the 48M internal oscillator clock frequency in Hz  */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE            0x0300U             /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE        0x2AU               /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */                             /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */                        /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */                             /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */                        /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#ifdef CLOCK_SETUP
+#if (CLOCK_SETUP == 0)
+  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_FEI /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x06U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00110000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00U               /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 1)
+  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 2)
+  #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_BLPI /* Clock generator mode */
+  /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x46U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00040000U         /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 3)
+  #define DEFAULT_SYSTEM_CLOCK         32768u              /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_BLPE /* Clock generator mode */
+  /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x82U               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
+  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x02U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=1 */
+  #define SYSTEM_MCG_C7_VALUE          0x01U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00U               /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 4)
+  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
+  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
+  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
+  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
+  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
+  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
+  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
+  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
+/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
+  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
+  #define SYSTEM_SIM_CLKDIV2_VALUE     0x09U               /* SIM_CLKDIV2 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
+  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
+/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
+#endif
+#else
+  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* #if !defined(SYSTEM_MK64F12_H_) */
diff --git a/Workspace/UART/SDK/platform/CMSIS/Include/arm_common_tables.h b/Workspace/UART/SDK/platform/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000..039cc3d
--- /dev/null
+++ b/Workspace/UART/SDK/platform/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/Workspace/UART/SDK/platform/CMSIS/Include/arm_const_structs.h b/Workspace/UART/SDK/platform/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 0000000..726d06e
--- /dev/null
+++ b/Workspace/UART/SDK/platform/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/Workspace/UART/SDK/platform/CMSIS/Include/arm_math.h b/Workspace/UART/SDK/platform/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000..e4b2f62
--- /dev/null
+++ b/Workspace/UART/SDK/platform/CMSIS/Include/arm_math.h
@@ -0,0 +1,7556 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_math.h
+*
+* Description:	Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   * 
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   * 
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+  #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31	   0x400000
+#define TABLE_SPACING_Q15	   0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+#elif defined __GNUC__
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__			/* Cosmic */
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+#elif defined __TASKING__
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+//#define __CLZ __clz
+//#endif
+
+//note: function can be removed when all toolchain support __CLZ for Cortex-M0
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+      ((q15_t) x * (q15_t) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		 *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15( 
+    const arm_cfft_instance_q15 * S, 
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31( 
+    const arm_cfft_instance_q31 * S, 
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+  
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in >= 0.0f)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+   
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("push")         \
+         _Pragma ("O1")
+    #else
+      #define LOW_OPTIMIZATION_ENTER 
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_EXIT \
+         _Pragma ("pop")
+    #else
+      #define LOW_OPTIMIZATION_EXIT  
+    #endif
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)		// Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)		// TASKING
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/Workspace/UART/SDK/platform/CMSIS/Include/core_cm4.h b/Workspace/UART/SDK/platform/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000..9749c27
--- /dev/null
+++ b/Workspace/UART/SDK/platform/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1858 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)IRQn < 0) {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)IRQn < 0) {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                             /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Workspace/UART/SDK/platform/CMSIS/Include/core_cmFunc.h b/Workspace/UART/SDK/platform/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000..b6ad0a4
--- /dev/null
+++ b/Workspace/UART/SDK/platform/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,664 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+    or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+	or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/Workspace/UART/SDK/platform/CMSIS/Include/core_cmInstr.h b/Workspace/UART/SDK/platform/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000..fca425c
--- /dev/null
+++ b/Workspace/UART/SDK/platform/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,916 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+  return(result);
+}
+#endif
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+#endif
+  return(result);
+}
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/Workspace/UART/SDK/platform/CMSIS/Include/core_cmSimd.h b/Workspace/UART/SDK/platform/CMSIS/Include/core_cmSimd.h
new file mode 100644
index 0000000..7b8e37f
--- /dev/null
+++ b/Workspace/UART/SDK/platform/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/Workspace/UART/SDK/platform/devices/MK64F12/include/MK64F12.h b/Workspace/UART/SDK/platform/devices/MK64F12/include/MK64F12.h
new file mode 100644
index 0000000..3114ad7
--- /dev/null
+++ b/Workspace/UART/SDK/platform/devices/MK64F12/include/MK64F12.h
@@ -0,0 +1,18767 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MK64F12
+**
+**     Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12.h
+ * @version 2.8
+ * @date 2015-02-19
+ * @brief CMSIS Peripheral Access Layer for MK64F12
+ *
+ * CMSIS Peripheral Access Layer for MK64F12
+ */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCU activation
+   ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MK64F12_H_)  /* Check if memory map has not been already included */
+#define MK64F12_H_
+#define MCU_MK64F12
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+  #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0008u
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ *        bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ *        0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return  Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 102                /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_IRQn                    = 0,                /**< DMA Channel 0 Transfer Complete */
+  DMA1_IRQn                    = 1,                /**< DMA Channel 1 Transfer Complete */
+  DMA2_IRQn                    = 2,                /**< DMA Channel 2 Transfer Complete */
+  DMA3_IRQn                    = 3,                /**< DMA Channel 3 Transfer Complete */
+  DMA4_IRQn                    = 4,                /**< DMA Channel 4 Transfer Complete */
+  DMA5_IRQn                    = 5,                /**< DMA Channel 5 Transfer Complete */
+  DMA6_IRQn                    = 6,                /**< DMA Channel 6 Transfer Complete */
+  DMA7_IRQn                    = 7,                /**< DMA Channel 7 Transfer Complete */
+  DMA8_IRQn                    = 8,                /**< DMA Channel 8 Transfer Complete */
+  DMA9_IRQn                    = 9,                /**< DMA Channel 9 Transfer Complete */
+  DMA10_IRQn                   = 10,               /**< DMA Channel 10 Transfer Complete */
+  DMA11_IRQn                   = 11,               /**< DMA Channel 11 Transfer Complete */
+  DMA12_IRQn                   = 12,               /**< DMA Channel 12 Transfer Complete */
+  DMA13_IRQn                   = 13,               /**< DMA Channel 13 Transfer Complete */
+  DMA14_IRQn                   = 14,               /**< DMA Channel 14 Transfer Complete */
+  DMA15_IRQn                   = 15,               /**< DMA Channel 15 Transfer Complete */
+  DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
+  MCM_IRQn                     = 17,               /**< Normal Interrupt */
+  FTFE_IRQn                    = 18,               /**< FTFE Command complete interrupt */
+  Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
+  LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
+  LLWU_IRQn                    = 21,               /**< Low Leakage Wakeup Unit */
+  WDOG_EWM_IRQn                = 22,               /**< WDOG Interrupt */
+  RNG_IRQn                     = 23,               /**< RNG Interrupt */
+  I2C0_IRQn                    = 24,               /**< I2C0 interrupt */
+  I2C1_IRQn                    = 25,               /**< I2C1 interrupt */
+  SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
+  SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
+  I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
+  I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
+  UART0_LON_IRQn               = 30,               /**< UART0 LON interrupt */
+  UART0_RX_TX_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
+  UART0_ERR_IRQn               = 32,               /**< UART0 Error interrupt */
+  UART1_RX_TX_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
+  UART1_ERR_IRQn               = 34,               /**< UART1 Error interrupt */
+  UART2_RX_TX_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
+  UART2_ERR_IRQn               = 36,               /**< UART2 Error interrupt */
+  UART3_RX_TX_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
+  UART3_ERR_IRQn               = 38,               /**< UART3 Error interrupt */
+  ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
+  CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
+  FTM0_IRQn                    = 42,               /**< FTM0 fault, overflow and channels interrupt */
+  FTM1_IRQn                    = 43,               /**< FTM1 fault, overflow and channels interrupt */
+  FTM2_IRQn                    = 44,               /**< FTM2 fault, overflow and channels interrupt */
+  CMT_IRQn                     = 45,               /**< CMT interrupt */
+  RTC_IRQn                     = 46,               /**< RTC interrupt */
+  RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
+  PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
+  PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
+  PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
+  PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
+  PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
+  USB0_IRQn                    = 53,               /**< USB0 interrupt */
+  USBDCD_IRQn                  = 54,               /**< USBDCD Interrupt */
+  Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
+  DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
+  MCG_IRQn                     = 57,               /**< MCG Interrupt */
+  LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
+  PORTA_IRQn                   = 59,               /**< Port A interrupt */
+  PORTB_IRQn                   = 60,               /**< Port B interrupt */
+  PORTC_IRQn                   = 61,               /**< Port C interrupt */
+  PORTD_IRQn                   = 62,               /**< Port D interrupt */
+  PORTE_IRQn                   = 63,               /**< Port E interrupt */
+  SWI_IRQn                     = 64,               /**< Software interrupt */
+  SPI2_IRQn                    = 65,               /**< SPI2 Interrupt */
+  UART4_RX_TX_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
+  UART4_ERR_IRQn               = 67,               /**< UART4 Error interrupt */
+  UART5_RX_TX_IRQn             = 68,               /**< UART5 Receive/Transmit interrupt */
+  UART5_ERR_IRQn               = 69,               /**< UART5 Error interrupt */
+  CMP2_IRQn                    = 70,               /**< CMP2 interrupt */
+  FTM3_IRQn                    = 71,               /**< FTM3 fault, overflow and channels interrupt */
+  DAC1_IRQn                    = 72,               /**< DAC1 interrupt */
+  ADC1_IRQn                    = 73,               /**< ADC1 interrupt */
+  I2C2_IRQn                    = 74,               /**< I2C2 interrupt */
+  CAN0_ORed_Message_buffer_IRQn = 75,              /**< CAN0 OR'd message buffers interrupt */
+  CAN0_Bus_Off_IRQn            = 76,               /**< CAN0 bus off interrupt */
+  CAN0_Error_IRQn              = 77,               /**< CAN0 error interrupt */
+  CAN0_Tx_Warning_IRQn         = 78,               /**< CAN0 Tx warning interrupt */
+  CAN0_Rx_Warning_IRQn         = 79,               /**< CAN0 Rx warning interrupt */
+  CAN0_Wake_Up_IRQn            = 80,               /**< CAN0 wake up interrupt */
+  SDHC_IRQn                    = 81,               /**< SDHC interrupt */
+  ENET_1588_Timer_IRQn         = 82,               /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+  ENET_Transmit_IRQn           = 83,               /**< Ethernet MAC Transmit Interrupt */
+  ENET_Receive_IRQn            = 84,               /**< Ethernet MAC Receive Interrupt */
+  ENET_Error_IRQn              = 85                /**< Ethernet MAC Error and miscelaneous Interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_MK64F12.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index)                  ((base)->SC1[index])
+#define ADC_SC1_COUNT                            2
+#define ADC_CFG1_REG(base)                       ((base)->CFG1)
+#define ADC_CFG2_REG(base)                       ((base)->CFG2)
+#define ADC_R_REG(base,index)                    ((base)->R[index])
+#define ADC_R_COUNT                              2
+#define ADC_CV1_REG(base)                        ((base)->CV1)
+#define ADC_CV2_REG(base)                        ((base)->CV2)
+#define ADC_SC2_REG(base)                        ((base)->SC2)
+#define ADC_SC3_REG(base)                        ((base)->SC3)
+#define ADC_OFS_REG(base)                        ((base)->OFS)
+#define ADC_PG_REG(base)                         ((base)->PG)
+#define ADC_MG_REG(base)                         ((base)->MG)
+#define ADC_CLPD_REG(base)                       ((base)->CLPD)
+#define ADC_CLPS_REG(base)                       ((base)->CLPS)
+#define ADC_CLP4_REG(base)                       ((base)->CLP4)
+#define ADC_CLP3_REG(base)                       ((base)->CLP3)
+#define ADC_CLP2_REG(base)                       ((base)->CLP2)
+#define ADC_CLP1_REG(base)                       ((base)->CLP1)
+#define ADC_CLP0_REG(base)                       ((base)->CLP0)
+#define ADC_CLMD_REG(base)                       ((base)->CLMD)
+#define ADC_CLMS_REG(base)                       ((base)->CLMS)
+#define ADC_CLM4_REG(base)                       ((base)->CLM4)
+#define ADC_CLM3_REG(base)                       ((base)->CLM3)
+#define ADC_CLM2_REG(base)                       ((base)->CLM2)
+#define ADC_CLM1_REG(base)                       ((base)->CLM1)
+#define ADC_CLM0_REG(base)                       ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK                        0x1Fu
+#define ADC_SC1_ADCH_SHIFT                       0
+#define ADC_SC1_ADCH_WIDTH                       5
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        0x20u
+#define ADC_SC1_DIFF_SHIFT                       5
+#define ADC_SC1_DIFF_WIDTH                       1
+#define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK                        0x40u
+#define ADC_SC1_AIEN_SHIFT                       6
+#define ADC_SC1_AIEN_WIDTH                       1
+#define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK                        0x80u
+#define ADC_SC1_COCO_SHIFT                       7
+#define ADC_SC1_COCO_WIDTH                       1
+#define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK                     0x3u
+#define ADC_CFG1_ADICLK_SHIFT                    0
+#define ADC_CFG1_ADICLK_WIDTH                    2
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       0xCu
+#define ADC_CFG1_MODE_SHIFT                      2
+#define ADC_CFG1_MODE_WIDTH                      2
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     0x10u
+#define ADC_CFG1_ADLSMP_SHIFT                    4
+#define ADC_CFG1_ADLSMP_WIDTH                    1
+#define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK                       0x60u
+#define ADC_CFG1_ADIV_SHIFT                      5
+#define ADC_CFG1_ADIV_WIDTH                      2
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      0x80u
+#define ADC_CFG1_ADLPC_SHIFT                     7
+#define ADC_CFG1_ADLPC_WIDTH                     1
+#define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK                     0x3u
+#define ADC_CFG2_ADLSTS_SHIFT                    0
+#define ADC_CFG2_ADLSTS_WIDTH                    2
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      0x4u
+#define ADC_CFG2_ADHSC_SHIFT                     2
+#define ADC_CFG2_ADHSC_WIDTH                     1
+#define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK                    0x8u
+#define ADC_CFG2_ADACKEN_SHIFT                   3
+#define ADC_CFG2_ADACKEN_WIDTH                   1
+#define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK                     0x10u
+#define ADC_CFG2_MUXSEL_SHIFT                    4
+#define ADC_CFG2_MUXSEL_WIDTH                    1
+#define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
+/* R Bit Fields */
+#define ADC_R_D_MASK                             0xFFFFu
+#define ADC_R_D_SHIFT                            0
+#define ADC_R_D_WIDTH                            16
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK                          0xFFFFu
+#define ADC_CV1_CV_SHIFT                         0
+#define ADC_CV1_CV_WIDTH                         16
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK                          0xFFFFu
+#define ADC_CV2_CV_SHIFT                         0
+#define ADC_CV2_CV_WIDTH                         16
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK                      0x3u
+#define ADC_SC2_REFSEL_SHIFT                     0
+#define ADC_SC2_REFSEL_WIDTH                     2
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       0x4u
+#define ADC_SC2_DMAEN_SHIFT                      2
+#define ADC_SC2_DMAEN_WIDTH                      1
+#define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK                       0x8u
+#define ADC_SC2_ACREN_SHIFT                      3
+#define ADC_SC2_ACREN_WIDTH                      1
+#define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK                       0x10u
+#define ADC_SC2_ACFGT_SHIFT                      4
+#define ADC_SC2_ACFGT_WIDTH                      1
+#define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK                        0x20u
+#define ADC_SC2_ACFE_SHIFT                       5
+#define ADC_SC2_ACFE_WIDTH                       1
+#define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK                       0x40u
+#define ADC_SC2_ADTRG_SHIFT                      6
+#define ADC_SC2_ADTRG_WIDTH                      1
+#define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK                       0x80u
+#define ADC_SC2_ADACT_SHIFT                      7
+#define ADC_SC2_ADACT_WIDTH                      1
+#define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK                        0x3u
+#define ADC_SC3_AVGS_SHIFT                       0
+#define ADC_SC3_AVGS_WIDTH                       2
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        0x4u
+#define ADC_SC3_AVGE_SHIFT                       2
+#define ADC_SC3_AVGE_WIDTH                       1
+#define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK                        0x8u
+#define ADC_SC3_ADCO_SHIFT                       3
+#define ADC_SC3_ADCO_WIDTH                       1
+#define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK                        0x40u
+#define ADC_SC3_CALF_SHIFT                       6
+#define ADC_SC3_CALF_WIDTH                       1
+#define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK                         0x80u
+#define ADC_SC3_CAL_SHIFT                        7
+#define ADC_SC3_CAL_WIDTH                        1
+#define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK                         0xFFFFu
+#define ADC_OFS_OFS_SHIFT                        0
+#define ADC_OFS_OFS_WIDTH                        16
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK                           0xFFFFu
+#define ADC_PG_PG_SHIFT                          0
+#define ADC_PG_PG_WIDTH                          16
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK                           0xFFFFu
+#define ADC_MG_MG_SHIFT                          0
+#define ADC_MG_MG_WIDTH                          16
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK                       0x3Fu
+#define ADC_CLPD_CLPD_SHIFT                      0
+#define ADC_CLPD_CLPD_WIDTH                      6
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK                       0x3Fu
+#define ADC_CLPS_CLPS_SHIFT                      0
+#define ADC_CLPS_CLPS_WIDTH                      6
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK                       0x3FFu
+#define ADC_CLP4_CLP4_SHIFT                      0
+#define ADC_CLP4_CLP4_WIDTH                      10
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK                       0x1FFu
+#define ADC_CLP3_CLP3_SHIFT                      0
+#define ADC_CLP3_CLP3_WIDTH                      9
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK                       0xFFu
+#define ADC_CLP2_CLP2_SHIFT                      0
+#define ADC_CLP2_CLP2_WIDTH                      8
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK                       0x7Fu
+#define ADC_CLP1_CLP1_SHIFT                      0
+#define ADC_CLP1_CLP1_WIDTH                      7
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK                       0x3Fu
+#define ADC_CLP0_CLP0_SHIFT                      0
+#define ADC_CLP0_CLP0_WIDTH                      6
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK                       0x3Fu
+#define ADC_CLMD_CLMD_SHIFT                      0
+#define ADC_CLMD_CLMD_WIDTH                      6
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK                       0x3Fu
+#define ADC_CLMS_CLMS_SHIFT                      0
+#define ADC_CLMS_CLMS_WIDTH                      6
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK                       0x3FFu
+#define ADC_CLM4_CLM4_SHIFT                      0
+#define ADC_CLM4_CLM4_WIDTH                      10
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK                       0x1FFu
+#define ADC_CLM3_CLM3_SHIFT                      0
+#define ADC_CLM3_CLM3_WIDTH                      9
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK                       0xFFu
+#define ADC_CLM2_CLM2_SHIFT                      0
+#define ADC_CLM2_CLM2_WIDTH                      8
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK                       0x7Fu
+#define ADC_CLM1_CLM1_SHIFT                      0
+#define ADC_CLM1_CLM1_WIDTH                      7
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK                       0x3Fu
+#define ADC_CLM0_CLM0_SHIFT                      0
+#define ADC_CLM0_CLM0_WIDTH                      6
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR                            (ADC0)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_Type *)ADC1_BASE)
+#define ADC1_BASE_PTR                            (ADC1)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ADC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A                                ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B                                ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1                                ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2                                ADC_CFG2_REG(ADC0)
+#define ADC0_RA                                  ADC_R_REG(ADC0,0)
+#define ADC0_RB                                  ADC_R_REG(ADC0,1)
+#define ADC0_CV1                                 ADC_CV1_REG(ADC0)
+#define ADC0_CV2                                 ADC_CV2_REG(ADC0)
+#define ADC0_SC2                                 ADC_SC2_REG(ADC0)
+#define ADC0_SC3                                 ADC_SC3_REG(ADC0)
+#define ADC0_OFS                                 ADC_OFS_REG(ADC0)
+#define ADC0_PG                                  ADC_PG_REG(ADC0)
+#define ADC0_MG                                  ADC_MG_REG(ADC0)
+#define ADC0_CLPD                                ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS                                ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4                                ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3                                ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2                                ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1                                ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0                                ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD                                ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS                                ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4                                ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3                                ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2                                ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1                                ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0                                ADC_CLM0_REG(ADC0)
+/* ADC1 */
+#define ADC1_SC1A                                ADC_SC1_REG(ADC1,0)
+#define ADC1_SC1B                                ADC_SC1_REG(ADC1,1)
+#define ADC1_CFG1                                ADC_CFG1_REG(ADC1)
+#define ADC1_CFG2                                ADC_CFG2_REG(ADC1)
+#define ADC1_RA                                  ADC_R_REG(ADC1,0)
+#define ADC1_RB                                  ADC_R_REG(ADC1,1)
+#define ADC1_CV1                                 ADC_CV1_REG(ADC1)
+#define ADC1_CV2                                 ADC_CV2_REG(ADC1)
+#define ADC1_SC2                                 ADC_SC2_REG(ADC1)
+#define ADC1_SC3                                 ADC_SC3_REG(ADC1)
+#define ADC1_OFS                                 ADC_OFS_REG(ADC1)
+#define ADC1_PG                                  ADC_PG_REG(ADC1)
+#define ADC1_MG                                  ADC_MG_REG(ADC1)
+#define ADC1_CLPD                                ADC_CLPD_REG(ADC1)
+#define ADC1_CLPS                                ADC_CLPS_REG(ADC1)
+#define ADC1_CLP4                                ADC_CLP4_REG(ADC1)
+#define ADC1_CLP3                                ADC_CLP3_REG(ADC1)
+#define ADC1_CLP2                                ADC_CLP2_REG(ADC1)
+#define ADC1_CLP1                                ADC_CLP1_REG(ADC1)
+#define ADC1_CLP0                                ADC_CLP0_REG(ADC1)
+#define ADC1_CLMD                                ADC_CLMD_REG(ADC1)
+#define ADC1_CLMS                                ADC_CLMS_REG(ADC1)
+#define ADC1_CLM4                                ADC_CLM4_REG(ADC1)
+#define ADC1_CLM3                                ADC_CLM3_REG(ADC1)
+#define ADC1_CLM2                                ADC_CLM2_REG(ADC1)
+#define ADC1_CLM1                                ADC_CLM1_REG(ADC1)
+#define ADC1_CLM0                                ADC_CLM0_REG(ADC1)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index)                          ADC_SC1_REG(ADC0,index)
+#define ADC1_SC1(index)                          ADC_SC1_REG(ADC1,index)
+#define ADC0_R(index)                            ADC_R_REG(ADC0,index)
+#define ADC1_R(index)                            ADC_R_REG(ADC1,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPRA;                              /**< Master Privilege Register A, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PACRA;                             /**< Peripheral Access Control Register, offset: 0x20 */
+  __IO uint32_t PACRB;                             /**< Peripheral Access Control Register, offset: 0x24 */
+  __IO uint32_t PACRC;                             /**< Peripheral Access Control Register, offset: 0x28 */
+  __IO uint32_t PACRD;                             /**< Peripheral Access Control Register, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PACRE;                             /**< Peripheral Access Control Register, offset: 0x40 */
+  __IO uint32_t PACRF;                             /**< Peripheral Access Control Register, offset: 0x44 */
+  __IO uint32_t PACRG;                             /**< Peripheral Access Control Register, offset: 0x48 */
+  __IO uint32_t PACRH;                             /**< Peripheral Access Control Register, offset: 0x4C */
+  __IO uint32_t PACRI;                             /**< Peripheral Access Control Register, offset: 0x50 */
+  __IO uint32_t PACRJ;                             /**< Peripheral Access Control Register, offset: 0x54 */
+  __IO uint32_t PACRK;                             /**< Peripheral Access Control Register, offset: 0x58 */
+  __IO uint32_t PACRL;                             /**< Peripheral Access Control Register, offset: 0x5C */
+  __IO uint32_t PACRM;                             /**< Peripheral Access Control Register, offset: 0x60 */
+  __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
+  __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
+  __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t PACRU;                             /**< Peripheral Access Control Register, offset: 0x80 */
+} AIPS_Type, *AIPS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register accessors */
+#define AIPS_MPRA_REG(base)                      ((base)->MPRA)
+#define AIPS_PACRA_REG(base)                     ((base)->PACRA)
+#define AIPS_PACRB_REG(base)                     ((base)->PACRB)
+#define AIPS_PACRC_REG(base)                     ((base)->PACRC)
+#define AIPS_PACRD_REG(base)                     ((base)->PACRD)
+#define AIPS_PACRE_REG(base)                     ((base)->PACRE)
+#define AIPS_PACRF_REG(base)                     ((base)->PACRF)
+#define AIPS_PACRG_REG(base)                     ((base)->PACRG)
+#define AIPS_PACRH_REG(base)                     ((base)->PACRH)
+#define AIPS_PACRI_REG(base)                     ((base)->PACRI)
+#define AIPS_PACRJ_REG(base)                     ((base)->PACRJ)
+#define AIPS_PACRK_REG(base)                     ((base)->PACRK)
+#define AIPS_PACRL_REG(base)                     ((base)->PACRL)
+#define AIPS_PACRM_REG(base)                     ((base)->PACRM)
+#define AIPS_PACRN_REG(base)                     ((base)->PACRN)
+#define AIPS_PACRO_REG(base)                     ((base)->PACRO)
+#define AIPS_PACRP_REG(base)                     ((base)->PACRP)
+#define AIPS_PACRU_REG(base)                     ((base)->PACRU)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/* MPRA Bit Fields */
+#define AIPS_MPRA_MPL5_MASK                      0x100u
+#define AIPS_MPRA_MPL5_SHIFT                     8
+#define AIPS_MPRA_MPL5_WIDTH                     1
+#define AIPS_MPRA_MPL5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL5_SHIFT))&AIPS_MPRA_MPL5_MASK)
+#define AIPS_MPRA_MTW5_MASK                      0x200u
+#define AIPS_MPRA_MTW5_SHIFT                     9
+#define AIPS_MPRA_MTW5_WIDTH                     1
+#define AIPS_MPRA_MTW5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW5_SHIFT))&AIPS_MPRA_MTW5_MASK)
+#define AIPS_MPRA_MTR5_MASK                      0x400u
+#define AIPS_MPRA_MTR5_SHIFT                     10
+#define AIPS_MPRA_MTR5_WIDTH                     1
+#define AIPS_MPRA_MTR5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR5_SHIFT))&AIPS_MPRA_MTR5_MASK)
+#define AIPS_MPRA_MPL4_MASK                      0x1000u
+#define AIPS_MPRA_MPL4_SHIFT                     12
+#define AIPS_MPRA_MPL4_WIDTH                     1
+#define AIPS_MPRA_MPL4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL4_SHIFT))&AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MTW4_MASK                      0x2000u
+#define AIPS_MPRA_MTW4_SHIFT                     13
+#define AIPS_MPRA_MTW4_WIDTH                     1
+#define AIPS_MPRA_MTW4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW4_SHIFT))&AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTR4_MASK                      0x4000u
+#define AIPS_MPRA_MTR4_SHIFT                     14
+#define AIPS_MPRA_MTR4_WIDTH                     1
+#define AIPS_MPRA_MTR4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR4_SHIFT))&AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MPL3_MASK                      0x10000u
+#define AIPS_MPRA_MPL3_SHIFT                     16
+#define AIPS_MPRA_MPL3_WIDTH                     1
+#define AIPS_MPRA_MPL3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL3_SHIFT))&AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MTW3_MASK                      0x20000u
+#define AIPS_MPRA_MTW3_SHIFT                     17
+#define AIPS_MPRA_MTW3_WIDTH                     1
+#define AIPS_MPRA_MTW3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW3_SHIFT))&AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTR3_MASK                      0x40000u
+#define AIPS_MPRA_MTR3_SHIFT                     18
+#define AIPS_MPRA_MTR3_WIDTH                     1
+#define AIPS_MPRA_MTR3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR3_SHIFT))&AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MPL2_MASK                      0x100000u
+#define AIPS_MPRA_MPL2_SHIFT                     20
+#define AIPS_MPRA_MPL2_WIDTH                     1
+#define AIPS_MPRA_MPL2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL2_SHIFT))&AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MTW2_MASK                      0x200000u
+#define AIPS_MPRA_MTW2_SHIFT                     21
+#define AIPS_MPRA_MTW2_WIDTH                     1
+#define AIPS_MPRA_MTW2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW2_SHIFT))&AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTR2_MASK                      0x400000u
+#define AIPS_MPRA_MTR2_SHIFT                     22
+#define AIPS_MPRA_MTR2_WIDTH                     1
+#define AIPS_MPRA_MTR2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR2_SHIFT))&AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MPL1_MASK                      0x1000000u
+#define AIPS_MPRA_MPL1_SHIFT                     24
+#define AIPS_MPRA_MPL1_WIDTH                     1
+#define AIPS_MPRA_MPL1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL1_SHIFT))&AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MTW1_MASK                      0x2000000u
+#define AIPS_MPRA_MTW1_SHIFT                     25
+#define AIPS_MPRA_MTW1_WIDTH                     1
+#define AIPS_MPRA_MTW1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW1_SHIFT))&AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTR1_MASK                      0x4000000u
+#define AIPS_MPRA_MTR1_SHIFT                     26
+#define AIPS_MPRA_MTR1_WIDTH                     1
+#define AIPS_MPRA_MTR1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR1_SHIFT))&AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MPL0_MASK                      0x10000000u
+#define AIPS_MPRA_MPL0_SHIFT                     28
+#define AIPS_MPRA_MPL0_WIDTH                     1
+#define AIPS_MPRA_MPL0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL0_SHIFT))&AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MTW0_MASK                      0x20000000u
+#define AIPS_MPRA_MTW0_SHIFT                     29
+#define AIPS_MPRA_MTW0_WIDTH                     1
+#define AIPS_MPRA_MTW0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW0_SHIFT))&AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTR0_MASK                      0x40000000u
+#define AIPS_MPRA_MTR0_SHIFT                     30
+#define AIPS_MPRA_MTR0_WIDTH                     1
+#define AIPS_MPRA_MTR0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR0_SHIFT))&AIPS_MPRA_MTR0_MASK)
+/* PACRA Bit Fields */
+#define AIPS_PACRA_TP7_MASK                      0x1u
+#define AIPS_PACRA_TP7_SHIFT                     0
+#define AIPS_PACRA_TP7_WIDTH                     1
+#define AIPS_PACRA_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP7_SHIFT))&AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_WP7_MASK                      0x2u
+#define AIPS_PACRA_WP7_SHIFT                     1
+#define AIPS_PACRA_WP7_WIDTH                     1
+#define AIPS_PACRA_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP7_SHIFT))&AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_SP7_MASK                      0x4u
+#define AIPS_PACRA_SP7_SHIFT                     2
+#define AIPS_PACRA_SP7_WIDTH                     1
+#define AIPS_PACRA_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP7_SHIFT))&AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_TP6_MASK                      0x10u
+#define AIPS_PACRA_TP6_SHIFT                     4
+#define AIPS_PACRA_TP6_WIDTH                     1
+#define AIPS_PACRA_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP6_SHIFT))&AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_WP6_MASK                      0x20u
+#define AIPS_PACRA_WP6_SHIFT                     5
+#define AIPS_PACRA_WP6_WIDTH                     1
+#define AIPS_PACRA_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP6_SHIFT))&AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_SP6_MASK                      0x40u
+#define AIPS_PACRA_SP6_SHIFT                     6
+#define AIPS_PACRA_SP6_WIDTH                     1
+#define AIPS_PACRA_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP6_SHIFT))&AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_TP5_MASK                      0x100u
+#define AIPS_PACRA_TP5_SHIFT                     8
+#define AIPS_PACRA_TP5_WIDTH                     1
+#define AIPS_PACRA_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP5_SHIFT))&AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_WP5_MASK                      0x200u
+#define AIPS_PACRA_WP5_SHIFT                     9
+#define AIPS_PACRA_WP5_WIDTH                     1
+#define AIPS_PACRA_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP5_SHIFT))&AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_SP5_MASK                      0x400u
+#define AIPS_PACRA_SP5_SHIFT                     10
+#define AIPS_PACRA_SP5_WIDTH                     1
+#define AIPS_PACRA_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP5_SHIFT))&AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_TP4_MASK                      0x1000u
+#define AIPS_PACRA_TP4_SHIFT                     12
+#define AIPS_PACRA_TP4_WIDTH                     1
+#define AIPS_PACRA_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP4_SHIFT))&AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_WP4_MASK                      0x2000u
+#define AIPS_PACRA_WP4_SHIFT                     13
+#define AIPS_PACRA_WP4_WIDTH                     1
+#define AIPS_PACRA_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP4_SHIFT))&AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_SP4_MASK                      0x4000u
+#define AIPS_PACRA_SP4_SHIFT                     14
+#define AIPS_PACRA_SP4_WIDTH                     1
+#define AIPS_PACRA_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP4_SHIFT))&AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_TP3_MASK                      0x10000u
+#define AIPS_PACRA_TP3_SHIFT                     16
+#define AIPS_PACRA_TP3_WIDTH                     1
+#define AIPS_PACRA_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP3_SHIFT))&AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_WP3_MASK                      0x20000u
+#define AIPS_PACRA_WP3_SHIFT                     17
+#define AIPS_PACRA_WP3_WIDTH                     1
+#define AIPS_PACRA_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP3_SHIFT))&AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_SP3_MASK                      0x40000u
+#define AIPS_PACRA_SP3_SHIFT                     18
+#define AIPS_PACRA_SP3_WIDTH                     1
+#define AIPS_PACRA_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP3_SHIFT))&AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_TP2_MASK                      0x100000u
+#define AIPS_PACRA_TP2_SHIFT                     20
+#define AIPS_PACRA_TP2_WIDTH                     1
+#define AIPS_PACRA_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP2_SHIFT))&AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_WP2_MASK                      0x200000u
+#define AIPS_PACRA_WP2_SHIFT                     21
+#define AIPS_PACRA_WP2_WIDTH                     1
+#define AIPS_PACRA_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP2_SHIFT))&AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_SP2_MASK                      0x400000u
+#define AIPS_PACRA_SP2_SHIFT                     22
+#define AIPS_PACRA_SP2_WIDTH                     1
+#define AIPS_PACRA_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP2_SHIFT))&AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_TP1_MASK                      0x1000000u
+#define AIPS_PACRA_TP1_SHIFT                     24
+#define AIPS_PACRA_TP1_WIDTH                     1
+#define AIPS_PACRA_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP1_SHIFT))&AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_WP1_MASK                      0x2000000u
+#define AIPS_PACRA_WP1_SHIFT                     25
+#define AIPS_PACRA_WP1_WIDTH                     1
+#define AIPS_PACRA_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP1_SHIFT))&AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_SP1_MASK                      0x4000000u
+#define AIPS_PACRA_SP1_SHIFT                     26
+#define AIPS_PACRA_SP1_WIDTH                     1
+#define AIPS_PACRA_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP1_SHIFT))&AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_TP0_MASK                      0x10000000u
+#define AIPS_PACRA_TP0_SHIFT                     28
+#define AIPS_PACRA_TP0_WIDTH                     1
+#define AIPS_PACRA_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP0_SHIFT))&AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_WP0_MASK                      0x20000000u
+#define AIPS_PACRA_WP0_SHIFT                     29
+#define AIPS_PACRA_WP0_WIDTH                     1
+#define AIPS_PACRA_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP0_SHIFT))&AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_SP0_MASK                      0x40000000u
+#define AIPS_PACRA_SP0_SHIFT                     30
+#define AIPS_PACRA_SP0_WIDTH                     1
+#define AIPS_PACRA_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP0_SHIFT))&AIPS_PACRA_SP0_MASK)
+/* PACRB Bit Fields */
+#define AIPS_PACRB_TP7_MASK                      0x1u
+#define AIPS_PACRB_TP7_SHIFT                     0
+#define AIPS_PACRB_TP7_WIDTH                     1
+#define AIPS_PACRB_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP7_SHIFT))&AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_WP7_MASK                      0x2u
+#define AIPS_PACRB_WP7_SHIFT                     1
+#define AIPS_PACRB_WP7_WIDTH                     1
+#define AIPS_PACRB_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP7_SHIFT))&AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_SP7_MASK                      0x4u
+#define AIPS_PACRB_SP7_SHIFT                     2
+#define AIPS_PACRB_SP7_WIDTH                     1
+#define AIPS_PACRB_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP7_SHIFT))&AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_TP6_MASK                      0x10u
+#define AIPS_PACRB_TP6_SHIFT                     4
+#define AIPS_PACRB_TP6_WIDTH                     1
+#define AIPS_PACRB_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP6_SHIFT))&AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_WP6_MASK                      0x20u
+#define AIPS_PACRB_WP6_SHIFT                     5
+#define AIPS_PACRB_WP6_WIDTH                     1
+#define AIPS_PACRB_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP6_SHIFT))&AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_SP6_MASK                      0x40u
+#define AIPS_PACRB_SP6_SHIFT                     6
+#define AIPS_PACRB_SP6_WIDTH                     1
+#define AIPS_PACRB_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP6_SHIFT))&AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_TP5_MASK                      0x100u
+#define AIPS_PACRB_TP5_SHIFT                     8
+#define AIPS_PACRB_TP5_WIDTH                     1
+#define AIPS_PACRB_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP5_SHIFT))&AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_WP5_MASK                      0x200u
+#define AIPS_PACRB_WP5_SHIFT                     9
+#define AIPS_PACRB_WP5_WIDTH                     1
+#define AIPS_PACRB_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP5_SHIFT))&AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_SP5_MASK                      0x400u
+#define AIPS_PACRB_SP5_SHIFT                     10
+#define AIPS_PACRB_SP5_WIDTH                     1
+#define AIPS_PACRB_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP5_SHIFT))&AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_TP4_MASK                      0x1000u
+#define AIPS_PACRB_TP4_SHIFT                     12
+#define AIPS_PACRB_TP4_WIDTH                     1
+#define AIPS_PACRB_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP4_SHIFT))&AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_WP4_MASK                      0x2000u
+#define AIPS_PACRB_WP4_SHIFT                     13
+#define AIPS_PACRB_WP4_WIDTH                     1
+#define AIPS_PACRB_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP4_SHIFT))&AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_SP4_MASK                      0x4000u
+#define AIPS_PACRB_SP4_SHIFT                     14
+#define AIPS_PACRB_SP4_WIDTH                     1
+#define AIPS_PACRB_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP4_SHIFT))&AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_TP3_MASK                      0x10000u
+#define AIPS_PACRB_TP3_SHIFT                     16
+#define AIPS_PACRB_TP3_WIDTH                     1
+#define AIPS_PACRB_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP3_SHIFT))&AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_WP3_MASK                      0x20000u
+#define AIPS_PACRB_WP3_SHIFT                     17
+#define AIPS_PACRB_WP3_WIDTH                     1
+#define AIPS_PACRB_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP3_SHIFT))&AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_SP3_MASK                      0x40000u
+#define AIPS_PACRB_SP3_SHIFT                     18
+#define AIPS_PACRB_SP3_WIDTH                     1
+#define AIPS_PACRB_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP3_SHIFT))&AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_TP2_MASK                      0x100000u
+#define AIPS_PACRB_TP2_SHIFT                     20
+#define AIPS_PACRB_TP2_WIDTH                     1
+#define AIPS_PACRB_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP2_SHIFT))&AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_WP2_MASK                      0x200000u
+#define AIPS_PACRB_WP2_SHIFT                     21
+#define AIPS_PACRB_WP2_WIDTH                     1
+#define AIPS_PACRB_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP2_SHIFT))&AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_SP2_MASK                      0x400000u
+#define AIPS_PACRB_SP2_SHIFT                     22
+#define AIPS_PACRB_SP2_WIDTH                     1
+#define AIPS_PACRB_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP2_SHIFT))&AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_TP1_MASK                      0x1000000u
+#define AIPS_PACRB_TP1_SHIFT                     24
+#define AIPS_PACRB_TP1_WIDTH                     1
+#define AIPS_PACRB_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP1_SHIFT))&AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_WP1_MASK                      0x2000000u
+#define AIPS_PACRB_WP1_SHIFT                     25
+#define AIPS_PACRB_WP1_WIDTH                     1
+#define AIPS_PACRB_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP1_SHIFT))&AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_SP1_MASK                      0x4000000u
+#define AIPS_PACRB_SP1_SHIFT                     26
+#define AIPS_PACRB_SP1_WIDTH                     1
+#define AIPS_PACRB_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP1_SHIFT))&AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_TP0_MASK                      0x10000000u
+#define AIPS_PACRB_TP0_SHIFT                     28
+#define AIPS_PACRB_TP0_WIDTH                     1
+#define AIPS_PACRB_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP0_SHIFT))&AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_WP0_MASK                      0x20000000u
+#define AIPS_PACRB_WP0_SHIFT                     29
+#define AIPS_PACRB_WP0_WIDTH                     1
+#define AIPS_PACRB_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP0_SHIFT))&AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_SP0_MASK                      0x40000000u
+#define AIPS_PACRB_SP0_SHIFT                     30
+#define AIPS_PACRB_SP0_WIDTH                     1
+#define AIPS_PACRB_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP0_SHIFT))&AIPS_PACRB_SP0_MASK)
+/* PACRC Bit Fields */
+#define AIPS_PACRC_TP7_MASK                      0x1u
+#define AIPS_PACRC_TP7_SHIFT                     0
+#define AIPS_PACRC_TP7_WIDTH                     1
+#define AIPS_PACRC_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP7_SHIFT))&AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_WP7_MASK                      0x2u
+#define AIPS_PACRC_WP7_SHIFT                     1
+#define AIPS_PACRC_WP7_WIDTH                     1
+#define AIPS_PACRC_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP7_SHIFT))&AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_SP7_MASK                      0x4u
+#define AIPS_PACRC_SP7_SHIFT                     2
+#define AIPS_PACRC_SP7_WIDTH                     1
+#define AIPS_PACRC_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP7_SHIFT))&AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_TP6_MASK                      0x10u
+#define AIPS_PACRC_TP6_SHIFT                     4
+#define AIPS_PACRC_TP6_WIDTH                     1
+#define AIPS_PACRC_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP6_SHIFT))&AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_WP6_MASK                      0x20u
+#define AIPS_PACRC_WP6_SHIFT                     5
+#define AIPS_PACRC_WP6_WIDTH                     1
+#define AIPS_PACRC_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP6_SHIFT))&AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_SP6_MASK                      0x40u
+#define AIPS_PACRC_SP6_SHIFT                     6
+#define AIPS_PACRC_SP6_WIDTH                     1
+#define AIPS_PACRC_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP6_SHIFT))&AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_TP5_MASK                      0x100u
+#define AIPS_PACRC_TP5_SHIFT                     8
+#define AIPS_PACRC_TP5_WIDTH                     1
+#define AIPS_PACRC_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP5_SHIFT))&AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_WP5_MASK                      0x200u
+#define AIPS_PACRC_WP5_SHIFT                     9
+#define AIPS_PACRC_WP5_WIDTH                     1
+#define AIPS_PACRC_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP5_SHIFT))&AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_SP5_MASK                      0x400u
+#define AIPS_PACRC_SP5_SHIFT                     10
+#define AIPS_PACRC_SP5_WIDTH                     1
+#define AIPS_PACRC_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP5_SHIFT))&AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_TP4_MASK                      0x1000u
+#define AIPS_PACRC_TP4_SHIFT                     12
+#define AIPS_PACRC_TP4_WIDTH                     1
+#define AIPS_PACRC_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP4_SHIFT))&AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_WP4_MASK                      0x2000u
+#define AIPS_PACRC_WP4_SHIFT                     13
+#define AIPS_PACRC_WP4_WIDTH                     1
+#define AIPS_PACRC_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP4_SHIFT))&AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_SP4_MASK                      0x4000u
+#define AIPS_PACRC_SP4_SHIFT                     14
+#define AIPS_PACRC_SP4_WIDTH                     1
+#define AIPS_PACRC_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP4_SHIFT))&AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_TP3_MASK                      0x10000u
+#define AIPS_PACRC_TP3_SHIFT                     16
+#define AIPS_PACRC_TP3_WIDTH                     1
+#define AIPS_PACRC_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP3_SHIFT))&AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_WP3_MASK                      0x20000u
+#define AIPS_PACRC_WP3_SHIFT                     17
+#define AIPS_PACRC_WP3_WIDTH                     1
+#define AIPS_PACRC_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP3_SHIFT))&AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_SP3_MASK                      0x40000u
+#define AIPS_PACRC_SP3_SHIFT                     18
+#define AIPS_PACRC_SP3_WIDTH                     1
+#define AIPS_PACRC_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP3_SHIFT))&AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_TP2_MASK                      0x100000u
+#define AIPS_PACRC_TP2_SHIFT                     20
+#define AIPS_PACRC_TP2_WIDTH                     1
+#define AIPS_PACRC_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP2_SHIFT))&AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_WP2_MASK                      0x200000u
+#define AIPS_PACRC_WP2_SHIFT                     21
+#define AIPS_PACRC_WP2_WIDTH                     1
+#define AIPS_PACRC_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP2_SHIFT))&AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_SP2_MASK                      0x400000u
+#define AIPS_PACRC_SP2_SHIFT                     22
+#define AIPS_PACRC_SP2_WIDTH                     1
+#define AIPS_PACRC_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP2_SHIFT))&AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_TP1_MASK                      0x1000000u
+#define AIPS_PACRC_TP1_SHIFT                     24
+#define AIPS_PACRC_TP1_WIDTH                     1
+#define AIPS_PACRC_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP1_SHIFT))&AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_WP1_MASK                      0x2000000u
+#define AIPS_PACRC_WP1_SHIFT                     25
+#define AIPS_PACRC_WP1_WIDTH                     1
+#define AIPS_PACRC_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP1_SHIFT))&AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_SP1_MASK                      0x4000000u
+#define AIPS_PACRC_SP1_SHIFT                     26
+#define AIPS_PACRC_SP1_WIDTH                     1
+#define AIPS_PACRC_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP1_SHIFT))&AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_TP0_MASK                      0x10000000u
+#define AIPS_PACRC_TP0_SHIFT                     28
+#define AIPS_PACRC_TP0_WIDTH                     1
+#define AIPS_PACRC_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP0_SHIFT))&AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_WP0_MASK                      0x20000000u
+#define AIPS_PACRC_WP0_SHIFT                     29
+#define AIPS_PACRC_WP0_WIDTH                     1
+#define AIPS_PACRC_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP0_SHIFT))&AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_SP0_MASK                      0x40000000u
+#define AIPS_PACRC_SP0_SHIFT                     30
+#define AIPS_PACRC_SP0_WIDTH                     1
+#define AIPS_PACRC_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP0_SHIFT))&AIPS_PACRC_SP0_MASK)
+/* PACRD Bit Fields */
+#define AIPS_PACRD_TP7_MASK                      0x1u
+#define AIPS_PACRD_TP7_SHIFT                     0
+#define AIPS_PACRD_TP7_WIDTH                     1
+#define AIPS_PACRD_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP7_SHIFT))&AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_WP7_MASK                      0x2u
+#define AIPS_PACRD_WP7_SHIFT                     1
+#define AIPS_PACRD_WP7_WIDTH                     1
+#define AIPS_PACRD_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP7_SHIFT))&AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_SP7_MASK                      0x4u
+#define AIPS_PACRD_SP7_SHIFT                     2
+#define AIPS_PACRD_SP7_WIDTH                     1
+#define AIPS_PACRD_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP7_SHIFT))&AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_TP6_MASK                      0x10u
+#define AIPS_PACRD_TP6_SHIFT                     4
+#define AIPS_PACRD_TP6_WIDTH                     1
+#define AIPS_PACRD_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP6_SHIFT))&AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_WP6_MASK                      0x20u
+#define AIPS_PACRD_WP6_SHIFT                     5
+#define AIPS_PACRD_WP6_WIDTH                     1
+#define AIPS_PACRD_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP6_SHIFT))&AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_SP6_MASK                      0x40u
+#define AIPS_PACRD_SP6_SHIFT                     6
+#define AIPS_PACRD_SP6_WIDTH                     1
+#define AIPS_PACRD_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP6_SHIFT))&AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_TP5_MASK                      0x100u
+#define AIPS_PACRD_TP5_SHIFT                     8
+#define AIPS_PACRD_TP5_WIDTH                     1
+#define AIPS_PACRD_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP5_SHIFT))&AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_WP5_MASK                      0x200u
+#define AIPS_PACRD_WP5_SHIFT                     9
+#define AIPS_PACRD_WP5_WIDTH                     1
+#define AIPS_PACRD_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP5_SHIFT))&AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_SP5_MASK                      0x400u
+#define AIPS_PACRD_SP5_SHIFT                     10
+#define AIPS_PACRD_SP5_WIDTH                     1
+#define AIPS_PACRD_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP5_SHIFT))&AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_TP4_MASK                      0x1000u
+#define AIPS_PACRD_TP4_SHIFT                     12
+#define AIPS_PACRD_TP4_WIDTH                     1
+#define AIPS_PACRD_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP4_SHIFT))&AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_WP4_MASK                      0x2000u
+#define AIPS_PACRD_WP4_SHIFT                     13
+#define AIPS_PACRD_WP4_WIDTH                     1
+#define AIPS_PACRD_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP4_SHIFT))&AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_SP4_MASK                      0x4000u
+#define AIPS_PACRD_SP4_SHIFT                     14
+#define AIPS_PACRD_SP4_WIDTH                     1
+#define AIPS_PACRD_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP4_SHIFT))&AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_TP3_MASK                      0x10000u
+#define AIPS_PACRD_TP3_SHIFT                     16
+#define AIPS_PACRD_TP3_WIDTH                     1
+#define AIPS_PACRD_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP3_SHIFT))&AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_WP3_MASK                      0x20000u
+#define AIPS_PACRD_WP3_SHIFT                     17
+#define AIPS_PACRD_WP3_WIDTH                     1
+#define AIPS_PACRD_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP3_SHIFT))&AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_SP3_MASK                      0x40000u
+#define AIPS_PACRD_SP3_SHIFT                     18
+#define AIPS_PACRD_SP3_WIDTH                     1
+#define AIPS_PACRD_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP3_SHIFT))&AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_TP2_MASK                      0x100000u
+#define AIPS_PACRD_TP2_SHIFT                     20
+#define AIPS_PACRD_TP2_WIDTH                     1
+#define AIPS_PACRD_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP2_SHIFT))&AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_WP2_MASK                      0x200000u
+#define AIPS_PACRD_WP2_SHIFT                     21
+#define AIPS_PACRD_WP2_WIDTH                     1
+#define AIPS_PACRD_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP2_SHIFT))&AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_SP2_MASK                      0x400000u
+#define AIPS_PACRD_SP2_SHIFT                     22
+#define AIPS_PACRD_SP2_WIDTH                     1
+#define AIPS_PACRD_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP2_SHIFT))&AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_TP1_MASK                      0x1000000u
+#define AIPS_PACRD_TP1_SHIFT                     24
+#define AIPS_PACRD_TP1_WIDTH                     1
+#define AIPS_PACRD_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP1_SHIFT))&AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_WP1_MASK                      0x2000000u
+#define AIPS_PACRD_WP1_SHIFT                     25
+#define AIPS_PACRD_WP1_WIDTH                     1
+#define AIPS_PACRD_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP1_SHIFT))&AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_SP1_MASK                      0x4000000u
+#define AIPS_PACRD_SP1_SHIFT                     26
+#define AIPS_PACRD_SP1_WIDTH                     1
+#define AIPS_PACRD_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP1_SHIFT))&AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_TP0_MASK                      0x10000000u
+#define AIPS_PACRD_TP0_SHIFT                     28
+#define AIPS_PACRD_TP0_WIDTH                     1
+#define AIPS_PACRD_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP0_SHIFT))&AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_WP0_MASK                      0x20000000u
+#define AIPS_PACRD_WP0_SHIFT                     29
+#define AIPS_PACRD_WP0_WIDTH                     1
+#define AIPS_PACRD_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP0_SHIFT))&AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_SP0_MASK                      0x40000000u
+#define AIPS_PACRD_SP0_SHIFT                     30
+#define AIPS_PACRD_SP0_WIDTH                     1
+#define AIPS_PACRD_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP0_SHIFT))&AIPS_PACRD_SP0_MASK)
+/* PACRE Bit Fields */
+#define AIPS_PACRE_TP7_MASK                      0x1u
+#define AIPS_PACRE_TP7_SHIFT                     0
+#define AIPS_PACRE_TP7_WIDTH                     1
+#define AIPS_PACRE_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP7_SHIFT))&AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_WP7_MASK                      0x2u
+#define AIPS_PACRE_WP7_SHIFT                     1
+#define AIPS_PACRE_WP7_WIDTH                     1
+#define AIPS_PACRE_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP7_SHIFT))&AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_SP7_MASK                      0x4u
+#define AIPS_PACRE_SP7_SHIFT                     2
+#define AIPS_PACRE_SP7_WIDTH                     1
+#define AIPS_PACRE_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP7_SHIFT))&AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_TP6_MASK                      0x10u
+#define AIPS_PACRE_TP6_SHIFT                     4
+#define AIPS_PACRE_TP6_WIDTH                     1
+#define AIPS_PACRE_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP6_SHIFT))&AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_WP6_MASK                      0x20u
+#define AIPS_PACRE_WP6_SHIFT                     5
+#define AIPS_PACRE_WP6_WIDTH                     1
+#define AIPS_PACRE_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP6_SHIFT))&AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_SP6_MASK                      0x40u
+#define AIPS_PACRE_SP6_SHIFT                     6
+#define AIPS_PACRE_SP6_WIDTH                     1
+#define AIPS_PACRE_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP6_SHIFT))&AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_TP5_MASK                      0x100u
+#define AIPS_PACRE_TP5_SHIFT                     8
+#define AIPS_PACRE_TP5_WIDTH                     1
+#define AIPS_PACRE_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP5_SHIFT))&AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_WP5_MASK                      0x200u
+#define AIPS_PACRE_WP5_SHIFT                     9
+#define AIPS_PACRE_WP5_WIDTH                     1
+#define AIPS_PACRE_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP5_SHIFT))&AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_SP5_MASK                      0x400u
+#define AIPS_PACRE_SP5_SHIFT                     10
+#define AIPS_PACRE_SP5_WIDTH                     1
+#define AIPS_PACRE_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP5_SHIFT))&AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_TP4_MASK                      0x1000u
+#define AIPS_PACRE_TP4_SHIFT                     12
+#define AIPS_PACRE_TP4_WIDTH                     1
+#define AIPS_PACRE_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP4_SHIFT))&AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_WP4_MASK                      0x2000u
+#define AIPS_PACRE_WP4_SHIFT                     13
+#define AIPS_PACRE_WP4_WIDTH                     1
+#define AIPS_PACRE_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP4_SHIFT))&AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_SP4_MASK                      0x4000u
+#define AIPS_PACRE_SP4_SHIFT                     14
+#define AIPS_PACRE_SP4_WIDTH                     1
+#define AIPS_PACRE_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP4_SHIFT))&AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_TP3_MASK                      0x10000u
+#define AIPS_PACRE_TP3_SHIFT                     16
+#define AIPS_PACRE_TP3_WIDTH                     1
+#define AIPS_PACRE_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP3_SHIFT))&AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_WP3_MASK                      0x20000u
+#define AIPS_PACRE_WP3_SHIFT                     17
+#define AIPS_PACRE_WP3_WIDTH                     1
+#define AIPS_PACRE_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP3_SHIFT))&AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_SP3_MASK                      0x40000u
+#define AIPS_PACRE_SP3_SHIFT                     18
+#define AIPS_PACRE_SP3_WIDTH                     1
+#define AIPS_PACRE_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP3_SHIFT))&AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_TP2_MASK                      0x100000u
+#define AIPS_PACRE_TP2_SHIFT                     20
+#define AIPS_PACRE_TP2_WIDTH                     1
+#define AIPS_PACRE_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP2_SHIFT))&AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_WP2_MASK                      0x200000u
+#define AIPS_PACRE_WP2_SHIFT                     21
+#define AIPS_PACRE_WP2_WIDTH                     1
+#define AIPS_PACRE_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP2_SHIFT))&AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_SP2_MASK                      0x400000u
+#define AIPS_PACRE_SP2_SHIFT                     22
+#define AIPS_PACRE_SP2_WIDTH                     1
+#define AIPS_PACRE_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP2_SHIFT))&AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_TP1_MASK                      0x1000000u
+#define AIPS_PACRE_TP1_SHIFT                     24
+#define AIPS_PACRE_TP1_WIDTH                     1
+#define AIPS_PACRE_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP1_SHIFT))&AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_WP1_MASK                      0x2000000u
+#define AIPS_PACRE_WP1_SHIFT                     25
+#define AIPS_PACRE_WP1_WIDTH                     1
+#define AIPS_PACRE_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP1_SHIFT))&AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_SP1_MASK                      0x4000000u
+#define AIPS_PACRE_SP1_SHIFT                     26
+#define AIPS_PACRE_SP1_WIDTH                     1
+#define AIPS_PACRE_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP1_SHIFT))&AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_TP0_MASK                      0x10000000u
+#define AIPS_PACRE_TP0_SHIFT                     28
+#define AIPS_PACRE_TP0_WIDTH                     1
+#define AIPS_PACRE_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP0_SHIFT))&AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_WP0_MASK                      0x20000000u
+#define AIPS_PACRE_WP0_SHIFT                     29
+#define AIPS_PACRE_WP0_WIDTH                     1
+#define AIPS_PACRE_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP0_SHIFT))&AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_SP0_MASK                      0x40000000u
+#define AIPS_PACRE_SP0_SHIFT                     30
+#define AIPS_PACRE_SP0_WIDTH                     1
+#define AIPS_PACRE_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP0_SHIFT))&AIPS_PACRE_SP0_MASK)
+/* PACRF Bit Fields */
+#define AIPS_PACRF_TP7_MASK                      0x1u
+#define AIPS_PACRF_TP7_SHIFT                     0
+#define AIPS_PACRF_TP7_WIDTH                     1
+#define AIPS_PACRF_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP7_SHIFT))&AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_WP7_MASK                      0x2u
+#define AIPS_PACRF_WP7_SHIFT                     1
+#define AIPS_PACRF_WP7_WIDTH                     1
+#define AIPS_PACRF_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP7_SHIFT))&AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_SP7_MASK                      0x4u
+#define AIPS_PACRF_SP7_SHIFT                     2
+#define AIPS_PACRF_SP7_WIDTH                     1
+#define AIPS_PACRF_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP7_SHIFT))&AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_TP6_MASK                      0x10u
+#define AIPS_PACRF_TP6_SHIFT                     4
+#define AIPS_PACRF_TP6_WIDTH                     1
+#define AIPS_PACRF_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP6_SHIFT))&AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_WP6_MASK                      0x20u
+#define AIPS_PACRF_WP6_SHIFT                     5
+#define AIPS_PACRF_WP6_WIDTH                     1
+#define AIPS_PACRF_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP6_SHIFT))&AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_SP6_MASK                      0x40u
+#define AIPS_PACRF_SP6_SHIFT                     6
+#define AIPS_PACRF_SP6_WIDTH                     1
+#define AIPS_PACRF_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP6_SHIFT))&AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_TP5_MASK                      0x100u
+#define AIPS_PACRF_TP5_SHIFT                     8
+#define AIPS_PACRF_TP5_WIDTH                     1
+#define AIPS_PACRF_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP5_SHIFT))&AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_WP5_MASK                      0x200u
+#define AIPS_PACRF_WP5_SHIFT                     9
+#define AIPS_PACRF_WP5_WIDTH                     1
+#define AIPS_PACRF_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP5_SHIFT))&AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_SP5_MASK                      0x400u
+#define AIPS_PACRF_SP5_SHIFT                     10
+#define AIPS_PACRF_SP5_WIDTH                     1
+#define AIPS_PACRF_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP5_SHIFT))&AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_TP4_MASK                      0x1000u
+#define AIPS_PACRF_TP4_SHIFT                     12
+#define AIPS_PACRF_TP4_WIDTH                     1
+#define AIPS_PACRF_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP4_SHIFT))&AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_WP4_MASK                      0x2000u
+#define AIPS_PACRF_WP4_SHIFT                     13
+#define AIPS_PACRF_WP4_WIDTH                     1
+#define AIPS_PACRF_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP4_SHIFT))&AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_SP4_MASK                      0x4000u
+#define AIPS_PACRF_SP4_SHIFT                     14
+#define AIPS_PACRF_SP4_WIDTH                     1
+#define AIPS_PACRF_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP4_SHIFT))&AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_TP3_MASK                      0x10000u
+#define AIPS_PACRF_TP3_SHIFT                     16
+#define AIPS_PACRF_TP3_WIDTH                     1
+#define AIPS_PACRF_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP3_SHIFT))&AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_WP3_MASK                      0x20000u
+#define AIPS_PACRF_WP3_SHIFT                     17
+#define AIPS_PACRF_WP3_WIDTH                     1
+#define AIPS_PACRF_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP3_SHIFT))&AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_SP3_MASK                      0x40000u
+#define AIPS_PACRF_SP3_SHIFT                     18
+#define AIPS_PACRF_SP3_WIDTH                     1
+#define AIPS_PACRF_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP3_SHIFT))&AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_TP2_MASK                      0x100000u
+#define AIPS_PACRF_TP2_SHIFT                     20
+#define AIPS_PACRF_TP2_WIDTH                     1
+#define AIPS_PACRF_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP2_SHIFT))&AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_WP2_MASK                      0x200000u
+#define AIPS_PACRF_WP2_SHIFT                     21
+#define AIPS_PACRF_WP2_WIDTH                     1
+#define AIPS_PACRF_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP2_SHIFT))&AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_SP2_MASK                      0x400000u
+#define AIPS_PACRF_SP2_SHIFT                     22
+#define AIPS_PACRF_SP2_WIDTH                     1
+#define AIPS_PACRF_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP2_SHIFT))&AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_TP1_MASK                      0x1000000u
+#define AIPS_PACRF_TP1_SHIFT                     24
+#define AIPS_PACRF_TP1_WIDTH                     1
+#define AIPS_PACRF_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP1_SHIFT))&AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_WP1_MASK                      0x2000000u
+#define AIPS_PACRF_WP1_SHIFT                     25
+#define AIPS_PACRF_WP1_WIDTH                     1
+#define AIPS_PACRF_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP1_SHIFT))&AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_SP1_MASK                      0x4000000u
+#define AIPS_PACRF_SP1_SHIFT                     26
+#define AIPS_PACRF_SP1_WIDTH                     1
+#define AIPS_PACRF_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP1_SHIFT))&AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_TP0_MASK                      0x10000000u
+#define AIPS_PACRF_TP0_SHIFT                     28
+#define AIPS_PACRF_TP0_WIDTH                     1
+#define AIPS_PACRF_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP0_SHIFT))&AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_WP0_MASK                      0x20000000u
+#define AIPS_PACRF_WP0_SHIFT                     29
+#define AIPS_PACRF_WP0_WIDTH                     1
+#define AIPS_PACRF_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP0_SHIFT))&AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_SP0_MASK                      0x40000000u
+#define AIPS_PACRF_SP0_SHIFT                     30
+#define AIPS_PACRF_SP0_WIDTH                     1
+#define AIPS_PACRF_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP0_SHIFT))&AIPS_PACRF_SP0_MASK)
+/* PACRG Bit Fields */
+#define AIPS_PACRG_TP7_MASK                      0x1u
+#define AIPS_PACRG_TP7_SHIFT                     0
+#define AIPS_PACRG_TP7_WIDTH                     1
+#define AIPS_PACRG_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP7_SHIFT))&AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_WP7_MASK                      0x2u
+#define AIPS_PACRG_WP7_SHIFT                     1
+#define AIPS_PACRG_WP7_WIDTH                     1
+#define AIPS_PACRG_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP7_SHIFT))&AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_SP7_MASK                      0x4u
+#define AIPS_PACRG_SP7_SHIFT                     2
+#define AIPS_PACRG_SP7_WIDTH                     1
+#define AIPS_PACRG_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP7_SHIFT))&AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_TP6_MASK                      0x10u
+#define AIPS_PACRG_TP6_SHIFT                     4
+#define AIPS_PACRG_TP6_WIDTH                     1
+#define AIPS_PACRG_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP6_SHIFT))&AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_WP6_MASK                      0x20u
+#define AIPS_PACRG_WP6_SHIFT                     5
+#define AIPS_PACRG_WP6_WIDTH                     1
+#define AIPS_PACRG_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP6_SHIFT))&AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_SP6_MASK                      0x40u
+#define AIPS_PACRG_SP6_SHIFT                     6
+#define AIPS_PACRG_SP6_WIDTH                     1
+#define AIPS_PACRG_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP6_SHIFT))&AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_TP5_MASK                      0x100u
+#define AIPS_PACRG_TP5_SHIFT                     8
+#define AIPS_PACRG_TP5_WIDTH                     1
+#define AIPS_PACRG_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP5_SHIFT))&AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_WP5_MASK                      0x200u
+#define AIPS_PACRG_WP5_SHIFT                     9
+#define AIPS_PACRG_WP5_WIDTH                     1
+#define AIPS_PACRG_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP5_SHIFT))&AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_SP5_MASK                      0x400u
+#define AIPS_PACRG_SP5_SHIFT                     10
+#define AIPS_PACRG_SP5_WIDTH                     1
+#define AIPS_PACRG_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP5_SHIFT))&AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_TP4_MASK                      0x1000u
+#define AIPS_PACRG_TP4_SHIFT                     12
+#define AIPS_PACRG_TP4_WIDTH                     1
+#define AIPS_PACRG_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP4_SHIFT))&AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_WP4_MASK                      0x2000u
+#define AIPS_PACRG_WP4_SHIFT                     13
+#define AIPS_PACRG_WP4_WIDTH                     1
+#define AIPS_PACRG_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP4_SHIFT))&AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_SP4_MASK                      0x4000u
+#define AIPS_PACRG_SP4_SHIFT                     14
+#define AIPS_PACRG_SP4_WIDTH                     1
+#define AIPS_PACRG_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP4_SHIFT))&AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_TP3_MASK                      0x10000u
+#define AIPS_PACRG_TP3_SHIFT                     16
+#define AIPS_PACRG_TP3_WIDTH                     1
+#define AIPS_PACRG_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP3_SHIFT))&AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_WP3_MASK                      0x20000u
+#define AIPS_PACRG_WP3_SHIFT                     17
+#define AIPS_PACRG_WP3_WIDTH                     1
+#define AIPS_PACRG_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP3_SHIFT))&AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_SP3_MASK                      0x40000u
+#define AIPS_PACRG_SP3_SHIFT                     18
+#define AIPS_PACRG_SP3_WIDTH                     1
+#define AIPS_PACRG_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP3_SHIFT))&AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_TP2_MASK                      0x100000u
+#define AIPS_PACRG_TP2_SHIFT                     20
+#define AIPS_PACRG_TP2_WIDTH                     1
+#define AIPS_PACRG_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP2_SHIFT))&AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_WP2_MASK                      0x200000u
+#define AIPS_PACRG_WP2_SHIFT                     21
+#define AIPS_PACRG_WP2_WIDTH                     1
+#define AIPS_PACRG_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP2_SHIFT))&AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_SP2_MASK                      0x400000u
+#define AIPS_PACRG_SP2_SHIFT                     22
+#define AIPS_PACRG_SP2_WIDTH                     1
+#define AIPS_PACRG_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP2_SHIFT))&AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_TP1_MASK                      0x1000000u
+#define AIPS_PACRG_TP1_SHIFT                     24
+#define AIPS_PACRG_TP1_WIDTH                     1
+#define AIPS_PACRG_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP1_SHIFT))&AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_WP1_MASK                      0x2000000u
+#define AIPS_PACRG_WP1_SHIFT                     25
+#define AIPS_PACRG_WP1_WIDTH                     1
+#define AIPS_PACRG_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP1_SHIFT))&AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_SP1_MASK                      0x4000000u
+#define AIPS_PACRG_SP1_SHIFT                     26
+#define AIPS_PACRG_SP1_WIDTH                     1
+#define AIPS_PACRG_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP1_SHIFT))&AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_TP0_MASK                      0x10000000u
+#define AIPS_PACRG_TP0_SHIFT                     28
+#define AIPS_PACRG_TP0_WIDTH                     1
+#define AIPS_PACRG_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP0_SHIFT))&AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_WP0_MASK                      0x20000000u
+#define AIPS_PACRG_WP0_SHIFT                     29
+#define AIPS_PACRG_WP0_WIDTH                     1
+#define AIPS_PACRG_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP0_SHIFT))&AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_SP0_MASK                      0x40000000u
+#define AIPS_PACRG_SP0_SHIFT                     30
+#define AIPS_PACRG_SP0_WIDTH                     1
+#define AIPS_PACRG_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP0_SHIFT))&AIPS_PACRG_SP0_MASK)
+/* PACRH Bit Fields */
+#define AIPS_PACRH_TP7_MASK                      0x1u
+#define AIPS_PACRH_TP7_SHIFT                     0
+#define AIPS_PACRH_TP7_WIDTH                     1
+#define AIPS_PACRH_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP7_SHIFT))&AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_WP7_MASK                      0x2u
+#define AIPS_PACRH_WP7_SHIFT                     1
+#define AIPS_PACRH_WP7_WIDTH                     1
+#define AIPS_PACRH_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP7_SHIFT))&AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_SP7_MASK                      0x4u
+#define AIPS_PACRH_SP7_SHIFT                     2
+#define AIPS_PACRH_SP7_WIDTH                     1
+#define AIPS_PACRH_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP7_SHIFT))&AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_TP6_MASK                      0x10u
+#define AIPS_PACRH_TP6_SHIFT                     4
+#define AIPS_PACRH_TP6_WIDTH                     1
+#define AIPS_PACRH_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP6_SHIFT))&AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_WP6_MASK                      0x20u
+#define AIPS_PACRH_WP6_SHIFT                     5
+#define AIPS_PACRH_WP6_WIDTH                     1
+#define AIPS_PACRH_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP6_SHIFT))&AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_SP6_MASK                      0x40u
+#define AIPS_PACRH_SP6_SHIFT                     6
+#define AIPS_PACRH_SP6_WIDTH                     1
+#define AIPS_PACRH_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP6_SHIFT))&AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_TP5_MASK                      0x100u
+#define AIPS_PACRH_TP5_SHIFT                     8
+#define AIPS_PACRH_TP5_WIDTH                     1
+#define AIPS_PACRH_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP5_SHIFT))&AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_WP5_MASK                      0x200u
+#define AIPS_PACRH_WP5_SHIFT                     9
+#define AIPS_PACRH_WP5_WIDTH                     1
+#define AIPS_PACRH_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP5_SHIFT))&AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_SP5_MASK                      0x400u
+#define AIPS_PACRH_SP5_SHIFT                     10
+#define AIPS_PACRH_SP5_WIDTH                     1
+#define AIPS_PACRH_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP5_SHIFT))&AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_TP4_MASK                      0x1000u
+#define AIPS_PACRH_TP4_SHIFT                     12
+#define AIPS_PACRH_TP4_WIDTH                     1
+#define AIPS_PACRH_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP4_SHIFT))&AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_WP4_MASK                      0x2000u
+#define AIPS_PACRH_WP4_SHIFT                     13
+#define AIPS_PACRH_WP4_WIDTH                     1
+#define AIPS_PACRH_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP4_SHIFT))&AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_SP4_MASK                      0x4000u
+#define AIPS_PACRH_SP4_SHIFT                     14
+#define AIPS_PACRH_SP4_WIDTH                     1
+#define AIPS_PACRH_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP4_SHIFT))&AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_TP3_MASK                      0x10000u
+#define AIPS_PACRH_TP3_SHIFT                     16
+#define AIPS_PACRH_TP3_WIDTH                     1
+#define AIPS_PACRH_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP3_SHIFT))&AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_WP3_MASK                      0x20000u
+#define AIPS_PACRH_WP3_SHIFT                     17
+#define AIPS_PACRH_WP3_WIDTH                     1
+#define AIPS_PACRH_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP3_SHIFT))&AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_SP3_MASK                      0x40000u
+#define AIPS_PACRH_SP3_SHIFT                     18
+#define AIPS_PACRH_SP3_WIDTH                     1
+#define AIPS_PACRH_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP3_SHIFT))&AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_TP2_MASK                      0x100000u
+#define AIPS_PACRH_TP2_SHIFT                     20
+#define AIPS_PACRH_TP2_WIDTH                     1
+#define AIPS_PACRH_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP2_SHIFT))&AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_WP2_MASK                      0x200000u
+#define AIPS_PACRH_WP2_SHIFT                     21
+#define AIPS_PACRH_WP2_WIDTH                     1
+#define AIPS_PACRH_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP2_SHIFT))&AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_SP2_MASK                      0x400000u
+#define AIPS_PACRH_SP2_SHIFT                     22
+#define AIPS_PACRH_SP2_WIDTH                     1
+#define AIPS_PACRH_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP2_SHIFT))&AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_TP1_MASK                      0x1000000u
+#define AIPS_PACRH_TP1_SHIFT                     24
+#define AIPS_PACRH_TP1_WIDTH                     1
+#define AIPS_PACRH_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP1_SHIFT))&AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_WP1_MASK                      0x2000000u
+#define AIPS_PACRH_WP1_SHIFT                     25
+#define AIPS_PACRH_WP1_WIDTH                     1
+#define AIPS_PACRH_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP1_SHIFT))&AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_SP1_MASK                      0x4000000u
+#define AIPS_PACRH_SP1_SHIFT                     26
+#define AIPS_PACRH_SP1_WIDTH                     1
+#define AIPS_PACRH_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP1_SHIFT))&AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_TP0_MASK                      0x10000000u
+#define AIPS_PACRH_TP0_SHIFT                     28
+#define AIPS_PACRH_TP0_WIDTH                     1
+#define AIPS_PACRH_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP0_SHIFT))&AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_WP0_MASK                      0x20000000u
+#define AIPS_PACRH_WP0_SHIFT                     29
+#define AIPS_PACRH_WP0_WIDTH                     1
+#define AIPS_PACRH_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP0_SHIFT))&AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_SP0_MASK                      0x40000000u
+#define AIPS_PACRH_SP0_SHIFT                     30
+#define AIPS_PACRH_SP0_WIDTH                     1
+#define AIPS_PACRH_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP0_SHIFT))&AIPS_PACRH_SP0_MASK)
+/* PACRI Bit Fields */
+#define AIPS_PACRI_TP7_MASK                      0x1u
+#define AIPS_PACRI_TP7_SHIFT                     0
+#define AIPS_PACRI_TP7_WIDTH                     1
+#define AIPS_PACRI_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP7_SHIFT))&AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_WP7_MASK                      0x2u
+#define AIPS_PACRI_WP7_SHIFT                     1
+#define AIPS_PACRI_WP7_WIDTH                     1
+#define AIPS_PACRI_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP7_SHIFT))&AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_SP7_MASK                      0x4u
+#define AIPS_PACRI_SP7_SHIFT                     2
+#define AIPS_PACRI_SP7_WIDTH                     1
+#define AIPS_PACRI_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP7_SHIFT))&AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_TP6_MASK                      0x10u
+#define AIPS_PACRI_TP6_SHIFT                     4
+#define AIPS_PACRI_TP6_WIDTH                     1
+#define AIPS_PACRI_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP6_SHIFT))&AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_WP6_MASK                      0x20u
+#define AIPS_PACRI_WP6_SHIFT                     5
+#define AIPS_PACRI_WP6_WIDTH                     1
+#define AIPS_PACRI_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP6_SHIFT))&AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_SP6_MASK                      0x40u
+#define AIPS_PACRI_SP6_SHIFT                     6
+#define AIPS_PACRI_SP6_WIDTH                     1
+#define AIPS_PACRI_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP6_SHIFT))&AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_TP5_MASK                      0x100u
+#define AIPS_PACRI_TP5_SHIFT                     8
+#define AIPS_PACRI_TP5_WIDTH                     1
+#define AIPS_PACRI_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP5_SHIFT))&AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_WP5_MASK                      0x200u
+#define AIPS_PACRI_WP5_SHIFT                     9
+#define AIPS_PACRI_WP5_WIDTH                     1
+#define AIPS_PACRI_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP5_SHIFT))&AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_SP5_MASK                      0x400u
+#define AIPS_PACRI_SP5_SHIFT                     10
+#define AIPS_PACRI_SP5_WIDTH                     1
+#define AIPS_PACRI_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP5_SHIFT))&AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_TP4_MASK                      0x1000u
+#define AIPS_PACRI_TP4_SHIFT                     12
+#define AIPS_PACRI_TP4_WIDTH                     1
+#define AIPS_PACRI_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP4_SHIFT))&AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_WP4_MASK                      0x2000u
+#define AIPS_PACRI_WP4_SHIFT                     13
+#define AIPS_PACRI_WP4_WIDTH                     1
+#define AIPS_PACRI_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP4_SHIFT))&AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_SP4_MASK                      0x4000u
+#define AIPS_PACRI_SP4_SHIFT                     14
+#define AIPS_PACRI_SP4_WIDTH                     1
+#define AIPS_PACRI_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP4_SHIFT))&AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_TP3_MASK                      0x10000u
+#define AIPS_PACRI_TP3_SHIFT                     16
+#define AIPS_PACRI_TP3_WIDTH                     1
+#define AIPS_PACRI_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP3_SHIFT))&AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_WP3_MASK                      0x20000u
+#define AIPS_PACRI_WP3_SHIFT                     17
+#define AIPS_PACRI_WP3_WIDTH                     1
+#define AIPS_PACRI_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP3_SHIFT))&AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_SP3_MASK                      0x40000u
+#define AIPS_PACRI_SP3_SHIFT                     18
+#define AIPS_PACRI_SP3_WIDTH                     1
+#define AIPS_PACRI_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP3_SHIFT))&AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_TP2_MASK                      0x100000u
+#define AIPS_PACRI_TP2_SHIFT                     20
+#define AIPS_PACRI_TP2_WIDTH                     1
+#define AIPS_PACRI_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP2_SHIFT))&AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_WP2_MASK                      0x200000u
+#define AIPS_PACRI_WP2_SHIFT                     21
+#define AIPS_PACRI_WP2_WIDTH                     1
+#define AIPS_PACRI_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP2_SHIFT))&AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_SP2_MASK                      0x400000u
+#define AIPS_PACRI_SP2_SHIFT                     22
+#define AIPS_PACRI_SP2_WIDTH                     1
+#define AIPS_PACRI_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP2_SHIFT))&AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_TP1_MASK                      0x1000000u
+#define AIPS_PACRI_TP1_SHIFT                     24
+#define AIPS_PACRI_TP1_WIDTH                     1
+#define AIPS_PACRI_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP1_SHIFT))&AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_WP1_MASK                      0x2000000u
+#define AIPS_PACRI_WP1_SHIFT                     25
+#define AIPS_PACRI_WP1_WIDTH                     1
+#define AIPS_PACRI_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP1_SHIFT))&AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_SP1_MASK                      0x4000000u
+#define AIPS_PACRI_SP1_SHIFT                     26
+#define AIPS_PACRI_SP1_WIDTH                     1
+#define AIPS_PACRI_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP1_SHIFT))&AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_TP0_MASK                      0x10000000u
+#define AIPS_PACRI_TP0_SHIFT                     28
+#define AIPS_PACRI_TP0_WIDTH                     1
+#define AIPS_PACRI_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP0_SHIFT))&AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_WP0_MASK                      0x20000000u
+#define AIPS_PACRI_WP0_SHIFT                     29
+#define AIPS_PACRI_WP0_WIDTH                     1
+#define AIPS_PACRI_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP0_SHIFT))&AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_SP0_MASK                      0x40000000u
+#define AIPS_PACRI_SP0_SHIFT                     30
+#define AIPS_PACRI_SP0_WIDTH                     1
+#define AIPS_PACRI_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP0_SHIFT))&AIPS_PACRI_SP0_MASK)
+/* PACRJ Bit Fields */
+#define AIPS_PACRJ_TP7_MASK                      0x1u
+#define AIPS_PACRJ_TP7_SHIFT                     0
+#define AIPS_PACRJ_TP7_WIDTH                     1
+#define AIPS_PACRJ_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP7_SHIFT))&AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_WP7_MASK                      0x2u
+#define AIPS_PACRJ_WP7_SHIFT                     1
+#define AIPS_PACRJ_WP7_WIDTH                     1
+#define AIPS_PACRJ_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP7_SHIFT))&AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_SP7_MASK                      0x4u
+#define AIPS_PACRJ_SP7_SHIFT                     2
+#define AIPS_PACRJ_SP7_WIDTH                     1
+#define AIPS_PACRJ_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP7_SHIFT))&AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_TP6_MASK                      0x10u
+#define AIPS_PACRJ_TP6_SHIFT                     4
+#define AIPS_PACRJ_TP6_WIDTH                     1
+#define AIPS_PACRJ_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP6_SHIFT))&AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_WP6_MASK                      0x20u
+#define AIPS_PACRJ_WP6_SHIFT                     5
+#define AIPS_PACRJ_WP6_WIDTH                     1
+#define AIPS_PACRJ_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP6_SHIFT))&AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_SP6_MASK                      0x40u
+#define AIPS_PACRJ_SP6_SHIFT                     6
+#define AIPS_PACRJ_SP6_WIDTH                     1
+#define AIPS_PACRJ_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP6_SHIFT))&AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_TP5_MASK                      0x100u
+#define AIPS_PACRJ_TP5_SHIFT                     8
+#define AIPS_PACRJ_TP5_WIDTH                     1
+#define AIPS_PACRJ_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP5_SHIFT))&AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_WP5_MASK                      0x200u
+#define AIPS_PACRJ_WP5_SHIFT                     9
+#define AIPS_PACRJ_WP5_WIDTH                     1
+#define AIPS_PACRJ_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP5_SHIFT))&AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_SP5_MASK                      0x400u
+#define AIPS_PACRJ_SP5_SHIFT                     10
+#define AIPS_PACRJ_SP5_WIDTH                     1
+#define AIPS_PACRJ_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP5_SHIFT))&AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_TP4_MASK                      0x1000u
+#define AIPS_PACRJ_TP4_SHIFT                     12
+#define AIPS_PACRJ_TP4_WIDTH                     1
+#define AIPS_PACRJ_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP4_SHIFT))&AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_WP4_MASK                      0x2000u
+#define AIPS_PACRJ_WP4_SHIFT                     13
+#define AIPS_PACRJ_WP4_WIDTH                     1
+#define AIPS_PACRJ_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP4_SHIFT))&AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_SP4_MASK                      0x4000u
+#define AIPS_PACRJ_SP4_SHIFT                     14
+#define AIPS_PACRJ_SP4_WIDTH                     1
+#define AIPS_PACRJ_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP4_SHIFT))&AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_TP3_MASK                      0x10000u
+#define AIPS_PACRJ_TP3_SHIFT                     16
+#define AIPS_PACRJ_TP3_WIDTH                     1
+#define AIPS_PACRJ_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP3_SHIFT))&AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_WP3_MASK                      0x20000u
+#define AIPS_PACRJ_WP3_SHIFT                     17
+#define AIPS_PACRJ_WP3_WIDTH                     1
+#define AIPS_PACRJ_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP3_SHIFT))&AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_SP3_MASK                      0x40000u
+#define AIPS_PACRJ_SP3_SHIFT                     18
+#define AIPS_PACRJ_SP3_WIDTH                     1
+#define AIPS_PACRJ_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP3_SHIFT))&AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_TP2_MASK                      0x100000u
+#define AIPS_PACRJ_TP2_SHIFT                     20
+#define AIPS_PACRJ_TP2_WIDTH                     1
+#define AIPS_PACRJ_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP2_SHIFT))&AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_WP2_MASK                      0x200000u
+#define AIPS_PACRJ_WP2_SHIFT                     21
+#define AIPS_PACRJ_WP2_WIDTH                     1
+#define AIPS_PACRJ_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP2_SHIFT))&AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_SP2_MASK                      0x400000u
+#define AIPS_PACRJ_SP2_SHIFT                     22
+#define AIPS_PACRJ_SP2_WIDTH                     1
+#define AIPS_PACRJ_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP2_SHIFT))&AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_TP1_MASK                      0x1000000u
+#define AIPS_PACRJ_TP1_SHIFT                     24
+#define AIPS_PACRJ_TP1_WIDTH                     1
+#define AIPS_PACRJ_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP1_SHIFT))&AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_WP1_MASK                      0x2000000u
+#define AIPS_PACRJ_WP1_SHIFT                     25
+#define AIPS_PACRJ_WP1_WIDTH                     1
+#define AIPS_PACRJ_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP1_SHIFT))&AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_SP1_MASK                      0x4000000u
+#define AIPS_PACRJ_SP1_SHIFT                     26
+#define AIPS_PACRJ_SP1_WIDTH                     1
+#define AIPS_PACRJ_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP1_SHIFT))&AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_TP0_MASK                      0x10000000u
+#define AIPS_PACRJ_TP0_SHIFT                     28
+#define AIPS_PACRJ_TP0_WIDTH                     1
+#define AIPS_PACRJ_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP0_SHIFT))&AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_WP0_MASK                      0x20000000u
+#define AIPS_PACRJ_WP0_SHIFT                     29
+#define AIPS_PACRJ_WP0_WIDTH                     1
+#define AIPS_PACRJ_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP0_SHIFT))&AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_SP0_MASK                      0x40000000u
+#define AIPS_PACRJ_SP0_SHIFT                     30
+#define AIPS_PACRJ_SP0_WIDTH                     1
+#define AIPS_PACRJ_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP0_SHIFT))&AIPS_PACRJ_SP0_MASK)
+/* PACRK Bit Fields */
+#define AIPS_PACRK_TP7_MASK                      0x1u
+#define AIPS_PACRK_TP7_SHIFT                     0
+#define AIPS_PACRK_TP7_WIDTH                     1
+#define AIPS_PACRK_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP7_SHIFT))&AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_WP7_MASK                      0x2u
+#define AIPS_PACRK_WP7_SHIFT                     1
+#define AIPS_PACRK_WP7_WIDTH                     1
+#define AIPS_PACRK_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP7_SHIFT))&AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_SP7_MASK                      0x4u
+#define AIPS_PACRK_SP7_SHIFT                     2
+#define AIPS_PACRK_SP7_WIDTH                     1
+#define AIPS_PACRK_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP7_SHIFT))&AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_TP6_MASK                      0x10u
+#define AIPS_PACRK_TP6_SHIFT                     4
+#define AIPS_PACRK_TP6_WIDTH                     1
+#define AIPS_PACRK_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP6_SHIFT))&AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_WP6_MASK                      0x20u
+#define AIPS_PACRK_WP6_SHIFT                     5
+#define AIPS_PACRK_WP6_WIDTH                     1
+#define AIPS_PACRK_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP6_SHIFT))&AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_SP6_MASK                      0x40u
+#define AIPS_PACRK_SP6_SHIFT                     6
+#define AIPS_PACRK_SP6_WIDTH                     1
+#define AIPS_PACRK_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP6_SHIFT))&AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_TP5_MASK                      0x100u
+#define AIPS_PACRK_TP5_SHIFT                     8
+#define AIPS_PACRK_TP5_WIDTH                     1
+#define AIPS_PACRK_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP5_SHIFT))&AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_WP5_MASK                      0x200u
+#define AIPS_PACRK_WP5_SHIFT                     9
+#define AIPS_PACRK_WP5_WIDTH                     1
+#define AIPS_PACRK_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP5_SHIFT))&AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_SP5_MASK                      0x400u
+#define AIPS_PACRK_SP5_SHIFT                     10
+#define AIPS_PACRK_SP5_WIDTH                     1
+#define AIPS_PACRK_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP5_SHIFT))&AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_TP4_MASK                      0x1000u
+#define AIPS_PACRK_TP4_SHIFT                     12
+#define AIPS_PACRK_TP4_WIDTH                     1
+#define AIPS_PACRK_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP4_SHIFT))&AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_WP4_MASK                      0x2000u
+#define AIPS_PACRK_WP4_SHIFT                     13
+#define AIPS_PACRK_WP4_WIDTH                     1
+#define AIPS_PACRK_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP4_SHIFT))&AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_SP4_MASK                      0x4000u
+#define AIPS_PACRK_SP4_SHIFT                     14
+#define AIPS_PACRK_SP4_WIDTH                     1
+#define AIPS_PACRK_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP4_SHIFT))&AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_TP3_MASK                      0x10000u
+#define AIPS_PACRK_TP3_SHIFT                     16
+#define AIPS_PACRK_TP3_WIDTH                     1
+#define AIPS_PACRK_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP3_SHIFT))&AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_WP3_MASK                      0x20000u
+#define AIPS_PACRK_WP3_SHIFT                     17
+#define AIPS_PACRK_WP3_WIDTH                     1
+#define AIPS_PACRK_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP3_SHIFT))&AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_SP3_MASK                      0x40000u
+#define AIPS_PACRK_SP3_SHIFT                     18
+#define AIPS_PACRK_SP3_WIDTH                     1
+#define AIPS_PACRK_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP3_SHIFT))&AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_TP2_MASK                      0x100000u
+#define AIPS_PACRK_TP2_SHIFT                     20
+#define AIPS_PACRK_TP2_WIDTH                     1
+#define AIPS_PACRK_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP2_SHIFT))&AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_WP2_MASK                      0x200000u
+#define AIPS_PACRK_WP2_SHIFT                     21
+#define AIPS_PACRK_WP2_WIDTH                     1
+#define AIPS_PACRK_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP2_SHIFT))&AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_SP2_MASK                      0x400000u
+#define AIPS_PACRK_SP2_SHIFT                     22
+#define AIPS_PACRK_SP2_WIDTH                     1
+#define AIPS_PACRK_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP2_SHIFT))&AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_TP1_MASK                      0x1000000u
+#define AIPS_PACRK_TP1_SHIFT                     24
+#define AIPS_PACRK_TP1_WIDTH                     1
+#define AIPS_PACRK_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP1_SHIFT))&AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_WP1_MASK                      0x2000000u
+#define AIPS_PACRK_WP1_SHIFT                     25
+#define AIPS_PACRK_WP1_WIDTH                     1
+#define AIPS_PACRK_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP1_SHIFT))&AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_SP1_MASK                      0x4000000u
+#define AIPS_PACRK_SP1_SHIFT                     26
+#define AIPS_PACRK_SP1_WIDTH                     1
+#define AIPS_PACRK_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP1_SHIFT))&AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_TP0_MASK                      0x10000000u
+#define AIPS_PACRK_TP0_SHIFT                     28
+#define AIPS_PACRK_TP0_WIDTH                     1
+#define AIPS_PACRK_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP0_SHIFT))&AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_WP0_MASK                      0x20000000u
+#define AIPS_PACRK_WP0_SHIFT                     29
+#define AIPS_PACRK_WP0_WIDTH                     1
+#define AIPS_PACRK_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP0_SHIFT))&AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_SP0_MASK                      0x40000000u
+#define AIPS_PACRK_SP0_SHIFT                     30
+#define AIPS_PACRK_SP0_WIDTH                     1
+#define AIPS_PACRK_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP0_SHIFT))&AIPS_PACRK_SP0_MASK)
+/* PACRL Bit Fields */
+#define AIPS_PACRL_TP7_MASK                      0x1u
+#define AIPS_PACRL_TP7_SHIFT                     0
+#define AIPS_PACRL_TP7_WIDTH                     1
+#define AIPS_PACRL_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP7_SHIFT))&AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_WP7_MASK                      0x2u
+#define AIPS_PACRL_WP7_SHIFT                     1
+#define AIPS_PACRL_WP7_WIDTH                     1
+#define AIPS_PACRL_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP7_SHIFT))&AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_SP7_MASK                      0x4u
+#define AIPS_PACRL_SP7_SHIFT                     2
+#define AIPS_PACRL_SP7_WIDTH                     1
+#define AIPS_PACRL_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP7_SHIFT))&AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_TP6_MASK                      0x10u
+#define AIPS_PACRL_TP6_SHIFT                     4
+#define AIPS_PACRL_TP6_WIDTH                     1
+#define AIPS_PACRL_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP6_SHIFT))&AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_WP6_MASK                      0x20u
+#define AIPS_PACRL_WP6_SHIFT                     5
+#define AIPS_PACRL_WP6_WIDTH                     1
+#define AIPS_PACRL_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP6_SHIFT))&AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_SP6_MASK                      0x40u
+#define AIPS_PACRL_SP6_SHIFT                     6
+#define AIPS_PACRL_SP6_WIDTH                     1
+#define AIPS_PACRL_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP6_SHIFT))&AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_TP5_MASK                      0x100u
+#define AIPS_PACRL_TP5_SHIFT                     8
+#define AIPS_PACRL_TP5_WIDTH                     1
+#define AIPS_PACRL_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP5_SHIFT))&AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_WP5_MASK                      0x200u
+#define AIPS_PACRL_WP5_SHIFT                     9
+#define AIPS_PACRL_WP5_WIDTH                     1
+#define AIPS_PACRL_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP5_SHIFT))&AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_SP5_MASK                      0x400u
+#define AIPS_PACRL_SP5_SHIFT                     10
+#define AIPS_PACRL_SP5_WIDTH                     1
+#define AIPS_PACRL_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP5_SHIFT))&AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_TP4_MASK                      0x1000u
+#define AIPS_PACRL_TP4_SHIFT                     12
+#define AIPS_PACRL_TP4_WIDTH                     1
+#define AIPS_PACRL_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP4_SHIFT))&AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_WP4_MASK                      0x2000u
+#define AIPS_PACRL_WP4_SHIFT                     13
+#define AIPS_PACRL_WP4_WIDTH                     1
+#define AIPS_PACRL_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP4_SHIFT))&AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_SP4_MASK                      0x4000u
+#define AIPS_PACRL_SP4_SHIFT                     14
+#define AIPS_PACRL_SP4_WIDTH                     1
+#define AIPS_PACRL_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP4_SHIFT))&AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_TP3_MASK                      0x10000u
+#define AIPS_PACRL_TP3_SHIFT                     16
+#define AIPS_PACRL_TP3_WIDTH                     1
+#define AIPS_PACRL_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP3_SHIFT))&AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_WP3_MASK                      0x20000u
+#define AIPS_PACRL_WP3_SHIFT                     17
+#define AIPS_PACRL_WP3_WIDTH                     1
+#define AIPS_PACRL_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP3_SHIFT))&AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_SP3_MASK                      0x40000u
+#define AIPS_PACRL_SP3_SHIFT                     18
+#define AIPS_PACRL_SP3_WIDTH                     1
+#define AIPS_PACRL_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP3_SHIFT))&AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_TP2_MASK                      0x100000u
+#define AIPS_PACRL_TP2_SHIFT                     20
+#define AIPS_PACRL_TP2_WIDTH                     1
+#define AIPS_PACRL_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP2_SHIFT))&AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_WP2_MASK                      0x200000u
+#define AIPS_PACRL_WP2_SHIFT                     21
+#define AIPS_PACRL_WP2_WIDTH                     1
+#define AIPS_PACRL_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP2_SHIFT))&AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_SP2_MASK                      0x400000u
+#define AIPS_PACRL_SP2_SHIFT                     22
+#define AIPS_PACRL_SP2_WIDTH                     1
+#define AIPS_PACRL_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP2_SHIFT))&AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_TP1_MASK                      0x1000000u
+#define AIPS_PACRL_TP1_SHIFT                     24
+#define AIPS_PACRL_TP1_WIDTH                     1
+#define AIPS_PACRL_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP1_SHIFT))&AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_WP1_MASK                      0x2000000u
+#define AIPS_PACRL_WP1_SHIFT                     25
+#define AIPS_PACRL_WP1_WIDTH                     1
+#define AIPS_PACRL_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP1_SHIFT))&AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_SP1_MASK                      0x4000000u
+#define AIPS_PACRL_SP1_SHIFT                     26
+#define AIPS_PACRL_SP1_WIDTH                     1
+#define AIPS_PACRL_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP1_SHIFT))&AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_TP0_MASK                      0x10000000u
+#define AIPS_PACRL_TP0_SHIFT                     28
+#define AIPS_PACRL_TP0_WIDTH                     1
+#define AIPS_PACRL_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP0_SHIFT))&AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_WP0_MASK                      0x20000000u
+#define AIPS_PACRL_WP0_SHIFT                     29
+#define AIPS_PACRL_WP0_WIDTH                     1
+#define AIPS_PACRL_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP0_SHIFT))&AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_SP0_MASK                      0x40000000u
+#define AIPS_PACRL_SP0_SHIFT                     30
+#define AIPS_PACRL_SP0_WIDTH                     1
+#define AIPS_PACRL_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP0_SHIFT))&AIPS_PACRL_SP0_MASK)
+/* PACRM Bit Fields */
+#define AIPS_PACRM_TP7_MASK                      0x1u
+#define AIPS_PACRM_TP7_SHIFT                     0
+#define AIPS_PACRM_TP7_WIDTH                     1
+#define AIPS_PACRM_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP7_SHIFT))&AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_WP7_MASK                      0x2u
+#define AIPS_PACRM_WP7_SHIFT                     1
+#define AIPS_PACRM_WP7_WIDTH                     1
+#define AIPS_PACRM_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP7_SHIFT))&AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_SP7_MASK                      0x4u
+#define AIPS_PACRM_SP7_SHIFT                     2
+#define AIPS_PACRM_SP7_WIDTH                     1
+#define AIPS_PACRM_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP7_SHIFT))&AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_TP6_MASK                      0x10u
+#define AIPS_PACRM_TP6_SHIFT                     4
+#define AIPS_PACRM_TP6_WIDTH                     1
+#define AIPS_PACRM_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP6_SHIFT))&AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_WP6_MASK                      0x20u
+#define AIPS_PACRM_WP6_SHIFT                     5
+#define AIPS_PACRM_WP6_WIDTH                     1
+#define AIPS_PACRM_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP6_SHIFT))&AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_SP6_MASK                      0x40u
+#define AIPS_PACRM_SP6_SHIFT                     6
+#define AIPS_PACRM_SP6_WIDTH                     1
+#define AIPS_PACRM_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP6_SHIFT))&AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_TP5_MASK                      0x100u
+#define AIPS_PACRM_TP5_SHIFT                     8
+#define AIPS_PACRM_TP5_WIDTH                     1
+#define AIPS_PACRM_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP5_SHIFT))&AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_WP5_MASK                      0x200u
+#define AIPS_PACRM_WP5_SHIFT                     9
+#define AIPS_PACRM_WP5_WIDTH                     1
+#define AIPS_PACRM_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP5_SHIFT))&AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_SP5_MASK                      0x400u
+#define AIPS_PACRM_SP5_SHIFT                     10
+#define AIPS_PACRM_SP5_WIDTH                     1
+#define AIPS_PACRM_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP5_SHIFT))&AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_TP4_MASK                      0x1000u
+#define AIPS_PACRM_TP4_SHIFT                     12
+#define AIPS_PACRM_TP4_WIDTH                     1
+#define AIPS_PACRM_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP4_SHIFT))&AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_WP4_MASK                      0x2000u
+#define AIPS_PACRM_WP4_SHIFT                     13
+#define AIPS_PACRM_WP4_WIDTH                     1
+#define AIPS_PACRM_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP4_SHIFT))&AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_SP4_MASK                      0x4000u
+#define AIPS_PACRM_SP4_SHIFT                     14
+#define AIPS_PACRM_SP4_WIDTH                     1
+#define AIPS_PACRM_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP4_SHIFT))&AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_TP3_MASK                      0x10000u
+#define AIPS_PACRM_TP3_SHIFT                     16
+#define AIPS_PACRM_TP3_WIDTH                     1
+#define AIPS_PACRM_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP3_SHIFT))&AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_WP3_MASK                      0x20000u
+#define AIPS_PACRM_WP3_SHIFT                     17
+#define AIPS_PACRM_WP3_WIDTH                     1
+#define AIPS_PACRM_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP3_SHIFT))&AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_SP3_MASK                      0x40000u
+#define AIPS_PACRM_SP3_SHIFT                     18
+#define AIPS_PACRM_SP3_WIDTH                     1
+#define AIPS_PACRM_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP3_SHIFT))&AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_TP2_MASK                      0x100000u
+#define AIPS_PACRM_TP2_SHIFT                     20
+#define AIPS_PACRM_TP2_WIDTH                     1
+#define AIPS_PACRM_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP2_SHIFT))&AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_WP2_MASK                      0x200000u
+#define AIPS_PACRM_WP2_SHIFT                     21
+#define AIPS_PACRM_WP2_WIDTH                     1
+#define AIPS_PACRM_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP2_SHIFT))&AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_SP2_MASK                      0x400000u
+#define AIPS_PACRM_SP2_SHIFT                     22
+#define AIPS_PACRM_SP2_WIDTH                     1
+#define AIPS_PACRM_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP2_SHIFT))&AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_TP1_MASK                      0x1000000u
+#define AIPS_PACRM_TP1_SHIFT                     24
+#define AIPS_PACRM_TP1_WIDTH                     1
+#define AIPS_PACRM_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP1_SHIFT))&AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_WP1_MASK                      0x2000000u
+#define AIPS_PACRM_WP1_SHIFT                     25
+#define AIPS_PACRM_WP1_WIDTH                     1
+#define AIPS_PACRM_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP1_SHIFT))&AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_SP1_MASK                      0x4000000u
+#define AIPS_PACRM_SP1_SHIFT                     26
+#define AIPS_PACRM_SP1_WIDTH                     1
+#define AIPS_PACRM_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP1_SHIFT))&AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_TP0_MASK                      0x10000000u
+#define AIPS_PACRM_TP0_SHIFT                     28
+#define AIPS_PACRM_TP0_WIDTH                     1
+#define AIPS_PACRM_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP0_SHIFT))&AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_WP0_MASK                      0x20000000u
+#define AIPS_PACRM_WP0_SHIFT                     29
+#define AIPS_PACRM_WP0_WIDTH                     1
+#define AIPS_PACRM_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP0_SHIFT))&AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_SP0_MASK                      0x40000000u
+#define AIPS_PACRM_SP0_SHIFT                     30
+#define AIPS_PACRM_SP0_WIDTH                     1
+#define AIPS_PACRM_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP0_SHIFT))&AIPS_PACRM_SP0_MASK)
+/* PACRN Bit Fields */
+#define AIPS_PACRN_TP7_MASK                      0x1u
+#define AIPS_PACRN_TP7_SHIFT                     0
+#define AIPS_PACRN_TP7_WIDTH                     1
+#define AIPS_PACRN_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP7_SHIFT))&AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_WP7_MASK                      0x2u
+#define AIPS_PACRN_WP7_SHIFT                     1
+#define AIPS_PACRN_WP7_WIDTH                     1
+#define AIPS_PACRN_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP7_SHIFT))&AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_SP7_MASK                      0x4u
+#define AIPS_PACRN_SP7_SHIFT                     2
+#define AIPS_PACRN_SP7_WIDTH                     1
+#define AIPS_PACRN_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP7_SHIFT))&AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_TP6_MASK                      0x10u
+#define AIPS_PACRN_TP6_SHIFT                     4
+#define AIPS_PACRN_TP6_WIDTH                     1
+#define AIPS_PACRN_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP6_SHIFT))&AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_WP6_MASK                      0x20u
+#define AIPS_PACRN_WP6_SHIFT                     5
+#define AIPS_PACRN_WP6_WIDTH                     1
+#define AIPS_PACRN_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP6_SHIFT))&AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_SP6_MASK                      0x40u
+#define AIPS_PACRN_SP6_SHIFT                     6
+#define AIPS_PACRN_SP6_WIDTH                     1
+#define AIPS_PACRN_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP6_SHIFT))&AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_TP5_MASK                      0x100u
+#define AIPS_PACRN_TP5_SHIFT                     8
+#define AIPS_PACRN_TP5_WIDTH                     1
+#define AIPS_PACRN_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP5_SHIFT))&AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_WP5_MASK                      0x200u
+#define AIPS_PACRN_WP5_SHIFT                     9
+#define AIPS_PACRN_WP5_WIDTH                     1
+#define AIPS_PACRN_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP5_SHIFT))&AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_SP5_MASK                      0x400u
+#define AIPS_PACRN_SP5_SHIFT                     10
+#define AIPS_PACRN_SP5_WIDTH                     1
+#define AIPS_PACRN_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP5_SHIFT))&AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_TP4_MASK                      0x1000u
+#define AIPS_PACRN_TP4_SHIFT                     12
+#define AIPS_PACRN_TP4_WIDTH                     1
+#define AIPS_PACRN_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP4_SHIFT))&AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_WP4_MASK                      0x2000u
+#define AIPS_PACRN_WP4_SHIFT                     13
+#define AIPS_PACRN_WP4_WIDTH                     1
+#define AIPS_PACRN_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP4_SHIFT))&AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_SP4_MASK                      0x4000u
+#define AIPS_PACRN_SP4_SHIFT                     14
+#define AIPS_PACRN_SP4_WIDTH                     1
+#define AIPS_PACRN_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP4_SHIFT))&AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_TP3_MASK                      0x10000u
+#define AIPS_PACRN_TP3_SHIFT                     16
+#define AIPS_PACRN_TP3_WIDTH                     1
+#define AIPS_PACRN_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP3_SHIFT))&AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_WP3_MASK                      0x20000u
+#define AIPS_PACRN_WP3_SHIFT                     17
+#define AIPS_PACRN_WP3_WIDTH                     1
+#define AIPS_PACRN_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP3_SHIFT))&AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_SP3_MASK                      0x40000u
+#define AIPS_PACRN_SP3_SHIFT                     18
+#define AIPS_PACRN_SP3_WIDTH                     1
+#define AIPS_PACRN_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP3_SHIFT))&AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_TP2_MASK                      0x100000u
+#define AIPS_PACRN_TP2_SHIFT                     20
+#define AIPS_PACRN_TP2_WIDTH                     1
+#define AIPS_PACRN_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP2_SHIFT))&AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_WP2_MASK                      0x200000u
+#define AIPS_PACRN_WP2_SHIFT                     21
+#define AIPS_PACRN_WP2_WIDTH                     1
+#define AIPS_PACRN_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP2_SHIFT))&AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_SP2_MASK                      0x400000u
+#define AIPS_PACRN_SP2_SHIFT                     22
+#define AIPS_PACRN_SP2_WIDTH                     1
+#define AIPS_PACRN_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP2_SHIFT))&AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_TP1_MASK                      0x1000000u
+#define AIPS_PACRN_TP1_SHIFT                     24
+#define AIPS_PACRN_TP1_WIDTH                     1
+#define AIPS_PACRN_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP1_SHIFT))&AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_WP1_MASK                      0x2000000u
+#define AIPS_PACRN_WP1_SHIFT                     25
+#define AIPS_PACRN_WP1_WIDTH                     1
+#define AIPS_PACRN_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP1_SHIFT))&AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_SP1_MASK                      0x4000000u
+#define AIPS_PACRN_SP1_SHIFT                     26
+#define AIPS_PACRN_SP1_WIDTH                     1
+#define AIPS_PACRN_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP1_SHIFT))&AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_TP0_MASK                      0x10000000u
+#define AIPS_PACRN_TP0_SHIFT                     28
+#define AIPS_PACRN_TP0_WIDTH                     1
+#define AIPS_PACRN_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP0_SHIFT))&AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_WP0_MASK                      0x20000000u
+#define AIPS_PACRN_WP0_SHIFT                     29
+#define AIPS_PACRN_WP0_WIDTH                     1
+#define AIPS_PACRN_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP0_SHIFT))&AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_SP0_MASK                      0x40000000u
+#define AIPS_PACRN_SP0_SHIFT                     30
+#define AIPS_PACRN_SP0_WIDTH                     1
+#define AIPS_PACRN_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP0_SHIFT))&AIPS_PACRN_SP0_MASK)
+/* PACRO Bit Fields */
+#define AIPS_PACRO_TP7_MASK                      0x1u
+#define AIPS_PACRO_TP7_SHIFT                     0
+#define AIPS_PACRO_TP7_WIDTH                     1
+#define AIPS_PACRO_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP7_SHIFT))&AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_WP7_MASK                      0x2u
+#define AIPS_PACRO_WP7_SHIFT                     1
+#define AIPS_PACRO_WP7_WIDTH                     1
+#define AIPS_PACRO_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP7_SHIFT))&AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_SP7_MASK                      0x4u
+#define AIPS_PACRO_SP7_SHIFT                     2
+#define AIPS_PACRO_SP7_WIDTH                     1
+#define AIPS_PACRO_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP7_SHIFT))&AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_TP6_MASK                      0x10u
+#define AIPS_PACRO_TP6_SHIFT                     4
+#define AIPS_PACRO_TP6_WIDTH                     1
+#define AIPS_PACRO_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP6_SHIFT))&AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_WP6_MASK                      0x20u
+#define AIPS_PACRO_WP6_SHIFT                     5
+#define AIPS_PACRO_WP6_WIDTH                     1
+#define AIPS_PACRO_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP6_SHIFT))&AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_SP6_MASK                      0x40u
+#define AIPS_PACRO_SP6_SHIFT                     6
+#define AIPS_PACRO_SP6_WIDTH                     1
+#define AIPS_PACRO_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP6_SHIFT))&AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_TP5_MASK                      0x100u
+#define AIPS_PACRO_TP5_SHIFT                     8
+#define AIPS_PACRO_TP5_WIDTH                     1
+#define AIPS_PACRO_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP5_SHIFT))&AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_WP5_MASK                      0x200u
+#define AIPS_PACRO_WP5_SHIFT                     9
+#define AIPS_PACRO_WP5_WIDTH                     1
+#define AIPS_PACRO_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP5_SHIFT))&AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_SP5_MASK                      0x400u
+#define AIPS_PACRO_SP5_SHIFT                     10
+#define AIPS_PACRO_SP5_WIDTH                     1
+#define AIPS_PACRO_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP5_SHIFT))&AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_TP4_MASK                      0x1000u
+#define AIPS_PACRO_TP4_SHIFT                     12
+#define AIPS_PACRO_TP4_WIDTH                     1
+#define AIPS_PACRO_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP4_SHIFT))&AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_WP4_MASK                      0x2000u
+#define AIPS_PACRO_WP4_SHIFT                     13
+#define AIPS_PACRO_WP4_WIDTH                     1
+#define AIPS_PACRO_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP4_SHIFT))&AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_SP4_MASK                      0x4000u
+#define AIPS_PACRO_SP4_SHIFT                     14
+#define AIPS_PACRO_SP4_WIDTH                     1
+#define AIPS_PACRO_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP4_SHIFT))&AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_TP3_MASK                      0x10000u
+#define AIPS_PACRO_TP3_SHIFT                     16
+#define AIPS_PACRO_TP3_WIDTH                     1
+#define AIPS_PACRO_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP3_SHIFT))&AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_WP3_MASK                      0x20000u
+#define AIPS_PACRO_WP3_SHIFT                     17
+#define AIPS_PACRO_WP3_WIDTH                     1
+#define AIPS_PACRO_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP3_SHIFT))&AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_SP3_MASK                      0x40000u
+#define AIPS_PACRO_SP3_SHIFT                     18
+#define AIPS_PACRO_SP3_WIDTH                     1
+#define AIPS_PACRO_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP3_SHIFT))&AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_TP2_MASK                      0x100000u
+#define AIPS_PACRO_TP2_SHIFT                     20
+#define AIPS_PACRO_TP2_WIDTH                     1
+#define AIPS_PACRO_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP2_SHIFT))&AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_WP2_MASK                      0x200000u
+#define AIPS_PACRO_WP2_SHIFT                     21
+#define AIPS_PACRO_WP2_WIDTH                     1
+#define AIPS_PACRO_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP2_SHIFT))&AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_SP2_MASK                      0x400000u
+#define AIPS_PACRO_SP2_SHIFT                     22
+#define AIPS_PACRO_SP2_WIDTH                     1
+#define AIPS_PACRO_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP2_SHIFT))&AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_TP1_MASK                      0x1000000u
+#define AIPS_PACRO_TP1_SHIFT                     24
+#define AIPS_PACRO_TP1_WIDTH                     1
+#define AIPS_PACRO_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP1_SHIFT))&AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_WP1_MASK                      0x2000000u
+#define AIPS_PACRO_WP1_SHIFT                     25
+#define AIPS_PACRO_WP1_WIDTH                     1
+#define AIPS_PACRO_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP1_SHIFT))&AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_SP1_MASK                      0x4000000u
+#define AIPS_PACRO_SP1_SHIFT                     26
+#define AIPS_PACRO_SP1_WIDTH                     1
+#define AIPS_PACRO_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP1_SHIFT))&AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_TP0_MASK                      0x10000000u
+#define AIPS_PACRO_TP0_SHIFT                     28
+#define AIPS_PACRO_TP0_WIDTH                     1
+#define AIPS_PACRO_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP0_SHIFT))&AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_WP0_MASK                      0x20000000u
+#define AIPS_PACRO_WP0_SHIFT                     29
+#define AIPS_PACRO_WP0_WIDTH                     1
+#define AIPS_PACRO_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP0_SHIFT))&AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_SP0_MASK                      0x40000000u
+#define AIPS_PACRO_SP0_SHIFT                     30
+#define AIPS_PACRO_SP0_WIDTH                     1
+#define AIPS_PACRO_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP0_SHIFT))&AIPS_PACRO_SP0_MASK)
+/* PACRP Bit Fields */
+#define AIPS_PACRP_TP7_MASK                      0x1u
+#define AIPS_PACRP_TP7_SHIFT                     0
+#define AIPS_PACRP_TP7_WIDTH                     1
+#define AIPS_PACRP_TP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP7_SHIFT))&AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_WP7_MASK                      0x2u
+#define AIPS_PACRP_WP7_SHIFT                     1
+#define AIPS_PACRP_WP7_WIDTH                     1
+#define AIPS_PACRP_WP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP7_SHIFT))&AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_SP7_MASK                      0x4u
+#define AIPS_PACRP_SP7_SHIFT                     2
+#define AIPS_PACRP_SP7_WIDTH                     1
+#define AIPS_PACRP_SP7(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP7_SHIFT))&AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_TP6_MASK                      0x10u
+#define AIPS_PACRP_TP6_SHIFT                     4
+#define AIPS_PACRP_TP6_WIDTH                     1
+#define AIPS_PACRP_TP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP6_SHIFT))&AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_WP6_MASK                      0x20u
+#define AIPS_PACRP_WP6_SHIFT                     5
+#define AIPS_PACRP_WP6_WIDTH                     1
+#define AIPS_PACRP_WP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP6_SHIFT))&AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_SP6_MASK                      0x40u
+#define AIPS_PACRP_SP6_SHIFT                     6
+#define AIPS_PACRP_SP6_WIDTH                     1
+#define AIPS_PACRP_SP6(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP6_SHIFT))&AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_TP5_MASK                      0x100u
+#define AIPS_PACRP_TP5_SHIFT                     8
+#define AIPS_PACRP_TP5_WIDTH                     1
+#define AIPS_PACRP_TP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP5_SHIFT))&AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_WP5_MASK                      0x200u
+#define AIPS_PACRP_WP5_SHIFT                     9
+#define AIPS_PACRP_WP5_WIDTH                     1
+#define AIPS_PACRP_WP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP5_SHIFT))&AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_SP5_MASK                      0x400u
+#define AIPS_PACRP_SP5_SHIFT                     10
+#define AIPS_PACRP_SP5_WIDTH                     1
+#define AIPS_PACRP_SP5(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP5_SHIFT))&AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_TP4_MASK                      0x1000u
+#define AIPS_PACRP_TP4_SHIFT                     12
+#define AIPS_PACRP_TP4_WIDTH                     1
+#define AIPS_PACRP_TP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP4_SHIFT))&AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_WP4_MASK                      0x2000u
+#define AIPS_PACRP_WP4_SHIFT                     13
+#define AIPS_PACRP_WP4_WIDTH                     1
+#define AIPS_PACRP_WP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP4_SHIFT))&AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_SP4_MASK                      0x4000u
+#define AIPS_PACRP_SP4_SHIFT                     14
+#define AIPS_PACRP_SP4_WIDTH                     1
+#define AIPS_PACRP_SP4(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP4_SHIFT))&AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_TP3_MASK                      0x10000u
+#define AIPS_PACRP_TP3_SHIFT                     16
+#define AIPS_PACRP_TP3_WIDTH                     1
+#define AIPS_PACRP_TP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP3_SHIFT))&AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_WP3_MASK                      0x20000u
+#define AIPS_PACRP_WP3_SHIFT                     17
+#define AIPS_PACRP_WP3_WIDTH                     1
+#define AIPS_PACRP_WP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP3_SHIFT))&AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_SP3_MASK                      0x40000u
+#define AIPS_PACRP_SP3_SHIFT                     18
+#define AIPS_PACRP_SP3_WIDTH                     1
+#define AIPS_PACRP_SP3(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP3_SHIFT))&AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_TP2_MASK                      0x100000u
+#define AIPS_PACRP_TP2_SHIFT                     20
+#define AIPS_PACRP_TP2_WIDTH                     1
+#define AIPS_PACRP_TP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP2_SHIFT))&AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_WP2_MASK                      0x200000u
+#define AIPS_PACRP_WP2_SHIFT                     21
+#define AIPS_PACRP_WP2_WIDTH                     1
+#define AIPS_PACRP_WP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP2_SHIFT))&AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_SP2_MASK                      0x400000u
+#define AIPS_PACRP_SP2_SHIFT                     22
+#define AIPS_PACRP_SP2_WIDTH                     1
+#define AIPS_PACRP_SP2(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP2_SHIFT))&AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_TP1_MASK                      0x1000000u
+#define AIPS_PACRP_TP1_SHIFT                     24
+#define AIPS_PACRP_TP1_WIDTH                     1
+#define AIPS_PACRP_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP1_SHIFT))&AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_WP1_MASK                      0x2000000u
+#define AIPS_PACRP_WP1_SHIFT                     25
+#define AIPS_PACRP_WP1_WIDTH                     1
+#define AIPS_PACRP_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP1_SHIFT))&AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_SP1_MASK                      0x4000000u
+#define AIPS_PACRP_SP1_SHIFT                     26
+#define AIPS_PACRP_SP1_WIDTH                     1
+#define AIPS_PACRP_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP1_SHIFT))&AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_TP0_MASK                      0x10000000u
+#define AIPS_PACRP_TP0_SHIFT                     28
+#define AIPS_PACRP_TP0_WIDTH                     1
+#define AIPS_PACRP_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP0_SHIFT))&AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_WP0_MASK                      0x20000000u
+#define AIPS_PACRP_WP0_SHIFT                     29
+#define AIPS_PACRP_WP0_WIDTH                     1
+#define AIPS_PACRP_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP0_SHIFT))&AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_SP0_MASK                      0x40000000u
+#define AIPS_PACRP_SP0_SHIFT                     30
+#define AIPS_PACRP_SP0_WIDTH                     1
+#define AIPS_PACRP_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP0_SHIFT))&AIPS_PACRP_SP0_MASK)
+/* PACRU Bit Fields */
+#define AIPS_PACRU_TP1_MASK                      0x1000000u
+#define AIPS_PACRU_TP1_SHIFT                     24
+#define AIPS_PACRU_TP1_WIDTH                     1
+#define AIPS_PACRU_TP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_TP1_SHIFT))&AIPS_PACRU_TP1_MASK)
+#define AIPS_PACRU_WP1_MASK                      0x2000000u
+#define AIPS_PACRU_WP1_SHIFT                     25
+#define AIPS_PACRU_WP1_WIDTH                     1
+#define AIPS_PACRU_WP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_WP1_SHIFT))&AIPS_PACRU_WP1_MASK)
+#define AIPS_PACRU_SP1_MASK                      0x4000000u
+#define AIPS_PACRU_SP1_SHIFT                     26
+#define AIPS_PACRU_SP1_WIDTH                     1
+#define AIPS_PACRU_SP1(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_SP1_SHIFT))&AIPS_PACRU_SP1_MASK)
+#define AIPS_PACRU_TP0_MASK                      0x10000000u
+#define AIPS_PACRU_TP0_SHIFT                     28
+#define AIPS_PACRU_TP0_WIDTH                     1
+#define AIPS_PACRU_TP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_TP0_SHIFT))&AIPS_PACRU_TP0_MASK)
+#define AIPS_PACRU_WP0_MASK                      0x20000000u
+#define AIPS_PACRU_WP0_SHIFT                     29
+#define AIPS_PACRU_WP0_WIDTH                     1
+#define AIPS_PACRU_WP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_WP0_SHIFT))&AIPS_PACRU_WP0_MASK)
+#define AIPS_PACRU_SP0_MASK                      0x40000000u
+#define AIPS_PACRU_SP0_SHIFT                     30
+#define AIPS_PACRU_SP0_WIDTH                     1
+#define AIPS_PACRU_SP0(x)                        (((uint32_t)(((uint32_t)(x))<<AIPS_PACRU_SP0_SHIFT))&AIPS_PACRU_SP0_MASK)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base address */
+#define AIPS0_BASE                               (0x40000000u)
+/** Peripheral AIPS0 base pointer */
+#define AIPS0                                    ((AIPS_Type *)AIPS0_BASE)
+#define AIPS0_BASE_PTR                           (AIPS0)
+/** Peripheral AIPS1 base address */
+#define AIPS1_BASE                               (0x40080000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1                                    ((AIPS_Type *)AIPS1_BASE)
+#define AIPS1_BASE_PTR                           (AIPS1)
+/** Array initializer of AIPS peripheral base addresses */
+#define AIPS_BASE_ADDRS                          { AIPS0_BASE, AIPS1_BASE }
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS                           { AIPS0, AIPS1 }
+
+/* ----------------------------------------------------------------------------
+   -- AIPS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register instance definitions */
+/* AIPS0 */
+#define AIPS0_MPRA                               AIPS_MPRA_REG(AIPS0)
+#define AIPS0_PACRA                              AIPS_PACRA_REG(AIPS0)
+#define AIPS0_PACRB                              AIPS_PACRB_REG(AIPS0)
+#define AIPS0_PACRC                              AIPS_PACRC_REG(AIPS0)
+#define AIPS0_PACRD                              AIPS_PACRD_REG(AIPS0)
+#define AIPS0_PACRE                              AIPS_PACRE_REG(AIPS0)
+#define AIPS0_PACRF                              AIPS_PACRF_REG(AIPS0)
+#define AIPS0_PACRG                              AIPS_PACRG_REG(AIPS0)
+#define AIPS0_PACRH                              AIPS_PACRH_REG(AIPS0)
+#define AIPS0_PACRI                              AIPS_PACRI_REG(AIPS0)
+#define AIPS0_PACRJ                              AIPS_PACRJ_REG(AIPS0)
+#define AIPS0_PACRK                              AIPS_PACRK_REG(AIPS0)
+#define AIPS0_PACRL                              AIPS_PACRL_REG(AIPS0)
+#define AIPS0_PACRM                              AIPS_PACRM_REG(AIPS0)
+#define AIPS0_PACRN                              AIPS_PACRN_REG(AIPS0)
+#define AIPS0_PACRO                              AIPS_PACRO_REG(AIPS0)
+#define AIPS0_PACRP                              AIPS_PACRP_REG(AIPS0)
+#define AIPS0_PACRU                              AIPS_PACRU_REG(AIPS0)
+/* AIPS1 */
+#define AIPS1_MPRA                               AIPS_MPRA_REG(AIPS1)
+#define AIPS1_PACRA                              AIPS_PACRA_REG(AIPS1)
+#define AIPS1_PACRB                              AIPS_PACRB_REG(AIPS1)
+#define AIPS1_PACRC                              AIPS_PACRC_REG(AIPS1)
+#define AIPS1_PACRD                              AIPS_PACRD_REG(AIPS1)
+#define AIPS1_PACRE                              AIPS_PACRE_REG(AIPS1)
+#define AIPS1_PACRF                              AIPS_PACRF_REG(AIPS1)
+#define AIPS1_PACRG                              AIPS_PACRG_REG(AIPS1)
+#define AIPS1_PACRH                              AIPS_PACRH_REG(AIPS1)
+#define AIPS1_PACRI                              AIPS_PACRI_REG(AIPS1)
+#define AIPS1_PACRJ                              AIPS_PACRJ_REG(AIPS1)
+#define AIPS1_PACRK                              AIPS_PACRK_REG(AIPS1)
+#define AIPS1_PACRL                              AIPS_PACRL_REG(AIPS1)
+#define AIPS1_PACRM                              AIPS_PACRM_REG(AIPS1)
+#define AIPS1_PACRN                              AIPS_PACRN_REG(AIPS1)
+#define AIPS1_PACRO                              AIPS_PACRO_REG(AIPS1)
+#define AIPS1_PACRP                              AIPS_PACRP_REG(AIPS1)
+#define AIPS1_PACRU                              AIPS_PACRU_REG(AIPS1)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t PRS;                               /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CRS;                               /**< Control Register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_1[236];
+  } SLAVE[5];
+       uint8_t RESERVED_0[768];
+  __IO uint32_t MGPCR0;                            /**< Master General Purpose Control Register, offset: 0x800 */
+       uint8_t RESERVED_1[252];
+  __IO uint32_t MGPCR1;                            /**< Master General Purpose Control Register, offset: 0x900 */
+       uint8_t RESERVED_2[252];
+  __IO uint32_t MGPCR2;                            /**< Master General Purpose Control Register, offset: 0xA00 */
+       uint8_t RESERVED_3[252];
+  __IO uint32_t MGPCR3;                            /**< Master General Purpose Control Register, offset: 0xB00 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t MGPCR4;                            /**< Master General Purpose Control Register, offset: 0xC00 */
+       uint8_t RESERVED_5[252];
+  __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
+} AXBS_Type, *AXBS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register accessors */
+#define AXBS_PRS_REG(base,index)                 ((base)->SLAVE[index].PRS)
+#define AXBS_PRS_COUNT                           5
+#define AXBS_CRS_REG(base,index)                 ((base)->SLAVE[index].CRS)
+#define AXBS_CRS_COUNT                           5
+#define AXBS_MGPCR0_REG(base)                    ((base)->MGPCR0)
+#define AXBS_MGPCR1_REG(base)                    ((base)->MGPCR1)
+#define AXBS_MGPCR2_REG(base)                    ((base)->MGPCR2)
+#define AXBS_MGPCR3_REG(base)                    ((base)->MGPCR3)
+#define AXBS_MGPCR4_REG(base)                    ((base)->MGPCR4)
+#define AXBS_MGPCR5_REG(base)                    ((base)->MGPCR5)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/* PRS Bit Fields */
+#define AXBS_PRS_M0_MASK                         0x7u
+#define AXBS_PRS_M0_SHIFT                        0
+#define AXBS_PRS_M0_WIDTH                        3
+#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK                         0x70u
+#define AXBS_PRS_M1_SHIFT                        4
+#define AXBS_PRS_M1_WIDTH                        3
+#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK                         0x700u
+#define AXBS_PRS_M2_SHIFT                        8
+#define AXBS_PRS_M2_WIDTH                        3
+#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK                         0x7000u
+#define AXBS_PRS_M3_SHIFT                        12
+#define AXBS_PRS_M3_WIDTH                        3
+#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK                         0x70000u
+#define AXBS_PRS_M4_SHIFT                        16
+#define AXBS_PRS_M4_WIDTH                        3
+#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK                         0x700000u
+#define AXBS_PRS_M5_SHIFT                        20
+#define AXBS_PRS_M5_WIDTH                        3
+#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
+/* CRS Bit Fields */
+#define AXBS_CRS_PARK_MASK                       0x7u
+#define AXBS_CRS_PARK_SHIFT                      0
+#define AXBS_CRS_PARK_WIDTH                      3
+#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK                       0x30u
+#define AXBS_CRS_PCTL_SHIFT                      4
+#define AXBS_CRS_PCTL_WIDTH                      2
+#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK                        0x300u
+#define AXBS_CRS_ARB_SHIFT                       8
+#define AXBS_CRS_ARB_WIDTH                       2
+#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK                        0x40000000u
+#define AXBS_CRS_HLP_SHIFT                       30
+#define AXBS_CRS_HLP_WIDTH                       1
+#define AXBS_CRS_HLP(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_HLP_SHIFT))&AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_RO_MASK                         0x80000000u
+#define AXBS_CRS_RO_SHIFT                        31
+#define AXBS_CRS_RO_WIDTH                        1
+#define AXBS_CRS_RO(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_RO_SHIFT))&AXBS_CRS_RO_MASK)
+/* MGPCR0 Bit Fields */
+#define AXBS_MGPCR0_AULB_MASK                    0x7u
+#define AXBS_MGPCR0_AULB_SHIFT                   0
+#define AXBS_MGPCR0_AULB_WIDTH                   3
+#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
+/* MGPCR1 Bit Fields */
+#define AXBS_MGPCR1_AULB_MASK                    0x7u
+#define AXBS_MGPCR1_AULB_SHIFT                   0
+#define AXBS_MGPCR1_AULB_WIDTH                   3
+#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
+/* MGPCR2 Bit Fields */
+#define AXBS_MGPCR2_AULB_MASK                    0x7u
+#define AXBS_MGPCR2_AULB_SHIFT                   0
+#define AXBS_MGPCR2_AULB_WIDTH                   3
+#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
+/* MGPCR3 Bit Fields */
+#define AXBS_MGPCR3_AULB_MASK                    0x7u
+#define AXBS_MGPCR3_AULB_SHIFT                   0
+#define AXBS_MGPCR3_AULB_WIDTH                   3
+#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
+/* MGPCR4 Bit Fields */
+#define AXBS_MGPCR4_AULB_MASK                    0x7u
+#define AXBS_MGPCR4_AULB_SHIFT                   0
+#define AXBS_MGPCR4_AULB_WIDTH                   3
+#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
+/* MGPCR5 Bit Fields */
+#define AXBS_MGPCR5_AULB_MASK                    0x7u
+#define AXBS_MGPCR5_AULB_SHIFT                   0
+#define AXBS_MGPCR5_AULB_WIDTH                   3
+#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS base address */
+#define AXBS_BASE                                (0x40004000u)
+/** Peripheral AXBS base pointer */
+#define AXBS                                     ((AXBS_Type *)AXBS_BASE)
+#define AXBS_BASE_PTR                            (AXBS)
+/** Array initializer of AXBS peripheral base addresses */
+#define AXBS_BASE_ADDRS                          { AXBS_BASE }
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASE_PTRS                           { AXBS }
+
+/* ----------------------------------------------------------------------------
+   -- AXBS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register instance definitions */
+/* AXBS */
+#define AXBS_PRS0                                AXBS_PRS_REG(AXBS,0)
+#define AXBS_CRS0                                AXBS_CRS_REG(AXBS,0)
+#define AXBS_PRS1                                AXBS_PRS_REG(AXBS,1)
+#define AXBS_CRS1                                AXBS_CRS_REG(AXBS,1)
+#define AXBS_PRS2                                AXBS_PRS_REG(AXBS,2)
+#define AXBS_CRS2                                AXBS_CRS_REG(AXBS,2)
+#define AXBS_PRS3                                AXBS_PRS_REG(AXBS,3)
+#define AXBS_CRS3                                AXBS_CRS_REG(AXBS,3)
+#define AXBS_PRS4                                AXBS_PRS_REG(AXBS,4)
+#define AXBS_CRS4                                AXBS_CRS_REG(AXBS,4)
+#define AXBS_MGPCR0                              AXBS_MGPCR0_REG(AXBS)
+#define AXBS_MGPCR1                              AXBS_MGPCR1_REG(AXBS)
+#define AXBS_MGPCR2                              AXBS_MGPCR2_REG(AXBS)
+#define AXBS_MGPCR3                              AXBS_MGPCR3_REG(AXBS)
+#define AXBS_MGPCR4                              AXBS_MGPCR4_REG(AXBS)
+#define AXBS_MGPCR5                              AXBS_MGPCR5_REG(AXBS)
+
+/* AXBS - Register array accessors */
+#define AXBS_PRS(index)                          AXBS_PRS_REG(AXBS,index)
+#define AXBS_CRS(index)                          AXBS_CRS_REG(AXBS,index)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
+  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
+  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
+  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
+  __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
+  __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
+  __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
+  __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
+  __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
+       uint8_t RESERVED_4[48];
+  struct {                                         /* offset: 0x80, array step: 0x10 */
+    __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+    __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+    __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+    __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+  } MB[16];
+       uint8_t RESERVED_5[1792];
+  __IO uint32_t RXIMR[16];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_Type, *CAN_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register accessors */
+#define CAN_MCR_REG(base)                        ((base)->MCR)
+#define CAN_CTRL1_REG(base)                      ((base)->CTRL1)
+#define CAN_TIMER_REG(base)                      ((base)->TIMER)
+#define CAN_RXMGMASK_REG(base)                   ((base)->RXMGMASK)
+#define CAN_RX14MASK_REG(base)                   ((base)->RX14MASK)
+#define CAN_RX15MASK_REG(base)                   ((base)->RX15MASK)
+#define CAN_ECR_REG(base)                        ((base)->ECR)
+#define CAN_ESR1_REG(base)                       ((base)->ESR1)
+#define CAN_IMASK1_REG(base)                     ((base)->IMASK1)
+#define CAN_IFLAG1_REG(base)                     ((base)->IFLAG1)
+#define CAN_CTRL2_REG(base)                      ((base)->CTRL2)
+#define CAN_ESR2_REG(base)                       ((base)->ESR2)
+#define CAN_CRCR_REG(base)                       ((base)->CRCR)
+#define CAN_RXFGMASK_REG(base)                   ((base)->RXFGMASK)
+#define CAN_RXFIR_REG(base)                      ((base)->RXFIR)
+#define CAN_CS_REG(base,index)                   ((base)->MB[index].CS)
+#define CAN_CS_COUNT                             16
+#define CAN_ID_REG(base,index)                   ((base)->MB[index].ID)
+#define CAN_ID_COUNT                             16
+#define CAN_WORD0_REG(base,index)                ((base)->MB[index].WORD0)
+#define CAN_WORD0_COUNT                          16
+#define CAN_WORD1_REG(base,index)                ((base)->MB[index].WORD1)
+#define CAN_WORD1_COUNT                          16
+#define CAN_RXIMR_REG(base,index)                ((base)->RXIMR[index])
+#define CAN_RXIMR_COUNT                          16
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define CAN_MCR_MAXMB_MASK                       0x7Fu
+#define CAN_MCR_MAXMB_SHIFT                      0
+#define CAN_MCR_MAXMB_WIDTH                      7
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK                        0x300u
+#define CAN_MCR_IDAM_SHIFT                       8
+#define CAN_MCR_IDAM_WIDTH                       2
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK                         0x1000u
+#define CAN_MCR_AEN_SHIFT                        12
+#define CAN_MCR_AEN_WIDTH                        1
+#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK                     0x2000u
+#define CAN_MCR_LPRIOEN_SHIFT                    13
+#define CAN_MCR_LPRIOEN_WIDTH                    1
+#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_IRMQ_MASK                        0x10000u
+#define CAN_MCR_IRMQ_SHIFT                       16
+#define CAN_MCR_IRMQ_WIDTH                       1
+#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK                      0x20000u
+#define CAN_MCR_SRXDIS_SHIFT                     17
+#define CAN_MCR_SRXDIS_WIDTH                     1
+#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_WAKSRC_MASK                      0x80000u
+#define CAN_MCR_WAKSRC_SHIFT                     19
+#define CAN_MCR_WAKSRC_WIDTH                     1
+#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKSRC_SHIFT))&CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_LPMACK_MASK                      0x100000u
+#define CAN_MCR_LPMACK_SHIFT                     20
+#define CAN_MCR_LPMACK_WIDTH                     1
+#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK                       0x200000u
+#define CAN_MCR_WRNEN_SHIFT                      21
+#define CAN_MCR_WRNEN_WIDTH                      1
+#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SLFWAK_MASK                      0x400000u
+#define CAN_MCR_SLFWAK_SHIFT                     22
+#define CAN_MCR_SLFWAK_WIDTH                     1
+#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SLFWAK_SHIFT))&CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SUPV_MASK                        0x800000u
+#define CAN_MCR_SUPV_SHIFT                       23
+#define CAN_MCR_SUPV_WIDTH                       1
+#define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
+#define CAN_MCR_FRZACK_MASK                      0x1000000u
+#define CAN_MCR_FRZACK_SHIFT                     24
+#define CAN_MCR_FRZACK_WIDTH                     1
+#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK                     0x2000000u
+#define CAN_MCR_SOFTRST_SHIFT                    25
+#define CAN_MCR_SOFTRST_WIDTH                    1
+#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_WAKMSK_MASK                      0x4000000u
+#define CAN_MCR_WAKMSK_SHIFT                     26
+#define CAN_MCR_WAKMSK_WIDTH                     1
+#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKMSK_SHIFT))&CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_NOTRDY_MASK                      0x8000000u
+#define CAN_MCR_NOTRDY_SHIFT                     27
+#define CAN_MCR_NOTRDY_WIDTH                     1
+#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK                        0x10000000u
+#define CAN_MCR_HALT_SHIFT                       28
+#define CAN_MCR_HALT_WIDTH                       1
+#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK                        0x20000000u
+#define CAN_MCR_RFEN_SHIFT                       29
+#define CAN_MCR_RFEN_WIDTH                       1
+#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK                         0x40000000u
+#define CAN_MCR_FRZ_SHIFT                        30
+#define CAN_MCR_FRZ_WIDTH                        1
+#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK                        0x80000000u
+#define CAN_MCR_MDIS_SHIFT                       31
+#define CAN_MCR_MDIS_WIDTH                       1
+#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
+/* CTRL1 Bit Fields */
+#define CAN_CTRL1_PROPSEG_MASK                   0x7u
+#define CAN_CTRL1_PROPSEG_SHIFT                  0
+#define CAN_CTRL1_PROPSEG_WIDTH                  3
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK                       0x8u
+#define CAN_CTRL1_LOM_SHIFT                      3
+#define CAN_CTRL1_LOM_WIDTH                      1
+#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK                      0x10u
+#define CAN_CTRL1_LBUF_SHIFT                     4
+#define CAN_CTRL1_LBUF_WIDTH                     1
+#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK                      0x20u
+#define CAN_CTRL1_TSYN_SHIFT                     5
+#define CAN_CTRL1_TSYN_WIDTH                     1
+#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK                   0x40u
+#define CAN_CTRL1_BOFFREC_SHIFT                  6
+#define CAN_CTRL1_BOFFREC_WIDTH                  1
+#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK                       0x80u
+#define CAN_CTRL1_SMP_SHIFT                      7
+#define CAN_CTRL1_SMP_WIDTH                      1
+#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK                   0x400u
+#define CAN_CTRL1_RWRNMSK_SHIFT                  10
+#define CAN_CTRL1_RWRNMSK_WIDTH                  1
+#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK                   0x800u
+#define CAN_CTRL1_TWRNMSK_SHIFT                  11
+#define CAN_CTRL1_TWRNMSK_WIDTH                  1
+#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK                       0x1000u
+#define CAN_CTRL1_LPB_SHIFT                      12
+#define CAN_CTRL1_LPB_WIDTH                      1
+#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_CLKSRC_MASK                    0x2000u
+#define CAN_CTRL1_CLKSRC_SHIFT                   13
+#define CAN_CTRL1_CLKSRC_WIDTH                   1
+#define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_ERRMSK_MASK                    0x4000u
+#define CAN_CTRL1_ERRMSK_SHIFT                   14
+#define CAN_CTRL1_ERRMSK_WIDTH                   1
+#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK                   0x8000u
+#define CAN_CTRL1_BOFFMSK_SHIFT                  15
+#define CAN_CTRL1_BOFFMSK_WIDTH                  1
+#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK                     0x70000u
+#define CAN_CTRL1_PSEG2_SHIFT                    16
+#define CAN_CTRL1_PSEG2_WIDTH                    3
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK                     0x380000u
+#define CAN_CTRL1_PSEG1_SHIFT                    19
+#define CAN_CTRL1_PSEG1_WIDTH                    3
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK                       0xC00000u
+#define CAN_CTRL1_RJW_SHIFT                      22
+#define CAN_CTRL1_RJW_WIDTH                      2
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
+#define CAN_CTRL1_PRESDIV_SHIFT                  24
+#define CAN_CTRL1_PRESDIV_WIDTH                  8
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
+/* TIMER Bit Fields */
+#define CAN_TIMER_TIMER_MASK                     0xFFFFu
+#define CAN_TIMER_TIMER_SHIFT                    0
+#define CAN_TIMER_TIMER_WIDTH                    16
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
+/* RXMGMASK Bit Fields */
+#define CAN_RXMGMASK_MG_MASK                     0xFFFFFFFFu
+#define CAN_RXMGMASK_MG_SHIFT                    0
+#define CAN_RXMGMASK_MG_WIDTH                    32
+#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
+/* RX14MASK Bit Fields */
+#define CAN_RX14MASK_RX14M_MASK                  0xFFFFFFFFu
+#define CAN_RX14MASK_RX14M_SHIFT                 0
+#define CAN_RX14MASK_RX14M_WIDTH                 32
+#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
+/* RX15MASK Bit Fields */
+#define CAN_RX15MASK_RX15M_MASK                  0xFFFFFFFFu
+#define CAN_RX15MASK_RX15M_SHIFT                 0
+#define CAN_RX15MASK_RX15M_WIDTH                 32
+#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
+/* ECR Bit Fields */
+#define CAN_ECR_TXERRCNT_MASK                    0xFFu
+#define CAN_ECR_TXERRCNT_SHIFT                   0
+#define CAN_ECR_TXERRCNT_WIDTH                   8
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK                    0xFF00u
+#define CAN_ECR_RXERRCNT_SHIFT                   8
+#define CAN_ECR_RXERRCNT_WIDTH                   8
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
+/* ESR1 Bit Fields */
+#define CAN_ESR1_WAKINT_MASK                     0x1u
+#define CAN_ESR1_WAKINT_SHIFT                    0
+#define CAN_ESR1_WAKINT_WIDTH                    1
+#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_WAKINT_SHIFT))&CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_ERRINT_MASK                     0x2u
+#define CAN_ESR1_ERRINT_SHIFT                    1
+#define CAN_ESR1_ERRINT_WIDTH                    1
+#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK                    0x4u
+#define CAN_ESR1_BOFFINT_SHIFT                   2
+#define CAN_ESR1_BOFFINT_WIDTH                   1
+#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK                         0x8u
+#define CAN_ESR1_RX_SHIFT                        3
+#define CAN_ESR1_RX_WIDTH                        1
+#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK                    0x30u
+#define CAN_ESR1_FLTCONF_SHIFT                   4
+#define CAN_ESR1_FLTCONF_WIDTH                   2
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK                         0x40u
+#define CAN_ESR1_TX_SHIFT                        6
+#define CAN_ESR1_TX_WIDTH                        1
+#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK                       0x80u
+#define CAN_ESR1_IDLE_SHIFT                      7
+#define CAN_ESR1_IDLE_WIDTH                      1
+#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK                      0x100u
+#define CAN_ESR1_RXWRN_SHIFT                     8
+#define CAN_ESR1_RXWRN_WIDTH                     1
+#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK                      0x200u
+#define CAN_ESR1_TXWRN_SHIFT                     9
+#define CAN_ESR1_TXWRN_WIDTH                     1
+#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK                     0x400u
+#define CAN_ESR1_STFERR_SHIFT                    10
+#define CAN_ESR1_STFERR_WIDTH                    1
+#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK                     0x800u
+#define CAN_ESR1_FRMERR_SHIFT                    11
+#define CAN_ESR1_FRMERR_WIDTH                    1
+#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK                     0x1000u
+#define CAN_ESR1_CRCERR_SHIFT                    12
+#define CAN_ESR1_CRCERR_WIDTH                    1
+#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK                     0x2000u
+#define CAN_ESR1_ACKERR_SHIFT                    13
+#define CAN_ESR1_ACKERR_WIDTH                    1
+#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK                    0x4000u
+#define CAN_ESR1_BIT0ERR_SHIFT                   14
+#define CAN_ESR1_BIT0ERR_WIDTH                   1
+#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK                    0x8000u
+#define CAN_ESR1_BIT1ERR_SHIFT                   15
+#define CAN_ESR1_BIT1ERR_WIDTH                   1
+#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK                    0x10000u
+#define CAN_ESR1_RWRNINT_SHIFT                   16
+#define CAN_ESR1_RWRNINT_WIDTH                   1
+#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK                    0x20000u
+#define CAN_ESR1_TWRNINT_SHIFT                   17
+#define CAN_ESR1_TWRNINT_WIDTH                   1
+#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK                      0x40000u
+#define CAN_ESR1_SYNCH_SHIFT                     18
+#define CAN_ESR1_SYNCH_WIDTH                     1
+#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
+/* IMASK1 Bit Fields */
+#define CAN_IMASK1_BUFLM_MASK                    0xFFFFFFFFu
+#define CAN_IMASK1_BUFLM_SHIFT                   0
+#define CAN_IMASK1_BUFLM_WIDTH                   32
+#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
+/* IFLAG1 Bit Fields */
+#define CAN_IFLAG1_BUF0I_MASK                    0x1u
+#define CAN_IFLAG1_BUF0I_SHIFT                   0
+#define CAN_IFLAG1_BUF0I_WIDTH                   1
+#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF4TO1I_MASK                 0x1Eu
+#define CAN_IFLAG1_BUF4TO1I_SHIFT                1
+#define CAN_IFLAG1_BUF4TO1I_WIDTH                4
+#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK                    0x20u
+#define CAN_IFLAG1_BUF5I_SHIFT                   5
+#define CAN_IFLAG1_BUF5I_WIDTH                   1
+#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK                    0x40u
+#define CAN_IFLAG1_BUF6I_SHIFT                   6
+#define CAN_IFLAG1_BUF6I_WIDTH                   1
+#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK                    0x80u
+#define CAN_IFLAG1_BUF7I_SHIFT                   7
+#define CAN_IFLAG1_BUF7I_WIDTH                   1
+#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK                0xFFFFFF00u
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               8
+#define CAN_IFLAG1_BUF31TO8I_WIDTH               24
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
+/* CTRL2 Bit Fields */
+#define CAN_CTRL2_EACEN_MASK                     0x10000u
+#define CAN_CTRL2_EACEN_SHIFT                    16
+#define CAN_CTRL2_EACEN_WIDTH                    1
+#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK                       0x20000u
+#define CAN_CTRL2_RRS_SHIFT                      17
+#define CAN_CTRL2_RRS_WIDTH                      1
+#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK                       0x40000u
+#define CAN_CTRL2_MRP_SHIFT                      18
+#define CAN_CTRL2_MRP_WIDTH                      1
+#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK                      0xF80000u
+#define CAN_CTRL2_TASD_SHIFT                     19
+#define CAN_CTRL2_TASD_WIDTH                     5
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK                      0xF000000u
+#define CAN_CTRL2_RFFN_SHIFT                     24
+#define CAN_CTRL2_RFFN_WIDTH                     4
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK                    0x10000000u
+#define CAN_CTRL2_WRMFRZ_SHIFT                   28
+#define CAN_CTRL2_WRMFRZ_WIDTH                   1
+#define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_WRMFRZ_SHIFT))&CAN_CTRL2_WRMFRZ_MASK)
+/* ESR2 Bit Fields */
+#define CAN_ESR2_IMB_MASK                        0x2000u
+#define CAN_ESR2_IMB_SHIFT                       13
+#define CAN_ESR2_IMB_WIDTH                       1
+#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK                        0x4000u
+#define CAN_ESR2_VPS_SHIFT                       14
+#define CAN_ESR2_VPS_WIDTH                       1
+#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK                       0x7F0000u
+#define CAN_ESR2_LPTM_SHIFT                      16
+#define CAN_ESR2_LPTM_WIDTH                      7
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
+/* CRCR Bit Fields */
+#define CAN_CRCR_TXCRC_MASK                      0x7FFFu
+#define CAN_CRCR_TXCRC_SHIFT                     0
+#define CAN_CRCR_TXCRC_WIDTH                     15
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK                      0x7F0000u
+#define CAN_CRCR_MBCRC_SHIFT                     16
+#define CAN_CRCR_MBCRC_WIDTH                     7
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
+/* RXFGMASK Bit Fields */
+#define CAN_RXFGMASK_FGM_MASK                    0xFFFFFFFFu
+#define CAN_RXFGMASK_FGM_SHIFT                   0
+#define CAN_RXFGMASK_FGM_WIDTH                   32
+#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
+/* RXFIR Bit Fields */
+#define CAN_RXFIR_IDHIT_MASK                     0x1FFu
+#define CAN_RXFIR_IDHIT_SHIFT                    0
+#define CAN_RXFIR_IDHIT_WIDTH                    9
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
+/* CS Bit Fields */
+#define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
+#define CAN_CS_TIME_STAMP_SHIFT                  0
+#define CAN_CS_TIME_STAMP_WIDTH                  16
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK                          0xF0000u
+#define CAN_CS_DLC_SHIFT                         16
+#define CAN_CS_DLC_WIDTH                         4
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK                          0x100000u
+#define CAN_CS_RTR_SHIFT                         20
+#define CAN_CS_RTR_WIDTH                         1
+#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_RTR_SHIFT))&CAN_CS_RTR_MASK)
+#define CAN_CS_IDE_MASK                          0x200000u
+#define CAN_CS_IDE_SHIFT                         21
+#define CAN_CS_IDE_WIDTH                         1
+#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_IDE_SHIFT))&CAN_CS_IDE_MASK)
+#define CAN_CS_SRR_MASK                          0x400000u
+#define CAN_CS_SRR_SHIFT                         22
+#define CAN_CS_SRR_WIDTH                         1
+#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_SRR_SHIFT))&CAN_CS_SRR_MASK)
+#define CAN_CS_CODE_MASK                         0xF000000u
+#define CAN_CS_CODE_SHIFT                        24
+#define CAN_CS_CODE_WIDTH                        4
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
+/* ID Bit Fields */
+#define CAN_ID_EXT_MASK                          0x3FFFFu
+#define CAN_ID_EXT_SHIFT                         0
+#define CAN_ID_EXT_WIDTH                         18
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK                          0x1FFC0000u
+#define CAN_ID_STD_SHIFT                         18
+#define CAN_ID_STD_WIDTH                         11
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK                         0xE0000000u
+#define CAN_ID_PRIO_SHIFT                        29
+#define CAN_ID_PRIO_WIDTH                        3
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
+/* WORD0 Bit Fields */
+#define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              0
+#define CAN_WORD0_DATA_BYTE_3_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              8
+#define CAN_WORD0_DATA_BYTE_2_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              16
+#define CAN_WORD0_DATA_BYTE_1_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              24
+#define CAN_WORD0_DATA_BYTE_0_WIDTH              8
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
+/* WORD1 Bit Fields */
+#define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              0
+#define CAN_WORD1_DATA_BYTE_7_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              8
+#define CAN_WORD1_DATA_BYTE_6_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              16
+#define CAN_WORD1_DATA_BYTE_5_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              24
+#define CAN_WORD1_DATA_BYTE_4_WIDTH              8
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
+/* RXIMR Bit Fields */
+#define CAN_RXIMR_MI_MASK                        0xFFFFFFFFu
+#define CAN_RXIMR_MI_SHIFT                       0
+#define CAN_RXIMR_MI_WIDTH                       32
+#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+#define CAN0_BASE_PTR                            (CAN0)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS                      { CAN0_Rx_Warning_IRQn }
+#define CAN_Tx_Warning_IRQS                      { CAN0_Tx_Warning_IRQn }
+#define CAN_Wake_Up_IRQS                         { CAN0_Wake_Up_IRQn }
+#define CAN_Error_IRQS                           { CAN0_Error_IRQn }
+#define CAN_Bus_Off_IRQS                         { CAN0_Bus_Off_IRQn }
+#define CAN_ORed_Message_buffer_IRQS             { CAN0_ORed_Message_buffer_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CAN - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
+ * @{
+ */
+
+
+/* CAN - Register instance definitions */
+/* CAN0 */
+#define CAN0_MCR                                 CAN_MCR_REG(CAN0)
+#define CAN0_CTRL1                               CAN_CTRL1_REG(CAN0)
+#define CAN0_TIMER                               CAN_TIMER_REG(CAN0)
+#define CAN0_RXMGMASK                            CAN_RXMGMASK_REG(CAN0)
+#define CAN0_RX14MASK                            CAN_RX14MASK_REG(CAN0)
+#define CAN0_RX15MASK                            CAN_RX15MASK_REG(CAN0)
+#define CAN0_ECR                                 CAN_ECR_REG(CAN0)
+#define CAN0_ESR1                                CAN_ESR1_REG(CAN0)
+#define CAN0_IMASK1                              CAN_IMASK1_REG(CAN0)
+#define CAN0_IFLAG1                              CAN_IFLAG1_REG(CAN0)
+#define CAN0_CTRL2                               CAN_CTRL2_REG(CAN0)
+#define CAN0_ESR2                                CAN_ESR2_REG(CAN0)
+#define CAN0_CRCR                                CAN_CRCR_REG(CAN0)
+#define CAN0_RXFGMASK                            CAN_RXFGMASK_REG(CAN0)
+#define CAN0_RXFIR                               CAN_RXFIR_REG(CAN0)
+#define CAN0_CS0                                 CAN_CS_REG(CAN0,0)
+#define CAN0_ID0                                 CAN_ID_REG(CAN0,0)
+#define CAN0_WORD00                              CAN_WORD0_REG(CAN0,0)
+#define CAN0_WORD10                              CAN_WORD1_REG(CAN0,0)
+#define CAN0_CS1                                 CAN_CS_REG(CAN0,1)
+#define CAN0_ID1                                 CAN_ID_REG(CAN0,1)
+#define CAN0_WORD01                              CAN_WORD0_REG(CAN0,1)
+#define CAN0_WORD11                              CAN_WORD1_REG(CAN0,1)
+#define CAN0_CS2                                 CAN_CS_REG(CAN0,2)
+#define CAN0_ID2                                 CAN_ID_REG(CAN0,2)
+#define CAN0_WORD02                              CAN_WORD0_REG(CAN0,2)
+#define CAN0_WORD12                              CAN_WORD1_REG(CAN0,2)
+#define CAN0_CS3                                 CAN_CS_REG(CAN0,3)
+#define CAN0_ID3                                 CAN_ID_REG(CAN0,3)
+#define CAN0_WORD03                              CAN_WORD0_REG(CAN0,3)
+#define CAN0_WORD13                              CAN_WORD1_REG(CAN0,3)
+#define CAN0_CS4                                 CAN_CS_REG(CAN0,4)
+#define CAN0_ID4                                 CAN_ID_REG(CAN0,4)
+#define CAN0_WORD04                              CAN_WORD0_REG(CAN0,4)
+#define CAN0_WORD14                              CAN_WORD1_REG(CAN0,4)
+#define CAN0_CS5                                 CAN_CS_REG(CAN0,5)
+#define CAN0_ID5                                 CAN_ID_REG(CAN0,5)
+#define CAN0_WORD05                              CAN_WORD0_REG(CAN0,5)
+#define CAN0_WORD15                              CAN_WORD1_REG(CAN0,5)
+#define CAN0_CS6                                 CAN_CS_REG(CAN0,6)
+#define CAN0_ID6                                 CAN_ID_REG(CAN0,6)
+#define CAN0_WORD06                              CAN_WORD0_REG(CAN0,6)
+#define CAN0_WORD16                              CAN_WORD1_REG(CAN0,6)
+#define CAN0_CS7                                 CAN_CS_REG(CAN0,7)
+#define CAN0_ID7                                 CAN_ID_REG(CAN0,7)
+#define CAN0_WORD07                              CAN_WORD0_REG(CAN0,7)
+#define CAN0_WORD17                              CAN_WORD1_REG(CAN0,7)
+#define CAN0_CS8                                 CAN_CS_REG(CAN0,8)
+#define CAN0_ID8                                 CAN_ID_REG(CAN0,8)
+#define CAN0_WORD08                              CAN_WORD0_REG(CAN0,8)
+#define CAN0_WORD18                              CAN_WORD1_REG(CAN0,8)
+#define CAN0_CS9                                 CAN_CS_REG(CAN0,9)
+#define CAN0_ID9                                 CAN_ID_REG(CAN0,9)
+#define CAN0_WORD09                              CAN_WORD0_REG(CAN0,9)
+#define CAN0_WORD19                              CAN_WORD1_REG(CAN0,9)
+#define CAN0_CS10                                CAN_CS_REG(CAN0,10)
+#define CAN0_ID10                                CAN_ID_REG(CAN0,10)
+#define CAN0_WORD010                             CAN_WORD0_REG(CAN0,10)
+#define CAN0_WORD110                             CAN_WORD1_REG(CAN0,10)
+#define CAN0_CS11                                CAN_CS_REG(CAN0,11)
+#define CAN0_ID11                                CAN_ID_REG(CAN0,11)
+#define CAN0_WORD011                             CAN_WORD0_REG(CAN0,11)
+#define CAN0_WORD111                             CAN_WORD1_REG(CAN0,11)
+#define CAN0_CS12                                CAN_CS_REG(CAN0,12)
+#define CAN0_ID12                                CAN_ID_REG(CAN0,12)
+#define CAN0_WORD012                             CAN_WORD0_REG(CAN0,12)
+#define CAN0_WORD112                             CAN_WORD1_REG(CAN0,12)
+#define CAN0_CS13                                CAN_CS_REG(CAN0,13)
+#define CAN0_ID13                                CAN_ID_REG(CAN0,13)
+#define CAN0_WORD013                             CAN_WORD0_REG(CAN0,13)
+#define CAN0_WORD113                             CAN_WORD1_REG(CAN0,13)
+#define CAN0_CS14                                CAN_CS_REG(CAN0,14)
+#define CAN0_ID14                                CAN_ID_REG(CAN0,14)
+#define CAN0_WORD014                             CAN_WORD0_REG(CAN0,14)
+#define CAN0_WORD114                             CAN_WORD1_REG(CAN0,14)
+#define CAN0_CS15                                CAN_CS_REG(CAN0,15)
+#define CAN0_ID15                                CAN_ID_REG(CAN0,15)
+#define CAN0_WORD015                             CAN_WORD0_REG(CAN0,15)
+#define CAN0_WORD115                             CAN_WORD1_REG(CAN0,15)
+#define CAN0_RXIMR0                              CAN_RXIMR_REG(CAN0,0)
+#define CAN0_RXIMR1                              CAN_RXIMR_REG(CAN0,1)
+#define CAN0_RXIMR2                              CAN_RXIMR_REG(CAN0,2)
+#define CAN0_RXIMR3                              CAN_RXIMR_REG(CAN0,3)
+#define CAN0_RXIMR4                              CAN_RXIMR_REG(CAN0,4)
+#define CAN0_RXIMR5                              CAN_RXIMR_REG(CAN0,5)
+#define CAN0_RXIMR6                              CAN_RXIMR_REG(CAN0,6)
+#define CAN0_RXIMR7                              CAN_RXIMR_REG(CAN0,7)
+#define CAN0_RXIMR8                              CAN_RXIMR_REG(CAN0,8)
+#define CAN0_RXIMR9                              CAN_RXIMR_REG(CAN0,9)
+#define CAN0_RXIMR10                             CAN_RXIMR_REG(CAN0,10)
+#define CAN0_RXIMR11                             CAN_RXIMR_REG(CAN0,11)
+#define CAN0_RXIMR12                             CAN_RXIMR_REG(CAN0,12)
+#define CAN0_RXIMR13                             CAN_RXIMR_REG(CAN0,13)
+#define CAN0_RXIMR14                             CAN_RXIMR_REG(CAN0,14)
+#define CAN0_RXIMR15                             CAN_RXIMR_REG(CAN0,15)
+
+/* CAN - Register array accessors */
+#define CAN0_CS(index)                           CAN_CS_REG(CAN0,index)
+#define CAN0_ID(index)                           CAN_ID_REG(CAN0,index)
+#define CAN0_WORD0(index)                        CAN_WORD0_REG(CAN0,index)
+#define CAN0_WORD1(index)                        CAN_WORD1_REG(CAN0,index)
+#define CAN0_RXIMR(index)                        CAN_RXIMR_REG(CAN0,index)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+  __O  uint32_t DIRECT[16];                        /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[2048];
+  __O  uint32_t LDR_CASR;                          /**< Status register - Load Register command, offset: 0x840 */
+  __O  uint32_t LDR_CAA;                           /**< Accumulator register - Load Register command, offset: 0x844 */
+  __O  uint32_t LDR_CA[9];                         /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
+       uint8_t RESERVED_1[20];
+  __I  uint32_t STR_CASR;                          /**< Status register - Store Register command, offset: 0x880 */
+  __I  uint32_t STR_CAA;                           /**< Accumulator register - Store Register command, offset: 0x884 */
+  __I  uint32_t STR_CA[9];                         /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
+       uint8_t RESERVED_2[20];
+  __O  uint32_t ADR_CASR;                          /**< Status register - Add Register command, offset: 0x8C0 */
+  __O  uint32_t ADR_CAA;                           /**< Accumulator register - Add to register command, offset: 0x8C4 */
+  __O  uint32_t ADR_CA[9];                         /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
+       uint8_t RESERVED_3[20];
+  __O  uint32_t RADR_CASR;                         /**< Status register - Reverse and Add to Register command, offset: 0x900 */
+  __O  uint32_t RADR_CAA;                          /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
+  __O  uint32_t RADR_CA[9];                        /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
+       uint8_t RESERVED_4[84];
+  __O  uint32_t XOR_CASR;                          /**< Status register - Exclusive Or command, offset: 0x980 */
+  __O  uint32_t XOR_CAA;                           /**< Accumulator register - Exclusive Or command, offset: 0x984 */
+  __O  uint32_t XOR_CA[9];                         /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
+       uint8_t RESERVED_5[20];
+  __O  uint32_t ROTL_CASR;                         /**< Status register - Rotate Left command, offset: 0x9C0 */
+  __O  uint32_t ROTL_CAA;                          /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
+  __O  uint32_t ROTL_CA[9];                        /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
+       uint8_t RESERVED_6[276];
+  __O  uint32_t AESC_CASR;                         /**< Status register - AES Column Operation command, offset: 0xB00 */
+  __O  uint32_t AESC_CAA;                          /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
+  __O  uint32_t AESC_CA[9];                        /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
+       uint8_t RESERVED_7[20];
+  __O  uint32_t AESIC_CASR;                        /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
+  __O  uint32_t AESIC_CAA;                         /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
+  __O  uint32_t AESIC_CA[9];                       /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
+} CAU_Type, *CAU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register accessors */
+#define CAU_DIRECT_REG(base,index)               ((base)->DIRECT[index])
+#define CAU_DIRECT_COUNT                         16
+#define CAU_LDR_CASR_REG(base)                   ((base)->LDR_CASR)
+#define CAU_LDR_CAA_REG(base)                    ((base)->LDR_CAA)
+#define CAU_LDR_CA_REG(base,index)               ((base)->LDR_CA[index])
+#define CAU_LDR_CA_COUNT                         9
+#define CAU_STR_CASR_REG(base)                   ((base)->STR_CASR)
+#define CAU_STR_CAA_REG(base)                    ((base)->STR_CAA)
+#define CAU_STR_CA_REG(base,index)               ((base)->STR_CA[index])
+#define CAU_STR_CA_COUNT                         9
+#define CAU_ADR_CASR_REG(base)                   ((base)->ADR_CASR)
+#define CAU_ADR_CAA_REG(base)                    ((base)->ADR_CAA)
+#define CAU_ADR_CA_REG(base,index)               ((base)->ADR_CA[index])
+#define CAU_ADR_CA_COUNT                         9
+#define CAU_RADR_CASR_REG(base)                  ((base)->RADR_CASR)
+#define CAU_RADR_CAA_REG(base)                   ((base)->RADR_CAA)
+#define CAU_RADR_CA_REG(base,index)              ((base)->RADR_CA[index])
+#define CAU_RADR_CA_COUNT                        9
+#define CAU_XOR_CASR_REG(base)                   ((base)->XOR_CASR)
+#define CAU_XOR_CAA_REG(base)                    ((base)->XOR_CAA)
+#define CAU_XOR_CA_REG(base,index)               ((base)->XOR_CA[index])
+#define CAU_XOR_CA_COUNT                         9
+#define CAU_ROTL_CASR_REG(base)                  ((base)->ROTL_CASR)
+#define CAU_ROTL_CAA_REG(base)                   ((base)->ROTL_CAA)
+#define CAU_ROTL_CA_REG(base,index)              ((base)->ROTL_CA[index])
+#define CAU_ROTL_CA_COUNT                        9
+#define CAU_AESC_CASR_REG(base)                  ((base)->AESC_CASR)
+#define CAU_AESC_CAA_REG(base)                   ((base)->AESC_CAA)
+#define CAU_AESC_CA_REG(base,index)              ((base)->AESC_CA[index])
+#define CAU_AESC_CA_COUNT                        9
+#define CAU_AESIC_CASR_REG(base)                 ((base)->AESIC_CASR)
+#define CAU_AESIC_CAA_REG(base)                  ((base)->AESIC_CAA)
+#define CAU_AESIC_CA_REG(base,index)             ((base)->AESIC_CA[index])
+#define CAU_AESIC_CA_COUNT                       9
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/* DIRECT Bit Fields */
+#define CAU_DIRECT_CAU_DIRECT0_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT0_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT0_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT0(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
+#define CAU_DIRECT_CAU_DIRECT1_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT1_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT1_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT1(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
+#define CAU_DIRECT_CAU_DIRECT2_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT2_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT2_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT2(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
+#define CAU_DIRECT_CAU_DIRECT3_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT3_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT3_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT3(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
+#define CAU_DIRECT_CAU_DIRECT4_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT4_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT4_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT4(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
+#define CAU_DIRECT_CAU_DIRECT5_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT5_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT5_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT5(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
+#define CAU_DIRECT_CAU_DIRECT6_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT6_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT6_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT6(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
+#define CAU_DIRECT_CAU_DIRECT7_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT7_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT7_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT7(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
+#define CAU_DIRECT_CAU_DIRECT8_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT8_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT8_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT8(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
+#define CAU_DIRECT_CAU_DIRECT9_MASK              0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT9_SHIFT             0
+#define CAU_DIRECT_CAU_DIRECT9_WIDTH             32
+#define CAU_DIRECT_CAU_DIRECT9(x)                (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
+#define CAU_DIRECT_CAU_DIRECT10_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT10_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT10_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT10(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
+#define CAU_DIRECT_CAU_DIRECT11_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT11_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT11_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT11(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
+#define CAU_DIRECT_CAU_DIRECT12_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT12_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT12_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT12(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
+#define CAU_DIRECT_CAU_DIRECT13_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT13_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT13_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT13(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
+#define CAU_DIRECT_CAU_DIRECT14_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT14_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT14_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT14(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
+#define CAU_DIRECT_CAU_DIRECT15_MASK             0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT15_SHIFT            0
+#define CAU_DIRECT_CAU_DIRECT15_WIDTH            32
+#define CAU_DIRECT_CAU_DIRECT15(x)               (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
+/* LDR_CASR Bit Fields */
+#define CAU_LDR_CASR_IC_MASK                     0x1u
+#define CAU_LDR_CASR_IC_SHIFT                    0
+#define CAU_LDR_CASR_IC_WIDTH                    1
+#define CAU_LDR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_IC_SHIFT))&CAU_LDR_CASR_IC_MASK)
+#define CAU_LDR_CASR_DPE_MASK                    0x2u
+#define CAU_LDR_CASR_DPE_SHIFT                   1
+#define CAU_LDR_CASR_DPE_WIDTH                   1
+#define CAU_LDR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_DPE_SHIFT))&CAU_LDR_CASR_DPE_MASK)
+#define CAU_LDR_CASR_VER_MASK                    0xF0000000u
+#define CAU_LDR_CASR_VER_SHIFT                   28
+#define CAU_LDR_CASR_VER_WIDTH                   4
+#define CAU_LDR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
+/* LDR_CAA Bit Fields */
+#define CAU_LDR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_LDR_CAA_ACC_SHIFT                    0
+#define CAU_LDR_CAA_ACC_WIDTH                    32
+#define CAU_LDR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
+/* LDR_CA Bit Fields */
+#define CAU_LDR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA0_SHIFT                     0
+#define CAU_LDR_CA_CA0_WIDTH                     32
+#define CAU_LDR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
+#define CAU_LDR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA1_SHIFT                     0
+#define CAU_LDR_CA_CA1_WIDTH                     32
+#define CAU_LDR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
+#define CAU_LDR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA2_SHIFT                     0
+#define CAU_LDR_CA_CA2_WIDTH                     32
+#define CAU_LDR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
+#define CAU_LDR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA3_SHIFT                     0
+#define CAU_LDR_CA_CA3_WIDTH                     32
+#define CAU_LDR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
+#define CAU_LDR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA4_SHIFT                     0
+#define CAU_LDR_CA_CA4_WIDTH                     32
+#define CAU_LDR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
+#define CAU_LDR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA5_SHIFT                     0
+#define CAU_LDR_CA_CA5_WIDTH                     32
+#define CAU_LDR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
+#define CAU_LDR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA6_SHIFT                     0
+#define CAU_LDR_CA_CA6_WIDTH                     32
+#define CAU_LDR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
+#define CAU_LDR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA7_SHIFT                     0
+#define CAU_LDR_CA_CA7_WIDTH                     32
+#define CAU_LDR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
+#define CAU_LDR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_LDR_CA_CA8_SHIFT                     0
+#define CAU_LDR_CA_CA8_WIDTH                     32
+#define CAU_LDR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
+/* STR_CASR Bit Fields */
+#define CAU_STR_CASR_IC_MASK                     0x1u
+#define CAU_STR_CASR_IC_SHIFT                    0
+#define CAU_STR_CASR_IC_WIDTH                    1
+#define CAU_STR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_IC_SHIFT))&CAU_STR_CASR_IC_MASK)
+#define CAU_STR_CASR_DPE_MASK                    0x2u
+#define CAU_STR_CASR_DPE_SHIFT                   1
+#define CAU_STR_CASR_DPE_WIDTH                   1
+#define CAU_STR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_DPE_SHIFT))&CAU_STR_CASR_DPE_MASK)
+#define CAU_STR_CASR_VER_MASK                    0xF0000000u
+#define CAU_STR_CASR_VER_SHIFT                   28
+#define CAU_STR_CASR_VER_WIDTH                   4
+#define CAU_STR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
+/* STR_CAA Bit Fields */
+#define CAU_STR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_STR_CAA_ACC_SHIFT                    0
+#define CAU_STR_CAA_ACC_WIDTH                    32
+#define CAU_STR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
+/* STR_CA Bit Fields */
+#define CAU_STR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA0_SHIFT                     0
+#define CAU_STR_CA_CA0_WIDTH                     32
+#define CAU_STR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
+#define CAU_STR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA1_SHIFT                     0
+#define CAU_STR_CA_CA1_WIDTH                     32
+#define CAU_STR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
+#define CAU_STR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA2_SHIFT                     0
+#define CAU_STR_CA_CA2_WIDTH                     32
+#define CAU_STR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
+#define CAU_STR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA3_SHIFT                     0
+#define CAU_STR_CA_CA3_WIDTH                     32
+#define CAU_STR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
+#define CAU_STR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA4_SHIFT                     0
+#define CAU_STR_CA_CA4_WIDTH                     32
+#define CAU_STR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
+#define CAU_STR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA5_SHIFT                     0
+#define CAU_STR_CA_CA5_WIDTH                     32
+#define CAU_STR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
+#define CAU_STR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA6_SHIFT                     0
+#define CAU_STR_CA_CA6_WIDTH                     32
+#define CAU_STR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
+#define CAU_STR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA7_SHIFT                     0
+#define CAU_STR_CA_CA7_WIDTH                     32
+#define CAU_STR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
+#define CAU_STR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_STR_CA_CA8_SHIFT                     0
+#define CAU_STR_CA_CA8_WIDTH                     32
+#define CAU_STR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
+/* ADR_CASR Bit Fields */
+#define CAU_ADR_CASR_IC_MASK                     0x1u
+#define CAU_ADR_CASR_IC_SHIFT                    0
+#define CAU_ADR_CASR_IC_WIDTH                    1
+#define CAU_ADR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_IC_SHIFT))&CAU_ADR_CASR_IC_MASK)
+#define CAU_ADR_CASR_DPE_MASK                    0x2u
+#define CAU_ADR_CASR_DPE_SHIFT                   1
+#define CAU_ADR_CASR_DPE_WIDTH                   1
+#define CAU_ADR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_DPE_SHIFT))&CAU_ADR_CASR_DPE_MASK)
+#define CAU_ADR_CASR_VER_MASK                    0xF0000000u
+#define CAU_ADR_CASR_VER_SHIFT                   28
+#define CAU_ADR_CASR_VER_WIDTH                   4
+#define CAU_ADR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
+/* ADR_CAA Bit Fields */
+#define CAU_ADR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_ADR_CAA_ACC_SHIFT                    0
+#define CAU_ADR_CAA_ACC_WIDTH                    32
+#define CAU_ADR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
+/* ADR_CA Bit Fields */
+#define CAU_ADR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA0_SHIFT                     0
+#define CAU_ADR_CA_CA0_WIDTH                     32
+#define CAU_ADR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
+#define CAU_ADR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA1_SHIFT                     0
+#define CAU_ADR_CA_CA1_WIDTH                     32
+#define CAU_ADR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
+#define CAU_ADR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA2_SHIFT                     0
+#define CAU_ADR_CA_CA2_WIDTH                     32
+#define CAU_ADR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
+#define CAU_ADR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA3_SHIFT                     0
+#define CAU_ADR_CA_CA3_WIDTH                     32
+#define CAU_ADR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
+#define CAU_ADR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA4_SHIFT                     0
+#define CAU_ADR_CA_CA4_WIDTH                     32
+#define CAU_ADR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
+#define CAU_ADR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA5_SHIFT                     0
+#define CAU_ADR_CA_CA5_WIDTH                     32
+#define CAU_ADR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
+#define CAU_ADR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA6_SHIFT                     0
+#define CAU_ADR_CA_CA6_WIDTH                     32
+#define CAU_ADR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
+#define CAU_ADR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA7_SHIFT                     0
+#define CAU_ADR_CA_CA7_WIDTH                     32
+#define CAU_ADR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
+#define CAU_ADR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_ADR_CA_CA8_SHIFT                     0
+#define CAU_ADR_CA_CA8_WIDTH                     32
+#define CAU_ADR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
+/* RADR_CASR Bit Fields */
+#define CAU_RADR_CASR_IC_MASK                    0x1u
+#define CAU_RADR_CASR_IC_SHIFT                   0
+#define CAU_RADR_CASR_IC_WIDTH                   1
+#define CAU_RADR_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_IC_SHIFT))&CAU_RADR_CASR_IC_MASK)
+#define CAU_RADR_CASR_DPE_MASK                   0x2u
+#define CAU_RADR_CASR_DPE_SHIFT                  1
+#define CAU_RADR_CASR_DPE_WIDTH                  1
+#define CAU_RADR_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_DPE_SHIFT))&CAU_RADR_CASR_DPE_MASK)
+#define CAU_RADR_CASR_VER_MASK                   0xF0000000u
+#define CAU_RADR_CASR_VER_SHIFT                  28
+#define CAU_RADR_CASR_VER_WIDTH                  4
+#define CAU_RADR_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
+/* RADR_CAA Bit Fields */
+#define CAU_RADR_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_RADR_CAA_ACC_SHIFT                   0
+#define CAU_RADR_CAA_ACC_WIDTH                   32
+#define CAU_RADR_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
+/* RADR_CA Bit Fields */
+#define CAU_RADR_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA0_SHIFT                    0
+#define CAU_RADR_CA_CA0_WIDTH                    32
+#define CAU_RADR_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
+#define CAU_RADR_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA1_SHIFT                    0
+#define CAU_RADR_CA_CA1_WIDTH                    32
+#define CAU_RADR_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
+#define CAU_RADR_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA2_SHIFT                    0
+#define CAU_RADR_CA_CA2_WIDTH                    32
+#define CAU_RADR_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
+#define CAU_RADR_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA3_SHIFT                    0
+#define CAU_RADR_CA_CA3_WIDTH                    32
+#define CAU_RADR_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
+#define CAU_RADR_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA4_SHIFT                    0
+#define CAU_RADR_CA_CA4_WIDTH                    32
+#define CAU_RADR_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
+#define CAU_RADR_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA5_SHIFT                    0
+#define CAU_RADR_CA_CA5_WIDTH                    32
+#define CAU_RADR_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
+#define CAU_RADR_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA6_SHIFT                    0
+#define CAU_RADR_CA_CA6_WIDTH                    32
+#define CAU_RADR_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
+#define CAU_RADR_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA7_SHIFT                    0
+#define CAU_RADR_CA_CA7_WIDTH                    32
+#define CAU_RADR_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
+#define CAU_RADR_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_RADR_CA_CA8_SHIFT                    0
+#define CAU_RADR_CA_CA8_WIDTH                    32
+#define CAU_RADR_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
+/* XOR_CASR Bit Fields */
+#define CAU_XOR_CASR_IC_MASK                     0x1u
+#define CAU_XOR_CASR_IC_SHIFT                    0
+#define CAU_XOR_CASR_IC_WIDTH                    1
+#define CAU_XOR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_IC_SHIFT))&CAU_XOR_CASR_IC_MASK)
+#define CAU_XOR_CASR_DPE_MASK                    0x2u
+#define CAU_XOR_CASR_DPE_SHIFT                   1
+#define CAU_XOR_CASR_DPE_WIDTH                   1
+#define CAU_XOR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_DPE_SHIFT))&CAU_XOR_CASR_DPE_MASK)
+#define CAU_XOR_CASR_VER_MASK                    0xF0000000u
+#define CAU_XOR_CASR_VER_SHIFT                   28
+#define CAU_XOR_CASR_VER_WIDTH                   4
+#define CAU_XOR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
+/* XOR_CAA Bit Fields */
+#define CAU_XOR_CAA_ACC_MASK                     0xFFFFFFFFu
+#define CAU_XOR_CAA_ACC_SHIFT                    0
+#define CAU_XOR_CAA_ACC_WIDTH                    32
+#define CAU_XOR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
+/* XOR_CA Bit Fields */
+#define CAU_XOR_CA_CA0_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA0_SHIFT                     0
+#define CAU_XOR_CA_CA0_WIDTH                     32
+#define CAU_XOR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
+#define CAU_XOR_CA_CA1_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA1_SHIFT                     0
+#define CAU_XOR_CA_CA1_WIDTH                     32
+#define CAU_XOR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
+#define CAU_XOR_CA_CA2_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA2_SHIFT                     0
+#define CAU_XOR_CA_CA2_WIDTH                     32
+#define CAU_XOR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
+#define CAU_XOR_CA_CA3_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA3_SHIFT                     0
+#define CAU_XOR_CA_CA3_WIDTH                     32
+#define CAU_XOR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
+#define CAU_XOR_CA_CA4_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA4_SHIFT                     0
+#define CAU_XOR_CA_CA4_WIDTH                     32
+#define CAU_XOR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
+#define CAU_XOR_CA_CA5_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA5_SHIFT                     0
+#define CAU_XOR_CA_CA5_WIDTH                     32
+#define CAU_XOR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
+#define CAU_XOR_CA_CA6_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA6_SHIFT                     0
+#define CAU_XOR_CA_CA6_WIDTH                     32
+#define CAU_XOR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
+#define CAU_XOR_CA_CA7_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA7_SHIFT                     0
+#define CAU_XOR_CA_CA7_WIDTH                     32
+#define CAU_XOR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
+#define CAU_XOR_CA_CA8_MASK                      0xFFFFFFFFu
+#define CAU_XOR_CA_CA8_SHIFT                     0
+#define CAU_XOR_CA_CA8_WIDTH                     32
+#define CAU_XOR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
+/* ROTL_CASR Bit Fields */
+#define CAU_ROTL_CASR_IC_MASK                    0x1u
+#define CAU_ROTL_CASR_IC_SHIFT                   0
+#define CAU_ROTL_CASR_IC_WIDTH                   1
+#define CAU_ROTL_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_IC_SHIFT))&CAU_ROTL_CASR_IC_MASK)
+#define CAU_ROTL_CASR_DPE_MASK                   0x2u
+#define CAU_ROTL_CASR_DPE_SHIFT                  1
+#define CAU_ROTL_CASR_DPE_WIDTH                  1
+#define CAU_ROTL_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_DPE_SHIFT))&CAU_ROTL_CASR_DPE_MASK)
+#define CAU_ROTL_CASR_VER_MASK                   0xF0000000u
+#define CAU_ROTL_CASR_VER_SHIFT                  28
+#define CAU_ROTL_CASR_VER_WIDTH                  4
+#define CAU_ROTL_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
+/* ROTL_CAA Bit Fields */
+#define CAU_ROTL_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_ROTL_CAA_ACC_SHIFT                   0
+#define CAU_ROTL_CAA_ACC_WIDTH                   32
+#define CAU_ROTL_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
+/* ROTL_CA Bit Fields */
+#define CAU_ROTL_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA0_SHIFT                    0
+#define CAU_ROTL_CA_CA0_WIDTH                    32
+#define CAU_ROTL_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
+#define CAU_ROTL_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA1_SHIFT                    0
+#define CAU_ROTL_CA_CA1_WIDTH                    32
+#define CAU_ROTL_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
+#define CAU_ROTL_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA2_SHIFT                    0
+#define CAU_ROTL_CA_CA2_WIDTH                    32
+#define CAU_ROTL_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
+#define CAU_ROTL_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA3_SHIFT                    0
+#define CAU_ROTL_CA_CA3_WIDTH                    32
+#define CAU_ROTL_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
+#define CAU_ROTL_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA4_SHIFT                    0
+#define CAU_ROTL_CA_CA4_WIDTH                    32
+#define CAU_ROTL_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
+#define CAU_ROTL_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA5_SHIFT                    0
+#define CAU_ROTL_CA_CA5_WIDTH                    32
+#define CAU_ROTL_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
+#define CAU_ROTL_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA6_SHIFT                    0
+#define CAU_ROTL_CA_CA6_WIDTH                    32
+#define CAU_ROTL_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
+#define CAU_ROTL_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA7_SHIFT                    0
+#define CAU_ROTL_CA_CA7_WIDTH                    32
+#define CAU_ROTL_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
+#define CAU_ROTL_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_ROTL_CA_CA8_SHIFT                    0
+#define CAU_ROTL_CA_CA8_WIDTH                    32
+#define CAU_ROTL_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
+/* AESC_CASR Bit Fields */
+#define CAU_AESC_CASR_IC_MASK                    0x1u
+#define CAU_AESC_CASR_IC_SHIFT                   0
+#define CAU_AESC_CASR_IC_WIDTH                   1
+#define CAU_AESC_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_IC_SHIFT))&CAU_AESC_CASR_IC_MASK)
+#define CAU_AESC_CASR_DPE_MASK                   0x2u
+#define CAU_AESC_CASR_DPE_SHIFT                  1
+#define CAU_AESC_CASR_DPE_WIDTH                  1
+#define CAU_AESC_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_DPE_SHIFT))&CAU_AESC_CASR_DPE_MASK)
+#define CAU_AESC_CASR_VER_MASK                   0xF0000000u
+#define CAU_AESC_CASR_VER_SHIFT                  28
+#define CAU_AESC_CASR_VER_WIDTH                  4
+#define CAU_AESC_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
+/* AESC_CAA Bit Fields */
+#define CAU_AESC_CAA_ACC_MASK                    0xFFFFFFFFu
+#define CAU_AESC_CAA_ACC_SHIFT                   0
+#define CAU_AESC_CAA_ACC_WIDTH                   32
+#define CAU_AESC_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
+/* AESC_CA Bit Fields */
+#define CAU_AESC_CA_CA0_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA0_SHIFT                    0
+#define CAU_AESC_CA_CA0_WIDTH                    32
+#define CAU_AESC_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
+#define CAU_AESC_CA_CA1_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA1_SHIFT                    0
+#define CAU_AESC_CA_CA1_WIDTH                    32
+#define CAU_AESC_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
+#define CAU_AESC_CA_CA2_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA2_SHIFT                    0
+#define CAU_AESC_CA_CA2_WIDTH                    32
+#define CAU_AESC_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
+#define CAU_AESC_CA_CA3_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA3_SHIFT                    0
+#define CAU_AESC_CA_CA3_WIDTH                    32
+#define CAU_AESC_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
+#define CAU_AESC_CA_CA4_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA4_SHIFT                    0
+#define CAU_AESC_CA_CA4_WIDTH                    32
+#define CAU_AESC_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
+#define CAU_AESC_CA_CA5_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA5_SHIFT                    0
+#define CAU_AESC_CA_CA5_WIDTH                    32
+#define CAU_AESC_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
+#define CAU_AESC_CA_CA6_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA6_SHIFT                    0
+#define CAU_AESC_CA_CA6_WIDTH                    32
+#define CAU_AESC_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
+#define CAU_AESC_CA_CA7_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA7_SHIFT                    0
+#define CAU_AESC_CA_CA7_WIDTH                    32
+#define CAU_AESC_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
+#define CAU_AESC_CA_CA8_MASK                     0xFFFFFFFFu
+#define CAU_AESC_CA_CA8_SHIFT                    0
+#define CAU_AESC_CA_CA8_WIDTH                    32
+#define CAU_AESC_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
+/* AESIC_CASR Bit Fields */
+#define CAU_AESIC_CASR_IC_MASK                   0x1u
+#define CAU_AESIC_CASR_IC_SHIFT                  0
+#define CAU_AESIC_CASR_IC_WIDTH                  1
+#define CAU_AESIC_CASR_IC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_IC_SHIFT))&CAU_AESIC_CASR_IC_MASK)
+#define CAU_AESIC_CASR_DPE_MASK                  0x2u
+#define CAU_AESIC_CASR_DPE_SHIFT                 1
+#define CAU_AESIC_CASR_DPE_WIDTH                 1
+#define CAU_AESIC_CASR_DPE(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_DPE_SHIFT))&CAU_AESIC_CASR_DPE_MASK)
+#define CAU_AESIC_CASR_VER_MASK                  0xF0000000u
+#define CAU_AESIC_CASR_VER_SHIFT                 28
+#define CAU_AESIC_CASR_VER_WIDTH                 4
+#define CAU_AESIC_CASR_VER(x)                    (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
+/* AESIC_CAA Bit Fields */
+#define CAU_AESIC_CAA_ACC_MASK                   0xFFFFFFFFu
+#define CAU_AESIC_CAA_ACC_SHIFT                  0
+#define CAU_AESIC_CAA_ACC_WIDTH                  32
+#define CAU_AESIC_CAA_ACC(x)                     (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
+/* AESIC_CA Bit Fields */
+#define CAU_AESIC_CA_CA0_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA0_SHIFT                   0
+#define CAU_AESIC_CA_CA0_WIDTH                   32
+#define CAU_AESIC_CA_CA0(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
+#define CAU_AESIC_CA_CA1_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA1_SHIFT                   0
+#define CAU_AESIC_CA_CA1_WIDTH                   32
+#define CAU_AESIC_CA_CA1(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
+#define CAU_AESIC_CA_CA2_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA2_SHIFT                   0
+#define CAU_AESIC_CA_CA2_WIDTH                   32
+#define CAU_AESIC_CA_CA2(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
+#define CAU_AESIC_CA_CA3_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA3_SHIFT                   0
+#define CAU_AESIC_CA_CA3_WIDTH                   32
+#define CAU_AESIC_CA_CA3(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
+#define CAU_AESIC_CA_CA4_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA4_SHIFT                   0
+#define CAU_AESIC_CA_CA4_WIDTH                   32
+#define CAU_AESIC_CA_CA4(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
+#define CAU_AESIC_CA_CA5_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA5_SHIFT                   0
+#define CAU_AESIC_CA_CA5_WIDTH                   32
+#define CAU_AESIC_CA_CA5(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
+#define CAU_AESIC_CA_CA6_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA6_SHIFT                   0
+#define CAU_AESIC_CA_CA6_WIDTH                   32
+#define CAU_AESIC_CA_CA6(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
+#define CAU_AESIC_CA_CA7_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA7_SHIFT                   0
+#define CAU_AESIC_CA_CA7_WIDTH                   32
+#define CAU_AESIC_CA_CA7(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
+#define CAU_AESIC_CA_CA8_MASK                    0xFFFFFFFFu
+#define CAU_AESIC_CA_CA8_SHIFT                   0
+#define CAU_AESIC_CA_CA8_WIDTH                   32
+#define CAU_AESIC_CA_CA8(x)                      (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+/** Peripheral CAU base address */
+#define CAU_BASE                                 (0xE0081000u)
+/** Peripheral CAU base pointer */
+#define CAU                                      ((CAU_Type *)CAU_BASE)
+#define CAU_BASE_PTR                             (CAU)
+/** Array initializer of CAU peripheral base addresses */
+#define CAU_BASE_ADDRS                           { CAU_BASE }
+/** Array initializer of CAU peripheral base pointers */
+#define CAU_BASE_PTRS                            { CAU }
+
+/* ----------------------------------------------------------------------------
+   -- CAU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
+ * @{
+ */
+
+
+/* CAU - Register instance definitions */
+/* CAU */
+#define CAU_DIRECT0                              CAU_DIRECT_REG(CAU,0)
+#define CAU_DIRECT1                              CAU_DIRECT_REG(CAU,1)
+#define CAU_DIRECT2                              CAU_DIRECT_REG(CAU,2)
+#define CAU_DIRECT3                              CAU_DIRECT_REG(CAU,3)
+#define CAU_DIRECT4                              CAU_DIRECT_REG(CAU,4)
+#define CAU_DIRECT5                              CAU_DIRECT_REG(CAU,5)
+#define CAU_DIRECT6                              CAU_DIRECT_REG(CAU,6)
+#define CAU_DIRECT7                              CAU_DIRECT_REG(CAU,7)
+#define CAU_DIRECT8                              CAU_DIRECT_REG(CAU,8)
+#define CAU_DIRECT9                              CAU_DIRECT_REG(CAU,9)
+#define CAU_DIRECT10                             CAU_DIRECT_REG(CAU,10)
+#define CAU_DIRECT11                             CAU_DIRECT_REG(CAU,11)
+#define CAU_DIRECT12                             CAU_DIRECT_REG(CAU,12)
+#define CAU_DIRECT13                             CAU_DIRECT_REG(CAU,13)
+#define CAU_DIRECT14                             CAU_DIRECT_REG(CAU,14)
+#define CAU_DIRECT15                             CAU_DIRECT_REG(CAU,15)
+#define CAU_LDR_CASR                             CAU_LDR_CASR_REG(CAU)
+#define CAU_LDR_CAA                              CAU_LDR_CAA_REG(CAU)
+#define CAU_LDR_CA0                              CAU_LDR_CA_REG(CAU,0)
+#define CAU_LDR_CA1                              CAU_LDR_CA_REG(CAU,1)
+#define CAU_LDR_CA2                              CAU_LDR_CA_REG(CAU,2)
+#define CAU_LDR_CA3                              CAU_LDR_CA_REG(CAU,3)
+#define CAU_LDR_CA4                              CAU_LDR_CA_REG(CAU,4)
+#define CAU_LDR_CA5                              CAU_LDR_CA_REG(CAU,5)
+#define CAU_LDR_CA6                              CAU_LDR_CA_REG(CAU,6)
+#define CAU_LDR_CA7                              CAU_LDR_CA_REG(CAU,7)
+#define CAU_LDR_CA8                              CAU_LDR_CA_REG(CAU,8)
+#define CAU_STR_CASR                             CAU_STR_CASR_REG(CAU)
+#define CAU_STR_CAA                              CAU_STR_CAA_REG(CAU)
+#define CAU_STR_CA0                              CAU_STR_CA_REG(CAU,0)
+#define CAU_STR_CA1                              CAU_STR_CA_REG(CAU,1)
+#define CAU_STR_CA2                              CAU_STR_CA_REG(CAU,2)
+#define CAU_STR_CA3                              CAU_STR_CA_REG(CAU,3)
+#define CAU_STR_CA4                              CAU_STR_CA_REG(CAU,4)
+#define CAU_STR_CA5                              CAU_STR_CA_REG(CAU,5)
+#define CAU_STR_CA6                              CAU_STR_CA_REG(CAU,6)
+#define CAU_STR_CA7                              CAU_STR_CA_REG(CAU,7)
+#define CAU_STR_CA8                              CAU_STR_CA_REG(CAU,8)
+#define CAU_ADR_CASR                             CAU_ADR_CASR_REG(CAU)
+#define CAU_ADR_CAA                              CAU_ADR_CAA_REG(CAU)
+#define CAU_ADR_CA0                              CAU_ADR_CA_REG(CAU,0)
+#define CAU_ADR_CA1                              CAU_ADR_CA_REG(CAU,1)
+#define CAU_ADR_CA2                              CAU_ADR_CA_REG(CAU,2)
+#define CAU_ADR_CA3                              CAU_ADR_CA_REG(CAU,3)
+#define CAU_ADR_CA4                              CAU_ADR_CA_REG(CAU,4)
+#define CAU_ADR_CA5                              CAU_ADR_CA_REG(CAU,5)
+#define CAU_ADR_CA6                              CAU_ADR_CA_REG(CAU,6)
+#define CAU_ADR_CA7                              CAU_ADR_CA_REG(CAU,7)
+#define CAU_ADR_CA8                              CAU_ADR_CA_REG(CAU,8)
+#define CAU_RADR_CASR                            CAU_RADR_CASR_REG(CAU)
+#define CAU_RADR_CAA                             CAU_RADR_CAA_REG(CAU)
+#define CAU_RADR_CA0                             CAU_RADR_CA_REG(CAU,0)
+#define CAU_RADR_CA1                             CAU_RADR_CA_REG(CAU,1)
+#define CAU_RADR_CA2                             CAU_RADR_CA_REG(CAU,2)
+#define CAU_RADR_CA3                             CAU_RADR_CA_REG(CAU,3)
+#define CAU_RADR_CA4                             CAU_RADR_CA_REG(CAU,4)
+#define CAU_RADR_CA5                             CAU_RADR_CA_REG(CAU,5)
+#define CAU_RADR_CA6                             CAU_RADR_CA_REG(CAU,6)
+#define CAU_RADR_CA7                             CAU_RADR_CA_REG(CAU,7)
+#define CAU_RADR_CA8                             CAU_RADR_CA_REG(CAU,8)
+#define CAU_XOR_CASR                             CAU_XOR_CASR_REG(CAU)
+#define CAU_XOR_CAA                              CAU_XOR_CAA_REG(CAU)
+#define CAU_XOR_CA0                              CAU_XOR_CA_REG(CAU,0)
+#define CAU_XOR_CA1                              CAU_XOR_CA_REG(CAU,1)
+#define CAU_XOR_CA2                              CAU_XOR_CA_REG(CAU,2)
+#define CAU_XOR_CA3                              CAU_XOR_CA_REG(CAU,3)
+#define CAU_XOR_CA4                              CAU_XOR_CA_REG(CAU,4)
+#define CAU_XOR_CA5                              CAU_XOR_CA_REG(CAU,5)
+#define CAU_XOR_CA6                              CAU_XOR_CA_REG(CAU,6)
+#define CAU_XOR_CA7                              CAU_XOR_CA_REG(CAU,7)
+#define CAU_XOR_CA8                              CAU_XOR_CA_REG(CAU,8)
+#define CAU_ROTL_CASR                            CAU_ROTL_CASR_REG(CAU)
+#define CAU_ROTL_CAA                             CAU_ROTL_CAA_REG(CAU)
+#define CAU_ROTL_CA0                             CAU_ROTL_CA_REG(CAU,0)
+#define CAU_ROTL_CA1                             CAU_ROTL_CA_REG(CAU,1)
+#define CAU_ROTL_CA2                             CAU_ROTL_CA_REG(CAU,2)
+#define CAU_ROTL_CA3                             CAU_ROTL_CA_REG(CAU,3)
+#define CAU_ROTL_CA4                             CAU_ROTL_CA_REG(CAU,4)
+#define CAU_ROTL_CA5                             CAU_ROTL_CA_REG(CAU,5)
+#define CAU_ROTL_CA6                             CAU_ROTL_CA_REG(CAU,6)
+#define CAU_ROTL_CA7                             CAU_ROTL_CA_REG(CAU,7)
+#define CAU_ROTL_CA8                             CAU_ROTL_CA_REG(CAU,8)
+#define CAU_AESC_CASR                            CAU_AESC_CASR_REG(CAU)
+#define CAU_AESC_CAA                             CAU_AESC_CAA_REG(CAU)
+#define CAU_AESC_CA0                             CAU_AESC_CA_REG(CAU,0)
+#define CAU_AESC_CA1                             CAU_AESC_CA_REG(CAU,1)
+#define CAU_AESC_CA2                             CAU_AESC_CA_REG(CAU,2)
+#define CAU_AESC_CA3                             CAU_AESC_CA_REG(CAU,3)
+#define CAU_AESC_CA4                             CAU_AESC_CA_REG(CAU,4)
+#define CAU_AESC_CA5                             CAU_AESC_CA_REG(CAU,5)
+#define CAU_AESC_CA6                             CAU_AESC_CA_REG(CAU,6)
+#define CAU_AESC_CA7                             CAU_AESC_CA_REG(CAU,7)
+#define CAU_AESC_CA8                             CAU_AESC_CA_REG(CAU,8)
+#define CAU_AESIC_CASR                           CAU_AESIC_CASR_REG(CAU)
+#define CAU_AESIC_CAA                            CAU_AESIC_CAA_REG(CAU)
+#define CAU_AESIC_CA0                            CAU_AESIC_CA_REG(CAU,0)
+#define CAU_AESIC_CA1                            CAU_AESIC_CA_REG(CAU,1)
+#define CAU_AESIC_CA2                            CAU_AESIC_CA_REG(CAU,2)
+#define CAU_AESIC_CA3                            CAU_AESIC_CA_REG(CAU,3)
+#define CAU_AESIC_CA4                            CAU_AESIC_CA_REG(CAU,4)
+#define CAU_AESIC_CA5                            CAU_AESIC_CA_REG(CAU,5)
+#define CAU_AESIC_CA6                            CAU_AESIC_CA_REG(CAU,6)
+#define CAU_AESIC_CA7                            CAU_AESIC_CA_REG(CAU,7)
+#define CAU_AESIC_CA8                            CAU_AESIC_CA_REG(CAU,8)
+
+/* CAU - Register array accessors */
+#define CAU_DIRECT(index)                        CAU_DIRECT_REG(CAU,index)
+#define CAU_LDR_CA(index)                        CAU_LDR_CA_REG(CAU,index)
+#define CAU_STR_CA(index)                        CAU_STR_CA_REG(CAU,index)
+#define CAU_ADR_CA(index)                        CAU_ADR_CA_REG(CAU,index)
+#define CAU_RADR_CA(index)                       CAU_RADR_CA_REG(CAU,index)
+#define CAU_XOR_CA(index)                        CAU_XOR_CA_REG(CAU,index)
+#define CAU_ROTL_CA(index)                       CAU_ROTL_CA_REG(CAU,index)
+#define CAU_AESC_CA(index)                       CAU_AESC_CA_REG(CAU,index)
+#define CAU_AESIC_CA(index)                      CAU_AESIC_CA_REG(CAU,index)
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base)                        ((base)->CR0)
+#define CMP_CR1_REG(base)                        ((base)->CR1)
+#define CMP_FPR_REG(base)                        ((base)->FPR)
+#define CMP_SCR_REG(base)                        ((base)->SCR)
+#define CMP_DACCR_REG(base)                      ((base)->DACCR)
+#define CMP_MUXCR_REG(base)                      ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK                     0x3u
+#define CMP_CR0_HYSTCTR_SHIFT                    0
+#define CMP_CR0_HYSTCTR_WIDTH                    2
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT                 4
+#define CMP_CR0_FILTER_CNT_WIDTH                 3
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK                          0x1u
+#define CMP_CR1_EN_SHIFT                         0
+#define CMP_CR1_EN_WIDTH                         1
+#define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK                         0x2u
+#define CMP_CR1_OPE_SHIFT                        1
+#define CMP_CR1_OPE_WIDTH                        1
+#define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK                         0x4u
+#define CMP_CR1_COS_SHIFT                        2
+#define CMP_CR1_COS_WIDTH                        1
+#define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK                         0x8u
+#define CMP_CR1_INV_SHIFT                        3
+#define CMP_CR1_INV_WIDTH                        1
+#define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK                       0x10u
+#define CMP_CR1_PMODE_SHIFT                      4
+#define CMP_CR1_PMODE_WIDTH                      1
+#define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
+#define CMP_CR1_WE_MASK                          0x40u
+#define CMP_CR1_WE_SHIFT                         6
+#define CMP_CR1_WE_WIDTH                         1
+#define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK                          0x80u
+#define CMP_CR1_SE_SHIFT                         7
+#define CMP_CR1_SE_WIDTH                         1
+#define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK                    0xFFu
+#define CMP_FPR_FILT_PER_SHIFT                   0
+#define CMP_FPR_FILT_PER_WIDTH                   8
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK                        0x1u
+#define CMP_SCR_COUT_SHIFT                       0
+#define CMP_SCR_COUT_WIDTH                       1
+#define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK                         0x2u
+#define CMP_SCR_CFF_SHIFT                        1
+#define CMP_SCR_CFF_WIDTH                        1
+#define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK                         0x4u
+#define CMP_SCR_CFR_SHIFT                        2
+#define CMP_SCR_CFR_WIDTH                        1
+#define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK                         0x8u
+#define CMP_SCR_IEF_SHIFT                        3
+#define CMP_SCR_IEF_WIDTH                        1
+#define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK                         0x10u
+#define CMP_SCR_IER_SHIFT                        4
+#define CMP_SCR_IER_WIDTH                        1
+#define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK                       0x40u
+#define CMP_SCR_DMAEN_SHIFT                      6
+#define CMP_SCR_DMAEN_WIDTH                      1
+#define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK                     0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT                    0
+#define CMP_DACCR_VOSEL_WIDTH                    6
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     0x40u
+#define CMP_DACCR_VRSEL_SHIFT                    6
+#define CMP_DACCR_VRSEL_WIDTH                    1
+#define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK                     0x80u
+#define CMP_DACCR_DACEN_SHIFT                    7
+#define CMP_DACCR_DACEN_WIDTH                    1
+#define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK                      0x7u
+#define CMP_MUXCR_MSEL_SHIFT                     0
+#define CMP_MUXCR_MSEL_WIDTH                     3
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      0x38u
+#define CMP_MUXCR_PSEL_SHIFT                     3
+#define CMP_MUXCR_PSEL_WIDTH                     3
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK                      0x80u
+#define CMP_MUXCR_PSTM_SHIFT                     7
+#define CMP_MUXCR_PSTM_WIDTH                     1
+#define CMP_MUXCR_PSTM(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSTM_SHIFT))&CMP_MUXCR_PSTM_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR                            (CMP0)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE                                (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1                                     ((CMP_Type *)CMP1_BASE)
+#define CMP1_BASE_PTR                            (CMP1)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE                                (0x40073010u)
+/** Peripheral CMP2 base pointer */
+#define CMP2                                     ((CMP_Type *)CMP2_BASE)
+#define CMP2_BASE_PTR                            (CMP2)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS                           { CMP0_BASE, CMP1_BASE, CMP2_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS                            { CMP0, CMP1, CMP2 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMP - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0                                 CMP_CR0_REG(CMP0)
+#define CMP0_CR1                                 CMP_CR1_REG(CMP0)
+#define CMP0_FPR                                 CMP_FPR_REG(CMP0)
+#define CMP0_SCR                                 CMP_SCR_REG(CMP0)
+#define CMP0_DACCR                               CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR                               CMP_MUXCR_REG(CMP0)
+/* CMP1 */
+#define CMP1_CR0                                 CMP_CR0_REG(CMP1)
+#define CMP1_CR1                                 CMP_CR1_REG(CMP1)
+#define CMP1_FPR                                 CMP_FPR_REG(CMP1)
+#define CMP1_SCR                                 CMP_SCR_REG(CMP1)
+#define CMP1_DACCR                               CMP_DACCR_REG(CMP1)
+#define CMP1_MUXCR                               CMP_MUXCR_REG(CMP1)
+/* CMP2 */
+#define CMP2_CR0                                 CMP_CR0_REG(CMP2)
+#define CMP2_CR1                                 CMP_CR1_REG(CMP2)
+#define CMP2_FPR                                 CMP_FPR_REG(CMP2)
+#define CMP2_SCR                                 CMP_SCR_REG(CMP2)
+#define CMP2_DACCR                               CMP_DACCR_REG(CMP2)
+#define CMP2_MUXCR                               CMP_MUXCR_REG(CMP2)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CGH1;                               /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+  __IO uint8_t CGL1;                               /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+  __IO uint8_t CGH2;                               /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+  __IO uint8_t CGL2;                               /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+  __IO uint8_t OC;                                 /**< CMT Output Control Register, offset: 0x4 */
+  __IO uint8_t MSC;                                /**< CMT Modulator Status and Control Register, offset: 0x5 */
+  __IO uint8_t CMD1;                               /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+  __IO uint8_t CMD2;                               /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+  __IO uint8_t CMD3;                               /**< CMT Modulator Data Register Space High, offset: 0x8 */
+  __IO uint8_t CMD4;                               /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+  __IO uint8_t PPS;                                /**< CMT Primary Prescaler Register, offset: 0xA */
+  __IO uint8_t DMA;                                /**< CMT Direct Memory Access Register, offset: 0xB */
+} CMT_Type, *CMT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register accessors */
+#define CMT_CGH1_REG(base)                       ((base)->CGH1)
+#define CMT_CGL1_REG(base)                       ((base)->CGL1)
+#define CMT_CGH2_REG(base)                       ((base)->CGH2)
+#define CMT_CGL2_REG(base)                       ((base)->CGL2)
+#define CMT_OC_REG(base)                         ((base)->OC)
+#define CMT_MSC_REG(base)                        ((base)->MSC)
+#define CMT_CMD1_REG(base)                       ((base)->CMD1)
+#define CMT_CMD2_REG(base)                       ((base)->CMD2)
+#define CMT_CMD3_REG(base)                       ((base)->CMD3)
+#define CMT_CMD4_REG(base)                       ((base)->CMD4)
+#define CMT_PPS_REG(base)                        ((base)->PPS)
+#define CMT_DMA_REG(base)                        ((base)->DMA)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK                         0xFFu
+#define CMT_CGH1_PH_SHIFT                        0
+#define CMT_CGH1_PH_WIDTH                        8
+#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK                         0xFFu
+#define CMT_CGL1_PL_SHIFT                        0
+#define CMT_CGL1_PL_WIDTH                        8
+#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK                         0xFFu
+#define CMT_CGH2_SH_SHIFT                        0
+#define CMT_CGH2_SH_WIDTH                        8
+#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK                         0xFFu
+#define CMT_CGL2_SL_SHIFT                        0
+#define CMT_CGL2_SL_WIDTH                        8
+#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK                       0x20u
+#define CMT_OC_IROPEN_SHIFT                      5
+#define CMT_OC_IROPEN_WIDTH                      1
+#define CMT_OC_IROPEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROPEN_SHIFT))&CMT_OC_IROPEN_MASK)
+#define CMT_OC_CMTPOL_MASK                       0x40u
+#define CMT_OC_CMTPOL_SHIFT                      6
+#define CMT_OC_CMTPOL_WIDTH                      1
+#define CMT_OC_CMTPOL(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_OC_CMTPOL_SHIFT))&CMT_OC_CMTPOL_MASK)
+#define CMT_OC_IROL_MASK                         0x80u
+#define CMT_OC_IROL_SHIFT                        7
+#define CMT_OC_IROL_WIDTH                        1
+#define CMT_OC_IROL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROL_SHIFT))&CMT_OC_IROL_MASK)
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK                       0x1u
+#define CMT_MSC_MCGEN_SHIFT                      0
+#define CMT_MSC_MCGEN_WIDTH                      1
+#define CMT_MSC_MCGEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_MCGEN_SHIFT))&CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_EOCIE_MASK                       0x2u
+#define CMT_MSC_EOCIE_SHIFT                      1
+#define CMT_MSC_EOCIE_WIDTH                      1
+#define CMT_MSC_EOCIE(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCIE_SHIFT))&CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_FSK_MASK                         0x4u
+#define CMT_MSC_FSK_SHIFT                        2
+#define CMT_MSC_FSK_WIDTH                        1
+#define CMT_MSC_FSK(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_MSC_FSK_SHIFT))&CMT_MSC_FSK_MASK)
+#define CMT_MSC_BASE_MASK                        0x8u
+#define CMT_MSC_BASE_SHIFT                       3
+#define CMT_MSC_BASE_WIDTH                       1
+#define CMT_MSC_BASE(x)                          (((uint8_t)(((uint8_t)(x))<<CMT_MSC_BASE_SHIFT))&CMT_MSC_BASE_MASK)
+#define CMT_MSC_EXSPC_MASK                       0x10u
+#define CMT_MSC_EXSPC_SHIFT                      4
+#define CMT_MSC_EXSPC_WIDTH                      1
+#define CMT_MSC_EXSPC(x)                         (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EXSPC_SHIFT))&CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_CMTDIV_MASK                      0x60u
+#define CMT_MSC_CMTDIV_SHIFT                     5
+#define CMT_MSC_CMTDIV_WIDTH                     2
+#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK                        0x80u
+#define CMT_MSC_EOCF_SHIFT                       7
+#define CMT_MSC_EOCF_WIDTH                       1
+#define CMT_MSC_EOCF(x)                          (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCF_SHIFT))&CMT_MSC_EOCF_MASK)
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK                         0xFFu
+#define CMT_CMD1_MB_SHIFT                        0
+#define CMT_CMD1_MB_WIDTH                        8
+#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK                         0xFFu
+#define CMT_CMD2_MB_SHIFT                        0
+#define CMT_CMD2_MB_WIDTH                        8
+#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK                         0xFFu
+#define CMT_CMD3_SB_SHIFT                        0
+#define CMT_CMD3_SB_WIDTH                        8
+#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK                         0xFFu
+#define CMT_CMD4_SB_SHIFT                        0
+#define CMT_CMD4_SB_WIDTH                        8
+#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK                      0xFu
+#define CMT_PPS_PPSDIV_SHIFT                     0
+#define CMT_PPS_PPSDIV_WIDTH                     4
+#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK                         0x1u
+#define CMT_DMA_DMA_SHIFT                        0
+#define CMT_DMA_DMA_WIDTH                        1
+#define CMT_DMA_DMA(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_DMA_DMA_SHIFT))&CMT_DMA_DMA_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE                                 (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT                                      ((CMT_Type *)CMT_BASE)
+#define CMT_BASE_PTR                             (CMT)
+/** Array initializer of CMT peripheral base addresses */
+#define CMT_BASE_ADDRS                           { CMT_BASE }
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASE_PTRS                            { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS                                 { CMT_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- CMT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
+ * @{
+ */
+
+
+/* CMT - Register instance definitions */
+/* CMT */
+#define CMT_CGH1                                 CMT_CGH1_REG(CMT)
+#define CMT_CGL1                                 CMT_CGL1_REG(CMT)
+#define CMT_CGH2                                 CMT_CGH2_REG(CMT)
+#define CMT_CGL2                                 CMT_CGL2_REG(CMT)
+#define CMT_OC                                   CMT_OC_REG(CMT)
+#define CMT_MSC                                  CMT_MSC_REG(CMT)
+#define CMT_CMD1                                 CMT_CMD1_REG(CMT)
+#define CMT_CMD2                                 CMT_CMD2_REG(CMT)
+#define CMT_CMD3                                 CMT_CMD3_REG(CMT)
+#define CMT_CMD4                                 CMT_CMD4_REG(CMT)
+#define CMT_PPS                                  CMT_PPS_REG(CMT)
+#define CMT_DMA                                  CMT_DMA_REG(CMT)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type, *CRC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register accessors */
+#define CRC_DATAL_REG(base)                      ((base)->ACCESS16BIT.DATAL)
+#define CRC_DATAH_REG(base)                      ((base)->ACCESS16BIT.DATAH)
+#define CRC_DATA_REG(base)                       ((base)->DATA)
+#define CRC_DATALL_REG(base)                     ((base)->ACCESS8BIT.DATALL)
+#define CRC_DATALU_REG(base)                     ((base)->ACCESS8BIT.DATALU)
+#define CRC_DATAHL_REG(base)                     ((base)->ACCESS8BIT.DATAHL)
+#define CRC_DATAHU_REG(base)                     ((base)->ACCESS8BIT.DATAHU)
+#define CRC_GPOLYL_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYL)
+#define CRC_GPOLYH_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYH)
+#define CRC_GPOLY_REG(base)                      ((base)->GPOLY)
+#define CRC_GPOLYLL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
+#define CRC_GPOLYLU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
+#define CRC_GPOLYHL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
+#define CRC_GPOLYHU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
+#define CRC_CTRL_REG(base)                       ((base)->CTRL)
+#define CRC_CTRLHU_REG(base)                     ((base)->CTRL_ACCESS8BIT.CTRLHU)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK                     0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT                    0
+#define CRC_DATAL_DATAL_WIDTH                    16
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK                     0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT                    0
+#define CRC_DATAH_DATAH_WIDTH                    16
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK                         0xFFu
+#define CRC_DATA_LL_SHIFT                        0
+#define CRC_DATA_LL_WIDTH                        8
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         0xFF00u
+#define CRC_DATA_LU_SHIFT                        8
+#define CRC_DATA_LU_WIDTH                        8
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         0xFF0000u
+#define CRC_DATA_HL_SHIFT                        16
+#define CRC_DATA_HL_WIDTH                        8
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         0xFF000000u
+#define CRC_DATA_HU_SHIFT                        24
+#define CRC_DATA_HU_WIDTH                        8
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK                   0xFFu
+#define CRC_DATALL_DATALL_SHIFT                  0
+#define CRC_DATALL_DATALL_WIDTH                  8
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK                   0xFFu
+#define CRC_DATALU_DATALU_SHIFT                  0
+#define CRC_DATALU_DATALU_WIDTH                  8
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK                   0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT                  0
+#define CRC_DATAHL_DATAHL_WIDTH                  8
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK                   0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT                  0
+#define CRC_DATAHU_DATAHU_WIDTH                  8
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT                  0
+#define CRC_GPOLYL_GPOLYL_WIDTH                  16
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT                  0
+#define CRC_GPOLYH_GPOLYH_WIDTH                  16
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK                       0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT                      0
+#define CRC_GPOLY_LOW_WIDTH                      16
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT                     16
+#define CRC_GPOLY_HIGH_WIDTH                     16
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                0
+#define CRC_GPOLYLL_GPOLYLL_WIDTH                8
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                0
+#define CRC_GPOLYLU_GPOLYLU_WIDTH                8
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                0
+#define CRC_GPOLYHL_GPOLYHL_WIDTH                8
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                0
+#define CRC_GPOLYHU_GPOLYHU_WIDTH                8
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK                       0x1000000u
+#define CRC_CTRL_TCRC_SHIFT                      24
+#define CRC_CTRL_TCRC_WIDTH                      1
+#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK                        0x2000000u
+#define CRC_CTRL_WAS_SHIFT                       25
+#define CRC_CTRL_WAS_WIDTH                       1
+#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK                       0x4000000u
+#define CRC_CTRL_FXOR_SHIFT                      26
+#define CRC_CTRL_FXOR_WIDTH                      1
+#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK                       0x30000000u
+#define CRC_CTRL_TOTR_SHIFT                      28
+#define CRC_CTRL_TOTR_WIDTH                      2
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        0xC0000000u
+#define CRC_CTRL_TOT_SHIFT                       30
+#define CRC_CTRL_TOT_WIDTH                       2
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK                     0x1u
+#define CRC_CTRLHU_TCRC_SHIFT                    0
+#define CRC_CTRLHU_TCRC_WIDTH                    1
+#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TCRC_SHIFT))&CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK                      0x2u
+#define CRC_CTRLHU_WAS_SHIFT                     1
+#define CRC_CTRLHU_WAS_WIDTH                     1
+#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_WAS_SHIFT))&CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK                     0x4u
+#define CRC_CTRLHU_FXOR_SHIFT                    2
+#define CRC_CTRLHU_FXOR_WIDTH                    1
+#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_FXOR_SHIFT))&CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK                     0x30u
+#define CRC_CTRLHU_TOTR_SHIFT                    4
+#define CRC_CTRLHU_TOTR_WIDTH                    2
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      0xC0u
+#define CRC_CTRLHU_TOT_SHIFT                     6
+#define CRC_CTRLHU_TOT_WIDTH                     2
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+#define CRC_BASE_PTR                             (CRC0)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/* ----------------------------------------------------------------------------
+   -- CRC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register instance definitions */
+/* CRC */
+#define CRC_DATA                                 CRC_DATA_REG(CRC0)
+#define CRC_DATAL                                CRC_DATAL_REG(CRC0)
+#define CRC_DATALL                               CRC_DATALL_REG(CRC0)
+#define CRC_DATALU                               CRC_DATALU_REG(CRC0)
+#define CRC_DATAH                                CRC_DATAH_REG(CRC0)
+#define CRC_DATAHL                               CRC_DATAHL_REG(CRC0)
+#define CRC_DATAHU                               CRC_DATAHU_REG(CRC0)
+#define CRC_GPOLY                                CRC_GPOLY_REG(CRC0)
+#define CRC_GPOLYL                               CRC_GPOLYL_REG(CRC0)
+#define CRC_GPOLYLL                              CRC_GPOLYLL_REG(CRC0)
+#define CRC_GPOLYLU                              CRC_GPOLYLU_REG(CRC0)
+#define CRC_GPOLYH                               CRC_GPOLYH_REG(CRC0)
+#define CRC_GPOLYHL                              CRC_GPOLYHL_REG(CRC0)
+#define CRC_GPOLYHU                              CRC_GPOLYHU_REG(CRC0)
+#define CRC_CTRL                                 CRC_CTRL_REG(CRC0)
+#define CRC_CTRLHU                               CRC_CTRLHU_REG(CRC0)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[16];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index)                 ((base)->DAT[index].DATL)
+#define DAC_DATL_COUNT                           16
+#define DAC_DATH_REG(base,index)                 ((base)->DAT[index].DATH)
+#define DAC_DATH_COUNT                           16
+#define DAC_SR_REG(base)                         ((base)->SR)
+#define DAC_C0_REG(base)                         ((base)->C0)
+#define DAC_C1_REG(base)                         ((base)->C1)
+#define DAC_C2_REG(base)                         ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK                      0xFFu
+#define DAC_DATL_DATA0_SHIFT                     0
+#define DAC_DATL_DATA0_WIDTH                     8
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK                      0xFu
+#define DAC_DATH_DATA1_SHIFT                     0
+#define DAC_DATH_DATA1_WIDTH                     4
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK                    0x1u
+#define DAC_SR_DACBFRPBF_SHIFT                   0
+#define DAC_SR_DACBFRPBF_WIDTH                   1
+#define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK                    0x2u
+#define DAC_SR_DACBFRPTF_SHIFT                   1
+#define DAC_SR_DACBFRPTF_WIDTH                   1
+#define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK                     0x4u
+#define DAC_SR_DACBFWMF_SHIFT                    2
+#define DAC_SR_DACBFWMF_WIDTH                    1
+#define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFWMF_SHIFT))&DAC_SR_DACBFWMF_MASK)
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK                     0x1u
+#define DAC_C0_DACBBIEN_SHIFT                    0
+#define DAC_C0_DACBBIEN_WIDTH                    1
+#define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK                     0x2u
+#define DAC_C0_DACBTIEN_SHIFT                    1
+#define DAC_C0_DACBTIEN_WIDTH                    1
+#define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK                     0x4u
+#define DAC_C0_DACBWIEN_SHIFT                    2
+#define DAC_C0_DACBWIEN_WIDTH                    1
+#define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBWIEN_SHIFT))&DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK                         0x8u
+#define DAC_C0_LPEN_SHIFT                        3
+#define DAC_C0_LPEN_WIDTH                        1
+#define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK                     0x10u
+#define DAC_C0_DACSWTRG_SHIFT                    4
+#define DAC_C0_DACSWTRG_WIDTH                    1
+#define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK                    0x20u
+#define DAC_C0_DACTRGSEL_SHIFT                   5
+#define DAC_C0_DACTRGSEL_WIDTH                   1
+#define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK                       0x40u
+#define DAC_C0_DACRFS_SHIFT                      6
+#define DAC_C0_DACRFS_WIDTH                      1
+#define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK                        0x80u
+#define DAC_C0_DACEN_SHIFT                       7
+#define DAC_C0_DACEN_WIDTH                       1
+#define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK                      0x1u
+#define DAC_C1_DACBFEN_SHIFT                     0
+#define DAC_C1_DACBFEN_WIDTH                     1
+#define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK                      0x6u
+#define DAC_C1_DACBFMD_SHIFT                     1
+#define DAC_C1_DACBFMD_WIDTH                     2
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK                      0x18u
+#define DAC_C1_DACBFWM_SHIFT                     3
+#define DAC_C1_DACBFWM_WIDTH                     2
+#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK                        0x80u
+#define DAC_C1_DMAEN_SHIFT                       7
+#define DAC_C1_DMAEN_WIDTH                       1
+#define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK                      0xFu
+#define DAC_C2_DACBFUP_SHIFT                     0
+#define DAC_C2_DACBFUP_WIDTH                     4
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      0xF0u
+#define DAC_C2_DACBFRP_SHIFT                     4
+#define DAC_C2_DACBFRP_WIDTH                     4
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR                            (DAC0)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE                                (0x400CD000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1                                     ((DAC_Type *)DAC1_BASE)
+#define DAC1_BASE_PTR                            (DAC1)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS                           { DAC0_BASE, DAC1_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS                            { DAC0, DAC1 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn, DAC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DAC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L                               DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H                               DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L                               DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H                               DAC_DATH_REG(DAC0,1)
+#define DAC0_DAT2L                               DAC_DATL_REG(DAC0,2)
+#define DAC0_DAT2H                               DAC_DATH_REG(DAC0,2)
+#define DAC0_DAT3L                               DAC_DATL_REG(DAC0,3)
+#define DAC0_DAT3H                               DAC_DATH_REG(DAC0,3)
+#define DAC0_DAT4L                               DAC_DATL_REG(DAC0,4)
+#define DAC0_DAT4H                               DAC_DATH_REG(DAC0,4)
+#define DAC0_DAT5L                               DAC_DATL_REG(DAC0,5)
+#define DAC0_DAT5H                               DAC_DATH_REG(DAC0,5)
+#define DAC0_DAT6L                               DAC_DATL_REG(DAC0,6)
+#define DAC0_DAT6H                               DAC_DATH_REG(DAC0,6)
+#define DAC0_DAT7L                               DAC_DATL_REG(DAC0,7)
+#define DAC0_DAT7H                               DAC_DATH_REG(DAC0,7)
+#define DAC0_DAT8L                               DAC_DATL_REG(DAC0,8)
+#define DAC0_DAT8H                               DAC_DATH_REG(DAC0,8)
+#define DAC0_DAT9L                               DAC_DATL_REG(DAC0,9)
+#define DAC0_DAT9H                               DAC_DATH_REG(DAC0,9)
+#define DAC0_DAT10L                              DAC_DATL_REG(DAC0,10)
+#define DAC0_DAT10H                              DAC_DATH_REG(DAC0,10)
+#define DAC0_DAT11L                              DAC_DATL_REG(DAC0,11)
+#define DAC0_DAT11H                              DAC_DATH_REG(DAC0,11)
+#define DAC0_DAT12L                              DAC_DATL_REG(DAC0,12)
+#define DAC0_DAT12H                              DAC_DATH_REG(DAC0,12)
+#define DAC0_DAT13L                              DAC_DATL_REG(DAC0,13)
+#define DAC0_DAT13H                              DAC_DATH_REG(DAC0,13)
+#define DAC0_DAT14L                              DAC_DATL_REG(DAC0,14)
+#define DAC0_DAT14H                              DAC_DATH_REG(DAC0,14)
+#define DAC0_DAT15L                              DAC_DATL_REG(DAC0,15)
+#define DAC0_DAT15H                              DAC_DATH_REG(DAC0,15)
+#define DAC0_SR                                  DAC_SR_REG(DAC0)
+#define DAC0_C0                                  DAC_C0_REG(DAC0)
+#define DAC0_C1                                  DAC_C1_REG(DAC0)
+#define DAC0_C2                                  DAC_C2_REG(DAC0)
+/* DAC1 */
+#define DAC1_DAT0L                               DAC_DATL_REG(DAC1,0)
+#define DAC1_DAT0H                               DAC_DATH_REG(DAC1,0)
+#define DAC1_DAT1L                               DAC_DATL_REG(DAC1,1)
+#define DAC1_DAT1H                               DAC_DATH_REG(DAC1,1)
+#define DAC1_DAT2L                               DAC_DATL_REG(DAC1,2)
+#define DAC1_DAT2H                               DAC_DATH_REG(DAC1,2)
+#define DAC1_DAT3L                               DAC_DATL_REG(DAC1,3)
+#define DAC1_DAT3H                               DAC_DATH_REG(DAC1,3)
+#define DAC1_DAT4L                               DAC_DATL_REG(DAC1,4)
+#define DAC1_DAT4H                               DAC_DATH_REG(DAC1,4)
+#define DAC1_DAT5L                               DAC_DATL_REG(DAC1,5)
+#define DAC1_DAT5H                               DAC_DATH_REG(DAC1,5)
+#define DAC1_DAT6L                               DAC_DATL_REG(DAC1,6)
+#define DAC1_DAT6H                               DAC_DATH_REG(DAC1,6)
+#define DAC1_DAT7L                               DAC_DATL_REG(DAC1,7)
+#define DAC1_DAT7H                               DAC_DATH_REG(DAC1,7)
+#define DAC1_DAT8L                               DAC_DATL_REG(DAC1,8)
+#define DAC1_DAT8H                               DAC_DATH_REG(DAC1,8)
+#define DAC1_DAT9L                               DAC_DATL_REG(DAC1,9)
+#define DAC1_DAT9H                               DAC_DATH_REG(DAC1,9)
+#define DAC1_DAT10L                              DAC_DATL_REG(DAC1,10)
+#define DAC1_DAT10H                              DAC_DATH_REG(DAC1,10)
+#define DAC1_DAT11L                              DAC_DATL_REG(DAC1,11)
+#define DAC1_DAT11H                              DAC_DATH_REG(DAC1,11)
+#define DAC1_DAT12L                              DAC_DATL_REG(DAC1,12)
+#define DAC1_DAT12H                              DAC_DATH_REG(DAC1,12)
+#define DAC1_DAT13L                              DAC_DATL_REG(DAC1,13)
+#define DAC1_DAT13H                              DAC_DATH_REG(DAC1,13)
+#define DAC1_DAT14L                              DAC_DATL_REG(DAC1,14)
+#define DAC1_DAT14H                              DAC_DATH_REG(DAC1,14)
+#define DAC1_DAT15L                              DAC_DATL_REG(DAC1,15)
+#define DAC1_DAT15H                              DAC_DATH_REG(DAC1,15)
+#define DAC1_SR                                  DAC_SR_REG(DAC1)
+#define DAC1_C0                                  DAC_C0_REG(DAC1)
+#define DAC1_C1                                  DAC_C1_REG(DAC1)
+#define DAC1_C2                                  DAC_C2_REG(DAC1)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index)                         DAC_DATL_REG(DAC0,index)
+#define DAC1_DATL(index)                         DAC_DATL_REG(DAC1,index)
+#define DAC0_DATH(index)                         DAC_DATH_REG(DAC0,index)
+#define DAC1_DATH(index)                         DAC_DATH_REG(DAC1,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[200];
+  __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /**< Channel n Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /**< Channel n Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /**< Channel n Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /**< Channel n Priority Register, offset: 0x107 */
+  __IO uint8_t DCHPRI11;                           /**< Channel n Priority Register, offset: 0x108 */
+  __IO uint8_t DCHPRI10;                           /**< Channel n Priority Register, offset: 0x109 */
+  __IO uint8_t DCHPRI9;                            /**< Channel n Priority Register, offset: 0x10A */
+  __IO uint8_t DCHPRI8;                            /**< Channel n Priority Register, offset: 0x10B */
+  __IO uint8_t DCHPRI15;                           /**< Channel n Priority Register, offset: 0x10C */
+  __IO uint8_t DCHPRI14;                           /**< Channel n Priority Register, offset: 0x10D */
+  __IO uint8_t DCHPRI13;                           /**< Channel n Priority Register, offset: 0x10E */
+  __IO uint8_t DCHPRI12;                           /**< Channel n Priority Register, offset: 0x10F */
+       uint8_t RESERVED_6[3824];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[16];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_CR_REG(base)                         ((base)->CR)
+#define DMA_ES_REG(base)                         ((base)->ES)
+#define DMA_ERQ_REG(base)                        ((base)->ERQ)
+#define DMA_EEI_REG(base)                        ((base)->EEI)
+#define DMA_CEEI_REG(base)                       ((base)->CEEI)
+#define DMA_SEEI_REG(base)                       ((base)->SEEI)
+#define DMA_CERQ_REG(base)                       ((base)->CERQ)
+#define DMA_SERQ_REG(base)                       ((base)->SERQ)
+#define DMA_CDNE_REG(base)                       ((base)->CDNE)
+#define DMA_SSRT_REG(base)                       ((base)->SSRT)
+#define DMA_CERR_REG(base)                       ((base)->CERR)
+#define DMA_CINT_REG(base)                       ((base)->CINT)
+#define DMA_INT_REG(base)                        ((base)->INT)
+#define DMA_ERR_REG(base)                        ((base)->ERR)
+#define DMA_HRS_REG(base)                        ((base)->HRS)
+#define DMA_DCHPRI3_REG(base)                    ((base)->DCHPRI3)
+#define DMA_DCHPRI2_REG(base)                    ((base)->DCHPRI2)
+#define DMA_DCHPRI1_REG(base)                    ((base)->DCHPRI1)
+#define DMA_DCHPRI0_REG(base)                    ((base)->DCHPRI0)
+#define DMA_DCHPRI7_REG(base)                    ((base)->DCHPRI7)
+#define DMA_DCHPRI6_REG(base)                    ((base)->DCHPRI6)
+#define DMA_DCHPRI5_REG(base)                    ((base)->DCHPRI5)
+#define DMA_DCHPRI4_REG(base)                    ((base)->DCHPRI4)
+#define DMA_DCHPRI11_REG(base)                   ((base)->DCHPRI11)
+#define DMA_DCHPRI10_REG(base)                   ((base)->DCHPRI10)
+#define DMA_DCHPRI9_REG(base)                    ((base)->DCHPRI9)
+#define DMA_DCHPRI8_REG(base)                    ((base)->DCHPRI8)
+#define DMA_DCHPRI15_REG(base)                   ((base)->DCHPRI15)
+#define DMA_DCHPRI14_REG(base)                   ((base)->DCHPRI14)
+#define DMA_DCHPRI13_REG(base)                   ((base)->DCHPRI13)
+#define DMA_DCHPRI12_REG(base)                   ((base)->DCHPRI12)
+#define DMA_SADDR_REG(base,index)                ((base)->TCD[index].SADDR)
+#define DMA_SADDR_COUNT                          16
+#define DMA_SOFF_REG(base,index)                 ((base)->TCD[index].SOFF)
+#define DMA_SOFF_COUNT                           16
+#define DMA_ATTR_REG(base,index)                 ((base)->TCD[index].ATTR)
+#define DMA_ATTR_COUNT                           16
+#define DMA_NBYTES_MLNO_REG(base,index)          ((base)->TCD[index].NBYTES_MLNO)
+#define DMA_NBYTES_MLNO_COUNT                    16
+#define DMA_NBYTES_MLOFFNO_REG(base,index)       ((base)->TCD[index].NBYTES_MLOFFNO)
+#define DMA_NBYTES_MLOFFNO_COUNT                 16
+#define DMA_NBYTES_MLOFFYES_REG(base,index)      ((base)->TCD[index].NBYTES_MLOFFYES)
+#define DMA_NBYTES_MLOFFYES_COUNT                16
+#define DMA_SLAST_REG(base,index)                ((base)->TCD[index].SLAST)
+#define DMA_SLAST_COUNT                          16
+#define DMA_DADDR_REG(base,index)                ((base)->TCD[index].DADDR)
+#define DMA_DADDR_COUNT                          16
+#define DMA_DOFF_REG(base,index)                 ((base)->TCD[index].DOFF)
+#define DMA_DOFF_COUNT                           16
+#define DMA_CITER_ELINKNO_REG(base,index)        ((base)->TCD[index].CITER_ELINKNO)
+#define DMA_CITER_ELINKNO_COUNT                  16
+#define DMA_CITER_ELINKYES_REG(base,index)       ((base)->TCD[index].CITER_ELINKYES)
+#define DMA_CITER_ELINKYES_COUNT                 16
+#define DMA_DLAST_SGA_REG(base,index)            ((base)->TCD[index].DLAST_SGA)
+#define DMA_DLAST_SGA_COUNT                      16
+#define DMA_CSR_REG(base,index)                  ((base)->TCD[index].CSR)
+#define DMA_CSR_COUNT                            16
+#define DMA_BITER_ELINKNO_REG(base,index)        ((base)->TCD[index].BITER_ELINKNO)
+#define DMA_BITER_ELINKNO_COUNT                  16
+#define DMA_BITER_ELINKYES_REG(base,index)       ((base)->TCD[index].BITER_ELINKYES)
+#define DMA_BITER_ELINKYES_COUNT                 16
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK                         0x2u
+#define DMA_CR_EDBG_SHIFT                        1
+#define DMA_CR_EDBG_WIDTH                        1
+#define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK                         0x4u
+#define DMA_CR_ERCA_SHIFT                        2
+#define DMA_CR_ERCA_WIDTH                        1
+#define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK                          0x10u
+#define DMA_CR_HOE_SHIFT                         4
+#define DMA_CR_HOE_WIDTH                         1
+#define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK                         0x20u
+#define DMA_CR_HALT_SHIFT                        5
+#define DMA_CR_HALT_WIDTH                        1
+#define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK                          0x40u
+#define DMA_CR_CLM_SHIFT                         6
+#define DMA_CR_CLM_WIDTH                         1
+#define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK                         0x80u
+#define DMA_CR_EMLM_SHIFT                        7
+#define DMA_CR_EMLM_WIDTH                        1
+#define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK                          0x10000u
+#define DMA_CR_ECX_SHIFT                         16
+#define DMA_CR_ECX_WIDTH                         1
+#define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK                           0x20000u
+#define DMA_CR_CX_SHIFT                          17
+#define DMA_CR_CX_WIDTH                          1
+#define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK                          0x1u
+#define DMA_ES_DBE_SHIFT                         0
+#define DMA_ES_DBE_WIDTH                         1
+#define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK                          0x2u
+#define DMA_ES_SBE_SHIFT                         1
+#define DMA_ES_SBE_WIDTH                         1
+#define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK                          0x4u
+#define DMA_ES_SGE_SHIFT                         2
+#define DMA_ES_SGE_WIDTH                         1
+#define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK                          0x8u
+#define DMA_ES_NCE_SHIFT                         3
+#define DMA_ES_NCE_WIDTH                         1
+#define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK                          0x10u
+#define DMA_ES_DOE_SHIFT                         4
+#define DMA_ES_DOE_WIDTH                         1
+#define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK                          0x20u
+#define DMA_ES_DAE_SHIFT                         5
+#define DMA_ES_DAE_WIDTH                         1
+#define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK                          0x40u
+#define DMA_ES_SOE_SHIFT                         6
+#define DMA_ES_SOE_WIDTH                         1
+#define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK                          0x80u
+#define DMA_ES_SAE_SHIFT                         7
+#define DMA_ES_SAE_WIDTH                         1
+#define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK                       0xF00u
+#define DMA_ES_ERRCHN_SHIFT                      8
+#define DMA_ES_ERRCHN_WIDTH                      4
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          0x4000u
+#define DMA_ES_CPE_SHIFT                         14
+#define DMA_ES_CPE_WIDTH                         1
+#define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK                          0x10000u
+#define DMA_ES_ECX_SHIFT                         16
+#define DMA_ES_ECX_WIDTH                         1
+#define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK                          0x80000000u
+#define DMA_ES_VLD_SHIFT                         31
+#define DMA_ES_VLD_WIDTH                         1
+#define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK                        0x1u
+#define DMA_ERQ_ERQ0_SHIFT                       0
+#define DMA_ERQ_ERQ0_WIDTH                       1
+#define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK                        0x2u
+#define DMA_ERQ_ERQ1_SHIFT                       1
+#define DMA_ERQ_ERQ1_WIDTH                       1
+#define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK                        0x4u
+#define DMA_ERQ_ERQ2_SHIFT                       2
+#define DMA_ERQ_ERQ2_WIDTH                       1
+#define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK                        0x8u
+#define DMA_ERQ_ERQ3_SHIFT                       3
+#define DMA_ERQ_ERQ3_WIDTH                       1
+#define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK                        0x10u
+#define DMA_ERQ_ERQ4_SHIFT                       4
+#define DMA_ERQ_ERQ4_WIDTH                       1
+#define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK                        0x20u
+#define DMA_ERQ_ERQ5_SHIFT                       5
+#define DMA_ERQ_ERQ5_WIDTH                       1
+#define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK                        0x40u
+#define DMA_ERQ_ERQ6_SHIFT                       6
+#define DMA_ERQ_ERQ6_WIDTH                       1
+#define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK                        0x80u
+#define DMA_ERQ_ERQ7_SHIFT                       7
+#define DMA_ERQ_ERQ7_WIDTH                       1
+#define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK                        0x100u
+#define DMA_ERQ_ERQ8_SHIFT                       8
+#define DMA_ERQ_ERQ8_WIDTH                       1
+#define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK                        0x200u
+#define DMA_ERQ_ERQ9_SHIFT                       9
+#define DMA_ERQ_ERQ9_WIDTH                       1
+#define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK                       0x400u
+#define DMA_ERQ_ERQ10_SHIFT                      10
+#define DMA_ERQ_ERQ10_WIDTH                      1
+#define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK                       0x800u
+#define DMA_ERQ_ERQ11_SHIFT                      11
+#define DMA_ERQ_ERQ11_WIDTH                      1
+#define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK                       0x1000u
+#define DMA_ERQ_ERQ12_SHIFT                      12
+#define DMA_ERQ_ERQ12_WIDTH                      1
+#define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK                       0x2000u
+#define DMA_ERQ_ERQ13_SHIFT                      13
+#define DMA_ERQ_ERQ13_WIDTH                      1
+#define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK                       0x4000u
+#define DMA_ERQ_ERQ14_SHIFT                      14
+#define DMA_ERQ_ERQ14_WIDTH                      1
+#define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK                       0x8000u
+#define DMA_ERQ_ERQ15_SHIFT                      15
+#define DMA_ERQ_ERQ15_WIDTH                      1
+#define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK                        0x1u
+#define DMA_EEI_EEI0_SHIFT                       0
+#define DMA_EEI_EEI0_WIDTH                       1
+#define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK                        0x2u
+#define DMA_EEI_EEI1_SHIFT                       1
+#define DMA_EEI_EEI1_WIDTH                       1
+#define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK                        0x4u
+#define DMA_EEI_EEI2_SHIFT                       2
+#define DMA_EEI_EEI2_WIDTH                       1
+#define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK                        0x8u
+#define DMA_EEI_EEI3_SHIFT                       3
+#define DMA_EEI_EEI3_WIDTH                       1
+#define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK                        0x10u
+#define DMA_EEI_EEI4_SHIFT                       4
+#define DMA_EEI_EEI4_WIDTH                       1
+#define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK                        0x20u
+#define DMA_EEI_EEI5_SHIFT                       5
+#define DMA_EEI_EEI5_WIDTH                       1
+#define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK                        0x40u
+#define DMA_EEI_EEI6_SHIFT                       6
+#define DMA_EEI_EEI6_WIDTH                       1
+#define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK                        0x80u
+#define DMA_EEI_EEI7_SHIFT                       7
+#define DMA_EEI_EEI7_WIDTH                       1
+#define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK                        0x100u
+#define DMA_EEI_EEI8_SHIFT                       8
+#define DMA_EEI_EEI8_WIDTH                       1
+#define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK                        0x200u
+#define DMA_EEI_EEI9_SHIFT                       9
+#define DMA_EEI_EEI9_WIDTH                       1
+#define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK                       0x400u
+#define DMA_EEI_EEI10_SHIFT                      10
+#define DMA_EEI_EEI10_WIDTH                      1
+#define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK                       0x800u
+#define DMA_EEI_EEI11_SHIFT                      11
+#define DMA_EEI_EEI11_WIDTH                      1
+#define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK                       0x1000u
+#define DMA_EEI_EEI12_SHIFT                      12
+#define DMA_EEI_EEI12_WIDTH                      1
+#define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK                       0x2000u
+#define DMA_EEI_EEI13_SHIFT                      13
+#define DMA_EEI_EEI13_WIDTH                      1
+#define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK                       0x4000u
+#define DMA_EEI_EEI14_SHIFT                      14
+#define DMA_EEI_EEI14_WIDTH                      1
+#define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK                       0x8000u
+#define DMA_EEI_EEI15_SHIFT                      15
+#define DMA_EEI_EEI15_WIDTH                      1
+#define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK                       0xFu
+#define DMA_CEEI_CEEI_SHIFT                      0
+#define DMA_CEEI_CEEI_WIDTH                      4
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       0x40u
+#define DMA_CEEI_CAEE_SHIFT                      6
+#define DMA_CEEI_CAEE_WIDTH                      1
+#define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK                        0x80u
+#define DMA_CEEI_NOP_SHIFT                       7
+#define DMA_CEEI_NOP_WIDTH                       1
+#define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK                       0xFu
+#define DMA_SEEI_SEEI_SHIFT                      0
+#define DMA_SEEI_SEEI_WIDTH                      4
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       0x40u
+#define DMA_SEEI_SAEE_SHIFT                      6
+#define DMA_SEEI_SAEE_WIDTH                      1
+#define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK                        0x80u
+#define DMA_SEEI_NOP_SHIFT                       7
+#define DMA_SEEI_NOP_WIDTH                       1
+#define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK                       0xFu
+#define DMA_CERQ_CERQ_SHIFT                      0
+#define DMA_CERQ_CERQ_WIDTH                      4
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       0x40u
+#define DMA_CERQ_CAER_SHIFT                      6
+#define DMA_CERQ_CAER_WIDTH                      1
+#define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK                        0x80u
+#define DMA_CERQ_NOP_SHIFT                       7
+#define DMA_CERQ_NOP_WIDTH                       1
+#define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK                       0xFu
+#define DMA_SERQ_SERQ_SHIFT                      0
+#define DMA_SERQ_SERQ_WIDTH                      4
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       0x40u
+#define DMA_SERQ_SAER_SHIFT                      6
+#define DMA_SERQ_SAER_WIDTH                      1
+#define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK                        0x80u
+#define DMA_SERQ_NOP_SHIFT                       7
+#define DMA_SERQ_NOP_WIDTH                       1
+#define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK                       0xFu
+#define DMA_CDNE_CDNE_SHIFT                      0
+#define DMA_CDNE_CDNE_WIDTH                      4
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       0x40u
+#define DMA_CDNE_CADN_SHIFT                      6
+#define DMA_CDNE_CADN_WIDTH                      1
+#define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK                        0x80u
+#define DMA_CDNE_NOP_SHIFT                       7
+#define DMA_CDNE_NOP_WIDTH                       1
+#define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK                       0xFu
+#define DMA_SSRT_SSRT_SHIFT                      0
+#define DMA_SSRT_SSRT_WIDTH                      4
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       0x40u
+#define DMA_SSRT_SAST_SHIFT                      6
+#define DMA_SSRT_SAST_WIDTH                      1
+#define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK                        0x80u
+#define DMA_SSRT_NOP_SHIFT                       7
+#define DMA_SSRT_NOP_WIDTH                       1
+#define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK                       0xFu
+#define DMA_CERR_CERR_SHIFT                      0
+#define DMA_CERR_CERR_WIDTH                      4
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       0x40u
+#define DMA_CERR_CAEI_SHIFT                      6
+#define DMA_CERR_CAEI_WIDTH                      1
+#define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK                        0x80u
+#define DMA_CERR_NOP_SHIFT                       7
+#define DMA_CERR_NOP_WIDTH                       1
+#define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK                       0xFu
+#define DMA_CINT_CINT_SHIFT                      0
+#define DMA_CINT_CINT_WIDTH                      4
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       0x40u
+#define DMA_CINT_CAIR_SHIFT                      6
+#define DMA_CINT_CAIR_WIDTH                      1
+#define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK                        0x80u
+#define DMA_CINT_NOP_SHIFT                       7
+#define DMA_CINT_NOP_WIDTH                       1
+#define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK                        0x1u
+#define DMA_INT_INT0_SHIFT                       0
+#define DMA_INT_INT0_WIDTH                       1
+#define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK                        0x2u
+#define DMA_INT_INT1_SHIFT                       1
+#define DMA_INT_INT1_WIDTH                       1
+#define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK                        0x4u
+#define DMA_INT_INT2_SHIFT                       2
+#define DMA_INT_INT2_WIDTH                       1
+#define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK                        0x8u
+#define DMA_INT_INT3_SHIFT                       3
+#define DMA_INT_INT3_WIDTH                       1
+#define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK                        0x10u
+#define DMA_INT_INT4_SHIFT                       4
+#define DMA_INT_INT4_WIDTH                       1
+#define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK                        0x20u
+#define DMA_INT_INT5_SHIFT                       5
+#define DMA_INT_INT5_WIDTH                       1
+#define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK                        0x40u
+#define DMA_INT_INT6_SHIFT                       6
+#define DMA_INT_INT6_WIDTH                       1
+#define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK                        0x80u
+#define DMA_INT_INT7_SHIFT                       7
+#define DMA_INT_INT7_WIDTH                       1
+#define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK                        0x100u
+#define DMA_INT_INT8_SHIFT                       8
+#define DMA_INT_INT8_WIDTH                       1
+#define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK                        0x200u
+#define DMA_INT_INT9_SHIFT                       9
+#define DMA_INT_INT9_WIDTH                       1
+#define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK                       0x400u
+#define DMA_INT_INT10_SHIFT                      10
+#define DMA_INT_INT10_WIDTH                      1
+#define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK                       0x800u
+#define DMA_INT_INT11_SHIFT                      11
+#define DMA_INT_INT11_WIDTH                      1
+#define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK                       0x1000u
+#define DMA_INT_INT12_SHIFT                      12
+#define DMA_INT_INT12_WIDTH                      1
+#define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK                       0x2000u
+#define DMA_INT_INT13_SHIFT                      13
+#define DMA_INT_INT13_WIDTH                      1
+#define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK                       0x4000u
+#define DMA_INT_INT14_SHIFT                      14
+#define DMA_INT_INT14_WIDTH                      1
+#define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK                       0x8000u
+#define DMA_INT_INT15_SHIFT                      15
+#define DMA_INT_INT15_WIDTH                      1
+#define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK                        0x1u
+#define DMA_ERR_ERR0_SHIFT                       0
+#define DMA_ERR_ERR0_WIDTH                       1
+#define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK                        0x2u
+#define DMA_ERR_ERR1_SHIFT                       1
+#define DMA_ERR_ERR1_WIDTH                       1
+#define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK                        0x4u
+#define DMA_ERR_ERR2_SHIFT                       2
+#define DMA_ERR_ERR2_WIDTH                       1
+#define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK                        0x8u
+#define DMA_ERR_ERR3_SHIFT                       3
+#define DMA_ERR_ERR3_WIDTH                       1
+#define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK                        0x10u
+#define DMA_ERR_ERR4_SHIFT                       4
+#define DMA_ERR_ERR4_WIDTH                       1
+#define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK                        0x20u
+#define DMA_ERR_ERR5_SHIFT                       5
+#define DMA_ERR_ERR5_WIDTH                       1
+#define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK                        0x40u
+#define DMA_ERR_ERR6_SHIFT                       6
+#define DMA_ERR_ERR6_WIDTH                       1
+#define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK                        0x80u
+#define DMA_ERR_ERR7_SHIFT                       7
+#define DMA_ERR_ERR7_WIDTH                       1
+#define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK                        0x100u
+#define DMA_ERR_ERR8_SHIFT                       8
+#define DMA_ERR_ERR8_WIDTH                       1
+#define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK                        0x200u
+#define DMA_ERR_ERR9_SHIFT                       9
+#define DMA_ERR_ERR9_WIDTH                       1
+#define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK                       0x400u
+#define DMA_ERR_ERR10_SHIFT                      10
+#define DMA_ERR_ERR10_WIDTH                      1
+#define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK                       0x800u
+#define DMA_ERR_ERR11_SHIFT                      11
+#define DMA_ERR_ERR11_WIDTH                      1
+#define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK                       0x1000u
+#define DMA_ERR_ERR12_SHIFT                      12
+#define DMA_ERR_ERR12_WIDTH                      1
+#define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK                       0x2000u
+#define DMA_ERR_ERR13_SHIFT                      13
+#define DMA_ERR_ERR13_WIDTH                      1
+#define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK                       0x4000u
+#define DMA_ERR_ERR14_SHIFT                      14
+#define DMA_ERR_ERR14_WIDTH                      1
+#define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK                       0x8000u
+#define DMA_ERR_ERR15_SHIFT                      15
+#define DMA_ERR_ERR15_WIDTH                      1
+#define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK                        0x1u
+#define DMA_HRS_HRS0_SHIFT                       0
+#define DMA_HRS_HRS0_WIDTH                       1
+#define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK                        0x2u
+#define DMA_HRS_HRS1_SHIFT                       1
+#define DMA_HRS_HRS1_WIDTH                       1
+#define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK                        0x4u
+#define DMA_HRS_HRS2_SHIFT                       2
+#define DMA_HRS_HRS2_WIDTH                       1
+#define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK                        0x8u
+#define DMA_HRS_HRS3_SHIFT                       3
+#define DMA_HRS_HRS3_WIDTH                       1
+#define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK                        0x10u
+#define DMA_HRS_HRS4_SHIFT                       4
+#define DMA_HRS_HRS4_WIDTH                       1
+#define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK                        0x20u
+#define DMA_HRS_HRS5_SHIFT                       5
+#define DMA_HRS_HRS5_WIDTH                       1
+#define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK                        0x40u
+#define DMA_HRS_HRS6_SHIFT                       6
+#define DMA_HRS_HRS6_WIDTH                       1
+#define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK                        0x80u
+#define DMA_HRS_HRS7_SHIFT                       7
+#define DMA_HRS_HRS7_WIDTH                       1
+#define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK                        0x100u
+#define DMA_HRS_HRS8_SHIFT                       8
+#define DMA_HRS_HRS8_WIDTH                       1
+#define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK                        0x200u
+#define DMA_HRS_HRS9_SHIFT                       9
+#define DMA_HRS_HRS9_WIDTH                       1
+#define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK                       0x400u
+#define DMA_HRS_HRS10_SHIFT                      10
+#define DMA_HRS_HRS10_WIDTH                      1
+#define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK                       0x800u
+#define DMA_HRS_HRS11_SHIFT                      11
+#define DMA_HRS_HRS11_WIDTH                      1
+#define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK                       0x1000u
+#define DMA_HRS_HRS12_SHIFT                      12
+#define DMA_HRS_HRS12_WIDTH                      1
+#define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK                       0x2000u
+#define DMA_HRS_HRS13_SHIFT                      13
+#define DMA_HRS_HRS13_WIDTH                      1
+#define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK                       0x4000u
+#define DMA_HRS_HRS14_SHIFT                      14
+#define DMA_HRS_HRS14_WIDTH                      1
+#define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK                       0x8000u
+#define DMA_HRS_HRS15_SHIFT                      15
+#define DMA_HRS_HRS15_WIDTH                      1
+#define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT                  0
+#define DMA_DCHPRI3_CHPRI_WIDTH                  4
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     0x40u
+#define DMA_DCHPRI3_DPA_SHIFT                    6
+#define DMA_DCHPRI3_DPA_WIDTH                    1
+#define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_DPA_SHIFT))&DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK                     0x80u
+#define DMA_DCHPRI3_ECP_SHIFT                    7
+#define DMA_DCHPRI3_ECP_WIDTH                    1
+#define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_ECP_SHIFT))&DMA_DCHPRI3_ECP_MASK)
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT                  0
+#define DMA_DCHPRI2_CHPRI_WIDTH                  4
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     0x40u
+#define DMA_DCHPRI2_DPA_SHIFT                    6
+#define DMA_DCHPRI2_DPA_WIDTH                    1
+#define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_DPA_SHIFT))&DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK                     0x80u
+#define DMA_DCHPRI2_ECP_SHIFT                    7
+#define DMA_DCHPRI2_ECP_WIDTH                    1
+#define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_ECP_SHIFT))&DMA_DCHPRI2_ECP_MASK)
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT                  0
+#define DMA_DCHPRI1_CHPRI_WIDTH                  4
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     0x40u
+#define DMA_DCHPRI1_DPA_SHIFT                    6
+#define DMA_DCHPRI1_DPA_WIDTH                    1
+#define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_DPA_SHIFT))&DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK                     0x80u
+#define DMA_DCHPRI1_ECP_SHIFT                    7
+#define DMA_DCHPRI1_ECP_WIDTH                    1
+#define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_ECP_SHIFT))&DMA_DCHPRI1_ECP_MASK)
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT                  0
+#define DMA_DCHPRI0_CHPRI_WIDTH                  4
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     0x40u
+#define DMA_DCHPRI0_DPA_SHIFT                    6
+#define DMA_DCHPRI0_DPA_WIDTH                    1
+#define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_DPA_SHIFT))&DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK                     0x80u
+#define DMA_DCHPRI0_ECP_SHIFT                    7
+#define DMA_DCHPRI0_ECP_WIDTH                    1
+#define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_ECP_SHIFT))&DMA_DCHPRI0_ECP_MASK)
+/* DCHPRI7 Bit Fields */
+#define DMA_DCHPRI7_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI7_CHPRI_SHIFT                  0
+#define DMA_DCHPRI7_CHPRI_WIDTH                  4
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     0x40u
+#define DMA_DCHPRI7_DPA_SHIFT                    6
+#define DMA_DCHPRI7_DPA_WIDTH                    1
+#define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_DPA_SHIFT))&DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK                     0x80u
+#define DMA_DCHPRI7_ECP_SHIFT                    7
+#define DMA_DCHPRI7_ECP_WIDTH                    1
+#define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_ECP_SHIFT))&DMA_DCHPRI7_ECP_MASK)
+/* DCHPRI6 Bit Fields */
+#define DMA_DCHPRI6_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI6_CHPRI_SHIFT                  0
+#define DMA_DCHPRI6_CHPRI_WIDTH                  4
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     0x40u
+#define DMA_DCHPRI6_DPA_SHIFT                    6
+#define DMA_DCHPRI6_DPA_WIDTH                    1
+#define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_DPA_SHIFT))&DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK                     0x80u
+#define DMA_DCHPRI6_ECP_SHIFT                    7
+#define DMA_DCHPRI6_ECP_WIDTH                    1
+#define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_ECP_SHIFT))&DMA_DCHPRI6_ECP_MASK)
+/* DCHPRI5 Bit Fields */
+#define DMA_DCHPRI5_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI5_CHPRI_SHIFT                  0
+#define DMA_DCHPRI5_CHPRI_WIDTH                  4
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     0x40u
+#define DMA_DCHPRI5_DPA_SHIFT                    6
+#define DMA_DCHPRI5_DPA_WIDTH                    1
+#define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_DPA_SHIFT))&DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK                     0x80u
+#define DMA_DCHPRI5_ECP_SHIFT                    7
+#define DMA_DCHPRI5_ECP_WIDTH                    1
+#define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_ECP_SHIFT))&DMA_DCHPRI5_ECP_MASK)
+/* DCHPRI4 Bit Fields */
+#define DMA_DCHPRI4_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI4_CHPRI_SHIFT                  0
+#define DMA_DCHPRI4_CHPRI_WIDTH                  4
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     0x40u
+#define DMA_DCHPRI4_DPA_SHIFT                    6
+#define DMA_DCHPRI4_DPA_WIDTH                    1
+#define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_DPA_SHIFT))&DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK                     0x80u
+#define DMA_DCHPRI4_ECP_SHIFT                    7
+#define DMA_DCHPRI4_ECP_WIDTH                    1
+#define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_ECP_SHIFT))&DMA_DCHPRI4_ECP_MASK)
+/* DCHPRI11 Bit Fields */
+#define DMA_DCHPRI11_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI11_CHPRI_SHIFT                 0
+#define DMA_DCHPRI11_CHPRI_WIDTH                 4
+#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK                    0x40u
+#define DMA_DCHPRI11_DPA_SHIFT                   6
+#define DMA_DCHPRI11_DPA_WIDTH                   1
+#define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_DPA_SHIFT))&DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_ECP_MASK                    0x80u
+#define DMA_DCHPRI11_ECP_SHIFT                   7
+#define DMA_DCHPRI11_ECP_WIDTH                   1
+#define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_ECP_SHIFT))&DMA_DCHPRI11_ECP_MASK)
+/* DCHPRI10 Bit Fields */
+#define DMA_DCHPRI10_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI10_CHPRI_SHIFT                 0
+#define DMA_DCHPRI10_CHPRI_WIDTH                 4
+#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK                    0x40u
+#define DMA_DCHPRI10_DPA_SHIFT                   6
+#define DMA_DCHPRI10_DPA_WIDTH                   1
+#define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_DPA_SHIFT))&DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_ECP_MASK                    0x80u
+#define DMA_DCHPRI10_ECP_SHIFT                   7
+#define DMA_DCHPRI10_ECP_WIDTH                   1
+#define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_ECP_SHIFT))&DMA_DCHPRI10_ECP_MASK)
+/* DCHPRI9 Bit Fields */
+#define DMA_DCHPRI9_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI9_CHPRI_SHIFT                  0
+#define DMA_DCHPRI9_CHPRI_WIDTH                  4
+#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK                     0x40u
+#define DMA_DCHPRI9_DPA_SHIFT                    6
+#define DMA_DCHPRI9_DPA_WIDTH                    1
+#define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_DPA_SHIFT))&DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_ECP_MASK                     0x80u
+#define DMA_DCHPRI9_ECP_SHIFT                    7
+#define DMA_DCHPRI9_ECP_WIDTH                    1
+#define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_ECP_SHIFT))&DMA_DCHPRI9_ECP_MASK)
+/* DCHPRI8 Bit Fields */
+#define DMA_DCHPRI8_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI8_CHPRI_SHIFT                  0
+#define DMA_DCHPRI8_CHPRI_WIDTH                  4
+#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK                     0x40u
+#define DMA_DCHPRI8_DPA_SHIFT                    6
+#define DMA_DCHPRI8_DPA_WIDTH                    1
+#define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_DPA_SHIFT))&DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_ECP_MASK                     0x80u
+#define DMA_DCHPRI8_ECP_SHIFT                    7
+#define DMA_DCHPRI8_ECP_WIDTH                    1
+#define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_ECP_SHIFT))&DMA_DCHPRI8_ECP_MASK)
+/* DCHPRI15 Bit Fields */
+#define DMA_DCHPRI15_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI15_CHPRI_SHIFT                 0
+#define DMA_DCHPRI15_CHPRI_WIDTH                 4
+#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK                    0x40u
+#define DMA_DCHPRI15_DPA_SHIFT                   6
+#define DMA_DCHPRI15_DPA_WIDTH                   1
+#define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_DPA_SHIFT))&DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_ECP_MASK                    0x80u
+#define DMA_DCHPRI15_ECP_SHIFT                   7
+#define DMA_DCHPRI15_ECP_WIDTH                   1
+#define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_ECP_SHIFT))&DMA_DCHPRI15_ECP_MASK)
+/* DCHPRI14 Bit Fields */
+#define DMA_DCHPRI14_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI14_CHPRI_SHIFT                 0
+#define DMA_DCHPRI14_CHPRI_WIDTH                 4
+#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK                    0x40u
+#define DMA_DCHPRI14_DPA_SHIFT                   6
+#define DMA_DCHPRI14_DPA_WIDTH                   1
+#define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_DPA_SHIFT))&DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_ECP_MASK                    0x80u
+#define DMA_DCHPRI14_ECP_SHIFT                   7
+#define DMA_DCHPRI14_ECP_WIDTH                   1
+#define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_ECP_SHIFT))&DMA_DCHPRI14_ECP_MASK)
+/* DCHPRI13 Bit Fields */
+#define DMA_DCHPRI13_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI13_CHPRI_SHIFT                 0
+#define DMA_DCHPRI13_CHPRI_WIDTH                 4
+#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK                    0x40u
+#define DMA_DCHPRI13_DPA_SHIFT                   6
+#define DMA_DCHPRI13_DPA_WIDTH                   1
+#define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_DPA_SHIFT))&DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_ECP_MASK                    0x80u
+#define DMA_DCHPRI13_ECP_SHIFT                   7
+#define DMA_DCHPRI13_ECP_WIDTH                   1
+#define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_ECP_SHIFT))&DMA_DCHPRI13_ECP_MASK)
+/* DCHPRI12 Bit Fields */
+#define DMA_DCHPRI12_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI12_CHPRI_SHIFT                 0
+#define DMA_DCHPRI12_CHPRI_WIDTH                 4
+#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK                    0x40u
+#define DMA_DCHPRI12_DPA_SHIFT                   6
+#define DMA_DCHPRI12_DPA_WIDTH                   1
+#define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_DPA_SHIFT))&DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_ECP_MASK                    0x80u
+#define DMA_DCHPRI12_ECP_SHIFT                   7
+#define DMA_DCHPRI12_ECP_WIDTH                   1
+#define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_ECP_SHIFT))&DMA_DCHPRI12_ECP_MASK)
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK                     0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT                    0
+#define DMA_SADDR_SADDR_WIDTH                    32
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK                       0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT                      0
+#define DMA_SOFF_SOFF_WIDTH                      16
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK                      0x7u
+#define DMA_ATTR_DSIZE_SHIFT                     0
+#define DMA_ATTR_DSIZE_WIDTH                     3
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       0xF8u
+#define DMA_ATTR_DMOD_SHIFT                      3
+#define DMA_ATTR_DMOD_WIDTH                      5
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      0x700u
+#define DMA_ATTR_SSIZE_SHIFT                     8
+#define DMA_ATTR_SSIZE_WIDTH                     3
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       0xF800u
+#define DMA_ATTR_SMOD_SHIFT                      11
+#define DMA_ATTR_SMOD_WIDTH                      5
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             0
+#define DMA_NBYTES_MLNO_NBYTES_WIDTH             32
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          0
+#define DMA_NBYTES_MLOFFNO_NBYTES_WIDTH          30
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           30
+#define DMA_NBYTES_MLOFFNO_DMLOE_WIDTH           1
+#define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           31
+#define DMA_NBYTES_MLOFFNO_SMLOE_WIDTH           1
+#define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         0
+#define DMA_NBYTES_MLOFFYES_NBYTES_WIDTH         10
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          10
+#define DMA_NBYTES_MLOFFYES_MLOFF_WIDTH          20
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          30
+#define DMA_NBYTES_MLOFFYES_DMLOE_WIDTH          1
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          31
+#define DMA_NBYTES_MLOFFYES_SMLOE_WIDTH          1
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK                     0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT                    0
+#define DMA_SLAST_SLAST_WIDTH                    32
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK                     0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT                    0
+#define DMA_DADDR_DADDR_WIDTH                    32
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK                       0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT                      0
+#define DMA_DOFF_DOFF_WIDTH                      16
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK             0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT            0
+#define DMA_CITER_ELINKNO_CITER_WIDTH            15
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            15
+#define DMA_CITER_ELINKNO_ELINK_WIDTH            1
+#define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_ELINK_SHIFT))&DMA_CITER_ELINKNO_ELINK_MASK)
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK            0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT           0
+#define DMA_CITER_ELINKYES_CITER_WIDTH           9
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_CITER_ELINKYES_LINKCH_WIDTH          4
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           15
+#define DMA_CITER_ELINKYES_ELINK_WIDTH           1
+#define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_ELINK_SHIFT))&DMA_CITER_ELINKYES_ELINK_MASK)
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             0
+#define DMA_DLAST_SGA_DLASTSGA_WIDTH             32
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK                       0x1u
+#define DMA_CSR_START_SHIFT                      0
+#define DMA_CSR_START_WIDTH                      1
+#define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_CSR_START_SHIFT))&DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK                    0x2u
+#define DMA_CSR_INTMAJOR_SHIFT                   1
+#define DMA_CSR_INTMAJOR_WIDTH                   1
+#define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTMAJOR_SHIFT))&DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK                     0x4u
+#define DMA_CSR_INTHALF_SHIFT                    2
+#define DMA_CSR_INTHALF_WIDTH                    1
+#define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTHALF_SHIFT))&DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK                        0x8u
+#define DMA_CSR_DREQ_SHIFT                       3
+#define DMA_CSR_DREQ_WIDTH                       1
+#define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DREQ_SHIFT))&DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK                         0x10u
+#define DMA_CSR_ESG_SHIFT                        4
+#define DMA_CSR_ESG_WIDTH                        1
+#define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ESG_SHIFT))&DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK                  0x20u
+#define DMA_CSR_MAJORELINK_SHIFT                 5
+#define DMA_CSR_MAJORELINK_WIDTH                 1
+#define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORELINK_SHIFT))&DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK                      0x40u
+#define DMA_CSR_ACTIVE_SHIFT                     6
+#define DMA_CSR_ACTIVE_WIDTH                     1
+#define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ACTIVE_SHIFT))&DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK                        0x80u
+#define DMA_CSR_DONE_SHIFT                       7
+#define DMA_CSR_DONE_WIDTH                       1
+#define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DONE_SHIFT))&DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK                 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT                8
+#define DMA_CSR_MAJORLINKCH_WIDTH                4
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         0xC000u
+#define DMA_CSR_BWC_SHIFT                        14
+#define DMA_CSR_BWC_WIDTH                        2
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK             0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT            0
+#define DMA_BITER_ELINKNO_BITER_WIDTH            15
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            15
+#define DMA_BITER_ELINKNO_ELINK_WIDTH            1
+#define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_ELINK_SHIFT))&DMA_BITER_ELINKNO_ELINK_MASK)
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK            0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT           0
+#define DMA_BITER_ELINKYES_BITER_WIDTH           9
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_BITER_ELINKYES_LINKCH_WIDTH          4
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           15
+#define DMA_BITER_ELINKYES_ELINK_WIDTH           1
+#define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_ELINK_SHIFT))&DMA_BITER_ELINKYES_ELINK_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR                             (DMA0)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- DMA - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_CR                                   DMA_CR_REG(DMA0)
+#define DMA_ES                                   DMA_ES_REG(DMA0)
+#define DMA_ERQ                                  DMA_ERQ_REG(DMA0)
+#define DMA_EEI                                  DMA_EEI_REG(DMA0)
+#define DMA_CEEI                                 DMA_CEEI_REG(DMA0)
+#define DMA_SEEI                                 DMA_SEEI_REG(DMA0)
+#define DMA_CERQ                                 DMA_CERQ_REG(DMA0)
+#define DMA_SERQ                                 DMA_SERQ_REG(DMA0)
+#define DMA_CDNE                                 DMA_CDNE_REG(DMA0)
+#define DMA_SSRT                                 DMA_SSRT_REG(DMA0)
+#define DMA_CERR                                 DMA_CERR_REG(DMA0)
+#define DMA_CINT                                 DMA_CINT_REG(DMA0)
+#define DMA_INT                                  DMA_INT_REG(DMA0)
+#define DMA_ERR                                  DMA_ERR_REG(DMA0)
+#define DMA_HRS                                  DMA_HRS_REG(DMA0)
+#define DMA_DCHPRI3                              DMA_DCHPRI3_REG(DMA0)
+#define DMA_DCHPRI2                              DMA_DCHPRI2_REG(DMA0)
+#define DMA_DCHPRI1                              DMA_DCHPRI1_REG(DMA0)
+#define DMA_DCHPRI0                              DMA_DCHPRI0_REG(DMA0)
+#define DMA_DCHPRI7                              DMA_DCHPRI7_REG(DMA0)
+#define DMA_DCHPRI6                              DMA_DCHPRI6_REG(DMA0)
+#define DMA_DCHPRI5                              DMA_DCHPRI5_REG(DMA0)
+#define DMA_DCHPRI4                              DMA_DCHPRI4_REG(DMA0)
+#define DMA_DCHPRI11                             DMA_DCHPRI11_REG(DMA0)
+#define DMA_DCHPRI10                             DMA_DCHPRI10_REG(DMA0)
+#define DMA_DCHPRI9                              DMA_DCHPRI9_REG(DMA0)
+#define DMA_DCHPRI8                              DMA_DCHPRI8_REG(DMA0)
+#define DMA_DCHPRI15                             DMA_DCHPRI15_REG(DMA0)
+#define DMA_DCHPRI14                             DMA_DCHPRI14_REG(DMA0)
+#define DMA_DCHPRI13                             DMA_DCHPRI13_REG(DMA0)
+#define DMA_DCHPRI12                             DMA_DCHPRI12_REG(DMA0)
+#define DMA_TCD0_SADDR                           DMA_SADDR_REG(DMA0,0)
+#define DMA_TCD0_SOFF                            DMA_SOFF_REG(DMA0,0)
+#define DMA_TCD0_ATTR                            DMA_ATTR_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,0)
+#define DMA_TCD0_SLAST                           DMA_SLAST_REG(DMA0,0)
+#define DMA_TCD0_DADDR                           DMA_DADDR_REG(DMA0,0)
+#define DMA_TCD0_DOFF                            DMA_DOFF_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD0_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,0)
+#define DMA_TCD0_CSR                             DMA_CSR_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD1_SADDR                           DMA_SADDR_REG(DMA0,1)
+#define DMA_TCD1_SOFF                            DMA_SOFF_REG(DMA0,1)
+#define DMA_TCD1_ATTR                            DMA_ATTR_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,1)
+#define DMA_TCD1_SLAST                           DMA_SLAST_REG(DMA0,1)
+#define DMA_TCD1_DADDR                           DMA_DADDR_REG(DMA0,1)
+#define DMA_TCD1_DOFF                            DMA_DOFF_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD1_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,1)
+#define DMA_TCD1_CSR                             DMA_CSR_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD2_SADDR                           DMA_SADDR_REG(DMA0,2)
+#define DMA_TCD2_SOFF                            DMA_SOFF_REG(DMA0,2)
+#define DMA_TCD2_ATTR                            DMA_ATTR_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,2)
+#define DMA_TCD2_SLAST                           DMA_SLAST_REG(DMA0,2)
+#define DMA_TCD2_DADDR                           DMA_DADDR_REG(DMA0,2)
+#define DMA_TCD2_DOFF                            DMA_DOFF_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD2_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,2)
+#define DMA_TCD2_CSR                             DMA_CSR_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD3_SADDR                           DMA_SADDR_REG(DMA0,3)
+#define DMA_TCD3_SOFF                            DMA_SOFF_REG(DMA0,3)
+#define DMA_TCD3_ATTR                            DMA_ATTR_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,3)
+#define DMA_TCD3_SLAST                           DMA_SLAST_REG(DMA0,3)
+#define DMA_TCD3_DADDR                           DMA_DADDR_REG(DMA0,3)
+#define DMA_TCD3_DOFF                            DMA_DOFF_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD3_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,3)
+#define DMA_TCD3_CSR                             DMA_CSR_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD4_SADDR                           DMA_SADDR_REG(DMA0,4)
+#define DMA_TCD4_SOFF                            DMA_SOFF_REG(DMA0,4)
+#define DMA_TCD4_ATTR                            DMA_ATTR_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,4)
+#define DMA_TCD4_SLAST                           DMA_SLAST_REG(DMA0,4)
+#define DMA_TCD4_DADDR                           DMA_DADDR_REG(DMA0,4)
+#define DMA_TCD4_DOFF                            DMA_DOFF_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD4_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,4)
+#define DMA_TCD4_CSR                             DMA_CSR_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD5_SADDR                           DMA_SADDR_REG(DMA0,5)
+#define DMA_TCD5_SOFF                            DMA_SOFF_REG(DMA0,5)
+#define DMA_TCD5_ATTR                            DMA_ATTR_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,5)
+#define DMA_TCD5_SLAST                           DMA_SLAST_REG(DMA0,5)
+#define DMA_TCD5_DADDR                           DMA_DADDR_REG(DMA0,5)
+#define DMA_TCD5_DOFF                            DMA_DOFF_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD5_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,5)
+#define DMA_TCD5_CSR                             DMA_CSR_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD6_SADDR                           DMA_SADDR_REG(DMA0,6)
+#define DMA_TCD6_SOFF                            DMA_SOFF_REG(DMA0,6)
+#define DMA_TCD6_ATTR                            DMA_ATTR_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,6)
+#define DMA_TCD6_SLAST                           DMA_SLAST_REG(DMA0,6)
+#define DMA_TCD6_DADDR                           DMA_DADDR_REG(DMA0,6)
+#define DMA_TCD6_DOFF                            DMA_DOFF_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD6_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,6)
+#define DMA_TCD6_CSR                             DMA_CSR_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD7_SADDR                           DMA_SADDR_REG(DMA0,7)
+#define DMA_TCD7_SOFF                            DMA_SOFF_REG(DMA0,7)
+#define DMA_TCD7_ATTR                            DMA_ATTR_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,7)
+#define DMA_TCD7_SLAST                           DMA_SLAST_REG(DMA0,7)
+#define DMA_TCD7_DADDR                           DMA_DADDR_REG(DMA0,7)
+#define DMA_TCD7_DOFF                            DMA_DOFF_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD7_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,7)
+#define DMA_TCD7_CSR                             DMA_CSR_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD8_SADDR                           DMA_SADDR_REG(DMA0,8)
+#define DMA_TCD8_SOFF                            DMA_SOFF_REG(DMA0,8)
+#define DMA_TCD8_ATTR                            DMA_ATTR_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,8)
+#define DMA_TCD8_SLAST                           DMA_SLAST_REG(DMA0,8)
+#define DMA_TCD8_DADDR                           DMA_DADDR_REG(DMA0,8)
+#define DMA_TCD8_DOFF                            DMA_DOFF_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD8_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,8)
+#define DMA_TCD8_CSR                             DMA_CSR_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD9_SADDR                           DMA_SADDR_REG(DMA0,9)
+#define DMA_TCD9_SOFF                            DMA_SOFF_REG(DMA0,9)
+#define DMA_TCD9_ATTR                            DMA_ATTR_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,9)
+#define DMA_TCD9_SLAST                           DMA_SLAST_REG(DMA0,9)
+#define DMA_TCD9_DADDR                           DMA_DADDR_REG(DMA0,9)
+#define DMA_TCD9_DOFF                            DMA_DOFF_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD9_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,9)
+#define DMA_TCD9_CSR                             DMA_CSR_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD10_SADDR                          DMA_SADDR_REG(DMA0,10)
+#define DMA_TCD10_SOFF                           DMA_SOFF_REG(DMA0,10)
+#define DMA_TCD10_ATTR                           DMA_ATTR_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,10)
+#define DMA_TCD10_SLAST                          DMA_SLAST_REG(DMA0,10)
+#define DMA_TCD10_DADDR                          DMA_DADDR_REG(DMA0,10)
+#define DMA_TCD10_DOFF                           DMA_DOFF_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD10_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,10)
+#define DMA_TCD10_CSR                            DMA_CSR_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD11_SADDR                          DMA_SADDR_REG(DMA0,11)
+#define DMA_TCD11_SOFF                           DMA_SOFF_REG(DMA0,11)
+#define DMA_TCD11_ATTR                           DMA_ATTR_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,11)
+#define DMA_TCD11_SLAST                          DMA_SLAST_REG(DMA0,11)
+#define DMA_TCD11_DADDR                          DMA_DADDR_REG(DMA0,11)
+#define DMA_TCD11_DOFF                           DMA_DOFF_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD11_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,11)
+#define DMA_TCD11_CSR                            DMA_CSR_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD12_SADDR                          DMA_SADDR_REG(DMA0,12)
+#define DMA_TCD12_SOFF                           DMA_SOFF_REG(DMA0,12)
+#define DMA_TCD12_ATTR                           DMA_ATTR_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,12)
+#define DMA_TCD12_SLAST                          DMA_SLAST_REG(DMA0,12)
+#define DMA_TCD12_DADDR                          DMA_DADDR_REG(DMA0,12)
+#define DMA_TCD12_DOFF                           DMA_DOFF_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD12_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,12)
+#define DMA_TCD12_CSR                            DMA_CSR_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD13_SADDR                          DMA_SADDR_REG(DMA0,13)
+#define DMA_TCD13_SOFF                           DMA_SOFF_REG(DMA0,13)
+#define DMA_TCD13_ATTR                           DMA_ATTR_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,13)
+#define DMA_TCD13_SLAST                          DMA_SLAST_REG(DMA0,13)
+#define DMA_TCD13_DADDR                          DMA_DADDR_REG(DMA0,13)
+#define DMA_TCD13_DOFF                           DMA_DOFF_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD13_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,13)
+#define DMA_TCD13_CSR                            DMA_CSR_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD14_SADDR                          DMA_SADDR_REG(DMA0,14)
+#define DMA_TCD14_SOFF                           DMA_SOFF_REG(DMA0,14)
+#define DMA_TCD14_ATTR                           DMA_ATTR_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,14)
+#define DMA_TCD14_SLAST                          DMA_SLAST_REG(DMA0,14)
+#define DMA_TCD14_DADDR                          DMA_DADDR_REG(DMA0,14)
+#define DMA_TCD14_DOFF                           DMA_DOFF_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD14_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,14)
+#define DMA_TCD14_CSR                            DMA_CSR_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD15_SADDR                          DMA_SADDR_REG(DMA0,15)
+#define DMA_TCD15_SOFF                           DMA_SOFF_REG(DMA0,15)
+#define DMA_TCD15_ATTR                           DMA_ATTR_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,15)
+#define DMA_TCD15_SLAST                          DMA_SLAST_REG(DMA0,15)
+#define DMA_TCD15_DADDR                          DMA_DADDR_REG(DMA0,15)
+#define DMA_TCD15_DOFF                           DMA_DOFF_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,15)
+#define DMA_TCD15_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,15)
+#define DMA_TCD15_CSR                            DMA_CSR_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,15)
+
+/* DMA - Register array accessors */
+#define DMA_SADDR(index)                         DMA_SADDR_REG(DMA0,index)
+#define DMA_SOFF(index)                          DMA_SOFF_REG(DMA0,index)
+#define DMA_ATTR(index)                          DMA_ATTR_REG(DMA0,index)
+#define DMA_NBYTES_MLNO(index)                   DMA_NBYTES_MLNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFNO(index)                DMA_NBYTES_MLOFFNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFYES(index)               DMA_NBYTES_MLOFFYES_REG(DMA0,index)
+#define DMA_SLAST(index)                         DMA_SLAST_REG(DMA0,index)
+#define DMA_DADDR(index)                         DMA_DADDR_REG(DMA0,index)
+#define DMA_DOFF(index)                          DMA_DOFF_REG(DMA0,index)
+#define DMA_CITER_ELINKNO(index)                 DMA_CITER_ELINKNO_REG(DMA0,index)
+#define DMA_CITER_ELINKYES(index)                DMA_CITER_ELINKYES_REG(DMA0,index)
+#define DMA_DLAST_SGA(index)                     DMA_DLAST_SGA_REG(DMA0,index)
+#define DMA_CSR(index)                           DMA_CSR_REG(DMA0,index)
+#define DMA_BITER_ELINKNO(index)                 DMA_BITER_ELINKNO_REG(DMA0,index)
+#define DMA_BITER_ELINKYES(index)                DMA_BITER_ELINKYES_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[16];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index)             ((base)->CHCFG[index])
+#define DMAMUX_CHCFG_COUNT                       16
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT                0
+#define DMAMUX_CHCFG_SOURCE_WIDTH                6
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT                  6
+#define DMAMUX_CHCFG_TRIG_WIDTH                  1
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT                  7
+#define DMAMUX_CHCFG_ENBL_WIDTH                  1
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE                              (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
+#define DMAMUX_BASE_PTR                          (DMAMUX)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { DMAMUX }
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX */
+#define DMAMUX_CHCFG0                            DMAMUX_CHCFG_REG(DMAMUX,0)
+#define DMAMUX_CHCFG1                            DMAMUX_CHCFG_REG(DMAMUX,1)
+#define DMAMUX_CHCFG2                            DMAMUX_CHCFG_REG(DMAMUX,2)
+#define DMAMUX_CHCFG3                            DMAMUX_CHCFG_REG(DMAMUX,3)
+#define DMAMUX_CHCFG4                            DMAMUX_CHCFG_REG(DMAMUX,4)
+#define DMAMUX_CHCFG5                            DMAMUX_CHCFG_REG(DMAMUX,5)
+#define DMAMUX_CHCFG6                            DMAMUX_CHCFG_REG(DMAMUX,6)
+#define DMAMUX_CHCFG7                            DMAMUX_CHCFG_REG(DMAMUX,7)
+#define DMAMUX_CHCFG8                            DMAMUX_CHCFG_REG(DMAMUX,8)
+#define DMAMUX_CHCFG9                            DMAMUX_CHCFG_REG(DMAMUX,9)
+#define DMAMUX_CHCFG10                           DMAMUX_CHCFG_REG(DMAMUX,10)
+#define DMAMUX_CHCFG11                           DMAMUX_CHCFG_REG(DMAMUX,11)
+#define DMAMUX_CHCFG12                           DMAMUX_CHCFG_REG(DMAMUX,12)
+#define DMAMUX_CHCFG13                           DMAMUX_CHCFG_REG(DMAMUX,13)
+#define DMAMUX_CHCFG14                           DMAMUX_CHCFG_REG(DMAMUX,14)
+#define DMAMUX_CHCFG15                           DMAMUX_CHCFG_REG(DMAMUX,15)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX_CHCFG(index)                      DMAMUX_CHCFG_REG(DMAMUX,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4];
+  __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
+  __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register, offset: 0x10 */
+  __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register, offset: 0x14 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
+  __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
+       uint8_t RESERVED_4[28];
+  __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
+       uint8_t RESERVED_5[28];
+  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
+  __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
+  __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
+       uint8_t RESERVED_8[40];
+  __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+  __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+  __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
+  __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
+       uint8_t RESERVED_9[28];
+  __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
+       uint8_t RESERVED_10[56];
+  __IO uint32_t RDSR;                              /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+  __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+  __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+  __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+  __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+  __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+  __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+  __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+  __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+  __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+  __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
+       uint8_t RESERVED_12[12];
+  __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+  __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+       uint8_t RESERVED_13[60];
+  __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
+  __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
+  __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
+  __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
+  __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
+  __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
+  __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
+  __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
+  __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
+  __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
+  __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
+  __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
+  __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
+  __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
+  __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
+  __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
+  __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
+       uint8_t RESERVED_14[4];
+  __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
+  __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
+  __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
+  __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
+  __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
+  __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
+  __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
+  __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
+       uint8_t RESERVED_15[4];
+  __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
+  __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
+       uint8_t RESERVED_16[12];
+  __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
+  __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
+  __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
+  __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
+  __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
+  __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
+  __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
+  __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
+       uint8_t RESERVED_17[4];
+  __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
+  __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
+  __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
+  __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
+  __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
+  __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
+  __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
+  __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
+  __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
+  __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
+  __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
+  __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
+  __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
+  __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
+  __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
+       uint8_t RESERVED_18[284];
+  __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
+  __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
+  __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
+  __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
+  __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
+  __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
+  __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+       uint8_t RESERVED_19[488];
+  __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
+  struct {                                         /* offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+  } CHANNEL[4];
+} ENET_Type, *ENET_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register accessors */
+#define ENET_EIR_REG(base)                       ((base)->EIR)
+#define ENET_EIMR_REG(base)                      ((base)->EIMR)
+#define ENET_RDAR_REG(base)                      ((base)->RDAR)
+#define ENET_TDAR_REG(base)                      ((base)->TDAR)
+#define ENET_ECR_REG(base)                       ((base)->ECR)
+#define ENET_MMFR_REG(base)                      ((base)->MMFR)
+#define ENET_MSCR_REG(base)                      ((base)->MSCR)
+#define ENET_MIBC_REG(base)                      ((base)->MIBC)
+#define ENET_RCR_REG(base)                       ((base)->RCR)
+#define ENET_TCR_REG(base)                       ((base)->TCR)
+#define ENET_PALR_REG(base)                      ((base)->PALR)
+#define ENET_PAUR_REG(base)                      ((base)->PAUR)
+#define ENET_OPD_REG(base)                       ((base)->OPD)
+#define ENET_IAUR_REG(base)                      ((base)->IAUR)
+#define ENET_IALR_REG(base)                      ((base)->IALR)
+#define ENET_GAUR_REG(base)                      ((base)->GAUR)
+#define ENET_GALR_REG(base)                      ((base)->GALR)
+#define ENET_TFWR_REG(base)                      ((base)->TFWR)
+#define ENET_RDSR_REG(base)                      ((base)->RDSR)
+#define ENET_TDSR_REG(base)                      ((base)->TDSR)
+#define ENET_MRBR_REG(base)                      ((base)->MRBR)
+#define ENET_RSFL_REG(base)                      ((base)->RSFL)
+#define ENET_RSEM_REG(base)                      ((base)->RSEM)
+#define ENET_RAEM_REG(base)                      ((base)->RAEM)
+#define ENET_RAFL_REG(base)                      ((base)->RAFL)
+#define ENET_TSEM_REG(base)                      ((base)->TSEM)
+#define ENET_TAEM_REG(base)                      ((base)->TAEM)
+#define ENET_TAFL_REG(base)                      ((base)->TAFL)
+#define ENET_TIPG_REG(base)                      ((base)->TIPG)
+#define ENET_FTRL_REG(base)                      ((base)->FTRL)
+#define ENET_TACC_REG(base)                      ((base)->TACC)
+#define ENET_RACC_REG(base)                      ((base)->RACC)
+#define ENET_RMON_T_PACKETS_REG(base)            ((base)->RMON_T_PACKETS)
+#define ENET_RMON_T_BC_PKT_REG(base)             ((base)->RMON_T_BC_PKT)
+#define ENET_RMON_T_MC_PKT_REG(base)             ((base)->RMON_T_MC_PKT)
+#define ENET_RMON_T_CRC_ALIGN_REG(base)          ((base)->RMON_T_CRC_ALIGN)
+#define ENET_RMON_T_UNDERSIZE_REG(base)          ((base)->RMON_T_UNDERSIZE)
+#define ENET_RMON_T_OVERSIZE_REG(base)           ((base)->RMON_T_OVERSIZE)
+#define ENET_RMON_T_FRAG_REG(base)               ((base)->RMON_T_FRAG)
+#define ENET_RMON_T_JAB_REG(base)                ((base)->RMON_T_JAB)
+#define ENET_RMON_T_COL_REG(base)                ((base)->RMON_T_COL)
+#define ENET_RMON_T_P64_REG(base)                ((base)->RMON_T_P64)
+#define ENET_RMON_T_P65TO127_REG(base)           ((base)->RMON_T_P65TO127)
+#define ENET_RMON_T_P128TO255_REG(base)          ((base)->RMON_T_P128TO255)
+#define ENET_RMON_T_P256TO511_REG(base)          ((base)->RMON_T_P256TO511)
+#define ENET_RMON_T_P512TO1023_REG(base)         ((base)->RMON_T_P512TO1023)
+#define ENET_RMON_T_P1024TO2047_REG(base)        ((base)->RMON_T_P1024TO2047)
+#define ENET_RMON_T_P_GTE2048_REG(base)          ((base)->RMON_T_P_GTE2048)
+#define ENET_RMON_T_OCTETS_REG(base)             ((base)->RMON_T_OCTETS)
+#define ENET_IEEE_T_FRAME_OK_REG(base)           ((base)->IEEE_T_FRAME_OK)
+#define ENET_IEEE_T_1COL_REG(base)               ((base)->IEEE_T_1COL)
+#define ENET_IEEE_T_MCOL_REG(base)               ((base)->IEEE_T_MCOL)
+#define ENET_IEEE_T_DEF_REG(base)                ((base)->IEEE_T_DEF)
+#define ENET_IEEE_T_LCOL_REG(base)               ((base)->IEEE_T_LCOL)
+#define ENET_IEEE_T_EXCOL_REG(base)              ((base)->IEEE_T_EXCOL)
+#define ENET_IEEE_T_MACERR_REG(base)             ((base)->IEEE_T_MACERR)
+#define ENET_IEEE_T_CSERR_REG(base)              ((base)->IEEE_T_CSERR)
+#define ENET_IEEE_T_FDXFC_REG(base)              ((base)->IEEE_T_FDXFC)
+#define ENET_IEEE_T_OCTETS_OK_REG(base)          ((base)->IEEE_T_OCTETS_OK)
+#define ENET_RMON_R_PACKETS_REG(base)            ((base)->RMON_R_PACKETS)
+#define ENET_RMON_R_BC_PKT_REG(base)             ((base)->RMON_R_BC_PKT)
+#define ENET_RMON_R_MC_PKT_REG(base)             ((base)->RMON_R_MC_PKT)
+#define ENET_RMON_R_CRC_ALIGN_REG(base)          ((base)->RMON_R_CRC_ALIGN)
+#define ENET_RMON_R_UNDERSIZE_REG(base)          ((base)->RMON_R_UNDERSIZE)
+#define ENET_RMON_R_OVERSIZE_REG(base)           ((base)->RMON_R_OVERSIZE)
+#define ENET_RMON_R_FRAG_REG(base)               ((base)->RMON_R_FRAG)
+#define ENET_RMON_R_JAB_REG(base)                ((base)->RMON_R_JAB)
+#define ENET_RMON_R_P64_REG(base)                ((base)->RMON_R_P64)
+#define ENET_RMON_R_P65TO127_REG(base)           ((base)->RMON_R_P65TO127)
+#define ENET_RMON_R_P128TO255_REG(base)          ((base)->RMON_R_P128TO255)
+#define ENET_RMON_R_P256TO511_REG(base)          ((base)->RMON_R_P256TO511)
+#define ENET_RMON_R_P512TO1023_REG(base)         ((base)->RMON_R_P512TO1023)
+#define ENET_RMON_R_P1024TO2047_REG(base)        ((base)->RMON_R_P1024TO2047)
+#define ENET_RMON_R_P_GTE2048_REG(base)          ((base)->RMON_R_P_GTE2048)
+#define ENET_RMON_R_OCTETS_REG(base)             ((base)->RMON_R_OCTETS)
+#define ENET_IEEE_R_DROP_REG(base)               ((base)->IEEE_R_DROP)
+#define ENET_IEEE_R_FRAME_OK_REG(base)           ((base)->IEEE_R_FRAME_OK)
+#define ENET_IEEE_R_CRC_REG(base)                ((base)->IEEE_R_CRC)
+#define ENET_IEEE_R_ALIGN_REG(base)              ((base)->IEEE_R_ALIGN)
+#define ENET_IEEE_R_MACERR_REG(base)             ((base)->IEEE_R_MACERR)
+#define ENET_IEEE_R_FDXFC_REG(base)              ((base)->IEEE_R_FDXFC)
+#define ENET_IEEE_R_OCTETS_OK_REG(base)          ((base)->IEEE_R_OCTETS_OK)
+#define ENET_ATCR_REG(base)                      ((base)->ATCR)
+#define ENET_ATVR_REG(base)                      ((base)->ATVR)
+#define ENET_ATOFF_REG(base)                     ((base)->ATOFF)
+#define ENET_ATPER_REG(base)                     ((base)->ATPER)
+#define ENET_ATCOR_REG(base)                     ((base)->ATCOR)
+#define ENET_ATINC_REG(base)                     ((base)->ATINC)
+#define ENET_ATSTMP_REG(base)                    ((base)->ATSTMP)
+#define ENET_TGSR_REG(base)                      ((base)->TGSR)
+#define ENET_TCSR_REG(base,index)                ((base)->CHANNEL[index].TCSR)
+#define ENET_TCSR_COUNT                          4
+#define ENET_TCCR_REG(base,index)                ((base)->CHANNEL[index].TCCR)
+#define ENET_TCCR_COUNT                          4
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/* EIR Bit Fields */
+#define ENET_EIR_TS_TIMER_MASK                   0x8000u
+#define ENET_EIR_TS_TIMER_SHIFT                  15
+#define ENET_EIR_TS_TIMER_WIDTH                  1
+#define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_TIMER_SHIFT))&ENET_EIR_TS_TIMER_MASK)
+#define ENET_EIR_TS_AVAIL_MASK                   0x10000u
+#define ENET_EIR_TS_AVAIL_SHIFT                  16
+#define ENET_EIR_TS_AVAIL_WIDTH                  1
+#define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_AVAIL_SHIFT))&ENET_EIR_TS_AVAIL_MASK)
+#define ENET_EIR_WAKEUP_MASK                     0x20000u
+#define ENET_EIR_WAKEUP_SHIFT                    17
+#define ENET_EIR_WAKEUP_WIDTH                    1
+#define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_EIR_WAKEUP_SHIFT))&ENET_EIR_WAKEUP_MASK)
+#define ENET_EIR_PLR_MASK                        0x40000u
+#define ENET_EIR_PLR_SHIFT                       18
+#define ENET_EIR_PLR_WIDTH                       1
+#define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_PLR_SHIFT))&ENET_EIR_PLR_MASK)
+#define ENET_EIR_UN_MASK                         0x80000u
+#define ENET_EIR_UN_SHIFT                        19
+#define ENET_EIR_UN_WIDTH                        1
+#define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_UN_SHIFT))&ENET_EIR_UN_MASK)
+#define ENET_EIR_RL_MASK                         0x100000u
+#define ENET_EIR_RL_SHIFT                        20
+#define ENET_EIR_RL_WIDTH                        1
+#define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RL_SHIFT))&ENET_EIR_RL_MASK)
+#define ENET_EIR_LC_MASK                         0x200000u
+#define ENET_EIR_LC_SHIFT                        21
+#define ENET_EIR_LC_WIDTH                        1
+#define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x))<<ENET_EIR_LC_SHIFT))&ENET_EIR_LC_MASK)
+#define ENET_EIR_EBERR_MASK                      0x400000u
+#define ENET_EIR_EBERR_SHIFT                     22
+#define ENET_EIR_EBERR_WIDTH                     1
+#define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIR_EBERR_SHIFT))&ENET_EIR_EBERR_MASK)
+#define ENET_EIR_MII_MASK                        0x800000u
+#define ENET_EIR_MII_SHIFT                       23
+#define ENET_EIR_MII_WIDTH                       1
+#define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_MII_SHIFT))&ENET_EIR_MII_MASK)
+#define ENET_EIR_RXB_MASK                        0x1000000u
+#define ENET_EIR_RXB_SHIFT                       24
+#define ENET_EIR_RXB_WIDTH                       1
+#define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXB_SHIFT))&ENET_EIR_RXB_MASK)
+#define ENET_EIR_RXF_MASK                        0x2000000u
+#define ENET_EIR_RXF_SHIFT                       25
+#define ENET_EIR_RXF_WIDTH                       1
+#define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXF_SHIFT))&ENET_EIR_RXF_MASK)
+#define ENET_EIR_TXB_MASK                        0x4000000u
+#define ENET_EIR_TXB_SHIFT                       26
+#define ENET_EIR_TXB_WIDTH                       1
+#define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXB_SHIFT))&ENET_EIR_TXB_MASK)
+#define ENET_EIR_TXF_MASK                        0x8000000u
+#define ENET_EIR_TXF_SHIFT                       27
+#define ENET_EIR_TXF_WIDTH                       1
+#define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXF_SHIFT))&ENET_EIR_TXF_MASK)
+#define ENET_EIR_GRA_MASK                        0x10000000u
+#define ENET_EIR_GRA_SHIFT                       28
+#define ENET_EIR_GRA_WIDTH                       1
+#define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIR_GRA_SHIFT))&ENET_EIR_GRA_MASK)
+#define ENET_EIR_BABT_MASK                       0x20000000u
+#define ENET_EIR_BABT_SHIFT                      29
+#define ENET_EIR_BABT_WIDTH                      1
+#define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABT_SHIFT))&ENET_EIR_BABT_MASK)
+#define ENET_EIR_BABR_MASK                       0x40000000u
+#define ENET_EIR_BABR_SHIFT                      30
+#define ENET_EIR_BABR_WIDTH                      1
+#define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABR_SHIFT))&ENET_EIR_BABR_MASK)
+/* EIMR Bit Fields */
+#define ENET_EIMR_TS_TIMER_MASK                  0x8000u
+#define ENET_EIMR_TS_TIMER_SHIFT                 15
+#define ENET_EIMR_TS_TIMER_WIDTH                 1
+#define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_TIMER_SHIFT))&ENET_EIMR_TS_TIMER_MASK)
+#define ENET_EIMR_TS_AVAIL_MASK                  0x10000u
+#define ENET_EIMR_TS_AVAIL_SHIFT                 16
+#define ENET_EIMR_TS_AVAIL_WIDTH                 1
+#define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_AVAIL_SHIFT))&ENET_EIMR_TS_AVAIL_MASK)
+#define ENET_EIMR_WAKEUP_MASK                    0x20000u
+#define ENET_EIMR_WAKEUP_SHIFT                   17
+#define ENET_EIMR_WAKEUP_WIDTH                   1
+#define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_WAKEUP_SHIFT))&ENET_EIMR_WAKEUP_MASK)
+#define ENET_EIMR_PLR_MASK                       0x40000u
+#define ENET_EIMR_PLR_SHIFT                      18
+#define ENET_EIMR_PLR_WIDTH                      1
+#define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_PLR_SHIFT))&ENET_EIMR_PLR_MASK)
+#define ENET_EIMR_UN_MASK                        0x80000u
+#define ENET_EIMR_UN_SHIFT                       19
+#define ENET_EIMR_UN_WIDTH                       1
+#define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_UN_SHIFT))&ENET_EIMR_UN_MASK)
+#define ENET_EIMR_RL_MASK                        0x100000u
+#define ENET_EIMR_RL_SHIFT                       20
+#define ENET_EIMR_RL_WIDTH                       1
+#define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RL_SHIFT))&ENET_EIMR_RL_MASK)
+#define ENET_EIMR_LC_MASK                        0x200000u
+#define ENET_EIMR_LC_SHIFT                       21
+#define ENET_EIMR_LC_WIDTH                       1
+#define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_LC_SHIFT))&ENET_EIMR_LC_MASK)
+#define ENET_EIMR_EBERR_MASK                     0x400000u
+#define ENET_EIMR_EBERR_SHIFT                    22
+#define ENET_EIMR_EBERR_WIDTH                    1
+#define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_EBERR_SHIFT))&ENET_EIMR_EBERR_MASK)
+#define ENET_EIMR_MII_MASK                       0x800000u
+#define ENET_EIMR_MII_SHIFT                      23
+#define ENET_EIMR_MII_WIDTH                      1
+#define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_MII_SHIFT))&ENET_EIMR_MII_MASK)
+#define ENET_EIMR_RXB_MASK                       0x1000000u
+#define ENET_EIMR_RXB_SHIFT                      24
+#define ENET_EIMR_RXB_WIDTH                      1
+#define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXB_SHIFT))&ENET_EIMR_RXB_MASK)
+#define ENET_EIMR_RXF_MASK                       0x2000000u
+#define ENET_EIMR_RXF_SHIFT                      25
+#define ENET_EIMR_RXF_WIDTH                      1
+#define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXF_SHIFT))&ENET_EIMR_RXF_MASK)
+#define ENET_EIMR_TXB_MASK                       0x4000000u
+#define ENET_EIMR_TXB_SHIFT                      26
+#define ENET_EIMR_TXB_WIDTH                      1
+#define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXB_SHIFT))&ENET_EIMR_TXB_MASK)
+#define ENET_EIMR_TXF_MASK                       0x8000000u
+#define ENET_EIMR_TXF_SHIFT                      27
+#define ENET_EIMR_TXF_WIDTH                      1
+#define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXF_SHIFT))&ENET_EIMR_TXF_MASK)
+#define ENET_EIMR_GRA_MASK                       0x10000000u
+#define ENET_EIMR_GRA_SHIFT                      28
+#define ENET_EIMR_GRA_WIDTH                      1
+#define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_GRA_SHIFT))&ENET_EIMR_GRA_MASK)
+#define ENET_EIMR_BABT_MASK                      0x20000000u
+#define ENET_EIMR_BABT_SHIFT                     29
+#define ENET_EIMR_BABT_WIDTH                     1
+#define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABT_SHIFT))&ENET_EIMR_BABT_MASK)
+#define ENET_EIMR_BABR_MASK                      0x40000000u
+#define ENET_EIMR_BABR_SHIFT                     30
+#define ENET_EIMR_BABR_WIDTH                     1
+#define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABR_SHIFT))&ENET_EIMR_BABR_MASK)
+/* RDAR Bit Fields */
+#define ENET_RDAR_RDAR_MASK                      0x1000000u
+#define ENET_RDAR_RDAR_SHIFT                     24
+#define ENET_RDAR_RDAR_WIDTH                     1
+#define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RDAR_RDAR_SHIFT))&ENET_RDAR_RDAR_MASK)
+/* TDAR Bit Fields */
+#define ENET_TDAR_TDAR_MASK                      0x1000000u
+#define ENET_TDAR_TDAR_SHIFT                     24
+#define ENET_TDAR_TDAR_WIDTH                     1
+#define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TDAR_TDAR_SHIFT))&ENET_TDAR_TDAR_MASK)
+/* ECR Bit Fields */
+#define ENET_ECR_RESET_MASK                      0x1u
+#define ENET_ECR_RESET_SHIFT                     0
+#define ENET_ECR_RESET_WIDTH                     1
+#define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_RESET_SHIFT))&ENET_ECR_RESET_MASK)
+#define ENET_ECR_ETHEREN_MASK                    0x2u
+#define ENET_ECR_ETHEREN_SHIFT                   1
+#define ENET_ECR_ETHEREN_WIDTH                   1
+#define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ECR_ETHEREN_SHIFT))&ENET_ECR_ETHEREN_MASK)
+#define ENET_ECR_MAGICEN_MASK                    0x4u
+#define ENET_ECR_MAGICEN_SHIFT                   2
+#define ENET_ECR_MAGICEN_WIDTH                   1
+#define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ECR_MAGICEN_SHIFT))&ENET_ECR_MAGICEN_MASK)
+#define ENET_ECR_SLEEP_MASK                      0x8u
+#define ENET_ECR_SLEEP_SHIFT                     3
+#define ENET_ECR_SLEEP_WIDTH                     1
+#define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_SLEEP_SHIFT))&ENET_ECR_SLEEP_MASK)
+#define ENET_ECR_EN1588_MASK                     0x10u
+#define ENET_ECR_EN1588_SHIFT                    4
+#define ENET_ECR_EN1588_WIDTH                    1
+#define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ECR_EN1588_SHIFT))&ENET_ECR_EN1588_MASK)
+#define ENET_ECR_DBGEN_MASK                      0x40u
+#define ENET_ECR_DBGEN_SHIFT                     6
+#define ENET_ECR_DBGEN_WIDTH                     1
+#define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBGEN_SHIFT))&ENET_ECR_DBGEN_MASK)
+#define ENET_ECR_STOPEN_MASK                     0x80u
+#define ENET_ECR_STOPEN_SHIFT                    7
+#define ENET_ECR_STOPEN_WIDTH                    1
+#define ENET_ECR_STOPEN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ECR_STOPEN_SHIFT))&ENET_ECR_STOPEN_MASK)
+#define ENET_ECR_DBSWP_MASK                      0x100u
+#define ENET_ECR_DBSWP_SHIFT                     8
+#define ENET_ECR_DBSWP_WIDTH                     1
+#define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBSWP_SHIFT))&ENET_ECR_DBSWP_MASK)
+/* MMFR Bit Fields */
+#define ENET_MMFR_DATA_MASK                      0xFFFFu
+#define ENET_MMFR_DATA_SHIFT                     0
+#define ENET_MMFR_DATA_WIDTH                     16
+#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK                        0x30000u
+#define ENET_MMFR_TA_SHIFT                       16
+#define ENET_MMFR_TA_WIDTH                       2
+#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK                        0x7C0000u
+#define ENET_MMFR_RA_SHIFT                       18
+#define ENET_MMFR_RA_WIDTH                       5
+#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK                        0xF800000u
+#define ENET_MMFR_PA_SHIFT                       23
+#define ENET_MMFR_PA_WIDTH                       5
+#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK                        0x30000000u
+#define ENET_MMFR_OP_SHIFT                       28
+#define ENET_MMFR_OP_WIDTH                       2
+#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK                        0xC0000000u
+#define ENET_MMFR_ST_SHIFT                       30
+#define ENET_MMFR_ST_WIDTH                       2
+#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
+/* MSCR Bit Fields */
+#define ENET_MSCR_MII_SPEED_MASK                 0x7Eu
+#define ENET_MSCR_MII_SPEED_SHIFT                1
+#define ENET_MSCR_MII_SPEED_WIDTH                6
+#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE_MASK                   0x80u
+#define ENET_MSCR_DIS_PRE_SHIFT                  7
+#define ENET_MSCR_DIS_PRE_WIDTH                  1
+#define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_DIS_PRE_SHIFT))&ENET_MSCR_DIS_PRE_MASK)
+#define ENET_MSCR_HOLDTIME_MASK                  0x700u
+#define ENET_MSCR_HOLDTIME_SHIFT                 8
+#define ENET_MSCR_HOLDTIME_WIDTH                 3
+#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
+/* MIBC Bit Fields */
+#define ENET_MIBC_MIB_CLEAR_MASK                 0x20000000u
+#define ENET_MIBC_MIB_CLEAR_SHIFT                29
+#define ENET_MIBC_MIB_CLEAR_WIDTH                1
+#define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_CLEAR_SHIFT))&ENET_MIBC_MIB_CLEAR_MASK)
+#define ENET_MIBC_MIB_IDLE_MASK                  0x40000000u
+#define ENET_MIBC_MIB_IDLE_SHIFT                 30
+#define ENET_MIBC_MIB_IDLE_WIDTH                 1
+#define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_IDLE_SHIFT))&ENET_MIBC_MIB_IDLE_MASK)
+#define ENET_MIBC_MIB_DIS_MASK                   0x80000000u
+#define ENET_MIBC_MIB_DIS_SHIFT                  31
+#define ENET_MIBC_MIB_DIS_WIDTH                  1
+#define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_DIS_SHIFT))&ENET_MIBC_MIB_DIS_MASK)
+/* RCR Bit Fields */
+#define ENET_RCR_LOOP_MASK                       0x1u
+#define ENET_RCR_LOOP_SHIFT                      0
+#define ENET_RCR_LOOP_WIDTH                      1
+#define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_LOOP_SHIFT))&ENET_RCR_LOOP_MASK)
+#define ENET_RCR_DRT_MASK                        0x2u
+#define ENET_RCR_DRT_SHIFT                       1
+#define ENET_RCR_DRT_WIDTH                       1
+#define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_DRT_SHIFT))&ENET_RCR_DRT_MASK)
+#define ENET_RCR_MII_MODE_MASK                   0x4u
+#define ENET_RCR_MII_MODE_SHIFT                  2
+#define ENET_RCR_MII_MODE_WIDTH                  1
+#define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MII_MODE_SHIFT))&ENET_RCR_MII_MODE_MASK)
+#define ENET_RCR_PROM_MASK                       0x8u
+#define ENET_RCR_PROM_SHIFT                      3
+#define ENET_RCR_PROM_WIDTH                      1
+#define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PROM_SHIFT))&ENET_RCR_PROM_MASK)
+#define ENET_RCR_BC_REJ_MASK                     0x10u
+#define ENET_RCR_BC_REJ_SHIFT                    4
+#define ENET_RCR_BC_REJ_WIDTH                    1
+#define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_BC_REJ_SHIFT))&ENET_RCR_BC_REJ_MASK)
+#define ENET_RCR_FCE_MASK                        0x20u
+#define ENET_RCR_FCE_SHIFT                       5
+#define ENET_RCR_FCE_WIDTH                       1
+#define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_FCE_SHIFT))&ENET_RCR_FCE_MASK)
+#define ENET_RCR_RMII_MODE_MASK                  0x100u
+#define ENET_RCR_RMII_MODE_SHIFT                 8
+#define ENET_RCR_RMII_MODE_WIDTH                 1
+#define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_MODE_SHIFT))&ENET_RCR_RMII_MODE_MASK)
+#define ENET_RCR_RMII_10T_MASK                   0x200u
+#define ENET_RCR_RMII_10T_SHIFT                  9
+#define ENET_RCR_RMII_10T_WIDTH                  1
+#define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_10T_SHIFT))&ENET_RCR_RMII_10T_MASK)
+#define ENET_RCR_PADEN_MASK                      0x1000u
+#define ENET_RCR_PADEN_SHIFT                     12
+#define ENET_RCR_PADEN_WIDTH                     1
+#define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PADEN_SHIFT))&ENET_RCR_PADEN_MASK)
+#define ENET_RCR_PAUFWD_MASK                     0x2000u
+#define ENET_RCR_PAUFWD_SHIFT                    13
+#define ENET_RCR_PAUFWD_WIDTH                    1
+#define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PAUFWD_SHIFT))&ENET_RCR_PAUFWD_MASK)
+#define ENET_RCR_CRCFWD_MASK                     0x4000u
+#define ENET_RCR_CRCFWD_SHIFT                    14
+#define ENET_RCR_CRCFWD_WIDTH                    1
+#define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CRCFWD_SHIFT))&ENET_RCR_CRCFWD_MASK)
+#define ENET_RCR_CFEN_MASK                       0x8000u
+#define ENET_RCR_CFEN_SHIFT                      15
+#define ENET_RCR_CFEN_WIDTH                      1
+#define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CFEN_SHIFT))&ENET_RCR_CFEN_MASK)
+#define ENET_RCR_MAX_FL_MASK                     0x3FFF0000u
+#define ENET_RCR_MAX_FL_SHIFT                    16
+#define ENET_RCR_MAX_FL_WIDTH                    14
+#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC_MASK                        0x40000000u
+#define ENET_RCR_NLC_SHIFT                       30
+#define ENET_RCR_NLC_WIDTH                       1
+#define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_NLC_SHIFT))&ENET_RCR_NLC_MASK)
+#define ENET_RCR_GRS_MASK                        0x80000000u
+#define ENET_RCR_GRS_SHIFT                       31
+#define ENET_RCR_GRS_WIDTH                       1
+#define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_RCR_GRS_SHIFT))&ENET_RCR_GRS_MASK)
+/* TCR Bit Fields */
+#define ENET_TCR_GTS_MASK                        0x1u
+#define ENET_TCR_GTS_SHIFT                       0
+#define ENET_TCR_GTS_WIDTH                       1
+#define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_TCR_GTS_SHIFT))&ENET_TCR_GTS_MASK)
+#define ENET_TCR_FDEN_MASK                       0x4u
+#define ENET_TCR_FDEN_SHIFT                      2
+#define ENET_TCR_FDEN_WIDTH                      1
+#define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCR_FDEN_SHIFT))&ENET_TCR_FDEN_MASK)
+#define ENET_TCR_TFC_PAUSE_MASK                  0x8u
+#define ENET_TCR_TFC_PAUSE_SHIFT                 3
+#define ENET_TCR_TFC_PAUSE_WIDTH                 1
+#define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_TCR_TFC_PAUSE_SHIFT))&ENET_TCR_TFC_PAUSE_MASK)
+#define ENET_TCR_RFC_PAUSE_MASK                  0x10u
+#define ENET_TCR_RFC_PAUSE_SHIFT                 4
+#define ENET_TCR_RFC_PAUSE_WIDTH                 1
+#define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_TCR_RFC_PAUSE_SHIFT))&ENET_TCR_RFC_PAUSE_MASK)
+#define ENET_TCR_ADDSEL_MASK                     0xE0u
+#define ENET_TCR_ADDSEL_SHIFT                    5
+#define ENET_TCR_ADDSEL_WIDTH                    3
+#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS_MASK                     0x100u
+#define ENET_TCR_ADDINS_SHIFT                    8
+#define ENET_TCR_ADDINS_WIDTH                    1
+#define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDINS_SHIFT))&ENET_TCR_ADDINS_MASK)
+#define ENET_TCR_CRCFWD_MASK                     0x200u
+#define ENET_TCR_CRCFWD_SHIFT                    9
+#define ENET_TCR_CRCFWD_WIDTH                    1
+#define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCR_CRCFWD_SHIFT))&ENET_TCR_CRCFWD_MASK)
+/* PALR Bit Fields */
+#define ENET_PALR_PADDR1_MASK                    0xFFFFFFFFu
+#define ENET_PALR_PADDR1_SHIFT                   0
+#define ENET_PALR_PADDR1_WIDTH                   32
+#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
+/* PAUR Bit Fields */
+#define ENET_PAUR_TYPE_MASK                      0xFFFFu
+#define ENET_PAUR_TYPE_SHIFT                     0
+#define ENET_PAUR_TYPE_WIDTH                     16
+#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK                    0xFFFF0000u
+#define ENET_PAUR_PADDR2_SHIFT                   16
+#define ENET_PAUR_PADDR2_WIDTH                   16
+#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
+/* OPD Bit Fields */
+#define ENET_OPD_PAUSE_DUR_MASK                  0xFFFFu
+#define ENET_OPD_PAUSE_DUR_SHIFT                 0
+#define ENET_OPD_PAUSE_DUR_WIDTH                 16
+#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK                     0xFFFF0000u
+#define ENET_OPD_OPCODE_SHIFT                    16
+#define ENET_OPD_OPCODE_WIDTH                    16
+#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
+/* IAUR Bit Fields */
+#define ENET_IAUR_IADDR1_MASK                    0xFFFFFFFFu
+#define ENET_IAUR_IADDR1_SHIFT                   0
+#define ENET_IAUR_IADDR1_WIDTH                   32
+#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
+/* IALR Bit Fields */
+#define ENET_IALR_IADDR2_MASK                    0xFFFFFFFFu
+#define ENET_IALR_IADDR2_SHIFT                   0
+#define ENET_IALR_IADDR2_WIDTH                   32
+#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
+/* GAUR Bit Fields */
+#define ENET_GAUR_GADDR1_MASK                    0xFFFFFFFFu
+#define ENET_GAUR_GADDR1_SHIFT                   0
+#define ENET_GAUR_GADDR1_WIDTH                   32
+#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
+/* GALR Bit Fields */
+#define ENET_GALR_GADDR2_MASK                    0xFFFFFFFFu
+#define ENET_GALR_GADDR2_SHIFT                   0
+#define ENET_GALR_GADDR2_WIDTH                   32
+#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
+/* TFWR Bit Fields */
+#define ENET_TFWR_TFWR_MASK                      0x3Fu
+#define ENET_TFWR_TFWR_SHIFT                     0
+#define ENET_TFWR_TFWR_WIDTH                     6
+#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD_MASK                    0x100u
+#define ENET_TFWR_STRFWD_SHIFT                   8
+#define ENET_TFWR_STRFWD_WIDTH                   1
+#define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_STRFWD_SHIFT))&ENET_TFWR_STRFWD_MASK)
+/* RDSR Bit Fields */
+#define ENET_RDSR_R_DES_START_MASK               0xFFFFFFF8u
+#define ENET_RDSR_R_DES_START_SHIFT              3
+#define ENET_RDSR_R_DES_START_WIDTH              29
+#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
+/* TDSR Bit Fields */
+#define ENET_TDSR_X_DES_START_MASK               0xFFFFFFF8u
+#define ENET_TDSR_X_DES_START_SHIFT              3
+#define ENET_TDSR_X_DES_START_WIDTH              29
+#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
+/* MRBR Bit Fields */
+#define ENET_MRBR_R_BUF_SIZE_MASK                0x3FF0u
+#define ENET_MRBR_R_BUF_SIZE_SHIFT               4
+#define ENET_MRBR_R_BUF_SIZE_WIDTH               10
+#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
+/* RSFL Bit Fields */
+#define ENET_RSFL_RX_SECTION_FULL_MASK           0xFFu
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT          0
+#define ENET_RSFL_RX_SECTION_FULL_WIDTH          8
+#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
+/* RSEM Bit Fields */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         0
+#define ENET_RSEM_RX_SECTION_EMPTY_WIDTH         8
+#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK        0x1F0000u
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       16
+#define ENET_RSEM_STAT_SECTION_EMPTY_WIDTH       5
+#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+/* RAEM Bit Fields */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          0
+#define ENET_RAEM_RX_ALMOST_EMPTY_WIDTH          8
+#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+/* RAFL Bit Fields */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK            0xFFu
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           0
+#define ENET_RAFL_RX_ALMOST_FULL_WIDTH           8
+#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
+/* TSEM Bit Fields */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK          0xFFu
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         0
+#define ENET_TSEM_TX_SECTION_EMPTY_WIDTH         8
+#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
+/* TAEM Bit Fields */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           0xFFu
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          0
+#define ENET_TAEM_TX_ALMOST_EMPTY_WIDTH          8
+#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+/* TAFL Bit Fields */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK            0xFFu
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           0
+#define ENET_TAFL_TX_ALMOST_FULL_WIDTH           8
+#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
+/* TIPG Bit Fields */
+#define ENET_TIPG_IPG_MASK                       0x1Fu
+#define ENET_TIPG_IPG_SHIFT                      0
+#define ENET_TIPG_IPG_WIDTH                      5
+#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
+/* FTRL Bit Fields */
+#define ENET_FTRL_TRUNC_FL_MASK                  0x3FFFu
+#define ENET_FTRL_TRUNC_FL_SHIFT                 0
+#define ENET_FTRL_TRUNC_FL_WIDTH                 14
+#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
+/* TACC Bit Fields */
+#define ENET_TACC_SHIFT16_MASK                   0x1u
+#define ENET_TACC_SHIFT16_SHIFT                  0
+#define ENET_TACC_SHIFT16_WIDTH                  1
+#define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_TACC_SHIFT16_SHIFT))&ENET_TACC_SHIFT16_MASK)
+#define ENET_TACC_IPCHK_MASK                     0x8u
+#define ENET_TACC_IPCHK_SHIFT                    3
+#define ENET_TACC_IPCHK_WIDTH                    1
+#define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TACC_IPCHK_SHIFT))&ENET_TACC_IPCHK_MASK)
+#define ENET_TACC_PROCHK_MASK                    0x10u
+#define ENET_TACC_PROCHK_SHIFT                   4
+#define ENET_TACC_PROCHK_WIDTH                   1
+#define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_TACC_PROCHK_SHIFT))&ENET_TACC_PROCHK_MASK)
+/* RACC Bit Fields */
+#define ENET_RACC_PADREM_MASK                    0x1u
+#define ENET_RACC_PADREM_SHIFT                   0
+#define ENET_RACC_PADREM_WIDTH                   1
+#define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PADREM_SHIFT))&ENET_RACC_PADREM_MASK)
+#define ENET_RACC_IPDIS_MASK                     0x2u
+#define ENET_RACC_IPDIS_SHIFT                    1
+#define ENET_RACC_IPDIS_WIDTH                    1
+#define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_RACC_IPDIS_SHIFT))&ENET_RACC_IPDIS_MASK)
+#define ENET_RACC_PRODIS_MASK                    0x4u
+#define ENET_RACC_PRODIS_SHIFT                   2
+#define ENET_RACC_PRODIS_WIDTH                   1
+#define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PRODIS_SHIFT))&ENET_RACC_PRODIS_MASK)
+#define ENET_RACC_LINEDIS_MASK                   0x40u
+#define ENET_RACC_LINEDIS_SHIFT                  6
+#define ENET_RACC_LINEDIS_WIDTH                  1
+#define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RACC_LINEDIS_SHIFT))&ENET_RACC_LINEDIS_MASK)
+#define ENET_RACC_SHIFT16_MASK                   0x80u
+#define ENET_RACC_SHIFT16_SHIFT                  7
+#define ENET_RACC_SHIFT16_WIDTH                  1
+#define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_RACC_SHIFT16_SHIFT))&ENET_RACC_SHIFT16_MASK)
+/* RMON_T_PACKETS Bit Fields */
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK          0xFFFFu
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         0
+#define ENET_RMON_T_PACKETS_TXPKTS_WIDTH         16
+#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
+/* RMON_T_BC_PKT Bit Fields */
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           0xFFFFu
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          0
+#define ENET_RMON_T_BC_PKT_TXPKTS_WIDTH          16
+#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+/* RMON_T_MC_PKT Bit Fields */
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           0xFFFFu
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          0
+#define ENET_RMON_T_MC_PKT_TXPKTS_WIDTH          16
+#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+/* RMON_T_CRC_ALIGN Bit Fields */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       0
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_WIDTH       16
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+/* RMON_T_UNDERSIZE Bit Fields */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       0
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_WIDTH       16
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+/* RMON_T_OVERSIZE Bit Fields */
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         0xFFFFu
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        0
+#define ENET_RMON_T_OVERSIZE_TXPKTS_WIDTH        16
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+/* RMON_T_FRAG Bit Fields */
+#define ENET_RMON_T_FRAG_TXPKTS_MASK             0xFFFFu
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            0
+#define ENET_RMON_T_FRAG_TXPKTS_WIDTH            16
+#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
+/* RMON_T_JAB Bit Fields */
+#define ENET_RMON_T_JAB_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT             0
+#define ENET_RMON_T_JAB_TXPKTS_WIDTH             16
+#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
+/* RMON_T_COL Bit Fields */
+#define ENET_RMON_T_COL_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_COL_TXPKTS_SHIFT             0
+#define ENET_RMON_T_COL_TXPKTS_WIDTH             16
+#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
+/* RMON_T_P64 Bit Fields */
+#define ENET_RMON_T_P64_TXPKTS_MASK              0xFFFFu
+#define ENET_RMON_T_P64_TXPKTS_SHIFT             0
+#define ENET_RMON_T_P64_TXPKTS_WIDTH             16
+#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
+/* RMON_T_P65TO127 Bit Fields */
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK         0xFFFFu
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        0
+#define ENET_RMON_T_P65TO127_TXPKTS_WIDTH        16
+#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
+/* RMON_T_P128TO255 Bit Fields */
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P128TO255_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
+/* RMON_T_P256TO511 Bit Fields */
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P256TO511_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
+/* RMON_T_P512TO1023 Bit Fields */
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       0xFFFFu
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      0
+#define ENET_RMON_T_P512TO1023_TXPKTS_WIDTH      16
+#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+/* RMON_T_P1024TO2047 Bit Fields */
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      0xFFFFu
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     0
+#define ENET_RMON_T_P1024TO2047_TXPKTS_WIDTH     16
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+/* RMON_T_P_GTE2048 Bit Fields */
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        0xFFFFu
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       0
+#define ENET_RMON_T_P_GTE2048_TXPKTS_WIDTH       16
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+/* RMON_T_OCTETS Bit Fields */
+#define ENET_RMON_T_OCTETS_TXOCTS_MASK           0xFFFFFFFFu
+#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          0
+#define ENET_RMON_T_OCTETS_TXOCTS_WIDTH          32
+#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
+/* IEEE_T_FRAME_OK Bit Fields */
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          0xFFFFu
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         0
+#define ENET_IEEE_T_FRAME_OK_COUNT_WIDTH         16
+#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+/* IEEE_T_1COL Bit Fields */
+#define ENET_IEEE_T_1COL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_1COL_COUNT_SHIFT             0
+#define ENET_IEEE_T_1COL_COUNT_WIDTH             16
+#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
+/* IEEE_T_MCOL Bit Fields */
+#define ENET_IEEE_T_MCOL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT             0
+#define ENET_IEEE_T_MCOL_COUNT_WIDTH             16
+#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
+/* IEEE_T_DEF Bit Fields */
+#define ENET_IEEE_T_DEF_COUNT_MASK               0xFFFFu
+#define ENET_IEEE_T_DEF_COUNT_SHIFT              0
+#define ENET_IEEE_T_DEF_COUNT_WIDTH              16
+#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
+/* IEEE_T_LCOL Bit Fields */
+#define ENET_IEEE_T_LCOL_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT             0
+#define ENET_IEEE_T_LCOL_COUNT_WIDTH             16
+#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
+/* IEEE_T_EXCOL Bit Fields */
+#define ENET_IEEE_T_EXCOL_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            0
+#define ENET_IEEE_T_EXCOL_COUNT_WIDTH            16
+#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
+/* IEEE_T_MACERR Bit Fields */
+#define ENET_IEEE_T_MACERR_COUNT_MASK            0xFFFFu
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT           0
+#define ENET_IEEE_T_MACERR_COUNT_WIDTH           16
+#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
+/* IEEE_T_CSERR Bit Fields */
+#define ENET_IEEE_T_CSERR_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT            0
+#define ENET_IEEE_T_CSERR_COUNT_WIDTH            16
+#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
+/* IEEE_T_FDXFC Bit Fields */
+#define ENET_IEEE_T_FDXFC_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            0
+#define ENET_IEEE_T_FDXFC_COUNT_WIDTH            16
+#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
+/* IEEE_T_OCTETS_OK Bit Fields */
+#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        0
+#define ENET_IEEE_T_OCTETS_OK_COUNT_WIDTH        32
+#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+/* RMON_R_PACKETS Bit Fields */
+#define ENET_RMON_R_PACKETS_COUNT_MASK           0xFFFFu
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT          0
+#define ENET_RMON_R_PACKETS_COUNT_WIDTH          16
+#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
+/* RMON_R_BC_PKT Bit Fields */
+#define ENET_RMON_R_BC_PKT_COUNT_MASK            0xFFFFu
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           0
+#define ENET_RMON_R_BC_PKT_COUNT_WIDTH           16
+#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
+/* RMON_R_MC_PKT Bit Fields */
+#define ENET_RMON_R_MC_PKT_COUNT_MASK            0xFFFFu
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           0
+#define ENET_RMON_R_MC_PKT_COUNT_WIDTH           16
+#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
+/* RMON_R_CRC_ALIGN Bit Fields */
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        0
+#define ENET_RMON_R_CRC_ALIGN_COUNT_WIDTH        16
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+/* RMON_R_UNDERSIZE Bit Fields */
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        0
+#define ENET_RMON_R_UNDERSIZE_COUNT_WIDTH        16
+#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+/* RMON_R_OVERSIZE Bit Fields */
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK          0xFFFFu
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         0
+#define ENET_RMON_R_OVERSIZE_COUNT_WIDTH         16
+#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
+/* RMON_R_FRAG Bit Fields */
+#define ENET_RMON_R_FRAG_COUNT_MASK              0xFFFFu
+#define ENET_RMON_R_FRAG_COUNT_SHIFT             0
+#define ENET_RMON_R_FRAG_COUNT_WIDTH             16
+#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
+/* RMON_R_JAB Bit Fields */
+#define ENET_RMON_R_JAB_COUNT_MASK               0xFFFFu
+#define ENET_RMON_R_JAB_COUNT_SHIFT              0
+#define ENET_RMON_R_JAB_COUNT_WIDTH              16
+#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
+/* RMON_R_P64 Bit Fields */
+#define ENET_RMON_R_P64_COUNT_MASK               0xFFFFu
+#define ENET_RMON_R_P64_COUNT_SHIFT              0
+#define ENET_RMON_R_P64_COUNT_WIDTH              16
+#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
+/* RMON_R_P65TO127 Bit Fields */
+#define ENET_RMON_R_P65TO127_COUNT_MASK          0xFFFFu
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT         0
+#define ENET_RMON_R_P65TO127_COUNT_WIDTH         16
+#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
+/* RMON_R_P128TO255 Bit Fields */
+#define ENET_RMON_R_P128TO255_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT        0
+#define ENET_RMON_R_P128TO255_COUNT_WIDTH        16
+#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
+/* RMON_R_P256TO511 Bit Fields */
+#define ENET_RMON_R_P256TO511_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT        0
+#define ENET_RMON_R_P256TO511_COUNT_WIDTH        16
+#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
+/* RMON_R_P512TO1023 Bit Fields */
+#define ENET_RMON_R_P512TO1023_COUNT_MASK        0xFFFFu
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       0
+#define ENET_RMON_R_P512TO1023_COUNT_WIDTH       16
+#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
+/* RMON_R_P1024TO2047 Bit Fields */
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK       0xFFFFu
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      0
+#define ENET_RMON_R_P1024TO2047_COUNT_WIDTH      16
+#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
+/* RMON_R_P_GTE2048 Bit Fields */
+#define ENET_RMON_R_P_GTE2048_COUNT_MASK         0xFFFFu
+#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        0
+#define ENET_RMON_R_P_GTE2048_COUNT_WIDTH        16
+#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
+/* RMON_R_OCTETS Bit Fields */
+#define ENET_RMON_R_OCTETS_COUNT_MASK            0xFFFFFFFFu
+#define ENET_RMON_R_OCTETS_COUNT_SHIFT           0
+#define ENET_RMON_R_OCTETS_COUNT_WIDTH           32
+#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
+/* IEEE_R_DROP Bit Fields */
+#define ENET_IEEE_R_DROP_COUNT_MASK              0xFFFFu
+#define ENET_IEEE_R_DROP_COUNT_SHIFT             0
+#define ENET_IEEE_R_DROP_COUNT_WIDTH             16
+#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
+/* IEEE_R_FRAME_OK Bit Fields */
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          0xFFFFu
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         0
+#define ENET_IEEE_R_FRAME_OK_COUNT_WIDTH         16
+#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+/* IEEE_R_CRC Bit Fields */
+#define ENET_IEEE_R_CRC_COUNT_MASK               0xFFFFu
+#define ENET_IEEE_R_CRC_COUNT_SHIFT              0
+#define ENET_IEEE_R_CRC_COUNT_WIDTH              16
+#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
+/* IEEE_R_ALIGN Bit Fields */
+#define ENET_IEEE_R_ALIGN_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            0
+#define ENET_IEEE_R_ALIGN_COUNT_WIDTH            16
+#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
+/* IEEE_R_MACERR Bit Fields */
+#define ENET_IEEE_R_MACERR_COUNT_MASK            0xFFFFu
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT           0
+#define ENET_IEEE_R_MACERR_COUNT_WIDTH           16
+#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
+/* IEEE_R_FDXFC Bit Fields */
+#define ENET_IEEE_R_FDXFC_COUNT_MASK             0xFFFFu
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            0
+#define ENET_IEEE_R_FDXFC_COUNT_WIDTH            16
+#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
+/* IEEE_R_OCTETS_OK Bit Fields */
+#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         0xFFFFFFFFu
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        0
+#define ENET_IEEE_R_OCTETS_OK_COUNT_WIDTH        32
+#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+/* ATCR Bit Fields */
+#define ENET_ATCR_EN_MASK                        0x1u
+#define ENET_ATCR_EN_SHIFT                       0
+#define ENET_ATCR_EN_WIDTH                       1
+#define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_EN_SHIFT))&ENET_ATCR_EN_MASK)
+#define ENET_ATCR_OFFEN_MASK                     0x4u
+#define ENET_ATCR_OFFEN_SHIFT                    2
+#define ENET_ATCR_OFFEN_WIDTH                    1
+#define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFEN_SHIFT))&ENET_ATCR_OFFEN_MASK)
+#define ENET_ATCR_OFFRST_MASK                    0x8u
+#define ENET_ATCR_OFFRST_SHIFT                   3
+#define ENET_ATCR_OFFRST_WIDTH                   1
+#define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFRST_SHIFT))&ENET_ATCR_OFFRST_MASK)
+#define ENET_ATCR_PEREN_MASK                     0x10u
+#define ENET_ATCR_PEREN_SHIFT                    4
+#define ENET_ATCR_PEREN_WIDTH                    1
+#define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PEREN_SHIFT))&ENET_ATCR_PEREN_MASK)
+#define ENET_ATCR_PINPER_MASK                    0x80u
+#define ENET_ATCR_PINPER_SHIFT                   7
+#define ENET_ATCR_PINPER_WIDTH                   1
+#define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PINPER_SHIFT))&ENET_ATCR_PINPER_MASK)
+#define ENET_ATCR_RESTART_MASK                   0x200u
+#define ENET_ATCR_RESTART_SHIFT                  9
+#define ENET_ATCR_RESTART_WIDTH                  1
+#define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_RESTART_SHIFT))&ENET_ATCR_RESTART_MASK)
+#define ENET_ATCR_CAPTURE_MASK                   0x800u
+#define ENET_ATCR_CAPTURE_SHIFT                  11
+#define ENET_ATCR_CAPTURE_WIDTH                  1
+#define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_CAPTURE_SHIFT))&ENET_ATCR_CAPTURE_MASK)
+#define ENET_ATCR_SLAVE_MASK                     0x2000u
+#define ENET_ATCR_SLAVE_SHIFT                    13
+#define ENET_ATCR_SLAVE_WIDTH                    1
+#define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_SLAVE_SHIFT))&ENET_ATCR_SLAVE_MASK)
+/* ATVR Bit Fields */
+#define ENET_ATVR_ATIME_MASK                     0xFFFFFFFFu
+#define ENET_ATVR_ATIME_SHIFT                    0
+#define ENET_ATVR_ATIME_WIDTH                    32
+#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
+/* ATOFF Bit Fields */
+#define ENET_ATOFF_OFFSET_MASK                   0xFFFFFFFFu
+#define ENET_ATOFF_OFFSET_SHIFT                  0
+#define ENET_ATOFF_OFFSET_WIDTH                  32
+#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
+/* ATPER Bit Fields */
+#define ENET_ATPER_PERIOD_MASK                   0xFFFFFFFFu
+#define ENET_ATPER_PERIOD_SHIFT                  0
+#define ENET_ATPER_PERIOD_WIDTH                  32
+#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
+/* ATCOR Bit Fields */
+#define ENET_ATCOR_COR_MASK                      0x7FFFFFFFu
+#define ENET_ATCOR_COR_SHIFT                     0
+#define ENET_ATCOR_COR_WIDTH                     31
+#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
+/* ATINC Bit Fields */
+#define ENET_ATINC_INC_MASK                      0x7Fu
+#define ENET_ATINC_INC_SHIFT                     0
+#define ENET_ATINC_INC_WIDTH                     7
+#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK                 0x7F00u
+#define ENET_ATINC_INC_CORR_SHIFT                8
+#define ENET_ATINC_INC_CORR_WIDTH                7
+#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
+/* ATSTMP Bit Fields */
+#define ENET_ATSTMP_TIMESTAMP_MASK               0xFFFFFFFFu
+#define ENET_ATSTMP_TIMESTAMP_SHIFT              0
+#define ENET_ATSTMP_TIMESTAMP_WIDTH              32
+#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
+/* TGSR Bit Fields */
+#define ENET_TGSR_TF0_MASK                       0x1u
+#define ENET_TGSR_TF0_SHIFT                      0
+#define ENET_TGSR_TF0_WIDTH                      1
+#define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF0_SHIFT))&ENET_TGSR_TF0_MASK)
+#define ENET_TGSR_TF1_MASK                       0x2u
+#define ENET_TGSR_TF1_SHIFT                      1
+#define ENET_TGSR_TF1_WIDTH                      1
+#define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF1_SHIFT))&ENET_TGSR_TF1_MASK)
+#define ENET_TGSR_TF2_MASK                       0x4u
+#define ENET_TGSR_TF2_SHIFT                      2
+#define ENET_TGSR_TF2_WIDTH                      1
+#define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF2_SHIFT))&ENET_TGSR_TF2_MASK)
+#define ENET_TGSR_TF3_MASK                       0x8u
+#define ENET_TGSR_TF3_SHIFT                      3
+#define ENET_TGSR_TF3_WIDTH                      1
+#define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF3_SHIFT))&ENET_TGSR_TF3_MASK)
+/* TCSR Bit Fields */
+#define ENET_TCSR_TDRE_MASK                      0x1u
+#define ENET_TCSR_TDRE_SHIFT                     0
+#define ENET_TCSR_TDRE_WIDTH                     1
+#define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TDRE_SHIFT))&ENET_TCSR_TDRE_MASK)
+#define ENET_TCSR_TMODE_MASK                     0x3Cu
+#define ENET_TCSR_TMODE_SHIFT                    2
+#define ENET_TCSR_TMODE_WIDTH                    4
+#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE_MASK                       0x40u
+#define ENET_TCSR_TIE_SHIFT                      6
+#define ENET_TCSR_TIE_WIDTH                      1
+#define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TIE_SHIFT))&ENET_TCSR_TIE_MASK)
+#define ENET_TCSR_TF_MASK                        0x80u
+#define ENET_TCSR_TF_SHIFT                       7
+#define ENET_TCSR_TF_WIDTH                       1
+#define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TF_SHIFT))&ENET_TCSR_TF_MASK)
+/* TCCR Bit Fields */
+#define ENET_TCCR_TCC_MASK                       0xFFFFFFFFu
+#define ENET_TCCR_TCC_SHIFT                      0
+#define ENET_TCCR_TCC_WIDTH                      32
+#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE                                (0x400C0000u)
+/** Peripheral ENET base pointer */
+#define ENET                                     ((ENET_Type *)ENET_BASE)
+#define ENET_BASE_PTR                            (ENET)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS                          { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS                           { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_Transmit_IRQS                       { ENET_Transmit_IRQn }
+#define ENET_Receive_IRQS                        { ENET_Receive_IRQn }
+#define ENET_Error_IRQS                          { ENET_Error_IRQn }
+#define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- ENET - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register instance definitions */
+/* ENET */
+#define ENET_EIR                                 ENET_EIR_REG(ENET)
+#define ENET_EIMR                                ENET_EIMR_REG(ENET)
+#define ENET_RDAR                                ENET_RDAR_REG(ENET)
+#define ENET_TDAR                                ENET_TDAR_REG(ENET)
+#define ENET_ECR                                 ENET_ECR_REG(ENET)
+#define ENET_MMFR                                ENET_MMFR_REG(ENET)
+#define ENET_MSCR                                ENET_MSCR_REG(ENET)
+#define ENET_MIBC                                ENET_MIBC_REG(ENET)
+#define ENET_RCR                                 ENET_RCR_REG(ENET)
+#define ENET_TCR                                 ENET_TCR_REG(ENET)
+#define ENET_PALR                                ENET_PALR_REG(ENET)
+#define ENET_PAUR                                ENET_PAUR_REG(ENET)
+#define ENET_OPD                                 ENET_OPD_REG(ENET)
+#define ENET_IAUR                                ENET_IAUR_REG(ENET)
+#define ENET_IALR                                ENET_IALR_REG(ENET)
+#define ENET_GAUR                                ENET_GAUR_REG(ENET)
+#define ENET_GALR                                ENET_GALR_REG(ENET)
+#define ENET_TFWR                                ENET_TFWR_REG(ENET)
+#define ENET_RDSR                                ENET_RDSR_REG(ENET)
+#define ENET_TDSR                                ENET_TDSR_REG(ENET)
+#define ENET_MRBR                                ENET_MRBR_REG(ENET)
+#define ENET_RSFL                                ENET_RSFL_REG(ENET)
+#define ENET_RSEM                                ENET_RSEM_REG(ENET)
+#define ENET_RAEM                                ENET_RAEM_REG(ENET)
+#define ENET_RAFL                                ENET_RAFL_REG(ENET)
+#define ENET_TSEM                                ENET_TSEM_REG(ENET)
+#define ENET_TAEM                                ENET_TAEM_REG(ENET)
+#define ENET_TAFL                                ENET_TAFL_REG(ENET)
+#define ENET_TIPG                                ENET_TIPG_REG(ENET)
+#define ENET_FTRL                                ENET_FTRL_REG(ENET)
+#define ENET_TACC                                ENET_TACC_REG(ENET)
+#define ENET_RACC                                ENET_RACC_REG(ENET)
+#define ENET_RMON_T_PACKETS                      ENET_RMON_T_PACKETS_REG(ENET)
+#define ENET_RMON_T_BC_PKT                       ENET_RMON_T_BC_PKT_REG(ENET)
+#define ENET_RMON_T_MC_PKT                       ENET_RMON_T_MC_PKT_REG(ENET)
+#define ENET_RMON_T_CRC_ALIGN                    ENET_RMON_T_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_T_UNDERSIZE                    ENET_RMON_T_UNDERSIZE_REG(ENET)
+#define ENET_RMON_T_OVERSIZE                     ENET_RMON_T_OVERSIZE_REG(ENET)
+#define ENET_RMON_T_FRAG                         ENET_RMON_T_FRAG_REG(ENET)
+#define ENET_RMON_T_JAB                          ENET_RMON_T_JAB_REG(ENET)
+#define ENET_RMON_T_COL                          ENET_RMON_T_COL_REG(ENET)
+#define ENET_RMON_T_P64                          ENET_RMON_T_P64_REG(ENET)
+#define ENET_RMON_T_P65TO127                     ENET_RMON_T_P65TO127_REG(ENET)
+#define ENET_RMON_T_P128TO255                    ENET_RMON_T_P128TO255_REG(ENET)
+#define ENET_RMON_T_P256TO511                    ENET_RMON_T_P256TO511_REG(ENET)
+#define ENET_RMON_T_P512TO1023                   ENET_RMON_T_P512TO1023_REG(ENET)
+#define ENET_RMON_T_P1024TO2047                  ENET_RMON_T_P1024TO2047_REG(ENET)
+#define ENET_RMON_T_P_GTE2048                    ENET_RMON_T_P_GTE2048_REG(ENET)
+#define ENET_RMON_T_OCTETS                       ENET_RMON_T_OCTETS_REG(ENET)
+#define ENET_IEEE_T_FRAME_OK                     ENET_IEEE_T_FRAME_OK_REG(ENET)
+#define ENET_IEEE_T_1COL                         ENET_IEEE_T_1COL_REG(ENET)
+#define ENET_IEEE_T_MCOL                         ENET_IEEE_T_MCOL_REG(ENET)
+#define ENET_IEEE_T_DEF                          ENET_IEEE_T_DEF_REG(ENET)
+#define ENET_IEEE_T_LCOL                         ENET_IEEE_T_LCOL_REG(ENET)
+#define ENET_IEEE_T_EXCOL                        ENET_IEEE_T_EXCOL_REG(ENET)
+#define ENET_IEEE_T_MACERR                       ENET_IEEE_T_MACERR_REG(ENET)
+#define ENET_IEEE_T_CSERR                        ENET_IEEE_T_CSERR_REG(ENET)
+#define ENET_IEEE_T_FDXFC                        ENET_IEEE_T_FDXFC_REG(ENET)
+#define ENET_IEEE_T_OCTETS_OK                    ENET_IEEE_T_OCTETS_OK_REG(ENET)
+#define ENET_RMON_R_PACKETS                      ENET_RMON_R_PACKETS_REG(ENET)
+#define ENET_RMON_R_BC_PKT                       ENET_RMON_R_BC_PKT_REG(ENET)
+#define ENET_RMON_R_MC_PKT                       ENET_RMON_R_MC_PKT_REG(ENET)
+#define ENET_RMON_R_CRC_ALIGN                    ENET_RMON_R_CRC_ALIGN_REG(ENET)
+#define ENET_RMON_R_UNDERSIZE                    ENET_RMON_R_UNDERSIZE_REG(ENET)
+#define ENET_RMON_R_OVERSIZE                     ENET_RMON_R_OVERSIZE_REG(ENET)
+#define ENET_RMON_R_FRAG                         ENET_RMON_R_FRAG_REG(ENET)
+#define ENET_RMON_R_JAB                          ENET_RMON_R_JAB_REG(ENET)
+#define ENET_RMON_R_P64                          ENET_RMON_R_P64_REG(ENET)
+#define ENET_RMON_R_P65TO127                     ENET_RMON_R_P65TO127_REG(ENET)
+#define ENET_RMON_R_P128TO255                    ENET_RMON_R_P128TO255_REG(ENET)
+#define ENET_RMON_R_P256TO511                    ENET_RMON_R_P256TO511_REG(ENET)
+#define ENET_RMON_R_P512TO1023                   ENET_RMON_R_P512TO1023_REG(ENET)
+#define ENET_RMON_R_P1024TO2047                  ENET_RMON_R_P1024TO2047_REG(ENET)
+#define ENET_RMON_R_P_GTE2048                    ENET_RMON_R_P_GTE2048_REG(ENET)
+#define ENET_RMON_R_OCTETS                       ENET_RMON_R_OCTETS_REG(ENET)
+#define ENET_IEEE_R_DROP                         ENET_IEEE_R_DROP_REG(ENET)
+#define ENET_IEEE_R_FRAME_OK                     ENET_IEEE_R_FRAME_OK_REG(ENET)
+#define ENET_IEEE_R_CRC                          ENET_IEEE_R_CRC_REG(ENET)
+#define ENET_IEEE_R_ALIGN                        ENET_IEEE_R_ALIGN_REG(ENET)
+#define ENET_IEEE_R_MACERR                       ENET_IEEE_R_MACERR_REG(ENET)
+#define ENET_IEEE_R_FDXFC                        ENET_IEEE_R_FDXFC_REG(ENET)
+#define ENET_IEEE_R_OCTETS_OK                    ENET_IEEE_R_OCTETS_OK_REG(ENET)
+#define ENET_ATCR                                ENET_ATCR_REG(ENET)
+#define ENET_ATVR                                ENET_ATVR_REG(ENET)
+#define ENET_ATOFF                               ENET_ATOFF_REG(ENET)
+#define ENET_ATPER                               ENET_ATPER_REG(ENET)
+#define ENET_ATCOR                               ENET_ATCOR_REG(ENET)
+#define ENET_ATINC                               ENET_ATINC_REG(ENET)
+#define ENET_ATSTMP                              ENET_ATSTMP_REG(ENET)
+#define ENET_TGSR                                ENET_TGSR_REG(ENET)
+#define ENET_TCSR0                               ENET_TCSR_REG(ENET,0)
+#define ENET_TCCR0                               ENET_TCCR_REG(ENET,0)
+#define ENET_TCSR1                               ENET_TCSR_REG(ENET,1)
+#define ENET_TCCR1                               ENET_TCCR_REG(ENET,1)
+#define ENET_TCSR2                               ENET_TCSR_REG(ENET,2)
+#define ENET_TCCR2                               ENET_TCCR_REG(ENET,2)
+#define ENET_TCSR3                               ENET_TCSR_REG(ENET,3)
+#define ENET_TCCR3                               ENET_TCCR_REG(ENET,3)
+
+/* ENET - Register array accessors */
+#define ENET_TCSR(index)                         ENET_TCSR_REG(ENET,index)
+#define ENET_TCCR(index)                         ENET_TCCR_REG(ENET,index)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
+} EWM_Type, *EWM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register accessors */
+#define EWM_CTRL_REG(base)                       ((base)->CTRL)
+#define EWM_SERV_REG(base)                       ((base)->SERV)
+#define EWM_CMPL_REG(base)                       ((base)->CMPL)
+#define EWM_CMPH_REG(base)                       ((base)->CMPH)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK                      0x1u
+#define EWM_CTRL_EWMEN_SHIFT                     0
+#define EWM_CTRL_EWMEN_WIDTH                     1
+#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK                      0x2u
+#define EWM_CTRL_ASSIN_SHIFT                     1
+#define EWM_CTRL_ASSIN_WIDTH                     1
+#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK                       0x4u
+#define EWM_CTRL_INEN_SHIFT                      2
+#define EWM_CTRL_INEN_WIDTH                      1
+#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK                      0x8u
+#define EWM_CTRL_INTEN_SHIFT                     3
+#define EWM_CTRL_INTEN_WIDTH                     1
+#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK                    0xFFu
+#define EWM_SERV_SERVICE_SHIFT                   0
+#define EWM_SERV_SERVICE_WIDTH                   8
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK                   0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT                  0
+#define EWM_CMPL_COMPAREL_WIDTH                  8
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK                   0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT                  0
+#define EWM_CMPH_COMPAREH_WIDTH                  8
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE                                 (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM                                      ((EWM_Type *)EWM_BASE)
+#define EWM_BASE_PTR                             (EWM)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS                           { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS                            { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS                                 { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- EWM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register instance definitions */
+/* EWM */
+#define EWM_CTRL                                 EWM_CTRL_REG(EWM)
+#define EWM_SERV                                 EWM_SERV_REG(EWM)
+#define EWM_CMPL                                 EWM_CMPL_REG(EWM)
+#define EWM_CMPH                                 EWM_CMPH_REG(EWM)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0xC */
+    __IO uint32_t CSAR;                              /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+    __IO uint32_t CSMR;                              /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+    __IO uint32_t CSCR;                              /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+  } CS[6];
+       uint8_t RESERVED_0[24];
+  __IO uint32_t CSPMCR;                            /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type, *FB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register accessors */
+#define FB_CSAR_REG(base,index)                  ((base)->CS[index].CSAR)
+#define FB_CSAR_COUNT                            6
+#define FB_CSMR_REG(base,index)                  ((base)->CS[index].CSMR)
+#define FB_CSMR_COUNT                            6
+#define FB_CSCR_REG(base,index)                  ((base)->CS[index].CSCR)
+#define FB_CSCR_COUNT                            6
+#define FB_CSPMCR_REG(base)                      ((base)->CSPMCR)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK                          0xFFFF0000u
+#define FB_CSAR_BA_SHIFT                         16
+#define FB_CSAR_BA_WIDTH                         16
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
+/* CSMR Bit Fields */
+#define FB_CSMR_V_MASK                           0x1u
+#define FB_CSMR_V_SHIFT                          0
+#define FB_CSMR_V_WIDTH                          1
+#define FB_CSMR_V(x)                             (((uint32_t)(((uint32_t)(x))<<FB_CSMR_V_SHIFT))&FB_CSMR_V_MASK)
+#define FB_CSMR_WP_MASK                          0x100u
+#define FB_CSMR_WP_SHIFT                         8
+#define FB_CSMR_WP_WIDTH                         1
+#define FB_CSMR_WP(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSMR_WP_SHIFT))&FB_CSMR_WP_MASK)
+#define FB_CSMR_BAM_MASK                         0xFFFF0000u
+#define FB_CSMR_BAM_SHIFT                        16
+#define FB_CSMR_BAM_WIDTH                        16
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
+/* CSCR Bit Fields */
+#define FB_CSCR_BSTW_MASK                        0x8u
+#define FB_CSCR_BSTW_SHIFT                       3
+#define FB_CSCR_BSTW_WIDTH                       1
+#define FB_CSCR_BSTW(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTW_SHIFT))&FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTR_MASK                        0x10u
+#define FB_CSCR_BSTR_SHIFT                       4
+#define FB_CSCR_BSTR_WIDTH                       1
+#define FB_CSCR_BSTR(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTR_SHIFT))&FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BEM_MASK                         0x20u
+#define FB_CSCR_BEM_SHIFT                        5
+#define FB_CSCR_BEM_WIDTH                        1
+#define FB_CSCR_BEM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BEM_SHIFT))&FB_CSCR_BEM_MASK)
+#define FB_CSCR_PS_MASK                          0xC0u
+#define FB_CSCR_PS_SHIFT                         6
+#define FB_CSCR_PS_WIDTH                         2
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK                          0x100u
+#define FB_CSCR_AA_SHIFT                         8
+#define FB_CSCR_AA_WIDTH                         1
+#define FB_CSCR_AA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_AA_SHIFT))&FB_CSCR_AA_MASK)
+#define FB_CSCR_BLS_MASK                         0x200u
+#define FB_CSCR_BLS_SHIFT                        9
+#define FB_CSCR_BLS_WIDTH                        1
+#define FB_CSCR_BLS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BLS_SHIFT))&FB_CSCR_BLS_MASK)
+#define FB_CSCR_WS_MASK                          0xFC00u
+#define FB_CSCR_WS_SHIFT                         10
+#define FB_CSCR_WS_WIDTH                         6
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        0x30000u
+#define FB_CSCR_WRAH_SHIFT                       16
+#define FB_CSCR_WRAH_WIDTH                       2
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        0xC0000u
+#define FB_CSCR_RDAH_SHIFT                       18
+#define FB_CSCR_RDAH_WIDTH                       2
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        0x300000u
+#define FB_CSCR_ASET_SHIFT                       20
+#define FB_CSCR_ASET_WIDTH                       2
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK                        0x400000u
+#define FB_CSCR_EXTS_SHIFT                       22
+#define FB_CSCR_EXTS_WIDTH                       1
+#define FB_CSCR_EXTS(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_EXTS_SHIFT))&FB_CSCR_EXTS_MASK)
+#define FB_CSCR_SWSEN_MASK                       0x800000u
+#define FB_CSCR_SWSEN_SHIFT                      23
+#define FB_CSCR_SWSEN_WIDTH                      1
+#define FB_CSCR_SWSEN(x)                         (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWSEN_SHIFT))&FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWS_MASK                         0xFC000000u
+#define FB_CSCR_SWS_SHIFT                        26
+#define FB_CSCR_SWS_WIDTH                        6
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
+/* CSPMCR Bit Fields */
+#define FB_CSPMCR_GROUP5_MASK                    0xF000u
+#define FB_CSPMCR_GROUP5_SHIFT                   12
+#define FB_CSPMCR_GROUP5_WIDTH                   4
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    0xF0000u
+#define FB_CSPMCR_GROUP4_SHIFT                   16
+#define FB_CSPMCR_GROUP4_WIDTH                   4
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    0xF00000u
+#define FB_CSPMCR_GROUP3_SHIFT                   20
+#define FB_CSPMCR_GROUP3_WIDTH                   4
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    0xF000000u
+#define FB_CSPMCR_GROUP2_SHIFT                   24
+#define FB_CSPMCR_GROUP2_WIDTH                   4
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    0xF0000000u
+#define FB_CSPMCR_GROUP1_SHIFT                   28
+#define FB_CSPMCR_GROUP1_WIDTH                   4
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE                                  (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB                                       ((FB_Type *)FB_BASE)
+#define FB_BASE_PTR                              (FB)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS                            { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS                             { FB }
+
+/* ----------------------------------------------------------------------------
+   -- FB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register instance definitions */
+/* FB */
+#define FB_CSAR0                                 FB_CSAR_REG(FB,0)
+#define FB_CSMR0                                 FB_CSMR_REG(FB,0)
+#define FB_CSCR0                                 FB_CSCR_REG(FB,0)
+#define FB_CSAR1                                 FB_CSAR_REG(FB,1)
+#define FB_CSMR1                                 FB_CSMR_REG(FB,1)
+#define FB_CSCR1                                 FB_CSCR_REG(FB,1)
+#define FB_CSAR2                                 FB_CSAR_REG(FB,2)
+#define FB_CSMR2                                 FB_CSMR_REG(FB,2)
+#define FB_CSCR2                                 FB_CSCR_REG(FB,2)
+#define FB_CSAR3                                 FB_CSAR_REG(FB,3)
+#define FB_CSMR3                                 FB_CSMR_REG(FB,3)
+#define FB_CSCR3                                 FB_CSCR_REG(FB,3)
+#define FB_CSAR4                                 FB_CSAR_REG(FB,4)
+#define FB_CSMR4                                 FB_CSMR_REG(FB,4)
+#define FB_CSCR4                                 FB_CSCR_REG(FB,4)
+#define FB_CSAR5                                 FB_CSAR_REG(FB,5)
+#define FB_CSMR5                                 FB_CSMR_REG(FB,5)
+#define FB_CSCR5                                 FB_CSCR_REG(FB,5)
+#define FB_CSPMCR                                FB_CSPMCR_REG(FB)
+
+/* FB - Register array accessors */
+#define FB_CSAR(index)                           FB_CSAR_REG(FB,index)
+#define FB_CSMR(index)                           FB_CSMR_REG(FB,index)
+#define FB_CSCR(index)                           FB_CSCR_REG(FB,index)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PFAPR;                             /**< Flash Access Protection Register, offset: 0x0 */
+  __IO uint32_t PFB0CR;                            /**< Flash Bank 0 Control Register, offset: 0x4 */
+  __IO uint32_t PFB1CR;                            /**< Flash Bank 1 Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[244];
+  __IO uint32_t TAGVDW0S[4];                       /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+  __IO uint32_t TAGVDW1S[4];                       /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
+  __IO uint32_t TAGVDW2S[4];                       /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+  __IO uint32_t TAGVDW3S[4];                       /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
+       uint8_t RESERVED_1[192];
+  struct {                                         /* offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_U;                            /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_L;                            /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
+  } SET[4][4];
+} FMC_Type, *FMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register accessors */
+#define FMC_PFAPR_REG(base)                      ((base)->PFAPR)
+#define FMC_PFB0CR_REG(base)                     ((base)->PFB0CR)
+#define FMC_PFB1CR_REG(base)                     ((base)->PFB1CR)
+#define FMC_TAGVDW0S_REG(base,index)             ((base)->TAGVDW0S[index])
+#define FMC_TAGVDW0S_COUNT                       4
+#define FMC_TAGVDW1S_REG(base,index)             ((base)->TAGVDW1S[index])
+#define FMC_TAGVDW1S_COUNT                       4
+#define FMC_TAGVDW2S_REG(base,index)             ((base)->TAGVDW2S[index])
+#define FMC_TAGVDW2S_COUNT                       4
+#define FMC_TAGVDW3S_REG(base,index)             ((base)->TAGVDW3S[index])
+#define FMC_TAGVDW3S_COUNT                       4
+#define FMC_DATA_U_REG(base,index,index2)        ((base)->SET[index][index2].DATA_U)
+#define FMC_DATA_U_COUNT                         4
+#define FMC_DATA_U_COUNT2                        4
+#define FMC_DATA_L_REG(base,index,index2)        ((base)->SET[index][index2].DATA_L)
+#define FMC_DATA_L_COUNT                         4
+#define FMC_DATA_L_COUNT2                        4
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK                      0x3u
+#define FMC_PFAPR_M0AP_SHIFT                     0
+#define FMC_PFAPR_M0AP_WIDTH                     2
+#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK                      0xCu
+#define FMC_PFAPR_M1AP_SHIFT                     2
+#define FMC_PFAPR_M1AP_WIDTH                     2
+#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK                      0x30u
+#define FMC_PFAPR_M2AP_SHIFT                     4
+#define FMC_PFAPR_M2AP_WIDTH                     2
+#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK                      0xC0u
+#define FMC_PFAPR_M3AP_SHIFT                     6
+#define FMC_PFAPR_M3AP_WIDTH                     2
+#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK                      0x300u
+#define FMC_PFAPR_M4AP_SHIFT                     8
+#define FMC_PFAPR_M4AP_WIDTH                     2
+#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK                      0xC00u
+#define FMC_PFAPR_M5AP_SHIFT                     10
+#define FMC_PFAPR_M5AP_WIDTH                     2
+#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK                      0x3000u
+#define FMC_PFAPR_M6AP_SHIFT                     12
+#define FMC_PFAPR_M6AP_WIDTH                     2
+#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK                      0xC000u
+#define FMC_PFAPR_M7AP_SHIFT                     14
+#define FMC_PFAPR_M7AP_WIDTH                     2
+#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK                     0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT                    16
+#define FMC_PFAPR_M0PFD_WIDTH                    1
+#define FMC_PFAPR_M0PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0PFD_SHIFT))&FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK                     0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT                    17
+#define FMC_PFAPR_M1PFD_WIDTH                    1
+#define FMC_PFAPR_M1PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1PFD_SHIFT))&FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK                     0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT                    18
+#define FMC_PFAPR_M2PFD_WIDTH                    1
+#define FMC_PFAPR_M2PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2PFD_SHIFT))&FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK                     0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT                    19
+#define FMC_PFAPR_M3PFD_WIDTH                    1
+#define FMC_PFAPR_M3PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3PFD_SHIFT))&FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M4PFD_MASK                     0x100000u
+#define FMC_PFAPR_M4PFD_SHIFT                    20
+#define FMC_PFAPR_M4PFD_WIDTH                    1
+#define FMC_PFAPR_M4PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4PFD_SHIFT))&FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M5PFD_MASK                     0x200000u
+#define FMC_PFAPR_M5PFD_SHIFT                    21
+#define FMC_PFAPR_M5PFD_WIDTH                    1
+#define FMC_PFAPR_M5PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5PFD_SHIFT))&FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M6PFD_MASK                     0x400000u
+#define FMC_PFAPR_M6PFD_SHIFT                    22
+#define FMC_PFAPR_M6PFD_WIDTH                    1
+#define FMC_PFAPR_M6PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6PFD_SHIFT))&FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M7PFD_MASK                     0x800000u
+#define FMC_PFAPR_M7PFD_SHIFT                    23
+#define FMC_PFAPR_M7PFD_WIDTH                    1
+#define FMC_PFAPR_M7PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7PFD_SHIFT))&FMC_PFAPR_M7PFD_MASK)
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK                   0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT                  0
+#define FMC_PFB0CR_B0SEBE_WIDTH                  1
+#define FMC_PFB0CR_B0SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0SEBE_SHIFT))&FMC_PFB0CR_B0SEBE_MASK)
+#define FMC_PFB0CR_B0IPE_MASK                    0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT                   1
+#define FMC_PFB0CR_B0IPE_WIDTH                   1
+#define FMC_PFB0CR_B0IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0IPE_SHIFT))&FMC_PFB0CR_B0IPE_MASK)
+#define FMC_PFB0CR_B0DPE_MASK                    0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT                   2
+#define FMC_PFB0CR_B0DPE_WIDTH                   1
+#define FMC_PFB0CR_B0DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DPE_SHIFT))&FMC_PFB0CR_B0DPE_MASK)
+#define FMC_PFB0CR_B0ICE_MASK                    0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT                   3
+#define FMC_PFB0CR_B0ICE_WIDTH                   1
+#define FMC_PFB0CR_B0ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0ICE_SHIFT))&FMC_PFB0CR_B0ICE_MASK)
+#define FMC_PFB0CR_B0DCE_MASK                    0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT                   4
+#define FMC_PFB0CR_B0DCE_WIDTH                   1
+#define FMC_PFB0CR_B0DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DCE_SHIFT))&FMC_PFB0CR_B0DCE_MASK)
+#define FMC_PFB0CR_CRC_MASK                      0xE0u
+#define FMC_PFB0CR_CRC_SHIFT                     5
+#define FMC_PFB0CR_CRC_WIDTH                     3
+#define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK                     0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT                    17
+#define FMC_PFB0CR_B0MW_WIDTH                    2
+#define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK                  0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT                 19
+#define FMC_PFB0CR_S_B_INV_WIDTH                 1
+#define FMC_PFB0CR_S_B_INV(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_S_B_INV_SHIFT))&FMC_PFB0CR_S_B_INV_MASK)
+#define FMC_PFB0CR_CINV_WAY_MASK                 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT                20
+#define FMC_PFB0CR_CINV_WAY_WIDTH                4
+#define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK                 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT                24
+#define FMC_PFB0CR_CLCK_WAY_WIDTH                4
+#define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK                   0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT                  28
+#define FMC_PFB0CR_B0RWSC_WIDTH                  4
+#define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* PFB1CR Bit Fields */
+#define FMC_PFB1CR_B1SEBE_MASK                   0x1u
+#define FMC_PFB1CR_B1SEBE_SHIFT                  0
+#define FMC_PFB1CR_B1SEBE_WIDTH                  1
+#define FMC_PFB1CR_B1SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1SEBE_SHIFT))&FMC_PFB1CR_B1SEBE_MASK)
+#define FMC_PFB1CR_B1IPE_MASK                    0x2u
+#define FMC_PFB1CR_B1IPE_SHIFT                   1
+#define FMC_PFB1CR_B1IPE_WIDTH                   1
+#define FMC_PFB1CR_B1IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1IPE_SHIFT))&FMC_PFB1CR_B1IPE_MASK)
+#define FMC_PFB1CR_B1DPE_MASK                    0x4u
+#define FMC_PFB1CR_B1DPE_SHIFT                   2
+#define FMC_PFB1CR_B1DPE_WIDTH                   1
+#define FMC_PFB1CR_B1DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DPE_SHIFT))&FMC_PFB1CR_B1DPE_MASK)
+#define FMC_PFB1CR_B1ICE_MASK                    0x8u
+#define FMC_PFB1CR_B1ICE_SHIFT                   3
+#define FMC_PFB1CR_B1ICE_WIDTH                   1
+#define FMC_PFB1CR_B1ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1ICE_SHIFT))&FMC_PFB1CR_B1ICE_MASK)
+#define FMC_PFB1CR_B1DCE_MASK                    0x10u
+#define FMC_PFB1CR_B1DCE_SHIFT                   4
+#define FMC_PFB1CR_B1DCE_WIDTH                   1
+#define FMC_PFB1CR_B1DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DCE_SHIFT))&FMC_PFB1CR_B1DCE_MASK)
+#define FMC_PFB1CR_B1MW_MASK                     0x60000u
+#define FMC_PFB1CR_B1MW_SHIFT                    17
+#define FMC_PFB1CR_B1MW_WIDTH                    2
+#define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK                   0xF0000000u
+#define FMC_PFB1CR_B1RWSC_SHIFT                  28
+#define FMC_PFB1CR_B1RWSC_WIDTH                  4
+#define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
+/* TAGVDW0S Bit Fields */
+#define FMC_TAGVDW0S_valid_MASK                  0x1u
+#define FMC_TAGVDW0S_valid_SHIFT                 0
+#define FMC_TAGVDW0S_valid_WIDTH                 1
+#define FMC_TAGVDW0S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_valid_SHIFT))&FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW0S_tag_SHIFT                   5
+#define FMC_TAGVDW0S_tag_WIDTH                   14
+#define FMC_TAGVDW0S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
+/* TAGVDW1S Bit Fields */
+#define FMC_TAGVDW1S_valid_MASK                  0x1u
+#define FMC_TAGVDW1S_valid_SHIFT                 0
+#define FMC_TAGVDW1S_valid_WIDTH                 1
+#define FMC_TAGVDW1S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_valid_SHIFT))&FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW1S_tag_SHIFT                   5
+#define FMC_TAGVDW1S_tag_WIDTH                   14
+#define FMC_TAGVDW1S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
+/* TAGVDW2S Bit Fields */
+#define FMC_TAGVDW2S_valid_MASK                  0x1u
+#define FMC_TAGVDW2S_valid_SHIFT                 0
+#define FMC_TAGVDW2S_valid_WIDTH                 1
+#define FMC_TAGVDW2S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_valid_SHIFT))&FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW2S_tag_SHIFT                   5
+#define FMC_TAGVDW2S_tag_WIDTH                   14
+#define FMC_TAGVDW2S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
+/* TAGVDW3S Bit Fields */
+#define FMC_TAGVDW3S_valid_MASK                  0x1u
+#define FMC_TAGVDW3S_valid_SHIFT                 0
+#define FMC_TAGVDW3S_valid_WIDTH                 1
+#define FMC_TAGVDW3S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_valid_SHIFT))&FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_tag_MASK                    0x7FFE0u
+#define FMC_TAGVDW3S_tag_SHIFT                   5
+#define FMC_TAGVDW3S_tag_WIDTH                   14
+#define FMC_TAGVDW3S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
+/* DATA_U Bit Fields */
+#define FMC_DATA_U_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_U_data_SHIFT                    0
+#define FMC_DATA_U_data_WIDTH                    32
+#define FMC_DATA_U_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
+/* DATA_L Bit Fields */
+#define FMC_DATA_L_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_L_data_SHIFT                    0
+#define FMC_DATA_L_data_WIDTH                    32
+#define FMC_DATA_L_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE                                 (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC                                      ((FMC_Type *)FMC_BASE)
+#define FMC_BASE_PTR                             (FMC)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS                           { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS                            { FMC }
+
+/* ----------------------------------------------------------------------------
+   -- FMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register instance definitions */
+/* FMC */
+#define FMC_PFAPR                                FMC_PFAPR_REG(FMC)
+#define FMC_PFB0CR                               FMC_PFB0CR_REG(FMC)
+#define FMC_PFB1CR                               FMC_PFB1CR_REG(FMC)
+#define FMC_TAGVDW0S0                            FMC_TAGVDW0S_REG(FMC,0)
+#define FMC_TAGVDW0S1                            FMC_TAGVDW0S_REG(FMC,1)
+#define FMC_TAGVDW0S2                            FMC_TAGVDW0S_REG(FMC,2)
+#define FMC_TAGVDW0S3                            FMC_TAGVDW0S_REG(FMC,3)
+#define FMC_TAGVDW1S0                            FMC_TAGVDW1S_REG(FMC,0)
+#define FMC_TAGVDW1S1                            FMC_TAGVDW1S_REG(FMC,1)
+#define FMC_TAGVDW1S2                            FMC_TAGVDW1S_REG(FMC,2)
+#define FMC_TAGVDW1S3                            FMC_TAGVDW1S_REG(FMC,3)
+#define FMC_TAGVDW2S0                            FMC_TAGVDW2S_REG(FMC,0)
+#define FMC_TAGVDW2S1                            FMC_TAGVDW2S_REG(FMC,1)
+#define FMC_TAGVDW2S2                            FMC_TAGVDW2S_REG(FMC,2)
+#define FMC_TAGVDW2S3                            FMC_TAGVDW2S_REG(FMC,3)
+#define FMC_TAGVDW3S0                            FMC_TAGVDW3S_REG(FMC,0)
+#define FMC_TAGVDW3S1                            FMC_TAGVDW3S_REG(FMC,1)
+#define FMC_TAGVDW3S2                            FMC_TAGVDW3S_REG(FMC,2)
+#define FMC_TAGVDW3S3                            FMC_TAGVDW3S_REG(FMC,3)
+#define FMC_DATAW0S0U                            FMC_DATA_U_REG(FMC,0,0)
+#define FMC_DATAW0S0L                            FMC_DATA_L_REG(FMC,0,0)
+#define FMC_DATAW0S1U                            FMC_DATA_U_REG(FMC,0,1)
+#define FMC_DATAW0S1L                            FMC_DATA_L_REG(FMC,0,1)
+#define FMC_DATAW0S2U                            FMC_DATA_U_REG(FMC,0,2)
+#define FMC_DATAW0S2L                            FMC_DATA_L_REG(FMC,0,2)
+#define FMC_DATAW0S3U                            FMC_DATA_U_REG(FMC,0,3)
+#define FMC_DATAW0S3L                            FMC_DATA_L_REG(FMC,0,3)
+#define FMC_DATAW1S0U                            FMC_DATA_U_REG(FMC,1,0)
+#define FMC_DATAW1S0L                            FMC_DATA_L_REG(FMC,1,0)
+#define FMC_DATAW1S1U                            FMC_DATA_U_REG(FMC,1,1)
+#define FMC_DATAW1S1L                            FMC_DATA_L_REG(FMC,1,1)
+#define FMC_DATAW1S2U                            FMC_DATA_U_REG(FMC,1,2)
+#define FMC_DATAW1S2L                            FMC_DATA_L_REG(FMC,1,2)
+#define FMC_DATAW1S3U                            FMC_DATA_U_REG(FMC,1,3)
+#define FMC_DATAW1S3L                            FMC_DATA_L_REG(FMC,1,3)
+#define FMC_DATAW2S0U                            FMC_DATA_U_REG(FMC,2,0)
+#define FMC_DATAW2S0L                            FMC_DATA_L_REG(FMC,2,0)
+#define FMC_DATAW2S1U                            FMC_DATA_U_REG(FMC,2,1)
+#define FMC_DATAW2S1L                            FMC_DATA_L_REG(FMC,2,1)
+#define FMC_DATAW2S2U                            FMC_DATA_U_REG(FMC,2,2)
+#define FMC_DATAW2S2L                            FMC_DATA_L_REG(FMC,2,2)
+#define FMC_DATAW2S3U                            FMC_DATA_U_REG(FMC,2,3)
+#define FMC_DATAW2S3L                            FMC_DATA_L_REG(FMC,2,3)
+#define FMC_DATAW3S0U                            FMC_DATA_U_REG(FMC,3,0)
+#define FMC_DATAW3S0L                            FMC_DATA_L_REG(FMC,3,0)
+#define FMC_DATAW3S1U                            FMC_DATA_U_REG(FMC,3,1)
+#define FMC_DATAW3S1L                            FMC_DATA_L_REG(FMC,3,1)
+#define FMC_DATAW3S2U                            FMC_DATA_U_REG(FMC,3,2)
+#define FMC_DATAW3S2L                            FMC_DATA_L_REG(FMC,3,2)
+#define FMC_DATAW3S3U                            FMC_DATA_U_REG(FMC,3,3)
+#define FMC_DATAW3S3L                            FMC_DATA_L_REG(FMC,3,3)
+
+/* FMC - Register array accessors */
+#define FMC_TAGVDW0S(index)                      FMC_TAGVDW0S_REG(FMC,index)
+#define FMC_TAGVDW1S(index)                      FMC_TAGVDW1S_REG(FMC,index)
+#define FMC_TAGVDW2S(index)                      FMC_TAGVDW2S_REG(FMC,index)
+#define FMC_TAGVDW3S(index)                      FMC_TAGVDW3S_REG(FMC,index)
+#define FMC_DATA_U(index,index2)                 FMC_DATA_U_REG(FMC,index,index2)
+#define FMC_DATA_L(index,index2)                 FMC_DATA_L_REG(FMC,index,index2)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t FEPROT;                             /**< EEPROM Protection Register, offset: 0x16 */
+  __IO uint8_t FDPROT;                             /**< Data Flash Protection Register, offset: 0x17 */
+} FTFE_Type, *FTFE_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register accessors */
+#define FTFE_FSTAT_REG(base)                     ((base)->FSTAT)
+#define FTFE_FCNFG_REG(base)                     ((base)->FCNFG)
+#define FTFE_FSEC_REG(base)                      ((base)->FSEC)
+#define FTFE_FOPT_REG(base)                      ((base)->FOPT)
+#define FTFE_FCCOB3_REG(base)                    ((base)->FCCOB3)
+#define FTFE_FCCOB2_REG(base)                    ((base)->FCCOB2)
+#define FTFE_FCCOB1_REG(base)                    ((base)->FCCOB1)
+#define FTFE_FCCOB0_REG(base)                    ((base)->FCCOB0)
+#define FTFE_FCCOB7_REG(base)                    ((base)->FCCOB7)
+#define FTFE_FCCOB6_REG(base)                    ((base)->FCCOB6)
+#define FTFE_FCCOB5_REG(base)                    ((base)->FCCOB5)
+#define FTFE_FCCOB4_REG(base)                    ((base)->FCCOB4)
+#define FTFE_FCCOBB_REG(base)                    ((base)->FCCOBB)
+#define FTFE_FCCOBA_REG(base)                    ((base)->FCCOBA)
+#define FTFE_FCCOB9_REG(base)                    ((base)->FCCOB9)
+#define FTFE_FCCOB8_REG(base)                    ((base)->FCCOB8)
+#define FTFE_FPROT3_REG(base)                    ((base)->FPROT3)
+#define FTFE_FPROT2_REG(base)                    ((base)->FPROT2)
+#define FTFE_FPROT1_REG(base)                    ((base)->FPROT1)
+#define FTFE_FPROT0_REG(base)                    ((base)->FPROT0)
+#define FTFE_FEPROT_REG(base)                    ((base)->FEPROT)
+#define FTFE_FDPROT_REG(base)                    ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFE_FSTAT_MGSTAT0_MASK                  0x1u
+#define FTFE_FSTAT_MGSTAT0_SHIFT                 0
+#define FTFE_FSTAT_MGSTAT0_WIDTH                 1
+#define FTFE_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_MGSTAT0_SHIFT))&FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_FPVIOL_MASK                   0x10u
+#define FTFE_FSTAT_FPVIOL_SHIFT                  4
+#define FTFE_FSTAT_FPVIOL_WIDTH                  1
+#define FTFE_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_FPVIOL_SHIFT))&FTFE_FSTAT_FPVIOL_MASK)
+#define FTFE_FSTAT_ACCERR_MASK                   0x20u
+#define FTFE_FSTAT_ACCERR_SHIFT                  5
+#define FTFE_FSTAT_ACCERR_WIDTH                  1
+#define FTFE_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_ACCERR_SHIFT))&FTFE_FSTAT_ACCERR_MASK)
+#define FTFE_FSTAT_RDCOLERR_MASK                 0x40u
+#define FTFE_FSTAT_RDCOLERR_SHIFT                6
+#define FTFE_FSTAT_RDCOLERR_WIDTH                1
+#define FTFE_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_RDCOLERR_SHIFT))&FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFE_FSTAT_CCIF_MASK                     0x80u
+#define FTFE_FSTAT_CCIF_SHIFT                    7
+#define FTFE_FSTAT_CCIF_WIDTH                    1
+#define FTFE_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_CCIF_SHIFT))&FTFE_FSTAT_CCIF_MASK)
+/* FCNFG Bit Fields */
+#define FTFE_FCNFG_EEERDY_MASK                   0x1u
+#define FTFE_FCNFG_EEERDY_SHIFT                  0
+#define FTFE_FCNFG_EEERDY_WIDTH                  1
+#define FTFE_FCNFG_EEERDY(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_EEERDY_SHIFT))&FTFE_FCNFG_EEERDY_MASK)
+#define FTFE_FCNFG_RAMRDY_MASK                   0x2u
+#define FTFE_FCNFG_RAMRDY_SHIFT                  1
+#define FTFE_FCNFG_RAMRDY_WIDTH                  1
+#define FTFE_FCNFG_RAMRDY(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RAMRDY_SHIFT))&FTFE_FCNFG_RAMRDY_MASK)
+#define FTFE_FCNFG_PFLSH_MASK                    0x4u
+#define FTFE_FCNFG_PFLSH_SHIFT                   2
+#define FTFE_FCNFG_PFLSH_WIDTH                   1
+#define FTFE_FCNFG_PFLSH(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_PFLSH_SHIFT))&FTFE_FCNFG_PFLSH_MASK)
+#define FTFE_FCNFG_SWAP_MASK                     0x8u
+#define FTFE_FCNFG_SWAP_SHIFT                    3
+#define FTFE_FCNFG_SWAP_WIDTH                    1
+#define FTFE_FCNFG_SWAP(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_SWAP_SHIFT))&FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_ERSSUSP_MASK                  0x10u
+#define FTFE_FCNFG_ERSSUSP_SHIFT                 4
+#define FTFE_FCNFG_ERSSUSP_WIDTH                 1
+#define FTFE_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSSUSP_SHIFT))&FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSAREQ_MASK                  0x20u
+#define FTFE_FCNFG_ERSAREQ_SHIFT                 5
+#define FTFE_FCNFG_ERSAREQ_WIDTH                 1
+#define FTFE_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSAREQ_SHIFT))&FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_RDCOLLIE_MASK                 0x40u
+#define FTFE_FCNFG_RDCOLLIE_SHIFT                6
+#define FTFE_FCNFG_RDCOLLIE_WIDTH                1
+#define FTFE_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RDCOLLIE_SHIFT))&FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_CCIE_MASK                     0x80u
+#define FTFE_FCNFG_CCIE_SHIFT                    7
+#define FTFE_FCNFG_CCIE_WIDTH                    1
+#define FTFE_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_CCIE_SHIFT))&FTFE_FCNFG_CCIE_MASK)
+/* FSEC Bit Fields */
+#define FTFE_FSEC_SEC_MASK                       0x3u
+#define FTFE_FSEC_SEC_SHIFT                      0
+#define FTFE_FSEC_SEC_WIDTH                      2
+#define FTFE_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK                    0xCu
+#define FTFE_FSEC_FSLACC_SHIFT                   2
+#define FTFE_FSEC_FSLACC_WIDTH                   2
+#define FTFE_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK                      0x30u
+#define FTFE_FSEC_MEEN_SHIFT                     4
+#define FTFE_FSEC_MEEN_WIDTH                     2
+#define FTFE_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK                     0xC0u
+#define FTFE_FSEC_KEYEN_SHIFT                    6
+#define FTFE_FSEC_KEYEN_WIDTH                    2
+#define FTFE_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFE_FOPT_OPT_MASK                       0xFFu
+#define FTFE_FOPT_OPT_SHIFT                      0
+#define FTFE_FOPT_OPT_WIDTH                      8
+#define FTFE_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFE_FCCOB3_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB3_CCOBn_SHIFT                  0
+#define FTFE_FCCOB3_CCOBn_WIDTH                  8
+#define FTFE_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFE_FCCOB2_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB2_CCOBn_SHIFT                  0
+#define FTFE_FCCOB2_CCOBn_WIDTH                  8
+#define FTFE_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFE_FCCOB1_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB1_CCOBn_SHIFT                  0
+#define FTFE_FCCOB1_CCOBn_WIDTH                  8
+#define FTFE_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFE_FCCOB0_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB0_CCOBn_SHIFT                  0
+#define FTFE_FCCOB0_CCOBn_WIDTH                  8
+#define FTFE_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFE_FCCOB7_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB7_CCOBn_SHIFT                  0
+#define FTFE_FCCOB7_CCOBn_WIDTH                  8
+#define FTFE_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFE_FCCOB6_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB6_CCOBn_SHIFT                  0
+#define FTFE_FCCOB6_CCOBn_WIDTH                  8
+#define FTFE_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFE_FCCOB5_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB5_CCOBn_SHIFT                  0
+#define FTFE_FCCOB5_CCOBn_WIDTH                  8
+#define FTFE_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFE_FCCOB4_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB4_CCOBn_SHIFT                  0
+#define FTFE_FCCOB4_CCOBn_WIDTH                  8
+#define FTFE_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFE_FCCOBB_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBB_CCOBn_SHIFT                  0
+#define FTFE_FCCOBB_CCOBn_WIDTH                  8
+#define FTFE_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFE_FCCOBA_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOBA_CCOBn_SHIFT                  0
+#define FTFE_FCCOBA_CCOBn_WIDTH                  8
+#define FTFE_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFE_FCCOB9_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB9_CCOBn_SHIFT                  0
+#define FTFE_FCCOB9_CCOBn_WIDTH                  8
+#define FTFE_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFE_FCCOB8_CCOBn_MASK                   0xFFu
+#define FTFE_FCCOB8_CCOBn_SHIFT                  0
+#define FTFE_FCCOB8_CCOBn_WIDTH                  8
+#define FTFE_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFE_FPROT3_PROT_MASK                    0xFFu
+#define FTFE_FPROT3_PROT_SHIFT                   0
+#define FTFE_FPROT3_PROT_WIDTH                   8
+#define FTFE_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFE_FPROT2_PROT_MASK                    0xFFu
+#define FTFE_FPROT2_PROT_SHIFT                   0
+#define FTFE_FPROT2_PROT_WIDTH                   8
+#define FTFE_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFE_FPROT1_PROT_MASK                    0xFFu
+#define FTFE_FPROT1_PROT_SHIFT                   0
+#define FTFE_FPROT1_PROT_WIDTH                   8
+#define FTFE_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFE_FPROT0_PROT_MASK                    0xFFu
+#define FTFE_FPROT0_PROT_SHIFT                   0
+#define FTFE_FPROT0_PROT_WIDTH                   8
+#define FTFE_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFE_FEPROT_EPROT_MASK                   0xFFu
+#define FTFE_FEPROT_EPROT_SHIFT                  0
+#define FTFE_FEPROT_EPROT_WIDTH                  8
+#define FTFE_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFE_FDPROT_DPROT_MASK                   0xFFu
+#define FTFE_FDPROT_DPROT_SHIFT                  0
+#define FTFE_FDPROT_DPROT_WIDTH                  8
+#define FTFE_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE                                (0x40020000u)
+/** Peripheral FTFE base pointer */
+#define FTFE                                     ((FTFE_Type *)FTFE_BASE)
+#define FTFE_BASE_PTR                            (FTFE)
+/** Array initializer of FTFE peripheral base addresses */
+#define FTFE_BASE_ADDRS                          { FTFE_BASE }
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASE_PTRS                           { FTFE }
+/** Interrupt vectors for the FTFE peripheral type */
+#define FTFE_COMMAND_COMPLETE_IRQS               { FTFE_IRQn }
+#define FTFE_READ_COLLISION_IRQS                 { Read_Collision_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTFE - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register instance definitions */
+/* FTFE */
+#define FTFE_FSTAT                               FTFE_FSTAT_REG(FTFE)
+#define FTFE_FCNFG                               FTFE_FCNFG_REG(FTFE)
+#define FTFE_FSEC                                FTFE_FSEC_REG(FTFE)
+#define FTFE_FOPT                                FTFE_FOPT_REG(FTFE)
+#define FTFE_FCCOB3                              FTFE_FCCOB3_REG(FTFE)
+#define FTFE_FCCOB2                              FTFE_FCCOB2_REG(FTFE)
+#define FTFE_FCCOB1                              FTFE_FCCOB1_REG(FTFE)
+#define FTFE_FCCOB0                              FTFE_FCCOB0_REG(FTFE)
+#define FTFE_FCCOB7                              FTFE_FCCOB7_REG(FTFE)
+#define FTFE_FCCOB6                              FTFE_FCCOB6_REG(FTFE)
+#define FTFE_FCCOB5                              FTFE_FCCOB5_REG(FTFE)
+#define FTFE_FCCOB4                              FTFE_FCCOB4_REG(FTFE)
+#define FTFE_FCCOBB                              FTFE_FCCOBB_REG(FTFE)
+#define FTFE_FCCOBA                              FTFE_FCCOBA_REG(FTFE)
+#define FTFE_FCCOB9                              FTFE_FCCOB9_REG(FTFE)
+#define FTFE_FCCOB8                              FTFE_FCCOB8_REG(FTFE)
+#define FTFE_FPROT3                              FTFE_FPROT3_REG(FTFE)
+#define FTFE_FPROT2                              FTFE_FPROT2_REG(FTFE)
+#define FTFE_FPROT1                              FTFE_FPROT1_REG(FTFE)
+#define FTFE_FPROT0                              FTFE_FPROT0_REG(FTFE)
+#define FTFE_FEPROT                              FTFE_FEPROT_REG(FTFE)
+#define FTFE_FDPROT                              FTFE_FDPROT_REG(FTFE)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[8];
+  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
+  __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
+  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
+  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
+  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
+  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
+  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
+  __IO uint32_t DEADTIME;                          /**< Deadtime Insertion Control, offset: 0x68 */
+  __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
+  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
+  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
+  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
+  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+  __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
+  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
+  __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
+  __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
+  __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type, *FTM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register accessors */
+#define FTM_SC_REG(base)                         ((base)->SC)
+#define FTM_CNT_REG(base)                        ((base)->CNT)
+#define FTM_MOD_REG(base)                        ((base)->MOD)
+#define FTM_CnSC_REG(base,index)                 ((base)->CONTROLS[index].CnSC)
+#define FTM_CnSC_COUNT                           8
+#define FTM_CnV_REG(base,index)                  ((base)->CONTROLS[index].CnV)
+#define FTM_CnV_COUNT                            8
+#define FTM_CNTIN_REG(base)                      ((base)->CNTIN)
+#define FTM_STATUS_REG(base)                     ((base)->STATUS)
+#define FTM_MODE_REG(base)                       ((base)->MODE)
+#define FTM_SYNC_REG(base)                       ((base)->SYNC)
+#define FTM_OUTINIT_REG(base)                    ((base)->OUTINIT)
+#define FTM_OUTMASK_REG(base)                    ((base)->OUTMASK)
+#define FTM_COMBINE_REG(base)                    ((base)->COMBINE)
+#define FTM_DEADTIME_REG(base)                   ((base)->DEADTIME)
+#define FTM_EXTTRIG_REG(base)                    ((base)->EXTTRIG)
+#define FTM_POL_REG(base)                        ((base)->POL)
+#define FTM_FMS_REG(base)                        ((base)->FMS)
+#define FTM_FILTER_REG(base)                     ((base)->FILTER)
+#define FTM_FLTCTRL_REG(base)                    ((base)->FLTCTRL)
+#define FTM_QDCTRL_REG(base)                     ((base)->QDCTRL)
+#define FTM_CONF_REG(base)                       ((base)->CONF)
+#define FTM_FLTPOL_REG(base)                     ((base)->FLTPOL)
+#define FTM_SYNCONF_REG(base)                    ((base)->SYNCONF)
+#define FTM_INVCTRL_REG(base)                    ((base)->INVCTRL)
+#define FTM_SWOCTRL_REG(base)                    ((base)->SWOCTRL)
+#define FTM_PWMLOAD_REG(base)                    ((base)->PWMLOAD)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK                           0x7u
+#define FTM_SC_PS_SHIFT                          0
+#define FTM_SC_PS_WIDTH                          3
+#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK                         0x18u
+#define FTM_SC_CLKS_SHIFT                        3
+#define FTM_SC_CLKS_WIDTH                        2
+#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK                        0x20u
+#define FTM_SC_CPWMS_SHIFT                       5
+#define FTM_SC_CPWMS_WIDTH                       1
+#define FTM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK                         0x40u
+#define FTM_SC_TOIE_SHIFT                        6
+#define FTM_SC_TOIE_WIDTH                        1
+#define FTM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK                          0x80u
+#define FTM_SC_TOF_SHIFT                         7
+#define FTM_SC_TOF_WIDTH                         1
+#define FTM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK                       0xFFFFu
+#define FTM_CNT_COUNT_SHIFT                      0
+#define FTM_CNT_COUNT_WIDTH                      16
+#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK                         0xFFFFu
+#define FTM_MOD_MOD_SHIFT                        0
+#define FTM_MOD_MOD_WIDTH                        16
+#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK                        0x1u
+#define FTM_CnSC_DMA_SHIFT                       0
+#define FTM_CnSC_DMA_WIDTH                       1
+#define FTM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ELSA_MASK                       0x4u
+#define FTM_CnSC_ELSA_SHIFT                      2
+#define FTM_CnSC_ELSA_WIDTH                      1
+#define FTM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK                       0x8u
+#define FTM_CnSC_ELSB_SHIFT                      3
+#define FTM_CnSC_ELSB_WIDTH                      1
+#define FTM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK                        0x10u
+#define FTM_CnSC_MSA_SHIFT                       4
+#define FTM_CnSC_MSA_WIDTH                       1
+#define FTM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK                        0x20u
+#define FTM_CnSC_MSB_SHIFT                       5
+#define FTM_CnSC_MSB_WIDTH                       1
+#define FTM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK                       0x40u
+#define FTM_CnSC_CHIE_SHIFT                      6
+#define FTM_CnSC_CHIE_WIDTH                      1
+#define FTM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK                        0x80u
+#define FTM_CnSC_CHF_SHIFT                       7
+#define FTM_CnSC_CHF_WIDTH                       1
+#define FTM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK                         0xFFFFu
+#define FTM_CnV_VAL_SHIFT                        0
+#define FTM_CnV_VAL_WIDTH                        16
+#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK                      0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT                     0
+#define FTM_CNTIN_INIT_WIDTH                     16
+#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK                     0x1u
+#define FTM_STATUS_CH0F_SHIFT                    0
+#define FTM_STATUS_CH0F_WIDTH                    1
+#define FTM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK                     0x2u
+#define FTM_STATUS_CH1F_SHIFT                    1
+#define FTM_STATUS_CH1F_WIDTH                    1
+#define FTM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK                     0x4u
+#define FTM_STATUS_CH2F_SHIFT                    2
+#define FTM_STATUS_CH2F_WIDTH                    1
+#define FTM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK                     0x8u
+#define FTM_STATUS_CH3F_SHIFT                    3
+#define FTM_STATUS_CH3F_WIDTH                    1
+#define FTM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK                     0x10u
+#define FTM_STATUS_CH4F_SHIFT                    4
+#define FTM_STATUS_CH4F_WIDTH                    1
+#define FTM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK                     0x20u
+#define FTM_STATUS_CH5F_SHIFT                    5
+#define FTM_STATUS_CH5F_WIDTH                    1
+#define FTM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK                     0x40u
+#define FTM_STATUS_CH6F_SHIFT                    6
+#define FTM_STATUS_CH6F_WIDTH                    1
+#define FTM_STATUS_CH6F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK                     0x80u
+#define FTM_STATUS_CH7F_SHIFT                    7
+#define FTM_STATUS_CH7F_WIDTH                    1
+#define FTM_STATUS_CH7F(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK                      0x1u
+#define FTM_MODE_FTMEN_SHIFT                     0
+#define FTM_MODE_FTMEN_WIDTH                     1
+#define FTM_MODE_FTMEN(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK                       0x2u
+#define FTM_MODE_INIT_SHIFT                      1
+#define FTM_MODE_INIT_WIDTH                      1
+#define FTM_MODE_INIT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK                      0x4u
+#define FTM_MODE_WPDIS_SHIFT                     2
+#define FTM_MODE_WPDIS_WIDTH                     1
+#define FTM_MODE_WPDIS(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK                    0x8u
+#define FTM_MODE_PWMSYNC_SHIFT                   3
+#define FTM_MODE_PWMSYNC_WIDTH                   1
+#define FTM_MODE_PWMSYNC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK                    0x10u
+#define FTM_MODE_CAPTEST_SHIFT                   4
+#define FTM_MODE_CAPTEST_WIDTH                   1
+#define FTM_MODE_CAPTEST(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK                     0x60u
+#define FTM_MODE_FAULTM_SHIFT                    5
+#define FTM_MODE_FAULTM_WIDTH                    2
+#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK                    0x80u
+#define FTM_MODE_FAULTIE_SHIFT                   7
+#define FTM_MODE_FAULTIE_WIDTH                   1
+#define FTM_MODE_FAULTIE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK                     0x1u
+#define FTM_SYNC_CNTMIN_SHIFT                    0
+#define FTM_SYNC_CNTMIN_WIDTH                    1
+#define FTM_SYNC_CNTMIN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK                     0x2u
+#define FTM_SYNC_CNTMAX_SHIFT                    1
+#define FTM_SYNC_CNTMAX_WIDTH                    1
+#define FTM_SYNC_CNTMAX(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK                     0x4u
+#define FTM_SYNC_REINIT_SHIFT                    2
+#define FTM_SYNC_REINIT_WIDTH                    1
+#define FTM_SYNC_REINIT(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK                    0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT                   3
+#define FTM_SYNC_SYNCHOM_WIDTH                   1
+#define FTM_SYNC_SYNCHOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK                      0x10u
+#define FTM_SYNC_TRIG0_SHIFT                     4
+#define FTM_SYNC_TRIG0_WIDTH                     1
+#define FTM_SYNC_TRIG0(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK                      0x20u
+#define FTM_SYNC_TRIG1_SHIFT                     5
+#define FTM_SYNC_TRIG1_WIDTH                     1
+#define FTM_SYNC_TRIG1(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK                      0x40u
+#define FTM_SYNC_TRIG2_SHIFT                     6
+#define FTM_SYNC_TRIG2_WIDTH                     1
+#define FTM_SYNC_TRIG2(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK                     0x80u
+#define FTM_SYNC_SWSYNC_SHIFT                    7
+#define FTM_SYNC_SWSYNC_WIDTH                    1
+#define FTM_SYNC_SWSYNC(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK                   0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT                  0
+#define FTM_OUTINIT_CH0OI_WIDTH                  1
+#define FTM_OUTINIT_CH0OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK                   0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT                  1
+#define FTM_OUTINIT_CH1OI_WIDTH                  1
+#define FTM_OUTINIT_CH1OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK                   0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT                  2
+#define FTM_OUTINIT_CH2OI_WIDTH                  1
+#define FTM_OUTINIT_CH2OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK                   0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT                  3
+#define FTM_OUTINIT_CH3OI_WIDTH                  1
+#define FTM_OUTINIT_CH3OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK                   0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT                  4
+#define FTM_OUTINIT_CH4OI_WIDTH                  1
+#define FTM_OUTINIT_CH4OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK                   0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT                  5
+#define FTM_OUTINIT_CH5OI_WIDTH                  1
+#define FTM_OUTINIT_CH5OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK                   0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT                  6
+#define FTM_OUTINIT_CH6OI_WIDTH                  1
+#define FTM_OUTINIT_CH6OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK                   0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT                  7
+#define FTM_OUTINIT_CH7OI_WIDTH                  1
+#define FTM_OUTINIT_CH7OI(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK                   0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT                  0
+#define FTM_OUTMASK_CH0OM_WIDTH                  1
+#define FTM_OUTMASK_CH0OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK                   0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT                  1
+#define FTM_OUTMASK_CH1OM_WIDTH                  1
+#define FTM_OUTMASK_CH1OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK                   0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT                  2
+#define FTM_OUTMASK_CH2OM_WIDTH                  1
+#define FTM_OUTMASK_CH2OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK                   0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT                  3
+#define FTM_OUTMASK_CH3OM_WIDTH                  1
+#define FTM_OUTMASK_CH3OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK                   0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT                  4
+#define FTM_OUTMASK_CH4OM_WIDTH                  1
+#define FTM_OUTMASK_CH4OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK                   0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT                  5
+#define FTM_OUTMASK_CH5OM_WIDTH                  1
+#define FTM_OUTMASK_CH5OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK                   0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT                  6
+#define FTM_OUTMASK_CH6OM_WIDTH                  1
+#define FTM_OUTMASK_CH6OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK                   0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT                  7
+#define FTM_OUTMASK_CH7OM_WIDTH                  1
+#define FTM_OUTMASK_CH7OM(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK                0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT               0
+#define FTM_COMBINE_COMBINE0_WIDTH               1
+#define FTM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK                   0x2u
+#define FTM_COMBINE_COMP0_SHIFT                  1
+#define FTM_COMBINE_COMP0_WIDTH                  1
+#define FTM_COMBINE_COMP0(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK                0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT               2
+#define FTM_COMBINE_DECAPEN0_WIDTH               1
+#define FTM_COMBINE_DECAPEN0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK                  0x8u
+#define FTM_COMBINE_DECAP0_SHIFT                 3
+#define FTM_COMBINE_DECAP0_WIDTH                 1
+#define FTM_COMBINE_DECAP0(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK                   0x10u
+#define FTM_COMBINE_DTEN0_SHIFT                  4
+#define FTM_COMBINE_DTEN0_WIDTH                  1
+#define FTM_COMBINE_DTEN0(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK                 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT                5
+#define FTM_COMBINE_SYNCEN0_WIDTH                1
+#define FTM_COMBINE_SYNCEN0(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK                0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT               6
+#define FTM_COMBINE_FAULTEN0_WIDTH               1
+#define FTM_COMBINE_FAULTEN0(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK                0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT               8
+#define FTM_COMBINE_COMBINE1_WIDTH               1
+#define FTM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK                   0x200u
+#define FTM_COMBINE_COMP1_SHIFT                  9
+#define FTM_COMBINE_COMP1_WIDTH                  1
+#define FTM_COMBINE_COMP1(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK                0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT               10
+#define FTM_COMBINE_DECAPEN1_WIDTH               1
+#define FTM_COMBINE_DECAPEN1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK                  0x800u
+#define FTM_COMBINE_DECAP1_SHIFT                 11
+#define FTM_COMBINE_DECAP1_WIDTH                 1
+#define FTM_COMBINE_DECAP1(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK                   0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT                  12
+#define FTM_COMBINE_DTEN1_WIDTH                  1
+#define FTM_COMBINE_DTEN1(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK                 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT                13
+#define FTM_COMBINE_SYNCEN1_WIDTH                1
+#define FTM_COMBINE_SYNCEN1(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK                0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT               14
+#define FTM_COMBINE_FAULTEN1_WIDTH               1
+#define FTM_COMBINE_FAULTEN1(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK                0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT               16
+#define FTM_COMBINE_COMBINE2_WIDTH               1
+#define FTM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK                   0x20000u
+#define FTM_COMBINE_COMP2_SHIFT                  17
+#define FTM_COMBINE_COMP2_WIDTH                  1
+#define FTM_COMBINE_COMP2(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK                0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT               18
+#define FTM_COMBINE_DECAPEN2_WIDTH               1
+#define FTM_COMBINE_DECAPEN2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK                  0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT                 19
+#define FTM_COMBINE_DECAP2_WIDTH                 1
+#define FTM_COMBINE_DECAP2(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK                   0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT                  20
+#define FTM_COMBINE_DTEN2_WIDTH                  1
+#define FTM_COMBINE_DTEN2(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK                 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT                21
+#define FTM_COMBINE_SYNCEN2_WIDTH                1
+#define FTM_COMBINE_SYNCEN2(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK                0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT               22
+#define FTM_COMBINE_FAULTEN2_WIDTH               1
+#define FTM_COMBINE_FAULTEN2(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK                0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT               24
+#define FTM_COMBINE_COMBINE3_WIDTH               1
+#define FTM_COMBINE_COMBINE3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK                   0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT                  25
+#define FTM_COMBINE_COMP3_WIDTH                  1
+#define FTM_COMBINE_COMP3(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK                0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT               26
+#define FTM_COMBINE_DECAPEN3_WIDTH               1
+#define FTM_COMBINE_DECAPEN3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK                  0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT                 27
+#define FTM_COMBINE_DECAP3_WIDTH                 1
+#define FTM_COMBINE_DECAP3(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK                   0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT                  28
+#define FTM_COMBINE_DTEN3_WIDTH                  1
+#define FTM_COMBINE_DTEN3(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK                 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT                29
+#define FTM_COMBINE_SYNCEN3_WIDTH                1
+#define FTM_COMBINE_SYNCEN3(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK                0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT               30
+#define FTM_COMBINE_FAULTEN3_WIDTH               1
+#define FTM_COMBINE_FAULTEN3(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK                  0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT                 0
+#define FTM_DEADTIME_DTVAL_WIDTH                 6
+#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK                   0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT                  6
+#define FTM_DEADTIME_DTPS_WIDTH                  2
+#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK                 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT                0
+#define FTM_EXTTRIG_CH2TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH2TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK                 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT                1
+#define FTM_EXTTRIG_CH3TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH3TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK                 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT                2
+#define FTM_EXTTRIG_CH4TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH4TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK                 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT                3
+#define FTM_EXTTRIG_CH5TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH5TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK                 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT                4
+#define FTM_EXTTRIG_CH0TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH0TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK                 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT                5
+#define FTM_EXTTRIG_CH1TRIG_WIDTH                1
+#define FTM_EXTTRIG_CH1TRIG(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK              0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT             6
+#define FTM_EXTTRIG_INITTRIGEN_WIDTH             1
+#define FTM_EXTTRIG_INITTRIGEN(x)                (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK                   0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT                  7
+#define FTM_EXTTRIG_TRIGF_WIDTH                  1
+#define FTM_EXTTRIG_TRIGF(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK                        0x1u
+#define FTM_POL_POL0_SHIFT                       0
+#define FTM_POL_POL0_WIDTH                       1
+#define FTM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK                        0x2u
+#define FTM_POL_POL1_SHIFT                       1
+#define FTM_POL_POL1_WIDTH                       1
+#define FTM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK                        0x4u
+#define FTM_POL_POL2_SHIFT                       2
+#define FTM_POL_POL2_WIDTH                       1
+#define FTM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK                        0x8u
+#define FTM_POL_POL3_SHIFT                       3
+#define FTM_POL_POL3_WIDTH                       1
+#define FTM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK                        0x10u
+#define FTM_POL_POL4_SHIFT                       4
+#define FTM_POL_POL4_WIDTH                       1
+#define FTM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK                        0x20u
+#define FTM_POL_POL5_SHIFT                       5
+#define FTM_POL_POL5_WIDTH                       1
+#define FTM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK                        0x40u
+#define FTM_POL_POL6_SHIFT                       6
+#define FTM_POL_POL6_WIDTH                       1
+#define FTM_POL_POL6(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK                        0x80u
+#define FTM_POL_POL7_SHIFT                       7
+#define FTM_POL_POL7_WIDTH                       1
+#define FTM_POL_POL7(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK                     0x1u
+#define FTM_FMS_FAULTF0_SHIFT                    0
+#define FTM_FMS_FAULTF0_WIDTH                    1
+#define FTM_FMS_FAULTF0(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK                     0x2u
+#define FTM_FMS_FAULTF1_SHIFT                    1
+#define FTM_FMS_FAULTF1_WIDTH                    1
+#define FTM_FMS_FAULTF1(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK                     0x4u
+#define FTM_FMS_FAULTF2_SHIFT                    2
+#define FTM_FMS_FAULTF2_WIDTH                    1
+#define FTM_FMS_FAULTF2(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK                     0x8u
+#define FTM_FMS_FAULTF3_SHIFT                    3
+#define FTM_FMS_FAULTF3_WIDTH                    1
+#define FTM_FMS_FAULTF3(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK                     0x20u
+#define FTM_FMS_FAULTIN_SHIFT                    5
+#define FTM_FMS_FAULTIN_WIDTH                    1
+#define FTM_FMS_FAULTIN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK                        0x40u
+#define FTM_FMS_WPEN_SHIFT                       6
+#define FTM_FMS_WPEN_WIDTH                       1
+#define FTM_FMS_WPEN(x)                          (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK                      0x80u
+#define FTM_FMS_FAULTF_SHIFT                     7
+#define FTM_FMS_FAULTF_WIDTH                     1
+#define FTM_FMS_FAULTF(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK                  0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT                 0
+#define FTM_FILTER_CH0FVAL_WIDTH                 4
+#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK                  0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT                 4
+#define FTM_FILTER_CH1FVAL_WIDTH                 4
+#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK                  0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT                 8
+#define FTM_FILTER_CH2FVAL_WIDTH                 4
+#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK                  0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT                 12
+#define FTM_FILTER_CH3FVAL_WIDTH                 4
+#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK                0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT               0
+#define FTM_FLTCTRL_FAULT0EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT0EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK                0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT               1
+#define FTM_FLTCTRL_FAULT1EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT1EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK                0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT               2
+#define FTM_FLTCTRL_FAULT2EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT2EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK                0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT               3
+#define FTM_FLTCTRL_FAULT3EN_WIDTH               1
+#define FTM_FLTCTRL_FAULT3EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK                0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT               4
+#define FTM_FLTCTRL_FFLTR0EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR0EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK                0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT               5
+#define FTM_FLTCTRL_FFLTR1EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR1EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK                0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT               6
+#define FTM_FLTCTRL_FFLTR2EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR2EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK                0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT               7
+#define FTM_FLTCTRL_FFLTR3EN_WIDTH               1
+#define FTM_FLTCTRL_FFLTR3EN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK                   0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT                  8
+#define FTM_FLTCTRL_FFVAL_WIDTH                  4
+#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK                   0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT                  0
+#define FTM_QDCTRL_QUADEN_WIDTH                  1
+#define FTM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK                   0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT                  1
+#define FTM_QDCTRL_TOFDIR_WIDTH                  1
+#define FTM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK                   0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT                  2
+#define FTM_QDCTRL_QUADIR_WIDTH                  1
+#define FTM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK                 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT                3
+#define FTM_QDCTRL_QUADMODE_WIDTH                1
+#define FTM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK                   0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT                  4
+#define FTM_QDCTRL_PHBPOL_WIDTH                  1
+#define FTM_QDCTRL_PHBPOL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK                   0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT                  5
+#define FTM_QDCTRL_PHAPOL_WIDTH                  1
+#define FTM_QDCTRL_PHAPOL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK                0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT               6
+#define FTM_QDCTRL_PHBFLTREN_WIDTH               1
+#define FTM_QDCTRL_PHBFLTREN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK                0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT               7
+#define FTM_QDCTRL_PHAFLTREN_WIDTH               1
+#define FTM_QDCTRL_PHAFLTREN(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK                     0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT                    0
+#define FTM_CONF_NUMTOF_WIDTH                    5
+#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK                    0xC0u
+#define FTM_CONF_BDMMODE_SHIFT                   6
+#define FTM_CONF_BDMMODE_WIDTH                   2
+#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK                     0x200u
+#define FTM_CONF_GTBEEN_SHIFT                    9
+#define FTM_CONF_GTBEEN_WIDTH                    1
+#define FTM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK                    0x400u
+#define FTM_CONF_GTBEOUT_SHIFT                   10
+#define FTM_CONF_GTBEOUT_WIDTH                   1
+#define FTM_CONF_GTBEOUT(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK                  0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT                 0
+#define FTM_FLTPOL_FLT0POL_WIDTH                 1
+#define FTM_FLTPOL_FLT0POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK                  0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT                 1
+#define FTM_FLTPOL_FLT1POL_WIDTH                 1
+#define FTM_FLTPOL_FLT1POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK                  0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT                 2
+#define FTM_FLTPOL_FLT2POL_WIDTH                 1
+#define FTM_FLTPOL_FLT2POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK                  0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT                 3
+#define FTM_FLTPOL_FLT3POL_WIDTH                 1
+#define FTM_FLTPOL_FLT3POL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK              0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT             0
+#define FTM_SYNCONF_HWTRIGMODE_WIDTH             1
+#define FTM_SYNCONF_HWTRIGMODE(x)                (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK                  0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT                 2
+#define FTM_SYNCONF_CNTINC_WIDTH                 1
+#define FTM_SYNCONF_CNTINC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK                    0x10u
+#define FTM_SYNCONF_INVC_SHIFT                   4
+#define FTM_SYNCONF_INVC_WIDTH                   1
+#define FTM_SYNCONF_INVC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK                    0x20u
+#define FTM_SYNCONF_SWOC_SHIFT                   5
+#define FTM_SYNCONF_SWOC_WIDTH                   1
+#define FTM_SYNCONF_SWOC(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK                0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT               7
+#define FTM_SYNCONF_SYNCMODE_WIDTH               1
+#define FTM_SYNCONF_SYNCMODE(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK                0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT               8
+#define FTM_SYNCONF_SWRSTCNT_WIDTH               1
+#define FTM_SYNCONF_SWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK                 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT                9
+#define FTM_SYNCONF_SWWRBUF_WIDTH                1
+#define FTM_SYNCONF_SWWRBUF(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK                    0x400u
+#define FTM_SYNCONF_SWOM_SHIFT                   10
+#define FTM_SYNCONF_SWOM_WIDTH                   1
+#define FTM_SYNCONF_SWOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK                  0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT                 11
+#define FTM_SYNCONF_SWINVC_WIDTH                 1
+#define FTM_SYNCONF_SWINVC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK                   0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT                  12
+#define FTM_SYNCONF_SWSOC_WIDTH                  1
+#define FTM_SYNCONF_SWSOC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK                0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT               16
+#define FTM_SYNCONF_HWRSTCNT_WIDTH               1
+#define FTM_SYNCONF_HWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK                 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT                17
+#define FTM_SYNCONF_HWWRBUF_WIDTH                1
+#define FTM_SYNCONF_HWWRBUF(x)                   (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK                    0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT                   18
+#define FTM_SYNCONF_HWOM_WIDTH                   1
+#define FTM_SYNCONF_HWOM(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK                  0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT                 19
+#define FTM_SYNCONF_HWINVC_WIDTH                 1
+#define FTM_SYNCONF_HWINVC(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK                   0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT                  20
+#define FTM_SYNCONF_HWSOC_WIDTH                  1
+#define FTM_SYNCONF_HWSOC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK                  0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT                 0
+#define FTM_INVCTRL_INV0EN_WIDTH                 1
+#define FTM_INVCTRL_INV0EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK                  0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT                 1
+#define FTM_INVCTRL_INV1EN_WIDTH                 1
+#define FTM_INVCTRL_INV1EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK                  0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT                 2
+#define FTM_INVCTRL_INV2EN_WIDTH                 1
+#define FTM_INVCTRL_INV2EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK                  0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT                 3
+#define FTM_INVCTRL_INV3EN_WIDTH                 1
+#define FTM_INVCTRL_INV3EN(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK                   0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT                  0
+#define FTM_SWOCTRL_CH0OC_WIDTH                  1
+#define FTM_SWOCTRL_CH0OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK                   0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT                  1
+#define FTM_SWOCTRL_CH1OC_WIDTH                  1
+#define FTM_SWOCTRL_CH1OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK                   0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT                  2
+#define FTM_SWOCTRL_CH2OC_WIDTH                  1
+#define FTM_SWOCTRL_CH2OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK                   0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT                  3
+#define FTM_SWOCTRL_CH3OC_WIDTH                  1
+#define FTM_SWOCTRL_CH3OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK                   0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT                  4
+#define FTM_SWOCTRL_CH4OC_WIDTH                  1
+#define FTM_SWOCTRL_CH4OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK                   0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT                  5
+#define FTM_SWOCTRL_CH5OC_WIDTH                  1
+#define FTM_SWOCTRL_CH5OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK                   0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT                  6
+#define FTM_SWOCTRL_CH6OC_WIDTH                  1
+#define FTM_SWOCTRL_CH6OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK                   0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT                  7
+#define FTM_SWOCTRL_CH7OC_WIDTH                  1
+#define FTM_SWOCTRL_CH7OC(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK                  0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT                 8
+#define FTM_SWOCTRL_CH0OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH0OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK                  0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT                 9
+#define FTM_SWOCTRL_CH1OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH1OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK                  0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT                 10
+#define FTM_SWOCTRL_CH2OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH2OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK                  0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT                 11
+#define FTM_SWOCTRL_CH3OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH3OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK                  0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT                 12
+#define FTM_SWOCTRL_CH4OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH4OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK                  0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT                 13
+#define FTM_SWOCTRL_CH5OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH5OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK                  0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT                 14
+#define FTM_SWOCTRL_CH6OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH6OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK                  0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT                 15
+#define FTM_SWOCTRL_CH7OCV_WIDTH                 1
+#define FTM_SWOCTRL_CH7OCV(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK                  0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT                 0
+#define FTM_PWMLOAD_CH0SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH0SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK                  0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT                 1
+#define FTM_PWMLOAD_CH1SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH1SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK                  0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT                 2
+#define FTM_PWMLOAD_CH2SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH2SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK                  0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT                 3
+#define FTM_PWMLOAD_CH3SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH3SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK                  0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT                 4
+#define FTM_PWMLOAD_CH4SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH4SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK                  0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT                 5
+#define FTM_PWMLOAD_CH5SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH5SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK                  0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT                 6
+#define FTM_PWMLOAD_CH6SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH6SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK                  0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT                 7
+#define FTM_PWMLOAD_CH7SEL_WIDTH                 1
+#define FTM_PWMLOAD_CH7SEL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK                    0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT                   9
+#define FTM_PWMLOAD_LDOK_WIDTH                   1
+#define FTM_PWMLOAD_LDOK(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE                                (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0                                     ((FTM_Type *)FTM0_BASE)
+#define FTM0_BASE_PTR                            (FTM0)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE                                (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1                                     ((FTM_Type *)FTM1_BASE)
+#define FTM1_BASE_PTR                            (FTM1)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE                                (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2                                     ((FTM_Type *)FTM2_BASE)
+#define FTM2_BASE_PTR                            (FTM2)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE                                (0x400B9000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3                                     ((FTM_Type *)FTM3_BASE)
+#define FTM3_BASE_PTR                            (FTM3)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS                           { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS                            { FTM0, FTM1, FTM2, FTM3 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS                                 { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- FTM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register instance definitions */
+/* FTM0 */
+#define FTM0_SC                                  FTM_SC_REG(FTM0)
+#define FTM0_CNT                                 FTM_CNT_REG(FTM0)
+#define FTM0_MOD                                 FTM_MOD_REG(FTM0)
+#define FTM0_C0SC                                FTM_CnSC_REG(FTM0,0)
+#define FTM0_C0V                                 FTM_CnV_REG(FTM0,0)
+#define FTM0_C1SC                                FTM_CnSC_REG(FTM0,1)
+#define FTM0_C1V                                 FTM_CnV_REG(FTM0,1)
+#define FTM0_C2SC                                FTM_CnSC_REG(FTM0,2)
+#define FTM0_C2V                                 FTM_CnV_REG(FTM0,2)
+#define FTM0_C3SC                                FTM_CnSC_REG(FTM0,3)
+#define FTM0_C3V                                 FTM_CnV_REG(FTM0,3)
+#define FTM0_C4SC                                FTM_CnSC_REG(FTM0,4)
+#define FTM0_C4V                                 FTM_CnV_REG(FTM0,4)
+#define FTM0_C5SC                                FTM_CnSC_REG(FTM0,5)
+#define FTM0_C5V                                 FTM_CnV_REG(FTM0,5)
+#define FTM0_C6SC                                FTM_CnSC_REG(FTM0,6)
+#define FTM0_C6V                                 FTM_CnV_REG(FTM0,6)
+#define FTM0_C7SC                                FTM_CnSC_REG(FTM0,7)
+#define FTM0_C7V                                 FTM_CnV_REG(FTM0,7)
+#define FTM0_CNTIN                               FTM_CNTIN_REG(FTM0)
+#define FTM0_STATUS                              FTM_STATUS_REG(FTM0)
+#define FTM0_MODE                                FTM_MODE_REG(FTM0)
+#define FTM0_SYNC                                FTM_SYNC_REG(FTM0)
+#define FTM0_OUTINIT                             FTM_OUTINIT_REG(FTM0)
+#define FTM0_OUTMASK                             FTM_OUTMASK_REG(FTM0)
+#define FTM0_COMBINE                             FTM_COMBINE_REG(FTM0)
+#define FTM0_DEADTIME                            FTM_DEADTIME_REG(FTM0)
+#define FTM0_EXTTRIG                             FTM_EXTTRIG_REG(FTM0)
+#define FTM0_POL                                 FTM_POL_REG(FTM0)
+#define FTM0_FMS                                 FTM_FMS_REG(FTM0)
+#define FTM0_FILTER                              FTM_FILTER_REG(FTM0)
+#define FTM0_FLTCTRL                             FTM_FLTCTRL_REG(FTM0)
+#define FTM0_QDCTRL                              FTM_QDCTRL_REG(FTM0)
+#define FTM0_CONF                                FTM_CONF_REG(FTM0)
+#define FTM0_FLTPOL                              FTM_FLTPOL_REG(FTM0)
+#define FTM0_SYNCONF                             FTM_SYNCONF_REG(FTM0)
+#define FTM0_INVCTRL                             FTM_INVCTRL_REG(FTM0)
+#define FTM0_SWOCTRL                             FTM_SWOCTRL_REG(FTM0)
+#define FTM0_PWMLOAD                             FTM_PWMLOAD_REG(FTM0)
+/* FTM1 */
+#define FTM1_SC                                  FTM_SC_REG(FTM1)
+#define FTM1_CNT                                 FTM_CNT_REG(FTM1)
+#define FTM1_MOD                                 FTM_MOD_REG(FTM1)
+#define FTM1_C0SC                                FTM_CnSC_REG(FTM1,0)
+#define FTM1_C0V                                 FTM_CnV_REG(FTM1,0)
+#define FTM1_C1SC                                FTM_CnSC_REG(FTM1,1)
+#define FTM1_C1V                                 FTM_CnV_REG(FTM1,1)
+#define FTM1_CNTIN                               FTM_CNTIN_REG(FTM1)
+#define FTM1_STATUS                              FTM_STATUS_REG(FTM1)
+#define FTM1_MODE                                FTM_MODE_REG(FTM1)
+#define FTM1_SYNC                                FTM_SYNC_REG(FTM1)
+#define FTM1_OUTINIT                             FTM_OUTINIT_REG(FTM1)
+#define FTM1_OUTMASK                             FTM_OUTMASK_REG(FTM1)
+#define FTM1_COMBINE                             FTM_COMBINE_REG(FTM1)
+#define FTM1_DEADTIME                            FTM_DEADTIME_REG(FTM1)
+#define FTM1_EXTTRIG                             FTM_EXTTRIG_REG(FTM1)
+#define FTM1_POL                                 FTM_POL_REG(FTM1)
+#define FTM1_FMS                                 FTM_FMS_REG(FTM1)
+#define FTM1_FILTER                              FTM_FILTER_REG(FTM1)
+#define FTM1_FLTCTRL                             FTM_FLTCTRL_REG(FTM1)
+#define FTM1_QDCTRL                              FTM_QDCTRL_REG(FTM1)
+#define FTM1_CONF                                FTM_CONF_REG(FTM1)
+#define FTM1_FLTPOL                              FTM_FLTPOL_REG(FTM1)
+#define FTM1_SYNCONF                             FTM_SYNCONF_REG(FTM1)
+#define FTM1_INVCTRL                             FTM_INVCTRL_REG(FTM1)
+#define FTM1_SWOCTRL                             FTM_SWOCTRL_REG(FTM1)
+#define FTM1_PWMLOAD                             FTM_PWMLOAD_REG(FTM1)
+/* FTM2 */
+#define FTM2_SC                                  FTM_SC_REG(FTM2)
+#define FTM2_CNT                                 FTM_CNT_REG(FTM2)
+#define FTM2_MOD                                 FTM_MOD_REG(FTM2)
+#define FTM2_C0SC                                FTM_CnSC_REG(FTM2,0)
+#define FTM2_C0V                                 FTM_CnV_REG(FTM2,0)
+#define FTM2_C1SC                                FTM_CnSC_REG(FTM2,1)
+#define FTM2_C1V                                 FTM_CnV_REG(FTM2,1)
+#define FTM2_CNTIN                               FTM_CNTIN_REG(FTM2)
+#define FTM2_STATUS                              FTM_STATUS_REG(FTM2)
+#define FTM2_MODE                                FTM_MODE_REG(FTM2)
+#define FTM2_SYNC                                FTM_SYNC_REG(FTM2)
+#define FTM2_OUTINIT                             FTM_OUTINIT_REG(FTM2)
+#define FTM2_OUTMASK                             FTM_OUTMASK_REG(FTM2)
+#define FTM2_COMBINE                             FTM_COMBINE_REG(FTM2)
+#define FTM2_DEADTIME                            FTM_DEADTIME_REG(FTM2)
+#define FTM2_EXTTRIG                             FTM_EXTTRIG_REG(FTM2)
+#define FTM2_POL                                 FTM_POL_REG(FTM2)
+#define FTM2_FMS                                 FTM_FMS_REG(FTM2)
+#define FTM2_FILTER                              FTM_FILTER_REG(FTM2)
+#define FTM2_FLTCTRL                             FTM_FLTCTRL_REG(FTM2)
+#define FTM2_QDCTRL                              FTM_QDCTRL_REG(FTM2)
+#define FTM2_CONF                                FTM_CONF_REG(FTM2)
+#define FTM2_FLTPOL                              FTM_FLTPOL_REG(FTM2)
+#define FTM2_SYNCONF                             FTM_SYNCONF_REG(FTM2)
+#define FTM2_INVCTRL                             FTM_INVCTRL_REG(FTM2)
+#define FTM2_SWOCTRL                             FTM_SWOCTRL_REG(FTM2)
+#define FTM2_PWMLOAD                             FTM_PWMLOAD_REG(FTM2)
+/* FTM3 */
+#define FTM3_SC                                  FTM_SC_REG(FTM3)
+#define FTM3_CNT                                 FTM_CNT_REG(FTM3)
+#define FTM3_MOD                                 FTM_MOD_REG(FTM3)
+#define FTM3_C0SC                                FTM_CnSC_REG(FTM3,0)
+#define FTM3_C0V                                 FTM_CnV_REG(FTM3,0)
+#define FTM3_C1SC                                FTM_CnSC_REG(FTM3,1)
+#define FTM3_C1V                                 FTM_CnV_REG(FTM3,1)
+#define FTM3_C2SC                                FTM_CnSC_REG(FTM3,2)
+#define FTM3_C2V                                 FTM_CnV_REG(FTM3,2)
+#define FTM3_C3SC                                FTM_CnSC_REG(FTM3,3)
+#define FTM3_C3V                                 FTM_CnV_REG(FTM3,3)
+#define FTM3_C4SC                                FTM_CnSC_REG(FTM3,4)
+#define FTM3_C4V                                 FTM_CnV_REG(FTM3,4)
+#define FTM3_C5SC                                FTM_CnSC_REG(FTM3,5)
+#define FTM3_C5V                                 FTM_CnV_REG(FTM3,5)
+#define FTM3_C6SC                                FTM_CnSC_REG(FTM3,6)
+#define FTM3_C6V                                 FTM_CnV_REG(FTM3,6)
+#define FTM3_C7SC                                FTM_CnSC_REG(FTM3,7)
+#define FTM3_C7V                                 FTM_CnV_REG(FTM3,7)
+#define FTM3_CNTIN                               FTM_CNTIN_REG(FTM3)
+#define FTM3_STATUS                              FTM_STATUS_REG(FTM3)
+#define FTM3_MODE                                FTM_MODE_REG(FTM3)
+#define FTM3_SYNC                                FTM_SYNC_REG(FTM3)
+#define FTM3_OUTINIT                             FTM_OUTINIT_REG(FTM3)
+#define FTM3_OUTMASK                             FTM_OUTMASK_REG(FTM3)
+#define FTM3_COMBINE                             FTM_COMBINE_REG(FTM3)
+#define FTM3_DEADTIME                            FTM_DEADTIME_REG(FTM3)
+#define FTM3_EXTTRIG                             FTM_EXTTRIG_REG(FTM3)
+#define FTM3_POL                                 FTM_POL_REG(FTM3)
+#define FTM3_FMS                                 FTM_FMS_REG(FTM3)
+#define FTM3_FILTER                              FTM_FILTER_REG(FTM3)
+#define FTM3_FLTCTRL                             FTM_FLTCTRL_REG(FTM3)
+#define FTM3_QDCTRL                              FTM_QDCTRL_REG(FTM3)
+#define FTM3_CONF                                FTM_CONF_REG(FTM3)
+#define FTM3_FLTPOL                              FTM_FLTPOL_REG(FTM3)
+#define FTM3_SYNCONF                             FTM_SYNCONF_REG(FTM3)
+#define FTM3_INVCTRL                             FTM_INVCTRL_REG(FTM3)
+#define FTM3_SWOCTRL                             FTM_SWOCTRL_REG(FTM3)
+#define FTM3_PWMLOAD                             FTM_PWMLOAD_REG(FTM3)
+
+/* FTM - Register array accessors */
+#define FTM0_CnSC(index)                         FTM_CnSC_REG(FTM0,index)
+#define FTM1_CnSC(index)                         FTM_CnSC_REG(FTM1,index)
+#define FTM2_CnSC(index)                         FTM_CnSC_REG(FTM2,index)
+#define FTM3_CnSC(index)                         FTM_CnSC_REG(FTM3,index)
+#define FTM0_CnV(index)                          FTM_CnV_REG(FTM0,index)
+#define FTM1_CnV(index)                          FTM_CnV_REG(FTM1,index)
+#define FTM2_CnV(index)                          FTM_CnV_REG(FTM2,index)
+#define FTM3_CnV(index)                          FTM_CnV_REG(FTM3,index)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base)                      ((base)->PDOR)
+#define GPIO_PSOR_REG(base)                      ((base)->PSOR)
+#define GPIO_PCOR_REG(base)                      ((base)->PCOR)
+#define GPIO_PTOR_REG(base)                      ((base)->PTOR)
+#define GPIO_PDIR_REG(base)                      ((base)->PDIR)
+#define GPIO_PDDR_REG(base)                      ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT                      0
+#define GPIO_PDOR_PDO_WIDTH                      32
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT                     0
+#define GPIO_PSOR_PTSO_WIDTH                     32
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT                     0
+#define GPIO_PCOR_PTCO_WIDTH                     32
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT                     0
+#define GPIO_PTOR_PTTO_WIDTH                     32
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT                      0
+#define GPIO_PDIR_PDI_WIDTH                      32
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT                      0
+#define GPIO_PDDR_PDD_WIDTH                      32
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE                                 (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA                                      ((GPIO_Type *)PTA_BASE)
+#define PTA_BASE_PTR                             (PTA)
+/** Peripheral PTB base address */
+#define PTB_BASE                                 (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB                                      ((GPIO_Type *)PTB_BASE)
+#define PTB_BASE_PTR                             (PTB)
+/** Peripheral PTC base address */
+#define PTC_BASE                                 (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC                                      ((GPIO_Type *)PTC_BASE)
+#define PTC_BASE_PTR                             (PTC)
+/** Peripheral PTD base address */
+#define PTD_BASE                                 (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD                                      ((GPIO_Type *)PTD_BASE)
+#define PTD_BASE_PTR                             (PTD)
+/** Peripheral PTE base address */
+#define PTE_BASE                                 (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE                                      ((GPIO_Type *)PTE_BASE)
+#define PTE_BASE_PTR                             (PTE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { PTA, PTB, PTC, PTD, PTE }
+
+/* ----------------------------------------------------------------------------
+   -- GPIO - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* PTA */
+#define GPIOA_PDOR                               GPIO_PDOR_REG(PTA)
+#define GPIOA_PSOR                               GPIO_PSOR_REG(PTA)
+#define GPIOA_PCOR                               GPIO_PCOR_REG(PTA)
+#define GPIOA_PTOR                               GPIO_PTOR_REG(PTA)
+#define GPIOA_PDIR                               GPIO_PDIR_REG(PTA)
+#define GPIOA_PDDR                               GPIO_PDDR_REG(PTA)
+/* PTB */
+#define GPIOB_PDOR                               GPIO_PDOR_REG(PTB)
+#define GPIOB_PSOR                               GPIO_PSOR_REG(PTB)
+#define GPIOB_PCOR                               GPIO_PCOR_REG(PTB)
+#define GPIOB_PTOR                               GPIO_PTOR_REG(PTB)
+#define GPIOB_PDIR                               GPIO_PDIR_REG(PTB)
+#define GPIOB_PDDR                               GPIO_PDDR_REG(PTB)
+/* PTC */
+#define GPIOC_PDOR                               GPIO_PDOR_REG(PTC)
+#define GPIOC_PSOR                               GPIO_PSOR_REG(PTC)
+#define GPIOC_PCOR                               GPIO_PCOR_REG(PTC)
+#define GPIOC_PTOR                               GPIO_PTOR_REG(PTC)
+#define GPIOC_PDIR                               GPIO_PDIR_REG(PTC)
+#define GPIOC_PDDR                               GPIO_PDDR_REG(PTC)
+/* PTD */
+#define GPIOD_PDOR                               GPIO_PDOR_REG(PTD)
+#define GPIOD_PSOR                               GPIO_PSOR_REG(PTD)
+#define GPIOD_PCOR                               GPIO_PCOR_REG(PTD)
+#define GPIOD_PTOR                               GPIO_PTOR_REG(PTD)
+#define GPIOD_PDIR                               GPIO_PDIR_REG(PTD)
+#define GPIOD_PDDR                               GPIO_PDDR_REG(PTD)
+/* PTE */
+#define GPIOE_PDOR                               GPIO_PDOR_REG(PTE)
+#define GPIOE_PSOR                               GPIO_PSOR_REG(PTE)
+#define GPIOE_PCOR                               GPIO_PCOR_REG(PTE)
+#define GPIOE_PTOR                               GPIO_PTOR_REG(PTE)
+#define GPIOE_PDIR                               GPIO_PDIR_REG(PTE)
+#define GPIOE_PDDR                               GPIO_PDDR_REG(PTE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base)                         ((base)->A1)
+#define I2C_F_REG(base)                          ((base)->F)
+#define I2C_C1_REG(base)                         ((base)->C1)
+#define I2C_S_REG(base)                          ((base)->S)
+#define I2C_D_REG(base)                          ((base)->D)
+#define I2C_C2_REG(base)                         ((base)->C2)
+#define I2C_FLT_REG(base)                        ((base)->FLT)
+#define I2C_RA_REG(base)                         ((base)->RA)
+#define I2C_SMB_REG(base)                        ((base)->SMB)
+#define I2C_A2_REG(base)                         ((base)->A2)
+#define I2C_SLTH_REG(base)                       ((base)->SLTH)
+#define I2C_SLTL_REG(base)                       ((base)->SLTL)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK                           0xFEu
+#define I2C_A1_AD_SHIFT                          1
+#define I2C_A1_AD_WIDTH                          7
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK                           0x3Fu
+#define I2C_F_ICR_SHIFT                          0
+#define I2C_F_ICR_WIDTH                          6
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          0xC0u
+#define I2C_F_MULT_SHIFT                         6
+#define I2C_F_MULT_WIDTH                         2
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK                        0x1u
+#define I2C_C1_DMAEN_SHIFT                       0
+#define I2C_C1_DMAEN_WIDTH                       1
+#define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_DMAEN_SHIFT))&I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK                         0x2u
+#define I2C_C1_WUEN_SHIFT                        1
+#define I2C_C1_WUEN_WIDTH                        1
+#define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_WUEN_SHIFT))&I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK                         0x4u
+#define I2C_C1_RSTA_SHIFT                        2
+#define I2C_C1_RSTA_WIDTH                        1
+#define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_RSTA_SHIFT))&I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK                         0x8u
+#define I2C_C1_TXAK_SHIFT                        3
+#define I2C_C1_TXAK_WIDTH                        1
+#define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C1_TXAK_SHIFT))&I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK                           0x10u
+#define I2C_C1_TX_SHIFT                          4
+#define I2C_C1_TX_WIDTH                          1
+#define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C1_TX_SHIFT))&I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK                          0x20u
+#define I2C_C1_MST_SHIFT                         5
+#define I2C_C1_MST_WIDTH                         1
+#define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_C1_MST_SHIFT))&I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK                        0x40u
+#define I2C_C1_IICIE_SHIFT                       6
+#define I2C_C1_IICIE_WIDTH                       1
+#define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICIE_SHIFT))&I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK                        0x80u
+#define I2C_C1_IICEN_SHIFT                       7
+#define I2C_C1_IICEN_WIDTH                       1
+#define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICEN_SHIFT))&I2C_C1_IICEN_MASK)
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK                          0x1u
+#define I2C_S_RXAK_SHIFT                         0
+#define I2C_S_RXAK_WIDTH                         1
+#define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_RXAK_SHIFT))&I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK                         0x2u
+#define I2C_S_IICIF_SHIFT                        1
+#define I2C_S_IICIF_WIDTH                        1
+#define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_S_IICIF_SHIFT))&I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK                           0x4u
+#define I2C_S_SRW_SHIFT                          2
+#define I2C_S_SRW_WIDTH                          1
+#define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_SRW_SHIFT))&I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK                           0x8u
+#define I2C_S_RAM_SHIFT                          3
+#define I2C_S_RAM_WIDTH                          1
+#define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_RAM_SHIFT))&I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK                          0x10u
+#define I2C_S_ARBL_SHIFT                         4
+#define I2C_S_ARBL_WIDTH                         1
+#define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_ARBL_SHIFT))&I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK                          0x20u
+#define I2C_S_BUSY_SHIFT                         5
+#define I2C_S_BUSY_WIDTH                         1
+#define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_BUSY_SHIFT))&I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK                          0x40u
+#define I2C_S_IAAS_SHIFT                         6
+#define I2C_S_IAAS_WIDTH                         1
+#define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_S_IAAS_SHIFT))&I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK                           0x80u
+#define I2C_S_TCF_SHIFT                          7
+#define I2C_S_TCF_WIDTH                          1
+#define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_S_TCF_SHIFT))&I2C_S_TCF_MASK)
+/* D Bit Fields */
+#define I2C_D_DATA_MASK                          0xFFu
+#define I2C_D_DATA_SHIFT                         0
+#define I2C_D_DATA_WIDTH                         8
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK                           0x7u
+#define I2C_C2_AD_SHIFT                          0
+#define I2C_C2_AD_WIDTH                          3
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         0x8u
+#define I2C_C2_RMEN_SHIFT                        3
+#define I2C_C2_RMEN_WIDTH                        1
+#define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_RMEN_SHIFT))&I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK                         0x10u
+#define I2C_C2_SBRC_SHIFT                        4
+#define I2C_C2_SBRC_WIDTH                        1
+#define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_SBRC_SHIFT))&I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK                         0x20u
+#define I2C_C2_HDRS_SHIFT                        5
+#define I2C_C2_HDRS_WIDTH                        1
+#define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_C2_HDRS_SHIFT))&I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK                        0x40u
+#define I2C_C2_ADEXT_SHIFT                       6
+#define I2C_C2_ADEXT_WIDTH                       1
+#define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_ADEXT_SHIFT))&I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK                        0x80u
+#define I2C_C2_GCAEN_SHIFT                       7
+#define I2C_C2_GCAEN_WIDTH                       1
+#define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_C2_GCAEN_SHIFT))&I2C_C2_GCAEN_MASK)
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK                         0xFu
+#define I2C_FLT_FLT_SHIFT                        0
+#define I2C_FLT_FLT_WIDTH                        4
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK                      0x10u
+#define I2C_FLT_STARTF_SHIFT                     4
+#define I2C_FLT_STARTF_WIDTH                     1
+#define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STARTF_SHIFT))&I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK                        0x20u
+#define I2C_FLT_SSIE_SHIFT                       5
+#define I2C_FLT_SSIE_WIDTH                       1
+#define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SSIE_SHIFT))&I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK                       0x40u
+#define I2C_FLT_STOPF_SHIFT                      6
+#define I2C_FLT_STOPF_WIDTH                      1
+#define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STOPF_SHIFT))&I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK                        0x80u
+#define I2C_FLT_SHEN_SHIFT                       7
+#define I2C_FLT_SHEN_WIDTH                       1
+#define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SHEN_SHIFT))&I2C_FLT_SHEN_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK                          0xFEu
+#define I2C_RA_RAD_SHIFT                         1
+#define I2C_RA_RAD_WIDTH                         7
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK                     0x1u
+#define I2C_SMB_SHTF2IE_SHIFT                    0
+#define I2C_SMB_SHTF2IE_WIDTH                    1
+#define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2IE_SHIFT))&I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK                       0x2u
+#define I2C_SMB_SHTF2_SHIFT                      1
+#define I2C_SMB_SHTF2_WIDTH                      1
+#define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2_SHIFT))&I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK                       0x4u
+#define I2C_SMB_SHTF1_SHIFT                      2
+#define I2C_SMB_SHTF1_WIDTH                      1
+#define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF1_SHIFT))&I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK                        0x8u
+#define I2C_SMB_SLTF_SHIFT                       3
+#define I2C_SMB_SLTF_WIDTH                       1
+#define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SLTF_SHIFT))&I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK                      0x10u
+#define I2C_SMB_TCKSEL_SHIFT                     4
+#define I2C_SMB_TCKSEL_WIDTH                     1
+#define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x))<<I2C_SMB_TCKSEL_SHIFT))&I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK                     0x20u
+#define I2C_SMB_SIICAEN_SHIFT                    5
+#define I2C_SMB_SIICAEN_WIDTH                    1
+#define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SIICAEN_SHIFT))&I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK                     0x40u
+#define I2C_SMB_ALERTEN_SHIFT                    6
+#define I2C_SMB_ALERTEN_WIDTH                    1
+#define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x))<<I2C_SMB_ALERTEN_SHIFT))&I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK                        0x80u
+#define I2C_SMB_FACK_SHIFT                       7
+#define I2C_SMB_FACK_WIDTH                       1
+#define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x))<<I2C_SMB_FACK_SHIFT))&I2C_SMB_FACK_MASK)
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK                          0xFEu
+#define I2C_A2_SAD_SHIFT                         1
+#define I2C_A2_SAD_WIDTH                         7
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK                       0xFFu
+#define I2C_SLTH_SSLT_SHIFT                      0
+#define I2C_SLTH_SSLT_WIDTH                      8
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK                       0xFFu
+#define I2C_SLTL_SSLT_SHIFT                      0
+#define I2C_SLTL_SSLT_WIDTH                      8
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR                            (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR                            (I2C1)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x400E6000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+#define I2C2_BASE_PTR                            (I2C2)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2C - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1                                  I2C_A1_REG(I2C0)
+#define I2C0_F                                   I2C_F_REG(I2C0)
+#define I2C0_C1                                  I2C_C1_REG(I2C0)
+#define I2C0_S                                   I2C_S_REG(I2C0)
+#define I2C0_D                                   I2C_D_REG(I2C0)
+#define I2C0_C2                                  I2C_C2_REG(I2C0)
+#define I2C0_FLT                                 I2C_FLT_REG(I2C0)
+#define I2C0_RA                                  I2C_RA_REG(I2C0)
+#define I2C0_SMB                                 I2C_SMB_REG(I2C0)
+#define I2C0_A2                                  I2C_A2_REG(I2C0)
+#define I2C0_SLTH                                I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL                                I2C_SLTL_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1                                  I2C_A1_REG(I2C1)
+#define I2C1_F                                   I2C_F_REG(I2C1)
+#define I2C1_C1                                  I2C_C1_REG(I2C1)
+#define I2C1_S                                   I2C_S_REG(I2C1)
+#define I2C1_D                                   I2C_D_REG(I2C1)
+#define I2C1_C2                                  I2C_C2_REG(I2C1)
+#define I2C1_FLT                                 I2C_FLT_REG(I2C1)
+#define I2C1_RA                                  I2C_RA_REG(I2C1)
+#define I2C1_SMB                                 I2C_SMB_REG(I2C1)
+#define I2C1_A2                                  I2C_A2_REG(I2C1)
+#define I2C1_SLTH                                I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL                                I2C_SLTL_REG(I2C1)
+/* I2C2 */
+#define I2C2_A1                                  I2C_A1_REG(I2C2)
+#define I2C2_F                                   I2C_F_REG(I2C2)
+#define I2C2_C1                                  I2C_C1_REG(I2C2)
+#define I2C2_S                                   I2C_S_REG(I2C2)
+#define I2C2_D                                   I2C_D_REG(I2C2)
+#define I2C2_C2                                  I2C_C2_REG(I2C2)
+#define I2C2_FLT                                 I2C_FLT_REG(I2C2)
+#define I2C2_RA                                  I2C_RA_REG(I2C2)
+#define I2C2_SMB                                 I2C_SMB_REG(I2C2)
+#define I2C2_A2                                  I2C_A2_REG(I2C2)
+#define I2C2_SLTH                                I2C_SLTH_REG(I2C2)
+#define I2C2_SLTL                                I2C_SLTL_REG(I2C2)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
+  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t TDR[2];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __I  uint32_t TFR[2];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_3[28];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
+  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t RDR[2];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[24];
+  __I  uint32_t RFR[2];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_6[24];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
+  __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base)                       ((base)->TCSR)
+#define I2S_TCR1_REG(base)                       ((base)->TCR1)
+#define I2S_TCR2_REG(base)                       ((base)->TCR2)
+#define I2S_TCR3_REG(base)                       ((base)->TCR3)
+#define I2S_TCR4_REG(base)                       ((base)->TCR4)
+#define I2S_TCR5_REG(base)                       ((base)->TCR5)
+#define I2S_TDR_REG(base,index)                  ((base)->TDR[index])
+#define I2S_TDR_COUNT                            2
+#define I2S_TFR_REG(base,index)                  ((base)->TFR[index])
+#define I2S_TFR_COUNT                            2
+#define I2S_TMR_REG(base)                        ((base)->TMR)
+#define I2S_RCSR_REG(base)                       ((base)->RCSR)
+#define I2S_RCR1_REG(base)                       ((base)->RCR1)
+#define I2S_RCR2_REG(base)                       ((base)->RCR2)
+#define I2S_RCR3_REG(base)                       ((base)->RCR3)
+#define I2S_RCR4_REG(base)                       ((base)->RCR4)
+#define I2S_RCR5_REG(base)                       ((base)->RCR5)
+#define I2S_RDR_REG(base,index)                  ((base)->RDR[index])
+#define I2S_RDR_COUNT                            2
+#define I2S_RFR_REG(base,index)                  ((base)->RFR[index])
+#define I2S_RFR_COUNT                            2
+#define I2S_RMR_REG(base)                        ((base)->RMR)
+#define I2S_MCR_REG(base)                        ((base)->MCR)
+#define I2S_MDR_REG(base)                        ((base)->MDR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK                       0x1u
+#define I2S_TCSR_FRDE_SHIFT                      0
+#define I2S_TCSR_FRDE_WIDTH                      1
+#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRDE_SHIFT))&I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK                       0x2u
+#define I2S_TCSR_FWDE_SHIFT                      1
+#define I2S_TCSR_FWDE_WIDTH                      1
+#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK                       0x100u
+#define I2S_TCSR_FRIE_SHIFT                      8
+#define I2S_TCSR_FRIE_WIDTH                      1
+#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRIE_SHIFT))&I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK                       0x200u
+#define I2S_TCSR_FWIE_SHIFT                      9
+#define I2S_TCSR_FWIE_WIDTH                      1
+#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK                       0x400u
+#define I2S_TCSR_FEIE_SHIFT                      10
+#define I2S_TCSR_FEIE_WIDTH                      1
+#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK                       0x800u
+#define I2S_TCSR_SEIE_SHIFT                      11
+#define I2S_TCSR_SEIE_WIDTH                      1
+#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK                       0x1000u
+#define I2S_TCSR_WSIE_SHIFT                      12
+#define I2S_TCSR_WSIE_WIDTH                      1
+#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK                        0x10000u
+#define I2S_TCSR_FRF_SHIFT                       16
+#define I2S_TCSR_FRF_WIDTH                       1
+#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRF_SHIFT))&I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK                        0x20000u
+#define I2S_TCSR_FWF_SHIFT                       17
+#define I2S_TCSR_FWF_WIDTH                       1
+#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK                        0x40000u
+#define I2S_TCSR_FEF_SHIFT                       18
+#define I2S_TCSR_FEF_WIDTH                       1
+#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK                        0x80000u
+#define I2S_TCSR_SEF_SHIFT                       19
+#define I2S_TCSR_SEF_WIDTH                       1
+#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK                        0x100000u
+#define I2S_TCSR_WSF_SHIFT                       20
+#define I2S_TCSR_WSF_WIDTH                       1
+#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK                         0x1000000u
+#define I2S_TCSR_SR_SHIFT                        24
+#define I2S_TCSR_SR_WIDTH                        1
+#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK                         0x2000000u
+#define I2S_TCSR_FR_SHIFT                        25
+#define I2S_TCSR_FR_WIDTH                        1
+#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK                        0x10000000u
+#define I2S_TCSR_BCE_SHIFT                       28
+#define I2S_TCSR_BCE_WIDTH                       1
+#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK                       0x20000000u
+#define I2S_TCSR_DBGE_SHIFT                      29
+#define I2S_TCSR_DBGE_WIDTH                      1
+#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK                      0x40000000u
+#define I2S_TCSR_STOPE_SHIFT                     30
+#define I2S_TCSR_STOPE_WIDTH                     1
+#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK                         0x80000000u
+#define I2S_TCSR_TE_SHIFT                        31
+#define I2S_TCSR_TE_WIDTH                        1
+#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK                        0x7u
+#define I2S_TCR1_TFW_SHIFT                       0
+#define I2S_TCR1_TFW_WIDTH                       3
+#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK                        0xFFu
+#define I2S_TCR2_DIV_SHIFT                       0
+#define I2S_TCR2_DIV_WIDTH                       8
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        0x1000000u
+#define I2S_TCR2_BCD_SHIFT                       24
+#define I2S_TCR2_BCD_WIDTH                       1
+#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK                        0x2000000u
+#define I2S_TCR2_BCP_SHIFT                       25
+#define I2S_TCR2_BCP_WIDTH                       1
+#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK                       0xC000000u
+#define I2S_TCR2_MSEL_SHIFT                      26
+#define I2S_TCR2_MSEL_WIDTH                      2
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK                        0x10000000u
+#define I2S_TCR2_BCI_SHIFT                       28
+#define I2S_TCR2_BCI_WIDTH                       1
+#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK                        0x20000000u
+#define I2S_TCR2_BCS_SHIFT                       29
+#define I2S_TCR2_BCS_WIDTH                       1
+#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK                       0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT                      30
+#define I2S_TCR2_SYNC_WIDTH                      2
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK                       0x1Fu
+#define I2S_TCR3_WDFL_SHIFT                      0
+#define I2S_TCR3_WDFL_WIDTH                      5
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        0x30000u
+#define I2S_TCR3_TCE_SHIFT                       16
+#define I2S_TCR3_TCE_WIDTH                       2
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK                        0x1u
+#define I2S_TCR4_FSD_SHIFT                       0
+#define I2S_TCR4_FSD_WIDTH                       1
+#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK                        0x2u
+#define I2S_TCR4_FSP_SHIFT                       1
+#define I2S_TCR4_FSP_WIDTH                       1
+#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSE_MASK                        0x8u
+#define I2S_TCR4_FSE_SHIFT                       3
+#define I2S_TCR4_FSE_WIDTH                       1
+#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK                         0x10u
+#define I2S_TCR4_MF_SHIFT                        4
+#define I2S_TCR4_MF_WIDTH                        1
+#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK                       0x1F00u
+#define I2S_TCR4_SYWD_SHIFT                      8
+#define I2S_TCR4_SYWD_WIDTH                      5
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT                      16
+#define I2S_TCR4_FRSZ_WIDTH                      5
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK                        0x1F00u
+#define I2S_TCR5_FBT_SHIFT                       8
+#define I2S_TCR5_FBT_WIDTH                       5
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        0x1F0000u
+#define I2S_TCR5_W0W_SHIFT                       16
+#define I2S_TCR5_W0W_WIDTH                       5
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        0x1F000000u
+#define I2S_TCR5_WNW_SHIFT                       24
+#define I2S_TCR5_WNW_WIDTH                       5
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT                        0
+#define I2S_TDR_TDR_WIDTH                        32
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK                         0xFu
+#define I2S_TFR_RFP_SHIFT                        0
+#define I2S_TFR_RFP_WIDTH                        4
+#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK                         0xF0000u
+#define I2S_TFR_WFP_SHIFT                        16
+#define I2S_TFR_WFP_WIDTH                        4
+#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK                         0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT                        0
+#define I2S_TMR_TWM_WIDTH                        32
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK                       0x1u
+#define I2S_RCSR_FRDE_SHIFT                      0
+#define I2S_RCSR_FRDE_WIDTH                      1
+#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRDE_SHIFT))&I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK                       0x2u
+#define I2S_RCSR_FWDE_SHIFT                      1
+#define I2S_RCSR_FWDE_WIDTH                      1
+#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK                       0x100u
+#define I2S_RCSR_FRIE_SHIFT                      8
+#define I2S_RCSR_FRIE_WIDTH                      1
+#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRIE_SHIFT))&I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK                       0x200u
+#define I2S_RCSR_FWIE_SHIFT                      9
+#define I2S_RCSR_FWIE_WIDTH                      1
+#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK                       0x400u
+#define I2S_RCSR_FEIE_SHIFT                      10
+#define I2S_RCSR_FEIE_WIDTH                      1
+#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK                       0x800u
+#define I2S_RCSR_SEIE_SHIFT                      11
+#define I2S_RCSR_SEIE_WIDTH                      1
+#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK                       0x1000u
+#define I2S_RCSR_WSIE_SHIFT                      12
+#define I2S_RCSR_WSIE_WIDTH                      1
+#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK                        0x10000u
+#define I2S_RCSR_FRF_SHIFT                       16
+#define I2S_RCSR_FRF_WIDTH                       1
+#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRF_SHIFT))&I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK                        0x20000u
+#define I2S_RCSR_FWF_SHIFT                       17
+#define I2S_RCSR_FWF_WIDTH                       1
+#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK                        0x40000u
+#define I2S_RCSR_FEF_SHIFT                       18
+#define I2S_RCSR_FEF_WIDTH                       1
+#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK                        0x80000u
+#define I2S_RCSR_SEF_SHIFT                       19
+#define I2S_RCSR_SEF_WIDTH                       1
+#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK                        0x100000u
+#define I2S_RCSR_WSF_SHIFT                       20
+#define I2S_RCSR_WSF_WIDTH                       1
+#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK                         0x1000000u
+#define I2S_RCSR_SR_SHIFT                        24
+#define I2S_RCSR_SR_WIDTH                        1
+#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK                         0x2000000u
+#define I2S_RCSR_FR_SHIFT                        25
+#define I2S_RCSR_FR_WIDTH                        1
+#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK                        0x10000000u
+#define I2S_RCSR_BCE_SHIFT                       28
+#define I2S_RCSR_BCE_WIDTH                       1
+#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK                       0x20000000u
+#define I2S_RCSR_DBGE_SHIFT                      29
+#define I2S_RCSR_DBGE_WIDTH                      1
+#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK                      0x40000000u
+#define I2S_RCSR_STOPE_SHIFT                     30
+#define I2S_RCSR_STOPE_WIDTH                     1
+#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK                         0x80000000u
+#define I2S_RCSR_RE_SHIFT                        31
+#define I2S_RCSR_RE_WIDTH                        1
+#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK                        0x7u
+#define I2S_RCR1_RFW_SHIFT                       0
+#define I2S_RCR1_RFW_WIDTH                       3
+#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK                        0xFFu
+#define I2S_RCR2_DIV_SHIFT                       0
+#define I2S_RCR2_DIV_WIDTH                       8
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        0x1000000u
+#define I2S_RCR2_BCD_SHIFT                       24
+#define I2S_RCR2_BCD_WIDTH                       1
+#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK                        0x2000000u
+#define I2S_RCR2_BCP_SHIFT                       25
+#define I2S_RCR2_BCP_WIDTH                       1
+#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK                       0xC000000u
+#define I2S_RCR2_MSEL_SHIFT                      26
+#define I2S_RCR2_MSEL_WIDTH                      2
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK                        0x10000000u
+#define I2S_RCR2_BCI_SHIFT                       28
+#define I2S_RCR2_BCI_WIDTH                       1
+#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK                        0x20000000u
+#define I2S_RCR2_BCS_SHIFT                       29
+#define I2S_RCR2_BCS_WIDTH                       1
+#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK                       0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT                      30
+#define I2S_RCR2_SYNC_WIDTH                      2
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK                       0x1Fu
+#define I2S_RCR3_WDFL_SHIFT                      0
+#define I2S_RCR3_WDFL_WIDTH                      5
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        0x30000u
+#define I2S_RCR3_RCE_SHIFT                       16
+#define I2S_RCR3_RCE_WIDTH                       2
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK                        0x1u
+#define I2S_RCR4_FSD_SHIFT                       0
+#define I2S_RCR4_FSD_WIDTH                       1
+#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK                        0x2u
+#define I2S_RCR4_FSP_SHIFT                       1
+#define I2S_RCR4_FSP_WIDTH                       1
+#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSE_MASK                        0x8u
+#define I2S_RCR4_FSE_SHIFT                       3
+#define I2S_RCR4_FSE_WIDTH                       1
+#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK                         0x10u
+#define I2S_RCR4_MF_SHIFT                        4
+#define I2S_RCR4_MF_WIDTH                        1
+#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK                       0x1F00u
+#define I2S_RCR4_SYWD_SHIFT                      8
+#define I2S_RCR4_SYWD_WIDTH                      5
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT                      16
+#define I2S_RCR4_FRSZ_WIDTH                      5
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK                        0x1F00u
+#define I2S_RCR5_FBT_SHIFT                       8
+#define I2S_RCR5_FBT_WIDTH                       5
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        0x1F0000u
+#define I2S_RCR5_W0W_SHIFT                       16
+#define I2S_RCR5_W0W_WIDTH                       5
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        0x1F000000u
+#define I2S_RCR5_WNW_SHIFT                       24
+#define I2S_RCR5_WNW_WIDTH                       5
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT                        0
+#define I2S_RDR_RDR_WIDTH                        32
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK                         0xFu
+#define I2S_RFR_RFP_SHIFT                        0
+#define I2S_RFR_RFP_WIDTH                        4
+#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK                         0xF0000u
+#define I2S_RFR_WFP_SHIFT                        16
+#define I2S_RFR_WFP_WIDTH                        4
+#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK                         0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT                        0
+#define I2S_RMR_RWM_WIDTH                        32
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK                        0x3000000u
+#define I2S_MCR_MICS_SHIFT                       24
+#define I2S_MCR_MICS_WIDTH                       2
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK                         0x40000000u
+#define I2S_MCR_MOE_SHIFT                        30
+#define I2S_MCR_MOE_WIDTH                        1
+#define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MOE_SHIFT))&I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK                         0x80000000u
+#define I2S_MCR_DUF_SHIFT                        31
+#define I2S_MCR_DUF_WIDTH                        1
+#define I2S_MCR_DUF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_DUF_SHIFT))&I2S_MCR_DUF_MASK)
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK                      0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT                     0
+#define I2S_MDR_DIVIDE_WIDTH                     12
+#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK                       0xFF000u
+#define I2S_MDR_FRACT_SHIFT                      12
+#define I2S_MDR_FRACT_WIDTH                      8
+#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR                            (I2S0)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS                              { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS                              { I2S0_Tx_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- I2S - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR                                I2S_TCSR_REG(I2S0)
+#define I2S0_TCR1                                I2S_TCR1_REG(I2S0)
+#define I2S0_TCR2                                I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3                                I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4                                I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5                                I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0                                I2S_TDR_REG(I2S0,0)
+#define I2S0_TDR1                                I2S_TDR_REG(I2S0,1)
+#define I2S0_TFR0                                I2S_TFR_REG(I2S0,0)
+#define I2S0_TFR1                                I2S_TFR_REG(I2S0,1)
+#define I2S0_TMR                                 I2S_TMR_REG(I2S0)
+#define I2S0_RCSR                                I2S_RCSR_REG(I2S0)
+#define I2S0_RCR1                                I2S_RCR1_REG(I2S0)
+#define I2S0_RCR2                                I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3                                I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4                                I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5                                I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0                                I2S_RDR_REG(I2S0,0)
+#define I2S0_RDR1                                I2S_RDR_REG(I2S0,1)
+#define I2S0_RFR0                                I2S_RFR_REG(I2S0,0)
+#define I2S0_RFR1                                I2S_RFR_REG(I2S0,1)
+#define I2S0_RMR                                 I2S_RMR_REG(I2S0)
+#define I2S0_MCR                                 I2S_MCR_REG(I2S0)
+#define I2S0_MDR                                 I2S_MDR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index)                          I2S_TDR_REG(I2S0,index)
+#define I2S0_TFR(index)                          I2S_TFR_REG(I2S0,index)
+#define I2S0_RDR(index)                          I2S_RDR_REG(I2S0,index)
+#define I2S0_RFR(index)                          I2S_RFR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
+  __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
+  __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
+  __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
+  __IO uint8_t RST;                                /**< LLWU Reset Enable register, offset: 0xA */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base)                       ((base)->PE1)
+#define LLWU_PE2_REG(base)                       ((base)->PE2)
+#define LLWU_PE3_REG(base)                       ((base)->PE3)
+#define LLWU_PE4_REG(base)                       ((base)->PE4)
+#define LLWU_ME_REG(base)                        ((base)->ME)
+#define LLWU_F1_REG(base)                        ((base)->F1)
+#define LLWU_F2_REG(base)                        ((base)->F2)
+#define LLWU_F3_REG(base)                        ((base)->F3)
+#define LLWU_FILT1_REG(base)                     ((base)->FILT1)
+#define LLWU_FILT2_REG(base)                     ((base)->FILT2)
+#define LLWU_RST_REG(base)                       ((base)->RST)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK                      0x3u
+#define LLWU_PE1_WUPE0_SHIFT                     0
+#define LLWU_PE1_WUPE0_WIDTH                     2
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      0xCu
+#define LLWU_PE1_WUPE1_SHIFT                     2
+#define LLWU_PE1_WUPE1_WIDTH                     2
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      0x30u
+#define LLWU_PE1_WUPE2_SHIFT                     4
+#define LLWU_PE1_WUPE2_WIDTH                     2
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      0xC0u
+#define LLWU_PE1_WUPE3_SHIFT                     6
+#define LLWU_PE1_WUPE3_WIDTH                     2
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK                      0x3u
+#define LLWU_PE2_WUPE4_SHIFT                     0
+#define LLWU_PE2_WUPE4_WIDTH                     2
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      0xCu
+#define LLWU_PE2_WUPE5_SHIFT                     2
+#define LLWU_PE2_WUPE5_WIDTH                     2
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      0x30u
+#define LLWU_PE2_WUPE6_SHIFT                     4
+#define LLWU_PE2_WUPE6_WIDTH                     2
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      0xC0u
+#define LLWU_PE2_WUPE7_SHIFT                     6
+#define LLWU_PE2_WUPE7_WIDTH                     2
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK                      0x3u
+#define LLWU_PE3_WUPE8_SHIFT                     0
+#define LLWU_PE3_WUPE8_WIDTH                     2
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      0xCu
+#define LLWU_PE3_WUPE9_SHIFT                     2
+#define LLWU_PE3_WUPE9_WIDTH                     2
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     0x30u
+#define LLWU_PE3_WUPE10_SHIFT                    4
+#define LLWU_PE3_WUPE10_WIDTH                    2
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     0xC0u
+#define LLWU_PE3_WUPE11_SHIFT                    6
+#define LLWU_PE3_WUPE11_WIDTH                    2
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK                     0x3u
+#define LLWU_PE4_WUPE12_SHIFT                    0
+#define LLWU_PE4_WUPE12_WIDTH                    2
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     0xCu
+#define LLWU_PE4_WUPE13_SHIFT                    2
+#define LLWU_PE4_WUPE13_WIDTH                    2
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     0x30u
+#define LLWU_PE4_WUPE14_SHIFT                    4
+#define LLWU_PE4_WUPE14_WIDTH                    2
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     0xC0u
+#define LLWU_PE4_WUPE15_SHIFT                    6
+#define LLWU_PE4_WUPE15_WIDTH                    2
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK                       0x1u
+#define LLWU_ME_WUME0_SHIFT                      0
+#define LLWU_ME_WUME0_WIDTH                      1
+#define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK                       0x2u
+#define LLWU_ME_WUME1_SHIFT                      1
+#define LLWU_ME_WUME1_WIDTH                      1
+#define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK                       0x4u
+#define LLWU_ME_WUME2_SHIFT                      2
+#define LLWU_ME_WUME2_WIDTH                      1
+#define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK                       0x8u
+#define LLWU_ME_WUME3_SHIFT                      3
+#define LLWU_ME_WUME3_WIDTH                      1
+#define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK                       0x10u
+#define LLWU_ME_WUME4_SHIFT                      4
+#define LLWU_ME_WUME4_WIDTH                      1
+#define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK                       0x20u
+#define LLWU_ME_WUME5_SHIFT                      5
+#define LLWU_ME_WUME5_WIDTH                      1
+#define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK                       0x40u
+#define LLWU_ME_WUME6_SHIFT                      6
+#define LLWU_ME_WUME6_WIDTH                      1
+#define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK                       0x80u
+#define LLWU_ME_WUME7_SHIFT                      7
+#define LLWU_ME_WUME7_WIDTH                      1
+#define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK                        0x1u
+#define LLWU_F1_WUF0_SHIFT                       0
+#define LLWU_F1_WUF0_WIDTH                       1
+#define LLWU_F1_WUF0(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF0_SHIFT))&LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK                        0x2u
+#define LLWU_F1_WUF1_SHIFT                       1
+#define LLWU_F1_WUF1_WIDTH                       1
+#define LLWU_F1_WUF1(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF1_SHIFT))&LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK                        0x4u
+#define LLWU_F1_WUF2_SHIFT                       2
+#define LLWU_F1_WUF2_WIDTH                       1
+#define LLWU_F1_WUF2(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF2_SHIFT))&LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK                        0x8u
+#define LLWU_F1_WUF3_SHIFT                       3
+#define LLWU_F1_WUF3_WIDTH                       1
+#define LLWU_F1_WUF3(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF3_SHIFT))&LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK                        0x10u
+#define LLWU_F1_WUF4_SHIFT                       4
+#define LLWU_F1_WUF4_WIDTH                       1
+#define LLWU_F1_WUF4(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF4_SHIFT))&LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK                        0x20u
+#define LLWU_F1_WUF5_SHIFT                       5
+#define LLWU_F1_WUF5_WIDTH                       1
+#define LLWU_F1_WUF5(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF5_SHIFT))&LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK                        0x40u
+#define LLWU_F1_WUF6_SHIFT                       6
+#define LLWU_F1_WUF6_WIDTH                       1
+#define LLWU_F1_WUF6(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF6_SHIFT))&LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK                        0x80u
+#define LLWU_F1_WUF7_SHIFT                       7
+#define LLWU_F1_WUF7_WIDTH                       1
+#define LLWU_F1_WUF7(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF7_SHIFT))&LLWU_F1_WUF7_MASK)
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK                        0x1u
+#define LLWU_F2_WUF8_SHIFT                       0
+#define LLWU_F2_WUF8_WIDTH                       1
+#define LLWU_F2_WUF8(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF8_SHIFT))&LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK                        0x2u
+#define LLWU_F2_WUF9_SHIFT                       1
+#define LLWU_F2_WUF9_WIDTH                       1
+#define LLWU_F2_WUF9(x)                          (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF9_SHIFT))&LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK                       0x4u
+#define LLWU_F2_WUF10_SHIFT                      2
+#define LLWU_F2_WUF10_WIDTH                      1
+#define LLWU_F2_WUF10(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF10_SHIFT))&LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK                       0x8u
+#define LLWU_F2_WUF11_SHIFT                      3
+#define LLWU_F2_WUF11_WIDTH                      1
+#define LLWU_F2_WUF11(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF11_SHIFT))&LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK                       0x10u
+#define LLWU_F2_WUF12_SHIFT                      4
+#define LLWU_F2_WUF12_WIDTH                      1
+#define LLWU_F2_WUF12(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF12_SHIFT))&LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK                       0x20u
+#define LLWU_F2_WUF13_SHIFT                      5
+#define LLWU_F2_WUF13_WIDTH                      1
+#define LLWU_F2_WUF13(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF13_SHIFT))&LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK                       0x40u
+#define LLWU_F2_WUF14_SHIFT                      6
+#define LLWU_F2_WUF14_WIDTH                      1
+#define LLWU_F2_WUF14(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF14_SHIFT))&LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK                       0x80u
+#define LLWU_F2_WUF15_SHIFT                      7
+#define LLWU_F2_WUF15_WIDTH                      1
+#define LLWU_F2_WUF15(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF15_SHIFT))&LLWU_F2_WUF15_MASK)
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK                       0x1u
+#define LLWU_F3_MWUF0_SHIFT                      0
+#define LLWU_F3_MWUF0_WIDTH                      1
+#define LLWU_F3_MWUF0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF0_SHIFT))&LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK                       0x2u
+#define LLWU_F3_MWUF1_SHIFT                      1
+#define LLWU_F3_MWUF1_WIDTH                      1
+#define LLWU_F3_MWUF1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF1_SHIFT))&LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK                       0x4u
+#define LLWU_F3_MWUF2_SHIFT                      2
+#define LLWU_F3_MWUF2_WIDTH                      1
+#define LLWU_F3_MWUF2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF2_SHIFT))&LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK                       0x8u
+#define LLWU_F3_MWUF3_SHIFT                      3
+#define LLWU_F3_MWUF3_WIDTH                      1
+#define LLWU_F3_MWUF3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF3_SHIFT))&LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK                       0x10u
+#define LLWU_F3_MWUF4_SHIFT                      4
+#define LLWU_F3_MWUF4_WIDTH                      1
+#define LLWU_F3_MWUF4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF4_SHIFT))&LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK                       0x20u
+#define LLWU_F3_MWUF5_SHIFT                      5
+#define LLWU_F3_MWUF5_WIDTH                      1
+#define LLWU_F3_MWUF5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF5_SHIFT))&LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK                       0x40u
+#define LLWU_F3_MWUF6_SHIFT                      6
+#define LLWU_F3_MWUF6_WIDTH                      1
+#define LLWU_F3_MWUF6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF6_SHIFT))&LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK                       0x80u
+#define LLWU_F3_MWUF7_SHIFT                      7
+#define LLWU_F3_MWUF7_WIDTH                      1
+#define LLWU_F3_MWUF7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF7_SHIFT))&LLWU_F3_MWUF7_MASK)
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK                  0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT                 0
+#define LLWU_FILT1_FILTSEL_WIDTH                 4
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    0x60u
+#define LLWU_FILT1_FILTE_SHIFT                   5
+#define LLWU_FILT1_FILTE_WIDTH                   2
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK                    0x80u
+#define LLWU_FILT1_FILTF_SHIFT                   7
+#define LLWU_FILT1_FILTF_WIDTH                   1
+#define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK                  0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT                 0
+#define LLWU_FILT2_FILTSEL_WIDTH                 4
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    0x60u
+#define LLWU_FILT2_FILTE_SHIFT                   5
+#define LLWU_FILT2_FILTE_WIDTH                   2
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK                    0x80u
+#define LLWU_FILT2_FILTF_SHIFT                   7
+#define LLWU_FILT2_FILTF_WIDTH                   1
+#define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK                    0x1u
+#define LLWU_RST_RSTFILT_SHIFT                   0
+#define LLWU_RST_RSTFILT_WIDTH                   1
+#define LLWU_RST_RSTFILT(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_RST_RSTFILT_SHIFT))&LLWU_RST_RSTFILT_MASK)
+#define LLWU_RST_LLRSTE_MASK                     0x2u
+#define LLWU_RST_LLRSTE_SHIFT                    1
+#define LLWU_RST_LLRSTE_WIDTH                    1
+#define LLWU_RST_LLRSTE(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_RST_LLRSTE_SHIFT))&LLWU_RST_LLRSTE_MASK)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR                            (LLWU)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LLWU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1                                 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2                                 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3                                 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4                                 LLWU_PE4_REG(LLWU)
+#define LLWU_ME                                  LLWU_ME_REG(LLWU)
+#define LLWU_F1                                  LLWU_F1_REG(LLWU)
+#define LLWU_F2                                  LLWU_F2_REG(LLWU)
+#define LLWU_F3                                  LLWU_F3_REG(LLWU)
+#define LLWU_FILT1                               LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2                               LLWU_FILT2_REG(LLWU)
+#define LLWU_RST                                 LLWU_RST_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base)                      ((base)->CSR)
+#define LPTMR_PSR_REG(base)                      ((base)->PSR)
+#define LPTMR_CMR_REG(base)                      ((base)->CMR)
+#define LPTMR_CNR_REG(base)                      ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK                       0x1u
+#define LPTMR_CSR_TEN_SHIFT                      0
+#define LPTMR_CSR_TEN_WIDTH                      1
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK                       0x2u
+#define LPTMR_CSR_TMS_SHIFT                      1
+#define LPTMR_CSR_TMS_WIDTH                      1
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK                       0x4u
+#define LPTMR_CSR_TFC_SHIFT                      2
+#define LPTMR_CSR_TFC_WIDTH                      1
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK                       0x8u
+#define LPTMR_CSR_TPP_SHIFT                      3
+#define LPTMR_CSR_TPP_WIDTH                      1
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK                       0x30u
+#define LPTMR_CSR_TPS_SHIFT                      4
+#define LPTMR_CSR_TPS_WIDTH                      2
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       0x40u
+#define LPTMR_CSR_TIE_SHIFT                      6
+#define LPTMR_CSR_TIE_WIDTH                      1
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK                       0x80u
+#define LPTMR_CSR_TCF_SHIFT                      7
+#define LPTMR_CSR_TCF_WIDTH                      1
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK                       0x3u
+#define LPTMR_PSR_PCS_SHIFT                      0
+#define LPTMR_PSR_PCS_WIDTH                      2
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      0x4u
+#define LPTMR_PSR_PBYP_SHIFT                     2
+#define LPTMR_PSR_PBYP_WIDTH                     1
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK                  0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT                 3
+#define LPTMR_PSR_PRESCALE_WIDTH                 4
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT                  0
+#define LPTMR_CMR_COMPARE_WIDTH                  16
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT                  0
+#define LPTMR_CNR_COUNTER_WIDTH                  16
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR                          (LPTMR0)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR                               LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR                               LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR                               LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR                               LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
+  __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
+  __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
+  __IO uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+  __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+  __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
+  __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base)                         ((base)->C1)
+#define MCG_C2_REG(base)                         ((base)->C2)
+#define MCG_C3_REG(base)                         ((base)->C3)
+#define MCG_C4_REG(base)                         ((base)->C4)
+#define MCG_C5_REG(base)                         ((base)->C5)
+#define MCG_C6_REG(base)                         ((base)->C6)
+#define MCG_S_REG(base)                          ((base)->S)
+#define MCG_SC_REG(base)                         ((base)->SC)
+#define MCG_ATCVH_REG(base)                      ((base)->ATCVH)
+#define MCG_ATCVL_REG(base)                      ((base)->ATCVL)
+#define MCG_C7_REG(base)                         ((base)->C7)
+#define MCG_C8_REG(base)                         ((base)->C8)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK                     0x1u
+#define MCG_C1_IREFSTEN_SHIFT                    0
+#define MCG_C1_IREFSTEN_WIDTH                    1
+#define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK                      0x2u
+#define MCG_C1_IRCLKEN_SHIFT                     1
+#define MCG_C1_IRCLKEN_WIDTH                     1
+#define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK                        0x4u
+#define MCG_C1_IREFS_SHIFT                       2
+#define MCG_C1_IREFS_WIDTH                       1
+#define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFS_SHIFT))&MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK                        0x38u
+#define MCG_C1_FRDIV_SHIFT                       3
+#define MCG_C1_FRDIV_WIDTH                       3
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         0xC0u
+#define MCG_C1_CLKS_SHIFT                        6
+#define MCG_C1_CLKS_WIDTH                        2
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK                         0x1u
+#define MCG_C2_IRCS_SHIFT                        0
+#define MCG_C2_IRCS_WIDTH                        1
+#define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK                           0x2u
+#define MCG_C2_LP_SHIFT                          1
+#define MCG_C2_LP_WIDTH                          1
+#define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x))<<MCG_C2_LP_SHIFT))&MCG_C2_LP_MASK)
+#define MCG_C2_EREFS_MASK                        0x4u
+#define MCG_C2_EREFS_SHIFT                       2
+#define MCG_C2_EREFS_WIDTH                       1
+#define MCG_C2_EREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS_SHIFT))&MCG_C2_EREFS_MASK)
+#define MCG_C2_HGO_MASK                          0x8u
+#define MCG_C2_HGO_SHIFT                         3
+#define MCG_C2_HGO_WIDTH                         1
+#define MCG_C2_HGO(x)                            (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO_SHIFT))&MCG_C2_HGO_MASK)
+#define MCG_C2_RANGE_MASK                        0x30u
+#define MCG_C2_RANGE_SHIFT                       4
+#define MCG_C2_RANGE_WIDTH                       2
+#define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK                      0x40u
+#define MCG_C2_FCFTRIM_SHIFT                     6
+#define MCG_C2_FCFTRIM_WIDTH                     1
+#define MCG_C2_FCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C2_FCFTRIM_SHIFT))&MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK                       0x80u
+#define MCG_C2_LOCRE0_SHIFT                      7
+#define MCG_C2_LOCRE0_WIDTH                      1
+#define MCG_C2_LOCRE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_LOCRE0_SHIFT))&MCG_C2_LOCRE0_MASK)
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK                       0xFFu
+#define MCG_C3_SCTRIM_SHIFT                      0
+#define MCG_C3_SCTRIM_WIDTH                      8
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK                      0x1u
+#define MCG_C4_SCFTRIM_SHIFT                     0
+#define MCG_C4_SCFTRIM_WIDTH                     1
+#define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C4_SCFTRIM_SHIFT))&MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK                       0x1Eu
+#define MCG_C4_FCTRIM_SHIFT                      1
+#define MCG_C4_FCTRIM_WIDTH                      4
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     0x60u
+#define MCG_C4_DRST_DRS_SHIFT                    5
+#define MCG_C4_DRST_DRS_WIDTH                    2
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK                        0x80u
+#define MCG_C4_DMX32_SHIFT                       7
+#define MCG_C4_DMX32_WIDTH                       1
+#define MCG_C4_DMX32(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C4_DMX32_SHIFT))&MCG_C4_DMX32_MASK)
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK                       0x1Fu
+#define MCG_C5_PRDIV0_SHIFT                      0
+#define MCG_C5_PRDIV0_WIDTH                      5
+#define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK                     0x20u
+#define MCG_C5_PLLSTEN0_SHIFT                    5
+#define MCG_C5_PLLSTEN0_WIDTH                    1
+#define MCG_C5_PLLSTEN0(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLSTEN0_SHIFT))&MCG_C5_PLLSTEN0_MASK)
+#define MCG_C5_PLLCLKEN0_MASK                    0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT                   6
+#define MCG_C5_PLLCLKEN0_WIDTH                   1
+#define MCG_C5_PLLCLKEN0(x)                      (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLCLKEN0_SHIFT))&MCG_C5_PLLCLKEN0_MASK)
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK                        0x1Fu
+#define MCG_C6_VDIV0_SHIFT                       0
+#define MCG_C6_VDIV0_WIDTH                       5
+#define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK                         0x20u
+#define MCG_C6_CME0_SHIFT                        5
+#define MCG_C6_CME0_WIDTH                        1
+#define MCG_C6_CME0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_CME0_SHIFT))&MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK                         0x40u
+#define MCG_C6_PLLS_SHIFT                        6
+#define MCG_C6_PLLS_WIDTH                        1
+#define MCG_C6_PLLS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_PLLS_SHIFT))&MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK                       0x80u
+#define MCG_C6_LOLIE0_SHIFT                      7
+#define MCG_C6_LOLIE0_WIDTH                      1
+#define MCG_C6_LOLIE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C6_LOLIE0_SHIFT))&MCG_C6_LOLIE0_MASK)
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK                         0x1u
+#define MCG_S_IRCST_SHIFT                        0
+#define MCG_S_IRCST_WIDTH                        1
+#define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_IRCST_SHIFT))&MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK                      0x2u
+#define MCG_S_OSCINIT0_SHIFT                     1
+#define MCG_S_OSCINIT0_WIDTH                     1
+#define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK                         0xCu
+#define MCG_S_CLKST_SHIFT                        2
+#define MCG_S_CLKST_WIDTH                        2
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK                        0x10u
+#define MCG_S_IREFST_SHIFT                       4
+#define MCG_S_IREFST_WIDTH                       1
+#define MCG_S_IREFST(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_S_IREFST_SHIFT))&MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK                         0x20u
+#define MCG_S_PLLST_SHIFT                        5
+#define MCG_S_PLLST_WIDTH                        1
+#define MCG_S_PLLST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_PLLST_SHIFT))&MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK                         0x40u
+#define MCG_S_LOCK0_SHIFT                        6
+#define MCG_S_LOCK0_WIDTH                        1
+#define MCG_S_LOCK0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOCK0_SHIFT))&MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK                         0x80u
+#define MCG_S_LOLS0_SHIFT                        7
+#define MCG_S_LOLS0_WIDTH                        1
+#define MCG_S_LOLS0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOLS0_SHIFT))&MCG_S_LOLS0_MASK)
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK                        0x1u
+#define MCG_SC_LOCS0_SHIFT                       0
+#define MCG_SC_LOCS0_WIDTH                       1
+#define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_SC_LOCS0_SHIFT))&MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK                       0xEu
+#define MCG_SC_FCRDIV_SHIFT                      1
+#define MCG_SC_FCRDIV_WIDTH                      3
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK                     0x10u
+#define MCG_SC_FLTPRSRV_SHIFT                    4
+#define MCG_SC_FLTPRSRV_WIDTH                    1
+#define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_SC_FLTPRSRV_SHIFT))&MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK                         0x20u
+#define MCG_SC_ATMF_SHIFT                        5
+#define MCG_SC_ATMF_WIDTH                        1
+#define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMF_SHIFT))&MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK                         0x40u
+#define MCG_SC_ATMS_SHIFT                        6
+#define MCG_SC_ATMS_WIDTH                        1
+#define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMS_SHIFT))&MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK                         0x80u
+#define MCG_SC_ATME_SHIFT                        7
+#define MCG_SC_ATME_WIDTH                        1
+#define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATME_SHIFT))&MCG_SC_ATME_MASK)
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK                     0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT                    0
+#define MCG_ATCVH_ATCVH_WIDTH                    8
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK                     0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT                    0
+#define MCG_ATCVL_ATCVL_WIDTH                    8
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK                       0x3u
+#define MCG_C7_OSCSEL_SHIFT                      0
+#define MCG_C7_OSCSEL_WIDTH                      2
+#define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK                        0x1u
+#define MCG_C8_LOCS1_SHIFT                       0
+#define MCG_C8_LOCS1_WIDTH                       1
+#define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCS1_SHIFT))&MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK                         0x20u
+#define MCG_C8_CME1_SHIFT                        5
+#define MCG_C8_CME1_WIDTH                        1
+#define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C8_CME1_SHIFT))&MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK                        0x40u
+#define MCG_C8_LOLRE_SHIFT                       6
+#define MCG_C8_LOLRE_WIDTH                       1
+#define MCG_C8_LOLRE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOLRE_SHIFT))&MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK                       0x80u
+#define MCG_C8_LOCRE1_SHIFT                      7
+#define MCG_C8_LOCRE1_WIDTH                      1
+#define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCRE1_SHIFT))&MCG_C8_LOCRE1_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR                             (MCG)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS                           { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS                            { MCG }
+
+/* ----------------------------------------------------------------------------
+   -- MCG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1                                   MCG_C1_REG(MCG)
+#define MCG_C2                                   MCG_C2_REG(MCG)
+#define MCG_C3                                   MCG_C3_REG(MCG)
+#define MCG_C4                                   MCG_C4_REG(MCG)
+#define MCG_C5                                   MCG_C5_REG(MCG)
+#define MCG_C6                                   MCG_C6_REG(MCG)
+#define MCG_S                                    MCG_S_REG(MCG)
+#define MCG_SC                                   MCG_SC_REG(MCG)
+#define MCG_ATCVH                                MCG_ATCVH_REG(MCG)
+#define MCG_ATCVL                                MCG_ATCVL_REG(MCG)
+#define MCG_C7                                   MCG_C7_REG(MCG)
+#define MCG_C8                                   MCG_C8_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t CR;                                /**< Control Register, offset: 0xC */
+  __IO uint32_t ISCR;                              /**< Interrupt Status Register, offset: 0x10 */
+  __IO uint32_t ETBCC;                             /**< ETB Counter Control register, offset: 0x14 */
+  __IO uint32_t ETBRL;                             /**< ETB Reload register, offset: 0x18 */
+  __I  uint32_t ETBCNT;                            /**< ETB Counter Value register, offset: 0x1C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PID;                               /**< Process ID register, offset: 0x30 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base)                      ((base)->PLASC)
+#define MCM_PLAMC_REG(base)                      ((base)->PLAMC)
+#define MCM_CR_REG(base)                         ((base)->CR)
+#define MCM_ISCR_REG(base)                       ((base)->ISCR)
+#define MCM_ETBCC_REG(base)                      ((base)->ETBCC)
+#define MCM_ETBRL_REG(base)                      ((base)->ETBRL)
+#define MCM_ETBCNT_REG(base)                     ((base)->ETBCNT)
+#define MCM_PID_REG(base)                        ((base)->PID)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK                       0xFFu
+#define MCM_PLASC_ASC_SHIFT                      0
+#define MCM_PLASC_ASC_WIDTH                      8
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK                       0xFFu
+#define MCM_PLAMC_AMC_SHIFT                      0
+#define MCM_PLAMC_AMC_WIDTH                      8
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* CR Bit Fields */
+#define MCM_CR_SRAMUAP_MASK                      0x3000000u
+#define MCM_CR_SRAMUAP_SHIFT                     24
+#define MCM_CR_SRAMUAP_WIDTH                     2
+#define MCM_CR_SRAMUAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP_MASK                      0x4000000u
+#define MCM_CR_SRAMUWP_SHIFT                     26
+#define MCM_CR_SRAMUWP_WIDTH                     1
+#define MCM_CR_SRAMUWP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUWP_SHIFT))&MCM_CR_SRAMUWP_MASK)
+#define MCM_CR_SRAMLAP_MASK                      0x30000000u
+#define MCM_CR_SRAMLAP_SHIFT                     28
+#define MCM_CR_SRAMLAP_WIDTH                     2
+#define MCM_CR_SRAMLAP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP_MASK                      0x40000000u
+#define MCM_CR_SRAMLWP_SHIFT                     30
+#define MCM_CR_SRAMLWP_WIDTH                     1
+#define MCM_CR_SRAMLWP(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLWP_SHIFT))&MCM_CR_SRAMLWP_MASK)
+/* ISCR Bit Fields */
+#define MCM_ISCR_IRQ_MASK                        0x2u
+#define MCM_ISCR_IRQ_SHIFT                       1
+#define MCM_ISCR_IRQ_WIDTH                       1
+#define MCM_ISCR_IRQ(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_IRQ_SHIFT))&MCM_ISCR_IRQ_MASK)
+#define MCM_ISCR_NMI_MASK                        0x4u
+#define MCM_ISCR_NMI_SHIFT                       2
+#define MCM_ISCR_NMI_WIDTH                       1
+#define MCM_ISCR_NMI(x)                          (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_NMI_SHIFT))&MCM_ISCR_NMI_MASK)
+#define MCM_ISCR_DHREQ_MASK                      0x8u
+#define MCM_ISCR_DHREQ_SHIFT                     3
+#define MCM_ISCR_DHREQ_WIDTH                     1
+#define MCM_ISCR_DHREQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_DHREQ_SHIFT))&MCM_ISCR_DHREQ_MASK)
+#define MCM_ISCR_FIOC_MASK                       0x100u
+#define MCM_ISCR_FIOC_SHIFT                      8
+#define MCM_ISCR_FIOC_WIDTH                      1
+#define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FDZC_MASK                       0x200u
+#define MCM_ISCR_FDZC_SHIFT                      9
+#define MCM_ISCR_FDZC_WIDTH                      1
+#define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FOFC_MASK                       0x400u
+#define MCM_ISCR_FOFC_SHIFT                      10
+#define MCM_ISCR_FOFC_WIDTH                      1
+#define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FUFC_MASK                       0x800u
+#define MCM_ISCR_FUFC_SHIFT                      11
+#define MCM_ISCR_FUFC_WIDTH                      1
+#define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FIXC_MASK                       0x1000u
+#define MCM_ISCR_FIXC_SHIFT                      12
+#define MCM_ISCR_FIXC_WIDTH                      1
+#define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIDC_MASK                       0x8000u
+#define MCM_ISCR_FIDC_SHIFT                      15
+#define MCM_ISCR_FIDC_WIDTH                      1
+#define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIOCE_MASK                      0x1000000u
+#define MCM_ISCR_FIOCE_SHIFT                     24
+#define MCM_ISCR_FIOCE_WIDTH                     1
+#define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FDZCE_MASK                      0x2000000u
+#define MCM_ISCR_FDZCE_SHIFT                     25
+#define MCM_ISCR_FDZCE_WIDTH                     1
+#define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FOFCE_MASK                      0x4000000u
+#define MCM_ISCR_FOFCE_SHIFT                     26
+#define MCM_ISCR_FOFCE_WIDTH                     1
+#define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FUFCE_MASK                      0x8000000u
+#define MCM_ISCR_FUFCE_SHIFT                     27
+#define MCM_ISCR_FUFCE_WIDTH                     1
+#define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FIXCE_MASK                      0x10000000u
+#define MCM_ISCR_FIXCE_SHIFT                     28
+#define MCM_ISCR_FIXCE_WIDTH                     1
+#define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIDCE_MASK                      0x80000000u
+#define MCM_ISCR_FIDCE_SHIFT                     31
+#define MCM_ISCR_FIDCE_WIDTH                     1
+#define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
+/* ETBCC Bit Fields */
+#define MCM_ETBCC_CNTEN_MASK                     0x1u
+#define MCM_ETBCC_CNTEN_SHIFT                    0
+#define MCM_ETBCC_CNTEN_WIDTH                    1
+#define MCM_ETBCC_CNTEN(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_CNTEN_SHIFT))&MCM_ETBCC_CNTEN_MASK)
+#define MCM_ETBCC_RSPT_MASK                      0x6u
+#define MCM_ETBCC_RSPT_SHIFT                     1
+#define MCM_ETBCC_RSPT_WIDTH                     2
+#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK                      0x8u
+#define MCM_ETBCC_RLRQ_SHIFT                     3
+#define MCM_ETBCC_RLRQ_WIDTH                     1
+#define MCM_ETBCC_RLRQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RLRQ_SHIFT))&MCM_ETBCC_RLRQ_MASK)
+#define MCM_ETBCC_ETDIS_MASK                     0x10u
+#define MCM_ETBCC_ETDIS_SHIFT                    4
+#define MCM_ETBCC_ETDIS_WIDTH                    1
+#define MCM_ETBCC_ETDIS(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ETDIS_SHIFT))&MCM_ETBCC_ETDIS_MASK)
+#define MCM_ETBCC_ITDIS_MASK                     0x20u
+#define MCM_ETBCC_ITDIS_SHIFT                    5
+#define MCM_ETBCC_ITDIS_WIDTH                    1
+#define MCM_ETBCC_ITDIS(x)                       (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ITDIS_SHIFT))&MCM_ETBCC_ITDIS_MASK)
+/* ETBRL Bit Fields */
+#define MCM_ETBRL_RELOAD_MASK                    0x7FFu
+#define MCM_ETBRL_RELOAD_SHIFT                   0
+#define MCM_ETBRL_RELOAD_WIDTH                   11
+#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
+/* ETBCNT Bit Fields */
+#define MCM_ETBCNT_COUNTER_MASK                  0x7FFu
+#define MCM_ETBCNT_COUNTER_SHIFT                 0
+#define MCM_ETBCNT_COUNTER_WIDTH                 11
+#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
+/* PID Bit Fields */
+#define MCM_PID_PID_MASK                         0xFFu
+#define MCM_PID_PID_SHIFT                        0
+#define MCM_PID_PID_WIDTH                        8
+#define MCM_PID_PID(x)                           (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR                             (MCM)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { MCM }
+/** Interrupt vectors for the MCM peripheral type */
+#define MCM_IRQS                                 { MCM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- MCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC                                MCM_PLASC_REG(MCM)
+#define MCM_PLAMC                                MCM_PLAMC_REG(MCM)
+#define MCM_CR                                   MCM_CR_REG(MCM)
+#define MCM_ISCR                                 MCM_ISCR_REG(MCM)
+#define MCM_ETBCC                                MCM_ETBCC_REG(MCM)
+#define MCM_ETBRL                                MCM_ETBRL_REG(MCM)
+#define MCM_ETBCNT                               MCM_ETBCNT_REG(MCM)
+#define MCM_PID                                  MCM_PID_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
+ * @{
+ */
+
+/** MPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} MPU_Type, *MPU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register accessors */
+#define MPU_CESR_REG(base)                       ((base)->CESR)
+#define MPU_EAR_REG(base,index)                  ((base)->SP[index].EAR)
+#define MPU_EAR_COUNT                            5
+#define MPU_EDR_REG(base,index)                  ((base)->SP[index].EDR)
+#define MPU_EDR_COUNT                            5
+#define MPU_WORD_REG(base,index,index2)          ((base)->WORD[index][index2])
+#define MPU_WORD_COUNT                           12
+#define MPU_WORD_COUNT2                          4
+#define MPU_RGDAAC_REG(base,index)               ((base)->RGDAAC[index])
+#define MPU_RGDAAC_COUNT                         12
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Masks MPU Register Masks
+ * @{
+ */
+
+/* CESR Bit Fields */
+#define MPU_CESR_VLD_MASK                        0x1u
+#define MPU_CESR_VLD_SHIFT                       0
+#define MPU_CESR_VLD_WIDTH                       1
+#define MPU_CESR_VLD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_VLD_SHIFT))&MPU_CESR_VLD_MASK)
+#define MPU_CESR_NRGD_MASK                       0xF00u
+#define MPU_CESR_NRGD_SHIFT                      8
+#define MPU_CESR_NRGD_WIDTH                      4
+#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
+#define MPU_CESR_NSP_MASK                        0xF000u
+#define MPU_CESR_NSP_SHIFT                       12
+#define MPU_CESR_NSP_WIDTH                       4
+#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
+#define MPU_CESR_HRL_MASK                        0xF0000u
+#define MPU_CESR_HRL_SHIFT                       16
+#define MPU_CESR_HRL_WIDTH                       4
+#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
+#define MPU_CESR_SPERR_MASK                      0xF8000000u
+#define MPU_CESR_SPERR_SHIFT                     27
+#define MPU_CESR_SPERR_WIDTH                     5
+#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
+/* EAR Bit Fields */
+#define MPU_EAR_EADDR_MASK                       0xFFFFFFFFu
+#define MPU_EAR_EADDR_SHIFT                      0
+#define MPU_EAR_EADDR_WIDTH                      32
+#define MPU_EAR_EADDR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
+/* EDR Bit Fields */
+#define MPU_EDR_ERW_MASK                         0x1u
+#define MPU_EDR_ERW_SHIFT                        0
+#define MPU_EDR_ERW_WIDTH                        1
+#define MPU_EDR_ERW(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_ERW_SHIFT))&MPU_EDR_ERW_MASK)
+#define MPU_EDR_EATTR_MASK                       0xEu
+#define MPU_EDR_EATTR_SHIFT                      1
+#define MPU_EDR_EATTR_WIDTH                      3
+#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
+#define MPU_EDR_EMN_MASK                         0xF0u
+#define MPU_EDR_EMN_SHIFT                        4
+#define MPU_EDR_EMN_WIDTH                        4
+#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
+#define MPU_EDR_EPID_MASK                        0xFF00u
+#define MPU_EDR_EPID_SHIFT                       8
+#define MPU_EDR_EPID_WIDTH                       8
+#define MPU_EDR_EPID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
+#define MPU_EDR_EACD_MASK                        0xFFFF0000u
+#define MPU_EDR_EACD_SHIFT                       16
+#define MPU_EDR_EACD_WIDTH                       16
+#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
+/* WORD Bit Fields */
+#define MPU_WORD_VLD_MASK                        0x1u
+#define MPU_WORD_VLD_SHIFT                       0
+#define MPU_WORD_VLD_WIDTH                       1
+#define MPU_WORD_VLD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_VLD_SHIFT))&MPU_WORD_VLD_MASK)
+#define MPU_WORD_M0UM_MASK                       0x7u
+#define MPU_WORD_M0UM_SHIFT                      0
+#define MPU_WORD_M0UM_WIDTH                      3
+#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
+#define MPU_WORD_M0SM_MASK                       0x18u
+#define MPU_WORD_M0SM_SHIFT                      3
+#define MPU_WORD_M0SM_WIDTH                      2
+#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
+#define MPU_WORD_M0PE_MASK                       0x20u
+#define MPU_WORD_M0PE_SHIFT                      5
+#define MPU_WORD_M0PE_WIDTH                      1
+#define MPU_WORD_M0PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0PE_SHIFT))&MPU_WORD_M0PE_MASK)
+#define MPU_WORD_ENDADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_ENDADDR_SHIFT                   5
+#define MPU_WORD_ENDADDR_WIDTH                   27
+#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
+#define MPU_WORD_SRTADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_SRTADDR_SHIFT                   5
+#define MPU_WORD_SRTADDR_WIDTH                   27
+#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
+#define MPU_WORD_M1UM_MASK                       0x1C0u
+#define MPU_WORD_M1UM_SHIFT                      6
+#define MPU_WORD_M1UM_WIDTH                      3
+#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
+#define MPU_WORD_M1SM_MASK                       0x600u
+#define MPU_WORD_M1SM_SHIFT                      9
+#define MPU_WORD_M1SM_WIDTH                      2
+#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
+#define MPU_WORD_M1PE_MASK                       0x800u
+#define MPU_WORD_M1PE_SHIFT                      11
+#define MPU_WORD_M1PE_WIDTH                      1
+#define MPU_WORD_M1PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1PE_SHIFT))&MPU_WORD_M1PE_MASK)
+#define MPU_WORD_M2UM_MASK                       0x7000u
+#define MPU_WORD_M2UM_SHIFT                      12
+#define MPU_WORD_M2UM_WIDTH                      3
+#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
+#define MPU_WORD_M2SM_MASK                       0x18000u
+#define MPU_WORD_M2SM_SHIFT                      15
+#define MPU_WORD_M2SM_WIDTH                      2
+#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
+#define MPU_WORD_PIDMASK_MASK                    0xFF0000u
+#define MPU_WORD_PIDMASK_SHIFT                   16
+#define MPU_WORD_PIDMASK_WIDTH                   8
+#define MPU_WORD_PIDMASK(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
+#define MPU_WORD_M2PE_MASK                       0x20000u
+#define MPU_WORD_M2PE_SHIFT                      17
+#define MPU_WORD_M2PE_WIDTH                      1
+#define MPU_WORD_M2PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2PE_SHIFT))&MPU_WORD_M2PE_MASK)
+#define MPU_WORD_M3UM_MASK                       0x1C0000u
+#define MPU_WORD_M3UM_SHIFT                      18
+#define MPU_WORD_M3UM_WIDTH                      3
+#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
+#define MPU_WORD_M3SM_MASK                       0x600000u
+#define MPU_WORD_M3SM_SHIFT                      21
+#define MPU_WORD_M3SM_WIDTH                      2
+#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
+#define MPU_WORD_M3PE_MASK                       0x800000u
+#define MPU_WORD_M3PE_SHIFT                      23
+#define MPU_WORD_M3PE_WIDTH                      1
+#define MPU_WORD_M3PE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3PE_SHIFT))&MPU_WORD_M3PE_MASK)
+#define MPU_WORD_PID_MASK                        0xFF000000u
+#define MPU_WORD_PID_SHIFT                       24
+#define MPU_WORD_PID_WIDTH                       8
+#define MPU_WORD_PID(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
+#define MPU_WORD_M4WE_MASK                       0x1000000u
+#define MPU_WORD_M4WE_SHIFT                      24
+#define MPU_WORD_M4WE_WIDTH                      1
+#define MPU_WORD_M4WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4WE_SHIFT))&MPU_WORD_M4WE_MASK)
+#define MPU_WORD_M4RE_MASK                       0x2000000u
+#define MPU_WORD_M4RE_SHIFT                      25
+#define MPU_WORD_M4RE_WIDTH                      1
+#define MPU_WORD_M4RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4RE_SHIFT))&MPU_WORD_M4RE_MASK)
+#define MPU_WORD_M5WE_MASK                       0x4000000u
+#define MPU_WORD_M5WE_SHIFT                      26
+#define MPU_WORD_M5WE_WIDTH                      1
+#define MPU_WORD_M5WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5WE_SHIFT))&MPU_WORD_M5WE_MASK)
+#define MPU_WORD_M5RE_MASK                       0x8000000u
+#define MPU_WORD_M5RE_SHIFT                      27
+#define MPU_WORD_M5RE_WIDTH                      1
+#define MPU_WORD_M5RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5RE_SHIFT))&MPU_WORD_M5RE_MASK)
+#define MPU_WORD_M6WE_MASK                       0x10000000u
+#define MPU_WORD_M6WE_SHIFT                      28
+#define MPU_WORD_M6WE_WIDTH                      1
+#define MPU_WORD_M6WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6WE_SHIFT))&MPU_WORD_M6WE_MASK)
+#define MPU_WORD_M6RE_MASK                       0x20000000u
+#define MPU_WORD_M6RE_SHIFT                      29
+#define MPU_WORD_M6RE_WIDTH                      1
+#define MPU_WORD_M6RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6RE_SHIFT))&MPU_WORD_M6RE_MASK)
+#define MPU_WORD_M7WE_MASK                       0x40000000u
+#define MPU_WORD_M7WE_SHIFT                      30
+#define MPU_WORD_M7WE_WIDTH                      1
+#define MPU_WORD_M7WE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7WE_SHIFT))&MPU_WORD_M7WE_MASK)
+#define MPU_WORD_M7RE_MASK                       0x80000000u
+#define MPU_WORD_M7RE_SHIFT                      31
+#define MPU_WORD_M7RE_WIDTH                      1
+#define MPU_WORD_M7RE(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7RE_SHIFT))&MPU_WORD_M7RE_MASK)
+/* RGDAAC Bit Fields */
+#define MPU_RGDAAC_M0UM_MASK                     0x7u
+#define MPU_RGDAAC_M0UM_SHIFT                    0
+#define MPU_RGDAAC_M0UM_WIDTH                    3
+#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
+#define MPU_RGDAAC_M0SM_MASK                     0x18u
+#define MPU_RGDAAC_M0SM_SHIFT                    3
+#define MPU_RGDAAC_M0SM_WIDTH                    2
+#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
+#define MPU_RGDAAC_M0PE_MASK                     0x20u
+#define MPU_RGDAAC_M0PE_SHIFT                    5
+#define MPU_RGDAAC_M0PE_WIDTH                    1
+#define MPU_RGDAAC_M0PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0PE_SHIFT))&MPU_RGDAAC_M0PE_MASK)
+#define MPU_RGDAAC_M1UM_MASK                     0x1C0u
+#define MPU_RGDAAC_M1UM_SHIFT                    6
+#define MPU_RGDAAC_M1UM_WIDTH                    3
+#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
+#define MPU_RGDAAC_M1SM_MASK                     0x600u
+#define MPU_RGDAAC_M1SM_SHIFT                    9
+#define MPU_RGDAAC_M1SM_WIDTH                    2
+#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
+#define MPU_RGDAAC_M1PE_MASK                     0x800u
+#define MPU_RGDAAC_M1PE_SHIFT                    11
+#define MPU_RGDAAC_M1PE_WIDTH                    1
+#define MPU_RGDAAC_M1PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1PE_SHIFT))&MPU_RGDAAC_M1PE_MASK)
+#define MPU_RGDAAC_M2UM_MASK                     0x7000u
+#define MPU_RGDAAC_M2UM_SHIFT                    12
+#define MPU_RGDAAC_M2UM_WIDTH                    3
+#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
+#define MPU_RGDAAC_M2SM_MASK                     0x18000u
+#define MPU_RGDAAC_M2SM_SHIFT                    15
+#define MPU_RGDAAC_M2SM_WIDTH                    2
+#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
+#define MPU_RGDAAC_M2PE_MASK                     0x20000u
+#define MPU_RGDAAC_M2PE_SHIFT                    17
+#define MPU_RGDAAC_M2PE_WIDTH                    1
+#define MPU_RGDAAC_M2PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2PE_SHIFT))&MPU_RGDAAC_M2PE_MASK)
+#define MPU_RGDAAC_M3UM_MASK                     0x1C0000u
+#define MPU_RGDAAC_M3UM_SHIFT                    18
+#define MPU_RGDAAC_M3UM_WIDTH                    3
+#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
+#define MPU_RGDAAC_M3SM_MASK                     0x600000u
+#define MPU_RGDAAC_M3SM_SHIFT                    21
+#define MPU_RGDAAC_M3SM_WIDTH                    2
+#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
+#define MPU_RGDAAC_M3PE_MASK                     0x800000u
+#define MPU_RGDAAC_M3PE_SHIFT                    23
+#define MPU_RGDAAC_M3PE_WIDTH                    1
+#define MPU_RGDAAC_M3PE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3PE_SHIFT))&MPU_RGDAAC_M3PE_MASK)
+#define MPU_RGDAAC_M4WE_MASK                     0x1000000u
+#define MPU_RGDAAC_M4WE_SHIFT                    24
+#define MPU_RGDAAC_M4WE_WIDTH                    1
+#define MPU_RGDAAC_M4WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4WE_SHIFT))&MPU_RGDAAC_M4WE_MASK)
+#define MPU_RGDAAC_M4RE_MASK                     0x2000000u
+#define MPU_RGDAAC_M4RE_SHIFT                    25
+#define MPU_RGDAAC_M4RE_WIDTH                    1
+#define MPU_RGDAAC_M4RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4RE_SHIFT))&MPU_RGDAAC_M4RE_MASK)
+#define MPU_RGDAAC_M5WE_MASK                     0x4000000u
+#define MPU_RGDAAC_M5WE_SHIFT                    26
+#define MPU_RGDAAC_M5WE_WIDTH                    1
+#define MPU_RGDAAC_M5WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5WE_SHIFT))&MPU_RGDAAC_M5WE_MASK)
+#define MPU_RGDAAC_M5RE_MASK                     0x8000000u
+#define MPU_RGDAAC_M5RE_SHIFT                    27
+#define MPU_RGDAAC_M5RE_WIDTH                    1
+#define MPU_RGDAAC_M5RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5RE_SHIFT))&MPU_RGDAAC_M5RE_MASK)
+#define MPU_RGDAAC_M6WE_MASK                     0x10000000u
+#define MPU_RGDAAC_M6WE_SHIFT                    28
+#define MPU_RGDAAC_M6WE_WIDTH                    1
+#define MPU_RGDAAC_M6WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6WE_SHIFT))&MPU_RGDAAC_M6WE_MASK)
+#define MPU_RGDAAC_M6RE_MASK                     0x20000000u
+#define MPU_RGDAAC_M6RE_SHIFT                    29
+#define MPU_RGDAAC_M6RE_WIDTH                    1
+#define MPU_RGDAAC_M6RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6RE_SHIFT))&MPU_RGDAAC_M6RE_MASK)
+#define MPU_RGDAAC_M7WE_MASK                     0x40000000u
+#define MPU_RGDAAC_M7WE_SHIFT                    30
+#define MPU_RGDAAC_M7WE_WIDTH                    1
+#define MPU_RGDAAC_M7WE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7WE_SHIFT))&MPU_RGDAAC_M7WE_MASK)
+#define MPU_RGDAAC_M7RE_MASK                     0x80000000u
+#define MPU_RGDAAC_M7RE_SHIFT                    31
+#define MPU_RGDAAC_M7RE_WIDTH                    1
+#define MPU_RGDAAC_M7RE(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7RE_SHIFT))&MPU_RGDAAC_M7RE_MASK)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Masks */
+
+
+/* MPU - Peripheral instance base addresses */
+/** Peripheral MPU base address */
+#define MPU_BASE                                 (0x4000D000u)
+/** Peripheral MPU base pointer */
+#define MPU                                      ((MPU_Type *)MPU_BASE)
+#define MPU_BASE_PTR                             (MPU)
+/** Array initializer of MPU peripheral base addresses */
+#define MPU_BASE_ADDRS                           { MPU_BASE }
+/** Array initializer of MPU peripheral base pointers */
+#define MPU_BASE_PTRS                            { MPU }
+
+/* ----------------------------------------------------------------------------
+   -- MPU - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
+ * @{
+ */
+
+
+/* MPU - Register instance definitions */
+/* MPU */
+#define MPU_CESR                                 MPU_CESR_REG(MPU)
+#define MPU_EAR0                                 MPU_EAR_REG(MPU,0)
+#define MPU_EDR0                                 MPU_EDR_REG(MPU,0)
+#define MPU_EAR1                                 MPU_EAR_REG(MPU,1)
+#define MPU_EDR1                                 MPU_EDR_REG(MPU,1)
+#define MPU_EAR2                                 MPU_EAR_REG(MPU,2)
+#define MPU_EDR2                                 MPU_EDR_REG(MPU,2)
+#define MPU_EAR3                                 MPU_EAR_REG(MPU,3)
+#define MPU_EDR3                                 MPU_EDR_REG(MPU,3)
+#define MPU_EAR4                                 MPU_EAR_REG(MPU,4)
+#define MPU_EDR4                                 MPU_EDR_REG(MPU,4)
+#define MPU_RGD0_WORD0                           MPU_WORD_REG(MPU,0,0)
+#define MPU_RGD0_WORD1                           MPU_WORD_REG(MPU,0,1)
+#define MPU_RGD0_WORD2                           MPU_WORD_REG(MPU,0,2)
+#define MPU_RGD0_WORD3                           MPU_WORD_REG(MPU,0,3)
+#define MPU_RGD1_WORD0                           MPU_WORD_REG(MPU,1,0)
+#define MPU_RGD1_WORD1                           MPU_WORD_REG(MPU,1,1)
+#define MPU_RGD1_WORD2                           MPU_WORD_REG(MPU,1,2)
+#define MPU_RGD1_WORD3                           MPU_WORD_REG(MPU,1,3)
+#define MPU_RGD2_WORD0                           MPU_WORD_REG(MPU,2,0)
+#define MPU_RGD2_WORD1                           MPU_WORD_REG(MPU,2,1)
+#define MPU_RGD2_WORD2                           MPU_WORD_REG(MPU,2,2)
+#define MPU_RGD2_WORD3                           MPU_WORD_REG(MPU,2,3)
+#define MPU_RGD3_WORD0                           MPU_WORD_REG(MPU,3,0)
+#define MPU_RGD3_WORD1                           MPU_WORD_REG(MPU,3,1)
+#define MPU_RGD3_WORD2                           MPU_WORD_REG(MPU,3,2)
+#define MPU_RGD3_WORD3                           MPU_WORD_REG(MPU,3,3)
+#define MPU_RGD4_WORD0                           MPU_WORD_REG(MPU,4,0)
+#define MPU_RGD4_WORD1                           MPU_WORD_REG(MPU,4,1)
+#define MPU_RGD4_WORD2                           MPU_WORD_REG(MPU,4,2)
+#define MPU_RGD4_WORD3                           MPU_WORD_REG(MPU,4,3)
+#define MPU_RGD5_WORD0                           MPU_WORD_REG(MPU,5,0)
+#define MPU_RGD5_WORD1                           MPU_WORD_REG(MPU,5,1)
+#define MPU_RGD5_WORD2                           MPU_WORD_REG(MPU,5,2)
+#define MPU_RGD5_WORD3                           MPU_WORD_REG(MPU,5,3)
+#define MPU_RGD6_WORD0                           MPU_WORD_REG(MPU,6,0)
+#define MPU_RGD6_WORD1                           MPU_WORD_REG(MPU,6,1)
+#define MPU_RGD6_WORD2                           MPU_WORD_REG(MPU,6,2)
+#define MPU_RGD6_WORD3                           MPU_WORD_REG(MPU,6,3)
+#define MPU_RGD7_WORD0                           MPU_WORD_REG(MPU,7,0)
+#define MPU_RGD7_WORD1                           MPU_WORD_REG(MPU,7,1)
+#define MPU_RGD7_WORD2                           MPU_WORD_REG(MPU,7,2)
+#define MPU_RGD7_WORD3                           MPU_WORD_REG(MPU,7,3)
+#define MPU_RGD8_WORD0                           MPU_WORD_REG(MPU,8,0)
+#define MPU_RGD8_WORD1                           MPU_WORD_REG(MPU,8,1)
+#define MPU_RGD8_WORD2                           MPU_WORD_REG(MPU,8,2)
+#define MPU_RGD8_WORD3                           MPU_WORD_REG(MPU,8,3)
+#define MPU_RGD9_WORD0                           MPU_WORD_REG(MPU,9,0)
+#define MPU_RGD9_WORD1                           MPU_WORD_REG(MPU,9,1)
+#define MPU_RGD9_WORD2                           MPU_WORD_REG(MPU,9,2)
+#define MPU_RGD9_WORD3                           MPU_WORD_REG(MPU,9,3)
+#define MPU_RGD10_WORD0                          MPU_WORD_REG(MPU,10,0)
+#define MPU_RGD10_WORD1                          MPU_WORD_REG(MPU,10,1)
+#define MPU_RGD10_WORD2                          MPU_WORD_REG(MPU,10,2)
+#define MPU_RGD10_WORD3                          MPU_WORD_REG(MPU,10,3)
+#define MPU_RGD11_WORD0                          MPU_WORD_REG(MPU,11,0)
+#define MPU_RGD11_WORD1                          MPU_WORD_REG(MPU,11,1)
+#define MPU_RGD11_WORD2                          MPU_WORD_REG(MPU,11,2)
+#define MPU_RGD11_WORD3                          MPU_WORD_REG(MPU,11,3)
+#define MPU_RGDAAC0                              MPU_RGDAAC_REG(MPU,0)
+#define MPU_RGDAAC1                              MPU_RGDAAC_REG(MPU,1)
+#define MPU_RGDAAC2                              MPU_RGDAAC_REG(MPU,2)
+#define MPU_RGDAAC3                              MPU_RGDAAC_REG(MPU,3)
+#define MPU_RGDAAC4                              MPU_RGDAAC_REG(MPU,4)
+#define MPU_RGDAAC5                              MPU_RGDAAC_REG(MPU,5)
+#define MPU_RGDAAC6                              MPU_RGDAAC_REG(MPU,6)
+#define MPU_RGDAAC7                              MPU_RGDAAC_REG(MPU,7)
+#define MPU_RGDAAC8                              MPU_RGDAAC_REG(MPU,8)
+#define MPU_RGDAAC9                              MPU_RGDAAC_REG(MPU,9)
+#define MPU_RGDAAC10                             MPU_RGDAAC_REG(MPU,10)
+#define MPU_RGDAAC11                             MPU_RGDAAC_REG(MPU,11)
+
+/* MPU - Register array accessors */
+#define MPU_EAR(index)                           MPU_EAR_REG(MPU,index)
+#define MPU_EDR(index)                           MPU_EDR_REG(MPU,index)
+#define MPU_WORD(index,index2)                   MPU_WORD_REG(MPU,index,index2)
+#define MPU_RGDAAC(index)                        MPU_RGDAAC_REG(MPU,index)
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+  __I  uint8_t FEPROT;                             /**< Non-volatile EERAM Protection Register, offset: 0xE */
+  __I  uint8_t FDPROT;                             /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base)                    ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base)                    ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base)                    ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base)                    ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base)                    ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base)                    ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base)                    ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base)                    ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base)                      ((base)->FPROT3)
+#define NV_FPROT2_REG(base)                      ((base)->FPROT2)
+#define NV_FPROT1_REG(base)                      ((base)->FPROT1)
+#define NV_FPROT0_REG(base)                      ((base)->FPROT0)
+#define NV_FSEC_REG(base)                        ((base)->FSEC)
+#define NV_FOPT_REG(base)                        ((base)->FOPT)
+#define NV_FEPROT_REG(base)                      ((base)->FEPROT)
+#define NV_FDPROT_REG(base)                      ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK                     0xFFu
+#define NV_BACKKEY3_KEY_SHIFT                    0
+#define NV_BACKKEY3_KEY_WIDTH                    8
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK                     0xFFu
+#define NV_BACKKEY2_KEY_SHIFT                    0
+#define NV_BACKKEY2_KEY_WIDTH                    8
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK                     0xFFu
+#define NV_BACKKEY1_KEY_SHIFT                    0
+#define NV_BACKKEY1_KEY_WIDTH                    8
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK                     0xFFu
+#define NV_BACKKEY0_KEY_SHIFT                    0
+#define NV_BACKKEY0_KEY_WIDTH                    8
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK                     0xFFu
+#define NV_BACKKEY7_KEY_SHIFT                    0
+#define NV_BACKKEY7_KEY_WIDTH                    8
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK                     0xFFu
+#define NV_BACKKEY6_KEY_SHIFT                    0
+#define NV_BACKKEY6_KEY_WIDTH                    8
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK                     0xFFu
+#define NV_BACKKEY5_KEY_SHIFT                    0
+#define NV_BACKKEY5_KEY_WIDTH                    8
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK                     0xFFu
+#define NV_BACKKEY4_KEY_SHIFT                    0
+#define NV_BACKKEY4_KEY_WIDTH                    8
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK                      0xFFu
+#define NV_FPROT3_PROT_SHIFT                     0
+#define NV_FPROT3_PROT_WIDTH                     8
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK                      0xFFu
+#define NV_FPROT2_PROT_SHIFT                     0
+#define NV_FPROT2_PROT_WIDTH                     8
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK                      0xFFu
+#define NV_FPROT1_PROT_SHIFT                     0
+#define NV_FPROT1_PROT_WIDTH                     8
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK                      0xFFu
+#define NV_FPROT0_PROT_SHIFT                     0
+#define NV_FPROT0_PROT_WIDTH                     8
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK                         0x3u
+#define NV_FSEC_SEC_SHIFT                        0
+#define NV_FSEC_SEC_WIDTH                        2
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      0xCu
+#define NV_FSEC_FSLACC_SHIFT                     2
+#define NV_FSEC_FSLACC_WIDTH                     2
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        0x30u
+#define NV_FSEC_MEEN_SHIFT                       4
+#define NV_FSEC_MEEN_WIDTH                       2
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       0xC0u
+#define NV_FSEC_KEYEN_SHIFT                      6
+#define NV_FSEC_KEYEN_WIDTH                      2
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK                      0x1u
+#define NV_FOPT_LPBOOT_SHIFT                     0
+#define NV_FOPT_LPBOOT_WIDTH                     1
+#define NV_FOPT_LPBOOT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT_SHIFT))&NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK                  0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT                 1
+#define NV_FOPT_EZPORT_DIS_WIDTH                 1
+#define NV_FOPT_EZPORT_DIS(x)                    (((uint8_t)(((uint8_t)(x))<<NV_FOPT_EZPORT_DIS_SHIFT))&NV_FOPT_EZPORT_DIS_MASK)
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK                     0xFFu
+#define NV_FEPROT_EPROT_SHIFT                    0
+#define NV_FEPROT_EPROT_WIDTH                    8
+#define NV_FEPROT_EPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK                     0xFFu
+#define NV_FDPROT_DPROT_SHIFT                    0
+#define NV_FDPROT_DPROT_WIDTH                    8
+#define NV_FDPROT_DPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFE_FlashConfig base address */
+#define FTFE_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFE_FlashConfig base pointer */
+#define FTFE_FlashConfig                         ((NV_Type *)FTFE_FlashConfig_BASE)
+#define FTFE_FlashConfig_BASE_PTR                (FTFE_FlashConfig)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS                            { FTFE_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS                             { FTFE_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+   -- NV - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFE_FlashConfig */
+#define NV_BACKKEY3                              NV_BACKKEY3_REG(FTFE_FlashConfig)
+#define NV_BACKKEY2                              NV_BACKKEY2_REG(FTFE_FlashConfig)
+#define NV_BACKKEY1                              NV_BACKKEY1_REG(FTFE_FlashConfig)
+#define NV_BACKKEY0                              NV_BACKKEY0_REG(FTFE_FlashConfig)
+#define NV_BACKKEY7                              NV_BACKKEY7_REG(FTFE_FlashConfig)
+#define NV_BACKKEY6                              NV_BACKKEY6_REG(FTFE_FlashConfig)
+#define NV_BACKKEY5                              NV_BACKKEY5_REG(FTFE_FlashConfig)
+#define NV_BACKKEY4                              NV_BACKKEY4_REG(FTFE_FlashConfig)
+#define NV_FPROT3                                NV_FPROT3_REG(FTFE_FlashConfig)
+#define NV_FPROT2                                NV_FPROT2_REG(FTFE_FlashConfig)
+#define NV_FPROT1                                NV_FPROT1_REG(FTFE_FlashConfig)
+#define NV_FPROT0                                NV_FPROT0_REG(FTFE_FlashConfig)
+#define NV_FSEC                                  NV_FSEC_REG(FTFE_FlashConfig)
+#define NV_FOPT                                  NV_FOPT_REG(FTFE_FlashConfig)
+#define NV_FEPROT                                NV_FEPROT_REG(FTFE_FlashConfig)
+#define NV_FDPROT                                NV_FDPROT_REG(FTFE_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base)                         ((base)->CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK                        0x1u
+#define OSC_CR_SC16P_SHIFT                       0
+#define OSC_CR_SC16P_WIDTH                       1
+#define OSC_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK                         0x2u
+#define OSC_CR_SC8P_SHIFT                        1
+#define OSC_CR_SC8P_WIDTH                        1
+#define OSC_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK                         0x4u
+#define OSC_CR_SC4P_SHIFT                        2
+#define OSC_CR_SC4P_WIDTH                        1
+#define OSC_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK                         0x8u
+#define OSC_CR_SC2P_SHIFT                        3
+#define OSC_CR_SC2P_WIDTH                        1
+#define OSC_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK                     0x20u
+#define OSC_CR_EREFSTEN_SHIFT                    5
+#define OSC_CR_EREFSTEN_WIDTH                    1
+#define OSC_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK                      0x80u
+#define OSC_CR_ERCLKEN_SHIFT                     7
+#define OSC_CR_ERCLKEN_WIDTH                     1
+#define OSC_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE                                 (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC                                      ((OSC_Type *)OSC_BASE)
+#define OSC_BASE_PTR                             (OSC)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS                           { OSC_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS                            { OSC }
+
+/* ----------------------------------------------------------------------------
+   -- OSC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC */
+#define OSC_CR                                   OSC_CR_REG(OSC)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control register, offset: 0x0 */
+  __IO uint32_t MOD;                               /**< Modulus register, offset: 0x4 */
+  __I  uint32_t CNT;                               /**< Counter register, offset: 0x8 */
+  __IO uint32_t IDLY;                              /**< Interrupt Delay register, offset: 0xC */
+  struct {                                         /* offset: 0x10, array step: 0x28 */
+    __IO uint32_t C1;                                /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+    __IO uint32_t S;                                 /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+    __IO uint32_t DLY[2];                            /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+         uint8_t RESERVED_0[24];
+  } CH[2];
+       uint8_t RESERVED_0[240];
+  struct {                                         /* offset: 0x150, array step: 0x8 */
+    __IO uint32_t INTC;                              /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+    __IO uint32_t INT;                               /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+  } DAC[2];
+       uint8_t RESERVED_1[48];
+  __IO uint32_t POEN;                              /**< Pulse-Out n Enable register, offset: 0x190 */
+  __IO uint32_t PODLY[3];                          /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type, *PDB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register accessors */
+#define PDB_SC_REG(base)                         ((base)->SC)
+#define PDB_MOD_REG(base)                        ((base)->MOD)
+#define PDB_CNT_REG(base)                        ((base)->CNT)
+#define PDB_IDLY_REG(base)                       ((base)->IDLY)
+#define PDB_C1_REG(base,index)                   ((base)->CH[index].C1)
+#define PDB_C1_COUNT                             2
+#define PDB_S_REG(base,index)                    ((base)->CH[index].S)
+#define PDB_S_COUNT                              2
+#define PDB_DLY_REG(base,index,index2)           ((base)->CH[index].DLY[index2])
+#define PDB_DLY_COUNT                            2
+#define PDB_DLY_COUNT2                           2
+#define PDB_INTC_REG(base,index)                 ((base)->DAC[index].INTC)
+#define PDB_INTC_COUNT                           2
+#define PDB_INT_REG(base,index)                  ((base)->DAC[index].INT)
+#define PDB_INT_COUNT                            2
+#define PDB_POEN_REG(base)                       ((base)->POEN)
+#define PDB_PODLY_REG(base,index)                ((base)->PODLY[index])
+#define PDB_PODLY_COUNT                          3
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK                         0x1u
+#define PDB_SC_LDOK_SHIFT                        0
+#define PDB_SC_LDOK_WIDTH                        1
+#define PDB_SC_LDOK(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK                         0x2u
+#define PDB_SC_CONT_SHIFT                        1
+#define PDB_SC_CONT_WIDTH                        1
+#define PDB_SC_CONT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK                         0xCu
+#define PDB_SC_MULT_SHIFT                        2
+#define PDB_SC_MULT_WIDTH                        2
+#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK                        0x20u
+#define PDB_SC_PDBIE_SHIFT                       5
+#define PDB_SC_PDBIE_WIDTH                       1
+#define PDB_SC_PDBIE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK                        0x40u
+#define PDB_SC_PDBIF_SHIFT                       6
+#define PDB_SC_PDBIF_WIDTH                       1
+#define PDB_SC_PDBIF(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK                        0x80u
+#define PDB_SC_PDBEN_SHIFT                       7
+#define PDB_SC_PDBEN_WIDTH                       1
+#define PDB_SC_PDBEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK                       0xF00u
+#define PDB_SC_TRGSEL_SHIFT                      8
+#define PDB_SC_TRGSEL_WIDTH                      4
+#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK                    0x7000u
+#define PDB_SC_PRESCALER_SHIFT                   12
+#define PDB_SC_PRESCALER_WIDTH                   3
+#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK                        0x8000u
+#define PDB_SC_DMAEN_SHIFT                       15
+#define PDB_SC_DMAEN_WIDTH                       1
+#define PDB_SC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK                       0x10000u
+#define PDB_SC_SWTRIG_SHIFT                      16
+#define PDB_SC_SWTRIG_WIDTH                      1
+#define PDB_SC_SWTRIG(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK                       0x20000u
+#define PDB_SC_PDBEIE_SHIFT                      17
+#define PDB_SC_PDBEIE_WIDTH                      1
+#define PDB_SC_PDBEIE(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK                        0xC0000u
+#define PDB_SC_LDMOD_SHIFT                       18
+#define PDB_SC_LDMOD_WIDTH                       2
+#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK                         0xFFFFu
+#define PDB_MOD_MOD_SHIFT                        0
+#define PDB_MOD_MOD_WIDTH                        16
+#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK                         0xFFFFu
+#define PDB_CNT_CNT_SHIFT                        0
+#define PDB_CNT_CNT_WIDTH                        16
+#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK                       0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT                      0
+#define PDB_IDLY_IDLY_WIDTH                      16
+#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK                           0xFFu
+#define PDB_C1_EN_SHIFT                          0
+#define PDB_C1_EN_WIDTH                          8
+#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK                          0xFF00u
+#define PDB_C1_TOS_SHIFT                         8
+#define PDB_C1_TOS_WIDTH                         8
+#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK                           0xFF0000u
+#define PDB_C1_BB_SHIFT                          16
+#define PDB_C1_BB_WIDTH                          8
+#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK                           0xFFu
+#define PDB_S_ERR_SHIFT                          0
+#define PDB_S_ERR_WIDTH                          8
+#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK                            0xFF0000u
+#define PDB_S_CF_SHIFT                           16
+#define PDB_S_CF_WIDTH                           8
+#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK                         0xFFFFu
+#define PDB_DLY_DLY_SHIFT                        0
+#define PDB_DLY_DLY_WIDTH                        16
+#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* INTC Bit Fields */
+#define PDB_INTC_TOE_MASK                        0x1u
+#define PDB_INTC_TOE_SHIFT                       0
+#define PDB_INTC_TOE_WIDTH                       1
+#define PDB_INTC_TOE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_TOE_SHIFT))&PDB_INTC_TOE_MASK)
+#define PDB_INTC_EXT_MASK                        0x2u
+#define PDB_INTC_EXT_SHIFT                       1
+#define PDB_INTC_EXT_WIDTH                       1
+#define PDB_INTC_EXT(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_EXT_SHIFT))&PDB_INTC_EXT_MASK)
+/* INT Bit Fields */
+#define PDB_INT_INT_MASK                         0xFFFFu
+#define PDB_INT_INT_SHIFT                        0
+#define PDB_INT_INT_WIDTH                        16
+#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK                       0xFFu
+#define PDB_POEN_POEN_SHIFT                      0
+#define PDB_POEN_POEN_WIDTH                      8
+#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK                      0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT                     0
+#define PDB_PODLY_DLY2_WIDTH                     16
+#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK                      0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT                     16
+#define PDB_PODLY_DLY1_WIDTH                     16
+#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE                                (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0                                     ((PDB_Type *)PDB0_BASE)
+#define PDB0_BASE_PTR                            (PDB0)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS                           { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS                            { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS                                 { PDB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PDB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register instance definitions */
+/* PDB0 */
+#define PDB0_SC                                  PDB_SC_REG(PDB0)
+#define PDB0_MOD                                 PDB_MOD_REG(PDB0)
+#define PDB0_CNT                                 PDB_CNT_REG(PDB0)
+#define PDB0_IDLY                                PDB_IDLY_REG(PDB0)
+#define PDB0_CH0C1                               PDB_C1_REG(PDB0,0)
+#define PDB0_CH0S                                PDB_S_REG(PDB0,0)
+#define PDB0_CH0DLY0                             PDB_DLY_REG(PDB0,0,0)
+#define PDB0_CH0DLY1                             PDB_DLY_REG(PDB0,0,1)
+#define PDB0_CH1C1                               PDB_C1_REG(PDB0,1)
+#define PDB0_CH1S                                PDB_S_REG(PDB0,1)
+#define PDB0_CH1DLY0                             PDB_DLY_REG(PDB0,1,0)
+#define PDB0_CH1DLY1                             PDB_DLY_REG(PDB0,1,1)
+#define PDB0_DACINTC0                            PDB_INTC_REG(PDB0,0)
+#define PDB0_DACINT0                             PDB_INT_REG(PDB0,0)
+#define PDB0_DACINTC1                            PDB_INTC_REG(PDB0,1)
+#define PDB0_DACINT1                             PDB_INT_REG(PDB0,1)
+#define PDB0_POEN                                PDB_POEN_REG(PDB0)
+#define PDB0_PO0DLY                              PDB_PODLY_REG(PDB0,0)
+#define PDB0_PO1DLY                              PDB_PODLY_REG(PDB0,1)
+#define PDB0_PO2DLY                              PDB_PODLY_REG(PDB0,2)
+
+/* PDB - Register array accessors */
+#define PDB0_C1(index)                           PDB_C1_REG(PDB0,index)
+#define PDB0_S(index)                            PDB_S_REG(PDB0,index)
+#define PDB0_DLY(index,index2)                   PDB_DLY_REG(PDB0,index,index2)
+#define PDB0_INTC(index)                         PDB_INTC_REG(PDB0,index)
+#define PDB0_INT(index)                          PDB_INT_REG(PDB0,index)
+#define PDB0_PODLY(index)                        PDB_PODLY_REG(PDB0,index)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[252];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[4];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base)                        ((base)->MCR)
+#define PIT_LDVAL_REG(base,index)                ((base)->CHANNEL[index].LDVAL)
+#define PIT_LDVAL_COUNT                          4
+#define PIT_CVAL_REG(base,index)                 ((base)->CHANNEL[index].CVAL)
+#define PIT_CVAL_COUNT                           4
+#define PIT_TCTRL_REG(base,index)                ((base)->CHANNEL[index].TCTRL)
+#define PIT_TCTRL_COUNT                          4
+#define PIT_TFLG_REG(base,index)                 ((base)->CHANNEL[index].TFLG)
+#define PIT_TFLG_COUNT                           4
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK                         0x1u
+#define PIT_MCR_FRZ_SHIFT                        0
+#define PIT_MCR_FRZ_WIDTH                        1
+#define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK                        0x2u
+#define PIT_MCR_MDIS_SHIFT                       1
+#define PIT_MCR_MDIS_WIDTH                       1
+#define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT                      0
+#define PIT_LDVAL_TSV_WIDTH                      32
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT                       0
+#define PIT_CVAL_TVL_WIDTH                       32
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK                       0x1u
+#define PIT_TCTRL_TEN_SHIFT                      0
+#define PIT_TCTRL_TEN_WIDTH                      1
+#define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK                       0x2u
+#define PIT_TCTRL_TIE_SHIFT                      1
+#define PIT_TCTRL_TIE_WIDTH                      1
+#define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK                       0x4u
+#define PIT_TCTRL_CHN_SHIFT                      2
+#define PIT_TCTRL_CHN_WIDTH                      1
+#define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK                        0x1u
+#define PIT_TFLG_TIF_SHIFT                       0
+#define PIT_TFLG_TIF_WIDTH                       1
+#define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR                             (PIT)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS                           { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PIT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR                                  PIT_MCR_REG(PIT)
+#define PIT_LDVAL0                               PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0                                PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0                               PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0                                PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1                               PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1                                PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1                               PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1                                PIT_TFLG_REG(PIT,1)
+#define PIT_LDVAL2                               PIT_LDVAL_REG(PIT,2)
+#define PIT_CVAL2                                PIT_CVAL_REG(PIT,2)
+#define PIT_TCTRL2                               PIT_TCTRL_REG(PIT,2)
+#define PIT_TFLG2                                PIT_TFLG_REG(PIT,2)
+#define PIT_LDVAL3                               PIT_LDVAL_REG(PIT,3)
+#define PIT_CVAL3                                PIT_CVAL_REG(PIT,3)
+#define PIT_TCTRL3                               PIT_TCTRL_REG(PIT,3)
+#define PIT_TFLG3                                PIT_TFLG_REG(PIT,3)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index)                         PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index)                          PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index)                         PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index)                          PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base)                     ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base)                     ((base)->LVDSC2)
+#define PMC_REGSC_REG(base)                      ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK                     0x3u
+#define PMC_LVDSC1_LVDV_SHIFT                    0
+#define PMC_LVDSC1_LVDV_WIDTH                    2
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT                   4
+#define PMC_LVDSC1_LVDRE_WIDTH                   1
+#define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK                    0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT                   5
+#define PMC_LVDSC1_LVDIE_WIDTH                   1
+#define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK                   0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT                  6
+#define PMC_LVDSC1_LVDACK_WIDTH                  1
+#define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK                     0x80u
+#define PMC_LVDSC1_LVDF_SHIFT                    7
+#define PMC_LVDSC1_LVDF_WIDTH                    1
+#define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK                     0x3u
+#define PMC_LVDSC2_LVWV_SHIFT                    0
+#define PMC_LVDSC2_LVWV_WIDTH                    2
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT                   5
+#define PMC_LVDSC2_LVWIE_WIDTH                   1
+#define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK                   0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT                  6
+#define PMC_LVDSC2_LVWACK_WIDTH                  1
+#define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK                     0x80u
+#define PMC_LVDSC2_LVWF_SHIFT                    7
+#define PMC_LVDSC2_LVWF_WIDTH                    1
+#define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK                      0x1u
+#define PMC_REGSC_BGBE_SHIFT                     0
+#define PMC_REGSC_BGBE_WIDTH                     1
+#define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK                    0x4u
+#define PMC_REGSC_REGONS_SHIFT                   2
+#define PMC_REGSC_REGONS_WIDTH                   1
+#define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK                    0x8u
+#define PMC_REGSC_ACKISO_SHIFT                   3
+#define PMC_REGSC_ACKISO_WIDTH                   1
+#define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK                      0x10u
+#define PMC_REGSC_BGEN_SHIFT                     4
+#define PMC_REGSC_BGEN_WIDTH                     1
+#define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR                             (PMC)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS                           { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { LVD_LVW_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1                               PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2                               PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC                                PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
+  __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
+  __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index)                 ((base)->PCR[index])
+#define PORT_PCR_COUNT                           32
+#define PORT_GPCLR_REG(base)                     ((base)->GPCLR)
+#define PORT_GPCHR_REG(base)                     ((base)->GPCHR)
+#define PORT_ISFR_REG(base)                      ((base)->ISFR)
+#define PORT_DFER_REG(base)                      ((base)->DFER)
+#define PORT_DFCR_REG(base)                      ((base)->DFCR)
+#define PORT_DFWR_REG(base)                      ((base)->DFWR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK                         0x1u
+#define PORT_PCR_PS_SHIFT                        0
+#define PORT_PCR_PS_WIDTH                        1
+#define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK                         0x2u
+#define PORT_PCR_PE_SHIFT                        1
+#define PORT_PCR_PE_WIDTH                        1
+#define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK                        0x4u
+#define PORT_PCR_SRE_SHIFT                       2
+#define PORT_PCR_SRE_WIDTH                       1
+#define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK                        0x10u
+#define PORT_PCR_PFE_SHIFT                       4
+#define PORT_PCR_PFE_WIDTH                       1
+#define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK                        0x20u
+#define PORT_PCR_ODE_SHIFT                       5
+#define PORT_PCR_ODE_WIDTH                       1
+#define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK                        0x40u
+#define PORT_PCR_DSE_SHIFT                       6
+#define PORT_PCR_DSE_WIDTH                       1
+#define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK                        0x700u
+#define PORT_PCR_MUX_SHIFT                       8
+#define PORT_PCR_MUX_WIDTH                       3
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK                         0x8000u
+#define PORT_PCR_LK_SHIFT                        15
+#define PORT_PCR_LK_WIDTH                        1
+#define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK                       0xF0000u
+#define PORT_PCR_IRQC_SHIFT                      16
+#define PORT_PCR_IRQC_WIDTH                      4
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        0x1000000u
+#define PORT_PCR_ISF_SHIFT                       24
+#define PORT_PCR_ISF_WIDTH                       1
+#define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT                    0
+#define PORT_GPCLR_GPWD_WIDTH                    16
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT                    16
+#define PORT_GPCLR_GPWE_WIDTH                    16
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT                    0
+#define PORT_GPCHR_GPWD_WIDTH                    16
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT                    16
+#define PORT_GPCHR_GPWE_WIDTH                    16
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT                      0
+#define PORT_ISFR_ISF_WIDTH                      32
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK                       0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT                      0
+#define PORT_DFER_DFE_WIDTH                      32
+#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK                        0x1u
+#define PORT_DFCR_CS_SHIFT                       0
+#define PORT_DFCR_CS_WIDTH                       1
+#define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK                      0x1Fu
+#define PORT_DFWR_FILT_SHIFT                     0
+#define PORT_DFWR_FILT_WIDTH                     5
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR                           (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR                           (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR                           (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR                           (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR                           (PORTE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- PORT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0                               PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1                               PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2                               PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3                               PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4                               PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5                               PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6                               PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7                               PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8                               PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9                               PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10                              PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11                              PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12                              PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13                              PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14                              PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15                              PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16                              PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17                              PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18                              PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19                              PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20                              PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21                              PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22                              PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23                              PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24                              PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25                              PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26                              PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27                              PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28                              PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29                              PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30                              PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31                              PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR                              PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR                              PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR                               PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0                               PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1                               PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2                               PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3                               PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4                               PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5                               PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6                               PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7                               PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8                               PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9                               PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10                              PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11                              PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12                              PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13                              PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14                              PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15                              PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16                              PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17                              PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18                              PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19                              PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20                              PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21                              PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22                              PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23                              PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24                              PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25                              PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26                              PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27                              PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28                              PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29                              PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30                              PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31                              PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR                              PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR                              PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR                               PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0                               PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1                               PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2                               PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3                               PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4                               PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5                               PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6                               PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7                               PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8                               PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9                               PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10                              PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11                              PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12                              PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13                              PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14                              PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15                              PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16                              PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17                              PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18                              PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19                              PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20                              PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21                              PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22                              PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23                              PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24                              PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25                              PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26                              PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27                              PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28                              PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29                              PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30                              PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31                              PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR                              PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR                              PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR                               PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0                               PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1                               PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2                               PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3                               PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4                               PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5                               PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6                               PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7                               PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8                               PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9                               PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10                              PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11                              PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12                              PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13                              PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14                              PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15                              PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16                              PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17                              PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18                              PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19                              PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20                              PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21                              PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22                              PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23                              PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24                              PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25                              PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26                              PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27                              PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28                              PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29                              PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30                              PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31                              PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR                              PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR                              PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR                               PORT_ISFR_REG(PORTD)
+#define PORTD_DFER                               PORT_DFER_REG(PORTD)
+#define PORTD_DFCR                               PORT_DFCR_REG(PORTD)
+#define PORTD_DFWR                               PORT_DFWR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0                               PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1                               PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2                               PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3                               PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4                               PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5                               PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6                               PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7                               PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8                               PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9                               PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10                              PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11                              PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12                              PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13                              PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14                              PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15                              PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16                              PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17                              PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18                              PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19                              PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20                              PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21                              PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22                              PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23                              PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24                              PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25                              PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26                              PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27                              PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28                              PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29                              PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30                              PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31                              PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR                              PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR                              PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR                               PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index)                         PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index)                         PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index)                         PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index)                         PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index)                         PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+       uint8_t RESERVED_1[1];
+  __I  uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base)                       ((base)->SRS0)
+#define RCM_SRS1_REG(base)                       ((base)->SRS1)
+#define RCM_RPFC_REG(base)                       ((base)->RPFC)
+#define RCM_RPFW_REG(base)                       ((base)->RPFW)
+#define RCM_MR_REG(base)                         ((base)->MR)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK                     0x1u
+#define RCM_SRS0_WAKEUP_SHIFT                    0
+#define RCM_SRS0_WAKEUP_WIDTH                    1
+#define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK                        0x2u
+#define RCM_SRS0_LVD_SHIFT                       1
+#define RCM_SRS0_LVD_WIDTH                       1
+#define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK                        0x4u
+#define RCM_SRS0_LOC_SHIFT                       2
+#define RCM_SRS0_LOC_WIDTH                       1
+#define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOC_SHIFT))&RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK                        0x8u
+#define RCM_SRS0_LOL_SHIFT                       3
+#define RCM_SRS0_LOL_WIDTH                       1
+#define RCM_SRS0_LOL(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOL_SHIFT))&RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK                       0x20u
+#define RCM_SRS0_WDOG_SHIFT                      5
+#define RCM_SRS0_WDOG_WIDTH                      1
+#define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK                        0x40u
+#define RCM_SRS0_PIN_SHIFT                       6
+#define RCM_SRS0_PIN_WIDTH                       1
+#define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK                        0x80u
+#define RCM_SRS0_POR_SHIFT                       7
+#define RCM_SRS0_POR_WIDTH                       1
+#define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK                       0x1u
+#define RCM_SRS1_JTAG_SHIFT                      0
+#define RCM_SRS1_JTAG_WIDTH                      1
+#define RCM_SRS1_JTAG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_JTAG_SHIFT))&RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK                     0x2u
+#define RCM_SRS1_LOCKUP_SHIFT                    1
+#define RCM_SRS1_LOCKUP_WIDTH                    1
+#define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK                         0x4u
+#define RCM_SRS1_SW_SHIFT                        2
+#define RCM_SRS1_SW_WIDTH                        1
+#define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK                     0x8u
+#define RCM_SRS1_MDM_AP_SHIFT                    3
+#define RCM_SRS1_MDM_AP_WIDTH                    1
+#define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK                       0x10u
+#define RCM_SRS1_EZPT_SHIFT                      4
+#define RCM_SRS1_EZPT_WIDTH                      1
+#define RCM_SRS1_EZPT(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_EZPT_SHIFT))&RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK                    0x20u
+#define RCM_SRS1_SACKERR_SHIFT                   5
+#define RCM_SRS1_SACKERR_WIDTH                   1
+#define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 0
+#define RCM_RPFC_RSTFLTSRW_WIDTH                 2
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK                   0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT                  2
+#define RCM_RPFC_RSTFLTSS_WIDTH                  1
+#define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 0
+#define RCM_RPFW_RSTFLTSEL_WIDTH                 5
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK                       0x2u
+#define RCM_MR_EZP_MS_SHIFT                      1
+#define RCM_MR_EZP_MS_WIDTH                      1
+#define RCM_MR_EZP_MS(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_MR_EZP_MS_SHIFT))&RCM_MR_EZP_MS_MASK)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR                             (RCM)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS                           { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS                            { RCM }
+
+/* ----------------------------------------------------------------------------
+   -- RCM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0                                 RCM_SRS0_REG(RCM)
+#define RCM_SRS1                                 RCM_SRS1_REG(RCM)
+#define RCM_RPFC                                 RCM_RPFC_REG(RCM)
+#define RCM_RPFW                                 RCM_RPFW_REG(RCM)
+#define RCM_MR                                   RCM_MR_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index)                ((base)->REG[index])
+#define RFSYS_REG_COUNT                          8
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK                        0xFFu
+#define RFSYS_REG_LL_SHIFT                       0
+#define RFSYS_REG_LL_WIDTH                       8
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        0xFF00u
+#define RFSYS_REG_LH_SHIFT                       8
+#define RFSYS_REG_LH_WIDTH                       8
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        0xFF0000u
+#define RFSYS_REG_HL_SHIFT                       16
+#define RFSYS_REG_HL_WIDTH                       8
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        0xFF000000u
+#define RFSYS_REG_HH_SHIFT                       24
+#define RFSYS_REG_HH_WIDTH                       8
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR                           (RFSYS)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS                          { RFSYS }
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0                               RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1                               RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2                               RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3                               RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4                               RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5                               RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6                               RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7                               RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index)                         RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type, *RFVBAT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register accessors */
+#define RFVBAT_REG_REG(base,index)               ((base)->REG[index])
+#define RFVBAT_REG_COUNT                         8
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK                       0xFFu
+#define RFVBAT_REG_LL_SHIFT                      0
+#define RFVBAT_REG_LL_WIDTH                      8
+#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK                       0xFF00u
+#define RFVBAT_REG_LH_SHIFT                      8
+#define RFVBAT_REG_LH_WIDTH                      8
+#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK                       0xFF0000u
+#define RFVBAT_REG_HL_SHIFT                      16
+#define RFVBAT_REG_HL_WIDTH                      8
+#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK                       0xFF000000u
+#define RFVBAT_REG_HH_SHIFT                      24
+#define RFVBAT_REG_HH_WIDTH                      8
+#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE                              (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
+#define RFVBAT_BASE_PTR                          (RFVBAT)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS                        { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS                         { RFVBAT }
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register instance definitions */
+/* RFVBAT */
+#define RFVBAT_REG0                              RFVBAT_REG_REG(RFVBAT,0)
+#define RFVBAT_REG1                              RFVBAT_REG_REG(RFVBAT,1)
+#define RFVBAT_REG2                              RFVBAT_REG_REG(RFVBAT,2)
+#define RFVBAT_REG3                              RFVBAT_REG_REG(RFVBAT,3)
+#define RFVBAT_REG4                              RFVBAT_REG_REG(RFVBAT,4)
+#define RFVBAT_REG5                              RFVBAT_REG_REG(RFVBAT,5)
+#define RFVBAT_REG6                              RFVBAT_REG_REG(RFVBAT,6)
+#define RFVBAT_REG7                              RFVBAT_REG_REG(RFVBAT,7)
+
+/* RFVBAT - Register array accessors */
+#define RFVBAT_REG(index)                        RFVBAT_REG_REG(RFVBAT,index)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< RNGA Control Register, offset: 0x0 */
+  __I  uint32_t SR;                                /**< RNGA Status Register, offset: 0x4 */
+  __O  uint32_t ER;                                /**< RNGA Entropy Register, offset: 0x8 */
+  __I  uint32_t OR;                                /**< RNGA Output Register, offset: 0xC */
+} RNG_Type, *RNG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register accessors */
+#define RNG_CR_REG(base)                         ((base)->CR)
+#define RNG_SR_REG(base)                         ((base)->SR)
+#define RNG_ER_REG(base)                         ((base)->ER)
+#define RNG_OR_REG(base)                         ((base)->OR)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define RNG_CR_GO_MASK                           0x1u
+#define RNG_CR_GO_SHIFT                          0
+#define RNG_CR_GO_WIDTH                          1
+#define RNG_CR_GO(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_GO_SHIFT))&RNG_CR_GO_MASK)
+#define RNG_CR_HA_MASK                           0x2u
+#define RNG_CR_HA_SHIFT                          1
+#define RNG_CR_HA_WIDTH                          1
+#define RNG_CR_HA(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_HA_SHIFT))&RNG_CR_HA_MASK)
+#define RNG_CR_INTM_MASK                         0x4u
+#define RNG_CR_INTM_SHIFT                        2
+#define RNG_CR_INTM_WIDTH                        1
+#define RNG_CR_INTM(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_INTM_SHIFT))&RNG_CR_INTM_MASK)
+#define RNG_CR_CLRI_MASK                         0x8u
+#define RNG_CR_CLRI_SHIFT                        3
+#define RNG_CR_CLRI_WIDTH                        1
+#define RNG_CR_CLRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_CLRI_SHIFT))&RNG_CR_CLRI_MASK)
+#define RNG_CR_SLP_MASK                          0x10u
+#define RNG_CR_SLP_SHIFT                         4
+#define RNG_CR_SLP_WIDTH                         1
+#define RNG_CR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_CR_SLP_SHIFT))&RNG_CR_SLP_MASK)
+/* SR Bit Fields */
+#define RNG_SR_SECV_MASK                         0x1u
+#define RNG_SR_SECV_SHIFT                        0
+#define RNG_SR_SECV_WIDTH                        1
+#define RNG_SR_SECV(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_SECV_SHIFT))&RNG_SR_SECV_MASK)
+#define RNG_SR_LRS_MASK                          0x2u
+#define RNG_SR_LRS_SHIFT                         1
+#define RNG_SR_LRS_WIDTH                         1
+#define RNG_SR_LRS(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_LRS_SHIFT))&RNG_SR_LRS_MASK)
+#define RNG_SR_ORU_MASK                          0x4u
+#define RNG_SR_ORU_SHIFT                         2
+#define RNG_SR_ORU_WIDTH                         1
+#define RNG_SR_ORU(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_ORU_SHIFT))&RNG_SR_ORU_MASK)
+#define RNG_SR_ERRI_MASK                         0x8u
+#define RNG_SR_ERRI_SHIFT                        3
+#define RNG_SR_ERRI_WIDTH                        1
+#define RNG_SR_ERRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_ERRI_SHIFT))&RNG_SR_ERRI_MASK)
+#define RNG_SR_SLP_MASK                          0x10u
+#define RNG_SR_SLP_SHIFT                         4
+#define RNG_SR_SLP_WIDTH                         1
+#define RNG_SR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_SLP_SHIFT))&RNG_SR_SLP_MASK)
+#define RNG_SR_OREG_LVL_MASK                     0xFF00u
+#define RNG_SR_OREG_LVL_SHIFT                    8
+#define RNG_SR_OREG_LVL_WIDTH                    8
+#define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK                    0xFF0000u
+#define RNG_SR_OREG_SIZE_SHIFT                   16
+#define RNG_SR_OREG_SIZE_WIDTH                   8
+#define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
+/* ER Bit Fields */
+#define RNG_ER_EXT_ENT_MASK                      0xFFFFFFFFu
+#define RNG_ER_EXT_ENT_SHIFT                     0
+#define RNG_ER_EXT_ENT_WIDTH                     32
+#define RNG_ER_EXT_ENT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
+/* OR Bit Fields */
+#define RNG_OR_RANDOUT_MASK                      0xFFFFFFFFu
+#define RNG_OR_RANDOUT_SHIFT                     0
+#define RNG_OR_RANDOUT_WIDTH                     32
+#define RNG_OR_RANDOUT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE                                 (0x40029000u)
+/** Peripheral RNG base pointer */
+#define RNG                                      ((RNG_Type *)RNG_BASE)
+#define RNG_BASE_PTR                             (RNG)
+/** Array initializer of RNG peripheral base addresses */
+#define RNG_BASE_ADDRS                           { RNG_BASE }
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASE_PTRS                            { RNG }
+/** Interrupt vectors for the RNG peripheral type */
+#define RNG_IRQS                                 { RNG_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RNG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register instance definitions */
+/* RNG */
+#define RNG_CR                                   RNG_CR_REG(RNG)
+#define RNG_SR                                   RNG_SR_REG(RNG)
+#define RNG_ER                                   RNG_ER_REG(RNG)
+#define RNG_OR                                   RNG_OR_REG(RNG)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+       uint8_t RESERVED_0[2016];
+  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base)                        ((base)->TSR)
+#define RTC_TPR_REG(base)                        ((base)->TPR)
+#define RTC_TAR_REG(base)                        ((base)->TAR)
+#define RTC_TCR_REG(base)                        ((base)->TCR)
+#define RTC_CR_REG(base)                         ((base)->CR)
+#define RTC_SR_REG(base)                         ((base)->SR)
+#define RTC_LR_REG(base)                         ((base)->LR)
+#define RTC_IER_REG(base)                        ((base)->IER)
+#define RTC_WAR_REG(base)                        ((base)->WAR)
+#define RTC_RAR_REG(base)                        ((base)->RAR)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT                        0
+#define RTC_TSR_TSR_WIDTH                        32
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK                         0xFFFFu
+#define RTC_TPR_TPR_SHIFT                        0
+#define RTC_TPR_TPR_WIDTH                        16
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT                        0
+#define RTC_TAR_TAR_WIDTH                        32
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK                         0xFFu
+#define RTC_TCR_TCR_SHIFT                        0
+#define RTC_TCR_TCR_WIDTH                        8
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         0xFF00u
+#define RTC_TCR_CIR_SHIFT                        8
+#define RTC_TCR_CIR_WIDTH                        8
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         0xFF0000u
+#define RTC_TCR_TCV_SHIFT                        16
+#define RTC_TCR_TCV_WIDTH                        8
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         0xFF000000u
+#define RTC_TCR_CIC_SHIFT                        24
+#define RTC_TCR_CIC_WIDTH                        8
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK                          0x1u
+#define RTC_CR_SWR_SHIFT                         0
+#define RTC_CR_SWR_WIDTH                         1
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK                          0x2u
+#define RTC_CR_WPE_SHIFT                         1
+#define RTC_CR_WPE_WIDTH                         1
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK                          0x4u
+#define RTC_CR_SUP_SHIFT                         2
+#define RTC_CR_SUP_WIDTH                         1
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK                           0x8u
+#define RTC_CR_UM_SHIFT                          3
+#define RTC_CR_UM_WIDTH                          1
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK                          0x10u
+#define RTC_CR_WPS_SHIFT                         4
+#define RTC_CR_WPS_WIDTH                         1
+#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK                         0x100u
+#define RTC_CR_OSCE_SHIFT                        8
+#define RTC_CR_OSCE_WIDTH                        1
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK                         0x200u
+#define RTC_CR_CLKO_SHIFT                        9
+#define RTC_CR_CLKO_WIDTH                        1
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK                        0x400u
+#define RTC_CR_SC16P_SHIFT                       10
+#define RTC_CR_SC16P_WIDTH                       1
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK                         0x800u
+#define RTC_CR_SC8P_SHIFT                        11
+#define RTC_CR_SC8P_WIDTH                        1
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK                         0x1000u
+#define RTC_CR_SC4P_SHIFT                        12
+#define RTC_CR_SC4P_WIDTH                        1
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK                         0x2000u
+#define RTC_CR_SC2P_SHIFT                        13
+#define RTC_CR_SC2P_WIDTH                        1
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK                          0x1u
+#define RTC_SR_TIF_SHIFT                         0
+#define RTC_SR_TIF_WIDTH                         1
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK                          0x2u
+#define RTC_SR_TOF_SHIFT                         1
+#define RTC_SR_TOF_WIDTH                         1
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK                          0x4u
+#define RTC_SR_TAF_SHIFT                         2
+#define RTC_SR_TAF_WIDTH                         1
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK                          0x10u
+#define RTC_SR_TCE_SHIFT                         4
+#define RTC_SR_TCE_WIDTH                         1
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK                          0x8u
+#define RTC_LR_TCL_SHIFT                         3
+#define RTC_LR_TCL_WIDTH                         1
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK                          0x10u
+#define RTC_LR_CRL_SHIFT                         4
+#define RTC_LR_CRL_WIDTH                         1
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK                          0x20u
+#define RTC_LR_SRL_SHIFT                         5
+#define RTC_LR_SRL_WIDTH                         1
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK                          0x40u
+#define RTC_LR_LRL_SHIFT                         6
+#define RTC_LR_LRL_WIDTH                         1
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK                        0x1u
+#define RTC_IER_TIIE_SHIFT                       0
+#define RTC_IER_TIIE_WIDTH                       1
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK                        0x2u
+#define RTC_IER_TOIE_SHIFT                       1
+#define RTC_IER_TOIE_WIDTH                       1
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK                        0x4u
+#define RTC_IER_TAIE_SHIFT                       2
+#define RTC_IER_TAIE_WIDTH                       1
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK                        0x10u
+#define RTC_IER_TSIE_SHIFT                       4
+#define RTC_IER_TSIE_WIDTH                       1
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK                        0x80u
+#define RTC_IER_WPON_SHIFT                       7
+#define RTC_IER_WPON_WIDTH                       1
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK                        0x1u
+#define RTC_WAR_TSRW_SHIFT                       0
+#define RTC_WAR_TSRW_WIDTH                       1
+#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TSRW_SHIFT))&RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK                        0x2u
+#define RTC_WAR_TPRW_SHIFT                       1
+#define RTC_WAR_TPRW_WIDTH                       1
+#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TPRW_SHIFT))&RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK                        0x4u
+#define RTC_WAR_TARW_SHIFT                       2
+#define RTC_WAR_TARW_WIDTH                       1
+#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TARW_SHIFT))&RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK                        0x8u
+#define RTC_WAR_TCRW_SHIFT                       3
+#define RTC_WAR_TCRW_WIDTH                       1
+#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TCRW_SHIFT))&RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK                         0x10u
+#define RTC_WAR_CRW_SHIFT                        4
+#define RTC_WAR_CRW_WIDTH                        1
+#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_CRW_SHIFT))&RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK                         0x20u
+#define RTC_WAR_SRW_SHIFT                        5
+#define RTC_WAR_SRW_WIDTH                        1
+#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_SRW_SHIFT))&RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK                         0x40u
+#define RTC_WAR_LRW_SHIFT                        6
+#define RTC_WAR_LRW_WIDTH                        1
+#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_LRW_SHIFT))&RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK                        0x80u
+#define RTC_WAR_IERW_SHIFT                       7
+#define RTC_WAR_IERW_WIDTH                       1
+#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_IERW_SHIFT))&RTC_WAR_IERW_MASK)
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK                        0x1u
+#define RTC_RAR_TSRR_SHIFT                       0
+#define RTC_RAR_TSRR_WIDTH                       1
+#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TSRR_SHIFT))&RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK                        0x2u
+#define RTC_RAR_TPRR_SHIFT                       1
+#define RTC_RAR_TPRR_WIDTH                       1
+#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TPRR_SHIFT))&RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK                        0x4u
+#define RTC_RAR_TARR_SHIFT                       2
+#define RTC_RAR_TARR_WIDTH                       1
+#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TARR_SHIFT))&RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK                        0x8u
+#define RTC_RAR_TCRR_SHIFT                       3
+#define RTC_RAR_TCRR_WIDTH                       1
+#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TCRR_SHIFT))&RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK                         0x10u
+#define RTC_RAR_CRR_SHIFT                        4
+#define RTC_RAR_CRR_WIDTH                        1
+#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_CRR_SHIFT))&RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK                         0x20u
+#define RTC_RAR_SRR_SHIFT                        5
+#define RTC_RAR_SRR_WIDTH                        1
+#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_SRR_SHIFT))&RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK                         0x40u
+#define RTC_RAR_LRR_SHIFT                        6
+#define RTC_RAR_LRR_WIDTH                        1
+#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_LRR_SHIFT))&RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK                        0x80u
+#define RTC_RAR_IERR_SHIFT                       7
+#define RTC_RAR_IERR_WIDTH                       1
+#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_IERR_SHIFT))&RTC_RAR_IERR_MASK)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR                             (RTC)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- RTC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR                                  RTC_TSR_REG(RTC)
+#define RTC_TPR                                  RTC_TPR_REG(RTC)
+#define RTC_TAR                                  RTC_TAR_REG(RTC)
+#define RTC_TCR                                  RTC_TCR_REG(RTC)
+#define RTC_CR                                   RTC_CR_REG(RTC)
+#define RTC_SR                                   RTC_SR_REG(RTC)
+#define RTC_LR                                   RTC_LR_REG(RTC)
+#define RTC_IER                                  RTC_IER_REG(RTC)
+#define RTC_WAR                                  RTC_WAR_REG(RTC)
+#define RTC_RAR                                  RTC_RAR_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
+ * @{
+ */
+
+/** SDHC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DSADDR;                            /**< DMA System Address register, offset: 0x0 */
+  __IO uint32_t BLKATTR;                           /**< Block Attributes register, offset: 0x4 */
+  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x8 */
+  __IO uint32_t XFERTYP;                           /**< Transfer Type register, offset: 0xC */
+  __I  uint32_t CMDRSP[4];                         /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t DATPORT;                           /**< Buffer Data Port register, offset: 0x20 */
+  __I  uint32_t PRSSTAT;                           /**< Present State register, offset: 0x24 */
+  __IO uint32_t PROCTL;                            /**< Protocol Control register, offset: 0x28 */
+  __IO uint32_t SYSCTL;                            /**< System Control register, offset: 0x2C */
+  __IO uint32_t IRQSTAT;                           /**< Interrupt Status register, offset: 0x30 */
+  __IO uint32_t IRQSTATEN;                         /**< Interrupt Status Enable register, offset: 0x34 */
+  __IO uint32_t IRQSIGEN;                          /**< Interrupt Signal Enable register, offset: 0x38 */
+  __I  uint32_t AC12ERR;                           /**< Auto CMD12 Error Status Register, offset: 0x3C */
+  __I  uint32_t HTCAPBLT;                          /**< Host Controller Capabilities, offset: 0x40 */
+  __IO uint32_t WML;                               /**< Watermark Level Register, offset: 0x44 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t FEVT;                              /**< Force Event register, offset: 0x50 */
+  __I  uint32_t ADMAES;                            /**< ADMA Error Status register, offset: 0x54 */
+  __IO uint32_t ADSADDR;                           /**< ADMA System Addressregister, offset: 0x58 */
+       uint8_t RESERVED_1[100];
+  __IO uint32_t VENDOR;                            /**< Vendor Specific register, offset: 0xC0 */
+  __IO uint32_t MMCBOOT;                           /**< MMC Boot register, offset: 0xC4 */
+       uint8_t RESERVED_2[52];
+  __I  uint32_t HOSTVER;                           /**< Host Controller Version, offset: 0xFC */
+} SDHC_Type, *SDHC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register accessors */
+#define SDHC_DSADDR_REG(base)                    ((base)->DSADDR)
+#define SDHC_BLKATTR_REG(base)                   ((base)->BLKATTR)
+#define SDHC_CMDARG_REG(base)                    ((base)->CMDARG)
+#define SDHC_XFERTYP_REG(base)                   ((base)->XFERTYP)
+#define SDHC_CMDRSP_REG(base,index)              ((base)->CMDRSP[index])
+#define SDHC_CMDRSP_COUNT                        4
+#define SDHC_DATPORT_REG(base)                   ((base)->DATPORT)
+#define SDHC_PRSSTAT_REG(base)                   ((base)->PRSSTAT)
+#define SDHC_PROCTL_REG(base)                    ((base)->PROCTL)
+#define SDHC_SYSCTL_REG(base)                    ((base)->SYSCTL)
+#define SDHC_IRQSTAT_REG(base)                   ((base)->IRQSTAT)
+#define SDHC_IRQSTATEN_REG(base)                 ((base)->IRQSTATEN)
+#define SDHC_IRQSIGEN_REG(base)                  ((base)->IRQSIGEN)
+#define SDHC_AC12ERR_REG(base)                   ((base)->AC12ERR)
+#define SDHC_HTCAPBLT_REG(base)                  ((base)->HTCAPBLT)
+#define SDHC_WML_REG(base)                       ((base)->WML)
+#define SDHC_FEVT_REG(base)                      ((base)->FEVT)
+#define SDHC_ADMAES_REG(base)                    ((base)->ADMAES)
+#define SDHC_ADSADDR_REG(base)                   ((base)->ADSADDR)
+#define SDHC_VENDOR_REG(base)                    ((base)->VENDOR)
+#define SDHC_MMCBOOT_REG(base)                   ((base)->MMCBOOT)
+#define SDHC_HOSTVER_REG(base)                   ((base)->HOSTVER)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/* DSADDR Bit Fields */
+#define SDHC_DSADDR_DSADDR_MASK                  0xFFFFFFFCu
+#define SDHC_DSADDR_DSADDR_SHIFT                 2
+#define SDHC_DSADDR_DSADDR_WIDTH                 30
+#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
+/* BLKATTR Bit Fields */
+#define SDHC_BLKATTR_BLKSIZE_MASK                0x1FFFu
+#define SDHC_BLKATTR_BLKSIZE_SHIFT               0
+#define SDHC_BLKATTR_BLKSIZE_WIDTH               13
+#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK                 0xFFFF0000u
+#define SDHC_BLKATTR_BLKCNT_SHIFT                16
+#define SDHC_BLKATTR_BLKCNT_WIDTH                16
+#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
+/* CMDARG Bit Fields */
+#define SDHC_CMDARG_CMDARG_MASK                  0xFFFFFFFFu
+#define SDHC_CMDARG_CMDARG_SHIFT                 0
+#define SDHC_CMDARG_CMDARG_WIDTH                 32
+#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
+/* XFERTYP Bit Fields */
+#define SDHC_XFERTYP_DMAEN_MASK                  0x1u
+#define SDHC_XFERTYP_DMAEN_SHIFT                 0
+#define SDHC_XFERTYP_DMAEN_WIDTH                 1
+#define SDHC_XFERTYP_DMAEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DMAEN_SHIFT))&SDHC_XFERTYP_DMAEN_MASK)
+#define SDHC_XFERTYP_BCEN_MASK                   0x2u
+#define SDHC_XFERTYP_BCEN_SHIFT                  1
+#define SDHC_XFERTYP_BCEN_WIDTH                  1
+#define SDHC_XFERTYP_BCEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_BCEN_SHIFT))&SDHC_XFERTYP_BCEN_MASK)
+#define SDHC_XFERTYP_AC12EN_MASK                 0x4u
+#define SDHC_XFERTYP_AC12EN_SHIFT                2
+#define SDHC_XFERTYP_AC12EN_WIDTH                1
+#define SDHC_XFERTYP_AC12EN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_AC12EN_SHIFT))&SDHC_XFERTYP_AC12EN_MASK)
+#define SDHC_XFERTYP_DTDSEL_MASK                 0x10u
+#define SDHC_XFERTYP_DTDSEL_SHIFT                4
+#define SDHC_XFERTYP_DTDSEL_WIDTH                1
+#define SDHC_XFERTYP_DTDSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DTDSEL_SHIFT))&SDHC_XFERTYP_DTDSEL_MASK)
+#define SDHC_XFERTYP_MSBSEL_MASK                 0x20u
+#define SDHC_XFERTYP_MSBSEL_SHIFT                5
+#define SDHC_XFERTYP_MSBSEL_WIDTH                1
+#define SDHC_XFERTYP_MSBSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_MSBSEL_SHIFT))&SDHC_XFERTYP_MSBSEL_MASK)
+#define SDHC_XFERTYP_RSPTYP_MASK                 0x30000u
+#define SDHC_XFERTYP_RSPTYP_SHIFT                16
+#define SDHC_XFERTYP_RSPTYP_WIDTH                2
+#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK                  0x80000u
+#define SDHC_XFERTYP_CCCEN_SHIFT                 19
+#define SDHC_XFERTYP_CCCEN_WIDTH                 1
+#define SDHC_XFERTYP_CCCEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CCCEN_SHIFT))&SDHC_XFERTYP_CCCEN_MASK)
+#define SDHC_XFERTYP_CICEN_MASK                  0x100000u
+#define SDHC_XFERTYP_CICEN_SHIFT                 20
+#define SDHC_XFERTYP_CICEN_WIDTH                 1
+#define SDHC_XFERTYP_CICEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CICEN_SHIFT))&SDHC_XFERTYP_CICEN_MASK)
+#define SDHC_XFERTYP_DPSEL_MASK                  0x200000u
+#define SDHC_XFERTYP_DPSEL_SHIFT                 21
+#define SDHC_XFERTYP_DPSEL_WIDTH                 1
+#define SDHC_XFERTYP_DPSEL(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DPSEL_SHIFT))&SDHC_XFERTYP_DPSEL_MASK)
+#define SDHC_XFERTYP_CMDTYP_MASK                 0xC00000u
+#define SDHC_XFERTYP_CMDTYP_SHIFT                22
+#define SDHC_XFERTYP_CMDTYP_WIDTH                2
+#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK                 0x3F000000u
+#define SDHC_XFERTYP_CMDINX_SHIFT                24
+#define SDHC_XFERTYP_CMDINX_WIDTH                6
+#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
+/* CMDRSP Bit Fields */
+#define SDHC_CMDRSP_CMDRSP0_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP0_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP0_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP1_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP1_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP2_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP2_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP3_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP3_WIDTH                32
+#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
+/* DATPORT Bit Fields */
+#define SDHC_DATPORT_DATCONT_MASK                0xFFFFFFFFu
+#define SDHC_DATPORT_DATCONT_SHIFT               0
+#define SDHC_DATPORT_DATCONT_WIDTH               32
+#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
+/* PRSSTAT Bit Fields */
+#define SDHC_PRSSTAT_CIHB_MASK                   0x1u
+#define SDHC_PRSSTAT_CIHB_SHIFT                  0
+#define SDHC_PRSSTAT_CIHB_WIDTH                  1
+#define SDHC_PRSSTAT_CIHB(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CIHB_SHIFT))&SDHC_PRSSTAT_CIHB_MASK)
+#define SDHC_PRSSTAT_CDIHB_MASK                  0x2u
+#define SDHC_PRSSTAT_CDIHB_SHIFT                 1
+#define SDHC_PRSSTAT_CDIHB_WIDTH                 1
+#define SDHC_PRSSTAT_CDIHB(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CDIHB_SHIFT))&SDHC_PRSSTAT_CDIHB_MASK)
+#define SDHC_PRSSTAT_DLA_MASK                    0x4u
+#define SDHC_PRSSTAT_DLA_SHIFT                   2
+#define SDHC_PRSSTAT_DLA_WIDTH                   1
+#define SDHC_PRSSTAT_DLA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLA_SHIFT))&SDHC_PRSSTAT_DLA_MASK)
+#define SDHC_PRSSTAT_SDSTB_MASK                  0x8u
+#define SDHC_PRSSTAT_SDSTB_SHIFT                 3
+#define SDHC_PRSSTAT_SDSTB_WIDTH                 1
+#define SDHC_PRSSTAT_SDSTB(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDSTB_SHIFT))&SDHC_PRSSTAT_SDSTB_MASK)
+#define SDHC_PRSSTAT_IPGOFF_MASK                 0x10u
+#define SDHC_PRSSTAT_IPGOFF_SHIFT                4
+#define SDHC_PRSSTAT_IPGOFF_WIDTH                1
+#define SDHC_PRSSTAT_IPGOFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_IPGOFF_SHIFT))&SDHC_PRSSTAT_IPGOFF_MASK)
+#define SDHC_PRSSTAT_HCKOFF_MASK                 0x20u
+#define SDHC_PRSSTAT_HCKOFF_SHIFT                5
+#define SDHC_PRSSTAT_HCKOFF_WIDTH                1
+#define SDHC_PRSSTAT_HCKOFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_HCKOFF_SHIFT))&SDHC_PRSSTAT_HCKOFF_MASK)
+#define SDHC_PRSSTAT_PEROFF_MASK                 0x40u
+#define SDHC_PRSSTAT_PEROFF_SHIFT                6
+#define SDHC_PRSSTAT_PEROFF_WIDTH                1
+#define SDHC_PRSSTAT_PEROFF(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_PEROFF_SHIFT))&SDHC_PRSSTAT_PEROFF_MASK)
+#define SDHC_PRSSTAT_SDOFF_MASK                  0x80u
+#define SDHC_PRSSTAT_SDOFF_SHIFT                 7
+#define SDHC_PRSSTAT_SDOFF_WIDTH                 1
+#define SDHC_PRSSTAT_SDOFF(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDOFF_SHIFT))&SDHC_PRSSTAT_SDOFF_MASK)
+#define SDHC_PRSSTAT_WTA_MASK                    0x100u
+#define SDHC_PRSSTAT_WTA_SHIFT                   8
+#define SDHC_PRSSTAT_WTA_WIDTH                   1
+#define SDHC_PRSSTAT_WTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_WTA_SHIFT))&SDHC_PRSSTAT_WTA_MASK)
+#define SDHC_PRSSTAT_RTA_MASK                    0x200u
+#define SDHC_PRSSTAT_RTA_SHIFT                   9
+#define SDHC_PRSSTAT_RTA_WIDTH                   1
+#define SDHC_PRSSTAT_RTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_RTA_SHIFT))&SDHC_PRSSTAT_RTA_MASK)
+#define SDHC_PRSSTAT_BWEN_MASK                   0x400u
+#define SDHC_PRSSTAT_BWEN_SHIFT                  10
+#define SDHC_PRSSTAT_BWEN_WIDTH                  1
+#define SDHC_PRSSTAT_BWEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BWEN_SHIFT))&SDHC_PRSSTAT_BWEN_MASK)
+#define SDHC_PRSSTAT_BREN_MASK                   0x800u
+#define SDHC_PRSSTAT_BREN_SHIFT                  11
+#define SDHC_PRSSTAT_BREN_WIDTH                  1
+#define SDHC_PRSSTAT_BREN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BREN_SHIFT))&SDHC_PRSSTAT_BREN_MASK)
+#define SDHC_PRSSTAT_CINS_MASK                   0x10000u
+#define SDHC_PRSSTAT_CINS_SHIFT                  16
+#define SDHC_PRSSTAT_CINS_WIDTH                  1
+#define SDHC_PRSSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CINS_SHIFT))&SDHC_PRSSTAT_CINS_MASK)
+#define SDHC_PRSSTAT_CLSL_MASK                   0x800000u
+#define SDHC_PRSSTAT_CLSL_SHIFT                  23
+#define SDHC_PRSSTAT_CLSL_WIDTH                  1
+#define SDHC_PRSSTAT_CLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CLSL_SHIFT))&SDHC_PRSSTAT_CLSL_MASK)
+#define SDHC_PRSSTAT_DLSL_MASK                   0xFF000000u
+#define SDHC_PRSSTAT_DLSL_SHIFT                  24
+#define SDHC_PRSSTAT_DLSL_WIDTH                  8
+#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
+/* PROCTL Bit Fields */
+#define SDHC_PROCTL_LCTL_MASK                    0x1u
+#define SDHC_PROCTL_LCTL_SHIFT                   0
+#define SDHC_PROCTL_LCTL_WIDTH                   1
+#define SDHC_PROCTL_LCTL(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_LCTL_SHIFT))&SDHC_PROCTL_LCTL_MASK)
+#define SDHC_PROCTL_DTW_MASK                     0x6u
+#define SDHC_PROCTL_DTW_SHIFT                    1
+#define SDHC_PROCTL_DTW_WIDTH                    2
+#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK                    0x8u
+#define SDHC_PROCTL_D3CD_SHIFT                   3
+#define SDHC_PROCTL_D3CD_WIDTH                   1
+#define SDHC_PROCTL_D3CD(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_D3CD_SHIFT))&SDHC_PROCTL_D3CD_MASK)
+#define SDHC_PROCTL_EMODE_MASK                   0x30u
+#define SDHC_PROCTL_EMODE_SHIFT                  4
+#define SDHC_PROCTL_EMODE_WIDTH                  2
+#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK                    0x40u
+#define SDHC_PROCTL_CDTL_SHIFT                   6
+#define SDHC_PROCTL_CDTL_WIDTH                   1
+#define SDHC_PROCTL_CDTL(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDTL_SHIFT))&SDHC_PROCTL_CDTL_MASK)
+#define SDHC_PROCTL_CDSS_MASK                    0x80u
+#define SDHC_PROCTL_CDSS_SHIFT                   7
+#define SDHC_PROCTL_CDSS_WIDTH                   1
+#define SDHC_PROCTL_CDSS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDSS_SHIFT))&SDHC_PROCTL_CDSS_MASK)
+#define SDHC_PROCTL_DMAS_MASK                    0x300u
+#define SDHC_PROCTL_DMAS_SHIFT                   8
+#define SDHC_PROCTL_DMAS_WIDTH                   2
+#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK                 0x10000u
+#define SDHC_PROCTL_SABGREQ_SHIFT                16
+#define SDHC_PROCTL_SABGREQ_WIDTH                1
+#define SDHC_PROCTL_SABGREQ(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_SABGREQ_SHIFT))&SDHC_PROCTL_SABGREQ_MASK)
+#define SDHC_PROCTL_CREQ_MASK                    0x20000u
+#define SDHC_PROCTL_CREQ_SHIFT                   17
+#define SDHC_PROCTL_CREQ_WIDTH                   1
+#define SDHC_PROCTL_CREQ(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CREQ_SHIFT))&SDHC_PROCTL_CREQ_MASK)
+#define SDHC_PROCTL_RWCTL_MASK                   0x40000u
+#define SDHC_PROCTL_RWCTL_SHIFT                  18
+#define SDHC_PROCTL_RWCTL_WIDTH                  1
+#define SDHC_PROCTL_RWCTL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_RWCTL_SHIFT))&SDHC_PROCTL_RWCTL_MASK)
+#define SDHC_PROCTL_IABG_MASK                    0x80000u
+#define SDHC_PROCTL_IABG_SHIFT                   19
+#define SDHC_PROCTL_IABG_WIDTH                   1
+#define SDHC_PROCTL_IABG(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_IABG_SHIFT))&SDHC_PROCTL_IABG_MASK)
+#define SDHC_PROCTL_WECINT_MASK                  0x1000000u
+#define SDHC_PROCTL_WECINT_SHIFT                 24
+#define SDHC_PROCTL_WECINT_WIDTH                 1
+#define SDHC_PROCTL_WECINT(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINT_SHIFT))&SDHC_PROCTL_WECINT_MASK)
+#define SDHC_PROCTL_WECINS_MASK                  0x2000000u
+#define SDHC_PROCTL_WECINS_SHIFT                 25
+#define SDHC_PROCTL_WECINS_WIDTH                 1
+#define SDHC_PROCTL_WECINS(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINS_SHIFT))&SDHC_PROCTL_WECINS_MASK)
+#define SDHC_PROCTL_WECRM_MASK                   0x4000000u
+#define SDHC_PROCTL_WECRM_SHIFT                  26
+#define SDHC_PROCTL_WECRM_WIDTH                  1
+#define SDHC_PROCTL_WECRM(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECRM_SHIFT))&SDHC_PROCTL_WECRM_MASK)
+/* SYSCTL Bit Fields */
+#define SDHC_SYSCTL_IPGEN_MASK                   0x1u
+#define SDHC_SYSCTL_IPGEN_SHIFT                  0
+#define SDHC_SYSCTL_IPGEN_WIDTH                  1
+#define SDHC_SYSCTL_IPGEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_IPGEN_SHIFT))&SDHC_SYSCTL_IPGEN_MASK)
+#define SDHC_SYSCTL_HCKEN_MASK                   0x2u
+#define SDHC_SYSCTL_HCKEN_SHIFT                  1
+#define SDHC_SYSCTL_HCKEN_WIDTH                  1
+#define SDHC_SYSCTL_HCKEN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_HCKEN_SHIFT))&SDHC_SYSCTL_HCKEN_MASK)
+#define SDHC_SYSCTL_PEREN_MASK                   0x4u
+#define SDHC_SYSCTL_PEREN_SHIFT                  2
+#define SDHC_SYSCTL_PEREN_WIDTH                  1
+#define SDHC_SYSCTL_PEREN(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_PEREN_SHIFT))&SDHC_SYSCTL_PEREN_MASK)
+#define SDHC_SYSCTL_SDCLKEN_MASK                 0x8u
+#define SDHC_SYSCTL_SDCLKEN_SHIFT                3
+#define SDHC_SYSCTL_SDCLKEN_WIDTH                1
+#define SDHC_SYSCTL_SDCLKEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKEN_SHIFT))&SDHC_SYSCTL_SDCLKEN_MASK)
+#define SDHC_SYSCTL_DVS_MASK                     0xF0u
+#define SDHC_SYSCTL_DVS_SHIFT                    4
+#define SDHC_SYSCTL_DVS_WIDTH                    4
+#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK                 0xFF00u
+#define SDHC_SYSCTL_SDCLKFS_SHIFT                8
+#define SDHC_SYSCTL_SDCLKFS_WIDTH                8
+#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK                   0xF0000u
+#define SDHC_SYSCTL_DTOCV_SHIFT                  16
+#define SDHC_SYSCTL_DTOCV_WIDTH                  4
+#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK                    0x1000000u
+#define SDHC_SYSCTL_RSTA_SHIFT                   24
+#define SDHC_SYSCTL_RSTA_WIDTH                   1
+#define SDHC_SYSCTL_RSTA(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTA_SHIFT))&SDHC_SYSCTL_RSTA_MASK)
+#define SDHC_SYSCTL_RSTC_MASK                    0x2000000u
+#define SDHC_SYSCTL_RSTC_SHIFT                   25
+#define SDHC_SYSCTL_RSTC_WIDTH                   1
+#define SDHC_SYSCTL_RSTC(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTC_SHIFT))&SDHC_SYSCTL_RSTC_MASK)
+#define SDHC_SYSCTL_RSTD_MASK                    0x4000000u
+#define SDHC_SYSCTL_RSTD_SHIFT                   26
+#define SDHC_SYSCTL_RSTD_WIDTH                   1
+#define SDHC_SYSCTL_RSTD(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTD_SHIFT))&SDHC_SYSCTL_RSTD_MASK)
+#define SDHC_SYSCTL_INITA_MASK                   0x8000000u
+#define SDHC_SYSCTL_INITA_SHIFT                  27
+#define SDHC_SYSCTL_INITA_WIDTH                  1
+#define SDHC_SYSCTL_INITA(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_INITA_SHIFT))&SDHC_SYSCTL_INITA_MASK)
+/* IRQSTAT Bit Fields */
+#define SDHC_IRQSTAT_CC_MASK                     0x1u
+#define SDHC_IRQSTAT_CC_SHIFT                    0
+#define SDHC_IRQSTAT_CC_WIDTH                    1
+#define SDHC_IRQSTAT_CC(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CC_SHIFT))&SDHC_IRQSTAT_CC_MASK)
+#define SDHC_IRQSTAT_TC_MASK                     0x2u
+#define SDHC_IRQSTAT_TC_SHIFT                    1
+#define SDHC_IRQSTAT_TC_WIDTH                    1
+#define SDHC_IRQSTAT_TC(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_TC_SHIFT))&SDHC_IRQSTAT_TC_MASK)
+#define SDHC_IRQSTAT_BGE_MASK                    0x4u
+#define SDHC_IRQSTAT_BGE_SHIFT                   2
+#define SDHC_IRQSTAT_BGE_WIDTH                   1
+#define SDHC_IRQSTAT_BGE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BGE_SHIFT))&SDHC_IRQSTAT_BGE_MASK)
+#define SDHC_IRQSTAT_DINT_MASK                   0x8u
+#define SDHC_IRQSTAT_DINT_SHIFT                  3
+#define SDHC_IRQSTAT_DINT_WIDTH                  1
+#define SDHC_IRQSTAT_DINT(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DINT_SHIFT))&SDHC_IRQSTAT_DINT_MASK)
+#define SDHC_IRQSTAT_BWR_MASK                    0x10u
+#define SDHC_IRQSTAT_BWR_SHIFT                   4
+#define SDHC_IRQSTAT_BWR_WIDTH                   1
+#define SDHC_IRQSTAT_BWR(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BWR_SHIFT))&SDHC_IRQSTAT_BWR_MASK)
+#define SDHC_IRQSTAT_BRR_MASK                    0x20u
+#define SDHC_IRQSTAT_BRR_SHIFT                   5
+#define SDHC_IRQSTAT_BRR_WIDTH                   1
+#define SDHC_IRQSTAT_BRR(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BRR_SHIFT))&SDHC_IRQSTAT_BRR_MASK)
+#define SDHC_IRQSTAT_CINS_MASK                   0x40u
+#define SDHC_IRQSTAT_CINS_SHIFT                  6
+#define SDHC_IRQSTAT_CINS_WIDTH                  1
+#define SDHC_IRQSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINS_SHIFT))&SDHC_IRQSTAT_CINS_MASK)
+#define SDHC_IRQSTAT_CRM_MASK                    0x80u
+#define SDHC_IRQSTAT_CRM_SHIFT                   7
+#define SDHC_IRQSTAT_CRM_WIDTH                   1
+#define SDHC_IRQSTAT_CRM(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CRM_SHIFT))&SDHC_IRQSTAT_CRM_MASK)
+#define SDHC_IRQSTAT_CINT_MASK                   0x100u
+#define SDHC_IRQSTAT_CINT_SHIFT                  8
+#define SDHC_IRQSTAT_CINT_WIDTH                  1
+#define SDHC_IRQSTAT_CINT(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINT_SHIFT))&SDHC_IRQSTAT_CINT_MASK)
+#define SDHC_IRQSTAT_CTOE_MASK                   0x10000u
+#define SDHC_IRQSTAT_CTOE_SHIFT                  16
+#define SDHC_IRQSTAT_CTOE_WIDTH                  1
+#define SDHC_IRQSTAT_CTOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CTOE_SHIFT))&SDHC_IRQSTAT_CTOE_MASK)
+#define SDHC_IRQSTAT_CCE_MASK                    0x20000u
+#define SDHC_IRQSTAT_CCE_SHIFT                   17
+#define SDHC_IRQSTAT_CCE_WIDTH                   1
+#define SDHC_IRQSTAT_CCE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CCE_SHIFT))&SDHC_IRQSTAT_CCE_MASK)
+#define SDHC_IRQSTAT_CEBE_MASK                   0x40000u
+#define SDHC_IRQSTAT_CEBE_SHIFT                  18
+#define SDHC_IRQSTAT_CEBE_WIDTH                  1
+#define SDHC_IRQSTAT_CEBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CEBE_SHIFT))&SDHC_IRQSTAT_CEBE_MASK)
+#define SDHC_IRQSTAT_CIE_MASK                    0x80000u
+#define SDHC_IRQSTAT_CIE_SHIFT                   19
+#define SDHC_IRQSTAT_CIE_WIDTH                   1
+#define SDHC_IRQSTAT_CIE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CIE_SHIFT))&SDHC_IRQSTAT_CIE_MASK)
+#define SDHC_IRQSTAT_DTOE_MASK                   0x100000u
+#define SDHC_IRQSTAT_DTOE_SHIFT                  20
+#define SDHC_IRQSTAT_DTOE_WIDTH                  1
+#define SDHC_IRQSTAT_DTOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DTOE_SHIFT))&SDHC_IRQSTAT_DTOE_MASK)
+#define SDHC_IRQSTAT_DCE_MASK                    0x200000u
+#define SDHC_IRQSTAT_DCE_SHIFT                   21
+#define SDHC_IRQSTAT_DCE_WIDTH                   1
+#define SDHC_IRQSTAT_DCE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DCE_SHIFT))&SDHC_IRQSTAT_DCE_MASK)
+#define SDHC_IRQSTAT_DEBE_MASK                   0x400000u
+#define SDHC_IRQSTAT_DEBE_SHIFT                  22
+#define SDHC_IRQSTAT_DEBE_WIDTH                  1
+#define SDHC_IRQSTAT_DEBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DEBE_SHIFT))&SDHC_IRQSTAT_DEBE_MASK)
+#define SDHC_IRQSTAT_AC12E_MASK                  0x1000000u
+#define SDHC_IRQSTAT_AC12E_SHIFT                 24
+#define SDHC_IRQSTAT_AC12E_WIDTH                 1
+#define SDHC_IRQSTAT_AC12E(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_AC12E_SHIFT))&SDHC_IRQSTAT_AC12E_MASK)
+#define SDHC_IRQSTAT_DMAE_MASK                   0x10000000u
+#define SDHC_IRQSTAT_DMAE_SHIFT                  28
+#define SDHC_IRQSTAT_DMAE_WIDTH                  1
+#define SDHC_IRQSTAT_DMAE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DMAE_SHIFT))&SDHC_IRQSTAT_DMAE_MASK)
+/* IRQSTATEN Bit Fields */
+#define SDHC_IRQSTATEN_CCSEN_MASK                0x1u
+#define SDHC_IRQSTATEN_CCSEN_SHIFT               0
+#define SDHC_IRQSTATEN_CCSEN_WIDTH               1
+#define SDHC_IRQSTATEN_CCSEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCSEN_SHIFT))&SDHC_IRQSTATEN_CCSEN_MASK)
+#define SDHC_IRQSTATEN_TCSEN_MASK                0x2u
+#define SDHC_IRQSTATEN_TCSEN_SHIFT               1
+#define SDHC_IRQSTATEN_TCSEN_WIDTH               1
+#define SDHC_IRQSTATEN_TCSEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_TCSEN_SHIFT))&SDHC_IRQSTATEN_TCSEN_MASK)
+#define SDHC_IRQSTATEN_BGESEN_MASK               0x4u
+#define SDHC_IRQSTATEN_BGESEN_SHIFT              2
+#define SDHC_IRQSTATEN_BGESEN_WIDTH              1
+#define SDHC_IRQSTATEN_BGESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BGESEN_SHIFT))&SDHC_IRQSTATEN_BGESEN_MASK)
+#define SDHC_IRQSTATEN_DINTSEN_MASK              0x8u
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT             3
+#define SDHC_IRQSTATEN_DINTSEN_WIDTH             1
+#define SDHC_IRQSTATEN_DINTSEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DINTSEN_SHIFT))&SDHC_IRQSTATEN_DINTSEN_MASK)
+#define SDHC_IRQSTATEN_BWRSEN_MASK               0x10u
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT              4
+#define SDHC_IRQSTATEN_BWRSEN_WIDTH              1
+#define SDHC_IRQSTATEN_BWRSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BWRSEN_SHIFT))&SDHC_IRQSTATEN_BWRSEN_MASK)
+#define SDHC_IRQSTATEN_BRRSEN_MASK               0x20u
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT              5
+#define SDHC_IRQSTATEN_BRRSEN_WIDTH              1
+#define SDHC_IRQSTATEN_BRRSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BRRSEN_SHIFT))&SDHC_IRQSTATEN_BRRSEN_MASK)
+#define SDHC_IRQSTATEN_CINSEN_MASK               0x40u
+#define SDHC_IRQSTATEN_CINSEN_SHIFT              6
+#define SDHC_IRQSTATEN_CINSEN_WIDTH              1
+#define SDHC_IRQSTATEN_CINSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINSEN_SHIFT))&SDHC_IRQSTATEN_CINSEN_MASK)
+#define SDHC_IRQSTATEN_CRMSEN_MASK               0x80u
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT              7
+#define SDHC_IRQSTATEN_CRMSEN_WIDTH              1
+#define SDHC_IRQSTATEN_CRMSEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CRMSEN_SHIFT))&SDHC_IRQSTATEN_CRMSEN_MASK)
+#define SDHC_IRQSTATEN_CINTSEN_MASK              0x100u
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT             8
+#define SDHC_IRQSTATEN_CINTSEN_WIDTH             1
+#define SDHC_IRQSTATEN_CINTSEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINTSEN_SHIFT))&SDHC_IRQSTATEN_CINTSEN_MASK)
+#define SDHC_IRQSTATEN_CTOESEN_MASK              0x10000u
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT             16
+#define SDHC_IRQSTATEN_CTOESEN_WIDTH             1
+#define SDHC_IRQSTATEN_CTOESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CTOESEN_SHIFT))&SDHC_IRQSTATEN_CTOESEN_MASK)
+#define SDHC_IRQSTATEN_CCESEN_MASK               0x20000u
+#define SDHC_IRQSTATEN_CCESEN_SHIFT              17
+#define SDHC_IRQSTATEN_CCESEN_WIDTH              1
+#define SDHC_IRQSTATEN_CCESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCESEN_SHIFT))&SDHC_IRQSTATEN_CCESEN_MASK)
+#define SDHC_IRQSTATEN_CEBESEN_MASK              0x40000u
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT             18
+#define SDHC_IRQSTATEN_CEBESEN_WIDTH             1
+#define SDHC_IRQSTATEN_CEBESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CEBESEN_SHIFT))&SDHC_IRQSTATEN_CEBESEN_MASK)
+#define SDHC_IRQSTATEN_CIESEN_MASK               0x80000u
+#define SDHC_IRQSTATEN_CIESEN_SHIFT              19
+#define SDHC_IRQSTATEN_CIESEN_WIDTH              1
+#define SDHC_IRQSTATEN_CIESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CIESEN_SHIFT))&SDHC_IRQSTATEN_CIESEN_MASK)
+#define SDHC_IRQSTATEN_DTOESEN_MASK              0x100000u
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT             20
+#define SDHC_IRQSTATEN_DTOESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DTOESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DTOESEN_SHIFT))&SDHC_IRQSTATEN_DTOESEN_MASK)
+#define SDHC_IRQSTATEN_DCESEN_MASK               0x200000u
+#define SDHC_IRQSTATEN_DCESEN_SHIFT              21
+#define SDHC_IRQSTATEN_DCESEN_WIDTH              1
+#define SDHC_IRQSTATEN_DCESEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DCESEN_SHIFT))&SDHC_IRQSTATEN_DCESEN_MASK)
+#define SDHC_IRQSTATEN_DEBESEN_MASK              0x400000u
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT             22
+#define SDHC_IRQSTATEN_DEBESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DEBESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DEBESEN_SHIFT))&SDHC_IRQSTATEN_DEBESEN_MASK)
+#define SDHC_IRQSTATEN_AC12ESEN_MASK             0x1000000u
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT            24
+#define SDHC_IRQSTATEN_AC12ESEN_WIDTH            1
+#define SDHC_IRQSTATEN_AC12ESEN(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_AC12ESEN_SHIFT))&SDHC_IRQSTATEN_AC12ESEN_MASK)
+#define SDHC_IRQSTATEN_DMAESEN_MASK              0x10000000u
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT             28
+#define SDHC_IRQSTATEN_DMAESEN_WIDTH             1
+#define SDHC_IRQSTATEN_DMAESEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DMAESEN_SHIFT))&SDHC_IRQSTATEN_DMAESEN_MASK)
+/* IRQSIGEN Bit Fields */
+#define SDHC_IRQSIGEN_CCIEN_MASK                 0x1u
+#define SDHC_IRQSIGEN_CCIEN_SHIFT                0
+#define SDHC_IRQSIGEN_CCIEN_WIDTH                1
+#define SDHC_IRQSIGEN_CCIEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCIEN_SHIFT))&SDHC_IRQSIGEN_CCIEN_MASK)
+#define SDHC_IRQSIGEN_TCIEN_MASK                 0x2u
+#define SDHC_IRQSIGEN_TCIEN_SHIFT                1
+#define SDHC_IRQSIGEN_TCIEN_WIDTH                1
+#define SDHC_IRQSIGEN_TCIEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_TCIEN_SHIFT))&SDHC_IRQSIGEN_TCIEN_MASK)
+#define SDHC_IRQSIGEN_BGEIEN_MASK                0x4u
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT               2
+#define SDHC_IRQSIGEN_BGEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BGEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BGEIEN_SHIFT))&SDHC_IRQSIGEN_BGEIEN_MASK)
+#define SDHC_IRQSIGEN_DINTIEN_MASK               0x8u
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT              3
+#define SDHC_IRQSIGEN_DINTIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DINTIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DINTIEN_SHIFT))&SDHC_IRQSIGEN_DINTIEN_MASK)
+#define SDHC_IRQSIGEN_BWRIEN_MASK                0x10u
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT               4
+#define SDHC_IRQSIGEN_BWRIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BWRIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BWRIEN_SHIFT))&SDHC_IRQSIGEN_BWRIEN_MASK)
+#define SDHC_IRQSIGEN_BRRIEN_MASK                0x20u
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT               5
+#define SDHC_IRQSIGEN_BRRIEN_WIDTH               1
+#define SDHC_IRQSIGEN_BRRIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BRRIEN_SHIFT))&SDHC_IRQSIGEN_BRRIEN_MASK)
+#define SDHC_IRQSIGEN_CINSIEN_MASK               0x40u
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT              6
+#define SDHC_IRQSIGEN_CINSIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CINSIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINSIEN_SHIFT))&SDHC_IRQSIGEN_CINSIEN_MASK)
+#define SDHC_IRQSIGEN_CRMIEN_MASK                0x80u
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT               7
+#define SDHC_IRQSIGEN_CRMIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CRMIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CRMIEN_SHIFT))&SDHC_IRQSIGEN_CRMIEN_MASK)
+#define SDHC_IRQSIGEN_CINTIEN_MASK               0x100u
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT              8
+#define SDHC_IRQSIGEN_CINTIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CINTIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINTIEN_SHIFT))&SDHC_IRQSIGEN_CINTIEN_MASK)
+#define SDHC_IRQSIGEN_CTOEIEN_MASK               0x10000u
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT              16
+#define SDHC_IRQSIGEN_CTOEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CTOEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CTOEIEN_SHIFT))&SDHC_IRQSIGEN_CTOEIEN_MASK)
+#define SDHC_IRQSIGEN_CCEIEN_MASK                0x20000u
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT               17
+#define SDHC_IRQSIGEN_CCEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CCEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCEIEN_SHIFT))&SDHC_IRQSIGEN_CCEIEN_MASK)
+#define SDHC_IRQSIGEN_CEBEIEN_MASK               0x40000u
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT              18
+#define SDHC_IRQSIGEN_CEBEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_CEBEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CEBEIEN_SHIFT))&SDHC_IRQSIGEN_CEBEIEN_MASK)
+#define SDHC_IRQSIGEN_CIEIEN_MASK                0x80000u
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT               19
+#define SDHC_IRQSIGEN_CIEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_CIEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CIEIEN_SHIFT))&SDHC_IRQSIGEN_CIEIEN_MASK)
+#define SDHC_IRQSIGEN_DTOEIEN_MASK               0x100000u
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT              20
+#define SDHC_IRQSIGEN_DTOEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DTOEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DTOEIEN_SHIFT))&SDHC_IRQSIGEN_DTOEIEN_MASK)
+#define SDHC_IRQSIGEN_DCEIEN_MASK                0x200000u
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT               21
+#define SDHC_IRQSIGEN_DCEIEN_WIDTH               1
+#define SDHC_IRQSIGEN_DCEIEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DCEIEN_SHIFT))&SDHC_IRQSIGEN_DCEIEN_MASK)
+#define SDHC_IRQSIGEN_DEBEIEN_MASK               0x400000u
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT              22
+#define SDHC_IRQSIGEN_DEBEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DEBEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DEBEIEN_SHIFT))&SDHC_IRQSIGEN_DEBEIEN_MASK)
+#define SDHC_IRQSIGEN_AC12EIEN_MASK              0x1000000u
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT             24
+#define SDHC_IRQSIGEN_AC12EIEN_WIDTH             1
+#define SDHC_IRQSIGEN_AC12EIEN(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_AC12EIEN_SHIFT))&SDHC_IRQSIGEN_AC12EIEN_MASK)
+#define SDHC_IRQSIGEN_DMAEIEN_MASK               0x10000000u
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT              28
+#define SDHC_IRQSIGEN_DMAEIEN_WIDTH              1
+#define SDHC_IRQSIGEN_DMAEIEN(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DMAEIEN_SHIFT))&SDHC_IRQSIGEN_DMAEIEN_MASK)
+/* AC12ERR Bit Fields */
+#define SDHC_AC12ERR_AC12NE_MASK                 0x1u
+#define SDHC_AC12ERR_AC12NE_SHIFT                0
+#define SDHC_AC12ERR_AC12NE_WIDTH                1
+#define SDHC_AC12ERR_AC12NE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12NE_SHIFT))&SDHC_AC12ERR_AC12NE_MASK)
+#define SDHC_AC12ERR_AC12TOE_MASK                0x2u
+#define SDHC_AC12ERR_AC12TOE_SHIFT               1
+#define SDHC_AC12ERR_AC12TOE_WIDTH               1
+#define SDHC_AC12ERR_AC12TOE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12TOE_SHIFT))&SDHC_AC12ERR_AC12TOE_MASK)
+#define SDHC_AC12ERR_AC12EBE_MASK                0x4u
+#define SDHC_AC12ERR_AC12EBE_SHIFT               2
+#define SDHC_AC12ERR_AC12EBE_WIDTH               1
+#define SDHC_AC12ERR_AC12EBE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12EBE_SHIFT))&SDHC_AC12ERR_AC12EBE_MASK)
+#define SDHC_AC12ERR_AC12CE_MASK                 0x8u
+#define SDHC_AC12ERR_AC12CE_SHIFT                3
+#define SDHC_AC12ERR_AC12CE_WIDTH                1
+#define SDHC_AC12ERR_AC12CE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12CE_SHIFT))&SDHC_AC12ERR_AC12CE_MASK)
+#define SDHC_AC12ERR_AC12IE_MASK                 0x10u
+#define SDHC_AC12ERR_AC12IE_SHIFT                4
+#define SDHC_AC12ERR_AC12IE_WIDTH                1
+#define SDHC_AC12ERR_AC12IE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12IE_SHIFT))&SDHC_AC12ERR_AC12IE_MASK)
+#define SDHC_AC12ERR_CNIBAC12E_MASK              0x80u
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT             7
+#define SDHC_AC12ERR_CNIBAC12E_WIDTH             1
+#define SDHC_AC12ERR_CNIBAC12E(x)                (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_CNIBAC12E_SHIFT))&SDHC_AC12ERR_CNIBAC12E_MASK)
+/* HTCAPBLT Bit Fields */
+#define SDHC_HTCAPBLT_MBL_MASK                   0x70000u
+#define SDHC_HTCAPBLT_MBL_SHIFT                  16
+#define SDHC_HTCAPBLT_MBL_WIDTH                  3
+#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK                 0x100000u
+#define SDHC_HTCAPBLT_ADMAS_SHIFT                20
+#define SDHC_HTCAPBLT_ADMAS_WIDTH                1
+#define SDHC_HTCAPBLT_ADMAS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_ADMAS_SHIFT))&SDHC_HTCAPBLT_ADMAS_MASK)
+#define SDHC_HTCAPBLT_HSS_MASK                   0x200000u
+#define SDHC_HTCAPBLT_HSS_SHIFT                  21
+#define SDHC_HTCAPBLT_HSS_WIDTH                  1
+#define SDHC_HTCAPBLT_HSS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_HSS_SHIFT))&SDHC_HTCAPBLT_HSS_MASK)
+#define SDHC_HTCAPBLT_DMAS_MASK                  0x400000u
+#define SDHC_HTCAPBLT_DMAS_SHIFT                 22
+#define SDHC_HTCAPBLT_DMAS_WIDTH                 1
+#define SDHC_HTCAPBLT_DMAS(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_DMAS_SHIFT))&SDHC_HTCAPBLT_DMAS_MASK)
+#define SDHC_HTCAPBLT_SRS_MASK                   0x800000u
+#define SDHC_HTCAPBLT_SRS_SHIFT                  23
+#define SDHC_HTCAPBLT_SRS_WIDTH                  1
+#define SDHC_HTCAPBLT_SRS(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_SRS_SHIFT))&SDHC_HTCAPBLT_SRS_MASK)
+#define SDHC_HTCAPBLT_VS33_MASK                  0x1000000u
+#define SDHC_HTCAPBLT_VS33_SHIFT                 24
+#define SDHC_HTCAPBLT_VS33_WIDTH                 1
+#define SDHC_HTCAPBLT_VS33(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_VS33_SHIFT))&SDHC_HTCAPBLT_VS33_MASK)
+/* WML Bit Fields */
+#define SDHC_WML_RDWML_MASK                      0xFFu
+#define SDHC_WML_RDWML_SHIFT                     0
+#define SDHC_WML_RDWML_WIDTH                     8
+#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK                      0xFF0000u
+#define SDHC_WML_WRWML_SHIFT                     16
+#define SDHC_WML_WRWML_WIDTH                     8
+#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
+/* FEVT Bit Fields */
+#define SDHC_FEVT_AC12NE_MASK                    0x1u
+#define SDHC_FEVT_AC12NE_SHIFT                   0
+#define SDHC_FEVT_AC12NE_WIDTH                   1
+#define SDHC_FEVT_AC12NE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12NE_SHIFT))&SDHC_FEVT_AC12NE_MASK)
+#define SDHC_FEVT_AC12TOE_MASK                   0x2u
+#define SDHC_FEVT_AC12TOE_SHIFT                  1
+#define SDHC_FEVT_AC12TOE_WIDTH                  1
+#define SDHC_FEVT_AC12TOE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12TOE_SHIFT))&SDHC_FEVT_AC12TOE_MASK)
+#define SDHC_FEVT_AC12CE_MASK                    0x4u
+#define SDHC_FEVT_AC12CE_SHIFT                   2
+#define SDHC_FEVT_AC12CE_WIDTH                   1
+#define SDHC_FEVT_AC12CE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12CE_SHIFT))&SDHC_FEVT_AC12CE_MASK)
+#define SDHC_FEVT_AC12EBE_MASK                   0x8u
+#define SDHC_FEVT_AC12EBE_SHIFT                  3
+#define SDHC_FEVT_AC12EBE_WIDTH                  1
+#define SDHC_FEVT_AC12EBE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12EBE_SHIFT))&SDHC_FEVT_AC12EBE_MASK)
+#define SDHC_FEVT_AC12IE_MASK                    0x10u
+#define SDHC_FEVT_AC12IE_SHIFT                   4
+#define SDHC_FEVT_AC12IE_WIDTH                   1
+#define SDHC_FEVT_AC12IE(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12IE_SHIFT))&SDHC_FEVT_AC12IE_MASK)
+#define SDHC_FEVT_CNIBAC12E_MASK                 0x80u
+#define SDHC_FEVT_CNIBAC12E_SHIFT                7
+#define SDHC_FEVT_CNIBAC12E_WIDTH                1
+#define SDHC_FEVT_CNIBAC12E(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CNIBAC12E_SHIFT))&SDHC_FEVT_CNIBAC12E_MASK)
+#define SDHC_FEVT_CTOE_MASK                      0x10000u
+#define SDHC_FEVT_CTOE_SHIFT                     16
+#define SDHC_FEVT_CTOE_WIDTH                     1
+#define SDHC_FEVT_CTOE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CTOE_SHIFT))&SDHC_FEVT_CTOE_MASK)
+#define SDHC_FEVT_CCE_MASK                       0x20000u
+#define SDHC_FEVT_CCE_SHIFT                      17
+#define SDHC_FEVT_CCE_WIDTH                      1
+#define SDHC_FEVT_CCE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CCE_SHIFT))&SDHC_FEVT_CCE_MASK)
+#define SDHC_FEVT_CEBE_MASK                      0x40000u
+#define SDHC_FEVT_CEBE_SHIFT                     18
+#define SDHC_FEVT_CEBE_WIDTH                     1
+#define SDHC_FEVT_CEBE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CEBE_SHIFT))&SDHC_FEVT_CEBE_MASK)
+#define SDHC_FEVT_CIE_MASK                       0x80000u
+#define SDHC_FEVT_CIE_SHIFT                      19
+#define SDHC_FEVT_CIE_WIDTH                      1
+#define SDHC_FEVT_CIE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CIE_SHIFT))&SDHC_FEVT_CIE_MASK)
+#define SDHC_FEVT_DTOE_MASK                      0x100000u
+#define SDHC_FEVT_DTOE_SHIFT                     20
+#define SDHC_FEVT_DTOE_WIDTH                     1
+#define SDHC_FEVT_DTOE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DTOE_SHIFT))&SDHC_FEVT_DTOE_MASK)
+#define SDHC_FEVT_DCE_MASK                       0x200000u
+#define SDHC_FEVT_DCE_SHIFT                      21
+#define SDHC_FEVT_DCE_WIDTH                      1
+#define SDHC_FEVT_DCE(x)                         (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DCE_SHIFT))&SDHC_FEVT_DCE_MASK)
+#define SDHC_FEVT_DEBE_MASK                      0x400000u
+#define SDHC_FEVT_DEBE_SHIFT                     22
+#define SDHC_FEVT_DEBE_WIDTH                     1
+#define SDHC_FEVT_DEBE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DEBE_SHIFT))&SDHC_FEVT_DEBE_MASK)
+#define SDHC_FEVT_AC12E_MASK                     0x1000000u
+#define SDHC_FEVT_AC12E_SHIFT                    24
+#define SDHC_FEVT_AC12E_WIDTH                    1
+#define SDHC_FEVT_AC12E(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12E_SHIFT))&SDHC_FEVT_AC12E_MASK)
+#define SDHC_FEVT_DMAE_MASK                      0x10000000u
+#define SDHC_FEVT_DMAE_SHIFT                     28
+#define SDHC_FEVT_DMAE_WIDTH                     1
+#define SDHC_FEVT_DMAE(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DMAE_SHIFT))&SDHC_FEVT_DMAE_MASK)
+#define SDHC_FEVT_CINT_MASK                      0x80000000u
+#define SDHC_FEVT_CINT_SHIFT                     31
+#define SDHC_FEVT_CINT_WIDTH                     1
+#define SDHC_FEVT_CINT(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CINT_SHIFT))&SDHC_FEVT_CINT_MASK)
+/* ADMAES Bit Fields */
+#define SDHC_ADMAES_ADMAES_MASK                  0x3u
+#define SDHC_ADMAES_ADMAES_SHIFT                 0
+#define SDHC_ADMAES_ADMAES_WIDTH                 2
+#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK                 0x4u
+#define SDHC_ADMAES_ADMALME_SHIFT                2
+#define SDHC_ADMAES_ADMALME_WIDTH                1
+#define SDHC_ADMAES_ADMALME(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMALME_SHIFT))&SDHC_ADMAES_ADMALME_MASK)
+#define SDHC_ADMAES_ADMADCE_MASK                 0x8u
+#define SDHC_ADMAES_ADMADCE_SHIFT                3
+#define SDHC_ADMAES_ADMADCE_WIDTH                1
+#define SDHC_ADMAES_ADMADCE(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMADCE_SHIFT))&SDHC_ADMAES_ADMADCE_MASK)
+/* ADSADDR Bit Fields */
+#define SDHC_ADSADDR_ADSADDR_MASK                0xFFFFFFFCu
+#define SDHC_ADSADDR_ADSADDR_SHIFT               2
+#define SDHC_ADSADDR_ADSADDR_WIDTH               30
+#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
+/* VENDOR Bit Fields */
+#define SDHC_VENDOR_EXTDMAEN_MASK                0x1u
+#define SDHC_VENDOR_EXTDMAEN_SHIFT               0
+#define SDHC_VENDOR_EXTDMAEN_WIDTH               1
+#define SDHC_VENDOR_EXTDMAEN(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXTDMAEN_SHIFT))&SDHC_VENDOR_EXTDMAEN_MASK)
+#define SDHC_VENDOR_EXBLKNU_MASK                 0x2u
+#define SDHC_VENDOR_EXBLKNU_SHIFT                1
+#define SDHC_VENDOR_EXBLKNU_WIDTH                1
+#define SDHC_VENDOR_EXBLKNU(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXBLKNU_SHIFT))&SDHC_VENDOR_EXBLKNU_MASK)
+#define SDHC_VENDOR_INTSTVAL_MASK                0xFF0000u
+#define SDHC_VENDOR_INTSTVAL_SHIFT               16
+#define SDHC_VENDOR_INTSTVAL_WIDTH               8
+#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
+/* MMCBOOT Bit Fields */
+#define SDHC_MMCBOOT_DTOCVACK_MASK               0xFu
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT              0
+#define SDHC_MMCBOOT_DTOCVACK_WIDTH              4
+#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK                0x10u
+#define SDHC_MMCBOOT_BOOTACK_SHIFT               4
+#define SDHC_MMCBOOT_BOOTACK_WIDTH               1
+#define SDHC_MMCBOOT_BOOTACK(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTACK_SHIFT))&SDHC_MMCBOOT_BOOTACK_MASK)
+#define SDHC_MMCBOOT_BOOTMODE_MASK               0x20u
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT              5
+#define SDHC_MMCBOOT_BOOTMODE_WIDTH              1
+#define SDHC_MMCBOOT_BOOTMODE(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTMODE_SHIFT))&SDHC_MMCBOOT_BOOTMODE_MASK)
+#define SDHC_MMCBOOT_BOOTEN_MASK                 0x40u
+#define SDHC_MMCBOOT_BOOTEN_SHIFT                6
+#define SDHC_MMCBOOT_BOOTEN_WIDTH                1
+#define SDHC_MMCBOOT_BOOTEN(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTEN_SHIFT))&SDHC_MMCBOOT_BOOTEN_MASK)
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK             0x80u
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            7
+#define SDHC_MMCBOOT_AUTOSABGEN_WIDTH            1
+#define SDHC_MMCBOOT_AUTOSABGEN(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_AUTOSABGEN_SHIFT))&SDHC_MMCBOOT_AUTOSABGEN_MASK)
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             0xFFFF0000u
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            16
+#define SDHC_MMCBOOT_BOOTBLKCNT_WIDTH            16
+#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+/* HOSTVER Bit Fields */
+#define SDHC_HOSTVER_SVN_MASK                    0xFFu
+#define SDHC_HOSTVER_SVN_SHIFT                   0
+#define SDHC_HOSTVER_SVN_WIDTH                   8
+#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK                    0xFF00u
+#define SDHC_HOSTVER_VVN_SHIFT                   8
+#define SDHC_HOSTVER_VVN_WIDTH                   8
+#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/** Peripheral SDHC base address */
+#define SDHC_BASE                                (0x400B1000u)
+/** Peripheral SDHC base pointer */
+#define SDHC                                     ((SDHC_Type *)SDHC_BASE)
+#define SDHC_BASE_PTR                            (SDHC)
+/** Array initializer of SDHC peripheral base addresses */
+#define SDHC_BASE_ADDRS                          { SDHC_BASE }
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASE_PTRS                           { SDHC }
+/** Interrupt vectors for the SDHC peripheral type */
+#define SDHC_IRQS                                { SDHC_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SDHC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
+ * @{
+ */
+
+
+/* SDHC - Register instance definitions */
+/* SDHC */
+#define SDHC_DSADDR                              SDHC_DSADDR_REG(SDHC)
+#define SDHC_BLKATTR                             SDHC_BLKATTR_REG(SDHC)
+#define SDHC_CMDARG                              SDHC_CMDARG_REG(SDHC)
+#define SDHC_XFERTYP                             SDHC_XFERTYP_REG(SDHC)
+#define SDHC_CMDRSP0                             SDHC_CMDRSP_REG(SDHC,0)
+#define SDHC_CMDRSP1                             SDHC_CMDRSP_REG(SDHC,1)
+#define SDHC_CMDRSP2                             SDHC_CMDRSP_REG(SDHC,2)
+#define SDHC_CMDRSP3                             SDHC_CMDRSP_REG(SDHC,3)
+#define SDHC_DATPORT                             SDHC_DATPORT_REG(SDHC)
+#define SDHC_PRSSTAT                             SDHC_PRSSTAT_REG(SDHC)
+#define SDHC_PROCTL                              SDHC_PROCTL_REG(SDHC)
+#define SDHC_SYSCTL                              SDHC_SYSCTL_REG(SDHC)
+#define SDHC_IRQSTAT                             SDHC_IRQSTAT_REG(SDHC)
+#define SDHC_IRQSTATEN                           SDHC_IRQSTATEN_REG(SDHC)
+#define SDHC_IRQSIGEN                            SDHC_IRQSIGEN_REG(SDHC)
+#define SDHC_AC12ERR                             SDHC_AC12ERR_REG(SDHC)
+#define SDHC_HTCAPBLT                            SDHC_HTCAPBLT_REG(SDHC)
+#define SDHC_WML                                 SDHC_WML_REG(SDHC)
+#define SDHC_FEVT                                SDHC_FEVT_REG(SDHC)
+#define SDHC_ADMAES                              SDHC_ADMAES_REG(SDHC)
+#define SDHC_ADSADDR                             SDHC_ADSADDR_REG(SDHC)
+#define SDHC_VENDOR                              SDHC_VENDOR_REG(SDHC)
+#define SDHC_MMCBOOT                             SDHC_MMCBOOT_REG(SDHC)
+#define SDHC_HOSTVER                             SDHC_HOSTVER_REG(SDHC)
+
+/* SDHC - Register array accessors */
+#define SDHC_CMDRSP(index)                       SDHC_CMDRSP_REG(SDHC,index)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
+       uint8_t RESERVED_0[4092];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+  __IO uint32_t SCGC1;                             /**< System Clock Gating Control Register 1, offset: 0x1028 */
+  __IO uint32_t SCGC2;                             /**< System Clock Gating Control Register 2, offset: 0x102C */
+  __IO uint32_t SCGC3;                             /**< System Clock Gating Control Register 3, offset: 0x1030 */
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+  __IO uint32_t CLKDIV2;                           /**< System Clock Divider Register 2, offset: 0x1048 */
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+  __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base)                      ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base)                   ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base)                      ((base)->SOPT2)
+#define SIM_SOPT4_REG(base)                      ((base)->SOPT4)
+#define SIM_SOPT5_REG(base)                      ((base)->SOPT5)
+#define SIM_SOPT7_REG(base)                      ((base)->SOPT7)
+#define SIM_SDID_REG(base)                       ((base)->SDID)
+#define SIM_SCGC1_REG(base)                      ((base)->SCGC1)
+#define SIM_SCGC2_REG(base)                      ((base)->SCGC2)
+#define SIM_SCGC3_REG(base)                      ((base)->SCGC3)
+#define SIM_SCGC4_REG(base)                      ((base)->SCGC4)
+#define SIM_SCGC5_REG(base)                      ((base)->SCGC5)
+#define SIM_SCGC6_REG(base)                      ((base)->SCGC6)
+#define SIM_SCGC7_REG(base)                      ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base)                    ((base)->CLKDIV1)
+#define SIM_CLKDIV2_REG(base)                    ((base)->CLKDIV2)
+#define SIM_FCFG1_REG(base)                      ((base)->FCFG1)
+#define SIM_FCFG2_REG(base)                      ((base)->FCFG2)
+#define SIM_UIDH_REG(base)                       ((base)->UIDH)
+#define SIM_UIDMH_REG(base)                      ((base)->UIDMH)
+#define SIM_UIDML_REG(base)                      ((base)->UIDML)
+#define SIM_UIDL_REG(base)                       ((base)->UIDL)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK                   0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT                  12
+#define SIM_SOPT1_RAMSIZE_WIDTH                  4
+#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT                18
+#define SIM_SOPT1_OSC32KSEL_WIDTH                2
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK                  0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT                 29
+#define SIM_SOPT1_USBVSTBY_WIDTH                 1
+#define SIM_SOPT1_USBVSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBVSTBY_SHIFT))&SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK                  0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT                 30
+#define SIM_SOPT1_USBSSTBY_WIDTH                 1
+#define SIM_SOPT1_USBSSTBY(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBSSTBY_SHIFT))&SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK                  0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT                 31
+#define SIM_SOPT1_USBREGEN_WIDTH                 1
+#define SIM_SOPT1_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBREGEN_SHIFT))&SIM_SOPT1_USBREGEN_MASK)
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK                   0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT                  24
+#define SIM_SOPT1CFG_URWE_WIDTH                  1
+#define SIM_SOPT1CFG_URWE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_URWE_SHIFT))&SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK                  0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT                 25
+#define SIM_SOPT1CFG_UVSWE_WIDTH                 1
+#define SIM_SOPT1CFG_UVSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_UVSWE_SHIFT))&SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK                  0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT                 26
+#define SIM_SOPT1CFG_USSWE_WIDTH                 1
+#define SIM_SOPT1CFG_USSWE(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_USSWE_SHIFT))&SIM_SOPT1CFG_USSWE_MASK)
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
+#define SIM_SOPT2_RTCCLKOUTSEL_WIDTH             1
+#define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                5
+#define SIM_SOPT2_CLKOUTSEL_WIDTH                3
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK                      0x300u
+#define SIM_SOPT2_FBSL_SHIFT                     8
+#define SIM_SOPT2_FBSL_WIDTH                     2
+#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK                   0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT                  11
+#define SIM_SOPT2_PTD7PAD_WIDTH                  1
+#define SIM_SOPT2_PTD7PAD(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PTD7PAD_SHIFT))&SIM_SOPT2_PTD7PAD_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK               0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT              12
+#define SIM_SOPT2_TRACECLKSEL_WIDTH              1
+#define SIM_SOPT2_TRACECLKSEL(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TRACECLKSEL_SHIFT))&SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK                 0x30000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                16
+#define SIM_SOPT2_PLLFLLSEL_WIDTH                2
+#define SIM_SOPT2_PLLFLLSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK                    0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT                   18
+#define SIM_SOPT2_USBSRC_WIDTH                   1
+#define SIM_SOPT2_USBSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_RMIISRC_MASK                   0x80000u
+#define SIM_SOPT2_RMIISRC_SHIFT                  19
+#define SIM_SOPT2_RMIISRC_WIDTH                  1
+#define SIM_SOPT2_RMIISRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RMIISRC_SHIFT))&SIM_SOPT2_RMIISRC_MASK)
+#define SIM_SOPT2_TIMESRC_MASK                   0x300000u
+#define SIM_SOPT2_TIMESRC_SHIFT                  20
+#define SIM_SOPT2_TIMESRC_WIDTH                  2
+#define SIM_SOPT2_TIMESRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK                   0x30000000u
+#define SIM_SOPT2_SDHCSRC_SHIFT                  28
+#define SIM_SOPT2_SDHCSRC_WIDTH                  2
+#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK                  0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT                 0
+#define SIM_SOPT4_FTM0FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT0_SHIFT))&SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK                  0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT                 1
+#define SIM_SOPT4_FTM0FLT1_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT1_SHIFT))&SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM0FLT2_MASK                  0x4u
+#define SIM_SOPT4_FTM0FLT2_SHIFT                 2
+#define SIM_SOPT4_FTM0FLT2_WIDTH                 1
+#define SIM_SOPT4_FTM0FLT2(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT2_SHIFT))&SIM_SOPT4_FTM0FLT2_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK                  0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT                 4
+#define SIM_SOPT4_FTM1FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM1FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1FLT0_SHIFT))&SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_MASK                  0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT                 8
+#define SIM_SOPT4_FTM2FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM2FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2FLT0_SHIFT))&SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM3FLT0_MASK                  0x1000u
+#define SIM_SOPT4_FTM3FLT0_SHIFT                 12
+#define SIM_SOPT4_FTM3FLT0_WIDTH                 1
+#define SIM_SOPT4_FTM3FLT0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3FLT0_SHIFT))&SIM_SOPT4_FTM3FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK                0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT               18
+#define SIM_SOPT4_FTM1CH0SRC_WIDTH               2
+#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK                0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT               20
+#define SIM_SOPT4_FTM2CH0SRC_WIDTH               2
+#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK                0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT               24
+#define SIM_SOPT4_FTM0CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0CLKSEL_SHIFT))&SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK                0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT               25
+#define SIM_SOPT4_FTM1CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CLKSEL_SHIFT))&SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_MASK                0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT               26
+#define SIM_SOPT4_FTM2CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CLKSEL_SHIFT))&SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM3CLKSEL_MASK                0x8000000u
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT               27
+#define SIM_SOPT4_FTM3CLKSEL_WIDTH               1
+#define SIM_SOPT4_FTM3CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3CLKSEL_SHIFT))&SIM_SOPT4_FTM3CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK               0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT              28
+#define SIM_SOPT4_FTM0TRG0SRC_WIDTH              1
+#define SIM_SOPT4_FTM0TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG0SRC_SHIFT))&SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_MASK               0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT              29
+#define SIM_SOPT4_FTM0TRG1SRC_WIDTH              1
+#define SIM_SOPT4_FTM0TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG1SRC_SHIFT))&SIM_SOPT4_FTM0TRG1SRC_MASK)
+#define SIM_SOPT4_FTM3TRG0SRC_MASK               0x40000000u
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT              30
+#define SIM_SOPT4_FTM3TRG0SRC_WIDTH              1
+#define SIM_SOPT4_FTM3TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG0SRC_SHIFT))&SIM_SOPT4_FTM3TRG0SRC_MASK)
+#define SIM_SOPT4_FTM3TRG1SRC_MASK               0x80000000u
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT              31
+#define SIM_SOPT4_FTM3TRG1SRC_WIDTH              1
+#define SIM_SOPT4_FTM3TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG1SRC_SHIFT))&SIM_SOPT4_FTM3TRG1SRC_MASK)
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK                0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT               0
+#define SIM_SOPT5_UART0TXSRC_WIDTH               2
+#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK                0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT               2
+#define SIM_SOPT5_UART0RXSRC_WIDTH               2
+#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK                0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT               4
+#define SIM_SOPT5_UART1TXSRC_WIDTH               2
+#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK                0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT               6
+#define SIM_SOPT5_UART1RXSRC_WIDTH               2
+#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
+#define SIM_SOPT7_ADC0TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
+#define SIM_SOPT7_ADC0PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
+#define SIM_SOPT7_ADC0ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_MASK                0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT               8
+#define SIM_SOPT7_ADC1TRGSEL_WIDTH               4
+#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK             0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            12
+#define SIM_SOPT7_ADC1PRETRGSEL_WIDTH            1
+#define SIM_SOPT7_ADC1PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1PRETRGSEL_SHIFT))&SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK              0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             15
+#define SIM_SOPT7_ADC1ALTTRGEN_WIDTH             1
+#define SIM_SOPT7_ADC1ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1ALTTRGEN_SHIFT))&SIM_SOPT7_ADC1ALTTRGEN_MASK)
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK                      0xFu
+#define SIM_SDID_PINID_SHIFT                     0
+#define SIM_SDID_PINID_WIDTH                     4
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK                      0x70u
+#define SIM_SDID_FAMID_SHIFT                     4
+#define SIM_SDID_FAMID_WIDTH                     3
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK                      0xF80u
+#define SIM_SDID_DIEID_SHIFT                     7
+#define SIM_SDID_DIEID_WIDTH                     5
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      0xF000u
+#define SIM_SDID_REVID_SHIFT                     12
+#define SIM_SDID_REVID_WIDTH                     4
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK                   0xF00000u
+#define SIM_SDID_SERIESID_SHIFT                  20
+#define SIM_SDID_SERIESID_WIDTH                  4
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT                  24
+#define SIM_SDID_SUBFAMID_WIDTH                  4
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK                   0xF0000000u
+#define SIM_SDID_FAMILYID_SHIFT                  28
+#define SIM_SDID_FAMILYID_WIDTH                  4
+#define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
+/* SCGC1 Bit Fields */
+#define SIM_SCGC1_I2C2_MASK                      0x40u
+#define SIM_SCGC1_I2C2_SHIFT                     6
+#define SIM_SCGC1_I2C2_WIDTH                     1
+#define SIM_SCGC1_I2C2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_I2C2_SHIFT))&SIM_SCGC1_I2C2_MASK)
+#define SIM_SCGC1_UART4_MASK                     0x400u
+#define SIM_SCGC1_UART4_SHIFT                    10
+#define SIM_SCGC1_UART4_WIDTH                    1
+#define SIM_SCGC1_UART4(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART4_SHIFT))&SIM_SCGC1_UART4_MASK)
+#define SIM_SCGC1_UART5_MASK                     0x800u
+#define SIM_SCGC1_UART5_SHIFT                    11
+#define SIM_SCGC1_UART5_WIDTH                    1
+#define SIM_SCGC1_UART5(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART5_SHIFT))&SIM_SCGC1_UART5_MASK)
+/* SCGC2 Bit Fields */
+#define SIM_SCGC2_ENET_MASK                      0x1u
+#define SIM_SCGC2_ENET_SHIFT                     0
+#define SIM_SCGC2_ENET_WIDTH                     1
+#define SIM_SCGC2_ENET(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_ENET_SHIFT))&SIM_SCGC2_ENET_MASK)
+#define SIM_SCGC2_DAC0_MASK                      0x1000u
+#define SIM_SCGC2_DAC0_SHIFT                     12
+#define SIM_SCGC2_DAC0_WIDTH                     1
+#define SIM_SCGC2_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC0_SHIFT))&SIM_SCGC2_DAC0_MASK)
+#define SIM_SCGC2_DAC1_MASK                      0x2000u
+#define SIM_SCGC2_DAC1_SHIFT                     13
+#define SIM_SCGC2_DAC1_WIDTH                     1
+#define SIM_SCGC2_DAC1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC1_SHIFT))&SIM_SCGC2_DAC1_MASK)
+/* SCGC3 Bit Fields */
+#define SIM_SCGC3_RNGA_MASK                      0x1u
+#define SIM_SCGC3_RNGA_SHIFT                     0
+#define SIM_SCGC3_RNGA_WIDTH                     1
+#define SIM_SCGC3_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_RNGA_SHIFT))&SIM_SCGC3_RNGA_MASK)
+#define SIM_SCGC3_SPI2_MASK                      0x1000u
+#define SIM_SCGC3_SPI2_SHIFT                     12
+#define SIM_SCGC3_SPI2_WIDTH                     1
+#define SIM_SCGC3_SPI2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SPI2_SHIFT))&SIM_SCGC3_SPI2_MASK)
+#define SIM_SCGC3_SDHC_MASK                      0x20000u
+#define SIM_SCGC3_SDHC_SHIFT                     17
+#define SIM_SCGC3_SDHC_WIDTH                     1
+#define SIM_SCGC3_SDHC(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SDHC_SHIFT))&SIM_SCGC3_SDHC_MASK)
+#define SIM_SCGC3_FTM2_MASK                      0x1000000u
+#define SIM_SCGC3_FTM2_SHIFT                     24
+#define SIM_SCGC3_FTM2_WIDTH                     1
+#define SIM_SCGC3_FTM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM2_SHIFT))&SIM_SCGC3_FTM2_MASK)
+#define SIM_SCGC3_FTM3_MASK                      0x2000000u
+#define SIM_SCGC3_FTM3_SHIFT                     25
+#define SIM_SCGC3_FTM3_WIDTH                     1
+#define SIM_SCGC3_FTM3(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM3_SHIFT))&SIM_SCGC3_FTM3_MASK)
+#define SIM_SCGC3_ADC1_MASK                      0x8000000u
+#define SIM_SCGC3_ADC1_SHIFT                     27
+#define SIM_SCGC3_ADC1_WIDTH                     1
+#define SIM_SCGC3_ADC1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_ADC1_SHIFT))&SIM_SCGC3_ADC1_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK                       0x2u
+#define SIM_SCGC4_EWM_SHIFT                      1
+#define SIM_SCGC4_EWM_WIDTH                      1
+#define SIM_SCGC4_EWM(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_EWM_SHIFT))&SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_CMT_MASK                       0x4u
+#define SIM_SCGC4_CMT_SHIFT                      2
+#define SIM_SCGC4_CMT_WIDTH                      1
+#define SIM_SCGC4_CMT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMT_SHIFT))&SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_I2C0_MASK                      0x40u
+#define SIM_SCGC4_I2C0_SHIFT                     6
+#define SIM_SCGC4_I2C0_WIDTH                     1
+#define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C0_SHIFT))&SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK                      0x80u
+#define SIM_SCGC4_I2C1_SHIFT                     7
+#define SIM_SCGC4_I2C1_WIDTH                     1
+#define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C1_SHIFT))&SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK                     0x400u
+#define SIM_SCGC4_UART0_SHIFT                    10
+#define SIM_SCGC4_UART0_WIDTH                    1
+#define SIM_SCGC4_UART0(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART0_SHIFT))&SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK                     0x800u
+#define SIM_SCGC4_UART1_SHIFT                    11
+#define SIM_SCGC4_UART1_WIDTH                    1
+#define SIM_SCGC4_UART1(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART1_SHIFT))&SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK                     0x1000u
+#define SIM_SCGC4_UART2_SHIFT                    12
+#define SIM_SCGC4_UART2_WIDTH                    1
+#define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_UART3_MASK                     0x2000u
+#define SIM_SCGC4_UART3_SHIFT                    13
+#define SIM_SCGC4_UART3_WIDTH                    1
+#define SIM_SCGC4_UART3(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART3_SHIFT))&SIM_SCGC4_UART3_MASK)
+#define SIM_SCGC4_USBOTG_MASK                    0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT                   18
+#define SIM_SCGC4_USBOTG_WIDTH                   1
+#define SIM_SCGC4_USBOTG(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBOTG_SHIFT))&SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK                       0x80000u
+#define SIM_SCGC4_CMP_SHIFT                      19
+#define SIM_SCGC4_CMP_WIDTH                      1
+#define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK                      0x100000u
+#define SIM_SCGC4_VREF_SHIFT                     20
+#define SIM_SCGC4_VREF_WIDTH                     1
+#define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_VREF_SHIFT))&SIM_SCGC4_VREF_MASK)
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK                     0x1u
+#define SIM_SCGC5_LPTMR_SHIFT                    0
+#define SIM_SCGC5_LPTMR_WIDTH                    1
+#define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_PORTA_MASK                     0x200u
+#define SIM_SCGC5_PORTA_SHIFT                    9
+#define SIM_SCGC5_PORTA_WIDTH                    1
+#define SIM_SCGC5_PORTA(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK                     0x400u
+#define SIM_SCGC5_PORTB_SHIFT                    10
+#define SIM_SCGC5_PORTB_WIDTH                    1
+#define SIM_SCGC5_PORTB(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK                     0x800u
+#define SIM_SCGC5_PORTC_SHIFT                    11
+#define SIM_SCGC5_PORTC_WIDTH                    1
+#define SIM_SCGC5_PORTC(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK                     0x1000u
+#define SIM_SCGC5_PORTD_SHIFT                    12
+#define SIM_SCGC5_PORTD_WIDTH                    1
+#define SIM_SCGC5_PORTD(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK                     0x2000u
+#define SIM_SCGC5_PORTE_SHIFT                    13
+#define SIM_SCGC5_PORTE_WIDTH                    1
+#define SIM_SCGC5_PORTE(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK                       0x1u
+#define SIM_SCGC6_FTF_SHIFT                      0
+#define SIM_SCGC6_FTF_WIDTH                      1
+#define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK                    0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT                   1
+#define SIM_SCGC6_DMAMUX_WIDTH                   1
+#define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_FLEXCAN0_MASK                  0x10u
+#define SIM_SCGC6_FLEXCAN0_SHIFT                 4
+#define SIM_SCGC6_FLEXCAN0_WIDTH                 1
+#define SIM_SCGC6_FLEXCAN0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FLEXCAN0_SHIFT))&SIM_SCGC6_FLEXCAN0_MASK)
+#define SIM_SCGC6_RNGA_MASK                      0x200u
+#define SIM_SCGC6_RNGA_SHIFT                     9
+#define SIM_SCGC6_RNGA_WIDTH                     1
+#define SIM_SCGC6_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RNGA_SHIFT))&SIM_SCGC6_RNGA_MASK)
+#define SIM_SCGC6_SPI0_MASK                      0x1000u
+#define SIM_SCGC6_SPI0_SHIFT                     12
+#define SIM_SCGC6_SPI0_WIDTH                     1
+#define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI0_SHIFT))&SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK                      0x2000u
+#define SIM_SCGC6_SPI1_SHIFT                     13
+#define SIM_SCGC6_SPI1_WIDTH                     1
+#define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI1_SHIFT))&SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_I2S_MASK                       0x8000u
+#define SIM_SCGC6_I2S_SHIFT                      15
+#define SIM_SCGC6_I2S_WIDTH                      1
+#define SIM_SCGC6_I2S(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S_SHIFT))&SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK                       0x40000u
+#define SIM_SCGC6_CRC_SHIFT                      18
+#define SIM_SCGC6_CRC_WIDTH                      1
+#define SIM_SCGC6_CRC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_CRC_SHIFT))&SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_USBDCD_MASK                    0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT                   21
+#define SIM_SCGC6_USBDCD_WIDTH                   1
+#define SIM_SCGC6_USBDCD(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_USBDCD_SHIFT))&SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_PDB_MASK                       0x400000u
+#define SIM_SCGC6_PDB_SHIFT                      22
+#define SIM_SCGC6_PDB_WIDTH                      1
+#define SIM_SCGC6_PDB(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PDB_SHIFT))&SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK                       0x800000u
+#define SIM_SCGC6_PIT_SHIFT                      23
+#define SIM_SCGC6_PIT_WIDTH                      1
+#define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK                      0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT                     24
+#define SIM_SCGC6_FTM0_WIDTH                     1
+#define SIM_SCGC6_FTM0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM0_SHIFT))&SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK                      0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT                     25
+#define SIM_SCGC6_FTM1_WIDTH                     1
+#define SIM_SCGC6_FTM1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM1_SHIFT))&SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM2_MASK                      0x4000000u
+#define SIM_SCGC6_FTM2_SHIFT                     26
+#define SIM_SCGC6_FTM2_WIDTH                     1
+#define SIM_SCGC6_FTM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM2_SHIFT))&SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_ADC0_MASK                      0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT                     27
+#define SIM_SCGC6_ADC0_WIDTH                     1
+#define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK                       0x20000000u
+#define SIM_SCGC6_RTC_SHIFT                      29
+#define SIM_SCGC6_RTC_WIDTH                      1
+#define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK                      0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT                     31
+#define SIM_SCGC6_DAC0_WIDTH                     1
+#define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_FLEXBUS_MASK                   0x1u
+#define SIM_SCGC7_FLEXBUS_SHIFT                  0
+#define SIM_SCGC7_FLEXBUS_WIDTH                  1
+#define SIM_SCGC7_FLEXBUS(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_FLEXBUS_SHIFT))&SIM_SCGC7_FLEXBUS_MASK)
+#define SIM_SCGC7_DMA_MASK                       0x2u
+#define SIM_SCGC7_DMA_SHIFT                      1
+#define SIM_SCGC7_DMA_WIDTH                      1
+#define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_MPU_MASK                       0x4u
+#define SIM_SCGC7_MPU_SHIFT                      2
+#define SIM_SCGC7_MPU_WIDTH                      1
+#define SIM_SCGC7_MPU(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_MPU_SHIFT))&SIM_SCGC7_MPU_MASK)
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
+#define SIM_CLKDIV1_OUTDIV4_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK                 0xF00000u
+#define SIM_CLKDIV1_OUTDIV3_SHIFT                20
+#define SIM_CLKDIV1_OUTDIV3_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV3(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK                 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT                24
+#define SIM_CLKDIV1_OUTDIV2_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
+#define SIM_CLKDIV1_OUTDIV1_WIDTH                4
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK                 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT                0
+#define SIM_CLKDIV2_USBFRAC_WIDTH                1
+#define SIM_CLKDIV2_USBFRAC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBFRAC_SHIFT))&SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK                  0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT                 1
+#define SIM_CLKDIV2_USBDIV_WIDTH                 3
+#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK                  0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT                 0
+#define SIM_FCFG1_FLASHDIS_WIDTH                 1
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT                1
+#define SIM_FCFG1_FLASHDOZE_WIDTH                1
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_DEPART_MASK                    0xF00u
+#define SIM_FCFG1_DEPART_SHIFT                   8
+#define SIM_FCFG1_DEPART_WIDTH                   4
+#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK                    0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT                   16
+#define SIM_FCFG1_EESIZE_WIDTH                   4
+#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT                   24
+#define SIM_FCFG1_PFSIZE_WIDTH                   4
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK                   0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT                  28
+#define SIM_FCFG1_NVMSIZE_WIDTH                  4
+#define SIM_FCFG1_NVMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK                  0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT                 16
+#define SIM_FCFG2_MAXADDR1_WIDTH                 7
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK                     0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT                    23
+#define SIM_FCFG2_PFLSH_WIDTH                    1
+#define SIM_FCFG2_PFLSH(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_PFLSH_SHIFT))&SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK                  0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT                 24
+#define SIM_FCFG2_MAXADDR0_WIDTH                 7
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT                       0
+#define SIM_UIDH_UID_WIDTH                       32
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT                      0
+#define SIM_UIDMH_UID_WIDTH                      32
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT                      0
+#define SIM_UIDML_UID_WIDTH                      32
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT                       0
+#define SIM_UIDL_UID_WIDTH                       32
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR                             (SIM)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/* ----------------------------------------------------------------------------
+   -- SIM - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1                                SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG                             SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2                                SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4                                SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5                                SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7                                SIM_SOPT7_REG(SIM)
+#define SIM_SDID                                 SIM_SDID_REG(SIM)
+#define SIM_SCGC1                                SIM_SCGC1_REG(SIM)
+#define SIM_SCGC2                                SIM_SCGC2_REG(SIM)
+#define SIM_SCGC3                                SIM_SCGC3_REG(SIM)
+#define SIM_SCGC4                                SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5                                SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6                                SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7                                SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1                              SIM_CLKDIV1_REG(SIM)
+#define SIM_CLKDIV2                              SIM_CLKDIV2_REG(SIM)
+#define SIM_FCFG1                                SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2                                SIM_FCFG2_REG(SIM)
+#define SIM_UIDH                                 SIM_UIDH_REG(SIM)
+#define SIM_UIDMH                                SIM_UIDMH_REG(SIM)
+#define SIM_UIDML                                SIM_UIDML_REG(SIM)
+#define SIM_UIDL                                 SIM_UIDL_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t VLLSCTRL;                           /**< VLLS Control register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base)                     ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base)                     ((base)->PMCTRL)
+#define SMC_VLLSCTRL_REG(base)                   ((base)->VLLSCTRL)
+#define SMC_PMSTAT_REG(base)                     ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK                    0x2u
+#define SMC_PMPROT_AVLLS_SHIFT                   1
+#define SMC_PMPROT_AVLLS_WIDTH                   1
+#define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK                     0x8u
+#define SMC_PMPROT_ALLS_SHIFT                    3
+#define SMC_PMPROT_ALLS_WIDTH                    1
+#define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK                     0x20u
+#define SMC_PMPROT_AVLP_SHIFT                    5
+#define SMC_PMPROT_AVLP_WIDTH                    1
+#define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK                    0x7u
+#define SMC_PMCTRL_STOPM_SHIFT                   0
+#define SMC_PMCTRL_STOPM_WIDTH                   3
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK                    0x8u
+#define SMC_PMCTRL_STOPA_SHIFT                   3
+#define SMC_PMCTRL_STOPA_WIDTH                   1
+#define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK                     0x60u
+#define SMC_PMCTRL_RUNM_SHIFT                    5
+#define SMC_PMCTRL_RUNM_WIDTH                    2
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK                    0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT                   7
+#define SMC_PMCTRL_LPWUI_WIDTH                   1
+#define SMC_PMCTRL_LPWUI(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_LPWUI_SHIFT))&SMC_PMCTRL_LPWUI_MASK)
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK                  0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT                 0
+#define SMC_VLLSCTRL_VLLSM_WIDTH                 3
+#define SMC_VLLSCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK                  0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT                 5
+#define SMC_VLLSCTRL_PORPO_WIDTH                 1
+#define SMC_VLLSCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_PORPO_SHIFT))&SMC_VLLSCTRL_PORPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK                   0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT                  0
+#define SMC_PMSTAT_PMSTAT_WIDTH                  7
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR                             (SMC)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC }
+
+/* ----------------------------------------------------------------------------
+   -- SMC - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT                               SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL                               SMC_PMCTRL_REG(SMC)
+#define SMC_VLLSCTRL                             SMC_VLLSCTRL_REG(SMC)
+#define SMC_PMSTAT                               SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+    __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+  };
+       uint8_t RESERVED_1[24];
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
+  __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+  union {                                          /* offset: 0x34 */
+    __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+    __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+  };
+  __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
+  __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
+  __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
+  __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
+  __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
+       uint8_t RESERVED_2[48];
+  __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
+  __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
+  __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
+  __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_MCR_REG(base)                        ((base)->MCR)
+#define SPI_TCR_REG(base)                        ((base)->TCR)
+#define SPI_CTAR_REG(base,index2)                ((base)->CTAR[index2])
+#define SPI_CTAR_COUNT                           2
+#define SPI_CTAR_SLAVE_REG(base,index2)          ((base)->CTAR_SLAVE[index2])
+#define SPI_CTAR_SLAVE_COUNT                     1
+#define SPI_SR_REG(base)                         ((base)->SR)
+#define SPI_RSER_REG(base)                       ((base)->RSER)
+#define SPI_PUSHR_REG(base)                      ((base)->PUSHR)
+#define SPI_PUSHR_SLAVE_REG(base)                ((base)->PUSHR_SLAVE)
+#define SPI_POPR_REG(base)                       ((base)->POPR)
+#define SPI_TXFR0_REG(base)                      ((base)->TXFR0)
+#define SPI_TXFR1_REG(base)                      ((base)->TXFR1)
+#define SPI_TXFR2_REG(base)                      ((base)->TXFR2)
+#define SPI_TXFR3_REG(base)                      ((base)->TXFR3)
+#define SPI_RXFR0_REG(base)                      ((base)->RXFR0)
+#define SPI_RXFR1_REG(base)                      ((base)->RXFR1)
+#define SPI_RXFR2_REG(base)                      ((base)->RXFR2)
+#define SPI_RXFR3_REG(base)                      ((base)->RXFR3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK                        0x1u
+#define SPI_MCR_HALT_SHIFT                       0
+#define SPI_MCR_HALT_WIDTH                       1
+#define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_HALT_SHIFT))&SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK                     0x300u
+#define SPI_MCR_SMPL_PT_SHIFT                    8
+#define SPI_MCR_SMPL_PT_WIDTH                    2
+#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK                     0x400u
+#define SPI_MCR_CLR_RXF_SHIFT                    10
+#define SPI_MCR_CLR_RXF_WIDTH                    1
+#define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_RXF_SHIFT))&SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK                     0x800u
+#define SPI_MCR_CLR_TXF_SHIFT                    11
+#define SPI_MCR_CLR_TXF_WIDTH                    1
+#define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_TXF_SHIFT))&SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK                     0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT                    12
+#define SPI_MCR_DIS_RXF_WIDTH                    1
+#define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_RXF_SHIFT))&SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK                     0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT                    13
+#define SPI_MCR_DIS_TXF_WIDTH                    1
+#define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_TXF_SHIFT))&SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK                        0x4000u
+#define SPI_MCR_MDIS_SHIFT                       14
+#define SPI_MCR_MDIS_WIDTH                       1
+#define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MDIS_SHIFT))&SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK                        0x8000u
+#define SPI_MCR_DOZE_SHIFT                       15
+#define SPI_MCR_DOZE_WIDTH                       1
+#define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DOZE_SHIFT))&SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK                       0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT                      16
+#define SPI_MCR_PCSIS_WIDTH                      6
+#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK                        0x1000000u
+#define SPI_MCR_ROOE_SHIFT                       24
+#define SPI_MCR_ROOE_WIDTH                       1
+#define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_ROOE_SHIFT))&SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK                       0x2000000u
+#define SPI_MCR_PCSSE_SHIFT                      25
+#define SPI_MCR_PCSSE_WIDTH                      1
+#define SPI_MCR_PCSSE(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSSE_SHIFT))&SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK                        0x4000000u
+#define SPI_MCR_MTFE_SHIFT                       26
+#define SPI_MCR_MTFE_WIDTH                       1
+#define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MTFE_SHIFT))&SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK                         0x8000000u
+#define SPI_MCR_FRZ_SHIFT                        27
+#define SPI_MCR_FRZ_WIDTH                        1
+#define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_MCR_FRZ_SHIFT))&SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK                       0x30000000u
+#define SPI_MCR_DCONF_SHIFT                      28
+#define SPI_MCR_DCONF_WIDTH                      2
+#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK                   0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT                  30
+#define SPI_MCR_CONT_SCKE_WIDTH                  1
+#define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CONT_SCKE_SHIFT))&SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK                        0x80000000u
+#define SPI_MCR_MSTR_SHIFT                       31
+#define SPI_MCR_MSTR_WIDTH                       1
+#define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MSTR_SHIFT))&SPI_MCR_MSTR_MASK)
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK                    0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT                   16
+#define SPI_TCR_SPI_TCNT_WIDTH                   16
+#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK                         0xFu
+#define SPI_CTAR_BR_SHIFT                        0
+#define SPI_CTAR_BR_WIDTH                        4
+#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK                         0xF0u
+#define SPI_CTAR_DT_SHIFT                        4
+#define SPI_CTAR_DT_WIDTH                        4
+#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK                        0xF00u
+#define SPI_CTAR_ASC_SHIFT                       8
+#define SPI_CTAR_ASC_WIDTH                       4
+#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK                      0xF000u
+#define SPI_CTAR_CSSCK_SHIFT                     12
+#define SPI_CTAR_CSSCK_WIDTH                     4
+#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK                        0x30000u
+#define SPI_CTAR_PBR_SHIFT                       16
+#define SPI_CTAR_PBR_WIDTH                       2
+#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK                        0xC0000u
+#define SPI_CTAR_PDT_SHIFT                       18
+#define SPI_CTAR_PDT_WIDTH                       2
+#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK                       0x300000u
+#define SPI_CTAR_PASC_SHIFT                      20
+#define SPI_CTAR_PASC_WIDTH                      2
+#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK                     0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT                    22
+#define SPI_CTAR_PCSSCK_WIDTH                    2
+#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK                      0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT                     24
+#define SPI_CTAR_LSBFE_WIDTH                     1
+#define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_LSBFE_SHIFT))&SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK                       0x2000000u
+#define SPI_CTAR_CPHA_SHIFT                      25
+#define SPI_CTAR_CPHA_WIDTH                      1
+#define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPHA_SHIFT))&SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK                       0x4000000u
+#define SPI_CTAR_CPOL_SHIFT                      26
+#define SPI_CTAR_CPOL_WIDTH                      1
+#define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPOL_SHIFT))&SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK                       0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT                      27
+#define SPI_CTAR_FMSZ_WIDTH                      4
+#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK                        0x80000000u
+#define SPI_CTAR_DBR_SHIFT                       31
+#define SPI_CTAR_DBR_WIDTH                       1
+#define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DBR_SHIFT))&SPI_CTAR_DBR_MASK)
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK                 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT                25
+#define SPI_CTAR_SLAVE_CPHA_WIDTH                1
+#define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPHA_SHIFT))&SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK                 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT                26
+#define SPI_CTAR_SLAVE_CPOL_WIDTH                1
+#define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPOL_SHIFT))&SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK                 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT                27
+#define SPI_CTAR_SLAVE_FMSZ_WIDTH                5
+#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK                    0xFu
+#define SPI_SR_POPNXTPTR_SHIFT                   0
+#define SPI_SR_POPNXTPTR_WIDTH                   4
+#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK                        0xF0u
+#define SPI_SR_RXCTR_SHIFT                       4
+#define SPI_SR_RXCTR_WIDTH                       4
+#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK                     0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT                    8
+#define SPI_SR_TXNXTPTR_WIDTH                    4
+#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK                        0xF000u
+#define SPI_SR_TXCTR_SHIFT                       12
+#define SPI_SR_TXCTR_WIDTH                       4
+#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK                         0x20000u
+#define SPI_SR_RFDF_SHIFT                        17
+#define SPI_SR_RFDF_WIDTH                        1
+#define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFDF_SHIFT))&SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK                         0x80000u
+#define SPI_SR_RFOF_SHIFT                        19
+#define SPI_SR_RFOF_WIDTH                        1
+#define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFOF_SHIFT))&SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK                         0x2000000u
+#define SPI_SR_TFFF_SHIFT                        25
+#define SPI_SR_TFFF_WIDTH                        1
+#define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK                         0x8000000u
+#define SPI_SR_TFUF_SHIFT                        27
+#define SPI_SR_TFUF_WIDTH                        1
+#define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFUF_SHIFT))&SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK                         0x10000000u
+#define SPI_SR_EOQF_SHIFT                        28
+#define SPI_SR_EOQF_WIDTH                        1
+#define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_EOQF_SHIFT))&SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK                        0x40000000u
+#define SPI_SR_TXRXS_SHIFT                       30
+#define SPI_SR_TXRXS_WIDTH                       1
+#define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXRXS_SHIFT))&SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK                          0x80000000u
+#define SPI_SR_TCF_SHIFT                         31
+#define SPI_SR_TCF_WIDTH                         1
+#define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x))<<SPI_SR_TCF_SHIFT))&SPI_SR_TCF_MASK)
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK                  0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT                 16
+#define SPI_RSER_RFDF_DIRS_WIDTH                 1
+#define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_DIRS_SHIFT))&SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK                    0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT                   17
+#define SPI_RSER_RFDF_RE_WIDTH                   1
+#define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_RE_SHIFT))&SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK                    0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT                   19
+#define SPI_RSER_RFOF_RE_WIDTH                   1
+#define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFOF_RE_SHIFT))&SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK                  0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT                 24
+#define SPI_RSER_TFFF_DIRS_WIDTH                 1
+#define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_DIRS_SHIFT))&SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK                    0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT                   25
+#define SPI_RSER_TFFF_RE_WIDTH                   1
+#define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK                    0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT                   27
+#define SPI_RSER_TFUF_RE_WIDTH                   1
+#define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFUF_RE_SHIFT))&SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK                    0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT                   28
+#define SPI_RSER_EOQF_RE_WIDTH                   1
+#define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_EOQF_RE_SHIFT))&SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK                     0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT                    31
+#define SPI_RSER_TCF_RE_WIDTH                    1
+#define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TCF_RE_SHIFT))&SPI_RSER_TCF_RE_MASK)
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK                    0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT                   0
+#define SPI_PUSHR_TXDATA_WIDTH                   16
+#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK                       0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT                      16
+#define SPI_PUSHR_PCS_WIDTH                      6
+#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK                     0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT                    26
+#define SPI_PUSHR_CTCNT_WIDTH                    1
+#define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTCNT_SHIFT))&SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK                       0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT                      27
+#define SPI_PUSHR_EOQ_WIDTH                      1
+#define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_EOQ_SHIFT))&SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK                      0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT                     28
+#define SPI_PUSHR_CTAS_WIDTH                     3
+#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK                      0x80000000u
+#define SPI_PUSHR_CONT_SHIFT                     31
+#define SPI_PUSHR_CONT_WIDTH                     1
+#define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CONT_SHIFT))&SPI_PUSHR_CONT_MASK)
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK              0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             0
+#define SPI_PUSHR_SLAVE_TXDATA_WIDTH             32
+#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK                     0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT                    0
+#define SPI_POPR_RXDATA_WIDTH                    32
+#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT                   0
+#define SPI_TXFR0_TXDATA_WIDTH                   16
+#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR0_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT                   0
+#define SPI_TXFR1_TXDATA_WIDTH                   16
+#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR1_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT                   0
+#define SPI_TXFR2_TXDATA_WIDTH                   16
+#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR2_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT                   0
+#define SPI_TXFR3_TXDATA_WIDTH                   16
+#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR3_TXCMD_TXDATA_WIDTH             16
+#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT                   0
+#define SPI_RXFR0_RXDATA_WIDTH                   32
+#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT                   0
+#define SPI_RXFR1_RXDATA_WIDTH                   32
+#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT                   0
+#define SPI_RXFR2_RXDATA_WIDTH                   32
+#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT                   0
+#define SPI_RXFR3_RXDATA_WIDTH                   32
+#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR                            (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR                            (SPI1)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x400AC000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+#define SPI2_BASE_PTR                            (SPI2)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- SPI - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_MCR                                 SPI_MCR_REG(SPI0)
+#define SPI0_TCR                                 SPI_TCR_REG(SPI0)
+#define SPI0_CTAR0                               SPI_CTAR_REG(SPI0,0)
+#define SPI0_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI0,0)
+#define SPI0_CTAR1                               SPI_CTAR_REG(SPI0,1)
+#define SPI0_SR                                  SPI_SR_REG(SPI0)
+#define SPI0_RSER                                SPI_RSER_REG(SPI0)
+#define SPI0_PUSHR                               SPI_PUSHR_REG(SPI0)
+#define SPI0_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI0)
+#define SPI0_POPR                                SPI_POPR_REG(SPI0)
+#define SPI0_TXFR0                               SPI_TXFR0_REG(SPI0)
+#define SPI0_TXFR1                               SPI_TXFR1_REG(SPI0)
+#define SPI0_TXFR2                               SPI_TXFR2_REG(SPI0)
+#define SPI0_TXFR3                               SPI_TXFR3_REG(SPI0)
+#define SPI0_RXFR0                               SPI_RXFR0_REG(SPI0)
+#define SPI0_RXFR1                               SPI_RXFR1_REG(SPI0)
+#define SPI0_RXFR2                               SPI_RXFR2_REG(SPI0)
+#define SPI0_RXFR3                               SPI_RXFR3_REG(SPI0)
+/* SPI1 */
+#define SPI1_MCR                                 SPI_MCR_REG(SPI1)
+#define SPI1_TCR                                 SPI_TCR_REG(SPI1)
+#define SPI1_CTAR0                               SPI_CTAR_REG(SPI1,0)
+#define SPI1_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI1,0)
+#define SPI1_CTAR1                               SPI_CTAR_REG(SPI1,1)
+#define SPI1_SR                                  SPI_SR_REG(SPI1)
+#define SPI1_RSER                                SPI_RSER_REG(SPI1)
+#define SPI1_PUSHR                               SPI_PUSHR_REG(SPI1)
+#define SPI1_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI1)
+#define SPI1_POPR                                SPI_POPR_REG(SPI1)
+#define SPI1_TXFR0                               SPI_TXFR0_REG(SPI1)
+#define SPI1_TXFR1                               SPI_TXFR1_REG(SPI1)
+#define SPI1_TXFR2                               SPI_TXFR2_REG(SPI1)
+#define SPI1_TXFR3                               SPI_TXFR3_REG(SPI1)
+#define SPI1_RXFR0                               SPI_RXFR0_REG(SPI1)
+#define SPI1_RXFR1                               SPI_RXFR1_REG(SPI1)
+#define SPI1_RXFR2                               SPI_RXFR2_REG(SPI1)
+#define SPI1_RXFR3                               SPI_RXFR3_REG(SPI1)
+/* SPI2 */
+#define SPI2_MCR                                 SPI_MCR_REG(SPI2)
+#define SPI2_TCR                                 SPI_TCR_REG(SPI2)
+#define SPI2_CTAR0                               SPI_CTAR_REG(SPI2,0)
+#define SPI2_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI2,0)
+#define SPI2_CTAR1                               SPI_CTAR_REG(SPI2,1)
+#define SPI2_SR                                  SPI_SR_REG(SPI2)
+#define SPI2_RSER                                SPI_RSER_REG(SPI2)
+#define SPI2_PUSHR                               SPI_PUSHR_REG(SPI2)
+#define SPI2_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI2)
+#define SPI2_POPR                                SPI_POPR_REG(SPI2)
+#define SPI2_TXFR0                               SPI_TXFR0_REG(SPI2)
+#define SPI2_TXFR1                               SPI_TXFR1_REG(SPI2)
+#define SPI2_TXFR2                               SPI_TXFR2_REG(SPI2)
+#define SPI2_TXFR3                               SPI_TXFR3_REG(SPI2)
+#define SPI2_RXFR0                               SPI_RXFR0_REG(SPI2)
+#define SPI2_RXFR1                               SPI_RXFR1_REG(SPI2)
+#define SPI2_RXFR2                               SPI_RXFR2_REG(SPI2)
+#define SPI2_RXFR3                               SPI_RXFR3_REG(SPI2)
+
+/* SPI - Register array accessors */
+#define SPI0_CTAR(index2)                        SPI_CTAR_REG(SPI0,index2)
+#define SPI1_CTAR(index2)                        SPI_CTAR_REG(SPI1,index2)
+#define SPI2_CTAR(index2)                        SPI_CTAR_REG(SPI2,index2)
+#define SPI0_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI0,index2)
+#define SPI1_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI1,index2)
+#define SPI2_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI2,index2)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
+  __I  uint8_t ED;                                 /**< UART Extended Data Register, offset: 0xC */
+  __IO uint8_t MODEM;                              /**< UART Modem Register, offset: 0xD */
+  __IO uint8_t IR;                                 /**< UART Infrared Register, offset: 0xE */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t PFIFO;                              /**< UART FIFO Parameters, offset: 0x10 */
+  __IO uint8_t CFIFO;                              /**< UART FIFO Control Register, offset: 0x11 */
+  __IO uint8_t SFIFO;                              /**< UART FIFO Status Register, offset: 0x12 */
+  __IO uint8_t TWFIFO;                             /**< UART FIFO Transmit Watermark, offset: 0x13 */
+  __I  uint8_t TCFIFO;                             /**< UART FIFO Transmit Count, offset: 0x14 */
+  __IO uint8_t RWFIFO;                             /**< UART FIFO Receive Watermark, offset: 0x15 */
+  __I  uint8_t RCFIFO;                             /**< UART FIFO Receive Count, offset: 0x16 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
+  __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+  __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+  union {                                          /* offset: 0x1B */
+    __IO uint8_t WP7816T0;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+    __IO uint8_t WP7816T1;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+  };
+  __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
+  __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
+  __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
+  __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base)                       ((base)->BDH)
+#define UART_BDL_REG(base)                       ((base)->BDL)
+#define UART_C1_REG(base)                        ((base)->C1)
+#define UART_C2_REG(base)                        ((base)->C2)
+#define UART_S1_REG(base)                        ((base)->S1)
+#define UART_S2_REG(base)                        ((base)->S2)
+#define UART_C3_REG(base)                        ((base)->C3)
+#define UART_D_REG(base)                         ((base)->D)
+#define UART_MA1_REG(base)                       ((base)->MA1)
+#define UART_MA2_REG(base)                       ((base)->MA2)
+#define UART_C4_REG(base)                        ((base)->C4)
+#define UART_C5_REG(base)                        ((base)->C5)
+#define UART_ED_REG(base)                        ((base)->ED)
+#define UART_MODEM_REG(base)                     ((base)->MODEM)
+#define UART_IR_REG(base)                        ((base)->IR)
+#define UART_PFIFO_REG(base)                     ((base)->PFIFO)
+#define UART_CFIFO_REG(base)                     ((base)->CFIFO)
+#define UART_SFIFO_REG(base)                     ((base)->SFIFO)
+#define UART_TWFIFO_REG(base)                    ((base)->TWFIFO)
+#define UART_TCFIFO_REG(base)                    ((base)->TCFIFO)
+#define UART_RWFIFO_REG(base)                    ((base)->RWFIFO)
+#define UART_RCFIFO_REG(base)                    ((base)->RCFIFO)
+#define UART_C7816_REG(base)                     ((base)->C7816)
+#define UART_IE7816_REG(base)                    ((base)->IE7816)
+#define UART_IS7816_REG(base)                    ((base)->IS7816)
+#define UART_WP7816T0_REG(base)                  ((base)->WP7816T0)
+#define UART_WP7816T1_REG(base)                  ((base)->WP7816T1)
+#define UART_WN7816_REG(base)                    ((base)->WN7816)
+#define UART_WF7816_REG(base)                    ((base)->WF7816)
+#define UART_ET7816_REG(base)                    ((base)->ET7816)
+#define UART_TL7816_REG(base)                    ((base)->TL7816)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK                        0x1Fu
+#define UART_BDH_SBR_SHIFT                       0
+#define UART_BDH_SBR_WIDTH                       5
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK                       0x20u
+#define UART_BDH_SBNS_SHIFT                      5
+#define UART_BDH_SBNS_WIDTH                      1
+#define UART_BDH_SBNS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBNS_SHIFT))&UART_BDH_SBNS_MASK)
+#define UART_BDH_RXEDGIE_MASK                    0x40u
+#define UART_BDH_RXEDGIE_SHIFT                   6
+#define UART_BDH_RXEDGIE_WIDTH                   1
+#define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK                     0x80u
+#define UART_BDH_LBKDIE_SHIFT                    7
+#define UART_BDH_LBKDIE_WIDTH                    1
+#define UART_BDH_LBKDIE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_BDH_LBKDIE_SHIFT))&UART_BDH_LBKDIE_MASK)
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK                        0xFFu
+#define UART_BDL_SBR_SHIFT                       0
+#define UART_BDL_SBR_WIDTH                       8
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK                          0x1u
+#define UART_C1_PT_SHIFT                         0
+#define UART_C1_PT_WIDTH                         1
+#define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
+#define UART_C1_PE_MASK                          0x2u
+#define UART_C1_PE_SHIFT                         1
+#define UART_C1_PE_WIDTH                         1
+#define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK                         0x4u
+#define UART_C1_ILT_SHIFT                        2
+#define UART_C1_ILT_WIDTH                        1
+#define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK                        0x8u
+#define UART_C1_WAKE_SHIFT                       3
+#define UART_C1_WAKE_WIDTH                       1
+#define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK                           0x10u
+#define UART_C1_M_SHIFT                          4
+#define UART_C1_M_WIDTH                          1
+#define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK                        0x20u
+#define UART_C1_RSRC_SHIFT                       5
+#define UART_C1_RSRC_WIDTH                       1
+#define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK                    0x40u
+#define UART_C1_UARTSWAI_SHIFT                   6
+#define UART_C1_UARTSWAI_WIDTH                   1
+#define UART_C1_UARTSWAI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C1_UARTSWAI_SHIFT))&UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK                       0x80u
+#define UART_C1_LOOPS_SHIFT                      7
+#define UART_C1_LOOPS_WIDTH                      1
+#define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK                         0x1u
+#define UART_C2_SBK_SHIFT                        0
+#define UART_C2_SBK_WIDTH                        1
+#define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK                         0x2u
+#define UART_C2_RWU_SHIFT                        1
+#define UART_C2_RWU_WIDTH                        1
+#define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK                          0x4u
+#define UART_C2_RE_SHIFT                         2
+#define UART_C2_RE_WIDTH                         1
+#define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
+#define UART_C2_TE_MASK                          0x8u
+#define UART_C2_TE_SHIFT                         3
+#define UART_C2_TE_WIDTH                         1
+#define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK                        0x10u
+#define UART_C2_ILIE_SHIFT                       4
+#define UART_C2_ILIE_WIDTH                       1
+#define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK                         0x20u
+#define UART_C2_RIE_SHIFT                        5
+#define UART_C2_RIE_WIDTH                        1
+#define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK                        0x40u
+#define UART_C2_TCIE_SHIFT                       6
+#define UART_C2_TCIE_WIDTH                       1
+#define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK                         0x80u
+#define UART_C2_TIE_SHIFT                        7
+#define UART_C2_TIE_WIDTH                        1
+#define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK                          0x1u
+#define UART_S1_PF_SHIFT                         0
+#define UART_S1_PF_WIDTH                         1
+#define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
+#define UART_S1_FE_MASK                          0x2u
+#define UART_S1_FE_SHIFT                         1
+#define UART_S1_FE_WIDTH                         1
+#define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
+#define UART_S1_NF_MASK                          0x4u
+#define UART_S1_NF_SHIFT                         2
+#define UART_S1_NF_WIDTH                         1
+#define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
+#define UART_S1_OR_MASK                          0x8u
+#define UART_S1_OR_SHIFT                         3
+#define UART_S1_OR_WIDTH                         1
+#define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK                        0x10u
+#define UART_S1_IDLE_SHIFT                       4
+#define UART_S1_IDLE_WIDTH                       1
+#define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK                        0x20u
+#define UART_S1_RDRF_SHIFT                       5
+#define UART_S1_RDRF_WIDTH                       1
+#define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK                          0x40u
+#define UART_S1_TC_SHIFT                         6
+#define UART_S1_TC_WIDTH                         1
+#define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK                        0x80u
+#define UART_S1_TDRE_SHIFT                       7
+#define UART_S1_TDRE_WIDTH                       1
+#define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK                         0x1u
+#define UART_S2_RAF_SHIFT                        0
+#define UART_S2_RAF_WIDTH                        1
+#define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK                       0x2u
+#define UART_S2_LBKDE_SHIFT                      1
+#define UART_S2_LBKDE_WIDTH                      1
+#define UART_S2_LBKDE(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDE_SHIFT))&UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK                       0x4u
+#define UART_S2_BRK13_SHIFT                      2
+#define UART_S2_BRK13_WIDTH                      1
+#define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK                       0x8u
+#define UART_S2_RWUID_SHIFT                      3
+#define UART_S2_RWUID_WIDTH                      1
+#define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK                       0x10u
+#define UART_S2_RXINV_SHIFT                      4
+#define UART_S2_RXINV_WIDTH                      1
+#define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK                        0x20u
+#define UART_S2_MSBF_SHIFT                       5
+#define UART_S2_MSBF_WIDTH                       1
+#define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S2_MSBF_SHIFT))&UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK                     0x40u
+#define UART_S2_RXEDGIF_SHIFT                    6
+#define UART_S2_RXEDGIF_WIDTH                    1
+#define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK                      0x80u
+#define UART_S2_LBKDIF_SHIFT                     7
+#define UART_S2_LBKDIF_WIDTH                     1
+#define UART_S2_LBKDIF(x)                        (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDIF_SHIFT))&UART_S2_LBKDIF_MASK)
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK                        0x1u
+#define UART_C3_PEIE_SHIFT                       0
+#define UART_C3_PEIE_WIDTH                       1
+#define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK                        0x2u
+#define UART_C3_FEIE_SHIFT                       1
+#define UART_C3_FEIE_WIDTH                       1
+#define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK                        0x4u
+#define UART_C3_NEIE_SHIFT                       2
+#define UART_C3_NEIE_WIDTH                       1
+#define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK                        0x8u
+#define UART_C3_ORIE_SHIFT                       3
+#define UART_C3_ORIE_WIDTH                       1
+#define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK                       0x10u
+#define UART_C3_TXINV_SHIFT                      4
+#define UART_C3_TXINV_WIDTH                      1
+#define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK                       0x20u
+#define UART_C3_TXDIR_SHIFT                      5
+#define UART_C3_TXDIR_WIDTH                      1
+#define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK                          0x40u
+#define UART_C3_T8_SHIFT                         6
+#define UART_C3_T8_WIDTH                         1
+#define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
+#define UART_C3_R8_MASK                          0x80u
+#define UART_C3_R8_SHIFT                         7
+#define UART_C3_R8_WIDTH                         1
+#define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
+/* D Bit Fields */
+#define UART_D_RT_MASK                           0xFFu
+#define UART_D_RT_SHIFT                          0
+#define UART_D_RT_WIDTH                          8
+#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK                         0xFFu
+#define UART_MA1_MA_SHIFT                        0
+#define UART_MA1_MA_WIDTH                        8
+#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK                         0xFFu
+#define UART_MA2_MA_SHIFT                        0
+#define UART_MA2_MA_WIDTH                        8
+#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK                        0x1Fu
+#define UART_C4_BRFA_SHIFT                       0
+#define UART_C4_BRFA_WIDTH                       5
+#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK                         0x20u
+#define UART_C4_M10_SHIFT                        5
+#define UART_C4_M10_WIDTH                        1
+#define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C4_M10_SHIFT))&UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK                       0x40u
+#define UART_C4_MAEN2_SHIFT                      6
+#define UART_C4_MAEN2_WIDTH                      1
+#define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN2_SHIFT))&UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK                       0x80u
+#define UART_C4_MAEN1_SHIFT                      7
+#define UART_C4_MAEN1_WIDTH                      1
+#define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN1_SHIFT))&UART_C4_MAEN1_MASK)
+/* C5 Bit Fields */
+#define UART_C5_LBKDDMAS_MASK                    0x8u
+#define UART_C5_LBKDDMAS_SHIFT                   3
+#define UART_C5_LBKDDMAS_WIDTH                   1
+#define UART_C5_LBKDDMAS(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C5_LBKDDMAS_SHIFT))&UART_C5_LBKDDMAS_MASK)
+#define UART_C5_ILDMAS_MASK                      0x10u
+#define UART_C5_ILDMAS_SHIFT                     4
+#define UART_C5_ILDMAS_WIDTH                     1
+#define UART_C5_ILDMAS(x)                        (((uint8_t)(((uint8_t)(x))<<UART_C5_ILDMAS_SHIFT))&UART_C5_ILDMAS_MASK)
+#define UART_C5_RDMAS_MASK                       0x20u
+#define UART_C5_RDMAS_SHIFT                      5
+#define UART_C5_RDMAS_WIDTH                      1
+#define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_RDMAS_SHIFT))&UART_C5_RDMAS_MASK)
+#define UART_C5_TCDMAS_MASK                      0x40u
+#define UART_C5_TCDMAS_SHIFT                     6
+#define UART_C5_TCDMAS_WIDTH                     1
+#define UART_C5_TCDMAS(x)                        (((uint8_t)(((uint8_t)(x))<<UART_C5_TCDMAS_SHIFT))&UART_C5_TCDMAS_MASK)
+#define UART_C5_TDMAS_MASK                       0x80u
+#define UART_C5_TDMAS_SHIFT                      7
+#define UART_C5_TDMAS_WIDTH                      1
+#define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_TDMAS_SHIFT))&UART_C5_TDMAS_MASK)
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK                     0x40u
+#define UART_ED_PARITYE_SHIFT                    6
+#define UART_ED_PARITYE_WIDTH                    1
+#define UART_ED_PARITYE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_ED_PARITYE_SHIFT))&UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK                       0x80u
+#define UART_ED_NOISY_SHIFT                      7
+#define UART_ED_NOISY_WIDTH                      1
+#define UART_ED_NOISY(x)                         (((uint8_t)(((uint8_t)(x))<<UART_ED_NOISY_SHIFT))&UART_ED_NOISY_MASK)
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK                   0x1u
+#define UART_MODEM_TXCTSE_SHIFT                  0
+#define UART_MODEM_TXCTSE_WIDTH                  1
+#define UART_MODEM_TXCTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXCTSE_SHIFT))&UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK                   0x2u
+#define UART_MODEM_TXRTSE_SHIFT                  1
+#define UART_MODEM_TXRTSE_WIDTH                  1
+#define UART_MODEM_TXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSE_SHIFT))&UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK                 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT                2
+#define UART_MODEM_TXRTSPOL_WIDTH                1
+#define UART_MODEM_TXRTSPOL(x)                   (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSPOL_SHIFT))&UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK                   0x8u
+#define UART_MODEM_RXRTSE_SHIFT                  3
+#define UART_MODEM_RXRTSE_WIDTH                  1
+#define UART_MODEM_RXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_RXRTSE_SHIFT))&UART_MODEM_RXRTSE_MASK)
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK                         0x3u
+#define UART_IR_TNP_SHIFT                        0
+#define UART_IR_TNP_WIDTH                        2
+#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK                        0x4u
+#define UART_IR_IREN_SHIFT                       2
+#define UART_IR_IREN_WIDTH                       1
+#define UART_IR_IREN(x)                          (((uint8_t)(((uint8_t)(x))<<UART_IR_IREN_SHIFT))&UART_IR_IREN_MASK)
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK               0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT              0
+#define UART_PFIFO_RXFIFOSIZE_WIDTH              3
+#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK                     0x8u
+#define UART_PFIFO_RXFE_SHIFT                    3
+#define UART_PFIFO_RXFE_WIDTH                    1
+#define UART_PFIFO_RXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFE_SHIFT))&UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK               0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT              4
+#define UART_PFIFO_TXFIFOSIZE_WIDTH              3
+#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK                     0x80u
+#define UART_PFIFO_TXFE_SHIFT                    7
+#define UART_PFIFO_TXFE_WIDTH                    1
+#define UART_PFIFO_TXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFE_SHIFT))&UART_PFIFO_TXFE_MASK)
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK                    0x1u
+#define UART_CFIFO_RXUFE_SHIFT                   0
+#define UART_CFIFO_RXUFE_WIDTH                   1
+#define UART_CFIFO_RXUFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXUFE_SHIFT))&UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK                    0x2u
+#define UART_CFIFO_TXOFE_SHIFT                   1
+#define UART_CFIFO_TXOFE_WIDTH                   1
+#define UART_CFIFO_TXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXOFE_SHIFT))&UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXOFE_MASK                    0x4u
+#define UART_CFIFO_RXOFE_SHIFT                   2
+#define UART_CFIFO_RXOFE_WIDTH                   1
+#define UART_CFIFO_RXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXOFE_SHIFT))&UART_CFIFO_RXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK                  0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT                 6
+#define UART_CFIFO_RXFLUSH_WIDTH                 1
+#define UART_CFIFO_RXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXFLUSH_SHIFT))&UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK                  0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT                 7
+#define UART_CFIFO_TXFLUSH_WIDTH                 1
+#define UART_CFIFO_TXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXFLUSH_SHIFT))&UART_CFIFO_TXFLUSH_MASK)
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK                     0x1u
+#define UART_SFIFO_RXUF_SHIFT                    0
+#define UART_SFIFO_RXUF_WIDTH                    1
+#define UART_SFIFO_RXUF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXUF_SHIFT))&UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK                     0x2u
+#define UART_SFIFO_TXOF_SHIFT                    1
+#define UART_SFIFO_TXOF_WIDTH                    1
+#define UART_SFIFO_TXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXOF_SHIFT))&UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXOF_MASK                     0x4u
+#define UART_SFIFO_RXOF_SHIFT                    2
+#define UART_SFIFO_RXOF_WIDTH                    1
+#define UART_SFIFO_RXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXOF_SHIFT))&UART_SFIFO_RXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK                   0x40u
+#define UART_SFIFO_RXEMPT_SHIFT                  6
+#define UART_SFIFO_RXEMPT_WIDTH                  1
+#define UART_SFIFO_RXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXEMPT_SHIFT))&UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK                   0x80u
+#define UART_SFIFO_TXEMPT_SHIFT                  7
+#define UART_SFIFO_TXEMPT_WIDTH                  1
+#define UART_SFIFO_TXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXEMPT_SHIFT))&UART_SFIFO_TXEMPT_MASK)
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK                 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT                0
+#define UART_TWFIFO_TXWATER_WIDTH                8
+#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK                 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT                0
+#define UART_TCFIFO_TXCOUNT_WIDTH                8
+#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK                 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT                0
+#define UART_RWFIFO_RXWATER_WIDTH                8
+#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK                 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT                0
+#define UART_RCFIFO_RXCOUNT_WIDTH                8
+#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK                0x1u
+#define UART_C7816_ISO_7816E_SHIFT               0
+#define UART_C7816_ISO_7816E_WIDTH               1
+#define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x))<<UART_C7816_ISO_7816E_SHIFT))&UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK                    0x2u
+#define UART_C7816_TTYPE_SHIFT                   1
+#define UART_C7816_TTYPE_WIDTH                   1
+#define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_TTYPE_SHIFT))&UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK                     0x4u
+#define UART_C7816_INIT_SHIFT                    2
+#define UART_C7816_INIT_WIDTH                    1
+#define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_C7816_INIT_SHIFT))&UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK                    0x8u
+#define UART_C7816_ANACK_SHIFT                   3
+#define UART_C7816_ANACK_WIDTH                   1
+#define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ANACK_SHIFT))&UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK                    0x10u
+#define UART_C7816_ONACK_SHIFT                   4
+#define UART_C7816_ONACK_WIDTH                   1
+#define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ONACK_SHIFT))&UART_C7816_ONACK_MASK)
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK                    0x1u
+#define UART_IE7816_RXTE_SHIFT                   0
+#define UART_IE7816_RXTE_WIDTH                   1
+#define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_RXTE_SHIFT))&UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK                    0x2u
+#define UART_IE7816_TXTE_SHIFT                   1
+#define UART_IE7816_TXTE_WIDTH                   1
+#define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_TXTE_SHIFT))&UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK                    0x4u
+#define UART_IE7816_GTVE_SHIFT                   2
+#define UART_IE7816_GTVE_WIDTH                   1
+#define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_GTVE_SHIFT))&UART_IE7816_GTVE_MASK)
+#define UART_IE7816_INITDE_MASK                  0x10u
+#define UART_IE7816_INITDE_SHIFT                 4
+#define UART_IE7816_INITDE_WIDTH                 1
+#define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x))<<UART_IE7816_INITDE_SHIFT))&UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK                    0x20u
+#define UART_IE7816_BWTE_SHIFT                   5
+#define UART_IE7816_BWTE_WIDTH                   1
+#define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_BWTE_SHIFT))&UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK                    0x40u
+#define UART_IE7816_CWTE_SHIFT                   6
+#define UART_IE7816_CWTE_WIDTH                   1
+#define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_CWTE_SHIFT))&UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK                     0x80u
+#define UART_IE7816_WTE_SHIFT                    7
+#define UART_IE7816_WTE_WIDTH                    1
+#define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IE7816_WTE_SHIFT))&UART_IE7816_WTE_MASK)
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK                     0x1u
+#define UART_IS7816_RXT_SHIFT                    0
+#define UART_IS7816_RXT_WIDTH                    1
+#define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_RXT_SHIFT))&UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK                     0x2u
+#define UART_IS7816_TXT_SHIFT                    1
+#define UART_IS7816_TXT_WIDTH                    1
+#define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_TXT_SHIFT))&UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK                     0x4u
+#define UART_IS7816_GTV_SHIFT                    2
+#define UART_IS7816_GTV_WIDTH                    1
+#define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_GTV_SHIFT))&UART_IS7816_GTV_MASK)
+#define UART_IS7816_INITD_MASK                   0x10u
+#define UART_IS7816_INITD_SHIFT                  4
+#define UART_IS7816_INITD_WIDTH                  1
+#define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x))<<UART_IS7816_INITD_SHIFT))&UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK                     0x20u
+#define UART_IS7816_BWT_SHIFT                    5
+#define UART_IS7816_BWT_WIDTH                    1
+#define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_BWT_SHIFT))&UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK                     0x40u
+#define UART_IS7816_CWT_SHIFT                    6
+#define UART_IS7816_CWT_WIDTH                    1
+#define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_CWT_SHIFT))&UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK                      0x80u
+#define UART_IS7816_WT_SHIFT                     7
+#define UART_IS7816_WT_WIDTH                     1
+#define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x))<<UART_IS7816_WT_SHIFT))&UART_IS7816_WT_MASK)
+/* WP7816T0 Bit Fields */
+#define UART_WP7816T0_WI_MASK                    0xFFu
+#define UART_WP7816T0_WI_SHIFT                   0
+#define UART_WP7816T0_WI_WIDTH                   8
+#define UART_WP7816T0_WI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
+/* WP7816T1 Bit Fields */
+#define UART_WP7816T1_BWI_MASK                   0xFu
+#define UART_WP7816T1_BWI_SHIFT                  0
+#define UART_WP7816T1_BWI_WIDTH                  4
+#define UART_WP7816T1_BWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
+#define UART_WP7816T1_CWI_MASK                   0xF0u
+#define UART_WP7816T1_CWI_SHIFT                  4
+#define UART_WP7816T1_CWI_WIDTH                  4
+#define UART_WP7816T1_CWI(x)                     (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK                     0xFFu
+#define UART_WN7816_GTN_SHIFT                    0
+#define UART_WN7816_GTN_WIDTH                    8
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK                    0xFFu
+#define UART_WF7816_GTFD_SHIFT                   0
+#define UART_WF7816_GTFD_WIDTH                   8
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK             0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT            0
+#define UART_ET7816_RXTHRESHOLD_WIDTH            4
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK             0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT            4
+#define UART_ET7816_TXTHRESHOLD_WIDTH            4
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK                    0xFFu
+#define UART_TL7816_TLEN_SHIFT                   0
+#define UART_TL7816_TLEN_WIDTH                   8
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0                                    ((UART_Type *)UART0_BASE)
+#define UART0_BASE_PTR                           (UART0)
+/** Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1                                    ((UART_Type *)UART1_BASE)
+#define UART1_BASE_PTR                           (UART1)
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR                           (UART2)
+/** Peripheral UART3 base address */
+#define UART3_BASE                               (0x4006D000u)
+/** Peripheral UART3 base pointer */
+#define UART3                                    ((UART_Type *)UART3_BASE)
+#define UART3_BASE_PTR                           (UART3)
+/** Peripheral UART4 base address */
+#define UART4_BASE                               (0x400EA000u)
+/** Peripheral UART4 base pointer */
+#define UART4                                    ((UART_Type *)UART4_BASE)
+#define UART4_BASE_PTR                           (UART4)
+/** Peripheral UART5 base address */
+#define UART5_BASE                               (0x400EB000u)
+/** Peripheral UART5 base pointer */
+#define UART5                                    ((UART_Type *)UART5_BASE)
+#define UART5_BASE_PTR                           (UART5)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS                           { UART0, UART1, UART2, UART3, UART4, UART5 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS                          { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
+#define UART_ERR_IRQS                            { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
+#define UART_LON_IRQS                            { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- UART - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART0 */
+#define UART0_BDH                                UART_BDH_REG(UART0)
+#define UART0_BDL                                UART_BDL_REG(UART0)
+#define UART0_C1                                 UART_C1_REG(UART0)
+#define UART0_C2                                 UART_C2_REG(UART0)
+#define UART0_S1                                 UART_S1_REG(UART0)
+#define UART0_S2                                 UART_S2_REG(UART0)
+#define UART0_C3                                 UART_C3_REG(UART0)
+#define UART0_D                                  UART_D_REG(UART0)
+#define UART0_MA1                                UART_MA1_REG(UART0)
+#define UART0_MA2                                UART_MA2_REG(UART0)
+#define UART0_C4                                 UART_C4_REG(UART0)
+#define UART0_C5                                 UART_C5_REG(UART0)
+#define UART0_ED                                 UART_ED_REG(UART0)
+#define UART0_MODEM                              UART_MODEM_REG(UART0)
+#define UART0_IR                                 UART_IR_REG(UART0)
+#define UART0_PFIFO                              UART_PFIFO_REG(UART0)
+#define UART0_CFIFO                              UART_CFIFO_REG(UART0)
+#define UART0_SFIFO                              UART_SFIFO_REG(UART0)
+#define UART0_TWFIFO                             UART_TWFIFO_REG(UART0)
+#define UART0_TCFIFO                             UART_TCFIFO_REG(UART0)
+#define UART0_RWFIFO                             UART_RWFIFO_REG(UART0)
+#define UART0_RCFIFO                             UART_RCFIFO_REG(UART0)
+#define UART0_C7816                              UART_C7816_REG(UART0)
+#define UART0_IE7816                             UART_IE7816_REG(UART0)
+#define UART0_IS7816                             UART_IS7816_REG(UART0)
+#define UART0_WP7816T0                           UART_WP7816T0_REG(UART0)
+#define UART0_WP7816T1                           UART_WP7816T1_REG(UART0)
+#define UART0_WN7816                             UART_WN7816_REG(UART0)
+#define UART0_WF7816                             UART_WF7816_REG(UART0)
+#define UART0_ET7816                             UART_ET7816_REG(UART0)
+#define UART0_TL7816                             UART_TL7816_REG(UART0)
+/* UART1 */
+#define UART1_BDH                                UART_BDH_REG(UART1)
+#define UART1_BDL                                UART_BDL_REG(UART1)
+#define UART1_C1                                 UART_C1_REG(UART1)
+#define UART1_C2                                 UART_C2_REG(UART1)
+#define UART1_S1                                 UART_S1_REG(UART1)
+#define UART1_S2                                 UART_S2_REG(UART1)
+#define UART1_C3                                 UART_C3_REG(UART1)
+#define UART1_D                                  UART_D_REG(UART1)
+#define UART1_MA1                                UART_MA1_REG(UART1)
+#define UART1_MA2                                UART_MA2_REG(UART1)
+#define UART1_C4                                 UART_C4_REG(UART1)
+#define UART1_C5                                 UART_C5_REG(UART1)
+#define UART1_ED                                 UART_ED_REG(UART1)
+#define UART1_MODEM                              UART_MODEM_REG(UART1)
+#define UART1_IR                                 UART_IR_REG(UART1)
+#define UART1_PFIFO                              UART_PFIFO_REG(UART1)
+#define UART1_CFIFO                              UART_CFIFO_REG(UART1)
+#define UART1_SFIFO                              UART_SFIFO_REG(UART1)
+#define UART1_TWFIFO                             UART_TWFIFO_REG(UART1)
+#define UART1_TCFIFO                             UART_TCFIFO_REG(UART1)
+#define UART1_RWFIFO                             UART_RWFIFO_REG(UART1)
+#define UART1_RCFIFO                             UART_RCFIFO_REG(UART1)
+/* UART2 */
+#define UART2_BDH                                UART_BDH_REG(UART2)
+#define UART2_BDL                                UART_BDL_REG(UART2)
+#define UART2_C1                                 UART_C1_REG(UART2)
+#define UART2_C2                                 UART_C2_REG(UART2)
+#define UART2_S1                                 UART_S1_REG(UART2)
+#define UART2_S2                                 UART_S2_REG(UART2)
+#define UART2_C3                                 UART_C3_REG(UART2)
+#define UART2_D                                  UART_D_REG(UART2)
+#define UART2_MA1                                UART_MA1_REG(UART2)
+#define UART2_MA2                                UART_MA2_REG(UART2)
+#define UART2_C4                                 UART_C4_REG(UART2)
+#define UART2_C5                                 UART_C5_REG(UART2)
+#define UART2_ED                                 UART_ED_REG(UART2)
+#define UART2_MODEM                              UART_MODEM_REG(UART2)
+#define UART2_IR                                 UART_IR_REG(UART2)
+#define UART2_PFIFO                              UART_PFIFO_REG(UART2)
+#define UART2_CFIFO                              UART_CFIFO_REG(UART2)
+#define UART2_SFIFO                              UART_SFIFO_REG(UART2)
+#define UART2_TWFIFO                             UART_TWFIFO_REG(UART2)
+#define UART2_TCFIFO                             UART_TCFIFO_REG(UART2)
+#define UART2_RWFIFO                             UART_RWFIFO_REG(UART2)
+#define UART2_RCFIFO                             UART_RCFIFO_REG(UART2)
+/* UART3 */
+#define UART3_BDH                                UART_BDH_REG(UART3)
+#define UART3_BDL                                UART_BDL_REG(UART3)
+#define UART3_C1                                 UART_C1_REG(UART3)
+#define UART3_C2                                 UART_C2_REG(UART3)
+#define UART3_S1                                 UART_S1_REG(UART3)
+#define UART3_S2                                 UART_S2_REG(UART3)
+#define UART3_C3                                 UART_C3_REG(UART3)
+#define UART3_D                                  UART_D_REG(UART3)
+#define UART3_MA1                                UART_MA1_REG(UART3)
+#define UART3_MA2                                UART_MA2_REG(UART3)
+#define UART3_C4                                 UART_C4_REG(UART3)
+#define UART3_C5                                 UART_C5_REG(UART3)
+#define UART3_ED                                 UART_ED_REG(UART3)
+#define UART3_MODEM                              UART_MODEM_REG(UART3)
+#define UART3_IR                                 UART_IR_REG(UART3)
+#define UART3_PFIFO                              UART_PFIFO_REG(UART3)
+#define UART3_CFIFO                              UART_CFIFO_REG(UART3)
+#define UART3_SFIFO                              UART_SFIFO_REG(UART3)
+#define UART3_TWFIFO                             UART_TWFIFO_REG(UART3)
+#define UART3_TCFIFO                             UART_TCFIFO_REG(UART3)
+#define UART3_RWFIFO                             UART_RWFIFO_REG(UART3)
+#define UART3_RCFIFO                             UART_RCFIFO_REG(UART3)
+/* UART4 */
+#define UART4_BDH                                UART_BDH_REG(UART4)
+#define UART4_BDL                                UART_BDL_REG(UART4)
+#define UART4_C1                                 UART_C1_REG(UART4)
+#define UART4_C2                                 UART_C2_REG(UART4)
+#define UART4_S1                                 UART_S1_REG(UART4)
+#define UART4_S2                                 UART_S2_REG(UART4)
+#define UART4_C3                                 UART_C3_REG(UART4)
+#define UART4_D                                  UART_D_REG(UART4)
+#define UART4_MA1                                UART_MA1_REG(UART4)
+#define UART4_MA2                                UART_MA2_REG(UART4)
+#define UART4_C4                                 UART_C4_REG(UART4)
+#define UART4_C5                                 UART_C5_REG(UART4)
+#define UART4_ED                                 UART_ED_REG(UART4)
+#define UART4_MODEM                              UART_MODEM_REG(UART4)
+#define UART4_IR                                 UART_IR_REG(UART4)
+#define UART4_PFIFO                              UART_PFIFO_REG(UART4)
+#define UART4_CFIFO                              UART_CFIFO_REG(UART4)
+#define UART4_SFIFO                              UART_SFIFO_REG(UART4)
+#define UART4_TWFIFO                             UART_TWFIFO_REG(UART4)
+#define UART4_TCFIFO                             UART_TCFIFO_REG(UART4)
+#define UART4_RWFIFO                             UART_RWFIFO_REG(UART4)
+#define UART4_RCFIFO                             UART_RCFIFO_REG(UART4)
+/* UART5 */
+#define UART5_BDH                                UART_BDH_REG(UART5)
+#define UART5_BDL                                UART_BDL_REG(UART5)
+#define UART5_C1                                 UART_C1_REG(UART5)
+#define UART5_C2                                 UART_C2_REG(UART5)
+#define UART5_S1                                 UART_S1_REG(UART5)
+#define UART5_S2                                 UART_S2_REG(UART5)
+#define UART5_C3                                 UART_C3_REG(UART5)
+#define UART5_D                                  UART_D_REG(UART5)
+#define UART5_MA1                                UART_MA1_REG(UART5)
+#define UART5_MA2                                UART_MA2_REG(UART5)
+#define UART5_C4                                 UART_C4_REG(UART5)
+#define UART5_C5                                 UART_C5_REG(UART5)
+#define UART5_ED                                 UART_ED_REG(UART5)
+#define UART5_MODEM                              UART_MODEM_REG(UART5)
+#define UART5_IR                                 UART_IR_REG(UART5)
+#define UART5_PFIFO                              UART_PFIFO_REG(UART5)
+#define UART5_CFIFO                              UART_CFIFO_REG(UART5)
+#define UART5_SFIFO                              UART_SFIFO_REG(UART5)
+#define UART5_TWFIFO                             UART_TWFIFO_REG(UART5)
+#define UART5_TCFIFO                             UART_TCFIFO_REG(UART5)
+#define UART5_RWFIFO                             UART_RWFIFO_REG(UART5)
+#define UART5_RCFIFO                             UART_RCFIFO_REG(UART5)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[3];
+  __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t OTGICR;                             /**< OTG Interrupt Control register, offset: 0x14 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_7[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_11[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_16[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t SOFTHLD;                            /**< SOF Threshold register, offset: 0xAC */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_20[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_21[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_22[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_25[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
+       uint8_t RESERVED_26[43];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_27[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48M oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_28[23];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base)                      ((base)->PERID)
+#define USB_IDCOMP_REG(base)                     ((base)->IDCOMP)
+#define USB_REV_REG(base)                        ((base)->REV)
+#define USB_ADDINFO_REG(base)                    ((base)->ADDINFO)
+#define USB_OTGISTAT_REG(base)                   ((base)->OTGISTAT)
+#define USB_OTGICR_REG(base)                     ((base)->OTGICR)
+#define USB_OTGSTAT_REG(base)                    ((base)->OTGSTAT)
+#define USB_OTGCTL_REG(base)                     ((base)->OTGCTL)
+#define USB_ISTAT_REG(base)                      ((base)->ISTAT)
+#define USB_INTEN_REG(base)                      ((base)->INTEN)
+#define USB_ERRSTAT_REG(base)                    ((base)->ERRSTAT)
+#define USB_ERREN_REG(base)                      ((base)->ERREN)
+#define USB_STAT_REG(base)                       ((base)->STAT)
+#define USB_CTL_REG(base)                        ((base)->CTL)
+#define USB_ADDR_REG(base)                       ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base)                   ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base)                    ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base)                    ((base)->FRMNUMH)
+#define USB_TOKEN_REG(base)                      ((base)->TOKEN)
+#define USB_SOFTHLD_REG(base)                    ((base)->SOFTHLD)
+#define USB_BDTPAGE2_REG(base)                   ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base)                   ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index)                ((base)->ENDPOINT[index].ENDPT)
+#define USB_ENDPT_COUNT                          16
+#define USB_USBCTRL_REG(base)                    ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base)                    ((base)->OBSERVE)
+#define USB_CONTROL_REG(base)                    ((base)->CONTROL)
+#define USB_USBTRC0_REG(base)                    ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base)               ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base)           ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base)         ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base)     ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK                        0x3Fu
+#define USB_PERID_ID_SHIFT                       0
+#define USB_PERID_ID_WIDTH                       6
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK                      0x3Fu
+#define USB_IDCOMP_NID_SHIFT                     0
+#define USB_IDCOMP_NID_WIDTH                     6
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK                         0xFFu
+#define USB_REV_REV_SHIFT                        0
+#define USB_REV_REV_WIDTH                        8
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK                  0x1u
+#define USB_ADDINFO_IEHOST_SHIFT                 0
+#define USB_ADDINFO_IEHOST_WIDTH                 1
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
+#define USB_ADDINFO_IRQNUM_MASK                  0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT                 3
+#define USB_ADDINFO_IRQNUM_WIDTH                 5
+#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK               0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT              0
+#define USB_OTGISTAT_AVBUSCHG_WIDTH              1
+#define USB_OTGISTAT_AVBUSCHG(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_AVBUSCHG_SHIFT))&USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK             0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT            2
+#define USB_OTGISTAT_B_SESS_CHG_WIDTH            1
+#define USB_OTGISTAT_B_SESS_CHG(x)               (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_B_SESS_CHG_SHIFT))&USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK             0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT            3
+#define USB_OTGISTAT_SESSVLDCHG_WIDTH            1
+#define USB_OTGISTAT_SESSVLDCHG(x)               (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_SESSVLDCHG_SHIFT))&USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK         0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        5
+#define USB_OTGISTAT_LINE_STATE_CHG_WIDTH        1
+#define USB_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK                0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT               6
+#define USB_OTGISTAT_ONEMSEC_WIDTH               1
+#define USB_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK                  0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT                 7
+#define USB_OTGISTAT_IDCHG_WIDTH                 1
+#define USB_OTGISTAT_IDCHG(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_IDCHG_SHIFT))&USB_OTGISTAT_IDCHG_MASK)
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK                  0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT                 0
+#define USB_OTGICR_AVBUSEN_WIDTH                 1
+#define USB_OTGICR_AVBUSEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_AVBUSEN_SHIFT))&USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK                  0x4u
+#define USB_OTGICR_BSESSEN_SHIFT                 2
+#define USB_OTGICR_BSESSEN_WIDTH                 1
+#define USB_OTGICR_BSESSEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_BSESSEN_SHIFT))&USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK                0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT               3
+#define USB_OTGICR_SESSVLDEN_WIDTH               1
+#define USB_OTGICR_SESSVLDEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_SESSVLDEN_SHIFT))&USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK              0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT             5
+#define USB_OTGICR_LINESTATEEN_WIDTH             1
+#define USB_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK                0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT               6
+#define USB_OTGICR_ONEMSECEN_WIDTH               1
+#define USB_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK                     0x80u
+#define USB_OTGICR_IDEN_SHIFT                    7
+#define USB_OTGICR_IDEN_WIDTH                    1
+#define USB_OTGICR_IDEN(x)                       (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_IDEN_SHIFT))&USB_OTGICR_IDEN_MASK)
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK                0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT               0
+#define USB_OTGSTAT_AVBUSVLD_WIDTH               1
+#define USB_OTGSTAT_AVBUSVLD(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_AVBUSVLD_SHIFT))&USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK                0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT               2
+#define USB_OTGSTAT_BSESSEND_WIDTH               1
+#define USB_OTGSTAT_BSESSEND(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_BSESSEND_SHIFT))&USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK                0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT               3
+#define USB_OTGSTAT_SESS_VLD_WIDTH               1
+#define USB_OTGSTAT_SESS_VLD(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_SESS_VLD_SHIFT))&USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK         0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        5
+#define USB_OTGSTAT_LINESTATESTABLE_WIDTH        1
+#define USB_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK               0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT              6
+#define USB_OTGSTAT_ONEMSECEN_WIDTH              1
+#define USB_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK                      0x80u
+#define USB_OTGSTAT_ID_SHIFT                     7
+#define USB_OTGSTAT_ID_WIDTH                     1
+#define USB_OTGSTAT_ID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ID_SHIFT))&USB_OTGSTAT_ID_MASK)
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK                    0x4u
+#define USB_OTGCTL_OTGEN_SHIFT                   2
+#define USB_OTGCTL_OTGEN_WIDTH                   1
+#define USB_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK                    0x10u
+#define USB_OTGCTL_DMLOW_SHIFT                   4
+#define USB_OTGCTL_DMLOW_WIDTH                   1
+#define USB_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK                    0x20u
+#define USB_OTGCTL_DPLOW_SHIFT                   5
+#define USB_OTGCTL_DPLOW_WIDTH                   1
+#define USB_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK                   0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT                  7
+#define USB_OTGCTL_DPHIGH_WIDTH                  1
+#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK                    0x1u
+#define USB_ISTAT_USBRST_SHIFT                   0
+#define USB_ISTAT_USBRST_WIDTH                   1
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK                     0x2u
+#define USB_ISTAT_ERROR_SHIFT                    1
+#define USB_ISTAT_ERROR_WIDTH                    1
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK                    0x4u
+#define USB_ISTAT_SOFTOK_SHIFT                   2
+#define USB_ISTAT_SOFTOK_WIDTH                   1
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK                    0x8u
+#define USB_ISTAT_TOKDNE_SHIFT                   3
+#define USB_ISTAT_TOKDNE_WIDTH                   1
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK                     0x10u
+#define USB_ISTAT_SLEEP_SHIFT                    4
+#define USB_ISTAT_SLEEP_WIDTH                    1
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK                    0x20u
+#define USB_ISTAT_RESUME_SHIFT                   5
+#define USB_ISTAT_RESUME_WIDTH                   1
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK                    0x40u
+#define USB_ISTAT_ATTACH_SHIFT                   6
+#define USB_ISTAT_ATTACH_WIDTH                   1
+#define USB_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK                     0x80u
+#define USB_ISTAT_STALL_SHIFT                    7
+#define USB_ISTAT_STALL_WIDTH                    1
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK                  0x1u
+#define USB_INTEN_USBRSTEN_SHIFT                 0
+#define USB_INTEN_USBRSTEN_WIDTH                 1
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK                   0x2u
+#define USB_INTEN_ERROREN_SHIFT                  1
+#define USB_INTEN_ERROREN_WIDTH                  1
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK                  0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT                 2
+#define USB_INTEN_SOFTOKEN_WIDTH                 1
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK                  0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT                 3
+#define USB_INTEN_TOKDNEEN_WIDTH                 1
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK                   0x10u
+#define USB_INTEN_SLEEPEN_SHIFT                  4
+#define USB_INTEN_SLEEPEN_WIDTH                  1
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK                  0x20u
+#define USB_INTEN_RESUMEEN_SHIFT                 5
+#define USB_INTEN_RESUMEEN_WIDTH                 1
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK                  0x40u
+#define USB_INTEN_ATTACHEN_SHIFT                 6
+#define USB_INTEN_ATTACHEN_WIDTH                 1
+#define USB_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK                   0x80u
+#define USB_INTEN_STALLEN_SHIFT                  7
+#define USB_INTEN_STALLEN_WIDTH                  1
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK                  0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT                 0
+#define USB_ERRSTAT_PIDERR_WIDTH                 1
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK                 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT                1
+#define USB_ERRSTAT_CRC5EOF_WIDTH                1
+#define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK                   0x4u
+#define USB_ERRSTAT_CRC16_SHIFT                  2
+#define USB_ERRSTAT_CRC16_WIDTH                  1
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK                    0x8u
+#define USB_ERRSTAT_DFN8_SHIFT                   3
+#define USB_ERRSTAT_DFN8_WIDTH                   1
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK                  0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT                 4
+#define USB_ERRSTAT_BTOERR_WIDTH                 1
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK                  0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT                 5
+#define USB_ERRSTAT_DMAERR_WIDTH                 1
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK                  0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT                 7
+#define USB_ERRSTAT_BTSERR_WIDTH                 1
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK                  0x1u
+#define USB_ERREN_PIDERREN_SHIFT                 0
+#define USB_ERREN_PIDERREN_WIDTH                 1
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK                 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT                1
+#define USB_ERREN_CRC5EOFEN_WIDTH                1
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK                   0x4u
+#define USB_ERREN_CRC16EN_SHIFT                  2
+#define USB_ERREN_CRC16EN_WIDTH                  1
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK                    0x8u
+#define USB_ERREN_DFN8EN_SHIFT                   3
+#define USB_ERREN_DFN8EN_WIDTH                   1
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK                  0x10u
+#define USB_ERREN_BTOERREN_SHIFT                 4
+#define USB_ERREN_BTOERREN_WIDTH                 1
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK                  0x20u
+#define USB_ERREN_DMAERREN_SHIFT                 5
+#define USB_ERREN_DMAERREN_WIDTH                 1
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK                  0x80u
+#define USB_ERREN_BTSERREN_SHIFT                 7
+#define USB_ERREN_BTSERREN_WIDTH                 1
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK                        0x4u
+#define USB_STAT_ODD_SHIFT                       2
+#define USB_STAT_ODD_WIDTH                       1
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK                         0x8u
+#define USB_STAT_TX_SHIFT                        3
+#define USB_STAT_TX_WIDTH                        1
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK                       0xF0u
+#define USB_STAT_ENDP_SHIFT                      4
+#define USB_STAT_ENDP_WIDTH                      4
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK                  0x1u
+#define USB_CTL_USBENSOFEN_SHIFT                 0
+#define USB_CTL_USBENSOFEN_WIDTH                 1
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK                      0x2u
+#define USB_CTL_ODDRST_SHIFT                     1
+#define USB_CTL_ODDRST_WIDTH                     1
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK                      0x4u
+#define USB_CTL_RESUME_SHIFT                     2
+#define USB_CTL_RESUME_WIDTH                     1
+#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK                  0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT                 3
+#define USB_CTL_HOSTMODEEN_WIDTH                 1
+#define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK                       0x10u
+#define USB_CTL_RESET_SHIFT                      4
+#define USB_CTL_RESET_WIDTH                      1
+#define USB_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
+#define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH         1
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK                         0x40u
+#define USB_CTL_SE0_SHIFT                        6
+#define USB_CTL_SE0_WIDTH                        1
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK                      0x80u
+#define USB_CTL_JSTATE_SHIFT                     7
+#define USB_CTL_JSTATE_WIDTH                     1
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK                       0x7Fu
+#define USB_ADDR_ADDR_SHIFT                      0
+#define USB_ADDR_ADDR_WIDTH                      7
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK                       0x80u
+#define USB_ADDR_LSEN_SHIFT                      7
+#define USB_ADDR_LSEN_WIDTH                      1
+#define USB_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT                 1
+#define USB_BDTPAGE1_BDTBA_WIDTH                 7
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK                     0xFFu
+#define USB_FRMNUML_FRM_SHIFT                    0
+#define USB_FRMNUML_FRM_WIDTH                    8
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK                     0x7u
+#define USB_FRMNUMH_FRM_SHIFT                    0
+#define USB_FRMNUMH_FRM_WIDTH                    3
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK                0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT               0
+#define USB_TOKEN_TOKENENDPT_WIDTH               4
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT                 4
+#define USB_TOKEN_TOKENPID_WIDTH                 4
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK                     0xFFu
+#define USB_SOFTHLD_CNT_SHIFT                    0
+#define USB_SOFTHLD_CNT_WIDTH                    8
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT                 0
+#define USB_BDTPAGE2_BDTBA_WIDTH                 8
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT                 0
+#define USB_BDTPAGE3_BDTBA_WIDTH                 8
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK                    0x1u
+#define USB_ENDPT_EPHSHK_SHIFT                   0
+#define USB_ENDPT_EPHSHK_WIDTH                   1
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK                   0x2u
+#define USB_ENDPT_EPSTALL_SHIFT                  1
+#define USB_ENDPT_EPSTALL_WIDTH                  1
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK                    0x4u
+#define USB_ENDPT_EPTXEN_SHIFT                   2
+#define USB_ENDPT_EPTXEN_WIDTH                   1
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK                    0x8u
+#define USB_ENDPT_EPRXEN_SHIFT                   3
+#define USB_ENDPT_EPRXEN_WIDTH                   1
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK                  0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT                 4
+#define USB_ENDPT_EPCTLDIS_WIDTH                 1
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK                  0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT                 6
+#define USB_ENDPT_RETRYDIS_WIDTH                 1
+#define USB_ENDPT_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK                 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT                7
+#define USB_ENDPT_HOSTWOHUB_WIDTH                1
+#define USB_ENDPT_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK                     0x40u
+#define USB_USBCTRL_PDE_SHIFT                    6
+#define USB_USBCTRL_PDE_WIDTH                    1
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK                    0x80u
+#define USB_USBCTRL_SUSP_SHIFT                   7
+#define USB_USBCTRL_SUSP_WIDTH                   1
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK                    0x10u
+#define USB_OBSERVE_DMPD_SHIFT                   4
+#define USB_OBSERVE_DMPD_WIDTH                   1
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK                    0x40u
+#define USB_OBSERVE_DPPD_SHIFT                   6
+#define USB_OBSERVE_DPPD_WIDTH                   1
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK                    0x80u
+#define USB_OBSERVE_DPPU_SHIFT                   7
+#define USB_OBSERVE_DPPU_WIDTH                   1
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
+#define USB_CONTROL_DPPULLUPNONOTG_WIDTH         1
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
+#define USB_USBTRC0_USB_RESUME_INT_WIDTH         1
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK                0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT               1
+#define USB_USBTRC0_SYNC_DET_WIDTH               1
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   2
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH   1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))&USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK               0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT              5
+#define USB_USBTRC0_USBRESMEN_WIDTH              1
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK                0x80u
+#define USB_USBTRC0_USBRESET_SHIFT               7
+#define USB_USBTRC0_USBRESET_WIDTH               1
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK                0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT               0
+#define USB_USBFRMADJUST_ADJ_WIDTH               8
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH 1
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))&USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK       0x1u
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      0
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH      1
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH 1
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))&USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR                            (USB0)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USB - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID                               USB_PERID_REG(USB0)
+#define USB0_IDCOMP                              USB_IDCOMP_REG(USB0)
+#define USB0_REV                                 USB_REV_REG(USB0)
+#define USB0_ADDINFO                             USB_ADDINFO_REG(USB0)
+#define USB0_OTGISTAT                            USB_OTGISTAT_REG(USB0)
+#define USB0_OTGICR                              USB_OTGICR_REG(USB0)
+#define USB0_OTGSTAT                             USB_OTGSTAT_REG(USB0)
+#define USB0_OTGCTL                              USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT                               USB_ISTAT_REG(USB0)
+#define USB0_INTEN                               USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT                             USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN                               USB_ERREN_REG(USB0)
+#define USB0_STAT                                USB_STAT_REG(USB0)
+#define USB0_CTL                                 USB_CTL_REG(USB0)
+#define USB0_ADDR                                USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1                            USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML                             USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH                             USB_FRMNUMH_REG(USB0)
+#define USB0_TOKEN                               USB_TOKEN_REG(USB0)
+#define USB0_SOFTHLD                             USB_SOFTHLD_REG(USB0)
+#define USB0_BDTPAGE2                            USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3                            USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0                              USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1                              USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2                              USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3                              USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4                              USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5                              USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6                              USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7                              USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8                              USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9                              USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10                             USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11                             USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12                             USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13                             USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14                             USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15                             USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL                             USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE                             USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL                             USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0                             USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST                        USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL                    USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN                  USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS              USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index)                        USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
+  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
+  __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
+  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
+  union {                                          /* offset: 0x18 */
+    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
+    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
+  };
+} USBDCD_Type, *USBDCD_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register accessors */
+#define USBDCD_CONTROL_REG(base)                 ((base)->CONTROL)
+#define USBDCD_CLOCK_REG(base)                   ((base)->CLOCK)
+#define USBDCD_STATUS_REG(base)                  ((base)->STATUS)
+#define USBDCD_TIMER0_REG(base)                  ((base)->TIMER0)
+#define USBDCD_TIMER1_REG(base)                  ((base)->TIMER1)
+#define USBDCD_TIMER2_BC11_REG(base)             ((base)->TIMER2_BC11)
+#define USBDCD_TIMER2_BC12_REG(base)             ((base)->TIMER2_BC12)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK                 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT                0
+#define USBDCD_CONTROL_IACK_WIDTH                1
+#define USBDCD_CONTROL_IACK(x)                   (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IACK_SHIFT))&USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IF_MASK                   0x100u
+#define USBDCD_CONTROL_IF_SHIFT                  8
+#define USBDCD_CONTROL_IF_WIDTH                  1
+#define USBDCD_CONTROL_IF(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IF_SHIFT))&USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IE_MASK                   0x10000u
+#define USBDCD_CONTROL_IE_SHIFT                  16
+#define USBDCD_CONTROL_IE_WIDTH                  1
+#define USBDCD_CONTROL_IE(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IE_SHIFT))&USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_BC12_MASK                 0x20000u
+#define USBDCD_CONTROL_BC12_SHIFT                17
+#define USBDCD_CONTROL_BC12_WIDTH                1
+#define USBDCD_CONTROL_BC12(x)                   (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_BC12_SHIFT))&USBDCD_CONTROL_BC12_MASK)
+#define USBDCD_CONTROL_START_MASK                0x1000000u
+#define USBDCD_CONTROL_START_SHIFT               24
+#define USBDCD_CONTROL_START_WIDTH               1
+#define USBDCD_CONTROL_START(x)                  (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_START_SHIFT))&USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_SR_MASK                   0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT                  25
+#define USBDCD_CONTROL_SR_WIDTH                  1
+#define USBDCD_CONTROL_SR(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_SR_SHIFT))&USBDCD_CONTROL_SR_MASK)
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK             0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            0
+#define USBDCD_CLOCK_CLOCK_UNIT_WIDTH            1
+#define USBDCD_CLOCK_CLOCK_UNIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_UNIT_SHIFT))&USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK            0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           2
+#define USBDCD_CLOCK_CLOCK_SPEED_WIDTH           10
+#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK               0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT              16
+#define USBDCD_STATUS_SEQ_RES_WIDTH              2
+#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK              0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT             18
+#define USBDCD_STATUS_SEQ_STAT_WIDTH             2
+#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK                   0x100000u
+#define USBDCD_STATUS_ERR_SHIFT                  20
+#define USBDCD_STATUS_ERR_WIDTH                  1
+#define USBDCD_STATUS_ERR(x)                     (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ERR_SHIFT))&USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_TO_MASK                    0x200000u
+#define USBDCD_STATUS_TO_SHIFT                   21
+#define USBDCD_STATUS_TO_WIDTH                   1
+#define USBDCD_STATUS_TO(x)                      (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_TO_SHIFT))&USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_ACTIVE_MASK                0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT               22
+#define USBDCD_STATUS_ACTIVE_WIDTH               1
+#define USBDCD_STATUS_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ACTIVE_SHIFT))&USBDCD_STATUS_ACTIVE_MASK)
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK              0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT             0
+#define USBDCD_TIMER0_TUNITCON_WIDTH             12
+#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK             0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            16
+#define USBDCD_TIMER0_TSEQ_INIT_WIDTH            10
+#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK            0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           0
+#define USBDCD_TIMER1_TVDPSRC_ON_WIDTH           10
+#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK             0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            16
+#define USBDCD_TIMER1_TDCD_DBNC_WIDTH            10
+#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2_BC11 Bit Fields */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK         0xFu
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        0
+#define USBDCD_TIMER2_BC11_CHECK_DM_WIDTH        4
+#define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      0x3FF0000u
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     16
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_WIDTH     10
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+/* TIMER2_BC12 Bit Fields */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       0x3FFu
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      0
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_WIDTH      10
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  0x3FF0000u
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_WIDTH 10
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE                              (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD                                   ((USBDCD_Type *)USBDCD_BASE)
+#define USBDCD_BASE_PTR                          (USBDCD)
+/** Array initializer of USBDCD peripheral base addresses */
+#define USBDCD_BASE_ADDRS                        { USBDCD_BASE }
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASE_PTRS                         { USBDCD }
+/** Interrupt vectors for the USBDCD peripheral type */
+#define USBDCD_IRQS                              { USBDCD_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
+ * @{
+ */
+
+
+/* USBDCD - Register instance definitions */
+/* USBDCD */
+#define USBDCD_CONTROL                           USBDCD_CONTROL_REG(USBDCD)
+#define USBDCD_CLOCK                             USBDCD_CLOCK_REG(USBDCD)
+#define USBDCD_STATUS                            USBDCD_STATUS_REG(USBDCD)
+#define USBDCD_TIMER0                            USBDCD_TIMER0_REG(USBDCD)
+#define USBDCD_TIMER1                            USBDCD_TIMER1_REG(USBDCD)
+#define USBDCD_TIMER2_BC11                       USBDCD_TIMER2_BC11_REG(USBDCD)
+#define USBDCD_TIMER2_BC12                       USBDCD_TIMER2_BC12_REG(USBDCD)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base)                       ((base)->TRM)
+#define VREF_SC_REG(base)                        ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK                       0x3Fu
+#define VREF_TRM_TRIM_SHIFT                      0
+#define VREF_TRM_TRIM_WIDTH                      6
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     0x40u
+#define VREF_TRM_CHOPEN_SHIFT                    6
+#define VREF_TRM_CHOPEN_WIDTH                    1
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_TRM_CHOPEN_SHIFT))&VREF_TRM_CHOPEN_MASK)
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK                     0x3u
+#define VREF_SC_MODE_LV_SHIFT                    0
+#define VREF_SC_MODE_LV_WIDTH                    2
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      0x4u
+#define VREF_SC_VREFST_SHIFT                     2
+#define VREF_SC_VREFST_WIDTH                     1
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFST_SHIFT))&VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK                     0x20u
+#define VREF_SC_ICOMPEN_SHIFT                    5
+#define VREF_SC_ICOMPEN_WIDTH                    1
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_ICOMPEN_SHIFT))&VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK                       0x40u
+#define VREF_SC_REGEN_SHIFT                      6
+#define VREF_SC_REGEN_WIDTH                      1
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x))<<VREF_SC_REGEN_SHIFT))&VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK                      0x80u
+#define VREF_SC_VREFEN_SHIFT                     7
+#define VREF_SC_VREFEN_WIDTH                     1
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFEN_SHIFT))&VREF_SC_VREFEN_MASK)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR                            (VREF)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/* ----------------------------------------------------------------------------
+   -- VREF - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM                                 VREF_TRM_REG(VREF)
+#define VREF_SC                                  VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t STCTRLH;                           /**< Watchdog Status and Control Register High, offset: 0x0 */
+  __IO uint16_t STCTRLL;                           /**< Watchdog Status and Control Register Low, offset: 0x2 */
+  __IO uint16_t TOVALH;                            /**< Watchdog Time-out Value Register High, offset: 0x4 */
+  __IO uint16_t TOVALL;                            /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+  __IO uint16_t WINH;                              /**< Watchdog Window Register High, offset: 0x8 */
+  __IO uint16_t WINL;                              /**< Watchdog Window Register Low, offset: 0xA */
+  __IO uint16_t REFRESH;                           /**< Watchdog Refresh register, offset: 0xC */
+  __IO uint16_t UNLOCK;                            /**< Watchdog Unlock register, offset: 0xE */
+  __IO uint16_t TMROUTH;                           /**< Watchdog Timer Output Register High, offset: 0x10 */
+  __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
+  __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
+  __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type, *WDOG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register accessors */
+#define WDOG_STCTRLH_REG(base)                   ((base)->STCTRLH)
+#define WDOG_STCTRLL_REG(base)                   ((base)->STCTRLL)
+#define WDOG_TOVALH_REG(base)                    ((base)->TOVALH)
+#define WDOG_TOVALL_REG(base)                    ((base)->TOVALL)
+#define WDOG_WINH_REG(base)                      ((base)->WINH)
+#define WDOG_WINL_REG(base)                      ((base)->WINL)
+#define WDOG_REFRESH_REG(base)                   ((base)->REFRESH)
+#define WDOG_UNLOCK_REG(base)                    ((base)->UNLOCK)
+#define WDOG_TMROUTH_REG(base)                   ((base)->TMROUTH)
+#define WDOG_TMROUTL_REG(base)                   ((base)->TMROUTL)
+#define WDOG_RSTCNT_REG(base)                    ((base)->RSTCNT)
+#define WDOG_PRESC_REG(base)                     ((base)->PRESC)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK                 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT                0
+#define WDOG_STCTRLH_WDOGEN_WIDTH                1
+#define WDOG_STCTRLH_WDOGEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WDOGEN_SHIFT))&WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK                 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT                1
+#define WDOG_STCTRLH_CLKSRC_WIDTH                1
+#define WDOG_STCTRLH_CLKSRC(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_CLKSRC_SHIFT))&WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK               0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT              2
+#define WDOG_STCTRLH_IRQRSTEN_WIDTH              1
+#define WDOG_STCTRLH_IRQRSTEN(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_IRQRSTEN_SHIFT))&WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK                  0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT                 3
+#define WDOG_STCTRLH_WINEN_WIDTH                 1
+#define WDOG_STCTRLH_WINEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WINEN_SHIFT))&WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK            0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           4
+#define WDOG_STCTRLH_ALLOWUPDATE_WIDTH           1
+#define WDOG_STCTRLH_ALLOWUPDATE(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_ALLOWUPDATE_SHIFT))&WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK                  0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT                 5
+#define WDOG_STCTRLH_DBGEN_WIDTH                 1
+#define WDOG_STCTRLH_DBGEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DBGEN_SHIFT))&WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK                 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT                6
+#define WDOG_STCTRLH_STOPEN_WIDTH                1
+#define WDOG_STCTRLH_STOPEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_STOPEN_SHIFT))&WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK                 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT                7
+#define WDOG_STCTRLH_WAITEN_WIDTH                1
+#define WDOG_STCTRLH_WAITEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WAITEN_SHIFT))&WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK               0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT              10
+#define WDOG_STCTRLH_TESTWDOG_WIDTH              1
+#define WDOG_STCTRLH_TESTWDOG(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTWDOG_SHIFT))&WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK                0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT               11
+#define WDOG_STCTRLH_TESTSEL_WIDTH               1
+#define WDOG_STCTRLH_TESTSEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTSEL_SHIFT))&WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK                0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT               12
+#define WDOG_STCTRLH_BYTESEL_WIDTH               2
+#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK            0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT           14
+#define WDOG_STCTRLH_DISTESTWDOG_WIDTH           1
+#define WDOG_STCTRLH_DISTESTWDOG(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DISTESTWDOG_SHIFT))&WDOG_STCTRLH_DISTESTWDOG_MASK)
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK                 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT                15
+#define WDOG_STCTRLL_INTFLG_WIDTH                1
+#define WDOG_STCTRLL_INTFLG(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLL_INTFLG_SHIFT))&WDOG_STCTRLL_INTFLG_MASK)
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK               0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              0
+#define WDOG_TOVALH_TOVALHIGH_WIDTH              16
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK                0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT               0
+#define WDOG_TOVALL_TOVALLOW_WIDTH               16
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK                   0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT                  0
+#define WDOG_WINH_WINHIGH_WIDTH                  16
+#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK                    0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT                   0
+#define WDOG_WINL_WINLOW_WIDTH                   16
+#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK            0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT           0
+#define WDOG_REFRESH_WDOGREFRESH_WIDTH           16
+#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK              0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             0
+#define WDOG_UNLOCK_WDOGUNLOCK_WIDTH             16
+#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK           0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          0
+#define WDOG_TMROUTH_TIMEROUTHIGH_WIDTH          16
+#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK            0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           0
+#define WDOG_TMROUTL_TIMEROUTLOW_WIDTH           16
+#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK                  0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT                 0
+#define WDOG_RSTCNT_RSTCNT_WIDTH                 16
+#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK                 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT                8
+#define WDOG_PRESC_PRESCVAL_WIDTH                3
+#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+#define WDOG_BASE_PTR                            (WDOG)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS                          { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS                           { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS                                { WDOG_EWM_IRQn }
+
+/* ----------------------------------------------------------------------------
+   -- WDOG - Register accessor macros
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register instance definitions */
+/* WDOG */
+#define WDOG_STCTRLH                             WDOG_STCTRLH_REG(WDOG)
+#define WDOG_STCTRLL                             WDOG_STCTRLL_REG(WDOG)
+#define WDOG_TOVALH                              WDOG_TOVALH_REG(WDOG)
+#define WDOG_TOVALL                              WDOG_TOVALL_REG(WDOG)
+#define WDOG_WINH                                WDOG_WINH_REG(WDOG)
+#define WDOG_WINL                                WDOG_WINL_REG(WDOG)
+#define WDOG_REFRESH                             WDOG_REFRESH_REG(WDOG)
+#define WDOG_UNLOCK                              WDOG_UNLOCK_REG(WDOG)
+#define WDOG_TMROUTH                             WDOG_TMROUTH_REG(WDOG)
+#define WDOG_TMROUTL                             WDOG_TMROUTL_REG(WDOG)
+#define WDOG_RSTCNT                              WDOG_RSTCNT_REG(WDOG)
+#define WDOG_PRESC                               WDOG_PRESC_REG(WDOG)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Backward Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define DMA_EARS_REG(base)                       This_symbol_has_been_deprecated
+#define DMA_EARS                                 This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_0_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_1_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_2_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_3_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_4_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_5_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_6_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_7_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_8_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_MASK                    This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_9_SHIFT                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_10_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_11_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_12_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_13_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_14_SHIFT                  This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_MASK                   This_symbol_has_been_deprecated
+#define DMA_EARS_EDREQ_15_SHIFT                  This_symbol_has_been_deprecated
+#define ENET_RMON_T_DROP_REG(base)               This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP_REG(base)               This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE_REG(base)                This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0_REG(base)            This_symbol_has_been_deprecated
+#define ENET_RMON_R_DROP_REG(base)               ENET_IEEE_R_DROP_REG(base)
+#define ENET_RMON_R_FRAME_OK_REG(base)           ENET_IEEE_R_FRAME_OK_REG(base)
+#define ENET_RMON_T_DROP                         This_symbol_has_been_deprecated
+#define ENET_IEEE_T_DROP                         This_symbol_has_been_deprecated
+#define ENET_IEEE_T_SQE                          This_symbol_has_been_deprecated
+#define ENET_RMON_R_RESVD_0                      This_symbol_has_been_deprecated
+#define MCG_C9_REG(base)                         This_symbol_has_been_deprecated
+#define MCG_C2_EREFS0_MASK                       MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT                      MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK                         MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT                        MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK                       MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT                      MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x)                         MCG_C2_RANGE(x)
+#define MCG_C9                                   This_symbol_has_been_deprecated
+#define MCM_PLACR_REG(base)                      This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_MASK                       This_symbol_has_been_deprecated
+#define MCM_PLACR_ARB_SHIFT                      This_symbol_has_been_deprecated
+#define MCM_PLACR                                This_symbol_has_been_deprecated
+#define ADC_BASES                    ADC_BASE_PTRS
+#define AIPS_BASES                   AIPS_BASE_PTRS
+#define AXBS_BASES                   AXBS_BASE_PTRS
+#define CAN_BASES                    CAN_BASE_PTRS
+#define CAU_BASES                    CAU_BASE_PTRS
+#define CMP_BASES                    CMP_BASE_PTRS
+#define CMT_BASES                    CMT_BASE_PTRS
+#define CRC_BASES                    CRC_BASE_PTRS
+#define DAC_BASES                    DAC_BASE_PTRS
+#define DMA_BASES                    DMA_BASE_PTRS
+#define DMAMUX_BASES                 DMAMUX_BASE_PTRS
+#define ENET_BASES                   ENET_BASE_PTRS
+#define EWM_BASES                    EWM_BASE_PTRS
+#define FB_BASES                     FB_BASE_PTRS
+#define FMC_BASES                    FMC_BASE_PTRS
+#define FTFE_BASES                   FTFE_BASE_PTRS
+#define FTM_BASES                    FTM_BASE_PTRS
+#define GPIO_BASES                   GPIO_BASE_PTRS
+#define I2C_BASES                    I2C_BASE_PTRS
+#define I2S_BASES                    I2S_BASE_PTRS
+#define LLWU_BASES                   LLWU_BASE_PTRS
+#define LPTMR_BASES                  LPTMR_BASE_PTRS
+#define MCG_BASES                    MCG_BASE_PTRS
+#define MCM_ISR_REG(base)            MCM_ISCR_REG(base)
+#define MCM_ISR_FIOC_MASK            MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT           MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK            MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT           MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK            MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT           MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK            MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT           MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK            MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT           MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK            MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT           MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK           MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT          MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK           MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT          MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK           MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT          MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK           MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT          MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK           MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT          MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK           MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT          MCM_ISCR_FIDCE_SHIFT
+#define MCM_BASES                    MCM_BASE_PTRS
+#define MPU_BASES                    MPU_BASE_PTRS
+#define NV_BASES                     NV_BASE_PTRS
+#define OSC_BASES                    OSC_BASE_PTRS
+#define PDB_BASES                    PDB_BASE_PTRS
+#define PIT_BASES                    PIT_BASE_PTRS
+#define PMC_BASES                    PMC_BASE_PTRS
+#define PORT_BASES                   PORT_BASE_PTRS
+#define RCM_BASES                    RCM_BASE_PTRS
+#define RFSYS_BASES                  RFSYS_BASE_PTRS
+#define RFVBAT_BASES                 RFVBAT_BASE_PTRS
+#define RNG_BASES                    RNG_BASE_PTRS
+#define RTC_BASES                    RTC_BASE_PTRS
+#define SDHC_BASES                   SDHC_BASE_PTRS
+#define SIM_BASES                    SIM_BASE_PTRS
+#define SMC_BASES                    SMC_BASE_PTRS
+#define SPI_BASES                    SPI_BASE_PTRS
+#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
+#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
+#define UART_WP7816_T_TYPE0_WI_MASK  UART_WP7816T0_WI_MASK
+#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
+#define UART_WP7816_T_TYPE0_WI(x)    UART_WP7816T0_WI(x)
+#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
+#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
+#define UART_WP7816_T_TYPE1_BWI(x)   UART_WP7816T1_BWI(x)
+#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
+#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
+#define UART_WP7816_T_TYPE1_CWI(x)   UART_WP7816T1_CWI(x)
+#define UART_BASES                   UART_BASE_PTRS
+#define USB_BASES                    USB_BASE_PTRS
+#define USBDCD_BASES                 USBDCD_BASE_PTRS
+#define VREF_BASES                   VREF_BASE_PTRS
+#define WDOG_BASES                   WDOG_BASE_PTRS
+#define Watchdog_IRQn                WDOG_EWM_IRQn
+#define Watchdog_IRQHandler          WDOG_EWM_IRQHandler
+#define LPTimer_IRQn                 LPTMR0_IRQn
+#define LPTimer_IRQHandler           LPTMR0_IRQHandler
+#define LLW_IRQn                     LLWU_IRQn
+#define LLW_IRQHandler               LLWU_IRQHandler
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MK64F12_H_) */
+  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+  #if (MCU_MEM_MAP_VERSION != 0x0200u)
+    #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+      #warning There are included two not compatible versions of memory maps. Please check possible differences.
+    #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+  #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
+#endif  /* #if !defined(MK64F12_H_) */
+
+/* MK64F12.h, eof. */
diff --git a/Workspace/UART/SDK/platform/devices/MK64F12/include/MK64F12_extension.h b/Workspace/UART/SDK/platform/devices/MK64F12/include/MK64F12_extension.h
new file mode 100644
index 0000000..c47b6c4
--- /dev/null
+++ b/Workspace/UART/SDK/platform/devices/MK64F12/include/MK64F12_extension.h
@@ -0,0 +1,63846 @@
+/*
+** ###################################################################
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          GNU C Compiler - CodeSourcery Sourcery G++
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150612
+**
+**     Abstract:
+**         Extension to the CMSIS register access layer header.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __MK64F12_EXTENSION_H__
+#define __MK64F12_EXTENSION_H__
+
+#include "MK64F12.h"
+#include "fsl_bitaccess.h"
+
+#if defined(__IAR_SYSTEMS_ICC__)
+  /*
+   * Suppress "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)"
+   * as some register descriptions contain code examples
+   */
+  #pragma diag_suppress=pm008
+#endif
+
+/*
+ * MK64F12 ADC
+ *
+ * Analog-to-Digital Converter
+ *
+ * Registers defined in this header file:
+ * - ADC_SC1 - ADC Status and Control Registers 1
+ * - ADC_CFG1 - ADC Configuration Register 1
+ * - ADC_CFG2 - ADC Configuration Register 2
+ * - ADC_R - ADC Data Result Register
+ * - ADC_CV1 - Compare Value Registers
+ * - ADC_CV2 - Compare Value Registers
+ * - ADC_SC2 - Status and Control Register 2
+ * - ADC_SC3 - Status and Control Register 3
+ * - ADC_OFS - ADC Offset Correction Register
+ * - ADC_PG - ADC Plus-Side Gain Register
+ * - ADC_MG - ADC Minus-Side Gain Register
+ * - ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ * - ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ * - ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ */
+
+#define ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
+#define ADC0_IDX (0U) /*!< Instance number for ADC0. */
+#define ADC1_IDX (1U) /*!< Instance number for ADC1. */
+
+/*******************************************************************************
+ * ADC_SC1 - ADC Status and Control Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC1 - ADC Status and Control Registers 1 (RW)
+ *
+ * Reset value: 0x0000001FU
+ *
+ * SC1A is used for both software and hardware trigger modes of operation. To
+ * allow sequential conversions of the ADC to be triggered by internal peripherals,
+ * the ADC can have more than one status and control register: one for each
+ * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
+ * for use only in hardware trigger mode. See the chip configuration information
+ * about the number of SC1n registers specific to this device. The SC1n registers
+ * have identical fields, and are used in a "ping-pong" approach to control ADC
+ * operation. At any one point in time, only one of the SC1n registers is actively
+ * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
+ * a conversion is allowed, and vice-versa for any of the SC1n registers specific
+ * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
+ * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
+ * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
+ * value other than all 1s. Writing any of the SC1n registers while that specific
+ * SC1n register is actively controlling a conversion aborts the current conversion.
+ * None of the SC1B-SC1n registers are used for software trigger operation and
+ * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC1 register
+ */
+/*@{*/
+#define ADC_RD_SC1(base, index)  (ADC_SC1_REG(base, index))
+#define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value))
+#define ADC_RMW_SC1(base, index, mask, value) (ADC_WR_SC1(base, index, (ADC_RD_SC1(base, index) & ~(mask)) | (value)))
+#define ADC_SET_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) |  (value)))
+#define ADC_CLR_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) & ~(value)))
+#define ADC_TOG_SC1(base, index, value) (ADC_WR_SC1(base, index, ADC_RD_SC1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC1 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC1, field ADCH[4:0] (RW)
+ *
+ * Selects one of the input channels. The input channel decode depends on the
+ * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
+ * DADMx. Some of the input channel options in the bitfield-setting descriptions might
+ * not be available for your device. For the actual ADC channel assignments for
+ * your device, see the Chip Configuration details. The successive approximation
+ * converter subsystem is turned off when the channel select bits are all set,
+ * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
+ * isolation of the input channel from all sources. Terminating continuous
+ * conversions this way prevents an additional single conversion from being performed. It
+ * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
+ * when continuous conversions are not enabled because the module automatically
+ * enters a low-power state when a conversion completes.
+ *
+ * Values:
+ * - 0b00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
+ *     selected as input.
+ * - 0b00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
+ *     selected as input.
+ * - 0b00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
+ *     selected as input.
+ * - 0b00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
+ *     selected as input.
+ * - 0b00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is
+ *     reserved.
+ * - 0b11000 - Reserved.
+ * - 0b11001 - Reserved.
+ * - 0b11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input;
+ *     when DIFF=1, Temp Sensor (differential) is selected as input.
+ * - 0b11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
+ *     DIFF=1, Bandgap (differential) is selected as input.
+ * - 0b11100 - Reserved.
+ * - 0b11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
+ *     (differential) is selected as input. Voltage reference selected is determined
+ *     by SC2[REFSEL].
+ * - 0b11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
+ *     reserved. Voltage reference selected is determined by SC2[REFSEL].
+ * - 0b11111 - Module is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_ADCH field. */
+#define ADC_RD_SC1_ADCH(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_ADCH_MASK) >> ADC_SC1_ADCH_SHIFT)
+#define ADC_BRD_SC1_ADCH(base, index) (ADC_RD_SC1_ADCH(base, index))
+
+/*! @brief Set the ADCH field to a new value. */
+#define ADC_WR_SC1_ADCH(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_ADCH_MASK, ADC_SC1_ADCH(value)))
+#define ADC_BWR_SC1_ADCH(base, index, value) (ADC_WR_SC1_ADCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field DIFF[5] (RW)
+ *
+ * Configures the ADC to operate in differential mode. When enabled, this mode
+ * automatically selects from the differential channels, and changes the
+ * conversion algorithm and the number of cycles to complete a conversion.
+ *
+ * Values:
+ * - 0b0 - Single-ended conversions and input channels are selected.
+ * - 0b1 - Differential conversions and input channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_DIFF field. */
+#define ADC_RD_SC1_DIFF(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_DIFF_MASK) >> ADC_SC1_DIFF_SHIFT)
+#define ADC_BRD_SC1_DIFF(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT))
+
+/*! @brief Set the DIFF field to a new value. */
+#define ADC_WR_SC1_DIFF(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_DIFF_MASK, ADC_SC1_DIFF(value)))
+#define ADC_BWR_SC1_DIFF(base, index, value) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field AIEN[6] (RW)
+ *
+ * Enables conversion complete interrupts. When COCO becomes set while the
+ * respective AIEN is high, an interrupt is asserted.
+ *
+ * Values:
+ * - 0b0 - Conversion complete interrupt is disabled.
+ * - 0b1 - Conversion complete interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_AIEN field. */
+#define ADC_RD_SC1_AIEN(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIEN_SHIFT)
+#define ADC_BRD_SC1_AIEN(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT))
+
+/*! @brief Set the AIEN field to a new value. */
+#define ADC_WR_SC1_AIEN(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_AIEN_MASK, ADC_SC1_AIEN(value)))
+#define ADC_BWR_SC1_AIEN(base, index, value) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC1, field COCO[7] (RO)
+ *
+ * This is a read-only field that is set each time a conversion is completed
+ * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
+ * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
+ * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
+ * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
+ * COCO is set upon completion of the selected number of conversions (determined
+ * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
+ * COCO is cleared when the respective SC1n register is written or when the
+ * respective Rn register is read.
+ *
+ * Values:
+ * - 0b0 - Conversion is not completed.
+ * - 0b1 - Conversion is completed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC1_COCO field. */
+#define ADC_RD_SC1_COCO(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_COCO_MASK) >> ADC_SC1_COCO_SHIFT)
+#define ADC_BRD_SC1_COCO(base, index) (BITBAND_ACCESS32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG1 - ADC Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG1 - ADC Configuration Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The configuration Register 1 (CFG1) selects the mode of operation, clock
+ * source, clock divide, and configuration for low power or long sample time.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG1 register
+ */
+/*@{*/
+#define ADC_RD_CFG1(base)        (ADC_CFG1_REG(base))
+#define ADC_WR_CFG1(base, value) (ADC_CFG1_REG(base) = (value))
+#define ADC_RMW_CFG1(base, mask, value) (ADC_WR_CFG1(base, (ADC_RD_CFG1(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) |  (value)))
+#define ADC_CLR_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) & ~(value)))
+#define ADC_TOG_CFG1(base, value) (ADC_WR_CFG1(base, ADC_RD_CFG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
+ *
+ * Selects the input clock source to generate the internal clock, ADCK. Note
+ * that when the ADACK clock source is selected, it is not required to be active
+ * prior to conversion start. When it is selected and it is not active prior to a
+ * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
+ * the start of a conversion and deactivated when conversions are terminated. In
+ * this case, there is an associated clock startup delay each time the clock
+ * source is re-activated.
+ *
+ * Values:
+ * - 0b00 - Bus clock
+ * - 0b01 - Alternate clock 2 (ALTCLK2)
+ * - 0b10 - Alternate clock (ALTCLK)
+ * - 0b11 - Asynchronous clock (ADACK)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADICLK field. */
+#define ADC_RD_CFG1_ADICLK(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADICLK_MASK) >> ADC_CFG1_ADICLK_SHIFT)
+#define ADC_BRD_CFG1_ADICLK(base) (ADC_RD_CFG1_ADICLK(base))
+
+/*! @brief Set the ADICLK field to a new value. */
+#define ADC_WR_CFG1_ADICLK(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADICLK_MASK, ADC_CFG1_ADICLK(value)))
+#define ADC_BWR_CFG1_ADICLK(base, value) (ADC_WR_CFG1_ADICLK(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field MODE[3:2] (RW)
+ *
+ * Selects the ADC resolution mode.
+ *
+ * Values:
+ * - 0b00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
+ *     differential 9-bit conversion with 2's complement output.
+ * - 0b01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it
+ *     is differential 13-bit conversion with 2's complement output.
+ * - 0b10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it
+ *     is differential 11-bit conversion with 2's complement output
+ * - 0b11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it
+ *     is differential 16-bit conversion with 2's complement output
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_MODE field. */
+#define ADC_RD_CFG1_MODE(base) ((ADC_CFG1_REG(base) & ADC_CFG1_MODE_MASK) >> ADC_CFG1_MODE_SHIFT)
+#define ADC_BRD_CFG1_MODE(base) (ADC_RD_CFG1_MODE(base))
+
+/*! @brief Set the MODE field to a new value. */
+#define ADC_WR_CFG1_MODE(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_MODE_MASK, ADC_CFG1_MODE(value)))
+#define ADC_BWR_CFG1_MODE(base, value) (ADC_WR_CFG1_MODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLSMP[4] (RW)
+ *
+ * Selects between different sample times based on the conversion mode selected.
+ * This field adjusts the sample period to allow higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption if
+ * continuous conversions are enabled and high conversion rates are not required.
+ * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
+ * extent of the long sample time.
+ *
+ * Values:
+ * - 0b0 - Short sample time.
+ * - 0b1 - Long sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
+#define ADC_RD_CFG1_ADLSMP(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLSMP_MASK) >> ADC_CFG1_ADLSMP_SHIFT)
+#define ADC_BRD_CFG1_ADLSMP(base) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT))
+
+/*! @brief Set the ADLSMP field to a new value. */
+#define ADC_WR_CFG1_ADLSMP(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLSMP_MASK, ADC_CFG1_ADLSMP(value)))
+#define ADC_BWR_CFG1_ADLSMP(base, value) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADIV[6:5] (RW)
+ *
+ * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
+ *
+ * Values:
+ * - 0b00 - The divide ratio is 1 and the clock rate is input clock.
+ * - 0b01 - The divide ratio is 2 and the clock rate is (input clock)/2.
+ * - 0b10 - The divide ratio is 4 and the clock rate is (input clock)/4.
+ * - 0b11 - The divide ratio is 8 and the clock rate is (input clock)/8.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADIV field. */
+#define ADC_RD_CFG1_ADIV(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT)
+#define ADC_BRD_CFG1_ADIV(base) (ADC_RD_CFG1_ADIV(base))
+
+/*! @brief Set the ADIV field to a new value. */
+#define ADC_WR_CFG1_ADIV(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADIV_MASK, ADC_CFG1_ADIV(value)))
+#define ADC_BWR_CFG1_ADIV(base, value) (ADC_WR_CFG1_ADIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG1, field ADLPC[7] (RW)
+ *
+ * Controls the power configuration of the successive approximation converter.
+ * This optimizes power consumption when higher sample rates are not required.
+ *
+ * Values:
+ * - 0b0 - Normal power configuration.
+ * - 0b1 - Low-power configuration. The power is reduced at the expense of
+ *     maximum clock speed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG1_ADLPC field. */
+#define ADC_RD_CFG1_ADLPC(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLPC_MASK) >> ADC_CFG1_ADLPC_SHIFT)
+#define ADC_BRD_CFG1_ADLPC(base) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT))
+
+/*! @brief Set the ADLPC field to a new value. */
+#define ADC_WR_CFG1_ADLPC(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLPC_MASK, ADC_CFG1_ADLPC(value)))
+#define ADC_BWR_CFG1_ADLPC(base, value) (BITBAND_ACCESS32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CFG2 - ADC Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CFG2 - ADC Configuration Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Configuration Register 2 (CFG2) selects the special high-speed configuration
+ * for very high speed conversions and selects the long sample time duration
+ * during long sample mode.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CFG2 register
+ */
+/*@{*/
+#define ADC_RD_CFG2(base)        (ADC_CFG2_REG(base))
+#define ADC_WR_CFG2(base, value) (ADC_CFG2_REG(base) = (value))
+#define ADC_RMW_CFG2(base, mask, value) (ADC_WR_CFG2(base, (ADC_RD_CFG2(base) & ~(mask)) | (value)))
+#define ADC_SET_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) |  (value)))
+#define ADC_CLR_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) & ~(value)))
+#define ADC_TOG_CFG2(base, value) (ADC_WR_CFG2(base, ADC_RD_CFG2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CFG2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
+ *
+ * Selects between the extended sample times when long sample time is selected,
+ * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
+ * accurately sampled or to maximize conversion speed for lower impedance inputs.
+ * Longer sample times can also be used to lower overall power consumption when
+ * continuous conversions are enabled if high conversion rates are not required.
+ *
+ * Values:
+ * - 0b00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
+ *     total.
+ * - 0b01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
+ * - 0b10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
+ * - 0b11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
+#define ADC_RD_CFG2_ADLSTS(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADLSTS_MASK) >> ADC_CFG2_ADLSTS_SHIFT)
+#define ADC_BRD_CFG2_ADLSTS(base) (ADC_RD_CFG2_ADLSTS(base))
+
+/*! @brief Set the ADLSTS field to a new value. */
+#define ADC_WR_CFG2_ADLSTS(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADLSTS_MASK, ADC_CFG2_ADLSTS(value)))
+#define ADC_BWR_CFG2_ADLSTS(base, value) (ADC_WR_CFG2_ADLSTS(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADHSC[2] (RW)
+ *
+ * Configures the ADC for very high-speed operation. The conversion sequence is
+ * altered with 2 ADCK cycles added to the conversion time to allow higher speed
+ * conversion clocks.
+ *
+ * Values:
+ * - 0b0 - Normal conversion sequence selected.
+ * - 0b1 - High-speed conversion sequence selected with 2 additional ADCK cycles
+ *     to total conversion time.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADHSC field. */
+#define ADC_RD_CFG2_ADHSC(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADHSC_MASK) >> ADC_CFG2_ADHSC_SHIFT)
+#define ADC_BRD_CFG2_ADHSC(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT))
+
+/*! @brief Set the ADHSC field to a new value. */
+#define ADC_WR_CFG2_ADHSC(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADHSC_MASK, ADC_CFG2_ADHSC(value)))
+#define ADC_BWR_CFG2_ADHSC(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field ADACKEN[3] (RW)
+ *
+ * Enables the asynchronous clock source and the clock source output regardless
+ * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
+ * asynchronous clock may be used by other modules. See chip configuration
+ * information. Setting this field allows the clock to be used even while the ADC is
+ * idle or operating from a different clock source. Also, latency of initiating a
+ * single or first-continuous conversion with the asynchronous clock selected is
+ * reduced because the ADACK clock is already operational.
+ *
+ * Values:
+ * - 0b0 - Asynchronous clock output disabled; Asynchronous clock is enabled
+ *     only if selected by ADICLK and a conversion is active.
+ * - 0b1 - Asynchronous clock and clock output is enabled regardless of the
+ *     state of the ADC.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
+#define ADC_RD_CFG2_ADACKEN(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADACKEN_MASK) >> ADC_CFG2_ADACKEN_SHIFT)
+#define ADC_BRD_CFG2_ADACKEN(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT))
+
+/*! @brief Set the ADACKEN field to a new value. */
+#define ADC_WR_CFG2_ADACKEN(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADACKEN_MASK, ADC_CFG2_ADACKEN(value)))
+#define ADC_BWR_CFG2_ADACKEN(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_CFG2, field MUXSEL[4] (RW)
+ *
+ * Changes the ADC mux setting to select between alternate sets of ADC channels.
+ *
+ * Values:
+ * - 0b0 - ADxxa channels are selected.
+ * - 0b1 - ADxxb channels are selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
+#define ADC_RD_CFG2_MUXSEL(base) ((ADC_CFG2_REG(base) & ADC_CFG2_MUXSEL_MASK) >> ADC_CFG2_MUXSEL_SHIFT)
+#define ADC_BRD_CFG2_MUXSEL(base) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT))
+
+/*! @brief Set the MUXSEL field to a new value. */
+#define ADC_WR_CFG2_MUXSEL(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_MUXSEL_MASK, ADC_CFG2_MUXSEL(value)))
+#define ADC_BWR_CFG2_MUXSEL(base, value) (BITBAND_ACCESS32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_R - ADC Data Result Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_R - ADC Data Result Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The data result registers (Rn) contain the result of an ADC conversion of the
+ * channel selected by the corresponding status and channel control register
+ * (SC1A:SC1n). For every status and channel control register, there is a
+ * corresponding data result register. Unused bits in R n are cleared in unsigned
+ * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
+ * For example, when configured for 10-bit single-ended mode, D[15:10] are
+ * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
+ * that is, bit 10 extended through bit 15. The following table describes the
+ * behavior of the data result registers in the different modes of operation. Data
+ * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
+ * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
+ * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
+ * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
+ * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
+ * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
+ * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
+ * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
+ * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
+ * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
+ * 2's complement data if indicated
+ */
+/*!
+ * @name Constants and macros for entire ADC_R register
+ */
+/*@{*/
+#define ADC_RD_R(base, index)    (ADC_R_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_R bitfields
+ */
+
+/*!
+ * @name Register ADC_R, field D[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_R_D field. */
+#define ADC_RD_R_D(base, index) ((ADC_R_REG(base, index) & ADC_R_D_MASK) >> ADC_R_D_SHIFT)
+#define ADC_BRD_R_D(base, index) (ADC_RD_R_D(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV1 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV1 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV1 register
+ */
+/*@{*/
+#define ADC_RD_CV1(base)         (ADC_CV1_REG(base))
+#define ADC_WR_CV1(base, value)  (ADC_CV1_REG(base) = (value))
+#define ADC_RMW_CV1(base, mask, value) (ADC_WR_CV1(base, (ADC_RD_CV1(base) & ~(mask)) | (value)))
+#define ADC_SET_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) |  (value)))
+#define ADC_CLR_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) & ~(value)))
+#define ADC_TOG_CV1(base, value) (ADC_WR_CV1(base, ADC_RD_CV1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV1, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV1_CV field. */
+#define ADC_RD_CV1_CV(base)  ((ADC_CV1_REG(base) & ADC_CV1_CV_MASK) >> ADC_CV1_CV_SHIFT)
+#define ADC_BRD_CV1_CV(base) (ADC_RD_CV1_CV(base))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV1_CV(base, value) (ADC_RMW_CV1(base, ADC_CV1_CV_MASK, ADC_CV1_CV(value)))
+#define ADC_BWR_CV1_CV(base, value) (ADC_WR_CV1_CV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CV2 - Compare Value Registers
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CV2 - Compare Value Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Compare Value Registers (CV1 and CV2) contain a compare value used to
+ * compare the conversion result when the compare function is enabled, that is,
+ * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
+ * different modes of operation for both bit position definition and value format
+ * using unsigned or sign-extended 2's complement. Therefore, the compare function
+ * uses only the CVn fields that are related to the ADC mode of operation. The
+ * compare value 2 register (CV2) is used only when the compare range function is
+ * enabled, that is, SC2[ACREN]=1.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CV2 register
+ */
+/*@{*/
+#define ADC_RD_CV2(base)         (ADC_CV2_REG(base))
+#define ADC_WR_CV2(base, value)  (ADC_CV2_REG(base) = (value))
+#define ADC_RMW_CV2(base, mask, value) (ADC_WR_CV2(base, (ADC_RD_CV2(base) & ~(mask)) | (value)))
+#define ADC_SET_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) |  (value)))
+#define ADC_CLR_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) & ~(value)))
+#define ADC_TOG_CV2(base, value) (ADC_WR_CV2(base, ADC_RD_CV2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CV2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CV2, field CV[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CV2_CV field. */
+#define ADC_RD_CV2_CV(base)  ((ADC_CV2_REG(base) & ADC_CV2_CV_MASK) >> ADC_CV2_CV_SHIFT)
+#define ADC_BRD_CV2_CV(base) (ADC_RD_CV2_CV(base))
+
+/*! @brief Set the CV field to a new value. */
+#define ADC_WR_CV2_CV(base, value) (ADC_RMW_CV2(base, ADC_CV2_CV_MASK, ADC_CV2_CV(value)))
+#define ADC_BWR_CV2_CV(base, value) (ADC_WR_CV2_CV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC2 - Status and Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC2 - Status and Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The status and control register 2 (SC2) contains the conversion active,
+ * hardware/software trigger select, compare function, and voltage reference select of
+ * the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC2 register
+ */
+/*@{*/
+#define ADC_RD_SC2(base)         (ADC_SC2_REG(base))
+#define ADC_WR_SC2(base, value)  (ADC_SC2_REG(base) = (value))
+#define ADC_RMW_SC2(base, mask, value) (ADC_WR_SC2(base, (ADC_RD_SC2(base) & ~(mask)) | (value)))
+#define ADC_SET_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) |  (value)))
+#define ADC_CLR_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) & ~(value)))
+#define ADC_TOG_SC2(base, value) (ADC_WR_SC2(base, ADC_RD_SC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC2 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC2, field REFSEL[1:0] (RW)
+ *
+ * Selects the voltage reference source used for conversions.
+ *
+ * Values:
+ * - 0b00 - Default voltage reference pin pair, that is, external pins VREFH and
+ *     VREFL
+ * - 0b01 - Alternate reference pair, that is, VALTH and VALTL . This pair may
+ *     be additional external pins or internal sources depending on the MCU
+ *     configuration. See the chip configuration information for details specific to
+ *     this MCU
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_REFSEL field. */
+#define ADC_RD_SC2_REFSEL(base) ((ADC_SC2_REG(base) & ADC_SC2_REFSEL_MASK) >> ADC_SC2_REFSEL_SHIFT)
+#define ADC_BRD_SC2_REFSEL(base) (ADC_RD_SC2_REFSEL(base))
+
+/*! @brief Set the REFSEL field to a new value. */
+#define ADC_WR_SC2_REFSEL(base, value) (ADC_RMW_SC2(base, ADC_SC2_REFSEL_MASK, ADC_SC2_REFSEL(value)))
+#define ADC_BWR_SC2_REFSEL(base, value) (ADC_WR_SC2_REFSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field DMAEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled and will assert the ADC DMA request during an ADC
+ *     conversion complete event noted when any of the SC1n[COCO] flags is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_DMAEN field. */
+#define ADC_RD_SC2_DMAEN(base) ((ADC_SC2_REG(base) & ADC_SC2_DMAEN_MASK) >> ADC_SC2_DMAEN_SHIFT)
+#define ADC_BRD_SC2_DMAEN(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define ADC_WR_SC2_DMAEN(base, value) (ADC_RMW_SC2(base, ADC_SC2_DMAEN_MASK, ADC_SC2_DMAEN(value)))
+#define ADC_BWR_SC2_DMAEN(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACREN[3] (RW)
+ *
+ * Configures the compare function to check if the conversion result of the
+ * input being monitored is either between or outside the range formed by CV1 and CV2
+ * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
+ * effect.
+ *
+ * Values:
+ * - 0b0 - Range function disabled. Only CV1 is compared.
+ * - 0b1 - Range function enabled. Both CV1 and CV2 are compared.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACREN field. */
+#define ADC_RD_SC2_ACREN(base) ((ADC_SC2_REG(base) & ADC_SC2_ACREN_MASK) >> ADC_SC2_ACREN_SHIFT)
+#define ADC_BRD_SC2_ACREN(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT))
+
+/*! @brief Set the ACREN field to a new value. */
+#define ADC_WR_SC2_ACREN(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACREN_MASK, ADC_SC2_ACREN(value)))
+#define ADC_BWR_SC2_ACREN(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFGT[4] (RW)
+ *
+ * Configures the compare function to check the conversion result relative to
+ * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
+ * have any effect.
+ *
+ * Values:
+ * - 0b0 - Configures less than threshold, outside range not inclusive and
+ *     inside range not inclusive; functionality based on the values placed in CV1 and
+ *     CV2.
+ * - 0b1 - Configures greater than or equal to threshold, outside and inside
+ *     ranges inclusive; functionality based on the values placed in CV1 and CV2.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFGT field. */
+#define ADC_RD_SC2_ACFGT(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFGT_MASK) >> ADC_SC2_ACFGT_SHIFT)
+#define ADC_BRD_SC2_ACFGT(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT))
+
+/*! @brief Set the ACFGT field to a new value. */
+#define ADC_WR_SC2_ACFGT(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFGT_MASK, ADC_SC2_ACFGT(value)))
+#define ADC_BWR_SC2_ACFGT(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ACFE[5] (RW)
+ *
+ * Enables the compare function.
+ *
+ * Values:
+ * - 0b0 - Compare function disabled.
+ * - 0b1 - Compare function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ACFE field. */
+#define ADC_RD_SC2_ACFE(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFE_MASK) >> ADC_SC2_ACFE_SHIFT)
+#define ADC_BRD_SC2_ACFE(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT))
+
+/*! @brief Set the ACFE field to a new value. */
+#define ADC_WR_SC2_ACFE(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFE_MASK, ADC_SC2_ACFE(value)))
+#define ADC_BWR_SC2_ACFE(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADTRG[6] (RW)
+ *
+ * Selects the type of trigger used for initiating a conversion. Two types of
+ * trigger are selectable: Software trigger: When software trigger is selected, a
+ * conversion is initiated following a write to SC1A. Hardware trigger: When
+ * hardware trigger is selected, a conversion is initiated following the assertion of
+ * the ADHWT input after a pulse of the ADHWTSn input.
+ *
+ * Values:
+ * - 0b0 - Software trigger selected.
+ * - 0b1 - Hardware trigger selected.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADTRG field. */
+#define ADC_RD_SC2_ADTRG(base) ((ADC_SC2_REG(base) & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT)
+#define ADC_BRD_SC2_ADTRG(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT))
+
+/*! @brief Set the ADTRG field to a new value. */
+#define ADC_WR_SC2_ADTRG(base, value) (ADC_RMW_SC2(base, ADC_SC2_ADTRG_MASK, ADC_SC2_ADTRG(value)))
+#define ADC_BWR_SC2_ADTRG(base, value) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC2, field ADACT[7] (RO)
+ *
+ * Indicates that a conversion or hardware averaging is in progress. ADACT is
+ * set when a conversion is initiated and cleared when a conversion is completed or
+ * aborted.
+ *
+ * Values:
+ * - 0b0 - Conversion not in progress.
+ * - 0b1 - Conversion in progress.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC2_ADACT field. */
+#define ADC_RD_SC2_ADACT(base) ((ADC_SC2_REG(base) & ADC_SC2_ADACT_MASK) >> ADC_SC2_ADACT_SHIFT)
+#define ADC_BRD_SC2_ADACT(base) (BITBAND_ACCESS32(&ADC_SC2_REG(base), ADC_SC2_ADACT_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_SC3 - Status and Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_SC3 - Status and Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Status and Control Register 3 (SC3) controls the calibration, continuous
+ * convert, and hardware averaging functions of the ADC module.
+ */
+/*!
+ * @name Constants and macros for entire ADC_SC3 register
+ */
+/*@{*/
+#define ADC_RD_SC3(base)         (ADC_SC3_REG(base))
+#define ADC_WR_SC3(base, value)  (ADC_SC3_REG(base) = (value))
+#define ADC_RMW_SC3(base, mask, value) (ADC_WR_SC3(base, (ADC_RD_SC3(base) & ~(mask)) | (value)))
+#define ADC_SET_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) |  (value)))
+#define ADC_CLR_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) & ~(value)))
+#define ADC_TOG_SC3(base, value) (ADC_WR_SC3(base, ADC_RD_SC3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_SC3 bitfields
+ */
+
+/*!
+ * @name Register ADC_SC3, field AVGS[1:0] (RW)
+ *
+ * Determines how many ADC conversions will be averaged to create the ADC
+ * average result.
+ *
+ * Values:
+ * - 0b00 - 4 samples averaged.
+ * - 0b01 - 8 samples averaged.
+ * - 0b10 - 16 samples averaged.
+ * - 0b11 - 32 samples averaged.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGS field. */
+#define ADC_RD_SC3_AVGS(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGS_MASK) >> ADC_SC3_AVGS_SHIFT)
+#define ADC_BRD_SC3_AVGS(base) (ADC_RD_SC3_AVGS(base))
+
+/*! @brief Set the AVGS field to a new value. */
+#define ADC_WR_SC3_AVGS(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGS_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGS(value)))
+#define ADC_BWR_SC3_AVGS(base, value) (ADC_WR_SC3_AVGS(base, value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field AVGE[2] (RW)
+ *
+ * Enables the hardware average function of the ADC.
+ *
+ * Values:
+ * - 0b0 - Hardware average function disabled.
+ * - 0b1 - Hardware average function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_AVGE field. */
+#define ADC_RD_SC3_AVGE(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGE_MASK) >> ADC_SC3_AVGE_SHIFT)
+#define ADC_BRD_SC3_AVGE(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT))
+
+/*! @brief Set the AVGE field to a new value. */
+#define ADC_WR_SC3_AVGE(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGE_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGE(value)))
+#define ADC_BWR_SC3_AVGE(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field ADCO[3] (RW)
+ *
+ * Enables continuous conversions.
+ *
+ * Values:
+ * - 0b0 - One conversion or one set of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ * - 0b1 - Continuous conversions or sets of conversions if the hardware average
+ *     function is enabled, that is, AVGE=1, after initiating a conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_ADCO field. */
+#define ADC_RD_SC3_ADCO(base) ((ADC_SC3_REG(base) & ADC_SC3_ADCO_MASK) >> ADC_SC3_ADCO_SHIFT)
+#define ADC_BRD_SC3_ADCO(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT))
+
+/*! @brief Set the ADCO field to a new value. */
+#define ADC_WR_SC3_ADCO(base, value) (ADC_RMW_SC3(base, (ADC_SC3_ADCO_MASK | ADC_SC3_CALF_MASK), ADC_SC3_ADCO(value)))
+#define ADC_BWR_SC3_ADCO(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CALF[6] (W1C)
+ *
+ * Displays the result of the calibration sequence. The calibration sequence
+ * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
+ * entered before the calibration sequence completes. Writing 1 to CALF clears it.
+ *
+ * Values:
+ * - 0b0 - Calibration completed normally.
+ * - 0b1 - Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CALF field. */
+#define ADC_RD_SC3_CALF(base) ((ADC_SC3_REG(base) & ADC_SC3_CALF_MASK) >> ADC_SC3_CALF_SHIFT)
+#define ADC_BRD_SC3_CALF(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT))
+
+/*! @brief Set the CALF field to a new value. */
+#define ADC_WR_SC3_CALF(base, value) (ADC_RMW_SC3(base, ADC_SC3_CALF_MASK, ADC_SC3_CALF(value)))
+#define ADC_BWR_SC3_CALF(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ADC_SC3, field CAL[7] (RW)
+ *
+ * Begins the calibration sequence when set. This field stays set while the
+ * calibration is in progress and is cleared when the calibration sequence is
+ * completed. CALF must be checked to determine the result of the calibration sequence.
+ * Once started, the calibration routine cannot be interrupted by writes to the
+ * ADC registers or the results will be invalid and CALF will set. Setting CAL
+ * will abort any current conversion.
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_SC3_CAL field. */
+#define ADC_RD_SC3_CAL(base) ((ADC_SC3_REG(base) & ADC_SC3_CAL_MASK) >> ADC_SC3_CAL_SHIFT)
+#define ADC_BRD_SC3_CAL(base) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT))
+
+/*! @brief Set the CAL field to a new value. */
+#define ADC_WR_SC3_CAL(base, value) (ADC_RMW_SC3(base, (ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK), ADC_SC3_CAL(value)))
+#define ADC_BWR_SC3_CAL(base, value) (BITBAND_ACCESS32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_OFS - ADC Offset Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_OFS - ADC Offset Correction Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * The ADC Offset Correction Register (OFS) contains the user-selected or
+ * calibration-generated offset error correction value. This register is a 2's
+ * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
+ * conversion and the result is transferred into the result registers, Rn. If the
+ * result is greater than the maximum or less than the minimum result value, it is
+ * forced to the appropriate limit for the current mode of operation.
+ */
+/*!
+ * @name Constants and macros for entire ADC_OFS register
+ */
+/*@{*/
+#define ADC_RD_OFS(base)         (ADC_OFS_REG(base))
+#define ADC_WR_OFS(base, value)  (ADC_OFS_REG(base) = (value))
+#define ADC_RMW_OFS(base, mask, value) (ADC_WR_OFS(base, (ADC_RD_OFS(base) & ~(mask)) | (value)))
+#define ADC_SET_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) |  (value)))
+#define ADC_CLR_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) & ~(value)))
+#define ADC_TOG_OFS(base, value) (ADC_WR_OFS(base, ADC_RD_OFS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_OFS bitfields
+ */
+
+/*!
+ * @name Register ADC_OFS, field OFS[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_OFS_OFS field. */
+#define ADC_RD_OFS_OFS(base) ((ADC_OFS_REG(base) & ADC_OFS_OFS_MASK) >> ADC_OFS_OFS_SHIFT)
+#define ADC_BRD_OFS_OFS(base) (ADC_RD_OFS_OFS(base))
+
+/*! @brief Set the OFS field to a new value. */
+#define ADC_WR_OFS_OFS(base, value) (ADC_RMW_OFS(base, ADC_OFS_OFS_MASK, ADC_OFS_OFS(value)))
+#define ADC_BWR_OFS_OFS(base, value) (ADC_WR_OFS_OFS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_PG - ADC Plus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_PG - ADC Plus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Plus-Side Gain Register (PG) contains the gain error correction for the
+ * plus-side input in differential mode or the overall conversion in single-ended
+ * mode. PG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
+ * written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_PG register
+ */
+/*@{*/
+#define ADC_RD_PG(base)          (ADC_PG_REG(base))
+#define ADC_WR_PG(base, value)   (ADC_PG_REG(base) = (value))
+#define ADC_RMW_PG(base, mask, value) (ADC_WR_PG(base, (ADC_RD_PG(base) & ~(mask)) | (value)))
+#define ADC_SET_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) |  (value)))
+#define ADC_CLR_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) & ~(value)))
+#define ADC_TOG_PG(base, value)  (ADC_WR_PG(base, ADC_RD_PG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_PG bitfields
+ */
+
+/*!
+ * @name Register ADC_PG, field PG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_PG_PG field. */
+#define ADC_RD_PG_PG(base)   ((ADC_PG_REG(base) & ADC_PG_PG_MASK) >> ADC_PG_PG_SHIFT)
+#define ADC_BRD_PG_PG(base)  (ADC_RD_PG_PG(base))
+
+/*! @brief Set the PG field to a new value. */
+#define ADC_WR_PG_PG(base, value) (ADC_RMW_PG(base, ADC_PG_PG_MASK, ADC_PG_PG(value)))
+#define ADC_BWR_PG_PG(base, value) (ADC_WR_PG_PG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_MG - ADC Minus-Side Gain Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_MG - ADC Minus-Side Gain Register (RW)
+ *
+ * Reset value: 0x00008200U
+ *
+ * The Minus-Side Gain Register (MG) contains the gain error correction for the
+ * minus-side input in differential mode. This register is ignored in
+ * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
+ * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
+ * be written by the user with the value described in the calibration procedure.
+ * Otherwise, the gain error specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_MG register
+ */
+/*@{*/
+#define ADC_RD_MG(base)          (ADC_MG_REG(base))
+#define ADC_WR_MG(base, value)   (ADC_MG_REG(base) = (value))
+#define ADC_RMW_MG(base, mask, value) (ADC_WR_MG(base, (ADC_RD_MG(base) & ~(mask)) | (value)))
+#define ADC_SET_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) |  (value)))
+#define ADC_CLR_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) & ~(value)))
+#define ADC_TOG_MG(base, value)  (ADC_WR_MG(base, ADC_RD_MG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_MG bitfields
+ */
+
+/*!
+ * @name Register ADC_MG, field MG[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_MG_MG field. */
+#define ADC_RD_MG_MG(base)   ((ADC_MG_REG(base) & ADC_MG_MG_MASK) >> ADC_MG_MG_SHIFT)
+#define ADC_BRD_MG_MG(base)  (ADC_RD_MG_MG(base))
+
+/*! @brief Set the MG field to a new value. */
+#define ADC_WR_MG_MG(base, value) (ADC_RMW_MG(base, ADC_MG_MG_MASK, ADC_MG_MG(value)))
+#define ADC_BWR_MG_MG(base, value) (ADC_WR_MG_MG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPD - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
+ * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
+ * when the self-calibration sequence is done, that is, CAL is cleared. If these
+ * registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPD register
+ */
+/*@{*/
+#define ADC_RD_CLPD(base)        (ADC_CLPD_REG(base))
+#define ADC_WR_CLPD(base, value) (ADC_CLPD_REG(base) = (value))
+#define ADC_RMW_CLPD(base, mask, value) (ADC_WR_CLPD(base, (ADC_RD_CLPD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) |  (value)))
+#define ADC_CLR_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) & ~(value)))
+#define ADC_TOG_CLPD(base, value) (ADC_WR_CLPD(base, ADC_RD_CLPD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPD, field CLPD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPD_CLPD field. */
+#define ADC_RD_CLPD_CLPD(base) ((ADC_CLPD_REG(base) & ADC_CLPD_CLPD_MASK) >> ADC_CLPD_CLPD_SHIFT)
+#define ADC_BRD_CLPD_CLPD(base) (ADC_RD_CLPD_CLPD(base))
+
+/*! @brief Set the CLPD field to a new value. */
+#define ADC_WR_CLPD_CLPD(base, value) (ADC_RMW_CLPD(base, ADC_CLPD_CLPD_MASK, ADC_CLPD_CLPD(value)))
+#define ADC_BWR_CLPD_CLPD(base, value) (ADC_WR_CLPD_CLPD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLPS - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLPS register
+ */
+/*@{*/
+#define ADC_RD_CLPS(base)        (ADC_CLPS_REG(base))
+#define ADC_WR_CLPS(base, value) (ADC_CLPS_REG(base) = (value))
+#define ADC_RMW_CLPS(base, mask, value) (ADC_WR_CLPS(base, (ADC_RD_CLPS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) |  (value)))
+#define ADC_CLR_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) & ~(value)))
+#define ADC_TOG_CLPS(base, value) (ADC_WR_CLPS(base, ADC_RD_CLPS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLPS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLPS, field CLPS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLPS_CLPS field. */
+#define ADC_RD_CLPS_CLPS(base) ((ADC_CLPS_REG(base) & ADC_CLPS_CLPS_MASK) >> ADC_CLPS_CLPS_SHIFT)
+#define ADC_BRD_CLPS_CLPS(base) (ADC_RD_CLPS_CLPS(base))
+
+/*! @brief Set the CLPS field to a new value. */
+#define ADC_WR_CLPS_CLPS(base, value) (ADC_RMW_CLPS(base, ADC_CLPS_CLPS_MASK, ADC_CLPS_CLPS(value)))
+#define ADC_BWR_CLPS_CLPS(base, value) (ADC_WR_CLPS_CLPS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP4 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP4 register
+ */
+/*@{*/
+#define ADC_RD_CLP4(base)        (ADC_CLP4_REG(base))
+#define ADC_WR_CLP4(base, value) (ADC_CLP4_REG(base) = (value))
+#define ADC_RMW_CLP4(base, mask, value) (ADC_WR_CLP4(base, (ADC_RD_CLP4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) |  (value)))
+#define ADC_CLR_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) & ~(value)))
+#define ADC_TOG_CLP4(base, value) (ADC_WR_CLP4(base, ADC_RD_CLP4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP4, field CLP4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP4_CLP4 field. */
+#define ADC_RD_CLP4_CLP4(base) ((ADC_CLP4_REG(base) & ADC_CLP4_CLP4_MASK) >> ADC_CLP4_CLP4_SHIFT)
+#define ADC_BRD_CLP4_CLP4(base) (ADC_RD_CLP4_CLP4(base))
+
+/*! @brief Set the CLP4 field to a new value. */
+#define ADC_WR_CLP4_CLP4(base, value) (ADC_RMW_CLP4(base, ADC_CLP4_CLP4_MASK, ADC_CLP4_CLP4(value)))
+#define ADC_BWR_CLP4_CLP4(base, value) (ADC_WR_CLP4_CLP4(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP3 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP3 register
+ */
+/*@{*/
+#define ADC_RD_CLP3(base)        (ADC_CLP3_REG(base))
+#define ADC_WR_CLP3(base, value) (ADC_CLP3_REG(base) = (value))
+#define ADC_RMW_CLP3(base, mask, value) (ADC_WR_CLP3(base, (ADC_RD_CLP3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) |  (value)))
+#define ADC_CLR_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) & ~(value)))
+#define ADC_TOG_CLP3(base, value) (ADC_WR_CLP3(base, ADC_RD_CLP3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP3, field CLP3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP3_CLP3 field. */
+#define ADC_RD_CLP3_CLP3(base) ((ADC_CLP3_REG(base) & ADC_CLP3_CLP3_MASK) >> ADC_CLP3_CLP3_SHIFT)
+#define ADC_BRD_CLP3_CLP3(base) (ADC_RD_CLP3_CLP3(base))
+
+/*! @brief Set the CLP3 field to a new value. */
+#define ADC_WR_CLP3_CLP3(base, value) (ADC_RMW_CLP3(base, ADC_CLP3_CLP3_MASK, ADC_CLP3_CLP3(value)))
+#define ADC_BWR_CLP3_CLP3(base, value) (ADC_WR_CLP3_CLP3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP2 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP2 register
+ */
+/*@{*/
+#define ADC_RD_CLP2(base)        (ADC_CLP2_REG(base))
+#define ADC_WR_CLP2(base, value) (ADC_CLP2_REG(base) = (value))
+#define ADC_RMW_CLP2(base, mask, value) (ADC_WR_CLP2(base, (ADC_RD_CLP2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) |  (value)))
+#define ADC_CLR_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) & ~(value)))
+#define ADC_TOG_CLP2(base, value) (ADC_WR_CLP2(base, ADC_RD_CLP2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP2, field CLP2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP2_CLP2 field. */
+#define ADC_RD_CLP2_CLP2(base) ((ADC_CLP2_REG(base) & ADC_CLP2_CLP2_MASK) >> ADC_CLP2_CLP2_SHIFT)
+#define ADC_BRD_CLP2_CLP2(base) (ADC_RD_CLP2_CLP2(base))
+
+/*! @brief Set the CLP2 field to a new value. */
+#define ADC_WR_CLP2_CLP2(base, value) (ADC_RMW_CLP2(base, ADC_CLP2_CLP2_MASK, ADC_CLP2_CLP2(value)))
+#define ADC_BWR_CLP2_CLP2(base, value) (ADC_WR_CLP2_CLP2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP1 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP1 register
+ */
+/*@{*/
+#define ADC_RD_CLP1(base)        (ADC_CLP1_REG(base))
+#define ADC_WR_CLP1(base, value) (ADC_CLP1_REG(base) = (value))
+#define ADC_RMW_CLP1(base, mask, value) (ADC_WR_CLP1(base, (ADC_RD_CLP1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) |  (value)))
+#define ADC_CLR_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) & ~(value)))
+#define ADC_TOG_CLP1(base, value) (ADC_WR_CLP1(base, ADC_RD_CLP1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP1, field CLP1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP1_CLP1 field. */
+#define ADC_RD_CLP1_CLP1(base) ((ADC_CLP1_REG(base) & ADC_CLP1_CLP1_MASK) >> ADC_CLP1_CLP1_SHIFT)
+#define ADC_BRD_CLP1_CLP1(base) (ADC_RD_CLP1_CLP1(base))
+
+/*! @brief Set the CLP1 field to a new value. */
+#define ADC_WR_CLP1_CLP1(base, value) (ADC_RMW_CLP1(base, ADC_CLP1_CLP1_MASK, ADC_CLP1_CLP1(value)))
+#define ADC_BWR_CLP1_CLP1(base, value) (ADC_WR_CLP1_CLP1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLP0 - ADC Plus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLPD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLP0 register
+ */
+/*@{*/
+#define ADC_RD_CLP0(base)        (ADC_CLP0_REG(base))
+#define ADC_WR_CLP0(base, value) (ADC_CLP0_REG(base) = (value))
+#define ADC_RMW_CLP0(base, mask, value) (ADC_WR_CLP0(base, (ADC_RD_CLP0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) |  (value)))
+#define ADC_CLR_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) & ~(value)))
+#define ADC_TOG_CLP0(base, value) (ADC_WR_CLP0(base, ADC_RD_CLP0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLP0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLP0, field CLP0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLP0_CLP0 field. */
+#define ADC_RD_CLP0_CLP0(base) ((ADC_CLP0_REG(base) & ADC_CLP0_CLP0_MASK) >> ADC_CLP0_CLP0_SHIFT)
+#define ADC_BRD_CLP0_CLP0(base) (ADC_RD_CLP0_CLP0(base))
+
+/*! @brief Set the CLP0 field to a new value. */
+#define ADC_WR_CLP0_CLP0(base, value) (ADC_RMW_CLP0(base, ADC_CLP0_CLP0_MASK, ADC_CLP0_CLP0(value)))
+#define ADC_BWR_CLP0_CLP0(base, value) (ADC_WR_CLP0_CLP0(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMD - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x0000000AU
+ *
+ * The Minus-Side General Calibration Value (CLMx) registers contain calibration
+ * information that is generated by the calibration function. These registers
+ * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
+ * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
+ * set when the self-calibration sequence is done, that is, CAL is cleared. If
+ * these registers are written by the user after calibration, the linearity error
+ * specifications may not be met.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMD register
+ */
+/*@{*/
+#define ADC_RD_CLMD(base)        (ADC_CLMD_REG(base))
+#define ADC_WR_CLMD(base, value) (ADC_CLMD_REG(base) = (value))
+#define ADC_RMW_CLMD(base, mask, value) (ADC_WR_CLMD(base, (ADC_RD_CLMD(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) |  (value)))
+#define ADC_CLR_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) & ~(value)))
+#define ADC_TOG_CLMD(base, value) (ADC_WR_CLMD(base, ADC_RD_CLMD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMD bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMD, field CLMD[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMD_CLMD field. */
+#define ADC_RD_CLMD_CLMD(base) ((ADC_CLMD_REG(base) & ADC_CLMD_CLMD_MASK) >> ADC_CLMD_CLMD_SHIFT)
+#define ADC_BRD_CLMD_CLMD(base) (ADC_RD_CLMD_CLMD(base))
+
+/*! @brief Set the CLMD field to a new value. */
+#define ADC_WR_CLMD_CLMD(base, value) (ADC_RMW_CLMD(base, ADC_CLMD_CLMD_MASK, ADC_CLMD_CLMD(value)))
+#define ADC_BWR_CLMD_CLMD(base, value) (ADC_WR_CLMD_CLMD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLMS - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLMS register
+ */
+/*@{*/
+#define ADC_RD_CLMS(base)        (ADC_CLMS_REG(base))
+#define ADC_WR_CLMS(base, value) (ADC_CLMS_REG(base) = (value))
+#define ADC_RMW_CLMS(base, mask, value) (ADC_WR_CLMS(base, (ADC_RD_CLMS(base) & ~(mask)) | (value)))
+#define ADC_SET_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) |  (value)))
+#define ADC_CLR_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) & ~(value)))
+#define ADC_TOG_CLMS(base, value) (ADC_WR_CLMS(base, ADC_RD_CLMS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLMS bitfields
+ */
+
+/*!
+ * @name Register ADC_CLMS, field CLMS[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLMS_CLMS field. */
+#define ADC_RD_CLMS_CLMS(base) ((ADC_CLMS_REG(base) & ADC_CLMS_CLMS_MASK) >> ADC_CLMS_CLMS_SHIFT)
+#define ADC_BRD_CLMS_CLMS(base) (ADC_RD_CLMS_CLMS(base))
+
+/*! @brief Set the CLMS field to a new value. */
+#define ADC_WR_CLMS_CLMS(base, value) (ADC_RMW_CLMS(base, ADC_CLMS_CLMS_MASK, ADC_CLMS_CLMS(value)))
+#define ADC_BWR_CLMS_CLMS(base, value) (ADC_WR_CLMS_CLMS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM4 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000200U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM4 register
+ */
+/*@{*/
+#define ADC_RD_CLM4(base)        (ADC_CLM4_REG(base))
+#define ADC_WR_CLM4(base, value) (ADC_CLM4_REG(base) = (value))
+#define ADC_RMW_CLM4(base, mask, value) (ADC_WR_CLM4(base, (ADC_RD_CLM4(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) |  (value)))
+#define ADC_CLR_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) & ~(value)))
+#define ADC_TOG_CLM4(base, value) (ADC_WR_CLM4(base, ADC_RD_CLM4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM4 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM4, field CLM4[9:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM4_CLM4 field. */
+#define ADC_RD_CLM4_CLM4(base) ((ADC_CLM4_REG(base) & ADC_CLM4_CLM4_MASK) >> ADC_CLM4_CLM4_SHIFT)
+#define ADC_BRD_CLM4_CLM4(base) (ADC_RD_CLM4_CLM4(base))
+
+/*! @brief Set the CLM4 field to a new value. */
+#define ADC_WR_CLM4_CLM4(base, value) (ADC_RMW_CLM4(base, ADC_CLM4_CLM4_MASK, ADC_CLM4_CLM4(value)))
+#define ADC_BWR_CLM4_CLM4(base, value) (ADC_WR_CLM4_CLM4(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM3 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000100U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM3 register
+ */
+/*@{*/
+#define ADC_RD_CLM3(base)        (ADC_CLM3_REG(base))
+#define ADC_WR_CLM3(base, value) (ADC_CLM3_REG(base) = (value))
+#define ADC_RMW_CLM3(base, mask, value) (ADC_WR_CLM3(base, (ADC_RD_CLM3(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) |  (value)))
+#define ADC_CLR_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) & ~(value)))
+#define ADC_TOG_CLM3(base, value) (ADC_WR_CLM3(base, ADC_RD_CLM3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM3 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM3, field CLM3[8:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM3_CLM3 field. */
+#define ADC_RD_CLM3_CLM3(base) ((ADC_CLM3_REG(base) & ADC_CLM3_CLM3_MASK) >> ADC_CLM3_CLM3_SHIFT)
+#define ADC_BRD_CLM3_CLM3(base) (ADC_RD_CLM3_CLM3(base))
+
+/*! @brief Set the CLM3 field to a new value. */
+#define ADC_WR_CLM3_CLM3(base, value) (ADC_RMW_CLM3(base, ADC_CLM3_CLM3_MASK, ADC_CLM3_CLM3(value)))
+#define ADC_BWR_CLM3_CLM3(base, value) (ADC_WR_CLM3_CLM3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM2 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000080U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM2 register
+ */
+/*@{*/
+#define ADC_RD_CLM2(base)        (ADC_CLM2_REG(base))
+#define ADC_WR_CLM2(base, value) (ADC_CLM2_REG(base) = (value))
+#define ADC_RMW_CLM2(base, mask, value) (ADC_WR_CLM2(base, (ADC_RD_CLM2(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) |  (value)))
+#define ADC_CLR_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) & ~(value)))
+#define ADC_TOG_CLM2(base, value) (ADC_WR_CLM2(base, ADC_RD_CLM2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM2 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM2, field CLM2[7:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM2_CLM2 field. */
+#define ADC_RD_CLM2_CLM2(base) ((ADC_CLM2_REG(base) & ADC_CLM2_CLM2_MASK) >> ADC_CLM2_CLM2_SHIFT)
+#define ADC_BRD_CLM2_CLM2(base) (ADC_RD_CLM2_CLM2(base))
+
+/*! @brief Set the CLM2 field to a new value. */
+#define ADC_WR_CLM2_CLM2(base, value) (ADC_RMW_CLM2(base, ADC_CLM2_CLM2_MASK, ADC_CLM2_CLM2(value)))
+#define ADC_BWR_CLM2_CLM2(base, value) (ADC_WR_CLM2_CLM2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM1 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000040U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM1 register
+ */
+/*@{*/
+#define ADC_RD_CLM1(base)        (ADC_CLM1_REG(base))
+#define ADC_WR_CLM1(base, value) (ADC_CLM1_REG(base) = (value))
+#define ADC_RMW_CLM1(base, mask, value) (ADC_WR_CLM1(base, (ADC_RD_CLM1(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) |  (value)))
+#define ADC_CLR_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) & ~(value)))
+#define ADC_TOG_CLM1(base, value) (ADC_WR_CLM1(base, ADC_RD_CLM1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM1 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM1, field CLM1[6:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM1_CLM1 field. */
+#define ADC_RD_CLM1_CLM1(base) ((ADC_CLM1_REG(base) & ADC_CLM1_CLM1_MASK) >> ADC_CLM1_CLM1_SHIFT)
+#define ADC_BRD_CLM1_CLM1(base) (ADC_RD_CLM1_CLM1(base))
+
+/*! @brief Set the CLM1 field to a new value. */
+#define ADC_WR_CLM1_CLM1(base, value) (ADC_RMW_CLM1(base, ADC_CLM1_CLM1_MASK, ADC_CLM1_CLM1(value)))
+#define ADC_BWR_CLM1_CLM1(base, value) (ADC_WR_CLM1_CLM1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ADC_CLM0 - ADC Minus-Side General Calibration Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * For more information, see CLMD register description.
+ */
+/*!
+ * @name Constants and macros for entire ADC_CLM0 register
+ */
+/*@{*/
+#define ADC_RD_CLM0(base)        (ADC_CLM0_REG(base))
+#define ADC_WR_CLM0(base, value) (ADC_CLM0_REG(base) = (value))
+#define ADC_RMW_CLM0(base, mask, value) (ADC_WR_CLM0(base, (ADC_RD_CLM0(base) & ~(mask)) | (value)))
+#define ADC_SET_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) |  (value)))
+#define ADC_CLR_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) & ~(value)))
+#define ADC_TOG_CLM0(base, value) (ADC_WR_CLM0(base, ADC_RD_CLM0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ADC_CLM0 bitfields
+ */
+
+/*!
+ * @name Register ADC_CLM0, field CLM0[5:0] (RW)
+ *
+ * Calibration Value
+ */
+/*@{*/
+/*! @brief Read current value of the ADC_CLM0_CLM0 field. */
+#define ADC_RD_CLM0_CLM0(base) ((ADC_CLM0_REG(base) & ADC_CLM0_CLM0_MASK) >> ADC_CLM0_CLM0_SHIFT)
+#define ADC_BRD_CLM0_CLM0(base) (ADC_RD_CLM0_CLM0(base))
+
+/*! @brief Set the CLM0 field to a new value. */
+#define ADC_WR_CLM0_CLM0(base, value) (ADC_RMW_CLM0(base, ADC_CLM0_CLM0_MASK, ADC_CLM0_CLM0(value)))
+#define ADC_BWR_CLM0_CLM0(base, value) (ADC_WR_CLM0_CLM0(base, value))
+/*@}*/
+
+/*
+ * MK64F12 AIPS
+ *
+ * AIPS-Lite Bridge
+ *
+ * Registers defined in this header file:
+ * - AIPS_MPRA - Master Privilege Register A
+ * - AIPS_PACRA - Peripheral Access Control Register
+ * - AIPS_PACRB - Peripheral Access Control Register
+ * - AIPS_PACRC - Peripheral Access Control Register
+ * - AIPS_PACRD - Peripheral Access Control Register
+ * - AIPS_PACRE - Peripheral Access Control Register
+ * - AIPS_PACRF - Peripheral Access Control Register
+ * - AIPS_PACRG - Peripheral Access Control Register
+ * - AIPS_PACRH - Peripheral Access Control Register
+ * - AIPS_PACRI - Peripheral Access Control Register
+ * - AIPS_PACRJ - Peripheral Access Control Register
+ * - AIPS_PACRK - Peripheral Access Control Register
+ * - AIPS_PACRL - Peripheral Access Control Register
+ * - AIPS_PACRM - Peripheral Access Control Register
+ * - AIPS_PACRN - Peripheral Access Control Register
+ * - AIPS_PACRO - Peripheral Access Control Register
+ * - AIPS_PACRP - Peripheral Access Control Register
+ * - AIPS_PACRU - Peripheral Access Control Register
+ */
+
+#define AIPS_INSTANCE_COUNT (2U) /*!< Number of instances of the AIPS module. */
+#define AIPS0_IDX (0U) /*!< Instance number for AIPS0. */
+#define AIPS1_IDX (1U) /*!< Instance number for AIPS1. */
+
+/*******************************************************************************
+ * AIPS_MPRA - Master Privilege Register A
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_MPRA - Master Privilege Register A (RW)
+ *
+ * Reset value: 0x77700000U
+ *
+ * The MPRA specifies identical 4-bit fields defining the access-privilege level
+ * associated with a bus master to various peripherals on the chip. The register
+ * provides one field per bus master. At reset, the default value loaded into
+ * the MPRA fields is chip-specific. See the chip configuration details for the
+ * value of a particular device. A register field that maps to an unimplemented
+ * master or peripheral behaves as read-only-zero. Each master is assigned a logical
+ * ID from 0 to 15. See the master logical ID assignment table in the
+ * chip-specific AIPS information.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_MPRA register
+ */
+/*@{*/
+#define AIPS_RD_MPRA(base)       (AIPS_MPRA_REG(base))
+#define AIPS_WR_MPRA(base, value) (AIPS_MPRA_REG(base) = (value))
+#define AIPS_RMW_MPRA(base, mask, value) (AIPS_WR_MPRA(base, (AIPS_RD_MPRA(base) & ~(mask)) | (value)))
+#define AIPS_SET_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) |  (value)))
+#define AIPS_CLR_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) & ~(value)))
+#define AIPS_TOG_MPRA(base, value) (AIPS_WR_MPRA(base, AIPS_RD_MPRA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_MPRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_MPRA, field MPL5[8] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL5 field. */
+#define AIPS_RD_MPRA_MPL5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL5_MASK) >> AIPS_MPRA_MPL5_SHIFT)
+#define AIPS_BRD_MPRA_MPL5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL5_SHIFT))
+
+/*! @brief Set the MPL5 field to a new value. */
+#define AIPS_WR_MPRA_MPL5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL5_MASK, AIPS_MPRA_MPL5(value)))
+#define AIPS_BWR_MPRA_MPL5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW5[9] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW5 field. */
+#define AIPS_RD_MPRA_MTW5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW5_MASK) >> AIPS_MPRA_MTW5_SHIFT)
+#define AIPS_BRD_MPRA_MTW5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW5_SHIFT))
+
+/*! @brief Set the MTW5 field to a new value. */
+#define AIPS_WR_MPRA_MTW5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW5_MASK, AIPS_MPRA_MTW5(value)))
+#define AIPS_BWR_MPRA_MTW5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR5[10] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR5 field. */
+#define AIPS_RD_MPRA_MTR5(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR5_MASK) >> AIPS_MPRA_MTR5_SHIFT)
+#define AIPS_BRD_MPRA_MTR5(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR5_SHIFT))
+
+/*! @brief Set the MTR5 field to a new value. */
+#define AIPS_WR_MPRA_MTR5(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR5_MASK, AIPS_MPRA_MTR5(value)))
+#define AIPS_BWR_MPRA_MTR5(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL4[12] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL4 field. */
+#define AIPS_RD_MPRA_MPL4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL4_MASK) >> AIPS_MPRA_MPL4_SHIFT)
+#define AIPS_BRD_MPRA_MPL4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL4_SHIFT))
+
+/*! @brief Set the MPL4 field to a new value. */
+#define AIPS_WR_MPRA_MPL4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL4_MASK, AIPS_MPRA_MPL4(value)))
+#define AIPS_BWR_MPRA_MPL4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW4[13] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW4 field. */
+#define AIPS_RD_MPRA_MTW4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW4_MASK) >> AIPS_MPRA_MTW4_SHIFT)
+#define AIPS_BRD_MPRA_MTW4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW4_SHIFT))
+
+/*! @brief Set the MTW4 field to a new value. */
+#define AIPS_WR_MPRA_MTW4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW4_MASK, AIPS_MPRA_MTW4(value)))
+#define AIPS_BWR_MPRA_MTW4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR4[14] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR4 field. */
+#define AIPS_RD_MPRA_MTR4(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR4_MASK) >> AIPS_MPRA_MTR4_SHIFT)
+#define AIPS_BRD_MPRA_MTR4(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR4_SHIFT))
+
+/*! @brief Set the MTR4 field to a new value. */
+#define AIPS_WR_MPRA_MTR4(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR4_MASK, AIPS_MPRA_MTR4(value)))
+#define AIPS_BWR_MPRA_MTR4(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL3[16] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL3 field. */
+#define AIPS_RD_MPRA_MPL3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL3_MASK) >> AIPS_MPRA_MPL3_SHIFT)
+#define AIPS_BRD_MPRA_MPL3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL3_SHIFT))
+
+/*! @brief Set the MPL3 field to a new value. */
+#define AIPS_WR_MPRA_MPL3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL3_MASK, AIPS_MPRA_MPL3(value)))
+#define AIPS_BWR_MPRA_MPL3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW3[17] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW3 field. */
+#define AIPS_RD_MPRA_MTW3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW3_MASK) >> AIPS_MPRA_MTW3_SHIFT)
+#define AIPS_BRD_MPRA_MTW3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW3_SHIFT))
+
+/*! @brief Set the MTW3 field to a new value. */
+#define AIPS_WR_MPRA_MTW3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW3_MASK, AIPS_MPRA_MTW3(value)))
+#define AIPS_BWR_MPRA_MTW3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR3[18] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR3 field. */
+#define AIPS_RD_MPRA_MTR3(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR3_MASK) >> AIPS_MPRA_MTR3_SHIFT)
+#define AIPS_BRD_MPRA_MTR3(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR3_SHIFT))
+
+/*! @brief Set the MTR3 field to a new value. */
+#define AIPS_WR_MPRA_MTR3(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR3_MASK, AIPS_MPRA_MTR3(value)))
+#define AIPS_BWR_MPRA_MTR3(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL2[20] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL2 field. */
+#define AIPS_RD_MPRA_MPL2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL2_MASK) >> AIPS_MPRA_MPL2_SHIFT)
+#define AIPS_BRD_MPRA_MPL2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL2_SHIFT))
+
+/*! @brief Set the MPL2 field to a new value. */
+#define AIPS_WR_MPRA_MPL2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL2_MASK, AIPS_MPRA_MPL2(value)))
+#define AIPS_BWR_MPRA_MPL2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW2[21] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW2 field. */
+#define AIPS_RD_MPRA_MTW2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW2_MASK) >> AIPS_MPRA_MTW2_SHIFT)
+#define AIPS_BRD_MPRA_MTW2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW2_SHIFT))
+
+/*! @brief Set the MTW2 field to a new value. */
+#define AIPS_WR_MPRA_MTW2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW2_MASK, AIPS_MPRA_MTW2(value)))
+#define AIPS_BWR_MPRA_MTW2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR2[22] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR2 field. */
+#define AIPS_RD_MPRA_MTR2(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR2_MASK) >> AIPS_MPRA_MTR2_SHIFT)
+#define AIPS_BRD_MPRA_MTR2(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR2_SHIFT))
+
+/*! @brief Set the MTR2 field to a new value. */
+#define AIPS_WR_MPRA_MTR2(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR2_MASK, AIPS_MPRA_MTR2(value)))
+#define AIPS_BWR_MPRA_MTR2(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL1[24] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL1 field. */
+#define AIPS_RD_MPRA_MPL1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL1_MASK) >> AIPS_MPRA_MPL1_SHIFT)
+#define AIPS_BRD_MPRA_MPL1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL1_SHIFT))
+
+/*! @brief Set the MPL1 field to a new value. */
+#define AIPS_WR_MPRA_MPL1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL1_MASK, AIPS_MPRA_MPL1(value)))
+#define AIPS_BWR_MPRA_MPL1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW1[25] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW1 field. */
+#define AIPS_RD_MPRA_MTW1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW1_MASK) >> AIPS_MPRA_MTW1_SHIFT)
+#define AIPS_BRD_MPRA_MTW1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW1_SHIFT))
+
+/*! @brief Set the MTW1 field to a new value. */
+#define AIPS_WR_MPRA_MTW1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW1_MASK, AIPS_MPRA_MTW1(value)))
+#define AIPS_BWR_MPRA_MTW1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR1[26] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR1 field. */
+#define AIPS_RD_MPRA_MTR1(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR1_MASK) >> AIPS_MPRA_MTR1_SHIFT)
+#define AIPS_BRD_MPRA_MTR1(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR1_SHIFT))
+
+/*! @brief Set the MTR1 field to a new value. */
+#define AIPS_WR_MPRA_MTR1(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR1_MASK, AIPS_MPRA_MTR1(value)))
+#define AIPS_BWR_MPRA_MTR1(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MPL0[28] (RW)
+ *
+ * Specifies how the privilege level of the master is determined.
+ *
+ * Values:
+ * - 0b0 - Accesses from this master are forced to user-mode.
+ * - 0b1 - Accesses from this master are not forced to user-mode.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MPL0 field. */
+#define AIPS_RD_MPRA_MPL0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MPL0_MASK) >> AIPS_MPRA_MPL0_SHIFT)
+#define AIPS_BRD_MPRA_MPL0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL0_SHIFT))
+
+/*! @brief Set the MPL0 field to a new value. */
+#define AIPS_WR_MPRA_MPL0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MPL0_MASK, AIPS_MPRA_MPL0(value)))
+#define AIPS_BWR_MPRA_MPL0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MPL0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTW0[29] (RW)
+ *
+ * Determines whether the master is trusted for write accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for write accesses.
+ * - 0b1 - This master is trusted for write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTW0 field. */
+#define AIPS_RD_MPRA_MTW0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTW0_MASK) >> AIPS_MPRA_MTW0_SHIFT)
+#define AIPS_BRD_MPRA_MTW0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW0_SHIFT))
+
+/*! @brief Set the MTW0 field to a new value. */
+#define AIPS_WR_MPRA_MTW0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTW0_MASK, AIPS_MPRA_MTW0(value)))
+#define AIPS_BWR_MPRA_MTW0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTW0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_MPRA, field MTR0[30] (RW)
+ *
+ * Determines whether the master is trusted for read accesses.
+ *
+ * Values:
+ * - 0b0 - This master is not trusted for read accesses.
+ * - 0b1 - This master is trusted for read accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_MPRA_MTR0 field. */
+#define AIPS_RD_MPRA_MTR0(base) ((AIPS_MPRA_REG(base) & AIPS_MPRA_MTR0_MASK) >> AIPS_MPRA_MTR0_SHIFT)
+#define AIPS_BRD_MPRA_MTR0(base) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR0_SHIFT))
+
+/*! @brief Set the MTR0 field to a new value. */
+#define AIPS_WR_MPRA_MTR0(base, value) (AIPS_RMW_MPRA(base, AIPS_MPRA_MTR0_MASK, AIPS_MPRA_MTR0(value)))
+#define AIPS_BWR_MPRA_MTR0(base, value) (BITBAND_ACCESS32(&AIPS_MPRA_REG(base), AIPS_MPRA_MTR0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRA - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRA - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x50004000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRA register
+ */
+/*@{*/
+#define AIPS_RD_PACRA(base)      (AIPS_PACRA_REG(base))
+#define AIPS_WR_PACRA(base, value) (AIPS_PACRA_REG(base) = (value))
+#define AIPS_RMW_PACRA(base, mask, value) (AIPS_WR_PACRA(base, (AIPS_RD_PACRA(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) |  (value)))
+#define AIPS_CLR_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) & ~(value)))
+#define AIPS_TOG_PACRA(base, value) (AIPS_WR_PACRA(base, AIPS_RD_PACRA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRA bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRA, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP7 field. */
+#define AIPS_RD_PACRA_TP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP7_MASK) >> AIPS_PACRA_TP7_SHIFT)
+#define AIPS_BRD_PACRA_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRA_TP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP7_MASK, AIPS_PACRA_TP7(value)))
+#define AIPS_BWR_PACRA_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP7 field. */
+#define AIPS_RD_PACRA_WP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP7_MASK) >> AIPS_PACRA_WP7_SHIFT)
+#define AIPS_BRD_PACRA_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRA_WP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP7_MASK, AIPS_PACRA_WP7(value)))
+#define AIPS_BWR_PACRA_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP7 field. */
+#define AIPS_RD_PACRA_SP7(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP7_MASK) >> AIPS_PACRA_SP7_SHIFT)
+#define AIPS_BRD_PACRA_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRA_SP7(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP7_MASK, AIPS_PACRA_SP7(value)))
+#define AIPS_BWR_PACRA_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP6 field. */
+#define AIPS_RD_PACRA_TP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP6_MASK) >> AIPS_PACRA_TP6_SHIFT)
+#define AIPS_BRD_PACRA_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRA_TP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP6_MASK, AIPS_PACRA_TP6(value)))
+#define AIPS_BWR_PACRA_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP6 field. */
+#define AIPS_RD_PACRA_WP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP6_MASK) >> AIPS_PACRA_WP6_SHIFT)
+#define AIPS_BRD_PACRA_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRA_WP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP6_MASK, AIPS_PACRA_WP6(value)))
+#define AIPS_BWR_PACRA_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP6 field. */
+#define AIPS_RD_PACRA_SP6(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP6_MASK) >> AIPS_PACRA_SP6_SHIFT)
+#define AIPS_BRD_PACRA_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRA_SP6(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP6_MASK, AIPS_PACRA_SP6(value)))
+#define AIPS_BWR_PACRA_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP5 field. */
+#define AIPS_RD_PACRA_TP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP5_MASK) >> AIPS_PACRA_TP5_SHIFT)
+#define AIPS_BRD_PACRA_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRA_TP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP5_MASK, AIPS_PACRA_TP5(value)))
+#define AIPS_BWR_PACRA_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP5 field. */
+#define AIPS_RD_PACRA_WP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP5_MASK) >> AIPS_PACRA_WP5_SHIFT)
+#define AIPS_BRD_PACRA_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRA_WP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP5_MASK, AIPS_PACRA_WP5(value)))
+#define AIPS_BWR_PACRA_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP5 field. */
+#define AIPS_RD_PACRA_SP5(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP5_MASK) >> AIPS_PACRA_SP5_SHIFT)
+#define AIPS_BRD_PACRA_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRA_SP5(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP5_MASK, AIPS_PACRA_SP5(value)))
+#define AIPS_BWR_PACRA_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP4 field. */
+#define AIPS_RD_PACRA_TP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP4_MASK) >> AIPS_PACRA_TP4_SHIFT)
+#define AIPS_BRD_PACRA_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRA_TP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP4_MASK, AIPS_PACRA_TP4(value)))
+#define AIPS_BWR_PACRA_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP4 field. */
+#define AIPS_RD_PACRA_WP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP4_MASK) >> AIPS_PACRA_WP4_SHIFT)
+#define AIPS_BRD_PACRA_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRA_WP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP4_MASK, AIPS_PACRA_WP4(value)))
+#define AIPS_BWR_PACRA_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP4 field. */
+#define AIPS_RD_PACRA_SP4(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP4_MASK) >> AIPS_PACRA_SP4_SHIFT)
+#define AIPS_BRD_PACRA_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRA_SP4(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP4_MASK, AIPS_PACRA_SP4(value)))
+#define AIPS_BWR_PACRA_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP3 field. */
+#define AIPS_RD_PACRA_TP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP3_MASK) >> AIPS_PACRA_TP3_SHIFT)
+#define AIPS_BRD_PACRA_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRA_TP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP3_MASK, AIPS_PACRA_TP3(value)))
+#define AIPS_BWR_PACRA_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP3 field. */
+#define AIPS_RD_PACRA_WP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP3_MASK) >> AIPS_PACRA_WP3_SHIFT)
+#define AIPS_BRD_PACRA_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRA_WP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP3_MASK, AIPS_PACRA_WP3(value)))
+#define AIPS_BWR_PACRA_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP3 field. */
+#define AIPS_RD_PACRA_SP3(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP3_MASK) >> AIPS_PACRA_SP3_SHIFT)
+#define AIPS_BRD_PACRA_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRA_SP3(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP3_MASK, AIPS_PACRA_SP3(value)))
+#define AIPS_BWR_PACRA_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP2 field. */
+#define AIPS_RD_PACRA_TP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP2_MASK) >> AIPS_PACRA_TP2_SHIFT)
+#define AIPS_BRD_PACRA_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRA_TP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP2_MASK, AIPS_PACRA_TP2(value)))
+#define AIPS_BWR_PACRA_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP2 field. */
+#define AIPS_RD_PACRA_WP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP2_MASK) >> AIPS_PACRA_WP2_SHIFT)
+#define AIPS_BRD_PACRA_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRA_WP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP2_MASK, AIPS_PACRA_WP2(value)))
+#define AIPS_BWR_PACRA_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP2 field. */
+#define AIPS_RD_PACRA_SP2(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP2_MASK) >> AIPS_PACRA_SP2_SHIFT)
+#define AIPS_BRD_PACRA_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRA_SP2(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP2_MASK, AIPS_PACRA_SP2(value)))
+#define AIPS_BWR_PACRA_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP1 field. */
+#define AIPS_RD_PACRA_TP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP1_MASK) >> AIPS_PACRA_TP1_SHIFT)
+#define AIPS_BRD_PACRA_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRA_TP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP1_MASK, AIPS_PACRA_TP1(value)))
+#define AIPS_BWR_PACRA_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP1 field. */
+#define AIPS_RD_PACRA_WP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP1_MASK) >> AIPS_PACRA_WP1_SHIFT)
+#define AIPS_BRD_PACRA_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRA_WP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP1_MASK, AIPS_PACRA_WP1(value)))
+#define AIPS_BWR_PACRA_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP1 field. */
+#define AIPS_RD_PACRA_SP1(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP1_MASK) >> AIPS_PACRA_SP1_SHIFT)
+#define AIPS_BRD_PACRA_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRA_SP1(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP1_MASK, AIPS_PACRA_SP1(value)))
+#define AIPS_BWR_PACRA_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_TP0 field. */
+#define AIPS_RD_PACRA_TP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_TP0_MASK) >> AIPS_PACRA_TP0_SHIFT)
+#define AIPS_BRD_PACRA_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRA_TP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_TP0_MASK, AIPS_PACRA_TP0(value)))
+#define AIPS_BWR_PACRA_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_WP0 field. */
+#define AIPS_RD_PACRA_WP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_WP0_MASK) >> AIPS_PACRA_WP0_SHIFT)
+#define AIPS_BRD_PACRA_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRA_WP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_WP0_MASK, AIPS_PACRA_WP0(value)))
+#define AIPS_BWR_PACRA_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRA, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRA_SP0 field. */
+#define AIPS_RD_PACRA_SP0(base) ((AIPS_PACRA_REG(base) & AIPS_PACRA_SP0_MASK) >> AIPS_PACRA_SP0_SHIFT)
+#define AIPS_BRD_PACRA_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRA_SP0(base, value) (AIPS_RMW_PACRA(base, AIPS_PACRA_SP0_MASK, AIPS_PACRA_SP0(value)))
+#define AIPS_BWR_PACRA_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRA_REG(base), AIPS_PACRA_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRB - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRB - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44004400U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRB register
+ */
+/*@{*/
+#define AIPS_RD_PACRB(base)      (AIPS_PACRB_REG(base))
+#define AIPS_WR_PACRB(base, value) (AIPS_PACRB_REG(base) = (value))
+#define AIPS_RMW_PACRB(base, mask, value) (AIPS_WR_PACRB(base, (AIPS_RD_PACRB(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) |  (value)))
+#define AIPS_CLR_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) & ~(value)))
+#define AIPS_TOG_PACRB(base, value) (AIPS_WR_PACRB(base, AIPS_RD_PACRB(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRB bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRB, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP7 field. */
+#define AIPS_RD_PACRB_TP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP7_MASK) >> AIPS_PACRB_TP7_SHIFT)
+#define AIPS_BRD_PACRB_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRB_TP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP7_MASK, AIPS_PACRB_TP7(value)))
+#define AIPS_BWR_PACRB_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP7 field. */
+#define AIPS_RD_PACRB_WP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP7_MASK) >> AIPS_PACRB_WP7_SHIFT)
+#define AIPS_BRD_PACRB_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRB_WP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP7_MASK, AIPS_PACRB_WP7(value)))
+#define AIPS_BWR_PACRB_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP7 field. */
+#define AIPS_RD_PACRB_SP7(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP7_MASK) >> AIPS_PACRB_SP7_SHIFT)
+#define AIPS_BRD_PACRB_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRB_SP7(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP7_MASK, AIPS_PACRB_SP7(value)))
+#define AIPS_BWR_PACRB_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP6 field. */
+#define AIPS_RD_PACRB_TP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP6_MASK) >> AIPS_PACRB_TP6_SHIFT)
+#define AIPS_BRD_PACRB_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRB_TP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP6_MASK, AIPS_PACRB_TP6(value)))
+#define AIPS_BWR_PACRB_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP6 field. */
+#define AIPS_RD_PACRB_WP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP6_MASK) >> AIPS_PACRB_WP6_SHIFT)
+#define AIPS_BRD_PACRB_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRB_WP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP6_MASK, AIPS_PACRB_WP6(value)))
+#define AIPS_BWR_PACRB_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP6 field. */
+#define AIPS_RD_PACRB_SP6(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP6_MASK) >> AIPS_PACRB_SP6_SHIFT)
+#define AIPS_BRD_PACRB_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRB_SP6(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP6_MASK, AIPS_PACRB_SP6(value)))
+#define AIPS_BWR_PACRB_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP5 field. */
+#define AIPS_RD_PACRB_TP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP5_MASK) >> AIPS_PACRB_TP5_SHIFT)
+#define AIPS_BRD_PACRB_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRB_TP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP5_MASK, AIPS_PACRB_TP5(value)))
+#define AIPS_BWR_PACRB_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP5 field. */
+#define AIPS_RD_PACRB_WP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP5_MASK) >> AIPS_PACRB_WP5_SHIFT)
+#define AIPS_BRD_PACRB_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRB_WP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP5_MASK, AIPS_PACRB_WP5(value)))
+#define AIPS_BWR_PACRB_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP5 field. */
+#define AIPS_RD_PACRB_SP5(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP5_MASK) >> AIPS_PACRB_SP5_SHIFT)
+#define AIPS_BRD_PACRB_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRB_SP5(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP5_MASK, AIPS_PACRB_SP5(value)))
+#define AIPS_BWR_PACRB_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP4 field. */
+#define AIPS_RD_PACRB_TP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP4_MASK) >> AIPS_PACRB_TP4_SHIFT)
+#define AIPS_BRD_PACRB_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRB_TP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP4_MASK, AIPS_PACRB_TP4(value)))
+#define AIPS_BWR_PACRB_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP4 field. */
+#define AIPS_RD_PACRB_WP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP4_MASK) >> AIPS_PACRB_WP4_SHIFT)
+#define AIPS_BRD_PACRB_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRB_WP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP4_MASK, AIPS_PACRB_WP4(value)))
+#define AIPS_BWR_PACRB_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP4 field. */
+#define AIPS_RD_PACRB_SP4(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP4_MASK) >> AIPS_PACRB_SP4_SHIFT)
+#define AIPS_BRD_PACRB_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRB_SP4(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP4_MASK, AIPS_PACRB_SP4(value)))
+#define AIPS_BWR_PACRB_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP3 field. */
+#define AIPS_RD_PACRB_TP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP3_MASK) >> AIPS_PACRB_TP3_SHIFT)
+#define AIPS_BRD_PACRB_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRB_TP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP3_MASK, AIPS_PACRB_TP3(value)))
+#define AIPS_BWR_PACRB_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP3 field. */
+#define AIPS_RD_PACRB_WP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP3_MASK) >> AIPS_PACRB_WP3_SHIFT)
+#define AIPS_BRD_PACRB_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRB_WP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP3_MASK, AIPS_PACRB_WP3(value)))
+#define AIPS_BWR_PACRB_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP3 field. */
+#define AIPS_RD_PACRB_SP3(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP3_MASK) >> AIPS_PACRB_SP3_SHIFT)
+#define AIPS_BRD_PACRB_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRB_SP3(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP3_MASK, AIPS_PACRB_SP3(value)))
+#define AIPS_BWR_PACRB_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP2 field. */
+#define AIPS_RD_PACRB_TP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP2_MASK) >> AIPS_PACRB_TP2_SHIFT)
+#define AIPS_BRD_PACRB_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRB_TP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP2_MASK, AIPS_PACRB_TP2(value)))
+#define AIPS_BWR_PACRB_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP2 field. */
+#define AIPS_RD_PACRB_WP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP2_MASK) >> AIPS_PACRB_WP2_SHIFT)
+#define AIPS_BRD_PACRB_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRB_WP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP2_MASK, AIPS_PACRB_WP2(value)))
+#define AIPS_BWR_PACRB_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP2 field. */
+#define AIPS_RD_PACRB_SP2(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP2_MASK) >> AIPS_PACRB_SP2_SHIFT)
+#define AIPS_BRD_PACRB_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRB_SP2(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP2_MASK, AIPS_PACRB_SP2(value)))
+#define AIPS_BWR_PACRB_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP1 field. */
+#define AIPS_RD_PACRB_TP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP1_MASK) >> AIPS_PACRB_TP1_SHIFT)
+#define AIPS_BRD_PACRB_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRB_TP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP1_MASK, AIPS_PACRB_TP1(value)))
+#define AIPS_BWR_PACRB_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP1 field. */
+#define AIPS_RD_PACRB_WP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP1_MASK) >> AIPS_PACRB_WP1_SHIFT)
+#define AIPS_BRD_PACRB_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRB_WP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP1_MASK, AIPS_PACRB_WP1(value)))
+#define AIPS_BWR_PACRB_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP1 field. */
+#define AIPS_RD_PACRB_SP1(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP1_MASK) >> AIPS_PACRB_SP1_SHIFT)
+#define AIPS_BRD_PACRB_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRB_SP1(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP1_MASK, AIPS_PACRB_SP1(value)))
+#define AIPS_BWR_PACRB_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_TP0 field. */
+#define AIPS_RD_PACRB_TP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_TP0_MASK) >> AIPS_PACRB_TP0_SHIFT)
+#define AIPS_BRD_PACRB_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRB_TP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_TP0_MASK, AIPS_PACRB_TP0(value)))
+#define AIPS_BWR_PACRB_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_WP0 field. */
+#define AIPS_RD_PACRB_WP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_WP0_MASK) >> AIPS_PACRB_WP0_SHIFT)
+#define AIPS_BRD_PACRB_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRB_WP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_WP0_MASK, AIPS_PACRB_WP0(value)))
+#define AIPS_BWR_PACRB_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRB, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRB_SP0 field. */
+#define AIPS_RD_PACRB_SP0(base) ((AIPS_PACRB_REG(base) & AIPS_PACRB_SP0_MASK) >> AIPS_PACRB_SP0_SHIFT)
+#define AIPS_BRD_PACRB_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRB_SP0(base, value) (AIPS_RMW_PACRB(base, AIPS_PACRB_SP0_MASK, AIPS_PACRB_SP0(value)))
+#define AIPS_BWR_PACRB_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRB_REG(base), AIPS_PACRB_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRC - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRC - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRC register
+ */
+/*@{*/
+#define AIPS_RD_PACRC(base)      (AIPS_PACRC_REG(base))
+#define AIPS_WR_PACRC(base, value) (AIPS_PACRC_REG(base) = (value))
+#define AIPS_RMW_PACRC(base, mask, value) (AIPS_WR_PACRC(base, (AIPS_RD_PACRC(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) |  (value)))
+#define AIPS_CLR_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) & ~(value)))
+#define AIPS_TOG_PACRC(base, value) (AIPS_WR_PACRC(base, AIPS_RD_PACRC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRC bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRC, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP7 field. */
+#define AIPS_RD_PACRC_TP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP7_MASK) >> AIPS_PACRC_TP7_SHIFT)
+#define AIPS_BRD_PACRC_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRC_TP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP7_MASK, AIPS_PACRC_TP7(value)))
+#define AIPS_BWR_PACRC_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP7 field. */
+#define AIPS_RD_PACRC_WP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP7_MASK) >> AIPS_PACRC_WP7_SHIFT)
+#define AIPS_BRD_PACRC_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRC_WP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP7_MASK, AIPS_PACRC_WP7(value)))
+#define AIPS_BWR_PACRC_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP7 field. */
+#define AIPS_RD_PACRC_SP7(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP7_MASK) >> AIPS_PACRC_SP7_SHIFT)
+#define AIPS_BRD_PACRC_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRC_SP7(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP7_MASK, AIPS_PACRC_SP7(value)))
+#define AIPS_BWR_PACRC_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP6 field. */
+#define AIPS_RD_PACRC_TP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP6_MASK) >> AIPS_PACRC_TP6_SHIFT)
+#define AIPS_BRD_PACRC_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRC_TP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP6_MASK, AIPS_PACRC_TP6(value)))
+#define AIPS_BWR_PACRC_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP6 field. */
+#define AIPS_RD_PACRC_WP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP6_MASK) >> AIPS_PACRC_WP6_SHIFT)
+#define AIPS_BRD_PACRC_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRC_WP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP6_MASK, AIPS_PACRC_WP6(value)))
+#define AIPS_BWR_PACRC_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP6 field. */
+#define AIPS_RD_PACRC_SP6(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP6_MASK) >> AIPS_PACRC_SP6_SHIFT)
+#define AIPS_BRD_PACRC_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRC_SP6(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP6_MASK, AIPS_PACRC_SP6(value)))
+#define AIPS_BWR_PACRC_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP5 field. */
+#define AIPS_RD_PACRC_TP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP5_MASK) >> AIPS_PACRC_TP5_SHIFT)
+#define AIPS_BRD_PACRC_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRC_TP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP5_MASK, AIPS_PACRC_TP5(value)))
+#define AIPS_BWR_PACRC_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP5 field. */
+#define AIPS_RD_PACRC_WP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP5_MASK) >> AIPS_PACRC_WP5_SHIFT)
+#define AIPS_BRD_PACRC_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRC_WP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP5_MASK, AIPS_PACRC_WP5(value)))
+#define AIPS_BWR_PACRC_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP5 field. */
+#define AIPS_RD_PACRC_SP5(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP5_MASK) >> AIPS_PACRC_SP5_SHIFT)
+#define AIPS_BRD_PACRC_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRC_SP5(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP5_MASK, AIPS_PACRC_SP5(value)))
+#define AIPS_BWR_PACRC_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP4 field. */
+#define AIPS_RD_PACRC_TP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP4_MASK) >> AIPS_PACRC_TP4_SHIFT)
+#define AIPS_BRD_PACRC_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRC_TP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP4_MASK, AIPS_PACRC_TP4(value)))
+#define AIPS_BWR_PACRC_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP4 field. */
+#define AIPS_RD_PACRC_WP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP4_MASK) >> AIPS_PACRC_WP4_SHIFT)
+#define AIPS_BRD_PACRC_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRC_WP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP4_MASK, AIPS_PACRC_WP4(value)))
+#define AIPS_BWR_PACRC_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP4 field. */
+#define AIPS_RD_PACRC_SP4(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP4_MASK) >> AIPS_PACRC_SP4_SHIFT)
+#define AIPS_BRD_PACRC_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRC_SP4(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP4_MASK, AIPS_PACRC_SP4(value)))
+#define AIPS_BWR_PACRC_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP3 field. */
+#define AIPS_RD_PACRC_TP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP3_MASK) >> AIPS_PACRC_TP3_SHIFT)
+#define AIPS_BRD_PACRC_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRC_TP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP3_MASK, AIPS_PACRC_TP3(value)))
+#define AIPS_BWR_PACRC_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP3 field. */
+#define AIPS_RD_PACRC_WP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP3_MASK) >> AIPS_PACRC_WP3_SHIFT)
+#define AIPS_BRD_PACRC_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRC_WP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP3_MASK, AIPS_PACRC_WP3(value)))
+#define AIPS_BWR_PACRC_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP3 field. */
+#define AIPS_RD_PACRC_SP3(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP3_MASK) >> AIPS_PACRC_SP3_SHIFT)
+#define AIPS_BRD_PACRC_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRC_SP3(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP3_MASK, AIPS_PACRC_SP3(value)))
+#define AIPS_BWR_PACRC_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP2 field. */
+#define AIPS_RD_PACRC_TP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP2_MASK) >> AIPS_PACRC_TP2_SHIFT)
+#define AIPS_BRD_PACRC_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRC_TP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP2_MASK, AIPS_PACRC_TP2(value)))
+#define AIPS_BWR_PACRC_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP2 field. */
+#define AIPS_RD_PACRC_WP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP2_MASK) >> AIPS_PACRC_WP2_SHIFT)
+#define AIPS_BRD_PACRC_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRC_WP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP2_MASK, AIPS_PACRC_WP2(value)))
+#define AIPS_BWR_PACRC_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP2 field. */
+#define AIPS_RD_PACRC_SP2(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP2_MASK) >> AIPS_PACRC_SP2_SHIFT)
+#define AIPS_BRD_PACRC_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRC_SP2(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP2_MASK, AIPS_PACRC_SP2(value)))
+#define AIPS_BWR_PACRC_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP1 field. */
+#define AIPS_RD_PACRC_TP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP1_MASK) >> AIPS_PACRC_TP1_SHIFT)
+#define AIPS_BRD_PACRC_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRC_TP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP1_MASK, AIPS_PACRC_TP1(value)))
+#define AIPS_BWR_PACRC_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP1 field. */
+#define AIPS_RD_PACRC_WP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP1_MASK) >> AIPS_PACRC_WP1_SHIFT)
+#define AIPS_BRD_PACRC_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRC_WP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP1_MASK, AIPS_PACRC_WP1(value)))
+#define AIPS_BWR_PACRC_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP1 field. */
+#define AIPS_RD_PACRC_SP1(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP1_MASK) >> AIPS_PACRC_SP1_SHIFT)
+#define AIPS_BRD_PACRC_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRC_SP1(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP1_MASK, AIPS_PACRC_SP1(value)))
+#define AIPS_BWR_PACRC_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_TP0 field. */
+#define AIPS_RD_PACRC_TP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_TP0_MASK) >> AIPS_PACRC_TP0_SHIFT)
+#define AIPS_BRD_PACRC_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRC_TP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_TP0_MASK, AIPS_PACRC_TP0(value)))
+#define AIPS_BWR_PACRC_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_WP0 field. */
+#define AIPS_RD_PACRC_WP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_WP0_MASK) >> AIPS_PACRC_WP0_SHIFT)
+#define AIPS_BRD_PACRC_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRC_WP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_WP0_MASK, AIPS_PACRC_WP0(value)))
+#define AIPS_BWR_PACRC_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRC, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRC_SP0 field. */
+#define AIPS_RD_PACRC_SP0(base) ((AIPS_PACRC_REG(base) & AIPS_PACRC_SP0_MASK) >> AIPS_PACRC_SP0_SHIFT)
+#define AIPS_BRD_PACRC_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRC_SP0(base, value) (AIPS_RMW_PACRC(base, AIPS_PACRC_SP0_MASK, AIPS_PACRC_SP0(value)))
+#define AIPS_BWR_PACRC_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRC_REG(base), AIPS_PACRC_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRD - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRD - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * Each PACR register consists of eight 4-bit PACR fields. Each PACR field
+ * defines the access levels for a particular peripheral. The mapping between a
+ * peripheral and its PACR field is shown in the table below. The peripheral assignment
+ * to each PACR is defined by the memory map slot that the peripheral is
+ * assigned to. See this chip's memory map for the assignment of a particular
+ * peripheral. The following table shows the location of each peripheral slot's PACR field
+ * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12]
+ * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
+ * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC
+ * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24
+ * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38
+ * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37
+ * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
+ * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH
+ * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64
+ * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74
+ * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83
+ * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93
+ * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102
+ * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110
+ * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
+ * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80
+ * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR
+ * A-D, which control peripheral slots 0-31, are shown below. The following
+ * section, PACRPeripheral Access Control Register , shows the register field
+ * descriptions for PACR E-P. All PACR registers are identical. They are divided into two
+ * sections because they occupy two non-contiguous address spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRD register
+ */
+/*@{*/
+#define AIPS_RD_PACRD(base)      (AIPS_PACRD_REG(base))
+#define AIPS_WR_PACRD(base, value) (AIPS_PACRD_REG(base) = (value))
+#define AIPS_RMW_PACRD(base, mask, value) (AIPS_WR_PACRD(base, (AIPS_RD_PACRD(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) |  (value)))
+#define AIPS_CLR_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) & ~(value)))
+#define AIPS_TOG_PACRD(base, value) (AIPS_WR_PACRD(base, AIPS_RD_PACRD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRD bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRD, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP7 field. */
+#define AIPS_RD_PACRD_TP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP7_MASK) >> AIPS_PACRD_TP7_SHIFT)
+#define AIPS_BRD_PACRD_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRD_TP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP7_MASK, AIPS_PACRD_TP7(value)))
+#define AIPS_BWR_PACRD_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP7 field. */
+#define AIPS_RD_PACRD_WP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP7_MASK) >> AIPS_PACRD_WP7_SHIFT)
+#define AIPS_BRD_PACRD_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRD_WP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP7_MASK, AIPS_PACRD_WP7(value)))
+#define AIPS_BWR_PACRD_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP7 field. */
+#define AIPS_RD_PACRD_SP7(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP7_MASK) >> AIPS_PACRD_SP7_SHIFT)
+#define AIPS_BRD_PACRD_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRD_SP7(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP7_MASK, AIPS_PACRD_SP7(value)))
+#define AIPS_BWR_PACRD_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP6 field. */
+#define AIPS_RD_PACRD_TP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP6_MASK) >> AIPS_PACRD_TP6_SHIFT)
+#define AIPS_BRD_PACRD_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRD_TP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP6_MASK, AIPS_PACRD_TP6(value)))
+#define AIPS_BWR_PACRD_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP6 field. */
+#define AIPS_RD_PACRD_WP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP6_MASK) >> AIPS_PACRD_WP6_SHIFT)
+#define AIPS_BRD_PACRD_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRD_WP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP6_MASK, AIPS_PACRD_WP6(value)))
+#define AIPS_BWR_PACRD_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP6 field. */
+#define AIPS_RD_PACRD_SP6(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP6_MASK) >> AIPS_PACRD_SP6_SHIFT)
+#define AIPS_BRD_PACRD_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRD_SP6(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP6_MASK, AIPS_PACRD_SP6(value)))
+#define AIPS_BWR_PACRD_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP5 field. */
+#define AIPS_RD_PACRD_TP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP5_MASK) >> AIPS_PACRD_TP5_SHIFT)
+#define AIPS_BRD_PACRD_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRD_TP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP5_MASK, AIPS_PACRD_TP5(value)))
+#define AIPS_BWR_PACRD_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP5 field. */
+#define AIPS_RD_PACRD_WP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP5_MASK) >> AIPS_PACRD_WP5_SHIFT)
+#define AIPS_BRD_PACRD_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRD_WP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP5_MASK, AIPS_PACRD_WP5(value)))
+#define AIPS_BWR_PACRD_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP5 field. */
+#define AIPS_RD_PACRD_SP5(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP5_MASK) >> AIPS_PACRD_SP5_SHIFT)
+#define AIPS_BRD_PACRD_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRD_SP5(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP5_MASK, AIPS_PACRD_SP5(value)))
+#define AIPS_BWR_PACRD_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP4 field. */
+#define AIPS_RD_PACRD_TP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP4_MASK) >> AIPS_PACRD_TP4_SHIFT)
+#define AIPS_BRD_PACRD_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRD_TP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP4_MASK, AIPS_PACRD_TP4(value)))
+#define AIPS_BWR_PACRD_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP4 field. */
+#define AIPS_RD_PACRD_WP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP4_MASK) >> AIPS_PACRD_WP4_SHIFT)
+#define AIPS_BRD_PACRD_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRD_WP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP4_MASK, AIPS_PACRD_WP4(value)))
+#define AIPS_BWR_PACRD_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP4 field. */
+#define AIPS_RD_PACRD_SP4(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP4_MASK) >> AIPS_PACRD_SP4_SHIFT)
+#define AIPS_BRD_PACRD_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRD_SP4(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP4_MASK, AIPS_PACRD_SP4(value)))
+#define AIPS_BWR_PACRD_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP3 field. */
+#define AIPS_RD_PACRD_TP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP3_MASK) >> AIPS_PACRD_TP3_SHIFT)
+#define AIPS_BRD_PACRD_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRD_TP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP3_MASK, AIPS_PACRD_TP3(value)))
+#define AIPS_BWR_PACRD_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP3 field. */
+#define AIPS_RD_PACRD_WP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP3_MASK) >> AIPS_PACRD_WP3_SHIFT)
+#define AIPS_BRD_PACRD_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRD_WP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP3_MASK, AIPS_PACRD_WP3(value)))
+#define AIPS_BWR_PACRD_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP3 field. */
+#define AIPS_RD_PACRD_SP3(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP3_MASK) >> AIPS_PACRD_SP3_SHIFT)
+#define AIPS_BRD_PACRD_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRD_SP3(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP3_MASK, AIPS_PACRD_SP3(value)))
+#define AIPS_BWR_PACRD_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP2 field. */
+#define AIPS_RD_PACRD_TP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP2_MASK) >> AIPS_PACRD_TP2_SHIFT)
+#define AIPS_BRD_PACRD_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRD_TP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP2_MASK, AIPS_PACRD_TP2(value)))
+#define AIPS_BWR_PACRD_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP2 field. */
+#define AIPS_RD_PACRD_WP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP2_MASK) >> AIPS_PACRD_WP2_SHIFT)
+#define AIPS_BRD_PACRD_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRD_WP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP2_MASK, AIPS_PACRD_WP2(value)))
+#define AIPS_BWR_PACRD_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP2 field. */
+#define AIPS_RD_PACRD_SP2(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP2_MASK) >> AIPS_PACRD_SP2_SHIFT)
+#define AIPS_BRD_PACRD_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRD_SP2(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP2_MASK, AIPS_PACRD_SP2(value)))
+#define AIPS_BWR_PACRD_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP1 field. */
+#define AIPS_RD_PACRD_TP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP1_MASK) >> AIPS_PACRD_TP1_SHIFT)
+#define AIPS_BRD_PACRD_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRD_TP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP1_MASK, AIPS_PACRD_TP1(value)))
+#define AIPS_BWR_PACRD_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP1 field. */
+#define AIPS_RD_PACRD_WP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP1_MASK) >> AIPS_PACRD_WP1_SHIFT)
+#define AIPS_BRD_PACRD_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRD_WP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP1_MASK, AIPS_PACRD_WP1(value)))
+#define AIPS_BWR_PACRD_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP1 field. */
+#define AIPS_RD_PACRD_SP1(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP1_MASK) >> AIPS_PACRD_SP1_SHIFT)
+#define AIPS_BRD_PACRD_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRD_SP1(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP1_MASK, AIPS_PACRD_SP1(value)))
+#define AIPS_BWR_PACRD_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_TP0 field. */
+#define AIPS_RD_PACRD_TP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_TP0_MASK) >> AIPS_PACRD_TP0_SHIFT)
+#define AIPS_BRD_PACRD_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRD_TP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_TP0_MASK, AIPS_PACRD_TP0(value)))
+#define AIPS_BWR_PACRD_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_WP0 field. */
+#define AIPS_RD_PACRD_WP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_WP0_MASK) >> AIPS_PACRD_WP0_SHIFT)
+#define AIPS_BRD_PACRD_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRD_WP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_WP0_MASK, AIPS_PACRD_WP0(value)))
+#define AIPS_BWR_PACRD_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRD, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRD_SP0 field. */
+#define AIPS_RD_PACRD_SP0(base) ((AIPS_PACRD_REG(base) & AIPS_PACRD_SP0_MASK) >> AIPS_PACRD_SP0_SHIFT)
+#define AIPS_BRD_PACRD_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRD_SP0(base, value) (AIPS_RMW_PACRD(base, AIPS_PACRD_SP0_MASK, AIPS_PACRD_SP0(value)))
+#define AIPS_BWR_PACRD_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRD_REG(base), AIPS_PACRD_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRE - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRE - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRE register
+ */
+/*@{*/
+#define AIPS_RD_PACRE(base)      (AIPS_PACRE_REG(base))
+#define AIPS_WR_PACRE(base, value) (AIPS_PACRE_REG(base) = (value))
+#define AIPS_RMW_PACRE(base, mask, value) (AIPS_WR_PACRE(base, (AIPS_RD_PACRE(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) |  (value)))
+#define AIPS_CLR_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) & ~(value)))
+#define AIPS_TOG_PACRE(base, value) (AIPS_WR_PACRE(base, AIPS_RD_PACRE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRE bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRE, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP7 field. */
+#define AIPS_RD_PACRE_TP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP7_MASK) >> AIPS_PACRE_TP7_SHIFT)
+#define AIPS_BRD_PACRE_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRE_TP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP7_MASK, AIPS_PACRE_TP7(value)))
+#define AIPS_BWR_PACRE_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP7 field. */
+#define AIPS_RD_PACRE_WP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP7_MASK) >> AIPS_PACRE_WP7_SHIFT)
+#define AIPS_BRD_PACRE_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRE_WP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP7_MASK, AIPS_PACRE_WP7(value)))
+#define AIPS_BWR_PACRE_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP7 field. */
+#define AIPS_RD_PACRE_SP7(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP7_MASK) >> AIPS_PACRE_SP7_SHIFT)
+#define AIPS_BRD_PACRE_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRE_SP7(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP7_MASK, AIPS_PACRE_SP7(value)))
+#define AIPS_BWR_PACRE_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP6 field. */
+#define AIPS_RD_PACRE_TP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP6_MASK) >> AIPS_PACRE_TP6_SHIFT)
+#define AIPS_BRD_PACRE_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRE_TP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP6_MASK, AIPS_PACRE_TP6(value)))
+#define AIPS_BWR_PACRE_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP6 field. */
+#define AIPS_RD_PACRE_WP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP6_MASK) >> AIPS_PACRE_WP6_SHIFT)
+#define AIPS_BRD_PACRE_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRE_WP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP6_MASK, AIPS_PACRE_WP6(value)))
+#define AIPS_BWR_PACRE_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP6 field. */
+#define AIPS_RD_PACRE_SP6(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP6_MASK) >> AIPS_PACRE_SP6_SHIFT)
+#define AIPS_BRD_PACRE_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRE_SP6(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP6_MASK, AIPS_PACRE_SP6(value)))
+#define AIPS_BWR_PACRE_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP5 field. */
+#define AIPS_RD_PACRE_TP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP5_MASK) >> AIPS_PACRE_TP5_SHIFT)
+#define AIPS_BRD_PACRE_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRE_TP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP5_MASK, AIPS_PACRE_TP5(value)))
+#define AIPS_BWR_PACRE_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP5 field. */
+#define AIPS_RD_PACRE_WP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP5_MASK) >> AIPS_PACRE_WP5_SHIFT)
+#define AIPS_BRD_PACRE_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRE_WP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP5_MASK, AIPS_PACRE_WP5(value)))
+#define AIPS_BWR_PACRE_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP5 field. */
+#define AIPS_RD_PACRE_SP5(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP5_MASK) >> AIPS_PACRE_SP5_SHIFT)
+#define AIPS_BRD_PACRE_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRE_SP5(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP5_MASK, AIPS_PACRE_SP5(value)))
+#define AIPS_BWR_PACRE_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP4 field. */
+#define AIPS_RD_PACRE_TP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP4_MASK) >> AIPS_PACRE_TP4_SHIFT)
+#define AIPS_BRD_PACRE_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRE_TP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP4_MASK, AIPS_PACRE_TP4(value)))
+#define AIPS_BWR_PACRE_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP4 field. */
+#define AIPS_RD_PACRE_WP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP4_MASK) >> AIPS_PACRE_WP4_SHIFT)
+#define AIPS_BRD_PACRE_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRE_WP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP4_MASK, AIPS_PACRE_WP4(value)))
+#define AIPS_BWR_PACRE_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP4 field. */
+#define AIPS_RD_PACRE_SP4(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP4_MASK) >> AIPS_PACRE_SP4_SHIFT)
+#define AIPS_BRD_PACRE_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRE_SP4(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP4_MASK, AIPS_PACRE_SP4(value)))
+#define AIPS_BWR_PACRE_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP3 field. */
+#define AIPS_RD_PACRE_TP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP3_MASK) >> AIPS_PACRE_TP3_SHIFT)
+#define AIPS_BRD_PACRE_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRE_TP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP3_MASK, AIPS_PACRE_TP3(value)))
+#define AIPS_BWR_PACRE_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP3 field. */
+#define AIPS_RD_PACRE_WP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP3_MASK) >> AIPS_PACRE_WP3_SHIFT)
+#define AIPS_BRD_PACRE_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRE_WP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP3_MASK, AIPS_PACRE_WP3(value)))
+#define AIPS_BWR_PACRE_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP3 field. */
+#define AIPS_RD_PACRE_SP3(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP3_MASK) >> AIPS_PACRE_SP3_SHIFT)
+#define AIPS_BRD_PACRE_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRE_SP3(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP3_MASK, AIPS_PACRE_SP3(value)))
+#define AIPS_BWR_PACRE_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP2 field. */
+#define AIPS_RD_PACRE_TP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP2_MASK) >> AIPS_PACRE_TP2_SHIFT)
+#define AIPS_BRD_PACRE_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRE_TP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP2_MASK, AIPS_PACRE_TP2(value)))
+#define AIPS_BWR_PACRE_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP2 field. */
+#define AIPS_RD_PACRE_WP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP2_MASK) >> AIPS_PACRE_WP2_SHIFT)
+#define AIPS_BRD_PACRE_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRE_WP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP2_MASK, AIPS_PACRE_WP2(value)))
+#define AIPS_BWR_PACRE_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP2 field. */
+#define AIPS_RD_PACRE_SP2(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP2_MASK) >> AIPS_PACRE_SP2_SHIFT)
+#define AIPS_BRD_PACRE_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRE_SP2(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP2_MASK, AIPS_PACRE_SP2(value)))
+#define AIPS_BWR_PACRE_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP1 field. */
+#define AIPS_RD_PACRE_TP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP1_MASK) >> AIPS_PACRE_TP1_SHIFT)
+#define AIPS_BRD_PACRE_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRE_TP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP1_MASK, AIPS_PACRE_TP1(value)))
+#define AIPS_BWR_PACRE_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP1 field. */
+#define AIPS_RD_PACRE_WP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP1_MASK) >> AIPS_PACRE_WP1_SHIFT)
+#define AIPS_BRD_PACRE_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRE_WP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP1_MASK, AIPS_PACRE_WP1(value)))
+#define AIPS_BWR_PACRE_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP1 field. */
+#define AIPS_RD_PACRE_SP1(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP1_MASK) >> AIPS_PACRE_SP1_SHIFT)
+#define AIPS_BRD_PACRE_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRE_SP1(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP1_MASK, AIPS_PACRE_SP1(value)))
+#define AIPS_BWR_PACRE_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_TP0 field. */
+#define AIPS_RD_PACRE_TP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_TP0_MASK) >> AIPS_PACRE_TP0_SHIFT)
+#define AIPS_BRD_PACRE_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRE_TP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_TP0_MASK, AIPS_PACRE_TP0(value)))
+#define AIPS_BWR_PACRE_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_WP0 field. */
+#define AIPS_RD_PACRE_WP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_WP0_MASK) >> AIPS_PACRE_WP0_SHIFT)
+#define AIPS_BRD_PACRE_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRE_WP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_WP0_MASK, AIPS_PACRE_WP0(value)))
+#define AIPS_BWR_PACRE_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRE, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRE_SP0 field. */
+#define AIPS_RD_PACRE_SP0(base) ((AIPS_PACRE_REG(base) & AIPS_PACRE_SP0_MASK) >> AIPS_PACRE_SP0_SHIFT)
+#define AIPS_BRD_PACRE_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRE_SP0(base, value) (AIPS_RMW_PACRE(base, AIPS_PACRE_SP0_MASK, AIPS_PACRE_SP0(value)))
+#define AIPS_BWR_PACRE_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRE_REG(base), AIPS_PACRE_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRF - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRF - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRF register
+ */
+/*@{*/
+#define AIPS_RD_PACRF(base)      (AIPS_PACRF_REG(base))
+#define AIPS_WR_PACRF(base, value) (AIPS_PACRF_REG(base) = (value))
+#define AIPS_RMW_PACRF(base, mask, value) (AIPS_WR_PACRF(base, (AIPS_RD_PACRF(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) |  (value)))
+#define AIPS_CLR_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) & ~(value)))
+#define AIPS_TOG_PACRF(base, value) (AIPS_WR_PACRF(base, AIPS_RD_PACRF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRF bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRF, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP7 field. */
+#define AIPS_RD_PACRF_TP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP7_MASK) >> AIPS_PACRF_TP7_SHIFT)
+#define AIPS_BRD_PACRF_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRF_TP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP7_MASK, AIPS_PACRF_TP7(value)))
+#define AIPS_BWR_PACRF_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP7 field. */
+#define AIPS_RD_PACRF_WP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP7_MASK) >> AIPS_PACRF_WP7_SHIFT)
+#define AIPS_BRD_PACRF_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRF_WP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP7_MASK, AIPS_PACRF_WP7(value)))
+#define AIPS_BWR_PACRF_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP7 field. */
+#define AIPS_RD_PACRF_SP7(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP7_MASK) >> AIPS_PACRF_SP7_SHIFT)
+#define AIPS_BRD_PACRF_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRF_SP7(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP7_MASK, AIPS_PACRF_SP7(value)))
+#define AIPS_BWR_PACRF_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP6 field. */
+#define AIPS_RD_PACRF_TP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP6_MASK) >> AIPS_PACRF_TP6_SHIFT)
+#define AIPS_BRD_PACRF_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRF_TP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP6_MASK, AIPS_PACRF_TP6(value)))
+#define AIPS_BWR_PACRF_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP6 field. */
+#define AIPS_RD_PACRF_WP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP6_MASK) >> AIPS_PACRF_WP6_SHIFT)
+#define AIPS_BRD_PACRF_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRF_WP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP6_MASK, AIPS_PACRF_WP6(value)))
+#define AIPS_BWR_PACRF_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP6 field. */
+#define AIPS_RD_PACRF_SP6(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP6_MASK) >> AIPS_PACRF_SP6_SHIFT)
+#define AIPS_BRD_PACRF_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRF_SP6(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP6_MASK, AIPS_PACRF_SP6(value)))
+#define AIPS_BWR_PACRF_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP5 field. */
+#define AIPS_RD_PACRF_TP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP5_MASK) >> AIPS_PACRF_TP5_SHIFT)
+#define AIPS_BRD_PACRF_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRF_TP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP5_MASK, AIPS_PACRF_TP5(value)))
+#define AIPS_BWR_PACRF_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP5 field. */
+#define AIPS_RD_PACRF_WP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP5_MASK) >> AIPS_PACRF_WP5_SHIFT)
+#define AIPS_BRD_PACRF_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRF_WP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP5_MASK, AIPS_PACRF_WP5(value)))
+#define AIPS_BWR_PACRF_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP5 field. */
+#define AIPS_RD_PACRF_SP5(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP5_MASK) >> AIPS_PACRF_SP5_SHIFT)
+#define AIPS_BRD_PACRF_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRF_SP5(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP5_MASK, AIPS_PACRF_SP5(value)))
+#define AIPS_BWR_PACRF_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP4 field. */
+#define AIPS_RD_PACRF_TP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP4_MASK) >> AIPS_PACRF_TP4_SHIFT)
+#define AIPS_BRD_PACRF_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRF_TP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP4_MASK, AIPS_PACRF_TP4(value)))
+#define AIPS_BWR_PACRF_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP4 field. */
+#define AIPS_RD_PACRF_WP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP4_MASK) >> AIPS_PACRF_WP4_SHIFT)
+#define AIPS_BRD_PACRF_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRF_WP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP4_MASK, AIPS_PACRF_WP4(value)))
+#define AIPS_BWR_PACRF_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP4 field. */
+#define AIPS_RD_PACRF_SP4(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP4_MASK) >> AIPS_PACRF_SP4_SHIFT)
+#define AIPS_BRD_PACRF_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRF_SP4(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP4_MASK, AIPS_PACRF_SP4(value)))
+#define AIPS_BWR_PACRF_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP3 field. */
+#define AIPS_RD_PACRF_TP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP3_MASK) >> AIPS_PACRF_TP3_SHIFT)
+#define AIPS_BRD_PACRF_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRF_TP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP3_MASK, AIPS_PACRF_TP3(value)))
+#define AIPS_BWR_PACRF_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP3 field. */
+#define AIPS_RD_PACRF_WP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP3_MASK) >> AIPS_PACRF_WP3_SHIFT)
+#define AIPS_BRD_PACRF_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRF_WP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP3_MASK, AIPS_PACRF_WP3(value)))
+#define AIPS_BWR_PACRF_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP3 field. */
+#define AIPS_RD_PACRF_SP3(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP3_MASK) >> AIPS_PACRF_SP3_SHIFT)
+#define AIPS_BRD_PACRF_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRF_SP3(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP3_MASK, AIPS_PACRF_SP3(value)))
+#define AIPS_BWR_PACRF_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP2 field. */
+#define AIPS_RD_PACRF_TP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP2_MASK) >> AIPS_PACRF_TP2_SHIFT)
+#define AIPS_BRD_PACRF_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRF_TP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP2_MASK, AIPS_PACRF_TP2(value)))
+#define AIPS_BWR_PACRF_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP2 field. */
+#define AIPS_RD_PACRF_WP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP2_MASK) >> AIPS_PACRF_WP2_SHIFT)
+#define AIPS_BRD_PACRF_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRF_WP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP2_MASK, AIPS_PACRF_WP2(value)))
+#define AIPS_BWR_PACRF_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP2 field. */
+#define AIPS_RD_PACRF_SP2(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP2_MASK) >> AIPS_PACRF_SP2_SHIFT)
+#define AIPS_BRD_PACRF_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRF_SP2(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP2_MASK, AIPS_PACRF_SP2(value)))
+#define AIPS_BWR_PACRF_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP1 field. */
+#define AIPS_RD_PACRF_TP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP1_MASK) >> AIPS_PACRF_TP1_SHIFT)
+#define AIPS_BRD_PACRF_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRF_TP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP1_MASK, AIPS_PACRF_TP1(value)))
+#define AIPS_BWR_PACRF_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP1 field. */
+#define AIPS_RD_PACRF_WP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP1_MASK) >> AIPS_PACRF_WP1_SHIFT)
+#define AIPS_BRD_PACRF_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRF_WP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP1_MASK, AIPS_PACRF_WP1(value)))
+#define AIPS_BWR_PACRF_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP1 field. */
+#define AIPS_RD_PACRF_SP1(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP1_MASK) >> AIPS_PACRF_SP1_SHIFT)
+#define AIPS_BRD_PACRF_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRF_SP1(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP1_MASK, AIPS_PACRF_SP1(value)))
+#define AIPS_BWR_PACRF_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_TP0 field. */
+#define AIPS_RD_PACRF_TP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_TP0_MASK) >> AIPS_PACRF_TP0_SHIFT)
+#define AIPS_BRD_PACRF_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRF_TP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_TP0_MASK, AIPS_PACRF_TP0(value)))
+#define AIPS_BWR_PACRF_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_WP0 field. */
+#define AIPS_RD_PACRF_WP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_WP0_MASK) >> AIPS_PACRF_WP0_SHIFT)
+#define AIPS_BRD_PACRF_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRF_WP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_WP0_MASK, AIPS_PACRF_WP0(value)))
+#define AIPS_BWR_PACRF_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRF, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRF_SP0 field. */
+#define AIPS_RD_PACRF_SP0(base) ((AIPS_PACRF_REG(base) & AIPS_PACRF_SP0_MASK) >> AIPS_PACRF_SP0_SHIFT)
+#define AIPS_BRD_PACRF_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRF_SP0(base, value) (AIPS_RMW_PACRF(base, AIPS_PACRF_SP0_MASK, AIPS_PACRF_SP0(value)))
+#define AIPS_BWR_PACRF_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRF_REG(base), AIPS_PACRF_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRG - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRG - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRG register
+ */
+/*@{*/
+#define AIPS_RD_PACRG(base)      (AIPS_PACRG_REG(base))
+#define AIPS_WR_PACRG(base, value) (AIPS_PACRG_REG(base) = (value))
+#define AIPS_RMW_PACRG(base, mask, value) (AIPS_WR_PACRG(base, (AIPS_RD_PACRG(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) |  (value)))
+#define AIPS_CLR_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) & ~(value)))
+#define AIPS_TOG_PACRG(base, value) (AIPS_WR_PACRG(base, AIPS_RD_PACRG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRG bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRG, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP7 field. */
+#define AIPS_RD_PACRG_TP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP7_MASK) >> AIPS_PACRG_TP7_SHIFT)
+#define AIPS_BRD_PACRG_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRG_TP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP7_MASK, AIPS_PACRG_TP7(value)))
+#define AIPS_BWR_PACRG_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP7 field. */
+#define AIPS_RD_PACRG_WP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP7_MASK) >> AIPS_PACRG_WP7_SHIFT)
+#define AIPS_BRD_PACRG_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRG_WP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP7_MASK, AIPS_PACRG_WP7(value)))
+#define AIPS_BWR_PACRG_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP7 field. */
+#define AIPS_RD_PACRG_SP7(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP7_MASK) >> AIPS_PACRG_SP7_SHIFT)
+#define AIPS_BRD_PACRG_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRG_SP7(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP7_MASK, AIPS_PACRG_SP7(value)))
+#define AIPS_BWR_PACRG_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP6 field. */
+#define AIPS_RD_PACRG_TP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP6_MASK) >> AIPS_PACRG_TP6_SHIFT)
+#define AIPS_BRD_PACRG_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRG_TP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP6_MASK, AIPS_PACRG_TP6(value)))
+#define AIPS_BWR_PACRG_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP6 field. */
+#define AIPS_RD_PACRG_WP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP6_MASK) >> AIPS_PACRG_WP6_SHIFT)
+#define AIPS_BRD_PACRG_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRG_WP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP6_MASK, AIPS_PACRG_WP6(value)))
+#define AIPS_BWR_PACRG_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP6 field. */
+#define AIPS_RD_PACRG_SP6(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP6_MASK) >> AIPS_PACRG_SP6_SHIFT)
+#define AIPS_BRD_PACRG_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRG_SP6(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP6_MASK, AIPS_PACRG_SP6(value)))
+#define AIPS_BWR_PACRG_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP5 field. */
+#define AIPS_RD_PACRG_TP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP5_MASK) >> AIPS_PACRG_TP5_SHIFT)
+#define AIPS_BRD_PACRG_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRG_TP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP5_MASK, AIPS_PACRG_TP5(value)))
+#define AIPS_BWR_PACRG_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP5 field. */
+#define AIPS_RD_PACRG_WP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP5_MASK) >> AIPS_PACRG_WP5_SHIFT)
+#define AIPS_BRD_PACRG_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRG_WP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP5_MASK, AIPS_PACRG_WP5(value)))
+#define AIPS_BWR_PACRG_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP5 field. */
+#define AIPS_RD_PACRG_SP5(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP5_MASK) >> AIPS_PACRG_SP5_SHIFT)
+#define AIPS_BRD_PACRG_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRG_SP5(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP5_MASK, AIPS_PACRG_SP5(value)))
+#define AIPS_BWR_PACRG_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP4 field. */
+#define AIPS_RD_PACRG_TP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP4_MASK) >> AIPS_PACRG_TP4_SHIFT)
+#define AIPS_BRD_PACRG_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRG_TP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP4_MASK, AIPS_PACRG_TP4(value)))
+#define AIPS_BWR_PACRG_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP4 field. */
+#define AIPS_RD_PACRG_WP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP4_MASK) >> AIPS_PACRG_WP4_SHIFT)
+#define AIPS_BRD_PACRG_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRG_WP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP4_MASK, AIPS_PACRG_WP4(value)))
+#define AIPS_BWR_PACRG_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP4 field. */
+#define AIPS_RD_PACRG_SP4(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP4_MASK) >> AIPS_PACRG_SP4_SHIFT)
+#define AIPS_BRD_PACRG_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRG_SP4(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP4_MASK, AIPS_PACRG_SP4(value)))
+#define AIPS_BWR_PACRG_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP3 field. */
+#define AIPS_RD_PACRG_TP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP3_MASK) >> AIPS_PACRG_TP3_SHIFT)
+#define AIPS_BRD_PACRG_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRG_TP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP3_MASK, AIPS_PACRG_TP3(value)))
+#define AIPS_BWR_PACRG_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP3 field. */
+#define AIPS_RD_PACRG_WP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP3_MASK) >> AIPS_PACRG_WP3_SHIFT)
+#define AIPS_BRD_PACRG_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRG_WP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP3_MASK, AIPS_PACRG_WP3(value)))
+#define AIPS_BWR_PACRG_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP3 field. */
+#define AIPS_RD_PACRG_SP3(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP3_MASK) >> AIPS_PACRG_SP3_SHIFT)
+#define AIPS_BRD_PACRG_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRG_SP3(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP3_MASK, AIPS_PACRG_SP3(value)))
+#define AIPS_BWR_PACRG_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP2 field. */
+#define AIPS_RD_PACRG_TP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP2_MASK) >> AIPS_PACRG_TP2_SHIFT)
+#define AIPS_BRD_PACRG_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRG_TP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP2_MASK, AIPS_PACRG_TP2(value)))
+#define AIPS_BWR_PACRG_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP2 field. */
+#define AIPS_RD_PACRG_WP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP2_MASK) >> AIPS_PACRG_WP2_SHIFT)
+#define AIPS_BRD_PACRG_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRG_WP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP2_MASK, AIPS_PACRG_WP2(value)))
+#define AIPS_BWR_PACRG_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP2 field. */
+#define AIPS_RD_PACRG_SP2(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP2_MASK) >> AIPS_PACRG_SP2_SHIFT)
+#define AIPS_BRD_PACRG_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRG_SP2(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP2_MASK, AIPS_PACRG_SP2(value)))
+#define AIPS_BWR_PACRG_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP1 field. */
+#define AIPS_RD_PACRG_TP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP1_MASK) >> AIPS_PACRG_TP1_SHIFT)
+#define AIPS_BRD_PACRG_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRG_TP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP1_MASK, AIPS_PACRG_TP1(value)))
+#define AIPS_BWR_PACRG_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP1 field. */
+#define AIPS_RD_PACRG_WP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP1_MASK) >> AIPS_PACRG_WP1_SHIFT)
+#define AIPS_BRD_PACRG_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRG_WP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP1_MASK, AIPS_PACRG_WP1(value)))
+#define AIPS_BWR_PACRG_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP1 field. */
+#define AIPS_RD_PACRG_SP1(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP1_MASK) >> AIPS_PACRG_SP1_SHIFT)
+#define AIPS_BRD_PACRG_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRG_SP1(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP1_MASK, AIPS_PACRG_SP1(value)))
+#define AIPS_BWR_PACRG_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_TP0 field. */
+#define AIPS_RD_PACRG_TP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_TP0_MASK) >> AIPS_PACRG_TP0_SHIFT)
+#define AIPS_BRD_PACRG_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRG_TP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_TP0_MASK, AIPS_PACRG_TP0(value)))
+#define AIPS_BWR_PACRG_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_WP0 field. */
+#define AIPS_RD_PACRG_WP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_WP0_MASK) >> AIPS_PACRG_WP0_SHIFT)
+#define AIPS_BRD_PACRG_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRG_WP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_WP0_MASK, AIPS_PACRG_WP0(value)))
+#define AIPS_BWR_PACRG_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRG, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRG_SP0 field. */
+#define AIPS_RD_PACRG_SP0(base) ((AIPS_PACRG_REG(base) & AIPS_PACRG_SP0_MASK) >> AIPS_PACRG_SP0_SHIFT)
+#define AIPS_BRD_PACRG_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRG_SP0(base, value) (AIPS_RMW_PACRG(base, AIPS_PACRG_SP0_MASK, AIPS_PACRG_SP0(value)))
+#define AIPS_BWR_PACRG_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRG_REG(base), AIPS_PACRG_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRH - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRH - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRH register
+ */
+/*@{*/
+#define AIPS_RD_PACRH(base)      (AIPS_PACRH_REG(base))
+#define AIPS_WR_PACRH(base, value) (AIPS_PACRH_REG(base) = (value))
+#define AIPS_RMW_PACRH(base, mask, value) (AIPS_WR_PACRH(base, (AIPS_RD_PACRH(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) |  (value)))
+#define AIPS_CLR_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) & ~(value)))
+#define AIPS_TOG_PACRH(base, value) (AIPS_WR_PACRH(base, AIPS_RD_PACRH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRH bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRH, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP7 field. */
+#define AIPS_RD_PACRH_TP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP7_MASK) >> AIPS_PACRH_TP7_SHIFT)
+#define AIPS_BRD_PACRH_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRH_TP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP7_MASK, AIPS_PACRH_TP7(value)))
+#define AIPS_BWR_PACRH_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP7 field. */
+#define AIPS_RD_PACRH_WP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP7_MASK) >> AIPS_PACRH_WP7_SHIFT)
+#define AIPS_BRD_PACRH_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRH_WP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP7_MASK, AIPS_PACRH_WP7(value)))
+#define AIPS_BWR_PACRH_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP7 field. */
+#define AIPS_RD_PACRH_SP7(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP7_MASK) >> AIPS_PACRH_SP7_SHIFT)
+#define AIPS_BRD_PACRH_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRH_SP7(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP7_MASK, AIPS_PACRH_SP7(value)))
+#define AIPS_BWR_PACRH_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP6 field. */
+#define AIPS_RD_PACRH_TP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP6_MASK) >> AIPS_PACRH_TP6_SHIFT)
+#define AIPS_BRD_PACRH_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRH_TP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP6_MASK, AIPS_PACRH_TP6(value)))
+#define AIPS_BWR_PACRH_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP6 field. */
+#define AIPS_RD_PACRH_WP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP6_MASK) >> AIPS_PACRH_WP6_SHIFT)
+#define AIPS_BRD_PACRH_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRH_WP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP6_MASK, AIPS_PACRH_WP6(value)))
+#define AIPS_BWR_PACRH_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP6 field. */
+#define AIPS_RD_PACRH_SP6(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP6_MASK) >> AIPS_PACRH_SP6_SHIFT)
+#define AIPS_BRD_PACRH_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRH_SP6(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP6_MASK, AIPS_PACRH_SP6(value)))
+#define AIPS_BWR_PACRH_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP5 field. */
+#define AIPS_RD_PACRH_TP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP5_MASK) >> AIPS_PACRH_TP5_SHIFT)
+#define AIPS_BRD_PACRH_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRH_TP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP5_MASK, AIPS_PACRH_TP5(value)))
+#define AIPS_BWR_PACRH_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP5 field. */
+#define AIPS_RD_PACRH_WP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP5_MASK) >> AIPS_PACRH_WP5_SHIFT)
+#define AIPS_BRD_PACRH_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRH_WP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP5_MASK, AIPS_PACRH_WP5(value)))
+#define AIPS_BWR_PACRH_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP5 field. */
+#define AIPS_RD_PACRH_SP5(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP5_MASK) >> AIPS_PACRH_SP5_SHIFT)
+#define AIPS_BRD_PACRH_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRH_SP5(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP5_MASK, AIPS_PACRH_SP5(value)))
+#define AIPS_BWR_PACRH_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP4 field. */
+#define AIPS_RD_PACRH_TP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP4_MASK) >> AIPS_PACRH_TP4_SHIFT)
+#define AIPS_BRD_PACRH_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRH_TP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP4_MASK, AIPS_PACRH_TP4(value)))
+#define AIPS_BWR_PACRH_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP4 field. */
+#define AIPS_RD_PACRH_WP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP4_MASK) >> AIPS_PACRH_WP4_SHIFT)
+#define AIPS_BRD_PACRH_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRH_WP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP4_MASK, AIPS_PACRH_WP4(value)))
+#define AIPS_BWR_PACRH_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP4 field. */
+#define AIPS_RD_PACRH_SP4(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP4_MASK) >> AIPS_PACRH_SP4_SHIFT)
+#define AIPS_BRD_PACRH_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRH_SP4(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP4_MASK, AIPS_PACRH_SP4(value)))
+#define AIPS_BWR_PACRH_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP3 field. */
+#define AIPS_RD_PACRH_TP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP3_MASK) >> AIPS_PACRH_TP3_SHIFT)
+#define AIPS_BRD_PACRH_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRH_TP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP3_MASK, AIPS_PACRH_TP3(value)))
+#define AIPS_BWR_PACRH_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP3 field. */
+#define AIPS_RD_PACRH_WP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP3_MASK) >> AIPS_PACRH_WP3_SHIFT)
+#define AIPS_BRD_PACRH_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRH_WP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP3_MASK, AIPS_PACRH_WP3(value)))
+#define AIPS_BWR_PACRH_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP3 field. */
+#define AIPS_RD_PACRH_SP3(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP3_MASK) >> AIPS_PACRH_SP3_SHIFT)
+#define AIPS_BRD_PACRH_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRH_SP3(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP3_MASK, AIPS_PACRH_SP3(value)))
+#define AIPS_BWR_PACRH_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP2 field. */
+#define AIPS_RD_PACRH_TP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP2_MASK) >> AIPS_PACRH_TP2_SHIFT)
+#define AIPS_BRD_PACRH_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRH_TP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP2_MASK, AIPS_PACRH_TP2(value)))
+#define AIPS_BWR_PACRH_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP2 field. */
+#define AIPS_RD_PACRH_WP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP2_MASK) >> AIPS_PACRH_WP2_SHIFT)
+#define AIPS_BRD_PACRH_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRH_WP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP2_MASK, AIPS_PACRH_WP2(value)))
+#define AIPS_BWR_PACRH_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP2 field. */
+#define AIPS_RD_PACRH_SP2(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP2_MASK) >> AIPS_PACRH_SP2_SHIFT)
+#define AIPS_BRD_PACRH_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRH_SP2(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP2_MASK, AIPS_PACRH_SP2(value)))
+#define AIPS_BWR_PACRH_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP1 field. */
+#define AIPS_RD_PACRH_TP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP1_MASK) >> AIPS_PACRH_TP1_SHIFT)
+#define AIPS_BRD_PACRH_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRH_TP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP1_MASK, AIPS_PACRH_TP1(value)))
+#define AIPS_BWR_PACRH_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP1 field. */
+#define AIPS_RD_PACRH_WP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP1_MASK) >> AIPS_PACRH_WP1_SHIFT)
+#define AIPS_BRD_PACRH_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRH_WP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP1_MASK, AIPS_PACRH_WP1(value)))
+#define AIPS_BWR_PACRH_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP1 field. */
+#define AIPS_RD_PACRH_SP1(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP1_MASK) >> AIPS_PACRH_SP1_SHIFT)
+#define AIPS_BRD_PACRH_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRH_SP1(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP1_MASK, AIPS_PACRH_SP1(value)))
+#define AIPS_BWR_PACRH_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_TP0 field. */
+#define AIPS_RD_PACRH_TP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_TP0_MASK) >> AIPS_PACRH_TP0_SHIFT)
+#define AIPS_BRD_PACRH_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRH_TP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_TP0_MASK, AIPS_PACRH_TP0(value)))
+#define AIPS_BWR_PACRH_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_WP0 field. */
+#define AIPS_RD_PACRH_WP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_WP0_MASK) >> AIPS_PACRH_WP0_SHIFT)
+#define AIPS_BRD_PACRH_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRH_WP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_WP0_MASK, AIPS_PACRH_WP0(value)))
+#define AIPS_BWR_PACRH_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRH, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRH_SP0 field. */
+#define AIPS_RD_PACRH_SP0(base) ((AIPS_PACRH_REG(base) & AIPS_PACRH_SP0_MASK) >> AIPS_PACRH_SP0_SHIFT)
+#define AIPS_BRD_PACRH_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRH_SP0(base, value) (AIPS_RMW_PACRH(base, AIPS_PACRH_SP0_MASK, AIPS_PACRH_SP0(value)))
+#define AIPS_BWR_PACRH_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRH_REG(base), AIPS_PACRH_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRI - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRI - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRI register
+ */
+/*@{*/
+#define AIPS_RD_PACRI(base)      (AIPS_PACRI_REG(base))
+#define AIPS_WR_PACRI(base, value) (AIPS_PACRI_REG(base) = (value))
+#define AIPS_RMW_PACRI(base, mask, value) (AIPS_WR_PACRI(base, (AIPS_RD_PACRI(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) |  (value)))
+#define AIPS_CLR_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) & ~(value)))
+#define AIPS_TOG_PACRI(base, value) (AIPS_WR_PACRI(base, AIPS_RD_PACRI(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRI bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRI, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP7 field. */
+#define AIPS_RD_PACRI_TP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP7_MASK) >> AIPS_PACRI_TP7_SHIFT)
+#define AIPS_BRD_PACRI_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRI_TP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP7_MASK, AIPS_PACRI_TP7(value)))
+#define AIPS_BWR_PACRI_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP7 field. */
+#define AIPS_RD_PACRI_WP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP7_MASK) >> AIPS_PACRI_WP7_SHIFT)
+#define AIPS_BRD_PACRI_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRI_WP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP7_MASK, AIPS_PACRI_WP7(value)))
+#define AIPS_BWR_PACRI_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP7 field. */
+#define AIPS_RD_PACRI_SP7(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP7_MASK) >> AIPS_PACRI_SP7_SHIFT)
+#define AIPS_BRD_PACRI_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRI_SP7(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP7_MASK, AIPS_PACRI_SP7(value)))
+#define AIPS_BWR_PACRI_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP6 field. */
+#define AIPS_RD_PACRI_TP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP6_MASK) >> AIPS_PACRI_TP6_SHIFT)
+#define AIPS_BRD_PACRI_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRI_TP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP6_MASK, AIPS_PACRI_TP6(value)))
+#define AIPS_BWR_PACRI_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP6 field. */
+#define AIPS_RD_PACRI_WP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP6_MASK) >> AIPS_PACRI_WP6_SHIFT)
+#define AIPS_BRD_PACRI_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRI_WP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP6_MASK, AIPS_PACRI_WP6(value)))
+#define AIPS_BWR_PACRI_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP6 field. */
+#define AIPS_RD_PACRI_SP6(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP6_MASK) >> AIPS_PACRI_SP6_SHIFT)
+#define AIPS_BRD_PACRI_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRI_SP6(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP6_MASK, AIPS_PACRI_SP6(value)))
+#define AIPS_BWR_PACRI_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP5 field. */
+#define AIPS_RD_PACRI_TP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP5_MASK) >> AIPS_PACRI_TP5_SHIFT)
+#define AIPS_BRD_PACRI_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRI_TP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP5_MASK, AIPS_PACRI_TP5(value)))
+#define AIPS_BWR_PACRI_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP5 field. */
+#define AIPS_RD_PACRI_WP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP5_MASK) >> AIPS_PACRI_WP5_SHIFT)
+#define AIPS_BRD_PACRI_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRI_WP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP5_MASK, AIPS_PACRI_WP5(value)))
+#define AIPS_BWR_PACRI_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP5 field. */
+#define AIPS_RD_PACRI_SP5(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP5_MASK) >> AIPS_PACRI_SP5_SHIFT)
+#define AIPS_BRD_PACRI_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRI_SP5(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP5_MASK, AIPS_PACRI_SP5(value)))
+#define AIPS_BWR_PACRI_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP4 field. */
+#define AIPS_RD_PACRI_TP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP4_MASK) >> AIPS_PACRI_TP4_SHIFT)
+#define AIPS_BRD_PACRI_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRI_TP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP4_MASK, AIPS_PACRI_TP4(value)))
+#define AIPS_BWR_PACRI_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP4 field. */
+#define AIPS_RD_PACRI_WP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP4_MASK) >> AIPS_PACRI_WP4_SHIFT)
+#define AIPS_BRD_PACRI_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRI_WP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP4_MASK, AIPS_PACRI_WP4(value)))
+#define AIPS_BWR_PACRI_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP4 field. */
+#define AIPS_RD_PACRI_SP4(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP4_MASK) >> AIPS_PACRI_SP4_SHIFT)
+#define AIPS_BRD_PACRI_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRI_SP4(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP4_MASK, AIPS_PACRI_SP4(value)))
+#define AIPS_BWR_PACRI_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP3 field. */
+#define AIPS_RD_PACRI_TP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP3_MASK) >> AIPS_PACRI_TP3_SHIFT)
+#define AIPS_BRD_PACRI_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRI_TP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP3_MASK, AIPS_PACRI_TP3(value)))
+#define AIPS_BWR_PACRI_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP3 field. */
+#define AIPS_RD_PACRI_WP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP3_MASK) >> AIPS_PACRI_WP3_SHIFT)
+#define AIPS_BRD_PACRI_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRI_WP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP3_MASK, AIPS_PACRI_WP3(value)))
+#define AIPS_BWR_PACRI_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP3 field. */
+#define AIPS_RD_PACRI_SP3(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP3_MASK) >> AIPS_PACRI_SP3_SHIFT)
+#define AIPS_BRD_PACRI_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRI_SP3(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP3_MASK, AIPS_PACRI_SP3(value)))
+#define AIPS_BWR_PACRI_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP2 field. */
+#define AIPS_RD_PACRI_TP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP2_MASK) >> AIPS_PACRI_TP2_SHIFT)
+#define AIPS_BRD_PACRI_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRI_TP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP2_MASK, AIPS_PACRI_TP2(value)))
+#define AIPS_BWR_PACRI_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP2 field. */
+#define AIPS_RD_PACRI_WP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP2_MASK) >> AIPS_PACRI_WP2_SHIFT)
+#define AIPS_BRD_PACRI_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRI_WP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP2_MASK, AIPS_PACRI_WP2(value)))
+#define AIPS_BWR_PACRI_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP2 field. */
+#define AIPS_RD_PACRI_SP2(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP2_MASK) >> AIPS_PACRI_SP2_SHIFT)
+#define AIPS_BRD_PACRI_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRI_SP2(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP2_MASK, AIPS_PACRI_SP2(value)))
+#define AIPS_BWR_PACRI_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP1 field. */
+#define AIPS_RD_PACRI_TP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP1_MASK) >> AIPS_PACRI_TP1_SHIFT)
+#define AIPS_BRD_PACRI_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRI_TP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP1_MASK, AIPS_PACRI_TP1(value)))
+#define AIPS_BWR_PACRI_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP1 field. */
+#define AIPS_RD_PACRI_WP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP1_MASK) >> AIPS_PACRI_WP1_SHIFT)
+#define AIPS_BRD_PACRI_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRI_WP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP1_MASK, AIPS_PACRI_WP1(value)))
+#define AIPS_BWR_PACRI_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP1 field. */
+#define AIPS_RD_PACRI_SP1(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP1_MASK) >> AIPS_PACRI_SP1_SHIFT)
+#define AIPS_BRD_PACRI_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRI_SP1(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP1_MASK, AIPS_PACRI_SP1(value)))
+#define AIPS_BWR_PACRI_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_TP0 field. */
+#define AIPS_RD_PACRI_TP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_TP0_MASK) >> AIPS_PACRI_TP0_SHIFT)
+#define AIPS_BRD_PACRI_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRI_TP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_TP0_MASK, AIPS_PACRI_TP0(value)))
+#define AIPS_BWR_PACRI_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_WP0 field. */
+#define AIPS_RD_PACRI_WP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_WP0_MASK) >> AIPS_PACRI_WP0_SHIFT)
+#define AIPS_BRD_PACRI_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRI_WP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_WP0_MASK, AIPS_PACRI_WP0(value)))
+#define AIPS_BWR_PACRI_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRI, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRI_SP0 field. */
+#define AIPS_RD_PACRI_SP0(base) ((AIPS_PACRI_REG(base) & AIPS_PACRI_SP0_MASK) >> AIPS_PACRI_SP0_SHIFT)
+#define AIPS_BRD_PACRI_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRI_SP0(base, value) (AIPS_RMW_PACRI(base, AIPS_PACRI_SP0_MASK, AIPS_PACRI_SP0(value)))
+#define AIPS_BWR_PACRI_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRI_REG(base), AIPS_PACRI_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRJ - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRJ - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRJ register
+ */
+/*@{*/
+#define AIPS_RD_PACRJ(base)      (AIPS_PACRJ_REG(base))
+#define AIPS_WR_PACRJ(base, value) (AIPS_PACRJ_REG(base) = (value))
+#define AIPS_RMW_PACRJ(base, mask, value) (AIPS_WR_PACRJ(base, (AIPS_RD_PACRJ(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) |  (value)))
+#define AIPS_CLR_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) & ~(value)))
+#define AIPS_TOG_PACRJ(base, value) (AIPS_WR_PACRJ(base, AIPS_RD_PACRJ(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRJ bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRJ, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP7 field. */
+#define AIPS_RD_PACRJ_TP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP7_MASK) >> AIPS_PACRJ_TP7_SHIFT)
+#define AIPS_BRD_PACRJ_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRJ_TP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP7_MASK, AIPS_PACRJ_TP7(value)))
+#define AIPS_BWR_PACRJ_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP7 field. */
+#define AIPS_RD_PACRJ_WP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP7_MASK) >> AIPS_PACRJ_WP7_SHIFT)
+#define AIPS_BRD_PACRJ_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRJ_WP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP7_MASK, AIPS_PACRJ_WP7(value)))
+#define AIPS_BWR_PACRJ_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP7 field. */
+#define AIPS_RD_PACRJ_SP7(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP7_MASK) >> AIPS_PACRJ_SP7_SHIFT)
+#define AIPS_BRD_PACRJ_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRJ_SP7(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP7_MASK, AIPS_PACRJ_SP7(value)))
+#define AIPS_BWR_PACRJ_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP6 field. */
+#define AIPS_RD_PACRJ_TP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP6_MASK) >> AIPS_PACRJ_TP6_SHIFT)
+#define AIPS_BRD_PACRJ_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRJ_TP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP6_MASK, AIPS_PACRJ_TP6(value)))
+#define AIPS_BWR_PACRJ_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP6 field. */
+#define AIPS_RD_PACRJ_WP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP6_MASK) >> AIPS_PACRJ_WP6_SHIFT)
+#define AIPS_BRD_PACRJ_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRJ_WP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP6_MASK, AIPS_PACRJ_WP6(value)))
+#define AIPS_BWR_PACRJ_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP6 field. */
+#define AIPS_RD_PACRJ_SP6(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP6_MASK) >> AIPS_PACRJ_SP6_SHIFT)
+#define AIPS_BRD_PACRJ_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRJ_SP6(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP6_MASK, AIPS_PACRJ_SP6(value)))
+#define AIPS_BWR_PACRJ_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP5 field. */
+#define AIPS_RD_PACRJ_TP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP5_MASK) >> AIPS_PACRJ_TP5_SHIFT)
+#define AIPS_BRD_PACRJ_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRJ_TP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP5_MASK, AIPS_PACRJ_TP5(value)))
+#define AIPS_BWR_PACRJ_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP5 field. */
+#define AIPS_RD_PACRJ_WP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP5_MASK) >> AIPS_PACRJ_WP5_SHIFT)
+#define AIPS_BRD_PACRJ_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRJ_WP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP5_MASK, AIPS_PACRJ_WP5(value)))
+#define AIPS_BWR_PACRJ_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP5 field. */
+#define AIPS_RD_PACRJ_SP5(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP5_MASK) >> AIPS_PACRJ_SP5_SHIFT)
+#define AIPS_BRD_PACRJ_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRJ_SP5(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP5_MASK, AIPS_PACRJ_SP5(value)))
+#define AIPS_BWR_PACRJ_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP4 field. */
+#define AIPS_RD_PACRJ_TP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP4_MASK) >> AIPS_PACRJ_TP4_SHIFT)
+#define AIPS_BRD_PACRJ_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRJ_TP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP4_MASK, AIPS_PACRJ_TP4(value)))
+#define AIPS_BWR_PACRJ_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP4 field. */
+#define AIPS_RD_PACRJ_WP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP4_MASK) >> AIPS_PACRJ_WP4_SHIFT)
+#define AIPS_BRD_PACRJ_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRJ_WP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP4_MASK, AIPS_PACRJ_WP4(value)))
+#define AIPS_BWR_PACRJ_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP4 field. */
+#define AIPS_RD_PACRJ_SP4(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP4_MASK) >> AIPS_PACRJ_SP4_SHIFT)
+#define AIPS_BRD_PACRJ_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRJ_SP4(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP4_MASK, AIPS_PACRJ_SP4(value)))
+#define AIPS_BWR_PACRJ_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP3 field. */
+#define AIPS_RD_PACRJ_TP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP3_MASK) >> AIPS_PACRJ_TP3_SHIFT)
+#define AIPS_BRD_PACRJ_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRJ_TP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP3_MASK, AIPS_PACRJ_TP3(value)))
+#define AIPS_BWR_PACRJ_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP3 field. */
+#define AIPS_RD_PACRJ_WP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP3_MASK) >> AIPS_PACRJ_WP3_SHIFT)
+#define AIPS_BRD_PACRJ_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRJ_WP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP3_MASK, AIPS_PACRJ_WP3(value)))
+#define AIPS_BWR_PACRJ_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP3 field. */
+#define AIPS_RD_PACRJ_SP3(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP3_MASK) >> AIPS_PACRJ_SP3_SHIFT)
+#define AIPS_BRD_PACRJ_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRJ_SP3(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP3_MASK, AIPS_PACRJ_SP3(value)))
+#define AIPS_BWR_PACRJ_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP2 field. */
+#define AIPS_RD_PACRJ_TP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP2_MASK) >> AIPS_PACRJ_TP2_SHIFT)
+#define AIPS_BRD_PACRJ_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRJ_TP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP2_MASK, AIPS_PACRJ_TP2(value)))
+#define AIPS_BWR_PACRJ_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP2 field. */
+#define AIPS_RD_PACRJ_WP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP2_MASK) >> AIPS_PACRJ_WP2_SHIFT)
+#define AIPS_BRD_PACRJ_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRJ_WP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP2_MASK, AIPS_PACRJ_WP2(value)))
+#define AIPS_BWR_PACRJ_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP2 field. */
+#define AIPS_RD_PACRJ_SP2(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP2_MASK) >> AIPS_PACRJ_SP2_SHIFT)
+#define AIPS_BRD_PACRJ_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRJ_SP2(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP2_MASK, AIPS_PACRJ_SP2(value)))
+#define AIPS_BWR_PACRJ_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP1 field. */
+#define AIPS_RD_PACRJ_TP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP1_MASK) >> AIPS_PACRJ_TP1_SHIFT)
+#define AIPS_BRD_PACRJ_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRJ_TP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP1_MASK, AIPS_PACRJ_TP1(value)))
+#define AIPS_BWR_PACRJ_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP1 field. */
+#define AIPS_RD_PACRJ_WP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP1_MASK) >> AIPS_PACRJ_WP1_SHIFT)
+#define AIPS_BRD_PACRJ_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRJ_WP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP1_MASK, AIPS_PACRJ_WP1(value)))
+#define AIPS_BWR_PACRJ_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP1 field. */
+#define AIPS_RD_PACRJ_SP1(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP1_MASK) >> AIPS_PACRJ_SP1_SHIFT)
+#define AIPS_BRD_PACRJ_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRJ_SP1(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP1_MASK, AIPS_PACRJ_SP1(value)))
+#define AIPS_BWR_PACRJ_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_TP0 field. */
+#define AIPS_RD_PACRJ_TP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_TP0_MASK) >> AIPS_PACRJ_TP0_SHIFT)
+#define AIPS_BRD_PACRJ_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRJ_TP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_TP0_MASK, AIPS_PACRJ_TP0(value)))
+#define AIPS_BWR_PACRJ_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_WP0 field. */
+#define AIPS_RD_PACRJ_WP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_WP0_MASK) >> AIPS_PACRJ_WP0_SHIFT)
+#define AIPS_BRD_PACRJ_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRJ_WP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_WP0_MASK, AIPS_PACRJ_WP0(value)))
+#define AIPS_BWR_PACRJ_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRJ, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRJ_SP0 field. */
+#define AIPS_RD_PACRJ_SP0(base) ((AIPS_PACRJ_REG(base) & AIPS_PACRJ_SP0_MASK) >> AIPS_PACRJ_SP0_SHIFT)
+#define AIPS_BRD_PACRJ_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRJ_SP0(base, value) (AIPS_RMW_PACRJ(base, AIPS_PACRJ_SP0_MASK, AIPS_PACRJ_SP0(value)))
+#define AIPS_BWR_PACRJ_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRJ_REG(base), AIPS_PACRJ_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRK - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRK - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRK register
+ */
+/*@{*/
+#define AIPS_RD_PACRK(base)      (AIPS_PACRK_REG(base))
+#define AIPS_WR_PACRK(base, value) (AIPS_PACRK_REG(base) = (value))
+#define AIPS_RMW_PACRK(base, mask, value) (AIPS_WR_PACRK(base, (AIPS_RD_PACRK(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) |  (value)))
+#define AIPS_CLR_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) & ~(value)))
+#define AIPS_TOG_PACRK(base, value) (AIPS_WR_PACRK(base, AIPS_RD_PACRK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRK bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRK, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP7 field. */
+#define AIPS_RD_PACRK_TP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP7_MASK) >> AIPS_PACRK_TP7_SHIFT)
+#define AIPS_BRD_PACRK_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRK_TP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP7_MASK, AIPS_PACRK_TP7(value)))
+#define AIPS_BWR_PACRK_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP7 field. */
+#define AIPS_RD_PACRK_WP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP7_MASK) >> AIPS_PACRK_WP7_SHIFT)
+#define AIPS_BRD_PACRK_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRK_WP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP7_MASK, AIPS_PACRK_WP7(value)))
+#define AIPS_BWR_PACRK_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP7 field. */
+#define AIPS_RD_PACRK_SP7(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP7_MASK) >> AIPS_PACRK_SP7_SHIFT)
+#define AIPS_BRD_PACRK_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRK_SP7(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP7_MASK, AIPS_PACRK_SP7(value)))
+#define AIPS_BWR_PACRK_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP6 field. */
+#define AIPS_RD_PACRK_TP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP6_MASK) >> AIPS_PACRK_TP6_SHIFT)
+#define AIPS_BRD_PACRK_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRK_TP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP6_MASK, AIPS_PACRK_TP6(value)))
+#define AIPS_BWR_PACRK_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP6 field. */
+#define AIPS_RD_PACRK_WP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP6_MASK) >> AIPS_PACRK_WP6_SHIFT)
+#define AIPS_BRD_PACRK_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRK_WP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP6_MASK, AIPS_PACRK_WP6(value)))
+#define AIPS_BWR_PACRK_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP6 field. */
+#define AIPS_RD_PACRK_SP6(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP6_MASK) >> AIPS_PACRK_SP6_SHIFT)
+#define AIPS_BRD_PACRK_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRK_SP6(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP6_MASK, AIPS_PACRK_SP6(value)))
+#define AIPS_BWR_PACRK_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP5 field. */
+#define AIPS_RD_PACRK_TP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP5_MASK) >> AIPS_PACRK_TP5_SHIFT)
+#define AIPS_BRD_PACRK_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRK_TP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP5_MASK, AIPS_PACRK_TP5(value)))
+#define AIPS_BWR_PACRK_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP5 field. */
+#define AIPS_RD_PACRK_WP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP5_MASK) >> AIPS_PACRK_WP5_SHIFT)
+#define AIPS_BRD_PACRK_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRK_WP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP5_MASK, AIPS_PACRK_WP5(value)))
+#define AIPS_BWR_PACRK_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP5 field. */
+#define AIPS_RD_PACRK_SP5(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP5_MASK) >> AIPS_PACRK_SP5_SHIFT)
+#define AIPS_BRD_PACRK_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRK_SP5(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP5_MASK, AIPS_PACRK_SP5(value)))
+#define AIPS_BWR_PACRK_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP4 field. */
+#define AIPS_RD_PACRK_TP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP4_MASK) >> AIPS_PACRK_TP4_SHIFT)
+#define AIPS_BRD_PACRK_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRK_TP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP4_MASK, AIPS_PACRK_TP4(value)))
+#define AIPS_BWR_PACRK_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP4 field. */
+#define AIPS_RD_PACRK_WP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP4_MASK) >> AIPS_PACRK_WP4_SHIFT)
+#define AIPS_BRD_PACRK_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRK_WP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP4_MASK, AIPS_PACRK_WP4(value)))
+#define AIPS_BWR_PACRK_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP4 field. */
+#define AIPS_RD_PACRK_SP4(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP4_MASK) >> AIPS_PACRK_SP4_SHIFT)
+#define AIPS_BRD_PACRK_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRK_SP4(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP4_MASK, AIPS_PACRK_SP4(value)))
+#define AIPS_BWR_PACRK_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP3 field. */
+#define AIPS_RD_PACRK_TP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP3_MASK) >> AIPS_PACRK_TP3_SHIFT)
+#define AIPS_BRD_PACRK_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRK_TP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP3_MASK, AIPS_PACRK_TP3(value)))
+#define AIPS_BWR_PACRK_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP3 field. */
+#define AIPS_RD_PACRK_WP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP3_MASK) >> AIPS_PACRK_WP3_SHIFT)
+#define AIPS_BRD_PACRK_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRK_WP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP3_MASK, AIPS_PACRK_WP3(value)))
+#define AIPS_BWR_PACRK_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP3 field. */
+#define AIPS_RD_PACRK_SP3(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP3_MASK) >> AIPS_PACRK_SP3_SHIFT)
+#define AIPS_BRD_PACRK_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRK_SP3(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP3_MASK, AIPS_PACRK_SP3(value)))
+#define AIPS_BWR_PACRK_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP2 field. */
+#define AIPS_RD_PACRK_TP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP2_MASK) >> AIPS_PACRK_TP2_SHIFT)
+#define AIPS_BRD_PACRK_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRK_TP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP2_MASK, AIPS_PACRK_TP2(value)))
+#define AIPS_BWR_PACRK_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP2 field. */
+#define AIPS_RD_PACRK_WP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP2_MASK) >> AIPS_PACRK_WP2_SHIFT)
+#define AIPS_BRD_PACRK_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRK_WP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP2_MASK, AIPS_PACRK_WP2(value)))
+#define AIPS_BWR_PACRK_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP2 field. */
+#define AIPS_RD_PACRK_SP2(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP2_MASK) >> AIPS_PACRK_SP2_SHIFT)
+#define AIPS_BRD_PACRK_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRK_SP2(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP2_MASK, AIPS_PACRK_SP2(value)))
+#define AIPS_BWR_PACRK_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP1 field. */
+#define AIPS_RD_PACRK_TP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP1_MASK) >> AIPS_PACRK_TP1_SHIFT)
+#define AIPS_BRD_PACRK_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRK_TP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP1_MASK, AIPS_PACRK_TP1(value)))
+#define AIPS_BWR_PACRK_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP1 field. */
+#define AIPS_RD_PACRK_WP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP1_MASK) >> AIPS_PACRK_WP1_SHIFT)
+#define AIPS_BRD_PACRK_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRK_WP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP1_MASK, AIPS_PACRK_WP1(value)))
+#define AIPS_BWR_PACRK_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP1 field. */
+#define AIPS_RD_PACRK_SP1(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP1_MASK) >> AIPS_PACRK_SP1_SHIFT)
+#define AIPS_BRD_PACRK_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRK_SP1(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP1_MASK, AIPS_PACRK_SP1(value)))
+#define AIPS_BWR_PACRK_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_TP0 field. */
+#define AIPS_RD_PACRK_TP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_TP0_MASK) >> AIPS_PACRK_TP0_SHIFT)
+#define AIPS_BRD_PACRK_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRK_TP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_TP0_MASK, AIPS_PACRK_TP0(value)))
+#define AIPS_BWR_PACRK_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_WP0 field. */
+#define AIPS_RD_PACRK_WP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_WP0_MASK) >> AIPS_PACRK_WP0_SHIFT)
+#define AIPS_BRD_PACRK_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRK_WP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_WP0_MASK, AIPS_PACRK_WP0(value)))
+#define AIPS_BWR_PACRK_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRK, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRK_SP0 field. */
+#define AIPS_RD_PACRK_SP0(base) ((AIPS_PACRK_REG(base) & AIPS_PACRK_SP0_MASK) >> AIPS_PACRK_SP0_SHIFT)
+#define AIPS_BRD_PACRK_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRK_SP0(base, value) (AIPS_RMW_PACRK(base, AIPS_PACRK_SP0_MASK, AIPS_PACRK_SP0(value)))
+#define AIPS_BWR_PACRK_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRK_REG(base), AIPS_PACRK_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRL - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRL - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRL register
+ */
+/*@{*/
+#define AIPS_RD_PACRL(base)      (AIPS_PACRL_REG(base))
+#define AIPS_WR_PACRL(base, value) (AIPS_PACRL_REG(base) = (value))
+#define AIPS_RMW_PACRL(base, mask, value) (AIPS_WR_PACRL(base, (AIPS_RD_PACRL(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) |  (value)))
+#define AIPS_CLR_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) & ~(value)))
+#define AIPS_TOG_PACRL(base, value) (AIPS_WR_PACRL(base, AIPS_RD_PACRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRL bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRL, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP7 field. */
+#define AIPS_RD_PACRL_TP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP7_MASK) >> AIPS_PACRL_TP7_SHIFT)
+#define AIPS_BRD_PACRL_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRL_TP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP7_MASK, AIPS_PACRL_TP7(value)))
+#define AIPS_BWR_PACRL_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP7 field. */
+#define AIPS_RD_PACRL_WP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP7_MASK) >> AIPS_PACRL_WP7_SHIFT)
+#define AIPS_BRD_PACRL_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRL_WP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP7_MASK, AIPS_PACRL_WP7(value)))
+#define AIPS_BWR_PACRL_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP7 field. */
+#define AIPS_RD_PACRL_SP7(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP7_MASK) >> AIPS_PACRL_SP7_SHIFT)
+#define AIPS_BRD_PACRL_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRL_SP7(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP7_MASK, AIPS_PACRL_SP7(value)))
+#define AIPS_BWR_PACRL_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP6 field. */
+#define AIPS_RD_PACRL_TP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP6_MASK) >> AIPS_PACRL_TP6_SHIFT)
+#define AIPS_BRD_PACRL_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRL_TP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP6_MASK, AIPS_PACRL_TP6(value)))
+#define AIPS_BWR_PACRL_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP6 field. */
+#define AIPS_RD_PACRL_WP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP6_MASK) >> AIPS_PACRL_WP6_SHIFT)
+#define AIPS_BRD_PACRL_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRL_WP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP6_MASK, AIPS_PACRL_WP6(value)))
+#define AIPS_BWR_PACRL_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP6 field. */
+#define AIPS_RD_PACRL_SP6(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP6_MASK) >> AIPS_PACRL_SP6_SHIFT)
+#define AIPS_BRD_PACRL_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRL_SP6(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP6_MASK, AIPS_PACRL_SP6(value)))
+#define AIPS_BWR_PACRL_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP5 field. */
+#define AIPS_RD_PACRL_TP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP5_MASK) >> AIPS_PACRL_TP5_SHIFT)
+#define AIPS_BRD_PACRL_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRL_TP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP5_MASK, AIPS_PACRL_TP5(value)))
+#define AIPS_BWR_PACRL_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP5 field. */
+#define AIPS_RD_PACRL_WP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP5_MASK) >> AIPS_PACRL_WP5_SHIFT)
+#define AIPS_BRD_PACRL_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRL_WP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP5_MASK, AIPS_PACRL_WP5(value)))
+#define AIPS_BWR_PACRL_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP5 field. */
+#define AIPS_RD_PACRL_SP5(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP5_MASK) >> AIPS_PACRL_SP5_SHIFT)
+#define AIPS_BRD_PACRL_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRL_SP5(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP5_MASK, AIPS_PACRL_SP5(value)))
+#define AIPS_BWR_PACRL_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP4 field. */
+#define AIPS_RD_PACRL_TP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP4_MASK) >> AIPS_PACRL_TP4_SHIFT)
+#define AIPS_BRD_PACRL_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRL_TP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP4_MASK, AIPS_PACRL_TP4(value)))
+#define AIPS_BWR_PACRL_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP4 field. */
+#define AIPS_RD_PACRL_WP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP4_MASK) >> AIPS_PACRL_WP4_SHIFT)
+#define AIPS_BRD_PACRL_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRL_WP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP4_MASK, AIPS_PACRL_WP4(value)))
+#define AIPS_BWR_PACRL_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP4 field. */
+#define AIPS_RD_PACRL_SP4(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP4_MASK) >> AIPS_PACRL_SP4_SHIFT)
+#define AIPS_BRD_PACRL_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRL_SP4(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP4_MASK, AIPS_PACRL_SP4(value)))
+#define AIPS_BWR_PACRL_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP3 field. */
+#define AIPS_RD_PACRL_TP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP3_MASK) >> AIPS_PACRL_TP3_SHIFT)
+#define AIPS_BRD_PACRL_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRL_TP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP3_MASK, AIPS_PACRL_TP3(value)))
+#define AIPS_BWR_PACRL_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP3 field. */
+#define AIPS_RD_PACRL_WP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP3_MASK) >> AIPS_PACRL_WP3_SHIFT)
+#define AIPS_BRD_PACRL_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRL_WP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP3_MASK, AIPS_PACRL_WP3(value)))
+#define AIPS_BWR_PACRL_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP3 field. */
+#define AIPS_RD_PACRL_SP3(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP3_MASK) >> AIPS_PACRL_SP3_SHIFT)
+#define AIPS_BRD_PACRL_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRL_SP3(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP3_MASK, AIPS_PACRL_SP3(value)))
+#define AIPS_BWR_PACRL_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP2 field. */
+#define AIPS_RD_PACRL_TP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP2_MASK) >> AIPS_PACRL_TP2_SHIFT)
+#define AIPS_BRD_PACRL_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRL_TP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP2_MASK, AIPS_PACRL_TP2(value)))
+#define AIPS_BWR_PACRL_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP2 field. */
+#define AIPS_RD_PACRL_WP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP2_MASK) >> AIPS_PACRL_WP2_SHIFT)
+#define AIPS_BRD_PACRL_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRL_WP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP2_MASK, AIPS_PACRL_WP2(value)))
+#define AIPS_BWR_PACRL_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP2 field. */
+#define AIPS_RD_PACRL_SP2(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP2_MASK) >> AIPS_PACRL_SP2_SHIFT)
+#define AIPS_BRD_PACRL_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRL_SP2(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP2_MASK, AIPS_PACRL_SP2(value)))
+#define AIPS_BWR_PACRL_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP1 field. */
+#define AIPS_RD_PACRL_TP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP1_MASK) >> AIPS_PACRL_TP1_SHIFT)
+#define AIPS_BRD_PACRL_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRL_TP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP1_MASK, AIPS_PACRL_TP1(value)))
+#define AIPS_BWR_PACRL_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP1 field. */
+#define AIPS_RD_PACRL_WP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP1_MASK) >> AIPS_PACRL_WP1_SHIFT)
+#define AIPS_BRD_PACRL_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRL_WP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP1_MASK, AIPS_PACRL_WP1(value)))
+#define AIPS_BWR_PACRL_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP1 field. */
+#define AIPS_RD_PACRL_SP1(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP1_MASK) >> AIPS_PACRL_SP1_SHIFT)
+#define AIPS_BRD_PACRL_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRL_SP1(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP1_MASK, AIPS_PACRL_SP1(value)))
+#define AIPS_BWR_PACRL_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_TP0 field. */
+#define AIPS_RD_PACRL_TP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_TP0_MASK) >> AIPS_PACRL_TP0_SHIFT)
+#define AIPS_BRD_PACRL_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRL_TP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_TP0_MASK, AIPS_PACRL_TP0(value)))
+#define AIPS_BWR_PACRL_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_WP0 field. */
+#define AIPS_RD_PACRL_WP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_WP0_MASK) >> AIPS_PACRL_WP0_SHIFT)
+#define AIPS_BRD_PACRL_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRL_WP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_WP0_MASK, AIPS_PACRL_WP0(value)))
+#define AIPS_BWR_PACRL_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRL, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRL_SP0 field. */
+#define AIPS_RD_PACRL_SP0(base) ((AIPS_PACRL_REG(base) & AIPS_PACRL_SP0_MASK) >> AIPS_PACRL_SP0_SHIFT)
+#define AIPS_BRD_PACRL_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRL_SP0(base, value) (AIPS_RMW_PACRL(base, AIPS_PACRL_SP0_MASK, AIPS_PACRL_SP0(value)))
+#define AIPS_BWR_PACRL_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRL_REG(base), AIPS_PACRL_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRM - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRM - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRM register
+ */
+/*@{*/
+#define AIPS_RD_PACRM(base)      (AIPS_PACRM_REG(base))
+#define AIPS_WR_PACRM(base, value) (AIPS_PACRM_REG(base) = (value))
+#define AIPS_RMW_PACRM(base, mask, value) (AIPS_WR_PACRM(base, (AIPS_RD_PACRM(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) |  (value)))
+#define AIPS_CLR_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) & ~(value)))
+#define AIPS_TOG_PACRM(base, value) (AIPS_WR_PACRM(base, AIPS_RD_PACRM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRM bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRM, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP7 field. */
+#define AIPS_RD_PACRM_TP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP7_MASK) >> AIPS_PACRM_TP7_SHIFT)
+#define AIPS_BRD_PACRM_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRM_TP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP7_MASK, AIPS_PACRM_TP7(value)))
+#define AIPS_BWR_PACRM_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP7 field. */
+#define AIPS_RD_PACRM_WP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP7_MASK) >> AIPS_PACRM_WP7_SHIFT)
+#define AIPS_BRD_PACRM_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRM_WP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP7_MASK, AIPS_PACRM_WP7(value)))
+#define AIPS_BWR_PACRM_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP7 field. */
+#define AIPS_RD_PACRM_SP7(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP7_MASK) >> AIPS_PACRM_SP7_SHIFT)
+#define AIPS_BRD_PACRM_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRM_SP7(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP7_MASK, AIPS_PACRM_SP7(value)))
+#define AIPS_BWR_PACRM_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP6 field. */
+#define AIPS_RD_PACRM_TP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP6_MASK) >> AIPS_PACRM_TP6_SHIFT)
+#define AIPS_BRD_PACRM_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRM_TP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP6_MASK, AIPS_PACRM_TP6(value)))
+#define AIPS_BWR_PACRM_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP6 field. */
+#define AIPS_RD_PACRM_WP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP6_MASK) >> AIPS_PACRM_WP6_SHIFT)
+#define AIPS_BRD_PACRM_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRM_WP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP6_MASK, AIPS_PACRM_WP6(value)))
+#define AIPS_BWR_PACRM_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP6 field. */
+#define AIPS_RD_PACRM_SP6(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP6_MASK) >> AIPS_PACRM_SP6_SHIFT)
+#define AIPS_BRD_PACRM_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRM_SP6(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP6_MASK, AIPS_PACRM_SP6(value)))
+#define AIPS_BWR_PACRM_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP5 field. */
+#define AIPS_RD_PACRM_TP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP5_MASK) >> AIPS_PACRM_TP5_SHIFT)
+#define AIPS_BRD_PACRM_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRM_TP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP5_MASK, AIPS_PACRM_TP5(value)))
+#define AIPS_BWR_PACRM_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP5 field. */
+#define AIPS_RD_PACRM_WP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP5_MASK) >> AIPS_PACRM_WP5_SHIFT)
+#define AIPS_BRD_PACRM_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRM_WP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP5_MASK, AIPS_PACRM_WP5(value)))
+#define AIPS_BWR_PACRM_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP5 field. */
+#define AIPS_RD_PACRM_SP5(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP5_MASK) >> AIPS_PACRM_SP5_SHIFT)
+#define AIPS_BRD_PACRM_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRM_SP5(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP5_MASK, AIPS_PACRM_SP5(value)))
+#define AIPS_BWR_PACRM_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP4 field. */
+#define AIPS_RD_PACRM_TP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP4_MASK) >> AIPS_PACRM_TP4_SHIFT)
+#define AIPS_BRD_PACRM_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRM_TP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP4_MASK, AIPS_PACRM_TP4(value)))
+#define AIPS_BWR_PACRM_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP4 field. */
+#define AIPS_RD_PACRM_WP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP4_MASK) >> AIPS_PACRM_WP4_SHIFT)
+#define AIPS_BRD_PACRM_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRM_WP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP4_MASK, AIPS_PACRM_WP4(value)))
+#define AIPS_BWR_PACRM_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP4 field. */
+#define AIPS_RD_PACRM_SP4(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP4_MASK) >> AIPS_PACRM_SP4_SHIFT)
+#define AIPS_BRD_PACRM_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRM_SP4(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP4_MASK, AIPS_PACRM_SP4(value)))
+#define AIPS_BWR_PACRM_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP3 field. */
+#define AIPS_RD_PACRM_TP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP3_MASK) >> AIPS_PACRM_TP3_SHIFT)
+#define AIPS_BRD_PACRM_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRM_TP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP3_MASK, AIPS_PACRM_TP3(value)))
+#define AIPS_BWR_PACRM_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP3 field. */
+#define AIPS_RD_PACRM_WP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP3_MASK) >> AIPS_PACRM_WP3_SHIFT)
+#define AIPS_BRD_PACRM_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRM_WP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP3_MASK, AIPS_PACRM_WP3(value)))
+#define AIPS_BWR_PACRM_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP3 field. */
+#define AIPS_RD_PACRM_SP3(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP3_MASK) >> AIPS_PACRM_SP3_SHIFT)
+#define AIPS_BRD_PACRM_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRM_SP3(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP3_MASK, AIPS_PACRM_SP3(value)))
+#define AIPS_BWR_PACRM_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP2 field. */
+#define AIPS_RD_PACRM_TP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP2_MASK) >> AIPS_PACRM_TP2_SHIFT)
+#define AIPS_BRD_PACRM_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRM_TP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP2_MASK, AIPS_PACRM_TP2(value)))
+#define AIPS_BWR_PACRM_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP2 field. */
+#define AIPS_RD_PACRM_WP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP2_MASK) >> AIPS_PACRM_WP2_SHIFT)
+#define AIPS_BRD_PACRM_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRM_WP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP2_MASK, AIPS_PACRM_WP2(value)))
+#define AIPS_BWR_PACRM_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP2 field. */
+#define AIPS_RD_PACRM_SP2(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP2_MASK) >> AIPS_PACRM_SP2_SHIFT)
+#define AIPS_BRD_PACRM_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRM_SP2(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP2_MASK, AIPS_PACRM_SP2(value)))
+#define AIPS_BWR_PACRM_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP1 field. */
+#define AIPS_RD_PACRM_TP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP1_MASK) >> AIPS_PACRM_TP1_SHIFT)
+#define AIPS_BRD_PACRM_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRM_TP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP1_MASK, AIPS_PACRM_TP1(value)))
+#define AIPS_BWR_PACRM_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP1 field. */
+#define AIPS_RD_PACRM_WP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP1_MASK) >> AIPS_PACRM_WP1_SHIFT)
+#define AIPS_BRD_PACRM_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRM_WP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP1_MASK, AIPS_PACRM_WP1(value)))
+#define AIPS_BWR_PACRM_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP1 field. */
+#define AIPS_RD_PACRM_SP1(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP1_MASK) >> AIPS_PACRM_SP1_SHIFT)
+#define AIPS_BRD_PACRM_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRM_SP1(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP1_MASK, AIPS_PACRM_SP1(value)))
+#define AIPS_BWR_PACRM_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_TP0 field. */
+#define AIPS_RD_PACRM_TP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_TP0_MASK) >> AIPS_PACRM_TP0_SHIFT)
+#define AIPS_BRD_PACRM_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRM_TP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_TP0_MASK, AIPS_PACRM_TP0(value)))
+#define AIPS_BWR_PACRM_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_WP0 field. */
+#define AIPS_RD_PACRM_WP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_WP0_MASK) >> AIPS_PACRM_WP0_SHIFT)
+#define AIPS_BRD_PACRM_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRM_WP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_WP0_MASK, AIPS_PACRM_WP0(value)))
+#define AIPS_BWR_PACRM_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRM, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRM_SP0 field. */
+#define AIPS_RD_PACRM_SP0(base) ((AIPS_PACRM_REG(base) & AIPS_PACRM_SP0_MASK) >> AIPS_PACRM_SP0_SHIFT)
+#define AIPS_BRD_PACRM_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRM_SP0(base, value) (AIPS_RMW_PACRM(base, AIPS_PACRM_SP0_MASK, AIPS_PACRM_SP0(value)))
+#define AIPS_BWR_PACRM_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRM_REG(base), AIPS_PACRM_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRN - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRN - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRN register
+ */
+/*@{*/
+#define AIPS_RD_PACRN(base)      (AIPS_PACRN_REG(base))
+#define AIPS_WR_PACRN(base, value) (AIPS_PACRN_REG(base) = (value))
+#define AIPS_RMW_PACRN(base, mask, value) (AIPS_WR_PACRN(base, (AIPS_RD_PACRN(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) |  (value)))
+#define AIPS_CLR_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) & ~(value)))
+#define AIPS_TOG_PACRN(base, value) (AIPS_WR_PACRN(base, AIPS_RD_PACRN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRN bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRN, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP7 field. */
+#define AIPS_RD_PACRN_TP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP7_MASK) >> AIPS_PACRN_TP7_SHIFT)
+#define AIPS_BRD_PACRN_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRN_TP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP7_MASK, AIPS_PACRN_TP7(value)))
+#define AIPS_BWR_PACRN_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP7 field. */
+#define AIPS_RD_PACRN_WP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP7_MASK) >> AIPS_PACRN_WP7_SHIFT)
+#define AIPS_BRD_PACRN_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRN_WP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP7_MASK, AIPS_PACRN_WP7(value)))
+#define AIPS_BWR_PACRN_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP7 field. */
+#define AIPS_RD_PACRN_SP7(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP7_MASK) >> AIPS_PACRN_SP7_SHIFT)
+#define AIPS_BRD_PACRN_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRN_SP7(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP7_MASK, AIPS_PACRN_SP7(value)))
+#define AIPS_BWR_PACRN_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP6 field. */
+#define AIPS_RD_PACRN_TP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP6_MASK) >> AIPS_PACRN_TP6_SHIFT)
+#define AIPS_BRD_PACRN_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRN_TP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP6_MASK, AIPS_PACRN_TP6(value)))
+#define AIPS_BWR_PACRN_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP6 field. */
+#define AIPS_RD_PACRN_WP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP6_MASK) >> AIPS_PACRN_WP6_SHIFT)
+#define AIPS_BRD_PACRN_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRN_WP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP6_MASK, AIPS_PACRN_WP6(value)))
+#define AIPS_BWR_PACRN_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP6 field. */
+#define AIPS_RD_PACRN_SP6(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP6_MASK) >> AIPS_PACRN_SP6_SHIFT)
+#define AIPS_BRD_PACRN_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRN_SP6(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP6_MASK, AIPS_PACRN_SP6(value)))
+#define AIPS_BWR_PACRN_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP5 field. */
+#define AIPS_RD_PACRN_TP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP5_MASK) >> AIPS_PACRN_TP5_SHIFT)
+#define AIPS_BRD_PACRN_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRN_TP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP5_MASK, AIPS_PACRN_TP5(value)))
+#define AIPS_BWR_PACRN_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP5 field. */
+#define AIPS_RD_PACRN_WP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP5_MASK) >> AIPS_PACRN_WP5_SHIFT)
+#define AIPS_BRD_PACRN_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRN_WP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP5_MASK, AIPS_PACRN_WP5(value)))
+#define AIPS_BWR_PACRN_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP5 field. */
+#define AIPS_RD_PACRN_SP5(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP5_MASK) >> AIPS_PACRN_SP5_SHIFT)
+#define AIPS_BRD_PACRN_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRN_SP5(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP5_MASK, AIPS_PACRN_SP5(value)))
+#define AIPS_BWR_PACRN_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP4 field. */
+#define AIPS_RD_PACRN_TP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP4_MASK) >> AIPS_PACRN_TP4_SHIFT)
+#define AIPS_BRD_PACRN_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRN_TP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP4_MASK, AIPS_PACRN_TP4(value)))
+#define AIPS_BWR_PACRN_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP4 field. */
+#define AIPS_RD_PACRN_WP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP4_MASK) >> AIPS_PACRN_WP4_SHIFT)
+#define AIPS_BRD_PACRN_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRN_WP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP4_MASK, AIPS_PACRN_WP4(value)))
+#define AIPS_BWR_PACRN_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP4 field. */
+#define AIPS_RD_PACRN_SP4(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP4_MASK) >> AIPS_PACRN_SP4_SHIFT)
+#define AIPS_BRD_PACRN_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRN_SP4(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP4_MASK, AIPS_PACRN_SP4(value)))
+#define AIPS_BWR_PACRN_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP3 field. */
+#define AIPS_RD_PACRN_TP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP3_MASK) >> AIPS_PACRN_TP3_SHIFT)
+#define AIPS_BRD_PACRN_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRN_TP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP3_MASK, AIPS_PACRN_TP3(value)))
+#define AIPS_BWR_PACRN_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP3 field. */
+#define AIPS_RD_PACRN_WP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP3_MASK) >> AIPS_PACRN_WP3_SHIFT)
+#define AIPS_BRD_PACRN_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRN_WP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP3_MASK, AIPS_PACRN_WP3(value)))
+#define AIPS_BWR_PACRN_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP3 field. */
+#define AIPS_RD_PACRN_SP3(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP3_MASK) >> AIPS_PACRN_SP3_SHIFT)
+#define AIPS_BRD_PACRN_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRN_SP3(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP3_MASK, AIPS_PACRN_SP3(value)))
+#define AIPS_BWR_PACRN_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP2 field. */
+#define AIPS_RD_PACRN_TP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP2_MASK) >> AIPS_PACRN_TP2_SHIFT)
+#define AIPS_BRD_PACRN_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRN_TP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP2_MASK, AIPS_PACRN_TP2(value)))
+#define AIPS_BWR_PACRN_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP2 field. */
+#define AIPS_RD_PACRN_WP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP2_MASK) >> AIPS_PACRN_WP2_SHIFT)
+#define AIPS_BRD_PACRN_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRN_WP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP2_MASK, AIPS_PACRN_WP2(value)))
+#define AIPS_BWR_PACRN_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP2 field. */
+#define AIPS_RD_PACRN_SP2(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP2_MASK) >> AIPS_PACRN_SP2_SHIFT)
+#define AIPS_BRD_PACRN_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRN_SP2(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP2_MASK, AIPS_PACRN_SP2(value)))
+#define AIPS_BWR_PACRN_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP1 field. */
+#define AIPS_RD_PACRN_TP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP1_MASK) >> AIPS_PACRN_TP1_SHIFT)
+#define AIPS_BRD_PACRN_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRN_TP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP1_MASK, AIPS_PACRN_TP1(value)))
+#define AIPS_BWR_PACRN_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP1 field. */
+#define AIPS_RD_PACRN_WP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP1_MASK) >> AIPS_PACRN_WP1_SHIFT)
+#define AIPS_BRD_PACRN_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRN_WP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP1_MASK, AIPS_PACRN_WP1(value)))
+#define AIPS_BWR_PACRN_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP1 field. */
+#define AIPS_RD_PACRN_SP1(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP1_MASK) >> AIPS_PACRN_SP1_SHIFT)
+#define AIPS_BRD_PACRN_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRN_SP1(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP1_MASK, AIPS_PACRN_SP1(value)))
+#define AIPS_BWR_PACRN_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_TP0 field. */
+#define AIPS_RD_PACRN_TP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_TP0_MASK) >> AIPS_PACRN_TP0_SHIFT)
+#define AIPS_BRD_PACRN_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRN_TP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_TP0_MASK, AIPS_PACRN_TP0(value)))
+#define AIPS_BWR_PACRN_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_WP0 field. */
+#define AIPS_RD_PACRN_WP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_WP0_MASK) >> AIPS_PACRN_WP0_SHIFT)
+#define AIPS_BRD_PACRN_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRN_WP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_WP0_MASK, AIPS_PACRN_WP0(value)))
+#define AIPS_BWR_PACRN_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRN, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRN_SP0 field. */
+#define AIPS_RD_PACRN_SP0(base) ((AIPS_PACRN_REG(base) & AIPS_PACRN_SP0_MASK) >> AIPS_PACRN_SP0_SHIFT)
+#define AIPS_BRD_PACRN_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRN_SP0(base, value) (AIPS_RMW_PACRN(base, AIPS_PACRN_SP0_MASK, AIPS_PACRN_SP0(value)))
+#define AIPS_BWR_PACRN_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRN_REG(base), AIPS_PACRN_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRO - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRO - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRO register
+ */
+/*@{*/
+#define AIPS_RD_PACRO(base)      (AIPS_PACRO_REG(base))
+#define AIPS_WR_PACRO(base, value) (AIPS_PACRO_REG(base) = (value))
+#define AIPS_RMW_PACRO(base, mask, value) (AIPS_WR_PACRO(base, (AIPS_RD_PACRO(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) |  (value)))
+#define AIPS_CLR_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) & ~(value)))
+#define AIPS_TOG_PACRO(base, value) (AIPS_WR_PACRO(base, AIPS_RD_PACRO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRO bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRO, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP7 field. */
+#define AIPS_RD_PACRO_TP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP7_MASK) >> AIPS_PACRO_TP7_SHIFT)
+#define AIPS_BRD_PACRO_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRO_TP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP7_MASK, AIPS_PACRO_TP7(value)))
+#define AIPS_BWR_PACRO_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP7 field. */
+#define AIPS_RD_PACRO_WP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP7_MASK) >> AIPS_PACRO_WP7_SHIFT)
+#define AIPS_BRD_PACRO_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRO_WP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP7_MASK, AIPS_PACRO_WP7(value)))
+#define AIPS_BWR_PACRO_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP7 field. */
+#define AIPS_RD_PACRO_SP7(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP7_MASK) >> AIPS_PACRO_SP7_SHIFT)
+#define AIPS_BRD_PACRO_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRO_SP7(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP7_MASK, AIPS_PACRO_SP7(value)))
+#define AIPS_BWR_PACRO_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP6 field. */
+#define AIPS_RD_PACRO_TP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP6_MASK) >> AIPS_PACRO_TP6_SHIFT)
+#define AIPS_BRD_PACRO_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRO_TP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP6_MASK, AIPS_PACRO_TP6(value)))
+#define AIPS_BWR_PACRO_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP6 field. */
+#define AIPS_RD_PACRO_WP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP6_MASK) >> AIPS_PACRO_WP6_SHIFT)
+#define AIPS_BRD_PACRO_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRO_WP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP6_MASK, AIPS_PACRO_WP6(value)))
+#define AIPS_BWR_PACRO_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP6 field. */
+#define AIPS_RD_PACRO_SP6(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP6_MASK) >> AIPS_PACRO_SP6_SHIFT)
+#define AIPS_BRD_PACRO_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRO_SP6(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP6_MASK, AIPS_PACRO_SP6(value)))
+#define AIPS_BWR_PACRO_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP5 field. */
+#define AIPS_RD_PACRO_TP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP5_MASK) >> AIPS_PACRO_TP5_SHIFT)
+#define AIPS_BRD_PACRO_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRO_TP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP5_MASK, AIPS_PACRO_TP5(value)))
+#define AIPS_BWR_PACRO_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP5 field. */
+#define AIPS_RD_PACRO_WP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP5_MASK) >> AIPS_PACRO_WP5_SHIFT)
+#define AIPS_BRD_PACRO_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRO_WP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP5_MASK, AIPS_PACRO_WP5(value)))
+#define AIPS_BWR_PACRO_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP5 field. */
+#define AIPS_RD_PACRO_SP5(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP5_MASK) >> AIPS_PACRO_SP5_SHIFT)
+#define AIPS_BRD_PACRO_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRO_SP5(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP5_MASK, AIPS_PACRO_SP5(value)))
+#define AIPS_BWR_PACRO_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP4 field. */
+#define AIPS_RD_PACRO_TP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP4_MASK) >> AIPS_PACRO_TP4_SHIFT)
+#define AIPS_BRD_PACRO_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRO_TP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP4_MASK, AIPS_PACRO_TP4(value)))
+#define AIPS_BWR_PACRO_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP4 field. */
+#define AIPS_RD_PACRO_WP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP4_MASK) >> AIPS_PACRO_WP4_SHIFT)
+#define AIPS_BRD_PACRO_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRO_WP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP4_MASK, AIPS_PACRO_WP4(value)))
+#define AIPS_BWR_PACRO_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP4 field. */
+#define AIPS_RD_PACRO_SP4(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP4_MASK) >> AIPS_PACRO_SP4_SHIFT)
+#define AIPS_BRD_PACRO_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRO_SP4(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP4_MASK, AIPS_PACRO_SP4(value)))
+#define AIPS_BWR_PACRO_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP3 field. */
+#define AIPS_RD_PACRO_TP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP3_MASK) >> AIPS_PACRO_TP3_SHIFT)
+#define AIPS_BRD_PACRO_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRO_TP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP3_MASK, AIPS_PACRO_TP3(value)))
+#define AIPS_BWR_PACRO_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP3 field. */
+#define AIPS_RD_PACRO_WP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP3_MASK) >> AIPS_PACRO_WP3_SHIFT)
+#define AIPS_BRD_PACRO_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRO_WP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP3_MASK, AIPS_PACRO_WP3(value)))
+#define AIPS_BWR_PACRO_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP3 field. */
+#define AIPS_RD_PACRO_SP3(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP3_MASK) >> AIPS_PACRO_SP3_SHIFT)
+#define AIPS_BRD_PACRO_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRO_SP3(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP3_MASK, AIPS_PACRO_SP3(value)))
+#define AIPS_BWR_PACRO_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP2 field. */
+#define AIPS_RD_PACRO_TP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP2_MASK) >> AIPS_PACRO_TP2_SHIFT)
+#define AIPS_BRD_PACRO_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRO_TP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP2_MASK, AIPS_PACRO_TP2(value)))
+#define AIPS_BWR_PACRO_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP2 field. */
+#define AIPS_RD_PACRO_WP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP2_MASK) >> AIPS_PACRO_WP2_SHIFT)
+#define AIPS_BRD_PACRO_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRO_WP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP2_MASK, AIPS_PACRO_WP2(value)))
+#define AIPS_BWR_PACRO_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP2 field. */
+#define AIPS_RD_PACRO_SP2(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP2_MASK) >> AIPS_PACRO_SP2_SHIFT)
+#define AIPS_BRD_PACRO_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRO_SP2(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP2_MASK, AIPS_PACRO_SP2(value)))
+#define AIPS_BWR_PACRO_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP1 field. */
+#define AIPS_RD_PACRO_TP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP1_MASK) >> AIPS_PACRO_TP1_SHIFT)
+#define AIPS_BRD_PACRO_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRO_TP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP1_MASK, AIPS_PACRO_TP1(value)))
+#define AIPS_BWR_PACRO_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP1 field. */
+#define AIPS_RD_PACRO_WP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP1_MASK) >> AIPS_PACRO_WP1_SHIFT)
+#define AIPS_BRD_PACRO_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRO_WP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP1_MASK, AIPS_PACRO_WP1(value)))
+#define AIPS_BWR_PACRO_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP1 field. */
+#define AIPS_RD_PACRO_SP1(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP1_MASK) >> AIPS_PACRO_SP1_SHIFT)
+#define AIPS_BRD_PACRO_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRO_SP1(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP1_MASK, AIPS_PACRO_SP1(value)))
+#define AIPS_BWR_PACRO_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_TP0 field. */
+#define AIPS_RD_PACRO_TP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_TP0_MASK) >> AIPS_PACRO_TP0_SHIFT)
+#define AIPS_BRD_PACRO_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRO_TP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_TP0_MASK, AIPS_PACRO_TP0(value)))
+#define AIPS_BWR_PACRO_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_WP0 field. */
+#define AIPS_RD_PACRO_WP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_WP0_MASK) >> AIPS_PACRO_WP0_SHIFT)
+#define AIPS_BRD_PACRO_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRO_WP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_WP0_MASK, AIPS_PACRO_WP0(value)))
+#define AIPS_BWR_PACRO_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRO, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRO_SP0 field. */
+#define AIPS_RD_PACRO_SP0(base) ((AIPS_PACRO_REG(base) & AIPS_PACRO_SP0_MASK) >> AIPS_PACRO_SP0_SHIFT)
+#define AIPS_BRD_PACRO_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRO_SP0(base, value) (AIPS_RMW_PACRO(base, AIPS_PACRO_SP0_MASK, AIPS_PACRO_SP0(value)))
+#define AIPS_BWR_PACRO_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRO_REG(base), AIPS_PACRO_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRP - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRP - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44444444U
+ *
+ * This section describes PACR registers E-P, which control peripheral slots
+ * 32-127. See PACRPeripheral Access Control Register for the description of these
+ * registers.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRP register
+ */
+/*@{*/
+#define AIPS_RD_PACRP(base)      (AIPS_PACRP_REG(base))
+#define AIPS_WR_PACRP(base, value) (AIPS_PACRP_REG(base) = (value))
+#define AIPS_RMW_PACRP(base, mask, value) (AIPS_WR_PACRP(base, (AIPS_RD_PACRP(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) |  (value)))
+#define AIPS_CLR_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) & ~(value)))
+#define AIPS_TOG_PACRP(base, value) (AIPS_WR_PACRP(base, AIPS_RD_PACRP(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRP bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRP, field TP7[0] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP7 field. */
+#define AIPS_RD_PACRP_TP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP7_MASK) >> AIPS_PACRP_TP7_SHIFT)
+#define AIPS_BRD_PACRP_TP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP7_SHIFT))
+
+/*! @brief Set the TP7 field to a new value. */
+#define AIPS_WR_PACRP_TP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP7_MASK, AIPS_PACRP_TP7(value)))
+#define AIPS_BWR_PACRP_TP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP7[1] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP7 field. */
+#define AIPS_RD_PACRP_WP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP7_MASK) >> AIPS_PACRP_WP7_SHIFT)
+#define AIPS_BRD_PACRP_WP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP7_SHIFT))
+
+/*! @brief Set the WP7 field to a new value. */
+#define AIPS_WR_PACRP_WP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP7_MASK, AIPS_PACRP_WP7(value)))
+#define AIPS_BWR_PACRP_WP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP7[2] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP7 field. */
+#define AIPS_RD_PACRP_SP7(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP7_MASK) >> AIPS_PACRP_SP7_SHIFT)
+#define AIPS_BRD_PACRP_SP7(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP7_SHIFT))
+
+/*! @brief Set the SP7 field to a new value. */
+#define AIPS_WR_PACRP_SP7(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP7_MASK, AIPS_PACRP_SP7(value)))
+#define AIPS_BWR_PACRP_SP7(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP6[4] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP6 field. */
+#define AIPS_RD_PACRP_TP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP6_MASK) >> AIPS_PACRP_TP6_SHIFT)
+#define AIPS_BRD_PACRP_TP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP6_SHIFT))
+
+/*! @brief Set the TP6 field to a new value. */
+#define AIPS_WR_PACRP_TP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP6_MASK, AIPS_PACRP_TP6(value)))
+#define AIPS_BWR_PACRP_TP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP6[5] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP6 field. */
+#define AIPS_RD_PACRP_WP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP6_MASK) >> AIPS_PACRP_WP6_SHIFT)
+#define AIPS_BRD_PACRP_WP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP6_SHIFT))
+
+/*! @brief Set the WP6 field to a new value. */
+#define AIPS_WR_PACRP_WP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP6_MASK, AIPS_PACRP_WP6(value)))
+#define AIPS_BWR_PACRP_WP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP6[6] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP6 field. */
+#define AIPS_RD_PACRP_SP6(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP6_MASK) >> AIPS_PACRP_SP6_SHIFT)
+#define AIPS_BRD_PACRP_SP6(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP6_SHIFT))
+
+/*! @brief Set the SP6 field to a new value. */
+#define AIPS_WR_PACRP_SP6(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP6_MASK, AIPS_PACRP_SP6(value)))
+#define AIPS_BWR_PACRP_SP6(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP5[8] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP5 field. */
+#define AIPS_RD_PACRP_TP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP5_MASK) >> AIPS_PACRP_TP5_SHIFT)
+#define AIPS_BRD_PACRP_TP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP5_SHIFT))
+
+/*! @brief Set the TP5 field to a new value. */
+#define AIPS_WR_PACRP_TP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP5_MASK, AIPS_PACRP_TP5(value)))
+#define AIPS_BWR_PACRP_TP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP5[9] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP5 field. */
+#define AIPS_RD_PACRP_WP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP5_MASK) >> AIPS_PACRP_WP5_SHIFT)
+#define AIPS_BRD_PACRP_WP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP5_SHIFT))
+
+/*! @brief Set the WP5 field to a new value. */
+#define AIPS_WR_PACRP_WP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP5_MASK, AIPS_PACRP_WP5(value)))
+#define AIPS_BWR_PACRP_WP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP5[10] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP5 field. */
+#define AIPS_RD_PACRP_SP5(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP5_MASK) >> AIPS_PACRP_SP5_SHIFT)
+#define AIPS_BRD_PACRP_SP5(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP5_SHIFT))
+
+/*! @brief Set the SP5 field to a new value. */
+#define AIPS_WR_PACRP_SP5(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP5_MASK, AIPS_PACRP_SP5(value)))
+#define AIPS_BWR_PACRP_SP5(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP4[12] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP4 field. */
+#define AIPS_RD_PACRP_TP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP4_MASK) >> AIPS_PACRP_TP4_SHIFT)
+#define AIPS_BRD_PACRP_TP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP4_SHIFT))
+
+/*! @brief Set the TP4 field to a new value. */
+#define AIPS_WR_PACRP_TP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP4_MASK, AIPS_PACRP_TP4(value)))
+#define AIPS_BWR_PACRP_TP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP4[13] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP4 field. */
+#define AIPS_RD_PACRP_WP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP4_MASK) >> AIPS_PACRP_WP4_SHIFT)
+#define AIPS_BRD_PACRP_WP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP4_SHIFT))
+
+/*! @brief Set the WP4 field to a new value. */
+#define AIPS_WR_PACRP_WP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP4_MASK, AIPS_PACRP_WP4(value)))
+#define AIPS_BWR_PACRP_WP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP4[14] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP4 field. */
+#define AIPS_RD_PACRP_SP4(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP4_MASK) >> AIPS_PACRP_SP4_SHIFT)
+#define AIPS_BRD_PACRP_SP4(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP4_SHIFT))
+
+/*! @brief Set the SP4 field to a new value. */
+#define AIPS_WR_PACRP_SP4(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP4_MASK, AIPS_PACRP_SP4(value)))
+#define AIPS_BWR_PACRP_SP4(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP3[16] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP3 field. */
+#define AIPS_RD_PACRP_TP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP3_MASK) >> AIPS_PACRP_TP3_SHIFT)
+#define AIPS_BRD_PACRP_TP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP3_SHIFT))
+
+/*! @brief Set the TP3 field to a new value. */
+#define AIPS_WR_PACRP_TP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP3_MASK, AIPS_PACRP_TP3(value)))
+#define AIPS_BWR_PACRP_TP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP3[17] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP3 field. */
+#define AIPS_RD_PACRP_WP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP3_MASK) >> AIPS_PACRP_WP3_SHIFT)
+#define AIPS_BRD_PACRP_WP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP3_SHIFT))
+
+/*! @brief Set the WP3 field to a new value. */
+#define AIPS_WR_PACRP_WP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP3_MASK, AIPS_PACRP_WP3(value)))
+#define AIPS_BWR_PACRP_WP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP3[18] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP3 field. */
+#define AIPS_RD_PACRP_SP3(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP3_MASK) >> AIPS_PACRP_SP3_SHIFT)
+#define AIPS_BRD_PACRP_SP3(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP3_SHIFT))
+
+/*! @brief Set the SP3 field to a new value. */
+#define AIPS_WR_PACRP_SP3(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP3_MASK, AIPS_PACRP_SP3(value)))
+#define AIPS_BWR_PACRP_SP3(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP2[20] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP2 field. */
+#define AIPS_RD_PACRP_TP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP2_MASK) >> AIPS_PACRP_TP2_SHIFT)
+#define AIPS_BRD_PACRP_TP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP2_SHIFT))
+
+/*! @brief Set the TP2 field to a new value. */
+#define AIPS_WR_PACRP_TP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP2_MASK, AIPS_PACRP_TP2(value)))
+#define AIPS_BWR_PACRP_TP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP2[21] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP2 field. */
+#define AIPS_RD_PACRP_WP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP2_MASK) >> AIPS_PACRP_WP2_SHIFT)
+#define AIPS_BRD_PACRP_WP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP2_SHIFT))
+
+/*! @brief Set the WP2 field to a new value. */
+#define AIPS_WR_PACRP_WP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP2_MASK, AIPS_PACRP_WP2(value)))
+#define AIPS_BWR_PACRP_WP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP2[22] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP2 field. */
+#define AIPS_RD_PACRP_SP2(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP2_MASK) >> AIPS_PACRP_SP2_SHIFT)
+#define AIPS_BRD_PACRP_SP2(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP2_SHIFT))
+
+/*! @brief Set the SP2 field to a new value. */
+#define AIPS_WR_PACRP_SP2(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP2_MASK, AIPS_PACRP_SP2(value)))
+#define AIPS_BWR_PACRP_SP2(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP1 field. */
+#define AIPS_RD_PACRP_TP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP1_MASK) >> AIPS_PACRP_TP1_SHIFT)
+#define AIPS_BRD_PACRP_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRP_TP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP1_MASK, AIPS_PACRP_TP1(value)))
+#define AIPS_BWR_PACRP_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP1 field. */
+#define AIPS_RD_PACRP_WP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP1_MASK) >> AIPS_PACRP_WP1_SHIFT)
+#define AIPS_BRD_PACRP_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRP_WP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP1_MASK, AIPS_PACRP_WP1(value)))
+#define AIPS_BWR_PACRP_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master must
+ * be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP1 field. */
+#define AIPS_RD_PACRP_SP1(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP1_MASK) >> AIPS_PACRP_SP1_SHIFT)
+#define AIPS_BRD_PACRP_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRP_SP1(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP1_MASK, AIPS_PACRP_SP1(value)))
+#define AIPS_BWR_PACRP_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this bit is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_TP0 field. */
+#define AIPS_RD_PACRP_TP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_TP0_MASK) >> AIPS_PACRP_TP0_SHIFT)
+#define AIPS_BRD_PACRP_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRP_TP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_TP0_MASK, AIPS_PACRP_TP0(value)))
+#define AIPS_BWR_PACRP_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_WP0 field. */
+#define AIPS_RD_PACRP_WP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_WP0_MASK) >> AIPS_PACRP_WP0_SHIFT)
+#define AIPS_BRD_PACRP_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRP_WP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_WP0_MASK, AIPS_PACRP_WP0(value)))
+#define AIPS_BWR_PACRP_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRP, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRP_SP0 field. */
+#define AIPS_RD_PACRP_SP0(base) ((AIPS_PACRP_REG(base) & AIPS_PACRP_SP0_MASK) >> AIPS_PACRP_SP0_SHIFT)
+#define AIPS_BRD_PACRP_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRP_SP0(base, value) (AIPS_RMW_PACRP(base, AIPS_PACRP_SP0_MASK, AIPS_PACRP_SP0(value)))
+#define AIPS_BWR_PACRP_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRP_REG(base), AIPS_PACRP_SP0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AIPS_PACRU - Peripheral Access Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AIPS_PACRU - Peripheral Access Control Register (RW)
+ *
+ * Reset value: 0x44000000U
+ *
+ * PACRU defines the access levels for the two global spaces.
+ */
+/*!
+ * @name Constants and macros for entire AIPS_PACRU register
+ */
+/*@{*/
+#define AIPS_RD_PACRU(base)      (AIPS_PACRU_REG(base))
+#define AIPS_WR_PACRU(base, value) (AIPS_PACRU_REG(base) = (value))
+#define AIPS_RMW_PACRU(base, mask, value) (AIPS_WR_PACRU(base, (AIPS_RD_PACRU(base) & ~(mask)) | (value)))
+#define AIPS_SET_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) |  (value)))
+#define AIPS_CLR_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) & ~(value)))
+#define AIPS_TOG_PACRU(base, value) (AIPS_WR_PACRU(base, AIPS_RD_PACRU(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AIPS_PACRU bitfields
+ */
+
+/*!
+ * @name Register AIPS_PACRU, field TP1[24] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_TP1 field. */
+#define AIPS_RD_PACRU_TP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_TP1_MASK) >> AIPS_PACRU_TP1_SHIFT)
+#define AIPS_BRD_PACRU_TP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP1_SHIFT))
+
+/*! @brief Set the TP1 field to a new value. */
+#define AIPS_WR_PACRU_TP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_TP1_MASK, AIPS_PACRU_TP1(value)))
+#define AIPS_BWR_PACRU_TP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field WP1[25] (RW)
+ *
+ * Determines whether the peripheral allows write accesss. When this bit is set
+ * and a write access is attempted, access terminates with an error response and
+ * no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_WP1 field. */
+#define AIPS_RD_PACRU_WP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_WP1_MASK) >> AIPS_PACRU_WP1_SHIFT)
+#define AIPS_BRD_PACRU_WP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP1_SHIFT))
+
+/*! @brief Set the WP1 field to a new value. */
+#define AIPS_WR_PACRU_WP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_WP1_MASK, AIPS_PACRU_WP1(value)))
+#define AIPS_BWR_PACRU_WP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field SP1[26] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * accesses. When this field is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control field for the master
+ * must be set. If not, access terminates with an error response and no peripheral
+ * access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_SP1 field. */
+#define AIPS_RD_PACRU_SP1(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_SP1_MASK) >> AIPS_PACRU_SP1_SHIFT)
+#define AIPS_BRD_PACRU_SP1(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP1_SHIFT))
+
+/*! @brief Set the SP1 field to a new value. */
+#define AIPS_WR_PACRU_SP1(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_SP1_MASK, AIPS_PACRU_SP1(value)))
+#define AIPS_BWR_PACRU_SP1(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field TP0[28] (RW)
+ *
+ * Determines whether the peripheral allows accesses from an untrusted master.
+ * When this field is set and an access is attempted by an untrusted master, the
+ * access terminates with an error response and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - Accesses from an untrusted master are allowed.
+ * - 0b1 - Accesses from an untrusted master are not allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_TP0 field. */
+#define AIPS_RD_PACRU_TP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_TP0_MASK) >> AIPS_PACRU_TP0_SHIFT)
+#define AIPS_BRD_PACRU_TP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP0_SHIFT))
+
+/*! @brief Set the TP0 field to a new value. */
+#define AIPS_WR_PACRU_TP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_TP0_MASK, AIPS_PACRU_TP0(value)))
+#define AIPS_BWR_PACRU_TP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_TP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field WP0[29] (RW)
+ *
+ * Determines whether the peripheral allows write accesses. When this field is
+ * set and a write access is attempted, access terminates with an error response
+ * and no peripheral access initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral allows write accesses.
+ * - 0b1 - This peripheral is write protected.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_WP0 field. */
+#define AIPS_RD_PACRU_WP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_WP0_MASK) >> AIPS_PACRU_WP0_SHIFT)
+#define AIPS_BRD_PACRU_WP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP0_SHIFT))
+
+/*! @brief Set the WP0 field to a new value. */
+#define AIPS_WR_PACRU_WP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_WP0_MASK, AIPS_PACRU_WP0(value)))
+#define AIPS_BWR_PACRU_WP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_WP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AIPS_PACRU, field SP0[30] (RW)
+ *
+ * Determines whether the peripheral requires supervisor privilege level for
+ * access. When this bit is set, the master privilege level must indicate the
+ * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be
+ * set. If not, access terminates with an error response and no peripheral access
+ * initiates.
+ *
+ * Values:
+ * - 0b0 - This peripheral does not require supervisor privilege level for
+ *     accesses.
+ * - 0b1 - This peripheral requires supervisor privilege level for accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the AIPS_PACRU_SP0 field. */
+#define AIPS_RD_PACRU_SP0(base) ((AIPS_PACRU_REG(base) & AIPS_PACRU_SP0_MASK) >> AIPS_PACRU_SP0_SHIFT)
+#define AIPS_BRD_PACRU_SP0(base) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP0_SHIFT))
+
+/*! @brief Set the SP0 field to a new value. */
+#define AIPS_WR_PACRU_SP0(base, value) (AIPS_RMW_PACRU(base, AIPS_PACRU_SP0_MASK, AIPS_PACRU_SP0(value)))
+#define AIPS_BWR_PACRU_SP0(base, value) (BITBAND_ACCESS32(&AIPS_PACRU_REG(base), AIPS_PACRU_SP0_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 AXBS
+ *
+ * Crossbar switch
+ *
+ * Registers defined in this header file:
+ * - AXBS_PRS - Priority Registers Slave
+ * - AXBS_CRS - Control Register
+ * - AXBS_MGPCR0 - Master General Purpose Control Register
+ * - AXBS_MGPCR1 - Master General Purpose Control Register
+ * - AXBS_MGPCR2 - Master General Purpose Control Register
+ * - AXBS_MGPCR3 - Master General Purpose Control Register
+ * - AXBS_MGPCR4 - Master General Purpose Control Register
+ * - AXBS_MGPCR5 - Master General Purpose Control Register
+ */
+
+#define AXBS_INSTANCE_COUNT (1U) /*!< Number of instances of the AXBS module. */
+#define AXBS_IDX (0U) /*!< Instance number for AXBS. */
+
+/*******************************************************************************
+ * AXBS_PRS - Priority Registers Slave
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_PRS - Priority Registers Slave (RW)
+ *
+ * Reset value: 0x00543210U
+ *
+ * The priority registers (PRSn) set the priority of each master port on a per
+ * slave port basis and reside in each slave port. The priority register can be
+ * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
+ * register can only be read; attempts to write to it have no effect on PRSn and
+ * result in a bus-error response to the master initiating the write. Two available
+ * masters must not be programmed with the same priority level. Attempts to
+ * program two or more masters with the same priority level result in a bus-error
+ * response and the PRSn is not updated. Valid values for the Mn priority fields
+ * depend on which masters are available on the chip. This information can be found in
+ * the chip-specific information for the crossbar. If the chip contains less
+ * than five masters, values 0 to 3 are valid. Writing other values will result in
+ * an error. If the chip contains five or more masters, valid values are 0 to n-1,
+ * where n is the number of masters attached to the AXBS module. Other values
+ * will result in an error.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_PRS register
+ */
+/*@{*/
+#define AXBS_RD_PRS(base, index) (AXBS_PRS_REG(base, index))
+#define AXBS_WR_PRS(base, index, value) (AXBS_PRS_REG(base, index) = (value))
+#define AXBS_RMW_PRS(base, index, mask, value) (AXBS_WR_PRS(base, index, (AXBS_RD_PRS(base, index) & ~(mask)) | (value)))
+#define AXBS_SET_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) |  (value)))
+#define AXBS_CLR_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) & ~(value)))
+#define AXBS_TOG_PRS(base, index, value) (AXBS_WR_PRS(base, index, AXBS_RD_PRS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_PRS bitfields
+ */
+
+/*!
+ * @name Register AXBS_PRS, field M0[2:0] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M0 field. */
+#define AXBS_RD_PRS_M0(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M0_MASK) >> AXBS_PRS_M0_SHIFT)
+#define AXBS_BRD_PRS_M0(base, index) (AXBS_RD_PRS_M0(base, index))
+
+/*! @brief Set the M0 field to a new value. */
+#define AXBS_WR_PRS_M0(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M0_MASK, AXBS_PRS_M0(value)))
+#define AXBS_BWR_PRS_M0(base, index, value) (AXBS_WR_PRS_M0(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M1[6:4] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M1 field. */
+#define AXBS_RD_PRS_M1(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M1_MASK) >> AXBS_PRS_M1_SHIFT)
+#define AXBS_BRD_PRS_M1(base, index) (AXBS_RD_PRS_M1(base, index))
+
+/*! @brief Set the M1 field to a new value. */
+#define AXBS_WR_PRS_M1(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M1_MASK, AXBS_PRS_M1(value)))
+#define AXBS_BWR_PRS_M1(base, index, value) (AXBS_WR_PRS_M1(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M2[10:8] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M2 field. */
+#define AXBS_RD_PRS_M2(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M2_MASK) >> AXBS_PRS_M2_SHIFT)
+#define AXBS_BRD_PRS_M2(base, index) (AXBS_RD_PRS_M2(base, index))
+
+/*! @brief Set the M2 field to a new value. */
+#define AXBS_WR_PRS_M2(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M2_MASK, AXBS_PRS_M2(value)))
+#define AXBS_BWR_PRS_M2(base, index, value) (AXBS_WR_PRS_M2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M3[14:12] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M3 field. */
+#define AXBS_RD_PRS_M3(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M3_MASK) >> AXBS_PRS_M3_SHIFT)
+#define AXBS_BRD_PRS_M3(base, index) (AXBS_RD_PRS_M3(base, index))
+
+/*! @brief Set the M3 field to a new value. */
+#define AXBS_WR_PRS_M3(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M3_MASK, AXBS_PRS_M3(value)))
+#define AXBS_BWR_PRS_M3(base, index, value) (AXBS_WR_PRS_M3(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M4[18:16] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M4 field. */
+#define AXBS_RD_PRS_M4(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M4_MASK) >> AXBS_PRS_M4_SHIFT)
+#define AXBS_BRD_PRS_M4(base, index) (AXBS_RD_PRS_M4(base, index))
+
+/*! @brief Set the M4 field to a new value. */
+#define AXBS_WR_PRS_M4(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M4_MASK, AXBS_PRS_M4(value)))
+#define AXBS_BWR_PRS_M4(base, index, value) (AXBS_WR_PRS_M4(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_PRS, field M5[22:20] (RW)
+ *
+ * Values:
+ * - 0b000 - This master has level 1, or highest, priority when accessing the
+ *     slave port.
+ * - 0b001 - This master has level 2 priority when accessing the slave port.
+ * - 0b010 - This master has level 3 priority when accessing the slave port.
+ * - 0b011 - This master has level 4 priority when accessing the slave port.
+ * - 0b100 - This master has level 5 priority when accessing the slave port.
+ * - 0b101 - This master has level 6 priority when accessing the slave port.
+ * - 0b110 - This master has level 7 priority when accessing the slave port.
+ * - 0b111 - This master has level 8, or lowest, priority when accessing the
+ *     slave port.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_PRS_M5 field. */
+#define AXBS_RD_PRS_M5(base, index) ((AXBS_PRS_REG(base, index) & AXBS_PRS_M5_MASK) >> AXBS_PRS_M5_SHIFT)
+#define AXBS_BRD_PRS_M5(base, index) (AXBS_RD_PRS_M5(base, index))
+
+/*! @brief Set the M5 field to a new value. */
+#define AXBS_WR_PRS_M5(base, index, value) (AXBS_RMW_PRS(base, index, AXBS_PRS_M5_MASK, AXBS_PRS_M5(value)))
+#define AXBS_BWR_PRS_M5(base, index, value) (AXBS_WR_PRS_M5(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_CRS - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_CRS - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers control several features of each slave port and must be
+ * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
+ * attempts to write to it have no effect and result in an error response.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_CRS register
+ */
+/*@{*/
+#define AXBS_RD_CRS(base, index) (AXBS_CRS_REG(base, index))
+#define AXBS_WR_CRS(base, index, value) (AXBS_CRS_REG(base, index) = (value))
+#define AXBS_RMW_CRS(base, index, mask, value) (AXBS_WR_CRS(base, index, (AXBS_RD_CRS(base, index) & ~(mask)) | (value)))
+#define AXBS_SET_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) |  (value)))
+#define AXBS_CLR_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) & ~(value)))
+#define AXBS_TOG_CRS(base, index, value) (AXBS_WR_CRS(base, index, AXBS_RD_CRS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_CRS bitfields
+ */
+
+/*!
+ * @name Register AXBS_CRS, field PARK[2:0] (RW)
+ *
+ * Determines which master port the current slave port parks on when no masters
+ * are actively making requests and the PCTL bits are cleared. Select only master
+ * ports that are present on the chip. Otherwise, undefined behavior might occur.
+ *
+ * Values:
+ * - 0b000 - Park on master port M0
+ * - 0b001 - Park on master port M1
+ * - 0b010 - Park on master port M2
+ * - 0b011 - Park on master port M3
+ * - 0b100 - Park on master port M4
+ * - 0b101 - Park on master port M5
+ * - 0b110 - Park on master port M6
+ * - 0b111 - Park on master port M7
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_PARK field. */
+#define AXBS_RD_CRS_PARK(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_PARK_MASK) >> AXBS_CRS_PARK_SHIFT)
+#define AXBS_BRD_CRS_PARK(base, index) (AXBS_RD_CRS_PARK(base, index))
+
+/*! @brief Set the PARK field to a new value. */
+#define AXBS_WR_CRS_PARK(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_PARK_MASK, AXBS_CRS_PARK(value)))
+#define AXBS_BWR_CRS_PARK(base, index, value) (AXBS_WR_CRS_PARK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field PCTL[5:4] (RW)
+ *
+ * Determines the slave port's parking control. The low-power park feature
+ * results in an overall power savings if the slave port is not saturated. However,
+ * this forces an extra latency clock when any master tries to access the slave
+ * port while not in use because it is not parked on any master.
+ *
+ * Values:
+ * - 0b00 - When no master makes a request, the arbiter parks the slave port on
+ *     the master port defined by the PARK field
+ * - 0b01 - When no master makes a request, the arbiter parks the slave port on
+ *     the last master to be in control of the slave port
+ * - 0b10 - When no master makes a request, the slave port is not parked on a
+ *     master and the arbiter drives all outputs to a constant safe state
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_PCTL field. */
+#define AXBS_RD_CRS_PCTL(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_PCTL_MASK) >> AXBS_CRS_PCTL_SHIFT)
+#define AXBS_BRD_CRS_PCTL(base, index) (AXBS_RD_CRS_PCTL(base, index))
+
+/*! @brief Set the PCTL field to a new value. */
+#define AXBS_WR_CRS_PCTL(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_PCTL_MASK, AXBS_CRS_PCTL(value)))
+#define AXBS_BWR_CRS_PCTL(base, index, value) (AXBS_WR_CRS_PCTL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field ARB[9:8] (RW)
+ *
+ * Selects the arbitration policy for the slave port.
+ *
+ * Values:
+ * - 0b00 - Fixed priority
+ * - 0b01 - Round-robin, or rotating, priority
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_ARB field. */
+#define AXBS_RD_CRS_ARB(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_ARB_MASK) >> AXBS_CRS_ARB_SHIFT)
+#define AXBS_BRD_CRS_ARB(base, index) (AXBS_RD_CRS_ARB(base, index))
+
+/*! @brief Set the ARB field to a new value. */
+#define AXBS_WR_CRS_ARB(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_ARB_MASK, AXBS_CRS_ARB(value)))
+#define AXBS_BWR_CRS_ARB(base, index, value) (AXBS_WR_CRS_ARB(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field HLP[30] (RW)
+ *
+ * Sets the initial arbitration priority for low power mode requests . Setting
+ * this bit will not affect the request for low power mode from attaining highest
+ * priority once it has control of the slave ports.
+ *
+ * Values:
+ * - 0b0 - The low power mode request has the highest priority for arbitration
+ *     on this slave port
+ * - 0b1 - The low power mode request has the lowest initial priority for
+ *     arbitration on this slave port
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_HLP field. */
+#define AXBS_RD_CRS_HLP(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_HLP_MASK) >> AXBS_CRS_HLP_SHIFT)
+#define AXBS_BRD_CRS_HLP(base, index) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_HLP_SHIFT))
+
+/*! @brief Set the HLP field to a new value. */
+#define AXBS_WR_CRS_HLP(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_HLP_MASK, AXBS_CRS_HLP(value)))
+#define AXBS_BWR_CRS_HLP(base, index, value) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_HLP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register AXBS_CRS, field RO[31] (RW)
+ *
+ * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
+ * only a hardware reset clears it.
+ *
+ * Values:
+ * - 0b0 - The slave port's registers are writeable
+ * - 0b1 - The slave port's registers are read-only and cannot be written.
+ *     Attempted writes have no effect on the registers and result in a bus error
+ *     response.
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_CRS_RO field. */
+#define AXBS_RD_CRS_RO(base, index) ((AXBS_CRS_REG(base, index) & AXBS_CRS_RO_MASK) >> AXBS_CRS_RO_SHIFT)
+#define AXBS_BRD_CRS_RO(base, index) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_RO_SHIFT))
+
+/*! @brief Set the RO field to a new value. */
+#define AXBS_WR_CRS_RO(base, index, value) (AXBS_RMW_CRS(base, index, AXBS_CRS_RO_MASK, AXBS_CRS_RO(value)))
+#define AXBS_BWR_CRS_RO(base, index, value) (BITBAND_ACCESS32(&AXBS_CRS_REG(base, index), AXBS_CRS_RO_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR0 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR0 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR0 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR0(base)     (AXBS_MGPCR0_REG(base))
+#define AXBS_WR_MGPCR0(base, value) (AXBS_MGPCR0_REG(base) = (value))
+#define AXBS_RMW_MGPCR0(base, mask, value) (AXBS_WR_MGPCR0(base, (AXBS_RD_MGPCR0(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) |  (value)))
+#define AXBS_CLR_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) & ~(value)))
+#define AXBS_TOG_MGPCR0(base, value) (AXBS_WR_MGPCR0(base, AXBS_RD_MGPCR0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR0 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR0_AULB field. */
+#define AXBS_RD_MGPCR0_AULB(base) ((AXBS_MGPCR0_REG(base) & AXBS_MGPCR0_AULB_MASK) >> AXBS_MGPCR0_AULB_SHIFT)
+#define AXBS_BRD_MGPCR0_AULB(base) (AXBS_RD_MGPCR0_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR0_AULB(base, value) (AXBS_RMW_MGPCR0(base, AXBS_MGPCR0_AULB_MASK, AXBS_MGPCR0_AULB(value)))
+#define AXBS_BWR_MGPCR0_AULB(base, value) (AXBS_WR_MGPCR0_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR1 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR1 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR1 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR1(base)     (AXBS_MGPCR1_REG(base))
+#define AXBS_WR_MGPCR1(base, value) (AXBS_MGPCR1_REG(base) = (value))
+#define AXBS_RMW_MGPCR1(base, mask, value) (AXBS_WR_MGPCR1(base, (AXBS_RD_MGPCR1(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) |  (value)))
+#define AXBS_CLR_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) & ~(value)))
+#define AXBS_TOG_MGPCR1(base, value) (AXBS_WR_MGPCR1(base, AXBS_RD_MGPCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR1 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR1_AULB field. */
+#define AXBS_RD_MGPCR1_AULB(base) ((AXBS_MGPCR1_REG(base) & AXBS_MGPCR1_AULB_MASK) >> AXBS_MGPCR1_AULB_SHIFT)
+#define AXBS_BRD_MGPCR1_AULB(base) (AXBS_RD_MGPCR1_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR1_AULB(base, value) (AXBS_RMW_MGPCR1(base, AXBS_MGPCR1_AULB_MASK, AXBS_MGPCR1_AULB(value)))
+#define AXBS_BWR_MGPCR1_AULB(base, value) (AXBS_WR_MGPCR1_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR2 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR2 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR2 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR2(base)     (AXBS_MGPCR2_REG(base))
+#define AXBS_WR_MGPCR2(base, value) (AXBS_MGPCR2_REG(base) = (value))
+#define AXBS_RMW_MGPCR2(base, mask, value) (AXBS_WR_MGPCR2(base, (AXBS_RD_MGPCR2(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) |  (value)))
+#define AXBS_CLR_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) & ~(value)))
+#define AXBS_TOG_MGPCR2(base, value) (AXBS_WR_MGPCR2(base, AXBS_RD_MGPCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR2 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR2_AULB field. */
+#define AXBS_RD_MGPCR2_AULB(base) ((AXBS_MGPCR2_REG(base) & AXBS_MGPCR2_AULB_MASK) >> AXBS_MGPCR2_AULB_SHIFT)
+#define AXBS_BRD_MGPCR2_AULB(base) (AXBS_RD_MGPCR2_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR2_AULB(base, value) (AXBS_RMW_MGPCR2(base, AXBS_MGPCR2_AULB_MASK, AXBS_MGPCR2_AULB(value)))
+#define AXBS_BWR_MGPCR2_AULB(base, value) (AXBS_WR_MGPCR2_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR3 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR3 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR3 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR3(base)     (AXBS_MGPCR3_REG(base))
+#define AXBS_WR_MGPCR3(base, value) (AXBS_MGPCR3_REG(base) = (value))
+#define AXBS_RMW_MGPCR3(base, mask, value) (AXBS_WR_MGPCR3(base, (AXBS_RD_MGPCR3(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) |  (value)))
+#define AXBS_CLR_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) & ~(value)))
+#define AXBS_TOG_MGPCR3(base, value) (AXBS_WR_MGPCR3(base, AXBS_RD_MGPCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR3 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR3_AULB field. */
+#define AXBS_RD_MGPCR3_AULB(base) ((AXBS_MGPCR3_REG(base) & AXBS_MGPCR3_AULB_MASK) >> AXBS_MGPCR3_AULB_SHIFT)
+#define AXBS_BRD_MGPCR3_AULB(base) (AXBS_RD_MGPCR3_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR3_AULB(base, value) (AXBS_RMW_MGPCR3(base, AXBS_MGPCR3_AULB_MASK, AXBS_MGPCR3_AULB(value)))
+#define AXBS_BWR_MGPCR3_AULB(base, value) (AXBS_WR_MGPCR3_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR4 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR4 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR4 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR4(base)     (AXBS_MGPCR4_REG(base))
+#define AXBS_WR_MGPCR4(base, value) (AXBS_MGPCR4_REG(base) = (value))
+#define AXBS_RMW_MGPCR4(base, mask, value) (AXBS_WR_MGPCR4(base, (AXBS_RD_MGPCR4(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) |  (value)))
+#define AXBS_CLR_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) & ~(value)))
+#define AXBS_TOG_MGPCR4(base, value) (AXBS_WR_MGPCR4(base, AXBS_RD_MGPCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR4 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR4_AULB field. */
+#define AXBS_RD_MGPCR4_AULB(base) ((AXBS_MGPCR4_REG(base) & AXBS_MGPCR4_AULB_MASK) >> AXBS_MGPCR4_AULB_SHIFT)
+#define AXBS_BRD_MGPCR4_AULB(base) (AXBS_RD_MGPCR4_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR4_AULB(base, value) (AXBS_RMW_MGPCR4(base, AXBS_MGPCR4_AULB_MASK, AXBS_MGPCR4_AULB(value)))
+#define AXBS_BWR_MGPCR4_AULB(base, value) (AXBS_WR_MGPCR4_AULB(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * AXBS_MGPCR5 - Master General Purpose Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief AXBS_MGPCR5 - Master General Purpose Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MGPCR controls only whether the master's undefined length burst accesses
+ * are allowed to complete uninterrupted or whether they can be broken by
+ * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
+ * mode with 32-bit accesses.
+ */
+/*!
+ * @name Constants and macros for entire AXBS_MGPCR5 register
+ */
+/*@{*/
+#define AXBS_RD_MGPCR5(base)     (AXBS_MGPCR5_REG(base))
+#define AXBS_WR_MGPCR5(base, value) (AXBS_MGPCR5_REG(base) = (value))
+#define AXBS_RMW_MGPCR5(base, mask, value) (AXBS_WR_MGPCR5(base, (AXBS_RD_MGPCR5(base) & ~(mask)) | (value)))
+#define AXBS_SET_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) |  (value)))
+#define AXBS_CLR_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) & ~(value)))
+#define AXBS_TOG_MGPCR5(base, value) (AXBS_WR_MGPCR5(base, AXBS_RD_MGPCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual AXBS_MGPCR5 bitfields
+ */
+
+/*!
+ * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
+ *
+ * Determines whether, and when, the crossbar switch arbitrates away the slave
+ * port the master owns when the master is performing undefined length burst
+ * accesses.
+ *
+ * Values:
+ * - 0b000 - No arbitration is allowed during an undefined length burst
+ * - 0b001 - Arbitration is allowed at any time during an undefined length burst
+ * - 0b010 - Arbitration is allowed after four beats of an undefined length burst
+ * - 0b011 - Arbitration is allowed after eight beats of an undefined length
+ *     burst
+ * - 0b100 - Arbitration is allowed after 16 beats of an undefined length burst
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the AXBS_MGPCR5_AULB field. */
+#define AXBS_RD_MGPCR5_AULB(base) ((AXBS_MGPCR5_REG(base) & AXBS_MGPCR5_AULB_MASK) >> AXBS_MGPCR5_AULB_SHIFT)
+#define AXBS_BRD_MGPCR5_AULB(base) (AXBS_RD_MGPCR5_AULB(base))
+
+/*! @brief Set the AULB field to a new value. */
+#define AXBS_WR_MGPCR5_AULB(base, value) (AXBS_RMW_MGPCR5(base, AXBS_MGPCR5_AULB_MASK, AXBS_MGPCR5_AULB(value)))
+#define AXBS_BWR_MGPCR5_AULB(base, value) (AXBS_WR_MGPCR5_AULB(base, value))
+/*@}*/
+
+/*
+ * MK64F12 CAN
+ *
+ * Flex Controller Area Network module
+ *
+ * Registers defined in this header file:
+ * - CAN_MCR - Module Configuration Register
+ * - CAN_CTRL1 - Control 1 register
+ * - CAN_TIMER - Free Running Timer
+ * - CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ * - CAN_RX14MASK - Rx 14 Mask register
+ * - CAN_RX15MASK - Rx 15 Mask register
+ * - CAN_ECR - Error Counter
+ * - CAN_ESR1 - Error and Status 1 register
+ * - CAN_IMASK1 - Interrupt Masks 1 register
+ * - CAN_IFLAG1 - Interrupt Flags 1 register
+ * - CAN_CTRL2 - Control 2 register
+ * - CAN_ESR2 - Error and Status 2 register
+ * - CAN_CRCR - CRC Register
+ * - CAN_RXFGMASK - Rx FIFO Global Mask register
+ * - CAN_RXFIR - Rx FIFO Information Register
+ * - CAN_CS - Message Buffer 0 CS Register
+ * - CAN_ID - Message Buffer 0 ID Register
+ * - CAN_WORD0 - Message Buffer 0 WORD0 Register
+ * - CAN_WORD1 - Message Buffer 0 WORD1 Register
+ * - CAN_RXIMR - Rx Individual Mask Registers
+ */
+
+#define CAN_INSTANCE_COUNT (1U) /*!< Number of instances of the CAN module. */
+#define CAN0_IDX (0U) /*!< Instance number for CAN0. */
+
+/*******************************************************************************
+ * CAN_MCR - Module Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0xD890000FU
+ *
+ * This register defines global system configurations, such as the module
+ * operation modes and the maximum message buffer configuration.
+ */
+/*!
+ * @name Constants and macros for entire CAN_MCR register
+ */
+/*@{*/
+#define CAN_RD_MCR(base)         (CAN_MCR_REG(base))
+#define CAN_WR_MCR(base, value)  (CAN_MCR_REG(base) = (value))
+#define CAN_RMW_MCR(base, mask, value) (CAN_WR_MCR(base, (CAN_RD_MCR(base) & ~(mask)) | (value)))
+#define CAN_SET_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) |  (value)))
+#define CAN_CLR_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) & ~(value)))
+#define CAN_TOG_MCR(base, value) (CAN_WR_MCR(base, CAN_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_MCR bitfields
+ */
+
+/*!
+ * @name Register CAN_MCR, field MAXMB[6:0] (RW)
+ *
+ * This 7-bit field defines the number of the last Message Buffers that will
+ * take part in the matching and arbitration processes. The reset value (0x0F) is
+ * equivalent to a 16 MB configuration. This field can be written only in Freeze
+ * mode because it is blocked by hardware in other modes. Number of the last MB =
+ * MAXMB MAXMB must be programmed with a value smaller than the parameter
+ * NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
+ * (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
+ * defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
+ * of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
+ * Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
+ * Matching Timing").
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_MAXMB field. */
+#define CAN_RD_MCR_MAXMB(base) ((CAN_MCR_REG(base) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT)
+#define CAN_BRD_MCR_MAXMB(base) (CAN_RD_MCR_MAXMB(base))
+
+/*! @brief Set the MAXMB field to a new value. */
+#define CAN_WR_MCR_MAXMB(base, value) (CAN_RMW_MCR(base, CAN_MCR_MAXMB_MASK, CAN_MCR_MAXMB(value)))
+#define CAN_BWR_MCR_MAXMB(base, value) (CAN_WR_MCR_MAXMB(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field IDAM[9:8] (RW)
+ *
+ * This 2-bit field identifies the format of the Rx FIFO ID Filter Table
+ * elements. Note that all elements of the table are configured at the same time by this
+ * field (they are all the same format). See Section "Rx FIFO Structure". This
+ * field can be written only in Freeze mode because it is blocked by hardware in
+ * other modes.
+ *
+ * Values:
+ * - 0b00 - Format A: One full ID (standard and extended) per ID Filter Table
+ *     element.
+ * - 0b01 - Format B: Two full standard IDs or two partial 14-bit (standard and
+ *     extended) IDs per ID Filter Table element.
+ * - 0b10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table
+ *     element.
+ * - 0b11 - Format D: All frames rejected.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_IDAM field. */
+#define CAN_RD_MCR_IDAM(base) ((CAN_MCR_REG(base) & CAN_MCR_IDAM_MASK) >> CAN_MCR_IDAM_SHIFT)
+#define CAN_BRD_MCR_IDAM(base) (CAN_RD_MCR_IDAM(base))
+
+/*! @brief Set the IDAM field to a new value. */
+#define CAN_WR_MCR_IDAM(base, value) (CAN_RMW_MCR(base, CAN_MCR_IDAM_MASK, CAN_MCR_IDAM(value)))
+#define CAN_BWR_MCR_IDAM(base, value) (CAN_WR_MCR_IDAM(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field AEN[12] (RW)
+ *
+ * This bit is supplied for backwards compatibility with legacy applications.
+ * When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
+ * safe procedure for aborting a pending transmission, so that no frame is sent in
+ * the CAN bus without notification. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
+ * only the abort mechanism (see Section "Transmission Abort Mechanism") must be
+ * used for updating Mailboxes configured for transmission. Writing the Abort code
+ * into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Abort disabled.
+ * - 0b1 - Abort enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_AEN field. */
+#define CAN_RD_MCR_AEN(base) ((CAN_MCR_REG(base) & CAN_MCR_AEN_MASK) >> CAN_MCR_AEN_SHIFT)
+#define CAN_BRD_MCR_AEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_AEN_SHIFT))
+
+/*! @brief Set the AEN field to a new value. */
+#define CAN_WR_MCR_AEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_AEN_MASK, CAN_MCR_AEN(value)))
+#define CAN_BWR_MCR_AEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_AEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field LPRIOEN[13] (RW)
+ *
+ * This bit is provided for backwards compatibility with legacy applications. It
+ * controls whether the local priority feature is enabled or not. It is used to
+ * expand the ID used during the arbitration process. With this expanded ID
+ * concept, the arbitration process is done based on the full 32-bit word, but the
+ * actual transmitted ID still has 11-bit for standard frames and 29-bit for
+ * extended frames. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Local Priority disabled.
+ * - 0b1 - Local Priority enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_LPRIOEN field. */
+#define CAN_RD_MCR_LPRIOEN(base) ((CAN_MCR_REG(base) & CAN_MCR_LPRIOEN_MASK) >> CAN_MCR_LPRIOEN_SHIFT)
+#define CAN_BRD_MCR_LPRIOEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPRIOEN_SHIFT))
+
+/*! @brief Set the LPRIOEN field to a new value. */
+#define CAN_WR_MCR_LPRIOEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_LPRIOEN_MASK, CAN_MCR_LPRIOEN(value)))
+#define CAN_BWR_MCR_LPRIOEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPRIOEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field IRMQ[16] (RW)
+ *
+ * This bit indicates whether Rx matching process will be based either on
+ * individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
+ * RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Individual Rx masking and queue feature are disabled. For backward
+ *     compatibility with legacy applications, the reading of C/S word locks the MB
+ *     even if it is EMPTY.
+ * - 0b1 - Individual Rx masking and queue feature are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_IRMQ field. */
+#define CAN_RD_MCR_IRMQ(base) ((CAN_MCR_REG(base) & CAN_MCR_IRMQ_MASK) >> CAN_MCR_IRMQ_SHIFT)
+#define CAN_BRD_MCR_IRMQ(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_IRMQ_SHIFT))
+
+/*! @brief Set the IRMQ field to a new value. */
+#define CAN_WR_MCR_IRMQ(base, value) (CAN_RMW_MCR(base, CAN_MCR_IRMQ_MASK, CAN_MCR_IRMQ(value)))
+#define CAN_BWR_MCR_IRMQ(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_IRMQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SRXDIS[17] (RW)
+ *
+ * This bit defines whether FlexCAN is allowed to receive frames transmitted by
+ * itself. If this bit is asserted, frames transmitted by the module will not be
+ * stored in any MB, regardless if the MB is programmed with an ID that matches
+ * the transmitted frame, and no interrupt flag or interrupt signal will be
+ * generated due to the frame reception. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Self reception enabled.
+ * - 0b1 - Self reception disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SRXDIS field. */
+#define CAN_RD_MCR_SRXDIS(base) ((CAN_MCR_REG(base) & CAN_MCR_SRXDIS_MASK) >> CAN_MCR_SRXDIS_SHIFT)
+#define CAN_BRD_MCR_SRXDIS(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SRXDIS_SHIFT))
+
+/*! @brief Set the SRXDIS field to a new value. */
+#define CAN_WR_MCR_SRXDIS(base, value) (CAN_RMW_MCR(base, CAN_MCR_SRXDIS_MASK, CAN_MCR_SRXDIS(value)))
+#define CAN_BWR_MCR_SRXDIS(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SRXDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WAKSRC[19] (RW)
+ *
+ * This bit defines whether the integrated low-pass filter is applied to protect
+ * the Rx CAN input from spurious wake up. This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ * - 0b1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
+ *     edges on the CAN bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WAKSRC field. */
+#define CAN_RD_MCR_WAKSRC(base) ((CAN_MCR_REG(base) & CAN_MCR_WAKSRC_MASK) >> CAN_MCR_WAKSRC_SHIFT)
+#define CAN_BRD_MCR_WAKSRC(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKSRC_SHIFT))
+
+/*! @brief Set the WAKSRC field to a new value. */
+#define CAN_WR_MCR_WAKSRC(base, value) (CAN_RMW_MCR(base, CAN_MCR_WAKSRC_MASK, CAN_MCR_WAKSRC(value)))
+#define CAN_BWR_MCR_WAKSRC(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field LPMACK[20] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in a low-power mode (Disable
+ * mode , Stop mode ). A low-power mode cannot be entered until all current
+ * transmission or reception processes have finished, so the CPU can poll the LPMACK bit
+ * to know when FlexCAN has actually entered low power mode. LPMACK will be
+ * asserted within 180 CAN bits from the low-power mode request by the CPU, and
+ * negated within 2 CAN bits after the low-power mode request removal (see Section
+ * "Protocol Timing").
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not in a low-power mode.
+ * - 0b1 - FlexCAN is in a low-power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_LPMACK field. */
+#define CAN_RD_MCR_LPMACK(base) ((CAN_MCR_REG(base) & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT)
+#define CAN_BRD_MCR_LPMACK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_LPMACK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WRNEN[21] (RW)
+ *
+ * When asserted, this bit enables the generation of the TWRNINT and RWRNINT
+ * flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
+ * RWRNINT flags will always be zero, independent of the values of the error
+ * counters, and no warning interrupt will ever be generated. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
+ *     error counters.
+ * - 0b1 - TWRNINT and RWRNINT bits are set when the respective error counter
+ *     transitions from less than 96 to greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WRNEN field. */
+#define CAN_RD_MCR_WRNEN(base) ((CAN_MCR_REG(base) & CAN_MCR_WRNEN_MASK) >> CAN_MCR_WRNEN_SHIFT)
+#define CAN_BRD_MCR_WRNEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WRNEN_SHIFT))
+
+/*! @brief Set the WRNEN field to a new value. */
+#define CAN_WR_MCR_WRNEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_WRNEN_MASK, CAN_MCR_WRNEN(value)))
+#define CAN_BWR_MCR_WRNEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WRNEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SLFWAK[22] (RW)
+ *
+ * This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
+ * other than Disable mode. When this feature is enabled, the FlexCAN module
+ * monitors the bus for wake up event, that is, a recessive-to-dominant transition.
+ * If a wake up event is detected during Stop mode, then FlexCAN generates, if
+ * enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
+ * globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
+ * low-power mode other than Disable mode, this bit cannot be written as it is
+ * blocked by hardware.
+ *
+ * Values:
+ * - 0b0 - FlexCAN Self Wake Up feature is disabled.
+ * - 0b1 - FlexCAN Self Wake Up feature is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SLFWAK field. */
+#define CAN_RD_MCR_SLFWAK(base) ((CAN_MCR_REG(base) & CAN_MCR_SLFWAK_MASK) >> CAN_MCR_SLFWAK_SHIFT)
+#define CAN_BRD_MCR_SLFWAK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SLFWAK_SHIFT))
+
+/*! @brief Set the SLFWAK field to a new value. */
+#define CAN_WR_MCR_SLFWAK(base, value) (CAN_RMW_MCR(base, CAN_MCR_SLFWAK_MASK, CAN_MCR_SLFWAK(value)))
+#define CAN_BWR_MCR_SLFWAK(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SLFWAK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SUPV[23] (RW)
+ *
+ * This bit configures the FlexCAN to be either in Supervisor or User mode. The
+ * registers affected by this bit are marked as S/U in the Access Type column of
+ * the module memory map. Reset value of this bit is 1, so the affected registers
+ * start with Supervisor access allowance only . This bit can be written only in
+ * Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
+ *     Unrestricted accesses .
+ * - 0b1 - FlexCAN is in Supervisor mode. Affected registers allow only
+ *     Supervisor access. Unrestricted access behaves as though the access was done to an
+ *     unimplemented register location .
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SUPV field. */
+#define CAN_RD_MCR_SUPV(base) ((CAN_MCR_REG(base) & CAN_MCR_SUPV_MASK) >> CAN_MCR_SUPV_SHIFT)
+#define CAN_BRD_MCR_SUPV(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SUPV_SHIFT))
+
+/*! @brief Set the SUPV field to a new value. */
+#define CAN_WR_MCR_SUPV(base, value) (CAN_RMW_MCR(base, CAN_MCR_SUPV_MASK, CAN_MCR_SUPV(value)))
+#define CAN_BWR_MCR_SUPV(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SUPV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field FRZACK[24] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
+ * is stopped. The Freeze mode request cannot be granted until current
+ * transmission or reception processes have finished. Therefore the software can poll the
+ * FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
+ * Mode request is negated, then this bit is negated after the FlexCAN prescaler is
+ * running again. If Freeze mode is requested while FlexCAN is in a low power
+ * mode, then the FRZACK bit will be set only when the low-power mode is exited.
+ * See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
+ * freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
+ * mode request removal (see Section "Protocol Timing").
+ *
+ * Values:
+ * - 0b0 - FlexCAN not in Freeze mode, prescaler running.
+ * - 0b1 - FlexCAN in Freeze mode, prescaler stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_FRZACK field. */
+#define CAN_RD_MCR_FRZACK(base) ((CAN_MCR_REG(base) & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)
+#define CAN_BRD_MCR_FRZACK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZACK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field SOFTRST[25] (RW)
+ *
+ * When this bit is asserted, FlexCAN resets its internal state machines and
+ * some of the memory mapped registers. The following registers are reset: MCR
+ * (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
+ * CRCR. Configuration registers that control the interface to the CAN bus are
+ * not affected by soft reset. The following registers are unaffected: CTRL1,
+ * CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
+ * Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
+ * writes to the MCR Register, but it is also asserted when global soft reset is
+ * requested at MCU level . Because soft reset is synchronous and has to follow a
+ * request/acknowledge procedure across clock domains, it may take some time to
+ * fully propagate its effect. The SOFTRST bit remains asserted while reset is
+ * pending, and is automatically negated when reset completes. Therefore, software can
+ * poll this bit to know when the soft reset has completed. Soft reset cannot be
+ * applied while clocks are shut down in a low power mode. The module should be
+ * first removed from low power mode, and then soft reset can be applied.
+ *
+ * Values:
+ * - 0b0 - No reset request.
+ * - 0b1 - Resets the registers affected by soft reset.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_SOFTRST field. */
+#define CAN_RD_MCR_SOFTRST(base) ((CAN_MCR_REG(base) & CAN_MCR_SOFTRST_MASK) >> CAN_MCR_SOFTRST_SHIFT)
+#define CAN_BRD_MCR_SOFTRST(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SOFTRST_SHIFT))
+
+/*! @brief Set the SOFTRST field to a new value. */
+#define CAN_WR_MCR_SOFTRST(base, value) (CAN_RMW_MCR(base, CAN_MCR_SOFTRST_MASK, CAN_MCR_SOFTRST(value)))
+#define CAN_BWR_MCR_SOFTRST(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_SOFTRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field WAKMSK[26] (RW)
+ *
+ * This bit enables the Wake Up Interrupt generation under Self Wake Up
+ * mechanism.
+ *
+ * Values:
+ * - 0b0 - Wake Up Interrupt is disabled.
+ * - 0b1 - Wake Up Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_WAKMSK field. */
+#define CAN_RD_MCR_WAKMSK(base) ((CAN_MCR_REG(base) & CAN_MCR_WAKMSK_MASK) >> CAN_MCR_WAKMSK_SHIFT)
+#define CAN_BRD_MCR_WAKMSK(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKMSK_SHIFT))
+
+/*! @brief Set the WAKMSK field to a new value. */
+#define CAN_WR_MCR_WAKMSK(base, value) (CAN_RMW_MCR(base, CAN_MCR_WAKMSK_MASK, CAN_MCR_WAKMSK(value)))
+#define CAN_BWR_MCR_WAKMSK(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_WAKMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field NOTRDY[27] (RO)
+ *
+ * This read-only bit indicates that FlexCAN is either in Disable mode , Stop
+ * mode or Freeze mode. It is negated once FlexCAN has exited these modes.
+ *
+ * Values:
+ * - 0b0 - FlexCAN module is either in Normal mode, Listen-Only mode or
+ *     Loop-Back mode.
+ * - 0b1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_NOTRDY field. */
+#define CAN_RD_MCR_NOTRDY(base) ((CAN_MCR_REG(base) & CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT)
+#define CAN_BRD_MCR_NOTRDY(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_NOTRDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field HALT[28] (RW)
+ *
+ * Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
+ * should clear it after initializing the Message Buffers and Control Register. No
+ * reception or transmission is performed by FlexCAN before this bit is cleared.
+ * Freeze mode cannot be entered while FlexCAN is in a low power mode.
+ *
+ * Values:
+ * - 0b0 - No Freeze mode request.
+ * - 0b1 - Enters Freeze mode if the FRZ bit is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_HALT field. */
+#define CAN_RD_MCR_HALT(base) ((CAN_MCR_REG(base) & CAN_MCR_HALT_MASK) >> CAN_MCR_HALT_SHIFT)
+#define CAN_BRD_MCR_HALT(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define CAN_WR_MCR_HALT(base, value) (CAN_RMW_MCR(base, CAN_MCR_HALT_MASK, CAN_MCR_HALT(value)))
+#define CAN_BWR_MCR_HALT(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field RFEN[29] (RW)
+ *
+ * This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
+ * set, MBs 0 to 5 cannot be used for normal reception and transmission because
+ * the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
+ * as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
+ * as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
+ * minimum number of peripheral clocks per CAN bit as described in the table
+ * "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
+ * "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Rx FIFO not enabled.
+ * - 0b1 - Rx FIFO enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_RFEN field. */
+#define CAN_RD_MCR_RFEN(base) ((CAN_MCR_REG(base) & CAN_MCR_RFEN_MASK) >> CAN_MCR_RFEN_SHIFT)
+#define CAN_BRD_MCR_RFEN(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_RFEN_SHIFT))
+
+/*! @brief Set the RFEN field to a new value. */
+#define CAN_WR_MCR_RFEN(base, value) (CAN_RMW_MCR(base, CAN_MCR_RFEN_MASK, CAN_MCR_RFEN(value)))
+#define CAN_BWR_MCR_RFEN(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_RFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field FRZ[30] (RW)
+ *
+ * The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
+ * Register is set or when Debug mode is requested at MCU level . When FRZ is
+ * asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
+ * FlexCAN to exit from Freeze mode.
+ *
+ * Values:
+ * - 0b0 - Not enabled to enter Freeze mode.
+ * - 0b1 - Enabled to enter Freeze mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_FRZ field. */
+#define CAN_RD_MCR_FRZ(base) ((CAN_MCR_REG(base) & CAN_MCR_FRZ_MASK) >> CAN_MCR_FRZ_SHIFT)
+#define CAN_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define CAN_WR_MCR_FRZ(base, value) (CAN_RMW_MCR(base, CAN_MCR_FRZ_MASK, CAN_MCR_FRZ(value)))
+#define CAN_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_MCR, field MDIS[31] (RW)
+ *
+ * This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
+ * disables the clocks to the CAN Protocol Engine and Controller Host Interface
+ * sub-modules. This is the only bit within this register not affected by soft
+ * reset.
+ *
+ * Values:
+ * - 0b0 - Enable the FlexCAN module.
+ * - 0b1 - Disable the FlexCAN module.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_MCR_MDIS field. */
+#define CAN_RD_MCR_MDIS(base) ((CAN_MCR_REG(base) & CAN_MCR_MDIS_MASK) >> CAN_MCR_MDIS_SHIFT)
+#define CAN_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define CAN_WR_MCR_MDIS(base, value) (CAN_RMW_MCR(base, CAN_MCR_MDIS_MASK, CAN_MCR_MDIS(value)))
+#define CAN_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&CAN_MCR_REG(base), CAN_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CTRL1 - Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CTRL1 - Control 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is defined for specific FlexCAN control features related to the
+ * CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
+ * Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
+ * (Bus-Off, Error, Warning). It also determines the Division Factor for the
+ * clock prescaler.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CTRL1 register
+ */
+/*@{*/
+#define CAN_RD_CTRL1(base)       (CAN_CTRL1_REG(base))
+#define CAN_WR_CTRL1(base, value) (CAN_CTRL1_REG(base) = (value))
+#define CAN_RMW_CTRL1(base, mask, value) (CAN_WR_CTRL1(base, (CAN_RD_CTRL1(base) & ~(mask)) | (value)))
+#define CAN_SET_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) |  (value)))
+#define CAN_CLR_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) & ~(value)))
+#define CAN_TOG_CTRL1(base, value) (CAN_WR_CTRL1(base, CAN_RD_CTRL1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CTRL1 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
+ *
+ * This 3-bit field defines the length of the Propagation Segment in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Propagation
+ * Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PROPSEG field. */
+#define CAN_RD_CTRL1_PROPSEG(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PROPSEG_MASK) >> CAN_CTRL1_PROPSEG_SHIFT)
+#define CAN_BRD_CTRL1_PROPSEG(base) (CAN_RD_CTRL1_PROPSEG(base))
+
+/*! @brief Set the PROPSEG field to a new value. */
+#define CAN_WR_CTRL1_PROPSEG(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PROPSEG_MASK, CAN_CTRL1_PROPSEG(value)))
+#define CAN_BWR_CTRL1_PROPSEG(base, value) (CAN_WR_CTRL1_PROPSEG(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LOM[3] (RW)
+ *
+ * This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
+ * transmission is disabled, all error counters are frozen and the module operates
+ * in a CAN Error Passive mode. Only messages acknowledged by another CAN station
+ * will be received. If FlexCAN detects a message that has not been acknowledged,
+ * it will flag a BIT0 error without changing the REC, as if it was trying to
+ * acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
+ * state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
+ * entered. There can be some delay between the Listen-Only mode request and
+ * acknowledge. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Listen-Only mode is deactivated.
+ * - 0b1 - FlexCAN module operates in Listen-Only mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LOM field. */
+#define CAN_RD_CTRL1_LOM(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LOM_MASK) >> CAN_CTRL1_LOM_SHIFT)
+#define CAN_BRD_CTRL1_LOM(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LOM_SHIFT))
+
+/*! @brief Set the LOM field to a new value. */
+#define CAN_WR_CTRL1_LOM(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LOM_MASK, CAN_CTRL1_LOM(value)))
+#define CAN_BWR_CTRL1_LOM(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LBUF[4] (RW)
+ *
+ * This bit defines the ordering mechanism for Message Buffer transmission. When
+ * asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0b0 - Buffer with highest priority is transmitted first.
+ * - 0b1 - Lowest number buffer is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LBUF field. */
+#define CAN_RD_CTRL1_LBUF(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LBUF_MASK) >> CAN_CTRL1_LBUF_SHIFT)
+#define CAN_BRD_CTRL1_LBUF(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LBUF_SHIFT))
+
+/*! @brief Set the LBUF field to a new value. */
+#define CAN_WR_CTRL1_LBUF(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LBUF_MASK, CAN_CTRL1_LBUF(value)))
+#define CAN_BWR_CTRL1_LBUF(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field TSYN[5] (RW)
+ *
+ * This bit enables a mechanism that resets the free-running timer each time a
+ * message is received in Message Buffer 0. This feature provides means to
+ * synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
+ * network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
+ * available Mailbox, according to CTRL2[RFFN] setting, is used for timer
+ * synchronization instead of MB0. This bit can be written only in Freeze mode because it is
+ * blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Timer Sync feature disabled
+ * - 0b1 - Timer Sync feature enabled
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_TSYN field. */
+#define CAN_RD_CTRL1_TSYN(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_TSYN_MASK) >> CAN_CTRL1_TSYN_SHIFT)
+#define CAN_BRD_CTRL1_TSYN(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TSYN_SHIFT))
+
+/*! @brief Set the TSYN field to a new value. */
+#define CAN_WR_CTRL1_TSYN(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_TSYN_MASK, CAN_CTRL1_TSYN(value)))
+#define CAN_BWR_CTRL1_TSYN(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TSYN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFREC[6] (RW)
+ *
+ * This bit defines how FlexCAN recovers from Bus Off state. If this bit is
+ * negated, automatic recovering from Bus Off state occurs according to the CAN
+ * Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
+ * disabled and the module remains in Bus Off state until the bit is negated by the
+ * user. If the negation occurs before 128 sequences of 11 recessive bits are
+ * detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
+ * never been asserted. If the negation occurs after 128 sequences of 11
+ * recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
+ * 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
+ * be re-asserted again during Bus Off, but it will be effective only the next
+ * time the module enters Bus Off. If BOFFREC was negated when the module entered
+ * Bus Off, asserting it during Bus Off will not be effective for the current Bus
+ * Off recovery.
+ *
+ * Values:
+ * - 0b0 - Automatic recovering from Bus Off state enabled, according to CAN
+ *     Spec 2.0 part B.
+ * - 0b1 - Automatic recovering from Bus Off state disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_BOFFREC field. */
+#define CAN_RD_CTRL1_BOFFREC(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_BOFFREC_MASK) >> CAN_CTRL1_BOFFREC_SHIFT)
+#define CAN_BRD_CTRL1_BOFFREC(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFREC_SHIFT))
+
+/*! @brief Set the BOFFREC field to a new value. */
+#define CAN_WR_CTRL1_BOFFREC(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_BOFFREC_MASK, CAN_CTRL1_BOFFREC(value)))
+#define CAN_BWR_CTRL1_BOFFREC(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFREC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field SMP[7] (RW)
+ *
+ * This bit defines the sampling mode of CAN bits at the Rx input. This bit can
+ * be written only in Freeze mode because it is blocked by hardware in other
+ * modes.
+ *
+ * Values:
+ * - 0b0 - Just one sample is used to determine the bit value.
+ * - 0b1 - Three samples are used to determine the value of the received bit:
+ *     the regular one (sample point) and 2 preceding samples; a majority rule is
+ *     used.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_SMP field. */
+#define CAN_RD_CTRL1_SMP(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_SMP_MASK) >> CAN_CTRL1_SMP_SHIFT)
+#define CAN_BRD_CTRL1_SMP(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_SMP_SHIFT))
+
+/*! @brief Set the SMP field to a new value. */
+#define CAN_WR_CTRL1_SMP(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_SMP_MASK, CAN_CTRL1_SMP(value)))
+#define CAN_BWR_CTRL1_SMP(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_SMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
+ *
+ * This bit provides a mask for the Rx Warning Interrupt associated with the
+ * RWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Rx Warning Interrupt disabled.
+ * - 0b1 - Rx Warning Interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_RWRNMSK field. */
+#define CAN_RD_CTRL1_RWRNMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_RWRNMSK_MASK) >> CAN_CTRL1_RWRNMSK_SHIFT)
+#define CAN_BRD_CTRL1_RWRNMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_RWRNMSK_SHIFT))
+
+/*! @brief Set the RWRNMSK field to a new value. */
+#define CAN_WR_CTRL1_RWRNMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_RWRNMSK_MASK, CAN_CTRL1_RWRNMSK(value)))
+#define CAN_BWR_CTRL1_RWRNMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_RWRNMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
+ *
+ * This bit provides a mask for the Tx Warning Interrupt associated with the
+ * TWRNINT flag in the Error and Status Register. This bit is read as zero when
+ * MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
+ * asserted.
+ *
+ * Values:
+ * - 0b0 - Tx Warning Interrupt disabled.
+ * - 0b1 - Tx Warning Interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_TWRNMSK field. */
+#define CAN_RD_CTRL1_TWRNMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_TWRNMSK_MASK) >> CAN_CTRL1_TWRNMSK_SHIFT)
+#define CAN_BRD_CTRL1_TWRNMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TWRNMSK_SHIFT))
+
+/*! @brief Set the TWRNMSK field to a new value. */
+#define CAN_WR_CTRL1_TWRNMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_TWRNMSK_MASK, CAN_CTRL1_TWRNMSK(value)))
+#define CAN_BWR_CTRL1_TWRNMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_TWRNMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field LPB[12] (RW)
+ *
+ * This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
+ * FlexCAN performs an internal loop back that can be used for self test operation.
+ * The bit stream output of the transmitter is fed back internally to the receiver
+ * input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
+ * recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
+ * and treats its own transmitted message as a message received from a remote
+ * node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
+ * frame acknowledge field, generating an internal acknowledge bit to ensure proper
+ * reception of its own message. Both transmit and receive interrupts are
+ * generated. This bit can be written only in Freeze mode because it is blocked by
+ * hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
+ * this will impede the self reception of a transmitted message.
+ *
+ * Values:
+ * - 0b0 - Loop Back disabled.
+ * - 0b1 - Loop Back enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_LPB field. */
+#define CAN_RD_CTRL1_LPB(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_LPB_MASK) >> CAN_CTRL1_LPB_SHIFT)
+#define CAN_BRD_CTRL1_LPB(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LPB_SHIFT))
+
+/*! @brief Set the LPB field to a new value. */
+#define CAN_WR_CTRL1_LPB(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_LPB_MASK, CAN_CTRL1_LPB(value)))
+#define CAN_BWR_CTRL1_LPB(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_LPB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field CLKSRC[13] (RW)
+ *
+ * This bit selects the clock source to the CAN Protocol Engine (PE) to be
+ * either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
+ * The selected clock is the one fed to the prescaler to generate the Serial Clock
+ * (Sclock). In order to guarantee reliable operation, this bit can be written
+ * only in Disable mode because it is blocked by hardware in other modes. See
+ * Section "Protocol Timing".
+ *
+ * Values:
+ * - 0b0 - The CAN engine clock source is the oscillator clock. Under this
+ *     condition, the oscillator clock frequency must be lower than the bus clock.
+ * - 0b1 - The CAN engine clock source is the peripheral clock.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_CLKSRC field. */
+#define CAN_RD_CTRL1_CLKSRC(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_CLKSRC_MASK) >> CAN_CTRL1_CLKSRC_SHIFT)
+#define CAN_BRD_CTRL1_CLKSRC(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_CLKSRC_SHIFT))
+
+/*! @brief Set the CLKSRC field to a new value. */
+#define CAN_WR_CTRL1_CLKSRC(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_CLKSRC_MASK, CAN_CTRL1_CLKSRC(value)))
+#define CAN_BWR_CTRL1_CLKSRC(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_CLKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field ERRMSK[14] (RW)
+ *
+ * This bit provides a mask for the Error Interrupt.
+ *
+ * Values:
+ * - 0b0 - Error interrupt disabled.
+ * - 0b1 - Error interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_ERRMSK field. */
+#define CAN_RD_CTRL1_ERRMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_ERRMSK_MASK) >> CAN_CTRL1_ERRMSK_SHIFT)
+#define CAN_BRD_CTRL1_ERRMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_ERRMSK_SHIFT))
+
+/*! @brief Set the ERRMSK field to a new value. */
+#define CAN_WR_CTRL1_ERRMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_ERRMSK_MASK, CAN_CTRL1_ERRMSK(value)))
+#define CAN_BWR_CTRL1_ERRMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_ERRMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
+ *
+ * This bit provides a mask for the Bus Off Interrupt.
+ *
+ * Values:
+ * - 0b0 - Bus Off interrupt disabled.
+ * - 0b1 - Bus Off interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_BOFFMSK field. */
+#define CAN_RD_CTRL1_BOFFMSK(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_BOFFMSK_MASK) >> CAN_CTRL1_BOFFMSK_SHIFT)
+#define CAN_BRD_CTRL1_BOFFMSK(base) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFMSK_SHIFT))
+
+/*! @brief Set the BOFFMSK field to a new value. */
+#define CAN_WR_CTRL1_BOFFMSK(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_BOFFMSK_MASK, CAN_CTRL1_BOFFMSK(value)))
+#define CAN_BWR_CTRL1_BOFFMSK(base, value) (BITBAND_ACCESS32(&CAN_CTRL1_REG(base), CAN_CTRL1_BOFFMSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
+ * time. The valid programmable values are 1-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 2 = (PSEG2 + 1) * Time-Quanta.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PSEG2 field. */
+#define CAN_RD_CTRL1_PSEG2(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PSEG2_MASK) >> CAN_CTRL1_PSEG2_SHIFT)
+#define CAN_BRD_CTRL1_PSEG2(base) (CAN_RD_CTRL1_PSEG2(base))
+
+/*! @brief Set the PSEG2 field to a new value. */
+#define CAN_WR_CTRL1_PSEG2(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PSEG2_MASK, CAN_CTRL1_PSEG2(value)))
+#define CAN_BWR_CTRL1_PSEG2(base, value) (CAN_WR_CTRL1_PSEG2(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
+ *
+ * This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
+ * time. The valid programmable values are 0-7. This field can be written only in
+ * Freeze mode because it is blocked by hardware in other modes. Phase Buffer
+ * Segment 1 = (PSEG1 + 1) * Time-Quanta.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PSEG1 field. */
+#define CAN_RD_CTRL1_PSEG1(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PSEG1_MASK) >> CAN_CTRL1_PSEG1_SHIFT)
+#define CAN_BRD_CTRL1_PSEG1(base) (CAN_RD_CTRL1_PSEG1(base))
+
+/*! @brief Set the PSEG1 field to a new value. */
+#define CAN_WR_CTRL1_PSEG1(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PSEG1_MASK, CAN_CTRL1_PSEG1(value)))
+#define CAN_BWR_CTRL1_PSEG1(base, value) (CAN_WR_CTRL1_PSEG1(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field RJW[23:22] (RW)
+ *
+ * This 2-bit field defines the maximum number of time quanta that a bit time
+ * can be changed by one re-synchronization. One time quantum is equal to the
+ * Sclock period. The valid programmable values are 0-3. This field can be written
+ * only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
+ * Width = RJW + 1.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_RJW field. */
+#define CAN_RD_CTRL1_RJW(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_RJW_MASK) >> CAN_CTRL1_RJW_SHIFT)
+#define CAN_BRD_CTRL1_RJW(base) (CAN_RD_CTRL1_RJW(base))
+
+/*! @brief Set the RJW field to a new value. */
+#define CAN_WR_CTRL1_RJW(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_RJW_MASK, CAN_CTRL1_RJW(value)))
+#define CAN_BWR_CTRL1_RJW(base, value) (CAN_WR_CTRL1_RJW(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
+ *
+ * This 8-bit field defines the ratio between the PE clock frequency and the
+ * Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
+ * the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
+ * clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
+ * Sclock frequency equal to the PE clock frequency divided by 256. See Section
+ * "Protocol Timing". This field can be written only in Freeze mode because it is
+ * blocked by hardware in other modes. Sclock frequency = PE clock frequency /
+ * (PRESDIV + 1)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL1_PRESDIV field. */
+#define CAN_RD_CTRL1_PRESDIV(base) ((CAN_CTRL1_REG(base) & CAN_CTRL1_PRESDIV_MASK) >> CAN_CTRL1_PRESDIV_SHIFT)
+#define CAN_BRD_CTRL1_PRESDIV(base) (CAN_RD_CTRL1_PRESDIV(base))
+
+/*! @brief Set the PRESDIV field to a new value. */
+#define CAN_WR_CTRL1_PRESDIV(base, value) (CAN_RMW_CTRL1(base, CAN_CTRL1_PRESDIV_MASK, CAN_CTRL1_PRESDIV(value)))
+#define CAN_BWR_CTRL1_PRESDIV(base, value) (CAN_WR_CTRL1_PRESDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_TIMER - Free Running Timer
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_TIMER - Free Running Timer (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register represents a 16-bit free running counter that can be read and
+ * written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
+ * 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
+ * defines the baud rate on the CAN bus. During a message transmission/reception,
+ * it increments by one for each bit that is received or transmitted. When there
+ * is no message on the bus, it counts using the previously programmed baud
+ * rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
+ * timer value is captured when the second bit of the identifier field of any frame
+ * is on the CAN bus. This captured value is written into the Time Stamp entry
+ * in a message buffer after a successful reception or transmission of a message.
+ * If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
+ * received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
+ * can write to this register anytime. However, if the write occurs at the same
+ * time that the Timer is being reset by a reception in the first Mailbox, then
+ * the write value is discarded. Reading this register affects the Mailbox
+ * Unlocking procedure; see Section "Mailbox Lock Mechanism".
+ */
+/*!
+ * @name Constants and macros for entire CAN_TIMER register
+ */
+/*@{*/
+#define CAN_RD_TIMER(base)       (CAN_TIMER_REG(base))
+#define CAN_WR_TIMER(base, value) (CAN_TIMER_REG(base) = (value))
+#define CAN_RMW_TIMER(base, mask, value) (CAN_WR_TIMER(base, (CAN_RD_TIMER(base) & ~(mask)) | (value)))
+#define CAN_SET_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) |  (value)))
+#define CAN_CLR_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) & ~(value)))
+#define CAN_TOG_TIMER(base, value) (CAN_WR_TIMER(base, CAN_RD_TIMER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_TIMER bitfields
+ */
+
+/*!
+ * @name Register CAN_TIMER, field TIMER[15:0] (RW)
+ *
+ * Contains the free-running counter value.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_TIMER_TIMER field. */
+#define CAN_RD_TIMER_TIMER(base) ((CAN_TIMER_REG(base) & CAN_TIMER_TIMER_MASK) >> CAN_TIMER_TIMER_SHIFT)
+#define CAN_BRD_TIMER_TIMER(base) (CAN_RD_TIMER_TIMER(base))
+
+/*! @brief Set the TIMER field to a new value. */
+#define CAN_WR_TIMER_TIMER(base, value) (CAN_RMW_TIMER(base, CAN_TIMER_TIMER_MASK, CAN_TIMER_TIMER(value)))
+#define CAN_BWR_TIMER_TIMER(base, value) (CAN_WR_TIMER_TIMER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXMGMASK - Rx Mailboxes Global Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RXMGMASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
+ * the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
+ * mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
+ * mask registers. This register can only be written in Freeze mode as it is
+ * blocked by hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXMGMASK register
+ */
+/*@{*/
+#define CAN_RD_RXMGMASK(base)    (CAN_RXMGMASK_REG(base))
+#define CAN_WR_RXMGMASK(base, value) (CAN_RXMGMASK_REG(base) = (value))
+#define CAN_RMW_RXMGMASK(base, mask, value) (CAN_WR_RXMGMASK(base, (CAN_RD_RXMGMASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) |  (value)))
+#define CAN_CLR_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) & ~(value)))
+#define CAN_TOG_RXMGMASK(base, value) (CAN_WR_RXMGMASK(base, CAN_RD_RXMGMASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RX14MASK - Rx 14 Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RX14MASK - Rx 14 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX14MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
+ * is used to mask the filter fields of Message Buffer 14. This register can only
+ * be programmed while the module is in Freeze mode as it is blocked by hardware
+ * in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RX14MASK register
+ */
+/*@{*/
+#define CAN_RD_RX14MASK(base)    (CAN_RX14MASK_REG(base))
+#define CAN_WR_RX14MASK(base, value) (CAN_RX14MASK_REG(base) = (value))
+#define CAN_RMW_RX14MASK(base, mask, value) (CAN_WR_RX14MASK(base, (CAN_RD_RX14MASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) |  (value)))
+#define CAN_CLR_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) & ~(value)))
+#define CAN_TOG_RX14MASK(base, value) (CAN_WR_RX14MASK(base, CAN_RD_RX14MASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RX15MASK - Rx 15 Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RX15MASK - Rx 15 Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. RX15MASK is provided for legacy application
+ * support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
+ * is used to mask the filter fields of Message Buffer 15. This register can be
+ * programmed only while the module is in Freeze mode because it is blocked by
+ * hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RX15MASK register
+ */
+/*@{*/
+#define CAN_RD_RX15MASK(base)    (CAN_RX15MASK_REG(base))
+#define CAN_WR_RX15MASK(base, value) (CAN_RX15MASK_REG(base) = (value))
+#define CAN_RMW_RX15MASK(base, mask, value) (CAN_WR_RX15MASK(base, (CAN_RD_RX15MASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) |  (value)))
+#define CAN_CLR_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) & ~(value)))
+#define CAN_TOG_RX15MASK(base, value) (CAN_WR_RX15MASK(base, CAN_RD_RX15MASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ECR - Error Counter
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ECR - Error Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has two 8-bit fields reflecting the value of two FlexCAN error
+ * counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
+ * (RXERRCNT field). The rules for increasing and decreasing these counters are
+ * described in the CAN protocol and are completely implemented in the FlexCAN
+ * module. Both counters are read-only except in Freeze mode, where they can be
+ * written by the CPU. FlexCAN responds to any bus state as described in the protocol,
+ * for example, transmit Error Active or Error Passive flag, delay its
+ * transmission start time (Error Passive) and avoid any influence on the bus when in Bus
+ * Off state. The following are the basic rules for FlexCAN bus state transitions:
+ * If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
+ * 128, the FLTCONF field in the Error and Status Register is updated to reflect
+ * 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
+ * TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
+ * other already satisfies this condition, the FLTCONF field in the Error and
+ * Status Register is updated to reflect 'Error Active' state. If the value of
+ * TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
+ * Register is updated to reflect 'Bus Off' state, and an interrupt may be
+ * issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
+ * state, then TXERRCNT is cascaded together with another internal counter to count
+ * the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
+ * TXERRCNT is reset to zero and counts in a manner where the internal counter counts
+ * 11 such bits and then wraps around while incrementing the TXERRCNT. When
+ * TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
+ * Register is updated to be 'Error Active' and both error counters are reset to zero.
+ * At any instance of dominant bit following a stream of less than 11
+ * consecutive recessive bits, the internal counter resets itself to zero without affecting
+ * the TXERRCNT value. If during system start-up, only one node is operating,
+ * then its TXERRCNT increases in each message it is trying to transmit, as a
+ * result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
+ * Register). After the transition to 'Error Passive' state, the TXERRCNT does not
+ * increment anymore by acknowledge errors. Therefore the device never goes to
+ * the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
+ * is not incremented further, even if more errors are detected while being a
+ * receiver. At the next successful message reception, the counter is set to a value
+ * between 119 and 127 to resume to 'Error Active' state.
+ */
+/*!
+ * @name Constants and macros for entire CAN_ECR register
+ */
+/*@{*/
+#define CAN_RD_ECR(base)         (CAN_ECR_REG(base))
+#define CAN_WR_ECR(base, value)  (CAN_ECR_REG(base) = (value))
+#define CAN_RMW_ECR(base, mask, value) (CAN_WR_ECR(base, (CAN_RD_ECR(base) & ~(mask)) | (value)))
+#define CAN_SET_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) |  (value)))
+#define CAN_CLR_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) & ~(value)))
+#define CAN_TOG_ECR(base, value) (CAN_WR_ECR(base, CAN_RD_ECR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ECR bitfields
+ */
+
+/*!
+ * @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ECR_TXERRCNT field. */
+#define CAN_RD_ECR_TXERRCNT(base) ((CAN_ECR_REG(base) & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT)
+#define CAN_BRD_ECR_TXERRCNT(base) (CAN_RD_ECR_TXERRCNT(base))
+
+/*! @brief Set the TXERRCNT field to a new value. */
+#define CAN_WR_ECR_TXERRCNT(base, value) (CAN_RMW_ECR(base, CAN_ECR_TXERRCNT_MASK, CAN_ECR_TXERRCNT(value)))
+#define CAN_BWR_ECR_TXERRCNT(base, value) (CAN_WR_ECR_TXERRCNT(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ECR_RXERRCNT field. */
+#define CAN_RD_ECR_RXERRCNT(base) ((CAN_ECR_REG(base) & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT)
+#define CAN_BRD_ECR_RXERRCNT(base) (CAN_RD_ECR_RXERRCNT(base))
+
+/*! @brief Set the RXERRCNT field to a new value. */
+#define CAN_WR_ECR_RXERRCNT(base, value) (CAN_RMW_ECR(base, CAN_ECR_RXERRCNT_MASK, CAN_ECR_RXERRCNT(value)))
+#define CAN_BWR_ECR_RXERRCNT(base, value) (CAN_WR_ECR_RXERRCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ESR1 - Error and Status 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ESR1 - Error and Status 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various error conditions, some general status of the
+ * device and it is the source of interrupts to the CPU. The CPU read action
+ * clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
+ * that occurred since the last time the CPU read this register. Bits 9-3 are
+ * status bits. The following table shows the FlexCAN state variables and their
+ * meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
+ * FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
+ * Transmitting 1 0 0 1 Receiving
+ */
+/*!
+ * @name Constants and macros for entire CAN_ESR1 register
+ */
+/*@{*/
+#define CAN_RD_ESR1(base)        (CAN_ESR1_REG(base))
+#define CAN_WR_ESR1(base, value) (CAN_ESR1_REG(base) = (value))
+#define CAN_RMW_ESR1(base, mask, value) (CAN_WR_ESR1(base, (CAN_RD_ESR1(base) & ~(mask)) | (value)))
+#define CAN_SET_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) |  (value)))
+#define CAN_CLR_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) & ~(value)))
+#define CAN_TOG_ESR1(base, value) (CAN_WR_ESR1(base, CAN_RD_ESR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ESR1 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR1, field WAKINT[0] (W1C)
+ *
+ * This field applies when FlexCAN is in low-power mode under Self Wake Up
+ * mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
+ * bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
+ * This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
+ * is masked. The CPU must clear this flag before disabling the bit. Otherwise
+ * it will be set when the SLFWAK is set again. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - Indicates a recessive to dominant transition was received on the CAN
+ *     bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_WAKINT field. */
+#define CAN_RD_ESR1_WAKINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_WAKINT_MASK) >> CAN_ESR1_WAKINT_SHIFT)
+#define CAN_BRD_ESR1_WAKINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_WAKINT_SHIFT))
+
+/*! @brief Set the WAKINT field to a new value. */
+#define CAN_WR_ESR1_WAKINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_WAKINT(value)))
+#define CAN_BWR_ESR1_WAKINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_WAKINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field ERRINT[1] (W1C)
+ *
+ * This bit indicates that at least one of the Error Bits (bits 15-10) is set.
+ * If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
+ * to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - Indicates setting of any Error Bit in the Error and Status Register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_ERRINT field. */
+#define CAN_RD_ESR1_ERRINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_ERRINT_MASK) >> CAN_ESR1_ERRINT_SHIFT)
+#define CAN_BRD_ESR1_ERRINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ERRINT_SHIFT))
+
+/*! @brief Set the ERRINT field to a new value. */
+#define CAN_WR_ESR1_ERRINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_ERRINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_ERRINT(value)))
+#define CAN_BWR_ESR1_ERRINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ERRINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BOFFINT[2] (W1C)
+ *
+ * This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
+ * mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
+ * the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - FlexCAN module entered Bus Off state.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BOFFINT field. */
+#define CAN_RD_ESR1_BOFFINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BOFFINT_MASK) >> CAN_ESR1_BOFFINT_SHIFT)
+#define CAN_BRD_ESR1_BOFFINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BOFFINT_SHIFT))
+
+/*! @brief Set the BOFFINT field to a new value. */
+#define CAN_WR_ESR1_BOFFINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_BOFFINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_RWRNINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_BOFFINT(value)))
+#define CAN_BWR_ESR1_BOFFINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BOFFINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RX[3] (RO)
+ *
+ * This bit indicates if FlexCAN is receiving a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not receiving a message.
+ * - 0b1 - FlexCAN is receiving a message.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RX field. */
+#define CAN_RD_ESR1_RX(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RX_MASK) >> CAN_ESR1_RX_SHIFT)
+#define CAN_BRD_ESR1_RX(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
+ *
+ * This 2-bit field indicates the Confinement State of the FlexCAN module. If
+ * the LOM bit in the Control Register is asserted, after some delay that depends
+ * on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
+ * same delay affects the way how FLTCONF reflects an update to ECR register by
+ * the CPU. It may be necessary up to one CAN bit time to get them coherent
+ * again. Because the Control Register is not affected by soft reset, the FLTCONF
+ * field will not be affected by soft reset if the LOM bit is asserted.
+ *
+ * Values:
+ * - 0b00 - Error Active
+ * - 0b01 - Error Passive
+ * - 0b1x - Bus Off
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_FLTCONF field. */
+#define CAN_RD_ESR1_FLTCONF(base) ((CAN_ESR1_REG(base) & CAN_ESR1_FLTCONF_MASK) >> CAN_ESR1_FLTCONF_SHIFT)
+#define CAN_BRD_ESR1_FLTCONF(base) (CAN_RD_ESR1_FLTCONF(base))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TX[6] (RO)
+ *
+ * This bit indicates if FlexCAN is transmitting a message. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not transmitting a message.
+ * - 0b1 - FlexCAN is transmitting a message.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TX field. */
+#define CAN_RD_ESR1_TX(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TX_MASK) >> CAN_ESR1_TX_SHIFT)
+#define CAN_BRD_ESR1_TX(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field IDLE[7] (RO)
+ *
+ * This bit indicates when CAN bus is in IDLE state. See the table in the
+ * overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - CAN bus is now IDLE.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_IDLE field. */
+#define CAN_RD_ESR1_IDLE(base) ((CAN_ESR1_REG(base) & CAN_ESR1_IDLE_MASK) >> CAN_ESR1_IDLE_SHIFT)
+#define CAN_BRD_ESR1_IDLE(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RXWRN[8] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * reception. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - RXERRCNT is greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RXWRN field. */
+#define CAN_RD_ESR1_RXWRN(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RXWRN_MASK) >> CAN_ESR1_RXWRN_SHIFT)
+#define CAN_BRD_ESR1_RXWRN(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RXWRN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TXWRN[9] (RO)
+ *
+ * This bit indicates when repetitive errors are occurring during message
+ * transmission. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - TXERRCNT is greater than or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TXWRN field. */
+#define CAN_RD_ESR1_TXWRN(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TXWRN_MASK) >> CAN_ESR1_TXWRN_SHIFT)
+#define CAN_BRD_ESR1_TXWRN(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TXWRN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field STFERR[10] (RO)
+ *
+ * This bit indicates that a Stuffing Error has been etected.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A Stuffing Error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_STFERR field. */
+#define CAN_RD_ESR1_STFERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_STFERR_MASK) >> CAN_ESR1_STFERR_SHIFT)
+#define CAN_BRD_ESR1_STFERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_STFERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field FRMERR[11] (RO)
+ *
+ * This bit indicates that a Form Error has been detected by the receiver node,
+ * that is, a fixed-form bit field contains at least one illegal bit.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A Form Error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_FRMERR field. */
+#define CAN_RD_ESR1_FRMERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_FRMERR_MASK) >> CAN_ESR1_FRMERR_SHIFT)
+#define CAN_BRD_ESR1_FRMERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_FRMERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field CRCERR[12] (RO)
+ *
+ * This bit indicates that a CRC Error has been detected by the receiver node,
+ * that is, the calculated CRC is different from the received.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - A CRC error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_CRCERR field. */
+#define CAN_RD_ESR1_CRCERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_CRCERR_MASK) >> CAN_ESR1_CRCERR_SHIFT)
+#define CAN_BRD_ESR1_CRCERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_CRCERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field ACKERR[13] (RO)
+ *
+ * This bit indicates that an Acknowledge Error has been detected by the
+ * transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - An ACK error occurred since last read of this register.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_ACKERR field. */
+#define CAN_RD_ESR1_ACKERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_ACKERR_MASK) >> CAN_ESR1_ACKERR_SHIFT)
+#define CAN_BRD_ESR1_ACKERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_ACKERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BIT0ERR[14] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - At least one bit sent as dominant is received as recessive.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BIT0ERR field. */
+#define CAN_RD_ESR1_BIT0ERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BIT0ERR_MASK) >> CAN_ESR1_BIT0ERR_SHIFT)
+#define CAN_BRD_ESR1_BIT0ERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BIT0ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field BIT1ERR[15] (RO)
+ *
+ * This bit indicates when an inconsistency occurs between the transmitted and
+ * the received bit in a message. This bit is not set by a transmitter in case of
+ * arbitration field or ACK slot, or in case of a node sending a passive error
+ * flag that detects dominant bits.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - At least one bit sent as recessive is received as dominant.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_BIT1ERR field. */
+#define CAN_RD_ESR1_BIT1ERR(base) ((CAN_ESR1_REG(base) & CAN_ESR1_BIT1ERR_MASK) >> CAN_ESR1_BIT1ERR_SHIFT)
+#define CAN_BRD_ESR1_BIT1ERR(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_BIT1ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field RWRNINT[16] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
+ * flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
+ * the corresponding mask bit in the Control Register (RWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
+ * WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This bit is not updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - The Rx error counter transitioned from less than 96 to greater than
+ *     or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_RWRNINT field. */
+#define CAN_RD_ESR1_RWRNINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_RWRNINT_MASK) >> CAN_ESR1_RWRNINT_SHIFT)
+#define CAN_BRD_ESR1_RWRNINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RWRNINT_SHIFT))
+
+/*! @brief Set the RWRNINT field to a new value. */
+#define CAN_WR_ESR1_RWRNINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_RWRNINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_TWRNINT_MASK), CAN_ESR1_RWRNINT(value)))
+#define CAN_BWR_ESR1_RWRNINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_RWRNINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field TWRNINT[17] (W1C)
+ *
+ * If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
+ * flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
+ * the corresponding mask bit in the Control Register (TWRNMSK) is set, an
+ * interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
+ * is negated, this flag is masked. CPU must clear this flag before disabling
+ * the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
+ * effect. This flag is not generated during Bus Off state. This bit is not
+ * updated during Freeze mode.
+ *
+ * Values:
+ * - 0b0 - No such occurrence.
+ * - 0b1 - The Tx error counter transitioned from less than 96 to greater than
+ *     or equal to 96.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_TWRNINT field. */
+#define CAN_RD_ESR1_TWRNINT(base) ((CAN_ESR1_REG(base) & CAN_ESR1_TWRNINT_MASK) >> CAN_ESR1_TWRNINT_SHIFT)
+#define CAN_BRD_ESR1_TWRNINT(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TWRNINT_SHIFT))
+
+/*! @brief Set the TWRNINT field to a new value. */
+#define CAN_WR_ESR1_TWRNINT(base, value) (CAN_RMW_ESR1(base, (CAN_ESR1_TWRNINT_MASK | CAN_ESR1_WAKINT_MASK | CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK), CAN_ESR1_TWRNINT(value)))
+#define CAN_BWR_ESR1_TWRNINT(base, value) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_TWRNINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR1, field SYNCH[18] (RO)
+ *
+ * This read-only flag indicates whether the FlexCAN is synchronized to the CAN
+ * bus and able to participate in the communication process. It is set and
+ * cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
+ *
+ * Values:
+ * - 0b0 - FlexCAN is not synchronized to the CAN bus.
+ * - 0b1 - FlexCAN is synchronized to the CAN bus.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR1_SYNCH field. */
+#define CAN_RD_ESR1_SYNCH(base) ((CAN_ESR1_REG(base) & CAN_ESR1_SYNCH_MASK) >> CAN_ESR1_SYNCH_SHIFT)
+#define CAN_BRD_ESR1_SYNCH(base) (BITBAND_ACCESS32(&CAN_ESR1_REG(base), CAN_ESR1_SYNCH_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_IMASK1 - Interrupt Masks 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_IMASK1 - Interrupt Masks 1 register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register allows any number of a range of the 32 Message Buffer
+ * Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
+ * bit per buffer, enabling the CPU to determine which buffer generates an
+ * interrupt after a successful transmission or reception, that is, when the
+ * corresponding IFLAG1 bit is set.
+ */
+/*!
+ * @name Constants and macros for entire CAN_IMASK1 register
+ */
+/*@{*/
+#define CAN_RD_IMASK1(base)      (CAN_IMASK1_REG(base))
+#define CAN_WR_IMASK1(base, value) (CAN_IMASK1_REG(base) = (value))
+#define CAN_RMW_IMASK1(base, mask, value) (CAN_WR_IMASK1(base, (CAN_RD_IMASK1(base) & ~(mask)) | (value)))
+#define CAN_SET_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) |  (value)))
+#define CAN_CLR_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) & ~(value)))
+#define CAN_TOG_IMASK1(base, value) (CAN_WR_IMASK1(base, CAN_RD_IMASK1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_IFLAG1 - Interrupt Flags 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the flags for the 32 Message Buffer interrupts for MB31
+ * to MB0. It contains one interrupt flag bit per buffer. Each successful
+ * transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
+ * IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
+ * cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
+ * are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
+ * bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
+ * BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
+ * the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
+ * must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
+ * FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
+ * belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
+ * the FIFO flags must be cleared. The same care must be taken when an RFFN
+ * value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
+ * 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
+ * must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
+ * bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
+ * they will remain set and be inconsistent with the number of MBs available.
+ */
+/*!
+ * @name Constants and macros for entire CAN_IFLAG1 register
+ */
+/*@{*/
+#define CAN_RD_IFLAG1(base)      (CAN_IFLAG1_REG(base))
+#define CAN_WR_IFLAG1(base, value) (CAN_IFLAG1_REG(base) = (value))
+#define CAN_RMW_IFLAG1(base, mask, value) (CAN_WR_IFLAG1(base, (CAN_RD_IFLAG1(base) & ~(mask)) | (value)))
+#define CAN_SET_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) |  (value)))
+#define CAN_CLR_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) & ~(value)))
+#define CAN_TOG_IFLAG1(base, value) (CAN_WR_IFLAG1(base, CAN_RD_IFLAG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_IFLAG1 bitfields
+ */
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
+ * set.
+ *
+ * Values:
+ * - 0b0 - The corresponding buffer has no occurrence of successfully completed
+ *     transmission or reception when MCR[RFEN]=0.
+ * - 0b1 - The corresponding buffer has successfully completed transmission or
+ *     reception when MCR[RFEN]=0.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF0I field. */
+#define CAN_RD_IFLAG1_BUF0I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF0I_MASK) >> CAN_IFLAG1_BUF0I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF0I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF0I_SHIFT))
+
+/*! @brief Set the BUF0I field to a new value. */
+#define CAN_WR_IFLAG1_BUF0I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF0I(value)))
+#define CAN_BWR_IFLAG1_BUF0I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF0I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
+ * the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
+ * the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
+ * when MCR[RFEN] is set.
+ *
+ * Values:
+ * - 0b0000 - The corresponding buffer has no occurrence of successfully
+ *     completed transmission or reception when MCR[RFEN]=0.
+ * - 0b0001 - The corresponding buffer has successfully completed transmission
+ *     or reception when MCR[RFEN]=0.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field. */
+#define CAN_RD_IFLAG1_BUF4TO1I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF4TO1I_MASK) >> CAN_IFLAG1_BUF4TO1I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF4TO1I(base) (CAN_RD_IFLAG1_BUF4TO1I(base))
+
+/*! @brief Set the BUF4TO1I field to a new value. */
+#define CAN_WR_IFLAG1_BUF4TO1I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF4TO1I(value)))
+#define CAN_BWR_IFLAG1_BUF4TO1I(base, value) (CAN_WR_IFLAG1_BUF4TO1I(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
+ * Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
+ * least one frame is available to be read from the Rx FIFO.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB5 completing transmission/reception when
+ *     MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
+ * - 0b1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
+ *     available in the Rx FIFO when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF5I field. */
+#define CAN_RD_IFLAG1_BUF5I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF5I_MASK) >> CAN_IFLAG1_BUF5I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF5I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF5I_SHIFT))
+
+/*! @brief Set the BUF5I field to a new value. */
+#define CAN_WR_IFLAG1_BUF5I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF5I(value)))
+#define CAN_BWR_IFLAG1_BUF5I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF5I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
+ * when MCR[RFEN] is set. In this case, the flag indicates when the number of
+ * unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
+ * a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
+ * cleared while the number of unread messages is greater than 4, it does not
+ * assert again until the number of unread messages within the Rx FIFO is decreased
+ * to be equal to or less than 4.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB6 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
+ * - 0b1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     almost full when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF6I field. */
+#define CAN_RD_IFLAG1_BUF6I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF6I_MASK) >> CAN_IFLAG1_BUF6I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF6I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF6I_SHIFT))
+
+/*! @brief Set the BUF6I field to a new value. */
+#define CAN_WR_IFLAG1_BUF6I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF6I(value)))
+#define CAN_BWR_IFLAG1_BUF6I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF6I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
+ *
+ * When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
+ * the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
+ * MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
+ * when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
+ * because the Rx FIFO is full. Note that the flag will not be asserted when the
+ * Rx FIFO is full and the message was captured by a Mailbox.
+ *
+ * Values:
+ * - 0b0 - No occurrence of MB7 completing transmission/reception when
+ *     MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
+ * - 0b1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
+ *     overflow when MCR[RFEN]=1
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF7I field. */
+#define CAN_RD_IFLAG1_BUF7I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF7I_MASK) >> CAN_IFLAG1_BUF7I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF7I(base) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF7I_SHIFT))
+
+/*! @brief Set the BUF7I field to a new value. */
+#define CAN_WR_IFLAG1_BUF7I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF7I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF31TO8I_MASK), CAN_IFLAG1_BUF7I(value)))
+#define CAN_BWR_IFLAG1_BUF7I(base, value) (BITBAND_ACCESS32(&CAN_IFLAG1_REG(base), CAN_IFLAG1_BUF7I_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
+ *
+ * Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
+ * MB8.
+ *
+ * Values:
+ * - 0b000000000000000000000000 - The corresponding buffer has no occurrence of
+ *     successfully completed transmission or reception.
+ * - 0b000000000000000000000001 - The corresponding buffer has successfully
+ *     completed transmission or reception.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field. */
+#define CAN_RD_IFLAG1_BUF31TO8I(base) ((CAN_IFLAG1_REG(base) & CAN_IFLAG1_BUF31TO8I_MASK) >> CAN_IFLAG1_BUF31TO8I_SHIFT)
+#define CAN_BRD_IFLAG1_BUF31TO8I(base) (CAN_RD_IFLAG1_BUF31TO8I(base))
+
+/*! @brief Set the BUF31TO8I field to a new value. */
+#define CAN_WR_IFLAG1_BUF31TO8I(base, value) (CAN_RMW_IFLAG1(base, (CAN_IFLAG1_BUF31TO8I_MASK | CAN_IFLAG1_BUF0I_MASK | CAN_IFLAG1_BUF4TO1I_MASK | CAN_IFLAG1_BUF5I_MASK | CAN_IFLAG1_BUF6I_MASK | CAN_IFLAG1_BUF7I_MASK), CAN_IFLAG1_BUF31TO8I(value)))
+#define CAN_BWR_IFLAG1_BUF31TO8I(base, value) (CAN_WR_IFLAG1_BUF31TO8I(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CTRL2 - Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CTRL2 - Control 2 register (RW)
+ *
+ * Reset value: 0x00B00000U
+ *
+ * This register contains control bits for CAN errors, FIFO features, and mode
+ * selection.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CTRL2 register
+ */
+/*@{*/
+#define CAN_RD_CTRL2(base)       (CAN_CTRL2_REG(base))
+#define CAN_WR_CTRL2(base, value) (CAN_CTRL2_REG(base) = (value))
+#define CAN_RMW_CTRL2(base, mask, value) (CAN_WR_CTRL2(base, (CAN_RD_CTRL2(base) & ~(mask)) | (value)))
+#define CAN_SET_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) |  (value)))
+#define CAN_CLR_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) & ~(value)))
+#define CAN_TOG_CTRL2(base, value) (CAN_WR_CTRL2(base, CAN_RD_CTRL2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CTRL2 bitfields
+ */
+
+/*!
+ * @name Register CAN_CTRL2, field EACEN[16] (RW)
+ *
+ * This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
+ * filters with their corresponding bits in the incoming frame by the matching
+ * process. This bit does not affect matching for Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
+ *     compared despite mask bits.
+ * - 0b1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit
+ *     with their corresponding bits within the incoming frame. Mask bits do apply.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_EACEN field. */
+#define CAN_RD_CTRL2_EACEN(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_EACEN_MASK) >> CAN_CTRL2_EACEN_SHIFT)
+#define CAN_BRD_CTRL2_EACEN(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_EACEN_SHIFT))
+
+/*! @brief Set the EACEN field to a new value. */
+#define CAN_WR_CTRL2_EACEN(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_EACEN_MASK, CAN_CTRL2_EACEN(value)))
+#define CAN_BWR_CTRL2_EACEN(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_EACEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field RRS[17] (RW)
+ *
+ * If this bit is asserted Remote Request Frame is submitted to a matching
+ * process and stored in the corresponding Message Buffer in the same fashion of a
+ * Data Frame. No automatic Remote Response Frame will be generated. If this bit is
+ * negated the Remote Request Frame is submitted to a matching process and an
+ * automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
+ * is found with the same ID. This bit can be written only in Freeze mode
+ * because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Remote Response Frame is generated.
+ * - 0b1 - Remote Request Frame is stored.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_RRS field. */
+#define CAN_RD_CTRL2_RRS(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_RRS_MASK) >> CAN_CTRL2_RRS_SHIFT)
+#define CAN_BRD_CTRL2_RRS(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_RRS_SHIFT))
+
+/*! @brief Set the RRS field to a new value. */
+#define CAN_WR_CTRL2_RRS(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_RRS_MASK, CAN_CTRL2_RRS(value)))
+#define CAN_BWR_CTRL2_RRS(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_RRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field MRP[18] (RW)
+ *
+ * If this bit is set the matching process starts from the Mailboxes and if no
+ * match occurs the matching continues on the Rx FIFO. This bit can be written
+ * only in Freeze mode because it is blocked by hardware in other modes.
+ *
+ * Values:
+ * - 0b0 - Matching starts from Rx FIFO and continues on Mailboxes.
+ * - 0b1 - Matching starts from Mailboxes and continues on Rx FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_MRP field. */
+#define CAN_RD_CTRL2_MRP(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_MRP_MASK) >> CAN_CTRL2_MRP_SHIFT)
+#define CAN_BRD_CTRL2_MRP(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_MRP_SHIFT))
+
+/*! @brief Set the MRP field to a new value. */
+#define CAN_WR_CTRL2_MRP(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_MRP_MASK, CAN_CTRL2_MRP(value)))
+#define CAN_BWR_CTRL2_MRP(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_MRP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field TASD[23:19] (RW)
+ *
+ * This 5-bit field indicates how many CAN bits the Tx arbitration process start
+ * point can be delayed from the first bit of CRC field on CAN bus. This field
+ * can be written only in Freeze mode because it is blocked by hardware in other
+ * modes. This field is useful to optimize the transmit performance based on
+ * factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
+ * The duration of an arbitration process, in terms of CAN bits, is directly
+ * proportional to the number of available MBs and CAN baud rate and inversely
+ * proportional to the peripheral clock frequency. The optimal arbitration timing is
+ * that in which the last MB is scanned right before the first bit of the
+ * Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
+ * clock ratio is high and the CAN baud rate is low then the arbitration can be
+ * delayed and vice-versa. If TASD is 0 then the arbitration start is not
+ * delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
+ * but more time is reserved for arbitration. On the other hand, if TASD is 24 then
+ * the CPU can configure a Tx MB later and less time is reserved for
+ * arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
+ * to find winner MBs in time to compete with other nodes for the CAN bus. If the
+ * arbitration ends too much time before the first bit of Intermission field then
+ * there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
+ * not the best to be transmitted. The optimal configuration for TASD can be
+ * calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
+ * 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
+ * CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
+ * Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
+ * field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
+ * PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
+ * field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
+ * CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
+ * Timing" for more details.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_TASD field. */
+#define CAN_RD_CTRL2_TASD(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_TASD_MASK) >> CAN_CTRL2_TASD_SHIFT)
+#define CAN_BRD_CTRL2_TASD(base) (CAN_RD_CTRL2_TASD(base))
+
+/*! @brief Set the TASD field to a new value. */
+#define CAN_WR_CTRL2_TASD(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_TASD_MASK, CAN_CTRL2_TASD(value)))
+#define CAN_BWR_CTRL2_TASD(base, value) (CAN_WR_CTRL2_TASD(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field RFFN[27:24] (RW)
+ *
+ * This 4-bit field defines the number of Rx FIFO filters, as shown in the
+ * following table. The maximum selectable number of filters is determined by the MCU.
+ * This field can only be written in Freeze mode as it is blocked by hardware in
+ * other modes. This field must not be programmed with values that make the
+ * number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
+ * Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
+ * a memory space equivalent to two Message Buffers which means that the more
+ * filters are implemented the less Mailboxes will be available. Considering that
+ * the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
+ * be programmed with a value correponding to a number of filters not greater
+ * than the number of available memory words which can be calculated as follows:
+ * (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
+ * The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
+ * 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
+ * SETUP_MB value (memory space available) the exceeding ones will not be functional.
+ * RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
+ * Filter Table Remaining Available MailboxesThe number of the last remaining
+ * available mailboxes is defined by the least value between the parameter
+ * NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
+ * by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
+ * all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
+ * Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
+ * 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
+ * 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
+ * Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
+ * 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
+ * Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
+ * 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
+ * Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
+ * 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
+ * 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
+ * Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
+ * 0-37 MB 38-63 Elements 0-31 Elements 32-127
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_RFFN field. */
+#define CAN_RD_CTRL2_RFFN(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT)
+#define CAN_BRD_CTRL2_RFFN(base) (CAN_RD_CTRL2_RFFN(base))
+
+/*! @brief Set the RFFN field to a new value. */
+#define CAN_WR_CTRL2_RFFN(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_RFFN_MASK, CAN_CTRL2_RFFN(value)))
+#define CAN_BWR_CTRL2_RFFN(base, value) (CAN_WR_CTRL2_RFFN(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
+ *
+ * Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
+ * can only be written in Freeze mode and has no effect out of Freeze mode.
+ *
+ * Values:
+ * - 0b0 - Maintain the write access restrictions.
+ * - 0b1 - Enable unrestricted write access to FlexCAN memory.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CTRL2_WRMFRZ field. */
+#define CAN_RD_CTRL2_WRMFRZ(base) ((CAN_CTRL2_REG(base) & CAN_CTRL2_WRMFRZ_MASK) >> CAN_CTRL2_WRMFRZ_SHIFT)
+#define CAN_BRD_CTRL2_WRMFRZ(base) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_WRMFRZ_SHIFT))
+
+/*! @brief Set the WRMFRZ field to a new value. */
+#define CAN_WR_CTRL2_WRMFRZ(base, value) (CAN_RMW_CTRL2(base, CAN_CTRL2_WRMFRZ_MASK, CAN_CTRL2_WRMFRZ(value)))
+#define CAN_BWR_CTRL2_WRMFRZ(base, value) (BITBAND_ACCESS32(&CAN_CTRL2_REG(base), CAN_CTRL2_WRMFRZ_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ESR2 - Error and Status 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ESR2 - Error and Status 2 register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register reflects various interrupt flags and some general status.
+ */
+/*!
+ * @name Constants and macros for entire CAN_ESR2 register
+ */
+/*@{*/
+#define CAN_RD_ESR2(base)        (CAN_ESR2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ESR2 bitfields
+ */
+
+/*!
+ * @name Register CAN_ESR2, field IMB[13] (RO)
+ *
+ * If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
+ * Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
+ * following cases: During arbitration, if an LPTM is found and it is inactive. If
+ * IMB is not asserted and a frame is transmitted successfully. This bit is
+ * cleared in all start of arbitration (see Section "Arbitration process"). LPTM
+ * mechanism have the following behavior: if an MB is successfully transmitted and
+ * ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
+ * the index related to the MB just transmitted is loaded into ESR2[LPTM].
+ *
+ * Values:
+ * - 0b0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
+ * - 0b1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox.
+ *     LPTM content is the number of the first one.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_IMB field. */
+#define CAN_RD_ESR2_IMB(base) ((CAN_ESR2_REG(base) & CAN_ESR2_IMB_MASK) >> CAN_ESR2_IMB_SHIFT)
+#define CAN_BRD_ESR2_IMB(base) (BITBAND_ACCESS32(&CAN_ESR2_REG(base), CAN_ESR2_IMB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR2, field VPS[14] (RO)
+ *
+ * This bit indicates whether IMB and LPTM contents are currently valid or not.
+ * VPS is asserted upon every complete Tx arbitration process unless the CPU
+ * writes to Control and Status word of a Mailbox that has already been scanned, that
+ * is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
+ * If there is no inactive Mailbox and only one Tx Mailbox that is being
+ * transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
+ * arbitration process or upon a write to Control and Status word of any Mailbox.
+ * ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
+ * blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
+ * in C/S of a MB that is being transmitted (pending abort), or any write attempt
+ * into a Tx MB with IFLAG set is blocked.
+ *
+ * Values:
+ * - 0b0 - Contents of IMB and LPTM are invalid.
+ * - 0b1 - Contents of IMB and LPTM are valid.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_VPS field. */
+#define CAN_RD_ESR2_VPS(base) ((CAN_ESR2_REG(base) & CAN_ESR2_VPS_MASK) >> CAN_ESR2_VPS_SHIFT)
+#define CAN_BRD_ESR2_VPS(base) (BITBAND_ACCESS32(&CAN_ESR2_REG(base), CAN_ESR2_VPS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CAN_ESR2, field LPTM[22:16] (RO)
+ *
+ * If ESR2[VPS] is asserted, this field indicates the lowest number inactive
+ * Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
+ * Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
+ * negated then the Mailbox indicated is the one that has the greatest arbitration
+ * value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
+ * asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
+ * a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
+ * If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
+ * updated with its Mailbox number.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ESR2_LPTM field. */
+#define CAN_RD_ESR2_LPTM(base) ((CAN_ESR2_REG(base) & CAN_ESR2_LPTM_MASK) >> CAN_ESR2_LPTM_SHIFT)
+#define CAN_BRD_ESR2_LPTM(base) (CAN_RD_ESR2_LPTM(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CRCR - CRC Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CRCR - CRC Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides information about the CRC of transmitted messages.
+ */
+/*!
+ * @name Constants and macros for entire CAN_CRCR register
+ */
+/*@{*/
+#define CAN_RD_CRCR(base)        (CAN_CRCR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CRCR bitfields
+ */
+
+/*!
+ * @name Register CAN_CRCR, field TXCRC[14:0] (RO)
+ *
+ * This field indicates the CRC value of the last message transmitted. This
+ * field is updated at the same time the Tx Interrupt Flag is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CRCR_TXCRC field. */
+#define CAN_RD_CRCR_TXCRC(base) ((CAN_CRCR_REG(base) & CAN_CRCR_TXCRC_MASK) >> CAN_CRCR_TXCRC_SHIFT)
+#define CAN_BRD_CRCR_TXCRC(base) (CAN_RD_CRCR_TXCRC(base))
+/*@}*/
+
+/*!
+ * @name Register CAN_CRCR, field MBCRC[22:16] (RO)
+ *
+ * This field indicates the number of the Mailbox corresponding to the value in
+ * TXCRC field.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CRCR_MBCRC field. */
+#define CAN_RD_CRCR_MBCRC(base) ((CAN_CRCR_REG(base) & CAN_CRCR_MBCRC_MASK) >> CAN_CRCR_MBCRC_SHIFT)
+#define CAN_BRD_CRCR_MBCRC(base) (CAN_RD_CRCR_MBCRC(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXFGMASK - Rx FIFO Global Mask register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
+ * mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
+ * according to CTRL2[RFFN] field setting. This register can only be written in
+ * Freeze mode as it is blocked by hardware in other modes.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXFGMASK register
+ */
+/*@{*/
+#define CAN_RD_RXFGMASK(base)    (CAN_RXFGMASK_REG(base))
+#define CAN_WR_RXFGMASK(base, value) (CAN_RXFGMASK_REG(base) = (value))
+#define CAN_RMW_RXFGMASK(base, mask, value) (CAN_WR_RXFGMASK(base, (CAN_RD_RXFGMASK(base) & ~(mask)) | (value)))
+#define CAN_SET_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) |  (value)))
+#define CAN_CLR_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) & ~(value)))
+#define CAN_TOG_RXFGMASK(base, value) (CAN_WR_RXFGMASK(base, CAN_RD_RXFGMASK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXFIR - Rx FIFO Information Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXFIR - Rx FIFO Information Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFIR provides information on Rx FIFO. This register is the port through
+ * which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
+ * is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
+ * well as its output is updated whenever the output of the Rx FIFO is updated
+ * with the next message. See Section "Rx FIFO" for instructions on reading this
+ * register.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXFIR register
+ */
+/*@{*/
+#define CAN_RD_RXFIR(base)       (CAN_RXFIR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_RXFIR bitfields
+ */
+
+/*!
+ * @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
+ *
+ * This field indicates which Identifier Acceptance Filter was hit by the
+ * received message that is in the output of the Rx FIFO. If multiple filters match the
+ * incoming message ID then the first matching IDAF found (lowest number) by the
+ * matching process is indicated. This field is valid only while the
+ * IFLAG[BUF5I] is asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_RXFIR_IDHIT field. */
+#define CAN_RD_RXFIR_IDHIT(base) ((CAN_RXFIR_REG(base) & CAN_RXFIR_IDHIT_MASK) >> CAN_RXFIR_IDHIT_SHIFT)
+#define CAN_BRD_RXFIR_IDHIT(base) (CAN_RD_RXFIR_IDHIT(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_CS - Message Buffer 0 CS Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_CS - Message Buffer 0 CS Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_CS register
+ */
+/*@{*/
+#define CAN_RD_CS(base, index)   (CAN_CS_REG(base, index))
+#define CAN_WR_CS(base, index, value) (CAN_CS_REG(base, index) = (value))
+#define CAN_RMW_CS(base, index, mask, value) (CAN_WR_CS(base, index, (CAN_RD_CS(base, index) & ~(mask)) | (value)))
+#define CAN_SET_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) |  (value)))
+#define CAN_CLR_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) & ~(value)))
+#define CAN_TOG_CS(base, index, value) (CAN_WR_CS(base, index, CAN_RD_CS(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_CS bitfields
+ */
+
+/*!
+ * @name Register CAN_CS, field TIME_STAMP[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_TIME_STAMP field. */
+#define CAN_RD_CS_TIME_STAMP(base, index) ((CAN_CS_REG(base, index) & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT)
+#define CAN_BRD_CS_TIME_STAMP(base, index) (CAN_RD_CS_TIME_STAMP(base, index))
+
+/*! @brief Set the TIME_STAMP field to a new value. */
+#define CAN_WR_CS_TIME_STAMP(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_TIME_STAMP_MASK, CAN_CS_TIME_STAMP(value)))
+#define CAN_BWR_CS_TIME_STAMP(base, index, value) (CAN_WR_CS_TIME_STAMP(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field DLC[19:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_DLC field. */
+#define CAN_RD_CS_DLC(base, index) ((CAN_CS_REG(base, index) & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT)
+#define CAN_BRD_CS_DLC(base, index) (CAN_RD_CS_DLC(base, index))
+
+/*! @brief Set the DLC field to a new value. */
+#define CAN_WR_CS_DLC(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_DLC_MASK, CAN_CS_DLC(value)))
+#define CAN_BWR_CS_DLC(base, index, value) (CAN_WR_CS_DLC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field RTR[20] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_RTR field. */
+#define CAN_RD_CS_RTR(base, index) ((CAN_CS_REG(base, index) & CAN_CS_RTR_MASK) >> CAN_CS_RTR_SHIFT)
+#define CAN_BRD_CS_RTR(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_RTR_SHIFT))
+
+/*! @brief Set the RTR field to a new value. */
+#define CAN_WR_CS_RTR(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_RTR_MASK, CAN_CS_RTR(value)))
+#define CAN_BWR_CS_RTR(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_RTR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field IDE[21] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_IDE field. */
+#define CAN_RD_CS_IDE(base, index) ((CAN_CS_REG(base, index) & CAN_CS_IDE_MASK) >> CAN_CS_IDE_SHIFT)
+#define CAN_BRD_CS_IDE(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_IDE_SHIFT))
+
+/*! @brief Set the IDE field to a new value. */
+#define CAN_WR_CS_IDE(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_IDE_MASK, CAN_CS_IDE(value)))
+#define CAN_BWR_CS_IDE(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_IDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field SRR[22] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_SRR field. */
+#define CAN_RD_CS_SRR(base, index) ((CAN_CS_REG(base, index) & CAN_CS_SRR_MASK) >> CAN_CS_SRR_SHIFT)
+#define CAN_BRD_CS_SRR(base, index) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_SRR_SHIFT))
+
+/*! @brief Set the SRR field to a new value. */
+#define CAN_WR_CS_SRR(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_SRR_MASK, CAN_CS_SRR(value)))
+#define CAN_BWR_CS_SRR(base, index, value) (BITBAND_ACCESS32(&CAN_CS_REG(base, index), CAN_CS_SRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CAN_CS, field CODE[27:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_CS_CODE field. */
+#define CAN_RD_CS_CODE(base, index) ((CAN_CS_REG(base, index) & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT)
+#define CAN_BRD_CS_CODE(base, index) (CAN_RD_CS_CODE(base, index))
+
+/*! @brief Set the CODE field to a new value. */
+#define CAN_WR_CS_CODE(base, index, value) (CAN_RMW_CS(base, index, CAN_CS_CODE_MASK, CAN_CS_CODE(value)))
+#define CAN_BWR_CS_CODE(base, index, value) (CAN_WR_CS_CODE(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_ID - Message Buffer 0 ID Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_ID - Message Buffer 0 ID Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_ID register
+ */
+/*@{*/
+#define CAN_RD_ID(base, index)   (CAN_ID_REG(base, index))
+#define CAN_WR_ID(base, index, value) (CAN_ID_REG(base, index) = (value))
+#define CAN_RMW_ID(base, index, mask, value) (CAN_WR_ID(base, index, (CAN_RD_ID(base, index) & ~(mask)) | (value)))
+#define CAN_SET_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) |  (value)))
+#define CAN_CLR_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) & ~(value)))
+#define CAN_TOG_ID(base, index, value) (CAN_WR_ID(base, index, CAN_RD_ID(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_ID bitfields
+ */
+
+/*!
+ * @name Register CAN_ID, field EXT[17:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_EXT field. */
+#define CAN_RD_ID_EXT(base, index) ((CAN_ID_REG(base, index) & CAN_ID_EXT_MASK) >> CAN_ID_EXT_SHIFT)
+#define CAN_BRD_ID_EXT(base, index) (CAN_RD_ID_EXT(base, index))
+
+/*! @brief Set the EXT field to a new value. */
+#define CAN_WR_ID_EXT(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_EXT_MASK, CAN_ID_EXT(value)))
+#define CAN_BWR_ID_EXT(base, index, value) (CAN_WR_ID_EXT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ID, field STD[28:18] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_STD field. */
+#define CAN_RD_ID_STD(base, index) ((CAN_ID_REG(base, index) & CAN_ID_STD_MASK) >> CAN_ID_STD_SHIFT)
+#define CAN_BRD_ID_STD(base, index) (CAN_RD_ID_STD(base, index))
+
+/*! @brief Set the STD field to a new value. */
+#define CAN_WR_ID_STD(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_STD_MASK, CAN_ID_STD(value)))
+#define CAN_BWR_ID_STD(base, index, value) (CAN_WR_ID_STD(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_ID, field PRIO[31:29] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_ID_PRIO field. */
+#define CAN_RD_ID_PRIO(base, index) ((CAN_ID_REG(base, index) & CAN_ID_PRIO_MASK) >> CAN_ID_PRIO_SHIFT)
+#define CAN_BRD_ID_PRIO(base, index) (CAN_RD_ID_PRIO(base, index))
+
+/*! @brief Set the PRIO field to a new value. */
+#define CAN_WR_ID_PRIO(base, index, value) (CAN_RMW_ID(base, index, CAN_ID_PRIO_MASK, CAN_ID_PRIO(value)))
+#define CAN_BWR_ID_PRIO(base, index, value) (CAN_WR_ID_PRIO(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_WORD0 - Message Buffer 0 WORD0 Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_WORD0 - Message Buffer 0 WORD0 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_WORD0 register
+ */
+/*@{*/
+#define CAN_RD_WORD0(base, index) (CAN_WORD0_REG(base, index))
+#define CAN_WR_WORD0(base, index, value) (CAN_WORD0_REG(base, index) = (value))
+#define CAN_RMW_WORD0(base, index, mask, value) (CAN_WR_WORD0(base, index, (CAN_RD_WORD0(base, index) & ~(mask)) | (value)))
+#define CAN_SET_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) |  (value)))
+#define CAN_CLR_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) & ~(value)))
+#define CAN_TOG_WORD0(base, index, value) (CAN_WR_WORD0(base, index, CAN_RD_WORD0(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_WORD0 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_3[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_3 field. */
+#define CAN_RD_WORD0_DATA_BYTE_3(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_3_MASK) >> CAN_WORD0_DATA_BYTE_3_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_3(base, index) (CAN_RD_WORD0_DATA_BYTE_3(base, index))
+
+/*! @brief Set the DATA_BYTE_3 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_3(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_3_MASK, CAN_WORD0_DATA_BYTE_3(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_3(base, index, value) (CAN_WR_WORD0_DATA_BYTE_3(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_2[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_2 field. */
+#define CAN_RD_WORD0_DATA_BYTE_2(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_2_MASK) >> CAN_WORD0_DATA_BYTE_2_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_2(base, index) (CAN_RD_WORD0_DATA_BYTE_2(base, index))
+
+/*! @brief Set the DATA_BYTE_2 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_2(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_2_MASK, CAN_WORD0_DATA_BYTE_2(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_2(base, index, value) (CAN_WR_WORD0_DATA_BYTE_2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_1[23:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_1 field. */
+#define CAN_RD_WORD0_DATA_BYTE_1(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_1_MASK) >> CAN_WORD0_DATA_BYTE_1_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_1(base, index) (CAN_RD_WORD0_DATA_BYTE_1(base, index))
+
+/*! @brief Set the DATA_BYTE_1 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_1(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_1_MASK, CAN_WORD0_DATA_BYTE_1(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_1(base, index, value) (CAN_WR_WORD0_DATA_BYTE_1(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD0, field DATA_BYTE_0[31:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD0_DATA_BYTE_0 field. */
+#define CAN_RD_WORD0_DATA_BYTE_0(base, index) ((CAN_WORD0_REG(base, index) & CAN_WORD0_DATA_BYTE_0_MASK) >> CAN_WORD0_DATA_BYTE_0_SHIFT)
+#define CAN_BRD_WORD0_DATA_BYTE_0(base, index) (CAN_RD_WORD0_DATA_BYTE_0(base, index))
+
+/*! @brief Set the DATA_BYTE_0 field to a new value. */
+#define CAN_WR_WORD0_DATA_BYTE_0(base, index, value) (CAN_RMW_WORD0(base, index, CAN_WORD0_DATA_BYTE_0_MASK, CAN_WORD0_DATA_BYTE_0(value)))
+#define CAN_BWR_WORD0_DATA_BYTE_0(base, index, value) (CAN_WR_WORD0_DATA_BYTE_0(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_WORD1 - Message Buffer 0 WORD1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_WORD1 - Message Buffer 0 WORD1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAN_WORD1 register
+ */
+/*@{*/
+#define CAN_RD_WORD1(base, index) (CAN_WORD1_REG(base, index))
+#define CAN_WR_WORD1(base, index, value) (CAN_WORD1_REG(base, index) = (value))
+#define CAN_RMW_WORD1(base, index, mask, value) (CAN_WR_WORD1(base, index, (CAN_RD_WORD1(base, index) & ~(mask)) | (value)))
+#define CAN_SET_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) |  (value)))
+#define CAN_CLR_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) & ~(value)))
+#define CAN_TOG_WORD1(base, index, value) (CAN_WR_WORD1(base, index, CAN_RD_WORD1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAN_WORD1 bitfields
+ */
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_7[7:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_7 field. */
+#define CAN_RD_WORD1_DATA_BYTE_7(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_7_MASK) >> CAN_WORD1_DATA_BYTE_7_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_7(base, index) (CAN_RD_WORD1_DATA_BYTE_7(base, index))
+
+/*! @brief Set the DATA_BYTE_7 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_7(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_7_MASK, CAN_WORD1_DATA_BYTE_7(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_7(base, index, value) (CAN_WR_WORD1_DATA_BYTE_7(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_6[15:8] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_6 field. */
+#define CAN_RD_WORD1_DATA_BYTE_6(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_6_MASK) >> CAN_WORD1_DATA_BYTE_6_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_6(base, index) (CAN_RD_WORD1_DATA_BYTE_6(base, index))
+
+/*! @brief Set the DATA_BYTE_6 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_6(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_6_MASK, CAN_WORD1_DATA_BYTE_6(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_6(base, index, value) (CAN_WR_WORD1_DATA_BYTE_6(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_5[23:16] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_5 field. */
+#define CAN_RD_WORD1_DATA_BYTE_5(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_5_MASK) >> CAN_WORD1_DATA_BYTE_5_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_5(base, index) (CAN_RD_WORD1_DATA_BYTE_5(base, index))
+
+/*! @brief Set the DATA_BYTE_5 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_5(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_5_MASK, CAN_WORD1_DATA_BYTE_5(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_5(base, index, value) (CAN_WR_WORD1_DATA_BYTE_5(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register CAN_WORD1, field DATA_BYTE_4[31:24] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the CAN_WORD1_DATA_BYTE_4 field. */
+#define CAN_RD_WORD1_DATA_BYTE_4(base, index) ((CAN_WORD1_REG(base, index) & CAN_WORD1_DATA_BYTE_4_MASK) >> CAN_WORD1_DATA_BYTE_4_SHIFT)
+#define CAN_BRD_WORD1_DATA_BYTE_4(base, index) (CAN_RD_WORD1_DATA_BYTE_4(base, index))
+
+/*! @brief Set the DATA_BYTE_4 field to a new value. */
+#define CAN_WR_WORD1_DATA_BYTE_4(base, index, value) (CAN_RMW_WORD1(base, index, CAN_WORD1_DATA_BYTE_4_MASK, CAN_WORD1_DATA_BYTE_4(value)))
+#define CAN_BWR_WORD1_DATA_BYTE_4(base, index, value) (CAN_WR_WORD1_DATA_BYTE_4(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAN_RXIMR - Rx Individual Mask Registers
+ ******************************************************************************/
+
+/*!
+ * @brief CAN_RXIMR - Rx Individual Mask Registers (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers are located in RAM. RXIMR are used as acceptance masks for ID
+ * filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
+ * register is provided for each available Mailbox, providing ID masking
+ * capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
+ * asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
+ * Table elements on a one-to-one correspondence depending on the setting of
+ * CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
+ * mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
+ * are not affected by reset and must be explicitly initialized prior to any
+ * reception.
+ */
+/*!
+ * @name Constants and macros for entire CAN_RXIMR register
+ */
+/*@{*/
+#define CAN_RD_RXIMR(base, index) (CAN_RXIMR_REG(base, index))
+#define CAN_WR_RXIMR(base, index, value) (CAN_RXIMR_REG(base, index) = (value))
+#define CAN_RMW_RXIMR(base, index, mask, value) (CAN_WR_RXIMR(base, index, (CAN_RD_RXIMR(base, index) & ~(mask)) | (value)))
+#define CAN_SET_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) |  (value)))
+#define CAN_CLR_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) & ~(value)))
+#define CAN_TOG_RXIMR(base, index, value) (CAN_WR_RXIMR(base, index, CAN_RD_RXIMR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 CAU
+ *
+ * Memory Mapped Cryptographic Acceleration Unit (MMCAU)
+ *
+ * Registers defined in this header file:
+ * - CAU_DIRECT - Direct access register 0
+ * - CAU_LDR_CASR - Status register - Load Register command
+ * - CAU_LDR_CAA - Accumulator register - Load Register command
+ * - CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ * - CAU_STR_CASR - Status register - Store Register command
+ * - CAU_STR_CAA - Accumulator register - Store Register command
+ * - CAU_STR_CA - General Purpose Register 0 - Store Register command
+ * - CAU_ADR_CASR - Status register - Add Register command
+ * - CAU_ADR_CAA - Accumulator register - Add to register command
+ * - CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ * - CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ * - CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ * - CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ * - CAU_XOR_CASR - Status register - Exclusive Or command
+ * - CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ * - CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ * - CAU_ROTL_CASR - Status register - Rotate Left command
+ * - CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ * - CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ * - CAU_AESC_CASR - Status register - AES Column Operation command
+ * - CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ * - CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ * - CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ * - CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ * - CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ */
+
+#define CAU_INSTANCE_COUNT (1U) /*!< Number of instances of the CAU module. */
+#define CAU_IDX (0U) /*!< Instance number for CAU. */
+
+/*******************************************************************************
+ * CAU_DIRECT - Direct access register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_DIRECT - Direct access register 0 (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_DIRECT register
+ */
+/*@{*/
+#define CAU_WR_DIRECT(base, index, value) (CAU_DIRECT_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CASR - Status register - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CASR - Status register - Load Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CASR register
+ */
+/*@{*/
+#define CAU_WR_LDR_CASR(base, value) (CAU_LDR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_LDR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_LDR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_LDR_CASR_IC(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_IC(value)))
+#define CAU_BWR_LDR_CASR_IC(base, value) (CAU_WR_LDR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_LDR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_LDR_CASR_DPE(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_DPE(value)))
+#define CAU_BWR_LDR_CASR_DPE(base, value) (CAU_WR_LDR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_LDR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_LDR_CASR_VER(base, value) (CAU_WR_LDR_CASR(base, CAU_LDR_CASR_VER(value)))
+#define CAU_BWR_LDR_CASR_VER(base, value) (CAU_WR_LDR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CAA - Accumulator register - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CAA - Accumulator register - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CAA register
+ */
+/*@{*/
+#define CAU_WR_LDR_CAA(base, value) (CAU_LDR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_LDR_CA - General Purpose Register 0 - Load Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_LDR_CA - General Purpose Register 0 - Load Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_LDR_CA register
+ */
+/*@{*/
+#define CAU_WR_LDR_CA(base, index, value) (CAU_LDR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CASR - Status register - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CASR - Status register - Store Register command (RO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CASR register
+ */
+/*@{*/
+#define CAU_RD_STR_CASR(base)    (CAU_STR_CASR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_STR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_STR_CASR, field IC[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_IC field. */
+#define CAU_RD_STR_CASR_IC(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_IC_MASK) >> CAU_STR_CASR_IC_SHIFT)
+#define CAU_BRD_STR_CASR_IC(base) (CAU_RD_STR_CASR_IC(base))
+/*@}*/
+
+/*!
+ * @name Register CAU_STR_CASR, field DPE[1] (RO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_DPE field. */
+#define CAU_RD_STR_CASR_DPE(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_DPE_MASK) >> CAU_STR_CASR_DPE_SHIFT)
+#define CAU_BRD_STR_CASR_DPE(base) (CAU_RD_STR_CASR_DPE(base))
+/*@}*/
+
+/*!
+ * @name Register CAU_STR_CASR, field VER[31:28] (RO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Read current value of the CAU_STR_CASR_VER field. */
+#define CAU_RD_STR_CASR_VER(base) ((CAU_STR_CASR_REG(base) & CAU_STR_CASR_VER_MASK) >> CAU_STR_CASR_VER_SHIFT)
+#define CAU_BRD_STR_CASR_VER(base) (CAU_RD_STR_CASR_VER(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CAA - Accumulator register - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CAA - Accumulator register - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CAA register
+ */
+/*@{*/
+#define CAU_RD_STR_CAA(base)     (CAU_STR_CAA_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_STR_CA - General Purpose Register 0 - Store Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_STR_CA - General Purpose Register 0 - Store Register command (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_STR_CA register
+ */
+/*@{*/
+#define CAU_RD_STR_CA(base, index) (CAU_STR_CA_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CASR - Status register - Add Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CASR - Status register - Add Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CASR register
+ */
+/*@{*/
+#define CAU_WR_ADR_CASR(base, value) (CAU_ADR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_ADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_ADR_CASR_IC(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_IC(value)))
+#define CAU_BWR_ADR_CASR_IC(base, value) (CAU_WR_ADR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_ADR_CASR_DPE(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_DPE(value)))
+#define CAU_BWR_ADR_CASR_DPE(base, value) (CAU_WR_ADR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_ADR_CASR_VER(base, value) (CAU_WR_ADR_CASR(base, CAU_ADR_CASR_VER(value)))
+#define CAU_BWR_ADR_CASR_VER(base, value) (CAU_WR_ADR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CAA - Accumulator register - Add to register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CAA - Accumulator register - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CAA register
+ */
+/*@{*/
+#define CAU_WR_ADR_CAA(base, value) (CAU_ADR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ADR_CA - General Purpose Register 0 - Add to register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ADR_CA - General Purpose Register 0 - Add to register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ADR_CA register
+ */
+/*@{*/
+#define CAU_WR_ADR_CA(base, index, value) (CAU_ADR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CASR - Status register - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CASR - Status register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CASR register
+ */
+/*@{*/
+#define CAU_WR_RADR_CASR(base, value) (CAU_RADR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_RADR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_RADR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_RADR_CASR_IC(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_IC(value)))
+#define CAU_BWR_RADR_CASR_IC(base, value) (CAU_WR_RADR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_RADR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_RADR_CASR_DPE(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_DPE(value)))
+#define CAU_BWR_RADR_CASR_DPE(base, value) (CAU_WR_RADR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_RADR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_RADR_CASR_VER(base, value) (CAU_WR_RADR_CASR(base, CAU_RADR_CASR_VER(value)))
+#define CAU_BWR_RADR_CASR_VER(base, value) (CAU_WR_RADR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CAA register
+ */
+/*@{*/
+#define CAU_WR_RADR_CAA(base, value) (CAU_RADR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_RADR_CA - General Purpose Register 0 - Reverse and Add to Register command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_RADR_CA register
+ */
+/*@{*/
+#define CAU_WR_RADR_CA(base, index, value) (CAU_RADR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CASR - Status register - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CASR - Status register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CASR register
+ */
+/*@{*/
+#define CAU_WR_XOR_CASR(base, value) (CAU_XOR_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_XOR_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_XOR_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_XOR_CASR_IC(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_IC(value)))
+#define CAU_BWR_XOR_CASR_IC(base, value) (CAU_WR_XOR_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_XOR_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_XOR_CASR_DPE(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_DPE(value)))
+#define CAU_BWR_XOR_CASR_DPE(base, value) (CAU_WR_XOR_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_XOR_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_XOR_CASR_VER(base, value) (CAU_WR_XOR_CASR(base, CAU_XOR_CASR_VER(value)))
+#define CAU_BWR_XOR_CASR_VER(base, value) (CAU_WR_XOR_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CAA - Accumulator register - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CAA register
+ */
+/*@{*/
+#define CAU_WR_XOR_CAA(base, value) (CAU_XOR_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_XOR_CA - General Purpose Register 0 - Exclusive Or command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_XOR_CA register
+ */
+/*@{*/
+#define CAU_WR_XOR_CA(base, index, value) (CAU_XOR_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CASR - Status register - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CASR - Status register - Rotate Left command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CASR register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CASR(base, value) (CAU_ROTL_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_ROTL_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_ROTL_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_ROTL_CASR_IC(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_IC(value)))
+#define CAU_BWR_ROTL_CASR_IC(base, value) (CAU_WR_ROTL_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ROTL_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_ROTL_CASR_DPE(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_DPE(value)))
+#define CAU_BWR_ROTL_CASR_DPE(base, value) (CAU_WR_ROTL_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_ROTL_CASR_VER(base, value) (CAU_WR_ROTL_CASR(base, CAU_ROTL_CASR_VER(value)))
+#define CAU_BWR_ROTL_CASR_VER(base, value) (CAU_WR_ROTL_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CAA - Accumulator register - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CAA register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CAA(base, value) (CAU_ROTL_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_ROTL_CA - General Purpose Register 0 - Rotate Left command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_ROTL_CA register
+ */
+/*@{*/
+#define CAU_WR_ROTL_CA(base, index, value) (CAU_ROTL_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CASR - Status register - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CASR - Status register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CASR register
+ */
+/*@{*/
+#define CAU_WR_AESC_CASR(base, value) (CAU_AESC_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_AESC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_AESC_CASR_IC(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_IC(value)))
+#define CAU_BWR_AESC_CASR_IC(base, value) (CAU_WR_AESC_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_AESC_CASR_DPE(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_DPE(value)))
+#define CAU_BWR_AESC_CASR_DPE(base, value) (CAU_WR_AESC_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_AESC_CASR_VER(base, value) (CAU_WR_AESC_CASR(base, CAU_AESC_CASR_VER(value)))
+#define CAU_BWR_AESC_CASR_VER(base, value) (CAU_WR_AESC_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CAA - Accumulator register - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CAA register
+ */
+/*@{*/
+#define CAU_WR_AESC_CAA(base, value) (CAU_AESC_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESC_CA - General Purpose Register 0 - AES Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESC_CA register
+ */
+/*@{*/
+#define CAU_WR_AESC_CA(base, index, value) (CAU_AESC_CA_REG(base, index) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CASR - Status register - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CASR - Status register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x20000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CASR register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CASR(base, value) (CAU_AESIC_CASR_REG(base) = (value))
+/*@}*/
+
+/*
+ * Constants & macros for individual CAU_AESIC_CASR bitfields
+ */
+
+/*!
+ * @name Register CAU_AESIC_CASR, field IC[0] (WO)
+ *
+ * Values:
+ * - 0b0 - No illegal commands issued
+ * - 0b1 - Illegal command issued
+ */
+/*@{*/
+/*! @brief Set the IC field to a new value. */
+#define CAU_WR_AESIC_CASR_IC(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_IC(value)))
+#define CAU_BWR_AESIC_CASR_IC(base, value) (CAU_WR_AESIC_CASR_IC(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESIC_CASR, field DPE[1] (WO)
+ *
+ * Values:
+ * - 0b0 - No error detected
+ * - 0b1 - DES key parity error detected
+ */
+/*@{*/
+/*! @brief Set the DPE field to a new value. */
+#define CAU_WR_AESIC_CASR_DPE(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_DPE(value)))
+#define CAU_BWR_AESIC_CASR_DPE(base, value) (CAU_WR_AESIC_CASR_DPE(base, value))
+/*@}*/
+
+/*!
+ * @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
+ *
+ * Values:
+ * - 0b0001 - Initial CAU version
+ * - 0b0010 - Second version, added support for SHA-256 algorithm.(This is the
+ *     value on this device)
+ */
+/*@{*/
+/*! @brief Set the VER field to a new value. */
+#define CAU_WR_AESIC_CASR_VER(base, value) (CAU_WR_AESIC_CASR(base, CAU_AESIC_CASR_VER(value)))
+#define CAU_BWR_AESIC_CASR_VER(base, value) (CAU_WR_AESIC_CASR_VER(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CAA register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CAA(base, value) (CAU_AESIC_CAA_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command
+ ******************************************************************************/
+
+/*!
+ * @brief CAU_AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command (WO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire CAU_AESIC_CA register
+ */
+/*@{*/
+#define CAU_WR_AESIC_CA(base, index, value) (CAU_AESIC_CA_REG(base, index) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CMP
+ *
+ * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
+ *
+ * Registers defined in this header file:
+ * - CMP_CR0 - CMP Control Register 0
+ * - CMP_CR1 - CMP Control Register 1
+ * - CMP_FPR - CMP Filter Period Register
+ * - CMP_SCR - CMP Status and Control Register
+ * - CMP_DACCR - DAC Control Register
+ * - CMP_MUXCR - MUX Control Register
+ */
+
+#define CMP_INSTANCE_COUNT (3U) /*!< Number of instances of the CMP module. */
+#define CMP0_IDX (0U) /*!< Instance number for CMP0. */
+#define CMP1_IDX (1U) /*!< Instance number for CMP1. */
+#define CMP2_IDX (2U) /*!< Instance number for CMP2. */
+
+/*******************************************************************************
+ * CMP_CR0 - CMP Control Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR0 - CMP Control Register 0 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR0 register
+ */
+/*@{*/
+#define CMP_RD_CR0(base)         (CMP_CR0_REG(base))
+#define CMP_WR_CR0(base, value)  (CMP_CR0_REG(base) = (value))
+#define CMP_RMW_CR0(base, mask, value) (CMP_WR_CR0(base, (CMP_RD_CR0(base) & ~(mask)) | (value)))
+#define CMP_SET_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) |  (value)))
+#define CMP_CLR_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) & ~(value)))
+#define CMP_TOG_CR0(base, value) (CMP_WR_CR0(base, CMP_RD_CR0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR0 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
+ *
+ * Defines the programmable hysteresis level. The hysteresis values associated
+ * with each level are device-specific. See the Data Sheet of the device for the
+ * exact values.
+ *
+ * Values:
+ * - 0b00 - Level 0
+ * - 0b01 - Level 1
+ * - 0b10 - Level 2
+ * - 0b11 - Level 3
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
+#define CMP_RD_CR0_HYSTCTR(base) ((CMP_CR0_REG(base) & CMP_CR0_HYSTCTR_MASK) >> CMP_CR0_HYSTCTR_SHIFT)
+#define CMP_BRD_CR0_HYSTCTR(base) (CMP_RD_CR0_HYSTCTR(base))
+
+/*! @brief Set the HYSTCTR field to a new value. */
+#define CMP_WR_CR0_HYSTCTR(base, value) (CMP_RMW_CR0(base, CMP_CR0_HYSTCTR_MASK, CMP_CR0_HYSTCTR(value)))
+#define CMP_BWR_CR0_HYSTCTR(base, value) (CMP_WR_CR0_HYSTCTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
+ *
+ * Represents the number of consecutive samples that must agree prior to the
+ * comparator ouput filter accepting a new output state. For information regarding
+ * filter programming and latency, see the Functional descriptionThe CMP module
+ * can be used to compare two analog input voltages applied to INP and INM. .
+ *
+ * Values:
+ * - 0b000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not
+ *     a legal state, and is not recommended. If SE = 0, COUT = COUTA.
+ * - 0b001 - One sample must agree. The comparator output is simply sampled.
+ * - 0b010 - 2 consecutive samples must agree.
+ * - 0b011 - 3 consecutive samples must agree.
+ * - 0b100 - 4 consecutive samples must agree.
+ * - 0b101 - 5 consecutive samples must agree.
+ * - 0b110 - 6 consecutive samples must agree.
+ * - 0b111 - 7 consecutive samples must agree.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
+#define CMP_RD_CR0_FILTER_CNT(base) ((CMP_CR0_REG(base) & CMP_CR0_FILTER_CNT_MASK) >> CMP_CR0_FILTER_CNT_SHIFT)
+#define CMP_BRD_CR0_FILTER_CNT(base) (CMP_RD_CR0_FILTER_CNT(base))
+
+/*! @brief Set the FILTER_CNT field to a new value. */
+#define CMP_WR_CR0_FILTER_CNT(base, value) (CMP_RMW_CR0(base, CMP_CR0_FILTER_CNT_MASK, CMP_CR0_FILTER_CNT(value)))
+#define CMP_BWR_CR0_FILTER_CNT(base, value) (CMP_WR_CR0_FILTER_CNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_CR1 - CMP Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_CR1 - CMP Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_CR1 register
+ */
+/*@{*/
+#define CMP_RD_CR1(base)         (CMP_CR1_REG(base))
+#define CMP_WR_CR1(base, value)  (CMP_CR1_REG(base) = (value))
+#define CMP_RMW_CR1(base, mask, value) (CMP_WR_CR1(base, (CMP_RD_CR1(base) & ~(mask)) | (value)))
+#define CMP_SET_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) |  (value)))
+#define CMP_CLR_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) & ~(value)))
+#define CMP_TOG_CR1(base, value) (CMP_WR_CR1(base, CMP_RD_CR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_CR1 bitfields
+ */
+
+/*!
+ * @name Register CMP_CR1, field EN[0] (RW)
+ *
+ * Enables the Analog Comparator module. When the module is not enabled, it
+ * remains in the off state, and consumes no power. When the user selects the same
+ * input from analog mux to the positive and negative port, the comparator is
+ * disabled automatically.
+ *
+ * Values:
+ * - 0b0 - Analog Comparator is disabled.
+ * - 0b1 - Analog Comparator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_EN field. */
+#define CMP_RD_CR1_EN(base)  ((CMP_CR1_REG(base) & CMP_CR1_EN_MASK) >> CMP_CR1_EN_SHIFT)
+#define CMP_BRD_CR1_EN(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT))
+
+/*! @brief Set the EN field to a new value. */
+#define CMP_WR_CR1_EN(base, value) (CMP_RMW_CR1(base, CMP_CR1_EN_MASK, CMP_CR1_EN(value)))
+#define CMP_BWR_CR1_EN(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field OPE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - CMPO is not available on the associated CMPO output pin. If the
+ *     comparator does not own the pin, this field has no effect.
+ * - 0b1 - CMPO is available on the associated CMPO output pin. The comparator
+ *     output (CMPO) is driven out on the associated CMPO output pin if the
+ *     comparator owns the pin. If the comparator does not own the field, this bit has
+ *     no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_OPE field. */
+#define CMP_RD_CR1_OPE(base) ((CMP_CR1_REG(base) & CMP_CR1_OPE_MASK) >> CMP_CR1_OPE_SHIFT)
+#define CMP_BRD_CR1_OPE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT))
+
+/*! @brief Set the OPE field to a new value. */
+#define CMP_WR_CR1_OPE(base, value) (CMP_RMW_CR1(base, CMP_CR1_OPE_MASK, CMP_CR1_OPE(value)))
+#define CMP_BWR_CR1_OPE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field COS[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Set the filtered comparator output (CMPO) to equal COUT.
+ * - 0b1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_COS field. */
+#define CMP_RD_CR1_COS(base) ((CMP_CR1_REG(base) & CMP_CR1_COS_MASK) >> CMP_CR1_COS_SHIFT)
+#define CMP_BRD_CR1_COS(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT))
+
+/*! @brief Set the COS field to a new value. */
+#define CMP_WR_CR1_COS(base, value) (CMP_RMW_CR1(base, CMP_CR1_COS_MASK, CMP_CR1_COS(value)))
+#define CMP_BWR_CR1_COS(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field INV[3] (RW)
+ *
+ * Allows selection of the polarity of the analog comparator function. It is
+ * also driven to the COUT output, on both the device pin and as SCR[COUT], when
+ * OPE=0.
+ *
+ * Values:
+ * - 0b0 - Does not invert the comparator output.
+ * - 0b1 - Inverts the comparator output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_INV field. */
+#define CMP_RD_CR1_INV(base) ((CMP_CR1_REG(base) & CMP_CR1_INV_MASK) >> CMP_CR1_INV_SHIFT)
+#define CMP_BRD_CR1_INV(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT))
+
+/*! @brief Set the INV field to a new value. */
+#define CMP_WR_CR1_INV(base, value) (CMP_RMW_CR1(base, CMP_CR1_INV_MASK, CMP_CR1_INV(value)))
+#define CMP_BWR_CR1_INV(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field PMODE[4] (RW)
+ *
+ * See the electrical specifications table in the device Data Sheet for details.
+ *
+ * Values:
+ * - 0b0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
+ *     output propagation delay and lower current consumption.
+ * - 0b1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has
+ *     faster output propagation delay and higher current consumption.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_PMODE field. */
+#define CMP_RD_CR1_PMODE(base) ((CMP_CR1_REG(base) & CMP_CR1_PMODE_MASK) >> CMP_CR1_PMODE_SHIFT)
+#define CMP_BRD_CR1_PMODE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT))
+
+/*! @brief Set the PMODE field to a new value. */
+#define CMP_WR_CR1_PMODE(base, value) (CMP_RMW_CR1(base, CMP_CR1_PMODE_MASK, CMP_CR1_PMODE(value)))
+#define CMP_BWR_CR1_PMODE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field WE[6] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0b0 - Windowing mode is not selected.
+ * - 0b1 - Windowing mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_WE field. */
+#define CMP_RD_CR1_WE(base)  ((CMP_CR1_REG(base) & CMP_CR1_WE_MASK) >> CMP_CR1_WE_SHIFT)
+#define CMP_BRD_CR1_WE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT))
+
+/*! @brief Set the WE field to a new value. */
+#define CMP_WR_CR1_WE(base, value) (CMP_RMW_CR1(base, CMP_CR1_WE_MASK, CMP_CR1_WE(value)))
+#define CMP_BWR_CR1_WE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_CR1, field SE[7] (RW)
+ *
+ * At any given time, either SE or WE can be set. If a write to this register
+ * attempts to set both, then SE is set and WE is cleared. However, avoid writing
+ * 1s to both field locations because this "11" case is reserved and may change in
+ * future implementations.
+ *
+ * Values:
+ * - 0b0 - Sampling mode is not selected.
+ * - 0b1 - Sampling mode is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_CR1_SE field. */
+#define CMP_RD_CR1_SE(base)  ((CMP_CR1_REG(base) & CMP_CR1_SE_MASK) >> CMP_CR1_SE_SHIFT)
+#define CMP_BRD_CR1_SE(base) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT))
+
+/*! @brief Set the SE field to a new value. */
+#define CMP_WR_CR1_SE(base, value) (CMP_RMW_CR1(base, CMP_CR1_SE_MASK, CMP_CR1_SE(value)))
+#define CMP_BWR_CR1_SE(base, value) (BITBAND_ACCESS8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_FPR - CMP Filter Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_FPR - CMP Filter Period Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_FPR register
+ */
+/*@{*/
+#define CMP_RD_FPR(base)         (CMP_FPR_REG(base))
+#define CMP_WR_FPR(base, value)  (CMP_FPR_REG(base) = (value))
+#define CMP_RMW_FPR(base, mask, value) (CMP_WR_FPR(base, (CMP_RD_FPR(base) & ~(mask)) | (value)))
+#define CMP_SET_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) |  (value)))
+#define CMP_CLR_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) & ~(value)))
+#define CMP_TOG_FPR(base, value) (CMP_WR_FPR(base, CMP_RD_FPR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_SCR - CMP Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_SCR - CMP Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_SCR register
+ */
+/*@{*/
+#define CMP_RD_SCR(base)         (CMP_SCR_REG(base))
+#define CMP_WR_SCR(base, value)  (CMP_SCR_REG(base) = (value))
+#define CMP_RMW_SCR(base, mask, value) (CMP_WR_SCR(base, (CMP_RD_SCR(base) & ~(mask)) | (value)))
+#define CMP_SET_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) |  (value)))
+#define CMP_CLR_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) & ~(value)))
+#define CMP_TOG_SCR(base, value) (CMP_WR_SCR(base, CMP_RD_SCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_SCR bitfields
+ */
+
+/*!
+ * @name Register CMP_SCR, field COUT[0] (RO)
+ *
+ * Returns the current value of the Analog Comparator output, when read. The
+ * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
+ * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_COUT field. */
+#define CMP_RD_SCR_COUT(base) ((CMP_SCR_REG(base) & CMP_SCR_COUT_MASK) >> CMP_SCR_COUT_SHIFT)
+#define CMP_BRD_SCR_COUT(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_COUT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFF[1] (W1C)
+ *
+ * Detects a falling-edge on COUT, when set, during normal operation. CFF is
+ * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0b0 - Falling-edge on COUT has not been detected.
+ * - 0b1 - Falling-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFF field. */
+#define CMP_RD_SCR_CFF(base) ((CMP_SCR_REG(base) & CMP_SCR_CFF_MASK) >> CMP_SCR_CFF_SHIFT)
+#define CMP_BRD_SCR_CFF(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT))
+
+/*! @brief Set the CFF field to a new value. */
+#define CMP_WR_SCR_CFF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_CFF(value)))
+#define CMP_BWR_SCR_CFF(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field CFR[2] (W1C)
+ *
+ * Detects a rising-edge on COUT, when set, during normal operation. CFR is
+ * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
+ * sensitive .
+ *
+ * Values:
+ * - 0b0 - Rising-edge on COUT has not been detected.
+ * - 0b1 - Rising-edge on COUT has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_CFR field. */
+#define CMP_RD_SCR_CFR(base) ((CMP_SCR_REG(base) & CMP_SCR_CFR_MASK) >> CMP_SCR_CFR_SHIFT)
+#define CMP_BRD_SCR_CFR(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT))
+
+/*! @brief Set the CFR field to a new value. */
+#define CMP_WR_SCR_CFR(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK), CMP_SCR_CFR(value)))
+#define CMP_BWR_SCR_CFR(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IEF[3] (RW)
+ *
+ * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFF is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled.
+ * - 0b1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IEF field. */
+#define CMP_RD_SCR_IEF(base) ((CMP_SCR_REG(base) & CMP_SCR_IEF_MASK) >> CMP_SCR_IEF_SHIFT)
+#define CMP_BRD_SCR_IEF(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT))
+
+/*! @brief Set the IEF field to a new value. */
+#define CMP_WR_SCR_IEF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IEF_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IEF(value)))
+#define CMP_BWR_SCR_IEF(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field IER[4] (RW)
+ *
+ * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
+ * will be asserted when CFR is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled.
+ * - 0b1 - Interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_IER field. */
+#define CMP_RD_SCR_IER(base) ((CMP_SCR_REG(base) & CMP_SCR_IER_MASK) >> CMP_SCR_IER_SHIFT)
+#define CMP_BRD_SCR_IER(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT))
+
+/*! @brief Set the IER field to a new value. */
+#define CMP_WR_SCR_IER(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IER_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IER(value)))
+#define CMP_BWR_SCR_IER(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_SCR, field DMAEN[6] (RW)
+ *
+ * Enables the DMA transfer triggered from the CMP module. When this field is
+ * set, a DMA request is asserted when CFR or CFF is set.
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_SCR_DMAEN field. */
+#define CMP_RD_SCR_DMAEN(base) ((CMP_SCR_REG(base) & CMP_SCR_DMAEN_MASK) >> CMP_SCR_DMAEN_SHIFT)
+#define CMP_BRD_SCR_DMAEN(base) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define CMP_WR_SCR_DMAEN(base, value) (CMP_RMW_SCR(base, (CMP_SCR_DMAEN_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_DMAEN(value)))
+#define CMP_BWR_SCR_DMAEN(base, value) (BITBAND_ACCESS8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_DACCR - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_DACCR - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_DACCR register
+ */
+/*@{*/
+#define CMP_RD_DACCR(base)       (CMP_DACCR_REG(base))
+#define CMP_WR_DACCR(base, value) (CMP_DACCR_REG(base) = (value))
+#define CMP_RMW_DACCR(base, mask, value) (CMP_WR_DACCR(base, (CMP_RD_DACCR(base) & ~(mask)) | (value)))
+#define CMP_SET_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) |  (value)))
+#define CMP_CLR_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) & ~(value)))
+#define CMP_TOG_DACCR(base, value) (CMP_WR_DACCR(base, CMP_RD_DACCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_DACCR bitfields
+ */
+
+/*!
+ * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
+ *
+ * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
+ * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VOSEL field. */
+#define CMP_RD_DACCR_VOSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VOSEL_MASK) >> CMP_DACCR_VOSEL_SHIFT)
+#define CMP_BRD_DACCR_VOSEL(base) (CMP_RD_DACCR_VOSEL(base))
+
+/*! @brief Set the VOSEL field to a new value. */
+#define CMP_WR_DACCR_VOSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VOSEL_MASK, CMP_DACCR_VOSEL(value)))
+#define CMP_BWR_DACCR_VOSEL(base, value) (CMP_WR_DACCR_VOSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field VRSEL[6] (RW)
+ *
+ * Values:
+ * - 0b0 - V is selected as resistor ladder network supply reference V. in1 in
+ * - 0b1 - V is selected as resistor ladder network supply reference V. in2 in
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_VRSEL field. */
+#define CMP_RD_DACCR_VRSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VRSEL_MASK) >> CMP_DACCR_VRSEL_SHIFT)
+#define CMP_BRD_DACCR_VRSEL(base) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT))
+
+/*! @brief Set the VRSEL field to a new value. */
+#define CMP_WR_DACCR_VRSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VRSEL_MASK, CMP_DACCR_VRSEL(value)))
+#define CMP_BWR_DACCR_VRSEL(base, value) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMP_DACCR, field DACEN[7] (RW)
+ *
+ * Enables the DAC. When the DAC is disabled, it is powered down to conserve
+ * power.
+ *
+ * Values:
+ * - 0b0 - DAC is disabled.
+ * - 0b1 - DAC is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_DACCR_DACEN field. */
+#define CMP_RD_DACCR_DACEN(base) ((CMP_DACCR_REG(base) & CMP_DACCR_DACEN_MASK) >> CMP_DACCR_DACEN_SHIFT)
+#define CMP_BRD_DACCR_DACEN(base) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT))
+
+/*! @brief Set the DACEN field to a new value. */
+#define CMP_WR_DACCR_DACEN(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_DACEN_MASK, CMP_DACCR_DACEN(value)))
+#define CMP_BWR_DACCR_DACEN(base, value) (BITBAND_ACCESS8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMP_MUXCR - MUX Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMP_MUXCR - MUX Control Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CMP_MUXCR register
+ */
+/*@{*/
+#define CMP_RD_MUXCR(base)       (CMP_MUXCR_REG(base))
+#define CMP_WR_MUXCR(base, value) (CMP_MUXCR_REG(base) = (value))
+#define CMP_RMW_MUXCR(base, mask, value) (CMP_WR_MUXCR(base, (CMP_RD_MUXCR(base) & ~(mask)) | (value)))
+#define CMP_SET_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) |  (value)))
+#define CMP_CLR_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) & ~(value)))
+#define CMP_TOG_MUXCR(base, value) (CMP_WR_MUXCR(base, CMP_RD_MUXCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMP_MUXCR bitfields
+ */
+
+/*!
+ * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
+ *
+ * Determines which input is selected for the minus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 0b000 - IN0
+ * - 0b001 - IN1
+ * - 0b010 - IN2
+ * - 0b011 - IN3
+ * - 0b100 - IN4
+ * - 0b101 - IN5
+ * - 0b110 - IN6
+ * - 0b111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_MSEL field. */
+#define CMP_RD_MUXCR_MSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_MSEL_MASK) >> CMP_MUXCR_MSEL_SHIFT)
+#define CMP_BRD_MUXCR_MSEL(base) (CMP_RD_MUXCR_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define CMP_WR_MUXCR_MSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_MSEL_MASK, CMP_MUXCR_MSEL(value)))
+#define CMP_BWR_MUXCR_MSEL(base, value) (CMP_WR_MUXCR_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
+ *
+ * Determines which input is selected for the plus input of the comparator. For
+ * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
+ * operation selects the same input for both muxes, the comparator automatically
+ * shuts down to prevent itself from becoming a noise generator.
+ *
+ * Values:
+ * - 0b000 - IN0
+ * - 0b001 - IN1
+ * - 0b010 - IN2
+ * - 0b011 - IN3
+ * - 0b100 - IN4
+ * - 0b101 - IN5
+ * - 0b110 - IN6
+ * - 0b111 - IN7
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSEL field. */
+#define CMP_RD_MUXCR_PSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSEL_MASK) >> CMP_MUXCR_PSEL_SHIFT)
+#define CMP_BRD_MUXCR_PSEL(base) (CMP_RD_MUXCR_PSEL(base))
+
+/*! @brief Set the PSEL field to a new value. */
+#define CMP_WR_MUXCR_PSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSEL_MASK, CMP_MUXCR_PSEL(value)))
+#define CMP_BWR_MUXCR_PSEL(base, value) (CMP_WR_MUXCR_PSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMP_MUXCR, field PSTM[7] (RW)
+ *
+ * This bit is used to enable to MUX pass through mode. Pass through mode is
+ * always available but for some devices this feature must be always disabled due to
+ * the lack of package pins.
+ *
+ * Values:
+ * - 0b0 - Pass Through Mode is disabled.
+ * - 0b1 - Pass Through Mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMP_MUXCR_PSTM field. */
+#define CMP_RD_MUXCR_PSTM(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSTM_MASK) >> CMP_MUXCR_PSTM_SHIFT)
+#define CMP_BRD_MUXCR_PSTM(base) (BITBAND_ACCESS8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT))
+
+/*! @brief Set the PSTM field to a new value. */
+#define CMP_WR_MUXCR_PSTM(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSTM_MASK, CMP_MUXCR_PSTM(value)))
+#define CMP_BWR_MUXCR_PSTM(base, value) (BITBAND_ACCESS8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CMT
+ *
+ * Carrier Modulator Transmitter
+ *
+ * Registers defined in this header file:
+ * - CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ * - CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ * - CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ * - CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ * - CMT_OC - CMT Output Control Register
+ * - CMT_MSC - CMT Modulator Status and Control Register
+ * - CMT_CMD1 - CMT Modulator Data Register Mark High
+ * - CMT_CMD2 - CMT Modulator Data Register Mark Low
+ * - CMT_CMD3 - CMT Modulator Data Register Space High
+ * - CMT_CMD4 - CMT Modulator Data Register Space Low
+ * - CMT_PPS - CMT Primary Prescaler Register
+ * - CMT_DMA - CMT Direct Memory Access Register
+ */
+
+#define CMT_INSTANCE_COUNT (1U) /*!< Number of instances of the CMT module. */
+#define CMT_IDX (0U) /*!< Instance number for CMT. */
+
+/*******************************************************************************
+ * CMT_CGH1 - CMT Carrier Generator High Data Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary high value for generating the carrier
+ * output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGH1 register
+ */
+/*@{*/
+#define CMT_RD_CGH1(base)        (CMT_CGH1_REG(base))
+#define CMT_WR_CGH1(base, value) (CMT_CGH1_REG(base) = (value))
+#define CMT_RMW_CGH1(base, mask, value) (CMT_WR_CGH1(base, (CMT_RD_CGH1(base) & ~(mask)) | (value)))
+#define CMT_SET_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) |  (value)))
+#define CMT_CLR_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) & ~(value)))
+#define CMT_TOG_CGH1(base, value) (CMT_WR_CGH1(base, CMT_RD_CGH1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGL1 - CMT Carrier Generator Low Data Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the primary low value for generating the carrier
+ * output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGL1 register
+ */
+/*@{*/
+#define CMT_RD_CGL1(base)        (CMT_CGL1_REG(base))
+#define CMT_WR_CGL1(base, value) (CMT_CGL1_REG(base) = (value))
+#define CMT_RMW_CGL1(base, mask, value) (CMT_WR_CGL1(base, (CMT_RD_CGL1(base) & ~(mask)) | (value)))
+#define CMT_SET_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) |  (value)))
+#define CMT_CLR_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) & ~(value)))
+#define CMT_TOG_CGL1(base, value) (CMT_WR_CGL1(base, CMT_RD_CGL1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGH2 - CMT Carrier Generator High Data Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary high value for generating the
+ * carrier output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGH2 register
+ */
+/*@{*/
+#define CMT_RD_CGH2(base)        (CMT_CGH2_REG(base))
+#define CMT_WR_CGH2(base, value) (CMT_CGH2_REG(base) = (value))
+#define CMT_RMW_CGH2(base, mask, value) (CMT_WR_CGH2(base, (CMT_RD_CGH2(base) & ~(mask)) | (value)))
+#define CMT_SET_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) |  (value)))
+#define CMT_CLR_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) & ~(value)))
+#define CMT_TOG_CGH2(base, value) (CMT_WR_CGH2(base, CMT_RD_CGH2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CGL2 - CMT Carrier Generator Low Data Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This data register contains the secondary low value for generating the
+ * carrier output.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CGL2 register
+ */
+/*@{*/
+#define CMT_RD_CGL2(base)        (CMT_CGL2_REG(base))
+#define CMT_WR_CGL2(base, value) (CMT_CGL2_REG(base) = (value))
+#define CMT_RMW_CGL2(base, mask, value) (CMT_WR_CGL2(base, (CMT_RD_CGL2(base) & ~(mask)) | (value)))
+#define CMT_SET_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) |  (value)))
+#define CMT_CLR_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) & ~(value)))
+#define CMT_TOG_CGL2(base, value) (CMT_WR_CGL2(base, CMT_RD_CGL2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_OC - CMT Output Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_OC - CMT Output Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to control the IRO signal of the CMT module.
+ */
+/*!
+ * @name Constants and macros for entire CMT_OC register
+ */
+/*@{*/
+#define CMT_RD_OC(base)          (CMT_OC_REG(base))
+#define CMT_WR_OC(base, value)   (CMT_OC_REG(base) = (value))
+#define CMT_RMW_OC(base, mask, value) (CMT_WR_OC(base, (CMT_RD_OC(base) & ~(mask)) | (value)))
+#define CMT_SET_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) |  (value)))
+#define CMT_CLR_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) & ~(value)))
+#define CMT_TOG_OC(base, value)  (CMT_WR_OC(base, CMT_RD_OC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_OC bitfields
+ */
+
+/*!
+ * @name Register CMT_OC, field IROPEN[5] (RW)
+ *
+ * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
+ * output that drives out either the CMT transmitter output or the state of IROL
+ * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
+ * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
+ * signal is disabled, it is in a high-impedance state and is unable to draw any
+ * current. This signal is disabled during reset.
+ *
+ * Values:
+ * - 0b0 - The IRO signal is disabled.
+ * - 0b1 - The IRO signal is enabled as output.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_IROPEN field. */
+#define CMT_RD_OC_IROPEN(base) ((CMT_OC_REG(base) & CMT_OC_IROPEN_MASK) >> CMT_OC_IROPEN_SHIFT)
+#define CMT_BRD_OC_IROPEN(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT))
+
+/*! @brief Set the IROPEN field to a new value. */
+#define CMT_WR_OC_IROPEN(base, value) (CMT_RMW_OC(base, CMT_OC_IROPEN_MASK, CMT_OC_IROPEN(value)))
+#define CMT_BWR_OC_IROPEN(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_OC, field CMTPOL[6] (RW)
+ *
+ * Controls the polarity of the IRO signal.
+ *
+ * Values:
+ * - 0b0 - The IRO signal is active-low.
+ * - 0b1 - The IRO signal is active-high.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_CMTPOL field. */
+#define CMT_RD_OC_CMTPOL(base) ((CMT_OC_REG(base) & CMT_OC_CMTPOL_MASK) >> CMT_OC_CMTPOL_SHIFT)
+#define CMT_BRD_OC_CMTPOL(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT))
+
+/*! @brief Set the CMTPOL field to a new value. */
+#define CMT_WR_OC_CMTPOL(base, value) (CMT_RMW_OC(base, CMT_OC_CMTPOL_MASK, CMT_OC_CMTPOL(value)))
+#define CMT_BWR_OC_CMTPOL(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_OC, field IROL[7] (RW)
+ *
+ * Reads the state of the IRO latch. Writing to IROL changes the state of the
+ * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_OC_IROL field. */
+#define CMT_RD_OC_IROL(base) ((CMT_OC_REG(base) & CMT_OC_IROL_MASK) >> CMT_OC_IROL_SHIFT)
+#define CMT_BRD_OC_IROL(base) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT))
+
+/*! @brief Set the IROL field to a new value. */
+#define CMT_WR_OC_IROL(base, value) (CMT_RMW_OC(base, CMT_OC_IROL_MASK, CMT_OC_IROL(value)))
+#define CMT_BWR_OC_IROL(base, value) (BITBAND_ACCESS8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_MSC - CMT Modulator Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_MSC - CMT Modulator Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the modulator and carrier generator enable (MCGEN),
+ * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
+ * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
+ * (EOCF) status bit.
+ */
+/*!
+ * @name Constants and macros for entire CMT_MSC register
+ */
+/*@{*/
+#define CMT_RD_MSC(base)         (CMT_MSC_REG(base))
+#define CMT_WR_MSC(base, value)  (CMT_MSC_REG(base) = (value))
+#define CMT_RMW_MSC(base, mask, value) (CMT_WR_MSC(base, (CMT_RD_MSC(base) & ~(mask)) | (value)))
+#define CMT_SET_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) |  (value)))
+#define CMT_CLR_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) & ~(value)))
+#define CMT_TOG_MSC(base, value) (CMT_WR_MSC(base, CMT_RD_MSC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_MSC bitfields
+ */
+
+/*!
+ * @name Register CMT_MSC, field MCGEN[0] (RW)
+ *
+ * Setting MCGEN will initialize the carrier generator and modulator and will
+ * enable all clocks. When enabled, the carrier generator and modulator will
+ * function continuously. When MCGEN is cleared, the current modulator cycle will be
+ * allowed to expire before all carrier and modulator clocks are disabled to save
+ * power and the modulator output is forced low. To prevent spurious operation,
+ * the user should initialize all data and control registers before enabling the
+ * system.
+ *
+ * Values:
+ * - 0b0 - Modulator and carrier generator disabled
+ * - 0b1 - Modulator and carrier generator enabled
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_MCGEN field. */
+#define CMT_RD_MSC_MCGEN(base) ((CMT_MSC_REG(base) & CMT_MSC_MCGEN_MASK) >> CMT_MSC_MCGEN_SHIFT)
+#define CMT_BRD_MSC_MCGEN(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT))
+
+/*! @brief Set the MCGEN field to a new value. */
+#define CMT_WR_MSC_MCGEN(base, value) (CMT_RMW_MSC(base, CMT_MSC_MCGEN_MASK, CMT_MSC_MCGEN(value)))
+#define CMT_BWR_MSC_MCGEN(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EOCIE[1] (RW)
+ *
+ * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
+ *
+ * Values:
+ * - 0b0 - CPU interrupt is disabled.
+ * - 0b1 - CPU interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EOCIE field. */
+#define CMT_RD_MSC_EOCIE(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCIE_MASK) >> CMT_MSC_EOCIE_SHIFT)
+#define CMT_BRD_MSC_EOCIE(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT))
+
+/*! @brief Set the EOCIE field to a new value. */
+#define CMT_WR_MSC_EOCIE(base, value) (CMT_RMW_MSC(base, CMT_MSC_EOCIE_MASK, CMT_MSC_EOCIE(value)))
+#define CMT_BWR_MSC_EOCIE(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field FSK[2] (RW)
+ *
+ * Enables FSK operation.
+ *
+ * Values:
+ * - 0b0 - The CMT operates in Time or Baseband mode.
+ * - 0b1 - The CMT operates in FSK mode.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_FSK field. */
+#define CMT_RD_MSC_FSK(base) ((CMT_MSC_REG(base) & CMT_MSC_FSK_MASK) >> CMT_MSC_FSK_SHIFT)
+#define CMT_BRD_MSC_FSK(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT))
+
+/*! @brief Set the FSK field to a new value. */
+#define CMT_WR_MSC_FSK(base, value) (CMT_RMW_MSC(base, CMT_MSC_FSK_MASK, CMT_MSC_FSK(value)))
+#define CMT_BWR_MSC_FSK(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field BASE[3] (RW)
+ *
+ * When set, BASE disables the carrier generator and forces the carrier output
+ * high for generation of baseband protocols. When BASE is cleared, the carrier
+ * generator is enabled and the carrier output toggles at the frequency determined
+ * by values stored in the carrier data registers. This field is cleared by
+ * reset. This field is not double-buffered and must not be written to during a
+ * transmission.
+ *
+ * Values:
+ * - 0b0 - Baseband mode is disabled.
+ * - 0b1 - Baseband mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_BASE field. */
+#define CMT_RD_MSC_BASE(base) ((CMT_MSC_REG(base) & CMT_MSC_BASE_MASK) >> CMT_MSC_BASE_SHIFT)
+#define CMT_BRD_MSC_BASE(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT))
+
+/*! @brief Set the BASE field to a new value. */
+#define CMT_WR_MSC_BASE(base, value) (CMT_RMW_MSC(base, CMT_MSC_BASE_MASK, CMT_MSC_BASE(value)))
+#define CMT_BWR_MSC_BASE(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EXSPC[4] (RW)
+ *
+ * Enables the extended space operation.
+ *
+ * Values:
+ * - 0b0 - Extended space is disabled.
+ * - 0b1 - Extended space is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EXSPC field. */
+#define CMT_RD_MSC_EXSPC(base) ((CMT_MSC_REG(base) & CMT_MSC_EXSPC_MASK) >> CMT_MSC_EXSPC_SHIFT)
+#define CMT_BRD_MSC_EXSPC(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT))
+
+/*! @brief Set the EXSPC field to a new value. */
+#define CMT_WR_MSC_EXSPC(base, value) (CMT_RMW_MSC(base, CMT_MSC_EXSPC_MASK, CMT_MSC_EXSPC(value)))
+#define CMT_BWR_MSC_EXSPC(base, value) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
+ *
+ * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
+ * divided by 2 ,4, or 8 . This field must not be changed during a transmission
+ * because it is not double-buffered.
+ *
+ * Values:
+ * - 0b00 - IF * 1
+ * - 0b01 - IF * 2
+ * - 0b10 - IF * 4
+ * - 0b11 - IF * 8
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_CMTDIV field. */
+#define CMT_RD_MSC_CMTDIV(base) ((CMT_MSC_REG(base) & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT)
+#define CMT_BRD_MSC_CMTDIV(base) (CMT_RD_MSC_CMTDIV(base))
+
+/*! @brief Set the CMTDIV field to a new value. */
+#define CMT_WR_MSC_CMTDIV(base, value) (CMT_RMW_MSC(base, CMT_MSC_CMTDIV_MASK, CMT_MSC_CMTDIV(value)))
+#define CMT_BWR_MSC_CMTDIV(base, value) (CMT_WR_MSC_CMTDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register CMT_MSC, field EOCF[7] (RO)
+ *
+ * Sets when: The modulator is not currently active and MCGEN is set to begin
+ * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
+ * set. This is recognized when a match occurs between the contents of the space
+ * period register and the down counter. At this time, the counter is
+ * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
+ * the space period register is loaded with, possibly new contents of the space
+ * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
+ * access of CMD2 or CMD4, or by the DMA transfer.
+ *
+ * Values:
+ * - 0b0 - End of modulation cycle has not occured since the flag last cleared.
+ * - 0b1 - End of modulator cycle has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_MSC_EOCF field. */
+#define CMT_RD_MSC_EOCF(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCF_MASK) >> CMT_MSC_EOCF_SHIFT)
+#define CMT_BRD_MSC_EOCF(base) (BITBAND_ACCESS8(&CMT_MSC_REG(base), CMT_MSC_EOCF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD1 - CMT Modulator Data Register Mark High
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD1 register
+ */
+/*@{*/
+#define CMT_RD_CMD1(base)        (CMT_CMD1_REG(base))
+#define CMT_WR_CMD1(base, value) (CMT_CMD1_REG(base) = (value))
+#define CMT_RMW_CMD1(base, mask, value) (CMT_WR_CMD1(base, (CMT_RD_CMD1(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) |  (value)))
+#define CMT_CLR_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) & ~(value)))
+#define CMT_TOG_CMD1(base, value) (CMT_WR_CMD1(base, CMT_RD_CMD1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD2 - CMT Modulator Data Register Mark Low
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the modulator down counter
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD2 register
+ */
+/*@{*/
+#define CMT_RD_CMD2(base)        (CMT_CMD2_REG(base))
+#define CMT_WR_CMD2(base, value) (CMT_CMD2_REG(base) = (value))
+#define CMT_RMW_CMD2(base, mask, value) (CMT_WR_CMD2(base, (CMT_RD_CMD2(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) |  (value)))
+#define CMT_CLR_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) & ~(value)))
+#define CMT_TOG_CMD2(base, value) (CMT_WR_CMD2(base, CMT_RD_CMD2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD3 - CMT Modulator Data Register Space High
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD3 - CMT Modulator Data Register Space High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD3 register
+ */
+/*@{*/
+#define CMT_RD_CMD3(base)        (CMT_CMD3_REG(base))
+#define CMT_WR_CMD3(base, value) (CMT_CMD3_REG(base) = (value))
+#define CMT_RMW_CMD3(base, mask, value) (CMT_WR_CMD3(base, (CMT_RD_CMD3(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) |  (value)))
+#define CMT_CLR_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) & ~(value)))
+#define CMT_TOG_CMD3(base, value) (CMT_WR_CMD3(base, CMT_RD_CMD3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_CMD4 - CMT Modulator Data Register Space Low
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The contents of this register are transferred to the space period register
+ * upon the completion of a modulation period.
+ */
+/*!
+ * @name Constants and macros for entire CMT_CMD4 register
+ */
+/*@{*/
+#define CMT_RD_CMD4(base)        (CMT_CMD4_REG(base))
+#define CMT_WR_CMD4(base, value) (CMT_CMD4_REG(base) = (value))
+#define CMT_RMW_CMD4(base, mask, value) (CMT_WR_CMD4(base, (CMT_RD_CMD4(base) & ~(mask)) | (value)))
+#define CMT_SET_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) |  (value)))
+#define CMT_CLR_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) & ~(value)))
+#define CMT_TOG_CMD4(base, value) (CMT_WR_CMD4(base, CMT_RD_CMD4(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_PPS - CMT Primary Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_PPS - CMT Primary Prescaler Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to set the Primary Prescaler Divider field (PPSDIV).
+ */
+/*!
+ * @name Constants and macros for entire CMT_PPS register
+ */
+/*@{*/
+#define CMT_RD_PPS(base)         (CMT_PPS_REG(base))
+#define CMT_WR_PPS(base, value)  (CMT_PPS_REG(base) = (value))
+#define CMT_RMW_PPS(base, mask, value) (CMT_WR_PPS(base, (CMT_RD_PPS(base) & ~(mask)) | (value)))
+#define CMT_SET_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) |  (value)))
+#define CMT_CLR_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) & ~(value)))
+#define CMT_TOG_PPS(base, value) (CMT_WR_PPS(base, CMT_RD_PPS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_PPS bitfields
+ */
+
+/*!
+ * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
+ *
+ * Divides the CMT clock to generate the Intermediate Frequency clock enable to
+ * the secondary prescaler.
+ *
+ * Values:
+ * - 0b0000 - Bus clock * 1
+ * - 0b0001 - Bus clock * 2
+ * - 0b0010 - Bus clock * 3
+ * - 0b0011 - Bus clock * 4
+ * - 0b0100 - Bus clock * 5
+ * - 0b0101 - Bus clock * 6
+ * - 0b0110 - Bus clock * 7
+ * - 0b0111 - Bus clock * 8
+ * - 0b1000 - Bus clock * 9
+ * - 0b1001 - Bus clock * 10
+ * - 0b1010 - Bus clock * 11
+ * - 0b1011 - Bus clock * 12
+ * - 0b1100 - Bus clock * 13
+ * - 0b1101 - Bus clock * 14
+ * - 0b1110 - Bus clock * 15
+ * - 0b1111 - Bus clock * 16
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_PPS_PPSDIV field. */
+#define CMT_RD_PPS_PPSDIV(base) ((CMT_PPS_REG(base) & CMT_PPS_PPSDIV_MASK) >> CMT_PPS_PPSDIV_SHIFT)
+#define CMT_BRD_PPS_PPSDIV(base) (CMT_RD_PPS_PPSDIV(base))
+
+/*! @brief Set the PPSDIV field to a new value. */
+#define CMT_WR_PPS_PPSDIV(base, value) (CMT_RMW_PPS(base, CMT_PPS_PPSDIV_MASK, CMT_PPS_PPSDIV(value)))
+#define CMT_BWR_PPS_PPSDIV(base, value) (CMT_WR_PPS_PPSDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CMT_DMA - CMT Direct Memory Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief CMT_DMA - CMT Direct Memory Access Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is used to enable/disable direct memory access (DMA).
+ */
+/*!
+ * @name Constants and macros for entire CMT_DMA register
+ */
+/*@{*/
+#define CMT_RD_DMA(base)         (CMT_DMA_REG(base))
+#define CMT_WR_DMA(base, value)  (CMT_DMA_REG(base) = (value))
+#define CMT_RMW_DMA(base, mask, value) (CMT_WR_DMA(base, (CMT_RD_DMA(base) & ~(mask)) | (value)))
+#define CMT_SET_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) |  (value)))
+#define CMT_CLR_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) & ~(value)))
+#define CMT_TOG_DMA(base, value) (CMT_WR_DMA(base, CMT_RD_DMA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CMT_DMA bitfields
+ */
+
+/*!
+ * @name Register CMT_DMA, field DMA[0] (RW)
+ *
+ * Enables the DMA protocol.
+ *
+ * Values:
+ * - 0b0 - DMA transfer request and done are disabled.
+ * - 0b1 - DMA transfer request and done are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the CMT_DMA_DMA field. */
+#define CMT_RD_DMA_DMA(base) ((CMT_DMA_REG(base) & CMT_DMA_DMA_MASK) >> CMT_DMA_DMA_SHIFT)
+#define CMT_BRD_DMA_DMA(base) (BITBAND_ACCESS8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define CMT_WR_DMA_DMA(base, value) (CMT_RMW_DMA(base, CMT_DMA_DMA_MASK, CMT_DMA_DMA(value)))
+#define CMT_BWR_DMA_DMA(base, value) (BITBAND_ACCESS8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 CRC
+ *
+ * Cyclic Redundancy Check
+ *
+ * Registers defined in this header file:
+ * - CRC_DATAL - CRC_DATAL register.
+ * - CRC_DATAH - CRC_DATAH register.
+ * - CRC_DATALL - CRC_DATALL register.
+ * - CRC_DATALU - CRC_DATALU register.
+ * - CRC_DATAHL - CRC_DATAHL register.
+ * - CRC_DATAHU - CRC_DATAHU register.
+ * - CRC_DATA - CRC Data register
+ * - CRC_GPOLY - CRC Polynomial register
+ * - CRC_GPOLYL - CRC_GPOLYL register.
+ * - CRC_GPOLYH - CRC_GPOLYH register.
+ * - CRC_GPOLYLL - CRC_GPOLYLL register.
+ * - CRC_GPOLYLU - CRC_GPOLYLU register.
+ * - CRC_GPOLYHL - CRC_GPOLYHL register.
+ * - CRC_GPOLYHU - CRC_GPOLYHU register.
+ * - CRC_CTRL - CRC Control register
+ * - CRC_CTRLHU - CRC_CTRLHU register.
+ */
+
+#define CRC_INSTANCE_COUNT (1U) /*!< Number of instances of the CRC module. */
+#define CRC_IDX (0U) /*!< Instance number for CRC. */
+
+/*******************************************************************************
+ * CRC_DATALL - CRC_DATALL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATALL - CRC_DATALL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATALL register
+ */
+/*@{*/
+#define CRC_RD_DATALL(base)      (CRC_DATALL_REG(base))
+#define CRC_WR_DATALL(base, value) (CRC_DATALL_REG(base) = (value))
+#define CRC_RMW_DATALL(base, mask, value) (CRC_WR_DATALL(base, (CRC_RD_DATALL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) |  (value)))
+#define CRC_CLR_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) & ~(value)))
+#define CRC_TOG_DATALL(base, value) (CRC_WR_DATALL(base, CRC_RD_DATALL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAL - CRC_DATAL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAL - CRC_DATAL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAL register
+ */
+/*@{*/
+#define CRC_RD_DATAL(base)       (CRC_DATAL_REG(base))
+#define CRC_WR_DATAL(base, value) (CRC_DATAL_REG(base) = (value))
+#define CRC_RMW_DATAL(base, mask, value) (CRC_WR_DATAL(base, (CRC_RD_DATAL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) |  (value)))
+#define CRC_CLR_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) & ~(value)))
+#define CRC_TOG_DATAL(base, value) (CRC_WR_DATAL(base, CRC_RD_DATAL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATA - CRC Data register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATA - CRC Data register (RW)
+ *
+ * Reset value: 0xFFFFFFFFU
+ *
+ * The CRC Data register contains the value of the seed, data, and checksum.
+ * When CTRL[WAS] is set, any write to the data register is regarded as the seed
+ * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
+ * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
+ * not used for programming the seed value, and reads of these fields return an
+ * indeterminate value. In 32-bit CRC mode, all fields are used for programming
+ * the seed value. When programming data values, the values can be written 8 bits,
+ * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
+ * data value written first. After all data values are written, the CRC result
+ * can be read from this data register. In 16-bit CRC mode, the CRC result is
+ * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
+ * result. Reads of this register at any time return the intermediate CRC value,
+ * provided the CRC module is configured.
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATA register
+ */
+/*@{*/
+#define CRC_RD_DATA(base)        (CRC_DATA_REG(base))
+#define CRC_WR_DATA(base, value) (CRC_DATA_REG(base) = (value))
+#define CRC_RMW_DATA(base, mask, value) (CRC_WR_DATA(base, (CRC_RD_DATA(base) & ~(mask)) | (value)))
+#define CRC_SET_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) |  (value)))
+#define CRC_CLR_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) & ~(value)))
+#define CRC_TOG_DATA(base, value) (CRC_WR_DATA(base, CRC_RD_DATA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_DATA bitfields
+ */
+
+/*!
+ * @name Register CRC_DATA, field LL[7:0] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_LL field. */
+#define CRC_RD_DATA_LL(base) ((CRC_DATA_REG(base) & CRC_DATA_LL_MASK) >> CRC_DATA_LL_SHIFT)
+#define CRC_BRD_DATA_LL(base) (CRC_RD_DATA_LL(base))
+
+/*! @brief Set the LL field to a new value. */
+#define CRC_WR_DATA_LL(base, value) (CRC_RMW_DATA(base, CRC_DATA_LL_MASK, CRC_DATA_LL(value)))
+#define CRC_BWR_DATA_LL(base, value) (CRC_WR_DATA_LL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field LU[15:8] (RW)
+ *
+ * When CTRL[WAS] is 1, values written to this field are part of the seed value.
+ * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
+ * generation.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_LU field. */
+#define CRC_RD_DATA_LU(base) ((CRC_DATA_REG(base) & CRC_DATA_LU_MASK) >> CRC_DATA_LU_SHIFT)
+#define CRC_BRD_DATA_LU(base) (CRC_RD_DATA_LU(base))
+
+/*! @brief Set the LU field to a new value. */
+#define CRC_WR_DATA_LU(base, value) (CRC_RMW_DATA(base, CRC_DATA_LU_MASK, CRC_DATA_LU(value)))
+#define CRC_BWR_DATA_LU(base, value) (CRC_WR_DATA_LU(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field HL[23:16] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_HL field. */
+#define CRC_RD_DATA_HL(base) ((CRC_DATA_REG(base) & CRC_DATA_HL_MASK) >> CRC_DATA_HL_SHIFT)
+#define CRC_BRD_DATA_HL(base) (CRC_RD_DATA_HL(base))
+
+/*! @brief Set the HL field to a new value. */
+#define CRC_WR_DATA_HL(base, value) (CRC_RMW_DATA(base, CRC_DATA_HL_MASK, CRC_DATA_HL(value)))
+#define CRC_BWR_DATA_HL(base, value) (CRC_WR_DATA_HL(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_DATA, field HU[31:24] (RW)
+ *
+ * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
+ * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
+ * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
+ * written to this field is used for CRC checksum generation in both 16-bit and
+ * 32-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_DATA_HU field. */
+#define CRC_RD_DATA_HU(base) ((CRC_DATA_REG(base) & CRC_DATA_HU_MASK) >> CRC_DATA_HU_SHIFT)
+#define CRC_BRD_DATA_HU(base) (CRC_RD_DATA_HU(base))
+
+/*! @brief Set the HU field to a new value. */
+#define CRC_WR_DATA_HU(base, value) (CRC_RMW_DATA(base, CRC_DATA_HU_MASK, CRC_DATA_HU(value)))
+#define CRC_BWR_DATA_HU(base, value) (CRC_WR_DATA_HU(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATALU - CRC_DATALU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATALU - CRC_DATALU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATALU register
+ */
+/*@{*/
+#define CRC_RD_DATALU(base)      (CRC_DATALU_REG(base))
+#define CRC_WR_DATALU(base, value) (CRC_DATALU_REG(base) = (value))
+#define CRC_RMW_DATALU(base, mask, value) (CRC_WR_DATALU(base, (CRC_RD_DATALU(base) & ~(mask)) | (value)))
+#define CRC_SET_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) |  (value)))
+#define CRC_CLR_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) & ~(value)))
+#define CRC_TOG_DATALU(base, value) (CRC_WR_DATALU(base, CRC_RD_DATALU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAHL - CRC_DATAHL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAHL - CRC_DATAHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAHL register
+ */
+/*@{*/
+#define CRC_RD_DATAHL(base)      (CRC_DATAHL_REG(base))
+#define CRC_WR_DATAHL(base, value) (CRC_DATAHL_REG(base) = (value))
+#define CRC_RMW_DATAHL(base, mask, value) (CRC_WR_DATAHL(base, (CRC_RD_DATAHL(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) |  (value)))
+#define CRC_CLR_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) & ~(value)))
+#define CRC_TOG_DATAHL(base, value) (CRC_WR_DATAHL(base, CRC_RD_DATAHL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAH - CRC_DATAH register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAH - CRC_DATAH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAH register
+ */
+/*@{*/
+#define CRC_RD_DATAH(base)       (CRC_DATAH_REG(base))
+#define CRC_WR_DATAH(base, value) (CRC_DATAH_REG(base) = (value))
+#define CRC_RMW_DATAH(base, mask, value) (CRC_WR_DATAH(base, (CRC_RD_DATAH(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) |  (value)))
+#define CRC_CLR_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) & ~(value)))
+#define CRC_TOG_DATAH(base, value) (CRC_WR_DATAH(base, CRC_RD_DATAH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_DATAHU - CRC_DATAHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_DATAHU - CRC_DATAHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_DATAHU register
+ */
+/*@{*/
+#define CRC_RD_DATAHU(base)      (CRC_DATAHU_REG(base))
+#define CRC_WR_DATAHU(base, value) (CRC_DATAHU_REG(base) = (value))
+#define CRC_RMW_DATAHU(base, mask, value) (CRC_WR_DATAHU(base, (CRC_RD_DATAHU(base) & ~(mask)) | (value)))
+#define CRC_SET_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) |  (value)))
+#define CRC_CLR_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) & ~(value)))
+#define CRC_TOG_DATAHU(base, value) (CRC_WR_DATAHU(base, CRC_RD_DATAHU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYLL - CRC_GPOLYLL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYLL(base)     (CRC_GPOLYLL_REG(base))
+#define CRC_WR_GPOLYLL(base, value) (CRC_GPOLYLL_REG(base) = (value))
+#define CRC_RMW_GPOLYLL(base, mask, value) (CRC_WR_GPOLYLL(base, (CRC_RD_GPOLYLL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) |  (value)))
+#define CRC_CLR_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) & ~(value)))
+#define CRC_TOG_GPOLYLL(base, value) (CRC_WR_GPOLYLL(base, CRC_RD_GPOLYLL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLY - CRC Polynomial register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLY - CRC Polynomial register (RW)
+ *
+ * Reset value: 0x00001021U
+ *
+ * This register contains the value of the polynomial for the CRC calculation.
+ * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
+ * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
+ * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
+ * used in both 16- and 32-bit CRC modes.
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLY register
+ */
+/*@{*/
+#define CRC_RD_GPOLY(base)       (CRC_GPOLY_REG(base))
+#define CRC_WR_GPOLY(base, value) (CRC_GPOLY_REG(base) = (value))
+#define CRC_RMW_GPOLY(base, mask, value) (CRC_WR_GPOLY(base, (CRC_RD_GPOLY(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) |  (value)))
+#define CRC_CLR_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) & ~(value)))
+#define CRC_TOG_GPOLY(base, value) (CRC_WR_GPOLY(base, CRC_RD_GPOLY(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_GPOLY bitfields
+ */
+
+/*!
+ * @name Register CRC_GPOLY, field LOW[15:0] (RW)
+ *
+ * Writable and readable in both 32-bit and 16-bit CRC modes.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_GPOLY_LOW field. */
+#define CRC_RD_GPOLY_LOW(base) ((CRC_GPOLY_REG(base) & CRC_GPOLY_LOW_MASK) >> CRC_GPOLY_LOW_SHIFT)
+#define CRC_BRD_GPOLY_LOW(base) (CRC_RD_GPOLY_LOW(base))
+
+/*! @brief Set the LOW field to a new value. */
+#define CRC_WR_GPOLY_LOW(base, value) (CRC_RMW_GPOLY(base, CRC_GPOLY_LOW_MASK, CRC_GPOLY_LOW(value)))
+#define CRC_BWR_GPOLY_LOW(base, value) (CRC_WR_GPOLY_LOW(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
+ *
+ * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
+ * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_GPOLY_HIGH field. */
+#define CRC_RD_GPOLY_HIGH(base) ((CRC_GPOLY_REG(base) & CRC_GPOLY_HIGH_MASK) >> CRC_GPOLY_HIGH_SHIFT)
+#define CRC_BRD_GPOLY_HIGH(base) (CRC_RD_GPOLY_HIGH(base))
+
+/*! @brief Set the HIGH field to a new value. */
+#define CRC_WR_GPOLY_HIGH(base, value) (CRC_RMW_GPOLY(base, CRC_GPOLY_HIGH_MASK, CRC_GPOLY_HIGH(value)))
+#define CRC_BWR_GPOLY_HIGH(base, value) (CRC_WR_GPOLY_HIGH(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYL - CRC_GPOLYL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYL - CRC_GPOLYL register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYL(base)      (CRC_GPOLYL_REG(base))
+#define CRC_WR_GPOLYL(base, value) (CRC_GPOLYL_REG(base) = (value))
+#define CRC_RMW_GPOLYL(base, mask, value) (CRC_WR_GPOLYL(base, (CRC_RD_GPOLYL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) |  (value)))
+#define CRC_CLR_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) & ~(value)))
+#define CRC_TOG_GPOLYL(base, value) (CRC_WR_GPOLYL(base, CRC_RD_GPOLYL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYLU - CRC_GPOLYLU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYLU register
+ */
+/*@{*/
+#define CRC_RD_GPOLYLU(base)     (CRC_GPOLYLU_REG(base))
+#define CRC_WR_GPOLYLU(base, value) (CRC_GPOLYLU_REG(base) = (value))
+#define CRC_RMW_GPOLYLU(base, mask, value) (CRC_WR_GPOLYLU(base, (CRC_RD_GPOLYLU(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) |  (value)))
+#define CRC_CLR_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) & ~(value)))
+#define CRC_TOG_GPOLYLU(base, value) (CRC_WR_GPOLYLU(base, CRC_RD_GPOLYLU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYH - CRC_GPOLYH register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYH - CRC_GPOLYH register. (RW)
+ *
+ * Reset value: 0xFFFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYH register
+ */
+/*@{*/
+#define CRC_RD_GPOLYH(base)      (CRC_GPOLYH_REG(base))
+#define CRC_WR_GPOLYH(base, value) (CRC_GPOLYH_REG(base) = (value))
+#define CRC_RMW_GPOLYH(base, mask, value) (CRC_WR_GPOLYH(base, (CRC_RD_GPOLYH(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) |  (value)))
+#define CRC_CLR_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) & ~(value)))
+#define CRC_TOG_GPOLYH(base, value) (CRC_WR_GPOLYH(base, CRC_RD_GPOLYH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYHL - CRC_GPOLYHL register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHL register
+ */
+/*@{*/
+#define CRC_RD_GPOLYHL(base)     (CRC_GPOLYHL_REG(base))
+#define CRC_WR_GPOLYHL(base, value) (CRC_GPOLYHL_REG(base) = (value))
+#define CRC_RMW_GPOLYHL(base, mask, value) (CRC_WR_GPOLYHL(base, (CRC_RD_GPOLYHL(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) |  (value)))
+#define CRC_CLR_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) & ~(value)))
+#define CRC_TOG_GPOLYHL(base, value) (CRC_WR_GPOLYHL(base, CRC_RD_GPOLYHL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_GPOLYHU - CRC_GPOLYHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire CRC_GPOLYHU register
+ */
+/*@{*/
+#define CRC_RD_GPOLYHU(base)     (CRC_GPOLYHU_REG(base))
+#define CRC_WR_GPOLYHU(base, value) (CRC_GPOLYHU_REG(base) = (value))
+#define CRC_RMW_GPOLYHU(base, mask, value) (CRC_WR_GPOLYHU(base, (CRC_RD_GPOLYHU(base) & ~(mask)) | (value)))
+#define CRC_SET_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) |  (value)))
+#define CRC_CLR_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) & ~(value)))
+#define CRC_TOG_GPOLYHU(base, value) (CRC_WR_GPOLYHU(base, CRC_RD_GPOLYHU(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_CTRL - CRC Control register
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_CTRL - CRC Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls the configuration and working of the CRC module.
+ * Appropriate bits must be set before starting a new CRC calculation. A new CRC
+ * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
+ * the CRC data register.
+ */
+/*!
+ * @name Constants and macros for entire CRC_CTRL register
+ */
+/*@{*/
+#define CRC_RD_CTRL(base)        (CRC_CTRL_REG(base))
+#define CRC_WR_CTRL(base, value) (CRC_CTRL_REG(base) = (value))
+#define CRC_RMW_CTRL(base, mask, value) (CRC_WR_CTRL(base, (CRC_RD_CTRL(base) & ~(mask)) | (value)))
+#define CRC_SET_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) |  (value)))
+#define CRC_CLR_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) & ~(value)))
+#define CRC_TOG_CTRL(base, value) (CRC_WR_CTRL(base, CRC_RD_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_CTRL bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRL, field TCRC[24] (RW)
+ *
+ * Width of CRC protocol.
+ *
+ * Values:
+ * - 0b0 - 16-bit CRC protocol.
+ * - 0b1 - 32-bit CRC protocol.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TCRC field. */
+#define CRC_RD_CTRL_TCRC(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TCRC_MASK) >> CRC_CTRL_TCRC_SHIFT)
+#define CRC_BRD_CTRL_TCRC(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_TCRC_SHIFT))
+
+/*! @brief Set the TCRC field to a new value. */
+#define CRC_WR_CTRL_TCRC(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TCRC_MASK, CRC_CTRL_TCRC(value)))
+#define CRC_BWR_CTRL_TCRC(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_TCRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field WAS[25] (RW)
+ *
+ * When asserted, a value written to the CRC data register is considered a seed
+ * value. When deasserted, a value written to the CRC data register is taken as
+ * data for CRC computation.
+ *
+ * Values:
+ * - 0b0 - Writes to the CRC data register are data values.
+ * - 0b1 - Writes to the CRC data register are seed values.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_WAS field. */
+#define CRC_RD_CTRL_WAS(base) ((CRC_CTRL_REG(base) & CRC_CTRL_WAS_MASK) >> CRC_CTRL_WAS_SHIFT)
+#define CRC_BRD_CTRL_WAS(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_WAS_SHIFT))
+
+/*! @brief Set the WAS field to a new value. */
+#define CRC_WR_CTRL_WAS(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_WAS_MASK, CRC_CTRL_WAS(value)))
+#define CRC_BWR_CTRL_WAS(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_WAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field FXOR[26] (RW)
+ *
+ * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
+ * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
+ *
+ * Values:
+ * - 0b0 - No XOR on reading.
+ * - 0b1 - Invert or complement the read value of the CRC Data register.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_FXOR field. */
+#define CRC_RD_CTRL_FXOR(base) ((CRC_CTRL_REG(base) & CRC_CTRL_FXOR_MASK) >> CRC_CTRL_FXOR_SHIFT)
+#define CRC_BRD_CTRL_FXOR(base) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_FXOR_SHIFT))
+
+/*! @brief Set the FXOR field to a new value. */
+#define CRC_WR_CTRL_FXOR(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_FXOR_MASK, CRC_CTRL_FXOR(value)))
+#define CRC_BWR_CTRL_FXOR(base, value) (BITBAND_ACCESS32(&CRC_CTRL_REG(base), CRC_CTRL_FXOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field TOTR[29:28] (RW)
+ *
+ * Identifies the transpose configuration of the value read from the CRC Data
+ * register. See the description of the transpose feature for the available
+ * transpose options.
+ *
+ * Values:
+ * - 0b00 - No transposition.
+ * - 0b01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TOTR field. */
+#define CRC_RD_CTRL_TOTR(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT)
+#define CRC_BRD_CTRL_TOTR(base) (CRC_RD_CTRL_TOTR(base))
+
+/*! @brief Set the TOTR field to a new value. */
+#define CRC_WR_CTRL_TOTR(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TOTR_MASK, CRC_CTRL_TOTR(value)))
+#define CRC_BWR_CTRL_TOTR(base, value) (CRC_WR_CTRL_TOTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRL, field TOT[31:30] (RW)
+ *
+ * Defines the transpose configuration of the data written to the CRC data
+ * register. See the description of the transpose feature for the available transpose
+ * options.
+ *
+ * Values:
+ * - 0b00 - No transposition.
+ * - 0b01 - Bits in bytes are transposed; bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRL_TOT field. */
+#define CRC_RD_CTRL_TOT(base) ((CRC_CTRL_REG(base) & CRC_CTRL_TOT_MASK) >> CRC_CTRL_TOT_SHIFT)
+#define CRC_BRD_CTRL_TOT(base) (CRC_RD_CTRL_TOT(base))
+
+/*! @brief Set the TOT field to a new value. */
+#define CRC_WR_CTRL_TOT(base, value) (CRC_RMW_CTRL(base, CRC_CTRL_TOT_MASK, CRC_CTRL_TOT(value)))
+#define CRC_BWR_CTRL_TOT(base, value) (CRC_WR_CTRL_TOT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * CRC_CTRLHU - CRC_CTRLHU register.
+ ******************************************************************************/
+
+/*!
+ * @brief CRC_CTRLHU - CRC_CTRLHU register. (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire CRC_CTRLHU register
+ */
+/*@{*/
+#define CRC_RD_CTRLHU(base)      (CRC_CTRLHU_REG(base))
+#define CRC_WR_CTRLHU(base, value) (CRC_CTRLHU_REG(base) = (value))
+#define CRC_RMW_CTRLHU(base, mask, value) (CRC_WR_CTRLHU(base, (CRC_RD_CTRLHU(base) & ~(mask)) | (value)))
+#define CRC_SET_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) |  (value)))
+#define CRC_CLR_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) & ~(value)))
+#define CRC_TOG_CTRLHU(base, value) (CRC_WR_CTRLHU(base, CRC_RD_CTRLHU(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual CRC_CTRLHU bitfields
+ */
+
+/*!
+ * @name Register CRC_CTRLHU, field TCRC[0] (RW)
+ *
+ * Values:
+ * - 0b0 - 16-bit CRC protocol.
+ * - 0b1 - 32-bit CRC protocol.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TCRC field. */
+#define CRC_RD_CTRLHU_TCRC(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TCRC_MASK) >> CRC_CTRLHU_TCRC_SHIFT)
+#define CRC_BRD_CTRLHU_TCRC(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_TCRC_SHIFT))
+
+/*! @brief Set the TCRC field to a new value. */
+#define CRC_WR_CTRLHU_TCRC(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TCRC_MASK, CRC_CTRLHU_TCRC(value)))
+#define CRC_BWR_CTRLHU_TCRC(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_TCRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field WAS[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Writes to CRC data register are data values.
+ * - 0b1 - Writes to CRC data reguster are seed values.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_WAS field. */
+#define CRC_RD_CTRLHU_WAS(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_WAS_MASK) >> CRC_CTRLHU_WAS_SHIFT)
+#define CRC_BRD_CTRLHU_WAS(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_WAS_SHIFT))
+
+/*! @brief Set the WAS field to a new value. */
+#define CRC_WR_CTRLHU_WAS(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_WAS_MASK, CRC_CTRLHU_WAS(value)))
+#define CRC_BWR_CTRLHU_WAS(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_WAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field FXOR[2] (RW)
+ *
+ * Values:
+ * - 0b0 - No XOR on reading.
+ * - 0b1 - Invert or complement the read value of CRC data register.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_FXOR field. */
+#define CRC_RD_CTRLHU_FXOR(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_FXOR_MASK) >> CRC_CTRLHU_FXOR_SHIFT)
+#define CRC_BRD_CTRLHU_FXOR(base) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_FXOR_SHIFT))
+
+/*! @brief Set the FXOR field to a new value. */
+#define CRC_WR_CTRLHU_FXOR(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_FXOR_MASK, CRC_CTRLHU_FXOR(value)))
+#define CRC_BWR_CTRLHU_FXOR(base, value) (BITBAND_ACCESS8(&CRC_CTRLHU_REG(base), CRC_CTRLHU_FXOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
+ *
+ * Values:
+ * - 0b00 - No Transposition.
+ * - 0b01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TOTR field. */
+#define CRC_RD_CTRLHU_TOTR(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TOTR_MASK) >> CRC_CTRLHU_TOTR_SHIFT)
+#define CRC_BRD_CTRLHU_TOTR(base) (CRC_RD_CTRLHU_TOTR(base))
+
+/*! @brief Set the TOTR field to a new value. */
+#define CRC_WR_CTRLHU_TOTR(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TOTR_MASK, CRC_CTRLHU_TOTR(value)))
+#define CRC_BWR_CTRLHU_TOTR(base, value) (CRC_WR_CTRLHU_TOTR(base, value))
+/*@}*/
+
+/*!
+ * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
+ *
+ * Values:
+ * - 0b00 - No Transposition.
+ * - 0b01 - Bits in bytes are transposed, bytes are not transposed.
+ * - 0b10 - Both bits in bytes and bytes are transposed.
+ * - 0b11 - Only bytes are transposed; no bits in a byte are transposed.
+ */
+/*@{*/
+/*! @brief Read current value of the CRC_CTRLHU_TOT field. */
+#define CRC_RD_CTRLHU_TOT(base) ((CRC_CTRLHU_REG(base) & CRC_CTRLHU_TOT_MASK) >> CRC_CTRLHU_TOT_SHIFT)
+#define CRC_BRD_CTRLHU_TOT(base) (CRC_RD_CTRLHU_TOT(base))
+
+/*! @brief Set the TOT field to a new value. */
+#define CRC_WR_CTRLHU_TOT(base, value) (CRC_RMW_CTRLHU(base, CRC_CTRLHU_TOT_MASK, CRC_CTRLHU_TOT(value)))
+#define CRC_BWR_CTRLHU_TOT(base, value) (CRC_WR_CTRLHU_TOT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 DAC
+ *
+ * 12-Bit Digital-to-Analog Converter
+ *
+ * Registers defined in this header file:
+ * - DAC_DATL - DAC Data Low Register
+ * - DAC_DATH - DAC Data High Register
+ * - DAC_SR - DAC Status Register
+ * - DAC_C0 - DAC Control Register
+ * - DAC_C1 - DAC Control Register 1
+ * - DAC_C2 - DAC Control Register 2
+ */
+
+#define DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
+#define DAC0_IDX (0U) /*!< Instance number for DAC0. */
+#define DAC1_IDX (1U) /*!< Instance number for DAC1. */
+
+/*******************************************************************************
+ * DAC_DATL - DAC Data Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATL - DAC Data Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATL register
+ */
+/*@{*/
+#define DAC_RD_DATL(base, index) (DAC_DATL_REG(base, index))
+#define DAC_WR_DATL(base, index, value) (DAC_DATL_REG(base, index) = (value))
+#define DAC_RMW_DATL(base, index, mask, value) (DAC_WR_DATL(base, index, (DAC_RD_DATL(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) |  (value)))
+#define DAC_CLR_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) & ~(value)))
+#define DAC_TOG_DATL(base, index, value) (DAC_WR_DATL(base, index, DAC_RD_DATL(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_DATH - DAC Data High Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_DATH - DAC Data High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire DAC_DATH register
+ */
+/*@{*/
+#define DAC_RD_DATH(base, index) (DAC_DATH_REG(base, index))
+#define DAC_WR_DATH(base, index, value) (DAC_DATH_REG(base, index) = (value))
+#define DAC_RMW_DATH(base, index, mask, value) (DAC_WR_DATH(base, index, (DAC_RD_DATH(base, index) & ~(mask)) | (value)))
+#define DAC_SET_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) |  (value)))
+#define DAC_CLR_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) & ~(value)))
+#define DAC_TOG_DATH(base, index, value) (DAC_WR_DATH(base, index, DAC_RD_DATH(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_DATH bitfields
+ */
+
+/*!
+ * @name Register DAC_DATH, field DATA1[3:0] (RW)
+ *
+ * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
+ * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
+ * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_DATH_DATA1 field. */
+#define DAC_RD_DATH_DATA1(base, index) ((DAC_DATH_REG(base, index) & DAC_DATH_DATA1_MASK) >> DAC_DATH_DATA1_SHIFT)
+#define DAC_BRD_DATH_DATA1(base, index) (DAC_RD_DATH_DATA1(base, index))
+
+/*! @brief Set the DATA1 field to a new value. */
+#define DAC_WR_DATH_DATA1(base, index, value) (DAC_RMW_DATH(base, index, DAC_DATH_DATA1_MASK, DAC_DATH_DATA1(value)))
+#define DAC_BWR_DATH_DATA1(base, index, value) (DAC_WR_DATH_DATA1(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_SR - DAC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_SR - DAC Status Register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
+ * request is done. Writing 0 to a field clears it whereas writing 1 has no
+ * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
+ * The flags are set only when the data buffer status is changed. Do not use
+ * 32/16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_SR register
+ */
+/*@{*/
+#define DAC_RD_SR(base)          (DAC_SR_REG(base))
+#define DAC_WR_SR(base, value)   (DAC_SR_REG(base) = (value))
+#define DAC_RMW_SR(base, mask, value) (DAC_WR_SR(base, (DAC_RD_SR(base) & ~(mask)) | (value)))
+#define DAC_SET_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) |  (value)))
+#define DAC_CLR_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) & ~(value)))
+#define DAC_TOG_SR(base, value)  (DAC_WR_SR(base, DAC_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_SR bitfields
+ */
+
+/*!
+ * @name Register DAC_SR, field DACBFRPBF[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
+ * - 0b1 - The DAC buffer read pointer is equal to C2[DACBFUP].
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
+#define DAC_RD_SR_DACBFRPBF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPBF_MASK) >> DAC_SR_DACBFRPBF_SHIFT)
+#define DAC_BRD_SR_DACBFRPBF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT))
+
+/*! @brief Set the DACBFRPBF field to a new value. */
+#define DAC_WR_SR_DACBFRPBF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPBF_MASK, DAC_SR_DACBFRPBF(value)))
+#define DAC_BWR_SR_DACBFRPBF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFRPTF[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer is not zero.
+ * - 0b1 - The DAC buffer read pointer is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
+#define DAC_RD_SR_DACBFRPTF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPTF_MASK) >> DAC_SR_DACBFRPTF_SHIFT)
+#define DAC_BRD_SR_DACBFRPTF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT))
+
+/*! @brief Set the DACBFRPTF field to a new value. */
+#define DAC_WR_SR_DACBFRPTF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPTF_MASK, DAC_SR_DACBFRPTF(value)))
+#define DAC_BWR_SR_DACBFRPTF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_SR, field DACBFWMF[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer has not reached the watermark level.
+ * - 0b1 - The DAC buffer read pointer has reached the watermark level.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_SR_DACBFWMF field. */
+#define DAC_RD_SR_DACBFWMF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFWMF_MASK) >> DAC_SR_DACBFWMF_SHIFT)
+#define DAC_BRD_SR_DACBFWMF(base) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFWMF_SHIFT))
+
+/*! @brief Set the DACBFWMF field to a new value. */
+#define DAC_WR_SR_DACBFWMF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFWMF_MASK, DAC_SR_DACBFWMF(value)))
+#define DAC_BWR_SR_DACBFWMF(base, value) (BITBAND_ACCESS8(&DAC_SR_REG(base), DAC_SR_DACBFWMF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C0 - DAC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C0 - DAC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_C0 register
+ */
+/*@{*/
+#define DAC_RD_C0(base)          (DAC_C0_REG(base))
+#define DAC_WR_C0(base, value)   (DAC_C0_REG(base) = (value))
+#define DAC_RMW_C0(base, mask, value) (DAC_WR_C0(base, (DAC_RD_C0(base) & ~(mask)) | (value)))
+#define DAC_SET_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) |  (value)))
+#define DAC_CLR_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) & ~(value)))
+#define DAC_TOG_C0(base, value)  (DAC_WR_C0(base, DAC_RD_C0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C0 bitfields
+ */
+
+/*!
+ * @name Register DAC_C0, field DACBBIEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer bottom flag interrupt is disabled.
+ * - 0b1 - The DAC buffer read pointer bottom flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBBIEN field. */
+#define DAC_RD_C0_DACBBIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBBIEN_MASK) >> DAC_C0_DACBBIEN_SHIFT)
+#define DAC_BRD_C0_DACBBIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT))
+
+/*! @brief Set the DACBBIEN field to a new value. */
+#define DAC_WR_C0_DACBBIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBBIEN_MASK, DAC_C0_DACBBIEN(value)))
+#define DAC_BWR_C0_DACBBIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBTIEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer read pointer top flag interrupt is disabled.
+ * - 0b1 - The DAC buffer read pointer top flag interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBTIEN field. */
+#define DAC_RD_C0_DACBTIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBTIEN_MASK) >> DAC_C0_DACBTIEN_SHIFT)
+#define DAC_BRD_C0_DACBTIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT))
+
+/*! @brief Set the DACBTIEN field to a new value. */
+#define DAC_WR_C0_DACBTIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBTIEN_MASK, DAC_C0_DACBTIEN(value)))
+#define DAC_BWR_C0_DACBTIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACBWIEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC buffer watermark interrupt is disabled.
+ * - 0b1 - The DAC buffer watermark interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACBWIEN field. */
+#define DAC_RD_C0_DACBWIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBWIEN_MASK) >> DAC_C0_DACBWIEN_SHIFT)
+#define DAC_BRD_C0_DACBWIEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBWIEN_SHIFT))
+
+/*! @brief Set the DACBWIEN field to a new value. */
+#define DAC_WR_C0_DACBWIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBWIEN_MASK, DAC_C0_DACBWIEN(value)))
+#define DAC_BWR_C0_DACBWIEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACBWIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field LPEN[3] (RW)
+ *
+ * See the 12-bit DAC electrical characteristics of the device data sheet for
+ * details on the impact of the modes below.
+ *
+ * Values:
+ * - 0b0 - High-Power mode
+ * - 0b1 - Low-Power mode
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_LPEN field. */
+#define DAC_RD_C0_LPEN(base) ((DAC_C0_REG(base) & DAC_C0_LPEN_MASK) >> DAC_C0_LPEN_SHIFT)
+#define DAC_BRD_C0_LPEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT))
+
+/*! @brief Set the LPEN field to a new value. */
+#define DAC_WR_C0_LPEN(base, value) (DAC_RMW_C0(base, DAC_C0_LPEN_MASK, DAC_C0_LPEN(value)))
+#define DAC_BWR_C0_LPEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
+ *
+ * Active high. This is a write-only field, which always reads 0. If DAC
+ * software trigger is selected and buffer is enabled, writing 1 to this field will
+ * advance the buffer read pointer once.
+ *
+ * Values:
+ * - 0b0 - The DAC soft trigger is not valid.
+ * - 0b1 - The DAC soft trigger is valid.
+ */
+/*@{*/
+/*! @brief Set the DACSWTRG field to a new value. */
+#define DAC_WR_C0_DACSWTRG(base, value) (DAC_RMW_C0(base, DAC_C0_DACSWTRG_MASK, DAC_C0_DACSWTRG(value)))
+#define DAC_BWR_C0_DACSWTRG(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACSWTRG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACTRGSEL[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC hardware trigger is selected.
+ * - 0b1 - The DAC software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
+#define DAC_RD_C0_DACTRGSEL(base) ((DAC_C0_REG(base) & DAC_C0_DACTRGSEL_MASK) >> DAC_C0_DACTRGSEL_SHIFT)
+#define DAC_BRD_C0_DACTRGSEL(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT))
+
+/*! @brief Set the DACTRGSEL field to a new value. */
+#define DAC_WR_C0_DACTRGSEL(base, value) (DAC_RMW_C0(base, DAC_C0_DACTRGSEL_MASK, DAC_C0_DACTRGSEL(value)))
+#define DAC_BWR_C0_DACTRGSEL(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACRFS[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The DAC selects DACREF_1 as the reference voltage.
+ * - 0b1 - The DAC selects DACREF_2 as the reference voltage.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACRFS field. */
+#define DAC_RD_C0_DACRFS(base) ((DAC_C0_REG(base) & DAC_C0_DACRFS_MASK) >> DAC_C0_DACRFS_SHIFT)
+#define DAC_BRD_C0_DACRFS(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT))
+
+/*! @brief Set the DACRFS field to a new value. */
+#define DAC_WR_C0_DACRFS(base, value) (DAC_RMW_C0(base, DAC_C0_DACRFS_MASK, DAC_C0_DACRFS(value)))
+#define DAC_BWR_C0_DACRFS(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C0, field DACEN[7] (RW)
+ *
+ * Starts the Programmable Reference Generator operation.
+ *
+ * Values:
+ * - 0b0 - The DAC system is disabled.
+ * - 0b1 - The DAC system is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C0_DACEN field. */
+#define DAC_RD_C0_DACEN(base) ((DAC_C0_REG(base) & DAC_C0_DACEN_MASK) >> DAC_C0_DACEN_SHIFT)
+#define DAC_BRD_C0_DACEN(base) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT))
+
+/*! @brief Set the DACEN field to a new value. */
+#define DAC_WR_C0_DACEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACEN_MASK, DAC_C0_DACEN(value)))
+#define DAC_BWR_C0_DACEN(base, value) (BITBAND_ACCESS8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C1 - DAC Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C1 - DAC Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Do not use 32- or 16-bit accesses to this register.
+ */
+/*!
+ * @name Constants and macros for entire DAC_C1 register
+ */
+/*@{*/
+#define DAC_RD_C1(base)          (DAC_C1_REG(base))
+#define DAC_WR_C1(base, value)   (DAC_C1_REG(base) = (value))
+#define DAC_RMW_C1(base, mask, value) (DAC_WR_C1(base, (DAC_RD_C1(base) & ~(mask)) | (value)))
+#define DAC_SET_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) |  (value)))
+#define DAC_CLR_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) & ~(value)))
+#define DAC_TOG_C1(base, value)  (DAC_WR_C1(base, DAC_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C1 bitfields
+ */
+
+/*!
+ * @name Register DAC_C1, field DACBFEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Buffer read pointer is disabled. The converted data is always the
+ *     first word of the buffer.
+ * - 0b1 - Buffer read pointer is enabled. The converted data is the word that
+ *     the read pointer points to. It means converted data can be from any word of
+ *     the buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFEN field. */
+#define DAC_RD_C1_DACBFEN(base) ((DAC_C1_REG(base) & DAC_C1_DACBFEN_MASK) >> DAC_C1_DACBFEN_SHIFT)
+#define DAC_BRD_C1_DACBFEN(base) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT))
+
+/*! @brief Set the DACBFEN field to a new value. */
+#define DAC_WR_C1_DACBFEN(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFEN_MASK, DAC_C1_DACBFEN(value)))
+#define DAC_BWR_C1_DACBFEN(base, value) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFMD[2:1] (RW)
+ *
+ * Values:
+ * - 0b00 - Normal mode
+ * - 0b01 - Swing mode
+ * - 0b10 - One-Time Scan mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFMD field. */
+#define DAC_RD_C1_DACBFMD(base) ((DAC_C1_REG(base) & DAC_C1_DACBFMD_MASK) >> DAC_C1_DACBFMD_SHIFT)
+#define DAC_BRD_C1_DACBFMD(base) (DAC_RD_C1_DACBFMD(base))
+
+/*! @brief Set the DACBFMD field to a new value. */
+#define DAC_WR_C1_DACBFMD(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFMD_MASK, DAC_C1_DACBFMD(value)))
+#define DAC_BWR_C1_DACBFMD(base, value) (DAC_WR_C1_DACBFMD(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DACBFWM[4:3] (RW)
+ *
+ * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
+ * the word defined by this field, which is 1-4 words away from the upper limit
+ * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
+ * watermark interrupt.
+ *
+ * Values:
+ * - 0b00 - 1 word
+ * - 0b01 - 2 words
+ * - 0b10 - 3 words
+ * - 0b11 - 4 words
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DACBFWM field. */
+#define DAC_RD_C1_DACBFWM(base) ((DAC_C1_REG(base) & DAC_C1_DACBFWM_MASK) >> DAC_C1_DACBFWM_SHIFT)
+#define DAC_BRD_C1_DACBFWM(base) (DAC_RD_C1_DACBFWM(base))
+
+/*! @brief Set the DACBFWM field to a new value. */
+#define DAC_WR_C1_DACBFWM(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFWM_MASK, DAC_C1_DACBFWM(value)))
+#define DAC_BWR_C1_DACBFWM(base, value) (DAC_WR_C1_DACBFWM(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C1, field DMAEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA is disabled.
+ * - 0b1 - DMA is enabled. When DMA is enabled, the DMA request will be
+ *     generated by original interrupts. The interrupts will not be presented on this
+ *     module at the same time.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C1_DMAEN field. */
+#define DAC_RD_C1_DMAEN(base) ((DAC_C1_REG(base) & DAC_C1_DMAEN_MASK) >> DAC_C1_DMAEN_SHIFT)
+#define DAC_BRD_C1_DMAEN(base) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define DAC_WR_C1_DMAEN(base, value) (DAC_RMW_C1(base, DAC_C1_DMAEN_MASK, DAC_C1_DMAEN(value)))
+#define DAC_BWR_C1_DMAEN(base, value) (BITBAND_ACCESS8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DAC_C2 - DAC Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief DAC_C2 - DAC Control Register 2 (RW)
+ *
+ * Reset value: 0x0FU
+ */
+/*!
+ * @name Constants and macros for entire DAC_C2 register
+ */
+/*@{*/
+#define DAC_RD_C2(base)          (DAC_C2_REG(base))
+#define DAC_WR_C2(base, value)   (DAC_C2_REG(base) = (value))
+#define DAC_RMW_C2(base, mask, value) (DAC_WR_C2(base, (DAC_RD_C2(base) & ~(mask)) | (value)))
+#define DAC_SET_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) |  (value)))
+#define DAC_CLR_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) & ~(value)))
+#define DAC_TOG_C2(base, value)  (DAC_WR_C2(base, DAC_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DAC_C2 bitfields
+ */
+
+/*!
+ * @name Register DAC_C2, field DACBFUP[3:0] (RW)
+ *
+ * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
+ * exceed it.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFUP field. */
+#define DAC_RD_C2_DACBFUP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFUP_MASK) >> DAC_C2_DACBFUP_SHIFT)
+#define DAC_BRD_C2_DACBFUP(base) (DAC_RD_C2_DACBFUP(base))
+
+/*! @brief Set the DACBFUP field to a new value. */
+#define DAC_WR_C2_DACBFUP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFUP_MASK, DAC_C2_DACBFUP(value)))
+#define DAC_BWR_C2_DACBFUP(base, value) (DAC_WR_C2_DACBFUP(base, value))
+/*@}*/
+
+/*!
+ * @name Register DAC_C2, field DACBFRP[7:4] (RW)
+ *
+ * Keeps the current value of the buffer read pointer.
+ */
+/*@{*/
+/*! @brief Read current value of the DAC_C2_DACBFRP field. */
+#define DAC_RD_C2_DACBFRP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT)
+#define DAC_BRD_C2_DACBFRP(base) (DAC_RD_C2_DACBFRP(base))
+
+/*! @brief Set the DACBFRP field to a new value. */
+#define DAC_WR_C2_DACBFRP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFRP_MASK, DAC_C2_DACBFRP(value)))
+#define DAC_BWR_C2_DACBFRP(base, value) (DAC_WR_C2_DACBFRP(base, value))
+/*@}*/
+
+/*
+ * MK64F12 DMA
+ *
+ * Enhanced direct memory access controller
+ *
+ * Registers defined in this header file:
+ * - DMA_CR - Control Register
+ * - DMA_ES - Error Status Register
+ * - DMA_ERQ - Enable Request Register
+ * - DMA_EEI - Enable Error Interrupt Register
+ * - DMA_CEEI - Clear Enable Error Interrupt Register
+ * - DMA_SEEI - Set Enable Error Interrupt Register
+ * - DMA_CERQ - Clear Enable Request Register
+ * - DMA_SERQ - Set Enable Request Register
+ * - DMA_CDNE - Clear DONE Status Bit Register
+ * - DMA_SSRT - Set START Bit Register
+ * - DMA_CERR - Clear Error Register
+ * - DMA_CINT - Clear Interrupt Request Register
+ * - DMA_INT - Interrupt Request Register
+ * - DMA_ERR - Error Register
+ * - DMA_HRS - Hardware Request Status Register
+ * - DMA_DCHPRI3 - Channel n Priority Register
+ * - DMA_DCHPRI2 - Channel n Priority Register
+ * - DMA_DCHPRI1 - Channel n Priority Register
+ * - DMA_DCHPRI0 - Channel n Priority Register
+ * - DMA_DCHPRI7 - Channel n Priority Register
+ * - DMA_DCHPRI6 - Channel n Priority Register
+ * - DMA_DCHPRI5 - Channel n Priority Register
+ * - DMA_DCHPRI4 - Channel n Priority Register
+ * - DMA_DCHPRI11 - Channel n Priority Register
+ * - DMA_DCHPRI10 - Channel n Priority Register
+ * - DMA_DCHPRI9 - Channel n Priority Register
+ * - DMA_DCHPRI8 - Channel n Priority Register
+ * - DMA_DCHPRI15 - Channel n Priority Register
+ * - DMA_DCHPRI14 - Channel n Priority Register
+ * - DMA_DCHPRI13 - Channel n Priority Register
+ * - DMA_DCHPRI12 - Channel n Priority Register
+ * - DMA_SADDR - TCD Source Address
+ * - DMA_SOFF - TCD Signed Source Address Offset
+ * - DMA_ATTR - TCD Transfer Attributes
+ * - DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ * - DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ * - DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ * - DMA_SLAST - TCD Last Source Address Adjustment
+ * - DMA_DADDR - TCD Destination Address
+ * - DMA_DOFF - TCD Signed Destination Address Offset
+ * - DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ * - DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ * - DMA_CSR - TCD Control and Status
+ * - DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ * - DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ */
+
+#define DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
+#define DMA_IDX (0U) /*!< Instance number for DMA. */
+
+/*******************************************************************************
+ * DMA_CR - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CR defines the basic operating configuration of the DMA. Arbitration can
+ * be configured to use either a fixed-priority or a round-robin scheme. For
+ * fixed-priority arbitration, the highest priority channel requesting service is
+ * selected to execute. The channel priority registers assign the priorities; see
+ * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
+ * ignored and channels are cycled through (from high to low channel number)
+ * without regard to priority. For correct operation, writes to the CR register must
+ * be performed only when the DMA channels are inactive; that is, when
+ * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
+ * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
+ * minor loop completion. When minor loop offsets are enabled, the minor loop
+ * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
+ * destination address (TCDn_DADDR), or to both prior to the addresses being
+ * written back into the TCD. If the major loop is complete, the minor loop offset is
+ * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
+ * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
+ * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
+ * is used to specify multiple fields: a source enable bit (SMLOE) to specify
+ * the minor loop offset should be applied to the source address (TCDn_SADDR) upon
+ * minor loop completion, a destination enable bit (DMLOE) to specify the minor
+ * loop offset should be applied to the destination address (TCDn_DADDR) upon
+ * minor loop completion, and the sign extended minor loop offset value (MLOFF). The
+ * same offset value (MLOFF) is used for both source and destination minor loop
+ * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
+ * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
+ * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
+ * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
+ * assigned to the NBYTES field.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CR register
+ */
+/*@{*/
+#define DMA_RD_CR(base)          (DMA_CR_REG(base))
+#define DMA_WR_CR(base, value)   (DMA_CR_REG(base) = (value))
+#define DMA_RMW_CR(base, mask, value) (DMA_WR_CR(base, (DMA_RD_CR(base) & ~(mask)) | (value)))
+#define DMA_SET_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) |  (value)))
+#define DMA_CLR_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) & ~(value)))
+#define DMA_TOG_CR(base, value)  (DMA_WR_CR(base, DMA_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CR bitfields
+ */
+
+/*!
+ * @name Register DMA_CR, field EDBG[1] (RW)
+ *
+ * Values:
+ * - 0b0 - When in debug mode, the DMA continues to operate.
+ * - 0b1 - When in debug mode, the DMA stalls the start of a new channel.
+ *     Executing channels are allowed to complete. Channel execution resumes when the
+ *     system exits debug mode or the EDBG bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_EDBG field. */
+#define DMA_RD_CR_EDBG(base) ((DMA_CR_REG(base) & DMA_CR_EDBG_MASK) >> DMA_CR_EDBG_SHIFT)
+#define DMA_BRD_CR_EDBG(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EDBG_SHIFT))
+
+/*! @brief Set the EDBG field to a new value. */
+#define DMA_WR_CR_EDBG(base, value) (DMA_RMW_CR(base, DMA_CR_EDBG_MASK, DMA_CR_EDBG(value)))
+#define DMA_BWR_CR_EDBG(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EDBG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field ERCA[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Fixed priority arbitration is used for channel selection .
+ * - 0b1 - Round robin arbitration is used for channel selection .
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_ERCA field. */
+#define DMA_RD_CR_ERCA(base) ((DMA_CR_REG(base) & DMA_CR_ERCA_MASK) >> DMA_CR_ERCA_SHIFT)
+#define DMA_BRD_CR_ERCA(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ERCA_SHIFT))
+
+/*! @brief Set the ERCA field to a new value. */
+#define DMA_WR_CR_ERCA(base, value) (DMA_RMW_CR(base, DMA_CR_ERCA_MASK, DMA_CR_ERCA(value)))
+#define DMA_BWR_CR_ERCA(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ERCA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field HOE[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Any error causes the HALT bit to set. Subsequently, all service
+ *     requests are ignored until the HALT bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_HOE field. */
+#define DMA_RD_CR_HOE(base)  ((DMA_CR_REG(base) & DMA_CR_HOE_MASK) >> DMA_CR_HOE_SHIFT)
+#define DMA_BRD_CR_HOE(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HOE_SHIFT))
+
+/*! @brief Set the HOE field to a new value. */
+#define DMA_WR_CR_HOE(base, value) (DMA_RMW_CR(base, DMA_CR_HOE_MASK, DMA_CR_HOE(value)))
+#define DMA_BWR_CR_HOE(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field HALT[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Stall the start of any new channels. Executing channels are allowed
+ *     to complete. Channel execution resumes when this bit is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_HALT field. */
+#define DMA_RD_CR_HALT(base) ((DMA_CR_REG(base) & DMA_CR_HALT_MASK) >> DMA_CR_HALT_SHIFT)
+#define DMA_BRD_CR_HALT(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define DMA_WR_CR_HALT(base, value) (DMA_RMW_CR(base, DMA_CR_HALT_MASK, DMA_CR_HALT(value)))
+#define DMA_BWR_CR_HALT(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field CLM[6] (RW)
+ *
+ * Values:
+ * - 0b0 - A minor loop channel link made to itself goes through channel
+ *     arbitration before being activated again.
+ * - 0b1 - A minor loop channel link made to itself does not go through channel
+ *     arbitration before being activated again. Upon minor loop completion, the
+ *     channel activates again if that channel has a minor loop channel link
+ *     enabled and the link channel is itself. This effectively applies the minor
+ *     loop offsets and restarts the next minor loop.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_CLM field. */
+#define DMA_RD_CR_CLM(base)  ((DMA_CR_REG(base) & DMA_CR_CLM_MASK) >> DMA_CR_CLM_SHIFT)
+#define DMA_BRD_CR_CLM(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CLM_SHIFT))
+
+/*! @brief Set the CLM field to a new value. */
+#define DMA_WR_CR_CLM(base, value) (DMA_RMW_CR(base, DMA_CR_CLM_MASK, DMA_CR_CLM(value)))
+#define DMA_BWR_CR_CLM(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CLM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field EMLM[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
+ * - 0b1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
+ *     an offset field, and the NBYTES field. The individual enable fields allow
+ *     the minor loop offset to be applied to the source address, the
+ *     destination address, or both. The NBYTES field is reduced when either offset is
+ *     enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_EMLM field. */
+#define DMA_RD_CR_EMLM(base) ((DMA_CR_REG(base) & DMA_CR_EMLM_MASK) >> DMA_CR_EMLM_SHIFT)
+#define DMA_BRD_CR_EMLM(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EMLM_SHIFT))
+
+/*! @brief Set the EMLM field to a new value. */
+#define DMA_WR_CR_EMLM(base, value) (DMA_RMW_CR(base, DMA_CR_EMLM_MASK, DMA_CR_EMLM(value)))
+#define DMA_BWR_CR_EMLM(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_EMLM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field ECX[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Cancel the remaining data transfer in the same fashion as the CX bit.
+ *     Stop the executing channel and force the minor loop to finish. The cancel
+ *     takes effect after the last write of the current read/write sequence. The
+ *     ECX bit clears itself after the cancel is honored. In addition to
+ *     cancelling the transfer, ECX treats the cancel as an error condition, thus
+ *     updating the Error Status register (DMAx_ES) and generating an optional error
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_ECX field. */
+#define DMA_RD_CR_ECX(base)  ((DMA_CR_REG(base) & DMA_CR_ECX_MASK) >> DMA_CR_ECX_SHIFT)
+#define DMA_BRD_CR_ECX(base) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ECX_SHIFT))
+
+/*! @brief Set the ECX field to a new value. */
+#define DMA_WR_CR_ECX(base, value) (DMA_RMW_CR(base, DMA_CR_ECX_MASK, DMA_CR_ECX(value)))
+#define DMA_BWR_CR_ECX(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_ECX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CR, field CX[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - Cancel the remaining data transfer. Stop the executing channel and
+ *     force the minor loop to finish. The cancel takes effect after the last write
+ *     of the current read/write sequence. The CX bit clears itself after the
+ *     cancel has been honored. This cancel retires the channel normally as if the
+ *     minor loop was completed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CR_CX field. */
+#define DMA_RD_CR_CX(base)   ((DMA_CR_REG(base) & DMA_CR_CX_MASK) >> DMA_CR_CX_SHIFT)
+#define DMA_BRD_CR_CX(base)  (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CX_SHIFT))
+
+/*! @brief Set the CX field to a new value. */
+#define DMA_WR_CR_CX(base, value) (DMA_RMW_CR(base, DMA_CR_CX_MASK, DMA_CR_CX(value)))
+#define DMA_BWR_CR_CX(base, value) (BITBAND_ACCESS32(&DMA_CR_REG(base), DMA_CR_CX_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ES - Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ES - Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ES provides information concerning the last recorded channel error.
+ * Channel errors can be caused by: A configuration error, that is: An illegal setting
+ * in the transfer-control descriptor, or An illegal priority register setting
+ * in fixed-arbitration An error termination to a bus master read or write cycle
+ * See the Error Reporting and Handling section for more details.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ES register
+ */
+/*@{*/
+#define DMA_RD_ES(base)          (DMA_ES_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ES bitfields
+ */
+
+/*!
+ * @name Register DMA_ES, field DBE[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination bus error
+ * - 0b1 - The last recorded error was a bus error on a destination write
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DBE field. */
+#define DMA_RD_ES_DBE(base)  ((DMA_ES_REG(base) & DMA_ES_DBE_MASK) >> DMA_ES_DBE_SHIFT)
+#define DMA_BRD_ES_DBE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SBE[1] (RO)
+ *
+ * Values:
+ * - 0b0 - No source bus error
+ * - 0b1 - The last recorded error was a bus error on a source read
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SBE field. */
+#define DMA_RD_ES_SBE(base)  ((DMA_ES_REG(base) & DMA_ES_SBE_MASK) >> DMA_ES_SBE_SHIFT)
+#define DMA_BRD_ES_SBE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SGE[2] (RO)
+ *
+ * Values:
+ * - 0b0 - No scatter/gather configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DLASTSGA field. This field is checked at the beginning of a
+ *     scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled.
+ *     TCDn_DLASTSGA is not on a 32 byte boundary.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SGE field. */
+#define DMA_RD_ES_SGE(base)  ((DMA_ES_REG(base) & DMA_ES_SGE_MASK) >> DMA_ES_SGE_SHIFT)
+#define DMA_BRD_ES_SGE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SGE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field NCE[3] (RO)
+ *
+ * Values:
+ * - 0b0 - No NBYTES/CITER configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
+ *     TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
+ *     TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_NCE field. */
+#define DMA_RD_ES_NCE(base)  ((DMA_ES_REG(base) & DMA_ES_NCE_MASK) >> DMA_ES_NCE_SHIFT)
+#define DMA_BRD_ES_NCE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_NCE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field DOE[4] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination offset configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DOE field. */
+#define DMA_RD_ES_DOE(base)  ((DMA_ES_REG(base) & DMA_ES_DOE_MASK) >> DMA_ES_DOE_SHIFT)
+#define DMA_BRD_ES_DOE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field DAE[5] (RO)
+ *
+ * Values:
+ * - 0b0 - No destination address configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_DAE field. */
+#define DMA_RD_ES_DAE(base)  ((DMA_ES_REG(base) & DMA_ES_DAE_MASK) >> DMA_ES_DAE_SHIFT)
+#define DMA_BRD_ES_DAE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_DAE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SOE[6] (RO)
+ *
+ * Values:
+ * - 0b0 - No source offset configuration error
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SOE field. */
+#define DMA_RD_ES_SOE(base)  ((DMA_ES_REG(base) & DMA_ES_SOE_MASK) >> DMA_ES_SOE_SHIFT)
+#define DMA_BRD_ES_SOE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field SAE[7] (RO)
+ *
+ * Values:
+ * - 0b0 - No source address configuration error.
+ * - 0b1 - The last recorded error was a configuration error detected in the
+ *     TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_SAE field. */
+#define DMA_RD_ES_SAE(base)  ((DMA_ES_REG(base) & DMA_ES_SAE_MASK) >> DMA_ES_SAE_SHIFT)
+#define DMA_BRD_ES_SAE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_SAE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field ERRCHN[11:8] (RO)
+ *
+ * The channel number of the last recorded error (excluding CPE errors) or last
+ * recorded error canceled transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_ERRCHN field. */
+#define DMA_RD_ES_ERRCHN(base) ((DMA_ES_REG(base) & DMA_ES_ERRCHN_MASK) >> DMA_ES_ERRCHN_SHIFT)
+#define DMA_BRD_ES_ERRCHN(base) (DMA_RD_ES_ERRCHN(base))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field CPE[14] (RO)
+ *
+ * Values:
+ * - 0b0 - No channel priority error
+ * - 0b1 - The last recorded error was a configuration error in the channel
+ *     priorities . Channel priorities are not unique.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_CPE field. */
+#define DMA_RD_ES_CPE(base)  ((DMA_ES_REG(base) & DMA_ES_CPE_MASK) >> DMA_ES_CPE_SHIFT)
+#define DMA_BRD_ES_CPE(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_CPE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field ECX[16] (RO)
+ *
+ * Values:
+ * - 0b0 - No canceled transfers
+ * - 0b1 - The last recorded entry was a canceled transfer by the error cancel
+ *     transfer input
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_ECX field. */
+#define DMA_RD_ES_ECX(base)  ((DMA_ES_REG(base) & DMA_ES_ECX_MASK) >> DMA_ES_ECX_SHIFT)
+#define DMA_BRD_ES_ECX(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_ECX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_ES, field VLD[31] (RO)
+ *
+ * Logical OR of all ERR status bits
+ *
+ * Values:
+ * - 0b0 - No ERR bits are set
+ * - 0b1 - At least one ERR bit is set indicating a valid error exists that has
+ *     not been cleared
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ES_VLD field. */
+#define DMA_RD_ES_VLD(base)  ((DMA_ES_REG(base) & DMA_ES_VLD_MASK) >> DMA_ES_VLD_SHIFT)
+#define DMA_BRD_ES_VLD(base) (BITBAND_ACCESS32(&DMA_ES_REG(base), DMA_ES_VLD_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ERQ - Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ERQ - Enable Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERQ register provides a bit map for the 16 implemented channels to enable
+ * the request signal for each channel. The state of any given channel enable is
+ * directly affected by writes to this register; it is also affected by writes
+ * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
+ * for a single channel can easily be modified without needing to perform a
+ * read-modify-write sequence to the ERQ. DMA request input signals and this enable
+ * request flag must be asserted before a channel's hardware service request is
+ * accepted. The state of the DMA enable request flag does not affect a channel
+ * service request made explicitly through software or a linked channel request.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ERQ register
+ */
+/*@{*/
+#define DMA_RD_ERQ(base)         (DMA_ERQ_REG(base))
+#define DMA_WR_ERQ(base, value)  (DMA_ERQ_REG(base) = (value))
+#define DMA_RMW_ERQ(base, mask, value) (DMA_WR_ERQ(base, (DMA_RD_ERQ(base) & ~(mask)) | (value)))
+#define DMA_SET_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) |  (value)))
+#define DMA_CLR_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) & ~(value)))
+#define DMA_TOG_ERQ(base, value) (DMA_WR_ERQ(base, DMA_RD_ERQ(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_ERQ, field ERQ0[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ0 field. */
+#define DMA_RD_ERQ_ERQ0(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ0_MASK) >> DMA_ERQ_ERQ0_SHIFT)
+#define DMA_BRD_ERQ_ERQ0(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ0_SHIFT))
+
+/*! @brief Set the ERQ0 field to a new value. */
+#define DMA_WR_ERQ_ERQ0(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ0_MASK, DMA_ERQ_ERQ0(value)))
+#define DMA_BWR_ERQ_ERQ0(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ1[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ1 field. */
+#define DMA_RD_ERQ_ERQ1(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ1_MASK) >> DMA_ERQ_ERQ1_SHIFT)
+#define DMA_BRD_ERQ_ERQ1(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ1_SHIFT))
+
+/*! @brief Set the ERQ1 field to a new value. */
+#define DMA_WR_ERQ_ERQ1(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ1_MASK, DMA_ERQ_ERQ1(value)))
+#define DMA_BWR_ERQ_ERQ1(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ2[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ2 field. */
+#define DMA_RD_ERQ_ERQ2(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ2_MASK) >> DMA_ERQ_ERQ2_SHIFT)
+#define DMA_BRD_ERQ_ERQ2(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ2_SHIFT))
+
+/*! @brief Set the ERQ2 field to a new value. */
+#define DMA_WR_ERQ_ERQ2(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ2_MASK, DMA_ERQ_ERQ2(value)))
+#define DMA_BWR_ERQ_ERQ2(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ3[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ3 field. */
+#define DMA_RD_ERQ_ERQ3(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ3_MASK) >> DMA_ERQ_ERQ3_SHIFT)
+#define DMA_BRD_ERQ_ERQ3(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ3_SHIFT))
+
+/*! @brief Set the ERQ3 field to a new value. */
+#define DMA_WR_ERQ_ERQ3(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ3_MASK, DMA_ERQ_ERQ3(value)))
+#define DMA_BWR_ERQ_ERQ3(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ4[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ4 field. */
+#define DMA_RD_ERQ_ERQ4(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ4_MASK) >> DMA_ERQ_ERQ4_SHIFT)
+#define DMA_BRD_ERQ_ERQ4(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ4_SHIFT))
+
+/*! @brief Set the ERQ4 field to a new value. */
+#define DMA_WR_ERQ_ERQ4(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ4_MASK, DMA_ERQ_ERQ4(value)))
+#define DMA_BWR_ERQ_ERQ4(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ5[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ5 field. */
+#define DMA_RD_ERQ_ERQ5(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ5_MASK) >> DMA_ERQ_ERQ5_SHIFT)
+#define DMA_BRD_ERQ_ERQ5(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ5_SHIFT))
+
+/*! @brief Set the ERQ5 field to a new value. */
+#define DMA_WR_ERQ_ERQ5(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ5_MASK, DMA_ERQ_ERQ5(value)))
+#define DMA_BWR_ERQ_ERQ5(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ6[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ6 field. */
+#define DMA_RD_ERQ_ERQ6(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ6_MASK) >> DMA_ERQ_ERQ6_SHIFT)
+#define DMA_BRD_ERQ_ERQ6(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ6_SHIFT))
+
+/*! @brief Set the ERQ6 field to a new value. */
+#define DMA_WR_ERQ_ERQ6(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ6_MASK, DMA_ERQ_ERQ6(value)))
+#define DMA_BWR_ERQ_ERQ6(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ7[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ7 field. */
+#define DMA_RD_ERQ_ERQ7(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ7_MASK) >> DMA_ERQ_ERQ7_SHIFT)
+#define DMA_BRD_ERQ_ERQ7(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ7_SHIFT))
+
+/*! @brief Set the ERQ7 field to a new value. */
+#define DMA_WR_ERQ_ERQ7(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ7_MASK, DMA_ERQ_ERQ7(value)))
+#define DMA_BWR_ERQ_ERQ7(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ8[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ8 field. */
+#define DMA_RD_ERQ_ERQ8(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ8_MASK) >> DMA_ERQ_ERQ8_SHIFT)
+#define DMA_BRD_ERQ_ERQ8(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ8_SHIFT))
+
+/*! @brief Set the ERQ8 field to a new value. */
+#define DMA_WR_ERQ_ERQ8(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ8_MASK, DMA_ERQ_ERQ8(value)))
+#define DMA_BWR_ERQ_ERQ8(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ9[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ9 field. */
+#define DMA_RD_ERQ_ERQ9(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ9_MASK) >> DMA_ERQ_ERQ9_SHIFT)
+#define DMA_BRD_ERQ_ERQ9(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ9_SHIFT))
+
+/*! @brief Set the ERQ9 field to a new value. */
+#define DMA_WR_ERQ_ERQ9(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ9_MASK, DMA_ERQ_ERQ9(value)))
+#define DMA_BWR_ERQ_ERQ9(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ10[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ10 field. */
+#define DMA_RD_ERQ_ERQ10(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ10_MASK) >> DMA_ERQ_ERQ10_SHIFT)
+#define DMA_BRD_ERQ_ERQ10(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ10_SHIFT))
+
+/*! @brief Set the ERQ10 field to a new value. */
+#define DMA_WR_ERQ_ERQ10(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ10_MASK, DMA_ERQ_ERQ10(value)))
+#define DMA_BWR_ERQ_ERQ10(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ11[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ11 field. */
+#define DMA_RD_ERQ_ERQ11(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ11_MASK) >> DMA_ERQ_ERQ11_SHIFT)
+#define DMA_BRD_ERQ_ERQ11(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ11_SHIFT))
+
+/*! @brief Set the ERQ11 field to a new value. */
+#define DMA_WR_ERQ_ERQ11(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ11_MASK, DMA_ERQ_ERQ11(value)))
+#define DMA_BWR_ERQ_ERQ11(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ12[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ12 field. */
+#define DMA_RD_ERQ_ERQ12(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ12_MASK) >> DMA_ERQ_ERQ12_SHIFT)
+#define DMA_BRD_ERQ_ERQ12(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ12_SHIFT))
+
+/*! @brief Set the ERQ12 field to a new value. */
+#define DMA_WR_ERQ_ERQ12(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ12_MASK, DMA_ERQ_ERQ12(value)))
+#define DMA_BWR_ERQ_ERQ12(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ13[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ13 field. */
+#define DMA_RD_ERQ_ERQ13(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ13_MASK) >> DMA_ERQ_ERQ13_SHIFT)
+#define DMA_BRD_ERQ_ERQ13(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ13_SHIFT))
+
+/*! @brief Set the ERQ13 field to a new value. */
+#define DMA_WR_ERQ_ERQ13(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ13_MASK, DMA_ERQ_ERQ13(value)))
+#define DMA_BWR_ERQ_ERQ13(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ14[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ14 field. */
+#define DMA_RD_ERQ_ERQ14(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ14_MASK) >> DMA_ERQ_ERQ14_SHIFT)
+#define DMA_BRD_ERQ_ERQ14(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ14_SHIFT))
+
+/*! @brief Set the ERQ14 field to a new value. */
+#define DMA_WR_ERQ_ERQ14(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ14_MASK, DMA_ERQ_ERQ14(value)))
+#define DMA_BWR_ERQ_ERQ14(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERQ, field ERQ15[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The DMA request signal for the corresponding channel is disabled
+ * - 0b1 - The DMA request signal for the corresponding channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERQ_ERQ15 field. */
+#define DMA_RD_ERQ_ERQ15(base) ((DMA_ERQ_REG(base) & DMA_ERQ_ERQ15_MASK) >> DMA_ERQ_ERQ15_SHIFT)
+#define DMA_BRD_ERQ_ERQ15(base) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ15_SHIFT))
+
+/*! @brief Set the ERQ15 field to a new value. */
+#define DMA_WR_ERQ_ERQ15(base, value) (DMA_RMW_ERQ(base, DMA_ERQ_ERQ15_MASK, DMA_ERQ_ERQ15(value)))
+#define DMA_BWR_ERQ_ERQ15(base, value) (BITBAND_ACCESS32(&DMA_ERQ_REG(base), DMA_ERQ_ERQ15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_EEI - Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_EEI - Enable Error Interrupt Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The EEI register provides a bit map for the 16 channels to enable the error
+ * interrupt signal for each channel. The state of any given channel's error
+ * interrupt enable is directly affected by writes to this register; it is also
+ * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
+ * interrupt enable for a single channel can easily be modified without the need to
+ * perform a read-modify-write sequence to the EEI register. The DMA error
+ * indicator and the error interrupt enable flag must be asserted before an error
+ * interrupt request for a given channel is asserted to the interrupt controller.
+ */
+/*!
+ * @name Constants and macros for entire DMA_EEI register
+ */
+/*@{*/
+#define DMA_RD_EEI(base)         (DMA_EEI_REG(base))
+#define DMA_WR_EEI(base, value)  (DMA_EEI_REG(base) = (value))
+#define DMA_RMW_EEI(base, mask, value) (DMA_WR_EEI(base, (DMA_RD_EEI(base) & ~(mask)) | (value)))
+#define DMA_SET_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) |  (value)))
+#define DMA_CLR_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) & ~(value)))
+#define DMA_TOG_EEI(base, value) (DMA_WR_EEI(base, DMA_RD_EEI(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_EEI bitfields
+ */
+
+/*!
+ * @name Register DMA_EEI, field EEI0[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI0 field. */
+#define DMA_RD_EEI_EEI0(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI0_MASK) >> DMA_EEI_EEI0_SHIFT)
+#define DMA_BRD_EEI_EEI0(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI0_SHIFT))
+
+/*! @brief Set the EEI0 field to a new value. */
+#define DMA_WR_EEI_EEI0(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI0_MASK, DMA_EEI_EEI0(value)))
+#define DMA_BWR_EEI_EEI0(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI1[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI1 field. */
+#define DMA_RD_EEI_EEI1(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI1_MASK) >> DMA_EEI_EEI1_SHIFT)
+#define DMA_BRD_EEI_EEI1(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI1_SHIFT))
+
+/*! @brief Set the EEI1 field to a new value. */
+#define DMA_WR_EEI_EEI1(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI1_MASK, DMA_EEI_EEI1(value)))
+#define DMA_BWR_EEI_EEI1(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI2[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI2 field. */
+#define DMA_RD_EEI_EEI2(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI2_MASK) >> DMA_EEI_EEI2_SHIFT)
+#define DMA_BRD_EEI_EEI2(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI2_SHIFT))
+
+/*! @brief Set the EEI2 field to a new value. */
+#define DMA_WR_EEI_EEI2(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI2_MASK, DMA_EEI_EEI2(value)))
+#define DMA_BWR_EEI_EEI2(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI3[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI3 field. */
+#define DMA_RD_EEI_EEI3(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI3_MASK) >> DMA_EEI_EEI3_SHIFT)
+#define DMA_BRD_EEI_EEI3(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI3_SHIFT))
+
+/*! @brief Set the EEI3 field to a new value. */
+#define DMA_WR_EEI_EEI3(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI3_MASK, DMA_EEI_EEI3(value)))
+#define DMA_BWR_EEI_EEI3(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI4[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI4 field. */
+#define DMA_RD_EEI_EEI4(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI4_MASK) >> DMA_EEI_EEI4_SHIFT)
+#define DMA_BRD_EEI_EEI4(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI4_SHIFT))
+
+/*! @brief Set the EEI4 field to a new value. */
+#define DMA_WR_EEI_EEI4(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI4_MASK, DMA_EEI_EEI4(value)))
+#define DMA_BWR_EEI_EEI4(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI5[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI5 field. */
+#define DMA_RD_EEI_EEI5(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI5_MASK) >> DMA_EEI_EEI5_SHIFT)
+#define DMA_BRD_EEI_EEI5(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI5_SHIFT))
+
+/*! @brief Set the EEI5 field to a new value. */
+#define DMA_WR_EEI_EEI5(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI5_MASK, DMA_EEI_EEI5(value)))
+#define DMA_BWR_EEI_EEI5(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI6[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI6 field. */
+#define DMA_RD_EEI_EEI6(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI6_MASK) >> DMA_EEI_EEI6_SHIFT)
+#define DMA_BRD_EEI_EEI6(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI6_SHIFT))
+
+/*! @brief Set the EEI6 field to a new value. */
+#define DMA_WR_EEI_EEI6(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI6_MASK, DMA_EEI_EEI6(value)))
+#define DMA_BWR_EEI_EEI6(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI7[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI7 field. */
+#define DMA_RD_EEI_EEI7(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI7_MASK) >> DMA_EEI_EEI7_SHIFT)
+#define DMA_BRD_EEI_EEI7(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI7_SHIFT))
+
+/*! @brief Set the EEI7 field to a new value. */
+#define DMA_WR_EEI_EEI7(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI7_MASK, DMA_EEI_EEI7(value)))
+#define DMA_BWR_EEI_EEI7(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI8[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI8 field. */
+#define DMA_RD_EEI_EEI8(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI8_MASK) >> DMA_EEI_EEI8_SHIFT)
+#define DMA_BRD_EEI_EEI8(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI8_SHIFT))
+
+/*! @brief Set the EEI8 field to a new value. */
+#define DMA_WR_EEI_EEI8(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI8_MASK, DMA_EEI_EEI8(value)))
+#define DMA_BWR_EEI_EEI8(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI9[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI9 field. */
+#define DMA_RD_EEI_EEI9(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI9_MASK) >> DMA_EEI_EEI9_SHIFT)
+#define DMA_BRD_EEI_EEI9(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI9_SHIFT))
+
+/*! @brief Set the EEI9 field to a new value. */
+#define DMA_WR_EEI_EEI9(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI9_MASK, DMA_EEI_EEI9(value)))
+#define DMA_BWR_EEI_EEI9(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI10[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI10 field. */
+#define DMA_RD_EEI_EEI10(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI10_MASK) >> DMA_EEI_EEI10_SHIFT)
+#define DMA_BRD_EEI_EEI10(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI10_SHIFT))
+
+/*! @brief Set the EEI10 field to a new value. */
+#define DMA_WR_EEI_EEI10(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI10_MASK, DMA_EEI_EEI10(value)))
+#define DMA_BWR_EEI_EEI10(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI11[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI11 field. */
+#define DMA_RD_EEI_EEI11(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI11_MASK) >> DMA_EEI_EEI11_SHIFT)
+#define DMA_BRD_EEI_EEI11(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI11_SHIFT))
+
+/*! @brief Set the EEI11 field to a new value. */
+#define DMA_WR_EEI_EEI11(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI11_MASK, DMA_EEI_EEI11(value)))
+#define DMA_BWR_EEI_EEI11(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI12[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI12 field. */
+#define DMA_RD_EEI_EEI12(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI12_MASK) >> DMA_EEI_EEI12_SHIFT)
+#define DMA_BRD_EEI_EEI12(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI12_SHIFT))
+
+/*! @brief Set the EEI12 field to a new value. */
+#define DMA_WR_EEI_EEI12(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI12_MASK, DMA_EEI_EEI12(value)))
+#define DMA_BWR_EEI_EEI12(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI13[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI13 field. */
+#define DMA_RD_EEI_EEI13(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI13_MASK) >> DMA_EEI_EEI13_SHIFT)
+#define DMA_BRD_EEI_EEI13(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI13_SHIFT))
+
+/*! @brief Set the EEI13 field to a new value. */
+#define DMA_WR_EEI_EEI13(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI13_MASK, DMA_EEI_EEI13(value)))
+#define DMA_BWR_EEI_EEI13(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI14[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI14 field. */
+#define DMA_RD_EEI_EEI14(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI14_MASK) >> DMA_EEI_EEI14_SHIFT)
+#define DMA_BRD_EEI_EEI14(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI14_SHIFT))
+
+/*! @brief Set the EEI14 field to a new value. */
+#define DMA_WR_EEI_EEI14(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI14_MASK, DMA_EEI_EEI14(value)))
+#define DMA_BWR_EEI_EEI14(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_EEI, field EEI15[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The error signal for corresponding channel does not generate an error
+ *     interrupt
+ * - 0b1 - The assertion of the error signal for corresponding channel generates
+ *     an error interrupt request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_EEI_EEI15 field. */
+#define DMA_RD_EEI_EEI15(base) ((DMA_EEI_REG(base) & DMA_EEI_EEI15_MASK) >> DMA_EEI_EEI15_SHIFT)
+#define DMA_BRD_EEI_EEI15(base) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI15_SHIFT))
+
+/*! @brief Set the EEI15 field to a new value. */
+#define DMA_WR_EEI_EEI15(base, value) (DMA_RMW_EEI(base, DMA_EEI_EEI15_MASK, DMA_EEI_EEI15(value)))
+#define DMA_BWR_EEI_EEI15(base, value) (BITBAND_ACCESS32(&DMA_EEI_REG(base), DMA_EEI_EEI15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CEEI - Clear Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CEEI - Clear Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
+ * the EEI to disable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be cleared. Setting
+ * the CAEE bit provides a global clear function, forcing the EEI contents to be
+ * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
+ * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
+ * Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CEEI register
+ */
+/*@{*/
+#define DMA_RD_CEEI(base)        (DMA_CEEI_REG(base))
+#define DMA_WR_CEEI(base, value) (DMA_CEEI_REG(base) = (value))
+#define DMA_RMW_CEEI(base, mask, value) (DMA_WR_CEEI(base, (DMA_RD_CEEI(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in EEI
+ */
+/*@{*/
+/*! @brief Set the CEEI field to a new value. */
+#define DMA_WR_CEEI_CEEI(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_CEEI_MASK, DMA_CEEI_CEEI(value)))
+#define DMA_BWR_CEEI_CEEI(base, value) (DMA_WR_CEEI_CEEI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CEEI, field CAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the EEI bit specified in the CEEI field
+ * - 0b1 - Clear all bits in EEI
+ */
+/*@{*/
+/*! @brief Set the CAEE field to a new value. */
+#define DMA_WR_CEEI_CAEE(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_CAEE_MASK, DMA_CEEI_CAEE(value)))
+#define DMA_BWR_CEEI_CAEE(base, value) (BITBAND_ACCESS8(&DMA_CEEI_REG(base), DMA_CEEI_CAEE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CEEI_NOP(base, value) (DMA_RMW_CEEI(base, DMA_CEEI_NOP_MASK, DMA_CEEI_NOP(value)))
+#define DMA_BWR_CEEI_NOP(base, value) (BITBAND_ACCESS8(&DMA_CEEI_REG(base), DMA_CEEI_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SEEI - Set Enable Error Interrupt Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SEEI - Set Enable Error Interrupt Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
+ * EEI to enable the error interrupt for a given channel. The data value on a
+ * register write causes the corresponding bit in the EEI to be set. Setting the
+ * SAEE bit provides a global set function, forcing the entire EEI contents to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SEEI register
+ */
+/*@{*/
+#define DMA_RD_SEEI(base)        (DMA_SEEI_REG(base))
+#define DMA_WR_SEEI(base, value) (DMA_SEEI_REG(base) = (value))
+#define DMA_RMW_SEEI(base, mask, value) (DMA_WR_SEEI(base, (DMA_RD_SEEI(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SEEI bitfields
+ */
+
+/*!
+ * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in EEI
+ */
+/*@{*/
+/*! @brief Set the SEEI field to a new value. */
+#define DMA_WR_SEEI_SEEI(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_SEEI_MASK, DMA_SEEI_SEEI(value)))
+#define DMA_BWR_SEEI_SEEI(base, value) (DMA_WR_SEEI_SEEI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SEEI, field SAEE[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the EEI bit specified in the SEEI field.
+ * - 0b1 - Sets all bits in EEI
+ */
+/*@{*/
+/*! @brief Set the SAEE field to a new value. */
+#define DMA_WR_SEEI_SAEE(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_SAEE_MASK, DMA_SEEI_SAEE(value)))
+#define DMA_BWR_SEEI_SAEE(base, value) (BITBAND_ACCESS8(&DMA_SEEI_REG(base), DMA_SEEI_SAEE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SEEI, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SEEI_NOP(base, value) (DMA_RMW_SEEI(base, DMA_SEEI_NOP_MASK, DMA_SEEI_NOP(value)))
+#define DMA_BWR_SEEI_NOP(base, value) (BITBAND_ACCESS8(&DMA_SEEI_REG(base), DMA_SEEI_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CERQ - Clear Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CERQ - Clear Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERQ to disable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be cleared. Setting the
+ * CAER bit provides a global clear function, forcing the entire contents of the
+ * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
+ * command is ignored. This allows you to write multiple-byte registers as a 32-bit
+ * word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CERQ register
+ */
+/*@{*/
+#define DMA_RD_CERQ(base)        (DMA_CERQ_REG(base))
+#define DMA_WR_CERQ(base, value) (DMA_CERQ_REG(base) = (value))
+#define DMA_RMW_CERQ(base, mask, value) (DMA_WR_CERQ(base, (DMA_RD_CERQ(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERQ
+ */
+/*@{*/
+/*! @brief Set the CERQ field to a new value. */
+#define DMA_WR_CERQ_CERQ(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_CERQ_MASK, DMA_CERQ_CERQ(value)))
+#define DMA_BWR_CERQ_CERQ(base, value) (DMA_WR_CERQ_CERQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERQ, field CAER[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the ERQ bit specified in the CERQ field
+ * - 0b1 - Clear all bits in ERQ
+ */
+/*@{*/
+/*! @brief Set the CAER field to a new value. */
+#define DMA_WR_CERQ_CAER(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_CAER_MASK, DMA_CERQ_CAER(value)))
+#define DMA_BWR_CERQ_CAER(base, value) (BITBAND_ACCESS8(&DMA_CERQ_REG(base), DMA_CERQ_CAER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CERQ_NOP(base, value) (DMA_RMW_CERQ(base, DMA_CERQ_NOP_MASK, DMA_CERQ_NOP(value)))
+#define DMA_BWR_CERQ_NOP(base, value) (BITBAND_ACCESS8(&DMA_CERQ_REG(base), DMA_CERQ_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SERQ - Set Enable Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SERQ - Set Enable Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
+ * ERQ to enable the DMA request for a given channel. The data value on a
+ * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
+ * bit provides a global set function, forcing the entire contents of ERQ to be
+ * set. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SERQ register
+ */
+/*@{*/
+#define DMA_RD_SERQ(base)        (DMA_SERQ_REG(base))
+#define DMA_WR_SERQ(base, value) (DMA_SERQ_REG(base) = (value))
+#define DMA_RMW_SERQ(base, mask, value) (DMA_WR_SERQ(base, (DMA_RD_SERQ(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SERQ bitfields
+ */
+
+/*!
+ * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in ERQ
+ */
+/*@{*/
+/*! @brief Set the SERQ field to a new value. */
+#define DMA_WR_SERQ_SERQ(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_SERQ_MASK, DMA_SERQ_SERQ(value)))
+#define DMA_BWR_SERQ_SERQ(base, value) (DMA_WR_SERQ_SERQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SERQ, field SAER[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the ERQ bit specified in the SERQ field
+ * - 0b1 - Set all bits in ERQ
+ */
+/*@{*/
+/*! @brief Set the SAER field to a new value. */
+#define DMA_WR_SERQ_SAER(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_SAER_MASK, DMA_SERQ_SAER(value)))
+#define DMA_BWR_SERQ_SAER(base, value) (BITBAND_ACCESS8(&DMA_SERQ_REG(base), DMA_SERQ_SAER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SERQ, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SERQ_NOP(base, value) (DMA_RMW_SERQ(base, DMA_SERQ_NOP_MASK, DMA_SERQ_NOP(value)))
+#define DMA_BWR_SERQ_NOP(base, value) (BITBAND_ACCESS8(&DMA_SERQ_REG(base), DMA_SERQ_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CDNE - Clear DONE Status Bit Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CDNE - Clear DONE Status Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
+ * the CADN bit provides a global clear function, forcing all DONE bits to be
+ * cleared. If the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all
+ * zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CDNE register
+ */
+/*@{*/
+#define DMA_RD_CDNE(base)        (DMA_CDNE_REG(base))
+#define DMA_WR_CDNE(base, value) (DMA_CDNE_REG(base) = (value))
+#define DMA_RMW_CDNE(base, mask, value) (DMA_WR_CDNE(base, (DMA_RD_CDNE(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CDNE bitfields
+ */
+
+/*!
+ * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in TCDn_CSR[DONE]
+ */
+/*@{*/
+/*! @brief Set the CDNE field to a new value. */
+#define DMA_WR_CDNE_CDNE(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_CDNE_MASK, DMA_CDNE_CDNE(value)))
+#define DMA_BWR_CDNE_CDNE(base, value) (DMA_WR_CDNE_CDNE(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CDNE, field CADN[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
+ * - 0b1 - Clears all bits in TCDn_CSR[DONE]
+ */
+/*@{*/
+/*! @brief Set the CADN field to a new value. */
+#define DMA_WR_CDNE_CADN(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_CADN_MASK, DMA_CDNE_CADN(value)))
+#define DMA_BWR_CDNE_CADN(base, value) (BITBAND_ACCESS8(&DMA_CDNE_REG(base), DMA_CDNE_CADN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CDNE, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CDNE_NOP(base, value) (DMA_RMW_CDNE(base, DMA_CDNE_NOP_MASK, DMA_CDNE_NOP(value)))
+#define DMA_BWR_CDNE_NOP(base, value) (BITBAND_ACCESS8(&DMA_CDNE_REG(base), DMA_CDNE_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SSRT - Set START Bit Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SSRT - Set START Bit Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The SSRT provides a simple memory-mapped mechanism to set the START bit in
+ * the TCD of the given channel. The data value on a register write causes the
+ * START bit in the corresponding transfer control descriptor to be set. Setting the
+ * SAST bit provides a global set function, forcing all START bits to be set. If
+ * the NOP bit is set, the command is ignored. This allows you to write
+ * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_SSRT register
+ */
+/*@{*/
+#define DMA_RD_SSRT(base)        (DMA_SSRT_REG(base))
+#define DMA_WR_SSRT(base, value) (DMA_SSRT_REG(base) = (value))
+#define DMA_RMW_SSRT(base, mask, value) (DMA_WR_SSRT(base, (DMA_RD_SSRT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_SSRT bitfields
+ */
+
+/*!
+ * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
+ *
+ * Sets the corresponding bit in TCDn_CSR[START]
+ */
+/*@{*/
+/*! @brief Set the SSRT field to a new value. */
+#define DMA_WR_SSRT_SSRT(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_SSRT_MASK, DMA_SSRT_SSRT(value)))
+#define DMA_BWR_SSRT_SSRT(base, value) (DMA_WR_SSRT_SSRT(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SSRT, field SAST[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
+ * - 0b1 - Set all bits in TCDn_CSR[START]
+ */
+/*@{*/
+/*! @brief Set the SAST field to a new value. */
+#define DMA_WR_SSRT_SAST(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_SAST_MASK, DMA_SSRT_SAST(value)))
+#define DMA_BWR_SSRT_SAST(base, value) (BITBAND_ACCESS8(&DMA_SSRT_REG(base), DMA_SSRT_SAST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_SSRT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_SSRT_NOP(base, value) (DMA_RMW_SSRT(base, DMA_SSRT_NOP_MASK, DMA_SSRT_NOP(value)))
+#define DMA_BWR_SSRT_NOP(base, value) (BITBAND_ACCESS8(&DMA_SSRT_REG(base), DMA_SSRT_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CERR - Clear Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CERR - Clear Error Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CERR provides a simple memory-mapped mechanism to clear a given bit in
+ * the ERR to disable the error condition flag for a given channel. The given value
+ * on a register write causes the corresponding bit in the ERR to be cleared.
+ * Setting the CAEI bit provides a global clear function, forcing the ERR contents
+ * to be cleared, clearing all channel error indicators. If the NOP bit is set,
+ * the command is ignored. This allows you to write multiple-byte registers as a
+ * 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CERR register
+ */
+/*@{*/
+#define DMA_RD_CERR(base)        (DMA_CERR_REG(base))
+#define DMA_WR_CERR(base, value) (DMA_CERR_REG(base) = (value))
+#define DMA_RMW_CERR(base, mask, value) (DMA_WR_CERR(base, (DMA_RD_CERR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CERR bitfields
+ */
+
+/*!
+ * @name Register DMA_CERR, field CERR[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in ERR
+ */
+/*@{*/
+/*! @brief Set the CERR field to a new value. */
+#define DMA_WR_CERR_CERR(base, value) (DMA_RMW_CERR(base, DMA_CERR_CERR_MASK, DMA_CERR_CERR(value)))
+#define DMA_BWR_CERR_CERR(base, value) (DMA_WR_CERR_CERR(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERR, field CAEI[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the ERR bit specified in the CERR field
+ * - 0b1 - Clear all bits in ERR
+ */
+/*@{*/
+/*! @brief Set the CAEI field to a new value. */
+#define DMA_WR_CERR_CAEI(base, value) (DMA_RMW_CERR(base, DMA_CERR_CAEI_MASK, DMA_CERR_CAEI(value)))
+#define DMA_BWR_CERR_CAEI(base, value) (BITBAND_ACCESS8(&DMA_CERR_REG(base), DMA_CERR_CAEI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CERR, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CERR_NOP(base, value) (DMA_RMW_CERR(base, DMA_CERR_NOP_MASK, DMA_CERR_NOP(value)))
+#define DMA_BWR_CERR_NOP(base, value) (BITBAND_ACCESS8(&DMA_CERR_REG(base), DMA_CERR_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CINT - Clear Interrupt Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CINT - Clear Interrupt Request Register (WO)
+ *
+ * Reset value: 0x00U
+ *
+ * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
+ * the INT to disable the interrupt request for a given channel. The given value
+ * on a register write causes the corresponding bit in the INT to be cleared.
+ * Setting the CAIR bit provides a global clear function, forcing the entire contents
+ * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
+ * bit is set, the command is ignored. This allows you to write multiple-byte
+ * registers as a 32-bit word. Reads of this register return all zeroes.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CINT register
+ */
+/*@{*/
+#define DMA_RD_CINT(base)        (DMA_CINT_REG(base))
+#define DMA_WR_CINT(base, value) (DMA_CINT_REG(base) = (value))
+#define DMA_RMW_CINT(base, mask, value) (DMA_WR_CINT(base, (DMA_RD_CINT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CINT bitfields
+ */
+
+/*!
+ * @name Register DMA_CINT, field CINT[3:0] (WORZ)
+ *
+ * Clears the corresponding bit in INT
+ */
+/*@{*/
+/*! @brief Set the CINT field to a new value. */
+#define DMA_WR_CINT_CINT(base, value) (DMA_RMW_CINT(base, DMA_CINT_CINT_MASK, DMA_CINT_CINT(value)))
+#define DMA_BWR_CINT_CINT(base, value) (DMA_WR_CINT_CINT(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CINT, field CAIR[6] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Clear only the INT bit specified in the CINT field
+ * - 0b1 - Clear all bits in INT
+ */
+/*@{*/
+/*! @brief Set the CAIR field to a new value. */
+#define DMA_WR_CINT_CAIR(base, value) (DMA_RMW_CINT(base, DMA_CINT_CAIR_MASK, DMA_CINT_CAIR(value)))
+#define DMA_BWR_CINT_CAIR(base, value) (BITBAND_ACCESS8(&DMA_CINT_REG(base), DMA_CINT_CAIR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CINT, field NOP[7] (WORZ)
+ *
+ * Values:
+ * - 0b0 - Normal operation
+ * - 0b1 - No operation, ignore the other bits in this register
+ */
+/*@{*/
+/*! @brief Set the NOP field to a new value. */
+#define DMA_WR_CINT_NOP(base, value) (DMA_RMW_CINT(base, DMA_CINT_NOP_MASK, DMA_CINT_NOP(value)))
+#define DMA_BWR_CINT_NOP(base, value) (BITBAND_ACCESS8(&DMA_CINT_REG(base), DMA_CINT_NOP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_INT - Interrupt Request Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_INT - Interrupt Request Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The INT register provides a bit map for the 16 channels signaling the
+ * presence of an interrupt request for each channel. Depending on the appropriate bit
+ * setting in the transfer-control descriptors, the eDMA engine generates an
+ * interrupt on data transfer completion. The outputs of this register are directly
+ * routed to the interrupt controller (INTC). During the interrupt-service routine
+ * associated with any given channel, it is the software's responsibility to
+ * clear the appropriate bit, negating the interrupt request. Typically, a write to
+ * the CINT register in the interrupt service routine is used for this purpose.
+ * The state of any given channel's interrupt request is directly affected by
+ * writes to this register; it is also affected by writes to the CINT register. On
+ * writes to INT, a 1 in any bit position clears the corresponding channel's
+ * interrupt request. A zero in any bit position has no affect on the corresponding
+ * channel's current interrupt status. The CINT register is provided so the interrupt
+ * request for a single channel can easily be cleared without the need to
+ * perform a read-modify-write sequence to the INT register.
+ */
+/*!
+ * @name Constants and macros for entire DMA_INT register
+ */
+/*@{*/
+#define DMA_RD_INT(base)         (DMA_INT_REG(base))
+#define DMA_WR_INT(base, value)  (DMA_INT_REG(base) = (value))
+#define DMA_RMW_INT(base, mask, value) (DMA_WR_INT(base, (DMA_RD_INT(base) & ~(mask)) | (value)))
+#define DMA_SET_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) |  (value)))
+#define DMA_CLR_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) & ~(value)))
+#define DMA_TOG_INT(base, value) (DMA_WR_INT(base, DMA_RD_INT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_INT bitfields
+ */
+
+/*!
+ * @name Register DMA_INT, field INT0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT0 field. */
+#define DMA_RD_INT_INT0(base) ((DMA_INT_REG(base) & DMA_INT_INT0_MASK) >> DMA_INT_INT0_SHIFT)
+#define DMA_BRD_INT_INT0(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT0_SHIFT))
+
+/*! @brief Set the INT0 field to a new value. */
+#define DMA_WR_INT_INT0(base, value) (DMA_RMW_INT(base, (DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT0(value)))
+#define DMA_BWR_INT_INT0(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT1 field. */
+#define DMA_RD_INT_INT1(base) ((DMA_INT_REG(base) & DMA_INT_INT1_MASK) >> DMA_INT_INT1_SHIFT)
+#define DMA_BRD_INT_INT1(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT1_SHIFT))
+
+/*! @brief Set the INT1 field to a new value. */
+#define DMA_WR_INT_INT1(base, value) (DMA_RMW_INT(base, (DMA_INT_INT1_MASK | DMA_INT_INT0_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT1(value)))
+#define DMA_BWR_INT_INT1(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT2 field. */
+#define DMA_RD_INT_INT2(base) ((DMA_INT_REG(base) & DMA_INT_INT2_MASK) >> DMA_INT_INT2_SHIFT)
+#define DMA_BRD_INT_INT2(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT2_SHIFT))
+
+/*! @brief Set the INT2 field to a new value. */
+#define DMA_WR_INT_INT2(base, value) (DMA_RMW_INT(base, (DMA_INT_INT2_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT2(value)))
+#define DMA_BWR_INT_INT2(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT3 field. */
+#define DMA_RD_INT_INT3(base) ((DMA_INT_REG(base) & DMA_INT_INT3_MASK) >> DMA_INT_INT3_SHIFT)
+#define DMA_BRD_INT_INT3(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT3_SHIFT))
+
+/*! @brief Set the INT3 field to a new value. */
+#define DMA_WR_INT_INT3(base, value) (DMA_RMW_INT(base, (DMA_INT_INT3_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT3(value)))
+#define DMA_BWR_INT_INT3(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT4[4] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT4 field. */
+#define DMA_RD_INT_INT4(base) ((DMA_INT_REG(base) & DMA_INT_INT4_MASK) >> DMA_INT_INT4_SHIFT)
+#define DMA_BRD_INT_INT4(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT4_SHIFT))
+
+/*! @brief Set the INT4 field to a new value. */
+#define DMA_WR_INT_INT4(base, value) (DMA_RMW_INT(base, (DMA_INT_INT4_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT4(value)))
+#define DMA_BWR_INT_INT4(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT5[5] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT5 field. */
+#define DMA_RD_INT_INT5(base) ((DMA_INT_REG(base) & DMA_INT_INT5_MASK) >> DMA_INT_INT5_SHIFT)
+#define DMA_BRD_INT_INT5(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT5_SHIFT))
+
+/*! @brief Set the INT5 field to a new value. */
+#define DMA_WR_INT_INT5(base, value) (DMA_RMW_INT(base, (DMA_INT_INT5_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT5(value)))
+#define DMA_BWR_INT_INT5(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT6[6] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT6 field. */
+#define DMA_RD_INT_INT6(base) ((DMA_INT_REG(base) & DMA_INT_INT6_MASK) >> DMA_INT_INT6_SHIFT)
+#define DMA_BRD_INT_INT6(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT6_SHIFT))
+
+/*! @brief Set the INT6 field to a new value. */
+#define DMA_WR_INT_INT6(base, value) (DMA_RMW_INT(base, (DMA_INT_INT6_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT6(value)))
+#define DMA_BWR_INT_INT6(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT7[7] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT7 field. */
+#define DMA_RD_INT_INT7(base) ((DMA_INT_REG(base) & DMA_INT_INT7_MASK) >> DMA_INT_INT7_SHIFT)
+#define DMA_BRD_INT_INT7(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT7_SHIFT))
+
+/*! @brief Set the INT7 field to a new value. */
+#define DMA_WR_INT_INT7(base, value) (DMA_RMW_INT(base, (DMA_INT_INT7_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT7(value)))
+#define DMA_BWR_INT_INT7(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT8[8] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT8 field. */
+#define DMA_RD_INT_INT8(base) ((DMA_INT_REG(base) & DMA_INT_INT8_MASK) >> DMA_INT_INT8_SHIFT)
+#define DMA_BRD_INT_INT8(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT8_SHIFT))
+
+/*! @brief Set the INT8 field to a new value. */
+#define DMA_WR_INT_INT8(base, value) (DMA_RMW_INT(base, (DMA_INT_INT8_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT8(value)))
+#define DMA_BWR_INT_INT8(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT9[9] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT9 field. */
+#define DMA_RD_INT_INT9(base) ((DMA_INT_REG(base) & DMA_INT_INT9_MASK) >> DMA_INT_INT9_SHIFT)
+#define DMA_BRD_INT_INT9(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT9_SHIFT))
+
+/*! @brief Set the INT9 field to a new value. */
+#define DMA_WR_INT_INT9(base, value) (DMA_RMW_INT(base, (DMA_INT_INT9_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT9(value)))
+#define DMA_BWR_INT_INT9(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT10[10] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT10 field. */
+#define DMA_RD_INT_INT10(base) ((DMA_INT_REG(base) & DMA_INT_INT10_MASK) >> DMA_INT_INT10_SHIFT)
+#define DMA_BRD_INT_INT10(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT10_SHIFT))
+
+/*! @brief Set the INT10 field to a new value. */
+#define DMA_WR_INT_INT10(base, value) (DMA_RMW_INT(base, (DMA_INT_INT10_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT10(value)))
+#define DMA_BWR_INT_INT10(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT11[11] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT11 field. */
+#define DMA_RD_INT_INT11(base) ((DMA_INT_REG(base) & DMA_INT_INT11_MASK) >> DMA_INT_INT11_SHIFT)
+#define DMA_BRD_INT_INT11(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT11_SHIFT))
+
+/*! @brief Set the INT11 field to a new value. */
+#define DMA_WR_INT_INT11(base, value) (DMA_RMW_INT(base, (DMA_INT_INT11_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT11(value)))
+#define DMA_BWR_INT_INT11(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT12[12] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT12 field. */
+#define DMA_RD_INT_INT12(base) ((DMA_INT_REG(base) & DMA_INT_INT12_MASK) >> DMA_INT_INT12_SHIFT)
+#define DMA_BRD_INT_INT12(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT12_SHIFT))
+
+/*! @brief Set the INT12 field to a new value. */
+#define DMA_WR_INT_INT12(base, value) (DMA_RMW_INT(base, (DMA_INT_INT12_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT12(value)))
+#define DMA_BWR_INT_INT12(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT13[13] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT13 field. */
+#define DMA_RD_INT_INT13(base) ((DMA_INT_REG(base) & DMA_INT_INT13_MASK) >> DMA_INT_INT13_SHIFT)
+#define DMA_BRD_INT_INT13(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT13_SHIFT))
+
+/*! @brief Set the INT13 field to a new value. */
+#define DMA_WR_INT_INT13(base, value) (DMA_RMW_INT(base, (DMA_INT_INT13_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT14_MASK | DMA_INT_INT15_MASK), DMA_INT_INT13(value)))
+#define DMA_BWR_INT_INT13(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT14[14] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT14 field. */
+#define DMA_RD_INT_INT14(base) ((DMA_INT_REG(base) & DMA_INT_INT14_MASK) >> DMA_INT_INT14_SHIFT)
+#define DMA_BRD_INT_INT14(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT14_SHIFT))
+
+/*! @brief Set the INT14 field to a new value. */
+#define DMA_WR_INT_INT14(base, value) (DMA_RMW_INT(base, (DMA_INT_INT14_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT15_MASK), DMA_INT_INT14(value)))
+#define DMA_BWR_INT_INT14(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_INT, field INT15[15] (W1C)
+ *
+ * Values:
+ * - 0b0 - The interrupt request for corresponding channel is cleared
+ * - 0b1 - The interrupt request for corresponding channel is active
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_INT_INT15 field. */
+#define DMA_RD_INT_INT15(base) ((DMA_INT_REG(base) & DMA_INT_INT15_MASK) >> DMA_INT_INT15_SHIFT)
+#define DMA_BRD_INT_INT15(base) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT15_SHIFT))
+
+/*! @brief Set the INT15 field to a new value. */
+#define DMA_WR_INT_INT15(base, value) (DMA_RMW_INT(base, (DMA_INT_INT15_MASK | DMA_INT_INT0_MASK | DMA_INT_INT1_MASK | DMA_INT_INT2_MASK | DMA_INT_INT3_MASK | DMA_INT_INT4_MASK | DMA_INT_INT5_MASK | DMA_INT_INT6_MASK | DMA_INT_INT7_MASK | DMA_INT_INT8_MASK | DMA_INT_INT9_MASK | DMA_INT_INT10_MASK | DMA_INT_INT11_MASK | DMA_INT_INT12_MASK | DMA_INT_INT13_MASK | DMA_INT_INT14_MASK), DMA_INT_INT15(value)))
+#define DMA_BWR_INT_INT15(base, value) (BITBAND_ACCESS32(&DMA_INT_REG(base), DMA_INT_INT15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ERR - Error Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ERR - Error Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The ERR provides a bit map for the 16 channels, signaling the presence of an
+ * error for each channel. The eDMA engine signals the occurrence of an error
+ * condition by setting the appropriate bit in this register. The outputs of this
+ * register are enabled by the contents of the EEI, and then routed to the
+ * interrupt controller. During the execution of the interrupt-service routine associated
+ * with any DMA errors, it is software's responsibility to clear the appropriate
+ * bit, negating the error-interrupt request. Typically, a write to the CERR in
+ * the interrupt-service routine is used for this purpose. The normal DMA channel
+ * completion indicators (setting the transfer control descriptor DONE flag and
+ * the possible assertion of an interrupt request) are not affected when an error
+ * is detected. The contents of this register can also be polled because a
+ * non-zero value indicates the presence of a channel error regardless of the state of
+ * the EEI. The state of any given channel's error indicators is affected by
+ * writes to this register; it is also affected by writes to the CERR. On writes to
+ * the ERR, a one in any bit position clears the corresponding channel's error
+ * status. A zero in any bit position has no affect on the corresponding channel's
+ * current error status. The CERR is provided so the error indicator for a single
+ * channel can easily be cleared.
+ */
+/*!
+ * @name Constants and macros for entire DMA_ERR register
+ */
+/*@{*/
+#define DMA_RD_ERR(base)         (DMA_ERR_REG(base))
+#define DMA_WR_ERR(base, value)  (DMA_ERR_REG(base) = (value))
+#define DMA_RMW_ERR(base, mask, value) (DMA_WR_ERR(base, (DMA_RD_ERR(base) & ~(mask)) | (value)))
+#define DMA_SET_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) |  (value)))
+#define DMA_CLR_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) & ~(value)))
+#define DMA_TOG_ERR(base, value) (DMA_WR_ERR(base, DMA_RD_ERR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ERR bitfields
+ */
+
+/*!
+ * @name Register DMA_ERR, field ERR0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR0 field. */
+#define DMA_RD_ERR_ERR0(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR0_MASK) >> DMA_ERR_ERR0_SHIFT)
+#define DMA_BRD_ERR_ERR0(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR0_SHIFT))
+
+/*! @brief Set the ERR0 field to a new value. */
+#define DMA_WR_ERR_ERR0(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR0(value)))
+#define DMA_BWR_ERR_ERR0(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR1 field. */
+#define DMA_RD_ERR_ERR1(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR1_MASK) >> DMA_ERR_ERR1_SHIFT)
+#define DMA_BRD_ERR_ERR1(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR1_SHIFT))
+
+/*! @brief Set the ERR1 field to a new value. */
+#define DMA_WR_ERR_ERR1(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR1_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR1(value)))
+#define DMA_BWR_ERR_ERR1(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR2 field. */
+#define DMA_RD_ERR_ERR2(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR2_MASK) >> DMA_ERR_ERR2_SHIFT)
+#define DMA_BRD_ERR_ERR2(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR2_SHIFT))
+
+/*! @brief Set the ERR2 field to a new value. */
+#define DMA_WR_ERR_ERR2(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR2_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR2(value)))
+#define DMA_BWR_ERR_ERR2(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR3 field. */
+#define DMA_RD_ERR_ERR3(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR3_MASK) >> DMA_ERR_ERR3_SHIFT)
+#define DMA_BRD_ERR_ERR3(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR3_SHIFT))
+
+/*! @brief Set the ERR3 field to a new value. */
+#define DMA_WR_ERR_ERR3(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR3_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR3(value)))
+#define DMA_BWR_ERR_ERR3(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR4[4] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR4 field. */
+#define DMA_RD_ERR_ERR4(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR4_MASK) >> DMA_ERR_ERR4_SHIFT)
+#define DMA_BRD_ERR_ERR4(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR4_SHIFT))
+
+/*! @brief Set the ERR4 field to a new value. */
+#define DMA_WR_ERR_ERR4(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR4_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR4(value)))
+#define DMA_BWR_ERR_ERR4(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR5[5] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR5 field. */
+#define DMA_RD_ERR_ERR5(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR5_MASK) >> DMA_ERR_ERR5_SHIFT)
+#define DMA_BRD_ERR_ERR5(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR5_SHIFT))
+
+/*! @brief Set the ERR5 field to a new value. */
+#define DMA_WR_ERR_ERR5(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR5_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR5(value)))
+#define DMA_BWR_ERR_ERR5(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR6[6] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR6 field. */
+#define DMA_RD_ERR_ERR6(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR6_MASK) >> DMA_ERR_ERR6_SHIFT)
+#define DMA_BRD_ERR_ERR6(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR6_SHIFT))
+
+/*! @brief Set the ERR6 field to a new value. */
+#define DMA_WR_ERR_ERR6(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR6_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR6(value)))
+#define DMA_BWR_ERR_ERR6(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR7[7] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR7 field. */
+#define DMA_RD_ERR_ERR7(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR7_MASK) >> DMA_ERR_ERR7_SHIFT)
+#define DMA_BRD_ERR_ERR7(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR7_SHIFT))
+
+/*! @brief Set the ERR7 field to a new value. */
+#define DMA_WR_ERR_ERR7(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR7_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR7(value)))
+#define DMA_BWR_ERR_ERR7(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR7_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR8[8] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR8 field. */
+#define DMA_RD_ERR_ERR8(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR8_MASK) >> DMA_ERR_ERR8_SHIFT)
+#define DMA_BRD_ERR_ERR8(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR8_SHIFT))
+
+/*! @brief Set the ERR8 field to a new value. */
+#define DMA_WR_ERR_ERR8(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR8_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR8(value)))
+#define DMA_BWR_ERR_ERR8(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR9[9] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR9 field. */
+#define DMA_RD_ERR_ERR9(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR9_MASK) >> DMA_ERR_ERR9_SHIFT)
+#define DMA_BRD_ERR_ERR9(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR9_SHIFT))
+
+/*! @brief Set the ERR9 field to a new value. */
+#define DMA_WR_ERR_ERR9(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR9_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR9(value)))
+#define DMA_BWR_ERR_ERR9(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR10[10] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR10 field. */
+#define DMA_RD_ERR_ERR10(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR10_MASK) >> DMA_ERR_ERR10_SHIFT)
+#define DMA_BRD_ERR_ERR10(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR10_SHIFT))
+
+/*! @brief Set the ERR10 field to a new value. */
+#define DMA_WR_ERR_ERR10(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR10_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR10(value)))
+#define DMA_BWR_ERR_ERR10(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR11[11] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR11 field. */
+#define DMA_RD_ERR_ERR11(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR11_MASK) >> DMA_ERR_ERR11_SHIFT)
+#define DMA_BRD_ERR_ERR11(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR11_SHIFT))
+
+/*! @brief Set the ERR11 field to a new value. */
+#define DMA_WR_ERR_ERR11(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR11_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR11(value)))
+#define DMA_BWR_ERR_ERR11(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR12[12] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR12 field. */
+#define DMA_RD_ERR_ERR12(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR12_MASK) >> DMA_ERR_ERR12_SHIFT)
+#define DMA_BRD_ERR_ERR12(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR12_SHIFT))
+
+/*! @brief Set the ERR12 field to a new value. */
+#define DMA_WR_ERR_ERR12(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR12_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR12(value)))
+#define DMA_BWR_ERR_ERR12(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR13[13] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR13 field. */
+#define DMA_RD_ERR_ERR13(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR13_MASK) >> DMA_ERR_ERR13_SHIFT)
+#define DMA_BRD_ERR_ERR13(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR13_SHIFT))
+
+/*! @brief Set the ERR13 field to a new value. */
+#define DMA_WR_ERR_ERR13(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR13_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR14_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR13(value)))
+#define DMA_BWR_ERR_ERR13(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR14[14] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR14 field. */
+#define DMA_RD_ERR_ERR14(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR14_MASK) >> DMA_ERR_ERR14_SHIFT)
+#define DMA_BRD_ERR_ERR14(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR14_SHIFT))
+
+/*! @brief Set the ERR14 field to a new value. */
+#define DMA_WR_ERR_ERR14(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR14_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR15_MASK), DMA_ERR_ERR14(value)))
+#define DMA_BWR_ERR_ERR14(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ERR, field ERR15[15] (W1C)
+ *
+ * Values:
+ * - 0b0 - An error in the corresponding channel has not occurred
+ * - 0b1 - An error in the corresponding channel has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ERR_ERR15 field. */
+#define DMA_RD_ERR_ERR15(base) ((DMA_ERR_REG(base) & DMA_ERR_ERR15_MASK) >> DMA_ERR_ERR15_SHIFT)
+#define DMA_BRD_ERR_ERR15(base) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR15_SHIFT))
+
+/*! @brief Set the ERR15 field to a new value. */
+#define DMA_WR_ERR_ERR15(base, value) (DMA_RMW_ERR(base, (DMA_ERR_ERR15_MASK | DMA_ERR_ERR0_MASK | DMA_ERR_ERR1_MASK | DMA_ERR_ERR2_MASK | DMA_ERR_ERR3_MASK | DMA_ERR_ERR4_MASK | DMA_ERR_ERR5_MASK | DMA_ERR_ERR6_MASK | DMA_ERR_ERR7_MASK | DMA_ERR_ERR8_MASK | DMA_ERR_ERR9_MASK | DMA_ERR_ERR10_MASK | DMA_ERR_ERR11_MASK | DMA_ERR_ERR12_MASK | DMA_ERR_ERR13_MASK | DMA_ERR_ERR14_MASK), DMA_ERR_ERR15(value)))
+#define DMA_BWR_ERR_ERR15(base, value) (BITBAND_ACCESS32(&DMA_ERR_REG(base), DMA_ERR_ERR15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_HRS - Hardware Request Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_HRS - Hardware Request Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The HRS register provides a bit map for the DMA channels, signaling the
+ * presence of a hardware request for each channel. The hardware request status bits
+ * reflect the current state of the register and qualified (via the ERQ fields)
+ * DMA request signals as seen by the DMA's arbitration logic. This view into the
+ * hardware request signals may be used for debug purposes. These bits reflect the
+ * state of the request as seen by the arbitration logic. Therefore, this status
+ * is affected by the ERQ bits.
+ */
+/*!
+ * @name Constants and macros for entire DMA_HRS register
+ */
+/*@{*/
+#define DMA_RD_HRS(base)         (DMA_HRS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_HRS bitfields
+ */
+
+/*!
+ * @name Register DMA_HRS, field HRS0[0] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 0 is not present
+ * - 0b1 - A hardware service request for channel 0 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS0 field. */
+#define DMA_RD_HRS_HRS0(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS0_MASK) >> DMA_HRS_HRS0_SHIFT)
+#define DMA_BRD_HRS_HRS0(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS1[1] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 1 is not present
+ * - 0b1 - A hardware service request for channel 1 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS1 field. */
+#define DMA_RD_HRS_HRS1(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS1_MASK) >> DMA_HRS_HRS1_SHIFT)
+#define DMA_BRD_HRS_HRS1(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS2[2] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 2 is not present
+ * - 0b1 - A hardware service request for channel 2 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS2 field. */
+#define DMA_RD_HRS_HRS2(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS2_MASK) >> DMA_HRS_HRS2_SHIFT)
+#define DMA_BRD_HRS_HRS2(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS2_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS3[3] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 3 is not present
+ * - 0b1 - A hardware service request for channel 3 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS3 field. */
+#define DMA_RD_HRS_HRS3(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS3_MASK) >> DMA_HRS_HRS3_SHIFT)
+#define DMA_BRD_HRS_HRS3(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS3_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS4[4] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 4 is not present
+ * - 0b1 - A hardware service request for channel 4 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS4 field. */
+#define DMA_RD_HRS_HRS4(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS4_MASK) >> DMA_HRS_HRS4_SHIFT)
+#define DMA_BRD_HRS_HRS4(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS4_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS5[5] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 5 is not present
+ * - 0b1 - A hardware service request for channel 5 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS5 field. */
+#define DMA_RD_HRS_HRS5(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS5_MASK) >> DMA_HRS_HRS5_SHIFT)
+#define DMA_BRD_HRS_HRS5(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS5_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS6[6] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 6 is not present
+ * - 0b1 - A hardware service request for channel 6 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS6 field. */
+#define DMA_RD_HRS_HRS6(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS6_MASK) >> DMA_HRS_HRS6_SHIFT)
+#define DMA_BRD_HRS_HRS6(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS6_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS7[7] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 7 is not present
+ * - 0b1 - A hardware service request for channel 7 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS7 field. */
+#define DMA_RD_HRS_HRS7(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS7_MASK) >> DMA_HRS_HRS7_SHIFT)
+#define DMA_BRD_HRS_HRS7(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS7_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS8[8] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 8 is not present
+ * - 0b1 - A hardware service request for channel 8 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS8 field. */
+#define DMA_RD_HRS_HRS8(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS8_MASK) >> DMA_HRS_HRS8_SHIFT)
+#define DMA_BRD_HRS_HRS8(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS8_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS9[9] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 9 is not present
+ * - 0b1 - A hardware service request for channel 9 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS9 field. */
+#define DMA_RD_HRS_HRS9(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS9_MASK) >> DMA_HRS_HRS9_SHIFT)
+#define DMA_BRD_HRS_HRS9(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS9_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS10[10] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 10 is not present
+ * - 0b1 - A hardware service request for channel 10 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS10 field. */
+#define DMA_RD_HRS_HRS10(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS10_MASK) >> DMA_HRS_HRS10_SHIFT)
+#define DMA_BRD_HRS_HRS10(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS10_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS11[11] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 11 is not present
+ * - 0b1 - A hardware service request for channel 11 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS11 field. */
+#define DMA_RD_HRS_HRS11(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS11_MASK) >> DMA_HRS_HRS11_SHIFT)
+#define DMA_BRD_HRS_HRS11(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS11_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS12[12] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 12 is not present
+ * - 0b1 - A hardware service request for channel 12 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS12 field. */
+#define DMA_RD_HRS_HRS12(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS12_MASK) >> DMA_HRS_HRS12_SHIFT)
+#define DMA_BRD_HRS_HRS12(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS12_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS13[13] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 13 is not present
+ * - 0b1 - A hardware service request for channel 13 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS13 field. */
+#define DMA_RD_HRS_HRS13(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS13_MASK) >> DMA_HRS_HRS13_SHIFT)
+#define DMA_BRD_HRS_HRS13(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS13_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS14[14] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 14 is not present
+ * - 0b1 - A hardware service request for channel 14 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS14 field. */
+#define DMA_RD_HRS_HRS14(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS14_MASK) >> DMA_HRS_HRS14_SHIFT)
+#define DMA_BRD_HRS_HRS14(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS14_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register DMA_HRS, field HRS15[15] (RO)
+ *
+ * The HRS bit for its respective channel remains asserted for the period when a
+ * Hardware Request is Present on the Channel. After the Request is completed
+ * and Channel is free , the HRS bit is automatically cleared by hardware.
+ *
+ * Values:
+ * - 0b0 - A hardware service request for channel 15 is not present
+ * - 0b1 - A hardware service request for channel 15 is present
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_HRS_HRS15 field. */
+#define DMA_RD_HRS_HRS15(base) ((DMA_HRS_REG(base) & DMA_HRS_HRS15_MASK) >> DMA_HRS_HRS15_SHIFT)
+#define DMA_BRD_HRS_HRS15(base) (BITBAND_ACCESS32(&DMA_HRS_REG(base), DMA_HRS_HRS15_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI3 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI3 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI3 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI3(base)     (DMA_DCHPRI3_REG(base))
+#define DMA_WR_DCHPRI3(base, value) (DMA_DCHPRI3_REG(base) = (value))
+#define DMA_RMW_DCHPRI3(base, mask, value) (DMA_WR_DCHPRI3(base, (DMA_RD_DCHPRI3(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) |  (value)))
+#define DMA_CLR_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) & ~(value)))
+#define DMA_TOG_DCHPRI3(base, value) (DMA_WR_DCHPRI3(base, DMA_RD_DCHPRI3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI3 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI3, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_CHPRI field. */
+#define DMA_RD_DCHPRI3_CHPRI(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_CHPRI_MASK) >> DMA_DCHPRI3_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI3_CHPRI(base) (DMA_RD_DCHPRI3_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI3_CHPRI(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_CHPRI_MASK, DMA_DCHPRI3_CHPRI(value)))
+#define DMA_BWR_DCHPRI3_CHPRI(base, value) (DMA_WR_DCHPRI3_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI3, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_DPA field. */
+#define DMA_RD_DCHPRI3_DPA(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_DPA_MASK) >> DMA_DCHPRI3_DPA_SHIFT)
+#define DMA_BRD_DCHPRI3_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI3_DPA(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_DPA_MASK, DMA_DCHPRI3_DPA(value)))
+#define DMA_BWR_DCHPRI3_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI3, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI3_ECP field. */
+#define DMA_RD_DCHPRI3_ECP(base) ((DMA_DCHPRI3_REG(base) & DMA_DCHPRI3_ECP_MASK) >> DMA_DCHPRI3_ECP_SHIFT)
+#define DMA_BRD_DCHPRI3_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI3_ECP(base, value) (DMA_RMW_DCHPRI3(base, DMA_DCHPRI3_ECP_MASK, DMA_DCHPRI3_ECP(value)))
+#define DMA_BWR_DCHPRI3_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI3_REG(base), DMA_DCHPRI3_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI2 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI2 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI2 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI2(base)     (DMA_DCHPRI2_REG(base))
+#define DMA_WR_DCHPRI2(base, value) (DMA_DCHPRI2_REG(base) = (value))
+#define DMA_RMW_DCHPRI2(base, mask, value) (DMA_WR_DCHPRI2(base, (DMA_RD_DCHPRI2(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) |  (value)))
+#define DMA_CLR_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) & ~(value)))
+#define DMA_TOG_DCHPRI2(base, value) (DMA_WR_DCHPRI2(base, DMA_RD_DCHPRI2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI2 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI2, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_CHPRI field. */
+#define DMA_RD_DCHPRI2_CHPRI(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_CHPRI_MASK) >> DMA_DCHPRI2_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI2_CHPRI(base) (DMA_RD_DCHPRI2_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI2_CHPRI(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_CHPRI_MASK, DMA_DCHPRI2_CHPRI(value)))
+#define DMA_BWR_DCHPRI2_CHPRI(base, value) (DMA_WR_DCHPRI2_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI2, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_DPA field. */
+#define DMA_RD_DCHPRI2_DPA(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_DPA_MASK) >> DMA_DCHPRI2_DPA_SHIFT)
+#define DMA_BRD_DCHPRI2_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI2_DPA(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_DPA_MASK, DMA_DCHPRI2_DPA(value)))
+#define DMA_BWR_DCHPRI2_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI2, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI2_ECP field. */
+#define DMA_RD_DCHPRI2_ECP(base) ((DMA_DCHPRI2_REG(base) & DMA_DCHPRI2_ECP_MASK) >> DMA_DCHPRI2_ECP_SHIFT)
+#define DMA_BRD_DCHPRI2_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI2_ECP(base, value) (DMA_RMW_DCHPRI2(base, DMA_DCHPRI2_ECP_MASK, DMA_DCHPRI2_ECP(value)))
+#define DMA_BWR_DCHPRI2_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI2_REG(base), DMA_DCHPRI2_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI1 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI1 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI1 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI1(base)     (DMA_DCHPRI1_REG(base))
+#define DMA_WR_DCHPRI1(base, value) (DMA_DCHPRI1_REG(base) = (value))
+#define DMA_RMW_DCHPRI1(base, mask, value) (DMA_WR_DCHPRI1(base, (DMA_RD_DCHPRI1(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) |  (value)))
+#define DMA_CLR_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) & ~(value)))
+#define DMA_TOG_DCHPRI1(base, value) (DMA_WR_DCHPRI1(base, DMA_RD_DCHPRI1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI1 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI1, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_CHPRI field. */
+#define DMA_RD_DCHPRI1_CHPRI(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_CHPRI_MASK) >> DMA_DCHPRI1_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI1_CHPRI(base) (DMA_RD_DCHPRI1_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI1_CHPRI(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_CHPRI_MASK, DMA_DCHPRI1_CHPRI(value)))
+#define DMA_BWR_DCHPRI1_CHPRI(base, value) (DMA_WR_DCHPRI1_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI1, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_DPA field. */
+#define DMA_RD_DCHPRI1_DPA(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_DPA_MASK) >> DMA_DCHPRI1_DPA_SHIFT)
+#define DMA_BRD_DCHPRI1_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI1_DPA(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_DPA_MASK, DMA_DCHPRI1_DPA(value)))
+#define DMA_BWR_DCHPRI1_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI1, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI1_ECP field. */
+#define DMA_RD_DCHPRI1_ECP(base) ((DMA_DCHPRI1_REG(base) & DMA_DCHPRI1_ECP_MASK) >> DMA_DCHPRI1_ECP_SHIFT)
+#define DMA_BRD_DCHPRI1_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI1_ECP(base, value) (DMA_RMW_DCHPRI1(base, DMA_DCHPRI1_ECP_MASK, DMA_DCHPRI1_ECP(value)))
+#define DMA_BWR_DCHPRI1_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI1_REG(base), DMA_DCHPRI1_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI0 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI0 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI0 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI0(base)     (DMA_DCHPRI0_REG(base))
+#define DMA_WR_DCHPRI0(base, value) (DMA_DCHPRI0_REG(base) = (value))
+#define DMA_RMW_DCHPRI0(base, mask, value) (DMA_WR_DCHPRI0(base, (DMA_RD_DCHPRI0(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) |  (value)))
+#define DMA_CLR_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) & ~(value)))
+#define DMA_TOG_DCHPRI0(base, value) (DMA_WR_DCHPRI0(base, DMA_RD_DCHPRI0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI0 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI0, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_CHPRI field. */
+#define DMA_RD_DCHPRI0_CHPRI(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_CHPRI_MASK) >> DMA_DCHPRI0_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI0_CHPRI(base) (DMA_RD_DCHPRI0_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI0_CHPRI(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_CHPRI_MASK, DMA_DCHPRI0_CHPRI(value)))
+#define DMA_BWR_DCHPRI0_CHPRI(base, value) (DMA_WR_DCHPRI0_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI0, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_DPA field. */
+#define DMA_RD_DCHPRI0_DPA(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_DPA_MASK) >> DMA_DCHPRI0_DPA_SHIFT)
+#define DMA_BRD_DCHPRI0_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI0_DPA(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_DPA_MASK, DMA_DCHPRI0_DPA(value)))
+#define DMA_BWR_DCHPRI0_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI0, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI0_ECP field. */
+#define DMA_RD_DCHPRI0_ECP(base) ((DMA_DCHPRI0_REG(base) & DMA_DCHPRI0_ECP_MASK) >> DMA_DCHPRI0_ECP_SHIFT)
+#define DMA_BRD_DCHPRI0_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI0_ECP(base, value) (DMA_RMW_DCHPRI0(base, DMA_DCHPRI0_ECP_MASK, DMA_DCHPRI0_ECP(value)))
+#define DMA_BWR_DCHPRI0_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI0_REG(base), DMA_DCHPRI0_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI7 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI7 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI7 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI7(base)     (DMA_DCHPRI7_REG(base))
+#define DMA_WR_DCHPRI7(base, value) (DMA_DCHPRI7_REG(base) = (value))
+#define DMA_RMW_DCHPRI7(base, mask, value) (DMA_WR_DCHPRI7(base, (DMA_RD_DCHPRI7(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) |  (value)))
+#define DMA_CLR_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) & ~(value)))
+#define DMA_TOG_DCHPRI7(base, value) (DMA_WR_DCHPRI7(base, DMA_RD_DCHPRI7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI7 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI7, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_CHPRI field. */
+#define DMA_RD_DCHPRI7_CHPRI(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_CHPRI_MASK) >> DMA_DCHPRI7_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI7_CHPRI(base) (DMA_RD_DCHPRI7_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI7_CHPRI(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_CHPRI_MASK, DMA_DCHPRI7_CHPRI(value)))
+#define DMA_BWR_DCHPRI7_CHPRI(base, value) (DMA_WR_DCHPRI7_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI7, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_DPA field. */
+#define DMA_RD_DCHPRI7_DPA(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_DPA_MASK) >> DMA_DCHPRI7_DPA_SHIFT)
+#define DMA_BRD_DCHPRI7_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI7_DPA(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_DPA_MASK, DMA_DCHPRI7_DPA(value)))
+#define DMA_BWR_DCHPRI7_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI7, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI7_ECP field. */
+#define DMA_RD_DCHPRI7_ECP(base) ((DMA_DCHPRI7_REG(base) & DMA_DCHPRI7_ECP_MASK) >> DMA_DCHPRI7_ECP_SHIFT)
+#define DMA_BRD_DCHPRI7_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI7_ECP(base, value) (DMA_RMW_DCHPRI7(base, DMA_DCHPRI7_ECP_MASK, DMA_DCHPRI7_ECP(value)))
+#define DMA_BWR_DCHPRI7_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI7_REG(base), DMA_DCHPRI7_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI6 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI6 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI6 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI6(base)     (DMA_DCHPRI6_REG(base))
+#define DMA_WR_DCHPRI6(base, value) (DMA_DCHPRI6_REG(base) = (value))
+#define DMA_RMW_DCHPRI6(base, mask, value) (DMA_WR_DCHPRI6(base, (DMA_RD_DCHPRI6(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) |  (value)))
+#define DMA_CLR_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) & ~(value)))
+#define DMA_TOG_DCHPRI6(base, value) (DMA_WR_DCHPRI6(base, DMA_RD_DCHPRI6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI6 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI6, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_CHPRI field. */
+#define DMA_RD_DCHPRI6_CHPRI(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_CHPRI_MASK) >> DMA_DCHPRI6_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI6_CHPRI(base) (DMA_RD_DCHPRI6_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI6_CHPRI(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_CHPRI_MASK, DMA_DCHPRI6_CHPRI(value)))
+#define DMA_BWR_DCHPRI6_CHPRI(base, value) (DMA_WR_DCHPRI6_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI6, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_DPA field. */
+#define DMA_RD_DCHPRI6_DPA(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_DPA_MASK) >> DMA_DCHPRI6_DPA_SHIFT)
+#define DMA_BRD_DCHPRI6_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI6_DPA(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_DPA_MASK, DMA_DCHPRI6_DPA(value)))
+#define DMA_BWR_DCHPRI6_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI6, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI6_ECP field. */
+#define DMA_RD_DCHPRI6_ECP(base) ((DMA_DCHPRI6_REG(base) & DMA_DCHPRI6_ECP_MASK) >> DMA_DCHPRI6_ECP_SHIFT)
+#define DMA_BRD_DCHPRI6_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI6_ECP(base, value) (DMA_RMW_DCHPRI6(base, DMA_DCHPRI6_ECP_MASK, DMA_DCHPRI6_ECP(value)))
+#define DMA_BWR_DCHPRI6_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI6_REG(base), DMA_DCHPRI6_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI5 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI5 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI5 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI5(base)     (DMA_DCHPRI5_REG(base))
+#define DMA_WR_DCHPRI5(base, value) (DMA_DCHPRI5_REG(base) = (value))
+#define DMA_RMW_DCHPRI5(base, mask, value) (DMA_WR_DCHPRI5(base, (DMA_RD_DCHPRI5(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) |  (value)))
+#define DMA_CLR_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) & ~(value)))
+#define DMA_TOG_DCHPRI5(base, value) (DMA_WR_DCHPRI5(base, DMA_RD_DCHPRI5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI5 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI5, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_CHPRI field. */
+#define DMA_RD_DCHPRI5_CHPRI(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_CHPRI_MASK) >> DMA_DCHPRI5_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI5_CHPRI(base) (DMA_RD_DCHPRI5_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI5_CHPRI(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_CHPRI_MASK, DMA_DCHPRI5_CHPRI(value)))
+#define DMA_BWR_DCHPRI5_CHPRI(base, value) (DMA_WR_DCHPRI5_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI5, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_DPA field. */
+#define DMA_RD_DCHPRI5_DPA(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_DPA_MASK) >> DMA_DCHPRI5_DPA_SHIFT)
+#define DMA_BRD_DCHPRI5_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI5_DPA(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_DPA_MASK, DMA_DCHPRI5_DPA(value)))
+#define DMA_BWR_DCHPRI5_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI5, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI5_ECP field. */
+#define DMA_RD_DCHPRI5_ECP(base) ((DMA_DCHPRI5_REG(base) & DMA_DCHPRI5_ECP_MASK) >> DMA_DCHPRI5_ECP_SHIFT)
+#define DMA_BRD_DCHPRI5_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI5_ECP(base, value) (DMA_RMW_DCHPRI5(base, DMA_DCHPRI5_ECP_MASK, DMA_DCHPRI5_ECP(value)))
+#define DMA_BWR_DCHPRI5_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI5_REG(base), DMA_DCHPRI5_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI4 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI4 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI4 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI4(base)     (DMA_DCHPRI4_REG(base))
+#define DMA_WR_DCHPRI4(base, value) (DMA_DCHPRI4_REG(base) = (value))
+#define DMA_RMW_DCHPRI4(base, mask, value) (DMA_WR_DCHPRI4(base, (DMA_RD_DCHPRI4(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) |  (value)))
+#define DMA_CLR_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) & ~(value)))
+#define DMA_TOG_DCHPRI4(base, value) (DMA_WR_DCHPRI4(base, DMA_RD_DCHPRI4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI4 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI4, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_CHPRI field. */
+#define DMA_RD_DCHPRI4_CHPRI(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_CHPRI_MASK) >> DMA_DCHPRI4_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI4_CHPRI(base) (DMA_RD_DCHPRI4_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI4_CHPRI(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_CHPRI_MASK, DMA_DCHPRI4_CHPRI(value)))
+#define DMA_BWR_DCHPRI4_CHPRI(base, value) (DMA_WR_DCHPRI4_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI4, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_DPA field. */
+#define DMA_RD_DCHPRI4_DPA(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_DPA_MASK) >> DMA_DCHPRI4_DPA_SHIFT)
+#define DMA_BRD_DCHPRI4_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI4_DPA(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_DPA_MASK, DMA_DCHPRI4_DPA(value)))
+#define DMA_BWR_DCHPRI4_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI4, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI4_ECP field. */
+#define DMA_RD_DCHPRI4_ECP(base) ((DMA_DCHPRI4_REG(base) & DMA_DCHPRI4_ECP_MASK) >> DMA_DCHPRI4_ECP_SHIFT)
+#define DMA_BRD_DCHPRI4_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI4_ECP(base, value) (DMA_RMW_DCHPRI4(base, DMA_DCHPRI4_ECP_MASK, DMA_DCHPRI4_ECP(value)))
+#define DMA_BWR_DCHPRI4_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI4_REG(base), DMA_DCHPRI4_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI11 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI11 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI11 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI11(base)    (DMA_DCHPRI11_REG(base))
+#define DMA_WR_DCHPRI11(base, value) (DMA_DCHPRI11_REG(base) = (value))
+#define DMA_RMW_DCHPRI11(base, mask, value) (DMA_WR_DCHPRI11(base, (DMA_RD_DCHPRI11(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) |  (value)))
+#define DMA_CLR_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) & ~(value)))
+#define DMA_TOG_DCHPRI11(base, value) (DMA_WR_DCHPRI11(base, DMA_RD_DCHPRI11(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI11 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI11, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_CHPRI field. */
+#define DMA_RD_DCHPRI11_CHPRI(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_CHPRI_MASK) >> DMA_DCHPRI11_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI11_CHPRI(base) (DMA_RD_DCHPRI11_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI11_CHPRI(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_CHPRI_MASK, DMA_DCHPRI11_CHPRI(value)))
+#define DMA_BWR_DCHPRI11_CHPRI(base, value) (DMA_WR_DCHPRI11_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI11, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_DPA field. */
+#define DMA_RD_DCHPRI11_DPA(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_DPA_MASK) >> DMA_DCHPRI11_DPA_SHIFT)
+#define DMA_BRD_DCHPRI11_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI11_DPA(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_DPA_MASK, DMA_DCHPRI11_DPA(value)))
+#define DMA_BWR_DCHPRI11_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI11, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI11_ECP field. */
+#define DMA_RD_DCHPRI11_ECP(base) ((DMA_DCHPRI11_REG(base) & DMA_DCHPRI11_ECP_MASK) >> DMA_DCHPRI11_ECP_SHIFT)
+#define DMA_BRD_DCHPRI11_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI11_ECP(base, value) (DMA_RMW_DCHPRI11(base, DMA_DCHPRI11_ECP_MASK, DMA_DCHPRI11_ECP(value)))
+#define DMA_BWR_DCHPRI11_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI11_REG(base), DMA_DCHPRI11_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI10 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI10 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI10 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI10(base)    (DMA_DCHPRI10_REG(base))
+#define DMA_WR_DCHPRI10(base, value) (DMA_DCHPRI10_REG(base) = (value))
+#define DMA_RMW_DCHPRI10(base, mask, value) (DMA_WR_DCHPRI10(base, (DMA_RD_DCHPRI10(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) |  (value)))
+#define DMA_CLR_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) & ~(value)))
+#define DMA_TOG_DCHPRI10(base, value) (DMA_WR_DCHPRI10(base, DMA_RD_DCHPRI10(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI10 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI10, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_CHPRI field. */
+#define DMA_RD_DCHPRI10_CHPRI(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_CHPRI_MASK) >> DMA_DCHPRI10_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI10_CHPRI(base) (DMA_RD_DCHPRI10_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI10_CHPRI(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_CHPRI_MASK, DMA_DCHPRI10_CHPRI(value)))
+#define DMA_BWR_DCHPRI10_CHPRI(base, value) (DMA_WR_DCHPRI10_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI10, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_DPA field. */
+#define DMA_RD_DCHPRI10_DPA(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_DPA_MASK) >> DMA_DCHPRI10_DPA_SHIFT)
+#define DMA_BRD_DCHPRI10_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI10_DPA(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_DPA_MASK, DMA_DCHPRI10_DPA(value)))
+#define DMA_BWR_DCHPRI10_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI10, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI10_ECP field. */
+#define DMA_RD_DCHPRI10_ECP(base) ((DMA_DCHPRI10_REG(base) & DMA_DCHPRI10_ECP_MASK) >> DMA_DCHPRI10_ECP_SHIFT)
+#define DMA_BRD_DCHPRI10_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI10_ECP(base, value) (DMA_RMW_DCHPRI10(base, DMA_DCHPRI10_ECP_MASK, DMA_DCHPRI10_ECP(value)))
+#define DMA_BWR_DCHPRI10_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI10_REG(base), DMA_DCHPRI10_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI9 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI9 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI9 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI9(base)     (DMA_DCHPRI9_REG(base))
+#define DMA_WR_DCHPRI9(base, value) (DMA_DCHPRI9_REG(base) = (value))
+#define DMA_RMW_DCHPRI9(base, mask, value) (DMA_WR_DCHPRI9(base, (DMA_RD_DCHPRI9(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) |  (value)))
+#define DMA_CLR_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) & ~(value)))
+#define DMA_TOG_DCHPRI9(base, value) (DMA_WR_DCHPRI9(base, DMA_RD_DCHPRI9(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI9 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI9, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_CHPRI field. */
+#define DMA_RD_DCHPRI9_CHPRI(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_CHPRI_MASK) >> DMA_DCHPRI9_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI9_CHPRI(base) (DMA_RD_DCHPRI9_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI9_CHPRI(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_CHPRI_MASK, DMA_DCHPRI9_CHPRI(value)))
+#define DMA_BWR_DCHPRI9_CHPRI(base, value) (DMA_WR_DCHPRI9_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI9, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_DPA field. */
+#define DMA_RD_DCHPRI9_DPA(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_DPA_MASK) >> DMA_DCHPRI9_DPA_SHIFT)
+#define DMA_BRD_DCHPRI9_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI9_DPA(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_DPA_MASK, DMA_DCHPRI9_DPA(value)))
+#define DMA_BWR_DCHPRI9_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI9, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI9_ECP field. */
+#define DMA_RD_DCHPRI9_ECP(base) ((DMA_DCHPRI9_REG(base) & DMA_DCHPRI9_ECP_MASK) >> DMA_DCHPRI9_ECP_SHIFT)
+#define DMA_BRD_DCHPRI9_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI9_ECP(base, value) (DMA_RMW_DCHPRI9(base, DMA_DCHPRI9_ECP_MASK, DMA_DCHPRI9_ECP(value)))
+#define DMA_BWR_DCHPRI9_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI9_REG(base), DMA_DCHPRI9_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI8 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI8 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI8 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI8(base)     (DMA_DCHPRI8_REG(base))
+#define DMA_WR_DCHPRI8(base, value) (DMA_DCHPRI8_REG(base) = (value))
+#define DMA_RMW_DCHPRI8(base, mask, value) (DMA_WR_DCHPRI8(base, (DMA_RD_DCHPRI8(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) |  (value)))
+#define DMA_CLR_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) & ~(value)))
+#define DMA_TOG_DCHPRI8(base, value) (DMA_WR_DCHPRI8(base, DMA_RD_DCHPRI8(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI8 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI8, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_CHPRI field. */
+#define DMA_RD_DCHPRI8_CHPRI(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_CHPRI_MASK) >> DMA_DCHPRI8_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI8_CHPRI(base) (DMA_RD_DCHPRI8_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI8_CHPRI(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_CHPRI_MASK, DMA_DCHPRI8_CHPRI(value)))
+#define DMA_BWR_DCHPRI8_CHPRI(base, value) (DMA_WR_DCHPRI8_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI8, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_DPA field. */
+#define DMA_RD_DCHPRI8_DPA(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_DPA_MASK) >> DMA_DCHPRI8_DPA_SHIFT)
+#define DMA_BRD_DCHPRI8_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI8_DPA(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_DPA_MASK, DMA_DCHPRI8_DPA(value)))
+#define DMA_BWR_DCHPRI8_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI8, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI8_ECP field. */
+#define DMA_RD_DCHPRI8_ECP(base) ((DMA_DCHPRI8_REG(base) & DMA_DCHPRI8_ECP_MASK) >> DMA_DCHPRI8_ECP_SHIFT)
+#define DMA_BRD_DCHPRI8_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI8_ECP(base, value) (DMA_RMW_DCHPRI8(base, DMA_DCHPRI8_ECP_MASK, DMA_DCHPRI8_ECP(value)))
+#define DMA_BWR_DCHPRI8_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI8_REG(base), DMA_DCHPRI8_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI15 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI15 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI15 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI15(base)    (DMA_DCHPRI15_REG(base))
+#define DMA_WR_DCHPRI15(base, value) (DMA_DCHPRI15_REG(base) = (value))
+#define DMA_RMW_DCHPRI15(base, mask, value) (DMA_WR_DCHPRI15(base, (DMA_RD_DCHPRI15(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) |  (value)))
+#define DMA_CLR_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) & ~(value)))
+#define DMA_TOG_DCHPRI15(base, value) (DMA_WR_DCHPRI15(base, DMA_RD_DCHPRI15(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI15 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI15, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_CHPRI field. */
+#define DMA_RD_DCHPRI15_CHPRI(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_CHPRI_MASK) >> DMA_DCHPRI15_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI15_CHPRI(base) (DMA_RD_DCHPRI15_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI15_CHPRI(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_CHPRI_MASK, DMA_DCHPRI15_CHPRI(value)))
+#define DMA_BWR_DCHPRI15_CHPRI(base, value) (DMA_WR_DCHPRI15_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI15, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_DPA field. */
+#define DMA_RD_DCHPRI15_DPA(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_DPA_MASK) >> DMA_DCHPRI15_DPA_SHIFT)
+#define DMA_BRD_DCHPRI15_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI15_DPA(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_DPA_MASK, DMA_DCHPRI15_DPA(value)))
+#define DMA_BWR_DCHPRI15_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI15, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI15_ECP field. */
+#define DMA_RD_DCHPRI15_ECP(base) ((DMA_DCHPRI15_REG(base) & DMA_DCHPRI15_ECP_MASK) >> DMA_DCHPRI15_ECP_SHIFT)
+#define DMA_BRD_DCHPRI15_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI15_ECP(base, value) (DMA_RMW_DCHPRI15(base, DMA_DCHPRI15_ECP_MASK, DMA_DCHPRI15_ECP(value)))
+#define DMA_BWR_DCHPRI15_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI15_REG(base), DMA_DCHPRI15_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI14 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI14 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI14 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI14(base)    (DMA_DCHPRI14_REG(base))
+#define DMA_WR_DCHPRI14(base, value) (DMA_DCHPRI14_REG(base) = (value))
+#define DMA_RMW_DCHPRI14(base, mask, value) (DMA_WR_DCHPRI14(base, (DMA_RD_DCHPRI14(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) |  (value)))
+#define DMA_CLR_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) & ~(value)))
+#define DMA_TOG_DCHPRI14(base, value) (DMA_WR_DCHPRI14(base, DMA_RD_DCHPRI14(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI14 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI14, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_CHPRI field. */
+#define DMA_RD_DCHPRI14_CHPRI(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_CHPRI_MASK) >> DMA_DCHPRI14_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI14_CHPRI(base) (DMA_RD_DCHPRI14_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI14_CHPRI(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_CHPRI_MASK, DMA_DCHPRI14_CHPRI(value)))
+#define DMA_BWR_DCHPRI14_CHPRI(base, value) (DMA_WR_DCHPRI14_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI14, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_DPA field. */
+#define DMA_RD_DCHPRI14_DPA(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_DPA_MASK) >> DMA_DCHPRI14_DPA_SHIFT)
+#define DMA_BRD_DCHPRI14_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI14_DPA(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_DPA_MASK, DMA_DCHPRI14_DPA(value)))
+#define DMA_BWR_DCHPRI14_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI14, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI14_ECP field. */
+#define DMA_RD_DCHPRI14_ECP(base) ((DMA_DCHPRI14_REG(base) & DMA_DCHPRI14_ECP_MASK) >> DMA_DCHPRI14_ECP_SHIFT)
+#define DMA_BRD_DCHPRI14_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI14_ECP(base, value) (DMA_RMW_DCHPRI14(base, DMA_DCHPRI14_ECP_MASK, DMA_DCHPRI14_ECP(value)))
+#define DMA_BWR_DCHPRI14_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI14_REG(base), DMA_DCHPRI14_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI13 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI13 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI13 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI13(base)    (DMA_DCHPRI13_REG(base))
+#define DMA_WR_DCHPRI13(base, value) (DMA_DCHPRI13_REG(base) = (value))
+#define DMA_RMW_DCHPRI13(base, mask, value) (DMA_WR_DCHPRI13(base, (DMA_RD_DCHPRI13(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) |  (value)))
+#define DMA_CLR_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) & ~(value)))
+#define DMA_TOG_DCHPRI13(base, value) (DMA_WR_DCHPRI13(base, DMA_RD_DCHPRI13(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI13 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI13, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_CHPRI field. */
+#define DMA_RD_DCHPRI13_CHPRI(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_CHPRI_MASK) >> DMA_DCHPRI13_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI13_CHPRI(base) (DMA_RD_DCHPRI13_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI13_CHPRI(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_CHPRI_MASK, DMA_DCHPRI13_CHPRI(value)))
+#define DMA_BWR_DCHPRI13_CHPRI(base, value) (DMA_WR_DCHPRI13_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI13, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_DPA field. */
+#define DMA_RD_DCHPRI13_DPA(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_DPA_MASK) >> DMA_DCHPRI13_DPA_SHIFT)
+#define DMA_BRD_DCHPRI13_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI13_DPA(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_DPA_MASK, DMA_DCHPRI13_DPA(value)))
+#define DMA_BWR_DCHPRI13_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI13, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI13_ECP field. */
+#define DMA_RD_DCHPRI13_ECP(base) ((DMA_DCHPRI13_REG(base) & DMA_DCHPRI13_ECP_MASK) >> DMA_DCHPRI13_ECP_SHIFT)
+#define DMA_BRD_DCHPRI13_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI13_ECP(base, value) (DMA_RMW_DCHPRI13(base, DMA_DCHPRI13_ECP_MASK, DMA_DCHPRI13_ECP(value)))
+#define DMA_BWR_DCHPRI13_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI13_REG(base), DMA_DCHPRI13_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DCHPRI12 - Channel n Priority Register
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DCHPRI12 - Channel n Priority Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
+ * contents of these registers define the unique priorities associated with each
+ * channel . The channel priorities are evaluated by numeric value; for example, 0 is
+ * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
+ * program the channel priorities with unique values; otherwise, a configuration
+ * error is reported. The range of the priority value is limited to the values of 0
+ * through 15.
+ */
+/*!
+ * @name Constants and macros for entire DMA_DCHPRI12 register
+ */
+/*@{*/
+#define DMA_RD_DCHPRI12(base)    (DMA_DCHPRI12_REG(base))
+#define DMA_WR_DCHPRI12(base, value) (DMA_DCHPRI12_REG(base) = (value))
+#define DMA_RMW_DCHPRI12(base, mask, value) (DMA_WR_DCHPRI12(base, (DMA_RD_DCHPRI12(base) & ~(mask)) | (value)))
+#define DMA_SET_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) |  (value)))
+#define DMA_CLR_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) & ~(value)))
+#define DMA_TOG_DCHPRI12(base, value) (DMA_WR_DCHPRI12(base, DMA_RD_DCHPRI12(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_DCHPRI12 bitfields
+ */
+
+/*!
+ * @name Register DMA_DCHPRI12, field CHPRI[3:0] (RW)
+ *
+ * Channel priority when fixed-priority arbitration is enabled Reset value for
+ * the channel priority fields, CHPRI, is equal to the corresponding channel
+ * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_CHPRI field. */
+#define DMA_RD_DCHPRI12_CHPRI(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_CHPRI_MASK) >> DMA_DCHPRI12_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRI12_CHPRI(base) (DMA_RD_DCHPRI12_CHPRI(base))
+
+/*! @brief Set the CHPRI field to a new value. */
+#define DMA_WR_DCHPRI12_CHPRI(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_CHPRI_MASK, DMA_DCHPRI12_CHPRI(value)))
+#define DMA_BWR_DCHPRI12_CHPRI(base, value) (DMA_WR_DCHPRI12_CHPRI(base, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI12, field DPA[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n can suspend a lower priority channel
+ * - 0b1 - Channel n cannot suspend any channel, regardless of channel priority
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_DPA field. */
+#define DMA_RD_DCHPRI12_DPA(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_DPA_MASK) >> DMA_DCHPRI12_DPA_SHIFT)
+#define DMA_BRD_DCHPRI12_DPA(base) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_DPA_SHIFT))
+
+/*! @brief Set the DPA field to a new value. */
+#define DMA_WR_DCHPRI12_DPA(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_DPA_MASK, DMA_DCHPRI12_DPA(value)))
+#define DMA_BWR_DCHPRI12_DPA(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_DPA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_DCHPRI12, field ECP[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Channel n cannot be suspended by a higher priority channel's service
+ *     request
+ * - 0b1 - Channel n can be temporarily suspended by the service request of a
+ *     higher priority channel
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_DCHPRI12_ECP field. */
+#define DMA_RD_DCHPRI12_ECP(base) ((DMA_DCHPRI12_REG(base) & DMA_DCHPRI12_ECP_MASK) >> DMA_DCHPRI12_ECP_SHIFT)
+#define DMA_BRD_DCHPRI12_ECP(base) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_ECP_SHIFT))
+
+/*! @brief Set the ECP field to a new value. */
+#define DMA_WR_DCHPRI12_ECP(base, value) (DMA_RMW_DCHPRI12(base, DMA_DCHPRI12_ECP_MASK, DMA_DCHPRI12_ECP(value)))
+#define DMA_BWR_DCHPRI12_ECP(base, value) (BITBAND_ACCESS8(&DMA_DCHPRI12_REG(base), DMA_DCHPRI12_ECP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SADDR - TCD Source Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SADDR - TCD Source Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SADDR register
+ */
+/*@{*/
+#define DMA_RD_SADDR(base, index) (DMA_SADDR_REG(base, index))
+#define DMA_WR_SADDR(base, index, value) (DMA_SADDR_REG(base, index) = (value))
+#define DMA_RMW_SADDR(base, index, mask, value) (DMA_WR_SADDR(base, index, (DMA_RD_SADDR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) |  (value)))
+#define DMA_CLR_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) & ~(value)))
+#define DMA_TOG_SADDR(base, index, value) (DMA_WR_SADDR(base, index, DMA_RD_SADDR(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SOFF - TCD Signed Source Address Offset
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SOFF - TCD Signed Source Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SOFF register
+ */
+/*@{*/
+#define DMA_RD_SOFF(base, index) (DMA_SOFF_REG(base, index))
+#define DMA_WR_SOFF(base, index, value) (DMA_SOFF_REG(base, index) = (value))
+#define DMA_RMW_SOFF(base, index, mask, value) (DMA_WR_SOFF(base, index, (DMA_RD_SOFF(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) |  (value)))
+#define DMA_CLR_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) & ~(value)))
+#define DMA_TOG_SOFF(base, index, value) (DMA_WR_SOFF(base, index, DMA_RD_SOFF(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_ATTR - TCD Transfer Attributes
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_ATTR - TCD Transfer Attributes (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_ATTR register
+ */
+/*@{*/
+#define DMA_RD_ATTR(base, index) (DMA_ATTR_REG(base, index))
+#define DMA_WR_ATTR(base, index, value) (DMA_ATTR_REG(base, index) = (value))
+#define DMA_RMW_ATTR(base, index, mask, value) (DMA_WR_ATTR(base, index, (DMA_RD_ATTR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) |  (value)))
+#define DMA_CLR_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) & ~(value)))
+#define DMA_TOG_ATTR(base, index, value) (DMA_WR_ATTR(base, index, DMA_RD_ATTR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_ATTR bitfields
+ */
+
+/*!
+ * @name Register DMA_ATTR, field DSIZE[2:0] (RW)
+ *
+ * See the SSIZE definition
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_DSIZE field. */
+#define DMA_RD_ATTR_DSIZE(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_DSIZE_MASK) >> DMA_ATTR_DSIZE_SHIFT)
+#define DMA_BRD_ATTR_DSIZE(base, index) (DMA_RD_ATTR_DSIZE(base, index))
+
+/*! @brief Set the DSIZE field to a new value. */
+#define DMA_WR_ATTR_DSIZE(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_DSIZE_MASK, DMA_ATTR_DSIZE(value)))
+#define DMA_BWR_ATTR_DSIZE(base, index, value) (DMA_WR_ATTR_DSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field DMOD[7:3] (RW)
+ *
+ * See the SMOD definition
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_DMOD field. */
+#define DMA_RD_ATTR_DMOD(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_DMOD_MASK) >> DMA_ATTR_DMOD_SHIFT)
+#define DMA_BRD_ATTR_DMOD(base, index) (DMA_RD_ATTR_DMOD(base, index))
+
+/*! @brief Set the DMOD field to a new value. */
+#define DMA_WR_ATTR_DMOD(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_DMOD_MASK, DMA_ATTR_DMOD(value)))
+#define DMA_BWR_ATTR_DMOD(base, index, value) (DMA_WR_ATTR_DMOD(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field SSIZE[10:8] (RW)
+ *
+ * The attempted use of a Reserved encoding causes a configuration error.
+ *
+ * Values:
+ * - 0b000 - 8-bit
+ * - 0b001 - 16-bit
+ * - 0b010 - 32-bit
+ * - 0b011 - Reserved
+ * - 0b100 - 16-byte
+ * - 0b101 - 32-byte
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_SSIZE field. */
+#define DMA_RD_ATTR_SSIZE(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_SSIZE_MASK) >> DMA_ATTR_SSIZE_SHIFT)
+#define DMA_BRD_ATTR_SSIZE(base, index) (DMA_RD_ATTR_SSIZE(base, index))
+
+/*! @brief Set the SSIZE field to a new value. */
+#define DMA_WR_ATTR_SSIZE(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_SSIZE_MASK, DMA_ATTR_SSIZE(value)))
+#define DMA_BWR_ATTR_SSIZE(base, index, value) (DMA_WR_ATTR_SSIZE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_ATTR, field SMOD[15:11] (RW)
+ *
+ * Values:
+ * - 0b00000 - Source address modulo feature is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_ATTR_SMOD field. */
+#define DMA_RD_ATTR_SMOD(base, index) ((DMA_ATTR_REG(base, index) & DMA_ATTR_SMOD_MASK) >> DMA_ATTR_SMOD_SHIFT)
+#define DMA_BRD_ATTR_SMOD(base, index) (DMA_RD_ATTR_SMOD(base, index))
+
+/*! @brief Set the SMOD field to a new value. */
+#define DMA_WR_ATTR_SMOD(base, index, value) (DMA_RMW_ATTR(base, index, DMA_ATTR_SMOD_MASK, DMA_ATTR_SMOD(value)))
+#define DMA_BWR_ATTR_SMOD(base, index, value) (DMA_WR_ATTR_SMOD(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
+ * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
+ * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
+ * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLOFFYES register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLOFFYES(base, index) (DMA_NBYTES_MLOFFYES_REG(base, index))
+#define DMA_WR_NBYTES_MLOFFYES(base, index, value) (DMA_NBYTES_MLOFFYES_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLOFFYES(base, index, mask, value) (DMA_WR_NBYTES_MLOFFYES(base, index, (DMA_RD_NBYTES_MLOFFYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLOFFYES(base, index, value) (DMA_WR_NBYTES_MLOFFYES(base, index, DMA_RD_NBYTES_MLOFFYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_NBYTES_MLOFFYES bitfields
+ */
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted.
+ * (Although, it may be stalled by using the bandwidth control field, or via
+ * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
+ * written back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_NBYTES field. */
+#define DMA_RD_NBYTES_MLOFFYES_NBYTES(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) >> DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_NBYTES(base, index) (DMA_RD_NBYTES_MLOFFYES_NBYTES(base, index))
+
+/*! @brief Set the NBYTES field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_NBYTES(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_NBYTES_MASK, DMA_NBYTES_MLOFFYES_NBYTES(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_NBYTES(base, index, value) (DMA_WR_NBYTES_MLOFFYES_NBYTES(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_MLOFF field. */
+#define DMA_RD_NBYTES_MLOFFYES_MLOFF(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) >> DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_MLOFF(base, index) (DMA_RD_NBYTES_MLOFFYES_MLOFF(base, index))
+
+/*! @brief Set the MLOFF field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_MLOFF(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_MLOFF_MASK, DMA_NBYTES_MLOFFYES_MLOFF(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_MLOFF(base, index, value) (DMA_WR_NBYTES_MLOFFYES_MLOFF(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the DADDR
+ * - 0b1 - The minor loop offset is applied to the DADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_DMLOE field. */
+#define DMA_RD_NBYTES_MLOFFYES_DMLOE(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) >> DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_DMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))
+
+/*! @brief Set the DMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_DMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_DMLOE_MASK, DMA_NBYTES_MLOFFYES_DMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_DMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_DMLOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFYES, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the SADDR
+ * - 0b1 - The minor loop offset is applied to the SADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFYES_SMLOE field. */
+#define DMA_RD_NBYTES_MLOFFYES_SMLOE(base, index) ((DMA_NBYTES_MLOFFYES_REG(base, index) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) >> DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFYES_SMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))
+
+/*! @brief Set the SMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFYES_SMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFYES(base, index, DMA_NBYTES_MLOFFYES_SMLOE_MASK, DMA_NBYTES_MLOFFYES_SMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFYES_SMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFYES_REG(base, index), DMA_NBYTES_MLOFFYES_SMLOE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
+ * register to use depends on whether minor loop mapping is disabled, enabled but not
+ * used for this channel, or enabled and used. TCD word 2 is defined as follows
+ * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
+ * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
+ * for TCD word 2's definition.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLNO register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLNO(base, index) (DMA_NBYTES_MLNO_REG(base, index))
+#define DMA_WR_NBYTES_MLNO(base, index, value) (DMA_NBYTES_MLNO_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLNO(base, index, mask, value) (DMA_WR_NBYTES_MLNO(base, index, (DMA_RD_NBYTES_MLNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLNO(base, index, value) (DMA_WR_NBYTES_MLNO(base, index, DMA_RD_NBYTES_MLNO(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * One of three registers (this register, TCD_NBYTES_MLNO, or
+ * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
+ * depends on whether minor loop mapping is disabled, enabled but not used for
+ * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
+ * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
+ * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
+ * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
+ * the TCD_NBYTES_MLNO register description.
+ */
+/*!
+ * @name Constants and macros for entire DMA_NBYTES_MLOFFNO register
+ */
+/*@{*/
+#define DMA_RD_NBYTES_MLOFFNO(base, index) (DMA_NBYTES_MLOFFNO_REG(base, index))
+#define DMA_WR_NBYTES_MLOFFNO(base, index, value) (DMA_NBYTES_MLOFFNO_REG(base, index) = (value))
+#define DMA_RMW_NBYTES_MLOFFNO(base, index, mask, value) (DMA_WR_NBYTES_MLOFFNO(base, index, (DMA_RD_NBYTES_MLOFFNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) |  (value)))
+#define DMA_CLR_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) & ~(value)))
+#define DMA_TOG_NBYTES_MLOFFNO(base, index, value) (DMA_WR_NBYTES_MLOFFNO(base, index, DMA_RD_NBYTES_MLOFFNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_NBYTES_MLOFFNO bitfields
+ */
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
+ *
+ * Number of bytes to be transferred in each service request of the channel. As
+ * a channel activates, the appropriate TCD contents load into the eDMA engine,
+ * and the appropriate reads and writes perform until the minor byte transfer
+ * count has transferred. This is an indivisible operation and cannot be halted;
+ * although, it may be stalled by using the bandwidth control field, or via
+ * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
+ * back into the TCD memory, the major iteration count is decremented and
+ * restored to the TCD memory. If the major iteration count is completed, additional
+ * processing is performed.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_NBYTES field. */
+#define DMA_RD_NBYTES_MLOFFNO_NBYTES(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) >> DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_NBYTES(base, index) (DMA_RD_NBYTES_MLOFFNO_NBYTES(base, index))
+
+/*! @brief Set the NBYTES field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_NBYTES(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_NBYTES_MASK, DMA_NBYTES_MLOFFNO_NBYTES(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_NBYTES(base, index, value) (DMA_WR_NBYTES_MLOFFNO_NBYTES(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field DMLOE[30] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the destination address
+ * upon minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the DADDR
+ * - 0b1 - The minor loop offset is applied to the DADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_DMLOE field. */
+#define DMA_RD_NBYTES_MLOFFNO_DMLOE(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) >> DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_DMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))
+
+/*! @brief Set the DMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_DMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_DMLOE_MASK, DMA_NBYTES_MLOFFNO_DMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_DMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_DMLOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_NBYTES_MLOFFNO, field SMLOE[31] (RW)
+ *
+ * Selects whether the minor loop offset is applied to the source address upon
+ * minor loop completion.
+ *
+ * Values:
+ * - 0b0 - The minor loop offset is not applied to the SADDR
+ * - 0b1 - The minor loop offset is applied to the SADDR
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_NBYTES_MLOFFNO_SMLOE field. */
+#define DMA_RD_NBYTES_MLOFFNO_SMLOE(base, index) ((DMA_NBYTES_MLOFFNO_REG(base, index) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) >> DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)
+#define DMA_BRD_NBYTES_MLOFFNO_SMLOE(base, index) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))
+
+/*! @brief Set the SMLOE field to a new value. */
+#define DMA_WR_NBYTES_MLOFFNO_SMLOE(base, index, value) (DMA_RMW_NBYTES_MLOFFNO(base, index, DMA_NBYTES_MLOFFNO_SMLOE_MASK, DMA_NBYTES_MLOFFNO_SMLOE(value)))
+#define DMA_BWR_NBYTES_MLOFFNO_SMLOE(base, index, value) (BITBAND_ACCESS32(&DMA_NBYTES_MLOFFNO_REG(base, index), DMA_NBYTES_MLOFFNO_SMLOE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_SLAST - TCD Last Source Address Adjustment
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_SLAST - TCD Last Source Address Adjustment (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_SLAST register
+ */
+/*@{*/
+#define DMA_RD_SLAST(base, index) (DMA_SLAST_REG(base, index))
+#define DMA_WR_SLAST(base, index, value) (DMA_SLAST_REG(base, index) = (value))
+#define DMA_RMW_SLAST(base, index, mask, value) (DMA_WR_SLAST(base, index, (DMA_RD_SLAST(base, index) & ~(mask)) | (value)))
+#define DMA_SET_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) |  (value)))
+#define DMA_CLR_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) & ~(value)))
+#define DMA_TOG_SLAST(base, index, value) (DMA_WR_SLAST(base, index, DMA_RD_SLAST(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DADDR - TCD Destination Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DADDR - TCD Destination Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DADDR register
+ */
+/*@{*/
+#define DMA_RD_DADDR(base, index) (DMA_DADDR_REG(base, index))
+#define DMA_WR_DADDR(base, index, value) (DMA_DADDR_REG(base, index) = (value))
+#define DMA_RMW_DADDR(base, index, mask, value) (DMA_WR_DADDR(base, index, (DMA_RD_DADDR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) |  (value)))
+#define DMA_CLR_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) & ~(value)))
+#define DMA_TOG_DADDR(base, index, value) (DMA_WR_DADDR(base, index, DMA_RD_DADDR(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DOFF - TCD Signed Destination Address Offset
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DOFF - TCD Signed Destination Address Offset (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DOFF register
+ */
+/*@{*/
+#define DMA_RD_DOFF(base, index) (DMA_DOFF_REG(base, index))
+#define DMA_WR_DOFF(base, index, value) (DMA_DOFF_REG(base, index) = (value))
+#define DMA_RMW_DOFF(base, index, mask, value) (DMA_WR_DOFF(base, index, (DMA_RD_DOFF(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) |  (value)))
+#define DMA_CLR_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) & ~(value)))
+#define DMA_TOG_DOFF(base, index, value) (DMA_WR_DOFF(base, index, DMA_RD_DOFF(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
+ * follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CITER_ELINKNO register
+ */
+/*@{*/
+#define DMA_RD_CITER_ELINKNO(base, index) (DMA_CITER_ELINKNO_REG(base, index))
+#define DMA_WR_CITER_ELINKNO(base, index, value) (DMA_CITER_ELINKNO_REG(base, index) = (value))
+#define DMA_RMW_CITER_ELINKNO(base, index, mask, value) (DMA_WR_CITER_ELINKNO(base, index, (DMA_RD_CITER_ELINKNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) |  (value)))
+#define DMA_CLR_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) & ~(value)))
+#define DMA_TOG_CITER_ELINKNO(base, index, value) (DMA_WR_CITER_ELINKNO(base, index, DMA_RD_CITER_ELINKNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_CITER_ELINKNO, field CITER[14:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKNO_CITER field. */
+#define DMA_RD_CITER_ELINKNO_CITER(base, index) ((DMA_CITER_ELINKNO_REG(base, index) & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT)
+#define DMA_BRD_CITER_ELINKNO_CITER(base, index) (DMA_RD_CITER_ELINKNO_CITER(base, index))
+
+/*! @brief Set the CITER field to a new value. */
+#define DMA_WR_CITER_ELINKNO_CITER(base, index, value) (DMA_RMW_CITER_ELINKNO(base, index, DMA_CITER_ELINKNO_CITER_MASK, DMA_CITER_ELINKNO_CITER(value)))
+#define DMA_BWR_CITER_ELINKNO_CITER(base, index, value) (DMA_WR_CITER_ELINKNO_CITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKNO_ELINK field. */
+#define DMA_RD_CITER_ELINKNO_ELINK(base, index) ((DMA_CITER_ELINKNO_REG(base, index) & DMA_CITER_ELINKNO_ELINK_MASK) >> DMA_CITER_ELINKNO_ELINK_SHIFT)
+#define DMA_BRD_CITER_ELINKNO_ELINK(base, index) (BITBAND_ACCESS16(&DMA_CITER_ELINKNO_REG(base, index), DMA_CITER_ELINKNO_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_CITER_ELINKNO_ELINK(base, index, value) (DMA_RMW_CITER_ELINKNO(base, index, DMA_CITER_ELINKNO_ELINK_MASK, DMA_CITER_ELINKNO_ELINK(value)))
+#define DMA_BWR_CITER_ELINKNO_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CITER_ELINKNO_REG(base, index), DMA_CITER_ELINKNO_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_CITER_ELINKYES register
+ */
+/*@{*/
+#define DMA_RD_CITER_ELINKYES(base, index) (DMA_CITER_ELINKYES_REG(base, index))
+#define DMA_WR_CITER_ELINKYES(base, index, value) (DMA_CITER_ELINKYES_REG(base, index) = (value))
+#define DMA_RMW_CITER_ELINKYES(base, index, mask, value) (DMA_WR_CITER_ELINKYES(base, index, (DMA_RD_CITER_ELINKYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) |  (value)))
+#define DMA_CLR_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) & ~(value)))
+#define DMA_TOG_CITER_ELINKYES(base, index, value) (DMA_WR_CITER_ELINKYES(base, index, DMA_RD_CITER_ELINKYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field CITER[8:0] (RW)
+ *
+ * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
+ * major loop count for the channel. It is decremented each time the minor loop is
+ * completed and updated in the transfer control descriptor memory. After the
+ * major iteration count is exhausted, the channel performs a number of operations
+ * (e.g., final source and destination address calculations), optionally generating
+ * an interrupt to signal channel completion before reloading the CITER field
+ * from the beginning iteration count (BITER) field. When the CITER field is
+ * initially loaded by software, it must be set to the same value as that contained in
+ * the BITER field. If the channel is configured to execute a single service
+ * request, the initial values of BITER and CITER should be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_CITER field. */
+#define DMA_RD_CITER_ELINKYES_CITER(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_CITER(base, index) (DMA_RD_CITER_ELINKYES_CITER(base, index))
+
+/*! @brief Set the CITER field to a new value. */
+#define DMA_WR_CITER_ELINKYES_CITER(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_CITER_MASK, DMA_CITER_ELINKYES_CITER(value)))
+#define DMA_BWR_CITER_ELINKYES_CITER(base, index, value) (DMA_WR_CITER_ELINKYES_CITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request to the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_LINKCH field. */
+#define DMA_RD_CITER_ELINKYES_LINKCH(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_LINKCH_MASK) >> DMA_CITER_ELINKYES_LINKCH_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_LINKCH(base, index) (DMA_RD_CITER_ELINKYES_LINKCH(base, index))
+
+/*! @brief Set the LINKCH field to a new value. */
+#define DMA_WR_CITER_ELINKYES_LINKCH(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_LINKCH_MASK, DMA_CITER_ELINKYES_LINKCH(value)))
+#define DMA_BWR_CITER_ELINKYES_LINKCH(base, index, value) (DMA_WR_CITER_ELINKYES_LINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables linking to another
+ * channel, defined by the LINKCH field. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the CITER value
+ * is extended to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
+ * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
+ * configuration error is reported.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CITER_ELINKYES_ELINK field. */
+#define DMA_RD_CITER_ELINKYES_ELINK(base, index) ((DMA_CITER_ELINKYES_REG(base, index) & DMA_CITER_ELINKYES_ELINK_MASK) >> DMA_CITER_ELINKYES_ELINK_SHIFT)
+#define DMA_BRD_CITER_ELINKYES_ELINK(base, index) (BITBAND_ACCESS16(&DMA_CITER_ELINKYES_REG(base, index), DMA_CITER_ELINKYES_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_CITER_ELINKYES_ELINK(base, index, value) (DMA_RMW_CITER_ELINKYES(base, index, DMA_CITER_ELINKYES_ELINK_MASK, DMA_CITER_ELINKYES_ELINK(value)))
+#define DMA_BWR_CITER_ELINKYES_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CITER_ELINKYES_REG(base, index), DMA_CITER_ELINKYES_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_DLAST_SGA register
+ */
+/*@{*/
+#define DMA_RD_DLAST_SGA(base, index) (DMA_DLAST_SGA_REG(base, index))
+#define DMA_WR_DLAST_SGA(base, index, value) (DMA_DLAST_SGA_REG(base, index) = (value))
+#define DMA_RMW_DLAST_SGA(base, index, mask, value) (DMA_WR_DLAST_SGA(base, index, (DMA_RD_DLAST_SGA(base, index) & ~(mask)) | (value)))
+#define DMA_SET_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) |  (value)))
+#define DMA_CLR_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) & ~(value)))
+#define DMA_TOG_DLAST_SGA(base, index, value) (DMA_WR_DLAST_SGA(base, index, DMA_RD_DLAST_SGA(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_CSR - TCD Control and Status
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_CSR - TCD Control and Status (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire DMA_CSR register
+ */
+/*@{*/
+#define DMA_RD_CSR(base, index)  (DMA_CSR_REG(base, index))
+#define DMA_WR_CSR(base, index, value) (DMA_CSR_REG(base, index) = (value))
+#define DMA_RMW_CSR(base, index, mask, value) (DMA_WR_CSR(base, index, (DMA_RD_CSR(base, index) & ~(mask)) | (value)))
+#define DMA_SET_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) |  (value)))
+#define DMA_CLR_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) & ~(value)))
+#define DMA_TOG_CSR(base, index, value) (DMA_WR_CSR(base, index, DMA_RD_CSR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_CSR bitfields
+ */
+
+/*!
+ * @name Register DMA_CSR, field START[0] (RW)
+ *
+ * If this flag is set, the channel is requesting service. The eDMA hardware
+ * automatically clears this flag after the channel begins execution.
+ *
+ * Values:
+ * - 0b0 - The channel is not explicitly started
+ * - 0b1 - The channel is explicitly started via a software initiated service
+ *     request
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_START field. */
+#define DMA_RD_CSR_START(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_START_MASK) >> DMA_CSR_START_SHIFT)
+#define DMA_BRD_CSR_START(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_START_SHIFT))
+
+/*! @brief Set the START field to a new value. */
+#define DMA_WR_CSR_START(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_START_MASK, DMA_CSR_START(value)))
+#define DMA_BWR_CSR_START(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_START_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field INTMAJOR[1] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT when the current major iteration count reaches
+ * zero.
+ *
+ * Values:
+ * - 0b0 - The end-of-major loop interrupt is disabled
+ * - 0b1 - The end-of-major loop interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_INTMAJOR field. */
+#define DMA_RD_CSR_INTMAJOR(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_INTMAJOR_MASK) >> DMA_CSR_INTMAJOR_SHIFT)
+#define DMA_BRD_CSR_INTMAJOR(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTMAJOR_SHIFT))
+
+/*! @brief Set the INTMAJOR field to a new value. */
+#define DMA_WR_CSR_INTMAJOR(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_INTMAJOR_MASK, DMA_CSR_INTMAJOR(value)))
+#define DMA_BWR_CSR_INTMAJOR(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTMAJOR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field INTHALF[2] (RW)
+ *
+ * If this flag is set, the channel generates an interrupt request by setting
+ * the appropriate bit in the INT register when the current major iteration count
+ * reaches the halfway point. Specifically, the comparison performed by the eDMA
+ * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
+ * provided to support double-buffered (aka ping-pong) schemes or other types of data
+ * movement where the processor needs an early indication of the transfer's
+ * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
+ *
+ * Values:
+ * - 0b0 - The half-point interrupt is disabled
+ * - 0b1 - The half-point interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_INTHALF field. */
+#define DMA_RD_CSR_INTHALF(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_INTHALF_MASK) >> DMA_CSR_INTHALF_SHIFT)
+#define DMA_BRD_CSR_INTHALF(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTHALF_SHIFT))
+
+/*! @brief Set the INTHALF field to a new value. */
+#define DMA_WR_CSR_INTHALF(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_INTHALF_MASK, DMA_CSR_INTHALF(value)))
+#define DMA_BWR_CSR_INTHALF(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_INTHALF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field DREQ[3] (RW)
+ *
+ * If this flag is set, the eDMA hardware automatically clears the corresponding
+ * ERQ bit when the current major iteration count reaches zero.
+ *
+ * Values:
+ * - 0b0 - The channel's ERQ bit is not affected
+ * - 0b1 - The channel's ERQ bit is cleared when the major loop is complete
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_DREQ field. */
+#define DMA_RD_CSR_DREQ(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_DREQ_MASK) >> DMA_CSR_DREQ_SHIFT)
+#define DMA_BRD_CSR_DREQ(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DREQ_SHIFT))
+
+/*! @brief Set the DREQ field to a new value. */
+#define DMA_WR_CSR_DREQ(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_DREQ_MASK, DMA_CSR_DREQ(value)))
+#define DMA_BWR_CSR_DREQ(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field ESG[4] (RW)
+ *
+ * As the channel completes the major loop, this flag enables scatter/gather
+ * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
+ * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
+ * loaded as the transfer control descriptor into the local memory. To support the
+ * dynamic scatter/gather coherency model, this field is forced to zero when
+ * written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0b0 - The current channel's TCD is normal format.
+ * - 0b1 - The current channel's TCD specifies a scatter gather format. The
+ *     DLASTSGA field provides a memory pointer to the next TCD to be loaded into
+ *     this channel after the major loop completes its execution.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_ESG field. */
+#define DMA_RD_CSR_ESG(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_ESG_MASK) >> DMA_CSR_ESG_SHIFT)
+#define DMA_BRD_CSR_ESG(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ESG_SHIFT))
+
+/*! @brief Set the ESG field to a new value. */
+#define DMA_WR_CSR_ESG(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_ESG_MASK, DMA_CSR_ESG(value)))
+#define DMA_BWR_CSR_ESG(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ESG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field MAJORELINK[5] (RW)
+ *
+ * As the channel completes the major loop, this flag enables the linking to
+ * another channel, defined by MAJORLINKCH. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. To support the dynamic linking coherency model,
+ * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_MAJORELINK field. */
+#define DMA_RD_CSR_MAJORELINK(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_MAJORELINK_MASK) >> DMA_CSR_MAJORELINK_SHIFT)
+#define DMA_BRD_CSR_MAJORELINK(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_MAJORELINK_SHIFT))
+
+/*! @brief Set the MAJORELINK field to a new value. */
+#define DMA_WR_CSR_MAJORELINK(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_MAJORELINK_MASK, DMA_CSR_MAJORELINK(value)))
+#define DMA_BWR_CSR_MAJORELINK(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_MAJORELINK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field ACTIVE[6] (RW)
+ *
+ * This flag signals the channel is currently in execution. It is set when
+ * channel service begins, and the eDMA clears it as the minor loop completes or if
+ * any error condition is detected. This bit resets to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_ACTIVE field. */
+#define DMA_RD_CSR_ACTIVE(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_ACTIVE_MASK) >> DMA_CSR_ACTIVE_SHIFT)
+#define DMA_BRD_CSR_ACTIVE(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ACTIVE_SHIFT))
+
+/*! @brief Set the ACTIVE field to a new value. */
+#define DMA_WR_CSR_ACTIVE(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_ACTIVE_MASK, DMA_CSR_ACTIVE(value)))
+#define DMA_BWR_CSR_ACTIVE(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_ACTIVE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field DONE[7] (RW)
+ *
+ * This flag indicates the eDMA has completed the major loop. The eDMA engine
+ * sets it as the CITER count reaches zero; The software clears it, or the hardware
+ * when the channel is activated. This bit must be cleared to write the
+ * MAJORELINK or ESG bits.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_DONE field. */
+#define DMA_RD_CSR_DONE(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT)
+#define DMA_BRD_CSR_DONE(base, index) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DONE_SHIFT))
+
+/*! @brief Set the DONE field to a new value. */
+#define DMA_WR_CSR_DONE(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_DONE_MASK, DMA_CSR_DONE(value)))
+#define DMA_BWR_CSR_DONE(base, index, value) (BITBAND_ACCESS16(&DMA_CSR_REG(base, index), DMA_CSR_DONE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field MAJORLINKCH[11:8] (RW)
+ *
+ * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
+ * performed after the major loop counter is exhausted. else After the major loop
+ * counter is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_MAJORLINKCH field. */
+#define DMA_RD_CSR_MAJORLINKCH(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_MAJORLINKCH_MASK) >> DMA_CSR_MAJORLINKCH_SHIFT)
+#define DMA_BRD_CSR_MAJORLINKCH(base, index) (DMA_RD_CSR_MAJORLINKCH(base, index))
+
+/*! @brief Set the MAJORLINKCH field to a new value. */
+#define DMA_WR_CSR_MAJORLINKCH(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_MAJORLINKCH_MASK, DMA_CSR_MAJORLINKCH(value)))
+#define DMA_BWR_CSR_MAJORLINKCH(base, index, value) (DMA_WR_CSR_MAJORLINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_CSR, field BWC[15:14] (RW)
+ *
+ * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
+ * the eDMA processes the minor loop, it continuously generates read/write
+ * sequences until the minor count is exhausted. This field forces the eDMA to stall
+ * after the completion of each read/write access to control the bus request
+ * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
+ * this field is ignored between the first and second transfers and after the
+ * last write of each minor loop. This behavior is a side effect of reducing
+ * start-up latency.
+ *
+ * Values:
+ * - 0b00 - No eDMA engine stalls
+ * - 0b01 - Reserved
+ * - 0b10 - eDMA engine stalls for 4 cycles after each r/w
+ * - 0b11 - eDMA engine stalls for 8 cycles after each r/w
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_CSR_BWC field. */
+#define DMA_RD_CSR_BWC(base, index) ((DMA_CSR_REG(base, index) & DMA_CSR_BWC_MASK) >> DMA_CSR_BWC_SHIFT)
+#define DMA_BRD_CSR_BWC(base, index) (DMA_RD_CSR_BWC(base, index))
+
+/*! @brief Set the BWC field to a new value. */
+#define DMA_WR_CSR_BWC(base, index, value) (DMA_RMW_CSR(base, index, DMA_CSR_BWC_MASK, DMA_CSR_BWC(value)))
+#define DMA_BWR_CSR_BWC(base, index, value) (DMA_WR_CSR_BWC(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
+ * follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_BITER_ELINKYES register
+ */
+/*@{*/
+#define DMA_RD_BITER_ELINKYES(base, index) (DMA_BITER_ELINKYES_REG(base, index))
+#define DMA_WR_BITER_ELINKYES(base, index, value) (DMA_BITER_ELINKYES_REG(base, index) = (value))
+#define DMA_RMW_BITER_ELINKYES(base, index, mask, value) (DMA_WR_BITER_ELINKYES(base, index, (DMA_RD_BITER_ELINKYES(base, index) & ~(mask)) | (value)))
+#define DMA_SET_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) |  (value)))
+#define DMA_CLR_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) & ~(value)))
+#define DMA_TOG_BITER_ELINKYES(base, index, value) (DMA_WR_BITER_ELINKYES(base, index, DMA_RD_BITER_ELINKYES(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_BITER_ELINKYES bitfields
+ */
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field BITER[8:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_BITER field. */
+#define DMA_RD_BITER_ELINKYES_BITER(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_BITER_MASK) >> DMA_BITER_ELINKYES_BITER_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_BITER(base, index) (DMA_RD_BITER_ELINKYES_BITER(base, index))
+
+/*! @brief Set the BITER field to a new value. */
+#define DMA_WR_BITER_ELINKYES_BITER(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_BITER_MASK, DMA_BITER_ELINKYES_BITER(value)))
+#define DMA_BWR_BITER_ELINKYES_BITER(base, index, value) (DMA_WR_BITER_ELINKYES_BITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field LINKCH[12:9] (RW)
+ *
+ * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
+ * loop is exhausted, the eDMA engine initiates a channel service request at the
+ * channel defined by these four bits by setting that channel's TCDn_CSR[START]
+ * bit. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the major
+ * iteration count is exhausted, the contents of this field is reloaded into the
+ * CITER field.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_LINKCH field. */
+#define DMA_RD_BITER_ELINKYES_LINKCH(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_LINKCH_MASK) >> DMA_BITER_ELINKYES_LINKCH_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_LINKCH(base, index) (DMA_RD_BITER_ELINKYES_LINKCH(base, index))
+
+/*! @brief Set the LINKCH field to a new value. */
+#define DMA_WR_BITER_ELINKYES_LINKCH(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_LINKCH_MASK, DMA_BITER_ELINKYES_LINKCH(value)))
+#define DMA_BWR_BITER_ELINKYES_LINKCH(base, index, value) (DMA_WR_BITER_ELINKYES_LINKCH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKYES, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking disables, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded into
+ * the CITER field.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKYES_ELINK field. */
+#define DMA_RD_BITER_ELINKYES_ELINK(base, index) ((DMA_BITER_ELINKYES_REG(base, index) & DMA_BITER_ELINKYES_ELINK_MASK) >> DMA_BITER_ELINKYES_ELINK_SHIFT)
+#define DMA_BRD_BITER_ELINKYES_ELINK(base, index) (BITBAND_ACCESS16(&DMA_BITER_ELINKYES_REG(base, index), DMA_BITER_ELINKYES_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_BITER_ELINKYES_ELINK(base, index, value) (DMA_RMW_BITER_ELINKYES(base, index, DMA_BITER_ELINKYES_ELINK_MASK, DMA_BITER_ELINKYES_ELINK(value)))
+#define DMA_BWR_BITER_ELINKYES_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_BITER_ELINKYES_REG(base, index), DMA_BITER_ELINKYES_ELINK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
+ ******************************************************************************/
+
+/*!
+ * @brief DMA_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
+ * as follows.
+ */
+/*!
+ * @name Constants and macros for entire DMA_BITER_ELINKNO register
+ */
+/*@{*/
+#define DMA_RD_BITER_ELINKNO(base, index) (DMA_BITER_ELINKNO_REG(base, index))
+#define DMA_WR_BITER_ELINKNO(base, index, value) (DMA_BITER_ELINKNO_REG(base, index) = (value))
+#define DMA_RMW_BITER_ELINKNO(base, index, mask, value) (DMA_WR_BITER_ELINKNO(base, index, (DMA_RD_BITER_ELINKNO(base, index) & ~(mask)) | (value)))
+#define DMA_SET_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) |  (value)))
+#define DMA_CLR_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) & ~(value)))
+#define DMA_TOG_BITER_ELINKNO(base, index, value) (DMA_WR_BITER_ELINKNO(base, index, DMA_RD_BITER_ELINKNO(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMA_BITER_ELINKNO bitfields
+ */
+
+/*!
+ * @name Register DMA_BITER_ELINKNO, field BITER[14:0] (RW)
+ *
+ * As the transfer control descriptor is first loaded by software, this 9-bit
+ * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
+ * field. As the major iteration count is exhausted, the contents of this field
+ * are reloaded into the CITER field. When the software loads the TCD, this field
+ * must be set equal to the corresponding CITER field; otherwise, a configuration
+ * error is reported. As the major iteration count is exhausted, the contents of
+ * this field is reloaded into the CITER field. If the channel is configured to
+ * execute a single service request, the initial values of BITER and CITER should
+ * be 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKNO_BITER field. */
+#define DMA_RD_BITER_ELINKNO_BITER(base, index) ((DMA_BITER_ELINKNO_REG(base, index) & DMA_BITER_ELINKNO_BITER_MASK) >> DMA_BITER_ELINKNO_BITER_SHIFT)
+#define DMA_BRD_BITER_ELINKNO_BITER(base, index) (DMA_RD_BITER_ELINKNO_BITER(base, index))
+
+/*! @brief Set the BITER field to a new value. */
+#define DMA_WR_BITER_ELINKNO_BITER(base, index, value) (DMA_RMW_BITER_ELINKNO(base, index, DMA_BITER_ELINKNO_BITER_MASK, DMA_BITER_ELINKNO_BITER(value)))
+#define DMA_BWR_BITER_ELINKNO_BITER(base, index, value) (DMA_WR_BITER_ELINKNO_BITER(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMA_BITER_ELINKNO, field ELINK[15] (RW)
+ *
+ * As the channel completes the minor loop, this flag enables the linking to
+ * another channel, defined by BITER[LINKCH]. The link target channel initiates a
+ * channel service request via an internal mechanism that sets the TCDn_CSR[START]
+ * bit of the specified channel. If channel linking is disabled, the BITER value
+ * extends to 15 bits in place of a link channel number. If the major loop is
+ * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
+ * linking. When the software loads the TCD, this field must be set equal to the
+ * corresponding CITER field; otherwise, a configuration error is reported. As the
+ * major iteration count is exhausted, the contents of this field is reloaded
+ * into the CITER field.
+ *
+ * Values:
+ * - 0b0 - The channel-to-channel linking is disabled
+ * - 0b1 - The channel-to-channel linking is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMA_BITER_ELINKNO_ELINK field. */
+#define DMA_RD_BITER_ELINKNO_ELINK(base, index) ((DMA_BITER_ELINKNO_REG(base, index) & DMA_BITER_ELINKNO_ELINK_MASK) >> DMA_BITER_ELINKNO_ELINK_SHIFT)
+#define DMA_BRD_BITER_ELINKNO_ELINK(base, index) (BITBAND_ACCESS16(&DMA_BITER_ELINKNO_REG(base, index), DMA_BITER_ELINKNO_ELINK_SHIFT))
+
+/*! @brief Set the ELINK field to a new value. */
+#define DMA_WR_BITER_ELINKNO_ELINK(base, index, value) (DMA_RMW_BITER_ELINKNO(base, index, DMA_BITER_ELINKNO_ELINK_MASK, DMA_BITER_ELINKNO_ELINK(value)))
+#define DMA_BWR_BITER_ELINKNO_ELINK(base, index, value) (BITBAND_ACCESS16(&DMA_BITER_ELINKNO_REG(base, index), DMA_BITER_ELINKNO_ELINK_SHIFT) = (value))
+/*@}*/
+
+/* Register macros for indexed access to DMA channel priority registers */
+/*
+ * Constants and macros for entire DMA_DCHPRIn register
+ */
+#define DMA_DCHPRIn_INDEX(channel)          (((channel) & ~0x03U) | (3 - ((channel) & 0x03U)))
+#define DMA_DCHPRIn_REG(base, index)        (((volatile uint8_t *)&DMA_DCHPRI3_REG(base))[DMA_DCHPRIn_INDEX(index)])
+#define DMA_RD_DCHPRIn(base, index)         (DMA_DCHPRIn_REG((base), (index)))
+#define DMA_WR_DCHPRIn(base, index, value)  (DMA_DCHPRIn_REG((base), (index)) = (value))
+#define DMA_SET_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) |  (value)))
+#define DMA_CLR_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) & ~(value)))
+#define DMA_TOG_DCHPRIn(base, index, value) (DMA_WR_DCHPRIn((base), (index), DMA_RD_DCHPRIn((base), (index)) ^  (value)))
+
+/*
+ * Register DMA_DCHPRIn, bit field CHPRI
+ */
+/* Read current value of the CHPRI bit field. */
+#define DMA_RD_DCHPRIn_CHPRI(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_CHPRI_MASK) >> DMA_DCHPRI0_CHPRI_SHIFT)
+#define DMA_BRD_DCHPRIn_CHPRI(base, index) (DMA_RD_DCHPRIn_CHPRI((base), (index)))
+
+/* Set the CHPRI bit field to a new value. */
+#define DMA_WR_DCHPRIn_CHPRI(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_CHPRI_MASK) | DMA_DCHPRI0_CHPRI(value)))
+#define DMA_BWR_DCHPRIn_CHPRI(base, index, value) (DMA_WR_DCHPRIn_CHPRI((base), (index), (value)))
+
+/*
+ * Register DMA_DCHPRIn, bit field DPA
+ */
+/* Read current value of the DPA bit field. */
+#define DMA_RD_DCHPRIn_DPA(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_DPA_MASK) >> DMA_DCHPRI0_DPA_SHIFT)
+#define DMA_BRD_DCHPRIn_DPA(base, index) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_DPA_SHIFT))
+
+/* Set the DPA bit field to a new value. */
+#define DMA_WR_DCHPRIn_DPA(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_DPA_MASK) | DMA_DCHPRI0_DPA(value)))
+#define DMA_BWR_DCHPRIn_DPA(base, index, value) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_DPA_SHIFT) = (value))
+
+/*
+ * Register DMA_DCHPRIn, bit field ECP
+ */
+/* Read current value of the ECP bit field. */
+#define DMA_RD_DCHPRIn_ECP(base, index) ((DMA_DCHPRIn_REG((base), (index)) & DMA_DCHPRI0_ECP_MASK) >> DMA_DCHPRI0_ECP_SHIFT)
+#define DMA_BRD_DCHPRIn_ECP(base, index) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_ECP_SHIFT))
+
+/* Set the ECP bit field to a new value. */
+#define DMA_WR_DCHPRIn_ECP(base, index, value) (DMA_WR_DCHPRIn((base), (index), (DMA_RD_DCHPRIn((base), (index)) & ~DMA_DCHPRI0_ECP_MASK) | DMA_DCHPRI0_ECP(value)))
+#define DMA_BWR_DCHPRIn_ECP(base, index, value) (BITBAND_ACCESS8(&DMA_DCHPRIn_REG((base), (index)), DMA_DCHPRI0_ECP_SHIFT) = (value))
+
+/*
+ * MK64F12 DMAMUX
+ *
+ * DMA channel multiplexor
+ *
+ * Registers defined in this header file:
+ * - DMAMUX_CHCFG - Channel Configuration register
+ */
+
+#define DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
+#define DMAMUX_IDX (0U) /*!< Instance number for DMAMUX. */
+
+/*******************************************************************************
+ * DMAMUX_CHCFG - Channel Configuration register
+ ******************************************************************************/
+
+/*!
+ * @brief DMAMUX_CHCFG - Channel Configuration register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Each of the DMA channels can be independently enabled/disabled and associated
+ * with one of the DMA slots (peripheral slots or always-on slots) in the
+ * system. Setting multiple CHCFG registers with the same source value will result in
+ * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
+ * Before changing the trigger or source settings, a DMA channel must be disabled
+ * via CHCFGn[ENBL].
+ */
+/*!
+ * @name Constants and macros for entire DMAMUX_CHCFG register
+ */
+/*@{*/
+#define DMAMUX_RD_CHCFG(base, index) (DMAMUX_CHCFG_REG(base, index))
+#define DMAMUX_WR_CHCFG(base, index, value) (DMAMUX_CHCFG_REG(base, index) = (value))
+#define DMAMUX_RMW_CHCFG(base, index, mask, value) (DMAMUX_WR_CHCFG(base, index, (DMAMUX_RD_CHCFG(base, index) & ~(mask)) | (value)))
+#define DMAMUX_SET_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) |  (value)))
+#define DMAMUX_CLR_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) & ~(value)))
+#define DMAMUX_TOG_CHCFG(base, index, value) (DMAMUX_WR_CHCFG(base, index, DMAMUX_RD_CHCFG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual DMAMUX_CHCFG bitfields
+ */
+
+/*!
+ * @name Register DMAMUX_CHCFG, field SOURCE[5:0] (RW)
+ *
+ * Specifies which DMA source, if any, is routed to a particular DMA channel.
+ * See your device's chip configuration details for information about the
+ * peripherals and their slot numbers.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_SOURCE field. */
+#define DMAMUX_RD_CHCFG_SOURCE(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT)
+#define DMAMUX_BRD_CHCFG_SOURCE(base, index) (DMAMUX_RD_CHCFG_SOURCE(base, index))
+
+/*! @brief Set the SOURCE field to a new value. */
+#define DMAMUX_WR_CHCFG_SOURCE(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_SOURCE_MASK, DMAMUX_CHCFG_SOURCE(value)))
+#define DMAMUX_BWR_CHCFG_SOURCE(base, index, value) (DMAMUX_WR_CHCFG_SOURCE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field TRIG[6] (RW)
+ *
+ * Enables the periodic trigger capability for the triggered DMA channel.
+ *
+ * Values:
+ * - 0b0 - Triggering is disabled. If triggering is disabled and ENBL is set,
+ *     the DMA Channel will simply route the specified source to the DMA channel.
+ *     (Normal mode)
+ * - 0b1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
+ *     DMAMUX is in Periodic Trigger mode.
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_TRIG field. */
+#define DMAMUX_RD_CHCFG_TRIG(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_TRIG_MASK) >> DMAMUX_CHCFG_TRIG_SHIFT)
+#define DMAMUX_BRD_CHCFG_TRIG(base, index) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT))
+
+/*! @brief Set the TRIG field to a new value. */
+#define DMAMUX_WR_CHCFG_TRIG(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_TRIG_MASK, DMAMUX_CHCFG_TRIG(value)))
+#define DMAMUX_BWR_CHCFG_TRIG(base, index, value) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register DMAMUX_CHCFG, field ENBL[7] (RW)
+ *
+ * Enables the DMA channel.
+ *
+ * Values:
+ * - 0b0 - DMA channel is disabled. This mode is primarily used during
+ *     configuration of the DMAMux. The DMA has separate channel enables/disables, which
+ *     should be used to disable or reconfigure a DMA channel.
+ * - 0b1 - DMA channel is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the DMAMUX_CHCFG_ENBL field. */
+#define DMAMUX_RD_CHCFG_ENBL(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT)
+#define DMAMUX_BRD_CHCFG_ENBL(base, index) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT))
+
+/*! @brief Set the ENBL field to a new value. */
+#define DMAMUX_WR_CHCFG_ENBL(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_ENBL_MASK, DMAMUX_CHCFG_ENBL(value)))
+#define DMAMUX_BWR_CHCFG_ENBL(base, index, value) (BITBAND_ACCESS8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 ENET
+ *
+ * Ethernet MAC-NET Core
+ *
+ * Registers defined in this header file:
+ * - ENET_EIR - Interrupt Event Register
+ * - ENET_EIMR - Interrupt Mask Register
+ * - ENET_RDAR - Receive Descriptor Active Register
+ * - ENET_TDAR - Transmit Descriptor Active Register
+ * - ENET_ECR - Ethernet Control Register
+ * - ENET_MMFR - MII Management Frame Register
+ * - ENET_MSCR - MII Speed Control Register
+ * - ENET_MIBC - MIB Control Register
+ * - ENET_RCR - Receive Control Register
+ * - ENET_TCR - Transmit Control Register
+ * - ENET_PALR - Physical Address Lower Register
+ * - ENET_PAUR - Physical Address Upper Register
+ * - ENET_OPD - Opcode/Pause Duration Register
+ * - ENET_IAUR - Descriptor Individual Upper Address Register
+ * - ENET_IALR - Descriptor Individual Lower Address Register
+ * - ENET_GAUR - Descriptor Group Upper Address Register
+ * - ENET_GALR - Descriptor Group Lower Address Register
+ * - ENET_TFWR - Transmit FIFO Watermark Register
+ * - ENET_RDSR - Receive Descriptor Ring Start Register
+ * - ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ * - ENET_MRBR - Maximum Receive Buffer Size Register
+ * - ENET_RSFL - Receive FIFO Section Full Threshold
+ * - ENET_RSEM - Receive FIFO Section Empty Threshold
+ * - ENET_RAEM - Receive FIFO Almost Empty Threshold
+ * - ENET_RAFL - Receive FIFO Almost Full Threshold
+ * - ENET_TSEM - Transmit FIFO Section Empty Threshold
+ * - ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ * - ENET_TAFL - Transmit FIFO Almost Full Threshold
+ * - ENET_TIPG - Transmit Inter-Packet Gap
+ * - ENET_FTRL - Frame Truncation Length
+ * - ENET_TACC - Transmit Accelerator Function Configuration
+ * - ENET_RACC - Receive Accelerator Function Configuration
+ * - ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ * - ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ * - ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ * - ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ * - ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ * - ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ * - ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ * - ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ * - ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ * - ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ * - ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ * - ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ * - ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ * - ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ * - ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ * - ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ * - ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ * - ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ * - ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ * - ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ * - ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ * - ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ * - ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ * - ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ * - ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ * - ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ * - ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ * - ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ * - ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ * - ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ * - ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ * - ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ * - ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ * - ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ * - ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ * - ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ * - ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ * - ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ * - ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ * - ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ * - ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ * - ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ * - ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ * - ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ * - ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ * - ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ * - ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ * - ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ * - ENET_ATCR - Adjustable Timer Control Register
+ * - ENET_ATVR - Timer Value Register
+ * - ENET_ATOFF - Timer Offset Register
+ * - ENET_ATPER - Timer Period Register
+ * - ENET_ATCOR - Timer Correction Register
+ * - ENET_ATINC - Time-Stamping Clock Period Register
+ * - ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ * - ENET_TGSR - Timer Global Status Register
+ * - ENET_TCSR - Timer Control Status Register
+ * - ENET_TCCR - Timer Compare Capture Register
+ */
+
+#define ENET_INSTANCE_COUNT (1U) /*!< Number of instances of the ENET module. */
+#define ENET_IDX (0U) /*!< Instance number for ENET. */
+
+/*******************************************************************************
+ * ENET_EIR - Interrupt Event Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_EIR - Interrupt Event Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an event occurs that sets a bit in EIR, an interrupt occurs if the
+ * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
+ * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
+ * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
+ * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
+ * Legacy mode does not require these flags to be enabled.
+ */
+/*!
+ * @name Constants and macros for entire ENET_EIR register
+ */
+/*@{*/
+#define ENET_RD_EIR(base)        (ENET_EIR_REG(base))
+#define ENET_WR_EIR(base, value) (ENET_EIR_REG(base) = (value))
+#define ENET_RMW_EIR(base, mask, value) (ENET_WR_EIR(base, (ENET_RD_EIR(base) & ~(mask)) | (value)))
+#define ENET_SET_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) |  (value)))
+#define ENET_CLR_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) & ~(value)))
+#define ENET_TOG_EIR(base, value) (ENET_WR_EIR(base, ENET_RD_EIR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_EIR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
+ *
+ * The adjustable timer reached the period event. A period event interrupt can
+ * be generated if ATCR[PEREN] is set and the timer wraps according to the
+ * periodic setting in the ATPER register. Set the timer period value before setting
+ * ATCR[PEREN].
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TS_TIMER field. */
+#define ENET_RD_EIR_TS_TIMER(base) ((ENET_EIR_REG(base) & ENET_EIR_TS_TIMER_MASK) >> ENET_EIR_TS_TIMER_SHIFT)
+#define ENET_BRD_EIR_TS_TIMER(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_TIMER_SHIFT))
+
+/*! @brief Set the TS_TIMER field to a new value. */
+#define ENET_WR_EIR_TS_TIMER(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TS_TIMER(value)))
+#define ENET_BWR_EIR_TS_TIMER(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_TIMER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
+ *
+ * Indicates that the timestamp of the last transmitted timing frame is
+ * available in the ATSTMP register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TS_AVAIL field. */
+#define ENET_RD_EIR_TS_AVAIL(base) ((ENET_EIR_REG(base) & ENET_EIR_TS_AVAIL_MASK) >> ENET_EIR_TS_AVAIL_SHIFT)
+#define ENET_BRD_EIR_TS_AVAIL(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_AVAIL_SHIFT))
+
+/*! @brief Set the TS_AVAIL field to a new value. */
+#define ENET_WR_EIR_TS_AVAIL(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TS_AVAIL_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TS_AVAIL(value)))
+#define ENET_BWR_EIR_TS_AVAIL(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TS_AVAIL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field WAKEUP[17] (W1C)
+ *
+ * Read-only status bit to indicate that a magic packet has been detected. Will
+ * act only if ECR[MAGICEN] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_WAKEUP field. */
+#define ENET_RD_EIR_WAKEUP(base) ((ENET_EIR_REG(base) & ENET_EIR_WAKEUP_MASK) >> ENET_EIR_WAKEUP_SHIFT)
+#define ENET_BRD_EIR_WAKEUP(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_WAKEUP_SHIFT))
+
+/*! @brief Set the WAKEUP field to a new value. */
+#define ENET_WR_EIR_WAKEUP(base, value) (ENET_RMW_EIR(base, (ENET_EIR_WAKEUP_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_WAKEUP(value)))
+#define ENET_BWR_EIR_WAKEUP(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_WAKEUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field PLR[18] (W1C)
+ *
+ * Indicates a frame was received with a payload length error. See Frame
+ * Length/Type Verification: Payload Length Check for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_PLR field. */
+#define ENET_RD_EIR_PLR(base) ((ENET_EIR_REG(base) & ENET_EIR_PLR_MASK) >> ENET_EIR_PLR_SHIFT)
+#define ENET_BRD_EIR_PLR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_PLR_SHIFT))
+
+/*! @brief Set the PLR field to a new value. */
+#define ENET_WR_EIR_PLR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_PLR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_PLR(value)))
+#define ENET_BWR_EIR_PLR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_PLR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field UN[19] (W1C)
+ *
+ * Indicates the transmit FIFO became empty before the complete frame was
+ * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
+ * frame is discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_UN field. */
+#define ENET_RD_EIR_UN(base) ((ENET_EIR_REG(base) & ENET_EIR_UN_MASK) >> ENET_EIR_UN_SHIFT)
+#define ENET_BRD_EIR_UN(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_UN_SHIFT))
+
+/*! @brief Set the UN field to a new value. */
+#define ENET_WR_EIR_UN(base, value) (ENET_RMW_EIR(base, (ENET_EIR_UN_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_UN(value)))
+#define ENET_BWR_EIR_UN(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_UN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RL[20] (W1C)
+ *
+ * Indicates a collision occurred on each of 16 successive attempts to transmit
+ * the frame. The frame is discarded without being transmitted and transmission
+ * of the next frame commences. This error can only occur in half-duplex mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RL field. */
+#define ENET_RD_EIR_RL(base) ((ENET_EIR_REG(base) & ENET_EIR_RL_MASK) >> ENET_EIR_RL_SHIFT)
+#define ENET_BRD_EIR_RL(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RL_SHIFT))
+
+/*! @brief Set the RL field to a new value. */
+#define ENET_WR_EIR_RL(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RL_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RL(value)))
+#define ENET_BWR_EIR_RL(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field LC[21] (W1C)
+ *
+ * Indicates a collision occurred beyond the collision window (slot time) in
+ * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
+ * frame is discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_LC field. */
+#define ENET_RD_EIR_LC(base) ((ENET_EIR_REG(base) & ENET_EIR_LC_MASK) >> ENET_EIR_LC_SHIFT)
+#define ENET_BRD_EIR_LC(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_LC_SHIFT))
+
+/*! @brief Set the LC field to a new value. */
+#define ENET_WR_EIR_LC(base, value) (ENET_RMW_EIR(base, (ENET_EIR_LC_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_LC(value)))
+#define ENET_BWR_EIR_LC(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_LC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field EBERR[22] (W1C)
+ *
+ * Indicates a system bus error occurred when a uDMA transaction is underway.
+ * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
+ * MAC. When this occurs, software must ensure proper actions, possibly resetting
+ * the system, to resume normal operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_EBERR field. */
+#define ENET_RD_EIR_EBERR(base) ((ENET_EIR_REG(base) & ENET_EIR_EBERR_MASK) >> ENET_EIR_EBERR_SHIFT)
+#define ENET_BRD_EIR_EBERR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_EBERR_SHIFT))
+
+/*! @brief Set the EBERR field to a new value. */
+#define ENET_WR_EIR_EBERR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_EBERR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_EBERR(value)))
+#define ENET_BWR_EIR_EBERR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_EBERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field MII[23] (W1C)
+ *
+ * Indicates that the MII has completed the data transfer requested.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_MII field. */
+#define ENET_RD_EIR_MII(base) ((ENET_EIR_REG(base) & ENET_EIR_MII_MASK) >> ENET_EIR_MII_SHIFT)
+#define ENET_BRD_EIR_MII(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_MII_SHIFT))
+
+/*! @brief Set the MII field to a new value. */
+#define ENET_WR_EIR_MII(base, value) (ENET_RMW_EIR(base, (ENET_EIR_MII_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_MII(value)))
+#define ENET_BWR_EIR_MII(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_MII_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RXB[24] (W1C)
+ *
+ * Indicates a receive buffer descriptor is not the last in the frame has been
+ * updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RXB field. */
+#define ENET_RD_EIR_RXB(base) ((ENET_EIR_REG(base) & ENET_EIR_RXB_MASK) >> ENET_EIR_RXB_SHIFT)
+#define ENET_BRD_EIR_RXB(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXB_SHIFT))
+
+/*! @brief Set the RXB field to a new value. */
+#define ENET_WR_EIR_RXB(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RXB_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RXB(value)))
+#define ENET_BWR_EIR_RXB(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field RXF[25] (W1C)
+ *
+ * Indicates a frame has been received and the last corresponding buffer
+ * descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_RXF field. */
+#define ENET_RD_EIR_RXF(base) ((ENET_EIR_REG(base) & ENET_EIR_RXF_MASK) >> ENET_EIR_RXF_SHIFT)
+#define ENET_BRD_EIR_RXF(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXF_SHIFT))
+
+/*! @brief Set the RXF field to a new value. */
+#define ENET_WR_EIR_RXF(base, value) (ENET_RMW_EIR(base, (ENET_EIR_RXF_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_RXF(value)))
+#define ENET_BWR_EIR_RXF(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TXB[26] (W1C)
+ *
+ * Indicates a transmit buffer descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TXB field. */
+#define ENET_RD_EIR_TXB(base) ((ENET_EIR_REG(base) & ENET_EIR_TXB_MASK) >> ENET_EIR_TXB_SHIFT)
+#define ENET_BRD_EIR_TXB(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXB_SHIFT))
+
+/*! @brief Set the TXB field to a new value. */
+#define ENET_WR_EIR_TXB(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TXB_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TXB(value)))
+#define ENET_BWR_EIR_TXB(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field TXF[27] (W1C)
+ *
+ * Indicates a frame has been transmitted and the last corresponding buffer
+ * descriptor has been updated.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_TXF field. */
+#define ENET_RD_EIR_TXF(base) ((ENET_EIR_REG(base) & ENET_EIR_TXF_MASK) >> ENET_EIR_TXF_SHIFT)
+#define ENET_BRD_EIR_TXF(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXF_SHIFT))
+
+/*! @brief Set the TXF field to a new value. */
+#define ENET_WR_EIR_TXF(base, value) (ENET_RMW_EIR(base, (ENET_EIR_TXF_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_TXF(value)))
+#define ENET_BWR_EIR_TXF(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field GRA[28] (W1C)
+ *
+ * This interrupt is asserted after the transmitter is put into a pause state
+ * after completion of the frame currently being transmitted. See Graceful Transmit
+ * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
+ * asserted only when the TX transitions into the stopped state. If this bit is
+ * cleared by writing 1 and the TX is still stopped, the bit is not set again.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_GRA field. */
+#define ENET_RD_EIR_GRA(base) ((ENET_EIR_REG(base) & ENET_EIR_GRA_MASK) >> ENET_EIR_GRA_SHIFT)
+#define ENET_BRD_EIR_GRA(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_GRA_SHIFT))
+
+/*! @brief Set the GRA field to a new value. */
+#define ENET_WR_EIR_GRA(base, value) (ENET_RMW_EIR(base, (ENET_EIR_GRA_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_BABT_MASK | ENET_EIR_BABR_MASK), ENET_EIR_GRA(value)))
+#define ENET_BWR_EIR_GRA(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_GRA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field BABT[29] (W1C)
+ *
+ * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
+ * this condition is caused when a frame that is too long is placed into the
+ * transmit data buffer(s). Truncation does not occur.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_BABT field. */
+#define ENET_RD_EIR_BABT(base) ((ENET_EIR_REG(base) & ENET_EIR_BABT_MASK) >> ENET_EIR_BABT_SHIFT)
+#define ENET_BRD_EIR_BABT(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABT_SHIFT))
+
+/*! @brief Set the BABT field to a new value. */
+#define ENET_WR_EIR_BABT(base, value) (ENET_RMW_EIR(base, (ENET_EIR_BABT_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABR_MASK), ENET_EIR_BABT(value)))
+#define ENET_BWR_EIR_BABT(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIR, field BABR[30] (W1C)
+ *
+ * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIR_BABR field. */
+#define ENET_RD_EIR_BABR(base) ((ENET_EIR_REG(base) & ENET_EIR_BABR_MASK) >> ENET_EIR_BABR_SHIFT)
+#define ENET_BRD_EIR_BABR(base) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABR_SHIFT))
+
+/*! @brief Set the BABR field to a new value. */
+#define ENET_WR_EIR_BABR(base, value) (ENET_RMW_EIR(base, (ENET_EIR_BABR_MASK | ENET_EIR_TS_TIMER_MASK | ENET_EIR_TS_AVAIL_MASK | ENET_EIR_WAKEUP_MASK | ENET_EIR_PLR_MASK | ENET_EIR_UN_MASK | ENET_EIR_RL_MASK | ENET_EIR_LC_MASK | ENET_EIR_EBERR_MASK | ENET_EIR_MII_MASK | ENET_EIR_RXB_MASK | ENET_EIR_RXF_MASK | ENET_EIR_TXB_MASK | ENET_EIR_TXF_MASK | ENET_EIR_GRA_MASK | ENET_EIR_BABT_MASK), ENET_EIR_BABR(value)))
+#define ENET_BWR_EIR_BABR(base, value) (BITBAND_ACCESS32(&ENET_EIR_REG(base), ENET_EIR_BABR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_EIMR - Interrupt Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_EIMR - Interrupt Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * EIMR controls which interrupt events are allowed to generate actual
+ * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
+ * and EIMR registers are set, an interrupt is generated. The interrupt signal
+ * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
+ * 0 is written to the EIMR field.
+ */
+/*!
+ * @name Constants and macros for entire ENET_EIMR register
+ */
+/*@{*/
+#define ENET_RD_EIMR(base)       (ENET_EIMR_REG(base))
+#define ENET_WR_EIMR(base, value) (ENET_EIMR_REG(base) = (value))
+#define ENET_RMW_EIMR(base, mask, value) (ENET_WR_EIMR(base, (ENET_RD_EIMR(base) & ~(mask)) | (value)))
+#define ENET_SET_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) |  (value)))
+#define ENET_CLR_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) & ~(value)))
+#define ENET_TOG_EIMR(base, value) (ENET_WR_EIMR(base, ENET_RD_EIMR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_EIMR bitfields
+ */
+
+/*!
+ * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_TIMER field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TS_TIMER field. */
+#define ENET_RD_EIMR_TS_TIMER(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TS_TIMER_MASK) >> ENET_EIMR_TS_TIMER_SHIFT)
+#define ENET_BRD_EIMR_TS_TIMER(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_TIMER_SHIFT))
+
+/*! @brief Set the TS_TIMER field to a new value. */
+#define ENET_WR_EIMR_TS_TIMER(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TS_TIMER_MASK, ENET_EIMR_TS_TIMER(value)))
+#define ENET_BWR_EIMR_TS_TIMER(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_TIMER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
+ *
+ * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TS_AVAIL field. */
+#define ENET_RD_EIMR_TS_AVAIL(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TS_AVAIL_MASK) >> ENET_EIMR_TS_AVAIL_SHIFT)
+#define ENET_BRD_EIMR_TS_AVAIL(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_AVAIL_SHIFT))
+
+/*! @brief Set the TS_AVAIL field to a new value. */
+#define ENET_WR_EIMR_TS_AVAIL(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TS_AVAIL_MASK, ENET_EIMR_TS_AVAIL(value)))
+#define ENET_BWR_EIMR_TS_AVAIL(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TS_AVAIL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field WAKEUP[17] (RW)
+ *
+ * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
+ * an interrupt condition can generate an interrupt. At every module clock, the
+ * EIR samples the signal generated by the interrupting source. The corresponding
+ * EIR WAKEUP field reflects the state of the interrupt signal even if the
+ * corresponding EIMR field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_WAKEUP field. */
+#define ENET_RD_EIMR_WAKEUP(base) ((ENET_EIMR_REG(base) & ENET_EIMR_WAKEUP_MASK) >> ENET_EIMR_WAKEUP_SHIFT)
+#define ENET_BRD_EIMR_WAKEUP(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_WAKEUP_SHIFT))
+
+/*! @brief Set the WAKEUP field to a new value. */
+#define ENET_WR_EIMR_WAKEUP(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_WAKEUP_MASK, ENET_EIMR_WAKEUP(value)))
+#define ENET_BWR_EIMR_WAKEUP(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_WAKEUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field PLR[18] (RW)
+ *
+ * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR PLR field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_PLR field. */
+#define ENET_RD_EIMR_PLR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_PLR_MASK) >> ENET_EIMR_PLR_SHIFT)
+#define ENET_BRD_EIMR_PLR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_PLR_SHIFT))
+
+/*! @brief Set the PLR field to a new value. */
+#define ENET_WR_EIMR_PLR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_PLR_MASK, ENET_EIMR_PLR(value)))
+#define ENET_BWR_EIMR_PLR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_PLR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field UN[19] (RW)
+ *
+ * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR UN field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_UN field. */
+#define ENET_RD_EIMR_UN(base) ((ENET_EIMR_REG(base) & ENET_EIMR_UN_MASK) >> ENET_EIMR_UN_SHIFT)
+#define ENET_BRD_EIMR_UN(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_UN_SHIFT))
+
+/*! @brief Set the UN field to a new value. */
+#define ENET_WR_EIMR_UN(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_UN_MASK, ENET_EIMR_UN(value)))
+#define ENET_BWR_EIMR_UN(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_UN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RL[20] (RW)
+ *
+ * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR RL field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RL field. */
+#define ENET_RD_EIMR_RL(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RL_MASK) >> ENET_EIMR_RL_SHIFT)
+#define ENET_BRD_EIMR_RL(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RL_SHIFT))
+
+/*! @brief Set the RL field to a new value. */
+#define ENET_WR_EIMR_RL(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RL_MASK, ENET_EIMR_RL(value)))
+#define ENET_BWR_EIMR_RL(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field LC[21] (RW)
+ *
+ * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples the
+ * signal generated by the interrupting source. The corresponding EIR LC field
+ * reflects the state of the interrupt signal even if the corresponding EIMR field
+ * is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_LC field. */
+#define ENET_RD_EIMR_LC(base) ((ENET_EIMR_REG(base) & ENET_EIMR_LC_MASK) >> ENET_EIMR_LC_SHIFT)
+#define ENET_BRD_EIMR_LC(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_LC_SHIFT))
+
+/*! @brief Set the LC field to a new value. */
+#define ENET_WR_EIMR_LC(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_LC_MASK, ENET_EIMR_LC(value)))
+#define ENET_BWR_EIMR_LC(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_LC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field EBERR[22] (RW)
+ *
+ * Corresponds to interrupt source EIR[EBERR] and determines whether an
+ * interrupt condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR EBERR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_EBERR field. */
+#define ENET_RD_EIMR_EBERR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_EBERR_MASK) >> ENET_EIMR_EBERR_SHIFT)
+#define ENET_BRD_EIMR_EBERR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_EBERR_SHIFT))
+
+/*! @brief Set the EBERR field to a new value. */
+#define ENET_WR_EIMR_EBERR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_EBERR_MASK, ENET_EIMR_EBERR(value)))
+#define ENET_BWR_EIMR_EBERR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_EBERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field MII[23] (RW)
+ *
+ * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR MII field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_MII field. */
+#define ENET_RD_EIMR_MII(base) ((ENET_EIMR_REG(base) & ENET_EIMR_MII_MASK) >> ENET_EIMR_MII_SHIFT)
+#define ENET_BRD_EIMR_MII(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_MII_SHIFT))
+
+/*! @brief Set the MII field to a new value. */
+#define ENET_WR_EIMR_MII(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_MII_MASK, ENET_EIMR_MII(value)))
+#define ENET_BWR_EIMR_MII(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_MII_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RXB[24] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXB field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RXB field. */
+#define ENET_RD_EIMR_RXB(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RXB_MASK) >> ENET_EIMR_RXB_SHIFT)
+#define ENET_BRD_EIMR_RXB(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXB_SHIFT))
+
+/*! @brief Set the RXB field to a new value. */
+#define ENET_WR_EIMR_RXB(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RXB_MASK, ENET_EIMR_RXB(value)))
+#define ENET_BWR_EIMR_RXB(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field RXF[25] (RW)
+ *
+ * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR RXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_RXF field. */
+#define ENET_RD_EIMR_RXF(base) ((ENET_EIMR_REG(base) & ENET_EIMR_RXF_MASK) >> ENET_EIMR_RXF_SHIFT)
+#define ENET_BRD_EIMR_RXF(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXF_SHIFT))
+
+/*! @brief Set the RXF field to a new value. */
+#define ENET_WR_EIMR_RXF(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_RXF_MASK, ENET_EIMR_RXF(value)))
+#define ENET_BWR_EIMR_RXF(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TXB[26] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TXB field. */
+#define ENET_RD_EIMR_TXB(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TXB_MASK) >> ENET_EIMR_TXB_SHIFT)
+#define ENET_BRD_EIMR_TXB(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXB_SHIFT))
+
+/*! @brief Set the TXB field to a new value. */
+#define ENET_WR_EIMR_TXB(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TXB_MASK, ENET_EIMR_TXB(value)))
+#define ENET_BWR_EIMR_TXB(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field TXF[27] (RW)
+ *
+ * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR TXF field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_TXF field. */
+#define ENET_RD_EIMR_TXF(base) ((ENET_EIMR_REG(base) & ENET_EIMR_TXF_MASK) >> ENET_EIMR_TXF_SHIFT)
+#define ENET_BRD_EIMR_TXF(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXF_SHIFT))
+
+/*! @brief Set the TXF field to a new value. */
+#define ENET_WR_EIMR_TXF(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_TXF_MASK, ENET_EIMR_TXF(value)))
+#define ENET_BWR_EIMR_TXF(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field GRA[28] (RW)
+ *
+ * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR GRA field
+ * reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_GRA field. */
+#define ENET_RD_EIMR_GRA(base) ((ENET_EIMR_REG(base) & ENET_EIMR_GRA_MASK) >> ENET_EIMR_GRA_SHIFT)
+#define ENET_BRD_EIMR_GRA(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_GRA_SHIFT))
+
+/*! @brief Set the GRA field to a new value. */
+#define ENET_WR_EIMR_GRA(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_GRA_MASK, ENET_EIMR_GRA(value)))
+#define ENET_BWR_EIMR_GRA(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_GRA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field BABT[29] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABT
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_BABT field. */
+#define ENET_RD_EIMR_BABT(base) ((ENET_EIMR_REG(base) & ENET_EIMR_BABT_MASK) >> ENET_EIMR_BABT_SHIFT)
+#define ENET_BRD_EIMR_BABT(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABT_SHIFT))
+
+/*! @brief Set the BABT field to a new value. */
+#define ENET_WR_EIMR_BABT(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_BABT_MASK, ENET_EIMR_BABT(value)))
+#define ENET_BWR_EIMR_BABT(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_EIMR, field BABR[30] (RW)
+ *
+ * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
+ * condition can generate an interrupt. At every module clock, the EIR samples
+ * the signal generated by the interrupting source. The corresponding EIR BABR
+ * field reflects the state of the interrupt signal even if the corresponding EIMR
+ * field is cleared.
+ *
+ * Values:
+ * - 0b0 - The corresponding interrupt source is masked.
+ * - 0b1 - The corresponding interrupt source is not masked.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_EIMR_BABR field. */
+#define ENET_RD_EIMR_BABR(base) ((ENET_EIMR_REG(base) & ENET_EIMR_BABR_MASK) >> ENET_EIMR_BABR_SHIFT)
+#define ENET_BRD_EIMR_BABR(base) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABR_SHIFT))
+
+/*! @brief Set the BABR field to a new value. */
+#define ENET_WR_EIMR_BABR(base, value) (ENET_RMW_EIMR(base, ENET_EIMR_BABR_MASK, ENET_EIMR_BABR(value)))
+#define ENET_BWR_EIMR_BABR(base, value) (BITBAND_ACCESS32(&ENET_EIMR_REG(base), ENET_EIMR_BABR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RDAR - Receive Descriptor Active Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RDAR - Receive Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDAR is a command register, written by the user, to indicate that the receive
+ * descriptor ring has been updated, that is, that the driver produced empty
+ * receive buffers with the empty bit set.
+ */
+/*!
+ * @name Constants and macros for entire ENET_RDAR register
+ */
+/*@{*/
+#define ENET_RD_RDAR(base)       (ENET_RDAR_REG(base))
+#define ENET_WR_RDAR(base, value) (ENET_RDAR_REG(base) = (value))
+#define ENET_RMW_RDAR(base, mask, value) (ENET_WR_RDAR(base, (ENET_RD_RDAR(base) & ~(mask)) | (value)))
+#define ENET_SET_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) |  (value)))
+#define ENET_CLR_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) & ~(value)))
+#define ENET_TOG_RDAR(base, value) (ENET_WR_RDAR(base, ENET_RD_RDAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDAR, field RDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This field is cleared by the MAC device when no additional empty
+ * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
+ * from set to cleared or when ECR[RESET] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RDAR_RDAR field. */
+#define ENET_RD_RDAR_RDAR(base) ((ENET_RDAR_REG(base) & ENET_RDAR_RDAR_MASK) >> ENET_RDAR_RDAR_SHIFT)
+#define ENET_BRD_RDAR_RDAR(base) (BITBAND_ACCESS32(&ENET_RDAR_REG(base), ENET_RDAR_RDAR_SHIFT))
+
+/*! @brief Set the RDAR field to a new value. */
+#define ENET_WR_RDAR_RDAR(base, value) (ENET_RMW_RDAR(base, ENET_RDAR_RDAR_MASK, ENET_RDAR_RDAR(value)))
+#define ENET_BWR_RDAR_RDAR(base, value) (BITBAND_ACCESS32(&ENET_RDAR_REG(base), ENET_RDAR_RDAR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TDAR - Transmit Descriptor Active Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TDAR - Transmit Descriptor Active Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The TDAR is a command register that the user writes to indicate that the
+ * transmit descriptor ring has been updated, that is, that transmit buffers have
+ * been produced by the driver with the ready bit set in the buffer descriptor. The
+ * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
+ * cleared, or when ECR[RESET] is set.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TDAR register
+ */
+/*@{*/
+#define ENET_RD_TDAR(base)       (ENET_TDAR_REG(base))
+#define ENET_WR_TDAR(base, value) (ENET_TDAR_REG(base) = (value))
+#define ENET_RMW_TDAR(base, mask, value) (ENET_WR_TDAR(base, (ENET_RD_TDAR(base) & ~(mask)) | (value)))
+#define ENET_SET_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) |  (value)))
+#define ENET_CLR_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) & ~(value)))
+#define ENET_TOG_TDAR(base, value) (ENET_WR_TDAR(base, ENET_RD_TDAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TDAR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDAR, field TDAR[24] (RW)
+ *
+ * Always set to 1 when this register is written, regardless of the value
+ * written. This bit is cleared by the MAC device when no additional ready descriptors
+ * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
+ * set to cleared or when ECR[RESET] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TDAR_TDAR field. */
+#define ENET_RD_TDAR_TDAR(base) ((ENET_TDAR_REG(base) & ENET_TDAR_TDAR_MASK) >> ENET_TDAR_TDAR_SHIFT)
+#define ENET_BRD_TDAR_TDAR(base) (BITBAND_ACCESS32(&ENET_TDAR_REG(base), ENET_TDAR_TDAR_SHIFT))
+
+/*! @brief Set the TDAR field to a new value. */
+#define ENET_WR_TDAR_TDAR(base, value) (ENET_RMW_TDAR(base, ENET_TDAR_TDAR_MASK, ENET_TDAR_TDAR(value)))
+#define ENET_BWR_TDAR_TDAR(base, value) (BITBAND_ACCESS32(&ENET_TDAR_REG(base), ENET_TDAR_TDAR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ECR - Ethernet Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ECR - Ethernet Control Register (RW)
+ *
+ * Reset value: 0xF0000000U
+ *
+ * ECR is a read/write user register, though hardware may also alter fields in
+ * this register. It controls many of the high level features of the Ethernet MAC,
+ * including legacy FEC support through the EN1588 field.
+ */
+/*!
+ * @name Constants and macros for entire ENET_ECR register
+ */
+/*@{*/
+#define ENET_RD_ECR(base)        (ENET_ECR_REG(base))
+#define ENET_WR_ECR(base, value) (ENET_ECR_REG(base) = (value))
+#define ENET_RMW_ECR(base, mask, value) (ENET_WR_ECR(base, (ENET_RD_ECR(base) & ~(mask)) | (value)))
+#define ENET_SET_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) |  (value)))
+#define ENET_CLR_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) & ~(value)))
+#define ENET_TOG_ECR(base, value) (ENET_WR_ECR(base, ENET_RD_ECR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ECR bitfields
+ */
+
+/*!
+ * @name Register ENET_ECR, field RESET[0] (RW)
+ *
+ * When this field is set, it clears the ETHEREN field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_RESET field. */
+#define ENET_RD_ECR_RESET(base) ((ENET_ECR_REG(base) & ENET_ECR_RESET_MASK) >> ENET_ECR_RESET_SHIFT)
+#define ENET_BRD_ECR_RESET(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_RESET_SHIFT))
+
+/*! @brief Set the RESET field to a new value. */
+#define ENET_WR_ECR_RESET(base, value) (ENET_RMW_ECR(base, ENET_ECR_RESET_MASK, ENET_ECR_RESET(value)))
+#define ENET_BWR_ECR_RESET(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_RESET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field ETHEREN[1] (RW)
+ *
+ * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
+ * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
+ * descriptor, and FIFO control logic are reset, including the buffer descriptor and
+ * FIFO pointers. Hardware clears this field under the following conditions: RESET
+ * is set by software An error condition causes the EBERR field to set. ETHEREN
+ * must be set at the very last step during ENET
+ * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
+ * is cleared to 0 by software then then next time ETHEREN is set, the EIR
+ * interrupts must cleared to 0 due to previous pending interrupts.
+ *
+ * Values:
+ * - 0b0 - Reception immediately stops and transmission stops after a bad CRC is
+ *     appended to any currently transmitted frame.
+ * - 0b1 - MAC is enabled, and reception and transmission are possible.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_ETHEREN field. */
+#define ENET_RD_ECR_ETHEREN(base) ((ENET_ECR_REG(base) & ENET_ECR_ETHEREN_MASK) >> ENET_ECR_ETHEREN_SHIFT)
+#define ENET_BRD_ECR_ETHEREN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_ETHEREN_SHIFT))
+
+/*! @brief Set the ETHEREN field to a new value. */
+#define ENET_WR_ECR_ETHEREN(base, value) (ENET_RMW_ECR(base, ENET_ECR_ETHEREN_MASK, ENET_ECR_ETHEREN(value)))
+#define ENET_BWR_ECR_ETHEREN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_ETHEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field MAGICEN[2] (RW)
+ *
+ * Enables/disables magic packet detection. MAGICEN is relevant only if the
+ * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
+ * sleep mode and magic packet detection.
+ *
+ * Values:
+ * - 0b0 - Magic detection logic disabled.
+ * - 0b1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a
+ *     frame is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_MAGICEN field. */
+#define ENET_RD_ECR_MAGICEN(base) ((ENET_ECR_REG(base) & ENET_ECR_MAGICEN_MASK) >> ENET_ECR_MAGICEN_SHIFT)
+#define ENET_BRD_ECR_MAGICEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_MAGICEN_SHIFT))
+
+/*! @brief Set the MAGICEN field to a new value. */
+#define ENET_WR_ECR_MAGICEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_MAGICEN_MASK, ENET_ECR_MAGICEN(value)))
+#define ENET_BWR_ECR_MAGICEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_MAGICEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field SLEEP[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal operating mode.
+ * - 0b1 - Sleep mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_SLEEP field. */
+#define ENET_RD_ECR_SLEEP(base) ((ENET_ECR_REG(base) & ENET_ECR_SLEEP_MASK) >> ENET_ECR_SLEEP_SHIFT)
+#define ENET_BRD_ECR_SLEEP(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_SLEEP_SHIFT))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define ENET_WR_ECR_SLEEP(base, value) (ENET_RMW_ECR(base, ENET_ECR_SLEEP_MASK, ENET_ECR_SLEEP(value)))
+#define ENET_BWR_ECR_SLEEP(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_SLEEP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field EN1588[4] (RW)
+ *
+ * Enables enhanced functionality of the MAC.
+ *
+ * Values:
+ * - 0b0 - Legacy FEC buffer descriptors and functions enabled.
+ * - 0b1 - Enhanced frame time-stamping functions enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_EN1588 field. */
+#define ENET_RD_ECR_EN1588(base) ((ENET_ECR_REG(base) & ENET_ECR_EN1588_MASK) >> ENET_ECR_EN1588_SHIFT)
+#define ENET_BRD_ECR_EN1588(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_EN1588_SHIFT))
+
+/*! @brief Set the EN1588 field to a new value. */
+#define ENET_WR_ECR_EN1588(base, value) (ENET_RMW_ECR(base, ENET_ECR_EN1588_MASK, ENET_ECR_EN1588(value)))
+#define ENET_BWR_ECR_EN1588(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_EN1588_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field DBGEN[6] (RW)
+ *
+ * Enables the MAC to enter hardware freeze mode when the device enters debug
+ * mode.
+ *
+ * Values:
+ * - 0b0 - MAC continues operation in debug mode.
+ * - 0b1 - MAC enters hardware freeze mode when the processor is in debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_DBGEN field. */
+#define ENET_RD_ECR_DBGEN(base) ((ENET_ECR_REG(base) & ENET_ECR_DBGEN_MASK) >> ENET_ECR_DBGEN_SHIFT)
+#define ENET_BRD_ECR_DBGEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBGEN_SHIFT))
+
+/*! @brief Set the DBGEN field to a new value. */
+#define ENET_WR_ECR_DBGEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_DBGEN_MASK, ENET_ECR_DBGEN(value)))
+#define ENET_BWR_ECR_DBGEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field STOPEN[7] (RW)
+ *
+ * Controls device behavior in doze mode. In doze mode, if this field is set
+ * then all the clocks of the ENET assembly are disabled, except the RMII /MII
+ * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
+ * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
+ * can still wake the system after receiving a magic packet in stop mode. MAGICEN
+ * must be set prior to entering sleep/stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_STOPEN field. */
+#define ENET_RD_ECR_STOPEN(base) ((ENET_ECR_REG(base) & ENET_ECR_STOPEN_MASK) >> ENET_ECR_STOPEN_SHIFT)
+#define ENET_BRD_ECR_STOPEN(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_STOPEN_SHIFT))
+
+/*! @brief Set the STOPEN field to a new value. */
+#define ENET_WR_ECR_STOPEN(base, value) (ENET_RMW_ECR(base, ENET_ECR_STOPEN_MASK, ENET_ECR_STOPEN(value)))
+#define ENET_BWR_ECR_STOPEN(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_STOPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ECR, field DBSWP[8] (RW)
+ *
+ * Swaps the byte locations of the buffer descriptors. This field must be
+ * written to 1 after reset.
+ *
+ * Values:
+ * - 0b0 - The buffer descriptor bytes are not swapped to support big-endian
+ *     devices.
+ * - 0b1 - The buffer descriptor bytes are swapped to support little-endian
+ *     devices.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ECR_DBSWP field. */
+#define ENET_RD_ECR_DBSWP(base) ((ENET_ECR_REG(base) & ENET_ECR_DBSWP_MASK) >> ENET_ECR_DBSWP_SHIFT)
+#define ENET_BRD_ECR_DBSWP(base) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBSWP_SHIFT))
+
+/*! @brief Set the DBSWP field to a new value. */
+#define ENET_WR_ECR_DBSWP(base, value) (ENET_RMW_ECR(base, ENET_ECR_DBSWP_MASK, ENET_ECR_DBSWP(value)))
+#define ENET_BWR_ECR_DBSWP(base, value) (BITBAND_ACCESS32(&ENET_ECR_REG(base), ENET_ECR_DBSWP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MMFR - MII Management Frame Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MMFR - MII Management Frame Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Writing to MMFR triggers a management frame transaction to the PHY device
+ * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
+ * during a write to MMFR, an MII frame is generated with the data previously written
+ * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
+ * MSCR is currently zero. If the MMFR register is written while frame generation is
+ * in progress, the frame contents are altered. Software must use the EIR[MII]
+ * interrupt indication to avoid writing to the MMFR register while frame
+ * generation is in progress.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MMFR register
+ */
+/*@{*/
+#define ENET_RD_MMFR(base)       (ENET_MMFR_REG(base))
+#define ENET_WR_MMFR(base, value) (ENET_MMFR_REG(base) = (value))
+#define ENET_RMW_MMFR(base, mask, value) (ENET_WR_MMFR(base, (ENET_RD_MMFR(base) & ~(mask)) | (value)))
+#define ENET_SET_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) |  (value)))
+#define ENET_CLR_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) & ~(value)))
+#define ENET_TOG_MMFR(base, value) (ENET_WR_MMFR(base, ENET_RD_MMFR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MMFR bitfields
+ */
+
+/*!
+ * @name Register ENET_MMFR, field DATA[15:0] (RW)
+ *
+ * This is the field for data to be written to or read from the PHY register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_DATA field. */
+#define ENET_RD_MMFR_DATA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT)
+#define ENET_BRD_MMFR_DATA(base) (ENET_RD_MMFR_DATA(base))
+
+/*! @brief Set the DATA field to a new value. */
+#define ENET_WR_MMFR_DATA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_DATA_MASK, ENET_MMFR_DATA(value)))
+#define ENET_BWR_MMFR_DATA(base, value) (ENET_WR_MMFR_DATA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field TA[17:16] (RW)
+ *
+ * This field must be programmed to 10 to generate a valid MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_TA field. */
+#define ENET_RD_MMFR_TA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_TA_MASK) >> ENET_MMFR_TA_SHIFT)
+#define ENET_BRD_MMFR_TA(base) (ENET_RD_MMFR_TA(base))
+
+/*! @brief Set the TA field to a new value. */
+#define ENET_WR_MMFR_TA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_TA_MASK, ENET_MMFR_TA(value)))
+#define ENET_BWR_MMFR_TA(base, value) (ENET_WR_MMFR_TA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field RA[22:18] (RW)
+ *
+ * Specifies one of up to 32 registers within the specified PHY device.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_RA field. */
+#define ENET_RD_MMFR_RA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_RA_MASK) >> ENET_MMFR_RA_SHIFT)
+#define ENET_BRD_MMFR_RA(base) (ENET_RD_MMFR_RA(base))
+
+/*! @brief Set the RA field to a new value. */
+#define ENET_WR_MMFR_RA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_RA_MASK, ENET_MMFR_RA(value)))
+#define ENET_BWR_MMFR_RA(base, value) (ENET_WR_MMFR_RA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field PA[27:23] (RW)
+ *
+ * Specifies one of up to 32 attached PHY devices.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_PA field. */
+#define ENET_RD_MMFR_PA(base) ((ENET_MMFR_REG(base) & ENET_MMFR_PA_MASK) >> ENET_MMFR_PA_SHIFT)
+#define ENET_BRD_MMFR_PA(base) (ENET_RD_MMFR_PA(base))
+
+/*! @brief Set the PA field to a new value. */
+#define ENET_WR_MMFR_PA(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_PA_MASK, ENET_MMFR_PA(value)))
+#define ENET_BWR_MMFR_PA(base, value) (ENET_WR_MMFR_PA(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field OP[29:28] (RW)
+ *
+ * Determines the frame operation.
+ *
+ * Values:
+ * - 0b00 - Write frame operation, but not MII compliant.
+ * - 0b01 - Write frame operation for a valid MII management frame.
+ * - 0b10 - Read frame operation for a valid MII management frame.
+ * - 0b11 - Read frame operation, but not MII compliant.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_OP field. */
+#define ENET_RD_MMFR_OP(base) ((ENET_MMFR_REG(base) & ENET_MMFR_OP_MASK) >> ENET_MMFR_OP_SHIFT)
+#define ENET_BRD_MMFR_OP(base) (ENET_RD_MMFR_OP(base))
+
+/*! @brief Set the OP field to a new value. */
+#define ENET_WR_MMFR_OP(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_OP_MASK, ENET_MMFR_OP(value)))
+#define ENET_BWR_MMFR_OP(base, value) (ENET_WR_MMFR_OP(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MMFR, field ST[31:30] (RW)
+ *
+ * These fields must be programmed to 01 for a valid MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MMFR_ST field. */
+#define ENET_RD_MMFR_ST(base) ((ENET_MMFR_REG(base) & ENET_MMFR_ST_MASK) >> ENET_MMFR_ST_SHIFT)
+#define ENET_BRD_MMFR_ST(base) (ENET_RD_MMFR_ST(base))
+
+/*! @brief Set the ST field to a new value. */
+#define ENET_WR_MMFR_ST(base, value) (ENET_RMW_MMFR(base, ENET_MMFR_ST_MASK, ENET_MMFR_ST(value)))
+#define ENET_BWR_MMFR_ST(base, value) (ENET_WR_MMFR_ST(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MSCR - MII Speed Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MSCR - MII Speed Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * MSCR provides control of the MII clock (MDC pin) frequency and allows a
+ * preamble drop on the MII management frame. The MII_SPEED field must be programmed
+ * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
+ * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
+ * a non-zero value to source a read or write management frame. After the
+ * management frame is complete, the MSCR register may optionally be cleared to turn
+ * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
+ * changes during operation. This change takes effect following a rising or falling
+ * edge of MDC. If the internal module clock is 25 MHz, programming this register
+ * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
+ * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
+ * MII_SPEED as a function of internal module clock frequency. Programming Examples
+ * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
+ * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
+ * 0xD 2.36 MHz
+ */
+/*!
+ * @name Constants and macros for entire ENET_MSCR register
+ */
+/*@{*/
+#define ENET_RD_MSCR(base)       (ENET_MSCR_REG(base))
+#define ENET_WR_MSCR(base, value) (ENET_MSCR_REG(base) = (value))
+#define ENET_RMW_MSCR(base, mask, value) (ENET_WR_MSCR(base, (ENET_RD_MSCR(base) & ~(mask)) | (value)))
+#define ENET_SET_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) |  (value)))
+#define ENET_CLR_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) & ~(value)))
+#define ENET_TOG_MSCR(base, value) (ENET_WR_MSCR(base, ENET_RD_MSCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MSCR bitfields
+ */
+
+/*!
+ * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
+ *
+ * Controls the frequency of the MII management interface clock (MDC) relative
+ * to the internal module clock. A value of 0 in this field turns off MDC and
+ * leaves it in low voltage state. Any non-zero value results in the MDC frequency
+ * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_MII_SPEED field. */
+#define ENET_RD_MSCR_MII_SPEED(base) ((ENET_MSCR_REG(base) & ENET_MSCR_MII_SPEED_MASK) >> ENET_MSCR_MII_SPEED_SHIFT)
+#define ENET_BRD_MSCR_MII_SPEED(base) (ENET_RD_MSCR_MII_SPEED(base))
+
+/*! @brief Set the MII_SPEED field to a new value. */
+#define ENET_WR_MSCR_MII_SPEED(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_MII_SPEED_MASK, ENET_MSCR_MII_SPEED(value)))
+#define ENET_BWR_MSCR_MII_SPEED(base, value) (ENET_WR_MSCR_MII_SPEED(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
+ *
+ * Enables/disables prepending a preamble to the MII management frame. The MII
+ * standard allows the preamble to be dropped if the attached PHY devices do not
+ * require it.
+ *
+ * Values:
+ * - 0b0 - Preamble enabled.
+ * - 0b1 - Preamble (32 ones) is not prepended to the MII management frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_DIS_PRE field. */
+#define ENET_RD_MSCR_DIS_PRE(base) ((ENET_MSCR_REG(base) & ENET_MSCR_DIS_PRE_MASK) >> ENET_MSCR_DIS_PRE_SHIFT)
+#define ENET_BRD_MSCR_DIS_PRE(base) (BITBAND_ACCESS32(&ENET_MSCR_REG(base), ENET_MSCR_DIS_PRE_SHIFT))
+
+/*! @brief Set the DIS_PRE field to a new value. */
+#define ENET_WR_MSCR_DIS_PRE(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_DIS_PRE_MASK, ENET_MSCR_DIS_PRE(value)))
+#define ENET_BWR_MSCR_DIS_PRE(base, value) (BITBAND_ACCESS32(&ENET_MSCR_REG(base), ENET_MSCR_DIS_PRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
+ *
+ * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
+ * output. Depending on the host bus frequency, the setting may need to be
+ * increased.
+ *
+ * Values:
+ * - 0b000 - 1 internal module clock cycle
+ * - 0b001 - 2 internal module clock cycles
+ * - 0b010 - 3 internal module clock cycles
+ * - 0b111 - 8 internal module clock cycles
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MSCR_HOLDTIME field. */
+#define ENET_RD_MSCR_HOLDTIME(base) ((ENET_MSCR_REG(base) & ENET_MSCR_HOLDTIME_MASK) >> ENET_MSCR_HOLDTIME_SHIFT)
+#define ENET_BRD_MSCR_HOLDTIME(base) (ENET_RD_MSCR_HOLDTIME(base))
+
+/*! @brief Set the HOLDTIME field to a new value. */
+#define ENET_WR_MSCR_HOLDTIME(base, value) (ENET_RMW_MSCR(base, ENET_MSCR_HOLDTIME_MASK, ENET_MSCR_HOLDTIME(value)))
+#define ENET_BWR_MSCR_HOLDTIME(base, value) (ENET_WR_MSCR_HOLDTIME(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MIBC - MIB Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MIBC - MIB Control Register (RW)
+ *
+ * Reset value: 0xC0000000U
+ *
+ * MIBC is a read/write register controlling and observing the state of the MIB
+ * block. Access this register to disable the MIB block operation or clear the
+ * MIB counters. The MIB_DIS field resets to 1.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MIBC register
+ */
+/*@{*/
+#define ENET_RD_MIBC(base)       (ENET_MIBC_REG(base))
+#define ENET_WR_MIBC(base, value) (ENET_MIBC_REG(base) = (value))
+#define ENET_RMW_MIBC(base, mask, value) (ENET_WR_MIBC(base, (ENET_RD_MIBC(base) & ~(mask)) | (value)))
+#define ENET_SET_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) |  (value)))
+#define ENET_CLR_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) & ~(value)))
+#define ENET_TOG_MIBC(base, value) (ENET_WR_MIBC(base, ENET_RD_MIBC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MIBC bitfields
+ */
+
+/*!
+ * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
+ *
+ * If set, all statistics counters are reset to 0. This field is not
+ * self-clearing. To clear the MIB counters set and then clear the field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_CLEAR field. */
+#define ENET_RD_MIBC_MIB_CLEAR(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_CLEAR_MASK) >> ENET_MIBC_MIB_CLEAR_SHIFT)
+#define ENET_BRD_MIBC_MIB_CLEAR(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_CLEAR_SHIFT))
+
+/*! @brief Set the MIB_CLEAR field to a new value. */
+#define ENET_WR_MIBC_MIB_CLEAR(base, value) (ENET_RMW_MIBC(base, ENET_MIBC_MIB_CLEAR_MASK, ENET_MIBC_MIB_CLEAR(value)))
+#define ENET_BWR_MIBC_MIB_CLEAR(base, value) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_CLEAR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
+ *
+ * If this status field is set, the MIB block is not currently updating any MIB
+ * counters.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_IDLE field. */
+#define ENET_RD_MIBC_MIB_IDLE(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_IDLE_MASK) >> ENET_MIBC_MIB_IDLE_SHIFT)
+#define ENET_BRD_MIBC_MIB_IDLE(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
+ *
+ * If this control field is set, the MIB logic halts and does not update any MIB
+ * counters.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MIBC_MIB_DIS field. */
+#define ENET_RD_MIBC_MIB_DIS(base) ((ENET_MIBC_REG(base) & ENET_MIBC_MIB_DIS_MASK) >> ENET_MIBC_MIB_DIS_SHIFT)
+#define ENET_BRD_MIBC_MIB_DIS(base) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_DIS_SHIFT))
+
+/*! @brief Set the MIB_DIS field to a new value. */
+#define ENET_WR_MIBC_MIB_DIS(base, value) (ENET_RMW_MIBC(base, ENET_MIBC_MIB_DIS_MASK, ENET_MIBC_MIB_DIS(value)))
+#define ENET_BWR_MIBC_MIB_DIS(base, value) (BITBAND_ACCESS32(&ENET_MIBC_REG(base), ENET_MIBC_MIB_DIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RCR - Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RCR - Receive Control Register (RW)
+ *
+ * Reset value: 0x05EE0001U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RCR register
+ */
+/*@{*/
+#define ENET_RD_RCR(base)        (ENET_RCR_REG(base))
+#define ENET_WR_RCR(base, value) (ENET_RCR_REG(base) = (value))
+#define ENET_RMW_RCR(base, mask, value) (ENET_WR_RCR(base, (ENET_RD_RCR(base) & ~(mask)) | (value)))
+#define ENET_SET_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) |  (value)))
+#define ENET_CLR_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) & ~(value)))
+#define ENET_TOG_RCR(base, value) (ENET_WR_RCR(base, ENET_RD_RCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RCR bitfields
+ */
+
+/*!
+ * @name Register ENET_RCR, field LOOP[0] (RW)
+ *
+ * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
+ * RMII_MODE must be written to 0.
+ *
+ * Values:
+ * - 0b0 - Loopback disabled.
+ * - 0b1 - Transmitted frames are looped back internal to the device and
+ *     transmit MII output signals are not asserted. DRT must be cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_LOOP field. */
+#define ENET_RD_RCR_LOOP(base) ((ENET_RCR_REG(base) & ENET_RCR_LOOP_MASK) >> ENET_RCR_LOOP_SHIFT)
+#define ENET_BRD_RCR_LOOP(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_LOOP_SHIFT))
+
+/*! @brief Set the LOOP field to a new value. */
+#define ENET_WR_RCR_LOOP(base, value) (ENET_RMW_RCR(base, ENET_RCR_LOOP_MASK, ENET_RCR_LOOP(value)))
+#define ENET_BWR_RCR_LOOP(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_LOOP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field DRT[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Receive path operates independently of transmit. Used for full-duplex
+ *     or to monitor transmit activity in half-duplex mode.
+ * - 0b1 - Disable reception of frames while transmitting. Normally used for
+ *     half-duplex mode.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_DRT field. */
+#define ENET_RD_RCR_DRT(base) ((ENET_RCR_REG(base) & ENET_RCR_DRT_MASK) >> ENET_RCR_DRT_SHIFT)
+#define ENET_BRD_RCR_DRT(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_DRT_SHIFT))
+
+/*! @brief Set the DRT field to a new value. */
+#define ENET_WR_RCR_DRT(base, value) (ENET_RMW_RCR(base, ENET_RCR_DRT_MASK, ENET_RCR_DRT(value)))
+#define ENET_BWR_RCR_DRT(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_DRT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field MII_MODE[2] (RW)
+ *
+ * This field must always be set.
+ *
+ * Values:
+ * - 0b0 - Reserved.
+ * - 0b1 - MII or RMII mode, as indicated by the RMII_MODE field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_MII_MODE field. */
+#define ENET_RD_RCR_MII_MODE(base) ((ENET_RCR_REG(base) & ENET_RCR_MII_MODE_MASK) >> ENET_RCR_MII_MODE_SHIFT)
+#define ENET_BRD_RCR_MII_MODE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_MII_MODE_SHIFT))
+
+/*! @brief Set the MII_MODE field to a new value. */
+#define ENET_WR_RCR_MII_MODE(base, value) (ENET_RMW_RCR(base, ENET_RCR_MII_MODE_MASK, ENET_RCR_MII_MODE(value)))
+#define ENET_BWR_RCR_MII_MODE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_MII_MODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PROM[3] (RW)
+ *
+ * All frames are accepted regardless of address matching.
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PROM field. */
+#define ENET_RD_RCR_PROM(base) ((ENET_RCR_REG(base) & ENET_RCR_PROM_MASK) >> ENET_RCR_PROM_SHIFT)
+#define ENET_BRD_RCR_PROM(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PROM_SHIFT))
+
+/*! @brief Set the PROM field to a new value. */
+#define ENET_WR_RCR_PROM(base, value) (ENET_RMW_RCR(base, ENET_RCR_PROM_MASK, ENET_RCR_PROM(value)))
+#define ENET_BWR_RCR_PROM(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PROM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field BC_REJ[4] (RW)
+ *
+ * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
+ * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
+ * broadcast DA are accepted and the MISS (M) is set in the receive buffer
+ * descriptor.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_BC_REJ field. */
+#define ENET_RD_RCR_BC_REJ(base) ((ENET_RCR_REG(base) & ENET_RCR_BC_REJ_MASK) >> ENET_RCR_BC_REJ_SHIFT)
+#define ENET_BRD_RCR_BC_REJ(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_BC_REJ_SHIFT))
+
+/*! @brief Set the BC_REJ field to a new value. */
+#define ENET_WR_RCR_BC_REJ(base, value) (ENET_RMW_RCR(base, ENET_RCR_BC_REJ_MASK, ENET_RCR_BC_REJ(value)))
+#define ENET_BWR_RCR_BC_REJ(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_BC_REJ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field FCE[5] (RW)
+ *
+ * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
+ * transmitter stops transmitting data frames for a given duration.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_FCE field. */
+#define ENET_RD_RCR_FCE(base) ((ENET_RCR_REG(base) & ENET_RCR_FCE_MASK) >> ENET_RCR_FCE_SHIFT)
+#define ENET_BRD_RCR_FCE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_FCE_SHIFT))
+
+/*! @brief Set the FCE field to a new value. */
+#define ENET_WR_RCR_FCE(base, value) (ENET_RMW_RCR(base, ENET_RCR_FCE_MASK, ENET_RCR_FCE(value)))
+#define ENET_BWR_RCR_FCE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_FCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field RMII_MODE[8] (RW)
+ *
+ * Specifies whether the MAC is configured for MII mode or RMII operation .
+ *
+ * Values:
+ * - 0b0 - MAC configured for MII mode.
+ * - 0b1 - MAC configured for RMII operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_RMII_MODE field. */
+#define ENET_RD_RCR_RMII_MODE(base) ((ENET_RCR_REG(base) & ENET_RCR_RMII_MODE_MASK) >> ENET_RCR_RMII_MODE_SHIFT)
+#define ENET_BRD_RCR_RMII_MODE(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_MODE_SHIFT))
+
+/*! @brief Set the RMII_MODE field to a new value. */
+#define ENET_WR_RCR_RMII_MODE(base, value) (ENET_RMW_RCR(base, ENET_RCR_RMII_MODE_MASK, ENET_RCR_RMII_MODE(value)))
+#define ENET_BWR_RCR_RMII_MODE(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_MODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field RMII_10T[9] (RW)
+ *
+ * Enables 10-Mbps mode of the RMII .
+ *
+ * Values:
+ * - 0b0 - 100 Mbps operation.
+ * - 0b1 - 10 Mbps operation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_RMII_10T field. */
+#define ENET_RD_RCR_RMII_10T(base) ((ENET_RCR_REG(base) & ENET_RCR_RMII_10T_MASK) >> ENET_RCR_RMII_10T_SHIFT)
+#define ENET_BRD_RCR_RMII_10T(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_10T_SHIFT))
+
+/*! @brief Set the RMII_10T field to a new value. */
+#define ENET_WR_RCR_RMII_10T(base, value) (ENET_RMW_RCR(base, ENET_RCR_RMII_10T_MASK, ENET_RCR_RMII_10T(value)))
+#define ENET_BWR_RCR_RMII_10T(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_RMII_10T_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PADEN[12] (RW)
+ *
+ * Specifies whether the MAC removes padding from received frames.
+ *
+ * Values:
+ * - 0b0 - No padding is removed on receive by the MAC.
+ * - 0b1 - Padding is removed from received frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PADEN field. */
+#define ENET_RD_RCR_PADEN(base) ((ENET_RCR_REG(base) & ENET_RCR_PADEN_MASK) >> ENET_RCR_PADEN_SHIFT)
+#define ENET_BRD_RCR_PADEN(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PADEN_SHIFT))
+
+/*! @brief Set the PADEN field to a new value. */
+#define ENET_WR_RCR_PADEN(base, value) (ENET_RMW_RCR(base, ENET_RCR_PADEN_MASK, ENET_RCR_PADEN(value)))
+#define ENET_BWR_RCR_PADEN(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PADEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field PAUFWD[13] (RW)
+ *
+ * Specifies whether pause frames are terminated or forwarded.
+ *
+ * Values:
+ * - 0b0 - Pause frames are terminated and discarded in the MAC.
+ * - 0b1 - Pause frames are forwarded to the user application.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_PAUFWD field. */
+#define ENET_RD_RCR_PAUFWD(base) ((ENET_RCR_REG(base) & ENET_RCR_PAUFWD_MASK) >> ENET_RCR_PAUFWD_SHIFT)
+#define ENET_BRD_RCR_PAUFWD(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PAUFWD_SHIFT))
+
+/*! @brief Set the PAUFWD field to a new value. */
+#define ENET_WR_RCR_PAUFWD(base, value) (ENET_RMW_RCR(base, ENET_RCR_PAUFWD_MASK, ENET_RCR_PAUFWD(value)))
+#define ENET_BWR_RCR_PAUFWD(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_PAUFWD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field CRCFWD[14] (RW)
+ *
+ * Specifies whether the CRC field of received frames is transmitted or
+ * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
+ * field is checked and always terminated and removed.
+ *
+ * Values:
+ * - 0b0 - The CRC field of received frames is transmitted to the user
+ *     application.
+ * - 0b1 - The CRC field is stripped from the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_CRCFWD field. */
+#define ENET_RD_RCR_CRCFWD(base) ((ENET_RCR_REG(base) & ENET_RCR_CRCFWD_MASK) >> ENET_RCR_CRCFWD_SHIFT)
+#define ENET_BRD_RCR_CRCFWD(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CRCFWD_SHIFT))
+
+/*! @brief Set the CRCFWD field to a new value. */
+#define ENET_WR_RCR_CRCFWD(base, value) (ENET_RMW_RCR(base, ENET_RCR_CRCFWD_MASK, ENET_RCR_CRCFWD(value)))
+#define ENET_BWR_RCR_CRCFWD(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CRCFWD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field CFEN[15] (RW)
+ *
+ * Enables/disables the MAC control frame.
+ *
+ * Values:
+ * - 0b0 - MAC control frames with any opcode other than 0x0001 (pause frame)
+ *     are accepted and forwarded to the client interface.
+ * - 0b1 - MAC control frames with any opcode other than 0x0001 (pause frame)
+ *     are silently discarded.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_CFEN field. */
+#define ENET_RD_RCR_CFEN(base) ((ENET_RCR_REG(base) & ENET_RCR_CFEN_MASK) >> ENET_RCR_CFEN_SHIFT)
+#define ENET_BRD_RCR_CFEN(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CFEN_SHIFT))
+
+/*! @brief Set the CFEN field to a new value. */
+#define ENET_WR_RCR_CFEN(base, value) (ENET_RMW_RCR(base, ENET_RCR_CFEN_MASK, ENET_RCR_CFEN(value)))
+#define ENET_BWR_RCR_CFEN(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_CFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
+ *
+ * Resets to decimal 1518. Length is measured starting at DA and includes the
+ * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
+ * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
+ * to occur and set the LG field in the end of frame receive buffer descriptor.
+ * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
+ * supported.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_MAX_FL field. */
+#define ENET_RD_RCR_MAX_FL(base) ((ENET_RCR_REG(base) & ENET_RCR_MAX_FL_MASK) >> ENET_RCR_MAX_FL_SHIFT)
+#define ENET_BRD_RCR_MAX_FL(base) (ENET_RD_RCR_MAX_FL(base))
+
+/*! @brief Set the MAX_FL field to a new value. */
+#define ENET_WR_RCR_MAX_FL(base, value) (ENET_RMW_RCR(base, ENET_RCR_MAX_FL_MASK, ENET_RCR_MAX_FL(value)))
+#define ENET_BWR_RCR_MAX_FL(base, value) (ENET_WR_RCR_MAX_FL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field NLC[30] (RW)
+ *
+ * Enables/disables a payload length check.
+ *
+ * Values:
+ * - 0b0 - The payload length check is disabled.
+ * - 0b1 - The core checks the frame's payload length with the frame length/type
+ *     field. Errors are indicated in the EIR[PLC] field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_NLC field. */
+#define ENET_RD_RCR_NLC(base) ((ENET_RCR_REG(base) & ENET_RCR_NLC_MASK) >> ENET_RCR_NLC_SHIFT)
+#define ENET_BRD_RCR_NLC(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_NLC_SHIFT))
+
+/*! @brief Set the NLC field to a new value. */
+#define ENET_WR_RCR_NLC(base, value) (ENET_RMW_RCR(base, ENET_RCR_NLC_MASK, ENET_RCR_NLC(value)))
+#define ENET_BWR_RCR_NLC(base, value) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_NLC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RCR, field GRS[31] (RO)
+ *
+ * Read-only status indicating that the MAC receive datapath is stopped.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RCR_GRS field. */
+#define ENET_RD_RCR_GRS(base) ((ENET_RCR_REG(base) & ENET_RCR_GRS_MASK) >> ENET_RCR_GRS_SHIFT)
+#define ENET_BRD_RCR_GRS(base) (BITBAND_ACCESS32(&ENET_RCR_REG(base), ENET_RCR_GRS_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCR - Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCR - Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR is read/write and configures the transmit block. This register is cleared
+ * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCR register
+ */
+/*@{*/
+#define ENET_RD_TCR(base)        (ENET_TCR_REG(base))
+#define ENET_WR_TCR(base, value) (ENET_TCR_REG(base) = (value))
+#define ENET_RMW_TCR(base, mask, value) (ENET_WR_TCR(base, (ENET_RD_TCR(base) & ~(mask)) | (value)))
+#define ENET_SET_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) |  (value)))
+#define ENET_CLR_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) & ~(value)))
+#define ENET_TOG_TCR(base, value) (ENET_WR_TCR(base, ENET_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TCR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCR, field GTS[0] (RW)
+ *
+ * When this field is set, MAC stops transmission after any frame currently
+ * transmitted is complete and EIR[GRA] is set. If frame transmission is not
+ * currently underway, the GRA interrupt is asserted immediately. After transmission
+ * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
+ * transmitted. If an early collision occurs during transmission when GTS is set,
+ * transmission stops after the collision. The frame is transmitted again after GTS is
+ * cleared. There may be old frames in the transmit FIFO that transmit when GTS
+ * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_GTS field. */
+#define ENET_RD_TCR_GTS(base) ((ENET_TCR_REG(base) & ENET_TCR_GTS_MASK) >> ENET_TCR_GTS_SHIFT)
+#define ENET_BRD_TCR_GTS(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_GTS_SHIFT))
+
+/*! @brief Set the GTS field to a new value. */
+#define ENET_WR_TCR_GTS(base, value) (ENET_RMW_TCR(base, ENET_TCR_GTS_MASK, ENET_TCR_GTS(value)))
+#define ENET_BWR_TCR_GTS(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_GTS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field FDEN[2] (RW)
+ *
+ * If this field is set, frames transmit independent of carrier sense and
+ * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_FDEN field. */
+#define ENET_RD_TCR_FDEN(base) ((ENET_TCR_REG(base) & ENET_TCR_FDEN_MASK) >> ENET_TCR_FDEN_SHIFT)
+#define ENET_BRD_TCR_FDEN(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_FDEN_SHIFT))
+
+/*! @brief Set the FDEN field to a new value. */
+#define ENET_WR_TCR_FDEN(base, value) (ENET_RMW_TCR(base, ENET_TCR_FDEN_MASK, ENET_TCR_FDEN(value)))
+#define ENET_BWR_TCR_FDEN(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_FDEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
+ *
+ * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
+ * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
+ * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
+ * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
+ * the MAC may continue transmitting a MAC control PAUSE frame.
+ *
+ * Values:
+ * - 0b0 - No PAUSE frame transmitted.
+ * - 0b1 - The MAC stops transmission of data frames after the current
+ *     transmission is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_TFC_PAUSE field. */
+#define ENET_RD_TCR_TFC_PAUSE(base) ((ENET_TCR_REG(base) & ENET_TCR_TFC_PAUSE_MASK) >> ENET_TCR_TFC_PAUSE_SHIFT)
+#define ENET_BRD_TCR_TFC_PAUSE(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_TFC_PAUSE_SHIFT))
+
+/*! @brief Set the TFC_PAUSE field to a new value. */
+#define ENET_WR_TCR_TFC_PAUSE(base, value) (ENET_RMW_TCR(base, ENET_TCR_TFC_PAUSE_MASK, ENET_TCR_TFC_PAUSE(value)))
+#define ENET_BWR_TCR_TFC_PAUSE(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_TFC_PAUSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
+ *
+ * This status field is set when a full-duplex flow control pause frame is
+ * received and the transmitter pauses for the duration defined in this pause frame.
+ * This field automatically clears when the pause duration is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_RFC_PAUSE field. */
+#define ENET_RD_TCR_RFC_PAUSE(base) ((ENET_TCR_REG(base) & ENET_TCR_RFC_PAUSE_MASK) >> ENET_TCR_RFC_PAUSE_SHIFT)
+#define ENET_BRD_TCR_RFC_PAUSE(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_RFC_PAUSE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
+ *
+ * If ADDINS is set, indicates the MAC address that overwrites the source MAC
+ * address.
+ *
+ * Values:
+ * - 0b000 - Node MAC address programmed on PADDR1/2 registers.
+ * - 0b100 - Reserved.
+ * - 0b101 - Reserved.
+ * - 0b110 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_ADDSEL field. */
+#define ENET_RD_TCR_ADDSEL(base) ((ENET_TCR_REG(base) & ENET_TCR_ADDSEL_MASK) >> ENET_TCR_ADDSEL_SHIFT)
+#define ENET_BRD_TCR_ADDSEL(base) (ENET_RD_TCR_ADDSEL(base))
+
+/*! @brief Set the ADDSEL field to a new value. */
+#define ENET_WR_TCR_ADDSEL(base, value) (ENET_RMW_TCR(base, ENET_TCR_ADDSEL_MASK, ENET_TCR_ADDSEL(value)))
+#define ENET_BWR_TCR_ADDSEL(base, value) (ENET_WR_TCR_ADDSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field ADDINS[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The source MAC address is not modified by the MAC.
+ * - 0b1 - The MAC overwrites the source MAC address with the programmed MAC
+ *     address according to ADDSEL.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_ADDINS field. */
+#define ENET_RD_TCR_ADDINS(base) ((ENET_TCR_REG(base) & ENET_TCR_ADDINS_MASK) >> ENET_TCR_ADDINS_SHIFT)
+#define ENET_BRD_TCR_ADDINS(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_ADDINS_SHIFT))
+
+/*! @brief Set the ADDINS field to a new value. */
+#define ENET_WR_TCR_ADDINS(base, value) (ENET_RMW_TCR(base, ENET_TCR_ADDINS_MASK, ENET_TCR_ADDINS(value)))
+#define ENET_BWR_TCR_ADDINS(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_ADDINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCR, field CRCFWD[9] (RW)
+ *
+ * Values:
+ * - 0b0 - TxBD[TC] controls whether the frame has a CRC from the application.
+ * - 0b1 - The transmitter does not append any CRC to transmitted frames, as it
+ *     is expecting a frame with CRC from the application.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCR_CRCFWD field. */
+#define ENET_RD_TCR_CRCFWD(base) ((ENET_TCR_REG(base) & ENET_TCR_CRCFWD_MASK) >> ENET_TCR_CRCFWD_SHIFT)
+#define ENET_BRD_TCR_CRCFWD(base) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_CRCFWD_SHIFT))
+
+/*! @brief Set the CRCFWD field to a new value. */
+#define ENET_WR_TCR_CRCFWD(base, value) (ENET_RMW_TCR(base, ENET_TCR_CRCFWD_MASK, ENET_TCR_CRCFWD(value)))
+#define ENET_BWR_TCR_CRCFWD(base, value) (BITBAND_ACCESS32(&ENET_TCR_REG(base), ENET_TCR_CRCFWD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_PALR - Physical Address Lower Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_PALR - Physical Address Lower Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
+ * in the address recognition process to compare with the destination address
+ * (DA) field of receive frames with an individual DA. In addition, this register
+ * is used in bytes 0 through 3 of the six-byte source address field when
+ * transmitting PAUSE frames. This register is not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_PALR register
+ */
+/*@{*/
+#define ENET_RD_PALR(base)       (ENET_PALR_REG(base))
+#define ENET_WR_PALR(base, value) (ENET_PALR_REG(base) = (value))
+#define ENET_RMW_PALR(base, mask, value) (ENET_WR_PALR(base, (ENET_RD_PALR(base) & ~(mask)) | (value)))
+#define ENET_SET_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) |  (value)))
+#define ENET_CLR_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) & ~(value)))
+#define ENET_TOG_PALR(base, value) (ENET_WR_PALR(base, ENET_RD_PALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_PAUR - Physical Address Upper Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_PAUR - Physical Address Upper Register (RW)
+ *
+ * Reset value: 0x00008808U
+ *
+ * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
+ * the address recognition process to compare with the destination address (DA)
+ * field of receive frames with an individual DA. In addition, this register is
+ * used in bytes 4 and 5 of the six-byte source address field when transmitting
+ * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
+ * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
+ * you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_PAUR register
+ */
+/*@{*/
+#define ENET_RD_PAUR(base)       (ENET_PAUR_REG(base))
+#define ENET_WR_PAUR(base, value) (ENET_PAUR_REG(base) = (value))
+#define ENET_RMW_PAUR(base, mask, value) (ENET_WR_PAUR(base, (ENET_RD_PAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) |  (value)))
+#define ENET_CLR_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) & ~(value)))
+#define ENET_TOG_PAUR(base, value) (ENET_WR_PAUR(base, ENET_RD_PAUR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_PAUR bitfields
+ */
+
+/*!
+ * @name Register ENET_PAUR, field TYPE[15:0] (RO)
+ *
+ * These fields have a constant value of 0x8808.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_PAUR_TYPE field. */
+#define ENET_RD_PAUR_TYPE(base) ((ENET_PAUR_REG(base) & ENET_PAUR_TYPE_MASK) >> ENET_PAUR_TYPE_SHIFT)
+#define ENET_BRD_PAUR_TYPE(base) (ENET_RD_PAUR_TYPE(base))
+/*@}*/
+
+/*!
+ * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
+ *
+ * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
+ * for exact match, and the source address field in PAUSE frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_PAUR_PADDR2 field. */
+#define ENET_RD_PAUR_PADDR2(base) ((ENET_PAUR_REG(base) & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT)
+#define ENET_BRD_PAUR_PADDR2(base) (ENET_RD_PAUR_PADDR2(base))
+
+/*! @brief Set the PADDR2 field to a new value. */
+#define ENET_WR_PAUR_PADDR2(base, value) (ENET_RMW_PAUR(base, ENET_PAUR_PADDR2_MASK, ENET_PAUR_PADDR2(value)))
+#define ENET_BWR_PAUR_PADDR2(base, value) (ENET_WR_PAUR_PADDR2(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_OPD - Opcode/Pause Duration Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_OPD - Opcode/Pause Duration Register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * OPD is read/write accessible. This register contains the 16-bit opcode and
+ * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
+ * field is a constant value, 0x0001. When another node detects a PAUSE frame,
+ * that node pauses transmission for the duration specified in the pause duration
+ * field. The lower 16 bits of this register are not reset and you must initialize
+ * it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_OPD register
+ */
+/*@{*/
+#define ENET_RD_OPD(base)        (ENET_OPD_REG(base))
+#define ENET_WR_OPD(base, value) (ENET_OPD_REG(base) = (value))
+#define ENET_RMW_OPD(base, mask, value) (ENET_WR_OPD(base, (ENET_RD_OPD(base) & ~(mask)) | (value)))
+#define ENET_SET_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) |  (value)))
+#define ENET_CLR_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) & ~(value)))
+#define ENET_TOG_OPD(base, value) (ENET_WR_OPD(base, ENET_RD_OPD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_OPD bitfields
+ */
+
+/*!
+ * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
+ *
+ * Pause duration field used in PAUSE frames.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_OPD_PAUSE_DUR field. */
+#define ENET_RD_OPD_PAUSE_DUR(base) ((ENET_OPD_REG(base) & ENET_OPD_PAUSE_DUR_MASK) >> ENET_OPD_PAUSE_DUR_SHIFT)
+#define ENET_BRD_OPD_PAUSE_DUR(base) (ENET_RD_OPD_PAUSE_DUR(base))
+
+/*! @brief Set the PAUSE_DUR field to a new value. */
+#define ENET_WR_OPD_PAUSE_DUR(base, value) (ENET_RMW_OPD(base, ENET_OPD_PAUSE_DUR_MASK, ENET_OPD_PAUSE_DUR(value)))
+#define ENET_BWR_OPD_PAUSE_DUR(base, value) (ENET_WR_OPD_PAUSE_DUR(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_OPD, field OPCODE[31:16] (RO)
+ *
+ * These fields have a constant value of 0x0001.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_OPD_OPCODE field. */
+#define ENET_RD_OPD_OPCODE(base) ((ENET_OPD_REG(base) & ENET_OPD_OPCODE_MASK) >> ENET_OPD_OPCODE_SHIFT)
+#define ENET_BRD_OPD_OPCODE(base) (ENET_RD_OPD_OPCODE(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IAUR - Descriptor Individual Upper Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IAUR - Descriptor Individual Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the destination address (DA) field of receive frames with an individual
+ * DA. This register is not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IAUR register
+ */
+/*@{*/
+#define ENET_RD_IAUR(base)       (ENET_IAUR_REG(base))
+#define ENET_WR_IAUR(base, value) (ENET_IAUR_REG(base) = (value))
+#define ENET_RMW_IAUR(base, mask, value) (ENET_WR_IAUR(base, (ENET_RD_IAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) |  (value)))
+#define ENET_CLR_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) & ~(value)))
+#define ENET_TOG_IAUR(base, value) (ENET_WR_IAUR(base, ENET_RD_IAUR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IALR - Descriptor Individual Lower Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IALR - Descriptor Individual Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * IALR contains the lower 32 bits of the 64-bit individual address hash table.
+ * The address recognition process uses this table to check for a possible match
+ * with the DA field of receive frames with an individual DA. This register is
+ * not reset and you must initialize it.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IALR register
+ */
+/*@{*/
+#define ENET_RD_IALR(base)       (ENET_IALR_REG(base))
+#define ENET_WR_IALR(base, value) (ENET_IALR_REG(base) = (value))
+#define ENET_RMW_IALR(base, mask, value) (ENET_WR_IALR(base, (ENET_RD_IALR(base) & ~(mask)) | (value)))
+#define ENET_SET_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) |  (value)))
+#define ENET_CLR_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) & ~(value)))
+#define ENET_TOG_IALR(base, value) (ENET_WR_IALR(base, ENET_RD_IALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_GAUR - Descriptor Group Upper Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_GAUR - Descriptor Group Upper Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+/*!
+ * @name Constants and macros for entire ENET_GAUR register
+ */
+/*@{*/
+#define ENET_RD_GAUR(base)       (ENET_GAUR_REG(base))
+#define ENET_WR_GAUR(base, value) (ENET_GAUR_REG(base) = (value))
+#define ENET_RMW_GAUR(base, mask, value) (ENET_WR_GAUR(base, (ENET_RD_GAUR(base) & ~(mask)) | (value)))
+#define ENET_SET_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) |  (value)))
+#define ENET_CLR_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) & ~(value)))
+#define ENET_TOG_GAUR(base, value) (ENET_WR_GAUR(base, ENET_RD_GAUR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_GALR - Descriptor Group Lower Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_GALR - Descriptor Group Lower Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * GALR contains the lower 32 bits of the 64-bit hash table used in the address
+ * recognition process for receive frames with a multicast address. You must
+ * initialize this register.
+ */
+/*!
+ * @name Constants and macros for entire ENET_GALR register
+ */
+/*@{*/
+#define ENET_RD_GALR(base)       (ENET_GALR_REG(base))
+#define ENET_WR_GALR(base, value) (ENET_GALR_REG(base) = (value))
+#define ENET_RMW_GALR(base, mask, value) (ENET_WR_GALR(base, (ENET_RD_GALR(base) & ~(mask)) | (value)))
+#define ENET_SET_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) |  (value)))
+#define ENET_CLR_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) & ~(value)))
+#define ENET_TOG_GALR(base, value) (ENET_WR_GALR(base, ENET_RD_GALR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TFWR - Transmit FIFO Watermark Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TFWR - Transmit FIFO Watermark Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
+ * in the transmit FIFO before transmission of a frame can begin. This allows you
+ * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
+ * latency (TFWR = 11) due to contention for the system bus. Setting the
+ * watermark to a high value minimizes the risk of transmit FIFO underrun due to
+ * contention for the system bus. The byte counts associated with the TFWR field may need
+ * to be modified to match a given system requirement. For example, worst case
+ * bus access latency by the transmit data DMA channel. When the FIFO level
+ * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
+ * transmit control logic starts frame transmission even before the end-of-frame is
+ * available in the FIFO (cut-through operation). If a complete frame has a size
+ * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
+ * to the line. To enable store and forward on the Transmit path, set STR_FWD to
+ * '1'. In this case, the MAC starts to transmit data only when a complete frame
+ * is stored in the Transmit FIFO.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TFWR register
+ */
+/*@{*/
+#define ENET_RD_TFWR(base)       (ENET_TFWR_REG(base))
+#define ENET_WR_TFWR(base, value) (ENET_TFWR_REG(base) = (value))
+#define ENET_RMW_TFWR(base, mask, value) (ENET_WR_TFWR(base, (ENET_RD_TFWR(base) & ~(mask)) | (value)))
+#define ENET_SET_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) |  (value)))
+#define ENET_CLR_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) & ~(value)))
+#define ENET_TOG_TFWR(base, value) (ENET_WR_TFWR(base, ENET_RD_TFWR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TFWR bitfields
+ */
+
+/*!
+ * @name Register ENET_TFWR, field TFWR[5:0] (RW)
+ *
+ * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
+ * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
+ * begins. If a frame with less than the threshold is written, it is still sent
+ * independently of this threshold setting. The threshold is relevant only if the
+ * frame is larger than the threshold given. This chip may not support the maximum
+ * number of bytes written shown below. See the chip-specific information for the
+ * ENET module for this value.
+ *
+ * Values:
+ * - 0b000000 - 64 bytes written.
+ * - 0b000001 - 64 bytes written.
+ * - 0b000010 - 128 bytes written.
+ * - 0b000011 - 192 bytes written.
+ * - 0b111110 - 3968 bytes written.
+ * - 0b111111 - 4032 bytes written.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TFWR_TFWR field. */
+#define ENET_RD_TFWR_TFWR(base) ((ENET_TFWR_REG(base) & ENET_TFWR_TFWR_MASK) >> ENET_TFWR_TFWR_SHIFT)
+#define ENET_BRD_TFWR_TFWR(base) (ENET_RD_TFWR_TFWR(base))
+
+/*! @brief Set the TFWR field to a new value. */
+#define ENET_WR_TFWR_TFWR(base, value) (ENET_RMW_TFWR(base, ENET_TFWR_TFWR_MASK, ENET_TFWR_TFWR(value)))
+#define ENET_BWR_TFWR_TFWR(base, value) (ENET_WR_TFWR_TFWR(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TFWR, field STRFWD[8] (RW)
+ *
+ * Values:
+ * - 0b0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
+ * - 0b1 - Enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TFWR_STRFWD field. */
+#define ENET_RD_TFWR_STRFWD(base) ((ENET_TFWR_REG(base) & ENET_TFWR_STRFWD_MASK) >> ENET_TFWR_STRFWD_SHIFT)
+#define ENET_BRD_TFWR_STRFWD(base) (BITBAND_ACCESS32(&ENET_TFWR_REG(base), ENET_TFWR_STRFWD_SHIFT))
+
+/*! @brief Set the STRFWD field to a new value. */
+#define ENET_WR_TFWR_STRFWD(base, value) (ENET_RMW_TFWR(base, ENET_TFWR_STRFWD_MASK, ENET_TFWR_STRFWD(value)))
+#define ENET_BWR_TFWR_STRFWD(base, value) (BITBAND_ACCESS32(&ENET_TFWR_REG(base), ENET_TFWR_STRFWD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RDSR - Receive Descriptor Ring Start Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RDSR - Receive Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RDSR points to the beginning of the circular receive buffer descriptor queue
+ * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
+ * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
+ * by 16. This register must be initialized prior to operation
+ */
+/*!
+ * @name Constants and macros for entire ENET_RDSR register
+ */
+/*@{*/
+#define ENET_RD_RDSR(base)       (ENET_RDSR_REG(base))
+#define ENET_WR_RDSR(base, value) (ENET_RDSR_REG(base) = (value))
+#define ENET_RMW_RDSR(base, mask, value) (ENET_WR_RDSR(base, (ENET_RD_RDSR(base) & ~(mask)) | (value)))
+#define ENET_SET_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) |  (value)))
+#define ENET_CLR_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) & ~(value)))
+#define ENET_TOG_RDSR(base, value) (ENET_WR_RDSR(base, ENET_RD_RDSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the receive buffer descriptor queue.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RDSR_R_DES_START field. */
+#define ENET_RD_RDSR_R_DES_START(base) ((ENET_RDSR_REG(base) & ENET_RDSR_R_DES_START_MASK) >> ENET_RDSR_R_DES_START_SHIFT)
+#define ENET_BRD_RDSR_R_DES_START(base) (ENET_RD_RDSR_R_DES_START(base))
+
+/*! @brief Set the R_DES_START field to a new value. */
+#define ENET_WR_RDSR_R_DES_START(base, value) (ENET_RMW_RDSR(base, ENET_RDSR_R_DES_START_MASK, ENET_RDSR_R_DES_START(value)))
+#define ENET_BWR_RDSR_R_DES_START(base, value) (ENET_WR_RDSR_R_DES_START(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TDSR provides a pointer to the beginning of the circular transmit buffer
+ * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
+ * must be zero); however, it is recommended to be 128-bit aligned, that is,
+ * evenly divisible by 16. This register must be initialized prior to operation.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TDSR register
+ */
+/*@{*/
+#define ENET_RD_TDSR(base)       (ENET_TDSR_REG(base))
+#define ENET_WR_TDSR(base, value) (ENET_TDSR_REG(base) = (value))
+#define ENET_RMW_TDSR(base, mask, value) (ENET_WR_TDSR(base, (ENET_RD_TDSR(base) & ~(mask)) | (value)))
+#define ENET_SET_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) |  (value)))
+#define ENET_CLR_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) & ~(value)))
+#define ENET_TOG_TDSR(base, value) (ENET_WR_TDSR(base, ENET_RD_TDSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TDSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
+ *
+ * Pointer to the beginning of the transmit buffer descriptor queue.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TDSR_X_DES_START field. */
+#define ENET_RD_TDSR_X_DES_START(base) ((ENET_TDSR_REG(base) & ENET_TDSR_X_DES_START_MASK) >> ENET_TDSR_X_DES_START_SHIFT)
+#define ENET_BRD_TDSR_X_DES_START(base) (ENET_RD_TDSR_X_DES_START(base))
+
+/*! @brief Set the X_DES_START field to a new value. */
+#define ENET_WR_TDSR_X_DES_START(base, value) (ENET_RMW_TDSR(base, ENET_TDSR_X_DES_START_MASK, ENET_TDSR_X_DES_START(value)))
+#define ENET_BWR_TDSR_X_DES_START(base, value) (ENET_WR_TDSR_X_DES_START(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_MRBR - Maximum Receive Buffer Size Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_MRBR - Maximum Receive Buffer Size Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MRBR is a user-programmable register that dictates the maximum size of
+ * all receive buffers. This value should take into consideration that the receive
+ * CRC is always written into the last receive buffer. To allow one maximum size
+ * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
+ * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
+ * set to zero by the device. To minimize bus usage (descriptor fetches), set
+ * MRBR greater than or equal to 256 bytes. This register must be initialized
+ * before operation.
+ */
+/*!
+ * @name Constants and macros for entire ENET_MRBR register
+ */
+/*@{*/
+#define ENET_RD_MRBR(base)       (ENET_MRBR_REG(base))
+#define ENET_WR_MRBR(base, value) (ENET_MRBR_REG(base) = (value))
+#define ENET_RMW_MRBR(base, mask, value) (ENET_WR_MRBR(base, (ENET_RD_MRBR(base) & ~(mask)) | (value)))
+#define ENET_SET_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) |  (value)))
+#define ENET_CLR_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) & ~(value)))
+#define ENET_TOG_MRBR(base, value) (ENET_WR_MRBR(base, ENET_RD_MRBR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_MRBR bitfields
+ */
+
+/*!
+ * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
+ *
+ * Receive buffer size in bytes.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field. */
+#define ENET_RD_MRBR_R_BUF_SIZE(base) ((ENET_MRBR_REG(base) & ENET_MRBR_R_BUF_SIZE_MASK) >> ENET_MRBR_R_BUF_SIZE_SHIFT)
+#define ENET_BRD_MRBR_R_BUF_SIZE(base) (ENET_RD_MRBR_R_BUF_SIZE(base))
+
+/*! @brief Set the R_BUF_SIZE field to a new value. */
+#define ENET_WR_MRBR_R_BUF_SIZE(base, value) (ENET_RMW_MRBR(base, ENET_MRBR_R_BUF_SIZE_MASK, ENET_MRBR_R_BUF_SIZE(value)))
+#define ENET_BWR_MRBR_R_BUF_SIZE(base, value) (ENET_WR_MRBR_R_BUF_SIZE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RSFL - Receive FIFO Section Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RSFL - Receive FIFO Section Full Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RSFL register
+ */
+/*@{*/
+#define ENET_RD_RSFL(base)       (ENET_RSFL_REG(base))
+#define ENET_WR_RSFL(base, value) (ENET_RSFL_REG(base) = (value))
+#define ENET_RMW_RSFL(base, mask, value) (ENET_WR_RSFL(base, (ENET_RD_RSFL(base) & ~(mask)) | (value)))
+#define ENET_SET_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) |  (value)))
+#define ENET_CLR_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) & ~(value)))
+#define ENET_TOG_RSFL(base, value) (ENET_WR_RSFL(base, ENET_RD_RSFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RSFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
+ * this field to enable store and forward on the RX FIFO. When programming a value
+ * greater than 0 (cut-through operation), it must be greater than
+ * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
+ * in the Receive FIFO (cut-through operation).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field. */
+#define ENET_RD_RSFL_RX_SECTION_FULL(base) ((ENET_RSFL_REG(base) & ENET_RSFL_RX_SECTION_FULL_MASK) >> ENET_RSFL_RX_SECTION_FULL_SHIFT)
+#define ENET_BRD_RSFL_RX_SECTION_FULL(base) (ENET_RD_RSFL_RX_SECTION_FULL(base))
+
+/*! @brief Set the RX_SECTION_FULL field to a new value. */
+#define ENET_WR_RSFL_RX_SECTION_FULL(base, value) (ENET_RMW_RSFL(base, ENET_RSFL_RX_SECTION_FULL_MASK, ENET_RSFL_RX_SECTION_FULL(value)))
+#define ENET_BWR_RSFL_RX_SECTION_FULL(base, value) (ENET_WR_RSFL_RX_SECTION_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RSEM - Receive FIFO Section Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RSEM register
+ */
+/*@{*/
+#define ENET_RD_RSEM(base)       (ENET_RSEM_REG(base))
+#define ENET_WR_RSEM(base, value) (ENET_RSEM_REG(base) = (value))
+#define ENET_RMW_RSEM(base, mask, value) (ENET_WR_RSEM(base, (ENET_RD_RSEM(base) & ~(mask)) | (value)))
+#define ENET_SET_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) |  (value)))
+#define ENET_CLR_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) & ~(value)))
+#define ENET_TOG_RSEM(base, value) (ENET_WR_RSEM(base, ENET_RD_RSEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
+ * FIFO has reached this level, a pause frame will be issued. A value of 0
+ * disables automatic pause frame generation. When the FIFO level goes below the value
+ * programmed in this field, an XON pause frame is issued to indicate the FIFO
+ * congestion is cleared to the remote Ethernet client. The section-empty
+ * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field. */
+#define ENET_RD_RSEM_RX_SECTION_EMPTY(base) ((ENET_RSEM_REG(base) & ENET_RSEM_RX_SECTION_EMPTY_MASK) >> ENET_RSEM_RX_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_RSEM_RX_SECTION_EMPTY(base) (ENET_RD_RSEM_RX_SECTION_EMPTY(base))
+
+/*! @brief Set the RX_SECTION_EMPTY field to a new value. */
+#define ENET_WR_RSEM_RX_SECTION_EMPTY(base, value) (ENET_RMW_RSEM(base, ENET_RSEM_RX_SECTION_EMPTY_MASK, ENET_RSEM_RX_SECTION_EMPTY(value)))
+#define ENET_BWR_RSEM_RX_SECTION_EMPTY(base, value) (ENET_WR_RSEM_RX_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
+ *
+ * Defines number of frames in the receive FIFO, independent of its size, that
+ * can be accepted. If the limit is reached, reception will continue normally,
+ * however a pause frame will be triggered to indicate a possible congestion to the
+ * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
+ * frame generation
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field. */
+#define ENET_RD_RSEM_STAT_SECTION_EMPTY(base) ((ENET_RSEM_REG(base) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) >> ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_RSEM_STAT_SECTION_EMPTY(base) (ENET_RD_RSEM_STAT_SECTION_EMPTY(base))
+
+/*! @brief Set the STAT_SECTION_EMPTY field to a new value. */
+#define ENET_WR_RSEM_STAT_SECTION_EMPTY(base, value) (ENET_RMW_RSEM(base, ENET_RSEM_STAT_SECTION_EMPTY_MASK, ENET_RSEM_STAT_SECTION_EMPTY(value)))
+#define ENET_BWR_RSEM_STAT_SECTION_EMPTY(base, value) (ENET_WR_RSEM_STAT_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RAEM - Receive FIFO Almost Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RAEM register
+ */
+/*@{*/
+#define ENET_RD_RAEM(base)       (ENET_RAEM_REG(base))
+#define ENET_WR_RAEM(base, value) (ENET_RAEM_REG(base) = (value))
+#define ENET_RMW_RAEM(base, mask, value) (ENET_WR_RAEM(base, (ENET_RD_RAEM(base) & ~(mask)) | (value)))
+#define ENET_SET_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) |  (value)))
+#define ENET_CLR_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) & ~(value)))
+#define ENET_TOG_RAEM(base, value) (ENET_WR_RAEM(base, ENET_RD_RAEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field and the end-of-frame has
+ * not been received for the frame yet, the core receive read control stops FIFO
+ * read (and subsequently stops transferring data to the MAC client
+ * application). It continues to deliver the frame, if again more data than the threshold or
+ * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field. */
+#define ENET_RD_RAEM_RX_ALMOST_EMPTY(base) ((ENET_RAEM_REG(base) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) >> ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)
+#define ENET_BRD_RAEM_RX_ALMOST_EMPTY(base) (ENET_RD_RAEM_RX_ALMOST_EMPTY(base))
+
+/*! @brief Set the RX_ALMOST_EMPTY field to a new value. */
+#define ENET_WR_RAEM_RX_ALMOST_EMPTY(base, value) (ENET_RMW_RAEM(base, ENET_RAEM_RX_ALMOST_EMPTY_MASK, ENET_RAEM_RX_ALMOST_EMPTY(value)))
+#define ENET_BWR_RAEM_RX_ALMOST_EMPTY(base, value) (ENET_WR_RAEM_RX_ALMOST_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RAFL - Receive FIFO Almost Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RAFL register
+ */
+/*@{*/
+#define ENET_RD_RAFL(base)       (ENET_RAFL_REG(base))
+#define ENET_WR_RAFL(base, value) (ENET_RAFL_REG(base) = (value))
+#define ENET_RMW_RAFL(base, mask, value) (ENET_WR_RAFL(base, (ENET_RD_RAFL(base) & ~(mask)) | (value)))
+#define ENET_SET_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) |  (value)))
+#define ENET_CLR_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) & ~(value)))
+#define ENET_TOG_RAFL(base, value) (ENET_WR_RAFL(base, ENET_RD_RAFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
+ * truncates the received frame to avoid FIFO overflow. The corresponding error
+ * status will be set when the frame is delivered to the application. A minimum
+ * value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field. */
+#define ENET_RD_RAFL_RX_ALMOST_FULL(base) ((ENET_RAFL_REG(base) & ENET_RAFL_RX_ALMOST_FULL_MASK) >> ENET_RAFL_RX_ALMOST_FULL_SHIFT)
+#define ENET_BRD_RAFL_RX_ALMOST_FULL(base) (ENET_RD_RAFL_RX_ALMOST_FULL(base))
+
+/*! @brief Set the RX_ALMOST_FULL field to a new value. */
+#define ENET_WR_RAFL_RX_ALMOST_FULL(base, value) (ENET_RMW_RAFL(base, ENET_RAFL_RX_ALMOST_FULL_MASK, ENET_RAFL_RX_ALMOST_FULL(value)))
+#define ENET_BWR_RAFL_RX_ALMOST_FULL(base, value) (ENET_WR_RAFL_RX_ALMOST_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TSEM - Transmit FIFO Section Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TSEM register
+ */
+/*@{*/
+#define ENET_RD_TSEM(base)       (ENET_TSEM_REG(base))
+#define ENET_WR_TSEM(base, value) (ENET_TSEM_REG(base) = (value))
+#define ENET_RMW_TSEM(base, mask, value) (ENET_WR_TSEM(base, (ENET_RD_TSEM(base) & ~(mask)) | (value)))
+#define ENET_SET_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) |  (value)))
+#define ENET_CLR_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) & ~(value)))
+#define ENET_TOG_TSEM(base, value) (ENET_WR_TSEM(base, ENET_RD_TSEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TSEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field. */
+#define ENET_RD_TSEM_TX_SECTION_EMPTY(base) ((ENET_TSEM_REG(base) & ENET_TSEM_TX_SECTION_EMPTY_MASK) >> ENET_TSEM_TX_SECTION_EMPTY_SHIFT)
+#define ENET_BRD_TSEM_TX_SECTION_EMPTY(base) (ENET_RD_TSEM_TX_SECTION_EMPTY(base))
+
+/*! @brief Set the TX_SECTION_EMPTY field to a new value. */
+#define ENET_WR_TSEM_TX_SECTION_EMPTY(base, value) (ENET_RMW_TSEM(base, ENET_TSEM_TX_SECTION_EMPTY_MASK, ENET_TSEM_TX_SECTION_EMPTY(value)))
+#define ENET_BWR_TSEM_TX_SECTION_EMPTY(base, value) (ENET_WR_TSEM_TX_SECTION_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TAEM - Transmit FIFO Almost Empty Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
+ *
+ * Reset value: 0x00000004U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TAEM register
+ */
+/*@{*/
+#define ENET_RD_TAEM(base)       (ENET_TAEM_REG(base))
+#define ENET_WR_TAEM(base, value) (ENET_TAEM_REG(base) = (value))
+#define ENET_RMW_TAEM(base, mask, value) (ENET_WR_TAEM(base, (ENET_RD_TAEM(base) & ~(mask)) | (value)))
+#define ENET_SET_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) |  (value)))
+#define ENET_CLR_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) & ~(value)))
+#define ENET_TOG_TAEM(base, value) (ENET_WR_TAEM(base, ENET_RD_TAEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TAEM bitfields
+ */
+
+/*!
+ * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
+ * FIFO level reaches the value programmed in this field, and no end-of-frame is
+ * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
+ * stops reading the FIFO and transmits a frame with an MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A minimum value of 4 should be set.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field. */
+#define ENET_RD_TAEM_TX_ALMOST_EMPTY(base) ((ENET_TAEM_REG(base) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) >> ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)
+#define ENET_BRD_TAEM_TX_ALMOST_EMPTY(base) (ENET_RD_TAEM_TX_ALMOST_EMPTY(base))
+
+/*! @brief Set the TX_ALMOST_EMPTY field to a new value. */
+#define ENET_WR_TAEM_TX_ALMOST_EMPTY(base, value) (ENET_RMW_TAEM(base, ENET_TAEM_TX_ALMOST_EMPTY_MASK, ENET_TAEM_TX_ALMOST_EMPTY(value)))
+#define ENET_BWR_TAEM_TX_ALMOST_EMPTY(base, value) (ENET_WR_TAEM_TX_ALMOST_EMPTY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TAFL - Transmit FIFO Almost Full Threshold
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
+ *
+ * Reset value: 0x00000008U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TAFL register
+ */
+/*@{*/
+#define ENET_RD_TAFL(base)       (ENET_TAFL_REG(base))
+#define ENET_WR_TAFL(base, value) (ENET_TAFL_REG(base) = (value))
+#define ENET_RMW_TAFL(base, mask, value) (ENET_WR_TAFL(base, (ENET_RD_TAFL(base) & ~(mask)) | (value)))
+#define ENET_SET_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) |  (value)))
+#define ENET_CLR_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) & ~(value)))
+#define ENET_TOG_TAFL(base, value) (ENET_WR_TAFL(base, ENET_RD_TAFL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TAFL bitfields
+ */
+
+/*!
+ * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
+ *
+ * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
+ * value of six is required . A recommended value of at least 8 should be set
+ * allowing a latency of two clock cycles to the application. If more latency is
+ * required the value can be increased as necessary (latency = TAFL - 5). When the
+ * FIFO level comes close to the maximum, so that there is no more space for at
+ * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
+ * application does not react on this signal, the FIFO write control logic, to
+ * avoid FIFO overflow, truncates the current frame and sets the error status. As a
+ * result, the frame will be transmitted with an GMII/MII error indication. See
+ * Transmit FIFOFour programmable thresholds are available which control the core
+ * operation. for more information. A FIFO overflow is a fatal error and requires
+ * a global reset on the transmit datapath or at least deassertion of ETHEREN.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field. */
+#define ENET_RD_TAFL_TX_ALMOST_FULL(base) ((ENET_TAFL_REG(base) & ENET_TAFL_TX_ALMOST_FULL_MASK) >> ENET_TAFL_TX_ALMOST_FULL_SHIFT)
+#define ENET_BRD_TAFL_TX_ALMOST_FULL(base) (ENET_RD_TAFL_TX_ALMOST_FULL(base))
+
+/*! @brief Set the TX_ALMOST_FULL field to a new value. */
+#define ENET_WR_TAFL_TX_ALMOST_FULL(base, value) (ENET_RMW_TAFL(base, ENET_TAFL_TX_ALMOST_FULL_MASK, ENET_TAFL_TX_ALMOST_FULL(value)))
+#define ENET_BWR_TAFL_TX_ALMOST_FULL(base, value) (ENET_WR_TAFL_TX_ALMOST_FULL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TIPG - Transmit Inter-Packet Gap
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TIPG - Transmit Inter-Packet Gap (RW)
+ *
+ * Reset value: 0x0000000CU
+ */
+/*!
+ * @name Constants and macros for entire ENET_TIPG register
+ */
+/*@{*/
+#define ENET_RD_TIPG(base)       (ENET_TIPG_REG(base))
+#define ENET_WR_TIPG(base, value) (ENET_TIPG_REG(base) = (value))
+#define ENET_RMW_TIPG(base, mask, value) (ENET_WR_TIPG(base, (ENET_RD_TIPG(base) & ~(mask)) | (value)))
+#define ENET_SET_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) |  (value)))
+#define ENET_CLR_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) & ~(value)))
+#define ENET_TOG_TIPG(base, value) (ENET_WR_TIPG(base, ENET_RD_TIPG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TIPG bitfields
+ */
+
+/*!
+ * @name Register ENET_TIPG, field IPG[4:0] (RW)
+ *
+ * Indicates the IPG, in bytes, between transmitted frames. Valid values range
+ * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
+ * 27, the IPG is 27.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TIPG_IPG field. */
+#define ENET_RD_TIPG_IPG(base) ((ENET_TIPG_REG(base) & ENET_TIPG_IPG_MASK) >> ENET_TIPG_IPG_SHIFT)
+#define ENET_BRD_TIPG_IPG(base) (ENET_RD_TIPG_IPG(base))
+
+/*! @brief Set the IPG field to a new value. */
+#define ENET_WR_TIPG_IPG(base, value) (ENET_RMW_TIPG(base, ENET_TIPG_IPG_MASK, ENET_TIPG_IPG(value)))
+#define ENET_BWR_TIPG_IPG(base, value) (ENET_WR_TIPG_IPG(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_FTRL - Frame Truncation Length
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_FTRL - Frame Truncation Length (RW)
+ *
+ * Reset value: 0x000007FFU
+ */
+/*!
+ * @name Constants and macros for entire ENET_FTRL register
+ */
+/*@{*/
+#define ENET_RD_FTRL(base)       (ENET_FTRL_REG(base))
+#define ENET_WR_FTRL(base, value) (ENET_FTRL_REG(base) = (value))
+#define ENET_RMW_FTRL(base, mask, value) (ENET_WR_FTRL(base, (ENET_RD_FTRL(base) & ~(mask)) | (value)))
+#define ENET_SET_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) |  (value)))
+#define ENET_CLR_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) & ~(value)))
+#define ENET_TOG_FTRL(base, value) (ENET_WR_FTRL(base, ENET_RD_FTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_FTRL bitfields
+ */
+
+/*!
+ * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
+ *
+ * Indicates the value a receive frame is truncated, if it is greater than this
+ * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
+ * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
+ * less data, guaranteeing that it never receives more than the set limit.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_FTRL_TRUNC_FL field. */
+#define ENET_RD_FTRL_TRUNC_FL(base) ((ENET_FTRL_REG(base) & ENET_FTRL_TRUNC_FL_MASK) >> ENET_FTRL_TRUNC_FL_SHIFT)
+#define ENET_BRD_FTRL_TRUNC_FL(base) (ENET_RD_FTRL_TRUNC_FL(base))
+
+/*! @brief Set the TRUNC_FL field to a new value. */
+#define ENET_WR_FTRL_TRUNC_FL(base, value) (ENET_RMW_FTRL(base, ENET_FTRL_TRUNC_FL_MASK, ENET_FTRL_TRUNC_FL(value)))
+#define ENET_BWR_FTRL_TRUNC_FL(base, value) (ENET_WR_FTRL_TRUNC_FL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TACC - Transmit Accelerator Function Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TACC - Transmit Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TACC controls accelerator actions when sending frames. The register can be
+ * changed before or after each frame, but it must remain unmodified during frame
+ * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
+ * checksum feature.
+ */
+/*!
+ * @name Constants and macros for entire ENET_TACC register
+ */
+/*@{*/
+#define ENET_RD_TACC(base)       (ENET_TACC_REG(base))
+#define ENET_WR_TACC(base, value) (ENET_TACC_REG(base) = (value))
+#define ENET_RMW_TACC(base, mask, value) (ENET_WR_TACC(base, (ENET_RD_TACC(base) & ~(mask)) | (value)))
+#define ENET_SET_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) |  (value)))
+#define ENET_CLR_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) & ~(value)))
+#define ENET_TOG_TACC(base, value) (ENET_WR_TACC(base, ENET_RD_TACC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TACC bitfields
+ */
+
+/*!
+ * @name Register ENET_TACC, field SHIFT16[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Indicates to the transmit data FIFO that the written frames contain
+ *     two additional octets before the frame data. This means the actual frame
+ *     begins at bit 16 of the first word written into the FIFO. This function
+ *     allows putting the frame payload on a 32-bit boundary in memory, as the
+ *     14-byte Ethernet header is extended to a 16-byte header.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_SHIFT16 field. */
+#define ENET_RD_TACC_SHIFT16(base) ((ENET_TACC_REG(base) & ENET_TACC_SHIFT16_MASK) >> ENET_TACC_SHIFT16_SHIFT)
+#define ENET_BRD_TACC_SHIFT16(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_SHIFT16_SHIFT))
+
+/*! @brief Set the SHIFT16 field to a new value. */
+#define ENET_WR_TACC_SHIFT16(base, value) (ENET_RMW_TACC(base, ENET_TACC_SHIFT16_MASK, ENET_TACC_SHIFT16(value)))
+#define ENET_BWR_TACC_SHIFT16(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_SHIFT16_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TACC, field IPCHK[3] (RW)
+ *
+ * Enables insertion of IP header checksum.
+ *
+ * Values:
+ * - 0b0 - Checksum is not inserted.
+ * - 0b1 - If an IP frame is transmitted, the checksum is inserted
+ *     automatically. The IP header checksum field must be cleared. If a non-IP frame is
+ *     transmitted the frame is not modified.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_IPCHK field. */
+#define ENET_RD_TACC_IPCHK(base) ((ENET_TACC_REG(base) & ENET_TACC_IPCHK_MASK) >> ENET_TACC_IPCHK_SHIFT)
+#define ENET_BRD_TACC_IPCHK(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_IPCHK_SHIFT))
+
+/*! @brief Set the IPCHK field to a new value. */
+#define ENET_WR_TACC_IPCHK(base, value) (ENET_RMW_TACC(base, ENET_TACC_IPCHK_MASK, ENET_TACC_IPCHK(value)))
+#define ENET_BWR_TACC_IPCHK(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_IPCHK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TACC, field PROCHK[4] (RW)
+ *
+ * Enables insertion of protocol checksum.
+ *
+ * Values:
+ * - 0b0 - Checksum not inserted.
+ * - 0b1 - If an IP frame with a known protocol is transmitted, the checksum is
+ *     inserted automatically into the frame. The checksum field must be cleared.
+ *     The other frames are not modified.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TACC_PROCHK field. */
+#define ENET_RD_TACC_PROCHK(base) ((ENET_TACC_REG(base) & ENET_TACC_PROCHK_MASK) >> ENET_TACC_PROCHK_SHIFT)
+#define ENET_BRD_TACC_PROCHK(base) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_PROCHK_SHIFT))
+
+/*! @brief Set the PROCHK field to a new value. */
+#define ENET_WR_TACC_PROCHK(base, value) (ENET_RMW_TACC(base, ENET_TACC_PROCHK_MASK, ENET_TACC_PROCHK(value)))
+#define ENET_BWR_TACC_PROCHK(base, value) (BITBAND_ACCESS32(&ENET_TACC_REG(base), ENET_TACC_PROCHK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RACC - Receive Accelerator Function Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RACC - Receive Accelerator Function Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RACC register
+ */
+/*@{*/
+#define ENET_RD_RACC(base)       (ENET_RACC_REG(base))
+#define ENET_WR_RACC(base, value) (ENET_RACC_REG(base) = (value))
+#define ENET_RMW_RACC(base, mask, value) (ENET_WR_RACC(base, (ENET_RD_RACC(base) & ~(mask)) | (value)))
+#define ENET_SET_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) |  (value)))
+#define ENET_CLR_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) & ~(value)))
+#define ENET_TOG_RACC(base, value) (ENET_WR_RACC(base, ENET_RD_RACC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RACC bitfields
+ */
+
+/*!
+ * @name Register ENET_RACC, field PADREM[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Padding not removed.
+ * - 0b1 - Any bytes following the IP payload section of the frame are removed
+ *     from the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_PADREM field. */
+#define ENET_RD_RACC_PADREM(base) ((ENET_RACC_REG(base) & ENET_RACC_PADREM_MASK) >> ENET_RACC_PADREM_SHIFT)
+#define ENET_BRD_RACC_PADREM(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PADREM_SHIFT))
+
+/*! @brief Set the PADREM field to a new value. */
+#define ENET_WR_RACC_PADREM(base, value) (ENET_RMW_RACC(base, ENET_RACC_PADREM_MASK, ENET_RACC_PADREM(value)))
+#define ENET_BWR_RACC_PADREM(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PADREM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field IPDIS[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with wrong IPv4 header checksum are not discarded.
+ * - 0b1 - If an IPv4 frame is received with a mismatching header checksum, the
+ *     frame is discarded. IPv6 has no header checksum and is not affected by
+ *     this setting. Discarding is only available when the RX FIFO operates in store
+ *     and forward mode (RSFL cleared).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_IPDIS field. */
+#define ENET_RD_RACC_IPDIS(base) ((ENET_RACC_REG(base) & ENET_RACC_IPDIS_MASK) >> ENET_RACC_IPDIS_SHIFT)
+#define ENET_BRD_RACC_IPDIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_IPDIS_SHIFT))
+
+/*! @brief Set the IPDIS field to a new value. */
+#define ENET_WR_RACC_IPDIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_IPDIS_MASK, ENET_RACC_IPDIS(value)))
+#define ENET_BWR_RACC_IPDIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_IPDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field PRODIS[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with wrong checksum are not discarded.
+ * - 0b1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong
+ *     TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only
+ *     available when the RX FIFO operates in store and forward mode (RSFL cleared).
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_PRODIS field. */
+#define ENET_RD_RACC_PRODIS(base) ((ENET_RACC_REG(base) & ENET_RACC_PRODIS_MASK) >> ENET_RACC_PRODIS_SHIFT)
+#define ENET_BRD_RACC_PRODIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PRODIS_SHIFT))
+
+/*! @brief Set the PRODIS field to a new value. */
+#define ENET_WR_RACC_PRODIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_PRODIS_MASK, ENET_RACC_PRODIS(value)))
+#define ENET_BWR_RACC_PRODIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_PRODIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field LINEDIS[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Frames with errors are not discarded.
+ * - 0b1 - Any frame received with a CRC, length, or PHY error is automatically
+ *     discarded and not forwarded to the user application interface.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_LINEDIS field. */
+#define ENET_RD_RACC_LINEDIS(base) ((ENET_RACC_REG(base) & ENET_RACC_LINEDIS_MASK) >> ENET_RACC_LINEDIS_SHIFT)
+#define ENET_BRD_RACC_LINEDIS(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_LINEDIS_SHIFT))
+
+/*! @brief Set the LINEDIS field to a new value. */
+#define ENET_WR_RACC_LINEDIS(base, value) (ENET_RMW_RACC(base, ENET_RACC_LINEDIS_MASK, ENET_RACC_LINEDIS(value)))
+#define ENET_BWR_RACC_LINEDIS(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_LINEDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_RACC, field SHIFT16[7] (RW)
+ *
+ * When this field is set, the actual frame data starts at bit 16 of the first
+ * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
+ * This function only affects the FIFO storage and has no influence on the
+ * statistics, which use the actual length of the frame received.
+ *
+ * Values:
+ * - 0b0 - Disabled.
+ * - 0b1 - Instructs the MAC to write two additional bytes in front of each
+ *     frame received into the RX FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RACC_SHIFT16 field. */
+#define ENET_RD_RACC_SHIFT16(base) ((ENET_RACC_REG(base) & ENET_RACC_SHIFT16_MASK) >> ENET_RACC_SHIFT16_SHIFT)
+#define ENET_BRD_RACC_SHIFT16(base) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_SHIFT16_SHIFT))
+
+/*! @brief Set the SHIFT16 field to a new value. */
+#define ENET_WR_RACC_SHIFT16(base, value) (ENET_RMW_RACC(base, ENET_RACC_SHIFT16_MASK, ENET_RACC_SHIFT16(value)))
+#define ENET_BWR_RACC_SHIFT16(base, value) (BITBAND_ACCESS32(&ENET_RACC_REG(base), ENET_RACC_SHIFT16_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_PACKETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_PACKETS(base) (ENET_RMON_T_PACKETS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field. */
+#define ENET_RD_RMON_T_PACKETS_TXPKTS(base) ((ENET_RMON_T_PACKETS_REG(base) & ENET_RMON_T_PACKETS_TXPKTS_MASK) >> ENET_RMON_T_PACKETS_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_PACKETS_TXPKTS(base) (ENET_RD_RMON_T_PACKETS_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RMON Tx Broadcast Packets
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_BC_PKT(base) (ENET_RMON_T_BC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field. */
+#define ENET_RD_RMON_T_BC_PKT_TXPKTS(base) ((ENET_RMON_T_BC_PKT_REG(base) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) >> ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_BC_PKT_TXPKTS(base) (ENET_RD_RMON_T_BC_PKT_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_MC_PKT(base) (ENET_RMON_T_MC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field. */
+#define ENET_RD_RMON_T_MC_PKT_TXPKTS(base) ((ENET_RMON_T_MC_PKT_REG(base) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) >> ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_MC_PKT_TXPKTS(base) (ENET_RD_RMON_T_MC_PKT_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_CRC_ALIGN(base) (ENET_RMON_T_CRC_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field. */
+#define ENET_RD_RMON_T_CRC_ALIGN_TXPKTS(base) ((ENET_RMON_T_CRC_ALIGN_REG(base) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) >> ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_CRC_ALIGN_TXPKTS(base) (ENET_RD_RMON_T_CRC_ALIGN_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_UNDERSIZE(base) (ENET_RMON_T_UNDERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field. */
+#define ENET_RD_RMON_T_UNDERSIZE_TXPKTS(base) ((ENET_RMON_T_UNDERSIZE_REG(base) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) >> ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_UNDERSIZE_TXPKTS(base) (ENET_RD_RMON_T_UNDERSIZE_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_OVERSIZE(base) (ENET_RMON_T_OVERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field. */
+#define ENET_RD_RMON_T_OVERSIZE_TXPKTS(base) ((ENET_RMON_T_OVERSIZE_REG(base) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) >> ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_OVERSIZE_TXPKTS(base) (ENET_RD_RMON_T_OVERSIZE_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_FRAG register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_FRAG(base) (ENET_RMON_T_FRAG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field. */
+#define ENET_RD_RMON_T_FRAG_TXPKTS(base) ((ENET_RMON_T_FRAG_REG(base) & ENET_RMON_T_FRAG_TXPKTS_MASK) >> ENET_RMON_T_FRAG_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_FRAG_TXPKTS(base) (ENET_RD_RMON_T_FRAG_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_JAB register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_JAB(base) (ENET_RMON_T_JAB_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field. */
+#define ENET_RD_RMON_T_JAB_TXPKTS(base) ((ENET_RMON_T_JAB_REG(base) & ENET_RMON_T_JAB_TXPKTS_MASK) >> ENET_RMON_T_JAB_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_JAB_TXPKTS(base) (ENET_RD_RMON_T_JAB_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_COL - Tx Collision Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_COL register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_COL(base) (ENET_RMON_T_COL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_COL bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field. */
+#define ENET_RD_RMON_T_COL_TXPKTS(base) ((ENET_RMON_T_COL_REG(base) & ENET_RMON_T_COL_TXPKTS_MASK) >> ENET_RMON_T_COL_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_COL_TXPKTS(base) (ENET_RD_RMON_T_COL_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P64 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P64(base) (ENET_RMON_T_P64_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field. */
+#define ENET_RD_RMON_T_P64_TXPKTS(base) ((ENET_RMON_T_P64_REG(base) & ENET_RMON_T_P64_TXPKTS_MASK) >> ENET_RMON_T_P64_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P64_TXPKTS(base) (ENET_RD_RMON_T_P64_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P65TO127(base) (ENET_RMON_T_P65TO127_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field. */
+#define ENET_RD_RMON_T_P65TO127_TXPKTS(base) ((ENET_RMON_T_P65TO127_REG(base) & ENET_RMON_T_P65TO127_TXPKTS_MASK) >> ENET_RMON_T_P65TO127_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P65TO127_TXPKTS(base) (ENET_RD_RMON_T_P65TO127_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P128TO255(base) (ENET_RMON_T_P128TO255_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field. */
+#define ENET_RD_RMON_T_P128TO255_TXPKTS(base) ((ENET_RMON_T_P128TO255_REG(base) & ENET_RMON_T_P128TO255_TXPKTS_MASK) >> ENET_RMON_T_P128TO255_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P128TO255_TXPKTS(base) (ENET_RD_RMON_T_P128TO255_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P256TO511(base) (ENET_RMON_T_P256TO511_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field. */
+#define ENET_RD_RMON_T_P256TO511_TXPKTS(base) ((ENET_RMON_T_P256TO511_REG(base) & ENET_RMON_T_P256TO511_TXPKTS_MASK) >> ENET_RMON_T_P256TO511_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P256TO511_TXPKTS(base) (ENET_RD_RMON_T_P256TO511_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * .
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P512TO1023(base) (ENET_RMON_T_P512TO1023_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field. */
+#define ENET_RD_RMON_T_P512TO1023_TXPKTS(base) ((ENET_RMON_T_P512TO1023_REG(base) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) >> ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P512TO1023_TXPKTS(base) (ENET_RD_RMON_T_P512TO1023_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P1024TO2047(base) (ENET_RMON_T_P1024TO2047_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field. */
+#define ENET_RD_RMON_T_P1024TO2047_TXPKTS(base) ((ENET_RMON_T_P1024TO2047_REG(base) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) >> ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P1024TO2047_TXPKTS(base) (ENET_RD_RMON_T_P1024TO2047_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_P_GTE2048(base) (ENET_RMON_T_P_GTE2048_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field. */
+#define ENET_RD_RMON_T_P_GTE2048_TXPKTS(base) ((ENET_RMON_T_P_GTE2048_REG(base) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) >> ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)
+#define ENET_BRD_RMON_T_P_GTE2048_TXPKTS(base) (ENET_RD_RMON_T_P_GTE2048_TXPKTS(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_T_OCTETS - Tx Octets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_T_OCTETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_T_OCTETS(base) (ENET_RMON_T_OCTETS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_FRAME_OK(base) (ENET_IEEE_T_FRAME_OK_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field. */
+#define ENET_RD_IEEE_T_FRAME_OK_COUNT(base) ((ENET_IEEE_T_FRAME_OK_REG(base) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) >> ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_FRAME_OK_COUNT(base) (ENET_RD_IEEE_T_FRAME_OK_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_1COL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_1COL(base) (ENET_IEEE_T_1COL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_1COL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field. */
+#define ENET_RD_IEEE_T_1COL_COUNT(base) ((ENET_IEEE_T_1COL_REG(base) & ENET_IEEE_T_1COL_COUNT_MASK) >> ENET_IEEE_T_1COL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_1COL_COUNT(base) (ENET_RD_IEEE_T_1COL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_MCOL(base) (ENET_IEEE_T_MCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field. */
+#define ENET_RD_IEEE_T_MCOL_COUNT(base) ((ENET_IEEE_T_MCOL_REG(base) & ENET_IEEE_T_MCOL_COUNT_MASK) >> ENET_IEEE_T_MCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_MCOL_COUNT(base) (ENET_RD_IEEE_T_MCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_DEF register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_DEF(base) (ENET_IEEE_T_DEF_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_DEF bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field. */
+#define ENET_RD_IEEE_T_DEF_COUNT(base) ((ENET_IEEE_T_DEF_REG(base) & ENET_IEEE_T_DEF_COUNT_MASK) >> ENET_IEEE_T_DEF_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_DEF_COUNT(base) (ENET_RD_IEEE_T_DEF_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_LCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_LCOL(base) (ENET_IEEE_T_LCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field. */
+#define ENET_RD_IEEE_T_LCOL_COUNT(base) ((ENET_IEEE_T_LCOL_REG(base) & ENET_IEEE_T_LCOL_COUNT_MASK) >> ENET_IEEE_T_LCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_LCOL_COUNT(base) (ENET_RD_IEEE_T_LCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_EXCOL(base) (ENET_IEEE_T_EXCOL_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field. */
+#define ENET_RD_IEEE_T_EXCOL_COUNT(base) ((ENET_IEEE_T_EXCOL_REG(base) & ENET_IEEE_T_EXCOL_COUNT_MASK) >> ENET_IEEE_T_EXCOL_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_EXCOL_COUNT(base) (ENET_RD_IEEE_T_EXCOL_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_MACERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_MACERR(base) (ENET_IEEE_T_MACERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field. */
+#define ENET_RD_IEEE_T_MACERR_COUNT(base) ((ENET_IEEE_T_MACERR_REG(base) & ENET_IEEE_T_MACERR_COUNT_MASK) >> ENET_IEEE_T_MACERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_MACERR_COUNT(base) (ENET_RD_IEEE_T_MACERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_CSERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_CSERR(base) (ENET_IEEE_T_CSERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field. */
+#define ENET_RD_IEEE_T_CSERR_COUNT(base) ((ENET_IEEE_T_CSERR_REG(base) & ENET_IEEE_T_CSERR_COUNT_MASK) >> ENET_IEEE_T_CSERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_CSERR_COUNT(base) (ENET_RD_IEEE_T_CSERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_FDXFC(base) (ENET_IEEE_T_FDXFC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field. */
+#define ENET_RD_IEEE_T_FDXFC_COUNT(base) ((ENET_IEEE_T_FDXFC_REG(base) & ENET_IEEE_T_FDXFC_COUNT_MASK) >> ENET_IEEE_T_FDXFC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_T_FDXFC_COUNT(base) (ENET_RD_IEEE_T_FDXFC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counts total octets (includes header and FCS fields).
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_T_OCTETS_OK(base) (ENET_IEEE_T_OCTETS_OK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_PACKETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_PACKETS(base) (ENET_RMON_R_PACKETS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field. */
+#define ENET_RD_RMON_R_PACKETS_COUNT(base) ((ENET_RMON_R_PACKETS_REG(base) & ENET_RMON_R_PACKETS_COUNT_MASK) >> ENET_RMON_R_PACKETS_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_PACKETS_COUNT(base) (ENET_RD_RMON_R_PACKETS_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_BC_PKT(base) (ENET_RMON_R_BC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field. */
+#define ENET_RD_RMON_R_BC_PKT_COUNT(base) ((ENET_RMON_R_BC_PKT_REG(base) & ENET_RMON_R_BC_PKT_COUNT_MASK) >> ENET_RMON_R_BC_PKT_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_BC_PKT_COUNT(base) (ENET_RD_RMON_R_BC_PKT_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_MC_PKT(base) (ENET_RMON_R_MC_PKT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field. */
+#define ENET_RD_RMON_R_MC_PKT_COUNT(base) ((ENET_RMON_R_MC_PKT_REG(base) & ENET_RMON_R_MC_PKT_COUNT_MASK) >> ENET_RMON_R_MC_PKT_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_MC_PKT_COUNT(base) (ENET_RD_RMON_R_MC_PKT_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_CRC_ALIGN(base) (ENET_RMON_R_CRC_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field. */
+#define ENET_RD_RMON_R_CRC_ALIGN_COUNT(base) ((ENET_RMON_R_CRC_ALIGN_REG(base) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) >> ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_CRC_ALIGN_COUNT(base) (ENET_RD_RMON_R_CRC_ALIGN_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_UNDERSIZE(base) (ENET_RMON_R_UNDERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field. */
+#define ENET_RD_RMON_R_UNDERSIZE_COUNT(base) ((ENET_RMON_R_UNDERSIZE_REG(base) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) >> ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_UNDERSIZE_COUNT(base) (ENET_RD_RMON_R_UNDERSIZE_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_OVERSIZE(base) (ENET_RMON_R_OVERSIZE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field. */
+#define ENET_RD_RMON_R_OVERSIZE_COUNT(base) ((ENET_RMON_R_OVERSIZE_REG(base) & ENET_RMON_R_OVERSIZE_COUNT_MASK) >> ENET_RMON_R_OVERSIZE_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_OVERSIZE_COUNT(base) (ENET_RD_RMON_R_OVERSIZE_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_FRAG register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_FRAG(base) (ENET_RMON_R_FRAG_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_FRAG bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field. */
+#define ENET_RD_RMON_R_FRAG_COUNT(base) ((ENET_RMON_R_FRAG_REG(base) & ENET_RMON_R_FRAG_COUNT_MASK) >> ENET_RMON_R_FRAG_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_FRAG_COUNT(base) (ENET_RD_RMON_R_FRAG_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_JAB register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_JAB(base) (ENET_RMON_R_JAB_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_JAB bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_JAB_COUNT field. */
+#define ENET_RD_RMON_R_JAB_COUNT(base) ((ENET_RMON_R_JAB_REG(base) & ENET_RMON_R_JAB_COUNT_MASK) >> ENET_RMON_R_JAB_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_JAB_COUNT(base) (ENET_RD_RMON_R_JAB_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P64 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P64(base) (ENET_RMON_R_P64_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P64 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P64_COUNT field. */
+#define ENET_RD_RMON_R_P64_COUNT(base) ((ENET_RMON_R_P64_REG(base) & ENET_RMON_R_P64_COUNT_MASK) >> ENET_RMON_R_P64_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P64_COUNT(base) (ENET_RD_RMON_R_P64_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P65TO127(base) (ENET_RMON_R_P65TO127_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field. */
+#define ENET_RD_RMON_R_P65TO127_COUNT(base) ((ENET_RMON_R_P65TO127_REG(base) & ENET_RMON_R_P65TO127_COUNT_MASK) >> ENET_RMON_R_P65TO127_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P65TO127_COUNT(base) (ENET_RD_RMON_R_P65TO127_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P128TO255(base) (ENET_RMON_R_P128TO255_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field. */
+#define ENET_RD_RMON_R_P128TO255_COUNT(base) ((ENET_RMON_R_P128TO255_REG(base) & ENET_RMON_R_P128TO255_COUNT_MASK) >> ENET_RMON_R_P128TO255_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P128TO255_COUNT(base) (ENET_RD_RMON_R_P128TO255_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P256TO511(base) (ENET_RMON_R_P256TO511_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field. */
+#define ENET_RD_RMON_R_P256TO511_COUNT(base) ((ENET_RMON_R_P256TO511_REG(base) & ENET_RMON_R_P256TO511_COUNT_MASK) >> ENET_RMON_R_P256TO511_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P256TO511_COUNT(base) (ENET_RD_RMON_R_P256TO511_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P512TO1023(base) (ENET_RMON_R_P512TO1023_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field. */
+#define ENET_RD_RMON_R_P512TO1023_COUNT(base) ((ENET_RMON_R_P512TO1023_REG(base) & ENET_RMON_R_P512TO1023_COUNT_MASK) >> ENET_RMON_R_P512TO1023_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P512TO1023_COUNT(base) (ENET_RD_RMON_R_P512TO1023_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P1024TO2047(base) (ENET_RMON_R_P1024TO2047_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field. */
+#define ENET_RD_RMON_R_P1024TO2047_COUNT(base) ((ENET_RMON_R_P1024TO2047_REG(base) & ENET_RMON_R_P1024TO2047_COUNT_MASK) >> ENET_RMON_R_P1024TO2047_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P1024TO2047_COUNT(base) (ENET_RD_RMON_R_P1024TO2047_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_P_GTE2048 register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_P_GTE2048(base) (ENET_RMON_R_P_GTE2048_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_RMON_R_P_GTE2048 bitfields
+ */
+
+/*!
+ * @name Register ENET_RMON_R_P_GTE2048, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_RMON_R_P_GTE2048_COUNT field. */
+#define ENET_RD_RMON_R_P_GTE2048_COUNT(base) ((ENET_RMON_R_P_GTE2048_REG(base) & ENET_RMON_R_P_GTE2048_COUNT_MASK) >> ENET_RMON_R_P_GTE2048_COUNT_SHIFT)
+#define ENET_BRD_RMON_R_P_GTE2048_COUNT(base) (ENET_RD_RMON_R_P_GTE2048_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_RMON_R_OCTETS - Rx Octets Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_RMON_R_OCTETS register
+ */
+/*@{*/
+#define ENET_RD_RMON_R_OCTETS(base) (ENET_RMON_R_OCTETS_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Counter increments if a frame with invalid or missing SFD character is
+ * detected and has been dropped. None of the other counters increments if this counter
+ * increments.
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_DROP register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_DROP(base) (ENET_IEEE_R_DROP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_DROP bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field. */
+#define ENET_RD_IEEE_R_DROP_COUNT(base) ((ENET_IEEE_R_DROP_REG(base) & ENET_IEEE_R_DROP_COUNT_MASK) >> ENET_IEEE_R_DROP_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_DROP_COUNT(base) (ENET_RD_IEEE_R_DROP_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_FRAME_OK(base) (ENET_IEEE_R_FRAME_OK_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field. */
+#define ENET_RD_IEEE_R_FRAME_OK_COUNT(base) ((ENET_IEEE_R_FRAME_OK_REG(base) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) >> ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_FRAME_OK_COUNT(base) (ENET_RD_IEEE_R_FRAME_OK_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_CRC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_CRC(base) (ENET_IEEE_R_CRC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_CRC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field. */
+#define ENET_RD_IEEE_R_CRC_COUNT(base) ((ENET_IEEE_R_CRC_REG(base) & ENET_IEEE_R_CRC_COUNT_MASK) >> ENET_IEEE_R_CRC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_CRC_COUNT(base) (ENET_RD_IEEE_R_CRC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_ALIGN(base) (ENET_IEEE_R_ALIGN_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field. */
+#define ENET_RD_IEEE_R_ALIGN_COUNT(base) ((ENET_IEEE_R_ALIGN_REG(base) & ENET_IEEE_R_ALIGN_COUNT_MASK) >> ENET_IEEE_R_ALIGN_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_ALIGN_COUNT(base) (ENET_RD_IEEE_R_ALIGN_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_MACERR register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_MACERR(base) (ENET_IEEE_R_MACERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field. */
+#define ENET_RD_IEEE_R_MACERR_COUNT(base) ((ENET_IEEE_R_MACERR_REG(base) & ENET_IEEE_R_MACERR_COUNT_MASK) >> ENET_IEEE_R_MACERR_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_MACERR_COUNT(base) (ENET_RD_IEEE_R_MACERR_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_FDXFC(base) (ENET_IEEE_R_FDXFC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
+ */
+
+/*!
+ * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field. */
+#define ENET_RD_IEEE_R_FDXFC_COUNT(base) ((ENET_IEEE_R_FDXFC_REG(base) & ENET_IEEE_R_FDXFC_COUNT_MASK) >> ENET_IEEE_R_FDXFC_COUNT_SHIFT)
+#define ENET_BRD_IEEE_R_FDXFC_COUNT(base) (ENET_RD_IEEE_R_FDXFC_COUNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
+ */
+/*@{*/
+#define ENET_RD_IEEE_R_OCTETS_OK(base) (ENET_IEEE_R_OCTETS_OK_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATCR - Adjustable Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATCR - Adjustable Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * ATCR command fields can trigger the corresponding events directly. It is not
+ * necessary to preserve any of the configuration fields when a command field is
+ * set in the register, that is, no read-modify-write is required. The fields are
+ * automatically cleared after the command completes.
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATCR register
+ */
+/*@{*/
+#define ENET_RD_ATCR(base)       (ENET_ATCR_REG(base))
+#define ENET_WR_ATCR(base, value) (ENET_ATCR_REG(base) = (value))
+#define ENET_RMW_ATCR(base, mask, value) (ENET_WR_ATCR(base, (ENET_RD_ATCR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) |  (value)))
+#define ENET_CLR_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) & ~(value)))
+#define ENET_TOG_ATCR(base, value) (ENET_WR_ATCR(base, ENET_RD_ATCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATCR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCR, field EN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer stops at the current value.
+ * - 0b1 - The timer starts incrementing.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_EN field. */
+#define ENET_RD_ATCR_EN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_EN_MASK) >> ENET_ATCR_EN_SHIFT)
+#define ENET_BRD_ATCR_EN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_EN_SHIFT))
+
+/*! @brief Set the EN field to a new value. */
+#define ENET_WR_ATCR_EN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_EN_MASK, ENET_ATCR_EN(value)))
+#define ENET_BWR_ATCR_EN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field OFFEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - The timer can be reset to zero when the given offset time is reached
+ *     (offset event). The field is cleared when the offset event is reached, so
+ *     no further event occurs until the field is set again. The timer offset
+ *     value must be set before setting this field.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_OFFEN field. */
+#define ENET_RD_ATCR_OFFEN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_OFFEN_MASK) >> ENET_ATCR_OFFEN_SHIFT)
+#define ENET_BRD_ATCR_OFFEN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFEN_SHIFT))
+
+/*! @brief Set the OFFEN field to a new value. */
+#define ENET_WR_ATCR_OFFEN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_OFFEN_MASK, ENET_ATCR_OFFEN(value)))
+#define ENET_BWR_ATCR_OFFEN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field OFFRST[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer is not affected and no action occurs, besides clearing
+ *     OFFEN, when the offset is reached.
+ * - 0b1 - If OFFEN is set, the timer resets to zero when the offset setting is
+ *     reached. The offset event does not cause a timer interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_OFFRST field. */
+#define ENET_RD_ATCR_OFFRST(base) ((ENET_ATCR_REG(base) & ENET_ATCR_OFFRST_MASK) >> ENET_ATCR_OFFRST_SHIFT)
+#define ENET_BRD_ATCR_OFFRST(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFRST_SHIFT))
+
+/*! @brief Set the OFFRST field to a new value. */
+#define ENET_WR_ATCR_OFFRST(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_OFFRST_MASK, ENET_ATCR_OFFRST(value)))
+#define ENET_BWR_ATCR_OFFRST(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_OFFRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field PEREN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the
+ *     event signal output is asserted when the timer wraps around according to the
+ *     periodic setting ATPER. The timer period value must be set before setting
+ *     this bit. Not all devices contain the event signal output. See the chip
+ *     configuration details.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_PEREN field. */
+#define ENET_RD_ATCR_PEREN(base) ((ENET_ATCR_REG(base) & ENET_ATCR_PEREN_MASK) >> ENET_ATCR_PEREN_SHIFT)
+#define ENET_BRD_ATCR_PEREN(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PEREN_SHIFT))
+
+/*! @brief Set the PEREN field to a new value. */
+#define ENET_WR_ATCR_PEREN(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_PEREN_MASK, ENET_ATCR_PEREN(value)))
+#define ENET_BWR_ATCR_PEREN(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field PINPER[7] (RW)
+ *
+ * Enables event signal output assertion on period event. Not all devices
+ * contain the event signal output. See the chip configuration details.
+ *
+ * Values:
+ * - 0b0 - Disable.
+ * - 0b1 - Enable.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_PINPER field. */
+#define ENET_RD_ATCR_PINPER(base) ((ENET_ATCR_REG(base) & ENET_ATCR_PINPER_MASK) >> ENET_ATCR_PINPER_SHIFT)
+#define ENET_BRD_ATCR_PINPER(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PINPER_SHIFT))
+
+/*! @brief Set the PINPER field to a new value. */
+#define ENET_WR_ATCR_PINPER(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_PINPER_MASK, ENET_ATCR_PINPER(value)))
+#define ENET_BWR_ATCR_PINPER(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_PINPER_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field RESTART[9] (RW)
+ *
+ * Resets the timer to zero. This has no effect on the counter enable. If the
+ * counter is enabled when this field is set, the timer is reset to zero and starts
+ * counting from there. When set, all other fields are ignored during a write.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_RESTART field. */
+#define ENET_RD_ATCR_RESTART(base) ((ENET_ATCR_REG(base) & ENET_ATCR_RESTART_MASK) >> ENET_ATCR_RESTART_SHIFT)
+#define ENET_BRD_ATCR_RESTART(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_RESTART_SHIFT))
+
+/*! @brief Set the RESTART field to a new value. */
+#define ENET_WR_ATCR_RESTART(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_RESTART_MASK, ENET_ATCR_RESTART(value)))
+#define ENET_BWR_ATCR_RESTART(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_RESTART_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field CAPTURE[11] (RW)
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - The current time is captured and can be read from the ATVR register.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_CAPTURE field. */
+#define ENET_RD_ATCR_CAPTURE(base) ((ENET_ATCR_REG(base) & ENET_ATCR_CAPTURE_MASK) >> ENET_ATCR_CAPTURE_SHIFT)
+#define ENET_BRD_ATCR_CAPTURE(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_CAPTURE_SHIFT))
+
+/*! @brief Set the CAPTURE field to a new value. */
+#define ENET_WR_ATCR_CAPTURE(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_CAPTURE_MASK, ENET_ATCR_CAPTURE(value)))
+#define ENET_BWR_ATCR_CAPTURE(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_CAPTURE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATCR, field SLAVE[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The timer is active and all configuration fields in this register are
+ *     relevant.
+ * - 0b1 - The internal timer is disabled and the externally provided timer
+ *     value is used. All other fields, except CAPTURE, in this register have no
+ *     effect. CAPTURE can still be used to capture the current timer value.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCR_SLAVE field. */
+#define ENET_RD_ATCR_SLAVE(base) ((ENET_ATCR_REG(base) & ENET_ATCR_SLAVE_MASK) >> ENET_ATCR_SLAVE_SHIFT)
+#define ENET_BRD_ATCR_SLAVE(base) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_SLAVE_SHIFT))
+
+/*! @brief Set the SLAVE field to a new value. */
+#define ENET_WR_ATCR_SLAVE(base, value) (ENET_RMW_ATCR(base, ENET_ATCR_SLAVE_MASK, ENET_ATCR_SLAVE(value)))
+#define ENET_BWR_ATCR_SLAVE(base, value) (BITBAND_ACCESS32(&ENET_ATCR_REG(base), ENET_ATCR_SLAVE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATVR - Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATVR - Timer Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATVR register
+ */
+/*@{*/
+#define ENET_RD_ATVR(base)       (ENET_ATVR_REG(base))
+#define ENET_WR_ATVR(base, value) (ENET_ATVR_REG(base) = (value))
+#define ENET_RMW_ATVR(base, mask, value) (ENET_WR_ATVR(base, (ENET_RD_ATVR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) |  (value)))
+#define ENET_CLR_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) & ~(value)))
+#define ENET_TOG_ATVR(base, value) (ENET_WR_ATVR(base, ENET_RD_ATVR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATOFF - Timer Offset Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATOFF - Timer Offset Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATOFF register
+ */
+/*@{*/
+#define ENET_RD_ATOFF(base)      (ENET_ATOFF_REG(base))
+#define ENET_WR_ATOFF(base, value) (ENET_ATOFF_REG(base) = (value))
+#define ENET_RMW_ATOFF(base, mask, value) (ENET_WR_ATOFF(base, (ENET_RD_ATOFF(base) & ~(mask)) | (value)))
+#define ENET_SET_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) |  (value)))
+#define ENET_CLR_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) & ~(value)))
+#define ENET_TOG_ATOFF(base, value) (ENET_WR_ATOFF(base, ENET_RD_ATOFF(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATPER - Timer Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATPER - Timer Period Register (RW)
+ *
+ * Reset value: 0x3B9ACA00U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATPER register
+ */
+/*@{*/
+#define ENET_RD_ATPER(base)      (ENET_ATPER_REG(base))
+#define ENET_WR_ATPER(base, value) (ENET_ATPER_REG(base) = (value))
+#define ENET_RMW_ATPER(base, mask, value) (ENET_WR_ATPER(base, (ENET_RD_ATPER(base) & ~(mask)) | (value)))
+#define ENET_SET_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) |  (value)))
+#define ENET_CLR_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) & ~(value)))
+#define ENET_TOG_ATPER(base, value) (ENET_WR_ATPER(base, ENET_RD_ATPER(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATCOR - Timer Correction Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATCOR - Timer Correction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATCOR register
+ */
+/*@{*/
+#define ENET_RD_ATCOR(base)      (ENET_ATCOR_REG(base))
+#define ENET_WR_ATCOR(base, value) (ENET_ATCOR_REG(base) = (value))
+#define ENET_RMW_ATCOR(base, mask, value) (ENET_WR_ATCOR(base, (ENET_RD_ATCOR(base) & ~(mask)) | (value)))
+#define ENET_SET_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) |  (value)))
+#define ENET_CLR_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) & ~(value)))
+#define ENET_TOG_ATCOR(base, value) (ENET_WR_ATCOR(base, ENET_RD_ATCOR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATCOR bitfields
+ */
+
+/*!
+ * @name Register ENET_ATCOR, field COR[30:0] (RW)
+ *
+ * Defines after how many timer clock cycles (ts_clk) the correction counter
+ * should be reset and trigger a correction increment on the timer. The amount of
+ * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
+ * counter and no corrections occur. This value is given in clock cycles, not in
+ * nanoseconds as all other values.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATCOR_COR field. */
+#define ENET_RD_ATCOR_COR(base) ((ENET_ATCOR_REG(base) & ENET_ATCOR_COR_MASK) >> ENET_ATCOR_COR_SHIFT)
+#define ENET_BRD_ATCOR_COR(base) (ENET_RD_ATCOR_COR(base))
+
+/*! @brief Set the COR field to a new value. */
+#define ENET_WR_ATCOR_COR(base, value) (ENET_RMW_ATCOR(base, ENET_ATCOR_COR_MASK, ENET_ATCOR_COR(value)))
+#define ENET_BWR_ATCOR_COR(base, value) (ENET_WR_ATCOR_COR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATINC - Time-Stamping Clock Period Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATINC - Time-Stamping Clock Period Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATINC register
+ */
+/*@{*/
+#define ENET_RD_ATINC(base)      (ENET_ATINC_REG(base))
+#define ENET_WR_ATINC(base, value) (ENET_ATINC_REG(base) = (value))
+#define ENET_RMW_ATINC(base, mask, value) (ENET_WR_ATINC(base, (ENET_RD_ATINC(base) & ~(mask)) | (value)))
+#define ENET_SET_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) |  (value)))
+#define ENET_CLR_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) & ~(value)))
+#define ENET_TOG_ATINC(base, value) (ENET_WR_ATINC(base, ENET_RD_ATINC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_ATINC bitfields
+ */
+
+/*!
+ * @name Register ENET_ATINC, field INC[6:0] (RW)
+ *
+ * The timer increments by this amount each clock cycle. For example, set to 10
+ * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
+ * that is an integer fraction of the period set in ATPER.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATINC_INC field. */
+#define ENET_RD_ATINC_INC(base) ((ENET_ATINC_REG(base) & ENET_ATINC_INC_MASK) >> ENET_ATINC_INC_SHIFT)
+#define ENET_BRD_ATINC_INC(base) (ENET_RD_ATINC_INC(base))
+
+/*! @brief Set the INC field to a new value. */
+#define ENET_WR_ATINC_INC(base, value) (ENET_RMW_ATINC(base, ENET_ATINC_INC_MASK, ENET_ATINC_INC(value)))
+#define ENET_BWR_ATINC_INC(base, value) (ENET_WR_ATINC_INC(base, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
+ *
+ * This value is added every time the correction timer expires (every clock
+ * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
+ * than INC speeds up the timer.
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_ATINC_INC_CORR field. */
+#define ENET_RD_ATINC_INC_CORR(base) ((ENET_ATINC_REG(base) & ENET_ATINC_INC_CORR_MASK) >> ENET_ATINC_INC_CORR_SHIFT)
+#define ENET_BRD_ATINC_INC_CORR(base) (ENET_RD_ATINC_INC_CORR(base))
+
+/*! @brief Set the INC_CORR field to a new value. */
+#define ENET_WR_ATINC_INC_CORR(base, value) (ENET_RMW_ATINC(base, ENET_ATINC_INC_CORR_MASK, ENET_ATINC_INC_CORR(value)))
+#define ENET_BWR_ATINC_INC_CORR(base, value) (ENET_WR_ATINC_INC_CORR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_ATSTMP - Timestamp of Last Transmitted Frame
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_ATSTMP register
+ */
+/*@{*/
+#define ENET_RD_ATSTMP(base)     (ENET_ATSTMP_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TGSR - Timer Global Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TGSR - Timer Global Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TGSR register
+ */
+/*@{*/
+#define ENET_RD_TGSR(base)       (ENET_TGSR_REG(base))
+#define ENET_WR_TGSR(base, value) (ENET_TGSR_REG(base) = (value))
+#define ENET_RMW_TGSR(base, mask, value) (ENET_WR_TGSR(base, (ENET_RD_TGSR(base) & ~(mask)) | (value)))
+#define ENET_SET_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) |  (value)))
+#define ENET_CLR_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) & ~(value)))
+#define ENET_TOG_TGSR(base, value) (ENET_WR_TGSR(base, ENET_RD_TGSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TGSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TGSR, field TF0[0] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 0 is clear
+ * - 0b1 - Timer Flag for Channel 0 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF0 field. */
+#define ENET_RD_TGSR_TF0(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF0_MASK) >> ENET_TGSR_TF0_SHIFT)
+#define ENET_BRD_TGSR_TF0(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF0_SHIFT))
+
+/*! @brief Set the TF0 field to a new value. */
+#define ENET_WR_TGSR_TF0(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF2_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF0(value)))
+#define ENET_BWR_TGSR_TF0(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF1[1] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 1 is clear
+ * - 0b1 - Timer Flag for Channel 1 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF1 field. */
+#define ENET_RD_TGSR_TF1(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF1_MASK) >> ENET_TGSR_TF1_SHIFT)
+#define ENET_BRD_TGSR_TF1(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF1_SHIFT))
+
+/*! @brief Set the TF1 field to a new value. */
+#define ENET_WR_TGSR_TF1(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF1_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF2_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF1(value)))
+#define ENET_BWR_TGSR_TF1(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF2[2] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 2 is clear
+ * - 0b1 - Timer Flag for Channel 2 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF2 field. */
+#define ENET_RD_TGSR_TF2(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF2_MASK) >> ENET_TGSR_TF2_SHIFT)
+#define ENET_BRD_TGSR_TF2(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF2_SHIFT))
+
+/*! @brief Set the TF2 field to a new value. */
+#define ENET_WR_TGSR_TF2(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF2_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF3_MASK), ENET_TGSR_TF2(value)))
+#define ENET_BWR_TGSR_TF2(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TGSR, field TF3[3] (W1C)
+ *
+ * Values:
+ * - 0b0 - Timer Flag for Channel 3 is clear
+ * - 0b1 - Timer Flag for Channel 3 is set
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TGSR_TF3 field. */
+#define ENET_RD_TGSR_TF3(base) ((ENET_TGSR_REG(base) & ENET_TGSR_TF3_MASK) >> ENET_TGSR_TF3_SHIFT)
+#define ENET_BRD_TGSR_TF3(base) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF3_SHIFT))
+
+/*! @brief Set the TF3 field to a new value. */
+#define ENET_WR_TGSR_TF3(base, value) (ENET_RMW_TGSR(base, (ENET_TGSR_TF3_MASK | ENET_TGSR_TF0_MASK | ENET_TGSR_TF1_MASK | ENET_TGSR_TF2_MASK), ENET_TGSR_TF3(value)))
+#define ENET_BWR_TGSR_TF3(base, value) (BITBAND_ACCESS32(&ENET_TGSR_REG(base), ENET_TGSR_TF3_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCSR - Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCSR - Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCSR register
+ */
+/*@{*/
+#define ENET_RD_TCSR(base, index) (ENET_TCSR_REG(base, index))
+#define ENET_WR_TCSR(base, index, value) (ENET_TCSR_REG(base, index) = (value))
+#define ENET_RMW_TCSR(base, index, mask, value) (ENET_WR_TCSR(base, index, (ENET_RD_TCSR(base, index) & ~(mask)) | (value)))
+#define ENET_SET_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) |  (value)))
+#define ENET_CLR_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) & ~(value)))
+#define ENET_TOG_TCSR(base, index, value) (ENET_WR_TCSR(base, index, ENET_RD_TCSR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual ENET_TCSR bitfields
+ */
+
+/*!
+ * @name Register ENET_TCSR, field TDRE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - DMA request is disabled
+ * - 0b1 - DMA request is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TDRE field. */
+#define ENET_RD_TCSR_TDRE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TDRE_MASK) >> ENET_TCSR_TDRE_SHIFT)
+#define ENET_BRD_TCSR_TDRE(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TDRE_SHIFT))
+
+/*! @brief Set the TDRE field to a new value. */
+#define ENET_WR_TCSR_TDRE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TDRE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TDRE(value)))
+#define ENET_BWR_TCSR_TDRE(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TDRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TMODE[5:2] (RW)
+ *
+ * Updating the Timer Mode field takes a few cycles to register because it is
+ * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
+ * from the 1588 clock domain. When changing Timer Mode, always disable the
+ * channel and read this register to verify the channel is disabled first.
+ *
+ * Values:
+ * - 0b0000 - Timer Channel is disabled.
+ * - 0b0001 - Timer Channel is configured for Input Capture on rising edge
+ * - 0b0010 - Timer Channel is configured for Input Capture on falling edge
+ * - 0b0011 - Timer Channel is configured for Input Capture on both edges
+ * - 0b0100 - Timer Channel is configured for Output Compare - software only
+ * - 0b0101 - Timer Channel is configured for Output Compare - toggle output on
+ *     compare
+ * - 0b0110 - Timer Channel is configured for Output Compare - clear output on
+ *     compare
+ * - 0b0111 - Timer Channel is configured for Output Compare - set output on
+ *     compare
+ * - 0b1000 - Reserved
+ * - 0b1010 - Timer Channel is configured for Output Compare - clear output on
+ *     compare, set output on overflow
+ * - 0b10x1 - Timer Channel is configured for Output Compare - set output on
+ *     compare, clear output on overflow
+ * - 0b1100 - Reserved
+ * - 0b1110 - Timer Channel is configured for Output Compare - pulse output low
+ *     on compare for one 1588 clock cycle
+ * - 0b1111 - Timer Channel is configured for Output Compare - pulse output high
+ *     on compare for one 1588 clock cycle
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TMODE field. */
+#define ENET_RD_TCSR_TMODE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TMODE_MASK) >> ENET_TCSR_TMODE_SHIFT)
+#define ENET_BRD_TCSR_TMODE(base, index) (ENET_RD_TCSR_TMODE(base, index))
+
+/*! @brief Set the TMODE field to a new value. */
+#define ENET_WR_TCSR_TMODE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TMODE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TMODE(value)))
+#define ENET_BWR_TCSR_TMODE(base, index, value) (ENET_WR_TCSR_TMODE(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TIE[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Interrupt is disabled
+ * - 0b1 - Interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TIE field. */
+#define ENET_RD_TCSR_TIE(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TIE_MASK) >> ENET_TCSR_TIE_SHIFT)
+#define ENET_BRD_TCSR_TIE(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define ENET_WR_TCSR_TIE(base, index, value) (ENET_RMW_TCSR(base, index, (ENET_TCSR_TIE_MASK | ENET_TCSR_TF_MASK), ENET_TCSR_TIE(value)))
+#define ENET_BWR_TCSR_TIE(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register ENET_TCSR, field TF[7] (W1C)
+ *
+ * Sets when input capture or output compare occurs. This flag is double
+ * buffered between the module clock and 1588 clock domains. When this field is 1, it
+ * can be cleared to 0 by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - Input Capture or Output Compare has not occurred
+ * - 0b1 - Input Capture or Output Compare has occurred
+ */
+/*@{*/
+/*! @brief Read current value of the ENET_TCSR_TF field. */
+#define ENET_RD_TCSR_TF(base, index) ((ENET_TCSR_REG(base, index) & ENET_TCSR_TF_MASK) >> ENET_TCSR_TF_SHIFT)
+#define ENET_BRD_TCSR_TF(base, index) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TF_SHIFT))
+
+/*! @brief Set the TF field to a new value. */
+#define ENET_WR_TCSR_TF(base, index, value) (ENET_RMW_TCSR(base, index, ENET_TCSR_TF_MASK, ENET_TCSR_TF(value)))
+#define ENET_BWR_TCSR_TF(base, index, value) (BITBAND_ACCESS32(&ENET_TCSR_REG(base, index), ENET_TCSR_TF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * ENET_TCCR - Timer Compare Capture Register
+ ******************************************************************************/
+
+/*!
+ * @brief ENET_TCCR - Timer Compare Capture Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire ENET_TCCR register
+ */
+/*@{*/
+#define ENET_RD_TCCR(base, index) (ENET_TCCR_REG(base, index))
+#define ENET_WR_TCCR(base, index, value) (ENET_TCCR_REG(base, index) = (value))
+#define ENET_RMW_TCCR(base, index, mask, value) (ENET_WR_TCCR(base, index, (ENET_RD_TCCR(base, index) & ~(mask)) | (value)))
+#define ENET_SET_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) |  (value)))
+#define ENET_CLR_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) & ~(value)))
+#define ENET_TOG_TCCR(base, index, value) (ENET_WR_TCCR(base, index, ENET_RD_TCCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 EWM
+ *
+ * External Watchdog Monitor
+ *
+ * Registers defined in this header file:
+ * - EWM_CTRL - Control Register
+ * - EWM_SERV - Service Register
+ * - EWM_CMPL - Compare Low Register
+ * - EWM_CMPH - Compare High Register
+ */
+
+#define EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
+#define EWM_IDX (0U) /*!< Instance number for EWM. */
+
+/*******************************************************************************
+ * EWM_CTRL - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CTRL - Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
+ * written once after a CPU reset. Modifying these bits more than once, generates
+ * a bus transfer error.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CTRL register
+ */
+/*@{*/
+#define EWM_RD_CTRL(base)        (EWM_CTRL_REG(base))
+#define EWM_WR_CTRL(base, value) (EWM_CTRL_REG(base) = (value))
+#define EWM_RMW_CTRL(base, mask, value) (EWM_WR_CTRL(base, (EWM_RD_CTRL(base) & ~(mask)) | (value)))
+#define EWM_SET_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) |  (value)))
+#define EWM_CLR_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) & ~(value)))
+#define EWM_TOG_CTRL(base, value) (EWM_WR_CTRL(base, EWM_RD_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual EWM_CTRL bitfields
+ */
+
+/*!
+ * @name Register EWM_CTRL, field EWMEN[0] (RW)
+ *
+ * This bit when set, enables the EWM module. This resets the EWM counter to
+ * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
+ * therefore it cannot be enabled until a reset occurs, due to the write-once
+ * nature of this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_EWMEN field. */
+#define EWM_RD_CTRL_EWMEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_EWMEN_MASK) >> EWM_CTRL_EWMEN_SHIFT)
+#define EWM_BRD_CTRL_EWMEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_EWMEN_SHIFT))
+
+/*! @brief Set the EWMEN field to a new value. */
+#define EWM_WR_CTRL_EWMEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_EWMEN_MASK, EWM_CTRL_EWMEN(value)))
+#define EWM_BWR_CTRL_EWMEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_EWMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field ASSIN[1] (RW)
+ *
+ * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
+ * inverts the assert state to a logic one.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_ASSIN field. */
+#define EWM_RD_CTRL_ASSIN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_ASSIN_MASK) >> EWM_CTRL_ASSIN_SHIFT)
+#define EWM_BRD_CTRL_ASSIN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_ASSIN_SHIFT))
+
+/*! @brief Set the ASSIN field to a new value. */
+#define EWM_WR_CTRL_ASSIN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_ASSIN_MASK, EWM_CTRL_ASSIN(value)))
+#define EWM_BWR_CTRL_ASSIN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_ASSIN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field INEN[2] (RW)
+ *
+ * This bit when set, enables the EWM_in port.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_INEN field. */
+#define EWM_RD_CTRL_INEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_INEN_MASK) >> EWM_CTRL_INEN_SHIFT)
+#define EWM_BRD_CTRL_INEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INEN_SHIFT))
+
+/*! @brief Set the INEN field to a new value. */
+#define EWM_WR_CTRL_INEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_INEN_MASK, EWM_CTRL_INEN(value)))
+#define EWM_BWR_CTRL_INEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register EWM_CTRL, field INTEN[3] (RW)
+ *
+ * This bit when set and EWM_out is asserted, an interrupt request is generated.
+ * To de-assert interrupt request, user should clear this bit by writing 0.
+ */
+/*@{*/
+/*! @brief Read current value of the EWM_CTRL_INTEN field. */
+#define EWM_RD_CTRL_INTEN(base) ((EWM_CTRL_REG(base) & EWM_CTRL_INTEN_MASK) >> EWM_CTRL_INTEN_SHIFT)
+#define EWM_BRD_CTRL_INTEN(base) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INTEN_SHIFT))
+
+/*! @brief Set the INTEN field to a new value. */
+#define EWM_WR_CTRL_INTEN(base, value) (EWM_RMW_CTRL(base, EWM_CTRL_INTEN_MASK, EWM_CTRL_INTEN(value)))
+#define EWM_BWR_CTRL_INTEN(base, value) (BITBAND_ACCESS8(&EWM_CTRL_REG(base), EWM_CTRL_INTEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_SERV - Service Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_SERV - Service Register (WORZ)
+ *
+ * Reset value: 0x00U
+ *
+ * The SERV register provides the interface from the CPU to the EWM module. It
+ * is write-only and reads of this register return zero.
+ */
+/*!
+ * @name Constants and macros for entire EWM_SERV register
+ */
+/*@{*/
+#define EWM_RD_SERV(base)        (EWM_SERV_REG(base))
+#define EWM_WR_SERV(base, value) (EWM_SERV_REG(base) = (value))
+#define EWM_RMW_SERV(base, mask, value) (EWM_WR_SERV(base, (EWM_RD_SERV(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_CMPL - Compare Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CMPL - Compare Low Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The CMPL register is reset to zero after a CPU reset. This provides no
+ * minimum time for the CPU to service the EWM counter. This register can be written
+ * only once after a CPU reset. Writing this register more than once generates a
+ * bus transfer error.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CMPL register
+ */
+/*@{*/
+#define EWM_RD_CMPL(base)        (EWM_CMPL_REG(base))
+#define EWM_WR_CMPL(base, value) (EWM_CMPL_REG(base) = (value))
+#define EWM_RMW_CMPL(base, mask, value) (EWM_WR_CMPL(base, (EWM_RD_CMPL(base) & ~(mask)) | (value)))
+#define EWM_SET_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) |  (value)))
+#define EWM_CLR_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) & ~(value)))
+#define EWM_TOG_CMPL(base, value) (EWM_WR_CMPL(base, EWM_RD_CMPL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * EWM_CMPH - Compare High Register
+ ******************************************************************************/
+
+/*!
+ * @brief EWM_CMPH - Compare High Register (RW)
+ *
+ * Reset value: 0xFFU
+ *
+ * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
+ * of 256 clocks time, for the CPU to service the EWM counter. This register can
+ * be written only once after a CPU reset. Writing this register more than once
+ * generates a bus transfer error. The valid values for CMPH are up to 0xFE
+ * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
+ * if EWM counter is greater than CMPH.
+ */
+/*!
+ * @name Constants and macros for entire EWM_CMPH register
+ */
+/*@{*/
+#define EWM_RD_CMPH(base)        (EWM_CMPH_REG(base))
+#define EWM_WR_CMPH(base, value) (EWM_CMPH_REG(base) = (value))
+#define EWM_RMW_CMPH(base, mask, value) (EWM_WR_CMPH(base, (EWM_RD_CMPH(base) & ~(mask)) | (value)))
+#define EWM_SET_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) |  (value)))
+#define EWM_CLR_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) & ~(value)))
+#define EWM_TOG_CMPH(base, value) (EWM_WR_CMPH(base, EWM_RD_CMPH(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FB
+ *
+ * FlexBus external bus interface
+ *
+ * Registers defined in this header file:
+ * - FB_CSAR - Chip Select Address Register
+ * - FB_CSMR - Chip Select Mask Register
+ * - FB_CSCR - Chip Select Control Register
+ * - FB_CSPMCR - Chip Select port Multiplexing Control Register
+ */
+
+#define FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
+#define FB_IDX (0U) /*!< Instance number for FB. */
+
+/*******************************************************************************
+ * FB_CSAR - Chip Select Address Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSAR - Chip Select Address Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the associated chip-select's base address.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSAR register
+ */
+/*@{*/
+#define FB_RD_CSAR(base, index)  (FB_CSAR_REG(base, index))
+#define FB_WR_CSAR(base, index, value) (FB_CSAR_REG(base, index) = (value))
+#define FB_RMW_CSAR(base, index, mask, value) (FB_WR_CSAR(base, index, (FB_RD_CSAR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) |  (value)))
+#define FB_CLR_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) & ~(value)))
+#define FB_TOG_CSAR(base, index, value) (FB_WR_CSAR(base, index, FB_RD_CSAR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSAR bitfields
+ */
+
+/*!
+ * @name Register FB_CSAR, field BA[31:16] (RW)
+ *
+ * Defines the base address for memory dedicated to the associated chip-select.
+ * BA is compared to bits 31-16 on the internal address bus to determine if the
+ * associated chip-select's memory is being accessed. Because the FlexBus module
+ * is one of the slaves connected to the crossbar switch, it is only accessible
+ * within a certain memory range. See the chip memory map for the applicable
+ * FlexBus "expansion" address range for which the chip-selects can be active. Set the
+ * CSARn and CSMRn registers appropriately before accessing this region.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSAR_BA field. */
+#define FB_RD_CSAR_BA(base, index) ((FB_CSAR_REG(base, index) & FB_CSAR_BA_MASK) >> FB_CSAR_BA_SHIFT)
+#define FB_BRD_CSAR_BA(base, index) (FB_RD_CSAR_BA(base, index))
+
+/*! @brief Set the BA field to a new value. */
+#define FB_WR_CSAR_BA(base, index, value) (FB_RMW_CSAR(base, index, FB_CSAR_BA_MASK, FB_CSAR_BA(value)))
+#define FB_BWR_CSAR_BA(base, index, value) (FB_WR_CSAR_BA(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSMR - Chip Select Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSMR - Chip Select Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies the address mask and allowable access types for the associated
+ * chip-select.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSMR register
+ */
+/*@{*/
+#define FB_RD_CSMR(base, index)  (FB_CSMR_REG(base, index))
+#define FB_WR_CSMR(base, index, value) (FB_CSMR_REG(base, index) = (value))
+#define FB_RMW_CSMR(base, index, mask, value) (FB_WR_CSMR(base, index, (FB_RD_CSMR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) |  (value)))
+#define FB_CLR_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) & ~(value)))
+#define FB_TOG_CSMR(base, index, value) (FB_WR_CSMR(base, index, FB_RD_CSMR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSMR bitfields
+ */
+
+/*!
+ * @name Register FB_CSMR, field V[0] (RW)
+ *
+ * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
+ * Programmed chip-selects do not assert until the V bit is 1b (except for
+ * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
+ * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
+ * select initialization sequence to allow other chip selects to function as
+ * programmed.
+ *
+ * Values:
+ * - 0b0 - Chip-select is invalid.
+ * - 0b1 - Chip-select is valid.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_V field. */
+#define FB_RD_CSMR_V(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_V_MASK) >> FB_CSMR_V_SHIFT)
+#define FB_BRD_CSMR_V(base, index) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_V_SHIFT))
+
+/*! @brief Set the V field to a new value. */
+#define FB_WR_CSMR_V(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_V_MASK, FB_CSMR_V(value)))
+#define FB_BWR_CSMR_V(base, index, value) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_V_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSMR, field WP[8] (RW)
+ *
+ * Controls write accesses to the address range in the corresponding CSAR.
+ *
+ * Values:
+ * - 0b0 - Write accesses are allowed.
+ * - 0b1 - Write accesses are not allowed. Attempting to write to the range of
+ *     addresses for which the WP bit is set results in a bus error termination of
+ *     the internal cycle and no external cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_WP field. */
+#define FB_RD_CSMR_WP(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_WP_MASK) >> FB_CSMR_WP_SHIFT)
+#define FB_BRD_CSMR_WP(base, index) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_WP_SHIFT))
+
+/*! @brief Set the WP field to a new value. */
+#define FB_WR_CSMR_WP(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_WP_MASK, FB_CSMR_WP(value)))
+#define FB_BWR_CSMR_WP(base, index, value) (BITBAND_ACCESS32(&FB_CSMR_REG(base, index), FB_CSMR_WP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSMR, field BAM[31:16] (RW)
+ *
+ * Defines the associated chip-select's block size by masking address bits.
+ *
+ * Values:
+ * - 0b0000000000000000 - The corresponding address bit in CSAR is used in the
+ *     chip-select decode.
+ * - 0b0000000000000001 - The corresponding address bit in CSAR is a don't care
+ *     in the chip-select decode.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSMR_BAM field. */
+#define FB_RD_CSMR_BAM(base, index) ((FB_CSMR_REG(base, index) & FB_CSMR_BAM_MASK) >> FB_CSMR_BAM_SHIFT)
+#define FB_BRD_CSMR_BAM(base, index) (FB_RD_CSMR_BAM(base, index))
+
+/*! @brief Set the BAM field to a new value. */
+#define FB_WR_CSMR_BAM(base, index, value) (FB_RMW_CSMR(base, index, FB_CSMR_BAM_MASK, FB_CSMR_BAM(value)))
+#define FB_BWR_CSMR_BAM(base, index, value) (FB_WR_CSMR_BAM(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSCR - Chip Select Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSCR - Chip Select Control Register (RW)
+ *
+ * Reset value: 0x003FFC00U
+ *
+ * Controls the auto-acknowledge, address setup and hold times, port size, burst
+ * capability, and number of wait states for the associated chip select. To
+ * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
+ * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
+ * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
+ * particular chip for information on the exact CSCR0 reset value.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSCR register
+ */
+/*@{*/
+#define FB_RD_CSCR(base, index)  (FB_CSCR_REG(base, index))
+#define FB_WR_CSCR(base, index, value) (FB_CSCR_REG(base, index) = (value))
+#define FB_RMW_CSCR(base, index, mask, value) (FB_WR_CSCR(base, index, (FB_RD_CSCR(base, index) & ~(mask)) | (value)))
+#define FB_SET_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) |  (value)))
+#define FB_CLR_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) & ~(value)))
+#define FB_TOG_CSCR(base, index, value) (FB_WR_CSCR(base, index, FB_RD_CSCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSCR, field BSTW[3] (RW)
+ *
+ * Specifies whether burst writes are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0b0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst writes. For example, a 32-bit write to an
+ *     8-bit port takes four byte writes.
+ * - 0b1 - Enabled. Enables burst write of data larger than the specified port
+ *     size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to
+ *     8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BSTW field. */
+#define FB_RD_CSCR_BSTW(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BSTW_MASK) >> FB_CSCR_BSTW_SHIFT)
+#define FB_BRD_CSCR_BSTW(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTW_SHIFT))
+
+/*! @brief Set the BSTW field to a new value. */
+#define FB_WR_CSCR_BSTW(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BSTW_MASK, FB_CSCR_BSTW(value)))
+#define FB_BWR_CSCR_BSTW(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BSTR[4] (RW)
+ *
+ * Specifies whether burst reads are enabled for memory associated with each
+ * chip select.
+ *
+ * Values:
+ * - 0b0 - Disabled. Data exceeding the specified port size is broken into
+ *     individual, port-sized, non-burst reads. For example, a 32-bit read from an
+ *     8-bit port is broken into four 8-bit reads.
+ * - 0b1 - Enabled. Enables data burst reads larger than the specified port
+ *     size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
+ *     ports, and line reads from 8-, 16-, and 32-bit ports.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BSTR field. */
+#define FB_RD_CSCR_BSTR(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BSTR_MASK) >> FB_CSCR_BSTR_SHIFT)
+#define FB_BRD_CSCR_BSTR(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTR_SHIFT))
+
+/*! @brief Set the BSTR field to a new value. */
+#define FB_WR_CSCR_BSTR(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BSTR_MASK, FB_CSCR_BSTR(value)))
+#define FB_BWR_CSCR_BSTR(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BSTR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BEM[5] (RW)
+ *
+ * Specifies whether the corresponding FB_BE is asserted for read accesses.
+ * Certain memories have byte enables that must be asserted during reads and writes.
+ * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
+ * of byte enable support for these SRAMs.
+ *
+ * Values:
+ * - 0b0 - FB_BE is asserted for data write only.
+ * - 0b1 - FB_BE is asserted for data read and write accesses.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BEM field. */
+#define FB_RD_CSCR_BEM(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BEM_MASK) >> FB_CSCR_BEM_SHIFT)
+#define FB_BRD_CSCR_BEM(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BEM_SHIFT))
+
+/*! @brief Set the BEM field to a new value. */
+#define FB_WR_CSCR_BEM(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BEM_MASK, FB_CSCR_BEM(value)))
+#define FB_BWR_CSCR_BEM(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BEM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field PS[7:6] (RW)
+ *
+ * Specifies the data port width of the associated chip-select, and determines
+ * where data is driven during write cycles and where data is sampled during read
+ * cycles.
+ *
+ * Values:
+ * - 0b00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
+ * - 0b01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24]
+ *     when BLS is 0b, or FB_D[7:0] when BLS is 1b.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_PS field. */
+#define FB_RD_CSCR_PS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_PS_MASK) >> FB_CSCR_PS_SHIFT)
+#define FB_BRD_CSCR_PS(base, index) (FB_RD_CSCR_PS(base, index))
+
+/*! @brief Set the PS field to a new value. */
+#define FB_WR_CSCR_PS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_PS_MASK, FB_CSCR_PS(value)))
+#define FB_BWR_CSCR_PS(base, index, value) (FB_WR_CSCR_PS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field AA[8] (RW)
+ *
+ * Asserts the internal transfer acknowledge for accesses specified by the
+ * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
+ * asserts an external FB_TA before the wait-state countdown asserts the
+ * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
+ * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
+ *
+ * Values:
+ * - 0b0 - Disabled. No internal transfer acknowledge is asserted and the cycle
+ *     is terminated externally.
+ * - 0b1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_AA field. */
+#define FB_RD_CSCR_AA(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_AA_MASK) >> FB_CSCR_AA_SHIFT)
+#define FB_BRD_CSCR_AA(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_AA_SHIFT))
+
+/*! @brief Set the AA field to a new value. */
+#define FB_WR_CSCR_AA(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_AA_MASK, FB_CSCR_AA(value)))
+#define FB_BWR_CSCR_AA(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_AA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field BLS[9] (RW)
+ *
+ * Specifies if data on FB_AD appears left-aligned or right-aligned during the
+ * data phase of a FlexBus access.
+ *
+ * Values:
+ * - 0b0 - Not shifted. Data is left-aligned on FB_AD.
+ * - 0b1 - Shifted. Data is right-aligned on FB_AD.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_BLS field. */
+#define FB_RD_CSCR_BLS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_BLS_MASK) >> FB_CSCR_BLS_SHIFT)
+#define FB_BRD_CSCR_BLS(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BLS_SHIFT))
+
+/*! @brief Set the BLS field to a new value. */
+#define FB_WR_CSCR_BLS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_BLS_MASK, FB_CSCR_BLS(value)))
+#define FB_BWR_CSCR_BLS(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_BLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field WS[15:10] (RW)
+ *
+ * Specifies the number of wait states inserted after FlexBus asserts the
+ * associated chip-select and before an internal transfer acknowledge is generated (WS
+ * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_WS field. */
+#define FB_RD_CSCR_WS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_WS_MASK) >> FB_CSCR_WS_SHIFT)
+#define FB_BRD_CSCR_WS(base, index) (FB_RD_CSCR_WS(base, index))
+
+/*! @brief Set the WS field to a new value. */
+#define FB_WR_CSCR_WS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_WS_MASK, FB_CSCR_WS(value)))
+#define FB_BWR_CSCR_WS(base, index, value) (FB_WR_CSCR_WS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field WRAH[17:16] (RW)
+ *
+ * Controls the address, data, and attribute hold time after the termination of
+ * a write cycle that hits in the associated chip-select's address space. The
+ * hold time applies only at the end of a transfer. Therefore, during a burst
+ * transfer or a transfer to a port size smaller than the transfer size, the hold time
+ * is only added after the last bus cycle.
+ *
+ * Values:
+ * - 0b00 - 1 cycle (default for all but FB_CS0 )
+ * - 0b01 - 2 cycles
+ * - 0b10 - 3 cycles
+ * - 0b11 - 4 cycles (default for FB_CS0 )
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_WRAH field. */
+#define FB_RD_CSCR_WRAH(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_WRAH_MASK) >> FB_CSCR_WRAH_SHIFT)
+#define FB_BRD_CSCR_WRAH(base, index) (FB_RD_CSCR_WRAH(base, index))
+
+/*! @brief Set the WRAH field to a new value. */
+#define FB_WR_CSCR_WRAH(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_WRAH_MASK, FB_CSCR_WRAH(value)))
+#define FB_BWR_CSCR_WRAH(base, index, value) (FB_WR_CSCR_WRAH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field RDAH[19:18] (RW)
+ *
+ * Controls the address and attribute hold time after the termination during a
+ * read cycle that hits in the associated chip-select's address space. The hold
+ * time applies only at the end of a transfer. Therefore, during a burst transfer
+ * or a transfer to a port size smaller than the transfer size, the hold time is
+ * only added after the last bus cycle. The number of cycles the address and
+ * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
+ *
+ * Values:
+ * - 0b00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
+ * - 0b01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
+ * - 0b10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
+ * - 0b11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_RDAH field. */
+#define FB_RD_CSCR_RDAH(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_RDAH_MASK) >> FB_CSCR_RDAH_SHIFT)
+#define FB_BRD_CSCR_RDAH(base, index) (FB_RD_CSCR_RDAH(base, index))
+
+/*! @brief Set the RDAH field to a new value. */
+#define FB_WR_CSCR_RDAH(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_RDAH_MASK, FB_CSCR_RDAH(value)))
+#define FB_BWR_CSCR_RDAH(base, index, value) (FB_WR_CSCR_RDAH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field ASET[21:20] (RW)
+ *
+ * Controls when the chip-select is asserted with respect to assertion of a
+ * valid address and attributes.
+ *
+ * Values:
+ * - 0b00 - Assert FB_CSn on the first rising clock edge after the address is
+ *     asserted (default for all but FB_CS0 ).
+ * - 0b01 - Assert FB_CSn on the second rising clock edge after the address is
+ *     asserted.
+ * - 0b10 - Assert FB_CSn on the third rising clock edge after the address is
+ *     asserted.
+ * - 0b11 - Assert FB_CSn on the fourth rising clock edge after the address is
+ *     asserted (default for FB_CS0 ).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_ASET field. */
+#define FB_RD_CSCR_ASET(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_ASET_MASK) >> FB_CSCR_ASET_SHIFT)
+#define FB_BRD_CSCR_ASET(base, index) (FB_RD_CSCR_ASET(base, index))
+
+/*! @brief Set the ASET field to a new value. */
+#define FB_WR_CSCR_ASET(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_ASET_MASK, FB_CSCR_ASET(value)))
+#define FB_BWR_CSCR_ASET(base, index, value) (FB_WR_CSCR_ASET(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field EXTS[22] (RW)
+ *
+ * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
+ * /FB_ALE is asserted.
+ *
+ * Values:
+ * - 0b0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
+ * - 0b1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive
+ *     clock edge after FB_CSn asserts.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_EXTS field. */
+#define FB_RD_CSCR_EXTS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_EXTS_MASK) >> FB_CSCR_EXTS_SHIFT)
+#define FB_BRD_CSCR_EXTS(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_EXTS_SHIFT))
+
+/*! @brief Set the EXTS field to a new value. */
+#define FB_WR_CSCR_EXTS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_EXTS_MASK, FB_CSCR_EXTS(value)))
+#define FB_BWR_CSCR_EXTS(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_EXTS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field SWSEN[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Disabled. A number of wait states (specified by WS) are inserted
+ *     before an internal transfer acknowledge is generated for all transfers.
+ * - 0b1 - Enabled. A number of wait states (specified by SWS) are inserted
+ *     before an internal transfer acknowledge is generated for burst transfer
+ *     secondary terminations.
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_SWSEN field. */
+#define FB_RD_CSCR_SWSEN(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_SWSEN_MASK) >> FB_CSCR_SWSEN_SHIFT)
+#define FB_BRD_CSCR_SWSEN(base, index) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_SWSEN_SHIFT))
+
+/*! @brief Set the SWSEN field to a new value. */
+#define FB_WR_CSCR_SWSEN(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_SWSEN_MASK, FB_CSCR_SWSEN(value)))
+#define FB_BWR_CSCR_SWSEN(base, index, value) (BITBAND_ACCESS32(&FB_CSCR_REG(base, index), FB_CSCR_SWSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSCR, field SWS[31:26] (RW)
+ *
+ * Used only when the SWSEN bit is 1b. Specifies the number of wait states
+ * inserted before an internal transfer acknowledge is generated for a burst transfer
+ * (except for the first termination, which is controlled by WS).
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSCR_SWS field. */
+#define FB_RD_CSCR_SWS(base, index) ((FB_CSCR_REG(base, index) & FB_CSCR_SWS_MASK) >> FB_CSCR_SWS_SHIFT)
+#define FB_BRD_CSCR_SWS(base, index) (FB_RD_CSCR_SWS(base, index))
+
+/*! @brief Set the SWS field to a new value. */
+#define FB_WR_CSCR_SWS(base, index, value) (FB_RMW_CSCR(base, index, FB_CSCR_SWS_MASK, FB_CSCR_SWS(value)))
+#define FB_BWR_CSCR_SWS(base, index, value) (FB_WR_CSCR_SWS(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FB_CSPMCR - Chip Select port Multiplexing Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
+ * do any of the following: Write to a reserved address Write to a reserved
+ * field in this register, or Access this register using a size other than 32 bits.
+ */
+/*!
+ * @name Constants and macros for entire FB_CSPMCR register
+ */
+/*@{*/
+#define FB_RD_CSPMCR(base)       (FB_CSPMCR_REG(base))
+#define FB_WR_CSPMCR(base, value) (FB_CSPMCR_REG(base) = (value))
+#define FB_RMW_CSPMCR(base, mask, value) (FB_WR_CSPMCR(base, (FB_RD_CSPMCR(base) & ~(mask)) | (value)))
+#define FB_SET_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) |  (value)))
+#define FB_CLR_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) & ~(value)))
+#define FB_TOG_CSPMCR(base, value) (FB_WR_CSPMCR(base, FB_RD_CSPMCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FB_CSPMCR bitfields
+ */
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
+ *
+ * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
+ * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
+ * bus hangs during a transfer.
+ *
+ * Values:
+ * - 0b0000 - FB_TA
+ * - 0b0001 - FB_CS3 . You must also write 1b to CSCR[AA].
+ * - 0b0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
+#define FB_RD_CSPMCR_GROUP5(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP5_MASK) >> FB_CSPMCR_GROUP5_SHIFT)
+#define FB_BRD_CSPMCR_GROUP5(base) (FB_RD_CSPMCR_GROUP5(base))
+
+/*! @brief Set the GROUP5 field to a new value. */
+#define FB_WR_CSPMCR_GROUP5(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP5_MASK, FB_CSPMCR_GROUP5(value)))
+#define FB_BWR_CSPMCR_GROUP5(base, value) (FB_WR_CSPMCR_GROUP5(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
+ *
+ * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_TBST
+ * - 0b0001 - FB_CS2
+ * - 0b0010 - FB_BE_15_8
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
+#define FB_RD_CSPMCR_GROUP4(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP4_MASK) >> FB_CSPMCR_GROUP4_SHIFT)
+#define FB_BRD_CSPMCR_GROUP4(base) (FB_RD_CSPMCR_GROUP4(base))
+
+/*! @brief Set the GROUP4 field to a new value. */
+#define FB_WR_CSPMCR_GROUP4(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP4_MASK, FB_CSPMCR_GROUP4(value)))
+#define FB_BWR_CSPMCR_GROUP4(base, value) (FB_WR_CSPMCR_GROUP4(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
+ *
+ * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_CS5
+ * - 0b0001 - FB_TSIZ1
+ * - 0b0010 - FB_BE_23_16
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
+#define FB_RD_CSPMCR_GROUP3(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP3_MASK) >> FB_CSPMCR_GROUP3_SHIFT)
+#define FB_BRD_CSPMCR_GROUP3(base) (FB_RD_CSPMCR_GROUP3(base))
+
+/*! @brief Set the GROUP3 field to a new value. */
+#define FB_WR_CSPMCR_GROUP3(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP3_MASK, FB_CSPMCR_GROUP3(value)))
+#define FB_BWR_CSPMCR_GROUP3(base, value) (FB_WR_CSPMCR_GROUP3(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
+ *
+ * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
+ *
+ * Values:
+ * - 0b0000 - FB_CS4
+ * - 0b0001 - FB_TSIZ0
+ * - 0b0010 - FB_BE_31_24
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
+#define FB_RD_CSPMCR_GROUP2(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP2_MASK) >> FB_CSPMCR_GROUP2_SHIFT)
+#define FB_BRD_CSPMCR_GROUP2(base) (FB_RD_CSPMCR_GROUP2(base))
+
+/*! @brief Set the GROUP2 field to a new value. */
+#define FB_WR_CSPMCR_GROUP2(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP2_MASK, FB_CSPMCR_GROUP2(value)))
+#define FB_BWR_CSPMCR_GROUP2(base, value) (FB_WR_CSPMCR_GROUP2(base, value))
+/*@}*/
+
+/*!
+ * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
+ *
+ * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
+ *
+ * Values:
+ * - 0b0000 - FB_ALE
+ * - 0b0001 - FB_CS1
+ * - 0b0010 - FB_TS
+ */
+/*@{*/
+/*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
+#define FB_RD_CSPMCR_GROUP1(base) ((FB_CSPMCR_REG(base) & FB_CSPMCR_GROUP1_MASK) >> FB_CSPMCR_GROUP1_SHIFT)
+#define FB_BRD_CSPMCR_GROUP1(base) (FB_RD_CSPMCR_GROUP1(base))
+
+/*! @brief Set the GROUP1 field to a new value. */
+#define FB_WR_CSPMCR_GROUP1(base, value) (FB_RMW_CSPMCR(base, FB_CSPMCR_GROUP1_MASK, FB_CSPMCR_GROUP1(value)))
+#define FB_BWR_CSPMCR_GROUP1(base, value) (FB_WR_CSPMCR_GROUP1(base, value))
+/*@}*/
+
+/*
+ * MK64F12 FMC
+ *
+ * Flash Memory Controller
+ *
+ * Registers defined in this header file:
+ * - FMC_PFAPR - Flash Access Protection Register
+ * - FMC_PFB0CR - Flash Bank 0 Control Register
+ * - FMC_PFB1CR - Flash Bank 1 Control Register
+ * - FMC_TAGVDW0S - Cache Tag Storage
+ * - FMC_TAGVDW1S - Cache Tag Storage
+ * - FMC_TAGVDW2S - Cache Tag Storage
+ * - FMC_TAGVDW3S - Cache Tag Storage
+ * - FMC_DATA_U - Cache Data Storage (upper word)
+ * - FMC_DATA_L - Cache Data Storage (lower word)
+ */
+
+#define FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */
+#define FMC_IDX (0U) /*!< Instance number for FMC. */
+
+/*******************************************************************************
+ * FMC_PFAPR - Flash Access Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFAPR - Flash Access Protection Register (RW)
+ *
+ * Reset value: 0x00F8003FU
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFAPR register
+ */
+/*@{*/
+#define FMC_RD_PFAPR(base)       (FMC_PFAPR_REG(base))
+#define FMC_WR_PFAPR(base, value) (FMC_PFAPR_REG(base) = (value))
+#define FMC_RMW_PFAPR(base, mask, value) (FMC_WR_PFAPR(base, (FMC_RD_PFAPR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) |  (value)))
+#define FMC_CLR_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) & ~(value)))
+#define FMC_TOG_PFAPR(base, value) (FMC_WR_PFAPR(base, FMC_RD_PFAPR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFAPR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFAPR, field M0AP[1:0] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M0AP field. */
+#define FMC_RD_PFAPR_M0AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M0AP_MASK) >> FMC_PFAPR_M0AP_SHIFT)
+#define FMC_BRD_PFAPR_M0AP(base) (FMC_RD_PFAPR_M0AP(base))
+
+/*! @brief Set the M0AP field to a new value. */
+#define FMC_WR_PFAPR_M0AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M0AP_MASK, FMC_PFAPR_M0AP(value)))
+#define FMC_BWR_PFAPR_M0AP(base, value) (FMC_WR_PFAPR_M0AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M1AP[3:2] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M1AP field. */
+#define FMC_RD_PFAPR_M1AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M1AP_MASK) >> FMC_PFAPR_M1AP_SHIFT)
+#define FMC_BRD_PFAPR_M1AP(base) (FMC_RD_PFAPR_M1AP(base))
+
+/*! @brief Set the M1AP field to a new value. */
+#define FMC_WR_PFAPR_M1AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M1AP_MASK, FMC_PFAPR_M1AP(value)))
+#define FMC_BWR_PFAPR_M1AP(base, value) (FMC_WR_PFAPR_M1AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M2AP[5:4] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M2AP field. */
+#define FMC_RD_PFAPR_M2AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M2AP_MASK) >> FMC_PFAPR_M2AP_SHIFT)
+#define FMC_BRD_PFAPR_M2AP(base) (FMC_RD_PFAPR_M2AP(base))
+
+/*! @brief Set the M2AP field to a new value. */
+#define FMC_WR_PFAPR_M2AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M2AP_MASK, FMC_PFAPR_M2AP(value)))
+#define FMC_BWR_PFAPR_M2AP(base, value) (FMC_WR_PFAPR_M2AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M3AP[7:6] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M3AP field. */
+#define FMC_RD_PFAPR_M3AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M3AP_MASK) >> FMC_PFAPR_M3AP_SHIFT)
+#define FMC_BRD_PFAPR_M3AP(base) (FMC_RD_PFAPR_M3AP(base))
+
+/*! @brief Set the M3AP field to a new value. */
+#define FMC_WR_PFAPR_M3AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M3AP_MASK, FMC_PFAPR_M3AP(value)))
+#define FMC_BWR_PFAPR_M3AP(base, value) (FMC_WR_PFAPR_M3AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M4AP[9:8] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M4AP field. */
+#define FMC_RD_PFAPR_M4AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M4AP_MASK) >> FMC_PFAPR_M4AP_SHIFT)
+#define FMC_BRD_PFAPR_M4AP(base) (FMC_RD_PFAPR_M4AP(base))
+
+/*! @brief Set the M4AP field to a new value. */
+#define FMC_WR_PFAPR_M4AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M4AP_MASK, FMC_PFAPR_M4AP(value)))
+#define FMC_BWR_PFAPR_M4AP(base, value) (FMC_WR_PFAPR_M4AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M5AP[11:10] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M5AP field. */
+#define FMC_RD_PFAPR_M5AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M5AP_MASK) >> FMC_PFAPR_M5AP_SHIFT)
+#define FMC_BRD_PFAPR_M5AP(base) (FMC_RD_PFAPR_M5AP(base))
+
+/*! @brief Set the M5AP field to a new value. */
+#define FMC_WR_PFAPR_M5AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M5AP_MASK, FMC_PFAPR_M5AP(value)))
+#define FMC_BWR_PFAPR_M5AP(base, value) (FMC_WR_PFAPR_M5AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M6AP[13:12] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master
+ * - 0b01 - Only read accesses may be performed by this master
+ * - 0b10 - Only write accesses may be performed by this master
+ * - 0b11 - Both read and write accesses may be performed by this master
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M6AP field. */
+#define FMC_RD_PFAPR_M6AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M6AP_MASK) >> FMC_PFAPR_M6AP_SHIFT)
+#define FMC_BRD_PFAPR_M6AP(base) (FMC_RD_PFAPR_M6AP(base))
+
+/*! @brief Set the M6AP field to a new value. */
+#define FMC_WR_PFAPR_M6AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M6AP_MASK, FMC_PFAPR_M6AP(value)))
+#define FMC_BWR_PFAPR_M6AP(base, value) (FMC_WR_PFAPR_M6AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M7AP[15:14] (RW)
+ *
+ * This field controls whether read and write access to the flash are allowed
+ * based on the logical master number of the requesting crossbar switch master.
+ *
+ * Values:
+ * - 0b00 - No access may be performed by this master.
+ * - 0b01 - Only read accesses may be performed by this master.
+ * - 0b10 - Only write accesses may be performed by this master.
+ * - 0b11 - Both read and write accesses may be performed by this master.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M7AP field. */
+#define FMC_RD_PFAPR_M7AP(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M7AP_MASK) >> FMC_PFAPR_M7AP_SHIFT)
+#define FMC_BRD_PFAPR_M7AP(base) (FMC_RD_PFAPR_M7AP(base))
+
+/*! @brief Set the M7AP field to a new value. */
+#define FMC_WR_PFAPR_M7AP(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M7AP_MASK, FMC_PFAPR_M7AP(value)))
+#define FMC_BWR_PFAPR_M7AP(base, value) (FMC_WR_PFAPR_M7AP(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M0PFD[16] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M0PFD field. */
+#define FMC_RD_PFAPR_M0PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M0PFD_MASK) >> FMC_PFAPR_M0PFD_SHIFT)
+#define FMC_BRD_PFAPR_M0PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M0PFD_SHIFT))
+
+/*! @brief Set the M0PFD field to a new value. */
+#define FMC_WR_PFAPR_M0PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M0PFD_MASK, FMC_PFAPR_M0PFD(value)))
+#define FMC_BWR_PFAPR_M0PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M0PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M1PFD[17] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M1PFD field. */
+#define FMC_RD_PFAPR_M1PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M1PFD_MASK) >> FMC_PFAPR_M1PFD_SHIFT)
+#define FMC_BRD_PFAPR_M1PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M1PFD_SHIFT))
+
+/*! @brief Set the M1PFD field to a new value. */
+#define FMC_WR_PFAPR_M1PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M1PFD_MASK, FMC_PFAPR_M1PFD(value)))
+#define FMC_BWR_PFAPR_M1PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M1PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M2PFD[18] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M2PFD field. */
+#define FMC_RD_PFAPR_M2PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M2PFD_MASK) >> FMC_PFAPR_M2PFD_SHIFT)
+#define FMC_BRD_PFAPR_M2PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M2PFD_SHIFT))
+
+/*! @brief Set the M2PFD field to a new value. */
+#define FMC_WR_PFAPR_M2PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M2PFD_MASK, FMC_PFAPR_M2PFD(value)))
+#define FMC_BWR_PFAPR_M2PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M2PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M3PFD[19] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M3PFD field. */
+#define FMC_RD_PFAPR_M3PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M3PFD_MASK) >> FMC_PFAPR_M3PFD_SHIFT)
+#define FMC_BRD_PFAPR_M3PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M3PFD_SHIFT))
+
+/*! @brief Set the M3PFD field to a new value. */
+#define FMC_WR_PFAPR_M3PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M3PFD_MASK, FMC_PFAPR_M3PFD(value)))
+#define FMC_BWR_PFAPR_M3PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M3PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M4PFD[20] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M4PFD field. */
+#define FMC_RD_PFAPR_M4PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M4PFD_MASK) >> FMC_PFAPR_M4PFD_SHIFT)
+#define FMC_BRD_PFAPR_M4PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M4PFD_SHIFT))
+
+/*! @brief Set the M4PFD field to a new value. */
+#define FMC_WR_PFAPR_M4PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M4PFD_MASK, FMC_PFAPR_M4PFD(value)))
+#define FMC_BWR_PFAPR_M4PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M4PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M5PFD[21] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M5PFD field. */
+#define FMC_RD_PFAPR_M5PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M5PFD_MASK) >> FMC_PFAPR_M5PFD_SHIFT)
+#define FMC_BRD_PFAPR_M5PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M5PFD_SHIFT))
+
+/*! @brief Set the M5PFD field to a new value. */
+#define FMC_WR_PFAPR_M5PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M5PFD_MASK, FMC_PFAPR_M5PFD(value)))
+#define FMC_BWR_PFAPR_M5PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M5PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M6PFD[22] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M6PFD field. */
+#define FMC_RD_PFAPR_M6PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M6PFD_MASK) >> FMC_PFAPR_M6PFD_SHIFT)
+#define FMC_BRD_PFAPR_M6PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M6PFD_SHIFT))
+
+/*! @brief Set the M6PFD field to a new value. */
+#define FMC_WR_PFAPR_M6PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M6PFD_MASK, FMC_PFAPR_M6PFD(value)))
+#define FMC_BWR_PFAPR_M6PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M6PFD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFAPR, field M7PFD[23] (RW)
+ *
+ * These bits control whether prefetching is enabled based on the logical number
+ * of the requesting crossbar switch master. This field is further qualified by
+ * the PFBnCR[BxDPE,BxIPE] bits.
+ *
+ * Values:
+ * - 0b0 - Prefetching for this master is enabled.
+ * - 0b1 - Prefetching for this master is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFAPR_M7PFD field. */
+#define FMC_RD_PFAPR_M7PFD(base) ((FMC_PFAPR_REG(base) & FMC_PFAPR_M7PFD_MASK) >> FMC_PFAPR_M7PFD_SHIFT)
+#define FMC_BRD_PFAPR_M7PFD(base) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M7PFD_SHIFT))
+
+/*! @brief Set the M7PFD field to a new value. */
+#define FMC_WR_PFAPR_M7PFD(base, value) (FMC_RMW_PFAPR(base, FMC_PFAPR_M7PFD_MASK, FMC_PFAPR_M7PFD(value)))
+#define FMC_BWR_PFAPR_M7PFD(base, value) (BITBAND_ACCESS32(&FMC_PFAPR_REG(base), FMC_PFAPR_M7PFD_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_PFB0CR - Flash Bank 0 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFB0CR - Flash Bank 0 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFB0CR register
+ */
+/*@{*/
+#define FMC_RD_PFB0CR(base)      (FMC_PFB0CR_REG(base))
+#define FMC_WR_PFB0CR(base, value) (FMC_PFB0CR_REG(base) = (value))
+#define FMC_RMW_PFB0CR(base, mask, value) (FMC_WR_PFB0CR(base, (FMC_RD_PFB0CR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) |  (value)))
+#define FMC_CLR_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) & ~(value)))
+#define FMC_TOG_PFB0CR(base, value) (FMC_WR_PFB0CR(base, FMC_RD_PFB0CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFB0CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB0CR, field B0SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry page buffer is enabled in response
+ * to flash read accesses. Its operation is independent from bank 1's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0b0 - Single entry buffer is disabled.
+ * - 0b1 - Single entry buffer is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */
+#define FMC_RD_PFB0CR_B0SEBE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0SEBE_MASK) >> FMC_PFB0CR_B0SEBE_SHIFT)
+#define FMC_BRD_PFB0CR_B0SEBE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0SEBE_SHIFT))
+
+/*! @brief Set the B0SEBE field to a new value. */
+#define FMC_WR_PFB0CR_B0SEBE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0SEBE_MASK, FMC_PFB0CR_B0SEBE(value)))
+#define FMC_BWR_PFB0CR_B0SEBE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0SEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to instruction fetches.
+ * - 0b1 - Enable prefetches in response to instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */
+#define FMC_RD_PFB0CR_B0IPE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0IPE_MASK) >> FMC_PFB0CR_B0IPE_SHIFT)
+#define FMC_BRD_PFB0CR_B0IPE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0IPE_SHIFT))
+
+/*! @brief Set the B0IPE field to a new value. */
+#define FMC_WR_PFB0CR_B0IPE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0IPE_MASK, FMC_PFB0CR_B0IPE(value)))
+#define FMC_BWR_PFB0CR_B0IPE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0IPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to data references.
+ * - 0b1 - Enable prefetches in response to data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */
+#define FMC_RD_PFB0CR_B0DPE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0DPE_MASK) >> FMC_PFB0CR_B0DPE_SHIFT)
+#define FMC_BRD_PFB0CR_B0DPE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DPE_SHIFT))
+
+/*! @brief Set the B0DPE field to a new value. */
+#define FMC_WR_PFB0CR_B0DPE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0DPE_MASK, FMC_PFB0CR_B0DPE(value)))
+#define FMC_BWR_PFB0CR_B0DPE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache instruction fetches.
+ * - 0b1 - Cache instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */
+#define FMC_RD_PFB0CR_B0ICE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0ICE_MASK) >> FMC_PFB0CR_B0ICE_SHIFT)
+#define FMC_BRD_PFB0CR_B0ICE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0ICE_SHIFT))
+
+/*! @brief Set the B0ICE field to a new value. */
+#define FMC_WR_PFB0CR_B0ICE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0ICE_MASK, FMC_PFB0CR_B0ICE(value)))
+#define FMC_BWR_PFB0CR_B0ICE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0ICE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache data references.
+ * - 0b1 - Cache data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */
+#define FMC_RD_PFB0CR_B0DCE(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0DCE_MASK) >> FMC_PFB0CR_B0DCE_SHIFT)
+#define FMC_BRD_PFB0CR_B0DCE(base) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DCE_SHIFT))
+
+/*! @brief Set the B0DCE field to a new value. */
+#define FMC_WR_PFB0CR_B0DCE(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_B0DCE_MASK, FMC_PFB0CR_B0DCE(value)))
+#define FMC_BWR_PFB0CR_B0DCE(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_B0DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CRC[7:5] (RW)
+ *
+ * This 3-bit field defines the replacement algorithm for accesses that are
+ * cached.
+ *
+ * Values:
+ * - 0b000 - LRU replacement algorithm per set across all four ways
+ * - 0b001 - Reserved
+ * - 0b010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data
+ * - 0b011 - Independent LRU with ways [0-2] for ifetches, [3] for data
+ * - 0b1xx - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_CRC field. */
+#define FMC_RD_PFB0CR_CRC(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_CRC_MASK) >> FMC_PFB0CR_CRC_SHIFT)
+#define FMC_BRD_PFB0CR_CRC(base) (FMC_RD_PFB0CR_CRC(base))
+
+/*! @brief Set the CRC field to a new value. */
+#define FMC_WR_PFB0CR_CRC(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CRC_MASK, FMC_PFB0CR_CRC(value)))
+#define FMC_BWR_PFB0CR_CRC(base, value) (FMC_WR_PFB0CR_CRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 0 memory.
+ *
+ * Values:
+ * - 0b00 - 32 bits
+ * - 0b01 - 64 bits
+ * - 0b10 - 128 bits
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0MW field. */
+#define FMC_RD_PFB0CR_B0MW(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0MW_MASK) >> FMC_PFB0CR_B0MW_SHIFT)
+#define FMC_BRD_PFB0CR_B0MW(base) (FMC_RD_PFB0CR_B0MW(base))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ)
+ *
+ * This bit determines if the FMC's prefetch speculation buffer and the single
+ * entry page buffer are to be invalidated (cleared). When this bit is written,
+ * the speculation buffer and single entry buffer are immediately cleared. This bit
+ * always reads as zero.
+ *
+ * Values:
+ * - 0b0 - Speculation buffer and single entry buffer are not affected.
+ * - 0b1 - Invalidate (clear) speculation buffer and single entry buffer.
+ */
+/*@{*/
+/*! @brief Set the S_B_INV field to a new value. */
+#define FMC_WR_PFB0CR_S_B_INV(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_S_B_INV_MASK, FMC_PFB0CR_S_B_INV(value)))
+#define FMC_BWR_PFB0CR_S_B_INV(base, value) (BITBAND_ACCESS32(&FMC_PFB0CR_REG(base), FMC_PFB0CR_S_B_INV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ)
+ *
+ * These bits determine if the given cache way is to be invalidated (cleared).
+ * When a bit within this field is written, the corresponding cache way is
+ * immediately invalidated: the way's tag, data, and valid contents are cleared. This
+ * field always reads as zero. Cache invalidation takes precedence over locking.
+ * The cache is invalidated by system reset. System software is required to
+ * maintain memory coherency when any segment of the flash memory is programmed or
+ * erased. Accordingly, cache invalidations must occur after a programming or erase
+ * event is completed and before the new memory image is accessed. The bit setting
+ * definitions are for each bit in the field.
+ *
+ * Values:
+ * - 0b0000 - No cache way invalidation for the corresponding cache
+ * - 0b0001 - Invalidate cache way for the corresponding cache: clear the tag,
+ *     data, and vld bits of ways selected
+ */
+/*@{*/
+/*! @brief Set the CINV_WAY field to a new value. */
+#define FMC_WR_PFB0CR_CINV_WAY(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY(value)))
+#define FMC_BWR_PFB0CR_CINV_WAY(base, value) (FMC_WR_PFB0CR_CINV_WAY(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW)
+ *
+ * These bits determine if the given cache way is locked such that its contents
+ * will not be displaced by future misses. The bit setting definitions are for
+ * each bit in the field.
+ *
+ * Values:
+ * - 0b0000 - Cache way is unlocked and may be displaced
+ * - 0b0001 - Cache way is locked and its contents are not displaced
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */
+#define FMC_RD_PFB0CR_CLCK_WAY(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_CLCK_WAY_MASK) >> FMC_PFB0CR_CLCK_WAY_SHIFT)
+#define FMC_BRD_PFB0CR_CLCK_WAY(base) (FMC_RD_PFB0CR_CLCK_WAY(base))
+
+/*! @brief Set the CLCK_WAY field to a new value. */
+#define FMC_WR_PFB0CR_CLCK_WAY(base, value) (FMC_RMW_PFB0CR(base, FMC_PFB0CR_CLCK_WAY_MASK, FMC_PFB0CR_CLCK_WAY(value)))
+#define FMC_BWR_PFB0CR_CLCK_WAY(base, value) (FMC_WR_PFB0CR_CLCK_WAY(base, value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 0 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */
+#define FMC_RD_PFB0CR_B0RWSC(base) ((FMC_PFB0CR_REG(base) & FMC_PFB0CR_B0RWSC_MASK) >> FMC_PFB0CR_B0RWSC_SHIFT)
+#define FMC_BRD_PFB0CR_B0RWSC(base) (FMC_RD_PFB0CR_B0RWSC(base))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_PFB1CR - Flash Bank 1 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_PFB1CR - Flash Bank 1 Control Register (RW)
+ *
+ * Reset value: 0x3004001FU
+ *
+ * This register has a format similar to that for PFB0CR, except it controls the
+ * operation of flash bank 1, and the "global" cache control fields are empty.
+ */
+/*!
+ * @name Constants and macros for entire FMC_PFB1CR register
+ */
+/*@{*/
+#define FMC_RD_PFB1CR(base)      (FMC_PFB1CR_REG(base))
+#define FMC_WR_PFB1CR(base, value) (FMC_PFB1CR_REG(base) = (value))
+#define FMC_RMW_PFB1CR(base, mask, value) (FMC_WR_PFB1CR(base, (FMC_RD_PFB1CR(base) & ~(mask)) | (value)))
+#define FMC_SET_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) |  (value)))
+#define FMC_CLR_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) & ~(value)))
+#define FMC_TOG_PFB1CR(base, value) (FMC_WR_PFB1CR(base, FMC_RD_PFB1CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_PFB1CR bitfields
+ */
+
+/*!
+ * @name Register FMC_PFB1CR, field B1SEBE[0] (RW)
+ *
+ * This bit controls whether the single entry buffer is enabled in response to
+ * flash read accesses. Its operation is independent from bank 0's cache. A
+ * high-to-low transition of this enable forces the page buffer to be invalidated.
+ *
+ * Values:
+ * - 0b0 - Single entry buffer is disabled.
+ * - 0b1 - Single entry buffer is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */
+#define FMC_RD_PFB1CR_B1SEBE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1SEBE_MASK) >> FMC_PFB1CR_B1SEBE_SHIFT)
+#define FMC_BRD_PFB1CR_B1SEBE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1SEBE_SHIFT))
+
+/*! @brief Set the B1SEBE field to a new value. */
+#define FMC_WR_PFB1CR_B1SEBE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1SEBE_MASK, FMC_PFB1CR_B1SEBE(value)))
+#define FMC_BWR_PFB1CR_B1SEBE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1SEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1IPE[1] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to instruction fetches.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to instruction fetches.
+ * - 0b1 - Enable prefetches in response to instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */
+#define FMC_RD_PFB1CR_B1IPE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1IPE_MASK) >> FMC_PFB1CR_B1IPE_SHIFT)
+#define FMC_BRD_PFB1CR_B1IPE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1IPE_SHIFT))
+
+/*! @brief Set the B1IPE field to a new value. */
+#define FMC_WR_PFB1CR_B1IPE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1IPE_MASK, FMC_PFB1CR_B1IPE(value)))
+#define FMC_BWR_PFB1CR_B1IPE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1IPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DPE[2] (RW)
+ *
+ * This bit controls whether prefetches (or speculative accesses) are initiated
+ * in response to data references.
+ *
+ * Values:
+ * - 0b0 - Do not prefetch in response to data references.
+ * - 0b1 - Enable prefetches in response to data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */
+#define FMC_RD_PFB1CR_B1DPE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1DPE_MASK) >> FMC_PFB1CR_B1DPE_SHIFT)
+#define FMC_BRD_PFB1CR_B1DPE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DPE_SHIFT))
+
+/*! @brief Set the B1DPE field to a new value. */
+#define FMC_WR_PFB1CR_B1DPE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1DPE_MASK, FMC_PFB1CR_B1DPE(value)))
+#define FMC_BWR_PFB1CR_B1DPE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1ICE[3] (RW)
+ *
+ * This bit controls whether instruction fetches are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache instruction fetches.
+ * - 0b1 - Cache instruction fetches.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */
+#define FMC_RD_PFB1CR_B1ICE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1ICE_MASK) >> FMC_PFB1CR_B1ICE_SHIFT)
+#define FMC_BRD_PFB1CR_B1ICE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1ICE_SHIFT))
+
+/*! @brief Set the B1ICE field to a new value. */
+#define FMC_WR_PFB1CR_B1ICE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1ICE_MASK, FMC_PFB1CR_B1ICE(value)))
+#define FMC_BWR_PFB1CR_B1ICE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1ICE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1DCE[4] (RW)
+ *
+ * This bit controls whether data references are loaded into the cache.
+ *
+ * Values:
+ * - 0b0 - Do not cache data references.
+ * - 0b1 - Cache data references.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */
+#define FMC_RD_PFB1CR_B1DCE(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1DCE_MASK) >> FMC_PFB1CR_B1DCE_SHIFT)
+#define FMC_BRD_PFB1CR_B1DCE(base) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DCE_SHIFT))
+
+/*! @brief Set the B1DCE field to a new value. */
+#define FMC_WR_PFB1CR_B1DCE(base, value) (FMC_RMW_PFB1CR(base, FMC_PFB1CR_B1DCE_MASK, FMC_PFB1CR_B1DCE(value)))
+#define FMC_BWR_PFB1CR_B1DCE(base, value) (BITBAND_ACCESS32(&FMC_PFB1CR_REG(base), FMC_PFB1CR_B1DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1MW[18:17] (RO)
+ *
+ * This read-only field defines the width of the bank 1 memory.
+ *
+ * Values:
+ * - 0b00 - 32 bits
+ * - 0b01 - 64 bits
+ * - 0b10 - 128 bits
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1MW field. */
+#define FMC_RD_PFB1CR_B1MW(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1MW_MASK) >> FMC_PFB1CR_B1MW_SHIFT)
+#define FMC_BRD_PFB1CR_B1MW(base) (FMC_RD_PFB1CR_B1MW(base))
+/*@}*/
+
+/*!
+ * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO)
+ *
+ * This read-only field defines the number of wait states required to access the
+ * bank 1 flash memory. The relationship between the read access time of the
+ * flash array (expressed in system clock cycles) and RWSC is defined as: Access
+ * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates
+ * this value based on the ratio of the system clock speed to the flash clock
+ * speed. For example, when this ratio is 4:1, the field's value is 3h.
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */
+#define FMC_RD_PFB1CR_B1RWSC(base) ((FMC_PFB1CR_REG(base) & FMC_PFB1CR_B1RWSC_MASK) >> FMC_PFB1CR_B1RWSC_SHIFT)
+#define FMC_BRD_PFB1CR_B1RWSC(base) (FMC_RD_PFB1CR_B1RWSC(base))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW0S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW0S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW0S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW0S(base, index) (FMC_TAGVDW0S_REG(base, index))
+#define FMC_WR_TAGVDW0S(base, index, value) (FMC_TAGVDW0S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW0S(base, index, mask, value) (FMC_WR_TAGVDW0S(base, index, (FMC_RD_TAGVDW0S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW0S(base, index, value) (FMC_WR_TAGVDW0S(base, index, FMC_RD_TAGVDW0S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW0S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW0S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW0S_valid field. */
+#define FMC_RD_TAGVDW0S_valid(base, index) ((FMC_TAGVDW0S_REG(base, index) & FMC_TAGVDW0S_valid_MASK) >> FMC_TAGVDW0S_valid_SHIFT)
+#define FMC_BRD_TAGVDW0S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW0S_REG(base, index), FMC_TAGVDW0S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW0S_valid(base, index, value) (FMC_RMW_TAGVDW0S(base, index, FMC_TAGVDW0S_valid_MASK, FMC_TAGVDW0S_valid(value)))
+#define FMC_BWR_TAGVDW0S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW0S_REG(base, index), FMC_TAGVDW0S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW0S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW0S_tag field. */
+#define FMC_RD_TAGVDW0S_tag(base, index) ((FMC_TAGVDW0S_REG(base, index) & FMC_TAGVDW0S_tag_MASK) >> FMC_TAGVDW0S_tag_SHIFT)
+#define FMC_BRD_TAGVDW0S_tag(base, index) (FMC_RD_TAGVDW0S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW0S_tag(base, index, value) (FMC_RMW_TAGVDW0S(base, index, FMC_TAGVDW0S_tag_MASK, FMC_TAGVDW0S_tag(value)))
+#define FMC_BWR_TAGVDW0S_tag(base, index, value) (FMC_WR_TAGVDW0S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW1S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW1S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW1S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW1S(base, index) (FMC_TAGVDW1S_REG(base, index))
+#define FMC_WR_TAGVDW1S(base, index, value) (FMC_TAGVDW1S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW1S(base, index, mask, value) (FMC_WR_TAGVDW1S(base, index, (FMC_RD_TAGVDW1S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW1S(base, index, value) (FMC_WR_TAGVDW1S(base, index, FMC_RD_TAGVDW1S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW1S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW1S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW1S_valid field. */
+#define FMC_RD_TAGVDW1S_valid(base, index) ((FMC_TAGVDW1S_REG(base, index) & FMC_TAGVDW1S_valid_MASK) >> FMC_TAGVDW1S_valid_SHIFT)
+#define FMC_BRD_TAGVDW1S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW1S_REG(base, index), FMC_TAGVDW1S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW1S_valid(base, index, value) (FMC_RMW_TAGVDW1S(base, index, FMC_TAGVDW1S_valid_MASK, FMC_TAGVDW1S_valid(value)))
+#define FMC_BWR_TAGVDW1S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW1S_REG(base, index), FMC_TAGVDW1S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW1S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW1S_tag field. */
+#define FMC_RD_TAGVDW1S_tag(base, index) ((FMC_TAGVDW1S_REG(base, index) & FMC_TAGVDW1S_tag_MASK) >> FMC_TAGVDW1S_tag_SHIFT)
+#define FMC_BRD_TAGVDW1S_tag(base, index) (FMC_RD_TAGVDW1S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW1S_tag(base, index, value) (FMC_RMW_TAGVDW1S(base, index, FMC_TAGVDW1S_tag_MASK, FMC_TAGVDW1S_tag(value)))
+#define FMC_BWR_TAGVDW1S_tag(base, index, value) (FMC_WR_TAGVDW1S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW2S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW2S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW2S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW2S(base, index) (FMC_TAGVDW2S_REG(base, index))
+#define FMC_WR_TAGVDW2S(base, index, value) (FMC_TAGVDW2S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW2S(base, index, mask, value) (FMC_WR_TAGVDW2S(base, index, (FMC_RD_TAGVDW2S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW2S(base, index, value) (FMC_WR_TAGVDW2S(base, index, FMC_RD_TAGVDW2S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW2S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW2S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW2S_valid field. */
+#define FMC_RD_TAGVDW2S_valid(base, index) ((FMC_TAGVDW2S_REG(base, index) & FMC_TAGVDW2S_valid_MASK) >> FMC_TAGVDW2S_valid_SHIFT)
+#define FMC_BRD_TAGVDW2S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW2S_REG(base, index), FMC_TAGVDW2S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW2S_valid(base, index, value) (FMC_RMW_TAGVDW2S(base, index, FMC_TAGVDW2S_valid_MASK, FMC_TAGVDW2S_valid(value)))
+#define FMC_BWR_TAGVDW2S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW2S_REG(base, index), FMC_TAGVDW2S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW2S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW2S_tag field. */
+#define FMC_RD_TAGVDW2S_tag(base, index) ((FMC_TAGVDW2S_REG(base, index) & FMC_TAGVDW2S_tag_MASK) >> FMC_TAGVDW2S_tag_SHIFT)
+#define FMC_BRD_TAGVDW2S_tag(base, index) (FMC_RD_TAGVDW2S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW2S_tag(base, index, value) (FMC_RMW_TAGVDW2S(base, index, FMC_TAGVDW2S_tag_MASK, FMC_TAGVDW2S_tag(value)))
+#define FMC_BWR_TAGVDW2S_tag(base, index, value) (FMC_WR_TAGVDW2S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_TAGVDW3S - Cache Tag Storage
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_TAGVDW3S - Cache Tag Storage (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache is a 4-way, set-associative cache with 4 sets. The ways are
+ * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y
+ * denotes the set. This section represents tag/vld information for all sets in the
+ * indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_TAGVDW3S register
+ */
+/*@{*/
+#define FMC_RD_TAGVDW3S(base, index) (FMC_TAGVDW3S_REG(base, index))
+#define FMC_WR_TAGVDW3S(base, index, value) (FMC_TAGVDW3S_REG(base, index) = (value))
+#define FMC_RMW_TAGVDW3S(base, index, mask, value) (FMC_WR_TAGVDW3S(base, index, (FMC_RD_TAGVDW3S(base, index) & ~(mask)) | (value)))
+#define FMC_SET_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) |  (value)))
+#define FMC_CLR_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) & ~(value)))
+#define FMC_TOG_TAGVDW3S(base, index, value) (FMC_WR_TAGVDW3S(base, index, FMC_RD_TAGVDW3S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FMC_TAGVDW3S bitfields
+ */
+
+/*!
+ * @name Register FMC_TAGVDW3S, field valid[0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW3S_valid field. */
+#define FMC_RD_TAGVDW3S_valid(base, index) ((FMC_TAGVDW3S_REG(base, index) & FMC_TAGVDW3S_valid_MASK) >> FMC_TAGVDW3S_valid_SHIFT)
+#define FMC_BRD_TAGVDW3S_valid(base, index) (BITBAND_ACCESS32(&FMC_TAGVDW3S_REG(base, index), FMC_TAGVDW3S_valid_SHIFT))
+
+/*! @brief Set the valid field to a new value. */
+#define FMC_WR_TAGVDW3S_valid(base, index, value) (FMC_RMW_TAGVDW3S(base, index, FMC_TAGVDW3S_valid_MASK, FMC_TAGVDW3S_valid(value)))
+#define FMC_BWR_TAGVDW3S_valid(base, index, value) (BITBAND_ACCESS32(&FMC_TAGVDW3S_REG(base, index), FMC_TAGVDW3S_valid_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FMC_TAGVDW3S, field tag[18:5] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FMC_TAGVDW3S_tag field. */
+#define FMC_RD_TAGVDW3S_tag(base, index) ((FMC_TAGVDW3S_REG(base, index) & FMC_TAGVDW3S_tag_MASK) >> FMC_TAGVDW3S_tag_SHIFT)
+#define FMC_BRD_TAGVDW3S_tag(base, index) (FMC_RD_TAGVDW3S_tag(base, index))
+
+/*! @brief Set the tag field to a new value. */
+#define FMC_WR_TAGVDW3S_tag(base, index, value) (FMC_RMW_TAGVDW3S(base, index, FMC_TAGVDW3S_tag_MASK, FMC_TAGVDW3S_tag(value)))
+#define FMC_BWR_TAGVDW3S_tag(base, index, value) (FMC_WR_TAGVDW3S_tag(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_DATA_U - Cache Data Storage (upper word)
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_DATA_U - Cache Data Storage (upper word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the upper word (bits
+ * [63:32]) of all sets in the indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_DATA_U register
+ */
+/*@{*/
+#define FMC_RD_DATA_U(base, index, index2) (FMC_DATA_U_REG(base, index, index2))
+#define FMC_WR_DATA_U(base, index, index2, value) (FMC_DATA_U_REG(base, index, index2) = (value))
+#define FMC_RMW_DATA_U(base, index, index2, mask, value) (FMC_WR_DATA_U(base, index, index2, (FMC_RD_DATA_U(base, index, index2) & ~(mask)) | (value)))
+#define FMC_SET_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) |  (value)))
+#define FMC_CLR_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) & ~(value)))
+#define FMC_TOG_DATA_U(base, index, index2, value) (FMC_WR_DATA_U(base, index, index2, FMC_RD_DATA_U(base, index, index2) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FMC_DATA_L - Cache Data Storage (lower word)
+ ******************************************************************************/
+
+/*!
+ * @brief FMC_DATA_L - Cache Data Storage (lower word) (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets.
+ * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and
+ * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and
+ * lower word, respectively. This section represents data for the lower word (bits
+ * [31:0]) of all sets in the indicated way.
+ */
+/*!
+ * @name Constants and macros for entire FMC_DATA_L register
+ */
+/*@{*/
+#define FMC_RD_DATA_L(base, index, index2) (FMC_DATA_L_REG(base, index, index2))
+#define FMC_WR_DATA_L(base, index, index2, value) (FMC_DATA_L_REG(base, index, index2) = (value))
+#define FMC_RMW_DATA_L(base, index, index2, mask, value) (FMC_WR_DATA_L(base, index, index2, (FMC_RD_DATA_L(base, index, index2) & ~(mask)) | (value)))
+#define FMC_SET_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) |  (value)))
+#define FMC_CLR_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) & ~(value)))
+#define FMC_TOG_DATA_L(base, index, index2, value) (FMC_WR_DATA_L(base, index, index2, FMC_RD_DATA_L(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FTFE
+ *
+ * Flash Memory Interface
+ *
+ * Registers defined in this header file:
+ * - FTFE_FSTAT - Flash Status Register
+ * - FTFE_FCNFG - Flash Configuration Register
+ * - FTFE_FSEC - Flash Security Register
+ * - FTFE_FOPT - Flash Option Register
+ * - FTFE_FCCOB3 - Flash Common Command Object Registers
+ * - FTFE_FCCOB2 - Flash Common Command Object Registers
+ * - FTFE_FCCOB1 - Flash Common Command Object Registers
+ * - FTFE_FCCOB0 - Flash Common Command Object Registers
+ * - FTFE_FCCOB7 - Flash Common Command Object Registers
+ * - FTFE_FCCOB6 - Flash Common Command Object Registers
+ * - FTFE_FCCOB5 - Flash Common Command Object Registers
+ * - FTFE_FCCOB4 - Flash Common Command Object Registers
+ * - FTFE_FCCOBB - Flash Common Command Object Registers
+ * - FTFE_FCCOBA - Flash Common Command Object Registers
+ * - FTFE_FCCOB9 - Flash Common Command Object Registers
+ * - FTFE_FCCOB8 - Flash Common Command Object Registers
+ * - FTFE_FPROT3 - Program Flash Protection Registers
+ * - FTFE_FPROT2 - Program Flash Protection Registers
+ * - FTFE_FPROT1 - Program Flash Protection Registers
+ * - FTFE_FPROT0 - Program Flash Protection Registers
+ * - FTFE_FEPROT - EEPROM Protection Register
+ * - FTFE_FDPROT - Data Flash Protection Register
+ */
+
+#define FTFE_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFE module. */
+#define FTFE_IDX (0U) /*!< Instance number for FTFE. */
+
+/*******************************************************************************
+ * FTFE_FSTAT - Flash Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FSTAT - Flash Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FSTAT register reports the operational status of the FTFE module. The
+ * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0
+ * bit is read only. The unassigned bits read 0 and are not writable. When set, the
+ * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this
+ * register prevent the launch of any more commands or writes to the FlexRAM (when
+ * EEERDY is set) until the flag is cleared (by writing a one to it).
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FSTAT register
+ */
+/*@{*/
+#define FTFE_RD_FSTAT(base)      (FTFE_FSTAT_REG(base))
+#define FTFE_WR_FSTAT(base, value) (FTFE_FSTAT_REG(base) = (value))
+#define FTFE_RMW_FSTAT(base, mask, value) (FTFE_WR_FSTAT(base, (FTFE_RD_FSTAT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) |  (value)))
+#define FTFE_CLR_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) & ~(value)))
+#define FTFE_TOG_FSTAT(base, value) (FTFE_WR_FSTAT(base, FTFE_RD_FSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FSTAT bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO)
+ *
+ * The MGSTAT0 status flag is set if an error is detected during execution of an
+ * FTFE command or during the flash reset sequence. As a status flag, this bit
+ * cannot (and need not) be cleared by the user like the other error flags in this
+ * register. The value of the MGSTAT0 bit for "command-N" is valid only at the
+ * end of the "command-N" execution when CCIF=1 and before the next command has
+ * been launched. At some point during the execution of "command-N+1," the previous
+ * result is discarded and any previous error is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field. */
+#define FTFE_RD_FSTAT_MGSTAT0(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_MGSTAT0_MASK) >> FTFE_FSTAT_MGSTAT0_SHIFT)
+#define FTFE_BRD_FSTAT_MGSTAT0(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_MGSTAT0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C)
+ *
+ * The FPVIOL error bit indicates an attempt was made to program or erase an
+ * address in a protected area of program flash or data flash memory during a
+ * command write sequence or a write was attempted to a protected area of the FlexRAM
+ * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared
+ * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a
+ * 0 to the FPVIOL bit has no effect.
+ *
+ * Values:
+ * - 0b0 - No protection violation detected
+ * - 0b1 - Protection violation detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_FPVIOL field. */
+#define FTFE_RD_FSTAT_FPVIOL(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_FPVIOL_MASK) >> FTFE_FSTAT_FPVIOL_SHIFT)
+#define FTFE_BRD_FSTAT_FPVIOL(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_FPVIOL_SHIFT))
+
+/*! @brief Set the FPVIOL field to a new value. */
+#define FTFE_WR_FSTAT_FPVIOL(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_FPVIOL(value)))
+#define FTFE_BWR_FSTAT_FPVIOL(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_FPVIOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field ACCERR[5] (W1C)
+ *
+ * The ACCERR error bit indicates an illegal access has occurred to an FTFE
+ * resource caused by a violation of the command write sequence or issuing an illegal
+ * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch
+ * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
+ * ACCERR bit has no effect.
+ *
+ * Values:
+ * - 0b0 - No access error detected
+ * - 0b1 - Access error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_ACCERR field. */
+#define FTFE_RD_FSTAT_ACCERR(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_ACCERR_MASK) >> FTFE_FSTAT_ACCERR_SHIFT)
+#define FTFE_BRD_FSTAT_ACCERR(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_ACCERR_SHIFT))
+
+/*! @brief Set the ACCERR field to a new value. */
+#define FTFE_WR_FSTAT_ACCERR(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_ACCERR(value)))
+#define FTFE_BWR_FSTAT_ACCERR(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_ACCERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C)
+ *
+ * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE
+ * resource that was being manipulated by an FTFE command (CCIF=0). Any
+ * simultaneous access is detected as a collision error by the block arbitration logic. The
+ * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by
+ * writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
+ *
+ * Values:
+ * - 0b0 - No collision error detected
+ * - 0b1 - Collision error detected
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_RDCOLERR field. */
+#define FTFE_RD_FSTAT_RDCOLERR(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_RDCOLERR_MASK) >> FTFE_FSTAT_RDCOLERR_SHIFT)
+#define FTFE_BRD_FSTAT_RDCOLERR(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_RDCOLERR_SHIFT))
+
+/*! @brief Set the RDCOLERR field to a new value. */
+#define FTFE_WR_FSTAT_RDCOLERR(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_RDCOLERR_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_CCIF_MASK), FTFE_FSTAT_RDCOLERR(value)))
+#define FTFE_BWR_FSTAT_RDCOLERR(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_RDCOLERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSTAT, field CCIF[7] (W1C)
+ *
+ * The CCIF flag indicates that a FTFE command or EEPROM file system operation
+ * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a
+ * command, and CCIF stays low until command completion or command violation. The
+ * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE,
+ * and CCIF stays low until the EEPROM file system has created the associated
+ * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory
+ * controller at the end of the reset initialization sequence. Depending on how
+ * quickly the read occurs after reset release, the user may or may not see the 0
+ * hardware reset value.
+ *
+ * Values:
+ * - 0b0 - FTFE command or EEPROM file system operation in progress
+ * - 0b1 - FTFE command or EEPROM file system operation has completed
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSTAT_CCIF field. */
+#define FTFE_RD_FSTAT_CCIF(base) ((FTFE_FSTAT_REG(base) & FTFE_FSTAT_CCIF_MASK) >> FTFE_FSTAT_CCIF_SHIFT)
+#define FTFE_BRD_FSTAT_CCIF(base) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_CCIF_SHIFT))
+
+/*! @brief Set the CCIF field to a new value. */
+#define FTFE_WR_FSTAT_CCIF(base, value) (FTFE_RMW_FSTAT(base, (FTFE_FSTAT_CCIF_MASK | FTFE_FSTAT_FPVIOL_MASK | FTFE_FSTAT_ACCERR_MASK | FTFE_FSTAT_RDCOLERR_MASK), FTFE_FSTAT_CCIF(value)))
+#define FTFE_BWR_FSTAT_CCIF(base, value) (BITBAND_ACCESS8(&FTFE_FSTAT_REG(base), FTFE_FSTAT_CCIF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCNFG - Flash Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCNFG - Flash Configuration Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides information on the current functional state of the
+ * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write
+ * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned
+ * bits read as noted and are not writable. The reset values for the SWAP, PFLSH,
+ * RAMRDY, and EEERDY bits are determined during the reset sequence.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCNFG register
+ */
+/*@{*/
+#define FTFE_RD_FCNFG(base)      (FTFE_FCNFG_REG(base))
+#define FTFE_WR_FCNFG(base, value) (FTFE_FCNFG_REG(base) = (value))
+#define FTFE_RMW_FCNFG(base, mask, value) (FTFE_WR_FCNFG(base, (FTFE_RD_FCNFG(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) |  (value)))
+#define FTFE_CLR_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) & ~(value)))
+#define FTFE_TOG_FCNFG(base, value) (FTFE_WR_FCNFG(base, FTFE_RD_FCNFG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FCNFG bitfields
+ */
+
+/*!
+ * @name Register FTFE_FCNFG, field EEERDY[0] (RO)
+ *
+ * For devices with FlexNVM: This flag indicates if the EEPROM backup data has
+ * been copied to the FlexRAM and is therefore available for read access. During
+ * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if
+ * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM:
+ * This bit is reserved.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FlexRAM is not available for EEPROM
+ *     operation.
+ * - 0b1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations
+ *     where: reads from the FlexRAM return data previously written to the
+ *     FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the
+ *     written data in the FlexRAM and EEPROM backup.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_EEERDY field. */
+#define FTFE_RD_FCNFG_EEERDY(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_EEERDY_MASK) >> FTFE_FCNFG_EEERDY_SHIFT)
+#define FTFE_BRD_FCNFG_EEERDY(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_EEERDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field RAMRDY[1] (RO)
+ *
+ * This flag indicates the current status of the FlexRAM/ programming
+ * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally
+ * controlled by the Set FlexRAM Function command. During the reset sequence, the
+ * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will
+ * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is
+ * cleared if the Program Partition command is run to partition the FlexNVM block
+ * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks
+ * command or execution of the erase-all operation triggered external to the FTFE.
+ * For devices without FlexNVM: This bit should always be set.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FlexRAM is not available for traditional
+ *     RAM access. For devices without FlexNVM: Programming acceleration RAM is not
+ *     available.
+ * - 0b1 - For devices with FlexNVM: FlexRAM is available as traditional RAM
+ *     only; writes to the FlexRAM do not trigger EEPROM operations. For devices
+ *     without FlexNVM: Programming acceleration RAM is available.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_RAMRDY field. */
+#define FTFE_RD_FCNFG_RAMRDY(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_RAMRDY_MASK) >> FTFE_FCNFG_RAMRDY_SHIFT)
+#define FTFE_BRD_FCNFG_RAMRDY(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RAMRDY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field PFLSH[2] (RO)
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: FTFE configuration supports two program
+ *     flash blocks and two FlexNVM blocks For devices with program flash only:
+ *     Reserved
+ * - 0b1 - For devices with FlexNVM: Reserved For devices with program flash
+ *     only: FTFE configuration supports four program flash blocks
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_PFLSH field. */
+#define FTFE_RD_FCNFG_PFLSH(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_PFLSH_MASK) >> FTFE_FCNFG_PFLSH_SHIFT)
+#define FTFE_BRD_FCNFG_PFLSH(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_PFLSH_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field SWAP[3] (RO)
+ *
+ * The SWAP flag indicates which half of the program flash space is located at
+ * relative address 0x0000. The state of the SWAP flag is set by the FTFE during
+ * the reset sequence. See for information on swap management.
+ *
+ * Values:
+ * - 0b0 - For devices with FlexNVM: Program flash 0 block is located at
+ *     relative address 0x0000 For devices with program flash only: Program flash 0
+ *     block is located at relative address 0x0000
+ * - 0b1 - For devices with FlexNVM: Reserved For devices with program flash
+ *     only: Program flash 1 block is located at relative address 0x0000
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_SWAP field. */
+#define FTFE_RD_FCNFG_SWAP(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_SWAP_MASK) >> FTFE_FCNFG_SWAP_SHIFT)
+#define FTFE_BRD_FCNFG_SWAP(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_SWAP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW)
+ *
+ * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector
+ * command while it is executing.
+ *
+ * Values:
+ * - 0b0 - No suspend requested
+ * - 0b1 - Suspend the current Erase Flash Sector command execution.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_ERSSUSP field. */
+#define FTFE_RD_FCNFG_ERSSUSP(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_ERSSUSP_MASK) >> FTFE_FCNFG_ERSSUSP_SHIFT)
+#define FTFE_BRD_FCNFG_ERSSUSP(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSSUSP_SHIFT))
+
+/*! @brief Set the ERSSUSP field to a new value. */
+#define FTFE_WR_FCNFG_ERSSUSP(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_ERSSUSP_MASK, FTFE_FCNFG_ERSSUSP(value)))
+#define FTFE_BWR_FCNFG_ERSSUSP(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSSUSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO)
+ *
+ * This bit issues a request to the memory controller to execute the Erase All
+ * Blocks command and release security. ERSAREQ is not directly writable but is
+ * under indirect user control. Refer to the device's Chip Configuration details on
+ * how to request this command. The ERSAREQ bit sets when an erase all request
+ * is triggered external to the FTFE and CCIF is set (no command is currently
+ * being executed). ERSAREQ is cleared by the FTFE when the operation completes.
+ *
+ * Values:
+ * - 0b0 - No request or request complete
+ * - 0b1 - Request to: run the Erase All Blocks command, verify the erased
+ *     state, program the security byte in the Flash Configuration Field to the
+ *     unsecure state, and release MCU security by setting the FSEC[SEC] field to the
+ *     unsecure state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_ERSAREQ field. */
+#define FTFE_RD_FCNFG_ERSAREQ(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_ERSAREQ_MASK) >> FTFE_FCNFG_ERSAREQ_SHIFT)
+#define FTFE_BRD_FCNFG_ERSAREQ(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_ERSAREQ_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW)
+ *
+ * The RDCOLLIE bit controls interrupt generation when an FTFE read collision
+ * error occurs.
+ *
+ * Values:
+ * - 0b0 - Read collision error interrupt disabled
+ * - 0b1 - Read collision error interrupt enabled. An interrupt request is
+ *     generated whenever an FTFE read collision error is detected (see the
+ *     description of FSTAT[RDCOLERR]).
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field. */
+#define FTFE_RD_FCNFG_RDCOLLIE(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_RDCOLLIE_MASK) >> FTFE_FCNFG_RDCOLLIE_SHIFT)
+#define FTFE_BRD_FCNFG_RDCOLLIE(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RDCOLLIE_SHIFT))
+
+/*! @brief Set the RDCOLLIE field to a new value. */
+#define FTFE_WR_FCNFG_RDCOLLIE(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_RDCOLLIE_MASK, FTFE_FCNFG_RDCOLLIE(value)))
+#define FTFE_BWR_FCNFG_RDCOLLIE(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_RDCOLLIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FCNFG, field CCIE[7] (RW)
+ *
+ * The CCIE bit controls interrupt generation when an FTFE command completes.
+ *
+ * Values:
+ * - 0b0 - Command complete interrupt disabled
+ * - 0b1 - Command complete interrupt enabled. An interrupt request is generated
+ *     whenever the FSTAT[CCIF] flag is set.
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FCNFG_CCIE field. */
+#define FTFE_RD_FCNFG_CCIE(base) ((FTFE_FCNFG_REG(base) & FTFE_FCNFG_CCIE_MASK) >> FTFE_FCNFG_CCIE_SHIFT)
+#define FTFE_BRD_FCNFG_CCIE(base) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_CCIE_SHIFT))
+
+/*! @brief Set the CCIE field to a new value. */
+#define FTFE_WR_FCNFG_CCIE(base, value) (FTFE_RMW_FCNFG(base, FTFE_FCNFG_CCIE_MASK, FTFE_FCNFG_CCIE(value)))
+#define FTFE_BWR_FCNFG_CCIE(base, value) (BITBAND_ACCESS8(&FTFE_FCNFG_REG(base), FTFE_FCNFG_CCIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FSEC - Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FSEC - Flash Security Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This read-only register holds all bits associated with the security of the
+ * MCU and FTFE module. During the reset sequence, the register is loaded with the
+ * contents of the flash security byte in the Flash Configuration Field located
+ * in program flash memory. The Flash basis for the values is signified by X in
+ * the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FSEC register
+ */
+/*@{*/
+#define FTFE_RD_FSEC(base)       (FTFE_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTFE_FSEC bitfields
+ */
+
+/*!
+ * @name Register FTFE_FSEC, field SEC[1:0] (RO)
+ *
+ * These bits define the security state of the MCU. In the secure state, the MCU
+ * limits access to FTFE module resources. The limitations are defined per
+ * device and are detailed in the Chip Configuration details. If the FTFE module is
+ * unsecured using backdoor key access, the SEC bits are forced to 10b.
+ *
+ * Values:
+ * - 0b00 - MCU security status is secure
+ * - 0b01 - MCU security status is secure
+ * - 0b10 - MCU security status is unsecure (The standard shipping condition of
+ *     the FTFE is unsecure.)
+ * - 0b11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_SEC field. */
+#define FTFE_RD_FSEC_SEC(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_SEC_MASK) >> FTFE_FSEC_SEC_SHIFT)
+#define FTFE_BRD_FSEC_SEC(base) (FTFE_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field FSLACC[3:2] (RO)
+ *
+ * These bits enable or disable access to the flash memory contents during
+ * returned part failure analysis at Freescale. When SEC is secure and FSLACC is
+ * denied, access to the program flash contents is denied and any failure analysis
+ * performed by Freescale factory test must begin with a full erase to unsecure the
+ * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is
+ * granted), Freescale factory testing has visibility of the current flash
+ * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to
+ * secure. When the SEC field is set to unsecure, the FSLACC setting does not
+ * matter.
+ *
+ * Values:
+ * - 0b00 - Freescale factory access granted
+ * - 0b01 - Freescale factory access denied
+ * - 0b10 - Freescale factory access denied
+ * - 0b11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_FSLACC field. */
+#define FTFE_RD_FSEC_FSLACC(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_FSLACC_MASK) >> FTFE_FSEC_FSLACC_SHIFT)
+#define FTFE_BRD_FSEC_FSLACC(base) (FTFE_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field MEEN[5:4] (RO)
+ *
+ * Enables and disables mass erase capability of the FTFE module. The state of
+ * the MEEN bits is only relevant when the SEC bits are set to secure outside of
+ * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does
+ * not matter.
+ *
+ * Values:
+ * - 0b00 - Mass erase is enabled
+ * - 0b01 - Mass erase is enabled
+ * - 0b10 - Mass erase is disabled
+ * - 0b11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_MEEN field. */
+#define FTFE_RD_FSEC_MEEN(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_MEEN_MASK) >> FTFE_FSEC_MEEN_SHIFT)
+#define FTFE_BRD_FSEC_MEEN(base) (FTFE_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register FTFE_FSEC, field KEYEN[7:6] (RO)
+ *
+ * These bits enable and disable backdoor key access to the FTFE module.
+ *
+ * Values:
+ * - 0b00 - Backdoor key access disabled
+ * - 0b01 - Backdoor key access disabled (preferred KEYEN state to disable
+ *     backdoor key access)
+ * - 0b10 - Backdoor key access enabled
+ * - 0b11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the FTFE_FSEC_KEYEN field. */
+#define FTFE_RD_FSEC_KEYEN(base) ((FTFE_FSEC_REG(base) & FTFE_FSEC_KEYEN_MASK) >> FTFE_FSEC_KEYEN_SHIFT)
+#define FTFE_BRD_FSEC_KEYEN(base) (FTFE_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FOPT - Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FOPT - Flash Option Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * The flash option register allows the MCU to customize its operations by
+ * examining the state of these read-only bits, which are loaded from NVM at reset.
+ * The function of the bits is defined in the device's Chip Configuration details.
+ * All bits in the register are read-only. During the reset sequence, the
+ * register is loaded from the flash nonvolatile option byte in the Flash Configuration
+ * Field located in program flash memory. The flash basis for the values is
+ * signified by X in the reset value.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FOPT register
+ */
+/*@{*/
+#define FTFE_RD_FOPT(base)       (FTFE_FOPT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB3 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB3 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB3 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB3(base)     (FTFE_FCCOB3_REG(base))
+#define FTFE_WR_FCCOB3(base, value) (FTFE_FCCOB3_REG(base) = (value))
+#define FTFE_RMW_FCCOB3(base, mask, value) (FTFE_WR_FCCOB3(base, (FTFE_RD_FCCOB3(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) |  (value)))
+#define FTFE_CLR_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) & ~(value)))
+#define FTFE_TOG_FCCOB3(base, value) (FTFE_WR_FCCOB3(base, FTFE_RD_FCCOB3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB2 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB2 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB2 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB2(base)     (FTFE_FCCOB2_REG(base))
+#define FTFE_WR_FCCOB2(base, value) (FTFE_FCCOB2_REG(base) = (value))
+#define FTFE_RMW_FCCOB2(base, mask, value) (FTFE_WR_FCCOB2(base, (FTFE_RD_FCCOB2(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) |  (value)))
+#define FTFE_CLR_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) & ~(value)))
+#define FTFE_TOG_FCCOB2(base, value) (FTFE_WR_FCCOB2(base, FTFE_RD_FCCOB2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB1 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB1 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB1 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB1(base)     (FTFE_FCCOB1_REG(base))
+#define FTFE_WR_FCCOB1(base, value) (FTFE_FCCOB1_REG(base) = (value))
+#define FTFE_RMW_FCCOB1(base, mask, value) (FTFE_WR_FCCOB1(base, (FTFE_RD_FCCOB1(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) |  (value)))
+#define FTFE_CLR_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) & ~(value)))
+#define FTFE_TOG_FCCOB1(base, value) (FTFE_WR_FCCOB1(base, FTFE_RD_FCCOB1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB0 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB0 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB0 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB0(base)     (FTFE_FCCOB0_REG(base))
+#define FTFE_WR_FCCOB0(base, value) (FTFE_FCCOB0_REG(base) = (value))
+#define FTFE_RMW_FCCOB0(base, mask, value) (FTFE_WR_FCCOB0(base, (FTFE_RD_FCCOB0(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) |  (value)))
+#define FTFE_CLR_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) & ~(value)))
+#define FTFE_TOG_FCCOB0(base, value) (FTFE_WR_FCCOB0(base, FTFE_RD_FCCOB0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB7 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB7 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB7 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB7(base)     (FTFE_FCCOB7_REG(base))
+#define FTFE_WR_FCCOB7(base, value) (FTFE_FCCOB7_REG(base) = (value))
+#define FTFE_RMW_FCCOB7(base, mask, value) (FTFE_WR_FCCOB7(base, (FTFE_RD_FCCOB7(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) |  (value)))
+#define FTFE_CLR_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) & ~(value)))
+#define FTFE_TOG_FCCOB7(base, value) (FTFE_WR_FCCOB7(base, FTFE_RD_FCCOB7(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB6 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB6 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB6 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB6(base)     (FTFE_FCCOB6_REG(base))
+#define FTFE_WR_FCCOB6(base, value) (FTFE_FCCOB6_REG(base) = (value))
+#define FTFE_RMW_FCCOB6(base, mask, value) (FTFE_WR_FCCOB6(base, (FTFE_RD_FCCOB6(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) |  (value)))
+#define FTFE_CLR_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) & ~(value)))
+#define FTFE_TOG_FCCOB6(base, value) (FTFE_WR_FCCOB6(base, FTFE_RD_FCCOB6(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB5 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB5 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB5 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB5(base)     (FTFE_FCCOB5_REG(base))
+#define FTFE_WR_FCCOB5(base, value) (FTFE_FCCOB5_REG(base) = (value))
+#define FTFE_RMW_FCCOB5(base, mask, value) (FTFE_WR_FCCOB5(base, (FTFE_RD_FCCOB5(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) |  (value)))
+#define FTFE_CLR_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) & ~(value)))
+#define FTFE_TOG_FCCOB5(base, value) (FTFE_WR_FCCOB5(base, FTFE_RD_FCCOB5(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB4 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB4 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB4 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB4(base)     (FTFE_FCCOB4_REG(base))
+#define FTFE_WR_FCCOB4(base, value) (FTFE_FCCOB4_REG(base) = (value))
+#define FTFE_RMW_FCCOB4(base, mask, value) (FTFE_WR_FCCOB4(base, (FTFE_RD_FCCOB4(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) |  (value)))
+#define FTFE_CLR_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) & ~(value)))
+#define FTFE_TOG_FCCOB4(base, value) (FTFE_WR_FCCOB4(base, FTFE_RD_FCCOB4(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOBB - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOBB - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBB register
+ */
+/*@{*/
+#define FTFE_RD_FCCOBB(base)     (FTFE_FCCOBB_REG(base))
+#define FTFE_WR_FCCOBB(base, value) (FTFE_FCCOBB_REG(base) = (value))
+#define FTFE_RMW_FCCOBB(base, mask, value) (FTFE_WR_FCCOBB(base, (FTFE_RD_FCCOBB(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) |  (value)))
+#define FTFE_CLR_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) & ~(value)))
+#define FTFE_TOG_FCCOBB(base, value) (FTFE_WR_FCCOBB(base, FTFE_RD_FCCOBB(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOBA - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOBA - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOBA register
+ */
+/*@{*/
+#define FTFE_RD_FCCOBA(base)     (FTFE_FCCOBA_REG(base))
+#define FTFE_WR_FCCOBA(base, value) (FTFE_FCCOBA_REG(base) = (value))
+#define FTFE_RMW_FCCOBA(base, mask, value) (FTFE_WR_FCCOBA(base, (FTFE_RD_FCCOBA(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) |  (value)))
+#define FTFE_CLR_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) & ~(value)))
+#define FTFE_TOG_FCCOBA(base, value) (FTFE_WR_FCCOBA(base, FTFE_RD_FCCOBA(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB9 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB9 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB9 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB9(base)     (FTFE_FCCOB9_REG(base))
+#define FTFE_WR_FCCOB9(base, value) (FTFE_FCCOB9_REG(base) = (value))
+#define FTFE_RMW_FCCOB9(base, mask, value) (FTFE_WR_FCCOB9(base, (FTFE_RD_FCCOB9(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) |  (value)))
+#define FTFE_CLR_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) & ~(value)))
+#define FTFE_TOG_FCCOB9(base, value) (FTFE_WR_FCCOB9(base, FTFE_RD_FCCOB9(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FCCOB8 - Flash Common Command Object Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FCCOB8 - Flash Common Command Object Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FCCOB register group provides 12 bytes for command codes and parameters.
+ * The individual bytes within the set append a 0-B hex identifier to the FCCOB
+ * register name: FCCOB0, FCCOB1, ..., FCCOBB.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FCCOB8 register
+ */
+/*@{*/
+#define FTFE_RD_FCCOB8(base)     (FTFE_FCCOB8_REG(base))
+#define FTFE_WR_FCCOB8(base, value) (FTFE_FCCOB8_REG(base) = (value))
+#define FTFE_RMW_FCCOB8(base, mask, value) (FTFE_WR_FCCOB8(base, (FTFE_RD_FCCOB8(base) & ~(mask)) | (value)))
+#define FTFE_SET_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) |  (value)))
+#define FTFE_CLR_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) & ~(value)))
+#define FTFE_TOG_FCCOB8(base, value) (FTFE_WR_FCCOB8(base, FTFE_RD_FCCOB8(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT3 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT3 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT3 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT3(base)     (FTFE_FPROT3_REG(base))
+#define FTFE_WR_FPROT3(base, value) (FTFE_FPROT3_REG(base) = (value))
+#define FTFE_RMW_FPROT3(base, mask, value) (FTFE_WR_FPROT3(base, (FTFE_RD_FPROT3(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) |  (value)))
+#define FTFE_CLR_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) & ~(value)))
+#define FTFE_TOG_FPROT3(base, value) (FTFE_WR_FPROT3(base, FTFE_RD_FPROT3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT2 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT2 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT2 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT2(base)     (FTFE_FPROT2_REG(base))
+#define FTFE_WR_FPROT2(base, value) (FTFE_FPROT2_REG(base) = (value))
+#define FTFE_RMW_FPROT2(base, mask, value) (FTFE_WR_FPROT2(base, (FTFE_RD_FPROT2(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) |  (value)))
+#define FTFE_CLR_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) & ~(value)))
+#define FTFE_TOG_FPROT2(base, value) (FTFE_WR_FPROT2(base, FTFE_RD_FPROT2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT1 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT1 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT1 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT1(base)     (FTFE_FPROT1_REG(base))
+#define FTFE_WR_FPROT1(base, value) (FTFE_FPROT1_REG(base) = (value))
+#define FTFE_RMW_FPROT1(base, mask, value) (FTFE_WR_FPROT1(base, (FTFE_RD_FPROT1(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) |  (value)))
+#define FTFE_CLR_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) & ~(value)))
+#define FTFE_TOG_FPROT1(base, value) (FTFE_WR_FPROT1(base, FTFE_RD_FPROT1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FPROT0 - Program Flash Protection Registers
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FPROT0 - Program Flash Protection Registers (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FPROT registers define which program flash regions are protected from
+ * program and erase operations. Protected flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by program and erase
+ * operations. The four FPROT registers allow up to 32 protectable regions of equal
+ * memory size. Program flash protection register Program flash protection bits
+ * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
+ * the reset sequence, the FPROT registers are loaded with the contents of the
+ * program flash protection bytes in the Flash Configuration Field as indicated in
+ * the following table. Program flash protection register Flash Configuration Field
+ * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
+ * change the program flash protection that is loaded during the reset sequence,
+ * unprotect the sector of program flash memory that contains the Flash
+ * Configuration Field. Then, reprogram the program flash protection byte.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FPROT0 register
+ */
+/*@{*/
+#define FTFE_RD_FPROT0(base)     (FTFE_FPROT0_REG(base))
+#define FTFE_WR_FPROT0(base, value) (FTFE_FPROT0_REG(base) = (value))
+#define FTFE_RMW_FPROT0(base, mask, value) (FTFE_WR_FPROT0(base, (FTFE_RD_FPROT0(base) & ~(mask)) | (value)))
+#define FTFE_SET_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) |  (value)))
+#define FTFE_CLR_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) & ~(value)))
+#define FTFE_TOG_FPROT0(base, value) (FTFE_WR_FPROT0(base, FTFE_RD_FPROT0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FEPROT - EEPROM Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FEPROT - EEPROM Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of
+ * the FlexRAM are protected against program and erase operations. Protected
+ * EEPROM regions cannot have their content changed by writing to it. Unprotected
+ * regions can be changed by writing to the FlexRAM. For devices with program flash
+ * only: This register is reserved and not used.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FEPROT register
+ */
+/*@{*/
+#define FTFE_RD_FEPROT(base)     (FTFE_FEPROT_REG(base))
+#define FTFE_WR_FEPROT(base, value) (FTFE_FEPROT_REG(base) = (value))
+#define FTFE_RMW_FEPROT(base, mask, value) (FTFE_WR_FEPROT(base, (FTFE_RD_FEPROT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) |  (value)))
+#define FTFE_CLR_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) & ~(value)))
+#define FTFE_TOG_FEPROT(base, value) (FTFE_WR_FEPROT(base, FTFE_RD_FEPROT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * FTFE_FDPROT - Data Flash Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief FTFE_FDPROT - Data Flash Protection Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The FDPROT register defines which data flash regions are protected against
+ * program and erase operations. Protected Flash regions cannot have their content
+ * changed; that is, these regions cannot be programmed and cannot be erased by
+ * any FTFE command. Unprotected regions can be changed by both program and erase
+ * operations.
+ */
+/*!
+ * @name Constants and macros for entire FTFE_FDPROT register
+ */
+/*@{*/
+#define FTFE_RD_FDPROT(base)     (FTFE_FDPROT_REG(base))
+#define FTFE_WR_FDPROT(base, value) (FTFE_FDPROT_REG(base) = (value))
+#define FTFE_RMW_FDPROT(base, mask, value) (FTFE_WR_FDPROT(base, (FTFE_RD_FDPROT(base) & ~(mask)) | (value)))
+#define FTFE_SET_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) |  (value)))
+#define FTFE_CLR_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) & ~(value)))
+#define FTFE_TOG_FDPROT(base, value) (FTFE_WR_FDPROT(base, FTFE_RD_FDPROT(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 FTM
+ *
+ * FlexTimer Module
+ *
+ * Registers defined in this header file:
+ * - FTM_SC - Status And Control
+ * - FTM_CNT - Counter
+ * - FTM_MOD - Modulo
+ * - FTM_CnSC - Channel (n) Status And Control
+ * - FTM_CnV - Channel (n) Value
+ * - FTM_CNTIN - Counter Initial Value
+ * - FTM_STATUS - Capture And Compare Status
+ * - FTM_MODE - Features Mode Selection
+ * - FTM_SYNC - Synchronization
+ * - FTM_OUTINIT - Initial State For Channels Output
+ * - FTM_OUTMASK - Output Mask
+ * - FTM_COMBINE - Function For Linked Channels
+ * - FTM_DEADTIME - Deadtime Insertion Control
+ * - FTM_EXTTRIG - FTM External Trigger
+ * - FTM_POL - Channels Polarity
+ * - FTM_FMS - Fault Mode Status
+ * - FTM_FILTER - Input Capture Filter Control
+ * - FTM_FLTCTRL - Fault Control
+ * - FTM_QDCTRL - Quadrature Decoder Control And Status
+ * - FTM_CONF - Configuration
+ * - FTM_FLTPOL - FTM Fault Input Polarity
+ * - FTM_SYNCONF - Synchronization Configuration
+ * - FTM_INVCTRL - FTM Inverting Control
+ * - FTM_SWOCTRL - FTM Software Output Control
+ * - FTM_PWMLOAD - FTM PWM Load
+ */
+
+#define FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
+#define FTM0_IDX (0U) /*!< Instance number for FTM0. */
+#define FTM1_IDX (1U) /*!< Instance number for FTM1. */
+#define FTM2_IDX (2U) /*!< Instance number for FTM2. */
+#define FTM3_IDX (3U) /*!< Instance number for FTM3. */
+
+/*******************************************************************************
+ * FTM_SC - Status And Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SC - Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * SC contains the overflow status flag and control bits used to configure the
+ * interrupt enable, FTM configuration, clock source, and prescaler factor. These
+ * controls relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SC register
+ */
+/*@{*/
+#define FTM_RD_SC(base)          (FTM_SC_REG(base))
+#define FTM_WR_SC(base, value)   (FTM_SC_REG(base) = (value))
+#define FTM_RMW_SC(base, mask, value) (FTM_WR_SC(base, (FTM_RD_SC(base) & ~(mask)) | (value)))
+#define FTM_SET_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) |  (value)))
+#define FTM_CLR_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) & ~(value)))
+#define FTM_TOG_SC(base, value)  (FTM_WR_SC(base, FTM_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SC bitfields
+ */
+
+/*!
+ * @name Register FTM_SC, field PS[2:0] (RW)
+ *
+ * Selects one of 8 division factors for the clock source selected by CLKS. The
+ * new prescaler factor affects the clock source on the next system clock cycle
+ * after the new value is updated into the register bits. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b000 - Divide by 1
+ * - 0b001 - Divide by 2
+ * - 0b010 - Divide by 4
+ * - 0b011 - Divide by 8
+ * - 0b100 - Divide by 16
+ * - 0b101 - Divide by 32
+ * - 0b110 - Divide by 64
+ * - 0b111 - Divide by 128
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_PS field. */
+#define FTM_RD_SC_PS(base)   ((FTM_SC_REG(base) & FTM_SC_PS_MASK) >> FTM_SC_PS_SHIFT)
+#define FTM_BRD_SC_PS(base)  (FTM_RD_SC_PS(base))
+
+/*! @brief Set the PS field to a new value. */
+#define FTM_WR_SC_PS(base, value) (FTM_RMW_SC(base, FTM_SC_PS_MASK, FTM_SC_PS(value)))
+#define FTM_BWR_SC_PS(base, value) (FTM_WR_SC_PS(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field CLKS[4:3] (RW)
+ *
+ * Selects one of the three FTM counter clock sources. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b00 - No clock selected. This in effect disables the FTM counter.
+ * - 0b01 - System clock
+ * - 0b10 - Fixed frequency clock
+ * - 0b11 - External clock
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_CLKS field. */
+#define FTM_RD_SC_CLKS(base) ((FTM_SC_REG(base) & FTM_SC_CLKS_MASK) >> FTM_SC_CLKS_SHIFT)
+#define FTM_BRD_SC_CLKS(base) (FTM_RD_SC_CLKS(base))
+
+/*! @brief Set the CLKS field to a new value. */
+#define FTM_WR_SC_CLKS(base, value) (FTM_RMW_SC(base, FTM_SC_CLKS_MASK, FTM_SC_CLKS(value)))
+#define FTM_BWR_SC_CLKS(base, value) (FTM_WR_SC_CLKS(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field CPWMS[5] (RW)
+ *
+ * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
+ * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ *
+ * Values:
+ * - 0b0 - FTM counter operates in Up Counting mode.
+ * - 0b1 - FTM counter operates in Up-Down Counting mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_CPWMS field. */
+#define FTM_RD_SC_CPWMS(base) ((FTM_SC_REG(base) & FTM_SC_CPWMS_MASK) >> FTM_SC_CPWMS_SHIFT)
+#define FTM_BRD_SC_CPWMS(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_CPWMS_SHIFT))
+
+/*! @brief Set the CPWMS field to a new value. */
+#define FTM_WR_SC_CPWMS(base, value) (FTM_RMW_SC(base, FTM_SC_CPWMS_MASK, FTM_SC_CPWMS(value)))
+#define FTM_BWR_SC_CPWMS(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_CPWMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field TOIE[6] (RW)
+ *
+ * Enables FTM overflow interrupts.
+ *
+ * Values:
+ * - 0b0 - Disable TOF interrupts. Use software polling.
+ * - 0b1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_TOIE field. */
+#define FTM_RD_SC_TOIE(base) ((FTM_SC_REG(base) & FTM_SC_TOIE_MASK) >> FTM_SC_TOIE_SHIFT)
+#define FTM_BRD_SC_TOIE(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOIE_SHIFT))
+
+/*! @brief Set the TOIE field to a new value. */
+#define FTM_WR_SC_TOIE(base, value) (FTM_RMW_SC(base, FTM_SC_TOIE_MASK, FTM_SC_TOIE(value)))
+#define FTM_BWR_SC_TOIE(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SC, field TOF[7] (ROWZ)
+ *
+ * Set by hardware when the FTM counter passes the value in the MOD register.
+ * The TOF bit is cleared by reading the SC register while TOF is set and then
+ * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
+ * occurs between the read and write operations, the write operation has no
+ * effect; therefore, TOF remains set indicating an overflow has occurred. In this
+ * case, a TOF interrupt request is not lost due to the clearing sequence for a
+ * previous TOF.
+ *
+ * Values:
+ * - 0b0 - FTM counter has not overflowed.
+ * - 0b1 - FTM counter has overflowed.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SC_TOF field. */
+#define FTM_RD_SC_TOF(base)  ((FTM_SC_REG(base) & FTM_SC_TOF_MASK) >> FTM_SC_TOF_SHIFT)
+#define FTM_BRD_SC_TOF(base) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOF_SHIFT))
+
+/*! @brief Set the TOF field to a new value. */
+#define FTM_WR_SC_TOF(base, value) (FTM_RMW_SC(base, FTM_SC_TOF_MASK, FTM_SC_TOF(value)))
+#define FTM_BWR_SC_TOF(base, value) (BITBAND_ACCESS32(&FTM_SC_REG(base), FTM_SC_TOF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CNT - Counter
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CNT - Counter (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The CNT register contains the FTM counter value. Reset clears the CNT
+ * register. Writing any value to COUNT updates the counter with its initial value,
+ * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
+ * may read.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CNT register
+ */
+/*@{*/
+#define FTM_RD_CNT(base)         (FTM_CNT_REG(base))
+#define FTM_WR_CNT(base, value)  (FTM_CNT_REG(base) = (value))
+#define FTM_RMW_CNT(base, mask, value) (FTM_WR_CNT(base, (FTM_RD_CNT(base) & ~(mask)) | (value)))
+#define FTM_SET_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) |  (value)))
+#define FTM_CLR_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) & ~(value)))
+#define FTM_TOG_CNT(base, value) (FTM_WR_CNT(base, FTM_RD_CNT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CNT bitfields
+ */
+
+/*!
+ * @name Register FTM_CNT, field COUNT[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CNT_COUNT field. */
+#define FTM_RD_CNT_COUNT(base) ((FTM_CNT_REG(base) & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT)
+#define FTM_BRD_CNT_COUNT(base) (FTM_RD_CNT_COUNT(base))
+
+/*! @brief Set the COUNT field to a new value. */
+#define FTM_WR_CNT_COUNT(base, value) (FTM_RMW_CNT(base, FTM_CNT_COUNT_MASK, FTM_CNT_COUNT(value)))
+#define FTM_BWR_CNT_COUNT(base, value) (FTM_WR_CNT_COUNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_MOD - Modulo
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_MOD - Modulo (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Modulo register contains the modulo value for the FTM counter. After the
+ * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
+ * the next clock, and the next value of FTM counter depends on the selected
+ * counting method; see Counter. Writing to the MOD register latches the value into a
+ * buffer. The MOD register is updated with the value of its write buffer
+ * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
+ * mechanism may be manually reset by writing to the SC register whether BDM is
+ * active or not. Initialize the FTM counter, by writing to CNT, before writing
+ * to the MOD register to avoid confusion about when the first counter overflow
+ * will occur.
+ */
+/*!
+ * @name Constants and macros for entire FTM_MOD register
+ */
+/*@{*/
+#define FTM_RD_MOD(base)         (FTM_MOD_REG(base))
+#define FTM_WR_MOD(base, value)  (FTM_MOD_REG(base) = (value))
+#define FTM_RMW_MOD(base, mask, value) (FTM_WR_MOD(base, (FTM_RD_MOD(base) & ~(mask)) | (value)))
+#define FTM_SET_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) |  (value)))
+#define FTM_CLR_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) & ~(value)))
+#define FTM_TOG_MOD(base, value) (FTM_WR_MOD(base, FTM_RD_MOD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_MOD bitfields
+ */
+
+/*!
+ * @name Register FTM_MOD, field MOD[15:0] (RW)
+ *
+ * Modulo Value
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MOD_MOD field. */
+#define FTM_RD_MOD_MOD(base) ((FTM_MOD_REG(base) & FTM_MOD_MOD_MASK) >> FTM_MOD_MOD_SHIFT)
+#define FTM_BRD_MOD_MOD(base) (FTM_RD_MOD_MOD(base))
+
+/*! @brief Set the MOD field to a new value. */
+#define FTM_WR_MOD_MOD(base, value) (FTM_RMW_MOD(base, FTM_MOD_MOD_MASK, FTM_MOD_MOD(value)))
+#define FTM_BWR_MOD_MOD(base, value) (FTM_WR_MOD_MOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CnSC - Channel (n) Status And Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CnSC - Channel (n) Status And Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CnSC contains the channel-interrupt-status flag and control bits used to
+ * configure the interrupt enable, channel configuration, and pin function. Mode,
+ * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
+ * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
+ * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
+ * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
+ * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
+ * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
+ * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
+ * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
+ * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
+ * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
+ * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
+ * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
+ * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
+ * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
+ * Enabled Rising and falling edges
+ */
+/*!
+ * @name Constants and macros for entire FTM_CnSC register
+ */
+/*@{*/
+#define FTM_RD_CnSC(base, index) (FTM_CnSC_REG(base, index))
+#define FTM_WR_CnSC(base, index, value) (FTM_CnSC_REG(base, index) = (value))
+#define FTM_RMW_CnSC(base, index, mask, value) (FTM_WR_CnSC(base, index, (FTM_RD_CnSC(base, index) & ~(mask)) | (value)))
+#define FTM_SET_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) |  (value)))
+#define FTM_CLR_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) & ~(value)))
+#define FTM_TOG_CnSC(base, index, value) (FTM_WR_CnSC(base, index, FTM_RD_CnSC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CnSC bitfields
+ */
+
+/*!
+ * @name Register FTM_CnSC, field DMA[0] (RW)
+ *
+ * Enables DMA transfers for the channel.
+ *
+ * Values:
+ * - 0b0 - Disable DMA transfers.
+ * - 0b1 - Enable DMA transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_DMA field. */
+#define FTM_RD_CnSC_DMA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_DMA_MASK) >> FTM_CnSC_DMA_SHIFT)
+#define FTM_BRD_CnSC_DMA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define FTM_WR_CnSC_DMA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_DMA_MASK, FTM_CnSC_DMA(value)))
+#define FTM_BWR_CnSC_DMA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_DMA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field ELSA[2] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_ELSA field. */
+#define FTM_RD_CnSC_ELSA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_ELSA_MASK) >> FTM_CnSC_ELSA_SHIFT)
+#define FTM_BRD_CnSC_ELSA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSA_SHIFT))
+
+/*! @brief Set the ELSA field to a new value. */
+#define FTM_WR_CnSC_ELSA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_ELSA_MASK, FTM_CnSC_ELSA(value)))
+#define FTM_BWR_CnSC_ELSA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field ELSB[3] (RW)
+ *
+ * The functionality of ELSB and ELSA depends on the channel mode. See
+ * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
+ * = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_ELSB field. */
+#define FTM_RD_CnSC_ELSB(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_ELSB_MASK) >> FTM_CnSC_ELSB_SHIFT)
+#define FTM_BRD_CnSC_ELSB(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSB_SHIFT))
+
+/*! @brief Set the ELSB field to a new value. */
+#define FTM_WR_CnSC_ELSB(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_ELSB_MASK, FTM_CnSC_ELSB(value)))
+#define FTM_BWR_CnSC_ELSB(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_ELSB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field MSA[4] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_MSA field. */
+#define FTM_RD_CnSC_MSA(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_MSA_MASK) >> FTM_CnSC_MSA_SHIFT)
+#define FTM_BRD_CnSC_MSA(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSA_SHIFT))
+
+/*! @brief Set the MSA field to a new value. */
+#define FTM_WR_CnSC_MSA(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_MSA_MASK, FTM_CnSC_MSA(value)))
+#define FTM_BWR_CnSC_MSA(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field MSB[5] (RW)
+ *
+ * Used for further selections in the channel logic. Its functionality is
+ * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_MSB field. */
+#define FTM_RD_CnSC_MSB(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_MSB_MASK) >> FTM_CnSC_MSB_SHIFT)
+#define FTM_BRD_CnSC_MSB(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSB_SHIFT))
+
+/*! @brief Set the MSB field to a new value. */
+#define FTM_WR_CnSC_MSB(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_MSB_MASK, FTM_CnSC_MSB(value)))
+#define FTM_BWR_CnSC_MSB(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_MSB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field CHIE[6] (RW)
+ *
+ * Enables channel interrupts.
+ *
+ * Values:
+ * - 0b0 - Disable channel interrupts. Use software polling.
+ * - 0b1 - Enable channel interrupts.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_CHIE field. */
+#define FTM_RD_CnSC_CHIE(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_CHIE_MASK) >> FTM_CnSC_CHIE_SHIFT)
+#define FTM_BRD_CnSC_CHIE(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHIE_SHIFT))
+
+/*! @brief Set the CHIE field to a new value. */
+#define FTM_WR_CnSC_CHIE(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_CHIE_MASK, FTM_CnSC_CHIE(value)))
+#define FTM_BWR_CnSC_CHIE(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CnSC, field CHF[7] (ROWZ)
+ *
+ * Set by hardware when an event occurs on the channel. CHF is cleared by
+ * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
+ * Writing a 1 to CHF has no effect. If another event occurs between the read and
+ * write operations, the write operation has no effect; therefore, CHF remains set
+ * indicating an event has occurred. In this case a CHF interrupt request is not
+ * lost due to the clearing sequence for a previous CHF.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnSC_CHF field. */
+#define FTM_RD_CnSC_CHF(base, index) ((FTM_CnSC_REG(base, index) & FTM_CnSC_CHF_MASK) >> FTM_CnSC_CHF_SHIFT)
+#define FTM_BRD_CnSC_CHF(base, index) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHF_SHIFT))
+
+/*! @brief Set the CHF field to a new value. */
+#define FTM_WR_CnSC_CHF(base, index, value) (FTM_RMW_CnSC(base, index, FTM_CnSC_CHF_MASK, FTM_CnSC_CHF(value)))
+#define FTM_BWR_CnSC_CHF(base, index, value) (BITBAND_ACCESS32(&FTM_CnSC_REG(base, index), FTM_CnSC_CHF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CnV - Channel (n) Value
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CnV - Channel (n) Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the captured FTM counter value for the input modes or
+ * the match value for the output modes. In Input Capture, Capture Test, and
+ * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
+ * writing to a CnV register latches the value into a buffer. A CnV register is
+ * updated with the value of its write buffer according to Registers updated from
+ * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
+ * reset by writing to the CnSC register whether BDM mode is active or not.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CnV register
+ */
+/*@{*/
+#define FTM_RD_CnV(base, index)  (FTM_CnV_REG(base, index))
+#define FTM_WR_CnV(base, index, value) (FTM_CnV_REG(base, index) = (value))
+#define FTM_RMW_CnV(base, index, mask, value) (FTM_WR_CnV(base, index, (FTM_RD_CnV(base, index) & ~(mask)) | (value)))
+#define FTM_SET_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) |  (value)))
+#define FTM_CLR_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) & ~(value)))
+#define FTM_TOG_CnV(base, index, value) (FTM_WR_CnV(base, index, FTM_RD_CnV(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CnV bitfields
+ */
+
+/*!
+ * @name Register FTM_CnV, field VAL[15:0] (RW)
+ *
+ * Captured FTM counter value of the input modes or the match value for the
+ * output modes
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CnV_VAL field. */
+#define FTM_RD_CnV_VAL(base, index) ((FTM_CnV_REG(base, index) & FTM_CnV_VAL_MASK) >> FTM_CnV_VAL_SHIFT)
+#define FTM_BRD_CnV_VAL(base, index) (FTM_RD_CnV_VAL(base, index))
+
+/*! @brief Set the VAL field to a new value. */
+#define FTM_WR_CnV_VAL(base, index, value) (FTM_RMW_CnV(base, index, FTM_CnV_VAL_MASK, FTM_CnV_VAL(value)))
+#define FTM_BWR_CnV_VAL(base, index, value) (FTM_WR_CnV_VAL(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CNTIN - Counter Initial Value
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CNTIN - Counter Initial Value (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Counter Initial Value register contains the initial value for the FTM
+ * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
+ * register is updated with the value of its write buffer according to Registers
+ * updated from write buffers. When the FTM clock is initially selected, by
+ * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
+ * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
+ * write the new value to the the CNTIN register and then initialize the FTM
+ * counter by writing any value to the CNT register.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CNTIN register
+ */
+/*@{*/
+#define FTM_RD_CNTIN(base)       (FTM_CNTIN_REG(base))
+#define FTM_WR_CNTIN(base, value) (FTM_CNTIN_REG(base) = (value))
+#define FTM_RMW_CNTIN(base, mask, value) (FTM_WR_CNTIN(base, (FTM_RD_CNTIN(base) & ~(mask)) | (value)))
+#define FTM_SET_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) |  (value)))
+#define FTM_CLR_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) & ~(value)))
+#define FTM_TOG_CNTIN(base, value) (FTM_WR_CNTIN(base, FTM_RD_CNTIN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CNTIN bitfields
+ */
+
+/*!
+ * @name Register FTM_CNTIN, field INIT[15:0] (RW)
+ *
+ * Initial Value Of The FTM Counter
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CNTIN_INIT field. */
+#define FTM_RD_CNTIN_INIT(base) ((FTM_CNTIN_REG(base) & FTM_CNTIN_INIT_MASK) >> FTM_CNTIN_INIT_SHIFT)
+#define FTM_BRD_CNTIN_INIT(base) (FTM_RD_CNTIN_INIT(base))
+
+/*! @brief Set the INIT field to a new value. */
+#define FTM_WR_CNTIN_INIT(base, value) (FTM_RMW_CNTIN(base, FTM_CNTIN_INIT_MASK, FTM_CNTIN_INIT(value)))
+#define FTM_BWR_CNTIN_INIT(base, value) (FTM_WR_CNTIN_INIT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_STATUS - Capture And Compare Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_STATUS - Capture And Compare Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
+ * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
+ * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
+ * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
+ * STATUS. Hardware sets the individual channel flags when an event occurs on the
+ * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
+ * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
+ * occurs between the read and write operations, the write operation has no effect;
+ * therefore, CHnF remains set indicating an event has occurred. In this case, a
+ * CHnF interrupt request is not lost due to the clearing sequence for a previous
+ * CHnF. The STATUS register should be used only in Combine mode.
+ */
+/*!
+ * @name Constants and macros for entire FTM_STATUS register
+ */
+/*@{*/
+#define FTM_RD_STATUS(base)      (FTM_STATUS_REG(base))
+#define FTM_WR_STATUS(base, value) (FTM_STATUS_REG(base) = (value))
+#define FTM_RMW_STATUS(base, mask, value) (FTM_WR_STATUS(base, (FTM_RD_STATUS(base) & ~(mask)) | (value)))
+#define FTM_SET_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) |  (value)))
+#define FTM_CLR_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) & ~(value)))
+#define FTM_TOG_STATUS(base, value) (FTM_WR_STATUS(base, FTM_RD_STATUS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_STATUS bitfields
+ */
+
+/*!
+ * @name Register FTM_STATUS, field CH0F[0] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH0F field. */
+#define FTM_RD_STATUS_CH0F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH0F_MASK) >> FTM_STATUS_CH0F_SHIFT)
+#define FTM_BRD_STATUS_CH0F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH0F_SHIFT))
+
+/*! @brief Set the CH0F field to a new value. */
+#define FTM_WR_STATUS_CH0F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH0F(value)))
+#define FTM_BWR_STATUS_CH0F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH0F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH1F[1] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH1F field. */
+#define FTM_RD_STATUS_CH1F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH1F_MASK) >> FTM_STATUS_CH1F_SHIFT)
+#define FTM_BRD_STATUS_CH1F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH1F_SHIFT))
+
+/*! @brief Set the CH1F field to a new value. */
+#define FTM_WR_STATUS_CH1F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH1F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH1F(value)))
+#define FTM_BWR_STATUS_CH1F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH1F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH2F[2] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH2F field. */
+#define FTM_RD_STATUS_CH2F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH2F_MASK) >> FTM_STATUS_CH2F_SHIFT)
+#define FTM_BRD_STATUS_CH2F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH2F_SHIFT))
+
+/*! @brief Set the CH2F field to a new value. */
+#define FTM_WR_STATUS_CH2F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH2F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH2F(value)))
+#define FTM_BWR_STATUS_CH2F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH2F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH3F[3] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH3F field. */
+#define FTM_RD_STATUS_CH3F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH3F_MASK) >> FTM_STATUS_CH3F_SHIFT)
+#define FTM_BRD_STATUS_CH3F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH3F_SHIFT))
+
+/*! @brief Set the CH3F field to a new value. */
+#define FTM_WR_STATUS_CH3F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH3F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH3F(value)))
+#define FTM_BWR_STATUS_CH3F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH3F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH4F[4] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH4F field. */
+#define FTM_RD_STATUS_CH4F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH4F_MASK) >> FTM_STATUS_CH4F_SHIFT)
+#define FTM_BRD_STATUS_CH4F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH4F_SHIFT))
+
+/*! @brief Set the CH4F field to a new value. */
+#define FTM_WR_STATUS_CH4F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH4F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH4F(value)))
+#define FTM_BWR_STATUS_CH4F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH4F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH5F[5] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH5F field. */
+#define FTM_RD_STATUS_CH5F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH5F_MASK) >> FTM_STATUS_CH5F_SHIFT)
+#define FTM_BRD_STATUS_CH5F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH5F_SHIFT))
+
+/*! @brief Set the CH5F field to a new value. */
+#define FTM_WR_STATUS_CH5F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH5F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH6F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH5F(value)))
+#define FTM_BWR_STATUS_CH5F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH5F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH6F[6] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH6F field. */
+#define FTM_RD_STATUS_CH6F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH6F_MASK) >> FTM_STATUS_CH6F_SHIFT)
+#define FTM_BRD_STATUS_CH6F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH6F_SHIFT))
+
+/*! @brief Set the CH6F field to a new value. */
+#define FTM_WR_STATUS_CH6F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH6F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH7F_MASK), FTM_STATUS_CH6F(value)))
+#define FTM_BWR_STATUS_CH6F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH6F_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_STATUS, field CH7F[7] (W1C)
+ *
+ * See the register description.
+ *
+ * Values:
+ * - 0b0 - No channel event has occurred.
+ * - 0b1 - A channel event has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_STATUS_CH7F field. */
+#define FTM_RD_STATUS_CH7F(base) ((FTM_STATUS_REG(base) & FTM_STATUS_CH7F_MASK) >> FTM_STATUS_CH7F_SHIFT)
+#define FTM_BRD_STATUS_CH7F(base) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH7F_SHIFT))
+
+/*! @brief Set the CH7F field to a new value. */
+#define FTM_WR_STATUS_CH7F(base, value) (FTM_RMW_STATUS(base, (FTM_STATUS_CH7F_MASK | FTM_STATUS_CH0F_MASK | FTM_STATUS_CH1F_MASK | FTM_STATUS_CH2F_MASK | FTM_STATUS_CH3F_MASK | FTM_STATUS_CH4F_MASK | FTM_STATUS_CH5F_MASK | FTM_STATUS_CH6F_MASK), FTM_STATUS_CH7F(value)))
+#define FTM_BWR_STATUS_CH7F(base, value) (BITBAND_ACCESS32(&FTM_STATUS_REG(base), FTM_STATUS_CH7F_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_MODE - Features Mode Selection
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_MODE - Features Mode Selection (RW)
+ *
+ * Reset value: 0x00000004U
+ *
+ * This register contains the global enable bit for FTM-specific features and
+ * the control bits used to configure: Fault control mode and interrupt Capture
+ * Test mode PWM synchronization Write protection Channel output initialization
+ * These controls relate to all channels within this module.
+ */
+/*!
+ * @name Constants and macros for entire FTM_MODE register
+ */
+/*@{*/
+#define FTM_RD_MODE(base)        (FTM_MODE_REG(base))
+#define FTM_WR_MODE(base, value) (FTM_MODE_REG(base) = (value))
+#define FTM_RMW_MODE(base, mask, value) (FTM_WR_MODE(base, (FTM_RD_MODE(base) & ~(mask)) | (value)))
+#define FTM_SET_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) |  (value)))
+#define FTM_CLR_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) & ~(value)))
+#define FTM_TOG_MODE(base, value) (FTM_WR_MODE(base, FTM_RD_MODE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_MODE bitfields
+ */
+
+/*!
+ * @name Register FTM_MODE, field FTMEN[0] (RW)
+ *
+ * This field is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Only the TPM-compatible registers (first set of registers) can be
+ *     used without any restriction. Do not use the FTM-specific registers.
+ * - 0b1 - All registers including the FTM-specific registers (second set of
+ *     registers) are available for use with no restrictions.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FTMEN field. */
+#define FTM_RD_MODE_FTMEN(base) ((FTM_MODE_REG(base) & FTM_MODE_FTMEN_MASK) >> FTM_MODE_FTMEN_SHIFT)
+#define FTM_BRD_MODE_FTMEN(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FTMEN_SHIFT))
+
+/*! @brief Set the FTMEN field to a new value. */
+#define FTM_WR_MODE_FTMEN(base, value) (FTM_RMW_MODE(base, FTM_MODE_FTMEN_MASK, FTM_MODE_FTMEN(value)))
+#define FTM_BWR_MODE_FTMEN(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FTMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field INIT[1] (RW)
+ *
+ * When a 1 is written to INIT bit the channels output is initialized according
+ * to the state of their corresponding bit in the OUTINIT register. Writing a 0
+ * to INIT bit has no effect. The INIT bit is always read as 0.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_INIT field. */
+#define FTM_RD_MODE_INIT(base) ((FTM_MODE_REG(base) & FTM_MODE_INIT_MASK) >> FTM_MODE_INIT_SHIFT)
+#define FTM_BRD_MODE_INIT(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_INIT_SHIFT))
+
+/*! @brief Set the INIT field to a new value. */
+#define FTM_WR_MODE_INIT(base, value) (FTM_RMW_MODE(base, FTM_MODE_INIT_MASK, FTM_MODE_INIT(value)))
+#define FTM_BWR_MODE_INIT(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_INIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field WPDIS[2] (RW)
+ *
+ * When write protection is enabled (WPDIS = 0), write protected bits cannot be
+ * written. When write protection is disabled (WPDIS = 1), write protected bits
+ * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
+ * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
+ * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
+ *
+ * Values:
+ * - 0b0 - Write protection is enabled.
+ * - 0b1 - Write protection is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_WPDIS field. */
+#define FTM_RD_MODE_WPDIS(base) ((FTM_MODE_REG(base) & FTM_MODE_WPDIS_MASK) >> FTM_MODE_WPDIS_SHIFT)
+#define FTM_BRD_MODE_WPDIS(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_WPDIS_SHIFT))
+
+/*! @brief Set the WPDIS field to a new value. */
+#define FTM_WR_MODE_WPDIS(base, value) (FTM_RMW_MODE(base, FTM_MODE_WPDIS_MASK, FTM_MODE_WPDIS(value)))
+#define FTM_BWR_MODE_WPDIS(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_WPDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field PWMSYNC[3] (RW)
+ *
+ * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
+ * synchronization. See PWM synchronization. The PWMSYNC bit configures the
+ * synchronization when SYNCMODE is 0.
+ *
+ * Values:
+ * - 0b0 - No restrictions. Software and hardware triggers can be used by MOD,
+ *     CnV, OUTMASK, and FTM counter synchronization.
+ * - 0b1 - Software trigger can only be used by MOD and CnV synchronization, and
+ *     hardware triggers can only be used by OUTMASK and FTM counter
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_PWMSYNC field. */
+#define FTM_RD_MODE_PWMSYNC(base) ((FTM_MODE_REG(base) & FTM_MODE_PWMSYNC_MASK) >> FTM_MODE_PWMSYNC_SHIFT)
+#define FTM_BRD_MODE_PWMSYNC(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_PWMSYNC_SHIFT))
+
+/*! @brief Set the PWMSYNC field to a new value. */
+#define FTM_WR_MODE_PWMSYNC(base, value) (FTM_RMW_MODE(base, FTM_MODE_PWMSYNC_MASK, FTM_MODE_PWMSYNC(value)))
+#define FTM_BWR_MODE_PWMSYNC(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_PWMSYNC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field CAPTEST[4] (RW)
+ *
+ * Enables the capture test mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Capture test mode is disabled.
+ * - 0b1 - Capture test mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_CAPTEST field. */
+#define FTM_RD_MODE_CAPTEST(base) ((FTM_MODE_REG(base) & FTM_MODE_CAPTEST_MASK) >> FTM_MODE_CAPTEST_SHIFT)
+#define FTM_BRD_MODE_CAPTEST(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_CAPTEST_SHIFT))
+
+/*! @brief Set the CAPTEST field to a new value. */
+#define FTM_WR_MODE_CAPTEST(base, value) (FTM_RMW_MODE(base, FTM_MODE_CAPTEST_MASK, FTM_MODE_CAPTEST(value)))
+#define FTM_BWR_MODE_CAPTEST(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_CAPTEST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field FAULTM[6:5] (RW)
+ *
+ * Defines the FTM fault control mode. This field is write protected. It can be
+ * written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b00 - Fault control is disabled for all channels.
+ * - 0b01 - Fault control is enabled for even channels only (channels 0, 2, 4,
+ *     and 6), and the selected mode is the manual fault clearing.
+ * - 0b10 - Fault control is enabled for all channels, and the selected mode is
+ *     the manual fault clearing.
+ * - 0b11 - Fault control is enabled for all channels, and the selected mode is
+ *     the automatic fault clearing.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FAULTM field. */
+#define FTM_RD_MODE_FAULTM(base) ((FTM_MODE_REG(base) & FTM_MODE_FAULTM_MASK) >> FTM_MODE_FAULTM_SHIFT)
+#define FTM_BRD_MODE_FAULTM(base) (FTM_RD_MODE_FAULTM(base))
+
+/*! @brief Set the FAULTM field to a new value. */
+#define FTM_WR_MODE_FAULTM(base, value) (FTM_RMW_MODE(base, FTM_MODE_FAULTM_MASK, FTM_MODE_FAULTM(value)))
+#define FTM_BWR_MODE_FAULTM(base, value) (FTM_WR_MODE_FAULTM(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_MODE, field FAULTIE[7] (RW)
+ *
+ * Enables the generation of an interrupt when a fault is detected by FTM and
+ * the FTM fault control is enabled.
+ *
+ * Values:
+ * - 0b0 - Fault control interrupt is disabled.
+ * - 0b1 - Fault control interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_MODE_FAULTIE field. */
+#define FTM_RD_MODE_FAULTIE(base) ((FTM_MODE_REG(base) & FTM_MODE_FAULTIE_MASK) >> FTM_MODE_FAULTIE_SHIFT)
+#define FTM_BRD_MODE_FAULTIE(base) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FAULTIE_SHIFT))
+
+/*! @brief Set the FAULTIE field to a new value. */
+#define FTM_WR_MODE_FAULTIE(base, value) (FTM_RMW_MODE(base, FTM_MODE_FAULTIE_MASK, FTM_MODE_FAULTIE(value)))
+#define FTM_BWR_MODE_FAULTIE(base, value) (BITBAND_ACCESS32(&FTM_MODE_REG(base), FTM_MODE_FAULTIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SYNC - Synchronization
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SYNC - Synchronization (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the PWM synchronization. A synchronization event can
+ * perform the synchronized update of MOD, CV, and OUTMASK registers with the
+ * value of their write buffer and the FTM counter initialization. The software
+ * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
+ * potential conflict if used together when SYNCMODE = 0. Use only hardware or
+ * software triggers but not both at the same time, otherwise unpredictable behavior
+ * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
+ * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
+ * all enabled channels simultaneously. The use of the loading point selection
+ * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
+ * bits, is likely to result in unpredictable behavior. The synchronization
+ * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
+ * register) bits. See PWM synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SYNC register
+ */
+/*@{*/
+#define FTM_RD_SYNC(base)        (FTM_SYNC_REG(base))
+#define FTM_WR_SYNC(base, value) (FTM_SYNC_REG(base) = (value))
+#define FTM_RMW_SYNC(base, mask, value) (FTM_WR_SYNC(base, (FTM_RD_SYNC(base) & ~(mask)) | (value)))
+#define FTM_SET_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) |  (value)))
+#define FTM_CLR_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) & ~(value)))
+#define FTM_TOG_SYNC(base, value) (FTM_WR_SYNC(base, FTM_RD_SYNC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SYNC bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNC, field CNTMIN[0] (RW)
+ *
+ * Selects the minimum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMIN is one, the selected loading point is when the
+ * FTM counter reaches its minimum value (CNTIN register).
+ *
+ * Values:
+ * - 0b0 - The minimum loading point is disabled.
+ * - 0b1 - The minimum loading point is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_CNTMIN field. */
+#define FTM_RD_SYNC_CNTMIN(base) ((FTM_SYNC_REG(base) & FTM_SYNC_CNTMIN_MASK) >> FTM_SYNC_CNTMIN_SHIFT)
+#define FTM_BRD_SYNC_CNTMIN(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMIN_SHIFT))
+
+/*! @brief Set the CNTMIN field to a new value. */
+#define FTM_WR_SYNC_CNTMIN(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_CNTMIN_MASK, FTM_SYNC_CNTMIN(value)))
+#define FTM_BWR_SYNC_CNTMIN(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMIN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field CNTMAX[1] (RW)
+ *
+ * Selects the maximum loading point to PWM synchronization. See Boundary cycle
+ * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
+ * counter reaches its maximum value (MOD register).
+ *
+ * Values:
+ * - 0b0 - The maximum loading point is disabled.
+ * - 0b1 - The maximum loading point is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_CNTMAX field. */
+#define FTM_RD_SYNC_CNTMAX(base) ((FTM_SYNC_REG(base) & FTM_SYNC_CNTMAX_MASK) >> FTM_SYNC_CNTMAX_SHIFT)
+#define FTM_BRD_SYNC_CNTMAX(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMAX_SHIFT))
+
+/*! @brief Set the CNTMAX field to a new value. */
+#define FTM_WR_SYNC_CNTMAX(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_CNTMAX_MASK, FTM_SYNC_CNTMAX(value)))
+#define FTM_BWR_SYNC_CNTMAX(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_CNTMAX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field REINIT[2] (RW)
+ *
+ * Determines if the FTM counter is reinitialized when the selected trigger for
+ * the synchronization is detected. The REINIT bit configures the synchronization
+ * when SYNCMODE is zero.
+ *
+ * Values:
+ * - 0b0 - FTM counter continues to count normally.
+ * - 0b1 - FTM counter is updated with its initial value when the selected
+ *     trigger is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_REINIT field. */
+#define FTM_RD_SYNC_REINIT(base) ((FTM_SYNC_REG(base) & FTM_SYNC_REINIT_MASK) >> FTM_SYNC_REINIT_SHIFT)
+#define FTM_BRD_SYNC_REINIT(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_REINIT_SHIFT))
+
+/*! @brief Set the REINIT field to a new value. */
+#define FTM_WR_SYNC_REINIT(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_REINIT_MASK, FTM_SYNC_REINIT(value)))
+#define FTM_BWR_SYNC_REINIT(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_REINIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
+ *
+ * Selects when the OUTMASK register is updated with the value of its buffer.
+ *
+ * Values:
+ * - 0b0 - OUTMASK register is updated with the value of its buffer in all
+ *     rising edges of the system clock.
+ * - 0b1 - OUTMASK register is updated with the value of its buffer only by the
+ *     PWM synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */
+#define FTM_RD_SYNC_SYNCHOM(base) ((FTM_SYNC_REG(base) & FTM_SYNC_SYNCHOM_MASK) >> FTM_SYNC_SYNCHOM_SHIFT)
+#define FTM_BRD_SYNC_SYNCHOM(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SYNCHOM_SHIFT))
+
+/*! @brief Set the SYNCHOM field to a new value. */
+#define FTM_WR_SYNC_SYNCHOM(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_SYNCHOM_MASK, FTM_SYNC_SYNCHOM(value)))
+#define FTM_BWR_SYNC_SYNCHOM(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SYNCHOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG0[4] (RW)
+ *
+ * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
+ * occurs when a rising edge is detected at the trigger 0 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG0 field. */
+#define FTM_RD_SYNC_TRIG0(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG0_MASK) >> FTM_SYNC_TRIG0_SHIFT)
+#define FTM_BRD_SYNC_TRIG0(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG0_SHIFT))
+
+/*! @brief Set the TRIG0 field to a new value. */
+#define FTM_WR_SYNC_TRIG0(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG0_MASK, FTM_SYNC_TRIG0(value)))
+#define FTM_BWR_SYNC_TRIG0(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG1[5] (RW)
+ *
+ * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
+ * happens when a rising edge is detected at the trigger 1 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG1 field. */
+#define FTM_RD_SYNC_TRIG1(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG1_MASK) >> FTM_SYNC_TRIG1_SHIFT)
+#define FTM_BRD_SYNC_TRIG1(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG1_SHIFT))
+
+/*! @brief Set the TRIG1 field to a new value. */
+#define FTM_WR_SYNC_TRIG1(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG1_MASK, FTM_SYNC_TRIG1(value)))
+#define FTM_BWR_SYNC_TRIG1(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field TRIG2[6] (RW)
+ *
+ * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
+ * happens when a rising edge is detected at the trigger 2 input signal.
+ *
+ * Values:
+ * - 0b0 - Trigger is disabled.
+ * - 0b1 - Trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_TRIG2 field. */
+#define FTM_RD_SYNC_TRIG2(base) ((FTM_SYNC_REG(base) & FTM_SYNC_TRIG2_MASK) >> FTM_SYNC_TRIG2_SHIFT)
+#define FTM_BRD_SYNC_TRIG2(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG2_SHIFT))
+
+/*! @brief Set the TRIG2 field to a new value. */
+#define FTM_WR_SYNC_TRIG2(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_TRIG2_MASK, FTM_SYNC_TRIG2(value)))
+#define FTM_BWR_SYNC_TRIG2(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_TRIG2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNC, field SWSYNC[7] (RW)
+ *
+ * Selects the software trigger as the PWM synchronization trigger. The software
+ * trigger happens when a 1 is written to SWSYNC bit.
+ *
+ * Values:
+ * - 0b0 - Software trigger is not selected.
+ * - 0b1 - Software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNC_SWSYNC field. */
+#define FTM_RD_SYNC_SWSYNC(base) ((FTM_SYNC_REG(base) & FTM_SYNC_SWSYNC_MASK) >> FTM_SYNC_SWSYNC_SHIFT)
+#define FTM_BRD_SYNC_SWSYNC(base) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SWSYNC_SHIFT))
+
+/*! @brief Set the SWSYNC field to a new value. */
+#define FTM_WR_SYNC_SWSYNC(base, value) (FTM_RMW_SYNC(base, FTM_SYNC_SWSYNC_MASK, FTM_SYNC_SWSYNC(value)))
+#define FTM_BWR_SYNC_SWSYNC(base, value) (BITBAND_ACCESS32(&FTM_SYNC_REG(base), FTM_SYNC_SWSYNC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_OUTINIT - Initial State For Channels Output
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_OUTINIT - Initial State For Channels Output (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire FTM_OUTINIT register
+ */
+/*@{*/
+#define FTM_RD_OUTINIT(base)     (FTM_OUTINIT_REG(base))
+#define FTM_WR_OUTINIT(base, value) (FTM_OUTINIT_REG(base) = (value))
+#define FTM_RMW_OUTINIT(base, mask, value) (FTM_WR_OUTINIT(base, (FTM_RD_OUTINIT(base) & ~(mask)) | (value)))
+#define FTM_SET_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) |  (value)))
+#define FTM_CLR_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) & ~(value)))
+#define FTM_TOG_OUTINIT(base, value) (FTM_WR_OUTINIT(base, FTM_RD_OUTINIT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_OUTINIT bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */
+#define FTM_RD_OUTINIT_CH0OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH0OI_MASK) >> FTM_OUTINIT_CH0OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH0OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH0OI_SHIFT))
+
+/*! @brief Set the CH0OI field to a new value. */
+#define FTM_WR_OUTINIT_CH0OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH0OI_MASK, FTM_OUTINIT_CH0OI(value)))
+#define FTM_BWR_OUTINIT_CH0OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH0OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */
+#define FTM_RD_OUTINIT_CH1OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH1OI_MASK) >> FTM_OUTINIT_CH1OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH1OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH1OI_SHIFT))
+
+/*! @brief Set the CH1OI field to a new value. */
+#define FTM_WR_OUTINIT_CH1OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH1OI_MASK, FTM_OUTINIT_CH1OI(value)))
+#define FTM_BWR_OUTINIT_CH1OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH1OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */
+#define FTM_RD_OUTINIT_CH2OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH2OI_MASK) >> FTM_OUTINIT_CH2OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH2OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH2OI_SHIFT))
+
+/*! @brief Set the CH2OI field to a new value. */
+#define FTM_WR_OUTINIT_CH2OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH2OI_MASK, FTM_OUTINIT_CH2OI(value)))
+#define FTM_BWR_OUTINIT_CH2OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH2OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */
+#define FTM_RD_OUTINIT_CH3OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH3OI_MASK) >> FTM_OUTINIT_CH3OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH3OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH3OI_SHIFT))
+
+/*! @brief Set the CH3OI field to a new value. */
+#define FTM_WR_OUTINIT_CH3OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH3OI_MASK, FTM_OUTINIT_CH3OI(value)))
+#define FTM_BWR_OUTINIT_CH3OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH3OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */
+#define FTM_RD_OUTINIT_CH4OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH4OI_MASK) >> FTM_OUTINIT_CH4OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH4OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH4OI_SHIFT))
+
+/*! @brief Set the CH4OI field to a new value. */
+#define FTM_WR_OUTINIT_CH4OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH4OI_MASK, FTM_OUTINIT_CH4OI(value)))
+#define FTM_BWR_OUTINIT_CH4OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH4OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */
+#define FTM_RD_OUTINIT_CH5OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH5OI_MASK) >> FTM_OUTINIT_CH5OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH5OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH5OI_SHIFT))
+
+/*! @brief Set the CH5OI field to a new value. */
+#define FTM_WR_OUTINIT_CH5OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH5OI_MASK, FTM_OUTINIT_CH5OI(value)))
+#define FTM_BWR_OUTINIT_CH5OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH5OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */
+#define FTM_RD_OUTINIT_CH6OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH6OI_MASK) >> FTM_OUTINIT_CH6OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH6OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH6OI_SHIFT))
+
+/*! @brief Set the CH6OI field to a new value. */
+#define FTM_WR_OUTINIT_CH6OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH6OI_MASK, FTM_OUTINIT_CH6OI(value)))
+#define FTM_BWR_OUTINIT_CH6OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH6OI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
+ *
+ * Selects the value that is forced into the channel output when the
+ * initialization occurs.
+ *
+ * Values:
+ * - 0b0 - The initialization value is 0.
+ * - 0b1 - The initialization value is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */
+#define FTM_RD_OUTINIT_CH7OI(base) ((FTM_OUTINIT_REG(base) & FTM_OUTINIT_CH7OI_MASK) >> FTM_OUTINIT_CH7OI_SHIFT)
+#define FTM_BRD_OUTINIT_CH7OI(base) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH7OI_SHIFT))
+
+/*! @brief Set the CH7OI field to a new value. */
+#define FTM_WR_OUTINIT_CH7OI(base, value) (FTM_RMW_OUTINIT(base, FTM_OUTINIT_CH7OI_MASK, FTM_OUTINIT_CH7OI(value)))
+#define FTM_BWR_OUTINIT_CH7OI(base, value) (BITBAND_ACCESS32(&FTM_OUTINIT_REG(base), FTM_OUTINIT_CH7OI_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_OUTMASK - Output Mask
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_OUTMASK - Output Mask (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register provides a mask for each FTM channel. The mask of a channel
+ * determines if its output responds, that is, it is masked or not, when a match
+ * occurs. This feature is used for BLDC control where the PWM signal is presented
+ * to an electric motor at specific times to provide electronic commutation. Any
+ * write to the OUTMASK register, stores the value in its write buffer. The
+ * register is updated with the value of its write buffer according to PWM
+ * synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_OUTMASK register
+ */
+/*@{*/
+#define FTM_RD_OUTMASK(base)     (FTM_OUTMASK_REG(base))
+#define FTM_WR_OUTMASK(base, value) (FTM_OUTMASK_REG(base) = (value))
+#define FTM_RMW_OUTMASK(base, mask, value) (FTM_WR_OUTMASK(base, (FTM_RD_OUTMASK(base) & ~(mask)) | (value)))
+#define FTM_SET_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) |  (value)))
+#define FTM_CLR_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) & ~(value)))
+#define FTM_TOG_OUTMASK(base, value) (FTM_WR_OUTMASK(base, FTM_RD_OUTMASK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_OUTMASK bitfields
+ */
+
+/*!
+ * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */
+#define FTM_RD_OUTMASK_CH0OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH0OM_MASK) >> FTM_OUTMASK_CH0OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH0OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH0OM_SHIFT))
+
+/*! @brief Set the CH0OM field to a new value. */
+#define FTM_WR_OUTMASK_CH0OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH0OM_MASK, FTM_OUTMASK_CH0OM(value)))
+#define FTM_BWR_OUTMASK_CH0OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH0OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */
+#define FTM_RD_OUTMASK_CH1OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH1OM_MASK) >> FTM_OUTMASK_CH1OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH1OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH1OM_SHIFT))
+
+/*! @brief Set the CH1OM field to a new value. */
+#define FTM_WR_OUTMASK_CH1OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH1OM_MASK, FTM_OUTMASK_CH1OM(value)))
+#define FTM_BWR_OUTMASK_CH1OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH1OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */
+#define FTM_RD_OUTMASK_CH2OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH2OM_MASK) >> FTM_OUTMASK_CH2OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH2OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH2OM_SHIFT))
+
+/*! @brief Set the CH2OM field to a new value. */
+#define FTM_WR_OUTMASK_CH2OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH2OM_MASK, FTM_OUTMASK_CH2OM(value)))
+#define FTM_BWR_OUTMASK_CH2OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH2OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */
+#define FTM_RD_OUTMASK_CH3OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH3OM_MASK) >> FTM_OUTMASK_CH3OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH3OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH3OM_SHIFT))
+
+/*! @brief Set the CH3OM field to a new value. */
+#define FTM_WR_OUTMASK_CH3OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH3OM_MASK, FTM_OUTMASK_CH3OM(value)))
+#define FTM_BWR_OUTMASK_CH3OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH3OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */
+#define FTM_RD_OUTMASK_CH4OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH4OM_MASK) >> FTM_OUTMASK_CH4OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH4OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH4OM_SHIFT))
+
+/*! @brief Set the CH4OM field to a new value. */
+#define FTM_WR_OUTMASK_CH4OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH4OM_MASK, FTM_OUTMASK_CH4OM(value)))
+#define FTM_BWR_OUTMASK_CH4OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH4OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */
+#define FTM_RD_OUTMASK_CH5OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH5OM_MASK) >> FTM_OUTMASK_CH5OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH5OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH5OM_SHIFT))
+
+/*! @brief Set the CH5OM field to a new value. */
+#define FTM_WR_OUTMASK_CH5OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH5OM_MASK, FTM_OUTMASK_CH5OM(value)))
+#define FTM_BWR_OUTMASK_CH5OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH5OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */
+#define FTM_RD_OUTMASK_CH6OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH6OM_MASK) >> FTM_OUTMASK_CH6OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH6OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH6OM_SHIFT))
+
+/*! @brief Set the CH6OM field to a new value. */
+#define FTM_WR_OUTMASK_CH6OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH6OM_MASK, FTM_OUTMASK_CH6OM(value)))
+#define FTM_BWR_OUTMASK_CH6OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH6OM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
+ *
+ * Defines if the channel output is masked or unmasked.
+ *
+ * Values:
+ * - 0b0 - Channel output is not masked. It continues to operate normally.
+ * - 0b1 - Channel output is masked. It is forced to its inactive state.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */
+#define FTM_RD_OUTMASK_CH7OM(base) ((FTM_OUTMASK_REG(base) & FTM_OUTMASK_CH7OM_MASK) >> FTM_OUTMASK_CH7OM_SHIFT)
+#define FTM_BRD_OUTMASK_CH7OM(base) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH7OM_SHIFT))
+
+/*! @brief Set the CH7OM field to a new value. */
+#define FTM_WR_OUTMASK_CH7OM(base, value) (FTM_RMW_OUTMASK(base, FTM_OUTMASK_CH7OM_MASK, FTM_OUTMASK_CH7OM(value)))
+#define FTM_BWR_OUTMASK_CH7OM(base, value) (BITBAND_ACCESS32(&FTM_OUTMASK_REG(base), FTM_OUTMASK_CH7OM_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_COMBINE - Function For Linked Channels
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_COMBINE - Function For Linked Channels (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the control bits used to configure the fault control,
+ * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
+ * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
+ * 4, and 6.
+ */
+/*!
+ * @name Constants and macros for entire FTM_COMBINE register
+ */
+/*@{*/
+#define FTM_RD_COMBINE(base)     (FTM_COMBINE_REG(base))
+#define FTM_WR_COMBINE(base, value) (FTM_COMBINE_REG(base) = (value))
+#define FTM_RMW_COMBINE(base, mask, value) (FTM_WR_COMBINE(base, (FTM_RD_COMBINE(base) & ~(mask)) | (value)))
+#define FTM_SET_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) |  (value)))
+#define FTM_CLR_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) & ~(value)))
+#define FTM_TOG_COMBINE(base, value) (FTM_WR_COMBINE(base, FTM_RD_COMBINE(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_COMBINE bitfields
+ */
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */
+#define FTM_RD_COMBINE_COMBINE0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE0_MASK) >> FTM_COMBINE_COMBINE0_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE0_SHIFT))
+
+/*! @brief Set the COMBINE0 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE0_MASK, FTM_COMBINE_COMBINE0(value)))
+#define FTM_BWR_COMBINE_COMBINE0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP0[1] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP0 field. */
+#define FTM_RD_COMBINE_COMP0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP0_MASK) >> FTM_COMBINE_COMP0_SHIFT)
+#define FTM_BRD_COMBINE_COMP0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP0_SHIFT))
+
+/*! @brief Set the COMP0 field to a new value. */
+#define FTM_WR_COMBINE_COMP0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP0_MASK, FTM_COMBINE_COMP0(value)))
+#define FTM_BWR_COMBINE_COMP0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */
+#define FTM_RD_COMBINE_DECAPEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN0_MASK) >> FTM_COMBINE_DECAPEN0_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN0_SHIFT))
+
+/*! @brief Set the DECAPEN0 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN0_MASK, FTM_COMBINE_DECAPEN0(value)))
+#define FTM_BWR_COMBINE_DECAPEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP0[3] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */
+#define FTM_RD_COMBINE_DECAP0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP0_MASK) >> FTM_COMBINE_DECAP0_SHIFT)
+#define FTM_BRD_COMBINE_DECAP0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP0_SHIFT))
+
+/*! @brief Set the DECAP0 field to a new value. */
+#define FTM_WR_COMBINE_DECAP0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP0_MASK, FTM_COMBINE_DECAP0(value)))
+#define FTM_BWR_COMBINE_DECAP0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN0[4] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */
+#define FTM_RD_COMBINE_DTEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN0_MASK) >> FTM_COMBINE_DTEN0_SHIFT)
+#define FTM_BRD_COMBINE_DTEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN0_SHIFT))
+
+/*! @brief Set the DTEN0 field to a new value. */
+#define FTM_WR_COMBINE_DTEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN0_MASK, FTM_COMBINE_DTEN0(value)))
+#define FTM_BWR_COMBINE_DTEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */
+#define FTM_RD_COMBINE_SYNCEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN0_MASK) >> FTM_COMBINE_SYNCEN0_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN0_SHIFT))
+
+/*! @brief Set the SYNCEN0 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN0_MASK, FTM_COMBINE_SYNCEN0(value)))
+#define FTM_BWR_COMBINE_SYNCEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */
+#define FTM_RD_COMBINE_FAULTEN0(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN0_MASK) >> FTM_COMBINE_FAULTEN0_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN0(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN0_SHIFT))
+
+/*! @brief Set the FAULTEN0 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN0(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN0_MASK, FTM_COMBINE_FAULTEN0(value)))
+#define FTM_BWR_COMBINE_FAULTEN0(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */
+#define FTM_RD_COMBINE_COMBINE1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE1_MASK) >> FTM_COMBINE_COMBINE1_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE1_SHIFT))
+
+/*! @brief Set the COMBINE1 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE1_MASK, FTM_COMBINE_COMBINE1(value)))
+#define FTM_BWR_COMBINE_COMBINE1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP1[9] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP1 field. */
+#define FTM_RD_COMBINE_COMP1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP1_MASK) >> FTM_COMBINE_COMP1_SHIFT)
+#define FTM_BRD_COMBINE_COMP1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP1_SHIFT))
+
+/*! @brief Set the COMP1 field to a new value. */
+#define FTM_WR_COMBINE_COMP1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP1_MASK, FTM_COMBINE_COMP1(value)))
+#define FTM_BWR_COMBINE_COMP1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */
+#define FTM_RD_COMBINE_DECAPEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN1_MASK) >> FTM_COMBINE_DECAPEN1_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN1_SHIFT))
+
+/*! @brief Set the DECAPEN1 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN1_MASK, FTM_COMBINE_DECAPEN1(value)))
+#define FTM_BWR_COMBINE_DECAPEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP1[11] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */
+#define FTM_RD_COMBINE_DECAP1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP1_MASK) >> FTM_COMBINE_DECAP1_SHIFT)
+#define FTM_BRD_COMBINE_DECAP1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP1_SHIFT))
+
+/*! @brief Set the DECAP1 field to a new value. */
+#define FTM_WR_COMBINE_DECAP1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP1_MASK, FTM_COMBINE_DECAP1(value)))
+#define FTM_BWR_COMBINE_DECAP1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN1[12] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */
+#define FTM_RD_COMBINE_DTEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN1_MASK) >> FTM_COMBINE_DTEN1_SHIFT)
+#define FTM_BRD_COMBINE_DTEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN1_SHIFT))
+
+/*! @brief Set the DTEN1 field to a new value. */
+#define FTM_WR_COMBINE_DTEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN1_MASK, FTM_COMBINE_DTEN1(value)))
+#define FTM_BWR_COMBINE_DTEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */
+#define FTM_RD_COMBINE_SYNCEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN1_MASK) >> FTM_COMBINE_SYNCEN1_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN1_SHIFT))
+
+/*! @brief Set the SYNCEN1 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN1_MASK, FTM_COMBINE_SYNCEN1(value)))
+#define FTM_BWR_COMBINE_SYNCEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */
+#define FTM_RD_COMBINE_FAULTEN1(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN1_MASK) >> FTM_COMBINE_FAULTEN1_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN1(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN1_SHIFT))
+
+/*! @brief Set the FAULTEN1 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN1(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN1_MASK, FTM_COMBINE_FAULTEN1(value)))
+#define FTM_BWR_COMBINE_FAULTEN1(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */
+#define FTM_RD_COMBINE_COMBINE2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE2_MASK) >> FTM_COMBINE_COMBINE2_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE2_SHIFT))
+
+/*! @brief Set the COMBINE2 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE2_MASK, FTM_COMBINE_COMBINE2(value)))
+#define FTM_BWR_COMBINE_COMBINE2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP2[17] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP2 field. */
+#define FTM_RD_COMBINE_COMP2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP2_MASK) >> FTM_COMBINE_COMP2_SHIFT)
+#define FTM_BRD_COMBINE_COMP2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP2_SHIFT))
+
+/*! @brief Set the COMP2 field to a new value. */
+#define FTM_WR_COMBINE_COMP2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP2_MASK, FTM_COMBINE_COMP2(value)))
+#define FTM_BWR_COMBINE_COMP2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */
+#define FTM_RD_COMBINE_DECAPEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN2_MASK) >> FTM_COMBINE_DECAPEN2_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN2_SHIFT))
+
+/*! @brief Set the DECAPEN2 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN2_MASK, FTM_COMBINE_DECAPEN2(value)))
+#define FTM_BWR_COMBINE_DECAPEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP2[19] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */
+#define FTM_RD_COMBINE_DECAP2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP2_MASK) >> FTM_COMBINE_DECAP2_SHIFT)
+#define FTM_BRD_COMBINE_DECAP2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP2_SHIFT))
+
+/*! @brief Set the DECAP2 field to a new value. */
+#define FTM_WR_COMBINE_DECAP2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP2_MASK, FTM_COMBINE_DECAP2(value)))
+#define FTM_BWR_COMBINE_DECAP2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN2[20] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */
+#define FTM_RD_COMBINE_DTEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN2_MASK) >> FTM_COMBINE_DTEN2_SHIFT)
+#define FTM_BRD_COMBINE_DTEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN2_SHIFT))
+
+/*! @brief Set the DTEN2 field to a new value. */
+#define FTM_WR_COMBINE_DTEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN2_MASK, FTM_COMBINE_DTEN2(value)))
+#define FTM_BWR_COMBINE_DTEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */
+#define FTM_RD_COMBINE_SYNCEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN2_MASK) >> FTM_COMBINE_SYNCEN2_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN2_SHIFT))
+
+/*! @brief Set the SYNCEN2 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN2_MASK, FTM_COMBINE_SYNCEN2(value)))
+#define FTM_BWR_COMBINE_SYNCEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */
+#define FTM_RD_COMBINE_FAULTEN2(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN2_MASK) >> FTM_COMBINE_FAULTEN2_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN2(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN2_SHIFT))
+
+/*! @brief Set the FAULTEN2 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN2(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN2_MASK, FTM_COMBINE_FAULTEN2(value)))
+#define FTM_BWR_COMBINE_FAULTEN2(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
+ *
+ * Enables the combine feature for channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Channels (n) and (n+1) are independent.
+ * - 0b1 - Channels (n) and (n+1) are combined.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */
+#define FTM_RD_COMBINE_COMBINE3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMBINE3_MASK) >> FTM_COMBINE_COMBINE3_SHIFT)
+#define FTM_BRD_COMBINE_COMBINE3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE3_SHIFT))
+
+/*! @brief Set the COMBINE3 field to a new value. */
+#define FTM_WR_COMBINE_COMBINE3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMBINE3_MASK, FTM_COMBINE_COMBINE3(value)))
+#define FTM_BWR_COMBINE_COMBINE3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMBINE3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field COMP3[25] (RW)
+ *
+ * Enables Complementary mode for the combined channels. In Complementary mode
+ * the channel (n+1) output is the inverse of the channel (n) output. This field
+ * is write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel (n+1) output is the same as the channel (n) output.
+ * - 0b1 - The channel (n+1) output is the complement of the channel (n) output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_COMP3 field. */
+#define FTM_RD_COMBINE_COMP3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_COMP3_MASK) >> FTM_COMBINE_COMP3_SHIFT)
+#define FTM_BRD_COMBINE_COMP3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP3_SHIFT))
+
+/*! @brief Set the COMP3 field to a new value. */
+#define FTM_WR_COMBINE_COMP3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_COMP3_MASK, FTM_COMBINE_COMP3(value)))
+#define FTM_BWR_COMBINE_COMP3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_COMP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
+ *
+ * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
+ * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
+ * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
+ * when FTMEN = 1. This field is write protected. It can be written only when
+ * MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The Dual Edge Capture mode in this pair of channels is disabled.
+ * - 0b1 - The Dual Edge Capture mode in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */
+#define FTM_RD_COMBINE_DECAPEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAPEN3_MASK) >> FTM_COMBINE_DECAPEN3_SHIFT)
+#define FTM_BRD_COMBINE_DECAPEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN3_SHIFT))
+
+/*! @brief Set the DECAPEN3 field to a new value. */
+#define FTM_WR_COMBINE_DECAPEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAPEN3_MASK, FTM_COMBINE_DECAPEN3(value)))
+#define FTM_BWR_COMBINE_DECAPEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAPEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DECAP3[27] (RW)
+ *
+ * Enables the capture of the FTM counter value according to the channel (n)
+ * input event and the configuration of the dual edge capture bits. This field
+ * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
+ * hardware if dual edge capture - one-shot mode is selected and when the capture
+ * of channel (n+1) event is made.
+ *
+ * Values:
+ * - 0b0 - The dual edge captures are inactive.
+ * - 0b1 - The dual edge captures are active.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */
+#define FTM_RD_COMBINE_DECAP3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DECAP3_MASK) >> FTM_COMBINE_DECAP3_SHIFT)
+#define FTM_BRD_COMBINE_DECAP3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP3_SHIFT))
+
+/*! @brief Set the DECAP3 field to a new value. */
+#define FTM_WR_COMBINE_DECAP3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DECAP3_MASK, FTM_COMBINE_DECAP3(value)))
+#define FTM_BWR_COMBINE_DECAP3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DECAP3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field DTEN3[28] (RW)
+ *
+ * Enables the deadtime insertion in the channels (n) and (n+1). This field is
+ * write protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The deadtime insertion in this pair of channels is disabled.
+ * - 0b1 - The deadtime insertion in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */
+#define FTM_RD_COMBINE_DTEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_DTEN3_MASK) >> FTM_COMBINE_DTEN3_SHIFT)
+#define FTM_BRD_COMBINE_DTEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN3_SHIFT))
+
+/*! @brief Set the DTEN3 field to a new value. */
+#define FTM_WR_COMBINE_DTEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_DTEN3_MASK, FTM_COMBINE_DTEN3(value)))
+#define FTM_BWR_COMBINE_DTEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_DTEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
+ *
+ * Enables PWM synchronization of registers C(n)V and C(n+1)V.
+ *
+ * Values:
+ * - 0b0 - The PWM synchronization in this pair of channels is disabled.
+ * - 0b1 - The PWM synchronization in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */
+#define FTM_RD_COMBINE_SYNCEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_SYNCEN3_MASK) >> FTM_COMBINE_SYNCEN3_SHIFT)
+#define FTM_BRD_COMBINE_SYNCEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN3_SHIFT))
+
+/*! @brief Set the SYNCEN3 field to a new value. */
+#define FTM_WR_COMBINE_SYNCEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_SYNCEN3_MASK, FTM_COMBINE_SYNCEN3(value)))
+#define FTM_BWR_COMBINE_SYNCEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_SYNCEN3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
+ *
+ * Enables the fault control in channels (n) and (n+1). This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault control in this pair of channels is disabled.
+ * - 0b1 - The fault control in this pair of channels is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */
+#define FTM_RD_COMBINE_FAULTEN3(base) ((FTM_COMBINE_REG(base) & FTM_COMBINE_FAULTEN3_MASK) >> FTM_COMBINE_FAULTEN3_SHIFT)
+#define FTM_BRD_COMBINE_FAULTEN3(base) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN3_SHIFT))
+
+/*! @brief Set the FAULTEN3 field to a new value. */
+#define FTM_WR_COMBINE_FAULTEN3(base, value) (FTM_RMW_COMBINE(base, FTM_COMBINE_FAULTEN3_MASK, FTM_COMBINE_FAULTEN3(value)))
+#define FTM_BWR_COMBINE_FAULTEN3(base, value) (BITBAND_ACCESS32(&FTM_COMBINE_REG(base), FTM_COMBINE_FAULTEN3_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_DEADTIME - Deadtime Insertion Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_DEADTIME - Deadtime Insertion Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the deadtime prescaler factor and deadtime value. All
+ * FTM channels use this clock prescaler and this deadtime value for the deadtime
+ * insertion.
+ */
+/*!
+ * @name Constants and macros for entire FTM_DEADTIME register
+ */
+/*@{*/
+#define FTM_RD_DEADTIME(base)    (FTM_DEADTIME_REG(base))
+#define FTM_WR_DEADTIME(base, value) (FTM_DEADTIME_REG(base) = (value))
+#define FTM_RMW_DEADTIME(base, mask, value) (FTM_WR_DEADTIME(base, (FTM_RD_DEADTIME(base) & ~(mask)) | (value)))
+#define FTM_SET_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) |  (value)))
+#define FTM_CLR_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) & ~(value)))
+#define FTM_TOG_DEADTIME(base, value) (FTM_WR_DEADTIME(base, FTM_RD_DEADTIME(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_DEADTIME bitfields
+ */
+
+/*!
+ * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
+ *
+ * Selects the deadtime insertion value for the deadtime counter. The deadtime
+ * counter is clocked by a scaled version of the system clock. See the description
+ * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
+ * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
+ * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
+ * This pattern continues up to a possible 63 counts. This field is write
+ * protected. It can be written only when MODE[WPDIS] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */
+#define FTM_RD_DEADTIME_DTVAL(base) ((FTM_DEADTIME_REG(base) & FTM_DEADTIME_DTVAL_MASK) >> FTM_DEADTIME_DTVAL_SHIFT)
+#define FTM_BRD_DEADTIME_DTVAL(base) (FTM_RD_DEADTIME_DTVAL(base))
+
+/*! @brief Set the DTVAL field to a new value. */
+#define FTM_WR_DEADTIME_DTVAL(base, value) (FTM_RMW_DEADTIME(base, FTM_DEADTIME_DTVAL_MASK, FTM_DEADTIME_DTVAL(value)))
+#define FTM_BWR_DEADTIME_DTVAL(base, value) (FTM_WR_DEADTIME_DTVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
+ *
+ * Selects the division factor of the system clock. This prescaled clock is used
+ * by the deadtime counter. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0x - Divide the system clock by 1.
+ * - 0b10 - Divide the system clock by 4.
+ * - 0b11 - Divide the system clock by 16.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_DEADTIME_DTPS field. */
+#define FTM_RD_DEADTIME_DTPS(base) ((FTM_DEADTIME_REG(base) & FTM_DEADTIME_DTPS_MASK) >> FTM_DEADTIME_DTPS_SHIFT)
+#define FTM_BRD_DEADTIME_DTPS(base) (FTM_RD_DEADTIME_DTPS(base))
+
+/*! @brief Set the DTPS field to a new value. */
+#define FTM_WR_DEADTIME_DTPS(base, value) (FTM_RMW_DEADTIME(base, FTM_DEADTIME_DTPS_MASK, FTM_DEADTIME_DTPS(value)))
+#define FTM_BWR_DEADTIME_DTPS(base, value) (FTM_WR_DEADTIME_DTPS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_EXTTRIG - FTM External Trigger
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_EXTTRIG - FTM External Trigger (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register: Indicates when a channel trigger was generated Enables the
+ * generation of a trigger when the FTM counter is equal to its initial value
+ * Selects which channels are used in the generation of the channel triggers Several
+ * channels can be selected to generate multiple triggers in one PWM period.
+ * Channels 6 and 7 are not used to generate channel triggers.
+ */
+/*!
+ * @name Constants and macros for entire FTM_EXTTRIG register
+ */
+/*@{*/
+#define FTM_RD_EXTTRIG(base)     (FTM_EXTTRIG_REG(base))
+#define FTM_WR_EXTTRIG(base, value) (FTM_EXTTRIG_REG(base) = (value))
+#define FTM_RMW_EXTTRIG(base, mask, value) (FTM_WR_EXTTRIG(base, (FTM_RD_EXTTRIG(base) & ~(mask)) | (value)))
+#define FTM_SET_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) |  (value)))
+#define FTM_CLR_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) & ~(value)))
+#define FTM_TOG_EXTTRIG(base, value) (FTM_WR_EXTTRIG(base, FTM_RD_EXTTRIG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_EXTTRIG bitfields
+ */
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */
+#define FTM_RD_EXTTRIG_CH2TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH2TRIG_MASK) >> FTM_EXTTRIG_CH2TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH2TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH2TRIG_SHIFT))
+
+/*! @brief Set the CH2TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH2TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH2TRIG_MASK, FTM_EXTTRIG_CH2TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH2TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH2TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */
+#define FTM_RD_EXTTRIG_CH3TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH3TRIG_MASK) >> FTM_EXTTRIG_CH3TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH3TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH3TRIG_SHIFT))
+
+/*! @brief Set the CH3TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH3TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH3TRIG_MASK, FTM_EXTTRIG_CH3TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH3TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH3TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */
+#define FTM_RD_EXTTRIG_CH4TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH4TRIG_MASK) >> FTM_EXTTRIG_CH4TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH4TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH4TRIG_SHIFT))
+
+/*! @brief Set the CH4TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH4TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH4TRIG_MASK, FTM_EXTTRIG_CH4TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH4TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH4TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */
+#define FTM_RD_EXTTRIG_CH5TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH5TRIG_MASK) >> FTM_EXTTRIG_CH5TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH5TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH5TRIG_SHIFT))
+
+/*! @brief Set the CH5TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH5TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH5TRIG_MASK, FTM_EXTTRIG_CH5TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH5TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH5TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */
+#define FTM_RD_EXTTRIG_CH0TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH0TRIG_MASK) >> FTM_EXTTRIG_CH0TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH0TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH0TRIG_SHIFT))
+
+/*! @brief Set the CH0TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH0TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH0TRIG_MASK, FTM_EXTTRIG_CH0TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH0TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH0TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
+ *
+ * Enables the generation of the channel trigger when the FTM counter is equal
+ * to the CnV register.
+ *
+ * Values:
+ * - 0b0 - The generation of the channel trigger is disabled.
+ * - 0b1 - The generation of the channel trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */
+#define FTM_RD_EXTTRIG_CH1TRIG(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_CH1TRIG_MASK) >> FTM_EXTTRIG_CH1TRIG_SHIFT)
+#define FTM_BRD_EXTTRIG_CH1TRIG(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH1TRIG_SHIFT))
+
+/*! @brief Set the CH1TRIG field to a new value. */
+#define FTM_WR_EXTTRIG_CH1TRIG(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_CH1TRIG_MASK, FTM_EXTTRIG_CH1TRIG(value)))
+#define FTM_BWR_EXTTRIG_CH1TRIG(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_CH1TRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
+ *
+ * Enables the generation of the trigger when the FTM counter is equal to the
+ * CNTIN register.
+ *
+ * Values:
+ * - 0b0 - The generation of initialization trigger is disabled.
+ * - 0b1 - The generation of initialization trigger is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */
+#define FTM_RD_EXTTRIG_INITTRIGEN(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_INITTRIGEN_MASK) >> FTM_EXTTRIG_INITTRIGEN_SHIFT)
+#define FTM_BRD_EXTTRIG_INITTRIGEN(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_INITTRIGEN_SHIFT))
+
+/*! @brief Set the INITTRIGEN field to a new value. */
+#define FTM_WR_EXTTRIG_INITTRIGEN(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_INITTRIGEN_MASK, FTM_EXTTRIG_INITTRIGEN(value)))
+#define FTM_BWR_EXTTRIG_INITTRIGEN(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_INITTRIGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
+ *
+ * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
+ * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
+ * has no effect. If another channel trigger is generated before the clearing
+ * sequence is completed, the sequence is reset so TRIGF remains set after the clear
+ * sequence is completed for the earlier TRIGF.
+ *
+ * Values:
+ * - 0b0 - No channel trigger was generated.
+ * - 0b1 - A channel trigger was generated.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */
+#define FTM_RD_EXTTRIG_TRIGF(base) ((FTM_EXTTRIG_REG(base) & FTM_EXTTRIG_TRIGF_MASK) >> FTM_EXTTRIG_TRIGF_SHIFT)
+#define FTM_BRD_EXTTRIG_TRIGF(base) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_TRIGF_SHIFT))
+
+/*! @brief Set the TRIGF field to a new value. */
+#define FTM_WR_EXTTRIG_TRIGF(base, value) (FTM_RMW_EXTTRIG(base, FTM_EXTTRIG_TRIGF_MASK, FTM_EXTTRIG_TRIGF(value)))
+#define FTM_BWR_EXTTRIG_TRIGF(base, value) (BITBAND_ACCESS32(&FTM_EXTTRIG_REG(base), FTM_EXTTRIG_TRIGF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_POL - Channels Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_POL - Channels Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the output polarity of the FTM channels. The safe value
+ * that is driven in a channel output when the fault control is enabled and a
+ * fault condition is detected is the inactive state of the channel. That is, the
+ * safe value of a channel is the value of its POL bit.
+ */
+/*!
+ * @name Constants and macros for entire FTM_POL register
+ */
+/*@{*/
+#define FTM_RD_POL(base)         (FTM_POL_REG(base))
+#define FTM_WR_POL(base, value)  (FTM_POL_REG(base) = (value))
+#define FTM_RMW_POL(base, mask, value) (FTM_WR_POL(base, (FTM_RD_POL(base) & ~(mask)) | (value)))
+#define FTM_SET_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) |  (value)))
+#define FTM_CLR_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) & ~(value)))
+#define FTM_TOG_POL(base, value) (FTM_WR_POL(base, FTM_RD_POL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_POL bitfields
+ */
+
+/*!
+ * @name Register FTM_POL, field POL0[0] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL0 field. */
+#define FTM_RD_POL_POL0(base) ((FTM_POL_REG(base) & FTM_POL_POL0_MASK) >> FTM_POL_POL0_SHIFT)
+#define FTM_BRD_POL_POL0(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL0_SHIFT))
+
+/*! @brief Set the POL0 field to a new value. */
+#define FTM_WR_POL_POL0(base, value) (FTM_RMW_POL(base, FTM_POL_POL0_MASK, FTM_POL_POL0(value)))
+#define FTM_BWR_POL_POL0(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL1[1] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL1 field. */
+#define FTM_RD_POL_POL1(base) ((FTM_POL_REG(base) & FTM_POL_POL1_MASK) >> FTM_POL_POL1_SHIFT)
+#define FTM_BRD_POL_POL1(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL1_SHIFT))
+
+/*! @brief Set the POL1 field to a new value. */
+#define FTM_WR_POL_POL1(base, value) (FTM_RMW_POL(base, FTM_POL_POL1_MASK, FTM_POL_POL1(value)))
+#define FTM_BWR_POL_POL1(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL2[2] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL2 field. */
+#define FTM_RD_POL_POL2(base) ((FTM_POL_REG(base) & FTM_POL_POL2_MASK) >> FTM_POL_POL2_SHIFT)
+#define FTM_BRD_POL_POL2(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL2_SHIFT))
+
+/*! @brief Set the POL2 field to a new value. */
+#define FTM_WR_POL_POL2(base, value) (FTM_RMW_POL(base, FTM_POL_POL2_MASK, FTM_POL_POL2(value)))
+#define FTM_BWR_POL_POL2(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL3[3] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL3 field. */
+#define FTM_RD_POL_POL3(base) ((FTM_POL_REG(base) & FTM_POL_POL3_MASK) >> FTM_POL_POL3_SHIFT)
+#define FTM_BRD_POL_POL3(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL3_SHIFT))
+
+/*! @brief Set the POL3 field to a new value. */
+#define FTM_WR_POL_POL3(base, value) (FTM_RMW_POL(base, FTM_POL_POL3_MASK, FTM_POL_POL3(value)))
+#define FTM_BWR_POL_POL3(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL4[4] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL4 field. */
+#define FTM_RD_POL_POL4(base) ((FTM_POL_REG(base) & FTM_POL_POL4_MASK) >> FTM_POL_POL4_SHIFT)
+#define FTM_BRD_POL_POL4(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL4_SHIFT))
+
+/*! @brief Set the POL4 field to a new value. */
+#define FTM_WR_POL_POL4(base, value) (FTM_RMW_POL(base, FTM_POL_POL4_MASK, FTM_POL_POL4(value)))
+#define FTM_BWR_POL_POL4(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL5[5] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL5 field. */
+#define FTM_RD_POL_POL5(base) ((FTM_POL_REG(base) & FTM_POL_POL5_MASK) >> FTM_POL_POL5_SHIFT)
+#define FTM_BRD_POL_POL5(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL5_SHIFT))
+
+/*! @brief Set the POL5 field to a new value. */
+#define FTM_WR_POL_POL5(base, value) (FTM_RMW_POL(base, FTM_POL_POL5_MASK, FTM_POL_POL5(value)))
+#define FTM_BWR_POL_POL5(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL6[6] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL6 field. */
+#define FTM_RD_POL_POL6(base) ((FTM_POL_REG(base) & FTM_POL_POL6_MASK) >> FTM_POL_POL6_SHIFT)
+#define FTM_BRD_POL_POL6(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL6_SHIFT))
+
+/*! @brief Set the POL6 field to a new value. */
+#define FTM_WR_POL_POL6(base, value) (FTM_RMW_POL(base, FTM_POL_POL6_MASK, FTM_POL_POL6(value)))
+#define FTM_BWR_POL_POL6(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_POL, field POL7[7] (RW)
+ *
+ * Defines the polarity of the channel output. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The channel polarity is active high.
+ * - 0b1 - The channel polarity is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_POL_POL7 field. */
+#define FTM_RD_POL_POL7(base) ((FTM_POL_REG(base) & FTM_POL_POL7_MASK) >> FTM_POL_POL7_SHIFT)
+#define FTM_BRD_POL_POL7(base) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL7_SHIFT))
+
+/*! @brief Set the POL7 field to a new value. */
+#define FTM_WR_POL_POL7(base, value) (FTM_RMW_POL(base, FTM_POL_POL7_MASK, FTM_POL_POL7(value)))
+#define FTM_BWR_POL_POL7(base, value) (BITBAND_ACCESS32(&FTM_POL_REG(base), FTM_POL_POL7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FMS - Fault Mode Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FMS - Fault Mode Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the fault detection flags, write protection enable
+ * bit, and the logic OR of the enabled fault inputs.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FMS register
+ */
+/*@{*/
+#define FTM_RD_FMS(base)         (FTM_FMS_REG(base))
+#define FTM_WR_FMS(base, value)  (FTM_FMS_REG(base) = (value))
+#define FTM_RMW_FMS(base, mask, value) (FTM_WR_FMS(base, (FTM_RD_FMS(base) & ~(mask)) | (value)))
+#define FTM_SET_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) |  (value)))
+#define FTM_CLR_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) & ~(value)))
+#define FTM_TOG_FMS(base, value) (FTM_WR_FMS(base, FTM_RD_FMS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FMS bitfields
+ */
+
+/*!
+ * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
+ * by reading the FMS register while FAULTF0 is set and then writing a 0 to
+ * FAULTF0 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF0 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF0 field. */
+#define FTM_RD_FMS_FAULTF0(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF0_MASK) >> FTM_FMS_FAULTF0_SHIFT)
+#define FTM_BRD_FMS_FAULTF0(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF0_SHIFT))
+
+/*! @brief Set the FAULTF0 field to a new value. */
+#define FTM_WR_FMS_FAULTF0(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF0_MASK, FTM_FMS_FAULTF0(value)))
+#define FTM_BWR_FMS_FAULTF0(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
+ * by reading the FMS register while FAULTF1 is set and then writing a 0 to
+ * FAULTF1 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF1 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF1 field. */
+#define FTM_RD_FMS_FAULTF1(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF1_MASK) >> FTM_FMS_FAULTF1_SHIFT)
+#define FTM_BRD_FMS_FAULTF1(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF1_SHIFT))
+
+/*! @brief Set the FAULTF1 field to a new value. */
+#define FTM_WR_FMS_FAULTF1(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF1_MASK, FTM_FMS_FAULTF1(value)))
+#define FTM_BWR_FMS_FAULTF1(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
+ * by reading the FMS register while FAULTF2 is set and then writing a 0 to
+ * FAULTF2 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF2 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF2 field. */
+#define FTM_RD_FMS_FAULTF2(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF2_MASK) >> FTM_FMS_FAULTF2_SHIFT)
+#define FTM_BRD_FMS_FAULTF2(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF2_SHIFT))
+
+/*! @brief Set the FAULTF2 field to a new value. */
+#define FTM_WR_FMS_FAULTF2(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF2_MASK, FTM_FMS_FAULTF2(value)))
+#define FTM_BWR_FMS_FAULTF2(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
+ *
+ * Set by hardware when fault control is enabled, the corresponding fault input
+ * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
+ * by reading the FMS register while FAULTF3 is set and then writing a 0 to
+ * FAULTF3 while there is no existing fault condition at the corresponding fault
+ * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
+ * FAULTF bit is cleared. If another fault condition is detected at the corresponding
+ * fault input before the clearing sequence is completed, the sequence is reset
+ * so FAULTF3 remains set after the clearing sequence is completed for the
+ * earlier fault condition.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected at the fault input.
+ * - 0b1 - A fault condition was detected at the fault input.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF3 field. */
+#define FTM_RD_FMS_FAULTF3(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF3_MASK) >> FTM_FMS_FAULTF3_SHIFT)
+#define FTM_BRD_FMS_FAULTF3(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF3_SHIFT))
+
+/*! @brief Set the FAULTF3 field to a new value. */
+#define FTM_WR_FMS_FAULTF3(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF3_MASK, FTM_FMS_FAULTF3(value)))
+#define FTM_BWR_FMS_FAULTF3(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTIN[5] (RO)
+ *
+ * Represents the logic OR of the enabled fault inputs after their filter (if
+ * their filter is enabled) when fault control is enabled.
+ *
+ * Values:
+ * - 0b0 - The logic OR of the enabled fault inputs is 0.
+ * - 0b1 - The logic OR of the enabled fault inputs is 1.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTIN field. */
+#define FTM_RD_FMS_FAULTIN(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTIN_MASK) >> FTM_FMS_FAULTIN_SHIFT)
+#define FTM_BRD_FMS_FAULTIN(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTIN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field WPEN[6] (RW)
+ *
+ * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
+ * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
+ * WPDIS. Writing 0 to WPEN has no effect.
+ *
+ * Values:
+ * - 0b0 - Write protection is disabled. Write protected bits can be written.
+ * - 0b1 - Write protection is enabled. Write protected bits cannot be written.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_WPEN field. */
+#define FTM_RD_FMS_WPEN(base) ((FTM_FMS_REG(base) & FTM_FMS_WPEN_MASK) >> FTM_FMS_WPEN_SHIFT)
+#define FTM_BRD_FMS_WPEN(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_WPEN_SHIFT))
+
+/*! @brief Set the WPEN field to a new value. */
+#define FTM_WR_FMS_WPEN(base, value) (FTM_RMW_FMS(base, FTM_FMS_WPEN_MASK, FTM_FMS_WPEN(value)))
+#define FTM_BWR_FMS_WPEN(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_WPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
+ *
+ * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
+ * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
+ * a 0 to FAULTF while there is no existing fault condition at the enabled fault
+ * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
+ * detected in an enabled fault input before the clearing sequence is completed, the
+ * sequence is reset so FAULTF remains set after the clearing sequence is
+ * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
+ * are cleared individually.
+ *
+ * Values:
+ * - 0b0 - No fault condition was detected.
+ * - 0b1 - A fault condition was detected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FMS_FAULTF field. */
+#define FTM_RD_FMS_FAULTF(base) ((FTM_FMS_REG(base) & FTM_FMS_FAULTF_MASK) >> FTM_FMS_FAULTF_SHIFT)
+#define FTM_BRD_FMS_FAULTF(base) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF_SHIFT))
+
+/*! @brief Set the FAULTF field to a new value. */
+#define FTM_WR_FMS_FAULTF(base, value) (FTM_RMW_FMS(base, FTM_FMS_FAULTF_MASK, FTM_FMS_FAULTF(value)))
+#define FTM_BWR_FMS_FAULTF(base, value) (BITBAND_ACCESS32(&FTM_FMS_REG(base), FTM_FMS_FAULTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FILTER - Input Capture Filter Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FILTER - Input Capture Filter Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the inputs of channels. Channels
+ * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
+ * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
+ * in input modes. Failure to do this could result in a missing valid signal.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FILTER register
+ */
+/*@{*/
+#define FTM_RD_FILTER(base)      (FTM_FILTER_REG(base))
+#define FTM_WR_FILTER(base, value) (FTM_FILTER_REG(base) = (value))
+#define FTM_RMW_FILTER(base, mask, value) (FTM_WR_FILTER(base, (FTM_RD_FILTER(base) & ~(mask)) | (value)))
+#define FTM_SET_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) |  (value)))
+#define FTM_CLR_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) & ~(value)))
+#define FTM_TOG_FILTER(base, value) (FTM_WR_FILTER(base, FTM_RD_FILTER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FILTER bitfields
+ */
+
+/*!
+ * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */
+#define FTM_RD_FILTER_CH0FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH0FVAL_MASK) >> FTM_FILTER_CH0FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH0FVAL(base) (FTM_RD_FILTER_CH0FVAL(base))
+
+/*! @brief Set the CH0FVAL field to a new value. */
+#define FTM_WR_FILTER_CH0FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH0FVAL_MASK, FTM_FILTER_CH0FVAL(value)))
+#define FTM_BWR_FILTER_CH0FVAL(base, value) (FTM_WR_FILTER_CH0FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */
+#define FTM_RD_FILTER_CH1FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH1FVAL_MASK) >> FTM_FILTER_CH1FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH1FVAL(base) (FTM_RD_FILTER_CH1FVAL(base))
+
+/*! @brief Set the CH1FVAL field to a new value. */
+#define FTM_WR_FILTER_CH1FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH1FVAL_MASK, FTM_FILTER_CH1FVAL(value)))
+#define FTM_BWR_FILTER_CH1FVAL(base, value) (FTM_WR_FILTER_CH1FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */
+#define FTM_RD_FILTER_CH2FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH2FVAL_MASK) >> FTM_FILTER_CH2FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH2FVAL(base) (FTM_RD_FILTER_CH2FVAL(base))
+
+/*! @brief Set the CH2FVAL field to a new value. */
+#define FTM_WR_FILTER_CH2FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH2FVAL_MASK, FTM_FILTER_CH2FVAL(value)))
+#define FTM_BWR_FILTER_CH2FVAL(base, value) (FTM_WR_FILTER_CH2FVAL(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
+ *
+ * Selects the filter value for the channel input. The filter is disabled when
+ * the value is zero.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */
+#define FTM_RD_FILTER_CH3FVAL(base) ((FTM_FILTER_REG(base) & FTM_FILTER_CH3FVAL_MASK) >> FTM_FILTER_CH3FVAL_SHIFT)
+#define FTM_BRD_FILTER_CH3FVAL(base) (FTM_RD_FILTER_CH3FVAL(base))
+
+/*! @brief Set the CH3FVAL field to a new value. */
+#define FTM_WR_FILTER_CH3FVAL(base, value) (FTM_RMW_FILTER(base, FTM_FILTER_CH3FVAL_MASK, FTM_FILTER_CH3FVAL(value)))
+#define FTM_BWR_FILTER_CH3FVAL(base, value) (FTM_WR_FILTER_CH3FVAL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FLTCTRL - Fault Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FLTCTRL - Fault Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the filter value for the fault inputs, enables the
+ * fault inputs and the fault inputs filter.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FLTCTRL register
+ */
+/*@{*/
+#define FTM_RD_FLTCTRL(base)     (FTM_FLTCTRL_REG(base))
+#define FTM_WR_FLTCTRL(base, value) (FTM_FLTCTRL_REG(base) = (value))
+#define FTM_RMW_FLTCTRL(base, mask, value) (FTM_WR_FLTCTRL(base, (FTM_RD_FLTCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) |  (value)))
+#define FTM_CLR_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) & ~(value)))
+#define FTM_TOG_FLTCTRL(base, value) (FTM_WR_FLTCTRL(base, FTM_RD_FLTCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FLTCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */
+#define FTM_RD_FLTCTRL_FAULT0EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT0EN_MASK) >> FTM_FLTCTRL_FAULT0EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT0EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT0EN_SHIFT))
+
+/*! @brief Set the FAULT0EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT0EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT0EN_MASK, FTM_FLTCTRL_FAULT0EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT0EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */
+#define FTM_RD_FLTCTRL_FAULT1EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT1EN_MASK) >> FTM_FLTCTRL_FAULT1EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT1EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT1EN_SHIFT))
+
+/*! @brief Set the FAULT1EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT1EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT1EN_MASK, FTM_FLTCTRL_FAULT1EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT1EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */
+#define FTM_RD_FLTCTRL_FAULT2EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT2EN_MASK) >> FTM_FLTCTRL_FAULT2EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT2EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT2EN_SHIFT))
+
+/*! @brief Set the FAULT2EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT2EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT2EN_MASK, FTM_FLTCTRL_FAULT2EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT2EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
+ *
+ * Enables the fault input. This field is write protected. It can be written
+ * only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input is disabled.
+ * - 0b1 - Fault input is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */
+#define FTM_RD_FLTCTRL_FAULT3EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FAULT3EN_MASK) >> FTM_FLTCTRL_FAULT3EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FAULT3EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT3EN_SHIFT))
+
+/*! @brief Set the FAULT3EN field to a new value. */
+#define FTM_WR_FLTCTRL_FAULT3EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FAULT3EN_MASK, FTM_FLTCTRL_FAULT3EN(value)))
+#define FTM_BWR_FLTCTRL_FAULT3EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FAULT3EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */
+#define FTM_RD_FLTCTRL_FFLTR0EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR0EN_MASK) >> FTM_FLTCTRL_FFLTR0EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR0EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR0EN_SHIFT))
+
+/*! @brief Set the FFLTR0EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR0EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR0EN_MASK, FTM_FLTCTRL_FFLTR0EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR0EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */
+#define FTM_RD_FLTCTRL_FFLTR1EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR1EN_MASK) >> FTM_FLTCTRL_FFLTR1EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR1EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR1EN_SHIFT))
+
+/*! @brief Set the FFLTR1EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR1EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR1EN_MASK, FTM_FLTCTRL_FFLTR1EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR1EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */
+#define FTM_RD_FLTCTRL_FFLTR2EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR2EN_MASK) >> FTM_FLTCTRL_FFLTR2EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR2EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR2EN_SHIFT))
+
+/*! @brief Set the FFLTR2EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR2EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR2EN_MASK, FTM_FLTCTRL_FFLTR2EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR2EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
+ *
+ * Enables the filter for the fault input. This field is write protected. It can
+ * be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Fault input filter is disabled.
+ * - 0b1 - Fault input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */
+#define FTM_RD_FLTCTRL_FFLTR3EN(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFLTR3EN_MASK) >> FTM_FLTCTRL_FFLTR3EN_SHIFT)
+#define FTM_BRD_FLTCTRL_FFLTR3EN(base) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR3EN_SHIFT))
+
+/*! @brief Set the FFLTR3EN field to a new value. */
+#define FTM_WR_FLTCTRL_FFLTR3EN(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFLTR3EN_MASK, FTM_FLTCTRL_FFLTR3EN(value)))
+#define FTM_BWR_FLTCTRL_FFLTR3EN(base, value) (BITBAND_ACCESS32(&FTM_FLTCTRL_REG(base), FTM_FLTCTRL_FFLTR3EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
+ *
+ * Selects the filter value for the fault inputs. The fault filter is disabled
+ * when the value is zero. Writing to this field has immediate effect and must be
+ * done only when the fault control or all fault inputs are disabled. Failure to
+ * do this could result in a missing fault detection.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */
+#define FTM_RD_FLTCTRL_FFVAL(base) ((FTM_FLTCTRL_REG(base) & FTM_FLTCTRL_FFVAL_MASK) >> FTM_FLTCTRL_FFVAL_SHIFT)
+#define FTM_BRD_FLTCTRL_FFVAL(base) (FTM_RD_FLTCTRL_FFVAL(base))
+
+/*! @brief Set the FFVAL field to a new value. */
+#define FTM_WR_FLTCTRL_FFVAL(base, value) (FTM_RMW_FLTCTRL(base, FTM_FLTCTRL_FFVAL_MASK, FTM_FLTCTRL_FFVAL(value)))
+#define FTM_BWR_FLTCTRL_FFVAL(base, value) (FTM_WR_FLTCTRL_FFVAL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_QDCTRL - Quadrature Decoder Control And Status
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register has the control and status bits for the Quadrature Decoder mode.
+ */
+/*!
+ * @name Constants and macros for entire FTM_QDCTRL register
+ */
+/*@{*/
+#define FTM_RD_QDCTRL(base)      (FTM_QDCTRL_REG(base))
+#define FTM_WR_QDCTRL(base, value) (FTM_QDCTRL_REG(base) = (value))
+#define FTM_RMW_QDCTRL(base, mask, value) (FTM_WR_QDCTRL(base, (FTM_RD_QDCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) |  (value)))
+#define FTM_CLR_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) & ~(value)))
+#define FTM_TOG_QDCTRL(base, value) (FTM_WR_QDCTRL(base, FTM_RD_QDCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_QDCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
+ *
+ * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
+ * signals control the FTM counter direction. The Quadrature Decoder mode has
+ * precedence over the other modes. See #ModeSel1Table. This field is write protected.
+ * It can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - Quadrature Decoder mode is disabled.
+ * - 0b1 - Quadrature Decoder mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */
+#define FTM_RD_QDCTRL_QUADEN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADEN_MASK) >> FTM_QDCTRL_QUADEN_SHIFT)
+#define FTM_BRD_QDCTRL_QUADEN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADEN_SHIFT))
+
+/*! @brief Set the QUADEN field to a new value. */
+#define FTM_WR_QDCTRL_QUADEN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_QUADEN_MASK, FTM_QDCTRL_QUADEN(value)))
+#define FTM_BWR_QDCTRL_QUADEN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
+ *
+ * Indicates if the TOF bit was set on the top or the bottom of counting.
+ *
+ * Values:
+ * - 0b0 - TOF bit was set on the bottom of counting. There was an FTM counter
+ *     decrement and FTM counter changes from its minimum value (CNTIN register)
+ *     to its maximum value (MOD register).
+ * - 0b1 - TOF bit was set on the top of counting. There was an FTM counter
+ *     increment and FTM counter changes from its maximum value (MOD register) to its
+ *     minimum value (CNTIN register).
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */
+#define FTM_RD_QDCTRL_TOFDIR(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_TOFDIR_MASK) >> FTM_QDCTRL_TOFDIR_SHIFT)
+#define FTM_BRD_QDCTRL_TOFDIR(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_TOFDIR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
+ *
+ * Indicates the counting direction.
+ *
+ * Values:
+ * - 0b0 - Counting direction is decreasing (FTM counter decrement).
+ * - 0b1 - Counting direction is increasing (FTM counter increment).
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */
+#define FTM_RD_QDCTRL_QUADIR(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADIR_MASK) >> FTM_QDCTRL_QUADIR_SHIFT)
+#define FTM_BRD_QDCTRL_QUADIR(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADIR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
+ *
+ * Selects the encoding mode used in the Quadrature Decoder mode.
+ *
+ * Values:
+ * - 0b0 - Phase A and phase B encoding mode.
+ * - 0b1 - Count and direction encoding mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */
+#define FTM_RD_QDCTRL_QUADMODE(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_QUADMODE_MASK) >> FTM_QDCTRL_QUADMODE_SHIFT)
+#define FTM_BRD_QDCTRL_QUADMODE(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADMODE_SHIFT))
+
+/*! @brief Set the QUADMODE field to a new value. */
+#define FTM_WR_QDCTRL_QUADMODE(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_QUADMODE_MASK, FTM_QDCTRL_QUADMODE(value)))
+#define FTM_BWR_QDCTRL_QUADMODE(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_QUADMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase B input.
+ *
+ * Values:
+ * - 0b0 - Normal polarity. Phase B input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 0b1 - Inverted polarity. Phase B input signal is inverted before
+ *     identifying the rising and falling edges of this signal.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */
+#define FTM_RD_QDCTRL_PHBPOL(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHBPOL_MASK) >> FTM_QDCTRL_PHBPOL_SHIFT)
+#define FTM_BRD_QDCTRL_PHBPOL(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBPOL_SHIFT))
+
+/*! @brief Set the PHBPOL field to a new value. */
+#define FTM_WR_QDCTRL_PHBPOL(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHBPOL_MASK, FTM_QDCTRL_PHBPOL(value)))
+#define FTM_BWR_QDCTRL_PHBPOL(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
+ *
+ * Selects the polarity for the quadrature decoder phase A input.
+ *
+ * Values:
+ * - 0b0 - Normal polarity. Phase A input signal is not inverted before
+ *     identifying the rising and falling edges of this signal.
+ * - 0b1 - Inverted polarity. Phase A input signal is inverted before
+ *     identifying the rising and falling edges of this signal.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */
+#define FTM_RD_QDCTRL_PHAPOL(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHAPOL_MASK) >> FTM_QDCTRL_PHAPOL_SHIFT)
+#define FTM_BRD_QDCTRL_PHAPOL(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAPOL_SHIFT))
+
+/*! @brief Set the PHAPOL field to a new value. */
+#define FTM_WR_QDCTRL_PHAPOL(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHAPOL_MASK, FTM_QDCTRL_PHAPOL(value)))
+#define FTM_BWR_QDCTRL_PHAPOL(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase B input. The filter value
+ * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
+ * filter is also disabled when CH1FVAL is zero.
+ *
+ * Values:
+ * - 0b0 - Phase B input filter is disabled.
+ * - 0b1 - Phase B input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */
+#define FTM_RD_QDCTRL_PHBFLTREN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHBFLTREN_MASK) >> FTM_QDCTRL_PHBFLTREN_SHIFT)
+#define FTM_BRD_QDCTRL_PHBFLTREN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBFLTREN_SHIFT))
+
+/*! @brief Set the PHBFLTREN field to a new value. */
+#define FTM_WR_QDCTRL_PHBFLTREN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHBFLTREN_MASK, FTM_QDCTRL_PHBFLTREN(value)))
+#define FTM_BWR_QDCTRL_PHBFLTREN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHBFLTREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
+ *
+ * Enables the filter for the quadrature decoder phase A input. The filter value
+ * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
+ * filter is also disabled when CH0FVAL is zero.
+ *
+ * Values:
+ * - 0b0 - Phase A input filter is disabled.
+ * - 0b1 - Phase A input filter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */
+#define FTM_RD_QDCTRL_PHAFLTREN(base) ((FTM_QDCTRL_REG(base) & FTM_QDCTRL_PHAFLTREN_MASK) >> FTM_QDCTRL_PHAFLTREN_SHIFT)
+#define FTM_BRD_QDCTRL_PHAFLTREN(base) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAFLTREN_SHIFT))
+
+/*! @brief Set the PHAFLTREN field to a new value. */
+#define FTM_WR_QDCTRL_PHAFLTREN(base, value) (FTM_RMW_QDCTRL(base, FTM_QDCTRL_PHAFLTREN_MASK, FTM_QDCTRL_PHAFLTREN(value)))
+#define FTM_BWR_QDCTRL_PHAFLTREN(base, value) (BITBAND_ACCESS32(&FTM_QDCTRL_REG(base), FTM_QDCTRL_PHAFLTREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_CONF - Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_CONF - Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the number of times that the FTM counter overflow
+ * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
+ * of an external global time base, and the global time base signal generation.
+ */
+/*!
+ * @name Constants and macros for entire FTM_CONF register
+ */
+/*@{*/
+#define FTM_RD_CONF(base)        (FTM_CONF_REG(base))
+#define FTM_WR_CONF(base, value) (FTM_CONF_REG(base) = (value))
+#define FTM_RMW_CONF(base, mask, value) (FTM_WR_CONF(base, (FTM_RD_CONF(base) & ~(mask)) | (value)))
+#define FTM_SET_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) |  (value)))
+#define FTM_CLR_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) & ~(value)))
+#define FTM_TOG_CONF(base, value) (FTM_WR_CONF(base, FTM_RD_CONF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_CONF bitfields
+ */
+
+/*!
+ * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
+ *
+ * Selects the ratio between the number of counter overflows to the number of
+ * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
+ * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
+ * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
+ * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
+ * first counter overflow but not for the next 3 overflows. This pattern continues
+ * up to a maximum of 31.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_NUMTOF field. */
+#define FTM_RD_CONF_NUMTOF(base) ((FTM_CONF_REG(base) & FTM_CONF_NUMTOF_MASK) >> FTM_CONF_NUMTOF_SHIFT)
+#define FTM_BRD_CONF_NUMTOF(base) (FTM_RD_CONF_NUMTOF(base))
+
+/*! @brief Set the NUMTOF field to a new value. */
+#define FTM_WR_CONF_NUMTOF(base, value) (FTM_RMW_CONF(base, FTM_CONF_NUMTOF_MASK, FTM_CONF_NUMTOF(value)))
+#define FTM_BWR_CONF_NUMTOF(base, value) (FTM_WR_CONF_NUMTOF(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
+ *
+ * Selects the FTM behavior in BDM mode. See BDM mode.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_BDMMODE field. */
+#define FTM_RD_CONF_BDMMODE(base) ((FTM_CONF_REG(base) & FTM_CONF_BDMMODE_MASK) >> FTM_CONF_BDMMODE_SHIFT)
+#define FTM_BRD_CONF_BDMMODE(base) (FTM_RD_CONF_BDMMODE(base))
+
+/*! @brief Set the BDMMODE field to a new value. */
+#define FTM_WR_CONF_BDMMODE(base, value) (FTM_RMW_CONF(base, FTM_CONF_BDMMODE_MASK, FTM_CONF_BDMMODE(value)))
+#define FTM_BWR_CONF_BDMMODE(base, value) (FTM_WR_CONF_BDMMODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field GTBEEN[9] (RW)
+ *
+ * Configures the FTM to use an external global time base signal that is
+ * generated by another FTM.
+ *
+ * Values:
+ * - 0b0 - Use of an external global time base is disabled.
+ * - 0b1 - Use of an external global time base is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_GTBEEN field. */
+#define FTM_RD_CONF_GTBEEN(base) ((FTM_CONF_REG(base) & FTM_CONF_GTBEEN_MASK) >> FTM_CONF_GTBEEN_SHIFT)
+#define FTM_BRD_CONF_GTBEEN(base) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEEN_SHIFT))
+
+/*! @brief Set the GTBEEN field to a new value. */
+#define FTM_WR_CONF_GTBEEN(base, value) (FTM_RMW_CONF(base, FTM_CONF_GTBEEN_MASK, FTM_CONF_GTBEEN(value)))
+#define FTM_BWR_CONF_GTBEEN(base, value) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_CONF, field GTBEOUT[10] (RW)
+ *
+ * Enables the global time base signal generation to other FTMs.
+ *
+ * Values:
+ * - 0b0 - A global time base signal generation is disabled.
+ * - 0b1 - A global time base signal generation is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_CONF_GTBEOUT field. */
+#define FTM_RD_CONF_GTBEOUT(base) ((FTM_CONF_REG(base) & FTM_CONF_GTBEOUT_MASK) >> FTM_CONF_GTBEOUT_SHIFT)
+#define FTM_BRD_CONF_GTBEOUT(base) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEOUT_SHIFT))
+
+/*! @brief Set the GTBEOUT field to a new value. */
+#define FTM_WR_CONF_GTBEOUT(base, value) (FTM_RMW_CONF(base, FTM_CONF_GTBEOUT_MASK, FTM_CONF_GTBEOUT(value)))
+#define FTM_BWR_CONF_GTBEOUT(base, value) (BITBAND_ACCESS32(&FTM_CONF_REG(base), FTM_CONF_GTBEOUT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_FLTPOL - FTM Fault Input Polarity
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_FLTPOL - FTM Fault Input Polarity (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register defines the fault inputs polarity.
+ */
+/*!
+ * @name Constants and macros for entire FTM_FLTPOL register
+ */
+/*@{*/
+#define FTM_RD_FLTPOL(base)      (FTM_FLTPOL_REG(base))
+#define FTM_WR_FLTPOL(base, value) (FTM_FLTPOL_REG(base) = (value))
+#define FTM_RMW_FLTPOL(base, mask, value) (FTM_WR_FLTPOL(base, (FTM_RD_FLTPOL(base) & ~(mask)) | (value)))
+#define FTM_SET_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) |  (value)))
+#define FTM_CLR_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) & ~(value)))
+#define FTM_TOG_FLTPOL(base, value) (FTM_WR_FLTPOL(base, FTM_RD_FLTPOL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_FLTPOL bitfields
+ */
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */
+#define FTM_RD_FLTPOL_FLT0POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT0POL_MASK) >> FTM_FLTPOL_FLT0POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT0POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT0POL_SHIFT))
+
+/*! @brief Set the FLT0POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT0POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT0POL_MASK, FTM_FLTPOL_FLT0POL(value)))
+#define FTM_BWR_FLTPOL_FLT0POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT0POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */
+#define FTM_RD_FLTPOL_FLT1POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT1POL_MASK) >> FTM_FLTPOL_FLT1POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT1POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT1POL_SHIFT))
+
+/*! @brief Set the FLT1POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT1POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT1POL_MASK, FTM_FLTPOL_FLT1POL(value)))
+#define FTM_BWR_FLTPOL_FLT1POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT1POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */
+#define FTM_RD_FLTPOL_FLT2POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT2POL_MASK) >> FTM_FLTPOL_FLT2POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT2POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT2POL_SHIFT))
+
+/*! @brief Set the FLT2POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT2POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT2POL_MASK, FTM_FLTPOL_FLT2POL(value)))
+#define FTM_BWR_FLTPOL_FLT2POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT2POL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
+ *
+ * Defines the polarity of the fault input. This field is write protected. It
+ * can be written only when MODE[WPDIS] = 1.
+ *
+ * Values:
+ * - 0b0 - The fault input polarity is active high. A 1 at the fault input
+ *     indicates a fault.
+ * - 0b1 - The fault input polarity is active low. A 0 at the fault input
+ *     indicates a fault.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */
+#define FTM_RD_FLTPOL_FLT3POL(base) ((FTM_FLTPOL_REG(base) & FTM_FLTPOL_FLT3POL_MASK) >> FTM_FLTPOL_FLT3POL_SHIFT)
+#define FTM_BRD_FLTPOL_FLT3POL(base) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT3POL_SHIFT))
+
+/*! @brief Set the FLT3POL field to a new value. */
+#define FTM_WR_FLTPOL_FLT3POL(base, value) (FTM_RMW_FLTPOL(base, FTM_FLTPOL_FLT3POL_MASK, FTM_FLTPOL_FLT3POL(value)))
+#define FTM_BWR_FLTPOL_FLT3POL(base, value) (BITBAND_ACCESS32(&FTM_FLTPOL_REG(base), FTM_FLTPOL_FLT3POL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SYNCONF - Synchronization Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SYNCONF - Synchronization Configuration (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
+ * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
+ * 0, 1, 2, when the hardware trigger j is detected.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SYNCONF register
+ */
+/*@{*/
+#define FTM_RD_SYNCONF(base)     (FTM_SYNCONF_REG(base))
+#define FTM_WR_SYNCONF(base, value) (FTM_SYNCONF_REG(base) = (value))
+#define FTM_RMW_SYNCONF(base, mask, value) (FTM_WR_SYNCONF(base, (FTM_RD_SYNCONF(base) & ~(mask)) | (value)))
+#define FTM_SET_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) |  (value)))
+#define FTM_CLR_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) & ~(value)))
+#define FTM_TOG_SYNCONF(base, value) (FTM_WR_SYNCONF(base, FTM_RD_SYNCONF(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SYNCONF bitfields
+ */
+
+/*!
+ * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - FTM clears the TRIGj bit when the hardware trigger j is detected,
+ *     where j = 0, 1,2.
+ * - 0b1 - FTM does not clear the TRIGj bit when the hardware trigger j is
+ *     detected, where j = 0, 1,2.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */
+#define FTM_RD_SYNCONF_HWTRIGMODE(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWTRIGMODE_MASK) >> FTM_SYNCONF_HWTRIGMODE_SHIFT)
+#define FTM_BRD_SYNCONF_HWTRIGMODE(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWTRIGMODE_SHIFT))
+
+/*! @brief Set the HWTRIGMODE field to a new value. */
+#define FTM_WR_SYNCONF_HWTRIGMODE(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWTRIGMODE_MASK, FTM_SYNCONF_HWTRIGMODE(value)))
+#define FTM_BWR_SYNCONF_HWTRIGMODE(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWTRIGMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
+ *
+ * Values:
+ * - 0b0 - CNTIN register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - CNTIN register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */
+#define FTM_RD_SYNCONF_CNTINC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_CNTINC_MASK) >> FTM_SYNCONF_CNTINC_SHIFT)
+#define FTM_BRD_SYNCONF_CNTINC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_CNTINC_SHIFT))
+
+/*! @brief Set the CNTINC field to a new value. */
+#define FTM_WR_SYNCONF_CNTINC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_CNTINC_MASK, FTM_SYNCONF_CNTINC(value)))
+#define FTM_BWR_SYNCONF_CNTINC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_CNTINC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field INVC[4] (RW)
+ *
+ * Values:
+ * - 0b0 - INVCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - INVCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_INVC field. */
+#define FTM_RD_SYNCONF_INVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_INVC_MASK) >> FTM_SYNCONF_INVC_SHIFT)
+#define FTM_BRD_SYNCONF_INVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_INVC_SHIFT))
+
+/*! @brief Set the INVC field to a new value. */
+#define FTM_WR_SYNCONF_INVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_INVC_MASK, FTM_SYNCONF_INVC(value)))
+#define FTM_BWR_SYNCONF_INVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_INVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOC[5] (RW)
+ *
+ * Values:
+ * - 0b0 - SWOCTRL register is updated with its buffer value at all rising edges
+ *     of system clock.
+ * - 0b1 - SWOCTRL register is updated with its buffer value by the PWM
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWOC field. */
+#define FTM_RD_SYNCONF_SWOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWOC_MASK) >> FTM_SYNCONF_SWOC_SHIFT)
+#define FTM_BRD_SYNCONF_SWOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOC_SHIFT))
+
+/*! @brief Set the SWOC field to a new value. */
+#define FTM_WR_SYNCONF_SWOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWOC_MASK, FTM_SYNCONF_SWOC(value)))
+#define FTM_BWR_SYNCONF_SWOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
+ *
+ * Selects the PWM Synchronization mode.
+ *
+ * Values:
+ * - 0b0 - Legacy PWM synchronization is selected.
+ * - 0b1 - Enhanced PWM synchronization is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */
+#define FTM_RD_SYNCONF_SYNCMODE(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SYNCMODE_MASK) >> FTM_SYNCONF_SYNCMODE_SHIFT)
+#define FTM_BRD_SYNCONF_SYNCMODE(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SYNCMODE_SHIFT))
+
+/*! @brief Set the SYNCMODE field to a new value. */
+#define FTM_WR_SYNCONF_SYNCMODE(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SYNCMODE_MASK, FTM_SYNCONF_SYNCMODE(value)))
+#define FTM_BWR_SYNCONF_SYNCMODE(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SYNCMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
+ *
+ * FTM counter synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the FTM counter
+ *     synchronization.
+ * - 0b1 - The software trigger activates the FTM counter synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */
+#define FTM_RD_SYNCONF_SWRSTCNT(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWRSTCNT_MASK) >> FTM_SYNCONF_SWRSTCNT_SHIFT)
+#define FTM_BRD_SYNCONF_SWRSTCNT(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWRSTCNT_SHIFT))
+
+/*! @brief Set the SWRSTCNT field to a new value. */
+#define FTM_WR_SYNCONF_SWRSTCNT(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWRSTCNT_MASK, FTM_SYNCONF_SWRSTCNT(value)))
+#define FTM_BWR_SYNCONF_SWRSTCNT(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWRSTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by the software
+ * trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 0b1 - The software trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */
+#define FTM_RD_SYNCONF_SWWRBUF(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWWRBUF_MASK) >> FTM_SYNCONF_SWWRBUF_SHIFT)
+#define FTM_BRD_SYNCONF_SWWRBUF(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWWRBUF_SHIFT))
+
+/*! @brief Set the SWWRBUF field to a new value. */
+#define FTM_WR_SYNCONF_SWWRBUF(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWWRBUF_MASK, FTM_SYNCONF_SWWRBUF(value)))
+#define FTM_BWR_SYNCONF_SWWRBUF(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWWRBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWOM[10] (RW)
+ *
+ * Output mask synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the OUTMASK register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWOM field. */
+#define FTM_RD_SYNCONF_SWOM(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWOM_MASK) >> FTM_SYNCONF_SWOM_SHIFT)
+#define FTM_BRD_SYNCONF_SWOM(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOM_SHIFT))
+
+/*! @brief Set the SWOM field to a new value. */
+#define FTM_WR_SYNCONF_SWOM(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWOM_MASK, FTM_SYNCONF_SWOM(value)))
+#define FTM_BWR_SYNCONF_SWOM(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
+ *
+ * Inverting control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the INVCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */
+#define FTM_RD_SYNCONF_SWINVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWINVC_MASK) >> FTM_SYNCONF_SWINVC_SHIFT)
+#define FTM_BRD_SYNCONF_SWINVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWINVC_SHIFT))
+
+/*! @brief Set the SWINVC field to a new value. */
+#define FTM_WR_SYNCONF_SWINVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWINVC_MASK, FTM_SYNCONF_SWINVC(value)))
+#define FTM_BWR_SYNCONF_SWINVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWINVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
+ *
+ * Software output control synchronization is activated by the software trigger.
+ *
+ * Values:
+ * - 0b0 - The software trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 0b1 - The software trigger activates the SWOCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */
+#define FTM_RD_SYNCONF_SWSOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_SWSOC_MASK) >> FTM_SYNCONF_SWSOC_SHIFT)
+#define FTM_BRD_SYNCONF_SWSOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWSOC_SHIFT))
+
+/*! @brief Set the SWSOC field to a new value. */
+#define FTM_WR_SYNCONF_SWSOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_SWSOC_MASK, FTM_SYNCONF_SWSOC(value)))
+#define FTM_BWR_SYNCONF_SWSOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_SWSOC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
+ *
+ * FTM counter synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the FTM counter synchronization.
+ * - 0b1 - A hardware trigger activates the FTM counter synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */
+#define FTM_RD_SYNCONF_HWRSTCNT(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWRSTCNT_MASK) >> FTM_SYNCONF_HWRSTCNT_SHIFT)
+#define FTM_BRD_SYNCONF_HWRSTCNT(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWRSTCNT_SHIFT))
+
+/*! @brief Set the HWRSTCNT field to a new value. */
+#define FTM_WR_SYNCONF_HWRSTCNT(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWRSTCNT_MASK, FTM_SYNCONF_HWRSTCNT(value)))
+#define FTM_BWR_SYNCONF_HWRSTCNT(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWRSTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
+ *
+ * MOD, CNTIN, and CV registers synchronization is activated by a hardware
+ * trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates MOD, CNTIN, and CV registers
+ *     synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */
+#define FTM_RD_SYNCONF_HWWRBUF(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWWRBUF_MASK) >> FTM_SYNCONF_HWWRBUF_SHIFT)
+#define FTM_BRD_SYNCONF_HWWRBUF(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWWRBUF_SHIFT))
+
+/*! @brief Set the HWWRBUF field to a new value. */
+#define FTM_WR_SYNCONF_HWWRBUF(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWWRBUF_MASK, FTM_SYNCONF_HWWRBUF(value)))
+#define FTM_BWR_SYNCONF_HWWRBUF(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWWRBUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWOM[18] (RW)
+ *
+ * Output mask synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the OUTMASK register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the OUTMASK register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWOM field. */
+#define FTM_RD_SYNCONF_HWOM(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWOM_MASK) >> FTM_SYNCONF_HWOM_SHIFT)
+#define FTM_BRD_SYNCONF_HWOM(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWOM_SHIFT))
+
+/*! @brief Set the HWOM field to a new value. */
+#define FTM_WR_SYNCONF_HWOM(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWOM_MASK, FTM_SYNCONF_HWOM(value)))
+#define FTM_BWR_SYNCONF_HWOM(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWOM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
+ *
+ * Inverting control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the INVCTRL register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the INVCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */
+#define FTM_RD_SYNCONF_HWINVC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWINVC_MASK) >> FTM_SYNCONF_HWINVC_SHIFT)
+#define FTM_BRD_SYNCONF_HWINVC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWINVC_SHIFT))
+
+/*! @brief Set the HWINVC field to a new value. */
+#define FTM_WR_SYNCONF_HWINVC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWINVC_MASK, FTM_SYNCONF_HWINVC(value)))
+#define FTM_BWR_SYNCONF_HWINVC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWINVC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
+ *
+ * Software output control synchronization is activated by a hardware trigger.
+ *
+ * Values:
+ * - 0b0 - A hardware trigger does not activate the SWOCTRL register
+ *     synchronization.
+ * - 0b1 - A hardware trigger activates the SWOCTRL register synchronization.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */
+#define FTM_RD_SYNCONF_HWSOC(base) ((FTM_SYNCONF_REG(base) & FTM_SYNCONF_HWSOC_MASK) >> FTM_SYNCONF_HWSOC_SHIFT)
+#define FTM_BRD_SYNCONF_HWSOC(base) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWSOC_SHIFT))
+
+/*! @brief Set the HWSOC field to a new value. */
+#define FTM_WR_SYNCONF_HWSOC(base, value) (FTM_RMW_SYNCONF(base, FTM_SYNCONF_HWSOC_MASK, FTM_SYNCONF_HWSOC(value)))
+#define FTM_BWR_SYNCONF_HWSOC(base, value) (BITBAND_ACCESS32(&FTM_SYNCONF_REG(base), FTM_SYNCONF_HWSOC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_INVCTRL - FTM Inverting Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_INVCTRL - FTM Inverting Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register controls when the channel (n) output becomes the channel (n+1)
+ * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
+ * bit enables the inverting operation for the corresponding pair channels m. This
+ * register has a write buffer. The INVmEN bit is updated by the INVCTRL
+ * register synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_INVCTRL register
+ */
+/*@{*/
+#define FTM_RD_INVCTRL(base)     (FTM_INVCTRL_REG(base))
+#define FTM_WR_INVCTRL(base, value) (FTM_INVCTRL_REG(base) = (value))
+#define FTM_RMW_INVCTRL(base, mask, value) (FTM_WR_INVCTRL(base, (FTM_RD_INVCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) |  (value)))
+#define FTM_CLR_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) & ~(value)))
+#define FTM_TOG_INVCTRL(base, value) (FTM_WR_INVCTRL(base, FTM_RD_INVCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_INVCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */
+#define FTM_RD_INVCTRL_INV0EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV0EN_MASK) >> FTM_INVCTRL_INV0EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV0EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV0EN_SHIFT))
+
+/*! @brief Set the INV0EN field to a new value. */
+#define FTM_WR_INVCTRL_INV0EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV0EN_MASK, FTM_INVCTRL_INV0EN(value)))
+#define FTM_BWR_INVCTRL_INV0EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV0EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */
+#define FTM_RD_INVCTRL_INV1EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV1EN_MASK) >> FTM_INVCTRL_INV1EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV1EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV1EN_SHIFT))
+
+/*! @brief Set the INV1EN field to a new value. */
+#define FTM_WR_INVCTRL_INV1EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV1EN_MASK, FTM_INVCTRL_INV1EN(value)))
+#define FTM_BWR_INVCTRL_INV1EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV1EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */
+#define FTM_RD_INVCTRL_INV2EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV2EN_MASK) >> FTM_INVCTRL_INV2EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV2EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV2EN_SHIFT))
+
+/*! @brief Set the INV2EN field to a new value. */
+#define FTM_WR_INVCTRL_INV2EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV2EN_MASK, FTM_INVCTRL_INV2EN(value)))
+#define FTM_BWR_INVCTRL_INV2EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV2EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Inverting is disabled.
+ * - 0b1 - Inverting is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */
+#define FTM_RD_INVCTRL_INV3EN(base) ((FTM_INVCTRL_REG(base) & FTM_INVCTRL_INV3EN_MASK) >> FTM_INVCTRL_INV3EN_SHIFT)
+#define FTM_BRD_INVCTRL_INV3EN(base) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV3EN_SHIFT))
+
+/*! @brief Set the INV3EN field to a new value. */
+#define FTM_WR_INVCTRL_INV3EN(base, value) (FTM_RMW_INVCTRL(base, FTM_INVCTRL_INV3EN_MASK, FTM_INVCTRL_INV3EN(value)))
+#define FTM_BWR_INVCTRL_INV3EN(base, value) (BITBAND_ACCESS32(&FTM_INVCTRL_REG(base), FTM_INVCTRL_INV3EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_SWOCTRL - FTM Software Output Control
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_SWOCTRL - FTM Software Output Control (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register enables software control of channel (n) output and defines the
+ * value forced to the channel (n) output: The CHnOC bits enable the control of
+ * the corresponding channel (n) output by software. The CHnOCV bits select the
+ * value that is forced at the corresponding channel (n) output. This register has
+ * a write buffer. The fields are updated by the SWOCTRL register synchronization.
+ */
+/*!
+ * @name Constants and macros for entire FTM_SWOCTRL register
+ */
+/*@{*/
+#define FTM_RD_SWOCTRL(base)     (FTM_SWOCTRL_REG(base))
+#define FTM_WR_SWOCTRL(base, value) (FTM_SWOCTRL_REG(base) = (value))
+#define FTM_RMW_SWOCTRL(base, mask, value) (FTM_WR_SWOCTRL(base, (FTM_RD_SWOCTRL(base) & ~(mask)) | (value)))
+#define FTM_SET_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) |  (value)))
+#define FTM_CLR_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) & ~(value)))
+#define FTM_TOG_SWOCTRL(base, value) (FTM_WR_SWOCTRL(base, FTM_RD_SWOCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_SWOCTRL bitfields
+ */
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */
+#define FTM_RD_SWOCTRL_CH0OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH0OC_MASK) >> FTM_SWOCTRL_CH0OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH0OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OC_SHIFT))
+
+/*! @brief Set the CH0OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH0OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH0OC_MASK, FTM_SWOCTRL_CH0OC(value)))
+#define FTM_BWR_SWOCTRL_CH0OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */
+#define FTM_RD_SWOCTRL_CH1OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH1OC_MASK) >> FTM_SWOCTRL_CH1OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH1OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OC_SHIFT))
+
+/*! @brief Set the CH1OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH1OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH1OC_MASK, FTM_SWOCTRL_CH1OC(value)))
+#define FTM_BWR_SWOCTRL_CH1OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */
+#define FTM_RD_SWOCTRL_CH2OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH2OC_MASK) >> FTM_SWOCTRL_CH2OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH2OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OC_SHIFT))
+
+/*! @brief Set the CH2OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH2OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH2OC_MASK, FTM_SWOCTRL_CH2OC(value)))
+#define FTM_BWR_SWOCTRL_CH2OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */
+#define FTM_RD_SWOCTRL_CH3OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH3OC_MASK) >> FTM_SWOCTRL_CH3OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH3OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OC_SHIFT))
+
+/*! @brief Set the CH3OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH3OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH3OC_MASK, FTM_SWOCTRL_CH3OC(value)))
+#define FTM_BWR_SWOCTRL_CH3OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */
+#define FTM_RD_SWOCTRL_CH4OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH4OC_MASK) >> FTM_SWOCTRL_CH4OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH4OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OC_SHIFT))
+
+/*! @brief Set the CH4OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH4OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH4OC_MASK, FTM_SWOCTRL_CH4OC(value)))
+#define FTM_BWR_SWOCTRL_CH4OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */
+#define FTM_RD_SWOCTRL_CH5OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH5OC_MASK) >> FTM_SWOCTRL_CH5OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH5OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OC_SHIFT))
+
+/*! @brief Set the CH5OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH5OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH5OC_MASK, FTM_SWOCTRL_CH5OC(value)))
+#define FTM_BWR_SWOCTRL_CH5OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */
+#define FTM_RD_SWOCTRL_CH6OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH6OC_MASK) >> FTM_SWOCTRL_CH6OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH6OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OC_SHIFT))
+
+/*! @brief Set the CH6OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH6OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH6OC_MASK, FTM_SWOCTRL_CH6OC(value)))
+#define FTM_BWR_SWOCTRL_CH6OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The channel output is not affected by software output control.
+ * - 0b1 - The channel output is affected by software output control.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */
+#define FTM_RD_SWOCTRL_CH7OC(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH7OC_MASK) >> FTM_SWOCTRL_CH7OC_SHIFT)
+#define FTM_BRD_SWOCTRL_CH7OC(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OC_SHIFT))
+
+/*! @brief Set the CH7OC field to a new value. */
+#define FTM_WR_SWOCTRL_CH7OC(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH7OC_MASK, FTM_SWOCTRL_CH7OC(value)))
+#define FTM_BWR_SWOCTRL_CH7OC(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */
+#define FTM_RD_SWOCTRL_CH0OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH0OCV_MASK) >> FTM_SWOCTRL_CH0OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH0OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OCV_SHIFT))
+
+/*! @brief Set the CH0OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH0OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH0OCV_MASK, FTM_SWOCTRL_CH0OCV(value)))
+#define FTM_BWR_SWOCTRL_CH0OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH0OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */
+#define FTM_RD_SWOCTRL_CH1OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH1OCV_MASK) >> FTM_SWOCTRL_CH1OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH1OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OCV_SHIFT))
+
+/*! @brief Set the CH1OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH1OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH1OCV_MASK, FTM_SWOCTRL_CH1OCV(value)))
+#define FTM_BWR_SWOCTRL_CH1OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH1OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */
+#define FTM_RD_SWOCTRL_CH2OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH2OCV_MASK) >> FTM_SWOCTRL_CH2OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH2OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OCV_SHIFT))
+
+/*! @brief Set the CH2OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH2OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH2OCV_MASK, FTM_SWOCTRL_CH2OCV(value)))
+#define FTM_BWR_SWOCTRL_CH2OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH2OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */
+#define FTM_RD_SWOCTRL_CH3OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH3OCV_MASK) >> FTM_SWOCTRL_CH3OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH3OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OCV_SHIFT))
+
+/*! @brief Set the CH3OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH3OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH3OCV_MASK, FTM_SWOCTRL_CH3OCV(value)))
+#define FTM_BWR_SWOCTRL_CH3OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH3OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */
+#define FTM_RD_SWOCTRL_CH4OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH4OCV_MASK) >> FTM_SWOCTRL_CH4OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH4OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OCV_SHIFT))
+
+/*! @brief Set the CH4OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH4OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH4OCV_MASK, FTM_SWOCTRL_CH4OCV(value)))
+#define FTM_BWR_SWOCTRL_CH4OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH4OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */
+#define FTM_RD_SWOCTRL_CH5OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH5OCV_MASK) >> FTM_SWOCTRL_CH5OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH5OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OCV_SHIFT))
+
+/*! @brief Set the CH5OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH5OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH5OCV_MASK, FTM_SWOCTRL_CH5OCV(value)))
+#define FTM_BWR_SWOCTRL_CH5OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH5OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */
+#define FTM_RD_SWOCTRL_CH6OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH6OCV_MASK) >> FTM_SWOCTRL_CH6OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH6OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OCV_SHIFT))
+
+/*! @brief Set the CH6OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH6OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH6OCV_MASK, FTM_SWOCTRL_CH6OCV(value)))
+#define FTM_BWR_SWOCTRL_CH6OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH6OCV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
+ *
+ * Values:
+ * - 0b0 - The software output control forces 0 to the channel output.
+ * - 0b1 - The software output control forces 1 to the channel output.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */
+#define FTM_RD_SWOCTRL_CH7OCV(base) ((FTM_SWOCTRL_REG(base) & FTM_SWOCTRL_CH7OCV_MASK) >> FTM_SWOCTRL_CH7OCV_SHIFT)
+#define FTM_BRD_SWOCTRL_CH7OCV(base) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OCV_SHIFT))
+
+/*! @brief Set the CH7OCV field to a new value. */
+#define FTM_WR_SWOCTRL_CH7OCV(base, value) (FTM_RMW_SWOCTRL(base, FTM_SWOCTRL_CH7OCV_MASK, FTM_SWOCTRL_CH7OCV(value)))
+#define FTM_BWR_SWOCTRL_CH7OCV(base, value) (BITBAND_ACCESS32(&FTM_SWOCTRL_REG(base), FTM_SWOCTRL_CH7OCV_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * FTM_PWMLOAD - FTM PWM Load
+ ******************************************************************************/
+
+/*!
+ * @brief FTM_PWMLOAD - FTM PWM Load (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
+ * values of their write buffers when the FTM counter changes from the MOD
+ * register value to its next value or when a channel (j) match occurs. A match occurs
+ * for the channel (j) when FTM counter = C(j)V.
+ */
+/*!
+ * @name Constants and macros for entire FTM_PWMLOAD register
+ */
+/*@{*/
+#define FTM_RD_PWMLOAD(base)     (FTM_PWMLOAD_REG(base))
+#define FTM_WR_PWMLOAD(base, value) (FTM_PWMLOAD_REG(base) = (value))
+#define FTM_RMW_PWMLOAD(base, mask, value) (FTM_WR_PWMLOAD(base, (FTM_RD_PWMLOAD(base) & ~(mask)) | (value)))
+#define FTM_SET_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) |  (value)))
+#define FTM_CLR_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) & ~(value)))
+#define FTM_TOG_PWMLOAD(base, value) (FTM_WR_PWMLOAD(base, FTM_RD_PWMLOAD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual FTM_PWMLOAD bitfields
+ */
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */
+#define FTM_RD_PWMLOAD_CH0SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH0SEL_MASK) >> FTM_PWMLOAD_CH0SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH0SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH0SEL_SHIFT))
+
+/*! @brief Set the CH0SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH0SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH0SEL_MASK, FTM_PWMLOAD_CH0SEL(value)))
+#define FTM_BWR_PWMLOAD_CH0SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH0SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */
+#define FTM_RD_PWMLOAD_CH1SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH1SEL_MASK) >> FTM_PWMLOAD_CH1SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH1SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH1SEL_SHIFT))
+
+/*! @brief Set the CH1SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH1SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH1SEL_MASK, FTM_PWMLOAD_CH1SEL(value)))
+#define FTM_BWR_PWMLOAD_CH1SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH1SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */
+#define FTM_RD_PWMLOAD_CH2SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH2SEL_MASK) >> FTM_PWMLOAD_CH2SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH2SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH2SEL_SHIFT))
+
+/*! @brief Set the CH2SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH2SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH2SEL_MASK, FTM_PWMLOAD_CH2SEL(value)))
+#define FTM_BWR_PWMLOAD_CH2SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH2SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */
+#define FTM_RD_PWMLOAD_CH3SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH3SEL_MASK) >> FTM_PWMLOAD_CH3SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH3SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH3SEL_SHIFT))
+
+/*! @brief Set the CH3SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH3SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH3SEL_MASK, FTM_PWMLOAD_CH3SEL(value)))
+#define FTM_BWR_PWMLOAD_CH3SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH3SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */
+#define FTM_RD_PWMLOAD_CH4SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH4SEL_MASK) >> FTM_PWMLOAD_CH4SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH4SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH4SEL_SHIFT))
+
+/*! @brief Set the CH4SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH4SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH4SEL_MASK, FTM_PWMLOAD_CH4SEL(value)))
+#define FTM_BWR_PWMLOAD_CH4SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH4SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */
+#define FTM_RD_PWMLOAD_CH5SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH5SEL_MASK) >> FTM_PWMLOAD_CH5SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH5SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH5SEL_SHIFT))
+
+/*! @brief Set the CH5SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH5SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH5SEL_MASK, FTM_PWMLOAD_CH5SEL(value)))
+#define FTM_BWR_PWMLOAD_CH5SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH5SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */
+#define FTM_RD_PWMLOAD_CH6SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH6SEL_MASK) >> FTM_PWMLOAD_CH6SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH6SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH6SEL_SHIFT))
+
+/*! @brief Set the CH6SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH6SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH6SEL_MASK, FTM_PWMLOAD_CH6SEL(value)))
+#define FTM_BWR_PWMLOAD_CH6SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH6SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the channel in the matching process.
+ * - 0b1 - Include the channel in the matching process.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */
+#define FTM_RD_PWMLOAD_CH7SEL(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_CH7SEL_MASK) >> FTM_PWMLOAD_CH7SEL_SHIFT)
+#define FTM_BRD_PWMLOAD_CH7SEL(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH7SEL_SHIFT))
+
+/*! @brief Set the CH7SEL field to a new value. */
+#define FTM_WR_PWMLOAD_CH7SEL(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_CH7SEL_MASK, FTM_PWMLOAD_CH7SEL(value)))
+#define FTM_BWR_PWMLOAD_CH7SEL(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_CH7SEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
+ *
+ * Enables the loading of the MOD, CNTIN, and CV registers with the values of
+ * their write buffers.
+ *
+ * Values:
+ * - 0b0 - Loading updated values is disabled.
+ * - 0b1 - Loading updated values is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */
+#define FTM_RD_PWMLOAD_LDOK(base) ((FTM_PWMLOAD_REG(base) & FTM_PWMLOAD_LDOK_MASK) >> FTM_PWMLOAD_LDOK_SHIFT)
+#define FTM_BRD_PWMLOAD_LDOK(base) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_LDOK_SHIFT))
+
+/*! @brief Set the LDOK field to a new value. */
+#define FTM_WR_PWMLOAD_LDOK(base, value) (FTM_RMW_PWMLOAD(base, FTM_PWMLOAD_LDOK_MASK, FTM_PWMLOAD_LDOK(value)))
+#define FTM_BWR_PWMLOAD_LDOK(base, value) (BITBAND_ACCESS32(&FTM_PWMLOAD_REG(base), FTM_PWMLOAD_LDOK_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 GPIO
+ *
+ * General Purpose Input/Output
+ *
+ * Registers defined in this header file:
+ * - GPIO_PDOR - Port Data Output Register
+ * - GPIO_PSOR - Port Set Output Register
+ * - GPIO_PCOR - Port Clear Output Register
+ * - GPIO_PTOR - Port Toggle Output Register
+ * - GPIO_PDIR - Port Data Input Register
+ * - GPIO_PDDR - Port Data Direction Register
+ */
+
+#define GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
+#define GPIOA_IDX (0U) /*!< Instance number for GPIOA. */
+#define GPIOB_IDX (1U) /*!< Instance number for GPIOB. */
+#define GPIOC_IDX (2U) /*!< Instance number for GPIOC. */
+#define GPIOD_IDX (3U) /*!< Instance number for GPIOD. */
+#define GPIOE_IDX (4U) /*!< Instance number for GPIOE. */
+
+/*******************************************************************************
+ * GPIO_PDOR - Port Data Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDOR - Port Data Output Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures the logic levels that are driven on each
+ * general-purpose output pins. Do not modify pin configuration registers associated with
+ * pins not available in your selected package. All unbonded pins not available in
+ * your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDOR register
+ */
+/*@{*/
+#define GPIO_RD_PDOR(base)       (GPIO_PDOR_REG(base))
+#define GPIO_WR_PDOR(base, value) (GPIO_PDOR_REG(base) = (value))
+#define GPIO_RMW_PDOR(base, mask, value) (GPIO_WR_PDOR(base, (GPIO_RD_PDOR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) |  (value)))
+#define GPIO_CLR_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) & ~(value)))
+#define GPIO_TOG_PDOR(base, value) (GPIO_WR_PDOR(base, GPIO_RD_PDOR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PSOR - Port Set Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PSOR - Port Set Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to set the fields of the PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PSOR register
+ */
+/*@{*/
+#define GPIO_RD_PSOR(base)       (GPIO_PSOR_REG(base))
+#define GPIO_WR_PSOR(base, value) (GPIO_PSOR_REG(base) = (value))
+#define GPIO_RMW_PSOR(base, mask, value) (GPIO_WR_PSOR(base, (GPIO_RD_PSOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PCOR - Port Clear Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PCOR - Port Clear Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register configures whether to clear the fields of PDOR.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PCOR register
+ */
+/*@{*/
+#define GPIO_RD_PCOR(base)       (GPIO_PCOR_REG(base))
+#define GPIO_WR_PCOR(base, value) (GPIO_PCOR_REG(base) = (value))
+#define GPIO_RMW_PCOR(base, mask, value) (GPIO_WR_PCOR(base, (GPIO_RD_PCOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PTOR - Port Toggle Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PTOR - Port Toggle Output Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PTOR register
+ */
+/*@{*/
+#define GPIO_RD_PTOR(base)       (GPIO_PTOR_REG(base))
+#define GPIO_WR_PTOR(base, value) (GPIO_PTOR_REG(base) = (value))
+#define GPIO_RMW_PTOR(base, mask, value) (GPIO_WR_PTOR(base, (GPIO_RD_PTOR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDIR - Port Data Input Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDIR - Port Data Input Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Do not modify pin configuration registers associated with pins not available
+ * in your selected package. All unbonded pins not available in your package will
+ * default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDIR register
+ */
+/*@{*/
+#define GPIO_RD_PDIR(base)       (GPIO_PDIR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * GPIO_PDDR - Port Data Direction Register
+ ******************************************************************************/
+
+/*!
+ * @brief GPIO_PDDR - Port Data Direction Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The PDDR configures the individual port pins for input or output.
+ */
+/*!
+ * @name Constants and macros for entire GPIO_PDDR register
+ */
+/*@{*/
+#define GPIO_RD_PDDR(base)       (GPIO_PDDR_REG(base))
+#define GPIO_WR_PDDR(base, value) (GPIO_PDDR_REG(base) = (value))
+#define GPIO_RMW_PDDR(base, mask, value) (GPIO_WR_PDDR(base, (GPIO_RD_PDDR(base) & ~(mask)) | (value)))
+#define GPIO_SET_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) |  (value)))
+#define GPIO_CLR_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) & ~(value)))
+#define GPIO_TOG_PDDR(base, value) (GPIO_WR_PDDR(base, GPIO_RD_PDDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 I2C
+ *
+ * Inter-Integrated Circuit
+ *
+ * Registers defined in this header file:
+ * - I2C_A1 - I2C Address Register 1
+ * - I2C_F - I2C Frequency Divider register
+ * - I2C_C1 - I2C Control Register 1
+ * - I2C_S - I2C Status register
+ * - I2C_D - I2C Data I/O register
+ * - I2C_C2 - I2C Control Register 2
+ * - I2C_FLT - I2C Programmable Input Glitch Filter register
+ * - I2C_RA - I2C Range Address register
+ * - I2C_SMB - I2C SMBus Control and Status register
+ * - I2C_A2 - I2C Address Register 2
+ * - I2C_SLTH - I2C SCL Low Timeout Register High
+ * - I2C_SLTL - I2C SCL Low Timeout Register Low
+ */
+
+#define I2C_INSTANCE_COUNT (3U) /*!< Number of instances of the I2C module. */
+#define I2C0_IDX (0U) /*!< Instance number for I2C0. */
+#define I2C1_IDX (1U) /*!< Instance number for I2C1. */
+#define I2C2_IDX (2U) /*!< Instance number for I2C2. */
+
+/*******************************************************************************
+ * I2C_A1 - I2C Address Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A1 - I2C Address Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the slave address to be used by the I2C module.
+ */
+/*!
+ * @name Constants and macros for entire I2C_A1 register
+ */
+/*@{*/
+#define I2C_RD_A1(base)          (I2C_A1_REG(base))
+#define I2C_WR_A1(base, value)   (I2C_A1_REG(base) = (value))
+#define I2C_RMW_A1(base, mask, value) (I2C_WR_A1(base, (I2C_RD_A1(base) & ~(mask)) | (value)))
+#define I2C_SET_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) |  (value)))
+#define I2C_CLR_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) & ~(value)))
+#define I2C_TOG_A1(base, value)  (I2C_WR_A1(base, I2C_RD_A1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A1 bitfields
+ */
+
+/*!
+ * @name Register I2C_A1, field AD[7:1] (RW)
+ *
+ * Contains the primary slave address used by the I2C module when it is
+ * addressed as a slave. This field is used in the 7-bit address scheme and the lower
+ * seven bits in the 10-bit address scheme.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A1_AD field. */
+#define I2C_RD_A1_AD(base)   ((I2C_A1_REG(base) & I2C_A1_AD_MASK) >> I2C_A1_AD_SHIFT)
+#define I2C_BRD_A1_AD(base)  (I2C_RD_A1_AD(base))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_A1_AD(base, value) (I2C_RMW_A1(base, I2C_A1_AD_MASK, I2C_A1_AD(value)))
+#define I2C_BWR_A1_AD(base, value) (I2C_WR_A1_AD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_F - I2C Frequency Divider register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_F - I2C Frequency Divider register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_F register
+ */
+/*@{*/
+#define I2C_RD_F(base)           (I2C_F_REG(base))
+#define I2C_WR_F(base, value)    (I2C_F_REG(base) = (value))
+#define I2C_RMW_F(base, mask, value) (I2C_WR_F(base, (I2C_RD_F(base) & ~(mask)) | (value)))
+#define I2C_SET_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) |  (value)))
+#define I2C_CLR_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) & ~(value)))
+#define I2C_TOG_F(base, value)   (I2C_WR_F(base, I2C_RD_F(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_F bitfields
+ */
+
+/*!
+ * @name Register I2C_F, field ICR[5:0] (RW)
+ *
+ * Prescales the I2C module clock for bit rate selection. This field and the
+ * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
+ * time, and the SCL stop hold time. For a list of values corresponding to each ICR
+ * setting, see I2C divider and hold values. The SCL divider multiplied by
+ * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
+ * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
+ * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
+ * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
+ * the delay from the falling edge of SDA (I2C data) while SCL is high (start
+ * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
+ * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
+ * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
+ * data) while SCL is high (stop condition). SCL stop hold time = I2C module
+ * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
+ * speed is 8 MHz, the following table shows the possible hold time values with
+ * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
+ * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h
+ * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
+ * 1.125 4.750 5.125
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_ICR field. */
+#define I2C_RD_F_ICR(base)   ((I2C_F_REG(base) & I2C_F_ICR_MASK) >> I2C_F_ICR_SHIFT)
+#define I2C_BRD_F_ICR(base)  (I2C_RD_F_ICR(base))
+
+/*! @brief Set the ICR field to a new value. */
+#define I2C_WR_F_ICR(base, value) (I2C_RMW_F(base, I2C_F_ICR_MASK, I2C_F_ICR(value)))
+#define I2C_BWR_F_ICR(base, value) (I2C_WR_F_ICR(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_F, field MULT[7:6] (RW)
+ *
+ * Defines the multiplier factor (mul). This factor is used along with the SCL
+ * divider to generate the I2C baud rate.
+ *
+ * Values:
+ * - 0b00 - mul = 1
+ * - 0b01 - mul = 2
+ * - 0b10 - mul = 4
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_F_MULT field. */
+#define I2C_RD_F_MULT(base)  ((I2C_F_REG(base) & I2C_F_MULT_MASK) >> I2C_F_MULT_SHIFT)
+#define I2C_BRD_F_MULT(base) (I2C_RD_F_MULT(base))
+
+/*! @brief Set the MULT field to a new value. */
+#define I2C_WR_F_MULT(base, value) (I2C_RMW_F(base, I2C_F_MULT_MASK, I2C_F_MULT(value)))
+#define I2C_BWR_F_MULT(base, value) (I2C_WR_F_MULT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C1 - I2C Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C1 - I2C Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C1 register
+ */
+/*@{*/
+#define I2C_RD_C1(base)          (I2C_C1_REG(base))
+#define I2C_WR_C1(base, value)   (I2C_C1_REG(base) = (value))
+#define I2C_RMW_C1(base, mask, value) (I2C_WR_C1(base, (I2C_RD_C1(base) & ~(mask)) | (value)))
+#define I2C_SET_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) |  (value)))
+#define I2C_CLR_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) & ~(value)))
+#define I2C_TOG_C1(base, value)  (I2C_WR_C1(base, I2C_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C1 bitfields
+ */
+
+/*!
+ * @name Register I2C_C1, field DMAEN[0] (RW)
+ *
+ * Enables or disables the DMA function.
+ *
+ * Values:
+ * - 0b0 - All DMA signalling disabled.
+ * - 0b1 - DMA transfer is enabled. While SMB[FACK] = 0, the following
+ *     conditions trigger the DMA request: a data byte is received, and either address or
+ *     data is transmitted. (ACK/NACK is automatic) the first byte received
+ *     matches the A1 register or is a general call address. If any address matching
+ *     occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
+ *     from master to slave, then it is not required to check S[SRW]. With this
+ *     assumption, DMA can also be used in this case. In other cases, if the master
+ *     reads data from the slave, then it is required to rewrite the C1 register
+ *     operation. With this assumption, DMA cannot be used. When FACK = 1, an
+ *     address or a data byte is transmitted.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_DMAEN field. */
+#define I2C_RD_C1_DMAEN(base) ((I2C_C1_REG(base) & I2C_C1_DMAEN_MASK) >> I2C_C1_DMAEN_SHIFT)
+#define I2C_BRD_C1_DMAEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define I2C_WR_C1_DMAEN(base, value) (I2C_RMW_C1(base, I2C_C1_DMAEN_MASK, I2C_C1_DMAEN(value)))
+#define I2C_BWR_C1_DMAEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field WUEN[1] (RW)
+ *
+ * The I2C module can wake the MCU from low power mode with no peripheral bus
+ * running when slave address matching occurs.
+ *
+ * Values:
+ * - 0b0 - Normal operation. No interrupt generated when address matching in low
+ *     power mode.
+ * - 0b1 - Enables the wakeup function in low power mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_WUEN field. */
+#define I2C_RD_C1_WUEN(base) ((I2C_C1_REG(base) & I2C_C1_WUEN_MASK) >> I2C_C1_WUEN_SHIFT)
+#define I2C_BRD_C1_WUEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT))
+
+/*! @brief Set the WUEN field to a new value. */
+#define I2C_WR_C1_WUEN(base, value) (I2C_RMW_C1(base, I2C_C1_WUEN_MASK, I2C_C1_WUEN(value)))
+#define I2C_BWR_C1_WUEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field RSTA[2] (WORZ)
+ *
+ * Writing 1 to this bit generates a repeated START condition provided it is the
+ * current master. This bit will always be read as 0. Attempting a repeat at the
+ * wrong time results in loss of arbitration.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define I2C_WR_C1_RSTA(base, value) (I2C_RMW_C1(base, I2C_C1_RSTA_MASK, I2C_C1_RSTA(value)))
+#define I2C_BWR_C1_RSTA(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_RSTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TXAK[3] (RW)
+ *
+ * Specifies the value driven onto the SDA during data acknowledge cycles for
+ * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
+ * generation. SCL is held low until TXAK is written.
+ *
+ * Values:
+ * - 0b0 - An acknowledge signal is sent to the bus on the following receiving
+ *     byte (if FACK is cleared) or the current receiving byte (if FACK is set).
+ * - 0b1 - No acknowledge signal is sent to the bus on the following receiving
+ *     data byte (if FACK is cleared) or the current receiving data byte (if FACK
+ *     is set).
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TXAK field. */
+#define I2C_RD_C1_TXAK(base) ((I2C_C1_REG(base) & I2C_C1_TXAK_MASK) >> I2C_C1_TXAK_SHIFT)
+#define I2C_BRD_C1_TXAK(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT))
+
+/*! @brief Set the TXAK field to a new value. */
+#define I2C_WR_C1_TXAK(base, value) (I2C_RMW_C1(base, I2C_C1_TXAK_MASK, I2C_C1_TXAK(value)))
+#define I2C_BWR_C1_TXAK(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field TX[4] (RW)
+ *
+ * Selects the direction of master and slave transfers. In master mode this bit
+ * must be set according to the type of transfer required. Therefore, for address
+ * cycles, this bit is always set. When addressed as a slave this bit must be
+ * set by software according to the SRW bit in the status register.
+ *
+ * Values:
+ * - 0b0 - Receive
+ * - 0b1 - Transmit
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_TX field. */
+#define I2C_RD_C1_TX(base)   ((I2C_C1_REG(base) & I2C_C1_TX_MASK) >> I2C_C1_TX_SHIFT)
+#define I2C_BRD_C1_TX(base)  (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT))
+
+/*! @brief Set the TX field to a new value. */
+#define I2C_WR_C1_TX(base, value) (I2C_RMW_C1(base, I2C_C1_TX_MASK, I2C_C1_TX(value)))
+#define I2C_BWR_C1_TX(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field MST[5] (RW)
+ *
+ * When MST is changed from 0 to 1, a START signal is generated on the bus and
+ * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
+ * generated and the mode of operation changes from master to slave.
+ *
+ * Values:
+ * - 0b0 - Slave mode
+ * - 0b1 - Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_MST field. */
+#define I2C_RD_C1_MST(base)  ((I2C_C1_REG(base) & I2C_C1_MST_MASK) >> I2C_C1_MST_SHIFT)
+#define I2C_BRD_C1_MST(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT))
+
+/*! @brief Set the MST field to a new value. */
+#define I2C_WR_C1_MST(base, value) (I2C_RMW_C1(base, I2C_C1_MST_MASK, I2C_C1_MST(value)))
+#define I2C_BWR_C1_MST(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICIE[6] (RW)
+ *
+ * Enables I2C interrupt requests.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICIE field. */
+#define I2C_RD_C1_IICIE(base) ((I2C_C1_REG(base) & I2C_C1_IICIE_MASK) >> I2C_C1_IICIE_SHIFT)
+#define I2C_BRD_C1_IICIE(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT))
+
+/*! @brief Set the IICIE field to a new value. */
+#define I2C_WR_C1_IICIE(base, value) (I2C_RMW_C1(base, I2C_C1_IICIE_MASK, I2C_C1_IICIE(value)))
+#define I2C_BWR_C1_IICIE(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C1, field IICEN[7] (RW)
+ *
+ * Enables I2C module operation.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C1_IICEN field. */
+#define I2C_RD_C1_IICEN(base) ((I2C_C1_REG(base) & I2C_C1_IICEN_MASK) >> I2C_C1_IICEN_SHIFT)
+#define I2C_BRD_C1_IICEN(base) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT))
+
+/*! @brief Set the IICEN field to a new value. */
+#define I2C_WR_C1_IICEN(base, value) (I2C_RMW_C1(base, I2C_C1_IICEN_MASK, I2C_C1_IICEN(value)))
+#define I2C_BWR_C1_IICEN(base, value) (BITBAND_ACCESS8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_S - I2C Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_S - I2C Status register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire I2C_S register
+ */
+/*@{*/
+#define I2C_RD_S(base)           (I2C_S_REG(base))
+#define I2C_WR_S(base, value)    (I2C_S_REG(base) = (value))
+#define I2C_RMW_S(base, mask, value) (I2C_WR_S(base, (I2C_RD_S(base) & ~(mask)) | (value)))
+#define I2C_SET_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) |  (value)))
+#define I2C_CLR_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) & ~(value)))
+#define I2C_TOG_S(base, value)   (I2C_WR_S(base, I2C_RD_S(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_S bitfields
+ */
+
+/*!
+ * @name Register I2C_S, field RXAK[0] (RO)
+ *
+ * Values:
+ * - 0b0 - Acknowledge signal was received after the completion of one byte of
+ *     data transmission on the bus
+ * - 0b1 - No acknowledge signal detected
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RXAK field. */
+#define I2C_RD_S_RXAK(base)  ((I2C_S_REG(base) & I2C_S_RXAK_MASK) >> I2C_S_RXAK_SHIFT)
+#define I2C_BRD_S_RXAK(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RXAK_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IICIF[1] (W1C)
+ *
+ * This bit sets when an interrupt is pending. This bit must be cleared by
+ * software by writing 1 to it, such as in the interrupt routine. One of the following
+ * events can set this bit: One byte transfer, including ACK/NACK bit, completes
+ * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
+ * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
+ * completes if FACK is 1. Match of slave address to calling address including
+ * primary slave address, range slave address , alert response address, second
+ * slave address, or general call address. Arbitration lost In SMBus mode, any
+ * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
+ * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
+ * start detection interrupt: In the interrupt service routine, first clear the
+ * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
+ * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
+ * asserted again.
+ *
+ * Values:
+ * - 0b0 - No interrupt pending
+ * - 0b1 - Interrupt pending
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IICIF field. */
+#define I2C_RD_S_IICIF(base) ((I2C_S_REG(base) & I2C_S_IICIF_MASK) >> I2C_S_IICIF_SHIFT)
+#define I2C_BRD_S_IICIF(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT))
+
+/*! @brief Set the IICIF field to a new value. */
+#define I2C_WR_S_IICIF(base, value) (I2C_RMW_S(base, (I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IICIF(value)))
+#define I2C_BWR_S_IICIF(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field SRW[2] (RO)
+ *
+ * When addressed as a slave, SRW indicates the value of the R/W command bit of
+ * the calling address sent to the master.
+ *
+ * Values:
+ * - 0b0 - Slave receive, master writing to slave
+ * - 0b1 - Slave transmit, master reading from slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_SRW field. */
+#define I2C_RD_S_SRW(base)   ((I2C_S_REG(base) & I2C_S_SRW_MASK) >> I2C_S_SRW_SHIFT)
+#define I2C_BRD_S_SRW(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_SRW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field RAM[3] (RW)
+ *
+ * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
+ * Any nonzero calling address is received that matches the address in the RA
+ * register. The calling address is within the range of values of the A1 and RA
+ * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
+ * Writing the C1 register with any value clears this bit to 0.
+ *
+ * Values:
+ * - 0b0 - Not addressed
+ * - 0b1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_RAM field. */
+#define I2C_RD_S_RAM(base)   ((I2C_S_REG(base) & I2C_S_RAM_MASK) >> I2C_S_RAM_SHIFT)
+#define I2C_BRD_S_RAM(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RAM_SHIFT))
+
+/*! @brief Set the RAM field to a new value. */
+#define I2C_WR_S_RAM(base, value) (I2C_RMW_S(base, (I2C_S_RAM_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_RAM(value)))
+#define I2C_BWR_S_RAM(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_RAM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field ARBL[4] (W1C)
+ *
+ * This bit is set by hardware when the arbitration procedure is lost. The ARBL
+ * bit must be cleared by software, by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - Standard bus operation.
+ * - 0b1 - Loss of arbitration.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_ARBL field. */
+#define I2C_RD_S_ARBL(base)  ((I2C_S_REG(base) & I2C_S_ARBL_MASK) >> I2C_S_ARBL_SHIFT)
+#define I2C_BRD_S_ARBL(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT))
+
+/*! @brief Set the ARBL field to a new value. */
+#define I2C_WR_S_ARBL(base, value) (I2C_RMW_S(base, (I2C_S_ARBL_MASK | I2C_S_IICIF_MASK), I2C_S_ARBL(value)))
+#define I2C_BWR_S_ARBL(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field BUSY[5] (RO)
+ *
+ * Indicates the status of the bus regardless of slave or master mode. This bit
+ * is set when a START signal is detected and cleared when a STOP signal is
+ * detected.
+ *
+ * Values:
+ * - 0b0 - Bus is idle
+ * - 0b1 - Bus is busy
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_BUSY field. */
+#define I2C_RD_S_BUSY(base)  ((I2C_S_REG(base) & I2C_S_BUSY_MASK) >> I2C_S_BUSY_SHIFT)
+#define I2C_BRD_S_BUSY(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_BUSY_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field IAAS[6] (RW)
+ *
+ * This bit is set by one of the following conditions: The calling address
+ * matches the programmed primary slave address in the A1 register, or matches the
+ * range address in the RA register (which must be set to a nonzero value and under
+ * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
+ * received. SMB[SIICAEN] is set and the calling address matches the second programmed
+ * slave address. ALERTEN is set and an SMBus alert response address is received
+ * RMEN is set and an address is received that is within the range between the
+ * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
+ * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
+ * value clears this bit.
+ *
+ * Values:
+ * - 0b0 - Not addressed
+ * - 0b1 - Addressed as a slave
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_IAAS field. */
+#define I2C_RD_S_IAAS(base)  ((I2C_S_REG(base) & I2C_S_IAAS_MASK) >> I2C_S_IAAS_SHIFT)
+#define I2C_BRD_S_IAAS(base) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT))
+
+/*! @brief Set the IAAS field to a new value. */
+#define I2C_WR_S_IAAS(base, value) (I2C_RMW_S(base, (I2C_S_IAAS_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IAAS(value)))
+#define I2C_BWR_S_IAAS(base, value) (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_S, field TCF[7] (RO)
+ *
+ * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
+ * This bit is valid only during or immediately following a transfer to or from
+ * the I2C module. TCF is cleared by reading the I2C data register in receive mode
+ * or by writing to the I2C data register in transmit mode.
+ *
+ * Values:
+ * - 0b0 - Transfer in progress
+ * - 0b1 - Transfer complete
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_S_TCF field. */
+#define I2C_RD_S_TCF(base)   ((I2C_S_REG(base) & I2C_S_TCF_MASK) >> I2C_S_TCF_SHIFT)
+#define I2C_BRD_S_TCF(base)  (BITBAND_ACCESS8(&I2C_S_REG(base), I2C_S_TCF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_D - I2C Data I/O register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_D - I2C Data I/O register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_D register
+ */
+/*@{*/
+#define I2C_RD_D(base)           (I2C_D_REG(base))
+#define I2C_WR_D(base, value)    (I2C_D_REG(base) = (value))
+#define I2C_RMW_D(base, mask, value) (I2C_WR_D(base, (I2C_RD_D(base) & ~(mask)) | (value)))
+#define I2C_SET_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) |  (value)))
+#define I2C_CLR_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) & ~(value)))
+#define I2C_TOG_D(base, value)   (I2C_WR_D(base, I2C_RD_D(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_C2 - I2C Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_C2 - I2C Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_C2 register
+ */
+/*@{*/
+#define I2C_RD_C2(base)          (I2C_C2_REG(base))
+#define I2C_WR_C2(base, value)   (I2C_C2_REG(base) = (value))
+#define I2C_RMW_C2(base, mask, value) (I2C_WR_C2(base, (I2C_RD_C2(base) & ~(mask)) | (value)))
+#define I2C_SET_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) |  (value)))
+#define I2C_CLR_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) & ~(value)))
+#define I2C_TOG_C2(base, value)  (I2C_WR_C2(base, I2C_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_C2 bitfields
+ */
+
+/*!
+ * @name Register I2C_C2, field AD[2:0] (RW)
+ *
+ * Contains the upper three bits of the slave address in the 10-bit address
+ * scheme. This field is valid only while the ADEXT bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_AD field. */
+#define I2C_RD_C2_AD(base)   ((I2C_C2_REG(base) & I2C_C2_AD_MASK) >> I2C_C2_AD_SHIFT)
+#define I2C_BRD_C2_AD(base)  (I2C_RD_C2_AD(base))
+
+/*! @brief Set the AD field to a new value. */
+#define I2C_WR_C2_AD(base, value) (I2C_RMW_C2(base, I2C_C2_AD_MASK, I2C_C2_AD(value)))
+#define I2C_BWR_C2_AD(base, value) (I2C_WR_C2_AD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field RMEN[3] (RW)
+ *
+ * This bit controls the slave address matching for addresses between the values
+ * of the A1 and RA registers. When this bit is set, a slave address matching
+ * occurs for any address greater than the value of the A1 register and less than
+ * or equal to the value of the RA register.
+ *
+ * Values:
+ * - 0b0 - Range mode disabled. No address matching occurs for an address within
+ *     the range of values of the A1 and RA registers.
+ * - 0b1 - Range mode enabled. Address matching occurs when a slave receives an
+ *     address within the range of values of the A1 and RA registers.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_RMEN field. */
+#define I2C_RD_C2_RMEN(base) ((I2C_C2_REG(base) & I2C_C2_RMEN_MASK) >> I2C_C2_RMEN_SHIFT)
+#define I2C_BRD_C2_RMEN(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT))
+
+/*! @brief Set the RMEN field to a new value. */
+#define I2C_WR_C2_RMEN(base, value) (I2C_RMW_C2(base, I2C_C2_RMEN_MASK, I2C_C2_RMEN(value)))
+#define I2C_BWR_C2_RMEN(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field SBRC[4] (RW)
+ *
+ * Enables independent slave mode baud rate at maximum frequency, which forces
+ * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
+ * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
+ * capture the master's data at only 10 kbit/s.
+ *
+ * Values:
+ * - 0b0 - The slave baud rate follows the master baud rate and clock stretching
+ *     may occur
+ * - 0b1 - Slave baud rate is independent of the master baud rate
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_SBRC field. */
+#define I2C_RD_C2_SBRC(base) ((I2C_C2_REG(base) & I2C_C2_SBRC_MASK) >> I2C_C2_SBRC_SHIFT)
+#define I2C_BRD_C2_SBRC(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT))
+
+/*! @brief Set the SBRC field to a new value. */
+#define I2C_WR_C2_SBRC(base, value) (I2C_RMW_C2(base, I2C_C2_SBRC_MASK, I2C_C2_SBRC(value)))
+#define I2C_BWR_C2_SBRC(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field HDRS[5] (RW)
+ *
+ * Controls the drive capability of the I2C pads.
+ *
+ * Values:
+ * - 0b0 - Normal drive mode
+ * - 0b1 - High drive mode
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_HDRS field. */
+#define I2C_RD_C2_HDRS(base) ((I2C_C2_REG(base) & I2C_C2_HDRS_MASK) >> I2C_C2_HDRS_SHIFT)
+#define I2C_BRD_C2_HDRS(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT))
+
+/*! @brief Set the HDRS field to a new value. */
+#define I2C_WR_C2_HDRS(base, value) (I2C_RMW_C2(base, I2C_C2_HDRS_MASK, I2C_C2_HDRS(value)))
+#define I2C_BWR_C2_HDRS(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field ADEXT[6] (RW)
+ *
+ * Controls the number of bits used for the slave address.
+ *
+ * Values:
+ * - 0b0 - 7-bit address scheme
+ * - 0b1 - 10-bit address scheme
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_ADEXT field. */
+#define I2C_RD_C2_ADEXT(base) ((I2C_C2_REG(base) & I2C_C2_ADEXT_MASK) >> I2C_C2_ADEXT_SHIFT)
+#define I2C_BRD_C2_ADEXT(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT))
+
+/*! @brief Set the ADEXT field to a new value. */
+#define I2C_WR_C2_ADEXT(base, value) (I2C_RMW_C2(base, I2C_C2_ADEXT_MASK, I2C_C2_ADEXT(value)))
+#define I2C_BWR_C2_ADEXT(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_C2, field GCAEN[7] (RW)
+ *
+ * Enables general call address.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_C2_GCAEN field. */
+#define I2C_RD_C2_GCAEN(base) ((I2C_C2_REG(base) & I2C_C2_GCAEN_MASK) >> I2C_C2_GCAEN_SHIFT)
+#define I2C_BRD_C2_GCAEN(base) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT))
+
+/*! @brief Set the GCAEN field to a new value. */
+#define I2C_WR_C2_GCAEN(base, value) (I2C_RMW_C2(base, I2C_C2_GCAEN_MASK, I2C_C2_GCAEN(value)))
+#define I2C_BWR_C2_GCAEN(base, value) (BITBAND_ACCESS8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_FLT - I2C Programmable Input Glitch Filter register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_FLT register
+ */
+/*@{*/
+#define I2C_RD_FLT(base)         (I2C_FLT_REG(base))
+#define I2C_WR_FLT(base, value)  (I2C_FLT_REG(base) = (value))
+#define I2C_RMW_FLT(base, mask, value) (I2C_WR_FLT(base, (I2C_RD_FLT(base) & ~(mask)) | (value)))
+#define I2C_SET_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) |  (value)))
+#define I2C_CLR_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) & ~(value)))
+#define I2C_TOG_FLT(base, value) (I2C_WR_FLT(base, I2C_RD_FLT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_FLT bitfields
+ */
+
+/*!
+ * @name Register I2C_FLT, field FLT[3:0] (RW)
+ *
+ * Controls the width of the glitch, in terms of I2C module clock cycles, that
+ * the filter must absorb. For any glitch whose size is less than or equal to this
+ * width setting, the filter does not allow the glitch to pass.
+ *
+ * Values:
+ * - 0b0000 - No filter/bypass
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_FLT field. */
+#define I2C_RD_FLT_FLT(base) ((I2C_FLT_REG(base) & I2C_FLT_FLT_MASK) >> I2C_FLT_FLT_SHIFT)
+#define I2C_BRD_FLT_FLT(base) (I2C_RD_FLT_FLT(base))
+
+/*! @brief Set the FLT field to a new value. */
+#define I2C_WR_FLT_FLT(base, value) (I2C_RMW_FLT(base, (I2C_FLT_FLT_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_FLT(value)))
+#define I2C_BWR_FLT_FLT(base, value) (I2C_WR_FLT_FLT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STARTF[4] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's start status is detected. The
+ * STARTF bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No start happens on I2C bus
+ * - 0b1 - Start detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STARTF field. */
+#define I2C_RD_FLT_STARTF(base) ((I2C_FLT_REG(base) & I2C_FLT_STARTF_MASK) >> I2C_FLT_STARTF_SHIFT)
+#define I2C_BRD_FLT_STARTF(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT))
+
+/*! @brief Set the STARTF field to a new value. */
+#define I2C_WR_FLT_STARTF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_STARTF(value)))
+#define I2C_BWR_FLT_STARTF(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SSIE[5] (RW)
+ *
+ * This bit enables the interrupt for I2C bus stop or start detection. To clear
+ * the I2C bus stop or start detection interrupt: In the interrupt service
+ * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
+ * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
+ * is asserted again.
+ *
+ * Values:
+ * - 0b0 - Stop or start detection interrupt is disabled
+ * - 0b1 - Stop or start detection interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SSIE field. */
+#define I2C_RD_FLT_SSIE(base) ((I2C_FLT_REG(base) & I2C_FLT_SSIE_MASK) >> I2C_FLT_SSIE_SHIFT)
+#define I2C_BRD_FLT_SSIE(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT))
+
+/*! @brief Set the SSIE field to a new value. */
+#define I2C_WR_FLT_SSIE(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SSIE_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SSIE(value)))
+#define I2C_BWR_FLT_SSIE(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field STOPF[6] (W1C)
+ *
+ * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
+ * bit must be cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No stop happens on I2C bus
+ * - 0b1 - Stop detected on I2C bus
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_STOPF field. */
+#define I2C_RD_FLT_STOPF(base) ((I2C_FLT_REG(base) & I2C_FLT_STOPF_MASK) >> I2C_FLT_STOPF_SHIFT)
+#define I2C_BRD_FLT_STOPF(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT))
+
+/*! @brief Set the STOPF field to a new value. */
+#define I2C_WR_FLT_STOPF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK), I2C_FLT_STOPF(value)))
+#define I2C_BWR_FLT_STOPF(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_FLT, field SHEN[7] (RW)
+ *
+ * Set this bit to hold off entry to stop mode when any data transmission or
+ * reception is occurring. The following scenario explains the holdoff
+ * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
+ * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
+ * byte currently being transferred, including both address and data, completes
+ * its transfer. The I2C slave or master acknowledges that the in-transfer byte
+ * completed its transfer and acknowledges the request to enter stop mode. After
+ * receiving the I2C module's acknowledgment of the request to enter stop mode,
+ * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
+ * is set to 1 and the I2C module is in an idle or disabled state when the MCU
+ * signals to enter stop mode, the module immediately acknowledges the request to
+ * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
+ * reception that was suspended by stop mode entry was incomplete: To resume the
+ * overall transmission or reception after the MCU exits stop mode, software must
+ * reinitialize the transfer by resending the address of the slave. If the I2C
+ * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
+ * system software will receive the interrupt triggered by the I2C Status Register's
+ * TCF bit after the MCU wakes from the stop mode.
+ *
+ * Values:
+ * - 0b0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
+ * - 0b1 - Stop holdoff is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_FLT_SHEN field. */
+#define I2C_RD_FLT_SHEN(base) ((I2C_FLT_REG(base) & I2C_FLT_SHEN_MASK) >> I2C_FLT_SHEN_SHIFT)
+#define I2C_BRD_FLT_SHEN(base) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT))
+
+/*! @brief Set the SHEN field to a new value. */
+#define I2C_WR_FLT_SHEN(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SHEN_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SHEN(value)))
+#define I2C_BWR_FLT_SHEN(base, value) (BITBAND_ACCESS8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_RA - I2C Range Address register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_RA - I2C Range Address register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_RA register
+ */
+/*@{*/
+#define I2C_RD_RA(base)          (I2C_RA_REG(base))
+#define I2C_WR_RA(base, value)   (I2C_RA_REG(base) = (value))
+#define I2C_RMW_RA(base, mask, value) (I2C_WR_RA(base, (I2C_RD_RA(base) & ~(mask)) | (value)))
+#define I2C_SET_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) |  (value)))
+#define I2C_CLR_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) & ~(value)))
+#define I2C_TOG_RA(base, value)  (I2C_WR_RA(base, I2C_RD_RA(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_RA bitfields
+ */
+
+/*!
+ * @name Register I2C_RA, field RAD[7:1] (RW)
+ *
+ * This field contains the slave address to be used by the I2C module. The field
+ * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
+ * value write enables this register. This register value can be considered as a
+ * maximum boundary in the range matching mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_RA_RAD field. */
+#define I2C_RD_RA_RAD(base)  ((I2C_RA_REG(base) & I2C_RA_RAD_MASK) >> I2C_RA_RAD_SHIFT)
+#define I2C_BRD_RA_RAD(base) (I2C_RD_RA_RAD(base))
+
+/*! @brief Set the RAD field to a new value. */
+#define I2C_WR_RA_RAD(base, value) (I2C_RMW_RA(base, I2C_RA_RAD_MASK, I2C_RA_RAD(value)))
+#define I2C_BWR_RA_RAD(base, value) (I2C_WR_RA_RAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SMB - I2C SMBus Control and Status register
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SMB - I2C SMBus Control and Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * When the SCL and SDA signals are held high for a length of time greater than
+ * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
+ * while the system is detecting how long these signals are being held high, a
+ * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
+ * bus transmission process with the idle bus state. When the TCKSEL bit is set,
+ * there is no need to monitor the SHTF1 bit because the bus speed is too high to
+ * match the protocol of SMBus.
+ */
+/*!
+ * @name Constants and macros for entire I2C_SMB register
+ */
+/*@{*/
+#define I2C_RD_SMB(base)         (I2C_SMB_REG(base))
+#define I2C_WR_SMB(base, value)  (I2C_SMB_REG(base) = (value))
+#define I2C_RMW_SMB(base, mask, value) (I2C_WR_SMB(base, (I2C_RD_SMB(base) & ~(mask)) | (value)))
+#define I2C_SET_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) |  (value)))
+#define I2C_CLR_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) & ~(value)))
+#define I2C_TOG_SMB(base, value) (I2C_WR_SMB(base, I2C_RD_SMB(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_SMB bitfields
+ */
+
+/*!
+ * @name Register I2C_SMB, field SHTF2IE[0] (RW)
+ *
+ * Enables SCL high and SDA low timeout interrupt.
+ *
+ * Values:
+ * - 0b0 - SHTF2 interrupt is disabled
+ * - 0b1 - SHTF2 interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2IE field. */
+#define I2C_RD_SMB_SHTF2IE(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2IE_MASK) >> I2C_SMB_SHTF2IE_SHIFT)
+#define I2C_BRD_SMB_SHTF2IE(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT))
+
+/*! @brief Set the SHTF2IE field to a new value. */
+#define I2C_WR_SMB_SHTF2IE(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2IE_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2IE(value)))
+#define I2C_BWR_SMB_SHTF2IE(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF2[1] (W1C)
+ *
+ * This bit sets when SCL is held high and SDA is held low more than clock *
+ * LoValue / 512. Software clears this bit by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No SCL high and SDA low timeout occurs
+ * - 0b1 - SCL high and SDA low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF2 field. */
+#define I2C_RD_SMB_SHTF2(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2_MASK) >> I2C_SMB_SHTF2_SHIFT)
+#define I2C_BRD_SMB_SHTF2(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT))
+
+/*! @brief Set the SHTF2 field to a new value. */
+#define I2C_WR_SMB_SHTF2(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2(value)))
+#define I2C_BWR_SMB_SHTF2(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SHTF1[2] (RO)
+ *
+ * This read-only bit sets when SCL and SDA are held high more than clock *
+ * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
+ *
+ * Values:
+ * - 0b0 - No SCL high and SDA high timeout occurs
+ * - 0b1 - SCL high and SDA high timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SHTF1 field. */
+#define I2C_RD_SMB_SHTF1(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF1_MASK) >> I2C_SMB_SHTF1_SHIFT)
+#define I2C_BRD_SMB_SHTF1(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SHTF1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SLTF[3] (W1C)
+ *
+ * This bit is set when the SLT register (consisting of the SLTH and SLTL
+ * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
+ * Software clears this bit by writing a logic 1 to it. The low timeout function
+ * is disabled when the SLT register's value is 0.
+ *
+ * Values:
+ * - 0b0 - No low timeout occurs
+ * - 0b1 - Low timeout occurs
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SLTF field. */
+#define I2C_RD_SMB_SLTF(base) ((I2C_SMB_REG(base) & I2C_SMB_SLTF_MASK) >> I2C_SMB_SLTF_SHIFT)
+#define I2C_BRD_SMB_SLTF(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT))
+
+/*! @brief Set the SLTF field to a new value. */
+#define I2C_WR_SMB_SLTF(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SLTF_MASK | I2C_SMB_SHTF2_MASK), I2C_SMB_SLTF(value)))
+#define I2C_BWR_SMB_SLTF(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field TCKSEL[4] (RW)
+ *
+ * Selects the clock source of the timeout counter.
+ *
+ * Values:
+ * - 0b0 - Timeout counter counts at the frequency of the I2C module clock / 64
+ * - 0b1 - Timeout counter counts at the frequency of the I2C module clock
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_TCKSEL field. */
+#define I2C_RD_SMB_TCKSEL(base) ((I2C_SMB_REG(base) & I2C_SMB_TCKSEL_MASK) >> I2C_SMB_TCKSEL_SHIFT)
+#define I2C_BRD_SMB_TCKSEL(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT))
+
+/*! @brief Set the TCKSEL field to a new value. */
+#define I2C_WR_SMB_TCKSEL(base, value) (I2C_RMW_SMB(base, (I2C_SMB_TCKSEL_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_TCKSEL(value)))
+#define I2C_BWR_SMB_TCKSEL(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field SIICAEN[5] (RW)
+ *
+ * Enables or disables SMBus device default address.
+ *
+ * Values:
+ * - 0b0 - I2C address register 2 matching is disabled
+ * - 0b1 - I2C address register 2 matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_SIICAEN field. */
+#define I2C_RD_SMB_SIICAEN(base) ((I2C_SMB_REG(base) & I2C_SMB_SIICAEN_MASK) >> I2C_SMB_SIICAEN_SHIFT)
+#define I2C_BRD_SMB_SIICAEN(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT))
+
+/*! @brief Set the SIICAEN field to a new value. */
+#define I2C_WR_SMB_SIICAEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SIICAEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SIICAEN(value)))
+#define I2C_BWR_SMB_SIICAEN(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field ALERTEN[6] (RW)
+ *
+ * Enables or disables SMBus alert response address matching. After the host
+ * responds to a device that used the alert response address, you must use software
+ * to put the device's address on the bus. The alert protocol is described in the
+ * SMBus specification.
+ *
+ * Values:
+ * - 0b0 - SMBus alert response address matching is disabled
+ * - 0b1 - SMBus alert response address matching is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_ALERTEN field. */
+#define I2C_RD_SMB_ALERTEN(base) ((I2C_SMB_REG(base) & I2C_SMB_ALERTEN_MASK) >> I2C_SMB_ALERTEN_SHIFT)
+#define I2C_BRD_SMB_ALERTEN(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT))
+
+/*! @brief Set the ALERTEN field to a new value. */
+#define I2C_WR_SMB_ALERTEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_ALERTEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_ALERTEN(value)))
+#define I2C_BWR_SMB_ALERTEN(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2C_SMB, field FACK[7] (RW)
+ *
+ * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
+ * according to the result of receiving data byte.
+ *
+ * Values:
+ * - 0b0 - An ACK or NACK is sent on the following receiving data byte
+ * - 0b1 - Writing 0 to TXAK after receiving a data byte generates an ACK.
+ *     Writing 1 to TXAK after receiving a data byte generates a NACK.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_SMB_FACK field. */
+#define I2C_RD_SMB_FACK(base) ((I2C_SMB_REG(base) & I2C_SMB_FACK_MASK) >> I2C_SMB_FACK_SHIFT)
+#define I2C_BRD_SMB_FACK(base) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT))
+
+/*! @brief Set the FACK field to a new value. */
+#define I2C_WR_SMB_FACK(base, value) (I2C_RMW_SMB(base, (I2C_SMB_FACK_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_FACK(value)))
+#define I2C_BWR_SMB_FACK(base, value) (BITBAND_ACCESS8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_A2 - I2C Address Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_A2 - I2C Address Register 2 (RW)
+ *
+ * Reset value: 0xC2U
+ */
+/*!
+ * @name Constants and macros for entire I2C_A2 register
+ */
+/*@{*/
+#define I2C_RD_A2(base)          (I2C_A2_REG(base))
+#define I2C_WR_A2(base, value)   (I2C_A2_REG(base) = (value))
+#define I2C_RMW_A2(base, mask, value) (I2C_WR_A2(base, (I2C_RD_A2(base) & ~(mask)) | (value)))
+#define I2C_SET_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) |  (value)))
+#define I2C_CLR_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) & ~(value)))
+#define I2C_TOG_A2(base, value)  (I2C_WR_A2(base, I2C_RD_A2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2C_A2 bitfields
+ */
+
+/*!
+ * @name Register I2C_A2, field SAD[7:1] (RW)
+ *
+ * Contains the slave address used by the SMBus. This field is used on the
+ * device default address or other related addresses.
+ */
+/*@{*/
+/*! @brief Read current value of the I2C_A2_SAD field. */
+#define I2C_RD_A2_SAD(base)  ((I2C_A2_REG(base) & I2C_A2_SAD_MASK) >> I2C_A2_SAD_SHIFT)
+#define I2C_BRD_A2_SAD(base) (I2C_RD_A2_SAD(base))
+
+/*! @brief Set the SAD field to a new value. */
+#define I2C_WR_A2_SAD(base, value) (I2C_RMW_A2(base, I2C_A2_SAD_MASK, I2C_A2_SAD(value)))
+#define I2C_BWR_A2_SAD(base, value) (I2C_WR_A2_SAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTH - I2C SCL Low Timeout Register High
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTH - I2C SCL Low Timeout Register High (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTH register
+ */
+/*@{*/
+#define I2C_RD_SLTH(base)        (I2C_SLTH_REG(base))
+#define I2C_WR_SLTH(base, value) (I2C_SLTH_REG(base) = (value))
+#define I2C_RMW_SLTH(base, mask, value) (I2C_WR_SLTH(base, (I2C_RD_SLTH(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) |  (value)))
+#define I2C_CLR_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) & ~(value)))
+#define I2C_TOG_SLTH(base, value) (I2C_WR_SLTH(base, I2C_RD_SLTH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2C_SLTL - I2C SCL Low Timeout Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire I2C_SLTL register
+ */
+/*@{*/
+#define I2C_RD_SLTL(base)        (I2C_SLTL_REG(base))
+#define I2C_WR_SLTL(base, value) (I2C_SLTL_REG(base) = (value))
+#define I2C_RMW_SLTL(base, mask, value) (I2C_WR_SLTL(base, (I2C_RD_SLTL(base) & ~(mask)) | (value)))
+#define I2C_SET_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) |  (value)))
+#define I2C_CLR_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) & ~(value)))
+#define I2C_TOG_SLTL(base, value) (I2C_WR_SLTL(base, I2C_RD_SLTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 I2S
+ *
+ * Inter-IC Sound / Synchronous Audio Interface
+ *
+ * Registers defined in this header file:
+ * - I2S_TCSR - SAI Transmit Control Register
+ * - I2S_TCR1 - SAI Transmit Configuration 1 Register
+ * - I2S_TCR2 - SAI Transmit Configuration 2 Register
+ * - I2S_TCR3 - SAI Transmit Configuration 3 Register
+ * - I2S_TCR4 - SAI Transmit Configuration 4 Register
+ * - I2S_TCR5 - SAI Transmit Configuration 5 Register
+ * - I2S_TDR - SAI Transmit Data Register
+ * - I2S_TFR - SAI Transmit FIFO Register
+ * - I2S_TMR - SAI Transmit Mask Register
+ * - I2S_RCSR - SAI Receive Control Register
+ * - I2S_RCR1 - SAI Receive Configuration 1 Register
+ * - I2S_RCR2 - SAI Receive Configuration 2 Register
+ * - I2S_RCR3 - SAI Receive Configuration 3 Register
+ * - I2S_RCR4 - SAI Receive Configuration 4 Register
+ * - I2S_RCR5 - SAI Receive Configuration 5 Register
+ * - I2S_RDR - SAI Receive Data Register
+ * - I2S_RFR - SAI Receive FIFO Register
+ * - I2S_RMR - SAI Receive Mask Register
+ * - I2S_MCR - SAI MCLK Control Register
+ * - I2S_MDR - SAI MCLK Divide Register
+ */
+
+#define I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */
+#define I2S0_IDX (0U) /*!< Instance number for I2S0. */
+
+/*******************************************************************************
+ * I2S_TCSR - SAI Transmit Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCSR - SAI Transmit Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCSR register
+ */
+/*@{*/
+#define I2S_RD_TCSR(base)        (I2S_TCSR_REG(base))
+#define I2S_WR_TCSR(base, value) (I2S_TCSR_REG(base) = (value))
+#define I2S_RMW_TCSR(base, mask, value) (I2S_WR_TCSR(base, (I2S_RD_TCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) |  (value)))
+#define I2S_CLR_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) & ~(value)))
+#define I2S_TOG_TCSR(base, value) (I2S_WR_TCSR(base, I2S_RD_TCSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_TCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRDE field. */
+#define I2S_RD_TCSR_FRDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRDE_MASK) >> I2S_TCSR_FRDE_SHIFT)
+#define I2S_BRD_TCSR_FRDE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRDE_SHIFT))
+
+/*! @brief Set the FRDE field to a new value. */
+#define I2S_WR_TCSR_FRDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FRDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FRDE(value)))
+#define I2S_BWR_TCSR_FRDE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWDE field. */
+#define I2S_RD_TCSR_FWDE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWDE_MASK) >> I2S_TCSR_FWDE_SHIFT)
+#define I2S_BRD_TCSR_FWDE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_TCSR_FWDE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWDE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWDE(value)))
+#define I2S_BWR_TCSR_FWDE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRIE field. */
+#define I2S_RD_TCSR_FRIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRIE_MASK) >> I2S_TCSR_FRIE_SHIFT)
+#define I2S_BRD_TCSR_FRIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRIE_SHIFT))
+
+/*! @brief Set the FRIE field to a new value. */
+#define I2S_WR_TCSR_FRIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FRIE(value)))
+#define I2S_BWR_TCSR_FRIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWIE field. */
+#define I2S_RD_TCSR_FWIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWIE_MASK) >> I2S_TCSR_FWIE_SHIFT)
+#define I2S_BRD_TCSR_FWIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_TCSR_FWIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FWIE(value)))
+#define I2S_BWR_TCSR_FWIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEIE field. */
+#define I2S_RD_TCSR_FEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEIE_MASK) >> I2S_TCSR_FEIE_SHIFT)
+#define I2S_BRD_TCSR_FEIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_TCSR_FEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEIE(value)))
+#define I2S_BWR_TCSR_FEIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEIE field. */
+#define I2S_RD_TCSR_SEIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEIE_MASK) >> I2S_TCSR_SEIE_SHIFT)
+#define I2S_BRD_TCSR_SEIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_TCSR_SEIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEIE(value)))
+#define I2S_BWR_TCSR_SEIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSIE field. */
+#define I2S_RD_TCSR_WSIE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSIE_MASK) >> I2S_TCSR_WSIE_SHIFT)
+#define I2S_BRD_TCSR_WSIE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_TCSR_WSIE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSIE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_WSIE(value)))
+#define I2S_BWR_TCSR_WSIE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled transmit channel FIFO is
+ * less than or equal to the transmit FIFO watermark.
+ *
+ * Values:
+ * - 0b0 - Transmit FIFO watermark has not been reached.
+ * - 0b1 - Transmit FIFO watermark has been reached.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FRF field. */
+#define I2S_RD_TCSR_FRF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FRF_MASK) >> I2S_TCSR_FRF_SHIFT)
+#define I2S_BRD_TCSR_FRF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled transmit FIFO is empty.
+ *
+ * Values:
+ * - 0b0 - No enabled transmit FIFO is empty.
+ * - 0b1 - Enabled transmit FIFO is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FWF field. */
+#define I2S_RD_TCSR_FWF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FWF_MASK) >> I2S_TCSR_FWF_SHIFT)
+#define I2S_BRD_TCSR_FWF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FWF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
+ * field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Transmit underrun not detected.
+ * - 0b1 - Transmit underrun detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_FEF field. */
+#define I2S_RD_TCSR_FEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_FEF_MASK) >> I2S_TCSR_FEF_SHIFT)
+#define I2S_BRD_TCSR_FEF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_TCSR_FEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FEF(value)))
+#define I2S_BWR_TCSR_FEF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Sync error not detected.
+ * - 0b1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SEF field. */
+#define I2S_RD_TCSR_SEF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SEF_MASK) >> I2S_TCSR_SEF_SHIFT)
+#define I2S_BRD_TCSR_SEF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_TCSR_SEF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SEF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SEF(value)))
+#define I2S_BWR_TCSR_SEF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Start of word not detected.
+ * - 0b1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_WSF field. */
+#define I2S_RD_TCSR_WSF(base) ((I2S_TCSR_REG(base) & I2S_TCSR_WSF_MASK) >> I2S_TCSR_WSF_SHIFT)
+#define I2S_BRD_TCSR_WSF(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_TCSR_WSF(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_WSF_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK), I2S_TCSR_WSF(value)))
+#define I2S_BWR_TCSR_WSF(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_WSF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field SR[24] (RW)
+ *
+ * When set, resets the internal transmitter logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_SR field. */
+#define I2S_RD_TCSR_SR(base) ((I2S_TCSR_REG(base) & I2S_TCSR_SR_MASK) >> I2S_TCSR_SR_SHIFT)
+#define I2S_BRD_TCSR_SR(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_TCSR_SR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_SR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_SR(value)))
+#define I2S_BWR_TCSR_SR(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_SR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the transmitter is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_TCSR_FR(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_FR_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_FR(value)))
+#define I2S_BWR_TCSR_FR(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_FR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field BCE[28] (RW)
+ *
+ * Enables the transmit bit clock, separately from the TE. This field is
+ * automatically set whenever TE is set. When software clears this field, the transmit
+ * bit clock remains enabled, and this bit remains set, until the end of the
+ * current frame.
+ *
+ * Values:
+ * - 0b0 - Transmit bit clock is disabled.
+ * - 0b1 - Transmit bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_BCE field. */
+#define I2S_RD_TCSR_BCE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_BCE_MASK) >> I2S_TCSR_BCE_SHIFT)
+#define I2S_BRD_TCSR_BCE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_TCSR_BCE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_BCE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_BCE(value)))
+#define I2S_BWR_TCSR_BCE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_BCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables transmitter operation in Debug mode. The transmit bit clock
+ * is not affected by debug mode.
+ *
+ * Values:
+ * - 0b0 - Transmitter is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 0b1 - Transmitter is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_DBGE field. */
+#define I2S_RD_TCSR_DBGE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_DBGE_MASK) >> I2S_TCSR_DBGE_SHIFT)
+#define I2S_BRD_TCSR_DBGE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_TCSR_DBGE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_DBGE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_DBGE(value)))
+#define I2S_BWR_TCSR_DBGE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_DBGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field STOPE[30] (RW)
+ *
+ * Configures transmitter operation in Stop mode. This field is ignored and the
+ * transmitter is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0b0 - Transmitter disabled in Stop mode.
+ * - 0b1 - Transmitter enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_STOPE field. */
+#define I2S_RD_TCSR_STOPE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_STOPE_MASK) >> I2S_TCSR_STOPE_SHIFT)
+#define I2S_BRD_TCSR_STOPE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_TCSR_STOPE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_STOPE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_STOPE(value)))
+#define I2S_BWR_TCSR_STOPE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_STOPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCSR, field TE[31] (RW)
+ *
+ * Enables/disables the transmitter. When software clears this field, the
+ * transmitter remains enabled, and this bit remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0b0 - Transmitter is disabled.
+ * - 0b1 - Transmitter is enabled, or transmitter has been disabled and has not
+ *     yet reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCSR_TE field. */
+#define I2S_RD_TCSR_TE(base) ((I2S_TCSR_REG(base) & I2S_TCSR_TE_MASK) >> I2S_TCSR_TE_SHIFT)
+#define I2S_BRD_TCSR_TE(base) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT))
+
+/*! @brief Set the TE field to a new value. */
+#define I2S_WR_TCSR_TE(base, value) (I2S_RMW_TCSR(base, (I2S_TCSR_TE_MASK | I2S_TCSR_FEF_MASK | I2S_TCSR_SEF_MASK | I2S_TCSR_WSF_MASK), I2S_TCSR_TE(value)))
+#define I2S_BWR_TCSR_TE(base, value) (BITBAND_ACCESS32(&I2S_TCSR_REG(base), I2S_TCSR_TE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR1 - SAI Transmit Configuration 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR1 register
+ */
+/*@{*/
+#define I2S_RD_TCR1(base)        (I2S_TCR1_REG(base))
+#define I2S_WR_TCR1(base, value) (I2S_TCR1_REG(base) = (value))
+#define I2S_RMW_TCR1(base, mask, value) (I2S_WR_TCR1(base, (I2S_RD_TCR1(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) |  (value)))
+#define I2S_CLR_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) & ~(value)))
+#define I2S_TOG_TCR1(base, value) (I2S_WR_TCR1(base, I2S_RD_TCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR1, field TFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled transmit channels.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR1_TFW field. */
+#define I2S_RD_TCR1_TFW(base) ((I2S_TCR1_REG(base) & I2S_TCR1_TFW_MASK) >> I2S_TCR1_TFW_SHIFT)
+#define I2S_BRD_TCR1_TFW(base) (I2S_RD_TCR1_TFW(base))
+
+/*! @brief Set the TFW field to a new value. */
+#define I2S_WR_TCR1_TFW(base, value) (I2S_RMW_TCR1(base, I2S_TCR1_TFW_MASK, I2S_TCR1_TFW(value)))
+#define I2S_BWR_TCR1_TFW(base, value) (I2S_WR_TCR1_TFW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR2 - SAI Transmit Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR2 register
+ */
+/*@{*/
+#define I2S_RD_TCR2(base)        (I2S_TCR2_REG(base))
+#define I2S_WR_TCR2(base, value) (I2S_TCR2_REG(base) = (value))
+#define I2S_RMW_TCR2(base, mask, value) (I2S_WR_TCR2(base, (I2S_RD_TCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) |  (value)))
+#define I2S_CLR_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) & ~(value)))
+#define I2S_TOG_TCR2(base, value) (I2S_WR_TCR2(base, I2S_RD_TCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_DIV field. */
+#define I2S_RD_TCR2_DIV(base) ((I2S_TCR2_REG(base) & I2S_TCR2_DIV_MASK) >> I2S_TCR2_DIV_SHIFT)
+#define I2S_BRD_TCR2_DIV(base) (I2S_RD_TCR2_DIV(base))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_TCR2_DIV(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_DIV_MASK, I2S_TCR2_DIV(value)))
+#define I2S_BWR_TCR2_DIV(base, value) (I2S_WR_TCR2_DIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is generated externally in Slave mode.
+ * - 0b1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCD field. */
+#define I2S_RD_TCR2_BCD(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCD_MASK) >> I2S_TCR2_BCD_SHIFT)
+#define I2S_BRD_TCR2_BCD(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_TCR2_BCD(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCD_MASK, I2S_TCR2_BCD(value)))
+#define I2S_BWR_TCR2_BCD(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 0b1 - Bit clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCP field. */
+#define I2S_RD_TCR2_BCP(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCP_MASK) >> I2S_TCR2_BCP_SHIFT)
+#define I2S_BRD_TCR2_BCP(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_TCR2_BCP(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCP_MASK, I2S_TCR2_BCP(value)))
+#define I2S_BWR_TCR2_BCP(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 0b00 - Bus Clock selected.
+ * - 0b01 - Master Clock (MCLK) 1 option selected.
+ * - 0b10 - Master Clock (MCLK) 2 option selected.
+ * - 0b11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_MSEL field. */
+#define I2S_RD_TCR2_MSEL(base) ((I2S_TCR2_REG(base) & I2S_TCR2_MSEL_MASK) >> I2S_TCR2_MSEL_SHIFT)
+#define I2S_BRD_TCR2_MSEL(base) (I2S_RD_TCR2_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_TCR2_MSEL(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_MSEL_MASK, I2S_TCR2_MSEL(value)))
+#define I2S_BWR_TCR2_MSEL(base, value) (I2S_WR_TCR2_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the
+ * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
+ * input as if the clock was externally generated). This has the effect of
+ * decreasing the data input setup time, but increasing the data output valid time. The
+ * slave mode timing from the datasheet should be used for the transmitter when
+ * this bit is set. In synchronous mode, this bit allows the transmitter to use
+ * the slave mode timing from the datasheet, while the receiver uses the master
+ * mode timing. This field has no effect when configured for an externally generated
+ * bit clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCI field. */
+#define I2S_RD_TCR2_BCI(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCI_MASK) >> I2S_TCR2_BCI_SHIFT)
+#define I2S_BRD_TCR2_BCI(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_TCR2_BCI(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCI_MASK, I2S_TCR2_BCI(value)))
+#define I2S_BWR_TCR2_BCI(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the transmitter. When the transmitter
+ * is configured in asynchronous mode and this bit is set, the transmitter is
+ * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the transmitter continues to use the
+ * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
+ * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
+ * the same value. When both are set, the transmitter and receiver are both
+ * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
+ * (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
+ * peripheral.
+ *
+ * Values:
+ * - 0b0 - Use the normal bit clock source.
+ * - 0b1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_BCS field. */
+#define I2S_RD_TCR2_BCS(base) ((I2S_TCR2_REG(base) & I2S_TCR2_BCS_MASK) >> I2S_TCR2_BCS_SHIFT)
+#define I2S_BRD_TCR2_BCS(base) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_TCR2_BCS(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_BCS_MASK, I2S_TCR2_BCS(value)))
+#define I2S_BWR_TCR2_BCS(base, value) (BITBAND_ACCESS32(&I2S_TCR2_REG(base), I2S_TCR2_BCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the receiver or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 0b00 - Asynchronous mode.
+ * - 0b01 - Synchronous with receiver.
+ * - 0b10 - Synchronous with another SAI transmitter.
+ * - 0b11 - Synchronous with another SAI receiver.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR2_SYNC field. */
+#define I2S_RD_TCR2_SYNC(base) ((I2S_TCR2_REG(base) & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT)
+#define I2S_BRD_TCR2_SYNC(base) (I2S_RD_TCR2_SYNC(base))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_TCR2_SYNC(base, value) (I2S_RMW_TCR2(base, I2S_TCR2_SYNC_MASK, I2S_TCR2_SYNC(value)))
+#define I2S_BWR_TCR2_SYNC(base, value) (I2S_WR_TCR2_SYNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR3 - SAI Transmit Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR3 register
+ */
+/*@{*/
+#define I2S_RD_TCR3(base)        (I2S_TCR3_REG(base))
+#define I2S_WR_TCR3(base, value) (I2S_TCR3_REG(base) = (value))
+#define I2S_RMW_TCR3(base, mask, value) (I2S_WR_TCR3(base, (I2S_RD_TCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) |  (value)))
+#define I2S_CLR_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) & ~(value)))
+#define I2S_TOG_TCR3(base, value) (I2S_WR_TCR3(base, I2S_RD_TCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word sets the start of word flag. The value written must be
+ * one less than the word number. For example, writing 0 configures the first
+ * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
+ * start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_WDFL field. */
+#define I2S_RD_TCR3_WDFL(base) ((I2S_TCR3_REG(base) & I2S_TCR3_WDFL_MASK) >> I2S_TCR3_WDFL_SHIFT)
+#define I2S_BRD_TCR3_WDFL(base) (I2S_RD_TCR3_WDFL(base))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_TCR3_WDFL(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_WDFL_MASK, I2S_TCR3_WDFL(value)))
+#define I2S_BWR_TCR3_WDFL(base, value) (I2S_WR_TCR3_WDFL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR3, field TCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for transmit operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0b00 - Transmit data channel N is disabled.
+ * - 0b01 - Transmit data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR3_TCE field. */
+#define I2S_RD_TCR3_TCE(base) ((I2S_TCR3_REG(base) & I2S_TCR3_TCE_MASK) >> I2S_TCR3_TCE_SHIFT)
+#define I2S_BRD_TCR3_TCE(base) (I2S_RD_TCR3_TCE(base))
+
+/*! @brief Set the TCE field to a new value. */
+#define I2S_WR_TCR3_TCE(base, value) (I2S_RMW_TCR3(base, I2S_TCR3_TCE_MASK, I2S_TCR3_TCE(value)))
+#define I2S_BWR_TCR3_TCE(base, value) (I2S_WR_TCR3_TCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR4 - SAI Transmit Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR4 register
+ */
+/*@{*/
+#define I2S_RD_TCR4(base)        (I2S_TCR4_REG(base))
+#define I2S_WR_TCR4(base, value) (I2S_TCR4_REG(base) = (value))
+#define I2S_RMW_TCR4(base, mask, value) (I2S_WR_TCR4(base, (I2S_RD_TCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) |  (value)))
+#define I2S_CLR_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) & ~(value)))
+#define I2S_TOG_TCR4(base, value) (I2S_WR_TCR4(base, I2S_RD_TCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is generated externally in Slave mode.
+ * - 0b1 - Frame sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSD field. */
+#define I2S_RD_TCR4_FSD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSD_MASK) >> I2S_TCR4_FSD_SHIFT)
+#define I2S_BRD_TCR4_FSD(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_TCR4_FSD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSD_MASK, I2S_TCR4_FSD(value)))
+#define I2S_BWR_TCR4_FSD(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is active high.
+ * - 0b1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSP field. */
+#define I2S_RD_TCR4_FSP(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSP_MASK) >> I2S_TCR4_FSP_SHIFT)
+#define I2S_BRD_TCR4_FSP(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_TCR4_FSP(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSP_MASK, I2S_TCR4_FSP(value)))
+#define I2S_BWR_TCR4_FSP(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Frame sync asserts with the first bit of the frame.
+ * - 0b1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FSE field. */
+#define I2S_RD_TCR4_FSE(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FSE_MASK) >> I2S_TCR4_FSE_SHIFT)
+#define I2S_BRD_TCR4_FSE(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_TCR4_FSE(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FSE_MASK, I2S_TCR4_FSE(value)))
+#define I2S_BWR_TCR4_FSE(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_FSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is transmitted first.
+ *
+ * Values:
+ * - 0b0 - LSB is transmitted first.
+ * - 0b1 - MSB is transmitted first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_MF field. */
+#define I2S_RD_TCR4_MF(base) ((I2S_TCR4_REG(base) & I2S_TCR4_MF_MASK) >> I2S_TCR4_MF_SHIFT)
+#define I2S_BRD_TCR4_MF(base) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_TCR4_MF(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_MF_MASK, I2S_TCR4_MF(value)))
+#define I2S_BWR_TCR4_MF(base, value) (BITBAND_ACCESS32(&I2S_TCR4_REG(base), I2S_TCR4_MF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_SYWD field. */
+#define I2S_RD_TCR4_SYWD(base) ((I2S_TCR4_REG(base) & I2S_TCR4_SYWD_MASK) >> I2S_TCR4_SYWD_SHIFT)
+#define I2S_BRD_TCR4_SYWD(base) (I2S_RD_TCR4_SYWD(base))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_TCR4_SYWD(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_SYWD_MASK, I2S_TCR4_SYWD(value)))
+#define I2S_BWR_TCR4_SYWD(base, value) (I2S_WR_TCR4_SYWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR4_FRSZ field. */
+#define I2S_RD_TCR4_FRSZ(base) ((I2S_TCR4_REG(base) & I2S_TCR4_FRSZ_MASK) >> I2S_TCR4_FRSZ_SHIFT)
+#define I2S_BRD_TCR4_FRSZ(base) (I2S_RD_TCR4_FRSZ(base))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_TCR4_FRSZ(base, value) (I2S_RMW_TCR4(base, I2S_TCR4_FRSZ_MASK, I2S_TCR4_FRSZ(value)))
+#define I2S_BWR_TCR4_FRSZ(base, value) (I2S_WR_TCR4_FRSZ(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TCR5 - SAI Transmit Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when TCSR[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TCR5 register
+ */
+/*@{*/
+#define I2S_RD_TCR5(base)        (I2S_TCR5_REG(base))
+#define I2S_WR_TCR5(base, value) (I2S_TCR5_REG(base) = (value))
+#define I2S_RMW_TCR5(base, mask, value) (I2S_WR_TCR5(base, (I2S_RD_TCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) |  (value)))
+#define I2S_CLR_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) & ~(value)))
+#define I2S_TOG_TCR5(base, value) (I2S_WR_TCR5(base, I2S_RD_TCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_TCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit transmitted for each word in the
+ * frame. If configured for MSB First, the index of the next bit transmitted is
+ * one less than the current bit transmitted. If configured for LSB First, the
+ * index of the next bit transmitted is one more than the current bit transmitted.
+ * The value written must be greater than or equal to the word width when
+ * configured for MSB First. The value written must be less than or equal to 31-word width
+ * when configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_FBT field. */
+#define I2S_RD_TCR5_FBT(base) ((I2S_TCR5_REG(base) & I2S_TCR5_FBT_MASK) >> I2S_TCR5_FBT_SHIFT)
+#define I2S_BRD_TCR5_FBT(base) (I2S_RD_TCR5_FBT(base))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_TCR5_FBT(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_FBT_MASK, I2S_TCR5_FBT(value)))
+#define I2S_BWR_TCR5_FBT(base, value) (I2S_WR_TCR5_FBT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_W0W field. */
+#define I2S_RD_TCR5_W0W(base) ((I2S_TCR5_REG(base) & I2S_TCR5_W0W_MASK) >> I2S_TCR5_W0W_SHIFT)
+#define I2S_BRD_TCR5_W0W(base) (I2S_RD_TCR5_W0W(base))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_TCR5_W0W(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_W0W_MASK, I2S_TCR5_W0W(value)))
+#define I2S_BWR_TCR5_W0W(base, value) (I2S_WR_TCR5_W0W(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_TCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TCR5_WNW field. */
+#define I2S_RD_TCR5_WNW(base) ((I2S_TCR5_REG(base) & I2S_TCR5_WNW_MASK) >> I2S_TCR5_WNW_SHIFT)
+#define I2S_BRD_TCR5_WNW(base) (I2S_RD_TCR5_WNW(base))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_TCR5_WNW(base, value) (I2S_RMW_TCR5(base, I2S_TCR5_WNW_MASK, I2S_TCR5_WNW(value)))
+#define I2S_BWR_TCR5_WNW(base, value) (I2S_WR_TCR5_WNW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TDR - SAI Transmit Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TDR - SAI Transmit Data Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_TDR register
+ */
+/*@{*/
+#define I2S_RD_TDR(base, index)  (I2S_TDR_REG(base, index))
+#define I2S_WR_TDR(base, index, value) (I2S_TDR_REG(base, index) = (value))
+#define I2S_RMW_TDR(base, index, mask, value) (I2S_WR_TDR(base, index, (I2S_RD_TDR(base, index) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TFR - SAI Transmit FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TFR - SAI Transmit FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TFR register
+ */
+/*@{*/
+#define I2S_RD_TFR(base, index)  (I2S_TFR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_TFR bitfields
+ */
+
+/*!
+ * @name Register I2S_TFR, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for transmit data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TFR_RFP field. */
+#define I2S_RD_TFR_RFP(base, index) ((I2S_TFR_REG(base, index) & I2S_TFR_RFP_MASK) >> I2S_TFR_RFP_SHIFT)
+#define I2S_BRD_TFR_RFP(base, index) (I2S_RD_TFR_RFP(base, index))
+/*@}*/
+
+/*!
+ * @name Register I2S_TFR, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for transmit data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_TFR_WFP field. */
+#define I2S_RD_TFR_WFP(base, index) ((I2S_TFR_REG(base, index) & I2S_TFR_WFP_MASK) >> I2S_TFR_WFP_SHIFT)
+#define I2S_BRD_TFR_WFP(base, index) (I2S_RD_TFR_WFP(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_TMR - SAI Transmit Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_TMR - SAI Transmit Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When TCSR[TE] is first set At
+ * the end of each frame. This allows the masked words in each frame to change
+ * from frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_TMR register
+ */
+/*@{*/
+#define I2S_RD_TMR(base)         (I2S_TMR_REG(base))
+#define I2S_WR_TMR(base, value)  (I2S_TMR_REG(base) = (value))
+#define I2S_RMW_TMR(base, mask, value) (I2S_WR_TMR(base, (I2S_RD_TMR(base) & ~(mask)) | (value)))
+#define I2S_SET_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) |  (value)))
+#define I2S_CLR_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) & ~(value)))
+#define I2S_TOG_TMR(base, value) (I2S_WR_TMR(base, I2S_RD_TMR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCSR - SAI Receive Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCSR - SAI Receive Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCSR register
+ */
+/*@{*/
+#define I2S_RD_RCSR(base)        (I2S_RCSR_REG(base))
+#define I2S_WR_RCSR(base, value) (I2S_RCSR_REG(base) = (value))
+#define I2S_RMW_RCSR(base, mask, value) (I2S_WR_RCSR(base, (I2S_RD_RCSR(base) & ~(mask)) | (value)))
+#define I2S_SET_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) |  (value)))
+#define I2S_CLR_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) & ~(value)))
+#define I2S_TOG_RCSR(base, value) (I2S_WR_RCSR(base, I2S_RD_RCSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCSR bitfields
+ */
+
+/*!
+ * @name Register I2S_RCSR, field FRDE[0] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRDE field. */
+#define I2S_RD_RCSR_FRDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRDE_MASK) >> I2S_RCSR_FRDE_SHIFT)
+#define I2S_BRD_RCSR_FRDE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRDE_SHIFT))
+
+/*! @brief Set the FRDE field to a new value. */
+#define I2S_WR_RCSR_FRDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FRDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FRDE(value)))
+#define I2S_BWR_RCSR_FRDE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWDE[1] (RW)
+ *
+ * Enables/disables DMA requests.
+ *
+ * Values:
+ * - 0b0 - Disables the DMA request.
+ * - 0b1 - Enables the DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWDE field. */
+#define I2S_RD_RCSR_FWDE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWDE_MASK) >> I2S_RCSR_FWDE_SHIFT)
+#define I2S_BRD_RCSR_FWDE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT))
+
+/*! @brief Set the FWDE field to a new value. */
+#define I2S_WR_RCSR_FWDE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWDE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWDE(value)))
+#define I2S_BWR_RCSR_FWDE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FRIE[8] (RW)
+ *
+ * Enables/disables FIFO request interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRIE field. */
+#define I2S_RD_RCSR_FRIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRIE_MASK) >> I2S_RCSR_FRIE_SHIFT)
+#define I2S_BRD_RCSR_FRIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRIE_SHIFT))
+
+/*! @brief Set the FRIE field to a new value. */
+#define I2S_WR_RCSR_FRIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FRIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FRIE(value)))
+#define I2S_BWR_RCSR_FRIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWIE[9] (RW)
+ *
+ * Enables/disables FIFO warning interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWIE field. */
+#define I2S_RD_RCSR_FWIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWIE_MASK) >> I2S_RCSR_FWIE_SHIFT)
+#define I2S_BRD_RCSR_FWIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT))
+
+/*! @brief Set the FWIE field to a new value. */
+#define I2S_WR_RCSR_FWIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FWIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FWIE(value)))
+#define I2S_BWR_RCSR_FWIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEIE[10] (RW)
+ *
+ * Enables/disables FIFO error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables the interrupt.
+ * - 0b1 - Enables the interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEIE field. */
+#define I2S_RD_RCSR_FEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEIE_MASK) >> I2S_RCSR_FEIE_SHIFT)
+#define I2S_BRD_RCSR_FEIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define I2S_WR_RCSR_FEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEIE(value)))
+#define I2S_BWR_RCSR_FEIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEIE[11] (RW)
+ *
+ * Enables/disables sync error interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEIE field. */
+#define I2S_RD_RCSR_SEIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEIE_MASK) >> I2S_RCSR_SEIE_SHIFT)
+#define I2S_BRD_RCSR_SEIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT))
+
+/*! @brief Set the SEIE field to a new value. */
+#define I2S_WR_RCSR_SEIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEIE(value)))
+#define I2S_BWR_RCSR_SEIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSIE[12] (RW)
+ *
+ * Enables/disables word start interrupts.
+ *
+ * Values:
+ * - 0b0 - Disables interrupt.
+ * - 0b1 - Enables interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSIE field. */
+#define I2S_RD_RCSR_WSIE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSIE_MASK) >> I2S_RCSR_WSIE_SHIFT)
+#define I2S_BRD_RCSR_WSIE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT))
+
+/*! @brief Set the WSIE field to a new value. */
+#define I2S_WR_RCSR_WSIE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSIE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_WSIE(value)))
+#define I2S_BWR_RCSR_WSIE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FRF[16] (RO)
+ *
+ * Indicates that the number of words in an enabled receive channel FIFO is
+ * greater than the receive FIFO watermark.
+ *
+ * Values:
+ * - 0b0 - Receive FIFO watermark not reached.
+ * - 0b1 - Receive FIFO watermark has been reached.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FRF field. */
+#define I2S_RD_RCSR_FRF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FRF_MASK) >> I2S_RCSR_FRF_SHIFT)
+#define I2S_BRD_RCSR_FRF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FWF[17] (RO)
+ *
+ * Indicates that an enabled receive FIFO is full.
+ *
+ * Values:
+ * - 0b0 - No enabled receive FIFO is full.
+ * - 0b1 - Enabled receive FIFO is full.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FWF field. */
+#define I2S_RD_RCSR_FWF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FWF_MASK) >> I2S_RCSR_FWF_SHIFT)
+#define I2S_BRD_RCSR_FWF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FWF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FEF[18] (W1C)
+ *
+ * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
+ * this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Receive overflow not detected.
+ * - 0b1 - Receive overflow detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_FEF field. */
+#define I2S_RD_RCSR_FEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_FEF_MASK) >> I2S_RCSR_FEF_SHIFT)
+#define I2S_BRD_RCSR_FEF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT))
+
+/*! @brief Set the FEF field to a new value. */
+#define I2S_WR_RCSR_FEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FEF(value)))
+#define I2S_BWR_RCSR_FEF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SEF[19] (W1C)
+ *
+ * Indicates that an error in the externally-generated frame sync has been
+ * detected. Write a logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Sync error not detected.
+ * - 0b1 - Frame sync error detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SEF field. */
+#define I2S_RD_RCSR_SEF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SEF_MASK) >> I2S_RCSR_SEF_SHIFT)
+#define I2S_BRD_RCSR_SEF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT))
+
+/*! @brief Set the SEF field to a new value. */
+#define I2S_WR_RCSR_SEF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SEF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SEF(value)))
+#define I2S_BWR_RCSR_SEF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SEF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field WSF[20] (W1C)
+ *
+ * Indicates that the start of the configured word has been detected. Write a
+ * logic 1 to this field to clear this flag.
+ *
+ * Values:
+ * - 0b0 - Start of word not detected.
+ * - 0b1 - Start of word detected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_WSF field. */
+#define I2S_RD_RCSR_WSF(base) ((I2S_RCSR_REG(base) & I2S_RCSR_WSF_MASK) >> I2S_RCSR_WSF_SHIFT)
+#define I2S_BRD_RCSR_WSF(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT))
+
+/*! @brief Set the WSF field to a new value. */
+#define I2S_WR_RCSR_WSF(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_WSF_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK), I2S_RCSR_WSF(value)))
+#define I2S_BWR_RCSR_WSF(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_WSF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field SR[24] (RW)
+ *
+ * Resets the internal receiver logic including the FIFO pointers.
+ * Software-visible registers are not affected, except for the status registers.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Software reset.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_SR field. */
+#define I2S_RD_RCSR_SR(base) ((I2S_RCSR_REG(base) & I2S_RCSR_SR_MASK) >> I2S_RCSR_SR_SHIFT)
+#define I2S_BRD_RCSR_SR(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT))
+
+/*! @brief Set the SR field to a new value. */
+#define I2S_WR_RCSR_SR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_SR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_SR(value)))
+#define I2S_BWR_RCSR_SR(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_SR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field FR[25] (WORZ)
+ *
+ * Resets the FIFO pointers. Reading this field will always return zero. FIFO
+ * pointers should only be reset when the receiver is disabled or the FIFO error
+ * flag is set.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - FIFO reset.
+ */
+/*@{*/
+/*! @brief Set the FR field to a new value. */
+#define I2S_WR_RCSR_FR(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_FR_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_FR(value)))
+#define I2S_BWR_RCSR_FR(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_FR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field BCE[28] (RW)
+ *
+ * Enables the receive bit clock, separately from RE. This field is
+ * automatically set whenever RE is set. When software clears this field, the receive bit
+ * clock remains enabled, and this field remains set, until the end of the current
+ * frame.
+ *
+ * Values:
+ * - 0b0 - Receive bit clock is disabled.
+ * - 0b1 - Receive bit clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_BCE field. */
+#define I2S_RD_RCSR_BCE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_BCE_MASK) >> I2S_RCSR_BCE_SHIFT)
+#define I2S_BRD_RCSR_BCE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT))
+
+/*! @brief Set the BCE field to a new value. */
+#define I2S_WR_RCSR_BCE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_BCE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_BCE(value)))
+#define I2S_BWR_RCSR_BCE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_BCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field DBGE[29] (RW)
+ *
+ * Enables/disables receiver operation in Debug mode. The receive bit clock is
+ * not affected by Debug mode.
+ *
+ * Values:
+ * - 0b0 - Receiver is disabled in Debug mode, after completing the current
+ *     frame.
+ * - 0b1 - Receiver is enabled in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_DBGE field. */
+#define I2S_RD_RCSR_DBGE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_DBGE_MASK) >> I2S_RCSR_DBGE_SHIFT)
+#define I2S_BRD_RCSR_DBGE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT))
+
+/*! @brief Set the DBGE field to a new value. */
+#define I2S_WR_RCSR_DBGE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_DBGE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_DBGE(value)))
+#define I2S_BWR_RCSR_DBGE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_DBGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field STOPE[30] (RW)
+ *
+ * Configures receiver operation in Stop mode. This bit is ignored and the
+ * receiver is disabled in all low-leakage stop modes.
+ *
+ * Values:
+ * - 0b0 - Receiver disabled in Stop mode.
+ * - 0b1 - Receiver enabled in Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_STOPE field. */
+#define I2S_RD_RCSR_STOPE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_STOPE_MASK) >> I2S_RCSR_STOPE_SHIFT)
+#define I2S_BRD_RCSR_STOPE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT))
+
+/*! @brief Set the STOPE field to a new value. */
+#define I2S_WR_RCSR_STOPE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_STOPE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_STOPE(value)))
+#define I2S_BWR_RCSR_STOPE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_STOPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCSR, field RE[31] (RW)
+ *
+ * Enables/disables the receiver. When software clears this field, the receiver
+ * remains enabled, and this bit remains set, until the end of the current frame.
+ *
+ * Values:
+ * - 0b0 - Receiver is disabled.
+ * - 0b1 - Receiver is enabled, or receiver has been disabled and has not yet
+ *     reached end of frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCSR_RE field. */
+#define I2S_RD_RCSR_RE(base) ((I2S_RCSR_REG(base) & I2S_RCSR_RE_MASK) >> I2S_RCSR_RE_SHIFT)
+#define I2S_BRD_RCSR_RE(base) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT))
+
+/*! @brief Set the RE field to a new value. */
+#define I2S_WR_RCSR_RE(base, value) (I2S_RMW_RCSR(base, (I2S_RCSR_RE_MASK | I2S_RCSR_FEF_MASK | I2S_RCSR_SEF_MASK | I2S_RCSR_WSF_MASK), I2S_RCSR_RE(value)))
+#define I2S_BWR_RCSR_RE(base, value) (BITBAND_ACCESS32(&I2S_RCSR_REG(base), I2S_RCSR_RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR1 - SAI Receive Configuration 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR1 register
+ */
+/*@{*/
+#define I2S_RD_RCR1(base)        (I2S_RCR1_REG(base))
+#define I2S_WR_RCR1(base, value) (I2S_RCR1_REG(base) = (value))
+#define I2S_RMW_RCR1(base, mask, value) (I2S_WR_RCR1(base, (I2S_RD_RCR1(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) |  (value)))
+#define I2S_CLR_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) & ~(value)))
+#define I2S_TOG_RCR1(base, value) (I2S_WR_RCR1(base, I2S_RD_RCR1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR1 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR1, field RFW[2:0] (RW)
+ *
+ * Configures the watermark level for all enabled receiver channels.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR1_RFW field. */
+#define I2S_RD_RCR1_RFW(base) ((I2S_RCR1_REG(base) & I2S_RCR1_RFW_MASK) >> I2S_RCR1_RFW_SHIFT)
+#define I2S_BRD_RCR1_RFW(base) (I2S_RD_RCR1_RFW(base))
+
+/*! @brief Set the RFW field to a new value. */
+#define I2S_WR_RCR1_RFW(base, value) (I2S_RMW_RCR1(base, I2S_RCR1_RFW_MASK, I2S_RCR1_RFW(value)))
+#define I2S_BWR_RCR1_RFW(base, value) (I2S_WR_RCR1_RFW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR2 - SAI Receive Configuration 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR2 register
+ */
+/*@{*/
+#define I2S_RD_RCR2(base)        (I2S_RCR2_REG(base))
+#define I2S_WR_RCR2(base, value) (I2S_RCR2_REG(base) = (value))
+#define I2S_RMW_RCR2(base, mask, value) (I2S_WR_RCR2(base, (I2S_RD_RCR2(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) |  (value)))
+#define I2S_CLR_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) & ~(value)))
+#define I2S_TOG_RCR2(base, value) (I2S_WR_RCR2(base, I2S_RD_RCR2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR2 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR2, field DIV[7:0] (RW)
+ *
+ * Divides down the audio master clock to generate the bit clock when configured
+ * for an internal bit clock. The division value is (DIV + 1) * 2.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_DIV field. */
+#define I2S_RD_RCR2_DIV(base) ((I2S_RCR2_REG(base) & I2S_RCR2_DIV_MASK) >> I2S_RCR2_DIV_SHIFT)
+#define I2S_BRD_RCR2_DIV(base) (I2S_RD_RCR2_DIV(base))
+
+/*! @brief Set the DIV field to a new value. */
+#define I2S_WR_RCR2_DIV(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_DIV_MASK, I2S_RCR2_DIV(value)))
+#define I2S_BWR_RCR2_DIV(base, value) (I2S_WR_RCR2_DIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCD[24] (RW)
+ *
+ * Configures the direction of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit clock is generated externally in Slave mode.
+ * - 0b1 - Bit clock is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCD field. */
+#define I2S_RD_RCR2_BCD(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCD_MASK) >> I2S_RCR2_BCD_SHIFT)
+#define I2S_BRD_RCR2_BCD(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT))
+
+/*! @brief Set the BCD field to a new value. */
+#define I2S_WR_RCR2_BCD(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCD_MASK, I2S_RCR2_BCD(value)))
+#define I2S_BWR_RCR2_BCD(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCP[25] (RW)
+ *
+ * Configures the polarity of the bit clock.
+ *
+ * Values:
+ * - 0b0 - Bit Clock is active high with drive outputs on rising edge and sample
+ *     inputs on falling edge.
+ * - 0b1 - Bit Clock is active low with drive outputs on falling edge and sample
+ *     inputs on rising edge.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCP field. */
+#define I2S_RD_RCR2_BCP(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCP_MASK) >> I2S_RCR2_BCP_SHIFT)
+#define I2S_BRD_RCR2_BCP(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT))
+
+/*! @brief Set the BCP field to a new value. */
+#define I2S_WR_RCR2_BCP(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCP_MASK, I2S_RCR2_BCP(value)))
+#define I2S_BWR_RCR2_BCP(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field MSEL[27:26] (RW)
+ *
+ * Selects the audio Master Clock option used to generate an internally
+ * generated bit clock. This field has no effect when configured for an externally
+ * generated bit clock. Depending on the device, some Master Clock options might not be
+ * available. See the chip configuration details for the availability and
+ * chip-specific meaning of each option.
+ *
+ * Values:
+ * - 0b00 - Bus Clock selected.
+ * - 0b01 - Master Clock (MCLK) 1 option selected.
+ * - 0b10 - Master Clock (MCLK) 2 option selected.
+ * - 0b11 - Master Clock (MCLK) 3 option selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_MSEL field. */
+#define I2S_RD_RCR2_MSEL(base) ((I2S_RCR2_REG(base) & I2S_RCR2_MSEL_MASK) >> I2S_RCR2_MSEL_SHIFT)
+#define I2S_BRD_RCR2_MSEL(base) (I2S_RD_RCR2_MSEL(base))
+
+/*! @brief Set the MSEL field to a new value. */
+#define I2S_WR_RCR2_MSEL(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_MSEL_MASK, I2S_RCR2_MSEL(value)))
+#define I2S_BWR_RCR2_MSEL(base, value) (I2S_WR_RCR2_MSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCI[28] (RW)
+ *
+ * When this field is set and using an internally generated bit clock in either
+ * synchronous or asynchronous mode, the bit clock actually used by the receiver
+ * is delayed by the pad output delay (the receiver is clocked by the pad input
+ * as if the clock was externally generated). This has the effect of decreasing
+ * the data input setup time, but increasing the data output valid time. The slave
+ * mode timing from the datasheet should be used for the receiver when this bit
+ * is set. In synchronous mode, this bit allows the receiver to use the slave mode
+ * timing from the datasheet, while the transmitter uses the master mode timing.
+ * This field has no effect when configured for an externally generated bit
+ * clock or when synchronous to another SAI peripheral .
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Internal logic is clocked as if bit clock was externally generated.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCI field. */
+#define I2S_RD_RCR2_BCI(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCI_MASK) >> I2S_RCR2_BCI_SHIFT)
+#define I2S_BRD_RCR2_BCI(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT))
+
+/*! @brief Set the BCI field to a new value. */
+#define I2S_WR_RCR2_BCI(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCI_MASK, I2S_RCR2_BCI(value)))
+#define I2S_BWR_RCR2_BCI(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field BCS[29] (RW)
+ *
+ * This field swaps the bit clock used by the receiver. When the receiver is
+ * configured in asynchronous mode and this bit is set, the receiver is clocked by
+ * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
+ * receiver to share the same bit clock, but the receiver continues to use the receiver
+ * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
+ * mode, the transmitter BCS field and receiver BCS field must be set to the same
+ * value. When both are set, the transmitter and receiver are both clocked by the
+ * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
+ * (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
+ *
+ * Values:
+ * - 0b0 - Use the normal bit clock source.
+ * - 0b1 - Swap the bit clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_BCS field. */
+#define I2S_RD_RCR2_BCS(base) ((I2S_RCR2_REG(base) & I2S_RCR2_BCS_MASK) >> I2S_RCR2_BCS_SHIFT)
+#define I2S_BRD_RCR2_BCS(base) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT))
+
+/*! @brief Set the BCS field to a new value. */
+#define I2S_WR_RCR2_BCS(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_BCS_MASK, I2S_RCR2_BCS(value)))
+#define I2S_BWR_RCR2_BCS(base, value) (BITBAND_ACCESS32(&I2S_RCR2_REG(base), I2S_RCR2_BCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR2, field SYNC[31:30] (RW)
+ *
+ * Configures between asynchronous and synchronous modes of operation. When
+ * configured for a synchronous mode of operation, the transmitter or other SAI
+ * peripheral must be configured for asynchronous operation.
+ *
+ * Values:
+ * - 0b00 - Asynchronous mode.
+ * - 0b01 - Synchronous with transmitter.
+ * - 0b10 - Synchronous with another SAI receiver.
+ * - 0b11 - Synchronous with another SAI transmitter.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR2_SYNC field. */
+#define I2S_RD_RCR2_SYNC(base) ((I2S_RCR2_REG(base) & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT)
+#define I2S_BRD_RCR2_SYNC(base) (I2S_RD_RCR2_SYNC(base))
+
+/*! @brief Set the SYNC field to a new value. */
+#define I2S_WR_RCR2_SYNC(base, value) (I2S_RMW_RCR2(base, I2S_RCR2_SYNC_MASK, I2S_RCR2_SYNC(value)))
+#define I2S_BWR_RCR2_SYNC(base, value) (I2S_WR_RCR2_SYNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR3 - SAI Receive Configuration 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR3 register
+ */
+/*@{*/
+#define I2S_RD_RCR3(base)        (I2S_RCR3_REG(base))
+#define I2S_WR_RCR3(base, value) (I2S_RCR3_REG(base) = (value))
+#define I2S_RMW_RCR3(base, mask, value) (I2S_WR_RCR3(base, (I2S_RD_RCR3(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) |  (value)))
+#define I2S_CLR_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) & ~(value)))
+#define I2S_TOG_RCR3(base, value) (I2S_WR_RCR3(base, I2S_RD_RCR3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR3 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR3, field WDFL[4:0] (RW)
+ *
+ * Configures which word the start of word flag is set. The value written should
+ * be one less than the word number (for example, write zero to configure for
+ * the first word in the frame). When configured to a value greater than the Frame
+ * Size field, then the start of word flag is never set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_WDFL field. */
+#define I2S_RD_RCR3_WDFL(base) ((I2S_RCR3_REG(base) & I2S_RCR3_WDFL_MASK) >> I2S_RCR3_WDFL_SHIFT)
+#define I2S_BRD_RCR3_WDFL(base) (I2S_RD_RCR3_WDFL(base))
+
+/*! @brief Set the WDFL field to a new value. */
+#define I2S_WR_RCR3_WDFL(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_WDFL_MASK, I2S_RCR3_WDFL(value)))
+#define I2S_BWR_RCR3_WDFL(base, value) (I2S_WR_RCR3_WDFL(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR3, field RCE[17:16] (RW)
+ *
+ * Enables the corresponding data channel for receive operation. A channel must
+ * be enabled before its FIFO is accessed.
+ *
+ * Values:
+ * - 0b00 - Receive data channel N is disabled.
+ * - 0b01 - Receive data channel N is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR3_RCE field. */
+#define I2S_RD_RCR3_RCE(base) ((I2S_RCR3_REG(base) & I2S_RCR3_RCE_MASK) >> I2S_RCR3_RCE_SHIFT)
+#define I2S_BRD_RCR3_RCE(base) (I2S_RD_RCR3_RCE(base))
+
+/*! @brief Set the RCE field to a new value. */
+#define I2S_WR_RCR3_RCE(base, value) (I2S_RMW_RCR3(base, I2S_RCR3_RCE_MASK, I2S_RCR3_RCE(value)))
+#define I2S_BWR_RCR3_RCE(base, value) (I2S_WR_RCR3_RCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR4 - SAI Receive Configuration 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR4 register
+ */
+/*@{*/
+#define I2S_RD_RCR4(base)        (I2S_RCR4_REG(base))
+#define I2S_WR_RCR4(base, value) (I2S_RCR4_REG(base) = (value))
+#define I2S_RMW_RCR4(base, mask, value) (I2S_WR_RCR4(base, (I2S_RD_RCR4(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) |  (value)))
+#define I2S_CLR_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) & ~(value)))
+#define I2S_TOG_RCR4(base, value) (I2S_WR_RCR4(base, I2S_RD_RCR4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR4 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR4, field FSD[0] (RW)
+ *
+ * Configures the direction of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame Sync is generated externally in Slave mode.
+ * - 0b1 - Frame Sync is generated internally in Master mode.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSD field. */
+#define I2S_RD_RCR4_FSD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSD_MASK) >> I2S_RCR4_FSD_SHIFT)
+#define I2S_BRD_RCR4_FSD(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT))
+
+/*! @brief Set the FSD field to a new value. */
+#define I2S_WR_RCR4_FSD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSD_MASK, I2S_RCR4_FSD(value)))
+#define I2S_BWR_RCR4_FSD(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSP[1] (RW)
+ *
+ * Configures the polarity of the frame sync.
+ *
+ * Values:
+ * - 0b0 - Frame sync is active high.
+ * - 0b1 - Frame sync is active low.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSP field. */
+#define I2S_RD_RCR4_FSP(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSP_MASK) >> I2S_RCR4_FSP_SHIFT)
+#define I2S_BRD_RCR4_FSP(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT))
+
+/*! @brief Set the FSP field to a new value. */
+#define I2S_WR_RCR4_FSP(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSP_MASK, I2S_RCR4_FSP(value)))
+#define I2S_BWR_RCR4_FSP(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FSE[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Frame sync asserts with the first bit of the frame.
+ * - 0b1 - Frame sync asserts one bit before the first bit of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FSE field. */
+#define I2S_RD_RCR4_FSE(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FSE_MASK) >> I2S_RCR4_FSE_SHIFT)
+#define I2S_BRD_RCR4_FSE(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT))
+
+/*! @brief Set the FSE field to a new value. */
+#define I2S_WR_RCR4_FSE(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FSE_MASK, I2S_RCR4_FSE(value)))
+#define I2S_BWR_RCR4_FSE(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_FSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field MF[4] (RW)
+ *
+ * Configures whether the LSB or the MSB is received first.
+ *
+ * Values:
+ * - 0b0 - LSB is received first.
+ * - 0b1 - MSB is received first.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_MF field. */
+#define I2S_RD_RCR4_MF(base) ((I2S_RCR4_REG(base) & I2S_RCR4_MF_MASK) >> I2S_RCR4_MF_SHIFT)
+#define I2S_BRD_RCR4_MF(base) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT))
+
+/*! @brief Set the MF field to a new value. */
+#define I2S_WR_RCR4_MF(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_MF_MASK, I2S_RCR4_MF(value)))
+#define I2S_BWR_RCR4_MF(base, value) (BITBAND_ACCESS32(&I2S_RCR4_REG(base), I2S_RCR4_MF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field SYWD[12:8] (RW)
+ *
+ * Configures the length of the frame sync in number of bit clocks. The value
+ * written must be one less than the number of bit clocks. For example, write 0 for
+ * the frame sync to assert for one bit clock only. The sync width cannot be
+ * configured longer than the first word of the frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_SYWD field. */
+#define I2S_RD_RCR4_SYWD(base) ((I2S_RCR4_REG(base) & I2S_RCR4_SYWD_MASK) >> I2S_RCR4_SYWD_SHIFT)
+#define I2S_BRD_RCR4_SYWD(base) (I2S_RD_RCR4_SYWD(base))
+
+/*! @brief Set the SYWD field to a new value. */
+#define I2S_WR_RCR4_SYWD(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_SYWD_MASK, I2S_RCR4_SYWD(value)))
+#define I2S_BWR_RCR4_SYWD(base, value) (I2S_WR_RCR4_SYWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR4, field FRSZ[20:16] (RW)
+ *
+ * Configures the number of words in each frame. The value written must be one
+ * less than the number of words in the frame. For example, write 0 for one word
+ * per frame. The maximum supported frame size is 32 words.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR4_FRSZ field. */
+#define I2S_RD_RCR4_FRSZ(base) ((I2S_RCR4_REG(base) & I2S_RCR4_FRSZ_MASK) >> I2S_RCR4_FRSZ_SHIFT)
+#define I2S_BRD_RCR4_FRSZ(base) (I2S_RD_RCR4_FRSZ(base))
+
+/*! @brief Set the FRSZ field to a new value. */
+#define I2S_WR_RCR4_FRSZ(base, value) (I2S_RMW_RCR4(base, I2S_RCR4_FRSZ_MASK, I2S_RCR4_FRSZ(value)))
+#define I2S_BWR_RCR4_FRSZ(base, value) (I2S_WR_RCR4_FRSZ(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RCR5 - SAI Receive Configuration 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register must not be altered when RCSR[RE] is set.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RCR5 register
+ */
+/*@{*/
+#define I2S_RD_RCR5(base)        (I2S_RCR5_REG(base))
+#define I2S_WR_RCR5(base, value) (I2S_RCR5_REG(base) = (value))
+#define I2S_RMW_RCR5(base, mask, value) (I2S_WR_RCR5(base, (I2S_RD_RCR5(base) & ~(mask)) | (value)))
+#define I2S_SET_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) |  (value)))
+#define I2S_CLR_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) & ~(value)))
+#define I2S_TOG_RCR5(base, value) (I2S_WR_RCR5(base, I2S_RD_RCR5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RCR5 bitfields
+ */
+
+/*!
+ * @name Register I2S_RCR5, field FBT[12:8] (RW)
+ *
+ * Configures the bit index for the first bit received for each word in the
+ * frame. If configured for MSB First, the index of the next bit received is one less
+ * than the current bit received. If configured for LSB First, the index of the
+ * next bit received is one more than the current bit received. The value written
+ * must be greater than or equal to the word width when configured for MSB
+ * First. The value written must be less than or equal to 31-word width when
+ * configured for LSB First.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_FBT field. */
+#define I2S_RD_RCR5_FBT(base) ((I2S_RCR5_REG(base) & I2S_RCR5_FBT_MASK) >> I2S_RCR5_FBT_SHIFT)
+#define I2S_BRD_RCR5_FBT(base) (I2S_RD_RCR5_FBT(base))
+
+/*! @brief Set the FBT field to a new value. */
+#define I2S_WR_RCR5_FBT(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_FBT_MASK, I2S_RCR5_FBT(value)))
+#define I2S_BWR_RCR5_FBT(base, value) (I2S_WR_RCR5_FBT(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field W0W[20:16] (RW)
+ *
+ * Configures the number of bits in the first word in each frame. The value
+ * written must be one less than the number of bits in the first word. Word width of
+ * less than 8 bits is not supported if there is only one word per frame.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_W0W field. */
+#define I2S_RD_RCR5_W0W(base) ((I2S_RCR5_REG(base) & I2S_RCR5_W0W_MASK) >> I2S_RCR5_W0W_SHIFT)
+#define I2S_BRD_RCR5_W0W(base) (I2S_RD_RCR5_W0W(base))
+
+/*! @brief Set the W0W field to a new value. */
+#define I2S_WR_RCR5_W0W(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_W0W_MASK, I2S_RCR5_W0W(value)))
+#define I2S_BWR_RCR5_W0W(base, value) (I2S_WR_RCR5_W0W(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_RCR5, field WNW[28:24] (RW)
+ *
+ * Configures the number of bits in each word, for each word except the first in
+ * the frame. The value written must be one less than the number of bits per
+ * word. Word width of less than 8 bits is not supported.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RCR5_WNW field. */
+#define I2S_RD_RCR5_WNW(base) ((I2S_RCR5_REG(base) & I2S_RCR5_WNW_MASK) >> I2S_RCR5_WNW_SHIFT)
+#define I2S_BRD_RCR5_WNW(base) (I2S_RD_RCR5_WNW(base))
+
+/*! @brief Set the WNW field to a new value. */
+#define I2S_WR_RCR5_WNW(base, value) (I2S_RMW_RCR5(base, I2S_RCR5_WNW_MASK, I2S_RCR5_WNW(value)))
+#define I2S_BWR_RCR5_WNW(base, value) (I2S_WR_RCR5_WNW(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RDR - SAI Receive Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RDR - SAI Receive Data Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Reading this register introduces one additional peripheral clock wait state
+ * on each read.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RDR register
+ */
+/*@{*/
+#define I2S_RD_RDR(base, index)  (I2S_RDR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RFR - SAI Receive FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RFR - SAI Receive FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MSB of the read and write pointers is used to distinguish between FIFO
+ * full and empty conditions. If the read and write pointers are identical, then
+ * the FIFO is empty. If the read and write pointers are identical except for the
+ * MSB, then the FIFO is full.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RFR register
+ */
+/*@{*/
+#define I2S_RD_RFR(base, index)  (I2S_RFR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_RFR bitfields
+ */
+
+/*!
+ * @name Register I2S_RFR, field RFP[3:0] (RO)
+ *
+ * FIFO read pointer for receive data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RFR_RFP field. */
+#define I2S_RD_RFR_RFP(base, index) ((I2S_RFR_REG(base, index) & I2S_RFR_RFP_MASK) >> I2S_RFR_RFP_SHIFT)
+#define I2S_BRD_RFR_RFP(base, index) (I2S_RD_RFR_RFP(base, index))
+/*@}*/
+
+/*!
+ * @name Register I2S_RFR, field WFP[19:16] (RO)
+ *
+ * FIFO write pointer for receive data channel.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_RFR_WFP field. */
+#define I2S_RD_RFR_WFP(base, index) ((I2S_RFR_REG(base, index) & I2S_RFR_WFP_MASK) >> I2S_RFR_WFP_SHIFT)
+#define I2S_BRD_RFR_WFP(base, index) (I2S_RD_RFR_WFP(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_RMR - SAI Receive Mask Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_RMR - SAI Receive Mask Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is double-buffered and updates: When RCSR[RE] is first set At
+ * the end of each frame This allows the masked words in each frame to change from
+ * frame to frame.
+ */
+/*!
+ * @name Constants and macros for entire I2S_RMR register
+ */
+/*@{*/
+#define I2S_RD_RMR(base)         (I2S_RMR_REG(base))
+#define I2S_WR_RMR(base, value)  (I2S_RMR_REG(base) = (value))
+#define I2S_RMW_RMR(base, mask, value) (I2S_WR_RMR(base, (I2S_RD_RMR(base) & ~(mask)) | (value)))
+#define I2S_SET_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) |  (value)))
+#define I2S_CLR_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) & ~(value)))
+#define I2S_TOG_RMR(base, value) (I2S_WR_RMR(base, I2S_RD_RMR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MCR - SAI MCLK Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MCR - SAI MCLK Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Control Register (MCR) controls the clock source and direction of
+ * the audio master clock.
+ */
+/*!
+ * @name Constants and macros for entire I2S_MCR register
+ */
+/*@{*/
+#define I2S_RD_MCR(base)         (I2S_MCR_REG(base))
+#define I2S_WR_MCR(base, value)  (I2S_MCR_REG(base) = (value))
+#define I2S_RMW_MCR(base, mask, value) (I2S_WR_MCR(base, (I2S_RD_MCR(base) & ~(mask)) | (value)))
+#define I2S_SET_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) |  (value)))
+#define I2S_CLR_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) & ~(value)))
+#define I2S_TOG_MCR(base, value) (I2S_WR_MCR(base, I2S_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MCR bitfields
+ */
+
+/*!
+ * @name Register I2S_MCR, field MICS[25:24] (RW)
+ *
+ * Selects the clock input to the MCLK divider. This field cannot be changed
+ * while the MCLK divider is enabled. See the chip configuration details for
+ * information about the connections to these inputs.
+ *
+ * Values:
+ * - 0b00 - MCLK divider input clock 0 selected.
+ * - 0b01 - MCLK divider input clock 1 selected.
+ * - 0b10 - MCLK divider input clock 2 selected.
+ * - 0b11 - MCLK divider input clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MICS field. */
+#define I2S_RD_MCR_MICS(base) ((I2S_MCR_REG(base) & I2S_MCR_MICS_MASK) >> I2S_MCR_MICS_SHIFT)
+#define I2S_BRD_MCR_MICS(base) (I2S_RD_MCR_MICS(base))
+
+/*! @brief Set the MICS field to a new value. */
+#define I2S_WR_MCR_MICS(base, value) (I2S_RMW_MCR(base, I2S_MCR_MICS_MASK, I2S_MCR_MICS(value)))
+#define I2S_BWR_MCR_MICS(base, value) (I2S_WR_MCR_MICS(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field MOE[30] (RW)
+ *
+ * Enables the MCLK divider and configures the MCLK signal pin as an output.
+ * When software clears this field, it remains set until the MCLK divider is fully
+ * disabled.
+ *
+ * Values:
+ * - 0b0 - MCLK signal pin is configured as an input that bypasses the MCLK
+ *     divider.
+ * - 0b1 - MCLK signal pin is configured as an output from the MCLK divider and
+ *     the MCLK divider is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_MOE field. */
+#define I2S_RD_MCR_MOE(base) ((I2S_MCR_REG(base) & I2S_MCR_MOE_MASK) >> I2S_MCR_MOE_SHIFT)
+#define I2S_BRD_MCR_MOE(base) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT))
+
+/*! @brief Set the MOE field to a new value. */
+#define I2S_WR_MCR_MOE(base, value) (I2S_RMW_MCR(base, I2S_MCR_MOE_MASK, I2S_MCR_MOE(value)))
+#define I2S_BWR_MCR_MOE(base, value) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_MOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MCR, field DUF[31] (RO)
+ *
+ * Provides the status of on-the-fly updates to the MCLK divider ratio.
+ *
+ * Values:
+ * - 0b0 - MCLK divider ratio is not being updated currently.
+ * - 0b1 - MCLK divider ratio is updating on-the-fly. Further updates to the
+ *     MCLK divider ratio are blocked while this flag remains set.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MCR_DUF field. */
+#define I2S_RD_MCR_DUF(base) ((I2S_MCR_REG(base) & I2S_MCR_DUF_MASK) >> I2S_MCR_DUF_SHIFT)
+#define I2S_BRD_MCR_DUF(base) (BITBAND_ACCESS32(&I2S_MCR_REG(base), I2S_MCR_DUF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * I2S_MDR - SAI MCLK Divide Register
+ ******************************************************************************/
+
+/*!
+ * @brief I2S_MDR - SAI MCLK Divide Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
+ * MDR can be changed when the MCLK divider clock is enabled, additional writes
+ * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
+ * divided clock is disabled do not set MCR[DUF].
+ */
+/*!
+ * @name Constants and macros for entire I2S_MDR register
+ */
+/*@{*/
+#define I2S_RD_MDR(base)         (I2S_MDR_REG(base))
+#define I2S_WR_MDR(base, value)  (I2S_MDR_REG(base) = (value))
+#define I2S_RMW_MDR(base, mask, value) (I2S_WR_MDR(base, (I2S_RD_MDR(base) & ~(mask)) | (value)))
+#define I2S_SET_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) |  (value)))
+#define I2S_CLR_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) & ~(value)))
+#define I2S_TOG_MDR(base, value) (I2S_WR_MDR(base, I2S_RD_MDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual I2S_MDR bitfields
+ */
+
+/*!
+ * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MDR_DIVIDE field. */
+#define I2S_RD_MDR_DIVIDE(base) ((I2S_MDR_REG(base) & I2S_MDR_DIVIDE_MASK) >> I2S_MDR_DIVIDE_SHIFT)
+#define I2S_BRD_MDR_DIVIDE(base) (I2S_RD_MDR_DIVIDE(base))
+
+/*! @brief Set the DIVIDE field to a new value. */
+#define I2S_WR_MDR_DIVIDE(base, value) (I2S_RMW_MDR(base, I2S_MDR_DIVIDE_MASK, I2S_MDR_DIVIDE(value)))
+#define I2S_BWR_MDR_DIVIDE(base, value) (I2S_WR_MDR_DIVIDE(base, value))
+/*@}*/
+
+/*!
+ * @name Register I2S_MDR, field FRACT[19:12] (RW)
+ *
+ * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
+ * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
+ * DIVIDE field.
+ */
+/*@{*/
+/*! @brief Read current value of the I2S_MDR_FRACT field. */
+#define I2S_RD_MDR_FRACT(base) ((I2S_MDR_REG(base) & I2S_MDR_FRACT_MASK) >> I2S_MDR_FRACT_SHIFT)
+#define I2S_BRD_MDR_FRACT(base) (I2S_RD_MDR_FRACT(base))
+
+/*! @brief Set the FRACT field to a new value. */
+#define I2S_WR_MDR_FRACT(base, value) (I2S_RMW_MDR(base, I2S_MDR_FRACT_MASK, I2S_MDR_FRACT(value)))
+#define I2S_BWR_MDR_FRACT(base, value) (I2S_WR_MDR_FRACT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 LLWU
+ *
+ * Low leakage wakeup unit
+ *
+ * Registers defined in this header file:
+ * - LLWU_PE1 - LLWU Pin Enable 1 register
+ * - LLWU_PE2 - LLWU Pin Enable 2 register
+ * - LLWU_PE3 - LLWU Pin Enable 3 register
+ * - LLWU_PE4 - LLWU Pin Enable 4 register
+ * - LLWU_ME - LLWU Module Enable register
+ * - LLWU_F1 - LLWU Flag 1 register
+ * - LLWU_F2 - LLWU Flag 2 register
+ * - LLWU_F3 - LLWU Flag 3 register
+ * - LLWU_FILT1 - LLWU Pin Filter 1 register
+ * - LLWU_FILT2 - LLWU Pin Filter 2 register
+ * - LLWU_RST - LLWU Reset Enable register
+ */
+
+#define LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
+#define LLWU_IDX (0U) /*!< Instance number for LLWU. */
+
+/*******************************************************************************
+ * LLWU_PE1 - LLWU Pin Enable 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE1 - LLWU Pin Enable 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE1 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE1 register
+ */
+/*@{*/
+#define LLWU_RD_PE1(base)        (LLWU_PE1_REG(base))
+#define LLWU_WR_PE1(base, value) (LLWU_PE1_REG(base) = (value))
+#define LLWU_RMW_PE1(base, mask, value) (LLWU_WR_PE1(base, (LLWU_RD_PE1(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) |  (value)))
+#define LLWU_CLR_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) & ~(value)))
+#define LLWU_TOG_PE1(base, value) (LLWU_WR_PE1(base, LLWU_RD_PE1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
+#define LLWU_RD_PE1_WUPE0(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE0_MASK) >> LLWU_PE1_WUPE0_SHIFT)
+#define LLWU_BRD_PE1_WUPE0(base) (LLWU_RD_PE1_WUPE0(base))
+
+/*! @brief Set the WUPE0 field to a new value. */
+#define LLWU_WR_PE1_WUPE0(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE0_MASK, LLWU_PE1_WUPE0(value)))
+#define LLWU_BWR_PE1_WUPE0(base, value) (LLWU_WR_PE1_WUPE0(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
+#define LLWU_RD_PE1_WUPE1(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE1_MASK) >> LLWU_PE1_WUPE1_SHIFT)
+#define LLWU_BRD_PE1_WUPE1(base) (LLWU_RD_PE1_WUPE1(base))
+
+/*! @brief Set the WUPE1 field to a new value. */
+#define LLWU_WR_PE1_WUPE1(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE1_MASK, LLWU_PE1_WUPE1(value)))
+#define LLWU_BWR_PE1_WUPE1(base, value) (LLWU_WR_PE1_WUPE1(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
+#define LLWU_RD_PE1_WUPE2(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE2_MASK) >> LLWU_PE1_WUPE2_SHIFT)
+#define LLWU_BRD_PE1_WUPE2(base) (LLWU_RD_PE1_WUPE2(base))
+
+/*! @brief Set the WUPE2 field to a new value. */
+#define LLWU_WR_PE1_WUPE2(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE2_MASK, LLWU_PE1_WUPE2(value)))
+#define LLWU_BWR_PE1_WUPE2(base, value) (LLWU_WR_PE1_WUPE2(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
+#define LLWU_RD_PE1_WUPE3(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE3_MASK) >> LLWU_PE1_WUPE3_SHIFT)
+#define LLWU_BRD_PE1_WUPE3(base) (LLWU_RD_PE1_WUPE3(base))
+
+/*! @brief Set the WUPE3 field to a new value. */
+#define LLWU_WR_PE1_WUPE3(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE3_MASK, LLWU_PE1_WUPE3(value)))
+#define LLWU_BWR_PE1_WUPE3(base, value) (LLWU_WR_PE1_WUPE3(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE2 - LLWU Pin Enable 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE2 - LLWU Pin Enable 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE2 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE2 register
+ */
+/*@{*/
+#define LLWU_RD_PE2(base)        (LLWU_PE2_REG(base))
+#define LLWU_WR_PE2(base, value) (LLWU_PE2_REG(base) = (value))
+#define LLWU_RMW_PE2(base, mask, value) (LLWU_WR_PE2(base, (LLWU_RD_PE2(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) |  (value)))
+#define LLWU_CLR_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) & ~(value)))
+#define LLWU_TOG_PE2(base, value) (LLWU_WR_PE2(base, LLWU_RD_PE2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
+#define LLWU_RD_PE2_WUPE4(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE4_MASK) >> LLWU_PE2_WUPE4_SHIFT)
+#define LLWU_BRD_PE2_WUPE4(base) (LLWU_RD_PE2_WUPE4(base))
+
+/*! @brief Set the WUPE4 field to a new value. */
+#define LLWU_WR_PE2_WUPE4(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE4_MASK, LLWU_PE2_WUPE4(value)))
+#define LLWU_BWR_PE2_WUPE4(base, value) (LLWU_WR_PE2_WUPE4(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
+#define LLWU_RD_PE2_WUPE5(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE5_MASK) >> LLWU_PE2_WUPE5_SHIFT)
+#define LLWU_BRD_PE2_WUPE5(base) (LLWU_RD_PE2_WUPE5(base))
+
+/*! @brief Set the WUPE5 field to a new value. */
+#define LLWU_WR_PE2_WUPE5(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE5_MASK, LLWU_PE2_WUPE5(value)))
+#define LLWU_BWR_PE2_WUPE5(base, value) (LLWU_WR_PE2_WUPE5(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
+#define LLWU_RD_PE2_WUPE6(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE6_MASK) >> LLWU_PE2_WUPE6_SHIFT)
+#define LLWU_BRD_PE2_WUPE6(base) (LLWU_RD_PE2_WUPE6(base))
+
+/*! @brief Set the WUPE6 field to a new value. */
+#define LLWU_WR_PE2_WUPE6(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE6_MASK, LLWU_PE2_WUPE6(value)))
+#define LLWU_BWR_PE2_WUPE6(base, value) (LLWU_WR_PE2_WUPE6(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
+#define LLWU_RD_PE2_WUPE7(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE7_MASK) >> LLWU_PE2_WUPE7_SHIFT)
+#define LLWU_BRD_PE2_WUPE7(base) (LLWU_RD_PE2_WUPE7(base))
+
+/*! @brief Set the WUPE7 field to a new value. */
+#define LLWU_WR_PE2_WUPE7(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE7_MASK, LLWU_PE2_WUPE7(value)))
+#define LLWU_BWR_PE2_WUPE7(base, value) (LLWU_WR_PE2_WUPE7(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE3 - LLWU Pin Enable 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE3 - LLWU Pin Enable 3 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE3 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module
+ * (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE3 register
+ */
+/*@{*/
+#define LLWU_RD_PE3(base)        (LLWU_PE3_REG(base))
+#define LLWU_WR_PE3(base, value) (LLWU_PE3_REG(base) = (value))
+#define LLWU_RMW_PE3(base, mask, value) (LLWU_WR_PE3(base, (LLWU_RD_PE3(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) |  (value)))
+#define LLWU_CLR_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) & ~(value)))
+#define LLWU_TOG_PE3(base, value) (LLWU_WR_PE3(base, LLWU_RD_PE3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
+#define LLWU_RD_PE3_WUPE8(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE8_MASK) >> LLWU_PE3_WUPE8_SHIFT)
+#define LLWU_BRD_PE3_WUPE8(base) (LLWU_RD_PE3_WUPE8(base))
+
+/*! @brief Set the WUPE8 field to a new value. */
+#define LLWU_WR_PE3_WUPE8(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE8_MASK, LLWU_PE3_WUPE8(value)))
+#define LLWU_BWR_PE3_WUPE8(base, value) (LLWU_WR_PE3_WUPE8(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
+#define LLWU_RD_PE3_WUPE9(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE9_MASK) >> LLWU_PE3_WUPE9_SHIFT)
+#define LLWU_BRD_PE3_WUPE9(base) (LLWU_RD_PE3_WUPE9(base))
+
+/*! @brief Set the WUPE9 field to a new value. */
+#define LLWU_WR_PE3_WUPE9(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE9_MASK, LLWU_PE3_WUPE9(value)))
+#define LLWU_BWR_PE3_WUPE9(base, value) (LLWU_WR_PE3_WUPE9(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
+#define LLWU_RD_PE3_WUPE10(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE10_MASK) >> LLWU_PE3_WUPE10_SHIFT)
+#define LLWU_BRD_PE3_WUPE10(base) (LLWU_RD_PE3_WUPE10(base))
+
+/*! @brief Set the WUPE10 field to a new value. */
+#define LLWU_WR_PE3_WUPE10(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE10_MASK, LLWU_PE3_WUPE10(value)))
+#define LLWU_BWR_PE3_WUPE10(base, value) (LLWU_WR_PE3_WUPE10(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
+#define LLWU_RD_PE3_WUPE11(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE11_MASK) >> LLWU_PE3_WUPE11_SHIFT)
+#define LLWU_BRD_PE3_WUPE11(base) (LLWU_RD_PE3_WUPE11(base))
+
+/*! @brief Set the WUPE11 field to a new value. */
+#define LLWU_WR_PE3_WUPE11(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE11_MASK, LLWU_PE3_WUPE11(value)))
+#define LLWU_BWR_PE3_WUPE11(base, value) (LLWU_WR_PE3_WUPE11(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_PE4 - LLWU Pin Enable 4 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_PE4 - LLWU Pin Enable 4 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_PE4 contains the field to enable and select the edge detect type for the
+ * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_PE4 register
+ */
+/*@{*/
+#define LLWU_RD_PE4(base)        (LLWU_PE4_REG(base))
+#define LLWU_WR_PE4(base, value) (LLWU_PE4_REG(base) = (value))
+#define LLWU_RMW_PE4(base, mask, value) (LLWU_WR_PE4(base, (LLWU_RD_PE4(base) & ~(mask)) | (value)))
+#define LLWU_SET_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) |  (value)))
+#define LLWU_CLR_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) & ~(value)))
+#define LLWU_TOG_PE4(base, value) (LLWU_WR_PE4(base, LLWU_RD_PE4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_PE4 bitfields
+ */
+
+/*!
+ * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
+#define LLWU_RD_PE4_WUPE12(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE12_MASK) >> LLWU_PE4_WUPE12_SHIFT)
+#define LLWU_BRD_PE4_WUPE12(base) (LLWU_RD_PE4_WUPE12(base))
+
+/*! @brief Set the WUPE12 field to a new value. */
+#define LLWU_WR_PE4_WUPE12(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE12_MASK, LLWU_PE4_WUPE12(value)))
+#define LLWU_BWR_PE4_WUPE12(base, value) (LLWU_WR_PE4_WUPE12(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
+#define LLWU_RD_PE4_WUPE13(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE13_MASK) >> LLWU_PE4_WUPE13_SHIFT)
+#define LLWU_BRD_PE4_WUPE13(base) (LLWU_RD_PE4_WUPE13(base))
+
+/*! @brief Set the WUPE13 field to a new value. */
+#define LLWU_WR_PE4_WUPE13(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE13_MASK, LLWU_PE4_WUPE13(value)))
+#define LLWU_BWR_PE4_WUPE13(base, value) (LLWU_WR_PE4_WUPE13(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
+#define LLWU_RD_PE4_WUPE14(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE14_MASK) >> LLWU_PE4_WUPE14_SHIFT)
+#define LLWU_BRD_PE4_WUPE14(base) (LLWU_RD_PE4_WUPE14(base))
+
+/*! @brief Set the WUPE14 field to a new value. */
+#define LLWU_WR_PE4_WUPE14(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE14_MASK, LLWU_PE4_WUPE14(value)))
+#define LLWU_BWR_PE4_WUPE14(base, value) (LLWU_WR_PE4_WUPE14(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
+ *
+ * Enables and configures the edge detection for the wakeup pin.
+ *
+ * Values:
+ * - 0b00 - External input pin disabled as wakeup input
+ * - 0b01 - External input pin enabled with rising edge detection
+ * - 0b10 - External input pin enabled with falling edge detection
+ * - 0b11 - External input pin enabled with any change detection
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
+#define LLWU_RD_PE4_WUPE15(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE15_MASK) >> LLWU_PE4_WUPE15_SHIFT)
+#define LLWU_BRD_PE4_WUPE15(base) (LLWU_RD_PE4_WUPE15(base))
+
+/*! @brief Set the WUPE15 field to a new value. */
+#define LLWU_WR_PE4_WUPE15(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE15_MASK, LLWU_PE4_WUPE15(value)))
+#define LLWU_BWR_PE4_WUPE15(base, value) (LLWU_WR_PE4_WUPE15(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_ME - LLWU Module Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_ME - LLWU Module Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_ME contains the bits to enable the internal module flag as a wakeup
+ * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
+ * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
+ * reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
+ * RCM implements many of the reset functions for the chip. See the chip's reset
+ * chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_ME register
+ */
+/*@{*/
+#define LLWU_RD_ME(base)         (LLWU_ME_REG(base))
+#define LLWU_WR_ME(base, value)  (LLWU_ME_REG(base) = (value))
+#define LLWU_RMW_ME(base, mask, value) (LLWU_WR_ME(base, (LLWU_RD_ME(base) & ~(mask)) | (value)))
+#define LLWU_SET_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) |  (value)))
+#define LLWU_CLR_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) & ~(value)))
+#define LLWU_TOG_ME(base, value) (LLWU_WR_ME(base, LLWU_RD_ME(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_ME bitfields
+ */
+
+/*!
+ * @name Register LLWU_ME, field WUME0[0] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME0 field. */
+#define LLWU_RD_ME_WUME0(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME0_MASK) >> LLWU_ME_WUME0_SHIFT)
+#define LLWU_BRD_ME_WUME0(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT))
+
+/*! @brief Set the WUME0 field to a new value. */
+#define LLWU_WR_ME_WUME0(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME0_MASK, LLWU_ME_WUME0(value)))
+#define LLWU_BWR_ME_WUME0(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME1[1] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME1 field. */
+#define LLWU_RD_ME_WUME1(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME1_MASK) >> LLWU_ME_WUME1_SHIFT)
+#define LLWU_BRD_ME_WUME1(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT))
+
+/*! @brief Set the WUME1 field to a new value. */
+#define LLWU_WR_ME_WUME1(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME1_MASK, LLWU_ME_WUME1(value)))
+#define LLWU_BWR_ME_WUME1(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME2[2] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME2 field. */
+#define LLWU_RD_ME_WUME2(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME2_MASK) >> LLWU_ME_WUME2_SHIFT)
+#define LLWU_BRD_ME_WUME2(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT))
+
+/*! @brief Set the WUME2 field to a new value. */
+#define LLWU_WR_ME_WUME2(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME2_MASK, LLWU_ME_WUME2(value)))
+#define LLWU_BWR_ME_WUME2(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME3[3] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME3 field. */
+#define LLWU_RD_ME_WUME3(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME3_MASK) >> LLWU_ME_WUME3_SHIFT)
+#define LLWU_BRD_ME_WUME3(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT))
+
+/*! @brief Set the WUME3 field to a new value. */
+#define LLWU_WR_ME_WUME3(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME3_MASK, LLWU_ME_WUME3(value)))
+#define LLWU_BWR_ME_WUME3(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME4[4] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME4 field. */
+#define LLWU_RD_ME_WUME4(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME4_MASK) >> LLWU_ME_WUME4_SHIFT)
+#define LLWU_BRD_ME_WUME4(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT))
+
+/*! @brief Set the WUME4 field to a new value. */
+#define LLWU_WR_ME_WUME4(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME4_MASK, LLWU_ME_WUME4(value)))
+#define LLWU_BWR_ME_WUME4(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME5[5] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME5 field. */
+#define LLWU_RD_ME_WUME5(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME5_MASK) >> LLWU_ME_WUME5_SHIFT)
+#define LLWU_BRD_ME_WUME5(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT))
+
+/*! @brief Set the WUME5 field to a new value. */
+#define LLWU_WR_ME_WUME5(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME5_MASK, LLWU_ME_WUME5(value)))
+#define LLWU_BWR_ME_WUME5(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME6[6] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME6 field. */
+#define LLWU_RD_ME_WUME6(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME6_MASK) >> LLWU_ME_WUME6_SHIFT)
+#define LLWU_BRD_ME_WUME6(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT))
+
+/*! @brief Set the WUME6 field to a new value. */
+#define LLWU_WR_ME_WUME6(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME6_MASK, LLWU_ME_WUME6(value)))
+#define LLWU_BWR_ME_WUME6(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_ME, field WUME7[7] (RW)
+ *
+ * Enables an internal module as a wakeup source input.
+ *
+ * Values:
+ * - 0b0 - Internal module flag not used as wakeup source
+ * - 0b1 - Internal module flag used as wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_ME_WUME7 field. */
+#define LLWU_RD_ME_WUME7(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME7_MASK) >> LLWU_ME_WUME7_SHIFT)
+#define LLWU_BRD_ME_WUME7(base) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT))
+
+/*! @brief Set the WUME7 field to a new value. */
+#define LLWU_WR_ME_WUME7(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME7_MASK, LLWU_ME_WUME7(value)))
+#define LLWU_BWR_ME_WUME7(base, value) (BITBAND_ACCESS8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F1 - LLWU Flag 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F1 - LLWU Flag 1 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F1 register
+ */
+/*@{*/
+#define LLWU_RD_F1(base)         (LLWU_F1_REG(base))
+#define LLWU_WR_F1(base, value)  (LLWU_F1_REG(base) = (value))
+#define LLWU_RMW_F1(base, mask, value) (LLWU_WR_F1(base, (LLWU_RD_F1(base) & ~(mask)) | (value)))
+#define LLWU_SET_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) |  (value)))
+#define LLWU_CLR_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) & ~(value)))
+#define LLWU_TOG_F1(base, value) (LLWU_WR_F1(base, LLWU_RD_F1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F1, field WUF0[0] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF0.
+ *
+ * Values:
+ * - 0b0 - LLWU_P0 input was not a wakeup source
+ * - 0b1 - LLWU_P0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF0 field. */
+#define LLWU_RD_F1_WUF0(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF0_MASK) >> LLWU_F1_WUF0_SHIFT)
+#define LLWU_BRD_F1_WUF0(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT))
+
+/*! @brief Set the WUF0 field to a new value. */
+#define LLWU_WR_F1_WUF0(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF0(value)))
+#define LLWU_BWR_F1_WUF0(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF1[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF1.
+ *
+ * Values:
+ * - 0b0 - LLWU_P1 input was not a wakeup source
+ * - 0b1 - LLWU_P1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF1 field. */
+#define LLWU_RD_F1_WUF1(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF1_MASK) >> LLWU_F1_WUF1_SHIFT)
+#define LLWU_BRD_F1_WUF1(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT))
+
+/*! @brief Set the WUF1 field to a new value. */
+#define LLWU_WR_F1_WUF1(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF1_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF1(value)))
+#define LLWU_BWR_F1_WUF1(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF2[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF2.
+ *
+ * Values:
+ * - 0b0 - LLWU_P2 input was not a wakeup source
+ * - 0b1 - LLWU_P2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF2 field. */
+#define LLWU_RD_F1_WUF2(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF2_MASK) >> LLWU_F1_WUF2_SHIFT)
+#define LLWU_BRD_F1_WUF2(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT))
+
+/*! @brief Set the WUF2 field to a new value. */
+#define LLWU_WR_F1_WUF2(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF2_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF2(value)))
+#define LLWU_BWR_F1_WUF2(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF3[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF3.
+ *
+ * Values:
+ * - 0b0 - LLWU_P3 input was not a wake-up source
+ * - 0b1 - LLWU_P3 input was a wake-up source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF3 field. */
+#define LLWU_RD_F1_WUF3(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF3_MASK) >> LLWU_F1_WUF3_SHIFT)
+#define LLWU_BRD_F1_WUF3(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT))
+
+/*! @brief Set the WUF3 field to a new value. */
+#define LLWU_WR_F1_WUF3(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF3_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF3(value)))
+#define LLWU_BWR_F1_WUF3(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF4[4] (W1C)
+ *
+ * Indicates that an enabled external wake-up pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF4.
+ *
+ * Values:
+ * - 0b0 - LLWU_P4 input was not a wakeup source
+ * - 0b1 - LLWU_P4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF4 field. */
+#define LLWU_RD_F1_WUF4(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF4_MASK) >> LLWU_F1_WUF4_SHIFT)
+#define LLWU_BRD_F1_WUF4(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT))
+
+/*! @brief Set the WUF4 field to a new value. */
+#define LLWU_WR_F1_WUF4(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF4_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF4(value)))
+#define LLWU_BWR_F1_WUF4(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF5[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF5.
+ *
+ * Values:
+ * - 0b0 - LLWU_P5 input was not a wakeup source
+ * - 0b1 - LLWU_P5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF5 field. */
+#define LLWU_RD_F1_WUF5(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF5_MASK) >> LLWU_F1_WUF5_SHIFT)
+#define LLWU_BRD_F1_WUF5(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT))
+
+/*! @brief Set the WUF5 field to a new value. */
+#define LLWU_WR_F1_WUF5(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF5_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF5(value)))
+#define LLWU_BWR_F1_WUF5(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF6[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF6.
+ *
+ * Values:
+ * - 0b0 - LLWU_P6 input was not a wakeup source
+ * - 0b1 - LLWU_P6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF6 field. */
+#define LLWU_RD_F1_WUF6(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF6_MASK) >> LLWU_F1_WUF6_SHIFT)
+#define LLWU_BRD_F1_WUF6(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT))
+
+/*! @brief Set the WUF6 field to a new value. */
+#define LLWU_WR_F1_WUF6(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF6_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF6(value)))
+#define LLWU_BWR_F1_WUF6(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F1, field WUF7[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF7.
+ *
+ * Values:
+ * - 0b0 - LLWU_P7 input was not a wakeup source
+ * - 0b1 - LLWU_P7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F1_WUF7 field. */
+#define LLWU_RD_F1_WUF7(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF7_MASK) >> LLWU_F1_WUF7_SHIFT)
+#define LLWU_BRD_F1_WUF7(base) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT))
+
+/*! @brief Set the WUF7 field to a new value. */
+#define LLWU_WR_F1_WUF7(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF7_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK), LLWU_F1_WUF7(value)))
+#define LLWU_BWR_F1_WUF7(base, value) (BITBAND_ACCESS8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F2 - LLWU Flag 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F2 - LLWU Flag 2 register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
+ * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
+ * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
+ * external wakeup flags are read-only and clearing a flag is accomplished by a write
+ * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
+ * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F2 register
+ */
+/*@{*/
+#define LLWU_RD_F2(base)         (LLWU_F2_REG(base))
+#define LLWU_WR_F2(base, value)  (LLWU_F2_REG(base) = (value))
+#define LLWU_RMW_F2(base, mask, value) (LLWU_WR_F2(base, (LLWU_RD_F2(base) & ~(mask)) | (value)))
+#define LLWU_SET_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) |  (value)))
+#define LLWU_CLR_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) & ~(value)))
+#define LLWU_TOG_F2(base, value) (LLWU_WR_F2(base, LLWU_RD_F2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F2, field WUF8[0] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF8.
+ *
+ * Values:
+ * - 0b0 - LLWU_P8 input was not a wakeup source
+ * - 0b1 - LLWU_P8 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF8 field. */
+#define LLWU_RD_F2_WUF8(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF8_MASK) >> LLWU_F2_WUF8_SHIFT)
+#define LLWU_BRD_F2_WUF8(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT))
+
+/*! @brief Set the WUF8 field to a new value. */
+#define LLWU_WR_F2_WUF8(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF8(value)))
+#define LLWU_BWR_F2_WUF8(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF9[1] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF9.
+ *
+ * Values:
+ * - 0b0 - LLWU_P9 input was not a wakeup source
+ * - 0b1 - LLWU_P9 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF9 field. */
+#define LLWU_RD_F2_WUF9(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF9_MASK) >> LLWU_F2_WUF9_SHIFT)
+#define LLWU_BRD_F2_WUF9(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT))
+
+/*! @brief Set the WUF9 field to a new value. */
+#define LLWU_WR_F2_WUF9(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF9_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF9(value)))
+#define LLWU_BWR_F2_WUF9(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF10[2] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF10.
+ *
+ * Values:
+ * - 0b0 - LLWU_P10 input was not a wakeup source
+ * - 0b1 - LLWU_P10 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF10 field. */
+#define LLWU_RD_F2_WUF10(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF10_MASK) >> LLWU_F2_WUF10_SHIFT)
+#define LLWU_BRD_F2_WUF10(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT))
+
+/*! @brief Set the WUF10 field to a new value. */
+#define LLWU_WR_F2_WUF10(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF10_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF10(value)))
+#define LLWU_BWR_F2_WUF10(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF11[3] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF11.
+ *
+ * Values:
+ * - 0b0 - LLWU_P11 input was not a wakeup source
+ * - 0b1 - LLWU_P11 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF11 field. */
+#define LLWU_RD_F2_WUF11(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF11_MASK) >> LLWU_F2_WUF11_SHIFT)
+#define LLWU_BRD_F2_WUF11(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT))
+
+/*! @brief Set the WUF11 field to a new value. */
+#define LLWU_WR_F2_WUF11(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF11_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF11(value)))
+#define LLWU_BWR_F2_WUF11(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF12[4] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF12.
+ *
+ * Values:
+ * - 0b0 - LLWU_P12 input was not a wakeup source
+ * - 0b1 - LLWU_P12 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF12 field. */
+#define LLWU_RD_F2_WUF12(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF12_MASK) >> LLWU_F2_WUF12_SHIFT)
+#define LLWU_BRD_F2_WUF12(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT))
+
+/*! @brief Set the WUF12 field to a new value. */
+#define LLWU_WR_F2_WUF12(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF12_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF12(value)))
+#define LLWU_BWR_F2_WUF12(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF13[5] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF13.
+ *
+ * Values:
+ * - 0b0 - LLWU_P13 input was not a wakeup source
+ * - 0b1 - LLWU_P13 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF13 field. */
+#define LLWU_RD_F2_WUF13(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF13_MASK) >> LLWU_F2_WUF13_SHIFT)
+#define LLWU_BRD_F2_WUF13(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT))
+
+/*! @brief Set the WUF13 field to a new value. */
+#define LLWU_WR_F2_WUF13(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF13_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF13(value)))
+#define LLWU_BWR_F2_WUF13(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF14[6] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF14.
+ *
+ * Values:
+ * - 0b0 - LLWU_P14 input was not a wakeup source
+ * - 0b1 - LLWU_P14 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF14 field. */
+#define LLWU_RD_F2_WUF14(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF14_MASK) >> LLWU_F2_WUF14_SHIFT)
+#define LLWU_BRD_F2_WUF14(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT))
+
+/*! @brief Set the WUF14 field to a new value. */
+#define LLWU_WR_F2_WUF14(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF14_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF14(value)))
+#define LLWU_BWR_F2_WUF14(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F2, field WUF15[7] (W1C)
+ *
+ * Indicates that an enabled external wakeup pin was a source of exiting a
+ * low-leakage power mode. To clear the flag, write a 1 to WUF15.
+ *
+ * Values:
+ * - 0b0 - LLWU_P15 input was not a wakeup source
+ * - 0b1 - LLWU_P15 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F2_WUF15 field. */
+#define LLWU_RD_F2_WUF15(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF15_MASK) >> LLWU_F2_WUF15_SHIFT)
+#define LLWU_BRD_F2_WUF15(base) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT))
+
+/*! @brief Set the WUF15 field to a new value. */
+#define LLWU_WR_F2_WUF15(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF15_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK), LLWU_F2_WUF15(value)))
+#define LLWU_BWR_F2_WUF15(base, value) (BITBAND_ACCESS8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_F3 - LLWU Flag 3 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_F3 - LLWU Flag 3 register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
+ * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
+ * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
+ * For internal peripherals that are capable of running in a low-leakage power
+ * mode, such as a real time clock module or CMP module, the flag from the
+ * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
+ * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
+ * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
+ * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
+ * the IntroductionInformation found here describes the registers of the Reset
+ * Control Module (RCM). The RCM implements many of the reset functions for the
+ * chip. See the chip's reset chapter for more information. details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_F3 register
+ */
+/*@{*/
+#define LLWU_RD_F3(base)         (LLWU_F3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_F3 bitfields
+ */
+
+/*!
+ * @name Register LLWU_F3, field MWUF0[0] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 0 input was not a wakeup source
+ * - 0b1 - Module 0 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF0 field. */
+#define LLWU_RD_F3_MWUF0(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF0_MASK) >> LLWU_F3_MWUF0_SHIFT)
+#define LLWU_BRD_F3_MWUF0(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF1[1] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 1 input was not a wakeup source
+ * - 0b1 - Module 1 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF1 field. */
+#define LLWU_RD_F3_MWUF1(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF1_MASK) >> LLWU_F3_MWUF1_SHIFT)
+#define LLWU_BRD_F3_MWUF1(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF1_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF2[2] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 2 input was not a wakeup source
+ * - 0b1 - Module 2 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF2 field. */
+#define LLWU_RD_F3_MWUF2(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF2_MASK) >> LLWU_F3_MWUF2_SHIFT)
+#define LLWU_BRD_F3_MWUF2(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF2_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF3[3] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 3 input was not a wakeup source
+ * - 0b1 - Module 3 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF3 field. */
+#define LLWU_RD_F3_MWUF3(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF3_MASK) >> LLWU_F3_MWUF3_SHIFT)
+#define LLWU_BRD_F3_MWUF3(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF3_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF4[4] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 4 input was not a wakeup source
+ * - 0b1 - Module 4 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF4 field. */
+#define LLWU_RD_F3_MWUF4(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF4_MASK) >> LLWU_F3_MWUF4_SHIFT)
+#define LLWU_BRD_F3_MWUF4(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF4_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF5[5] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 5 input was not a wakeup source
+ * - 0b1 - Module 5 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF5 field. */
+#define LLWU_RD_F3_MWUF5(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF5_MASK) >> LLWU_F3_MWUF5_SHIFT)
+#define LLWU_BRD_F3_MWUF5(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF5_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF6[6] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 6 input was not a wakeup source
+ * - 0b1 - Module 6 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF6 field. */
+#define LLWU_RD_F3_MWUF6(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF6_MASK) >> LLWU_F3_MWUF6_SHIFT)
+#define LLWU_BRD_F3_MWUF6(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF6_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register LLWU_F3, field MWUF7[7] (RO)
+ *
+ * Indicates that an enabled internal peripheral was a source of exiting a
+ * low-leakage power mode. To clear the flag, follow the internal peripheral flag
+ * clearing mechanism.
+ *
+ * Values:
+ * - 0b0 - Module 7 input was not a wakeup source
+ * - 0b1 - Module 7 input was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_F3_MWUF7 field. */
+#define LLWU_RD_F3_MWUF7(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF7_MASK) >> LLWU_F3_MWUF7_SHIFT)
+#define LLWU_BRD_F3_MWUF7(base) (BITBAND_ACCESS8(&LLWU_F3_REG(base), LLWU_F3_MWUF7_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT1 - LLWU Pin Filter 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT1 is a control and status register that is used to enable/disable
+ * the digital filter 1 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT1 register
+ */
+/*@{*/
+#define LLWU_RD_FILT1(base)      (LLWU_FILT1_REG(base))
+#define LLWU_WR_FILT1(base, value) (LLWU_FILT1_REG(base) = (value))
+#define LLWU_RMW_FILT1(base, mask, value) (LLWU_WR_FILT1(base, (LLWU_RD_FILT1(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) |  (value)))
+#define LLWU_CLR_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) & ~(value)))
+#define LLWU_TOG_FILT1(base, value) (LLWU_WR_FILT1(base, LLWU_RD_FILT1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT1 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0b0000 - Select LLWU_P0 for filter
+ * - 0b1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
+#define LLWU_RD_FILT1_FILTSEL(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTSEL_MASK) >> LLWU_FILT1_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT1_FILTSEL(base) (LLWU_RD_FILT1_FILTSEL(base))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT1_FILTSEL(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTSEL(value)))
+#define LLWU_BWR_FILT1_FILTSEL(base, value) (LLWU_WR_FILT1_FILTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 0b00 - Filter disabled
+ * - 0b01 - Filter posedge detect enabled
+ * - 0b10 - Filter negedge detect enabled
+ * - 0b11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTE field. */
+#define LLWU_RD_FILT1_FILTE(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTE_MASK) >> LLWU_FILT1_FILTE_SHIFT)
+#define LLWU_BRD_FILT1_FILTE(base) (LLWU_RD_FILT1_FILTE(base))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT1_FILTE(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTE_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTE(value)))
+#define LLWU_BWR_FILT1_FILTE(base, value) (LLWU_WR_FILT1_FILTE(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT1, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0b0 - Pin Filter 1 was not a wakeup source
+ * - 0b1 - Pin Filter 1 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT1_FILTF field. */
+#define LLWU_RD_FILT1_FILTF(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTF_MASK) >> LLWU_FILT1_FILTF_SHIFT)
+#define LLWU_BRD_FILT1_FILTF(base) (BITBAND_ACCESS8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT1_FILTF(base, value) (LLWU_RMW_FILT1(base, LLWU_FILT1_FILTF_MASK, LLWU_FILT1_FILTF(value)))
+#define LLWU_BWR_FILT1_FILTF(base, value) (BITBAND_ACCESS8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_FILT2 - LLWU Pin Filter 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * LLWU_FILT2 is a control and status register that is used to enable/disable
+ * the digital filter 2 features for an external pin. This register is reset on
+ * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See
+ * the chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_FILT2 register
+ */
+/*@{*/
+#define LLWU_RD_FILT2(base)      (LLWU_FILT2_REG(base))
+#define LLWU_WR_FILT2(base, value) (LLWU_FILT2_REG(base) = (value))
+#define LLWU_RMW_FILT2(base, mask, value) (LLWU_WR_FILT2(base, (LLWU_RD_FILT2(base) & ~(mask)) | (value)))
+#define LLWU_SET_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) |  (value)))
+#define LLWU_CLR_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) & ~(value)))
+#define LLWU_TOG_FILT2(base, value) (LLWU_WR_FILT2(base, LLWU_RD_FILT2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_FILT2 bitfields
+ */
+
+/*!
+ * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
+ *
+ * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
+ *
+ * Values:
+ * - 0b0000 - Select LLWU_P0 for filter
+ * - 0b1111 - Select LLWU_P15 for filter
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
+#define LLWU_RD_FILT2_FILTSEL(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTSEL_MASK) >> LLWU_FILT2_FILTSEL_SHIFT)
+#define LLWU_BRD_FILT2_FILTSEL(base) (LLWU_RD_FILT2_FILTSEL(base))
+
+/*! @brief Set the FILTSEL field to a new value. */
+#define LLWU_WR_FILT2_FILTSEL(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTSEL_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTSEL(value)))
+#define LLWU_BWR_FILT2_FILTSEL(base, value) (LLWU_WR_FILT2_FILTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
+ *
+ * Controls the digital filter options for the external pin detect.
+ *
+ * Values:
+ * - 0b00 - Filter disabled
+ * - 0b01 - Filter posedge detect enabled
+ * - 0b10 - Filter negedge detect enabled
+ * - 0b11 - Filter any edge detect enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTE field. */
+#define LLWU_RD_FILT2_FILTE(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTE_MASK) >> LLWU_FILT2_FILTE_SHIFT)
+#define LLWU_BRD_FILT2_FILTE(base) (LLWU_RD_FILT2_FILTE(base))
+
+/*! @brief Set the FILTE field to a new value. */
+#define LLWU_WR_FILT2_FILTE(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTE_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTE(value)))
+#define LLWU_BWR_FILT2_FILTE(base, value) (LLWU_WR_FILT2_FILTE(base, value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_FILT2, field FILTF[7] (W1C)
+ *
+ * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
+ * source of exiting a low-leakage power mode. To clear the flag write a one to
+ * FILTF.
+ *
+ * Values:
+ * - 0b0 - Pin Filter 2 was not a wakeup source
+ * - 0b1 - Pin Filter 2 was a wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_FILT2_FILTF field. */
+#define LLWU_RD_FILT2_FILTF(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTF_MASK) >> LLWU_FILT2_FILTF_SHIFT)
+#define LLWU_BRD_FILT2_FILTF(base) (BITBAND_ACCESS8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT))
+
+/*! @brief Set the FILTF field to a new value. */
+#define LLWU_WR_FILT2_FILTF(base, value) (LLWU_RMW_FILT2(base, LLWU_FILT2_FILTF_MASK, LLWU_FILT2_FILTF(value)))
+#define LLWU_BWR_FILT2_FILTF(base, value) (BITBAND_ACCESS8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LLWU_RST - LLWU Reset Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief LLWU_RST - LLWU Reset Enable register (RW)
+ *
+ * Reset value: 0x02U
+ *
+ * LLWU_RST is a control register that is used to enable/disable the digital
+ * filter for the external pin detect and RESET pin. This register is reset on Chip
+ * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
+ * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
+ * IntroductionInformation found here describes the registers of the Reset Control
+ * Module (RCM). The RCM implements many of the reset functions for the chip. See the
+ * chip's reset chapter for more information. details for more information.
+ */
+/*!
+ * @name Constants and macros for entire LLWU_RST register
+ */
+/*@{*/
+#define LLWU_RD_RST(base)        (LLWU_RST_REG(base))
+#define LLWU_WR_RST(base, value) (LLWU_RST_REG(base) = (value))
+#define LLWU_RMW_RST(base, mask, value) (LLWU_WR_RST(base, (LLWU_RD_RST(base) & ~(mask)) | (value)))
+#define LLWU_SET_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) |  (value)))
+#define LLWU_CLR_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) & ~(value)))
+#define LLWU_TOG_RST(base, value) (LLWU_WR_RST(base, LLWU_RD_RST(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LLWU_RST bitfields
+ */
+
+/*!
+ * @name Register LLWU_RST, field RSTFILT[0] (RW)
+ *
+ * Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or
+ * VLLS1 modes.
+ *
+ * Values:
+ * - 0b0 - Filter not enabled
+ * - 0b1 - Filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_RST_RSTFILT field. */
+#define LLWU_RD_RST_RSTFILT(base) ((LLWU_RST_REG(base) & LLWU_RST_RSTFILT_MASK) >> LLWU_RST_RSTFILT_SHIFT)
+#define LLWU_BRD_RST_RSTFILT(base) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_RSTFILT_SHIFT))
+
+/*! @brief Set the RSTFILT field to a new value. */
+#define LLWU_WR_RST_RSTFILT(base, value) (LLWU_RMW_RST(base, LLWU_RST_RSTFILT_MASK, LLWU_RST_RSTFILT(value)))
+#define LLWU_BWR_RST_RSTFILT(base, value) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_RSTFILT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LLWU_RST, field LLRSTE[1] (RW)
+ *
+ * This bit must be set to allow the device to be reset while in a low-leakage
+ * power mode. On devices where Reset is not a dedicated pin, the RESET pin must
+ * also be enabled in the explicit port mux control.
+ *
+ * Values:
+ * - 0b0 - RESET pin not enabled as a leakage mode exit source
+ * - 0b1 - RESET pin enabled as a low leakage mode exit source
+ */
+/*@{*/
+/*! @brief Read current value of the LLWU_RST_LLRSTE field. */
+#define LLWU_RD_RST_LLRSTE(base) ((LLWU_RST_REG(base) & LLWU_RST_LLRSTE_MASK) >> LLWU_RST_LLRSTE_SHIFT)
+#define LLWU_BRD_RST_LLRSTE(base) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_LLRSTE_SHIFT))
+
+/*! @brief Set the LLRSTE field to a new value. */
+#define LLWU_WR_RST_LLRSTE(base, value) (LLWU_RMW_RST(base, LLWU_RST_LLRSTE_MASK, LLWU_RST_LLRSTE(value)))
+#define LLWU_BWR_RST_LLRSTE(base, value) (BITBAND_ACCESS8(&LLWU_RST_REG(base), LLWU_RST_LLRSTE_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 LPTMR
+ *
+ * Low Power Timer
+ *
+ * Registers defined in this header file:
+ * - LPTMR_CSR - Low Power Timer Control Status Register
+ * - LPTMR_PSR - Low Power Timer Prescale Register
+ * - LPTMR_CMR - Low Power Timer Compare Register
+ * - LPTMR_CNR - Low Power Timer Counter Register
+ */
+
+#define LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
+#define LPTMR0_IDX (0U) /*!< Instance number for LPTMR0. */
+
+/*******************************************************************************
+ * LPTMR_CSR - Low Power Timer Control Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CSR - Low Power Timer Control Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CSR register
+ */
+/*@{*/
+#define LPTMR_RD_CSR(base)       (LPTMR_CSR_REG(base))
+#define LPTMR_WR_CSR(base, value) (LPTMR_CSR_REG(base) = (value))
+#define LPTMR_RMW_CSR(base, mask, value) (LPTMR_WR_CSR(base, (LPTMR_RD_CSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) |  (value)))
+#define LPTMR_CLR_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) & ~(value)))
+#define LPTMR_TOG_CSR(base, value) (LPTMR_WR_CSR(base, LPTMR_RD_CSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CSR, field TEN[0] (RW)
+ *
+ * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
+ * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
+ * CSR[5:1] must not be altered.
+ *
+ * Values:
+ * - 0b0 - LPTMR is disabled and internal logic is reset.
+ * - 0b1 - LPTMR is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TEN field. */
+#define LPTMR_RD_CSR_TEN(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TEN_MASK) >> LPTMR_CSR_TEN_SHIFT)
+#define LPTMR_BRD_CSR_TEN(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT))
+
+/*! @brief Set the TEN field to a new value. */
+#define LPTMR_WR_CSR_TEN(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TEN_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TEN(value)))
+#define LPTMR_BWR_CSR_TEN(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TMS[1] (RW)
+ *
+ * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
+ * disabled.
+ *
+ * Values:
+ * - 0b0 - Time Counter mode.
+ * - 0b1 - Pulse Counter mode.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TMS field. */
+#define LPTMR_RD_CSR_TMS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TMS_MASK) >> LPTMR_CSR_TMS_SHIFT)
+#define LPTMR_BRD_CSR_TMS(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT))
+
+/*! @brief Set the TMS field to a new value. */
+#define LPTMR_WR_CSR_TMS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TMS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TMS(value)))
+#define LPTMR_BWR_CSR_TMS(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TFC[2] (RW)
+ *
+ * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
+ * TFC configures the CNR to reset on overflow. TFC must be altered only when the
+ * LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - CNR is reset whenever TCF is set.
+ * - 0b1 - CNR is reset on overflow.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TFC field. */
+#define LPTMR_RD_CSR_TFC(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TFC_MASK) >> LPTMR_CSR_TFC_SHIFT)
+#define LPTMR_BRD_CSR_TFC(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT))
+
+/*! @brief Set the TFC field to a new value. */
+#define LPTMR_WR_CSR_TFC(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TFC_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TFC(value)))
+#define LPTMR_BWR_CSR_TFC(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPP[3] (RW)
+ *
+ * Configures the polarity of the input source in Pulse Counter mode. TPP must
+ * be changed only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - Pulse Counter input source is active-high, and the CNR will increment
+ *     on the rising-edge.
+ * - 0b1 - Pulse Counter input source is active-low, and the CNR will increment
+ *     on the falling-edge.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPP field. */
+#define LPTMR_RD_CSR_TPP(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPP_MASK) >> LPTMR_CSR_TPP_SHIFT)
+#define LPTMR_BRD_CSR_TPP(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT))
+
+/*! @brief Set the TPP field to a new value. */
+#define LPTMR_WR_CSR_TPP(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPP_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPP(value)))
+#define LPTMR_BWR_CSR_TPP(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TPS[5:4] (RW)
+ *
+ * Configures the input source to be used in Pulse Counter mode. TPS must be
+ * altered only when the LPTMR is disabled. The input connections vary by device.
+ * See the chip configuration details for information on the connections to these
+ * inputs.
+ *
+ * Values:
+ * - 0b00 - Pulse counter input 0 is selected.
+ * - 0b01 - Pulse counter input 1 is selected.
+ * - 0b10 - Pulse counter input 2 is selected.
+ * - 0b11 - Pulse counter input 3 is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TPS field. */
+#define LPTMR_RD_CSR_TPS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPS_MASK) >> LPTMR_CSR_TPS_SHIFT)
+#define LPTMR_BRD_CSR_TPS(base) (LPTMR_RD_CSR_TPS(base))
+
+/*! @brief Set the TPS field to a new value. */
+#define LPTMR_WR_CSR_TPS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPS(value)))
+#define LPTMR_BWR_CSR_TPS(base, value) (LPTMR_WR_CSR_TPS(base, value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TIE[6] (RW)
+ *
+ * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
+ *
+ * Values:
+ * - 0b0 - Timer interrupt disabled.
+ * - 0b1 - Timer interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TIE field. */
+#define LPTMR_RD_CSR_TIE(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TIE_MASK) >> LPTMR_CSR_TIE_SHIFT)
+#define LPTMR_BRD_CSR_TIE(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define LPTMR_WR_CSR_TIE(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TIE_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TIE(value)))
+#define LPTMR_BWR_CSR_TIE(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_CSR, field TCF[7] (W1C)
+ *
+ * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
+ * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
+ *
+ * Values:
+ * - 0b0 - The value of CNR is not equal to CMR and increments.
+ * - 0b1 - The value of CNR is equal to CMR and increments.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CSR_TCF field. */
+#define LPTMR_RD_CSR_TCF(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TCF_MASK) >> LPTMR_CSR_TCF_SHIFT)
+#define LPTMR_BRD_CSR_TCF(base) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT))
+
+/*! @brief Set the TCF field to a new value. */
+#define LPTMR_WR_CSR_TCF(base, value) (LPTMR_RMW_CSR(base, LPTMR_CSR_TCF_MASK, LPTMR_CSR_TCF(value)))
+#define LPTMR_BWR_CSR_TCF(base, value) (BITBAND_ACCESS32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_PSR - Low Power Timer Prescale Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_PSR - Low Power Timer Prescale Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_PSR register
+ */
+/*@{*/
+#define LPTMR_RD_PSR(base)       (LPTMR_PSR_REG(base))
+#define LPTMR_WR_PSR(base, value) (LPTMR_PSR_REG(base) = (value))
+#define LPTMR_RMW_PSR(base, mask, value) (LPTMR_WR_PSR(base, (LPTMR_RD_PSR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) |  (value)))
+#define LPTMR_CLR_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) & ~(value)))
+#define LPTMR_TOG_PSR(base, value) (LPTMR_WR_PSR(base, LPTMR_RD_PSR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_PSR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_PSR, field PCS[1:0] (RW)
+ *
+ * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
+ * be altered only when the LPTMR is disabled. The clock connections vary by
+ * device. See the chip configuration details for information on the connections to
+ * these inputs.
+ *
+ * Values:
+ * - 0b00 - Prescaler/glitch filter clock 0 selected.
+ * - 0b01 - Prescaler/glitch filter clock 1 selected.
+ * - 0b10 - Prescaler/glitch filter clock 2 selected.
+ * - 0b11 - Prescaler/glitch filter clock 3 selected.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PCS field. */
+#define LPTMR_RD_PSR_PCS(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PCS_MASK) >> LPTMR_PSR_PCS_SHIFT)
+#define LPTMR_BRD_PSR_PCS(base) (LPTMR_RD_PSR_PCS(base))
+
+/*! @brief Set the PCS field to a new value. */
+#define LPTMR_WR_PSR_PCS(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PCS_MASK, LPTMR_PSR_PCS(value)))
+#define LPTMR_BWR_PSR_PCS(base, value) (LPTMR_WR_PSR_PCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PBYP[2] (RW)
+ *
+ * When PBYP is set, the selected prescaler clock in Time Counter mode or
+ * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
+ * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
+ * must be altered only when the LPTMR is disabled.
+ *
+ * Values:
+ * - 0b0 - Prescaler/glitch filter is enabled.
+ * - 0b1 - Prescaler/glitch filter is bypassed.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PBYP field. */
+#define LPTMR_RD_PSR_PBYP(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PBYP_MASK) >> LPTMR_PSR_PBYP_SHIFT)
+#define LPTMR_BRD_PSR_PBYP(base) (BITBAND_ACCESS32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT))
+
+/*! @brief Set the PBYP field to a new value. */
+#define LPTMR_WR_PSR_PBYP(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PBYP_MASK, LPTMR_PSR_PBYP(value)))
+#define LPTMR_BWR_PSR_PBYP(base, value) (BITBAND_ACCESS32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
+ *
+ * Configures the size of the Prescaler in Time Counter mode or width of the
+ * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
+ * is disabled.
+ *
+ * Values:
+ * - 0b0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
+ *     support this configuration.
+ * - 0b0001 - Prescaler divides the prescaler clock by 4; glitch filter
+ *     recognizes change on input pin after 2 rising clock edges.
+ * - 0b0010 - Prescaler divides the prescaler clock by 8; glitch filter
+ *     recognizes change on input pin after 4 rising clock edges.
+ * - 0b0011 - Prescaler divides the prescaler clock by 16; glitch filter
+ *     recognizes change on input pin after 8 rising clock edges.
+ * - 0b0100 - Prescaler divides the prescaler clock by 32; glitch filter
+ *     recognizes change on input pin after 16 rising clock edges.
+ * - 0b0101 - Prescaler divides the prescaler clock by 64; glitch filter
+ *     recognizes change on input pin after 32 rising clock edges.
+ * - 0b0110 - Prescaler divides the prescaler clock by 128; glitch filter
+ *     recognizes change on input pin after 64 rising clock edges.
+ * - 0b0111 - Prescaler divides the prescaler clock by 256; glitch filter
+ *     recognizes change on input pin after 128 rising clock edges.
+ * - 0b1000 - Prescaler divides the prescaler clock by 512; glitch filter
+ *     recognizes change on input pin after 256 rising clock edges.
+ * - 0b1001 - Prescaler divides the prescaler clock by 1024; glitch filter
+ *     recognizes change on input pin after 512 rising clock edges.
+ * - 0b1010 - Prescaler divides the prescaler clock by 2048; glitch filter
+ *     recognizes change on input pin after 1024 rising clock edges.
+ * - 0b1011 - Prescaler divides the prescaler clock by 4096; glitch filter
+ *     recognizes change on input pin after 2048 rising clock edges.
+ * - 0b1100 - Prescaler divides the prescaler clock by 8192; glitch filter
+ *     recognizes change on input pin after 4096 rising clock edges.
+ * - 0b1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
+ *     recognizes change on input pin after 8192 rising clock edges.
+ * - 0b1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
+ *     recognizes change on input pin after 16,384 rising clock edges.
+ * - 0b1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
+ *     recognizes change on input pin after 32,768 rising clock edges.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
+#define LPTMR_RD_PSR_PRESCALE(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PRESCALE_MASK) >> LPTMR_PSR_PRESCALE_SHIFT)
+#define LPTMR_BRD_PSR_PRESCALE(base) (LPTMR_RD_PSR_PRESCALE(base))
+
+/*! @brief Set the PRESCALE field to a new value. */
+#define LPTMR_WR_PSR_PRESCALE(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PRESCALE_MASK, LPTMR_PSR_PRESCALE(value)))
+#define LPTMR_BWR_PSR_PRESCALE(base, value) (LPTMR_WR_PSR_PRESCALE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CMR - Low Power Timer Compare Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CMR - Low Power Timer Compare Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CMR register
+ */
+/*@{*/
+#define LPTMR_RD_CMR(base)       (LPTMR_CMR_REG(base))
+#define LPTMR_WR_CMR(base, value) (LPTMR_CMR_REG(base) = (value))
+#define LPTMR_RMW_CMR(base, mask, value) (LPTMR_WR_CMR(base, (LPTMR_RD_CMR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) |  (value)))
+#define LPTMR_CLR_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) & ~(value)))
+#define LPTMR_TOG_CMR(base, value) (LPTMR_WR_CMR(base, LPTMR_RD_CMR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CMR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
+ *
+ * When the LPTMR is enabled and the CNR equals the value in the CMR and
+ * increments, TCF is set and the hardware trigger asserts until the next time the CNR
+ * increments. If the CMR is 0, the hardware trigger will remain asserted until
+ * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
+ * when TCF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
+#define LPTMR_RD_CMR_COMPARE(base) ((LPTMR_CMR_REG(base) & LPTMR_CMR_COMPARE_MASK) >> LPTMR_CMR_COMPARE_SHIFT)
+#define LPTMR_BRD_CMR_COMPARE(base) (LPTMR_RD_CMR_COMPARE(base))
+
+/*! @brief Set the COMPARE field to a new value. */
+#define LPTMR_WR_CMR_COMPARE(base, value) (LPTMR_RMW_CMR(base, LPTMR_CMR_COMPARE_MASK, LPTMR_CMR_COMPARE(value)))
+#define LPTMR_BWR_CMR_COMPARE(base, value) (LPTMR_WR_CMR_COMPARE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * LPTMR_CNR - Low Power Timer Counter Register
+ ******************************************************************************/
+
+/*!
+ * @brief LPTMR_CNR - Low Power Timer Counter Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire LPTMR_CNR register
+ */
+/*@{*/
+#define LPTMR_RD_CNR(base)       (LPTMR_CNR_REG(base))
+#define LPTMR_WR_CNR(base, value) (LPTMR_CNR_REG(base) = (value))
+#define LPTMR_RMW_CNR(base, mask, value) (LPTMR_WR_CNR(base, (LPTMR_RD_CNR(base) & ~(mask)) | (value)))
+#define LPTMR_SET_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) |  (value)))
+#define LPTMR_CLR_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) & ~(value)))
+#define LPTMR_TOG_CNR(base, value) (LPTMR_WR_CNR(base, LPTMR_RD_CNR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual LPTMR_CNR bitfields
+ */
+
+/*!
+ * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
+#define LPTMR_RD_CNR_COUNTER(base) ((LPTMR_CNR_REG(base) & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT)
+#define LPTMR_BRD_CNR_COUNTER(base) (LPTMR_RD_CNR_COUNTER(base))
+
+/*! @brief Set the COUNTER field to a new value. */
+#define LPTMR_WR_CNR_COUNTER(base, value) (LPTMR_RMW_CNR(base, LPTMR_CNR_COUNTER_MASK, LPTMR_CNR_COUNTER(value)))
+#define LPTMR_BWR_CNR_COUNTER(base, value) (LPTMR_WR_CNR_COUNTER(base, value))
+/*@}*/
+
+/*
+ * MK64F12 MCG
+ *
+ * Multipurpose Clock Generator module
+ *
+ * Registers defined in this header file:
+ * - MCG_C1 - MCG Control 1 Register
+ * - MCG_C2 - MCG Control 2 Register
+ * - MCG_C3 - MCG Control 3 Register
+ * - MCG_C4 - MCG Control 4 Register
+ * - MCG_C5 - MCG Control 5 Register
+ * - MCG_C6 - MCG Control 6 Register
+ * - MCG_S - MCG Status Register
+ * - MCG_SC - MCG Status and Control Register
+ * - MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ * - MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ * - MCG_C7 - MCG Control 7 Register
+ * - MCG_C8 - MCG Control 8 Register
+ */
+
+#define MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */
+#define MCG_IDX (0U) /*!< Instance number for MCG. */
+
+/*******************************************************************************
+ * MCG_C1 - MCG Control 1 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C1 - MCG Control 1 Register (RW)
+ *
+ * Reset value: 0x04U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C1 register
+ */
+/*@{*/
+#define MCG_RD_C1(base)          (MCG_C1_REG(base))
+#define MCG_WR_C1(base, value)   (MCG_C1_REG(base) = (value))
+#define MCG_RMW_C1(base, mask, value) (MCG_WR_C1(base, (MCG_RD_C1(base) & ~(mask)) | (value)))
+#define MCG_SET_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) |  (value)))
+#define MCG_CLR_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) & ~(value)))
+#define MCG_TOG_C1(base, value)  (MCG_WR_C1(base, MCG_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C1 bitfields
+ */
+
+/*!
+ * @name Register MCG_C1, field IREFSTEN[0] (RW)
+ *
+ * Controls whether or not the internal reference clock remains enabled when the
+ * MCG enters Stop mode.
+ *
+ * Values:
+ * - 0b0 - Internal reference clock is disabled in Stop mode.
+ * - 0b1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
+ *     if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFSTEN field. */
+#define MCG_RD_C1_IREFSTEN(base) ((MCG_C1_REG(base) & MCG_C1_IREFSTEN_MASK) >> MCG_C1_IREFSTEN_SHIFT)
+#define MCG_BRD_C1_IREFSTEN(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT))
+
+/*! @brief Set the IREFSTEN field to a new value. */
+#define MCG_WR_C1_IREFSTEN(base, value) (MCG_RMW_C1(base, MCG_C1_IREFSTEN_MASK, MCG_C1_IREFSTEN(value)))
+#define MCG_BWR_C1_IREFSTEN(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IRCLKEN[1] (RW)
+ *
+ * Enables the internal reference clock for use as MCGIRCLK.
+ *
+ * Values:
+ * - 0b0 - MCGIRCLK inactive.
+ * - 0b1 - MCGIRCLK active.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IRCLKEN field. */
+#define MCG_RD_C1_IRCLKEN(base) ((MCG_C1_REG(base) & MCG_C1_IRCLKEN_MASK) >> MCG_C1_IRCLKEN_SHIFT)
+#define MCG_BRD_C1_IRCLKEN(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT))
+
+/*! @brief Set the IRCLKEN field to a new value. */
+#define MCG_WR_C1_IRCLKEN(base, value) (MCG_RMW_C1(base, MCG_C1_IRCLKEN_MASK, MCG_C1_IRCLKEN(value)))
+#define MCG_BWR_C1_IRCLKEN(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field IREFS[2] (RW)
+ *
+ * Selects the reference clock source for the FLL.
+ *
+ * Values:
+ * - 0b0 - External reference clock is selected.
+ * - 0b1 - The slow internal reference clock is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_IREFS field. */
+#define MCG_RD_C1_IREFS(base) ((MCG_C1_REG(base) & MCG_C1_IREFS_MASK) >> MCG_C1_IREFS_SHIFT)
+#define MCG_BRD_C1_IREFS(base) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT))
+
+/*! @brief Set the IREFS field to a new value. */
+#define MCG_WR_C1_IREFS(base, value) (MCG_RMW_C1(base, MCG_C1_IREFS_MASK, MCG_C1_IREFS(value)))
+#define MCG_BWR_C1_IREFS(base, value) (BITBAND_ACCESS8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field FRDIV[5:3] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the FLL.
+ * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
+ * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
+ * not required to meet this range, but it is recommended in the cases when trying
+ * to enter a FLL mode from FBE).
+ *
+ * Values:
+ * - 0b000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
+ *     values, Divide Factor is 32.
+ * - 0b001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
+ *     values, Divide Factor is 64.
+ * - 0b010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
+ *     values, Divide Factor is 128.
+ * - 0b011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
+ *     values, Divide Factor is 256.
+ * - 0b100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
+ *     values, Divide Factor is 512.
+ * - 0b101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
+ *     values, Divide Factor is 1024.
+ * - 0b110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
+ *     values, Divide Factor is 1280 .
+ * - 0b111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other
+ *     RANGE values, Divide Factor is 1536 .
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_FRDIV field. */
+#define MCG_RD_C1_FRDIV(base) ((MCG_C1_REG(base) & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
+#define MCG_BRD_C1_FRDIV(base) (MCG_RD_C1_FRDIV(base))
+
+/*! @brief Set the FRDIV field to a new value. */
+#define MCG_WR_C1_FRDIV(base, value) (MCG_RMW_C1(base, MCG_C1_FRDIV_MASK, MCG_C1_FRDIV(value)))
+#define MCG_BWR_C1_FRDIV(base, value) (MCG_WR_C1_FRDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C1, field CLKS[7:6] (RW)
+ *
+ * Selects the clock source for MCGOUTCLK .
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS
+ *     control bit).
+ * - 0b01 - Encoding 1 - Internal reference clock is selected.
+ * - 0b10 - Encoding 2 - External reference clock is selected.
+ * - 0b11 - Encoding 3 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C1_CLKS field. */
+#define MCG_RD_C1_CLKS(base) ((MCG_C1_REG(base) & MCG_C1_CLKS_MASK) >> MCG_C1_CLKS_SHIFT)
+#define MCG_BRD_C1_CLKS(base) (MCG_RD_C1_CLKS(base))
+
+/*! @brief Set the CLKS field to a new value. */
+#define MCG_WR_C1_CLKS(base, value) (MCG_RMW_C1(base, MCG_C1_CLKS_MASK, MCG_C1_CLKS(value)))
+#define MCG_BWR_C1_CLKS(base, value) (MCG_WR_C1_CLKS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C2 - MCG Control 2 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C2 - MCG Control 2 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C2 register
+ */
+/*@{*/
+#define MCG_RD_C2(base)          (MCG_C2_REG(base))
+#define MCG_WR_C2(base, value)   (MCG_C2_REG(base) = (value))
+#define MCG_RMW_C2(base, mask, value) (MCG_WR_C2(base, (MCG_RD_C2(base) & ~(mask)) | (value)))
+#define MCG_SET_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) |  (value)))
+#define MCG_CLR_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) & ~(value)))
+#define MCG_TOG_C2(base, value)  (MCG_WR_C2(base, MCG_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C2 bitfields
+ */
+
+/*!
+ * @name Register MCG_C2, field IRCS[0] (RW)
+ *
+ * Selects between the fast or slow internal reference clock source.
+ *
+ * Values:
+ * - 0b0 - Slow internal reference clock selected.
+ * - 0b1 - Fast internal reference clock selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_IRCS field. */
+#define MCG_RD_C2_IRCS(base) ((MCG_C2_REG(base) & MCG_C2_IRCS_MASK) >> MCG_C2_IRCS_SHIFT)
+#define MCG_BRD_C2_IRCS(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT))
+
+/*! @brief Set the IRCS field to a new value. */
+#define MCG_WR_C2_IRCS(base, value) (MCG_RMW_C2(base, MCG_C2_IRCS_MASK, MCG_C2_IRCS(value)))
+#define MCG_BWR_C2_IRCS(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field LP[1] (RW)
+ *
+ * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
+ * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
+ * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
+ * other MCG mode, LP bit has no affect.
+ *
+ * Values:
+ * - 0b0 - FLL or PLL is not disabled in bypass modes.
+ * - 0b1 - FLL or PLL is disabled in bypass modes (lower power)
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_LP field. */
+#define MCG_RD_C2_LP(base)   ((MCG_C2_REG(base) & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
+#define MCG_BRD_C2_LP(base)  (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT))
+
+/*! @brief Set the LP field to a new value. */
+#define MCG_WR_C2_LP(base, value) (MCG_RMW_C2(base, MCG_C2_LP_MASK, MCG_C2_LP(value)))
+#define MCG_BWR_C2_LP(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field EREFS[2] (RW)
+ *
+ * Selects the source for the external reference clock. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0b0 - External reference clock requested.
+ * - 0b1 - Oscillator requested.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_EREFS field. */
+#define MCG_RD_C2_EREFS(base) ((MCG_C2_REG(base) & MCG_C2_EREFS_MASK) >> MCG_C2_EREFS_SHIFT)
+#define MCG_BRD_C2_EREFS(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT))
+
+/*! @brief Set the EREFS field to a new value. */
+#define MCG_WR_C2_EREFS(base, value) (MCG_RMW_C2(base, MCG_C2_EREFS_MASK, MCG_C2_EREFS(value)))
+#define MCG_BWR_C2_EREFS(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field HGO[3] (RW)
+ *
+ * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
+ * chapter for more details.
+ *
+ * Values:
+ * - 0b0 - Configure crystal oscillator for low-power operation.
+ * - 0b1 - Configure crystal oscillator for high-gain operation.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_HGO field. */
+#define MCG_RD_C2_HGO(base)  ((MCG_C2_REG(base) & MCG_C2_HGO_MASK) >> MCG_C2_HGO_SHIFT)
+#define MCG_BRD_C2_HGO(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT))
+
+/*! @brief Set the HGO field to a new value. */
+#define MCG_WR_C2_HGO(base, value) (MCG_RMW_C2(base, MCG_C2_HGO_MASK, MCG_C2_HGO(value)))
+#define MCG_BWR_C2_HGO(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field RANGE[5:4] (RW)
+ *
+ * Selects the frequency range for the crystal oscillator or external clock
+ * source. See the Oscillator (OSC) chapter for more details and the device data
+ * sheet for the frequency ranges used.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Low frequency range selected for the crystal oscillator
+ *     .
+ * - 0b01 - Encoding 1 - High frequency range selected for the crystal
+ *     oscillator .
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_RANGE field. */
+#define MCG_RD_C2_RANGE(base) ((MCG_C2_REG(base) & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
+#define MCG_BRD_C2_RANGE(base) (MCG_RD_C2_RANGE(base))
+
+/*! @brief Set the RANGE field to a new value. */
+#define MCG_WR_C2_RANGE(base, value) (MCG_RMW_C2(base, MCG_C2_RANGE_MASK, MCG_C2_RANGE(value)))
+#define MCG_BWR_C2_RANGE(base, value) (MCG_WR_C2_RANGE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field FCFTRIM[6] (RW)
+ *
+ * FCFTRIM controls the smallest adjustment of the fast internal reference clock
+ * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
+ * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_FCFTRIM field. */
+#define MCG_RD_C2_FCFTRIM(base) ((MCG_C2_REG(base) & MCG_C2_FCFTRIM_MASK) >> MCG_C2_FCFTRIM_SHIFT)
+#define MCG_BRD_C2_FCFTRIM(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT))
+
+/*! @brief Set the FCFTRIM field to a new value. */
+#define MCG_WR_C2_FCFTRIM(base, value) (MCG_RMW_C2(base, MCG_C2_FCFTRIM_MASK, MCG_C2_FCFTRIM(value)))
+#define MCG_BWR_C2_FCFTRIM(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C2, field LOCRE0[7] (RW)
+ *
+ * Determines whether an interrupt or a reset request is made following a loss
+ * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
+ * set.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a loss of OSC0 external reference
+ *     clock.
+ * - 0b1 - Generate a reset request on a loss of OSC0 external reference clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C2_LOCRE0 field. */
+#define MCG_RD_C2_LOCRE0(base) ((MCG_C2_REG(base) & MCG_C2_LOCRE0_MASK) >> MCG_C2_LOCRE0_SHIFT)
+#define MCG_BRD_C2_LOCRE0(base) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT))
+
+/*! @brief Set the LOCRE0 field to a new value. */
+#define MCG_WR_C2_LOCRE0(base, value) (MCG_RMW_C2(base, MCG_C2_LOCRE0_MASK, MCG_C2_LOCRE0(value)))
+#define MCG_BWR_C2_LOCRE0(base, value) (BITBAND_ACCESS8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C3 - MCG Control 3 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C3 - MCG Control 3 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C3 register
+ */
+/*@{*/
+#define MCG_RD_C3(base)          (MCG_C3_REG(base))
+#define MCG_WR_C3(base, value)   (MCG_C3_REG(base) = (value))
+#define MCG_RMW_C3(base, mask, value) (MCG_WR_C3(base, (MCG_RD_C3(base) & ~(mask)) | (value)))
+#define MCG_SET_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) |  (value)))
+#define MCG_CLR_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) & ~(value)))
+#define MCG_TOG_C3(base, value)  (MCG_WR_C3(base, MCG_RD_C3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C4 - MCG Control 4 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C4 - MCG Control 4 Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Reset values for DRST and DMX32 bits are 0.
+ */
+/*!
+ * @name Constants and macros for entire MCG_C4 register
+ */
+/*@{*/
+#define MCG_RD_C4(base)          (MCG_C4_REG(base))
+#define MCG_WR_C4(base, value)   (MCG_C4_REG(base) = (value))
+#define MCG_RMW_C4(base, mask, value) (MCG_WR_C4(base, (MCG_RD_C4(base) & ~(mask)) | (value)))
+#define MCG_SET_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) |  (value)))
+#define MCG_CLR_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) & ~(value)))
+#define MCG_TOG_C4(base, value)  (MCG_WR_C4(base, MCG_RD_C4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C4 bitfields
+ */
+
+/*!
+ * @name Register MCG_C4, field SCFTRIM[0] (RW)
+ *
+ * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
+ * location . controls the smallest adjustment of the slow internal reference
+ * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
+ * decreases the period by the smallest amount possible. If an SCFTRIM value stored in
+ * nonvolatile memory is to be used, it is your responsibility to copy that value
+ * from the nonvolatile memory location to this bit.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_SCFTRIM field. */
+#define MCG_RD_C4_SCFTRIM(base) ((MCG_C4_REG(base) & MCG_C4_SCFTRIM_MASK) >> MCG_C4_SCFTRIM_SHIFT)
+#define MCG_BRD_C4_SCFTRIM(base) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT))
+
+/*! @brief Set the SCFTRIM field to a new value. */
+#define MCG_WR_C4_SCFTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_SCFTRIM_MASK, MCG_C4_SCFTRIM(value)))
+#define MCG_BWR_C4_SCFTRIM(base, value) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field FCTRIM[4:1] (RW)
+ *
+ * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
+ * location. controls the fast internal reference clock frequency by controlling
+ * the fast internal reference clock period. The FCTRIM bits are binary weighted,
+ * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
+ * increases the period, and decreasing the value decreases the period. If an
+ * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
+ * responsibility to copy that value from the nonvolatile memory location to this register.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_FCTRIM field. */
+#define MCG_RD_C4_FCTRIM(base) ((MCG_C4_REG(base) & MCG_C4_FCTRIM_MASK) >> MCG_C4_FCTRIM_SHIFT)
+#define MCG_BRD_C4_FCTRIM(base) (MCG_RD_C4_FCTRIM(base))
+
+/*! @brief Set the FCTRIM field to a new value. */
+#define MCG_WR_C4_FCTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_FCTRIM_MASK, MCG_C4_FCTRIM(value)))
+#define MCG_BWR_C4_FCTRIM(base, value) (MCG_WR_C4_FCTRIM(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
+ *
+ * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
+ * LP bit is set, writes to the DRS bits are ignored. The DRST read field
+ * indicates the current frequency range for DCOOUT. The DRST field does not update
+ * immediately after a write to the DRS field due to internal synchronization between
+ * clock domains. See the DCO Frequency Range table for more details.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Low range (reset default).
+ * - 0b01 - Encoding 1 - Mid range.
+ * - 0b10 - Encoding 2 - Mid-high range.
+ * - 0b11 - Encoding 3 - High range.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_DRST_DRS field. */
+#define MCG_RD_C4_DRST_DRS(base) ((MCG_C4_REG(base) & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
+#define MCG_BRD_C4_DRST_DRS(base) (MCG_RD_C4_DRST_DRS(base))
+
+/*! @brief Set the DRST_DRS field to a new value. */
+#define MCG_WR_C4_DRST_DRS(base, value) (MCG_RMW_C4(base, MCG_C4_DRST_DRS_MASK, MCG_C4_DRST_DRS(value)))
+#define MCG_BWR_C4_DRST_DRS(base, value) (MCG_WR_C4_DRST_DRS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C4, field DMX32[7] (RW)
+ *
+ * The DMX32 bit controls whether the DCO frequency range is narrowed to its
+ * maximum frequency with a 32.768 kHz reference. The following table identifies
+ * settings for the DCO frequency range. The system clocks derived from this source
+ * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
+ * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
+ * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
+ * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
+ * 80-100 MHz 1 32.768 kHz 2929 96 MHz
+ *
+ * Values:
+ * - 0b0 - DCO has a default range of 25%.
+ * - 0b1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C4_DMX32 field. */
+#define MCG_RD_C4_DMX32(base) ((MCG_C4_REG(base) & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
+#define MCG_BRD_C4_DMX32(base) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT))
+
+/*! @brief Set the DMX32 field to a new value. */
+#define MCG_WR_C4_DMX32(base, value) (MCG_RMW_C4(base, MCG_C4_DMX32_MASK, MCG_C4_DMX32(value)))
+#define MCG_BWR_C4_DMX32(base, value) (BITBAND_ACCESS8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C5 - MCG Control 5 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C5 - MCG Control 5 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C5 register
+ */
+/*@{*/
+#define MCG_RD_C5(base)          (MCG_C5_REG(base))
+#define MCG_WR_C5(base, value)   (MCG_C5_REG(base) = (value))
+#define MCG_RMW_C5(base, mask, value) (MCG_WR_C5(base, (MCG_RD_C5(base) & ~(mask)) | (value)))
+#define MCG_SET_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) |  (value)))
+#define MCG_CLR_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) & ~(value)))
+#define MCG_TOG_C5(base, value)  (MCG_WR_C5(base, MCG_RD_C5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C5 bitfields
+ */
+
+/*!
+ * @name Register MCG_C5, field PRDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide down the external reference clock for the PLL.
+ * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
+ * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
+ * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
+ * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
+ * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
+ * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
+ * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
+ * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
+ * Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PRDIV0 field. */
+#define MCG_RD_C5_PRDIV0(base) ((MCG_C5_REG(base) & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
+#define MCG_BRD_C5_PRDIV0(base) (MCG_RD_C5_PRDIV0(base))
+
+/*! @brief Set the PRDIV0 field to a new value. */
+#define MCG_WR_C5_PRDIV0(base, value) (MCG_RMW_C5(base, MCG_C5_PRDIV0_MASK, MCG_C5_PRDIV0(value)))
+#define MCG_BWR_C5_PRDIV0(base, value) (MCG_WR_C5_PRDIV0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C5, field PLLSTEN0[5] (RW)
+ *
+ * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
+ * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
+ * has no affect and does not enable the PLL Clock to run if it is written to 1.
+ *
+ * Values:
+ * - 0b0 - MCGPLLCLK is disabled in any of the Stop modes.
+ * - 0b1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */
+#define MCG_RD_C5_PLLSTEN0(base) ((MCG_C5_REG(base) & MCG_C5_PLLSTEN0_MASK) >> MCG_C5_PLLSTEN0_SHIFT)
+#define MCG_BRD_C5_PLLSTEN0(base) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLSTEN0_SHIFT))
+
+/*! @brief Set the PLLSTEN0 field to a new value. */
+#define MCG_WR_C5_PLLSTEN0(base, value) (MCG_RMW_C5(base, MCG_C5_PLLSTEN0_MASK, MCG_C5_PLLSTEN0(value)))
+#define MCG_BWR_C5_PLLSTEN0(base, value) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLSTEN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C5, field PLLCLKEN0[6] (RW)
+ *
+ * Enables the PLL independent of PLLS and enables the PLL clock for use as
+ * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
+ * PLL reference clock in the range of 2 - 4 MHz range prior to setting the
+ * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
+ * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
+ * and the external oscillator is being used as the reference clock, the OSCINIT 0
+ * bit should be checked to make sure it is set.
+ *
+ * Values:
+ * - 0b0 - MCGPLLCLK is inactive.
+ * - 0b1 - MCGPLLCLK is active.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */
+#define MCG_RD_C5_PLLCLKEN0(base) ((MCG_C5_REG(base) & MCG_C5_PLLCLKEN0_MASK) >> MCG_C5_PLLCLKEN0_SHIFT)
+#define MCG_BRD_C5_PLLCLKEN0(base) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLCLKEN0_SHIFT))
+
+/*! @brief Set the PLLCLKEN0 field to a new value. */
+#define MCG_WR_C5_PLLCLKEN0(base, value) (MCG_RMW_C5(base, MCG_C5_PLLCLKEN0_MASK, MCG_C5_PLLCLKEN0(value)))
+#define MCG_BWR_C5_PLLCLKEN0(base, value) (BITBAND_ACCESS8(&MCG_C5_REG(base), MCG_C5_PLLCLKEN0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C6 - MCG Control 6 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C6 - MCG Control 6 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C6 register
+ */
+/*@{*/
+#define MCG_RD_C6(base)          (MCG_C6_REG(base))
+#define MCG_WR_C6(base, value)   (MCG_C6_REG(base) = (value))
+#define MCG_RMW_C6(base, mask, value) (MCG_WR_C6(base, (MCG_RD_C6(base) & ~(mask)) | (value)))
+#define MCG_SET_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) |  (value)))
+#define MCG_CLR_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) & ~(value)))
+#define MCG_TOG_C6(base, value)  (MCG_WR_C6(base, MCG_RD_C6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C6 bitfields
+ */
+
+/*!
+ * @name Register MCG_C6, field VDIV0[4:0] (RW)
+ *
+ * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
+ * establish the multiplication factor (M) applied to the reference clock frequency.
+ * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
+ * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
+ * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
+ * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
+ * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
+ * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
+ * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_VDIV0 field. */
+#define MCG_RD_C6_VDIV0(base) ((MCG_C6_REG(base) & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
+#define MCG_BRD_C6_VDIV0(base) (MCG_RD_C6_VDIV0(base))
+
+/*! @brief Set the VDIV0 field to a new value. */
+#define MCG_WR_C6_VDIV0(base, value) (MCG_RMW_C6(base, MCG_C6_VDIV0_MASK, MCG_C6_VDIV0(value)))
+#define MCG_BWR_C6_VDIV0(base, value) (MCG_WR_C6_VDIV0(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field CME0[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the OSC0 external reference
+ * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
+ * generated following a loss of OSC0 indication. The CME0 bit must only be set
+ * to a logic 1 when the MCG is in an operational mode that uses the external
+ * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
+ * the value of the RANGE0 bits in the C2 register should not be changed. CME0
+ * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur while in Stop mode. CME0 should also be set to a
+ * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
+ *
+ * Values:
+ * - 0b0 - External clock monitor is disabled for OSC0.
+ * - 0b1 - External clock monitor is enabled for OSC0.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_CME0 field. */
+#define MCG_RD_C6_CME0(base) ((MCG_C6_REG(base) & MCG_C6_CME0_MASK) >> MCG_C6_CME0_SHIFT)
+#define MCG_BRD_C6_CME0(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_CME0_SHIFT))
+
+/*! @brief Set the CME0 field to a new value. */
+#define MCG_WR_C6_CME0(base, value) (MCG_RMW_C6(base, MCG_C6_CME0_MASK, MCG_C6_CME0(value)))
+#define MCG_BWR_C6_CME0(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_CME0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field PLLS[6] (RW)
+ *
+ * Controls whether the PLL or FLL output is selected as the MCG source when
+ * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
+ * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
+ *
+ * Values:
+ * - 0b0 - FLL is selected.
+ * - 0b1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
+ *     to generate a PLL reference clock in the range of 2-4 MHz prior to
+ *     setting the PLLS bit).
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_PLLS field. */
+#define MCG_RD_C6_PLLS(base) ((MCG_C6_REG(base) & MCG_C6_PLLS_MASK) >> MCG_C6_PLLS_SHIFT)
+#define MCG_BRD_C6_PLLS(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_PLLS_SHIFT))
+
+/*! @brief Set the PLLS field to a new value. */
+#define MCG_WR_C6_PLLS(base, value) (MCG_RMW_C6(base, MCG_C6_PLLS_MASK, MCG_C6_PLLS(value)))
+#define MCG_BWR_C6_PLLS(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_PLLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C6, field LOLIE0[7] (RW)
+ *
+ * Determines if an interrupt request is made following a loss of lock
+ * indication. This bit only has an effect when LOLS 0 is set.
+ *
+ * Values:
+ * - 0b0 - No interrupt request is generated on loss of lock.
+ * - 0b1 - Generate an interrupt request on loss of lock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C6_LOLIE0 field. */
+#define MCG_RD_C6_LOLIE0(base) ((MCG_C6_REG(base) & MCG_C6_LOLIE0_MASK) >> MCG_C6_LOLIE0_SHIFT)
+#define MCG_BRD_C6_LOLIE0(base) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_LOLIE0_SHIFT))
+
+/*! @brief Set the LOLIE0 field to a new value. */
+#define MCG_WR_C6_LOLIE0(base, value) (MCG_RMW_C6(base, MCG_C6_LOLIE0_MASK, MCG_C6_LOLIE0(value)))
+#define MCG_BWR_C6_LOLIE0(base, value) (BITBAND_ACCESS8(&MCG_C6_REG(base), MCG_C6_LOLIE0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_S - MCG Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_S - MCG Status Register (RW)
+ *
+ * Reset value: 0x10U
+ */
+/*!
+ * @name Constants and macros for entire MCG_S register
+ */
+/*@{*/
+#define MCG_RD_S(base)           (MCG_S_REG(base))
+#define MCG_WR_S(base, value)    (MCG_S_REG(base) = (value))
+#define MCG_RMW_S(base, mask, value) (MCG_WR_S(base, (MCG_RD_S(base) & ~(mask)) | (value)))
+#define MCG_SET_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) |  (value)))
+#define MCG_CLR_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) & ~(value)))
+#define MCG_TOG_S(base, value)   (MCG_WR_S(base, MCG_RD_S(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_S bitfields
+ */
+
+/*!
+ * @name Register MCG_S, field IRCST[0] (RO)
+ *
+ * The IRCST bit indicates the current source for the internal reference clock
+ * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
+ * to the IRCS bit due to internal synchronization between clock domains. The
+ * IRCST bit will only be updated if the internal reference clock is enabled,
+ * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
+ * bit .
+ *
+ * Values:
+ * - 0b0 - Source of internal reference clock is the slow clock (32 kHz IRC).
+ * - 0b1 - Source of internal reference clock is the fast clock (4 MHz IRC).
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_IRCST field. */
+#define MCG_RD_S_IRCST(base) ((MCG_S_REG(base) & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT)
+#define MCG_BRD_S_IRCST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_IRCST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field OSCINIT0[1] (RO)
+ *
+ * This bit, which resets to 0, is set to 1 after the initialization cycles of
+ * the crystal oscillator clock have completed. After being set, the bit is
+ * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
+ * description for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_OSCINIT0 field. */
+#define MCG_RD_S_OSCINIT0(base) ((MCG_S_REG(base) & MCG_S_OSCINIT0_MASK) >> MCG_S_OSCINIT0_SHIFT)
+#define MCG_BRD_S_OSCINIT0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_OSCINIT0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field CLKST[3:2] (RO)
+ *
+ * These bits indicate the current clock mode. The CLKST bits do not update
+ * immediately after a write to the CLKS bits due to internal synchronization between
+ * clock domains.
+ *
+ * Values:
+ * - 0b00 - Encoding 0 - Output of the FLL is selected (reset default).
+ * - 0b01 - Encoding 1 - Internal reference clock is selected.
+ * - 0b10 - Encoding 2 - External reference clock is selected.
+ * - 0b11 - Encoding 3 - Output of the PLL is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_CLKST field. */
+#define MCG_RD_S_CLKST(base) ((MCG_S_REG(base) & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
+#define MCG_BRD_S_CLKST(base) (MCG_RD_S_CLKST(base))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field IREFST[4] (RO)
+ *
+ * This bit indicates the current source for the FLL reference clock. The IREFST
+ * bit does not update immediately after a write to the IREFS bit due to
+ * internal synchronization between clock domains.
+ *
+ * Values:
+ * - 0b0 - Source of FLL reference clock is the external reference clock.
+ * - 0b1 - Source of FLL reference clock is the internal reference clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_IREFST field. */
+#define MCG_RD_S_IREFST(base) ((MCG_S_REG(base) & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
+#define MCG_BRD_S_IREFST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_IREFST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field PLLST[5] (RO)
+ *
+ * This bit indicates the clock source selected by PLLS . The PLLST bit does not
+ * update immediately after a write to the PLLS bit due to internal
+ * synchronization between clock domains.
+ *
+ * Values:
+ * - 0b0 - Source of PLLS clock is FLL clock.
+ * - 0b1 - Source of PLLS clock is PLL output clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_PLLST field. */
+#define MCG_RD_S_PLLST(base) ((MCG_S_REG(base) & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT)
+#define MCG_BRD_S_PLLST(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_PLLST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field LOCK0[6] (RO)
+ *
+ * This bit indicates whether the PLL has acquired lock. Lock detection is only
+ * enabled when the PLL is enabled (either through clock mode selection or
+ * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
+ * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
+ * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
+ * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
+ * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
+ * reference clock will also cause the LOCK0 bit to clear until the PLL has
+ * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
+ * the lock status bit to clear and stay cleared until the Stop mode is exited
+ * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
+ * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
+ * again.
+ *
+ * Values:
+ * - 0b0 - PLL is currently unlocked.
+ * - 0b1 - PLL is currently locked.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_LOCK0 field. */
+#define MCG_RD_S_LOCK0(base) ((MCG_S_REG(base) & MCG_S_LOCK0_MASK) >> MCG_S_LOCK0_SHIFT)
+#define MCG_BRD_S_LOCK0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOCK0_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MCG_S, field LOLS0[7] (W1C)
+ *
+ * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
+ * if after acquiring lock, the PLL output frequency has fallen outside the lock
+ * exit frequency tolerance, D unl . LOLIE determines whether an interrupt
+ * request is made when LOLS is set. LOLRE determines whether a reset request is made
+ * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
+ * when set. Writing a logic 0 to this bit has no effect.
+ *
+ * Values:
+ * - 0b0 - PLL has not lost lock since LOLS 0 was last cleared.
+ * - 0b1 - PLL has lost lock since LOLS 0 was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_S_LOLS0 field. */
+#define MCG_RD_S_LOLS0(base) ((MCG_S_REG(base) & MCG_S_LOLS0_MASK) >> MCG_S_LOLS0_SHIFT)
+#define MCG_BRD_S_LOLS0(base) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOLS0_SHIFT))
+
+/*! @brief Set the LOLS0 field to a new value. */
+#define MCG_WR_S_LOLS0(base, value) (MCG_RMW_S(base, MCG_S_LOLS0_MASK, MCG_S_LOLS0(value)))
+#define MCG_BWR_S_LOLS0(base, value) (BITBAND_ACCESS8(&MCG_S_REG(base), MCG_S_LOLS0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_SC - MCG Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_SC - MCG Status and Control Register (RW)
+ *
+ * Reset value: 0x02U
+ */
+/*!
+ * @name Constants and macros for entire MCG_SC register
+ */
+/*@{*/
+#define MCG_RD_SC(base)          (MCG_SC_REG(base))
+#define MCG_WR_SC(base, value)   (MCG_SC_REG(base) = (value))
+#define MCG_RMW_SC(base, mask, value) (MCG_WR_SC(base, (MCG_RD_SC(base) & ~(mask)) | (value)))
+#define MCG_SET_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) |  (value)))
+#define MCG_CLR_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) & ~(value)))
+#define MCG_TOG_SC(base, value)  (MCG_WR_SC(base, MCG_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_SC bitfields
+ */
+
+/*!
+ * @name Register MCG_SC, field LOCS0[0] (W1C)
+ *
+ * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
+ * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
+ * logic 1 to it when set.
+ *
+ * Values:
+ * - 0b0 - Loss of OSC0 has not occurred.
+ * - 0b1 - Loss of OSC0 has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_LOCS0 field. */
+#define MCG_RD_SC_LOCS0(base) ((MCG_SC_REG(base) & MCG_SC_LOCS0_MASK) >> MCG_SC_LOCS0_SHIFT)
+#define MCG_BRD_SC_LOCS0(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT))
+
+/*! @brief Set the LOCS0 field to a new value. */
+#define MCG_WR_SC_LOCS0(base, value) (MCG_RMW_SC(base, MCG_SC_LOCS0_MASK, MCG_SC_LOCS0(value)))
+#define MCG_BWR_SC_LOCS0(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field FCRDIV[3:1] (RW)
+ *
+ * Selects the amount to divide down the fast internal reference clock. The
+ * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
+ * divider when the Fast IRC is enabled is not supported).
+ *
+ * Values:
+ * - 0b000 - Divide Factor is 1
+ * - 0b001 - Divide Factor is 2.
+ * - 0b010 - Divide Factor is 4.
+ * - 0b011 - Divide Factor is 8.
+ * - 0b100 - Divide Factor is 16
+ * - 0b101 - Divide Factor is 32
+ * - 0b110 - Divide Factor is 64
+ * - 0b111 - Divide Factor is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FCRDIV field. */
+#define MCG_RD_SC_FCRDIV(base) ((MCG_SC_REG(base) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
+#define MCG_BRD_SC_FCRDIV(base) (MCG_RD_SC_FCRDIV(base))
+
+/*! @brief Set the FCRDIV field to a new value. */
+#define MCG_WR_SC_FCRDIV(base, value) (MCG_RMW_SC(base, (MCG_SC_FCRDIV_MASK | MCG_SC_LOCS0_MASK), MCG_SC_FCRDIV(value)))
+#define MCG_BWR_SC_FCRDIV(base, value) (MCG_WR_SC_FCRDIV(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field FLTPRSRV[4] (RW)
+ *
+ * This bit will prevent the FLL filter values from resetting allowing the FLL
+ * output frequency to remain the same during clock mode changes where the FLL/DCO
+ * output is still valid. (Note: This requires that the FLL reference frequency
+ * to remain the same as what it was prior to the new clock mode switch.
+ * Otherwise FLL filter and frequency values will change.)
+ *
+ * Values:
+ * - 0b0 - FLL filter and FLL frequency will reset on changes to currect clock
+ *     mode.
+ * - 0b1 - Fll filter and FLL frequency retain their previous values during new
+ *     clock mode change.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_FLTPRSRV field. */
+#define MCG_RD_SC_FLTPRSRV(base) ((MCG_SC_REG(base) & MCG_SC_FLTPRSRV_MASK) >> MCG_SC_FLTPRSRV_SHIFT)
+#define MCG_BRD_SC_FLTPRSRV(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT))
+
+/*! @brief Set the FLTPRSRV field to a new value. */
+#define MCG_WR_SC_FLTPRSRV(base, value) (MCG_RMW_SC(base, (MCG_SC_FLTPRSRV_MASK | MCG_SC_LOCS0_MASK), MCG_SC_FLTPRSRV(value)))
+#define MCG_BWR_SC_FLTPRSRV(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATMF[5] (RW)
+ *
+ * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
+ * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
+ * registers is detected or the MCG enters into any Stop mode. A write to ATMF
+ * clears the flag.
+ *
+ * Values:
+ * - 0b0 - Automatic Trim Machine completed normally.
+ * - 0b1 - Automatic Trim Machine failed.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATMF field. */
+#define MCG_RD_SC_ATMF(base) ((MCG_SC_REG(base) & MCG_SC_ATMF_MASK) >> MCG_SC_ATMF_SHIFT)
+#define MCG_BRD_SC_ATMF(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT))
+
+/*! @brief Set the ATMF field to a new value. */
+#define MCG_WR_SC_ATMF(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMF(value)))
+#define MCG_BWR_SC_ATMF(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATMS[6] (RW)
+ *
+ * Selects the IRCS clock for Auto Trim Test.
+ *
+ * Values:
+ * - 0b0 - 32 kHz Internal Reference Clock selected.
+ * - 0b1 - 4 MHz Internal Reference Clock selected.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATMS field. */
+#define MCG_RD_SC_ATMS(base) ((MCG_SC_REG(base) & MCG_SC_ATMS_MASK) >> MCG_SC_ATMS_SHIFT)
+#define MCG_BRD_SC_ATMS(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT))
+
+/*! @brief Set the ATMS field to a new value. */
+#define MCG_WR_SC_ATMS(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMS(value)))
+#define MCG_BWR_SC_ATMS(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_SC, field ATME[7] (RW)
+ *
+ * Enables the Auto Trim Machine to start automatically trimming the selected
+ * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
+ * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
+ * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
+ * operation and clears this bit.
+ *
+ * Values:
+ * - 0b0 - Auto Trim Machine disabled.
+ * - 0b1 - Auto Trim Machine enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_SC_ATME field. */
+#define MCG_RD_SC_ATME(base) ((MCG_SC_REG(base) & MCG_SC_ATME_MASK) >> MCG_SC_ATME_SHIFT)
+#define MCG_BRD_SC_ATME(base) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT))
+
+/*! @brief Set the ATME field to a new value. */
+#define MCG_WR_SC_ATME(base, value) (MCG_RMW_SC(base, (MCG_SC_ATME_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATME(value)))
+#define MCG_BWR_SC_ATME(base, value) (BITBAND_ACCESS8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_ATCVH - MCG Auto Trim Compare Value High Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_ATCVH register
+ */
+/*@{*/
+#define MCG_RD_ATCVH(base)       (MCG_ATCVH_REG(base))
+#define MCG_WR_ATCVH(base, value) (MCG_ATCVH_REG(base) = (value))
+#define MCG_RMW_ATCVH(base, mask, value) (MCG_WR_ATCVH(base, (MCG_RD_ATCVH(base) & ~(mask)) | (value)))
+#define MCG_SET_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) |  (value)))
+#define MCG_CLR_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) & ~(value)))
+#define MCG_TOG_ATCVH(base, value) (MCG_WR_ATCVH(base, MCG_RD_ATCVH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_ATCVL - MCG Auto Trim Compare Value Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_ATCVL register
+ */
+/*@{*/
+#define MCG_RD_ATCVL(base)       (MCG_ATCVL_REG(base))
+#define MCG_WR_ATCVL(base, value) (MCG_ATCVL_REG(base) = (value))
+#define MCG_RMW_ATCVL(base, mask, value) (MCG_WR_ATCVL(base, (MCG_RD_ATCVL(base) & ~(mask)) | (value)))
+#define MCG_SET_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) |  (value)))
+#define MCG_CLR_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) & ~(value)))
+#define MCG_TOG_ATCVL(base, value) (MCG_WR_ATCVL(base, MCG_RD_ATCVL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C7 - MCG Control 7 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C7 - MCG Control 7 Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C7 register
+ */
+/*@{*/
+#define MCG_RD_C7(base)          (MCG_C7_REG(base))
+#define MCG_WR_C7(base, value)   (MCG_C7_REG(base) = (value))
+#define MCG_RMW_C7(base, mask, value) (MCG_WR_C7(base, (MCG_RD_C7(base) & ~(mask)) | (value)))
+#define MCG_SET_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) |  (value)))
+#define MCG_CLR_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) & ~(value)))
+#define MCG_TOG_C7(base, value)  (MCG_WR_C7(base, MCG_RD_C7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C7 bitfields
+ */
+
+/*!
+ * @name Register MCG_C7, field OSCSEL[1:0] (RW)
+ *
+ * Selects the MCG FLL external reference clock
+ *
+ * Values:
+ * - 0b00 - Selects Oscillator (OSCCLK0).
+ * - 0b01 - Selects 32 kHz RTC Oscillator.
+ * - 0b10 - Selects Oscillator (OSCCLK1).
+ * - 0b11 - RESERVED
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C7_OSCSEL field. */
+#define MCG_RD_C7_OSCSEL(base) ((MCG_C7_REG(base) & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
+#define MCG_BRD_C7_OSCSEL(base) (MCG_RD_C7_OSCSEL(base))
+
+/*! @brief Set the OSCSEL field to a new value. */
+#define MCG_WR_C7_OSCSEL(base, value) (MCG_RMW_C7(base, MCG_C7_OSCSEL_MASK, MCG_C7_OSCSEL(value)))
+#define MCG_BWR_C7_OSCSEL(base, value) (MCG_WR_C7_OSCSEL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCG_C8 - MCG Control 8 Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCG_C8 - MCG Control 8 Register (RW)
+ *
+ * Reset value: 0x80U
+ */
+/*!
+ * @name Constants and macros for entire MCG_C8 register
+ */
+/*@{*/
+#define MCG_RD_C8(base)          (MCG_C8_REG(base))
+#define MCG_WR_C8(base, value)   (MCG_C8_REG(base) = (value))
+#define MCG_RMW_C8(base, mask, value) (MCG_WR_C8(base, (MCG_RD_C8(base) & ~(mask)) | (value)))
+#define MCG_SET_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) |  (value)))
+#define MCG_CLR_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) & ~(value)))
+#define MCG_TOG_C8(base, value)  (MCG_WR_C8(base, MCG_RD_C8(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCG_C8 bitfields
+ */
+
+/*!
+ * @name Register MCG_C8, field LOCS1[0] (W1C)
+ *
+ * This bit indicates when a loss of clock has occurred. This bit is cleared by
+ * writing a logic 1 to it when set.
+ *
+ * Values:
+ * - 0b0 - Loss of RTC has not occur.
+ * - 0b1 - Loss of RTC has occur
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOCS1 field. */
+#define MCG_RD_C8_LOCS1(base) ((MCG_C8_REG(base) & MCG_C8_LOCS1_MASK) >> MCG_C8_LOCS1_SHIFT)
+#define MCG_BRD_C8_LOCS1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT))
+
+/*! @brief Set the LOCS1 field to a new value. */
+#define MCG_WR_C8_LOCS1(base, value) (MCG_RMW_C8(base, MCG_C8_LOCS1_MASK, MCG_C8_LOCS1(value)))
+#define MCG_BWR_C8_LOCS1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field CME1[5] (RW)
+ *
+ * Enables the loss of clock monitoring circuit for the output of the RTC
+ * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
+ * reset request is generated following a loss of RTC clock indication. The CME1
+ * bit should be set to a logic 1 when the MCG is in an operational mode that uses
+ * the RTC as its external reference clock or if the RTC is operational. CME1 bit
+ * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
+ * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
+ * before entering VLPR or VLPW power modes.
+ *
+ * Values:
+ * - 0b0 - External clock monitor is disabled for RTC clock.
+ * - 0b1 - External clock monitor is enabled for RTC clock.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_CME1 field. */
+#define MCG_RD_C8_CME1(base) ((MCG_C8_REG(base) & MCG_C8_CME1_MASK) >> MCG_C8_CME1_SHIFT)
+#define MCG_BRD_C8_CME1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT))
+
+/*! @brief Set the CME1 field to a new value. */
+#define MCG_WR_C8_CME1(base, value) (MCG_RMW_C8(base, (MCG_C8_CME1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_CME1(value)))
+#define MCG_BWR_C8_CME1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field LOLRE[6] (RW)
+ *
+ * Determines if an interrupt or a reset request is made following a PLL loss of
+ * lock.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a PLL loss of lock indication. The
+ *     PLL loss of lock interrupt enable bit must also be set to generate the
+ *     interrupt request.
+ * - 0b1 - Generate a reset request on a PLL loss of lock indication.
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOLRE field. */
+#define MCG_RD_C8_LOLRE(base) ((MCG_C8_REG(base) & MCG_C8_LOLRE_MASK) >> MCG_C8_LOLRE_SHIFT)
+#define MCG_BRD_C8_LOLRE(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOLRE_SHIFT))
+
+/*! @brief Set the LOLRE field to a new value. */
+#define MCG_WR_C8_LOLRE(base, value) (MCG_RMW_C8(base, (MCG_C8_LOLRE_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOLRE(value)))
+#define MCG_BWR_C8_LOLRE(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOLRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MCG_C8, field LOCRE1[7] (RW)
+ *
+ * Determines if a interrupt or a reset request is made following a loss of RTC
+ * external reference clock. The LOCRE1 only has an affect when CME1 is set.
+ *
+ * Values:
+ * - 0b0 - Interrupt request is generated on a loss of RTC external reference
+ *     clock.
+ * - 0b1 - Generate a reset request on a loss of RTC external reference clock
+ */
+/*@{*/
+/*! @brief Read current value of the MCG_C8_LOCRE1 field. */
+#define MCG_RD_C8_LOCRE1(base) ((MCG_C8_REG(base) & MCG_C8_LOCRE1_MASK) >> MCG_C8_LOCRE1_SHIFT)
+#define MCG_BRD_C8_LOCRE1(base) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT))
+
+/*! @brief Set the LOCRE1 field to a new value. */
+#define MCG_WR_C8_LOCRE1(base, value) (MCG_RMW_C8(base, (MCG_C8_LOCRE1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOCRE1(value)))
+#define MCG_BWR_C8_LOCRE1(base, value) (BITBAND_ACCESS8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 MCM
+ *
+ * Core Platform Miscellaneous Control Module
+ *
+ * Registers defined in this header file:
+ * - MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ * - MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ * - MCM_CR - Control Register
+ * - MCM_ISCR - Interrupt Status Register
+ * - MCM_ETBCC - ETB Counter Control register
+ * - MCM_ETBRL - ETB Reload register
+ * - MCM_ETBCNT - ETB Counter Value register
+ * - MCM_PID - Process ID register
+ */
+
+#define MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
+#define MCM_IDX (0U) /*!< Instance number for MCM. */
+
+/*******************************************************************************
+ * MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
+ *
+ * Reset value: 0x001FU
+ *
+ * PLASC is a 16-bit read-only register identifying the presence/absence of bus
+ * slave connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLASC register
+ */
+/*@{*/
+#define MCM_RD_PLASC(base)       (MCM_PLASC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLASC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLASC, field ASC[7:0] (RO)
+ *
+ * Values:
+ * - 0b00000000 - A bus slave connection to AXBS input port n is absent
+ * - 0b00000001 - A bus slave connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLASC_ASC field. */
+#define MCM_RD_PLASC_ASC(base) ((MCM_PLASC_REG(base) & MCM_PLASC_ASC_MASK) >> MCM_PLASC_ASC_SHIFT)
+#define MCM_BRD_PLASC_ASC(base) (MCM_RD_PLASC_ASC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
+ *
+ * Reset value: 0x0037U
+ *
+ * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
+ * master connections to the device's crossbar switch.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PLAMC register
+ */
+/*@{*/
+#define MCM_RD_PLAMC(base)       (MCM_PLAMC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PLAMC bitfields
+ */
+
+/*!
+ * @name Register MCM_PLAMC, field AMC[7:0] (RO)
+ *
+ * Values:
+ * - 0b00000000 - A bus master connection to AXBS input port n is absent
+ * - 0b00000001 - A bus master connection to AXBS input port n is present
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PLAMC_AMC field. */
+#define MCM_RD_PLAMC_AMC(base) ((MCM_PLAMC_REG(base) & MCM_PLAMC_AMC_MASK) >> MCM_PLAMC_AMC_SHIFT)
+#define MCM_BRD_PLAMC_AMC(base) (MCM_RD_PLAMC_AMC(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_CR - Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_CR - Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * CR defines the arbitration and protection schemes for the two system RAM
+ * arrays.
+ */
+/*!
+ * @name Constants and macros for entire MCM_CR register
+ */
+/*@{*/
+#define MCM_RD_CR(base)          (MCM_CR_REG(base))
+#define MCM_WR_CR(base, value)   (MCM_CR_REG(base) = (value))
+#define MCM_RMW_CR(base, mask, value) (MCM_WR_CR(base, (MCM_RD_CR(base) & ~(mask)) | (value)))
+#define MCM_SET_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) |  (value)))
+#define MCM_CLR_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) & ~(value)))
+#define MCM_TOG_CR(base, value)  (MCM_WR_CR(base, MCM_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_CR bitfields
+ */
+
+/*!
+ * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_U array.
+ *
+ * Values:
+ * - 0b00 - Round robin
+ * - 0b01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 0b10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 0b11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMUAP field. */
+#define MCM_RD_CR_SRAMUAP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMUAP_MASK) >> MCM_CR_SRAMUAP_SHIFT)
+#define MCM_BRD_CR_SRAMUAP(base) (MCM_RD_CR_SRAMUAP(base))
+
+/*! @brief Set the SRAMUAP field to a new value. */
+#define MCM_WR_CR_SRAMUAP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMUAP_MASK, MCM_CR_SRAMUAP(value)))
+#define MCM_BWR_CR_SRAMUAP(base, value) (MCM_WR_CR_SRAMUAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMUWP[26] (RW)
+ *
+ * When this bit is set, writes to SRAM_U array generates a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMUWP field. */
+#define MCM_RD_CR_SRAMUWP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMUWP_MASK) >> MCM_CR_SRAMUWP_SHIFT)
+#define MCM_BRD_CR_SRAMUWP(base) (MCM_RD_CR_SRAMUWP(base))
+
+/*! @brief Set the SRAMUWP field to a new value. */
+#define MCM_WR_CR_SRAMUWP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMUWP_MASK, MCM_CR_SRAMUWP(value)))
+#define MCM_BWR_CR_SRAMUWP(base, value) (MCM_WR_CR_SRAMUWP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
+ *
+ * Defines the arbitration scheme and priority for the processor and SRAM
+ * backdoor accesses to the SRAM_L array.
+ *
+ * Values:
+ * - 0b00 - Round robin
+ * - 0b01 - Special round robin (favors SRAM backoor accesses over the processor)
+ * - 0b10 - Fixed priority. Processor has highest, backdoor has lowest
+ * - 0b11 - Fixed priority. Backdoor has highest, processor has lowest
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMLAP field. */
+#define MCM_RD_CR_SRAMLAP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMLAP_MASK) >> MCM_CR_SRAMLAP_SHIFT)
+#define MCM_BRD_CR_SRAMLAP(base) (MCM_RD_CR_SRAMLAP(base))
+
+/*! @brief Set the SRAMLAP field to a new value. */
+#define MCM_WR_CR_SRAMLAP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMLAP_MASK, MCM_CR_SRAMLAP(value)))
+#define MCM_BWR_CR_SRAMLAP(base, value) (MCM_WR_CR_SRAMLAP(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_CR, field SRAMLWP[30] (RW)
+ *
+ * When this bit is set, writes to SRAM_L array generates a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_CR_SRAMLWP field. */
+#define MCM_RD_CR_SRAMLWP(base) ((MCM_CR_REG(base) & MCM_CR_SRAMLWP_MASK) >> MCM_CR_SRAMLWP_SHIFT)
+#define MCM_BRD_CR_SRAMLWP(base) (MCM_RD_CR_SRAMLWP(base))
+
+/*! @brief Set the SRAMLWP field to a new value. */
+#define MCM_WR_CR_SRAMLWP(base, value) (MCM_RMW_CR(base, MCM_CR_SRAMLWP_MASK, MCM_CR_SRAMLWP(value)))
+#define MCM_BWR_CR_SRAMLWP(base, value) (MCM_WR_CR_SRAMLWP(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ISCR - Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ISCR - Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ISCR register
+ */
+/*@{*/
+#define MCM_RD_ISCR(base)        (MCM_ISCR_REG(base))
+#define MCM_WR_ISCR(base, value) (MCM_ISCR_REG(base) = (value))
+#define MCM_RMW_ISCR(base, mask, value) (MCM_WR_ISCR(base, (MCM_RD_ISCR(base) & ~(mask)) | (value)))
+#define MCM_SET_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) |  (value)))
+#define MCM_CLR_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) & ~(value)))
+#define MCM_TOG_ISCR(base, value) (MCM_WR_ISCR(base, MCM_RD_ISCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ISCR bitfields
+ */
+
+/*!
+ * @name Register MCM_ISCR, field IRQ[1] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0b0 - No pending interrupt
+ * - 0b1 - Due to the ETB counter expiring, a normal interrupt is pending
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_IRQ field. */
+#define MCM_RD_ISCR_IRQ(base) ((MCM_ISCR_REG(base) & MCM_ISCR_IRQ_MASK) >> MCM_ISCR_IRQ_SHIFT)
+#define MCM_BRD_ISCR_IRQ(base) (MCM_RD_ISCR_IRQ(base))
+
+/*! @brief Set the IRQ field to a new value. */
+#define MCM_WR_ISCR_IRQ(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_IRQ(value)))
+#define MCM_BWR_ISCR_IRQ(base, value) (MCM_WR_ISCR_IRQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field NMI[2] (W1C)
+ *
+ * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
+ *
+ * Values:
+ * - 0b0 - No pending NMI
+ * - 0b1 - Due to the ETB counter expiring, an NMI is pending
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_NMI field. */
+#define MCM_RD_ISCR_NMI(base) ((MCM_ISCR_REG(base) & MCM_ISCR_NMI_MASK) >> MCM_ISCR_NMI_SHIFT)
+#define MCM_BRD_ISCR_NMI(base) (MCM_RD_ISCR_NMI(base))
+
+/*! @brief Set the NMI field to a new value. */
+#define MCM_WR_ISCR_NMI(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_NMI_MASK | MCM_ISCR_IRQ_MASK), MCM_ISCR_NMI(value)))
+#define MCM_BWR_ISCR_NMI(base, value) (MCM_WR_ISCR_NMI(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field DHREQ[3] (RO)
+ *
+ * Indicates that a debug halt request is initiated due to a ETB counter
+ * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
+ * counter is disabled or when the ETB counter is reloaded.
+ *
+ * Values:
+ * - 0b0 - No debug halt request
+ * - 0b1 - Debug halt request initiated
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_DHREQ field. */
+#define MCM_RD_ISCR_DHREQ(base) ((MCM_ISCR_REG(base) & MCM_ISCR_DHREQ_MASK) >> MCM_ISCR_DHREQ_SHIFT)
+#define MCM_BRD_ISCR_DHREQ(base) (MCM_RD_ISCR_DHREQ(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIOC[8] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
+ * illegal operation has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IOC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIOC field. */
+#define MCM_RD_ISCR_FIOC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIOC_MASK) >> MCM_ISCR_FIOC_SHIFT)
+#define MCM_BRD_ISCR_FIOC(base) (MCM_RD_ISCR_FIOC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FDZC[9] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
+ * divide by zero has been detected in the processor's FPU. Once set, this bit remains
+ * set until software clears the FPSCR[DZC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FDZC field. */
+#define MCM_RD_ISCR_FDZC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FDZC_MASK) >> MCM_ISCR_FDZC_SHIFT)
+#define MCM_BRD_ISCR_FDZC(base) (MCM_RD_ISCR_FDZC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FOFC[10] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
+ * overflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[OFC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FOFC field. */
+#define MCM_RD_ISCR_FOFC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FOFC_MASK) >> MCM_ISCR_FOFC_SHIFT)
+#define MCM_BRD_ISCR_FOFC(base) (MCM_RD_ISCR_FOFC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FUFC[11] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
+ * underflow has been detected in the processor's FPU. Once set, this bit remains set
+ * until software clears the FPSCR[UFC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FUFC field. */
+#define MCM_RD_ISCR_FUFC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FUFC_MASK) >> MCM_ISCR_FUFC_SHIFT)
+#define MCM_BRD_ISCR_FUFC(base) (MCM_RD_ISCR_FUFC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIXC[12] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
+ * inexact number has been detected in the processor's FPU. Once set, this bit
+ * remains set until software clears the FPSCR[IXC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIXC field. */
+#define MCM_RD_ISCR_FIXC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIXC_MASK) >> MCM_ISCR_FIXC_SHIFT)
+#define MCM_BRD_ISCR_FIXC(base) (MCM_RD_ISCR_FIXC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIDC[15] (RO)
+ *
+ * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
+ * denormalized number has been detected in the processor's FPU. Once set, this
+ * bit remains set until software clears the FPSCR[IDC] bit.
+ *
+ * Values:
+ * - 0b0 - No interrupt
+ * - 0b1 - Interrupt occurred
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIDC field. */
+#define MCM_RD_ISCR_FIDC(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIDC_MASK) >> MCM_ISCR_FIDC_SHIFT)
+#define MCM_BRD_ISCR_FIDC(base) (MCM_RD_ISCR_FIDC(base))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIOCE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIOCE field. */
+#define MCM_RD_ISCR_FIOCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIOCE_MASK) >> MCM_ISCR_FIOCE_SHIFT)
+#define MCM_BRD_ISCR_FIOCE(base) (MCM_RD_ISCR_FIOCE(base))
+
+/*! @brief Set the FIOCE field to a new value. */
+#define MCM_WR_ISCR_FIOCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIOCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIOCE(value)))
+#define MCM_BWR_ISCR_FIOCE(base, value) (MCM_WR_ISCR_FIOCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FDZCE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FDZCE field. */
+#define MCM_RD_ISCR_FDZCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FDZCE_MASK) >> MCM_ISCR_FDZCE_SHIFT)
+#define MCM_BRD_ISCR_FDZCE(base) (MCM_RD_ISCR_FDZCE(base))
+
+/*! @brief Set the FDZCE field to a new value. */
+#define MCM_WR_ISCR_FDZCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FDZCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FDZCE(value)))
+#define MCM_BWR_ISCR_FDZCE(base, value) (MCM_WR_ISCR_FDZCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FOFCE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FOFCE field. */
+#define MCM_RD_ISCR_FOFCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FOFCE_MASK) >> MCM_ISCR_FOFCE_SHIFT)
+#define MCM_BRD_ISCR_FOFCE(base) (MCM_RD_ISCR_FOFCE(base))
+
+/*! @brief Set the FOFCE field to a new value. */
+#define MCM_WR_ISCR_FOFCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FOFCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FOFCE(value)))
+#define MCM_BWR_ISCR_FOFCE(base, value) (MCM_WR_ISCR_FOFCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FUFCE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FUFCE field. */
+#define MCM_RD_ISCR_FUFCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FUFCE_MASK) >> MCM_ISCR_FUFCE_SHIFT)
+#define MCM_BRD_ISCR_FUFCE(base) (MCM_RD_ISCR_FUFCE(base))
+
+/*! @brief Set the FUFCE field to a new value. */
+#define MCM_WR_ISCR_FUFCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FUFCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FUFCE(value)))
+#define MCM_BWR_ISCR_FUFCE(base, value) (MCM_WR_ISCR_FUFCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIXCE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIXCE field. */
+#define MCM_RD_ISCR_FIXCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIXCE_MASK) >> MCM_ISCR_FIXCE_SHIFT)
+#define MCM_BRD_ISCR_FIXCE(base) (MCM_RD_ISCR_FIXCE(base))
+
+/*! @brief Set the FIXCE field to a new value. */
+#define MCM_WR_ISCR_FIXCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIXCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIXCE(value)))
+#define MCM_BWR_ISCR_FIXCE(base, value) (MCM_WR_ISCR_FIXCE(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ISCR, field FIDCE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable interrupt
+ * - 0b1 - Enable interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ISCR_FIDCE field. */
+#define MCM_RD_ISCR_FIDCE(base) ((MCM_ISCR_REG(base) & MCM_ISCR_FIDCE_MASK) >> MCM_ISCR_FIDCE_SHIFT)
+#define MCM_BRD_ISCR_FIDCE(base) (MCM_RD_ISCR_FIDCE(base))
+
+/*! @brief Set the FIDCE field to a new value. */
+#define MCM_WR_ISCR_FIDCE(base, value) (MCM_RMW_ISCR(base, (MCM_ISCR_FIDCE_MASK | MCM_ISCR_IRQ_MASK | MCM_ISCR_NMI_MASK), MCM_ISCR_FIDCE(value)))
+#define MCM_BWR_ISCR_FIDCE(base, value) (MCM_WR_ISCR_FIDCE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBCC - ETB Counter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBCC - ETB Counter Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBCC register
+ */
+/*@{*/
+#define MCM_RD_ETBCC(base)       (MCM_ETBCC_REG(base))
+#define MCM_WR_ETBCC(base, value) (MCM_ETBCC_REG(base) = (value))
+#define MCM_RMW_ETBCC(base, mask, value) (MCM_WR_ETBCC(base, (MCM_RD_ETBCC(base) & ~(mask)) | (value)))
+#define MCM_SET_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) |  (value)))
+#define MCM_CLR_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) & ~(value)))
+#define MCM_TOG_ETBCC(base, value) (MCM_WR_ETBCC(base, MCM_RD_ETBCC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBCC bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCC, field CNTEN[0] (RW)
+ *
+ * Enables the ETB counter.
+ *
+ * Values:
+ * - 0b0 - ETB counter disabled
+ * - 0b1 - ETB counter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_CNTEN field. */
+#define MCM_RD_ETBCC_CNTEN(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_CNTEN_MASK) >> MCM_ETBCC_CNTEN_SHIFT)
+#define MCM_BRD_ETBCC_CNTEN(base) (MCM_RD_ETBCC_CNTEN(base))
+
+/*! @brief Set the CNTEN field to a new value. */
+#define MCM_WR_ETBCC_CNTEN(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_CNTEN_MASK, MCM_ETBCC_CNTEN(value)))
+#define MCM_BWR_ETBCC_CNTEN(base, value) (MCM_WR_ETBCC_CNTEN(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
+ *
+ * Values:
+ * - 0b00 - No response when the ETB count expires
+ * - 0b01 - Generate a normal interrupt when the ETB count expires
+ * - 0b10 - Generate an NMI when the ETB count expires
+ * - 0b11 - Generate a debug halt when the ETB count expires
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_RSPT field. */
+#define MCM_RD_ETBCC_RSPT(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_RSPT_MASK) >> MCM_ETBCC_RSPT_SHIFT)
+#define MCM_BRD_ETBCC_RSPT(base) (MCM_RD_ETBCC_RSPT(base))
+
+/*! @brief Set the RSPT field to a new value. */
+#define MCM_WR_ETBCC_RSPT(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_RSPT_MASK, MCM_ETBCC_RSPT(value)))
+#define MCM_BWR_ETBCC_RSPT(base, value) (MCM_WR_ETBCC_RSPT(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field RLRQ[3] (RW)
+ *
+ * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
+ * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
+ * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
+ * If debug halt was enabled and a debug halt request was asserted on counter
+ * expiration, setting this bit clears the debug halt request.
+ *
+ * Values:
+ * - 0b0 - No effect
+ * - 0b1 - Clears pending debug halt, NMI, or IRQ interrupt requests
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_RLRQ field. */
+#define MCM_RD_ETBCC_RLRQ(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_RLRQ_MASK) >> MCM_ETBCC_RLRQ_SHIFT)
+#define MCM_BRD_ETBCC_RLRQ(base) (MCM_RD_ETBCC_RLRQ(base))
+
+/*! @brief Set the RLRQ field to a new value. */
+#define MCM_WR_ETBCC_RLRQ(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_RLRQ_MASK, MCM_ETBCC_RLRQ(value)))
+#define MCM_BWR_ETBCC_RLRQ(base, value) (MCM_WR_ETBCC_RLRQ(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field ETDIS[4] (RW)
+ *
+ * Disables the trace path from ETM to TPIU.
+ *
+ * Values:
+ * - 0b0 - ETM-to-TPIU trace path enabled
+ * - 0b1 - ETM-to-TPIU trace path disabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_ETDIS field. */
+#define MCM_RD_ETBCC_ETDIS(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_ETDIS_MASK) >> MCM_ETBCC_ETDIS_SHIFT)
+#define MCM_BRD_ETBCC_ETDIS(base) (MCM_RD_ETBCC_ETDIS(base))
+
+/*! @brief Set the ETDIS field to a new value. */
+#define MCM_WR_ETBCC_ETDIS(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_ETDIS_MASK, MCM_ETBCC_ETDIS(value)))
+#define MCM_BWR_ETBCC_ETDIS(base, value) (MCM_WR_ETBCC_ETDIS(base, value))
+/*@}*/
+
+/*!
+ * @name Register MCM_ETBCC, field ITDIS[5] (RW)
+ *
+ * Disables the trace path from ITM to TPIU.
+ *
+ * Values:
+ * - 0b0 - ITM-to-TPIU trace path enabled
+ * - 0b1 - ITM-to-TPIU trace path disabled
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCC_ITDIS field. */
+#define MCM_RD_ETBCC_ITDIS(base) ((MCM_ETBCC_REG(base) & MCM_ETBCC_ITDIS_MASK) >> MCM_ETBCC_ITDIS_SHIFT)
+#define MCM_BRD_ETBCC_ITDIS(base) (MCM_RD_ETBCC_ITDIS(base))
+
+/*! @brief Set the ITDIS field to a new value. */
+#define MCM_WR_ETBCC_ITDIS(base, value) (MCM_RMW_ETBCC(base, MCM_ETBCC_ITDIS_MASK, MCM_ETBCC_ITDIS(value)))
+#define MCM_BWR_ETBCC_ITDIS(base, value) (MCM_WR_ETBCC_ITDIS(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBRL - ETB Reload register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBRL - ETB Reload register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBRL register
+ */
+/*@{*/
+#define MCM_RD_ETBRL(base)       (MCM_ETBRL_REG(base))
+#define MCM_WR_ETBRL(base, value) (MCM_ETBRL_REG(base) = (value))
+#define MCM_RMW_ETBRL(base, mask, value) (MCM_WR_ETBRL(base, (MCM_RD_ETBRL(base) & ~(mask)) | (value)))
+#define MCM_SET_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) |  (value)))
+#define MCM_CLR_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) & ~(value)))
+#define MCM_TOG_ETBRL(base, value) (MCM_WR_ETBRL(base, MCM_RD_ETBRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBRL bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
+ *
+ * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
+ * value to this field results in a bus error.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBRL_RELOAD field. */
+#define MCM_RD_ETBRL_RELOAD(base) ((MCM_ETBRL_REG(base) & MCM_ETBRL_RELOAD_MASK) >> MCM_ETBRL_RELOAD_SHIFT)
+#define MCM_BRD_ETBRL_RELOAD(base) (MCM_RD_ETBRL_RELOAD(base))
+
+/*! @brief Set the RELOAD field to a new value. */
+#define MCM_WR_ETBRL_RELOAD(base, value) (MCM_RMW_ETBRL(base, MCM_ETBRL_RELOAD_MASK, MCM_ETBRL_RELOAD(value)))
+#define MCM_BWR_ETBRL_RELOAD(base, value) (MCM_WR_ETBRL_RELOAD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_ETBCNT - ETB Counter Value register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_ETBCNT - ETB Counter Value register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire MCM_ETBCNT register
+ */
+/*@{*/
+#define MCM_RD_ETBCNT(base)      (MCM_ETBCNT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_ETBCNT bitfields
+ */
+
+/*!
+ * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
+ *
+ * Indicates the current 0-mod-4 value of the counter.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_ETBCNT_COUNTER field. */
+#define MCM_RD_ETBCNT_COUNTER(base) ((MCM_ETBCNT_REG(base) & MCM_ETBCNT_COUNTER_MASK) >> MCM_ETBCNT_COUNTER_SHIFT)
+#define MCM_BRD_ETBCNT_COUNTER(base) (MCM_RD_ETBCNT_COUNTER(base))
+/*@}*/
+
+/*******************************************************************************
+ * MCM_PID - Process ID register
+ ******************************************************************************/
+
+/*!
+ * @brief MCM_PID - Process ID register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register drives the M0_PID and M1_PID values in the Memory Protection
+ * Unit(MPU). System software loads this register before passing control to a given
+ * user mode process. If the PID of the process does not match the value in this
+ * register, a bus error occurs. See the MPU chapter for more details.
+ */
+/*!
+ * @name Constants and macros for entire MCM_PID register
+ */
+/*@{*/
+#define MCM_RD_PID(base)         (MCM_PID_REG(base))
+#define MCM_WR_PID(base, value)  (MCM_PID_REG(base) = (value))
+#define MCM_RMW_PID(base, mask, value) (MCM_WR_PID(base, (MCM_RD_PID(base) & ~(mask)) | (value)))
+#define MCM_SET_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) |  (value)))
+#define MCM_CLR_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) & ~(value)))
+#define MCM_TOG_PID(base, value) (MCM_WR_PID(base, MCM_RD_PID(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MCM_PID bitfields
+ */
+
+/*!
+ * @name Register MCM_PID, field PID[7:0] (RW)
+ *
+ * Drives the M0_PID and M1_PID values in the MPU.
+ */
+/*@{*/
+/*! @brief Read current value of the MCM_PID_PID field. */
+#define MCM_RD_PID_PID(base) ((MCM_PID_REG(base) & MCM_PID_PID_MASK) >> MCM_PID_PID_SHIFT)
+#define MCM_BRD_PID_PID(base) (MCM_RD_PID_PID(base))
+
+/*! @brief Set the PID field to a new value. */
+#define MCM_WR_PID_PID(base, value) (MCM_RMW_PID(base, MCM_PID_PID_MASK, MCM_PID_PID(value)))
+#define MCM_BWR_PID_PID(base, value) (MCM_WR_PID_PID(base, value))
+/*@}*/
+
+/*
+ * MK64F12 MPU
+ *
+ * Memory protection unit
+ *
+ * Registers defined in this header file:
+ * - MPU_CESR - Control/Error Status Register
+ * - MPU_EAR - Error Address Register, slave port n
+ * - MPU_EDR - Error Detail Register, slave port n
+ * - MPU_WORD - Region Descriptor n, Word 0
+ * - MPU_RGDAAC - Region Descriptor Alternate Access Control n
+ */
+
+#define MPU_INSTANCE_COUNT (1U) /*!< Number of instances of the MPU module. */
+#define MPU_IDX (0U) /*!< Instance number for MPU. */
+
+/*******************************************************************************
+ * MPU_CESR - Control/Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_CESR - Control/Error Status Register (RW)
+ *
+ * Reset value: 0x00815101U
+ */
+/*!
+ * @name Constants and macros for entire MPU_CESR register
+ */
+/*@{*/
+#define MPU_RD_CESR(base)        (MPU_CESR_REG(base))
+#define MPU_WR_CESR(base, value) (MPU_CESR_REG(base) = (value))
+#define MPU_RMW_CESR(base, mask, value) (MPU_WR_CESR(base, (MPU_RD_CESR(base) & ~(mask)) | (value)))
+#define MPU_SET_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) |  (value)))
+#define MPU_CLR_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) & ~(value)))
+#define MPU_TOG_CESR(base, value) (MPU_WR_CESR(base, MPU_RD_CESR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_CESR bitfields
+ */
+
+/*!
+ * @name Register MPU_CESR, field VLD[0] (RW)
+ *
+ * Global enable/disable for the MPU.
+ *
+ * Values:
+ * - 0b0 - MPU is disabled. All accesses from all bus masters are allowed.
+ * - 0b1 - MPU is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_VLD field. */
+#define MPU_RD_CESR_VLD(base) ((MPU_CESR_REG(base) & MPU_CESR_VLD_MASK) >> MPU_CESR_VLD_SHIFT)
+#define MPU_BRD_CESR_VLD(base) (BITBAND_ACCESS32(&MPU_CESR_REG(base), MPU_CESR_VLD_SHIFT))
+
+/*! @brief Set the VLD field to a new value. */
+#define MPU_WR_CESR_VLD(base, value) (MPU_RMW_CESR(base, (MPU_CESR_VLD_MASK | MPU_CESR_SPERR_MASK), MPU_CESR_VLD(value)))
+#define MPU_BWR_CESR_VLD(base, value) (BITBAND_ACCESS32(&MPU_CESR_REG(base), MPU_CESR_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field NRGD[11:8] (RO)
+ *
+ * Indicates the number of region descriptors implemented in the MPU.
+ *
+ * Values:
+ * - 0b0000 - 8 region descriptors
+ * - 0b0001 - 12 region descriptors
+ * - 0b0010 - 16 region descriptors
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_NRGD field. */
+#define MPU_RD_CESR_NRGD(base) ((MPU_CESR_REG(base) & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT)
+#define MPU_BRD_CESR_NRGD(base) (MPU_RD_CESR_NRGD(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field NSP[15:12] (RO)
+ *
+ * Specifies the number of slave ports connected to the MPU.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_NSP field. */
+#define MPU_RD_CESR_NSP(base) ((MPU_CESR_REG(base) & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT)
+#define MPU_BRD_CESR_NSP(base) (MPU_RD_CESR_NSP(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field HRL[19:16] (RO)
+ *
+ * Specifies the MPU's hardware and definition revision level. It can be read by
+ * software to determine the functional definition of the module.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_HRL field. */
+#define MPU_RD_CESR_HRL(base) ((MPU_CESR_REG(base) & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT)
+#define MPU_BRD_CESR_HRL(base) (MPU_RD_CESR_HRL(base))
+/*@}*/
+
+/*!
+ * @name Register MPU_CESR, field SPERR[31:27] (W1C)
+ *
+ * Indicates a captured error in EARn and EDRn. This bit is set when the
+ * hardware detects an error and records the faulting address and attributes. It is
+ * cleared by writing one to it. If another error is captured at the exact same cycle
+ * as the write, the flag remains set. A find-first-one instruction or
+ * equivalent can detect the presence of a captured error. The following shows the
+ * correspondence between the bit number and slave port number: Bit 31 corresponds to
+ * slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
+ * port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
+ *
+ * Values:
+ * - 0b00000 - No error has occurred for slave port n.
+ * - 0b00001 - An error has occurred for slave port n.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_CESR_SPERR field. */
+#define MPU_RD_CESR_SPERR(base) ((MPU_CESR_REG(base) & MPU_CESR_SPERR_MASK) >> MPU_CESR_SPERR_SHIFT)
+#define MPU_BRD_CESR_SPERR(base) (MPU_RD_CESR_SPERR(base))
+
+/*! @brief Set the SPERR field to a new value. */
+#define MPU_WR_CESR_SPERR(base, value) (MPU_RMW_CESR(base, MPU_CESR_SPERR_MASK, MPU_CESR_SPERR(value)))
+#define MPU_BWR_CESR_SPERR(base, value) (MPU_WR_CESR_SPERR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_EAR - Error Address Register, slave port n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_EAR - Error Address Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, the 32-bit reference
+ * address is captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] set. Additional information about the faulting access is captured in
+ * the corresponding EDRn at the same time. This register and the corresponding
+ * EDRn contain the most recent access error; there are no hardware interlocks with
+ * CESR[SPERR], as the error registers are always loaded upon the occurrence of
+ * each protection violation.
+ */
+/*!
+ * @name Constants and macros for entire MPU_EAR register
+ */
+/*@{*/
+#define MPU_RD_EAR(base, index)  (MPU_EAR_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_EDR - Error Detail Register, slave port n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_EDR - Error Detail Register, slave port n (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the MPU detects an access error on slave port n, 32 bits of error detail
+ * are captured in this read-only register and the corresponding bit in
+ * CESR[SPERR] is set. Information on the faulting address is captured in the
+ * corresponding EARn register at the same time. This register and the corresponding EARn
+ * register contain the most recent access error; there are no hardware interlocks
+ * with CESR[SPERR] as the error registers are always loaded upon the occurrence
+ * of each protection violation.
+ */
+/*!
+ * @name Constants and macros for entire MPU_EDR register
+ */
+/*@{*/
+#define MPU_RD_EDR(base, index)  (MPU_EDR_REG(base, index))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_EDR bitfields
+ */
+
+/*!
+ * @name Register MPU_EDR, field ERW[0] (RO)
+ *
+ * Indicates the access type of the faulting reference.
+ *
+ * Values:
+ * - 0b0 - Read
+ * - 0b1 - Write
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_ERW field. */
+#define MPU_RD_EDR_ERW(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT)
+#define MPU_BRD_EDR_ERW(base, index) (BITBAND_ACCESS32(&MPU_EDR_REG(base, index), MPU_EDR_ERW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EATTR[3:1] (RO)
+ *
+ * Indicates attribute information about the faulting reference. All other
+ * encodings are reserved.
+ *
+ * Values:
+ * - 0b000 - User mode, instruction access
+ * - 0b001 - User mode, data access
+ * - 0b010 - Supervisor mode, instruction access
+ * - 0b011 - Supervisor mode, data access
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EATTR field. */
+#define MPU_RD_EDR_EATTR(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT)
+#define MPU_BRD_EDR_EATTR(base, index) (MPU_RD_EDR_EATTR(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EMN[7:4] (RO)
+ *
+ * Indicates the bus master that generated the access error.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EMN field. */
+#define MPU_RD_EDR_EMN(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT)
+#define MPU_BRD_EDR_EMN(base, index) (MPU_RD_EDR_EMN(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EPID[15:8] (RO)
+ *
+ * Records the process identifier of the faulting reference. The process
+ * identifier is typically driven only by processor cores; for other bus masters, this
+ * field is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EPID field. */
+#define MPU_RD_EDR_EPID(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT)
+#define MPU_BRD_EDR_EPID(base, index) (MPU_RD_EDR_EPID(base, index))
+/*@}*/
+
+/*!
+ * @name Register MPU_EDR, field EACD[31:16] (RO)
+ *
+ * Indicates the region descriptor with the access error. If EDRn contains a
+ * captured error and EACD is cleared, an access did not hit in any region
+ * descriptor. If only a single EACD bit is set, the protection error was caused by a
+ * single non-overlapping region descriptor. If two or more EACD bits are set, the
+ * protection error was caused by an overlapping set of region descriptors.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_EDR_EACD field. */
+#define MPU_RD_EDR_EACD(base, index) ((MPU_EDR_REG(base, index) & MPU_EDR_EACD_MASK) >> MPU_EDR_EACD_SHIFT)
+#define MPU_BRD_EDR_EACD(base, index) (MPU_RD_EDR_EACD(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_WORD - Region Descriptor n, Word 0
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_WORD - Region Descriptor n, Word 0 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The first word of the region descriptor defines the 0-modulo-32 byte start
+ * address of the memory region. Writes to this register clear the region
+ * descriptor's valid bit (RGDn_WORD3[VLD]).
+ */
+/*!
+ * @name Constants and macros for entire MPU_WORD register
+ */
+/*@{*/
+#define MPU_RD_WORD(base, index, index2) (MPU_WORD_REG(base, index, index2))
+#define MPU_WR_WORD(base, index, index2, value) (MPU_WORD_REG(base, index, index2) = (value))
+#define MPU_RMW_WORD(base, index, index2, mask, value) (MPU_WR_WORD(base, index, index2, (MPU_RD_WORD(base, index, index2) & ~(mask)) | (value)))
+#define MPU_SET_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) |  (value)))
+#define MPU_CLR_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) & ~(value)))
+#define MPU_TOG_WORD(base, index, index2, value) (MPU_WR_WORD(base, index, index2, MPU_RD_WORD(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_WORD bitfields
+ */
+
+/*!
+ * @name Register MPU_WORD, field VLD[0] (RW)
+ *
+ * Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
+ * bit.
+ *
+ * Values:
+ * - 0b0 - Region descriptor is invalid
+ * - 0b1 - Region descriptor is valid
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_VLD field. */
+#define MPU_RD_WORD_VLD(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_VLD_MASK) >> MPU_WORD_VLD_SHIFT)
+#define MPU_BRD_WORD_VLD(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_VLD_SHIFT))
+
+/*! @brief Set the VLD field to a new value. */
+#define MPU_WR_WORD_VLD(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_VLD_MASK, MPU_WORD_VLD(value)))
+#define MPU_BWR_WORD_VLD(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0UM field. */
+#define MPU_RD_WORD_M0UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0UM_MASK) >> MPU_WORD_M0UM_SHIFT)
+#define MPU_BRD_WORD_M0UM(base, index, index2) (MPU_RD_WORD_M0UM(base, index, index2))
+
+/*! @brief Set the M0UM field to a new value. */
+#define MPU_WR_WORD_M0UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0UM_MASK, MPU_WORD_M0UM(value)))
+#define MPU_BWR_WORD_M0UM(base, index, index2, value) (MPU_WR_WORD_M0UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0SM field. */
+#define MPU_RD_WORD_M0SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0SM_MASK) >> MPU_WORD_M0SM_SHIFT)
+#define MPU_BRD_WORD_M0SM(base, index, index2) (MPU_RD_WORD_M0SM(base, index, index2))
+
+/*! @brief Set the M0SM field to a new value. */
+#define MPU_WR_WORD_M0SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0SM_MASK, MPU_WORD_M0SM(value)))
+#define MPU_BWR_WORD_M0SM(base, index, index2, value) (MPU_WR_WORD_M0SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M0PE[5] (RW)
+ *
+ * See M0PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M0PE field. */
+#define MPU_RD_WORD_M0PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M0PE_MASK) >> MPU_WORD_M0PE_SHIFT)
+#define MPU_BRD_WORD_M0PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M0PE_SHIFT))
+
+/*! @brief Set the M0PE field to a new value. */
+#define MPU_WR_WORD_M0PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M0PE_MASK, MPU_WORD_M0PE(value)))
+#define MPU_BWR_WORD_M0PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M0PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field ENDADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 31-modulo-32 byte end address of the
+ * memory region. The MPU does not verify that ENDADDR >= SRTADDR.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_ENDADDR field. */
+#define MPU_RD_WORD_ENDADDR(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_ENDADDR_MASK) >> MPU_WORD_ENDADDR_SHIFT)
+#define MPU_BRD_WORD_ENDADDR(base, index, index2) (MPU_RD_WORD_ENDADDR(base, index, index2))
+
+/*! @brief Set the ENDADDR field to a new value. */
+#define MPU_WR_WORD_ENDADDR(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_ENDADDR_MASK, MPU_WORD_ENDADDR(value)))
+#define MPU_BWR_WORD_ENDADDR(base, index, index2, value) (MPU_WR_WORD_ENDADDR(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field SRTADDR[31:5] (RW)
+ *
+ * Defines the most significant bits of the 0-modulo-32 byte start address of
+ * the memory region.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_SRTADDR field. */
+#define MPU_RD_WORD_SRTADDR(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_SRTADDR_MASK) >> MPU_WORD_SRTADDR_SHIFT)
+#define MPU_BRD_WORD_SRTADDR(base, index, index2) (MPU_RD_WORD_SRTADDR(base, index, index2))
+
+/*! @brief Set the SRTADDR field to a new value. */
+#define MPU_WR_WORD_SRTADDR(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_SRTADDR_MASK, MPU_WORD_SRTADDR(value)))
+#define MPU_BWR_WORD_SRTADDR(base, index, index2, value) (MPU_WR_WORD_SRTADDR(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1UM field. */
+#define MPU_RD_WORD_M1UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1UM_MASK) >> MPU_WORD_M1UM_SHIFT)
+#define MPU_BRD_WORD_M1UM(base, index, index2) (MPU_RD_WORD_M1UM(base, index, index2))
+
+/*! @brief Set the M1UM field to a new value. */
+#define MPU_WR_WORD_M1UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1UM_MASK, MPU_WORD_M1UM(value)))
+#define MPU_BWR_WORD_M1UM(base, index, index2, value) (MPU_WR_WORD_M1UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1SM field. */
+#define MPU_RD_WORD_M1SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1SM_MASK) >> MPU_WORD_M1SM_SHIFT)
+#define MPU_BRD_WORD_M1SM(base, index, index2) (MPU_RD_WORD_M1SM(base, index, index2))
+
+/*! @brief Set the M1SM field to a new value. */
+#define MPU_WR_WORD_M1SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1SM_MASK, MPU_WORD_M1SM(value)))
+#define MPU_BWR_WORD_M1SM(base, index, index2, value) (MPU_WR_WORD_M1SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M1PE field. */
+#define MPU_RD_WORD_M1PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M1PE_MASK) >> MPU_WORD_M1PE_SHIFT)
+#define MPU_BRD_WORD_M1PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M1PE_SHIFT))
+
+/*! @brief Set the M1PE field to a new value. */
+#define MPU_WR_WORD_M1PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M1PE_MASK, MPU_WORD_M1PE(value)))
+#define MPU_BWR_WORD_M1PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M1PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2UM field. */
+#define MPU_RD_WORD_M2UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2UM_MASK) >> MPU_WORD_M2UM_SHIFT)
+#define MPU_BRD_WORD_M2UM(base, index, index2) (MPU_RD_WORD_M2UM(base, index, index2))
+
+/*! @brief Set the M2UM field to a new value. */
+#define MPU_WR_WORD_M2UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2UM_MASK, MPU_WORD_M2UM(value)))
+#define MPU_BWR_WORD_M2UM(base, index, index2, value) (MPU_WR_WORD_M2UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2SM field. */
+#define MPU_RD_WORD_M2SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2SM_MASK) >> MPU_WORD_M2SM_SHIFT)
+#define MPU_BRD_WORD_M2SM(base, index, index2) (MPU_RD_WORD_M2SM(base, index, index2))
+
+/*! @brief Set the M2SM field to a new value. */
+#define MPU_WR_WORD_M2SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2SM_MASK, MPU_WORD_M2SM(value)))
+#define MPU_BWR_WORD_M2SM(base, index, index2, value) (MPU_WR_WORD_M2SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field PIDMASK[23:16] (RW)
+ *
+ * Provides a masking capability so that multiple process identifiers can be
+ * included as part of the region hit determination. If a bit in PIDMASK is set,
+ * then the corresponding PID bit is ignored in the comparison. This field and PID
+ * are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
+ * more information on the handling of the PID and PIDMASK, see "Access Evaluation
+ * - Hit Determination."
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_PIDMASK field. */
+#define MPU_RD_WORD_PIDMASK(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_PIDMASK_MASK) >> MPU_WORD_PIDMASK_SHIFT)
+#define MPU_BRD_WORD_PIDMASK(base, index, index2) (MPU_RD_WORD_PIDMASK(base, index, index2))
+
+/*! @brief Set the PIDMASK field to a new value. */
+#define MPU_WR_WORD_PIDMASK(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_PIDMASK_MASK, MPU_WORD_PIDMASK(value)))
+#define MPU_BWR_WORD_PIDMASK(base, index, index2, value) (MPU_WR_WORD_PIDMASK(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M2PE field. */
+#define MPU_RD_WORD_M2PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M2PE_MASK) >> MPU_WORD_M2PE_SHIFT)
+#define MPU_BRD_WORD_M2PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M2PE_SHIFT))
+
+/*! @brief Set the M2PE field to a new value. */
+#define MPU_WR_WORD_M2PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M2PE_MASK, MPU_WORD_M2PE(value)))
+#define MPU_BWR_WORD_M2PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M2PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in User mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0b000 - An attempted access of that mode may be terminated with an access
+ *     error (if not allowed by another descriptor) and the access not performed.
+ * - 0b001 - Allows the given access type to occur
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3UM field. */
+#define MPU_RD_WORD_M3UM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3UM_MASK) >> MPU_WORD_M3UM_SHIFT)
+#define MPU_BRD_WORD_M3UM(base, index, index2) (MPU_RD_WORD_M3UM(base, index, index2))
+
+/*! @brief Set the M3UM field to a new value. */
+#define MPU_WR_WORD_M3UM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3UM_MASK, MPU_WORD_M3UM(value)))
+#define MPU_BWR_WORD_M3UM(base, index, index2, value) (MPU_WR_WORD_M3UM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 0b00 - r/w/x; read, write and execute allowed
+ * - 0b01 - r/x; read and execute allowed, but no write
+ * - 0b10 - r/w; read and write allowed, but no execute
+ * - 0b11 - Same as User mode defined in M3UM
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3SM field. */
+#define MPU_RD_WORD_M3SM(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3SM_MASK) >> MPU_WORD_M3SM_SHIFT)
+#define MPU_BRD_WORD_M3SM(base, index, index2) (MPU_RD_WORD_M3SM(base, index, index2))
+
+/*! @brief Set the M3SM field to a new value. */
+#define MPU_WR_WORD_M3SM(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3SM_MASK, MPU_WORD_M3SM(value)))
+#define MPU_BWR_WORD_M3SM(base, index, index2, value) (MPU_WR_WORD_M3SM(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the process identifier in the evaluation
+ * - 0b1 - Include the process identifier and mask (RGDn_WORD3) in the region
+ *     hit evaluation
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M3PE field. */
+#define MPU_RD_WORD_M3PE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M3PE_MASK) >> MPU_WORD_M3PE_SHIFT)
+#define MPU_BRD_WORD_M3PE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M3PE_SHIFT))
+
+/*! @brief Set the M3PE field to a new value. */
+#define MPU_WR_WORD_M3PE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M3PE_MASK, MPU_WORD_M3PE(value)))
+#define MPU_BWR_WORD_M3PE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M3PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field PID[31:24] (RW)
+ *
+ * Specifies the process identifier that is included in the region hit
+ * determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
+ * field.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_PID field. */
+#define MPU_RD_WORD_PID(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_PID_MASK) >> MPU_WORD_PID_SHIFT)
+#define MPU_BRD_WORD_PID(base, index, index2) (MPU_RD_WORD_PID(base, index, index2))
+
+/*! @brief Set the PID field to a new value. */
+#define MPU_WR_WORD_PID(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_PID_MASK, MPU_WORD_PID(value)))
+#define MPU_BWR_WORD_PID(base, index, index2, value) (MPU_WR_WORD_PID(base, index, index2, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 4 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M4WE field. */
+#define MPU_RD_WORD_M4WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M4WE_MASK) >> MPU_WORD_M4WE_SHIFT)
+#define MPU_BRD_WORD_M4WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4WE_SHIFT))
+
+/*! @brief Set the M4WE field to a new value. */
+#define MPU_WR_WORD_M4WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M4WE_MASK, MPU_WORD_M4WE(value)))
+#define MPU_BWR_WORD_M4WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 4 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M4RE field. */
+#define MPU_RD_WORD_M4RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M4RE_MASK) >> MPU_WORD_M4RE_SHIFT)
+#define MPU_BRD_WORD_M4RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4RE_SHIFT))
+
+/*! @brief Set the M4RE field to a new value. */
+#define MPU_WR_WORD_M4RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M4RE_MASK, MPU_WORD_M4RE(value)))
+#define MPU_BWR_WORD_M4RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M4RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 5 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M5WE field. */
+#define MPU_RD_WORD_M5WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M5WE_MASK) >> MPU_WORD_M5WE_SHIFT)
+#define MPU_BRD_WORD_M5WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5WE_SHIFT))
+
+/*! @brief Set the M5WE field to a new value. */
+#define MPU_WR_WORD_M5WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M5WE_MASK, MPU_WORD_M5WE(value)))
+#define MPU_BWR_WORD_M5WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 5 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M5RE field. */
+#define MPU_RD_WORD_M5RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M5RE_MASK) >> MPU_WORD_M5RE_SHIFT)
+#define MPU_BRD_WORD_M5RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5RE_SHIFT))
+
+/*! @brief Set the M5RE field to a new value. */
+#define MPU_WR_WORD_M5RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M5RE_MASK, MPU_WORD_M5RE(value)))
+#define MPU_BWR_WORD_M5RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M5RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 6 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M6WE field. */
+#define MPU_RD_WORD_M6WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M6WE_MASK) >> MPU_WORD_M6WE_SHIFT)
+#define MPU_BRD_WORD_M6WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6WE_SHIFT))
+
+/*! @brief Set the M6WE field to a new value. */
+#define MPU_WR_WORD_M6WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M6WE_MASK, MPU_WORD_M6WE(value)))
+#define MPU_BWR_WORD_M6WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 6 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M6RE field. */
+#define MPU_RD_WORD_M6RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M6RE_MASK) >> MPU_WORD_M6RE_SHIFT)
+#define MPU_BRD_WORD_M6RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6RE_SHIFT))
+
+/*! @brief Set the M6RE field to a new value. */
+#define MPU_WR_WORD_M6RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M6RE_MASK, MPU_WORD_M6RE(value)))
+#define MPU_BWR_WORD_M6RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M6RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 7 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M7WE field. */
+#define MPU_RD_WORD_M7WE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M7WE_MASK) >> MPU_WORD_M7WE_SHIFT)
+#define MPU_BRD_WORD_M7WE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7WE_SHIFT))
+
+/*! @brief Set the M7WE field to a new value. */
+#define MPU_WR_WORD_M7WE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M7WE_MASK, MPU_WORD_M7WE(value)))
+#define MPU_BWR_WORD_M7WE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_WORD, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 7 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_WORD_M7RE field. */
+#define MPU_RD_WORD_M7RE(base, index, index2) ((MPU_WORD_REG(base, index, index2) & MPU_WORD_M7RE_MASK) >> MPU_WORD_M7RE_SHIFT)
+#define MPU_BRD_WORD_M7RE(base, index, index2) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7RE_SHIFT))
+
+/*! @brief Set the M7RE field to a new value. */
+#define MPU_WR_WORD_M7RE(base, index, index2, value) (MPU_RMW_WORD(base, index, index2, MPU_WORD_M7RE_MASK, MPU_WORD_M7RE(value)))
+#define MPU_BWR_WORD_M7RE(base, index, index2, value) (BITBAND_ACCESS32(&MPU_WORD_REG(base, index, index2), MPU_WORD_M7RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * MPU_RGDAAC - Region Descriptor Alternate Access Control n
+ ******************************************************************************/
+
+/*!
+ * @brief MPU_RGDAAC - Region Descriptor Alternate Access Control n (RW)
+ *
+ * Reset value: 0x0061F7DFU
+ *
+ * Because software may adjust only the access controls within a region
+ * descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
+ * this 32-bit entity is available. Writing to this register does not affect the
+ * descriptor's valid bit.
+ */
+/*!
+ * @name Constants and macros for entire MPU_RGDAAC register
+ */
+/*@{*/
+#define MPU_RD_RGDAAC(base, index) (MPU_RGDAAC_REG(base, index))
+#define MPU_WR_RGDAAC(base, index, value) (MPU_RGDAAC_REG(base, index) = (value))
+#define MPU_RMW_RGDAAC(base, index, mask, value) (MPU_WR_RGDAAC(base, index, (MPU_RD_RGDAAC(base, index) & ~(mask)) | (value)))
+#define MPU_SET_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) |  (value)))
+#define MPU_CLR_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) & ~(value)))
+#define MPU_TOG_RGDAAC(base, index, value) (MPU_WR_RGDAAC(base, index, MPU_RD_RGDAAC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual MPU_RGDAAC bitfields
+ */
+
+/*!
+ * @name Register MPU_RGDAAC, field M0UM[2:0] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0UM field. */
+#define MPU_RD_RGDAAC_M0UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0UM_MASK) >> MPU_RGDAAC_M0UM_SHIFT)
+#define MPU_BRD_RGDAAC_M0UM(base, index) (MPU_RD_RGDAAC_M0UM(base, index))
+
+/*! @brief Set the M0UM field to a new value. */
+#define MPU_WR_RGDAAC_M0UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0UM_MASK, MPU_RGDAAC_M0UM(value)))
+#define MPU_BWR_RGDAAC_M0UM(base, index, value) (MPU_WR_RGDAAC_M0UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M0SM[4:3] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0SM field. */
+#define MPU_RD_RGDAAC_M0SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0SM_MASK) >> MPU_RGDAAC_M0SM_SHIFT)
+#define MPU_BRD_RGDAAC_M0SM(base, index) (MPU_RD_RGDAAC_M0SM(base, index))
+
+/*! @brief Set the M0SM field to a new value. */
+#define MPU_WR_RGDAAC_M0SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0SM_MASK, MPU_RGDAAC_M0SM(value)))
+#define MPU_BWR_RGDAAC_M0SM(base, index, value) (MPU_WR_RGDAAC_M0SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M0PE[5] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M0PE field. */
+#define MPU_RD_RGDAAC_M0PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M0PE_MASK) >> MPU_RGDAAC_M0PE_SHIFT)
+#define MPU_BRD_RGDAAC_M0PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M0PE_SHIFT))
+
+/*! @brief Set the M0PE field to a new value. */
+#define MPU_WR_RGDAAC_M0PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M0PE_MASK, MPU_RGDAAC_M0PE(value)))
+#define MPU_BWR_RGDAAC_M0PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M0PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1UM[8:6] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1UM field. */
+#define MPU_RD_RGDAAC_M1UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1UM_MASK) >> MPU_RGDAAC_M1UM_SHIFT)
+#define MPU_BRD_RGDAAC_M1UM(base, index) (MPU_RD_RGDAAC_M1UM(base, index))
+
+/*! @brief Set the M1UM field to a new value. */
+#define MPU_WR_RGDAAC_M1UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1UM_MASK, MPU_RGDAAC_M1UM(value)))
+#define MPU_BWR_RGDAAC_M1UM(base, index, value) (MPU_WR_RGDAAC_M1UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1SM[10:9] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1SM field. */
+#define MPU_RD_RGDAAC_M1SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1SM_MASK) >> MPU_RGDAAC_M1SM_SHIFT)
+#define MPU_BRD_RGDAAC_M1SM(base, index) (MPU_RD_RGDAAC_M1SM(base, index))
+
+/*! @brief Set the M1SM field to a new value. */
+#define MPU_WR_RGDAAC_M1SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1SM_MASK, MPU_RGDAAC_M1SM(value)))
+#define MPU_BWR_RGDAAC_M1SM(base, index, value) (MPU_WR_RGDAAC_M1SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M1PE[11] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M1PE field. */
+#define MPU_RD_RGDAAC_M1PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M1PE_MASK) >> MPU_RGDAAC_M1PE_SHIFT)
+#define MPU_BRD_RGDAAC_M1PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M1PE_SHIFT))
+
+/*! @brief Set the M1PE field to a new value. */
+#define MPU_WR_RGDAAC_M1PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M1PE_MASK, MPU_RGDAAC_M1PE(value)))
+#define MPU_BWR_RGDAAC_M1PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M1PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2UM[14:12] (RW)
+ *
+ * See M3UM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2UM field. */
+#define MPU_RD_RGDAAC_M2UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2UM_MASK) >> MPU_RGDAAC_M2UM_SHIFT)
+#define MPU_BRD_RGDAAC_M2UM(base, index) (MPU_RD_RGDAAC_M2UM(base, index))
+
+/*! @brief Set the M2UM field to a new value. */
+#define MPU_WR_RGDAAC_M2UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2UM_MASK, MPU_RGDAAC_M2UM(value)))
+#define MPU_BWR_RGDAAC_M2UM(base, index, value) (MPU_WR_RGDAAC_M2UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2SM[16:15] (RW)
+ *
+ * See M3SM description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2SM field. */
+#define MPU_RD_RGDAAC_M2SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2SM_MASK) >> MPU_RGDAAC_M2SM_SHIFT)
+#define MPU_BRD_RGDAAC_M2SM(base, index) (MPU_RD_RGDAAC_M2SM(base, index))
+
+/*! @brief Set the M2SM field to a new value. */
+#define MPU_WR_RGDAAC_M2SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2SM_MASK, MPU_RGDAAC_M2SM(value)))
+#define MPU_BWR_RGDAAC_M2SM(base, index, value) (MPU_WR_RGDAAC_M2SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M2PE[17] (RW)
+ *
+ * See M3PE description.
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M2PE field. */
+#define MPU_RD_RGDAAC_M2PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M2PE_MASK) >> MPU_RGDAAC_M2PE_SHIFT)
+#define MPU_BRD_RGDAAC_M2PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M2PE_SHIFT))
+
+/*! @brief Set the M2PE field to a new value. */
+#define MPU_WR_RGDAAC_M2PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M2PE_MASK, MPU_RGDAAC_M2PE(value)))
+#define MPU_BWR_RGDAAC_M2PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M2PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3UM[20:18] (RW)
+ *
+ * Defines the access controls for bus master 3 in user mode. M3UM consists of
+ * three independent bits, enabling read (r), write (w), and execute (x)
+ * permissions.
+ *
+ * Values:
+ * - 0b000 - An attempted access of that mode may be terminated with an access
+ *     error (if not allowed by another descriptor) and the access not performed.
+ * - 0b001 - Allows the given access type to occur
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3UM field. */
+#define MPU_RD_RGDAAC_M3UM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3UM_MASK) >> MPU_RGDAAC_M3UM_SHIFT)
+#define MPU_BRD_RGDAAC_M3UM(base, index) (MPU_RD_RGDAAC_M3UM(base, index))
+
+/*! @brief Set the M3UM field to a new value. */
+#define MPU_WR_RGDAAC_M3UM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3UM_MASK, MPU_RGDAAC_M3UM(value)))
+#define MPU_BWR_RGDAAC_M3UM(base, index, value) (MPU_WR_RGDAAC_M3UM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3SM[22:21] (RW)
+ *
+ * Defines the access controls for bus master 3 in Supervisor mode.
+ *
+ * Values:
+ * - 0b00 - r/w/x; read, write and execute allowed
+ * - 0b01 - r/x; read and execute allowed, but no write
+ * - 0b10 - r/w; read and write allowed, but no execute
+ * - 0b11 - Same as User mode defined in M3UM
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3SM field. */
+#define MPU_RD_RGDAAC_M3SM(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3SM_MASK) >> MPU_RGDAAC_M3SM_SHIFT)
+#define MPU_BRD_RGDAAC_M3SM(base, index) (MPU_RD_RGDAAC_M3SM(base, index))
+
+/*! @brief Set the M3SM field to a new value. */
+#define MPU_WR_RGDAAC_M3SM(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3SM_MASK, MPU_RGDAAC_M3SM(value)))
+#define MPU_BWR_RGDAAC_M3SM(base, index, value) (MPU_WR_RGDAAC_M3SM(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M3PE[23] (RW)
+ *
+ * Values:
+ * - 0b0 - Do not include the process identifier in the evaluation
+ * - 0b1 - Include the process identifier and mask (RGDn.RGDAAC) in the region
+ *     hit evaluation
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M3PE field. */
+#define MPU_RD_RGDAAC_M3PE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M3PE_MASK) >> MPU_RGDAAC_M3PE_SHIFT)
+#define MPU_BRD_RGDAAC_M3PE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M3PE_SHIFT))
+
+/*! @brief Set the M3PE field to a new value. */
+#define MPU_WR_RGDAAC_M3PE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M3PE_MASK, MPU_RGDAAC_M3PE(value)))
+#define MPU_BWR_RGDAAC_M3PE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M3PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M4WE[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 4 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M4WE field. */
+#define MPU_RD_RGDAAC_M4WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M4WE_MASK) >> MPU_RGDAAC_M4WE_SHIFT)
+#define MPU_BRD_RGDAAC_M4WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4WE_SHIFT))
+
+/*! @brief Set the M4WE field to a new value. */
+#define MPU_WR_RGDAAC_M4WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M4WE_MASK, MPU_RGDAAC_M4WE(value)))
+#define MPU_BWR_RGDAAC_M4WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M4RE[25] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 4 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 4 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M4RE field. */
+#define MPU_RD_RGDAAC_M4RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M4RE_MASK) >> MPU_RGDAAC_M4RE_SHIFT)
+#define MPU_BRD_RGDAAC_M4RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4RE_SHIFT))
+
+/*! @brief Set the M4RE field to a new value. */
+#define MPU_WR_RGDAAC_M4RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M4RE_MASK, MPU_RGDAAC_M4RE(value)))
+#define MPU_BWR_RGDAAC_M4RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M4RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M5WE[26] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 5 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M5WE field. */
+#define MPU_RD_RGDAAC_M5WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M5WE_MASK) >> MPU_RGDAAC_M5WE_SHIFT)
+#define MPU_BRD_RGDAAC_M5WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5WE_SHIFT))
+
+/*! @brief Set the M5WE field to a new value. */
+#define MPU_WR_RGDAAC_M5WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M5WE_MASK, MPU_RGDAAC_M5WE(value)))
+#define MPU_BWR_RGDAAC_M5WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M5RE[27] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 5 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 5 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M5RE field. */
+#define MPU_RD_RGDAAC_M5RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M5RE_MASK) >> MPU_RGDAAC_M5RE_SHIFT)
+#define MPU_BRD_RGDAAC_M5RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5RE_SHIFT))
+
+/*! @brief Set the M5RE field to a new value. */
+#define MPU_WR_RGDAAC_M5RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M5RE_MASK, MPU_RGDAAC_M5RE(value)))
+#define MPU_BWR_RGDAAC_M5RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M5RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M6WE[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 6 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M6WE field. */
+#define MPU_RD_RGDAAC_M6WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M6WE_MASK) >> MPU_RGDAAC_M6WE_SHIFT)
+#define MPU_BRD_RGDAAC_M6WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6WE_SHIFT))
+
+/*! @brief Set the M6WE field to a new value. */
+#define MPU_WR_RGDAAC_M6WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M6WE_MASK, MPU_RGDAAC_M6WE(value)))
+#define MPU_BWR_RGDAAC_M6WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M6RE[29] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 6 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 6 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M6RE field. */
+#define MPU_RD_RGDAAC_M6RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M6RE_MASK) >> MPU_RGDAAC_M6RE_SHIFT)
+#define MPU_BRD_RGDAAC_M6RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6RE_SHIFT))
+
+/*! @brief Set the M6RE field to a new value. */
+#define MPU_WR_RGDAAC_M6RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M6RE_MASK, MPU_RGDAAC_M6RE(value)))
+#define MPU_BWR_RGDAAC_M6RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M6RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M7WE[30] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 writes terminate with an access error and the write is
+ *     not performed
+ * - 0b1 - Bus master 7 writes allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M7WE field. */
+#define MPU_RD_RGDAAC_M7WE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M7WE_MASK) >> MPU_RGDAAC_M7WE_SHIFT)
+#define MPU_BRD_RGDAAC_M7WE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7WE_SHIFT))
+
+/*! @brief Set the M7WE field to a new value. */
+#define MPU_WR_RGDAAC_M7WE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M7WE_MASK, MPU_RGDAAC_M7WE(value)))
+#define MPU_BWR_RGDAAC_M7WE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7WE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register MPU_RGDAAC, field M7RE[31] (RW)
+ *
+ * Values:
+ * - 0b0 - Bus master 7 reads terminate with an access error and the read is not
+ *     performed
+ * - 0b1 - Bus master 7 reads allowed
+ */
+/*@{*/
+/*! @brief Read current value of the MPU_RGDAAC_M7RE field. */
+#define MPU_RD_RGDAAC_M7RE(base, index) ((MPU_RGDAAC_REG(base, index) & MPU_RGDAAC_M7RE_MASK) >> MPU_RGDAAC_M7RE_SHIFT)
+#define MPU_BRD_RGDAAC_M7RE(base, index) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7RE_SHIFT))
+
+/*! @brief Set the M7RE field to a new value. */
+#define MPU_WR_RGDAAC_M7RE(base, index, value) (MPU_RMW_RGDAAC(base, index, MPU_RGDAAC_M7RE_MASK, MPU_RGDAAC_M7RE(value)))
+#define MPU_BWR_RGDAAC_M7RE(base, index, value) (BITBAND_ACCESS32(&MPU_RGDAAC_REG(base, index), MPU_RGDAAC_M7RE_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 NV
+ *
+ * Flash configuration field
+ *
+ * Registers defined in this header file:
+ * - NV_BACKKEY3 - Backdoor Comparison Key 3.
+ * - NV_BACKKEY2 - Backdoor Comparison Key 2.
+ * - NV_BACKKEY1 - Backdoor Comparison Key 1.
+ * - NV_BACKKEY0 - Backdoor Comparison Key 0.
+ * - NV_BACKKEY7 - Backdoor Comparison Key 7.
+ * - NV_BACKKEY6 - Backdoor Comparison Key 6.
+ * - NV_BACKKEY5 - Backdoor Comparison Key 5.
+ * - NV_BACKKEY4 - Backdoor Comparison Key 4.
+ * - NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ * - NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ * - NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ * - NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ * - NV_FSEC - Non-volatile Flash Security Register
+ * - NV_FOPT - Non-volatile Flash Option Register
+ * - NV_FEPROT - Non-volatile EERAM Protection Register
+ * - NV_FDPROT - Non-volatile D-Flash Protection Register
+ */
+
+#define NV_INSTANCE_COUNT (1U) /*!< Number of instances of the NV module. */
+#define FTFE_FlashConfig_IDX (0U) /*!< Instance number for FTFE_FlashConfig. */
+
+/*******************************************************************************
+ * NV_BACKKEY3 - Backdoor Comparison Key 3.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY3 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY3(base)     (NV_BACKKEY3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY2 - Backdoor Comparison Key 2.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY2 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY2(base)     (NV_BACKKEY2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY1 - Backdoor Comparison Key 1.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY1 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY1(base)     (NV_BACKKEY1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY0 - Backdoor Comparison Key 0.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY0 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY0(base)     (NV_BACKKEY0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY7 - Backdoor Comparison Key 7.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY7 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY7(base)     (NV_BACKKEY7_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY6 - Backdoor Comparison Key 6.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY6 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY6(base)     (NV_BACKKEY6_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY5 - Backdoor Comparison Key 5.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY5 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY5(base)     (NV_BACKKEY5_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_BACKKEY4 - Backdoor Comparison Key 4.
+ ******************************************************************************/
+
+/*!
+ * @brief NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_BACKKEY4 register
+ */
+/*@{*/
+#define NV_RD_BACKKEY4(base)     (NV_BACKKEY4_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT3 register
+ */
+/*@{*/
+#define NV_RD_FPROT3(base)       (NV_FPROT3_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT2 register
+ */
+/*@{*/
+#define NV_RD_FPROT2(base)       (NV_FPROT2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT1 register
+ */
+/*@{*/
+#define NV_RD_FPROT1(base)       (NV_FPROT1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FPROT0 register
+ */
+/*@{*/
+#define NV_RD_FPROT0(base)       (NV_FPROT0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FSEC - Non-volatile Flash Security Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FSEC - Non-volatile Flash Security Register (RO)
+ *
+ * Reset value: 0xFFU
+ *
+ * Allows the user to customize the operation of the MCU at boot time
+ */
+/*!
+ * @name Constants and macros for entire NV_FSEC register
+ */
+/*@{*/
+#define NV_RD_FSEC(base)         (NV_FSEC_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FSEC bitfields
+ */
+
+/*!
+ * @name Register NV_FSEC, field SEC[1:0] (RO)
+ *
+ * Values:
+ * - 0b10 - MCU security status is unsecure
+ * - 0b11 - MCU security status is secure
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_SEC field. */
+#define NV_RD_FSEC_SEC(base) ((NV_FSEC_REG(base) & NV_FSEC_SEC_MASK) >> NV_FSEC_SEC_SHIFT)
+#define NV_BRD_FSEC_SEC(base) (NV_RD_FSEC_SEC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field FSLACC[3:2] (RO)
+ *
+ * Values:
+ * - 0b10 - Freescale factory access denied
+ * - 0b11 - Freescale factory access granted
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_FSLACC field. */
+#define NV_RD_FSEC_FSLACC(base) ((NV_FSEC_REG(base) & NV_FSEC_FSLACC_MASK) >> NV_FSEC_FSLACC_SHIFT)
+#define NV_BRD_FSEC_FSLACC(base) (NV_RD_FSEC_FSLACC(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field MEEN[5:4] (RO)
+ *
+ * Values:
+ * - 0b10 - Mass erase is disabled
+ * - 0b11 - Mass erase is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_MEEN field. */
+#define NV_RD_FSEC_MEEN(base) ((NV_FSEC_REG(base) & NV_FSEC_MEEN_MASK) >> NV_FSEC_MEEN_SHIFT)
+#define NV_BRD_FSEC_MEEN(base) (NV_RD_FSEC_MEEN(base))
+/*@}*/
+
+/*!
+ * @name Register NV_FSEC, field KEYEN[7:6] (RO)
+ *
+ * Values:
+ * - 0b10 - Backdoor key access enabled
+ * - 0b11 - Backdoor key access disabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FSEC_KEYEN field. */
+#define NV_RD_FSEC_KEYEN(base) ((NV_FSEC_REG(base) & NV_FSEC_KEYEN_MASK) >> NV_FSEC_KEYEN_SHIFT)
+#define NV_BRD_FSEC_KEYEN(base) (NV_RD_FSEC_KEYEN(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FOPT - Non-volatile Flash Option Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FOPT - Non-volatile Flash Option Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FOPT register
+ */
+/*@{*/
+#define NV_RD_FOPT(base)         (NV_FOPT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual NV_FOPT bitfields
+ */
+
+/*!
+ * @name Register NV_FOPT, field LPBOOT[0] (RO)
+ *
+ * Values:
+ * - 0b0 - Low-power boot
+ * - 0b1 - Normal boot
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_LPBOOT field. */
+#define NV_RD_FOPT_LPBOOT(base) ((NV_FOPT_REG(base) & NV_FOPT_LPBOOT_MASK) >> NV_FOPT_LPBOOT_SHIFT)
+#define NV_BRD_FOPT_LPBOOT(base) (BITBAND_ACCESS8(&NV_FOPT_REG(base), NV_FOPT_LPBOOT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register NV_FOPT, field EZPORT_DIS[1] (RO)
+ *
+ * Values:
+ * - 0b0 - EzPort operation is disabled
+ * - 0b1 - EzPort operation is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the NV_FOPT_EZPORT_DIS field. */
+#define NV_RD_FOPT_EZPORT_DIS(base) ((NV_FOPT_REG(base) & NV_FOPT_EZPORT_DIS_MASK) >> NV_FOPT_EZPORT_DIS_SHIFT)
+#define NV_BRD_FOPT_EZPORT_DIS(base) (BITBAND_ACCESS8(&NV_FOPT_REG(base), NV_FOPT_EZPORT_DIS_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FEPROT - Non-volatile EERAM Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FEPROT - Non-volatile EERAM Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FEPROT register
+ */
+/*@{*/
+#define NV_RD_FEPROT(base)       (NV_FEPROT_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * NV_FDPROT - Non-volatile D-Flash Protection Register
+ ******************************************************************************/
+
+/*!
+ * @brief NV_FDPROT - Non-volatile D-Flash Protection Register (RO)
+ *
+ * Reset value: 0xFFU
+ */
+/*!
+ * @name Constants and macros for entire NV_FDPROT register
+ */
+/*@{*/
+#define NV_RD_FDPROT(base)       (NV_FDPROT_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 OSC
+ *
+ * Oscillator
+ *
+ * Registers defined in this header file:
+ * - OSC_CR - OSC Control Register
+ */
+
+#define OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */
+#define OSC_IDX (0U) /*!< Instance number for OSC. */
+
+/*******************************************************************************
+ * OSC_CR - OSC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief OSC_CR - OSC Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * After OSC is enabled and starts generating the clocks, the configurations
+ * such as low power and frequency range, must not be changed.
+ */
+/*!
+ * @name Constants and macros for entire OSC_CR register
+ */
+/*@{*/
+#define OSC_RD_CR(base)          (OSC_CR_REG(base))
+#define OSC_WR_CR(base, value)   (OSC_CR_REG(base) = (value))
+#define OSC_RMW_CR(base, mask, value) (OSC_WR_CR(base, (OSC_RD_CR(base) & ~(mask)) | (value)))
+#define OSC_SET_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) |  (value)))
+#define OSC_CLR_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) & ~(value)))
+#define OSC_TOG_CR(base, value)  (OSC_WR_CR(base, OSC_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual OSC_CR bitfields
+ */
+
+/*!
+ * @name Register OSC_CR, field SC16P[0] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 16 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC16P field. */
+#define OSC_RD_CR_SC16P(base) ((OSC_CR_REG(base) & OSC_CR_SC16P_MASK) >> OSC_CR_SC16P_SHIFT)
+#define OSC_BRD_CR_SC16P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT))
+
+/*! @brief Set the SC16P field to a new value. */
+#define OSC_WR_CR_SC16P(base, value) (OSC_RMW_CR(base, OSC_CR_SC16P_MASK, OSC_CR_SC16P(value)))
+#define OSC_BWR_CR_SC16P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC16P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC8P[1] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 8 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC8P field. */
+#define OSC_RD_CR_SC8P(base) ((OSC_CR_REG(base) & OSC_CR_SC8P_MASK) >> OSC_CR_SC8P_SHIFT)
+#define OSC_BRD_CR_SC8P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT))
+
+/*! @brief Set the SC8P field to a new value. */
+#define OSC_WR_CR_SC8P(base, value) (OSC_RMW_CR(base, OSC_CR_SC8P_MASK, OSC_CR_SC8P(value)))
+#define OSC_BWR_CR_SC8P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC8P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC4P[2] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 4 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC4P field. */
+#define OSC_RD_CR_SC4P(base) ((OSC_CR_REG(base) & OSC_CR_SC4P_MASK) >> OSC_CR_SC4P_SHIFT)
+#define OSC_BRD_CR_SC4P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT))
+
+/*! @brief Set the SC4P field to a new value. */
+#define OSC_WR_CR_SC4P(base, value) (OSC_RMW_CR(base, OSC_CR_SC4P_MASK, OSC_CR_SC4P(value)))
+#define OSC_BWR_CR_SC4P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC4P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field SC2P[3] (RW)
+ *
+ * Configures the oscillator load.
+ *
+ * Values:
+ * - 0b0 - Disable the selection.
+ * - 0b1 - Add 2 pF capacitor to the oscillator load.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_SC2P field. */
+#define OSC_RD_CR_SC2P(base) ((OSC_CR_REG(base) & OSC_CR_SC2P_MASK) >> OSC_CR_SC2P_SHIFT)
+#define OSC_BRD_CR_SC2P(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT))
+
+/*! @brief Set the SC2P field to a new value. */
+#define OSC_WR_CR_SC2P(base, value) (OSC_RMW_CR(base, OSC_CR_SC2P_MASK, OSC_CR_SC2P(value)))
+#define OSC_BWR_CR_SC2P(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_SC2P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field EREFSTEN[5] (RW)
+ *
+ * Controls whether or not the external reference clock (OSCERCLK) remains
+ * enabled when MCU enters Stop mode.
+ *
+ * Values:
+ * - 0b0 - External reference clock is disabled in Stop mode.
+ * - 0b1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
+ *     before entering Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_EREFSTEN field. */
+#define OSC_RD_CR_EREFSTEN(base) ((OSC_CR_REG(base) & OSC_CR_EREFSTEN_MASK) >> OSC_CR_EREFSTEN_SHIFT)
+#define OSC_BRD_CR_EREFSTEN(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT))
+
+/*! @brief Set the EREFSTEN field to a new value. */
+#define OSC_WR_CR_EREFSTEN(base, value) (OSC_RMW_CR(base, OSC_CR_EREFSTEN_MASK, OSC_CR_EREFSTEN(value)))
+#define OSC_BWR_CR_EREFSTEN(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_EREFSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register OSC_CR, field ERCLKEN[7] (RW)
+ *
+ * Enables external reference clock (OSCERCLK).
+ *
+ * Values:
+ * - 0b0 - External reference clock is inactive.
+ * - 0b1 - External reference clock is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the OSC_CR_ERCLKEN field. */
+#define OSC_RD_CR_ERCLKEN(base) ((OSC_CR_REG(base) & OSC_CR_ERCLKEN_MASK) >> OSC_CR_ERCLKEN_SHIFT)
+#define OSC_BRD_CR_ERCLKEN(base) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT))
+
+/*! @brief Set the ERCLKEN field to a new value. */
+#define OSC_WR_CR_ERCLKEN(base, value) (OSC_RMW_CR(base, OSC_CR_ERCLKEN_MASK, OSC_CR_ERCLKEN(value)))
+#define OSC_BWR_CR_ERCLKEN(base, value) (BITBAND_ACCESS8(&OSC_CR_REG(base), OSC_CR_ERCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PDB
+ *
+ * Programmable Delay Block
+ *
+ * Registers defined in this header file:
+ * - PDB_SC - Status and Control register
+ * - PDB_MOD - Modulus register
+ * - PDB_CNT - Counter register
+ * - PDB_IDLY - Interrupt Delay register
+ * - PDB_C1 - Channel n Control register 1
+ * - PDB_S - Channel n Status register
+ * - PDB_DLY - Channel n Delay 0 register
+ * - PDB_INTC - DAC Interval Trigger n Control register
+ * - PDB_INT - DAC Interval n register
+ * - PDB_POEN - Pulse-Out n Enable register
+ * - PDB_PODLY - Pulse-Out n Delay register
+ */
+
+#define PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */
+#define PDB0_IDX (0U) /*!< Instance number for PDB0. */
+
+/*******************************************************************************
+ * PDB_SC - Status and Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_SC - Status and Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_SC register
+ */
+/*@{*/
+#define PDB_RD_SC(base)          (PDB_SC_REG(base))
+#define PDB_WR_SC(base, value)   (PDB_SC_REG(base) = (value))
+#define PDB_RMW_SC(base, mask, value) (PDB_WR_SC(base, (PDB_RD_SC(base) & ~(mask)) | (value)))
+#define PDB_SET_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) |  (value)))
+#define PDB_CLR_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) & ~(value)))
+#define PDB_TOG_SC(base, value)  (PDB_WR_SC(base, PDB_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_SC bitfields
+ */
+
+/*!
+ * @name Register PDB_SC, field LDOK[0] (RW)
+ *
+ * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
+ * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
+ * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
+ * written to the LDOK field, the values in the buffers of above registers are
+ * not effective and the buffers cannot be written until the values in buffers are
+ * loaded into their internal registers. LDOK can be written only when PDBEN is
+ * set or it can be written at the same time with PDBEN being written to 1. It is
+ * automatically cleared when the values in buffers are loaded into the internal
+ * registers or the PDBEN is cleared. Writing 0 to it has no effect.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_LDOK field. */
+#define PDB_RD_SC_LDOK(base) ((PDB_SC_REG(base) & PDB_SC_LDOK_MASK) >> PDB_SC_LDOK_SHIFT)
+#define PDB_BRD_SC_LDOK(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_LDOK_SHIFT))
+
+/*! @brief Set the LDOK field to a new value. */
+#define PDB_WR_SC_LDOK(base, value) (PDB_RMW_SC(base, PDB_SC_LDOK_MASK, PDB_SC_LDOK(value)))
+#define PDB_BWR_SC_LDOK(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_LDOK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field CONT[1] (RW)
+ *
+ * Enables the PDB operation in Continuous mode.
+ *
+ * Values:
+ * - 0b0 - PDB operation in One-Shot mode
+ * - 0b1 - PDB operation in Continuous mode
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_CONT field. */
+#define PDB_RD_SC_CONT(base) ((PDB_SC_REG(base) & PDB_SC_CONT_MASK) >> PDB_SC_CONT_SHIFT)
+#define PDB_BRD_SC_CONT(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_CONT_SHIFT))
+
+/*! @brief Set the CONT field to a new value. */
+#define PDB_WR_SC_CONT(base, value) (PDB_RMW_SC(base, PDB_SC_CONT_MASK, PDB_SC_CONT(value)))
+#define PDB_BWR_SC_CONT(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_CONT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field MULT[3:2] (RW)
+ *
+ * Selects the multiplication factor of the prescaler divider for the counter
+ * clock.
+ *
+ * Values:
+ * - 0b00 - Multiplication factor is 1.
+ * - 0b01 - Multiplication factor is 10.
+ * - 0b10 - Multiplication factor is 20.
+ * - 0b11 - Multiplication factor is 40.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_MULT field. */
+#define PDB_RD_SC_MULT(base) ((PDB_SC_REG(base) & PDB_SC_MULT_MASK) >> PDB_SC_MULT_SHIFT)
+#define PDB_BRD_SC_MULT(base) (PDB_RD_SC_MULT(base))
+
+/*! @brief Set the MULT field to a new value. */
+#define PDB_WR_SC_MULT(base, value) (PDB_RMW_SC(base, PDB_SC_MULT_MASK, PDB_SC_MULT(value)))
+#define PDB_BWR_SC_MULT(base, value) (PDB_WR_SC_MULT(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBIE[5] (RW)
+ *
+ * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
+ * generates a PDB interrupt.
+ *
+ * Values:
+ * - 0b0 - PDB interrupt disabled.
+ * - 0b1 - PDB interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBIE field. */
+#define PDB_RD_SC_PDBIE(base) ((PDB_SC_REG(base) & PDB_SC_PDBIE_MASK) >> PDB_SC_PDBIE_SHIFT)
+#define PDB_BRD_SC_PDBIE(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIE_SHIFT))
+
+/*! @brief Set the PDBIE field to a new value. */
+#define PDB_WR_SC_PDBIE(base, value) (PDB_RMW_SC(base, PDB_SC_PDBIE_MASK, PDB_SC_PDBIE(value)))
+#define PDB_BWR_SC_PDBIE(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBIF[6] (RW)
+ *
+ * This field is set when the counter value is equal to the IDLY register.
+ * Writing zero clears this field.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBIF field. */
+#define PDB_RD_SC_PDBIF(base) ((PDB_SC_REG(base) & PDB_SC_PDBIF_MASK) >> PDB_SC_PDBIF_SHIFT)
+#define PDB_BRD_SC_PDBIF(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIF_SHIFT))
+
+/*! @brief Set the PDBIF field to a new value. */
+#define PDB_WR_SC_PDBIF(base, value) (PDB_RMW_SC(base, PDB_SC_PDBIF_MASK, PDB_SC_PDBIF(value)))
+#define PDB_BWR_SC_PDBIF(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - PDB disabled. Counter is off.
+ * - 0b1 - PDB enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBEN field. */
+#define PDB_RD_SC_PDBEN(base) ((PDB_SC_REG(base) & PDB_SC_PDBEN_MASK) >> PDB_SC_PDBEN_SHIFT)
+#define PDB_BRD_SC_PDBEN(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEN_SHIFT))
+
+/*! @brief Set the PDBEN field to a new value. */
+#define PDB_WR_SC_PDBEN(base, value) (PDB_RMW_SC(base, PDB_SC_PDBEN_MASK, PDB_SC_PDBEN(value)))
+#define PDB_BWR_SC_PDBEN(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field TRGSEL[11:8] (RW)
+ *
+ * Selects the trigger input source for the PDB. The trigger input source can be
+ * internal or external (EXTRG pin), or the software trigger. Refer to chip
+ * configuration details for the actual PDB input trigger connections.
+ *
+ * Values:
+ * - 0b0000 - Trigger-In 0 is selected.
+ * - 0b0001 - Trigger-In 1 is selected.
+ * - 0b0010 - Trigger-In 2 is selected.
+ * - 0b0011 - Trigger-In 3 is selected.
+ * - 0b0100 - Trigger-In 4 is selected.
+ * - 0b0101 - Trigger-In 5 is selected.
+ * - 0b0110 - Trigger-In 6 is selected.
+ * - 0b0111 - Trigger-In 7 is selected.
+ * - 0b1000 - Trigger-In 8 is selected.
+ * - 0b1001 - Trigger-In 9 is selected.
+ * - 0b1010 - Trigger-In 10 is selected.
+ * - 0b1011 - Trigger-In 11 is selected.
+ * - 0b1100 - Trigger-In 12 is selected.
+ * - 0b1101 - Trigger-In 13 is selected.
+ * - 0b1110 - Trigger-In 14 is selected.
+ * - 0b1111 - Software trigger is selected.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_TRGSEL field. */
+#define PDB_RD_SC_TRGSEL(base) ((PDB_SC_REG(base) & PDB_SC_TRGSEL_MASK) >> PDB_SC_TRGSEL_SHIFT)
+#define PDB_BRD_SC_TRGSEL(base) (PDB_RD_SC_TRGSEL(base))
+
+/*! @brief Set the TRGSEL field to a new value. */
+#define PDB_WR_SC_TRGSEL(base, value) (PDB_RMW_SC(base, PDB_SC_TRGSEL_MASK, PDB_SC_TRGSEL(value)))
+#define PDB_BWR_SC_TRGSEL(base, value) (PDB_WR_SC_TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PRESCALER[14:12] (RW)
+ *
+ * Values:
+ * - 0b000 - Counting uses the peripheral clock divided by multiplication factor
+ *     selected by MULT.
+ * - 0b001 - Counting uses the peripheral clock divided by twice of the
+ *     multiplication factor selected by MULT.
+ * - 0b010 - Counting uses the peripheral clock divided by four times of the
+ *     multiplication factor selected by MULT.
+ * - 0b011 - Counting uses the peripheral clock divided by eight times of the
+ *     multiplication factor selected by MULT.
+ * - 0b100 - Counting uses the peripheral clock divided by 16 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b101 - Counting uses the peripheral clock divided by 32 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b110 - Counting uses the peripheral clock divided by 64 times of the
+ *     multiplication factor selected by MULT.
+ * - 0b111 - Counting uses the peripheral clock divided by 128 times of the
+ *     multiplication factor selected by MULT.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PRESCALER field. */
+#define PDB_RD_SC_PRESCALER(base) ((PDB_SC_REG(base) & PDB_SC_PRESCALER_MASK) >> PDB_SC_PRESCALER_SHIFT)
+#define PDB_BRD_SC_PRESCALER(base) (PDB_RD_SC_PRESCALER(base))
+
+/*! @brief Set the PRESCALER field to a new value. */
+#define PDB_WR_SC_PRESCALER(base, value) (PDB_RMW_SC(base, PDB_SC_PRESCALER_MASK, PDB_SC_PRESCALER(value)))
+#define PDB_BWR_SC_PRESCALER(base, value) (PDB_WR_SC_PRESCALER(base, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field DMAEN[15] (RW)
+ *
+ * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
+ * interrupt.
+ *
+ * Values:
+ * - 0b0 - DMA disabled.
+ * - 0b1 - DMA enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_DMAEN field. */
+#define PDB_RD_SC_DMAEN(base) ((PDB_SC_REG(base) & PDB_SC_DMAEN_MASK) >> PDB_SC_DMAEN_SHIFT)
+#define PDB_BRD_SC_DMAEN(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define PDB_WR_SC_DMAEN(base, value) (PDB_RMW_SC(base, PDB_SC_DMAEN_MASK, PDB_SC_DMAEN(value)))
+#define PDB_BWR_SC_DMAEN(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field SWTRIG[16] (WORZ)
+ *
+ * When PDB is enabled and the software trigger is selected as the trigger input
+ * source, writing 1 to this field resets and restarts the counter. Writing 0 to
+ * this field has no effect. Reading this field results 0.
+ */
+/*@{*/
+/*! @brief Set the SWTRIG field to a new value. */
+#define PDB_WR_SC_SWTRIG(base, value) (PDB_RMW_SC(base, PDB_SC_SWTRIG_MASK, PDB_SC_SWTRIG(value)))
+#define PDB_BWR_SC_SWTRIG(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_SWTRIG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field PDBEIE[17] (RW)
+ *
+ * Enables the PDB sequence error interrupt. When this field is set, any of the
+ * PDB channel sequence error flags generates a PDB sequence error interrupt.
+ *
+ * Values:
+ * - 0b0 - PDB sequence error interrupt disabled.
+ * - 0b1 - PDB sequence error interrupt enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_PDBEIE field. */
+#define PDB_RD_SC_PDBEIE(base) ((PDB_SC_REG(base) & PDB_SC_PDBEIE_MASK) >> PDB_SC_PDBEIE_SHIFT)
+#define PDB_BRD_SC_PDBEIE(base) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEIE_SHIFT))
+
+/*! @brief Set the PDBEIE field to a new value. */
+#define PDB_WR_SC_PDBEIE(base, value) (PDB_RMW_SC(base, PDB_SC_PDBEIE_MASK, PDB_SC_PDBEIE(value)))
+#define PDB_BWR_SC_PDBEIE(base, value) (BITBAND_ACCESS32(&PDB_SC_REG(base), PDB_SC_PDBEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_SC, field LDMOD[19:18] (RW)
+ *
+ * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
+ * after 1 is written to LDOK.
+ *
+ * Values:
+ * - 0b00 - The internal registers are loaded with the values from their buffers
+ *     immediately after 1 is written to LDOK.
+ * - 0b01 - The internal registers are loaded with the values from their buffers
+ *     when the PDB counter reaches the MOD register value after 1 is written to
+ *     LDOK.
+ * - 0b10 - The internal registers are loaded with the values from their buffers
+ *     when a trigger input event is detected after 1 is written to LDOK.
+ * - 0b11 - The internal registers are loaded with the values from their buffers
+ *     when either the PDB counter reaches the MOD register value or a trigger
+ *     input event is detected, after 1 is written to LDOK.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_SC_LDMOD field. */
+#define PDB_RD_SC_LDMOD(base) ((PDB_SC_REG(base) & PDB_SC_LDMOD_MASK) >> PDB_SC_LDMOD_SHIFT)
+#define PDB_BRD_SC_LDMOD(base) (PDB_RD_SC_LDMOD(base))
+
+/*! @brief Set the LDMOD field to a new value. */
+#define PDB_WR_SC_LDMOD(base, value) (PDB_RMW_SC(base, PDB_SC_LDMOD_MASK, PDB_SC_LDMOD(value)))
+#define PDB_BWR_SC_LDMOD(base, value) (PDB_WR_SC_LDMOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_MOD - Modulus register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_MOD - Modulus register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+/*!
+ * @name Constants and macros for entire PDB_MOD register
+ */
+/*@{*/
+#define PDB_RD_MOD(base)         (PDB_MOD_REG(base))
+#define PDB_WR_MOD(base, value)  (PDB_MOD_REG(base) = (value))
+#define PDB_RMW_MOD(base, mask, value) (PDB_WR_MOD(base, (PDB_RD_MOD(base) & ~(mask)) | (value)))
+#define PDB_SET_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) |  (value)))
+#define PDB_CLR_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) & ~(value)))
+#define PDB_TOG_MOD(base, value) (PDB_WR_MOD(base, PDB_RD_MOD(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_MOD bitfields
+ */
+
+/*!
+ * @name Register PDB_MOD, field MOD[15:0] (RW)
+ *
+ * Specifies the period of the counter. When the counter reaches this value, it
+ * will be reset back to zero. If the PDB is in Continuous mode, the count begins
+ * anew. Reading this field returns the value of the internal register that is
+ * effective for the current cycle of PDB.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_MOD_MOD field. */
+#define PDB_RD_MOD_MOD(base) ((PDB_MOD_REG(base) & PDB_MOD_MOD_MASK) >> PDB_MOD_MOD_SHIFT)
+#define PDB_BRD_MOD_MOD(base) (PDB_RD_MOD_MOD(base))
+
+/*! @brief Set the MOD field to a new value. */
+#define PDB_WR_MOD_MOD(base, value) (PDB_RMW_MOD(base, PDB_MOD_MOD_MASK, PDB_MOD_MOD(value)))
+#define PDB_BWR_MOD_MOD(base, value) (PDB_WR_MOD_MOD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_CNT - Counter register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_CNT - Counter register (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_CNT register
+ */
+/*@{*/
+#define PDB_RD_CNT(base)         (PDB_CNT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_CNT bitfields
+ */
+
+/*!
+ * @name Register PDB_CNT, field CNT[15:0] (RO)
+ *
+ * Contains the current value of the counter.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_CNT_CNT field. */
+#define PDB_RD_CNT_CNT(base) ((PDB_CNT_REG(base) & PDB_CNT_CNT_MASK) >> PDB_CNT_CNT_SHIFT)
+#define PDB_BRD_CNT_CNT(base) (PDB_RD_CNT_CNT(base))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_IDLY - Interrupt Delay register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_IDLY - Interrupt Delay register (RW)
+ *
+ * Reset value: 0x0000FFFFU
+ */
+/*!
+ * @name Constants and macros for entire PDB_IDLY register
+ */
+/*@{*/
+#define PDB_RD_IDLY(base)        (PDB_IDLY_REG(base))
+#define PDB_WR_IDLY(base, value) (PDB_IDLY_REG(base) = (value))
+#define PDB_RMW_IDLY(base, mask, value) (PDB_WR_IDLY(base, (PDB_RD_IDLY(base) & ~(mask)) | (value)))
+#define PDB_SET_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) |  (value)))
+#define PDB_CLR_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) & ~(value)))
+#define PDB_TOG_IDLY(base, value) (PDB_WR_IDLY(base, PDB_RD_IDLY(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_IDLY bitfields
+ */
+
+/*!
+ * @name Register PDB_IDLY, field IDLY[15:0] (RW)
+ *
+ * Specifies the delay value to schedule the PDB interrupt. It can be used to
+ * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
+ * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
+ * this field returns the value of internal register that is effective for the
+ * current cycle of the PDB.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_IDLY_IDLY field. */
+#define PDB_RD_IDLY_IDLY(base) ((PDB_IDLY_REG(base) & PDB_IDLY_IDLY_MASK) >> PDB_IDLY_IDLY_SHIFT)
+#define PDB_BRD_IDLY_IDLY(base) (PDB_RD_IDLY_IDLY(base))
+
+/*! @brief Set the IDLY field to a new value. */
+#define PDB_WR_IDLY_IDLY(base, value) (PDB_RMW_IDLY(base, PDB_IDLY_IDLY_MASK, PDB_IDLY_IDLY(value)))
+#define PDB_BWR_IDLY_IDLY(base, value) (PDB_WR_IDLY_IDLY(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_C1 - Channel n Control register 1
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_C1 - Channel n Control register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each PDB channel has one control register, CHnC1. The bits in this register
+ * control the functionality of each PDB channel operation.
+ */
+/*!
+ * @name Constants and macros for entire PDB_C1 register
+ */
+/*@{*/
+#define PDB_RD_C1(base, index)   (PDB_C1_REG(base, index))
+#define PDB_WR_C1(base, index, value) (PDB_C1_REG(base, index) = (value))
+#define PDB_RMW_C1(base, index, mask, value) (PDB_WR_C1(base, index, (PDB_RD_C1(base, index) & ~(mask)) | (value)))
+#define PDB_SET_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) |  (value)))
+#define PDB_CLR_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) & ~(value)))
+#define PDB_TOG_C1(base, index, value) (PDB_WR_C1(base, index, PDB_RD_C1(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_C1 bitfields
+ */
+
+/*!
+ * @name Register PDB_C1, field EN[7:0] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
+ * bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger disabled.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_EN field. */
+#define PDB_RD_C1_EN(base, index) ((PDB_C1_REG(base, index) & PDB_C1_EN_MASK) >> PDB_C1_EN_SHIFT)
+#define PDB_BRD_C1_EN(base, index) (PDB_RD_C1_EN(base, index))
+
+/*! @brief Set the EN field to a new value. */
+#define PDB_WR_C1_EN(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_EN_MASK, PDB_C1_EN(value)))
+#define PDB_BWR_C1_EN(base, index, value) (PDB_WR_C1_EN(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_C1, field TOS[15:8] (RW)
+ *
+ * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
+ * implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger is in bypassed mode.
+ *     The pre-trigger asserts one peripheral clock cycle after a rising edge is
+ *     detected on selected trigger input source or software trigger is selected
+ *     and SWTRIG is written with 1.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger asserts when the
+ *     counter reaches the channel delay register and one peripheral clock cycle after
+ *     a rising edge is detected on selected trigger input source or software
+ *     trigger is selected and SETRIG is written with 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_TOS field. */
+#define PDB_RD_C1_TOS(base, index) ((PDB_C1_REG(base, index) & PDB_C1_TOS_MASK) >> PDB_C1_TOS_SHIFT)
+#define PDB_BRD_C1_TOS(base, index) (PDB_RD_C1_TOS(base, index))
+
+/*! @brief Set the TOS field to a new value. */
+#define PDB_WR_C1_TOS(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_TOS_MASK, PDB_C1_TOS(value)))
+#define PDB_BWR_C1_TOS(base, index, value) (PDB_WR_C1_TOS(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_C1, field BB[23:16] (RW)
+ *
+ * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
+ * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
+ * enables the ADC conversions complete to trigger the next PDB channel
+ * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
+ * set of configuration and results registers. Application code must only enable
+ * the back-to-back operation of the PDB pre-triggers at the leading of the
+ * back-to-back connection chain.
+ *
+ * Values:
+ * - 0b00000000 - PDB channel's corresponding pre-trigger back-to-back operation
+ *     disabled.
+ * - 0b00000001 - PDB channel's corresponding pre-trigger back-to-back operation
+ *     enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_C1_BB field. */
+#define PDB_RD_C1_BB(base, index) ((PDB_C1_REG(base, index) & PDB_C1_BB_MASK) >> PDB_C1_BB_SHIFT)
+#define PDB_BRD_C1_BB(base, index) (PDB_RD_C1_BB(base, index))
+
+/*! @brief Set the BB field to a new value. */
+#define PDB_WR_C1_BB(base, index, value) (PDB_RMW_C1(base, index, PDB_C1_BB_MASK, PDB_C1_BB(value)))
+#define PDB_BWR_C1_BB(base, index, value) (PDB_WR_C1_BB(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_S - Channel n Status register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_S - Channel n Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_S register
+ */
+/*@{*/
+#define PDB_RD_S(base, index)    (PDB_S_REG(base, index))
+#define PDB_WR_S(base, index, value) (PDB_S_REG(base, index) = (value))
+#define PDB_RMW_S(base, index, mask, value) (PDB_WR_S(base, index, (PDB_RD_S(base, index) & ~(mask)) | (value)))
+#define PDB_SET_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) |  (value)))
+#define PDB_CLR_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) & ~(value)))
+#define PDB_TOG_S(base, index, value) (PDB_WR_S(base, index, PDB_RD_S(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_S bitfields
+ */
+
+/*!
+ * @name Register PDB_S, field ERR[7:0] (RW)
+ *
+ * Only the lower M bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - Sequence error not detected on PDB channel's corresponding
+ *     pre-trigger.
+ * - 0b00000001 - Sequence error detected on PDB channel's corresponding
+ *     pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from
+ *     PDB channel n. When one conversion, which is triggered by one of the
+ *     pre-triggers from PDB channel n, is in progress, new trigger from PDB
+ *     channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is
+ *     set. Writing 0's to clear the sequence error flags.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_S_ERR field. */
+#define PDB_RD_S_ERR(base, index) ((PDB_S_REG(base, index) & PDB_S_ERR_MASK) >> PDB_S_ERR_SHIFT)
+#define PDB_BRD_S_ERR(base, index) (PDB_RD_S_ERR(base, index))
+
+/*! @brief Set the ERR field to a new value. */
+#define PDB_WR_S_ERR(base, index, value) (PDB_RMW_S(base, index, PDB_S_ERR_MASK, PDB_S_ERR(value)))
+#define PDB_BWR_S_ERR(base, index, value) (PDB_WR_S_ERR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_S, field CF[23:16] (RW)
+ *
+ * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
+ * clear these bits.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_S_CF field. */
+#define PDB_RD_S_CF(base, index) ((PDB_S_REG(base, index) & PDB_S_CF_MASK) >> PDB_S_CF_SHIFT)
+#define PDB_BRD_S_CF(base, index) (PDB_RD_S_CF(base, index))
+
+/*! @brief Set the CF field to a new value. */
+#define PDB_WR_S_CF(base, index, value) (PDB_RMW_S(base, index, PDB_S_CF_MASK, PDB_S_CF(value)))
+#define PDB_BWR_S_CF(base, index, value) (PDB_WR_S_CF(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_DLY - Channel n Delay 0 register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_DLY - Channel n Delay 0 register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_DLY register
+ */
+/*@{*/
+#define PDB_RD_DLY(base, index, index2) (PDB_DLY_REG(base, index, index2))
+#define PDB_WR_DLY(base, index, index2, value) (PDB_DLY_REG(base, index, index2) = (value))
+#define PDB_RMW_DLY(base, index, index2, mask, value) (PDB_WR_DLY(base, index, index2, (PDB_RD_DLY(base, index, index2) & ~(mask)) | (value)))
+#define PDB_SET_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) |  (value)))
+#define PDB_CLR_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) & ~(value)))
+#define PDB_TOG_DLY(base, index, index2, value) (PDB_WR_DLY(base, index, index2, PDB_RD_DLY(base, index, index2) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_DLY bitfields
+ */
+
+/*!
+ * @name Register PDB_DLY, field DLY[15:0] (RW)
+ *
+ * Specifies the delay value for the channel's corresponding pre-trigger. The
+ * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
+ * the value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_DLY_DLY field. */
+#define PDB_RD_DLY_DLY(base, index, index2) ((PDB_DLY_REG(base, index, index2) & PDB_DLY_DLY_MASK) >> PDB_DLY_DLY_SHIFT)
+#define PDB_BRD_DLY_DLY(base, index, index2) (PDB_RD_DLY_DLY(base, index, index2))
+
+/*! @brief Set the DLY field to a new value. */
+#define PDB_WR_DLY_DLY(base, index, index2, value) (PDB_RMW_DLY(base, index, index2, PDB_DLY_DLY_MASK, PDB_DLY_DLY(value)))
+#define PDB_BWR_DLY_DLY(base, index, index2, value) (PDB_WR_DLY_DLY(base, index, index2, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_INTC - DAC Interval Trigger n Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_INTC - DAC Interval Trigger n Control register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_INTC register
+ */
+/*@{*/
+#define PDB_RD_INTC(base, index) (PDB_INTC_REG(base, index))
+#define PDB_WR_INTC(base, index, value) (PDB_INTC_REG(base, index) = (value))
+#define PDB_RMW_INTC(base, index, mask, value) (PDB_WR_INTC(base, index, (PDB_RD_INTC(base, index) & ~(mask)) | (value)))
+#define PDB_SET_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) |  (value)))
+#define PDB_CLR_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) & ~(value)))
+#define PDB_TOG_INTC(base, index, value) (PDB_WR_INTC(base, index, PDB_RD_INTC(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_INTC bitfields
+ */
+
+/*!
+ * @name Register PDB_INTC, field TOE[0] (RW)
+ *
+ * This bit enables the DAC interval trigger.
+ *
+ * Values:
+ * - 0b0 - DAC interval trigger disabled.
+ * - 0b1 - DAC interval trigger enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INTC_TOE field. */
+#define PDB_RD_INTC_TOE(base, index) ((PDB_INTC_REG(base, index) & PDB_INTC_TOE_MASK) >> PDB_INTC_TOE_SHIFT)
+#define PDB_BRD_INTC_TOE(base, index) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_TOE_SHIFT))
+
+/*! @brief Set the TOE field to a new value. */
+#define PDB_WR_INTC_TOE(base, index, value) (PDB_RMW_INTC(base, index, PDB_INTC_TOE_MASK, PDB_INTC_TOE(value)))
+#define PDB_BWR_INTC_TOE(base, index, value) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_TOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PDB_INTC, field EXT[1] (RW)
+ *
+ * Enables the external trigger for DAC interval counter.
+ *
+ * Values:
+ * - 0b0 - DAC external trigger input disabled. DAC interval counter is reset
+ *     and counting starts when a rising edge is detected on selected trigger input
+ *     source or software trigger is selected and SWTRIG is written with 1.
+ * - 0b1 - DAC external trigger input enabled. DAC interval counter is bypassed
+ *     and DAC external trigger input triggers the DAC interval trigger.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INTC_EXT field. */
+#define PDB_RD_INTC_EXT(base, index) ((PDB_INTC_REG(base, index) & PDB_INTC_EXT_MASK) >> PDB_INTC_EXT_SHIFT)
+#define PDB_BRD_INTC_EXT(base, index) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_EXT_SHIFT))
+
+/*! @brief Set the EXT field to a new value. */
+#define PDB_WR_INTC_EXT(base, index, value) (PDB_RMW_INTC(base, index, PDB_INTC_EXT_MASK, PDB_INTC_EXT(value)))
+#define PDB_BWR_INTC_EXT(base, index, value) (BITBAND_ACCESS32(&PDB_INTC_REG(base, index), PDB_INTC_EXT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_INT - DAC Interval n register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_INT - DAC Interval n register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_INT register
+ */
+/*@{*/
+#define PDB_RD_INT(base, index)  (PDB_INT_REG(base, index))
+#define PDB_WR_INT(base, index, value) (PDB_INT_REG(base, index) = (value))
+#define PDB_RMW_INT(base, index, mask, value) (PDB_WR_INT(base, index, (PDB_RD_INT(base, index) & ~(mask)) | (value)))
+#define PDB_SET_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) |  (value)))
+#define PDB_CLR_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) & ~(value)))
+#define PDB_TOG_INT(base, index, value) (PDB_WR_INT(base, index, PDB_RD_INT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_INT bitfields
+ */
+
+/*!
+ * @name Register PDB_INT, field INT[15:0] (RW)
+ *
+ * Specifies the interval value for DAC interval trigger. DAC interval trigger
+ * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
+ * Reading this field returns the value of internal register that is effective
+ * for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_INT_INT field. */
+#define PDB_RD_INT_INT(base, index) ((PDB_INT_REG(base, index) & PDB_INT_INT_MASK) >> PDB_INT_INT_SHIFT)
+#define PDB_BRD_INT_INT(base, index) (PDB_RD_INT_INT(base, index))
+
+/*! @brief Set the INT field to a new value. */
+#define PDB_WR_INT_INT(base, index, value) (PDB_RMW_INT(base, index, PDB_INT_INT_MASK, PDB_INT_INT(value)))
+#define PDB_BWR_INT_INT(base, index, value) (PDB_WR_INT_INT(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_POEN - Pulse-Out n Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_POEN - Pulse-Out n Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_POEN register
+ */
+/*@{*/
+#define PDB_RD_POEN(base)        (PDB_POEN_REG(base))
+#define PDB_WR_POEN(base, value) (PDB_POEN_REG(base) = (value))
+#define PDB_RMW_POEN(base, mask, value) (PDB_WR_POEN(base, (PDB_RD_POEN(base) & ~(mask)) | (value)))
+#define PDB_SET_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) |  (value)))
+#define PDB_CLR_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) & ~(value)))
+#define PDB_TOG_POEN(base, value) (PDB_WR_POEN(base, PDB_RD_POEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_POEN bitfields
+ */
+
+/*!
+ * @name Register PDB_POEN, field POEN[7:0] (RW)
+ *
+ * Enables the pulse output. Only lower Y bits are implemented in this MCU.
+ *
+ * Values:
+ * - 0b00000000 - PDB Pulse-Out disabled
+ * - 0b00000001 - PDB Pulse-Out enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_POEN_POEN field. */
+#define PDB_RD_POEN_POEN(base) ((PDB_POEN_REG(base) & PDB_POEN_POEN_MASK) >> PDB_POEN_POEN_SHIFT)
+#define PDB_BRD_POEN_POEN(base) (PDB_RD_POEN_POEN(base))
+
+/*! @brief Set the POEN field to a new value. */
+#define PDB_WR_POEN_POEN(base, value) (PDB_RMW_POEN(base, PDB_POEN_POEN_MASK, PDB_POEN_POEN(value)))
+#define PDB_BWR_POEN_POEN(base, value) (PDB_WR_POEN_POEN(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PDB_PODLY - Pulse-Out n Delay register
+ ******************************************************************************/
+
+/*!
+ * @brief PDB_PODLY - Pulse-Out n Delay register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire PDB_PODLY register
+ */
+/*@{*/
+#define PDB_RD_PODLY(base, index) (PDB_PODLY_REG(base, index))
+#define PDB_WR_PODLY(base, index, value) (PDB_PODLY_REG(base, index) = (value))
+#define PDB_RMW_PODLY(base, index, mask, value) (PDB_WR_PODLY(base, index, (PDB_RD_PODLY(base, index) & ~(mask)) | (value)))
+#define PDB_SET_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) |  (value)))
+#define PDB_CLR_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) & ~(value)))
+#define PDB_TOG_PODLY(base, index, value) (PDB_WR_PODLY(base, index, PDB_RD_PODLY(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PDB_PODLY bitfields
+ */
+
+/*!
+ * @name Register PDB_PODLY, field DLY2[15:0] (RW)
+ *
+ * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
+ * low when the PDB counter is equal to the DLY2. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_PODLY_DLY2 field. */
+#define PDB_RD_PODLY_DLY2(base, index) ((PDB_PODLY_REG(base, index) & PDB_PODLY_DLY2_MASK) >> PDB_PODLY_DLY2_SHIFT)
+#define PDB_BRD_PODLY_DLY2(base, index) (PDB_RD_PODLY_DLY2(base, index))
+
+/*! @brief Set the DLY2 field to a new value. */
+#define PDB_WR_PODLY_DLY2(base, index, value) (PDB_RMW_PODLY(base, index, PDB_PODLY_DLY2_MASK, PDB_PODLY_DLY2(value)))
+#define PDB_BWR_PODLY_DLY2(base, index, value) (PDB_WR_PODLY_DLY2(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PDB_PODLY, field DLY1[31:16] (RW)
+ *
+ * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
+ * high when the PDB counter is equal to the DLY1. Reading these bits returns the
+ * value of internal register that is effective for the current PDB cycle.
+ */
+/*@{*/
+/*! @brief Read current value of the PDB_PODLY_DLY1 field. */
+#define PDB_RD_PODLY_DLY1(base, index) ((PDB_PODLY_REG(base, index) & PDB_PODLY_DLY1_MASK) >> PDB_PODLY_DLY1_SHIFT)
+#define PDB_BRD_PODLY_DLY1(base, index) (PDB_RD_PODLY_DLY1(base, index))
+
+/*! @brief Set the DLY1 field to a new value. */
+#define PDB_WR_PODLY_DLY1(base, index, value) (PDB_RMW_PODLY(base, index, PDB_PODLY_DLY1_MASK, PDB_PODLY_DLY1(value)))
+#define PDB_BWR_PODLY_DLY1(base, index, value) (PDB_WR_PODLY_DLY1(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 PIT
+ *
+ * Periodic Interrupt Timer
+ *
+ * Registers defined in this header file:
+ * - PIT_MCR - PIT Module Control Register
+ * - PIT_LDVAL - Timer Load Value Register
+ * - PIT_CVAL - Current Timer Value Register
+ * - PIT_TCTRL - Timer Control Register
+ * - PIT_TFLG - Timer Flag Register
+ */
+
+#define PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
+#define PIT_IDX (0U) /*!< Instance number for PIT. */
+
+/*******************************************************************************
+ * PIT_MCR - PIT Module Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_MCR - PIT Module Control Register (RW)
+ *
+ * Reset value: 0x00000006U
+ *
+ * This register enables or disables the PIT timer clocks and controls the
+ * timers when the PIT enters the Debug mode.
+ */
+/*!
+ * @name Constants and macros for entire PIT_MCR register
+ */
+/*@{*/
+#define PIT_RD_MCR(base)         (PIT_MCR_REG(base))
+#define PIT_WR_MCR(base, value)  (PIT_MCR_REG(base) = (value))
+#define PIT_RMW_MCR(base, mask, value) (PIT_WR_MCR(base, (PIT_RD_MCR(base) & ~(mask)) | (value)))
+#define PIT_SET_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) |  (value)))
+#define PIT_CLR_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) & ~(value)))
+#define PIT_TOG_MCR(base, value) (PIT_WR_MCR(base, PIT_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_MCR bitfields
+ */
+
+/*!
+ * @name Register PIT_MCR, field FRZ[0] (RW)
+ *
+ * Allows the timers to be stopped when the device enters the Debug mode.
+ *
+ * Values:
+ * - 0b0 - Timers continue to run in Debug mode.
+ * - 0b1 - Timers are stopped in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_FRZ field. */
+#define PIT_RD_MCR_FRZ(base) ((PIT_MCR_REG(base) & PIT_MCR_FRZ_MASK) >> PIT_MCR_FRZ_SHIFT)
+#define PIT_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define PIT_WR_MCR_FRZ(base, value) (PIT_RMW_MCR(base, PIT_MCR_FRZ_MASK, PIT_MCR_FRZ(value)))
+#define PIT_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_MCR, field MDIS[1] (RW)
+ *
+ * Disables the standard timers. This field must be enabled before any other
+ * setup is done.
+ *
+ * Values:
+ * - 0b0 - Clock for standard PIT timers is enabled.
+ * - 0b1 - Clock for standard PIT timers is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_MCR_MDIS field. */
+#define PIT_RD_MCR_MDIS(base) ((PIT_MCR_REG(base) & PIT_MCR_MDIS_MASK) >> PIT_MCR_MDIS_SHIFT)
+#define PIT_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define PIT_WR_MCR_MDIS(base, value) (PIT_RMW_MCR(base, PIT_MCR_MDIS_MASK, PIT_MCR_MDIS(value)))
+#define PIT_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_LDVAL - Timer Load Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_LDVAL - Timer Load Value Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers select the timeout period for the timer interrupts.
+ */
+/*!
+ * @name Constants and macros for entire PIT_LDVAL register
+ */
+/*@{*/
+#define PIT_RD_LDVAL(base, index) (PIT_LDVAL_REG(base, index))
+#define PIT_WR_LDVAL(base, index, value) (PIT_LDVAL_REG(base, index) = (value))
+#define PIT_RMW_LDVAL(base, index, mask, value) (PIT_WR_LDVAL(base, index, (PIT_RD_LDVAL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) |  (value)))
+#define PIT_CLR_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) & ~(value)))
+#define PIT_TOG_LDVAL(base, index, value) (PIT_WR_LDVAL(base, index, PIT_RD_LDVAL(base, index) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_CVAL - Current Timer Value Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_CVAL - Current Timer Value Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers indicate the current timer position.
+ */
+/*!
+ * @name Constants and macros for entire PIT_CVAL register
+ */
+/*@{*/
+#define PIT_RD_CVAL(base, index) (PIT_CVAL_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TCTRL - Timer Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TCTRL - Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers contain the control bits for each timer.
+ */
+/*!
+ * @name Constants and macros for entire PIT_TCTRL register
+ */
+/*@{*/
+#define PIT_RD_TCTRL(base, index) (PIT_TCTRL_REG(base, index))
+#define PIT_WR_TCTRL(base, index, value) (PIT_TCTRL_REG(base, index) = (value))
+#define PIT_RMW_TCTRL(base, index, mask, value) (PIT_WR_TCTRL(base, index, (PIT_RD_TCTRL(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) |  (value)))
+#define PIT_CLR_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) & ~(value)))
+#define PIT_TOG_TCTRL(base, index, value) (PIT_WR_TCTRL(base, index, PIT_RD_TCTRL(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TCTRL bitfields
+ */
+
+/*!
+ * @name Register PIT_TCTRL, field TEN[0] (RW)
+ *
+ * Enables or disables the timer.
+ *
+ * Values:
+ * - 0b0 - Timer n is disabled.
+ * - 0b1 - Timer n is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TEN field. */
+#define PIT_RD_TCTRL_TEN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TEN_MASK) >> PIT_TCTRL_TEN_SHIFT)
+#define PIT_BRD_TCTRL_TEN(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT))
+
+/*! @brief Set the TEN field to a new value. */
+#define PIT_WR_TCTRL_TEN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TEN_MASK, PIT_TCTRL_TEN(value)))
+#define PIT_BWR_TCTRL_TEN(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field TIE[1] (RW)
+ *
+ * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
+ * will immediately cause an interrupt event. To avoid this, the associated
+ * TFLGn[TIF] must be cleared first.
+ *
+ * Values:
+ * - 0b0 - Interrupt requests from Timer n are disabled.
+ * - 0b1 - Interrupt will be requested whenever TIF is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_TIE field. */
+#define PIT_RD_TCTRL_TIE(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TIE_MASK) >> PIT_TCTRL_TIE_SHIFT)
+#define PIT_BRD_TCTRL_TIE(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define PIT_WR_TCTRL_TIE(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TIE_MASK, PIT_TCTRL_TIE(value)))
+#define PIT_BWR_TCTRL_TIE(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PIT_TCTRL, field CHN[2] (RW)
+ *
+ * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
+ * Timer 0 cannot be chained.
+ *
+ * Values:
+ * - 0b0 - Timer is not chained.
+ * - 0b1 - Timer is chained to previous timer. For example, for Channel 2, if
+ *     this field is set, Timer 2 is chained to Timer 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TCTRL_CHN field. */
+#define PIT_RD_TCTRL_CHN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_CHN_MASK) >> PIT_TCTRL_CHN_SHIFT)
+#define PIT_BRD_TCTRL_CHN(base, index) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT))
+
+/*! @brief Set the CHN field to a new value. */
+#define PIT_WR_TCTRL_CHN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_CHN_MASK, PIT_TCTRL_CHN(value)))
+#define PIT_BWR_TCTRL_CHN(base, index, value) (BITBAND_ACCESS32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PIT_TFLG - Timer Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PIT_TFLG - Timer Flag Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * These registers hold the PIT interrupt flags.
+ */
+/*!
+ * @name Constants and macros for entire PIT_TFLG register
+ */
+/*@{*/
+#define PIT_RD_TFLG(base, index) (PIT_TFLG_REG(base, index))
+#define PIT_WR_TFLG(base, index, value) (PIT_TFLG_REG(base, index) = (value))
+#define PIT_RMW_TFLG(base, index, mask, value) (PIT_WR_TFLG(base, index, (PIT_RD_TFLG(base, index) & ~(mask)) | (value)))
+#define PIT_SET_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) |  (value)))
+#define PIT_CLR_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) & ~(value)))
+#define PIT_TOG_TFLG(base, index, value) (PIT_WR_TFLG(base, index, PIT_RD_TFLG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PIT_TFLG bitfields
+ */
+
+/*!
+ * @name Register PIT_TFLG, field TIF[0] (W1C)
+ *
+ * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
+ * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
+ * interrupt request.
+ *
+ * Values:
+ * - 0b0 - Timeout has not yet occurred.
+ * - 0b1 - Timeout has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the PIT_TFLG_TIF field. */
+#define PIT_RD_TFLG_TIF(base, index) ((PIT_TFLG_REG(base, index) & PIT_TFLG_TIF_MASK) >> PIT_TFLG_TIF_SHIFT)
+#define PIT_BRD_TFLG_TIF(base, index) (BITBAND_ACCESS32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT))
+
+/*! @brief Set the TIF field to a new value. */
+#define PIT_WR_TFLG_TIF(base, index, value) (PIT_RMW_TFLG(base, index, PIT_TFLG_TIF_MASK, PIT_TFLG_TIF(value)))
+#define PIT_BWR_TFLG_TIF(base, index, value) (BITBAND_ACCESS32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PMC
+ *
+ * Power Management Controller
+ *
+ * Registers defined in this header file:
+ * - PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ * - PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ * - PMC_REGSC - Regulator Status And Control register
+ */
+
+#define PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
+#define PMC_IDX (0U) /*!< Instance number for PMC. */
+
+/*******************************************************************************
+ * PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
+ *
+ * Reset value: 0x10U
+ *
+ * This register contains status and control bits to support the low voltage
+ * detect function. This register should be written during the reset initialization
+ * program to set the desired controls even if the desired settings are the same
+ * as the reset settings. While the device is in the very low power or low
+ * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
+ * systems that must have LVD always on, configure the Power Mode Protection
+ * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
+ * low leakage modes from being enabled. See the device's data sheet for the
+ * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
+ * register's other bits are reset on Chip Reset Not VLLS. For more information
+ * about these reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC1 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC1(base)      (PMC_LVDSC1_REG(base))
+#define PMC_WR_LVDSC1(base, value) (PMC_LVDSC1_REG(base) = (value))
+#define PMC_RMW_LVDSC1(base, mask, value) (PMC_WR_LVDSC1(base, (PMC_RD_LVDSC1(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) |  (value)))
+#define PMC_CLR_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) & ~(value)))
+#define PMC_TOG_LVDSC1(base, value) (PMC_WR_LVDSC1(base, PMC_RD_LVDSC1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC1 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
+ *
+ * Selects the LVD trip point voltage (V LVD ).
+ *
+ * Values:
+ * - 0b00 - Low trip point selected (V LVD = V LVDL )
+ * - 0b01 - High trip point selected (V LVD = V LVDH )
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
+#define PMC_RD_LVDSC1_LVDV(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDV_MASK) >> PMC_LVDSC1_LVDV_SHIFT)
+#define PMC_BRD_LVDSC1_LVDV(base) (PMC_RD_LVDSC1_LVDV(base))
+
+/*! @brief Set the LVDV field to a new value. */
+#define PMC_WR_LVDSC1_LVDV(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDV_MASK, PMC_LVDSC1_LVDV(value)))
+#define PMC_BWR_LVDSC1_LVDV(base, value) (PMC_WR_LVDSC1_LVDV(base, value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
+ *
+ * This write-once bit enables LVDF events to generate a hardware reset.
+ * Additional writes are ignored.
+ *
+ * Values:
+ * - 0b0 - LVDF does not generate hardware resets
+ * - 0b1 - Force an MCU reset when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
+#define PMC_RD_LVDSC1_LVDRE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDRE_MASK) >> PMC_LVDSC1_LVDRE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDRE(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT))
+
+/*! @brief Set the LVDRE field to a new value. */
+#define PMC_WR_LVDSC1_LVDRE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDRE_MASK, PMC_LVDSC1_LVDRE(value)))
+#define PMC_BWR_LVDSC1_LVDRE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVDF.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupt disabled (use polling)
+ * - 0b1 - Request a hardware interrupt when LVDF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
+#define PMC_RD_LVDSC1_LVDIE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDIE_MASK) >> PMC_LVDSC1_LVDIE_SHIFT)
+#define PMC_BRD_LVDSC1_LVDIE(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT))
+
+/*! @brief Set the LVDIE field to a new value. */
+#define PMC_WR_LVDSC1_LVDIE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDIE_MASK, PMC_LVDSC1_LVDIE(value)))
+#define PMC_BWR_LVDSC1_LVDIE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage detection errors.
+ * Write 1 to clear LVDF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVDACK field to a new value. */
+#define PMC_WR_LVDSC1_LVDACK(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDACK_MASK, PMC_LVDSC1_LVDACK(value)))
+#define PMC_BWR_LVDSC1_LVDACK(base, value) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC1, field LVDF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage detect event.
+ *
+ * Values:
+ * - 0b0 - Low-voltage event not detected
+ * - 0b1 - Low-voltage event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
+#define PMC_RD_LVDSC1_LVDF(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDF_MASK) >> PMC_LVDSC1_LVDF_SHIFT)
+#define PMC_BRD_LVDSC1_LVDF(base) (BITBAND_ACCESS8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains status and control bits to support the low voltage
+ * warning function. While the device is in the very low power or low leakage modes,
+ * the LVD system is disabled regardless of LVDSC2 settings. See the device's
+ * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
+ * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
+ * register are reset on Chip Reset Not VLLS. For more information about these
+ * reset types, refer to the Reset section details.
+ */
+/*!
+ * @name Constants and macros for entire PMC_LVDSC2 register
+ */
+/*@{*/
+#define PMC_RD_LVDSC2(base)      (PMC_LVDSC2_REG(base))
+#define PMC_WR_LVDSC2(base, value) (PMC_LVDSC2_REG(base) = (value))
+#define PMC_RMW_LVDSC2(base, mask, value) (PMC_WR_LVDSC2(base, (PMC_RD_LVDSC2(base) & ~(mask)) | (value)))
+#define PMC_SET_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) |  (value)))
+#define PMC_CLR_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) & ~(value)))
+#define PMC_TOG_LVDSC2(base, value) (PMC_WR_LVDSC2(base, PMC_RD_LVDSC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_LVDSC2 bitfields
+ */
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
+ *
+ * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
+ * depends on LVDSC1[LVDV].
+ *
+ * Values:
+ * - 0b00 - Low trip point selected (VLVW = VLVW1)
+ * - 0b01 - Mid 1 trip point selected (VLVW = VLVW2)
+ * - 0b10 - Mid 2 trip point selected (VLVW = VLVW3)
+ * - 0b11 - High trip point selected (VLVW = VLVW4)
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
+#define PMC_RD_LVDSC2_LVWV(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWV_MASK) >> PMC_LVDSC2_LVWV_SHIFT)
+#define PMC_BRD_LVDSC2_LVWV(base) (PMC_RD_LVDSC2_LVWV(base))
+
+/*! @brief Set the LVWV field to a new value. */
+#define PMC_WR_LVDSC2_LVWV(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWV_MASK, PMC_LVDSC2_LVWV(value)))
+#define PMC_BWR_LVDSC2_LVWV(base, value) (PMC_WR_LVDSC2_LVWV(base, value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
+ *
+ * Enables hardware interrupt requests for LVWF.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupt disabled (use polling)
+ * - 0b1 - Request a hardware interrupt when LVWF = 1
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
+#define PMC_RD_LVDSC2_LVWIE(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWIE_MASK) >> PMC_LVDSC2_LVWIE_SHIFT)
+#define PMC_BRD_LVDSC2_LVWIE(base) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT))
+
+/*! @brief Set the LVWIE field to a new value. */
+#define PMC_WR_LVDSC2_LVWIE(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWIE_MASK, PMC_LVDSC2_LVWIE(value)))
+#define PMC_BWR_LVDSC2_LVWIE(base, value) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
+ *
+ * This write-only field is used to acknowledge low voltage warning errors.
+ * Write 1 to clear LVWF. Reads always return 0.
+ */
+/*@{*/
+/*! @brief Set the LVWACK field to a new value. */
+#define PMC_WR_LVDSC2_LVWACK(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWACK_MASK, PMC_LVDSC2_LVWACK(value)))
+#define PMC_BWR_LVDSC2_LVWACK(base, value) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_LVDSC2, field LVWF[7] (RO)
+ *
+ * This read-only status field indicates a low-voltage warning event. LVWF is
+ * set when VSupply transitions below the trip point, or after reset and VSupply is
+ * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
+ * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
+ * LVWACK first.
+ *
+ * Values:
+ * - 0b0 - Low-voltage warning event not detected
+ * - 0b1 - Low-voltage warning event detected
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
+#define PMC_RD_LVDSC2_LVWF(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWF_MASK) >> PMC_LVDSC2_LVWF_SHIFT)
+#define PMC_BRD_LVDSC2_LVWF(base) (BITBAND_ACCESS8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWF_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * PMC_REGSC - Regulator Status And Control register
+ ******************************************************************************/
+
+/*!
+ * @brief PMC_REGSC - Regulator Status And Control register (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * The PMC contains an internal voltage regulator. The voltage regulator design
+ * uses a bandgap reference that is also available through a buffer as input to
+ * certain internal peripherals, such as the CMP and ADC. The internal regulator
+ * provides a status bit (REGONS) indicating the regulator is in run regulation.
+ * This register is reset on Chip Reset Not VLLS and by reset types that trigger
+ * Chip Reset not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire PMC_REGSC register
+ */
+/*@{*/
+#define PMC_RD_REGSC(base)       (PMC_REGSC_REG(base))
+#define PMC_WR_REGSC(base, value) (PMC_REGSC_REG(base) = (value))
+#define PMC_RMW_REGSC(base, mask, value) (PMC_WR_REGSC(base, (PMC_RD_REGSC(base) & ~(mask)) | (value)))
+#define PMC_SET_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) |  (value)))
+#define PMC_CLR_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) & ~(value)))
+#define PMC_TOG_REGSC(base, value) (PMC_WR_REGSC(base, PMC_RD_REGSC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PMC_REGSC bitfields
+ */
+
+/*!
+ * @name Register PMC_REGSC, field BGBE[0] (RW)
+ *
+ * Enables the bandgap buffer.
+ *
+ * Values:
+ * - 0b0 - Bandgap buffer not enabled
+ * - 0b1 - Bandgap buffer enabled
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGBE field. */
+#define PMC_RD_REGSC_BGBE(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGBE_MASK) >> PMC_REGSC_BGBE_SHIFT)
+#define PMC_BRD_REGSC_BGBE(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT))
+
+/*! @brief Set the BGBE field to a new value. */
+#define PMC_WR_REGSC_BGBE(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGBE_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGBE(value)))
+#define PMC_BWR_REGSC_BGBE(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field REGONS[2] (RO)
+ *
+ * This read-only field provides the current status of the internal voltage
+ * regulator.
+ *
+ * Values:
+ * - 0b0 - Regulator is in stop regulation or in transition to/from it
+ * - 0b1 - Regulator is in run regulation
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_REGONS field. */
+#define PMC_RD_REGSC_REGONS(base) ((PMC_REGSC_REG(base) & PMC_REGSC_REGONS_MASK) >> PMC_REGSC_REGONS_SHIFT)
+#define PMC_BRD_REGSC_REGONS(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_REGONS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field ACKISO[3] (W1C)
+ *
+ * Reading this field indicates whether certain peripherals and the I/O pads are
+ * in a latched state as a result of having been in a VLLS mode. Writing 1 to
+ * this field when it is set releases the I/O pads and certain peripherals to their
+ * normal run mode state. After recovering from a VLLS mode, user should restore
+ * chip configuration before clearing ACKISO. In particular, pin configuration
+ * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
+ * being falsely set when ACKISO is cleared.
+ *
+ * Values:
+ * - 0b0 - Peripherals and I/O pads are in normal run state.
+ * - 0b1 - Certain peripherals and I/O pads are in an isolated and latched state.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_ACKISO field. */
+#define PMC_RD_REGSC_ACKISO(base) ((PMC_REGSC_REG(base) & PMC_REGSC_ACKISO_MASK) >> PMC_REGSC_ACKISO_SHIFT)
+#define PMC_BRD_REGSC_ACKISO(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT))
+
+/*! @brief Set the ACKISO field to a new value. */
+#define PMC_WR_REGSC_ACKISO(base, value) (PMC_RMW_REGSC(base, PMC_REGSC_ACKISO_MASK, PMC_REGSC_ACKISO(value)))
+#define PMC_BWR_REGSC_ACKISO(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PMC_REGSC, field BGEN[4] (RW)
+ *
+ * BGEN controls whether the bandgap is enabled in lower power modes of
+ * operation (VLPx, LLS, and VLLSx). When on-chip peripherals require the bandgap voltage
+ * reference in low power modes of operation, set BGEN to continue to enable the
+ * bandgap operation. When the bandgap voltage reference is not needed in low
+ * power modes, clear BGEN to avoid excess power consumption.
+ *
+ * Values:
+ * - 0b0 - Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
+ * - 0b1 - Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
+ */
+/*@{*/
+/*! @brief Read current value of the PMC_REGSC_BGEN field. */
+#define PMC_RD_REGSC_BGEN(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGEN_MASK) >> PMC_REGSC_BGEN_SHIFT)
+#define PMC_BRD_REGSC_BGEN(base) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT))
+
+/*! @brief Set the BGEN field to a new value. */
+#define PMC_WR_REGSC_BGEN(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGEN_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGEN(value)))
+#define PMC_BWR_REGSC_BGEN(base, value) (BITBAND_ACCESS8(&PMC_REGSC_REG(base), PMC_REGSC_BGEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 PORT
+ *
+ * Pin Control and Interrupts
+ *
+ * Registers defined in this header file:
+ * - PORT_PCR - Pin Control Register n
+ * - PORT_GPCLR - Global Pin Control Low Register
+ * - PORT_GPCHR - Global Pin Control High Register
+ * - PORT_ISFR - Interrupt Status Flag Register
+ * - PORT_DFER - Digital Filter Enable Register
+ * - PORT_DFCR - Digital Filter Clock Register
+ * - PORT_DFWR - Digital Filter Width Register
+ */
+
+#define PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
+#define PORTA_IDX (0U) /*!< Instance number for PORTA. */
+#define PORTB_IDX (1U) /*!< Instance number for PORTB. */
+#define PORTC_IDX (2U) /*!< Instance number for PORTC. */
+#define PORTD_IDX (3U) /*!< Instance number for PORTD. */
+#define PORTE_IDX (4U) /*!< Instance number for PORTE. */
+
+/*******************************************************************************
+ * PORT_PCR - Pin Control Register n
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_PCR - Pin Control Register n (RW)
+ *
+ * Reset value: 0x00000746U
+ *
+ * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
+ * this device. See the GPIO Configuration section for details on the available
+ * functions for each pin. Do not modify pin configuration registers associated
+ * with pins not available in your selected package. All unbonded pins not
+ * available in your package will default to DISABLE state for lowest power consumption.
+ */
+/*!
+ * @name Constants and macros for entire PORT_PCR register
+ */
+/*@{*/
+#define PORT_RD_PCR(base, index) (PORT_PCR_REG(base, index))
+#define PORT_WR_PCR(base, index, value) (PORT_PCR_REG(base, index) = (value))
+#define PORT_RMW_PCR(base, index, mask, value) (PORT_WR_PCR(base, index, (PORT_RD_PCR(base, index) & ~(mask)) | (value)))
+#define PORT_SET_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) |  (value)))
+#define PORT_CLR_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) & ~(value)))
+#define PORT_TOG_PCR(base, index, value) (PORT_WR_PCR(base, index, PORT_RD_PCR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_PCR bitfields
+ */
+
+/*!
+ * @name Register PORT_PCR, field PS[0] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Internal pulldown resistor is enabled on the corresponding pin, if
+ *     the corresponding PE field is set.
+ * - 0b1 - Internal pullup resistor is enabled on the corresponding pin, if the
+ *     corresponding PE field is set.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PS field. */
+#define PORT_RD_PCR_PS(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PS_MASK) >> PORT_PCR_PS_SHIFT)
+#define PORT_BRD_PCR_PS(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT))
+
+/*! @brief Set the PS field to a new value. */
+#define PORT_WR_PCR_PS(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PS_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PS(value)))
+#define PORT_BWR_PCR_PS(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PE[1] (RW)
+ *
+ * Pull configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Internal pullup or pulldown resistor is not enabled on the
+ *     corresponding pin.
+ * - 0b1 - Internal pullup or pulldown resistor is enabled on the corresponding
+ *     pin, if the pin is configured as a digital input.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PE field. */
+#define PORT_RD_PCR_PE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PE_MASK) >> PORT_PCR_PE_SHIFT)
+#define PORT_BRD_PCR_PE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT))
+
+/*! @brief Set the PE field to a new value. */
+#define PORT_WR_PCR_PE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PE(value)))
+#define PORT_BWR_PCR_PE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field SRE[2] (RW)
+ *
+ * Slew rate configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Fast slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ * - 0b1 - Slow slew rate is configured on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_SRE field. */
+#define PORT_RD_PCR_SRE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_SRE_MASK) >> PORT_PCR_SRE_SHIFT)
+#define PORT_BRD_PCR_SRE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT))
+
+/*! @brief Set the SRE field to a new value. */
+#define PORT_WR_PCR_SRE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_SRE(value)))
+#define PORT_BWR_PCR_SRE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field PFE[4] (RW)
+ *
+ * Passive filter configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Passive input filter is disabled on the corresponding pin.
+ * - 0b1 - Passive input filter is enabled on the corresponding pin, if the pin
+ *     is configured as a digital input. Refer to the device data sheet for
+ *     filter characteristics.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_PFE field. */
+#define PORT_RD_PCR_PFE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PFE_MASK) >> PORT_PCR_PFE_SHIFT)
+#define PORT_BRD_PCR_PFE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT))
+
+/*! @brief Set the PFE field to a new value. */
+#define PORT_WR_PCR_PFE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PFE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PFE(value)))
+#define PORT_BWR_PCR_PFE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ODE[5] (RW)
+ *
+ * Open drain configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Open drain output is disabled on the corresponding pin.
+ * - 0b1 - Open drain output is enabled on the corresponding pin, if the pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ODE field. */
+#define PORT_RD_PCR_ODE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ODE_MASK) >> PORT_PCR_ODE_SHIFT)
+#define PORT_BRD_PCR_ODE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ODE_SHIFT))
+
+/*! @brief Set the ODE field to a new value. */
+#define PORT_WR_PCR_ODE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_ODE(value)))
+#define PORT_BWR_PCR_ODE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field DSE[6] (RW)
+ *
+ * Drive strength configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Low drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ * - 0b1 - High drive strength is configured on the corresponding pin, if pin is
+ *     configured as a digital output.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_DSE field. */
+#define PORT_RD_PCR_DSE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_DSE_MASK) >> PORT_PCR_DSE_SHIFT)
+#define PORT_BRD_PCR_DSE(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT))
+
+/*! @brief Set the DSE field to a new value. */
+#define PORT_WR_PCR_DSE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_DSE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_DSE(value)))
+#define PORT_BWR_PCR_DSE(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field MUX[10:8] (RW)
+ *
+ * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
+ * reserved and may result in configuring the pin for a different pin muxing
+ * slot. The corresponding pin is configured in the following pin muxing slot as
+ * follows:
+ *
+ * Values:
+ * - 0b000 - Pin disabled (analog).
+ * - 0b001 - Alternative 1 (GPIO).
+ * - 0b010 - Alternative 2 (chip-specific).
+ * - 0b011 - Alternative 3 (chip-specific).
+ * - 0b100 - Alternative 4 (chip-specific).
+ * - 0b101 - Alternative 5 (chip-specific).
+ * - 0b110 - Alternative 6 (chip-specific).
+ * - 0b111 - Alternative 7 (chip-specific).
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_MUX field. */
+#define PORT_RD_PCR_MUX(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_MUX_MASK) >> PORT_PCR_MUX_SHIFT)
+#define PORT_BRD_PCR_MUX(base, index) (PORT_RD_PCR_MUX(base, index))
+
+/*! @brief Set the MUX field to a new value. */
+#define PORT_WR_PCR_MUX(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_MUX_MASK | PORT_PCR_ISF_MASK), PORT_PCR_MUX(value)))
+#define PORT_BWR_PCR_MUX(base, index, value) (PORT_WR_PCR_MUX(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field LK[15] (RW)
+ *
+ * Values:
+ * - 0b0 - Pin Control Register fields [15:0] are not locked.
+ * - 0b1 - Pin Control Register fields [15:0] are locked and cannot be updated
+ *     until the next system reset.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_LK field. */
+#define PORT_RD_PCR_LK(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_LK_MASK) >> PORT_PCR_LK_SHIFT)
+#define PORT_BRD_PCR_LK(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_LK_SHIFT))
+
+/*! @brief Set the LK field to a new value. */
+#define PORT_WR_PCR_LK(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_LK_MASK | PORT_PCR_ISF_MASK), PORT_PCR_LK(value)))
+#define PORT_BWR_PCR_LK(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_LK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field IRQC[19:16] (RW)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * corresponding pin is configured to generate interrupt/DMA request as follows:
+ *
+ * Values:
+ * - 0b0000 - Interrupt/DMA request disabled.
+ * - 0b0001 - DMA request on rising edge.
+ * - 0b0010 - DMA request on falling edge.
+ * - 0b0011 - DMA request on either edge.
+ * - 0b1000 - Interrupt when logic 0.
+ * - 0b1001 - Interrupt on rising-edge.
+ * - 0b1010 - Interrupt on falling-edge.
+ * - 0b1011 - Interrupt on either edge.
+ * - 0b1100 - Interrupt when logic 1.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_IRQC field. */
+#define PORT_RD_PCR_IRQC(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_IRQC_MASK) >> PORT_PCR_IRQC_SHIFT)
+#define PORT_BRD_PCR_IRQC(base, index) (PORT_RD_PCR_IRQC(base, index))
+
+/*! @brief Set the IRQC field to a new value. */
+#define PORT_WR_PCR_IRQC(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_IRQC_MASK | PORT_PCR_ISF_MASK), PORT_PCR_IRQC(value)))
+#define PORT_BWR_PCR_IRQC(base, index, value) (PORT_WR_PCR_IRQC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_PCR, field ISF[24] (W1C)
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes.
+ *
+ * Values:
+ * - 0b0 - Configured interrupt is not detected.
+ * - 0b1 - Configured interrupt is detected. If the pin is configured to
+ *     generate a DMA request, then the corresponding flag will be cleared automatically
+ *     at the completion of the requested DMA transfer. Otherwise, the flag
+ *     remains set until a logic 1 is written to the flag. If the pin is configured
+ *     for a level sensitive interrupt and the pin remains asserted, then the flag
+ *     is set again immediately after it is cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_PCR_ISF field. */
+#define PORT_RD_PCR_ISF(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ISF_MASK) >> PORT_PCR_ISF_SHIFT)
+#define PORT_BRD_PCR_ISF(base, index) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT))
+
+/*! @brief Set the ISF field to a new value. */
+#define PORT_WR_PCR_ISF(base, index, value) (PORT_RMW_PCR(base, index, PORT_PCR_ISF_MASK, PORT_PCR_ISF(value)))
+#define PORT_BWR_PCR_ISF(base, index, value) (BITBAND_ACCESS32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCLR - Global Pin Control Low Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCLR - Global Pin Control Low Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCLR register
+ */
+/*@{*/
+#define PORT_RD_GPCLR(base)      (PORT_GPCLR_REG(base))
+#define PORT_WR_GPCLR(base, value) (PORT_GPCLR_REG(base) = (value))
+#define PORT_RMW_GPCLR(base, mask, value) (PORT_WR_GPCLR(base, (PORT_RD_GPCLR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCLR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCLR_GPWD(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWD_MASK, PORT_GPCLR_GPWD(value)))
+#define PORT_BWR_GPCLR_GPWD(base, value) (PORT_WR_GPCLR_GPWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
+ *     the value in GPWD.
+ * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
+ *     value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCLR_GPWE(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWE_MASK, PORT_GPCLR_GPWE(value)))
+#define PORT_BWR_GPCLR_GPWE(base, value) (PORT_WR_GPCLR_GPWE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_GPCHR - Global Pin Control High Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_GPCHR - Global Pin Control High Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Only 32-bit writes are supported to this register.
+ */
+/*!
+ * @name Constants and macros for entire PORT_GPCHR register
+ */
+/*@{*/
+#define PORT_RD_GPCHR(base)      (PORT_GPCHR_REG(base))
+#define PORT_WR_GPCHR(base, value) (PORT_GPCHR_REG(base) = (value))
+#define PORT_RMW_GPCHR(base, mask, value) (PORT_WR_GPCHR(base, (PORT_RD_GPCHR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_GPCHR bitfields
+ */
+
+/*!
+ * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
+ *
+ * Write value that is written to all Pin Control Registers bits [15:0] that are
+ * selected by GPWE.
+ */
+/*@{*/
+/*! @brief Set the GPWD field to a new value. */
+#define PORT_WR_GPCHR_GPWD(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWD_MASK, PORT_GPCHR_GPWD(value)))
+#define PORT_BWR_GPCHR_GPWD(base, value) (PORT_WR_GPCHR_GPWD(base, value))
+/*@}*/
+
+/*!
+ * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
+ *
+ * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
+ * the value in GPWD. If a selected Pin Control Register is locked then the write
+ * to that register is ignored.
+ *
+ * Values:
+ * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
+ *     the value in GPWD.
+ * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
+ *     value in GPWD.
+ */
+/*@{*/
+/*! @brief Set the GPWE field to a new value. */
+#define PORT_WR_GPCHR_GPWE(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWE_MASK, PORT_GPCHR_GPWE(value)))
+#define PORT_BWR_GPCHR_GPWE(base, value) (PORT_WR_GPCHR_GPWE(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_ISFR - Interrupt Status Flag Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_ISFR - Interrupt Status Flag Register (W1C)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The pin interrupt configuration is valid in all digital pin muxing modes. The
+ * Interrupt Status Flag for each pin is also visible in the corresponding Pin
+ * Control Register, and each flag can be cleared in either location.
+ */
+/*!
+ * @name Constants and macros for entire PORT_ISFR register
+ */
+/*@{*/
+#define PORT_RD_ISFR(base)       (PORT_ISFR_REG(base))
+#define PORT_WR_ISFR(base, value) (PORT_ISFR_REG(base) = (value))
+#define PORT_RMW_ISFR(base, mask, value) (PORT_WR_ISFR(base, (PORT_RD_ISFR(base) & ~(mask)) | (value)))
+#define PORT_SET_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) |  (value)))
+#define PORT_CLR_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) & ~(value)))
+#define PORT_TOG_ISFR(base, value) (PORT_WR_ISFR(base, PORT_RD_ISFR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFER - Digital Filter Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFER - Digital Filter Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The corresponding bit is read only for pins that do not support a digital
+ * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
+ * the pins that support digital filter. The digital filter configuration is valid
+ * in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFER register
+ */
+/*@{*/
+#define PORT_RD_DFER(base)       (PORT_DFER_REG(base))
+#define PORT_WR_DFER(base, value) (PORT_DFER_REG(base) = (value))
+#define PORT_RMW_DFER(base, mask, value) (PORT_WR_DFER(base, (PORT_RD_DFER(base) & ~(mask)) | (value)))
+#define PORT_SET_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) |  (value)))
+#define PORT_CLR_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) & ~(value)))
+#define PORT_TOG_DFER(base, value) (PORT_WR_DFER(base, PORT_RD_DFER(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFCR - Digital Filter Clock Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFCR - Digital Filter Clock Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFCR register
+ */
+/*@{*/
+#define PORT_RD_DFCR(base)       (PORT_DFCR_REG(base))
+#define PORT_WR_DFCR(base, value) (PORT_DFCR_REG(base) = (value))
+#define PORT_RMW_DFCR(base, mask, value) (PORT_WR_DFCR(base, (PORT_RD_DFCR(base) & ~(mask)) | (value)))
+#define PORT_SET_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) |  (value)))
+#define PORT_CLR_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) & ~(value)))
+#define PORT_TOG_DFCR(base, value) (PORT_WR_DFCR(base, PORT_RD_DFCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_DFCR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFCR, field CS[0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the clock source for the digital input filters. Changing the filter
+ * clock source must be done only when all digital filters are disabled.
+ *
+ * Values:
+ * - 0b0 - Digital filters are clocked by the bus clock.
+ * - 0b1 - Digital filters are clocked by the 1 kHz LPO clock.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_DFCR_CS field. */
+#define PORT_RD_DFCR_CS(base) ((PORT_DFCR_REG(base) & PORT_DFCR_CS_MASK) >> PORT_DFCR_CS_SHIFT)
+#define PORT_BRD_DFCR_CS(base) (BITBAND_ACCESS32(&PORT_DFCR_REG(base), PORT_DFCR_CS_SHIFT))
+
+/*! @brief Set the CS field to a new value. */
+#define PORT_WR_DFCR_CS(base, value) (PORT_RMW_DFCR(base, PORT_DFCR_CS_MASK, PORT_DFCR_CS(value)))
+#define PORT_BWR_DFCR_CS(base, value) (BITBAND_ACCESS32(&PORT_DFCR_REG(base), PORT_DFCR_CS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * PORT_DFWR - Digital Filter Width Register
+ ******************************************************************************/
+
+/*!
+ * @brief PORT_DFWR - Digital Filter Width Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is read only for ports that do not support a digital filter.
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ */
+/*!
+ * @name Constants and macros for entire PORT_DFWR register
+ */
+/*@{*/
+#define PORT_RD_DFWR(base)       (PORT_DFWR_REG(base))
+#define PORT_WR_DFWR(base, value) (PORT_DFWR_REG(base) = (value))
+#define PORT_RMW_DFWR(base, mask, value) (PORT_WR_DFWR(base, (PORT_RD_DFWR(base) & ~(mask)) | (value)))
+#define PORT_SET_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) |  (value)))
+#define PORT_CLR_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) & ~(value)))
+#define PORT_TOG_DFWR(base, value) (PORT_WR_DFWR(base, PORT_RD_DFWR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual PORT_DFWR bitfields
+ */
+
+/*!
+ * @name Register PORT_DFWR, field FILT[4:0] (RW)
+ *
+ * The digital filter configuration is valid in all digital pin muxing modes.
+ * Configures the maximum size of the glitches, in clock cycles, that the digital
+ * filter absorbs for the enabled digital filters. Glitches that are longer than
+ * this register setting will pass through the digital filter, and glitches that
+ * are equal to or less than this register setting are filtered. Changing the
+ * filter length must be done only after all filters are disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the PORT_DFWR_FILT field. */
+#define PORT_RD_DFWR_FILT(base) ((PORT_DFWR_REG(base) & PORT_DFWR_FILT_MASK) >> PORT_DFWR_FILT_SHIFT)
+#define PORT_BRD_DFWR_FILT(base) (PORT_RD_DFWR_FILT(base))
+
+/*! @brief Set the FILT field to a new value. */
+#define PORT_WR_DFWR_FILT(base, value) (PORT_RMW_DFWR(base, PORT_DFWR_FILT_MASK, PORT_DFWR_FILT(value)))
+#define PORT_BWR_DFWR_FILT(base, value) (PORT_WR_DFWR_FILT(base, value))
+/*@}*/
+
+/*
+ * MK64F12 RCM
+ *
+ * Reset Control Module
+ *
+ * Registers defined in this header file:
+ * - RCM_SRS0 - System Reset Status Register 0
+ * - RCM_SRS1 - System Reset Status Register 1
+ * - RCM_RPFC - Reset Pin Filter Control register
+ * - RCM_RPFW - Reset Pin Filter Width register
+ * - RCM_MR - Mode Register
+ */
+
+#define RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */
+#define RCM_IDX (0U) /*!< Instance number for RCM. */
+
+/*******************************************************************************
+ * RCM_SRS0 - System Reset Status Register 0
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS0 - System Reset Status Register 0 (RO)
+ *
+ * Reset value: 0x82U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
+ * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS0 register
+ */
+/*@{*/
+#define RCM_RD_SRS0(base)        (RCM_SRS0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS0 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS0, field WAKEUP[0] (RO)
+ *
+ * Indicates a reset has been caused by an enabled LLWU module wakeup source
+ * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
+ * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
+ * mode causes a reset. This bit is cleared by any reset except WAKEUP.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by LLWU module wakeup source
+ * - 0b1 - Reset caused by LLWU module wakeup source
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WAKEUP field. */
+#define RCM_RD_SRS0_WAKEUP(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WAKEUP_MASK) >> RCM_SRS0_WAKEUP_SHIFT)
+#define RCM_BRD_SRS0_WAKEUP(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_WAKEUP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LVD[1] (RO)
+ *
+ * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
+ * an LVD reset occurs. This field is also set by POR.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by LVD trip or POR
+ * - 0b1 - Reset caused by LVD trip or POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LVD field. */
+#define RCM_RD_SRS0_LVD(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LVD_MASK) >> RCM_SRS0_LVD_SHIFT)
+#define RCM_BRD_SRS0_LVD(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LVD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LOC[2] (RO)
+ *
+ * Indicates a reset has been caused by a loss of external clock. The MCG clock
+ * monitor must be enabled for a loss of clock to be detected. Refer to the
+ * detailed MCG description for information on enabling the clock monitor.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by a loss of external clock.
+ * - 0b1 - Reset caused by a loss of external clock.
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LOC field. */
+#define RCM_RD_SRS0_LOC(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOC_MASK) >> RCM_SRS0_LOC_SHIFT)
+#define RCM_BRD_SRS0_LOC(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LOC_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field LOL[3] (RO)
+ *
+ * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
+ * MCG description for information on the loss-of-clock event.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by a loss of lock in the PLL
+ * - 0b1 - Reset caused by a loss of lock in the PLL
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_LOL field. */
+#define RCM_RD_SRS0_LOL(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOL_MASK) >> RCM_SRS0_LOL_SHIFT)
+#define RCM_BRD_SRS0_LOL(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_LOL_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field WDOG[5] (RO)
+ *
+ * Indicates a reset has been caused by the watchdog timer Computer Operating
+ * Properly (COP) timing out. This reset source can be blocked by disabling the COP
+ * watchdog: write 00 to SIM_COPCTRL[COPT].
+ *
+ * Values:
+ * - 0b0 - Reset not caused by watchdog timeout
+ * - 0b1 - Reset caused by watchdog timeout
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_WDOG field. */
+#define RCM_RD_SRS0_WDOG(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WDOG_MASK) >> RCM_SRS0_WDOG_SHIFT)
+#define RCM_BRD_SRS0_WDOG(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_WDOG_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field PIN[6] (RO)
+ *
+ * Indicates a reset has been caused by an active-low level on the external
+ * RESET pin.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by external reset pin
+ * - 0b1 - Reset caused by external reset pin
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_PIN field. */
+#define RCM_RD_SRS0_PIN(base) ((RCM_SRS0_REG(base) & RCM_SRS0_PIN_MASK) >> RCM_SRS0_PIN_SHIFT)
+#define RCM_BRD_SRS0_PIN(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_PIN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS0, field POR[7] (RO)
+ *
+ * Indicates a reset has been caused by the power-on detection logic. Because
+ * the internal supply voltage was ramping up at the time, the low-voltage reset
+ * (LVD) status bit is also set to indicate that the reset occurred while the
+ * internal supply was below the LVD threshold.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by POR
+ * - 0b1 - Reset caused by POR
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS0_POR field. */
+#define RCM_RD_SRS0_POR(base) ((RCM_SRS0_REG(base) & RCM_SRS0_POR_MASK) >> RCM_SRS0_POR_SHIFT)
+#define RCM_BRD_SRS0_POR(base) (BITBAND_ACCESS8(&RCM_SRS0_REG(base), RCM_SRS0_POR_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_SRS1 - System Reset Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_SRS1 - System Reset Status Register 1 (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the source of the
+ * most recent reset. The reset state of these bits depends on what caused the MCU
+ * to reset. The reset value of this register depends on the reset source: POR
+ * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
+ * reset - a bit is set if its corresponding reset source caused the reset
+ */
+/*!
+ * @name Constants and macros for entire RCM_SRS1 register
+ */
+/*@{*/
+#define RCM_RD_SRS1(base)        (RCM_SRS1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_SRS1 bitfields
+ */
+
+/*!
+ * @name Register RCM_SRS1, field JTAG[0] (RO)
+ *
+ * Indicates a reset has been caused by JTAG selection of certain IR codes:
+ * EZPORT, EXTEST, HIGHZ, and CLAMP.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by JTAG
+ * - 0b1 - Reset caused by JTAG
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_JTAG field. */
+#define RCM_RD_SRS1_JTAG(base) ((RCM_SRS1_REG(base) & RCM_SRS1_JTAG_MASK) >> RCM_SRS1_JTAG_SHIFT)
+#define RCM_BRD_SRS1_JTAG(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_JTAG_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field LOCKUP[1] (RO)
+ *
+ * Indicates a reset has been caused by the ARM core indication of a LOCKUP
+ * event.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by core LOCKUP event
+ * - 0b1 - Reset caused by core LOCKUP event
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_LOCKUP field. */
+#define RCM_RD_SRS1_LOCKUP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_LOCKUP_MASK) >> RCM_SRS1_LOCKUP_SHIFT)
+#define RCM_BRD_SRS1_LOCKUP(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_LOCKUP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SW[2] (RO)
+ *
+ * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
+ * Application Interrupt and Reset Control Register in the ARM core.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by software setting of SYSRESETREQ bit
+ * - 0b1 - Reset caused by software setting of SYSRESETREQ bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SW field. */
+#define RCM_RD_SRS1_SW(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SW_MASK) >> RCM_SRS1_SW_SHIFT)
+#define RCM_BRD_SRS1_SW(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_SW_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field MDM_AP[3] (RO)
+ *
+ * Indicates a reset has been caused by the host debugger system setting of the
+ * System Reset Request bit in the MDM-AP Control Register.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by host debugger system setting of the System Reset
+ *     Request bit
+ * - 0b1 - Reset caused by host debugger system setting of the System Reset
+ *     Request bit
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_MDM_AP field. */
+#define RCM_RD_SRS1_MDM_AP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_MDM_AP_MASK) >> RCM_SRS1_MDM_AP_SHIFT)
+#define RCM_BRD_SRS1_MDM_AP(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_MDM_AP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field EZPT[4] (RO)
+ *
+ * Indicates a reset has been caused by EzPort receiving the RESET command while
+ * the device is in EzPort mode.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by EzPort receiving the RESET command while the
+ *     device is in EzPort mode
+ * - 0b1 - Reset caused by EzPort receiving the RESET command while the device
+ *     is in EzPort mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_EZPT field. */
+#define RCM_RD_SRS1_EZPT(base) ((RCM_SRS1_REG(base) & RCM_SRS1_EZPT_MASK) >> RCM_SRS1_EZPT_SHIFT)
+#define RCM_BRD_SRS1_EZPT(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_EZPT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RCM_SRS1, field SACKERR[5] (RO)
+ *
+ * Indicates that after an attempt to enter Stop mode, a reset has been caused
+ * by a failure of one or more peripherals to acknowledge within approximately one
+ * second to enter stop mode.
+ *
+ * Values:
+ * - 0b0 - Reset not caused by peripheral failure to acknowledge attempt to
+ *     enter stop mode
+ * - 0b1 - Reset caused by peripheral failure to acknowledge attempt to enter
+ *     stop mode
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_SRS1_SACKERR field. */
+#define RCM_RD_SRS1_SACKERR(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SACKERR_MASK) >> RCM_SRS1_SACKERR_SHIFT)
+#define RCM_BRD_SRS1_SACKERR(base) (BITBAND_ACCESS8(&RCM_SRS1_REG(base), RCM_SRS1_SACKERR_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFC - Reset Pin Filter Control register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFC - Reset Pin Filter Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
+ * other reset types. The bus clock filter is reset when disabled or when entering
+ * stop mode. The LPO filter is reset when disabled or when entering any low
+ * leakage stop mode .
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFC register
+ */
+/*@{*/
+#define RCM_RD_RPFC(base)        (RCM_RPFC_REG(base))
+#define RCM_WR_RPFC(base, value) (RCM_RPFC_REG(base) = (value))
+#define RCM_RMW_RPFC(base, mask, value) (RCM_WR_RPFC(base, (RCM_RD_RPFC(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) |  (value)))
+#define RCM_CLR_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) & ~(value)))
+#define RCM_TOG_RPFC(base, value) (RCM_WR_RPFC(base, RCM_RD_RPFC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFC bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
+ *
+ * Selects how the reset pin filter is enabled in run and wait modes.
+ *
+ * Values:
+ * - 0b00 - All filtering disabled
+ * - 0b01 - Bus clock filter enabled for normal operation
+ * - 0b10 - LPO clock filter enabled for normal operation
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */
+#define RCM_RD_RPFC_RSTFLTSRW(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSRW_MASK) >> RCM_RPFC_RSTFLTSRW_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSRW(base) (RCM_RD_RPFC_RSTFLTSRW(base))
+
+/*! @brief Set the RSTFLTSRW field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSRW(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSRW_MASK, RCM_RPFC_RSTFLTSRW(value)))
+#define RCM_BWR_RPFC_RSTFLTSRW(base, value) (RCM_WR_RPFC_RSTFLTSRW(base, value))
+/*@}*/
+
+/*!
+ * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
+ *
+ * Selects how the reset pin filter is enabled in Stop and VLPS modes
+ *
+ * Values:
+ * - 0b0 - All filtering disabled
+ * - 0b1 - LPO clock filter enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */
+#define RCM_RD_RPFC_RSTFLTSS(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSS_MASK) >> RCM_RPFC_RSTFLTSS_SHIFT)
+#define RCM_BRD_RPFC_RSTFLTSS(base) (BITBAND_ACCESS8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT))
+
+/*! @brief Set the RSTFLTSS field to a new value. */
+#define RCM_WR_RPFC_RSTFLTSS(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSS_MASK, RCM_RPFC_RSTFLTSS(value)))
+#define RCM_BWR_RPFC_RSTFLTSS(base, value) (BITBAND_ACCESS8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_RPFW - Reset Pin Filter Width register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_RPFW - Reset Pin Filter Width register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
+ * They are unaffected by other reset types.
+ */
+/*!
+ * @name Constants and macros for entire RCM_RPFW register
+ */
+/*@{*/
+#define RCM_RD_RPFW(base)        (RCM_RPFW_REG(base))
+#define RCM_WR_RPFW(base, value) (RCM_RPFW_REG(base) = (value))
+#define RCM_RMW_RPFW(base, mask, value) (RCM_WR_RPFW(base, (RCM_RD_RPFW(base) & ~(mask)) | (value)))
+#define RCM_SET_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) |  (value)))
+#define RCM_CLR_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) & ~(value)))
+#define RCM_TOG_RPFW(base, value) (RCM_WR_RPFW(base, RCM_RD_RPFW(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_RPFW bitfields
+ */
+
+/*!
+ * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
+ *
+ * Selects the reset pin bus clock filter width.
+ *
+ * Values:
+ * - 0b00000 - Bus clock filter count is 1
+ * - 0b00001 - Bus clock filter count is 2
+ * - 0b00010 - Bus clock filter count is 3
+ * - 0b00011 - Bus clock filter count is 4
+ * - 0b00100 - Bus clock filter count is 5
+ * - 0b00101 - Bus clock filter count is 6
+ * - 0b00110 - Bus clock filter count is 7
+ * - 0b00111 - Bus clock filter count is 8
+ * - 0b01000 - Bus clock filter count is 9
+ * - 0b01001 - Bus clock filter count is 10
+ * - 0b01010 - Bus clock filter count is 11
+ * - 0b01011 - Bus clock filter count is 12
+ * - 0b01100 - Bus clock filter count is 13
+ * - 0b01101 - Bus clock filter count is 14
+ * - 0b01110 - Bus clock filter count is 15
+ * - 0b01111 - Bus clock filter count is 16
+ * - 0b10000 - Bus clock filter count is 17
+ * - 0b10001 - Bus clock filter count is 18
+ * - 0b10010 - Bus clock filter count is 19
+ * - 0b10011 - Bus clock filter count is 20
+ * - 0b10100 - Bus clock filter count is 21
+ * - 0b10101 - Bus clock filter count is 22
+ * - 0b10110 - Bus clock filter count is 23
+ * - 0b10111 - Bus clock filter count is 24
+ * - 0b11000 - Bus clock filter count is 25
+ * - 0b11001 - Bus clock filter count is 26
+ * - 0b11010 - Bus clock filter count is 27
+ * - 0b11011 - Bus clock filter count is 28
+ * - 0b11100 - Bus clock filter count is 29
+ * - 0b11101 - Bus clock filter count is 30
+ * - 0b11110 - Bus clock filter count is 31
+ * - 0b11111 - Bus clock filter count is 32
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */
+#define RCM_RD_RPFW_RSTFLTSEL(base) ((RCM_RPFW_REG(base) & RCM_RPFW_RSTFLTSEL_MASK) >> RCM_RPFW_RSTFLTSEL_SHIFT)
+#define RCM_BRD_RPFW_RSTFLTSEL(base) (RCM_RD_RPFW_RSTFLTSEL(base))
+
+/*! @brief Set the RSTFLTSEL field to a new value. */
+#define RCM_WR_RPFW_RSTFLTSEL(base, value) (RCM_RMW_RPFW(base, RCM_RPFW_RSTFLTSEL_MASK, RCM_RPFW_RSTFLTSEL(value)))
+#define RCM_BWR_RPFW_RSTFLTSEL(base, value) (RCM_WR_RPFW_RSTFLTSEL(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * RCM_MR - Mode Register
+ ******************************************************************************/
+
+/*!
+ * @brief RCM_MR - Mode Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register includes read-only status flags to indicate the state of the
+ * mode pins during the last Chip Reset.
+ */
+/*!
+ * @name Constants and macros for entire RCM_MR register
+ */
+/*@{*/
+#define RCM_RD_MR(base)          (RCM_MR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RCM_MR bitfields
+ */
+
+/*!
+ * @name Register RCM_MR, field EZP_MS[1] (RO)
+ *
+ * Reflects the state of the EZP_MS pin during the last Chip Reset
+ *
+ * Values:
+ * - 0b0 - Pin deasserted (logic 1)
+ * - 0b1 - Pin asserted (logic 0)
+ */
+/*@{*/
+/*! @brief Read current value of the RCM_MR_EZP_MS field. */
+#define RCM_RD_MR_EZP_MS(base) ((RCM_MR_REG(base) & RCM_MR_EZP_MS_MASK) >> RCM_MR_EZP_MS_SHIFT)
+#define RCM_BRD_MR_EZP_MS(base) (BITBAND_ACCESS8(&RCM_MR_REG(base), RCM_MR_EZP_MS_SHIFT))
+/*@}*/
+
+/*
+ * MK64F12 RFSYS
+ *
+ * System register file
+ *
+ * Registers defined in this header file:
+ * - RFSYS_REG - Register file register
+ */
+
+#define RFSYS_INSTANCE_COUNT (1U) /*!< Number of instances of the RFSYS module. */
+#define RFSYS_IDX (0U) /*!< Instance number for RFSYS. */
+
+/*******************************************************************************
+ * RFSYS_REG - Register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFSYS_REG - Register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFSYS_REG register
+ */
+/*@{*/
+#define RFSYS_RD_REG(base, index) (RFSYS_REG_REG(base, index))
+#define RFSYS_WR_REG(base, index, value) (RFSYS_REG_REG(base, index) = (value))
+#define RFSYS_RMW_REG(base, index, mask, value) (RFSYS_WR_REG(base, index, (RFSYS_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFSYS_SET_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) |  (value)))
+#define RFSYS_CLR_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) & ~(value)))
+#define RFSYS_TOG_REG(base, index, value) (RFSYS_WR_REG(base, index, RFSYS_RD_REG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFSYS_REG bitfields
+ */
+
+/*!
+ * @name Register RFSYS_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LL field. */
+#define RFSYS_RD_REG_LL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LL_MASK) >> RFSYS_REG_LL_SHIFT)
+#define RFSYS_BRD_REG_LL(base, index) (RFSYS_RD_REG_LL(base, index))
+
+/*! @brief Set the LL field to a new value. */
+#define RFSYS_WR_REG_LL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LL_MASK, RFSYS_REG_LL(value)))
+#define RFSYS_BWR_REG_LL(base, index, value) (RFSYS_WR_REG_LL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_LH field. */
+#define RFSYS_RD_REG_LH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_LH_MASK) >> RFSYS_REG_LH_SHIFT)
+#define RFSYS_BRD_REG_LH(base, index) (RFSYS_RD_REG_LH(base, index))
+
+/*! @brief Set the LH field to a new value. */
+#define RFSYS_WR_REG_LH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_LH_MASK, RFSYS_REG_LH(value)))
+#define RFSYS_BWR_REG_LH(base, index, value) (RFSYS_WR_REG_LH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HL field. */
+#define RFSYS_RD_REG_HL(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HL_MASK) >> RFSYS_REG_HL_SHIFT)
+#define RFSYS_BRD_REG_HL(base, index) (RFSYS_RD_REG_HL(base, index))
+
+/*! @brief Set the HL field to a new value. */
+#define RFSYS_WR_REG_HL(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HL_MASK, RFSYS_REG_HL(value)))
+#define RFSYS_BWR_REG_HL(base, index, value) (RFSYS_WR_REG_HL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFSYS_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFSYS_REG_HH field. */
+#define RFSYS_RD_REG_HH(base, index) ((RFSYS_REG_REG(base, index) & RFSYS_REG_HH_MASK) >> RFSYS_REG_HH_SHIFT)
+#define RFSYS_BRD_REG_HH(base, index) (RFSYS_RD_REG_HH(base, index))
+
+/*! @brief Set the HH field to a new value. */
+#define RFSYS_WR_REG_HH(base, index, value) (RFSYS_RMW_REG(base, index, RFSYS_REG_HH_MASK, RFSYS_REG_HH(value)))
+#define RFSYS_BWR_REG_HH(base, index, value) (RFSYS_WR_REG_HH(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 RFVBAT
+ *
+ * VBAT register file
+ *
+ * Registers defined in this header file:
+ * - RFVBAT_REG - VBAT register file register
+ */
+
+#define RFVBAT_INSTANCE_COUNT (1U) /*!< Number of instances of the RFVBAT module. */
+#define RFVBAT_IDX (0U) /*!< Instance number for RFVBAT. */
+
+/*******************************************************************************
+ * RFVBAT_REG - VBAT register file register
+ ******************************************************************************/
+
+/*!
+ * @brief RFVBAT_REG - VBAT register file register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Each register can be accessed as 8-, 16-, or 32-bits.
+ */
+/*!
+ * @name Constants and macros for entire RFVBAT_REG register
+ */
+/*@{*/
+#define RFVBAT_RD_REG(base, index) (RFVBAT_REG_REG(base, index))
+#define RFVBAT_WR_REG(base, index, value) (RFVBAT_REG_REG(base, index) = (value))
+#define RFVBAT_RMW_REG(base, index, mask, value) (RFVBAT_WR_REG(base, index, (RFVBAT_RD_REG(base, index) & ~(mask)) | (value)))
+#define RFVBAT_SET_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) |  (value)))
+#define RFVBAT_CLR_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) & ~(value)))
+#define RFVBAT_TOG_REG(base, index, value) (RFVBAT_WR_REG(base, index, RFVBAT_RD_REG(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RFVBAT_REG bitfields
+ */
+
+/*!
+ * @name Register RFVBAT_REG, field LL[7:0] (RW)
+ *
+ * Low lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_LL field. */
+#define RFVBAT_RD_REG_LL(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_LL_MASK) >> RFVBAT_REG_LL_SHIFT)
+#define RFVBAT_BRD_REG_LL(base, index) (RFVBAT_RD_REG_LL(base, index))
+
+/*! @brief Set the LL field to a new value. */
+#define RFVBAT_WR_REG_LL(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_LL_MASK, RFVBAT_REG_LL(value)))
+#define RFVBAT_BWR_REG_LL(base, index, value) (RFVBAT_WR_REG_LL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field LH[15:8] (RW)
+ *
+ * Low higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_LH field. */
+#define RFVBAT_RD_REG_LH(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_LH_MASK) >> RFVBAT_REG_LH_SHIFT)
+#define RFVBAT_BRD_REG_LH(base, index) (RFVBAT_RD_REG_LH(base, index))
+
+/*! @brief Set the LH field to a new value. */
+#define RFVBAT_WR_REG_LH(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_LH_MASK, RFVBAT_REG_LH(value)))
+#define RFVBAT_BWR_REG_LH(base, index, value) (RFVBAT_WR_REG_LH(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field HL[23:16] (RW)
+ *
+ * High lower byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_HL field. */
+#define RFVBAT_RD_REG_HL(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_HL_MASK) >> RFVBAT_REG_HL_SHIFT)
+#define RFVBAT_BRD_REG_HL(base, index) (RFVBAT_RD_REG_HL(base, index))
+
+/*! @brief Set the HL field to a new value. */
+#define RFVBAT_WR_REG_HL(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_HL_MASK, RFVBAT_REG_HL(value)))
+#define RFVBAT_BWR_REG_HL(base, index, value) (RFVBAT_WR_REG_HL(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register RFVBAT_REG, field HH[31:24] (RW)
+ *
+ * High higher byte
+ */
+/*@{*/
+/*! @brief Read current value of the RFVBAT_REG_HH field. */
+#define RFVBAT_RD_REG_HH(base, index) ((RFVBAT_REG_REG(base, index) & RFVBAT_REG_HH_MASK) >> RFVBAT_REG_HH_SHIFT)
+#define RFVBAT_BRD_REG_HH(base, index) (RFVBAT_RD_REG_HH(base, index))
+
+/*! @brief Set the HH field to a new value. */
+#define RFVBAT_WR_REG_HH(base, index, value) (RFVBAT_RMW_REG(base, index, RFVBAT_REG_HH_MASK, RFVBAT_REG_HH(value)))
+#define RFVBAT_BWR_REG_HH(base, index, value) (RFVBAT_WR_REG_HH(base, index, value))
+/*@}*/
+
+/*
+ * MK64F12 RNG
+ *
+ * Random Number Generator Accelerator
+ *
+ * Registers defined in this header file:
+ * - RNG_CR - RNGA Control Register
+ * - RNG_SR - RNGA Status Register
+ * - RNG_ER - RNGA Entropy Register
+ * - RNG_OR - RNGA Output Register
+ */
+
+#define RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
+#define RNG_IDX (0U) /*!< Instance number for RNG. */
+
+/*******************************************************************************
+ * RNG_CR - RNGA Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_CR - RNGA Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the operation of RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_CR register
+ */
+/*@{*/
+#define RNG_RD_CR(base)          (RNG_CR_REG(base))
+#define RNG_WR_CR(base, value)   (RNG_CR_REG(base) = (value))
+#define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value)))
+#define RNG_SET_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) |  (value)))
+#define RNG_CLR_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) & ~(value)))
+#define RNG_TOG_CR(base, value)  (RNG_WR_CR(base, RNG_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RNG_CR bitfields
+ */
+
+/*!
+ * @name Register RNG_CR, field GO[0] (RW)
+ *
+ * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
+ * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
+ * OR[RANDOUT] with data.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_GO field. */
+#define RNG_RD_CR_GO(base)   ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT)
+#define RNG_BRD_CR_GO(base)  (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_GO_SHIFT))
+
+/*! @brief Set the GO field to a new value. */
+#define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value)))
+#define RNG_BWR_CR_GO(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_GO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field HA[1] (RW)
+ *
+ * Enables notification of security violations (via SR[SECV]). A security
+ * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
+ * After enabling notification of security violations, you must reset RNGA to
+ * disable them again.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_HA field. */
+#define RNG_RD_CR_HA(base)   ((RNG_CR_REG(base) & RNG_CR_HA_MASK) >> RNG_CR_HA_SHIFT)
+#define RNG_BRD_CR_HA(base)  (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_HA_SHIFT))
+
+/*! @brief Set the HA field to a new value. */
+#define RNG_WR_CR_HA(base, value) (RNG_RMW_CR(base, RNG_CR_HA_MASK, RNG_CR_HA(value)))
+#define RNG_BWR_CR_HA(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_HA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field INTM[2] (RW)
+ *
+ * Masks the triggering of an error interrupt to the interrupt controller when
+ * an OR underflow condition occurs. An OR underflow condition occurs when you
+ * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
+ *
+ * Values:
+ * - 0b0 - Not masked
+ * - 0b1 - Masked
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_INTM field. */
+#define RNG_RD_CR_INTM(base) ((RNG_CR_REG(base) & RNG_CR_INTM_MASK) >> RNG_CR_INTM_SHIFT)
+#define RNG_BRD_CR_INTM(base) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_INTM_SHIFT))
+
+/*! @brief Set the INTM field to a new value. */
+#define RNG_WR_CR_INTM(base, value) (RNG_RMW_CR(base, RNG_CR_INTM_MASK, RNG_CR_INTM(value)))
+#define RNG_BWR_CR_INTM(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_INTM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field CLRI[3] (WORZ)
+ *
+ * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
+ *
+ * Values:
+ * - 0b0 - Do not clear the interrupt.
+ * - 0b1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
+ *     the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
+ */
+/*@{*/
+/*! @brief Set the CLRI field to a new value. */
+#define RNG_WR_CR_CLRI(base, value) (RNG_RMW_CR(base, RNG_CR_CLRI_MASK, RNG_CR_CLRI(value)))
+#define RNG_BWR_CR_CLRI(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_CLRI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field SLP[4] (RW)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_SLP field. */
+#define RNG_RD_CR_SLP(base)  ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT)
+#define RNG_BRD_CR_SLP(base) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_SLP_SHIFT))
+
+/*! @brief Set the SLP field to a new value. */
+#define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value)))
+#define RNG_BWR_CR_SLP(base, value) (BITBAND_ACCESS32(&RNG_CR_REG(base), RNG_CR_SLP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_SR - RNGA Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_SR - RNGA Status Register (RO)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Indicates the status of RNGA. This register is read-only.
+ */
+/*!
+ * @name Constants and macros for entire RNG_SR register
+ */
+/*@{*/
+#define RNG_RD_SR(base)          (RNG_SR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual RNG_SR bitfields
+ */
+
+/*!
+ * @name Register RNG_SR, field SECV[0] (RO)
+ *
+ * Used only when high assurance is enabled (CR[HA]). Indicates that a security
+ * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
+ * RNGA.
+ *
+ * Values:
+ * - 0b0 - No security violation
+ * - 0b1 - Security violation
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SECV field. */
+#define RNG_RD_SR_SECV(base) ((RNG_SR_REG(base) & RNG_SR_SECV_MASK) >> RNG_SR_SECV_SHIFT)
+#define RNG_BRD_SR_SECV(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_SECV_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field LRS[1] (RO)
+ *
+ * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
+ * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
+ * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
+ * After you read this register, RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_LRS field. */
+#define RNG_RD_SR_LRS(base)  ((RNG_SR_REG(base) & RNG_SR_LRS_MASK) >> RNG_SR_LRS_SHIFT)
+#define RNG_BRD_SR_LRS(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_LRS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field ORU[2] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last read
+ * this register (SR) or RNGA was reset, regardless of whether the error
+ * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
+ * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
+ * field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_ORU field. */
+#define RNG_RD_SR_ORU(base)  ((RNG_SR_REG(base) & RNG_SR_ORU_MASK) >> RNG_SR_ORU_SHIFT)
+#define RNG_BRD_SR_ORU(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_ORU_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field ERRI[3] (RO)
+ *
+ * Indicates whether an OR underflow condition has occurred since you last
+ * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
+ * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
+ * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
+ * indicator (via CR[CLRI]), RNGA writes 0 to this field.
+ *
+ * Values:
+ * - 0b0 - No underflow
+ * - 0b1 - Underflow
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_ERRI field. */
+#define RNG_RD_SR_ERRI(base) ((RNG_SR_REG(base) & RNG_SR_ERRI_MASK) >> RNG_SR_ERRI_SHIFT)
+#define RNG_BRD_SR_ERRI(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_ERRI_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field SLP[4] (RO)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SLP field. */
+#define RNG_RD_SR_SLP(base)  ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT)
+#define RNG_BRD_SR_SLP(base) (BITBAND_ACCESS32(&RNG_SR_REG(base), RNG_SR_SLP_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
+ *
+ * Indicates the number of random-data words that are in OR[RANDOUT], which
+ * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
+ * is not 0, then the contents of a random number contained in OR[RANDOUT] are
+ * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
+ *
+ * Values:
+ * - 0b00000000 - No words (empty)
+ * - 0b00000001 - One word (valid)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_LVL field. */
+#define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT)
+#define RNG_BRD_SR_OREG_LVL(base) (RNG_RD_SR_OREG_LVL(base))
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
+ *
+ * Indicates the size of the Output (OR) register in terms of the number of
+ * 32-bit random-data words it can hold.
+ *
+ * Values:
+ * - 0b00000001 - One word (this value is fixed)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
+#define RNG_RD_SR_OREG_SIZE(base) ((RNG_SR_REG(base) & RNG_SR_OREG_SIZE_MASK) >> RNG_SR_OREG_SIZE_SHIFT)
+#define RNG_BRD_SR_OREG_SIZE(base) (RNG_RD_SR_OREG_SIZE(base))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_ER - RNGA Entropy Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_ER - RNGA Entropy Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies an entropy value that RNGA uses in addition to its ring oscillators
+ * to seed its pseudorandom algorithm. This is a write-only register; reads
+ * return all zeros.
+ */
+/*!
+ * @name Constants and macros for entire RNG_ER register
+ */
+/*@{*/
+#define RNG_RD_ER(base)          (RNG_ER_REG(base))
+#define RNG_WR_ER(base, value)   (RNG_ER_REG(base) = (value))
+#define RNG_RMW_ER(base, mask, value) (RNG_WR_ER(base, (RNG_RD_ER(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_OR - RNGA Output Register
+ ******************************************************************************/
+
+/*!
+ * @brief RNG_OR - RNGA Output Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Stores a random-data word generated by RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_OR register
+ */
+/*@{*/
+#define RNG_RD_OR(base)          (RNG_OR_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 RTC
+ *
+ * Secure Real Time Clock
+ *
+ * Registers defined in this header file:
+ * - RTC_TSR - RTC Time Seconds Register
+ * - RTC_TPR - RTC Time Prescaler Register
+ * - RTC_TAR - RTC Time Alarm Register
+ * - RTC_TCR - RTC Time Compensation Register
+ * - RTC_CR - RTC Control Register
+ * - RTC_SR - RTC Status Register
+ * - RTC_LR - RTC Lock Register
+ * - RTC_IER - RTC Interrupt Enable Register
+ * - RTC_WAR - RTC Write Access Register
+ * - RTC_RAR - RTC Read Access Register
+ */
+
+#define RTC_INSTANCE_COUNT (1U) /*!< Number of instances of the RTC module. */
+#define RTC_IDX (0U) /*!< Instance number for RTC. */
+
+/*******************************************************************************
+ * RTC_TSR - RTC Time Seconds Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TSR - RTC Time Seconds Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TSR register
+ */
+/*@{*/
+#define RTC_RD_TSR(base)         (RTC_TSR_REG(base))
+#define RTC_WR_TSR(base, value)  (RTC_TSR_REG(base) = (value))
+#define RTC_RMW_TSR(base, mask, value) (RTC_WR_TSR(base, (RTC_RD_TSR(base) & ~(mask)) | (value)))
+#define RTC_SET_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) |  (value)))
+#define RTC_CLR_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) & ~(value)))
+#define RTC_TOG_TSR(base, value) (RTC_WR_TSR(base, RTC_RD_TSR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TPR - RTC Time Prescaler Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TPR - RTC Time Prescaler Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TPR register
+ */
+/*@{*/
+#define RTC_RD_TPR(base)         (RTC_TPR_REG(base))
+#define RTC_WR_TPR(base, value)  (RTC_TPR_REG(base) = (value))
+#define RTC_RMW_TPR(base, mask, value) (RTC_WR_TPR(base, (RTC_RD_TPR(base) & ~(mask)) | (value)))
+#define RTC_SET_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) |  (value)))
+#define RTC_CLR_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) & ~(value)))
+#define RTC_TOG_TPR(base, value) (RTC_WR_TPR(base, RTC_RD_TPR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TPR bitfields
+ */
+
+/*!
+ * @name Register RTC_TPR, field TPR[15:0] (RW)
+ *
+ * When the time counter is enabled, the TPR is read only and increments every
+ * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
+ * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
+ * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
+ * to a logic zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TPR_TPR field. */
+#define RTC_RD_TPR_TPR(base) ((RTC_TPR_REG(base) & RTC_TPR_TPR_MASK) >> RTC_TPR_TPR_SHIFT)
+#define RTC_BRD_TPR_TPR(base) (RTC_RD_TPR_TPR(base))
+
+/*! @brief Set the TPR field to a new value. */
+#define RTC_WR_TPR_TPR(base, value) (RTC_RMW_TPR(base, RTC_TPR_TPR_MASK, RTC_TPR_TPR(value)))
+#define RTC_BWR_TPR_TPR(base, value) (RTC_WR_TPR_TPR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TAR - RTC Time Alarm Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TAR - RTC Time Alarm Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TAR register
+ */
+/*@{*/
+#define RTC_RD_TAR(base)         (RTC_TAR_REG(base))
+#define RTC_WR_TAR(base, value)  (RTC_TAR_REG(base) = (value))
+#define RTC_RMW_TAR(base, mask, value) (RTC_WR_TAR(base, (RTC_RD_TAR(base) & ~(mask)) | (value)))
+#define RTC_SET_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) |  (value)))
+#define RTC_CLR_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) & ~(value)))
+#define RTC_TOG_TAR(base, value) (RTC_WR_TAR(base, RTC_RD_TAR(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_TCR - RTC Time Compensation Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_TCR - RTC Time Compensation Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_TCR register
+ */
+/*@{*/
+#define RTC_RD_TCR(base)         (RTC_TCR_REG(base))
+#define RTC_WR_TCR(base, value)  (RTC_TCR_REG(base) = (value))
+#define RTC_RMW_TCR(base, mask, value) (RTC_WR_TCR(base, (RTC_RD_TCR(base) & ~(mask)) | (value)))
+#define RTC_SET_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) |  (value)))
+#define RTC_CLR_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) & ~(value)))
+#define RTC_TOG_TCR(base, value) (RTC_WR_TCR(base, RTC_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_TCR bitfields
+ */
+
+/*!
+ * @name Register RTC_TCR, field TCR[7:0] (RW)
+ *
+ * Configures the number of 32.768 kHz clock cycles in each second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ *
+ * Values:
+ * - 0b10000000 - Time Prescaler Register overflows every 32896 clock cycles.
+ * - 0b11111111 - Time Prescaler Register overflows every 32769 clock cycles.
+ * - 0b00000000 - Time Prescaler Register overflows every 32768 clock cycles.
+ * - 0b00000001 - Time Prescaler Register overflows every 32767 clock cycles.
+ * - 0b01111111 - Time Prescaler Register overflows every 32641 clock cycles.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCR field. */
+#define RTC_RD_TCR_TCR(base) ((RTC_TCR_REG(base) & RTC_TCR_TCR_MASK) >> RTC_TCR_TCR_SHIFT)
+#define RTC_BRD_TCR_TCR(base) (RTC_RD_TCR_TCR(base))
+
+/*! @brief Set the TCR field to a new value. */
+#define RTC_WR_TCR_TCR(base, value) (RTC_RMW_TCR(base, RTC_TCR_TCR_MASK, RTC_TCR_TCR(value)))
+#define RTC_BWR_TCR_TCR(base, value) (RTC_WR_TCR_TCR(base, value))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIR[15:8] (RW)
+ *
+ * Configures the compensation interval in seconds from 1 to 256 to control how
+ * frequently the TCR should adjust the number of 32.768 kHz cycles in each
+ * second. The value written should be one less than the number of seconds. For
+ * example, write zero to configure for a compensation interval of one second. This
+ * register is double buffered and writes do not take affect until the end of the
+ * current compensation interval.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIR field. */
+#define RTC_RD_TCR_CIR(base) ((RTC_TCR_REG(base) & RTC_TCR_CIR_MASK) >> RTC_TCR_CIR_SHIFT)
+#define RTC_BRD_TCR_CIR(base) (RTC_RD_TCR_CIR(base))
+
+/*! @brief Set the CIR field to a new value. */
+#define RTC_WR_TCR_CIR(base, value) (RTC_RMW_TCR(base, RTC_TCR_CIR_MASK, RTC_TCR_CIR(value)))
+#define RTC_BWR_TCR_CIR(base, value) (RTC_WR_TCR_CIR(base, value))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field TCV[23:16] (RO)
+ *
+ * Current value used by the compensation logic for the present second interval.
+ * Updated once a second if the CIC equals 0 with the contents of the TCR field.
+ * If the CIC does not equal zero then it is loaded with zero (compensation is
+ * not enabled for that second increment).
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_TCV field. */
+#define RTC_RD_TCR_TCV(base) ((RTC_TCR_REG(base) & RTC_TCR_TCV_MASK) >> RTC_TCR_TCV_SHIFT)
+#define RTC_BRD_TCR_TCV(base) (RTC_RD_TCR_TCV(base))
+/*@}*/
+
+/*!
+ * @name Register RTC_TCR, field CIC[31:24] (RO)
+ *
+ * Current value of the compensation interval counter. If the compensation
+ * interval counter equals zero then it is loaded with the contents of the CIR. If the
+ * CIC does not equal zero then it is decremented once a second.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_TCR_CIC field. */
+#define RTC_RD_TCR_CIC(base) ((RTC_TCR_REG(base) & RTC_TCR_CIC_MASK) >> RTC_TCR_CIC_SHIFT)
+#define RTC_BRD_TCR_CIC(base) (RTC_RD_TCR_CIC(base))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_CR - RTC Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_CR - RTC Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire RTC_CR register
+ */
+/*@{*/
+#define RTC_RD_CR(base)          (RTC_CR_REG(base))
+#define RTC_WR_CR(base, value)   (RTC_CR_REG(base) = (value))
+#define RTC_RMW_CR(base, mask, value) (RTC_WR_CR(base, (RTC_RD_CR(base) & ~(mask)) | (value)))
+#define RTC_SET_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) |  (value)))
+#define RTC_CLR_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) & ~(value)))
+#define RTC_TOG_CR(base, value)  (RTC_WR_CR(base, RTC_RD_CR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_CR bitfields
+ */
+
+/*!
+ * @name Register RTC_CR, field SWR[0] (RW)
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
+ *     RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
+ *     explicitly clearing it.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SWR field. */
+#define RTC_RD_CR_SWR(base)  ((RTC_CR_REG(base) & RTC_CR_SWR_MASK) >> RTC_CR_SWR_SHIFT)
+#define RTC_BRD_CR_SWR(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT))
+
+/*! @brief Set the SWR field to a new value. */
+#define RTC_WR_CR_SWR(base, value) (RTC_RMW_CR(base, RTC_CR_SWR_MASK, RTC_CR_SWR(value)))
+#define RTC_BWR_CR_SWR(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPE[1] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0b0 - Wakeup pin is disabled.
+ * - 0b1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPE field. */
+#define RTC_RD_CR_WPE(base)  ((RTC_CR_REG(base) & RTC_CR_WPE_MASK) >> RTC_CR_WPE_SHIFT)
+#define RTC_BRD_CR_WPE(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT))
+
+/*! @brief Set the WPE field to a new value. */
+#define RTC_WR_CR_WPE(base, value) (RTC_RMW_CR(base, RTC_CR_WPE_MASK, RTC_CR_WPE(value)))
+#define RTC_BWR_CR_WPE(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SUP[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Non-supervisor mode write accesses are not supported and generate a
+ *     bus error.
+ * - 0b1 - Non-supervisor mode write accesses are supported.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SUP field. */
+#define RTC_RD_CR_SUP(base)  ((RTC_CR_REG(base) & RTC_CR_SUP_MASK) >> RTC_CR_SUP_SHIFT)
+#define RTC_BRD_CR_SUP(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT))
+
+/*! @brief Set the SUP field to a new value. */
+#define RTC_WR_CR_SUP(base, value) (RTC_RMW_CR(base, RTC_CR_SUP_MASK, RTC_CR_SUP(value)))
+#define RTC_BWR_CR_SUP(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field UM[3] (RW)
+ *
+ * Allows SR[TCE] to be written even when the Status Register is locked. When
+ * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
+ * the SR[TCE] is clear.
+ *
+ * Values:
+ * - 0b0 - Registers cannot be written when locked.
+ * - 0b1 - Registers can be written when locked under limited conditions.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_UM field. */
+#define RTC_RD_CR_UM(base)   ((RTC_CR_REG(base) & RTC_CR_UM_MASK) >> RTC_CR_UM_SHIFT)
+#define RTC_BRD_CR_UM(base)  (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT))
+
+/*! @brief Set the UM field to a new value. */
+#define RTC_WR_CR_UM(base, value) (RTC_RMW_CR(base, RTC_CR_UM_MASK, RTC_CR_UM(value)))
+#define RTC_BWR_CR_UM(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field WPS[4] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices.
+ *
+ * Values:
+ * - 0b0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
+ *     asserts or the wakeup pin is turned on.
+ * - 0b1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup
+ *     pin is turned on and the 32kHz clock is output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_WPS field. */
+#define RTC_RD_CR_WPS(base)  ((RTC_CR_REG(base) & RTC_CR_WPS_MASK) >> RTC_CR_WPS_SHIFT)
+#define RTC_BRD_CR_WPS(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT))
+
+/*! @brief Set the WPS field to a new value. */
+#define RTC_WR_CR_WPS(base, value) (RTC_RMW_CR(base, RTC_CR_WPS_MASK, RTC_CR_WPS(value)))
+#define RTC_BWR_CR_WPS(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field OSCE[8] (RW)
+ *
+ * Values:
+ * - 0b0 - 32.768 kHz oscillator is disabled.
+ * - 0b1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
+ *     oscillator startup time before enabling the time counter to allow the 32.768
+ *     kHz clock time to stabilize.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_OSCE field. */
+#define RTC_RD_CR_OSCE(base) ((RTC_CR_REG(base) & RTC_CR_OSCE_MASK) >> RTC_CR_OSCE_SHIFT)
+#define RTC_BRD_CR_OSCE(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT))
+
+/*! @brief Set the OSCE field to a new value. */
+#define RTC_WR_CR_OSCE(base, value) (RTC_RMW_CR(base, RTC_CR_OSCE_MASK, RTC_CR_OSCE(value)))
+#define RTC_BWR_CR_OSCE(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field CLKO[9] (RW)
+ *
+ * Values:
+ * - 0b0 - The 32 kHz clock is output to other peripherals.
+ * - 0b1 - The 32 kHz clock is not output to other peripherals.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_CLKO field. */
+#define RTC_RD_CR_CLKO(base) ((RTC_CR_REG(base) & RTC_CR_CLKO_MASK) >> RTC_CR_CLKO_SHIFT)
+#define RTC_BRD_CR_CLKO(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT))
+
+/*! @brief Set the CLKO field to a new value. */
+#define RTC_WR_CR_CLKO(base, value) (RTC_RMW_CR(base, RTC_CR_CLKO_MASK, RTC_CR_CLKO(value)))
+#define RTC_BWR_CR_CLKO(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC16P[10] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC16P field. */
+#define RTC_RD_CR_SC16P(base) ((RTC_CR_REG(base) & RTC_CR_SC16P_MASK) >> RTC_CR_SC16P_SHIFT)
+#define RTC_BRD_CR_SC16P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT))
+
+/*! @brief Set the SC16P field to a new value. */
+#define RTC_WR_CR_SC16P(base, value) (RTC_RMW_CR(base, RTC_CR_SC16P_MASK, RTC_CR_SC16P(value)))
+#define RTC_BWR_CR_SC16P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC8P[11] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC8P field. */
+#define RTC_RD_CR_SC8P(base) ((RTC_CR_REG(base) & RTC_CR_SC8P_MASK) >> RTC_CR_SC8P_SHIFT)
+#define RTC_BRD_CR_SC8P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT))
+
+/*! @brief Set the SC8P field to a new value. */
+#define RTC_WR_CR_SC8P(base, value) (RTC_RMW_CR(base, RTC_CR_SC8P_MASK, RTC_CR_SC8P(value)))
+#define RTC_BWR_CR_SC8P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC4P[12] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC4P field. */
+#define RTC_RD_CR_SC4P(base) ((RTC_CR_REG(base) & RTC_CR_SC4P_MASK) >> RTC_CR_SC4P_SHIFT)
+#define RTC_BRD_CR_SC4P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT))
+
+/*! @brief Set the SC4P field to a new value. */
+#define RTC_WR_CR_SC4P(base, value) (RTC_RMW_CR(base, RTC_CR_SC4P_MASK, RTC_CR_SC4P(value)))
+#define RTC_BWR_CR_SC4P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_CR, field SC2P[13] (RW)
+ *
+ * Values:
+ * - 0b0 - Disable the load.
+ * - 0b1 - Enable the additional load.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_CR_SC2P field. */
+#define RTC_RD_CR_SC2P(base) ((RTC_CR_REG(base) & RTC_CR_SC2P_MASK) >> RTC_CR_SC2P_SHIFT)
+#define RTC_BRD_CR_SC2P(base) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT))
+
+/*! @brief Set the SC2P field to a new value. */
+#define RTC_WR_CR_SC2P(base, value) (RTC_RMW_CR(base, RTC_CR_SC2P_MASK, RTC_CR_SC2P(value)))
+#define RTC_BWR_CR_SC2P(base, value) (BITBAND_ACCESS32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_SR - RTC Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_SR - RTC Status Register (RW)
+ *
+ * Reset value: 0x00000001U
+ */
+/*!
+ * @name Constants and macros for entire RTC_SR register
+ */
+/*@{*/
+#define RTC_RD_SR(base)          (RTC_SR_REG(base))
+#define RTC_WR_SR(base, value)   (RTC_SR_REG(base) = (value))
+#define RTC_RMW_SR(base, mask, value) (RTC_WR_SR(base, (RTC_RD_SR(base) & ~(mask)) | (value)))
+#define RTC_SET_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) |  (value)))
+#define RTC_CLR_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) & ~(value)))
+#define RTC_TOG_SR(base, value)  (RTC_WR_SR(base, RTC_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_SR bitfields
+ */
+
+/*!
+ * @name Register RTC_SR, field TIF[0] (RO)
+ *
+ * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
+ * do not increment and read as zero when this bit is set. This bit is cleared by
+ * writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0b0 - Time is valid.
+ * - 0b1 - Time is invalid and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TIF field. */
+#define RTC_RD_SR_TIF(base)  ((RTC_SR_REG(base) & RTC_SR_TIF_MASK) >> RTC_SR_TIF_SHIFT)
+#define RTC_BRD_SR_TIF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TIF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TOF[1] (RO)
+ *
+ * Time overflow flag is set when the time counter is enabled and overflows. The
+ * TSR and TPR do not increment and read as zero when this bit is set. This bit
+ * is cleared by writing the TSR register when the time counter is disabled.
+ *
+ * Values:
+ * - 0b0 - Time overflow has not occurred.
+ * - 0b1 - Time overflow has occurred and time counter is read as zero.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TOF field. */
+#define RTC_RD_SR_TOF(base)  ((RTC_SR_REG(base) & RTC_SR_TOF_MASK) >> RTC_SR_TOF_SHIFT)
+#define RTC_BRD_SR_TOF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TOF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TAF[2] (RO)
+ *
+ * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
+ * increments. This bit is cleared by writing the TAR register.
+ *
+ * Values:
+ * - 0b0 - Time alarm has not occurred.
+ * - 0b1 - Time alarm has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TAF field. */
+#define RTC_RD_SR_TAF(base)  ((RTC_SR_REG(base) & RTC_SR_TAF_MASK) >> RTC_SR_TAF_SHIFT)
+#define RTC_BRD_SR_TAF(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TAF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register RTC_SR, field TCE[4] (RW)
+ *
+ * When time counter is disabled the TSR register and TPR register are
+ * writeable, but do not increment. When time counter is enabled the TSR register and TPR
+ * register are not writeable, but increment.
+ *
+ * Values:
+ * - 0b0 - Time counter is disabled.
+ * - 0b1 - Time counter is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_SR_TCE field. */
+#define RTC_RD_SR_TCE(base)  ((RTC_SR_REG(base) & RTC_SR_TCE_MASK) >> RTC_SR_TCE_SHIFT)
+#define RTC_BRD_SR_TCE(base) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT))
+
+/*! @brief Set the TCE field to a new value. */
+#define RTC_WR_SR_TCE(base, value) (RTC_RMW_SR(base, RTC_SR_TCE_MASK, RTC_SR_TCE(value)))
+#define RTC_BWR_SR_TCE(base, value) (BITBAND_ACCESS32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_LR - RTC Lock Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_LR - RTC Lock Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_LR register
+ */
+/*@{*/
+#define RTC_RD_LR(base)          (RTC_LR_REG(base))
+#define RTC_WR_LR(base, value)   (RTC_LR_REG(base) = (value))
+#define RTC_RMW_LR(base, mask, value) (RTC_WR_LR(base, (RTC_RD_LR(base) & ~(mask)) | (value)))
+#define RTC_SET_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) |  (value)))
+#define RTC_CLR_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) & ~(value)))
+#define RTC_TOG_LR(base, value)  (RTC_WR_LR(base, RTC_RD_LR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_LR bitfields
+ */
+
+/*!
+ * @name Register RTC_LR, field TCL[3] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Time Compensation Register is locked and writes are ignored.
+ * - 0b1 - Time Compensation Register is not locked and writes complete as
+ *     normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_TCL field. */
+#define RTC_RD_LR_TCL(base)  ((RTC_LR_REG(base) & RTC_LR_TCL_MASK) >> RTC_LR_TCL_SHIFT)
+#define RTC_BRD_LR_TCL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT))
+
+/*! @brief Set the TCL field to a new value. */
+#define RTC_WR_LR_TCL(base, value) (RTC_RMW_LR(base, RTC_LR_TCL_MASK, RTC_LR_TCL(value)))
+#define RTC_BWR_LR_TCL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field CRL[4] (RW)
+ *
+ * After being cleared, this bit can only be set by VBAT POR.
+ *
+ * Values:
+ * - 0b0 - Control Register is locked and writes are ignored.
+ * - 0b1 - Control Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_CRL field. */
+#define RTC_RD_LR_CRL(base)  ((RTC_LR_REG(base) & RTC_LR_CRL_MASK) >> RTC_LR_CRL_SHIFT)
+#define RTC_BRD_LR_CRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT))
+
+/*! @brief Set the CRL field to a new value. */
+#define RTC_WR_LR_CRL(base, value) (RTC_RMW_LR(base, RTC_LR_CRL_MASK, RTC_LR_CRL(value)))
+#define RTC_BWR_LR_CRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field SRL[5] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Status Register is locked and writes are ignored.
+ * - 0b1 - Status Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_SRL field. */
+#define RTC_RD_LR_SRL(base)  ((RTC_LR_REG(base) & RTC_LR_SRL_MASK) >> RTC_LR_SRL_SHIFT)
+#define RTC_BRD_LR_SRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT))
+
+/*! @brief Set the SRL field to a new value. */
+#define RTC_WR_LR_SRL(base, value) (RTC_RMW_LR(base, RTC_LR_SRL_MASK, RTC_LR_SRL(value)))
+#define RTC_BWR_LR_SRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_LR, field LRL[6] (RW)
+ *
+ * After being cleared, this bit can be set only by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Lock Register is locked and writes are ignored.
+ * - 0b1 - Lock Register is not locked and writes complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_LR_LRL field. */
+#define RTC_RD_LR_LRL(base)  ((RTC_LR_REG(base) & RTC_LR_LRL_MASK) >> RTC_LR_LRL_SHIFT)
+#define RTC_BRD_LR_LRL(base) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT))
+
+/*! @brief Set the LRL field to a new value. */
+#define RTC_WR_LR_LRL(base, value) (RTC_RMW_LR(base, RTC_LR_LRL_MASK, RTC_LR_LRL(value)))
+#define RTC_BWR_LR_LRL(base, value) (BITBAND_ACCESS32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_IER - RTC Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_IER - RTC Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00000007U
+ */
+/*!
+ * @name Constants and macros for entire RTC_IER register
+ */
+/*@{*/
+#define RTC_RD_IER(base)         (RTC_IER_REG(base))
+#define RTC_WR_IER(base, value)  (RTC_IER_REG(base) = (value))
+#define RTC_RMW_IER(base, mask, value) (RTC_WR_IER(base, (RTC_RD_IER(base) & ~(mask)) | (value)))
+#define RTC_SET_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) |  (value)))
+#define RTC_CLR_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) & ~(value)))
+#define RTC_TOG_IER(base, value) (RTC_WR_IER(base, RTC_RD_IER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_IER bitfields
+ */
+
+/*!
+ * @name Register RTC_IER, field TIIE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Time invalid flag does not generate an interrupt.
+ * - 0b1 - Time invalid flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TIIE field. */
+#define RTC_RD_IER_TIIE(base) ((RTC_IER_REG(base) & RTC_IER_TIIE_MASK) >> RTC_IER_TIIE_SHIFT)
+#define RTC_BRD_IER_TIIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT))
+
+/*! @brief Set the TIIE field to a new value. */
+#define RTC_WR_IER_TIIE(base, value) (RTC_RMW_IER(base, RTC_IER_TIIE_MASK, RTC_IER_TIIE(value)))
+#define RTC_BWR_IER_TIIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TOIE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Time overflow flag does not generate an interrupt.
+ * - 0b1 - Time overflow flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TOIE field. */
+#define RTC_RD_IER_TOIE(base) ((RTC_IER_REG(base) & RTC_IER_TOIE_MASK) >> RTC_IER_TOIE_SHIFT)
+#define RTC_BRD_IER_TOIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT))
+
+/*! @brief Set the TOIE field to a new value. */
+#define RTC_WR_IER_TOIE(base, value) (RTC_RMW_IER(base, RTC_IER_TOIE_MASK, RTC_IER_TOIE(value)))
+#define RTC_BWR_IER_TOIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TAIE[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Time alarm flag does not generate an interrupt.
+ * - 0b1 - Time alarm flag does generate an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TAIE field. */
+#define RTC_RD_IER_TAIE(base) ((RTC_IER_REG(base) & RTC_IER_TAIE_MASK) >> RTC_IER_TAIE_SHIFT)
+#define RTC_BRD_IER_TAIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT))
+
+/*! @brief Set the TAIE field to a new value. */
+#define RTC_WR_IER_TAIE(base, value) (RTC_RMW_IER(base, RTC_IER_TAIE_MASK, RTC_IER_TAIE(value)))
+#define RTC_BWR_IER_TAIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field TSIE[4] (RW)
+ *
+ * The seconds interrupt is an edge-sensitive interrupt with a dedicated
+ * interrupt vector. It is generated once a second and requires no software overhead
+ * (there is no corresponding status flag to clear).
+ *
+ * Values:
+ * - 0b0 - Seconds interrupt is disabled.
+ * - 0b1 - Seconds interrupt is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_TSIE field. */
+#define RTC_RD_IER_TSIE(base) ((RTC_IER_REG(base) & RTC_IER_TSIE_MASK) >> RTC_IER_TSIE_SHIFT)
+#define RTC_BRD_IER_TSIE(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT))
+
+/*! @brief Set the TSIE field to a new value. */
+#define RTC_WR_IER_TSIE(base, value) (RTC_RMW_IER(base, RTC_IER_TSIE_MASK, RTC_IER_TSIE(value)))
+#define RTC_BWR_IER_TSIE(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_IER, field WPON[7] (RW)
+ *
+ * The wakeup pin is optional and not available on all devices. Whenever the
+ * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - If the wakeup pin is enabled, then the wakeup pin will assert.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_IER_WPON field. */
+#define RTC_RD_IER_WPON(base) ((RTC_IER_REG(base) & RTC_IER_WPON_MASK) >> RTC_IER_WPON_SHIFT)
+#define RTC_BRD_IER_WPON(base) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT))
+
+/*! @brief Set the WPON field to a new value. */
+#define RTC_WR_IER_WPON(base, value) (RTC_RMW_IER(base, RTC_IER_WPON_MASK, RTC_IER_WPON(value)))
+#define RTC_BWR_IER_WPON(base, value) (BITBAND_ACCESS32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_WAR - RTC Write Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_WAR - RTC Write Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_WAR register
+ */
+/*@{*/
+#define RTC_RD_WAR(base)         (RTC_WAR_REG(base))
+#define RTC_WR_WAR(base, value)  (RTC_WAR_REG(base) = (value))
+#define RTC_RMW_WAR(base, mask, value) (RTC_WR_WAR(base, (RTC_RD_WAR(base) & ~(mask)) | (value)))
+#define RTC_SET_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) |  (value)))
+#define RTC_CLR_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) & ~(value)))
+#define RTC_TOG_WAR(base, value) (RTC_WR_WAR(base, RTC_RD_WAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_WAR bitfields
+ */
+
+/*!
+ * @name Register RTC_WAR, field TSRW[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Seconds Register are ignored.
+ * - 0b1 - Writes to the Time Seconds Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TSRW field. */
+#define RTC_RD_WAR_TSRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TSRW_MASK) >> RTC_WAR_TSRW_SHIFT)
+#define RTC_BRD_WAR_TSRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TSRW_SHIFT))
+
+/*! @brief Set the TSRW field to a new value. */
+#define RTC_WR_WAR_TSRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TSRW_MASK, RTC_WAR_TSRW(value)))
+#define RTC_BWR_WAR_TSRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TSRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TPRW[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Prescaler Register are ignored.
+ * - 0b1 - Writes to the Time Prescaler Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TPRW field. */
+#define RTC_RD_WAR_TPRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TPRW_MASK) >> RTC_WAR_TPRW_SHIFT)
+#define RTC_BRD_WAR_TPRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TPRW_SHIFT))
+
+/*! @brief Set the TPRW field to a new value. */
+#define RTC_WR_WAR_TPRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TPRW_MASK, RTC_WAR_TPRW(value)))
+#define RTC_BWR_WAR_TPRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TPRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TARW[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Alarm Register are ignored.
+ * - 0b1 - Writes to the Time Alarm Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TARW field. */
+#define RTC_RD_WAR_TARW(base) ((RTC_WAR_REG(base) & RTC_WAR_TARW_MASK) >> RTC_WAR_TARW_SHIFT)
+#define RTC_BRD_WAR_TARW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TARW_SHIFT))
+
+/*! @brief Set the TARW field to a new value. */
+#define RTC_WR_WAR_TARW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TARW_MASK, RTC_WAR_TARW(value)))
+#define RTC_BWR_WAR_TARW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TARW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field TCRW[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Time Compensation Register are ignored.
+ * - 0b1 - Writes to the Time Compensation Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_TCRW field. */
+#define RTC_RD_WAR_TCRW(base) ((RTC_WAR_REG(base) & RTC_WAR_TCRW_MASK) >> RTC_WAR_TCRW_SHIFT)
+#define RTC_BRD_WAR_TCRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TCRW_SHIFT))
+
+/*! @brief Set the TCRW field to a new value. */
+#define RTC_WR_WAR_TCRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_TCRW_MASK, RTC_WAR_TCRW(value)))
+#define RTC_BWR_WAR_TCRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_TCRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field CRW[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Control Register are ignored.
+ * - 0b1 - Writes to the Control Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_CRW field. */
+#define RTC_RD_WAR_CRW(base) ((RTC_WAR_REG(base) & RTC_WAR_CRW_MASK) >> RTC_WAR_CRW_SHIFT)
+#define RTC_BRD_WAR_CRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_CRW_SHIFT))
+
+/*! @brief Set the CRW field to a new value. */
+#define RTC_WR_WAR_CRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_CRW_MASK, RTC_WAR_CRW(value)))
+#define RTC_BWR_WAR_CRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_CRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field SRW[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Status Register are ignored.
+ * - 0b1 - Writes to the Status Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_SRW field. */
+#define RTC_RD_WAR_SRW(base) ((RTC_WAR_REG(base) & RTC_WAR_SRW_MASK) >> RTC_WAR_SRW_SHIFT)
+#define RTC_BRD_WAR_SRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_SRW_SHIFT))
+
+/*! @brief Set the SRW field to a new value. */
+#define RTC_WR_WAR_SRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_SRW_MASK, RTC_WAR_SRW(value)))
+#define RTC_BWR_WAR_SRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_SRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field LRW[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Lock Register are ignored.
+ * - 0b1 - Writes to the Lock Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_LRW field. */
+#define RTC_RD_WAR_LRW(base) ((RTC_WAR_REG(base) & RTC_WAR_LRW_MASK) >> RTC_WAR_LRW_SHIFT)
+#define RTC_BRD_WAR_LRW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_LRW_SHIFT))
+
+/*! @brief Set the LRW field to a new value. */
+#define RTC_WR_WAR_LRW(base, value) (RTC_RMW_WAR(base, RTC_WAR_LRW_MASK, RTC_WAR_LRW(value)))
+#define RTC_BWR_WAR_LRW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_LRW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_WAR, field IERW[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Writes to the Interupt Enable Register are ignored.
+ * - 0b1 - Writes to the Interrupt Enable Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_WAR_IERW field. */
+#define RTC_RD_WAR_IERW(base) ((RTC_WAR_REG(base) & RTC_WAR_IERW_MASK) >> RTC_WAR_IERW_SHIFT)
+#define RTC_BRD_WAR_IERW(base) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_IERW_SHIFT))
+
+/*! @brief Set the IERW field to a new value. */
+#define RTC_WR_WAR_IERW(base, value) (RTC_RMW_WAR(base, RTC_WAR_IERW_MASK, RTC_WAR_IERW(value)))
+#define RTC_BWR_WAR_IERW(base, value) (BITBAND_ACCESS32(&RTC_WAR_REG(base), RTC_WAR_IERW_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * RTC_RAR - RTC Read Access Register
+ ******************************************************************************/
+
+/*!
+ * @brief RTC_RAR - RTC Read Access Register (RW)
+ *
+ * Reset value: 0x000000FFU
+ */
+/*!
+ * @name Constants and macros for entire RTC_RAR register
+ */
+/*@{*/
+#define RTC_RD_RAR(base)         (RTC_RAR_REG(base))
+#define RTC_WR_RAR(base, value)  (RTC_RAR_REG(base) = (value))
+#define RTC_RMW_RAR(base, mask, value) (RTC_WR_RAR(base, (RTC_RD_RAR(base) & ~(mask)) | (value)))
+#define RTC_SET_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) |  (value)))
+#define RTC_CLR_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) & ~(value)))
+#define RTC_TOG_RAR(base, value) (RTC_WR_RAR(base, RTC_RD_RAR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual RTC_RAR bitfields
+ */
+
+/*!
+ * @name Register RTC_RAR, field TSRR[0] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Seconds Register are ignored.
+ * - 0b1 - Reads to the Time Seconds Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TSRR field. */
+#define RTC_RD_RAR_TSRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TSRR_MASK) >> RTC_RAR_TSRR_SHIFT)
+#define RTC_BRD_RAR_TSRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TSRR_SHIFT))
+
+/*! @brief Set the TSRR field to a new value. */
+#define RTC_WR_RAR_TSRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TSRR_MASK, RTC_RAR_TSRR(value)))
+#define RTC_BWR_RAR_TSRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TSRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TPRR[1] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Pprescaler Register are ignored.
+ * - 0b1 - Reads to the Time Prescaler Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TPRR field. */
+#define RTC_RD_RAR_TPRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TPRR_MASK) >> RTC_RAR_TPRR_SHIFT)
+#define RTC_BRD_RAR_TPRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TPRR_SHIFT))
+
+/*! @brief Set the TPRR field to a new value. */
+#define RTC_WR_RAR_TPRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TPRR_MASK, RTC_RAR_TPRR(value)))
+#define RTC_BWR_RAR_TPRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TPRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TARR[2] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Alarm Register are ignored.
+ * - 0b1 - Reads to the Time Alarm Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TARR field. */
+#define RTC_RD_RAR_TARR(base) ((RTC_RAR_REG(base) & RTC_RAR_TARR_MASK) >> RTC_RAR_TARR_SHIFT)
+#define RTC_BRD_RAR_TARR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TARR_SHIFT))
+
+/*! @brief Set the TARR field to a new value. */
+#define RTC_WR_RAR_TARR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TARR_MASK, RTC_RAR_TARR(value)))
+#define RTC_BWR_RAR_TARR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TARR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field TCRR[3] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Time Compensation Register are ignored.
+ * - 0b1 - Reads to the Time Compensation Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_TCRR field. */
+#define RTC_RD_RAR_TCRR(base) ((RTC_RAR_REG(base) & RTC_RAR_TCRR_MASK) >> RTC_RAR_TCRR_SHIFT)
+#define RTC_BRD_RAR_TCRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TCRR_SHIFT))
+
+/*! @brief Set the TCRR field to a new value. */
+#define RTC_WR_RAR_TCRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_TCRR_MASK, RTC_RAR_TCRR(value)))
+#define RTC_BWR_RAR_TCRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_TCRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field CRR[4] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Control Register are ignored.
+ * - 0b1 - Reads to the Control Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_CRR field. */
+#define RTC_RD_RAR_CRR(base) ((RTC_RAR_REG(base) & RTC_RAR_CRR_MASK) >> RTC_RAR_CRR_SHIFT)
+#define RTC_BRD_RAR_CRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_CRR_SHIFT))
+
+/*! @brief Set the CRR field to a new value. */
+#define RTC_WR_RAR_CRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_CRR_MASK, RTC_RAR_CRR(value)))
+#define RTC_BWR_RAR_CRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_CRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field SRR[5] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Status Register are ignored.
+ * - 0b1 - Reads to the Status Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_SRR field. */
+#define RTC_RD_RAR_SRR(base) ((RTC_RAR_REG(base) & RTC_RAR_SRR_MASK) >> RTC_RAR_SRR_SHIFT)
+#define RTC_BRD_RAR_SRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_SRR_SHIFT))
+
+/*! @brief Set the SRR field to a new value. */
+#define RTC_WR_RAR_SRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_SRR_MASK, RTC_RAR_SRR(value)))
+#define RTC_BWR_RAR_SRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_SRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field LRR[6] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Lock Register are ignored.
+ * - 0b1 - Reads to the Lock Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_LRR field. */
+#define RTC_RD_RAR_LRR(base) ((RTC_RAR_REG(base) & RTC_RAR_LRR_MASK) >> RTC_RAR_LRR_SHIFT)
+#define RTC_BRD_RAR_LRR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_LRR_SHIFT))
+
+/*! @brief Set the LRR field to a new value. */
+#define RTC_WR_RAR_LRR(base, value) (RTC_RMW_RAR(base, RTC_RAR_LRR_MASK, RTC_RAR_LRR(value)))
+#define RTC_BWR_RAR_LRR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_LRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register RTC_RAR, field IERR[7] (RW)
+ *
+ * After being cleared, this bit is set only by system reset. It is not affected
+ * by VBAT POR or software reset.
+ *
+ * Values:
+ * - 0b0 - Reads to the Interrupt Enable Register are ignored.
+ * - 0b1 - Reads to the Interrupt Enable Register complete as normal.
+ */
+/*@{*/
+/*! @brief Read current value of the RTC_RAR_IERR field. */
+#define RTC_RD_RAR_IERR(base) ((RTC_RAR_REG(base) & RTC_RAR_IERR_MASK) >> RTC_RAR_IERR_SHIFT)
+#define RTC_BRD_RAR_IERR(base) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_IERR_SHIFT))
+
+/*! @brief Set the IERR field to a new value. */
+#define RTC_WR_RAR_IERR(base, value) (RTC_RMW_RAR(base, RTC_RAR_IERR_MASK, RTC_RAR_IERR(value)))
+#define RTC_BWR_RAR_IERR(base, value) (BITBAND_ACCESS32(&RTC_RAR_REG(base), RTC_RAR_IERR_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 SDHC
+ *
+ * Secured Digital Host Controller
+ *
+ * Registers defined in this header file:
+ * - SDHC_DSADDR - DMA System Address register
+ * - SDHC_BLKATTR - Block Attributes register
+ * - SDHC_CMDARG - Command Argument register
+ * - SDHC_XFERTYP - Transfer Type register
+ * - SDHC_CMDRSP - Command Response 0
+ * - SDHC_DATPORT - Buffer Data Port register
+ * - SDHC_PRSSTAT - Present State register
+ * - SDHC_PROCTL - Protocol Control register
+ * - SDHC_SYSCTL - System Control register
+ * - SDHC_IRQSTAT - Interrupt Status register
+ * - SDHC_IRQSTATEN - Interrupt Status Enable register
+ * - SDHC_IRQSIGEN - Interrupt Signal Enable register
+ * - SDHC_AC12ERR - Auto CMD12 Error Status Register
+ * - SDHC_HTCAPBLT - Host Controller Capabilities
+ * - SDHC_WML - Watermark Level Register
+ * - SDHC_FEVT - Force Event register
+ * - SDHC_ADMAES - ADMA Error Status register
+ * - SDHC_ADSADDR - ADMA System Addressregister
+ * - SDHC_VENDOR - Vendor Specific register
+ * - SDHC_MMCBOOT - MMC Boot register
+ * - SDHC_HOSTVER - Host Controller Version
+ */
+
+#define SDHC_INSTANCE_COUNT (1U) /*!< Number of instances of the SDHC module. */
+#define SDHC_IDX (0U) /*!< Instance number for SDHC. */
+
+/*******************************************************************************
+ * SDHC_DSADDR - DMA System Address register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_DSADDR - DMA System Address register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for DMA
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_DSADDR register
+ */
+/*@{*/
+#define SDHC_RD_DSADDR(base)     (SDHC_DSADDR_REG(base))
+#define SDHC_WR_DSADDR(base, value) (SDHC_DSADDR_REG(base) = (value))
+#define SDHC_RMW_DSADDR(base, mask, value) (SDHC_WR_DSADDR(base, (SDHC_RD_DSADDR(base) & ~(mask)) | (value)))
+#define SDHC_SET_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) |  (value)))
+#define SDHC_CLR_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) & ~(value)))
+#define SDHC_TOG_DSADDR(base, value) (SDHC_WR_DSADDR(base, SDHC_RD_DSADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_DSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
+ *
+ * Contains the 32-bit system memory address for a DMA transfer. Because the
+ * address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
+ * When the SDHC stops a DMA transfer, this register points to the system address
+ * of the next contiguous data position. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read operation
+ * during transfers may return an invalid value. The host driver shall initialize
+ * this register before starting a DMA transaction. After DMA has stopped, the
+ * system address of the next contiguous data position can be read from this register.
+ * This register is protected during a data transfer. When data lines are
+ * active, write to this register is ignored. The host driver shall wait, until
+ * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
+ * not support a virtual memory system. It supports only continuous physical
+ * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
+ * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
+ * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
+ * automatically alters the value of internal address counter, so SW cannot
+ * change this register when IRQSTAT[TC] is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_DSADDR_DSADDR field. */
+#define SDHC_RD_DSADDR_DSADDR(base) ((SDHC_DSADDR_REG(base) & SDHC_DSADDR_DSADDR_MASK) >> SDHC_DSADDR_DSADDR_SHIFT)
+#define SDHC_BRD_DSADDR_DSADDR(base) (SDHC_RD_DSADDR_DSADDR(base))
+
+/*! @brief Set the DSADDR field to a new value. */
+#define SDHC_WR_DSADDR_DSADDR(base, value) (SDHC_RMW_DSADDR(base, SDHC_DSADDR_DSADDR_MASK, SDHC_DSADDR_DSADDR(value)))
+#define SDHC_BWR_DSADDR_DSADDR(base, value) (SDHC_WR_DSADDR_DSADDR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_BLKATTR - Block Attributes register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_BLKATTR - Block Attributes register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to configure the number of data blocks and the number
+ * of bytes in each block.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_BLKATTR register
+ */
+/*@{*/
+#define SDHC_RD_BLKATTR(base)    (SDHC_BLKATTR_REG(base))
+#define SDHC_WR_BLKATTR(base, value) (SDHC_BLKATTR_REG(base) = (value))
+#define SDHC_RMW_BLKATTR(base, mask, value) (SDHC_WR_BLKATTR(base, (SDHC_RD_BLKATTR(base) & ~(mask)) | (value)))
+#define SDHC_SET_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) |  (value)))
+#define SDHC_CLR_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) & ~(value)))
+#define SDHC_TOG_BLKATTR(base, value) (SDHC_WR_BLKATTR(base, SDHC_RD_BLKATTR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_BLKATTR bitfields
+ */
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
+ *
+ * Specifies the block size for block data transfers. Values ranging from 1 byte
+ * up to the maximum buffer size can be set. It can be accessed only when no
+ * transaction is executing, that is, after a transaction has stopped. Read
+ * operations during transfers may return an invalid value, and write operations will be
+ * ignored.
+ *
+ * Values:
+ * - 0b0000000000000 - No data transfer.
+ * - 0b0000000000001 - 1 Byte
+ * - 0b0000000000010 - 2 Bytes
+ * - 0b0000000000011 - 3 Bytes
+ * - 0b0000000000100 - 4 Bytes
+ * - 0b0000111111111 - 511 Bytes
+ * - 0b0001000000000 - 512 Bytes
+ * - 0b0100000000000 - 2048 Bytes
+ * - 0b1000000000000 - 4096 Bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field. */
+#define SDHC_RD_BLKATTR_BLKSIZE(base) ((SDHC_BLKATTR_REG(base) & SDHC_BLKATTR_BLKSIZE_MASK) >> SDHC_BLKATTR_BLKSIZE_SHIFT)
+#define SDHC_BRD_BLKATTR_BLKSIZE(base) (SDHC_RD_BLKATTR_BLKSIZE(base))
+
+/*! @brief Set the BLKSIZE field to a new value. */
+#define SDHC_WR_BLKATTR_BLKSIZE(base, value) (SDHC_RMW_BLKATTR(base, SDHC_BLKATTR_BLKSIZE_MASK, SDHC_BLKATTR_BLKSIZE(value)))
+#define SDHC_BWR_BLKATTR_BLKSIZE(base, value) (SDHC_WR_BLKATTR_BLKSIZE(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
+ *
+ * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
+ * multiple block transfers. For single block transfer, this register will
+ * always read as 1. The host driver shall set this register to a value between 1 and
+ * the maximum block count. The SDHC decrements the block count after each block
+ * transfer and stops when the count reaches zero. Setting the block count to 0
+ * results in no data blocks being transferred. This register must be accessed
+ * only when no transaction is executing, that is, after transactions are stopped.
+ * During data transfer, read operations on this register may return an invalid
+ * value and write operations are ignored. When saving transfer content as a result
+ * of a suspend command, the number of blocks yet to be transferred can be
+ * determined by reading this register. The reading of this register must be applied
+ * after transfer is paused by stop at block gap operation and before sending the
+ * command marked as suspend. This is because when suspend command is sent out,
+ * SDHC will regard the current transfer as aborted and change BLKCNT back to its
+ * original value instead of keeping the dynamical indicator of remained block
+ * count. When restoring transfer content prior to issuing a resume command, the
+ * host driver shall restore the previously saved block count. Although the BLKCNT
+ * field is 0 after reset, the read of reset value is 0x1. This is because when
+ * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
+ * BLKCNT is always 1.
+ *
+ * Values:
+ * - 0b0000000000000000 - Stop count.
+ * - 0b0000000000000001 - 1 block
+ * - 0b0000000000000010 - 2 blocks
+ * - 0b1111111111111111 - 65535 blocks
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_BLKATTR_BLKCNT field. */
+#define SDHC_RD_BLKATTR_BLKCNT(base) ((SDHC_BLKATTR_REG(base) & SDHC_BLKATTR_BLKCNT_MASK) >> SDHC_BLKATTR_BLKCNT_SHIFT)
+#define SDHC_BRD_BLKATTR_BLKCNT(base) (SDHC_RD_BLKATTR_BLKCNT(base))
+
+/*! @brief Set the BLKCNT field to a new value. */
+#define SDHC_WR_BLKATTR_BLKCNT(base, value) (SDHC_RMW_BLKATTR(base, SDHC_BLKATTR_BLKCNT_MASK, SDHC_BLKATTR_BLKCNT(value)))
+#define SDHC_BWR_BLKATTR_BLKCNT(base, value) (SDHC_WR_BLKATTR_BLKCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_CMDARG - Command Argument register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_CMDARG - Command Argument register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the SD/MMC command argument.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_CMDARG register
+ */
+/*@{*/
+#define SDHC_RD_CMDARG(base)     (SDHC_CMDARG_REG(base))
+#define SDHC_WR_CMDARG(base, value) (SDHC_CMDARG_REG(base) = (value))
+#define SDHC_RMW_CMDARG(base, mask, value) (SDHC_WR_CMDARG(base, (SDHC_RD_CMDARG(base) & ~(mask)) | (value)))
+#define SDHC_SET_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) |  (value)))
+#define SDHC_CLR_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) & ~(value)))
+#define SDHC_TOG_CMDARG(base, value) (SDHC_WR_CMDARG(base, SDHC_RD_CMDARG(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_XFERTYP - Transfer Type register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_XFERTYP - Transfer Type register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to control the operation of data transfers. The host
+ * driver shall set this register before issuing a command followed by a data
+ * transfer, or before issuing a resume command. To prevent data loss, the SDHC
+ * prevents writing to the bits that are involved in the data transfer of this
+ * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
+ * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
+ * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
+ * send a command with data by writing to this register is ignored; when
+ * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
+ * data transfer involved, it is mandatory that the block size is nonzero.
+ * Besides, block count must also be nonzero, or indicated as single block transfer
+ * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
+ * this register is 0 when written), otherwise SDHC will ignore the sending of
+ * this command and do nothing. For write command, with all above restrictions, it
+ * is also mandatory that the write protect switch is not active (WPSPL bit of
+ * Present State Register is 1), otherwise SDHC will also ignore the command. If
+ * the commands with data transfer does not receive the response in 64 clock
+ * cycles, that is, response time-out, SDHC will regard the external device does not
+ * accept the command and abort the data transfer. In this scenario, the driver
+ * must issue the command again to retry the transfer. It is also possible that,
+ * for some reason, the card responds to the command but SDHC does not receive the
+ * response, and if it is internal DMA (either simple DMA or ADMA) read
+ * operation, the external system memory is over-written by the internal DMA with data
+ * sent back from the card. The following table shows the summary of how register
+ * settings determine the type of data transfer. Transfer Type register setting for
+ * various transfer types Multi/Single block select Block count enable Block
+ * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
+ * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
+ * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
+ * in regards to XFERTYP[RSPTYP] as well as the name of the response type.
+ * Relationship between parameters and the name of the response type Response type
+ * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
+ * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
+ * the SDIO specification, response type notation for R5b is not defined. R5
+ * includes R5b in the SDIO specification. But R5b is defined in this specification
+ * to specify that the SDHC will check the busy status after receiving a
+ * response. For example, usually CMD52 is used with R5, but the I/O abort command shall
+ * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
+ * The CRC check shall be disabled for these response types.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_XFERTYP register
+ */
+/*@{*/
+#define SDHC_RD_XFERTYP(base)    (SDHC_XFERTYP_REG(base))
+#define SDHC_WR_XFERTYP(base, value) (SDHC_XFERTYP_REG(base) = (value))
+#define SDHC_RMW_XFERTYP(base, mask, value) (SDHC_WR_XFERTYP(base, (SDHC_RD_XFERTYP(base) & ~(mask)) | (value)))
+#define SDHC_SET_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) |  (value)))
+#define SDHC_CLR_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) & ~(value)))
+#define SDHC_TOG_XFERTYP(base, value) (SDHC_WR_XFERTYP(base, SDHC_RD_XFERTYP(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_XFERTYP bitfields
+ */
+
+/*!
+ * @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
+ *
+ * Enables DMA functionality. If this bit is set to 1, a DMA operation shall
+ * begin when the host driver sets the DPSEL bit of this register. Whether the
+ * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DMAEN field. */
+#define SDHC_RD_XFERTYP_DMAEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DMAEN_MASK) >> SDHC_XFERTYP_DMAEN_SHIFT)
+#define SDHC_BRD_XFERTYP_DMAEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DMAEN_SHIFT))
+
+/*! @brief Set the DMAEN field to a new value. */
+#define SDHC_WR_XFERTYP_DMAEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DMAEN_MASK, SDHC_XFERTYP_DMAEN(value)))
+#define SDHC_BWR_XFERTYP_DMAEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field BCEN[1] (RW)
+ *
+ * Used to enable the Block Count register, which is only relevant for multiple
+ * block transfers. When this bit is 0, the internal counter for block is
+ * disabled, which is useful in executing an infinite transfer.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_BCEN field. */
+#define SDHC_RD_XFERTYP_BCEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_BCEN_MASK) >> SDHC_XFERTYP_BCEN_SHIFT)
+#define SDHC_BRD_XFERTYP_BCEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_BCEN_SHIFT))
+
+/*! @brief Set the BCEN field to a new value. */
+#define SDHC_WR_XFERTYP_BCEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_BCEN_MASK, SDHC_XFERTYP_BCEN(value)))
+#define SDHC_BWR_XFERTYP_BCEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_BCEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
+ *
+ * Multiple block transfers for memory require a CMD12 to stop the transaction.
+ * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
+ * last block transfer has completed. The host driver shall not set this bit to
+ * issue commands that do not require CMD12 to stop a multiple block data
+ * transfer. In particular, secure commands defined in File Security Specification (see
+ * reference list) do not require CMD12. In single block transfer, the SDHC will
+ * ignore this bit whether it is set or not.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_AC12EN field. */
+#define SDHC_RD_XFERTYP_AC12EN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_AC12EN_MASK) >> SDHC_XFERTYP_AC12EN_SHIFT)
+#define SDHC_BRD_XFERTYP_AC12EN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_AC12EN_SHIFT))
+
+/*! @brief Set the AC12EN field to a new value. */
+#define SDHC_WR_XFERTYP_AC12EN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_AC12EN_MASK, SDHC_XFERTYP_AC12EN(value)))
+#define SDHC_BWR_XFERTYP_AC12EN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_AC12EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
+ *
+ * Defines the direction of DAT line data transfers. The bit is set to 1 by the
+ * host driver to transfer data from the SD card to the SDHC and is set to 0 for
+ * all other commands.
+ *
+ * Values:
+ * - 0b0 - Write host to card.
+ * - 0b1 - Read card to host.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DTDSEL field. */
+#define SDHC_RD_XFERTYP_DTDSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DTDSEL_MASK) >> SDHC_XFERTYP_DTDSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_DTDSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DTDSEL_SHIFT))
+
+/*! @brief Set the DTDSEL field to a new value. */
+#define SDHC_WR_XFERTYP_DTDSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DTDSEL_MASK, SDHC_XFERTYP_DTDSEL(value)))
+#define SDHC_BWR_XFERTYP_DTDSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DTDSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
+ *
+ * Enables multiple block DAT line data transfers. For any other commands, this
+ * bit shall be set to 0. If this bit is 0, it is not necessary to set the block
+ * count register.
+ *
+ * Values:
+ * - 0b0 - Single block.
+ * - 0b1 - Multiple blocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_MSBSEL field. */
+#define SDHC_RD_XFERTYP_MSBSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_MSBSEL_MASK) >> SDHC_XFERTYP_MSBSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_MSBSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_MSBSEL_SHIFT))
+
+/*! @brief Set the MSBSEL field to a new value. */
+#define SDHC_WR_XFERTYP_MSBSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_MSBSEL_MASK, SDHC_XFERTYP_MSBSEL(value)))
+#define SDHC_BWR_XFERTYP_MSBSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_MSBSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
+ *
+ * Values:
+ * - 0b00 - No response.
+ * - 0b01 - Response length 136.
+ * - 0b10 - Response length 48.
+ * - 0b11 - Response length 48, check busy after response.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_RSPTYP field. */
+#define SDHC_RD_XFERTYP_RSPTYP(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_RSPTYP_MASK) >> SDHC_XFERTYP_RSPTYP_SHIFT)
+#define SDHC_BRD_XFERTYP_RSPTYP(base) (SDHC_RD_XFERTYP_RSPTYP(base))
+
+/*! @brief Set the RSPTYP field to a new value. */
+#define SDHC_WR_XFERTYP_RSPTYP(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_RSPTYP_MASK, SDHC_XFERTYP_RSPTYP(value)))
+#define SDHC_BWR_XFERTYP_RSPTYP(base, value) (SDHC_WR_XFERTYP_RSPTYP(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
+ *
+ * If this bit is set to 1, the SDHC shall check the CRC field in the response.
+ * If an error is detected, it is reported as a Command CRC Error. If this bit is
+ * set to 0, the CRC field is not checked. The number of bits checked by the CRC
+ * field value changes according to the length of the response.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CCCEN field. */
+#define SDHC_RD_XFERTYP_CCCEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CCCEN_MASK) >> SDHC_XFERTYP_CCCEN_SHIFT)
+#define SDHC_BRD_XFERTYP_CCCEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CCCEN_SHIFT))
+
+/*! @brief Set the CCCEN field to a new value. */
+#define SDHC_WR_XFERTYP_CCCEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CCCEN_MASK, SDHC_XFERTYP_CCCEN(value)))
+#define SDHC_BWR_XFERTYP_CCCEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CCCEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CICEN[20] (RW)
+ *
+ * If this bit is set to 1, the SDHC will check the index field in the response
+ * to see if it has the same value as the command index. If it is not, it is
+ * reported as a command index error. If this bit is set to 0, the index field is not
+ * checked.
+ *
+ * Values:
+ * - 0b0 - Disable
+ * - 0b1 - Enable
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CICEN field. */
+#define SDHC_RD_XFERTYP_CICEN(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CICEN_MASK) >> SDHC_XFERTYP_CICEN_SHIFT)
+#define SDHC_BRD_XFERTYP_CICEN(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CICEN_SHIFT))
+
+/*! @brief Set the CICEN field to a new value. */
+#define SDHC_WR_XFERTYP_CICEN(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CICEN_MASK, SDHC_XFERTYP_CICEN(value)))
+#define SDHC_BWR_XFERTYP_CICEN(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_CICEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
+ *
+ * This bit is set to 1 to indicate that data is present and shall be
+ * transferred using the DAT line. It is set to 0 for the following: Commands using only
+ * the CMD line, for example: CMD52. Commands with no data transfer, but using the
+ * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
+ * this bit shall be set, and other bits in this register shall be set the same
+ * as when the transfer was initially launched. When the Write Protect switch is
+ * on, that is, the WPSPL bit is active as 0, any command with a write operation
+ * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
+ * 0, writes to the register Transfer Type are ignored.
+ *
+ * Values:
+ * - 0b0 - No data present.
+ * - 0b1 - Data present.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_DPSEL field. */
+#define SDHC_RD_XFERTYP_DPSEL(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_DPSEL_MASK) >> SDHC_XFERTYP_DPSEL_SHIFT)
+#define SDHC_BRD_XFERTYP_DPSEL(base) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DPSEL_SHIFT))
+
+/*! @brief Set the DPSEL field to a new value. */
+#define SDHC_WR_XFERTYP_DPSEL(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_DPSEL_MASK, SDHC_XFERTYP_DPSEL(value)))
+#define SDHC_BWR_XFERTYP_DPSEL(base, value) (BITBAND_ACCESS32(&SDHC_XFERTYP_REG(base), SDHC_XFERTYP_DPSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
+ *
+ * There are three types of special commands: suspend, resume, and abort. These
+ * bits shall be set to 00b for all other commands. Suspend command: If the
+ * suspend command succeeds, the SDHC shall assume that the card bus has been released
+ * and that it is possible to issue the next command which uses the DAT line.
+ * Because the SDHC does not monitor the content of command response, it does not
+ * know if the suspend command succeeded or not. It is the host driver's
+ * responsibility to check the status of the suspend command and send another command
+ * marked as suspend to inform the SDHC that a suspend command was successfully
+ * issued. After the end bit of command is sent, the SDHC deasserts read wait for read
+ * transactions and stops checking busy for write transactions. In 4-bit mode,
+ * the interrupt cycle starts. If the suspend command fails, the SDHC will
+ * maintain its current state, and the host driver shall restart the transfer by setting
+ * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
+ * restoring the registers saved before sending the suspend command and then sends
+ * the resume command. The SDHC will check for a pending busy state before
+ * starting write transfers. Abort command: If this command is set when executing a
+ * read transfer, the SDHC will stop reads to the buffer. If this command is set
+ * when executing a write transfer, the SDHC will stop driving the DAT line. After
+ * issuing the abort command, the host driver must issue a software reset (abort
+ * transaction).
+ *
+ * Values:
+ * - 0b00 - Normal other commands.
+ * - 0b01 - Suspend CMD52 for writing bus suspend in CCCR.
+ * - 0b10 - Resume CMD52 for writing function select in CCCR.
+ * - 0b11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CMDTYP field. */
+#define SDHC_RD_XFERTYP_CMDTYP(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CMDTYP_MASK) >> SDHC_XFERTYP_CMDTYP_SHIFT)
+#define SDHC_BRD_XFERTYP_CMDTYP(base) (SDHC_RD_XFERTYP_CMDTYP(base))
+
+/*! @brief Set the CMDTYP field to a new value. */
+#define SDHC_WR_XFERTYP_CMDTYP(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CMDTYP_MASK, SDHC_XFERTYP_CMDTYP(value)))
+#define SDHC_BWR_XFERTYP_CMDTYP(base, value) (SDHC_WR_XFERTYP_CMDTYP(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
+ *
+ * These bits shall be set to the command number that is specified in bits 45-40
+ * of the command-format in the SD Memory Card Physical Layer Specification and
+ * SDIO Card Specification.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_XFERTYP_CMDINX field. */
+#define SDHC_RD_XFERTYP_CMDINX(base) ((SDHC_XFERTYP_REG(base) & SDHC_XFERTYP_CMDINX_MASK) >> SDHC_XFERTYP_CMDINX_SHIFT)
+#define SDHC_BRD_XFERTYP_CMDINX(base) (SDHC_RD_XFERTYP_CMDINX(base))
+
+/*! @brief Set the CMDINX field to a new value. */
+#define SDHC_WR_XFERTYP_CMDINX(base, value) (SDHC_RMW_XFERTYP(base, SDHC_XFERTYP_CMDINX_MASK, SDHC_XFERTYP_CMDINX(value)))
+#define SDHC_BWR_XFERTYP_CMDINX(base, value) (SDHC_WR_XFERTYP_CMDINX(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_CMDRSP - Command Response 0
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_CMDRSP - Command Response 0 (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to store part 0 of the response bits from the card.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_CMDRSP register
+ */
+/*@{*/
+#define SDHC_RD_CMDRSP(base, index) (SDHC_CMDRSP_REG(base, index))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_DATPORT - Buffer Data Port register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_DATPORT - Buffer Data Port register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This is a 32-bit data port register used to access the internal buffer and it
+ * cannot be updated in Idle mode.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_DATPORT register
+ */
+/*@{*/
+#define SDHC_RD_DATPORT(base)    (SDHC_DATPORT_REG(base))
+#define SDHC_WR_DATPORT(base, value) (SDHC_DATPORT_REG(base) = (value))
+#define SDHC_RMW_DATPORT(base, mask, value) (SDHC_WR_DATPORT(base, (SDHC_RD_DATPORT(base) & ~(mask)) | (value)))
+#define SDHC_SET_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) |  (value)))
+#define SDHC_CLR_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) & ~(value)))
+#define SDHC_TOG_DATPORT(base, value) (SDHC_WR_DATPORT(base, SDHC_RD_DATPORT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_PRSSTAT - Present State register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_PRSSTAT - Present State register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The host driver can get status of the SDHC from this 32-bit read-only
+ * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
+ * SDIO) when the DAT lines are busy during a data transfer. These commands can be
+ * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
+ * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
+ * Physical Specification may add other commands to this list in the future.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_PRSSTAT register
+ */
+/*@{*/
+#define SDHC_RD_PRSSTAT(base)    (SDHC_PRSSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_PRSSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
+ *
+ * If this status bit is 0, it indicates that the CMD line is not in use and the
+ * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
+ * immediately after the Transfer Type register is written. This bit is cleared when
+ * the command response is received. Even if the CDIHB bit is set to 1, Commands
+ * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
+ * generates a command complete interrupt in the interrupt status register. If the
+ * SDHC cannot issue the command because of a command conflict error (see
+ * command CRC error) or because of a command not issued by auto CMD12 error, this bit
+ * will remain 1 and the command complete is not set. The status of issuing an
+ * auto CMD12 does not show on this bit.
+ *
+ * Values:
+ * - 0b0 - Can issue command using only CMD line.
+ * - 0b1 - Cannot issue command.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CIHB field. */
+#define SDHC_RD_PRSSTAT_CIHB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CIHB_MASK) >> SDHC_PRSSTAT_CIHB_SHIFT)
+#define SDHC_BRD_PRSSTAT_CIHB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CIHB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
+ *
+ * This status bit is generated if either the DLA or the RTA is set to 1. If
+ * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
+ * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
+ * the case when the command busy is finished, changing from 1 to 0 generates a
+ * transfer complete interrupt in the Interrupt Status register. The SD host
+ * driver can save registers for a suspend transaction after this bit has changed
+ * from 1 to 0.
+ *
+ * Values:
+ * - 0b0 - Can issue command which uses the DAT line.
+ * - 0b1 - Cannot issue command which uses the DAT line.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CDIHB field. */
+#define SDHC_RD_PRSSTAT_CDIHB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CDIHB_MASK) >> SDHC_PRSSTAT_CDIHB_SHIFT)
+#define SDHC_BRD_PRSSTAT_CDIHB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CDIHB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLA[2] (RO)
+ *
+ * Indicates whether one of the DAT lines on the SD bus is in use. In the case
+ * of read transactions: This status indicates whether a read transfer is
+ * executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
+ * generates a block gap event interrupt in the Interrupt Status register. This bit
+ * will be set in either of the following cases: After the end bit of the read
+ * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
+ * will be cleared in either of the following cases: When the end bit of the last
+ * data block is sent from the SD bus to the SDHC. When the read wait state is
+ * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
+ * the next block gap by driving read wait at the start of the interrupt cycle.
+ * If the read wait signal is already driven (data buffer cannot receive data),
+ * the SDHC can wait for a current block gap by continuing to drive the read wait
+ * signal. It is necessary to support read wait to use the suspend / resume
+ * function. This bit will remain 1 during read wait. In the case of write
+ * transactions: This status indicates that a write transfer is executing on the SD bus.
+ * Changes in this value from 1 to 0 generate a transfer complete interrupt in the
+ * interrupt status register. This bit will be set in either of the following
+ * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
+ * continue a write transfer. This bit will be cleared in either of the
+ * following cases: When the SD card releases write busy of the last data block, the SDHC
+ * will also detect if the output is not busy. If the SD card does not drive the
+ * busy signal after the CRC status is received, the SDHC shall assume the card
+ * drive "Not busy". When the SD card releases write busy, prior to waiting for
+ * write transfer, and as a result of a stop at block gap request. In the case of
+ * command with busy pending: This status indicates that a busy state follows the
+ * command and the data line is in use. This bit will be cleared when the DAT0
+ * line is released.
+ *
+ * Values:
+ * - 0b0 - DAT line inactive.
+ * - 0b1 - DAT line active.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_DLA field. */
+#define SDHC_RD_PRSSTAT_DLA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_DLA_MASK) >> SDHC_PRSSTAT_DLA_SHIFT)
+#define SDHC_BRD_PRSSTAT_DLA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_DLA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
+ *
+ * Indicates that the internal card clock is stable. This bit is for the host
+ * driver to poll clock status when changing the clock frequency. It is recommended
+ * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
+ * frequency is changing.
+ *
+ * Values:
+ * - 0b0 - Clock is changing frequency and not stable.
+ * - 0b1 - Clock is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_SDSTB field. */
+#define SDHC_RD_PRSSTAT_SDSTB(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_SDSTB_MASK) >> SDHC_PRSSTAT_SDSTB_SHIFT)
+#define SDHC_BRD_PRSSTAT_SDSTB(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_SDSTB_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
+ *
+ * Indicates that the bus clock is internally gated off. This bit is for the
+ * host driver to debug.
+ *
+ * Values:
+ * - 0b0 - Bus clock is active.
+ * - 0b1 - Bus clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field. */
+#define SDHC_RD_PRSSTAT_IPGOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_IPGOFF_MASK) >> SDHC_PRSSTAT_IPGOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_IPGOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_IPGOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
+ *
+ * Indicates that the system clock is internally gated off. This bit is for the
+ * host driver to debug during a data transfer.
+ *
+ * Values:
+ * - 0b0 - System clock is active.
+ * - 0b1 - System clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field. */
+#define SDHC_RD_PRSSTAT_HCKOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_HCKOFF_MASK) >> SDHC_PRSSTAT_HCKOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_HCKOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_HCKOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
+ *
+ * Indicates that the is internally gated off. This bit is for the host driver
+ * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
+ * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
+ * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
+ * clock SDHC clock bus clock
+ *
+ * Values:
+ * - 0b0 - SDHC clock is active.
+ * - 0b1 - SDHC clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_PEROFF field. */
+#define SDHC_RD_PRSSTAT_PEROFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_PEROFF_MASK) >> SDHC_PRSSTAT_PEROFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_PEROFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_PEROFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
+ *
+ * Indicates that the SD clock is internally gated off, because of buffer
+ * over/under-run or read pause without read wait assertion, or the driver has cleared
+ * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
+ * data transaction on the SD bus.
+ *
+ * Values:
+ * - 0b0 - SD clock is active.
+ * - 0b1 - SD clock is gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_SDOFF field. */
+#define SDHC_RD_PRSSTAT_SDOFF(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_SDOFF_MASK) >> SDHC_PRSSTAT_SDOFF_SHIFT)
+#define SDHC_BRD_PRSSTAT_SDOFF(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_SDOFF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field WTA[8] (RO)
+ *
+ * Indicates that a write transfer is active. If this bit is 0, it means no
+ * valid write data exists in the SDHC. This bit is set in either of the following
+ * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
+ * restart a write transfer. This bit is cleared in either of the following
+ * cases: After getting the CRC status of the last data block as specified by the
+ * transfer count (single and multiple). After getting the CRC status of any block
+ * where data transmission is about to be stopped by a stop at block gap request.
+ * During a write transaction, a block gap event interrupt is generated when this
+ * bit is changed to 0, as result of the stop at block gap request being set.
+ * This status is useful for the host driver in determining when to issue commands
+ * during write busy state.
+ *
+ * Values:
+ * - 0b0 - No valid data.
+ * - 0b1 - Transferring data.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_WTA field. */
+#define SDHC_RD_PRSSTAT_WTA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_WTA_MASK) >> SDHC_PRSSTAT_WTA_SHIFT)
+#define SDHC_BRD_PRSSTAT_WTA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_WTA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field RTA[9] (RO)
+ *
+ * Used for detecting completion of a read transfer. This bit is set for either
+ * of the following conditions: After the end bit of the read command. When
+ * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
+ * interrupt is generated when this bit changes to 0. This bit is cleared for either of
+ * the following conditions: When the last data block as specified by block
+ * length is transferred to the system, that is, all data are read away from SDHC
+ * internal buffer. When all valid data blocks have been transferred from SDHC
+ * internal buffer to the system and no current block transfers are being sent as a
+ * result of the stop at block gap request being set to 1.
+ *
+ * Values:
+ * - 0b0 - No valid data.
+ * - 0b1 - Transferring data.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_RTA field. */
+#define SDHC_RD_PRSSTAT_RTA(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_RTA_MASK) >> SDHC_PRSSTAT_RTA_SHIFT)
+#define SDHC_BRD_PRSSTAT_RTA(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_RTA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
+ *
+ * Used for non-DMA write transfers. The SDHC can implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates whether space is
+ * available for write data. If this bit is 1, valid data greater than the watermark
+ * level can be written to the buffer. This read-only flag indicates whether
+ * space is available for write data.
+ *
+ * Values:
+ * - 0b0 - Write disable, the buffer can hold valid data less than the write
+ *     watermark level.
+ * - 0b1 - Write enable, the buffer can hold valid data greater than the write
+ *     watermark level.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_BWEN field. */
+#define SDHC_RD_PRSSTAT_BWEN(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_BWEN_MASK) >> SDHC_PRSSTAT_BWEN_SHIFT)
+#define SDHC_BRD_PRSSTAT_BWEN(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_BWEN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field BREN[11] (RO)
+ *
+ * Used for non-DMA read transfers. The SDHC may implement multiple buffers to
+ * transfer data efficiently. This read-only flag indicates that valid data exists
+ * in the host side buffer. If this bit is high, valid data greater than the
+ * watermark level exist in the buffer. This read-only flag indicates that valid
+ * data exists in the host side buffer.
+ *
+ * Values:
+ * - 0b0 - Read disable, valid data less than the watermark level exist in the
+ *     buffer.
+ * - 0b1 - Read enable, valid data greater than the watermark level exist in the
+ *     buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_BREN field. */
+#define SDHC_RD_PRSSTAT_BREN(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_BREN_MASK) >> SDHC_PRSSTAT_BREN_SHIFT)
+#define SDHC_BRD_PRSSTAT_BREN(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_BREN_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CINS[16] (RO)
+ *
+ * Indicates whether a card has been inserted. The SDHC debounces this signal so
+ * that the host driver will not need to wait for it to stabilize. Changing from
+ * a 0 to 1 generates a card insertion interrupt in the Interrupt Status
+ * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
+ * Status register. A write to the force event register does not effect this bit.
+ * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
+ * bit.
+ *
+ * Values:
+ * - 0b0 - Power on reset or no card.
+ * - 0b1 - Card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CINS field. */
+#define SDHC_RD_PRSSTAT_CINS(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CINS_MASK) >> SDHC_PRSSTAT_CINS_SHIFT)
+#define SDHC_BRD_PRSSTAT_CINS(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CINS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
+ *
+ * Used to check the CMD line level to recover from errors, and for debugging.
+ * The reset value is effected by the external pullup/pulldown resistor, by
+ * default, the read value of this bit after reset is 1b, when the command line is
+ * pulled up.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_CLSL field. */
+#define SDHC_RD_PRSSTAT_CLSL(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_CLSL_MASK) >> SDHC_PRSSTAT_CLSL_SHIFT)
+#define SDHC_BRD_PRSSTAT_CLSL(base) (BITBAND_ACCESS32(&SDHC_PRSSTAT_REG(base), SDHC_PRSSTAT_CLSL_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
+ *
+ * Used to check the DAT line level to recover from errors, and for debugging.
+ * This is especially useful in detecting the busy signal level from DAT[0]. The
+ * reset value is effected by the external pullup/pulldown resistors. By default,
+ * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
+ * down and the other lines are pulled up.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PRSSTAT_DLSL field. */
+#define SDHC_RD_PRSSTAT_DLSL(base) ((SDHC_PRSSTAT_REG(base) & SDHC_PRSSTAT_DLSL_MASK) >> SDHC_PRSSTAT_DLSL_SHIFT)
+#define SDHC_BRD_PRSSTAT_DLSL(base) (SDHC_RD_PRSSTAT_DLSL(base))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_PROCTL - Protocol Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_PROCTL - Protocol Control register (RW)
+ *
+ * Reset value: 0x00000020U
+ *
+ * There are three cases to restart the transfer after stop at the block gap.
+ * Which case is appropriate depends on whether the SDHC issues a suspend command
+ * or the SD card accepts the suspend command: If the host driver does not issue a
+ * suspend command, the continue request shall be used to restart the transfer.
+ * If the host driver issues a suspend command and the SD card accepts it, a
+ * resume command shall be used to restart the transfer. If the host driver issues a
+ * suspend command and the SD card does not accept it, the continue request shall
+ * be used to restart the transfer. Any time stop at block gap request stops the
+ * data transfer, the host driver shall wait for a transfer complete (in the
+ * interrupt status register), before attempting to restart the transfer. When
+ * restarting the data transfer by continue request, the host driver shall clear the
+ * stop at block gap request before or simultaneously.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_PROCTL register
+ */
+/*@{*/
+#define SDHC_RD_PROCTL(base)     (SDHC_PROCTL_REG(base))
+#define SDHC_WR_PROCTL(base, value) (SDHC_PROCTL_REG(base) = (value))
+#define SDHC_RMW_PROCTL(base, mask, value) (SDHC_WR_PROCTL(base, (SDHC_RD_PROCTL(base) & ~(mask)) | (value)))
+#define SDHC_SET_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) |  (value)))
+#define SDHC_CLR_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) & ~(value)))
+#define SDHC_TOG_PROCTL(base, value) (SDHC_WR_PROCTL(base, SDHC_RD_PROCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_PROCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_PROCTL, field LCTL[0] (RW)
+ *
+ * This bit, fully controlled by the host driver, is used to caution the user
+ * not to remove the card while the card is being accessed. If the software is
+ * going to issue multiple SD commands, this bit can be set during all these
+ * transactions. It is not necessary to change for each transaction. When the software
+ * issues multiple SD commands, setting the bit once before the first command is
+ * sufficient: it is not necessary to reset the bit between commands.
+ *
+ * Values:
+ * - 0b0 - LED off.
+ * - 0b1 - LED on.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_LCTL field. */
+#define SDHC_RD_PROCTL_LCTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_LCTL_MASK) >> SDHC_PROCTL_LCTL_SHIFT)
+#define SDHC_BRD_PROCTL_LCTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_LCTL_SHIFT))
+
+/*! @brief Set the LCTL field to a new value. */
+#define SDHC_WR_PROCTL_LCTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_LCTL_MASK, SDHC_PROCTL_LCTL(value)))
+#define SDHC_BWR_PROCTL_LCTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_LCTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field DTW[2:1] (RW)
+ *
+ * Selects the data width of the SD bus for a data transfer. The host driver
+ * shall set it to match the data width of the card. Possible data transfer width is
+ * 1-bit, 4-bits or 8-bits.
+ *
+ * Values:
+ * - 0b00 - 1-bit mode
+ * - 0b01 - 4-bit mode
+ * - 0b10 - 8-bit mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_DTW field. */
+#define SDHC_RD_PROCTL_DTW(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_DTW_MASK) >> SDHC_PROCTL_DTW_SHIFT)
+#define SDHC_BRD_PROCTL_DTW(base) (SDHC_RD_PROCTL_DTW(base))
+
+/*! @brief Set the DTW field to a new value. */
+#define SDHC_WR_PROCTL_DTW(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_DTW_MASK, SDHC_PROCTL_DTW(value)))
+#define SDHC_BWR_PROCTL_DTW(base, value) (SDHC_WR_PROCTL_DTW(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field D3CD[3] (RW)
+ *
+ * If this bit is set, DAT3 should be pulled down to act as a card detection
+ * pin. Be cautious when using this feature, because DAT3 is also a chip-select for
+ * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
+ * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
+ * is used.
+ *
+ * Values:
+ * - 0b0 - DAT3 does not monitor card Insertion.
+ * - 0b1 - DAT3 as card detection pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_D3CD field. */
+#define SDHC_RD_PROCTL_D3CD(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_D3CD_MASK) >> SDHC_PROCTL_D3CD_SHIFT)
+#define SDHC_BRD_PROCTL_D3CD(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_D3CD_SHIFT))
+
+/*! @brief Set the D3CD field to a new value. */
+#define SDHC_WR_PROCTL_D3CD(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_D3CD_MASK, SDHC_PROCTL_D3CD(value)))
+#define SDHC_BWR_PROCTL_D3CD(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_D3CD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
+ *
+ * The SDHC supports all four endian modes in data transfer.
+ *
+ * Values:
+ * - 0b00 - Big endian mode
+ * - 0b01 - Half word big endian mode
+ * - 0b10 - Little endian mode
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_EMODE field. */
+#define SDHC_RD_PROCTL_EMODE(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_EMODE_MASK) >> SDHC_PROCTL_EMODE_SHIFT)
+#define SDHC_BRD_PROCTL_EMODE(base) (SDHC_RD_PROCTL_EMODE(base))
+
+/*! @brief Set the EMODE field to a new value. */
+#define SDHC_WR_PROCTL_EMODE(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_EMODE_MASK, SDHC_PROCTL_EMODE(value)))
+#define SDHC_BWR_PROCTL_EMODE(base, value) (SDHC_WR_PROCTL_EMODE(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CDTL[6] (RW)
+ *
+ * Enabled while the CDSS is set to 1 and it indicates card insertion.
+ *
+ * Values:
+ * - 0b0 - Card detect test level is 0, no card inserted.
+ * - 0b1 - Card detect test level is 1, card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CDTL field. */
+#define SDHC_RD_PROCTL_CDTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CDTL_MASK) >> SDHC_PROCTL_CDTL_SHIFT)
+#define SDHC_BRD_PROCTL_CDTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDTL_SHIFT))
+
+/*! @brief Set the CDTL field to a new value. */
+#define SDHC_WR_PROCTL_CDTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CDTL_MASK, SDHC_PROCTL_CDTL(value)))
+#define SDHC_BWR_PROCTL_CDTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CDSS[7] (RW)
+ *
+ * Selects the source for the card detection.
+ *
+ * Values:
+ * - 0b0 - Card detection level is selected for normal purpose.
+ * - 0b1 - Card detection test level is selected for test purpose.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CDSS field. */
+#define SDHC_RD_PROCTL_CDSS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CDSS_MASK) >> SDHC_PROCTL_CDSS_SHIFT)
+#define SDHC_BRD_PROCTL_CDSS(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDSS_SHIFT))
+
+/*! @brief Set the CDSS field to a new value. */
+#define SDHC_WR_PROCTL_CDSS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CDSS_MASK, SDHC_PROCTL_CDSS(value)))
+#define SDHC_BWR_PROCTL_CDSS(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CDSS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
+ *
+ * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
+ * operation.
+ *
+ * Values:
+ * - 0b00 - No DMA or simple DMA is selected.
+ * - 0b01 - ADMA1 is selected.
+ * - 0b10 - ADMA2 is selected.
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_DMAS field. */
+#define SDHC_RD_PROCTL_DMAS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT)
+#define SDHC_BRD_PROCTL_DMAS(base) (SDHC_RD_PROCTL_DMAS(base))
+
+/*! @brief Set the DMAS field to a new value. */
+#define SDHC_WR_PROCTL_DMAS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_DMAS_MASK, SDHC_PROCTL_DMAS(value)))
+#define SDHC_BWR_PROCTL_DMAS(base, value) (SDHC_WR_PROCTL_DMAS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
+ *
+ * Used to stop executing a transaction at the next block gap for both DMA and
+ * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
+ * transfer completion, the host driver shall leave this bit set to 1. Clearing both
+ * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
+ * Wait is used to stop the read transaction at the block gap. The SDHC will
+ * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
+ * that SDIO card support read wait. Therefore, the host driver shall not set
+ * this bit during read transfers unless the SDIO card supports read wait and has
+ * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
+ * the read operation during block gap. In the case of write transfers in which
+ * the host driver writes data to the data port register, the host driver shall set
+ * this bit after all block data is written. If this bit is set to 1, the host
+ * driver shall not write data to the Data Port register after a block is sent.
+ * Once this bit is set, the host driver shall not clear this bit before
+ * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
+ * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
+ *
+ * Values:
+ * - 0b0 - Transfer
+ * - 0b1 - Stop
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_SABGREQ field. */
+#define SDHC_RD_PROCTL_SABGREQ(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_SABGREQ_MASK) >> SDHC_PROCTL_SABGREQ_SHIFT)
+#define SDHC_BRD_PROCTL_SABGREQ(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_SABGREQ_SHIFT))
+
+/*! @brief Set the SABGREQ field to a new value. */
+#define SDHC_WR_PROCTL_SABGREQ(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_SABGREQ_MASK, SDHC_PROCTL_SABGREQ(value)))
+#define SDHC_BWR_PROCTL_SABGREQ(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_SABGREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field CREQ[17] (RW)
+ *
+ * Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
+ * When a suspend operation is not accepted by the card, it is also by setting this
+ * bit to restart the paused transfer. To cancel stop at the block gap, set
+ * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
+ * automatically clears this bit, therefore it is not necessary for the host driver to
+ * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
+ * request is ignored.
+ *
+ * Values:
+ * - 0b0 - No effect.
+ * - 0b1 - Restart
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_CREQ field. */
+#define SDHC_RD_PROCTL_CREQ(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_CREQ_MASK) >> SDHC_PROCTL_CREQ_SHIFT)
+#define SDHC_BRD_PROCTL_CREQ(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CREQ_SHIFT))
+
+/*! @brief Set the CREQ field to a new value. */
+#define SDHC_WR_PROCTL_CREQ(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_CREQ_MASK, SDHC_PROCTL_CREQ(value)))
+#define SDHC_BWR_PROCTL_CREQ(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_CREQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field RWCTL[18] (RW)
+ *
+ * The read wait function is optional for SDIO cards. If the card supports read
+ * wait, set this bit to enable use of the read wait protocol to stop read data
+ * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
+ * read data, which restricts commands generation. When the host driver detects an
+ * SDIO card insertion, it shall set this bit according to the CCCR of the card.
+ * If the card does not support read wait, this bit shall never be set to 1,
+ * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
+ * during read operation is also supported, but the SDHC will stop the SD Clock
+ * to pause reading operation.
+ *
+ * Values:
+ * - 0b0 - Disable read wait control, and stop SD clock at block gap when
+ *     SABGREQ is set.
+ * - 0b1 - Enable read wait control, and assert read wait without stopping SD
+ *     clock at block gap when SABGREQ bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_RWCTL field. */
+#define SDHC_RD_PROCTL_RWCTL(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_RWCTL_MASK) >> SDHC_PROCTL_RWCTL_SHIFT)
+#define SDHC_BRD_PROCTL_RWCTL(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_RWCTL_SHIFT))
+
+/*! @brief Set the RWCTL field to a new value. */
+#define SDHC_WR_PROCTL_RWCTL(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_RWCTL_MASK, SDHC_PROCTL_RWCTL(value)))
+#define SDHC_BWR_PROCTL_RWCTL(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_RWCTL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field IABG[19] (RW)
+ *
+ * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
+ * interrupt cycle. Setting to 1 enables interrupt detection at the block gap
+ * for a multiple block transfer. Setting to 0 disables interrupt detection during
+ * a multiple block transfer. If the SDIO card can't signal an interrupt during a
+ * multiple block transfer, this bit must be set to 0 to avoid an inadvertent
+ * interrupt. When the host driver detects an SDIO card insertion, it shall set
+ * this bit according to the CCCR of the card.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_IABG field. */
+#define SDHC_RD_PROCTL_IABG(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_IABG_MASK) >> SDHC_PROCTL_IABG_SHIFT)
+#define SDHC_BRD_PROCTL_IABG(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_IABG_SHIFT))
+
+/*! @brief Set the IABG field to a new value. */
+#define SDHC_WR_PROCTL_IABG(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_IABG_MASK, SDHC_PROCTL_IABG(value)))
+#define SDHC_BWR_PROCTL_IABG(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_IABG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINT[24] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
+ * (Wake Up Support) in CIS is set to 1. When this bit is set, the card
+ * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
+ * the wakeup feature is not enabled, the SD_CLK must be active to assert the
+ * card interrupt status and the SDHC interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECINT field. */
+#define SDHC_RD_PROCTL_WECINT(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECINT_MASK) >> SDHC_PROCTL_WECINT_SHIFT)
+#define SDHC_BRD_PROCTL_WECINT(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINT_SHIFT))
+
+/*! @brief Set the WECINT field to a new value. */
+#define SDHC_WR_PROCTL_WECINT(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECINT_MASK, SDHC_PROCTL_WECINT(value)))
+#define SDHC_BWR_PROCTL_WECINT(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECINS[25] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
+ * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
+ * interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECINS field. */
+#define SDHC_RD_PROCTL_WECINS(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECINS_MASK) >> SDHC_PROCTL_WECINS_SHIFT)
+#define SDHC_BRD_PROCTL_WECINS(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINS_SHIFT))
+
+/*! @brief Set the WECINS field to a new value. */
+#define SDHC_WR_PROCTL_WECINS(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECINS_MASK, SDHC_PROCTL_WECINS(value)))
+#define SDHC_BWR_PROCTL_WECINS(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_PROCTL, field WECRM[26] (RW)
+ *
+ * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
+ * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
+ * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
+ * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_PROCTL_WECRM field. */
+#define SDHC_RD_PROCTL_WECRM(base) ((SDHC_PROCTL_REG(base) & SDHC_PROCTL_WECRM_MASK) >> SDHC_PROCTL_WECRM_SHIFT)
+#define SDHC_BRD_PROCTL_WECRM(base) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECRM_SHIFT))
+
+/*! @brief Set the WECRM field to a new value. */
+#define SDHC_WR_PROCTL_WECRM(base, value) (SDHC_RMW_PROCTL(base, SDHC_PROCTL_WECRM_MASK, SDHC_PROCTL_WECRM(value)))
+#define SDHC_BWR_PROCTL_WECRM(base, value) (BITBAND_ACCESS32(&SDHC_PROCTL_REG(base), SDHC_PROCTL_WECRM_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_SYSCTL - System Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_SYSCTL - System Control register (RW)
+ *
+ * Reset value: 0x00008008U
+ */
+/*!
+ * @name Constants and macros for entire SDHC_SYSCTL register
+ */
+/*@{*/
+#define SDHC_RD_SYSCTL(base)     (SDHC_SYSCTL_REG(base))
+#define SDHC_WR_SYSCTL(base, value) (SDHC_SYSCTL_REG(base) = (value))
+#define SDHC_RMW_SYSCTL(base, mask, value) (SDHC_WR_SYSCTL(base, (SDHC_RD_SYSCTL(base) & ~(mask)) | (value)))
+#define SDHC_SET_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) |  (value)))
+#define SDHC_CLR_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) & ~(value)))
+#define SDHC_TOG_SYSCTL(base, value) (SDHC_WR_SYSCTL(base, SDHC_RD_SYSCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_SYSCTL bitfields
+ */
+
+/*!
+ * @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
+ *
+ * If this bit is set, bus clock will always be active and no automatic gating
+ * is applied. The bus clock will be internally gated off, if none of the
+ * following factors are met: The cmd part is reset, or Data part is reset, or Soft
+ * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
+ * request is just set, or This bit is set, or Card insertion is detected, or Card
+ * removal is detected, or Card external interrupt is detected, or The SDHC
+ * clock is not gated off The bus clock will not be auto gated off if the SDHC clock
+ * is not gated off. So clearing only this bit has no effect unless the PEREN bit
+ * is also cleared.
+ *
+ * Values:
+ * - 0b0 - Bus clock will be internally gated off.
+ * - 0b1 - Bus clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_IPGEN field. */
+#define SDHC_RD_SYSCTL_IPGEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_IPGEN_MASK) >> SDHC_SYSCTL_IPGEN_SHIFT)
+#define SDHC_BRD_SYSCTL_IPGEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_IPGEN_SHIFT))
+
+/*! @brief Set the IPGEN field to a new value. */
+#define SDHC_WR_SYSCTL_IPGEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_IPGEN_MASK, SDHC_SYSCTL_IPGEN(value)))
+#define SDHC_BWR_SYSCTL_IPGEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_IPGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
+ *
+ * If this bit is set, system clock will always be active and no automatic
+ * gating is applied. When this bit is cleared, system clock will be automatically off
+ * when no data transfer is on the SD bus.
+ *
+ * Values:
+ * - 0b0 - System clock will be internally gated off.
+ * - 0b1 - System clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_HCKEN field. */
+#define SDHC_RD_SYSCTL_HCKEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_HCKEN_MASK) >> SDHC_SYSCTL_HCKEN_SHIFT)
+#define SDHC_BRD_SYSCTL_HCKEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_HCKEN_SHIFT))
+
+/*! @brief Set the HCKEN field to a new value. */
+#define SDHC_WR_SYSCTL_HCKEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_HCKEN_MASK, SDHC_SYSCTL_HCKEN(value)))
+#define SDHC_BWR_SYSCTL_HCKEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_HCKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field PEREN[2] (RW)
+ *
+ * If this bit is set, SDHC clock will always be active and no automatic gating
+ * is applied. Thus the SDCLK is active except for when auto gating-off during
+ * buffer danger (buffer about to over-run or under-run). When this bit is cleared,
+ * the SDHC clock will be automatically off whenever there is no transaction on
+ * the SD bus. Because this bit is only a feature enabling bit, clearing this bit
+ * does not stop SDCLK immediately. The SDHC clock will be internally gated off,
+ * if none of the following factors are met: The cmd part is reset, or Data part
+ * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
+ * just updated, or Continue request is just set, or This bit is set, or Card
+ * insertion is detected, or Card removal is detected, or Card external interrupt is
+ * detected, or 80 clocks for initialization phase is ongoing
+ *
+ * Values:
+ * - 0b0 - SDHC clock will be internally gated off.
+ * - 0b1 - SDHC clock will not be automatically gated off.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_PEREN field. */
+#define SDHC_RD_SYSCTL_PEREN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_PEREN_MASK) >> SDHC_SYSCTL_PEREN_SHIFT)
+#define SDHC_BRD_SYSCTL_PEREN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_PEREN_SHIFT))
+
+/*! @brief Set the PEREN field to a new value. */
+#define SDHC_WR_SYSCTL_PEREN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_PEREN_MASK, SDHC_SYSCTL_PEREN(value)))
+#define SDHC_BWR_SYSCTL_PEREN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_PEREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
+ *
+ * The host controller shall stop SDCLK when writing this bit to 0. SDCLK
+ * frequency can be changed when this bit is 0. Then, the host controller shall
+ * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
+ * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
+ * power.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field. */
+#define SDHC_RD_SYSCTL_SDCLKEN(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_SDCLKEN_MASK) >> SDHC_SYSCTL_SDCLKEN_SHIFT)
+#define SDHC_BRD_SYSCTL_SDCLKEN(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_SDCLKEN_SHIFT))
+
+/*! @brief Set the SDCLKEN field to a new value. */
+#define SDHC_WR_SYSCTL_SDCLKEN(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_SDCLKEN_MASK, SDHC_SYSCTL_SDCLKEN(value)))
+#define SDHC_BWR_SYSCTL_SDCLKEN(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_SDCLKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
+ *
+ * Used to provide a more exact divisor to generate the desired SD clock
+ * frequency. Note the divider can even support odd divisor without deterioration of
+ * duty cycle. The setting are as following:
+ *
+ * Values:
+ * - 0b0000 - Divisor by 1.
+ * - 0b0001 - Divisor by 2.
+ * - 0b1110 - Divisor by 15.
+ * - 0b1111 - Divisor by 16.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_DVS field. */
+#define SDHC_RD_SYSCTL_DVS(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_DVS_MASK) >> SDHC_SYSCTL_DVS_SHIFT)
+#define SDHC_BRD_SYSCTL_DVS(base) (SDHC_RD_SYSCTL_DVS(base))
+
+/*! @brief Set the DVS field to a new value. */
+#define SDHC_WR_SYSCTL_DVS(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_DVS_MASK, SDHC_SYSCTL_DVS(value)))
+#define SDHC_BWR_SYSCTL_DVS(base, value) (SDHC_WR_SYSCTL_DVS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
+ *
+ * Used to select the frequency of the SDCLK pin. The frequency is not
+ * programmed directly. Rather this register holds the prescaler (this register) and
+ * divisor (next register) of the base clock frequency register. Setting 00h bypasses
+ * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
+ * behavior of this prescaler is undefined. The two default divider values can
+ * be calculated by the frequency of SDHC clock and the following divisor bits.
+ * The frequency of SDCLK is set by the following formula: Clock frequency = (Base
+ * clock) / (prescaler x divisor) For example, if the base clock frequency is 96
+ * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
+ * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
+ * less than or equal to the target. Similarly, to approach a clock value of 400
+ * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
+ * value of 400 kHz. The reset value of this field is 80h, so if the input base
+ * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
+ * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
+ * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
+ * never exceed this limit. Only the following settings are allowed:
+ *
+ * Values:
+ * - 0b00000001 - Base clock divided by 2.
+ * - 0b00000010 - Base clock divided by 4.
+ * - 0b00000100 - Base clock divided by 8.
+ * - 0b00001000 - Base clock divided by 16.
+ * - 0b00010000 - Base clock divided by 32.
+ * - 0b00100000 - Base clock divided by 64.
+ * - 0b01000000 - Base clock divided by 128.
+ * - 0b10000000 - Base clock divided by 256.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field. */
+#define SDHC_RD_SYSCTL_SDCLKFS(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_SDCLKFS_MASK) >> SDHC_SYSCTL_SDCLKFS_SHIFT)
+#define SDHC_BRD_SYSCTL_SDCLKFS(base) (SDHC_RD_SYSCTL_SDCLKFS(base))
+
+/*! @brief Set the SDCLKFS field to a new value. */
+#define SDHC_WR_SYSCTL_SDCLKFS(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_SDCLKFS_MASK, SDHC_SYSCTL_SDCLKFS(value)))
+#define SDHC_BWR_SYSCTL_SDCLKFS(base, value) (SDHC_WR_SYSCTL_SDCLKFS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
+ *
+ * Determines the interval by which DAT line timeouts are detected. See
+ * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
+ * clock frequency will be generated by dividing the base clock SDCLK value by this
+ * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
+ * time-out events.
+ *
+ * Values:
+ * - 0b0000 - SDCLK x 2 13
+ * - 0b0001 - SDCLK x 2 14
+ * - 0b1110 - SDCLK x 2 27
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_DTOCV field. */
+#define SDHC_RD_SYSCTL_DTOCV(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_DTOCV_MASK) >> SDHC_SYSCTL_DTOCV_SHIFT)
+#define SDHC_BRD_SYSCTL_DTOCV(base) (SDHC_RD_SYSCTL_DTOCV(base))
+
+/*! @brief Set the DTOCV field to a new value. */
+#define SDHC_WR_SYSCTL_DTOCV(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_DTOCV_MASK, SDHC_SYSCTL_DTOCV(value)))
+#define SDHC_BWR_SYSCTL_DTOCV(base, value) (SDHC_WR_SYSCTL_DTOCV(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
+ *
+ * Effects the entire host controller except for the card detection circuit.
+ * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
+ * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
+ * reset this bit to 0 when the capabilities registers are valid and the host driver
+ * can read them. Additional use of software reset for all does not affect the
+ * value of the capabilities registers. After this bit is set, it is recommended
+ * that the host driver reset the external card and reinitialize it.
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTA field to a new value. */
+#define SDHC_WR_SYSCTL_RSTA(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTA_MASK, SDHC_SYSCTL_RSTA(value)))
+#define SDHC_BWR_SYSCTL_RSTA(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
+ *
+ * Only part of the command circuit is reset. The following registers and bits
+ * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTC field to a new value. */
+#define SDHC_WR_SYSCTL_RSTC(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTC_MASK, SDHC_SYSCTL_RSTC(value)))
+#define SDHC_BWR_SYSCTL_RSTC(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
+ *
+ * Only part of the data circuit is reset. DMA circuit is also reset. The
+ * following registers and bits are cleared by this bit: Data Port register Buffer Is
+ * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
+ * Enable Read Transfer Active Write Transfer Active DAT Line Active Command
+ * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
+ * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
+ * Block Gap Event Transfer Complete
+ *
+ * Values:
+ * - 0b0 - No reset.
+ * - 0b1 - Reset.
+ */
+/*@{*/
+/*! @brief Set the RSTD field to a new value. */
+#define SDHC_WR_SYSCTL_RSTD(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_RSTD_MASK, SDHC_SYSCTL_RSTD(value)))
+#define SDHC_BWR_SYSCTL_RSTD(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_RSTD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_SYSCTL, field INITA[27] (RW)
+ *
+ * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
+ * are sent, this bit is self-cleared. This bit is very useful during the card
+ * power-up period when 74 SD-clocks are needed and the clock auto gating feature
+ * is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
+ * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
+ * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
+ * when command line or data lines are active, write to this bit is not allowed.
+ * On the otherhand, when this bit is set, that is, during intialization active
+ * period, it is allowed to issue command, and the command bit stream will appear
+ * on the CMD pad after all 80 clock cycles are done. So when this command ends,
+ * the driver can make sure the 80 clock cycles are sent out. This is very useful
+ * when the driver needs send 80 cycles to the card and does not want to wait
+ * till this bit is self-cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_SYSCTL_INITA field. */
+#define SDHC_RD_SYSCTL_INITA(base) ((SDHC_SYSCTL_REG(base) & SDHC_SYSCTL_INITA_MASK) >> SDHC_SYSCTL_INITA_SHIFT)
+#define SDHC_BRD_SYSCTL_INITA(base) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_INITA_SHIFT))
+
+/*! @brief Set the INITA field to a new value. */
+#define SDHC_WR_SYSCTL_INITA(base, value) (SDHC_RMW_SYSCTL(base, SDHC_SYSCTL_INITA_MASK, SDHC_SYSCTL_INITA(value)))
+#define SDHC_BWR_SYSCTL_INITA(base, value) (BITBAND_ACCESS32(&SDHC_SYSCTL_REG(base), SDHC_SYSCTL_INITA_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSTAT - Interrupt Status register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * An interrupt is generated when the Normal Interrupt Signal Enable is enabled
+ * and at least one of the status bits is set to 1. For all bits, writing 1 to a
+ * bit clears it; writing to 0 keeps the bit unchanged. More than one status can
+ * be cleared with a single register write. For Card Interrupt, before writing 1
+ * to clear, it is required that the card stops asserting the interrupt, meaning
+ * that when the Card Driver services the interrupt condition, otherwise the CINT
+ * bit will be asserted again. The table below shows the relationship between
+ * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
+ * complete Command timeout error Meaning of the status 0 0 X X 1 Response not
+ * received within 64 SDCLK cycles 1 0 Response received The table below shows the
+ * relationship between the Transfer Complete and the Data Timeout Error. SDHC status
+ * for data timeout error/transfer complete bit combinations Transfer complete
+ * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
+ * transfer 1 X Data transfer complete The table below shows the relationship between
+ * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
+ * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
+ * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
+ * CMD line conflict
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTAT register
+ */
+/*@{*/
+#define SDHC_RD_IRQSTAT(base)    (SDHC_IRQSTAT_REG(base))
+#define SDHC_WR_IRQSTAT(base, value) (SDHC_IRQSTAT_REG(base) = (value))
+#define SDHC_RMW_IRQSTAT(base, mask, value) (SDHC_WR_IRQSTAT(base, (SDHC_RD_IRQSTAT(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) |  (value)))
+#define SDHC_CLR_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) & ~(value)))
+#define SDHC_TOG_IRQSTAT(base, value) (SDHC_WR_IRQSTAT(base, SDHC_RD_IRQSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSTAT bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CC[0] (W1C)
+ *
+ * This bit is set when you receive the end bit of the command response, except
+ * Auto CMD12. See PRSSTAT[CIHB].
+ *
+ * Values:
+ * - 0b0 - Command not complete.
+ * - 0b1 - Command complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CC field. */
+#define SDHC_RD_IRQSTAT_CC(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CC_MASK) >> SDHC_IRQSTAT_CC_SHIFT)
+#define SDHC_BRD_IRQSTAT_CC(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CC_SHIFT))
+
+/*! @brief Set the CC field to a new value. */
+#define SDHC_WR_IRQSTAT_CC(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CC(value)))
+#define SDHC_BWR_IRQSTAT_CC(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field TC[1] (W1C)
+ *
+ * This bit is set when a read or write transfer is completed. In the case of a
+ * read transaction: This bit is set at the falling edge of the read transfer
+ * active status. There are two cases in which this interrupt is generated. The
+ * first is when a data transfer is completed as specified by the data length, after
+ * the last data has been read to the host system. The second is when data has
+ * stopped at the block gap and completed the data transfer by setting
+ * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
+ * transaction: This bit is set at the falling edge of the DAT line active
+ * status. There are two cases in which this interrupt is generated. The first is when
+ * the last data is written to the SD card as specified by the data length and
+ * the busy signal is released. The second is when data transfers are stopped at
+ * the block gap, by setting PROCTL[SABGREQ], and the data transfers are
+ * completed,after valid data is written to the SD card and the busy signal released.
+ *
+ * Values:
+ * - 0b0 - Transfer not complete.
+ * - 0b1 - Transfer complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_TC field. */
+#define SDHC_RD_IRQSTAT_TC(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_TC_MASK) >> SDHC_IRQSTAT_TC_SHIFT)
+#define SDHC_BRD_IRQSTAT_TC(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_TC_SHIFT))
+
+/*! @brief Set the TC field to a new value. */
+#define SDHC_WR_IRQSTAT_TC(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_TC(value)))
+#define SDHC_BWR_IRQSTAT_TC(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_TC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
+ *
+ * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
+ * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
+ * set to 1. In the case of a read transaction: This bit is set at the falling
+ * edge of the DAT line active status, when the transaction is stopped at SD Bus
+ * timing. The read wait must be supported in order to use this function. In the
+ * case of write transaction: This bit is set at the falling edge of write transfer
+ * active status, after getting CRC status at SD bus timing.
+ *
+ * Values:
+ * - 0b0 - No block gap event.
+ * - 0b1 - Transaction stopped at block gap.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BGE field. */
+#define SDHC_RD_IRQSTAT_BGE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BGE_MASK) >> SDHC_IRQSTAT_BGE_SHIFT)
+#define SDHC_BRD_IRQSTAT_BGE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BGE_SHIFT))
+
+/*! @brief Set the BGE field to a new value. */
+#define SDHC_WR_IRQSTAT_BGE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BGE(value)))
+#define SDHC_BWR_IRQSTAT_BGE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BGE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
+ *
+ * Occurs only when the internal DMA finishes the data transfer successfully.
+ * Whenever errors occur during data transfer, this bit will not be set. Instead,
+ * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
+ * this bit will be set.
+ *
+ * Values:
+ * - 0b0 - No DMA Interrupt.
+ * - 0b1 - DMA Interrupt is generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DINT field. */
+#define SDHC_RD_IRQSTAT_DINT(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DINT_MASK) >> SDHC_IRQSTAT_DINT_SHIFT)
+#define SDHC_BRD_IRQSTAT_DINT(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DINT_SHIFT))
+
+/*! @brief Set the DINT field to a new value. */
+#define SDHC_WR_IRQSTAT_DINT(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DINT(value)))
+#define SDHC_BWR_IRQSTAT_DINT(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
+ *
+ * This status bit is set if the Buffer Write Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0b0 - Not ready to write buffer.
+ * - 0b1 - Ready to write buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BWR field. */
+#define SDHC_RD_IRQSTAT_BWR(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BWR_MASK) >> SDHC_IRQSTAT_BWR_SHIFT)
+#define SDHC_BRD_IRQSTAT_BWR(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BWR_SHIFT))
+
+/*! @brief Set the BWR field to a new value. */
+#define SDHC_WR_IRQSTAT_BWR(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BWR(value)))
+#define SDHC_BWR_IRQSTAT_BWR(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BWR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
+ *
+ * This status bit is set if the Buffer Read Enable bit, in the Present State
+ * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
+ * State register for additional information.
+ *
+ * Values:
+ * - 0b0 - Not ready to read buffer.
+ * - 0b1 - Ready to read buffer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_BRR field. */
+#define SDHC_RD_IRQSTAT_BRR(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_BRR_MASK) >> SDHC_IRQSTAT_BRR_SHIFT)
+#define SDHC_BRD_IRQSTAT_BRR(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BRR_SHIFT))
+
+/*! @brief Set the BRR field to a new value. */
+#define SDHC_WR_IRQSTAT_BRR(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_BRR(value)))
+#define SDHC_BWR_IRQSTAT_BRR(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_BRR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 0 to 1. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if a card is inserted. To leave it cleared,
+ * clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0b0 - Card state unstable or removed.
+ * - 0b1 - Card inserted.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CINS field. */
+#define SDHC_RD_IRQSTAT_CINS(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CINS_MASK) >> SDHC_IRQSTAT_CINS_SHIFT)
+#define SDHC_BRD_IRQSTAT_CINS(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINS_SHIFT))
+
+/*! @brief Set the CINS field to a new value. */
+#define SDHC_WR_IRQSTAT_CINS(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CINS(value)))
+#define SDHC_BWR_IRQSTAT_CINS(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
+ *
+ * This status bit is set if the Card Inserted bit in the Present State register
+ * changes from 1 to 0. When the host driver writes this bit to 1 to clear this
+ * status, the status of the Card Inserted in the Present State register must be
+ * confirmed. Because the card state may possibly be changed when the host driver
+ * clears this bit and the interrupt event may not be generated. When this bit
+ * is cleared, it will be set again if no card is inserted. To leave it cleared,
+ * clear the Card Removal Status Enable bit in Interrupt Status Enable register.
+ *
+ * Values:
+ * - 0b0 - Card state unstable or inserted.
+ * - 0b1 - Card removed.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CRM field. */
+#define SDHC_RD_IRQSTAT_CRM(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CRM_MASK) >> SDHC_IRQSTAT_CRM_SHIFT)
+#define SDHC_BRD_IRQSTAT_CRM(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CRM_SHIFT))
+
+/*! @brief Set the CRM field to a new value. */
+#define SDHC_WR_IRQSTAT_CRM(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CRM(value)))
+#define SDHC_BWR_IRQSTAT_CRM(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CRM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
+ *
+ * This status bit is set when an interrupt signal is detected from the external
+ * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
+ * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
+ * during the interrupt cycle, so the interrupt from card can only be sampled
+ * during interrupt cycle, introducing some delay between the interrupt signal from
+ * the SDIO card and the interrupt to the host system. Writing this bit to 1 can
+ * clear this bit, but as the interrupt factor from the SDIO card does not clear,
+ * this bit is set again. To clear this bit, it is required to reset the interrupt
+ * factor from the external card followed by a writing 1 to this bit. When this
+ * status has been set, and the host driver needs to service this interrupt, the
+ * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
+ * 0 to stop driving the interrupt signal to the host system. After completion
+ * of the card interrupt service (it must reset the interrupt factors in the SDIO
+ * card and the interrupt signal may not be asserted), write 1 to clear this bit,
+ * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
+ * signal again.
+ *
+ * Values:
+ * - 0b0 - No Card Interrupt.
+ * - 0b1 - Generate Card Interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CINT field. */
+#define SDHC_RD_IRQSTAT_CINT(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CINT_MASK) >> SDHC_IRQSTAT_CINT_SHIFT)
+#define SDHC_BRD_IRQSTAT_CINT(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINT_SHIFT))
+
+/*! @brief Set the CINT field to a new value. */
+#define SDHC_WR_IRQSTAT_CINT(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CINT(value)))
+#define SDHC_BWR_IRQSTAT_CINT(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CINT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
+ *
+ * Occurs only if no response is returned within 64 SDCLK cycles from the end
+ * bit of the command. If the SDHC detects a CMD line conflict, in which case a
+ * Command CRC Error shall also be set, this bit shall be set without waiting for 64
+ * SDCLK cycles. This is because the command will be aborted by the SDHC.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CTOE field. */
+#define SDHC_RD_IRQSTAT_CTOE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CTOE_MASK) >> SDHC_IRQSTAT_CTOE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CTOE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CTOE_SHIFT))
+
+/*! @brief Set the CTOE field to a new value. */
+#define SDHC_WR_IRQSTAT_CTOE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CTOE(value)))
+#define SDHC_BWR_IRQSTAT_CTOE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
+ *
+ * Command CRC Error is generated in two cases. If a response is returned and
+ * the Command Timeout Error is set to 0, indicating no time-out, this bit is set
+ * when detecting a CRC error in the command response. The SDHC detects a CMD line
+ * conflict by monitoring the CMD line when a command is issued. If the SDHC
+ * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
+ * then the SDHC shall abort the command (Stop driving CMD line) and set this bit
+ * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
+ * conflict.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - CRC Error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CCE field. */
+#define SDHC_RD_IRQSTAT_CCE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CCE_MASK) >> SDHC_IRQSTAT_CCE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CCE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CCE_SHIFT))
+
+/*! @brief Set the CCE field to a new value. */
+#define SDHC_WR_IRQSTAT_CCE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CCE(value)))
+#define SDHC_BWR_IRQSTAT_CCE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
+ *
+ * Occurs when detecting that the end bit of a command response is 0.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - End Bit Error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CEBE field. */
+#define SDHC_RD_IRQSTAT_CEBE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CEBE_MASK) >> SDHC_IRQSTAT_CEBE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CEBE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CEBE_SHIFT))
+
+/*! @brief Set the CEBE field to a new value. */
+#define SDHC_WR_IRQSTAT_CEBE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CEBE(value)))
+#define SDHC_BWR_IRQSTAT_CEBE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
+ *
+ * Occurs if a Command Index error occurs in the command response.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_CIE field. */
+#define SDHC_RD_IRQSTAT_CIE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_CIE_MASK) >> SDHC_IRQSTAT_CIE_SHIFT)
+#define SDHC_BRD_IRQSTAT_CIE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CIE_SHIFT))
+
+/*! @brief Set the CIE field to a new value. */
+#define SDHC_WR_IRQSTAT_CIE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_CIE(value)))
+#define SDHC_BWR_IRQSTAT_CIE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_CIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
+ *
+ * Occurs when detecting one of following time-out conditions. Busy time-out for
+ * R1b,R5b type Busy time-out after Write CRC status Read Data time-out
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DTOE field. */
+#define SDHC_RD_IRQSTAT_DTOE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DTOE_MASK) >> SDHC_IRQSTAT_DTOE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DTOE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DTOE_SHIFT))
+
+/*! @brief Set the DTOE field to a new value. */
+#define SDHC_WR_IRQSTAT_DTOE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DTOE(value)))
+#define SDHC_BWR_IRQSTAT_DTOE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
+ *
+ * Occurs when detecting a CRC error when transferring read data, which uses the
+ * DAT line, or when detecting the Write CRC status having a value other than
+ * 010.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DCE field. */
+#define SDHC_RD_IRQSTAT_DCE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DCE_MASK) >> SDHC_IRQSTAT_DCE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DCE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DCE_SHIFT))
+
+/*! @brief Set the DCE field to a new value. */
+#define SDHC_WR_IRQSTAT_DCE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DCE(value)))
+#define SDHC_BWR_IRQSTAT_DCE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
+ *
+ * Occurs either when detecting 0 at the end bit position of read data, which
+ * uses the DAT line, or at the end bit position of the CRC.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DEBE field. */
+#define SDHC_RD_IRQSTAT_DEBE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DEBE_MASK) >> SDHC_IRQSTAT_DEBE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DEBE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DEBE_SHIFT))
+
+/*! @brief Set the DEBE field to a new value. */
+#define SDHC_WR_IRQSTAT_DEBE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_DEBE(value)))
+#define SDHC_BWR_IRQSTAT_DEBE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
+ *
+ * Occurs when detecting that one of the bits in the Auto CMD12 Error Status
+ * register has changed from 0 to 1. This bit is set to 1, not only when the errors
+ * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
+ * previous command error.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_AC12E field. */
+#define SDHC_RD_IRQSTAT_AC12E(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_AC12E_MASK) >> SDHC_IRQSTAT_AC12E_SHIFT)
+#define SDHC_BRD_IRQSTAT_AC12E(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_AC12E_SHIFT))
+
+/*! @brief Set the AC12E field to a new value. */
+#define SDHC_WR_IRQSTAT_AC12E(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_AC12E_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_DMAE_MASK), SDHC_IRQSTAT_AC12E(value)))
+#define SDHC_BWR_IRQSTAT_AC12E(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_AC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
+ *
+ * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
+ * some error occurs in the data transfer. This error can be caused by either
+ * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
+ * Address register is the next fetch address where the error occurs. Because any
+ * error corrupts the whole data block, the host driver shall restart the transfer
+ * from the corrupted block boundary. The address of the block boundary can be
+ * calculated either from the current DSADDR value or from the remaining number of
+ * blocks and the block size.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTAT_DMAE field. */
+#define SDHC_RD_IRQSTAT_DMAE(base) ((SDHC_IRQSTAT_REG(base) & SDHC_IRQSTAT_DMAE_MASK) >> SDHC_IRQSTAT_DMAE_SHIFT)
+#define SDHC_BRD_IRQSTAT_DMAE(base) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DMAE_SHIFT))
+
+/*! @brief Set the DMAE field to a new value. */
+#define SDHC_WR_IRQSTAT_DMAE(base, value) (SDHC_RMW_IRQSTAT(base, (SDHC_IRQSTAT_DMAE_MASK | SDHC_IRQSTAT_CC_MASK | SDHC_IRQSTAT_TC_MASK | SDHC_IRQSTAT_BGE_MASK | SDHC_IRQSTAT_DINT_MASK | SDHC_IRQSTAT_BWR_MASK | SDHC_IRQSTAT_BRR_MASK | SDHC_IRQSTAT_CINS_MASK | SDHC_IRQSTAT_CRM_MASK | SDHC_IRQSTAT_CINT_MASK | SDHC_IRQSTAT_CTOE_MASK | SDHC_IRQSTAT_CCE_MASK | SDHC_IRQSTAT_CEBE_MASK | SDHC_IRQSTAT_CIE_MASK | SDHC_IRQSTAT_DTOE_MASK | SDHC_IRQSTAT_DCE_MASK | SDHC_IRQSTAT_DEBE_MASK | SDHC_IRQSTAT_AC12E_MASK), SDHC_IRQSTAT_DMAE(value)))
+#define SDHC_BWR_IRQSTAT_DMAE(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTAT_REG(base), SDHC_IRQSTAT_DMAE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSTATEN - Interrupt Status Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
+ *
+ * Reset value: 0x117F013FU
+ *
+ * Setting the bits in this register to 1 enables the corresponding interrupt
+ * status to be set by the specified event. If any bit is cleared, the
+ * corresponding interrupt status bit is also cleared, that is, when the bit in this register
+ * is cleared, the corresponding bit in interrupt status register is always 0.
+ * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
+ * card interrupt signal during the interrupt period and hold its value in the
+ * flip-flop. There will be some delays on the card interrupt, asserted from the card,
+ * to the time the host system is informed. To detect a CMD line conflict, the
+ * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSTATEN register
+ */
+/*@{*/
+#define SDHC_RD_IRQSTATEN(base)  (SDHC_IRQSTATEN_REG(base))
+#define SDHC_WR_IRQSTATEN(base, value) (SDHC_IRQSTATEN_REG(base) = (value))
+#define SDHC_RMW_IRQSTATEN(base, mask, value) (SDHC_WR_IRQSTATEN(base, (SDHC_RD_IRQSTATEN(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) |  (value)))
+#define SDHC_CLR_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) & ~(value)))
+#define SDHC_TOG_IRQSTATEN(base, value) (SDHC_WR_IRQSTATEN(base, SDHC_RD_IRQSTATEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSTATEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field. */
+#define SDHC_RD_IRQSTATEN_CCSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CCSEN_MASK) >> SDHC_IRQSTATEN_CCSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CCSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCSEN_SHIFT))
+
+/*! @brief Set the CCSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CCSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CCSEN_MASK, SDHC_IRQSTATEN_CCSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CCSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field. */
+#define SDHC_RD_IRQSTATEN_TCSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_TCSEN_MASK) >> SDHC_IRQSTATEN_TCSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_TCSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_TCSEN_SHIFT))
+
+/*! @brief Set the TCSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_TCSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_TCSEN_MASK, SDHC_IRQSTATEN_TCSEN(value)))
+#define SDHC_BWR_IRQSTATEN_TCSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_TCSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field. */
+#define SDHC_RD_IRQSTATEN_BGESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BGESEN_MASK) >> SDHC_IRQSTATEN_BGESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BGESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BGESEN_SHIFT))
+
+/*! @brief Set the BGESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BGESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BGESEN_MASK, SDHC_IRQSTATEN_BGESEN(value)))
+#define SDHC_BWR_IRQSTATEN_BGESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BGESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field. */
+#define SDHC_RD_IRQSTATEN_DINTSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DINTSEN_MASK) >> SDHC_IRQSTATEN_DINTSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DINTSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DINTSEN_SHIFT))
+
+/*! @brief Set the DINTSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DINTSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DINTSEN_MASK, SDHC_IRQSTATEN_DINTSEN(value)))
+#define SDHC_BWR_IRQSTATEN_DINTSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DINTSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field. */
+#define SDHC_RD_IRQSTATEN_BWRSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BWRSEN_MASK) >> SDHC_IRQSTATEN_BWRSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BWRSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BWRSEN_SHIFT))
+
+/*! @brief Set the BWRSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BWRSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BWRSEN_MASK, SDHC_IRQSTATEN_BWRSEN(value)))
+#define SDHC_BWR_IRQSTATEN_BWRSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BWRSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field. */
+#define SDHC_RD_IRQSTATEN_BRRSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_BRRSEN_MASK) >> SDHC_IRQSTATEN_BRRSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_BRRSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BRRSEN_SHIFT))
+
+/*! @brief Set the BRRSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_BRRSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_BRRSEN_MASK, SDHC_IRQSTATEN_BRRSEN(value)))
+#define SDHC_BWR_IRQSTATEN_BRRSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_BRRSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field. */
+#define SDHC_RD_IRQSTATEN_CINSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CINSEN_MASK) >> SDHC_IRQSTATEN_CINSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CINSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINSEN_SHIFT))
+
+/*! @brief Set the CINSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CINSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CINSEN_MASK, SDHC_IRQSTATEN_CINSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CINSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field. */
+#define SDHC_RD_IRQSTATEN_CRMSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CRMSEN_MASK) >> SDHC_IRQSTATEN_CRMSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CRMSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CRMSEN_SHIFT))
+
+/*! @brief Set the CRMSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CRMSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CRMSEN_MASK, SDHC_IRQSTATEN_CRMSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CRMSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CRMSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
+ *
+ * If this bit is set to 0, the SDHC will clear the interrupt request to the
+ * system. The card interrupt detection is stopped when this bit is cleared and
+ * restarted when this bit is set to 1. The host driver must clear the this bit
+ * before servicing the card interrupt and must set this bit again after all interrupt
+ * requests from the card are cleared to prevent inadvertent interrupts.
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field. */
+#define SDHC_RD_IRQSTATEN_CINTSEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CINTSEN_MASK) >> SDHC_IRQSTATEN_CINTSEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CINTSEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINTSEN_SHIFT))
+
+/*! @brief Set the CINTSEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CINTSEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CINTSEN_MASK, SDHC_IRQSTATEN_CINTSEN(value)))
+#define SDHC_BWR_IRQSTATEN_CINTSEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CINTSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field. */
+#define SDHC_RD_IRQSTATEN_CTOESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CTOESEN_MASK) >> SDHC_IRQSTATEN_CTOESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CTOESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CTOESEN_SHIFT))
+
+/*! @brief Set the CTOESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CTOESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CTOESEN_MASK, SDHC_IRQSTATEN_CTOESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CTOESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CTOESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field. */
+#define SDHC_RD_IRQSTATEN_CCESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CCESEN_MASK) >> SDHC_IRQSTATEN_CCESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CCESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCESEN_SHIFT))
+
+/*! @brief Set the CCESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CCESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CCESEN_MASK, SDHC_IRQSTATEN_CCESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CCESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CCESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field. */
+#define SDHC_RD_IRQSTATEN_CEBESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CEBESEN_MASK) >> SDHC_IRQSTATEN_CEBESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CEBESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CEBESEN_SHIFT))
+
+/*! @brief Set the CEBESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CEBESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CEBESEN_MASK, SDHC_IRQSTATEN_CEBESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CEBESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CEBESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field. */
+#define SDHC_RD_IRQSTATEN_CIESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_CIESEN_MASK) >> SDHC_IRQSTATEN_CIESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_CIESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CIESEN_SHIFT))
+
+/*! @brief Set the CIESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_CIESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_CIESEN_MASK, SDHC_IRQSTATEN_CIESEN(value)))
+#define SDHC_BWR_IRQSTATEN_CIESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_CIESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field. */
+#define SDHC_RD_IRQSTATEN_DTOESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DTOESEN_MASK) >> SDHC_IRQSTATEN_DTOESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DTOESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DTOESEN_SHIFT))
+
+/*! @brief Set the DTOESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DTOESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DTOESEN_MASK, SDHC_IRQSTATEN_DTOESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DTOESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DTOESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field. */
+#define SDHC_RD_IRQSTATEN_DCESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DCESEN_MASK) >> SDHC_IRQSTATEN_DCESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DCESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DCESEN_SHIFT))
+
+/*! @brief Set the DCESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DCESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DCESEN_MASK, SDHC_IRQSTATEN_DCESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DCESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DCESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field. */
+#define SDHC_RD_IRQSTATEN_DEBESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DEBESEN_MASK) >> SDHC_IRQSTATEN_DEBESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DEBESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DEBESEN_SHIFT))
+
+/*! @brief Set the DEBESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DEBESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DEBESEN_MASK, SDHC_IRQSTATEN_DEBESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DEBESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DEBESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field. */
+#define SDHC_RD_IRQSTATEN_AC12ESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_AC12ESEN_MASK) >> SDHC_IRQSTATEN_AC12ESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_AC12ESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_AC12ESEN_SHIFT))
+
+/*! @brief Set the AC12ESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_AC12ESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_AC12ESEN_MASK, SDHC_IRQSTATEN_AC12ESEN(value)))
+#define SDHC_BWR_IRQSTATEN_AC12ESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_AC12ESEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field. */
+#define SDHC_RD_IRQSTATEN_DMAESEN(base) ((SDHC_IRQSTATEN_REG(base) & SDHC_IRQSTATEN_DMAESEN_MASK) >> SDHC_IRQSTATEN_DMAESEN_SHIFT)
+#define SDHC_BRD_IRQSTATEN_DMAESEN(base) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DMAESEN_SHIFT))
+
+/*! @brief Set the DMAESEN field to a new value. */
+#define SDHC_WR_IRQSTATEN_DMAESEN(base, value) (SDHC_RMW_IRQSTATEN(base, SDHC_IRQSTATEN_DMAESEN_MASK, SDHC_IRQSTATEN_DMAESEN(value)))
+#define SDHC_BWR_IRQSTATEN_DMAESEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSTATEN_REG(base), SDHC_IRQSTATEN_DMAESEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_IRQSIGEN - Interrupt Signal Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register is used to select which interrupt status is indicated to the
+ * host system as the interrupt. All of these status bits share the same interrupt
+ * line. Setting any of these bits to 1 enables interrupt generation. The
+ * corresponding status register bit will generate an interrupt when the corresponding
+ * interrupt signal enable bit is set.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_IRQSIGEN register
+ */
+/*@{*/
+#define SDHC_RD_IRQSIGEN(base)   (SDHC_IRQSIGEN_REG(base))
+#define SDHC_WR_IRQSIGEN(base, value) (SDHC_IRQSIGEN_REG(base) = (value))
+#define SDHC_RMW_IRQSIGEN(base, mask, value) (SDHC_WR_IRQSIGEN(base, (SDHC_RD_IRQSIGEN(base) & ~(mask)) | (value)))
+#define SDHC_SET_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) |  (value)))
+#define SDHC_CLR_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) & ~(value)))
+#define SDHC_TOG_IRQSIGEN(base, value) (SDHC_WR_IRQSIGEN(base, SDHC_RD_IRQSIGEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_IRQSIGEN bitfields
+ */
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field. */
+#define SDHC_RD_IRQSIGEN_CCIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CCIEN_MASK) >> SDHC_IRQSIGEN_CCIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CCIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCIEN_SHIFT))
+
+/*! @brief Set the CCIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CCIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CCIEN_MASK, SDHC_IRQSIGEN_CCIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CCIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field. */
+#define SDHC_RD_IRQSIGEN_TCIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_TCIEN_MASK) >> SDHC_IRQSIGEN_TCIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_TCIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_TCIEN_SHIFT))
+
+/*! @brief Set the TCIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_TCIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_TCIEN_MASK, SDHC_IRQSIGEN_TCIEN(value)))
+#define SDHC_BWR_IRQSIGEN_TCIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_TCIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field. */
+#define SDHC_RD_IRQSIGEN_BGEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BGEIEN_MASK) >> SDHC_IRQSIGEN_BGEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BGEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BGEIEN_SHIFT))
+
+/*! @brief Set the BGEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BGEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BGEIEN_MASK, SDHC_IRQSIGEN_BGEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BGEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BGEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field. */
+#define SDHC_RD_IRQSIGEN_DINTIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DINTIEN_MASK) >> SDHC_IRQSIGEN_DINTIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DINTIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DINTIEN_SHIFT))
+
+/*! @brief Set the DINTIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DINTIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DINTIEN_MASK, SDHC_IRQSIGEN_DINTIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DINTIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DINTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field. */
+#define SDHC_RD_IRQSIGEN_BWRIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BWRIEN_MASK) >> SDHC_IRQSIGEN_BWRIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BWRIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BWRIEN_SHIFT))
+
+/*! @brief Set the BWRIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BWRIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BWRIEN_MASK, SDHC_IRQSIGEN_BWRIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BWRIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BWRIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field. */
+#define SDHC_RD_IRQSIGEN_BRRIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_BRRIEN_MASK) >> SDHC_IRQSIGEN_BRRIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_BRRIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BRRIEN_SHIFT))
+
+/*! @brief Set the BRRIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_BRRIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_BRRIEN_MASK, SDHC_IRQSIGEN_BRRIEN(value)))
+#define SDHC_BWR_IRQSIGEN_BRRIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_BRRIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field. */
+#define SDHC_RD_IRQSIGEN_CINSIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CINSIEN_MASK) >> SDHC_IRQSIGEN_CINSIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CINSIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINSIEN_SHIFT))
+
+/*! @brief Set the CINSIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CINSIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CINSIEN_MASK, SDHC_IRQSIGEN_CINSIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CINSIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINSIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field. */
+#define SDHC_RD_IRQSIGEN_CRMIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CRMIEN_MASK) >> SDHC_IRQSIGEN_CRMIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CRMIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CRMIEN_SHIFT))
+
+/*! @brief Set the CRMIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CRMIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CRMIEN_MASK, SDHC_IRQSIGEN_CRMIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CRMIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CRMIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field. */
+#define SDHC_RD_IRQSIGEN_CINTIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CINTIEN_MASK) >> SDHC_IRQSIGEN_CINTIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CINTIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINTIEN_SHIFT))
+
+/*! @brief Set the CINTIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CINTIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CINTIEN_MASK, SDHC_IRQSIGEN_CINTIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CINTIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CINTIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field. */
+#define SDHC_RD_IRQSIGEN_CTOEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CTOEIEN_MASK) >> SDHC_IRQSIGEN_CTOEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CTOEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CTOEIEN_SHIFT))
+
+/*! @brief Set the CTOEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CTOEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CTOEIEN_MASK, SDHC_IRQSIGEN_CTOEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CTOEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CTOEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field. */
+#define SDHC_RD_IRQSIGEN_CCEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CCEIEN_MASK) >> SDHC_IRQSIGEN_CCEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CCEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCEIEN_SHIFT))
+
+/*! @brief Set the CCEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CCEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CCEIEN_MASK, SDHC_IRQSIGEN_CCEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CCEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CCEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field. */
+#define SDHC_RD_IRQSIGEN_CEBEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CEBEIEN_MASK) >> SDHC_IRQSIGEN_CEBEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CEBEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CEBEIEN_SHIFT))
+
+/*! @brief Set the CEBEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CEBEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CEBEIEN_MASK, SDHC_IRQSIGEN_CEBEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CEBEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CEBEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field. */
+#define SDHC_RD_IRQSIGEN_CIEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_CIEIEN_MASK) >> SDHC_IRQSIGEN_CIEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_CIEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CIEIEN_SHIFT))
+
+/*! @brief Set the CIEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_CIEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_CIEIEN_MASK, SDHC_IRQSIGEN_CIEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_CIEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_CIEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field. */
+#define SDHC_RD_IRQSIGEN_DTOEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DTOEIEN_MASK) >> SDHC_IRQSIGEN_DTOEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DTOEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DTOEIEN_SHIFT))
+
+/*! @brief Set the DTOEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DTOEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DTOEIEN_MASK, SDHC_IRQSIGEN_DTOEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DTOEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DTOEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field. */
+#define SDHC_RD_IRQSIGEN_DCEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DCEIEN_MASK) >> SDHC_IRQSIGEN_DCEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DCEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DCEIEN_SHIFT))
+
+/*! @brief Set the DCEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DCEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DCEIEN_MASK, SDHC_IRQSIGEN_DCEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DCEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DCEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field. */
+#define SDHC_RD_IRQSIGEN_DEBEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DEBEIEN_MASK) >> SDHC_IRQSIGEN_DEBEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DEBEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DEBEIEN_SHIFT))
+
+/*! @brief Set the DEBEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DEBEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DEBEIEN_MASK, SDHC_IRQSIGEN_DEBEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DEBEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DEBEIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field. */
+#define SDHC_RD_IRQSIGEN_AC12EIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_AC12EIEN_MASK) >> SDHC_IRQSIGEN_AC12EIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_AC12EIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_AC12EIEN_SHIFT))
+
+/*! @brief Set the AC12EIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_AC12EIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_AC12EIEN_MASK, SDHC_IRQSIGEN_AC12EIEN(value)))
+#define SDHC_BWR_IRQSIGEN_AC12EIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_AC12EIEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
+ *
+ * Values:
+ * - 0b0 - Masked
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field. */
+#define SDHC_RD_IRQSIGEN_DMAEIEN(base) ((SDHC_IRQSIGEN_REG(base) & SDHC_IRQSIGEN_DMAEIEN_MASK) >> SDHC_IRQSIGEN_DMAEIEN_SHIFT)
+#define SDHC_BRD_IRQSIGEN_DMAEIEN(base) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DMAEIEN_SHIFT))
+
+/*! @brief Set the DMAEIEN field to a new value. */
+#define SDHC_WR_IRQSIGEN_DMAEIEN(base, value) (SDHC_RMW_IRQSIGEN(base, SDHC_IRQSIGEN_DMAEIEN_MASK, SDHC_IRQSIGEN_DMAEIEN(value)))
+#define SDHC_BWR_IRQSIGEN_DMAEIEN(base, value) (BITBAND_ACCESS32(&SDHC_IRQSIGEN_REG(base), SDHC_IRQSIGEN_DMAEIEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_AC12ERR - Auto CMD12 Error Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When the AC12ESEN bit in the Status register is set, the host driver shall
+ * check this register to identify what kind of error the Auto CMD12 indicated.
+ * This register is valid only when the Auto CMD12 Error status bit is set. The
+ * following table shows the relationship between the Auto CMGD12 CRC error and the
+ * Auto CMD12 command timeout error. Relationship between Command CRC Error and
+ * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
+ * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
+ * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
+ * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
+ * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
+ * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
+ * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
+ * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
+ * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
+ * command that can't be issued. Clear bit 7 if there is no command to issue. The
+ * timing for generating the auto CMD12 error and writing to the command register
+ * are asynchronous. After that, bit 7 shall be sampled when the driver is not
+ * writing to the command register. So it is suggested to read this register only
+ * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
+ * of the error bits (0-4) is set to 1. The command not issued by auto CMD12
+ * error does not generate an interrupt.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_AC12ERR register
+ */
+/*@{*/
+#define SDHC_RD_AC12ERR(base)    (SDHC_AC12ERR_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_AC12ERR bitfields
+ */
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
+ *
+ * If memory multiple block data transfer is not started, due to a command
+ * error, this bit is not set because it is not necessary to issue an auto CMD12.
+ * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
+ * multiple block data transfer due to some error. If this bit is set to 1, other
+ * error status bits (1-4) have no meaning.
+ *
+ * Values:
+ * - 0b0 - Executed.
+ * - 0b1 - Not executed.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12NE field. */
+#define SDHC_RD_AC12ERR_AC12NE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12NE_MASK) >> SDHC_AC12ERR_AC12NE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12NE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12NE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
+ *
+ * Occurs if no response is returned within 64 SDCLK cycles from the end bit of
+ * the command. If this bit is set to 1, the other error status bits (2-4) have
+ * no meaning.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Time out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12TOE field. */
+#define SDHC_RD_AC12ERR_AC12TOE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12TOE_MASK) >> SDHC_AC12ERR_AC12TOE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12TOE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12TOE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
+ *
+ * Occurs when detecting that the end bit of command response is 0 which must be
+ * 1.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - End bit error generated.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12EBE field. */
+#define SDHC_RD_AC12ERR_AC12EBE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12EBE_MASK) >> SDHC_AC12ERR_AC12EBE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12EBE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12EBE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
+ *
+ * Occurs when detecting a CRC error in the command response.
+ *
+ * Values:
+ * - 0b0 - No CRC error.
+ * - 0b1 - CRC error met in Auto CMD12 response.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12CE field. */
+#define SDHC_RD_AC12ERR_AC12CE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12CE_MASK) >> SDHC_AC12ERR_AC12CE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12CE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12CE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
+ *
+ * Occurs if the command index error occurs in response to a command.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error, the CMD index in response is not CMD12.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_AC12IE field. */
+#define SDHC_RD_AC12ERR_AC12IE(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_AC12IE_MASK) >> SDHC_AC12ERR_AC12IE_SHIFT)
+#define SDHC_BRD_AC12ERR_AC12IE(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_AC12IE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
+ *
+ * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
+ * error (D04-D01) in this register.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Not issued.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field. */
+#define SDHC_RD_AC12ERR_CNIBAC12E(base) ((SDHC_AC12ERR_REG(base) & SDHC_AC12ERR_CNIBAC12E_MASK) >> SDHC_AC12ERR_CNIBAC12E_SHIFT)
+#define SDHC_BRD_AC12ERR_CNIBAC12E(base) (BITBAND_ACCESS32(&SDHC_AC12ERR_REG(base), SDHC_AC12ERR_CNIBAC12E_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_HTCAPBLT - Host Controller Capabilities
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_HTCAPBLT - Host Controller Capabilities (RO)
+ *
+ * Reset value: 0x07F30000U
+ *
+ * This register provides the host driver with information specific to the SDHC
+ * implementation. The value in this register is the power-on-reset value, and
+ * does not change with a software reset. Any write to this register is ignored.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_HTCAPBLT register
+ */
+/*@{*/
+#define SDHC_RD_HTCAPBLT(base)   (SDHC_HTCAPBLT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_HTCAPBLT bitfields
+ */
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
+ *
+ * This value indicates the maximum block size that the host driver can read and
+ * write to the buffer in the SDHC. The buffer shall transfer block size without
+ * wait cycles.
+ *
+ * Values:
+ * - 0b000 - 512 bytes
+ * - 0b001 - 1024 bytes
+ * - 0b010 - 2048 bytes
+ * - 0b011 - 4096 bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_MBL field. */
+#define SDHC_RD_HTCAPBLT_MBL(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_MBL_MASK) >> SDHC_HTCAPBLT_MBL_SHIFT)
+#define SDHC_BRD_HTCAPBLT_MBL(base) (SDHC_RD_HTCAPBLT_MBL(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
+ *
+ * This bit indicates whether the SDHC supports the ADMA feature.
+ *
+ * Values:
+ * - 0b0 - Advanced DMA not supported.
+ * - 0b1 - Advanced DMA supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field. */
+#define SDHC_RD_HTCAPBLT_ADMAS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_ADMAS_MASK) >> SDHC_HTCAPBLT_ADMAS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_ADMAS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_ADMAS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
+ *
+ * This bit indicates whether the SDHC supports high speed mode and the host
+ * system can supply a SD Clock frequency from 25 MHz to 50 MHz.
+ *
+ * Values:
+ * - 0b0 - High speed not supported.
+ * - 0b1 - High speed supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_HSS field. */
+#define SDHC_RD_HTCAPBLT_HSS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_HSS_MASK) >> SDHC_HTCAPBLT_HSS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_HSS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_HSS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
+ *
+ * This bit indicates whether the SDHC is capable of using the internal DMA to
+ * transfer data between system memory and the data buffer directly.
+ *
+ * Values:
+ * - 0b0 - DMA not supported.
+ * - 0b1 - DMA supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_DMAS field. */
+#define SDHC_RD_HTCAPBLT_DMAS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_DMAS_MASK) >> SDHC_HTCAPBLT_DMAS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_DMAS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_DMAS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
+ *
+ * This bit indicates whether the SDHC supports suspend / resume functionality.
+ * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
+ * are not supported, and the host driver shall not issue either suspend or
+ * resume commands.
+ *
+ * Values:
+ * - 0b0 - Not supported.
+ * - 0b1 - Supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_SRS field. */
+#define SDHC_RD_HTCAPBLT_SRS(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_SRS_MASK) >> SDHC_HTCAPBLT_SRS_SHIFT)
+#define SDHC_BRD_HTCAPBLT_SRS(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_SRS_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
+ *
+ * This bit shall depend on the host system ability.
+ *
+ * Values:
+ * - 0b0 - 3.3 V not supported.
+ * - 0b1 - 3.3 V supported.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HTCAPBLT_VS33 field. */
+#define SDHC_RD_HTCAPBLT_VS33(base) ((SDHC_HTCAPBLT_REG(base) & SDHC_HTCAPBLT_VS33_MASK) >> SDHC_HTCAPBLT_VS33_SHIFT)
+#define SDHC_BRD_HTCAPBLT_VS33(base) (BITBAND_ACCESS32(&SDHC_HTCAPBLT_REG(base), SDHC_HTCAPBLT_VS33_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_WML - Watermark Level Register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_WML - Watermark Level Register (RW)
+ *
+ * Reset value: 0x00100010U
+ *
+ * Both write and read watermark levels (FIFO threshold) are configurable. There
+ * value can range from 1 to 128 words. Both write and read burst lengths are
+ * also configurable. There value can range from 1 to 31 words.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_WML register
+ */
+/*@{*/
+#define SDHC_RD_WML(base)        (SDHC_WML_REG(base))
+#define SDHC_WR_WML(base, value) (SDHC_WML_REG(base) = (value))
+#define SDHC_RMW_WML(base, mask, value) (SDHC_WR_WML(base, (SDHC_RD_WML(base) & ~(mask)) | (value)))
+#define SDHC_SET_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) |  (value)))
+#define SDHC_CLR_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) & ~(value)))
+#define SDHC_TOG_WML(base, value) (SDHC_WR_WML(base, SDHC_RD_WML(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_WML bitfields
+ */
+
+/*!
+ * @name Register SDHC_WML, field RDWML[7:0] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * read operation. Also the number of words as a sequence of read bursts in
+ * back-to-back mode. The maximum legal value for the read water mark level is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_WML_RDWML field. */
+#define SDHC_RD_WML_RDWML(base) ((SDHC_WML_REG(base) & SDHC_WML_RDWML_MASK) >> SDHC_WML_RDWML_SHIFT)
+#define SDHC_BRD_WML_RDWML(base) (SDHC_RD_WML_RDWML(base))
+
+/*! @brief Set the RDWML field to a new value. */
+#define SDHC_WR_WML_RDWML(base, value) (SDHC_RMW_WML(base, SDHC_WML_RDWML_MASK, SDHC_WML_RDWML(value)))
+#define SDHC_BWR_WML_RDWML(base, value) (SDHC_WR_WML_RDWML(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_WML, field WRWML[23:16] (RW)
+ *
+ * The number of words used as the watermark level (FIFO threshold) in a DMA
+ * write operation. Also the number of words as a sequence of write bursts in
+ * back-to-back mode. The maximum legal value for the write watermark level is 128.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_WML_WRWML field. */
+#define SDHC_RD_WML_WRWML(base) ((SDHC_WML_REG(base) & SDHC_WML_WRWML_MASK) >> SDHC_WML_WRWML_SHIFT)
+#define SDHC_BRD_WML_WRWML(base) (SDHC_RD_WML_WRWML(base))
+
+/*! @brief Set the WRWML field to a new value. */
+#define SDHC_WR_WML_WRWML(base, value) (SDHC_RMW_WML(base, SDHC_WML_WRWML_MASK, SDHC_WML_WRWML(value)))
+#define SDHC_BWR_WML_WRWML(base, value) (SDHC_WR_WML_WRWML(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_FEVT - Force Event register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_FEVT - Force Event register (WO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The Force Event (FEVT) register is not a physically implemented register.
+ * Rather, it is an address at which the Interrupt Status register can be written if
+ * the corresponding bit of the Interrupt Status Enable register is set. This
+ * register is a write only register and writing 0 to it has no effect. Writing 1
+ * to this register actually sets the corresponding bit of Interrupt Status
+ * register. A read from this register always results in 0's. To change the
+ * corresponding status bits in the interrupt status register, make sure to set
+ * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
+ * short pulse on the DAT[1] line, and the driver may treat this interrupt as a
+ * normal interrupt. The interrupt service routine may skip polling the card
+ * interrupt factor as the interrupt is selfcleared.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_FEVT register
+ */
+/*@{*/
+#define SDHC_RD_FEVT(base)       (SDHC_FEVT_REG(base))
+#define SDHC_WR_FEVT(base, value) (SDHC_FEVT_REG(base) = (value))
+#define SDHC_RMW_FEVT(base, mask, value) (SDHC_WR_FEVT(base, (SDHC_RD_FEVT(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_FEVT bitfields
+ */
+
+/*!
+ * @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
+ *
+ * Forces AC12ERR[AC12NE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12NE field to a new value. */
+#define SDHC_WR_FEVT_AC12NE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12NE_MASK, SDHC_FEVT_AC12NE(value)))
+#define SDHC_BWR_FEVT_AC12NE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12NE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
+ *
+ * Forces AC12ERR[AC12TOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12TOE field to a new value. */
+#define SDHC_WR_FEVT_AC12TOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12TOE_MASK, SDHC_FEVT_AC12TOE(value)))
+#define SDHC_BWR_FEVT_AC12TOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12TOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
+ *
+ * Forces AC12ERR[AC12CE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12CE field to a new value. */
+#define SDHC_WR_FEVT_AC12CE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12CE_MASK, SDHC_FEVT_AC12CE(value)))
+#define SDHC_BWR_FEVT_AC12CE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12CE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
+ *
+ * Forces AC12ERR[AC12EBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12EBE field to a new value. */
+#define SDHC_WR_FEVT_AC12EBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12EBE_MASK, SDHC_FEVT_AC12EBE(value)))
+#define SDHC_BWR_FEVT_AC12EBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12EBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
+ *
+ * Forces AC12ERR[AC12IE] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12IE field to a new value. */
+#define SDHC_WR_FEVT_AC12IE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12IE_MASK, SDHC_FEVT_AC12IE(value)))
+#define SDHC_BWR_FEVT_AC12IE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
+ *
+ * Forces AC12ERR[CNIBAC12E] to be set.
+ */
+/*@{*/
+/*! @brief Set the CNIBAC12E field to a new value. */
+#define SDHC_WR_FEVT_CNIBAC12E(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CNIBAC12E_MASK, SDHC_FEVT_CNIBAC12E(value)))
+#define SDHC_BWR_FEVT_CNIBAC12E(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CNIBAC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CTOE[16] (WORZ)
+ *
+ * Forces IRQSTAT[CTOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CTOE field to a new value. */
+#define SDHC_WR_FEVT_CTOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CTOE_MASK, SDHC_FEVT_CTOE(value)))
+#define SDHC_BWR_FEVT_CTOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CCE[17] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CCE field to a new value. */
+#define SDHC_WR_FEVT_CCE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CCE_MASK, SDHC_FEVT_CCE(value)))
+#define SDHC_BWR_FEVT_CCE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CEBE[18] (WORZ)
+ *
+ * Forces IRQSTAT[CEBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CEBE field to a new value. */
+#define SDHC_WR_FEVT_CEBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CEBE_MASK, SDHC_FEVT_CEBE(value)))
+#define SDHC_BWR_FEVT_CEBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CIE[19] (WORZ)
+ *
+ * Forces IRQSTAT[CCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the CIE field to a new value. */
+#define SDHC_WR_FEVT_CIE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CIE_MASK, SDHC_FEVT_CIE(value)))
+#define SDHC_BWR_FEVT_CIE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DTOE[20] (WORZ)
+ *
+ * Forces IRQSTAT[DTOE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DTOE field to a new value. */
+#define SDHC_WR_FEVT_DTOE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DTOE_MASK, SDHC_FEVT_DTOE(value)))
+#define SDHC_BWR_FEVT_DTOE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DTOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DCE[21] (WORZ)
+ *
+ * Forces IRQSTAT[DCE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DCE field to a new value. */
+#define SDHC_WR_FEVT_DCE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DCE_MASK, SDHC_FEVT_DCE(value)))
+#define SDHC_BWR_FEVT_DCE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DCE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DEBE[22] (WORZ)
+ *
+ * Forces IRQSTAT[DEBE] to be set.
+ */
+/*@{*/
+/*! @brief Set the DEBE field to a new value. */
+#define SDHC_WR_FEVT_DEBE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DEBE_MASK, SDHC_FEVT_DEBE(value)))
+#define SDHC_BWR_FEVT_DEBE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DEBE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field AC12E[24] (WORZ)
+ *
+ * Forces IRQSTAT[AC12E] to be set.
+ */
+/*@{*/
+/*! @brief Set the AC12E field to a new value. */
+#define SDHC_WR_FEVT_AC12E(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_AC12E_MASK, SDHC_FEVT_AC12E(value)))
+#define SDHC_BWR_FEVT_AC12E(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_AC12E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field DMAE[28] (WORZ)
+ *
+ * Forces the DMAE bit of Interrupt Status Register to be set.
+ */
+/*@{*/
+/*! @brief Set the DMAE field to a new value. */
+#define SDHC_WR_FEVT_DMAE(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_DMAE_MASK, SDHC_FEVT_DMAE(value)))
+#define SDHC_BWR_FEVT_DMAE(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_DMAE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_FEVT, field CINT[31] (WORZ)
+ *
+ * Writing 1 to this bit generates a short low-level pulse on the internal
+ * DAT[1] line, as if a self-clearing interrupt was received from the external card.
+ * If enabled, the CINT bit will be set and the interrupt service routine may
+ * treat this interrupt as a normal interrupt from the external card.
+ */
+/*@{*/
+/*! @brief Set the CINT field to a new value. */
+#define SDHC_WR_FEVT_CINT(base, value) (SDHC_RMW_FEVT(base, SDHC_FEVT_CINT_MASK, SDHC_FEVT_CINT(value)))
+#define SDHC_BWR_FEVT_CINT(base, value) (BITBAND_ACCESS32(&SDHC_FEVT_REG(base), SDHC_FEVT_CINT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_ADMAES - ADMA Error Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_ADMAES - ADMA Error Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * When an ADMA error interrupt has occurred, the ADMA Error States field in
+ * this register holds the ADMA state and the ADMA System Address register holds the
+ * address around the error descriptor. For recovering from this error, the host
+ * driver requires the ADMA state to identify the error descriptor address as
+ * follows: ST_STOP: Previous location set in the ADMA System Address register is
+ * the error descriptor address. ST_FDS: Current location set in the ADMA System
+ * Address register is the error descriptor address. ST_CADR: This state is never
+ * set because it only increments the descriptor pointer and doesn't generate an
+ * ADMA error. ST_TFR: Previous location set in the ADMA System Address register
+ * is the error descriptor address. In case of a write operation, the host driver
+ * must use the ACMD22 to get the number of the written block, rather than using
+ * this information, because unwritten data may exist in the host controller.
+ * The host controller generates the ADMA error interrupt when it detects invalid
+ * descriptor data (valid = 0) in the ST_FDS state. The host driver can
+ * distinguish this error by reading the valid bit of the error descriptor. ADMA Error
+ * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
+ * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
+ * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
+ * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
+ * (Transfer Data) Holds the address of the next executable descriptor command
+ */
+/*!
+ * @name Constants and macros for entire SDHC_ADMAES register
+ */
+/*@{*/
+#define SDHC_RD_ADMAES(base)     (SDHC_ADMAES_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_ADMAES bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
+ *
+ * Indicates the state of the ADMA when an error has occurred during an ADMA
+ * data transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMAES field. */
+#define SDHC_RD_ADMAES_ADMAES(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMAES_MASK) >> SDHC_ADMAES_ADMAES_SHIFT)
+#define SDHC_BRD_ADMAES_ADMAES(base) (SDHC_RD_ADMAES_ADMAES(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMALME[2] (RO)
+ *
+ * This error occurs in the following 2 cases: While the block count enable is
+ * being set, the total data length specified by the descriptor table is different
+ * from that specified by the block count and block length. Total data length
+ * can not be divided by the block length.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMALME field. */
+#define SDHC_RD_ADMAES_ADMALME(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMALME_MASK) >> SDHC_ADMAES_ADMALME_SHIFT)
+#define SDHC_BRD_ADMAES_ADMALME(base) (BITBAND_ACCESS32(&SDHC_ADMAES_REG(base), SDHC_ADMAES_ADMALME_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
+ *
+ * This error occurs when an invalid descriptor is fetched by ADMA.
+ *
+ * Values:
+ * - 0b0 - No error.
+ * - 0b1 - Error.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADMAES_ADMADCE field. */
+#define SDHC_RD_ADMAES_ADMADCE(base) ((SDHC_ADMAES_REG(base) & SDHC_ADMAES_ADMADCE_MASK) >> SDHC_ADMAES_ADMADCE_SHIFT)
+#define SDHC_BRD_ADMAES_ADMADCE(base) (BITBAND_ACCESS32(&SDHC_ADMAES_REG(base), SDHC_ADMAES_ADMADCE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_ADSADDR - ADMA System Addressregister
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_ADSADDR - ADMA System Addressregister (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the physical system memory address used for ADMA
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_ADSADDR register
+ */
+/*@{*/
+#define SDHC_RD_ADSADDR(base)    (SDHC_ADSADDR_REG(base))
+#define SDHC_WR_ADSADDR(base, value) (SDHC_ADSADDR_REG(base) = (value))
+#define SDHC_RMW_ADSADDR(base, mask, value) (SDHC_WR_ADSADDR(base, (SDHC_RD_ADSADDR(base) & ~(mask)) | (value)))
+#define SDHC_SET_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) |  (value)))
+#define SDHC_CLR_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) & ~(value)))
+#define SDHC_TOG_ADSADDR(base, value) (SDHC_WR_ADSADDR(base, SDHC_RD_ADSADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_ADSADDR bitfields
+ */
+
+/*!
+ * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
+ *
+ * Holds the word address of the executing command in the descriptor table. At
+ * the start of ADMA, the host driver shall set the start address of the
+ * Descriptor table. The ADMA engine increments this register address whenever fetching a
+ * descriptor command. When the ADMA is stopped at the block gap, this register
+ * indicates the address of the next executable descriptor command. When the ADMA
+ * error interrupt is generated, this register shall hold the valid descriptor
+ * address depending on the ADMA state. The lower 2 bits of this register is tied
+ * to '0' so the ADMA address is always word-aligned. Because this register
+ * supports dynamic address reflecting, when TC bit is set, it automatically alters the
+ * value of internal address counter, so SW cannot change this register when TC
+ * bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_ADSADDR_ADSADDR field. */
+#define SDHC_RD_ADSADDR_ADSADDR(base) ((SDHC_ADSADDR_REG(base) & SDHC_ADSADDR_ADSADDR_MASK) >> SDHC_ADSADDR_ADSADDR_SHIFT)
+#define SDHC_BRD_ADSADDR_ADSADDR(base) (SDHC_RD_ADSADDR_ADSADDR(base))
+
+/*! @brief Set the ADSADDR field to a new value. */
+#define SDHC_WR_ADSADDR_ADSADDR(base, value) (SDHC_RMW_ADSADDR(base, SDHC_ADSADDR_ADSADDR_MASK, SDHC_ADSADDR_ADSADDR(value)))
+#define SDHC_BWR_ADSADDR_ADSADDR(base, value) (SDHC_WR_ADSADDR_ADSADDR(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_VENDOR - Vendor Specific register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_VENDOR - Vendor Specific register (RW)
+ *
+ * Reset value: 0x00000001U
+ *
+ * This register contains the vendor-specific control/status register.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_VENDOR register
+ */
+/*@{*/
+#define SDHC_RD_VENDOR(base)     (SDHC_VENDOR_REG(base))
+#define SDHC_WR_VENDOR(base, value) (SDHC_VENDOR_REG(base) = (value))
+#define SDHC_RMW_VENDOR(base, mask, value) (SDHC_WR_VENDOR(base, (SDHC_RD_VENDOR(base) & ~(mask)) | (value)))
+#define SDHC_SET_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) |  (value)))
+#define SDHC_CLR_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) & ~(value)))
+#define SDHC_TOG_VENDOR(base, value) (SDHC_WR_VENDOR(base, SDHC_RD_VENDOR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_VENDOR bitfields
+ */
+
+/*!
+ * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
+ *
+ * Enables the request to external DMA. When the internal DMA (either simple DMA
+ * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
+ * request when the internal buffer is ready. This bit is particularly useful when
+ * transferring data by CPU polling mode, and it is not allowed to send out the
+ * external DMA request. By default, this bit is set.
+ *
+ * Values:
+ * - 0b0 - In any scenario, SDHC does not send out the external DMA request.
+ * - 0b1 - When internal DMA is not active, the external DMA request will be
+ *     sent out.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field. */
+#define SDHC_RD_VENDOR_EXTDMAEN(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_EXTDMAEN_MASK) >> SDHC_VENDOR_EXTDMAEN_SHIFT)
+#define SDHC_BRD_VENDOR_EXTDMAEN(base) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXTDMAEN_SHIFT))
+
+/*! @brief Set the EXTDMAEN field to a new value. */
+#define SDHC_WR_VENDOR_EXTDMAEN(base, value) (SDHC_RMW_VENDOR(base, SDHC_VENDOR_EXTDMAEN_MASK, SDHC_VENDOR_EXTDMAEN(value)))
+#define SDHC_BWR_VENDOR_EXTDMAEN(base, value) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXTDMAEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
+ *
+ * This bit must be set before S/W issues CMD53 multi-block read with exact
+ * block number. This bit must not be set if the CMD53 multi-block read is not exact
+ * block number.
+ *
+ * Values:
+ * - 0b0 - None exact block read.
+ * - 0b1 - Exact block read for SDIO CMD53.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_EXBLKNU field. */
+#define SDHC_RD_VENDOR_EXBLKNU(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_EXBLKNU_MASK) >> SDHC_VENDOR_EXBLKNU_SHIFT)
+#define SDHC_BRD_VENDOR_EXBLKNU(base) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXBLKNU_SHIFT))
+
+/*! @brief Set the EXBLKNU field to a new value. */
+#define SDHC_WR_VENDOR_EXBLKNU(base, value) (SDHC_RMW_VENDOR(base, SDHC_VENDOR_EXBLKNU_MASK, SDHC_VENDOR_EXBLKNU(value)))
+#define SDHC_BWR_VENDOR_EXBLKNU(base, value) (BITBAND_ACCESS32(&SDHC_VENDOR_REG(base), SDHC_VENDOR_EXBLKNU_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
+ *
+ * Internal state value, reflecting the corresponding state value selected by
+ * Debug Select field. This field is read-only and write to this field does not
+ * have effect.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_VENDOR_INTSTVAL field. */
+#define SDHC_RD_VENDOR_INTSTVAL(base) ((SDHC_VENDOR_REG(base) & SDHC_VENDOR_INTSTVAL_MASK) >> SDHC_VENDOR_INTSTVAL_SHIFT)
+#define SDHC_BRD_VENDOR_INTSTVAL(base) (SDHC_RD_VENDOR_INTSTVAL(base))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_MMCBOOT - MMC Boot register
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_MMCBOOT - MMC Boot register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * This register contains the MMC fast boot control register.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_MMCBOOT register
+ */
+/*@{*/
+#define SDHC_RD_MMCBOOT(base)    (SDHC_MMCBOOT_REG(base))
+#define SDHC_WR_MMCBOOT(base, value) (SDHC_MMCBOOT_REG(base) = (value))
+#define SDHC_RMW_MMCBOOT(base, mask, value) (SDHC_WR_MMCBOOT(base, (SDHC_RD_MMCBOOT(base) & ~(mask)) | (value)))
+#define SDHC_SET_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) |  (value)))
+#define SDHC_CLR_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) & ~(value)))
+#define SDHC_TOG_MMCBOOT(base, value) (SDHC_WR_MMCBOOT(base, SDHC_RD_MMCBOOT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_MMCBOOT bitfields
+ */
+
+/*!
+ * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
+ *
+ * Values:
+ * - 0b0000 - SDCLK x 2^8
+ * - 0b0001 - SDCLK x 2^9
+ * - 0b0010 - SDCLK x 2^10
+ * - 0b0011 - SDCLK x 2^11
+ * - 0b0100 - SDCLK x 2^12
+ * - 0b0101 - SDCLK x 2^13
+ * - 0b0110 - SDCLK x 2^14
+ * - 0b0111 - SDCLK x 2^15
+ * - 0b1110 - SDCLK x 2^22
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field. */
+#define SDHC_RD_MMCBOOT_DTOCVACK(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_DTOCVACK_MASK) >> SDHC_MMCBOOT_DTOCVACK_SHIFT)
+#define SDHC_BRD_MMCBOOT_DTOCVACK(base) (SDHC_RD_MMCBOOT_DTOCVACK(base))
+
+/*! @brief Set the DTOCVACK field to a new value. */
+#define SDHC_WR_MMCBOOT_DTOCVACK(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_DTOCVACK_MASK, SDHC_MMCBOOT_DTOCVACK(value)))
+#define SDHC_BWR_MMCBOOT_DTOCVACK(base, value) (SDHC_WR_MMCBOOT_DTOCVACK(base, value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
+ *
+ * Values:
+ * - 0b0 - No ack.
+ * - 0b1 - Ack.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field. */
+#define SDHC_RD_MMCBOOT_BOOTACK(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTACK_MASK) >> SDHC_MMCBOOT_BOOTACK_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTACK(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTACK_SHIFT))
+
+/*! @brief Set the BOOTACK field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTACK(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTACK_MASK, SDHC_MMCBOOT_BOOTACK(value)))
+#define SDHC_BWR_MMCBOOT_BOOTACK(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Normal boot.
+ * - 0b1 - Alternative boot.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field. */
+#define SDHC_RD_MMCBOOT_BOOTMODE(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTMODE_MASK) >> SDHC_MMCBOOT_BOOTMODE_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTMODE(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTMODE_SHIFT))
+
+/*! @brief Set the BOOTMODE field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTMODE(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTMODE_MASK, SDHC_MMCBOOT_BOOTMODE(value)))
+#define SDHC_BWR_MMCBOOT_BOOTMODE(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTMODE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Fast boot disable.
+ * - 0b1 - Fast boot enable.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field. */
+#define SDHC_RD_MMCBOOT_BOOTEN(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTEN_MASK) >> SDHC_MMCBOOT_BOOTEN_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTEN(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTEN_SHIFT))
+
+/*! @brief Set the BOOTEN field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTEN(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTEN_MASK, SDHC_MMCBOOT_BOOTEN(value)))
+#define SDHC_BWR_MMCBOOT_BOOTEN(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_BOOTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
+ *
+ * When boot, enable auto stop at block gap function. This function will be
+ * triggered, and host will stop at block gap when received card block cnt is equal
+ * to BOOTBLKCNT.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field. */
+#define SDHC_RD_MMCBOOT_AUTOSABGEN(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_AUTOSABGEN_MASK) >> SDHC_MMCBOOT_AUTOSABGEN_SHIFT)
+#define SDHC_BRD_MMCBOOT_AUTOSABGEN(base) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_AUTOSABGEN_SHIFT))
+
+/*! @brief Set the AUTOSABGEN field to a new value. */
+#define SDHC_WR_MMCBOOT_AUTOSABGEN(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_AUTOSABGEN_MASK, SDHC_MMCBOOT_AUTOSABGEN(value)))
+#define SDHC_BWR_MMCBOOT_AUTOSABGEN(base, value) (BITBAND_ACCESS32(&SDHC_MMCBOOT_REG(base), SDHC_MMCBOOT_AUTOSABGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
+ *
+ * Defines the stop at block gap value of automatic mode. When received card
+ * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field. */
+#define SDHC_RD_MMCBOOT_BOOTBLKCNT(base) ((SDHC_MMCBOOT_REG(base) & SDHC_MMCBOOT_BOOTBLKCNT_MASK) >> SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)
+#define SDHC_BRD_MMCBOOT_BOOTBLKCNT(base) (SDHC_RD_MMCBOOT_BOOTBLKCNT(base))
+
+/*! @brief Set the BOOTBLKCNT field to a new value. */
+#define SDHC_WR_MMCBOOT_BOOTBLKCNT(base, value) (SDHC_RMW_MMCBOOT(base, SDHC_MMCBOOT_BOOTBLKCNT_MASK, SDHC_MMCBOOT_BOOTBLKCNT(value)))
+#define SDHC_BWR_MMCBOOT_BOOTBLKCNT(base, value) (SDHC_WR_MMCBOOT_BOOTBLKCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SDHC_HOSTVER - Host Controller Version
+ ******************************************************************************/
+
+/*!
+ * @brief SDHC_HOSTVER - Host Controller Version (RO)
+ *
+ * Reset value: 0x00001201U
+ *
+ * This register contains the vendor host controller version information. All
+ * bits are read only and will read the same as the power-reset value.
+ */
+/*!
+ * @name Constants and macros for entire SDHC_HOSTVER register
+ */
+/*@{*/
+#define SDHC_RD_HOSTVER(base)    (SDHC_HOSTVER_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SDHC_HOSTVER bitfields
+ */
+
+/*!
+ * @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
+ *
+ * These status bits indicate the host controller specification version.
+ *
+ * Values:
+ * - 0b00000001 - SD host specification version 2.0, supports test event
+ *     register and ADMA.
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HOSTVER_SVN field. */
+#define SDHC_RD_HOSTVER_SVN(base) ((SDHC_HOSTVER_REG(base) & SDHC_HOSTVER_SVN_MASK) >> SDHC_HOSTVER_SVN_SHIFT)
+#define SDHC_BRD_HOSTVER_SVN(base) (SDHC_RD_HOSTVER_SVN(base))
+/*@}*/
+
+/*!
+ * @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
+ *
+ * These status bits are reserved for the vendor version number. The host driver
+ * shall not use this status.
+ *
+ * Values:
+ * - 0b00000000 - Freescale SDHC version 1.0
+ * - 0b00010000 - Freescale SDHC version 2.0
+ * - 0b00010001 - Freescale SDHC version 2.1
+ * - 0b00010010 - Freescale SDHC version 2.2
+ */
+/*@{*/
+/*! @brief Read current value of the SDHC_HOSTVER_VVN field. */
+#define SDHC_RD_HOSTVER_VVN(base) ((SDHC_HOSTVER_REG(base) & SDHC_HOSTVER_VVN_MASK) >> SDHC_HOSTVER_VVN_SHIFT)
+#define SDHC_BRD_HOSTVER_VVN(base) (SDHC_RD_HOSTVER_VVN(base))
+/*@}*/
+
+/*
+ * MK64F12 SIM
+ *
+ * System Integration Module
+ *
+ * Registers defined in this header file:
+ * - SIM_SOPT1 - System Options Register 1
+ * - SIM_SOPT1CFG - SOPT1 Configuration Register
+ * - SIM_SOPT2 - System Options Register 2
+ * - SIM_SOPT4 - System Options Register 4
+ * - SIM_SOPT5 - System Options Register 5
+ * - SIM_SOPT7 - System Options Register 7
+ * - SIM_SDID - System Device Identification Register
+ * - SIM_SCGC1 - System Clock Gating Control Register 1
+ * - SIM_SCGC2 - System Clock Gating Control Register 2
+ * - SIM_SCGC3 - System Clock Gating Control Register 3
+ * - SIM_SCGC4 - System Clock Gating Control Register 4
+ * - SIM_SCGC5 - System Clock Gating Control Register 5
+ * - SIM_SCGC6 - System Clock Gating Control Register 6
+ * - SIM_SCGC7 - System Clock Gating Control Register 7
+ * - SIM_CLKDIV1 - System Clock Divider Register 1
+ * - SIM_CLKDIV2 - System Clock Divider Register 2
+ * - SIM_FCFG1 - Flash Configuration Register 1
+ * - SIM_FCFG2 - Flash Configuration Register 2
+ * - SIM_UIDH - Unique Identification Register High
+ * - SIM_UIDMH - Unique Identification Register Mid-High
+ * - SIM_UIDML - Unique Identification Register Mid Low
+ * - SIM_UIDL - Unique Identification Register Low
+ */
+
+#define SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */
+#define SIM_IDX (0U) /*!< Instance number for SIM. */
+
+/*******************************************************************************
+ * SIM_SOPT1 - System Options Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1 - System Options Register 1 (RW)
+ *
+ * Reset value: 0x80000000U
+ *
+ * The SOPT1 register is only reset on POR or LVD.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1 register
+ */
+/*@{*/
+#define SIM_RD_SOPT1(base)       (SIM_SOPT1_REG(base))
+#define SIM_WR_SOPT1(base, value) (SIM_SOPT1_REG(base) = (value))
+#define SIM_RMW_SOPT1(base, mask, value) (SIM_WR_SOPT1(base, (SIM_RD_SOPT1(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) |  (value)))
+#define SIM_CLR_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) & ~(value)))
+#define SIM_TOG_SOPT1(base, value) (SIM_WR_SOPT1(base, SIM_RD_SOPT1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
+ *
+ * This field specifies the amount of system RAM available on the device.
+ *
+ * Values:
+ * - 0b0001 - 8 KB
+ * - 0b0011 - 16 KB
+ * - 0b0100 - 24 KB
+ * - 0b0101 - 32 KB
+ * - 0b0110 - 48 KB
+ * - 0b0111 - 64 KB
+ * - 0b1000 - 96 KB
+ * - 0b1001 - 128 KB
+ * - 0b1011 - 256 KB
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */
+#define SIM_RD_SOPT1_RAMSIZE(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_RAMSIZE_MASK) >> SIM_SOPT1_RAMSIZE_SHIFT)
+#define SIM_BRD_SOPT1_RAMSIZE(base) (SIM_RD_SOPT1_RAMSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
+ *
+ * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
+ * only on POR/LVD.
+ *
+ * Values:
+ * - 0b00 - System oscillator (OSC32KCLK)
+ * - 0b01 - Reserved
+ * - 0b10 - RTC 32.768kHz oscillator
+ * - 0b11 - LPO 1 kHz
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */
+#define SIM_RD_SOPT1_OSC32KSEL(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
+#define SIM_BRD_SOPT1_OSC32KSEL(base) (SIM_RD_SOPT1_OSC32KSEL(base))
+
+/*! @brief Set the OSC32KSEL field to a new value. */
+#define SIM_WR_SOPT1_OSC32KSEL(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_OSC32KSEL_MASK, SIM_SOPT1_OSC32KSEL(value)))
+#define SIM_BWR_SOPT1_OSC32KSEL(base, value) (SIM_WR_SOPT1_OSC32KSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * VLPR and VLPW modes.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator not in standby during VLPR and VLPW modes.
+ * - 0b1 - USB voltage regulator in standby during VLPR and VLPW modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */
+#define SIM_RD_SOPT1_USBVSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBVSTBY_MASK) >> SIM_SOPT1_USBVSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBVSTBY(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT))
+
+/*! @brief Set the USBVSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBVSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBVSTBY_MASK, SIM_SOPT1_USBVSTBY(value)))
+#define SIM_BWR_SOPT1_USBVSTBY(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBVSTBY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
+ *
+ * Controls whether the USB voltage regulator is placed in standby mode during
+ * Stop, VLPS, LLS and VLLS modes.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ * - 0b1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS
+ *     modes.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */
+#define SIM_RD_SOPT1_USBSSTBY(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBSSTBY_MASK) >> SIM_SOPT1_USBSSTBY_SHIFT)
+#define SIM_BRD_SOPT1_USBSSTBY(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT))
+
+/*! @brief Set the USBSSTBY field to a new value. */
+#define SIM_WR_SOPT1_USBSSTBY(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBSSTBY_MASK, SIM_SOPT1_USBSSTBY(value)))
+#define SIM_BWR_SOPT1_USBSSTBY(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBSSTBY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
+ *
+ * Controls whether the USB voltage regulator is enabled.
+ *
+ * Values:
+ * - 0b0 - USB voltage regulator is disabled.
+ * - 0b1 - USB voltage regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */
+#define SIM_RD_SOPT1_USBREGEN(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_USBREGEN_MASK) >> SIM_SOPT1_USBREGEN_SHIFT)
+#define SIM_BRD_SOPT1_USBREGEN(base) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT))
+
+/*! @brief Set the USBREGEN field to a new value. */
+#define SIM_WR_SOPT1_USBREGEN(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_USBREGEN_MASK, SIM_SOPT1_USBREGEN(value)))
+#define SIM_BWR_SOPT1_USBREGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT1_REG(base), SIM_SOPT1_USBREGEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT1CFG - SOPT1 Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * The SOPT1CFG register is reset on System Reset not VLLS.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT1CFG register
+ */
+/*@{*/
+#define SIM_RD_SOPT1CFG(base)    (SIM_SOPT1CFG_REG(base))
+#define SIM_WR_SOPT1CFG(base, value) (SIM_SOPT1CFG_REG(base) = (value))
+#define SIM_RMW_SOPT1CFG(base, mask, value) (SIM_WR_SOPT1CFG(base, (SIM_RD_SOPT1CFG(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) |  (value)))
+#define SIM_CLR_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) & ~(value)))
+#define SIM_TOG_SOPT1CFG(base, value) (SIM_WR_SOPT1CFG(base, SIM_RD_SOPT1CFG(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT1CFG bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
+ *
+ * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
+ * register bit clears after a write to USBREGEN.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBREGEN cannot be written.
+ * - 0b1 - SOPT1 USBREGEN can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */
+#define SIM_RD_SOPT1CFG_URWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_URWE_MASK) >> SIM_SOPT1CFG_URWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_URWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT))
+
+/*! @brief Set the URWE field to a new value. */
+#define SIM_WR_SOPT1CFG_URWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_URWE_MASK, SIM_SOPT1CFG_URWE(value)))
+#define SIM_BWR_SOPT1CFG_URWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_URWE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
+ *
+ * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
+ * This register bit clears after a write to USBVSTBY.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBVSTBY cannot be written.
+ * - 0b1 - SOPT1 USBVSTBY can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */
+#define SIM_RD_SOPT1CFG_UVSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_UVSWE_MASK) >> SIM_SOPT1CFG_UVSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_UVSWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT))
+
+/*! @brief Set the UVSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_UVSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_UVSWE_MASK, SIM_SOPT1CFG_UVSWE(value)))
+#define SIM_BWR_SOPT1CFG_UVSWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_UVSWE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
+ *
+ * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
+ * This register bit clears after a write to USBSSTBY.
+ *
+ * Values:
+ * - 0b0 - SOPT1 USBSSTBY cannot be written.
+ * - 0b1 - SOPT1 USBSSTBY can be written.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */
+#define SIM_RD_SOPT1CFG_USSWE(base) ((SIM_SOPT1CFG_REG(base) & SIM_SOPT1CFG_USSWE_MASK) >> SIM_SOPT1CFG_USSWE_SHIFT)
+#define SIM_BRD_SOPT1CFG_USSWE(base) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT))
+
+/*! @brief Set the USSWE field to a new value. */
+#define SIM_WR_SOPT1CFG_USSWE(base, value) (SIM_RMW_SOPT1CFG(base, SIM_SOPT1CFG_USSWE_MASK, SIM_SOPT1CFG_USSWE(value)))
+#define SIM_BWR_SOPT1CFG_USSWE(base, value) (BITBAND_ACCESS32(&SIM_SOPT1CFG_REG(base), SIM_SOPT1CFG_USSWE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT2 - System Options Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT2 - System Options Register 2 (RW)
+ *
+ * Reset value: 0x00001000U
+ *
+ * SOPT2 contains the controls for selecting many of the module clock source
+ * options on this device. See the Clock Distribution chapter for more information
+ * including clocking diagrams and definitions of device clocks.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT2 register
+ */
+/*@{*/
+#define SIM_RD_SOPT2(base)       (SIM_SOPT2_REG(base))
+#define SIM_WR_SOPT2(base, value) (SIM_SOPT2_REG(base) = (value))
+#define SIM_RMW_SOPT2(base, mask, value) (SIM_WR_SOPT2(base, (SIM_RD_SOPT2(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) |  (value)))
+#define SIM_CLR_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) & ~(value)))
+#define SIM_TOG_SOPT2(base, value) (SIM_WR_SOPT2(base, SIM_RD_SOPT2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
+ *
+ * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
+ * RTC_CLKOUT pin.
+ *
+ * Values:
+ * - 0b0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
+ * - 0b1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */
+#define SIM_RD_SOPT2_RTCCLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RTCCLKOUTSEL_MASK) >> SIM_SOPT2_RTCCLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_RTCCLKOUTSEL(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT))
+
+/*! @brief Set the RTCCLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_RTCCLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RTCCLKOUTSEL_MASK, SIM_SOPT2_RTCCLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_RTCCLKOUTSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RTCCLKOUTSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
+ *
+ * Selects the clock to output on the CLKOUT pin.
+ *
+ * Values:
+ * - 0b000 - FlexBus CLKOUT
+ * - 0b001 - Reserved
+ * - 0b010 - Flash clock
+ * - 0b011 - LPO clock (1 kHz)
+ * - 0b100 - MCGIRCLK
+ * - 0b101 - RTC 32.768kHz clock
+ * - 0b110 - OSCERCLK0
+ * - 0b111 - IRC 48 MHz clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */
+#define SIM_RD_SOPT2_CLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_CLKOUTSEL_MASK) >> SIM_SOPT2_CLKOUTSEL_SHIFT)
+#define SIM_BRD_SOPT2_CLKOUTSEL(base) (SIM_RD_SOPT2_CLKOUTSEL(base))
+
+/*! @brief Set the CLKOUTSEL field to a new value. */
+#define SIM_WR_SOPT2_CLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_CLKOUTSEL_MASK, SIM_SOPT2_CLKOUTSEL(value)))
+#define SIM_BWR_SOPT2_CLKOUTSEL(base, value) (SIM_WR_SOPT2_CLKOUTSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
+ *
+ * If flash security is enabled, then this field affects what CPU operations can
+ * access off-chip via the FlexBus interface. This field has no effect if flash
+ * security is not enabled.
+ *
+ * Values:
+ * - 0b00 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 0b01 - All off-chip accesses (instruction and data) via the FlexBus are
+ *     disallowed.
+ * - 0b10 - Off-chip instruction accesses are disallowed. Data accesses are
+ *     allowed.
+ * - 0b11 - Off-chip instruction accesses and data accesses are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_FBSL field. */
+#define SIM_RD_SOPT2_FBSL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_FBSL_MASK) >> SIM_SOPT2_FBSL_SHIFT)
+#define SIM_BRD_SOPT2_FBSL(base) (SIM_RD_SOPT2_FBSL(base))
+
+/*! @brief Set the FBSL field to a new value. */
+#define SIM_WR_SOPT2_FBSL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_FBSL_MASK, SIM_SOPT2_FBSL(value)))
+#define SIM_BWR_SOPT2_FBSL(base, value) (SIM_WR_SOPT2_FBSL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
+ *
+ * Controls the output drive strength of the PTD7 pin by selecting either one or
+ * two pads to drive it.
+ *
+ * Values:
+ * - 0b0 - Single-pad drive strength for PTD7.
+ * - 0b1 - Double pad drive strength for PTD7.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_PTD7PAD field. */
+#define SIM_RD_SOPT2_PTD7PAD(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_PTD7PAD_MASK) >> SIM_SOPT2_PTD7PAD_SHIFT)
+#define SIM_BRD_SOPT2_PTD7PAD(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_PTD7PAD_SHIFT))
+
+/*! @brief Set the PTD7PAD field to a new value. */
+#define SIM_WR_SOPT2_PTD7PAD(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_PTD7PAD_MASK, SIM_SOPT2_PTD7PAD(value)))
+#define SIM_BWR_SOPT2_PTD7PAD(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_PTD7PAD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
+ *
+ * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
+ * clock source.
+ *
+ * Values:
+ * - 0b0 - MCGOUTCLK
+ * - 0b1 - Core/system clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */
+#define SIM_RD_SOPT2_TRACECLKSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TRACECLKSEL_MASK) >> SIM_SOPT2_TRACECLKSEL_SHIFT)
+#define SIM_BRD_SOPT2_TRACECLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_TRACECLKSEL_SHIFT))
+
+/*! @brief Set the TRACECLKSEL field to a new value. */
+#define SIM_WR_SOPT2_TRACECLKSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TRACECLKSEL_MASK, SIM_SOPT2_TRACECLKSEL(value)))
+#define SIM_BWR_SOPT2_TRACECLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_TRACECLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
+ *
+ * Selects the high frequency clock for various peripheral clocking options.
+ *
+ * Values:
+ * - 0b00 - MCGFLLCLK clock
+ * - 0b01 - MCGPLLCLK clock
+ * - 0b10 - Reserved
+ * - 0b11 - IRC48 MHz clock
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */
+#define SIM_RD_SOPT2_PLLFLLSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
+#define SIM_BRD_SOPT2_PLLFLLSEL(base) (SIM_RD_SOPT2_PLLFLLSEL(base))
+
+/*! @brief Set the PLLFLLSEL field to a new value. */
+#define SIM_WR_SOPT2_PLLFLLSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_PLLFLLSEL_MASK, SIM_SOPT2_PLLFLLSEL(value)))
+#define SIM_BWR_SOPT2_PLLFLLSEL(base, value) (SIM_WR_SOPT2_PLLFLLSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field USBSRC[18] (RW)
+ *
+ * Selects the clock source for the USB 48 MHz clock.
+ *
+ * Values:
+ * - 0b0 - External bypass clock (USB_CLKIN).
+ * - 0b1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
+ *     SIM_CLKDIV2[USBFRAC, USBDIV].
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_USBSRC field. */
+#define SIM_RD_SOPT2_USBSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_USBSRC_MASK) >> SIM_SOPT2_USBSRC_SHIFT)
+#define SIM_BRD_SOPT2_USBSRC(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT))
+
+/*! @brief Set the USBSRC field to a new value. */
+#define SIM_WR_SOPT2_USBSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_USBSRC_MASK, SIM_SOPT2_USBSRC(value)))
+#define SIM_BWR_SOPT2_USBSRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_USBSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field RMIISRC[19] (RW)
+ *
+ * Selects the clock source for the Ethernet RMII interface
+ *
+ * Values:
+ * - 0b0 - EXTAL clock
+ * - 0b1 - External bypass clock (ENET_1588_CLKIN).
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_RMIISRC field. */
+#define SIM_RD_SOPT2_RMIISRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_RMIISRC_MASK) >> SIM_SOPT2_RMIISRC_SHIFT)
+#define SIM_BRD_SOPT2_RMIISRC(base) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RMIISRC_SHIFT))
+
+/*! @brief Set the RMIISRC field to a new value. */
+#define SIM_WR_SOPT2_RMIISRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_RMIISRC_MASK, SIM_SOPT2_RMIISRC(value)))
+#define SIM_BWR_SOPT2_RMIISRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT2_REG(base), SIM_SOPT2_RMIISRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
+ *
+ * Selects the clock source for the Ethernet timestamp clock.
+ *
+ * Values:
+ * - 0b00 - Core/system clock.
+ * - 0b01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 0b10 - OSCERCLK clock
+ * - 0b11 - External bypass clock (ENET_1588_CLKIN).
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_TIMESRC field. */
+#define SIM_RD_SOPT2_TIMESRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TIMESRC_MASK) >> SIM_SOPT2_TIMESRC_SHIFT)
+#define SIM_BRD_SOPT2_TIMESRC(base) (SIM_RD_SOPT2_TIMESRC(base))
+
+/*! @brief Set the TIMESRC field to a new value. */
+#define SIM_WR_SOPT2_TIMESRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TIMESRC_MASK, SIM_SOPT2_TIMESRC(value)))
+#define SIM_BWR_SOPT2_TIMESRC(base, value) (SIM_WR_SOPT2_TIMESRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
+ *
+ * Selects the clock source for the SDHC clock .
+ *
+ * Values:
+ * - 0b00 - Core/system clock.
+ * - 0b01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
+ *     SOPT2[PLLFLLSEL].
+ * - 0b10 - OSCERCLK clock
+ * - 0b11 - External bypass clock (SDHC0_CLKIN)
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT2_SDHCSRC field. */
+#define SIM_RD_SOPT2_SDHCSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_SDHCSRC_MASK) >> SIM_SOPT2_SDHCSRC_SHIFT)
+#define SIM_BRD_SOPT2_SDHCSRC(base) (SIM_RD_SOPT2_SDHCSRC(base))
+
+/*! @brief Set the SDHCSRC field to a new value. */
+#define SIM_WR_SOPT2_SDHCSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_SDHCSRC_MASK, SIM_SOPT2_SDHCSRC(value)))
+#define SIM_BWR_SOPT2_SDHCSRC(base, value) (SIM_WR_SOPT2_SDHCSRC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT4 - System Options Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT4 - System Options Register 4 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT4 register
+ */
+/*@{*/
+#define SIM_RD_SOPT4(base)       (SIM_SOPT4_REG(base))
+#define SIM_WR_SOPT4(base, value) (SIM_SOPT4_REG(base) = (value))
+#define SIM_RMW_SOPT4(base, mask, value) (SIM_WR_SOPT4(base, (SIM_RD_SOPT4(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) |  (value)))
+#define SIM_CLR_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) & ~(value)))
+#define SIM_TOG_SOPT4(base, value) (SIM_WR_SOPT4(base, SIM_RD_SOPT4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
+ *
+ * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */
+#define SIM_RD_SOPT4_FTM0FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT0_MASK) >> SIM_SOPT4_FTM0FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT0_SHIFT))
+
+/*! @brief Set the FTM0FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT0_MASK, SIM_SOPT4_FTM0FLT0(value)))
+#define SIM_BWR_SOPT4_FTM0FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
+ *
+ * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT1 pin
+ * - 0b1 - CMP1 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */
+#define SIM_RD_SOPT4_FTM0FLT1(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT1_MASK) >> SIM_SOPT4_FTM0FLT1_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT1(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT1_SHIFT))
+
+/*! @brief Set the FTM0FLT1 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT1(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT1_MASK, SIM_SOPT4_FTM0FLT1(value)))
+#define SIM_BWR_SOPT4_FTM0FLT1(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
+ *
+ * Selects the source of FTM0 fault 2. The pin source for fault 2 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM0_FLT2 pin
+ * - 0b1 - CMP2 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. */
+#define SIM_RD_SOPT4_FTM0FLT2(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0FLT2_MASK) >> SIM_SOPT4_FTM0FLT2_SHIFT)
+#define SIM_BRD_SOPT4_FTM0FLT2(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT2_SHIFT))
+
+/*! @brief Set the FTM0FLT2 field to a new value. */
+#define SIM_WR_SOPT4_FTM0FLT2(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0FLT2_MASK, SIM_SOPT4_FTM0FLT2(value)))
+#define SIM_BWR_SOPT4_FTM0FLT2(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0FLT2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
+ *
+ * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate pin control
+ * register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM1_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */
+#define SIM_RD_SOPT4_FTM1FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1FLT0_MASK) >> SIM_SOPT4_FTM1FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM1FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1FLT0_SHIFT))
+
+/*! @brief Set the FTM1FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM1FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1FLT0_MASK, SIM_SOPT4_FTM1FLT0(value)))
+#define SIM_BWR_SOPT4_FTM1FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
+ *
+ * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0b0 - FTM2_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */
+#define SIM_RD_SOPT4_FTM2FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2FLT0_MASK) >> SIM_SOPT4_FTM2FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM2FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2FLT0_SHIFT))
+
+/*! @brief Set the FTM2FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM2FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2FLT0_MASK, SIM_SOPT4_FTM2FLT0(value)))
+#define SIM_BWR_SOPT4_FTM2FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
+ *
+ * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
+ * configured for the FTM module fault function through the appropriate PORTx pin
+ * control register.
+ *
+ * Values:
+ * - 0b0 - FTM3_FLT0 pin
+ * - 0b1 - CMP0 out
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */
+#define SIM_RD_SOPT4_FTM3FLT0(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3FLT0_MASK) >> SIM_SOPT4_FTM3FLT0_SHIFT)
+#define SIM_BRD_SOPT4_FTM3FLT0(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3FLT0_SHIFT))
+
+/*! @brief Set the FTM3FLT0 field to a new value. */
+#define SIM_WR_SOPT4_FTM3FLT0(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3FLT0_MASK, SIM_SOPT4_FTM3FLT0(value)))
+#define SIM_BWR_SOPT4_FTM3FLT0(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3FLT0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
+ *
+ * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0b00 - FTM1_CH0 signal
+ * - 0b01 - CMP0 output
+ * - 0b10 - CMP1 output
+ * - 0b11 - USB start of frame pulse
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */
+#define SIM_RD_SOPT4_FTM1CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1CH0SRC_MASK) >> SIM_SOPT4_FTM1CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM1CH0SRC(base) (SIM_RD_SOPT4_FTM1CH0SRC(base))
+
+/*! @brief Set the FTM1CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM1CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1CH0SRC_MASK, SIM_SOPT4_FTM1CH0SRC(value)))
+#define SIM_BWR_SOPT4_FTM1CH0SRC(base, value) (SIM_WR_SOPT4_FTM1CH0SRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
+ *
+ * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
+ * input capture mode, clear this field.
+ *
+ * Values:
+ * - 0b00 - FTM2_CH0 signal
+ * - 0b01 - CMP0 output
+ * - 0b10 - CMP1 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */
+#define SIM_RD_SOPT4_FTM2CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2CH0SRC_MASK) >> SIM_SOPT4_FTM2CH0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM2CH0SRC(base) (SIM_RD_SOPT4_FTM2CH0SRC(base))
+
+/*! @brief Set the FTM2CH0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM2CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2CH0SRC_MASK, SIM_SOPT4_FTM2CH0SRC(value)))
+#define SIM_BWR_SOPT4_FTM2CH0SRC(base, value) (SIM_WR_SOPT4_FTM2CH0SRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM0 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM_CLK0 pin
+ * - 0b1 - FTM_CLK1 pin
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */
+#define SIM_RD_SOPT4_FTM0CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0CLKSEL_MASK) >> SIM_SOPT4_FTM0CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM0CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0CLKSEL_SHIFT))
+
+/*! @brief Set the FTM0CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM0CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0CLKSEL_MASK, SIM_SOPT4_FTM0CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM0CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM1 module. The
+ * selected pin must also be configured for the FTM external clock function through
+ * the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM_CLK0 pin
+ * - 0b1 - FTM_CLK1 pin
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */
+#define SIM_RD_SOPT4_FTM1CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM1CLKSEL_MASK) >> SIM_SOPT4_FTM1CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM1CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1CLKSEL_SHIFT))
+
+/*! @brief Set the FTM1CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM1CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM1CLKSEL_MASK, SIM_SOPT4_FTM1CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM1CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM1CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM2 module. The
+ * selected pin must also be configured for the FTM2 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM2 external clock driven by FTM_CLK0 pin.
+ * - 0b1 - FTM2 external clock driven by FTM_CLK1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */
+#define SIM_RD_SOPT4_FTM2CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM2CLKSEL_MASK) >> SIM_SOPT4_FTM2CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM2CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2CLKSEL_SHIFT))
+
+/*! @brief Set the FTM2CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM2CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM2CLKSEL_MASK, SIM_SOPT4_FTM2CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM2CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM2CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
+ *
+ * Selects the external pin used to drive the clock to the FTM3 module. The
+ * selected pin must also be configured for the FTM3 module external clock function
+ * through the appropriate pin control register in the port control module.
+ *
+ * Values:
+ * - 0b0 - FTM3 external clock driven by FTM_CLK0 pin.
+ * - 0b1 - FTM3 external clock driven by FTM_CLK1 pin.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */
+#define SIM_RD_SOPT4_FTM3CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3CLKSEL_MASK) >> SIM_SOPT4_FTM3CLKSEL_SHIFT)
+#define SIM_BRD_SOPT4_FTM3CLKSEL(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3CLKSEL_SHIFT))
+
+/*! @brief Set the FTM3CLKSEL field to a new value. */
+#define SIM_WR_SOPT4_FTM3CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3CLKSEL_MASK, SIM_SOPT4_FTM3CLKSEL(value)))
+#define SIM_BWR_SOPT4_FTM3CLKSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3CLKSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 0.
+ *
+ * Values:
+ * - 0b0 - HSCMP0 output drives FTM0 hardware trigger 0
+ * - 0b1 - FTM1 channel match drives FTM0 hardware trigger 0
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */
+#define SIM_RD_SOPT4_FTM0TRG0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0TRG0SRC_MASK) >> SIM_SOPT4_FTM0TRG0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM0TRG0SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG0SRC_SHIFT))
+
+/*! @brief Set the FTM0TRG0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM0TRG0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0TRG0SRC_MASK, SIM_SOPT4_FTM0TRG0SRC(value)))
+#define SIM_BWR_SOPT4_FTM0TRG0SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG0SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
+ *
+ * Selects the source of FTM0 hardware trigger 1.
+ *
+ * Values:
+ * - 0b0 - PDB output trigger 1 drives FTM0 hardware trigger 1
+ * - 0b1 - FTM2 channel match drives FTM0 hardware trigger 1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */
+#define SIM_RD_SOPT4_FTM0TRG1SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM0TRG1SRC_MASK) >> SIM_SOPT4_FTM0TRG1SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM0TRG1SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG1SRC_SHIFT))
+
+/*! @brief Set the FTM0TRG1SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM0TRG1SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM0TRG1SRC_MASK, SIM_SOPT4_FTM0TRG1SRC(value)))
+#define SIM_BWR_SOPT4_FTM0TRG1SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM0TRG1SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 0.
+ *
+ * Values:
+ * - 0b0 - Reserved
+ * - 0b1 - FTM1 channel match drives FTM3 hardware trigger 0
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */
+#define SIM_RD_SOPT4_FTM3TRG0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3TRG0SRC_MASK) >> SIM_SOPT4_FTM3TRG0SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM3TRG0SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG0SRC_SHIFT))
+
+/*! @brief Set the FTM3TRG0SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM3TRG0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3TRG0SRC_MASK, SIM_SOPT4_FTM3TRG0SRC(value)))
+#define SIM_BWR_SOPT4_FTM3TRG0SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG0SRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
+ *
+ * Selects the source of FTM3 hardware trigger 1.
+ *
+ * Values:
+ * - 0b0 - Reserved
+ * - 0b1 - FTM2 channel match drives FTM3 hardware trigger 1
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */
+#define SIM_RD_SOPT4_FTM3TRG1SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_FTM3TRG1SRC_MASK) >> SIM_SOPT4_FTM3TRG1SRC_SHIFT)
+#define SIM_BRD_SOPT4_FTM3TRG1SRC(base) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG1SRC_SHIFT))
+
+/*! @brief Set the FTM3TRG1SRC field to a new value. */
+#define SIM_WR_SOPT4_FTM3TRG1SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_FTM3TRG1SRC_MASK, SIM_SOPT4_FTM3TRG1SRC(value)))
+#define SIM_BWR_SOPT4_FTM3TRG1SRC(base, value) (BITBAND_ACCESS32(&SIM_SOPT4_REG(base), SIM_SOPT4_FTM3TRG1SRC_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT5 - System Options Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT5 - System Options Register 5 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT5 register
+ */
+/*@{*/
+#define SIM_RD_SOPT5(base)       (SIM_SOPT5_REG(base))
+#define SIM_WR_SOPT5(base, value) (SIM_SOPT5_REG(base) = (value))
+#define SIM_RMW_SOPT5(base, mask, value) (SIM_WR_SOPT5(base, (SIM_RD_SOPT5(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) |  (value)))
+#define SIM_CLR_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) & ~(value)))
+#define SIM_TOG_SOPT5(base, value) (SIM_WR_SOPT5(base, SIM_RD_SOPT5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
+ *
+ * Selects the source for the UART 0 transmit data.
+ *
+ * Values:
+ * - 0b00 - UART0_TX pin
+ * - 0b01 - UART0_TX pin modulated with FTM1 channel 0 output
+ * - 0b10 - UART0_TX pin modulated with FTM2 channel 0 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */
+#define SIM_RD_SOPT5_UART0TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART0TXSRC_MASK) >> SIM_SOPT5_UART0TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART0TXSRC(base) (SIM_RD_SOPT5_UART0TXSRC(base))
+
+/*! @brief Set the UART0TXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART0TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART0TXSRC_MASK, SIM_SOPT5_UART0TXSRC(value)))
+#define SIM_BWR_SOPT5_UART0TXSRC(base, value) (SIM_WR_SOPT5_UART0TXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
+ *
+ * Selects the source for the UART 0 receive data.
+ *
+ * Values:
+ * - 0b00 - UART0_RX pin
+ * - 0b01 - CMP0
+ * - 0b10 - CMP1
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */
+#define SIM_RD_SOPT5_UART0RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART0RXSRC_MASK) >> SIM_SOPT5_UART0RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART0RXSRC(base) (SIM_RD_SOPT5_UART0RXSRC(base))
+
+/*! @brief Set the UART0RXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART0RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART0RXSRC_MASK, SIM_SOPT5_UART0RXSRC(value)))
+#define SIM_BWR_SOPT5_UART0RXSRC(base, value) (SIM_WR_SOPT5_UART0RXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
+ *
+ * Selects the source for the UART 1 transmit data.
+ *
+ * Values:
+ * - 0b00 - UART1_TX pin
+ * - 0b01 - UART1_TX pin modulated with FTM1 channel 0 output
+ * - 0b10 - UART1_TX pin modulated with FTM2 channel 0 output
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */
+#define SIM_RD_SOPT5_UART1TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART1TXSRC_MASK) >> SIM_SOPT5_UART1TXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART1TXSRC(base) (SIM_RD_SOPT5_UART1TXSRC(base))
+
+/*! @brief Set the UART1TXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART1TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART1TXSRC_MASK, SIM_SOPT5_UART1TXSRC(value)))
+#define SIM_BWR_SOPT5_UART1TXSRC(base, value) (SIM_WR_SOPT5_UART1TXSRC(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
+ *
+ * Selects the source for the UART 1 receive data.
+ *
+ * Values:
+ * - 0b00 - UART1_RX pin
+ * - 0b01 - CMP0
+ * - 0b10 - CMP1
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */
+#define SIM_RD_SOPT5_UART1RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_UART1RXSRC_MASK) >> SIM_SOPT5_UART1RXSRC_SHIFT)
+#define SIM_BRD_SOPT5_UART1RXSRC(base) (SIM_RD_SOPT5_UART1RXSRC(base))
+
+/*! @brief Set the UART1RXSRC field to a new value. */
+#define SIM_WR_SOPT5_UART1RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_UART1RXSRC_MASK, SIM_SOPT5_UART1RXSRC(value)))
+#define SIM_BWR_SOPT5_UART1RXSRC(base, value) (SIM_WR_SOPT5_UART1RXSRC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SOPT7 - System Options Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SOPT7 - System Options Register 7 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SOPT7 register
+ */
+/*@{*/
+#define SIM_RD_SOPT7(base)       (SIM_SOPT7_REG(base))
+#define SIM_WR_SOPT7(base, value) (SIM_SOPT7_REG(base) = (value))
+#define SIM_RMW_SOPT7(base, mask, value) (SIM_WR_SOPT7(base, (SIM_RD_SOPT7(base) & ~(mask)) | (value)))
+#define SIM_SET_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) |  (value)))
+#define SIM_CLR_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) & ~(value)))
+#define SIM_TOG_SOPT7(base, value) (SIM_WR_SOPT7(base, SIM_RD_SOPT7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SOPT7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
+ *
+ * Selects the ADC0 trigger source when alternative triggers are functional in
+ * stop and VLPS modes. .
+ *
+ * Values:
+ * - 0b0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0b0001 - High speed comparator 0 output
+ * - 0b0010 - High speed comparator 1 output
+ * - 0b0011 - High speed comparator 2 output
+ * - 0b0100 - PIT trigger 0
+ * - 0b0101 - PIT trigger 1
+ * - 0b0110 - PIT trigger 2
+ * - 0b0111 - PIT trigger 3
+ * - 0b1000 - FTM0 trigger
+ * - 0b1001 - FTM1 trigger
+ * - 0b1010 - FTM2 trigger
+ * - 0b1011 - FTM3 trigger
+ * - 0b1100 - RTC alarm
+ * - 0b1101 - RTC seconds
+ * - 0b1110 - Low-power timer (LPTMR) trigger
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */
+#define SIM_RD_SOPT7_ADC0TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0TRGSEL_MASK) >> SIM_SOPT7_ADC0TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0TRGSEL(base) (SIM_RD_SOPT7_ADC0TRGSEL(base))
+
+/*! @brief Set the ADC0TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0TRGSEL_MASK, SIM_SOPT7_ADC0TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0TRGSEL(base, value) (SIM_WR_SOPT7_ADC0TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
+ *
+ * Selects the ADC0 pre-trigger source when alternative triggers are enabled
+ * through ADC0ALTTRGEN.
+ *
+ * Values:
+ * - 0b0 - Pre-trigger A
+ * - 0b1 - Pre-trigger B
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC0PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0PRETRGSEL_MASK) >> SIM_SOPT7_ADC0PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC0PRETRGSEL(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT))
+
+/*! @brief Set the ADC0PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC0PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0PRETRGSEL_MASK, SIM_SOPT7_ADC0PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC0PRETRGSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
+ *
+ * Enable alternative conversion triggers for ADC0.
+ *
+ * Values:
+ * - 0b0 - PDB trigger selected for ADC0.
+ * - 0b1 - Alternate trigger selected for ADC0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC0ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0ALTTRGEN_MASK) >> SIM_SOPT7_ADC0ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC0ALTTRGEN(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT))
+
+/*! @brief Set the ADC0ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC0ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0ALTTRGEN_MASK, SIM_SOPT7_ADC0ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC0ALTTRGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
+ *
+ * Selects the ADC1 trigger source when alternative triggers are functional in
+ * stop and VLPS modes.
+ *
+ * Values:
+ * - 0b0000 - PDB external trigger pin input (PDB0_EXTRG)
+ * - 0b0001 - High speed comparator 0 output
+ * - 0b0010 - High speed comparator 1 output
+ * - 0b0011 - High speed comparator 2 output
+ * - 0b0100 - PIT trigger 0
+ * - 0b0101 - PIT trigger 1
+ * - 0b0110 - PIT trigger 2
+ * - 0b0111 - PIT trigger 3
+ * - 0b1000 - FTM0 trigger
+ * - 0b1001 - FTM1 trigger
+ * - 0b1010 - FTM2 trigger
+ * - 0b1011 - FTM3 trigger
+ * - 0b1100 - RTC alarm
+ * - 0b1101 - RTC seconds
+ * - 0b1110 - Low-power timer (LPTMR) trigger
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */
+#define SIM_RD_SOPT7_ADC1TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1TRGSEL_MASK) >> SIM_SOPT7_ADC1TRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC1TRGSEL(base) (SIM_RD_SOPT7_ADC1TRGSEL(base))
+
+/*! @brief Set the ADC1TRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC1TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1TRGSEL_MASK, SIM_SOPT7_ADC1TRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC1TRGSEL(base, value) (SIM_WR_SOPT7_ADC1TRGSEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
+ *
+ * Selects the ADC1 pre-trigger source when alternative triggers are enabled
+ * through ADC1ALTTRGEN.
+ *
+ * Values:
+ * - 0b0 - Pre-trigger A selected for ADC1.
+ * - 0b1 - Pre-trigger B selected for ADC1.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */
+#define SIM_RD_SOPT7_ADC1PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1PRETRGSEL_MASK) >> SIM_SOPT7_ADC1PRETRGSEL_SHIFT)
+#define SIM_BRD_SOPT7_ADC1PRETRGSEL(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1PRETRGSEL_SHIFT))
+
+/*! @brief Set the ADC1PRETRGSEL field to a new value. */
+#define SIM_WR_SOPT7_ADC1PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1PRETRGSEL_MASK, SIM_SOPT7_ADC1PRETRGSEL(value)))
+#define SIM_BWR_SOPT7_ADC1PRETRGSEL(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1PRETRGSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
+ *
+ * Enable alternative conversion triggers for ADC1.
+ *
+ * Values:
+ * - 0b0 - PDB trigger selected for ADC1
+ * - 0b1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */
+#define SIM_RD_SOPT7_ADC1ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC1ALTTRGEN_MASK) >> SIM_SOPT7_ADC1ALTTRGEN_SHIFT)
+#define SIM_BRD_SOPT7_ADC1ALTTRGEN(base) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1ALTTRGEN_SHIFT))
+
+/*! @brief Set the ADC1ALTTRGEN field to a new value. */
+#define SIM_WR_SOPT7_ADC1ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC1ALTTRGEN_MASK, SIM_SOPT7_ADC1ALTTRGEN(value)))
+#define SIM_BWR_SOPT7_ADC1ALTTRGEN(base, value) (BITBAND_ACCESS32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC1ALTTRGEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SDID - System Device Identification Register
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SDID - System Device Identification Register (RO)
+ *
+ * Reset value: 0x00000380U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SDID register
+ */
+/*@{*/
+#define SIM_RD_SDID(base)        (SIM_SDID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SDID bitfields
+ */
+
+/*!
+ * @name Register SIM_SDID, field PINID[3:0] (RO)
+ *
+ * Specifies the pincount of the device.
+ *
+ * Values:
+ * - 0b0000 - Reserved
+ * - 0b0001 - Reserved
+ * - 0b0010 - 32-pin
+ * - 0b0011 - Reserved
+ * - 0b0100 - 48-pin
+ * - 0b0101 - 64-pin
+ * - 0b0110 - 80-pin
+ * - 0b0111 - 81-pin or 121-pin
+ * - 0b1000 - 100-pin
+ * - 0b1001 - 121-pin
+ * - 0b1010 - 144-pin
+ * - 0b1011 - Custom pinout (WLCSP)
+ * - 0b1100 - 169-pin
+ * - 0b1101 - Reserved
+ * - 0b1110 - 256-pin
+ * - 0b1111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_PINID field. */
+#define SIM_RD_SDID_PINID(base) ((SIM_SDID_REG(base) & SIM_SDID_PINID_MASK) >> SIM_SDID_PINID_SHIFT)
+#define SIM_BRD_SDID_PINID(base) (SIM_RD_SDID_PINID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMID[6:4] (RO)
+ *
+ * This field is maintained for compatibility only, but has been superceded by
+ * the SERIESID, FAMILYID and SUBFAMID fields in this register.
+ *
+ * Values:
+ * - 0b000 - K1x Family (without tamper)
+ * - 0b001 - K2x Family (without tamper)
+ * - 0b010 - K3x Family or K1x/K6x Family (with tamper)
+ * - 0b011 - K4x Family or K2x Family (with tamper)
+ * - 0b100 - K6x Family (without tamper)
+ * - 0b101 - K7x Family
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMID field. */
+#define SIM_RD_SDID_FAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMID_MASK) >> SIM_SDID_FAMID_SHIFT)
+#define SIM_BRD_SDID_FAMID(base) (SIM_RD_SDID_FAMID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field DIEID[11:7] (RO)
+ *
+ * Specifies the silicon feature set identication number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_DIEID field. */
+#define SIM_RD_SDID_DIEID(base) ((SIM_SDID_REG(base) & SIM_SDID_DIEID_MASK) >> SIM_SDID_DIEID_SHIFT)
+#define SIM_BRD_SDID_DIEID(base) (SIM_RD_SDID_DIEID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field REVID[15:12] (RO)
+ *
+ * Specifies the silicon implementation number for the device.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_REVID field. */
+#define SIM_RD_SDID_REVID(base) ((SIM_SDID_REG(base) & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT)
+#define SIM_BRD_SDID_REVID(base) (SIM_RD_SDID_REVID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SERIESID[23:20] (RO)
+ *
+ * Specifies the Kinetis series of the device.
+ *
+ * Values:
+ * - 0b0000 - Kinetis K series
+ * - 0b0001 - Kinetis L series
+ * - 0b0101 - Kinetis W series
+ * - 0b0110 - Kinetis V series
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SERIESID field. */
+#define SIM_RD_SDID_SERIESID(base) ((SIM_SDID_REG(base) & SIM_SDID_SERIESID_MASK) >> SIM_SDID_SERIESID_SHIFT)
+#define SIM_BRD_SDID_SERIESID(base) (SIM_RD_SDID_SERIESID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
+ *
+ * Specifies the Kinetis sub-family of the device.
+ *
+ * Values:
+ * - 0b0000 - Kx0 Subfamily
+ * - 0b0001 - Kx1 Subfamily (tamper detect)
+ * - 0b0010 - Kx2 Subfamily
+ * - 0b0011 - Kx3 Subfamily (tamper detect)
+ * - 0b0100 - Kx4 Subfamily
+ * - 0b0101 - Kx5 Subfamily (tamper detect)
+ * - 0b0110 - Kx6 Subfamily
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_SUBFAMID field. */
+#define SIM_RD_SDID_SUBFAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_SUBFAMID_MASK) >> SIM_SDID_SUBFAMID_SHIFT)
+#define SIM_BRD_SDID_SUBFAMID(base) (SIM_RD_SDID_SUBFAMID(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
+ *
+ * Specifies the Kinetis family of the device.
+ *
+ * Values:
+ * - 0b0001 - K1x Family
+ * - 0b0010 - K2x Family
+ * - 0b0011 - K3x Family
+ * - 0b0100 - K4x Family
+ * - 0b0110 - K6x Family
+ * - 0b0111 - K7x Family
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SDID_FAMILYID field. */
+#define SIM_RD_SDID_FAMILYID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMILYID_MASK) >> SIM_SDID_FAMILYID_SHIFT)
+#define SIM_BRD_SDID_FAMILYID(base) (SIM_RD_SDID_FAMILYID(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC1 - System Clock Gating Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC1 register
+ */
+/*@{*/
+#define SIM_RD_SCGC1(base)       (SIM_SCGC1_REG(base))
+#define SIM_WR_SCGC1(base, value) (SIM_SCGC1_REG(base) = (value))
+#define SIM_RMW_SCGC1(base, mask, value) (SIM_WR_SCGC1(base, (SIM_RD_SCGC1(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) |  (value)))
+#define SIM_CLR_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) & ~(value)))
+#define SIM_TOG_SCGC1(base, value) (SIM_WR_SCGC1(base, SIM_RD_SCGC1(base) ^  (value)))
+/*@}*/
+
+/* Unified clock gate bit access macros */
+#define SIM_SCGC_BIT_REG(base, index)        (*((volatile uint32_t *)&SIM_SCGC1_REG(base) + (((uint32_t)(index) >> 5) - 0U)))
+#define SIM_SCGC_BIT_SHIFT(index)            ((uint32_t)(index) & ((1U << 5) - 1U))
+#define SIM_RD_SCGC_BIT(base, index)         (SIM_SCGC_BIT_REG((base), (index)) & (1U << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BRD_SCGC_BIT(base, index)        (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_WR_SCGC_BIT(base, index, value)  (SIM_SCGC_BIT_REG((base), (index)) = (SIM_SCGC_BIT_REG((base), (index)) & ~(1U << SIM_SCGC_BIT_SHIFT(index))) | ((uint32_t)(value) << SIM_SCGC_BIT_SHIFT(index)))
+#define SIM_BWR_SCGC_BIT(base, index, value) (BITBAND_ACCESS32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index)) = (uint32_t)(value))
+
+/*
+ * Constants & macros for individual SIM_SCGC1 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC1, field I2C2[6] (RW)
+ *
+ * This bit controls the clock gate to the I2C2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_I2C2 field. */
+#define SIM_RD_SCGC1_I2C2(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_I2C2_MASK) >> SIM_SCGC1_I2C2_SHIFT)
+#define SIM_BRD_SCGC1_I2C2(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_I2C2_SHIFT))
+
+/*! @brief Set the I2C2 field to a new value. */
+#define SIM_WR_SCGC1_I2C2(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_I2C2_MASK, SIM_SCGC1_I2C2(value)))
+#define SIM_BWR_SCGC1_I2C2(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_I2C2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC1, field UART4[10] (RW)
+ *
+ * This bit controls the clock gate to the UART4 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_UART4 field. */
+#define SIM_RD_SCGC1_UART4(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_UART4_MASK) >> SIM_SCGC1_UART4_SHIFT)
+#define SIM_BRD_SCGC1_UART4(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART4_SHIFT))
+
+/*! @brief Set the UART4 field to a new value. */
+#define SIM_WR_SCGC1_UART4(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_UART4_MASK, SIM_SCGC1_UART4(value)))
+#define SIM_BWR_SCGC1_UART4(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART4_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC1, field UART5[11] (RW)
+ *
+ * This bit controls the clock gate to the UART5 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC1_UART5 field. */
+#define SIM_RD_SCGC1_UART5(base) ((SIM_SCGC1_REG(base) & SIM_SCGC1_UART5_MASK) >> SIM_SCGC1_UART5_SHIFT)
+#define SIM_BRD_SCGC1_UART5(base) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART5_SHIFT))
+
+/*! @brief Set the UART5 field to a new value. */
+#define SIM_WR_SCGC1_UART5(base, value) (SIM_RMW_SCGC1(base, SIM_SCGC1_UART5_MASK, SIM_SCGC1_UART5(value)))
+#define SIM_BWR_SCGC1_UART5(base, value) (BITBAND_ACCESS32(&SIM_SCGC1_REG(base), SIM_SCGC1_UART5_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC2 - System Clock Gating Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
+ * AIPS1, define the clock gate control bits in the SCGC2. When accessing through
+ * AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC2 register
+ */
+/*@{*/
+#define SIM_RD_SCGC2(base)       (SIM_SCGC2_REG(base))
+#define SIM_WR_SCGC2(base, value) (SIM_SCGC2_REG(base) = (value))
+#define SIM_RMW_SCGC2(base, mask, value) (SIM_WR_SCGC2(base, (SIM_RD_SCGC2(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) |  (value)))
+#define SIM_CLR_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) & ~(value)))
+#define SIM_TOG_SCGC2(base, value) (SIM_WR_SCGC2(base, SIM_RD_SCGC2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC2 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC2, field ENET[0] (RW)
+ *
+ * This bit controls the clock gate to the ENET module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_ENET field. */
+#define SIM_RD_SCGC2_ENET(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_ENET_MASK) >> SIM_SCGC2_ENET_SHIFT)
+#define SIM_BRD_SCGC2_ENET(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_ENET_SHIFT))
+
+/*! @brief Set the ENET field to a new value. */
+#define SIM_WR_SCGC2_ENET(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_ENET_MASK, SIM_SCGC2_ENET(value)))
+#define SIM_BWR_SCGC2_ENET(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_ENET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC2, field DAC0[12] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_DAC0 field. */
+#define SIM_RD_SCGC2_DAC0(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_DAC0_MASK) >> SIM_SCGC2_DAC0_SHIFT)
+#define SIM_BRD_SCGC2_DAC0(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC0_SHIFT))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC2_DAC0(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_DAC0_MASK, SIM_SCGC2_DAC0(value)))
+#define SIM_BWR_SCGC2_DAC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC2, field DAC1[13] (RW)
+ *
+ * This bit controls the clock gate to the DAC1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC2_DAC1 field. */
+#define SIM_RD_SCGC2_DAC1(base) ((SIM_SCGC2_REG(base) & SIM_SCGC2_DAC1_MASK) >> SIM_SCGC2_DAC1_SHIFT)
+#define SIM_BRD_SCGC2_DAC1(base) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC1_SHIFT))
+
+/*! @brief Set the DAC1 field to a new value. */
+#define SIM_WR_SCGC2_DAC1(base, value) (SIM_RMW_SCGC2(base, SIM_SCGC2_DAC1_MASK, SIM_SCGC2_DAC1(value)))
+#define SIM_BWR_SCGC2_DAC1(base, value) (BITBAND_ACCESS32(&SIM_SCGC2_REG(base), SIM_SCGC2_DAC1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC3 - System Clock Gating Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
+ * through AIPS1, define the clock gate control bits in the SCGC3. When accessing
+ * through AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC3 register
+ */
+/*@{*/
+#define SIM_RD_SCGC3(base)       (SIM_SCGC3_REG(base))
+#define SIM_WR_SCGC3(base, value) (SIM_SCGC3_REG(base) = (value))
+#define SIM_RMW_SCGC3(base, mask, value) (SIM_WR_SCGC3(base, (SIM_RD_SCGC3(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) |  (value)))
+#define SIM_CLR_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) & ~(value)))
+#define SIM_TOG_SCGC3(base, value) (SIM_WR_SCGC3(base, SIM_RD_SCGC3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC3 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC3, field RNGA[0] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_RNGA field. */
+#define SIM_RD_SCGC3_RNGA(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_RNGA_MASK) >> SIM_SCGC3_RNGA_SHIFT)
+#define SIM_BRD_SCGC3_RNGA(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_RNGA_SHIFT))
+
+/*! @brief Set the RNGA field to a new value. */
+#define SIM_WR_SCGC3_RNGA(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_RNGA_MASK, SIM_SCGC3_RNGA(value)))
+#define SIM_BWR_SCGC3_RNGA(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_RNGA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field SPI2[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_SPI2 field. */
+#define SIM_RD_SCGC3_SPI2(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_SPI2_MASK) >> SIM_SCGC3_SPI2_SHIFT)
+#define SIM_BRD_SCGC3_SPI2(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SPI2_SHIFT))
+
+/*! @brief Set the SPI2 field to a new value. */
+#define SIM_WR_SCGC3_SPI2(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_SPI2_MASK, SIM_SCGC3_SPI2(value)))
+#define SIM_BWR_SCGC3_SPI2(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SPI2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field SDHC[17] (RW)
+ *
+ * This bit controls the clock gate to the SDHC module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_SDHC field. */
+#define SIM_RD_SCGC3_SDHC(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_SDHC_MASK) >> SIM_SCGC3_SDHC_SHIFT)
+#define SIM_BRD_SCGC3_SDHC(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SDHC_SHIFT))
+
+/*! @brief Set the SDHC field to a new value. */
+#define SIM_WR_SCGC3_SDHC(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_SDHC_MASK, SIM_SCGC3_SDHC(value)))
+#define SIM_BWR_SCGC3_SDHC(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_SDHC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field FTM2[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_FTM2 field. */
+#define SIM_RD_SCGC3_FTM2(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_FTM2_MASK) >> SIM_SCGC3_FTM2_SHIFT)
+#define SIM_BRD_SCGC3_FTM2(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM2_SHIFT))
+
+/*! @brief Set the FTM2 field to a new value. */
+#define SIM_WR_SCGC3_FTM2(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_FTM2_MASK, SIM_SCGC3_FTM2(value)))
+#define SIM_BWR_SCGC3_FTM2(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field FTM3[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM3 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_FTM3 field. */
+#define SIM_RD_SCGC3_FTM3(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_FTM3_MASK) >> SIM_SCGC3_FTM3_SHIFT)
+#define SIM_BRD_SCGC3_FTM3(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM3_SHIFT))
+
+/*! @brief Set the FTM3 field to a new value. */
+#define SIM_WR_SCGC3_FTM3(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_FTM3_MASK, SIM_SCGC3_FTM3(value)))
+#define SIM_BWR_SCGC3_FTM3(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_FTM3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC3, field ADC1[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC3_ADC1 field. */
+#define SIM_RD_SCGC3_ADC1(base) ((SIM_SCGC3_REG(base) & SIM_SCGC3_ADC1_MASK) >> SIM_SCGC3_ADC1_SHIFT)
+#define SIM_BRD_SCGC3_ADC1(base) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_ADC1_SHIFT))
+
+/*! @brief Set the ADC1 field to a new value. */
+#define SIM_WR_SCGC3_ADC1(base, value) (SIM_RMW_SCGC3(base, SIM_SCGC3_ADC1_MASK, SIM_SCGC3_ADC1(value)))
+#define SIM_BWR_SCGC3_ADC1(base, value) (BITBAND_ACCESS32(&SIM_SCGC3_REG(base), SIM_SCGC3_ADC1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC4 - System Clock Gating Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
+ *
+ * Reset value: 0xF0100030U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC4 register
+ */
+/*@{*/
+#define SIM_RD_SCGC4(base)       (SIM_SCGC4_REG(base))
+#define SIM_WR_SCGC4(base, value) (SIM_SCGC4_REG(base) = (value))
+#define SIM_RMW_SCGC4(base, mask, value) (SIM_WR_SCGC4(base, (SIM_RD_SCGC4(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) |  (value)))
+#define SIM_CLR_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) & ~(value)))
+#define SIM_TOG_SCGC4(base, value) (SIM_WR_SCGC4(base, SIM_RD_SCGC4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC4 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC4, field EWM[1] (RW)
+ *
+ * This bit controls the clock gate to the EWM module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_EWM field. */
+#define SIM_RD_SCGC4_EWM(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_EWM_MASK) >> SIM_SCGC4_EWM_SHIFT)
+#define SIM_BRD_SCGC4_EWM(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_EWM_SHIFT))
+
+/*! @brief Set the EWM field to a new value. */
+#define SIM_WR_SCGC4_EWM(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_EWM_MASK, SIM_SCGC4_EWM(value)))
+#define SIM_BWR_SCGC4_EWM(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_EWM_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMT[2] (RW)
+ *
+ * This bit controls the clock gate to the CMT module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMT field. */
+#define SIM_RD_SCGC4_CMT(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMT_MASK) >> SIM_SCGC4_CMT_SHIFT)
+#define SIM_BRD_SCGC4_CMT(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT))
+
+/*! @brief Set the CMT field to a new value. */
+#define SIM_WR_SCGC4_CMT(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMT_MASK, SIM_SCGC4_CMT(value)))
+#define SIM_BWR_SCGC4_CMT(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C0[6] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C0 field. */
+#define SIM_RD_SCGC4_I2C0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C0_MASK) >> SIM_SCGC4_I2C0_SHIFT)
+#define SIM_BRD_SCGC4_I2C0(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT))
+
+/*! @brief Set the I2C0 field to a new value. */
+#define SIM_WR_SCGC4_I2C0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C0_MASK, SIM_SCGC4_I2C0(value)))
+#define SIM_BWR_SCGC4_I2C0(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field I2C1[7] (RW)
+ *
+ * This bit controls the clock gate to the I 2 C1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_I2C1 field. */
+#define SIM_RD_SCGC4_I2C1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C1_MASK) >> SIM_SCGC4_I2C1_SHIFT)
+#define SIM_BRD_SCGC4_I2C1(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT))
+
+/*! @brief Set the I2C1 field to a new value. */
+#define SIM_WR_SCGC4_I2C1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C1_MASK, SIM_SCGC4_I2C1(value)))
+#define SIM_BWR_SCGC4_I2C1(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART0[10] (RW)
+ *
+ * This bit controls the clock gate to the UART0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART0 field. */
+#define SIM_RD_SCGC4_UART0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT)
+#define SIM_BRD_SCGC4_UART0(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART0_SHIFT))
+
+/*! @brief Set the UART0 field to a new value. */
+#define SIM_WR_SCGC4_UART0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART0_MASK, SIM_SCGC4_UART0(value)))
+#define SIM_BWR_SCGC4_UART0(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART1[11] (RW)
+ *
+ * This bit controls the clock gate to the UART1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART1 field. */
+#define SIM_RD_SCGC4_UART1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT)
+#define SIM_BRD_SCGC4_UART1(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART1_SHIFT))
+
+/*! @brief Set the UART1 field to a new value. */
+#define SIM_WR_SCGC4_UART1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART1_MASK, SIM_SCGC4_UART1(value)))
+#define SIM_BWR_SCGC4_UART1(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART2[12] (RW)
+ *
+ * This bit controls the clock gate to the UART2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART2 field. */
+#define SIM_RD_SCGC4_UART2(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT)
+#define SIM_BRD_SCGC4_UART2(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT))
+
+/*! @brief Set the UART2 field to a new value. */
+#define SIM_WR_SCGC4_UART2(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART2_MASK, SIM_SCGC4_UART2(value)))
+#define SIM_BWR_SCGC4_UART2(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field UART3[13] (RW)
+ *
+ * This bit controls the clock gate to the UART3 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_UART3 field. */
+#define SIM_RD_SCGC4_UART3(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_UART3_MASK) >> SIM_SCGC4_UART3_SHIFT)
+#define SIM_BRD_SCGC4_UART3(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART3_SHIFT))
+
+/*! @brief Set the UART3 field to a new value. */
+#define SIM_WR_SCGC4_UART3(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_UART3_MASK, SIM_SCGC4_UART3(value)))
+#define SIM_BWR_SCGC4_UART3(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_UART3_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field USBOTG[18] (RW)
+ *
+ * This bit controls the clock gate to the USB module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_USBOTG field. */
+#define SIM_RD_SCGC4_USBOTG(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_USBOTG_MASK) >> SIM_SCGC4_USBOTG_SHIFT)
+#define SIM_BRD_SCGC4_USBOTG(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBOTG_SHIFT))
+
+/*! @brief Set the USBOTG field to a new value. */
+#define SIM_WR_SCGC4_USBOTG(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_USBOTG_MASK, SIM_SCGC4_USBOTG(value)))
+#define SIM_BWR_SCGC4_USBOTG(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_USBOTG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field CMP[19] (RW)
+ *
+ * This bit controls the clock gate to the comparator module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_CMP field. */
+#define SIM_RD_SCGC4_CMP(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMP_MASK) >> SIM_SCGC4_CMP_SHIFT)
+#define SIM_BRD_SCGC4_CMP(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT))
+
+/*! @brief Set the CMP field to a new value. */
+#define SIM_WR_SCGC4_CMP(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMP_MASK, SIM_SCGC4_CMP(value)))
+#define SIM_BWR_SCGC4_CMP(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC4, field VREF[20] (RW)
+ *
+ * This bit controls the clock gate to the VREF module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC4_VREF field. */
+#define SIM_RD_SCGC4_VREF(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_VREF_MASK) >> SIM_SCGC4_VREF_SHIFT)
+#define SIM_BRD_SCGC4_VREF(base) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT))
+
+/*! @brief Set the VREF field to a new value. */
+#define SIM_WR_SCGC4_VREF(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_VREF_MASK, SIM_SCGC4_VREF(value)))
+#define SIM_BWR_SCGC4_VREF(base, value) (BITBAND_ACCESS32(&SIM_SCGC4_REG(base), SIM_SCGC4_VREF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC5 - System Clock Gating Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
+ *
+ * Reset value: 0x00040182U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC5 register
+ */
+/*@{*/
+#define SIM_RD_SCGC5(base)       (SIM_SCGC5_REG(base))
+#define SIM_WR_SCGC5(base, value) (SIM_SCGC5_REG(base) = (value))
+#define SIM_RMW_SCGC5(base, mask, value) (SIM_WR_SCGC5(base, (SIM_RD_SCGC5(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) |  (value)))
+#define SIM_CLR_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) & ~(value)))
+#define SIM_TOG_SCGC5(base, value) (SIM_WR_SCGC5(base, SIM_RD_SCGC5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC5 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC5, field LPTMR[0] (RW)
+ *
+ * This bit controls software access to the Low Power Timer module.
+ *
+ * Values:
+ * - 0b0 - Access disabled
+ * - 0b1 - Access enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_LPTMR field. */
+#define SIM_RD_SCGC5_LPTMR(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPTMR_MASK) >> SIM_SCGC5_LPTMR_SHIFT)
+#define SIM_BRD_SCGC5_LPTMR(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT))
+
+/*! @brief Set the LPTMR field to a new value. */
+#define SIM_WR_SCGC5_LPTMR(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPTMR_MASK, SIM_SCGC5_LPTMR(value)))
+#define SIM_BWR_SCGC5_LPTMR(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTA[9] (RW)
+ *
+ * This bit controls the clock gate to the Port A module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTA field. */
+#define SIM_RD_SCGC5_PORTA(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTA_MASK) >> SIM_SCGC5_PORTA_SHIFT)
+#define SIM_BRD_SCGC5_PORTA(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT))
+
+/*! @brief Set the PORTA field to a new value. */
+#define SIM_WR_SCGC5_PORTA(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTA_MASK, SIM_SCGC5_PORTA(value)))
+#define SIM_BWR_SCGC5_PORTA(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTB[10] (RW)
+ *
+ * This bit controls the clock gate to the Port B module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTB field. */
+#define SIM_RD_SCGC5_PORTB(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTB_MASK) >> SIM_SCGC5_PORTB_SHIFT)
+#define SIM_BRD_SCGC5_PORTB(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT))
+
+/*! @brief Set the PORTB field to a new value. */
+#define SIM_WR_SCGC5_PORTB(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTB_MASK, SIM_SCGC5_PORTB(value)))
+#define SIM_BWR_SCGC5_PORTB(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTC[11] (RW)
+ *
+ * This bit controls the clock gate to the Port C module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTC field. */
+#define SIM_RD_SCGC5_PORTC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTC_MASK) >> SIM_SCGC5_PORTC_SHIFT)
+#define SIM_BRD_SCGC5_PORTC(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT))
+
+/*! @brief Set the PORTC field to a new value. */
+#define SIM_WR_SCGC5_PORTC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTC_MASK, SIM_SCGC5_PORTC(value)))
+#define SIM_BWR_SCGC5_PORTC(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTD[12] (RW)
+ *
+ * This bit controls the clock gate to the Port D module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTD field. */
+#define SIM_RD_SCGC5_PORTD(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTD_MASK) >> SIM_SCGC5_PORTD_SHIFT)
+#define SIM_BRD_SCGC5_PORTD(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT))
+
+/*! @brief Set the PORTD field to a new value. */
+#define SIM_WR_SCGC5_PORTD(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTD_MASK, SIM_SCGC5_PORTD(value)))
+#define SIM_BWR_SCGC5_PORTD(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC5, field PORTE[13] (RW)
+ *
+ * This bit controls the clock gate to the Port E module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC5_PORTE field. */
+#define SIM_RD_SCGC5_PORTE(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTE_MASK) >> SIM_SCGC5_PORTE_SHIFT)
+#define SIM_BRD_SCGC5_PORTE(base) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT))
+
+/*! @brief Set the PORTE field to a new value. */
+#define SIM_WR_SCGC5_PORTE(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTE_MASK, SIM_SCGC5_PORTE(value)))
+#define SIM_BWR_SCGC5_PORTE(base, value) (BITBAND_ACCESS32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC6 - System Clock Gating Control Register 6
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
+ *
+ * Reset value: 0x40000001U
+ *
+ * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
+ * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
+ * When accessing through AIPS0, define the clock gate control bits in SCGC6.
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC6 register
+ */
+/*@{*/
+#define SIM_RD_SCGC6(base)       (SIM_SCGC6_REG(base))
+#define SIM_WR_SCGC6(base, value) (SIM_SCGC6_REG(base) = (value))
+#define SIM_RMW_SCGC6(base, mask, value) (SIM_WR_SCGC6(base, (SIM_RD_SCGC6(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) |  (value)))
+#define SIM_CLR_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) & ~(value)))
+#define SIM_TOG_SCGC6(base, value) (SIM_WR_SCGC6(base, SIM_RD_SCGC6(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC6 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC6, field FTF[0] (RW)
+ *
+ * This bit controls the clock gate to the flash memory. Flash reads are still
+ * supported while the flash memory is clock gated, but entry into low power modes
+ * is blocked.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTF field. */
+#define SIM_RD_SCGC6_FTF(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTF_MASK) >> SIM_SCGC6_FTF_SHIFT)
+#define SIM_BRD_SCGC6_FTF(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT))
+
+/*! @brief Set the FTF field to a new value. */
+#define SIM_WR_SCGC6_FTF(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTF_MASK, SIM_SCGC6_FTF(value)))
+#define SIM_BWR_SCGC6_FTF(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA Mux module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */
+#define SIM_RD_SCGC6_DMAMUX(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DMAMUX_MASK) >> SIM_SCGC6_DMAMUX_SHIFT)
+#define SIM_BRD_SCGC6_DMAMUX(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT))
+
+/*! @brief Set the DMAMUX field to a new value. */
+#define SIM_WR_SCGC6_DMAMUX(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DMAMUX_MASK, SIM_SCGC6_DMAMUX(value)))
+#define SIM_BWR_SCGC6_DMAMUX(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
+ *
+ * This bit controls the clock gate to the FlexCAN0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. */
+#define SIM_RD_SCGC6_FLEXCAN0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FLEXCAN0_MASK) >> SIM_SCGC6_FLEXCAN0_SHIFT)
+#define SIM_BRD_SCGC6_FLEXCAN0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FLEXCAN0_SHIFT))
+
+/*! @brief Set the FLEXCAN0 field to a new value. */
+#define SIM_WR_SCGC6_FLEXCAN0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FLEXCAN0_MASK, SIM_SCGC6_FLEXCAN0(value)))
+#define SIM_BWR_SCGC6_FLEXCAN0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FLEXCAN0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RNGA[9] (RW)
+ *
+ * This bit controls the clock gate to the RNGA module.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RNGA field. */
+#define SIM_RD_SCGC6_RNGA(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RNGA_MASK) >> SIM_SCGC6_RNGA_SHIFT)
+#define SIM_BRD_SCGC6_RNGA(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RNGA_SHIFT))
+
+/*! @brief Set the RNGA field to a new value. */
+#define SIM_WR_SCGC6_RNGA(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RNGA_MASK, SIM_SCGC6_RNGA(value)))
+#define SIM_BWR_SCGC6_RNGA(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RNGA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field SPI0[12] (RW)
+ *
+ * This bit controls the clock gate to the SPI0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_SPI0 field. */
+#define SIM_RD_SCGC6_SPI0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI0_MASK) >> SIM_SCGC6_SPI0_SHIFT)
+#define SIM_BRD_SCGC6_SPI0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT))
+
+/*! @brief Set the SPI0 field to a new value. */
+#define SIM_WR_SCGC6_SPI0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI0_MASK, SIM_SCGC6_SPI0(value)))
+#define SIM_BWR_SCGC6_SPI0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field SPI1[13] (RW)
+ *
+ * This bit controls the clock gate to the SPI1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_SPI1 field. */
+#define SIM_RD_SCGC6_SPI1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI1_MASK) >> SIM_SCGC6_SPI1_SHIFT)
+#define SIM_BRD_SCGC6_SPI1(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT))
+
+/*! @brief Set the SPI1 field to a new value. */
+#define SIM_WR_SCGC6_SPI1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI1_MASK, SIM_SCGC6_SPI1(value)))
+#define SIM_BWR_SCGC6_SPI1(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field I2S[15] (RW)
+ *
+ * This bit controls the clock gate to the I 2 S module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_I2S field. */
+#define SIM_RD_SCGC6_I2S(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_I2S_MASK) >> SIM_SCGC6_I2S_SHIFT)
+#define SIM_BRD_SCGC6_I2S(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT))
+
+/*! @brief Set the I2S field to a new value. */
+#define SIM_WR_SCGC6_I2S(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_I2S_MASK, SIM_SCGC6_I2S(value)))
+#define SIM_BWR_SCGC6_I2S(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_I2S_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field CRC[18] (RW)
+ *
+ * This bit controls the clock gate to the CRC module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_CRC field. */
+#define SIM_RD_SCGC6_CRC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_CRC_MASK) >> SIM_SCGC6_CRC_SHIFT)
+#define SIM_BRD_SCGC6_CRC(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_CRC_SHIFT))
+
+/*! @brief Set the CRC field to a new value. */
+#define SIM_WR_SCGC6_CRC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_CRC_MASK, SIM_SCGC6_CRC(value)))
+#define SIM_BWR_SCGC6_CRC(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_CRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field USBDCD[21] (RW)
+ *
+ * This bit controls the clock gate to the USB DCD module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_USBDCD field. */
+#define SIM_RD_SCGC6_USBDCD(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_USBDCD_MASK) >> SIM_SCGC6_USBDCD_SHIFT)
+#define SIM_BRD_SCGC6_USBDCD(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_USBDCD_SHIFT))
+
+/*! @brief Set the USBDCD field to a new value. */
+#define SIM_WR_SCGC6_USBDCD(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_USBDCD_MASK, SIM_SCGC6_USBDCD(value)))
+#define SIM_BWR_SCGC6_USBDCD(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_USBDCD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PDB[22] (RW)
+ *
+ * This bit controls the clock gate to the PDB module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PDB field. */
+#define SIM_RD_SCGC6_PDB(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PDB_MASK) >> SIM_SCGC6_PDB_SHIFT)
+#define SIM_BRD_SCGC6_PDB(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PDB_SHIFT))
+
+/*! @brief Set the PDB field to a new value. */
+#define SIM_WR_SCGC6_PDB(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PDB_MASK, SIM_SCGC6_PDB(value)))
+#define SIM_BWR_SCGC6_PDB(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PDB_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field PIT[23] (RW)
+ *
+ * This bit controls the clock gate to the PIT module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_PIT field. */
+#define SIM_RD_SCGC6_PIT(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PIT_MASK) >> SIM_SCGC6_PIT_SHIFT)
+#define SIM_BRD_SCGC6_PIT(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT))
+
+/*! @brief Set the PIT field to a new value. */
+#define SIM_WR_SCGC6_PIT(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PIT_MASK, SIM_SCGC6_PIT(value)))
+#define SIM_BWR_SCGC6_PIT(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM0[24] (RW)
+ *
+ * This bit controls the clock gate to the FTM0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM0 field. */
+#define SIM_RD_SCGC6_FTM0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM0_MASK) >> SIM_SCGC6_FTM0_SHIFT)
+#define SIM_BRD_SCGC6_FTM0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM0_SHIFT))
+
+/*! @brief Set the FTM0 field to a new value. */
+#define SIM_WR_SCGC6_FTM0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM0_MASK, SIM_SCGC6_FTM0(value)))
+#define SIM_BWR_SCGC6_FTM0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM1[25] (RW)
+ *
+ * This bit controls the clock gate to the FTM1 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM1 field. */
+#define SIM_RD_SCGC6_FTM1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM1_MASK) >> SIM_SCGC6_FTM1_SHIFT)
+#define SIM_BRD_SCGC6_FTM1(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM1_SHIFT))
+
+/*! @brief Set the FTM1 field to a new value. */
+#define SIM_WR_SCGC6_FTM1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM1_MASK, SIM_SCGC6_FTM1(value)))
+#define SIM_BWR_SCGC6_FTM1(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM1_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field FTM2[26] (RW)
+ *
+ * This bit controls the clock gate to the FTM2 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_FTM2 field. */
+#define SIM_RD_SCGC6_FTM2(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTM2_MASK) >> SIM_SCGC6_FTM2_SHIFT)
+#define SIM_BRD_SCGC6_FTM2(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM2_SHIFT))
+
+/*! @brief Set the FTM2 field to a new value. */
+#define SIM_WR_SCGC6_FTM2(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTM2_MASK, SIM_SCGC6_FTM2(value)))
+#define SIM_BWR_SCGC6_FTM2(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTM2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field ADC0[27] (RW)
+ *
+ * This bit controls the clock gate to the ADC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_ADC0 field. */
+#define SIM_RD_SCGC6_ADC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_ADC0_MASK) >> SIM_SCGC6_ADC0_SHIFT)
+#define SIM_BRD_SCGC6_ADC0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT))
+
+/*! @brief Set the ADC0 field to a new value. */
+#define SIM_WR_SCGC6_ADC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_ADC0_MASK, SIM_SCGC6_ADC0(value)))
+#define SIM_BWR_SCGC6_ADC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field RTC[29] (RW)
+ *
+ * This bit controls software access and interrupts to the RTC module.
+ *
+ * Values:
+ * - 0b0 - Access and interrupts disabled
+ * - 0b1 - Access and interrupts enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_RTC field. */
+#define SIM_RD_SCGC6_RTC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RTC_MASK) >> SIM_SCGC6_RTC_SHIFT)
+#define SIM_BRD_SCGC6_RTC(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT))
+
+/*! @brief Set the RTC field to a new value. */
+#define SIM_WR_SCGC6_RTC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RTC_MASK, SIM_SCGC6_RTC(value)))
+#define SIM_BWR_SCGC6_RTC(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC6, field DAC0[31] (RW)
+ *
+ * This bit controls the clock gate to the DAC0 module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC6_DAC0 field. */
+#define SIM_RD_SCGC6_DAC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DAC0_MASK) >> SIM_SCGC6_DAC0_SHIFT)
+#define SIM_BRD_SCGC6_DAC0(base) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT))
+
+/*! @brief Set the DAC0 field to a new value. */
+#define SIM_WR_SCGC6_DAC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DAC0_MASK, SIM_SCGC6_DAC0(value)))
+#define SIM_BWR_SCGC6_DAC0(base, value) (BITBAND_ACCESS32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_SCGC7 - System Clock Gating Control Register 7
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
+ *
+ * Reset value: 0x00000006U
+ */
+/*!
+ * @name Constants and macros for entire SIM_SCGC7 register
+ */
+/*@{*/
+#define SIM_RD_SCGC7(base)       (SIM_SCGC7_REG(base))
+#define SIM_WR_SCGC7(base, value) (SIM_SCGC7_REG(base) = (value))
+#define SIM_RMW_SCGC7(base, mask, value) (SIM_WR_SCGC7(base, (SIM_RD_SCGC7(base) & ~(mask)) | (value)))
+#define SIM_SET_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) |  (value)))
+#define SIM_CLR_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) & ~(value)))
+#define SIM_TOG_SCGC7(base, value) (SIM_WR_SCGC7(base, SIM_RD_SCGC7(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_SCGC7 bitfields
+ */
+
+/*!
+ * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
+ *
+ * This bit controls the clock gate to the FlexBus module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */
+#define SIM_RD_SCGC7_FLEXBUS(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_FLEXBUS_MASK) >> SIM_SCGC7_FLEXBUS_SHIFT)
+#define SIM_BRD_SCGC7_FLEXBUS(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_FLEXBUS_SHIFT))
+
+/*! @brief Set the FLEXBUS field to a new value. */
+#define SIM_WR_SCGC7_FLEXBUS(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_FLEXBUS_MASK, SIM_SCGC7_FLEXBUS(value)))
+#define SIM_BWR_SCGC7_FLEXBUS(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_FLEXBUS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC7, field DMA[1] (RW)
+ *
+ * This bit controls the clock gate to the DMA module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_DMA field. */
+#define SIM_RD_SCGC7_DMA(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_DMA_MASK) >> SIM_SCGC7_DMA_SHIFT)
+#define SIM_BRD_SCGC7_DMA(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT))
+
+/*! @brief Set the DMA field to a new value. */
+#define SIM_WR_SCGC7_DMA(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_DMA_MASK, SIM_SCGC7_DMA(value)))
+#define SIM_BWR_SCGC7_DMA(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_SCGC7, field MPU[2] (RW)
+ *
+ * This bit controls the clock gate to the MPU module.
+ *
+ * Values:
+ * - 0b0 - Clock disabled
+ * - 0b1 - Clock enabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_SCGC7_MPU field. */
+#define SIM_RD_SCGC7_MPU(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_MPU_MASK) >> SIM_SCGC7_MPU_SHIFT)
+#define SIM_BRD_SCGC7_MPU(base) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_MPU_SHIFT))
+
+/*! @brief Set the MPU field to a new value. */
+#define SIM_WR_SCGC7_MPU(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_MPU_MASK, SIM_SCGC7_MPU(value)))
+#define SIM_BWR_SCGC7_MPU(base, value) (BITBAND_ACCESS32(&SIM_SCGC7_REG(base), SIM_SCGC7_MPU_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV1 - System Clock Divider Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * When updating CLKDIV1, update all fields using the one write command.
+ * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
+ * write to be ignored. The maximum divide ratio that can be programmed between
+ * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
+ * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
+ * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
+ * mode.
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV1 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV1(base)     (SIM_CLKDIV1_REG(base))
+#define SIM_WR_CLKDIV1(base, value) (SIM_CLKDIV1_REG(base) = (value))
+#define SIM_RMW_CLKDIV1(base, mask, value) (SIM_WR_CLKDIV1(base, (SIM_RD_CLKDIV1(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) |  (value)))
+#define SIM_CLR_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) & ~(value)))
+#define SIM_TOG_CLKDIV1(base, value) (SIM_WR_CLKDIV1(base, SIM_RD_CLKDIV1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV1 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
+ *
+ * This field sets the divide value for the flash clock from MCGOUTCLK. At the
+ * end of reset, it is loaded with either 0001 or 1111 depending on
+ * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
+ * frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */
+#define SIM_RD_CLKDIV1_OUTDIV4(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV4(base) (SIM_RD_CLKDIV1_OUTDIV4(base))
+
+/*! @brief Set the OUTDIV4 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV4(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV4_MASK, SIM_CLKDIV1_OUTDIV4(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV4(base, value) (SIM_WR_CLKDIV1_OUTDIV4(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
+ *
+ * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
+ * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
+ * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
+ * divide of the system clock frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */
+#define SIM_RD_CLKDIV1_OUTDIV3(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV3(base) (SIM_RD_CLKDIV1_OUTDIV3(base))
+
+/*! @brief Set the OUTDIV3 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV3(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV3_MASK, SIM_CLKDIV1_OUTDIV3(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV3(base, value) (SIM_WR_CLKDIV1_OUTDIV3(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
+ *
+ * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
+ * of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
+ * frequency.
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */
+#define SIM_RD_CLKDIV1_OUTDIV2(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV2(base) (SIM_RD_CLKDIV1_OUTDIV2(base))
+
+/*! @brief Set the OUTDIV2 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV2(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV2_MASK, SIM_CLKDIV1_OUTDIV2(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV2(base, value) (SIM_WR_CLKDIV1_OUTDIV2(base, value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
+ *
+ * This field sets the divide value for the core/system clock from MCGOUTCLK. At
+ * the end of reset, it is loaded with either 0000 or 0111 depending on
+ * FTF_FOPT[LPBOOT].
+ *
+ * Values:
+ * - 0b0000 - Divide-by-1.
+ * - 0b0001 - Divide-by-2.
+ * - 0b0010 - Divide-by-3.
+ * - 0b0011 - Divide-by-4.
+ * - 0b0100 - Divide-by-5.
+ * - 0b0101 - Divide-by-6.
+ * - 0b0110 - Divide-by-7.
+ * - 0b0111 - Divide-by-8.
+ * - 0b1000 - Divide-by-9.
+ * - 0b1001 - Divide-by-10.
+ * - 0b1010 - Divide-by-11.
+ * - 0b1011 - Divide-by-12.
+ * - 0b1100 - Divide-by-13.
+ * - 0b1101 - Divide-by-14.
+ * - 0b1110 - Divide-by-15.
+ * - 0b1111 - Divide-by-16.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */
+#define SIM_RD_CLKDIV1_OUTDIV1(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
+#define SIM_BRD_CLKDIV1_OUTDIV1(base) (SIM_RD_CLKDIV1_OUTDIV1(base))
+
+/*! @brief Set the OUTDIV1 field to a new value. */
+#define SIM_WR_CLKDIV1_OUTDIV1(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV1_MASK, SIM_CLKDIV1_OUTDIV1(value)))
+#define SIM_BWR_CLKDIV1_OUTDIV1(base, value) (SIM_WR_CLKDIV1_OUTDIV1(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_CLKDIV2 - System Clock Divider Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_CLKDIV2 register
+ */
+/*@{*/
+#define SIM_RD_CLKDIV2(base)     (SIM_CLKDIV2_REG(base))
+#define SIM_WR_CLKDIV2(base, value) (SIM_CLKDIV2_REG(base) = (value))
+#define SIM_RMW_CLKDIV2(base, mask, value) (SIM_WR_CLKDIV2(base, (SIM_RD_CLKDIV2(base) & ~(mask)) | (value)))
+#define SIM_SET_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) |  (value)))
+#define SIM_CLR_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) & ~(value)))
+#define SIM_TOG_CLKDIV2(base, value) (SIM_WR_CLKDIV2(base, SIM_RD_CLKDIV2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_CLKDIV2 bitfields
+ */
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
+ *
+ * This field sets the fraction multiply value for the fractional clock divider
+ * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
+ * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. */
+#define SIM_RD_CLKDIV2_USBFRAC(base) ((SIM_CLKDIV2_REG(base) & SIM_CLKDIV2_USBFRAC_MASK) >> SIM_CLKDIV2_USBFRAC_SHIFT)
+#define SIM_BRD_CLKDIV2_USBFRAC(base) (BITBAND_ACCESS32(&SIM_CLKDIV2_REG(base), SIM_CLKDIV2_USBFRAC_SHIFT))
+
+/*! @brief Set the USBFRAC field to a new value. */
+#define SIM_WR_CLKDIV2_USBFRAC(base, value) (SIM_RMW_CLKDIV2(base, SIM_CLKDIV2_USBFRAC_MASK, SIM_CLKDIV2_USBFRAC(value)))
+#define SIM_BWR_CLKDIV2_USBFRAC(base, value) (BITBAND_ACCESS32(&SIM_CLKDIV2_REG(base), SIM_CLKDIV2_USBFRAC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
+ *
+ * This field sets the divide value for the fractional clock divider when the
+ * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
+ * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_CLKDIV2_USBDIV field. */
+#define SIM_RD_CLKDIV2_USBDIV(base) ((SIM_CLKDIV2_REG(base) & SIM_CLKDIV2_USBDIV_MASK) >> SIM_CLKDIV2_USBDIV_SHIFT)
+#define SIM_BRD_CLKDIV2_USBDIV(base) (SIM_RD_CLKDIV2_USBDIV(base))
+
+/*! @brief Set the USBDIV field to a new value. */
+#define SIM_WR_CLKDIV2_USBDIV(base, value) (SIM_RMW_CLKDIV2(base, SIM_CLKDIV2_USBDIV_MASK, SIM_CLKDIV2_USBDIV(value)))
+#define SIM_BWR_CLKDIV2_USBDIV(base, value) (SIM_WR_CLKDIV2_USBDIV(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG1 - Flash Configuration Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG1 - Flash Configuration Register 1 (RW)
+ *
+ * Reset value: 0xFF0F0F00U
+ *
+ * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
+ * user programming in user IFR via the PGMPART flash command. For devices with
+ * program flash only:
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG1 register
+ */
+/*@{*/
+#define SIM_RD_FCFG1(base)       (SIM_FCFG1_REG(base))
+#define SIM_WR_FCFG1(base, value) (SIM_FCFG1_REG(base) = (value))
+#define SIM_RMW_FCFG1(base, mask, value) (SIM_WR_FCFG1(base, (SIM_RD_FCFG1(base) & ~(mask)) | (value)))
+#define SIM_SET_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) |  (value)))
+#define SIM_CLR_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) & ~(value)))
+#define SIM_TOG_FCFG1(base, value) (SIM_WR_FCFG1(base, SIM_RD_FCFG1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG1 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
+ *
+ * Flash accesses are disabled (and generate a bus error) and the Flash memory
+ * is placed in a low power state. This bit should not be changed during VLP
+ * modes. Relocate the interrupt vectors out of Flash memory before disabling the
+ * Flash.
+ *
+ * Values:
+ * - 0b0 - Flash is enabled
+ * - 0b1 - Flash is disabled
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */
+#define SIM_RD_FCFG1_FLASHDIS(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDIS_MASK) >> SIM_FCFG1_FLASHDIS_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDIS(base) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT))
+
+/*! @brief Set the FLASHDIS field to a new value. */
+#define SIM_WR_FCFG1_FLASHDIS(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDIS_MASK, SIM_FCFG1_FLASHDIS(value)))
+#define SIM_BWR_FCFG1_FLASHDIS(base, value) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
+ *
+ * When set, Flash memory is disabled for the duration of Wait mode. An attempt
+ * by the DMA or other bus master to access the Flash when the Flash is disabled
+ * will result in a bus error. This bit should be clear during VLP modes. The
+ * Flash will be automatically enabled again at the end of Wait mode so interrupt
+ * vectors do not need to be relocated out of Flash memory. The wakeup time from
+ * Wait mode is extended when this bit is set.
+ *
+ * Values:
+ * - 0b0 - Flash remains enabled during Wait mode
+ * - 0b1 - Flash is disabled for the duration of Wait mode
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */
+#define SIM_RD_FCFG1_FLASHDOZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDOZE_MASK) >> SIM_FCFG1_FLASHDOZE_SHIFT)
+#define SIM_BRD_FCFG1_FLASHDOZE(base) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT))
+
+/*! @brief Set the FLASHDOZE field to a new value. */
+#define SIM_WR_FCFG1_FLASHDOZE(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDOZE_MASK, SIM_FCFG1_FLASHDOZE(value)))
+#define SIM_BWR_FCFG1_FLASHDOZE(base, value) (BITBAND_ACCESS32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
+ *
+ * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
+ * description in FTFE chapter. For devices without FlexNVM: Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_DEPART field. */
+#define SIM_RD_FCFG1_DEPART(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT)
+#define SIM_BRD_FCFG1_DEPART(base) (SIM_RD_FCFG1_DEPART(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
+ *
+ * EEPROM data size .
+ *
+ * Values:
+ * - 0b0000 - 16 KB
+ * - 0b0001 - 8 KB
+ * - 0b0010 - 4 KB
+ * - 0b0011 - 2 KB
+ * - 0b0100 - 1 KB
+ * - 0b0101 - 512 Bytes
+ * - 0b0110 - 256 Bytes
+ * - 0b0111 - 128 Bytes
+ * - 0b1000 - 64 Bytes
+ * - 0b1001 - 32 Bytes
+ * - 0b1111 - 0 Bytes
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_EESIZE field. */
+#define SIM_RD_FCFG1_EESIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_EESIZE_MASK) >> SIM_FCFG1_EESIZE_SHIFT)
+#define SIM_BRD_FCFG1_EESIZE(base) (SIM_RD_FCFG1_EESIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
+ *
+ * This field specifies the amount of program flash memory available on the
+ * device . Undefined values are reserved.
+ *
+ * Values:
+ * - 0b0011 - 32 KB of program flash memory
+ * - 0b0101 - 64 KB of program flash memory
+ * - 0b0111 - 128 KB of program flash memory
+ * - 0b1001 - 256 KB of program flash memory
+ * - 0b1011 - 512 KB of program flash memory
+ * - 0b1101 - 1024 KB of program flash memory
+ * - 0b1111 - 1024 KB of program flash memory
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */
+#define SIM_RD_FCFG1_PFSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT)
+#define SIM_BRD_FCFG1_PFSIZE(base) (SIM_RD_FCFG1_PFSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
+ *
+ * This field specifies the amount of FlexNVM memory available on the device .
+ * Undefined values are reserved.
+ *
+ * Values:
+ * - 0b0000 - 0 KB of FlexNVM
+ * - 0b0011 - 32 KB of FlexNVM
+ * - 0b0101 - 64 KB of FlexNVM
+ * - 0b0111 - 128 KB of FlexNVM
+ * - 0b1001 - 256 KB of FlexNVM
+ * - 0b1011 - 512 KB of FlexNVM
+ * - 0b1111 - 512 KB of FlexNVM
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG1_NVMSIZE field. */
+#define SIM_RD_FCFG1_NVMSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_NVMSIZE_MASK) >> SIM_FCFG1_NVMSIZE_SHIFT)
+#define SIM_BRD_FCFG1_NVMSIZE(base) (SIM_RD_FCFG1_NVMSIZE(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_FCFG2 - Flash Configuration Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_FCFG2 - Flash Configuration Register 2 (RO)
+ *
+ * Reset value: 0x7F7F0000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_FCFG2 register
+ */
+/*@{*/
+#define SIM_RD_FCFG2(base)       (SIM_FCFG2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SIM_FCFG2 bitfields
+ */
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
+ *
+ * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
+ * the FlexNVM base address indicates the first invalid address of the FlexNVM
+ * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
+ * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
+ * for a device with 256 KB FlexNVM. For devices with program flash only: This
+ * field equals zero if there is only one program flash block, otherwise it equals
+ * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
+ * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
+ * the MAXADDR1 value for a device with 512 KB program flash memory across two
+ * flash blocks and no FlexNVM.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */
+#define SIM_RD_FCFG2_MAXADDR1(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR1_MASK) >> SIM_FCFG2_MAXADDR1_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR1(base) (SIM_RD_FCFG2_MAXADDR1(base))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field PFLSH[23] (RO)
+ *
+ * For devices with FlexNVM, this bit is always clear. For devices without
+ * FlexNVM, this bit is always set.
+ *
+ * Values:
+ * - 0b0 - Device supports FlexNVM
+ * - 0b1 - Program Flash only, device does not support FlexNVM
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_PFLSH field. */
+#define SIM_RD_FCFG2_PFLSH(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_PFLSH_MASK) >> SIM_FCFG2_PFLSH_SHIFT)
+#define SIM_BRD_FCFG2_PFLSH(base) (BITBAND_ACCESS32(&SIM_FCFG2_REG(base), SIM_FCFG2_PFLSH_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
+ *
+ * This field concatenated with 13 trailing zeros indicates the first invalid
+ * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
+ * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
+ * value for a device with 256 KB program flash in flash block 0.
+ */
+/*@{*/
+/*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */
+#define SIM_RD_FCFG2_MAXADDR0(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR0_MASK) >> SIM_FCFG2_MAXADDR0_SHIFT)
+#define SIM_BRD_FCFG2_MAXADDR0(base) (SIM_RD_FCFG2_MAXADDR0(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDH - Unique Identification Register High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDH - Unique Identification Register High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDH register
+ */
+/*@{*/
+#define SIM_RD_UIDH(base)        (SIM_UIDH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDMH - Unique Identification Register Mid-High
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDMH - Unique Identification Register Mid-High (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDMH register
+ */
+/*@{*/
+#define SIM_RD_UIDMH(base)       (SIM_UIDMH_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDML - Unique Identification Register Mid Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDML - Unique Identification Register Mid Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDML register
+ */
+/*@{*/
+#define SIM_RD_UIDML(base)       (SIM_UIDML_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SIM_UIDL - Unique Identification Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief SIM_UIDL - Unique Identification Register Low (RO)
+ *
+ * Reset value: 0x00000000U
+ */
+/*!
+ * @name Constants and macros for entire SIM_UIDL register
+ */
+/*@{*/
+#define SIM_RD_UIDL(base)        (SIM_UIDL_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 SMC
+ *
+ * System Mode Controller
+ *
+ * Registers defined in this header file:
+ * - SMC_PMPROT - Power Mode Protection register
+ * - SMC_PMCTRL - Power Mode Control register
+ * - SMC_VLLSCTRL - VLLS Control register
+ * - SMC_PMSTAT - Power Mode Status register
+ */
+
+#define SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
+#define SMC_IDX (0U) /*!< Instance number for SMC. */
+
+/*******************************************************************************
+ * SMC_PMPROT - Power Mode Protection register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMPROT - Power Mode Protection register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides protection for entry into any low-power run or stop
+ * mode. The enabling of the low-power run or stop mode occurs by configuring the
+ * Power Mode Control register (PMCTRL). The PMPROT register can be written only
+ * once after any system reset. If the MCU is configured for a disallowed or
+ * reserved power mode, the MCU remains in its current power mode. For example, if the
+ * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
+ * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
+ * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
+ * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
+ * that do not trigger Chip Reset not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMPROT register
+ */
+/*@{*/
+#define SMC_RD_PMPROT(base)      (SMC_PMPROT_REG(base))
+#define SMC_WR_PMPROT(base, value) (SMC_PMPROT_REG(base) = (value))
+#define SMC_RMW_PMPROT(base, mask, value) (SMC_WR_PMPROT(base, (SMC_RD_PMPROT(base) & ~(mask)) | (value)))
+#define SMC_SET_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) |  (value)))
+#define SMC_CLR_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) & ~(value)))
+#define SMC_TOG_PMPROT(base, value) (SMC_WR_PMPROT(base, SMC_RD_PMPROT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMPROT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMPROT, field AVLLS[1] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write once
+ * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
+ *
+ * Values:
+ * - 0b0 - Any VLLSx mode is not allowed
+ * - 0b1 - Any VLLSx mode is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
+#define SMC_RD_PMPROT_AVLLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLLS_MASK) >> SMC_PMPROT_AVLLS_SHIFT)
+#define SMC_BRD_PMPROT_AVLLS(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT))
+
+/*! @brief Set the AVLLS field to a new value. */
+#define SMC_WR_PMPROT_AVLLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLLS_MASK, SMC_PMPROT_AVLLS(value)))
+#define SMC_BWR_PMPROT_AVLLS(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field ALLS[3] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any low-leakage stop mode (LLS).
+ *
+ * Values:
+ * - 0b0 - LLS is not allowed
+ * - 0b1 - LLS is allowed
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_ALLS field. */
+#define SMC_RD_PMPROT_ALLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_ALLS_MASK) >> SMC_PMPROT_ALLS_SHIFT)
+#define SMC_BRD_PMPROT_ALLS(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT))
+
+/*! @brief Set the ALLS field to a new value. */
+#define SMC_WR_PMPROT_ALLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_ALLS_MASK, SMC_PMPROT_ALLS(value)))
+#define SMC_BWR_PMPROT_ALLS(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMPROT, field AVLP[5] (RW)
+ *
+ * Provided the appropriate control bits are set up in PMCTRL, this write-once
+ * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
+ *
+ * Values:
+ * - 0b0 - VLPR, VLPW, and VLPS are not allowed.
+ * - 0b1 - VLPR, VLPW, and VLPS are allowed.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMPROT_AVLP field. */
+#define SMC_RD_PMPROT_AVLP(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLP_MASK) >> SMC_PMPROT_AVLP_SHIFT)
+#define SMC_BRD_PMPROT_AVLP(base) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT))
+
+/*! @brief Set the AVLP field to a new value. */
+#define SMC_WR_PMPROT_AVLP(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLP_MASK, SMC_PMPROT_AVLP(value)))
+#define SMC_BWR_PMPROT_AVLP(base, value) (BITBAND_ACCESS8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMCTRL - Power Mode Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMCTRL - Power Mode Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The PMCTRL register controls entry into low-power Run and Stop modes,
+ * provided that the selected power mode is allowed via an appropriate setting of the
+ * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
+ * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
+ * that do not trigger Chip POR not VLLS. See the Reset section details for more
+ * information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMCTRL register
+ */
+/*@{*/
+#define SMC_RD_PMCTRL(base)      (SMC_PMCTRL_REG(base))
+#define SMC_WR_PMCTRL(base, value) (SMC_PMCTRL_REG(base) = (value))
+#define SMC_RMW_PMCTRL(base, mask, value) (SMC_WR_PMCTRL(base, (SMC_RD_PMCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) |  (value)))
+#define SMC_CLR_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) & ~(value)))
+#define SMC_TOG_PMCTRL(base, value) (SMC_WR_PMCTRL(base, SMC_RD_PMCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
+ *
+ * When written, controls entry into the selected stop mode when Sleep-Now or
+ * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
+ * blocked if the protection level has not been enabled using the PMPROT register.
+ * After any system reset, this field is cleared by hardware on any successful write
+ * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
+ * register is used to further select the particular VLLS submode which will be
+ * entered.
+ *
+ * Values:
+ * - 0b000 - Normal Stop (STOP)
+ * - 0b001 - Reserved
+ * - 0b010 - Very-Low-Power Stop (VLPS)
+ * - 0b011 - Low-Leakage Stop (LLS)
+ * - 0b100 - Very-Low-Leakage Stop (VLLSx)
+ * - 0b101 - Reserved
+ * - 0b110 - Reseved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
+#define SMC_RD_PMCTRL_STOPM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPM_MASK) >> SMC_PMCTRL_STOPM_SHIFT)
+#define SMC_BRD_PMCTRL_STOPM(base) (SMC_RD_PMCTRL_STOPM(base))
+
+/*! @brief Set the STOPM field to a new value. */
+#define SMC_WR_PMCTRL_STOPM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_STOPM_MASK, SMC_PMCTRL_STOPM(value)))
+#define SMC_BWR_PMCTRL_STOPM(base, value) (SMC_WR_PMCTRL_STOPM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field STOPA[3] (RO)
+ *
+ * When set, this read-only status bit indicates an interrupt or reset occured
+ * during the previous stop mode entry sequence, preventing the system from
+ * entering that mode. This field is cleared by hardware at the beginning of any stop
+ * mode entry sequence and is set if the sequence was aborted.
+ *
+ * Values:
+ * - 0b0 - The previous stop mode entry was successsful.
+ * - 0b1 - The previous stop mode entry was aborted.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
+#define SMC_RD_PMCTRL_STOPA(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPA_MASK) >> SMC_PMCTRL_STOPA_SHIFT)
+#define SMC_BRD_PMCTRL_STOPA(base) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_STOPA_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
+ *
+ * When written, causes entry into the selected run mode. Writes to this field
+ * are blocked if the protection level has not been enabled using the PMPROT
+ * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
+ * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
+ *
+ * Values:
+ * - 0b00 - Normal Run mode (RUN)
+ * - 0b01 - Reserved
+ * - 0b10 - Very-Low-Power Run mode (VLPR)
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
+#define SMC_RD_PMCTRL_RUNM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_RUNM_MASK) >> SMC_PMCTRL_RUNM_SHIFT)
+#define SMC_BRD_PMCTRL_RUNM(base) (SMC_RD_PMCTRL_RUNM(base))
+
+/*! @brief Set the RUNM field to a new value. */
+#define SMC_WR_PMCTRL_RUNM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_RUNM_MASK, SMC_PMCTRL_RUNM(value)))
+#define SMC_BWR_PMCTRL_RUNM(base, value) (SMC_WR_PMCTRL_RUNM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
+ *
+ * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
+ * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
+ * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
+ * the LPWUI setting. LPWUI must be modified only while the system is in RUN
+ * mode, that is, when PMSTAT=RUN.
+ *
+ * Values:
+ * - 0b0 - The system remains in a VLP mode on an interrupt
+ * - 0b1 - The system exits to Normal RUN mode on an interrupt
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMCTRL_LPWUI field. */
+#define SMC_RD_PMCTRL_LPWUI(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_LPWUI_MASK) >> SMC_PMCTRL_LPWUI_SHIFT)
+#define SMC_BRD_PMCTRL_LPWUI(base) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_LPWUI_SHIFT))
+
+/*! @brief Set the LPWUI field to a new value. */
+#define SMC_WR_PMCTRL_LPWUI(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_LPWUI_MASK, SMC_PMCTRL_LPWUI(value)))
+#define SMC_BWR_PMCTRL_LPWUI(base, value) (BITBAND_ACCESS8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_LPWUI_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_VLLSCTRL - VLLS Control register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_VLLSCTRL - VLLS Control register (RW)
+ *
+ * Reset value: 0x03U
+ *
+ * The VLLSCTRL register controls features related to VLLS modes. This register
+ * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
+ * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
+ * the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_VLLSCTRL register
+ */
+/*@{*/
+#define SMC_RD_VLLSCTRL(base)    (SMC_VLLSCTRL_REG(base))
+#define SMC_WR_VLLSCTRL(base, value) (SMC_VLLSCTRL_REG(base) = (value))
+#define SMC_RMW_VLLSCTRL(base, mask, value) (SMC_WR_VLLSCTRL(base, (SMC_RD_VLLSCTRL(base) & ~(mask)) | (value)))
+#define SMC_SET_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) |  (value)))
+#define SMC_CLR_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) & ~(value)))
+#define SMC_TOG_VLLSCTRL(base, value) (SMC_WR_VLLSCTRL(base, SMC_RD_VLLSCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_VLLSCTRL bitfields
+ */
+
+/*!
+ * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
+ *
+ * Controls which VLLS sub-mode to enter if STOPM=VLLS.
+ *
+ * Values:
+ * - 0b000 - VLLS0
+ * - 0b001 - VLLS1
+ * - 0b010 - VLLS2
+ * - 0b011 - VLLS3
+ * - 0b100 - Reserved
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_VLLSCTRL_VLLSM field. */
+#define SMC_RD_VLLSCTRL_VLLSM(base) ((SMC_VLLSCTRL_REG(base) & SMC_VLLSCTRL_VLLSM_MASK) >> SMC_VLLSCTRL_VLLSM_SHIFT)
+#define SMC_BRD_VLLSCTRL_VLLSM(base) (SMC_RD_VLLSCTRL_VLLSM(base))
+
+/*! @brief Set the VLLSM field to a new value. */
+#define SMC_WR_VLLSCTRL_VLLSM(base, value) (SMC_RMW_VLLSCTRL(base, SMC_VLLSCTRL_VLLSM_MASK, SMC_VLLSCTRL_VLLSM(value)))
+#define SMC_BWR_VLLSCTRL_VLLSM(base, value) (SMC_WR_VLLSCTRL_VLLSM(base, value))
+/*@}*/
+
+/*!
+ * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
+ *
+ * Controls whether the POR detect circuit (for brown-out detection) is enabled
+ * in VLLS0 mode.
+ *
+ * Values:
+ * - 0b0 - POR detect circuit is enabled in VLLS0.
+ * - 0b1 - POR detect circuit is disabled in VLLS0.
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_VLLSCTRL_PORPO field. */
+#define SMC_RD_VLLSCTRL_PORPO(base) ((SMC_VLLSCTRL_REG(base) & SMC_VLLSCTRL_PORPO_MASK) >> SMC_VLLSCTRL_PORPO_SHIFT)
+#define SMC_BRD_VLLSCTRL_PORPO(base) (BITBAND_ACCESS8(&SMC_VLLSCTRL_REG(base), SMC_VLLSCTRL_PORPO_SHIFT))
+
+/*! @brief Set the PORPO field to a new value. */
+#define SMC_WR_VLLSCTRL_PORPO(base, value) (SMC_RMW_VLLSCTRL(base, SMC_VLLSCTRL_PORPO_MASK, SMC_VLLSCTRL_PORPO(value)))
+#define SMC_BWR_VLLSCTRL_PORPO(base, value) (BITBAND_ACCESS8(&SMC_VLLSCTRL_REG(base), SMC_VLLSCTRL_PORPO_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SMC_PMSTAT - Power Mode Status register
+ ******************************************************************************/
+
+/*!
+ * @brief SMC_PMSTAT - Power Mode Status register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * PMSTAT is a read-only, one-hot register which indicates the current power
+ * mode of the system. This register is reset on Chip POR not VLLS and by reset
+ * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
+ * trigger Chip POR not VLLS. See the Reset section details for more information.
+ */
+/*!
+ * @name Constants and macros for entire SMC_PMSTAT register
+ */
+/*@{*/
+#define SMC_RD_PMSTAT(base)      (SMC_PMSTAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SMC_PMSTAT bitfields
+ */
+
+/*!
+ * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
+ *
+ * When debug is enabled, the PMSTAT will not update to STOP or VLPS
+ */
+/*@{*/
+/*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */
+#define SMC_RD_PMSTAT_PMSTAT(base) ((SMC_PMSTAT_REG(base) & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT)
+#define SMC_BRD_PMSTAT_PMSTAT(base) (SMC_RD_PMSTAT_PMSTAT(base))
+/*@}*/
+
+/*
+ * MK64F12 SPI
+ *
+ * Serial Peripheral Interface
+ *
+ * Registers defined in this header file:
+ * - SPI_MCR - Module Configuration Register
+ * - SPI_TCR - Transfer Count Register
+ * - SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
+ * - SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ * - SPI_SR - Status Register
+ * - SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ * - SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ * - SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ * - SPI_POPR - POP RX FIFO Register
+ * - SPI_TXFR0 - Transmit FIFO Registers
+ * - SPI_TXFR1 - Transmit FIFO Registers
+ * - SPI_TXFR2 - Transmit FIFO Registers
+ * - SPI_TXFR3 - Transmit FIFO Registers
+ * - SPI_RXFR0 - Receive FIFO Registers
+ * - SPI_RXFR1 - Receive FIFO Registers
+ * - SPI_RXFR2 - Receive FIFO Registers
+ * - SPI_RXFR3 - Receive FIFO Registers
+ */
+
+#define SPI_INSTANCE_COUNT (3U) /*!< Number of instances of the SPI module. */
+#define SPI0_IDX (0U) /*!< Instance number for SPI0. */
+#define SPI1_IDX (1U) /*!< Instance number for SPI1. */
+#define SPI2_IDX (2U) /*!< Instance number for SPI2. */
+
+/*******************************************************************************
+ * SPI_MCR - Module Configuration Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_MCR - Module Configuration Register (RW)
+ *
+ * Reset value: 0x00004001U
+ *
+ * Contains bits to configure various attributes associated with the module
+ * operations. The HALT and MDIS bits can be changed at any time, but the effect
+ * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
+ * MCR can be changed, while the module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_MCR register
+ */
+/*@{*/
+#define SPI_RD_MCR(base)         (SPI_MCR_REG(base))
+#define SPI_WR_MCR(base, value)  (SPI_MCR_REG(base) = (value))
+#define SPI_RMW_MCR(base, mask, value) (SPI_WR_MCR(base, (SPI_RD_MCR(base) & ~(mask)) | (value)))
+#define SPI_SET_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) |  (value)))
+#define SPI_CLR_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) & ~(value)))
+#define SPI_TOG_MCR(base, value) (SPI_WR_MCR(base, SPI_RD_MCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_MCR bitfields
+ */
+
+/*!
+ * @name Register SPI_MCR, field HALT[0] (RW)
+ *
+ * The HALT bit starts and stops frame transfers. See Start and Stop of Module
+ * transfers
+ *
+ * Values:
+ * - 0b0 - Start transfers.
+ * - 0b1 - Stop transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_HALT field. */
+#define SPI_RD_MCR_HALT(base) ((SPI_MCR_REG(base) & SPI_MCR_HALT_MASK) >> SPI_MCR_HALT_SHIFT)
+#define SPI_BRD_MCR_HALT(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT))
+
+/*! @brief Set the HALT field to a new value. */
+#define SPI_WR_MCR_HALT(base, value) (SPI_RMW_MCR(base, SPI_MCR_HALT_MASK, SPI_MCR_HALT(value)))
+#define SPI_BWR_MCR_HALT(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
+ *
+ * Controls when the module master samples SIN in Modified Transfer Format. This
+ * field is valid only when CPHA bit in CTARn[CPHA] is 0.
+ *
+ * Values:
+ * - 0b00 - 0 protocol clock cycles between SCK edge and SIN sample
+ * - 0b01 - 1 protocol clock cycle between SCK edge and SIN sample
+ * - 0b10 - 2 protocol clock cycles between SCK edge and SIN sample
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_SMPL_PT field. */
+#define SPI_RD_MCR_SMPL_PT(base) ((SPI_MCR_REG(base) & SPI_MCR_SMPL_PT_MASK) >> SPI_MCR_SMPL_PT_SHIFT)
+#define SPI_BRD_MCR_SMPL_PT(base) (SPI_RD_MCR_SMPL_PT(base))
+
+/*! @brief Set the SMPL_PT field to a new value. */
+#define SPI_WR_MCR_SMPL_PT(base, value) (SPI_RMW_MCR(base, SPI_MCR_SMPL_PT_MASK, SPI_MCR_SMPL_PT(value)))
+#define SPI_BWR_MCR_SMPL_PT(base, value) (SPI_WR_MCR_SMPL_PT(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
+ *
+ * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
+ * CLR_RXF bit is always read as zero.
+ *
+ * Values:
+ * - 0b0 - Do not clear the RX FIFO counter.
+ * - 0b1 - Clear the RX FIFO counter.
+ */
+/*@{*/
+/*! @brief Set the CLR_RXF field to a new value. */
+#define SPI_WR_MCR_CLR_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_RXF_MASK, SPI_MCR_CLR_RXF(value)))
+#define SPI_BWR_MCR_CLR_RXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CLR_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
+ *
+ * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
+ * CLR_TXF bit is always read as zero.
+ *
+ * Values:
+ * - 0b0 - Do not clear the TX FIFO counter.
+ * - 0b1 - Clear the TX FIFO counter.
+ */
+/*@{*/
+/*! @brief Set the CLR_TXF field to a new value. */
+#define SPI_WR_MCR_CLR_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_TXF_MASK, SPI_MCR_CLR_TXF(value)))
+#define SPI_BWR_MCR_CLR_TXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CLR_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DIS_RXF[12] (RW)
+ *
+ * When the RX FIFO is disabled, the receive part of the module operates as a
+ * simplified double-buffered SPI. This bit can only be written when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0b0 - RX FIFO is enabled.
+ * - 0b1 - RX FIFO is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DIS_RXF field. */
+#define SPI_RD_MCR_DIS_RXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_RXF_MASK) >> SPI_MCR_DIS_RXF_SHIFT)
+#define SPI_BRD_MCR_DIS_RXF(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT))
+
+/*! @brief Set the DIS_RXF field to a new value. */
+#define SPI_WR_MCR_DIS_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_RXF_MASK, SPI_MCR_DIS_RXF(value)))
+#define SPI_BWR_MCR_DIS_RXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DIS_TXF[13] (RW)
+ *
+ * When the TX FIFO is disabled, the transmit part of the module operates as a
+ * simplified double-buffered SPI. This bit can be written only when the MDIS bit
+ * is cleared.
+ *
+ * Values:
+ * - 0b0 - TX FIFO is enabled.
+ * - 0b1 - TX FIFO is disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DIS_TXF field. */
+#define SPI_RD_MCR_DIS_TXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_TXF_MASK) >> SPI_MCR_DIS_TXF_SHIFT)
+#define SPI_BRD_MCR_DIS_TXF(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT))
+
+/*! @brief Set the DIS_TXF field to a new value. */
+#define SPI_WR_MCR_DIS_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_TXF_MASK, SPI_MCR_DIS_TXF(value)))
+#define SPI_BWR_MCR_DIS_TXF(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MDIS[14] (RW)
+ *
+ * Allows the clock to be stopped to the non-memory mapped logic in the module
+ * effectively putting it in a software-controlled power-saving state. The reset
+ * value of the MDIS bit is parameterized, with a default reset value of 0. When
+ * the module is used in Slave Mode, we recommend leaving this bit 0, because a
+ * slave doesn't have control over master transactions.
+ *
+ * Values:
+ * - 0b0 - Enables the module clocks.
+ * - 0b1 - Allows external logic to disable the module clocks.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MDIS field. */
+#define SPI_RD_MCR_MDIS(base) ((SPI_MCR_REG(base) & SPI_MCR_MDIS_MASK) >> SPI_MCR_MDIS_SHIFT)
+#define SPI_BRD_MCR_MDIS(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT))
+
+/*! @brief Set the MDIS field to a new value. */
+#define SPI_WR_MCR_MDIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_MDIS_MASK, SPI_MCR_MDIS(value)))
+#define SPI_BWR_MCR_MDIS(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DOZE[15] (RW)
+ *
+ * Provides support for an externally controlled Doze mode power-saving
+ * mechanism.
+ *
+ * Values:
+ * - 0b0 - Doze mode has no effect on the module.
+ * - 0b1 - Doze mode disables the module.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DOZE field. */
+#define SPI_RD_MCR_DOZE(base) ((SPI_MCR_REG(base) & SPI_MCR_DOZE_MASK) >> SPI_MCR_DOZE_SHIFT)
+#define SPI_BRD_MCR_DOZE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT))
+
+/*! @brief Set the DOZE field to a new value. */
+#define SPI_WR_MCR_DOZE(base, value) (SPI_RMW_MCR(base, SPI_MCR_DOZE_MASK, SPI_MCR_DOZE(value)))
+#define SPI_BWR_MCR_DOZE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field PCSIS[21:16] (RW)
+ *
+ * Determines the inactive state of PCSx.
+ *
+ * Values:
+ * - 0b000000 - The inactive state of PCSx is low.
+ * - 0b000001 - The inactive state of PCSx is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_PCSIS field. */
+#define SPI_RD_MCR_PCSIS(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSIS_MASK) >> SPI_MCR_PCSIS_SHIFT)
+#define SPI_BRD_MCR_PCSIS(base) (SPI_RD_MCR_PCSIS(base))
+
+/*! @brief Set the PCSIS field to a new value. */
+#define SPI_WR_MCR_PCSIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSIS_MASK, SPI_MCR_PCSIS(value)))
+#define SPI_BWR_MCR_PCSIS(base, value) (SPI_WR_MCR_PCSIS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field ROOE[24] (RW)
+ *
+ * In the RX FIFO overflow condition, configures the module to ignore the
+ * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
+ * is received, the data from the transfer, generating the overflow, is ignored
+ * or shifted into the shift register.
+ *
+ * Values:
+ * - 0b0 - Incoming data is ignored.
+ * - 0b1 - Incoming data is shifted into the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_ROOE field. */
+#define SPI_RD_MCR_ROOE(base) ((SPI_MCR_REG(base) & SPI_MCR_ROOE_MASK) >> SPI_MCR_ROOE_SHIFT)
+#define SPI_BRD_MCR_ROOE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT))
+
+/*! @brief Set the ROOE field to a new value. */
+#define SPI_WR_MCR_ROOE(base, value) (SPI_RMW_MCR(base, SPI_MCR_ROOE_MASK, SPI_MCR_ROOE(value)))
+#define SPI_BWR_MCR_ROOE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field PCSSE[25] (RW)
+ *
+ * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
+ *
+ * Values:
+ * - 0b0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
+ * - 0b1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_PCSSE field. */
+#define SPI_RD_MCR_PCSSE(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSSE_MASK) >> SPI_MCR_PCSSE_SHIFT)
+#define SPI_BRD_MCR_PCSSE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_PCSSE_SHIFT))
+
+/*! @brief Set the PCSSE field to a new value. */
+#define SPI_WR_MCR_PCSSE(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSSE_MASK, SPI_MCR_PCSSE(value)))
+#define SPI_BWR_MCR_PCSSE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_PCSSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MTFE[26] (RW)
+ *
+ * Enables a modified transfer format to be used.
+ *
+ * Values:
+ * - 0b0 - Modified SPI transfer format disabled.
+ * - 0b1 - Modified SPI transfer format enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MTFE field. */
+#define SPI_RD_MCR_MTFE(base) ((SPI_MCR_REG(base) & SPI_MCR_MTFE_MASK) >> SPI_MCR_MTFE_SHIFT)
+#define SPI_BRD_MCR_MTFE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT))
+
+/*! @brief Set the MTFE field to a new value. */
+#define SPI_WR_MCR_MTFE(base, value) (SPI_RMW_MCR(base, SPI_MCR_MTFE_MASK, SPI_MCR_MTFE(value)))
+#define SPI_BWR_MCR_MTFE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field FRZ[27] (RW)
+ *
+ * Enables transfers to be stopped on the next frame boundary when the device
+ * enters Debug mode.
+ *
+ * Values:
+ * - 0b0 - Do not halt serial transfers in Debug mode.
+ * - 0b1 - Halt serial transfers in Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_FRZ field. */
+#define SPI_RD_MCR_FRZ(base) ((SPI_MCR_REG(base) & SPI_MCR_FRZ_MASK) >> SPI_MCR_FRZ_SHIFT)
+#define SPI_BRD_MCR_FRZ(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT))
+
+/*! @brief Set the FRZ field to a new value. */
+#define SPI_WR_MCR_FRZ(base, value) (SPI_RMW_MCR(base, SPI_MCR_FRZ_MASK, SPI_MCR_FRZ(value)))
+#define SPI_BWR_MCR_FRZ(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field DCONF[29:28] (RO)
+ *
+ * Selects among the different configurations of the module.
+ *
+ * Values:
+ * - 0b00 - SPI
+ * - 0b01 - Reserved
+ * - 0b10 - Reserved
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_DCONF field. */
+#define SPI_RD_MCR_DCONF(base) ((SPI_MCR_REG(base) & SPI_MCR_DCONF_MASK) >> SPI_MCR_DCONF_SHIFT)
+#define SPI_BRD_MCR_DCONF(base) (SPI_RD_MCR_DCONF(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
+ *
+ * Enables the Serial Communication Clock (SCK) to run continuously.
+ *
+ * Values:
+ * - 0b0 - Continuous SCK disabled.
+ * - 0b1 - Continuous SCK enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */
+#define SPI_RD_MCR_CONT_SCKE(base) ((SPI_MCR_REG(base) & SPI_MCR_CONT_SCKE_MASK) >> SPI_MCR_CONT_SCKE_SHIFT)
+#define SPI_BRD_MCR_CONT_SCKE(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT))
+
+/*! @brief Set the CONT_SCKE field to a new value. */
+#define SPI_WR_MCR_CONT_SCKE(base, value) (SPI_RMW_MCR(base, SPI_MCR_CONT_SCKE_MASK, SPI_MCR_CONT_SCKE(value)))
+#define SPI_BWR_MCR_CONT_SCKE(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_MCR, field MSTR[31] (RW)
+ *
+ * Enables either Master mode (if supported) or Slave mode (if supported)
+ * operation.
+ *
+ * Values:
+ * - 0b0 - Enables Slave mode
+ * - 0b1 - Enables Master mode
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_MCR_MSTR field. */
+#define SPI_RD_MCR_MSTR(base) ((SPI_MCR_REG(base) & SPI_MCR_MSTR_MASK) >> SPI_MCR_MSTR_SHIFT)
+#define SPI_BRD_MCR_MSTR(base) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT))
+
+/*! @brief Set the MSTR field to a new value. */
+#define SPI_WR_MCR_MSTR(base, value) (SPI_RMW_MCR(base, SPI_MCR_MSTR_MASK, SPI_MCR_MSTR(value)))
+#define SPI_BWR_MCR_MSTR(base, value) (BITBAND_ACCESS32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TCR - Transfer Count Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TCR - Transfer Count Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TCR contains a counter that indicates the number of SPI transfers made. The
+ * transfer counter is intended to assist in queue management. Do not write the
+ * TCR when the module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TCR register
+ */
+/*@{*/
+#define SPI_RD_TCR(base)         (SPI_TCR_REG(base))
+#define SPI_WR_TCR(base, value)  (SPI_TCR_REG(base) = (value))
+#define SPI_RMW_TCR(base, mask, value) (SPI_WR_TCR(base, (SPI_RD_TCR(base) & ~(mask)) | (value)))
+#define SPI_SET_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) |  (value)))
+#define SPI_CLR_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) & ~(value)))
+#define SPI_TOG_TCR(base, value) (SPI_WR_TCR(base, SPI_RD_TCR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TCR bitfields
+ */
+
+/*!
+ * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
+ *
+ * Counts the number of SPI transfers the module makes. The SPI_TCNT field
+ * increments every time the last bit of an SPI frame is transmitted. A value written
+ * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
+ * the beginning of the frame when the CTCNT field is set in the executing SPI
+ * command. The Transfer Counter wraps around; incrementing the counter past 65535
+ * resets the counter to zero.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */
+#define SPI_RD_TCR_SPI_TCNT(base) ((SPI_TCR_REG(base) & SPI_TCR_SPI_TCNT_MASK) >> SPI_TCR_SPI_TCNT_SHIFT)
+#define SPI_BRD_TCR_SPI_TCNT(base) (SPI_RD_TCR_SPI_TCNT(base))
+
+/*! @brief Set the SPI_TCNT field to a new value. */
+#define SPI_WR_TCR_SPI_TCNT(base, value) (SPI_RMW_TCR(base, SPI_TCR_SPI_TCNT_MASK, SPI_TCR_SPI_TCNT(value)))
+#define SPI_BWR_TCR_SPI_TCNT(base, value) (SPI_WR_TCR_SPI_TCNT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * When the module is configured as an SPI bus slave, the CTAR0 register is used.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CTAR_SLAVE register
+ */
+/*@{*/
+#define SPI_RD_CTAR_SLAVE(base, index) (SPI_CTAR_SLAVE_REG(base, index))
+#define SPI_WR_CTAR_SLAVE(base, index, value) (SPI_CTAR_SLAVE_REG(base, index) = (value))
+#define SPI_RMW_CTAR_SLAVE(base, index, mask, value) (SPI_WR_CTAR_SLAVE(base, index, (SPI_RD_CTAR_SLAVE(base, index) & ~(mask)) | (value)))
+#define SPI_SET_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) |  (value)))
+#define SPI_CLR_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) & ~(value)))
+#define SPI_TOG_CTAR_SLAVE(base, index, value) (SPI_WR_CTAR_SLAVE(base, index, SPI_RD_CTAR_SLAVE(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CTAR_SLAVE bitfields
+ */
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0b0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 0b1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_CPHA field. */
+#define SPI_RD_CTAR_SLAVE_CPHA(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPHA_MASK) >> SPI_CTAR_SLAVE_CPHA_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_CPHA(base, index) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_CTAR_SLAVE_CPHA(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPHA_MASK, SPI_CTAR_SLAVE_CPHA(value)))
+#define SPI_BWR_CTAR_SLAVE_CPHA(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0b0 - The inactive state value of SCK is low.
+ * - 0b1 - The inactive state value of SCK is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_CPOL field. */
+#define SPI_RD_CTAR_SLAVE_CPOL(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPOL_MASK) >> SPI_CTAR_SLAVE_CPOL_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_CPOL(base, index) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_CTAR_SLAVE_CPOL(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPOL_MASK, SPI_CTAR_SLAVE_CPOL(value)))
+#define SPI_BWR_CTAR_SLAVE_CPOL(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR_SLAVE, field FMSZ[31:27] (RW)
+ *
+ * The number of bits transfered per frame is equal to the FMSZ field value plus
+ * 1. Note that the minimum valid value of frame size is 4.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_SLAVE_FMSZ field. */
+#define SPI_RD_CTAR_SLAVE_FMSZ(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT)
+#define SPI_BRD_CTAR_SLAVE_FMSZ(base, index) (SPI_RD_CTAR_SLAVE_FMSZ(base, index))
+
+/*! @brief Set the FMSZ field to a new value. */
+#define SPI_WR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_FMSZ_MASK, SPI_CTAR_SLAVE_FMSZ(value)))
+#define SPI_BWR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_WR_CTAR_SLAVE_FMSZ(base, index, value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode) (RW)
+ *
+ * Reset value: 0x78000000U
+ *
+ * CTAR registers are used to define different transfer attributes. Do not write
+ * to the CTAR registers while the module is in the Running state. In Master
+ * mode, the CTAR registers define combinations of transfer attributes such as frame
+ * size, clock phase and polarity, data bit ordering, baud rate, and various
+ * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
+ * slave transfer attributes. When the module is configured as an SPI master, the
+ * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
+ * registers is used. When the module is configured as an SPI bus slave, it uses
+ * the CTAR0 register.
+ */
+/*!
+ * @name Constants and macros for entire SPI_CTAR register
+ */
+/*@{*/
+#define SPI_RD_CTAR(base, index) (SPI_CTAR_REG(base, index))
+#define SPI_WR_CTAR(base, index, value) (SPI_CTAR_REG(base, index) = (value))
+#define SPI_RMW_CTAR(base, index, mask, value) (SPI_WR_CTAR(base, index, (SPI_RD_CTAR(base, index) & ~(mask)) | (value)))
+#define SPI_SET_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) |  (value)))
+#define SPI_CLR_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) & ~(value)))
+#define SPI_TOG_CTAR(base, index, value) (SPI_WR_CTAR(base, index, SPI_RD_CTAR(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_CTAR bitfields
+ */
+
+/*!
+ * @name Register SPI_CTAR, field BR[3:0] (RW)
+ *
+ * Selects the scaler value for the baud rate. This field is used only in master
+ * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
+ * generate the frequency of the SCK. The baud rate is computed according to the
+ * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
+ * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
+ * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
+ * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_BR field. */
+#define SPI_RD_CTAR_BR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_BR_MASK) >> SPI_CTAR_BR_SHIFT)
+#define SPI_BRD_CTAR_BR(base, index) (SPI_RD_CTAR_BR(base, index))
+
+/*! @brief Set the BR field to a new value. */
+#define SPI_WR_CTAR_BR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_BR_MASK, SPI_CTAR_BR(value)))
+#define SPI_BWR_CTAR_BR(base, index, value) (SPI_WR_CTAR_BR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field DT[7:4] (RW)
+ *
+ * Selects the Delay after Transfer Scaler. This field is used only in master
+ * mode. The Delay after Transfer is the time between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the next
+ * frame. In the Continuous Serial Communications Clock operation, the DT value
+ * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
+ * protocol clock period, and it is computed according to the following
+ * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
+ * field description for scaler values.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_DT field. */
+#define SPI_RD_CTAR_DT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DT_MASK) >> SPI_CTAR_DT_SHIFT)
+#define SPI_BRD_CTAR_DT(base, index) (SPI_RD_CTAR_DT(base, index))
+
+/*! @brief Set the DT field to a new value. */
+#define SPI_WR_CTAR_DT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DT_MASK, SPI_CTAR_DT(value)))
+#define SPI_BWR_CTAR_DT(base, index, value) (SPI_WR_CTAR_DT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field ASC[11:8] (RW)
+ *
+ * Selects the scaler value for the After SCK Delay. This field is used only in
+ * master mode. The After SCK Delay is the delay between the last edge of SCK and
+ * the negation of PCS. The delay is a multiple of the protocol clock period,
+ * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
+ * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
+ * scaler values. Refer After SCK Delay (tASC ) for more details.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_ASC field. */
+#define SPI_RD_CTAR_ASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_ASC_MASK) >> SPI_CTAR_ASC_SHIFT)
+#define SPI_BRD_CTAR_ASC(base, index) (SPI_RD_CTAR_ASC(base, index))
+
+/*! @brief Set the ASC field to a new value. */
+#define SPI_WR_CTAR_ASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_ASC_MASK, SPI_CTAR_ASC(value)))
+#define SPI_BWR_CTAR_ASC(base, index, value) (SPI_WR_CTAR_ASC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CSSCK[15:12] (RW)
+ *
+ * Selects the scaler value for the PCS to SCK delay. This field is used only in
+ * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
+ * and the first edge of the SCK. The delay is a multiple of the protocol clock
+ * period, and it is computed according to the following equation: t CSC = (1/fP )
+ * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
+ * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
+ * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
+ * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
+ * details.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CSSCK field. */
+#define SPI_RD_CTAR_CSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CSSCK_MASK) >> SPI_CTAR_CSSCK_SHIFT)
+#define SPI_BRD_CTAR_CSSCK(base, index) (SPI_RD_CTAR_CSSCK(base, index))
+
+/*! @brief Set the CSSCK field to a new value. */
+#define SPI_WR_CTAR_CSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CSSCK_MASK, SPI_CTAR_CSSCK(value)))
+#define SPI_BWR_CTAR_CSSCK(base, index, value) (SPI_WR_CTAR_CSSCK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PBR[17:16] (RW)
+ *
+ * Selects the prescaler value for the baud rate. This field is used only in
+ * master mode. The baud rate is the frequency of the SCK. The protocol clock is
+ * divided by the prescaler value before the baud rate selection takes place. See
+ * the BR field description for details on how to compute the baud rate.
+ *
+ * Values:
+ * - 0b00 - Baud Rate Prescaler value is 2.
+ * - 0b01 - Baud Rate Prescaler value is 3.
+ * - 0b10 - Baud Rate Prescaler value is 5.
+ * - 0b11 - Baud Rate Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PBR field. */
+#define SPI_RD_CTAR_PBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PBR_MASK) >> SPI_CTAR_PBR_SHIFT)
+#define SPI_BRD_CTAR_PBR(base, index) (SPI_RD_CTAR_PBR(base, index))
+
+/*! @brief Set the PBR field to a new value. */
+#define SPI_WR_CTAR_PBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PBR_MASK, SPI_CTAR_PBR(value)))
+#define SPI_BWR_CTAR_PBR(base, index, value) (SPI_WR_CTAR_PBR(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PDT[19:18] (RW)
+ *
+ * Selects the prescaler value for the delay between the negation of the PCS
+ * signal at the end of a frame and the assertion of PCS at the beginning of the
+ * next frame. The PDT field is only used in master mode. See the DT field
+ * description for details on how to compute the Delay after Transfer. Refer Delay after
+ * Transfer (tDT ) for more details.
+ *
+ * Values:
+ * - 0b00 - Delay after Transfer Prescaler value is 1.
+ * - 0b01 - Delay after Transfer Prescaler value is 3.
+ * - 0b10 - Delay after Transfer Prescaler value is 5.
+ * - 0b11 - Delay after Transfer Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PDT field. */
+#define SPI_RD_CTAR_PDT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PDT_MASK) >> SPI_CTAR_PDT_SHIFT)
+#define SPI_BRD_CTAR_PDT(base, index) (SPI_RD_CTAR_PDT(base, index))
+
+/*! @brief Set the PDT field to a new value. */
+#define SPI_WR_CTAR_PDT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PDT_MASK, SPI_CTAR_PDT(value)))
+#define SPI_BWR_CTAR_PDT(base, index, value) (SPI_WR_CTAR_PDT(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PASC[21:20] (RW)
+ *
+ * Selects the prescaler value for the delay between the last edge of SCK and
+ * the negation of PCS. See the ASC field description for information on how to
+ * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
+ *
+ * Values:
+ * - 0b00 - Delay after Transfer Prescaler value is 1.
+ * - 0b01 - Delay after Transfer Prescaler value is 3.
+ * - 0b10 - Delay after Transfer Prescaler value is 5.
+ * - 0b11 - Delay after Transfer Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PASC field. */
+#define SPI_RD_CTAR_PASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PASC_MASK) >> SPI_CTAR_PASC_SHIFT)
+#define SPI_BRD_CTAR_PASC(base, index) (SPI_RD_CTAR_PASC(base, index))
+
+/*! @brief Set the PASC field to a new value. */
+#define SPI_WR_CTAR_PASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PASC_MASK, SPI_CTAR_PASC(value)))
+#define SPI_BWR_CTAR_PASC(base, index, value) (SPI_WR_CTAR_PASC(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field PCSSCK[23:22] (RW)
+ *
+ * Selects the prescaler value for the delay between assertion of PCS and the
+ * first edge of the SCK. See the CSSCK field description for information on how to
+ * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
+ *
+ * Values:
+ * - 0b00 - PCS to SCK Prescaler value is 1.
+ * - 0b01 - PCS to SCK Prescaler value is 3.
+ * - 0b10 - PCS to SCK Prescaler value is 5.
+ * - 0b11 - PCS to SCK Prescaler value is 7.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_PCSSCK field. */
+#define SPI_RD_CTAR_PCSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PCSSCK_MASK) >> SPI_CTAR_PCSSCK_SHIFT)
+#define SPI_BRD_CTAR_PCSSCK(base, index) (SPI_RD_CTAR_PCSSCK(base, index))
+
+/*! @brief Set the PCSSCK field to a new value. */
+#define SPI_WR_CTAR_PCSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PCSSCK_MASK, SPI_CTAR_PCSSCK(value)))
+#define SPI_BWR_CTAR_PCSSCK(base, index, value) (SPI_WR_CTAR_PCSSCK(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field LSBFE[24] (RW)
+ *
+ * Specifies whether the LSB or MSB of the frame is transferred first.
+ *
+ * Values:
+ * - 0b0 - Data is transferred MSB first.
+ * - 0b1 - Data is transferred LSB first.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_LSBFE field. */
+#define SPI_RD_CTAR_LSBFE(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_LSBFE_MASK) >> SPI_CTAR_LSBFE_SHIFT)
+#define SPI_BRD_CTAR_LSBFE(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT))
+
+/*! @brief Set the LSBFE field to a new value. */
+#define SPI_WR_CTAR_LSBFE(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_LSBFE_MASK, SPI_CTAR_LSBFE(value)))
+#define SPI_BWR_CTAR_LSBFE(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CPHA[25] (RW)
+ *
+ * Selects which edge of SCK causes data to change and which edge causes data to
+ * be captured. This bit is used in both master and slave mode. For successful
+ * communication between serial devices, the devices must have identical clock
+ * phase settings. In Continuous SCK mode, the bit value is ignored and the
+ * transfers are done as if the CPHA bit is set to 1.
+ *
+ * Values:
+ * - 0b0 - Data is captured on the leading edge of SCK and changed on the
+ *     following edge.
+ * - 0b1 - Data is changed on the leading edge of SCK and captured on the
+ *     following edge.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CPHA field. */
+#define SPI_RD_CTAR_CPHA(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPHA_MASK) >> SPI_CTAR_CPHA_SHIFT)
+#define SPI_BRD_CTAR_CPHA(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT))
+
+/*! @brief Set the CPHA field to a new value. */
+#define SPI_WR_CTAR_CPHA(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPHA_MASK, SPI_CTAR_CPHA(value)))
+#define SPI_BWR_CTAR_CPHA(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field CPOL[26] (RW)
+ *
+ * Selects the inactive state of the Serial Communications Clock (SCK). This bit
+ * is used in both master and slave mode. For successful communication between
+ * serial devices, the devices must have identical clock polarities. When the
+ * Continuous Selection Format is selected, switching between clock polarities
+ * without stopping the module can cause errors in the transfer due to the peripheral
+ * device interpreting the switch of clock polarity as a valid clock edge. In case
+ * of continous sck mode, when the module goes in low power mode(disabled),
+ * inactive state of sck is not guaranted.
+ *
+ * Values:
+ * - 0b0 - The inactive state value of SCK is low.
+ * - 0b1 - The inactive state value of SCK is high.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_CPOL field. */
+#define SPI_RD_CTAR_CPOL(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPOL_MASK) >> SPI_CTAR_CPOL_SHIFT)
+#define SPI_BRD_CTAR_CPOL(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT))
+
+/*! @brief Set the CPOL field to a new value. */
+#define SPI_WR_CTAR_CPOL(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPOL_MASK, SPI_CTAR_CPOL(value)))
+#define SPI_BWR_CTAR_CPOL(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field FMSZ[30:27] (RW)
+ *
+ * The number of bits transferred per frame is equal to the FMSZ value plus 1.
+ * Regardless of the transmission mode, the minimum valid frame size value is 4.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_FMSZ field. */
+#define SPI_RD_CTAR_FMSZ(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT)
+#define SPI_BRD_CTAR_FMSZ(base, index) (SPI_RD_CTAR_FMSZ(base, index))
+
+/*! @brief Set the FMSZ field to a new value. */
+#define SPI_WR_CTAR_FMSZ(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_FMSZ_MASK, SPI_CTAR_FMSZ(value)))
+#define SPI_BWR_CTAR_FMSZ(base, index, value) (SPI_WR_CTAR_FMSZ(base, index, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_CTAR, field DBR[31] (RW)
+ *
+ * Doubles the effective baud rate of the Serial Communications Clock (SCK).
+ * This field is used only in master mode. It effectively halves the Baud Rate
+ * division ratio, supporting faster frequencies, and odd division ratios for the
+ * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
+ * Serial Communications Clock (SCK) depends on the value in the Baud Rate
+ * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
+ * description for details on how to compute the baud rate. SPI SCK Duty Cycle
+ * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
+ * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
+ *
+ * Values:
+ * - 0b0 - The baud rate is computed normally with a 50/50 duty cycle.
+ * - 0b1 - The baud rate is doubled with the duty cycle depending on the Baud
+ *     Rate Prescaler.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_CTAR_DBR field. */
+#define SPI_RD_CTAR_DBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DBR_MASK) >> SPI_CTAR_DBR_SHIFT)
+#define SPI_BRD_CTAR_DBR(base, index) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT))
+
+/*! @brief Set the DBR field to a new value. */
+#define SPI_WR_CTAR_DBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DBR_MASK, SPI_CTAR_DBR(value)))
+#define SPI_BWR_CTAR_DBR(base, index, value) (BITBAND_ACCESS32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_SR - Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_SR - Status Register (RW)
+ *
+ * Reset value: 0x02000000U
+ *
+ * SR contains status and flag bits. The bits reflect the status of the module
+ * and indicate the occurrence of events that can generate interrupt or DMA
+ * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
+ * to a flag bit has no effect. This register may not be writable in Module
+ * Disable mode due to the use of power saving mechanisms.
+ */
+/*!
+ * @name Constants and macros for entire SPI_SR register
+ */
+/*@{*/
+#define SPI_RD_SR(base)          (SPI_SR_REG(base))
+#define SPI_WR_SR(base, value)   (SPI_SR_REG(base) = (value))
+#define SPI_RMW_SR(base, mask, value) (SPI_WR_SR(base, (SPI_RD_SR(base) & ~(mask)) | (value)))
+#define SPI_SET_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) |  (value)))
+#define SPI_CLR_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) & ~(value)))
+#define SPI_TOG_SR(base, value)  (SPI_WR_SR(base, SPI_RD_SR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_SR bitfields
+ */
+
+/*!
+ * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
+ *
+ * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
+ * The POPNXTPTR is updated when the POPR is read.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_POPNXTPTR field. */
+#define SPI_RD_SR_POPNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_POPNXTPTR_MASK) >> SPI_SR_POPNXTPTR_SHIFT)
+#define SPI_BRD_SR_POPNXTPTR(base) (SPI_RD_SR_POPNXTPTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RXCTR[7:4] (RO)
+ *
+ * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
+ * every time the POPR is read. The RXCTR is incremented every time data is
+ * transferred from the shift register to the RX FIFO.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RXCTR field. */
+#define SPI_RD_SR_RXCTR(base) ((SPI_SR_REG(base) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT)
+#define SPI_BRD_SR_RXCTR(base) (SPI_RD_SR_RXCTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
+ *
+ * Indicates which TX FIFO entry is transmitted during the next transfer. The
+ * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
+ * the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXNXTPTR field. */
+#define SPI_RD_SR_TXNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_TXNXTPTR_MASK) >> SPI_SR_TXNXTPTR_SHIFT)
+#define SPI_BRD_SR_TXNXTPTR(base) (SPI_RD_SR_TXNXTPTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXCTR[15:12] (RO)
+ *
+ * Indicates the number of valid entries in the TX FIFO. The TXCTR is
+ * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
+ * command is executed and the SPI data is transferred to the shift register.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXCTR field. */
+#define SPI_RD_SR_TXCTR(base) ((SPI_SR_REG(base) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT)
+#define SPI_BRD_SR_TXCTR(base) (SPI_RD_SR_TXCTR(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RFDF[17] (W1C)
+ *
+ * Provides a method for the module to request that entries be removed from the
+ * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller when
+ * the RX FIFO is empty.
+ *
+ * Values:
+ * - 0b0 - RX FIFO is empty.
+ * - 0b1 - RX FIFO is not empty.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RFDF field. */
+#define SPI_RD_SR_RFDF(base) ((SPI_SR_REG(base) & SPI_SR_RFDF_MASK) >> SPI_SR_RFDF_SHIFT)
+#define SPI_BRD_SR_RFDF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT))
+
+/*! @brief Set the RFDF field to a new value. */
+#define SPI_WR_SR_RFDF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFDF(value)))
+#define SPI_BWR_SR_RFDF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field RFOF[19] (W1C)
+ *
+ * Indicates an overflow condition in the RX FIFO. The field is set when the RX
+ * FIFO and shift register are full and a transfer is initiated. The bit remains
+ * set until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - No Rx FIFO overflow.
+ * - 0b1 - Rx FIFO overflow has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_RFOF field. */
+#define SPI_RD_SR_RFOF(base) ((SPI_SR_REG(base) & SPI_SR_RFOF_MASK) >> SPI_SR_RFOF_SHIFT)
+#define SPI_BRD_SR_RFOF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT))
+
+/*! @brief Set the RFOF field to a new value. */
+#define SPI_WR_SR_RFOF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFOF(value)))
+#define SPI_BWR_SR_RFOF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TFFF[25] (W1C)
+ *
+ * Provides a method for the module to request more entries to be added to the
+ * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
+ * cleared by writing 1 to it or by acknowledgement from the DMA controller to
+ * the TX FIFO full request.
+ *
+ * Values:
+ * - 0b0 - TX FIFO is full.
+ * - 0b1 - TX FIFO is not full.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TFFF field. */
+#define SPI_RD_SR_TFFF(base) ((SPI_SR_REG(base) & SPI_SR_TFFF_MASK) >> SPI_SR_TFFF_SHIFT)
+#define SPI_BRD_SR_TFFF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT))
+
+/*! @brief Set the TFFF field to a new value. */
+#define SPI_WR_SR_TFFF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFFF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFFF(value)))
+#define SPI_BWR_SR_TFFF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TFUF[27] (W1C)
+ *
+ * Indicates an underflow condition in the TX FIFO. The transmit underflow
+ * condition is detected only for SPI blocks operating in Slave mode and SPI
+ * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
+ * is empty and an external SPI master initiates a transfer. The TFUF bit remains
+ * set until cleared by writing 1 to it.
+ *
+ * Values:
+ * - 0b0 - No TX FIFO underflow.
+ * - 0b1 - TX FIFO underflow has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TFUF field. */
+#define SPI_RD_SR_TFUF(base) ((SPI_SR_REG(base) & SPI_SR_TFUF_MASK) >> SPI_SR_TFUF_SHIFT)
+#define SPI_BRD_SR_TFUF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT))
+
+/*! @brief Set the TFUF field to a new value. */
+#define SPI_WR_SR_TFUF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFUF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFUF(value)))
+#define SPI_BWR_SR_TFUF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field EOQF[28] (W1C)
+ *
+ * Indicates that the last entry in a queue has been transmitted when the module
+ * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
+ * set in the command halfword and the end of the transfer is reached. The EOQF
+ * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
+ * the TXRXS bit is automatically cleared.
+ *
+ * Values:
+ * - 0b0 - EOQ is not set in the executing command.
+ * - 0b1 - EOQ is set in the executing SPI command.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_EOQF field. */
+#define SPI_RD_SR_EOQF(base) ((SPI_SR_REG(base) & SPI_SR_EOQF_MASK) >> SPI_SR_EOQF_SHIFT)
+#define SPI_BRD_SR_EOQF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT))
+
+/*! @brief Set the EOQF field to a new value. */
+#define SPI_WR_SR_EOQF(base, value) (SPI_RMW_SR(base, (SPI_SR_EOQF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_EOQF(value)))
+#define SPI_BWR_SR_EOQF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TXRXS[30] (W1C)
+ *
+ * Reflects the run status of the module.
+ *
+ * Values:
+ * - 0b0 - Transmit and receive operations are disabled (The module is in
+ *     Stopped state).
+ * - 0b1 - Transmit and receive operations are enabled (The module is in Running
+ *     state).
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TXRXS field. */
+#define SPI_RD_SR_TXRXS(base) ((SPI_SR_REG(base) & SPI_SR_TXRXS_MASK) >> SPI_SR_TXRXS_SHIFT)
+#define SPI_BRD_SR_TXRXS(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT))
+
+/*! @brief Set the TXRXS field to a new value. */
+#define SPI_WR_SR_TXRXS(base, value) (SPI_RMW_SR(base, (SPI_SR_TXRXS_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TCF_MASK), SPI_SR_TXRXS(value)))
+#define SPI_BWR_SR_TXRXS(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_SR, field TCF[31] (W1C)
+ *
+ * Indicates that all bits in a frame have been shifted out. TCF remains set
+ * until it is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - Transfer not complete.
+ * - 0b1 - Transfer complete.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_SR_TCF field. */
+#define SPI_RD_SR_TCF(base)  ((SPI_SR_REG(base) & SPI_SR_TCF_MASK) >> SPI_SR_TCF_SHIFT)
+#define SPI_BRD_SR_TCF(base) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT))
+
+/*! @brief Set the TCF field to a new value. */
+#define SPI_WR_SR_TCF(base, value) (SPI_RMW_SR(base, (SPI_SR_TCF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK), SPI_SR_TCF(value)))
+#define SPI_BWR_SR_TCF(base, value) (BITBAND_ACCESS32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RSER - DMA/Interrupt Request Select and Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RSER controls DMA and interrupt requests. Do not write to the RSER while the
+ * module is in the Running state.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RSER register
+ */
+/*@{*/
+#define SPI_RD_RSER(base)        (SPI_RSER_REG(base))
+#define SPI_WR_RSER(base, value) (SPI_RSER_REG(base) = (value))
+#define SPI_RMW_RSER(base, mask, value) (SPI_WR_RSER(base, (SPI_RD_RSER(base) & ~(mask)) | (value)))
+#define SPI_SET_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) |  (value)))
+#define SPI_CLR_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) & ~(value)))
+#define SPI_TOG_RSER(base, value) (SPI_WR_RSER(base, SPI_RD_RSER(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_RSER bitfields
+ */
+
+/*!
+ * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When the
+ * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
+ * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - Interrupt request.
+ * - 0b1 - DMA request.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */
+#define SPI_RD_RSER_RFDF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_DIRS_MASK) >> SPI_RSER_RFDF_DIRS_SHIFT)
+#define SPI_BRD_RSER_RFDF_DIRS(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT))
+
+/*! @brief Set the RFDF_DIRS field to a new value. */
+#define SPI_WR_RSER_RFDF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_DIRS_MASK, SPI_RSER_RFDF_DIRS(value)))
+#define SPI_BWR_RSER_RFDF_DIRS(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field RFDF_RE[17] (RW)
+ *
+ * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - RFDF interrupt or DMA requests are disabled.
+ * - 0b1 - RFDF interrupt or DMA requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFDF_RE field. */
+#define SPI_RD_RSER_RFDF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_RE_MASK) >> SPI_RSER_RFDF_RE_SHIFT)
+#define SPI_BRD_RSER_RFDF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT))
+
+/*! @brief Set the RFDF_RE field to a new value. */
+#define SPI_WR_RSER_RFDF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_RE_MASK, SPI_RSER_RFDF_RE(value)))
+#define SPI_BWR_RSER_RFDF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field RFOF_RE[19] (RW)
+ *
+ * Enables the RFOF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - RFOF interrupt requests are disabled.
+ * - 0b1 - RFOF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_RFOF_RE field. */
+#define SPI_RD_RSER_RFOF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFOF_RE_MASK) >> SPI_RSER_RFOF_RE_SHIFT)
+#define SPI_BRD_RSER_RFOF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT))
+
+/*! @brief Set the RFOF_RE field to a new value. */
+#define SPI_WR_RSER_RFOF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFOF_RE_MASK, SPI_RSER_RFOF_RE(value)))
+#define SPI_BWR_RSER_RFOF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
+ *
+ * Selects between generating a DMA request or an interrupt request. When
+ * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
+ * interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - TFFF flag generates interrupt requests.
+ * - 0b1 - TFFF flag generates DMA requests.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */
+#define SPI_RD_RSER_TFFF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_DIRS_MASK) >> SPI_RSER_TFFF_DIRS_SHIFT)
+#define SPI_BRD_RSER_TFFF_DIRS(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT))
+
+/*! @brief Set the TFFF_DIRS field to a new value. */
+#define SPI_WR_RSER_TFFF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_DIRS_MASK, SPI_RSER_TFFF_DIRS(value)))
+#define SPI_BWR_RSER_TFFF_DIRS(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFFF_RE[25] (RW)
+ *
+ * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
+ * selects between generating an interrupt request or a DMA request.
+ *
+ * Values:
+ * - 0b0 - TFFF interrupts or DMA requests are disabled.
+ * - 0b1 - TFFF interrupts or DMA requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFFF_RE field. */
+#define SPI_RD_RSER_TFFF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_RE_MASK) >> SPI_RSER_TFFF_RE_SHIFT)
+#define SPI_BRD_RSER_TFFF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT))
+
+/*! @brief Set the TFFF_RE field to a new value. */
+#define SPI_WR_RSER_TFFF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_RE_MASK, SPI_RSER_TFFF_RE(value)))
+#define SPI_BWR_RSER_TFFF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TFUF_RE[27] (RW)
+ *
+ * Enables the TFUF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - TFUF interrupt requests are disabled.
+ * - 0b1 - TFUF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TFUF_RE field. */
+#define SPI_RD_RSER_TFUF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFUF_RE_MASK) >> SPI_RSER_TFUF_RE_SHIFT)
+#define SPI_BRD_RSER_TFUF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT))
+
+/*! @brief Set the TFUF_RE field to a new value. */
+#define SPI_WR_RSER_TFUF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFUF_RE_MASK, SPI_RSER_TFUF_RE(value)))
+#define SPI_BWR_RSER_TFUF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field EOQF_RE[28] (RW)
+ *
+ * Enables the EOQF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - EOQF interrupt requests are disabled.
+ * - 0b1 - EOQF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_EOQF_RE field. */
+#define SPI_RD_RSER_EOQF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_EOQF_RE_MASK) >> SPI_RSER_EOQF_RE_SHIFT)
+#define SPI_BRD_RSER_EOQF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT))
+
+/*! @brief Set the EOQF_RE field to a new value. */
+#define SPI_WR_RSER_EOQF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_EOQF_RE_MASK, SPI_RSER_EOQF_RE(value)))
+#define SPI_BWR_RSER_EOQF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_RSER, field TCF_RE[31] (RW)
+ *
+ * Enables TCF flag in the SR to generate an interrupt request.
+ *
+ * Values:
+ * - 0b0 - TCF interrupt requests are disabled.
+ * - 0b1 - TCF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_RSER_TCF_RE field. */
+#define SPI_RD_RSER_TCF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TCF_RE_MASK) >> SPI_RSER_TCF_RE_SHIFT)
+#define SPI_BRD_RSER_TCF_RE(base) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT))
+
+/*! @brief Set the TCF_RE field to a new value. */
+#define SPI_WR_RSER_TCF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TCF_RE_MASK, SPI_RSER_TCF_RE(value)))
+#define SPI_BWR_RSER_TCF_RE(base, value) (BITBAND_ACCESS32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_PUSHR - PUSH TX FIFO Register In Master Mode
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
+ * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
+ * can be used as data, supporting up to 32-bit frame operation. A read access
+ * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
+ * writing to this register does not update the FIFO. Therefore, any reads performed
+ * while the module is disabled return the last PUSHR write performed while the
+ * module was still enabled.
+ */
+/*!
+ * @name Constants and macros for entire SPI_PUSHR register
+ */
+/*@{*/
+#define SPI_RD_PUSHR(base)       (SPI_PUSHR_REG(base))
+#define SPI_WR_PUSHR(base, value) (SPI_PUSHR_REG(base) = (value))
+#define SPI_RMW_PUSHR(base, mask, value) (SPI_WR_PUSHR(base, (SPI_RD_PUSHR(base) & ~(mask)) | (value)))
+#define SPI_SET_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) |  (value)))
+#define SPI_CLR_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) & ~(value)))
+#define SPI_TOG_PUSHR(base, value) (SPI_WR_PUSHR(base, SPI_RD_PUSHR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_PUSHR bitfields
+ */
+
+/*!
+ * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
+ *
+ * Holds SPI data to be transferred according to the associated SPI command.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_TXDATA field. */
+#define SPI_RD_PUSHR_TXDATA(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_TXDATA_MASK) >> SPI_PUSHR_TXDATA_SHIFT)
+#define SPI_BRD_PUSHR_TXDATA(base) (SPI_RD_PUSHR_TXDATA(base))
+
+/*! @brief Set the TXDATA field to a new value. */
+#define SPI_WR_PUSHR_TXDATA(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_TXDATA_MASK, SPI_PUSHR_TXDATA(value)))
+#define SPI_BWR_PUSHR_TXDATA(base, value) (SPI_WR_PUSHR_TXDATA(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field PCS[21:16] (RW)
+ *
+ * Select which PCS signals are to be asserted for the transfer. Refer to the
+ * chip configuration details for the number of PCS signals used in this MCU.
+ *
+ * Values:
+ * - 0b000000 - Negate the PCS[x] signal.
+ * - 0b000001 - Assert the PCS[x] signal.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_PCS field. */
+#define SPI_RD_PUSHR_PCS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_PCS_MASK) >> SPI_PUSHR_PCS_SHIFT)
+#define SPI_BRD_PUSHR_PCS(base) (SPI_RD_PUSHR_PCS(base))
+
+/*! @brief Set the PCS field to a new value. */
+#define SPI_WR_PUSHR_PCS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_PCS_MASK, SPI_PUSHR_PCS(value)))
+#define SPI_BWR_PUSHR_PCS(base, value) (SPI_WR_PUSHR_PCS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CTCNT[26] (RW)
+ *
+ * Clears the TCNT field in the TCR register. The TCNT field is cleared before
+ * the module starts transmitting the current SPI frame.
+ *
+ * Values:
+ * - 0b0 - Do not clear the TCR[TCNT] field.
+ * - 0b1 - Clear the TCR[TCNT] field.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CTCNT field. */
+#define SPI_RD_PUSHR_CTCNT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTCNT_MASK) >> SPI_PUSHR_CTCNT_SHIFT)
+#define SPI_BRD_PUSHR_CTCNT(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT))
+
+/*! @brief Set the CTCNT field to a new value. */
+#define SPI_WR_PUSHR_CTCNT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTCNT_MASK, SPI_PUSHR_CTCNT(value)))
+#define SPI_BWR_PUSHR_CTCNT(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field EOQ[27] (RW)
+ *
+ * Host software uses this bit to signal to the module that the current SPI
+ * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
+ * SR is set.
+ *
+ * Values:
+ * - 0b0 - The SPI data is not the last data to transfer.
+ * - 0b1 - The SPI data is the last data to transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_EOQ field. */
+#define SPI_RD_PUSHR_EOQ(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_EOQ_MASK) >> SPI_PUSHR_EOQ_SHIFT)
+#define SPI_BRD_PUSHR_EOQ(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT))
+
+/*! @brief Set the EOQ field to a new value. */
+#define SPI_WR_PUSHR_EOQ(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_EOQ_MASK, SPI_PUSHR_EOQ(value)))
+#define SPI_BWR_PUSHR_EOQ(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
+ *
+ * Selects which CTAR to use in master mode to specify the transfer attributes
+ * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
+ * configuration details to determine how many CTARs this device has. You should
+ * not program a value in this field for a register that is not present.
+ *
+ * Values:
+ * - 0b000 - CTAR0
+ * - 0b001 - CTAR1
+ * - 0b010 - Reserved
+ * - 0b011 - Reserved
+ * - 0b100 - Reserved
+ * - 0b101 - Reserved
+ * - 0b110 - Reserved
+ * - 0b111 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CTAS field. */
+#define SPI_RD_PUSHR_CTAS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTAS_MASK) >> SPI_PUSHR_CTAS_SHIFT)
+#define SPI_BRD_PUSHR_CTAS(base) (SPI_RD_PUSHR_CTAS(base))
+
+/*! @brief Set the CTAS field to a new value. */
+#define SPI_WR_PUSHR_CTAS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTAS_MASK, SPI_PUSHR_CTAS(value)))
+#define SPI_BWR_PUSHR_CTAS(base, value) (SPI_WR_PUSHR_CTAS(base, value))
+/*@}*/
+
+/*!
+ * @name Register SPI_PUSHR, field CONT[31] (RW)
+ *
+ * Selects a continuous selection format. The bit is used in SPI Master mode.
+ * The bit enables the selected PCS signals to remain asserted between transfers.
+ *
+ * Values:
+ * - 0b0 - Return PCSn signals to their inactive state between transfers.
+ * - 0b1 - Keep PCSn signals asserted between transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_PUSHR_CONT field. */
+#define SPI_RD_PUSHR_CONT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CONT_MASK) >> SPI_PUSHR_CONT_SHIFT)
+#define SPI_BRD_PUSHR_CONT(base) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT))
+
+/*! @brief Set the CONT field to a new value. */
+#define SPI_WR_PUSHR_CONT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CONT_MASK, SPI_PUSHR_CONT(value)))
+#define SPI_BWR_PUSHR_CONT(base, value) (BITBAND_ACCESS32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
+ * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
+ * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
+ * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
+ * SPI Frame operation.
+ */
+/*!
+ * @name Constants and macros for entire SPI_PUSHR_SLAVE register
+ */
+/*@{*/
+#define SPI_RD_PUSHR_SLAVE(base) (SPI_PUSHR_SLAVE_REG(base))
+#define SPI_WR_PUSHR_SLAVE(base, value) (SPI_PUSHR_SLAVE_REG(base) = (value))
+#define SPI_RMW_PUSHR_SLAVE(base, mask, value) (SPI_WR_PUSHR_SLAVE(base, (SPI_RD_PUSHR_SLAVE(base) & ~(mask)) | (value)))
+#define SPI_SET_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) |  (value)))
+#define SPI_CLR_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) & ~(value)))
+#define SPI_TOG_PUSHR_SLAVE(base, value) (SPI_WR_PUSHR_SLAVE(base, SPI_RD_PUSHR_SLAVE(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_POPR - POP RX FIFO Register
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_POPR - POP RX FIFO Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
+ * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
+ * this register will generate a Transfer Error.
+ */
+/*!
+ * @name Constants and macros for entire SPI_POPR register
+ */
+/*@{*/
+#define SPI_RD_POPR(base)        (SPI_POPR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR0 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR0 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR0 register
+ */
+/*@{*/
+#define SPI_RD_TXFR0(base)       (SPI_TXFR0_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR0 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR0, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR0_TXDATA field. */
+#define SPI_RD_TXFR0_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXDATA_MASK) >> SPI_TXFR0_TXDATA_SHIFT)
+#define SPI_BRD_TXFR0_TXDATA(base) (SPI_RD_TXFR0_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR0, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR0_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR0_TXCMD_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXCMD_TXDATA_MASK) >> SPI_TXFR0_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR0_TXCMD_TXDATA(base) (SPI_RD_TXFR0_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR1 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR1 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR1 register
+ */
+/*@{*/
+#define SPI_RD_TXFR1(base)       (SPI_TXFR1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR1 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR1, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR1_TXDATA field. */
+#define SPI_RD_TXFR1_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXDATA_MASK) >> SPI_TXFR1_TXDATA_SHIFT)
+#define SPI_BRD_TXFR1_TXDATA(base) (SPI_RD_TXFR1_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR1, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR1_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR1_TXCMD_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXCMD_TXDATA_MASK) >> SPI_TXFR1_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR1_TXCMD_TXDATA(base) (SPI_RD_TXFR1_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR2 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR2 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR2 register
+ */
+/*@{*/
+#define SPI_RD_TXFR2(base)       (SPI_TXFR2_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR2 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR2, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR2_TXDATA field. */
+#define SPI_RD_TXFR2_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXDATA_MASK) >> SPI_TXFR2_TXDATA_SHIFT)
+#define SPI_BRD_TXFR2_TXDATA(base) (SPI_RD_TXFR2_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR2, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR2_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR2_TXCMD_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXCMD_TXDATA_MASK) >> SPI_TXFR2_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR2_TXCMD_TXDATA(base) (SPI_RD_TXFR2_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_TXFR3 - Transmit FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_TXFR3 - Transmit FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
+ * Each register is an entry in the TX FIFO. The registers are read-only and
+ * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
+ * FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_TXFR3 register
+ */
+/*@{*/
+#define SPI_RD_TXFR3(base)       (SPI_TXFR3_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual SPI_TXFR3 bitfields
+ */
+
+/*!
+ * @name Register SPI_TXFR3, field TXDATA[15:0] (RO)
+ *
+ * Contains the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR3_TXDATA field. */
+#define SPI_RD_TXFR3_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXDATA_MASK) >> SPI_TXFR3_TXDATA_SHIFT)
+#define SPI_BRD_TXFR3_TXDATA(base) (SPI_RD_TXFR3_TXDATA(base))
+/*@}*/
+
+/*!
+ * @name Register SPI_TXFR3, field TXCMD_TXDATA[31:16] (RO)
+ *
+ * In Master mode the TXCMD field contains the command that sets the transfer
+ * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
+ * the SPI data to be shifted out.
+ */
+/*@{*/
+/*! @brief Read current value of the SPI_TXFR3_TXCMD_TXDATA field. */
+#define SPI_RD_TXFR3_TXCMD_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXCMD_TXDATA_MASK) >> SPI_TXFR3_TXCMD_TXDATA_SHIFT)
+#define SPI_BRD_TXFR3_TXCMD_TXDATA(base) (SPI_RD_TXFR3_TXCMD_TXDATA(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR0 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR0 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR0 register
+ */
+/*@{*/
+#define SPI_RD_RXFR0(base)       (SPI_RXFR0_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR1 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR1 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR1 register
+ */
+/*@{*/
+#define SPI_RD_RXFR1(base)       (SPI_RXFR1_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR2 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR2 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR2 register
+ */
+/*@{*/
+#define SPI_RD_RXFR2(base)       (SPI_RXFR2_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * SPI_RXFR3 - Receive FIFO Registers
+ ******************************************************************************/
+
+/*!
+ * @brief SPI_RXFR3 - Receive FIFO Registers (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
+ * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
+ * RXFRx registers does not alter the state of the RX FIFO.
+ */
+/*!
+ * @name Constants and macros for entire SPI_RXFR3 register
+ */
+/*@{*/
+#define SPI_RD_RXFR3(base)       (SPI_RXFR3_REG(base))
+/*@}*/
+
+/*
+ * MK64F12 UART
+ *
+ * Serial Communication Interface
+ *
+ * Registers defined in this header file:
+ * - UART_BDH - UART Baud Rate Registers: High
+ * - UART_BDL - UART Baud Rate Registers: Low
+ * - UART_C1 - UART Control Register 1
+ * - UART_C2 - UART Control Register 2
+ * - UART_S1 - UART Status Register 1
+ * - UART_S2 - UART Status Register 2
+ * - UART_C3 - UART Control Register 3
+ * - UART_D - UART Data Register
+ * - UART_MA1 - UART Match Address Registers 1
+ * - UART_MA2 - UART Match Address Registers 2
+ * - UART_C4 - UART Control Register 4
+ * - UART_C5 - UART Control Register 5
+ * - UART_ED - UART Extended Data Register
+ * - UART_MODEM - UART Modem Register
+ * - UART_IR - UART Infrared Register
+ * - UART_PFIFO - UART FIFO Parameters
+ * - UART_CFIFO - UART FIFO Control Register
+ * - UART_SFIFO - UART FIFO Status Register
+ * - UART_TWFIFO - UART FIFO Transmit Watermark
+ * - UART_TCFIFO - UART FIFO Transmit Count
+ * - UART_RWFIFO - UART FIFO Receive Watermark
+ * - UART_RCFIFO - UART FIFO Receive Count
+ * - UART_C7816 - UART 7816 Control Register
+ * - UART_IE7816 - UART 7816 Interrupt Enable Register
+ * - UART_IS7816 - UART 7816 Interrupt Status Register
+ * - UART_WP7816T0 - UART 7816 Wait Parameter Register
+ * - UART_WP7816T1 - UART 7816 Wait Parameter Register
+ * - UART_WN7816 - UART 7816 Wait N Register
+ * - UART_WF7816 - UART 7816 Wait FD Register
+ * - UART_ET7816 - UART 7816 Error Threshold Register
+ * - UART_TL7816 - UART 7816 Transmit Length Register
+ */
+
+#define UART_INSTANCE_COUNT (6U) /*!< Number of instances of the UART module. */
+#define UART0_IDX (0U) /*!< Instance number for UART0. */
+#define UART1_IDX (1U) /*!< Instance number for UART1. */
+#define UART2_IDX (2U) /*!< Instance number for UART2. */
+#define UART3_IDX (3U) /*!< Instance number for UART3. */
+#define UART4_IDX (4U) /*!< Instance number for UART4. */
+#define UART5_IDX (5U) /*!< Instance number for UART5. */
+
+/*******************************************************************************
+ * UART_BDH - UART Baud Rate Registers: High
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDH - UART Baud Rate Registers: High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register, along with the BDL register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting
+ * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write
+ * to BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is,
+ * when C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDH register
+ */
+/*@{*/
+#define UART_RD_BDH(base)        (UART_BDH_REG(base))
+#define UART_WR_BDH(base, value) (UART_BDH_REG(base) = (value))
+#define UART_RMW_BDH(base, mask, value) (UART_WR_BDH(base, (UART_RD_BDH(base) & ~(mask)) | (value)))
+#define UART_SET_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) |  (value)))
+#define UART_CLR_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) & ~(value)))
+#define UART_TOG_BDH(base, value) (UART_WR_BDH(base, UART_RD_BDH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_BDH bitfields
+ */
+
+/*!
+ * @name Register UART_BDH, field SBR[4:0] (RW)
+ *
+ * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate
+ * generation for details. The baud rate generator is disabled until C2[TE] or
+ * C2[RE] is set for the first time after reset.The baud rate generator is disabled
+ * when SBR = 0. Writing to BDH has no effect without writing to BDL, because
+ * writing to BDH puts the data in a temporary location until BDL is written.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBR field. */
+#define UART_RD_BDH_SBR(base) ((UART_BDH_REG(base) & UART_BDH_SBR_MASK) >> UART_BDH_SBR_SHIFT)
+#define UART_BRD_BDH_SBR(base) (UART_RD_BDH_SBR(base))
+
+/*! @brief Set the SBR field to a new value. */
+#define UART_WR_BDH_SBR(base, value) (UART_RMW_BDH(base, UART_BDH_SBR_MASK, UART_BDH_SBR(value)))
+#define UART_BWR_BDH_SBR(base, value) (UART_WR_BDH_SBR(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field SBNS[5] (RW)
+ *
+ * SBNS selects the number of stop bits present in a data frame. This field
+ * valid for all 8, 9 and 10 bit data formats available. This field is not valid when
+ * C7816[ISO7816E] is enabled.
+ *
+ * Values:
+ * - 0b0 - Data frame consists of a single stop bit.
+ * - 0b1 - Data frame consists of two stop bits.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_SBNS field. */
+#define UART_RD_BDH_SBNS(base) ((UART_BDH_REG(base) & UART_BDH_SBNS_MASK) >> UART_BDH_SBNS_SHIFT)
+#define UART_BRD_BDH_SBNS(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_SBNS_SHIFT))
+
+/*! @brief Set the SBNS field to a new value. */
+#define UART_WR_BDH_SBNS(base, value) (UART_RMW_BDH(base, UART_BDH_SBNS_MASK, UART_BDH_SBNS(value)))
+#define UART_BWR_BDH_SBNS(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_SBNS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field RXEDGIE[6] (RW)
+ *
+ * Enables the receive input active edge, RXEDGIF, to generate interrupt
+ * requests.
+ *
+ * Values:
+ * - 0b0 - Hardware interrupts from RXEDGIF disabled using polling.
+ * - 0b1 - RXEDGIF interrupt request enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_RXEDGIE field. */
+#define UART_RD_BDH_RXEDGIE(base) ((UART_BDH_REG(base) & UART_BDH_RXEDGIE_MASK) >> UART_BDH_RXEDGIE_SHIFT)
+#define UART_BRD_BDH_RXEDGIE(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT))
+
+/*! @brief Set the RXEDGIE field to a new value. */
+#define UART_WR_BDH_RXEDGIE(base, value) (UART_RMW_BDH(base, UART_BDH_RXEDGIE_MASK, UART_BDH_RXEDGIE(value)))
+#define UART_BWR_BDH_RXEDGIE(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_RXEDGIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_BDH, field LBKDIE[7] (RW)
+ *
+ * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests
+ * based on the state of LBKDDMAS. or DMA transfer requests,
+ *
+ * Values:
+ * - 0b0 - LBKDIF interrupt and DMA transfer requests disabled.
+ * - 0b1 - LBKDIF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_BDH_LBKDIE field. */
+#define UART_RD_BDH_LBKDIE(base) ((UART_BDH_REG(base) & UART_BDH_LBKDIE_MASK) >> UART_BDH_LBKDIE_SHIFT)
+#define UART_BRD_BDH_LBKDIE(base) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_LBKDIE_SHIFT))
+
+/*! @brief Set the LBKDIE field to a new value. */
+#define UART_WR_BDH_LBKDIE(base, value) (UART_RMW_BDH(base, UART_BDH_LBKDIE_MASK, UART_BDH_LBKDIE(value)))
+#define UART_BWR_BDH_LBKDIE(base, value) (BITBAND_ACCESS8(&UART_BDH_REG(base), UART_BDH_LBKDIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_BDL - UART Baud Rate Registers: Low
+ ******************************************************************************/
+
+/*!
+ * @brief UART_BDL - UART Baud Rate Registers: Low (RW)
+ *
+ * Reset value: 0x04U
+ *
+ * This register, along with the BDH register, controls the prescale divisor for
+ * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0],
+ * first write to BDH to buffer the high half of the new value and then write to
+ * BDL. The working value in BDH does not change until BDL is written. BDL is
+ * reset to a nonzero value, but after reset, the baud rate generator remains
+ * disabled until the first time the receiver or transmitter is enabled, that is, when
+ * C2[RE] or C2[TE] is set.
+ */
+/*!
+ * @name Constants and macros for entire UART_BDL register
+ */
+/*@{*/
+#define UART_RD_BDL(base)        (UART_BDL_REG(base))
+#define UART_WR_BDL(base, value) (UART_BDL_REG(base) = (value))
+#define UART_RMW_BDL(base, mask, value) (UART_WR_BDL(base, (UART_RD_BDL(base) & ~(mask)) | (value)))
+#define UART_SET_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) |  (value)))
+#define UART_CLR_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) & ~(value)))
+#define UART_TOG_BDL(base, value) (UART_WR_BDL(base, UART_RD_BDL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C1 - UART Control Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C1 - UART Control Register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This read/write register controls various optional features of the UART
+ * system.
+ */
+/*!
+ * @name Constants and macros for entire UART_C1 register
+ */
+/*@{*/
+#define UART_RD_C1(base)         (UART_C1_REG(base))
+#define UART_WR_C1(base, value)  (UART_C1_REG(base) = (value))
+#define UART_RMW_C1(base, mask, value) (UART_WR_C1(base, (UART_RD_C1(base) & ~(mask)) | (value)))
+#define UART_SET_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) |  (value)))
+#define UART_CLR_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) & ~(value)))
+#define UART_TOG_C1(base, value) (UART_WR_C1(base, UART_RD_C1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C1 bitfields
+ */
+
+/*!
+ * @name Register UART_C1, field PT[0] (RW)
+ *
+ * Determines whether the UART generates and checks for even parity or odd
+ * parity. With even parity, an even number of 1s clears the parity bit and an odd
+ * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the
+ * parity bit and an even number of 1s sets the parity bit. This field must be
+ * cleared when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Even parity.
+ * - 0b1 - Odd parity.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PT field. */
+#define UART_RD_C1_PT(base)  ((UART_C1_REG(base) & UART_C1_PT_MASK) >> UART_C1_PT_SHIFT)
+#define UART_BRD_C1_PT(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PT_SHIFT))
+
+/*! @brief Set the PT field to a new value. */
+#define UART_WR_C1_PT(base, value) (UART_RMW_C1(base, UART_C1_PT_MASK, UART_C1_PT(value)))
+#define UART_BWR_C1_PT(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field PE[1] (RW)
+ *
+ * Enables the parity function. When parity is enabled, parity function inserts
+ * a parity bit in the bit position immediately preceding the stop bit. This
+ * field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Parity function disabled.
+ * - 0b1 - Parity function enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_PE field. */
+#define UART_RD_C1_PE(base)  ((UART_C1_REG(base) & UART_C1_PE_MASK) >> UART_C1_PE_SHIFT)
+#define UART_BRD_C1_PE(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PE_SHIFT))
+
+/*! @brief Set the PE field to a new value. */
+#define UART_WR_C1_PE(base, value) (UART_RMW_C1(base, UART_C1_PE_MASK, UART_C1_PE(value)))
+#define UART_BWR_C1_PE(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_PE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field ILT[2] (RW)
+ *
+ * Determines when the receiver starts counting logic 1s as idle character bits.
+ * The count begins either after a valid start bit or after the stop bit. If the
+ * count begins after the start bit, then a string of logic 1s preceding the
+ * stop bit can cause false recognition of an idle character. Beginning the count
+ * after the stop bit avoids false idle character recognition, but requires
+ * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a
+ * logic of 1'b0 is automatically shifted after a received stop bit, therefore
+ * resetting the idle count. In case the UART is programmed for IDLE line wakeup
+ * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting
+ * logic 1s as idle character bits. In idle line wakeup, an idle character is
+ * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE,
+ * and C4[M10] fields.
+ *
+ * Values:
+ * - 0b0 - Idle character bit count starts after start bit.
+ * - 0b1 - Idle character bit count starts after stop bit.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_ILT field. */
+#define UART_RD_C1_ILT(base) ((UART_C1_REG(base) & UART_C1_ILT_MASK) >> UART_C1_ILT_SHIFT)
+#define UART_BRD_C1_ILT(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_ILT_SHIFT))
+
+/*! @brief Set the ILT field to a new value. */
+#define UART_WR_C1_ILT(base, value) (UART_RMW_C1(base, UART_C1_ILT_MASK, UART_C1_ILT(value)))
+#define UART_BWR_C1_ILT(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_ILT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field WAKE[3] (RW)
+ *
+ * Determines which condition wakes the UART: Address mark in the most
+ * significant bit position of a received data character, or An idle condition on the
+ * receive pin input signal.
+ *
+ * Values:
+ * - 0b0 - Idle line wakeup.
+ * - 0b1 - Address mark wakeup.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_WAKE field. */
+#define UART_RD_C1_WAKE(base) ((UART_C1_REG(base) & UART_C1_WAKE_MASK) >> UART_C1_WAKE_SHIFT)
+#define UART_BRD_C1_WAKE(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT))
+
+/*! @brief Set the WAKE field to a new value. */
+#define UART_WR_C1_WAKE(base, value) (UART_RMW_C1(base, UART_C1_WAKE_MASK, UART_C1_WAKE(value)))
+#define UART_BWR_C1_WAKE(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_WAKE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field M[4] (RW)
+ *
+ * This field must be set when C7816[ISO_7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) +
+ *     stop.
+ * - 0b1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_M field. */
+#define UART_RD_C1_M(base)   ((UART_C1_REG(base) & UART_C1_M_MASK) >> UART_C1_M_SHIFT)
+#define UART_BRD_C1_M(base)  (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_M_SHIFT))
+
+/*! @brief Set the M field to a new value. */
+#define UART_WR_C1_M(base, value) (UART_RMW_C1(base, UART_C1_M_MASK, UART_C1_M(value)))
+#define UART_BWR_C1_M(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_M_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field RSRC[5] (RW)
+ *
+ * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
+ * is set, the RSRC field determines the source for the receiver shift register
+ * input.
+ *
+ * Values:
+ * - 0b0 - Selects internal loop back mode. The receiver input is internally
+ *     connected to transmitter output.
+ * - 0b1 - Single wire UART mode where the receiver input is connected to the
+ *     transmit pin input signal.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_RSRC field. */
+#define UART_RD_C1_RSRC(base) ((UART_C1_REG(base) & UART_C1_RSRC_MASK) >> UART_C1_RSRC_SHIFT)
+#define UART_BRD_C1_RSRC(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT))
+
+/*! @brief Set the RSRC field to a new value. */
+#define UART_WR_C1_RSRC(base, value) (UART_RMW_C1(base, UART_C1_RSRC_MASK, UART_C1_RSRC(value)))
+#define UART_BWR_C1_RSRC(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_RSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field UARTSWAI[6] (RW)
+ *
+ * Values:
+ * - 0b0 - UART clock continues to run in Wait mode.
+ * - 0b1 - UART clock freezes while CPU is in Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_UARTSWAI field. */
+#define UART_RD_C1_UARTSWAI(base) ((UART_C1_REG(base) & UART_C1_UARTSWAI_MASK) >> UART_C1_UARTSWAI_SHIFT)
+#define UART_BRD_C1_UARTSWAI(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_UARTSWAI_SHIFT))
+
+/*! @brief Set the UARTSWAI field to a new value. */
+#define UART_WR_C1_UARTSWAI(base, value) (UART_RMW_C1(base, UART_C1_UARTSWAI_MASK, UART_C1_UARTSWAI(value)))
+#define UART_BWR_C1_UARTSWAI(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_UARTSWAI_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C1, field LOOPS[7] (RW)
+ *
+ * When LOOPS is set, the RxD pin is disconnected from the UART and the
+ * transmitter output is internally connected to the receiver input. The transmitter and
+ * the receiver must be enabled to use the loop function.
+ *
+ * Values:
+ * - 0b0 - Normal operation.
+ * - 0b1 - Loop mode where transmitter output is internally connected to
+ *     receiver input. The receiver input is determined by RSRC.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C1_LOOPS field. */
+#define UART_RD_C1_LOOPS(base) ((UART_C1_REG(base) & UART_C1_LOOPS_MASK) >> UART_C1_LOOPS_SHIFT)
+#define UART_BRD_C1_LOOPS(base) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT))
+
+/*! @brief Set the LOOPS field to a new value. */
+#define UART_WR_C1_LOOPS(base, value) (UART_RMW_C1(base, UART_C1_LOOPS_MASK, UART_C1_LOOPS(value)))
+#define UART_BWR_C1_LOOPS(base, value) (BITBAND_ACCESS8(&UART_C1_REG(base), UART_C1_LOOPS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C2 - UART Control Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C2 - UART Control Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register can be read or written at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_C2 register
+ */
+/*@{*/
+#define UART_RD_C2(base)         (UART_C2_REG(base))
+#define UART_WR_C2(base, value)  (UART_C2_REG(base) = (value))
+#define UART_RMW_C2(base, mask, value) (UART_WR_C2(base, (UART_RD_C2(base) & ~(mask)) | (value)))
+#define UART_SET_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) |  (value)))
+#define UART_CLR_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) & ~(value)))
+#define UART_TOG_C2(base, value) (UART_WR_C2(base, UART_RD_C2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C2 bitfields
+ */
+
+/*!
+ * @name Register UART_C2, field SBK[0] (RW)
+ *
+ * Toggling SBK sends one break character from the following: See Transmitting
+ * break characters for the number of logic 0s for the different configurations.
+ * Toggling implies clearing the SBK field before the break character has finished
+ * transmitting. As long as SBK is set, the transmitter continues to send
+ * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits).
+ * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit.
+ * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13]
+ * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when
+ * C7816[ISO_7816E] is set.
+ *
+ * Values:
+ * - 0b0 - Normal transmitter operation.
+ * - 0b1 - Queue break characters to be sent.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_SBK field. */
+#define UART_RD_C2_SBK(base) ((UART_C2_REG(base) & UART_C2_SBK_MASK) >> UART_C2_SBK_SHIFT)
+#define UART_BRD_C2_SBK(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_SBK_SHIFT))
+
+/*! @brief Set the SBK field to a new value. */
+#define UART_WR_C2_SBK(base, value) (UART_RMW_C2(base, UART_C2_SBK_MASK, UART_C2_SBK(value)))
+#define UART_BWR_C2_SBK(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_SBK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RWU[1] (RW)
+ *
+ * This field can be set to place the UART receiver in a standby state. RWU
+ * automatically clears when an RWU event occurs, that is, an IDLE event when
+ * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be
+ * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup
+ * on idle) if the channel is currently not idle. This can be determined by
+ * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already
+ * idle, it is possible that the UART will discard data. This is because the data
+ * must be received or a LIN break detected after an IDLE is detected before IDLE
+ * is allowed to reasserted.
+ *
+ * Values:
+ * - 0b0 - Normal operation.
+ * - 0b1 - RWU enables the wakeup function and inhibits further receiver
+ *     interrupt requests. Normally, hardware wakes the receiver by automatically
+ *     clearing RWU.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RWU field. */
+#define UART_RD_C2_RWU(base) ((UART_C2_REG(base) & UART_C2_RWU_MASK) >> UART_C2_RWU_SHIFT)
+#define UART_BRD_C2_RWU(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RWU_SHIFT))
+
+/*! @brief Set the RWU field to a new value. */
+#define UART_WR_C2_RWU(base, value) (UART_RMW_C2(base, UART_C2_RWU_MASK, UART_C2_RWU(value)))
+#define UART_BWR_C2_RWU(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RWU_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RE[2] (RW)
+ *
+ * Enables the UART receiver.
+ *
+ * Values:
+ * - 0b0 - Receiver off.
+ * - 0b1 - Receiver on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RE field. */
+#define UART_RD_C2_RE(base)  ((UART_C2_REG(base) & UART_C2_RE_MASK) >> UART_C2_RE_SHIFT)
+#define UART_BRD_C2_RE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RE_SHIFT))
+
+/*! @brief Set the RE field to a new value. */
+#define UART_WR_C2_RE(base, value) (UART_RMW_C2(base, UART_C2_RE_MASK, UART_C2_RE(value)))
+#define UART_BWR_C2_RE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TE[3] (RW)
+ *
+ * Enables the UART transmitter. TE can be used to queue an idle preamble by
+ * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and
+ * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been
+ * transmitted. This condition is detected when TL7816[TLEN] = 0 and four
+ * additional characters are transmitted.
+ *
+ * Values:
+ * - 0b0 - Transmitter off.
+ * - 0b1 - Transmitter on.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TE field. */
+#define UART_RD_C2_TE(base)  ((UART_C2_REG(base) & UART_C2_TE_MASK) >> UART_C2_TE_SHIFT)
+#define UART_BRD_C2_TE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TE_SHIFT))
+
+/*! @brief Set the TE field to a new value. */
+#define UART_WR_C2_TE(base, value) (UART_RMW_C2(base, UART_C2_TE_MASK, UART_C2_TE(value)))
+#define UART_BWR_C2_TE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field ILIE[4] (RW)
+ *
+ * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA
+ * transfer requests based on the state of C5[ILDMAS].
+ *
+ * Values:
+ * - 0b0 - IDLE interrupt requests disabled. and DMA transfer
+ * - 0b1 - IDLE interrupt requests enabled. or DMA transfer
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_ILIE field. */
+#define UART_RD_C2_ILIE(base) ((UART_C2_REG(base) & UART_C2_ILIE_MASK) >> UART_C2_ILIE_SHIFT)
+#define UART_BRD_C2_ILIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT))
+
+/*! @brief Set the ILIE field to a new value. */
+#define UART_WR_C2_ILIE(base, value) (UART_RMW_C2(base, UART_C2_ILIE_MASK, UART_C2_ILIE(value)))
+#define UART_BWR_C2_ILIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_ILIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field RIE[5] (RW)
+ *
+ * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[RDMAS].
+ *
+ * Values:
+ * - 0b0 - RDRF interrupt and DMA transfer requests disabled.
+ * - 0b1 - RDRF interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_RIE field. */
+#define UART_RD_C2_RIE(base) ((UART_C2_REG(base) & UART_C2_RIE_MASK) >> UART_C2_RIE_SHIFT)
+#define UART_BRD_C2_RIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RIE_SHIFT))
+
+/*! @brief Set the RIE field to a new value. */
+#define UART_WR_C2_RIE(base, value) (UART_RMW_C2(base, UART_C2_RIE_MASK, UART_C2_RIE(value)))
+#define UART_BWR_C2_RIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_RIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TCIE[6] (RW)
+ *
+ * Enables the transmission complete flag, S1[TC], to generate interrupt
+ * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and
+ * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be
+ * written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0b0 - TC interrupt and DMA transfer requests disabled.
+ * - 0b1 - TC interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TCIE field. */
+#define UART_RD_C2_TCIE(base) ((UART_C2_REG(base) & UART_C2_TCIE_MASK) >> UART_C2_TCIE_SHIFT)
+#define UART_BRD_C2_TCIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT))
+
+/*! @brief Set the TCIE field to a new value. */
+#define UART_WR_C2_TCIE(base, value) (UART_RMW_C2(base, UART_C2_TCIE_MASK, UART_C2_TCIE(value)))
+#define UART_BWR_C2_TCIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TCIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C2, field TIE[7] (RW)
+ *
+ * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests,
+ * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE
+ * must be cleared, and D[D] must not be written unless servicing a DMA request.
+ *
+ * Values:
+ * - 0b0 - TDRE interrupt and DMA transfer requests disabled.
+ * - 0b1 - TDRE interrupt or DMA transfer requests enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C2_TIE field. */
+#define UART_RD_C2_TIE(base) ((UART_C2_REG(base) & UART_C2_TIE_MASK) >> UART_C2_TIE_SHIFT)
+#define UART_BRD_C2_TIE(base) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TIE_SHIFT))
+
+/*! @brief Set the TIE field to a new value. */
+#define UART_WR_C2_TIE(base, value) (UART_RMW_C2(base, UART_C2_TIE_MASK, UART_C2_TIE(value)))
+#define UART_BWR_C2_TIE(base, value) (BITBAND_ACCESS8(&UART_C2_REG(base), UART_C2_TIE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S1 - UART Status Register 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S1 - UART Status Register 1 (RO)
+ *
+ * Reset value: 0xC0U
+ *
+ * The S1 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. This register can also be polled by the MCU to check the
+ * status of its fields. To clear a flag, the status register should be read followed
+ * by a read or write to D register, depending on the interrupt flag type. Other
+ * instructions can be executed between the two steps as long the handling of
+ * I/O is not compromised, but the order of operations is important for flag
+ * clearing. When a flag is configured to trigger a DMA request, assertion of the
+ * associated DMA done signal from the DMA controller clears the flag. If the
+ * condition that results in the assertion of the flag, interrupt, or DMA request is not
+ * resolved prior to clearing the flag, the flag, and interrupt/DMA request,
+ * reasserts. For example, if the DMA or interrupt service routine fails to write
+ * sufficient data to the transmit buffer to raise it above the watermark level, the
+ * flag reasserts and generates another interrupt or DMA request. Reading an
+ * empty data register to clear one of the flags of the S1 register causes the FIFO
+ * pointers to become misaligned. A receive FIFO flush reinitializes the
+ * pointers. A better way to prevent this situation is to always leave one byte in FIFO
+ * and this byte will be read eventually in clearing the flag bit.
+ */
+/*!
+ * @name Constants and macros for entire UART_S1 register
+ */
+/*@{*/
+#define UART_RD_S1(base)         (UART_S1_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S1 bitfields
+ */
+
+/*!
+ * @name Register UART_S1, field PF[0] (RO)
+ *
+ * PF is set when PE is set and the parity of the received data does not match
+ * its parity bit. The PF is not set in the case of an overrun condition. When PF
+ * is set, it indicates only that a dataword was received with parity error since
+ * the last time it was cleared. There is no guarantee that the first dataword
+ * read from the receive buffer has a parity error or that there is only one
+ * dataword in the buffer that was received with a parity error, unless the receive
+ * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is
+ * disabled, Within the receive buffer structure the received dataword is tagged
+ * if it is received with a parity error. This information is available by reading
+ * the ED register prior to reading the D register.
+ *
+ * Values:
+ * - 0b0 - No parity error detected since the last time this flag was cleared.
+ *     If the receive buffer has a depth greater than 1, then there may be data in
+ *     the receive buffer what was received with a parity error.
+ * - 0b1 - At least one dataword was received with a parity error since the last
+ *     time this flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_PF field. */
+#define UART_RD_S1_PF(base)  ((UART_S1_REG(base) & UART_S1_PF_MASK) >> UART_S1_PF_SHIFT)
+#define UART_BRD_S1_PF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_PF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field FE[1] (RO)
+ *
+ * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set,
+ * then FE will set when a logic 0 is accepted for either of the two stop bits.
+ * FE does not set in the case of an overrun or while the LIN break detect feature
+ * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is
+ * cleared. To clear FE, read S1 with FE set and then read D. The last data in the
+ * receive buffer represents the data that was received with the frame error
+ * enabled. Framing errors are not supported when 7816E is set/enabled. However, if
+ * this flag is set, data is still not received in 7816 mode.
+ *
+ * Values:
+ * - 0b0 - No framing error detected.
+ * - 0b1 - Framing error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_FE field. */
+#define UART_RD_S1_FE(base)  ((UART_S1_REG(base) & UART_S1_FE_MASK) >> UART_S1_FE_SHIFT)
+#define UART_BRD_S1_FE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_FE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field NF[2] (RO)
+ *
+ * NF is set when the UART detects noise on the receiver input. NF does not
+ * become set in the case of an overrun or while the LIN break detect feature is
+ * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has
+ * been received with noise since the last time it was cleared. There is no
+ * guarantee that the first dataword read from the receive buffer has noise or that there
+ * is only one dataword in the buffer that was received with noise unless the
+ * receive buffer has a depth of one. To clear NF, read S1 and then read D.
+ *
+ * Values:
+ * - 0b0 - No noise detected since the last time this flag was cleared. If the
+ *     receive buffer has a depth greater than 1 then there may be data in the
+ *     receiver buffer that was received with noise.
+ * - 0b1 - At least one dataword was received with noise detected since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_NF field. */
+#define UART_RD_S1_NF(base)  ((UART_S1_REG(base) & UART_S1_NF_MASK) >> UART_S1_NF_SHIFT)
+#define UART_BRD_S1_NF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_NF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field OR[3] (RO)
+ *
+ * OR is set when software fails to prevent the receive data register from
+ * overflowing with data. The OR bit is set immediately after the stop bit has been
+ * completely received for the dataword that overflows the buffer and all the other
+ * error flags (FE, NF, and PF) are prevented from setting. The data in the
+ * shift register is lost, but the data already in the UART data registers is not
+ * affected. If the OR flag is set, no data is stored in the data buffer even if
+ * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE
+ * flags are blocked from asserting, that is, transition from an inactive to an
+ * active state. To clear OR, read S1 when OR is set and then read D. See
+ * functional description for more details regarding the operation of the OR bit.If
+ * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF]
+ * is not cleared before the next data character is received. In 7816 mode, it is
+ * possible to configure a NACK to be returned by programing C7816[ONACK].
+ *
+ * Values:
+ * - 0b0 - No overrun has occurred since the last time the flag was cleared.
+ * - 0b1 - Overrun has occurred or the overrun flag has not been cleared since
+ *     the last overrun occured.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_OR field. */
+#define UART_RD_S1_OR(base)  ((UART_S1_REG(base) & UART_S1_OR_MASK) >> UART_S1_OR_SHIFT)
+#define UART_BRD_S1_OR(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_OR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field IDLE[4] (RO)
+ *
+ * After the IDLE flag is cleared, a frame must be received (although not
+ * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN
+ * break character must set the S2[LBKDIF] flag before an idle condition can set the
+ * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
+ * IDLE is set when either of the following appear on the receiver input: 10
+ * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10]
+ * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle
+ * detection is not supported when 7816E is set/enabled and hence this flag is
+ * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE
+ * flag if RWUID is set, else the IDLE flag does not become set.
+ *
+ * Values:
+ * - 0b0 - Receiver input is either active now or has never become active since
+ *     the IDLE flag was last cleared.
+ * - 0b1 - Receiver input has become idle or the flag has not been cleared since
+ *     it last asserted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_IDLE field. */
+#define UART_RD_S1_IDLE(base) ((UART_S1_REG(base) & UART_S1_IDLE_MASK) >> UART_S1_IDLE_SHIFT)
+#define UART_BRD_S1_IDLE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_IDLE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field RDRF[5] (RO)
+ *
+ * RDRF is set when the number of datawords in the receive buffer is equal to or
+ * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the
+ * process of being received is not included in the count. To clear RDRF, read S1
+ * when RDRF is set and then read D. For more efficient interrupt and DMA
+ * operation, read all data except the final value from the buffer, using D/C3[T8]/ED.
+ * Then read S1 and the final data value, resulting in the clearing of the RDRF
+ * flag. Even if RDRF is set, data will continue to be received until an overrun
+ * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set.
+ * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive
+ * buffer but over-write each other.
+ *
+ * Values:
+ * - 0b0 - The number of datawords in the receive buffer is less than the number
+ *     indicated by RXWATER.
+ * - 0b1 - The number of datawords in the receive buffer is equal to or greater
+ *     than the number indicated by RXWATER at some point in time since this flag
+ *     was last cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_RDRF field. */
+#define UART_RD_S1_RDRF(base) ((UART_S1_REG(base) & UART_S1_RDRF_MASK) >> UART_S1_RDRF_SHIFT)
+#define UART_BRD_S1_RDRF(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_RDRF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TC[6] (RO)
+ *
+ * TC is set when the transmit buffer is empty and no data, preamble, or break
+ * character is being transmitted. When TC is set, the transmit data output signal
+ * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then
+ * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is
+ * set after any NACK signal has been received, but prior to any corresponding
+ * guard times expiring. Writing to D to transmit new data. Queuing a preamble by
+ * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK
+ * in C2.
+ *
+ * Values:
+ * - 0b0 - Transmitter active (sending data, a preamble, or a break).
+ * - 0b1 - Transmitter idle (transmission activity complete).
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TC field. */
+#define UART_RD_S1_TC(base)  ((UART_S1_REG(base) & UART_S1_TC_MASK) >> UART_S1_TC_SHIFT)
+#define UART_BRD_S1_TC(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_TC_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S1, field TDRE[7] (RO)
+ *
+ * TDRE will set when the number of datawords in the transmit buffer (D and
+ * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A
+ * character that is in the process of being transmitted is not included in the count.
+ * To clear TDRE, read S1 when TDRE is set and then write to the UART data
+ * register (D). For more efficient interrupt servicing, all data except the final value
+ * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read
+ * before writing the final data value, resulting in the clearing of the TRDE
+ * flag. This is more efficient because the TDRE reasserts until the watermark has
+ * been exceeded. So, attempting to clear the TDRE with every write will be
+ * ineffective until sufficient data has been written.
+ *
+ * Values:
+ * - 0b0 - The amount of data in the transmit buffer is greater than the value
+ *     indicated by TWFIFO[TXWATER].
+ * - 0b1 - The amount of data in the transmit buffer is less than or equal to
+ *     the value indicated by TWFIFO[TXWATER] at some point in time since the flag
+ *     has been cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S1_TDRE field. */
+#define UART_RD_S1_TDRE(base) ((UART_S1_REG(base) & UART_S1_TDRE_MASK) >> UART_S1_TDRE_SHIFT)
+#define UART_BRD_S1_TDRE(base) (BITBAND_ACCESS8(&UART_S1_REG(base), UART_S1_TDRE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_S2 - UART Status Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_S2 - UART Status Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The S2 register provides inputs to the MCU for generation of UART interrupts
+ * or DMA requests. Also, this register can be polled by the MCU to check the
+ * status of these bits. This register can be read or written at any time, with the
+ * exception of the MSBF and RXINV bits, which should be changed by the user only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_S2 register
+ */
+/*@{*/
+#define UART_RD_S2(base)         (UART_S2_REG(base))
+#define UART_WR_S2(base, value)  (UART_S2_REG(base) = (value))
+#define UART_RMW_S2(base, mask, value) (UART_WR_S2(base, (UART_RD_S2(base) & ~(mask)) | (value)))
+#define UART_SET_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) |  (value)))
+#define UART_CLR_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) & ~(value)))
+#define UART_TOG_S2(base, value) (UART_WR_S2(base, UART_RD_S2(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_S2 bitfields
+ */
+
+/*!
+ * @name Register UART_S2, field RAF[0] (RO)
+ *
+ * RAF is set when the UART receiver detects a logic 0 during the RT1 time
+ * period of the start bit search. RAF is cleared when the receiver detects an idle
+ * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is
+ * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] =
+ * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible
+ * to configure the guard time to 12. However, if a NACK is required to be
+ * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a
+ * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU
+ * prior to actually being inactive.
+ *
+ * Values:
+ * - 0b0 - UART receiver idle/inactive waiting for a start bit.
+ * - 0b1 - UART receiver active, RxD input not idle.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RAF field. */
+#define UART_RD_S2_RAF(base) ((UART_S2_REG(base) & UART_S2_RAF_MASK) >> UART_S2_RAF_SHIFT)
+#define UART_BRD_S2_RAF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RAF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field LBKDE[1] (RW)
+ *
+ * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF],
+ * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see .
+ * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set.
+ *
+ * Values:
+ * - 0b0 - Break character detection is disabled.
+ * - 0b1 - Break character is detected at length of 11 bit times if C1[M] = 0 or
+ *     12 bits time if C1[M] = 1.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_LBKDE field. */
+#define UART_RD_S2_LBKDE(base) ((UART_S2_REG(base) & UART_S2_LBKDE_MASK) >> UART_S2_LBKDE_SHIFT)
+#define UART_BRD_S2_LBKDE(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDE_SHIFT))
+
+/*! @brief Set the LBKDE field to a new value. */
+#define UART_WR_S2_LBKDE(base, value) (UART_RMW_S2(base, (UART_S2_LBKDE_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_LBKDE(value)))
+#define UART_BWR_S2_LBKDE(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field BRK13[2] (RW)
+ *
+ * Determines whether the transmit break character is 10, 11, or 12 bits long,
+ * or 13 or 14 bits long. See for the length of the break character for the
+ * different configurations. The detection of a framing error is not affected by this
+ * field. Transmitting break characters
+ *
+ * Values:
+ * - 0b0 - Break character is 10, 11, or 12 bits long.
+ * - 0b1 - Break character is 13 or 14 bits long.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_BRK13 field. */
+#define UART_RD_S2_BRK13(base) ((UART_S2_REG(base) & UART_S2_BRK13_MASK) >> UART_S2_BRK13_SHIFT)
+#define UART_BRD_S2_BRK13(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT))
+
+/*! @brief Set the BRK13 field to a new value. */
+#define UART_WR_S2_BRK13(base, value) (UART_RMW_S2(base, (UART_S2_BRK13_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_BRK13(value)))
+#define UART_BWR_S2_BRK13(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_BRK13_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RWUID[3] (RW)
+ *
+ * When RWU is set and WAKE is cleared, this field controls whether the idle
+ * character that wakes the receiver sets S1[IDLE]. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled.
+ *
+ * Values:
+ * - 0b0 - S1[IDLE] is not set upon detection of an idle character.
+ * - 0b1 - S1[IDLE] is set upon detection of an idle character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RWUID field. */
+#define UART_RD_S2_RWUID(base) ((UART_S2_REG(base) & UART_S2_RWUID_MASK) >> UART_S2_RWUID_SHIFT)
+#define UART_BRD_S2_RWUID(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT))
+
+/*! @brief Set the RWUID field to a new value. */
+#define UART_WR_S2_RWUID(base, value) (UART_RMW_S2(base, (UART_S2_RWUID_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RWUID(value)))
+#define UART_BWR_S2_RWUID(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RWUID_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the received data input. In NRZ
+ * format, a one is represented by a mark and a zero is represented by a space for
+ * normal polarity, and the opposite for inverted polarity. In IrDA format, a
+ * zero is represented by short high pulse in the middle of a bit time remaining
+ * idle low for a one for normal polarity. A zero is represented by a short low
+ * pulse in the middle of a bit time remaining idle high for a one for inverted
+ * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are
+ * enabled and an initial character is detected in T = 0 protocol mode. Setting
+ * RXINV inverts the RxD input for data bits, start and stop bits, break, and
+ * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit
+ * are inverted.
+ *
+ * Values:
+ * - 0b0 - Receive data is not inverted.
+ * - 0b1 - Receive data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXINV field. */
+#define UART_RD_S2_RXINV(base) ((UART_S2_REG(base) & UART_S2_RXINV_MASK) >> UART_S2_RXINV_SHIFT)
+#define UART_BRD_S2_RXINV(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT))
+
+/*! @brief Set the RXINV field to a new value. */
+#define UART_WR_S2_RXINV(base, value) (UART_RMW_S2(base, (UART_S2_RXINV_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RXINV(value)))
+#define UART_BWR_S2_RXINV(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXINV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field MSBF[5] (RW)
+ *
+ * Setting this field reverses the order of the bits that are transmitted and
+ * received on the wire. This field does not affect the polarity of the bits, the
+ * location of the parity bit, or the location of the start or stop bits. This
+ * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and
+ * an initial character is detected in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0b0 - LSB (bit0) is the first bit that is transmitted following the start
+ *     bit. Further, the first bit received after the start bit is identified as
+ *     bit0.
+ * - 0b1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted
+ *     following the start bit, depending on the setting of C1[M] and C1[PE]. Further,
+ *     the first bit received after the start bit is identified as bit8, bit7, or
+ *     bit6, depending on the setting of C1[M] and C1[PE].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_MSBF field. */
+#define UART_RD_S2_MSBF(base) ((UART_S2_REG(base) & UART_S2_MSBF_MASK) >> UART_S2_MSBF_SHIFT)
+#define UART_BRD_S2_MSBF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT))
+
+/*! @brief Set the MSBF field to a new value. */
+#define UART_WR_S2_MSBF(base, value) (UART_RMW_S2(base, (UART_S2_MSBF_MASK | UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_MSBF(value)))
+#define UART_BWR_S2_MSBF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_MSBF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field RXEDGIF[6] (W1C)
+ *
+ * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is
+ * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1
+ * to it. See for additional details. RXEDGIF description The active edge is
+ * detected only in two wire mode and on receiving data coming from the RxD pin.
+ *
+ * Values:
+ * - 0b0 - No active edge on the receive pin has occurred.
+ * - 0b1 - An active edge on the receive pin has occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_RXEDGIF field. */
+#define UART_RD_S2_RXEDGIF(base) ((UART_S2_REG(base) & UART_S2_RXEDGIF_MASK) >> UART_S2_RXEDGIF_SHIFT)
+#define UART_BRD_S2_RXEDGIF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT))
+
+/*! @brief Set the RXEDGIF field to a new value. */
+#define UART_WR_S2_RXEDGIF(base, value) (UART_RMW_S2(base, (UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK), UART_S2_RXEDGIF(value)))
+#define UART_BWR_S2_RXEDGIF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_RXEDGIF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_S2, field LBKDIF[7] (W1C)
+ *
+ * LBKDIF is set when LBKDE is set and a LIN break character is detected on the
+ * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M]
+ * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the
+ * last LIN break character. LBKDIF is cleared by writing a 1 to it.
+ *
+ * Values:
+ * - 0b0 - No LIN break character detected.
+ * - 0b1 - LIN break character detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_S2_LBKDIF field. */
+#define UART_RD_S2_LBKDIF(base) ((UART_S2_REG(base) & UART_S2_LBKDIF_MASK) >> UART_S2_LBKDIF_SHIFT)
+#define UART_BRD_S2_LBKDIF(base) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDIF_SHIFT))
+
+/*! @brief Set the LBKDIF field to a new value. */
+#define UART_WR_S2_LBKDIF(base, value) (UART_RMW_S2(base, (UART_S2_LBKDIF_MASK | UART_S2_RXEDGIF_MASK), UART_S2_LBKDIF(value)))
+#define UART_BWR_S2_LBKDIF(base, value) (BITBAND_ACCESS8(&UART_S2_REG(base), UART_S2_LBKDIF_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C3 - UART Control Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C3 - UART Control Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Writing R8 does not have any effect. TXDIR and TXINV can be changed only
+ * between transmit and receive packets.
+ */
+/*!
+ * @name Constants and macros for entire UART_C3 register
+ */
+/*@{*/
+#define UART_RD_C3(base)         (UART_C3_REG(base))
+#define UART_WR_C3(base, value)  (UART_C3_REG(base) = (value))
+#define UART_RMW_C3(base, mask, value) (UART_WR_C3(base, (UART_RD_C3(base) & ~(mask)) | (value)))
+#define UART_SET_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) |  (value)))
+#define UART_CLR_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) & ~(value)))
+#define UART_TOG_C3(base, value) (UART_WR_C3(base, UART_RD_C3(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C3 bitfields
+ */
+
+/*!
+ * @name Register UART_C3, field PEIE[0] (RW)
+ *
+ * Enables the parity error flag, S1[PF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - PF interrupt requests are disabled.
+ * - 0b1 - PF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_PEIE field. */
+#define UART_RD_C3_PEIE(base) ((UART_C3_REG(base) & UART_C3_PEIE_MASK) >> UART_C3_PEIE_SHIFT)
+#define UART_BRD_C3_PEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT))
+
+/*! @brief Set the PEIE field to a new value. */
+#define UART_WR_C3_PEIE(base, value) (UART_RMW_C3(base, UART_C3_PEIE_MASK, UART_C3_PEIE(value)))
+#define UART_BWR_C3_PEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_PEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field FEIE[1] (RW)
+ *
+ * Enables the framing error flag, S1[FE], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - FE interrupt requests are disabled.
+ * - 0b1 - FE interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_FEIE field. */
+#define UART_RD_C3_FEIE(base) ((UART_C3_REG(base) & UART_C3_FEIE_MASK) >> UART_C3_FEIE_SHIFT)
+#define UART_BRD_C3_FEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT))
+
+/*! @brief Set the FEIE field to a new value. */
+#define UART_WR_C3_FEIE(base, value) (UART_RMW_C3(base, UART_C3_FEIE_MASK, UART_C3_FEIE(value)))
+#define UART_BWR_C3_FEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_FEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field NEIE[2] (RW)
+ *
+ * Enables the noise flag, S1[NF], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - NF interrupt requests are disabled.
+ * - 0b1 - NF interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_NEIE field. */
+#define UART_RD_C3_NEIE(base) ((UART_C3_REG(base) & UART_C3_NEIE_MASK) >> UART_C3_NEIE_SHIFT)
+#define UART_BRD_C3_NEIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT))
+
+/*! @brief Set the NEIE field to a new value. */
+#define UART_WR_C3_NEIE(base, value) (UART_RMW_C3(base, UART_C3_NEIE_MASK, UART_C3_NEIE(value)))
+#define UART_BWR_C3_NEIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_NEIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field ORIE[3] (RW)
+ *
+ * Enables the overrun error flag, S1[OR], to generate interrupt requests.
+ *
+ * Values:
+ * - 0b0 - OR interrupts are disabled.
+ * - 0b1 - OR interrupt requests are enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_ORIE field. */
+#define UART_RD_C3_ORIE(base) ((UART_C3_REG(base) & UART_C3_ORIE_MASK) >> UART_C3_ORIE_SHIFT)
+#define UART_BRD_C3_ORIE(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT))
+
+/*! @brief Set the ORIE field to a new value. */
+#define UART_WR_C3_ORIE(base, value) (UART_RMW_C3(base, UART_C3_ORIE_MASK, UART_C3_ORIE(value)))
+#define UART_BWR_C3_ORIE(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_ORIE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXINV[4] (RW)
+ *
+ * Setting this field reverses the polarity of the transmitted data output. In
+ * NRZ format, a one is represented by a mark and a zero is represented by a space
+ * for normal polarity, and the opposite for inverted polarity. In IrDA format,
+ * a zero is represented by short high pulse in the middle of a bit time
+ * remaining idle low for a one for normal polarity, and a zero is represented by short
+ * low pulse in the middle of a bit time remaining idle high for a one for
+ * inverted polarity. This field is automatically set when C7816[INIT] and
+ * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode.
+ * Setting TXINV inverts all transmitted values, including idle, break, start, and
+ * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit
+ * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only
+ * the transmitted data bits and parity bit are inverted.
+ *
+ * Values:
+ * - 0b0 - Transmit data is not inverted.
+ * - 0b1 - Transmit data is inverted.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXINV field. */
+#define UART_RD_C3_TXINV(base) ((UART_C3_REG(base) & UART_C3_TXINV_MASK) >> UART_C3_TXINV_SHIFT)
+#define UART_BRD_C3_TXINV(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT))
+
+/*! @brief Set the TXINV field to a new value. */
+#define UART_WR_C3_TXINV(base, value) (UART_RMW_C3(base, UART_C3_TXINV_MASK, UART_C3_TXINV(value)))
+#define UART_BWR_C3_TXINV(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXINV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field TXDIR[5] (RW)
+ *
+ * Determines whether the TXD pin is used as an input or output in the
+ * single-wire mode of operation. This field is relevant only to the single wire mode.
+ * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is
+ * automatically cleared after the requested block is transmitted. This condition is
+ * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted.
+ * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is
+ * being transmitted, the hardware automatically overrides this field as needed. In
+ * this situation, TXDIR does not reflect the temporary state associated with
+ * the NACK.
+ *
+ * Values:
+ * - 0b0 - TXD pin is an input in single wire mode.
+ * - 0b1 - TXD pin is an output in single wire mode.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_TXDIR field. */
+#define UART_RD_C3_TXDIR(base) ((UART_C3_REG(base) & UART_C3_TXDIR_MASK) >> UART_C3_TXDIR_SHIFT)
+#define UART_BRD_C3_TXDIR(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT))
+
+/*! @brief Set the TXDIR field to a new value. */
+#define UART_WR_C3_TXDIR(base, value) (UART_RMW_C3(base, UART_C3_TXDIR_MASK, UART_C3_TXDIR(value)))
+#define UART_BWR_C3_TXDIR(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_TXDIR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field T8[6] (RW)
+ *
+ * T8 is the ninth data bit transmitted when the UART is configured for 9-bit
+ * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the
+ * same as in the previous transmission, T8 does not have to be rewritten. The same
+ * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit,
+ * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with
+ * the remaining data.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_T8 field. */
+#define UART_RD_C3_T8(base)  ((UART_C3_REG(base) & UART_C3_T8_MASK) >> UART_C3_T8_SHIFT)
+#define UART_BRD_C3_T8(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_T8_SHIFT))
+
+/*! @brief Set the T8 field to a new value. */
+#define UART_WR_C3_T8(base, value) (UART_RMW_C3(base, UART_C3_T8_MASK, UART_C3_T8(value)))
+#define UART_BWR_C3_T8(base, value) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_T8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C3, field R8[7] (RO)
+ *
+ * R8 is the ninth data bit received when the UART is configured for 9-bit data
+ * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the
+ * current data value in the UARTx_D register. To read the 9th bit, read the
+ * value of UARTx_C3[R8], then read the UARTx_D register.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C3_R8 field. */
+#define UART_RD_C3_R8(base)  ((UART_C3_REG(base) & UART_C3_R8_MASK) >> UART_C3_R8_SHIFT)
+#define UART_BRD_C3_R8(base) (BITBAND_ACCESS8(&UART_C3_REG(base), UART_C3_R8_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_D - UART Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_D - UART Data Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register is actually two separate registers. Reads return the contents
+ * of the read-only receive data register and writes go to the write-only transmit
+ * data register. In 8-bit or 9-bit data format, only UART data register (D)
+ * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is
+ * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D
+ * register, only if the ninth bit of data needs to be captured. Similarly, the
+ * ED register needs to be read, prior to the D register, only if the additional
+ * flag data for the dataword needs to be captured. In the normal 8-bit mode (M
+ * bit cleared) if the parity is enabled, you get seven data bits and one parity
+ * bit. That one parity bit is loaded into the D register. So, for the data bits,
+ * mask off the parity bit from the value you read out of this register. When
+ * transmitting in 9-bit data format and using 8-bit write instructions, write first
+ * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to
+ * C3[T8] stores the data in a temporary register. If D register is written first,
+ * and then the new data on data bus is stored in D, the temporary value written by
+ * the last write to C3[T8] gets stored in the C3[T8] register.
+ */
+/*!
+ * @name Constants and macros for entire UART_D register
+ */
+/*@{*/
+#define UART_RD_D(base)          (UART_D_REG(base))
+#define UART_WR_D(base, value)   (UART_D_REG(base) = (value))
+#define UART_RMW_D(base, mask, value) (UART_WR_D(base, (UART_RD_D(base) & ~(mask)) | (value)))
+#define UART_SET_D(base, value)  (UART_WR_D(base, UART_RD_D(base) |  (value)))
+#define UART_CLR_D(base, value)  (UART_WR_D(base, UART_RD_D(base) & ~(value)))
+#define UART_TOG_D(base, value)  (UART_WR_D(base, UART_RD_D(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA1 - UART Match Address Registers 1
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA1 - UART Match Address Registers 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MA1 and MA2 registers are compared to input data addresses when the most
+ * significant bit is set and the associated C4[MAEN] field is set. If a match
+ * occurs, the following data is transferred to the data register. If a match
+ * fails, the following data is discarded. These registers can be read and written at
+ * anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA1 register
+ */
+/*@{*/
+#define UART_RD_MA1(base)        (UART_MA1_REG(base))
+#define UART_WR_MA1(base, value) (UART_MA1_REG(base) = (value))
+#define UART_RMW_MA1(base, mask, value) (UART_WR_MA1(base, (UART_RD_MA1(base) & ~(mask)) | (value)))
+#define UART_SET_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) |  (value)))
+#define UART_CLR_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) & ~(value)))
+#define UART_TOG_MA1(base, value) (UART_WR_MA1(base, UART_RD_MA1(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MA2 - UART Match Address Registers 2
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MA2 - UART Match Address Registers 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * These registers can be read and written at anytime. The MA1 and MA2 registers
+ * are compared to input data addresses when the most significant bit is set and
+ * the associated C4[MAEN] field is set. If a match occurs, the following data
+ * is transferred to the data register. If a match fails, the following data is
+ * discarded.
+ */
+/*!
+ * @name Constants and macros for entire UART_MA2 register
+ */
+/*@{*/
+#define UART_RD_MA2(base)        (UART_MA2_REG(base))
+#define UART_WR_MA2(base, value) (UART_MA2_REG(base) = (value))
+#define UART_RMW_MA2(base, mask, value) (UART_WR_MA2(base, (UART_RD_MA2(base) & ~(mask)) | (value)))
+#define UART_SET_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) |  (value)))
+#define UART_CLR_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) & ~(value)))
+#define UART_TOG_MA2(base, value) (UART_WR_MA2(base, UART_RD_MA2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C4 - UART Control Register 4
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C4 - UART Control Register 4 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C4 register
+ */
+/*@{*/
+#define UART_RD_C4(base)         (UART_C4_REG(base))
+#define UART_WR_C4(base, value)  (UART_C4_REG(base) = (value))
+#define UART_RMW_C4(base, mask, value) (UART_WR_C4(base, (UART_RD_C4(base) & ~(mask)) | (value)))
+#define UART_SET_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) |  (value)))
+#define UART_CLR_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) & ~(value)))
+#define UART_TOG_C4(base, value) (UART_WR_C4(base, UART_RD_C4(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C4 bitfields
+ */
+
+/*!
+ * @name Register UART_C4, field BRFA[4:0] (RW)
+ *
+ * This bit field is used to add more timing resolution to the average baud
+ * frequency, in increments of 1/32. See Baud rate generation for more information.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_BRFA field. */
+#define UART_RD_C4_BRFA(base) ((UART_C4_REG(base) & UART_C4_BRFA_MASK) >> UART_C4_BRFA_SHIFT)
+#define UART_BRD_C4_BRFA(base) (UART_RD_C4_BRFA(base))
+
+/*! @brief Set the BRFA field to a new value. */
+#define UART_WR_C4_BRFA(base, value) (UART_RMW_C4(base, UART_C4_BRFA_MASK, UART_C4_BRFA(value)))
+#define UART_BWR_C4_BRFA(base, value) (UART_WR_C4_BRFA(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field M10[5] (RW)
+ *
+ * Causes a tenth, non-memory mapped bit to be part of the serial transmission.
+ * This tenth bit is generated and interpreted as a parity bit. The M10 field
+ * does not affect the LIN send or detect break behavior. If M10 is set, then both
+ * C1[M] and C1[PE] must also be set. This field must be cleared when
+ * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information.
+ *
+ * Values:
+ * - 0b0 - The parity bit is the ninth bit in the serial transmission.
+ * - 0b1 - The parity bit is the tenth bit in the serial transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_M10 field. */
+#define UART_RD_C4_M10(base) ((UART_C4_REG(base) & UART_C4_M10_MASK) >> UART_C4_M10_SHIFT)
+#define UART_BRD_C4_M10(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_M10_SHIFT))
+
+/*! @brief Set the M10 field to a new value. */
+#define UART_WR_C4_M10(base, value) (UART_RMW_C4(base, UART_C4_M10_MASK, UART_C4_M10(value)))
+#define UART_BWR_C4_M10(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_M10_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN2[6] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0b0 - All data received is transferred to the data buffer if MAEN1 is
+ *     cleared.
+ * - 0b1 - All data received with the most significant bit cleared, is
+ *     discarded. All data received with the most significant bit set, is compared with
+ *     contents of MA2 register. If no match occurs, the data is discarded. If a
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN2 field. */
+#define UART_RD_C4_MAEN2(base) ((UART_C4_REG(base) & UART_C4_MAEN2_MASK) >> UART_C4_MAEN2_SHIFT)
+#define UART_BRD_C4_MAEN2(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT))
+
+/*! @brief Set the MAEN2 field to a new value. */
+#define UART_WR_C4_MAEN2(base, value) (UART_RMW_C4(base, UART_C4_MAEN2_MASK, UART_C4_MAEN2(value)))
+#define UART_BWR_C4_MAEN2(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN2_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C4, field MAEN1[7] (RW)
+ *
+ * See Match address operation for more information.
+ *
+ * Values:
+ * - 0b0 - All data received is transferred to the data buffer if MAEN2 is
+ *     cleared.
+ * - 0b1 - All data received with the most significant bit cleared, is
+ *     discarded. All data received with the most significant bit set, is compared with
+ *     contents of MA1 register. If no match occurs, the data is discarded. If
+ *     match occurs, data is transferred to the data buffer. This field must be
+ *     cleared when C7816[ISO7816E] is set/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C4_MAEN1 field. */
+#define UART_RD_C4_MAEN1(base) ((UART_C4_REG(base) & UART_C4_MAEN1_MASK) >> UART_C4_MAEN1_SHIFT)
+#define UART_BRD_C4_MAEN1(base) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT))
+
+/*! @brief Set the MAEN1 field to a new value. */
+#define UART_WR_C4_MAEN1(base, value) (UART_RMW_C4(base, UART_C4_MAEN1_MASK, UART_C4_MAEN1(value)))
+#define UART_BWR_C4_MAEN1(base, value) (BITBAND_ACCESS8(&UART_C4_REG(base), UART_C4_MAEN1_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C5 - UART Control Register 5
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C5 - UART Control Register 5 (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire UART_C5 register
+ */
+/*@{*/
+#define UART_RD_C5(base)         (UART_C5_REG(base))
+#define UART_WR_C5(base, value)  (UART_C5_REG(base) = (value))
+#define UART_RMW_C5(base, mask, value) (UART_WR_C5(base, (UART_RD_C5(base) & ~(mask)) | (value)))
+#define UART_SET_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) |  (value)))
+#define UART_CLR_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) & ~(value)))
+#define UART_TOG_C5(base, value) (UART_WR_C5(base, UART_RD_C5(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C5 bitfields
+ */
+
+/*!
+ * @name Register UART_C5, field LBKDDMAS[3] (RW)
+ *
+ * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or
+ * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is
+ * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless
+ * of the state of LBKDDMAS.
+ *
+ * Values:
+ * - 0b0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is
+ *     asserted to request an interrupt service.
+ * - 0b1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal
+ *     is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_LBKDDMAS field. */
+#define UART_RD_C5_LBKDDMAS(base) ((UART_C5_REG(base) & UART_C5_LBKDDMAS_MASK) >> UART_C5_LBKDDMAS_SHIFT)
+#define UART_BRD_C5_LBKDDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_LBKDDMAS_SHIFT))
+
+/*! @brief Set the LBKDDMAS field to a new value. */
+#define UART_WR_C5_LBKDDMAS(base, value) (UART_RMW_C5(base, UART_C5_LBKDDMAS_MASK, UART_C5_LBKDDMAS(value)))
+#define UART_BWR_C5_LBKDDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_LBKDDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field ILDMAS[4] (RW)
+ *
+ * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA
+ * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE
+ * DMA and IDLE interrupt request signals are not asserted, regardless of the state
+ * of ILDMAS.
+ *
+ * Values:
+ * - 0b0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal
+ *     is asserted to request an interrupt service.
+ * - 0b1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_ILDMAS field. */
+#define UART_RD_C5_ILDMAS(base) ((UART_C5_REG(base) & UART_C5_ILDMAS_MASK) >> UART_C5_ILDMAS_SHIFT)
+#define UART_BRD_C5_ILDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_ILDMAS_SHIFT))
+
+/*! @brief Set the ILDMAS field to a new value. */
+#define UART_WR_C5_ILDMAS(base, value) (UART_RMW_C5(base, UART_C5_ILDMAS_MASK, UART_C5_ILDMAS(value)))
+#define UART_BWR_C5_ILDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_ILDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field RDMAS[5] (RW)
+ *
+ * Configures the receiver data register full flag, S1[RDRF], to generate
+ * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is
+ * set, the RDRF DMA and RDFR interrupt request signals are not asserted,
+ * regardless of the state of RDMAS.
+ *
+ * Values:
+ * - 0b0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is
+ *     asserted to request an interrupt service.
+ * - 0b1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is
+ *     asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_RDMAS field. */
+#define UART_RD_C5_RDMAS(base) ((UART_C5_REG(base) & UART_C5_RDMAS_MASK) >> UART_C5_RDMAS_SHIFT)
+#define UART_BRD_C5_RDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT))
+
+/*! @brief Set the RDMAS field to a new value. */
+#define UART_WR_C5_RDMAS(base, value) (UART_RMW_C5(base, UART_C5_RDMAS_MASK, UART_C5_RDMAS(value)))
+#define UART_BWR_C5_RDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_RDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TCDMAS[6] (RW)
+ *
+ * Configures the transmission complete flag, S1[TC], to generate interrupt or
+ * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC
+ * interrupt request signals are not asserted when the S1[TC] flag is set, regardless
+ * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE]
+ * must be cleared, and D must not be written unless a DMA request is being serviced.
+ *
+ * Values:
+ * - 0b0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt
+ *     request signal is asserted to request an interrupt service.
+ * - 0b1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TCDMAS field. */
+#define UART_RD_C5_TCDMAS(base) ((UART_C5_REG(base) & UART_C5_TCDMAS_MASK) >> UART_C5_TCDMAS_SHIFT)
+#define UART_BRD_C5_TCDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TCDMAS_SHIFT))
+
+/*! @brief Set the TCDMAS field to a new value. */
+#define UART_WR_C5_TCDMAS(base, value) (UART_RMW_C5(base, UART_C5_TCDMAS_MASK, UART_C5_TCDMAS(value)))
+#define UART_BWR_C5_TCDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TCDMAS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C5, field TDMAS[7] (RW)
+ *
+ * Configures the transmit data register empty flag, S1[TDRE], to generate
+ * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and
+ * TDRE interrupt request signals are not asserted when the TDRE flag is set,
+ * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE]
+ * must be cleared, and D must not be written unless a DMA request is being
+ * serviced.
+ *
+ * Values:
+ * - 0b0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt
+ *     request signal is asserted to request interrupt service.
+ * - 0b1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request
+ *     signal is asserted to request a DMA transfer.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C5_TDMAS field. */
+#define UART_RD_C5_TDMAS(base) ((UART_C5_REG(base) & UART_C5_TDMAS_MASK) >> UART_C5_TDMAS_SHIFT)
+#define UART_BRD_C5_TDMAS(base) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT))
+
+/*! @brief Set the TDMAS field to a new value. */
+#define UART_WR_C5_TDMAS(base, value) (UART_RMW_C5(base, UART_C5_TDMAS_MASK, UART_C5_TDMAS(value)))
+#define UART_BWR_C5_TDMAS(base, value) (BITBAND_ACCESS8(&UART_C5_REG(base), UART_C5_TDMAS_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ED - UART Extended Data Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ED - UART Extended Data Register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains additional information flags that are stored with a
+ * received dataword. This register may be read at any time but contains valid data
+ * only if there is a dataword in the receive FIFO. The data contained in this
+ * register represents additional information regarding the conditions on which a
+ * dataword was received. The importance of this data varies with the
+ * application, and in some cases maybe completely optional. These fields automatically
+ * update to reflect the conditions of the next dataword whenever D is read. If
+ * S1[NF] and S1[PF] have not been set since the last time the receive buffer was
+ * empty, the NOISY and PARITYE fields will be zero.
+ */
+/*!
+ * @name Constants and macros for entire UART_ED register
+ */
+/*@{*/
+#define UART_RD_ED(base)         (UART_ED_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ED bitfields
+ */
+
+/*!
+ * @name Register UART_ED, field PARITYE[6] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with a
+ * parity error.
+ *
+ * Values:
+ * - 0b0 - The dataword was received without a parity error.
+ * - 0b1 - The dataword was received with a parity error.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ED_PARITYE field. */
+#define UART_RD_ED_PARITYE(base) ((UART_ED_REG(base) & UART_ED_PARITYE_MASK) >> UART_ED_PARITYE_SHIFT)
+#define UART_BRD_ED_PARITYE(base) (BITBAND_ACCESS8(&UART_ED_REG(base), UART_ED_PARITYE_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_ED, field NOISY[7] (RO)
+ *
+ * The current received dataword contained in D and C3[R8] was received with
+ * noise.
+ *
+ * Values:
+ * - 0b0 - The dataword was received without noise.
+ * - 0b1 - The data was received with noise.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ED_NOISY field. */
+#define UART_RD_ED_NOISY(base) ((UART_ED_REG(base) & UART_ED_NOISY_MASK) >> UART_ED_NOISY_SHIFT)
+#define UART_BRD_ED_NOISY(base) (BITBAND_ACCESS8(&UART_ED_REG(base), UART_ED_NOISY_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_MODEM - UART Modem Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_MODEM - UART Modem Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The MODEM register controls options for setting the modem configuration.
+ * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is
+ * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The
+ * ISO-7816 protocol does not use the RTS and CTS signals.
+ */
+/*!
+ * @name Constants and macros for entire UART_MODEM register
+ */
+/*@{*/
+#define UART_RD_MODEM(base)      (UART_MODEM_REG(base))
+#define UART_WR_MODEM(base, value) (UART_MODEM_REG(base) = (value))
+#define UART_RMW_MODEM(base, mask, value) (UART_WR_MODEM(base, (UART_RD_MODEM(base) & ~(mask)) | (value)))
+#define UART_SET_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) |  (value)))
+#define UART_CLR_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) & ~(value)))
+#define UART_TOG_MODEM(base, value) (UART_WR_MODEM(base, UART_RD_MODEM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_MODEM bitfields
+ */
+
+/*!
+ * @name Register UART_MODEM, field TXCTSE[0] (RW)
+ *
+ * TXCTSE controls the operation of the transmitter. TXCTSE can be set
+ * independently from the state of TXRTSE and RXRTSE.
+ *
+ * Values:
+ * - 0b0 - CTS has no effect on the transmitter.
+ * - 0b1 - Enables clear-to-send operation. The transmitter checks the state of
+ *     CTS each time it is ready to send a character. If CTS is asserted, the
+ *     character is sent. If CTS is deasserted, the signal TXD remains in the mark
+ *     state and transmission is delayed until CTS is asserted. Changes in CTS as
+ *     a character is being sent do not affect its transmission.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXCTSE field. */
+#define UART_RD_MODEM_TXCTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_TXCTSE_MASK) >> UART_MODEM_TXCTSE_SHIFT)
+#define UART_BRD_MODEM_TXCTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXCTSE_SHIFT))
+
+/*! @brief Set the TXCTSE field to a new value. */
+#define UART_WR_MODEM_TXCTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXCTSE_MASK, UART_MODEM_TXCTSE(value)))
+#define UART_BWR_MODEM_TXCTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXCTSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field TXRTSE[1] (RW)
+ *
+ * Controls RTS before and after a transmission.
+ *
+ * Values:
+ * - 0b0 - The transmitter has no effect on RTS.
+ * - 0b1 - When a character is placed into an empty transmitter data buffer ,
+ *     RTS asserts one bit time before the start bit is transmitted. RTS deasserts
+ *     one bit time after all characters in the transmitter data buffer and shift
+ *     register are completely sent, including the last stop bit. (FIFO) (FIFO)
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXRTSE field. */
+#define UART_RD_MODEM_TXRTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_TXRTSE_MASK) >> UART_MODEM_TXRTSE_SHIFT)
+#define UART_BRD_MODEM_TXRTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSE_SHIFT))
+
+/*! @brief Set the TXRTSE field to a new value. */
+#define UART_WR_MODEM_TXRTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXRTSE_MASK, UART_MODEM_TXRTSE(value)))
+#define UART_BWR_MODEM_TXRTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field TXRTSPOL[2] (RW)
+ *
+ * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
+ * polarity of the receiver RTS. RTS will remain negated in the active low state
+ * unless TXRTSE is set.
+ *
+ * Values:
+ * - 0b0 - Transmitter RTS is active low.
+ * - 0b1 - Transmitter RTS is active high.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_TXRTSPOL field. */
+#define UART_RD_MODEM_TXRTSPOL(base) ((UART_MODEM_REG(base) & UART_MODEM_TXRTSPOL_MASK) >> UART_MODEM_TXRTSPOL_SHIFT)
+#define UART_BRD_MODEM_TXRTSPOL(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSPOL_SHIFT))
+
+/*! @brief Set the TXRTSPOL field to a new value. */
+#define UART_WR_MODEM_TXRTSPOL(base, value) (UART_RMW_MODEM(base, UART_MODEM_TXRTSPOL_MASK, UART_MODEM_TXRTSPOL(value)))
+#define UART_BWR_MODEM_TXRTSPOL(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_TXRTSPOL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_MODEM, field RXRTSE[3] (RW)
+ *
+ * Allows the RTS output to control the CTS input of the transmitting device to
+ * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
+ *
+ * Values:
+ * - 0b0 - The receiver has no effect on RTS.
+ * - 0b1 - RTS is deasserted if the number of characters in the receiver data
+ *     register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted
+ *     when the number of characters in the receiver data register (FIFO) is
+ *     less than RWFIFO[RXWATER].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_MODEM_RXRTSE field. */
+#define UART_RD_MODEM_RXRTSE(base) ((UART_MODEM_REG(base) & UART_MODEM_RXRTSE_MASK) >> UART_MODEM_RXRTSE_SHIFT)
+#define UART_BRD_MODEM_RXRTSE(base) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_RXRTSE_SHIFT))
+
+/*! @brief Set the RXRTSE field to a new value. */
+#define UART_WR_MODEM_RXRTSE(base, value) (UART_RMW_MODEM(base, UART_MODEM_RXRTSE_MASK, UART_MODEM_RXRTSE(value)))
+#define UART_BWR_MODEM_RXRTSE(base, value) (BITBAND_ACCESS8(&UART_MODEM_REG(base), UART_MODEM_RXRTSE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IR - UART Infrared Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IR - UART Infrared Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IR register controls options for setting the infrared configuration.
+ */
+/*!
+ * @name Constants and macros for entire UART_IR register
+ */
+/*@{*/
+#define UART_RD_IR(base)         (UART_IR_REG(base))
+#define UART_WR_IR(base, value)  (UART_IR_REG(base) = (value))
+#define UART_RMW_IR(base, mask, value) (UART_WR_IR(base, (UART_RD_IR(base) & ~(mask)) | (value)))
+#define UART_SET_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) |  (value)))
+#define UART_CLR_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) & ~(value)))
+#define UART_TOG_IR(base, value) (UART_WR_IR(base, UART_RD_IR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IR bitfields
+ */
+
+/*!
+ * @name Register UART_IR, field TNP[1:0] (RW)
+ *
+ * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse.
+ *
+ * Values:
+ * - 0b00 - 3/16.
+ * - 0b01 - 1/16.
+ * - 0b10 - 1/32.
+ * - 0b11 - 1/4.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IR_TNP field. */
+#define UART_RD_IR_TNP(base) ((UART_IR_REG(base) & UART_IR_TNP_MASK) >> UART_IR_TNP_SHIFT)
+#define UART_BRD_IR_TNP(base) (UART_RD_IR_TNP(base))
+
+/*! @brief Set the TNP field to a new value. */
+#define UART_WR_IR_TNP(base, value) (UART_RMW_IR(base, UART_IR_TNP_MASK, UART_IR_TNP(value)))
+#define UART_BWR_IR_TNP(base, value) (UART_WR_IR_TNP(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_IR, field IREN[2] (RW)
+ *
+ * Enables/disables the infrared modulation/demodulation.
+ *
+ * Values:
+ * - 0b0 - IR disabled.
+ * - 0b1 - IR enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IR_IREN field. */
+#define UART_RD_IR_IREN(base) ((UART_IR_REG(base) & UART_IR_IREN_MASK) >> UART_IR_IREN_SHIFT)
+#define UART_BRD_IR_IREN(base) (BITBAND_ACCESS8(&UART_IR_REG(base), UART_IR_IREN_SHIFT))
+
+/*! @brief Set the IREN field to a new value. */
+#define UART_WR_IR_IREN(base, value) (UART_RMW_IR(base, UART_IR_IREN_MASK, UART_IR_IREN(value)))
+#define UART_BWR_IR_IREN(base, value) (BITBAND_ACCESS8(&UART_IR_REG(base), UART_IR_IREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_PFIFO - UART FIFO Parameters
+ ******************************************************************************/
+
+/*!
+ * @brief UART_PFIFO - UART FIFO Parameters (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability for the programmer to turn on and off FIFO
+ * functionality. It also provides the size of the FIFO that has been
+ * implemented. This register may be read at any time. This register must be written only
+ * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is
+ * empty.
+ */
+/*!
+ * @name Constants and macros for entire UART_PFIFO register
+ */
+/*@{*/
+#define UART_RD_PFIFO(base)      (UART_PFIFO_REG(base))
+#define UART_WR_PFIFO(base, value) (UART_PFIFO_REG(base) = (value))
+#define UART_RMW_PFIFO(base, mask, value) (UART_WR_PFIFO(base, (UART_RD_PFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) |  (value)))
+#define UART_CLR_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) & ~(value)))
+#define UART_TOG_PFIFO(base, value) (UART_WR_PFIFO(base, UART_RD_PFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_PFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO)
+ *
+ * The maximum number of receive datawords that can be stored in the receive
+ * buffer before an overrun occurs. This field is read only.
+ *
+ * Values:
+ * - 0b000 - Receive FIFO/Buffer depth = 1 dataword.
+ * - 0b001 - Receive FIFO/Buffer depth = 4 datawords.
+ * - 0b010 - Receive FIFO/Buffer depth = 8 datawords.
+ * - 0b011 - Receive FIFO/Buffer depth = 16 datawords.
+ * - 0b100 - Receive FIFO/Buffer depth = 32 datawords.
+ * - 0b101 - Receive FIFO/Buffer depth = 64 datawords.
+ * - 0b110 - Receive FIFO/Buffer depth = 128 datawords.
+ * - 0b111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. */
+#define UART_RD_PFIFO_RXFIFOSIZE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_RXFIFOSIZE_MASK) >> UART_PFIFO_RXFIFOSIZE_SHIFT)
+#define UART_BRD_PFIFO_RXFIFOSIZE(base) (UART_RD_PFIFO_RXFIFOSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field RXFE[3] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the receive buffer is
+ * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field.
+ * If this field is not set, the receive buffer operates as a FIFO of depth one
+ * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be
+ * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH
+ * commands must be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0b0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
+ * - 0b1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_RXFE field. */
+#define UART_RD_PFIFO_RXFE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_RXFE_MASK) >> UART_PFIFO_RXFE_SHIFT)
+#define UART_BRD_PFIFO_RXFE(base) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_RXFE_SHIFT))
+
+/*! @brief Set the RXFE field to a new value. */
+#define UART_WR_PFIFO_RXFE(base, value) (UART_RMW_PFIFO(base, UART_PFIFO_RXFE_MASK, UART_PFIFO_RXFE(value)))
+#define UART_BWR_PFIFO_RXFE(base, value) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_RXFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO)
+ *
+ * The maximum number of transmit datawords that can be stored in the transmit
+ * buffer. This field is read only.
+ *
+ * Values:
+ * - 0b000 - Transmit FIFO/Buffer depth = 1 dataword.
+ * - 0b001 - Transmit FIFO/Buffer depth = 4 datawords.
+ * - 0b010 - Transmit FIFO/Buffer depth = 8 datawords.
+ * - 0b011 - Transmit FIFO/Buffer depth = 16 datawords.
+ * - 0b100 - Transmit FIFO/Buffer depth = 32 datawords.
+ * - 0b101 - Transmit FIFO/Buffer depth = 64 datawords.
+ * - 0b110 - Transmit FIFO/Buffer depth = 128 datawords.
+ * - 0b111 - Reserved.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. */
+#define UART_RD_PFIFO_TXFIFOSIZE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_TXFIFOSIZE_MASK) >> UART_PFIFO_TXFIFOSIZE_SHIFT)
+#define UART_BRD_PFIFO_TXFIFOSIZE(base) (UART_RD_PFIFO_TXFIFOSIZE(base))
+/*@}*/
+
+/*!
+ * @name Register UART_PFIFO, field TXFE[7] (RW)
+ *
+ * When this field is set, the built in FIFO structure for the transmit buffer
+ * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this
+ * field is not set, the transmit buffer operates as a FIFO of depth one dataword
+ * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared
+ * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must
+ * be issued immediately after changing this field.
+ *
+ * Values:
+ * - 0b0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
+ * - 0b1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_PFIFO_TXFE field. */
+#define UART_RD_PFIFO_TXFE(base) ((UART_PFIFO_REG(base) & UART_PFIFO_TXFE_MASK) >> UART_PFIFO_TXFE_SHIFT)
+#define UART_BRD_PFIFO_TXFE(base) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_TXFE_SHIFT))
+
+/*! @brief Set the TXFE field to a new value. */
+#define UART_WR_PFIFO_TXFE(base, value) (UART_RMW_PFIFO(base, UART_PFIFO_TXFE_MASK, UART_PFIFO_TXFE(value)))
+#define UART_BWR_PFIFO_TXFE(base, value) (BITBAND_ACCESS8(&UART_PFIFO_REG(base), UART_PFIFO_TXFE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_CFIFO - UART FIFO Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_CFIFO - UART FIFO Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to program various control fields for FIFO
+ * operation. This register may be read or written at any time. Note that
+ * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action
+ * to prevent unintended/unpredictable behavior. Therefore, it is recommended that
+ * TE and RE be cleared prior to flushing the corresponding FIFO.
+ */
+/*!
+ * @name Constants and macros for entire UART_CFIFO register
+ */
+/*@{*/
+#define UART_RD_CFIFO(base)      (UART_CFIFO_REG(base))
+#define UART_WR_CFIFO(base, value) (UART_CFIFO_REG(base) = (value))
+#define UART_RMW_CFIFO(base, mask, value) (UART_WR_CFIFO(base, (UART_RD_CFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) |  (value)))
+#define UART_CLR_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) & ~(value)))
+#define UART_TOG_CFIFO(base, value) (UART_WR_CFIFO(base, UART_RD_CFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_CFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_CFIFO, field RXUFE[0] (RW)
+ *
+ * When this field is set, the RXUF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - RXUF flag does not generate an interrupt to the host.
+ * - 0b1 - RXUF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_RXUFE field. */
+#define UART_RD_CFIFO_RXUFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_RXUFE_MASK) >> UART_CFIFO_RXUFE_SHIFT)
+#define UART_BRD_CFIFO_RXUFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXUFE_SHIFT))
+
+/*! @brief Set the RXUFE field to a new value. */
+#define UART_WR_CFIFO_RXUFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXUFE_MASK, UART_CFIFO_RXUFE(value)))
+#define UART_BWR_CFIFO_RXUFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXUFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field TXOFE[1] (RW)
+ *
+ * When this field is set, the TXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - TXOF flag does not generate an interrupt to the host.
+ * - 0b1 - TXOF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_TXOFE field. */
+#define UART_RD_CFIFO_TXOFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_TXOFE_MASK) >> UART_CFIFO_TXOFE_SHIFT)
+#define UART_BRD_CFIFO_TXOFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXOFE_SHIFT))
+
+/*! @brief Set the TXOFE field to a new value. */
+#define UART_WR_CFIFO_TXOFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_TXOFE_MASK, UART_CFIFO_TXOFE(value)))
+#define UART_BWR_CFIFO_TXOFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXOFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field RXOFE[2] (RW)
+ *
+ * When this field is set, the RXOF flag generates an interrupt to the host.
+ *
+ * Values:
+ * - 0b0 - RXOF flag does not generate an interrupt to the host.
+ * - 0b1 - RXOF flag generates an interrupt to the host.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_CFIFO_RXOFE field. */
+#define UART_RD_CFIFO_RXOFE(base) ((UART_CFIFO_REG(base) & UART_CFIFO_RXOFE_MASK) >> UART_CFIFO_RXOFE_SHIFT)
+#define UART_BRD_CFIFO_RXOFE(base) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXOFE_SHIFT))
+
+/*! @brief Set the RXOFE field to a new value. */
+#define UART_WR_CFIFO_RXOFE(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXOFE_MASK, UART_CFIFO_RXOFE(value)))
+#define UART_BWR_CFIFO_RXOFE(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXOFE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the receive
+ * FIFO/buffer to be flushed. This does not affect data that is in the receive shift
+ * register.
+ *
+ * Values:
+ * - 0b0 - No flush operation occurs.
+ * - 0b1 - All data in the receive FIFO/buffer is cleared out.
+ */
+/*@{*/
+/*! @brief Set the RXFLUSH field to a new value. */
+#define UART_WR_CFIFO_RXFLUSH(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_RXFLUSH_MASK, UART_CFIFO_RXFLUSH(value)))
+#define UART_BWR_CFIFO_RXFLUSH(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_RXFLUSH_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ)
+ *
+ * Writing to this field causes all data that is stored in the transmit
+ * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift
+ * register.
+ *
+ * Values:
+ * - 0b0 - No flush operation occurs.
+ * - 0b1 - All data in the transmit FIFO/Buffer is cleared out.
+ */
+/*@{*/
+/*! @brief Set the TXFLUSH field to a new value. */
+#define UART_WR_CFIFO_TXFLUSH(base, value) (UART_RMW_CFIFO(base, UART_CFIFO_TXFLUSH_MASK, UART_CFIFO_TXFLUSH(value)))
+#define UART_BWR_CFIFO_TXFLUSH(base, value) (BITBAND_ACCESS8(&UART_CFIFO_REG(base), UART_CFIFO_TXFLUSH_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_SFIFO - UART FIFO Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_SFIFO - UART FIFO Status Register (RW)
+ *
+ * Reset value: 0xC0U
+ *
+ * This register provides status information regarding the transmit and receiver
+ * buffers/FIFOs, including interrupt information. This register may be written
+ * to or read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_SFIFO register
+ */
+/*@{*/
+#define UART_RD_SFIFO(base)      (UART_SFIFO_REG(base))
+#define UART_WR_SFIFO(base, value) (UART_SFIFO_REG(base) = (value))
+#define UART_RMW_SFIFO(base, mask, value) (UART_WR_SFIFO(base, (UART_RD_SFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) |  (value)))
+#define UART_CLR_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) & ~(value)))
+#define UART_TOG_SFIFO(base, value) (UART_WR_SFIFO(base, UART_RD_SFIFO(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_SFIFO bitfields
+ */
+
+/*!
+ * @name Register UART_SFIFO, field RXUF[0] (W1C)
+ *
+ * Indicates that more data has been read from the receive buffer than was
+ * present. This field will assert regardless of the value of CFIFO[RXUFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No receive buffer underflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one receive buffer underflow has occurred since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXUF field. */
+#define UART_RD_SFIFO_RXUF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXUF_MASK) >> UART_SFIFO_RXUF_SHIFT)
+#define UART_BRD_SFIFO_RXUF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXUF_SHIFT))
+
+/*! @brief Set the RXUF field to a new value. */
+#define UART_WR_SFIFO_RXUF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_RXUF_MASK | UART_SFIFO_TXOF_MASK | UART_SFIFO_RXOF_MASK), UART_SFIFO_RXUF(value)))
+#define UART_BWR_SFIFO_RXUF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXUF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field TXOF[1] (W1C)
+ *
+ * Indicates that more data has been written to the transmit buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This
+ * flag is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No transmit buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one transmit buffer overflow has occurred since the last
+ *     time the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_TXOF field. */
+#define UART_RD_SFIFO_TXOF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_TXOF_MASK) >> UART_SFIFO_TXOF_SHIFT)
+#define UART_BRD_SFIFO_TXOF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXOF_SHIFT))
+
+/*! @brief Set the TXOF field to a new value. */
+#define UART_WR_SFIFO_TXOF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_TXOF_MASK | UART_SFIFO_RXUF_MASK | UART_SFIFO_RXOF_MASK), UART_SFIFO_TXOF(value)))
+#define UART_BWR_SFIFO_TXOF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field RXOF[2] (W1C)
+ *
+ * Indicates that more data has been written to the receive buffer than it can
+ * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However,
+ * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag
+ * is cleared by writing a 1.
+ *
+ * Values:
+ * - 0b0 - No receive buffer overflow has occurred since the last time the flag
+ *     was cleared.
+ * - 0b1 - At least one receive buffer overflow has occurred since the last time
+ *     the flag was cleared.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXOF field. */
+#define UART_RD_SFIFO_RXOF(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXOF_MASK) >> UART_SFIFO_RXOF_SHIFT)
+#define UART_BRD_SFIFO_RXOF(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXOF_SHIFT))
+
+/*! @brief Set the RXOF field to a new value. */
+#define UART_WR_SFIFO_RXOF(base, value) (UART_RMW_SFIFO(base, (UART_SFIFO_RXOF_MASK | UART_SFIFO_RXUF_MASK | UART_SFIFO_TXOF_MASK), UART_SFIFO_RXOF(value)))
+#define UART_BWR_SFIFO_RXOF(base, value) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field RXEMPT[6] (RO)
+ *
+ * Asserts when there is no data in the receive FIFO/Buffer. This field does not
+ * take into account data that is in the receive shift register.
+ *
+ * Values:
+ * - 0b0 - Receive buffer is not empty.
+ * - 0b1 - Receive buffer is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_RXEMPT field. */
+#define UART_RD_SFIFO_RXEMPT(base) ((UART_SFIFO_REG(base) & UART_SFIFO_RXEMPT_MASK) >> UART_SFIFO_RXEMPT_SHIFT)
+#define UART_BRD_SFIFO_RXEMPT(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_RXEMPT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register UART_SFIFO, field TXEMPT[7] (RO)
+ *
+ * Asserts when there is no data in the Transmit FIFO/buffer. This field does
+ * not take into account data that is in the transmit shift register.
+ *
+ * Values:
+ * - 0b0 - Transmit buffer is not empty.
+ * - 0b1 - Transmit buffer is empty.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_SFIFO_TXEMPT field. */
+#define UART_RD_SFIFO_TXEMPT(base) ((UART_SFIFO_REG(base) & UART_SFIFO_TXEMPT_MASK) >> UART_SFIFO_TXEMPT_SHIFT)
+#define UART_BRD_SFIFO_TXEMPT(base) (BITBAND_ACCESS8(&UART_SFIFO_REG(base), UART_SFIFO_TXEMPT_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TWFIFO - UART FIFO Transmit Watermark
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TWFIFO - UART FIFO Transmit Watermark (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of needing additional transmit data. This register may be read at any
+ * time but must be written only when C2[TE] is not set. Changing the value of the
+ * watermark will not clear the S1[TDRE] flag.
+ */
+/*!
+ * @name Constants and macros for entire UART_TWFIFO register
+ */
+/*@{*/
+#define UART_RD_TWFIFO(base)     (UART_TWFIFO_REG(base))
+#define UART_WR_TWFIFO(base, value) (UART_TWFIFO_REG(base) = (value))
+#define UART_RMW_TWFIFO(base, mask, value) (UART_WR_TWFIFO(base, (UART_RD_TWFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) |  (value)))
+#define UART_CLR_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) & ~(value)))
+#define UART_TOG_TWFIFO(base, value) (UART_WR_TWFIFO(base, UART_RD_TWFIFO(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TCFIFO - UART FIFO Transmit Count
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TCFIFO - UART FIFO Transmit Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the transmit buffer/FIFO. It may be read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_TCFIFO register
+ */
+/*@{*/
+#define UART_RD_TCFIFO(base)     (UART_TCFIFO_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * UART_RWFIFO - UART FIFO Receive Watermark
+ ******************************************************************************/
+
+/*!
+ * @brief UART_RWFIFO - UART FIFO Receive Watermark (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * This register provides the ability to set a programmable threshold for
+ * notification of the need to remove data from the receiver FIFO/buffer. This register
+ * may be read at any time but must be written only when C2[RE] is not asserted.
+ * Changing the value in this register will not clear S1[RDRF].
+ */
+/*!
+ * @name Constants and macros for entire UART_RWFIFO register
+ */
+/*@{*/
+#define UART_RD_RWFIFO(base)     (UART_RWFIFO_REG(base))
+#define UART_WR_RWFIFO(base, value) (UART_RWFIFO_REG(base) = (value))
+#define UART_RMW_RWFIFO(base, mask, value) (UART_WR_RWFIFO(base, (UART_RD_RWFIFO(base) & ~(mask)) | (value)))
+#define UART_SET_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) |  (value)))
+#define UART_CLR_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) & ~(value)))
+#define UART_TOG_RWFIFO(base, value) (UART_WR_RWFIFO(base, UART_RD_RWFIFO(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_RCFIFO - UART FIFO Receive Count
+ ******************************************************************************/
+
+/*!
+ * @brief UART_RCFIFO - UART FIFO Receive Count (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * This is a read only register that indicates how many datawords are currently
+ * in the receive FIFO/buffer. It may be read at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_RCFIFO register
+ */
+/*@{*/
+#define UART_RD_RCFIFO(base)     (UART_RCFIFO_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * UART_C7816 - UART 7816 Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_C7816 - UART 7816 Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The C7816 register is the primary control register for ISO-7816 specific
+ * functionality. This register is specific to 7816 functionality and the values in
+ * this register have no effect on UART operation and should be ignored if
+ * ISO_7816E is not set/enabled. This register may be read at any time but values must
+ * be changed only when ISO_7816E is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_C7816 register
+ */
+/*@{*/
+#define UART_RD_C7816(base)      (UART_C7816_REG(base))
+#define UART_WR_C7816(base, value) (UART_C7816_REG(base) = (value))
+#define UART_RMW_C7816(base, mask, value) (UART_WR_C7816(base, (UART_RD_C7816(base) & ~(mask)) | (value)))
+#define UART_SET_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) |  (value)))
+#define UART_CLR_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) & ~(value)))
+#define UART_TOG_C7816(base, value) (UART_WR_C7816(base, UART_RD_C7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_C7816 bitfields
+ */
+
+/*!
+ * @name Register UART_C7816, field ISO_7816E[0] (RW)
+ *
+ * Indicates that the UART is operating according to the ISO-7816 protocol. This
+ * field must be modified only when no transmit or receive is occurring. If this
+ * field is changed during a data transfer, the data being transmitted or
+ * received may be transferred incorrectly.
+ *
+ * Values:
+ * - 0b0 - ISO-7816 functionality is turned off/not enabled.
+ * - 0b1 - ISO-7816 functionality is turned on/enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ISO_7816E field. */
+#define UART_RD_C7816_ISO_7816E(base) ((UART_C7816_REG(base) & UART_C7816_ISO_7816E_MASK) >> UART_C7816_ISO_7816E_SHIFT)
+#define UART_BRD_C7816_ISO_7816E(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT))
+
+/*! @brief Set the ISO_7816E field to a new value. */
+#define UART_WR_C7816_ISO_7816E(base, value) (UART_RMW_C7816(base, UART_C7816_ISO_7816E_MASK, UART_C7816_ISO_7816E(value)))
+#define UART_BWR_C7816_ISO_7816E(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ISO_7816E_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field TTYPE[1] (RW)
+ *
+ * Indicates the transfer protocol being used. See ISO-7816 / smartcard support
+ * for more details.
+ *
+ * Values:
+ * - 0b0 - T = 0 per the ISO-7816 specification.
+ * - 0b1 - T = 1 per the ISO-7816 specification.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_TTYPE field. */
+#define UART_RD_C7816_TTYPE(base) ((UART_C7816_REG(base) & UART_C7816_TTYPE_MASK) >> UART_C7816_TTYPE_SHIFT)
+#define UART_BRD_C7816_TTYPE(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT))
+
+/*! @brief Set the TTYPE field to a new value. */
+#define UART_WR_C7816_TTYPE(base, value) (UART_RMW_C7816(base, UART_C7816_TTYPE_MASK, UART_C7816_TTYPE(value)))
+#define UART_BWR_C7816_TTYPE(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_TTYPE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field INIT[2] (RW)
+ *
+ * When this field is set, all received characters are searched for a valid
+ * initial character. If an invalid initial character is identified, and ANACK is
+ * set, a NACK is sent. All received data is discarded and error flags blocked
+ * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV])
+ * until a valid initial character is detected. Upon detecting a valid initial
+ * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are
+ * automatically updated to reflect the initial character that was received. The
+ * actual INIT data value is not stored in the receive buffer. Additionally, upon
+ * detection of a valid initial character, IS7816[INITD] is set and an interrupt
+ * issued as programmed by IE7816[INITDE]. When a valid initial character is
+ * detected, INIT is automatically cleared. This Initial Character Detect feature is
+ * supported only in T = 0 protocol mode.
+ *
+ * Values:
+ * - 0b0 - Normal operating mode. Receiver does not seek to identify initial
+ *     character.
+ * - 0b1 - Receiver searches for initial character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_INIT field. */
+#define UART_RD_C7816_INIT(base) ((UART_C7816_REG(base) & UART_C7816_INIT_MASK) >> UART_C7816_INIT_SHIFT)
+#define UART_BRD_C7816_INIT(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT))
+
+/*! @brief Set the INIT field to a new value. */
+#define UART_WR_C7816_INIT(base, value) (UART_RMW_C7816(base, UART_C7816_INIT_MASK, UART_C7816_INIT(value)))
+#define UART_BWR_C7816_INIT(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_INIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ANACK[3] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a parity error occurs or if INIT is set and an invalid initial character is
+ * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART
+ * attempts to retransmit the data indefinitely. To stop retransmission attempts,
+ * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again.
+ *
+ * Values:
+ * - 0b0 - No NACK is automatically generated.
+ * - 0b1 - A NACK is automatically generated if a parity error is detected or if
+ *     an invalid initial character is detected.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ANACK field. */
+#define UART_RD_C7816_ANACK(base) ((UART_C7816_REG(base) & UART_C7816_ANACK_MASK) >> UART_C7816_ANACK_SHIFT)
+#define UART_BRD_C7816_ANACK(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT))
+
+/*! @brief Set the ANACK field to a new value. */
+#define UART_WR_C7816_ANACK(base, value) (UART_RMW_C7816(base, UART_C7816_ANACK_MASK, UART_C7816_ANACK(value)))
+#define UART_BWR_C7816_ANACK(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ANACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_C7816, field ONACK[4] (RW)
+ *
+ * When this field is set, the receiver automatically generates a NACK response
+ * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems,
+ * this results in the transmitter resending the packet that overflowed until the
+ * retransmit threshold for that transmitter is reached. A NACK is generated only
+ * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK
+ * considerations
+ *
+ * Values:
+ * - 0b0 - The received data does not generate a NACK when the receipt of the
+ *     data results in an overflow event.
+ * - 0b1 - If the receiver buffer overflows, a NACK is automatically sent on a
+ *     received character.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_C7816_ONACK field. */
+#define UART_RD_C7816_ONACK(base) ((UART_C7816_REG(base) & UART_C7816_ONACK_MASK) >> UART_C7816_ONACK_SHIFT)
+#define UART_BRD_C7816_ONACK(base) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT))
+
+/*! @brief Set the ONACK field to a new value. */
+#define UART_WR_C7816_ONACK(base, value) (UART_RMW_C7816(base, UART_C7816_ONACK_MASK, UART_C7816_ONACK(value)))
+#define UART_BWR_C7816_ONACK(base, value) (BITBAND_ACCESS8(&UART_C7816_REG(base), UART_C7816_ONACK_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IE7816 - UART 7816 Interrupt Enable Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IE7816 - UART 7816 Interrupt Enable Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IE7816 register controls which flags result in an interrupt being issued.
+ * This register is specific to 7816 functionality, the corresponding flags that
+ * drive the interrupts are not asserted when 7816E is not set/enabled. However,
+ * these flags may remain set if they are asserted while 7816E was set and not
+ * subsequently cleared. This register may be read or written to at any time.
+ */
+/*!
+ * @name Constants and macros for entire UART_IE7816 register
+ */
+/*@{*/
+#define UART_RD_IE7816(base)     (UART_IE7816_REG(base))
+#define UART_WR_IE7816(base, value) (UART_IE7816_REG(base) = (value))
+#define UART_RMW_IE7816(base, mask, value) (UART_WR_IE7816(base, (UART_RD_IE7816(base) & ~(mask)) | (value)))
+#define UART_SET_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) |  (value)))
+#define UART_CLR_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) & ~(value)))
+#define UART_TOG_IE7816(base, value) (UART_WR_IE7816(base, UART_RD_IE7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IE7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IE7816, field RXTE[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[RXT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[RXT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_RXTE field. */
+#define UART_RD_IE7816_RXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_RXTE_MASK) >> UART_IE7816_RXTE_SHIFT)
+#define UART_BRD_IE7816_RXTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT))
+
+/*! @brief Set the RXTE field to a new value. */
+#define UART_WR_IE7816_RXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_RXTE_MASK, UART_IE7816_RXTE(value)))
+#define UART_BWR_IE7816_RXTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_RXTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field TXTE[1] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[TXT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[TXT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_TXTE field. */
+#define UART_RD_IE7816_TXTE(base) ((UART_IE7816_REG(base) & UART_IE7816_TXTE_MASK) >> UART_IE7816_TXTE_SHIFT)
+#define UART_BRD_IE7816_TXTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT))
+
+/*! @brief Set the TXTE field to a new value. */
+#define UART_WR_IE7816_TXTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_TXTE_MASK, UART_IE7816_TXTE(value)))
+#define UART_BWR_IE7816_TXTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_TXTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field GTVE[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[GTV] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[GTV] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_GTVE field. */
+#define UART_RD_IE7816_GTVE(base) ((UART_IE7816_REG(base) & UART_IE7816_GTVE_MASK) >> UART_IE7816_GTVE_SHIFT)
+#define UART_BRD_IE7816_GTVE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT))
+
+/*! @brief Set the GTVE field to a new value. */
+#define UART_WR_IE7816_GTVE(base, value) (UART_RMW_IE7816(base, UART_IE7816_GTVE_MASK, UART_IE7816_GTVE(value)))
+#define UART_BWR_IE7816_GTVE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_GTVE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field INITDE[4] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[INITD] does not result in the generation of
+ *     an interrupt.
+ * - 0b1 - The assertion of IS7816[INITD] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_INITDE field. */
+#define UART_RD_IE7816_INITDE(base) ((UART_IE7816_REG(base) & UART_IE7816_INITDE_MASK) >> UART_IE7816_INITDE_SHIFT)
+#define UART_BRD_IE7816_INITDE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT))
+
+/*! @brief Set the INITDE field to a new value. */
+#define UART_WR_IE7816_INITDE(base, value) (UART_RMW_IE7816(base, UART_IE7816_INITDE_MASK, UART_IE7816_INITDE(value)))
+#define UART_BWR_IE7816_INITDE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_INITDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field BWTE[5] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[BWT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[BWT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_BWTE field. */
+#define UART_RD_IE7816_BWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_BWTE_MASK) >> UART_IE7816_BWTE_SHIFT)
+#define UART_BRD_IE7816_BWTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT))
+
+/*! @brief Set the BWTE field to a new value. */
+#define UART_WR_IE7816_BWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_BWTE_MASK, UART_IE7816_BWTE(value)))
+#define UART_BWR_IE7816_BWTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_BWTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field CWTE[6] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[CWT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[CWT] results in the generation of an
+ *     interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_CWTE field. */
+#define UART_RD_IE7816_CWTE(base) ((UART_IE7816_REG(base) & UART_IE7816_CWTE_MASK) >> UART_IE7816_CWTE_SHIFT)
+#define UART_BRD_IE7816_CWTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT))
+
+/*! @brief Set the CWTE field to a new value. */
+#define UART_WR_IE7816_CWTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_CWTE_MASK, UART_IE7816_CWTE(value)))
+#define UART_BWR_IE7816_CWTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_CWTE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IE7816, field WTE[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The assertion of IS7816[WT] does not result in the generation of an
+ *     interrupt.
+ * - 0b1 - The assertion of IS7816[WT] results in the generation of an interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IE7816_WTE field. */
+#define UART_RD_IE7816_WTE(base) ((UART_IE7816_REG(base) & UART_IE7816_WTE_MASK) >> UART_IE7816_WTE_SHIFT)
+#define UART_BRD_IE7816_WTE(base) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT))
+
+/*! @brief Set the WTE field to a new value. */
+#define UART_WR_IE7816_WTE(base, value) (UART_RMW_IE7816(base, UART_IE7816_WTE_MASK, UART_IE7816_WTE(value)))
+#define UART_BWR_IE7816_WTE(base, value) (BITBAND_ACCESS8(&UART_IE7816_REG(base), UART_IE7816_WTE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_IS7816 - UART 7816 Interrupt Status Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_IS7816 - UART 7816 Interrupt Status Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The IS7816 register provides a mechanism to read and clear the interrupt
+ * flags. All flags/interrupts are cleared by writing a 1 to the field location.
+ * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only
+ * the flag condition that occurred since the last time the bit was cleared, not
+ * that the condition currently exists. The status flags are set regardless of
+ * whether the corresponding field in the IE7816 is set or cleared. The IE7816
+ * controls only if an interrupt is issued to the host processor. This register is
+ * specific to 7816 functionality and the values in this register have no affect on
+ * UART operation and should be ignored if 7816E is not set/enabled. This
+ * register may be read or written at anytime.
+ */
+/*!
+ * @name Constants and macros for entire UART_IS7816 register
+ */
+/*@{*/
+#define UART_RD_IS7816(base)     (UART_IS7816_REG(base))
+#define UART_WR_IS7816(base, value) (UART_IS7816_REG(base) = (value))
+#define UART_RMW_IS7816(base, mask, value) (UART_WR_IS7816(base, (UART_RD_IS7816(base) & ~(mask)) | (value)))
+#define UART_SET_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) |  (value)))
+#define UART_CLR_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) & ~(value)))
+#define UART_TOG_IS7816(base, value) (UART_WR_IS7816(base, UART_RD_IS7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_IS7816 bitfields
+ */
+
+/*!
+ * @name Register UART_IS7816, field RXT[0] (W1C)
+ *
+ * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS
+ * generated in response to parity errors on received data. This flag requires ANACK
+ * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0.
+ * Clearing this field also resets the counter keeping track of consecutive NACKS. The
+ * UART will continue to attempt to receive data regardless of whether this flag
+ * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1,
+ * or packet is received without needing to issue a NACK, the internal NACK
+ * detection counter is cleared and the count restarts from zero on the next
+ * transmitted NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - The number of consecutive NACKS generated as a result of parity
+ *     errors and buffer overruns is less than or equal to the value in
+ *     ET7816[RXTHRESHOLD].
+ * - 0b1 - The number of consecutive NACKS generated as a result of parity
+ *     errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_RXT field. */
+#define UART_RD_IS7816_RXT(base) ((UART_IS7816_REG(base) & UART_IS7816_RXT_MASK) >> UART_IS7816_RXT_SHIFT)
+#define UART_BRD_IS7816_RXT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT))
+
+/*! @brief Set the RXT field to a new value. */
+#define UART_WR_IS7816_RXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_RXT(value)))
+#define UART_BWR_IS7816_RXT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_RXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field TXT[1] (W1C)
+ *
+ * Indicates that the transmit NACK threshold has been exceeded as indicated by
+ * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART
+ * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If
+ * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is
+ * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the
+ * internal NACK detection counter is cleared and the count restarts from zero on
+ * the next received NACK. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - The number of retries and corresponding NACKS does not exceed the
+ *     value in ET7816[TXTHRESHOLD].
+ * - 0b1 - The number of retries and corresponding NACKS exceeds the value in
+ *     ET7816[TXTHRESHOLD].
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_TXT field. */
+#define UART_RD_IS7816_TXT(base) ((UART_IS7816_REG(base) & UART_IS7816_TXT_MASK) >> UART_IS7816_TXT_SHIFT)
+#define UART_BRD_IS7816_TXT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT))
+
+/*! @brief Set the TXT field to a new value. */
+#define UART_WR_IS7816_TXT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_TXT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_TXT(value)))
+#define UART_BWR_IS7816_TXT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_TXT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field GTV[2] (W1C)
+ *
+ * Indicates that one or more of the character guard time, block guard time, or
+ * guard time are violated. This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - A guard time (GT, CGT, or BGT) has not been violated.
+ * - 0b1 - A guard time (GT, CGT, or BGT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_GTV field. */
+#define UART_RD_IS7816_GTV(base) ((UART_IS7816_REG(base) & UART_IS7816_GTV_MASK) >> UART_IS7816_GTV_SHIFT)
+#define UART_BRD_IS7816_GTV(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT))
+
+/*! @brief Set the GTV field to a new value. */
+#define UART_WR_IS7816_GTV(base, value) (UART_RMW_IS7816(base, (UART_IS7816_GTV_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_GTV(value)))
+#define UART_BWR_IS7816_GTV(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_GTV_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field INITD[4] (W1C)
+ *
+ * Indicates that a valid initial character is received. This interrupt is
+ * cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - A valid initial character has not been received.
+ * - 0b1 - A valid initial character has been received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_INITD field. */
+#define UART_RD_IS7816_INITD(base) ((UART_IS7816_REG(base) & UART_IS7816_INITD_MASK) >> UART_IS7816_INITD_SHIFT)
+#define UART_BRD_IS7816_INITD(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT))
+
+/*! @brief Set the INITD field to a new value. */
+#define UART_WR_IS7816_INITD(base, value) (UART_RMW_IS7816(base, (UART_IS7816_INITD_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_INITD(value)))
+#define UART_BWR_IS7816_INITD(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_INITD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field BWT[5] (W1C)
+ *
+ * Indicates that the block wait time, the time between the leading edge of
+ * first received character of a block and the leading edge of the last character the
+ * previously transmitted block, has exceeded the programmed value. This flag
+ * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - Block wait time (BWT) has not been violated.
+ * - 0b1 - Block wait time (BWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_BWT field. */
+#define UART_RD_IS7816_BWT(base) ((UART_IS7816_REG(base) & UART_IS7816_BWT_MASK) >> UART_IS7816_BWT_SHIFT)
+#define UART_BRD_IS7816_BWT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT))
+
+/*! @brief Set the BWT field to a new value. */
+#define UART_WR_IS7816_BWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_BWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_CWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_BWT(value)))
+#define UART_BWR_IS7816_BWT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_BWT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field CWT[6] (W1C)
+ *
+ * Indicates that the character wait time, the time between the leading edges of
+ * two consecutive characters in a block, has exceeded the programmed value.
+ * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by
+ * writing 1.
+ *
+ * Values:
+ * - 0b0 - Character wait time (CWT) has not been violated.
+ * - 0b1 - Character wait time (CWT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_CWT field. */
+#define UART_RD_IS7816_CWT(base) ((UART_IS7816_REG(base) & UART_IS7816_CWT_MASK) >> UART_IS7816_CWT_SHIFT)
+#define UART_BRD_IS7816_CWT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT))
+
+/*! @brief Set the CWT field to a new value. */
+#define UART_WR_IS7816_CWT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_CWT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_WT_MASK), UART_IS7816_CWT(value)))
+#define UART_BWR_IS7816_CWT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_CWT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register UART_IS7816, field WT[7] (W1C)
+ *
+ * Indicates that the wait time, the time between the leading edge of a
+ * character being transmitted and the leading edge of the next response character, has
+ * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0.
+ * This interrupt is cleared by writing 1.
+ *
+ * Values:
+ * - 0b0 - Wait time (WT) has not been violated.
+ * - 0b1 - Wait time (WT) has been violated.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_IS7816_WT field. */
+#define UART_RD_IS7816_WT(base) ((UART_IS7816_REG(base) & UART_IS7816_WT_MASK) >> UART_IS7816_WT_SHIFT)
+#define UART_BRD_IS7816_WT(base) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT))
+
+/*! @brief Set the WT field to a new value. */
+#define UART_WR_IS7816_WT(base, value) (UART_RMW_IS7816(base, (UART_IS7816_WT_MASK | UART_IS7816_RXT_MASK | UART_IS7816_TXT_MASK | UART_IS7816_GTV_MASK | UART_IS7816_INITD_MASK | UART_IS7816_BWT_MASK | UART_IS7816_CWT_MASK), UART_IS7816_WT(value)))
+#define UART_BWR_IS7816_WT(base, value) (BITBAND_ACCESS8(&UART_IS7816_REG(base), UART_IS7816_WT_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816T0 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816T0 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816T0 register
+ */
+/*@{*/
+#define UART_RD_WP7816T0(base)   (UART_WP7816T0_REG(base))
+#define UART_WR_WP7816T0(base, value) (UART_WP7816T0_REG(base) = (value))
+#define UART_RMW_WP7816T0(base, mask, value) (UART_WR_WP7816T0(base, (UART_RD_WP7816T0(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) |  (value)))
+#define UART_CLR_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) & ~(value)))
+#define UART_TOG_WP7816T0(base, value) (UART_WR_WP7816T0(base, UART_RD_WP7816T0(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WP7816T1 - UART 7816 Wait Parameter Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WP7816T1 - UART 7816 Wait Parameter Register (RW)
+ *
+ * Reset value: 0x0AU
+ *
+ * The WP7816 register contains constants used in the generation of various wait
+ * timer counters. To save register space, this register is used differently
+ * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WP7816T1 register
+ */
+/*@{*/
+#define UART_RD_WP7816T1(base)   (UART_WP7816T1_REG(base))
+#define UART_WR_WP7816T1(base, value) (UART_WP7816T1_REG(base) = (value))
+#define UART_RMW_WP7816T1(base, mask, value) (UART_WR_WP7816T1(base, (UART_RD_WP7816T1(base) & ~(mask)) | (value)))
+#define UART_SET_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) |  (value)))
+#define UART_CLR_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) & ~(value)))
+#define UART_TOG_WP7816T1(base, value) (UART_WR_WP7816T1(base, UART_RD_WP7816T1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_WP7816T1 bitfields
+ */
+
+/*!
+ * @name Register UART_WP7816T1, field BWI[3:0] (RW)
+ *
+ * Used to calculate the value used for the BWT counter. It represent a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816T1_BWI field. */
+#define UART_RD_WP7816T1_BWI(base) ((UART_WP7816T1_REG(base) & UART_WP7816T1_BWI_MASK) >> UART_WP7816T1_BWI_SHIFT)
+#define UART_BRD_WP7816T1_BWI(base) (UART_RD_WP7816T1_BWI(base))
+
+/*! @brief Set the BWI field to a new value. */
+#define UART_WR_WP7816T1_BWI(base, value) (UART_RMW_WP7816T1(base, UART_WP7816T1_BWI_MASK, UART_WP7816T1_BWI(value)))
+#define UART_BWR_WP7816T1_BWI(base, value) (UART_WR_WP7816T1_BWI(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_WP7816T1, field CWI[7:4] (RW)
+ *
+ * Used to calculate the value used for the CWT counter. It represents a value
+ * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time
+ * and guard time parameters .
+ */
+/*@{*/
+/*! @brief Read current value of the UART_WP7816T1_CWI field. */
+#define UART_RD_WP7816T1_CWI(base) ((UART_WP7816T1_REG(base) & UART_WP7816T1_CWI_MASK) >> UART_WP7816T1_CWI_SHIFT)
+#define UART_BRD_WP7816T1_CWI(base) (UART_RD_WP7816T1_CWI(base))
+
+/*! @brief Set the CWI field to a new value. */
+#define UART_WR_WP7816T1_CWI(base, value) (UART_RMW_WP7816T1(base, UART_WP7816T1_CWI_MASK, UART_WP7816T1_CWI(value)))
+#define UART_BWR_WP7816T1_CWI(base, value) (UART_WR_WP7816T1_CWI(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WN7816 - UART 7816 Wait N Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WN7816 - UART 7816 Wait N Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The WN7816 register contains a parameter that is used in the calculation of
+ * the guard time counter. This register may be read at any time. This register
+ * must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WN7816 register
+ */
+/*@{*/
+#define UART_RD_WN7816(base)     (UART_WN7816_REG(base))
+#define UART_WR_WN7816(base, value) (UART_WN7816_REG(base) = (value))
+#define UART_RMW_WN7816(base, mask, value) (UART_WR_WN7816(base, (UART_RD_WN7816(base) & ~(mask)) | (value)))
+#define UART_SET_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) |  (value)))
+#define UART_CLR_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) & ~(value)))
+#define UART_TOG_WN7816(base, value) (UART_WR_WN7816(base, UART_RD_WN7816(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_WF7816 - UART 7816 Wait FD Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_WF7816 - UART 7816 Wait FD Register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * The WF7816 contains parameters that are used in the generation of various
+ * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any
+ * time. This register must be written to only when C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_WF7816 register
+ */
+/*@{*/
+#define UART_RD_WF7816(base)     (UART_WF7816_REG(base))
+#define UART_WR_WF7816(base, value) (UART_WF7816_REG(base) = (value))
+#define UART_RMW_WF7816(base, mask, value) (UART_WR_WF7816(base, (UART_RD_WF7816(base) & ~(mask)) | (value)))
+#define UART_SET_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) |  (value)))
+#define UART_CLR_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) & ~(value)))
+#define UART_TOG_WF7816(base, value) (UART_WR_WF7816(base, UART_RD_WF7816(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * UART_ET7816 - UART 7816 Error Threshold Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_ET7816 - UART 7816 Error Threshold Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The ET7816 register contains fields that determine the number of NACKs that
+ * must be received or transmitted before the host processor is notified. This
+ * register may be read at anytime. This register must be written to only when
+ * C7816[ISO_7816E] is not set.
+ */
+/*!
+ * @name Constants and macros for entire UART_ET7816 register
+ */
+/*@{*/
+#define UART_RD_ET7816(base)     (UART_ET7816_REG(base))
+#define UART_WR_ET7816(base, value) (UART_ET7816_REG(base) = (value))
+#define UART_RMW_ET7816(base, mask, value) (UART_WR_ET7816(base, (UART_RD_ET7816(base) & ~(mask)) | (value)))
+#define UART_SET_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) |  (value)))
+#define UART_CLR_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) & ~(value)))
+#define UART_TOG_ET7816(base, value) (UART_WR_ET7816(base, UART_RD_ET7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual UART_ET7816 bitfields
+ */
+
+/*!
+ * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW)
+ *
+ * The value written to this field indicates the maximum number of consecutive
+ * NACKs generated as a result of a parity error or receiver buffer overruns
+ * before the host processor is notified. After the counter exceeds that value in the
+ * field, the IS7816[RXT] is asserted. This field is meaningful only when
+ * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive
+ * NACKs that have been transmitted since the last successful reception. This
+ * counter saturates at 4'hF and does not wrap around. Regardless of the number of
+ * NACKs sent, the UART continues to receive valid packets indefinitely. For
+ * additional information, see IS7816[RXT] field description.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */
+#define UART_RD_ET7816_RXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_RXTHRESHOLD_MASK) >> UART_ET7816_RXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_RXTHRESHOLD(base) (UART_RD_ET7816_RXTHRESHOLD(base))
+
+/*! @brief Set the RXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_RXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_RXTHRESHOLD_MASK, UART_ET7816_RXTHRESHOLD(value)))
+#define UART_BWR_ET7816_RXTHRESHOLD(base, value) (UART_WR_ET7816_RXTHRESHOLD(base, value))
+/*@}*/
+
+/*!
+ * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW)
+ *
+ * The value written to this field indicates the maximum number of failed
+ * attempts (NACKs) a transmitted character can have before the host processor is
+ * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1.
+ * The value read from this field represents the number of consecutive NACKs
+ * that have been received since the last successful transmission. This counter
+ * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are
+ * received, the UART continues to retransmit indefinitely. This flag only
+ * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field
+ * description.
+ *
+ * Values:
+ * - 0b0000 - TXT asserts on the first NACK that is received.
+ * - 0b0001 - TXT asserts on the second NACK that is received.
+ */
+/*@{*/
+/*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */
+#define UART_RD_ET7816_TXTHRESHOLD(base) ((UART_ET7816_REG(base) & UART_ET7816_TXTHRESHOLD_MASK) >> UART_ET7816_TXTHRESHOLD_SHIFT)
+#define UART_BRD_ET7816_TXTHRESHOLD(base) (UART_RD_ET7816_TXTHRESHOLD(base))
+
+/*! @brief Set the TXTHRESHOLD field to a new value. */
+#define UART_WR_ET7816_TXTHRESHOLD(base, value) (UART_RMW_ET7816(base, UART_ET7816_TXTHRESHOLD_MASK, UART_ET7816_TXTHRESHOLD(value)))
+#define UART_BWR_ET7816_TXTHRESHOLD(base, value) (UART_WR_ET7816_TXTHRESHOLD(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * UART_TL7816 - UART 7816 Transmit Length Register
+ ******************************************************************************/
+
+/*!
+ * @brief UART_TL7816 - UART 7816 Transmit Length Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The TL7816 register is used to indicate the number of characters contained in
+ * the block being transmitted. This register is used only when C7816[TTYPE] =
+ * 1. This register may be read at anytime. This register must be written only
+ * when C2[TE] is not enabled.
+ */
+/*!
+ * @name Constants and macros for entire UART_TL7816 register
+ */
+/*@{*/
+#define UART_RD_TL7816(base)     (UART_TL7816_REG(base))
+#define UART_WR_TL7816(base, value) (UART_TL7816_REG(base) = (value))
+#define UART_RMW_TL7816(base, mask, value) (UART_WR_TL7816(base, (UART_RD_TL7816(base) & ~(mask)) | (value)))
+#define UART_SET_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) |  (value)))
+#define UART_CLR_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) & ~(value)))
+#define UART_TOG_TL7816(base, value) (UART_WR_TL7816(base, UART_RD_TL7816(base) ^  (value)))
+/*@}*/
+
+/*
+ * MK64F12 USB
+ *
+ * Universal Serial Bus, OTG Capable Controller
+ *
+ * Registers defined in this header file:
+ * - USB_PERID - Peripheral ID register
+ * - USB_IDCOMP - Peripheral ID Complement register
+ * - USB_REV - Peripheral Revision register
+ * - USB_ADDINFO - Peripheral Additional Info register
+ * - USB_OTGISTAT - OTG Interrupt Status register
+ * - USB_OTGICR - OTG Interrupt Control register
+ * - USB_OTGSTAT - OTG Status register
+ * - USB_OTGCTL - OTG Control register
+ * - USB_ISTAT - Interrupt Status register
+ * - USB_INTEN - Interrupt Enable register
+ * - USB_ERRSTAT - Error Interrupt Status register
+ * - USB_ERREN - Error Interrupt Enable register
+ * - USB_STAT - Status register
+ * - USB_CTL - Control register
+ * - USB_ADDR - Address register
+ * - USB_BDTPAGE1 - BDT Page register 1
+ * - USB_FRMNUML - Frame Number register Low
+ * - USB_FRMNUMH - Frame Number register High
+ * - USB_TOKEN - Token register
+ * - USB_SOFTHLD - SOF Threshold register
+ * - USB_BDTPAGE2 - BDT Page Register 2
+ * - USB_BDTPAGE3 - BDT Page Register 3
+ * - USB_ENDPT - Endpoint Control register
+ * - USB_USBCTRL - USB Control register
+ * - USB_OBSERVE - USB OTG Observe register
+ * - USB_CONTROL - USB OTG Control register
+ * - USB_USBTRC0 - USB Transceiver Control register 0
+ * - USB_USBFRMADJUST - Frame Adjust Register
+ * - USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ * - USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ * - USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ */
+
+#define USB_INSTANCE_COUNT (1U) /*!< Number of instances of the USB module. */
+#define USB0_IDX (0U) /*!< Instance number for USB0. */
+
+/*******************************************************************************
+ * USB_PERID - Peripheral ID register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_PERID - Peripheral ID register (RO)
+ *
+ * Reset value: 0x04U
+ *
+ * Reads back the value of 0x04. This value is defined for the USB peripheral.
+ */
+/*!
+ * @name Constants and macros for entire USB_PERID register
+ */
+/*@{*/
+#define USB_RD_PERID(base)       (USB_PERID_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_PERID bitfields
+ */
+
+/*!
+ * @name Register USB_PERID, field ID[5:0] (RO)
+ *
+ * This field always reads 0x4h.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_PERID_ID field. */
+#define USB_RD_PERID_ID(base) ((USB_PERID_REG(base) & USB_PERID_ID_MASK) >> USB_PERID_ID_SHIFT)
+#define USB_BRD_PERID_ID(base) (USB_RD_PERID_ID(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_IDCOMP - Peripheral ID Complement register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_IDCOMP - Peripheral ID Complement register (RO)
+ *
+ * Reset value: 0xFBU
+ *
+ * Reads back the complement of the Peripheral ID register. For the USB
+ * peripheral, the value is 0xFB.
+ */
+/*!
+ * @name Constants and macros for entire USB_IDCOMP register
+ */
+/*@{*/
+#define USB_RD_IDCOMP(base)      (USB_IDCOMP_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_IDCOMP bitfields
+ */
+
+/*!
+ * @name Register USB_IDCOMP, field NID[5:0] (RO)
+ *
+ * Ones' complement of PERID[ID]. bits.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_IDCOMP_NID field. */
+#define USB_RD_IDCOMP_NID(base) ((USB_IDCOMP_REG(base) & USB_IDCOMP_NID_MASK) >> USB_IDCOMP_NID_SHIFT)
+#define USB_BRD_IDCOMP_NID(base) (USB_RD_IDCOMP_NID(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_REV - Peripheral Revision register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_REV - Peripheral Revision register (RO)
+ *
+ * Reset value: 0x33U
+ *
+ * Contains the revision number of the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_REV register
+ */
+/*@{*/
+#define USB_RD_REV(base)         (USB_REV_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDINFO - Peripheral Additional Info register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDINFO - Peripheral Additional Info register (RO)
+ *
+ * Reset value: 0x01U
+ *
+ * Reads back the value of the fixed Interrupt Request Level (IRQNUM) along with
+ * the Host Enable bit.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDINFO register
+ */
+/*@{*/
+#define USB_RD_ADDINFO(base)     (USB_ADDINFO_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDINFO bitfields
+ */
+
+/*!
+ * @name Register USB_ADDINFO, field IEHOST[0] (RO)
+ *
+ * This bit is set if host mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IEHOST field. */
+#define USB_RD_ADDINFO_IEHOST(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IEHOST_MASK) >> USB_ADDINFO_IEHOST_SHIFT)
+#define USB_BRD_ADDINFO_IEHOST(base) (BITBAND_ACCESS8(&USB_ADDINFO_REG(base), USB_ADDINFO_IEHOST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_ADDINFO, field IRQNUM[7:3] (RO)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDINFO_IRQNUM field. */
+#define USB_RD_ADDINFO_IRQNUM(base) ((USB_ADDINFO_REG(base) & USB_ADDINFO_IRQNUM_MASK) >> USB_ADDINFO_IRQNUM_SHIFT)
+#define USB_BRD_ADDINFO_IRQNUM(base) (USB_RD_ADDINFO_IRQNUM(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGISTAT - OTG Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGISTAT - OTG Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Records changes of the ID sense and VBUS signals. Software can read this
+ * register to determine the event that triggers an interrupt. Only bits that have
+ * changed since the last software read are set. Writing a one to a bit clears the
+ * associated interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGISTAT register
+ */
+/*@{*/
+#define USB_RD_OTGISTAT(base)    (USB_OTGISTAT_REG(base))
+#define USB_WR_OTGISTAT(base, value) (USB_OTGISTAT_REG(base) = (value))
+#define USB_RMW_OTGISTAT(base, mask, value) (USB_WR_OTGISTAT(base, (USB_RD_OTGISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) |  (value)))
+#define USB_CLR_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) & ~(value)))
+#define USB_TOG_OTGISTAT(base, value) (USB_WR_OTGISTAT(base, USB_RD_OTGISTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGISTAT, field AVBUSCHG[0] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on an A device.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_AVBUSCHG field. */
+#define USB_RD_OTGISTAT_AVBUSCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_AVBUSCHG_MASK) >> USB_OTGISTAT_AVBUSCHG_SHIFT)
+#define USB_BRD_OTGISTAT_AVBUSCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_AVBUSCHG_SHIFT))
+
+/*! @brief Set the AVBUSCHG field to a new value. */
+#define USB_WR_OTGISTAT_AVBUSCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_AVBUSCHG_MASK, USB_OTGISTAT_AVBUSCHG(value)))
+#define USB_BWR_OTGISTAT_AVBUSCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_AVBUSCHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field B_SESS_CHG[2] (RW)
+ *
+ * This bit is set when a change in VBUS is detected on a B device.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_B_SESS_CHG field. */
+#define USB_RD_OTGISTAT_B_SESS_CHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_B_SESS_CHG_MASK) >> USB_OTGISTAT_B_SESS_CHG_SHIFT)
+#define USB_BRD_OTGISTAT_B_SESS_CHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_B_SESS_CHG_SHIFT))
+
+/*! @brief Set the B_SESS_CHG field to a new value. */
+#define USB_WR_OTGISTAT_B_SESS_CHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_B_SESS_CHG_MASK, USB_OTGISTAT_B_SESS_CHG(value)))
+#define USB_BWR_OTGISTAT_B_SESS_CHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_B_SESS_CHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field SESSVLDCHG[3] (RW)
+ *
+ * This bit is set when a change in VBUS is detected indicating a session valid
+ * or a session no longer valid.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_SESSVLDCHG field. */
+#define USB_RD_OTGISTAT_SESSVLDCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_SESSVLDCHG_MASK) >> USB_OTGISTAT_SESSVLDCHG_SHIFT)
+#define USB_BRD_OTGISTAT_SESSVLDCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_SESSVLDCHG_SHIFT))
+
+/*! @brief Set the SESSVLDCHG field to a new value. */
+#define USB_WR_OTGISTAT_SESSVLDCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_SESSVLDCHG_MASK, USB_OTGISTAT_SESSVLDCHG(value)))
+#define USB_BWR_OTGISTAT_SESSVLDCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_SESSVLDCHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field LINE_STATE_CHG[5] (RW)
+ *
+ * This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits)
+ * are stable without change for 1 millisecond, and the value of the line state
+ * is different from the last time when the line state was stable. It is set on
+ * transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
+ * Changes in J-state while SE0 is true do not cause an interrupt. This interrupt
+ * can be used in detecting Reset, Resume, Connect, and Data Line Pulse
+ * signaling.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_LINE_STATE_CHG field. */
+#define USB_RD_OTGISTAT_LINE_STATE_CHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_LINE_STATE_CHG_MASK) >> USB_OTGISTAT_LINE_STATE_CHG_SHIFT)
+#define USB_BRD_OTGISTAT_LINE_STATE_CHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_LINE_STATE_CHG_SHIFT))
+
+/*! @brief Set the LINE_STATE_CHG field to a new value. */
+#define USB_WR_OTGISTAT_LINE_STATE_CHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_LINE_STATE_CHG_MASK, USB_OTGISTAT_LINE_STATE_CHG(value)))
+#define USB_BWR_OTGISTAT_LINE_STATE_CHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_LINE_STATE_CHG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field ONEMSEC[6] (RW)
+ *
+ * This bit is set when the 1 millisecond timer expires. This bit stays asserted
+ * until cleared by software. The interrupt must be serviced every millisecond
+ * to avoid losing 1msec counts.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_ONEMSEC field. */
+#define USB_RD_OTGISTAT_ONEMSEC(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_ONEMSEC_MASK) >> USB_OTGISTAT_ONEMSEC_SHIFT)
+#define USB_BRD_OTGISTAT_ONEMSEC(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_ONEMSEC_SHIFT))
+
+/*! @brief Set the ONEMSEC field to a new value. */
+#define USB_WR_OTGISTAT_ONEMSEC(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_ONEMSEC_MASK, USB_OTGISTAT_ONEMSEC(value)))
+#define USB_BWR_OTGISTAT_ONEMSEC(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_ONEMSEC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGISTAT, field IDCHG[7] (RW)
+ *
+ * This bit is set when a change in the ID Signal from the USB connector is
+ * sensed.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGISTAT_IDCHG field. */
+#define USB_RD_OTGISTAT_IDCHG(base) ((USB_OTGISTAT_REG(base) & USB_OTGISTAT_IDCHG_MASK) >> USB_OTGISTAT_IDCHG_SHIFT)
+#define USB_BRD_OTGISTAT_IDCHG(base) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_IDCHG_SHIFT))
+
+/*! @brief Set the IDCHG field to a new value. */
+#define USB_WR_OTGISTAT_IDCHG(base, value) (USB_RMW_OTGISTAT(base, USB_OTGISTAT_IDCHG_MASK, USB_OTGISTAT_IDCHG(value)))
+#define USB_BWR_OTGISTAT_IDCHG(base, value) (BITBAND_ACCESS8(&USB_OTGISTAT_REG(base), USB_OTGISTAT_IDCHG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGICR - OTG Interrupt Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGICR - OTG Interrupt Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Enables the corresponding interrupt status bits defined in the OTG Interrupt
+ * Status Register.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGICR register
+ */
+/*@{*/
+#define USB_RD_OTGICR(base)      (USB_OTGICR_REG(base))
+#define USB_WR_OTGICR(base, value) (USB_OTGICR_REG(base) = (value))
+#define USB_RMW_OTGICR(base, mask, value) (USB_WR_OTGICR(base, (USB_RD_OTGICR(base) & ~(mask)) | (value)))
+#define USB_SET_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) |  (value)))
+#define USB_CLR_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) & ~(value)))
+#define USB_TOG_OTGICR(base, value) (USB_WR_OTGICR(base, USB_RD_OTGICR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGICR bitfields
+ */
+
+/*!
+ * @name Register USB_OTGICR, field AVBUSEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the AVBUSCHG interrupt.
+ * - 0b1 - Enables the AVBUSCHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_AVBUSEN field. */
+#define USB_RD_OTGICR_AVBUSEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_AVBUSEN_MASK) >> USB_OTGICR_AVBUSEN_SHIFT)
+#define USB_BRD_OTGICR_AVBUSEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_AVBUSEN_SHIFT))
+
+/*! @brief Set the AVBUSEN field to a new value. */
+#define USB_WR_OTGICR_AVBUSEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_AVBUSEN_MASK, USB_OTGICR_AVBUSEN(value)))
+#define USB_BWR_OTGICR_AVBUSEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_AVBUSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field BSESSEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the B_SESS_CHG interrupt.
+ * - 0b1 - Enables the B_SESS_CHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_BSESSEN field. */
+#define USB_RD_OTGICR_BSESSEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_BSESSEN_MASK) >> USB_OTGICR_BSESSEN_SHIFT)
+#define USB_BRD_OTGICR_BSESSEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_BSESSEN_SHIFT))
+
+/*! @brief Set the BSESSEN field to a new value. */
+#define USB_WR_OTGICR_BSESSEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_BSESSEN_MASK, USB_OTGICR_BSESSEN(value)))
+#define USB_BWR_OTGICR_BSESSEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_BSESSEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field SESSVLDEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the SESSVLDCHG interrupt.
+ * - 0b1 - Enables the SESSVLDCHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_SESSVLDEN field. */
+#define USB_RD_OTGICR_SESSVLDEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_SESSVLDEN_MASK) >> USB_OTGICR_SESSVLDEN_SHIFT)
+#define USB_BRD_OTGICR_SESSVLDEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_SESSVLDEN_SHIFT))
+
+/*! @brief Set the SESSVLDEN field to a new value. */
+#define USB_WR_OTGICR_SESSVLDEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_SESSVLDEN_MASK, USB_OTGICR_SESSVLDEN(value)))
+#define USB_BWR_OTGICR_SESSVLDEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_SESSVLDEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field LINESTATEEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the LINE_STAT_CHG interrupt.
+ * - 0b1 - Enables the LINE_STAT_CHG interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_LINESTATEEN field. */
+#define USB_RD_OTGICR_LINESTATEEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_LINESTATEEN_MASK) >> USB_OTGICR_LINESTATEEN_SHIFT)
+#define USB_BRD_OTGICR_LINESTATEEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_LINESTATEEN_SHIFT))
+
+/*! @brief Set the LINESTATEEN field to a new value. */
+#define USB_WR_OTGICR_LINESTATEEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_LINESTATEEN_MASK, USB_OTGICR_LINESTATEEN(value)))
+#define USB_BWR_OTGICR_LINESTATEEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_LINESTATEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field ONEMSECEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Diables the 1ms timer interrupt.
+ * - 0b1 - Enables the 1ms timer interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_ONEMSECEN field. */
+#define USB_RD_OTGICR_ONEMSECEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_ONEMSECEN_MASK) >> USB_OTGICR_ONEMSECEN_SHIFT)
+#define USB_BRD_OTGICR_ONEMSECEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_ONEMSECEN_SHIFT))
+
+/*! @brief Set the ONEMSECEN field to a new value. */
+#define USB_WR_OTGICR_ONEMSECEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_ONEMSECEN_MASK, USB_OTGICR_ONEMSECEN(value)))
+#define USB_BWR_OTGICR_ONEMSECEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_ONEMSECEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGICR, field IDEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - The ID interrupt is disabled
+ * - 0b1 - The ID interrupt is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGICR_IDEN field. */
+#define USB_RD_OTGICR_IDEN(base) ((USB_OTGICR_REG(base) & USB_OTGICR_IDEN_MASK) >> USB_OTGICR_IDEN_SHIFT)
+#define USB_BRD_OTGICR_IDEN(base) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_IDEN_SHIFT))
+
+/*! @brief Set the IDEN field to a new value. */
+#define USB_WR_OTGICR_IDEN(base, value) (USB_RMW_OTGICR(base, USB_OTGICR_IDEN_MASK, USB_OTGICR_IDEN(value)))
+#define USB_BWR_OTGICR_IDEN(base, value) (BITBAND_ACCESS8(&USB_OTGICR_REG(base), USB_OTGICR_IDEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGSTAT - OTG Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGSTAT - OTG Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Displays the actual value from the external comparator outputs of the ID pin
+ * and VBUS.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGSTAT register
+ */
+/*@{*/
+#define USB_RD_OTGSTAT(base)     (USB_OTGSTAT_REG(base))
+#define USB_WR_OTGSTAT(base, value) (USB_OTGSTAT_REG(base) = (value))
+#define USB_RMW_OTGSTAT(base, mask, value) (USB_WR_OTGSTAT(base, (USB_RD_OTGSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) |  (value)))
+#define USB_CLR_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) & ~(value)))
+#define USB_TOG_OTGSTAT(base, value) (USB_WR_OTGSTAT(base, USB_RD_OTGSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_OTGSTAT, field AVBUSVLD[0] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is below the A VBUS Valid threshold.
+ * - 0b1 - The VBUS voltage is above the A VBUS Valid threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_AVBUSVLD field. */
+#define USB_RD_OTGSTAT_AVBUSVLD(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_AVBUSVLD_MASK) >> USB_OTGSTAT_AVBUSVLD_SHIFT)
+#define USB_BRD_OTGSTAT_AVBUSVLD(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_AVBUSVLD_SHIFT))
+
+/*! @brief Set the AVBUSVLD field to a new value. */
+#define USB_WR_OTGSTAT_AVBUSVLD(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_AVBUSVLD_MASK, USB_OTGSTAT_AVBUSVLD(value)))
+#define USB_BWR_OTGSTAT_AVBUSVLD(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_AVBUSVLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field BSESSEND[2] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is above the B session end threshold.
+ * - 0b1 - The VBUS voltage is below the B session end threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_BSESSEND field. */
+#define USB_RD_OTGSTAT_BSESSEND(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_BSESSEND_MASK) >> USB_OTGSTAT_BSESSEND_SHIFT)
+#define USB_BRD_OTGSTAT_BSESSEND(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_BSESSEND_SHIFT))
+
+/*! @brief Set the BSESSEND field to a new value. */
+#define USB_WR_OTGSTAT_BSESSEND(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_BSESSEND_MASK, USB_OTGSTAT_BSESSEND(value)))
+#define USB_BWR_OTGSTAT_BSESSEND(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_BSESSEND_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field SESS_VLD[3] (RW)
+ *
+ * Values:
+ * - 0b0 - The VBUS voltage is below the B session valid threshold
+ * - 0b1 - The VBUS voltage is above the B session valid threshold.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_SESS_VLD field. */
+#define USB_RD_OTGSTAT_SESS_VLD(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_SESS_VLD_MASK) >> USB_OTGSTAT_SESS_VLD_SHIFT)
+#define USB_BRD_OTGSTAT_SESS_VLD(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_SESS_VLD_SHIFT))
+
+/*! @brief Set the SESS_VLD field to a new value. */
+#define USB_WR_OTGSTAT_SESS_VLD(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_SESS_VLD_MASK, USB_OTGSTAT_SESS_VLD(value)))
+#define USB_BWR_OTGSTAT_SESS_VLD(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_SESS_VLD_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field LINESTATESTABLE[5] (RW)
+ *
+ * Indicates that the internal signals that control the LINE_STATE_CHG field of
+ * OTGISTAT are stable for at least 1 millisecond. First read LINE_STATE_CHG
+ * field and then read this field. If this field reads as 1, then the value of
+ * LINE_STATE_CHG can be considered stable.
+ *
+ * Values:
+ * - 0b0 - The LINE_STAT_CHG bit is not yet stable.
+ * - 0b1 - The LINE_STAT_CHG bit has been debounced and is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_LINESTATESTABLE field. */
+#define USB_RD_OTGSTAT_LINESTATESTABLE(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_LINESTATESTABLE_MASK) >> USB_OTGSTAT_LINESTATESTABLE_SHIFT)
+#define USB_BRD_OTGSTAT_LINESTATESTABLE(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_LINESTATESTABLE_SHIFT))
+
+/*! @brief Set the LINESTATESTABLE field to a new value. */
+#define USB_WR_OTGSTAT_LINESTATESTABLE(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_LINESTATESTABLE_MASK, USB_OTGSTAT_LINESTATESTABLE(value)))
+#define USB_BWR_OTGSTAT_LINESTATESTABLE(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_LINESTATESTABLE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field ONEMSECEN[6] (RW)
+ *
+ * This bit is reserved for the 1ms count, but it is not useful to software.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_ONEMSECEN field. */
+#define USB_RD_OTGSTAT_ONEMSECEN(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_ONEMSECEN_MASK) >> USB_OTGSTAT_ONEMSECEN_SHIFT)
+#define USB_BRD_OTGSTAT_ONEMSECEN(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ONEMSECEN_SHIFT))
+
+/*! @brief Set the ONEMSECEN field to a new value. */
+#define USB_WR_OTGSTAT_ONEMSECEN(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_ONEMSECEN_MASK, USB_OTGSTAT_ONEMSECEN(value)))
+#define USB_BWR_OTGSTAT_ONEMSECEN(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ONEMSECEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGSTAT, field ID[7] (RW)
+ *
+ * Indicates the current state of the ID pin on the USB connector
+ *
+ * Values:
+ * - 0b0 - Indicates a Type A cable is plugged into the USB connector.
+ * - 0b1 - Indicates no cable is attached or a Type B cable is plugged into the
+ *     USB connector.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGSTAT_ID field. */
+#define USB_RD_OTGSTAT_ID(base) ((USB_OTGSTAT_REG(base) & USB_OTGSTAT_ID_MASK) >> USB_OTGSTAT_ID_SHIFT)
+#define USB_BRD_OTGSTAT_ID(base) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ID_SHIFT))
+
+/*! @brief Set the ID field to a new value. */
+#define USB_WR_OTGSTAT_ID(base, value) (USB_RMW_OTGSTAT(base, USB_OTGSTAT_ID_MASK, USB_OTGSTAT_ID(value)))
+#define USB_BWR_OTGSTAT_ID(base, value) (BITBAND_ACCESS8(&USB_OTGSTAT_REG(base), USB_OTGSTAT_ID_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OTGCTL - OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OTGCTL - OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Controls the operation of VBUS and Data Line termination resistors.
+ */
+/*!
+ * @name Constants and macros for entire USB_OTGCTL register
+ */
+/*@{*/
+#define USB_RD_OTGCTL(base)      (USB_OTGCTL_REG(base))
+#define USB_WR_OTGCTL(base, value) (USB_OTGCTL_REG(base) = (value))
+#define USB_RMW_OTGCTL(base, mask, value) (USB_WR_OTGCTL(base, (USB_RD_OTGCTL(base) & ~(mask)) | (value)))
+#define USB_SET_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) |  (value)))
+#define USB_CLR_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) & ~(value)))
+#define USB_TOG_OTGCTL(base, value) (USB_WR_OTGCTL(base, USB_RD_OTGCTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OTGCTL bitfields
+ */
+
+/*!
+ * @name Register USB_OTGCTL, field OTGEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then
+ *     the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+
+ *     and D- Data Line pull-down resistors are engaged.
+ * - 0b1 - The pull-up and pull-down controls in this register are used.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_OTGEN field. */
+#define USB_RD_OTGCTL_OTGEN(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_OTGEN_MASK) >> USB_OTGCTL_OTGEN_SHIFT)
+#define USB_BRD_OTGCTL_OTGEN(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_OTGEN_SHIFT))
+
+/*! @brief Set the OTGEN field to a new value. */
+#define USB_WR_OTGCTL_OTGEN(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_OTGEN_MASK, USB_OTGCTL_OTGEN(value)))
+#define USB_BWR_OTGCTL_OTGEN(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_OTGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DMLOW[4] (RW)
+ *
+ * Values:
+ * - 0b0 - D- pulldown resistor is not enabled.
+ * - 0b1 - D- pulldown resistor is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DMLOW field. */
+#define USB_RD_OTGCTL_DMLOW(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DMLOW_MASK) >> USB_OTGCTL_DMLOW_SHIFT)
+#define USB_BRD_OTGCTL_DMLOW(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DMLOW_SHIFT))
+
+/*! @brief Set the DMLOW field to a new value. */
+#define USB_WR_OTGCTL_DMLOW(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DMLOW_MASK, USB_OTGCTL_DMLOW(value)))
+#define USB_BWR_OTGCTL_DMLOW(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DMLOW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DPLOW[5] (RW)
+ *
+ * This bit should always be enabled together with bit 4 (DMLOW)
+ *
+ * Values:
+ * - 0b0 - D+ pulldown resistor is not enabled.
+ * - 0b1 - D+ pulldown resistor is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPLOW field. */
+#define USB_RD_OTGCTL_DPLOW(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPLOW_MASK) >> USB_OTGCTL_DPLOW_SHIFT)
+#define USB_BRD_OTGCTL_DPLOW(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPLOW_SHIFT))
+
+/*! @brief Set the DPLOW field to a new value. */
+#define USB_WR_OTGCTL_DPLOW(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPLOW_MASK, USB_OTGCTL_DPLOW(value)))
+#define USB_BWR_OTGCTL_DPLOW(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPLOW_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_OTGCTL, field DPHIGH[7] (RW)
+ *
+ * Values:
+ * - 0b0 - D+ pullup resistor is not enabled
+ * - 0b1 - D+ pullup resistor is enabled
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OTGCTL_DPHIGH field. */
+#define USB_RD_OTGCTL_DPHIGH(base) ((USB_OTGCTL_REG(base) & USB_OTGCTL_DPHIGH_MASK) >> USB_OTGCTL_DPHIGH_SHIFT)
+#define USB_BRD_OTGCTL_DPHIGH(base) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT))
+
+/*! @brief Set the DPHIGH field to a new value. */
+#define USB_WR_OTGCTL_DPHIGH(base, value) (USB_RMW_OTGCTL(base, USB_OTGCTL_DPHIGH_MASK, USB_OTGCTL_DPHIGH(value)))
+#define USB_BWR_OTGCTL_DPHIGH(base, value) (BITBAND_ACCESS8(&USB_OTGCTL_REG(base), USB_OTGCTL_DPHIGH_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ISTAT - Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ISTAT - Interrupt Status register (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains fields for each of the interrupt sources within the USB Module. Each
+ * of these fields are qualified with their respective interrupt enable bits.
+ * All fields of this register are logically OR'd together along with the OTG
+ * Interrupt Status Register (OTGSTAT) to form a single interrupt source for the
+ * processor's interrupt controller. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ISTAT register
+ */
+/*@{*/
+#define USB_RD_ISTAT(base)       (USB_ISTAT_REG(base))
+#define USB_WR_ISTAT(base, value) (USB_ISTAT_REG(base) = (value))
+#define USB_RMW_ISTAT(base, mask, value) (USB_WR_ISTAT(base, (USB_RD_ISTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) |  (value)))
+#define USB_CLR_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) & ~(value)))
+#define USB_TOG_ISTAT(base, value) (USB_WR_ISTAT(base, USB_RD_ISTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ISTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ISTAT, field USBRST[0] (W1C)
+ *
+ * This bit is set when the USB Module has decoded a valid USB reset. This
+ * informs the processor that it should write 0x00 into the address register and
+ * enable endpoint 0. USBRST is set after a USB reset has been detected for 2.5
+ * microseconds. It is not asserted again until the USB reset condition has been
+ * removed and then reasserted.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_USBRST field. */
+#define USB_RD_ISTAT_USBRST(base) ((USB_ISTAT_REG(base) & USB_ISTAT_USBRST_MASK) >> USB_ISTAT_USBRST_SHIFT)
+#define USB_BRD_ISTAT_USBRST(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT))
+
+/*! @brief Set the USBRST field to a new value. */
+#define USB_WR_ISTAT_USBRST(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_USBRST(value)))
+#define USB_BWR_ISTAT_USBRST(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_USBRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ERROR[1] (W1C)
+ *
+ * This bit is set when any of the error conditions within Error Interrupt
+ * Status (ERRSTAT) register occur. The processor must then read the ERRSTAT register
+ * to determine the source of the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ERROR field. */
+#define USB_RD_ISTAT_ERROR(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ERROR_MASK) >> USB_ISTAT_ERROR_SHIFT)
+#define USB_BRD_ISTAT_ERROR(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT))
+
+/*! @brief Set the ERROR field to a new value. */
+#define USB_WR_ISTAT_ERROR(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ERROR_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ERROR(value)))
+#define USB_BWR_ISTAT_ERROR(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ERROR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SOFTOK[2] (W1C)
+ *
+ * This bit is set when the USB Module receives a Start Of Frame (SOF) token. In
+ * Host mode this field is set when the SOF threshold is reached, so that
+ * software can prepare for the next SOF.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SOFTOK field. */
+#define USB_RD_ISTAT_SOFTOK(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SOFTOK_MASK) >> USB_ISTAT_SOFTOK_SHIFT)
+#define USB_BRD_ISTAT_SOFTOK(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT))
+
+/*! @brief Set the SOFTOK field to a new value. */
+#define USB_WR_ISTAT_SOFTOK(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SOFTOK_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SOFTOK(value)))
+#define USB_BWR_ISTAT_SOFTOK(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SOFTOK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field TOKDNE[3] (W1C)
+ *
+ * This bit is set when the current token being processed has completed. The
+ * processor must immediately read the STATUS (STAT) register to determine the
+ * EndPoint and BD used for this token. Clearing this bit (by writing a one) causes
+ * STAT to be cleared or the STAT holding register to be loaded into the STAT
+ * register.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_TOKDNE field. */
+#define USB_RD_ISTAT_TOKDNE(base) ((USB_ISTAT_REG(base) & USB_ISTAT_TOKDNE_MASK) >> USB_ISTAT_TOKDNE_SHIFT)
+#define USB_BRD_ISTAT_TOKDNE(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT))
+
+/*! @brief Set the TOKDNE field to a new value. */
+#define USB_WR_ISTAT_TOKDNE(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_TOKDNE_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_TOKDNE(value)))
+#define USB_BWR_ISTAT_TOKDNE(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_TOKDNE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field SLEEP[4] (W1C)
+ *
+ * This bit is set when the USB Module detects a constant idle on the USB bus
+ * for 3 ms. The sleep timer is reset by activity on the USB bus.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_SLEEP field. */
+#define USB_RD_ISTAT_SLEEP(base) ((USB_ISTAT_REG(base) & USB_ISTAT_SLEEP_MASK) >> USB_ISTAT_SLEEP_SHIFT)
+#define USB_BRD_ISTAT_SLEEP(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT))
+
+/*! @brief Set the SLEEP field to a new value. */
+#define USB_WR_ISTAT_SLEEP(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_SLEEP_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_SLEEP(value)))
+#define USB_BWR_ISTAT_SLEEP(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_SLEEP_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field RESUME[5] (W1C)
+ *
+ * This bit is set when a K-state is observed on the DP/DM signals for 2.5 us.
+ * When not in suspend mode this interrupt must be disabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_RESUME field. */
+#define USB_RD_ISTAT_RESUME(base) ((USB_ISTAT_REG(base) & USB_ISTAT_RESUME_MASK) >> USB_ISTAT_RESUME_SHIFT)
+#define USB_BRD_ISTAT_RESUME(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_ISTAT_RESUME(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_RESUME_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_ATTACH_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_RESUME(value)))
+#define USB_BWR_ISTAT_RESUME(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_RESUME_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field ATTACH[6] (W1C)
+ *
+ * This bit is set when the USB Module detects an attach of a USB device. This
+ * signal is only valid if HOSTMODEEN is true. This interrupt signifies that a
+ * peripheral is now present and must be configured; it is asserted if there have
+ * been no transitions on the USB for 2.5 us and the current bus state is not SE0."
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_ATTACH field. */
+#define USB_RD_ISTAT_ATTACH(base) ((USB_ISTAT_REG(base) & USB_ISTAT_ATTACH_MASK) >> USB_ISTAT_ATTACH_SHIFT)
+#define USB_BRD_ISTAT_ATTACH(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ATTACH_SHIFT))
+
+/*! @brief Set the ATTACH field to a new value. */
+#define USB_WR_ISTAT_ATTACH(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_ATTACH_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_STALL_MASK), USB_ISTAT_ATTACH(value)))
+#define USB_BWR_ISTAT_ATTACH(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_ATTACH_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ISTAT, field STALL[7] (W1C)
+ *
+ * In Target mode this bit is asserted when a STALL handshake is sent by the
+ * SIE. In Host mode this bit is set when the USB Module detects a STALL acknowledge
+ * during the handshake phase of a USB transaction.This interrupt can be used to
+ * determine whether the last USB transaction was completed successfully or
+ * stalled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ISTAT_STALL field. */
+#define USB_RD_ISTAT_STALL(base) ((USB_ISTAT_REG(base) & USB_ISTAT_STALL_MASK) >> USB_ISTAT_STALL_SHIFT)
+#define USB_BRD_ISTAT_STALL(base) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT))
+
+/*! @brief Set the STALL field to a new value. */
+#define USB_WR_ISTAT_STALL(base, value) (USB_RMW_ISTAT(base, (USB_ISTAT_STALL_MASK | USB_ISTAT_USBRST_MASK | USB_ISTAT_ERROR_MASK | USB_ISTAT_SOFTOK_MASK | USB_ISTAT_TOKDNE_MASK | USB_ISTAT_SLEEP_MASK | USB_ISTAT_RESUME_MASK | USB_ISTAT_ATTACH_MASK), USB_ISTAT_STALL(value)))
+#define USB_BWR_ISTAT_STALL(base, value) (BITBAND_ACCESS8(&USB_ISTAT_REG(base), USB_ISTAT_STALL_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_INTEN - Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_INTEN - Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable fields for each of the interrupt sources within the USB
+ * Module. Setting any of these bits enables the respective interrupt source in the
+ * ISTAT register. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_INTEN register
+ */
+/*@{*/
+#define USB_RD_INTEN(base)       (USB_INTEN_REG(base))
+#define USB_WR_INTEN(base, value) (USB_INTEN_REG(base) = (value))
+#define USB_RMW_INTEN(base, mask, value) (USB_WR_INTEN(base, (USB_RD_INTEN(base) & ~(mask)) | (value)))
+#define USB_SET_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) |  (value)))
+#define USB_CLR_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) & ~(value)))
+#define USB_TOG_INTEN(base, value) (USB_WR_INTEN(base, USB_RD_INTEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_INTEN bitfields
+ */
+
+/*!
+ * @name Register USB_INTEN, field USBRSTEN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the USBRST interrupt.
+ * - 0b1 - Enables the USBRST interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_USBRSTEN field. */
+#define USB_RD_INTEN_USBRSTEN(base) ((USB_INTEN_REG(base) & USB_INTEN_USBRSTEN_MASK) >> USB_INTEN_USBRSTEN_SHIFT)
+#define USB_BRD_INTEN_USBRSTEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT))
+
+/*! @brief Set the USBRSTEN field to a new value. */
+#define USB_WR_INTEN_USBRSTEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_USBRSTEN_MASK, USB_INTEN_USBRSTEN(value)))
+#define USB_BWR_INTEN_USBRSTEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_USBRSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ERROREN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the ERROR interrupt.
+ * - 0b1 - Enables the ERROR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ERROREN field. */
+#define USB_RD_INTEN_ERROREN(base) ((USB_INTEN_REG(base) & USB_INTEN_ERROREN_MASK) >> USB_INTEN_ERROREN_SHIFT)
+#define USB_BRD_INTEN_ERROREN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT))
+
+/*! @brief Set the ERROREN field to a new value. */
+#define USB_WR_INTEN_ERROREN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ERROREN_MASK, USB_INTEN_ERROREN(value)))
+#define USB_BWR_INTEN_ERROREN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ERROREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SOFTOKEN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disbles the SOFTOK interrupt.
+ * - 0b1 - Enables the SOFTOK interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SOFTOKEN field. */
+#define USB_RD_INTEN_SOFTOKEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SOFTOKEN_MASK) >> USB_INTEN_SOFTOKEN_SHIFT)
+#define USB_BRD_INTEN_SOFTOKEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT))
+
+/*! @brief Set the SOFTOKEN field to a new value. */
+#define USB_WR_INTEN_SOFTOKEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SOFTOKEN_MASK, USB_INTEN_SOFTOKEN(value)))
+#define USB_BWR_INTEN_SOFTOKEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SOFTOKEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field TOKDNEEN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the TOKDNE interrupt.
+ * - 0b1 - Enables the TOKDNE interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_TOKDNEEN field. */
+#define USB_RD_INTEN_TOKDNEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_TOKDNEEN_MASK) >> USB_INTEN_TOKDNEEN_SHIFT)
+#define USB_BRD_INTEN_TOKDNEEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT))
+
+/*! @brief Set the TOKDNEEN field to a new value. */
+#define USB_WR_INTEN_TOKDNEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_TOKDNEEN_MASK, USB_INTEN_TOKDNEEN(value)))
+#define USB_BWR_INTEN_TOKDNEEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_TOKDNEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field SLEEPEN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the SLEEP interrupt.
+ * - 0b1 - Enables the SLEEP interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_SLEEPEN field. */
+#define USB_RD_INTEN_SLEEPEN(base) ((USB_INTEN_REG(base) & USB_INTEN_SLEEPEN_MASK) >> USB_INTEN_SLEEPEN_SHIFT)
+#define USB_BRD_INTEN_SLEEPEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT))
+
+/*! @brief Set the SLEEPEN field to a new value. */
+#define USB_WR_INTEN_SLEEPEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_SLEEPEN_MASK, USB_INTEN_SLEEPEN(value)))
+#define USB_BWR_INTEN_SLEEPEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_SLEEPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field RESUMEEN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the RESUME interrupt.
+ * - 0b1 - Enables the RESUME interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_RESUMEEN field. */
+#define USB_RD_INTEN_RESUMEEN(base) ((USB_INTEN_REG(base) & USB_INTEN_RESUMEEN_MASK) >> USB_INTEN_RESUMEEN_SHIFT)
+#define USB_BRD_INTEN_RESUMEEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT))
+
+/*! @brief Set the RESUMEEN field to a new value. */
+#define USB_WR_INTEN_RESUMEEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_RESUMEEN_MASK, USB_INTEN_RESUMEEN(value)))
+#define USB_BWR_INTEN_RESUMEEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_RESUMEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field ATTACHEN[6] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the ATTACH interrupt.
+ * - 0b1 - Enables the ATTACH interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_ATTACHEN field. */
+#define USB_RD_INTEN_ATTACHEN(base) ((USB_INTEN_REG(base) & USB_INTEN_ATTACHEN_MASK) >> USB_INTEN_ATTACHEN_SHIFT)
+#define USB_BRD_INTEN_ATTACHEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ATTACHEN_SHIFT))
+
+/*! @brief Set the ATTACHEN field to a new value. */
+#define USB_WR_INTEN_ATTACHEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_ATTACHEN_MASK, USB_INTEN_ATTACHEN(value)))
+#define USB_BWR_INTEN_ATTACHEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_ATTACHEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_INTEN, field STALLEN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Diasbles the STALL interrupt.
+ * - 0b1 - Enables the STALL interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_INTEN_STALLEN field. */
+#define USB_RD_INTEN_STALLEN(base) ((USB_INTEN_REG(base) & USB_INTEN_STALLEN_MASK) >> USB_INTEN_STALLEN_SHIFT)
+#define USB_BRD_INTEN_STALLEN(base) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT))
+
+/*! @brief Set the STALLEN field to a new value. */
+#define USB_WR_INTEN_STALLEN(base, value) (USB_RMW_INTEN(base, USB_INTEN_STALLEN_MASK, USB_INTEN_STALLEN(value)))
+#define USB_BWR_INTEN_STALLEN(base, value) (BITBAND_ACCESS8(&USB_INTEN_REG(base), USB_INTEN_STALLEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERRSTAT - Error Interrupt Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERRSTAT - Error Interrupt Status register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error sources within the USB Module.
+ * Each of these bits are qualified with their respective error enable bits. All
+ * bits of this register are logically OR'd together and the result placed in the
+ * ERROR bit of the ISTAT register. After an interrupt bit has been set it may only
+ * be cleared by writing a one to the respective interrupt bit. Each bit is set
+ * as soon as the error condition is detected. Therefore, the interrupt does not
+ * typically correspond with the end of a token being processed. This register
+ * contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERRSTAT register
+ */
+/*@{*/
+#define USB_RD_ERRSTAT(base)     (USB_ERRSTAT_REG(base))
+#define USB_WR_ERRSTAT(base, value) (USB_ERRSTAT_REG(base) = (value))
+#define USB_RMW_ERRSTAT(base, mask, value) (USB_WR_ERRSTAT(base, (USB_RD_ERRSTAT(base) & ~(mask)) | (value)))
+#define USB_SET_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) |  (value)))
+#define USB_CLR_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) & ~(value)))
+#define USB_TOG_ERRSTAT(base, value) (USB_WR_ERRSTAT(base, USB_RD_ERRSTAT(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERRSTAT bitfields
+ */
+
+/*!
+ * @name Register USB_ERRSTAT, field PIDERR[0] (W1C)
+ *
+ * This bit is set when the PID check field fails.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_PIDERR field. */
+#define USB_RD_ERRSTAT_PIDERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_PIDERR_MASK) >> USB_ERRSTAT_PIDERR_SHIFT)
+#define USB_BRD_ERRSTAT_PIDERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT))
+
+/*! @brief Set the PIDERR field to a new value. */
+#define USB_WR_ERRSTAT_PIDERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_PIDERR(value)))
+#define USB_BWR_ERRSTAT_PIDERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_PIDERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC5EOF[1] (W1C)
+ *
+ * This error interrupt has two functions. When the USB Module is operating in
+ * peripheral mode (HOSTMODEEN=0), this interrupt detects CRC5 errors in the token
+ * packets generated by the host. If set the token packet was rejected due to a
+ * CRC5 error. When the USB Module is operating in host mode (HOSTMODEEN=1), this
+ * interrupt detects End Of Frame (EOF) error conditions. This occurs when the
+ * USB Module is transmitting or receiving data and the SOF counter reaches zero.
+ * This interrupt is useful when developing USB packet scheduling software to
+ * ensure that no USB transactions cross the start of the next frame.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC5EOF field. */
+#define USB_RD_ERRSTAT_CRC5EOF(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC5EOF_MASK) >> USB_ERRSTAT_CRC5EOF_SHIFT)
+#define USB_BRD_ERRSTAT_CRC5EOF(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5EOF_SHIFT))
+
+/*! @brief Set the CRC5EOF field to a new value. */
+#define USB_WR_ERRSTAT_CRC5EOF(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC5EOF(value)))
+#define USB_BWR_ERRSTAT_CRC5EOF(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC5EOF_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field CRC16[2] (W1C)
+ *
+ * This bit is set when a data packet is rejected due to a CRC16 error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_CRC16 field. */
+#define USB_RD_ERRSTAT_CRC16(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_CRC16_MASK) >> USB_ERRSTAT_CRC16_SHIFT)
+#define USB_BRD_ERRSTAT_CRC16(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT))
+
+/*! @brief Set the CRC16 field to a new value. */
+#define USB_WR_ERRSTAT_CRC16(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_CRC16(value)))
+#define USB_BWR_ERRSTAT_CRC16(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_CRC16_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DFN8[3] (W1C)
+ *
+ * This bit is set if the data field received was not 8 bits in length. USB
+ * Specification 1.0 requires that data fields be an integral number of bytes. If the
+ * data field was not an integral number of bytes, this bit is set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DFN8 field. */
+#define USB_RD_ERRSTAT_DFN8(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DFN8_MASK) >> USB_ERRSTAT_DFN8_SHIFT)
+#define USB_BRD_ERRSTAT_DFN8(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT))
+
+/*! @brief Set the DFN8 field to a new value. */
+#define USB_WR_ERRSTAT_DFN8(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DFN8(value)))
+#define USB_BWR_ERRSTAT_DFN8(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DFN8_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTOERR[4] (W1C)
+ *
+ * This bit is set when a bus turnaround timeout error occurs. The USB module
+ * contains a bus turnaround timer that keeps track of the amount of time elapsed
+ * between the token and data phases of a SETUP or OUT TOKEN or the data and
+ * handshake phases of a IN TOKEN. If more than 16 bit times are counted from the
+ * previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTOERR field. */
+#define USB_RD_ERRSTAT_BTOERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTOERR_MASK) >> USB_ERRSTAT_BTOERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTOERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT))
+
+/*! @brief Set the BTOERR field to a new value. */
+#define USB_WR_ERRSTAT_BTOERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_BTOERR(value)))
+#define USB_BWR_ERRSTAT_BTOERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTOERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field DMAERR[5] (W1C)
+ *
+ * This bit is set if the USB Module has requested a DMA access to read a new
+ * BDT but has not been given the bus before it needs to receive or transmit data.
+ * If processing a TX transfer this would cause a transmit data underflow
+ * condition. If processing a RX transfer this would cause a receive data overflow
+ * condition. This interrupt is useful when developing device arbitration hardware for
+ * the microprocessor and the USB module to minimize bus request and bus grant
+ * latency. This bit is also set if a data packet to or from the host is larger
+ * than the buffer size allocated in the BDT. In this case the data packet is
+ * truncated as it is put in buffer memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_DMAERR field. */
+#define USB_RD_ERRSTAT_DMAERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_DMAERR_MASK) >> USB_ERRSTAT_DMAERR_SHIFT)
+#define USB_BRD_ERRSTAT_DMAERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT))
+
+/*! @brief Set the DMAERR field to a new value. */
+#define USB_WR_ERRSTAT_DMAERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_DMAERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_BTSERR_MASK), USB_ERRSTAT_DMAERR(value)))
+#define USB_BWR_ERRSTAT_DMAERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_DMAERR_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERRSTAT, field BTSERR[7] (W1C)
+ *
+ * This bit is set when a bit stuff error is detected. If set, the corresponding
+ * packet is rejected due to the error.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERRSTAT_BTSERR field. */
+#define USB_RD_ERRSTAT_BTSERR(base) ((USB_ERRSTAT_REG(base) & USB_ERRSTAT_BTSERR_MASK) >> USB_ERRSTAT_BTSERR_SHIFT)
+#define USB_BRD_ERRSTAT_BTSERR(base) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT))
+
+/*! @brief Set the BTSERR field to a new value. */
+#define USB_WR_ERRSTAT_BTSERR(base, value) (USB_RMW_ERRSTAT(base, (USB_ERRSTAT_BTSERR_MASK | USB_ERRSTAT_PIDERR_MASK | USB_ERRSTAT_CRC5EOF_MASK | USB_ERRSTAT_CRC16_MASK | USB_ERRSTAT_DFN8_MASK | USB_ERRSTAT_BTOERR_MASK | USB_ERRSTAT_DMAERR_MASK), USB_ERRSTAT_BTSERR(value)))
+#define USB_BWR_ERRSTAT_BTSERR(base, value) (BITBAND_ACCESS8(&USB_ERRSTAT_REG(base), USB_ERRSTAT_BTSERR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ERREN - Error Interrupt Enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ERREN - Error Interrupt Enable register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains enable bits for each of the error interrupt sources within the USB
+ * module. Setting any of these bits enables the respective interrupt source in
+ * ERRSTAT. Each bit is set as soon as the error condition is detected. Therefore,
+ * the interrupt does not typically correspond with the end of a token being
+ * processed. This register contains the value of 0x00 after a reset.
+ */
+/*!
+ * @name Constants and macros for entire USB_ERREN register
+ */
+/*@{*/
+#define USB_RD_ERREN(base)       (USB_ERREN_REG(base))
+#define USB_WR_ERREN(base, value) (USB_ERREN_REG(base) = (value))
+#define USB_RMW_ERREN(base, mask, value) (USB_WR_ERREN(base, (USB_RD_ERREN(base) & ~(mask)) | (value)))
+#define USB_SET_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) |  (value)))
+#define USB_CLR_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) & ~(value)))
+#define USB_TOG_ERREN(base, value) (USB_WR_ERREN(base, USB_RD_ERREN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ERREN bitfields
+ */
+
+/*!
+ * @name Register USB_ERREN, field PIDERREN[0] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the PIDERR interrupt.
+ * - 0b1 - Enters the PIDERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_PIDERREN field. */
+#define USB_RD_ERREN_PIDERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_PIDERREN_MASK) >> USB_ERREN_PIDERREN_SHIFT)
+#define USB_BRD_ERREN_PIDERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT))
+
+/*! @brief Set the PIDERREN field to a new value. */
+#define USB_WR_ERREN_PIDERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_PIDERREN_MASK, USB_ERREN_PIDERREN(value)))
+#define USB_BWR_ERREN_PIDERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_PIDERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC5EOFEN[1] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the CRC5/EOF interrupt.
+ * - 0b1 - Enables the CRC5/EOF interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC5EOFEN field. */
+#define USB_RD_ERREN_CRC5EOFEN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC5EOFEN_MASK) >> USB_ERREN_CRC5EOFEN_SHIFT)
+#define USB_BRD_ERREN_CRC5EOFEN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT))
+
+/*! @brief Set the CRC5EOFEN field to a new value. */
+#define USB_WR_ERREN_CRC5EOFEN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC5EOFEN_MASK, USB_ERREN_CRC5EOFEN(value)))
+#define USB_BWR_ERREN_CRC5EOFEN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC5EOFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field CRC16EN[2] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the CRC16 interrupt.
+ * - 0b1 - Enables the CRC16 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_CRC16EN field. */
+#define USB_RD_ERREN_CRC16EN(base) ((USB_ERREN_REG(base) & USB_ERREN_CRC16EN_MASK) >> USB_ERREN_CRC16EN_SHIFT)
+#define USB_BRD_ERREN_CRC16EN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT))
+
+/*! @brief Set the CRC16EN field to a new value. */
+#define USB_WR_ERREN_CRC16EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_CRC16EN_MASK, USB_ERREN_CRC16EN(value)))
+#define USB_BWR_ERREN_CRC16EN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_CRC16EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DFN8EN[3] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the DFN8 interrupt.
+ * - 0b1 - Enables the DFN8 interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DFN8EN field. */
+#define USB_RD_ERREN_DFN8EN(base) ((USB_ERREN_REG(base) & USB_ERREN_DFN8EN_MASK) >> USB_ERREN_DFN8EN_SHIFT)
+#define USB_BRD_ERREN_DFN8EN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT))
+
+/*! @brief Set the DFN8EN field to a new value. */
+#define USB_WR_ERREN_DFN8EN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DFN8EN_MASK, USB_ERREN_DFN8EN(value)))
+#define USB_BWR_ERREN_DFN8EN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DFN8EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTOERREN[4] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the BTOERR interrupt.
+ * - 0b1 - Enables the BTOERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTOERREN field. */
+#define USB_RD_ERREN_BTOERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTOERREN_MASK) >> USB_ERREN_BTOERREN_SHIFT)
+#define USB_BRD_ERREN_BTOERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT))
+
+/*! @brief Set the BTOERREN field to a new value. */
+#define USB_WR_ERREN_BTOERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTOERREN_MASK, USB_ERREN_BTOERREN(value)))
+#define USB_BWR_ERREN_BTOERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTOERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field DMAERREN[5] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the DMAERR interrupt.
+ * - 0b1 - Enables the DMAERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_DMAERREN field. */
+#define USB_RD_ERREN_DMAERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_DMAERREN_MASK) >> USB_ERREN_DMAERREN_SHIFT)
+#define USB_BRD_ERREN_DMAERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT))
+
+/*! @brief Set the DMAERREN field to a new value. */
+#define USB_WR_ERREN_DMAERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_DMAERREN_MASK, USB_ERREN_DMAERREN(value)))
+#define USB_BWR_ERREN_DMAERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_DMAERREN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ERREN, field BTSERREN[7] (RW)
+ *
+ * Values:
+ * - 0b0 - Disables the BTSERR interrupt.
+ * - 0b1 - Enables the BTSERR interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ERREN_BTSERREN field. */
+#define USB_RD_ERREN_BTSERREN(base) ((USB_ERREN_REG(base) & USB_ERREN_BTSERREN_MASK) >> USB_ERREN_BTSERREN_SHIFT)
+#define USB_BRD_ERREN_BTSERREN(base) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT))
+
+/*! @brief Set the BTSERREN field to a new value. */
+#define USB_WR_ERREN_BTSERREN(base, value) (USB_RMW_ERREN(base, USB_ERREN_BTSERREN_MASK, USB_ERREN_BTSERREN(value)))
+#define USB_BWR_ERREN_BTSERREN(base, value) (BITBAND_ACCESS8(&USB_ERREN_REG(base), USB_ERREN_BTSERREN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_STAT - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_STAT - Status register (RO)
+ *
+ * Reset value: 0x00U
+ *
+ * Reports the transaction status within the USB module. When the processor's
+ * interrupt controller has received a TOKDNE, interrupt the Status Register must
+ * be read to determine the status of the previous endpoint communication. The
+ * data in the status register is valid when TOKDNE interrupt is asserted. The
+ * Status register is actually a read window into a status FIFO maintained by the USB
+ * module. When the USB module uses a BD, it updates the Status register. If
+ * another USB transaction is performed before the TOKDNE interrupt is serviced, the
+ * USB module stores the status of the next transaction in the STAT FIFO. Thus
+ * STAT is actually a four byte FIFO that allows the processor core to process one
+ * transaction while the SIE is processing the next transaction. Clearing the
+ * TOKDNE bit in the ISTAT register causes the SIE to update STAT with the contents
+ * of the next STAT value. If the data in the STAT holding register is valid, the
+ * SIE immediately reasserts to TOKDNE interrupt.
+ */
+/*!
+ * @name Constants and macros for entire USB_STAT register
+ */
+/*@{*/
+#define USB_RD_STAT(base)        (USB_STAT_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_STAT bitfields
+ */
+
+/*!
+ * @name Register USB_STAT, field ODD[2] (RO)
+ *
+ * This bit is set if the last buffer descriptor updated was in the odd bank of
+ * the BDT.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ODD field. */
+#define USB_RD_STAT_ODD(base) ((USB_STAT_REG(base) & USB_STAT_ODD_MASK) >> USB_STAT_ODD_SHIFT)
+#define USB_BRD_STAT_ODD(base) (BITBAND_ACCESS8(&USB_STAT_REG(base), USB_STAT_ODD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field TX[3] (RO)
+ *
+ * Values:
+ * - 0b0 - The most recent transaction was a receive operation.
+ * - 0b1 - The most recent transaction was a transmit operation.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_TX field. */
+#define USB_RD_STAT_TX(base) ((USB_STAT_REG(base) & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT)
+#define USB_BRD_STAT_TX(base) (BITBAND_ACCESS8(&USB_STAT_REG(base), USB_STAT_TX_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_STAT, field ENDP[7:4] (RO)
+ *
+ * This four-bit field encodes the endpoint address that received or transmitted
+ * the previous token. This allows the processor core to determine the BDT entry
+ * that was updated by the last USB transaction.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_STAT_ENDP field. */
+#define USB_RD_STAT_ENDP(base) ((USB_STAT_REG(base) & USB_STAT_ENDP_MASK) >> USB_STAT_ENDP_SHIFT)
+#define USB_BRD_STAT_ENDP(base) (USB_RD_STAT_ENDP(base))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CTL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CTL - Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides various control and configuration information for the USB module.
+ */
+/*!
+ * @name Constants and macros for entire USB_CTL register
+ */
+/*@{*/
+#define USB_RD_CTL(base)         (USB_CTL_REG(base))
+#define USB_WR_CTL(base, value)  (USB_CTL_REG(base) = (value))
+#define USB_RMW_CTL(base, mask, value) (USB_WR_CTL(base, (USB_RD_CTL(base) & ~(mask)) | (value)))
+#define USB_SET_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) |  (value)))
+#define USB_CLR_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) & ~(value)))
+#define USB_TOG_CTL(base, value) (USB_WR_CTL(base, USB_RD_CTL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CTL bitfields
+ */
+
+/*!
+ * @name Register USB_CTL, field USBENSOFEN[0] (RW)
+ *
+ * Setting this bit enables the USB-FS to operate; clearing it disables the
+ * USB-FS. Setting the bit causes the SIE to reset all of its ODD bits to the BDTs.
+ * Therefore, setting this bit resets much of the logic in the SIE. When host mode
+ * is enabled, clearing this bit causes the SIE to stop sending SOF tokens.
+ *
+ * Values:
+ * - 0b0 - Disables the USB Module.
+ * - 0b1 - Enables the USB Module.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_USBENSOFEN field. */
+#define USB_RD_CTL_USBENSOFEN(base) ((USB_CTL_REG(base) & USB_CTL_USBENSOFEN_MASK) >> USB_CTL_USBENSOFEN_SHIFT)
+#define USB_BRD_CTL_USBENSOFEN(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT))
+
+/*! @brief Set the USBENSOFEN field to a new value. */
+#define USB_WR_CTL_USBENSOFEN(base, value) (USB_RMW_CTL(base, USB_CTL_USBENSOFEN_MASK, USB_CTL_USBENSOFEN(value)))
+#define USB_BWR_CTL_USBENSOFEN(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_USBENSOFEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field ODDRST[1] (RW)
+ *
+ * Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which
+ * then specifies the EVEN BDT bank.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_ODDRST field. */
+#define USB_RD_CTL_ODDRST(base) ((USB_CTL_REG(base) & USB_CTL_ODDRST_MASK) >> USB_CTL_ODDRST_SHIFT)
+#define USB_BRD_CTL_ODDRST(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT))
+
+/*! @brief Set the ODDRST field to a new value. */
+#define USB_WR_CTL_ODDRST(base, value) (USB_RMW_CTL(base, USB_CTL_ODDRST_MASK, USB_CTL_ODDRST(value)))
+#define USB_BWR_CTL_ODDRST(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_ODDRST_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field RESUME[2] (RW)
+ *
+ * When set to 1 this bit enables the USB Module to execute resume signaling.
+ * This allows the USB Module to perform remote wake-up. Software must set RESUME
+ * to 1 for the required amount of time and then clear it to 0. If the HOSTMODEEN
+ * bit is set, the USB module appends a Low Speed End of Packet to the Resume
+ * signaling when the RESUME bit is cleared. For more information on RESUME
+ * signaling see Section 7.1.4.5 of the USB specification version 1.0.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_RESUME field. */
+#define USB_RD_CTL_RESUME(base) ((USB_CTL_REG(base) & USB_CTL_RESUME_MASK) >> USB_CTL_RESUME_SHIFT)
+#define USB_BRD_CTL_RESUME(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESUME_SHIFT))
+
+/*! @brief Set the RESUME field to a new value. */
+#define USB_WR_CTL_RESUME(base, value) (USB_RMW_CTL(base, USB_CTL_RESUME_MASK, USB_CTL_RESUME(value)))
+#define USB_BWR_CTL_RESUME(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESUME_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field HOSTMODEEN[3] (RW)
+ *
+ * When set to 1, this bit enables the USB Module to operate in Host mode. In
+ * host mode, the USB module performs USB transactions under the programmed control
+ * of the host processor.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_HOSTMODEEN field. */
+#define USB_RD_CTL_HOSTMODEEN(base) ((USB_CTL_REG(base) & USB_CTL_HOSTMODEEN_MASK) >> USB_CTL_HOSTMODEEN_SHIFT)
+#define USB_BRD_CTL_HOSTMODEEN(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_HOSTMODEEN_SHIFT))
+
+/*! @brief Set the HOSTMODEEN field to a new value. */
+#define USB_WR_CTL_HOSTMODEEN(base, value) (USB_RMW_CTL(base, USB_CTL_HOSTMODEEN_MASK, USB_CTL_HOSTMODEEN(value)))
+#define USB_BWR_CTL_HOSTMODEEN(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_HOSTMODEEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field RESET[4] (RW)
+ *
+ * Setting this bit enables the USB Module to generate USB reset signaling. This
+ * allows the USB Module to reset USB peripherals. This control signal is only
+ * valid in Host mode (HOSTMODEEN=1). Software must set RESET to 1 for the
+ * required amount of time and then clear it to 0 to end reset signaling. For more
+ * information on reset signaling see Section 7.1.4.3 of the USB specification version
+ * 1.0.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_RESET field. */
+#define USB_RD_CTL_RESET(base) ((USB_CTL_REG(base) & USB_CTL_RESET_MASK) >> USB_CTL_RESET_SHIFT)
+#define USB_BRD_CTL_RESET(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESET_SHIFT))
+
+/*! @brief Set the RESET field to a new value. */
+#define USB_WR_CTL_RESET(base, value) (USB_RMW_CTL(base, USB_CTL_RESET_MASK, USB_CTL_RESET(value)))
+#define USB_BWR_CTL_RESET(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_RESET_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field TXSUSPENDTOKENBUSY[5] (RW)
+ *
+ * In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB
+ * token. Software must not write more token commands to the Token Register when
+ * TOKEN_BUSY is set. Software should check this field before writing any tokens
+ * to the Token Register to ensure that token commands are not lost. In Target
+ * mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and
+ * reception. Clearing this bit allows the SIE to continue token processing. This bit
+ * is set by the SIE when a SETUP Token is received allowing software to dequeue
+ * any pending packet transactions in the BDT before resuming token processing.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_TXSUSPENDTOKENBUSY field. */
+#define USB_RD_CTL_TXSUSPENDTOKENBUSY(base) ((USB_CTL_REG(base) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) >> USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)
+#define USB_BRD_CTL_TXSUSPENDTOKENBUSY(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))
+
+/*! @brief Set the TXSUSPENDTOKENBUSY field to a new value. */
+#define USB_WR_CTL_TXSUSPENDTOKENBUSY(base, value) (USB_RMW_CTL(base, USB_CTL_TXSUSPENDTOKENBUSY_MASK, USB_CTL_TXSUSPENDTOKENBUSY(value)))
+#define USB_BWR_CTL_TXSUSPENDTOKENBUSY(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_TXSUSPENDTOKENBUSY_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field SE0[6] (RW)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_SE0 field. */
+#define USB_RD_CTL_SE0(base) ((USB_CTL_REG(base) & USB_CTL_SE0_MASK) >> USB_CTL_SE0_SHIFT)
+#define USB_BRD_CTL_SE0(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT))
+
+/*! @brief Set the SE0 field to a new value. */
+#define USB_WR_CTL_SE0(base, value) (USB_RMW_CTL(base, USB_CTL_SE0_MASK, USB_CTL_SE0(value)))
+#define USB_BWR_CTL_SE0(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_SE0_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CTL, field JSTATE[7] (RW)
+ *
+ * The polarity of this signal is affected by the current state of LSEN .
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CTL_JSTATE field. */
+#define USB_RD_CTL_JSTATE(base) ((USB_CTL_REG(base) & USB_CTL_JSTATE_MASK) >> USB_CTL_JSTATE_SHIFT)
+#define USB_BRD_CTL_JSTATE(base) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT))
+
+/*! @brief Set the JSTATE field to a new value. */
+#define USB_WR_CTL_JSTATE(base, value) (USB_RMW_CTL(base, USB_CTL_JSTATE_MASK, USB_CTL_JSTATE(value)))
+#define USB_BWR_CTL_JSTATE(base, value) (BITBAND_ACCESS8(&USB_CTL_REG(base), USB_CTL_JSTATE_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ADDR - Address register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ADDR - Address register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Holds the unique USB address that the USB module decodes when in Peripheral
+ * mode (HOSTMODEEN=0). When operating in Host mode (HOSTMODEEN=1) the USB module
+ * transmits this address with a TOKEN packet. This enables the USB module to
+ * uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN] must be 1.
+ * The Address register is reset to 0x00 after the reset input becomes active or
+ * the USB module decodes a USB reset signal. This action initializes the Address
+ * register to decode address 0x00 as required by the USB specification.
+ */
+/*!
+ * @name Constants and macros for entire USB_ADDR register
+ */
+/*@{*/
+#define USB_RD_ADDR(base)        (USB_ADDR_REG(base))
+#define USB_WR_ADDR(base, value) (USB_ADDR_REG(base) = (value))
+#define USB_RMW_ADDR(base, mask, value) (USB_WR_ADDR(base, (USB_RD_ADDR(base) & ~(mask)) | (value)))
+#define USB_SET_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) |  (value)))
+#define USB_CLR_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) & ~(value)))
+#define USB_TOG_ADDR(base, value) (USB_WR_ADDR(base, USB_RD_ADDR(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ADDR bitfields
+ */
+
+/*!
+ * @name Register USB_ADDR, field ADDR[6:0] (RW)
+ *
+ * Defines the USB address that the USB module decodes in peripheral mode, or
+ * transmits when in host mode.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_ADDR field. */
+#define USB_RD_ADDR_ADDR(base) ((USB_ADDR_REG(base) & USB_ADDR_ADDR_MASK) >> USB_ADDR_ADDR_SHIFT)
+#define USB_BRD_ADDR_ADDR(base) (USB_RD_ADDR_ADDR(base))
+
+/*! @brief Set the ADDR field to a new value. */
+#define USB_WR_ADDR_ADDR(base, value) (USB_RMW_ADDR(base, USB_ADDR_ADDR_MASK, USB_ADDR_ADDR(value)))
+#define USB_BWR_ADDR_ADDR(base, value) (USB_WR_ADDR_ADDR(base, value))
+/*@}*/
+
+/*!
+ * @name Register USB_ADDR, field LSEN[7] (RW)
+ *
+ * Informs the USB module that the next token command written to the token
+ * register must be performed at low speed. This enables the USB module to perform the
+ * necessary preamble required for low-speed data transmissions.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ADDR_LSEN field. */
+#define USB_RD_ADDR_LSEN(base) ((USB_ADDR_REG(base) & USB_ADDR_LSEN_MASK) >> USB_ADDR_LSEN_SHIFT)
+#define USB_BRD_ADDR_LSEN(base) (BITBAND_ACCESS8(&USB_ADDR_REG(base), USB_ADDR_LSEN_SHIFT))
+
+/*! @brief Set the LSEN field to a new value. */
+#define USB_WR_ADDR_LSEN(base, value) (USB_RMW_ADDR(base, USB_ADDR_LSEN_MASK, USB_ADDR_LSEN(value)))
+#define USB_BWR_ADDR_LSEN(base, value) (BITBAND_ACCESS8(&USB_ADDR_REG(base), USB_ADDR_LSEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE1 - BDT Page register 1
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE1 - BDT Page register 1 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Provides address bits 15 through 9 of the base address where the current
+ * Buffer Descriptor Table (BDT) resides in system memory. See Buffer Descriptor
+ * Table. The 32-bit BDT Base Address is always aligned on 512-byte boundaries, so
+ * bits 8 through 0 of the base address are always zero.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE1 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE1(base)    (USB_BDTPAGE1_REG(base))
+#define USB_WR_BDTPAGE1(base, value) (USB_BDTPAGE1_REG(base) = (value))
+#define USB_RMW_BDTPAGE1(base, mask, value) (USB_WR_BDTPAGE1(base, (USB_RD_BDTPAGE1(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) |  (value)))
+#define USB_CLR_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) & ~(value)))
+#define USB_TOG_BDTPAGE1(base, value) (USB_WR_BDTPAGE1(base, USB_RD_BDTPAGE1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_BDTPAGE1 bitfields
+ */
+
+/*!
+ * @name Register USB_BDTPAGE1, field BDTBA[7:1] (RW)
+ *
+ * Provides address bits 15 through 9 of the BDT base address.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_BDTPAGE1_BDTBA field. */
+#define USB_RD_BDTPAGE1_BDTBA(base) ((USB_BDTPAGE1_REG(base) & USB_BDTPAGE1_BDTBA_MASK) >> USB_BDTPAGE1_BDTBA_SHIFT)
+#define USB_BRD_BDTPAGE1_BDTBA(base) (USB_RD_BDTPAGE1_BDTBA(base))
+
+/*! @brief Set the BDTBA field to a new value. */
+#define USB_WR_BDTPAGE1_BDTBA(base, value) (USB_RMW_BDTPAGE1(base, USB_BDTPAGE1_BDTBA_MASK, USB_BDTPAGE1_BDTBA(value)))
+#define USB_BWR_BDTPAGE1_BDTBA(base, value) (USB_WR_BDTPAGE1_BDTBA(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUML - Frame Number register Low
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUML - Frame Number register Low (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUML register
+ */
+/*@{*/
+#define USB_RD_FRMNUML(base)     (USB_FRMNUML_REG(base))
+#define USB_WR_FRMNUML(base, value) (USB_FRMNUML_REG(base) = (value))
+#define USB_RMW_FRMNUML(base, mask, value) (USB_WR_FRMNUML(base, (USB_RD_FRMNUML(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) |  (value)))
+#define USB_CLR_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) & ~(value)))
+#define USB_TOG_FRMNUML(base, value) (USB_WR_FRMNUML(base, USB_RD_FRMNUML(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_FRMNUMH - Frame Number register High
+ ******************************************************************************/
+
+/*!
+ * @brief USB_FRMNUMH - Frame Number register High (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The Frame Number registers (low and high) contain the 11-bit frame number.
+ * These registers are updated with the current frame number whenever a SOF TOKEN
+ * is received.
+ */
+/*!
+ * @name Constants and macros for entire USB_FRMNUMH register
+ */
+/*@{*/
+#define USB_RD_FRMNUMH(base)     (USB_FRMNUMH_REG(base))
+#define USB_WR_FRMNUMH(base, value) (USB_FRMNUMH_REG(base) = (value))
+#define USB_RMW_FRMNUMH(base, mask, value) (USB_WR_FRMNUMH(base, (USB_RD_FRMNUMH(base) & ~(mask)) | (value)))
+#define USB_SET_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) |  (value)))
+#define USB_CLR_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) & ~(value)))
+#define USB_TOG_FRMNUMH(base, value) (USB_WR_FRMNUMH(base, USB_RD_FRMNUMH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_FRMNUMH bitfields
+ */
+
+/*!
+ * @name Register USB_FRMNUMH, field FRM[2:0] (RW)
+ *
+ * This 3-bit field and the 8-bit field in the Frame Number Register Low are
+ * used to compute the address where the current Buffer Descriptor Table (BDT)
+ * resides in system memory.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_FRMNUMH_FRM field. */
+#define USB_RD_FRMNUMH_FRM(base) ((USB_FRMNUMH_REG(base) & USB_FRMNUMH_FRM_MASK) >> USB_FRMNUMH_FRM_SHIFT)
+#define USB_BRD_FRMNUMH_FRM(base) (USB_RD_FRMNUMH_FRM(base))
+
+/*! @brief Set the FRM field to a new value. */
+#define USB_WR_FRMNUMH_FRM(base, value) (USB_RMW_FRMNUMH(base, USB_FRMNUMH_FRM_MASK, USB_FRMNUMH_FRM(value)))
+#define USB_BWR_FRMNUMH_FRM(base, value) (USB_WR_FRMNUMH_FRM(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_TOKEN - Token register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_TOKEN - Token register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Used to initiate USB transactions when in host mode (HOSTMODEEN=1). When the
+ * software needs to execute a USB transaction to a peripheral, it writes the
+ * TOKEN type and endpoint to this register. After this register has been written,
+ * the USB module begins the specified USB transaction to the address contained in
+ * the address register. The processor core must always check that the
+ * TOKEN_BUSY bit in the control register is not 1 before writing to the Token Register.
+ * This ensures that the token commands are not overwritten before they can be
+ * executed. The address register and endpoint control register 0 are also used when
+ * performing a token command and therefore must also be written before the
+ * Token Register. The address register is used to select the USB peripheral address
+ * transmitted by the token command. The endpoint control register determines the
+ * handshake and retry policies used during the transfer.
+ */
+/*!
+ * @name Constants and macros for entire USB_TOKEN register
+ */
+/*@{*/
+#define USB_RD_TOKEN(base)       (USB_TOKEN_REG(base))
+#define USB_WR_TOKEN(base, value) (USB_TOKEN_REG(base) = (value))
+#define USB_RMW_TOKEN(base, mask, value) (USB_WR_TOKEN(base, (USB_RD_TOKEN(base) & ~(mask)) | (value)))
+#define USB_SET_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) |  (value)))
+#define USB_CLR_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) & ~(value)))
+#define USB_TOG_TOKEN(base, value) (USB_WR_TOKEN(base, USB_RD_TOKEN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_TOKEN bitfields
+ */
+
+/*!
+ * @name Register USB_TOKEN, field TOKENENDPT[3:0] (RW)
+ *
+ * Holds the Endpoint address for the token command. The four bit value written
+ * must be a valid endpoint.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_TOKEN_TOKENENDPT field. */
+#define USB_RD_TOKEN_TOKENENDPT(base) ((USB_TOKEN_REG(base) & USB_TOKEN_TOKENENDPT_MASK) >> USB_TOKEN_TOKENENDPT_SHIFT)
+#define USB_BRD_TOKEN_TOKENENDPT(base) (USB_RD_TOKEN_TOKENENDPT(base))
+
+/*! @brief Set the TOKENENDPT field to a new value. */
+#define USB_WR_TOKEN_TOKENENDPT(base, value) (USB_RMW_TOKEN(base, USB_TOKEN_TOKENENDPT_MASK, USB_TOKEN_TOKENENDPT(value)))
+#define USB_BWR_TOKEN_TOKENENDPT(base, value) (USB_WR_TOKEN_TOKENENDPT(base, value))
+/*@}*/
+
+/*!
+ * @name Register USB_TOKEN, field TOKENPID[7:4] (RW)
+ *
+ * Contains the token type executed by the USB module.
+ *
+ * Values:
+ * - 0b0001 - OUT Token. USB Module performs an OUT (TX) transaction.
+ * - 0b1001 - IN Token. USB Module performs an In (RX) transaction.
+ * - 0b1101 - SETUP Token. USB Module performs a SETUP (TX) transaction
+ */
+/*@{*/
+/*! @brief Read current value of the USB_TOKEN_TOKENPID field. */
+#define USB_RD_TOKEN_TOKENPID(base) ((USB_TOKEN_REG(base) & USB_TOKEN_TOKENPID_MASK) >> USB_TOKEN_TOKENPID_SHIFT)
+#define USB_BRD_TOKEN_TOKENPID(base) (USB_RD_TOKEN_TOKENPID(base))
+
+/*! @brief Set the TOKENPID field to a new value. */
+#define USB_WR_TOKEN_TOKENPID(base, value) (USB_RMW_TOKEN(base, USB_TOKEN_TOKENPID_MASK, USB_TOKEN_TOKENPID(value)))
+#define USB_BWR_TOKEN_TOKENPID(base, value) (USB_WR_TOKEN_TOKENPID(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_SOFTHLD - SOF Threshold register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_SOFTHLD - SOF Threshold register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * The SOF Threshold Register is used only in Host mode (HOSTMODEEN=1). When in
+ * Host mode, the 14-bit SOF counter counts the interval between SOF frames. The
+ * SOF must be transmitted every 1ms so therefore the SOF counter is loaded with
+ * a value of 12000. When the SOF counter reaches zero, a Start Of Frame (SOF)
+ * token is transmitted. The SOF threshold register is used to program the number
+ * of USB byte times before the SOF to stop initiating token packet transactions.
+ * This register must be set to a value that ensures that other packets are not
+ * actively being transmitted when the SOF time counts to zero. When the SOF
+ * counter reaches the threshold value, no more tokens are transmitted until after the
+ * SOF has been transmitted. The value programmed into the threshold register
+ * must reserve enough time to ensure the worst case transaction completes. In
+ * general the worst case transaction is an IN token followed by a data packet from
+ * the target followed by the response from the host. The actual time required is
+ * a function of the maximum packet size on the bus. Typical values for the SOF
+ * threshold are: 64-byte packets=74; 32-byte packets=42; 16-byte packets=26;
+ * 8-byte packets=18.
+ */
+/*!
+ * @name Constants and macros for entire USB_SOFTHLD register
+ */
+/*@{*/
+#define USB_RD_SOFTHLD(base)     (USB_SOFTHLD_REG(base))
+#define USB_WR_SOFTHLD(base, value) (USB_SOFTHLD_REG(base) = (value))
+#define USB_RMW_SOFTHLD(base, mask, value) (USB_WR_SOFTHLD(base, (USB_RD_SOFTHLD(base) & ~(mask)) | (value)))
+#define USB_SET_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) |  (value)))
+#define USB_CLR_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) & ~(value)))
+#define USB_TOG_SOFTHLD(base, value) (USB_WR_SOFTHLD(base, USB_RD_SOFTHLD(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE2 - BDT Page Register 2
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE2 - BDT Page Register 2 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE2 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE2(base)    (USB_BDTPAGE2_REG(base))
+#define USB_WR_BDTPAGE2(base, value) (USB_BDTPAGE2_REG(base) = (value))
+#define USB_RMW_BDTPAGE2(base, mask, value) (USB_WR_BDTPAGE2(base, (USB_RD_BDTPAGE2(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) |  (value)))
+#define USB_CLR_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) & ~(value)))
+#define USB_TOG_BDTPAGE2(base, value) (USB_WR_BDTPAGE2(base, USB_RD_BDTPAGE2(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_BDTPAGE3 - BDT Page Register 3
+ ******************************************************************************/
+
+/*!
+ * @brief USB_BDTPAGE3 - BDT Page Register 3 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains an 8-bit value used to compute the address where the current Buffer
+ * Descriptor Table (BDT) resides in system memory. See Buffer Descriptor Table.
+ */
+/*!
+ * @name Constants and macros for entire USB_BDTPAGE3 register
+ */
+/*@{*/
+#define USB_RD_BDTPAGE3(base)    (USB_BDTPAGE3_REG(base))
+#define USB_WR_BDTPAGE3(base, value) (USB_BDTPAGE3_REG(base) = (value))
+#define USB_RMW_BDTPAGE3(base, mask, value) (USB_WR_BDTPAGE3(base, (USB_RD_BDTPAGE3(base) & ~(mask)) | (value)))
+#define USB_SET_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) |  (value)))
+#define USB_CLR_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) & ~(value)))
+#define USB_TOG_BDTPAGE3(base, value) (USB_WR_BDTPAGE3(base, USB_RD_BDTPAGE3(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_ENDPT - Endpoint Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_ENDPT - Endpoint Control register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Contains the endpoint control bits for each of the 16 endpoints available
+ * within the USB module for a decoded address. The format for these registers is
+ * shown in the following figure. Endpoint 0 (ENDPT0) is associated with control
+ * pipe 0, which is required for all USB functions. Therefore, after a USBRST
+ * interrupt occurs the processor core should set ENDPT0 to contain 0x0D. In Host mode
+ * ENDPT0 is used to determine the handshake, retry and low speed
+ * characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the EPHSHK
+ * bit should be 1. For Isochronous transfers it should be 0. Common values to
+ * use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers,
+ * and 0x4C for Isochronous transfers. The three bits EPCTLDIS, EPRXEN, and
+ * EPTXEN define if an endpoint is enabled and define the direction of the endpoint.
+ * The endpoint enable/direction control is defined in the following table.
+ * Endpoint enable and direction control EPCTLDIS EPRXEN EPTXEN Endpoint
+ * enable/direction control X 0 0 Disable endpoint X 0 1 Enable endpoint for Tx transfers only
+ * X 1 0 Enable endpoint for Rx transfers only 1 1 1 Enable endpoint for Rx and
+ * Tx transfers 0 1 1 Enable Endpoint for RX and TX as well as control (SETUP)
+ * transfers.
+ */
+/*!
+ * @name Constants and macros for entire USB_ENDPT register
+ */
+/*@{*/
+#define USB_RD_ENDPT(base, index) (USB_ENDPT_REG(base, index))
+#define USB_WR_ENDPT(base, index, value) (USB_ENDPT_REG(base, index) = (value))
+#define USB_RMW_ENDPT(base, index, mask, value) (USB_WR_ENDPT(base, index, (USB_RD_ENDPT(base, index) & ~(mask)) | (value)))
+#define USB_SET_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) |  (value)))
+#define USB_CLR_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) & ~(value)))
+#define USB_TOG_ENDPT(base, index, value) (USB_WR_ENDPT(base, index, USB_RD_ENDPT(base, index) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_ENDPT bitfields
+ */
+
+/*!
+ * @name Register USB_ENDPT, field EPHSHK[0] (RW)
+ *
+ * When set this bit enables an endpoint to perform handshaking during a
+ * transaction to this endpoint. This bit is generally 1 unless the endpoint is
+ * Isochronous.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPHSHK field. */
+#define USB_RD_ENDPT_EPHSHK(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPHSHK_MASK) >> USB_ENDPT_EPHSHK_SHIFT)
+#define USB_BRD_ENDPT_EPHSHK(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT))
+
+/*! @brief Set the EPHSHK field to a new value. */
+#define USB_WR_ENDPT_EPHSHK(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPHSHK_MASK, USB_ENDPT_EPHSHK(value)))
+#define USB_BWR_ENDPT_EPHSHK(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPHSHK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPSTALL[1] (RW)
+ *
+ * When set this bit indicates that the endpoint is called. This bit has
+ * priority over all other control bits in the EndPoint Enable Register, but it is only
+ * valid if EPTXEN=1 or EPRXEN=1. Any access to this endpoint causes the USB
+ * Module to return a STALL handshake. After an endpoint is stalled it requires
+ * intervention from the Host Controller.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPSTALL field. */
+#define USB_RD_ENDPT_EPSTALL(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPSTALL_MASK) >> USB_ENDPT_EPSTALL_SHIFT)
+#define USB_BRD_ENDPT_EPSTALL(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT))
+
+/*! @brief Set the EPSTALL field to a new value. */
+#define USB_WR_ENDPT_EPSTALL(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPSTALL_MASK, USB_ENDPT_EPSTALL(value)))
+#define USB_BWR_ENDPT_EPSTALL(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPSTALL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPTXEN[2] (RW)
+ *
+ * This bit, when set, enables the endpoint for TX transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPTXEN field. */
+#define USB_RD_ENDPT_EPTXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPTXEN_MASK) >> USB_ENDPT_EPTXEN_SHIFT)
+#define USB_BRD_ENDPT_EPTXEN(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT))
+
+/*! @brief Set the EPTXEN field to a new value. */
+#define USB_WR_ENDPT_EPTXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPTXEN_MASK, USB_ENDPT_EPTXEN(value)))
+#define USB_BWR_ENDPT_EPTXEN(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPTXEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPRXEN[3] (RW)
+ *
+ * This bit, when set, enables the endpoint for RX transfers.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPRXEN field. */
+#define USB_RD_ENDPT_EPRXEN(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPRXEN_MASK) >> USB_ENDPT_EPRXEN_SHIFT)
+#define USB_BRD_ENDPT_EPRXEN(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT))
+
+/*! @brief Set the EPRXEN field to a new value. */
+#define USB_WR_ENDPT_EPRXEN(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPRXEN_MASK, USB_ENDPT_EPRXEN(value)))
+#define USB_BWR_ENDPT_EPRXEN(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPRXEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field EPCTLDIS[4] (RW)
+ *
+ * This bit, when set, disables control (SETUP) transfers. When cleared, control
+ * transfers are enabled. This applies if and only if the EPRXEN and EPTXEN bits
+ * are also set.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_EPCTLDIS field. */
+#define USB_RD_ENDPT_EPCTLDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_EPCTLDIS_MASK) >> USB_ENDPT_EPCTLDIS_SHIFT)
+#define USB_BRD_ENDPT_EPCTLDIS(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT))
+
+/*! @brief Set the EPCTLDIS field to a new value. */
+#define USB_WR_ENDPT_EPCTLDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_EPCTLDIS_MASK, USB_ENDPT_EPCTLDIS(value)))
+#define USB_BWR_ENDPT_EPCTLDIS(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_EPCTLDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field RETRYDIS[6] (RW)
+ *
+ * This is a Host mode only bit and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit causes the host to not retry NAK'ed
+ * (Negative Acknowledgement) transactions. When a transaction is NAKed, the BDT PID
+ * field is updated with the NAK PID, and the TOKEN_DNE interrupt is set. When
+ * this bit is cleared, NAKed transactions are retried in hardware. This bit must
+ * be set when the host is attempting to poll an interrupt endpoint.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_RETRYDIS field. */
+#define USB_RD_ENDPT_RETRYDIS(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_RETRYDIS_MASK) >> USB_ENDPT_RETRYDIS_SHIFT)
+#define USB_BRD_ENDPT_RETRYDIS(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_RETRYDIS_SHIFT))
+
+/*! @brief Set the RETRYDIS field to a new value. */
+#define USB_WR_ENDPT_RETRYDIS(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_RETRYDIS_MASK, USB_ENDPT_RETRYDIS(value)))
+#define USB_BWR_ENDPT_RETRYDIS(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_RETRYDIS_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_ENDPT, field HOSTWOHUB[7] (RW)
+ *
+ * This is a Host mode only field and is present in the control register for
+ * endpoint 0 (ENDPT0) only. When set this bit allows the host to communicate to a
+ * directly connected low speed device. When cleared, the host produces the
+ * PRE_PID. It then switches to low-speed signaling when sending a token to a low speed
+ * device as required to communicate with a low speed device through a hub.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_ENDPT_HOSTWOHUB field. */
+#define USB_RD_ENDPT_HOSTWOHUB(base, index) ((USB_ENDPT_REG(base, index) & USB_ENDPT_HOSTWOHUB_MASK) >> USB_ENDPT_HOSTWOHUB_SHIFT)
+#define USB_BRD_ENDPT_HOSTWOHUB(base, index) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_HOSTWOHUB_SHIFT))
+
+/*! @brief Set the HOSTWOHUB field to a new value. */
+#define USB_WR_ENDPT_HOSTWOHUB(base, index, value) (USB_RMW_ENDPT(base, index, USB_ENDPT_HOSTWOHUB_MASK, USB_ENDPT_HOSTWOHUB(value)))
+#define USB_BWR_ENDPT_HOSTWOHUB(base, index, value) (BITBAND_ACCESS8(&USB_ENDPT_REG(base, index), USB_ENDPT_HOSTWOHUB_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBCTRL - USB Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBCTRL - USB Control register (RW)
+ *
+ * Reset value: 0xC0U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBCTRL register
+ */
+/*@{*/
+#define USB_RD_USBCTRL(base)     (USB_USBCTRL_REG(base))
+#define USB_WR_USBCTRL(base, value) (USB_USBCTRL_REG(base) = (value))
+#define USB_RMW_USBCTRL(base, mask, value) (USB_WR_USBCTRL(base, (USB_RD_USBCTRL(base) & ~(mask)) | (value)))
+#define USB_SET_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) |  (value)))
+#define USB_CLR_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) & ~(value)))
+#define USB_TOG_USBCTRL(base, value) (USB_WR_USBCTRL(base, USB_RD_USBCTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBCTRL bitfields
+ */
+
+/*!
+ * @name Register USB_USBCTRL, field PDE[6] (RW)
+ *
+ * Enables the weak pulldowns on the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - Weak pulldowns are disabled on D+ and D-.
+ * - 0b1 - Weak pulldowns are enabled on D+ and D-.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_PDE field. */
+#define USB_RD_USBCTRL_PDE(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_PDE_MASK) >> USB_USBCTRL_PDE_SHIFT)
+#define USB_BRD_USBCTRL_PDE(base) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT))
+
+/*! @brief Set the PDE field to a new value. */
+#define USB_WR_USBCTRL_PDE(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_PDE_MASK, USB_USBCTRL_PDE(value)))
+#define USB_BWR_USBCTRL_PDE(base, value) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_PDE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_USBCTRL, field SUSP[7] (RW)
+ *
+ * Places the USB transceiver into the suspend state.
+ *
+ * Values:
+ * - 0b0 - USB transceiver is not in suspend state.
+ * - 0b1 - USB transceiver is in suspend state.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBCTRL_SUSP field. */
+#define USB_RD_USBCTRL_SUSP(base) ((USB_USBCTRL_REG(base) & USB_USBCTRL_SUSP_MASK) >> USB_USBCTRL_SUSP_SHIFT)
+#define USB_BRD_USBCTRL_SUSP(base) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT))
+
+/*! @brief Set the SUSP field to a new value. */
+#define USB_WR_USBCTRL_SUSP(base, value) (USB_RMW_USBCTRL(base, USB_USBCTRL_SUSP_MASK, USB_USBCTRL_SUSP(value)))
+#define USB_BWR_USBCTRL_SUSP(base, value) (BITBAND_ACCESS8(&USB_USBCTRL_REG(base), USB_USBCTRL_SUSP_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_OBSERVE - USB OTG Observe register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_OBSERVE - USB OTG Observe register (RO)
+ *
+ * Reset value: 0x50U
+ *
+ * Provides visibility on the state of the pull-ups and pull-downs at the
+ * transceiver. Useful when interfacing to an external OTG control module via a serial
+ * interface.
+ */
+/*!
+ * @name Constants and macros for entire USB_OBSERVE register
+ */
+/*@{*/
+#define USB_RD_OBSERVE(base)     (USB_OBSERVE_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_OBSERVE bitfields
+ */
+
+/*!
+ * @name Register USB_OBSERVE, field DMPD[4] (RO)
+ *
+ * Provides observability of the D- Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D- pulldown disabled.
+ * - 0b1 - D- pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DMPD field. */
+#define USB_RD_OBSERVE_DMPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DMPD_MASK) >> USB_OBSERVE_DMPD_SHIFT)
+#define USB_BRD_OBSERVE_DMPD(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DMPD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPD[6] (RO)
+ *
+ * Provides observability of the D+ Pulldown enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D+ pulldown disabled.
+ * - 0b1 - D+ pulldown enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPD field. */
+#define USB_RD_OBSERVE_DPPD(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPD_MASK) >> USB_OBSERVE_DPPD_SHIFT)
+#define USB_BRD_OBSERVE_DPPD(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPD_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_OBSERVE, field DPPU[7] (RO)
+ *
+ * Provides observability of the D+ Pullup enable at the USB transceiver.
+ *
+ * Values:
+ * - 0b0 - D+ pullup disabled.
+ * - 0b1 - D+ pullup enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_OBSERVE_DPPU field. */
+#define USB_RD_OBSERVE_DPPU(base) ((USB_OBSERVE_REG(base) & USB_OBSERVE_DPPU_MASK) >> USB_OBSERVE_DPPU_SHIFT)
+#define USB_BRD_OBSERVE_DPPU(base) (BITBAND_ACCESS8(&USB_OBSERVE_REG(base), USB_OBSERVE_DPPU_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CONTROL - USB OTG Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CONTROL - USB OTG Control register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_CONTROL register
+ */
+/*@{*/
+#define USB_RD_CONTROL(base)     (USB_CONTROL_REG(base))
+#define USB_WR_CONTROL(base, value) (USB_CONTROL_REG(base) = (value))
+#define USB_RMW_CONTROL(base, mask, value) (USB_WR_CONTROL(base, (USB_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USB_SET_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) |  (value)))
+#define USB_CLR_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) & ~(value)))
+#define USB_TOG_CONTROL(base, value) (USB_WR_CONTROL(base, USB_RD_CONTROL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USB_CONTROL, field DPPULLUPNONOTG[4] (RW)
+ *
+ * Provides control of the DP Pullup in USBOTG, if USB is configured in non-OTG
+ * device mode.
+ *
+ * Values:
+ * - 0b0 - DP Pullup in non-OTG device mode is not enabled.
+ * - 0b1 - DP Pullup in non-OTG device mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CONTROL_DPPULLUPNONOTG field. */
+#define USB_RD_CONTROL_DPPULLUPNONOTG(base) ((USB_CONTROL_REG(base) & USB_CONTROL_DPPULLUPNONOTG_MASK) >> USB_CONTROL_DPPULLUPNONOTG_SHIFT)
+#define USB_BRD_CONTROL_DPPULLUPNONOTG(base) (BITBAND_ACCESS8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT))
+
+/*! @brief Set the DPPULLUPNONOTG field to a new value. */
+#define USB_WR_CONTROL_DPPULLUPNONOTG(base, value) (USB_RMW_CONTROL(base, USB_CONTROL_DPPULLUPNONOTG_MASK, USB_CONTROL_DPPULLUPNONOTG(value)))
+#define USB_BWR_CONTROL_DPPULLUPNONOTG(base, value) (BITBAND_ACCESS8(&USB_CONTROL_REG(base), USB_CONTROL_DPPULLUPNONOTG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBTRC0 - USB Transceiver Control register 0
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBTRC0 - USB Transceiver Control register 0 (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Includes signals for basic operation of the on-chip USB Full Speed
+ * transceiver and configuration of the USB data connection that are not otherwise included
+ * in the USB Full Speed controller registers.
+ */
+/*!
+ * @name Constants and macros for entire USB_USBTRC0 register
+ */
+/*@{*/
+#define USB_RD_USBTRC0(base)     (USB_USBTRC0_REG(base))
+#define USB_WR_USBTRC0(base, value) (USB_USBTRC0_REG(base) = (value))
+#define USB_RMW_USBTRC0(base, mask, value) (USB_WR_USBTRC0(base, (USB_RD_USBTRC0(base) & ~(mask)) | (value)))
+#define USB_SET_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) |  (value)))
+#define USB_CLR_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) & ~(value)))
+#define USB_TOG_USBTRC0(base, value) (USB_WR_USBTRC0(base, USB_RD_USBTRC0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_USBTRC0 bitfields
+ */
+
+/*!
+ * @name Register USB_USBTRC0, field USB_RESUME_INT[0] (RO)
+ *
+ * Values:
+ * - 0b0 - No interrupt was generated.
+ * - 0b1 - Interrupt was generated because of the USB asynchronous interrupt.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_RESUME_INT field. */
+#define USB_RD_USBTRC0_USB_RESUME_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_RESUME_INT_MASK) >> USB_USBTRC0_USB_RESUME_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_RESUME_INT(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_RESUME_INT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field SYNC_DET[1] (RO)
+ *
+ * Values:
+ * - 0b0 - Synchronous interrupt has not been detected.
+ * - 0b1 - Synchronous interrupt has been detected.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_SYNC_DET field. */
+#define USB_RD_USBTRC0_SYNC_DET(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_SYNC_DET_MASK) >> USB_USBTRC0_SYNC_DET_SHIFT)
+#define USB_BRD_USBTRC0_SYNC_DET(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_SYNC_DET_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USB_CLK_RECOVERY_INT[2] (RO)
+ *
+ * This read-only field will be set to value high at 1'b1 when any of USB clock
+ * recovery interrupt conditions are detected and those interrupts are unmasked.
+ * For customer use the only unmasked USB clock recovery interrupt condition
+ * results from an overflow of the frequency trim setting values indicating that the
+ * frequency trim calculated is out of the adjustment range of the IRC48M output
+ * clock. To clear this bit after it has been set, Write 0xFF to register
+ * USB_CLK_RECOVER_INT_STATUS.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USB_CLK_RECOVERY_INT field. */
+#define USB_RD_USBTRC0_USB_CLK_RECOVERY_INT(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) >> USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)
+#define USB_BRD_USBTRC0_USB_CLK_RECOVERY_INT(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESMEN[5] (RW)
+ *
+ * This bit, when set, allows the USB module to send an asynchronous wakeup
+ * event to the MCU upon detection of resume signaling on the USB bus. The MCU then
+ * re-enables clocks to the USB module. It is used for low-power suspend mode when
+ * USB module clocks are stopped or the USB transceiver is in Suspend mode.
+ * Async wakeup only works in device mode.
+ *
+ * Values:
+ * - 0b0 - USB asynchronous wakeup from suspend mode disabled.
+ * - 0b1 - USB asynchronous wakeup from suspend mode enabled. The asynchronous
+ *     resume interrupt differs from the synchronous resume interrupt in that it
+ *     asynchronously detects K-state using the unfiltered state of the D+ and D-
+ *     pins. This interrupt should only be enabled when the Transceiver is
+ *     suspended.
+ */
+/*@{*/
+/*! @brief Read current value of the USB_USBTRC0_USBRESMEN field. */
+#define USB_RD_USBTRC0_USBRESMEN(base) ((USB_USBTRC0_REG(base) & USB_USBTRC0_USBRESMEN_MASK) >> USB_USBTRC0_USBRESMEN_SHIFT)
+#define USB_BRD_USBTRC0_USBRESMEN(base) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT))
+
+/*! @brief Set the USBRESMEN field to a new value. */
+#define USB_WR_USBTRC0_USBRESMEN(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESMEN_MASK, USB_USBTRC0_USBRESMEN(value)))
+#define USB_BWR_USBTRC0_USBRESMEN(base, value) (BITBAND_ACCESS8(&USB_USBTRC0_REG(base), USB_USBTRC0_USBRESMEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_USBTRC0, field USBRESET[7] (WO)
+ *
+ * Generates a hard reset to USBOTG. After this bit is set and the reset occurs,
+ * this bit is automatically cleared. This bit is always read as zero. Wait two
+ * USB clock cycles after setting this bit.
+ *
+ * Values:
+ * - 0b0 - Normal USB module operation.
+ * - 0b1 - Returns the USB module to its reset state.
+ */
+/*@{*/
+/*! @brief Set the USBRESET field to a new value. */
+#define USB_WR_USBTRC0_USBRESET(base, value) (USB_RMW_USBTRC0(base, USB_USBTRC0_USBRESET_MASK, USB_USBTRC0_USBRESET(value)))
+#define USB_BWR_USBTRC0_USBRESET(base, value) (USB_WR_USBTRC0_USBRESET(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_USBFRMADJUST - Frame Adjust Register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_USBFRMADJUST - Frame Adjust Register (RW)
+ *
+ * Reset value: 0x00U
+ */
+/*!
+ * @name Constants and macros for entire USB_USBFRMADJUST register
+ */
+/*@{*/
+#define USB_RD_USBFRMADJUST(base) (USB_USBFRMADJUST_REG(base))
+#define USB_WR_USBFRMADJUST(base, value) (USB_USBFRMADJUST_REG(base) = (value))
+#define USB_RMW_USBFRMADJUST(base, mask, value) (USB_WR_USBFRMADJUST(base, (USB_RD_USBFRMADJUST(base) & ~(mask)) | (value)))
+#define USB_SET_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) |  (value)))
+#define USB_CLR_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) & ~(value)))
+#define USB_TOG_USBFRMADJUST(base, value) (USB_WR_USBFRMADJUST(base, USB_RD_USBFRMADJUST(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_CTRL - USB Clock recovery control
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_CTRL - USB Clock recovery control (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * Signals in this register control the crystal-less USB clock mode in which the
+ * internal IRC48M oscillator is tuned to match the clock extracted from the
+ * incoming USB data stream. The IRC48M internal oscillator module must be enabled
+ * in register USB_CLK_RECOVER_IRC_EN for this mode.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_CTRL register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_CTRL(base) (USB_CLK_RECOVER_CTRL_REG(base))
+#define USB_WR_CLK_RECOVER_CTRL(base, value) (USB_CLK_RECOVER_CTRL_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_CTRL(base, mask, value) (USB_WR_CLK_RECOVER_CTRL(base, (USB_RD_CLK_RECOVER_CTRL(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_CTRL(base, value) (USB_WR_CLK_RECOVER_CTRL(base, USB_RD_CLK_RECOVER_CTRL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_CTRL bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESTART_IFRTRIM_EN[5] (RW)
+ *
+ * IRC48 has a default trim fine value whose default value is factory trimmed
+ * (the IFR trim value). Clock recover block tracks the accuracy of the clock 48Mhz
+ * and keeps updating the trim fine value accordingly
+ *
+ * Values:
+ * - 0b0 - Trim fine adjustment always works based on the previous updated trim
+ *     fine value (default)
+ * - 0b1 - Trim fine restarts from the IFR trim value whenever
+ *     bus_reset/bus_resume is detected or module enable is desasserted
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))
+
+/*! @brief Set the RESTART_IFRTRIM_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK, USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field RESET_RESUME_ROUGH_EN[6] (RW)
+ *
+ * The clock recovery block tracks the IRC48Mhz to get an accurate 48Mhz clock.
+ * It has two phases after user enables clock_recover_en bit, rough phase and
+ * tracking phase. The step to fine tune the IRC 48Mhz by adjusting the trim fine
+ * value is different during these two phases. The step in rough phase is larger
+ * than that in tracking phase. Switch back to rough stage whenever USB bus reset
+ * or bus resume occurs.
+ *
+ * Values:
+ * - 0b0 - Always works in tracking phase after the 1st time rough to track
+ *     transition (default)
+ * - 0b1 - Go back to rough stage whenever bus reset or bus resume occurs
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) >> USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))
+
+/*! @brief Set the RESET_RESUME_ROUGH_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK, USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_CTRL, field CLOCK_RECOVER_EN[7] (RW)
+ *
+ * This bit must be enabled if user wants to use the crystal-less USB mode for
+ * the Full Speed USB controller and transceiver. This bit should not be set for
+ * USB host mode or OTG.
+ *
+ * Values:
+ * - 0b0 - Disable clock recovery block (default)
+ * - 0b1 - Enable clock recovery block
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN field. */
+#define USB_RD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) ((USB_CLK_RECOVER_CTRL_REG(base) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) >> USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))
+
+/*! @brief Set the CLOCK_RECOVER_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (USB_RMW_CLK_RECOVER_CTRL(base, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK, USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(value)))
+#define USB_BWR_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_CTRL_REG(base), USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_IRC_EN - IRC48M oscillator enable register (RW)
+ *
+ * Reset value: 0x01U
+ *
+ * Controls basic operation of the on-chip IRC48M module used to produce nominal
+ * 48MHz clocks for USB crystal-less operation and other functions. See
+ * additional information about the IRC48M operation in the Clock Distribution chapter.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_IRC_EN register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_IRC_EN(base) (USB_CLK_RECOVER_IRC_EN_REG(base))
+#define USB_WR_CLK_RECOVER_IRC_EN(base, value) (USB_CLK_RECOVER_IRC_EN_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_IRC_EN(base, mask, value) (USB_WR_CLK_RECOVER_IRC_EN(base, (USB_RD_CLK_RECOVER_IRC_EN(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_IRC_EN(base, value) (USB_WR_CLK_RECOVER_IRC_EN(base, USB_RD_CLK_RECOVER_IRC_EN(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_IRC_EN bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field REG_EN[0] (RW)
+ *
+ * This bit is used to enable the local analog regulator for IRC48Mhz module.
+ * This bit must be set if user wants to use the crystal-less USB clock
+ * configuration.
+ *
+ * Values:
+ * - 0b0 - IRC48M local regulator is disabled
+ * - 0b1 - IRC48M local regulator is enabled (default)
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_REG_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_REG_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_REG_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))
+
+/*! @brief Set the REG_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_REG_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_REG_EN_MASK, USB_CLK_RECOVER_IRC_EN_REG_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_REG_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USB_CLK_RECOVER_IRC_EN, field IRC_EN[1] (RW)
+ *
+ * This bit is used to enable the on-chip IRC48Mhz module to generate clocks for
+ * crystal-less USB. It can only be used for FS USB device mode operation. This
+ * bit must be set before using the crystal-less USB clock configuration.
+ *
+ * Values:
+ * - 0b0 - Disable the IRC48M module (default)
+ * - 0b1 - Enable the IRC48M module
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_IRC_EN_IRC_EN field. */
+#define USB_RD_CLK_RECOVER_IRC_EN_IRC_EN(base) ((USB_CLK_RECOVER_IRC_EN_REG(base) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) >> USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)
+#define USB_BRD_CLK_RECOVER_IRC_EN_IRC_EN(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))
+
+/*! @brief Set the IRC_EN field to a new value. */
+#define USB_WR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (USB_RMW_CLK_RECOVER_IRC_EN(base, USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK, USB_CLK_RECOVER_IRC_EN_IRC_EN(value)))
+#define USB_BWR_CLK_RECOVER_IRC_EN_IRC_EN(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_IRC_EN_REG(base), USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status
+ ******************************************************************************/
+
+/*!
+ * @brief USB_CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status (W1C)
+ *
+ * Reset value: 0x00U
+ *
+ * A Write operation with value high at 1'b1 on any combination of individual
+ * bits will clear those bits.
+ */
+/*!
+ * @name Constants and macros for entire USB_CLK_RECOVER_INT_STATUS register
+ */
+/*@{*/
+#define USB_RD_CLK_RECOVER_INT_STATUS(base) (USB_CLK_RECOVER_INT_STATUS_REG(base))
+#define USB_WR_CLK_RECOVER_INT_STATUS(base, value) (USB_CLK_RECOVER_INT_STATUS_REG(base) = (value))
+#define USB_RMW_CLK_RECOVER_INT_STATUS(base, mask, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, (USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(mask)) | (value)))
+#define USB_SET_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) |  (value)))
+#define USB_CLR_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) & ~(value)))
+#define USB_TOG_CLK_RECOVER_INT_STATUS(base, value) (USB_WR_CLK_RECOVER_INT_STATUS(base, USB_RD_CLK_RECOVER_INT_STATUS(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USB_CLK_RECOVER_INT_STATUS bitfields
+ */
+
+/*!
+ * @name Register USB_CLK_RECOVER_INT_STATUS, field OVF_ERROR[4] (W1C)
+ *
+ * Indicates that the USB clock recovery algorithm has detected that the
+ * frequency trim adjustment needed for the IRC48M output clock is outside the available
+ * TRIM_FINE adjustment range for the IRC48M module.
+ *
+ * Values:
+ * - 0b0 - No interrupt is reported
+ * - 0b1 - Unmasked interrupt has been generated
+ */
+/*@{*/
+/*! @brief Read current value of the USB_CLK_RECOVER_INT_STATUS_OVF_ERROR field. */
+#define USB_RD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) ((USB_CLK_RECOVER_INT_STATUS_REG(base) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) >> USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)
+#define USB_BRD_CLK_RECOVER_INT_STATUS_OVF_ERROR(base) (BITBAND_ACCESS8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))
+
+/*! @brief Set the OVF_ERROR field to a new value. */
+#define USB_WR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (USB_RMW_CLK_RECOVER_INT_STATUS(base, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK, USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(value)))
+#define USB_BWR_CLK_RECOVER_INT_STATUS_OVF_ERROR(base, value) (BITBAND_ACCESS8(&USB_CLK_RECOVER_INT_STATUS_REG(base), USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 USBDCD
+ *
+ * USB Device Charger Detection module
+ *
+ * Registers defined in this header file:
+ * - USBDCD_CONTROL - Control register
+ * - USBDCD_CLOCK - Clock register
+ * - USBDCD_STATUS - Status register
+ * - USBDCD_TIMER0 - TIMER0 register
+ * - USBDCD_TIMER1 - TIMER1 register
+ * - USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ * - USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ */
+
+#define USBDCD_INSTANCE_COUNT (1U) /*!< Number of instances of the USBDCD module. */
+#define USBDCD_IDX (0U) /*!< Instance number for USBDCD. */
+
+/*******************************************************************************
+ * USBDCD_CONTROL - Control register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_CONTROL - Control register (RW)
+ *
+ * Reset value: 0x00010000U
+ *
+ * Contains the control and interrupt bit fields.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_CONTROL register
+ */
+/*@{*/
+#define USBDCD_RD_CONTROL(base)  (USBDCD_CONTROL_REG(base))
+#define USBDCD_WR_CONTROL(base, value) (USBDCD_CONTROL_REG(base) = (value))
+#define USBDCD_RMW_CONTROL(base, mask, value) (USBDCD_WR_CONTROL(base, (USBDCD_RD_CONTROL(base) & ~(mask)) | (value)))
+#define USBDCD_SET_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) |  (value)))
+#define USBDCD_CLR_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) & ~(value)))
+#define USBDCD_TOG_CONTROL(base, value) (USBDCD_WR_CONTROL(base, USBDCD_RD_CONTROL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_CONTROL bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CONTROL, field IACK[0] (WORZ)
+ *
+ * Determines whether the interrupt is cleared.
+ *
+ * Values:
+ * - 0b0 - Do not clear the interrupt.
+ * - 0b1 - Clear the IF bit (interrupt flag).
+ */
+/*@{*/
+/*! @brief Set the IACK field to a new value. */
+#define USBDCD_WR_CONTROL_IACK(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_IACK_MASK, USBDCD_CONTROL_IACK(value)))
+#define USBDCD_BWR_CONTROL_IACK(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IACK_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field IF[8] (RO)
+ *
+ * Determines whether an interrupt is pending.
+ *
+ * Values:
+ * - 0b0 - No interrupt is pending.
+ * - 0b1 - An interrupt is pending.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_IF field. */
+#define USBDCD_RD_CONTROL_IF(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_IF_MASK) >> USBDCD_CONTROL_IF_SHIFT)
+#define USBDCD_BRD_CONTROL_IF(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IF_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field IE[16] (RW)
+ *
+ * Enables/disables interrupts to the system.
+ *
+ * Values:
+ * - 0b0 - Disable interrupts to the system.
+ * - 0b1 - Enable interrupts to the system.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_IE field. */
+#define USBDCD_RD_CONTROL_IE(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_IE_MASK) >> USBDCD_CONTROL_IE_SHIFT)
+#define USBDCD_BRD_CONTROL_IE(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IE_SHIFT))
+
+/*! @brief Set the IE field to a new value. */
+#define USBDCD_WR_CONTROL_IE(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_IE_MASK, USBDCD_CONTROL_IE(value)))
+#define USBDCD_BWR_CONTROL_IE(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_IE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field BC12[17] (RW)
+ *
+ * BC1.2 compatibility. This bit cannot be changed after start detection.
+ *
+ * Values:
+ * - 0b0 - Compatible with BC1.1 (default)
+ * - 0b1 - Compatible with BC1.2
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CONTROL_BC12 field. */
+#define USBDCD_RD_CONTROL_BC12(base) ((USBDCD_CONTROL_REG(base) & USBDCD_CONTROL_BC12_MASK) >> USBDCD_CONTROL_BC12_SHIFT)
+#define USBDCD_BRD_CONTROL_BC12(base) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_BC12_SHIFT))
+
+/*! @brief Set the BC12 field to a new value. */
+#define USBDCD_WR_CONTROL_BC12(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_BC12_MASK, USBDCD_CONTROL_BC12(value)))
+#define USBDCD_BWR_CONTROL_BC12(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_BC12_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field START[24] (WORZ)
+ *
+ * Determines whether the charger detection sequence is initiated.
+ *
+ * Values:
+ * - 0b0 - Do not start the sequence. Writes of this value have no effect.
+ * - 0b1 - Initiate the charger detection sequence. If the sequence is already
+ *     running, writes of this value have no effect.
+ */
+/*@{*/
+/*! @brief Set the START field to a new value. */
+#define USBDCD_WR_CONTROL_START(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_START_MASK, USBDCD_CONTROL_START(value)))
+#define USBDCD_BWR_CONTROL_START(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_START_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CONTROL, field SR[25] (WORZ)
+ *
+ * Determines whether a software reset is performed.
+ *
+ * Values:
+ * - 0b0 - Do not perform a software reset.
+ * - 0b1 - Perform a software reset.
+ */
+/*@{*/
+/*! @brief Set the SR field to a new value. */
+#define USBDCD_WR_CONTROL_SR(base, value) (USBDCD_RMW_CONTROL(base, USBDCD_CONTROL_SR_MASK, USBDCD_CONTROL_SR(value)))
+#define USBDCD_BWR_CONTROL_SR(base, value) (BITBAND_ACCESS32(&USBDCD_CONTROL_REG(base), USBDCD_CONTROL_SR_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_CLOCK - Clock register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_CLOCK - Clock register (RW)
+ *
+ * Reset value: 0x000000C1U
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_CLOCK register
+ */
+/*@{*/
+#define USBDCD_RD_CLOCK(base)    (USBDCD_CLOCK_REG(base))
+#define USBDCD_WR_CLOCK(base, value) (USBDCD_CLOCK_REG(base) = (value))
+#define USBDCD_RMW_CLOCK(base, mask, value) (USBDCD_WR_CLOCK(base, (USBDCD_RD_CLOCK(base) & ~(mask)) | (value)))
+#define USBDCD_SET_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) |  (value)))
+#define USBDCD_CLR_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) & ~(value)))
+#define USBDCD_TOG_CLOCK(base, value) (USBDCD_WR_CLOCK(base, USBDCD_RD_CLOCK(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_CLOCK bitfields
+ */
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW)
+ *
+ * Specifies the unit of measure for the clock speed.
+ *
+ * Values:
+ * - 0b0 - kHz Speed (between 1 kHz and 1023 kHz)
+ * - 0b1 - MHz Speed (between 1 MHz and 1023 MHz)
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field. */
+#define USBDCD_RD_CLOCK_CLOCK_UNIT(base) ((USBDCD_CLOCK_REG(base) & USBDCD_CLOCK_CLOCK_UNIT_MASK) >> USBDCD_CLOCK_CLOCK_UNIT_SHIFT)
+#define USBDCD_BRD_CLOCK_CLOCK_UNIT(base) (BITBAND_ACCESS32(&USBDCD_CLOCK_REG(base), USBDCD_CLOCK_CLOCK_UNIT_SHIFT))
+
+/*! @brief Set the CLOCK_UNIT field to a new value. */
+#define USBDCD_WR_CLOCK_CLOCK_UNIT(base, value) (USBDCD_RMW_CLOCK(base, USBDCD_CLOCK_CLOCK_UNIT_MASK, USBDCD_CLOCK_CLOCK_UNIT(value)))
+#define USBDCD_BWR_CLOCK_CLOCK_UNIT(base, value) (BITBAND_ACCESS32(&USBDCD_CLOCK_REG(base), USBDCD_CLOCK_CLOCK_UNIT_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW)
+ *
+ * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to
+ * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples
+ * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz:
+ * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100)
+ * For 500 kHz: 0b01_1111_0100 (500)
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field. */
+#define USBDCD_RD_CLOCK_CLOCK_SPEED(base) ((USBDCD_CLOCK_REG(base) & USBDCD_CLOCK_CLOCK_SPEED_MASK) >> USBDCD_CLOCK_CLOCK_SPEED_SHIFT)
+#define USBDCD_BRD_CLOCK_CLOCK_SPEED(base) (USBDCD_RD_CLOCK_CLOCK_SPEED(base))
+
+/*! @brief Set the CLOCK_SPEED field to a new value. */
+#define USBDCD_WR_CLOCK_CLOCK_SPEED(base, value) (USBDCD_RMW_CLOCK(base, USBDCD_CLOCK_CLOCK_SPEED_MASK, USBDCD_CLOCK_CLOCK_SPEED(value)))
+#define USBDCD_BWR_CLOCK_CLOCK_SPEED(base, value) (USBDCD_WR_CLOCK_CLOCK_SPEED(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_STATUS - Status register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_STATUS - Status register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Provides the current state of the module for system software monitoring.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_STATUS register
+ */
+/*@{*/
+#define USBDCD_RD_STATUS(base)   (USBDCD_STATUS_REG(base))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_STATUS bitfields
+ */
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO)
+ *
+ * Reports how the charger detection is attached.
+ *
+ * Values:
+ * - 0b00 - No results to report.
+ * - 0b01 - Attached to a standard host. Must comply with USB 2.0 by drawing
+ *     only 2.5 mA (max) until connected.
+ * - 0b10 - Attached to a charging port. The exact meaning depends on bit 18: 0:
+ *     Attached to either a charging host or a dedicated charger. The charger
+ *     type detection has not completed. 1: Attached to a charging host. The
+ *     charger type detection has completed.
+ * - 0b11 - Attached to a dedicated charger.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_SEQ_RES field. */
+#define USBDCD_RD_STATUS_SEQ_RES(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_SEQ_RES_MASK) >> USBDCD_STATUS_SEQ_RES_SHIFT)
+#define USBDCD_BRD_STATUS_SEQ_RES(base) (USBDCD_RD_STATUS_SEQ_RES(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO)
+ *
+ * Indicates the status of the charger detection sequence.
+ *
+ * Values:
+ * - 0b00 - The module is either not enabled, or the module is enabled but the
+ *     data pins have not yet been detected.
+ * - 0b01 - Data pin contact detection is complete.
+ * - 0b10 - Charging port detection is complete.
+ * - 0b11 - Charger type detection is complete.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field. */
+#define USBDCD_RD_STATUS_SEQ_STAT(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_SEQ_STAT_MASK) >> USBDCD_STATUS_SEQ_STAT_SHIFT)
+#define USBDCD_BRD_STATUS_SEQ_STAT(base) (USBDCD_RD_STATUS_SEQ_STAT(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field ERR[20] (RO)
+ *
+ * Indicates whether there is an error in the detection sequence.
+ *
+ * Values:
+ * - 0b0 - No sequence errors.
+ * - 0b1 - Error in the detection sequence. See the SEQ_STAT field to determine
+ *     the phase in which the error occurred.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_ERR field. */
+#define USBDCD_RD_STATUS_ERR(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_ERR_MASK) >> USBDCD_STATUS_ERR_SHIFT)
+#define USBDCD_BRD_STATUS_ERR(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_ERR_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field TO[21] (RO)
+ *
+ * Indicates whether the detection sequence has passed the timeout threshhold.
+ *
+ * Values:
+ * - 0b0 - The detection sequence has not been running for over 1 s.
+ * - 0b1 - It has been over 1 s since the data pin contact was detected and
+ *     debounced.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_TO field. */
+#define USBDCD_RD_STATUS_TO(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_TO_MASK) >> USBDCD_STATUS_TO_SHIFT)
+#define USBDCD_BRD_STATUS_TO(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_TO_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_STATUS, field ACTIVE[22] (RO)
+ *
+ * Indicates whether the sequence is running.
+ *
+ * Values:
+ * - 0b0 - The sequence is not running.
+ * - 0b1 - The sequence is running.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_STATUS_ACTIVE field. */
+#define USBDCD_RD_STATUS_ACTIVE(base) ((USBDCD_STATUS_REG(base) & USBDCD_STATUS_ACTIVE_MASK) >> USBDCD_STATUS_ACTIVE_SHIFT)
+#define USBDCD_BRD_STATUS_ACTIVE(base) (BITBAND_ACCESS32(&USBDCD_STATUS_REG(base), USBDCD_STATUS_ACTIVE_SHIFT))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER0 - TIMER0 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER0 - TIMER0 register (RW)
+ *
+ * Reset value: 0x00100000U
+ *
+ * TIMER0 has an TSEQ_INIT field that represents the system latency in ms.
+ * Latency is measured from the time when VBUS goes active until the time system
+ * software initiates charger detection sequence in USBDCD module. When software sets
+ * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized
+ * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery
+ * Charging Specification requires the entire sequence, including TSEQ_INIT, to be
+ * completed in 1s or less.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER0 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER0(base)   (USBDCD_TIMER0_REG(base))
+#define USBDCD_WR_TIMER0(base, value) (USBDCD_TIMER0_REG(base) = (value))
+#define USBDCD_RMW_TIMER0(base, mask, value) (USBDCD_WR_TIMER0(base, (USBDCD_RD_TIMER0(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) |  (value)))
+#define USBDCD_CLR_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) & ~(value)))
+#define USBDCD_TOG_TIMER0(base, value) (USBDCD_WR_TIMER0(base, USBDCD_RD_TIMER0(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER0 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO)
+ *
+ * Displays the amount of elapsed time since the event of setting the START bit
+ * plus the value of TSEQ_INIT. The timer is automatically initialized with the
+ * value of TSEQ_INIT before starting to count. This timer enables compliance with
+ * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging
+ * Specification. If the timer reaches the one second limit, the module triggers
+ * an interrupt and sets the error flag STATUS[ERR]. The timer continues
+ * counting throughout the charger detection sequence, even when control has been passed
+ * to software. As long as the module is active, the timer continues to count
+ * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not
+ * rollover to zero. A software reset clears the timer.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER0_TUNITCON field. */
+#define USBDCD_RD_TIMER0_TUNITCON(base) ((USBDCD_TIMER0_REG(base) & USBDCD_TIMER0_TUNITCON_MASK) >> USBDCD_TIMER0_TUNITCON_SHIFT)
+#define USBDCD_BRD_TIMER0_TUNITCON(base) (USBDCD_RD_TIMER0_TUNITCON(base))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW)
+ *
+ * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS
+ * goes active to the time system software initiates the charger detection
+ * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit
+ * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid
+ * values are 0-1023, but the USB Battery Charging Specification requires the
+ * entire sequence, including TSEQ_INIT, to be completed in 1s or less.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field. */
+#define USBDCD_RD_TIMER0_TSEQ_INIT(base) ((USBDCD_TIMER0_REG(base) & USBDCD_TIMER0_TSEQ_INIT_MASK) >> USBDCD_TIMER0_TSEQ_INIT_SHIFT)
+#define USBDCD_BRD_TIMER0_TSEQ_INIT(base) (USBDCD_RD_TIMER0_TSEQ_INIT(base))
+
+/*! @brief Set the TSEQ_INIT field to a new value. */
+#define USBDCD_WR_TIMER0_TSEQ_INIT(base, value) (USBDCD_RMW_TIMER0(base, USBDCD_TIMER0_TSEQ_INIT_MASK, USBDCD_TIMER0_TSEQ_INIT(value)))
+#define USBDCD_BWR_TIMER0_TSEQ_INIT(base, value) (USBDCD_WR_TIMER0_TSEQ_INIT(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER1 - TIMER1 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER1 - TIMER1 register (RW)
+ *
+ * Reset value: 0x000A0028U
+ *
+ * TIMER1 contains timing parameters. Note that register values can be written
+ * that are not compliant with the USB Battery Charging Specification, so care
+ * should be taken when overwriting the default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER1 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER1(base)   (USBDCD_TIMER1_REG(base))
+#define USBDCD_WR_TIMER1(base, value) (USBDCD_TIMER1_REG(base) = (value))
+#define USBDCD_RMW_TIMER1(base, mask, value) (USBDCD_WR_TIMER1(base, (USBDCD_RD_TIMER1(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) |  (value)))
+#define USBDCD_CLR_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) & ~(value)))
+#define USBDCD_TOG_TIMER1(base, value) (USBDCD_WR_TIMER1(base, USBDCD_RD_TIMER1(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER1 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW)
+ *
+ * This timing parameter is used after detection of the data pin. See "Charging
+ * Port Detection". Valid values are 1-1023, but the USB Battery Charging
+ * Specification requires a minimum value of 40 ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field. */
+#define USBDCD_RD_TIMER1_TVDPSRC_ON(base) ((USBDCD_TIMER1_REG(base) & USBDCD_TIMER1_TVDPSRC_ON_MASK) >> USBDCD_TIMER1_TVDPSRC_ON_SHIFT)
+#define USBDCD_BRD_TIMER1_TVDPSRC_ON(base) (USBDCD_RD_TIMER1_TVDPSRC_ON(base))
+
+/*! @brief Set the TVDPSRC_ON field to a new value. */
+#define USBDCD_WR_TIMER1_TVDPSRC_ON(base, value) (USBDCD_RMW_TIMER1(base, USBDCD_TIMER1_TVDPSRC_ON_MASK, USBDCD_TIMER1_TVDPSRC_ON(value)))
+#define USBDCD_BWR_TIMER1_TVDPSRC_ON(base, value) (USBDCD_WR_TIMER1_TVDPSRC_ON(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW)
+ *
+ * Sets the time period (ms) to debounce the D+ signal during the data pin
+ * contact detection phase. See "Debouncing the data pin contact" Valid values are
+ * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10
+ * ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field. */
+#define USBDCD_RD_TIMER1_TDCD_DBNC(base) ((USBDCD_TIMER1_REG(base) & USBDCD_TIMER1_TDCD_DBNC_MASK) >> USBDCD_TIMER1_TDCD_DBNC_SHIFT)
+#define USBDCD_BRD_TIMER1_TDCD_DBNC(base) (USBDCD_RD_TIMER1_TDCD_DBNC(base))
+
+/*! @brief Set the TDCD_DBNC field to a new value. */
+#define USBDCD_WR_TIMER1_TDCD_DBNC(base, value) (USBDCD_RMW_TIMER1(base, USBDCD_TIMER1_TDCD_DBNC_MASK, USBDCD_TIMER1_TDCD_DBNC(value)))
+#define USBDCD_BWR_TIMER1_TDCD_DBNC(base, value) (USBDCD_WR_TIMER1_TDCD_DBNC(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER2_BC11 - TIMER2_BC11 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW)
+ *
+ * Reset value: 0x00280001U
+ *
+ * TIMER2_BC11 contains timing parameters for USB Battery Charging
+ * Specification, v1.1. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC11 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER2_BC11(base) (USBDCD_TIMER2_BC11_REG(base))
+#define USBDCD_WR_TIMER2_BC11(base, value) (USBDCD_TIMER2_BC11_REG(base) = (value))
+#define USBDCD_RMW_TIMER2_BC11(base, mask, value) (USBDCD_WR_TIMER2_BC11(base, (USBDCD_RD_TIMER2_BC11(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) |  (value)))
+#define USBDCD_CLR_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) & ~(value)))
+#define USBDCD_TOG_TIMER2_BC11(base, value) (USBDCD_WR_TIMER2_BC11(base, USBDCD_RD_TIMER2_BC11(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after the device
+ * connects to the USB bus until checking the state of the D- line to determine the
+ * type of charging port. See "Charger Type Detection." Valid values are 1-15ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field. */
+#define USBDCD_RD_TIMER2_BC11_CHECK_DM(base) ((USBDCD_TIMER2_BC11_REG(base) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) >> USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)
+#define USBDCD_BRD_TIMER2_BC11_CHECK_DM(base) (USBDCD_RD_TIMER2_BC11_CHECK_DM(base))
+
+/*! @brief Set the CHECK_DM field to a new value. */
+#define USBDCD_WR_TIMER2_BC11_CHECK_DM(base, value) (USBDCD_RMW_TIMER2_BC11(base, USBDCD_TIMER2_BC11_CHECK_DM_MASK, USBDCD_TIMER2_BC11_CHECK_DM(value)))
+#define USBDCD_BWR_TIMER2_BC11_CHECK_DM(base, value) (USBDCD_WR_TIMER2_BC11_CHECK_DM(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW)
+ *
+ * Sets the time period (ms) that the module waits after charging port detection
+ * before system software must enable the D+ pullup to connect to the USB host.
+ * Valid values are 1-1023, but the USB Battery Charging Specification requires a
+ * minimum value of 40 ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field. */
+#define USBDCD_RD_TIMER2_BC11_TVDPSRC_CON(base) ((USBDCD_TIMER2_BC11_REG(base) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) >> USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)
+#define USBDCD_BRD_TIMER2_BC11_TVDPSRC_CON(base) (USBDCD_RD_TIMER2_BC11_TVDPSRC_CON(base))
+
+/*! @brief Set the TVDPSRC_CON field to a new value. */
+#define USBDCD_WR_TIMER2_BC11_TVDPSRC_CON(base, value) (USBDCD_RMW_TIMER2_BC11(base, USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK, USBDCD_TIMER2_BC11_TVDPSRC_CON(value)))
+#define USBDCD_BWR_TIMER2_BC11_TVDPSRC_CON(base, value) (USBDCD_WR_TIMER2_BC11_TVDPSRC_CON(base, value))
+/*@}*/
+
+/*******************************************************************************
+ * USBDCD_TIMER2_BC12 - TIMER2_BC12 register
+ ******************************************************************************/
+
+/*!
+ * @brief USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW)
+ *
+ * Reset value: 0x00010028U
+ *
+ * TIMER2_BC12 contains timing parameters for USB Battery Charging
+ * Specification, v1.2. Register values can be written that are not compliant with the USB
+ * Battery Charging Specification, so care should be taken when overwriting the
+ * default values.
+ */
+/*!
+ * @name Constants and macros for entire USBDCD_TIMER2_BC12 register
+ */
+/*@{*/
+#define USBDCD_RD_TIMER2_BC12(base) (USBDCD_TIMER2_BC12_REG(base))
+#define USBDCD_WR_TIMER2_BC12(base, value) (USBDCD_TIMER2_BC12_REG(base) = (value))
+#define USBDCD_RMW_TIMER2_BC12(base, mask, value) (USBDCD_WR_TIMER2_BC12(base, (USBDCD_RD_TIMER2_BC12(base) & ~(mask)) | (value)))
+#define USBDCD_SET_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) |  (value)))
+#define USBDCD_CLR_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) & ~(value)))
+#define USBDCD_TOG_TIMER2_BC12(base, value) (USBDCD_WR_TIMER2_BC12(base, USBDCD_RD_TIMER2_BC12(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields
+ */
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW)
+ *
+ * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid
+ * values are 0-40ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field. */
+#define USBDCD_RD_TIMER2_BC12_TVDMSRC_ON(base) ((USBDCD_TIMER2_BC12_REG(base) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) >> USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)
+#define USBDCD_BRD_TIMER2_BC12_TVDMSRC_ON(base) (USBDCD_RD_TIMER2_BC12_TVDMSRC_ON(base))
+
+/*! @brief Set the TVDMSRC_ON field to a new value. */
+#define USBDCD_WR_TIMER2_BC12_TVDMSRC_ON(base, value) (USBDCD_RMW_TIMER2_BC12(base, USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK, USBDCD_TIMER2_BC12_TVDMSRC_ON(value)))
+#define USBDCD_BWR_TIMER2_BC12_TVDMSRC_ON(base, value) (USBDCD_WR_TIMER2_BC12_TVDMSRC_ON(base, value))
+/*@}*/
+
+/*!
+ * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW)
+ *
+ * Sets the amount of time (in ms) that the module waits after primary detection
+ * before start to secondary detection. Valid values are 1-1023ms. Default is
+ * 1ms.
+ */
+/*@{*/
+/*! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field. */
+#define USBDCD_RD_TIMER2_BC12_TWAIT_AFTER_PRD(base) ((USBDCD_TIMER2_BC12_REG(base) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) >> USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)
+#define USBDCD_BRD_TIMER2_BC12_TWAIT_AFTER_PRD(base) (USBDCD_RD_TIMER2_BC12_TWAIT_AFTER_PRD(base))
+
+/*! @brief Set the TWAIT_AFTER_PRD field to a new value. */
+#define USBDCD_WR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value) (USBDCD_RMW_TIMER2_BC12(base, USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK, USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(value)))
+#define USBDCD_BWR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value) (USBDCD_WR_TIMER2_BC12_TWAIT_AFTER_PRD(base, value))
+/*@}*/
+
+/*
+ * MK64F12 VREF
+ *
+ * Voltage Reference
+ *
+ * Registers defined in this header file:
+ * - VREF_TRM - VREF Trim Register
+ * - VREF_SC - VREF Status and Control Register
+ */
+
+#define VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
+#define VREF_IDX (0U) /*!< Instance number for VREF. */
+
+/*******************************************************************************
+ * VREF_TRM - VREF Trim Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_TRM - VREF Trim Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains bits that contain the trim data for the Voltage
+ * Reference.
+ */
+/*!
+ * @name Constants and macros for entire VREF_TRM register
+ */
+/*@{*/
+#define VREF_RD_TRM(base)        (VREF_TRM_REG(base))
+#define VREF_WR_TRM(base, value) (VREF_TRM_REG(base) = (value))
+#define VREF_RMW_TRM(base, mask, value) (VREF_WR_TRM(base, (VREF_RD_TRM(base) & ~(mask)) | (value)))
+#define VREF_SET_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) |  (value)))
+#define VREF_CLR_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) & ~(value)))
+#define VREF_TOG_TRM(base, value) (VREF_WR_TRM(base, VREF_RD_TRM(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_TRM bitfields
+ */
+
+/*!
+ * @name Register VREF_TRM, field TRIM[5:0] (RW)
+ *
+ * These bits change the resulting VREF by approximately +/- 0.5 mV for each
+ * step. Min = minimum and max = maximum voltage reference output. For minimum and
+ * maximum voltage reference output values, refer to the Data Sheet for this chip.
+ *
+ * Values:
+ * - 0b000000 - Min
+ * - 0b111111 - Max
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_TRIM field. */
+#define VREF_RD_TRM_TRIM(base) ((VREF_TRM_REG(base) & VREF_TRM_TRIM_MASK) >> VREF_TRM_TRIM_SHIFT)
+#define VREF_BRD_TRM_TRIM(base) (VREF_RD_TRM_TRIM(base))
+
+/*! @brief Set the TRIM field to a new value. */
+#define VREF_WR_TRM_TRIM(base, value) (VREF_RMW_TRM(base, VREF_TRM_TRIM_MASK, VREF_TRM_TRIM(value)))
+#define VREF_BWR_TRM_TRIM(base, value) (VREF_WR_TRM_TRIM(base, value))
+/*@}*/
+
+/*!
+ * @name Register VREF_TRM, field CHOPEN[6] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0b0 - Chop oscillator is disabled.
+ * - 0b1 - Chop oscillator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_TRM_CHOPEN field. */
+#define VREF_RD_TRM_CHOPEN(base) ((VREF_TRM_REG(base) & VREF_TRM_CHOPEN_MASK) >> VREF_TRM_CHOPEN_SHIFT)
+#define VREF_BRD_TRM_CHOPEN(base) (BITBAND_ACCESS8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT))
+
+/*! @brief Set the CHOPEN field to a new value. */
+#define VREF_WR_TRM_CHOPEN(base, value) (VREF_RMW_TRM(base, VREF_TRM_CHOPEN_MASK, VREF_TRM_CHOPEN(value)))
+#define VREF_BWR_TRM_CHOPEN(base, value) (BITBAND_ACCESS8(&VREF_TRM_REG(base), VREF_TRM_CHOPEN_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * VREF_SC - VREF Status and Control Register
+ ******************************************************************************/
+
+/*!
+ * @brief VREF_SC - VREF Status and Control Register (RW)
+ *
+ * Reset value: 0x00U
+ *
+ * This register contains the control bits used to enable the internal voltage
+ * reference and to select the buffer mode to be used.
+ */
+/*!
+ * @name Constants and macros for entire VREF_SC register
+ */
+/*@{*/
+#define VREF_RD_SC(base)         (VREF_SC_REG(base))
+#define VREF_WR_SC(base, value)  (VREF_SC_REG(base) = (value))
+#define VREF_RMW_SC(base, mask, value) (VREF_WR_SC(base, (VREF_RD_SC(base) & ~(mask)) | (value)))
+#define VREF_SET_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) |  (value)))
+#define VREF_CLR_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) & ~(value)))
+#define VREF_TOG_SC(base, value) (VREF_WR_SC(base, VREF_RD_SC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual VREF_SC bitfields
+ */
+
+/*!
+ * @name Register VREF_SC, field MODE_LV[1:0] (RW)
+ *
+ * These bits select the buffer modes for the Voltage Reference module.
+ *
+ * Values:
+ * - 0b00 - Bandgap on only, for stabilization and startup
+ * - 0b01 - High power buffer mode enabled
+ * - 0b10 - Low-power buffer mode enabled
+ * - 0b11 - Reserved
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_MODE_LV field. */
+#define VREF_RD_SC_MODE_LV(base) ((VREF_SC_REG(base) & VREF_SC_MODE_LV_MASK) >> VREF_SC_MODE_LV_SHIFT)
+#define VREF_BRD_SC_MODE_LV(base) (VREF_RD_SC_MODE_LV(base))
+
+/*! @brief Set the MODE_LV field to a new value. */
+#define VREF_WR_SC_MODE_LV(base, value) (VREF_RMW_SC(base, VREF_SC_MODE_LV_MASK, VREF_SC_MODE_LV(value)))
+#define VREF_BWR_SC_MODE_LV(base, value) (VREF_WR_SC_MODE_LV(base, value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFST[2] (RO)
+ *
+ * This bit indicates that the bandgap reference within the Voltage Reference
+ * module has completed its startup and stabilization.
+ *
+ * Values:
+ * - 0b0 - The module is disabled or not stable.
+ * - 0b1 - The module is stable.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFST field. */
+#define VREF_RD_SC_VREFST(base) ((VREF_SC_REG(base) & VREF_SC_VREFST_MASK) >> VREF_SC_VREFST_SHIFT)
+#define VREF_BRD_SC_VREFST(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFST_SHIFT))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field ICOMPEN[5] (RW)
+ *
+ * This bit is set during factory trimming of the VREF voltage. This bit should
+ * be written to 1 to achieve the performance stated in the data sheet.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_ICOMPEN field. */
+#define VREF_RD_SC_ICOMPEN(base) ((VREF_SC_REG(base) & VREF_SC_ICOMPEN_MASK) >> VREF_SC_ICOMPEN_SHIFT)
+#define VREF_BRD_SC_ICOMPEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT))
+
+/*! @brief Set the ICOMPEN field to a new value. */
+#define VREF_WR_SC_ICOMPEN(base, value) (VREF_RMW_SC(base, VREF_SC_ICOMPEN_MASK, VREF_SC_ICOMPEN(value)))
+#define VREF_BWR_SC_ICOMPEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_ICOMPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field REGEN[6] (RW)
+ *
+ * This bit is used to enable the internal 1.75 V regulator to produce a
+ * constant internal voltage supply in order to reduce the sensitivity to external
+ * supply noise and variation. If it is desired to keep the regulator enabled in very
+ * low power modes, refer to the Chip Configuration details for a description on
+ * how this can be achieved. This bit is set during factory trimming of the VREF
+ * voltage. This bit should be written to 1 to achieve the performance stated in
+ * the data sheet.
+ *
+ * Values:
+ * - 0b0 - Internal 1.75 V regulator is disabled.
+ * - 0b1 - Internal 1.75 V regulator is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_REGEN field. */
+#define VREF_RD_SC_REGEN(base) ((VREF_SC_REG(base) & VREF_SC_REGEN_MASK) >> VREF_SC_REGEN_SHIFT)
+#define VREF_BRD_SC_REGEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT))
+
+/*! @brief Set the REGEN field to a new value. */
+#define VREF_WR_SC_REGEN(base, value) (VREF_RMW_SC(base, VREF_SC_REGEN_MASK, VREF_SC_REGEN(value)))
+#define VREF_BWR_SC_REGEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_REGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register VREF_SC, field VREFEN[7] (RW)
+ *
+ * This bit is used to enable the bandgap reference within the Voltage Reference
+ * module. After the VREF is enabled, turning off the clock to the VREF module
+ * via the corresponding clock gate register will not disable the VREF. VREF must
+ * be disabled via this VREFEN bit.
+ *
+ * Values:
+ * - 0b0 - The module is disabled.
+ * - 0b1 - The module is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the VREF_SC_VREFEN field. */
+#define VREF_RD_SC_VREFEN(base) ((VREF_SC_REG(base) & VREF_SC_VREFEN_MASK) >> VREF_SC_VREFEN_SHIFT)
+#define VREF_BRD_SC_VREFEN(base) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT))
+
+/*! @brief Set the VREFEN field to a new value. */
+#define VREF_WR_SC_VREFEN(base, value) (VREF_RMW_SC(base, VREF_SC_VREFEN_MASK, VREF_SC_VREFEN(value)))
+#define VREF_BWR_SC_VREFEN(base, value) (BITBAND_ACCESS8(&VREF_SC_REG(base), VREF_SC_VREFEN_SHIFT) = (value))
+/*@}*/
+
+/*
+ * MK64F12 WDOG
+ *
+ * Generation 2008 Watchdog Timer
+ *
+ * Registers defined in this header file:
+ * - WDOG_STCTRLH - Watchdog Status and Control Register High
+ * - WDOG_STCTRLL - Watchdog Status and Control Register Low
+ * - WDOG_TOVALH - Watchdog Time-out Value Register High
+ * - WDOG_TOVALL - Watchdog Time-out Value Register Low
+ * - WDOG_WINH - Watchdog Window Register High
+ * - WDOG_WINL - Watchdog Window Register Low
+ * - WDOG_REFRESH - Watchdog Refresh register
+ * - WDOG_UNLOCK - Watchdog Unlock register
+ * - WDOG_TMROUTH - Watchdog Timer Output Register High
+ * - WDOG_TMROUTL - Watchdog Timer Output Register Low
+ * - WDOG_RSTCNT - Watchdog Reset Count register
+ * - WDOG_PRESC - Watchdog Prescaler register
+ */
+
+#define WDOG_INSTANCE_COUNT (1U) /*!< Number of instances of the WDOG module. */
+#define WDOG_IDX (0U) /*!< Instance number for WDOG. */
+
+/*******************************************************************************
+ * WDOG_STCTRLH - Watchdog Status and Control Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
+ *
+ * Reset value: 0x01D3U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLH register
+ */
+/*@{*/
+#define WDOG_RD_STCTRLH(base)    (WDOG_STCTRLH_REG(base))
+#define WDOG_WR_STCTRLH(base, value) (WDOG_STCTRLH_REG(base) = (value))
+#define WDOG_RMW_STCTRLH(base, mask, value) (WDOG_WR_STCTRLH(base, (WDOG_RD_STCTRLH(base) & ~(mask)) | (value)))
+#define WDOG_SET_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) |  (value)))
+#define WDOG_CLR_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) & ~(value)))
+#define WDOG_TOG_STCTRLH(base, value) (WDOG_WR_STCTRLH(base, WDOG_RD_STCTRLH(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_STCTRLH bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
+ *
+ * Enables or disables the WDOG's operation. In the disabled state, the watchdog
+ * timer is kept in the reset state, but the other exception conditions can
+ * still trigger a reset/interrupt. A change in the value of this bit must be held
+ * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled.
+ * - 0b1 - WDOG is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. */
+#define WDOG_RD_STCTRLH_WDOGEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WDOGEN_MASK) >> WDOG_STCTRLH_WDOGEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WDOGEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WDOGEN_SHIFT))
+
+/*! @brief Set the WDOGEN field to a new value. */
+#define WDOG_WR_STCTRLH_WDOGEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WDOGEN_MASK, WDOG_STCTRLH_WDOGEN(value)))
+#define WDOG_BWR_STCTRLH_WDOGEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WDOGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
+ *
+ * Selects clock source for the WDOG timer and other internal timing operations.
+ *
+ * Values:
+ * - 0b0 - WDOG clock sourced from LPO .
+ * - 0b1 - WDOG clock sourced from alternate clock source.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. */
+#define WDOG_RD_STCTRLH_CLKSRC(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_CLKSRC_MASK) >> WDOG_STCTRLH_CLKSRC_SHIFT)
+#define WDOG_BRD_STCTRLH_CLKSRC(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_CLKSRC_SHIFT))
+
+/*! @brief Set the CLKSRC field to a new value. */
+#define WDOG_WR_STCTRLH_CLKSRC(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_CLKSRC_MASK, WDOG_STCTRLH_CLKSRC(value)))
+#define WDOG_BWR_STCTRLH_CLKSRC(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_CLKSRC_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
+ *
+ * Used to enable the debug breadcrumbs feature. A change in this bit is updated
+ * immediately, as opposed to updating after WCT.
+ *
+ * Values:
+ * - 0b0 - WDOG time-out generates reset only.
+ * - 0b1 - WDOG time-out initially generates an interrupt. After WCT, it
+ *     generates a reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. */
+#define WDOG_RD_STCTRLH_IRQRSTEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_IRQRSTEN_MASK) >> WDOG_STCTRLH_IRQRSTEN_SHIFT)
+#define WDOG_BRD_STCTRLH_IRQRSTEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_IRQRSTEN_SHIFT))
+
+/*! @brief Set the IRQRSTEN field to a new value. */
+#define WDOG_WR_STCTRLH_IRQRSTEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_IRQRSTEN_MASK, WDOG_STCTRLH_IRQRSTEN(value)))
+#define WDOG_BWR_STCTRLH_IRQRSTEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_IRQRSTEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
+ *
+ * Enables Windowing mode.
+ *
+ * Values:
+ * - 0b0 - Windowing mode is disabled.
+ * - 0b1 - Windowing mode is enabled.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WINEN field. */
+#define WDOG_RD_STCTRLH_WINEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WINEN_MASK) >> WDOG_STCTRLH_WINEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WINEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WINEN_SHIFT))
+
+/*! @brief Set the WINEN field to a new value. */
+#define WDOG_WR_STCTRLH_WINEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WINEN_MASK, WDOG_STCTRLH_WINEN(value)))
+#define WDOG_BWR_STCTRLH_WINEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WINEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
+ *
+ * Enables updates to watchdog write-once registers, after the reset-triggered
+ * initial configuration window (WCT) closes, through unlock sequence.
+ *
+ * Values:
+ * - 0b0 - No further updates allowed to WDOG write-once registers.
+ * - 0b1 - WDOG write-once registers can be unlocked for updating.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. */
+#define WDOG_RD_STCTRLH_ALLOWUPDATE(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_ALLOWUPDATE_MASK) >> WDOG_STCTRLH_ALLOWUPDATE_SHIFT)
+#define WDOG_BRD_STCTRLH_ALLOWUPDATE(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_ALLOWUPDATE_SHIFT))
+
+/*! @brief Set the ALLOWUPDATE field to a new value. */
+#define WDOG_WR_STCTRLH_ALLOWUPDATE(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_ALLOWUPDATE_MASK, WDOG_STCTRLH_ALLOWUPDATE(value)))
+#define WDOG_BWR_STCTRLH_ALLOWUPDATE(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_ALLOWUPDATE_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
+ *
+ * Enables or disables WDOG in Debug mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Debug mode.
+ * - 0b1 - WDOG is enabled in CPU Debug mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_DBGEN field. */
+#define WDOG_RD_STCTRLH_DBGEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_DBGEN_MASK) >> WDOG_STCTRLH_DBGEN_SHIFT)
+#define WDOG_BRD_STCTRLH_DBGEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DBGEN_SHIFT))
+
+/*! @brief Set the DBGEN field to a new value. */
+#define WDOG_WR_STCTRLH_DBGEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_DBGEN_MASK, WDOG_STCTRLH_DBGEN(value)))
+#define WDOG_BWR_STCTRLH_DBGEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DBGEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
+ *
+ * Enables or disables WDOG in Stop mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Stop mode.
+ * - 0b1 - WDOG is enabled in CPU Stop mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_STOPEN field. */
+#define WDOG_RD_STCTRLH_STOPEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_STOPEN_MASK) >> WDOG_STCTRLH_STOPEN_SHIFT)
+#define WDOG_BRD_STCTRLH_STOPEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_STOPEN_SHIFT))
+
+/*! @brief Set the STOPEN field to a new value. */
+#define WDOG_WR_STCTRLH_STOPEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_STOPEN_MASK, WDOG_STCTRLH_STOPEN(value)))
+#define WDOG_BWR_STCTRLH_STOPEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_STOPEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
+ *
+ * Enables or disables WDOG in Wait mode.
+ *
+ * Values:
+ * - 0b0 - WDOG is disabled in CPU Wait mode.
+ * - 0b1 - WDOG is enabled in CPU Wait mode.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_WAITEN field. */
+#define WDOG_RD_STCTRLH_WAITEN(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_WAITEN_MASK) >> WDOG_STCTRLH_WAITEN_SHIFT)
+#define WDOG_BRD_STCTRLH_WAITEN(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WAITEN_SHIFT))
+
+/*! @brief Set the WAITEN field to a new value. */
+#define WDOG_WR_STCTRLH_WAITEN(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_WAITEN_MASK, WDOG_STCTRLH_WAITEN(value)))
+#define WDOG_BWR_STCTRLH_WAITEN(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_WAITEN_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
+ *
+ * Puts the watchdog in the functional test mode. In this mode, the watchdog
+ * timer and the associated compare and reset generation logic is tested for correct
+ * operation. The clock for the timer is switched from the main watchdog clock
+ * to the fast clock input for watchdog functional test. The TESTSEL bit selects
+ * the test to be run.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. */
+#define WDOG_RD_STCTRLH_TESTWDOG(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_TESTWDOG_MASK) >> WDOG_STCTRLH_TESTWDOG_SHIFT)
+#define WDOG_BRD_STCTRLH_TESTWDOG(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTWDOG_SHIFT))
+
+/*! @brief Set the TESTWDOG field to a new value. */
+#define WDOG_WR_STCTRLH_TESTWDOG(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_TESTWDOG_MASK, WDOG_STCTRLH_TESTWDOG(value)))
+#define WDOG_BWR_STCTRLH_TESTWDOG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTWDOG_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
+ *
+ * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
+ * timer.
+ *
+ * Values:
+ * - 0b0 - Quick test. The timer runs in normal operation. You can load a small
+ *     time-out value to do a quick test.
+ * - 0b1 - Byte test. Puts the timer in the byte test mode where individual
+ *     bytes of the timer are enabled for operation and are compared for time-out
+ *     against the corresponding byte of the programmed time-out value. Select the
+ *     byte through BYTESEL[1:0] for testing.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. */
+#define WDOG_RD_STCTRLH_TESTSEL(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_TESTSEL_MASK) >> WDOG_STCTRLH_TESTSEL_SHIFT)
+#define WDOG_BRD_STCTRLH_TESTSEL(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTSEL_SHIFT))
+
+/*! @brief Set the TESTSEL field to a new value. */
+#define WDOG_WR_STCTRLH_TESTSEL(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_TESTSEL_MASK, WDOG_STCTRLH_TESTSEL(value)))
+#define WDOG_BWR_STCTRLH_TESTSEL(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_TESTSEL_SHIFT) = (value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
+ *
+ * This 2-bit field selects the byte to be tested when the watchdog is in the
+ * byte test mode.
+ *
+ * Values:
+ * - 0b00 - Byte 0 selected
+ * - 0b01 - Byte 1 selected
+ * - 0b10 - Byte 2 selected
+ * - 0b11 - Byte 3 selected
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. */
+#define WDOG_RD_STCTRLH_BYTESEL(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_BYTESEL_MASK) >> WDOG_STCTRLH_BYTESEL_SHIFT)
+#define WDOG_BRD_STCTRLH_BYTESEL(base) (WDOG_RD_STCTRLH_BYTESEL(base))
+
+/*! @brief Set the BYTESEL field to a new value. */
+#define WDOG_WR_STCTRLH_BYTESEL(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_BYTESEL_MASK, WDOG_STCTRLH_BYTESEL(value)))
+#define WDOG_BWR_STCTRLH_BYTESEL(base, value) (WDOG_WR_STCTRLH_BYTESEL(base, value))
+/*@}*/
+
+/*!
+ * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
+ *
+ * Allows the WDOG's functional test mode to be disabled permanently. After it
+ * is set, it can only be cleared by a reset. It cannot be unlocked for editing
+ * after it is set.
+ *
+ * Values:
+ * - 0b0 - WDOG functional test mode is not disabled.
+ * - 0b1 - WDOG functional test mode is disabled permanently until reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. */
+#define WDOG_RD_STCTRLH_DISTESTWDOG(base) ((WDOG_STCTRLH_REG(base) & WDOG_STCTRLH_DISTESTWDOG_MASK) >> WDOG_STCTRLH_DISTESTWDOG_SHIFT)
+#define WDOG_BRD_STCTRLH_DISTESTWDOG(base) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DISTESTWDOG_SHIFT))
+
+/*! @brief Set the DISTESTWDOG field to a new value. */
+#define WDOG_WR_STCTRLH_DISTESTWDOG(base, value) (WDOG_RMW_STCTRLH(base, WDOG_STCTRLH_DISTESTWDOG_MASK, WDOG_STCTRLH_DISTESTWDOG(value)))
+#define WDOG_BWR_STCTRLH_DISTESTWDOG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLH_REG(base), WDOG_STCTRLH_DISTESTWDOG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_STCTRLL - Watchdog Status and Control Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
+ *
+ * Reset value: 0x0001U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_STCTRLL register
+ */
+/*@{*/
+#define WDOG_RD_STCTRLL(base)    (WDOG_STCTRLL_REG(base))
+#define WDOG_WR_STCTRLL(base, value) (WDOG_STCTRLL_REG(base) = (value))
+#define WDOG_RMW_STCTRLL(base, mask, value) (WDOG_WR_STCTRLL(base, (WDOG_RD_STCTRLL(base) & ~(mask)) | (value)))
+#define WDOG_SET_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) |  (value)))
+#define WDOG_CLR_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) & ~(value)))
+#define WDOG_TOG_STCTRLL(base, value) (WDOG_WR_STCTRLL(base, WDOG_RD_STCTRLL(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_STCTRLL bitfields
+ */
+
+/*!
+ * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
+ *
+ * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
+ * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
+ * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
+ * bit. It also gets cleared on a system reset.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_STCTRLL_INTFLG field. */
+#define WDOG_RD_STCTRLL_INTFLG(base) ((WDOG_STCTRLL_REG(base) & WDOG_STCTRLL_INTFLG_MASK) >> WDOG_STCTRLL_INTFLG_SHIFT)
+#define WDOG_BRD_STCTRLL_INTFLG(base) (BITBAND_ACCESS16(&WDOG_STCTRLL_REG(base), WDOG_STCTRLL_INTFLG_SHIFT))
+
+/*! @brief Set the INTFLG field to a new value. */
+#define WDOG_WR_STCTRLL_INTFLG(base, value) (WDOG_RMW_STCTRLL(base, WDOG_STCTRLL_INTFLG_MASK, WDOG_STCTRLL_INTFLG(value)))
+#define WDOG_BWR_STCTRLL_INTFLG(base, value) (BITBAND_ACCESS16(&WDOG_STCTRLL_REG(base), WDOG_STCTRLL_INTFLG_SHIFT) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TOVALH - Watchdog Time-out Value Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
+ *
+ * Reset value: 0x004CU
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TOVALH register
+ */
+/*@{*/
+#define WDOG_RD_TOVALH(base)     (WDOG_TOVALH_REG(base))
+#define WDOG_WR_TOVALH(base, value) (WDOG_TOVALH_REG(base) = (value))
+#define WDOG_RMW_TOVALH(base, mask, value) (WDOG_WR_TOVALH(base, (WDOG_RD_TOVALH(base) & ~(mask)) | (value)))
+#define WDOG_SET_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) |  (value)))
+#define WDOG_CLR_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) & ~(value)))
+#define WDOG_TOG_TOVALH(base, value) (WDOG_WR_TOVALH(base, WDOG_RD_TOVALH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TOVALL - Watchdog Time-out Value Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
+ *
+ * Reset value: 0x4B4CU
+ *
+ * The time-out value of the watchdog must be set to a minimum of four watchdog
+ * clock cycles. This is to take into account the delay in new settings taking
+ * effect in the watchdog clock domain.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TOVALL register
+ */
+/*@{*/
+#define WDOG_RD_TOVALL(base)     (WDOG_TOVALL_REG(base))
+#define WDOG_WR_TOVALL(base, value) (WDOG_TOVALL_REG(base) = (value))
+#define WDOG_RMW_TOVALL(base, mask, value) (WDOG_WR_TOVALL(base, (WDOG_RD_TOVALL(base) & ~(mask)) | (value)))
+#define WDOG_SET_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) |  (value)))
+#define WDOG_CLR_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) & ~(value)))
+#define WDOG_TOG_TOVALL(base, value) (WDOG_WR_TOVALL(base, WDOG_RD_TOVALL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_WINH - Watchdog Window Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_WINH - Watchdog Window Register High (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_WINH register
+ */
+/*@{*/
+#define WDOG_RD_WINH(base)       (WDOG_WINH_REG(base))
+#define WDOG_WR_WINH(base, value) (WDOG_WINH_REG(base) = (value))
+#define WDOG_RMW_WINH(base, mask, value) (WDOG_WR_WINH(base, (WDOG_RD_WINH(base) & ~(mask)) | (value)))
+#define WDOG_SET_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) |  (value)))
+#define WDOG_CLR_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) & ~(value)))
+#define WDOG_TOG_WINH(base, value) (WDOG_WR_WINH(base, WDOG_RD_WINH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_WINL - Watchdog Window Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_WINL - Watchdog Window Register Low (RW)
+ *
+ * Reset value: 0x0010U
+ *
+ * You must set the Window Register value lower than the Time-out Value Register.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_WINL register
+ */
+/*@{*/
+#define WDOG_RD_WINL(base)       (WDOG_WINL_REG(base))
+#define WDOG_WR_WINL(base, value) (WDOG_WINL_REG(base) = (value))
+#define WDOG_RMW_WINL(base, mask, value) (WDOG_WR_WINL(base, (WDOG_RD_WINL(base) & ~(mask)) | (value)))
+#define WDOG_SET_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) |  (value)))
+#define WDOG_CLR_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) & ~(value)))
+#define WDOG_TOG_WINL(base, value) (WDOG_WR_WINL(base, WDOG_RD_WINL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_REFRESH - Watchdog Refresh register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_REFRESH - Watchdog Refresh register (RW)
+ *
+ * Reset value: 0xB480U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_REFRESH register
+ */
+/*@{*/
+#define WDOG_RD_REFRESH(base)    (WDOG_REFRESH_REG(base))
+#define WDOG_WR_REFRESH(base, value) (WDOG_REFRESH_REG(base) = (value))
+#define WDOG_RMW_REFRESH(base, mask, value) (WDOG_WR_REFRESH(base, (WDOG_RD_REFRESH(base) & ~(mask)) | (value)))
+#define WDOG_SET_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) |  (value)))
+#define WDOG_CLR_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) & ~(value)))
+#define WDOG_TOG_REFRESH(base, value) (WDOG_WR_REFRESH(base, WDOG_RD_REFRESH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_UNLOCK - Watchdog Unlock register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_UNLOCK - Watchdog Unlock register (RW)
+ *
+ * Reset value: 0xD928U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_UNLOCK register
+ */
+/*@{*/
+#define WDOG_RD_UNLOCK(base)     (WDOG_UNLOCK_REG(base))
+#define WDOG_WR_UNLOCK(base, value) (WDOG_UNLOCK_REG(base) = (value))
+#define WDOG_RMW_UNLOCK(base, mask, value) (WDOG_WR_UNLOCK(base, (WDOG_RD_UNLOCK(base) & ~(mask)) | (value)))
+#define WDOG_SET_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) |  (value)))
+#define WDOG_CLR_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) & ~(value)))
+#define WDOG_TOG_UNLOCK(base, value) (WDOG_WR_UNLOCK(base, WDOG_RD_UNLOCK(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TMROUTH - Watchdog Timer Output Register High
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTH register
+ */
+/*@{*/
+#define WDOG_RD_TMROUTH(base)    (WDOG_TMROUTH_REG(base))
+#define WDOG_WR_TMROUTH(base, value) (WDOG_TMROUTH_REG(base) = (value))
+#define WDOG_RMW_TMROUTH(base, mask, value) (WDOG_WR_TMROUTH(base, (WDOG_RD_TMROUTH(base) & ~(mask)) | (value)))
+#define WDOG_SET_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) |  (value)))
+#define WDOG_CLR_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) & ~(value)))
+#define WDOG_TOG_TMROUTH(base, value) (WDOG_WR_TMROUTH(base, WDOG_RD_TMROUTH(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_TMROUTL - Watchdog Timer Output Register Low
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
+ *
+ * Reset value: 0x0000U
+ *
+ * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
+ * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
+ * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
+ * the watchdog timer.
+ */
+/*!
+ * @name Constants and macros for entire WDOG_TMROUTL register
+ */
+/*@{*/
+#define WDOG_RD_TMROUTL(base)    (WDOG_TMROUTL_REG(base))
+#define WDOG_WR_TMROUTL(base, value) (WDOG_TMROUTL_REG(base) = (value))
+#define WDOG_RMW_TMROUTL(base, mask, value) (WDOG_WR_TMROUTL(base, (WDOG_RD_TMROUTL(base) & ~(mask)) | (value)))
+#define WDOG_SET_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) |  (value)))
+#define WDOG_CLR_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) & ~(value)))
+#define WDOG_TOG_TMROUTL(base, value) (WDOG_WR_TMROUTL(base, WDOG_RD_TMROUTL(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_RSTCNT - Watchdog Reset Count register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_RSTCNT - Watchdog Reset Count register (RW)
+ *
+ * Reset value: 0x0000U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_RSTCNT register
+ */
+/*@{*/
+#define WDOG_RD_RSTCNT(base)     (WDOG_RSTCNT_REG(base))
+#define WDOG_WR_RSTCNT(base, value) (WDOG_RSTCNT_REG(base) = (value))
+#define WDOG_RMW_RSTCNT(base, mask, value) (WDOG_WR_RSTCNT(base, (WDOG_RD_RSTCNT(base) & ~(mask)) | (value)))
+#define WDOG_SET_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) |  (value)))
+#define WDOG_CLR_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) & ~(value)))
+#define WDOG_TOG_RSTCNT(base, value) (WDOG_WR_RSTCNT(base, WDOG_RD_RSTCNT(base) ^  (value)))
+/*@}*/
+
+/*******************************************************************************
+ * WDOG_PRESC - Watchdog Prescaler register
+ ******************************************************************************/
+
+/*!
+ * @brief WDOG_PRESC - Watchdog Prescaler register (RW)
+ *
+ * Reset value: 0x0400U
+ */
+/*!
+ * @name Constants and macros for entire WDOG_PRESC register
+ */
+/*@{*/
+#define WDOG_RD_PRESC(base)      (WDOG_PRESC_REG(base))
+#define WDOG_WR_PRESC(base, value) (WDOG_PRESC_REG(base) = (value))
+#define WDOG_RMW_PRESC(base, mask, value) (WDOG_WR_PRESC(base, (WDOG_RD_PRESC(base) & ~(mask)) | (value)))
+#define WDOG_SET_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) |  (value)))
+#define WDOG_CLR_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) & ~(value)))
+#define WDOG_TOG_PRESC(base, value) (WDOG_WR_PRESC(base, WDOG_RD_PRESC(base) ^  (value)))
+/*@}*/
+
+/*
+ * Constants & macros for individual WDOG_PRESC bitfields
+ */
+
+/*!
+ * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
+ *
+ * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
+ * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
+ * 1) to provide the prescaled WDOG_CLK.
+ */
+/*@{*/
+/*! @brief Read current value of the WDOG_PRESC_PRESCVAL field. */
+#define WDOG_RD_PRESC_PRESCVAL(base) ((WDOG_PRESC_REG(base) & WDOG_PRESC_PRESCVAL_MASK) >> WDOG_PRESC_PRESCVAL_SHIFT)
+#define WDOG_BRD_PRESC_PRESCVAL(base) (WDOG_RD_PRESC_PRESCVAL(base))
+
+/*! @brief Set the PRESCVAL field to a new value. */
+#define WDOG_WR_PRESC_PRESCVAL(base, value) (WDOG_RMW_PRESC(base, WDOG_PRESC_PRESCVAL_MASK, WDOG_PRESC_PRESCVAL(value)))
+#define WDOG_BWR_PRESC_PRESCVAL(base, value) (WDOG_WR_PRESC_PRESCVAL(base, value))
+/*@}*/
+
+/* Instance numbers for core modules */
+#define JTAG_IDX (0) /*!< Instance number for JTAG. */
+#define TPIU_IDX (0) /*!< Instance number for TPIU. */
+#define SCB_IDX (0) /*!< Instance number for SCB. */
+#define CoreDebug_IDX (0) /*!< Instance number for CoreDebug. */
+
+#if defined(__IAR_SYSTEMS_ICC__)
+  /* Restore checking of "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)" */
+  #pragma diag_default=pm008
+#endif
+
+#endif /* __MK64F12_EXTENSION_H__ */
+/* EOF */
diff --git a/Workspace/UART/SDK/platform/devices/MK64F12/include/MK64F12_features.h b/Workspace/UART/SDK/platform/devices/MK64F12/include/MK64F12_features.h
new file mode 100644
index 0000000..9c826df
--- /dev/null
+++ b/Workspace/UART/SDK/platform/devices/MK64F12/include/MK64F12_features.h
@@ -0,0 +1,1901 @@
+/*
+** ###################################################################
+**     Version:             rev. 2.14, 2015-06-08
+**     Build:               b150715
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-01-30)
+**         Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.6 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.7 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.8 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.9 (2015-01-21)
+**         Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
+**     - rev. 2.10 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**     - rev. 2.11 (2015-05-19)
+**         FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
+**         Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
+**         Added features for PDB and PORT.
+**     - rev. 2.12 (2015-05-25)
+**         Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
+**     - rev. 2.13 (2015-05-27)
+**         Several USB features added.
+**     - rev. 2.14 (2015-06-08)
+**         FTM features BUS_CLOCK and FAST_CLOCK removed.
+**
+** ###################################################################
+*/
+
+#if !defined(__FSL_MK64F12_FEATURES_H__)
+#define __FSL_MK64F12_FEATURES_H__
+
+/* ADC16 module features */
+
+/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
+#define FSL_FEATURE_ADC16_HAS_PGA (0)
+/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
+/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
+#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
+/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
+#define FSL_FEATURE_ADC16_HAS_DMA (1)
+/* @brief Has differential mode (bitfield SC1x[DIFF]). */
+#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
+/* @brief Has FIFO (bit SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_HAS_FIFO (0)
+/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
+#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
+/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
+#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
+/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
+#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
+/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
+#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
+/* @brief Has HW averaging (bit SC3[AVGE]). */
+#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
+/* @brief Has offset correction (register OFS). */
+#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
+/* @brief Maximum ADC resolution. */
+#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
+/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
+#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
+
+/* FLEXCAN module features */
+
+/* @brief Message buffer size */
+#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16)
+/* @brief Has doze mode support (register bit field MCR[DOZE]). */
+#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
+/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
+#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
+/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
+/* @brief Has extended bit timing register (register CBT). */
+#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
+/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
+#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
+/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
+#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
+/* @brief Number of interrupt vectors. */
+#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
+
+/* CMP module features */
+
+/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
+#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
+/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
+#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
+/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
+#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
+/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
+#define FSL_FEATURE_CMP_HAS_DMA (1)
+/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
+#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
+/* @brief Has DAC Test function in CMP (register DACTEST). */
+#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
+
+/* SOC module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief ACMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_ACMP_COUNT (0)
+    /* @brief ADC16 availability on the SoC. */
+    #define FSL_FEATURE_SOC_ADC16_COUNT (2)
+    /* @brief AFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_AFE_COUNT (0)
+    /* @brief AIPS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AIPS_COUNT (2)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (0)
+    /* @brief AXBS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AXBS_COUNT (1)
+    /* @brief CADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CADC_COUNT (0)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief MMCAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
+    /* @brief CMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMP_COUNT (3)
+    /* @brief CMT availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMT_COUNT (1)
+    /* @brief CNC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CNC_COUNT (0)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief DAC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DAC_COUNT (2)
+    /* @brief DCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DCDC_COUNT (0)
+    /* @brief DDR availability on the SoC. */
+    #define FSL_FEATURE_SOC_DDR_COUNT (0)
+    /* @brief DMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMA_COUNT (0)
+    /* @brief DMAMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+    /* @brief DRY availability on the SoC. */
+    #define FSL_FEATURE_SOC_DRY_COUNT (0)
+    /* @brief DSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_DSPI_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EMVSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+    /* @brief ENC availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENC_COUNT (0)
+    /* @brief ENET availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENET_COUNT (1)
+    /* @brief EWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EWM_COUNT (1)
+    /* @brief FB availability on the SoC. */
+    #define FSL_FEATURE_SOC_FB_COUNT (1)
+    /* @brief FGPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+    /* @brief FLEXIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FSKDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+    /* @brief FTFA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFA_COUNT (0)
+    /* @brief FTFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFE_COUNT (1)
+    /* @brief FTFL availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFL_COUNT (0)
+    /* @brief FTM availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTM_COUNT (4)
+    /* @brief FTMRA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+    /* @brief FTMRE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+    /* @brief FTMRH availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief HSADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_HSADC_COUNT (0)
+    /* @brief I2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2C_COUNT (3)
+    /* @brief I2S availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2S_COUNT (1)
+    /* @brief ICS availability on the SoC. */
+    #define FSL_FEATURE_SOC_ICS_COUNT (0)
+    /* @brief IRQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_IRQ_COUNT (0)
+    /* @brief KBI availability on the SoC. */
+    #define FSL_FEATURE_SOC_KBI_COUNT (0)
+    /* @brief SLCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_SLCD_COUNT (0)
+    /* @brief LCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LCDC_COUNT (0)
+    /* @brief LDO availability on the SoC. */
+    #define FSL_FEATURE_SOC_LDO_COUNT (0)
+    /* @brief LLWU availability on the SoC. */
+    #define FSL_FEATURE_SOC_LLWU_COUNT (1)
+    /* @brief LMEM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LMEM_COUNT (0)
+    /* @brief LPSCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPTPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (0)
+    /* @brief LTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LTC_COUNT (0)
+    /* @brief MC availability on the SoC. */
+    #define FSL_FEATURE_SOC_MC_COUNT (0)
+    /* @brief MCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCG_COUNT (1)
+    /* @brief MCGLITE availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+    /* @brief MCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCM_COUNT (1)
+    /* @brief MMAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMAU_COUNT (0)
+    /* @brief MMDVSQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+    /* @brief MPU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MPU_COUNT (1)
+    /* @brief MSCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+    /* @brief MTB availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTB_COUNT (0)
+    /* @brief MTBDWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
+    /* @brief NFC availability on the SoC. */
+    #define FSL_FEATURE_SOC_NFC_COUNT (0)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+    /* @brief OSC availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSC_COUNT (1)
+    /* @brief OTFAD availability on the SoC. */
+    #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+    /* @brief PDB availability on the SoC. */
+    #define FSL_FEATURE_SOC_PDB_COUNT (1)
+    /* @brief PGA availability on the SoC. */
+    #define FSL_FEATURE_SOC_PGA_COUNT (0)
+    /* @brief PIT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PIT_COUNT (1)
+    /* @brief PMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_PMC_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (0)
+    /* @brief PWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWT_COUNT (0)
+    /* @brief QuadSPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+    /* @brief RCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RCM_COUNT (1)
+    /* @brief RFSYS availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+    /* @brief RFVBAT availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+    /* @brief RNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNG_COUNT (1)
+    /* @brief RNGB availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNGB_COUNT (0)
+    /* @brief ROM availability on the SoC. */
+    #define FSL_FEATURE_SOC_ROM_COUNT (0)
+    /* @brief RSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RSIM_COUNT (0)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCI_COUNT (0)
+    /* @brief SDHC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDHC_COUNT (1)
+    /* @brief SDRAM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+    /* @brief SIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SIM_COUNT (1)
+    /* @brief SMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMC_COUNT (1)
+    /* @brief SPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPI_COUNT (0)
+    /* @brief TMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_TMR_COUNT (0)
+    /* @brief TPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_TPM_COUNT (0)
+    /* @brief TRIAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+    /* @brief TRNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRNG_COUNT (0)
+    /* @brief TSI availability on the SoC. */
+    #define FSL_FEATURE_SOC_TSI_COUNT (0)
+    /* @brief UART availability on the SoC. */
+    #define FSL_FEATURE_SOC_UART_COUNT (6)
+    /* @brief USB availability on the SoC. */
+    #define FSL_FEATURE_SOC_USB_COUNT (1)
+    /* @brief USBDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+    /* @brief USBHSDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+    /* @brief USBPHY availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+    /* @brief VREF availability on the SoC. */
+    #define FSL_FEATURE_SOC_VREF_COUNT (1)
+    /* @brief WDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_WDOG_COUNT (1)
+    /* @brief XBAR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XBAR_COUNT (0)
+    /* @brief XCVR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XCVR_COUNT (0)
+    /* @brief ZLL availability on the SoC. */
+    #define FSL_FEATURE_SOC_ZLL_COUNT (0)
+#elif defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12)
+    /* @brief ACMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_ACMP_COUNT (0)
+    /* @brief ADC16 availability on the SoC. */
+    #define FSL_FEATURE_SOC_ADC16_COUNT (2)
+    /* @brief AFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_AFE_COUNT (0)
+    /* @brief AIPS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AIPS_COUNT (2)
+    /* @brief AOI availability on the SoC. */
+    #define FSL_FEATURE_SOC_AOI_COUNT (0)
+    /* @brief AXBS availability on the SoC. */
+    #define FSL_FEATURE_SOC_AXBS_COUNT (1)
+    /* @brief CADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CADC_COUNT (0)
+    /* @brief FLEXCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
+    /* @brief MMCAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
+    /* @brief CMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMP_COUNT (3)
+    /* @brief CMT availability on the SoC. */
+    #define FSL_FEATURE_SOC_CMT_COUNT (1)
+    /* @brief CNC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CNC_COUNT (0)
+    /* @brief CRC availability on the SoC. */
+    #define FSL_FEATURE_SOC_CRC_COUNT (1)
+    /* @brief DAC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DAC_COUNT (1)
+    /* @brief DCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_DCDC_COUNT (0)
+    /* @brief DDR availability on the SoC. */
+    #define FSL_FEATURE_SOC_DDR_COUNT (0)
+    /* @brief DMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMA_COUNT (0)
+    /* @brief DMAMUX availability on the SoC. */
+    #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
+    /* @brief DRY availability on the SoC. */
+    #define FSL_FEATURE_SOC_DRY_COUNT (0)
+    /* @brief DSPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_DSPI_COUNT (3)
+    /* @brief EDMA availability on the SoC. */
+    #define FSL_FEATURE_SOC_EDMA_COUNT (1)
+    /* @brief EMVSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
+    /* @brief ENC availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENC_COUNT (0)
+    /* @brief ENET availability on the SoC. */
+    #define FSL_FEATURE_SOC_ENET_COUNT (1)
+    /* @brief EWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_EWM_COUNT (1)
+    /* @brief FB availability on the SoC. */
+    #define FSL_FEATURE_SOC_FB_COUNT (1)
+    /* @brief FGPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FGPIO_COUNT (0)
+    /* @brief FLEXIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
+    /* @brief FMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_FMC_COUNT (1)
+    /* @brief FSKDT availability on the SoC. */
+    #define FSL_FEATURE_SOC_FSKDT_COUNT (0)
+    /* @brief FTFA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFA_COUNT (0)
+    /* @brief FTFE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFE_COUNT (1)
+    /* @brief FTFL availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTFL_COUNT (0)
+    /* @brief FTM availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTM_COUNT (4)
+    /* @brief FTMRA availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRA_COUNT (0)
+    /* @brief FTMRE availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRE_COUNT (0)
+    /* @brief FTMRH availability on the SoC. */
+    #define FSL_FEATURE_SOC_FTMRH_COUNT (0)
+    /* @brief GPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_GPIO_COUNT (5)
+    /* @brief HSADC availability on the SoC. */
+    #define FSL_FEATURE_SOC_HSADC_COUNT (0)
+    /* @brief I2C availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2C_COUNT (3)
+    /* @brief I2S availability on the SoC. */
+    #define FSL_FEATURE_SOC_I2S_COUNT (1)
+    /* @brief ICS availability on the SoC. */
+    #define FSL_FEATURE_SOC_ICS_COUNT (0)
+    /* @brief IRQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_IRQ_COUNT (0)
+    /* @brief KBI availability on the SoC. */
+    #define FSL_FEATURE_SOC_KBI_COUNT (0)
+    /* @brief SLCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_SLCD_COUNT (0)
+    /* @brief LCDC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LCDC_COUNT (0)
+    /* @brief LDO availability on the SoC. */
+    #define FSL_FEATURE_SOC_LDO_COUNT (0)
+    /* @brief LLWU availability on the SoC. */
+    #define FSL_FEATURE_SOC_LLWU_COUNT (1)
+    /* @brief LMEM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LMEM_COUNT (0)
+    /* @brief LPSCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPSCI_COUNT (0)
+    /* @brief LPTMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
+    /* @brief LPTPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPTPM_COUNT (0)
+    /* @brief LPUART availability on the SoC. */
+    #define FSL_FEATURE_SOC_LPUART_COUNT (0)
+    /* @brief LTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_LTC_COUNT (0)
+    /* @brief MC availability on the SoC. */
+    #define FSL_FEATURE_SOC_MC_COUNT (0)
+    /* @brief MCG availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCG_COUNT (1)
+    /* @brief MCGLITE availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
+    /* @brief MCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_MCM_COUNT (1)
+    /* @brief MMAU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMAU_COUNT (0)
+    /* @brief MMDVSQ availability on the SoC. */
+    #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
+    /* @brief MPU availability on the SoC. */
+    #define FSL_FEATURE_SOC_MPU_COUNT (1)
+    /* @brief MSCAN availability on the SoC. */
+    #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
+    /* @brief MTB availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTB_COUNT (0)
+    /* @brief MTBDWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
+    /* @brief NFC availability on the SoC. */
+    #define FSL_FEATURE_SOC_NFC_COUNT (0)
+    /* @brief OPAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_OPAMP_COUNT (0)
+    /* @brief OSC availability on the SoC. */
+    #define FSL_FEATURE_SOC_OSC_COUNT (1)
+    /* @brief OTFAD availability on the SoC. */
+    #define FSL_FEATURE_SOC_OTFAD_COUNT (0)
+    /* @brief PDB availability on the SoC. */
+    #define FSL_FEATURE_SOC_PDB_COUNT (1)
+    /* @brief PGA availability on the SoC. */
+    #define FSL_FEATURE_SOC_PGA_COUNT (0)
+    /* @brief PIT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PIT_COUNT (1)
+    /* @brief PMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_PMC_COUNT (1)
+    /* @brief PORT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PORT_COUNT (5)
+    /* @brief PWM availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWM_COUNT (0)
+    /* @brief PWT availability on the SoC. */
+    #define FSL_FEATURE_SOC_PWT_COUNT (0)
+    /* @brief QuadSPIO availability on the SoC. */
+    #define FSL_FEATURE_SOC_QuadSPIO_COUNT (0)
+    /* @brief RCM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RCM_COUNT (1)
+    /* @brief RFSYS availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
+    /* @brief RFVBAT availability on the SoC. */
+    #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
+    /* @brief RNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNG_COUNT (1)
+    /* @brief RNGB availability on the SoC. */
+    #define FSL_FEATURE_SOC_RNGB_COUNT (0)
+    /* @brief ROM availability on the SoC. */
+    #define FSL_FEATURE_SOC_ROM_COUNT (0)
+    /* @brief RSIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_RSIM_COUNT (0)
+    /* @brief RTC availability on the SoC. */
+    #define FSL_FEATURE_SOC_RTC_COUNT (1)
+    /* @brief SCI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SCI_COUNT (0)
+    /* @brief SDHC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDHC_COUNT (1)
+    /* @brief SDRAM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SDRAM_COUNT (0)
+    /* @brief SIM availability on the SoC. */
+    #define FSL_FEATURE_SOC_SIM_COUNT (1)
+    /* @brief SMC availability on the SoC. */
+    #define FSL_FEATURE_SOC_SMC_COUNT (1)
+    /* @brief SPI availability on the SoC. */
+    #define FSL_FEATURE_SOC_SPI_COUNT (0)
+    /* @brief TMR availability on the SoC. */
+    #define FSL_FEATURE_SOC_TMR_COUNT (0)
+    /* @brief TPM availability on the SoC. */
+    #define FSL_FEATURE_SOC_TPM_COUNT (0)
+    /* @brief TRIAMP availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
+    /* @brief TRNG availability on the SoC. */
+    #define FSL_FEATURE_SOC_TRNG_COUNT (0)
+    /* @brief TSI availability on the SoC. */
+    #define FSL_FEATURE_SOC_TSI_COUNT (0)
+    /* @brief UART availability on the SoC. */
+    #define FSL_FEATURE_SOC_UART_COUNT (6)
+    /* @brief USB availability on the SoC. */
+    #define FSL_FEATURE_SOC_USB_COUNT (1)
+    /* @brief USBDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+    /* @brief USBHSDCD availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
+    /* @brief USBPHY availability on the SoC. */
+    #define FSL_FEATURE_SOC_USBPHY_COUNT (0)
+    /* @brief VREF availability on the SoC. */
+    #define FSL_FEATURE_SOC_VREF_COUNT (1)
+    /* @brief WDOG availability on the SoC. */
+    #define FSL_FEATURE_SOC_WDOG_COUNT (1)
+    /* @brief XBAR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XBAR_COUNT (0)
+    /* @brief XCVR availability on the SoC. */
+    #define FSL_FEATURE_SOC_XCVR_COUNT (0)
+    /* @brief ZLL availability on the SoC. */
+    #define FSL_FEATURE_SOC_ZLL_COUNT (0)
+#endif
+
+/* CRC module features */
+
+/* @brief Has data register with name CRC */
+#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
+
+/* DAC module features */
+
+/* @brief Define the size of hardware buffer */
+#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
+/* @brief Define whether the buffer supports watermark event detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
+/* @brief Define whether the buffer supports watermark selection detection or not. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
+/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
+/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
+/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
+#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
+/* @brief Define whether FIFO buffer mode is available or not. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
+/* @brief Define whether swing buffer mode is available or not.. */
+#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
+
+/* EDMA module features */
+
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (DMA_INSTANCE_COUNT * 16)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
+
+/* DMAMUX module features */
+
+/* @brief Number of DMA channels (related to number of register CHCFGn). */
+#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
+/* @brief Total number of DMA channels on all modules. */
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (DMAMUX_INSTANCE_COUNT * 16)
+/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
+#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
+
+/* ENET module features */
+
+/* @brief Has buffer descriptor byte swapping (register bit field ECR[DBSWP]). */
+#define FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY (0)
+/* @brief Has precision time protocol (IEEE 1588) support (register bit field ECR[EN1588], registers ATCR, ATVR, ATOFF, ATPER, ATCOR, ATINC, ATSTMP). */
+#define FSL_FEATURE_ENET_SUPPORT_PTP (1)
+/* @brief Number of associated interrupt vectors. */
+#define FSL_FEATURE_ENET_INTERRUPT_COUNT (4)
+/* @brief Errata 2597: No support for IEEE 1588 timestamp timer overflow interrupt. */
+#define FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT_ERRATA_2579 (0)
+/* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */
+#define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1)
+
+/* EWM module features */
+
+/* @brief Has clock prescaler (register CLKPRESCALER). */
+#define FSL_FEATURE_EWM_HAS_PRESCALER  (0)
+
+/* FLEXBUS module features */
+
+/* No feature definitions */
+
+/* FLASH module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (0)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (1)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (131072)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00020000)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0001C000)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00018000)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00010000)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00000000)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00020000)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+#elif defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief Is of type FTFA. */
+    #define FSL_FEATURE_FLASH_IS_FTFA (0)
+    /* @brief Is of type FTFE. */
+    #define FSL_FEATURE_FLASH_IS_FTFE (1)
+    /* @brief Is of type FTFL. */
+    #define FSL_FEATURE_FLASH_IS_FTFL (0)
+    /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
+    /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
+    /* @brief Has EEPROM region protection (register FEPROT). */
+    #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
+    /* @brief Has data flash region protection (register FDPROT). */
+    #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
+    /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
+    #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
+    /* @brief Has flash cache control in FMC module. */
+    #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
+    /* @brief Has flash cache control in MCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief P-Flash start address. */
+    #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
+    /* @brief P-Flash block count. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
+    /* @brief P-Flash block size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
+    /* @brief P-Flash sector size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
+    /* @brief P-Flash write unit size. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
+    /* @brief P-Flash data path width. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
+    /* @brief P-Flash block swap feature. */
+    #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
+    /* @brief Has FlexNVM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
+    /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
+    /* @brief FlexNVM block count. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
+    /* @brief FlexNVM block size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
+    /* @brief FlexNVM sector size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
+    /* @brief FlexNVM write unit size. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
+    /* @brief FlexNVM data path width. */
+    #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
+    /* @brief Has FlexRAM memory. */
+    #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
+    /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
+    /* @brief FlexRAM size. */
+    #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
+    /* @brief Has 0x00 Read 1s Block command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
+    /* @brief Has 0x01 Read 1s Section command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
+    /* @brief Has 0x02 Program Check command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
+    /* @brief Has 0x03 Read Resource command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
+    /* @brief Has 0x06 Program Longword command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
+    /* @brief Has 0x07 Program Phrase command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
+    /* @brief Has 0x08 Erase Flash Block command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
+    /* @brief Has 0x09 Erase Flash Sector command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
+    /* @brief Has 0x0B Program Section command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
+    /* @brief Has 0x40 Read 1s All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x41 Read Once command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
+    /* @brief Has 0x43 Program Once command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
+    /* @brief Has 0x44 Erase All Blocks command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
+    /* @brief Has 0x45 Verify Backdoor Access Key command. */
+    #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
+    /* @brief Has 0x46 Swap Control command. */
+    #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
+    /* @brief Has 0x80 Program Partition command. */
+    #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
+    /* @brief Has 0x81 Set FlexRAM Function command. */
+    #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
+    /* @brief P-Flash Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief P-Flash Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
+    /* @brief P-Flash Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
+    /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Erase sector command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Rrogram/Verify section command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Read resource command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM Program check command address alignment. */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
+    /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
+    /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
+    /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
+    /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
+    /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
+    /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
+    /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
+    /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
+    /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
+    /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
+    /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
+    /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
+    /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
+    /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
+    /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
+    /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
+    /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
+    /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
+    #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
+#endif
+
+/* FTM module features */
+
+/* @brief Number of channels. */
+#define FSL_FEATURE_FTM_CHANNEL_COUNT (8)
+#define FSL_FEATURE_FTM_CHANNEL_COUNTx { 8, 2, 2, 8 }
+/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
+#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+
+/* I2C module features */
+
+/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
+#define FSL_FEATURE_I2C_HAS_SMBUS (1)
+/* @brief Maximum supported baud rate in kilobit per second. */
+#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
+/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
+#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
+/* @brief Has DMA support (register bit C1[DMAEN]). */
+#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
+/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
+/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
+#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
+/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
+#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
+/* @brief Maximum width of the glitch filter in number of bus clocks. */
+#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
+/* @brief Has control of the drive capability of the I2C pins. */
+#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
+/* @brief Has double buffering support (register S2). */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
+
+/* SAI module features */
+
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+#define FSL_FEATURE_SAI_FIFO_COUNT (8)
+/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
+#define FSL_FEATURE_SAI_CHANNEL_COUNT (2)
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
+#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
+#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
+/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
+#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
+/* @brief Ihe interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
+
+/* LLWU module features */
+
+/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
+/* @brief Has pins 8-15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
+/* @brief Maximum number of internal modules connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
+/* @brief Number of digital filters. */
+#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
+/* @brief Has MF5 register. */
+#define FSL_FEATURE_LLWU_HAS_MF (0)
+/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
+#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1)
+/* @brief Has external pin 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
+/* @brief Has external pin 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
+/* @brief Has external pin 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
+/* @brief Has external pin 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
+/* @brief Has external pin 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
+/* @brief Has external pin 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
+/* @brief Has external pin 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
+/* @brief Has external pin 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
+/* @brief Has external pin 8 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
+/* @brief Has external pin 9 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
+/* @brief Has external pin 10 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
+/* @brief Has external pin 11 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
+/* @brief Has external pin 12 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
+/* @brief Has external pin 13 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
+/* @brief Has external pin 14 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
+/* @brief Has external pin 15 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
+/* @brief Has external pin 16 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
+/* @brief Has external pin 17 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
+/* @brief Has external pin 18 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
+/* @brief Has external pin 19 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
+/* @brief Has external pin 20 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
+/* @brief Has external pin 21 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
+/* @brief Has external pin 22 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
+/* @brief Has external pin 23 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
+/* @brief Has external pin 24 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
+/* @brief Has external pin 25 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
+/* @brief Has external pin 26 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
+/* @brief Has external pin 27 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
+/* @brief Has external pin 28 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
+/* @brief Has external pin 29 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
+/* @brief Has external pin 30 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
+/* @brief Has external pin 31 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
+/* @brief Index of port of external pin. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
+/* @brief Number of external pin port on specified port. */
+#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
+/* @brief Has internal module 0 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
+/* @brief Has internal module 1 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
+/* @brief Has internal module 2 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
+/* @brief Has internal module 3 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
+/* @brief Has internal module 4 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
+/* @brief Has internal module 5 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
+/* @brief Has internal module 6 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
+/* @brief Has internal module 7 connected to LLWU device. */
+#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
+
+/* LPTMR module features */
+
+/* @brief Has shared interrupt handler with another LPTMR module. */
+#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+
+/* MCG module features */
+
+/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
+/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
+#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
+/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
+#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
+/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
+/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
+#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
+/* @brief The PLL clock is divided by 2 before VCO divider. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
+/* @brief FRDIV supports 1280. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
+/* @brief FRDIV supports 1536. */
+#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
+#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
+/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
+#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
+/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_PLL1 (0)
+/* @brief Has 48MHz internal oscillator. */
+#define FSL_FEATURE_MCG_HAS_IRC_48M (1)
+/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
+#define FSL_FEATURE_MCG_HAS_OSC1 (0)
+/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
+#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
+/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
+#define FSL_FEATURE_MCG_HAS_LOLRE (1)
+/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
+#define FSL_FEATURE_MCG_USE_OSCSEL (1)
+/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
+#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
+/* @brief TBD */
+#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL (1)
+/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
+/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
+#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
+/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
+#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
+/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
+#define FSL_FEATURE_MCG_HAS_FLL (1)
+/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
+/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
+#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
+/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
+/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
+#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
+/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
+#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
+/* @brief Has external clock monitor (register bit C6[CME]). */
+#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
+/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
+#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
+/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
+#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
+/* @brief Has PEI mode or PBI mode. */
+#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
+/* @brief Reset clock mode is BLPI. */
+#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
+
+/* MPU module features */
+
+/* @brief Specifies number of descriptors available. */
+#define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12)
+/* @brief Has process identifier support. */
+#define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1)
+/* @brief Has master 0. */
+#define FSL_FEATURE_MPU_HAS_MASTER0 (1)
+/* @brief Has master 1. */
+#define FSL_FEATURE_MPU_HAS_MASTER1 (1)
+/* @brief Has master 2. */
+#define FSL_FEATURE_MPU_HAS_MASTER2 (1)
+/* @brief Has master 3. */
+#define FSL_FEATURE_MPU_HAS_MASTER3 (1)
+/* @brief Has master 4. */
+#define FSL_FEATURE_MPU_HAS_MASTER4 (1)
+/* @brief Has master 5. */
+#define FSL_FEATURE_MPU_HAS_MASTER5 (1)
+/* @brief Has master 6. */
+#define FSL_FEATURE_MPU_HAS_MASTER6 (0)
+/* @brief Has master 7. */
+#define FSL_FEATURE_MPU_HAS_MASTER7 (0)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
+
+/* OSC module features */
+
+/* @brief Has OSC1 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC1 (0)
+/* @brief Has OSC0 external oscillator. */
+#define FSL_FEATURE_OSC_HAS_OSC0 (0)
+/* @brief Has OSC external oscillator (without index). */
+#define FSL_FEATURE_OSC_HAS_OSC (1)
+/* @brief Number of OSC external oscillators. */
+#define FSL_FEATURE_OSC_OSC_COUNT (1)
+/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
+#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
+
+/* PDB module features */
+
+/* @brief Define the count of supporting ADC pre-trigger for each channel. */
+#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2)
+/* @brief Has DAC support. */
+#define FSL_FEATURE_PDB_HAS_DAC (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
+
+/* PIT module features */
+
+/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
+#define FSL_FEATURE_PIT_TIMER_COUNT (4)
+/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
+#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
+/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
+#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
+/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
+#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
+
+/* PMC module features */
+
+/* @brief Has Bandgap Enable In VLPx Operation support. */
+#define FSL_FEATURE_PMC_HAS_BGEN (1)
+/* @brief Has Bandgap Buffer Drive Select. */
+#define FSL_FEATURE_PMC_HAS_BGBDS (0)
+
+/* PORT module features */
+
+/* @brief Has control lock (register bit PCR[LK]). */
+#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
+/* @brief Has open drain control (register bit PCR[ODE]). */
+#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
+/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
+#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
+/* @brief Has DMA request (register bit field PCR[IRQC] values). */
+#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
+/* @brief Has pull resistor selection available. */
+#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
+/* @brief Has pull resistor enable (register bit PCR[PE]). */
+#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
+/* @brief Has slew rate control (register bit PCR[SRE]). */
+#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
+/* @brief Has passive filter (register bit field PCR[PFE]). */
+#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
+/* @brief Has drive strength control (register bit PCR[DSE]). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
+/* @brief Has separate drive strength register (HDRVE). */
+#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
+/* @brief Has glitch filter (register IOFLT). */
+#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
+/* @brief Defines width of PCR[MUX] field. */
+#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
+/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
+/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
+#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
+
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR (1)
+
+/* RCM module features */
+
+/* @brief Has Loss-of-Lock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOL (1)
+/* @brief Has Loss-of-Clock Reset support. */
+#define FSL_FEATURE_RCM_HAS_LOC (1)
+/* @brief Has JTAG generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_JTAG (1)
+/* @brief Has EzPort generated Reset support. */
+#define FSL_FEATURE_RCM_HAS_EZPORT (1)
+/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
+#define FSL_FEATURE_RCM_HAS_EZPMS (1)
+/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
+#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
+/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
+#define FSL_FEATURE_RCM_HAS_SSRS (0)
+
+/* RTC module features */
+
+#if defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \
+    defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12)
+    /* @brief Has wakeup pin (bit field CR[WPS]). */
+    #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+    /* @brief Has low power features (registers MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+    /* @brief Has read/write access control (registers WAR and RAR). */
+    #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+    /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_SECURITY (1)
+#elif defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
+    /* @brief Has wakeup pin (bit field CR[WPS]). */
+    #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
+    /* @brief Has low power features (registers MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
+    /* @brief Has read/write access control (registers WAR and RAR). */
+    #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
+    /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
+    #define FSL_FEATURE_RTC_HAS_SECURITY (0)
+#endif
+
+/* SDHC module features */
+
+/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
+#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1)
+/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
+#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0)
+/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
+#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0)
+
+/* SIM module features */
+
+/* @brief Has USB FS divider. */
+#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
+/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
+#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
+/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
+/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
+/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
+/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
+#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
+/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
+/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
+/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
+/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
+/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
+/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
+/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
+/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
+#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
+/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
+#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
+/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
+#define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
+/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
+/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
+/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
+/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
+/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
+/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
+#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
+/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
+/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
+/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
+/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
+/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
+/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
+/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
+/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
+/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
+/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
+/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
+#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
+/* @brief Has FTM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
+/* @brief Number of FTM modules. */
+#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
+/* @brief Number of FTM triggers with selectable source. */
+#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
+/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
+/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
+/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
+/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
+/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
+/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
+/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
+/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
+/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
+/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
+#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
+/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
+/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
+#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
+/* @brief Has TPM module(s) configuration. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
+/* @brief The highest TPM module index. */
+#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
+/* @brief Has TPM module with index 0. */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
+/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
+/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
+/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
+/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
+/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
+/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
+/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
+/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
+/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
+#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
+/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
+/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
+/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
+/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
+/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1)
+/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1)
+/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
+/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
+/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
+/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
+/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
+/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
+/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
+/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
+/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
+/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
+#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
+/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
+#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
+/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
+/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
+/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
+/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
+#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
+/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
+/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
+/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
+/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
+/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
+/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
+/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
+/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
+#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
+/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
+/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
+/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
+/* @brief Has device die ID (register bit field SDID[DIEID]). */
+#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
+/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
+#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
+/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
+/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
+/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
+/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
+/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
+/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
+/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
+/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
+/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
+/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
+/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
+/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
+#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
+/* @brief Has miscellanious control register (register MCR). */
+#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
+/* @brief Has COP watchdog (registers COPC and SRVCOP). */
+#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
+/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
+#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
+/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
+#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
+
+/* SMC module features */
+
+/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
+#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
+/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
+#define FSL_FEATURE_SMC_HAS_LPOPO (0)
+/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
+#define FSL_FEATURE_SMC_HAS_PORPO (1)
+/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
+#define FSL_FEATURE_SMC_HAS_LPWUI (1)
+/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
+#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
+/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
+/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
+#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
+/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
+#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
+/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
+#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
+/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
+#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
+/* @brief Has stop submode 0(VLLS0). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
+/* @brief Has stop submode 2(VLLS2). */
+#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
+
+/* DSPI module features */
+
+/* @brief Receive/transmit FIFO size in number of items. */
+#define FSL_FEATURE_DSPI_FIFO_SIZE (4)
+#define FSL_FEATURE_DSPI_FIFO_SIZEx { 4, 1, 1 }
+/* @brief Maximum transfer data width in bits. */
+#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
+/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
+#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
+/* @brief Number of chip select pins. */
+#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
+/* @brief Has chip select strobe capability on the PCS5 pin. */
+#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
+/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
+/* @brief Has 16-bit data transfer support. */
+#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (0) : \
+    ((x) == 2 ? (0) : (-1))))
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
+
+/* UART module features */
+
+/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
+#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
+/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_HAS_FIFO (1)
+/* @brief Hardware flow control (RTS, CTS) is supported. */
+#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
+/* @brief Infrared (modulation) is supported. */
+#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
+/* @brief 2 bits long stop bit is available. */
+#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
+/* @brief Baud rate fine adjustment is available. */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
+/* @brief Baud rate oversampling is available. */
+#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
+/* @brief Peripheral type. */
+#define FSL_FEATURE_UART_IS_SCI (0)
+/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
+#define FSL_FEATURE_UART_FIFO_SIZE (8)
+/* @brief Maximal data width without parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
+/* @brief Maximal data width with parity bit. */
+#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
+/* @brief Supports two match addresses to filter incoming frames. */
+#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
+/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
+#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
+#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
+/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
+#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
+/* @brief Has improved smart card (ISO7816 protocol) support. */
+#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
+/* @brief Has local operation network (CEA709.1-B protocol) support. */
+#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
+/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
+#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
+/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
+#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
+/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
+#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
+/* @brief Has separate DMA RX and TX requests. */
+#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
+    ((x) == 0 ? (1) : \
+    ((x) == 1 ? (1) : \
+    ((x) == 2 ? (1) : \
+    ((x) == 3 ? (1) : \
+    ((x) == 4 ? (0) : \
+    ((x) == 5 ? (0) : (-1)))))))
+
+/* USB module features */
+
+/* @brief HOST mode enabled */
+#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
+/* @brief OTG mode enabled */
+#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
+/* @brief Has KEEP_ALIVE_CTRL register */
+#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
+/* @brief Has the Dynamic SOF threshold compare support */
+#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
+/* @brief Has the VBUS detect support */
+#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
+/* @brief Has the IRC48M module clock support */
+#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
+
+/* VREF module features */
+
+/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
+#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
+/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
+#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
+/* @brief Describes the set of SC[MODE_LV] bitfield values */
+#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
+/* @brief Module has also low reference (registers VREFL/VREFH) */
+#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
+
+/* WDOG module features */
+
+/* @brief Watchdog is available. */
+#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
+/* @brief Has Wait mode support. */
+#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
+
+#endif /* __FSL_MK64F12_FEATURES_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/Workspace/UART/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h b/Workspace/UART/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
new file mode 100644
index 0000000..0044bbf
--- /dev/null
+++ b/Workspace/UART/SDK/platform/devices/MK64F12/include/fsl_bitaccess.h
@@ -0,0 +1,111 @@
+/*
+** ###################################################################
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b150225
+**
+**     Abstract:
+**         Register bit field access macros.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**
+** ###################################################################
+*/
+
+#ifndef _FSL_BITACCESS_H
+#define _FSL_BITACCESS_H  1
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/**
+ * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+/**
+ * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uintptr_t)(Reg) - (uintptr_t)0x40000000u)) + (4u*((uintptr_t)(Bit))))))
+
+#endif /* _FSL_BITACCESS_H */
+
+/******************************************************************************/
diff --git a/Workspace/UART/SDK/platform/devices/fsl_device_registers.h b/Workspace/UART/SDK/platform/devices/fsl_device_registers.h
new file mode 100644
index 0000000..abeb4ac
--- /dev/null
+++ b/Workspace/UART/SDK/platform/devices/fsl_device_registers.h
@@ -0,0 +1,1083 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.0, 2014-05-15
+**     Build:               b141209
+**
+**     Abstract:
+**         Common include file for CMSIS register access layer headers.
+**
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2014-05-15)
+**         Customer release.
+**
+** ###################################################################
+*/
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || \
+    defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10))
+
+    #define K02F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK02F12810/include/MK02F12810.h"
+    /* Extension register definitions */
+    #include "MK02F12810/include/MK02F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK02F12810/include/MK02F12810_features.h"
+
+#elif (defined(CPU_MK10DN512VLK10) || defined(CPU_MK10DN512VLL10) || defined(CPU_MK10DX128VLQ10) || \
+    defined(CPU_MK10DX256VLQ10) || defined(CPU_MK10DN512VLQ10) || defined(CPU_MK10DN512VMC10) || \
+    defined(CPU_MK10DX128VMD10) || defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10))
+
+    #define K10D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK10D10/include/MK10D10.h"
+    /* Extension register definitions */
+    #include "MK10D10/include/MK10D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK10D10/include/MK10D10_features.h"
+
+#elif (defined(CPU_MK11DX128AVLK5) || defined(CPU_MK11DX256AVLK5) || defined(CPU_MK11DN512AVLK5) || \
+    defined(CPU_MK11DX128AVMC5) || defined(CPU_MK11DX256AVMC5) || defined(CPU_MK11DN512AVMC5))
+
+    #define K11DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK11DA5/include/MK11DA5.h"
+    /* Extension register definitions */
+    #include "MK11DA5/include/MK11DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK11DA5/include/MK11DA5_features.h"
+
+#elif (defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DX256VLK10) || defined(CPU_MK20DN512VLL10) || \
+    defined(CPU_MK20DX256VLL10) || defined(CPU_MK20DX128VLQ10) || defined(CPU_MK20DX256VLQ10) || \
+    defined(CPU_MK20DN512VLQ10) || defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || \
+    defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || defined(CPU_MK20DN512VMD10))
+
+    #define K20D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D10/include/MK20D10.h"
+    /* Extension register definitions */
+    #include "MK20D10/include/MK20D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D10/include/MK20D10_features.h"
+
+#elif (defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || \
+    defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \
+    defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \
+    defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
+    defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || \
+    defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \
+    defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || \
+    defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
+    defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \
+    defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5))
+
+    #define K20D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK20D5/include/MK20D5.h"
+    /* Extension register definitions */
+    #include "MK20D5/include/MK20D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK20D5/include/MK20D5_features.h"
+
+#elif (defined(CPU_MK21DX128AVLK5) || defined(CPU_MK21DX256AVLK5) || defined(CPU_MK21DN512AVLK5) || \
+    defined(CPU_MK21DX128AVMC5) || defined(CPU_MK21DX256AVMC5) || defined(CPU_MK21DN512AVMC5))
+
+    #define K21DA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21DA5/include/MK21DA5.h"
+    /* Extension register definitions */
+    #include "MK21DA5/include/MK21DA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21DA5/include/MK21DA5_features.h"
+
+#elif (defined(CPU_MK21FX512AVLQ12) || defined(CPU_MK21FN1M0AVLQ12) || defined(CPU_MK21FX512AVMC12) || \
+    defined(CPU_MK21FN1M0AVMC12) || defined(CPU_MK21FX512AVMD12) || defined(CPU_MK21FN1M0AVMD12))
+
+    #define K21FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK21FA12/include/MK21FA12.h"
+    /* Extension register definitions */
+    #include "MK21FA12/include/MK21FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK21FA12/include/MK21FA12_features.h"
+
+#elif (defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || \
+    defined(CPU_MK22FN128VMP10))
+
+    #define K22F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F12810/include/MK22F12810.h"
+    /* Extension register definitions */
+    #include "MK22F12810/include/MK22F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F12810/include/MK22F12810_features.h"
+
+#elif (defined(CPU_MK22FX512AVLH12) || defined(CPU_MK22FN1M0AVLH12) || defined(CPU_MK22FX512AVLK12) || \
+    defined(CPU_MK22FN1M0AVLK12) || defined(CPU_MK22FX512AVLL12) || defined(CPU_MK22FN1M0AVLL12) || \
+    defined(CPU_MK22FX512AVLQ12) || defined(CPU_MK22FN1M0AVLQ12) || defined(CPU_MK22FX512AVMC12) || \
+    defined(CPU_MK22FN1M0AVMC12) || defined(CPU_MK22FX512AVMD12) || defined(CPU_MK22FN1M0AVMD12))
+
+    #define K22FA12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22FA12/include/MK22FA12.h"
+    /* Extension register definitions */
+    #include "MK22FA12/include/MK22FA12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22FA12/include/MK22FA12_features.h"
+
+#elif (defined(CPU_MK22FN256CAH12) || defined(CPU_MK22FN128CAH12) || defined(CPU_MK22FN256VDC12) || \
+    defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12))
+
+    #define K22F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F25612/include/MK22F25612.h"
+    /* Extension register definitions */
+    #include "MK22F25612/include/MK22F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F25612/include/MK22F25612_features.h"
+
+#elif (defined(CPU_MK22FN512CAP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
+    defined(CPU_MK22FN512VLL12) || defined(CPU_MK22FN512VMP12))
+
+    #define K22F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK22F51212/include/MK22F51212.h"
+    /* Extension register definitions */
+    #include "MK22F51212/include/MK22F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK22F51212/include/MK22F51212_features.h"
+
+#elif (defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12))
+
+    #define K24F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F12/include/MK24F12.h"
+    /* Extension register definitions */
+    #include "MK24F12/include/MK24F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F12/include/MK24F12_features.h"
+
+#elif (defined(CPU_MK24FN256VDC12))
+
+    #define K24F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK24F25612/include/MK24F25612.h"
+    /* Extension register definitions */
+    #include "MK24F25612/include/MK24F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK24F25612/include/MK24F25612_features.h"
+
+#elif (defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VLQ18) || defined(CPU_MK26FN2M0VMD18) || \
+    defined(CPU_MK26FN2M0VMI18))
+
+    #define K26F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK26F18/include/MK26F18.h"
+    /* Extension register definitions */
+    #include "MK26F18/include/MK26F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK26F18/include/MK26F18_features.h"
+
+#elif (defined(CPU_MK30DN512VLK10) || defined(CPU_MK30DN512VLL10) || defined(CPU_MK30DX128VLQ10) || \
+    defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMC10) || \
+    defined(CPU_MK30DX128VMD10) || defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10))
+
+    #define K30D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK30D10/include/MK30D10.h"
+    /* Extension register definitions */
+    #include "MK30D10/include/MK30D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK30D10/include/MK30D10_features.h"
+
+#elif (defined(CPU_MK40DN512VLK10) || defined(CPU_MK40DN512VLL10) || defined(CPU_MK40DX128VLQ10) || \
+    defined(CPU_MK40DX256VLQ10) || defined(CPU_MK40DN512VLQ10) || defined(CPU_MK40DN512VMC10) || \
+    defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || defined(CPU_MK40DN512VMD10))
+
+    #define K40D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK40D10/include/MK40D10.h"
+    /* Extension register definitions */
+    #include "MK40D10/include/MK40D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK40D10/include/MK40D10_features.h"
+
+#elif (defined(CPU_MK50DX256CLL10) || defined(CPU_MK50DN512CLL10) || defined(CPU_MK50DN512CLQ10) || \
+    defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || defined(CPU_MK50DN512CMD10) || \
+    defined(CPU_MK50DX256CMD10) || defined(CPU_MK50DX256CLK10))
+
+    #define K50D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK50D10/include/MK50D10.h"
+    /* Extension register definitions */
+    #include "MK50D10/include/MK50D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK50D10/include/MK50D10_features.h"
+
+#elif (defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10) || defined(CPU_MK51DN256CLQ10) || \
+    defined(CPU_MK51DN512CLQ10) || defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || \
+    defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10) || defined(CPU_MK51DX256CLK10))
+
+    #define K51D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK51D10/include/MK51D10.h"
+    /* Extension register definitions */
+    #include "MK51D10/include/MK51D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK51D10/include/MK51D10_features.h"
+
+#elif (defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10))
+
+    #define K52D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK52D10/include/MK52D10.h"
+    /* Extension register definitions */
+    #include "MK52D10/include/MK52D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK52D10/include/MK52D10_features.h"
+
+#elif (defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || defined(CPU_MK53DN512CMD10) || \
+    defined(CPU_MK53DX256CMD10))
+
+    #define K53D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK53D10/include/MK53D10.h"
+    /* Extension register definitions */
+    #include "MK53D10/include/MK53D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK53D10/include/MK53D10_features.h"
+
+#elif (defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DN512VLL10) || \
+    defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DN512VLQ10) || \
+    defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || defined(CPU_MK60DN512VMC10) || \
+    defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10))
+
+    #define K60D10_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK60D10/include/MK60D10.h"
+    /* Extension register definitions */
+    #include "MK60D10/include/MK60D10_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK60D10/include/MK60D10_features.h"
+
+#elif (defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12))
+
+    #define K63F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK63F12/include/MK63F12.h"
+    /* Extension register definitions */
+    #include "MK63F12/include/MK63F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK63F12/include/MK63F12_features.h"
+
+#elif (defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \
+    defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
+    defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12))
+
+
+    #define K64F12_SERIES
+    /* CMSIS-style register definitions */
+    #include "MK64F12/include/MK64F12.h"
+    /* Extension register definitions */
+    #include "MK64F12/include/MK64F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK64F12/include/MK64F12_features.h"
+
+#elif (defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
+    defined(CPU_MK65FX1M0VMI18))
+
+    #define K65F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK65F18/include/MK65F18.h"
+    /* Extension register definitions */
+    #include "MK65F18/include/MK65F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK65F18/include/MK65F18_features.h"
+
+#elif (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
+    defined(CPU_MK66FX1M0VMD18))
+
+    #define K66F18_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK66F18/include/MK66F18.h"
+    /* Extension register definitions */
+    #include "MK66F18/include/MK66F18_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK66F18/include/MK66F18_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12))
+
+    #define K70F12_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F12/include/MK70F12.h"
+    /* Extension register definitions */
+    #include "MK70F12/include/MK70F12_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F12/include/MK70F12_features.h"
+
+#elif (defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15))
+
+    #define K70F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK70F15/include/MK70F15.h"
+    /* Extension register definitions */
+    #include "MK70F15/include/MK70F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK70F15/include/MK70F15_features.h"
+
+#elif (defined(CPU_MK80FN256CAx15) || defined(CPU_MK80FN256VDC15) || defined(CPU_MK80FN256VLL15) || \
+    defined(CPU_MK80FN256VLQ15))
+
+    #define K80F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK80F25615/include/MK80F25615.h"
+    /* Extension register definitions */
+    #include "MK80F25615/include/MK80F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK80F25615/include/MK80F25615_features.h"
+
+#elif (defined(CPU_MK81FN256CAx15) || defined(CPU_MK81FN256VDC15) || defined(CPU_MK81FN256VLL15) || \
+    defined(CPU_MK81FN256VLQ15))
+
+    #define K81F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK81F25615/include/MK81F25615.h"
+    /* Extension register definitions */
+    #include "MK81F25615/include/MK81F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK81F25615/include/MK81F25615_features.h"
+
+#elif (defined(CPU_MK82FN256CAx15) || defined(CPU_MK82FN256VDC15) || defined(CPU_MK82FN256VLL15) || \
+    defined(CPU_MK82FN256VLQ15))
+
+    #define K82F25615_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MK82F25615/include/MK82F25615.h"
+    /* Extension register definitions */
+    #include "MK82F25615/include/MK82F25615_extension.h"
+    /* CPU specific feature definitions */
+    #include "MK82F25615/include/MK82F25615_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC2) || defined(CPU_MKE02Z32VLC2) || defined(CPU_MKE02Z16VLC2) || \
+    defined(CPU_MKE02Z64VLD2) || defined(CPU_MKE02Z32VLD2) || defined(CPU_MKE02Z16VLD2) || \
+    defined(CPU_MKE02Z64VLH2) || defined(CPU_MKE02Z64VQH2) || defined(CPU_MKE02Z32VLH2) || \
+    defined(CPU_MKE02Z32VQH2))
+
+    #define KE02Z2_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z2/include/MKE02Z2.h"
+    /* Extension register definitions */
+    #include "MKE02Z2/include/MKE02Z2_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z2/include/MKE02Z2_features.h"
+
+#elif (defined(CPU_SKEAZN64MLC2) || defined(CPU_SKEAZN32MLC2) || defined(CPU_SKEAZN16MLC2) || \
+    defined(CPU_SKEAZN64MLD2) || defined(CPU_SKEAZN32MLD2) || defined(CPU_SKEAZN16MLD2) || \
+    defined(CPU_SKEAZN64MLH2) || defined(CPU_SKEAZN32MLH2))
+
+    #define SKEAZN642_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN642/include/SKEAZN642.h"
+    /* Extension register definitions */
+    #include "SKEAZN642/include/SKEAZN642_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN642/include/SKEAZN642_features.h"
+
+#elif (defined(CPU_MKE02Z64VLC4) || defined(CPU_MKE02Z32VLC4) || defined(CPU_MKE02Z16VLC4) || \
+    defined(CPU_MKE02Z64VLD4) || defined(CPU_MKE02Z32VLD4) || defined(CPU_MKE02Z16VLD4) || \
+    defined(CPU_MKE02Z64VLH4) || defined(CPU_MKE02Z64VQH4) || defined(CPU_MKE02Z32VLH4) || \
+    defined(CPU_MKE02Z32VQH4))
+
+    #define KE02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE02Z4/include/MKE02Z4.h"
+    /* Extension register definitions */
+    #include "MKE02Z4/include/MKE02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE02Z4/include/MKE02Z4_features.h"
+
+#elif (defined(CPU_MKE04Z128VLD4) || defined(CPU_MKE04Z64VLD4) || defined(CPU_MKE04Z128VLK4) || \
+    defined(CPU_MKE04Z64VLK4) || defined(CPU_MKE04Z128VQH4) || defined(CPU_MKE04Z64VQH4) || \
+    defined(CPU_MKE04Z128VLH4) || defined(CPU_MKE04Z64VLH4))
+
+    #define KE04Z1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284.h"
+    /* Extension register definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z1284/include/MKE04Z1284_features.h"
+
+#elif (defined(CPU_MKE04Z8VFK4) || defined(CPU_MKE04Z8VTG4) || defined(CPU_MKE04Z8VWJ4))
+
+    #define KE04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE04Z4/include/MKE04Z4.h"
+    /* Extension register definitions */
+    #include "MKE04Z4/include/MKE04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE04Z4/include/MKE04Z4_features.h"
+
+#elif (defined(CPU_SKEAZN8MFK) || defined(CPU_SKEAZN8MTG))
+
+    #define SKEAZN84_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZN84/include/SKEAZN84.h"
+    /* Extension register definitions */
+    #include "SKEAZN84/include/SKEAZN84_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZN84/include/SKEAZN84_features.h"
+
+#elif (defined(CPU_MKE06Z128VLD4) || defined(CPU_MKE06Z64VLD4) || defined(CPU_MKE06Z128VLK4) || \
+    defined(CPU_MKE06Z64VLK4) || defined(CPU_MKE06Z128VQH4) || defined(CPU_MKE06Z64VQH4) || \
+    defined(CPU_MKE06Z128VLH4) || defined(CPU_MKE06Z64VLH4))
+
+    #define KE06Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKE06Z4/include/MKE06Z4.h"
+    /* Extension register definitions */
+    #include "MKE06Z4/include/MKE06Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKE06Z4/include/MKE06Z4_features.h"
+
+#elif (defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \
+    defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || \
+    defined(CPU_MKL02Z16VFM4) || defined(CPU_MKL02Z32VFM4))
+
+    #define KL02Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL02Z4/include/MKL02Z4.h"
+    /* Extension register definitions */
+    #include "MKL02Z4/include/MKL02Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL02Z4/include/MKL02Z4_features.h"
+
+#elif (defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || \
+    defined(CPU_MKL03Z32VFG4) || defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || \
+    defined(CPU_MKL03Z32VFK4))
+
+    #define KL03Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL03Z4/include/MKL03Z4.h"
+    /* Extension register definitions */
+    #include "MKL03Z4/include/MKL03Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL03Z4/include/MKL03Z4_features.h"
+
+#elif (defined(CPU_MKL04Z8VFK4) || defined(CPU_MKL04Z16VFK4) || defined(CPU_MKL04Z32VFK4) || \
+    defined(CPU_MKL04Z8VLC4) || defined(CPU_MKL04Z16VLC4) || defined(CPU_MKL04Z32VLC4) || \
+    defined(CPU_MKL04Z8VFM4) || defined(CPU_MKL04Z16VFM4) || defined(CPU_MKL04Z32VFM4) || \
+    defined(CPU_MKL04Z16VLF4) || defined(CPU_MKL04Z32VLF4))
+
+    #define KL04Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL04Z4/include/MKL04Z4.h"
+    /* Extension register definitions */
+    #include "MKL04Z4/include/MKL04Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL04Z4/include/MKL04Z4_features.h"
+
+#elif (defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || \
+    defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
+    defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \
+    defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4))
+
+    #define KL05Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL05Z4/include/MKL05Z4.h"
+    /* Extension register definitions */
+    #include "MKL05Z4/include/MKL05Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL05Z4/include/MKL05Z4_features.h"
+
+#elif (defined(CPU_MKL13Z32VFM4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z32VFT4) || \
+    defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z32VLH4) || defined(CPU_MKL13Z64VLH4) || \
+    defined(CPU_MKL13Z32VLK4) || defined(CPU_MKL13Z64VLK4) || defined(CPU_MKL13Z32VMP4) || \
+    defined(CPU_MKL13Z64VMP4))
+
+    #define KL13Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL13Z644/include/MKL13Z644.h"
+    /* Extension register definitions */
+    #include "MKL13Z644/include/MKL13Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL13Z644/include/MKL13Z644_features.h"
+
+#elif (defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || defined(CPU_MKL14Z32VFT4) || \
+    defined(CPU_MKL14Z64VFT4) || defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || \
+    defined(CPU_MKL14Z32VLK4) || defined(CPU_MKL14Z64VLK4))
+
+    #define KL14Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL14Z4/include/MKL14Z4.h"
+    /* Extension register definitions */
+    #include "MKL14Z4/include/MKL14Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL14Z4/include/MKL14Z4_features.h"
+
+#elif (defined(CPU_MKL15Z128CAD4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || \
+    defined(CPU_MKL15Z128VFM4) || defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || \
+    defined(CPU_MKL15Z128VFT4) || defined(CPU_MKL15Z32VLH4) || defined(CPU_MKL15Z64VLH4) || \
+    defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || defined(CPU_MKL15Z64VLK4) || \
+    defined(CPU_MKL15Z128VLK4))
+
+    #define KL15Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL15Z4/include/MKL15Z4.h"
+    /* Extension register definitions */
+    #include "MKL15Z4/include/MKL15Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL15Z4/include/MKL15Z4_features.h"
+
+#elif (defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || \
+    defined(CPU_MKL16Z32VFT4) || defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || \
+    defined(CPU_MKL16Z32VLH4) || defined(CPU_MKL16Z64VLH4) || defined(CPU_MKL16Z128VLH4) || \
+    defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VMP4))
+
+    #define KL16Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL16Z4/include/MKL16Z4.h"
+    /* Extension register definitions */
+    #include "MKL16Z4/include/MKL16Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL16Z4/include/MKL16Z4_features.h"
+
+#elif (defined(CPU_MKL17Z128VFM4) || defined(CPU_MKL17Z256VFM4) || defined(CPU_MKL17Z128VFT4) || \
+    defined(CPU_MKL17Z256VFT4) || defined(CPU_MKL17Z128VLH4) || defined(CPU_MKL17Z256VLH4) || \
+    defined(CPU_MKL17Z128VMP4) || defined(CPU_MKL17Z256VMP4))
+
+    #define KL17Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z4/include/MKL17Z4.h"
+    /* Extension register definitions */
+    #include "MKL17Z4/include/MKL17Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z4/include/MKL17Z4_features.h"
+
+#elif (defined(CPU_MKL17Z32VDA4) || defined(CPU_MKL17Z64VDA4) || defined(CPU_MKL17Z32VFM4) || \
+    defined(CPU_MKL17Z64VFM4) || defined(CPU_MKL17Z32VFT4) || defined(CPU_MKL17Z64VFT4) || \
+    defined(CPU_MKL17Z32VLH4) || defined(CPU_MKL17Z64VLH4) || defined(CPU_MKL17Z32VMP4) || \
+    defined(CPU_MKL17Z64VMP4))
+
+    #define KL17Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL17Z644/include/MKL17Z644.h"
+    /* Extension register definitions */
+    #include "MKL17Z644/include/MKL17Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL17Z644/include/MKL17Z644_features.h"
+
+#elif (defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || defined(CPU_MKL24Z32VFT4) || \
+    defined(CPU_MKL24Z64VFT4) || defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || \
+    defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4))
+
+    #define KL24Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL24Z4/include/MKL24Z4.h"
+    /* Extension register definitions */
+    #include "MKL24Z4/include/MKL24Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL24Z4/include/MKL24Z4_features.h"
+
+#elif (defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
+    defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \
+    defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
+    defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4))
+
+    #define KL25Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL25Z4/include/MKL25Z4.h"
+    /* Extension register definitions */
+    #include "MKL25Z4/include/MKL25Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL25Z4/include/MKL25Z4_features.h"
+
+
+#elif (defined(CPU_MKL26Z128CAL4) || defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || \
+    defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || \
+    defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || \
+    defined(CPU_MKL26Z128VLH4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z128VLL4) || \
+    defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \
+    defined(CPU_MKL26Z256VMP4))
+
+    #define KL26Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL26Z4/include/MKL26Z4.h"
+    /* Extension register definitions */
+    #include "MKL26Z4/include/MKL26Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL26Z4/include/MKL26Z4_features.h"
+
+#elif (defined(CPU_MKL27Z128VFM4) || defined(CPU_MKL27Z256VFM4) || defined(CPU_MKL27Z128VFT4) || \
+    defined(CPU_MKL27Z256VFT4) || defined(CPU_MKL27Z128VLH4) || defined(CPU_MKL27Z256VLH4) || \
+    defined(CPU_MKL27Z128VMP4) || defined(CPU_MKL27Z256VMP4))
+
+    #define KL27Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z4/include/MKL27Z4.h"
+    /* Extension register definitions */
+    #include "MKL27Z4/include/MKL27Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z4/include/MKL27Z4_features.h"
+
+#elif (defined(CPU_MKL27Z32VDA4) || defined(CPU_MKL27Z64VDA4) || defined(CPU_MKL27Z32VFM4) || \
+    defined(CPU_MKL27Z64VFM4) || defined(CPU_MKL27Z32VFT4) || defined(CPU_MKL27Z64VFT4) || \
+    defined(CPU_MKL27Z32VLH4) || defined(CPU_MKL27Z64VLH4) || defined(CPU_MKL27Z32VMP4) || \
+    defined(CPU_MKL27Z64VMP4))
+
+    #define KL27Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL27Z644/include/MKL27Z644.h"
+    /* Extension register definitions */
+    #include "MKL27Z644/include/MKL27Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL27Z644/include/MKL27Z644_features.h"
+
+#elif (defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || \
+    defined(CPU_MKL33Z256VMP4))
+
+    #define KL33Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z4/include/MKL33Z4.h"
+    /* Extension register definitions */
+    #include "MKL33Z4/include/MKL33Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z4/include/MKL33Z4_features.h"
+
+#elif (defined(CPU_MKL33Z32VFT4) || defined(CPU_MKL33Z64VFT4) || defined(CPU_MKL33Z32VLH4) || \
+    defined(CPU_MKL33Z64VLH4) || defined(CPU_MKL33Z32VLK4) || defined(CPU_MKL33Z64VLK4) || \
+    defined(CPU_MKL33Z32VMP4) || defined(CPU_MKL33Z64VMP4))
+
+    #define KL33Z644_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL33Z644/include/MKL33Z644.h"
+    /* Extension register definitions */
+    #include "MKL33Z644/include/MKL33Z644_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL33Z644/include/MKL33Z644_features.h"
+
+#elif (defined(CPU_MKL34Z64VLH4) || defined(CPU_MKL34Z64VLL4))
+
+    #define KL34Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL34Z4/include/MKL34Z4.h"
+    /* Extension register definitions */
+    #include "MKL34Z4/include/MKL34Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL34Z4/include/MKL34Z4_features.h"
+
+#elif (defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || \
+    defined(CPU_MKL36Z64VLL4) || defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || \
+    defined(CPU_MKL36Z128VMC4) || defined(CPU_MKL36Z256VMC4) || defined(CPU_MKL36Z256VMP4))
+
+    #define KL36Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL36Z4/include/MKL36Z4.h"
+    /* Extension register definitions */
+    #include "MKL36Z4/include/MKL36Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL36Z4/include/MKL36Z4_features.h"
+
+#elif (defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z128VMP4) || \
+    defined(CPU_MKL43Z256VMP4))
+
+    #define KL43Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL43Z4/include/MKL43Z4.h"
+    /* Extension register definitions */
+    #include "MKL43Z4/include/MKL43Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL43Z4/include/MKL43Z4_features.h"
+
+#elif (defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
+    defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || \
+    defined(CPU_MKL46Z256VMP4))
+
+    #define KL46Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKL46Z4/include/MKL46Z4.h"
+    /* Extension register definitions */
+    #include "MKL46Z4/include/MKL46Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKL46Z4/include/MKL46Z4_features.h"
+
+#elif (defined(CPU_MKM14Z128AHH5) || defined(CPU_MKM14Z64AHH5))
+
+    #define KM14ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5.h"
+    /* Extension register definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM14ZA5/include/MKM14ZA5_features.h"
+
+#elif (defined(CPU_MKM33Z128ALH5) || defined(CPU_MKM33Z64ALH5) || defined(CPU_MKM33Z128ALL5) || \
+    defined(CPU_MKM33Z64ALL5))
+
+    #define KM33ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5.h"
+    /* Extension register definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM33ZA5/include/MKM33ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z128ALL5))
+
+    #define KM34ZA5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5.h"
+    /* Extension register definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34ZA5/include/MKM34ZA5_features.h"
+
+#elif (defined(CPU_MKM34Z256VLL7) || defined(CPU_MKM34Z256VLQ7))
+
+    #define KM34Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKM34Z7/include/MKM34Z7.h"
+    /* Extension register definitions */
+    #include "MKM34Z7/include/MKM34Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKM34Z7/include/MKM34Z7_features.h"
+
+#elif (defined(CPU_MKV10Z16VFM7) || defined(CPU_MKV10Z16VLC7) || defined(CPU_MKV10Z16VLF7) || \
+    defined(CPU_MKV10Z32VFM7) || defined(CPU_MKV10Z32VLC7) || defined(CPU_MKV10Z32VLF7))
+
+    #define KV10Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z7/include/MKV10Z7.h"
+    /* Extension register definitions */
+    #include "MKV10Z7/include/MKV10Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z7/include/MKV10Z7_features.h"
+
+#elif (defined(CPU_MKV10Z128VFM7) || defined(CPU_MKV10Z128VLC7) || defined(CPU_MKV10Z128VLF7) || \
+    defined(CPU_MKV10Z128VLH7) || defined(CPU_MKV10Z64VFM7) || defined(CPU_MKV10Z64VLC7) || \
+    defined(CPU_MKV10Z64VLF7) || defined(CPU_MKV10Z64VLH7))
+
+    #define KV10Z1287_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV10Z1287/include/MKV10Z1287.h"
+    /* Extension register definitions */
+    #include "MKV10Z1287/include/MKV10Z1287_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV10Z1287/include/MKV10Z1287_features.h"
+
+#elif (defined(CPU_MKV11Z128VFM7) || defined(CPU_MKV11Z128VLC7) || defined(CPU_MKV11Z128VLF7) || \
+    defined(CPU_MKV11Z128VLH7) || defined(CPU_MKV11Z64VFM7) || defined(CPU_MKV11Z64VLC7) || \
+    defined(CPU_MKV11Z64VLF7) || defined(CPU_MKV11Z64VLH7))
+
+    #define KV11Z7_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV11Z7/include/MKV11Z7.h"
+    /* Extension register definitions */
+    #include "MKV11Z7/include/MKV11Z7_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV11Z7/include/MKV11Z7_features.h"
+
+#elif (defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
+    defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10))
+
+    #define KV30F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV30F12810/include/MKV30F12810.h"
+    /* Extension register definitions */
+    #include "MKV30F12810/include/MKV30F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV30F12810/include/MKV30F12810_features.h"
+
+#elif (defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10))
+
+    #define KV31F12810_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F12810/include/MKV31F12810.h"
+    /* Extension register definitions */
+    #include "MKV31F12810/include/MKV31F12810_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F12810/include/MKV31F12810_features.h"
+
+#elif (defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12))
+
+    #define KV31F25612_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F25612/include/MKV31F25612.h"
+    /* Extension register definitions */
+    #include "MKV31F25612/include/MKV31F25612_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F25612/include/MKV31F25612_features.h"
+
+#elif (defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12))
+
+    #define KV31F51212_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV31F51212/include/MKV31F51212.h"
+    /* Extension register definitions */
+    #include "MKV31F51212/include/MKV31F51212_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV31F51212/include/MKV31F51212_features.h"
+
+#elif (defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || \
+    defined(CPU_MKV40F256VLL15) || defined(CPU_MKV40F64VLH15))
+
+    #define KV40F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV40F15/include/MKV40F15.h"
+    /* Extension register definitions */
+    #include "MKV40F15/include/MKV40F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV40F15/include/MKV40F15_features.h"
+
+#elif (defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15))
+
+    #define KV43F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV43F15/include/MKV43F15.h"
+    /* Extension register definitions */
+    #include "MKV43F15/include/MKV43F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV43F15/include/MKV43F15_features.h"
+
+#elif (defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15))
+
+    #define KV44F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV44F15/include/MKV44F15.h"
+    /* Extension register definitions */
+    #include "MKV44F15/include/MKV44F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV44F15/include/MKV44F15_features.h"
+
+#elif (defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || \
+    defined(CPU_MKV45F256VLL15))
+
+    #define KV45F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV45F15/include/MKV45F15.h"
+    /* Extension register definitions */
+    #include "MKV45F15/include/MKV45F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV45F15/include/MKV45F15_features.h"
+
+#elif (defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || \
+    defined(CPU_MKV46F256VLL15))
+
+    #define KV46F15_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKV46F15/include/MKV46F15.h"
+    /* Extension register definitions */
+    #include "MKV46F15/include/MKV46F15_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKV46F15/include/MKV46F15_features.h"
+
+#elif (defined(CPU_MKW01Z128CHN4))
+
+    #define KW01Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW01Z4/include/MKW01Z4.h"
+    /* Extension register definitions */
+    #include "MKW01Z4/include/MKW01Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW01Z4/include/MKW01Z4_features.h"
+
+#elif (defined(CPU_MKW20Z160VHT4))
+
+    #define KW20Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW20Z4/include/MKW20Z4.h"
+    /* Extension register definitions */
+    #include "MKW20Z4/include/MKW20Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW20Z4/include/MKW20Z4_features.h"
+
+#elif (defined(CPU_MKW21D256VHA5) || defined(CPU_MKW21D512VHA5))
+
+    #define KW21D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW21D5/include/MKW21D5.h"
+    /* Extension register definitions */
+    #include "MKW21D5/include/MKW21D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW21D5/include/MKW21D5_features.h"
+
+#elif (defined(CPU_MKW22D512VHA5))
+
+    #define KW22D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW22D5/include/MKW22D5.h"
+    /* Extension register definitions */
+    #include "MKW22D5/include/MKW22D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW22D5/include/MKW22D5_features.h"
+
+#elif (defined(CPU_MKW24D512VHA5))
+
+    #define KW24D5_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW24D5/include/MKW24D5.h"
+    /* Extension register definitions */
+    #include "MKW24D5/include/MKW24D5_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW24D5/include/MKW24D5_features.h"
+
+#elif (defined(CPU_MKW30Z160VHM4))
+
+    #define KW30Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW30Z4/include/MKW30Z4.h"
+    /* Extension register definitions */
+    #include "MKW30Z4/include/MKW30Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW30Z4/include/MKW30Z4_features.h"
+
+#elif (defined(CPU_MKW40Z160VHT4))
+
+    #define KW40Z4_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "MKW40Z4/include/MKW40Z4.h"
+    /* Extension register definitions */
+    #include "MKW40Z4/include/MKW40Z4_extension.h"
+    /* CPU specific feature definitions */
+    #include "MKW40Z4/include/MKW40Z4_features.h"
+
+#elif (defined(CPU_SKEAZ128MLH) || defined(CPU_SKEAZ64MLH) || defined(CPU_SKEAZ128MLK) || \
+    defined(CPU_SKEAZ64MLK))
+
+    #define SKEAZ1284_SERIES
+
+    /* CMSIS-style register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284.h"
+    /* Extension register definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_extension.h"
+    /* CPU specific feature definitions */
+    #include "SKEAZ1284/include/SKEAZ1284_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/Workspace/UART/Sources/main.c b/Workspace/UART/Sources/main.c
new file mode 100644
index 0000000..b6ad5a2
--- /dev/null
+++ b/Workspace/UART/Sources/main.c
@@ -0,0 +1,54 @@
+#include "MK64F12.h"
+
+uint8_t uart_getchar();
+void put(char *ptr_str);
+void uart_putchar(char ch);
+
+int main(void)
+{
+
+	uint16_t ubd;/*Variable to save the baud rate*/
+	uint8_t temp;
+	SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; /*Enable the UART clock*/
+	SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK; /*Enable the PORTB clock*/
+	PORTB_PCR16 |= PORT_PCR_MUX(3);
+	PORTB_PCR17 |= PORT_PCR_MUX(3);
+	UART0_C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK ); /*Disable Tx and Rx*/
+	UART0_C1 = 0; /*Dafault settings of the register*/
+	ubd = (uint16_t)((21000*1000)/(9600 * 16)); /* Calculate baud settings */
+	temp = UART0_BDH & ~(UART_BDH_SBR(0x1F));/*Save the value of UART0_BDH except SBR*/
+	UART0_BDH = temp | (((ubd& 0x1F00) >> 8));
+	UART0_BDL = (uint8_t)(ubd& UART_BDL_SBR_MASK);
+	UART0_C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK );/* Enable receiver and transmitter */
+	uint8_t ch;
+	put("\r\nSerialcode example\r\n"); /*Print the text*/
+	while(1)
+	{
+		ch= uart_getchar();
+		uart_putchar(ch);
+		//BLUE_TOGGLE;
+	}
+	return 0;
+}
+
+uint8_t uart_getchar()
+{
+	/* Wait until character has been received */
+	while (!(UART0_S1 & UART_S1_RDRF_MASK)); /* Return the 8-bit data from the receiver */
+	return UART0_D;
+}
+
+void uart_putchar(char ch)
+{
+	/* Wait until space is available in the FIFO */
+	while(!(UART0_S1 & UART_S1_TDRE_MASK));
+
+	/* Send the character */
+	UART0_D = (uint8_t)ch;
+}
+
+void put(char *ptr_str)
+{
+	while(*ptr_str)
+		uart_putchar(*ptr_str++);
+}